Intel®  Trust Domain Extensions - SEAM Loader
(SEAMLDR) Interface Specification
343755-003US
MARCH 2022ii Ref. # 343755-003Notices & Disclaimers
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names and brands may be claimed as the property of others.Ref. # 343755-003 iiiRevision History
Revision Description Date
343755-001 Initial release of document. September 2020
343755-002 Updated to include Intel persistent SEAMLDR details. May 2021
343755-003 Updated to include TD-Preserving support. March 2022Ref. # 343755-003 ivREVISION HISTORY
CHAPTER 1
SECURE ARBITRATION MODE (SEAM)
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-1
CHAPTER 2 
INTEL P-SEAMLDR MODULE LOAD AND UPDATE
2.1 CPU State Following NP-SEAMLDR ACM Execution  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .  3-2
2.2 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-3
CHAPTER 3 
SEAMLDR DATA STRUCTURES
3.1 SEAM_SIGSTRUCT: Intel® TDX Module Signature Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-1
3.2 SEAMLDR_PARAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-3
3.3 SEAMLDR_INFO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-4
3.4 SEAMLDR_SEAMINFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-4
CHAPTER 4 
P-SEAMLDR FUNCTIONS
4.1 SEAMLDR.INFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-1
4.2 SEAMLDR.INSTALL  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-1
4.3 SEAMLDR.SHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-44.4 SEAMLDR.SEAMINFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-4
4.5 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-54.6 Software Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-5Ref. # 343755-003 vTABLES
PAGE
2-1 CPU State After NP-SEAMLDR ACM Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
2-2 Error Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
2-3 NP-SEAMLDR Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-1 SEAM_SIGSTRUCT: Intel® TDX Module Signature Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3-2 SEAMLDR_PARAMS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-3 SEAMLDR_INFO Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-4 SEAMLDR_SEAMINFO Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
4-1 Settings to Initialize Intel® TDX Module Signature Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4-2 Error Codes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5Ref. # 343755-003 viFIGURES
PAGE
Figure 1-1. Intel® Trust Domain Extension Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Figure 1-2. SEAM Range Register Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Ref. # 343755-003 1-1SECURE ARBITRATION MODE (SEAM)
CHAPTER 1
1.1 OVERVIEW
Secure Arbitration Mode (SEAM)  is an extension to the Virtual Machines Extension (VMX) architecture to define 
a new, VMX root operation called SEAM VMX root and a new VMX non-root operation called SEAM VMX non-root. 
Collectively, the SEAM VMX root and SEAM VMX non- root execution modes are called operation in SEAM.
SEAM VMX root operation is designed to host a CPU-attested, software module called the Intel® Trust-Domain-
Extensions (Intel® TDX) module to manage virtual machine (VM) guests called Trust Domains (TD) . 
The Intel TDX module helps implement the functions to buil d, tear down, and start execution of TD VMs. The VMM 
is designed to provide the memory resources to build  the TD and schedule the TD executions using the API 
provided by the Intel TDX module. SEAM VMX root operation is designed to additionally host a CPU-attested, soft-
ware module called the Intel Persistent SEAM Loader  (Intel P-SEAMLDR) to load and update Intel TDX modules.
NOTE
Currently, the Intel TDX Module is the only SEAM module that the Intel P-SEAMLDR installs. In the 
future, the Intel P-SEAMLDR may support th e installation of other SEAM modules.
Virtual machines launched/resumed from SEAM VMX root operation are TDs, and VMs launched/resumed from 
legacy VMX root operation are legacy VMs. Intel TDX modules use the SEAM instruction set extensions to help 
protect the confidentiality and integrity of TD memory cont ents and CPU state from all other software, including the 
hosting Virtual Machine Monitor (VMM), unle ss explicitly shared by the TD itself.
Figure 1-1.  Intel® Trust Domain Extension ComponentsVM
VMMVMM Enforced Access Controls Intel® TDX Module Enforced Access Controls
SEAMCALLVM VM TD VM TD VM TD VM
SEAMRET
SEAM Range RegisterModule RangeIntel® TDX Module
Persistent SEAMLDR RangeIntel Persistent SEAMLDR ModuleSEAMCALL
SEAMRET1-2 Ref. # 343755-003SECURE ARBITRATION MODE (SEAM)
The Intel TDX module and the Intel P-SEAMLDR module, wh ich execute in SEAM VMX-root operation, execute out 
of the memory range defined by the SEAM range regist ers (SEAMRR). The reserved range of memory specified 
using SEAM range registers (SEAM range) is configured  by the platform owner and programmed by the BIOS.
The SEAM range is further partitioned into two sub-ranges by the processor:
•MODULE_RANGE
•P_SEAMLDR_RANGE

SEAMRET
The MODULE_RANGE is used by the Intel TDX module, whic h provides functions to build and manage TD VMs. The 
P_SEAMLDR_RANGE is used by the P-SEAMLDR module, whic h is used to measure, verify, and install Intel TDX 
modules into the MODULE_RANGE. By design, access to the P-SEAMLDR range is restricted to the P-SEAMLDR 
module only.
Intel provides an authenticated code module (ACM) called the Intel Non-Persistent SEAM Loader ( Intel NP-
SEAMLDR) to install an Intel P-SEAMLDR module , whose image is embedded within the NP-SEAMLDR ACM,  in the 
P_SEAMLDR_RANGE.
This is illustrated in Figure 1-2.
The NP-SEAMLDR ACM helps with the init ialization of the SEAM range, establishes the P-SEAMLDR range, sets up 
the SEAM transfer VMCS structure for transfers to the Intel P-SEAMLDR module, and loads the embedded Intel P-
SEAMLDR module's image into the P_SEAMLDR_RANGE.
The OS can launch the SEAMLDR ACM us ing the GETSEC[ENTERACCS] instruction if the SEAMRR range enable bit 
(bit 11) of the IA32_SEAMRR_PHYS_MASK MSR is 1.
The SVN of the NP-SEAMLDR ACM itself is reported in the IA32_SGX_SVN_STATUS MSR in bits 63:56. OS/VMMs 
that launch an ACM such as SINIT or NP-SEAMLDR ar e expected to read the IA32_SGX_SVN_STATUS MSR to 
determine whether the ACM can be launched or if a new ACM is needed. If either the Intel® Software Guard Exten-
sions (Intel® SGX) SVN of the ACM value in th e ACM's header is greater than or equal to  the value reported by the
IA32_SGX_SVN_STATUS MSR, or the lock bit in the IA32_ SGX_SVN_STATUS MSR is not set, then the OS/VMM can 
safely launch the NP-SEAMLDR ACM. Otherwise,  the OS/VMM would not launch that version of the ACM. It would 
obtain an updated version of the ACM either fr om the BIOS or from an external resource.
The NP-SEAMLDR ACM is designed to follow the steps below to load or update the Intel P-SEAMLDR module into the 
Persistent SEAMLDR range in SEAMRR:
1. Perform basic checks on current state of platform.2. Initialize the entire SEAM memory range.
3. Install the embedded Intel P-SEAMLDR module in the P-SEAMLDR memory range.
4. Set up data and stack regions for the Intel P-SEAMLDR module.Figure 1-2.  SEAM Range Register DetailsSEAMRR.BaseInstall Intel P-SEAMLDRNP-SEAMLDR (ACM)
P-SEAMLDR Image
Intel® TDX Module
(Installed by P-SEAMLDR)
Install Intel TDX Module
(At boot and at runtime) Intel P-SEAMLDR
(Installed by NP-SEAMLDR)
P_SEAMLDR_RR.BaseSEAMRR.Limit
P_SEAMLDR_RR.LimitMODULE_RANGE P_SEAMLDR_RANGERef. # 343755-003 1-3SECURE ARBITRATION MODE (SEAM)
5. Set up a single SEAM transfer VMCS. This VMCS is us ed by SEAMCALL instructions  when an Intel P-SEAMLDR 
module's API is called, and by the SEAMRET instru ction when the Intel P-SEAMLDR module API returns.
6. Update the load status of  the Intel P-SEAMLDR module.
7. Exit to OS using the GE TSEC[EXITAC] instruction.
The Intel P-SEAMLDR module aims to pr ovide interfaces to the VMM, invoked using the SEAMCALL instruction, to 
gain information about Intel TDX, install Intel TDX modu les, and shutdown itself. The installation interface  is 
designed to follow the steps below to load or up date an Intel TDX module into the MODULE_RANGE:
1. Verify input parameters, including the Intel TD X module's signature structure (SEAM_SIGSTRUCT).
2. Load the Intel TDX module image into the MODULE_R ANGE, measure it and verify the measurement matches 
with the signature structure.
3. Set up data regions,  stack regions , and page tables  for all logical processors.
4. Set up SEAM transfer VMCSs for all logical processors . These VMCSs are used by SEAMCALL instructions when 
an Intel TDX module's API is called,  and by the SEAMRET instruction when the Intel TDX module API returns.
5. Record the Intel TDX module identity into CPU measurement registers and update its load status.6. Return to VMM using the SEAMRET instruction.1-4 Ref. # 343755-003SECURE ARBITRATION MODE (SEAM)Ref. # 343755-003 3-1INTEL P-SEAMLDR MODULE LOAD AND UPDATE
CHAPTER 2
The OS/VMM loader is designed to perform the following actions to load or update a previously loaded Intel P-
SEAMLDR module:
1. Find the NP-SEAMLDR ACM image file and copy it to memory. The memory for the NP-SEAMLDR image must be 
contiguous, physical memory and must be below 4 GB.
2. Ensure that the NP-SEAMLDR ACM is compatible with  the platform using the same rules as other ACMs. 
However, NP- SEAMLDR does not have dependency on In tel® TXT-supported chipset and TPM. So, filtering by 
Chipset ID or TPM information tables is not required  (the NP-SEAMLDR ACM will have empty Chipset ID and 
TPM information tables). The steps to be performed are as follows:
— Step 1: Verify it is NP-SEAMLDR  ACM by evaluating module type.
— Step 2: Verify platform type match.— Step 3: Verify AC module and chipset production flags match.— Step 4: Match CPUID.FMS and PLATFORM_ID.
3. The NP-SEAMLDR ACM must be launched on a logical processor marked BSP (i.e., where IA32_APIC_BASE.BSP 
is 1). All other logical processors in the socket on which NP-SEAMLDR will be launched must be in the WAIT-
FOR-SIPI state. If they are not already in the WAIT-FOR-S IPI state (for example, coming out of reset), then the 
OS might need to send INIT IPIs to all other logical processors to place them in the WAIT-FOR-SIPI state.
4. The NP-SEAMLDR ACM also requires that the OS/VMM lo ader has invoked the shutdown function provided by 
the Intel P-SEAMLDR module (if it was previously  installed), and VMXOFF has been executed on the BSP logical 
processor in which NP-SEAMLDR is launched .
5. The OS/VMM loader should prepare to launch NP-SEAML DR ACM by setting up parameters for the NP-SEAMLDR 
in registers as follows:
— R9 = GDT base to be established when returning to the OS.
— R10 = RIP where control is transf erred when returning to the OS.
— R11 = CR3 value to be established when returning to the OS.
— R12 = IDTR base value to be established when returning to the OS.
— EBX = NP-SEAMLDR ACM physical address base.—E C X  =  N P - S E A M L D R  A C M  s i z e .
— EAX = 2, which is the leaf number for the ENTERACCS function of the GETSEC instruction.
6. The OS/VMM loader should launch NP-SEAMLDR ACM in IA 32e mode with either 4-level or 5-level paging mode.
7. The OS/VMM loader invokes GETSEC[ENT ERACCS] to launch the NP-SEAMLDR ACM.
8. Before exiting, the NP-SEAMLDR ACM restores launcher's GDTR, IDTR, and  CR3. Certain processor states are 
not restored on EXITAC, and the OS/VMM loader must re -establish such states when control returns from the 
NP-SEAMLDR.
9. The NP-SEAMLDR ACM returns completi on status in register R9. A value of 0 indicates that the P-SEAMLDR 
module has been successfully installed into P_SEAM LDR_RANGE, and can be invoked by the VMM using 
SEAMCALL instructions.
A TXT MLE that launches the NP-SEAMLDR ACM using ENTERACCS should be aware of following:
•The NP-SEAMLDR ACM does not close the TPM locality 2 or  the TXT private space if the platform is post-SENTER 
as indicated by LT.STS[0] == 0x01. An MLE that launch es the NP-SEAMLDR ACM shou ld be aware of this, and 
re-evaluate TPM locality 2 and TXT private space st atus following execution of the NP-SEAMLDR ACM. TPM 
Locality 3 is closed unconditionally.3-2 Ref. # 343755-003INTEL P-SEAMLDR MODULE LOAD AND UPDATE
•The GETSEC[ EXITAC ] function unconditionally unmasks SMI, INIT , and NMI signals. Such an MLE must launch 
NP-SEAMLDR ACM only after the MLE has enabled SMI (or there is no STM/PPAM, and so SMI are enabled by 
SINIT).
2.1 CPU STATE FOLLOWING NP-SEAMLDR ACM EXECUTION
Table 2-1 describes the intended CPU state after NP-SEAMLDR ACM execution.
Table 2-1.  CPU State After NP-SEAMLDR ACM Execution 
Register CPU State After EXITAC from NP-SEAMLDR
CR0 PE=1, PG=1, NE=1; other bits cleared.CR3 As provided by OS in R11 with PCD and PWT bits cleared .
CR4 PAE=1, SMXE=1; PGE and LA57 are unchanged  (as it was when NP-SEAMLDR was launched) ; 
other bits cleared.
RFLAGS Reset value (0x2).
IA32_EFER LME=1, LMA=1, NXE=1; other bits cleared.IA32_PAT Reset value (0x00070406_00070406).RIP As provided by OS in R10.RAX EXITAC leaf number (0x3).RBX As Provided by OS in R10.R9 Load status returned by NP-SEAMLDR: success (0x0) or error code.Other GPRs, including RSP 0x0CS Selector value bits 11:3 unchanged (as it was when NP-SEAMLDR was laun ched); selector bits 
15:12 and 2:0 cleared; base/limit denote flat segment.
DS Selector value bits  11:3 same as original ES (as ES was when NP-SEAMLDR was launched); 
selector bits 15:12 and 2:0 cleared; base/limit denote flat segment.
ES Selector value bits 11:3 unchanged (as it was when NP-SEAMLDR was laun ched); selector bits 
FS Selector value bits 11:3 unchanged (as it was when NP-SEAMLDR was laun ched); selector bits 
GS Selector value bits 11:3 unchanged (as it was when NP-SEAMLDR was laun ched); selector bits

GS Selector value bits 11:3 unchanged (as it was when NP-SEAMLDR was laun ched); selector bits 
SS Selector value bits 11:3 unchanged (as it was when NP-SEAMLDR was laun ched); selector bits 
GDTR Base = As provided by OS in R9; Limit unchanged.
IDTR Base = As provided by OS in R12; Limit unchanged.
DR7 0x400IA32_DEBUGCTL 0x0IA32_PERF_GLOBAL_CTRL 0x0IA32_PEBS_ENABLE 0x0IA32_RTIT_CTRL TraceEn = 0, other bits are unchanged.IA32_LBR_CTRL 0x0IA32_MISC_ENABLES 0x8 (only th ermal throttlin g is enabled)
Other registers (including MSRs, 
XCR0, XSAVES-able registers, DRs)UnchangedRef. # 343755-003 3-3INTEL P-SEAMLDR MODULE LOAD AND UPDATE
2.2 ERROR HANDLING
The NP-SEAMLDR ACM returns error codes in the form at 0x80000000_cccceeee, where the value cccc specifies the 
error class, and the value eeee specifies the error code within that class.
The error classes are described in Table 2-2.
The list of errors codes returned by the NP-SEAMLDR are described in Table 2-3.
If the class of error is ECPARAM or ECPLAT, these are usuall y indicative of BIOS or OS software errors. Retrying the 
load will likely not succeed, and thus these errors can be fatal to the load process.Table 2-2.  Error Classes
Error Class Error Class Name Description
0000 ECPARAM Parameter validation errors. These errors are usually indicative of errors in the 
software that invokes the NP-SEAMLDR ACM.
0001 ECPLAT Platform configuration errors. These are usually indicative of misconfiguration of the 
platform. This might be due to BIOS errors  or unsupported hardware configurations.
Table 2-3.  NP-SEAMLDR Error Codes
Error Code Error Name Description
0x8000 0000 0000 0001 EMODBUSY The P-SEAMLDR module has not been shut down.0x8000 0000 0000 0002 ELDINPROG Software attempted to invoke the NP-SEAMLDR ACM simultaneously 
on multiple logical processors.
0x8000 0000 0001 0000 EBADRANGE The SEAM range is not valid.0x8000 0000 0001 0001 EBADPLATF Unsu pported platform configuration.
0x8000 0000 0001 0002 ENOMEM The P-SEAMLDR module does not fit within the P_SEAMLDR_RANGE 
constraints.
0x8000 0000 0001 0003 EUNSPECERR Unspecified error.3-4 Ref. # 343755-003INTEL P-SEAMLDR MODULE LOAD AND UPDATERef. # 343755-003 3-1SEAMLDR DATA STRUCTURES
CHAPTER 3
3.1 SEAM_SIGSTRUCT: INTEL® TDX MODULE SIGNATURE STRUCTURE
Each Intel TDX module is accompanied by a signature st ructure, which provides metadata information about the 
module and allows verification.
All fields in the SEAM_SIGSTRUCT (e.g., MODULUS, SIGNATURE, etc.) are in little-endian form.
Table 3-1.  SEAM_SIGSTRUCT: Intel®  TDX Module Signature Structure
Field Name Offset Size Description Signed?
SIGNATURE STRUCTURE HEADER
HEADER_TYPE 0 4 Module type; must be 6. Generic FW. YHEADER_LENGTH 4 4 Header Length; must be 0xE1 (900 bytes).
The length includes the following:
• Header: 128 B
• MODULUS: 384 B
• EXPONENT: 4 B• SIGNATURE: 384 B
The bytes following this Header (offset 900 onwards) are 
the body of the signed module.Y
HEADER_VERSION 8 4 Structure Version 
Bits 31:16 - Major VersionBits 15:0 - Minor Version
Must be 0x00010000.Y
MODULE_TYPE 12 4 Module Type
Bits 30:0 must be 0.Bit 31: Debug/Production Signed
•0 :  P r o d u c t i o n
•1 :  D e b u gY
MODULE_VENDOR 16 4 Module Vendor
Must be 8086h (Intel module).Y
DATE 20 4 Build date: yyyymmdd format 
(yyyy: four-digit year, mm:  1 to 12, dd: 1 to 31)Y
SIZE 24 4 Size of entire module (i.e., SEAM_SIGSTRUCT) in DWORDS; 
must be 0x200.Y
KEY_SIZE 28 4 RSA public key size; must be 0x60. Y
MODULUS_SIZE 32 4 RSA public key modulus size; must be 0x60. YEXPONENT_SIZE 36 4 RSA public key exponent size; must be 1. YRESERVED 40 88 Must be 0x0. Y
MODULUS AND SIGNATURE
MODULUS 128 384 Module public key (3072 bits) represented as a byte 
string of length 384, with the most significant byte at 
offset 511, i.e., in little-endian format.N
EXPONENT 512 4 RSA exponent. Must be 2^16+1. N3-2 Ref. # 343755-003SEAMLDR DATA STRUCTURES
SIGNATURE 516 384 RSA signature represented as a byte string of length 384, 
with the most signific ant byte at offset 89 9, i.e., in little-
endian format. 
Signature hash covers (Heade r (128B) || Body) in that 
order.N
Intel TDX MODULE CONFIGURATION PARAMETERS (Body)
SEAMHASH 900 48 Intel TDX module SHA384 hash. YSEAMSVN 948 2 Intel TDX module SVN. YATTRIBUTES 950 8 TDX module attributes (non-Intel).
Must be 0x0.Y
RIP_OFFSET 958 4 Offset of Inte l TDX module entry point. Y
NUM_STACK_PAGES 962 1 Stack size per thre ad in units of (# of 4K pages), minus  1. Y
NUM_TLS_PAGES 963 1 TLS size per thread in units of (# of 4K pages), minus 1. Y
NUM_KEYHOLE_ PAGES 964 2 Keyhole pages in units of (# of 4K pages), minus  1. Y
NUM_GLOBAL_DATA_PAGES 966 2 Global data in units of (# of 4KB pages), minus 1.
This number does not include # of handoff data pages.Y
MAX_TDMRS 968 2 Max number of TDMRs.
0 = 64 TDMRs.
N > 0 = N TDMRs.Y
MAX_RESERVED_PER_TDMR 970 2 Max numb er of reserved areas per TDMR.
0 = 16 reserved areas.
N > 0 = N reserved areas.Y
PAMT_ENTRY_SIZE_4K 972 2 PAMT entry size for 4KB pages, in bytes.
0 = 16 bytes.N > 0 = N bytes.Y
PAMT_ENTRY_SIZE_2M 974 2 PAMT entry size for 2MB pages, in bytes.
0 = 16 bytes.
N > 0 = N bytes.Y
PAMT_ENTRY_SIZE_1G 976 2 PAMT entry size for 1GB pages, in bytes.
RESERVED 978 6 Must be 0. Y
MODULE_HV 984 2 The handoff version that this Intel TDX module natively 
supports.Y
MIN_UPDATE_HV 986 2 The minimum handoff version that this Intel TDX module 
NO_DOWNGRADE 988 1 A boolean flag that  indicates whethe r this Intel TDX 
module cannot be replaced by an Intel TDX module whose 
handoff version is smaller than MODULE_HV.
0 = Downgrade allowed.
1 = Downgrade disallowed.Y
RESERVED 989 1 Must be 0. Y
NUM_HANDOFF_PAGES 990 2 Handoff data size in units of (# of  4KB pages) - 1. YTable 3-1.  SEAM_SIGSTRUCT: Intel®  TDX Module Signature Structure
Field Name Offset Size Description Signed?Ref. # 343755-003 3-3SEAMLDR DATA STRUCTURES
3.2 SEAMLDR_PARAMS
The SEAMLDR_PARAMS structure is used by the VMM to provide the Intel P-SEAMLDR module with information 
about the Intel TDX module to load or update. The SEAMLDR_PARAMS structure contains a pointer to the 
SEAM_SIGSTRUCT structure that describes the Intel TDX module, a list of pointers to Intel TDX module image 
pages, and the requested update/load scenario.
A SEAMLDR_PARAMS structure with version = 0 is 4K by tes in size and formatted as described in Table 3-2.RESERVED 992 32 Must be 0. Y
CPUID_TABLE_SIZE 1024 4 Number of entries in CPUID table. Valid values are 0 
through 255. Setting to 0 matches all CPUs.Y
CPUID_TABLE 1028 1020 Table of supported CPU version numbers as returned by 
CPUID.1.EAX. Stepping number is ignored for the match.Y
Table 3-2.  SEAMLDR_PARAMS Structure
Field NameOffset 
(Bytes)Size 
(Bytes)Description
VERSION 0 4 Structure version; must be 0.
SCENARIO 4 4 Scenario for which SEAMLDR was invoked:
• 0: LOAD. Load Intel TDX module.
• 1: UPDATE. Update previously load ed Intel TDX module to the same 
or another Intel TDX module.
Other values are reserved.
SIGSTRUCT_PA 8 8 A 4-KByte aligned physical  address of the Intel TDX module’s 
SEAM_SIGSTRUCT.
RESERVED 16 104 Reserved; must be 0.NUM_MODULE_PAGES 120 8 Intel TDX mo dule size in number of 4-KByte pages. Valid range 1 to 
496 for version 0.
MOD_PAGES_PA_LIST 128 8 * 496 Array of 4-KByte aligne d physical addresses to the Intel TDX module’s 
executable pages.Table 3-1.  SEAM_SIGSTRUCT: Intel®  TDX Module Signature Structure
Field Name Offset Size Description Signed?3-4 Ref. # 343755-003SEAMLDR DATA STRUCTURES
3.3 SEAMLDR_INFO
This data structure is used to return SEAMLDR informatio n to the VMM. Some of the SEAMLDR_INFO fields describe 
the NP-SEAMLDR ACM that insta lled this P-SEAMDLR instance. 
A SEAMLDR_INFO structure with version = 0 is 256 byte s in size and formatted as described in Table 3-3.
3.4 SEAMLDR_SEAMINFO
This data structure is used to return SEAM system information to the VMM. 
A SEAMLDR_SEAMINFO structure with ve rsion = 0 is 2K bytes in size and formatted as described in Table 3-4.Table 3-3.  SEAMLDR_INFO Structure
Field Name Offset (Bytes ) Size (Bytes) Description
VERSION 0 4 Structure Version; returns 0.A T T R I B U T E S 44B i t m a p  o f  a t t r i b u t e s :
• Bit 31 - Production-worthy (0) or debug (1).
• Bits 30:0 - Reserved 0.
VENDOR_ID 8 4 Vendor ID: 
Value is fixed to 0x8086 (Intel P-SEAMLDR module).
BUILD_DATE 12 4 Build date, in yyyy.mm. dd BCD format (fro m NP-SEAMLDR ACM 
header).
BUILD_NUM 16 2 Build number.MINOR 18 2 Minor version number.MAJOR 20 2 Major version number.RESEREVED 22 2 Reserved 0.ACM_X2APICID 24 4 The X2APICID of the lo gical processor on which NP-SEAMLDR 
ACM was launched.
NUM_REMAINING_UPDATES 28 4 Number of remaining Intel TDX module updates.
SEAM_INFO 32 128 The SEAM information of the Intel TDX module  currently loaded 
in MODULE_RANGE (0 if no In tel TDX module is currently 
loaded).

header).
loaded).
The SEAMINFO structure provides information about the 
currently loaded Inte l TDX module. It's the lower 128 bytes of 
the TEE_TCB_INFO structure, as  defined in th e Intel® Trust 
Domain CPU Architectural Extensions Specification, Table 2-3.
SEAM_READY 160 1 A boolean flag that indica tes, when set to 0x1, that the Intel 
TDX module is ready for SEAMCALL.
SEAM_DEBUG 161 1 A boolean flag that in dicates, when set to 0x1, that a 
debuggable Intel TDX module (i.e., an Intel TDX module with 
SEAM_SIGSTRUCT.MODULE_TYPE[bit 31] = 1) can be loaded.
P_SEAMLDR_READY 162 1 A boolean flag that indi cates, when set to 0x 1, that the Intel P-
SEAMLDR module is ready for SEAMCALLs (always 0x1). 
RESEREVED 168 88 Reserved 0.Ref. # 343755-003 3-5SEAMLDR DATA STRUCTURES
Table 3-4.  SEAMLDR_SEAMINFO Structure
Field Name Offset (Bytes) Size (Bytes) Description
VERSION 0 8 Structure Version - Set to 0.TOT_NUM_LPS 8 4 Total number of logical processors in platform.TOT_NUM_SOCKETS 12 4 Total number of sockets in platform. For single socket platforms 
this will report 1. The maximum number of sockets supported is 
8.
SOCKET_CPUID_TABLE 16 32 A table of 8 family/model/stepping (FMS) values, as reported by 
CPUID leaf 1 in the EAX regi ster, from all sockets. If 
TOT_NUM_SOCKETS < 8, entries TOT_NUM_SOCKETS … 7 return 
0.
P_SEAMLDR_RANGE_BASE 48 8 Physical ba se address of P_SEAMLDR_RANGE.
P_SEAMLDR_RANGE_SIZE 56 8 Size of  P_SEAMLDR_RANGE, in bytes.
SKIP_SMRR2_CHECK 64 1 A boolean flag that indicates whether the Intel TDX module can 
skip checking of SMRR2.
TDX_AC 65 1 A boolean flag that indica tes whether TDX memory is protected 
by access control (AC) mechanism, without memory integrity.
RESERVED 66 62 Must be 0.CMR_0_BASE 128 8 A 4K-aligned physical base address of Convertible Memory 
Region 0 (CMR0).
CMR_0_SIZE 136 8 Size of CMR0, in  bytes (a multiple of 4K).
Size = 0 indicates that  CMR0 is not valid.
...CMR_31_BASE 624 8 A 4K-aligned physical base address of CMR31.CMR_31_SIZE 632 8 Size of CMR31, in bytes (a multiple of 4K).
Size = 0 indicates that  CMR31 is not valid.
RESERVED 640 1408 Must be 0.3-6 Ref. # 343755-003SEAMLDR DATA STRUCTURESRef. # 343755-003 4-1P-SEAMLDR FUNCTIONS
CHAPTER 4
The Intel P-SEAMLDR module provides several APIs fo r the VMM. The ABI can be invoked after the Intel P-
SEAMLDR module has been su ccessfully loaded by the NP-SEAMDLR AC M into the P_SEAMLD R_RANGE within the 
SEAM range, and until the Intel P-SEAMLDR module's shut down session ended, or a fatal SEAM shutdown event 
occurred. 
The Intel P-SEAMLDR module's ABI is in voked by executing the SEAMCALL instru ction with RAX bit 63 set to '1. A 
successful SEAMCALL invocation transi tions to the Intel P-SEAMLDR module unless another call to the Intel P-
SEAMLDR module is already in progress.
The Intel P-SEAMLDR module's ABI supports the following functions:
•Leaf 0 = SEAMDLR.INFO: Retrieve information about th e Intel P-SEAMLDR module and the current Intel TDX 
module.
•Leaf 1 = SEAMLDR.INSTALL: Load or update an Intel TDX module.
•Leaf 2 = SEAMLDR.SHUTDOWN: Shutdown the Intel P- SEAMLDR module in preparation for updating it.
•Leaf 3 = SEAMLDR.SEAMINFO: Get SEAM information.
If the input RAX contains an unsupported API index, th en the P-SEAMLDR module re turns an EBADPARAM error. 
4.1 SEAM LDR.INFO
This function allows the VMM to query about the st atus of the Intel P-SEAMLDR and Intel TDX modules.
Usage:
•Can be invoked on any logical processor.
Inputs:
•RAX = 0x80000000.00000000
•RCX = A 64-bit physical address of an output buffer of type SEAMLDR_INFO. This address must satisfy the 
following rules:
— No reserved bits.—N o  T D X - p r i v a t e  K e y  I D .
— No overlap with SEAM range defined by SEAMRR.
— Aligned to a 256-byte boundary.
Operation:
•Check input RCX.
•Fill the given buffer with SEAMLDR_INFO.
Outputs:
•RAX = Success (0), or one of the following error codes:
—E B A D P A R A M
•If the physical address in input RCX is illegal.
4.2 SEAM LDR.INSTALL
This function allows the VMM to install a new Intel TD X module into the MODULE_RAN GE within the SEAM range.4-2 Ref. # 343755-003P-SEAMLDR FUNCTIONS
Usage:
•The API should be called on all logical processors in the platform, serially. When invoked on the first logical 
processor, it starts the “installation session”. When invoked on the last logical processor, it loads or updates the MODULE_RANGE with the given Intel TDX mo dule, and ends the installation session.
•During the installation session, the old Intel TDX module, if any, cannot be invoked (i.e., SEAMCALL instructions 
with RAX bit 63 set to '0, return VMFailInvalid flags).
•The update session may end with one of the following outcomes:
—Success.  This outcome is indicated by  output RAX == 0. On success, the newly installed Intel TDX  module 
can be invoked.
—Recoverable Error.  This outcome is indicated by output RAX !=  0 and output RDX == 0. On a recoverable 
installation error, the old Intel TDX module can be invoked. This outcome is possible only in “update” 
scenarios.
—Non-Recoverable Error.  This outcome is indicated by output RAX != 0 and output RDX != 0. On a non-
recoverable installation error, the old Inte l TDX module, if any, cannot be invoked. 
Inputs:
•RAX = 0x80000000.00000001
•RCX = A 64-bit physical address of an input buffer of  type SEAMLDR_PARAMS. This address must satisfy the 
—N o  r e s e r v e d  b i t s .
—N o  T D X - p r i v a t e  K e y  I D .— No overlap with SEAM range.
— Aligned on 4K-byte boundary.
•Return a recoverable error if a shutdown session is already in progress or this API was already called in this 
logical processor in the current installation session .
•Start an installation session if an installation session is not yet in progress.
•If this is not the last logical processor on which this API was called, return success.
•Else // last logical processor in the installation session.
— Load or update the new Intel TDX module into the MO DULE_RANGE, according to the requested installation 
scenario (as specified in SEAMLDR_PARAMS.SCENA RIO). This is done in the following steps:
1. Check input SEAMLDR_PARAMS address (in RCX).
2. Read SEAMLDR_PARAMS (pointed by RC X) and check the structure's contents.
3. Read SEAM_SIGSTRUCT (pointed by SEAMLDR_PARAMS.SEAM_SIGSTRUCT_PA), check the 
structure's contents, and authenticate it.
4.If the installation scenario is “update”, check that the SEAMSVN of the new Intel TDX module is not less 
than the SEAMSVN of the old Intel TDX module.
5.On CPUs that support TD-Preserving module updates: check that the handoff data left by the old Intel 
TDX module in MODULE_RANGE is valid, and that its version matches with the handoff version that the new Intel TDX module can handle (as specified in the MODULE_HV, MIN_UPDATE_HV and NO_DOWN-
GRADE fields of SEAM_SIGSTRUCT).
6. Check that the new Intel TDX module fits within the MODULE_RANGE.
7. Clear the MODULE_RANGE (on CPUs that support TD-Preserving module updates, if the installation 
scenario is “update”, the handoff data pages are not cleared) .
a.Note: From this point, all failures are reported as unrecoverable.
8. Copy the new Intel TDX module's image pages ( pointed by  the SEAMLDR_PARAMS.MOD_PAG-
ES_PA_LIST array) into the MODULE_RANGE.Ref. # 343755-003 4-3P-SEAMLDR FUNCTIONS
9. Measure the image and verify it's equal to the expected measurement (in 
SEAM_SIGSTRUCT.MRSEAM).
10. Create mappings for the new Intel TDX module's code, data, and stacks.
11. Create transfer VMCSs for the new Intel TDX module.
12. Pass system information in a dedicated MODULE_RANGE page to the new Intel TDX module.13. Record the SEAMINFO of the new Intel TDX module.
14. End the installation session.
15. Return success.
— If any error was detected during the above process, then:
•End the installation session.
•If the error was detected before memo ry cleanup and the requested scenario was “update”, then return 
a recoverable error indication.
•Else return an unrecoverable error indication.
Outputs:
—E B A D P A R A M  
•The input RCX is illegal.
•Any TMP_PARAMS field is invalid.
•An “update” scenario was requested but ther e's no Intel TDX module in MODULE_RANGE.
—E U N S P E C E R R
•Unexpected error.
—E N O E N T R O P Y
•Random number could not be generated.
—E B A D C A L L
•Shutdown session started.
•This API already called on this logical processor.
•Too many updates.
—E B A D S I G
•SEAM_SIGSTRUCT field is invalid.
•Unknown public key in SEAM_SIGSTRUCT.
•The SEAM_SIGSTRUCT signature not authenticated.
•SEAM_SIGSTRUCT is debug-signed but SEAM_UNDER_DEBUG is 0.
•Attempt to update to a differe nt Intel TDX module vendor.
•Attempt to update to a smaller SEAM SVN.
—E N O M E M
•Module range doesn't suffice for the new module's code and data.
—E B A D H A S H
•Module's hash in SEAM_SIGSTRUCT doesn't matc h the actual hash of the new module's image.
—EBADHANDOFF

Outputs:
—E B A D C A L L
—E B A D S I G
—E N O M E M
—E B A D H A S H
•The old module's handoff data in MODULE_RANGE is no t valid, or is of a version that the new Intel TDX 
module cannot support.4-4 Ref. # 343755-003P-SEAMLDR FUNCTIONS
4.3 SEAM LDR.SHUTDOWN
This API allows the VMM to shut down the P-SEAMLDR mo dule, in order to update it (by launching another NP-
SEAMLDR ACM).
Usage:
•The API should be called on all logical processors in the platform, serially, such that the last logical processor on 
which this API is called is the same logical processo r on which the NP-SEAMLDR ACM that installed the P-
SEAMLDR module had been launched.
•When invoked on the first logical processor, it starts the “shutdown session”. When invoked on the last logical 
processor, the shutdown session ends and the P-SEAMLDR becomes non-executable.
•After the shutdown session starts , the old Intel TDX module, if any, cannot be invoked anymore .
Inputs:
•RAX = 0x80000000.00000002
•Start a shutdown session if a shutdown  session is not yet in progress.
•Check that this is the logical processor on which the NP-SEAMLDR ACM that installed P-SEAMLDR was launched.
•End the shutdown session and return success.
Outputs:
•Unspecified error.
—E B A D C A L L
•This logical processor is not the logical processor on which NP-SEAMLDR ACM was launched.
4.4 SEAMLDR.SEAMINFO
This function allows the VMM to query SEAM information.
Usage:
Inputs:
•RAX = 0x80000000.00000003
•RCX = A 64-bit physical address of an  output buffer of type SEAMLDR_SE AMINFO. This address must satisfy 
the following rules:
—No reserved bits.
—No TDX-private Key ID.
—No overlap with SEAM range defined by SEAMRR.
—Aligned to a 2K-byte boundary.
•Fill the given buffer with SEAMLDR_SEAMINFO.
Outputs:
—EBADPARAM
•If the physical address in input RCX is illegal.Ref. # 343755-003 4-5P-SEAMLDR FUNCTIONS
4.5 ERROR HANDLING
The Intel P-SEAMLDR module returns error codes in th e format 0x80000000_cccceeee, where the value cccc spec-
ifies the error class, and the value eeee specifies the error code within that class.
The error classes are described in Table 4-1.
The list of errors codes returned by the Intel P-SEAMLDR module ABI are described in Table 4-2.
4.6 SOFTWARE CONSIDERATIONS
The Intel P-SEAMLDR module's functions preserve the CPU register state, exce pt the RIP register, which is incre-
mented to point at the instruction that follows SEAMCALL.
Upon return from an Intel P-SEAMLDR mo dule's function, the VMX working pointer, if any, is invalidated. The VMM 
can restore its VMX working pointer using the VMPTRLD instruction.
The Intel P-SEAMLDR module's APIs are no t interruptible by external events (NMI, SMI, INIT, interrupts). In partic-
ular, calls to the SEAMLDR.INSTALL API on the last logical processor in the Intel TDX mo dule's installation session 
may be a lengthy operation.Table 4-1.  Settings to Initialize Intel® TDX Module Signature Structure
0002 ECIMG Module image verification errors. These are usually indicative of corruptions in the 
module image leadin g to errors like signature verification error etc.
0003 ECPROG Progress status.
Table 4-2.  Error Codes
Error Code Error Name Description0x8000 0000 0000 0000 EBADPARAM Bad input parameter.0x8000 0000 0000 0003 EBADCALL P-SEAMLDR has already been called on the LP.0x8000 0000 0000 0004 EBADHANDOFF Update failure due to invalid or unsupported handoff data.
0x8000 0000 0001 0002 ENOMEM The new SEAM module does not fit within the SEAM range 
0x8000 0000 0001 0003 EUNSPECERR Unspecified platform configuration error.0x8000 0000 0001 0004 EUNSUPCPU The new SEAM module cannot be loaded on one (or more) CPUs in the 
platform.
0x8000 0000 0002 0000 EBADSIG Bad SEAM module signature (malformed, or signature verification 
failed).
0x8000 0000 0002 0001 EBADHASH The Intel TDX module's image hash verification failed.0x8000 0000 0003 0000 EINTERRUPT The function was interrupted.0x8000 0000 0003 0001 ENOENTROPY Insufficient entropy for generating random numbers.4-6 Ref. # 343755-003P-SEAMLDR FUNCTIONSUniﬁed Extensible Firmware Interface
(UEFI) Speciﬁcation
Release 2.10
UEFI Forum, Inc.
Aug 29, 2022CONTENTS
1 Introduction 1
1.1 Principle of Inclusive Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 UEFI Driver Model Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Target Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 UEFI Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7 UEFI Driver Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.7.1 UEFI Driver Model Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.7.2 Legacy Option ROM Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.8 Migration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8.1 Legacy Operating System Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8.2 Supporting the UEFI Speciﬁcation on a Legacy Platform . . . . . . . . . . . . . . . . . . . 10
1.9 Conventions Used in this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.9.1 Data Structure Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.9.2 Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.9.3 Procedure Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.9.4 Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.9.5 Pseudo-Code Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9.6 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9.7 Number formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.9.7.1 Hexadecimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.9.7.2 Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.9.8 SI & Binary preﬁxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.9.9 Revision Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Overview 15
2.1 Boot Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.1 UEFI Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.2 UEFI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.3 UEFI OS Loaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.4 UEFI Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Firmware Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 UEFI Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2 Runtime Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Calling Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.2 IA-32 Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.2.1 Handoff State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.2.2 Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
i2.3.3 Intel®Itanium®-Based Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.3.1 Handoff State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.3.3.2 Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.4 x64 Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.4.1 Handoff State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.4.2 Detailed Calling Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.4.3 Enabling Paging or Alternate Translations in an Application . . . . . . . . . . . . . 30
2.3.5 AArch32 Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.5.1 Handoff State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.3.5.2 Enabling Paging or Alternate Translations in an Application . . . . . . . . . . . . . 33
2.3.5.3 Detailed Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3.6 AArch64 Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3.6.1 Memory types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.6.2 Handoff State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.6.3 Enabling Paging or Alternate Translations in an Application . . . . . . . . . . . . . 38
2.3.6.4 Detailed Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.3.7 RISC-V Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3.7.1 Handoff State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.3.7.2 Data Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.3.7.3 Detailed Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.3.8 LoongArch Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.3.8.1 Handoff Statue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3.8.2 Detailed Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.4 Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.5 UEFI Driver Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.5.1 Legacy Option ROM Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.1.1 32-bit/16-Bit Real Mode Binaries . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.1.2 Fixed Resources for Working with Option ROMs . . . . . . . . . . . . . . . . . . 53
2.5.1.3 Matching Option ROMs to their Devices . . . . . . . . . . . . . . . . . . . . . . . 53
2.5.1.4 Ties to PC-AT System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.5.1.5 Ambiguities in Speciﬁcation and WorkaroundsBorn of Experience . . . . . . . . . 54
2.5.2 Driver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.5.3 Host Bus Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.5.4 Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.5.5 Bus Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.5.6 Platform Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.5.7 Hot-Plug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.5.8 EFI Services Binding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.6 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.6.1 Required Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.6.2 Platform-Speciﬁc Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.6.3 Driver-Speciﬁc Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.6.4 Extensions to this Speciﬁcation Published Elsewhere . . . . . . . . . . . . . . . . . . . . . 67
2.6.5 Cryptographic Algorithm Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3 Boot Manager 69
3.1 Firmware Boot Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.1.1 Boot Manager Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.1.2 Load Option Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.1.3 Load Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.1.4 Boot Manager Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.1.5 Launching Boot#### Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.1.6 Launching Boot#### Load Options Using Hot Keys . . . . . . . . . . . . . . . . . . . . . . 74
3.1.7 Required System Preparation Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ii3.2 Boot Manager Policy Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.2.1 EFI_BOOT_MANAGER_POLICY_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 76
3.2.2 EFI_BOOT_MANAGER_POLICY_PROTOCOL.ConnectDevicePath() . . . . . . . . . . . 77
3.2.3 EFI_BOOT_MANAGER_POLICY_PROTOCOL.ConnectDeviceClass() . . . . . . . . . . 78
3.3 Globally Deﬁned Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.4 Boot Option Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.4.1 OS-Deﬁned Boot Option Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.4.2 Platform-Deﬁned Boot Option Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.4.3 Boot Option Variables Default Boot Behavior . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5 Boot Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5.1 Boot via the Simple File Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5.1.1 Removable Media Boot Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.5.2 Boot via the Load File Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.5.2.1 Network Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.5.2.2 Future Boot Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4 EFI System Table 88
4.1 UEFI Image Entry Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.1.1 EFI_IMAGE_ENTRY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.2 EFI Table Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.2.1 EFI_TABLE_HEADER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.3 EFI System Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.3.1 EFI_SYSTEM_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.4 EFI Boot Services Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.4.1 EFI_BOOT_SERVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.5 EFI Runtime Services Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.5.1 EFI_RUNTIME_SERVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.6 EFI Conﬁguration Table & Properties Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.6.1 EFI_CONFIGURATION_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.6.1.1 Industry Standard Conﬁguration Tables . . . . . . . . . . . . . . . . . . . . . . . . 98
4.6.1.2 JSON Conﬁguration Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.6.1.3 Devicetree Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.6.2 EFI_RT_PROPERTIES_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.6.3 EFI_PROPERTIES_TABLE (deprecated) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6.4 EFI_MEMORY_ATTRIBUTES_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6.5 EFI_CONFORMANCE_PROFILE_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.6.6 Other Conﬁguration Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.7 Image Entry Point Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.7.1 Image Entry Point Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.7.2 UEFI Driver Model Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.7.3 UEFI Driver Model Example (Unloadable) . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.7.4 EFI Driver Model Example (Multiple Instances) . . . . . . . . . . . . . . . . . . . . . . . . 108
5 GUID Partition Table (GPT) Disk Layout 110
5.1 GPT and MBR disk layout comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2 LBA 0 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.1 Legacy Master Boot Record (MBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.2 OS Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.2.3 Protective MBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.2.4 Partition Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3 GUID Partition Table (GPT) Disk Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.1 GPT overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.2 GPT Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.3.3 GPT Partition Entry Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
iii6 Block Translation Table (BTT) Layout 121
6.1 Block Translation Table (BTT) Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2 Block Translation Table (BTT) Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2.1 BTT Info Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2.2 BTT Map Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.3 BTT Flog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.4 BTT Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.2.5 NVDIMM Label Protocol Address Abstraction Guid . . . . . . . . . . . . . . . . . . . . . 127
6.3 BTT Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.1 BTT Arenas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.2 Atomicity of Data Blocks in an Arena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.3 Atomicity of BTT Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.4 Writing the Initial BTT layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.5 Validating BTT Arenas at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.6 Validating the Flog entries at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.7 Read Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.8 Write Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7 Services — Boot Services 134
7.1 Event, Timer, and Task Priority Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.1.1 EFI_BOOT_SERVICES.CreateEvent() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.1.2 EFI_BOOT_SERVICES.CreateEventEx() . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.1.3 EFI_BOOT_SERVICES.CloseEvent() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.1.4 EFI_BOOT_SERVICES.SignalEvent() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.1.5 EFI_BOOT_SERVICES.WaitForEvent() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.1.6 EFI_BOOT_SERVICES.CheckEvent() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.1.7 EFI_BOOT_SERVICES.SetTimer() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.1.8 EFI_BOOT_SERVICES.RaiseTPL() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.1.9 EFI_BOOT_SERVICES.RestoreTPL() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.2 Memory Allocation Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.2.1 EFI_BOOT_SERVICES.AllocatePages() . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.2.2 EFI_BOOT_SERVICES.FreePages() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.2.3 EFI_BOOT_SERVICES.GetMemoryMap() . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.2.4 EFI_BOOT_SERVICES.AllocatePool() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.2.5 EFI_BOOT_SERVICES.FreePool() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.3 Protocol Handler Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.3.1 Driver Model Boot Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.3.2 EFI_BOOT_SERVICES.InstallProtocolInterface() . . . . . . . . . . . . . . . . . . . . . . 162
7.3.3 EFI_BOOT_SERVICES.UninstallProtocolInterface() . . . . . . . . . . . . . . . . . . . . . 164
7.3.4 EFI_BOOT_SERVICES.ReinstallProtocolInterface() . . . . . . . . . . . . . . . . . . . . . 165
7.3.5 EFI_BOOT_SERVICES.RegisterProtocolNotify() . . . . . . . . . . . . . . . . . . . . . . . 166
7.3.6 EFI_BOOT_SERVICES.LocateHandle() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.3.7 EFI_BOOT_SERVICES.HandleProtocol() . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
7.3.8 EFI_BOOT_SERVICES.LocateDevicePath() . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.3.9 EFI_BOOT_SERVICES.OpenProtocol() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.3.10 EFI_BOOT_SERVICES.CloseProtocol() . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.3.11 EFI_BOOT_SERVICES.OpenProtocolInformation() . . . . . . . . . . . . . . . . . . . . . 177
7.3.12 EFI_BOOT_SERVICES.ConnectController() . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.3.13 EFI_BOOT_SERVICES.DisconnectController() . . . . . . . . . . . . . . . . . . . . . . . . 182
7.3.14 EFI_BOOT_SERVICES.ProtocolsPerHandle() . . . . . . . . . . . . . . . . . . . . . . . . 184
7.3.15 EFI_BOOT_SERVICES.LocateHandleBuffer() . . . . . . . . . . . . . . . . . . . . . . . . 185
7.3.16 EFI_BOOT_SERVICES.LocateProtocol() . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.3.17 EFI_BOOT_SERVICES.InstallMultipleProtocolInterfaces() . . . . . . . . . . . . . . . . . 188
7.3.18 EFI_BOOT_SERVICES.UninstallMultipleProtocolInterfaces() . . . . . . . . . . . . . . . . 189
iv7.4 Image Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.4.1 EFI_BOOT_SERVICES.LoadImage() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.4.2 EFI_BOOT_SERVICES.StartImage() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.4.3 EFI_BOOT_SERVICES.UnloadImage() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.4.4 EFI_IMAGE_ENTRY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.4.5 EFI_BOOT_SERVICES.Exit() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
7.4.6 EFI_BOOT_SERVICES.ExitBootServices() . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.5 Miscellaneous Boot Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.5.1 EFI_BOOT_SERVICES.SetWatchdogTimer() . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.5.2 EFI_BOOT_SERVICES.Stall() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.5.3 EFI_BOOT_SERVICES.CopyMem() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.5.4 EFI_BOOT_SERVICES.SetMem() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.5.5 EFI_BOOT_SERVICES.GetNextMonotonicCount() . . . . . . . . . . . . . . . . . . . . . 202
7.5.6 EFI_BOOT_SERVICES.InstallConﬁgurationTable() . . . . . . . . . . . . . . . . . . . . . 203
7.5.7 EFI_BOOT_SERVICES.CalculateCrc32() . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
8 Services — Runtime Services 205
8.1 Runtime Services Rules and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
8.1.1 Exception for Machine Check, INIT, and NMI . . . . . . . . . . . . . . . . . . . . . . . . . 207
8.2 Variable Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
8.2.1 GetVariable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.2.2 GetNextVariableName() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
8.2.3 SetVariable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
8.2.4 QueryVariableInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
8.2.5 Using the EFI_V ARIABLE_AUTHENTICATION_3 descriptor . . . . . . . . . . . . . . . 218

8.2.6 Using the EFI_V ARIABLE_AUTHENTICATION_2 descriptor . . . . . . . . . . . . . . . 220
8.2.7 Using the EFI_V ARIABLE_AUTHENTICATION descriptor . . . . . . . . . . . . . . . . . 223
8.2.8 Hardware Error Record Persistence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
8.2.8.1 Hardware Error Record Non-V olatile Store . . . . . . . . . . . . . . . . . . . . . . 224
8.2.8.2 Hardware Error Record Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
8.2.8.3 Common Platform Error Record Format . . . . . . . . . . . . . . . . . . . . . . . 224
8.3 Time Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.3.1 GetTime() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.3.2 SetTime() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.3.3 GetWakeupTime() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8.3.4 SetWakeupTime() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.4 Virtual Memory Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.4.1 SetVirtualAddressMap() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.4.2 ConvertPointer() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
8.5 Miscellaneous Runtime Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
8.5.1 Reset System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
8.5.1.1 ResetSystem() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
8.5.2 Get Next High Monotonic Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
8.5.2.1 GetNextHighMonotonicCount() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
8.5.3 Update Capsule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
8.5.3.1 UpdateCapsule() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
8.5.3.2 Capsule Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
8.5.3.3 EFI_MEMORY_RANGE_CAPSULE_GUID . . . . . . . . . . . . . . . . . . . . 240
8.5.3.4 QueryCapsuleCapabilities() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
8.5.4 Exchanging information between the OS and Firmware . . . . . . . . . . . . . . . . . . . . 242
8.5.5 Delivery of Capsules via ﬁle on Mass Storage Device . . . . . . . . . . . . . . . . . . . . . 243
8.5.6 UEFI variable reporting on the Success or any Errors encountered in processing of capsules
after restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
8.5.6.1 EFI_CAPSULE_REPORT_GUID . . . . . . . . . . . . . . . . . . . . . . . . . . 245
v9 Protocols - EFI Loaded Image 248
9.1 EFI Loaded Image Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
9.1.1 EFI_LOADED_IMAGE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
9.1.2 EFI_LOADED_IMAGE_PROTOCOL.Unload() . . . . . . . . . . . . . . . . . . . . . . . . 249
9.2 EFI Loaded Image Device Path Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
9.2.1 EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL . . . . . . . . . . . . . . . . . . . 250
10 Protocols – Device Path Protocol 251
10.1 Device Path Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10.2 EFI Device Path Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10.3 Device Path Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
10.3.1 Generic Device Path Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
10.3.2 Hardware Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
10.3.2.1 PCI Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
10.3.2.2 PCCARD Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
10.3.2.3 Memory Mapped Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
10.3.2.4 Vendor Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
10.3.2.5 Controller Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
10.3.2.6 BMC Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
10.3.3 ACPI Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
10.3.3.1 ACPI _ADR Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
10.3.3.2 NVDIMM Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
10.3.4 Messaging Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
10.3.4.1 ATAPI Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
10.3.4.2 SCSI Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
10.3.4.3 Fibre Channel Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
10.3.4.4 1394 Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
10.3.4.5 USB Device Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
10.3.4.6 SATA Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
10.3.4.7 USB Device Paths (WWID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
10.3.4.8 Device Logical Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
10.3.4.9 I 2O Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
10.3.4.10 MAC Address Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
10.3.4.11 IPv4 Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
10.3.4.12 IPv6 Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
10.3.4.13 2. VLAN device path node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
10.3.4.14 InﬁniBand Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
10.3.4.15 UART Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
10.3.4.16 Vendor-Deﬁned Messaging Device Path . . . . . . . . . . . . . . . . . . . . . . . 268
10.3.4.17 UART Flow Control Messaging Path . . . . . . . . . . . . . . . . . . . . . . . . . 269
10.3.4.18 Serial Attached SCSI (SAS) Device Path . . . . . . . . . . . . . . . . . . . . . . . 269
10.3.4.19 Serial Attached SCSI (SAS) Extended Device Path . . . . . . . . . . . . . . . . . 271
10.3.4.20 iSCSI Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
10.3.4.21 NVM Express namespace messaging device path node . . . . . . . . . . . . . . . . 280
10.3.4.22 Uniform Resource Identiﬁers (URI) Device Path . . . . . . . . . . . . . . . . . . . 281
10.3.4.23 UFS (Universal Flash Storage) device messaging devicepath node . . . . . . . . . . 281
10.3.4.24 SD (Secure Digital) Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
10.3.4.25 EFI Bluetooth Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
10.3.4.26 Wireless Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
10.3.4.27 eMMC (Embedded Multi-Media Card) Device Path . . . . . . . . . . . . . . . . . 282
10.3.4.28 EFI BluetoothLE Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
10.3.4.29 DNS Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
10.3.4.30 NVDIMM Namespace path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
10.3.4.31 REST Service Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
vi10.3.4.32 NVMe over Fabric (NVMe-oF) Namespace Device Path . . . . . . . . . . . . . . . 284
10.3.4.33 NVMe over Fabric (NVMe-oF) Namespace Device Path Example . . . . . . . . . . 285
10.3.5 Media Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
10.3.5.1 Hard Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
10.3.5.2 CD-ROM Media Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
10.3.5.3 Vendor-Deﬁned Media Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . 288
10.3.5.4 File Path Media Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
10.3.5.5 Media Protocol Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

10.3.5.6 PIWG Firmware File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
10.3.5.7 PIWG Firmware V olume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
10.3.5.8 Relative Offset Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
10.3.5.9 RAM Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
10.3.6 BIOS Boot Speciﬁcation Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
10.4 Device Path Generation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.4.1 Housekeeping Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.4.2 Rules with ACPI _HID and _UID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.4.3 Rules with ACPI _ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.4.4 Hardware vs. Messaging Device Path Rules . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.4.5 Media Device Path Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
10.4.6 Other Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
10.5 Device Path Utilities Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
10.5.1 EFI_DEVICE_PATH_UTILITIES_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 294
10.5.2 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.GetDevicePathSize() . . . . . . . . . . . . 295
10.5.3 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.DuplicateDevicePath() . . . . . . . . . . . 296
10.5.4 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.AppendDevicePath() . . . . . . . . . . . . 296
10.5.5 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.AppendDeviceNode() . . . . . . . . . . . 297
10.5.6 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.AppendDevicePathInstance() . . . . . . . 298
10.5.7 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.GetNextDevicePathInstance() . . . . . . . 298
10.5.8 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.CreateDeviceNode() . . . . . . . . . . . . 299
10.5.9 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.IsDevicePathMultiInstance() . . . . . . . . 300
10.6 EFI Device Path Display Format Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
10.6.1 Design Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
10.6.1.1 Standardized Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
10.6.1.2 Readability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
10.6.1.3 Round-Trip Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
10.6.1.4 Command-Line Parsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
10.6.1.5 Text Representation Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
10.6.1.6 Text Device Node Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
10.6.2 Device Path to Text Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
10.6.2.1 EFI_DEVICE_PATH_TO_TEXT_PROTOCOL . . . . . . . . . . . . . . . . . . . 320
10.6.3 EFI_DEVICE_PATH_TO_TEXT_PROTOCOL.ConvertDeviceNodeToText() . . . . . . . . 321
10.6.4 EFI_DEVICE_PATH_TO_TEXT_PROTOCOL.ConvertDevicePathToText() . . . . . . . . . 322
10.6.5 Device Path from Text Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
10.6.5.1 EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL . . . . . . . . . . . . . . . . . 323
10.6.5.2 EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL.ConvertTextToDeviceNode() . 323
10.6.5.3 EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL.ConvertTextToDevicePath( . . 324
11 Protocols — UEFI Driver Model 325
11.1 EFI Driver Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
11.1.1 EFI_DRIVER_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
11.1.2 EFI_DRIVER_BINDING_PROTOCOL.Supported() . . . . . . . . . . . . . . . . . . . . . 327
11.1.3 EFI_DRIVER_BINDING_PROTOCOL.Start() . . . . . . . . . . . . . . . . . . . . . . . . 331
11.1.4 EFI_DRIVER_BINDING_PROTOCOL.Stop() . . . . . . . . . . . . . . . . . . . . . . . . 339
11.2 EFI Platform Driver Override Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
vii11.2.1 EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriver() . . . . . . . . . . . . . 344
11.2.2 EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriverPath() . . . . . . . . . . 345
11.2.3 EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.DriverLoaded() . . . . . . . . . . . 346
11.3 EFI Bus Speciﬁc Driver Override Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
11.3.1 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL . . . . . . . . . . . . . . . . . 347
11.3.2 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL.GetDriver() . . . . . . . . . . . 348
11.4 EFI Driver Diagnostics Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
11.4.1 EFI_DRIVER_DIAGNOSTICS2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 349
11.4.2 EFI_DRIVER_DIAGNOSTICS2_PROTOCOL.RunDiagnostics() . . . . . . . . . . . . . . 349
11.5 EFI Component Name Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
11.5.1 EFI_COMPONENT_NAME2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 352
11.5.2 EFI_COMPONENT_NAME2_PROTOCOL.GetDriverName() . . . . . . . . . . . . . . . . 352
11.5.3 EFI_COMPONENT_NAME2_PROTOCOL.GetControllerName() . . . . . . . . . . . . . . 353
11.6 EFI Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
11.6.1 EFI_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
11.6.2 EFI_SERVICE_BINDING_PROTOCOL.CreateChild() . . . . . . . . . . . . . . . . . . . . 355
11.6.3 EFI_SERVICE_BINDING_PROTOCOL.DestroyChild() . . . . . . . . . . . . . . . . . . . 359
11.7 EFI Platform to Driver Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
11.7.1 EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL . . . . . . . . . . . . . 362
11.7.2 EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL.Query() . . . . . . . . 363
11.7.3 EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL.Response() . . . . . . 364
11.7.4 DMTF SM CLP ParameterTypeGuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
11.8 EFI Driver Supported EFI Version Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
11.8.1 EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL . . . . . . . . . . . . . . . . . 367
11.9 EFI Driver Family Override Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
11.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
11.9.1.1 EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL . . . . . . . . . . . . . . . . . 368
11.9.1.2 EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL.GetVersion() . . . . . . . . . 369
11.10 EFI Driver Health Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
11.10.1 EFI_DRIVER_HEALTH_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
11.10.2 EFI_DRIVER_HEALTH_PROTOCOL.GetHealthStatus() . . . . . . . . . . . . . . . . . . 370
11.10.3 EFI_DRIVER_HEALTH_PROTOCOL.Repair() . . . . . . . . . . . . . . . . . . . . . . . . 374
11.10.4 UEFI Boot Manager Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.10.4.1 All Controllers Healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.10.4.2 Process a Controller Until Terminal StateReached . . . . . . . . . . . . . . . . . . 377
11.10.4.3 Repair Notiﬁcation Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
11.10.4.4 Process Message List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
11.10.4.5 Process HII Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
11.10.5 UEFI Driver Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.10.5.1 Driver Entry Point Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.10.5.2 Add global variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.10.5.3 Update private context structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.10.5.4 Implement GetHealthStatus() service . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.10.5.5 Implement Repair() service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
11.11 EFI Adapter Information Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
11.11.1 EFI_ADAPTER_INFORMATION_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 380
11.11.2 EFI_ADAPTER_INFORMATION_PROTOCOL.EFI_ADAPTER_GET_INFO() . . . . . . 381
11.11.3 EFI_ADAPTER_INFORMATION_PROTOCOL.EFI_ADAPTER_INFO_SET_INFO() . . . 382

11.11.4 EFI_ADAPTER_INFORMATION_PROTOCOL. EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES()382
11.12 EFI Adapter Information Protocol Information Types . . . . . . . . . . . . . . . . . . . . . . . . . . 383
11.12.1 Network Media State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
11.12.2 Network Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
11.12.3 SAN MAC Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
11.12.4 IPV6 Support from UNDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
viii11.12.5 Network Media Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
11.12.6 Coherent Device Attribute Table (CDAT) Type . . . . . . . . . . . . . . . . . . . . . . . . 386
12 Protocols — Console Support 388
12.1 Console I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
12.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
12.1.2 ConsoleIn Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
12.2 Simple Text Input Ex Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
12.2.1 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 389
12.2.2 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . 390
12.2.3 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.ReadKeyStrokeEx() . . . . . . . . . . . . 391
12.2.4 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.SetState() . . . . . . . . . . . . . . . . . . 393
12.2.5 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.RegisterKeyNotify() . . . . . . . . . . . . 393
12.2.6 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.UnregisterKeyNotify() . . . . . . . . . . . 394
12.3 Simple Text Input Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
12.3.1 EFI_SIMPLE_TEXT_INPUT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 395
12.3.2 EFI_SIMPLE_TEXT_INPUT_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . 396
12.3.3 EFI_SIMPLE_TEXT_INPUT_PROTOCOL.ReadKeyStroke() . . . . . . . . . . . . . . . . 396
12.3.4 ConsoleOut or StandardError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.4 Simple Text Output Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.4.1 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 398
12.4.2 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . 400
12.4.3 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.OutputString() . . . . . . . . . . . . . . . . 400
12.4.4 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.TestString() . . . . . . . . . . . . . . . . . . 403
12.4.5 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.QueryMode() . . . . . . . . . . . . . . . . . 403
12.4.6 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetMode() . . . . . . . . . . . . . . . . . . 404
12.4.7 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetAttribute() . . . . . . . . . . . . . . . . . 405
12.4.8 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.ClearScreen() . . . . . . . . . . . . . . . . . 406
12.4.9 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetCursorPosition() . . . . . . . . . . . . . 407
12.4.10 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.EnableCursor() . . . . . . . . . . . . . . . . 407
12.5 Simple Pointer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
12.5.1 EFI_SIMPLE_POINTER_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
12.5.2 EFI_SIMPLE_POINTER_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . . . 409
12.5.3 EFI_SIMPLE_POINTER_PROTOCOL.GetState() . . . . . . . . . . . . . . . . . . . . . . 410
12.6 EFI Simple Pointer Device Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
12.7 Absolute Pointer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
12.7.1 EFI_ABSOLUTE_POINTER_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 414
12.7.2 EFI_ABSOLUTE_POINTER_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . 416
12.7.3 EFI_ABSOLUTE_POINTER_PROTOCOL.GetState() . . . . . . . . . . . . . . . . . . . . 416
12.8 Serial I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
12.8.1 EFI_SERIAL_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
12.8.2 Serial Device Identiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
12.8.3 Serial Device Type GUIDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
12.8.3.1 EFI_SERIAL_IO_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . . . 421
12.8.3.2 EFI_SERIAL_IO_PROTOCOL.SetAttributes() . . . . . . . . . . . . . . . . . . . 421
12.8.3.3 EFI_SERIAL_IO_PROTOCOL.SetControl() . . . . . . . . . . . . . . . . . . . . . 422
12.8.3.4 EFI_SERIAL_IO_PROTOCOL.GetControl() . . . . . . . . . . . . . . . . . . . . 423
12.8.3.5 EFI_SERIAL_IO_PROTOCOL.Write() . . . . . . . . . . . . . . . . . . . . . . . 424
12.8.3.6 EFI_SERIAL_IO_PROTOCOL.Read() . . . . . . . . . . . . . . . . . . . . . . . . 425
12.9 Graphics Output Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
12.9.1 Blt Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
12.9.2 EFI_GRAPHICS_OUTPUT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
12.9.2.1 EFI_GRAPHICS_OUTPUT_PROTOCOL.QueryMode() . . . . . . . . . . . . . . 430
12.9.2.2 EFI_GRAPHICS_OUTPUT_PROTOCOL.SetMode() . . . . . . . . . . . . . . . . 431
ix12.9.2.3 EFI_GRAPHICS_OUTPUT_PROTOCOL.Blt() . . . . . . . . . . . . . . . . . . . 432
12.9.2.4 EFI_EDID_DISCOVERED_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . 433
12.9.2.5 EFI_EDID_ACTIVE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 434
12.9.2.6 EFI_EDID_OVERRIDE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 435
12.9.2.7 EFI_EDID_OVERRIDE_PROTOCOL.GetEdid() . . . . . . . . . . . . . . . . . . 435
12.10 Rules for PCI/AGP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
13 Protocols – Media Access 439
13.1 Load File Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
13.1.1 EFI_LOAD_FILE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
13.1.2 EFI_LOAD_FILE_PROTOCOL.LoadFile() . . . . . . . . . . . . . . . . . . . . . . . . . . 440
13.2 Load File 2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
13.2.1 EFI_LOAD_FILE2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
13.2.2 EFI_LOAD_FILE2_PROTOCOL.LoadFile() . . . . . . . . . . . . . . . . . . . . . . . . . 442
13.3 File System Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
13.3.1 System Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
13.3.1.1 File System Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
13.3.1.2 File Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
13.3.1.3 Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
13.3.2 Partition Discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
13.3.2.1 ISO-9660 and El Torito . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
13.3.3 Number and Location of System Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
13.3.4 Media Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
13.3.4.1 Removable Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
13.3.4.2 Diskette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
13.3.4.3 Hard Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.3.4.4 CD-ROM and DVD-ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.3.4.5 Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.4 Simple File System Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.4.1 EFI_SIMPLE_FILE_SYSTEM_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.4.2 EFI_SIMPLE_FILE SYSTEM_PROTOCOL.OpenV olume() . . . . . . . . . . . . . . . . . 449
13.5 File Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
13.5.1 EFI_FILE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
13.5.2 EFI_FILE_PROTOCOL.Open() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

13.5.3 EFI_FILE_PROTOCOL.Close() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
13.5.4 EFI_FILE_PROTOCOL.Delete() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
13.5.5 EFI_FILE_PROTOCOL.Read() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
13.5.6 EFI_FILE_PROTOCOL.Write() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
13.5.7 EFI_FILE_PROTOCOL.OpenEx() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
13.5.8 EFI_FILE_PROTOCOL.ReadEx() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
13.5.9 EFI_FILE_PROTOCOL.WriteEx() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
13.5.10 EFI_FILE_PROTOCOL.FlushEx() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
13.5.11 EFI_FILE_PROTOCOL.SetPosition() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
13.5.12 EFI_FILE_PROTOCOL.GetPosition() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
13.5.13 EFI_FILE_PROTOCOL.GetInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
13.5.14 EFI_FILE_PROTOCOL.SetInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
13.5.15 EFI_FILE_PROTOCOL.Flush() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
13.5.16 EFI_FILE_INFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
13.5.17 EFI_FILE_SYSTEM_INFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
13.5.18 EFI_FILE_SYSTEM_VOLUME_LABEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
13.6 Tape Boot Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
13.6.1 Tape I/O Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
13.6.2 Tape I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
13.6.2.1 EFI_TAPE_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
x13.6.2.2 EFI_TAPE_IO_PROTOCOL.TapeRead() . . . . . . . . . . . . . . . . . . . . . . . 469
13.6.2.3 EFI_TAPE_IO_PROTOCOL.TapeWrite() . . . . . . . . . . . . . . . . . . . . . . 470
13.6.2.4 EFI_TAPE_IO_PROTOCOL.TapeRewind() . . . . . . . . . . . . . . . . . . . . . 471
13.6.2.5 EFI_TAPE_IO_PROTOCOL.TapeSpace() . . . . . . . . . . . . . . . . . . . . . . 472
13.6.2.6 EFI_TAPE_IO_PROTOCOL.TapeWriteFM() . . . . . . . . . . . . . . . . . . . . 473
13.6.2.7 EFI_TAPE_IO_PROTOCOL.TapeReset() . . . . . . . . . . . . . . . . . . . . . . 473
13.6.3 Tape Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
13.7 Disk I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
13.7.1 EFI_DISK_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
13.7.2 EFI_DISK_IO_PROTOCOL.ReadDisk() . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
13.7.3 EFI_DISK_IO_PROTOCOL.WriteDisk() . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
13.8 Disk I/O 2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
13.8.1 EFI_DISK_IO2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
13.8.2 EFI_DISK_IO2_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
13.8.3 EFI_DISK_IO2_PROTOCOL.ReadDiskEx() . . . . . . . . . . . . . . . . . . . . . . . . . 480
13.8.4 EFI_DISK_IO2_PROTOCOL.WriteDiskEx() . . . . . . . . . . . . . . . . . . . . . . . . . 481
13.8.5 EFI_DISK_IO2_PROTOCOL.FlushDiskEx() . . . . . . . . . . . . . . . . . . . . . . . . . 482
13.9 Block I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
13.9.1 EFI_BLOCK_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
13.9.2 EFI_BLOCK_IO_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
13.9.3 EFI_BLOCK_IO_PROTOCOL.ReadBlocks() . . . . . . . . . . . . . . . . . . . . . . . . . 486
13.9.4 EFI_BLOCK_IO_PROTOCOL.WriteBlocks() . . . . . . . . . . . . . . . . . . . . . . . . . 487
13.9.5 EFI_BLOCK_IO_PROTOCOL.FlushBlocks() . . . . . . . . . . . . . . . . . . . . . . . . . 488
13.10 Block I/O 2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
13.10.1 EFI_BLOCK_IO2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
13.10.2 EFI_BLOCK_IO2_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
13.10.3 EFI_BLOCK_IO2_PROTOCOL.ReadBlocksEx() . . . . . . . . . . . . . . . . . . . . . . . 490
13.10.4 EFI_BLOCK_IO2_PROTOCOL.WriteBlocksEx() . . . . . . . . . . . . . . . . . . . . . . 491
13.10.5 EFI_BLOCK_IO2_PROTOCOL.FlushBlocksEx() . . . . . . . . . . . . . . . . . . . . . . 493
13.11 Inline Cryptographic Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
13.11.1 EFI_BLOCK_IO_CRYPTO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
13.11.2 EFI_BLOCK_IO_CRYPTO_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . . 497
13.11.3 EFI_BLOCK_IO_CRYPTO_PROTOCOL.GetCapabilities() . . . . . . . . . . . . . . . . . 498
13.11.4 EFI_BLOCK_IO_CRYPTO_PROTOCOL.SetConﬁguration() . . . . . . . . . . . . . . . . 499
13.11.5 EFI_BLOCK_IO_CRYPTO_PROTOCOL.GetConﬁguration() . . . . . . . . . . . . . . . . 500
13.11.6 EFI_BLOCK_IO_CRYPTO_PROTOCOL.ReadExtended() . . . . . . . . . . . . . . . . . . 501
13.11.7 EFI_BLOCK_IO_CRYPTO_PROTOCOL.WriteExtended() . . . . . . . . . . . . . . . . . 502
13.11.8 EFI_BLOCK_IO_CRYPTO_PROTOCOL.FlushBlocks() . . . . . . . . . . . . . . . . . . . 503
13.12 Erase Block Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
13.12.1 EFI_ERASE_BLOCK_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
13.12.2 EFI_ERASE_BLOCK_PROTOCOL.EraseBlocks() . . . . . . . . . . . . . . . . . . . . . . 505
13.13 ATA Pass Thru Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
13.13.1 EFI_ATA_PASS_THRU_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
13.13.2 EFI_ATA_PASS_THRU_PROTOCOL.PassThru() . . . . . . . . . . . . . . . . . . . . . . . 509
13.13.3 EFI_ATA_PASS_THRU_PROTOCOL.GetNextPort() . . . . . . . . . . . . . . . . . . . . . 513
13.13.4 EFI_ATA_PASS_THRU_PROTOCOL.GetNextDevice() . . . . . . . . . . . . . . . . . . . 514
13.13.5 EFI_ATA_PASS_THRU_PROTOCOL.BuildDevicePath() . . . . . . . . . . . . . . . . . . 515
13.13.6 EFI_ATA_PASS_THRU_PROTOCOL.GetDevice() . . . . . . . . . . . . . . . . . . . . . . 516
13.13.7 EFI_ATA_PASS_THRU_PROTOCOL.ResetPort() . . . . . . . . . . . . . . . . . . . . . . 517
13.13.8 EFI_ATA_PASS_THRU_PROTOCOL.ResetDevice() . . . . . . . . . . . . . . . . . . . . . 517
13.14 Storage Security Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
13.14.1 EFI_STORAGE_SECURITY_COMMAND_PROTOCOL . . . . . . . . . . . . . . . . . . 518
13.14.2 EFI_STORAGE_SECURITY_COMMAND_PROTOCOL.ReceiveData() . . . . . . . . . . 519
13.14.3 EFI_STORAGE_SECURITY_COMMAND_PROTOCOL.SendData() . . . . . . . . . . . . 521
xi13.15 NVM Express Pass Through Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
13.15.1 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . 522
13.15.2 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() . . . . . . . . . . . . . . . . 524
13.15.3 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() . . . . . . . . . . 527
13.15.4 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() . . . . . . . . . . . 528
13.15.5 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() . . . . . . . . . . . . 529
13.16 SD MMC Pass Thru Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
13.16.1 EFI_SD_MMC_PASS_THRU_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 530
13.16.2 EFI_SD_MMC_PASS_THRU_PROTOCOL.PassThru() . . . . . . . . . . . . . . . . . . . 530
13.16.3 EFI_SD_MMC_PASS_THRU_PROTOCOL.GetNextSlot() . . . . . . . . . . . . . . . . . . 533
13.16.4 EFI_SD_MMC_PASS_THRU_PROTOCOL.BuildDevicePath() . . . . . . . . . . . . . . . 533
13.16.5 EFI_SD_MMC_PASS_THRU_PROTOCOL.GetSlotNumber() . . . . . . . . . . . . . . . . 534
13.16.6 EFI_SD_MMC_PASS_THRU_PROTOCOL.ResetDevice() . . . . . . . . . . . . . . . . . . 535
13.17 RAM Disk Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
13.17.1 EFI_RAM_DISK_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
13.17.2 EFI_RAM_DISK_PROTOCOL.Register() . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
13.17.3 EFI_RAM_DISK_PROTOCOL.Unregister() . . . . . . . . . . . . . . . . . . . . . . . . . 537
13.18 Partition Information Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

13.19 NVDIMM Label Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
13.19.1 EFI_NVDIMM_LABEL_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
13.19.2 EFI_NVDIMM_LABEL_PROTOCOL.LabelStorageInformation() . . . . . . . . . . . . . . 540
13.19.3 EFI_NVDIMM_LABEL_PROTOCOL.LabelStorageRead() . . . . . . . . . . . . . . . . . 540
13.19.4 EFI_NVDIMM_LABEL_PROTOCOL.LabelStorageWrite() . . . . . . . . . . . . . . . . . 541
13.19.5 Label Storage Area Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
13.19.5.1 Updating the Name of a Namespace Description . . . . . . . . . . . . . . . . . . . 552
13.20 EFI UFS Device Conﬁg Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
13.20.1 EFI_UFS_DEVICE_CONFIG_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 552
13.20.2 EFI_UFS_DEVICE_CONFIG_PROTOCOL.RwUfsDescriptor() . . . . . . . . . . . . . . . 553
13.20.3 EFI_UFS_DEVICE_CONFIG_PROTOCOL.RwUfsFlag() . . . . . . . . . . . . . . . . . . 554
13.20.4 EFI_UFS_DEVICE_CONFIG_PROTOCOL.RwUfsAttribute() . . . . . . . . . . . . . . . . 555
14 Protocols — PCI Bus Support 556
14.1 PCI Root Bridge I/O Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
14.1.1 PCI Root Bridge I/O Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
14.1.2 Sample PCI Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
14.2 PCI Root Bridge I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
14.2.1 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 560
14.2.2 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.PollMem() . . . . . . . . . . . . . . . . . . . 566
14.2.3 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.PollIo() . . . . . . . . . . . . . . . . . . . . . 567
14.2.4 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Mem.Read() . . . . . . . . . . . . . . . . . . 568
14.2.5 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Mem.Write() . . . . . . . . . . . . . . . . . . 568
14.2.6 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Io.Read() . . . . . . . . . . . . . . . . . . . . 569
14.2.7 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Io.Write() . . . . . . . . . . . . . . . . . . . 569
14.2.8 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() . . . . . . . . . . . . . . . . . . . 570
14.2.9 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() . . . . . . . . . . . . . . . . . . . 570
14.2.10 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.CopyMem() . . . . . . . . . . . . . . . . . . 572
14.2.11 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map() . . . . . . . . . . . . . . . . . . . . . 573
14.2.12 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Unmap() . . . . . . . . . . . . . . . . . . . . 574
14.2.13 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.AllocateBuffer() . . . . . . . . . . . . . . . . 575
14.2.14 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.FreeBuffer() . . . . . . . . . . . . . . . . . . 576
14.2.15 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Flush() . . . . . . . . . . . . . . . . . . . . . 577
14.2.16 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() . . . . . . . . . . . . . . . . . 578
14.2.17 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.SetAttributes() . . . . . . . . . . . . . . . . . 578
14.2.18 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Conﬁguration() . . . . . . . . . . . . . . . . . 580
xii14.2.19 PCI Root Bridge Device Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
14.3 PCI Driver Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
14.3.1 PCI Driver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
14.3.2 Driver Diagnostics Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
14.3.3 Component Name Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
14.3.4 Driver Family Override Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
14.3.5 PCI Bus Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
14.3.6 Driver Binding Protocol for PCI Bus Drivers . . . . . . . . . . . . . . . . . . . . . . . . . 587
14.3.7 PCI Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
14.3.8 PCI Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
14.3.9 Driver Binding Protocol for PCI Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . 589
14.4 EFI PCI I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
14.4.1 EFI_PCI_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
14.4.2 EFI_PCI_IO_PROTOCOL.PollMem() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
14.4.3 EFI_PCI_IO_PROTOCOL.PollIo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
14.4.4 EFI_PCI_IO_PROTOCOL.Mem.Read() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
14.4.5 EFI_PCI_IO_PROTOCOL.Mem.Write() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
14.4.6 EFI_PCI_IO_PROTOCOL.Io.Read() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
14.4.7 EFI_PCI_IO_PROTOCOL.Io.Write() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
14.4.8 EFI_PCI_IO_PROTOCOL.Pci.Read() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
14.4.9 EFI_PCI_IO_PROTOCOL.Pci.Write() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
14.4.10 EFI_PCI_IO_PROTOCOL.CopyMem() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
14.4.11 EFI_PCI_IO_PROTOCOL.Map() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
14.4.12 EFI-PCI-IO-PROTOCOL-Unmap() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
14.4.13 EFI_PCI_IO_PROTOCOL.AllocateBuffer() . . . . . . . . . . . . . . . . . . . . . . . . . . 607
14.4.14 EFI_PCI_IO_PROTOCOL.FreeBuffer() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
14.4.15 EFI_PCI_IO_PROTOCOL.Flush() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
14.4.16 EFI_PCI_IO_PROTOCOL.GetLocation() . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
14.4.17 EFI_PCI_IO_PROTOCOL.Attributes() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
14.4.18 EFI_PCI_IO_PROTOCOL.GetBarAttributes() . . . . . . . . . . . . . . . . . . . . . . . . . 612
14.4.19 EFI_PCI_IO_PROTOCOL.SetBarAttributes() . . . . . . . . . . . . . . . . . . . . . . . . . 614
14.4.20 PCI Device Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
14.4.21 PCI Option ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.4.22 PCI Bus Driver Responsibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
14.4.23 PCI Device Driver Responsibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
14.4.24 Nonvolatile Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
14.4.25 PCI Hot-Plug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
15 Protocols — SCSI Driver Models and Bus Support 626
15.1 SCSI Driver Model Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
15.2 SCSI Bus Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
15.2.1 Driver Binding Protocol for SCSI Bus Drivers . . . . . . . . . . . . . . . . . . . . . . . . . 627
15.2.2 SCSI Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
15.3 SCSI Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
15.3.1 Driver Binding Protocol for SCSI Device Drivers . . . . . . . . . . . . . . . . . . . . . . . 628
15.4 EFI SCSI I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
15.4.1 EFI_SCSI_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
15.4.2 EFI_SCSI_IO_PROTOCOL.GetDeviceType() . . . . . . . . . . . . . . . . . . . . . . . . . 630
15.4.3 EFI_SCSI_IO_PROTOCOL.GetDeviceLocation() . . . . . . . . . . . . . . . . . . . . . . . 631
15.4.4 EFI_SCSI_IO_PROTOCOL.ResetBus() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
15.4.5 EFI_SCSI_IO_PROTOCOL.ResetDevice() . . . . . . . . . . . . . . . . . . . . . . . . . . 632
15.4.6 EFI_SCSI_IO_PROTOCOL.ExecuteScsiCommand() . . . . . . . . . . . . . . . . . . . . . 633
15.5 SCSI Device Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
15.5.1 SCSI Device Path Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
xiii15.5.2 ATAPI Device Path Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
15.5.3 Fibre Channel Device Path Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

15.5.4 InﬁniBand Device Path Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
15.6 SCSI Pass Thru Device Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
15.7 Extended SCSI Pass Thru Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
15.7.1 EFI_EXT_SCSI_PASS_THRU_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 642
15.7.2 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.PassThru() . . . . . . . . . . . . . . . . . . . 644
15.7.3 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetNextTargetLun() . . . . . . . . . . . . . . 648
15.7.4 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.BuildDevicePath() . . . . . . . . . . . . . . . 649
15.7.5 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetTargetLun() . . . . . . . . . . . . . . . . 650
15.7.6 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.ResetChannel() . . . . . . . . . . . . . . . . 651
15.7.7 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.ResetTargetLun() . . . . . . . . . . . . . . . 651
15.7.8 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetNextTarget() . . . . . . . . . . . . . . . . 652
16 Protocols — iSCSI Boot 654
16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
16.1.1 iSCSI UEFI Driver Layering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
16.2 EFI iSCSI Initiator Name Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
16.2.1 EFI_ISCSI_INITIATOR_NAME_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 655
16.2.2 EFI_ISCSI_INITIATOR_NAME_PROTOCOL. Get() . . . . . . . . . . . . . . . . . . . . . 655
16.2.3 EFI_ISCSI_INITIATOR_NAME_PROTOCOL.Set() . . . . . . . . . . . . . . . . . . . . . 656
17 Protocols — USB Support 657
17.1 USB2 Host Controller Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
17.1.1 USB Host Controller Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
17.1.2 EFI_USB2_HC_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
17.1.3 EFI_USB2_HC_PROTOCOL.GetCapability() . . . . . . . . . . . . . . . . . . . . . . . . . 659
17.1.4 EFI_USB2_HC_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
17.1.5 EFI_USB2_HC_PROTOCOL.GetState() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
17.1.6 EFI_USB2_HC_PROTOCOL.SetState() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
17.1.7 EFI_USB2_HC_PROTOCOL.ControlTransfer() . . . . . . . . . . . . . . . . . . . . . . . . 663
17.1.8 EFI_USB2_HC_PROTOCOL.BulkTransfer() . . . . . . . . . . . . . . . . . . . . . . . . . 665
17.1.9 EFI_USB2_HC_PROTOCOL.AsyncInterruptTransfer() . . . . . . . . . . . . . . . . . . . . 667
17.1.10 EFI_USB2_HC_PROTOCOL.SyncInterruptTransfer() . . . . . . . . . . . . . . . . . . . . 669
17.1.11 EFI_USB2_HC_PROTOCOL.IsochronousTransfer() . . . . . . . . . . . . . . . . . . . . . 670
17.1.12 EFI_USB2_HC_PROTOCOL.AsyncIsochronousTransfer() . . . . . . . . . . . . . . . . . . 672
17.1.13 EFI_USB2_HC_PROTOCOL.GetRootHubPortStatus() . . . . . . . . . . . . . . . . . . . . 674
17.1.14 EFI_USB2_HC_PROTOCOL.SetRootHubPortFeature() . . . . . . . . . . . . . . . . . . . 677
17.1.15 EFI_USB2_HC_PROTOCOL.ClearRootHubPortFeature() . . . . . . . . . . . . . . . . . . 679
17.2 USB Driver Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
17.2.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
17.2.2 USB Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
17.2.2.1 USB Bus Driver Entry Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
17.2.2.2 Driver Binding Protocol for USB Bus Drivers . . . . . . . . . . . . . . . . . . . . 681
17.2.2.3 USB Hot-Plug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
17.2.2.4 USB Bus Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
17.2.3 USB Device Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
17.2.3.1 USB Device Driver Entry Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
17.2.3.2 Driver Binding Protocol for USB DeviceDrivers . . . . . . . . . . . . . . . . . . . 683
17.2.4 USB I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
17.2.5 EFI_USB_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
17.2.6 EFI_USB_IO_PROTOCOL.UsbControlTransfer() . . . . . . . . . . . . . . . . . . . . . . . 685
17.2.7 EFI_USB_IO_PROTOCOL.UsbBulkTransfer() . . . . . . . . . . . . . . . . . . . . . . . . 687
17.2.8 EFI_USB_IO_PROTOCOL.UsbAsyncInterruptTransfer() . . . . . . . . . . . . . . . . . . . 688
xiv17.2.9 EFI_USB_IO_PROTOCOL.UsbSyncInterruptTransfer() . . . . . . . . . . . . . . . . . . . 690
17.2.10 EFI_USB_IO_PROTOCOL.UsbIsochronousTransfer() . . . . . . . . . . . . . . . . . . . . 691
17.2.11 EFI_USB_IO_PROTOCOL.UsbAsyncIsochronousTransfer() . . . . . . . . . . . . . . . . . 692
17.2.12 EFI_USB_IO_PROTOCOL.UsbGetDeviceDescriptor() . . . . . . . . . . . . . . . . . . . . 693
17.2.13 EFI_USB_IO_PROTOCOL.UsbGetConﬁgDescriptor() . . . . . . . . . . . . . . . . . . . . 694
17.2.14 EFI_USB_IO_PROTOCOL.UsbGetInterfaceDescriptor() . . . . . . . . . . . . . . . . . . . 695
17.2.15 EFI_USB_IO_PROTOCOL.UsbGetEndpointDescriptor() . . . . . . . . . . . . . . . . . . . 696
17.2.16 EFI_USB_IO_PROTOCOL.UsbGetStringDescriptor() . . . . . . . . . . . . . . . . . . . . 698
17.2.17 EFI_USB_IO_PROTOCOL.UsbGetSupportedLanguages() . . . . . . . . . . . . . . . . . . 698
17.2.18 EFI_USB_IO_PROTOCOL.UsbPortReset() . . . . . . . . . . . . . . . . . . . . . . . . . . 699
17.3 USB Function Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
17.3.1 EFI_USBFN_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
17.3.2 EFI_USBFN_IO_PROTOCOL.DetectPort() . . . . . . . . . . . . . . . . . . . . . . . . . . 702
17.3.3 EFI_USBFN_IO_PROTOCOL.ConﬁgureEnableEndpoints() . . . . . . . . . . . . . . . . . 703
17.3.4 EFI_USBFN_IO_PROTOCOL.GetEndpointMaxPacketSize() . . . . . . . . . . . . . . . . 704
17.3.5 EFI_USBFN_IO_PROTOCOL.GetDeviceInfo() . . . . . . . . . . . . . . . . . . . . . . . . 705
17.3.6 EFI_USBFN_IO_PROTOCOL.GetVendorIdProductId() . . . . . . . . . . . . . . . . . . . 706
17.3.7 EFI_USBFN_IO_PROTOCOL.AbortTransfer() . . . . . . . . . . . . . . . . . . . . . . . . 706
17.3.8 EFI_USBFN_IO_PROTOCOL.GetEndpointStallState() . . . . . . . . . . . . . . . . . . . . 707
17.3.9 EFI_USBFN_IO_PROTOCOL.SetEndpointStallState() . . . . . . . . . . . . . . . . . . . . 708
17.3.10 EFI_USBFN_IO_PROTOCOL.EventHandler() . . . . . . . . . . . . . . . . . . . . . . . . 708
17.3.11 EFI_USBFN_IO_PROTOCOL.Transfer() . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
17.3.12 EFI_USBFN_IO_PROTOCOL.GetMaxTransferSize() . . . . . . . . . . . . . . . . . . . . 713
17.3.13 EFI_USBFN_IO_PROTOCOL.AllocateTransferBuffer() . . . . . . . . . . . . . . . . . . . 713
17.3.14 EFI_USBFN_IO_PROTOCOL.FreeTransferBuffer() . . . . . . . . . . . . . . . . . . . . . 714
17.3.15 EFI_USBFN_IO_PROTOCOL.StartController() . . . . . . . . . . . . . . . . . . . . . . . . 714
17.3.16 EFI_USBFN_IO_PROTOCOL.StopController() . . . . . . . . . . . . . . . . . . . . . . . . 715
17.3.16.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
17.3.17 EFI_USBFN_IO_PROTOCOL.SetEndpointPolicy() . . . . . . . . . . . . . . . . . . . . . . 715
17.3.18 EFI_USBFN_IO_PROTOCOL.GetEndpointPolicy() . . . . . . . . . . . . . . . . . . . . . 717
17.3.19 USB Function Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
18 Protocols — Debugger Support 720
18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
18.2 EFI Debug Support Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
18.2.1 EFI Debug Support Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
18.2.2 EFI_DEBUG_SUPPORT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
18.2.3 EFI_DEBUG_SUPPORT_PROTOCOL.GetMaximumProcessorIndex() . . . . . . . . . . . 723
18.2.4 EFI_DEBUG_SUPPORT_PROTOCOL.RegisterPeriodicCallback() . . . . . . . . . . . . . 723
18.2.5 EFI_DEBUG_SUPPORT_PROTOCOL.RegisterExceptionCallback() . . . . . . . . . . . . 731
18.2.6 EFI_DEBUG_SUPPORT_PROTOCOL.InvalidateInstructionCache() . . . . . . . . . . . . . 735
18.3 EFI Debugport Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
18.3.1 EFI Debugport Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
18.3.2 EFI_DEBUGPORT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

18.3.3 EFI_DEBUGPORT_PROTOCOL.Reset() . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
18.3.4 EFI_DEBUGPORT_PROTOCOL.Write() . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
18.3.5 EFI_DEBUGPORT_PROTOCOL.Read() . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
18.3.6 EFI_DEBUGPORT_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
18.3.7 Debugport Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
18.3.8 EFI Debugport Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
18.4 EFI Debug Support Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
18.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
18.4.2 EFI System Table Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
18.4.3 EFI Image Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
xv19 Protocols — Compression Algorithm Speciﬁcation 744
19.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
19.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
19.2.1 Bit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
19.2.2 Overall Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
19.2.3 Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
19.2.3.1 Block Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
19.2.3.2 Block Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
19.3 Compressor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
19.3.1 Overall Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
19.3.2 String Info Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
19.3.2.1 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
19.3.2.2 Searching the Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
19.3.2.3 Adding String Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
19.3.2.4 Deleting String Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
19.3.3 Huffman Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
19.3.3.1 Huffman Tree Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
19.3.3.2 Code Length Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
19.3.3.3 Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
19.4 Decompressor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
19.5 Decompress Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
19.5.1 EFI_DECOMPRESS_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
19.5.2 EFI_DECOMPRESS_PROTOCOL.GetInfo() . . . . . . . . . . . . . . . . . . . . . . . . . 759
19.5.3 EFI_DECOMPRESS_PROTOCOL.Decompress() . . . . . . . . . . . . . . . . . . . . . . . 760
20 Protocols — ACPI Protocols 762
20.1 EFI_ACPI_TABLE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
20.2 EFI_ACPI_TABLE_PROTOCOL.InstallAcpiTable() . . . . . . . . . . . . . . . . . . . . . . . . . . 762
20.3 EFI_ACPI_TABLE_PROTOCOL.UninstallAcpiTable() . . . . . . . . . . . . . . . . . . . . . . . . 763
21 Protocols — String Services 765
21.1 Unicode Collation Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
21.1.1 EFI_UNICODE_COLLATION_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 765
21.1.2 EFI_UNICODE_COLLATION_PROTOCOL.StriColl() . . . . . . . . . . . . . . . . . . . . 766
21.1.3 EFI_UNICODE_COLLATION_PROTOCOL.MetaiMatch() . . . . . . . . . . . . . . . . . 767
21.1.4 EFI_UNICODE_COLLATION_PROTOCOL.StrLwr() . . . . . . . . . . . . . . . . . . . . 768
21.1.5 EFI_UNICODE_COLLATION_PROTOCOL.StrUpr() . . . . . . . . . . . . . . . . . . . . 768
21.1.6 EFI_UNICODE_COLLATION_PROTOCOL.FatToStr() . . . . . . . . . . . . . . . . . . . 769
21.1.7 EFI_UNICODE_COLLATION_PROTOCOL.StrToFat() . . . . . . . . . . . . . . . . . . . 769
21.2 Regular Expression Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
21.2.1 EFI_REGULAR_EXPRESSION_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 770
21.2.2 EFI_REGULAR_EXPRESSION_PROTOCOL.MatchString() . . . . . . . . . . . . . . . . 770
21.2.3 EFI_REGULAR_EXPRESSION_PROTOCOL.GetInfo() . . . . . . . . . . . . . . . . . . . 772
21.2.4 EFI Regular Expression Syntax Type Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . 773
22 EFI Byte Code Virtual Machine 774
22.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
22.1.1 Processor Architecture Independence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
22.1.2 OS Independent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
22.1.3 EFI Compliant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
22.1.4 Coexistence of Legacy Option ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
22.1.5 Relocatable Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
22.1.6 Size Restrictions Based on Memory Available . . . . . . . . . . . . . . . . . . . . . . . . . 776
22.2 Memory Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
xvi22.3 Virtual Machine Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
22.4 Natural Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
22.4.1 Sign Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
22.4.2 Bits Assigned to Natural Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
22.4.3 Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
22.4.4 Natural Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
22.5 EBC Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
22.5.1 Direct Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
22.5.2 Indirect Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
22.5.3 Indirect with Index Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
22.5.4 Immediate Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
22.6 EBC Instruction Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
22.7 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
22.7.1 Instruction Opcode Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
22.7.2 Instruction Operands Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
22.7.3 Index/Immediate Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
22.8 EBC Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
22.8.1 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
22.8.2 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
22.8.3 ASHR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
22.8.4 BREAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
22.8.5 CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
22.8.6 CMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
22.8.7 CMPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
22.8.8 DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
22.8.9 DIVU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
22.8.10 EXTNDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

22.8.11 EXTNDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
22.8.12 EXTNDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
22.8.13 JMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
22.8.14 JMP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
22.8.15 LOADSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
22.8.16 MOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
22.8.17 MODU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
22.8.18 MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
22.8.19 MOVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
22.8.20 MOVIn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
22.8.21 MOVn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
22.8.22 MOVREL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
22.8.23 MOVsn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
22.8.24 MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
22.8.25 MULU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
22.8.26 NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
22.8.27 NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
22.8.28 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
22.8.29 POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
22.8.30 POPn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
22.8.31 PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
22.8.32 PUSHn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
22.8.33 RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
22.8.34 SHL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
22.8.35 SHR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
22.8.36 STORESP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
22.8.37 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
xvii22.8.38 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
22.9 Runtime and Software Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
22.9.1 Calling Outside VM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
22.9.2 Calling Inside VM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
22.9.3 Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
22.9.4 Return Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
22.9.5 Binary Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
22.10 Architectural Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
22.10.1 EBC Image Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
22.10.2 EBC Execution Interfacing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
22.10.3 Interfacing Function Parameters Requirements . . . . . . . . . . . . . . . . . . . . . . . . 823
22.10.4 Function Return Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
22.10.5 Function Return Values Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
22.11 EBC Interpreter Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.11.1 EFI_EBC_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.11.2 EFI_EBC_PROTOCOL.CreateThunk() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.11.3 EFI_EBC_PROTOCOL.UnloadImage() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
22.11.4 EFI_EBC_PROTOCOL.RegisterICacheFlush() . . . . . . . . . . . . . . . . . . . . . . . . 826
22.11.5 EFI_EBC_PROTOCOL.GetVersion() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
22.12 EBC Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
22.12.1 EBC C Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
22.12.2 C Coding Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
22.12.3 EBC Interface Assembly Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
22.12.4 Stack Maintenance and Argument Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
22.12.5 Native to EBC Arguments Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . 828
22.12.6 EBC to Native Arguments Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . 828
22.12.7 EBC to EBC Arguments Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . 829
22.12.8 Function Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
22.12.9 Function Return Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
22.12.10Thunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
22.12.10.1 Thunking EBC to Native Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
22.12.10.2 Thunking Native Code to EBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
22.12.10.3 Thunking EBC to EBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
22.12.11EBC Linker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
22.12.12Image Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
22.12.13Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
22.13 VM Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
22.13.1 Divide By 0 Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
22.13.2 Debug Break Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
22.13.3 Invalid Opcode Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
22.13.4 Stack Fault Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
22.13.5 Alignment Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
22.13.6 Instruction Encoding Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
22.13.7 Bad Break Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
22.13.8 Undeﬁned Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
22.14 Option ROM Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
22.14.1 EFI Drivers for PCI Add-in Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
22.14.2 Non-PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
23 Firmware Update and Reporting 835
23.1 Firmware Management Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
23.1.1 EFI_FIRMWARE_MANAGEMENT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . 835
23.1.2 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo() . . . . . . . . . . . . . 836
23.1.3 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImage() . . . . . . . . . . . . . . . 841
xviii23.1.4 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage() . . . . . . . . . . . . . . . . 842
23.1.5 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.CheckImage() . . . . . . . . . . . . . . 843
23.1.6 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetPackageInfo() . . . . . . . . . . . . 845
23.1.7 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetPackageInfo() . . . . . . . . . . . . 846
23.2 Dependency Expression Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

23.2.1 PUSH_GUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
23.2.2 PUSH_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
23.2.3 DECLARE_VERSION_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
23.2.4 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
23.2.5 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
23.2.6 NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
23.2.7 TRUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
23.2.8 FALSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
23.2.9 EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
23.2.10 GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
23.2.11 GTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
23.2.12 LT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
23.2.13 LTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
23.2.14 END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
23.2.15 DECLARE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
23.3 Delivering Capsules Containing Updates toFirmware Management Protocol . . . . . . . . . . . . . . 855
23.3.1 EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID . . . . . . . . . . . . . . . . . 855
23.3.2 DEFINED FIRMWARE MANAGEMENT PROTOCOL DATA CAPSULE STRUCTURE . 856
23.3.3 Firmware Processing of the Capsule Identiﬁed by EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID859
23.4 EFI System Resource Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
23.4.1 EFI_SYSTEM_RESOURCE_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
23.4.2 Adding and Removing Devices from the ESRT . . . . . . . . . . . . . . . . . . . . . . . . 862
23.4.3 ESRT and Firmware Management Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 863
23.4.4 Mapping Firmware Management Protocol Descriptors to ESRT Entries . . . . . . . . . . . 863
23.5 Delivering Capsule Containing JSON payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
23.5.1 EFI_JSON_CAPSULE_ID_GUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
23.5.2 Deﬁned JSON Capsule Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
23.5.3 Firmware Processing of the Capsule Identiﬁed by EFI_JSON_CAPSULE_ID_GUID . . . . 866
24 Network Protocols — SNP, PXE, BIS and HTTP Boot 867
24.1 Simple Network Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
24.1.1 EFI_SIMPLE_NETWORK_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
24.1.2 EFI_SIMPLE_NETWORK.Start() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
24.1.3 EFI_SIMPLE_NETWORK.Stop() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
24.1.4 EFI_SIMPLE_NETWORK.Initialize() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
24.1.5 EFI_SIMPLE_NETWORK.Reset() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
24.1.6 EFI_SIMPLE_NETWORK.Shutdown() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
24.1.7 EFI_SIMPLE_NETWORK.ReceiveFilters() . . . . . . . . . . . . . . . . . . . . . . . . . . 874
24.1.8 EFI_SIMPLE_NETWORK.StationAddress() . . . . . . . . . . . . . . . . . . . . . . . . . 876
24.1.9 EFI_SIMPLE_NETWORK.Statistics() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
24.1.10 EFI_SIMPLE_NETWORK.MCastIPtoMAC() . . . . . . . . . . . . . . . . . . . . . . . . . 879
24.1.11 EFI_SIMPLE_NETWORK.NvData() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
24.1.12 EFI_SIMPLE_NETWORK.GetStatus() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
24.1.13 EFI_SIMPLE_NETWORK.Transmit() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
24.1.14 EFI_SIMPLE_NETWORK.Receive() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
24.2 Network Interface Identiﬁer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
24.2.1 EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL . . . . . . . . . . . . . . . . . 885
24.3 PXE Base Code Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
24.3.1 EFI_PXE_BASE_CODE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
xix24.3.2 DHCP Packet Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
24.3.3 IP Receive Filter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
24.3.4 ARP Cache Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
24.3.5 Filter Operations for UDP Read/Write Functions . . . . . . . . . . . . . . . . . . . . . . . 894
24.3.6 EFI_PXE_BASE_CODE_PROTOCOL.Start() . . . . . . . . . . . . . . . . . . . . . . . . . 896
24.3.7 EFI_PXE_BASE_CODE_PROTOCOL.Stop() . . . . . . . . . . . . . . . . . . . . . . . . . 897
24.3.8 EFI_PXE_BASE_CODE_PROTOCOL.Dhcp() . . . . . . . . . . . . . . . . . . . . . . . . 898
24.3.9 EFI_PXE_BASE_CODE_PROTOCOL.Discover() . . . . . . . . . . . . . . . . . . . . . . 899
24.3.10 EFI_PXE_BASE_CODE_PROTOCOL.Mtftp() . . . . . . . . . . . . . . . . . . . . . . . . 901
24.3.11 EFI_PXE_BASE_CODE_PROTOCOL.UdpWrite() . . . . . . . . . . . . . . . . . . . . . . 904
24.3.12 EFI_PXE_BASE_CODE_PROTOCOL.UdpRead() . . . . . . . . . . . . . . . . . . . . . . 906
24.3.13 EFI_PXE_BASE_CODE_PROTOCOL.SetIpFilter() . . . . . . . . . . . . . . . . . . . . . 908
24.3.14 EFI_PXE_BASE_CODE_PROTOCOL.Arp() . . . . . . . . . . . . . . . . . . . . . . . . . 910
24.3.15 EFI_PXE_BASE_CODE_PROTOCOL.SetParameters() . . . . . . . . . . . . . . . . . . . 911
24.3.16 EFI_PXE_BASE_CODE_PROTOCOL.SetStationIp() . . . . . . . . . . . . . . . . . . . . 912
24.3.17 EFI_PXE_BASE_CODE_PROTOCOL.SetPackets() . . . . . . . . . . . . . . . . . . . . . 913
24.3.18 Netboot6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
24.3.18.1 DHCP6 options for PXE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
24.3.18.2 IPv6-based PXE boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
24.3.18.3 Proxy DHCP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
24.4 PXE Base Code Callback Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
24.4.1 EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 920
24.4.2 EFI_PXE_BASE_CODE_CALLBACK.Callback() . . . . . . . . . . . . . . . . . . . . . . 920
24.5 Boot Integrity Services Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
24.5.1 EFI_BIS_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
24.5.2 EFI_BIS_PROTOCOL.Initialize() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
24.5.3 EFI_BIS_PROTOCOL.Shutdown() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
24.5.4 EFI_BIS_PROTOCOL.Free() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
24.5.5 EFI_BIS_PROTOCOL.GetBootObjectAuthorizationCertiﬁcate() . . . . . . . . . . . . . . . 928
24.5.6 EFI_BIS_PROTOCOL.GetBootObjectAuthorizationCheckFlag() . . . . . . . . . . . . . . . 928
24.5.7 EFI_BIS_PROTOCOL.GetBootObjectAuthorizationUpdateToken() . . . . . . . . . . . . . 929
24.5.8 EFI_BIS_PROTOCOL.GetSignatureInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
24.5.9 EFI_BIS_PROTOCOL.UpdateBootObjectAuthorization() . . . . . . . . . . . . . . . . . . 933
24.5.10 EFI_BIS_PROTOCOL.VerifyBootObject() . . . . . . . . . . . . . . . . . . . . . . . . . . 939
24.5.11 EFI_BIS_PROTOCOL.VerifyObjectWithCredential() . . . . . . . . . . . . . . . . . . . . . 944
24.6 DHCP options for ISCSI on IPV6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
24.7 HTTP Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
24.7.1 Boot from URL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
24.7.2 Concept conﬁguration for a typical HTTP Bootscenario . . . . . . . . . . . . . . . . . . . . 951
24.7.2.1 Use in Corporate environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
24.7.2.2 Use case in Home environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951

24.7.3 Protocol Layout for UEFI HTTP Boot Clientconcept conﬁguration for a typical HTTP Boot
scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
24.7.3.1 Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
24.7.4 Concept of Message Exchange in a typical HTTPBoot scenario (IPv4 in Corporate Environ-
ment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
24.7.4.1 Message exchange between EFI Client and DHCPserver using DHCP Client Exten-
sions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
24.7.5 Priority1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
24.7.6 Priority2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
24.7.7 Priority3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
24.7.8 Priority4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
24.7.8.1 Message exchange between UEFI Client and DHCPserver not using DHCP Client
Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
xx24.7.8.2 Message in DNS Query/Reply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
24.7.8.3 Message in HTTP Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
24.7.9 Concept of Message Exchange in HTTP Bootscenario (IPv6) . . . . . . . . . . . . . . . . . 958
24.7.9.1 Message exchange between EFI Client andDHCPv6 server with DHCP Client ex-
tensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
24.7.9.2 Message exchange between UEFI Client andDHCPv6 server not using DHCP Client
Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
24.7.9.3 Message exchange between UEFI Client and DNS6server . . . . . . . . . . . . . . 960
24.7.9.4 Message in HTTP Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
24.7.10 EFI HTTP Boot Callback Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
24.7.11 EFI_HTTP_BOOT_CALLBACK_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 960
24.7.12 EFI_HTTP_BOOT_CALLBACK_PROTOCOL.Callback() . . . . . . . . . . . . . . . . . . 960
25 Network Protocols - Managed Network 962
25.1 EFI Managed Network Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
25.1.1 EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . 962
25.1.2 EFI_MANAGED_NETWORK_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 963
25.1.3 EFI_MANAGED_NETWORK_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . 964
25.1.4 EFI_MANAGED_NETWORK_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . 965
25.1.5 EFI_MANAGED_NETWORK_PROTOCOL.McastIpToMac() . . . . . . . . . . . . . . . . 966
25.1.6 EFI_MANAGED_NETWORK_PROTOCOL.Groups() . . . . . . . . . . . . . . . . . . . . 967
25.1.7 EFI_MANAGED_NETWORK_PROTOCOL.Transmit() . . . . . . . . . . . . . . . . . . . 968
25.1.8 EFI_MANAGED_NETWORK_PROTOCOL.Receive() . . . . . . . . . . . . . . . . . . . . 972
25.1.9 EFI_MANAGED_NETWORK_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . 973
25.1.10 EFI_MANAGED_NETWORK_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . 974
26 Network Protocols — Bluetooth 975
26.1 EFI Bluetooth Host Controller Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
26.1.1 EFI_BLUETOOTH_HC_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
26.1.2 BLUETOOTH_HC_PROTOCOL.SendCommand() . . . . . . . . . . . . . . . . . . . . . . 976
26.1.3 BLUETOOTH_HC_PROTOCOL.ReceiveEvent() . . . . . . . . . . . . . . . . . . . . . . . 977
26.1.4 BLUETOOTH_HC_PROTOCOL.AsyncReceiveEvent() . . . . . . . . . . . . . . . . . . . 978
26.1.5 BLUETOOTH_HC_PROTOCOL.SendACLData() . . . . . . . . . . . . . . . . . . . . . . 979
26.1.6 BLUETOOTH_HC_PROTOCOL.ReceiveACLData() . . . . . . . . . . . . . . . . . . . . . 980
26.1.7 BLUETOOTH_HC_PROTOCOL.AsyncReceiveACLData() . . . . . . . . . . . . . . . . . 981
26.1.8 BLUETOOTH_HC_PROTOCOL.SendSCOData() . . . . . . . . . . . . . . . . . . . . . . 982
26.1.9 BLUETOOTH_HC_PROTOCOL.ReceiveSCOData() . . . . . . . . . . . . . . . . . . . . . 983
26.1.10 BLUETOOTH_HC_PROTOCOL.AsyncReceiveSCOData() . . . . . . . . . . . . . . . . . 984
26.2 EFI Bluetooth Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
26.2.1 EFI_BLUETOOTH_IO_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . 985
26.2.2 EFI_BLUETOOTH_IO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
26.2.3 BLUETOOTH_IO_PROTOCOL.GetDeviceInfo . . . . . . . . . . . . . . . . . . . . . . . . 986
26.2.4 BLUETOOTH_IO_PROTOCOL.GetSdpInfo . . . . . . . . . . . . . . . . . . . . . . . . . 987
26.2.5 BLUETOOTH_IO_PROTOCOL.L2CapRawSend . . . . . . . . . . . . . . . . . . . . . . . 988
26.2.6 BLUETOOTH_IO_PROTOCOL.L2CapRawReceive . . . . . . . . . . . . . . . . . . . . . 989
26.2.7 BLUETOOTH_IO_PROTOCOL.L2CapRawAsyncReceive . . . . . . . . . . . . . . . . . . 990
26.2.8 BLUETOOTH_IO_PROTOCOL.L2CapSend . . . . . . . . . . . . . . . . . . . . . . . . . 991
26.2.9 BLUETOOTH_IO_PROTOCOL.L2CapReceive . . . . . . . . . . . . . . . . . . . . . . . . 992
26.2.10 BLUETOOTH_IO_PROTOCOL.L2CapAsyncReceive . . . . . . . . . . . . . . . . . . . . 993
26.2.11 BLUETOOTH_IO_PROTOCOL.L2CapConnect . . . . . . . . . . . . . . . . . . . . . . . 994
26.2.12 BLUETOOTH_IO_PROTOCOL.L2CapDisconnect . . . . . . . . . . . . . . . . . . . . . . 995
26.2.13 BLUETOOTH_IO_PROTOCOL.L2CapRegisterService . . . . . . . . . . . . . . . . . . . 995
26.3 EFI Bluetooth Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
26.3.1 EFI_BLUETOOTH_CONFIG_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 996
xxi26.3.2 BLUETOOTH_CONFIG_PROTOCOL.Init . . . . . . . . . . . . . . . . . . . . . . . . . . 997
26.3.3 BLUETOOTH_CONFIG_PROTOCOL.Scan . . . . . . . . . . . . . . . . . . . . . . . . . 997
26.3.4 BLUETOOTH_CONFIG_PROTOCOL.Connect . . . . . . . . . . . . . . . . . . . . . . . 999
26.3.5 BLUETOOTH_CONFIG_PROTOCOL.Disconnect . . . . . . . . . . . . . . . . . . . . . . 999
26.3.6 BLUETOOTH_CONFIG_PROTOCOL.GetData . . . . . . . . . . . . . . . . . . . . . . . 1000
26.3.7 BLUETOOTH_CONFIG_PROTOCOL.SetData . . . . . . . . . . . . . . . . . . . . . . . . 1002
26.3.8 BLUETOOTH_CONFIG_PROTOCOL.GetRemoteData . . . . . . . . . . . . . . . . . . . 1002
26.3.9 BLUETOOTH_CONFIG_PROTOCOL.RegisterPinCallback . . . . . . . . . . . . . . . . . 1003
26.3.10 BLUETOOTH_CONFIG_PROTOCOL.RegisterGetLinkKeyCallback . . . . . . . . . . . . 1005
26.3.11 BLUETOOTH_CONFIG_PROTOCOL.RegisterSetLinkKeyCallback . . . . . . . . . . . . 1006
26.3.12 BLUETOOTH_CONFIG_PROTOCOL.RegisterLinkConnectCompleteCallback . . . . . . . 1007
26.4 EFI Bluetooth Attribute Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
26.4.1 EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 1008
26.4.2 BLUETOOTH_ATTRIBUTE_PROTOCOL.SendRequest . . . . . . . . . . . . . . . . . . . 1009
26.4.3 BLUETOOTH_ATTRIBUTE_PROTOCOL.RegisterForServerNotiﬁcation . . . . . . . . . . 1010
26.4.4 BLUETOOTH_ATTRIBUTE_PROTOCOL.GetServiceInfo . . . . . . . . . . . . . . . . . 1011
26.4.5 BLUETOOTH_ATTRIBUTE_PROTOCOL.GetDeviceInfo . . . . . . . . . . . . . . . . . . 1014
26.4.6 EFI_BLUETOOTH_ATTRIBUTE_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . 1015
26.5 EFI Bluetooth LE Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
26.5.1 EFI_BLUETOOTH_LE_CONFIG_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 1016
26.5.2 BLUETOOTH_LE_CONFIG_PROTOCOL.Init . . . . . . . . . . . . . . . . . . . . . . . . 1017
26.5.3 BLUETOOTH_LE_CONFIG_PROTOCOL.Scan . . . . . . . . . . . . . . . . . . . . . . . 1017
26.5.4 BLUETOOTH_LE_CONFIG_PROTOCOL.Connect . . . . . . . . . . . . . . . . . . . . . 1019
26.5.5 BLUETOOTH_LE_CONFIG_PROTOCOL.Disconnect . . . . . . . . . . . . . . . . . . . . 1020
26.5.6 BLUETOOTH_LE_CONFIG_PROTOCOL.GetData . . . . . . . . . . . . . . . . . . . . . 1021
26.5.7 BLUETOOTH_LE_CONFIG_PROTOCOL.SetData . . . . . . . . . . . . . . . . . . . . . 1022
26.5.8 BLUETOOTH_LE_CONFIG_PROTOCOL.GetRemoteData . . . . . . . . . . . . . . . . . 1022
26.5.9 BLUETOOTH_LE_CONFIG_PROTOCOL.RegisterSmpAuthCallback . . . . . . . . . . . 1023
26.5.10 BLUETOOTH_LE_CONFIG_PROTOCOL.SendSmpAuthData . . . . . . . . . . . . . . . 1025
26.5.11 BLUETOOTH_LE_CONFIG_PROTOCOL.RegisterSmpGetDataCallback . . . . . . . . . . 1025
26.5.12 BLUETOOTH_LE_CONFIG_PROTOCOL.RegisterSmpSetDataCallback . . . . . . . . . . 1028
26.5.13 BLUETOOTH_LE_CONFIG_PROTOCOL.RegisterLinkConnectCompleteCallback . . . . 1029
27 Network Protocols — VLAN, EAP, Wi-Fi and Supplicant 1031

27.1 VLAN Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
27.1.1 EFI_VLAN_CONFIG_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
27.1.2 EFI_VLAN_CONFIG_PROTOCOL.Set() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
27.1.3 EFI_VLAN_CONFIG_PROTOCOL.Find() . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
27.1.4 EFI_VLAN_CONFIG_PROTOCOL.Remove() . . . . . . . . . . . . . . . . . . . . . . . . 1034
27.2 EAP Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
27.2.1 EFI_EAP_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
27.2.2 EFI_EAP.SetDesiredAuthMethod() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
27.2.3 EFI_EAP.RegisterAuthMethod() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
27.2.4 EAPManagement Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
27.2.5 EFI_EAP_MANAGEMENT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
27.2.6 EFI_EAP_MANAGEMENT.GetSystemConﬁguration() . . . . . . . . . . . . . . . . . . . . 1038
27.2.7 EFI_EAP_MANAGEMENT.SetSystemConﬁguration() . . . . . . . . . . . . . . . . . . . . 1039
27.2.8 EFI_EAP_MANAGEMENT.InitializePort() . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
27.2.9 EFI_EAP_MANAGEMENT.UserLogon() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
27.2.10 EFI_EAP_MANAGEMENT.UserLogoff() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
27.2.11 EFI_EAP_MANAGEMENT.GetSupplicantStatus() . . . . . . . . . . . . . . . . . . . . . . 1041
27.2.12 EFI_EAP_MANAGEMENT.SetSupplicantConﬁguration() . . . . . . . . . . . . . . . . . . 1043
27.2.13 EFI_EAP_MANAGEMENT.GetSupplicantStatistics() . . . . . . . . . . . . . . . . . . . . 1043
27.2.14 EFI EAP Management2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
xxii27.2.14.1 EFI_EAP_MANAGEMENT2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 1045
27.2.15 EFI_EAP_MANAGEMENT2_PROTOCOL.GetKey() . . . . . . . . . . . . . . . . . . . . 1045
27.2.16 EFI EAP Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
27.2.16.1 EFI_EAP_CONFIGURATION_PROTOCOL . . . . . . . . . . . . . . . . . . . . 1046
27.2.17 EFI_EAP_CONFIGURATION_PROTOCOL.SetData() . . . . . . . . . . . . . . . . . . . . 1047
27.2.18 EFI_EAP_CONFIGURATION_PROTOCOL.GetData() . . . . . . . . . . . . . . . . . . . 1048
27.3 EFI Wireless MAC Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
27.3.1 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL . . . . . . . . . . . . . . . . . . . . 1049
27.3.2 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Scan() . . . . . . . . . . . . . . . . 1050
27.3.3 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Associate() . . . . . . . . . . . . . 1058
27.3.4 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Disassociate() . . . . . . . . . . . . 1061
27.3.5 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Authenticate() . . . . . . . . . . . . 1063
27.3.6 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Deauthenticate() . . . . . . . . . . 1066
27.4 EFI Wireless MAC Connection II Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
27.4.1 EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL . . . . . . . . . . . . . . . . . . 1068
27.4.2 EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL.GetNetworks() . . . . . . . . . . 1068
27.4.3 EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL.ConnectNetwork() . . . . . . . . 1072
27.4.4 EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL.DisconnectNetwork() . . . . . . 1074
27.5 EFI Supplicant Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
27.5.1 Supplicant Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
27.5.2 EFI_SUPPLICANT_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . 1075
27.5.3 Supplicant Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
27.5.4 EFI_SUPPLICANT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
27.5.5 EFI_SUPPLICANT_PROTOCOL.BuildResponsePacket() . . . . . . . . . . . . . . . . . . 1077
27.5.6 EFI_SUPPLICANT_PROTOCOL.ProcessPacket() . . . . . . . . . . . . . . . . . . . . . . 1078
27.5.7 EFI_SUPPLICANT_PROTOCOL.SetData() . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
27.5.8 EFI_SUPPLICANT_PROTOCOL.GetData() . . . . . . . . . . . . . . . . . . . . . . . . . 1083
28 Network Protocols — TCP, IP, IPsec, FTP, TLS and Conﬁgurations 1085
28.1 EFI TCPv4 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
28.1.1 TCP4 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
28.1.2 EFI_TCP4_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 1085
28.1.3 TCP4 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
28.1.4 EFI_TCP4_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
28.1.5 EFI_TCP4_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
28.1.6 EFI_TCP4_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
28.1.7 EFI_TCP4_PROTOCOL.Routes() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
28.1.8 EFI_TCP4_PROTOCOL.Connect() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
28.1.9 EFI_TCP4_PROTOCOL.Accept() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
28.1.10 EFI_TCP4_PROTOCOL.Transmit() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
28.1.10.1 EFI_TCP4_PROTOCOL.Receive() . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
28.1.11 EFI_TCP4_PROTOCOL.Close() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
28.1.12 EFI_TCP4_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
28.1.13 EFI_TCP4_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
28.2 EFI TCPv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
28.2.1 TCPv6 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
28.2.2 EFI_TCP6_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 1104
28.2.3 TCPv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
28.2.4 EFI_TCP6_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
28.2.5 EFI_TCP6_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
28.2.6 EFI_TCP6_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
28.2.7 EFI_TCP6_PROTOCOL.Connect() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
28.2.8 EFI_TCP6_PROTOCOL.Accept() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
28.2.9 EFI_TCP6_PROTOCOL.Transmit() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
xxiii28.2.10 EFI_TCP6_PROTOCOL.Receive() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
28.2.11 EFI_TCP6_PROTOCOL.Close() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
28.2.12 EFI_TCP6_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
28.2.13 EFI_TCP6_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
28.3 EFI IPv4 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
28.3.1 IP4 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
28.3.2 EFI_IP4_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 1122
28.3.3 IP4 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
28.3.4 EFI_IP4_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
28.3.5 EFI_IP4_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
28.3.6 EFI_IP4_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
28.3.7 EFI_IP4_PROTOCOL.Groups() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
28.3.8 EFI_IP4_PROTOCOL.Routes() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
28.3.9 EFI_IP4_PROTOCOL.Transmit() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
28.3.10 EFI_IP4_PROTOCOL.Receive() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
28.3.11 EFI_IP4_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
28.3.12 EFI_IP4_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136

28.4 EFI IPv4 Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
28.4.1 EFI_IP4_CONFIG_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
28.4.2 EFI_IP4_CONFIG_PROTOCOL.Start() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
28.4.3 EFI_IP4_CONFIG_PROTOCOL.Stop() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
28.4.4 EFI_IP4_CONFIG_PROTOCOL.GetData() . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
28.5 EFI IPv4 Conﬁguration II Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
28.5.1 EFI_IP4_CONFIG2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
28.5.2 EFI_IP4_CONFIG2_PROTOCOL.SetData() . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
28.5.3 EFI_IP4_CONFIG2_PROTOCOL.GetData() . . . . . . . . . . . . . . . . . . . . . . . . . 1145
28.5.4 EFI_IP4_CONFIG2_PROTOCOL.RegisterDataNotify () . . . . . . . . . . . . . . . . . . . 1146
28.5.5 EFI_IP4_CONFIG2_PROTOCOL.UnregisterDataNotify () . . . . . . . . . . . . . . . . . . 1147
28.6 EFI IPv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
28.6.1 IPv6 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
28.6.2 EFI_IP6_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 1148
28.6.3 IPv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
28.6.4 EFI_IP6_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
28.6.5 EFI_IP6_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
28.6.6 EFI_IP6_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
28.6.7 EFI_IP6_PROTOCOL.Groups() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156
28.6.8 EFI_IP6_PROTOCOL.Routes() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
28.6.9 EFI_IP6_PROTOCOL.Neighbors() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
28.6.10 EFI_IP6_PROTOCOL.Transmit() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
28.6.11 EFI_IP6_PROTOCOL.Receive() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
28.6.12 EFI_IP6_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
28.6.13 EFI_IP6_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
28.7 EFI IPv6 Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
28.7.1 EFI_IP6_CONFIG_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
28.7.2 EFI_IP6_CONFIG_PROTOCOL.SetData() . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
28.7.3 EFI_IP6_CONFIG_PROTOCOL.GetData() . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
28.7.4 EFI_IP6_CONFIG_PROTOCOL.RegisterDataNotify () . . . . . . . . . . . . . . . . . . . . 1171
28.7.5 EFI_IP6_CONFIG_PROTOCOL.UnregisterDataNotify() . . . . . . . . . . . . . . . . . . . 1172
28.8 IPsec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
28.8.1 IPsec Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
28.8.2 EFI IPsec Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
28.8.3 EFI_IPSEC_CONFIG_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
28.8.4 EFI_IPSEC_CONFIG_PROTOCOL.SetData() . . . . . . . . . . . . . . . . . . . . . . . . 1174
28.8.5 EFI_IPSEC_CONFIG_PROTOCOL.GetData() . . . . . . . . . . . . . . . . . . . . . . . . 1183
xxiv28.8.6 EFI_IPSEC_CONFIG_PROTOCOL.GetNextSelector() . . . . . . . . . . . . . . . . . . . . 1184
28.8.7 EFI_IPSEC_CONFIG_PROTOCOL.RegisterDataNotify () . . . . . . . . . . . . . . . . . . 1185
28.8.8 EFI_IPSEC_CONFIG_PROTOCOL.UnregisterDataNotify () . . . . . . . . . . . . . . . . . 1186
28.8.9 EFI IPsec Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
28.8.10 EFI_IPSEC_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
28.8.11 EFI_IPSEC_PROTOCOL.Process() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
28.8.12 EFI IPsec2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
28.8.13 EFI_IPSEC2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
28.8.14 EFI_IPSEC2_PROTOCOL.ProcessExt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
28.9 Network Protocol - EFI FTP Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
28.9.1 EFI_FTP4_SERVICE_BINDING_PROTOCOL Summary . . . . . . . . . . . . . . . . . . 1191
28.9.2 EFI_FTP4_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
28.9.3 EFI_FTP4_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
28.9.4 EFI_FTP4_PROTOCOL.Connect() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
28.9.5 EFI_FTP4_PROTOCOL.Close() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
28.9.6 EFI_FTP4_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
28.9.7 EFI_FTP4_PROTOCOL.ReadFile() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
28.9.8 EFI_FTP4_PROTOCOL.WriteFile() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
28.9.9 EFI_FTP4_PROTOCOL.ReadDirectory() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
28.9.10 EFI_FTP4_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
28.10 EFI TLS Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
28.10.1 EFI TLS Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
28.10.1.1 EFI_TLS_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . 1203
28.10.2 EFI TLS Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
28.10.2.1 EFI_TLS_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
28.10.3 EFI_TLS_PROTOCOL.SetSessionData () . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
28.10.4 EFI_TLS_PROTOCOL.GetSessionData () . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
28.10.5 EFI_TLS_PROTOCOL.BuildResponsePacket () . . . . . . . . . . . . . . . . . . . . . . . . 1209
28.10.6 EFI_TLS_PROTOCOL.ProcessPacket () . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
28.10.7 EFI TLS Conﬁguration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
28.10.7.1 EFI_TLS_CONFIGURATION_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 1212
28.10.8 EFI_TLS_CONFIGURATION_PROTOCOL.SetData() . . . . . . . . . . . . . . . . . . . . 1213
28.10.9 EFI_TLS_CONFIGURATION_PROTOCOL.GetData() . . . . . . . . . . . . . . . . . . . . 1214
29 Network Protocols — ARP, DHCP, DNS, HTTP and REST 1215
29.1 ARP Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
29.1.1 EFI_ARP_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 1215
29.1.2 EFI_ARP_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
29.1.3 EFI_ARP_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
29.1.4 EFI_ARP_PROTOCOL.Add() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
29.1.5 EFI_ARP_PROTOCOL.Find() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
29.1.6 EFI_ARP_PROTOCOL.Delete() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
29.1.7 EFI_ARP_PROTOCOL.Flush() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
29.1.8 EFI_ARP_PROTOCOL.Request() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
29.1.9 EFI_ARP_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
29.2 EFI DHCPv4 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
29.2.1 EFI_DHCP4_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . 1224
29.2.2 EFI_DHCP4_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
29.2.3 EFI_DHCP4_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
29.2.4 EFI_DHCP4_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
29.2.5 EFI_DHCP4_PROTOCOL.Start() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
29.2.6 EFI_DHCP4_PROTOCOL.RenewRebind() . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
29.2.7 EFI_DHCP4_PROTOCOL.Release() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236

29.2.8 EFI_DHCP4_PROTOCOL.Stop() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
xxv29.2.9 EFI_DHCP4_PROTOCOL.Build() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
29.2.10 EFI_DHCP4_PROTOCOL.TransmitReceive() . . . . . . . . . . . . . . . . . . . . . . . . . 1238
29.2.11 EFI_DHCP4_PROTOCOL.Parse() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
29.3 EFI DHCP6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
29.3.1 DHCP6 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
29.3.2 EFI_DHCP6_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . 1241
29.3.3 DHCP6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
29.3.4 EFI_DHCP6_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
29.3.5 EFI_DHCP6_PROTOCOL.GetModeData () . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
29.3.6 EFI_DHCP6_PROTOCOL.Conﬁgure () . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246
29.3.7 EFI_DHCP6_PROTOCOL.Start () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
29.3.8 EFI_DHCP6_PROTOCOL.InfoRequest () . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
29.3.9 EFI_DHCP6_PROTOCOL.RenewRebind () . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
29.3.10 EFI_DHCP6_PROTOCOL.Decline () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
29.3.11 EFI_DHCP6_PROTOCOL.Release () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
29.3.12 EFI_DHCP6_PROTOCOL.Stop () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
29.3.13 EFI_DHCP6_PROTOCOL.Parse () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
29.4 EFI DNSv4 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
29.4.1 EFI_DNS4_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 1258
29.4.2 EFI_DNS4_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
29.4.3 EFI_DNS4_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
29.4.4 EFI_DNS4_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
29.4.5 EFI_DNS4_PROTOCOL.HostNameToIp() . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
29.4.6 EFI_DNS4_PROTOCOL.IpToHostName() . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
29.4.7 EFI_DNS4_PROTOCOL.GeneralLookUp() . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
29.4.8 EFI_DNS4_PROTOCOL.UpdateDnsCache() . . . . . . . . . . . . . . . . . . . . . . . . . 1267
29.4.9 EFI_DNS4_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
29.4.10 EFI_DNS4_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
29.5 EFI DNSv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
29.5.1 DNS6 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
29.5.2 EFI_DNS6_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 1269
29.5.3 DNS6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
29.5.4 EFI_DNS6_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
29.5.5 EFI_DNS6_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
29.5.6 EFI_DNS6_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
29.5.7 EFI_DNS6_PROTOCOL.HostNameToIp() . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
29.5.8 EFI_DNS6_PROTOCOL.IpToHostName() . . . . . . . . . . . . . . . . . . . . . . . . . . 1276
29.5.9 EFI_DNS6_PROTOCOL.GeneralLookUp() . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
29.5.10 EFI_DNS6_PROTOCOL.UpdateDnsCache() . . . . . . . . . . . . . . . . . . . . . . . . . 1278
29.5.11 EFI_DNS6_PROTOCOL.POLL() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
29.5.12 EFI_DNS6_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
29.6 EFI HTTP Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
29.6.1 HTTP Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
29.6.1.1 EFI_HTTP_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . 1281
29.6.2 EFI HTTP Protocol Speciﬁc Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
29.6.3 EFI_HTTP_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
29.6.4 EFI_HTTP_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
29.6.5 EFI_HTTP_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
29.6.6 EFI_HTTP_PROTOCOL.Request() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285
29.6.7 EFI_HTTP_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
29.6.8 EFI_HTTP_PROTOCOL.Response() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
29.6.9 EFI_HTTP_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
29.6.9.1 Usage Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
29.6.10 HTTP Utilities Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
xxvi29.6.11 EFI_HTTP_UTILITIES_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
29.6.12 EFI_HTTP_UTILITIES_PROTOCOL.Build() . . . . . . . . . . . . . . . . . . . . . . . . . 1297
29.6.13 EFI_HTTP_UTILITIES_PROTOCOL.Parse() . . . . . . . . . . . . . . . . . . . . . . . . . 1298
29.7 EFI REST Support Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
29.7.1 EFI REST Support Scenario 1 (PlatformManagement) . . . . . . . . . . . . . . . . . . . . 1299
29.7.2 EFI REST Support Scenario 2 (PlatformManagement) . . . . . . . . . . . . . . . . . . . . 1303
29.7.3 EFI REST Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
29.7.3.1 EFI REST Protocol Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
29.7.4 EFI_REST_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
29.7.5 EFI_REST_PROTOCOL.SendReceive() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
29.7.6 EFI_REST_PROTOCOL.GetServiceTime() . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
29.7.7 EFI REST EX Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
29.7.7.1 REST EX Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
29.7.8 EFI_REST_EX_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 1306
29.7.8.1 REST EX Protocol Speciﬁc Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . 1307
29.7.9 EFI_REST_EX_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
29.7.10 EFI_REST_EX_PROTOCOL.SendReceive() . . . . . . . . . . . . . . . . . . . . . . . . . 1308
29.7.11 EFI_REST_EX_PROTOCOL.GetService() . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
29.7.12 EFI_REST_EX_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . 1312
29.7.13 EFI_REST_EX_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313
29.7.14 EFI_REST_EX_PROTOCOL.AsyncSendReceive() . . . . . . . . . . . . . . . . . . . . . . 1314
29.7.15 EFI_REST_EX_PROTOCOL.EventService() . . . . . . . . . . . . . . . . . . . . . . . . . 1316
29.7.15.1 Usage Example (HTTP-aware REST EX Protocol DriverInstance) . . . . . . . . . 1318
29.7.16 EFI_REST_EX_PROTOCOL.EventService() . . . . . . . . . . . . . . . . . . . . . . . . . 1322
29.7.17 EFI REST JSON Resource to C Structure Converter . . . . . . . . . . . . . . . . . . . . . . 1322
29.7.17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322
29.7.17.2 EFI REST JSON Structure Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 1325
29.7.18 EFI_REST_JSON_STRUCTURE.Register () . . . . . . . . . . . . . . . . . . . . . . . . . 1326
29.7.19 EFI_REST_JSON_STRUCTURE.ToStructure () . . . . . . . . . . . . . . . . . . . . . . . 1328
29.7.20 EFI_REST_JSON_STRUCTURE.ToJson () . . . . . . . . . . . . . . . . . . . . . . . . . . 1329
29.7.21 EFI_REST_JSON_STRUCTURE.DestroyStructure () . . . . . . . . . . . . . . . . . . . . . 1330
29.7.21.1 EFI Redﬁsh JSON Structure Converter . . . . . . . . . . . . . . . . . . . . . . . . 1331
30 Network Protocols — UDP and MTFTP 1332
30.1 EFI UDP Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
30.1.1 UDP4 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332

30.1.1.1 EFI_UDP4_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . 1332
30.1.2 UDP4 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
30.1.2.1 EFI_UDP4_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
30.1.2.2 EFI_UDP4_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . 1334
30.1.2.3 EFI_UDP4_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . 1336
30.1.2.4 EFI_UDP4_PROTOCOL.Groups() . . . . . . . . . . . . . . . . . . . . . . . . . . 1337
30.1.2.5 EFI_UDP4_PROTOCOL.Routes() . . . . . . . . . . . . . . . . . . . . . . . . . . 1338
30.1.2.6 EFI_UDP4_PROTOCOL.Transmit() . . . . . . . . . . . . . . . . . . . . . . . . . 1339
30.1.2.7 EFI_UDP4_PROTOCOL.Receive() . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
30.1.2.8 EFI_UDP4_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
30.1.2.9 EFI_UDP4_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
30.2 EFI UDPv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
30.2.1 UDP6 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
30.2.1.1 EFI_UDP6_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . 1346
30.2.2 EFI UDP6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
30.2.2.1 EFI_UDP6_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
30.2.2.2 EFI_UDP6_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . 1347
30.2.2.3 EFI_UDP6_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . 1349
xxvii30.2.2.4 EFI_UDP6_PROTOCOL.Groups() . . . . . . . . . . . . . . . . . . . . . . . . . . 1350
30.2.2.5 EFI_UDP6_PROTOCOL.Transmit() . . . . . . . . . . . . . . . . . . . . . . . . . 1351
30.2.2.6 EFI_UDP6_PROTOCOL.Receive() . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
30.2.2.7 EFI_UDP6_PROTOCOL.Cancel() . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
30.2.2.8 EFI_UDP6_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
30.3 EFI MTFTPv4 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
30.3.1 EFI_MTFTP4_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . 1357
30.3.2 EFI_MTFTP4_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
30.3.3 EFI_MTFTP4_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . . . . . 1359
30.3.4 EFI_MTFTP4_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
30.3.5 EFI_MTFTP4_PROTOCOL.GetInfo() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
30.3.6 EFI_MTFTP4_PROTOCOL.ParseOptions() . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
30.3.7 EFI_MTFTP4_PROTOCOL.ReadFile() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
30.3.8 EFI_MTFTP4_PROTOCOL.WriteFile() . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
30.3.9 EFI_MTFTP4_PROTOCOL.ReadDirectory() . . . . . . . . . . . . . . . . . . . . . . . . . 1375
30.3.10 EFI_MTFTP4_PROTOCOL.POLL() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376
30.4 EFI MTFTPv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
30.4.1 MTFTP6 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
30.4.1.1 EFI_MTFTP6_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . 1377
30.4.2 MTFTP6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
30.4.2.1 EFI_MTFTP6_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
30.4.2.2 EFI_MTFTP6_PROTOCOL.GetModeData() . . . . . . . . . . . . . . . . . . . . . 1379
30.4.2.3 EFI_MTFTP6_PROTOCOL.Conﬁgure() . . . . . . . . . . . . . . . . . . . . . . . 1380
30.4.2.4 EFI_MTFTP6_PROTOCOL.GetInfo() . . . . . . . . . . . . . . . . . . . . . . . . 1381
30.4.2.5 EFI_MTFTP6_PROTOCOL.ParseOptions() . . . . . . . . . . . . . . . . . . . . . 1387
30.4.2.6 EFI_MTFTP6_PROTOCOL.ReadFile() . . . . . . . . . . . . . . . . . . . . . . . 1388
30.4.2.7 EFI_MTFTP6_PROTOCOL.WriteFile() . . . . . . . . . . . . . . . . . . . . . . . 1392
30.4.2.8 EFI_MTFTP6_PROTOCOL.ReadDirectory() . . . . . . . . . . . . . . . . . . . . 1393
30.4.2.9 EFI_MTFTP6_PROTOCOL.Poll() . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
31 EFI Redﬁsh Service Support 1396
31.1 EFI Redﬁsh Discover Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396
31.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396
31.1.2 EFI Redﬁsh Discover Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
31.1.3 EFI Redﬁsh Discover Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
31.1.4 EFI Redﬁsh Discover Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
31.1.4.1 EFI_REDFISH_DISCOVER_PROTOCOL.GetNetworkInterfaceList() . . . . . . . 1400
31.1.4.2 EFI_REDFISH_DISCOVER_PROTOCOL.AcquireRedﬁshService() . . . . . . . . 1401
31.1.4.3 EFI_REDFISH_DISCOVER_PROTOCOL.AbortAcquireRedﬁshService() . . . . . 1405
31.1.4.4 EFI_REDFISH_DISCOVER_PROTOCOL.ReleaseRedﬁshService() . . . . . . . . 1406
31.1.5 Implementation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
31.1.5.1 Processes to Discover Redﬁsh Services . . . . . . . . . . . . . . . . . . . . . . . . 1407
31.1.5.2 Network Interface Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
31.2 EFI Redﬁsh JSON Structure Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
31.2.1 The Guidance of Writing EFI Redﬁsh JSONStructure Converter . . . . . . . . . . . . . . . 1408
31.2.2 The Guidance of Using EFI Redﬁsh JSON Structure Converter . . . . . . . . . . . . . . . . 1410
32 Secure Boot and Driver Signing 1411
32.1 Secure Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
32.1.1 EFI_AUTHENTICATION_INFO_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 1411
32.1.2 EFI_AUTHENTICATION_INFO_PROTOCOL.Get() . . . . . . . . . . . . . . . . . . . . . 1412
32.1.3 EFI_AUTHENTICATION_INFO_PROTOCOL.Set() . . . . . . . . . . . . . . . . . . . . . 1412
32.1.4 Authentication Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
32.1.5 Generic Authentication Node Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
xxviii32.1.6 CHAP (using RADIUS) Authentication Node . . . . . . . . . . . . . . . . . . . . . . . . . 1413
32.2 UEFI Driver Signing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
32.2.1 Digital Signatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
32.2.2 Embedded Signatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
32.2.3 Creating Image Digests from Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
32.2.4 Code Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
32.2.4.1 WIN_CERTIFICATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
32.2.4.2 WIN_CERTIFICATE_EFI_PKCS1_15 . . . . . . . . . . . . . . . . . . . . . . . . 1420
32.2.4.3 WIN_CERTIFICATE_UEFI_GUID . . . . . . . . . . . . . . . . . . . . . . . . . 1421
32.3 Firmware/OS Key Exchange: Creating Trust Relationships . . . . . . . . . . . . . . . . . . . . . . . 1422
32.3.1 Enrolling The Platform Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
32.3.2 Clearing The Platform Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
32.3.3 Transitioning to Audit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
32.3.4 Transitioning to Deployed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
32.3.5 Enrolling Key Exchange Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
32.3.6 Platform Firmware Key Storage Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 1425
32.4 Firmware/OS Key Exchange: Passing Public Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
32.4.1 Signature Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
32.4.1.1 EFI_SIGNATURE_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
32.4.2 Image Execution Information Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
32.5 Firmware/OS Crypto Algorithm Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432
32.6 UEFI Image Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433

32.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
32.6.2 Authorized User . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
32.6.3 Signature Database Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
32.6.3.1 Using The Image Execution Information Table . . . . . . . . . . . . . . . . . . . . 1435
32.6.3.2 Firmware Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437
32.6.3.3 Authorization Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437
32.7 Device Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
32.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
32.7.2 Authorized User . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
32.7.3 Device Signature Database Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
32.8 Code Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
32.8.1 UEFI Image Variable GUID & Variable Name . . . . . . . . . . . . . . . . . . . . . . . . . 1440
32.8.2 UEFI Device Signature Variable GUID and Variable Name . . . . . . . . . . . . . . . . . . 1441
33 Human Interface Infrastructure Overview 1442
33.1 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442
33.2 Design Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443
33.2.1 Drivers And Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444
33.2.1.1 Platform and Driver Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . 1444
33.2.1.2 Pre-O/S applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444
33.2.1.3 Description of User Interface Components . . . . . . . . . . . . . . . . . . . . . . 1444
33.2.1.4 Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444
33.2.1.5 Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448
33.2.1.6 Images/Fonts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448
33.2.1.7 Consumers of the user interface data . . . . . . . . . . . . . . . . . . . . . . . . . 1448
33.2.1.8 Connected forms browser/processor . . . . . . . . . . . . . . . . . . . . . . . . . 1448
33.2.1.9 Disconnected Forms Browser/Processor . . . . . . . . . . . . . . . . . . . . . . . 1448
33.2.1.10 O/S-Present Forms Browser/Processor . . . . . . . . . . . . . . . . . . . . . . . . 1449
33.2.1.11 Where are the Results Stored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
33.2.2 Localization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
33.2.3 User Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
33.2.4 Keyboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
xxix33.2.4.1 Keyboard Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
33.2.4.2 Modiﬁer Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
33.2.4.3 Non-Spacing Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
33.2.5 Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454
33.2.5.1 Form Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
33.2.5.2 Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
33.2.5.3 Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458
33.2.5.4 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
33.2.5.5 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
33.2.5.6 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
33.2.5.7 Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471
33.2.5.8 Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473
33.2.5.9 Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474
33.2.5.10 Forms Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475
33.2.5.11 Forms Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476
33.2.5.12 Forms Processing & Security Privileges . . . . . . . . . . . . . . . . . . . . . . . 1477
33.2.6 Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
33.2.6.1 Conﬁguration Language Paradigm . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
33.2.6.2 Unicode Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
33.2.7 Fonts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
33.2.7.1 Font Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
33.2.7.2 Limiting Glyphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
33.2.7.3 Fixed Font Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
33.2.7.4 Proportional Fonts Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
33.2.8 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
33.2.8.1 Converting to a 32-bit Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
33.2.8.2 Non-TrueColor Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
33.2.9 HII Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
33.2.10 Forms Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
33.2.10.1 User Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
33.2.11 Conﬁguration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
33.2.11.1 OS Runtime Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
33.2.11.2 Working with a UEFI Conﬁguration Language . . . . . . . . . . . . . . . . . . . . 1494
33.2.12 Form Callback Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
33.2.13 Driver Model Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
33.2.14 Human Interface Component Interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
33.2.15 Standards Map Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
33.2.15.1 Create A Question’s Value By Combing MultipleConﬁguration Settings . . . . . . 1501
33.2.15.2 Changing Multiple Conﬁguration Settings FromOne Question’s Value . . . . . . . 1501
33.2.15.3 Value Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
33.2.15.4 Prompts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
33.3 Code Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
33.3.1 Package Lists and Package Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
33.3.1.1 EFI_HII_PACKAGE_HEADER . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
33.3.1.2 EFI_HII_PACKAGE_LIST_HEADER . . . . . . . . . . . . . . . . . . . . . . . . 1504
33.3.2 Simpliﬁed Font Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
33.3.2.1 EFI_HII_SIMPLE_FONT_PACKAGE_HDR . . . . . . . . . . . . . . . . . . . . 1505
33.3.2.2 EFI_NARROW_GLYPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
33.3.2.3 EFI_WIDE_GLYPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
33.3.3 Font Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
33.3.3.1 Fixed Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
33.3.3.2 Glyph Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
33.3.4 Device Path Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
33.3.5 GUID Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
xxx33.3.6 String Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
33.3.6.1 Fixed Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518

33.3.6.2 String Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
33.3.6.3 String Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530
33.3.7 Image Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530
33.3.7.1 Fixed Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530
33.3.7.2 Image Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
33.3.7.3 Palette Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542
33.3.8 Forms Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
33.3.8.1 Binary Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
33.3.8.2 Standard Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545
33.3.8.3 Opcode Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
33.3.9 Keyboard Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
33.3.10 Animations Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
33.3.10.1 Animated Images Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
33.3.10.2 Animation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
34 HII Protocols 1621
34.1 Font Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
34.1.1 EFI_HII_FONT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
34.1.2 EFI_HII_FONT_PROTOCOL.StringToImage() . . . . . . . . . . . . . . . . . . . . . . . . 1622
34.1.3 EFI_HII_FONT_PROTOCOL.StringIdToImage() . . . . . . . . . . . . . . . . . . . . . . . 1624
34.1.4 EFI_HII_FONT_PROTOCOL.GetGlyph() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
34.1.5 EFI_HII_FONT_PROTOCOL.GetFontInfo() . . . . . . . . . . . . . . . . . . . . . . . . . 1626
34.2 EFI HII Font Ex Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
34.2.1 EFI_HII_FONT_EX_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
34.2.2 EFI_HII_FONT_EX_PROTOCOL.StringToImageEx() . . . . . . . . . . . . . . . . . . . . 1628
34.2.3 EFI_HII_FONT_EX_PROTOCOL.StringIdToImageEx() . . . . . . . . . . . . . . . . . . . 1629
34.2.4 EFI_HII_FONT_EX_PROTOCOL.GetGlyphEx() . . . . . . . . . . . . . . . . . . . . . . . 1629
34.2.5 EFI_HII_FONT_EX_PROTOCOL.GetFontInfoEx() . . . . . . . . . . . . . . . . . . . . . 1630
34.2.6 EFI_HII_FONT_EX_PROTOCOL.GetGlyphInfo() . . . . . . . . . . . . . . . . . . . . . . 1630
34.2.7 Code Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
34.2.7.1 EFI_FONT_DISPLAY_INFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
34.2.7.2 EFI_IMAGE_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
34.3 String Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
34.3.1 EFI_HII_STRING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
34.3.2 EFI_HII_STRING_PROTOCOL.NewString() . . . . . . . . . . . . . . . . . . . . . . . . . 1634
34.3.3 EFI_HII_STRING_PROTOCOL.GetString() . . . . . . . . . . . . . . . . . . . . . . . . . 1635
34.3.4 EFI_HII_STRING_PROTOCOL.SetString() . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
34.3.5 EFI_HII_STRING_PROTOCOL.GetLanguages() . . . . . . . . . . . . . . . . . . . . . . . 1637
34.3.6 EFI_HII_STRING_PROTOCOL.GetSecondaryLanguages() . . . . . . . . . . . . . . . . . 1638
34.4 Image Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
34.4.1 EFI_HII_IMAGE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
34.4.2 EFI_HII_IMAGE_PROTOCOL.NewImage() . . . . . . . . . . . . . . . . . . . . . . . . . 1639
34.4.3 EFI_HII_IMAGE_PROTOCOL.GetImage() . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
34.4.4 EFI_HII_IMAGE_PROTOCOL.SetImage() . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
34.4.5 EFI_HII_IMAGE_PROTOCOL.DrawImage() . . . . . . . . . . . . . . . . . . . . . . . . . 1642
34.4.6 EFI_HII_IMAGE_PROTOCOL.DrawImageId() . . . . . . . . . . . . . . . . . . . . . . . . 1643
34.5 EFI HII Image Ex Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
34.5.1 EFI_HII_IMAGE_EX_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
34.5.2 EFI_HII_IMAGE_EX_PROTOCOL.NewImageEx() . . . . . . . . . . . . . . . . . . . . . 1645
34.5.3 EFI_HII_IMAGE_EX_PROTOCOL.GetImageEx() . . . . . . . . . . . . . . . . . . . . . . 1645
34.5.4 EFI_HII_IMAGE_EX_PROTOCOL.SetImageEx() . . . . . . . . . . . . . . . . . . . . . . 1646
34.5.5 EFI_HII_IMAGE_EX_PROTOCOL.DrawImageEx() . . . . . . . . . . . . . . . . . . . . . 1646
xxxi34.5.6 EFI_HII_IMAGE_EX_PROTOCOL.DrawImageIdEx() . . . . . . . . . . . . . . . . . . . . 1647
34.5.7 EFI_HII_IMAGE_EX_PROTOCOL.GetImageInfo() . . . . . . . . . . . . . . . . . . . . . 1647
34.6 EFI HII Image Decoder Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
34.6.1 EFI_HII_IMAGE_DECODER_PROTOCOL.DecodeImage() . . . . . . . . . . . . . . . . . 1648
34.6.2 EFI_HII_IMAGE_DECODER_PROTOCOL.GetImageDecoderName() . . . . . . . . . . . 1650
34.6.3 EFI_HII_IMAGE_DECODER_PROTOCOL.GetImageInfo() . . . . . . . . . . . . . . . . . 1651
34.6.4 EFI_HII_IMAGE_DECODER_PROTOCOL.Decode() . . . . . . . . . . . . . . . . . . . . 1653
34.7 Font Glyph Generator Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
34.7.1 EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL . . . . . . . . . . . . . . . . . . . . 1654
34.7.2 EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL.GenerateGlyph() . . . . . . . . . . 1655
34.7.3 EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL.GenerateGlyphImage() . . . . . . . 1655
34.8 Database Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
34.8.1 EFI_HII_DATABASE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
34.8.2 EFI_HII_DATABASE_PROTOCOL.NewPackageList() . . . . . . . . . . . . . . . . . . . . 1657
34.8.3 EFI_HII_DATABASE_PROTOCOL.RemovePackageList() . . . . . . . . . . . . . . . . . . 1658
34.8.4 EFI_HII_DATABASE_PROTOCOL.UpdatePackageList() . . . . . . . . . . . . . . . . . . 1659
34.8.5 EFI_HII_DATABASE_PROTOCOL.ListPackageLists() . . . . . . . . . . . . . . . . . . . . 1660
34.8.6 EFI_HII_DATABASE_PROTOCOL.ExportPackageLists() . . . . . . . . . . . . . . . . . . 1661
34.8.7 EFI_HII_DATABASE_PROTOCOL.RegisterPackageNotify() . . . . . . . . . . . . . . . . 1661
34.8.8 EFI_HII_DATABASE_PROTOCOL.UnregisterPackageNotify() . . . . . . . . . . . . . . . 1663
34.8.9 EFI_HII_DATABASE_PROTOCOL.FindKeyboardLayouts() . . . . . . . . . . . . . . . . . 1663
34.8.10 EFI_HII_DATABASE_PROTOCOL.GetKeyboardLayout() . . . . . . . . . . . . . . . . . . 1664
34.8.11 EFI_HII_DATABASE_PROTOCOL.SetKeyboardLayout() . . . . . . . . . . . . . . . . . . 1668
34.8.12 EFI_HII_DATABASE_PROTOCOL.GetPackageListHandle() . . . . . . . . . . . . . . . . 1669
34.8.13 Database Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
34.8.13.1 EFI_HII_DATABASE_NOTIFY . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
34.8.14 EFI_HII_DATABASE_NOTIFY_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
35 HII Conﬁguration Processing and Browser Protocol 1671
35.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
35.1.1 Common Conﬁguration Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
35.1.2 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
35.2 Conﬁguration Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
35.2.1 String Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
35.2.1.1 Basic forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
35.2.1.2 Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
35.2.1.3 Routing elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
35.2.1.4 Body elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
35.2.1.5 Conﬁguration strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
35.2.1.6 Keyword strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
35.2.2 String Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677

35.3 EFI Conﬁguration Keyword Handler Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677
35.3.1 EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL . . . . . . . . . . . . . . . . . . . . 1678
35.3.2 EFI_KEYWORD_HANDLER _PROTOCOL.SetData() . . . . . . . . . . . . . . . . . . . . 1678
35.3.3 EFI_KEYWORD_HANDLER _PROTOCOL.GetData() . . . . . . . . . . . . . . . . . . . 1680
35.4 EFI HII Conﬁguration Routing Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1681
35.4.1 EFI_HII_CONFIG_ROUTING_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 1681
35.4.2 EFI_HII_CONFIG_ROUTING_PROTOCOL.ExtractConﬁg() . . . . . . . . . . . . . . . . 1682
35.4.3 EFI_HII_CONFIG_ROUTING_PROTOCOL.ExportConﬁg() . . . . . . . . . . . . . . . . . 1683
35.4.4 EFI_HII_CONFIG_ROUTING_PROTOCOL.RouteConﬁg() . . . . . . . . . . . . . . . . . 1684
35.4.5 EFI_HII_CONFIG_ROUTING_PROTOCOL.BlockToConﬁg() . . . . . . . . . . . . . . . . 1685
35.4.6 EFI_HII_CONFIG_ROUTING_PROTOCOL.ConﬁgToBlock() . . . . . . . . . . . . . . . . 1686
35.4.7 EFI_HII_CONFIG_ROUTING_PROTOCOL.GetAltCfg() . . . . . . . . . . . . . . . . . . 1687
35.5 EFI HII Conﬁguration Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
xxxii35.5.1 EFI_HII_CONFIG_ACCESS_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
35.5.2 EFI_HII_CONFIG_ACCESS_PROTOCOL.ExtractConﬁg() . . . . . . . . . . . . . . . . . 1689
35.5.3 EFI_HII_CONFIG_ACCESS_PROTOCOL.RouteConﬁg() . . . . . . . . . . . . . . . . . . 1691
35.5.4 EFI_HII_CONFIG_ACCESS_PROTOCOL.CallBack() . . . . . . . . . . . . . . . . . . . . 1692
35.6 Form Browser Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
35.6.1 EFI_FORM_BROWSER2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
35.6.2 EFI_FORM_BROWSER2_PROTOCOL.SendForm() . . . . . . . . . . . . . . . . . . . . . 1696
35.6.3 EFI_FORM_BROWSER2_PROTOCOL.BrowserCallback() . . . . . . . . . . . . . . . . . 1698
35.7 HII Popup Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
35.7.1 EFI_HII_POPUP_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
35.7.2 EFI_HII_POPUP_PROTOCOL.CreatePopup() . . . . . . . . . . . . . . . . . . . . . . . . 1700
36 User Identiﬁcation 1702
36.1 User Identiﬁcation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
36.1.1 User Identify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
36.1.2 User Proﬁles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
36.1.2.1 User Proﬁle Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
36.1.2.2 User Identiﬁcation Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
36.1.3 Credential Providers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
36.1.4 Security Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
36.1.5 Deferred Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
36.2 User Identiﬁcation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
36.2.1 User Identiﬁcation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
36.2.2 Changing The Current User Proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
36.2.3 Ready To Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
36.3 Code Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
36.3.1 User Manager Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
36.3.1.1 EFI_USER_MANAGER_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . 1709
36.3.1.2 EFI_USER_MANAGER_PROTOCOL.Create() . . . . . . . . . . . . . . . . . . . 1710
36.3.1.3 EFI_USER_MANAGER_PROTOCOL.Delete() . . . . . . . . . . . . . . . . . . . 1710
36.3.1.4 EFI_USER_MANAGER_PROTOCOL.GetNext() . . . . . . . . . . . . . . . . . . 1711
36.3.1.5 EFI_USER_MANAGER_PROTOCOL.Current() . . . . . . . . . . . . . . . . . . 1712
36.3.1.6 EFI_USER_MANAGER_PROTOCOL.Identify() . . . . . . . . . . . . . . . . . . 1712
36.3.1.7 EFI_USER_MANAGER_PROTOCOL.Find() . . . . . . . . . . . . . . . . . . . . 1713
36.3.1.8 EFI_USER_MANAGER_PROTOCOL.Notify() . . . . . . . . . . . . . . . . . . . 1714
36.3.1.9 EFI_USER_MANAGER_PROTOCOL.GetInfo() . . . . . . . . . . . . . . . . . . 1715
36.3.1.10 EFI_USER_MANAGER_PROTOCOL.SetInfo() . . . . . . . . . . . . . . . . . . . 1716
36.3.1.11 EFI_USER_MANAGER_PROTOCOL.DeleteInfo() . . . . . . . . . . . . . . . . . 1717
36.3.1.12 EFI_USER_MANAGER_PROTOCOL.GetNextInfo() . . . . . . . . . . . . . . . . 1718
36.3.2 Credential Provider Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
36.3.2.1 EFI_USER_CREDENTIAL2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 1718
36.3.2.2 EFI_USER_CREDENTIAL2_PROTOCOL.Enroll() . . . . . . . . . . . . . . . . . 1720
36.3.2.3 EFI_USER_CREDENTIAL2_PROTOCOL.Form() . . . . . . . . . . . . . . . . . 1721
36.3.2.4 EFI_USER_CREDENTIAL2_PROTOCOL.Tile() . . . . . . . . . . . . . . . . . . 1721
36.3.2.5 EFI_USER_CREDENTIAL2_PROTOCOL.Title() . . . . . . . . . . . . . . . . . . 1722
36.3.2.6 EFI_USER_CREDENTIAL2_PROTOCOL.User() . . . . . . . . . . . . . . . . . . 1723
36.3.2.7 EFI_USER_CREDENTIAL2_PROTOCOL.Select() . . . . . . . . . . . . . . . . . 1724
36.3.2.8 EFI_USER_CREDENTIAL2_PROTOCOL.Deselect() . . . . . . . . . . . . . . . . 1725
36.3.2.9 EFI_USER_CREDENTIAL2_PROTOCOL.Default() . . . . . . . . . . . . . . . . 1725
36.3.2.10 EFI_USER_CREDENTIAL2_PROTOCOL.GetInfo() . . . . . . . . . . . . . . . . 1726
36.3.2.11 EFI_USER_CREDENTIAL2_PROTOCOL.GetNextInfo() . . . . . . . . . . . . . 1726
36.3.2.12 EFI_USER_CREDENTIAL2_PROTOCOL.Delete() . . . . . . . . . . . . . . . . . 1727
36.3.3 Deferred Image Load Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
36.3.3.1 EFI_DEFERRED_IMAGE_LOAD_PROTOCOL . . . . . . . . . . . . . . . . . . 1728
xxxiii36.3.3.2 EFI_DEFERRED_IMAGE_LOAD_PROTOCOL.GetImageInfo() . . . . . . . . . . 1728
36.4 User Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
36.4.1 EFI_USER_INFO_ACCESS_POLICY_RECORD . . . . . . . . . . . . . . . . . . . . . . 1730
36.4.1.1 EFI_USER_INFO_ACCESS_FORBID_LOAD . . . . . . . . . . . . . . . . . . . 1730
36.4.1.2 EFI_USER_INFO_ACCESS_PERMIT_LOAD . . . . . . . . . . . . . . . . . . . 1731
36.4.1.3 EFI_USER_INFO_ACCESS_ENROLL_SELF . . . . . . . . . . . . . . . . . . . . 1731
36.4.1.4 EFI_USER_INFO_ACCESS_ENROLL_OTHERS . . . . . . . . . . . . . . . . . . 1731
36.4.1.5 EFI_USER_INFO_ACCESS_MANAGE . . . . . . . . . . . . . . . . . . . . . . . 1732
36.4.1.6 EFI_USER_INFO_ACCESS_SETUP . . . . . . . . . . . . . . . . . . . . . . . . 1732
36.4.1.7 EFI_USER_INFO_ACCESS_FORBID_CONNECT . . . . . . . . . . . . . . . . . 1733
36.4.1.8 EFI_USER_INFO_ACCESS_PERMIT_CONNECT . . . . . . . . . . . . . . . . . 1733
36.4.1.9 EFI_USER_INFO_ACCESS_BOOT_ORDER . . . . . . . . . . . . . . . . . . . . 1733
36.4.2 EFI_USER_INFO_CBEFF_RECORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
36.4.3 EFI_USER_INFO_CREATE_DATE_RECORD . . . . . . . . . . . . . . . . . . . . . . . . 1734
36.4.4 EFI_USER_INFO_CREDENTIAL_PROVIDER_RECORD . . . . . . . . . . . . . . . . . 1734
36.4.5 EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME_RECORD . . . . . . . . . . . . . 1735
36.4.6 EFI_USER_INFO_CREDENTIAL_TYPE_RECORD . . . . . . . . . . . . . . . . . . . . 1735
36.4.7 EFI_USER_INFO_CREDENTIAL_TYPE_NAME_RECORD . . . . . . . . . . . . . . . . 1735
36.4.8 EFI_USER_INFO_GUID_RECORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
36.4.9 EFI_USER_INFO_FAR_RECORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
36.4.10 EFI_USER_INFO_IDENTIFIER_RECORD . . . . . . . . . . . . . . . . . . . . . . . . . 1736
36.4.11 EFI_USER_INFO_IDENTITY_POLICY_RECORD . . . . . . . . . . . . . . . . . . . . . 1737
36.4.12 EFI_USER_INFO_NAME_RECORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
36.4.13 EFI_USER_INFO_PKCS11_RECORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
36.4.14 EFI_USER_INFO_RETRY_RECORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
36.4.15 EFI_USER_INFO_USAGE_DATE_RECORD . . . . . . . . . . . . . . . . . . . . . . . . 1739
36.4.16 EFI_USER_INFO_USAGE_COUNT_RECORD . . . . . . . . . . . . . . . . . . . . . . . 1739
36.5 User Information Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
37 Secure Technologies 1741
37.1 Hash Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1741

37.1.1 Hash References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1741
37.1.1.1 EFI_HASH_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . 1741
37.1.1.2 EFI_HASH_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
37.1.1.3 EFI_HASH_PROTOCOL.GetHashSize() . . . . . . . . . . . . . . . . . . . . . . . 1742
37.1.1.4 EFI_HASH_PROTOCOL.Hash() . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
37.1.2 Other Code Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
37.1.2.1 EFI_SHA1_HASH, EFI_SHA224_HASH, EFI_SHA256_HASH,EFI_SHA384_HASH,
EFI_SHA512HASH, EFI_MD5_HASH . . . . . . . . . . . . . . . . . . . . . . . 1744
37.1.2.2 EFI Hash Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
37.2 Hash2 Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
37.2.1 EFI Hash2 Service Binding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
37.2.1.1 EFI_HASH2_SERVICE_BINDING_PROTOCOL . . . . . . . . . . . . . . . . . . 1746
37.2.2 EFI Hash2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
37.2.2.1 EFI_HASH2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
37.2.2.2 EFI_HASH2_PROTOCOL.GetHashSize() . . . . . . . . . . . . . . . . . . . . . . 1749
37.2.2.3 EFI_HASH2_PROTOCOL.Hash() . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
37.2.2.4 EFI_HASH2_PROTOCOL.HashInit() . . . . . . . . . . . . . . . . . . . . . . . . 1750
37.2.2.5 EFI_HASH2_PROTOCOL.HashUpdate() . . . . . . . . . . . . . . . . . . . . . . 1751
37.2.2.6 EFI_HASH2_PROTOCOL.HashFinal() . . . . . . . . . . . . . . . . . . . . . . . 1752
37.2.3 Other Code Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
37.2.3.1 EFI_HASH2_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
37.3 Key Management Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
37.3.1 EFI_KEY_MANAGEMENT_SERVICE_PROTOCOL . . . . . . . . . . . . . . . . . . . . 1753
xxxiv37.3.2 EFI_KMS_PROTOCOL.GetServiceStatus() . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
37.3.2.1 EFI_KMS_PROTOCOL.RegisterClient() . . . . . . . . . . . . . . . . . . . . . . . 1763
37.3.2.2 EFI_KMS_PROTOCOL.CreateKey() . . . . . . . . . . . . . . . . . . . . . . . . . 1764
37.3.2.3 EFI_KMS_PROTOCOL.GetKey() . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
37.3.2.4 EFI_KMS_PROTOCOL.AddKey() . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
37.3.2.5 EFI_KMS_PROTOCOL.DeleteKey() . . . . . . . . . . . . . . . . . . . . . . . . . 1770
37.3.2.6 EFI_KMS_PROTOCOL.GetKeyAttributes() . . . . . . . . . . . . . . . . . . . . . 1771
37.3.2.7 EFI_KMS_PROTOCOL.AddKeyAttributes() . . . . . . . . . . . . . . . . . . . . . 1773
37.3.2.8 EFI_KMS_PROTOCOL.DeleteKeyAttributes() . . . . . . . . . . . . . . . . . . . 1775
37.3.2.9 EFI_KMS_PROTOCOL.GetKeyByAttributes() . . . . . . . . . . . . . . . . . . . 1777
37.4 PKCS7 Verify Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
37.4.1 EFI_PKCS7_VERIFY_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
37.4.2 EFI_PKCS7_VERIFY_PROTOCOL.VerifyBuffer() . . . . . . . . . . . . . . . . . . . . . . 1780
37.4.2.1 EFI_PKCS7_VERIFY_PROTOCOL.VerifySignature() . . . . . . . . . . . . . . . 1782
37.5 Random Number Generator Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
37.5.1 EFI_RNG_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
37.5.2 EFI_RNG_PROTOCOL.GetInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
37.5.3 EFI_RNG_PROTOCOL.GetRNG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
37.5.4 EFI RNG Algorithm Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787
37.5.5 RNG References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
37.6 Smart Card Reader and Smart Card Edge Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
37.6.1 Smart Card Reader Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
37.6.1.1 EFI_SMART_CARD_READER_PROTOCOL Summary . . . . . . . . . . . . . . 1788
37.6.2 EFI_SMART_CARD_READER_PROTOCOL.SCardConnect() . . . . . . . . . . . . . . . 1789
37.6.3 EFI_SMART_CARD_READER_PROTOCOL.SCardDisconnect() . . . . . . . . . . . . . . 1791
37.6.4 EFI_SMART_CARD_READER_PROTOCOL.SCardStatus() . . . . . . . . . . . . . . . . 1791
37.6.5 EFI_SMART_CARD_READER_PROTOCOL.SCardTransmit() . . . . . . . . . . . . . . . 1793
37.6.6 EFI_SMART_CARD_READER_PROTOCOL.SCardControl() . . . . . . . . . . . . . . . . 1794
37.6.7 EFI_SMART_CARD_READER_PROTOCOL.SCardGetAttrib() . . . . . . . . . . . . . . . 1795
37.6.8 Smart Card Edge Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
37.6.8.1 EFI_SMART_CARD_EDGE_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 1796
37.6.8.2 EFI_SMART_CARD_EDGE_PROTOCOL.GetContext() . . . . . . . . . . . . . . 1798
37.6.8.3 EFI_SMART_CARD_EDGE_PROTOCOL. Connect() . . . . . . . . . . . . . . . 1799
37.6.8.4 EFI_SMART_CARD_EDGE_PROTOCOL.Disconnect() . . . . . . . . . . . . . . 1800
37.6.8.5 EFI_SMART_CARD_EDGE_PROTOCOL.GetCsn . . . . . . . . . . . . . . . . . 1801
37.6.8.6 EFI_SMART_CARD_EDGE_PROTOCOL.GetReaderName . . . . . . . . . . . . 1801
37.6.8.7 EFI_SMART_CARD_EDGE_PROTOCOL.VerifyPin() . . . . . . . . . . . . . . . 1802
37.6.8.8 EFI_SMART_CARD_EDGE_PROTOCOL.GetPinRemaining() . . . . . . . . . . . 1803
37.6.8.9 EFI_SMART_CARD_EDGE_PROTOCOL.GetData() . . . . . . . . . . . . . . . . 1804
37.6.8.10 EFI_SMART_CARD_EDGE_PROTOCOL.GetCredentials() . . . . . . . . . . . . 1805
37.6.8.11 EFI_SMART_CARD_EDGE_PROTOCOL.SignData() . . . . . . . . . . . . . . . 1807
37.6.8.12 EFI_SMART_CARD_EDGE_PROTOCOL.DecryptData() . . . . . . . . . . . . . 1808
37.6.8.13 EFI_SMART_CARD_EDGE_PROTOCOL.BuildDHAgreement() . . . . . . . . . 1810
37.7 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
37.7.1 EFI_MEMORY_ATTRIBUTE PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
37.7.1.1 EFI_MEMORY_ATTRIBUTE_PROTOCOL.GetMemoryAttributes . . . . . . . . 1812
37.7.1.2 EFI_MEMORY_ATTRIBUTE_PROTOCOL.SetMemoryAttributes . . . . . . . . . 1812
37.7.1.3 EFI_MEMORY_ATTRIBUTE_PROTOCOL.ClearMemoryAttributes . . . . . . . . 1813
38 Conﬁdential Computing 1815
38.1 Virtual Platform CC Event Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
38.2 EFI_CC_MEASUREMENT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
38.2.1 EFI_CC_MEASUREMENT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
38.2.2 EFI_CC_MEASUREMENT_PROTOCOL.GetCapability . . . . . . . . . . . . . . . . . . . 1816
xxxv38.2.3 EFI_CC_PROTOCOL.GetEventLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1818
38.2.4 EFI_CC_MEASUREMENT_PROTOCOL.HashLogExtendEvent . . . . . . . . . . . . . . 1819
38.2.5 EFI_CC_MEASUREMENT_PROTOCOL.MapPcrToMrIndex . . . . . . . . . . . . . . . . 1821
38.3 EFI CC Final Events Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1821
38.4 Vendor Speciﬁc Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
38.4.1 Intel Trust Domain Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
39 Miscellaneous Protocols 1823
39.1 EFI Timestamp Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823
39.1.1 EFI_TIMESTAMP_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823
39.1.2 EFI_TIMESTAMP_PROTOCOL.GetTimestamp() . . . . . . . . . . . . . . . . . . . . . . 1823
39.1.3 EFI_TIMESTAMP_PROTOCOL.GetProperties() . . . . . . . . . . . . . . . . . . . . . . . 1824
39.2 Reset Notiﬁcation Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
39.2.1 EFI_RESET_NOTIFICATION_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . 1825
39.2.2 EFI_RESET_NOTIFICATION_PROTOCOL.RegisterResetNotify() . . . . . . . . . . . . . 1825
39.2.3 EFI_RESET_NOTIFICATION_PROTOCOL.UnregisterResetNotify() . . . . . . . . . . . . 1826
A GUID and Time Formats 1827
B Console 1829
B.1 EFI_SIMPLE_TEXT_INPUT_PROTOCOL and EFI_SIMPLE_TEXT _INPUT_EX_PROTOCOL . 1829
B.2 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL for PC ANSI or ANSI X3.64 terminals . . . . . . . . 1831
C Device Path Examples 1835
C.1 Example Computer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
C.2 Legacy Floppy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836

C.3 IDE Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1837
C.4 Secondary Root PCI Bus with PCI to PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838
C.5 ACPI Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839
C.6 EFI Device Path as a Name Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1840
D Status Codes 1841
E Universal Network Driver Interfaces 1844
E.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844
E.1.1 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844
E.1.2 Referenced Speciﬁcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846
E.1.3 OS Network Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1849
E.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
E.2.1 32/64-bit UNDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
E.2.1.1 Issuing UNDI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
E.2.2 UNDI Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
E.3 UNDI C Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857
E.3.1 Portability Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857
E.3.1.1 PXE_INTEL_ORDER or PXE_NETWORK_ORDER . . . . . . . . . . . . . . . . 1857
E.3.1.2 PXE_UINT64_SUPPORT or PXE_NO_UINT64_SUPPORT . . . . . . . . . . . . 1859
E.3.1.3 PXE_BUSTYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
E.3.1.4 PXE_SWAP_UINT16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
E.3.1.5 PXE_SWAP_UINT32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
E.3.1.6 PXE_SWAP_UINT64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
E.3.2 Miscellaneous Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
E.3.2.1 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
E.3.3 Portability Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
E.3.3.1 PXE_CONST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862
E.3.3.2 PXE_VOLATILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862
xxxviE.3.3.3 PXE_VOID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862
E.3.3.4 PXE_UINT8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862
E.3.3.5 PXE_UINT16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
E.3.3.6 PXE_UINT32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
E.3.3.7 PXE_UINT64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
E.3.3.8 PXE_UINTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
E.3.4 Simple Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
E.3.4.1 PXE_BOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
E.3.4.2 PXE_OPCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
E.3.4.3 PXE_OPFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
E.3.4.4 PXE_STATFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
E.3.4.5 PXE_STATCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1872
E.3.4.6 PXE_IFNUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1872
E.3.4.7 PXE_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873
E.3.4.8 PXE_FRAME_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873
E.3.4.9 PXE_IPV4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873
E.3.4.10 PXE_IPV6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
E.3.4.11 PXE_MAC_ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
E.3.4.12 PXE_IFTYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
E.3.4.13 PXE_MEDIA_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
E.3.5 Compound Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
E.3.5.1 PXE_HW_UNDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
E.3.5.2 PXE_SW_UNDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876
E.3.5.3 PXE_UNDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
E.3.5.4 PXE_CDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
E.3.5.5 PXE_IP_ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
E.3.5.6 PXE_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
E.4 UNDI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
E.4.1 Command Linking and Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881
E.4.2 Get State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
E.4.2.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
E.4.2.2 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1883
E.4.2.3 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1884
E.4.3 Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
E.4.3.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
E.4.3.2 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1885
E.4.3.3 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1889
E.4.3.4 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1889
E.4.4 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
E.4.4.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
E.4.4.2 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1890
E.4.4.3 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1890
E.4.5 Get Init Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
E.4.5.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
E.4.5.2 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1891
E.4.5.3 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1891
E.4.5.4 StatFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1892
E.4.5.5 DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1892
E.4.6 Get Conﬁg Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
E.4.6.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
E.4.6.2 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1894
E.4.6.3 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1894
E.4.6.4 DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
E.4.7 Initialize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
xxxviiE.4.7.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
E.4.7.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
E.4.7.3 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
E.4.7.4 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1898
E.4.7.5 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1898
E.4.7.6 StatFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
E.4.7.7 Before Using the DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1899
E.4.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1899
E.4.8.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1899

E.4.8.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
E.4.8.3 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1900
E.4.8.4 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1900
E.4.8.5 StatFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
E.4.9 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
E.4.9.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
E.4.9.2 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1901
E.4.9.3 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1902
E.4.10 Interrupt Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
E.4.10.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
E.4.10.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
E.4.10.3 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1903
E.4.10.4 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1903
E.4.10.5 StatFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
E.4.11 Receive Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904
E.4.11.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904
E.4.11.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904
E.4.11.3 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
E.4.11.4 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1905
E.4.11.5 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1905
E.4.11.6 StatFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
E.4.11.7 DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
E.4.12 Station Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
E.4.12.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
E.4.12.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
E.4.12.3 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
E.4.12.4 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1907
E.4.12.5 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1907
E.4.12.6 Before Using the DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
E.4.13 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
E.4.13.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
E.4.13.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
E.4.13.3 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1909
E.4.13.4 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1909
E.4.13.5 DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1909
E.4.14 MCast IP To MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
E.4.14.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
E.4.14.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
E.4.14.3 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
E.4.14.4 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1912
E.4.14.5 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1912
E.4.14.6 Before Using the DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
E.4.15 NvData . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
E.4.15.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
E.4.15.2 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
xxxviiiE.4.15.3 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1914
E.4.15.4 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1914
E.4.16 Get Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
E.4.16.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
E.4.16.2 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1916
E.4.16.3 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1916
E.4.16.4 StatFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916
E.4.16.5 Using the DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
E.4.17 Fill Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
E.4.17.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
E.4.17.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
E.4.17.3 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
E.4.17.4 Nonfragmented Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
E.4.17.5 Fragmented Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919
E.4.17.6 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1919
E.4.17.7 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1920
E.4.18 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920
E.4.18.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920
E.4.18.2 OpFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
E.4.18.3 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
E.4.18.4 Nonfragmented Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
E.4.18.5 Fragmented Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
E.4.18.6 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1922
E.4.18.7 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1922
E.4.19 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
E.4.19.1 Issuing the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
E.4.19.2 Preparing the CPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
E.4.19.3 Waiting for the Command to Execute . . . . . . . . . . . . . . . . . . . . . . . . . 1924
E.4.19.4 Checking Command Execution Results . . . . . . . . . . . . . . . . . . . . . . . . 1924
E.4.19.5 Using the DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1924
E.4.20 PXE 2.1 speciﬁcation wire protocol clariﬁcations . . . . . . . . . . . . . . . . . . . . . . . 1925
E.4.20.1 Issue #1-time-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925
E.4.20.2 Issue #2 - siaddr/option 54 precedence . . . . . . . . . . . . . . . . . . . . . . . . 1925
E.4.20.3 Issue #3 - PXE Vendor Options Existence . . . . . . . . . . . . . . . . . . . . . . 1925
F Using the Simple Pointer Protocol 1928
G Using the EFI Extended SCSI Pass Thru Protocol 1929
H Compression Source Code 1932
I Decompression Source Code 1961
J EFI Byte Code Virtual Machine Opcode List 1977
K Alphabetic Function Lists 1979
L EFI 1.10 Protocol Changes and Deprecation List 1980
L.1 Protocol and GUID Name Changes from EFI 1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1980
L.2 Deprecated Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1982
M Formats — Language Codes and Language Code Arrays 1983
M.1 Specifying individual language codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
M.1.1 Specifying language code arrays: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
xxxixN Common Platform Error Record (CPER) 1984
N.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984

N.2 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
N.2.1 Record Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985
N.2.1.1 Notiﬁcation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1988
N.2.1.2 Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990
N.2.2 Section Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
N.2.3 Non-standard Section Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994
N.2.4 Processor Error Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994
N.2.4.1 Generic Processor Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994
N.2.4.2 IA32/X64 Processor Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . 1997
N.2.4.3 IA64 Processor Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2006
N.2.4.4 ARM Processor Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2006
N.2.5 Memory Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2018
N.2.6 Memory Error Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
N.2.7 PCI Express Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2024
N.2.8 PCI/PCI-X Bus Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
N.2.9 PCI/PCI-X Component Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2027
N.2.10 Firmware Error Record Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
N.2.11 DMAr Error Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
N.2.11.1 DMAr Generic Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2029
N.2.11.2 Intel® VT for Directed I/O speciﬁc DMAr Error Section . . . . . . . . . . . . . . 2030
N.2.11.3 IOMMU Speciﬁc DMAr Error Section . . . . . . . . . . . . . . . . . . . . . . . . 2031
N.2.12 CCIX PER Log Error Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2031
N.2.13 Compute Express Link (CXL) Protocol Error Section . . . . . . . . . . . . . . . . . . . . . 2032
N.2.14 CXL Component Events Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2035
O UEFI ACPI Data Table 2037
O.1 Invocation method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2038
P Hardware Error Record Persistence Usage 2040
P.1 Determining space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2040
P.2 Saving Hardware error records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2040
P.3 Clearing error record variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2041
Q References 2042
Q.1 Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042
Q.2 Prerequisite Speciﬁcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
Q.2.1 ACPI Speciﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
Q.2.2 Additional Considerations for Itanium-BasedPlatforms . . . . . . . . . . . . . . . . . . . . 2048
R Glossary 2049
xlUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
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speciﬁcation to maintain an electronic version of this work accessible by its internal personnel, and to print a copy of
this speciﬁcation in hard copy form, in whole or in part, in each case solely for use by that person in connection with
the implementation of this Speciﬁcation, provided no modiﬁcation is made to the Speciﬁcation.
CONTENTS xliUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
List of Tables
Chapter 1
• Table 1.2 SI Preﬁxes
• Table 1.3 Binary Preﬁxes
Chapter 2
• Table 2.1 UEFI Image Memory Types
• Table 2.2 UEFI Runtime Services
• Table 2.3 Common UEFI Data Types
• Table 2.4 Modiﬁers for Common UEFI Data Types
• Table 2.5 Map EFI Cacheability Attributes to AArch64 Memory Types
• Table 2.6 Map UEFI Permission Attributes to ARM Paging Attributes
• Table 2.8 RV32 datatype alignment
• Table 2.9 RV64 datatype alignment
• Table 2.10 Register name and ABI name
• Table 2.11 UEFI Protocols
• Table 2.12 Required UEFI Implementation Elements
Chapter 3
• Table 3.3 Global Variables
• Table 3.4 UEFI Image Types
Chapter 4
• Table 4.1 Usage of Memory Attribute Deﬁnitions
Chapter 5
• Table 5.1 Legacy MBR
• Table 5.2 Legacy MBR Partition Record
• Table 5.3 Protective MBR
• Table 5.4 Protective MBR Partition Record protecting the entire disk*
• Table 5.6 GPT Partition Entry
• Table 5.7 Deﬁned GPT Partition Entry — Partition Type GUIDs
• Table 5.8 Deﬁned GPT Partition Entry - Attributes
Chapter 6
Chapter 7
• Table 7.1 Event, Timer, and Task Priority Functions
• Table 7.2 TPL Usage
• Table 7.3 TPL Restrictions
• Table 7.8 Memory Allocation Functions
• Table 7.9 Memory Type Usage before ExitBootServices()
CONTENTS xliiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Table 7.10 Memory Type Usage after ExitBootServices()
• Table 7.14 Protocol Interface Functions
• Table 7.30 Image Type Differences Summary
• Table 7.31 Image Functions
• Table 7.37 Miscellaneous Boot Services Functions
Chapter 8
• Table 8.1 Rules for Reentry Into Runtime Services
• Table 8.2 Functions that may be called after Machine Check, INIT and NMI
• Table 8.3 Variable Services Functions
• Table 8.8 Hardware Error Record Persistence Variables
• Table 8.9 Time Services Functions
• Table 8.14 Virtual Memory Services
• Table 8.17 Miscellaneous Runtime Services
• Table 8.19 Flag Firmware Behavior
• Table 8.22 Variables Using EFI_CAPSULE_REPORT_GUID
Chapter 9
Chapter 10
• Table 10.1 Generic Device Path Node Structure
• Table 10.2 Device Path End Structure
• Table 10.3 PCI Device Path
• Table 10.4 PCCARD Device Path
• Table 10.5 Memory Mapped Device Path
• Table 10.6 Vendor-Deﬁned Device Path
• Table 10.7 Controller Device Path
• Table 10.8 BMC Device Path
• Table 10.9 ACPI Device Path
• Table 10.10 Expanded ACPI Device Path
• Table 10.11 ACPI _ADR Device Path
• Table 10.12 NVDIMM Device Path
• Table 10.13 ATAPI Device Path
• Table 10.14 SCSI Device Path
• Table 10.15 Fibre Channel Device Path
• Table 10.16 Fibre Channel Ex Device Path
• Table 10.17 Fibre Channel Ex Device Path Example
• Table 10.18 1394 Device Path
CONTENTS xliiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

Chapter 9
Chapter 10
• Table 10.19 USB Device Paths
• Table 10.20 USB Device Path Examples
• Table 10.21 Another USB Device Path Example
• Table 10.22 SATA Device Path
• Table 10.23 USB WWID Device Path
• Table 10.24 Device Logical Unit
• Table 10.25 USB Class Device Path
• Table 10.26 I 2 O Device Path
• Table 10.27 MAC Address Device Path
• Table 10.28 IPv4 Device Path
• Table 10.29 IPv6 Device Path
• Table 10.31 InﬁniBand Device Path
• Table 10.32 UART Device Path
• Table 10.33 Vendor-Deﬁned Messaging Device Path
• Table 10.34 UART Flow Control Messaging Device Path
• Table 10.35 SAS Messaging Device Path Structure
• Table 10.36 SAS Extended Messaging Device Path Structure
• Table 10.37 iSCSI Device Path Node (Base Information)
• Table 10.38 IPv4 conﬁguration
• Table 10.39 IPv6 conﬁguration
• Table 10.40 NVM Express Namespace Device Path
• Table 10.41 URI Device Path
• Table 10.42 UFS Device Path
• Table 10.43 SD Device Path
• Table 10.44 EFI Bluetooth Device Path
• Table 10.45 Wi-Fi Device Path
• Table 10.46 eMMC Device Path
• Table 10.47 EFI BluetoothLE Device Path
• Table 10.48 DNS Device Path
• Table 10.49 NVDIMM Namespace Device Path
• Table 10.54 Hard Drive Media Device Path
• Table 10.55 CD-ROM Media Device Path
• Table 10.56 Vendor-Deﬁned Media Device Path
• Table 10.57 File Path Media Device Path
• Table 10.58 Media Protocol Media Device Path
• Table 10.59 PIWG Firmware File Device Path
CONTENTS xlivUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Table 10.60 PIWG Firmware Volume Device Path
• Table 10.61 Relative Offset Range
• Table 10.62 RAM Disk Device Path
• Table 10.63 BIOS Boot Speciﬁcation Device Path
• Table 10.64 ACPI_CRS to EFI Device Path Mapping
• Table 10.66 EFI Device Path Option Parameter Values
• Table 10.67 Device Node Table
Chapter 11
Chapter 12
• Table 12.1 Supported Unicode Control Characters
• Table B.1 EFI Scan Codes for EFI_SIMPLE_TEXT_INPUT_PROTOCOL
• Table B.2 EFI Scan Codes for EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL
• Table 12.10 EFI Cursor Location/Advance Rules
• Table 12.20 PS/2 Mouse Device Path
• Table 12.21 Serial Mouse Device Path
• Table 12.22 USB Mouse Device Path
• Table 12.32 Blt Operation Table
• Table 12.34 Attributes Deﬁnition Table
Chapter 13
• Table 13.24 Tape Header Formats
• Table 13.45 PATA device mapping to ports and portmultiplier ports
• Table 13.46 Special Programming Considerations
Chapter 14
• Table 14.5 PCI Conﬁguration Address
• Table 14.15 QWORD Address Space Descriptor
• Table 14.16 End Tag
• Table 14.18 PCI Root Bridge Device Path for a Desktop System
• Table 14.19 PCI Root Bridge Device Path for Bridge #0 in a Server System
• Table 14.20 PCI Root Bridge Device Path for Bridge #1 in aServer System
• Table 14.21 PCI Root Bridge Device Path for Bridge #2 in aServer System
• Table 14.22 PCI Root Bridge Device Path for Bridge #3 in a Server System
• Table 14.37 QWORD Address Space Descriptor
• Table 14.38 End Tag
• Table 14.41 PCI Device 7, Function 0 on PCI Root Bridge 0
• Table 14.42 PCI Device 7, Function 0 behind PCI to PCI bridge
• Table 14.43 Standard PCI Expansion ROM Header (Example from PCI Firmware Speciﬁcation 3.0)
CONTENTS xlvUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Table 14.44 PCI Expansion ROM Code Types (Example from PCI Firmware Speciﬁcation 3.0)
• Table 14.45 EFI PCI Expansion ROM Header
• Table 14.46 Device Path for an EFI Driver loaded from PCIO ption ROM
• Table 14.47 Recommended PCI Device Driver Layout
Chapter 15
• Table 15.4 SCSI Device Path Examples
• Table 15.5 ATAPI Device Path Examples
• Table 15.6 Fibre Channel Device Path Examples
• Table 15.7 InﬁniBand Device Path Examples
• Table 15.9 Single Channel PCI SCSI Controller Behind a PCI Bridge
• Table 15.10 Channel #3 of a PCI SCSI Controller behind a PCIBridge
Chapter 16
Chapter 17
• Table 17.10 USB Hub Port Status Bitmap
• Table 17.11 Hub Port Change Status Bitmap
• Table 17.12 USB Port Features
• Table 17.33 Payload Associated Messages and Descriptions
Chapter 18
• Table 18.1 Debugport Messaging Device Path
Chapter 19
• Table 19.1 Block Header Fields
Chapter 20
Chapter 21
Chapter 22
• Table 22.1 General Purpose VM Registers
• Table 22.2 Dedicated VM Registers
• Table 22.3 VM Flags Register
• Table 22.4 Index Encoding
• Table 22.5 Index Size in Index Encoding
• Table 22.6 Opcode Byte Encoding
• Table 22.7 Operand Byte Encoding
• Table 22.8 ADD Instruction Encoding
• Table 22.9 AND Instruction Encoding
• Table 22.10 ASHR Instruction Encoding
• Table 22.11 VM Version Format
• Table 22.12 BREAK Instruction Encoding
CONTENTS xlviUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Table 22.13 CALL Instruction Encoding
• Table 22.14 CMP Instruction Encoding
• Table 22.15 CMPI Instruction Encoding
• Table 22.16 DIV Instruction Encoding
• Table 22.17 DIVU Instruction Encoding
• Table 22.18 EXTNDB Instruction Encoding
• Table 22.19 EXTNDD Instruction Encoding
• Table 22.20 EXTNDW Instruction Encoding
• Table 22.21 JMP Instruction Encoding
• Table 22.22 JMP8 Instruction Encoding
• Table 22.23 LOADSP Instruction Encoding
• Table 22.24 MOD Instruction Encoding
• Table 22.25 MODU Instruction Encoding
• Table 22.26 MOV Instruction Encoding
• Table 22.27 MOVI Instruction Encoding
• Table 22.28 MOVIn Instruction Encoding
• Table 22.29 MOVn Instruction Encoding
• Table 22.30 MOVREL Instruction Encoding
• Table 22.31 MOVsn Instruction Encoding
• Table 22.32 MUL Instruction Encoding
• Table 22.33 MULU Instruction Encoding
• Table 22.34 NEG Instruction Encoding
• Table 22.35 NOT Instruction Encoding
• Table 22.36 OR Instruction Encoding
• Table 22.37 POP Instruction Encoding
• Table 22.38 POPn Instruction Encoding
• Table 22.39 PUSH Instruction Encoding
• Table 22.40 PUSHn Instruction Encoding
• Table 22.41 RET Instruction Encoding
• Table 22.42 SHL Instruction Encoding
• Table 22.43 SHR Instruction Encoding
• Table 22.44 STORESP Instruction Encoding
• Table 22.45 SUB Instruction Encoding
• Table 22.46 XOR Instruction Encoding
Chapter 23
CONTENTS xlviiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Table 23.5 PUSH_GUID Instruction Encoding
• Table 23.6 PUSH_VERSION Instruction Encoding
• Table 23.7 DECLARE_VERSION_NAME Instruction Encoding
• Table 23.8 AND Instruction Encoding
• Table 23.9 OR Instruction Encoding
• Table 23.10 NOT Instruction Encoding
• Table 23.11 TRUE Instruction Encoding
• Table 23.12 FALSE Instruction Encoding
• Table 23.13 EQ Instruction Encoding
• Table 23.14 GT Instruction Encoding
• Table 23.15 GTE Instruction Encoding
• Table 23.16 LT Instruction Encoding
• Table 23.17 LTE Instruction Encoding
• Table 23.18 END Instruction Encoding
• Table 23.19 DECLARE_LENGTH Instruction Encoding
• Table 23.20 ESRT and FMP Fields
Chapter 24
• Table 24.13 PXE Tag Deﬁnitions for EFI
• Table 24.20 Destination IP Filter Operation
• Table 24.21 Destination UDP Port Filter Operation
• Table 24.22 Source IP Filter Operation
• Table 24.23 Source UDP Port Filter Operation
Chapter 25
Chapter 26
Chapter 27
Chapter 28
Chapter 29
• Table 29.8 DHCP4 Enumerations
• Table 29.19 Field Descriptions
• Table 29.21 Callback Return Values
Chapter 30
• Table 30.18 Descriptions of Parameters in MTFTPv4 PacketStructures
• Table 30.30 Descriptions of Parameters in MTFTPv6 PacketStructures
• Table 30.31 MTFTP Packet OpCode Descriptions
• Table 30.32 MTFTP ERROR Packet ErrorCode Descriptions
CONTENTS xlviiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Chapter 31
Chapter 32
• Table 32.2 Generic Authentication Node Structure
• Table 32.3 CHAP Authentication Node Structure using RADIUS
• Table 32.4 CHAP Authentication Node Structure using Local Database
• Table 32.5 PE/COFF Certiﬁcates Types and UEFI Signature Database Certiﬁcate Types
• Table 32.6 Authentication Attempt Status Codes
Chapter 33
• Table 33.1 Localization Issues
• Table 33.2 Information for Types of Storage
• Table 33.3 Common Control Codes for Font Display Information
• Table 33.11 Guidelines for UEFI System Fonts
• Table 33.12 Truth Table: Mapping A Single Question To Three Conﬁguration Settings
• Table 33.13 Multiple Conﬁguration Settings Example #2
• Table 33.14 Values
• Table 33.15 Package Types
• Table 33.18 Block Types
• Table 33.20 IFR Opcodes
• Table 33.21 VarStoreType Descriptions
• Table 33.22 Animation Block Types
Chapter 34
Chapter 35
• Table 35.11 Callback Behavior
Callback 36
• Table 36.15 Record Values and Descriptions
• Table 36.16 Standard Values for Access to Conﬁgure the Platform
Chapter 37
• Table 37.1 EFI Hash Algorithms
• Table 37.2 Identical Hash Results
• Table 37.8 Algorithms that may be used with EFI_HASH2_PROTOCOL
• Table 37.9 Encryption Algorithm Properties
• Table 37.22 Details of Supported Signature Format
Appendix A
• Table A.1 EFI GUID Format
• Table A.2 Text representation relationships
Appendix B
CONTENTS xlixUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

Chapter 34
Chapter 35
Chapter 37
Appendix A
Appendix B
• Table B.3 Control Sequences to Implement EFI_SIMPLE_TEXT_INPUT_PROTOCOL
Appendix C
• Table C.1 Legacy Floppy Device Path
• Table C.2 IDE Disk Device Path
• Table C.3 Secondary Root PCI Bus with PCI to PCI Bridge Device Path
Appendix D
• Table D.1 EFI_STATUS Code Ranges
• Table D.2 EFI_STATUS Success Codes (High Bit Clear)
• Table D.3 EFI_STATUS Error Codes (High Bit Set)
• Table D.4 EFI_STATUS Warning Codes (High Bit Clear)
Appendix E
• Table E.1 Deﬁnitions
• Table E.2 Referenced Speciﬁcations
• Table E.3 Driver Types: Pros and Cons
• Table E.4 !PXE Structure Field Deﬁnitions
• Table E.5 UNDI CDB Field Deﬁnitions
Appendix F
Appendix G
Appendix H
Appendix I
Appendix J
• Table J.1 EBC Virtual Machine Opcode Summary
Appendix K
Appendix L
• Table L.1 Protocol Name changes
• Table L.2 Revision Identiﬁer Name Changes
Appendix M
• Table M.1 Alias Codes Supported in Addition to RFC 4646
Appendix N
• Table N.1 Error record header
• Table N.2 Error Record Header Flags
• Table N.3 Error Status Fields
• Table N.4 Error Types
• Table N.5 Section Descriptor
CONTENTS lUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Table N.6 Processor Generic Error Section
• Table N.7 Processor Error Record
• Table N.8 IA32/X64 Processor Error Information Structure
• Table N.9 IA32/X64 Cache Check Structure
• Table N.10 IA32/X64 TLB Check Structure
• Table N.11 IA32/X64 Bus Check Structure
• Table N.12 IA32/X64 MS Check Field Description
• Table N.13 IA32/X64 Processor Context Information
• Table N.14 IA32 Register State
• Table N.15 X64 Register State
• Table N.16 ARM Processor Error Section
• Table N.17 ARM Processor Error Information Structure
• Table N.19 ARM TLB Error Structure
• Table N.20 ARM Bus Error Structure
• Table N.21 ARM Processor Error Context Information HeaderStructure
• Table N.22 ARMv8 AArch32 GPRs (Type 0)
• Table N.23 ARM AArch32 EL1 Context System Registers (Type 1)
• Table N.24 ARM AArch32 EL2 Context System Registers (Type 2)
• Table N.25 ARM AArch32 secure Context System Registers (Type3)
• Table N.26 ARMv8 AArch64 GPRs (Type 4)
• Table N.27 ARM AArch64 EL1 Context System Registers (Type 5)
• Table N.28 ARM AArch64 EL2 Context System Registers (Type 6)
• Table N.29 ARM AArch64 EL3 Context System Registers (Type 7)
• Table N.30 ARM Misc. Context System Register (Type 8) - SingleRegister Entry
• Table N.31 Memory Error Record
• Table N.32 Memory Error Record 2
• Table N.33 PCI Express Error Record
• Table N.34 PCI/PCI-X Bus Error Section
• Table N.35 PCI/PCI-X Component Error Section
• Table N.36 Firmware Error Record Reference
• Table N.37 DMAr Generic Errors
• Table N.38 Intel® VT for Directed I/O speciﬁc DMAr Errors
• Table N.39 IOMMU-speciﬁc DMAr Errors
• Table N.40 CCIX PER Log Error Record
• Table N.41 CXL Protocol Error Section
• Table N.42 CXL Component Event Log Record
CONTENTS liUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Appendix O
• Table O.1 UEFI Table Structure
• Table O.2 SMM Communication ACPI Table.
Appendix P
Appendix Q
Appendix R
CONTENTS liiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
List of Figures
Chapter 1
Fig. 1.1 UEFI Conceptual Overview
Chapter 2
Fig. 2.1 Booting Sequence
Fig. 2.2 Stack After AddressOfEntryPoint Called, IA-32
Fig. 2.3 Stack after AddressOfEntryPoint Called, Itanium-based Systems
Fig. 2.4 Construction of a Protocol
Fig. 2.5 Desktop System
Fig. 2.6 Server System
Fig. 2.7 Image Handle
Fig. 2.8 Driver Image Handle
Fig. 2.9 Host Bus Controllers
Fig. 2.10 PCI Root Bridge Device Handle
Fig. 2.11 Connecting Device Drivers
Fig. 2.12 Connecting Bus Drivers
Fig. 2.13 Child Device Handle with a Bus Speciﬁc Override
Fig. 2.14 Software Service Relationships
Chapter 5
Fig. 5.1 MBRDisk Layout with legacy MBR example
Fig. 5.2 GPT disk layout with protective MBR
Fig. 5.3 GPT disk layout with protective MBR on a diskwith capacity > LBA 0xFFFFFFFF
Fig. 5.4 GUID Partition Table (GPT) example
Chapter 6
Fig. 6.1 The BTT Layout in a BTT Arena
Fig. 6.2 A BTT With Multiple Arenas in a Large Namespace
Fig. 6.3 Cyclic Sequence Numbers for Flog Entries
Fig. 6.4 BTT Read Path Overview
Fig. 6.5 BTT Write Path Overview
Chapter 7
Fig. 7.1 Device Handle to Protocol Handler Mapping
Fig. 7.2 Handle Database
Chapter 8
Fig. 8.1 Scatter-Gather List of EFI_CAPSULE_BLOCK_DESCRIPTOR Structures
Chapter 9
Chapter 10
CONTENTS liiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Chapter 11
Fig. 11.1 Driver Health Status States
Chapter 12
Fig. 12.1 Serial Device Identiﬁcation Driver Relationships
Fig. 12.2 Software BLT Buffer
Chapter 13
Fig. 13.1 Nesting of Legacy MBR Partition Records
Fig. 13.2 Cyclic Sequence Numbers in Label Index Block
Fig. 13.3 Organization of the Label Storage Area
Chapter 14
Fig. 14.1 Host Bus Controllers
Fig. 14.2 Device Handle for a PCI Root Bridge Controller
Fig. 14.3 Desktop System with One PCI Root Bridge
Fig. 14.4 Server System with Four PCI Root Bridges
Fig. 14.5 Server System with Two PCI Segments
Fig. 14.6 Server System with Two PCI Host Buses
Fig. 14.7 Image Handle
Fig. 14.8 PCI Driver Image Handle
Fig. 14.9 PCI Host Bus Controller
Fig. 14.10 Device Handle for a PCI Host Bus Controller
Fig. 14.11 Physical PCI Bus Structure
Fig. 14.12 Connecting a PCI Bus Driver
Fig. 14.13 Child Handle Created by a PCI Bus Driver
Fig. 14.14 Connecting a PCI Device Driver
Fig. 14.15 Unsigned PCI Driver Image Layout
Fig. 14.16 Signed and Compressed PCI Driver Image Flow
Fig. 14.17 Signed and Compressed PCI Driver Image Layout
Fig. 14.18 Signed but not Compressed PCI Driver Image Flow
Fig. 14.19 Signed and Uncompressed PCI Driver Image Layout
Chapter 15
Fig. 15.1 Device Handle for a SCSI Bus Controller
Fig. 15.2 Child Handle Created by a SCSI Bus Driver
Chapter 16
Chapter 17
Fig. 17.1 Software Triggered State Transitions of a USB Host Controller
Fig. 17.2 USB Bus Controller Handle
CONTENTS livUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 17.3 Sequence of Operations with Endpoint Policy Changes
Chapter 18
Fig. 18.1 Debug Support Table Indirection and Pointer Usage
Chapter 19
Fig. 19.1 Bit Sequence of Compressed Data
Fig. 19.2 Compressed Data Structure
Fig. 19.3 Block Structure
Fig. 19.4 Block Body
Fig. 19.5 String Info Log Search Tree
Fig. 19.6 Node Split
Chapter 20
Chapter 21
Chapter 22
Chapter 23
Fig. 23.1 Firmware Image with no Authentication Support
Fig. 23.2 Firmware Image with Authentication Support
Fig. 23.3 Firmware Image with Dependency/AuthenticationSupport
Fig. 23.4 Optional Scatter-Gather Construction of Capsule Submitted to Update Capsule()
Fig. 23.5 Capsule Header and Firmware Management Capsule Header
Fig. 23.6 Firmware Management and Firmware Image Management headers
Chapter 24
Fig. 24.1 IPv6-based PXE Boot
Fig. 24.2 Netboot6 (DHCP6 and ProxyDHCP6 reside on the same server)
Fig. 24.3 IPv6-based PXE boot (DHCP6 and ProxyDHCP6reside on the different server)
Fig. 24.4 HTTP Boot Network Topology Concept -Corporate Environment
Fig. 24.5 HTTP Boot Network Topology Concept2 — Homeenvironments
Fig. 24.6 UEFI HTTP Boot Protocol Layout
Fig. 24.7 HTTP Boot Overall Flow
Chapter 25
Chapter 26
Chapter 27
Chapter 28
Chapter 29
Fig. 29.1 EFI REST Support, Single Protocol
Fig. 29.2 EFI REST Support, Multiple Protocols
Fig. 29.3 EFI REST Support, BMC on Board
CONTENTS lvUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 29.4 EFI REST Support, Redﬁsh Service
Fig. 29.5 EFI REST Support, Protocol Usages
Chapter 30
Chapter 31
Chapter 32
Fig. 32.1 Creating A Digital Signature
Fig. 32.2 Veriying a Digital Signature
Fig. 32.3 Embedded Digital Certiﬁcates
Fig. 32.4 Secure Boot Modes
Fig. 32.5 Signature Lists
Fig. 32.6 Process for Adding a New Signature by the OS
Fig. 32.7 Authorization Process Flow
Chapter 33
Fig. 33.1 Platform Conﬁguration Overview
Fig. 33.2 HII Resources In Drivers & Applications
Fig. 33.3 Creating UI Resources With Resource Files
Fig. 33.4 Creating UI Resources With Intermediate Source Representation
Fig. 33.5 The Platform and Standard User Interactions
Fig. 33.6 User and Platform Component Interaction
Fig. 33.7 User Interface Components
Fig. 33.8 Connected Forms Browser/Processor
Fig. 33.9 Disconnected Forms Browser/Processor
Fig. 33.10 O/S-Present Forms Browser/Processor
Fig. 33.11 Platform Data Storage
Fig. 33.12 Keyboard Layout
Fig. 33.13 Forms-based Interface Example
Fig. 33.14 Platform Conﬁguration Overview
Fig. 33.15 Question Value Retrieval Process
Fig. 33.16 Question Value Change Process
Fig. 33.17 String Identiﬁers
Fig. 33.18 Fonts
Fig. 33.19 Font Description Terms
Fig. 33.20 16 x 19 Font Parameters
Fig. 33.21 Font Structure Layout
Fig. 33.22 Proportional Font Parameters and Byte Padding
Fig. 33.23 Aligning Glyphs
CONTENTS lviUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.24 HII Database
Fig. 33.25 Setup Browser

Fig. 33.26 Storing Conﬁguration Settings
Fig. 33.27 OS Runtime Utilization
Fig. 33.28 Standard Application Obtaining Setting Example
Fig. 33.29 Typical Forms Processor Decisions Necessitating a Callback (1)
Fig. 33.30 Typical Forms Processor Decisions Necessitatinga Callback (2)
Fig. 33.31 Typical Forms Processor Decisions Necessitatinga Callback (3)
Fig. 33.32 Driver Model Interactions
Fig. 33.33 Managing Human Interface Components
Fig. 33.34 EFI IFR Form Set conﬁguration
Fig. 33.35 EFI IFR Form Set Question Changes
Fig. 33.36 Glyph Information Encoded in Blocks
Fig. 33.37 Glyph Block Processing
Fig. 33.38 EFI_HII_GIBT_GLYPH_VARIABLITY Glyph Drawing Processing
Fig. 33.39 String Information Encoded in Blocks
Fig. 33.40 String Block Processing: Base Processing
Fig. 33.41 String Block Processing: SCSU Processing
Fig. 33.42 String Block Processing: UTF Processing
Fig. 33.43 Image Information Encoded in Blocks
Fig. 33.44 Palette Structure of a Black & White, One-BitImage
Fig. 33.45 Palette Structure of a Four-Bit Image
Fig. 33.46 Palette Structure of a Four-Bit, Six-ColorImage
Fig. 33.47 Simple Binary Object
Fig. 33.48 Password Flowchart (part one)
Fig. 33.49 Password Flowchart (part two)
Fig. 33.50 Animation Information Encoded in Blocks
Chapter 34
Fig. 34.1 Glyph Example
Fig. 34.2 How EFI_HII_IMAGE_EX_PROTOCOL uses EFI_HII_IMAGE_DECODER_PROTOCOL
Fig. 34.3 Keyboard Layout
Chapter 35
Chapter 36
Fig. 36.1 User Identity
Fig. 36.2 User Identity Manager
Chapter 37
CONTENTS lviiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 37.1 Hash workﬂow
Chapter 38
Chapter 39
Appendix A
Appendix B
Appendix C
Fig. C.1 Example Computer System
Fig. C.2 Partial ACPI Name Space for Example System
Fig. C.3 EFI Device Path Displayed As a Name Space
Appendix D
Appendix E
Fig. E.1 Network Stacks with Three Classes of Drivers
Fig. E.2 !PXE Structures for H/W and S/W UNDI
Fig. E.3 Issuing UNDI Commands
Fig. E.4 UNDI Command Descriptor Block (CDB)
Fig. E.5 Storage Types
Fig. E.6 UNDI States, Transitions & Valid Commands
Fig. E.7 Linked CDBs
Fig. E.8 Queued CDBs
Appendix F
Appendix G
Appendix H
Appendix I
Appendix J
Appendix K
Appendix L
Appendix M
Appendix N
Fig. N.1 Error Record Format
Appendix O
Appendix P
Appendix Q
Appendix R
CONTENTS lviiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Revision History
Many people have contributed to the contents of this speciﬁcation, including the following:
• UEFI Speciﬁcation Working Group (USWG)
• Tianocore Community Members
• Others noted in the Revision History below
Changes in this release
Revision Mantis# - Description Affected Content
2.10 2205 - Enabling SHA-384/SHA-512 signing scheme for Authenti-
cated VariablesSection 8.2.6
2.10 2207 - EFI_SECURITY_VIOLATION can’t be returned by
EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImage()Section 23.1.3
2.10 2217 - Device Authentication Signature Database Section 3.3, Section 32.4.1, Sec-
tion 32.7, Section 32.8.2
2.10 2229 - Support ISA-speciﬁc memory attributes in descriptors Section 2.3.6.1, Section 7.2.3
2.10 2247 - Support crypto agile Section 2.6.5, Section 8.2.5,
Section 8.2.6, Section 27.2, Sec-
tion 28.10, Section 32.3, Section
32.6.3.3, Section 37.4
2.10 2262 - Add Memory Protection proposal -
UEFI_MEMORY_ATTRIBUTE protocolSection 37.7.1
2.10 2266 - Code First - Image Execution Table - revocations of hashes
(Samer El-Haj-Mahmoud)Section 32.4.2
2.10 2271 - Introduce UEFI Conformance Proﬁles Section 2.6, Section 4.6.5
2.10 2277 - Code ﬁrst - Uart() UEFI DevicePath binary/text confusion
issue (Samer El-Haj-Mahmoud)Section 10.6.1.6
2.10 2278 - AARCH64 binding requirement for an OS calling RT ser-
vices on platforms with SMESection 2.3.6, Section 2.3.6.4
2.10 2291 - Support crypto agile - Address crypto agile compatibility Section 3.3, Section 32.5
2.10 2292 - Forward Control Flow Guard Instruction runtime indicator Section 4.6.4
2.10 2313 - Add LoongArch architecture support to UEFI speciﬁcation Section 2.3.8
2.10 2315 - Add NVM Express over Fabrics messaging device path AND
NVMe Trademark updatesSection 6.1, Table 10.52,
Section 10.3.4.32, Section
10.3.4.33, Table 10.67, Section
13.15.2
2.10 2317 - Add conﬁdential computing extension for UEFI Section 38
2.10 2318 - Update boot requirement for RISC-V platform Section 2.3.7.1
2.10 2320 - Remove EBBR Conformance proﬁle Section 4.6.5
2.10 2329 - Update the UEFI to Version 2.10 Section 4.3
2.10 2336 - Feedback on UEFI 2.10 draft sections throughout
2.10 2337 - Code First -Add LoongArch to section UEFI Images Boot
Manager PCI Option ROMs and Debugger Support sections (Li
Chao)sections throughout
2.10 2339 - Re-add RSA 4k support for UEFI 2.10 crypto agility Section 32.5
2.10 2342 - GetHealthStatus: Make the statement and table consistent
for EFI_UNSUPPORTED for Controller Handle Null caseSection 11.10.2
Changes in previous releases
CONTENTS lixUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Revision Mantis # / Description Affected Content
2.9A 2225 - Clarify the speciﬁcation requirements around processing
Boot#### variableSection 3.1.7, Table 3.3, Section
7.1.2
2.9A 2227 - Clarify NVMe device path EUI-64 byte order Section 10.3.4.21
2.9A 2235 - Clarify EFI_LOAD_OPTION.FilePathList[] device path
deﬁnitionSection 3.1.3
2.9A 2243 - Removing old references to Wired for Management
(WfM)Section 3.5.2.1, Section 7.3.1, Ta-
ble 24.13, Referenced Speciﬁca-
tions ,Glossary
2.9A 2249 - Cleanup of the SI & Binary Preﬁxes section Section 1.9.8
2.9A 2251 - Clariﬁcation of DevicePath examples using 0xFF for End
of HW DPSection 10.3.4.4, Table 12.20, Ta-
ble 14.18, Table 15.4, Legacy
Floppy
2.9A 2252 - Clarify OS dependency on UEFI vs PI interfaces Section 1.4
2.9A 2263 - CXL CPER updates Table N.41
2.9A 2270 - Add “CPER” acronym to Appendix N Common Platform Error Record
(CPER)
2.9A 2286 - Section header for CHAP (using RADIUS) Authentication
NodeSection 32.1.6
2.9A 2306 - Deﬁne Arm CPER Processor Error Types ARM Processor Error Information
Structure
2.9A 2311 - Deﬁne the DevicePath argument from LoadImage as op-
tionalSection 7.4.1
2.9A 2327 - Correcting subtype value for REST Service Device Path Section 10.3.4.31
2.9A 2330 - Principle of Inclusive Terminology statement Section 1.1
Revision Mantis # - Description Release Date
2.9 1866 GetInfo() of Adapter Information Protocol should have a
provision for IHV to return no dataMarch 2021
2.9 1982 Clarify the PKCS#7 SignedData structure of
EFI_V ARIABLE_AUTHENTICATIONMarch 2021
2.9 1986 Need a mechanism using which browser to exit out of IHV
formset silently without any popupMarch 2021
2.9 1989 NVDIMM SPA Location Cookie March 2021
2.9 2024 CXL CPER Records March 2021
2.9 2042 New Event Group EFI_EVENT_GROUP_ AF-
TER_READY_TO_BOOTMarch 2021
2.9 2043 New Event Group EFI_EV
ENT_GROUP_BEFORE_EXIT_BOOT_SERVICESMarch 2021
2.9 2046 Add support for Key 14 & 56 for Japanese keyboard layout March 2021
2.9 2053 Figure/Table Numbers are Duplicated in Appendices March 2021
2.9 2062 Table numbering to restart for each chapter March 2021
2.9 2065 CXL proposal for CDAT table extraction from devices March 2021
2.9 2093 UpdateCapsule ScatterGatherList cache maintenance March 2021
2.9 2129 Add DTB Conﬁguration Table standard GUID March 2021
2.9 2131 Clarify Console requirements March 2021
2.9 2134 Introduce unaccepted memory type March 2021
2.9 2155 Typo in Arm Processor CPER Error Section March 2021
2.9 2167 CPER for CXL Component Events March 2021
2.9 2185 Declaration for UEFI 2.9 speciﬁcation in the System Table March 2021
continues on next page
CONTENTS lxUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 3 – continued from previous page
2.9 2190 Misc. spec review feedback March 2021
2.9 2199 EFI_IMAGE_EXECUTION_INFO_TABLE references March 2021
2.9 2200 Conﬁg tables references from section 4.6 March 2021
2.9 2204 Typo in GUID deﬁnition for EFI_MANAG
ED_NETWORK_SERVICE_BINDING_PROTOCOLMarch 2021
2.9 2212 Incorrect cross reference to User Information Table March 2021
2.8 C 2117 - E FI_BROWSER_ACTION_REQUEST_RECONNECT -
perform the action when user exits out of formsetJan. 2021
2.8 C 2139 Update RISC-V UEFI corresponding spec to align with lat-
est RISC-V specJan. 2021
2.8 C 2155 Typo in Arm Processor CPER Error Section Jan. 2021
2.8 C 2158 EFI_DRIVE R_HEALTH_PROTOCOL.GetHealthStatus()
- Driver not managing any controllerJan. 2021
2.8 C 2172 Revise EFI_REDFISH_DICOVER_PROTOCOL deﬁni-
tions to match the implementation.Jan. 2021
2.8 C 2173 Question on EFI_CAPSULE_HEADER Flags deﬁnition Jan. 2021
2.8 C 2184 FI_BOOT_MANAGER_POLICY_PROTOCOL typos Jan. 2021
2.8 C 2190 EFI_SUCCESS misspelled in ﬁve places Jan. 2021
2.8 B 1926 update: corrected EFI_SYSTEM_TABLE entries from 2_8
to 2_80May 2020
2.8 B 1935 update: removed a space from several references to the
EFI_JSON_CAPSULE_ID_GUIDMay 2020
2.8 B 2073 Modify deﬁnition of “DPA” for use with CXL based devices May 2020
2.8 B 2074 Memory Range typo May 2020

2.8 B 2080 Typo in N.2.2 Section Descriptor Table 56 May 2020
2.8 B 2083 Typo in guid deﬁnition of CCIX PER Log Error Section May 2020
2.8 B 2088 Clariﬁcations on caller-freed buffers May 2020
2.8 B 2091 Inconsistency in description of EFI_FIRMW
ARE_MANAGEMENT_CAPSULE_IMAGE_HEADER struc-
tureMay 2020
2.8 B 2092 Typo in deﬁnition of PEI Notiﬁcation type in Table 269.
Error record headerMay 2020
2.8 B 2095 PCI I/O attribute typos in section 14.4 “EFI PCI I/O Proto-
col”May 2020
2.8 B UEFI Runtime Service Table correction May 2020
2.8 B 2096 Typo in deﬁnition of EFI_JSON_CONFIG_DATA_ITEM May 2020
2.8 A 1970 Security Command Protocol change for OPAL RAID de-
vicesFebruary 2020
2.8 A 1998 Update RISC-V related spec February 2020
2.8 A 2000 JSON Capsule clariﬁcation February 2020
2.8 A 2002 Memory allocations between ExitBootServices calls February 2020
2.8 A 2009 DMTF references in UEFI spec February 2020
2.8 A 2013 Correct EFI _BOOT_SERVICES.DisconnectController
contradicting info in DescriptionFebruary 2020
2.8 A 2018 EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID should
take an EFI_HANDLE as ChildHandleFebruary 2020
2.8 A 2020 EF I_LOADED_IMAGE_PROTOCOL.LoadOptions does
not mention it is related to Load Options.February 2020
2.8 A 2025 Capsule Depex Length Declaration February 2020
2.8 A 2026 FMP Capsule Image Header extension February 2020
CONTENTS lxiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.8 A 2029 Add missing GUIDs in Appendix N February 2020
2.8 A 2030 Fix spec index to show the Appendix chapters February 2020
2.8 A 2034 Depex added description February 2020
2.8 A 2035 Fix OUT parameters marked as IN OUT February 2020
2.8 A 2036 SetVariable errata: clarify that in-place variable update is
supportedFebruary 2020
2.8 A 2038 Conﬁguration Tables Errata February 2020
2.8 A 2041 EFI_EVENT_GROUP_EXIT_BOOT_SERVICES Errata February 2020
2.8 A 2050 Incomplete list of EFI_SERVICE_BINDING_PROTOCOL
protocolsFebruary 2020
2.8 A 2049 RuntimeServicesSupported EFI variable should be a conﬁg
tableFebruary 2020
2.8 A 2051 Typo in Table - CPER IA32/X64 Bus Check Structure February 2020
2.8 A 2053 Figure/Table Numbers are Duplicated in Appendices February 2020
2.8 1832 Extend SERIAL_IO with DeviceTypeGuid March 2019
2.8 1834 UEFI REST EX Protocol March 2019
2.8 1853 Adding support for a REST style formset March 2019
2.8 1858 New Device Path for bootable NVDIMM namespaces March 2019
2.8 1861 New EFI_MEMORY_RANGE_CAPSULE Descriptor March 2019
2.8 1866 GetInfo() of Adapter Information Protocol should have a
provision for IHV to return no dataMarch 2019
2.8 1872 Peripheral-attached Memory March 2019
2.8 1876 Remove the EBC support requirement March 2019
2.8 1879 Clariﬁcation of REST (EX) protocol March 2019
2.8 1908 Update of uncommitted data in the FOROM_OPEN call-
backMarch 2019
2.8 1919 Memory Cryptography Attribute March 2019
2.8 1920 Redﬁsh Discover Protocol March 2019
2.8 1921 HTTPS hostname validation March 2019
2.8 1924 Update to EF I_REST_EX_PROTOCOL.AsyncSendReceive March 2019
2.8 1925 Clarify requirement of REST related protocols March 2019
2.8 1926 New UEFI Spec Revision –> 2.8 March 2019
2.8 1935 UEFI JSON Capsule Support March 2019
2.8 1936 ResetSystem - support ResetData for all status scenarios. March 2019
2.8 1937 Behavior of default values March 2019
2.8 1941 New EFI REST JSON Structure Protocol March 2019
2.8 1942 Adding dependency expression capability into FMP type
capsulesMarch 2019
2.8 1947 Keyword strings of Conﬁguration Keyword Handler Proto-
col EnhancementsMarch 2019
2.8 1953 Add document version# conventions March 2019
2.8 1954 set (*Attributes) when GetVariable() returns
EFI_BUFFER_TOO_SMALL and Attributes is non-NULLMarch 2019
2.8 1956 Platform to honor ActionRequest for Action changing March 2019
2.8 1961 Add EFI_UNSUPPORTED to
EFI_RUNTIME_SERVICES callsMarch 2019
2.8 1966 Add new capsule processing error codes March 2019
2.8 1974 Add new CCIX PER Log Error Section to appendix March 2019
2.8 1996 Firmware Processing of the Capsule Identiﬁed by
EFI_JSON_CAPSULE_ID_GUIDMarch 2019
2.7B 1773 Clarify The EFI System Table entry for capsule image March 2019
CONTENTS lxiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.7B 1801 ExtractConﬁg() format may change when called multiple
timesMarch 2019
2.7B 1835 Misleading / unclear statement about EFI-bootability of
UDF mediaMarch 2019
2.7B 1838 RGB/BGR Contradiction in 2.7 GOP March 2019
2.7B 1841 BluetoothLE ECR - support autoreconnect March 2019
2.7B 1842 BluetoothLE ECR - Add missing ConnectionCompleteCall-
2.7B 1843 HTTP Example Code Update March 2019
2.7B 1844 Replace obsoleted RFC number with new number for TCP March 2019
2.7B 1845 Clariﬁcation on AIP types “Network boot” and “SAN MAC
Address”March 2019
2.7B 1846 EFI_LOAD_FILE2 requirement March 2019
2.7B 1865 Adding clariﬁcation in EFI_NOT_READY for Read-
KeyStrokeEx()March 2019
2.7B 1869 Clarify FMP buffer too small behavior March 2019
2.7B 1874 Add RFC3021 to reference in ueﬁ.org March 2019
2.7B 1875 Clarify platform speciﬁc elements in chapter 2.6.2 March 2019
2.7B 1878 Errata - Make DHCP server optional for HTTP boot March 2019
2.7B 1880 Arm binding EL2 register state clariﬁcation March 2019
2.7B 1890 EﬁMemoryMappedIO Usage Clariﬁcation March 2019
2.7B 1897 Clariﬁcation on mapping of UEFI memory attributes to
ARM memory types and paging attributesMarch 2019
2.7B 1899 Errata: Clarify EFI_INV ALID_PARAMETER for FMP-
>GetImageInfo()March 2019
2.7B 1901 GPT Protective MBR description March 2019
2.7B 1902 CapsuleImageSize Clariﬁcation March 2019
2.7B 1903 Root Directory File Name March 2019
2.7B 1906 ACPI Table Pointer Installation March 2019
2.7B 1908 Update of uncommitted data in the FOROM_OPEN call-
2.7B 1923 Syntax error in EFI iSCSI Initiator Name Protocol March 2019
2.7B 1957 Request to add status code EFI_DEVICE_ERROR for Ex-
tractConﬁgMarch 2019
2.7B 1964 Print disclaimer for all future UEFI specs March 2019
2.7B 1987 incorrect VLAN_CONFIG_SET function deﬁnition March 2019
2.7A 1830 Label Protocol - EFI_NVDIMM_LABEL_FLAGS_LOCAL
deﬁnition needs to be updatedAugust 2017
2.7A 1829 Label Protocol Section - Missing deﬁne for
EFI_NVDIMM_LABEL_FLAGS_UPDATINGAugust 2017
2.7A 1823 Modiﬁcations to the examples of the PCI Option ROM im-
age combinationsAugust 2017
2.7A 1822 UEFI 2.7 Organization chapter duplicated August 2017
2.7A 1821 Modify the requirement to enable PCI Bus Mastering August 2017
2.7A 1817 NVDIMM Label Protocol - SetCookie SerialNumber needs
to be UINT32 NOT UINT64August 2017
2.7A 1816 Clariﬁcation of Using HttpConﬁgData in HTTP protocol August 2017
2.7A 1815 OpenProtocol() / EFI_ALREADY_STARTED should out-
put existent InterfaceAugust 2017
2.7A 1808 Clariﬁcation of using option 43 in PXE v2.1 August 2017
2.7 1779 Adjusting UEFI version to UEFI 2.7 April 2017
CONTENTS lxiiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.7 1771BluetoothLE minor ﬁx April 2017
2.7 1762 UEFI UFS DEVICECONFIG Protocol April 2017
2.7 1751 Update DNS Device Path April 2017
2.7 1750 Add new data type to EFI Supplicant Protocol April 2017
2.7 1745 NVDIMM Label Protocol April 2017
2.7 1744 NVDIMMBlock Translation Table (BTT) Protocol
{NewChapter}April 2017
2.7 1730 HII Popup Protocol April 2017
2.7 1726 Host and I/O defense April 2017
2.7 1720 Have Partition driver publish addition information for
MBR/GPT partition types.April 2017
2.7 1719 Add EFI HTTP Boot Callback Protocol April 2017
2.7 1718 Allow SetData to clear conﬁguration in
Ip4Conﬁg2/Ip6Conﬁg ProtocolApril 2017
2.7 1716 Add BluetoothLE ECR April 2017
2.7 1711 Firmware Error Record Update April 2017
2.7 1707 Clariﬁcation of Private Authenticated Variables April 2017
2.7 1701 Add wildcard support to RegisterKeyNotify April 2017
2.7 1690 Reset Notiﬁcation Protocol Update April 2017
2.7 1689 Secure Boot with Externally Managed Conﬁguration April 2017
2.7 1685 Key Management Services (KMS) Protocol Enhancement April 2017
2.7 1672 UEFI Variable Enhancements April 2017
2.7 1654 New AIP Information block for wireless NIC April 2017
2.7 1652 Add DNS device path node April 2017
2.7 1647 UEFI binding for RISC-V April 2017
2.7 1641 Simplify SecureBoot Revocation and Usage of VerifySig-
natureApril 2017
2.7 1641 Simplify Secure Boot Revocation and Usage of VerifySig-
2.7 1627 Support ASCII RegEx Patterns in
EFI_REGULAR_EXPRESSION_PROTOCOLApril 2017
2.7 1627 EFI regular expression syntax type deﬁnitions April 2017
2.7 1623 New EFI_HTTP_STATUS_CODE enum for 308 Permanent
RedirectApril 2017
2.6B 1772 Clarify EFI_NOT_READY in Media State of AIP April 2017
2.6B 1767 Incorrect structure deﬁnition for
EFI_IFR_RESET_BUTTON_OPApril 2017

2.6B 1742 Clairfy PK enrolling in user mode April 2017
2.6B 1741 The memory map returnedByBS->GetMemoryMap() may-
Contain impossible values.April 2017
2.6B 1739 typos -Broken references link. April 2017
2.6B 1729Cleanup of ACPI 2.0 references in UEFI spec April 2017
2.6B 1708 Typos in Imge Decode and Image Ex Protocols April 2017
2.6B 1700 Align ACPI descriptor deﬁnitions in PCI I/O and PCI Root-
Bridge I/OApril 2017
2.6B 1698 Update to Mantis 1613 - GetNextVariable April 2017
2.6B 1691 Remove/Deprecate SMM Communication ACPI Table April 2017
2.6B 1682 HII Protocol StatusCodes April 2017
2.6B 1678 Simplify the ACPI Table GUID declarations April 2017
CONTENTS lxivUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.6B 1675 section 30.5.1 typo April 2017
2.6B 1668 Duplicate GUID issue - mustChange the Image Decoder
Protocol GUIDApril 2017
2.6B 1655 HTTP errata inConﬁgure() April 2017
2.6B 1653 Incorrect errorCode value in MTFTP6 April 2017
2.6B 1634 Update to the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
TPL restrictionApril 2017
2.6B 1629 Errata in GetVariable description April 2017
2.6B 1625 Clariﬁcation of HTTPBoot wire protocol “HTTPClient”
VendorClass OptionApril 2017
2.6B 1624 Fix spelling typo in EFI_HTTP_STATUS_CODE April 2017
2.6B 1613 GetNextVariableName Errata April 2017
2.6B 1612 ResetSystem Errata April 2017
2.6B 1609 UEFI Errata - Address Security problems in the Pkcs7Verify
ProtocolApril 2017
2.6B 1608 Enhance EFI_IFR_NUMERIC (Step) April 2017
2.6B 1586 Errors in appendix N for ARM ProcessorContext Informa-
tionApril 2017
2.6B 1584 WIFI errata April 2017
2.6B 1580 Correct some typos April 2017
2.6B 1559 Clarify return value for NULL pointer in LocateProtocol()
APIApril 2017
2.6B 1557 secureBoot and auth variable errata April 2017
2.6B 1556 HTTPv6Boot DHCP Options Errata April 2017
2.6B 1555 USB Function port protocol errata April 2017
2.6B 1554 ﬁx to ecr 1539 April 2017
2.6B 1553 os recoveryBoot option errata April 2017
2.6B 1551 EFIBluetoothConﬁguration Protocol Errata April 2017
2.6B 1550 Replace FTP4 dataCallback pointer-to-function-pointer
with regular function pointerApril 2017
2.6A SameContent as version 2.6,But with the Adobe “accessibility”
feature activated so text-to-speech will work.December 2016
2.6 1548ClarifyBoot procedure when ﬁle name is absent2. January, 2016
2.6 1547Clarify requirements for setting the PK variable. January, 2016
2.6 1544 DNS lookup API spelling January, 2016
2.6 1543 ip4/6Conﬁg policy errata/2.6 update January, 2016
2.6 1542 UEFI 2.6 supplicant errata January, 2016
2.6 1539 New EFI_HTTP_ERROR StatusCode December, 2015
2.6 1538 UEFI TLS errata December, 2015
2.6 1536 UEFI 2.6 Errata : IMAGE EX Protocol and EFI HII Image
Decoder protocol ErrataDecember, 2015
2.6 1534 EditorialComments against 2.6 Final Draft December, 2015
2.6 1533Bugs in the HTTP usage example December, 2015
2.6 1523Comments against 2.6 Draft December, 2015
2.6 1522 AArch64Bindings AlignmentBit errata December, 2015
2.6 1521Comment against UEFI.next draft - M1479 December, 2015
2.6 1519 Version for the next UEFI spec is. . . December, 2015
2.6 1518Comments against 2.6 Draft December, 2015
2.6 1516 EditorialComments against 2.6 Draft December, 2015
2.6 1509 EFI_PLATFO RM_TO_DRIVER_CONFIGURATION_
PROTOCOL Response to unsupported ParameterTypeGuidDecember, 2015
CONTENTS lxvUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.6 1508 Lack of ﬂexibility and realism in exception levelChoice
whenCalling runtime servicesDecember, 2015
2.6 1507 Insufﬁcient qualiﬁcation of page attributes for AArch64 December, 2015
2.6 1502 PCI IO Deﬁne how to use the Address Translation Offset
for systems that are not mapped 1:1November, 2015
2.6 1501 Deﬁne the usage of the “Address Space Granularity” ﬁeld is
deﬁned in the PCI Root IONovember, 2015
2.6 1496Bad table reference in 13.2 EFI_PCI_ROOT
_BRIDGE_IO_PROTOCOL.Conﬁguration()November, 2015
2.6 1494 Errata against UEFI 2.5 Properties Table November, 2015
2.6 1493 Updates to the SD_MMC_PASS_THRU interface November, 2015
2.6 1492 wireless macConnection protocol II errata November, 2015
2.6 1491 supplicant errata November, 2015
2.6 1480 Reﬁne Progress description in
EFI_KEYWORD_HANDLER_PROTOCOLNovember, 2015
2.6 1479 UEFI Properties TableClariﬁcation November, 2015
2.6 1471 SD/eMMC PassThru Protocol update (follow up to mantis
1376)November, 2015
2.6 1467 New API - EFI_ WIRE-
LESS_MAC_CONNECTION_II_PROTOCOLNovember, 2015
2.6 1466 UEFI Ram disk protocol November, 2015
2.6 1452 Minor edits to 0001409 November, 2015
2.6 1414 Generalisation ofCommunication method in Appendix O November, 2015
2.6 1409 EFI HII ImageEX protocol and EFI HII Image Decoder pro-
tocolsNovember, 2015
2.6 1408 EFI HII Font EX protocol and EFI HII Font Glyph Genera-
tor protocolsNovember, 2015
2.6 1402 Add EFI_BROWSER_ACTION_SUBMITTED November, 2015
2.6 1383 Adding an EraseBlocks() function to a new protocol November, 2015
2.6 1376 SD/eMMC PassThru Protocol November, 2015
2.6 1357 ARMCPER extensions November, 2015
2.5A 1481 new networkConﬁg2 protocol data structure has a magic
numberOctober 2015
2.5A 1477 AllowCloseEvent toBeCalled within the Notiﬁcation Func-
tionOctober 2015
2.5A 1476 Update to Indicate thatCloseEvent UnregistersCorrespond-
ing Protocol Notiﬁcation RegistrationsOctober 2015
2.5A 1472 ATA Pass Thru Errata October 2015
2.5A 1469 UNDI Errata - add more statistics October 2015
2.5A 1468 Errata on UEFI Supplicant protocol October 2015
2.5A 1451 Memory MapConsistency October 2015
2.5A 1441 UEFI2.5A – UNDI ProtocolClariﬁcation October 2015
2.5A 1426 UEFI 2.5 typo October 2015
2.5A 1424 Incorrect link in Section 22.1 FMP GetImageInfo() October 2015
2.5A 1421 Misc HTTP API typos October 2015
2.5A 1420 Get NextHighMonotonicCountClariﬁcation October 2015
2.5A 1419 Supplicant protocol using same GUID as TLS protocol October 2015
2.5A 1418 Inconsistent issues in DNS October 2015
2.5A 1417 Add HttpMethodMax to EFI_HTTP_METHOD enum October 2015
2.5A 1410Clariﬁcations in appendix O October 2015
2.5A 1407 Networking errata - EFI_HTTP_STATUS typos October 2015
CONTENTS lxviUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.5A 1405 Errata in table 271 in Appendix O October 2015
2.5A 1399 Clariﬁcation for EFI_BROWSER_ACTION_ RE-
QUEST_RECONNECTOctober 2015
2.5A 1398 Errata update to the runtime GetVariable operation docu-
mentationOctober 2015
2.5A 1388 Missed memory type ﬁxes October 2015
2.5A 1381 Remove informativeContent in 12.6.1 October 2015
2.5A 1365 7.4 Virtual Memory Services lists Section 2.3.2 through
Section 2.3.4. incorrectlyOctober 2015
2.5A 1363 Short form URI device path October 2015
2.5A 1209 UEFI networking APIChapter 2.6 requirements errors October 2015
2.5A October 2015
2.5 1364 Extend supplicant data type for EAP April, 2015
2.5 1362 HTTPBoot typos/bugs April, 2015
2.5 1360 Vendor Range for UEFI memory Types April, 2015
2.5 1358 v2.5 amendment and v2.4 errata (missed implementation of
Mantis 1089)April, 2015
2.5 1353 SATA Device Path Node Errata April, 2015
2.5 1352 Errata for 1263 and 1227
2.5 1350 Keyword Strings Errata April, 2015
2.5 1348 ERRATA - Section 10.12 EFI
_ADAPTER_INFORMATION_PROTOCOLCustom TypesApril, 2015
2.5 1347Boot Manager Policy Errata April, 2015
2.5 1346 Mantis 1288 Errata April, 2015
2.5 1345 EFI_USB2_HC_PROTOCOL Errata April, 2015
2.5 1342 DNS6 - friendly amendment for reviewBy USWG April, 2015
2.5 1341 DNS4 - friendly amendment toBe reviewedBy USWG April, 2015
2.5 1339 Errata in section 7.2.3.2 Hardware Error Record Variables April, 2015
2.5 1309 Disallow EFI_V ARIABLE_AUTHENTICATION from Se-
cureBoot Policy VariablesApril, 2015
2.5 1308 Fix typo’s found in the ﬁnal/published UEFI 2.4 ErrataB
specFebruary, 2015
2.5 1304 Add IMA GE_UPDATABLE_V ALID_WITH_VENDOR_
CODE to FMPCheck imageFebruary, 2015
2.5 1303 Update the UEFI version to reﬂect new revision February, 2015
2.5 1288 The Macro deﬁnitionConﬂict in EFI_SIMPLE_
TEXT_OUTPUT_PROTOCOL.SetAttribute() in UEFI 2.4BFebruary, 2015
2.5 1287 Errata: EFI Driver Supported EFI Version not matching the
spec revisionFebruary, 2015
2.5 1269Conﬁguration Routing Protocol andConﬁguration String
UpdatesFebruary, 2015
2.5 1268 RAM Disk UEFI Device Path Node February, 2015
2.5 1266 UEFI.Next Feature - IP_CONFIG2 Protocol February, 2015
2.5 1263Customized Deployment of SecureBoot February, 2015
2.5 1257Correct the typedef deﬁnitions for EFI_BOOT_SERVI
CES/EFI_RUNTIME_SERVICES–ReiterateFebruary, 2015
2.5 1255 UFS Device Path Node Length February, 2015
2.5 1254 SD Device Path February, 2015
2.5 1251 EFI_REGULAR_EXPRESSION_PROTOCOL and
EFI_IFR_MATCH2 HII op-codeFebruary, 2015
2.5 1244 sections of the spec mis-arranged February, 2015

CONTENTS lxviiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.5 1234 UEFI.Next feature - SmartCard edge protocol February, 2015
2.5 1227 UEFI.Next feature - Platform recovery February, 2015
2.5 1224 UEFI.Next - Adding support for No executable data areas February, 2015
2.5 1223 UEFI.Next networking features -Chapter 2.6 requirements February, 2015
2.5 1222 UEFI.Next feature -BMC/Service Processor Device Path February, 2015
2.5 1221 UEFI.Next feature - REST Protocol February, 2015
2.5 1220 UEFI.Next feature -Bluetooth February, 2015
2.5 1219 UEFI.Next Feature - UEFI TLS API February, 2015
2.5 1218 UEFI.Next feature - EAP2 Protocol February, 2015
2.5 1217 UEFI.Next feature - WIFI support February, 2015
2.5 1216 UEFI.next feature - DNS version 6 February, 2015
2.5 1215 UEFI.Next feature - DNS version 4 February, 2015
2.5 1214 UEFI.Next feature - HTTPBoot February, 2015
2.5 1213 UEFI.Next feature - HTTP helper API February, 2015
2.5 1212 UEFI.Next feature - HTTP API February, 2015
2.5 1204 new UEFI USB Function I/O Protocol addition to the UEFI
2.5 1201 Exposing Memory Redundancy to OSPM February, 2015
2.5 1199 Add NVM Express Pass Thru Protocol February, 2015
2.5 1191 Add new SMBIOS3_TABLE_GUID in
EFI_CONFIGURATION_TABLEFebruary, 2015
2.5 1186 AArch64BindingClariﬁcations and errata February, 2015
2.5 1183 New Protocol with 2 Function for PKCS7 Signature Veriﬁ-
cation ServicesFebruary, 2015
2.5 1174 errata - Error in EFI_IFR_PASSWORD logic ﬂowchart February, 2015
2.5 1167 Persistent Memory Type support February, 2015
2.5 1166 hash 2 protocol errata February, 2015
2.5 1163 InlineCryptographic Interface Protocol proposal February, 2015
2.5 1159 Proposal for System Prep Applications February, 2015
2.5 1158 errata -Boot managerClariﬁcation February, 2015
2.5 1147–REDACT February, 2015
2.5 1121 IPV6 support from UNDI February, 2015
2.5 1109 SmartCard Reader February, 2015
2.5 1103 Longer term NewCPER Memory Section February, 2015
2.5 1091Clariﬁcation of handle to host FMP February, 2015
2.5 1090 ESRT: EFI System Resource Table andComponent
ﬁrmware updatesFebruary, 2015
2.5 1071 New EFI_HASH2_PROTOCOL February, 2015
2.4C 1308 Fix typo’s found in the ﬁnal/published UEFI 2.4 ErrataB
specJanuary 2015
2.4C 1287 Errata: EFI Driver Supported EFI Version not matching the
spec revisionJanuary 2015
2.4C 1257Correct the typedef deﬁnitions for EFI_
_BOOT_SERVICES/EFI_RUNTIME_SERVICESJanuary 2015
2.4C 1244 sections of the spec misarranged January 2015
2.4C 1211 EFI_LOAD_OPTION Deﬁnition January 2015
2.4C 1209 Errata - UEFI networking APIChapter 2.6 requirements January 2015
2.4C 1205 Errata for Hii Set item January 2015
2.4C 1200 Universal Flash Storage (UFS) Device Path January 2015
2.4C 1198 EFI_ ATA_PASS_THRU_PROTOCOLClariﬁcation January 2015
CONTENTS lxviiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.4C 1194 Add EFI_IFR_FLAG_RECONNECT_REQUIRED January 2015
2.4C 1192Cleanup GUID formatting issues January 2015
2.4C 1186 AArch64BindingClariﬁcations and errata January 2015
2.4C 1185 errata - tcp api January 2015
2.4C 1184 errata - snp modeClariﬁcation January 2015
2.4C 1182 Errata - UEFI URI Device path issue January 2015
2.4C 1174 errata - Error in EFI_IFR_PASSWORD logic ﬂowchart January 2015
2.4C 1173 EFI_IFR_NUMERIC Errata July 11, 2014
2.4C 1172 EﬁACPIMemoryNVS deﬁnition missing S4 July 11, 2014
2.4C 1170 Errata pxeBc apiClariﬁation July 11, 2014
2.4C 1169 Errata - volatile networking variableCleanup July 11, 2014
2.4C 1168 MTFTP Errata July 11, 2014
2.4C 1165 Option rom layout errata July 11, 2014
2.4C 1162 Typo in ReinstallProtocolInterface() EFI 1.10 Extension
sectionJuly 11, 2014
2.4C 1150 Missing LineBreakCharacter (HII Errata) July 11, 2014
2.4C 1147 EFI_USB2_H C_PROTOCOL.AsyncInterruptTransfer()
ErrataJuly 11, 2014
2.4C 1141 UEFI errata - ia32/x64 vector register management July 11, 2014
2.4C 1140UEFI Errata - image execution info table July 11, 2014
2.4C 1139 UEFI Errata on the storage securityCommand protocol July 11, 2014
2.4C 1066 Errata–reference to missing table (90) removed July 11, 2014
2.4C 1043 Ability to refresh the entire form [newContent] July 11, 2014
2.4C 1042 AddBrowser Action Request “reconnect” July 11, 2014
2.4B 1146 Typos andBroken links April 17, 2014
2.4B 1137 Typographic errors in the 2.4 ErrataB draft April 16, 2014
2.4B 1128 URI device path node redux–supersedes (defunct) 1119 April 4, 2014
2.4B 1127 USB Errata - unnecessary restriction on UEFI interrupt
transfer typesMarch 27, 2014
2.4B 1124 Adding text description for NVMe device node March 27, 2014
2.4B 1122Correct misleading language in the UEFI 2.4a speciﬁcation
about the EFI_ADAPTER_INFORMATION_PROTOCOL.E
FI_ADAPTER_INFO_GET_SUPPORTED_TYPES functionMarch 27, 2014
2.4B 1120 Make time stamp handlingConsistent around all of the net-
working API’sMarch 27, 2014
2.4B 1118 Network Performance EnhancementsConcerning V olatile
VariablesMarch 27, 2014
2.4B 1115Clariﬁcation on the usage of XMM/FPU instructions from
within a UEFI Runtime Service on an x64 processorMarch 27, 2014
2.4B 1111 Errors in DisconnectController() returnCode descriptions March 27, 2014
2.4B 1101 Errata – ReinstallProtocolInterface March 27, 2014
2.4B 1092Clariﬁcation to PCI Option ROM Driver Loading Descrip-
tionMarch 27, 2014
2.4B 1085 Error–added in missing text approved for 2.4A April 17, 2014
2.4B 1014 HIIConﬁg Access Protocol Errata April 3, 2014
2.4 A 1089 Short-termCPER Memory Section errata Nov. 14, 2013
2.4 A 1088 Add revision #deﬁne to EFI_FILE_PROTOCOL Nov. 6, 2013
2.4 A 1085 Issues with Interactive password Nov.14, 2013
2.4 A 1082 Mistake in 2.3.5.1 / 2.3.6.2 Handoff State Nov. 6, 2013
2.4 A 1081 Update Install Table protocol to deal with duplicate tables Nov. 6, 2013
2.4 A 1079 UEFI 2.4: Remove repetitive “the” (typo) Nov. 6, 2013
CONTENTS lxixUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.4 A 1078 Adjust some text for handling
EFI_BROWSER_ACTION_CHANGINGNov. 6, 2013
2.4 A 1077 Fix wording in EVT_SIGNAL_EXIT_BOOT_SERVICES Nov. 6, 2013
2.4 A 1076 typo in UEFI v2.3.1d and v2.4 Nov. 6, 2013
2.4 A 1075Clariﬁcations to Table 88. Device Node Table (Device Node
to TextConversion)Nov. 6, 2013
2.4 A 1074 AddClariﬁcations on DMA requirements for PCI_IO Nov. 6, 2013
2.4 A 1073 Add requirement for EFI_USB_IO_PROTOCOL Nov. 6, 2013
2.4 A 1066 Errata - ISCSI IPV6 Root PathClariﬁcation Nov. 6, 2013
2.4 A 1064 AIP Errata Nov. 6, 2013
2.4 A 1063Correction to GPT expression for SizeofPartitionEntry Nov. 6, 2013
2.4 A 1062 EFI_CERT_X509_GUID does not specify theCertiﬁcate
encodingNov. 6, 2013
2.4 A 1061 UEFI 2.4 section 2.6.2 and 2.6.3 don’t use protocol hyper-
linksConsistentlyNov. 6, 2013
2.4 A 1060 SlightClariﬁcation to FMP Authentication Requirments Nov. 6, 2013
2.4 A 1059Clariﬁcation of a return statusCode of HASH protocol Nov. 6, 2013
2.4 A 1058Correct mistake in the system table revision Nov. 6, 2013
2.4 A 1056 text modiﬁcation to deﬁnition of EF
I_FIRMWARE_IMAGE_DESCRIPTOR_VERSION 2Nov. 6, 2013
2.4 A 1055 Disk IO 2 errata Nov. 6, 2013
2.4 A 1054 Deprecate 6 Hash Algorithms with inconsistent usage Nov. 6, 2013
2.4 A 1053 Reduce Name space ofCapsule Result variable to increase
performanceNov. 6, 2013
2.4 A 1035 PCI Option ROM Errata (ﬁve ﬁgures) Nov. 6, 2013
2.4 997 Driver Health Protocol errorCodes April 25, 2013
2.4 993 (original ticket–supersededBy 1026)
2.4 992 Adapter Information Protocol (AIP) April 25, 2013
2.4 991 Greater than 256 NICs support on UNDI April 25, 2013
2.4 968 HII Forms op-code for displaying a warning message April 25, 2013
2.4 966 Spec typos April 25, 2013
2.4 964 Disk IO 2 Protocol to support Async IO April 25, 2013
2.4 963 Add new device path node NVM Express devices April 25, 2013
2.4 956 Require network drivers to return EFI_NO_MEDIA April 25, 2013
2.4 946 ForbidCreation of non-spec variables in
EFI_GLOBAL_V ARIABLE namespaceApril 25, 2013
2.4 920 Add a variable for indicating out ofBand key modiﬁcation April 25, 2013
2.4 905 Need more granularity in EFI_RESET_TYPE to support
platform speciﬁc resetsApril 25, 2013
2.4 1052 UEFI 2.4 Draft April 25th -Corrections to ARM sections May 16, 2013
2.4 1050 2.4 Draft April 25 has missing text for ECR 1009 May 16, 2013
2.4 1049 2.4 Draft April 25 has missing text for ECR 1008 May 16, 2013
2.4 1048Comment against UEFI 2.4 - NVMe related May 16, 2013
2.4 1047Comment on Feb 25th draft - ﬁx alignment issue May 16, 2013
2.4 1045 PCI OpROM Device ListChanges to section 14.2 June 28, 2013
2.4 1044Corrections to Mantis 1015, Interruptible driver diagnostics May 16, 2013
2.4 1037 Add 2.4 to the system table version May 16, 2013
2.4 1036Comments on April 25 Draft May 16, 2013
2.4 1033 HiiConﬁgAccess->ExtractConﬁg StatusCodes Errata May 16, 2013

2.4 1032 HiiConﬁgRouting->ExtractConﬁg StatusCodes Errata May 16, 2013
2.4 1031 NVMe subtypeConﬂict errata April 25, 2013
CONTENTS lxxUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.4 1029 Method for delivery ofCapsule on disk; Method for report-
ingCapsule processing statusApril 25, 2013
2.4 1026 (supersedes 993) Update to the AArch64 proposedBind-
ingChangeApril 25, 2013
2.4 1024Clariﬁcation to the NVMe Device Path text descriptions April 25, 2013
2.4 1023 Deﬁnition ofCapsule format to deliver update image to
ﬁrmware management protocolApril 25, 2013
2.4 1022 adapter information protocol for NIC iSCSI and FCoEBoot-
Capabilities andCurrentBooot Mode.April 25, 2013
2.4 1017 AIP Instance - FCOE SAN MAC Address April 25, 2013
2.4 1016 AIP Instance - Image Update April 25, 2013
2.4 1015 Interruptible driver diagnostics April 25, 2013
2.4 1009 Enable hashes ofCertiﬁcates toBe used for revocation, and
timestamp supportApril 25, 2013
2.4 1008 New Random Number Generator / Entropy Protocol April 25, 2013
2.4 1007Create a new Security Technologies section to avoidBlurring
with SecureBootApril 25, 2013
2.4 1002 Timestamp Protocol April 25, 2013
2.3.1D 996 UEFI 2.0 version number still in the 2.3.1C spec April 3, 2013
2.3.1D 995CSA linkChange April 3, 2013
2.3.1D 994 Spec typos April 3, 2013
2.3.1D 990 EFI_ATA_PASS_THRU need oneClariﬁcation if it supports
ATAPI deviceApril 3, 2013
2.3.1D 989Clarify hot-remove responsibility of aBus Driver April 3, 2013
2.3.1D 988 EFI_BLOCK_IO2_PROTOCOLBlocksChild from stopping
while doing non-blocking I/OApril 3, 2013
2.3.1D 987 EFI_BLOCK_IO2_PROTOCOL has aCopy pasteBug de-
scribing the Token ParameterApril 3, 2013
2.3.1D 980 Errata on SNP Media detect April 3, 2013
2.3.1D 978 Error Retun IndicatesCapsule requiresBoot Services April 3, 2013
2.3.1D 977 missing statement April 3, 2013
2.3.1D 976BrowserCallback text update to description April 3, 2013
2.3.1D 975 UNDI errata to add missing memory type deﬁnitions April 3, 2013
2.3.1D 974 UNDI IncorrectCPB function names ECR April 3, 2013
2.3.1D 973 UNDI Mem_Map()Clariﬁcation April 3, 2013
2.3.1D 972 ISCSI DHCP6Boot April 3, 2013
2.3.1D 971 typo April 3, 2013
2.3.1D 970 Typo section 28.3.8.3.41 EFI_IFR_MODAL_TAG April 3, 2013
2.3.1D 965 File IO Async extenstion April 3, 2013
2.3.1D 962 Remove 2.3 table revision number April 3, 2013
2.3.1D 960 Typo in netboot6 description April 3, 2013
2.3.1D 959 InstallAcpiTable() does not say what to do when an attempt
is made to install a duplicate tableApril 3, 2013
2.3.1D 955Clearing The Platform Key Errata April 3, 2013
2.3.1D 954 LoadImage Errata April 3, 2013
2.3.1D 953 Need text deﬁnitions for Device Path Media Type Subtype
6/7April 3, 2013
2.3.1D 952Clariﬁcation of requirements to update timestamp associated
with authenticated variableApril 3, 2013
2.3.1D 950 IndeterminateBehavior for attribute modiﬁcations mayCause
security issuesApril 3, 2013
CONTENTS lxxiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.1D 949 PCI IO.GetBarAttributes needs adjustment - - Address Space
Granularity ﬁeldApril 3, 2013
2.3.1D 944 Errata - Replace RFC reference April 3, 2013
2.3.1D 943 Errata - Proposed updates to required interfaces inChapter
2.6April 3, 2013
2.3.1D 942 ExportConﬁg() description does not make sense April 3, 2013
2.3.1D 941 Add OEM StatusCode ranges to EFI StatusCode Ranges Ta-
bleApril 3, 2013
2.3.1D 938 InstallMultipleProtocolInterface() is missing StatusCode Re-
turned valuesApril 3, 2013
2.3.1D 935ClarifyChaining requirements with regards to the Platform
KeyApril 3, 2013
2.3.1D 934 Missing Figures and typos April 3, 2013
2.3.1D 930Clarify usage of EFI Variable Varstores in HII April 3, 2013
2.3.1D 928Best Matching Language algorithm April 3, 2013
2.3.1D 926 UEFI Image VeriﬁcationClariﬁcation April 3, 2013
2.3.1D 924 New ErrorCode to handle reporting of IPV4 duplicate ad-
dress detectionApril 3, 2013
2.3.1D 1021 ATA_PASS_THRU on ATAPI device handle. April 3, 2013
2.3.1D 1020Clarify HII variable store deﬁnitions. April 3, 2013
2.3.1D 1019 Alignment RequirementsClariﬁcation April 3, 2013
2.3.1D 1018 HII Font Errata April 3, 2013
2.3.1D 1013 HII Errata April 3, 2013
2.3.1D 1012 Touchup to text of GPT April 3, 2013
2.3.1D 1011 Typo regarding Debug Port in UEFI Spec April 3, 2013
2.3.1D 1003 Missing “(” in section 11.7 April 3, 2013
2.3.1D 1000Clariﬁcation to the IFR_REF4 opcode April 3, 2013
2.3.1C 921 Length of IPv6 Device Path is incorrect June 13, 2012
2.3.1C 917 UNDI drive does not need toBe initialized as runtime driver June 13, 2012
2.3.1C 915 For x64,Change Floating Point DefaultConﬁguration to
Double-Extended PrecisionJune 13, 2012
2.3.1C 914 Error Descriptor Reset FlagClariﬁcation June 13, 2012
2.3.1C 913 Enum deﬁnition does not match what ourCurrentCompilers
implement.June 13, 2012
2.3.1C 912 UEFI 2.3.1 Type June 13, 2012
2.3.1C 909 Update to returnCodes for AllocatePool / AllocatePages June 13, 2012
2.3.1C 907 iSCSI Device Path error June 13, 2012
2.3.1C 882 Indications Variable - OS/FW feature &CapabilityCommu-
nicationJune 13, 2012
2.3.1C 874 Provide a mechanism for providing keys in setup mode June 13, 2012
2.3.1C 831 PXEBootCSA Type deﬁnitionCleanup June 13, 2012
2.3.1B 896 StartImage andConnectController returnCodes April 10, 2012
2.3.1B 893 SMMCommunication ACPI Table Update April 10, 2012
2.3.1B 891Component Name Protocol References April 10, 2012
2.3.1B 890 DriveConﬁguration Protocol Phantom. April 10, 2012
2.3.1B 888 typo in EFI_USB_HC Protocol April 10, 2012
2.3.1B 887 union is declared twice in same section April 10, 2012
2.3.1B 885 Errata in the GPT Table structureComment April 10, 2012
CONTENTS lxxiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.1B 884 EFI_BOOT_KEY_DATA relies on implementation-
deﬁnedBehaviorApril 10, 2012
2.3.1B 881 netboot6 - multicast versus unicast April 10, 2012
2.3.1B 880 netboot6Clariﬁcation/errata April 10, 2012
2.3.1B 879 Reference to unsupported speciﬁcation in SCSIChapter
(14.1)April 10, 2012
2.3.1B 878 Updated HII “Selected Form”Behaviors to Reﬂect NewCall-
back ResultsApril 10, 2012
2.3.1B 877 TableChecksum updateBy the A
CPI_TABLE_PROTOCOL.InstallAcpiTableApril 10, 2012
2.3.1B 876 ToClarify EDID_OVERRIDE attribute deﬁnitions and ex-
pected operationsApril 10, 2012
2.3.1B 873 Section 9.3.7 incorrectly assumes that all uses ofBBS device
paths are non-UEFIApril 10, 2012
2.3.1B 872Change to SIMPLE_TEXT_INPUT_EX_PROTOCOL.Re
gisterKeyNotify/UnregisterKeyNotifyApril 10, 2012
2.3.1B 871 Typo in InstallMultipleProtocolInterfaces April 10, 2012
2.3.1B 870Clarify FrameBufferSize deﬁnition under
EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE structApril 10, 2012
2.3.1B 869 Reference to FIPS 180 inChapter 27.3 is obsolete and incor-
rectApril 10, 2012
2.3.1B 867Clarify requirment for use of
EFI_HASH_SERVICE_BINDING_PROTOCOLApril 10, 2012
2.3.1B 866 PK, KEK, db, dbx relationsClariﬁcation April 10, 2012
2.3.1B 865 Modify Protective MBRBootIndicator deﬁnition April 10, 2012
2.3.1B 864 Typo in Question-Level Validation section April 10, 2012
2.3.1B 863 Attributes of the Globally Deﬁned Variables April 10, 2012
2.3.1B 862 User identity typo April 10, 2012
2.3.1B 861 Globally Deﬁned Variables Errata April 10, 2012
2.3.1B 858 Superﬂuous and incorrect image hash description April 10, 2012
2.3.1B 857 Absolute pointer typo April 10, 2012
2.3.1B 855Clariﬁcation of UEFI driver signing/Code deﬁnitions April 10, 2012
2.3.1B 853 The EFI_HASH_PROTOCOL.Hash() description needsClar-
iﬁcation on padding responsibilitiesApril 10, 2012
2.3.1B 852 Various EFI_IFR_REFRESH_ID errata. April 10, 2012
2.3.1B 851 For EFI_IFR_REFRESH opcode,Clarify RefreshInterval = 0
means no auto-refresh.April 10, 2012
2.3.1B 850Clariﬁcation of responsibility for array allocation in
EFI_HASH_PROTOCOLApril 10, 2012
2.3.1B 849 IFR EFI_IFR_MODAL_TAG_OP is also valid under
EFI_IFR_FORM_MAP_OPApril 10, 2012
2.3.1B 848Clariﬁcation of semantics of SecureBoot variable April 10, 2012
2.3.1B 847 When enrolling a PK, the platform shall not require a reboot
to leave SetupModeApril 10, 2012
2.3.1B 845 EFI_SCSI_PASS_THRU_PROTOCOL replacement April 10, 2012
2.3.1B 842 Text to explain how the UEFI revision is referred April 10, 2012
2.3.1B 836 StructureComment for EFI_IFR_TYPE_V ALUE references
unknown value type.April 10, 2012
2.3.1B 828 Network Driver Options April 10, 2012
2.3.1B 826Comments against Mantis 790 April 10, 2012
2.3.1B 825 DMTF SMCLP errata April 10, 2012
CONTENTS lxxiiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.1B 819 Mantis 715 was not fully implemented April 10, 2012
2.3.1B 812 Errata – DUID-UUID usage April 10, 2012

2.3.1B 809 Errata – Messaging Device PathClariﬁcation April 10, 2012
2.3.1B 808 Errata –Boot File URL April 10, 2012
2.3.1B 807 Give speciﬁc TPL rules to Stall()Boot services April 10, 2012
2.3.1B 771 SHA1 and MD5 references April 10, 2012
2.3.1A MinorCorrections in toes to tickets 772, 785, 794, 804, also
formattingCorrection for _WIN_CERTIFICATE_UEFI_GUID
typedef’s parametersSeptember 7, 2011
2.3.1A 820 Driver Health Needs to have Mantis 0000169 implemented August 17, 2011
2.3.1A 819 ECR715 was not fully implemented August 17, 2011
2.3.1A 806 Text update to Driver Health Description -Clarify role of user
interactionAugust 17, 2011
2.3.1A 805Correct Wrong Palette Information in 28.3.7.2.3 example August 17, 2011
2.3.1A 804ClarifyContraints and alternatives when enrolling PK, KeK,
db or dbx keysAugust 17, 2011
2.3.1A 803 Fix AcpiExp device node text description. August 17, 2011
2.3.1A 801ClarifyIFR Opcode Summary and Description #4 August 17, 2011
2.3.1A 800Clarify IFR Opcode Summary and Description #3 August 17, 2011
2.3.1A 797Clarify IFR Opcode Summary and Description #2 August 17, 2011
2.3.1A 796Clarify IFR Opcode Summary and Description #1 August 17, 2011
2.3.1A 795 Typo in ReadKeyStrokeEx() August 17, 2011
2.3.1A 794 Incomplete text describingClearing of Platform Key August 17, 2011
2.3.1A 793 Inconsistent wording about RemainingDevicePath August 17, 2011
2.3.1A 790 Add warning to ReadKeyStrokeEx for partial key press August 17, 2011
2.3.1A 789Clarify HII opcode deﬁnition August 17, 2011
2.3.1A 788 SasEx entry in Table 86-Device Node TableContains optional
Reserved entry that does not exist in device pathAugust 17, 2011
2.3.1A 786 PCI I/O Dual AddressCycle attributeClariﬁcation August 17, 2011
2.3.1A 785 Allowing more general use of UEFI 2.3.1 Variable time-
based authenticationAugust 17, 2011
2.3.1A 780 Errata in returnCode descriptions August 17, 2011
2.3.1A 778 EFI_HI I_CONFIG_ACCESS_PROTOCOL.CallBack() Er-
rataAugust 17, 2011
2.3.1A 777 Speciﬁed signature sizes incorrect in Section 27.6.1 August 17, 2011
2.3.1A 776 Clarifycomputation of EFI_V ARIABLE_ AUTHENTICA-
TION_2 hash valueAugust 17, 2011
2.3.1A 774 Deﬁne EFI_BLOCK_IO_PROTOCOL_REVISION3 August 17, 2011
2.3.1A 773Clarify the value for opcode EFI_IFR_REFRESH_ID_OP August 17, 2011
2.3.1A 772 Deﬁnition of EFI_IMAGE_SECURITY_DATABAE_GUID
incorrectAugust 17, 2011
2.3.1A 770 Remove references to UEFI 2.1 spec August 17, 2011
2.3.1A 767 The ReadBlocks function forBlockIO andBlockIO2 need
synchronizationAugust 17, 2011
2.3.1A 212 (revisit) ﬁnal sentence section 28.2.15 missing ﬁnal words. April 21, 2011
2.3.1 765 ECR to limit the hash and encryption algorithms used with
PKCSCertiﬁcatesApril 5, 2011
2.3.1 762 DevicePath in the Image Execution Information Table. April 5, 2011
2.3.1 761 Table 195. Information for Types of Storage April 5, 2011
2.3.1 760 SuggestedChanges to 2.3.1 ﬁnal draft spec April 5, 2011
2.3.1 759 UEFI Errata - wincerts for rest of hash algorithms April 5, 2011
CONTENTS lxxivUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.1 755 Errata in Legacy MBR table and Legacy MBR GUID April 5, 2011
2.3.1 754 USB timeout parameter mismatch. April 5, 2011
2.3.1 751 Fix USB HC2 erroneous references to IsSlowDevice March 11, 2011
2.3.1 750 Fix section 27.2.5 “related deﬁnitions” re: RSA public key
exponentMarch 11, 2011
2.3.1 749 Fix Table 10 (Global Variables) WithCorrect Attributes March 11, 2011
2.3.1 748Clarify Standard GUID Text Representation March 11, 2011
2.3.1 744 ProcessorContext information structure deﬁnition notClear March 11, 2011
2.3.1 741 Errata:Corrected text for section 7.2.1.4 step 7 March 11, 2011
2.3.1 740 Errata: signatureheadersize inconsistencyCorrections April 6, 2011
2.3.1 736 Insert SMMCommunication ACPI Table and related data
structures to the UEFI SpeciﬁcationApril 5, 2011
2.3.1 735Clariﬁcation on Tape Header Format March 11, 2011
2.3.1 734 SecureBoot variable April 5, 2011
2.3.1 733 Errata: 27.6.1 signatureheadersize deﬁnition March 11, 2011
2.3.1 732 Amendment to Mantis 711: section 7.2.1.6 March 11, 2011
2.3.1 729 Errata:Clariﬁcation of Microsoft references in appendix Q March 11, 2011
2.3.1 728 Netboot 6 errata - DUID-UUID March 11, 2011
2.3.1 727 Errata on returnCode for User Info Identity policy record March 11, 2011
2.3.1 726 Errata/clean-up of EFI_DHCP4_TRANSMIT_RECEIVE_
TOKEN deﬁnitionMarch 11, 2011
2.3.1 724 SetVariable Update 2 March 11, 2011
2.3.1 723 User Identiﬁcation (UID) Errata – EFI User Manager Notify
& EnrollClariﬁcationApril 5, 2011
2.3.1 722 User Identiﬁcation (UID) Errata –Credential Provider En-
rollClariﬁcationApril 5, 2011
2.3.1 721 User Identiﬁcation (UID) Errata – SetInfoClariﬁcation March 11, 2011
2.3.1 720 User Identiﬁcation (UID) Errata –Credential Provider En-
rollClariﬁcationMarch 11, 2011
2.3.1 716 EFI_EXT_SCSI_PASS_THRU_ PROTO-
COL.GetNextTarget() IN OUT parameter Target input value
shallBe 0xFFsMarch 11, 2011
2.3.1 715CPER Record and section ﬁeldClariﬁcation March 11, 2011
2.3.1 713 Remove the errata revision from the EFI_IFR_VERSION
format.March 11, 2011
2.3.1 711 SetVariable Update March 11, 2011
2.3.1 709 NewCallback() Action Requests Related To Individual
Forms.Feb. 3, 2011
2.3.1 708 Errata (non-blockingBLOCK IO) April 5, 2011
2.3.1 707 Errata revision in the EFI_IFR_VERSION format Feb. 3, 2011
2.3.1 705 REPC signature deﬁnition stillConfusing Feb. 3, 2011
2.3.1 704 Unload() deﬁnition is wrong Feb. 3, 2011
2.3.1 702Clariﬁcations on Variable Storage for Questions Feb. 3, 2011
2.3.1 696 Update System Table with this new #deﬁne for
EFI_SYSTEM_TABLE_REVISIONFeb. 3, 2011
2.3.1 695 Add Port Ownership probing Feb. 3, 2011
2.3.1 687 Update System Table with this new #deﬁne for 2.3.1 Jan. 17, 2011
2.3.1 686 HII -Clarify FormsBrowser ‘standard’ user interfactions. Feb. 3, 2011
2.3.1 685 HII - New op-code to enable event initiated refresh of-
BrowserContext dataFeb. 3, 2011
2.3.1 682 [UCST] Modal Form Feb. 3, 2011
CONTENTS lxxvUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.1 681 Typo: Pg. 56 Jan. 17, 2011
2.3.1 680 Netboot6 handleClariﬁcation Jan. 17, 2011
2.3.1 679 UEFI Authenticated Variable & Signature Database Updates Jan. 17, 2011
2.3.1 678 Section 27.6.2: Imagehash reference needs toBe removed Jan. 17, 2011
2.3.1 677 Section 27.2.5 & 27.6.1: Typo in X509 Signature Type Jan. 17, 2011
2.3.1 674 Section 3.2: Missing variable type for SetupMode variable Jan. 17, 2011
2.3.1 671 Errata: USB device path example is incorrect Jan. 17, 2011
2.3.1 668 LUN implementations are notConsistent Feb. 3, 2011
2.3.1 661 USB 3.0 Updates Oct. 29, 2010
2.3.1 645 Non-blocking interface forBLOCK oriented devices
(BLOCK_IO_EX transition toBLOCK_IO_2)Oct. 29, 2010
2.3.1 634 FormsBrowser DefaultBehavior Jan. 17, 2011
2.3.1 634 FormsBrowser DefaultBehavior Oct. 29, 2010
2.3.1 616 Security ProtocolCommand to support encrypted HDD Jan. 17, 2011
2.3.1 616 Security ProtocolCommand to support encrypted HDD Oct. 29, 2010
2.3.1 612 UEFI system Partition FAT32 data Region Alignment Oct. 29, 2010
2.3.1 484 Key Management Service Protocol Oct. 28, 2010
2.3.1 484 Key Management Service (KMS) Protocol Oct. 29, 2010
2.3.1 478 (REVISIT) Update to ALTCFG references March 11, 2011
2.3 D 667Clariﬁcation to the UEFIConﬁguration Table deﬁnition Oct. 28, 2010
2.3 D 664 Appendix update for IPV6 networkBoot Oct. 28, 2010
2.3 D 663 Update ARM PlatformBinding to allow OS loader to assume
unaligned access support is enabledNov. 10, 2010
2.3 D 662 ARM ABI errata Oct. 28, 2010
2.3 D 659Clarify section length deﬁnition in the error record Oct. 28, 2010
2.3 D 653 Errata to the Appendix N (Common Platform Error Record) Oct. 28, 2010
2.3 D 652Clariﬁcation to the TimeZone value usage Oct. 28, 2010
2.3 D 651 update to IPSec for tunnel mode support Oct. 28, 2010
2.3 D 650 networking support errata Oct. 28, 2010
2.3 D 638 Add facility for dynamic IFR dynamicCross-references Oct. 28, 2010
2.3 D 538 IPV6 PXE Oct. 28, 2010
2.3C 640 String ReferenceCleanup July 14, 2010
2.3C 639Callback() does not describe
FORM_OPEN/FORM_CLOSEBehaviorJuly 14, 2010
2.3C 637Clariﬁcation for Date/Time Question usage in IFR expres-
sions.July 14, 2010
2.3C 636 Mistaken Reference to “Date” inside ofBoolean question de-
scriptionJuly 14, 2010
2.3C 635 Missing GUID label forConﬁg Access protocol July 14, 2010
2.3C 633 Explicitly Specify ACPI Table Signature Format July 14, 2010
2.3C 632ClarifyBlock IO ReadBlocks and WriteBlocks functions han-
dling of media stateChange eventsJuly 14, 2010
2.3C 625 Minor typo in surrogateCharacter description section July 14, 2010
2.3C 622 Identify() function errata July 14, 2010
2.3C 621 Typos in an EFI_HII_CONFIG_ACCESS_ PROTO-
COL.Callback() memberJuly 14, 2010
2.3C 620Cariﬁcation of need for Path MTU support for IPV4 and IPV6 July 14, 2010
2.3C 613 PAUSE Key July 14, 2010

2.3C 611 LanguageCorrection requested for InstallProtocolInterface()
and InstallConﬁgurationTable(), Ref# 583July 14, 2010
2.3C 610 RSA data structureClariﬁcation July 14, 2010
CONTENTS lxxviUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3C 609 StartImage returnCode update July 14, 2010
2.3C 583 How do we know an EFI_HANDLE is Valid/Invalid July 14, 2010
2.3C 508 Update networking references, incl ipv6 July 14, 2010
2.3B 608 more media detectClean-up Feb. 24, 2010
2.3B 605Clarify user identity Find API Feb. 24, 2010
2.3B 601 UNDI update as part of media detectChanges Feb. 24, 2010
2.3B 600 Update toConﬁgAccess/ConﬁgRouting Feb. 24, 2010
2.3B 598 ARP is only an IPV4Concept. Feb. 24, 2010
2.3B 590 Media detectClean-up Feb. 24, 2010
2.3B 589 Device path representation of IPv4/v6 text Feb. 24, 2010
2.3B 588 UEFI User Identity - ReturnCodes Feb. 24, 2010
2.3B 587 UEFI User Identity - NamingConsistency Feb. 24, 2010
2.3B 586Clariﬁcation of PXE2.1 speciﬁcation for IPV4 interoperabil-
ity issuesFeb. 24, 2010
2.3B 585 Errata to EFI_IFR_SET op-code Feb. 24, 2010
2.3B 584 EFI_PXE_BASE_CODE_DHCPV6_PACKET missing for
pxeBc protocolFeb. 24, 2010
2.3B 583 How do we know an EFI_HANDLE is Valid/Invalid Feb. 24, 2010
2.3B 580 ACPI_SUPPORT_PROTOCOLClariﬁcations related to
FADT and the DSDT/FACSDec. 15, 2009
2.3B 578 ATA Passthrough updates / questions Dec. 15, 2009
2.3B 577Clariﬁcations on the user identity protocol Dec. 15, 2009
2.3B 576Clariﬁcations in the Routing Protocol Dec. 15, 2009
2.3B 575 Machine hand-off/MP state modiﬁcation Feb. 24, 2010
2.3B 574 Add an “OPTIONAL” tag to a parameter in NewPackageList Dec. 15, 2009
2.3B 573 EFI_DESCRIPTION_STRING and
EFI_DESCRIPTION_BUNDLE adjustmentsFeb. 24, 2010
2.3B 572 EFI_IFR_SECURITY shouldBe EFI_IFR_SECURITY_OP
in Table 194Dec. 15, 2009
2.3B 568 ATA_STATUS_BLOCK name errata Dec. 15, 2009
2.3B 567 Various miscellaneous typos/updates Feb. 24, 2010
2.3B 566 Minor update to HII->NewString function description Dec. 15, 2009
2.3B 560Correct erroneous example in ExtractConﬁg() Dec. 15, 2009
2.3B 559 Extraneous “default” tag in EFI_IFR_SECUITY grammar Dec. 15, 2009
2.3B 558Clarify VLANConﬁg publication requirements Dec. 15, 2009
2.3B 557Corrected Image Execution Information omission & ambigu-
ityDec. 15, 2009
2.3B 556 additional IPSec errata/issues Dec. 15, 2009
2.3B 549Binary preﬁxChange Dec. 15, 2009
2.3B 547Clean-Up In HII Sections Dec. 15, 2009
2.3B 546 typo in GOP deﬁniton Dec. 15, 2009
2.3B 545 Action parameter of the EFI_HI
I_CONFIG_ACCESS_PROTOCOL.CallBack()Dec. 15, 2009
2.3B 542 Device Path DescriptionChanges Dec. 15, 2009
2.3B 540 Register name usage Dec. 15, 2009
2.3B 539CHAP node ﬁx for iSCSI Dec. 15, 2009
2.3B 537 Add missing ACPI ADR Device Path Representation Dec. 15, 2009
2.3B 536 IPSec errata Dec. 15, 2009
2.3B 534 Size of Partition Entry restriction Dec. 15, 2009
2.3B 533 GPT editorialCleanup Dec. 15, 2009
CONTENTS lxxviiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3B 532 “LegacyBIOSBootable” GPT attribute Dec. 15, 2009
2.3B 531Clarify HII Variable Storage Dec. 15, 2009
2.3B 519 AddConsole table (chapt 11) for
EFI_SIMPLE_TEXST_INPUT_EX_PROTOCOLDec. 15, 2009
2.3B 518 Typos in the UEFI2.3 speciﬁcation Feb. 24, 2010
2.3B 515 Authenticated VariablesClariﬁcation Feb. 24, 2010
2.3B 514 HIIConﬁguration String SyntaxClariﬁcation Feb. 24, 2010
2.3B 507Clarify ACPI Protocol’s position onChecksums Dec. 15, 2009
2.3B 479 TPM guideline added to section 2.6.2 Dec. 15, 2009
2.3B 476 Text adjustment toConﬁgAccess &ConﬁgRouting Dec. 15, 2009
2.3B 460 Section 2.6 languageChange Dec. 15, 2009
2.3B 454 Dynamic support of media dectection - network stack Dec. 15, 2009
2.3B 431 UEFI 2.3 Feb Draft: Section 30.4 Feb. 24, 2010
2.3B 301 Errata to the Authentication Protocol Dec. 15, 2009
2.3B 215 previously added to Device Driver (wrong), nowBusDriver
(correct)Dec. 15, 2009
2.3A 522Bugs in EFI_CERT_BLOCK_RSA_2048_SHA256, ISCSI
device path,CHAP device pathSept 15, 2009
2.3A 518 typos Sept 15, 2009
2.3A 517 IP stack related protocol update Sept 15, 2009
2.3A 516 User Identity ProtocolBugs Sept 15, 2009
2.3A 513 add support for gateways in ipv4 & ipv6 device path nodes Sept 15, 2009
2.3A 506 TCP6/MTFTP6 StatusCode Deﬁnition Sept 15, 2009
2.3A 505 TCP4/MTFTP4 statusCodes Sept 15, 2009
2.3A 490Correction 28.2.5.6, Table 185. Information for Types of Stor-
ageSept 15, 2009
2.3A 478 Update to ALTCFG references Sept 15, 2009
2.3A 477 Text adjustment toConﬁgAccess/ConﬁgRouting Sept 15, 2009
2.3 463 Update EFI_IP6_PROTOCOL.Neighbors() API May 7, 2009
2.3 462 ExitBootServices timers deavtivation May 7, 2009
2.3 461IP4 Mode Data deﬁnition update May 7, 2009
2.3 460Chapter 2.6 language update May 7, 2009
2.3 457Change KeyData.PackedValue to 0x40000200, page 63. May 7, 2009
2.3 456 How to handle PXEBoot w/o NII Section 21.3 May 7, 2009
2.3 454 Dynamic support of media detection - network stack May 7, 2009
2.3 453 Errata to support dynamic media detection - UNDI May 7, 2009
2.3 452 Support to dynamically detect media errata - SNP May 7, 2009
2.3 450 Missing opcode headers and formatting, section 28.3.8.3.x. May 7, 2009
2.3 449 Add missing EFI_IFR_GET, EFI_IFR_SET and
EFI_IFR_MAP to the syntax.Section 28.2.5.7.May 7, 2009
2.3 448 Section 28.2.5.4 Questions, Syntax, Update question-option-
tag; Add EFI_IFR_READ and EFI_IFR_WRITE in the question
syntax.May 7, 2009
2.3 447Section 28.2.5.11.2 Moving Forms, Update line that
starts with EFI_IFR_FORM to: EFI_IFR_FORM or
EFI_IFR_FORM_MAP (and all references in EFI_IFR_REF)May 7, 2009
2.3 446 Section 28.2.5.2 Forms, Syntax,Change 3rd line to: form
:= EFI_IFR_FORM form-tag-list | EFI_IFR_FORM_MAP form-
tag-listMay 7, 2009
2.3 445 Table 194: EFI_IFR_FORM_MAP_OP, 2ndColumn
shouldBe 0x5d (not 05xd)May 7, 2009
CONTENTS lxxviiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3 444 Form Set Syntax: Section 28.2.5.1.1, section shouldBe sub-
heading, not heading level 5; Section 28.2.5.1, Syntax, line 3, text
after := is not aligned with other text on line 2, 4May 7, 2009
2.3 443 Section 28.3.8.3.38, EFI_IFR_MAP, Prototype, line 4, out-
dent 2 spaces.May 7, 2009
2.3 442 Section 28.3.8.3.64, EFI_IFR_SET, Prototype, lines 3-8, in-
dentBy 2 spacesMay 7, 2009
2.3 440Change the deﬁned type of EFI_STATUs from INTN to
UINTNMay 7, 2009
2.3 439 Incorrect deﬁnitions of UEFI_CONFIG_LANG and
UEFI_CONFIG_LANG_2 in UEFI 2.3 Feb18 draftFeb 25, 2009
2.3 438 UEFI 2.3 Feb 13 Draft:Chapter 28 Formatting Issues Feb 18, 2009
2.3 437 Errata to 2.3 draft material from UEFI Spec 2_3_Draft_Jan29 Feb 18, 2009
2.3 436 UEFI 2.3 split Figure 88 into 3 ﬁgures Feb. 12, 2009
2.3 435 Partition SignatureClariﬁcation Feb. 12, 2009
2.3 434 UEFI 2.3 Feb Draft: 28.3.8.3.58 Feb. 12, 2009
2.3 432 UEFI 2.3 Feb Draft: Appendix M. Feb. 12, 2009
2.3 431 UEFI 2.3 Feb Draft: Section 30.4 Feb. 12, 2009
2.3 418Change Appendix O from “UEFI ACPI Table” to “UEFI
ACPI DataFeb 18, 2009
2.3 413Correct the deﬁnition of UEFI_CONFIG_LANG Feb 18, 2009
2.3 410 UNDIBuffer usage Feb 18, 2009
2.3 408 ARMBindingCorrections Feb. 12, 2009
2.3 406 Missing EFI System Table Revision In UEFI 2.3 Draft Feb. 12, 2009
2.3 395 New “Non-removable MediaBootBehavior” section Feb. 12, 2009
2.3 394 Omission in EFI_USB2_HC_PROTOCOL Feb. 12, 2009
2.3 388 Add HIICallback types (FORM_OPEN, FORM_CLOSE)
when a form is opened orClosed.Feb. 12, 2009
2.3 376 Add ARM processorBinding to UEFI Jan. 12, 2009
2.3 326 Add Firmware Management Protocol Feb. 12, 2009
2.2A 429 EFI_HASH_SERVICE_BINDING_PROTOCOL GUID de-
ﬁne misses _GUIDFeb. 12, 2009
2.2A 404 RemoveConstraint form EFI_TIME.YearComment Feb. 12, 2009
2.2A 400 FreePool() description error Feb. 12, 2009
2.2A 393 UEFI 2.1/2.2Boot ManagerBehaviorClariﬁcation Feb. 12, 2009
2.2A 392 MBR errata in UEFI 2.2 Feb. 12, 2009
2.2A 391 Polarity of INCONSISTENT_IF and NO_SUBMIT_IF IFR
opcodes wrongFeb. 12, 2009
2.2A 390 UEFI 2.2 Miscellaneous HII-related errata Feb. 12, 2009
2.2A 389 UEFI 2.2 HII-Related Formatting Issues Feb. 12, 2009
2.2A 387 UEFI 2.1/UEFI 2.2A (ch. 12) Feb. 12, 2009
2.2A 384 Fix HII package description omission. Feb. 12, 2009
2.2A 379 UEFI 2.1/UEFI 2.2 HII-Related Errata Feb. 12, 2009
2.2A 378 UEFI 2.1 & UEFI 2.2 HIICallbackClariﬁcations Feb. 12, 2009
2.2A 377 MissingBLTBuffer ﬁgure. Feb. 12, 2009
2.2A 375 Extra periods errata in UEFI 2.2 Feb. 12, 2009
2.2A 374 UEFI 2.1 & UEFI 2.2A (10.7-10.10) Feb. 12, 2009
2.2A 373 UEFI 2.2,Chs. 9.5 & 9.6.2 & 9.6.3 (Device Path) Errata Feb. 12, 2009
2.2A 372 UEFI 2.2 remove “Draft for Review” Feb. 12, 2009
2.2A 371 UEFI 2.1 & UEFI 2.2 Typos (ch. 10) Feb. 12, 2009
2.2A 370 EFI_SYSTEM_TABLE Errata (UEFI 2.1/UEFI 2.2) Feb. 12, 2009
CONTENTS lxxixUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

2.2A 368 EFI_FONT_DISPLAY_INFO.FontInfo description incorrect Feb. 12, 2009
2.2A 366 UEFI 2.x: Erroneous refer-
ences to EFI_BOOT_SERVICES_TABLE,
EFI_RUNTIME_SERVICES_TABLEFeb. 12, 2009
2.2A 364 UEFI 2.2 Typos & Formatting Issues (ch. 9) Feb. 12, 2009
2.2A 362 UEFI 2.2 Typos (Next) Feb. 12, 2009
2.2A 361 UEFI 2.2 Typos & Formatting Issues Feb. 12, 2009
2.2A 359 TPL Table Feb. 12, 2009
2.2A 358 Missing signature for UEFI 2.2. Feb. 12, 2009
2.2 398 Update to M348 to ﬁx small typo Jan. 11, 2009
2.2 397 PCICopyMem() misspelling Jan. 11, 2009
2.2 394 Omission in EFI_USB2_HC_PROTOCOL Jan. 11, 2009
2.2 357Clarify EFI_IFR_DISABLE_IFBehavior with regard to dy-
namic valuesJan. 11, 2009
2.2 351 Fix an unaligned ﬁeld in a device path Jan. 11, 2009
2.2 350 EFI_HII_STRING_PROTOCOL Typos Jan. 11, 2009
2.2 348 EFI_IFR_RESET_BUTTON is incorrectly listed as a ques-
tionJan. 11, 2009
2.2 347 Replace ﬁrst paragraph of the “Description” section for the
ExitBootServices()Sept. 25, 2008
2.2 346 Nest, Sections 10.11 & 10.12 Under 10.10 Sept. 25, 2008
2.2 344Correct missing statusCodes returned section for Form() in
EFI_USER_CREDENTIAL_PROTOCOL.Sept. 25, 2008
2.2 343Correct missing parameter for User() function in
EFI_USER_CREDENTIAL_PROTOCOLSept. 25, 2008
2.2 340 UEFI 2.2 Editorial / Formatting Issues Sept. 25, 2008
2.2 339 Update missing TPL restrictions Sept. 25, 2008
2.2 337 Replace the EFI_CRYPT_HANDLE reference (in the IPSsec
API)with a self-contained, independent deﬁnition.Sept. 25, 2008
2.2 335 User Authentication errata Sept. 25, 2008
2.2 334 Standardized “Unicode” References Jan. 11, 2009
2.2 333Correct the incorrect ‘;’ at the end of EFI_GUID #deﬁnes Sept. 25, 2008
2.2 332Correct SendForm description Type, PackageGuid and Form-
setGuid parametersSept. 25, 2008
2.2 331 Deﬁnition for EFI_BROWSER_ACTION and the related
#deﬁnes were not present–Insert.Sept. 25, 2008
2.2 330 EFI_IFR_REF:ChangeCross reference to a question Sept. 25, 2008
2.2 327Clarify the support in DHCP4 protocol for “Inform”
(DHCPINFORM) messages.Sept. 25, 2008
2.2 325 MinorCorrection 28.3.8.3.20 July 25, 2008
2.2 324 ATA Pass-Thru ECR Update July 25, 2008
2.2 323 VLAN modiﬁcationBecause of IPV6 July 25, 2008
2.2 322Chapter 2 updates for IP6 net stack July 25, 2008
2.2 321Enable PCIe 2.0 andBeyond support in the UEFI error records July 25, 2008
2.2 320Clarifcation for WIN_CERTIFICATE types & relationship
with signature database typesJuly 25, 2008
2.2 319 UEFI IPSec protocol July 25, 2008
2.2 315 EFI TCP6 Protocol July 25, 2008
2.2 314 EFI MTFTP6 Protocol July 25, 2008
2.2 313 EFI IPv6Conﬁguration Protocol July 25, 2008
2.2 312 EFI IPv6 Protocol July 25, 2008
CONTENTS lxxxUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.2 311EFI DHCPv6 Protocol July 25, 2008
2.2 310 EFI UDPv6 Protocol July 25, 2008
2.2 309 IPv6 Address display formatClariﬁcation July 25, 2008
2.2 306 Some errata to the animation support July 25, 2008
2.2 304 Errata to UpdateCapsule() July 25, 2008
2.2 303 Add ability to have aCapsule that initiates a reset & doesn’t
return to theCallerJuly 25, 2008
2.2 301 Errata to the Authentication Protocol July 25, 2008
2.2 300 MTFTP errata July 25, 2008
2.2 299 PIWG Firmware File/Firmware V olume Typo Errata July 25, 2008
2.2 294 LocateDevicePath with multi-instance device path July 25, 2008
2.2 291 HII Errata / Update July 25, 2008
2.2 288 Additional wording ﬁxes for GPT Entry AttributeBit 1 July 25, 2008
2.2 282 Updated Requirements Section For ATA Pass Through
(M242)July 25, 2008
2.2 279 Firmware/OS Trusted Key Exchange and Image Validation July 25, 2008
2.2 242 UEFI ATA Pass-Through Protocol July 25, 2008
2.2 237 UEFI User Identiﬁcation Proposal (from USST) July 25, 2008
2.2 215 new Start() RemainingDevicePath Syntax July 25, 2008
2.2 212 UEFI HII Standards Mapping July 25, 2008
2.2 211UEFI Setup Question / Form Access Update July 25, 2008
2.2 210 UEFI HII Animation addition July 25, 2008
2.2 202 EAP Management July 25, 2008
2.2 201EAP July 25, 2008
2.2 200 VLAN July 25, 2008
2.2 199 FTP API July 25, 2008
2.2 198 GUID Partition Entry AttributesClariﬁcation and Deﬁnition July 25, 2008
2.2 169 EFI Driver Health Protocol July 25, 2008
2.2 157 Floating-Point ABIChanges For X86, X64 & Itanium July 25, 2008
2.1C Re-format Revision History fromBulleted lists to one row per
Mantis ticket/ EngineeringChange RequestJune 5, 2008
2.1C 60 iSCSI Device Path Update June 5, 2008
2.1C 59 Add returnCode to Diagnostics Protocol June 5, 2008
2.1C 58 Language update for EﬁReservedMemory type usage June 5, 2008
2.1C 57Clarify text for Extended SCSI Pass Thru Proto-
col.GetNextTargetLun()June 5, 2008
2.1C 56Clariﬁcation on ResetSystem June 5, 2008
2.1C 55Clariﬁcation on UpdateCapsule June 5, 2008
2.1C 54 ACPI Table Protocol GUID Update June 5, 2008
2.1C 52 New GUID for Driver Diagnostics and DriverConﬁguration
Protocols with new GUIDJune 5, 2008
2.1C 283 Minor update toClarify a typedef/returnCode in HII June 5, 2008
2.1C 281 Runtime memory allocation June 5, 2008
2.1C 280 Some minor errata to keyboard related topics June 5, 2008
2.1C 278Change references to EFI_SIMPLE_INPUT_PROTOCOL
into EFI_SIMPLE_TEXT_INPUT_PROTOCOLJune 5, 2008
2.1C 266 PKCS11.5 structure does notCorrectly specify the portion of
theCited RFC that pertains to theCertiﬁcate struct/algorithmJune 5, 2008
2.1C 249 Latest update to UCST Errata list June 5, 2008
2.1C 248Correction to text inChapter 8.2 of UEFI 2.1B June 5, 2008
CONTENTS lxxxiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.1C 246 New returnCode June 5, 2008
2.1C 245 Remove extraneous text inChapter 29 June 5, 2008
2.1C 244 Replace references to EFI_FIRMWARE_VOLUME_INFO_
PPI with EFI_PEI_FIRMWARE_VOLUME_INFO_PPIJune 5, 2008
2.1C 221ImageBlock Structure name typos in 27.3.7.2 June 5, 2008
2.1C 220 Replace references to RFC 3066 to RFC 4646 June 5, 2008
2.1C 219 IA-32 and x64 stack need toBe 16-byte aligned June 5, 2008
2.1C 218 SATA update to section 9.3.5.6 June 5, 2008
2.1C 217 EFI_PLATFORM_TO_DR
IVER_CONFIGURATION_PROTOCOL.Query() UpdateJune 5, 2008
2.1C 216 UEFI 2.1 textCorrections June 5, 2008
2.1C 214 Device_IO + typos June 5, 2008
2.1C 213 UEFI HII Errata June 5, 2008
2.1C 209 ESP number/locationClariﬁcations June 5, 2008
2.1C 208 Driver Protocol Names and GUIDs June 5, 2008
2.1C 207 Updated Wording for the File Path June 5, 2008
2.1C 206Clarify return values for extended scsi passthru protocol June 5, 2008
2.1C 203 Platform Error Record - x64 register state errata June 5, 2008
2.1C 193 Loaded Image device paths for EFI Drivers loaded from PCI
Option ROMsJune 5, 2008
2.1C 189 Graphics Output ProtocolClariﬁcation June 5, 2008
2.1B 51 Long physicalBlocks updates December 11, 2007
2.1B 205Change LoadImage() parameter name from
FilePath to DevicePath; endsConfusion with
EFI_LOADED_IMAGE_PROTOCOLDecember 11, 2007
2.1B 197 EFI Loaded Image Device Path Protocol December 11, 2007
2.1B 190 Extensive errata form UCST including OPCodesChanges ro
resolveConﬂicts.December 11, 2007
2.1B 187Clarify input protocols. December 11, 2007
2.1B 186Change PCIR struct to match PCI FW Spec 3.0 December 11, 2007
2.1B 185Change EFI term to UEFI forConsistency December 11, 2007
2.1B 184 SNIA/DDF Wording Update December 11, 2007
2.1B 182Clarify EFI_MTFTP4_TOKEN December 11, 2007
2.1B 181Correct MNP GUIDCollision December 11, 2007
2.1B 177 remove ending paragraph (editing text) in section 9.6 December 11, 2007
2.1B 175 Update to SendForm API December 11, 2007
2.1B 174 Error record addition for dma remapping units December 11, 2007
2.1B 173 MinorChanges to the description of two of the ﬁelds in
theCommon Platform Error Record, in Appendix NDecember 11, 2007
2.1B 172 Typo for ResetSystem() December 11, 2007
2.1B 170 (Addition of) Driver Family Override Protocol December 11, 2007
2.1B 168 Remove LOAD_OPTION_GRAPHICS December 11, 2007
2.1B 165 Fix EFI_GRAPHICS_OUTPUT_PIXEL December 11, 2007
2.1B 164 Update to USB2_HC_PROTOCOL Table December 11, 2007
2.1B 162 UEFI PIWG Device Path Errata December 11, 2007
2.1B 160Clean up references to PCIR December 11, 2007
2.1B 158 Errata to the UEFI 2.1Conﬁguration sections December 11, 2007
2.1B 156 SendForm API Errata December 11, 2007
2.1B 159 Adjust some of the #deﬁne names in the Simple Text Input
Ex protocolDecember 11, 2007
2.1A UEFI 2.1 incorporating Errata through 4-27-07 April 27, 2007
CONTENTS lxxxiiUniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.1 Second release January 23, 2007
2.0 First release of speciﬁcation. January 31, 2006
CONTENTS lxxxiiiCHAPTER
ONE
INTRODUCTION
This Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation describes an interface between the operating system

ONE
(OS) and the platform ﬁrmware. UEFI was preceded by the Extensible Firmware Interface Speciﬁcation 1.10 (EFI). As
a result, some code and certain protocol names retain the EFI designation. Unless otherwise noted, EFI designations
in this speciﬁcation may be assumed to be part of UEFI.
The interface is in the form of data tables that contain platform-related information, and boot and runtime service calls
that are available to the OS loader and the OS. Together, these provide a standard environment for booting an OS.
This speciﬁcation is designed as a pure interface speciﬁcation. As such, the speciﬁcation deﬁnes the set of interfaces
and structures that platform ﬁrmware must implement. Similarly, the speciﬁcation deﬁnes the set of interfaces and
structures that the OS may use in booting. How either the ﬁrmware developer chooses to implement the required
elements or the OS developer chooses to make use of those interfaces and structures is an implementation decision left
for the developer.
The intent of this speciﬁcation is to deﬁne a way for the OS and platform ﬁrmware to communicate only information
necessary to support the OS boot process. This is accomplished through a formal and complete abstract speciﬁcation
of the software-visible interface presented to the OS by the platform and ﬁrmware.
Using this formal deﬁnition, a shrink-wrap OS intended to run on platforms compatible with supported processor
speciﬁcations will be able to boot on a variety of system designs without further platform or OS customization. The
deﬁnition will also allow for platform innovation to introduce new features and functionality that enhance platform
capability without requiring new code to be written in the OS boot sequence.
Furthermore, an abstract speciﬁcation opens a route to replace legacy devices and ﬁrmware code over time. New
device types and associated code can provide equivalent functionality through the same deﬁned abstract interface,
again without impact on the OS boot support code.
The speciﬁcation is applicable to a full range of hardware platforms from mobile systems to servers. The speciﬁcation
provides a core set of services along with a selection of protocol interfaces. The selection of protocol interfaces can
evolve over time to be optimized for various platform market segments. At the same time, the speciﬁcation allows
maximum extensibility and customization abilities for OEMs to allow differentiation. In this, the purpose of UEFI is
to deﬁne an evolutionary path from the traditional “PC-AT”-style boot world into a legacy-API free environment.
1.1 Principle of Inclusive Terminology
The UEFI Forum follows a Principle of Inclusive Terminology in building and maintaining content for speciﬁcations.
This means that efforts are made to ensure that all wording is perceived or likely to be perceived as welcoming by
everyone regardless of personal characteristics. In some cases, the Forum acknowledges that wording derived from
earlier work, for example references to legacy speciﬁcations not controlled by the Forum, may not follow this principle.
In order to preserve compatibility for code that reads on legacy speciﬁcations, particularly where that speciﬁcation is
no longer under maintenance or development, language in this speciﬁcation may appear out of sync with the Principle.
The Forum is resolved to work with other standards development bodies to eliminate such examples over time. In
the meanwhile, by acknowledging and calling attention to this issue the hope is to promote discussion and action
1Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
towards more complete use of Inclusive Language reﬂective of the diverse and innovative population of the technical
community that works on standards.
1.2 UEFI Driver Model Extensions
Access to boot devices is provided through a set of protocol interfaces. One purpose of the UEFI Driver Model is to
provide a replacement for “PC-AT”-style option ROMs. It is important to point out that drivers written to the UEFI
Driver Model are designed to access boot devices in the preboot environment. They are not designed to replace the
high-performance, OS-speciﬁc drivers.
The UEFI Driver Model is designed to support the execution of modular pieces of code, also known as drivers, that
run in the preboot environment. These drivers may manage or control hardware buses and devices on the platform, or
they may provide some software-derived, platform-speciﬁc service.
The UEFI Driver Model also contains information required by UEFI driver writers to design and implement any
combination of bus drivers and device drivers that a platform might need to boot a UEFI-compliant OS.
The UEFI Driver Model is designed to be generic and can be adapted to any type of bus or device. The UEFI Spec-
iﬁcation describes how to write PCI bus drivers, PCI device drivers, USB bus drivers, USB device drivers, and SCSI
drivers. Additional details are provided that allow UEFI drivers to be stored in PCI option ROMs, while maintaining
compatibility with legacy option ROM images.
One of the design goals in the UEFI Speciﬁcation is keeping the driver images as small as possible. However, if a
driver is required to support multiple processor architectures, a driver object ﬁle would also be required to be shipped
for each supported processor architecture. To address this space issue, this speciﬁcation also deﬁnes the EFI Byte
Code Virtual Machine . A UEFI driver can be compiled into a single EFI Byte Code object ﬁle. UEFI Speciﬁcation-
complaint ﬁrmware must contain an EFI Byte Code interpreter. This allows a single EFI Byte Code object ﬁle that
supports multiple processor architectures to be shipped. Another space saving technique is the use of compression.
This speciﬁcation deﬁnes compression and decompression algorithms that may be used to reduce the size of UEFI
Drivers, and thus reduce the overhead when UEFI Drivers are stored in ROM devices.
The information contained in the UEFI Speciﬁcation can be used by OSVs, IHVs, OEMs, and ﬁrmware vendors to
design and implement ﬁrmware conforming to this speciﬁcation, drivers that produce standard protocol interfaces, and
operating system loaders that can be used to boot UEFI-compliant operating systems.
1.3 Organization
The high-level organization of this speciﬁcation is as follows:
Table 1.1: Organization of this speciﬁcation
Section(s) Description
Introduction / Overview Introduces the UEFI Speciﬁcation, and describes the major components of UEFI.
Boot Manager Manager used to load drivers and applications written to this speciﬁcation.
EFI System Table and Par-
titionsDescribes an EFI System Table that is passed to every compliant driver and applica-
tion, and deﬁnes a GUID-based partitioning scheme.
Block Transition Table A layout and set of rules for doing block I/O that provide power fail write atomicity
of a single block.
Boot Services Contains the deﬁnitions of the fundamental services that are present in a UEFI-
compliant system before an OS is booted.
Runtime Services Contains deﬁnitions for the fundamental services that are present in a compliant sys-
tem before and after an OS is booted.
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Table 1.1 – continued from previous page
Protocols
• The EFI Loaded Image Protocol describes a UEFI Image that has been loaded into
memory.
• The Device Path Protocol provides the information needed to construct and manage
device paths in the UEFI environment.
• The UEFI Driver Model describes a set of services and protocols that apply to
every bus and device type.
• The Console Support Protocol deﬁnes I/O protocols that handle input and output of
text-based information intended for the system user while executing in the boot
services environment.
• The Media Access Protocol deﬁnes the Load File protocol, ﬁle system format and
media formats for handling removable media.
• PCI Bus Support Protocols deﬁne PCI Bus Drivers, PCI Device Drivers, and PCI
Option ROM layouts. The protocols described include the PCI Root Bridge I/O
Protocol and the PCI I/O Protocol.
• SCSI Driver Models and Bus support deﬁnes the SCSI I/O Protocol and the
Extended SCSI Pass Thru Protocol that is used to abstract access to a SCSI channel
that is produced by a SCSI host controller.
• The iSCSI protocol deﬁnes a transport for SCSI data over TCP/IP.
• The USB Support Protocol deﬁnes USB Bus Drivers and USB Device Drivers.
• Debugger Support Protocols describe an optional set of protocols that provide the
services required to implement a source-level debugger for the UEFI environment.
• The Compression Algorithm Speciﬁcation describes the
compression/decompression algorithm in detail, plus a standard EFI decompression
interface for use at boot time.
• ACPI Protocols may be used to install or remove an ACPI table from a platform.
• String Services: the Unicode Collation protocol allows code running in the boot

services environment to perform lexical comparison functions on Unicode strings for
given languages; the Regular Expression Protocol is used to match Unicode strings
against Regular Expression patterns.
EFI Byte Code Virtual
MachineDeﬁnes the EFI Byte Code virtual processor and its instruction set. It also deﬁnes
how EBC object ﬁles are loaded into memory, and the mechanism fo transitioning
from native code to EBC code and back to native code.
Firmware Update and Re-
portingProvides an abstraction for devices to provide ﬁrmware management support.
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Network Protocols
• SNP, PXE, BIS, and HTTP Boot protocols deﬁne the protocols that provide access
to network devices while executing in the UEFI boot services environment.
• Managed Network protocols deﬁne the EFI Managed Network Protocol, which
provides raw (unformatted) asynchronous network packet I/O services and Managed
Network Service Binding Protocol, used to locate communication devices that are
supported by an MNP driver.
• VLAN, EAP, Wi-Fi and Supplicant protocols deﬁne a protocol that is to provide a
manageability interface for VLAN conﬁgurations.
• Bluetooth protocol deﬁnitions.
• TCP, IP, PIPsec, FTP, GTLS, and Conﬁgurations protocols deﬁne the EFI TCPv4
(Transmission Control Protocol version 4) Protocol and the EFI IPv4 (Internet
Protocol version 4) Protocol.
• ARP, DHCP, DNS, HTTP, and REST protocols deﬁne the EFI Address Resolution
Protocol (ARP) Protocol interface and the EFI DHCPv4 Protocol.
• UDP and MTFTP protocols deﬁne the EFI UDPv4 (User Datagram Protocol
version 4) Protocol that interfaces over the EFI IPv4 Protocol and deﬁnes the EFI
MTFTPv4 Protocol interface that is built on the EFI UDPv4 Protocol.
Secure Boot and Driver
SigningDescribes Secure Boot and a means of generating a digital signature for UEFI.
Human Interface Infras-
tructure • Deﬁnes the core code and (HII) services that are required for an implementation of
the Human Interface Infrastructure (HII), including basic mechanisms for managing
user input and code deﬁnitions for related protocols.
• Describes the data and APIs used to manage the system’s conﬁguration: the actual
data that describes the knobs and settings.
User Identiﬁcation Describes services that describe the current user of the platform.
Secure Technologies Describes the protocols for utilizing security technologies, including cryptographic
hashing and key management.
Miscellaneous Protocols The Timestamp protocol provides a platform independent interface for retrieving a
high resolution timestamp counter. The Reset Notiﬁcation Protocol provides services
to register for a notiﬁcation when ResetSystem is called.
1.3. Organization 4Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Appendices
• GUID and Time Formats.
• Console requirements for a basic text-based console required by EFI-conformant
systems to provide communication capabilities.
• Device Path examples of use of the data structures that deﬁne various hardware
devices to the boot services.
• Status Codes lists success, error, and warning codes returned by UEFI interfaces.
• Universal Network Driver Interfaces deﬁnes the 32/64-bit hardware and software
Universal Network Driver Interfaces (UNDIs).
• Using the Simple Pointer Protocol.
• Using the EFI Extended SCISI Pass-thru Protocol.
• Compression Source Code for an implementation of the Compression Algorithm.
• Decompression Source Code for an implementation of the EFI Decompression
Algorithm.
• The EFI Byte Code Virtual Machine Opcode List provides a summary of the
corresponding instruction set.
• Alphabetic Function Lists identify all UEFI interface functions alphabetically.
• EFI 1.10 Protocol Changes and Depreciation List identiﬁes the Protocol, GUID,
and revision identiﬁer name changes and the deprecated protocols compared to the
EFI Speciﬁcation 1.10.
• Formats: Language Codes and Language Code Arrays list the formats for language
codes and language code arrays.
• The Common Platform Error Record describes the common platform error record
format for representing platform hardware errors.
• The UEFI ACPI Data Table deﬁnes the UEFI ACPI table format.
• Hardware Error Record Persistence Usage.
• References
• Glossary
Index Provides an index to the key terms and concepts in the speciﬁcation.
1.4 Goals
The “PC-AT” boot environment presents signiﬁcant challenges to innovation within the industry. Each new platform
capability or hardware innovation requires ﬁrmware developers to craft increasingly complex solutions, and often
requires OS developers to make changes to their boot code before customers can beneﬁt from the innovation. This can
be a time-consuming process requiring a signiﬁcant investment of resources.
The primary goal of the UEFI speciﬁcation is to deﬁne an alternative boot environment that can alleviate some of these
considerations. In this goal, the speciﬁcation is similar to other existing boot speciﬁcations. The main properties of
this speciﬁcation can be summarized by these attributes:
•Coherent, scalable platform environment . The speciﬁcation deﬁnes a complete solution for the ﬁrmware to
describe all platform features and surface platform capabilities to the OS during the boot process. The deﬁnitions
are rich enough to cover a range of contemporary processor designs.
•Abstraction of the OS from the ﬁrmware . The speciﬁcation deﬁnes interfaces to platform capabilities. Through
the use of abstract interfaces, the speciﬁcation allows the OS loader to be constructed with far less knowledge
of the platform and ﬁrmware that underlie those interfaces. The interfaces represent a well-deﬁned and stable
boundary between the underlying platform and ﬁrmware implementation and the OS loader. Such a bound-
1.4. Goals 5Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ary allows the underlying ﬁrmware and the OS loader to change provided both limit their interactions to the
deﬁned interfaces. The standard interfaces deﬁned in this speciﬁcation may be complemented by companion
OS/ﬁrmware interfaces such as those deﬁned by the ACPI speciﬁcation. On the other hand, ﬁrmware-internal
interfaces, such as those deﬁned by the PI Speciﬁcation, are produced and consumed by ﬁrmware only, and are
not considered interfaces that a UEFI aware OS can connect to, interact with, or depend on.
•Reasonable device abstraction free of legacy interfaces . “PC-AT” BIOS interfaces require the OS loader to
have speciﬁc knowledge of the workings of certain hardware devices. This speciﬁcation provides OS loader
developers with something different: abstract interfaces that make it possible to build code that works on a
range of underlying hardware devices without having explicit knowledge of the speciﬁcs for each device in the
range.
•Abstraction of Option ROMs from the ﬁrmware . This speciﬁcation deﬁnes interfaces to platform capabilities
including standard bus types such as PCI, USB, and SCSI. The list of supported bus types may grow over time,
so a mechanism to extend to future bus types is included. These deﬁned interfaces, and the ability to extend
to future bus types, are components of the UEFI Driver Model . One purpose of the UEFI Driver Model is to
solve a wide range of issues that are present in existing “PC-AT” option ROMs. Like OS loaders, drivers use the
abstract interfaces so device drivers and bus drivers can be constructed with far less knowledge of the platform
and ﬁrmware that underlie those interfaces.
•Architecturally shareable system partition . Initiatives to expand platform capabilities and add new devices
often require software support. In many cases, when these platform innovations are activated before the OS
takes control of the platform, they must be supported by code that is speciﬁc to the platform rather than to
the customer’s choice of OS. The traditional approach to this problem has been to embed code in the platform
during manufacturing (for example, in ﬂash memory devices). Demand for such persistent storage is increasing
at a rapid rate. This speciﬁcation deﬁnes persistent store on large mass storage media types for use by platform
support code extensions to supplement the traditional approach. The deﬁnition of how this works is made clear
in the speciﬁcation to ensure that ﬁrmware developers, OEMs, operating system vendors, and perhaps even third
parties can share the space safely while adding to platform capability.
Deﬁning a boot environment that delivers these attributes could be accomplished in many ways. Indeed, several
alternatives, perhaps viable from an academic point of view, already existed at the time this speciﬁcation was written.
These alternatives, however, typically presented high barriers to entry given the current infrastructure capabilities

surrounding supported processor platforms. This speciﬁcation is intended to deliver the attributes listed above, while
also recognizing the unique needs of an industry that has considerable investment in compatibility and a large installed
base of systems that cannot be abandoned summarily. These needs drive the requirements for the additional attributes
embodied in this speciﬁcation:
•Evolutionary, not revolutionary . The interfaces and structures in the speciﬁcation are designed to reduce the
burden of an initial implementation as much as possible. While care has been taken to ensure that appropriate
abstractions are maintained in the interfaces themselves, the design also ensures that reuse of BIOS code to
implement the interfaces is possible with a minimum of additional coding effort. In other words, on PC-AT
platforms the speciﬁcation can be implemented initially as a thin interface layer over an underlying implemen-
tation based on existing code. At the same time, introduction of the abstract interfaces provides for migration
away from legacy code in the future. Once the abstraction is established as the means for the ﬁrmware and OS
loader to interact during boot, developers are free to replace legacy code underneath the abstract interfaces at
leisure. A similar migration for hardware legacy is also possible. Since the abstractions hide the speciﬁcs of
devices, it is possible to remove underlying hardware, and replace it with new hardware that provides improved
functionality, reduced cost, or both. Clearly this requires that new platform ﬁrmware be written to support the
device and present it to the OS loader via the abstract interfaces. However, without the interface abstraction,
removal of the legacy device might not be possible at all.
•Compatibility by design . The design of the system partition structures also preserves all the structures that are
currently used in the “PC-AT” boot environment. Thus, it is a simple matter to construct a single system that is
capable of booting a legacy OS or an EFI-aware OS from the same disk.
•Simpliﬁes addition of OS-neutral platform value-add . The speciﬁcation deﬁnes an open, extensible interface
1.4. Goals 6Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
that lends itself to the creation of platform “drivers.” These may be analogous to OS drivers, providing support
for new device types during the boot process, or they may be used to implement enhanced platform capabilities,
such as fault tolerance or security. Furthermore, this ability to extend platform capability is designed into the
speciﬁcation from the outset. This is intended to help developers avoid many of the frustrations inherent in
trying to squeeze new code into the traditional BIOS environment. As a result of the inclusion of interfaces to
add new protocols, OEMs or ﬁrmware developers have an infrastructure to add capability to the platform in a
modular way. Such drivers may potentially be implemented using high-level coding languages because of the
calling conventions and environment deﬁned in the speciﬁcation. This in turn may help to reduce the difﬁculty
and cost of innovation. The option of a system partition provides an alternative to nonvolatile memory storage
for such extensions.
•Built on existing investment . Where possible, the speciﬁcation avoids redeﬁning interfaces and structures in
areas where existing industry speciﬁcations provide adequate coverage. For example, the ACPI speciﬁcation
provides the OS with all the information necessary to discover and conﬁgure platform resources. Again, this
philosophical choice for the design of the speciﬁcation is intended to keep barriers to its adoption as low as
possible.
1.5 Target Audience
This document is intended for the following readers:
• IHVs and OEMs who will be implementing UEFI drivers.
• OEMs who will be creating supported processor platforms intended to boot shrink-wrap operating systems.
• BIOS developers, either those who create general-purpose BIOS and other ﬁrmware products or those who
modify these products for use in supported processor-based products.
• Operating system developers who will be adapting their shrink-wrap operating system products to run on sup-
ported processor-based platforms.
1.6 UEFI Design Overview
The design of UEFI is based on the following fundamental elements:
•Reuse of existing table-based interfaces . In order to preserve investment in existing infrastructure support code,
both in the OS and ﬁrmware, a number of existing speciﬁcations that are commonly implemented on platforms
compatible with supported processor speciﬁcations must be implemented on platforms wishing to comply with
the UEFI speciﬁcation. (For additional information, see References .)
•System partition . The System partition deﬁnes a partition and ﬁle system that are designed to allow safe sharing
between multiple vendors, and for different purposes. The ability to include a separate, sharable system partition
presents an opportunity to increase platform value-add without signiﬁcantly growing the need for nonvolatile
platform memory.
•Boot services . Boot services provide interfaces for devices and system functionality that can be used during
boot time. Device access is abstracted through “handles” and “protocols.” This facilitates reuse of investment
in existing BIOS code by keeping underlying implementation requirements out of the speciﬁcation without
burdening the consumer accessing the device.
•Runtime services . A minimal set of runtime services is presented to ensure appropriate abstraction of base
platform hardware resources that may be needed by the OS during its normal operations.
The Figure below shows the principal components of UEFI and their relationship to platform hardware and OS soft-
ware.
1.5. Target Audience 7Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 1.1: UEFI Conceptual Overview
This Figure illustrates the interactions of the various components of an UEFI speciﬁcation-compliant system that are
used to accomplish platform and OS boot.
The platform ﬁrmware is able to retrieve the OS loader image from the System Partition. The speciﬁcation provides
for a variety of mass storage device types including disk, CD-ROM, and DVD as well as remote boot via a network.
Through the extensible protocol interfaces, it is possible to add other boot media types, although these may require OS
loader modiﬁcations if they require use of protocols other than those deﬁned in this document.
Once started, the OS loader continues to boot the complete operating system. To do so, it may use the EFI boot services
and interfaces deﬁned by this or other required speciﬁcations to survey, comprehend, and initialize the various platform
components and the OS software that manages them. EFI runtime services are also available to the OS loader during
the boot phase.
1.7 UEFI Driver Model
This section describes the goals of a driver model for ﬁrmware conforming to this speciﬁcation. The goal is for
this driver model to provide a mechanism for implementing bus drivers and device drivers for all types of buses and
devices. At the time of writing, supported bus types include PCI, USB, and so on.
As hardware architectures continue to evolve, the number and types of buses present in platforms are increasing. This
trend is especially true in high-end servers. However, a more diverse set of bus types is being designed into desktop
and mobile systems and even some embedded systems. This increasing complexity means that a simple method for
describing and managing all the buses and devices in a platform is required in the preboot environment. The UEFI
Driver Model provides this simple method in the form of protocols services and boot services.
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1.7.1 UEFI Driver Model Goals
The UEFI Driver Model has the following goals:
•Compatible — Drivers conforming to this speciﬁcation must maintain compatibility with the EFI 1.10 Speciﬁ-
cation and the UEFI Speciﬁcation . This means that the UEFI Driver Model takes advantage of the extensibility
mechanisms in the UEFI 2. 0 Speciﬁcation to add the required functionality.
•Simple — Drivers that conform to this speciﬁcation must be simple to implement and simple to maintain. The
UEFI Driver Model must allow a driver writer to concentrate on the speciﬁc device for which the driver is
being developed. A driver should not be concerned with platform policy or platform management issues. These
considerations should be left to the system ﬁrmware.
•Scalable — The UEFI Driver Model must be able to adapt to all types of platforms. These platforms include
embedded systems, mobile, and desktop systems, as well as workstations and servers.
•Flexible — The UEFI Driver Model must support the ability to enumerate all the devices, or to enumerate only

those devices required to boot the required OS. The minimum device enumeration provides support for more
rapid boot capability, and the full device enumeration provides the ability to perform OS installations, system
maintenance, or system diagnostics on any boot device present in the system.
•Extensible — The UEFI Driver Model must be able to extend to future bus types as they are deﬁned.
•Portable — Drivers written to the UEFI Driver Model processor architectures.
•Interoperable — Drivers must coexist with other drivers and system ﬁrmware and must do so without generating
resource conﬂicts.
•Describe complex bus hierarchies — The UEFI Driver Model must be able to describe a variety of bus topologies
from very simple single bus platforms to very complex platforms containing many buses of various types.
•Small driver footprint — The size of executables produced by the UEFI Driver Model must be minimized to
reduce the overall platform cost. While ﬂexibility and extensibility are goals, the additional overhead required
to support these must be kept to a minimum to prevent the size of ﬁrmware components from becoming unman-
ageable.
•Address legacy option rom issues — The UEFI Driver Model must directly address and solve the constraints
and limitations of legacy option ROMs. Speciﬁcally, it must be possible to build add-in cards that support
both UEFI drivers and legacy option ROMs, where such cards can execute in both legacy BIOS systems and
UEFI-conforming platforms, without modiﬁcations to the code carried on the card. The solution must provide
an evolutionary path to migrate from legacy option ROMs driver to UEFI drivers.
1.7.2 Legacy Option ROM Issues
This idea of supporting a driver model came from feedback on the UEFI Speciﬁcation that provided a clear, market-
driven requirement for an alternative to the legacy option ROM (sometimes also referred to as an expansion ROM).
The perception is that the advent of the UEFI Speciﬁcation represents a chance to escape the limitations implicit in the
construction and operation of legacy option ROM images by replacing them with an alternative mechanism that works
within the framework of the UEFI Speciﬁcation .
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1.8 Migration Requirements
Migration requirements cover the transition period from initial implementation of this speciﬁcation to a future time
when all platforms and operating systems implement to this speciﬁcation. During this period, two major compatibility
considerations are important:
• The ability to continue booting legacy operating systems;
• The ability to implement UEFI on existing platforms by reusing as much existing ﬁrmware code to keep devel-
opment resource and time requirements to a minimum.
1.8.1 Legacy Operating System Support
The UEFI speciﬁcation represents the preferred means for a shrink-wrap OS and ﬁrmware to communicate during
the boot process. However, choosing to make a platform that complies with this speciﬁcation in no way precludes a
platform from also supporting existing legacy OS binaries that have no knowledge of the UEFI speciﬁcation.
The UEFI speciﬁcation does not restrict a platform designer who chooses to support both the UEFI speciﬁcation
and a more traditional “PC-AT” boot infrastructure. If such a legacy infrastructure is to be implemented, it should
be developed in accordance with existing industry practice that is deﬁned outside the scope of this speciﬁcation. The
choice of legacy operating systems that are supported on any given platform is left to the manufacturer of that platform.
1.8.2 Supporting the UEFI Speciﬁcation on a Legacy Platform
The UEFI speciﬁcation has been carefully designed to allow for existing systems to be extended to support it with a
minimum of development effort. In particular, the abstract structures and services deﬁned in the UEFI speciﬁcation
can all be supported on legacy platforms.
For example, to accomplish such support on an existing and supported 32-bit-based platform that uses traditional BIOS
to support operating system boot, an additional layer of ﬁrmware code would need to be provided. This extra code
would be required to translate existing interfaces for services and devices into support for the abstractions deﬁned in
this speciﬁcation.
1.9 Conventions Used in this Document
This document uses typographic and illustrative conventions described below.
1.9.1 Data Structure Descriptions
Supported processors are “little endian” machines. This distinction means that the low-order byte of a multibyte data
item in memory is at the lowest address, while the high-order byte is at the highest address. Some supported 64-bit
processors may be conﬁgured for both “little endian” and “big endian” operation. All implementations designed to
conform to this speciﬁcation use “little endian” operation.
In some memory layout descriptions, certain ﬁelds are marked reserved . Software must initialize such ﬁelds to zero
and ignore them when read. On an update operation, software must preserve any reserved ﬁeld.
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1.9.2 Protocol Descriptions
A protocol description generally has the following format:
Protocol Name: The formal name of the protocol interface.
Summary: A brief description of the protocol interface.
GUID: The 128-bit Globally Unique Identiﬁer (GUID) for the protocol interface.
Protocol Interface Structure: A “C-style” data structure deﬁnition containing the procedures and data ﬁelds pro-
duced by this protocol interface.
Parameters: A brief description of each ﬁeld in the protocol interface structure.
Description: A description of the functionality provided by the interface, including any limitations and caveats of
which the caller should be aware.
Related Deﬁnitions: The type declarations and constants that are used in the protocol interface structure or any of its
procedures.
1.9.3 Procedure Descriptions
A procedure description generally has the following format:
ProcedureName(): The formal name of the procedure.
Summary: A brief description of the procedure.
Prototype: A “C-style” procedure header deﬁning the calling sequence.
Parameters: A brief description of each ﬁeld in the procedure prototype.
Related Deﬁnitions: The type declarations and constants that are used only by this procedure.
Status Codes Returned: A description of any codes returned by the interface. The procedure is required to implement
any status codes listed in this table. Additional error codes may be returned, but they will not be tested by standard
compliance tests, and any software that uses the procedure cannot depend on any of the extended error codes that an
implementation may provide.
1.9.4 Instruction Descriptions
An instruction description for EBC instructions generally has the following format:
InstructionName: The formal name of the instruction.
Syntax: A brief description of the instruction.
Description: A description of the functionality provided by the instruction accompanied by a table that details the
instruction encoding.
Operation: Details the operations performed on operands.
Behaviors and Restrictions: An item-by-item description of the behavior of each operand involved in the instruction
and any restrictions that apply to the operands or the instruction.
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1.9.5 Pseudo-Code Conventions
Pseudo code is presented to describe algorithms in a more concise form. None of the algorithms in this document are
intended to be compiled directly. The code is presented at a level corresponding to the surrounding text.
In describing variables, a listis an unordered collection of homogeneous objects. A queue is an ordered list of
homogeneous objects. Unless otherwise noted, the ordering is assumed to be FIFO.
Pseudo code is presented in a C-like format, using C conventions where appropriate. The coding style, particularly
the indentation style, is used for readability and does not necessarily comply with an implementation of the UEFI
Speciﬁcation .
1.9.6 Typographic Conventions
This document uses the typographic and illustrative conventions described below:
Plain text
The normal text typeface is used for the vast majority of the descriptive text in a speciﬁcation.
Plain text (blue)
Any plain text that is underlined and in blue indicates an active link to the cross-reference. Click on the
word to follow the hyperlink.
Bold
In text, a Bold typeface identiﬁes a processor register name. In other instances, a Bold typeface can be
used as a running head within a paragraph.
Italic
In text, an Italic typeface can be used as emphasis to introduce a new term or to indicate a manual or
speciﬁcation name.
BOLD Monospace

Plain text
Bold
Italic
Computer code, example code segments, and all prototype code segments use a BOLD Monospace type-
face with a dark red color. These code listings normally appear in one or more separate paragraphs, though
words or segments can also be embedded in a normal text paragraph.
Bold Monospace (Blue, underlined)
Words in a Bold Monospace typeface that is underlined and in blue indicate an active hyperlink to the
code deﬁnition for that function or type deﬁnition. Click on the word to follow the hyperlink.
Note: Due to management and ﬁle size considerations, only the ﬁrst occurrence of the reference on each page is
an active link. Subsequent references on the same page will not be actively linked to the deﬁnition and will use the
standard, nonunderlined BOLD Monospace typeface. Find the ﬁrst instance of the name (in the underlined BOLD
Monospace typeface) on the page and click on the word to jump to the function or type deﬁnition .
Italic Monospace
In code or in text, words in Italic Monospace indicate placeholder names for variable information that
must be supplied (i.e., arguments).
1.9. Conventions Used in this Document 12Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
1.9.7 Number formats
A binary number is represented in this standard by any sequence of digits consisting of only the Western-Arabic
numerals 0 and 1 immediately followed by a lower-case b (e.g., 0101b).
Underscores or spaces may be included between characters in binary number representations to increase readability or
delineate ﬁeld boundaries (e.g., 0 0101 1010b or 0_0101_1010b).
1.9.7.1 Hexadecimal
A hexadecimal number is represented in this standard by 0x preceding any sequence of digits consisting of only the
Western-Arabic numerals 0 through 9 and/or the upper-case English letters A through F (e.g., 0xFA23).
Underscores or spaces may be included between characters in hexadecimal number representations to increase read-
ability or delineate ﬁeld boundaries (e.g., 0xB FD8C FA23 or 0xB_FD8C_FA23).
1.9.7.2 Decimal
A decimal number is represented in this standard by any sequence of digits consisting of only the Arabic numerals 0
through 9 not immediately followed by a lower-case b or lower-case h (e.g., 25).
This standard uses the following conventions for representing decimal numbers:
• the decimal separator (i.e., separating the integer and fractional portions of the number) is a period;
• the thousands separator (i.e., separating groups of three digits in a portion of the number) is a comma;
• the thousands separator is used in the integer portion and is not used in the fraction portion of a number.
1.9.8 SI & Binary preﬁxes
This standard uses the preﬁxes deﬁned in the International System of Units (SI) for values that are powers of ten. See
“Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “SI Binary Preﬁxes”.
SI preﬁxes
Table 1.2: SI Preﬁxes
1031,000 kilo K
1061,000,000 mega M
1091,000,000,000 giga G
This standard uses the binary preﬁxes deﬁned in ISO/IEC 80000-13 Quantities and units – Part 13: Information science
and technology and IEEE 1514 Standard for Preﬁxes for Binary Multiples for values that are powers of two.
Binary preﬁxes
Table 1.3: Binary Preﬁxes
Factor Factor Name Symbol
2101,024 kibi Ki
2201,048,576 mebi Mi
2301,073,741,824 gibi Gi
For example, 4 KB means 4,000 bytes and 4 KiB means 4,096 bytes.
1.9. Conventions Used in this Document 13Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
1.9.9 Revision Numbers
Updates to the UEFI speciﬁcation are considered either new revisions or errata as described below:
• A new revision is produced when there is substantive new content or changes that may modify existing behavior.
New revisions are designated by a major.minor version number (e.g. xx.yy). In cases where the changes are
exceptionally minor, we may have a major.minor.minor naming convention (e.g. xx.yy.zz).
• Errata versions are produced when approved updates to the speciﬁcation do not include any signiﬁcant new
material or modify existing behavior. Errata are designated by adding an upper-case letter at the end of the
version number, such as xx.yy errata A.
1.9. Conventions Used in this Document 14CHAPTER
TWO
OVERVIEW
UEFI allows the extension of platform ﬁrmware by loading UEFI driver and UEFI application images. When UEFI
drivers and UEFI applications are loaded they have access to all UEFI-deﬁned runtime and boot services. See the
Booting Sequence ﬁgure below.
Fig. 2.1: Booting Sequence
UEFI allows the consolidation of boot menus from the OS loader and platform ﬁrmware into a single platform ﬁrmware
menu. These platform ﬁrmware menus will allow the selection of any UEFI OS loader from any partition on any boot
medium that is supported by UEFI boot services. An UEFI OS loader can support multiple options that can appear
on the user interface. It is also possible to include legacy boot options, such as booting from the A: or C: drive in the
platform ﬁrmware boot menus.
15Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UEFI supports booting from media that contain an UEFI OS loader or an UEFI-deﬁned System Partition. An UEFI-
deﬁned System Partition is required by UEFI to boot from a block device. UEFI does not require any change to the
ﬁrst sector of a partition, so it is possible to build media that will boot on both legacy architectures and UEFI platforms.
2.1 Boot Manager
UEFI contains a boot manager that allows the loading of applications written to this speciﬁcation (including OS ﬁrst
stage loader) or UEFI drivers from any ﬁle on an UEFI-deﬁned ﬁle system or through the use of an UEFI-deﬁned
image loading service. UEFI deﬁnes NVRAM variables that are used to point to the ﬁle to be loaded. These variables
also contain application-speciﬁc data that are passed directly to the UEFI application. The variables also contain a
human readable string that can be displayed in a menu to the user.
The variables deﬁned by UEFI allow the system ﬁrmware to contain a boot menu that can point to all of the operating
systems, and even multiple versions of the same operating systems. The design goal of UEFI was to have one set of
boot menus that could live in platform ﬁrmware. UEFI speciﬁes only the NVRAM variables used in selecting boot
options. UEFI leaves the implementation of the menu system as value added implementation space.
UEFI greatly extends the boot ﬂexibility of a system over the current state of the art in the PC-AT-class system. The
PC-AT-class systems today are restricted to boot from the ﬁrst ﬂoppy, hard drive, CD-ROM, USB keys, or network
card attached to the system. Booting from a common hard drive can cause many interoperability problems between
operating systems, and different versions of operating systems from the same vendor.
2.1.1 UEFI Images
UEFI Images are a class of ﬁles deﬁned by UEFI that contain executable code. The most distinguishing feature of
UEFI Images is that the ﬁrst set of bytes in the UEFI Image ﬁle contains an image header that deﬁnes the encoding of
the executable image.
UEFI uses a subset of the PE32+ image format with a modiﬁed header signature. The modiﬁcation to the signature
value in the PE32+ image is done to distinguish UEFI images from normal PE32 executables. The “+” addition to
PE32 provides the 64-bit relocation ﬁx-up extensions to standard PE32 format.
For images with the UEFI image signature, the Subsystem values in the PE image header are deﬁned below. The major
differences between image types are the memory type that the ﬁrmware will load the image into, and the action taken
when the image’s entry point exits or returns. A UEFI application image is always unloaded when control is returned
from the image’s entry point. A UEFI driver image is only unloaded if control is passed back with a UEFI error code.
// PE32+ Subsystem type forEFI images
#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10
#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12
// PE32+ Machine type forEFI images
#define EFI_IMAGE_MACHINE_IA32 0x014c
#define EFI_IMAGE_MACHINE_IA64 0x0200
#define EFI_IMAGE_MACHINE_EBC 0x0EBC
#define EFI_IMAGE_MACHINE_x64 0x8664
#define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
#define EFI_IMAGE_MACHINE_AARCH64 0xAA64
#define EFI_IMAGE_MACHINE_RISCV32 0x5032
#define EFI_IMAGE_MACHINE_RISCV64 0x5064
#define EFI_IMAGE_MACHINE_RISCV128 0x5128
#define EFI_IMAGE_MACHINE_LOONGARCH32 0x6232
#define EFI_IMAGE_MACHINE_LOONGARCH64 0x6264
2.1. Boot Manager 16Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Note: This image type is chosen to enable UEFI images to contain Thumb and Thumb2 instructions while deﬁning
the EFI interfaces themselves to be in ARM mode.
Table 2.1: UEFI Image Memory Types
Subsystem Type Code Memory Type Data Memory Type
EFI_IMAGE_SUSBS
YTEM_EFI_APPLICATIONEﬁLoaderCode EﬁLoaderData
EFI _IMAGE_SUBSYSTEM_EFI

_BOOT_SERVICE_DRIVEREﬁBootServicesCode EﬁBootServicesData
EFI_IMAGE_SUBSYSTE
M_EFI_RUNTIME_DRIVEREf iRuntimeServicesCode Ef iRuntimeServicesData
The Machine value that is found in the PE image ﬁle header is used to indicate the machine code type of the image. The
machine code types for images with the UEFI image signature are deﬁned below. A given platform must implement
the image type native to that platform and the image type for EFI Byte Code (EBC). Support for other machine code
types is optional to the platform.
A UEFI image is loaded into memory through the EFI_BOOT_SERVICES.LoadImage() Boot Service. This service
loads an image with a PE32+ format into memory. This PE32+ loader is required to load all sections of the PE32+
image into memory. Once the image is loaded into memory, and the appropriate ﬁx-ups have been performed, control
is transferred to a loaded image at the AddressOfEntryPoint reference according to the normal indirect calling conven-
tions of applications based on supported 32-bit, 64-bit, or 128-bit processors. All other linkage to and from an UEFI
image is done programmatically.
2.1.2 UEFI Applications
Applications written to this speciﬁcation are loaded by the Boot Manager or by other UEFI applications. To load
a UEFI application the ﬁrmware allocates enough memory to hold the image, copies the sections within the UEFI
application image to the allocated memory, and applies the relocation ﬁx-ups needed. Once done, the allocated
memory is set to be the proper type for code and data for the image. Control is then transferred to the UEFI
application’s entry point. When the application returns from its entry point, or when it calls the Boot Service
EFI_BOOT_SERVICES.LoadImage() , the UEFI application is unloaded from memory and control is returned to the
UEFI component that loaded the UEFI application.
When the Boot Manager loads a UEFI application, the image handle may be used to locate the “load options” for the
UEFI application. The load options are stored in nonvolatile storage and are associated with the UEFI application
being loaded and executed by the Boot Manager.
2.1.3 UEFI OS Loaders
A UEFI OS loader is a special type of UEFI application that normally takes over control of the system from ﬁrmware
conforming to this speciﬁcation. When loaded, the UEFI OS loader behaves like any other UEFI application in that
it must only use memory it has allocated from the ﬁrmware and can only use UEFI services and protocols to access
the devices that the ﬁrmware exposes. If the UEFI OS loader includes any boot service style driver functions, it must
use the proper UEFI interfaces to obtain access to the bus speciﬁc-resources. That is, I/O and memory-mapped device
registers must be accessed through the proper bus speciﬁc I/O calls like those that a UEFI driver would perform.
If the UEFI OS loader experiences a problem and cannot load its operating system correctly, it can release all allocated
resources and return control back to the ﬁrmware via the Boot Service Exit() call. The Exit() call allows both an error
code and ExitData to be returned. The ExitData contains both a string and OS loader-speciﬁc data to be returned.
If the UEFI OS loader successfully loads its operating system, it can take control of the system by using the Boot
2.1. Boot Manager 17Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Service EFI_BOOT_SERVICES.ExitBootServices() . After successfully calling ExitBootServices() , all boot services
in the system are terminated, including memory management, and the UEFI OS loader is responsible for the continued
operation of the system.
2.1.4 UEFI Drivers
UEFI drivers are loaded by the Boot Manager, ﬁrmware conforming to this speciﬁcation, or by other UEFI ap-
plications. To load a UEFI driver the ﬁrmware allocates enough memory to hold the image, copies the sections
within the UEFI driver image to the allocated memory and applies the relocation ﬁx-ups needed. Once done, the
allocated memory is set to be the proper type for code and data for the image. Control is then transferred to the
UEFI driver’s entry point. When the UEFI driver returns from its entry point, or when it calls the Boot Service
EFI_BOOT_SERVICES.ExitBootServices() , the UEFI driver is optionally unloaded from memory and control is re-
turned to the component that loaded the UEFI driver. A UEFI driver is not unloaded from memory if it returns a status
code of EFI_SUCCESS . If the UEFI driver’s return code is an error status code, then the driver is unloaded from
memory.
There are two types of UEFI drivers: boot service drivers and runtime drivers. The only difference between these two
driver types is that UEFI runtime drivers are available after a UEFI OS loader has taken control of the platform with
the Boot Service EFI_BOOT_SERVICES.ExitBootServices() .
UEFI boot service drivers are terminated when ExitBootServices() is called, and all the memory resources consumed
by the UEFI boot service drivers are released for use in the operating system environment.
A runtime driver of type EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER gets ﬁxed up with virtual mappngs
when the OS calls SetVirtualAddressMap() .
2.2 Firmware Core
This section provides an overview of the services deﬁned by UEFI. These include boot services and runtime services.
2.2.1 UEFI Services
The purpose of the UEFI interfaces is to deﬁne a common boot environment abstraction for use by loaded UEFI
images, which include UEFI drivers, UEFI applications, and UEFI OS loaders. The calls are deﬁned with a full 64-bit
interface, so that there is headroom for future growth. The goal of this set of abstracted platform calls is to allow
the platform and OS to evolve and innovate independently of one another. Also, a standard set of primitive runtime
services may be used by operating systems.
Platform interfaces deﬁned in this section allow the use of standard Plug and Play Option ROMs as the underlying
implementation methodology for the boot services. The interfaces have been designed in such as way as to map back
into legacy interfaces. These interfaces have in no way been burdened with any restrictions inherent to legacy Option
ROMs.
The UEFI platform interfaces are intended to provide an abstraction between the platform and the OS that is to boot
on the platform. The UEFI speciﬁcation also provides abstraction between diagnostics or utility programs and the
platform; however, it does not attempt to implement a full diagnostic OS environment. It is envisioned that a small
diagnostic OS-like environment can be easily built on top of an UEFI system. Such a diagnostic environment is not
described by this speciﬁcation. Interfaces added by this speciﬁcation are divided into the following categories and are
detailed later in this document:
• Runtime services
• Boot services interfaces, with the following subcategories:
– Global boot service interfaces
2.2. Firmware Core 18Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
– Device handle-based boot service interfaces
– Device protocols
– Protocol services
2.2.2 Runtime Services
This section describes UEFI runtime service functions. The primary purpose of the runtime services is to abstract
minor parts of the hardware implementation of the platform from the OS. Runtime service functions are available
during the boot process and also at runtime provided the OS switches into ﬂat physical addressing mode to make the
runtime call. However, if the OS loader or OS uses the Runtime Service SetVirtualAddressMap() service, the OS will
only be able to call runtime services in a virtual addressing mode. All runtime interfaces are non-blocking interfaces
and can be called with interrupts disabled if desired.To ensure maximum compatibility with existing platforms it is
recommended that all UEFI modules that comprise the Runtime Services be represented in the MemoryMap as a single
EFI_MEMORY_DESCRIPTOR of Type EﬁRuntimeServicesCode.
In all cases memory used by the runtime services must be reserved and not used by the OS. runtime services memory
is always available to an UEFI function and will never be directly manipulated by the OS or its components. UEFI
is responsible for deﬁning the hardware resources used by runtime services, so the OS can synchronize with those
resources when runtime service calls are made, or guarantee that the OS never uses those resources. See the table
below for lists of the Runtime Services functions.
Table 2.2: UEFI Runtime Services
Name Description
GetTime()Returns the current time, time context, and time keeping
capabilities.
SetTime()Sets the current time and time context.
GetWakeupTime()Returns the current wakeup alarm settings.
SetWakeupTime()Sets the current wakeup alarm settings.
GetVariable()Returns the value of a named variable.
GetNextVariableName()Enumerates variable names.
SetVariable()Sets, and if needed creates, a variable.
SetVirtualAddressMap()Switches all runtime functions from physical to virtual
addressing.

ConvertPointer()Used to convert a pointer from physical to virtual ad-
dressing.
2.2. Firmware Core 19Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 2.2 – continued from previous page
Get Next High Monotonic CountSubsumes the platform’s monotonic counter functional-
ity.
ResetSystem()Resets all processors and devices and reboots the sys-
tem.
Update CapsulePasses capsules to the ﬁrmware with both virtual and
physical mapping.
QueryCapsuleCapabilities() Returns if the capsule can be supported via UpdateCap-
sule() .
QueryVariableInfo()Returns information about the EFI variable store.
2.3 Calling Conventions
Unless otherwise stated, all functions deﬁned in the UEFI speciﬁcation are called through pointers in common, archi-
tecturally deﬁned, calling onventions found in C compilers. Pointers to the various global UEFI functions are found in
the EFI_RUNTIME_SERVICES and EFI_BOOT_SERVICES tables that are located via the system table. Pointers to
other functions deﬁned in this speciﬁcation are located dynamically through device handles. In all cases, all pointers
to UEFI functions are cast with the word EFIAPI . This allows the compiler for each architecture to supply the proper
compiler keywords to achieve the needed calling conventions. When passing pointer arguments to Boot Services,
Runtime Services, and Protocol Interfaces, the caller has the following responsibilities:
• It is the caller’s responsibility to pass pointer parameters that reference physical memory locations. If a pointer
is passed that does not point to a physical memory location (i.e., a memory mapped I/O region), the results are
unpredictable and the system may halt.
• It is the caller’s responsibility to pass pointer parameters with correct alignment. If an unaligned pointer is
passed to a function, the results are unpredictable and the system may halt.
• It is the caller’s responsibility to not pass in a NULL parameter to a function unless it is explicitly allowed. If a
NULL pointer is passed to a function, the results are unpredictable and the system may hang.
• Unless otherwise stated, a caller should not make any assumptions regarding the state of pointer parameters if
the function returns with an error.
• A caller may not pass structures that are larger than native size by value and these structures must be passed by
reference (via a pointer) by the caller. Passing a structure larger than native width (4 bytes on supported 32-bit
processors; 8 bytes on supported 64-bit processor instructions) on the stack will produce undeﬁned results.
Calling conventions for supported 32-bit and supported 64-bit applications are described in more detail below. Any
function or protocol may return any valid return code.
All public interfaces of a UEFI module must follow the UEFI calling convention. Public interfaces include the image
entry point, UEFI event handlers, and protocol member functions. The type EFIAPI is used to indicate conformance
to the calling conventions deﬁned in this section. Non public interfaces, such as private functions and static library
calls, are not required to follow the UEFI calling conventions and may be optimized by the compiler.
2.3. Calling Conventions 20Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.1 Data Types
See the table below which lists the common data types that are used in the interface deﬁnitions, and the following
table, Modiﬁers for Common UEFI Data Types, lists their modiﬁers. Unless otherwise speciﬁed all data types are
naturally aligned. Structures are aligned on boundaries equal to the largest internal datum of the structure and internal
data are implicitly padded to achieve natural alignment.
The values of the pointers passed into or returned by the UEFI interfaces must provide natural alignment for the
underlying types.
Common UEFI Data Types
Table 2.3: Common UEFI Data Types
Mnemonic Description
BOOLEAN Logical Boolean. 1-byte value containing a 0 for FALSE or a 1 for TRUE . Other
values are undeﬁned.
INTN Signed value of native width. (4 bytes on supported 32-bit processor instructions,
8 bytes on supported 64-bit processor instructions, 16 bytes on supported 128-bit
processor instructions)
UINTN Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
INT8 1-byte signed value.
UINT8 1-byte unsigned value.
INT16 2-byte signed value.
UINT16 2-byte unsigned value.
INT32 4-byte signed value.
UINT32 4-byte unsigned value.
INT64 8-byte signed value.
UINT64 8-byte unsigned value.
INT128 16-byte signed value.
UINT128 16-byte unsigned value.
CHAR8 1-byte character. Unless otherwise speciﬁed, all 1-byte or ASCII characters and
strings are stored in 8-bit ASCII encoding format, using the ISO-Latin-1 character
set.
CHAR16 2-byte Character. Unless otherwise speciﬁed all characters and strings are stored in
the UCS-2 encoding format as deﬁned by Unicode 2.1 and ISO/IEC 10646 standards.
VOID Undeclared type.
EFI_GUID 128-bit buffer containing a unique identiﬁer value. Unless otherwise speciﬁed,
aligned on a 64-bit boundary.
EFI_STATUS Status code. Type UINTN.
EFI_HANDLE A collection of related interfaces. Type VOID *.
EFI_EVENT Handle to an event structure. Type VOID *.
EFI_LBA Logical block address. Type UINT64.
EFI_TPL Task priority level. Type UINTN.
EFI_MAC_ADDRESS 32-byte buffer containing a network Media Access Control address.
EFI_IPv4_ADDRESS 4-byte buffer. An IPv4 internet protocol address.
EFI_IPv6_ADDRESS 16-byte buffer. An IPv6 internet protocol address.
EFI_IP_ADDRESS 16-byte buffer aligned on a 4-byte boundary. An IPv4 or IPv6 internet protocol ad-
dress.
2.3. Calling Conventions 21Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 2.3 – continued from previous page
<Enumerated Type> Element of a standard ANSI C enum type declaration. Type INT32.or UINT32. ANSI
C does not deﬁne the size of sign of an enum so they should never be used in struc-
tures. ANSI C integer promotion rules make INT32 or UINT32 interchangeable when
passed as an argument to a function.
sizeof (VOID *) 4 bytes on supported 32-bit processor instructions. 8 bytes on supported 64-bit pro-
cessor instructions. 16 bytes on supported 128-bit processor.
Bitﬁelds Bitﬁelds are ordered such that bit 0 is the least signiﬁcant bit.
Table 2.4: Modiﬁers for Common UEFI Data Types
IN Datum is passed to the function.
OUT Datum is returned from the function.
OPTIONAL Passing the datum to the function is optional, and a NULL may be passed if the value
is not supplied.
CONST Datum is read-only.
EFIAPI Deﬁnes the calling convention for UEFI interfaces.
2.3.2 IA-32 Platforms
All functions are called with the C language calling convention. The general-purpose registers that are volatile across
function calls are eax, ecx, and edx. All other general-purpose registers are nonvolatile and are preserved by the target
function. In addition, unless otherwise speciﬁed by the function deﬁnition, all other registers are preserved.
Firmware boot ‘services and runtime services run in the following processor execution mode prior to the OS calling
ExitBootServices():
• Uniprocessor, as described in chapter 8.4 of:
— Intel 64 and IA-32 Architectures Software Developer’s Manual
— V olume 3, System Programming Guide, Part 1
— Order Number: 253668-033US, December 2009
— See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “Intel Processor Manuals.””
• Protected mode
• Paging mode may be enabled. If paging mode is enabled, PAE (Physical Address Extensions) mode is recom-
mended. If paging mode is enabled, any memory space deﬁned by the UEFI memory map is identity mapped
(virtual address equals physical address). The mappings to other regions are undeﬁned and may vary from
implementation to implementation.
• Selectors are set to be ﬂat and are otherwise not used
• Interrupts are enabled-though no interrupt services are supported other than the UEFI boot services timer func-
tions (All loaded device drivers are serviced synchronously by “polling.”)
• Direction ﬂag in EFLAGs is clear
• Other general purpose ﬂag registers are undeﬁned
• 128 KiB, or more, of available stack space
• The stack must be 16-byte aligned. Stack may be marked as non-executable in identity mapped page tables.
• Floating-point control word must be initialized to 0x027F (all exceptions masked, double-precision, round-to-
nearest)
2.3. Calling Conventions 22Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Multimedia-extensions control word (if supported) must be initialized to 0x1F80 (all exceptions masked, round-
to-nearest, ﬂush to zero for masked underﬂow).
• CR0.EM must be zero
• CR0.TS must be zero
An application written to this speciﬁcation may alter the processor execution mode, but the UEFI image must ensure

nearest)
ﬁrmware boot services and runtime services are executed with the prescribed execution environment.
After an Operating System calls ExitBootServices() , ﬁrmware boot services are no longer available and it is illegal
to call any boot service. After ExitBootServices, ﬁrmware runtime services are still available and may be called with
paging enabled and virtual address pointers if SetVirtualAddressMap() has been called describing all virtual address
ranges used by the ﬁrmware runtime service. For an operating system to use any UEFI runtime services, it must:
• Preserve all memory in the memory map marked as runtime code and runtime data
• Call the runtime service functions, with the following conditions:
— In protected mode
— Paging may or may not be enabled, however if paging is enabled and SetVirtualAddressMap() has not been
called, any memory space deﬁned by the UEFI memory map is identity mapped (virtual address equals physical
address), although the attributes of certain regions may not have all read, write, and execute attributes or be
unmarked for purposes of platform protection. The mappings to other regions are undeﬁned and may vary from
implementation to implementation. See description of SetVirtualAddressMap() for details of memory map after
this function has been called.
— Direction ﬂag in EFLAGs clear
— 4 KiB, or more, of available stack space
— The stack must be 16-byte aligned
— Floating-point control word must be initialized to 0x027F (all exceptions masked, double-precision, round-
to-nearest)
— Multimedia-extensions control word (if supported) must be initialized to 0x1F80 (all exceptions masked,
round-to-nearest, ﬂush to zero for masked underﬂow)
— CR0.EM must be zero
— CR0.TS must be zero
— Interrupts disabled or enabled at the discretion of the caller
• ACPI Tables loaded at boot time can be contained in memory of type EﬁACPIReclaimMemory (recommended)
or EﬁACPIMemoryNVS . ACPI FACS must be contained in memory of type EﬁACPIMemoryNVS.
• The system ﬁrmware must not request a virtual mapping for any memory descriptor of type EﬁACPIReclaim-
Memory or EﬁACPIMemoryNVS .
• EFI memory descriptors of type EﬁACPIReclaimMemory and EﬁACPIMemoryNVS must be aligned on a 4
KiB boundary and must be a multiple of 4 KiB in size.
• Any UEFI memory descriptor that requests a virtual mapping via the EFI_MEMORY_DESCRIPTOR having
the EFI_MEMORY_RUNTIME bit set must be aligned on a 4 KiB boundary and must be a multiple of 4 KiB
in size.
• An ACPI Memory Op-region must inherit cacheability attributes from the UEFI memory map. If the system
memory map does not contain cacheability attributes, the ACPI Memory Op-region must inherit its cacheability
attributes from the ACPI name space. If no cacheability attributes exist in the system memory map or the ACPI
name space, then the region must be assumed to be non-cacheable.
2.3. Calling Conventions 23Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• ACPI tables loaded at runtime must be contained in memory of type EﬁACPIMemoryNVS . The cacheability
attributes for ACPI tables loaded at runtime should be deﬁned in the UEFI memory map. If no information
about the table location exists in the UEFI memory map, cacheability attributes may be obtained from ACPI
memory descriptors. If no information about the table location exists in the UEFI memory map or ACPI memory
descriptors, the table is assumed to be non-cached.
• In general, UEFI Conﬁguration Tables loaded at boot time (e.g., SMBIOS table) can be contained in mem-
ory of type EﬁRuntimeServicesData (recommended), EﬁBootServicesData , EﬁACPIReclaimMemory or Eﬁ-
ACPIMemoryNVS . Tables loaded at runtime must be contained in memory of type EﬁRuntimeServicesData
(recommended) or EﬁACPIMemoryNVS .
Note :Previous EFI speciﬁcations allowed ACPI tables loaded at runtime to be in the EﬁReservedMemoryType and
there was no guidance provided for other EFI Conﬁguration Tables. EﬁReservedMemoryType is not intended to be
used for the storage of any EFI Conﬁguration Tables. Also, only OSes conforming to the UEFI Speciﬁcation are
guaranteed to handle SMBIOS table in memory of type EﬁBootServicesData.
2.3.2.1 Handoff State
When a 32-bit UEFI OS is loaded, the system ﬁrmware hands off control to the OS in ﬂat 32-bit mode. All descriptors
are set to their 4GiB limits so that all of memory is accessible from all segments.
The Figure below ( Stack After AddressOfEntryPoint Called, IA-32 )shows the stack after AddressOfEntryPoint in the
image’s PE32+ header has been called on supported 32-bit systems. All UEFI image entry points take two parameters.
These are the image handle of the UEFI image, and a pointer to the EFI System Table.
Fig. 2.2: Stack After AddressOfEntryPoint Called, IA-32
2.3.2.2 Calling Convention
function calls are eax , ecx , and edx . All other general-purpose registers are nonvolatile and are preserved by the
target function.
In addition, unless otherwise speciﬁed by the function deﬁnition, all other CPU registers (including MMX and XMM)
are preserved.
The ﬂoating point status register is not preserved by the target function. The ﬂoating point control register and MMX
control register are saved by the target function.
If the return value is a ﬂoat or a double, the value is returned in ST(0).
2.3. Calling Conventions 24Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.3 Intel®Itanium®-Based Platforms
UEFI executes as an extension to the SAL execution environment with the same rules as laid out by the SAL speciﬁ-
cation.
During boot services time the processor is in the following execution mode:
• Uniprocessor, as detailed in chapter 13.1.2 of:
— Intel Itanium Architecture Software Developer’s Manual
— V olume 2: System Architecture
— Revision 2.2
— January 2006
— See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “Intel Itanium Documenta-
tion”.
— Document Number: 245318-005
• Physical mode
• 16 KiB, or more, of available backing store space
— FPSR.traps: Set to all 1’s (all exceptions disabled)
— FPSR.sf0:
• .pc: Precision Control - 11b (extended precision)
• .rc: Rounding Control - 0 (round to nearest)
• .wre: Widest Range Exponent - 0 (IEEE mode)
• .ftz: Flush-To-Zero mode - 0 (off)
— FPSR.sf1:
• .td: Traps Disable = 1 (traps disabled)
• wreWidest Range Exponent - 1 (full register exponent range)
• ftz Flush-To-Zero mode - 0 (off)
— FPSR.sf2,3:
• .td Traps Disable = 1 (traps disabled)
• pc: Precision Control - 11b (extended precision)
After an Operating System calls ExitBootServices(), ﬁrmware boot services are no longer available and it is illegal
to call any boot service. After ExitBootServices, ﬁrmware runtime services are still available When calling runtime
2.3. Calling Conventions 25Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
services, paging may or may not be enabled, however if paging is enabled and SetVirtualAddressMap() has not been
called, any memory space deﬁned by the UEFI memory map is identity mapped (virtual address equals physical ad-
dress). The mappings to other regions are undeﬁned and may vary from implementation to implementation. See
description of SetVirtualAddressMap() for details of memory map after this function has been called. After Exit-
BootServices(), runtime service functions may be called with interrupts disabled or enabled at the discretion of the
caller.
or EﬁACPIMemoryNVS. CPI FACS must be contained in memory of type EﬁACPIMemoryNVS.
Memory or EﬁACPIMemoryNVS.
• EFI memory descriptors of type EﬁACPIReclaimMemory and EﬁACPIMemoryNVS. must be aligned on an 8
KiB boundary and must be a multiple of 8 KiB in size.
the EFI_MEMORY_RUNTIME bit set must be aligned on an 8 KiB boundary and must be a multiple of 8 KiB
in size.
memory map does not contain cacheability attributes the ACPI Memory Op-region must inherit its cacheability

in size.
• In general, Conﬁguration Tables loaded at boot time (e.g., SMBIOS table) can be contained in memory of type
EﬁRuntimeServicesData (recommended), EﬁBootServicesData, EﬁACPIReclaimMemory or EﬁACPIMemo-
ryNVS. Tables loaded at runtime must be contained in memory of type EﬁRuntimeServicesData (recommended)
or EﬁACPIMemoryNVS.
there was no guidance provided for other EFI Conﬁguration Tables . EﬁReservedMemoryType is not intended to be
used by ﬁrmware. Also, only OSes conforming to the UEFI Speciﬁcation are guaranteed to handle SMBIOS table in
memory of type EﬁBootServicesData.
Refer to the IA-64 System Abstraction Layer Speciﬁcation ( References ) for details.
UEFI procedures are invoked using the P64 C calling conventions deﬁned for Intel ® Itanium ® -based applications.
Refer to the document 64 Bit Runtime Architecture and Software Conventions for IA-64 ( References ) for more
information.
2.3.3.1 Handoff State
UEFI uses the standard P64 C calling conventions that are deﬁned for Itanium-based operating systems. The Figure
below shows the stack after ImageEntryPoint has been called on Itanium-based systems. The arguments are also stored
in registers: out0 contains EFI_HANDLE and out1 contains the address of the EFI_SYSTEM_TABLE . The gp for
the UEFI Image will have been loaded from the plabel pointed to by the AddressOfEntryPoint in the image’s PE32+
header. All UEFI image entry points take two parameters. These are the image handle of the image, and a pointer to
the System Table.
The SAL speciﬁcation ( References ) deﬁnes the state of the system registers at boot handoff. The SAL speciﬁcation
also deﬁnes which system registers can only be used after UEFI boot services have been properly terminated.
2.3. Calling Conventions 26Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 2.3: Stack after AddressOfEntryPoint Called, Itanium-based Systems
2.3.3.2 Calling Convention
UEFI executes as an extension to the SAL execution environment with the same rules as laid out by the SAL speciﬁca-
tion. UEFI procedures are invoked using the P64 C calling conventions deﬁned for Intel®Itanium®-based applications.
Refer to the document 64 Bit Runtime Architecture and Software Conventions for IA-64 (see the index appendix for
more information).
For ﬂoating point, functions may only use the lower 32 ﬂoating point registers Return values appear in f8-f15 registers.
Single, double, and extended values are all returned using the appropriate format. Registers f6-f7 are local registers
and are not preserved for the caller. All other ﬂoating point registers are preserved. Note that, when compiling UEFI
programs, a special switch will likely need to be speciﬁed to guarantee that the compiler does not use f32-f127, which
are not normally preserved in the regular calling convention for Itanium. A procedure using one of the preserved
ﬂoating point registers must save and restore the caller’s original contents without generating a NaT consumption
fault.
Floating point arguments are passed in f8-f15 registers when possible. Parameters beyond the registers appear in
memory, as explained in Section 8.5 of the Itanium Software Conventions and Runtime Architecture Guide. Within
the called function, these are local registers and are not preserved for the caller. Registers f6-f7 are local registers
fault.
The ﬂoating point status register must be preserved across calls to a target function. Flags ﬁelds in SF1,2,3 are
not preserved for the caller. Flags ﬁelds in SF0 upon return will reﬂect the value passed in, and with bits set to 1
corresponding to any IEEE exceptions detected on non-speculative ﬂoating-point operations executed as part of the
callee.
Floating-point operations executed by the callee may require software emulation. The caller must be prepared to
handle FP Software Assist (FPSWA) interruptions. Callees should not raise IEEE traps by changing FPSR.traps bits
to 0 and then executing ﬂoating-point operations that raise such traps.
2.3.4 x64 Platforms
All functions are called with the C language calling convention. Detailed Calling Conventions for more detail.
— Intel 64 and IA-32 Architectures Software Developer’s Manual, V olume 3, System Programming Guide, Part
1, Order Number: 253668-033US, December 2009
— See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “Intel Processor Manuals”.
2.3. Calling Conventions 27Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Long mode, in 64-bit mode
• Paging mode is enabled and any memory space deﬁned by the UEFI memory map is identity mapped (virtual
address equals physical address), although the attributes of certain regions may not have all read, write, and
execute attributes or be unmarked for purposes of platform protection. The mappings to other regions, such as
those for unaccepted memory, are undeﬁned and may vary from implementation to implementation.
• Selectors are set to be ﬂat and are otherwise not used.
• Floating-point control word must be initialized to 0x037F (all exceptions masked, double-extended-precision,
round-to-nearest)
For an operating system to use any UEFI runtime services, it must:
• In long mode, in 64-bit mode
• Paging enabled
• All selectors set to be ﬂat with virtual = physical address. If the UEFI OS loader or OS used SetVirtualAd-
dressMap() to relocate the runtime services in a virtual address space, then this condition does not have to be
met. See description SetVirtualAddressMap() for details of memory map after this function has been called.
• Direction ﬂag in EFLAGs clear
• 4 KiB, or more, of available stack space
• The stack must be 16-byte aligned
to-nearest, ﬂush to zero for masked underﬂow)
• Interrupts may be disabled or enabled at the discretion of the caller.
or EﬁACPIMemoryNVS . ACPI FACS must be contained in memory of type EﬁACPIMemoryNVS .
2.3. Calling Conventions 28Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
in size.

in size.
(recommended) or EﬁACPIMemoryNVS.
2.3.4.1 Handoff State
Rcx - EFI_HANDLE
Rdx - EFI_SYSTEM_TABLE*
RSP - <return address>
2.3.4.2 Detailed Calling Conventions
The caller passes the ﬁrst four integer arguments in registers. The integer values are passed from left to right in Rcx,
Rdx, R8, and R9 registers. The caller passes arguments ﬁve and above onto the stack. All arguments must be right-
justiﬁed in the register in which they are passed. This ensures the callee can process only the bits in the register that
are required.
The caller passes arrays and strings via a pointer to memory allocated by the caller. The caller passes structures and
unions of size 8, 16, 32, or 64 bits as if they were integers of the same size. The caller is not allowed to pass structures
and unions of other than these sizes and must pass these unions and structures via a pointer.
The callee must dump the register parameters into their shadow space if required. The most common requirement is
to take the address of an argument.
If the parameters are passed through varargs then essentially the typical parameter passing applies, including spilling
the ﬁfth and subsequent arguments onto the stack. The callee must dump the arguments that have their address taken.
Return values that ﬁx into 64-bits are returned in the Rax register. If the return value does not ﬁt within 64-bits, then
the caller must allocate and pass a pointer for the return value as the ﬁrst argument, Rcx. Subsequent arguments are
then shifted one argument to the right, so for example argument one would be passed in Rdx. User-deﬁned types to be
returned must be 1,2,4,8,16,32, or 64 bits in length.
2.3. Calling Conventions 29Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The registers Rax, Rcx Rdx R8, R9, R10, R11, and XMM0-XMM5 are volatile and are, therefore, destroyed on
function calls.
The registers RBX, RBP, RDI, RSI, R12, R13, R14, R15, and XMM6-XMM15 are considered nonvolatile and must
be saved and restored by a function that uses them.
Function pointers are pointers to the label of the respective function and don’t require special treatment.
A caller must always call with the stack 16-byte aligned.
For MMX, XMM and ﬂoating-point values, return values that can ﬁt into 64-bits are returned through RAX (including
MMX types). However, XMM 128-bit types, ﬂoats, and doubles are returned in XMM0. The ﬂoating point status
register is not saved by the target function. Floating-point and double-precision arguments are passed in XMM0 -
XMM3 (up to 4) with the integer slot (RCX, RDX, R8, and R9) that would normally be used for that cardinal slot
being ignored (see example) and vice versa. XMM types are never passed by immediate value but rather a pointer
will be passed to memory allocated by the caller. MMX types will be passed as if they were integers of the same size.
Callees must not unmask exceptions without providing correct exception handlers.
2.3.4.3 Enabling Paging or Alternate Translations in an Application
Boot Services deﬁne an execution environment where paging is not enabled (supported 32-bit) or where translations
are enabled but mapped virtual equal physical (x64) and this section will describe how to write an application with
alternate translations or with paging enabled. Some Operating Systems require the OS Loader to be able to enable OS
required translations at Boot Services time.
If a UEFI application uses its own page tables, GDT or IDT, the application must ensure that the ﬁrmware executes
with each supplanted data structure. There are two ways that ﬁrmware conforming to this speciﬁcation can execute
when the application has paging enabled.
• Explicit ﬁrmware call
• Firmware preemption of application via timer event
An application with translations enabled can restore ﬁrmware required mapping before each UEFI call. However
the possibility of preemption may require the translation enabled application to disable interrupts while alternate
translations are enabled. It’s legal for the translation enabled application to enable interrupts if the application catches
the interrupt and restores the EFI ﬁrmware environment prior to calling the UEFI interrupt ISR. After the UEFI ISR
context is executed it will return to the translation enabled application context and restore any mappings required by
the application.
2.3.5 AArch32 Platforms
All functions are called with the C language calling convention speciﬁed in Detailed Calling Convention . In addition,
the invoking OSs can assume that unaligned access support is enabled if it is present in the processor.
• Unaligned access should be enabled if supported; Alignment faults are enabled otherwise.
• Uniprocessor.
• A privileged mode.
• The MMU is enabled (CP15 c1 System Control Register (SCTLR) SCTLR.M=1) and any RAM deﬁned by the
UEFI memory map is identity mapped (virtual address equals physical address). The mappings to other regions
are undeﬁned and may vary from implementation to implementation
2.3. Calling Conventions 30Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• The core will be conﬁgured as follows (common across all processor architecture revisions):
–MMU enabled
–Instruction and Data caches enabled
–Access ﬂag disabled
–Translation remap disabled
–Little endian mode
–Domain access control mechanism (if supported) will be conﬁgured to check access permission bits in the
page descriptor
–Fast Context Switch Extension (FCSE) must be disabled
This will be achieved by:
–Conﬁguring the CP15 c1 System Control Register (SCTLR) as follows: I=1, C=1, B=0, TRE=0, AFE=0,
M=1
–Conﬁguring the CP15 c3 Domain Access Control Register (DACR) to 0x33333333.
–Conﬁguring the CP15 c1 System Control Register (SCTLR), A=1 on ARMv4 and ARMv5, A=0, U=1 on
ARMv6 and ARMv7.
The state of other system control register bits is not dictated by this speciﬁcation.
• Implementations of boot services will enable architecturally manageable caches and TLBs i.e., those that can
be managed directly using CP15 operations using mechanisms and procedures deﬁned in the ARM Architecture
Reference Manual. They should not enable caches requiring platform information to manage or invoke non-
architectural cache/TLB lockdown mechanisms
• MMU conﬁguration — Implementations must use only 4k pages and a single translation base register. On de-
vices supporting multiple translation base registers, TTBR0 must be used solely. The binding does not mandate
whether page tables are cached or un-cached.
–On processors implementing the ARMv4 through ARMv6K architecture deﬁnitions, the core is addition-
ally conﬁgured to disable extended page tables support, if present.
This will be achieved by conﬁguring the CP15 c1 System Control Register (SCTLR) as follows: XP=0
–On processors implementing the ARMv7 and later architecture deﬁnitions, the core will be conﬁgured to
enable the extended page table format and disable the TEX remap mechanism.
This will be achieved by conﬁguring the CP15 c1 System Control Register (SCTLR) as follows: XP=1,
TRE=0
• 128 KiB or more of available stack space
For an operating system to use any runtime services, it must:

TRE=0
–In a privileged mode.
–The system address regions described by all the entries in the EFI memory map that have the
EFI_MEMORY_RUNTIME bit set must be identity mapped as they were for the EFI boot environment.
If the OS Loader or OS used SetVirtualAddressMap() to relocate the runtime services in a virtual address
2.3. Calling Conventions 31Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
space, then this condition does not have to be met. See description of SetVirtualAddressMap() for details
of memory map after this function has been called.
–The processor must be in a mode in which it has access to the system address regions speciﬁed in the EFI
memory map with the EFI_MEMORY_RUNTIME bit set.
–4 KiB, or more, of available stack space
–Interrupts may be disabled or enabled at the discretion of the caller
An application written to this speciﬁcation may alter the processor execution mode, but the invoking OS must ensure
If ACPI is supported:
or EﬁACPIMemoryNVS. ACPI FACS must be contained in memory of type EﬁACPIMemoryNVS
in size.
• ACPI tables loaded at runtime must be contained in memory of type EﬁACPIMemoryNVS. The cacheability
ACPIMemoryNVS. Tables loaded at runtime must be contained in memory of type EﬁRuntimeServicesData
memory of type EﬁBootServicesData .
2.3.5.1 Handoff State
R0 - EFI_HANDLE
R1 - EFI_SYSTEM_TABLE*
R14 - Return Address
2.3. Calling Conventions 32Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.5.2 Enabling Paging or Alternate Translations in an Application
Boot Services deﬁne a speciﬁc execution environment. This section will describe how to write an application that
creates an alternative execution environment. Some Operating Systems require the OS Loader to be able to enable OS
required translations at Boot Services time, and make other changes to the UEFI deﬁned execution environment.
If a UEFI application uses its own page tables, or other processor state, the application must ensure that the ﬁrmware
executes with each supplanted functionality. There are two ways that ﬁrmware conforming to this speciﬁcation can
execute in this alternate execution environment:
An application with an alternate execution environment can restore the ﬁrmware environment before each UEFI call.
However the possibility of preemption may require the alternate execution-enabled application to disable interrupts
while the alternate execution environment is active. It’s legal for the alternate execution environment enabled appli-
cation to enable interrupts if the application catches the interrupt and restores the EFI ﬁrmware environment prior
to calling the UEFI interrupt ISR. After the UEFI ISR context is executed it will return to the alternate execution
environment enabled application context.
An alternate execution environment created by a UEFI application must not change the semantics or behavior of the
MMU conﬁguration created by the UEFI ﬁrmware prior to invoking ExitBootServices(), including the bit layout of
the page table entries.
After an OS loader calls ExitBootServices() it should immediately conﬁgure the exception vector to point to appropri-
ate code.
2.3.5.3 Detailed Calling Convention
The base calling convention for the ARM binding is deﬁned here:
Procedure Call Standard for the ARM Architecture V2.06 (or later)
See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Arm Architecture Base Calling
Convention”.
This binding further constrains the calling convention in these ways:
• Calls to UEFI deﬁned interfaces must be done assuming that the target code requires the ARM instruction set
state. Images are free to use other instruction set states except when invoking UEFI interfaces.
• Floating point, SIMD, vector operations and other instruction set extensions must not be used.
• Only little endian operation is supported.
• The stack will maintain 8 byte alignment as described in the AAPCS for public interfaces.
• Use of coprocessor registers for passing call arguments must not be used
• Structures (or other types larger than 64-bits) must be passed by reference and not by value
• The EFI ARM platform binding deﬁnes register r9 as an additional callee-saved variable register.
2.3. Calling Conventions 33Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.6 AArch64 Platforms
AArch64 UEFI will only execute 64-bit ARM code, as the ARMv8 architecture does not allow for the mixing of 32-bit
and 64-bit code at the same privilege level.
All functions are called with the C language calling convention speciﬁed in Detailed calling Convention section below.
During boot services only a single processor is used for execution. All secondary processors must be either powered
off or held in a quiescent state.
The primary processor is in the following execution mode:
• Unaligned access must be enabled.
• Use the highest 64 bit non secure privilege level available; Non-secure EL2 (Hyp) or Non-secure EL1(Kernel).
• The MMU is enabled and any RAM deﬁned by the UEFI memory map is identity mapped (virtual address
equals physical address). The mappings to other regions are undeﬁned and may vary from implementation to
implementation
• The core will be conﬁgured as follows:
–Stack Alignment Enforced
–NOT Top Byte Ignored
–Valid Physical Address Space
–4K Translation Granule
1. Conﬁguring the System Control Register SCTLR_EL2 or SCTLR_EL1:
• EE=0, I=1, SA=1, C=1, A=0, M=1
2. Conﬁguring the appropriate Translation Control Register:
• TCR_EL2
–TBI=0
–PS must contain the valid Physical Address Space Size.
–TG0=00
• TCR_EL1
–TBI0=0
–IPS must contain the valid Intermediate Physical Address Space Size.
–TG0=00
Note :The state of other system control register bits is not dictated by this speciﬁcation .
• All ﬂoating point traps and exceptions will be disabled at the relevant exception levels (FPCR=0,
CPACR_EL1.FPEN=11, CPTR_EL2.TFP=0). This implies that the FP unit will be enabled by default.
• Implementations of boot services will enable architecturally manageable caches and TLBs i.e., those that can be
managed directly using implementation independent registers using mechanisms and procedures deﬁned in the
ARM Architecture Reference Manual. They should not enable caches requiring platform information to manage
or invoke non-architectural cache/TLB lockdown mechanisms.
2.3. Calling Conventions 34Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• MMU conﬁguration: Implementations must use only 4k pages and a single translation base register. On devices
supporting multiple translation base registers, TTBR0 must be used solely. The binding does not mandate

–TG0=00
• Interrupts are enabled, though no interrupt services are supported other than the UEFI boot services timer func-
tions (All loaded device drivers are serviced synchronously by “polling”). All UEFI interrupts must be routed
to the IRQ vector only.
• The architecture generic timer must be initialized and enabled. The Counter Frequency register (CNTFRQ)
must be programmed with the timer frequency. Timer access must be provided to non-secure EL1 and EL0 by
setting bits EL1PCTEN and EL1PCEN in register CNTHCTL_EL2.
• The system ﬁrmware is not expected to initialize EL2 registers that do not have an architectural reset value,
except in cases where ﬁrmware itself is running at EL2 and needs to do so.
• The ARM architecture allows mapping pages at a variety of granularities, including 4KiB and 64KiB. If a 64KiB
physical page contains any 4KiB page with any of the following types listed below, then all 4KiB pages in the
64KiB page must use identical ARM Memory Page Attributes (as described in Map EFI Cacheability Attributes
to AArch64 Memory Types ):
– EﬁRuntimeServicesCode
– EﬁRuntimeServicesData
– EﬁReserved
– EﬁACPIMemoryNVS
Mixed attribute mappings within a larger page are not allowed.
Note :This constraint allows a 64K paged based Operating System to safely map runtime services memory .
For an operating system to use any runtime services, Runtime services must:
• Support calls from either the EL1 or the EL2 exception levels.
• Once called, simultaneous or nested calls from EL1 and EL2 are not permitted.
Note :Sequential, non-overlapping, calls from EL1 and EL2 are permitted .
Runtime services are permitted to make synchronous SMC and HVC calls into higher exception levels.
Note :These rules allow Boot Services to start at EL2, and Runtime services to be assigned to an EL1 Operating
System. In this case a call to SetVirtualAddressMap()is expected to provided an EL1 appropriate set of mappings.
• Enable unaligned access support.
–From either EL1 or EL2 exception levels.
–Consistently call runtime services from the same exception level. Sharing of runtime services between
different exception levels is not permitted.
–Runtime services must only be assigned to a single operating system or hypervisor. They must not be
shared between multiple guest operating systems.
2.3. Calling Conventions 35Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
–8 KiB, or more, of available stack space.
–The stack must be 16-byte aligned (128-bit).
–Interrupts may be disabled or enabled at the discretion of the caller.
–If the core implements the Scalable Matrix Extension, the OS must ensure that the per-core Streaming
SVE mode is disabled before the core calls a runtime service.
If ACPI is supported :
• ACPI FACS must be contained in memory of type EﬁACPIMemoryNVS. The system ﬁrmware must not request
a virtual mapping for any memory descriptor of type EﬁACPIReclaimMemory or EﬁACPIMemoryNVS.
in size.
ory of type EﬁRuntimeServicesData (recommended), EﬁBootServicesdata , EﬁACPIReclaimMemory or Eﬁ-
used by ﬁrmware. UEFI 2.0 clariﬁed the situation moving forward. Also, only OSes conforming to UEFI Speciﬁcation
are guaranteed to handle SMBIOS table in memory of type EﬁBootServiceData.
2.3. Calling Conventions 36Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.6.1 Memory types
Table 2.5: Map EFI Cacheability Attributes to AArch64 Memory Types
EFI Memory Type ARM Memory
Type: MAIR at-
tribute encoding
Attr<n> [7:4] [3:0]ARM Memory Type: Meaning
EFI_MEMORY_UC (Not
cacheable)0000 0000 Device-nGnRnE (Device non-Gathering, non-Reordering,
no Early Write Acknowledgement)
EFI_MEMORY_WC
(Write combine)0100 0100 Normal Memory Outer non-cacheable Inner non-cacheable
EFI_MEMORY_WT
(Write through)1011 1011 Normal Memory Outer Write-through non-transient Inner
Write-through non-transient
EFI_MEMORY_WB
(Write back)1111 1111 Normal Memory Outer Write-back non-transient Inner
Write-back non-transient
EFI_MEMORY_UCE Not used or deﬁned
EFI_MEMORY_ISA_MASK Direct copy of the
values of MAIR
Attr<n> [7:4][3:0]As deﬁned in the ARM Architecture Reference Manual.
Table 2.6: Map UEFI Permission Attributes to ARM Paging Attributes
EFI Memory Type ARM Paging Attributes
EFI_MEMORY_XP EL2 translation regime:
XN Execute never
EL1/0 translation regime:
UXN Unprivileged execute never
PXN Privileged execute never
EFI_MEMORY_RO Read only access AP[2]=1
EFI_MEMORY_RP,
EFI_MEMORY_WPNot used or deﬁned
2.3.6.2 Handoff State
X0 - EFI_HANDLE
X1 - EFI_SYSTEM_TABLE
X30 - Return Address
2.3. Calling Conventions 37Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.6.3 Enabling Paging or Alternate Translations in an Application

ate code.
2.3.6.4 Detailed Calling Convention
The base calling convention for the AArch64 binding is deﬁned in the document Procedure Call Standard for the ARM
64-bit Architecture Version A-0.06 (or later) :
See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “ARM 64-bit Base Calling Conven-
tion”
• The AArch64 execution state must not be modiﬁed by the callee.
• All code exits, normal and exceptional, must be from the A64 instruction set.
• Floating point and SIMD instructions may be used.
• Optional vector and matrix operations and other instruction set extensions may only be used:
–After dynamically checking for their existence.
–Saving and then later restoring any additional execution state context.
–Additional feature enablement or control, such as power, must be explicitly managed.
• The stack will maintain 16 byte alignment.
• Structures (or other types larger than 64-bits) must be passed by reference and not by value.
• The EFI AArch64 platform binding deﬁnes the platform register (r18) as “do not use”. Avoiding use of r18 in
ﬁrmware makes the code compatible with both a ﬁxed role for r18 deﬁned by the OS platform ABI and the use
of r18 by the OS and its applications as a temporary register.
2.3. Calling Conventions 38Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.3.7 RISC-V Platforms
All functions are called with the C language calling convention. See Detailed Calling Convention for more detail. On
RISC-V platform, three privileged levels are currently introduced in RISC-V architecture. Beyond the User privilege,
Supervisor privilege and Machine privileges cover all aspects of RISC-V system. The privileged instructions are also
deﬁned in each privilege level.
Table 2.7: RISC-V Platforms
Level Encoding Name Abbreviation
0 0 User/Application U
1 1 Supervisor S
2 10 Reserved
3 11 Machine M
A RISC-V platform can contain one or more RISC-V cores and other components such as physical memory, ﬁxed-
function accelerators and I/O devices. The term RISC-V core refers to a component which contains an independent
instruction fetch unit. A RISC-V core may have multiple RISC-V-compatible hardware threads, or hart. RISC-V UEFI
ﬁrmware could be executed in either Machine mode or Supervisor mode during the entire POST, according to the hart
capability and the platform design. However, RISC-V UEFI ﬁrmware has to switch the boot hart to Supervisor mode
at either early or late POST if the platform is designed to boot a Supervisor mode OS or OS loader.
The machine mode has the highest privilege and this mode is the only mandatory privilege level for RISC-V platforms;
all other privilege levels are optional depending on the platform requirements. Machine mode is the initial privelege
mode entered at the power-on reset. This level is used in UEFI for low-level access to a hardware platform.
UEFI ﬁrmware implementation may provide the Supervisor Binary Interface (SBI) to allow the Supervisor mode
execution environment to invoke privileged functions or access privileged hardware.
The processor is in the following execution mode during boot service:
• Total 32 general-purpose registers x1-x31. Register x0 is hardwired to 0. Each register has its ABI (Application
Binary Interface) name. See Detailed Calling Convention for more detail.
• The width of the native base integer depends on the RISC-V privileged mode implementation. XLEN is a
general term which used to refer the width of base integer in bits.
— For the Base Integer ISA in 32-bit width, XLEN = 32
— For the Base Integer ISA in 64-bit width, XLEN = 64
— For the Base Integer ISA in 128-bit width, XLEN = 128
• The width of processor registers could be determined by placing the immediate 4 in a register then shifting the
register left by 31 bits at a time. If zero after one shift, then the machine is RV32. If zero after two shifts, then
the machine is RV64, else RV128.
• Processor reset vector is platform speciﬁed. In UEFI, it is conﬁgured to the platform implementation-deﬁned
reset vector. The reset vector address is the ﬁrst instruction which fetched by RISC-V processor when the
power-on reset.
• The mcause value after reset have implementation-speciﬁc interpretation, value 0 should be returned on imple-
mentations that do not distinguish different reset conditions. Implementations that distinguish different reset
conditions should only use 0 to indicate the most complete reset (e.g., hard reset). The causes of reset could be
power-on reset, external hard reset, brownout detected, watchdog timer elapse, sleep-mode wakeup, etc., which
machine-mode UEFI system ﬁrmware has to distinguish.
• The mstatus.xIE indicates the current processor interrupt activation in current privilege mode.
— mstatus.MIE is set to one while mstatus.SIE and mstatus.UIE are set to zero during early UEFI POST stage.
2.3. Calling Conventions 39Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• The machine mode interrupt is enabled during boot service in UEFI. Two kinds of interrupts are enabled, one is
for timer interrupt and another is software interrupt.
• mie.MSIE = 1
• mie.MTIE = 1
• The memory is in physical addressing mode. Page is disabled in RISC-V machine mode during UEFI boot
service.
• I/O access is through memory map I/O.
• Only support Machine level Control and Status Registers (CSRs) in UEFI.
• Machine ISA (misa) register contains the information regarding to the capabilities of CPU implementation. The
misa.MXL ﬁeld encodes the native base integer ISA width in machine mode. MXLEN (Machine XLEN) is
given by setting of misa.MXL.
— misa.MXL = 1, MXLEN is 32 bit
— misa.MXL = 2, MXLEN is 64 bit
— misa.MXL = 3, MXLEN is 128 bit
• RISC-V processor supports extensive customization and specialization instruction sets. RISC-V variations pro-
vide various purposes of processor implementations and the processor capability is reported in the extension
bits in misa register. UEFI drivers will need to know the capabilities of processor before executing the speciﬁed
RISC-V extension instructions. The extensions ﬁelds encodes the presence of the standard extensions, with
a single bit per letter of the alphabet. (Bit 0 encodes presence of extension “A”, Bit 1 encodes presence of
extension “B” and so on. Currently the single letter extension mnemonics are as below,
— A - Atomic extension
— B - Tentatively reserved for Bit operations extension
— C - Compressed extension
— D - Double-Precision Floating-Point extension
— E - Reduced Register Set Indicator RV32E (16 registers)
— F - Single-Precision Floating-Point extension
— G - Additional standard extensions present
— H - Hypervisor extension
— I - RV32I/64I/128I base ISA
— J - Tentatively reserved for Dynamically Translated Languages extension
— K - Reserved
— L - Tentatively reserved for Decimal Floating-Point extension
— M - Integer Multiplication and Division extension
— N - User-level interrupts supported
— O - Reserved
— P - Tentatively reserved for Packed-SIMD extension
— Q - Quad-Precision Floating-Point extension
— S - Supervisor mode implemented
— T - Tentatively reserved for Transactional Memory extension
2.3. Calling Conventions 40Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
— U - User mode implemented
— V - Tentatively reserved for Vector extension
— W - Reserved
— X - Non-standard extension present
— Y - Reserved
— Z - Reserved
— Zifenci - Instruction-Fetch Fence
— Zicsr - Control and Status Register Access
• Machine Vendor ID Register
— The mvendorid is a 32-bit read-only register encoding the manufacture of the part. Value of 0 indicates this
ﬁeld is not implemented or this is a non-commercial implementation.
• Machine Architecture ID Register
— The marchid is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. The
combination of mvendorid and marchid should uniquely identify the type of hart microarchitecture that is im-
plemented.
• Machine Implementation ID Register
— This provides a unique encoding of the version of processor implementation.
After an Operating System calls ExitBootServices (), ﬁrmware boot services are no longer available and it is illegal

paging enabled and virtual address pointers if SetVirtualAddressMap () has been called describing all virtual address
ranges used by the ﬁrmware runtime service.
orEﬁACPIMemoryNVS . ACPI FACS must be contained in memory of type EﬁACPIMemoryNVS
Memory orEﬁACPIMemoryNVS .
• EFI memory descriptors of type EﬁACPIReclaimMemory andEﬁACPIMemoryNVS must be aligned on a 4 KiB
boundary and must be a multiple of 4 KiB in size.
• Any UEFI memory descriptor that requests a virtual mapping via the EFI_MEMORY_DESCRIPTOR having the
EFI_MEMORY_RUNTIME bit set must be aligned on a 4 KiB boundary and must be a multiple of 4 KiB in size.
• ACPI tables loaded at runtime must be contained in memory of type EﬁACPIMemoryNVS .
The cacheability attributes for ACPI tables loaded at runtime should be deﬁned in the UEFI memory map. If no
information about the table location exists in the UEFI memory map, cacheability attributes may be obtained from
ACPI memory descriptors. If no information about the table location exists in the UEFI memory map or ACPI
memory descriptors, the table is assumed to be non-cached.
2.3. Calling Conventions 41Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• In general, UEFI Conﬁguration Tables loaded at boot time (e.g., SMBIOS table) can be contained in memory of
type EﬁRuntimeServicesData (recommended), EﬁBootServicesData ,EﬁACPIReclaimMemory orEﬁACPIMem-
oryNVS . Tables loaded at runtime must be contained in memory of type EﬁRuntimeServicesData (recommended)
orEﬁACPIMemoryNVS .
used by ﬁrmware. The UEFI Speciﬁcation intends to clarify the situation moving forward. Also, only OSes conforming
to the UEFI Speciﬁcation are guaranteed to handle SMBIOS table in memory of type EﬁBootServicesData.
2.3.7.1 Handoff State
When UEFI ﬁrmware hands off control to Supervisor mode OS, RISC-V boot hart must be operated in Supervisor
mode, and the memory addressing must be operated in Bare mode which is no memory address translation or protection
through the virtual page table entry.
In order to describe the heterogeneous RISC-V cores and harts for the next boot stage after POST, UEFI ﬁrmware must
build up the information of core and hart hardware capabilities in the ﬁrmware data structure if the target bootable
image requires this information. (e.g. If the platform supports SMBIOS structure, SMBIOS record type 44 record,
see “Link to UEFI Speciﬁcation-Related Document” on https://ueﬁ.org/ueﬁ under the heading “RISC-V Processor
SMBIOS Speciﬁcation”).
UEFI based RISC-V platform ﬁrmware must implement the RISCV_EFI_BOOT_PROTOCOL for the boot image
that requires the boot information during the handoff from the ﬁrmware boot stage. Launched EFI binaries should
use the RISCV_EFI_BOOT_PROTOCOL.GetBootHartId() to obtain the boot hart ID. The boot hart ID information
provided by either SMBIOS or Device Tree (as described in the UEFI 2.9 speciﬁcation) is ignored by the boot image.
See “Links to UEFI Speciﬁcation-Related Document” on https://ueﬁ.org/ueﬁ under the heading “RISC-V EFI Boot
Protocol.”
If the platform supports Device Tree structure to describe the system conﬁgurations, the Flattened Device Blob (DTB)
must be installed in the EFI Conﬁguration Table ( EFI Conﬁguration Table & Properties Table for details).
All UEFI images takes two parameters: the UEFI image handle and the pointer to EFI System Table. According to the
RISC-V calling convention, EFI_HANDLE is passed through the a0 register and EFI_SYSTEM_TABLE is passed
through the a1 register.
• x10 - EFI_HANDLE (ABI name: a0)
• x11 - EFI_SYSTEM_TABLE (ABI name: a1)
• x1 - Return Address (ABI name: ra)
2.3.7.2 Data Alignment
In the RV32I and RV64I, the datatypes must be aligned at its natural size when stored in memory. The following table
describes the datatype and its alignment in RV32I and RV64I in UEFI.
Table 2.8: RV32 datatype alignment
Datatype Description Alignment
BOOLEAN Logical Boolean 1
INTN Signed value in native width. 4
UINTN Unsigned value in native width. 4
INT8 1-byte signed value 1
UINT8 1-byte unsigned value 1
INT16 2-byte signed value 2
2.3. Calling Conventions 42Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 2.8 – continued from previous page
UINT16 2-byte unsigned value 2
INT32 4-byte signed value 4
UINT32 4-byte unsigned value 4
INT64 8-byte signed value 8
UINT64 8-byte unsigned value 8
CHAR8 1-byte character 1
CHAR16 2-byte character 2
VOID Undeclared type 4
Table 2.9: RV64 datatype alignment
INTN Signed value in native width. 8
UINTN Unsigned value in native width. 8
VOID Undeclared type 8
2.3.7.3 Detailed Calling Convention
The RISC-V calling convention passes arguments in register when necessary. In RISC-V , total 32 general registers are
declared, each register has its corresponding ABI name.
Table 2.10: Register name and ABI name
Register ABI Name Description
x0 zero Hardwired to zero
x1 ra Return address
x2 sp Stack pointer
x3 gp Global pointer
x4 tp Thread pointer
x5-7 t0-2 Temporaries
x8 s0/fp Saved register/frame pointer
x9 s1 Saved register
x10-11 a0-1 Function arguments/Return values
x12-17 a2-7 Function arguments
x18-27 s2-11 Saved registers
x28-31 t3-6 Temporaries
In the RISC-V calling convention, up to eight integer registers are used for passing argument, a0-a7. a0-a7 are the ABI
names and the corresponding registers are x10-x17. Values are returned from functions in integer registers a0 and a1,
those are register x10 and x11. In the standard RISC-V calling convention, the stack grows downward and the stack
2.3. Calling Conventions 43Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
point is always kept 16-byte aligned. Five integer register t0-t6 are temporary registers that are volatile across calls
and must be saved by the caller if later used. Twelve integer registers s0-s11 are preserved across calls and must be
saved by the callee if used.
In view of the following statement:
“In the standard ABI, procedures should not modify the integer registers tp and gp, because signal handlers may rely
upon their values”
mentioned in the RISC-V EFL psABI Speciﬁcation, and the RISC-V calling convention that gp and tp registers are
not assigned a speciﬁc owner to save and restore their values (see links below), UEFI ﬁrmware must neither trust the
values of tp and gp nor make an assumption of owning the write access to these register in any circumstances. (Such
as in EFI Boot service, EFI Runtime service, EFI Management Mode service and any UEFI ﬁrmware interfaces which
may invoked by the EFI drivers, OS or external ﬁrmware payload.)
Preserve the values in gp or tp register if UEFI ﬁrmware needs to change them, and never touch them after ExitBoot-
Services(). Whether and how to preserve gp and tp in the UEFI ﬁrmware environment is implementation-speciﬁc.
See Links to UEFI Speciﬁcation-Related Documents (https://ueﬁ.org/ueﬁ) under the heading “RISC-V EFL psABI
Speciﬁcation”, and the RISC-V assembly programmer’s handbook section in the RISC-V Unprivileged ISA speciﬁca-
tion.
2.3.8 LoongArch Platforms
All functions are called with the C language calling convention speciﬁed in the Detailed Calling Conventions section
in 2.3.8.2.
LoongArch processor cores are divided into four privilege levels (PLV0 to PLV3). Usually, the PLV3 are recommended
for the user mode.
LoongArch UEFI will only be executed in PLV0 mode. PLV0 is the privilege level with the highest privilege and is the
only privilege level that can use privileged instructions and access all privileged resources. The three privilege levels,
PLV1 to PLV3, cannot execute privileged instructions to access privileged resources.

tion.
• Total 32 general-purpose integer registers, r0-r31.
• FP unit can be used(CSR.EUEN.FPE to enable), calling convention refer to 2.3.8.2. If the FP unit is used, it is
recommended to save and restore ﬂoating-point registers in exception context to improve security.
• Instruction and Data caches enabled.
• MMU enabled.
• Address space is uniform addressing.
• The processor reset vactor has been ﬁxed and the address is 0x1c00,0000.
• Control and Status Resgers(CSRs) are support.
• The memory is in physical addressing mode. LoongArch architecture deﬁnes two memory access modes,
namely direct address translation mode and mapped address translation mode. In driect address translation
mode, the address load/store consistent cacheable type determined by CSR.DATM, and in the mapped address
translation mode, the consistent cacheable type determined by TLB consistent cacheable type.
• 128 KiB or more available stack space.
• The stack must be 16-byte aligned.
2.3. Calling Conventions 44Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Stable counter enabled.
• Timer Interrupt enabled.
• Preserve all memory in the memory map marked as runtime code and runtime data.
–In PLV0 mode.
–16 KiB, or more, of available stack space.
• EFI memory descriptors of type EﬁACPIReclaimMemory and EﬁACPIMemoryNVS must be aligned on a 64
KiB boundary and must be a multiple of 64 KiB in size.
the EFI_MEMORY_RUNTIME bit set must be aligned on a 64 KiB boundary and must be a multiple of 64 KiB
in size.
ory of type EﬁRuntimeServicesData (recommended), EﬁBootServicesdata, EﬁACPIReclaimMemory or Eﬁ-
2.3. Calling Conventions 45Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Note: Previous EFI speciﬁcations allowed ACPI tables loaded at runtime to be in the EﬁReservedMemoryType and
2.3.8.1 Handoff Statue
All UEFI image takes two parameters, these are UEFI image handle and the pointer to EFI System. Accord-
ing the LoongArch calling convention, two registers are used to pass them. EFI_HANDLE is passed by a0, and
EFI_SYSTEM_TABLE * is passed by a1.
• r4 - EFI_HANDLE(ABI name: a0)
• r5 - EFI_SYSTEM_TABLE *(ABI name: a1)
• r1 - Return Address(ABI name: ra)
2.3.8.2 Detailed Calling Convention
LoongArch architecture deﬁnes 32 general-purpose registers, and the ABI refer to https://loongson.github.io/
LoongArch-Documentation/LoongArch-ELF-ABI-EN.html. The basic principle of the LoongArch procedure call-
ing convention is to pass arguments in registers as much as possible (i.e. ﬂoating-point arguments are passed in
ﬂoating-point registers and non ﬂoating-point arguments are passed in general-purpose registers, as much as possible);
arguments are passed on the stack only when no appropriate register is available.
Eight general-purpose register r4-r11(general-pupose argument registers, ABI name: a0-a7) used for pass integer
arguments, with a0-a1 reused to return values. Eight ﬂoating-point registers f0-f7(ﬂoating-point argument registers,
ABI name: fa0-fa7) used for pass ﬂoating-point arguments, and fa0-fa1 are also used to return values. Generally,
the general-pupose argument registers are used to pass ﬁxed-point arguments, and ﬂoating-point arguments when no
ﬂoating-point argument register is available. Bit ﬁelds are stored in little endian. In addition, subroutines should ensure
that the values of general-purpose registers r22-r31(ABI name: s0-s9) and ﬂoating-point registers f24-f31(ABI name:
fs0-fs7) are preserved across procedure calls.
2.4 Protocols
The protocols that a device handle supports are discovered through the EFI_BOOT_SERVICES.HandleProtocol() Boot
Service or EFI_BOOT_SERVICES.OpenProtocol() Boot Service. Each protocol has a speciﬁcation that includes the
following:
• The protocol’s globally unique ID (GUID)
• The Protocol Interface structure
• The Protocol Services
Unless otherwise speciﬁed a protocol’s interface structure is not allocated from runtime memory and the protocol
member functions should not be called at runtime. If not explicitly speciﬁed a protocol member function can be called
at a TPL level of less than or equal to TPL_NOTIFY ( Event, Timer, and Task Priority Services ). Unless otherwise
speciﬁed a protocol’s member function is not reentrant or MP safe.
Any status codes deﬁned by the protocol member function deﬁnition are required to be implemented, Additional
error codes may be returned, but they will not be tested by standard compliance tests, and any software that uses the
procedure cannot depend on any of the extended error codes that an implementation may provide.
2.4. Protocols 46Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
To determine if the handle supports any given protocol, the protocol’s GUID is passed to HandleProtocol() or OpenPro-
tocol() . If the device supports the requested protocol, a pointer to the deﬁned Protocol Interface structure is returned.
The Protocol Interface structure links the caller to the protocol-speciﬁc services to use for this device.
The Figue below shows the construction of a protocol. The UEFI driver contains functions spe-
ciﬁc to one or more protocol implementations, and registers them with the Boot Service, see
EFI_BOOT_SERVICES.InstallProtocolInterface() . The ﬁrmware returns the Protocol Interface for the protocol
that is then used to invoke the protocol speciﬁc services. The UEFI driver keeps private, device-speciﬁc context with
protocol interfaces.
Fig. 2.4: Construction of a Protocol
The following C code fragment illustrates the use of protocols:
// There is a global "EffectsDevice" structure. This
// structure contains information to the device.
// Connect to the ILLUSTRATION_PROTOCOL on the EffectsDevice,
// by calling HandleProtocol with the device’s EFI device handle
// and the ILLUSTRATION_PROTOCOL GUID.

EffectsDevice.Handle = DeviceHandle;
Status = HandleProtocol (
EffectsDevice.EFIHandle,
&IllustrationProtocolGuid,
&EffectsDevice.IllustrationProtocol
);
// Use the EffectsDevice illustration protocol’s "MakeEffects"
// service to make flashy and noisy effects.
Status = EffectsDevice.IllustrationProtocol->MakeEffects (
EffectsDevice.IllustrationProtocol,
TheFlashyAndNoisyEffect
);
The Table below, UEFI Protocols , lists the UEFI protocols deﬁned by this speciﬁcation.
Table 2.11: UEFI Protocols
Protocol Description
EFI Loaded Image Protocol Provides information on the image.
2.4. Protocols 47Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 2.11 – continued from previous page
EFI Loaded Image Device Path Protocol Speciﬁes the device path that was used when a
PE/COFF image was loaded through the EFI Boot Ser-
vice LoadImage().
EFI Device Path Protocol Provides the location of the device.
EFI Driver Binding Protocol Provides services to determine if an UEFI driver sup-
ports a given controller, and services to start and stop a
given controller.
EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL Provides a the Driver Family Override mechanism for
selecting the best driver for a given controller.
EFI Platform Driver Override Protocol Provide a platform speciﬁc override mechanism for the
selection of the best driver for a given controller.
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL Provides a bus speciﬁc override mechanism for the se-
lection of the best driver for a given controller.
EFI_DRIVER_DIAGNOSTICS2_PROTOCOL Provides diagnostics services for the controllers that
UEFI drivers are managing.
EFI_COMPONENT_NAME2_PROTOCOL Provides human readable names for UEFI Drivers and
the controllers that the drivers are managing.
EFI_SIMPLE_TEXT_INPUT_PROTOCOL Protocol interfaces for devices that support simple con-
sole style text input.
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL Protocol interfaces for devices that support console style
text displaying.
EFI_SIMPLE_POINTER_PROTOCOL Protocol interfaces for devices such as mice and track-
balls.
EFI_SERIAL_IO_PROTOCOL Protocol interfaces for devices that support serial char-
acter transfer.
EFI_LOAD_FILE_PROTOCOL Protocol interface for reading a ﬁle from an arbitrary
device.
EFI_LOAD_FILE2_PROTOCOL Protocol interface for reading a non-boot option ﬁle
from an arbitrary device
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL Protocol interfaces for opening disk volume containing
a UEFI ﬁle system.
EFI_FILE_PROTOCOL Provides access to supported ﬁle systems.
EFI_DISK_IO_PROTOCOL A protocol interface that layers onto any BLOCK_IO or
BLOCK_IO_EX interface.
EFI_BLOCK_IO_PROTOCOL Protocol interfaces for devices that support block I/O
style accesses.
EFI_BLOCK_IO2_PROTOCOL Protocol interfaces for devices that support block I/O
style accesses. This interface is capable of non-blocking
transactions.
EFI_UNICODE_COLLATION_PROTOCOL Protocol interfaces for string comparison operations.
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Protocol interfaces to abstract memory, I/O, PCI conﬁg-
uration, and DMA accesses to a PCI root bridge con-
troller.
EFI PCI I/O Protocol Protocol interfaces to abstract memory, I/O, PCI conﬁg-
uration, and DMA accesses to a PCI controller on a PCI
bus.
EFI_USB_IO_PROTOCOL Protocol interfaces to abstract access to a USB con-
troller.
EFI_SIMPLE_NETWORK_PROTOCOL Provides interface for devices that support packet based
transfers.
2.4. Protocols 48Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_PXE_BASE_CODE_PROTOCOL Protocol interfaces for devices that support network
booting.
EFI_BIS_PROTOCOL Protocol interfaces to validate boot images before they
are loaded and invoked.
EFI Debug Support Protocol Protocol interfaces to save and restore processor context
and hook processor exceptions.
EFI Debugport Protocol Protocol interface that abstracts a byte stream connec-
tion between a debug host and a debug target system.
EFI_DECOMPRESS_PROTOCOL Protocol interfaces to decompress an image that was
compressed using the EFI Compression Algorithm.
EFI_EBC_PROTOCOL Protocols interfaces required to support an EFI Byte
Code interpreter.
EFI_GRAPHICS_OUTPUT_PROTOCOL Protocol interfaces for devices that support graphical
output.
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL Protocol interfaces that allow NVM Express commands
to be issued to an NVM Express controller.
EFI_EXT_SCSI_PASS_THRU_PROTOCOL Protocol interfaces for a SCSI channel that allows SCSI
Request Packets to be sent to SCSI devices.
EFI_USB2_HC_PROTOCOL Protocol interfaces to abstract access to a USB Host
Controller.
EFI_AUTHENTICATION_INFO_PROTOCOL Provides access for generic authentication information
associated with speciﬁc device paths
EFI_DEVICE_PATH_UTILITIES_PROTOCOL Aids in creating and manipulating device paths.
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL Converts device nodes and paths to text.
EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL Converts text to device paths and device nodes.
EFI_EDID_DISCOVERED_PROTOCOL Contains the EDID information retrieved from a video
output device.
EFI_EDID_ACTIVE_PROTOCOL Contains the EDID information for an active video out-
put device.
EFI_EDID_OVERRIDE_PROTOCOL Produced by the platform to allow the platform to pro-
vide EDID information to the producer of the Graphics
Output protocol
EFI iSCSI Initiator Name Protocol Sets and obtains the iSCSI Initiator Name.
EFI_TAPE_IO_PROTOCOL Provides services to control and access a tape drive.
EFI Managed Network Protocol Used to locate communication devices that are sup-
ported by an MNP driver and create and destroy in-
stances of the MNP child protocol driver that can use
the underlying communications devices.
EFI_ARP_SERVICE_BINDING_PROTOCOL Used to locate communications devices that are sup-
ported by an ARP driver and to create and destroy in-
stances of the ARP child protocol driver.
EFI_ARP_PROTOCOL Used to resolve local network protocol addresses into
network hardware addresses.
EFI_DHCP4_SERVICE_BINDING_PROTOCOL Used to locate communication devices that are sup-
ported by an EFI DHCPv4 Protocol driver and to cre-
ate and destroy EFI DHCPv4 Protocol child driver in-
stances that can use the underlying communications de-
vices.
EFI_DHCP4_PROTOCOL Used to collect conﬁguration information for the EFI
IPv4 Protocol drivers and to provide DHCPv4 server
and PXE boot server discovery services.
2.4. Protocols 49Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_TCP4_SERVICE_BINDING_PROTOCOL Used to locate EFI TCPv4Protocol drivers to create and
destroy child of the driver to communicate with other
host using TCP protocol.
EFI_TCP4_PROTOCOL Provides services to send and receive data stream.
EFI_IP4_SERVICE_BINDING_PROTOCOL Used to locate communication devices that are sup-
ported by an EFI IPv4 Protocol Driver and to create and
destroy instances of the EFI IPv4 Protocol child proto-
col driver that can use the underlying communication
device.
EFI_IP4_PROTOCOL Provides basic network IPv4 packet I/O services.
EFI_IP4_CONFIG2_PROTOCOL The EFI IPv4 Conﬁg Protocol driver performs platform-
and policy-dependent conﬁguration of the EFI IPv4 Pro-
tocol driver.
EFI_IP4_CONFIG2_PROTOCOL The EFI IPv4 Conﬁguration II Protocol driver performs
platform- and policy-dependent conﬁguration of the EFI
IPv4 Protocol driver.
EFI_UDP4_SERVICE_BINDING_PROTOCOL Used to locate communication devices that are sup-
ported by an EFI UDPv4 Protocol driver and to create
and destroy instances of the EFI UDPv4 Protocol child
protocol driver that can use the underlying communica-
tion device.
EFI_UDP4_PROTOCOL Provides simple packet-oriented services to transmit and
receive UDP packets.
EFI_MTFTP4_SERVICE_BINDING_PROTOCOL Used to locate communication devices that are sup-
ported by an EFI MTFTPv4 Protocol driver and to cre-
ate and destroy instances of the EFI MTFTPv4 Protocol
child protocol driver that can use the underlying com-
munication device.
EFI_MTFTP4_PROTOCOL Provides basic services for client-side unicast or multi-
cast TFTP operations.
EFI_HASH_PROTOCOL Allows creating a hash of an arbitrary message digest
using one or more hash algorithms.
EFI_HASH_SERVICE_BINDING_PROTOCOL Used to locate hashing services support provided by a
driver and create and destroy instances of the EFI Hash
Protocol so that a multiple drivers can use the underly-
ing hashing services.
EFI_SD_MMC_PASS_THRU_PROTOCOL Protocol interface that allows SD/eMMC commands to
be sent to an SD/eMMC controller.
2.5 UEFI Driver Model
The UEFI Driver Model is intended to simplify the design and implementation of device drivers, and produce small
executable image sizes. As a result, some complexity has been moved into bus drivers and in a larger part into common
ﬁrmware services.
A device driver is required to produce a Driver Binding Protocol on the same image handle on which the driver was

loaded. It then waits for the system ﬁrmware to connect the driver to a controller. When that occurs, the device
driver is responsible for producing a protocol on the controller’s device handle that abstracts the I/O operations that
the controller supports. A bus driver performs these exact same tasks. In addition, a bus driver is also responsible for
discovering any child controllers on the bus, and creating a device handle for each child controller found.
One assumption is that the architecture of a system can be viewed as a set of one or more processors connected to one
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or more core chipsets. The core chipsets are responsible for producing one or more I/O buses. The UEFI Driver Model
does not attempt to describe the processors or the core chipsets. Instead, the UEFI Driver Model describes the set of
I/O buses produced by the core chipsets, and any children of these I/O buses. These children can either be devices or
additional I/O buses. This can be viewed as a tree of buses and devices with the core chipsets at the root of that tree.
The leaf nodes in this tree structure are peripherals that perform some type of I/O. This could include keyboards,
displays, disks, network, etc. The nonleaf nodes are the buses that move data between devices and buses, or between
different bus types. Desktop System shows a sample desktop system with four buses and six devices.
Fig. 2.5: Desktop System
Server System is an example of a more complex server system. The idea is to make the UEFI Driver Model simple and
extensible so more complex systems like the one below can be described and managed in the preboot environment.
This system contains six buses and eight devices.
The combination of ﬁrmware services, bus drivers, and device drivers in any given platform is likely to be produced by
a wide variety of vendors including OEMs, IBVs, and IHVs. These different components from different vendors are
required to work together to produce a protocol for an I/O device than can be used to boot a UEFI compliant operating
system. As a result, the UEFI Driver Model is described in great detail in order to increase the interoperability of these
components
This remainder of this section is a brief overview of the UEFI Driver Model . It describes the legacy option ROM
issues that the UEFI Driver Model is designed to address, the entry point of a driver, host bus controllers, properties
of device drivers, properties of bus drivers, and how the UEFI Driver Model can accommodate hot-plug events.
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Fig. 2.6: Server System
2.5.1 Legacy Option ROM Issues
Legacy option ROMs have a number of constraints and limitations that restrict innovation on the part of platform
designers and adapter vendors. At the time of writing, both ISA and PCI adapters use legacy option ROMs. For the
purposes of this discussion, only PCI option ROMs will be considered; legacy ISA option ROMs are not supported as
part of the UEFI Speciﬁcation .
The following is a list of the major constraints and limitations of legacy option ROMs. For each issue, the design
considerations that went into the design of the UEFI Driver Model are also listed. Thus, the design of the UEFI Driver
Model directly addresses the requirements for a solution to overcome the limitations implicit to PC-AT-style legacy
option ROMs.
2.5.1.1 32-bit/16-Bit Real Mode Binaries
Legacy option ROMs typically contain 16-bit real mode code for an IA-32 processor. This means that the legacy
option ROM on a PCI card cannot be used in platforms that do not support the execution of IA-32 real mode binaries.
Also, 16-bit real mode only allows the driver to access directly the lower 1 MiB of system memory. It is possible
for the driver to switch the processor into modes other than real mode in order to access resources above 1 MiB,
but this requires a lot of additional code, and causes interoperability issues with other option ROMs and the system
BIOS. Also, option ROMs that switch the processor into to alternate execution modes are not compatible with Itanium
Processors.
UEFI Driver Model design considerations:
• Drivers need ﬂat memory mode with full access to system components.
• Drivers need to be written in C so they are portable between processor architectures.
• Drivers may be compiled into a virtual machine executable, allowing a single binary driver to work on machines
using different processor architectures.
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2.5.1.2 Fixed Resources for Working with Option ROMs
Since legacy option ROMs can only directly address the lower 1 MiB of system memory, this means that the code from
the legacy option ROM must exist below 1 MiB. In a PC-AT platform, memory from 0x00000-0x9FFFF is system
memory. Memory from 0xA0000-0xBFFFF is VGA memory, and memory from 0xF0000-0xFFFFF is reserved for the
system BIOS. Also, since system BIOS has become more complex over the years, many platforms also use 0xE0000-
0xEFFFF for system BIOS. This leaves 128 KiB of memory from 0xC0000-0xDFFFF for legacy option ROMs. This
limits how many legacy option ROMs can be run during BIOS POST.
Also, it is not easy for legacy option ROMs to allocate system memory. Their choices are to allocate memory from
Extended BIOS Data Area (EBDA), allocate memory through a Post Memory Manager (PMM), or search for free
memory based on a heuristic. Of these, only EBDA is standard, and the others are not used consistently between
adapters, or between BIOS vendors, which adds complexity and the potential for conﬂicts.
• Drivers need to be capable of being relocated so that they can be loaded anywhere in memory (PE/COFF Images)
• Drivers should allocate memory through the boot services. These are well-speciﬁed interfaces, and can be
guaranteed to function as expected across a wide variety of platform implementations.
2.5.1.3 Matching Option ROMs to their Devices
It is not clear which controller may be managed by a particular legacy option ROM. Some legacy option ROMs search
the entire system for controllers to manage. This can be a lengthy process depending on the size and complexity of the
platform. Also, due to limitation in BIOS design, all the legacy option ROMs must be executed, and they must scan
for all the peripheral devices before an operating system can be booted. This can also be a lengthy process, especially
if SCSI buses must be scanned for SCSI devices. This means that legacy option ROMs are making policy decision
about how the platform is being initialized, and which controllers are managed by which legacy option ROMs. This
makes it very difﬁcult for a system designer to predict how legacy option ROMs will interact with each other. This
can also cause issues with on-board controllers, because a legacy option ROM may incorrectly choose to manage the
on-board controller.
• Driver to controller matching must be deterministic
• Give OEMs more control through Platform Driver Override Protocol and Driver Conﬁguration Protocol
• It must be possible to start only the drivers and controllers required to boot an operating system.
2.5.1.4 Ties to PC-AT System Design
Legacy option ROMs assume a PC-AT-like system architecture. Many of them include code that directly touches
hardware registers. This can make them incompatible on legacy-free and headless platforms. Legacy option ROMs
may also contain setup programs that assume a PC-AT-like system architecture to interact with a keyboard or video
display. This makes the setup application incompatible on legacy-free and headless platforms.
• Drivers should use well-deﬁned protocols to interact with system hardware, system input devices, and syste-
moutput devices.
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2.5.1.5 Ambiguities in Speciﬁcation and WorkaroundsBorn of Experience
Many legacy option ROMs and BIOS code contain workarounds because of incompatibilities between legacy option
ROMs and system BIOS. These incompatibilities exist in part because there are no clear speciﬁcations on how to write
a legacy option ROM or write a system BIOS.
Also, interrupt chaining and boot device selection is very complex in legacy option ROMs. It is not always clear which
device will be the boot device for the OS.
• Drivers and ﬁrmware are written to follow this speciﬁcation. Since both components have a clearly deﬁned
speciﬁcation, compliance tests can be developed to prove that drivers and system ﬁrmware are compliant. This
should eliminate the need to build workarounds into either drivers or system ﬁrmware (other than those that

might be required to address speciﬁc hardware issues).
• Give OEMs more control through Platform Driver Override Protocol and Driver Conﬁguration Protocol and
other OEM value-add components to manage the boot device selection process.
2.5.2 Driver Initialization
The ﬁle for a driver image must be loaded from some type of media. This could include ROM, FLASH, hard drives,
ﬂoppy drives, CD-ROM, or even a network connection. Once a driver image has been found, it can be loaded into
system memory with the boot service EFI_BOOT_SERVICES.LoadImage() . LoadImage() loads a PE/COFF formatted
image into system memory. A handle is created for the driver, and a Loaded Image Protocol instance is placed on that
handle. A handle that contains a Loaded Image Protocol instance is called an Image Handle . At this point, the driver
has not been started. It is just sitting in memory waiting to be started. The ﬁgure below shows the state of an image
handle for a driver after LoadImage() has been called.
Fig. 2.7: Image Handle
After a driver has been loaded with the boot service LoadImage(), it must be started with the boot service
EFI_BOOT_SERVICES.StartImage() . This is true of all types of UEFI Applications and UEFI Drivers that can be
loaded and started on an UEFI-compliant system. The entry point for a driver that follows the UEFI Driver Model
must follow some strict rules. First, it is not allowed to touch any hardware. Instead, the driver is only allowed to
install protocol instances onto its own Image Handle . A driver that follows the UEFI Driver Model isrequired to
install an instance of the Driver Binding Protocol onto its own Image Handle . It may optionally install the Driver
Conﬁguration Protocol, the Driver Diagnostics Protocol, or the Component Name Protocol. In addition, if a driver
wishes to be unloadable it may optionally update the Loaded Image Protocol ( EFI Loaded Image Protocol ) to provide
its own Unload() EFI_LOADED_IMAGE_PROTOCOL.Unload() function. Finally, if a driver needs to perform any
special operations when the boot service EFI_BOOT_SERVICES.ExitBootServices() is called, it may optionally create
an event with a notiﬁcation function that is triggered when the boot service ExitBootServices() is called. An Image
Handle that contains a Driver Binding Protocol instance is known as a Driver Image Handle .Driver Image Handle
shows a possible conﬁguration for the Image Handle from Fig. 2.7 after the boot service StartImage() has been called.
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Fig. 2.8: Driver Image Handle
2.5.3 Host Bus Controllers
Drivers are not allowed to touch any hardware in the driver’s entry point. As a result, drivers will be loaded and started,
but they will all be waiting to be told to manage one or more controllers in the system. A platform component, like
the Boot Manager, is responsible for managing the connection of drivers to controllers. However, before even the ﬁrst
connection can be made, there has to be some initial collection of controllers for the drivers to manage. This initial
collection of controllers is known as the Host Bus Controllers. The I/O abstractions that the Host Bus Controllers
provide are produced by ﬁrmware components that are outside the scope of the UEFI Driver Model . The device
handles for the Host Bus Controllers and the I/O abstraction for each one must be produced by the core ﬁrmware
on the platform, or a driver that may not follow the UEFI Driver Model. See the PCI Root Bridge I/O Protocol
Speciﬁcation for an example of an I/O abstraction for PCI buses.
A platform can be viewed as a set of processors and a set of core chipset components that may produce one or more
host buses. The following ﬁgure shows a platform with n processors (CPUs), and a set of core chipset components
that produce m host bridges.
Each host bridge is represented in UEFI as a device handle that contains a Device Path Protocol instance, and a protocol
instance that abstracts the I/O operations that the host bus can perform. For example, a PCI Host Bus Controller
supports one or more PCI Root Bridges that are abstracted by the PCI Root Bridge I/O Protocol. The following ﬁgure
shows an example device handle for a PCI Root Bridge.
A PCI Bus Driver could connect to this PCI Root Bridge, and create child handles for each of the PCI devices in
the system. PCI Device Drivers should then be connected to these child handles, and produce I/O abstractions that
may be used to boot a UEFI compliant OS. The following section describes the different types of drivers that can be
implemented within the UEFI Driver Model . The UEFI Driver Model is very ﬂexible, so all the possible types of
drivers will not be discussed here. Instead, the major types will be covered that can be used as a starting point for
designing and implementing additional driver types.
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Fig. 2.9: Host Bus Controllers
Fig. 2.10: PCI Root Bridge Device Handle
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2.5.4 Device Drivers
A device driver is not allowed to create any new device handles. Instead, it installs additional protocol interfaces on
an existing device handle. The most common type of device driver will attach an I/O abstraction to a device handle
that was created by a bus driver. This I/O abstraction may be used to boot a UEFI compliant OS. Some example I/O
abstractions would include Simple Text Output, Simple Input, Block I/O, and Simple Network Protocol. Fig. 2.11
shows a device handle before and after a device driver is connected to it. In this example, the device handle is a child
of the XYZ Bus, so it contains an XYZ I/O Protocol for the I/O services that the XYZ bus supports. It also contains a
Device Path Protocol that was placed there by the XYZ Bus Driver. The Device Path Protocol is not required for all
device handles. It is only required for device handles that represent physical devices in the system. Handles for virtual
devices will not contain a Device Path Protocol.
Fig. 2.11: Connecting Device Drivers
The device driver that connects to the device handle in the above Figure must have installed a Driver Bind-
ing Protocol on its own image handle. The Driver Binding Protocol contains three functions called Supported()
(EFI_DRIVER_BINDING_PROTOCOL.Supported() ); Start() ( EFI_DRIVER_BINDING_PROTOCOL.Start() ), and
Stop() ( EFI_DRIVER_BINDING_PROTOCOL.Stop() ). The Supported() function tests to see if the driver supports a
given controller. In this example, the driver will check to see if the device handle supports the Device Path Protocol
and the XYZ I/O Protocol. If a driver’s Supported() function passes, then the driver can be connected to the controller
by calling the driver’s Start() function. The Start() function is what actually adds the additional I/O protocols to a
device handle. In this example, the Block I/O Protocol is being installed. To provide symmetry, the Driver Binding
Protocol also has a Stop()function that forces the driver to stop managing a device handle. This will cause the device
driver to uninstall any protocol interfaces that were installed in Start().
The Supported() , Start() , and Stop() functions of the EFI Driver Binding Protocol are required to make
use of the boot service EFI_BOOT_SERVICES.OpenProtocol() to get a protocol interface and the boot service
EFI_BOOT_SERVICES.CloseProtocol() to release a protocol interface. OpenProtocol() and CloseProtocol() update
the handle database maintained by the system ﬁrmware to track which drivers are consuming protocol interfaces. The
information in the handle database can be used to retrieve information about both drivers and controllers. The new
boot service EFI_BOOT_SERVICES.OpenProtocolInformation() can be used to get the list of components that are
currently consuming a speciﬁc protocol interface.
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2.5.5 Bus Drivers
Bus drivers and device drivers are virtually identical from the UEFI Driver Model ’s point of view. The only difference
is that a bus driver creates new device handles for the child controllers that the bus driver discovers on its bus. As a
result, bus drivers are slightly more complex than device drivers, but this in turn simpliﬁes the design and implemen-
tation of device drivers. There are two major types of bus drivers. The ﬁrst creates handles for all child controllers on
the ﬁrst call to Start() . The other type allows the handles for the child controllers to be created across multiple calls
to Start() . This second type of bus driver is very useful in supporting a rapid boot capability. It allows a few child
handles or even one child handle to be created. On buses that take a long time to enumerate all of their children (e.g.

SCSI), this can lead to a very large timesaving in booting a platform. Connecting Bus Drivers shows the tree st ructure
of a bus controller before and after Start() is called. The dashed line coming into the bus controller node represents
a link to the bus controller’s parent controller. If the bus controller is a Host Bus Controller , then it will not have a
parent controller. Nodes A, B, C ,D, and E represent the child controllers of the bus controller.
Fig. 2.12: Connecting Bus Drivers
A bus driver that supports creating one child on each call to Start() might choose to create child C ﬁrst, and then child
E, and then the remaining children A, B, and D. The Supported() , Start() , and Stop() functions of the Driver Binding
Protocol are ﬂexible enough to allow this type of behavior.
A bus driver must install protocol interfaces onto every child handle that is creates. At a minimum, it must install
a protocol interface that provides an I/O abstraction of the bus’s services to the child controllers. If the bus driver
creates a child handle that represents a physical device, then the bus driver must also install a Device Path Pro-
tocol instance onto the child handle. A bus driver may optionally install a Bus Speciﬁc Driver Override Protocol
onto each child handle. This protocol is used when drivers are connected to the child controllers. The boot service
EFI_BOOT_SERVICES.ConnectController() uses architecturally deﬁned precedence rules to choose the best set of
drivers for a given controller. The Bus Speciﬁc Driver Override Protocol has higher precedence than a general driver
search algorithm, and lower precedence than platform overrides. An example of a bus speciﬁc driver selection occurs
with PCI. A PCI Bus Driver gives a driver stored in a PCI controller’s option ROM a higher precedence than drivers
stored elsewhere in the platform. Child Device Handle with a Bus Speciﬁc Override shows an example child device
handle that was created by the XYZ Bus Driver that supports a bus speciﬁc driver override mechanism.
2.5.6 Platform Components
Under the UEFI Driver Model , the act of connecting and disconnecting drivers from controllers in a platform
is under the platform ﬁrmware’s control. This will typically be implemented as part of the UEFI Boot Man-
ager, but other implementations are possible. The boot services EFI_BOOT_SERVICES.ConnectController() and
EFI_BOOT_SERVICES.DisconnectController() can be used by the platform ﬁrmware to determine which controllers
get started and which ones do not. If the platform wishes to perform system diagnostics or install an operating system,
then it may choose to connect drivers to all possible boot devices. If a platform wishes to boot a preinstalled operating
system, it may choose to only connect drivers to the devices that are required to boot the selected operating system.
The UEFI Driver Model supports both these modes of operation through the boot services ConnectController() and
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Fig. 2.13: Child Device Handle with a Bus Speciﬁc Override
DisconnectController() . In addition, since the platform component that is in charge of booting the platform has to
work with device paths for console devices and boot options, all of the services and protocols involved in the UEFI
Driver Model are optimized with device paths in mind.
Since the platform ﬁrmware may choose to only connect the devices required to produce consoles and gain access to
a boot device, the OS present device drivers cannot assume that a UEFI driver for a device has been executed. The
presence of a UEFI driver in the system ﬁrmware or in an option ROM does not guarantee that the UEFI driver will
be loaded, executed, or allowed to manage any devices in a platform. All OS present device drivers must be able to
handle devices that have been managed by a UEFI driver and devices that have not been managed by an UEFI driver.
The platform may also choose to produce a protocol named the Platform Driver Override Protocol. This is similar
to the Bus Speciﬁc Driver Override Protocol, but it has higher priority. This gives the platform ﬁrmware the highest
priority when deciding which drivers are connected to which controllers. The Platform Driver Override Protocol is
attached to a handle in the system. The boot service ConnectController() will make use of this protocol if it is present
in the system.
2.5.7 Hot-Plug Events
In the past, system ﬁrmware has not had to deal with hot-plug events in the preboot environment. However, with the
advent of buses like USB, where the end user can add and remove devices at any time, it is important to make sure
that it is possible to describe these types of buses in the UEFI Driver Model. It is up to the bus driver of a bus that
supports the hot adding and removing of devices to provide support for such events. For these types of buses, some of
the platform management is going to have to move into the bus drivers. For example, when a keyboard is hot added
to a USB bus on a platform, the end user would expect the keyboard to be active. A USB Bus driver could detect
the hot-add event and create a child handle for the keyboard device. However, because drivers are not connected to
controllers unless EFI_BOOT_SERVICES.ConnectController() is called, the keyboard would not become an active
input device. Making the keyboard driver active requires the USB Bus driver to call ConnectController() when a hot-
add event occurs. In addition, the USB Bus Driver would have to call EFI_BOOT_SERVICES.DisconnectController()
when a hot-remove event occurs. If EFI_BOOT_SERVICES.DisconnectController() returns an error the USB Bus
Driver needs to retry EFI_BOOT_SERVICES.DisconnectController() from a timer event until it succeeds.
Device drivers are also affected by these hot-plug events. In the case of USB, a device can be removed without any
notice. This means that the Stop() functions of USB device drivers will have to deal with shutting down a driver for a
device that is no longer present in the system. As a result, any outstanding I/O requests will have to be ﬂushed without
actually being able to touch the device hardware.
In general, adding support for hot-plug events greatly increases the complexity of both bus drivers and device drivers.
Adding this support is up to the driver writer, so the extra complexity and size of the driver will need to be weighed
against the need for the feature in the preboot environment.
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2.5.8 EFI Services Binding
The UEFI Driver Model maps well onto hardware devices, hardware bus controllers, and simple combinations of
software services that layer on top of hardware devices. However, the UEFI driver Model does not map well onto
complex combinations of software services. As a result, an additional set of complementary protocols are required for
more complex combinations of software services.
Figure below, Software Service Relationships , contains three examples showing the different ways that software
services relate to each other. In the ﬁrst two cases, each service consumes one or more other services, and at most
one other service consumes all of the services. Case #3 differs because two different services consume service A.
The EFI_DRIVER_BINDING_PROTOCOL can be used to model cases #1 and #2, but it cannot be used to model
case #3 because of the way that the UEFI Boot Service OpenProtocol() behaves. When used with the BY_DRIVER
open mode, OpenProtocol() allows each protocol to have only at most one consumer. This feature is very useful and
prevents multiple drivers from attempting to manage the same controller. However, it makes it difﬁcult to produce sets
of software services that look like case #3.
Fig. 2.14: Software Service Relationships
Software Service Relationships The EFI_SERVICE_BINDING_PROTOCOL provides the mechanism that al-
lows protocols to have more than one consumer. The EFI_SERVICE_BINDING_PROTOCOL is used with
theEFI_DRIVER_BINDING_PROTOCOL . A UEFI driver that produces protocols that need to be available
to more than one consumer at the same time will produce both the EFI_DRIVER_BINDING_PROTOCOL
and the EFI_SERVICE_BINDING_PROTOCOL . This type of driver is a hybrid driver that will produce the
EFI_DRIVER_BINDING_PROTOCOL in its driver entry point.
When the driver receives a request to start managing a controller, it will produce the
EFI_SERVICE_BINDING_PROTOCOL on the handle of the controller that is being started. The
EFI_SERVICE_BINDING_PROTOCO*L is slightly different from other protocols deﬁned in the UEFI Speciﬁ-
cation. It does not have a GUID associated with it. Instead, this protocol instance structure actually represents
a family of protocols. Each software service driver that requires an *EFI_SERVICE_BINDING_PROTOCOL
instance will be required to generate a new GUID for its own type of EFI_SERVICE_BINDING_PROTOCOL .

This requirement is why the various network protocols in this speciﬁcation contain two GUIDs. One is the
EFI_SERVICE_BINDING_PROTOCOL GUID for that network protocol, and the other GUID is for the protocol that
contains the speciﬁc member services produced by the network driver. The mechanism deﬁned here is not limited
to network protocol drivers. It can be applied to any set of protocols that the EFI_DRIVER_BINDING_PROTOCOL
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cannot directly map because the protocols contain one or more relationships like case #3 in Software Service
Relationships .
Neither the EFI_DRIVER_BINDING_PROTOCOL nor the combination of the EFI_DRIVER_BINDING_PROTOCOL
and the EFI_SERVICE_BINDING_PROTOCOL can handle circular dependencies. There are methods to allow circular
references, but they require that the circular link be present for short periods of time. When the protocols across the
circular link are used, these methods also require that the protocol must be opened with an open mode of EXCLUSIVE
, so that any attempts to deconstruct the set of protocols with a call to DisconnectController() will fail. As soon as the
driver is ﬁnished with the protocol across the circular link, the protocol should be closed.
2.6 Requirements
This document is an architectural speciﬁcation. As such, care has been taken to specify architecture in ways that
allow maximum ﬂexibility in implementation. However, there are certain requirements on which elements of this
speciﬁcation must be implemented to ensure that operating system loaders and other code designed to run with UEFI
boot services can rely upon a consistent environment.
For the purposes of describing these requirements, the speciﬁcation is broken up into required and optional elements.
In general, an optional element is completely deﬁned in the section that matches the element name. For required
elements however, the deﬁnition may in a few cases not be entirely self contained in the section that is named for the
particular element. In implementing required elements, care should be taken to cover all the semantics deﬁned in this
speciﬁcation that relate to the particular element.
A system vendor may choose not to implement all the required elements, for example on specialized system con-
ﬁgurations that do not support all the services and functionality implied by the required elements. However, since
most applications, drivers and operating system loaders are written assuming all the required elements are present on
a system that implements the UEFI speciﬁcation; any such code is likely to require explicit customization to run on a
less than complete implementation of the required elements in this speciﬁcation. On such systems, the implementa-
tion may choose to advertise the proﬁle which it conforms to using EFI_CONFORMANCE_PROFILES_TABLE (see
Section 4.6).
2.6.1 Required Elements
Required UEFI Implementation Elements lists the required elements. Any system that is designed to conform to
this speciﬁcation must provide a complete implementation of all these elements. This means that all the required
service functions and protocols must be present and the implementation must deliver the full semantics deﬁned in the
speciﬁcation for all combinations of calls and parameters. Implementers of applications, drivers or operating system
loaders that are designed to run on a broad range of systems conforming to the UEFI speciﬁcation may assume that all
such systems implement all the required elements.
Table 2.12: Required UEFI Implementation Elements
Element Description
EFI System Table Provides access to UEFI Boot Services, UEFI Runtime
Services, consoles, ﬁrmware vendor information, and
the system conﬁguration tables.
EFI_BOOT_SERVICES All functions deﬁned as boot services.
EFI_RUNTIME_SERVICES All functions deﬁned as runtime services.
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Table 2.12 – continued from previous page
EFI_DEVICE_PATH_UTILITIES_PROTOCOL Protocol interfaces to create and manipulate UEFI de-
vice paths and UEFI device path nodes.
2.6.2 Platform-Speciﬁc Elements
There are a number of elements that can be added or removed depending on the speciﬁc features that a platform
requires. Platform ﬁrmware developers are required to implement UEFI elements based upon the features included.
The following is a list of potential platform features and the elements that are required for each feature type:
1. If a platform includes console devices, the EFI_SIMPLE_TEXT_INPUT_PROTOCOL ,
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL , and EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL must
be implemented.
2. If a platform includes a conﬁguration infrastructure, then EFI_HII_DATABASE_PROTOCOL ,
EFI_HII_STRING_PROTOCOL , EFI HII Conﬁguration Routing Protocol , and
EFI_HII_CONFIG_ACCESS_PROTOCOL are required. If you support bitmapped fonts, you must sup-
portEFI_HII_FONT_PROTOCOL .
3. If a platform includes graphical console devices, then EFI_GRAPHICS_OUTPUT_PROTOCOL ,
EFI_EDID_DISCOVERED_PROTOCOL , and EFI_EDID_ACTIVE_PROTOCOL must be implemented.
In order to support the EFI_GRAPHICS_OUTPUT_PROTOCOL ; a platform must contain a driver to consume
EFI_GRAPHICS_OUTPUT_PROTOCOL and produce EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL even if
theEFI_GRAPHICS_OUTPUT_PROTOCOL is produced by an external driver.
4. If a platform includes a pointer device as part of its console support, EFI_SIMPLE_POINTER_PROTOCOL
must be implemented.
5. If a platform includes the ability to boot from a disk device, then
EFI_BLOCK_IO_PROTOCOL ,EFI_DISK_IO_PROTOCOL ,EFI_SIMPLE_FILE_SYSTEM_PROTOCOL ,
andEFI_UNICODE_COLLATION_PROTOCOL are required. In addition, partition support for MBR, GPT,
and El Torito must be implemented. For disk devices supporting the security commands of the SPC-4 or
ATA8-ACS command set EFI_STORAGE_SECURITY_COMMAND_PROTOCOL is also required. An external
driver may produce the Block I/O Protocol and the EFI_STORAGE_SECURITY_COMMAND_PROTOCOL .
All other protocols required to boot from a disk device must be carried as part of the platform.
6. If a platform includes the ability to perform a TFTP-based boot from a network device, then
EFI_PXE_BASE_CODE_PROTOCOL is required. The platform must be prepared to pro-
duce this protocol on any of EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL (UNDI),
EFI_SIMPLE_NETWORK_PROTOCOL , or EFI Managed Network Protocol . If a platform includes the
ability to validate a boot image received through a network device, it is also required that image veriﬁcation be
supported, including SetupMode equal zero and the boot image hash or a veriﬁcation certiﬁcate corresponding
to the image exist in the ‘db’ variable and not in the ‘dbx’ variable. An external driver may produce the UNDI
interface. All other protocols required to boot from a network device must be carried by the platform.
7. If a platform supports UEFI general purpose network applications, then the EFI Man-
aged Network Protocol , EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL ,
EFI_ARP_PROTOCOL , EFI_ARP_SERVICE_BINDING_PROTOCOL , EFI_DHCP4_PROTOCOL ,
EFI_DHCP4_SERVICE_BINDING_PROTOCOL ,EFI_TCP4_PROTOCOL ,EFI_TCP4_SERVICE_BINDING_PROTOCOL ,
EFI_IP4_CONFIG2_PROTOCOL , EFI_IP4_SERVICE_BINDING_PROTOCOL ,
EFI_IP4_CONFIG2_PROTOCOL ,EFI_UDP4_PROTOCOL , and EFI_UDP4_SERVICE_BINDING_PROTOCOL
are required. If additional IPv6 support is needed for the platform,
then EFI DHCP6 Protocol , EFI_DHCP6_SERVICE_BINDING_PROTOCOL ,
2.6. Requirements 62Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_TCP6_PROTOCOL , EFI_TCP6_SERVICE_BINDING_PROTOCOL , EFI_IP6_PROTOCOL ,
EFI_IP6_SERVICE_BINDING_PROTOCOL ,EFI_IP6_CONFIG_PROTOCOL EFI_UDP6_PROTOCOL
.EFI_UDP6_SERVICE_BINDING_PROTOCOL are additionally required. If the network application requires
DNS capability, EFI_DNS4_SERVICE_BINDING_PROTOCOL andEFI_DNS4_PROTOCOL are required for
the IPv4 stack. EFI_DNS6_SERVICE_BINDING_PROTOCOL andEFI_DNS6_PROTOCOL are required for
the IPv6 stack. If the network environment requires TLS feature, EFI TLS Service Binding Protocol ,EFI TLS
Protocol .EFI TLS Conﬁguration Protocol are required. If the network environment requires IPSEC feature,
EFI_IPSEC_CONFIG_PROTOCOL andEFI IPsec2 Protocol are required. If the network environment requires
VLAN features, EFI_VLAN_CONFIG_PROTOCOL is required.
8. If a platform includes a byte-stream device such as a UART, then the EFI_SERIAL_IO_PROTOCOL must be
implemented.
9. If a platform includes PCI bus support, then the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL , the EFI PCI I/O

Protocol , must be implemented.
10. If a platform includes USB bus support, then EFI_USB2_HC_PROTOCOL andEFI_USB_IO_PROTOCOL
must be implemented. An external device can support USB by producing a USB Host Controller Protocol.
11. If a platform includes an NVM Express controller, then EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL must
12. If a platform supports booting from a block-oriented NVM Express controller, then
EFI_BLOCK_IO_PROTOCOL must be implemented. An external driver may produce the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL . All other protocols required to boot from an NVM
Express subsystem must be carried by the platform.
13. If a platform includes an I/O subsystem that utilizes SCSI command packets, then
EFI_EXT_SCSI_PASS_THRU_PROTOCOL must be implemented.
14. If a platform supports booting from a block oriented SCSI peripheral, then EFI SCSI I/O Proto-
col and EFI_BLOCK_IO_PROTOCOL must be implemented. An external driver may produce the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL . All other protocols required to boot from a SCSI I/O subsystem
must be carried by the platform.
15. If a platform supports booting from an iSCSI peripheral, then the EFI iSCSI Initiator Name Protocol and
EFI_AUTHENTICATION_INFO_PROTOCOL must be implemented.
16. If a platform includes debugging capabilities, then EFI Debug Support Protocol , the EFI Debugport Protocol ,
and the EFI Image Info Table must be implemented.
17. If a platform includes the ability to override the default driver to the controller matching algorithm provided by
the UEFI Driver Model, then EFI Platform Driver Override Protocol must be implemented.
18. If a platform includes an I/O subsystem that utilizes ATA command packets, then the
EFI_ATA_PASS_THRU_PROTOCOL must be implemented.
19. If a platform supports option ROMs from devices not permanently attached to the platform and it supports the
ability to authenticate those option ROMs, then it must support the option ROM validation methods described in
Network Protocols — UDP and MTFTP and the authenticated EFI variables described in Exception for Machine
Check, INIT, and NMI .
20. If a platform includes the ability to authenticate UEFI images and the platform potentially supports more than
one OS loader, it must support the methods described in Network Protocols — UDP and MTFTP and the
authenticated UEFI variables described in Exception for Machine Check, INIT, and NMI .
21. EBC support is no longer required as of UEFI Speciﬁcation version 2.8. If an EBC interpreter is implemented,
then it must produce the EFI_EBC_PROTOCOL interface.
22. If a platform includes the ability to perform a HTTP-based boot from a network de-
vice, then the EFI_HTTP_SERVICE_BINDING_PROTOCOL , EFI_HTTP_PROTOCOL and
2.6. Requirements 63Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_HTTP_UTILITIES_PROTOCOL are required. If it includes the ability to perform a HTTPS-based
boot from network device, besides above protocols EFI TLS Service Binding Protocol ,EFI TLS Protocol and
EFI TLS Conﬁguration Protocol are also required. If it includes the ability to perform a HTTP(S)-based boot
with DNS feature, then EFI_DNS4_SERVICE_BINDING_PROTOCOL ,EFI_DNS4_PROTOCOL are required
for the IPv4 stack; EFI_DNS6_SERVICE_BINDING_PROTOCOL andEFI_DNS6_PROTOCOL are required
for the IPv6 stack.
23. If a platform includes the ability to perform a wireless boot from a network device with EAP feature, and if
this platform provides a standalone wireless EAP driver, then EFI_EAP_PROTOCOL ,EFI EAP Conﬁguration
Protocol , and EFI EAP Management2 Protocol are required; if the platform provides a standalone wireless
supplicant, then EFI Supplicant Protocol andEFI EAP Conﬁguration Protocol are required. If it includes the
ability to perform a wireless boot with TLS feature, then EFI TLS Service Binding Protocol ,EFI TLS Protocol
andEFI TLS Conﬁguration Protocol are required.
24. If a platform supports classic Bluetooth, then EFI_BLUETOOTH_HC_PROTOCOL ,
EFI_BLUETOOTH_IO_PROTOCOL , and EFI_BLUETOOTH_CONFIG_PROTOCOL must be imple-
mented, and EFI Bluetooth Attribute Protocol may be implemented. If a platform supports Bluetooth Smart
(Bluetooth Low Energy), then EFI_BLUETOOTH_HC_PROTOCOL ,EFI Bluetooth Attribute Protocol and
EFI_BLUETOOTH_LE_CONFIG_PROTOCOL must be implemented. If a platform supports both Bluetooth
classic and BluetoothLE, then both above requirements should be satisﬁed.
25. If a platform supports RESTful communication over HTTP or over an in-band path to a BMC, then the
EFI REST Protocol or EFI_REST_EX_PROTOCOL must be implemented. If EFI_REST_EX_PROTOCOL
is implemented, EFI_REST_EX_SERVICE_BINDING_PROTOCOL must be implemented as well. If
a platform supports Redﬁsh communication over HTTP or over an in-band path to a BMC, the
EFI_REDFISH_DISCOVER_PROTOCOL and EFI REST JSON Structure Protocol may be implemented.
26. If a platform includes the ability to use a hardware feature to create high quality random numbers, this capability
should be exposed by instance of EFI_RNG_PROTOCOL with at least one EFI RNG Algorithm supported.
27. If a platform permits the installation of Load Option Variables, (Boot####, or Driver####, or SysPrep####), the
platform must support and recognize all deﬁned values for Attributes within the variable and report these capa-
bilities in BootOptionSupport. If a platform supports installation of Load Option Variables of type Driver####,
all installed Driver#### variables must be processed and the indicated driver loaded and initialized during every
boot. And all installed SysPrep#### options must be processed prior to processing Boot#### options.
28. If the platform supports UEFI secure boot as described in Secure Boot and Driver Signing , the platform must
provide the PKCS veriﬁcation functions described in PKCS7 Verify Protocol .
29. If a platform includes an I/O subsystem that utilizes SD or eMMC command packets, then the
EFI_SD_MMC_PASS_THRU_PROTOCOL must be implemented.
30. If a platform includes the ability to create/destroy a speciﬁed RAM disk, the EFI_RAM_DISK_PROTOCOL
must be implemented and only one instance of this protocol exists.
31. If a platform includes a mass storage device which supports hardware-based erase on a speciﬁed range, then
EFI_ERASE_BLOCK_PROTOCOL must be implemented.
32. If a platform includes the ability to register for notiﬁcations when a call to ResetSystem is called, then the
EFI_RESET_NOTIFICATION_PROTOCOL must be implemented.
33. If a platform includes UFS devices, the EFI UFS Device Conﬁg Protocol must be implemented.
34. If a platform cannot support calls deﬁned in EFI_RUNTIME_SERVICES after ExitBootServices() is called, that
platform is permitted to provide implementations of those runtime services that return EFI_UNSUPPORTED
when invoked at runtime. On such systems, an EFI_RT_PROPERTIES_TABLE conﬁguration table should be
published describing which runtime services are supported at runtime.
35. If a platform includes support for CXL devices with coherent memory, then the platform must support extracting
the Coherent Device Attribute Table (CDAT) from the device, using either the CXL Data Object Exchange ser-
2.6. Requirements 64Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
vices (as deﬁned in the CXL 2.0 Speciﬁcation) or the EFI_ADAPTER_INFORMATION_PROTOCOL instance
(with EFI_ADAPTER_INFO_CDAT_TYPE_GUID type) installed on that device.
Note :Some of the required protocol instances are created by the corresponding Service Binding Protocol. For ex-
ample , EFI_IP4_PROTOCOL is created by EFI_IP4_SERVICE_BINDING_PROTOCOL. Please refer to the corre-
sponding sections of Service Binding Protocol for the details .
2.6.3 Driver-Speciﬁc Elements
There are a number of UEFI elements that can be added or removed depending on the features that a speciﬁc driver
requires. Drivers can be implemented by platform ﬁrmware developers to support buses and devices in a speciﬁc
platform. Drivers can also be implemented by add-in card vendors for devices that might be integrated into the
platform hardware or added to a platform through an expansion slot.
The following list includes possible driver features, and the UEFI elements that are required for each feature type:
1. If a driver follows the driver model of this speciﬁcation, the EFI Driver Binding Protocol must be implemented.
It is strongly recommended that all drivers that follow the driver model of this speciﬁcation also implement the
EFI_COMPONENT_NAME2_PROTOCOL .
2. If a driver requires conﬁguration information, the driver must use the EFI_HII_DATABASE_PROTOCOL . A
driver should not otherwise display information to the user or request information from the user.
3. If a driver requires diagnostics, the EFI_DRIVER_DIAGNOSTICS2_PROTOCOL must be implemented. In
order to support low boot times, limit diagnostics during normal boots. Time consuming diagnostics should be
deferred until the EFI_DRIVER_DIAGNOSTICS2_PROTOCOL is invoked.

4. If a bus supports devices that are able to provide containers for drivers (e.g. option ROMs), then the bus driver
for that bus type must implement the EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL .
5. If a driver is written for a console output device, then the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL must be
6. If a driver is written for a graphical console output device, then the EFI_GRAPHICS_OUTPUT_PROTOCOL ,
EFI_EDID_DISCOVERED_PROTOCOL andEFI_EDID_ACTIVE_PROTOCOL must be implemented.
7. If a driver is written for a console input device, then the EFI_SIMPLE_TEXT_INPUT_PROTOCOL and
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL must be implemented.
8. If a driver is written for a pointer device, then the EFI_SIMPLE_POINTER_PROTOCOL must be implemented.
9. If a driver is written for a network device, then the EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL ,
EFI_SIMPLE_NETWORK_PROTOCOL orEFI Managed Network Protocol must be implemented.
If VLAN is supported in hardware, then driver for the network device may implement the
EFI_VLAN_CONFIG_PROTOCOL . If a network device chooses to only produce the EFI Managed Net-
work Protocol , then the driver for the network device must implement the EFI_VLAN_CONFIG_PROTOCOL
. If a driver is written for a network device to supply wireless feature, besides above protocols,
EFI_ADAPTER_INFORMATION_PROTOCOL must be implemented. If the wireless driver does not provide
user conﬁguration capability, EFI Wireless MAC Connection II Protocol must be implemented. If the wireless
driver is written for a platform which provides a standalone wireless EAP driver, EFI_EAP_PROTOCOL must
10. If a driver is written for a disk device, then the EFI_BLOCK_IO_PROTOCOL
and the EFI_BLOCK_IO2_PROTOCOL must be implemented. In addition, the
EFI_STORAGE_SECURITY_COMMAND_PROTOCOL must be implemented for disk devices support-
ing the security commands of the SPC-4 or ATA8-ACS command set. In addition, for devices that support
incline encryption in the host storage controller, the EFI_BLOCK_IO_CRYPTO_PROTOCOL must be
supported.
2.6. Requirements 65Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11. If a driver is written for a disk device, then the EFI_BLOCK_IO_PROTOCOL
ing the security commands of the SPC-4 or ATA8-ACS command set.
12. If a driver is written for a device that is not a block oriented device but one that can provide a ﬁle system-like
interface, then the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL must be implemented.
13. If a driver is written for a PCI root bridge, then the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL and the EFI
PCI I/O Protocol must be implemented.
14. If a driver is written for an NVM Express controller, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL
15. If a driver is written for a USB host controller, then the EFI_USB2_HC_PROTOCOL and the
EFI_USB_IO_PROTOCOL must be implemented.
16. If a driver is written for a SCSI controller, then the EFI_EXT_SCSI_PASS_THRU_PROTOCOL must be imple-
mented.
17. If a driver is digitally signed, it must embed the digital signature in the PE/COFF image as described in Embed-
ded Signatures .
18. If a driver is written for a boot device that is not a block-oriented device, a ﬁle system-based device, or a console
device, then the EFI_LOAD_FILE2_PROTOCOL must be implemented.
19. If a driver follows the driver model of this speciﬁcation, and the driver wants to produce warning or error
messages for the user, then the EFI Driver Health Protocol must be used to produce those messages. The Boot
Manager may optionally display the messages to the user.
20. If a driver follows the driver model of this speciﬁcation, and the driver needs to perform a repair operation that
is not part of the normal initialization sequence, and that repair operation requires an extended period of time,
then the EFI Driver Health Protocol must be used to provide the repair feature. If the Boot Manager detects a
boot device that requires a repair operation, then the Boot Manager must use the EFI Driver Health Protocol
to perform the repair operation. The Boot Manager can optionally display progress indicators as the repair
operation is performed by the driver.
21. If a driver follows the driver model of this speciﬁcation, and the driver requires the user to make software
and/or hardware conﬁguration changes before the boot devices that the driver manages can be used, then the
EFI Driver Health Protocol must be produced. If the Boot Manager detects a boot device that requires software
and/or hardware conﬁguration changes to make the boot device usable, then the Boot Manager may optionally
allow the user to make those conﬁguration changes.
22. If a driver is written for an ATA controller, then the EFI_ATA_PASS_THRU_PROTOCOL must be implemented.
23. If a driver follows the driver model of this speciﬁcation, and the driver wants to be used with higher pri-
ority than the Bus Speciﬁc Driver Override Protocol when selecting the best driver for controller, then the
EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL must be produced on the same handle as the EFI Driver
Binding Protocol .
24. If a driver supports ﬁrmware management by an external agent or application, then the
EFI_FIRMWARE_MANAGEMENT_PROTOCOL must be used to support ﬁrmware management.
25. If a driver follows the driver model of this speciﬁcation and a driver is a device driver as deﬁned in UEFI Driver
Model , it must perform bus transactions via the bus abstraction protocol produced by a parent bus driver. Thus
a driver for a device that conforms to the PCI speciﬁcation must use EFI PCI I/O Protocol for all PCI memory
space, PCI I/O, PCI conﬁguration space, and DMA operations.
26. If a driver is written for a classic Bluetooth controller, then EFI_BLUETOOTH_HC_PROTOCOL ,
EFI_BLUETOOTH_IO_PROTOCOL and EFI_BLUETOOTH_CONFIG_PROTOCOL must be implemented,
2.6. Requirements 66Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
andEFI Bluetooth Attribute Protocol may be implemented. If a driver written for a Bluetooth Smart (Blue-
tooth Low Energy) controller, then EFI_BLUETOOTH_HC_PROTOCOL ,EFI Bluetooth Attribute Protocol and
EFI_BLUETOOTH_LE_CONFIG_PROTOCOL must be implemented. If a driver supports both Bluetooth clas-
sic and BluetoothLE, then both above requirements should be satisﬁed.
27. If a driver is written for an SD controller or eMMC controller, then the
28. If a driver is written for a UFS device, then EFI_UFS_DEVICE_CONFIG_PROTOCOL must be implemented.
2.6.4 Extensions to this Speciﬁcation Published Elsewhere
This speciﬁcation has been extended over time to include support for new devices and technologies. As the name of
the speciﬁcation implies, the original intent in its deﬁnition was to create a baseline for ﬁrmware interfaces that is
extensible without the need to include extensions in the main body of this speciﬁcation.
Readers of this speciﬁcation may ﬁnd that a feature or type of device is not treated by the speciﬁcation. This does
not necessarily mean that there is no agreed “standard” way to support the feature or device in implementations that
claim conformance to this Speciﬁcation. On occasion, it may be more appropriate for other standards organizations
to publish their own extensions that are designed to be used in concert with the deﬁnitions presented here. This may
for example allow support for new features in a more timely fashion than would be accomplished by waiting for a
revision to this speciﬁcation or perhaps that such support is deﬁned by a group with a speciﬁc expertise in the subject
area. Readers looking for means to access features or devices that are not treated in this document are therefore
recommended to inquire of appropriate standards groups to ascertain if appropriate extension publications already
exist before creating their own extensions.
By way of examples, at the time of writing the UEFI Forum is aware of a number of extension publications that are
compatible with and designed for use with this speciﬁcation. Such extensions include:
•Developers Interface Guide for Itanium® Architecture Based Servers : published and hosted by the DIG64 group
(See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ ) under the heading “Developers Interface Guide
for Itanium® Architecture Based Servers”). This document is a set of technical guidelines that deﬁne hardware,
ﬁrmware, and operating system compatibility for Itanium™-based servers;
•TCG EFI Platform Speciﬁcation : published and hosted by the Trusted Computing Group (See “Links to UEFI-
Related Documents” ( http://ueﬁ.org/ueﬁ ) under the heading “TCG EFI Platform Speciﬁcation”). This doc-
ument is about the processes that boot an EFI platform and boot an OS on that platform. Speciﬁcally, this
speciﬁcation contains the requirements for measuring boot events into TPM PCRs and adding boot event entries

into the Event Log.
•TCG EFI Protocol Speciﬁcation : published and hosted by the Trusted Computing Group (See “Links to UEFI-
Related Documents” ( http://ueﬁ.org/ueﬁ ) under the heading “TCG EFI Protocol Speciﬁcation”). This docu-
ment deﬁnes a standard interface to the TPM on an EFI platform.
Other extension documents may exist outside the view of the UEFI Forum or may have been created since the last
revision of this document.
2.6. Requirements 67Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.6.5 Cryptographic Algorithm Requirement
1. UEFI variable authentication
• For EFI_V ARIABLE_AUTHENTICATION_3 or EFI_V ARIABLE_AUTHENTICATION_2 descrip-
tor, SignedData.digestAlgorithms shall support SHA-256 (oid: 2.16.840.1.101.3.4.2.1), Signer-
Info.digestEncryptionAlgorithm be support digest encryption algorithm of RSA with PKCS #1 v1.5
padding (RSASSA_PKCS1v1_5) (oid: sha256WithRSAEncryption: 1.2.840.113549.1.1.11).
2. EAP protocol
• The cryptographic strength of EFI_EAP_TYPE_TLS shall be at least of hash strength SHA-256 and RSA
key length of at least 2048 bits.
3. TLS protocol
• The recommended TLS version is 1.2 or 1.3.
4. Secure Boot
• The platform key (PK) format shall be at least RSA-2048. The hash of the UEFI image binary in the dbx
shall be at least SHA-256.
5. Hash Protocol and Hash2 Protocol
• SHA-1 and MD5 shall only be used for backwards compatibility. For example, SHA-1 shall only be used
to support TPM1.2. MD5 shall only be used for iSCSI CHAP.
6. PKCS7 Verify Protocol.
• Digest (Hash) Algorithm shall support SHA-256 (oid: 2.16.840.1.101.3.4.2.1). Digest Encryption shall
support sha256WithRSAEncryption (oid: 1.2.840.113549.1.1.11).
2.6. Requirements 68CHAPTER
THREE
BOOT MANAGER
The UEFI boot manager is a ﬁrmware policy engine that can be conﬁgured by modifying architecturally deﬁned global
NVRAM variables. The boot manager will attempt to load UEFI drivers and UEFI applications (including UEFI OS
boot loaders) in an order deﬁned by the global NVRAM variables. The platform ﬁrmware must use the boot order
speciﬁed in the global NVRAM variables for normal boot. The platform ﬁrmware may add extra boot options or
remove invalid boot options from the boot order list.
The platform ﬁrmware may also implement value added features in the boot manager if an exceptional condition is
discovered in the ﬁrmware boot process. One example of a value added feature would be not loading a UEFI driver if
booting failed the ﬁrst time the driver was loaded. Another example would be booting to an OEM-deﬁned diagnostic
environment if a critical error was discovered in the boot process.
The boot sequence for UEFI consists of the following:
• The boot order list is read from a globally deﬁned NVRAM variable. Modiﬁcations to this variable are only
guaranteed to take effect after the next platform reset. The boot order list deﬁnes a list of NVRAM variables
that contain information about what is to be booted. Each NVRAM variable deﬁnes a name for the boot option
that can be displayed to a user.
• The variable also contains a pointer to the hardware device and to a ﬁle on that hardware device that contains
the UEFI image to be loaded.
• The variable might also contain paths to the OS partition and directory along with other conﬁguration speciﬁc
directories.
The NVRAM can also contain load options that are passed directly to the UEFI image. The platform ﬁrmware has no
knowledge of what is contained in the load options. The load options are set by higher level software when it writes
to a global NVRAM variable to set the platform ﬁrmware boot policy. This information could be used to deﬁne the
location of the OS kernel if it was different than the location of the UEFI OS loader.
3.1 Firmware Boot Manager
The boot manager is a component in ﬁrmware conforming to this speciﬁcation that determines which drivers and
applications should be explicitly loaded and when. Once compliant ﬁrmware is initialized, it passes control to the boot
manager. The boot manager is then responsible for determining what to load and any interactions with the user that
may be required to make such a decision.
The actions taken by the boot manager depend upon the system type and the policies set by the system designer.
For systems that allow the installation of new Boot Variables ( See Boot Option Recovery ), the Boot Manager must
automatically or upon the request of the loaded item, initialize at least one system console, as well as perform all
required initialization of the device indicated within the primary boot target. For such systems, the Boot Manager is
also required to honor the priorities set in BootOrder variable.
69Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
In particular, likely implementation options might include any console interface concerning boot, integrated platform
management of boot selections, and possible knowledge of other internal applications or recovery drivers that may be
integrated into the system through the boot manager.
3.1.1 Boot Manager Programming
Programmatic interaction with the boot manager is accomplished through globally deﬁned variables. On initialization
the boot manager reads the values which comprise all of the published load options among the UEFI environment
variables. By using the SetVariable() function the data that contain these environment variables can be modiﬁed.
Such modiﬁcations are guaranteed to take effect after the next system boot commences. However, boot manager
implementations may choose to improve on this guarantee and have changes take immediate effect for all subsequent
accesses to the variables that affect boot manager behavior without requiring any form of system reset.
Each load option entry resides in a Boot#### ,Driver#### ,SysPrep#### ,OsRecovery#### orPlatformRecovery####
variable where #### is replaced by a unique option number in printable hexadecimal representation using the digits
0-9, and the upper case versions of the characters A-F (0000-FFFF).
The#### must always be four digits, so small numbers must use leading zeros. The load options are then logically
ordered by an array of option numbers listed in the desired order. There are two such option ordering lists when
booting normally. The ﬁrst is DriverOrder that orders the Driver#### load option variables into their load order. The
second is BootOrder that orders the Boot#### load options variables into their load order.
For example, to add a new boot option, a new Boot#### variable would be added. Then the option number of the
new Boot#### variable would be added to the BootOrder ordered list and the BootOrder variable would be rewritten.
To change boot option on an existing Boot#### , only the Boot#### variable would need to be rewritten. A similar
operation would be done to add, remove, or modify the driver load list.
If the boot via Boot#### returns with a status of EFI_SUCCESS , platform ﬁrmware supports boot manager menu,
and if ﬁrmware is conﬁgured to boot in an interactive mode, the boot manager will stop processing the BootOrder
variable and present a boot manager menu to the user. If any of the above-mentioned conditions is not satisﬁed, the
next Boot#### in the BootOrder variable will be tried until all possibilities are exhausted. In this case, boot option
recovery must be performed ( See Boot Option Recovery ).
The boot manager may perform automatic maintenance of the database variables. For example, it may remove unref-
erenced load option variables or any load option variables that cannot be parsed, and it may rewrite any ordered list
to remove any load options that do not have corresponding load option variables. The boot manager can also, at its
own discretion, provide an administrator with the ability to invoke manual maintenance operations as well. Examples
include choosing the order of any or all load options, activating or deactivating load options, initiating OS-deﬁned or
platform-deﬁned recovery, etc. In addition, if a platform intends to create PlatformRecovery#### , before attempting to
load and execute any DriverOrder orBootOrder entries, the ﬁrmware must create any and all PlatformRecovery####
variables ( See Platform-Deﬁned Boot Option Recovery ). The ﬁrmware should not, under normal operation, automat-
ically remove any correctly formed Boot#### variable currently referenced by the BootOrder orBootNext variables.
Such removal should be limited to scenarios where the ﬁrmware is guided by direct user interaction.
The contents of PlatformRecovery#### represent the ﬁnal recovery options the ﬁrmware would have attempted had
recovery been initiated during the current boot, and need not include entries to reﬂect contingencies such as signiﬁcant
hardware reconﬁguration, or entries corresponding to speciﬁc hardware that the ﬁrmware is not yet aware of.
The behavior of the UEFI Boot Manager is impacted when Secure Boot is enabled, Firmware/OS Key Exchange:
Passing Public Keys .

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3.1.2 Load Option Processing
The boot manager is required to process the Driver load option entries before the Boot load option entries. If
theEFI_OS_INDICATIONS_START_OS_RECOVERY bit has been set in OsIndications , the ﬁrmware shall at-
tempt OS-deﬁned recovery (See OS-Deﬁned Boot Option Recovery ) rather than normal boot processing. If the
EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY bit has been set in OsIndications , the ﬁrmware shall
attempt platform-deﬁned recovery ( See Platform-Deﬁned Boot Option Recovery ) rather than normal boot processing
or handling of the EFI_OS_INDICATIONS_START_OS_RECOVERY bit. In either case, both bits should be cleared.
Otherwise, the boot manager is also required to initiate a boot of the boot option speciﬁed by the BootNext variable
as the ﬁrst boot option on the next boot, and only on the next boot. The boot manager removes the BootNext variable
before transferring control to the BootNext boot option. After the BootNext boot option is tried, the normal BootOrder
list is used. To prevent loops, the boot manager deletes BootNext before transferring control to the preselected boot
option.
If all entries of BootNext andBootOrder have been exhausted without success, or if the ﬁrmware has been instructed
to attempt boot order recovery, the ﬁrmware must attempt boot option recovery ( See Boot Option Recovery ).
The boot manager must call EFI_BOOT_SERVICES.LoadImage() which supports at least
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL and EFI_LOAD_FILE_PROTOCOL for resolving load options.
IfLoadImage() succeeds, the boot manager must enable the watchdog timer for 5 minutes by using the
EFI_BOOT_SERVICES.SetWatchdogTimer() boot service prior to calling EFI_BOOT_SERVICES.StartImage() .
If a boot option returns control to the boot manager, the boot manager must disable the watchdog timer with an
additional call to the SetWatchdogTimer() boot service.
If the boot image is not loaded via EFI_BOOT_SERVICES.LoadImage() the boot manager is required to check for
a default application to boot. Searching for a default application to boot happens on both removable and ﬁxed
media types. This search occurs when the device path of the boot image listed in any boot option points di-
rectly to an EFI_SIMPLE_FILE_SYSTEM_PROTOCOL device and does not specify the exact ﬁle to load. The
ﬁle discovery method is explained in Boot Option Recovery . The default media boot case of a protocol other than
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL is handled by the EFI_LOAD_FILE_PROTOCOL for the target device
path and does not need to be handled by the boot manager.
The UEFI boot manager must support booting from a short-form device path that starts with the ﬁrst element being a
USB WWID ( USB WWID Device Path ) or a USB Class ( USB Class Device Path ) device path. For USB WWID, the
boot manager must use the device vendor ID, device product id, and serial number, and must match any USB device
in the system that contains this information. If more than one device matches the USB WWID device path, the boot
manager will pick one arbitrarily. For USB Class, the boot manager must use the vendor ID, Product ID, Device Class,
Device Subclass, and Device Protocol, and must match any USB device in the system that contains this information.
If any of the ID, Product ID, Device Class, Device Subclass, or Device Protocol contain all F’s (0xFFFF or 0xFF), this
element is skipped for the purpose of matching. If more than one device matches the USB Class device path, the boot
manager will pick one arbitrarily.
The boot manager must also support booting from a short-form device path that starts with the ﬁrst element being a
hard drive media device path ( Hard Drive Media Device Path ). The boot manager must use the GUID or signature
and partition number in the hard drive device path to match it to a device in the system. If the drive supports the GPT
partitioning scheme the GUID in the hard drive media device path is compared with the UniquePartitionGuid ﬁeld of
the GUID Partition Entry ( GPT Partition Entry ). If the drive supports the PC-AT MBR scheme the signature in the
hard drive media device path is compared with the UniqueMBRSignature in the Legacy Master Boot Record ( Legacy
MBR ). If a signature match is made, then the partition number must also be matched. The hard drive device path
can be appended to the matching hardware device path and normal boot behavior can then be used. If more than one
device matches the hard drive device path, the boot manager will pick one arbitrarily. Thus the operating system must
ensure the uniqueness of the signatures on hard drives to guarantee deterministic boot behavior.
File Path Media Device Path ( File Path Media Device Path ). When the boot manager attempts to boot a short-form
File Path Media Device Path, it will enumerate all removable media devices, followed by all ﬁxed media devices,
3.1. Firmware Boot Manager 71Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
creating boot options for each device. The boot option FilePathList[0] is constructed by appending short-form File
Path Media Device Path to the device path of a media. The order within each group is undeﬁned. These new boot
options must not be saved to non volatile storage, and may not be added to BootOrder . The boot manager will then
attempt to boot from each boot option. If a device does not support the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL ,
but supports the EFI_BLOCK_IO_PROTOCOL protocol, then the EFI Boot Service ConnectController must be called
for this device with DriverImageHandle andRemainingDevicePath set to NULL and the Recursive ﬂag is set to TRUE .
The ﬁrmware will then attempt to boot from any child handles produced using the algorithms outlined above.
URI Device Path ( URI Device Path ). When the boot manager attempts to boot a short-form URI Device Path, it could
attempt to connect any device which will produce a device path protocol including a URI device path node until it
matches a device, or fail to match any device. The boot manager will enumerate all LoadFile protocol instances, and
invoke LoadFile protocol with FilePath set to the short-form device path during the matching process.
3.1.3 Load Options
Each load option variable contains an EFI_LOAD_OPTION descriptor that is a byte packed buffer of variable length
ﬁelds.
typedef struct _EFI_LOAD_OPTION {
UINT32 Attributes;
UINT16 FilePathListLength;
// CHAR16 Description[];
// EFI_DEVICE_PATH_PROTOCOL FilePathList[];
// UINT8 OptionalData[];
} EFI_LOAD_OPTION;
Parameters
Attributes The attributes for this load option entry. All unused bits must be zero and are reserved by the UEFI
speciﬁcation for future growth. See “Related Deﬁnitions.”
FilePathListLength Length in bytes of the FilePathList. OptionalData starts at offset sizeof(UINT32) +
sizeof(UINT16) + StrSize(Description) + FilePathListLength of the EFI_LOAD_OPTION descriptor.
Description The user readable description for the load option. This ﬁeld ends with a Null character.
FilePathList A packed array of UEFI device paths. The ﬁrst element of the array is a device path that describes the
device and location of the Image for this load option. The FilePathList[0] is speciﬁc to the device type. Other
device paths may optionally exist in the FilePathList, but their usage is OSV speciﬁc. Each element in the array
is variable length, and ends at the device path end structure. Because the size of Description is arbitrary, this
data structure is not guaranteed to be aligned on a natural boundary. This data structure may have to be copied
to an aligned natural boundary before it is used.
OptionalData The remaining bytes in the load option descriptor are a binary data buffer that is passed to the loaded
image. If the ﬁeld is zero bytes long, a NULL pointer is passed to the loaded image. The number of bytes in
OptionalData can be computed by subtracting the starting offset of OptionalData from total size in bytes of the
EFI_LOAD_OPTION.
Note: Each device path in the FilePathList can be a single instance or a multi-instance device path.
Related Deﬁnitions
//********************************************************
// Attributes
(continues on next page)
3.1. Firmware Boot Manager 72Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
(continued from previous page)
#define LOAD_OPTION_ACTIVE 0x00000001
#define LOAD_OPTION_FORCE_RECONNECT 0x00000002
#define LOAD_OPTION_HIDDEN 0x00000008
#define LOAD_OPTION_CATEGORY 0x00001F00
#define LOAD_OPTION_CATEGORY_BOOT 0x00000000
#define LOAD_OPTION_CATEGORY_APP 0x00000100
// All values 0x00000200-0x00001F00 are reserved
Description

Calling SetVariable() creates a load option. The size of the load option is the same as the size of the DataSize argument
to the SetVariable() call that created the variable. When creating a new load option, all undeﬁned attribute bits must
be written as zero. When updating a load option, all undeﬁned attribute bits must be preserved.
If a load option is marked as LOAD_OPTION_ACTIVE, the boot manager will attempt to boot automatically using
the device path information in the load option. This provides an easy way to disable or enable load options without
needing to delete and re-add them.
If any Driver#### load option is marked as LOAD_OPTION_FORCE_RECONNECT , then all of the UEFI drivers
in the system will be disconnected and reconnected after the last Driver#### load option is processed. This allows a
UEFI driver loaded with a Driver#### load option to override a UEFI driver that was loaded prior to the execution of
the UEFI Boot Manager.
The executable indicated by FilePathList[0] in Driver#### load option must be of type
EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER orEFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER
otherwise the indicated executable will not be entered for initialization.
The executable indicated by FilePathList[0] inSysPrep### ,Boot#### , orOsRecovery#### load option must be of
type EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION, otherwise the indicated executable will not be entered.
TheLOAD_OPTION_CATEGORY is a sub-ﬁeld of Attributes that provides details to the boot manager to describe how
it should group the Boot#### load options. This ﬁeld is ignored for variables of the form Driver#### ,SysPrep####,
orOsRecovery#### .
Boot#### load options with LOAD_OPTION_CATEGORY set to LOAD_OPTION_CATEGORY_BOOT are meant to
be part of the normal boot processing.
Boot#### load options with LOAD_OPTION_CATEGORY set to LOAD_OPTION_CATEGORY_APP are executables
which are not part of the normal boot processing but can be optionally chosen for execution if boot menu is provided,
or via Hot Keys. See See Launching Boot#### Load Options Using Hot Keys for details.
Boot options with reserved category values, will be ignored by the boot manager.
If any Boot#### load option is marked as LOAD_OPTION_HIDDEN , then the load option will not appear in the
menu (if any) provided by the boot manager for load option selection.
3.1. Firmware Boot Manager 73Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3.1.4 Boot Manager Capabilities
The boot manager can report its capabilities through the global variable BootOptionSupport . If the global variable is
not present, then an installer or application must act as if a value of 0 was returned.
#define EFI_BOOT_OPTION_SUPPORT_KEY 0x00000001
#define EFI_BOOT_OPTION_SUPPORT_APP 0x00000002
#define EFI_BOOT_OPTION_SUPPORT_SYSPREP 0x00000010
#define EFI_BOOT_OPTION_SUPPORT_COUNT 0x00000300
IfEFI_BOOT_OPTION_SUPPORT_KEY is set then the boot manager supports launching of Boot#### load options
using key presses. If EFI_BOOT_OPTION_SUPPORT_APP is set then the boot manager supports boot options with
LOAD_OPTION_CATEGORY_APP . IfEFI_BOOT_OPTION_SUPPORT_SYSPREP is set then the boot manager sup-
ports boot options of form SysPrep####.
The value speciﬁed in EFI_BOOT_OPTION_SUPPORT_COUNT describes the maximum number of key presses
which the boot manager supports in the EFI_KEY_OPTION .KeyData.InputKeyCount . This value is only valid if
EFI_BOOT_OPTION_SUPPORT_KEY is set. Key sequences with more keys speciﬁed are ignored.
3.1.5 Launching Boot#### Applications
The boot manager may support a separate category of Boot#### load option for applications. The boot manager
indicates that it supports this separate category by setting the EFI_BOOT_OPTION_SUPPORT_APP in the BootOp-
tionSupport global variable.
When an application’s Boot#### option is being added to the BootOrder , the installer should clear
LOAD_OPTION_ACTIVE so that the boot manager does not attempt to automatically “boot” the application. If the
boot manager indicates that it supports a separate application category, as described above, the installer should set
LOAD_OPTION_CATEGORY_APP . If not, it should set LOAD_OPTION_CATEGORY_BOOT .
3.1.6 Launching Boot#### Load Options Using Hot Keys
The boot manager may support launching a Boot#### load option using a special key press. If so, the boot manager
reports this capability by setting EFI_BOOT_OPTION_SUPPORT_KEY in the BootOptionSupport global variable.
A boot manager which supports key press launch reads the current key information from the console. Then, if there
was a key press, it compares the key returned against zero or more Key#### global variables. If it ﬁnds a match, it
veriﬁes that the Boot#### load option speciﬁed is valid and, if so, attempts to launch it immediately. The #### in
theKey#### is a printable hexadecimal number (‘0’-‘9’, ‘A’-‘F’) with leading zeroes. The order which the Key####
variables are checked is implementation-speciﬁc.
The boot manager may ignore Key#### variables where the hot keys speciﬁed overlap with those used for internal
boot manager functions. It is recommended that the boot manager delete these keys.
TheKey#### variables have the following format:
Prototype
typedef struct _EFI_KEY_OPTION {
EFI_BOOT_KEY_DATA KeyData;
UINT32 BootOptionCrc;
UINT16 BootOption;
// EFI_INPUT_KEY Keys[];
} EFI_KEY_OPTION;
3.1. Firmware Boot Manager 74Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
KeyData Speciﬁes options about how the key will be processed. Type EFI_BOOT_KEY_DATA is deﬁned in “Related
Deﬁnitions” below.
BootOptionCrc The CRC-32 which should match the CRC-32 of the entire EFI_LOAD_OPTION to which BootOp-
tion refers. If the CRC-32s do not match this value, then this key option is ignored.
BootOption The Boot#### option which will be invoked if this key is pressed and the boot option is active
(LOAD_OPTION_ACTIVE is set).
Keys The key codes to compare against those returned by the EFI_SIMPLE_TEXT_INPUT and
EFI_SIMPLE_TEXT_INPUT_EX protocols. The number of key codes (0-3) is speciﬁed by the
EFI_KEY_CODE_COUNT ﬁeld in KeyOptions.
typedef union {
struct {
UINT32 Revision : 8;
UINT32 ShiftPressed : 1;
UINT32 ControlPressed : 1;
UINT32 AltPressed : 1;
UINT32 LogoPressed : 1;
UINT32 MenuPressed : 1;
UINT32 SysReqPressed : 1;
UINT32 Reserved : 16;
UINT32 InputKeyCount : 2;
} Options;
UINT32 PackedValue;
} EFI_BOOT_KEY_DATA;
Revision Indicates the revision of the EFI_KEY_OPTION structure. This revision level should be 0.
ShiftPressed Either the left or right Shift keys must be pressed (1) or must not be pressed (0).
ControlPressed Either the left or right Control keys must be pressed (1) or must not be pressed (0).
AltPressed Either the left or right Alt keys must be pressed (1) or must not be pressed (0).
LogoPressed Either the left or right Logo keys must be pressed (1) or must not be pressed (0).
MenuPressed The Menu key must be pressed (1) or must not be pressed (0).
SysReqPressed The SysReq key must be pressed (1) or must not be pressed (0).
InputKeyCount Speciﬁes the actual number of entries in EFI_KEY_OPTION. Keys, from 0-3. If zero, then only the
shift state is considered. If more than one, then the boot option will only be launched if all of the speciﬁed keys
are pressed with the same shift state.
Example #1: ALT is the hot key. KeyData.PackedValue =0x00000400 .
Example #2: CTRL-ALT-P-R. KeyData.PackedValue =0x80000600 .
Example #3: CTRL-F1. KeyData.PackedValue =0x40000200 .
3.1. Firmware Boot Manager 75Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3.1.7 Required System Preparation Applications
A load option of the form SysPrep#### is intended to designate a UEFI application that is required to execute in order
to complete system preparation prior to processing of any Boot#### variables. The execution order of SysPrep####
applications is determined by the contents of the variable SysPrepOrder in a way directly analogous to the ordering of
Boot#### options by BootOrder .
The platform is required to examine all SysPrep#### variables referenced in SysPrepOrder . If Attributes bit
LOAD_OPTION_ACTIVE is set, and the application referenced by FilePathList[0] is present, the UEFI Applications
thus identiﬁed must be loaded and launched in the order they appear in SysPrepOrder and prior to the launch of any
load options of type Boot#### .
When launched, the platform is required to provide the application loaded by S ysPrep#### , with the same services
such as console and network as are normally provided at launch to applications referenced by a Boot#### variable.
SysPrep#### application must exit and may not call ExitBootServices() . Processing of any Error Code returned at
exit is according to system policy and does not necessarily change processing of following boot options. Any driver
portion of the feature supported by SysPrep#### boot option that is required to remain resident should be loaded by
use of Driver#### variable.

The Attributes option LOAD_OPTION_FORCE_RECONNECT is ignored for SysPrep#### variables, and in the event
that an application so launched performs some action that adds to the available hardware or drivers, the system prepa-
ration application shall itself utilize appropriate calls to ConnectController() orDisconnectController() to revise con-
nections between drivers and hardware
After all SysPrep#### variables have been launched and exited, the platform shall notify
EFI_EVENT_GROUP_READY_TO_BOOT and EFI_EVENT_GROUP_AFTER_READY_TO_BOOT event groups.
This should happen when the Boot Manager is about to load and execute Boot#### variables with Attributes set to
LOAD_OPTION_CATEGORY_BOOT according to the order deﬁned by BootOrder.
3.2 Boot Manager Policy Protocol
3.2.1 EFI_BOOT_MANAGER_POLICY_PROTOCOL
Summary
This protocol is used by EFI Applications to request the UEFI Boot Manager to connect devices using platform policy.
GUID
#define EFI_BOOT_MANAGER_POLICY_PROTOCOL_GUID \
{ 0xFEDF8E0C, 0xE147, 0x11E3,\
{ 0x99, 0x03, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } }
Protocol Interface Structure
typedef struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL
EFI_BOOT_MANAGER_POLICY_PROTOCOL;
struct \_EFI_BOOT_MANAGER_POLICY_PROTOCOL {
UINT64 Revision;
EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_PATH ConnectDevicePath;
EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS ConnectDeviceClass;
};
ConnectDevicePath Connect a Device Path following the platforms EFI Boot Manager policy.
ConnectDeviceClass Connect a class of devices, named by EFI_GUID, following the platforms UEFI Boot Manager
policy.
3.2. Boot Manager Policy Protocol 76Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The EFI_BOOT_MANAGER_POLICY_PROTOCOL is produced by the platform ﬁrmware to ex-
pose Boot Manager policy and platform speciﬁc EFI_BOOT_SERVICES.ConnectController()
EFI_BOOT_SERVICES.ConnectController() behavior.
#define EFI_BOOT_MANAGER_POLICY_PROTOCOL_REVISION 0x00010000
3.2.2 EFI_BOOT_MANAGER_POLICY_PROTOCOL.ConnectDevicePath()
Summary
Connect a device path following the platform’s EFI Boot Manager policy.
Prototype
typedef
EFI_STATUS
(EFIAPI *EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_PATH)(
IN EFI_BOOT_MANAGER_POLICY_PROTOCOL *This,
IN EFI_DEVICE_PATH *DevicePath,
IN BOOLEAN Recursive
);
This A pointer to the EFI_BOOT_MANAGER_POLICY_PROTOCOL instance. Type
EFI_BOOT_MANAGER_POLICY_PROTOCOL deﬁned above.
DevicePath Points to the start of the EFI device path to connect. If DevicePath is NULL then all the controllers in the
system will be connected using the platform’s EFI Boot Manager policy.
Recursive IfTRUE , then ConnectController() is called recursively until the entire tree of controllers below the con-
troller speciﬁed by DevicePath have been created. If FALSE , then the tree of controllers is only expanded one
level. If DevicePath is NULL then Recursive is ignored.
TheConnectDevicePath() function allows the caller to connect a DevicePath using the same policy as the EFI Boot
Manager.
IfRecursive isTRUE , then ConnectController() is called recursively until the entire tree of controllers below the
controller speciﬁed by DevicePath have been created. If Recursive isFALSE , then the tree of controllers is only
expanded one level. If DevicePath is NULL then Recursive is ignored.
Status Codes Returned
EFI_SUCCESS TheDevicePath was connected
EFI_NOT_FOUND TheDevicePath was not found
EFI_NOT_FOUND No driver was connected to DevicePath .
EFI_SECURITY_VIOLATION The user has no permission to start UEFI device drivers
EFI_UNSUPPORTED The current TPL is not TPL_APPLICATION .
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3.2.3 EFI_BOOT_MANAGER_POLICY_PROTOCOL.ConnectDeviceClass()
Summary
Connect a class of devices using the platform Boot Manager policy.
Prototype
typedef
(EFIAPI *EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS)(
IN EFI_GUID *Class
);
EFI_BOOT_MANAGER_POLICY_PROTOCOL is deﬁned above.
Class A pointer to an EFI_GUID that represents a class of devices that will be connected using the Boot Manager’s
platform policy.
TheConnectDeviceClass() function allows the caller to request that the Boot Manager connect a class of devices.
IfClass isEFI_BOOT_MANAGER_POLICY_CONSOLE_GUID then the Boot Manager will use platform policy to
connect consoles. Some platforms may restrict the number of consoles connected as they attempt to fast boot, and call-
ingConnectDeviceClass() with a Class value of EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID must connect
the set of consoles that follow the Boot Manager platform policy, and the EFI_SIMPLE_TEXT_INPUT_PROTOCOL ,
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL , and the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL are produced
on the connected handles. The Boot Manager may restrict which consoles get connect due to platform policy, for
example a security policy may require that a given console is not connected.
IfClass isEFI_BOOT_MANAGER_POLICY_NETWORK_GUID then the Boot Manager will connect the protocols
the platform supports for UEFI general purpose network applications on one or more handles. The protocols associated
with UEFI general purpose network applications are deﬁned in Platform-Speciﬁc Elements , list item number 7. If more
than one network controller is available a platform will connect, one, many, or all of the networks based on platform
policy. Connecting UEFI networking protocols, like EFI_DHCP4_PROTOCOL , does not establish connections on
the network. The UEFI general purpose network application that called ConnectDeviceClass() may need to use the
published protocols to establish the network connection. The Boot Manager can optionally have a policy to establish
a network connection.
IfClass isEFI_BOOT_MANAGER_POLICY_CONNECT_ALL_GUID then the Boot Manager will connect all UEFI
drivers using the UEFI Boot Service EFI_BOOT_SERVICES.ConnectController() . If the Boot Manager has policy
associated with connect all UEFI drivers this policy will be used.
A platform can also deﬁne platform speciﬁc Class values as a properly generated EFI_GUID would never conﬂict
with this speciﬁcation.
#define EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID \
{ 0xCAB0E94C, 0xE15F, 0x11E3,\
{ 0x91, 0x8D, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } }
#define EFI_BOOT_MANAGER_POLICY_NETWORK_GUID \
{ 0xD04159DC, 0xE15F, 0x11E3,\
{ 0xB2, 0x61, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } }
#define EFI_BOOT_MANAGER_POLICY_CONNECT_ALL_GUID \
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{ 0x113B2126, 0xFC8A, 0x11E3,\
{ 0xBD, 0x6C, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } }
EFI_SUCCESS At least one devices of the Class was connected.
EFI_DE ERROR Devices were not connected due to an error.
EFI_NOT_FOUND TheClass is not supported by the platform.
3.3 Globally Deﬁned Variables
This section deﬁnes a set of variables that have architecturally deﬁned meanings. In addition to the deﬁned data
content, each such variable has an architecturally deﬁned attribute that indicates when the data variable may be ac-
cessed. The variables with an attribute of NV are nonvolatile. This means that their values are persistent across resets
and power cycles. The value of any environment variable that does not have this attribute will be lost when power
is removed from the system and the state of ﬁrmware reserved memory is not otherwise preserved. The variables
with an attribute of BS are only available before EFI_BOOT_SERVICES.ExitBootServices() is called. This means that
these environment variables can only be retrieved or modiﬁed in the preboot environment. They are not visible to
an operating system. Environment variables with an attribute of RT are available before and after ExitBootServices()
is called. Environment variables of this type can be retrieved and modiﬁed in the preboot environment, and from an
operating system. The variables with an attribute of AT are variables with a time-based authenticated write access
deﬁned in Using the EFI_VARIABLE_AUTHENTICATION_3 descriptor . All architecturally deﬁned variables use the
EFI_GLOBAL_VARIABLE VendorGuid .
#define EFI_GLOBAL_VARIABLE \
{0x8BE4DF61,0x93CA,0x11d2,\
{0xAA,0x0D,0x00,0xE0,0x98,0x03,0x2B,0x8C}}
To prevent name collisions with possible future globally deﬁned variables, other internal ﬁrmware data variables that
are not deﬁned here must be saved with a unique VendorGuid other than EFI_GLOBAL_VARIABLE or any other
GUID deﬁned by the UEFI Speciﬁcation. Implementations must only permit the creation of variables with a UEFI
Speciﬁcation-deﬁned VendorGuid when these variables are documented in the UEFI Speciﬁcation.
Table 3.3: Global Variables

Variable Name Attribute Description
AuditMode BS, RT Whether the system is operating in Audit Mode (1) or not (0). All
other values are reserved. Should be treated as read-only except
when DeployedMode is 0. Always becomes read-only after Exit-
BootServices() is called.
Boot#### NV , BS, RT A boot load option. #### is a printed hex value. No 0x or h is
included in the hex value.
BootCurrent BS, RT The boot option that was selected for the current boot.
BootNext NV , BS, RT The boot option for the next boot only.
BootOrder NV , BS, RT The ordered boot option load list.
BootOptionSupport BS,RT, The types of boot options supported by the boot manager. Should
be treated as read-only.
ConIn NV , BS, RT The device path of the default input console.
ConInDev BS, RT The device path of all possible console input devices.
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Table 3.3 – continued from previous page
ConOut NV , BS, RT The device path of the default output console.
ConOutDev BS, RT The device path of all possible console output devices.
CryptoIndications NV , BS, RT Allows the OS to request the crypto algorithm to BIOS.
CryptoIndicationsSupported BS, RT Allows the ﬁrmware to indicate supported crypto algorithm to OS.
CryptoIndicationsActivated BS, RT Allows the ﬁrmware to indicate activated crypto algorithm to OS.
dbDefault BS, RT The OEM’s default secure boot signature store. Should be treated
as read-only.
dbrDefault BS, RT The OEM’s default OS Recovery signature store. Should be treated
dbtDefault BS, RT The OEM’s default secure boot timestamp signature store. Should
dbxDefault BS, RT The OEM’s default secure boot blacklist signature store. Should be
treated as read-only.
DeployedMode BS, RT Whether the system is operating in Deployed Mode (1) or not (0).
All other values are reserved. Should be treated as read-only when
its value is 1. Always becomes read-only after ExitBootServices()
is called.
devAuthBoot BS, RT Whether the platform ﬁrmware is operating in device authentication
boot mode (1) or not (0). All other values are reserved. Should be
devdbDefault BS, RT The OEM’s default device authentication signature store. Should be
Driver#### NV , BS, RT A driver load option. #### is a printed hex value.
DriverOrder NV , BS, RT The ordered driver load option list.
ErrOut NV , BS, RT The device path of the default error output device.
ErrOutDev BS, RT The device path of all possible error output devices.
HwErrRecSupport NV , BS, RT Identiﬁes the level of hardware error record persistence support
implemented by the platform. This variable is only modiﬁed by
ﬁrmware and is read-only to the OS.
KEK NV , BS, RT,AT The Key Exchange Key Signature Database.
KEKDefault BS, RT The OEM’s default Key Exchange Key Signature Database. Should
Key#### NV , BS, RT Describes hot key relationship with a Boot#### load option.
Lang NV , BS, RT The language code that the system is conﬁgured for. This value is
deprecated.
LangCodes BS, RT The language codes that the ﬁrmware supports. This value is depre-
cated.
OsIndications NV , BS, RT Allows the OS to request the ﬁrmware to enable certain features and
to take certain actions.
OsIndicationsSupported BS, RT Allows the ﬁrmware to indicate supported features and actions to
the OS.
OsRecoveryOrder BS,RT,NV ,AT OS-speciﬁed recovery options.
PK NV , BS, RT,AT The public Platform Key.
PKDefault BS, RT The OEM’s default public Platform Key. Should be treated as read-
only.
PlatformLangCodes BS, RT The language codes that the ﬁrmware supports.
PlatformLang NV , BS, RT The language code that the system is conﬁgured for.
PlatformRecovery#### BS, RT Platform-speciﬁed recovery options. These variables are only mod-
iﬁed by ﬁrmware and are read-only to the OS.
SignatureSupport BS, RT Array of GUIDs representing the type of signatures supported by
the platform ﬁrmware. Should be treated as read-only.
3.3. Globally Deﬁned Variables 80Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SecureBoot BS, RT Whether the platform ﬁrmware is operating in Secure boot mode
(1) or not (0). All other values are reserved. Should be treated as
read-only.
SetupMode BS, RT Whether the system should require authentication on SetVariable()
requests to Secure Boot policy variables (0) or not (1). Should be
treated as read-only. The system is in “Setup Mode” when Setup-
Mode==1, AuditMode==0, and DeployedMode==0.
SysPrep#### NV , BS, RT A System Prep application load option containing an
EFI_LOAD_OPTION descriptor. #### is a printed hex value.
SysPrepOrder NV , BS, RT The ordered System Prep Application load option list.
Timeout NV , BS, RT The ﬁrmware’s boot managers timeout, in seconds, before initiating
the default boot selection.
VendorKeys BS, RT Whether the system is conﬁgured to use only vendor-provided keys
or not. Should be treated as read-only.
The PlatformLangCodes variable contains a null- terminated ASCII string representing the language codes that the
ﬁrmware can support. At initialization time the ﬁrmware computes the supported languages and creates this data
variable. Since the ﬁrmware creates this value on each initialization, its contents are not stored in nonvolatile memory.
This value is considered read-only. PlatformLangCodes is speciﬁed in Native RFC 4646 format. Formats — Language
Codes and Language Code Arrays .LangCodes is deprecated and may be provided for backwards compatibility.
ThePlatformLang variable contains a null- terminated ASCII string language code that the machine has been conﬁg-
ured for. This value may be changed to any value supported by PlatformLangCodes . If this change is made in the
preboot environment, then the change will take effect immediately. If this change is made at OS runtime, then the
change does not take effect until the next boot. If the language code is set to an unsupported value, the ﬁrmware will
choose a supported default at initialization and set PlatformLang to a supported value. PlatformLang is speciﬁed in
Native RFC 4646 array format. Formats — Language Codes and Language Code Arrays .Lang is deprecated and
may be provided for backwards compatibility.
Lang has been deprecated. If the platform supports this variable, it must map any changes in the Lang variable into
PlatformLang in the appropriate format.
Langcodes has been deprecated. If the platform supports this variable, it must map any changes in the Langcodes
variable into PlatformLang in the appropriate format.
TheTimeout variable contains a binary UINT16 that supplies the number of seconds that the ﬁrmware will wait before
initiating the original default boot selection. A value of 0 indicates that the default boot selection is to be initiated
immediately on boot. If the value is not present, or contains the value of 0xFFFF then ﬁrmware will wait for user input
before booting. This means the default boot selection is not automatically started by the ﬁrmware.
The ConIn ,ConOut , and ErrOut variables each contain an EFI Device Path Protocol descriptor that deﬁnes the
default device to use on boot. Changes to these values made in the preboot environment take effect immediately.
Changes to these values at OS runtime do not take effect until the next boot. If the ﬁrmware cannot resolve the device
path, it is allowed to automatically replace the values, as needed, to provide a console for the system. If the device
path starts with a USB Class device path ( USB Class Device Path ), then any input or output device that matches the
device path must be used as a console if it is supported by the ﬁrmware.
TheConInDev ,ConOutDev , and ErrOutDev variables each contain an EFI_DEVICE_PATH_PROTOCOL descriptor
that deﬁnes all the possible default devices to use on boot. These variables are volatile, and are set dynamically on
every boot. ConIn ,ConOut , and ErrOut are always proper subsets of ConInDev ,ConOutDev , and ErrOutDev .
Each Boot#### variable contains an EFI_LOAD_OPTION . Each Boot#### variable is the name “Boot” appended with
a unique four digit hexadecimal number. For example, Boot0001, Boot0002, Boot0A02, etc.
The OsRecoveryOrder variable contains an array of EFI_GUID structures. Each EFI_GUID structure speciﬁes a
namespace for variables containing OS-deﬁned recovery entries ( See OS-Deﬁned Boot Option Recovery ). Write ac-
3.3. Globally Deﬁned Variables 81Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
cess to this variable is controlled by the security key database dbr ( Using the EFI_VARIABLE_AUTHENTICATION_3
descriptor ).
PlatformRecovery#### variables share the same structure as Boot#### variables. These variables are processed when
the system is performing recovery of boot options.
TheBootOrder variable contains an array of UINT16 ’s that make up an ordered list of the Boot#### options. The ﬁrst

element in the array is the value for the ﬁrst logical boot option, the second element is the value for the second logical
boot option, etc. The BootOrder order list is used by the ﬁrmware’s boot manager as the default boot order.
TheBootNext variable is a single UINT16 that deﬁnes the Boot#### option that is to be tried ﬁrst on the next boot.
After the BootNext boot option is tried the normal BootOrder list is used. To prevent loops, the boot manager deletes
this variable before transferring control to the preselected boot option.
TheBootCurrent variable is a single UINT16 that deﬁnes the Boot#### option that was selected on the current boot.
The platform sets this variable before signaling EFI_EVENT_GROUP_READY_TO_BOOT. This variable is not set
when attempting to launch OsRecovery### or PlatformRecovery### options.
TheBootOptionSupport variable is a UINT32 that deﬁnes the types of boot options supported by the boot manager.
The CryptoIndicationsSupported variable indicates which crypto algorithms the ﬁrmware supports. This variable is
recreated by ﬁrmware every boot, and cannot be modiﬁed by the OS (see SetVariable()Attributes usage rules once
ExitBootServices() is performed).
The CryptoIndicationsActivated variable indicates which crypto algorithms the ﬁrmware activates. This variable is
ExitBootServices() is performed). It must be a subset of CryptoIndicationsSupported.
The CryptoIndications variable is used to indicate which crypto algorithms the OS wants ﬁrmware to activate in the
next boot. It must be a subset of CryptoIndicationsSupported. The OS will supply this data with a SetVariable() call.
See Section 8.5.4 for the variable deﬁnition. Once the data is consulted by the ﬁrmware and synced to CryptoIndica-
tionsActivated, the ﬁrmware must delete this variable.
Each Driver#### variable contains an EFI_LOAD_OPTION . Each load option variable is appended with a unique
number, for example Driver0001, Driver0002, etc.
TheDriverOrder variable contains an array of UINT16 ’s that make up an ordered list of the Driver#### variable. The
ﬁrst element in the array is the value for the ﬁrst logical driver load option, the second element is the value for the
second logical driver load option, etc. The DriverOrder list is used by the ﬁrmware’s boot manager as the default load
order for UEFI drivers that it should explicitly load.
The Key#### variable associates a key press with a single boot option. Each Key#### variable is the name “Key”
appended with a unique four digit hexadecimal number. For example, Key0001, Key0002, Key00A0, etc.
TheHwErrRecSupport variable contains a binary UINT16 that supplies the level of support for Hardware Error Record
Persistence ( Hardware Error Record Persistence ) that is implemented by the platform. If the value is not present,
then the platform implements no support for Hardware Error Record Persistence. A value of zero indicates that
the platform implements no support for Hardware Error Record Persistence. A value of 1 indicates that the platform
implements Hardware Error Record Persistence as deﬁned in Hardware Error Record Persistence . Firmware initializes
this variable. All other values are reserved for future use.
TheSetupMode variable is an 8-bit unsigned integer that deﬁnes whether the system is should require authentication
(0) or not (1) on SetVariable() requests to Secure Boot Policy Variables. Secure Boot Policy Variables include:
• The global variables PK,KEK , and OsRecoveryOrder
• All variables named OsRecovery#### under all VendorGuids
• All variables with the VendorGuid EFI_IMAGE_SECURITY_DATABASE_GUID.
Secure Boot Policy Variables must be created using the EFI_VARIABLE_AUTHENTICATION_2 structure.
3.3. Globally Deﬁned Variables 82Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheAuditMode variable is an 8-bit unsigned integer that deﬁnes whether the system is currently operating in Audit
Mode.
The DeployedMode variable is an 8-bit unsigned integer that deﬁnes whether the system is currently operating in
Deployed Mode.
TheKEK variable contains the current Key Exchange Key database.
ThePKvariable contains the current Platform Key.
TheVendorKeys variable is an 8-bit unsigned integer that deﬁnes whether the Security Boot Policy Variables have been
modiﬁed by anyone other than the platform vendor or a holder of the vendor-provided keys. A value of 0 indicates that
someone other than the platform vendor or a holder of the vendor-provided keys has modiﬁed the Secure Boot Policy
Variables Otherwise, the value will be 1.
TheKEKDefault variable, if present, contains the platform-deﬁned Key Exchange Key database. This is not used at
runtime but is provided in order to allow the OS to recover the OEM’s default key setup. The contents of this variable
do not include an EFI_VARIABLE_AUTHENTICATION orEFI_VARIABLE_AUTHENTICATION2 structure.
The PKDefault variable, if present, contains the platform-deﬁned Platform Key. This is not used at runtime but is
provided in order to allow the OS to recover the OEM’s default key setup. The contents of this variable do not include
anEFI_VARIABLE_AUTHENTICATION2 structure.
ThedbDefault variable, if present, contains the platform-deﬁned secure boot signature database. This is not used at
do not include an EFI_VARIABLE_AUTHENTICATION2 structure.
ThedbrDefault variable, if present, contains the platform-deﬁned secure boot authorized recovery signature database.
This is not used at runtime but is provided in order to allow the OS to recover the OEM’s default key setup. The
contents of this variable do not include an EFI_VARIABLE_AUTHENTICATION2 structure.
ThedbtDefault variable, if present, contains the platform-deﬁned secure boot timestamp signature database. This is
not used at runtime but is provided in order to allow the OS to recover the OEM’s default key setup. The contents of
this variable do not include an EFI_VARIABLE_AUTHENTICATION2 structure.
ThedbxDefault variable, if present, contains the platform-deﬁned secure boot blacklist signature database. This is not
used at runtime but is provided in order to allow the OS to recover the OEM’s default key setup. The contents of this
variable do not include an EFI_VARIABLE_AUTHENTICATION2 structure.
The SignatureSupport variable returns an array of GUIDs, with each GUID representing a type of signature which
the platform ﬁrmware supports for images and other data. The different signature types are described in “Signature
Database”.
The SecureBoot variable is an 8-bit unsigned integer that deﬁnes whether the platform ﬁrmware is operating with
Secure Boot enabled. A value of 1 indicates that platform ﬁrmware performs driver and boot application signature
veriﬁcation as speciﬁed in UEFI Image Validation during the current boot. A value of 0 indicates that driver and boot
application signature veriﬁcation is not active during the current boot. The SecureBoot variable is initialized prior to
Secure Boot image authentication and thereafter should be treated as read-only and immutable. Its initialization value
is determined by platform policy but must be 0 if the platform is in Setup Mode or Audit Mode during its initialization.
The OsIndicationsSupported variable indicates which of the OS indication features and actions that the ﬁrmware
supports. This variable is recreated by ﬁrmware every boot, and cannot be modiﬁed by the OS (see SetVariable()
Attributes usage rules once ExitBootServices() is performed).
TheOsIndications variable is used to indicate which features the OS wants ﬁrmware to enable or which actions the OS
wants the ﬁrmware to take. The OS will supply this data with a SetVariable() call. Exchanging information between
the OS and Firmware for the variable deﬁnition.
The devAuthBoot variable is an 8-bit unsigned integer that deﬁnes whether the platform ﬁrmware is operating with
device authentication boot enabled. A value of 1 indicates that platform ﬁrmware performs device authentication as
speciﬁed in Device Authentication during the current boot. A value of 0 indicates that device authentication is not
3.3. Globally Deﬁned Variables 83Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
active during the current boot. The devAuthBoot variable is initialized prior to device authentication and thereafter
should be treated as read-only and immutable. Its initialization value is determined by platform policy.
The devdbDefault variable, if present, contains the platform-deﬁned device authentication signature database. This is
this variable do not include an EFI_V ARIABLE_AUTHENTICATION2 structure.
3.4 Boot Option Recovery

Boot option recovery consists of two independent parts, operating system-deﬁned recovery and platform-deﬁned re-
covery. OS-deﬁned recovery is an attempt to allow installed operating systems to recover any needed boot options, or
to launch full operating system recovery. Platform-deﬁned recovery includes any remedial actions performed by the
platform as a last resort when no operating system is found, such as the Default Boot Behavior ( Boot Option Variables
Default Boot Behavior ). This could include behaviors such as warranty service reconﬁguration or diagnostic options.
In the event that boot option recovery must be performed, the boot manager must ﬁrst attempt OS-deﬁned recovery,
re-attempt normal booting via Boot#### andBootOrder variables, and ﬁnally attempt platform-deﬁned recovery if no
options have succeeded.
3.4.1 OS-Deﬁned Boot Option Recovery
If the EFI_OS_INDICATIONS_START_OS_RECOVERY bit is set in OsIndications , or if processing of BootOrder
does not result in success, the platform must process OS-deﬁned recovery options. In the case where
OS-deﬁned recovery is entered due to OsIndications ,SysPrepOrder and SysPrep#### variables should not
be processed. Note that in order to avoid ambiguity in intent, this bit is ignored in OsIndications if
EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY is set.
OS-deﬁned recovery uses the OsRecoveryOrder variable, as well as variables created with vendor speciﬁc VendorGuid
values and a name following the pattern OsRecovery#### . Each of these variables must be an authenticated variable
with the EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute set.
To process these variables, the boot manager iterates over the array of EFI_GUID structures in the OsRecoveryOrder
variable, and each GUID speciﬁed is treated as a VendorGuid associated with a series of variable names. For each
GUID, the ﬁrmware attempts to load and execute, in hexadecimal sort order, every variable with that GUID and a
name following the pattern OsRecovery#### . These variables have the same format as Boot#### variables, and the
boot manager must verify that each variable it attempts to load was created with a public key that is associated with a
certiﬁcate chaining to one listed in the authorized recovery signature database dbrand not in the forbidden signature
database, or is created by a key in the Key Exchange Key database KEK or the current Platform Key PK.
If the boot manager ﬁnishes processing OsRecovery#### options without EFI_BOOT_SERVICES.ExitBootServices()
orResetSystem() having been called, it must attempt to process BootOrder a second time. If booting does not succeed
during that process, OS-deﬁned recovery has failed, and the boot manager must attempt platform-based recovery.
If, while processing OsRecovery#### variables, the boot manager encounters an entry which cannot be loaded or
executed due to a security policy violation, it must ignore that variable.
3.4. Boot Option Recovery 84Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3.4.2 Platform-Deﬁned Boot Option Recovery
If the EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY bit is set in OsIndications , or if OS-deﬁned recov-
ery has failed, the system ﬁrmware must commence with platform-speciﬁc recovery by iterating its PlatformRecov-
ery#### variables in the same manner as OsRecovery#### , but must stop processing if any entry is successful. In
the case where platform-speciﬁc recovery is entered due to OsIndications ,SysPrepOrder andSysPrep#### variables
should not be processed.
3.4.3 Boot Option Variables Default Boot Behavior
The default state of globally-deﬁned variables is ﬁrmware vendor speciﬁc. However the boot options require a standard
default behavior in the exceptional case that valid boot options are not present on a platform. The default behavior
must be invoked any time the BootOrder variable does not exist or only points to nonexistent boot options, or if no
entry in BootOrder can successfully be executed.
If system ﬁrmware supports boot option recovery as described in Boot Option Recovery , system ﬁrmware must include
aPlatformRecovery#### variable specifying a short-form File Path Media Device Path ( Load Option Processing )
containing the platform default ﬁle path for removable media ( UEFI Image Types ). It is recommended for maximal
compatibility with prior versions of this speciﬁcation that this entry be the ﬁrst such variable, though it may be at any
position within the list.
It is expected that this default boot will load an operating system or a maintenance utility. If this is an operating system
setup program it is then responsible for setting the requisite environment variables for subsequent boots. The platform
ﬁrmware may also decide to recover or set to a known set of boot options.
3.5 Boot Mechanisms
EFI can boot from a device using the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL or the
EFI_LOAD_FILE_PROTOCOL . A device that supports the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL must
materialize a ﬁle system protocol for that device to be bootable. If a device does not wish to support a complete
ﬁle system it may produce an EFI_LOAD_FILE_PROTOCOL which allows it to materialize an image directly. The
Boot Manager will attempt to boot using the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL ﬁrst. If that fails, then the
EFI_LOAD_FILE_PROTOCOL will be used.
3.5.1 Boot via the Simple File Protocol
When booting via the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL , the FilePath will start with a de-
vice path that points to the device that implements the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL or the
EFI_BLOCK_IO_PROTOCOL . The next part of the FilePath may point to the ﬁle name, including subdirectories,
which contain the bootable image. If the ﬁle name is a null device path, the ﬁle name must be generated from the rules
deﬁned below.
If the FilePathList[0] device does not support the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL , but supports the
EFI_BLOCK_IO_PROTOCOL protocol, then the EFI Boot Service EFI_BOOT_SERVICES.ConnectController() must
be called for FilePathList[0] with DriverImageHandle andRemainingDevicePath set to NULL and the Recursive ﬂag
is set to TRUE .The ﬁrmware will then attempt to boot from any child handles produced using the algorithms outlined
below.
The format of the ﬁle system speciﬁed is contained in File System Format . While the ﬁrmware must produce an
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL that understands the UEFI ﬁle system, any ﬁle system can be abstracted
with the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL interface.
3.5. Boot Mechanisms 85Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3.5.1.1 Removable Media Boot Behavior
To generate a ﬁle name when none is present in the FilePath , the ﬁrmware must append a default ﬁle name in the
form \EFIBOOTBOOT{machine type short-name}.EFI where machine type short-name deﬁnes a PE32+ image format
architecture. Each ﬁle only contains one UEFI image type, and a system may support booting from one or more images
types. UEFI Image Types lists the UEFI image types.
Table 3.4: UEFI Image Types
File Name Convention PE Executable Machine Type *
32-bit BOOTIA32.EFI 0x14c
x64 BOOTx64.EFI 0x8664
Itanium architecture BOOTIA64.EFI 0x200
AArch32 architecture BOOTARM.EFI 0x01c2
AArch64 architecture BOOTAA64.EFI 0xAA64
RISC-V 32-bit architecture BOOTRISCV32.EFI 0x5032
RISC-V 64-bit architecture BOOTRISCV64.EFI 0x5064
RISC-V 128-bit architecture BOOTRISCV128.EFI 0x5128
LoongArch32 architecture BOOTLOONGARCH32.EFI 0x6232
LoongArch64 architecture BOOTLOONGARCH64.EFI 0x6264
Note :The PE Executable machine type is contained in the machine ﬁeld of the COFF ﬁle header as deﬁned in the
Microsoft Portable Executable and Common Object File Format Speciﬁcation, Revision 6.0
Media may support multiple architectures by simply having a \EFIBOOTBOOT{machine type short-name}.EFI ﬁle
of each possible machine type.
3.5.2 Boot via the Load File Protocol
When booting via the EFI_LOAD_FILE_PROTOCOL protocol, the FilePath is a device path that points to a device
that “speaks” the EFI_LOAD_FILE_PROTOCOL . The image is loaded directly from the device that supports the
EFI_LOAD_FILE_PROTOCOL . The remainder of the FilePath will contain information that is speciﬁc to the device.
Firmware passes this device-speciﬁc data to the loaded image, but does not use it to load the image. If the remainder
of the FilePath is a null device path it is the loaded image’s responsibility to implement a policy to ﬁnd the correct
boot device.
The EFI_LOAD_FILE_PROTOCOL is used for devices that do not directly support ﬁle systems. Network devices
commonly boot in this model where the image is materialized without the need of a ﬁle system.
3.5.2.1 Network Booting
Network booting is described by the Preboot eXecution Environment (PXE) BIOS Support Speciﬁcation . PXE speciﬁes
UDP, DHCP, and TFTP network protocols that a booting platform can use to interact with an intelligent system
load server. UEFI deﬁnes special interfaces that are used to implement PXE. These interfaces are contained in the
EFI_PXE_BASE_CODE_PROTOCOL .

3.5. Boot Mechanisms 86Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3.5.2.2 Future Boot Media
Since UEFI deﬁnes an abstraction between the platform and the OS and its loader it should be possible to add new
types of boot media as technology evolves. The OS loader will not necessarily have to change to support new types of
boot. The implementation of the UEFI platform services may change, but the interface will remain constant. The OS
will require a driver to support the new type of boot media so that it can make the transition from UEFI boot services
to OS control of the boot media.
3.5. Boot Mechanisms 87CHAPTER
FOUR
EFI SYSTEM TABLE
This section describes the entry point to a UEFI image and the parameters that are passed to that entry point. There are
three types of UEFI images that can be loaded and executed by ﬁrmware conforming to this speciﬁcation. These are
UEFI applications ( UEFI Applications ), UEFI boot service drivers ( UEFI Drivers ), and UEFI runtime drivers ( UEFI
Drivers ). UEFI applications include UEFI OS loaders ( UEFI OS Loaders ). There are no differences in the entry point
for these three image types.
4.1 UEFI Image Entry Point
The most signiﬁcant parameter that is passed to an image is a pointer to the System Table (see deﬁnition immediately
below), the main entry point for a UEFI Image. The System Table contains pointers to the active console devices,
a pointer to the Boot Services Table, a pointer to the Runtime Services Table, and a pointer to the list of system
conﬁguration tables such as ACPI, SMBIOS, and the SAL System Table. This section describes the System Table in
detail.
4.1.1 EFI_IMAGE_ENTRY_POINT
Summary
This is the main entry point for a UEFI Image. This entry point is the same for UEFI applications and UEFI drivers.
Prototype
typedef
(EFIAPI *EFI_IMAGE_ENTRY_POINT) (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
);
ImageHandle The ﬁrmware allocated handle for the UEFI image.
SystemTable A pointer to the EFI System Table.
This function is the entry point to an EFI image. An EFI image is loaded and relocated in system memory by the
EFI Boot Service EFI_BOOT_SERVICES.LoadImage() . An EFI image is invoked through the EFI Boot Service
EFI_BOOT_SERVICES.StartImage() .
The ﬁrst argument is the image’s image handle. The second argument is a pointer to the image’s system table.
The system table contains the standard output and input handles, plus pointers to the EFI_BOOT_SERVICES and
88Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_RUNTIME_SERVICES tables. The service tables contain the entry points in the ﬁrmware for accessing the core
EFI system functionality. The handles in the system table are used to obtain basic access to the console. In addition,
the System Table contains pointers to other standard tables that a loaded image may use if the associated pointers are
initialized to nonzero values. Examples of such tables are ACPI, SMBIOS, SAL System Table, etc.
The ImageHandle is a ﬁrmware-allocated handle that is used to identify the image on various func-
tions. The handle also supports one or more protocols that the image can use. All images support the
EFI_LOADED_IMAGE_PROTOCOL and the EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL that returns the
source location of the image, the memory location of the image, the load options for the image, etc. The exact
EFI_LOADED_IMAGE_PROTOCOL andEFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL structures are de-
ﬁned in EFI_LOADED_IMAGE_PROTOCOL.Unload() .
If the UEFI image is a UEFI application that is not a UEFI OS loader, then the application executes and either returns
or calls the EFI Boot Services EFI_BOOT_SERVICES.Exit() . A UEFI application is always unloaded from memory
when it exits, and its return status is returned to the component that started the UEFI application.
If the UEFI image is a UEFI OS Loader, then the UEFI OS Loader executes and either returns, calls the EFI Boot
Service Exit() , or calls the EFI Boot Service EFI_BOOT_SERVICES.ExitBootServices() . If the EFI OS Loader returns
or calls Exit() , then the load of the OS has failed, and the EFI OS Loader is unloaded from memory and control is
returned to the component that attempted to boot the UEFI OS Loader. If ExitBootServices() is called, then the UEFI
OS Loader has taken control of the platform, and EFI will not regain control of the system until the platform is reset.
One method of resetting the platform is through the EFI Runtime Service ResetSystem() .
If the UEFI image is a UEFI Driver, then the UEFI driver executes and either returns or calls the Boot Service Exit() .
If the UEFI driver returns an error, then the driver is unloaded from memory. If the UEFI driver returns EFI_SUCCESS
, then it stays resident in memory. If the UEFI driver does not follow the UEFI Driver Model, then it performs any
required initialization and installs its protocol services before returning. If the driver does follow the UEFI Driver
Model, then the entry point is not allowed to touch any device hardware. Instead, the entry point is required to create
and install the EFI Driver Binding Protocol (EFI Driver Binding Protocol ) on the ImageHandle of the UEFI driver.
If this process is completed, then EFI_SUCCESS is returned. If the resources are not available to complete the UEFI
driver initialization, then EFI_OUT_OF_RESOURCES is returned.
EFI_SUCCESS The driver was initialized.
EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
4.2 EFI Table Header
The data type EFI_TABLE_HEADER is the data structure that precedes all of the standard EFI table types. It includes
a signature that is unique for each table type, a revision of the table that may be updated as extensions are added to the
EFI table types, and a 32-bit CRC so a consumer of an EFI table type can validate the contents of the EFI table.
4.2.1 EFI_TABLE_HEADER
Summary
Data structure that precedes all of the standard EFI table types.
typedef struct {
UINT64 Signature;
UINT32 Revision;
4.2. EFI Table Header 89Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT32 HeaderSize;
UINT32 CRC32;
UINT32 Reserved;
} EFI_TABLE_HEADER;
Signature A 64-bit signature that identiﬁes the type of table that follows. Unique signatures have been generated for
the EFI System Table, the EFI Boot Services Table, and the EFI Runtime Services Table.
Revision The revision of the EFI Speciﬁcation to which this table conforms. The upper 16 bits of this ﬁeld contain
the major revision value, and the lower 16 bits contain the minor revision value. The minor revision values are
binary coded decimals and are limited to the range of 00..99.
When printed or displayed UEFI spec revision is referred as (Major revision).(Minor revision upper deci-
mal).(Minor revision lower decimal) or (Major revision).(Minor revision upper decimal) in case Minor revision
lower decimal is set to 0. For example:
Speciﬁcation with the revision value ((2<<16) | (30)) would be referred as 2.3;
A speciﬁcation with the revision value ((2<<16) | (31)) would be referred as 2.3.1
HeaderSize The size, in bytes, of the entire table including the FI_TABLE_HEADER.
CRC32 The 32-bit CRC for the entire table. This value is computed by setting this ﬁeld to 0, and computing the
32-bit CRC for HeaderSize bytes.
Reserved Reserved ﬁeld that must be set to 0.
NOTE: The capabilities found in the EFI system table, runtime table and boot services table may change over time.
The ﬁrst ﬁeld in each of these tables is an EFI_TABLE_HEADER. This header’s Revision ﬁeld is incremented when
new capabilities and functions are added to the functions in the table. When checking for capabilities, code should
verify that Revision is greater than or equal to the revision level of the table at the point when the capabilities were
added to the UEFI speciﬁcation.
NOTE: Unless otherwise speciﬁed, UEFI uses a standard CCITT32 CRC algorithm with a seed polynomial value of
0x04c11db7 for its CRC calculations.
NOTE: The size of the system table, runtime services table, and boot services table may increase over time. It is very
important to always use the HeaderSize ﬁeld of the EFI_TABLE_HEADER to determine the size of these tables.
4.3 EFI System Table
UEFI uses the EFI System Table, which contains pointers to the runtime and boot services tables. The deﬁnition
for this table is shown in the following code fragments. Except for the table header, all elements in the service
tables are pointers to functions as deﬁned in Services — Boot Services andServices — Runtime Services . Prior to
a call to EFI_BOOT_SERVICES.ExitBootServices() , all of the ﬁelds of the EFI System Table are valid. After an
operating system has taken control of the platform with a call to ExitBootServices() , only the Hdr ,FirmwareVendor

,FirmwareRevision ,RuntimeServices ,NumberOfTableEntries , and ConﬁgurationTable ﬁelds are valid.
4.3. EFI System Table 90Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
4.3.1 EFI_SYSTEM_TABLE
Summary
Contains pointers to the runtime and boot services tables.
#define EFI_SYSTEM_TABLE_SIGNATURE 0x5453595320494249
#define EFI_2_100_SYSTEM_TABLE_REVISION ((2<<16) | (100))
#define EFI_2_90_SYSTEM_TABLE_REVISION ((2<<16) | (90))
#define EFI_2_80_SYSTEM_TABLE_REVISION ((2<<16) | (80))
#define EFI_2_70_SYSTEM_TABLE_REVISION ((2<<16) | (70))
#define EFI_2_60_SYSTEM_TABLE_REVISION ((2<<16) | (60))
#define EFI_2_50_SYSTEM_TABLE_REVISION ((2<<16) | (50))
#define EFI_2_40_SYSTEM_TABLE_REVISION ((2<<16) | (40))
#define EFI_2_31_SYSTEM_TABLE_REVISION ((2<<16) | (31))
#define EFI_2_30_SYSTEM_TABLE_REVISION ((2<<16) | (30))
#define EFI_2_20_SYSTEM_TABLE_REVISION ((2<<16) | (20))
#define EFI_2_10_SYSTEM_TABLE_REVISION ((2<<16) | (10))
#define EFI_2_00_SYSTEM_TABLE_REVISION ((2<<16) | (00))
#define EFI_1_10_SYSTEM_TABLE_REVISION ((1<<16) | (10))
#define EFI_1_02_SYSTEM_TABLE_REVISION ((1<<16) | (02))
#define EFI_SPECIFICATION_VERSION EFI_SYSTEM_TABLE_REVISION
#define EFI_SYSTEM_TABLE_REVISION EFI_2_100_SYSTEM_TABLE_REVISION
EFI_TABLE_HEADER Hdr;
CHAR16 *FirmwareVendor;
UINT32 FirmwareRevision;
EFI_HANDLE ConsoleInHandle;
EFI_SIMPLE_TEXT_INPUT_PROTOCOL *ConIn;
EFI_HANDLE ConsoleOutHandle;
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *ConOut;
EFI_HANDLE StandardErrorHandle;
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *StdErr;
EFI_RUNTIME_SERVICES *RuntimeServices;
EFI_BOOT_SERVICES *BootServices;
UINTN NumberOfTableEntries;
EFI_CONFIGURATION_TABLE *ConfigurationTable;
} EFI_SYSTEM_TABLE;
Hdr The table header for the EFI System Table. This header contains the EFI_SYSTEM_TABLE_SIGNATURE and
EFI_SYSTEM_TABLE_REVISION values along with the size of the EFI_SYSTEM_TABLE structure and a
32-bit CRC to verify that the contents of the EFI System Table are valid.
FirmwareVendor A pointer to a null terminated string that identiﬁes the vendor that produces the system ﬁrmware
for the platform.
FirmwareRevision A ﬁrmware vendor speciﬁc value that identiﬁes the revision of the system ﬁrmware for the plat-
form.
ConsoleInHandle The handle for the active console input device. This handle must support
EFI_SIMPLE_TEXT_INPUT_PROTOCOL and EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL . If there is
no active console, these protocols must still be present.
ConIn A pointer to the EFI_SIMPLE_TEXT_INPUT_PROTOCOL interface that is associated with ConsoleInHandle .
4.3. EFI System Table 91Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ConsoleOutHandle The handle for the active console output device. This handle must support the
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL .
If there is no active console, this protocol must still be present.
ConOut A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL interface that is associated with Console-
OutHandle .
StandardErrorHandle The handle for the active standard error console device. This handle must support the
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL. If there is no active console, this protocol must still be present.
StdErr A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL interface that is associated with StandardEr-
rorHandle .
RuntimeServices A pointer to the EFI Runtime Services Table .
BootServices A pointer to the EFI Boot Services Table. See ref: eﬁ-boot-services-table_eﬁ_system_table .
NumberOfTableEntries The number of system conﬁguration tables in the buffer ConﬁgurationTable .
ConﬁgurationTable A pointer to the system conﬁguration tables. The number of entries in the table is Num-
berOfTableEntries .
4.4 EFI Boot Services Table
UEFI uses the EFI Boot Services Table, which contains a table header and pointers to all of the boot services. The
deﬁnition for this table is shown in the following code fragments. Except for the table header, all elements in the EFI
Boot Services Tables are prototypes of function pointers to functions as deﬁned in Services — Boot Services . The
function pointers in this table are not valid after the operating system has taken control of the platform with a call to
EFI_BOOT_SERVICES.ExitBootServices() .
4.4.1 EFI_BOOT_SERVICES
Summary
Contains a table header and pointers to all of the boot services.
#define EFI_BOOT_SERVICES_SIGNATURE 0x56524553544f4f42
#define EFI_BOOT_SERVICES_REVISION EFI_SPECIFICATION_VERSION
//
// Task Priority Services
//
EFI_RAISE_TPL RaiseTPL; // EFI 1.0+
EFI_RESTORE_TPL RestoreTPL; // EFI 1.0+
//
// Memory Services
//
EFI_ALLOCATE_PAGES AllocatePages; // EFI 1.0+
EFI_FREE_PAGES FreePages; // EFI 1.0+
EFI_GET_MEMORY_MAP GetMemoryMap; // EFI 1.0+
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EFI_ALLOCATE_POOL AllocatePool; // EFI 1.0+
EFI_FREE_POOL FreePool; // EFI 1.0+
//
// Event & Timer Services
//
EFI_CREATE_EVENT CreateEvent; // EFI 1.0+
EFI_SET_TIMER SetTimer; // EFI 1.0+
EFI_WAIT_FOR_EVENT WaitForEvent; // EFI 1.0+
EFI_SIGNAL_EVENT SignalEvent; // EFI 1.0+
EFI_CLOSE_EVENT CloseEvent; // EFI 1.0+
EFI_CHECK_EVENT CheckEvent; // EFI 1.0+
//
// Protocol Handler Services
//
EFI_INSTALL_PROTOCOL_INTERFACE InstallProtocolInterface; // EFI 1.
˓→0+
EFI_REINSTALL_PROTOCOL_INTERFACE ReinstallProtocolInterface; // EFI 1.
˓→0+
EFI_UNINSTALL_PROTOCOL_INTERFACE UninstallProtocolInterface; // EFI 1.
˓→0+
EFI_HANDLE_PROTOCOL HandleProtocol; // EFI 1.
˓→0+
VOID*Reserved; // EFI 1.0+
EFI_REGISTER_PROTOCOL_NOTIFY RegisterProtocolNotify; // EFI 1.
˓→0+
EFI_LOCATE_HANDLE LocateHandle; // EFI 1.
˓→0+
EFI_LOCATE_DEVICE_PATH LocateDevicePath; // EFI 1.
˓→0+
EFI_INSTALL_CONFIGURATION_TABLE InstallConfigurationTable; // EFI 1.
˓→0+
//
// Image Services
//
EFI_IMAGE_UNLOAD LoadImage; // EFI 1.0+
EFI_IMAGE_START StartImage; // EFI 1.0+
EFI_EXIT Exit; // EFI 1.0+
EFI_IMAGE_UNLOAD UnloadImage; // EFI 1.0+
EFI_EXIT_BOOT_SERVICES ExitBootServices; // EFI 1.0+
//
// Miscellaneous Services
//
EFI_GET_NEXT_MONOTONIC_COUNT GetNextMonotonicCount; // EFI 1.0+
EFI_STALL Stall; // EFI 1.0+
EFI_SET_WATCHDOG_TIMER SetWatchdogTimer; // EFI 1.0+
//
// DriverSupport Services
//
EFI_CONNECT_CONTROLLER ConnectController; // EFI 1.1
EFI_DISCONNECT_CONTROLLER DisconnectController; // EFI 1.1+
//
4.4. EFI Boot Services Table 93Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// Open andClose Protocol Services
//
EFI_OPEN_PROTOCOL OpenProtocol; // EFI 1.1+
EFI_CLOSE_PROTOCOL CloseProtocol; // EFI 1.1+
EFI_OPEN_PROTOCOL_INFORMATION OpenProtocolInformation;// EFI 1.1+
//
// Library Services
//
EFI_PROTOCOLS_PER_HANDLE ProtocolsPerHandle; // EFI 1.1+
EFI_LOCATE_HANDLE_BUFFER LocateHandleBuffer; // EFI 1.1+
EFI_LOCATE_PROTOCOL LocateProtocol; // EFI 1.1+
EFI_UNINSTALL_MULTIPLE_PROTOCOL_INTERFACES InstallMultipleProtocolInterfaces; //
˓→EFI 1.1+
EFI_UNINSTALL_MULTIPLE_PROTOCOL_INTERFACES UninstallMultipleProtocolInterfaces; //
˓→EFI 1.1+ *
//
// 32-bit CRC Services
//
EFI_CALCULATE_CRC32 CalculateCrc32; // EFI 1.1+
//
//
EFI_COPY_MEM CopyMem; // EFI 1.1+
EFI_SET_MEM SetMem; // EFI 1.1+
EFI_CREATE_EVENT_EX CreateEventEx; // UEFI 2.0+
} EFI_BOOT_SERVICES;
Hdr The table header for the EFI Boot Services Table. This header contains the
EFI_BOOT_SERVICES_SIGNATURE and EFI_BOOT_SERVICES_REVISION values along with the
size of the EFI_BOOT_SERVICES structure and a 32-bit CRC to verify that the contents of the EFI Boot
Services Table are valid.
RaiseTPL Raises the task priority level.
RestoreTPL Restores/lowers the task priority level.
AllocatePages Allocates pages of a particular type.
FreePages Frees allocated pages.
GetMemoryMap Returns the current boot services memory map and memory map key.
AllocatePool Allocates a pool of a particular type.
FreePool Frees allocated pool.
CreateEvent Creates a general-purpose event structure.
SetTimer Sets an event to be signaled at a particular time.
WaitForEvent Stops execution until an event is signaled.
SignalEvent Signals an event.
CloseEvent Closes and frees an event structure.
CheckEvent Checks whether an event is in the signaled state.
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InstallProtocolInterface Installs a protocol interface on a device handle.
ReinstallProtocolInterface Reinstalls a protocol interface on a device handle.
UninstallProtocolInterface Removes a protocol interface from a device handle.
HandleProtocol Queries a handle to determine if it supports a speciﬁed protocol.
Reserved Reserved. Must be NULL.
RegisterProtocolNotify Registers an event that is to be signaled whenever an interface is installed for a speciﬁed
protocol.
LocateHandle Returns an array of handles that support a speciﬁed protocol.

protocol.
LocateDevicePath Locates all devices on a device path that support a speciﬁed protocol and returns the handle to the
device that is closest to the path.
InstallConﬁgurationTable Adds, updates, or removes a conﬁguration table from the EFI System Table.
LoadImag Loads an EFI image into memory.
StartImage Transfers control to a loaded image’s entry point.
Exit Exits the image’s entry point.
UnloadImage Unloads an image.
ExitBootServices Terminates boot services.
GetNextMonotonicCount Returns a monotonically increasing count for the platform.
Stall Stalls the processor.
SetWatchdogTimer Resets and sets a watchdog timer used during boot services time.
ConnectController Uses a set of precedence rules to ﬁnd the best set of drivers to manage a controller.
DisconnectController Informs a set of drivers to stop managing a controller.
OpenProtocol Adds elements to the list of agents consuming a protocol interface.
CloseProtocol Removes elements from the list of agents consuming a protocol interface.
OpenProtocolInformtion Retrieve the list of agents that are currently consuming a protocol interface.
ProtocolsPerHandle Retrieves the list of protocols installed on a handle. The return buffer is automatically allocated.
LocateHandleBuffer Retrieves the list of handles from the handle database that meet the search criteria. The return
buffer is automatically allocated.
LocateProtocol Finds the ﬁrst handle in the handle database the supports the requested protocol.
InstallMultipleProtocolInterfaces Installs one or more protocol interfaces onto a handle.
UninstallMultipleProtocolInterfaces Uninstalls one or more protocol interfaces from a handle.
CalculateCrc32 Computes and returns a 32-bit CRC for a data buffer.
CopyMem Copies the contents of one buffer to another buffer.
SetMem Fills a buffer with a speciﬁed value.
CreateEventEx Creates an event structure as part of an event group.
4.4. EFI Boot Services Table 95Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
4.5 EFI Runtime Services Table
UEFI uses the EFI Runtime Services Table, which contains a table header and pointers to all of the runtime services.
The deﬁnition for this table is shown in the following code fragments. Except for the table header, all elements in
the EFI Runtime Services Tables are prototypes of function pointers to functions as deﬁned in Services — Runtime
Services . Unlike the EFI Boot Services Table, this table, and the function pointers it contains are valid after the UEFI
OS loader and OS have taken control of the platform with a call to EFI_BOOT_SERVICES.ExitBootServices() . If a
call to SetVirtualAddressMap() is made by the OS, then the function pointers in this table are ﬁxed up to point to the
new virtually mapped entry points.
4.5.1 EFI_RUNTIME_SERVICES
Summary
Contains a table header and pointers to all of the runtime services.
#define EFI_RUNTIME_SERVICES_SIGNATURE 0x56524553544e5552
#define EFI_RUNTIME_SERVICES_REVISION EFI_SPECIFICATION_VERSION
//
// Time Services
//
EFI_GET_TIME GetTime;
EFI_SET_TIME SetTime;
EFI_GET_WAKEUP_TIME GetWakeupTime;
EFI_SET_WAKEUP_TIME SetWakeupTime;
//
// Virtual Memory Services
//
EFI_SET_VIRTUAL_ADDRESS_MAP SetVirtualAddressMap;
EFI_CONVERT_POINTER ConvertPointer;
//
// Variable Services
//
EFI_GET_VARIABLE GetVariable;
EFI_GET_NEXT_VARIABLE_NAME GetNextVariableName;
EFI_SET_VARIABLE SetVariable;
//
//
EFI_GET_NEXT_HIGH_MONO_COUNT GetNextHighMonotonicCount;
EFI_RESET_SYSTEM ResetSystem;
//
// UEFI 2.0 Capsule Services
//
EFI_UPDATE_CAPSULE UpdateCapsule;
EFI_QUERY_CAPSULE_CAPABILITIES QueryCapsuleCapabilities;
4.5. EFI Runtime Services Table 96Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// Miscellaneous UEFI 2.0 Service
//
EFI_QUERY_VARIABLE_INFO QueryVariableInfo;
} EFI_RUNTIME_SERVICES;
Hdr The table header for the EFI Runtime Services Table. This header contains the
EFI_RUNTIME_SERVICES_SIGNATURE and EFI_RUNTIME_SERVICES_REVISION values along
with the size of the EFI_RUNTIME_SERVICES structure and a 32-bit CRC to verify that the contents of the
EFI Runtime Services Table are valid.
GetTime Returns the current time and date, and the time-keeping capabilities of the platform.
SetTime Sets the current local time and date information.
GetWakeupTime Returns the current wakeup alarm clock setting.
SetWakeupTime Sets the system wakeup alarm clock time.
SetVirtualAddressMap Used by a UEFI OS loader to convert from physical addressing to virtual addressing.
ConvertPointer Used by EFI components to convert internal pointers when switching to virtual addressing.
GetVariable Returns the value of a variable.
GetNextVariableName Enumerates the current variable names.
SetVariable Sets the value of a variable.
GetNextHighMonotonicCount Returns the next high 32 bits of the platform’s monotonic counter.
ResetSyste Resets the entire platform.
UpdateCapsule Passes capsules to the ﬁrmware with both virtual and physical mapping.
QueryCapsuleCapabilities nReturns if the capsule can be supported via UpdateCapsule() .
QueryVariableInfo Returns information about the EFI variable store.
4.6 EFI Conﬁguration Table & Properties Table
The EFI Conﬁguration Table is the ConﬁgurationTable ﬁeld in the EFI System Table. This table contains a set of
GUID/pointer pairs. Each element of this table is described by the EFI_CONFIGURATION_TABLE structure below.
The number of types of conﬁguration tables is expected to grow over time. This is why a GUID is used to identify the
conﬁguration table type. The EFI Conﬁguration Table may contain at most once instance of each table type.
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4.6.1 EFI_CONFIGURATION_TABLE
Summary
Contains a set of GUID/pointer pairs comprised of ConﬁgurationTable ﬁeld in the EFI System Table.
typedef struct{
EFI_GUID VendorGuid;
VOID *VendorTable;
} EFI_CONFIGURATION_TABLE;
VendorGuid The 128-bit GUID value that uniquely identiﬁes the system conﬁguration table.
VendorTable A pointer to the table associated with VendorGuid. Type of the memory that is used to store the table as
well as whether this pointer is a physical address or a virtual address during runtime (whether or not a particular
address reported in the table gets ﬁxed up when a call to SetVirtualAddressMap() is made) is determined by
the VendorGuid. Unless otherwise speciﬁed, memory type of the table buffer is deﬁned by the guidelines set
forth in the Calling Conventions section in Chapter 2. It is the responsibility of the speciﬁcation deﬁning the
VendorTable to specify additional memory type requirements (if any) and whether to convert the addresses re-
ported in the table. Any required address conversion is a responsibility of the driver that publishes corresponding
conﬁguration table.
A pointer to the table associated with VendorGuid. Whether this pointer is a physical address or a virtual ad-
dress during runtime is determined by the VendorGuid. The VendorGuid associated with a given VendorTable
pointer deﬁnes whether or not a particular address reported in the table gets ﬁxed up when a call to SetVirtual-
AddressMap() is made. It is the responsibility of the speciﬁcation deﬁning the VendorTable to specify whether
to convert the addresses reported in the table.
4.6.1.1 Industry Standard Conﬁguration Tables
The following list shows the GUIDs for tables deﬁned in some of the industry standards. These industry standards
deﬁne tables accessed as UEFI Conﬁguration Tables on UEFI-based systems. All the addresses reported in these table
entries will be referenced as physical and will not be ﬁxed up when transition from preboot to runtime phase. This list
is not exhaustive and does not show GUIDs for all possible UEFI Conﬁguration tables.
#define EFI_ACPI_20_TABLE_GUID \
{0x8868e871,0xe4f1,0x11d3,\
{0xbc,0x22,0x00,0x80,0xc7,0x3c,0x88,0x81}}
#define ACPI_TABLE_GUID \
{0xeb9d2d30,0x2d88,0x11d3,\
{0x9a,0x16,0x00,0x90,0x27,0x3f,0xc1,0x4d}}
#define SAL_SYSTEM_TABLE_GUID \
{0xeb9d2d32,0x2d88,0x11d3,\
#define SMBIOS_TABLE_GUID \
{0xeb9d2d31,0x2d88,0x11d3,\
#define SMBIOS3_TABLE_GUID \
{0xf2fd1544, 0x9794, 0x4a2c,\
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{0x99,0x2e,0xe5,0xbb,0xcf,0x20,0xe3,0x94})
#define MPS_TABLE_GUID \
{0xeb9d2d2f,0x2d88,0x11d3,\
//
// ACPI 2.0 ornewer tables should use EFI_ACPI_TABLE_GUID
//
#define EFI_ACPI_TABLE_GUID \
#define EFI_ACPI_20_TABLE_GUID EFI_ACPI_TABLE_GUID

//
//
#define ACPI_10_TABLE_GUID ACPI_TABLE_GUID *
4.6.1.2 JSON Conﬁguration Tables
The following list shows the GUIDs for tables deﬁned for reporting ﬁrmware conﬁguration data to EFI Conﬁgura-
tion Tables and also for processing JSON payload capsule as deﬁned in Section 23.5. The address reported in the
table entry identiﬁed by EFI_JSON_CAPSULE_DATA_TABLE_GUID will be referenced as physical and will not
be ﬁxed up when transition from preboot to runtime phase. The addresses reported in these table entries identiﬁed
by EFI_JSON_CONFIG_DATA_TABLE_GUID and EFI_JSON_CAPSULE_RESULT_TABLE_GUID will be refer-
enced as virtual and will be ﬁxed up when transition from preboot to runtime phase.
#define EFI_JSON_CONFIG_DATA_TABLE_GUID \
{0x87367f87, 0x1119, 0x41ce, \
{0xaa, 0xec, 0x8b, 0xe0, 0x11, 0x1f, 0x55, 0x8a }}
#define EFI_JSON_CAPSULE_DATA_TABLE_GUID \
{0x35e7a725, 0x8dd2, 0x4cac, \
{ 0x80, 0x11, 0x33, 0xcd, 0xa8, 0x10, 0x90, 0x56 }}
#define EFI_JSON_CAPSULE_RESULT_TABLE_GUID \
{0xdbc461c3, 0xb3de, 0x422a,\
{0xb9, 0xb4, 0x98, 0x86, 0xfd, 0x49, 0xa1, 0xe5 }}
4.6.1.3 Devicetree Tables
The following list shows the GUIDs for the Devicetree table (DTB). For more information, see “Links to UEFI-Related
Documents” ( http://ueﬁ.org/ueﬁ ) under the headings “Devicetree Speciﬁcation”. The DTB must be contained in
memory of type EﬁACPIReclaimMemory. The address reported in this table entry will be referenced as physical
and will not be ﬁxed up when transition from preboot to runtime phase. Firmware must have the DTB resident in
memory and installed in the EFI system table before executing any UEFI applications or drivers that are not part of
the system ﬁrmware image. Once the DTB is installed as a conﬁguration table, the system ﬁrmware must not make
any modiﬁcation to it or reference any data contained within the DTB.
UEFI applications are permitted to modify or replace the loaded DTB. System ﬁrmware must not depend on any data
contained within the DTB. If system ﬁrmware makes use of a DTB for its own conﬁguration, it should use a separate
private copy that is not installed in the EFI System Table or otherwise be exposed to EFI applications.
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//
// Devicetree table, inFlattened Devicetree Blob (DTB) format
//
#define EFI_DTB_TABLE_GUID \
{0xb1b621d5, 0xf19c, 0x41a5, \
{0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0}}
4.6.2 EFI_RT_PROPERTIES_TABLE
This table should be published by a platform if it no longer supports all EFI runtime services once ExitBootSer-
vices() has been called by the OS. Note that this is merely a hint to the OS, which it is free to ignore, and so the
platform is still required to provide callable implementations of unsupported runtime services that simply return
EFI_UNSUPPORTED.
#define EFI_RT_PROPERTIES_TABLE_GUID \\
{ 0xeb66918a, 0x7eef, 0x402a, \\
{ 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9 }}
UINT16 Version;
UINT16 Length;
UINT32 RuntimeServicesSupported;
} EFI_RT_PROPERTIES_TABLE;
Version Version of the table, must be 0x1
#define EFI_RT_PROPERTIES_TABLE_VERSION 0x1
Length Size in bytes of the entire EFI_RT_PROPERTIES_TABLE, must be 8.
RuntimeServicesSupported Bitmask of which calls are or are not supported, where a bit set to 1 indicates that the
call is supported, and 0 indicates that it is not.
#define EFI_RT_SUPPORTED_GET_TIME 0x0001
#define EFI_RT_SUPPORTED_SET_TIME 0x0002
#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004
#define EFI_RT_SUPPORTED_SET_WAKEUP_TIME 0x0008
#define EFI_RT_SUPPORTED_GET_VARIABLE 0x0010
#define EFI_RT_SUPPORTED_GET_NEXT_VARIABLE_NAME 0x0020
#define EFI_RT_SUPPORTED_SET_VARIABLE 0x0040
#define EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP 0x0080
#define EFI_RT_SUPPORTED_CONVERT_POINTER 0x0100
#define EFI_RT_SUPPORTED_GET_NEXT_HIGH_MONOTONIC_COUNT 0x0200
#define EFI_RT_SUPPORTED_RESET_SYSTEM 0x0400
#define EFI_RT_SUPPORTED_UPDATE_CAPSULE 0x0800
#define EFI_RT_SUPPORTED_QUERY_CAPSULE_CAPABILITIES 0x1000
#define EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO 0x2000
The address reported in the EFI conﬁguration table entry of this type will be referenced as physical and will not be
ﬁxed up when transitioning from preboot to runtime phase.
4.6. EFI Conﬁguration Table & Properties Table 100Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
4.6.3 EFI_PROPERTIES_TABLE (deprecated)
Note: This table is deprecated and should no longer be used! It will be removed from future versions of the speciﬁca-
tion. EFI_MEMORY_ATTRIBUTES_TABLE described below provides alternative mechanism to implement runtime
memory protection.
This table is published if the platform meets some of the construction requirements listed in the MemoryProtectionAt-
tributes .
UINT32 Version;
UINT32 Length;
UINT64 MemoryProtectionAttribute;
} EFI_PROPERTIES_TABLE;
Version This is revision of the table. Successive version may populate additional bits and growth the table length. In
the case of the latter, the Length ﬁeld will be adjusted appropriately
#define EFI_PROPERTIES_TABLE_VERSION 0x00010000
Length This is the size of the entire EFI_PROPERTIES_TABLE structure, including the version. The initial version
will be of length 16.
MemoryProtectionAttribute This ﬁeld is a bit mask. Any bits not deﬁned shall be considered reserved. A set bit
means that the underlying ﬁrmware has been constructed responsive to the given property.
//
// Memory attribute (Not defined bits are reserved)
//
#define EFI_PROPERTIES_RUNTIME_MEMORY_PROTECTION_NON_EXECUTABLE_PE_DATA 0x1
\
// BIT 0 - description - implies the runtime data isseparated from the code
This bit implies that the UEFI runtime code and data sections of the executable image are separate and must be aligned
as speciﬁed in Calling Conventions . This bit also implies that the data pages do not have any executable code.
It is recommended not to use this attribute, especially for implementations that broke the runtime code memory map
descriptors into the underlying code and data sections within UEFI modules. This splitting causes interoperability
issues with operating systems that invoke SetVirtualAddress() without realizing that there is a relationship between
these runtime descriptors.
4.6.4 EFI_MEMORY_ATTRIBUTES_TABLE
Summary
When published by the system ﬁrmware, the EFI_MEMORY_ATTRIBUTES_TABLE provides additional informa-
tion about regions within the run-time memory blocks deﬁned in the EFI_MEMORY_DESCRIPTOR entries returned
from EFI_BOOT_SERVICES . GetMemoryMap() function. The Memory Attributes Table is currently used to describe
memory protections that may be applied to the EFI Runtime code and data by an operating system or hypervisor. Con-
sumers of this table must currently ignore entries containing any values for Type except for EﬁRuntimeServicesData
andEﬁRuntimeServicesCode to ensure compatibility with future uses of this table. The Memory Attributes Table may
deﬁne multiple entries to describe sub-regions that comprise a single entry returned by GetMemoryMap() however the
sub-regions must total to completely describe the larger region and may not cross boundaries between entries reported
by GetMemoryMap() . If a run-time region returned in GetMemoryMap() entry is not described within the Memory
Attributes Table, this region is assumed to not be compatible with any memory protections.
4.6. EFI Conﬁguration Table & Properties Table 101Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Only entire EFI_MEMORY_DESCRIPTOR entries as returned by GetMemoryMap() may be passed to SetVirtualAd-
dressMap() .
ﬁxed up when transition from preboot to runtime phase.
Prototype
#define EFI_MEMORY_ATTRIBUTES_TABLE_GUID \
{0xdcfa911d, 0x26eb, 0x469f, \
{0xa2, 0x20, 0x38, 0xb7, 0xdc, 0x46, 0x12, 0x20}}
With the following data structure:
/**********************************************
/*EFI_MEMORY_ATTRIBUTES_TABLE
UINT32 Version ;
UINT32 NumberOfEntries ;
UINT32 DescriptorSize ;
UINT32 Flags ;
// EFI_MEMORY_DESCRIPTOR Entry [1] ;
} EFI_MEMORY_ATTRIBUTES_TABLE;
Version The version of this table. Present version is 0x00000002
NumberOfEntries Count of EFI_MEMORY_DESCRIPTOR entries provided. This is typically the total number of
PE/COFF sections within all UEFI modules that comprise the UEFI Runtime and all UEFI Data regions (e.g.
runtime heap).
Entry Array of Entries of type EFI_MEMORY_DESCRIPTOR.
DescriptorSize Size of the memory descriptor.
Flags Flags to provide more information for the memory attributes
#define EFI_MEMORY_ATTRIBUTES_FLAGS_RT_FORWARD_CONTROL_FLOW_GUARD 0x1
// BIT0 implies that Runtime code includes the forward control flow guard
// instruction, such asX86 CET-IBT orARM BTI.

For each array entry, the EFI_MEMORY_DESCRIPTOR . Attribute ﬁeld can inform a runtime agency, such as op-
erating system or hypervisor, as to what class of protection settings can be made in the memory management unit
for the memory deﬁned by this entry. The only valid bits for Attribute ﬁeld currently are EFI_MEMORY_RO ,
EFI_MEMORY_XP , plus EFI_MEMORY_RUNTIME . Irrespective of the memory protections implied by Attribute
, the EFI_MEMORY_DESCRIPTOR . Type ﬁeld should match the type of the memory in enclosing SetMemoryMap()
entry. PhysicalStart must be aligned as speciﬁed in Calling Conventions . The list must be sorted by physical
start address in ascending order. VirtualStart ﬁeld must be zero and ignored by the OS since it has no purpose
for this table. NumPages must cover the entire memory region for the protection mapping. Each Descriptor in the
EFI_MEMORY_ATTRIBUTES_TABLE with attribute EFI_MEMORY_RUNTIME must not overlap any other De-
scriptor in the EFI_MEMORY_ATTRIBUTES_TABLE with attribute EFI_MEMORY_RUNTIME . Additionally, ev-
ery memory region described by a Descriptor in EFI_MEMORY_ATTRIBUTES_TABLE must be a sub-region of, or
equal to, a descriptor in the table produced by GetMemoryMap().
4.6. EFI Conﬁguration Table & Properties Table 102Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 4.1: Usage of Memory Attribute Deﬁnitions
EFI_MEMORY_RO EFI_MEMORY_XP EFI _MEM-
ORY_RUNTIME
No memory access pro-
tection is possible for En-
try0 0 1
Write-protected Code 1 0 1
Read/Write Data 0 1 1
Read-only Data 1 1 1
4.6.5 EFI_CONFORMANCE_PROFILE_TABLE
Summary
This table allows the platform to advertise its UEFI speciﬁcation conformance in the form of pre-deﬁned proﬁles.
Each proﬁle is identiﬁed by a GUID, with known proﬁles listed in the Description section below.
The absence of this table shall indicate that the platform implementation is conformant with the UEFI speciﬁca-
tion requirements, as deﬁned in Section 2.6. This is equivalent to publishing this conﬁguration table with the
EFI_CONFORMANCE_PROFILES_UEFI_SPEC_GUID conformance proﬁle.
Prototype
#define EFI_CONFORMANCE_PROFILES_TABLE_GUID \
{ 0x36122546, 0xf7e7, 0x4c8f, \
{ 0xbd, 0x9b, 0xeb, 0x85, 0x25, 0xb5, 0x0c, 0x0b }}
UINT16 NumberOfProfiles;
//EFI_GUID ConformanceProfiles [];
} EFI_CONFORMANCE_PROFILES_TABLE;
Version
Version of the table, must be 0x1:
#define EFI_CONFORMANCE_PROFILES_TABLE_VERSION 0x1
NumberOfProﬁles
The number of conformance proﬁles GUIDs present in ConformanceProﬁles.
ConformanceProﬁles
An array of conformance proﬁle GUIDs that are supported by this system.
The following list shows the GUIDs of known conformance proﬁles. This list is not exhaustive and does not show
GUIDs for all possible proﬁles. Additional proﬁles can be deﬁned and published in other speciﬁcations:
#define EFI_CONFORMANCE_PROFILES_UEFI_SPEC_GUID \
{ 0x523c91af, 0xa195, 0x4382, \
{ 0x81, 0x8d, 0x29, 0x5f, 0xe4, 0x00, 0x64, 0x65 }}
4.6. EFI Conﬁguration Table & Properties Table 103Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Conformance proﬁle deﬁned by this speciﬁcation, as deﬁned in Section 2.6.
4.6.6 Other Conﬁguration Tables
The following list shows additional conﬁguration tables deﬁned in this speciﬁcation:
• EFI_MEMORY_RANGE_CAPSULE_GUID (Section 8.5.3.3)
• EFI_DEBUG_IMAGE_INFO_TABLE (Section 18.4.3)
• EFI_SYSTEM_RESOURCE_TABLE (Section 23.4)
• EFI_IMAGE_EXECUTION_INFO_TABLE (Section 32.6.3.1)
• User Information Table (Section 36.5)
• HII Database export buffer (Section 33.2.11.1)
4.7 Image Entry Point Examples
The examples in the following sections show how the various table examples are presented in the UEFI environment.
4.7.1 Image Entry Point Examples
The following example shows the image entry point for a UEFI Application. This application makes use of the EFI
System Table, the EFI Boot Services Table, and the EFI Runtime Services Table.
EFI_SYSTEM_TABLE *gST;
EFI_BOOT_SERVICES *gBS;
EFI_RUNTIME_SERVICES *gRT;
EfiApplicationEntryPoint(
)
{
EFI_STATUS Status;
EFI_TIME *Time;
gST = SystemTable;
gBS = gST->BootServices;
gRT = gST->RuntimeServices;
//
// Use EFI System Table to print "Hello World" to the active console output
// device.
//
Status = gST->ConOut->OutputString (gST->ConOut, L"Hello world \n\r");if(EFI_
˓→ERROR (Status)) {
returnStatus;
}
//
// Use EFI Boot Services Table to allocate a buffer to store the current time
4.7. Image Entry Point Examples 104Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//anddate.
//
Status = gBS->AllocatePool (
EfiBootServicesData,
sizeof (EFI_TIME),
(VOID \**)&Time
);
if(EFI_ERROR (Status)) {
}
//
// Use the EFI Runtime Services Table to get the current time anddate.
//
Status = gRT->GetTime (Time, NULL)
}
}
The following example shows the UEFI image entry point for a driver that does not follow the UEFI Driver Model .
Since this driver returns EFI_SUCCESS , it will stay resident in memory after it exits.
EfiDriverEntryPoint(
)
{
//
// Implement driver initialization here.
//
returnEFI_SUCCESS;
}
The following example shows the UEFI image entry point for a driver that also does not follow the UEFI Driver Model
. Since this driver returns EFI_DEVICE_ERROR, it will not stay resident in memory after it exits.
4.7. Image Entry Point Examples 105Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
)
{
//
//
returnEFI_DEVICE_ERROR;
}
4.7.2 UEFI Driver Model Example
The following is an UEFI Driver Model example that shows the driver initialization routine for the ABC device
controller that is on the XYZ bus. The EFI_DRIVER_BINDING_PROTOCOL and the function prototypes for Abc-
Supported(), AbcStart(), and AbcStop() are deﬁned in EFI Driver Binding Protocol This function saves the driver’s
image handle and a pointer to the EFI boot services table in global variables, so the other functions in the same driver
can have access to these values. It then creates an instance of the EFI_DRIVER_BINDING_PROTOCOL and installs
it onto the driver’s image handle.
extern EFI_GUID gEfiLoadedImageProtocolGuid;
extern EFI_GUID gEfiDriverBindingProtocolGuid;
static EFI_DRIVER_BINDING_PROTOCOL mAbcDriverBinding = {
AbcSupported,
AbcStart,
AbcStop,
1,
NULL,
NULL
};
AbcEntryPoint(
)
{
gBS = SystemTable->BootServices;
mAbcDriverBinding->ImageHandle = ImageHandle;
mAbcDriverBinding->DriverBindingHandle = ImageHandle;
Status = gBS->InstallMultipleProtocolInterfaces(
&mAbcDriverBinding->DriverBindingHandle,
&gEfiDriverBindingProtocolGuid, &mAbcDriverBinding,
NULL
);
}
4.7. Image Entry Point Examples 106Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
4.7.3 UEFI Driver Model Example (Unloadable)
The following is the same UEFI Driver Model example as above, except it also includes the code required to allow
the driver to be unloaded through the boot service Unload() EFI_LOADED_IMAGE_PROTOCOL.Unload() . Any
protocols installed or memory allocated in AbcEntryPoint() must be uninstalled or freed in the AbcUnload().
AbcStart,
AbcStop,
1,
NULL,
NULL
};
AbcUnload (
IN EFI_HANDLE ImageHandle
);
)
{
EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
Status = gBS->OpenProtocol (
ImageHandle,
&gEfiLoadedImageProtocolGuid,
&LoadedImage,
NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
}
LoadedImage->Unload = AbcUnload;
NULL
);
}

AbcStart,
AbcStop,
1,
NULL,
NULL
};
);
)
{
NULL,
);
}
NULL
);
}
4.7. Image Entry Point Examples 107Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_STATUS Status
)
{
Status = gBS->UninstallMultipleProtocolInterfaces (
NULL
);
}
4.7.4 EFI Driver Model Example (Multiple Instances)
The following is the same as the ﬁrst UEFI Driver Model example, except it produces three EFI Driver Binding
Protocol instances. The ﬁrst one is installed onto the driver’s image handle. The other two are installed onto newly
created handles.
static EFI_DRIVER_BINDING_PROTOCOL mAbcDriverBindingA = {
AbcSupportedA,
AbcStartA,
AbcStopA,
1,
NULL,
NULL
};
static EFI_DRIVER_BINDING_PROTOCOL mAbcDriverBindingB = {
AbcSupportedB,
AbcStartB,
AbcStopB,
1,
NULL,
NULL
};
static EFI_DRIVER_BINDING_PROTOCOL mAbcDriverBindingC = {
AbcSupportedC,
AbcStartC,
AbcStopC,
1,
NULL,
NULL
};
4.7. Image Entry Point Examples 108Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
)
{
//
// Install mAbcDriverBindingA onto ImageHandle
//
mAbcDriverBindingA->ImageHandle = ImageHandle;
mAbcDriverBindingA->DriverBindingHandle = ImageHandle;
&mAbcDriverBindingA->DriverBindingHandle,
&gEfiDriverBindingProtocolGuid, &mAbcDriverBindingA,
NULL
);
}
//
// Install mAbcDriverBindingB onto a newly created handle
//
mAbcDriverBindingB->ImageHandle = ImageHandle;
mAbcDriverBindingB->DriverBindingHandle = NULL;
&mAbcDriverBindingB->DriverBindingHandle,
&gEfiDriverBindingProtocolGuid, &mAbcDriverBindingB,
NULL
);
}
//
// Install mAbcDriverBindingC onto a newly created handle
//
mAbcDriverBindingC->ImageHandle = ImageHandle;
mAbcDriverBindingC->DriverBindingHandle = NULL;
&mAbcDriverBindingC->DriverBindingHandle,
&gEfiDriverBindingProtocolGuid, &mAbcDriverBindingC,
NULL
);
}
4.7. Image Entry Point Examples 109CHAPTER
FIVE
GUID PARTITION TABLE (GPT) DISK LAYOUT
5.1 GPT and MBR disk layout comparison
This speciﬁcation deﬁnes the GUID Partition table (GPT) disk layout (i.e., partitioning scheme). The following list
outlines the advantages of using the GPT disk layout over the legacy Master Boot Record (MBR) disk layout:
• Logical Block Addresses (LBAs) are 64 bits (rather than 32 bits).
• Supports many partitions (rather than just four primary partitions).
• Provides both a primary and backup partition table for redundancy.
• Uses version number and size ﬁelds for future expansion.
• Uses CRC32 ﬁelds for improved data integrity.
• Deﬁnes a GUID for uniquely identifying each partition.
• Uses a GUID and attributes to deﬁne partition content type.
• Each partition contains a 36 character human readable name.
5.2 LBA 0 Format
LBA 0 (i.e., the ﬁrst logical block) of the hard disk contains either
• a legacy Master Boot Record (MBR) ( See Legacy Master Boot Record (MBR) )
• or a protective MBR ( See Protective MBR ).
5.2.1 Legacy Master Boot Record (MBR)
A legacy MBR may be located at LBA 0 (i.e., the ﬁrst logical block) of the disk if it is not using the GPT disk layout
(i.e., if it is using the MBR disk layout). The boot code on the MBR is not executed by UEFI ﬁrmware.
Table 5.1: Legacy MBR
Mnemonic Byte Offset Byte
LengthDescription
BootCode 0 424 x86 code used on a non-UEFI system to select an MBR par-
tition record and load the ﬁrst logical block of that partition
. This code shall not be executed on UEFI systems.
110Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 5.1 – continued from previous page
UniqueMB RDiskSig-
nature440 4 Unique Disk Signature This may be used by the OS to iden-
tify the disk from other disks in the system. This value
is always written by the OS and is never written by EFI
ﬁrmware.
Unknown 444 2 Unknown. This ﬁeld shall not be used by UEFI ﬁrmware.
PartitionRecord 446 16*4 Array of four legacy MBR partition records ( See Legacy
MBR Partition Record ).
Signature 510 2 Set to 0xAA55 (i.e., byte 510 contains 0x55 and byte 5 11
contains 0xAA).
Reserved 512 Logical
BlockSize -
512The rest of the logical block, if any, is reserved.
The MBR contains four partition records (see Table 11) that each deﬁne the beginning and ending LBAs that a partition
consumes on a disk.
Table 5.2: Legacy MBR Partition Record
BootIndicator 0 1 0x80 indicates that this is the bootable legacy partition.
Other values indicate that this is not a bootable legacy par-
tition. This ﬁeld shall not be used by UEFI ﬁrmware.
StartingCHS 1 3 Start of partition in CHS address format. This ﬁeld shall
not be used by UEFI ﬁrmware.
OSType 4 1 Type of partition. See See OS Types .
EndingCHS 5 3 End of partition in CHS address format. This ﬁeld shall not
be used by UEFI ﬁrmware.
StartingLBA 8 4 Starting LBA of the partition on the disk. This ﬁeld is used
by UEFI ﬁrmware to determine the start of the partition.
SizeInLBA 12 4 Size of the partition in LBA units of logical blocks. This
ﬁeld is used by UEFI ﬁrmware to determine the size of the
partition.
If an MBR partition has an OSType ﬁeld of 0xEF (i.e., UEFI System Partition), then the ﬁrmware must add the UEFI
System Partition GUID to the handle for the MBR partition using InstallProtocolInterface() . This allows drivers and
applications, including OS loaders, to easily search for handles that represent UEFI System Partitions.
The following test must be performed to determine if a legacy MBR is valid:
• The Signature must be 0xaa55
• A Partition Record that contains an OSType value of zero or a SizeInLBA value of zero may be ignored.
Otherwise:
• The partition deﬁned by each MBR Partition Record must physically reside on the disk (i.e., not exceed the
capacity of the disk).
• Each partition must not overlap with other partitions.
Figure 5.1 (below) shows an example of an MBR disk layout with four partitions.
5.2. LBA 0 Format 111Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 5.1: MBRDisk Layout with legacy MBR example
#pragma pack(1)
///
/// MBR Partition Entry
///
UINT8 BootIndicator;
UINT8 StartHead;
UINT8 StartSector;
UINT8 StartTrack;
UINT8 OSIndicator;
UINT8 EndHead;
UINT8 EndSector;
UINT8 EndTrack;
UINT8 StartingLBA[4];
UINT8 SizeInLBA[4];
} MBR_PARTITION_RECORD;
///
/// MBR Partition Table
///
UINT8 BootStrapCode[440];
UINT8 UniqueMbrSignature[4];
UINT8 Unknown[2];
MBR_PARTITION_RECORD Partition[4];
UINT16 Signature;
} MASTER_BOOT_RECORD;
#pragma pack()
5.2.2 OS Types
Unique types deﬁned by this speciﬁcation (other values are not deﬁned by this speciﬁcation):
• 0xEF (i.e., UEFI System Partition) deﬁnes a UEFI system partition.
• 0xEE (i.e., GPT Protective) is used by a protective MBR (see 5.2.2) to deﬁne a fake partition covering the entire
disk.
Other values are used by legacy operating systems, and are allocated independently of the UEFI speciﬁcation.
NOTE: “Partition types” by Andries Brouwer: See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under
the heading “OS Type values used in the MBR disk layout” .
5.2. LBA 0 Format 112Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
5.2.3 Protective MBR
For a bootable disk, a Protective MBR must be located at LBA 0 (i.e., the ﬁrst logical block) of the disk if it is using
the GPT disk layout. The Protective MBR precedes the GUID Partition Table Header to maintain compatibility with
existing tools that do not understand GPT partition structures.
Table 5.3: Protective MBR
LengthContents
Boot Code 0 440 Unused by UEFI systems.
Unique MBR Disk
Signature440 4 Unused. Set to zero.
Unknown 444 2 Unused. Set to zero.
Partition Record 446 16*4
Array of four MBR partition records. Contains:
• one partition record as deﬁned See Table (below); and
• three partition records each set to zero.
Signature 510 2 Set to 0xAA55 (i.e., byte 510 contains 0x55 and byte 511
Block Size
- 512The rest of the logical block, if any, is reserved. Set to zero.
One of the Partition Records shall be as deﬁned in table 12, reserving the entire space on the disk after the Protective
MBR itself for the GPT disk layout.
Table 5.4: Protective MBR Partition Record protecting the entire disk*
BootIndicator 0 1 Set to 0x00 to indicate a non-bootable partition. If set to
any value other than 0x00 the behavior of this ﬂag on non-

Block Size
UEFI systems is undeﬁned. Must be ignored by UEFI i
mplementations.
StartingCHS 1 3 Set to 0x000200, corresponding to the Starting LBA ﬁeld.
OSType 4 1 Set to 0xEE (i.e., GPT Protective)
EndingCHS 5 3 Set to the CHS address of the last logical block on the disk.
Set to 0xFFFFFF if it is not possible to represent the value
in this ﬁeld.
StartingLBA 8 4 Set to 0x00000001 (i.e., the LBA of the GPT Partition
Header).
SizeInLBA 12 4 Set to the size of the disk minus one. Set to 0xFFFFFFFF
if the size of the disk is too large to be represented in this
ﬁeld.
The remaining Partition Records shall each be set to zeros.
Figure 5.2 (below) shows an example of a GPT disk layout with four partitions with a protective MBR.
Figure 5.3 (below) shows an example of a GPT disk layout with four partitions with a protective MBR, where the disk
capacity exceeds LBA 0xFFFFFFFF.
5.2. LBA 0 Format 113Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 5.2: GPT disk layout with protective MBR
Fig. 5.3: GPT disk layout with protective MBR on a diskwith capacity > LBA 0xFFFFFFFF
5.2.4 Partition Information
Install an EFI_PARTITION_INFO protocol on each of the device handles that logical EFI_BLOCK_IO_PROTOTOLs
are installed.
5.3 GUID Partition Table (GPT) Disk Layout
5.3.1 GPT overview
The GPT partitioning scheme is depicted in the Figure GUID Partition Table (GPT) example . The GPT Header ( GPT
Header ) includes a signature and a revision number that speciﬁes the format of the data bytes in the partition header.
The GUID Partition Table Header contains a header size ﬁeld that is used in calculating the CRC32 that conﬁrms the
integrity of the GPT Header. While the GPT Header’s size may increase in the future it cannot span more than one
logical block on the device.
LBA 0 (i.e., the ﬁrst logical block) contains a protective MBR ( See Protective MBR ).
Two GPT Header structures are stored on the device: the primary and the backup. The primary GPT Header must be
located in LBA 1 (i.e., the second logical block), and the backup GPT Header must be located in the last LBA of the
device. Within the GPT Header the My LBA ﬁeld contains the LBA of the GPT Header itself, and the Alternate LBA
ﬁeld contains the LBA of the other GPT Header. For example, the primary GPT Header’s My LBA value would be 1
and its Alternate LBA would be the value for the last LBA of the device. The backup GPT Header’s ﬁelds would be
reversed.
The GPT Header deﬁnes the range of LBAs that are usable by GPT Partition Entries. This range is deﬁned to be
5.3. GUID Partition Table (GPT) Disk Layout 114Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
inclusive of First Usable LBA through Last Usable LBA on the logical device. All data stored on the volume must
be stored between the First Usable LBA through Last Usable LBA , and only the data structures deﬁned by UEFI to
manage partitions may reside outside of the usable space. The value of Disk GUID is a GUID that uniquely identiﬁes
the entire GPT Header and all its associated storage. This value can be used to uniquely identify the disk. The start of
the GPT Partition Entry Array is located at the LBA indicated by the Partition Entry LBA ﬁeld. The size of a GUID
Partition Entry element is deﬁned in the Size Of Partition Entry ﬁeld. There is a 32-bit CRC of the GPT Partition Entry
Array that is stored in the GPT Header in Partition Entry Array CRC32 ﬁeld. The size of the GPT Partition Entry
Array is S ize Of Partition Entry multiplied by Number Of Partition Entries . If the size of the GUID Partition Entry
Array is not an even multiple of the logical block size, then any space left over in the last logical block is Reserved and
not covered by the Partition Entry Array CRC32 ﬁeld. When a GUID Partition Entry is updated, the Partition Entry
Array CRC32 must be updated. When the Partition Entry Array CRC32 is updated, the GPT Header CRC must also
be updated, since the Partition Entry Array CRC32 is stored in the GPT Header.
Fig. 5.4: GUID Partition Table (GPT) example
The primary GPT Partition Entry Array must be located after the primary GPT Header and end before the First Usable
LBA. The backup GPT Partition Entry Array must be located after the Last Usable LBA and end before the backup
GPT Header.
Therefore the primary and backup GPT Partition EntryArrays are stored in separate locations on the disk. Each GPT
Partition Entry deﬁnes a partition that is contained in a range that is within the usable space declared by the GPT
Header. Zero or more GPT Partition Entries may be in use in the GPT Partition Entry Array. Each deﬁned partition
must not overlap with any other deﬁned partition. If all the ﬁelds of a GUID Partition Entry are zero, the entry is not
in use. A minimum of 16,384 bytes of space must be reserved for the GPT Partition Entry Array.
If the block size is 512, the First Usable LBA must be greater than or equal to 34 (allowing 1 block for the Protective
MBR, 1 block for the Partition Table Header, and 32 blocks for the GPT Partition Entry Array); if the logical block
size is 4096, the First Useable LBA must be greater than or equal to 6 (allowing 1 block for the Protective MBR, 1
block for the GPT Header, and 4 blocks for the GPT Partition Entry Array).
The device may present a logical block size that is not 512 bytes long. In ATA, this is called the Long Logical Sector
feature set; an ATA device reports support for this feature set in IDENTIFY DEVICE data word 106 bit 12 and reports
the number of words (i.e., 2 bytes) per logical sector in IDENTIFY DEVICE data words 117-118 (see ATA8-ACS). A
SCSI device reports its logical block size in the READ CAPACITY parameter data Block Length In Bytes ﬁeld (see
SBC-3).
The device may present a logical block size that is smaller than the physical block size (e.g., present a logical block
size of 512 bytes but implement a physical block size of 4,096 bytes). In ATA, this is called the Long Physical Sector
feature set; an ATA device reports support for this feature set in IDENTIFY DEVICE data word 106 bit 13 and reports
the Physical Sector Size/Logical Sector Size exponential ratio in IDENTIFY DEVICE data word 106 bits 3-0 (See
5.3. GUID Partition Table (GPT) Disk Layout 115Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ATA8-ACS). A SCSI device reports its logical block size/physical block exponential ratio in the READ CAPACITY
(16) parameter data Logical Blocks Per Physical Block Exponent ﬁeld (see SBC-3).These ﬁelds return 2 xlogical
sectors per physical sector (e.g., 3 means 2 3=8 logical sectors per physical sector).
A device implementing long physical blocks may present logical blocks that are not aligned to the underlying phys-
ical block boundaries. An ATA device reports the alignment of logical blocks within a physical block in IDENTIFY
DEVICE data word 209 (see ATA8-ACS). A SCSI device reports its alignment in the READ CAPACITY (16) param-
eter data Lowest Aligned Logical Block Address ﬁeld (see SBC-3). Note that the ATA and SCSI ﬁelds are deﬁned
differently (e.g., to make LBA 63 aligned, ATA returns a value of 1 while SCSI returns a value of 7).
In SCSI devices, the Block Limits VPD page Optimal Transfer Length Granularity ﬁeld (see SBC-3) may also report
a granularity that is important for alignment purposes (e.g., RAID controllers may return their RAID stripe depth in
that ﬁeld)
GPT partitions should be aligned to the larger of:
a – The physical block boundary, if any
b – The optimal transfer length granularity, if any.
For example
a – If the logical block size is 512 bytes, the physical block size is 4,096 bytes (i.e., 512 bytes x 8 logical blocks), there
is no optimal transfer length granularity, and logical block 0 is aligned to a physical block boundary, then each GPT
partition should start at an LBA that is a multiple of 8.
b – If the logical block size is 512 bytes, the physical block size is 8,192 bytes (i.e., 512 bytes x 16 logical blocks), the
optimal transfer length granularity is 65,536 bytes (i.e., 512 bytes x 128 logical blocks), and logical block 0 is aligned
to a physical block boundary, then each GPT partition should start at an LBA that is a multiple of 128.
To avoid the need to determine the physical block size and the optimal transfer length granularity, software may align
GPT partitions at signiﬁcantly larger boundaries. For example, assuming logical block 0 is aligned, it may use LBAs
that are multiples of 2,048 to align to 1,048,576 byte (1 MiB) boundaries, which supports most common physical
block sizes and RAID stripe sizes.
References are as follows:
ISO/IEC 24739-200 [ANSI INCITS 452-2008] AT Attachment 8 - ATA/ATAPI Command Set (ATA8-ACS). By the
INCITS T13 technical committee. (See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ under the headings
“InterNational Committee on Information Technology Standards (INCITS)” and “INCITs T13 technical committee”).

ISO/IEC 14776-323 [T10/1799-D] SCSI Block Commands - 3 (SBC-3). Available from www.incits.org. By the
INCITS T10 technical committee (See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ under the headings
“InterNational Committee on Information Technology Standards (INCITS)” and “SCSI Block Commands”).
5.3.2 GPT Header
See Table (below) which deﬁnes the GPT Header.
Table 5.5: GPT Header
Mnemonic Byte
OffsetByte
Signature 0 8 Identiﬁes EFI-compatible partition table header. This value must con-
tain the ASCII string “EFI PART”, encoded as the 64-bit constant 0x54
52415020494645.
Revision 8 4 The revision number for this header. This revision value is not related to the
UEFI Speciﬁcation version. This header is version 1.0, so the correct value
is 0x00010000.
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Table 5.5 – continued from previous page
HeaderSize 12 4 Size in bytes of the GPT Header. The HeaderSize must be greater than or
equal to 92 and must be less than or equal to the logical block size.
HeaderCRC32 16 4 CRC32 checksum for the GPT Header structure. This value is computed by
setting this ﬁeld to 0, and computing the 32-bit CRC for HeaderSize bytes.
Reserved 20 4 Must be zero.
MyLBA 24 8 The LBA that contains this data structure.
AlternateLBA 32 8 LBA address of the alternate GPT Header.
•
FirstUsableLBA*40 8 The ﬁrst usable logical block that may be used by a partition described by a
GUID Partition Entry.
LastUsableLBA 48 8 The last usable logical block that may be used by a partition described by a
DiskGUID 56 16 GUID that can be used to uniquely identify the disk.
Par titionEn-
tryLBA72 8 The starting LBA of the GUID Partition Entry array.
NumberOfPa
rtitionEntries80 4 The number of Partition Entries in the GUID Partition Entry array.
SizeOf Partitio-
nEntry84 4 The size, in bytes, of each the GUID Partition Entry structures in the GUID
Partition Entry array. This ﬁeld shall be set to a value of 128 x 2 nwhere n
is an integer greater than or equal to zero (e.g., 128, 256, 512, etc.). NOTE:
Previous versions of this speciﬁcation allowed any multiple of 8..
PartitionE ntr-
yArrayCRC3288 4 The CRC32 of the GUID Partition Entry array. Starts at Par titionEntryLBA
and is computed over a byte length of NumberOfP artitionEntries * SizeOfP
artitionEntry.
Reserved 92 BlockSize
- 92The rest of the block is reserved by UEFI and must be zero.
The following test must be performed to determine if a GPT is valid:
• Check the Signature
• Check the Header CRC
• Check that the MyLBA entry points to the LBA that contains the GUID Partition Table
• Check the CRC of the GUID Partition Entry Array
If the GPT is the primary table, stored at LBA 1:
• Check the AlternateLBA to see if it is a valid GPT
If the primary GPT is corrupt, software must check the last LBA of the device to see if it has a valid GPT Header
and point to a valid GPT Partition Entry Array. If it points to a valid GPT Partition Entry Array, then software
should restore the primary GPT if allowed by platform policy settings (e.g. a platform may require a user to provide
conﬁrmation before restoring the table, or may allow the table to be restored automatically). Software must report
whenever it restores a GPT.
Software should ask a user for conﬁrmation before restoring the primary GPT and must report whenever it does modify
the media to restore a GPT. If a GPT formatted disk is reformatted to the legacy MBR format by legacy software, the
last logical block might not be overwritten and might still contain a stale GPT. If GPT-cognizant software then accesses
the disk and honors the stale GPT, it will misinterpret the contents of the disk. Software may detect this scenario if the
legacy MBR contains valid partitions rather than a protective MBR ( Legacy Master Boot Record (MBR) ).
Any software that updates the primary GPT must also update the backup GPT. Software may update the GPT Header
and GPT Partition Entry Array in any order, since all the CRCs are stored in the GPT Header. Software must update
5.3. GUID Partition Table (GPT) Disk Layout 117Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
the backup GPT before the primary GPT, so if the size of device has changed (e.g. volume expansion) and the update
is interrupted, the backup GPT is in the proper location on the disk
If the primary GPT is invalid, the backup GPT is used instead and it is located on the last logical block on the disk. If
the backup GPT is valid it must be used to restore the primary GPT. If the primary GPT is valid and the backup GPT
is invalid software must restore the backup GPT. If both the primary and backup GPTs are corrupted this block device
is deﬁned as not having a valid GUID Partition Header.
Both the primary and backup GPTs must be valid before an attempt is made to grow the size of a physical volume.
This is due to the GPT recovery scheme depending on locating the backup GPT at the end of the device. A volume
may grow in size when disks are added to a RAID device. As soon as the volume size is increased the backup GPT
must be moved to the end of the volume and the primary and backup GPT Headers must be updated to reﬂect the new
volume size.
5.3.3 GPT Partition Entry Array
The GPT Partition Entry Array contains an array of GPT Partition Entries. See Table (below) which deﬁnes the GPT
Partition Entry.
Table 5.6: GPT Partition Entry
PartitionTypeGUID 0 16 Unique ID that deﬁnes the purpose and type of this Parti-
tion. A value of zero deﬁnes that this partition entry is not
being used.
UniquePartitionGUID 16 16 GUID that is unique for every partition entry. Every par-
tition ever created will have a unique GUID. This GUID
must be assigned when the GPT Partition Entry is created.
The GPT Partition Entry is created whenever the Num-
berOfPa rtitionEntries in the GPT Header is increased to
include a larger range of addresses.
StartingLBA 32 8 Starting LBA of the partition deﬁned by this entry.
EndingLBA 40 8 Ending LBA of the partition deﬁned by this entry.
Attributes 48 8 Attribute bits, all bits reserved by UEFI ( Deﬁned GPT Par-
tition Entry — Partition Type GUIDs .
PartitionName 56 72 Null-terminated string containing a human-readable name
of the partition.
Reserved 128 SizeOf Par-
titionEntry
- 128The rest of the GPT Partition Entry, if any, is reserved by
UEFI and must be zero.
TheSizeOfPartitionEntry variable in the GPT Header deﬁnes the size of each GUID Partition Entry. Each partition
entry contains a Unique Partition GUID value that uniquely identiﬁes every partition that will ever be created. Any
time a new partition entry is created a new GUID must be generated for that partition, and every partition is guaranteed
to have a unique GUID. The partition is deﬁned as all the logical blocks inclusive of the StartingLBA andEndingLBA
.
The PartitionTypeGUID ﬁeld identiﬁes the contents of the partition. This GUID is similar to the OS Type ﬁeld in
the MBR. Each ﬁlesystem must publish its unique GUID. The Attributes ﬁeld can be used by utilities to make broad
inferences about the usage of a partition and is deﬁned in Table (below).
The ﬁrmware must add the PartitionTypeGuid to the handle of every active GPT partition using
EFI_BOOT_SERVICES.InstallProtocolInterface() . This will allow drivers and applications, including OS loaders,
to easily search for handles that represent EFI System Partitions or vendor speciﬁc partition types.
5.3. GUID Partition Table (GPT) Disk Layout 118Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Software that makes copies of GPT-formatted disks and partitions must generate new Disk GUID values in the GPT
Headers and new Unique Partition GUID values in each GPT Partition Entry. If GPT-cognizant software encounters
two disks or partitions with identical GUIDs, results will be indeterminate.
Table 5.7: Deﬁned GPT Partition Entry — Partition Type GUIDs
Description GUID Value
Unused Entry 00000000-0000-0000-0000-000000000000
EFI System Partition C12A7328-F81F-11D2-BA4B-00A0C93EC93B
Partition containing a legacy MBR 024DEE41-33E7-11D3-9D69-0008C781F39F
OS vendors need to generate their own Partition Type GUIDs to identify their partition types.
Table 5.8: Deﬁned GPT Partition Entry - Attributes
Bits Name Description
Bit 0 Required Partition If this bit is set, the partition is required for the platform to function. The
owner/creator of the partition indicates that deletion or modiﬁcation of the con-
tents can result in loss of platform features or failure for the platform to boot
or operate. The system cannot function normally if this partition is removed,
and it should be considered part of the hardware of the system. Actions such as
running diagnostics, system recovery, or even OS install or boot could poten-
tially stop working if this partition is removed. Unless OS software or ﬁrmware

recognizes this partition, it should never be removed or modiﬁed as the UEFI
ﬁrmware or platform hardware may become non-functional.
Bit 1 No Block IO Protocol If this bit is set, then ﬁrmware must not produce an
EFI_BLOCK_IO_PROTOCOL device for this partition. See Partition Dis-
covery for more details. By not producing an EFI_BLOCK_IO_PROTOCOL
partition, ﬁle system mappings will not be created for this partition in UEFI.
Bit 2 Legacy BIOS Bootable This bit is set aside by this speciﬁcation to let systems with traditional PC-
AT BIOS ﬁrmware implementations inform certain limited, special-purpose
software running on these systems that a GPT partition may be bootable. For
systems with ﬁrmware implementations conforming to this speciﬁcation, the
UEFI boot manager (see chapter 3) must ignore this bit when selecting a UEFI-
compliant application, e.g., an OS loader (see 2.1.3). Therefore there is no need
for this speciﬁcation to deﬁne the exact meaning of this bit.
Bits
3-47Undeﬁned and must be zero. Reserved for expansion by future versions of the
UEFI speciﬁcation.
Bits
48-63Reserved for GUID speciﬁc use. The use of these bits will vary depending on
thePartitionTypeGUID . Only the owner of the PartitionTypeGUID is allowed
to modify these bits. They must be preserved if Bits 0-47 are modiﬁed.
Related Deﬁnitions:
///
/// GPT Partition Entry.
///
EFI_GUID PartitionTypeGUID;
EFI_GUID UniquePartitionGUID;
EFI_LBA StartingLBA;
EFI_LBA EndingLBA;
UINT64 Attributes;
CHAR16 PartitionName[36];
5.3. GUID Partition Table (GPT) Disk Layout 119Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_PARTITION_ENTRY;
5.3. GUID Partition Table (GPT) Disk Layout 120CHAPTER
SIX
BLOCK TRANSLATION TABLE (BTT) LAYOUT
This speciﬁcation deﬁnes the Block Translation Table (BTT) metadata layout. The following sub-sections outline the
BTT format that is utilized on the media, the data structures involved, and a detailed description of how SW is to
interpret the BTT layout.
6.1 Block Translation Table (BTT) Background
A namespace deﬁnes a contiguously-addressed range of Non-V olatile Memory conceptually similar to a SCSI Logical
Unit (LUN) or a NVM Express® namespace. *
Note: * NVM Express® and NVMe® are registered trademarks of NVM Express, Inc. for use in describing the NVM
Express, Inc. organization and items developed by NVM Express, Inc. NVMe-oF™ is an unregistered trademark of
NVM Express, Inc.
Any namespace being utilized for block storage may contain a Block Translation Table (BTT), which is a layout and
set of rules for doing block I/O that provide powerfail write atomicity of a single block. Traditional block storage,
including hard disks and SSDs, usually protect against torn sectors, which are sectors partially written when interrupted
by power failure. Existing software, mostly ﬁle systems, depend on this behavior, often without the authors realizing it.
To enable such software to work correctly on namespaces supporting block storage access, the BTT layout deﬁned by
this document sub-divides a namespace into one or more BTT Arenas, which are large sections of the namespace that
contain the metadata required to provide the desired write atomicity. Each of these BTT Arenas contains a metadata
layout as shown in Figures 6-1 and 6-2 below.
Each arena contains the layout shown in Figure 6-1 (above), the primary info block, data area, map, ﬂog, and a backup
info block. Each of these areas is described in the following sections. When the namespace is larger than 512 GiB,
multiple arenas are required by the BTT layout, as shown in Figure 6-2 (below). Each namespace using a BTT is
divided into as many 512 GiB arenas as shall ﬁt, followed by a smaller arena to contain any remaining space as
appropriate. The smallest arena size is 16MiB so the last arena size shall be between 16MiB and 512GiBs. Any
remaining space less than 16MiB is unused. Because of these rules for arena placement, software can locate every
primary Info block and every backup Info block without reading any metadata, based solely on the namespace size.
121Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 6.1: The BTT Layout in a BTT Arena
Fig. 6.2: A BTT With Multiple Arenas in a Large Namespace
6.1. Block Translation Table (BTT) Background 122Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
6.2 Block Translation Table (BTT) Data Structures
The following sub-sections outline the data structures associated with the BTT Layout.
6.2.1 BTT Info Block
// Alignment of all BTT structures
#define EFI_BTT_ALIGNMENT 4096
#define EFI_BTT_INFO_UNUSED_LEN 3968
#define EFI_BTT_INFO_BLOCK_SIG_LEN 16
// Constants forFlags field
#define EFI_BTT_INFO_BLOCK_FLAGS_ERROR 0x00000001
// Constants forMajorandMinor version fields
#define EFI_BTT_INFO_BLOCK_MAJOR_VERSION 2
#define EFI_BTT_INFO_BLOCK_MINOR_VERSION 0
typdef struct _EFI_BTT_INFO_BLOCK {
CHAR8 Sig[EFI_BTT_INFO_BLOCK_SIG_LEN];
EFI_GUID Uuid;
EFI_GUID ParentUuid;
UINT32 Flags;
UINT16 Major;
UINT16 Minor;
UINT32 ExternalLbaSize;
UINT32 ExternalNLba;
UINT32 InternalLbaSize;
UINT32 InternalNLba;
UINT32 NFree;
UINT32 InfoSize;
UINT64 NextOff;
UINT64 DataOff;
UINT64 MapOff;
UINT64 FlogOff;
UINT64 InfoOff;
CHAR8 Unused[EFI_BTT_INFO_UNUSED_LEN];
UINT64 Checksum;
} EFI_BTT_INFO_BLOCK
SigSignature of the BTT Index Block data structure. Shall be “BTT_ARENA_INFO00”.
UUID UUID identifying this BTT instance. A new UUID is created each time the initial BTT Arenas are written.
This value shall be identical across all BTT Info Blocks within all arenas within a namespace.
ParentUuid UUID of containing namespace, used when validating the BTT Info Block to ensure this instance of the
BTT layout is intended for the current surrounding namespace, and not left over from a previous namespace
that used the same area of the media. This value shall be identical across all BTT Info Blocks within all arenas
within a namespace.
Flags Boolean attributes of this BTT Info Block. See the additional description below on the use of the ﬂags. The
following values are deﬁned:
EFI_BTT_INFO_BLOCK_FLAGS_ERROR - The BTT Arena is in the error state. When a BTT implemen-
tation discovers issues such as inconsistent metadata or lost metadata due to unrecoverable media errors, the
6.2. Block Translation Table (BTT) Data Structures 123Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
error bit for the associated arena shall be set. See the BTT Theory of Operation section regarding handling of
EFI_BTT_INFO_BLOCK_FLAGS_ERROR.
Major Major version number. Currently at version 2. This value shall be identical across all BTT Info Blocks within
all arenas within a namespace.
Minor Minor version number. Currently at version 0. This value shall be identical across all BTT Info Blocks within
ExternalLbaSize Advertised LBA size in bytes. I/O requests shall be in this size chunk. This value shall be identical
across all BTT Info Blocks within all arenas within a namespace.
ExternalNLba Advertised number of LBAs in this arena. The sum of this ﬁeld, across all BTT Arenas, is the total
number of available LBAs in the namespace.
InternalLbaSize Internal LBA size shall be greater than or equal to ExternalLbaSize and shall not be smaller than 512
bytes. Each block in the arena data area is this size in bytes and contains exactly one block of data. Optionally,
this may be larger than the ExternalLbaSize due to alignment padding between LBAs. This value shall be
identical across all BTT Info Blocks within all arenas within a namespace.
InternalNLba Number of internal blocks in the arena data area. This shall be equal to ExternalNLba + NFree
because each internal lba is either mapped to an external lba or shown as free in the ﬂog.
NFree Number of free blocks maintained for writes to this arena. NFree shall be equal to InternalNLba – Exter-
nalNLba . This value shall be identical across all BTT Info Blocks within all arenas within a namespace.
InfoSize The size of this info block in bytes. This value shall be identical across all BTT Info Blocks within all arenas
NextOff Offset of next arena, relative to the beginning of this arena. An offset of 0 indicates that no arenas follow
the current arena. This ﬁeld is provided for convience as the start of each arena can be calculated from the size
of the namespace as described in the Theory of Operation – Validating BTT Arenas at start-up description.
This value shall be identical in the primary and backup BTT Info Blocks within an arena.
DataOff Offset of the data area for this arena, relative to the beginning of this arena. The internal-LBA number zero
lives at this offset. This value shall be identical in the primary and backup BTT Info Blocks within an arena.
MapOff Offset of the map for this arena, relative to the beginning of this arena. This value shall be identical in the

primary and backup BTT Info Blocks within an arena.
FlogOff Offset of the ﬂog for this arena, relative to the beginning of this arena. This value shall be identical in the
InfoOff Offset of the backup copy of this arena’s info block, relative to the beginning of this arena. This value shall
be identical in the primary and backup BTT Info Blocks within an arena.
Reserved Shall be zero.
Checksum 64-bit Fletcher64 checksum of all ﬁelds. This ﬁeld is considered as containing zero when the checksum
is computed.
BTT Info Block Description
The existence of a valid BTT Info Block is used to determine whether a namespace is used as a BTT block device.
Each BTT Arena contains two BTT Info Blocks, a primary copy at the beginning of the BTT Arena, at address
offset 0 , and ends with an identical backup BTT Info Block, in the highest block available in the arena aligned on a
EFI_BTT_ALIGNMENT boundary. When writing the BTT layout, implementations shall write out the info blocks
from the highest arena to the lowest, writing the backup info block and other BTT data structures before writing the
primary info block. Writing the layout in this manner shall ensure that a valid BTT layout is only detected after the
entire layout has been written.
6.2. Block Translation Table (BTT) Data Structures 124Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
6.2.2 BTT Map Entry
typedef struct _EFI_BTT_MAP_ENTRY {
UINT32 PostMapLba : 30;
UINT32 Error : 1;
UINT32 Zero : 1;
} EFI_BTT_MAP_ENTRY ;
PostMapLba Post-map LBA number (block number in this arena’s data area)
Error When set and Zero is not set, reads on this block return an error. Writes to this block clear this ﬂag.
Zero When set and Error is not set, reads on this block return a full block of zeros. Writes to this block clear this
ﬂag.
BTT Map Description
The BTT Map area maps an LBA that indexes into the arena, to its actual location. The BTT Map is located as high
as possible in the arena, after room for the backup info block and ﬂog (and any required alignment) has been taken
into account. The terminology pre-map LBA andpost-map LBA is used to describe the input and output values of this
mapping.
The BTT Map area is indexed by the pre-map LBA and each entry in the map contains the 30 bit post-map LBA and
bits to indicate if there is an error or if LBA contains zeroes (see EFI_BTT_MAP_ENTRY).
TheError andZero bits indicate conditions that cannot both be true at the same time, so that combination is used to
indicate a normal map entry, where no error or zeroed block is indicated. The error condition is indicated only when
theError bit is set and the Zero bit is clear, with similar logic for the zero block condition. When neither condition
is indicated, both Error andZero are set to indicate a map entry in its normal, non-error state. This leaves the case
where both Error andZero are bits are zero, which is the initial state of all map entries when the BTT layout is
ﬁrst written. Both bits zero means that the map entry contains the initial identity mapping where the pre-map LBA is
mapped to the same post-map LBA. Deﬁning the map this way allows an implementation to leverage the case where
the initial contents of the namespace is known to be zero, requiring no writes to the map when writing the layout. This
can greatly improve the layout time since the map is the largest BTT data structure written during layout.
6.2.3 BTT Flog
// Alignment of each flog structure
#define EFI_BTT_FLOG_ENTRY_ALIGNMENT 64
typedef struct _EFI_BTT_FLOG {
UINT32 Lba0;
UINT32 OldMap0;
UINT32 NewMap0;
UINT32 Seq0;
UINT32 Lba1;
UINT32 OldMap1;
UINT32 NewMap1;
UINT32 Seq1;
} EFI_BTT_FLOG
lba0 Last pre-map LBA written using this ﬂog entry. This value is used as an index into the BTT Map when updating
it to complete the transaction.
OldMap0 Old post-map LBA. This is the old entry in the map when the last write using this ﬂog entry occurred. If
the transaction is complete, this LBA is now the free block associated with this ﬂog entry.
6.2. Block Translation Table (BTT) Data Structures 125Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NewMap0 New post-map LBA. This is the block allocated when the last write using this ﬂog entry occurred. By
deﬁnition, a write transaction is complete if the BTT Map entry contains this value.
Seq0 TheSeq0 ﬁeld in each ﬂog entry is used to determine which set of ﬁelds is newer between the two sets (Lba0,
OldMap0, NewMpa0, Seq0 vs Lba1, Oldmap1, NewMap1, Seq1). Updates to a ﬂog entry shall always be made
to the older set of ﬁelds and shall be implemented carefully so that the Seq0 bits are only written after the other
ﬁelds are known to be committed to persistence. The ﬁgure below shows the progression of the Seq0 bits over
time, where the newer entry is indicated by a value that is clockwise of the older value.
Fig. 6.3: Cyclic Sequence Numbers for Flog Entries
Lba1 Alternate lba entry
OldMap1 Alternate old entry
NewMap1 Alternate new entry
Seq1 Alternate Seq entry
BTT Flog Description
The BTT Flog is so named to illustrate that it is both a free list and a log, rolled into one data structure. The Flog size
is determined by the NFree ﬁeld in the BTT Info Block which determines how many of these ﬂog entries there are.
The ﬂog location is the highest address in the arena after space for the backup info block and alignment requirements
have been taken in account.
6.2. Block Translation Table (BTT) Data Structures 126Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
6.2.4 BTT Data Area
Starting from the low address to high, the BTT Data Area starts immediately after the BTT Info Block and extends
to the beginning of the BTT Map data structure. The number of internal data blocks that can be stored in an arena is
calculated by ﬁrst calculating the necessary space required for the BTT Info Blocks, map, and ﬂog (plus any alignment
required), subtracting that amount from the total arena size, and then calculating how many blocks ﬁt into the resulting
space.
6.2.5 NVDIMM Label Protocol Address Abstraction Guid
This version of the BTT layout and behavior is collectively described by the AddressAbstractionGuid in the UEFI
NVDIMM Label protocol section utilizing this GUID:
#define EFI_BTT_ABSTRACTION_GUID \
{0x18633bfc,0x1735,0x4217,
{0x8a,0xc9,0x17,0x23,0x92,0x82,0xd3,0xf8}
6.3 BTT Theory of Operation
This section outlines the theory of operation for the BTT and describes the responsibilities that any software imple-
mentation shall follow.
A speciﬁc instance of the BTT layout depends on the size of the namespace and three administrative choices made at
the time the initial layout is created:
•ExternalLbaSize : the desired block size
•InternalLbaSize : the block size with any internal padding
•NFree : the number of concurrent writes supported by the layout
The BTT data structures do not support an InternalLbaSize smaller than 512 bytes, so if ExternalLbaSize is smaller
than 512 bytes, the InternalLbaSize shall be rounded up to 512. For performance, the InternalLbaSize may also in-
clude some padding bytes. For example, a BTT layout supporting 520-byte blocks may use 576-byte blocks internally
in order to round up the size to a multiple of a 64-byte cache line size. In this example, the ExternalLbaSize , visible
to software above the BTT software, would be 520 bytes, but the InternalLbaSize would be 576 bytes.
Once these administrative choices above are determined, the namespace is divided up into arenas , as described in the
BTT Arenas section, where each arena uses the same values for ExternalLbaSize ,InternalLbaSize , and Nfree .
6.3.1 BTT Arenas
In order to reduce the size of BTT metadata and increase the possibility of concurrent updates, the BTT layout in
a namespace is divided into arenas . An arena cannot be larger than 512GiB or smaller than 16MiB. A namespace
is divided into as many 512GiB arenas that shall ﬁt, starting from offset zero and packed together without padding,
followed by one arena smaller than 512GiB if the remaining space is at least 16MiB. The smaller area size is rounded
down to be a multiple of EFI_BTT_ALIGNMENT if necessary. Because of these rules, the location and size of every
BTT Arena in a namespace can be determined from the namespace size.
Within an arena, the amount of space used for the Flog is NFree times the amount of space required for each Flog
entry. Flog entries shall be aligned on 64-byte boundaries. In addition, the full BTT Flog table shall be aligned on
a EFI_BTT_ALIGNMENT boundary and have a size that is padded to be multiple of EFI_BTT_ALIGNMENT. In
summary, the space in an arena taken by the Flog is:
6.3. BTT Theory of Operation 127Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
FlogSize = roundup(NFree *roundup(sizeof(EFI_BTT_FLOG),
EFI_BTT_FLOG_ENTRY_ALIGNMENT), EFI_BTT_ALIGNMENT)
Within an arena, the amount of space available for data blocks and the associated Map is the arena size minus the

space used for the BTT Info Blocks and the Flog:
DataAndMapSize = ArenaSize - 2 *sizeof(EFI_BTT_INFO_BLOCK) - FlogSize
Within an arena, the number of data blocks is calculated by dividing the available space, DataAndMapSize, by the
InternalLbaSize plus the map overhead required for each block, and rounding down the result to ensure the data area
is aligned on a EFI_BTT_ALIGNMENT boundary:
InternalNLba = (DataAndMapSize - EFI_BTT_ALIGNMENT) / (InternalLbaSize +
sizeof(EFI_BTT_MAP_ENTRY)
With the InternalNLba value known, the calculation for the number of external LBAs subtracts off NFree for the pool
of unadvertised free blocks:
ExternalNLba = InternalNLba - Nfree
Within an arena, the number of bytes required for the BTT Map is one entry for each external LBA, plus any alignment
required to maintain an alignment of EFI_BTT_ALIGNMENT for the entire map:
MapSize = roundup(ExternalNLba *sizeof(EFI_BTT_MAP_ENTRY),
EFI_BTT_ALIGNMENT)
The number of concurrent writes allowed for an arena is based on the NFree value chosen at BTT layout time. For
example, choosing NFree of 256 means the BTT Arena shall have 256 free blocks to use for in-ﬂight write operations.
Since BTT Arenas each have NFree free blocks, the number of concurrent writes allowed in a namespace may be
larger when there are multiple arenas and the writes are spread out between multiple arenas.
6.3.2 Atomicity of Data Blocks in an Arena
The primary reason for the BTT is to provide failure atomicity when writing data blocks, so that any write of a single
block cannot be torn by interruptions such as power loss. The BTT provides this by maintaining a pool of free blocks
which are not part of the capacity advertised to software layers above the BTT software. The BTT Data Area is large
enough to hold the advertised capacity as well as the pool of free blocks. The BTT software manages the blocks in the
BTT Data Area as a list of internal LBAs, which are block numbers only visible internally to the BTT software. The
block numbers that make up the advertised capacity are known as external LBAs, and at any given point in time, each
one of those external LBAs is mapped by the BTT Map to one of the blocks in the BTT Data Area. Each block write
done by the BTT software starts by allocating one of the free blocks, writing the data to it, and only when that block
is fully persistent (including any ﬂushes required), are steps taken to make that block active, as outlined in the BTT
Theory of Operations - Write Path section.
The BTT Flog (a combination of a free list and a log) is at the heart of the atomic updates when writing blocks. The
“quiet” state of a BTT Flog, when no in-ﬂight writes are happening and no recovery steps are outstanding, is that the
NFree free blocks currently available for writes are contained in the OldMap ﬁelds in the Flog entries. A write shall
use one of those Flog entries to ﬁnd a free block to write to, and then the Lba and NewMap ﬁelds in the Flog are
used as a write-ahead-log for the BTT Map update when the data portion of the write is complete, as described in the
Validating the Flog at start-up section.
It is up to run-time logic in the BTT software to ensure that only one Flog entry is in use at a time, and that any reads
still executing on the block indicated by the OldMap entry have ﬁnished before starting a write using that block.
6.3. BTT Theory of Operation 128Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
6.3.3 Atomicity of BTT Data Structures
Byte-addressable persistent media may not support atomic updates larger than 8-bytes, so any data structure larger
than 8-bytes in the BTT uses software-implemented atomicity for updates. Note that 8-byte write atomicity, meaning
an 8-byte store to the persistent media cannot be torn by interruptions such as power failures, is a minimal requirement
for using the BTT described in this document.
There are four types of data structures in the BTT:
• The BTT Info Blocks
• The BTT Map
• The BTT Flog
• The BTT Data Area
The BTT Map entries are 4-bytes in size, and so can be updated atomically with a single store instruction. All other
data structures are updated by following the rules described in this document, which update an inactive version of the
data structure ﬁrst, followed by steps to make it active atomically.
For the BTT Info Blocks, atomicity is provided by always writing the backup Info block ﬁrst, and only after that update
is fully persistent (the block checksums correctly), is the primary BTT Info Block updated as described in the Writing
the initial BTT layout section. Recovery from an interrupted update is provided by checking the primary Info block’s
checksum on start-up, and if it is bad, copying the backup Info block to the primary to complete the interrupted update
as described in the Validating BTT Arenas at start-up section.
For the BTT Flog, each entry is double-sized, with two complete copies of every ﬁeld (Lba, OldMap, NewMap, Seq).
The active entry has the higher Seq number, so updates always write to the inactive ﬁelds, and once those ﬁelds are
fully persistent, the Seq ﬁeld for the inactive entry is updated to make it become the active entry atomically. This is
described in the Validating the Flog at start-up section.
For the BTT Data Area, all block writes can be thought of as allocating writes , where an inactive block is chosen from
the free list maintained by the Flog, and only after the new data written to that block is fully persistent, that block is
made active atomically by updating the Flog and Map entries as described in the Write Path section.
6.3.4 Writing the Initial BTT layout
The overall layout of the BTT relies on the fact that all arenas shall be 512GiB in size, except the last arena which is
a minimum of 16MiB. Initializing the BTT on-media structures only happens once in the lifetime of a BTT, when it
is created. This sequence assumes that software has determined that new BTT layout needs to be created and the total
raw size of the namespace is known.
Immediately before creating a new BTT layout, the UUID of the surrounding namespace may be updated to a newly-
generated UUID. This optional step, depending on the needs of a BTT software implementation, has the effect of
invalidating any previous BTT Info Blocks in the namespace and ensuring the detection of an invalid layout if the BTT
layout creation process is interrupted. This detection works because the parent UUID ﬁeld
The on-media structures in the BTT layout may be written out in any order except for the BTT Info Blocks, which
shall be written out as the last step of the layout, starting from the last arena (highest offset in the namespace) to
the ﬁrst arena (lowest offset in the namespace), writing the backup BTT Info Block in each arena ﬁrst, then writing
the primary BTT Info block for that arena second. This allows the detection of an incomplete BTT layout when the
algorithm in the Validating BTT Arenas at start-up section is executed.
Since the number of internal LBAs for an arena exceeds the number of external LBAs by NFree , there are enough
internal LBA numbers to fully initialize the BTT Map as well as the BTT Flog, where the BTT Flog is initialized with
theNFree highest internal LBA numbers, and the rest are used in the BTT Map.
6.3. BTT Theory of Operation 129Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The BTT Map in each arena is initialized to zeros. Zero entries in the map indicate the identity mapping of all pre-map
LBAs to the corresponding post-map LBAs. This uses all but NFree of the internal LBAs, leaving Nfree of them for
the BTT Flog.
The BTT Flog in each arena is initialized by starting with all zeros for the entire ﬂog area, setting the Lba0 ﬁeld in
each ﬂog entry to unique pre-map LBAs, zero through NFree - 1 , and both OldMap0 andNewMap0 ﬁelds in each
ﬂog entry are set to one of the remaining internal LBAs. For example, ﬂog entry zero would have Lba0 set to 0, and
OldMap0 andNewMap0 both set to the ﬁrst internal LBA not represented in the map (since there are ExternalNLba
entries in the map, the next available internal LBA is equal to ExternalNLba ).
6.3.5 Validating BTT Arenas at start-up
When software prepares to access the BTT layout in a namespace, the ﬁrst step is to check the BTT Arenas for
consistency. Reading and validating BTT Arenas relies on the fact that all arenas shall be 512GiB in size, except the
last arena which is a minimum of 16MiB.
The following tests shall pass before software considers the BTT layout to be valid:
• For each BTT Arena:
–ReadAndVerifyPrimaryBttInfoBlock
*If the read of the primary BTT Info Block fails, goto ReadAndVerifyBackupBttInfoBlock
*If the primary BTT Info Block contains an incorrect Sigﬁeld it is invalid, goto ReadAndVerifyBack-
upBttInfoBlock
*If the primary BTT Info Block ParentUuid ﬁeld does not match the UUID of the surrounding names-
pace, goto ReadAndVerifyBackupBttInfoBlock
*If the primary BTT Info Block contains an incorrect Checksum it is invalid, goto ReadAndVerify-
BackupBttInfoBlock

*The primary BTT Info Block is valid. Use the NextOff ﬁeld to ﬁnd the start of the next arena and
continue BTT Info Block validation, goto ReadAndVerifyPrimaryBttInfoBlock
–ReadAndVerifyBackupBttInfoBlock
*Determine the location of the backup BTT Info Block:
1. All of the arenas shall be the full 512GiB data area size except the last arena which is at least
16MiB.
2. The backup BTT Info Block is the last EFI_BTT_ALIGNMENT aligned block in the arena.
*If the read of the backup BTT Info Block at the high address of the BTT Arena fails, neither copy
could be read, and software shall assume that there is no valid BTT metadata layout for the namespace
*If the backup BTT Info Block contains an incorrect Sigﬁeld it is invalid, and software shall assume
that there is no valid BTT metadata layout for the namespace
*If the backup BTT Info Block ParentUuid ﬁeld does not match the UUID of the surrounding names-
pace it is invalid, and software shall assume that there is no valid BTT metadata layout for the names-
pace
*If the backup BTT Info Block contains an incorrect Checksum it is invalid, and software shall assume
*The backup BTT Info Block is valid. Since the primary copy is bad, software shall copy the contents
of the valid backup BTT Info Block down to the primary BTT Info Block before validation of all of
the BTT Info Blocks in all of the arenas can complete successfully.
6.3. BTT Theory of Operation 130Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
6.3.6 Validating the Flog entries at start-up
After validating the BTT Info Blocks as described in the Validating BTT Arenas at start-up section, the next step
software shall take is to validate the BTT Flog entries. When blocks of data are being written, as described in the
Write Path section below, the persistent Flog and Map states are not updated until the free block is written with new
data. This ensures a power failure at any point during the data transfer is harmless, leaving the partially written data
in a free block that remains free. Once the Flog is updated (made atomic by the Seq bits in the Flog entry), the write
algorithm is committed to the update and a power failure from this point in the write ﬂow onwards shall be handled
by completing the update to the BTT Map on recovery. The Flog contains all the information required to complete the
Map entry update.
Note that the Flog entry recovery outlined here is intended to happen single-threaded, on an inactive BTT (before
the BTT block namespace is allowed to accept I/O requests). The maximum amount of time required for recovery
is determined by NFree , but is only a few loads and a single store (and the corresponding cache ﬂushes) for each
incomplete write discovered.
The following steps are executed for each ﬂog entry in each arena, to recover any interrupted writes and to verify the
ﬂog entries are consistent at start up. Any consistency issues found during these steps results in setting the error state
(EFI_BTT_INFO_BLOCK_FLAGS_ERROR) for the arena and terminates the ﬂog validation process for this arena.
1. The Seq0 andSeq1 ﬁelds are examined for the ﬂog entry. If both ﬁelds are zero, or both ﬁelds are equal to each
other, the ﬂog entry is inconsistent. Otherwise, the higher Seq ﬁeld indicates which set of ﬂog ﬁelds to use for
the next steps ( Lba0 ,OldMap0 ,NewMap0 , versus Lba1 ,OldMap1 ,NewMap1 ). From this point on in this
section, the chosen ﬁelds are referenced as Lba, OldMap, and NewMap.
2. If OldMap and NewMap are equal, this is a ﬂog entry that was never used since the initial layout of the BTT
was created.
3. The Lba ﬁeld is checked to ensure it is a valid pre-map LBA (in the range zero to ExternalNLba – 1). If the
check fails, the ﬂog entry is inconsistent.
4. The BTT Map entry corresponding to the Flog entry Lba ﬁeld is fetched. Since the Map can contain special
zero entries to indicate identity mappings, the fetched entry is adjusted to the corresponding internal LBA when
a zero is encountered (by interpreting the entry as the same LBA as the Flog entry Lba ﬁeld).
5. If the adjusted map entry from the previous step does not match the NewMap ﬁeld in the Flog entry, and it
matches the OldMap ﬁeld, then an interrupted BTT Map update has been detected. The recovery step is to write
the NewMap ﬁeld to the BTT Map entry indexed by the Flog entry Lba ﬁeld.
6.3.7 Read Path
The following high level sequence describes the steps to read a single block of data while utilizing the BTT as is
illustrated in the Figure: BTT Read Path Overview below:
1. If EFI_BTT_INFO_BLOCK_FLAGS_ERROR is set in the arena’s BTT Info Block, the BTT software may
return an error for the read, or an implementation may choose to continue to provide read-only access and
continue these steps.
2. Use the external LBA provided with the read operation to determine which BTT Arena to access. Starting from
the ﬁrst arena (lowest offset in the namespace), and looping through the arena in order, the ExternalNLba ﬁeld
in the BTT Info Block describes how many exernal LBAs are in that area. Once the correct arena is identiﬁed,
the external LBAs contained in the lower, skipped, arenas are subtracted from the provided LBA to obtain the
pre-map LBA for the selected arena.
3. Use the pre-map LBA to index into the arena’s BTT Map and the map entry.
4. If both the Zero andError bits are set in the map entry, this indicates a normal entry. The PostMapLba ﬁeld in
the Map entry is used to index into the arena Data Area by multiplying it by the InternalLbaSize and adding
6.3. BTT Theory of Operation 131Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
the result to the DataOff ﬁeld from the arena’s BTT Info Block. This provides the location of the data in the
arena and software then copies ExternalLbaSize bytes into the provided buffer to satisfy the read request.
5. Otherwise, if only the Error bit is set in the map entry, a read error is returned.
6. Otherwise, if only the Zero bit is set in the map entry, a block of ExternalLbaSize bytes of zeros is copied into
the provided buffer to satisfy the read request.
7. Finally, if both Zero andError bits are clear, this the initial identity mapping and the pre-map LBA is used to
index into the arena Data Area by multiplying it by the InternalLbaSize and adding the result to the DataOff
ﬁeld from the arena’s BTT Info Block. This provides the location of the data in the arena and software then
copies ExternalLbaSize bytes into the provided buffer to satisfy the read request.
Fig. 6.4: BTT Read Path Overview
6.3.8 Write Path
The following high level sequence describes the steps to write a single block of data while utilizing the BTT as is
illustrated in the Figure: BTT Write Path Overview below :
1. If EFI_BTT_INFO_BLOCK_FLAGS_ERROR is set in the arena’s BTT Info Block, the BTT software shall
return an error for the write.
2. Use the external LBA provided with the write operation to determine which BTT Arena to access. Starting from
3. The BTT software allocates one of the Flog entries in the arena to be used for this write. The Flog entry shall not
be shared by multiple concurrent writes. The exact method for managing the exclusive use of the Flog entries is
BTT software implementation-dependent. There’s no on-media indication of whether a Flog entry is currently
6.3. BTT Theory of Operation 132Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
allocated to a write request or not. Note that the free block tracked by the Flog entry in the OldMap ﬁeld, may
still have reads from relatively slow threads operating on it. The BTT software implementation shall ensure any
such reads have completed before moving to the next step.
4. Lock out access to the BTT Map area associated with the pre-map LBA for the next three steps. The granularity
of the locking is implementation-dependent; an implementation may choose to lock individual Map entries, lock
the entire BTT Map, or something in-between.
5. Use the pre-map LBA to index into the arena’s BTT Map and fetch the old map entry.
6. Update the Flog entry by writing the inactive set of Flog ﬁelds (the lower Seq number). First, update the
Lba, OldMap, and NewMap ﬁelds with the pre-map LBA, old Map entry, and the free block chosen above,
respectively. Once those ﬁelds are fully persistent (with any required ﬂushes completed), the Seq ﬁeld is updated
to make the new ﬁelds active. This update of the Seq ﬁeld commits the write - before this update, the write shall

not take place if the operation is interrupted. After the Seq ﬁeld is updated, the write shall take place even if the
operation is interrupted because the Map update in the next step shall take place during the BTT recovery that
happens on start-up.
7. Update the Map entry with the free block chosen above.
8. Drop the map lock acquired in step 4 above. The write request is now satisﬁed.
Fig. 6.5: BTT Write Path Overview
6.3. BTT Theory of Operation 133CHAPTER
SEVEN
SERVICES — BOOT SERVICES
This section discusses the fundamental boot services that are present in a UEFI compliant system. The services are
deﬁned by interface functions that may be used by code running in the UEFI environment. Such code may include
protocols that manage device access or extend platform capability, as well as applications running in the preboot
environment, and OS loaders.
Two types of services apply in an compliant system:
Boot Services
Functions that are available before a successful call to EFI_BOOT_SERVICES.ExitBootServices() . These functions
are described in this section.
Runtime Services
Functions that are available before and after any call to ExitBootServices(). These functions are described in Services
— Runtime Services .
During boot, system resources are owned by the ﬁrmware and are controlled through boot services interface functions.
These functions can be characterized as “global” or “handle-based.” The term “global” simply means that a function
accesses system services and is available on all platforms (since all platforms support all system services). The term
“handle-based” means that the function accesses a speciﬁc device or device functionality and may not be available on
some platforms (since some devices are not available on some platforms). Protocols are created dynamically. This
section discusses the “global” functions and runtime functions; subsequent sections discuss the “handle-based.”
UEFI applications (including UEFI OS loaders) must use boot services functions to access devices and allocate mem-
ory. On entry, an Image is provided a pointer to a system table which contains the Boot Services dispatch table and
the default handles for accessing the console. All boot services functionality is available until a UEFI OS loader loads
enough of its own environment to take control of the system’s continued operation and then terminates boot services
with a call to ExitBootServices().
In principle, the ExitBootServices() call is intended for use by the operating system to indicate that its loader is ready
to assume control of the platform and all platform resource management. Thus boot services are available up to this
point to assist the UEFI OS loader in preparing to boot the operating system. Once the UEFI OS loader takes control
of the system and completes the operating system boot process, only runtime services may be called. Code other than
the UEFI OS loader, however, may or may not choose to call ExitBootServices(). This choice may in part depend
upon whether or not such code is designed to make continued use of boot services or the boot services environment.
The rest of this section discusses individual functions. Global boot services functions fall into these categories:
• Event, Timer, and Task Priority Services Event, Timer, and Task Priority Services
• Memory Allocation Services Memory Allocation Services
• Protocol Handler Services Protocol Handler Services
• Image Services Image Services
134Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.1 Event, Timer, and Task Priority Services
The functions that make up the Event, Timer, and Task Priority Services are used during preboot to create, close,
signal, and wait for events; to set timers; and to raise and restore task priority levels. See the following table for
details.
Table 7.1: Event, Timer, and Task Priority Functions
Name Type Description
CreateEvent Boot Creates a general-purpose event structure
CreateEventEx Boot Creates an event structure as part of an event group
CloseEvent Boot Closes and frees an event structure
SignalEvent Boot Signals an event
WaitForEvent Boot Stops execution until an event is signaled
CheckEvent Boot Checks whether an event is in the signaled state
SetTimer Boot Sets an event to be signaled at a particular time
RaiseTPL Boot Raises the task priority level
RestoreTPL Boot Restores/lowers the task priority level
Execution in the boot services environment occurs at different task priority levels, or TPLs. The boot services envi-
ronment exposes only three of these levels to UEFI applications and drivers ( see table below: TPL Usage )
•TPL_APPLICATION — the lowest priority level
•TPL_CALLBACK — an intermediate priority level{
•TPL_NOTIFY — the highest priority level
Tasks that execute at a higher priority level may interrupt tasks that execute at a lower priority level. For example,
tasks that run at the TPL_NOTIFY level may interrupt tasks that run at the TPL_APPLICATION or TPL_CALLBACK
level. While TPL_NOTIFY is the highest level exposed to the boot services applications, the ﬁrmware may have higher
task priority items it deals with. For example, the ﬁrmware may have to deal with tasks of higher priority like timer
ticks and internal devices. Consequently, there is a fourth TPL, TPL_HIGH_LEVEL {link needed}, designed for use
exclusively by the ﬁrmware.
The intended usage of the priority levels is shown in the TPL Usage table below, from the lowest level
(TPL_APPLICATION) to the highest level (TPL_HIGH_LEVEL). As the level increases, the duration of the code
and the amount of blocking allowed decrease. Execution generally occurs at the TPL_APPLICATION level. Execu-
tion occurs at other levels as a direct result of the triggering of an event notiﬁcation function(this is typically caused
by the signaling of an event). During timer interrupts, ﬁrmware signals timer events when an event’s “trigger time”
has expired. This allows event notiﬁcation functions to interrupt lower priority code to check devices (for example).
The notiﬁcation function can signal other events as required. After all pending event notiﬁcation functions execute,
execution continues at the TPL_APPLICATION level.
Table 7.2: TPL Usage
Task Priority Level Usage
TPL_APPLICATION This is the lowest priority level. It is the level of execution which occurs when no
event notiﬁcations are pending and which interacts with the user. User I/O (and block-
ing on User I/O) can be performed at this level. The boot manager executes at this
level and passes control to other UEFI applications at this level.
TPL_CALLBACK Interrupts code executing below TPL_CALLBACK level. Long term operations (such
as ﬁle system operations and disk I/O) can occur at this level.
7.1. Event, Timer, and Task Priority Services 135Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 7.2 – continued from previous page
TPL_NOTIFY Interrupts code executing below TPL_NOTIFY level. Blocking is not allowed at this
level. Code executes to completion and returns. If code requires more processing, it
needs to signal an event to wait to obtain control again at whatever level it requires.
This level is typically used to process low level IO to or from a device.
(Firmware Interrupts) This level is internal to the ﬁrmware. It is the level at which internal interrupts occur.
Code running at this level interrupts code running at the TPL_NOTIFY level (or lower
levels). If the interrupt requires extended time to complete, ﬁrmware signals another
event (or events) to perform the longer term operations so that other interrupts can
occur.
TPL_HIGH_LEVEL Interrupts code executing below TPL_HIGH_LEVEL This is the highest priority
level. It is not interruptible (interrupts are disabled) and is used sparingly by ﬁrmware
to synchronize operations that need to be accessible from any priority level. For exam-
ple, it must be possible to signal events while executing at any priority level. There-
fore, ﬁrmware manipulates the internal event structure while at this priority level.
Executing code can temporarily raise its priority level by calling the EFI_BOOT_SERVICES.RaiseTPL() func-
tion. Doing this masks event notiﬁcations from code running at equal or lower priority levels until the
EFI_BOOT_SERVICES.RestoreTPL() function is called to reduce the priority to a level below that of the pending
event notiﬁcations. There are restrictions on the TPL levels at which many UEFI service functions and protocol
interface functions can execute. TPL Restrictions summarizes the restrictions.
Table 7.3: TPL Restrictions
Name Restrictions Task Priority
ACPI Table Protocol < TPL_NOTIFY
ARP <= TPL_CALLBACK
ARP Service Binding <= TPL_CALLBACK
Authentication Info <= TPL_NOTIFY
Block I/O Protocol <= TPL_CALLBACK
Block I/O 2 Protocol <= TPL_CALLBACK
Bluetooth Host <= TPL_CALLBACK
Bluetooth Host Controller <= TPL_CALLBACK
Bluetooth IO Service Binding <= TPL_CALLBACK
Bluetooth IO <= TPL_CALLBACK

Bluetooth Attribute <= TPL_CALLBACK
Bluetooth Conﬁguration <= TPL_CALLBACK
BluetoorhLE Conﬁguration <= TPL_CALLBACK
CheckEvent() < TPL_HIGH_LEVEL
CloseEvent() < TPL_HIGH_LEVEL
CreateEvent() < TPL_HIGH_LEVEL
Deferred Image Load Protocol <= TPL_NOTIFY
Device Path Utilities <= TPL_NOTIFY
Device Path From Text <= TPL_NOTIFY
DHCP4 Service Binding <= TPL_CALLBACK
DHCP4 <= TPL_CALLBACK
DHCP6 <= TPL_CALLBACK
DHCP6 Service Binding <= TPL_CALLBACK
Disk I/O Protocol <= TPL_CALLBACK
Disk I/O 2 Protocol <= TPL_CALLBACK
DNS4 Service Binding <= TPL_CALLBACK
DNS4 <= TPL_CALLBACK
7.1. Event, Timer, and Task Priority Services 136Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 7.3 – continued from previous page
DNS6 Service Binding <= TPL_CALLBACK
DNS6<= TPL_CALLBACK
Driver Health <= TPL_NOTIFY
EAP <= TPL_CALLBACK
EAP Conﬁguration <= TPL_CALLBACK
EAP Management <= TPL_CALLBACK
EAP Management2 <= TPL_CALLBACK
EDID Active <= TPL_NOTIFY
EDID Discovered <= TPL_NOTIFY
EFI_SIMPLE_TEXT_INPUT_PROTOCOL <= TPL_CALLBACK
EFI_SIMPLE_TEXT_INPUT_PROTOCOL.ReadKeyStroke <= TPL_APPLICATION
EFI_SIMPLE_TEXT_INPUT_PROTOCOL.Reset <= TPL_APPLICATION
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL <= TPL_CALLBACK
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.ReadKeyStrokeEx <= TPL_APPLICATION
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.Reset <= TPL_APPLICATION
Event Notiﬁcation Levels > TPL_APPLICATION
Event Notiﬁcation Levels <= TPL_HIGH_LEVEL
Exit() <= TPL_CALLBACK
ExitBootServices() = TPL_APPLICATION
Form Browser2 Protocol/SendForm = TPL_APPLICATION
FTP <= TPL_CALLBACK
Graphics Output EDID Override <= TPL_NOTIFY
HII Protocols <= TPL_NOTIFY
HTTP Service Binding <= TPL_CALLBACK
HTTP <= TPL_CALLBACK
HTTP Utilities <= TPL_CALLBACK
IP4 Service Binding <= TPL_CALLBACK
IP4 <= TPL_CALLBACK
IP4 Conﬁg <= TPL_CALLBACK
IP4 Conﬁg2 <= TPL_CALLBACK
IP6 <= TPL_CALLBACK
IP6 Conﬁg <= TPL_CALLBACK
IPSec Conﬁguration <= TPL_CALLBACK
iSCSI Initiator Name <= TPL_NOTIFY
LoadImage() < TPL_CALLBACK
Managed Network Service Binding <= TPL_CALLBACK
Memory Allocation Services <= TPL_NOTIFY
MTFTP4 Service Binding <= TPL_CALLBACK
MTFTP4 <= TPL_CALLBACK
MTFTP6 <= TPL_CALLBACK
MTFTP6 Service Binding <= TPL_CALLBACK
PXE Base Code Protocol <= TPL_CALLBACK
Protocol Handler Services <= TPL_NOTIFY
REST <= TPL_CALLBACK
Serial I/O Protocol <= TPL_CALLBACK
SetTimer() < TPL_HIGH_LEVEL
SignalEvent() <= TPL_HIGH_LEVEL
Simple File System Protocol <= TPL_CALLBACK
7.1. Event, Timer, and Task Priority Services 137Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Simple Network Protocol <= TPL_CALLBACK
Simple Text Output Protocol <= TPL_NOTIFY
Stall() <= TPL_HIGH_LEVEL
StartImage() < TPL_CALLBACK
Supplicant <= TPL_CALLBACK
Tape IO <= TPL_NOTIFY
TCP4 Service Binding <= TPL_CALLBACK
TCP4 <= TPL_CALLBACK
TCP6 <= TPL_CALLBACK
TCP6 Service Binding <= TPL_CALLBACK
Time Services <= TPL_CALLBACK
TLS Service Binding <= TPL_CALLBACK
TLS <= TPL_CALLBACK
TLS Conﬁguration <= TPL_CALLBACK
UDP4 Service Binding <= TPL_CALLBACK
UDP4 <= TPL_CALLBACK
UDP6 <= TPL_CALLBACK
UDP6 Service Binding <= TPL_CALLBACK
UnloadImage() <= TPL_CALLBACK
User Manager Protocol <= TPL_NOTIFY
User Manager Protocol/Identify() = TPL_APPLICATION
User Credential Protocol <= TPL_NOTIFY
User Info Protocol <= TPL_NOTIFY
Variable Services <= TPL_CALLBACK
VLAN Conﬁguration <= TPL_CALLBACK
WaitForEvent() = TPL_APPLICATION
Wireless MAC Connection <= TPL_CALLBACK
Other protocols and services, if not listed above <= TPL_NOTIFY
7.1.1 EFI_BOOT_SERVICES.CreateEvent()
Summary
Creates an event.
Prototype
typedef
(EFIAPI *EFI_CREATE_EVENT) (
IN UINT32 Type,
IN EFI_TPL NotifyTpl,
IN EFI_EVENT_NOTIFY NotifyFunction, OPTIONAL
IN VOID *NotifyContext, OPTIONAL
OUT EFI_EVENT *Event
);
Type The type of event to create and its mode and attributes. The #deﬁne statements in “Related Deﬁnitions” can be
used to specify an event’s mode and attributes.
NotifyTpl The task priority level of event notiﬁcations, if needed. See EFI_BOOT_SERVICES.RaiseTPL() .
7.1. Event, Timer, and Task Priority Services 138Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NotifyFunction Pointer to the event’s notiﬁcation function, if any. See “Related Deﬁnitions.”
NotifyContext Pointer to the notiﬁcation function’s context; corresponds to parameter Context in the notiﬁcation
function.
Event Pointer to the newly created event if the call succeeds; undeﬁned otherwise.
//***************************************************
// EFI_EVENT
//******************************************************
typedef VOID *EFI_EVENT
// Event Types
// These types can be "ORed" together asneeded - forexample,
// EVT_TIMER might be "Ored" withEVT_NOTIFY_WAIT or
// EVT_NOTIFY_SIGNAL.
#define EVT_TIMER 0x80000000
#define EVT_RUNTIME 0x40000000
#define EVT_NOTIFY_WAIT 0x00000100
#define EVT_NOTIFY_SIGNAL 0x00000200
#define EVT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201
#define EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202
EVT_TIMER The event is a timer event and may be passed to EFI_BOOT_SERVICES.SetTimer() . Note that timers
only function during boot services time.
EVT_RUNTIME The event is allocated from runtime memory. If an event is to be signaled after the call to
EFI_BOOT_SERVICES.ExitBootServices() the event’s data structure and notiﬁcation function need to be al-
located from runtime memory. For more information, see SetVirtualAddressMap() .
EVT_NOTIFY_WAIT If an event of this type is not already in the signaled state, then the event’s No-
tiﬁcationFunction will be queued at the event’s NotifyTpl whenever the event is being waited on via
EFI_BOOT_SERVICES.WaitForEvent() orEFI_BOOT_SERVICES.CheckEvent() .
EVT_NOTIFY_SIGNAL The event’s NotifyFunction is queued whenever the event is signaled.
EVT_SIGNAL_EXIT_BOOT_SERVICES This event is of type EVT_NOTIFY_SIGNAL.
It should not be combined with any other event types. This event type is func-
tionally equivalent to the EFI_EVENT_GROUP_EXIT_BOOT_SERVICES event group.
Refer to EFI_EVENT_GROUP_EXIT_BOOT_SERVICES event group description in
EFI_BOOT_SERVICES.CreateEventEx() section below for additional details.
EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE The event is to be notiﬁed by the system when SetVirtualAd-
dressMap() is performed. This event type is a composite of EVT_NOTIFY_SIGNAL, EVT_RUNTIME, and
EVT_RUNTIME_CONTEXT and should not be combined with any other event types.
//****************************************************** \*
// EFI_EVENT_NOTIFY
typedef
VOID
(EFIAPI *EFI_EVENT_NOTIFY) (
IN EFI_EVENT Event,
7.1. Event, Timer, and Task Priority Services 139Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN VOID *Context
);
Event Event whose notiﬁcation function is being invoked.
Context Pointer to the notiﬁcation function’s context, which is implementation-dependent. Context corresponds to
NotifyContext inEFI_BOOT_SERVICES.CreateEventEx() .
TheCreateEvent() function creates a new event of type Type and returns it in the location referenced by Event . The
event’s notiﬁcation function, context, and task priority level are speciﬁed by NotifyFunction ,NotifyContext , and Noti-
fyTpl , respectively.
Events exist in one of two states, “waiting” or “signaled.” When an event is created, ﬁrmware puts it in the “waiting”
state. When the event is signaled, ﬁrmware changes its state to “signaled” and, if EVT_NOTIFY_SIGNAL is speciﬁed,
places a call to its notiﬁcation function in a FIFO queue. There is a queue for each of the “basic” task priority levels
deﬁned in Event, Timer, and Task Priority Services (TPL_CALLBACK , and TPL_NOTIFY ). The functions in these
queues are invoked in FIFO order, starting with the highest priority level queue and proceeding to the lowest priority
queue that is unmasked by the current TPL. If the current TPL is equal to or greater than the queued notiﬁcation, it
will wait until the TPL is lowered via EFI_BOOT_SERVICES.RestoreTPL() .
In a general sense, there are two “types” of events, synchronous and asynchronous. Asynchronous events are closely
related to timers and are used to support periodic or timed interruption of program execution. This capability is
typically used with device drivers. For example, a network device driver that needs to poll for the presence of new
packets could create an event whose type includes EVT_TIMER and then call the EFI_BOOT_SERVICES.SetTimer()
function. When the timer expires, the ﬁrmware signals the event.
Synchronous events have no particular relationship to timers. Instead, they are used to ensure that certain ac-
tivities occur following a call to a speciﬁc interface function. One example of this is the cleanup that needs

to be performed in response to a call to the EFI_BOOT_SERVICES.ExitBootServices() function. ExitBoot-
Services() can clean up the ﬁrmware since it understands ﬁrmware internals, but it cannot clean up on be-
half of drivers that have been loaded into the system. The drivers have to do that themselves by creating
an event whose type is EVT_SIGNAL_EXIT_BOOT_SERVICES and whose notiﬁcation function is a function
within the driver itself. Then, when ExitBootServices() has ﬁnished its cleanup, it signals each event of type
EVT_SIGNAL_EXIT_BOOT_SERVICES.
Another example of the use of synchronous events occurs when an event of type
EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE is used in conjunction with the SetVirtualAddressMap() .
The EVT_NOTIFY_WAIT and EVT_NOTIFY_SIGNAL ﬂags are exclusive. If neither ﬂag is speciﬁed, the caller
does not require any notiﬁcation concerning the event and the NotifyTpl ,NotifyFunction , and NotifyContext pa-
rameters are ignored. If EVT_NOTIFY_WAIT is speciﬁed and the event is not in the signaled state, then the
EVT_NOTIFY_WAIT notify function is queued whenever a consumer of the event is waiting for the event (via
EFI_BOOT_SERVICES.WaitForEvent() or EFI_BOOT_SERVICES.CheckEvent() ). If the EVT_NOTIFY_SIGNAL
ﬂag is speciﬁed then the event’s notify function is queued whenever the event is signaled.
NOTE :Because its internal structure is unknown to the caller , Event cannot be modiﬁed by the caller. The only way
to manipulate it is to use the published event interfaces .
EFI_SUCCESS The event structure was created.
EFI_INV ALID_PARAMETER One of the parameters has an invalid value.
EFI_INV ALID_PARAMETER Event is NULL.
EFI_INV ALID_PARAMETER Type has an unsupported bit set.
7.1. Event, Timer, and Task Priority Services 140Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 7.4 – continued from previous page
EFI_INV ALID_PARAMETER Type has both EVT_NOTIFY_SIGNAL and EVT_NOTIFY_WAIT set.
EFI_INV ALID_PARAMETER Type has either EVT_NOTIFY_SIGNAL or EVT_NOTIFY_WAIT set and
-NotifyFunction is NULL.
NotifyTpl is not a supported TPL level.
EFI_OUT_OF_RESOURCES The event could not be allocated.
7.1.2 EFI_BOOT_SERVICES.CreateEventEx()
Summary
Creates an event in a group.
Prototype
typedef
(EFIAPI *EFI_CREATE_EVENT_EX) (
IN EFI_EVENT_NOTIFY NotifyFunction OPTIONAL,
IN CONST VOID *NotifyContext OPTIONAL,
IN CONST EFI_GUID *EventGroup OPTIONAL,
);
Type The type of event to create and its mode and attributes.
NotifyFunction Pointer to the event’s notiﬁcation function, if any.
function.
EventGroup Pointer to the unique identiﬁer of the group to which this event belongs. If this is NULL, then the
function behaves as if the parameters were passed to CreateEvent.
The CreateEventEx function creates a new event of type Type and returns it in the speciﬁed location indicated by
Event . The event’s notiﬁcation function, context and task priority are speciﬁed by NotifyFunction, NotifyContext , and
NotifyTpl , respectively. The event will be added to the group of events identiﬁed by EventGroup.
If no group is speciﬁed by EventGroup , then this function behaves as if the same parameters had been passed to
CreateEvent.
Event groups are collections of events identiﬁed by a shared EFI_GUID where, when one member event is signaled,
all other events are signaled and their individual notiﬁcation actions are taken (as described in CreateEvent). All events
are guaranteed to be signaled before the ﬁrst notiﬁcation action is taken. All notiﬁcation functions will be executed in
the order speciﬁed by their NotifyTpl .
A single event can only be part of a single event group. An event may be removed from an event group by using
CloseEvent.
7.1. Event, Timer, and Task Priority Services 141Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The Type of an event uses the same values as deﬁned in CreateEvent except that
EVT_SIGNAL_EXIT_BOOT_SERVICES and EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE are not valid.
IfType has EVT_NOTIFY_SIGNAL or EVT_NOTIFY_WAIT, then NotifyFunction must be non-NULL and NotifyTpl
must be a valid task priority level. Otherwise these parameters are ignored.
More than one event of type EVT_TIMER may be part of a single event group. However, there is no mechanism for
determining which of the timers was signaled.
Conﬁguration Table Groups
The GUID for a conﬁguration table also deﬁnes a corresponding event group GUID with the same value. If the data
represented by a conﬁguration table is changed, InstallConﬁgurationTable() should be called. When InstallConﬁgu-
rationTable() is called, the corresponding event is signaled. When this event is signaled, any components that cache
information from the conﬁguration table can optionally update their cached state.
For example, EFI_ACPI_TABLE_GUID deﬁnes a conﬁguration table for ACPI data. When ACPI data is changed,
InstallConﬁgurationTable() is called. During the execution of InstallConﬁgurationTable(), a corresponding event group
with EFI_ACPI_TABLE_GUID is signaled, allowing an application to invalidate any cached ACPI data.
Pre-Deﬁned Event Groups
This section describes the pre-deﬁned event groups used by the UEFI speciﬁcation.
EFI_EVENT_GROUP_EXIT_BOOT_SERVICES
This event group is notiﬁed by the system when ExitBootServices() is invoked after notifying
EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES event group. This event group is functionally equivalent
to the EVT_SIGNAL_EXIT_BOOT_SERVICES ﬂag for the Type argument of CreateEvent. The notiﬁcation function
for this event must comply with the following requirements:
• The notiﬁcation function is not allowed to use the Memory Allocation Services, or call any functions that use
the Memory Allocation Services, because these services modify the current memory map.
Note: Since consumer of the service does not necessarily knows if the service uses memory allocation services,
this requirement is effectively a mandate to reduce usage of any external services (services implemented outside of
the driver owning the notiﬁcation function) to an absolute minimum required to perform an orderly transition to a
runtime environment .Usage of the external services may yield unexpected results .Since UEFI speciﬁcation does not
guarantee any given order of notiﬁcation function invocation, a notiﬁcation function consuming the service may be
invoked before or after the notiﬁcation function of the driver providing the service .As a result, a service being called
by the notiﬁcation function may exhibit boot time behavior or a runtime behavior (which is undeﬁned for a pure boot
services ).
• The notiﬁcation function must not depend on timer events since timer services will be deactivated before any
notiﬁcation functions are called.
Refer to EFI_BOOT_SERVICES.ExitBootServices() below for additional details.
EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES
This event group is notiﬁed by the system ExitBootServices() is invoked right before notifying
EFI_EVENT_GROUP_EXIT_BOOT_SERVICES event group. The event presents the last opportunity to use
ﬁrmware interfaces in the boot environment.
The notiﬁcation function for this event must not depend on any kind of delayed processing (processing that happens in
a timer callback beyond the time span of the notiﬁcation function) because system ﬁrmware deactivates timer services
right after dispatching handlers for this event group.
Refer to EFI_BOOT_SERVICES .ExitBootServices() below for additional details.
EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE
7.1. Event, Timer, and Task Priority Services 142Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This event group is notiﬁed by the system when SetVirtualAddressMap() is invoked. This is functionally equivalent to
the VT_SIGNAL_VIRTUAL_ADDRESS_CHANGE ﬂag for the Type argument of CreateEvent.
EFI_EVENT_GROUP_MEMORY_MAP_CHANGE
This event group is notiﬁed by the system when the memory map has changed. The notiﬁcation function for this event
should not use Memory Allocation Services to avoid reentrancy complications.
EFI_EVENT_GROUP_READY_TO_BOOT
This event group is notiﬁed by the system right before notifying EFI_EVENT_GROUP_AFTER_READY_TO_BOOT
event group when the Boot Manager is about to load and execute a boot option or a platform or OS recovery option.
The event group presents the last chance to modify device or system conﬁguration prior to passing control to a boot
option.
EFI_EVENT_GROUP_AFTER_READY_TO_BOOT

option.
This event group is notiﬁed by the system immediately after notifying EFI_EVENT_GROUP_READY_TO_BOOT
The event group presents the last chance to survey device or system conﬁguration prior to passing control to a boot
option.
EFI_EVENT_GROUP_RESET_SYSTEM
This event group is notiﬁed by the system when ResetSystem() is invoked and the system is about to be reset. The
event group is only notiﬁed prior to ExitBootServices() invocation.
EFI_EVENT is deﬁned in CreateEvent .
EVT_SIGNAL_EXIT_BOOT_SERVICE and EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE are deﬁned in Cre-
ateEvent .
#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
{0x27abf055, 0xb1b8, 0x4c26, 0x80, 0x48, 0x74, 0x8f, 0x37,\
0xba, 0xa2, 0xdf}}
#define EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES \
{ 0x8be0e274, 0x3970, 0x4b44, { 0x80, 0xc5, 0x1a, 0xb9, 0x50, 0x2f, 0x3b, 0xfc } }
#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \
{0x13fa7698, 0xc831, 0x49c7, 0x87, 0xea, 0x8f, 0x43, 0xfc,\
0xc2, 0x51, 0x96}
#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \
{0x78bee926, 0x692f, 0x48fd, 0x9e, 0xdb, 0x1, 0x42, 0x2e, \
0xf0, 0xd7, 0xab}
#define EFI_EVENT_GROUP_READY_TO_BOOT \
{0x7ce88fb3, 0x4bd7, 0x4679, 0x87, 0xa8, 0xa8, 0xd8, 0xde,\
0xe5,0xd, 0x2b}
define EFI_EVENT_GROUP_AFTER_READY_TO_BOOT \
{ 0x3a2a00ad, 0x98b9, 0x4cdf, { 0xa4, 0x78, 0x70, 0x27, 0x77,
0xf1, 0xc1, 0xb } }
#define EFI_EVENT_GROUP_RESET_SYSTEM \
{ 0x62da6a56, 0x13fb, 0x485a, { 0xa8, 0xda, 0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b
} }
7.1. Event, Timer, and Task Priority Services 143Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NotifyFunction is NULL.
7.1.3 EFI_BOOT_SERVICES.CloseEvent()
Summary
Closes an event.
Prototype
typedef
(EFIAPI *EFI_CLOSE_EVENT) (
IN EFI_EVENT Event
);
Event The event to close. Type EFI_EVENT is deﬁned in the CreateEvent() function description.
The CloseEvent() function removes the caller’s reference to the event, removes it from any event group to which it
belongs, and closes it. Once the event is closed, the event is no longer valid and may not be used on any subsequent
function calls. If Event was registered with RegisterProtocolNotify() then CloseEvent() will remove the corresponding
registration. It is safe to call CloseEvent() within the corresponding notify function.
EFI_SUCCESS The event has been closed.
7.1.4 EFI_BOOT_SERVICES.SignalEvent()
Summary
Signals an event.
Prototype
typedef
(EFIAPI *EFI_SIGNAL_EVENT) (
);
7.1. Event, Timer, and Task Priority Services 144Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Event The event to signal. Type EFI_EVENT is deﬁned in the EFI_BOOT_SERVICES.CheckEvent() function de-
scription.
The supplied Event is placed in the signaled state. If Event is already in the signaled state, then EFI_SUCCESS is
returned. If Event is of type EVT_NOTIFY_SIGNAL, then the event’s notiﬁcation function is scheduled to be invoked
at the event’s notiﬁcation task priority level. SignalEvent() may be invoked from any task priority level.
If the supplied Event is a part of an event group, then all of the events in the event group are also signaled and their
notiﬁcation functions are scheduled.
When signaling an event group, it is possible to create an event in the group, signal it and then close the event to
remove it from the group. For example:
EFI_EVENT Event;
EFI_GUID gMyEventGroupGuid = EFI_MY_EVENT_GROUP_GUID;
gBS->CreateEventEx (
0,
0,
NULL,
NULL,
&gMyEventGroupGuid,
&Event
);
gBS->SignalEvent (Event);
gBS->CloseEvent (Event);
EFI_SUCCESS The event was signaled.
7.1.5 EFI_BOOT_SERVICES.WaitForEvent()
Summary
Stops execution until an event is signaled.
Prototype
typedef
(EFIAPI *EFI_WAIT_FOR_EVENT) (
IN UINTN NumberOfEvents,
IN EFI_EVENT *Event,
OUT UINTN *Index
);
NumberOfEvents The number of events in the Event array.
Event An array of EFI_EVENT. Type EFI_EVENT is deﬁned in UEFI Forum, Inc. March 2021 148
EFI_BOOT_SERVICES.CreateEvent() function description.
Index Pointer to the index of the event which satisﬁed the wait condition.
7.1. Event, Timer, and Task Priority Services 145Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function must be called at priority level TPL_APPLICATION. If an attempt is made to call it at any other priority
level, EFI_UNSUPPORTED is returned.
The list of events in the Event array are evaluated in order from ﬁrst to last, and this evaluation is repeated until an
event is signaled or an error is detected. The following checks are performed on each event in the Event array.
• If an event is of type EVT_NOTIFY_SIGNAL, then EFI_INV ALID_PARAMETER is returned and Index indi-
cates the event that caused the failure.
• If an event is in the signaled state, the signaled state is cleared and EFI_SUCCESS is returned, and Index
indicates the event that was signaled.
• If an event is not in the signaled state but does have a notiﬁcation function, the notiﬁcation function is queued at
the event’s notiﬁcation task priority level. If the execution of the event’s notiﬁcation function causes the event
to be signaled, then the signaled state is cleared, EFI_SUCCESS is returned, and Index indicates the event that
was signaled.
To wait for a speciﬁed time, a timer event must be included in the Event array.
To check if an event is signaled without waiting, an already signaled event can be used as the last event in the list being
checked, or the CheckEvent() interface may be used.
EFI_SUCCESS The event indicated by Index was signaled.
EFI_INV ALID_PARAMETER NumberOfEvents is 0.
EFI_INV ALID_PARAMETER The event indicated by Index is of type EVT_NOTIFY_SIGNAL.
EFI_UNSUPPORTED The current TPL is not TPL_APPLICATION.
7.1.6 EFI_BOOT_SERVICES.CheckEvent()
Summary
Checks whether an event is in the signaled state.
Prototype
typedef
(EFIAPI *EFI_CHECK_EVENT) (
);
Event The event to check. Type EFI_EVENT is deﬁned in the CreateEvent() function description.
The CheckEvent() function checks to see whether Event is in the signaled state. If Event is of type
EVT_NOTIFY_SIGNAL, then EFI_INV ALID_PARAMETER is returned. Otherwise, there are three possibilities:
• IfEvent is in the signaled state, it is cleared and EFI_SUCCESS is returned.
• IfEvent is not in the signaled state and has no notiﬁcation function, EFI_NOT_READY is returned.
• IfEvent is not in the signaled state but does have a notiﬁcation function, the notiﬁcation function is queued
at the event’s notiﬁcation task priority level. If the execution of the notiﬁcation function causes Event to be
signaled, then the signaled state is cleared and EFI_SUCCESS is returned; if the Event is not signaled, then
EFI_NOT_READY is returned.
7.1. Event, Timer, and Task Priority Services 146Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The event is in the signaled state.
EFI_NOT_READY The event is not in the signaled state.
EFI_INV ALID_PARAMETER Event is of type EVT_NOTIFY_SIGNAL.
7.1.7 EFI_BOOT_SERVICES.SetTimer()
Summary
Sets the type of timer and the trigger time for a timer event.
Prototype
typedef
(EFIAPI *EFI_SET_TIMER) (
IN EFI_TIMER_DELAY Type,
IN UINT64 TriggerTime
);
Event The timer event that is to be signaled at the speciﬁed time. Type EFI_EVENT is deﬁned in the CreateEvent()
function description.
Type The type of time that is speciﬁed in TriggerTime . See the timer delay types in “Related Deﬁnitions.”
TriggerTime The number of 100ns units until the timer expires. A TriggerTime of 0 is legal. If Type isTimerRelative
andTriggerTime is 0, then the timer event will be signaled on the next timer tick. If Type is TimerPeriodic and
TriggerTime is 0, then the timer event will be signaled on every timer tick.
//EFI_TIMER_DELAY
typedef enum {
TimerCancel,
TimerPeriodic,
TimerRelative
} EFI_TIMER_DELAY;
TimerCancel The event’s timer setting is to be cancelled and no timer trigger is to be set. TriggerTime is ignored

);
when canceling a timer.
TimerPeriodic The event is to be signaled periodically at TriggerTime intervals from the current time. This is the
only timer trigger Type for which the event timer does not need to be reset for each notiﬁcation. All other timer
trigger types are “one shot.”
TimerRelative The event is to be signaled in TriggerTime 100ns units.
The SetTimer() function cancels any previous time trigger setting for the event, and sets the new trigger time for the
event. This function can only be used on events of type EVT_TIMER.
7.1. Event, Timer, and Task Priority Services 147Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The event has been set to be signaled at the requested time.
EFI_INV ALID_PARAMETER Event orType is not valid.
7.1.8 EFI_BOOT_SERVICES.RaiseTPL()
Summary
Raises a task’s priority level and returns its previous level.
Prototype
typedef
EFI_TPL
(EFIAPI *EFI_RAISE_TPL) (
IN EFI_TPL NewTpl
);
NewTpl The new task priority level. It must be greater than or equal to the current task priority level. See “Related
Deﬁnitions.”
// EFI_TPL
typedef UINTN EFI_TPL
// Task Priority Levels
#define TPL_APPLICATION 4
#define TPL_CALLBACK 8
#define TPL_NOTIFY 16
#define TPL_HIGH_LEVEL 31
This function raises the priority of the currently executing task and returns its previous priority level.
Only three task priority levels are exposed outside of the ﬁrmware during boot services execution. The ﬁrst is
TPL_APPLICATION where all normal execution occurs. That level may be interrupted to perform various asyn-
chronous interrupt style notiﬁcations, which occur at the TPL_CALLBACK or TPL_NOTIFY level. By raising the
task priority level to TPL_NOTIFY such notiﬁcations are masked until the task priority level is restored, thereby
synchronizing execution with such notiﬁcations. Synchronous blocking I/O functions execute at TPL_NOTIFY .
TPL_CALLBACK is the typically used for application level notiﬁcation functions. Device drivers will typically
use TPL_CALLBACK or TPL_NOTIFY for their notiﬁcation functions. Applications and drivers may also use
TPL_NOTIFY to protect data structures in critical sections of code.
The caller must restore the task priority level with EFI_BOOT_SERVICES.RestoreTPL() to the previous level before
returning.
NOTE :IfNewTpl is below the current TPL level, then the system behavior is indeterminate .Additionally, only
TPL_APPLICATION, TPL_CALLBACK, `TPL_NOTIFY <Services%20Boot%20Services.htm#TPL_NOTIFY> `__,
and TPL_HIGH_LEVEL may be used .All other values are reserved for use by the ﬁrmware; using them will re-
sult in unpredictable behavior .Good coding practice dictates that all code should execute at its lowest possible
7.1. Event, Timer, and Task Priority Services 148Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TPL level, and the use of TPL levels above TPL_APPLICATION must be minimized .Executing at TPL levels above
TPL_APPLICATION for extended periods of time may also result in unpredictable behavior .
Unlike other UEFI interface functions, EFI_BOOT_SERVICES.RaiseTPL() does not return a status code. Instead, it
returns the previous task priority level, which is to be restored later with a matching call to RestoreTPL().
7.1.9 EFI_BOOT_SERVICES.RestoreTPL()
Summary
Restores a task’s priority level to its previous value.
Prototype
typedef
VOID
(EFIAPI *EFI_RESTORE_TPL) (
IN EFI_TPL OldTpl
)
OldTpl The previous task priority level to restore (the value from a previous, matching call to
EFI_BOOT_SERVICES.RaiseTPL() . Type EFI_TPL is deﬁned in the RaiseTPL() function description.
The RestoreTPL() function restores a task’s priority level to its previous value. Calls to RestoreTPL() are matched
with calls to RaiseTPL().
NOTE :IfOldTpl is above the current TPL level, then the system behavior is indeterminate .Additionally, only
TPL_APPLICATION, TPL_CALLBACK, TPL_NOTIFY , and TPL_HIGH_LEVEL*may be used*. All other values
are reserved for use by the ﬁrmware; using them will result in unpredictable behavior .Good coding practice dictates
that all code should execute at its lowest possible TPL level, and the use of TPL levels above TPL_APPLICATION
must be minimized .Executing at TPL levels above TPL_APPLICATION for extended periods of time may also result
in unpredictable behavior .
None.
7.2 Memory Allocation Services
The functions that make up Memory Allocation Services are used during preboot to allocate and free memory, and to
obtain the system’s memory map, below, Memory Allocation Functions .
Table 7.8: Memory Allocation Functions
AllocatePages Boot Allocates pages of a particular type.
FreePages Boot Frees allocated pages.
GetMemoryMap Boot Returns the current boot services memory map and
memory map key.
AllocatePool Boot Allocates a pool of a particular type
FreePool Boot Frees allocated pool.
7.2. Memory Allocation Services 149Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The way in which these functions are used is directly related to an important feature of UEFI memory design. This
feature, which stipulates that EFI ﬁrmware owns the system’s memory map during preboot, has three major conse-
quences:
• During preboot, all components (including executing EFI images) must cooperate with the ﬁrmware by al-
locating and freeing memory from the system with the functions EFI_BOOT_SERVICES.AllocatePages()
, EFI_BOOT_SERVICES.AllocatePool() , EFI_BOOT_SERVICES.FreePages() , and
EFI_BOOT_SERVICES.FreePool() . The ﬁrmware dynamically maintains the memory map as these
functions are called.
• During preboot, an executing EFI Image must only use the memory it has allocated.
• Before an executing EFI image exits and returns control to the ﬁrmware, it must free all resources it has explicitly
allocated. This includes all memory pages, pool allocations, open ﬁle handles, etc. Memory allocated by the
ﬁrmware to load an image is freed by the ﬁrmware when the image is unloaded.
This speciﬁcation describes numerous memory buffers that are allocated by a service, where it is the caller’s respon-
sibility to free the allocated memory. Unless stated otherwise in this speciﬁcation, it is assumed that such memory
buffers are allocated with AllocatePool() and freed with FreePool().
When memory is allocated, it is “typed” according to the values in EFI_MEMORY_TYPE (see the de-
scription for EFI_BOOT_SERVICES.AllocatePages() . Some of the types have a different usage before
EFI_BOOT_SERVICES.ExitBootServices() is called than they do afterwards . See Table, below, Memory Type Usage
before ExitBootServices() lists each type and its usage before the call; See Table Memory Type Usage after ExitBoot-
Services() lists each type and its usage after the call. The system ﬁrmware must follow the processor-speciﬁc rules
outlined in IA-32 Platforms and x64 Platforms in the layout of the EFI memory map to enable the OS to make the
required virtual mappings.
Table 7.9: Memory Type Usage before ExitBootServices()
EﬁReservedMemoryType Not usable.
EﬁLoaderCode The code portions of a loaded UEFI application.
EﬁLoaderData The data portions of a loaded UEFI application and the default data alloca-
tion type used by a UEFI application to allocate pool memory.
EﬁBootServicesCode The code portions of a loaded UEFI Boot Service Driver.
EﬁBootServicesData The data portions of a loaded UEFI Boot Serve Driver, and the default data
allocation type used by a UEFI Boot Service Driver to allocate pool mem-
ory.
EﬁRuntimeServicesCode The code portions of a loaded UEFI Runtime Driver.
EﬁRuntimeServicesData The data portions of a loaded UEFI Runtime Driver and the default data
allocation type used by a UEFI Runtime Driver to allocate pool memory.
EﬁConventionalMemory Free (unallocated) memory.
EﬁUnusableMemory Memory in which errors have been detected.
EﬁACPIReclaimMemory Memory that holds the ACPI tables.
EﬁACPIMemoryNVS Address space reserved for use by the ﬁrmware.
EﬁMemoryMappedIO Used by system ﬁrmware to request that a memory-mapped IO region be
mapped by the OS to a virtual address so it can be accessed by EFI runtime
services.
EﬁMemoryMappedIOPortSpace System memory-mapped IO region that is used to translate memory cycles
to IO cycles by the processor.
EﬁPalCode Address space reserved by the ﬁrmware for code that is part of the processor.
EﬁPersistentMemory A memory region that operates as EﬁConventionalMemory. However, it
happens to also support byte-addressable non-volatility.

services.
7.2. Memory Allocation Services 150Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 7.9 – continued from previous page
EﬁUnacceptedMemoryType A memory region that represents unaccepted memory, that must be accepted
by the boot target before it can be used. Unless otherwise noted, ll other EFI
memory types are accepted. For platforms that support unaccepted memory,
all unaccepted valid memory will be reported as unaccepted in the memory
map. Unreported physical address ranges must be treated as not-present
memory.
Note: There is only one region of type EﬁMemoryMappedIoPortSpace deﬁned in the architecture for Itanium-based
platforms. As a result, there should be one and only one region of type EﬁMemoryMappedIoPortSpace in the EFI
memory map of an Itanium-based platform .
Table 7.10: Memory Type Usage after ExitBootServices()
EﬁLoaderCode The UEFI OS Loader and/or OS may use this memory as they see ﬁt. Note:
the UEFI OS loader that called EFI_BOOT_SERVICES.ExitBootServices()
is utilizing one or more EﬁLoaderCode ranges.
EﬁLoaderData The Loader and/or OS may use this memory as they see ﬁt. Note: the OS
loader that called ExitBootServices() is utilizing one or more EﬁLoaderData
ranges.
EﬁBootServicesCode Memory available for general use.
EﬁBootServicesData Memory available for general use.
EﬁRuntimeServicesCode The memory in this range is to be preserved by the UEFI OS loader and OS
in the working and ACPI S1-S3 states.
EﬁRuntimeServicesData The memory in this range is to be preserved by the UEFI OS l loader and
OS in the working and ACPI S1-S3 states.
EﬁConventionalMemory Memory available for general use.
EﬁUnusableMemory Memory that contains errors and is not to be used.
EﬁACPIReclaimMemory This memory is to be preserved by the UEFI OS loader and OS until ACPI
is enabled. Once ACPI is enabled, the memory in this range is available for
general use.
EﬁACPIMemoryNVS This memory is to be preserved by the UEFI OS loader and OS in the work-
ing and ACPI S1-S3 states.
EﬁMemoryMappedIO This memory is not used by the OS. All system memory-mapped IO infor-
mation should come from ACPI tables.
EﬁMemoryMappedIOPortSpace This memory is not used by the OS. All system memory-mapped IO port
space information should come from ACPI tables.
EﬁPalCode This memory is to be preserved by the UEFI OS loader and OS in the work-
ing and ACPI S1-S4 states. This memory may also have other attributes that
are deﬁned by the processor implementation.
EﬁPersistentMemory A memory region that operates as EﬁConventionalMemory . However, it
by the boot target before it can be used. Unless otherwise noted, all other
EFI memory types are accepted. For platforms that support unaccepted
memory, all unaccepted valid memory will be reported as unaccepted in
the memory map. Unreported physical address ranges must be treated as
not-present memory.
NOTE :An image that calls ExitBootServices() (i.e., a UEFI OS Loader) ﬁrst calls
EFI_BOOT_SERVICES.GetMemoryMap() to obtain the current memory map. Following the ExitBootServices() call,
7.2. Memory Allocation Services 151Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
the image implicitly owns all unused memory in the map. This includes memory types EﬁLoaderCode, EﬁLoaderData,
EﬁBootServicesCode, EﬁBootServicesData, and EﬁConventionalMemory. A UEFI OS Loader and OS must preserve
the memory marked as EﬁRuntimeServicesCode andEﬁRuntimeServicesData.
7.2.1 EFI_BOOT_SERVICES.AllocatePages()
Summary
Allocates memory pages from the system.
Prototype
typedef
(EFIAPI *EFI_ALLOCATE_PAGES) (
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
IN OUT EFI_PHYSICAL_ADDRESS *Memory
);
Type The type of allocation to perform. See “Related Deﬁnitions.”
MemoryType The type of memory to allocate. The type EFI_MEMORY_TYPE is deﬁned in “Related Deﬁnitions”
below. These memory types are also described in more detail in Memory Type Usage before ExitBootServices() ,
andMemory Type Usage after ExitBootServices() . Normal allocations (that is, allocations by any UEFI ap-
plication) are of type EﬁLoaderData. MemoryType values in the range 0x70000000..0x7FFFFFFF are reserved
for OEM use. MemoryType values in the range 0x80000000..0xFFFFFFFF are reserved for use by UEFI OS
loaders that are provided by operating system vendors.
Pages The number of contiguous 4 KiB pages to allocate.
Memory Pointer to a physical address. On input, the way in which the address is used depends on the value of Type.
See “Description” for more information. On output the address is set to the base of the page range that was
allocated. See “Related Deﬁnitions.”
NOTE : UEFI Applications, UEFI Drivers, and UEFI OS Loaders must not allocate memory of types EﬁReserved-
MemoryType, EﬁMemoryMappedIO, andEﬁUnacceptedMemoryType.
//EFI_ALLOCATE_TYPE
// These types are discussed inthe "Description" section below.
AllocateAnyPages,
AllocateMaxAddress,
AllocateAddress,
MaxAllocateType
} EFI_ALLOCATE_TYPE;
//EFI_MEMORY_TYPE
// These type values are discussed inMemory Type Usage before ExitBootServices()
˓→andMemory Type Usage after ExitBootServices().
7.2. Memory Allocation Services 152Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EfiReservedMemoryType,
EfiLoaderCode,
EfiLoaderData,
EfiBootServicesCode,
EfiRuntimeServicesCode,
EfiRuntimeServicesData,
EfiConventionalMemory,
EfiUnusableMemory,
EfiACPIReclaimMemory,
EfiACPIMemoryNVS,
EfiMemoryMappedIO,
EfiMemoryMappedIOPortSpace,
EfiPalCode,
EfiPersistentMemory,
EfiUnacceptedMemoryType,
EfiMaxMemoryType
} EFI_MEMORY_TYPE;
//EFI_PHYSICAL_ADDRESS
typedef UINT64 EFI_PHYSICAL_ADDRESS;
The AllocatePages() function allocates the requested number of pages and returns a pointer to the base address of the
page range in the location referenced by Memory . The function scans the memory map to locate free pages. When it
ﬁnds a physically contiguous block of pages that is large enough and also satisﬁes the allocation requirements of Type,
it changes the memory map to indicate that the pages are now of type MemoryType .
In general, UEFI OS loaders and UEFI applications should allocate memory (and pool) of type EﬁLoaderData. UEFI
boot service drivers must allocate memory (and pool) of type EﬁBootServicesData. UREFI runtime drivers should
allocate memory (and pool) of type EﬁRuntimeServicesData (although such allocation can only be made during boot
services time).
Allocation requests of Type AllocateAnyPages allocate any available range of pages that satisﬁes the request. On
input, the address pointed to by Memory is ignored.
Allocation requests of Type AllocateMaxAddress allocate any available range of pages whose uppermost address is
less than or equal to the address pointed to by Memory on input.
Allocation requests of Type AllocateAddress allocate pages at the address pointed to by Memory on input.
NOTE :UEFI drivers and UEFI applications that are not targeted for a speciﬁc implementation must perform memory
allocations for the following runtime types using AllocateAnyPages address mode:
EfiReservedMemoryType.
EFI_SUCCESS The requested pages were allocated.
7.2. Memory Allocation Services 153Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 7.11 – continued from previous page
EFI_OUT_OF_RESOURCEST The pages could not be allocated.
EFI_INV ALID_PARAMETER Type is not AllocateAnyPages or AllocateMaxAddress or AllocateAddress
EFI_INV ALID_PARAMETER MemoryType is in the range EﬁMaxMemoryType..0x6FFFFFFF.
EFI_INV ALID_PARAMETER MemoryType is EﬁPersistentMemoryType or EﬁUnacceptedMemory.
EFI_INV ALID_PARAMETER Memory is NULL.
EFI_NOT_FOUND The requested pages could not be found.
7.2.2 EFI_BOOT_SERVICES.FreePages()
Summary
Frees memory pages.
Prototype
typedef
(EFIAPI *EFI_FREE_PAGES) (
IN EFI_PHYSICAL_ADDRESS Memory,
IN UINTN Pages
);
Memory The base physical address of the pages to be freed. Type EFI_PHYSICAL_ADDRESS is deﬁned in the
EFI_BOOT_SERVICES.AllocatePages() function description.
Pages The number of contiguous 4 KiB pages to free.
The FreePages() function returns memory allocated by AllocatePages() to the ﬁrmware.

Summary
Prototype
typedef
);
EFFI_SUCCESS The requested memory pages were freed
EFI_NOT_FOUND The requested memory pages were not allocated with AllocatePages().
EFI_INV ALID_PARAMETER Memory is not a page-aligned address or Pages is invalid.
7.2.3 EFI_BOOT_SERVICES.GetMemoryMap()
Summary
Returns the current memory map.
Prototype
typedef
(EFIAPI \ *EFI_GET_MEMORY_MAP) (
IN OUT UINTN *MemoryMapSize,
OUT EFI_MEMORY_DESCRIPTOR *MemoryMap,
OUT UINTN *MapKey,
OUT UINTN *DescriptorSize,
OUT UINT32 *DescriptorVersion
);
7.2. Memory Allocation Services 154Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
MemoryMapSize A pointer to the size, in bytes, of the MemoryMap buffer. On input, this is the size of the buffer
allocated by the caller. On output, it is the size of the buffer returned by the ﬁrmware if the buffer was large
enough, or the size of the buffer needed to contain the map if the buffer was too small.
MemoryMap A pointer to the buffer in which ﬁrmware places the current memory map. The map is an array of
EFI_MEMORY_DESCRIPTORs. See “Related Deﬁnitions.”
MapKey A pointer to the location in which ﬁrmware returns the key for the current memory map.
DescriptorSize A pointer to the location in which ﬁrmware returns the size, in bytes, of an individual
EFI_MEMORY_DESCRIPTOR.
DescriptorVersion A pointer to the location in which ﬁrmware returns the version number associated with the
EFI_MEMORY_DESCRIPTOR. See “Related Deﬁnitions.”
..code-block:
//EFI_MEMORY_DESCRIPTOR
UINT32 Type;
EFI_PHYSICAL_ADDRESS PhysicalStart;
EFI_VIRTUAL_ADDRESS VirtualStart;
UINT64 NumberOfPages;
UINT64 Attribute;
} EFI_MEMORY_DESCRIPTOR;
Type Type of the memory region. Type EFI_MEMORY_TYPE is deﬁned in the
PhysicalStart Physical address of the ﬁrst byte in the memory region. PhysicalStart must be aligned on a 4 KiB
boundary, and must not be above 0xfffffffffffff000. Type EFI_PHYSICAL_ADDRESS is deﬁned in the Allo-
catePages() function description.
VirtualStart Virtual address of the ﬁrst byte in the memory region. VirtualStart must be aligned on a 4 KiB boundary,
and must not be above 0xfffffffffffff000. Type EFI_VIRTUAL_ADDRESS is deﬁned in “Related Deﬁnitions.”
NumberOfPages Number of 4 KiB pages in the memory region. NumberOfPages must not be 0, and must not be any
value that would represent a memory page with a start address, either physical or virtual, above 0xfffffffffffff000
Attribute Attributes of the memory region that describe the bit mask of capabilities for that memory region, and not
necessarily the current settings for that memory region. See the following “Memory Attribute Deﬁnitions.”
// Memory Attribute Definitions
// These types can be "ORed" together asneeded.
#define EFI_MEMORY_UC 0x0000000000000001
#define EFI_MEMORY_WC 0x0000000000000002
#define EFI_MEMORY_WT 0x0000000000000004
#define EFI_MEMORY_WB 0x0000000000000008
#define EFI_MEMORY_UCE 0x0000000000000010
#define EFI_MEMORY_WP 0x0000000000001000
#define EFI_MEMORY_RP 0x0000000000002000
#define EFI_MEMORY_XP 0x0000000000004000
#define EFI_MEMORY_NV 0x0000000000008000
7.2. Memory Allocation Services 155Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_MEMORY_MORE_RELIABLE 0x0000000000010000
#define EFI_MEMORY_RO 0x0000000000020000
#define EFI_MEMORY_SP 0x0000000000040000
#define EFI_MEMORY_CPU_CRYPTO 0x0000000000080000
#define EFI_MEMORY_RUNTIME 0x8000000000000000
#define EFI_MEMORY_ISA_VALID 0x4000000000000000
#define EFI_MEMORY_ISA_MASK 0x0FFFF00000000000
EFI_MEMORY_UC Memory cacheability attribute: The memory region supports being conﬁgured as not
cacheable.
EFI_MEMORY_WC Memory cacheability attribute: The memory region supports being conﬁgured as write com-
bining.
EFI_MEMORY_WT Memory cacheability attribute: The memory region supports being conﬁgured as cacheable
with a “write through” policy. Writes that hit in the cache will also be written to main memory.
EFI_MEMORY_WB Memory cacheability attribute: The memory region supports being conﬁgured as cacheable
with a “write back” policy. Reads and writes that hit in the cache do not propagate to main memory. Dirty data
is written back to main memory when a new cache line is allocated.
EFI_MEMORY_UCE Memory cacheability attribute: The memory region supports being conﬁgured as not
cacheable, exported, and supports the “fetch and add” semaphore mechanism.
EFI_MEMORY_WP Physical memory protection attribute: The memory region supports being conﬁgured as write-
protected by system hardware. This is typically used as a cacheability attribute today. The memory region
supports being conﬁgured as cacheable with a “write protected” policy. Reads come from cache lines when
possible, and read misses cause cache ﬁlls. Writes are propagated to the system bus and cause corresponding
cache lines on all processors on the bus to be invalidated.
EFI_MEMORY_RP Physical memory protection attribute: The memory region supports being conﬁgured as read-
protected by system hardware.
EFI_MEMORY_XP Physical memory protection attribute: The memory region supports being conﬁgured so it is
protected by system hardware from executing code.
EFI_MEMORY_NV Runtime memory attribute: The memory region refers to persistent memory
EFI_MEMORY_MORE_RELIABLE The memory region provides higher reliability relative to other memory in
the system. If all memory has the same reliability, then this bit is not used.
EFI_MEMORY_RO Physical memory protection attribute: The memory region supports making this memory range
read-only by system hardware.
EFI_MEMORY_SP Speciﬁc-purpose memory (SPM). The memory is earmarked for speciﬁc purposes such as for
speciﬁc device drivers or applications. The SPM attribute serves as a hint to the OS to avoid allocating this
memory for core OS data or code that can not be relocated. Prolonged use of this memory for purposes other
than the intended purpose may result in suboptimal platform performance.
EFI_MEMORY_CPU_CRYPTO If this ﬂag is set, the memory region is capable of being protected with the CPU’s
memory cryptographic capabilities. If this ﬂag is clear, the memory region is not capable of being protected
with the CPU’s memory cryptographic capabilities or the CPU does not support CPU memory cryptographic
EFI_MEMORY_RUNTIME Runtime memory attribute: The memory region needs to be given a virtual mapping
by the operating system when SetVirtualAddressMap() is called (described in Virtual Memory Services .
EFI_MEMORY_ISA_V ALID If this ﬂag is set, the memory region is described with additional ISA-speciﬁc mem-
ory attributes as speciﬁed in EFI_MEMORY_ISA_MASK .
7.2. Memory Allocation Services 156Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_MEMORY_ISA_MASK Deﬁnes the bits reserved for describing optional ISA-speciﬁc cacheability attributes
that are not covered by the standard UEFI Memory Attributes cacheability bits (EFI_MEMORY_UC,
EFI_MEMORY_WC, EFI_MEMORY_WT, EFI_MEMORY_WB and EFI_MEMORY_UCE). See Calling
Conventions for further ISA-speciﬁc enumeration of these bits.
Note: UEFI Speciﬁcation 2.5 and following use EFI_MEMORY_RO as rite-protected physical memory protection
attribute. Also, EFI_MEMORY_WP means cacheability attribute.
//EFI_VIRTUAL_ADDRESS
typedef UINT64 EFI_VIRTUAL_ADDRESS;
// Memory Descriptor Version Number
#define EFI_MEMORY_DESCRIPTOR_VERSION 1
The GetMemoryMap() function returns a copy of the current memory map. The map is an array of memory de-
scriptors, each of which describes a contiguous block of memory. The map describes all of memory, no mat-
ter how it is being used. That is, it includes blocks allocated by EFI_BOOT_SERVICES.AllocatePages() and
EFI_BOOT_SERVICES.AllocatePool() , as well as blocks that the ﬁrmware is using for its own purposes. The memory
map is only used to describe memory that is present in the system. The ﬁrmware does not return a range description
for address space regions that are not backed by physical hardware. Regions that are backed by physical hardware, but
are not supposed to be accessed by the OS, must be returned as EﬁReservedMemoryType. The OS may use addresses
of memory ranges that are not described in the memory map at its own discretion.
Until EFI_BOOT_SERVICES.ExitBootServices() is called, the memory map is owned by the ﬁrmware and the cur-
rently executing UEFI Image should only use memory pages it has explicitly allocated.

If the MemoryMap buffer is too small, the EFI_BUFFER_TOO_SMALL error code is returned and the MemoryMap-
Size value contains the size of the buffer needed to contain the current memory map. The actual size of the buffer
allocated for the consequent call to GetMemoryMap() should be bigger then the value returned in MemoryMapSize,
since allocation of the new buffer may potentially increase memory map size.
On success a MapKey is returned that identiﬁes the current memory map. The ﬁrmware’s key is changed every time
something in the memory map changes. In order to successfully invoke EFI_BOOT_SERVICES.ExitBootServices()
the caller must provide the current memory map key.
The GetMemoryMap() function also returns the size and revision number of the EFI_MEMORY_DESCRIPTOR. The
DescriptorSize represents the size in bytes of an EFI_MEMORY_DESCRIPTOR array element returned in Mem-
oryMap. The size is returned to allow for future expansion of the EFI_MEMORY_DESCRIPTOR in response to
hardware innovation. The structure of the EFI_MEMORY_DESCRIPTOR may be extended in the future but it will
remain backwards compatible with the current deﬁnition. Thus OS software must use the DescriptorSize to ﬁnd the
start of each EFI_MEMORY_DESCRIPTOR in the MemoryMap array.
EFI_SUCCESS The memory map was returned in the MemoryMap buffer.
EFI_BUFFER_TOO_SMALL The MemoryMap buffer was too small. Thecurrent buffer size needed to
hold the memory map is returned in MemoryMapSize .
EFI_INV ALID_PARAMETER MemoryMapSize is NULL.
EFI_INV ALID_PARAMETER TheMemoryMap buffer is not too small and MemoryMap is NULL.
7.2. Memory Allocation Services 157Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.2.4 EFI_BOOT_SERVICES.AllocatePool()
Summary
Allocates pool memory.
Prototype
typedef
(EFIAPI *EFI_ALLOCATE_POOL) (
IN EFI_MEMORY_TYPE PoolType,
IN UINTN Size,
OUT VOID **Buffer
);
PoolType The type of pool to allocate. Type EFI_MEMORY_TYPE is deﬁned in the
EFI_BOOT_SERVICES.AllocatePages() function description. PoolType values in the range
0x70000000..0x7FFFFFFF are reserved for OEM use. PoolType values in the range 0x80000000..0xFFFFFFFF
are reserved for use by UEFI OS loaders that are provided by operating system vendors.
Size The number of bytes to allocate from the pool.
Buffer A pointer to a pointer to the allocated buffer if the call succeeds; undeﬁned otherwise.
Note: UEFI applications and UEFI drivers must not allocate memory of type EﬁReservedMemoryType.
The AllocatePool() function allocates a memory region of Size bytes from memory of type PoolType and returns the
address of the allocated memory in the location referenced by Buffer . This function allocates pages from EﬁConven-
tionalMemory as needed to grow the requested pool type. All allocations are eight-byte aligned.
The allocated pool memory is returned to the available pool with the EFI_BOOT_SERVICES.FreePool() function.
EFI_SUCCESS The requested number of bytes was allocated.
EFI_OUT_OF_RESOURCES The pool requested could not be allocated.
EFI_INV ALID_PARAMETER PoolType is in the range EﬁMaxMemoryType..0x6FFFFFFF.
EFI_INV ALID_PARAMETER PoolType is EﬁPersistentMemory.
EFI_INV ALID_PARAMETER Buffer is NULL.
7.2.5 EFI_BOOT_SERVICES.FreePool()
Summary
Returns pool memory to the system.
Prototype
typedef
(EFIAPI *EFI_FREE_POOL) (
IN VOID *Buffer
);
7.2. Memory Allocation Services 158Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Buffer Pointer to the buffer to free.
The FreePool() function returns the memory speciﬁed by Buffer to the system. On return, the memory’s type is
EﬁConventionalMemory. The Buffer that is freed must have been allocated by AllocatePool().
EFI_SUCCESS The memory was returned to the system.
EFI_INV ALID_PARAMETER Buffer was invalid.
7.3 Protocol Handler Services
In the abstract, a protocol consists of a 128-bit globally unique identiﬁer (GUID) and a Protocol Interface structure.
The structure contains the functions and instance data that are used to access a device. The functions that make up
Protocol Handler Services allow applications to install a protocol on a handle, identify the handles that support a given
protocol, determine whether a handle supports a given protocol, and so forth. See the Table, below.
Table 7.14: Protocol Interface Functions
InstallProtocolInterface Boot Installs a protocol interface on a device handle.
UninstallProtocolInterface Boot Removes a protocol interface from a device handle.
ReinstallProtocolInterface Boot Reinstalls a protocolinterface on a device handle.
RegisterProtocolNotify Boot Registers an event that is to be signaled whenever an interface is
installed for a speciﬁed protocol.
LocateHandle Boot Returns an array of handles that support a speciﬁed protocol.
HandleProtocol Boot Queries a handle to determine if it supports a speciﬁed protocol.
LocateDevicePath Boot Locates all devices on a device path that support a speciﬁed protocol
and returns the handle to the device that is closest to the path.
OpenProtocol Boot Adds elements to the list of agents consuming a protocol interface.
CloseProtocol Boot Removes elements from the list of agents consuming a protocol in-
terface.
OpenProtocolInformation Boot Retrieve the list of agents that are currently consuming a protocol
interface.
ConnectController Boot Uses a set of precedence rules to ﬁnd the best set of drivers to man-
age a controller.
DisconnectController Boot Informs a set of drivers to stop managing a controller.
ProtocolsPerHandle Boot Retrieves the list of protocols installed on a handle. The return
LocateHandleBuffer Boot Retrieves the list of handles from the handle database that meet the
search criteria. The return buffer is automatically allocated.
LocateProtocol Boot Finds the ﬁrst handle in the handle database the supports the re-
quested protocol.
InstallMultipleProtocolInterfaces Boot Installs one or more protocol interfaces onto a handle.
UninstallMultipleProtocolInterfaces Boot Uninstalls one or more protocol interfaces from a handle.
The Protocol Handler boot services have been modiﬁed to take advantage of the information that is now being tracked
with the EFI_BOOT_SERVICES.OpenProtocol() andEFI_BOOT_SERVICES.CloseProtocol() . Since the usage of
protocol interfaces is being tracked with these new boot services, it is now possible to safely uninstall and reinstall
protocol interfaces that are being consumed by UEFI drivers.
7.3. Protocol Handler Services 159Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
As depicted in Figure 7-1 (below) the ﬁrmware is responsible for maintaining a “data base” that shows which
protocols are attached to each device handle. (The ﬁgure depicts the “data base” as a linked list, but the
choice of data structure is implementation-dependent.) The “data base” is built dynamically by calling the
EFI_BOOT_SERVICES.InstallProtocolInterface() function. Protocols can only be installed by UEFI drivers or the
ﬁrmware itself. In the ﬁgure, a device handle ( EFI_HANDLE) refers to a list of one or more registered protocol
interfaces for that handle. The ﬁrst handle in the system has four attached protocols, and the second handle has two
attached protocols. Each attached protocol is represented as a GUID/Interface pointer pair. The GUID is the name of
the protocol, and Interface points to a protocol instance. This data structure will typically contain a list of interface
functions, and some amount of instance data.
Access to devices is initiated by calling the EFI_BOOT_SERVICES.HandleProtocol() function, which determines
whether a handle supports a given protocol. If it does, a pointer to the matching Protocol Interface structure is returned.
When a protocol is added to the system, it may either be added to an existing device handle or it may be added to
create a new device handle. See Figure 7-1 (below) shows that protocol handlers are listed for each device handle and
that each protocol handler is logically a UEFI driver.
Fig. 7.1: Device Handle to Protocol Handler Mapping
The ability to add new protocol interfaces as new handles or to layer them on existing interfaces provides great
ﬂexibility. Layering makes it possible to add a new protocol that builds on a device’s basic protocols. An example
of this might be to layer on a EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL support that would build on the handle’s
underlyin EFI_SERIAL_IO_PROTOCOL .
The ability to add new handles can be used to generate new devices as they are found, or even to generate abstract
devices. An example of this might be to add a multiplexing device that replaces ConsoleOut with a virtual device that
multiplexes the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL protocol onto multiple underlying device handles.
7.3. Protocol Handler Services 160Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

7.3.1 Driver Model Boot Services
Following is a detailed description of the new UEFI boot services that are required by the UEFI Driver Model . These
boot services are being added to reduce the size and complexity of the bus drivers and device drivers. This, in turn,
will reduce the amount of ROM space required by drivers that are programmed into ROMs on adapters or into system
FLASH, and reduce the development and testing time required by driver writers.
These new services fall into two categories. The ﬁrst group is used to track the usage of protocol interfaces by
different agents in the system. Protocol interfaces are stored in a handle database. The handle database con-
sists of a list of handles, and on each handle there is a list of one or more protocol interfaces. The boot ser-
vices EFI_BOOT_SERVICES.InstallProtocolInterface() ,EFI_BOOT_SERVICES.UninstallProtocolInterface() and
EFI_BOOT_SERVICES.ReinstallProtocolInterface() are used to add, remove, and replace protocol interfaces in the
handle database. The boot service EFI_BOOT_SERVICES.HandleProtocol() is used to look up a protocol interface
in the handle database. However, agents that call HandleProtocol() are not tracked, so it is not safe to call Uninstall-
ProtocolInterface() orReinstallProtocolInterface() because an agent may be using the protocol interface that is being
removed or replaced.
The solution is to track the usage of protocol interfaces in the handle database itself. To accomplish this, each protocol
interface includes a list of agents that are consuming the protocol interface. Figure 7-2 (below) shows an example
handle database with these new agent lists. An agent consists of an image handle, a controller handle, and some
attributes. The image handle identiﬁes the driver or application that is consuming the protocol interface. The controller
handle identiﬁes the controller that is consuming the protocol interface. Since a driver may manage more than one
controller, the combination of a driver’s image handle and a controller’s controller handle uniquely identiﬁes the agent
that is consuming the protocol interface. The attributes show how the protocol interface is being used.
Fig. 7.2: Handle Database
In order to maintain these agent lists in the handle database, some new boot services are re-
7.3. Protocol Handler Services 161Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
quired. These are EFI_BOOT_SERVICES.OpenProtocol() ,EFI_BOOT_SERVICES.CloseProtocol() , and
EFI_BOOT_SERVICES.OpenProtocolInformation() .OpenProtocol() adds elements to the list of agents consum-
ing a protocol interface. CloseProtocol() removes elements from the list of agents consuming a protocol interface,
andEFI_BOOT_SERVICES.OpenProtocolInformation() retrieves the entire list of agents that are currently using a
protocol interface.
The second group of boot services is used to deterministically connect and disconnect drivers to
controllers. The boot services in this group are EFI_BOOT_SERVICES.ConnectController() and
EFI_BOOT_SERVICES.DisconnectController() . These services take advantage of the new features of the
handle database along with the new protocols described in this document to manage the drivers and controllers present
in the system. ConnectController() uses a set of strict precedence rules to ﬁnd the best set of drivers for a controller.
This provides a deterministic matching of drivers to controllers with extensibility mechanisms for OEMs, IBVs, and
IHVs. DisconnectController() allows drivers to be disconnected from controllers in a controlled manner, and by using
the new features of the handle database it is possible to fail a disconnect request because a protocol interface cannot
be released at the time of the disconnect request.
The third group of boot services is designed to help simplify the implementation of drivers, and produce
drivers with smaller executable footprints. The EFI_BOOT_SERVICES.LocateHandleBuffer() is a new ver-
sion of EFI_BOOT_SERVICES.LocateHandle() that allocates the required buffer for the caller. This elim-
inates two calls to LocateHandle() and a call to EFI_BOOT_SERVICES.AllocatePool() from the caller’s
code. EFI_BOOT_SERVICES.LocateProtocol() searches the handle database for the ﬁrst protocol in-
stance that matches the search criteria. The EFI_BOOT_SERVICES.InstallMultipleProtocolInterfaces() and
EFI_BOOT_SERVICES.UninstallMultipleProtocolInterfaces() are very useful to driver writers. These boot services
allow one or more protocol interfaces to be added or removed from a handle. In addition, InstallMultipleProtocolInter-
faces() guarantees that a duplicate device path is never added to the handle database. This is very useful to bus drivers
that can create one child handle at a time, because it guarantees that the bus driver will not inadvertently create two
instances of the same child handle.
7.3.2 EFI_BOOT_SERVICES.InstallProtocolInterface()
Summary
Installs a protocol interface on a device handle. If the handle does not exist, it is created and added to the list of handles
in the system. InstallMultipleProtocolInterfaces() performs more error checking than InstallProtocolInterface(), so it
is recommended that InstallMultipleProtocolInterfaces() be used in place of InstallProtocolInterface()
Prototype
typedef
(EFIAPI *EFI_INSTALL_PROTOCOL_INTERFACE) (
IN OUT EFI_HANDLE *Handle,
IN EFI_GUID *Protocol,
IN EFI_INTERFACE_TYPE InterfaceType,
IN VOID *Interface
);
Handle A pointer to the EFI_HANDLE on which the interface is to be installed. If * Handle is NULL on input, a
new handle is created and returned on output. If * Handle is not NULL on input, the protocol is added to the
handle, and the handle is returned unmodiﬁed. The type EFI_HANDLE is deﬁned in “Related Deﬁnitions.” If *
Handle is not a valid handle, then EFI_INV ALID_PARAMETER is returned.
Protocol The numeric ID of the protocol interface. The type EFI_GUID is deﬁned in “Related Deﬁnitions.” It is the
caller’s responsibility to pass in a valid GUID. For a description of valid GUID values, see “Links to UEFI-
Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “RFC 4122”.
7.3. Protocol Handler Services 162Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
InterfaceType Indicates whether Interface is supplied in native form. This value indicates the original execution
environment of the request. See “Related Deﬁnitions.”
Interface A pointer to the protocol interface. The Interface must adhere to the structure deﬁned by Protocol . NULL
can be used if a structure is not associated with Protocol .
//EFI_HANDLE
typedef VOID *EFI_HANDLE;
//EFI_GUID
UINT32 Data1;
UINT16 Data2;
UINT16 Data3;
UINT8 Data4[8];
} EFI_GUID;
//EFI_INTERFACE_TYPE
EFI_NATIVE_INTERFACE
} EFI_INTERFACE_TYPE;
The InstallProtocolInterface() function installs a protocol interface (a GUID/Protocol Interface structure pair) on a
device handle. The same GUID cannot be installed more than once onto the same handle. If installation of a duplicate
GUID on a handle is attempted, an EFI_INV ALID_PARAMETER will result.
Installing a protocol interface allows other components to locate the Handle, and the interfaces installed on it.
When a protocol interface is installed, the ﬁrmware calls all notiﬁcation functions that have registered to wait for
the installation of Protocol. For more information, see the EFI_BOOT_SERVICES.RegisterProtocolNotify() function
description.
EFI_SUCCESS The protocol interface was installed.
EFI_OUT_OF_RESOURCES Space for a new handle could not be allocated.
EFI_INV ALID_PARAMETER HandLe is NULL
EFI_INV ALID_PARAMETER ProtocoL is NULL.
EFI_INV ALID_PARAMETER InterfaceType is not EFI_NATIVE_INTERFACE.
EFI_INV ALID_PARAMETER ProtocoL is already installed on the handle speciﬁed by HandLe .
7.3. Protocol Handler Services 163Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.3.3 EFI_BOOT_SERVICES.UninstallProtocolInterface()
Summary
Removes a protocol interface from a device handle. It is recommended that UninstallMultipleProtocolInterfaces() be
used in place of UninstallProtocolInterface().
Prototype
typedef
(EFIAPI *EFI_UNINSTALL_PROTOCOL_INTERFACE) (
IN EFI_HANDLE Handle,
);
Handle The handle on which the interface was installed. If Handle is not a valid han-
dle, then EFI_INV ALID_PARAMETER is returned. Type EFI_HANDLE is deﬁned in the
EFI_BOOT_SERVICES.InstallProtocolInterface() function description.

Summary
Prototype
typedef
);
Protocol The numeric ID of the interface. It is the caller’s responsibility to pass in a valid GUID. For a description
of valid GUID values, see “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “RFC
4122”. Type EFI_GUID is deﬁned in the EFI_BOOT_SERVICES.InstallProtocolInterface() function descrip-
tion.
Interface A pointer to the interface. NULL can be used if a structure is not associated with Protocol.
The UninstallProtocolInterface() function removes a protocol interface from the handle on which it was previously
installed. The Protocol and Interface values deﬁne the protocol interface to remove from the handle.
The caller is responsible for ensuring that there are no references to a protocol interface that has been removed. In
some cases, outstanding reference information is not available in the protocol, so the protocol, once added, cannot be
removed. Examples include Console I/O, Block I/O, Disk I/O, and (in general) handles to device protocols.
If the last protocol interface is removed from a handle, the handle is freed and is no longer valid.
EFI 1.10 Extension
The extension to this service directly addresses the limitations described in the section above. There may be some
drivers that are currently consuming the protocol interface that needs to be uninstalled, so it may be dangerous to just
blindly remove a protocol interface from the system. Since the usage of protocol interfaces is now being tracked for
components that use the EFI_BOOT_SERVICES.OpenProtocol() andEFI_BOOT_SERVICES.CloseProtocol() . boot
services, a safe version of this function can be implemented. Before the protocol interface is removed, an attempt is
made to force all the drivers that are consuming the protocol interface to stop consuming that protocol interface. This
is done by calling EFI_BOOT_SERVICES.DisconnectController() for the driver that currently have the protocol inter-
face open with an attribute of EFI_OPEN_PROTOCOL_BY_DRIVER or EFI_OPEN_PROTOCOL_BY_DRIVER |
EFI_OPEN_PROTOCOL_EXCLUSIVE.
If the disconnect succeeds, then those agents will have called the boot service EFI_BOOT_SERVICES.CloseProtocol()
to release the protocol interface. Lastly, all of the agents that have the protocol interface open with an at-
tribute of EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL, EFI_OPEN_PROTOCOL_GET_PROTOCOL, or
EFI_OPEN_PROTOCOL_TEST_PROTOCOL are closed. If there are any agents remaining that still have the pro-
tocol interface open, the protocol interface is not removed from the handle and EFI_ACCESS_DENIED is returned.
In addition, all of the drivers that were disconnected with the boot service DisconnectController() earlier, are recon-
nected with the boot service EFI_BOOT_SERVICES.ConnectController() . If there are no agents remaining that are
consuming the protocol interface, then the protocol interface is removed from the handle as described above.
7.3. Protocol Handler Services 164Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The interface was removed.
EFI_NOT_FOUND The interface was not found.
EFI_ACCESS_DENIED The interface was not removed because the interface is still being used by a
driver.
EFI_INV ALID_PARAMETER HandLe is NULL.
7.3.4 EFI_BOOT_SERVICES.ReinstallProtocolInterface()
Summary
Reinstalls a protocol interface on a device handle.
Prototype
typedef
(EFIAPI *EFI_REINSTALL_PROTOCOL_INTERFACE) (
IN VOID *OldInterface,
IN VOID *NewInterface
);
Handle Handle on which the interface is to be reinstalled. If Handle is not a valid han-
4122”. Type EFI_GUID is deﬁned in the InstallProtocolInterface() function description.
OldInterface A pointer to the old interface. NULL can be used if a structure is not associated with Protocol.
NewInterface A pointer to the new interface. NULL can be used if a structure is not associated with Protocol.
The ReinstallProtocolInterface() function reinstalls a protocol interface on a device handle. The OldInterface for
Protocol is replaced by the NewInterface . NewInterface may be the same as OldInterface . If it is, the registered
protocol notiﬁes occur for the handle without replacing the interface on the handle.
As with InstallProtocolInterface(), any process that has registered to wait for the installation of the interface is notiﬁed.
The caller is responsible for ensuring that there are no references to the OldInterface that is being removed.
The extension to this service directly addresses the limitations described in the section above. There may be some num-
ber of drivers currently consuming the protocol interface that is being reinstalled. In this case, it may be dangerous to
replace a protocol interface in the system. It could result in an unstable state, because a driver may attempt to use the old
protocol interface after a new one has been reinstalled. Since the usage of protocol interfaces is now being tracked for
components that use the EFI_BOOT_SERVICES.OpenProtocol() andEFI_BOOT_SERVICES.CloseProtocol() boot
services, a safe version of this function can be implemented.
7.3. Protocol Handler Services 165Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
When this function is called, a call is ﬁrst made to the boot service UninstallProtocolInterface(). This will guaran-
tee that all of the agents are currently consuming the protocol interface OldInterface will stop using OldInterface.
If UninstallProtocolInterface() returns EFI_ACCESS_DENIED, then this function returns EFI_ACCESS_DENIED,
OldInterface remains on Handle, and the protocol notiﬁes are not processed because NewInterface was never installed.
If UninstallProtocolInterface() succeeds, then a call is made to the boot service
EFI_BOOT_SERVICES.InstallProtocolInterface() to put the NewInterface onto Handle.
Finally, the boot service EFI_BOOT_SERVICES.ConnectController() is called so all agents that were forced to re-
lease OldInterface with UninstallProtocolInterface() can now consume the protocol interface NewInterface that was
installed with InstallProtocolInterface(). After OldInterface has been replaced with NewInterface, any process that has
registered to wait for the installation of the interface is notiﬁed.
EFI_SUCCESS The protocol interface was reinstalled.
EFI_NOT_FOUND The OldInterface on the handle was not found.
EFI_ACCESS_DENIED The protocol interface could not be reinstalled, because OldInterface is still
being used by a driver that will not release it.
7.3.5 EFI_BOOT_SERVICES.RegisterProtocolNotify()
Summary
Creates an event that is to be signaled whenever an interface is installed for a speciﬁed protocol.
Prototype
typedef
(EFIAPI *EFI_REGISTER_PROTOCOL_NOTIFY) (
OUT VOID **Registration
);
Protocol The numeric ID of the protocol for which the event is to be registered. Type EFI_GUID is deﬁned in the
Event Event that is to be signaled whenever a protocol interface is registered for Protocol. The type EFI_EVENT is
deﬁned in the CreateEvent() function description. The same EFI_EVENT may be used for multiple protocol
notify registrations.
Registration A pointer to a memory location to receive the registration value. This value must be saved and used
by the notiﬁcation function of Event to retrieve the list of handles that have added a protocol interface of type
Protocol.
The RegisterProtocolNotify() function creates an event that is to be signaled whenever a protocol interface is installed
for Protocol by InstallProtocolInterface() or EFI_BOOT_SERVICES.ReinstallProtocolInterface() .
Once Event has been signaled, the EFI_BOOT_SERVICES.LocateHandle() function can be called to iden-
tify the newly installed, or reinstalled, handles that support Protocol. The Registration parameter in
7.3. Protocol Handler Services 166Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_BOOT_SERVICES.RegisterProtocolNotify() corresponds to the SearchKey parameter in LocateHandle(). Note
that the same handle may be returned multiple times if the handle reinstalls the target protocol ID multiple times. This
is typical for removable media devices, because when such a device reappears, it will reinstall the Block I/O protocol

Protocol.
to indicate that the device needs to be checked again. In response, layered Disk I/O and Simple File System protocols
may then reinstall their protocols to indicate that they can be re-checked, and so forth.
Events that have been registered for protocol interface notiﬁcation can be unregistered by calling CloseEvent().
EFI_SUCCESS The notiﬁcation event has been registered.
EFI_OUT_OF_RESOURCES Space for the notiﬁcation event could not be allocated.
EFI_INV ALID_PARAMETER Protocol is NULL.
EFI_INV ALID_PARAMETER Registration is NULL.
7.3.6 EFI_BOOT_SERVICES.LocateHandle()
Summary
Returns an array of handles that support a speciﬁed protocol.
Prototype
typedef
(EFIAPI *EFI_LOCATE_HANDLE) (
IN EFI_LOCATE_SEARCH_TYPE SearchType,
IN EFI_GUID *Protocol OPTIONAL,
IN VOID *SearchKey OPTIONAL,
IN OUT UINTN *BufferSize,
OUT EFI_HANDLE *Buffer
);
SearchType Speciﬁes which handle(s) are to be returned. Type EFI_LOCATE_SEARCH_TYPE is deﬁned in “Re-
lated Deﬁnitions.”
Protocol Speciﬁes the protocol to search by. This parameter is only valid if SearchType is ByProtocol . Type
EFI_GUID is deﬁned in the EFI_BOOT_SERVICES.InstallProtocolInterface() function description.
SearchKey Speciﬁes the search key. This parameter is ignored if SearchType is AllHandles orByProtocol .
If SearchType is ByRegisterNotify , the parameter must be the Registration value returned by function
EFI_BOOT_SERVICES.RegisterProtocolNotify() .
BufferSize On input, the size in bytes of Buffer. On output, the size in bytes of the array returned in*Buffer*(if the
buffer was large enough) or the size, in bytes, of the buffer needed to obtain the array (if the buffer was not large
enough).
Buffer The buffer in which the array is returned. Type EFI_HANDLE is deﬁned in the InstallProtocolInterface()
// EFI_LOCATE_SEARCH_TYPE
7.3. Protocol Handler Services 167Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
AllHandles,
ByRegisterNotify,
ByProtocol
} EFI_LOCATE_SEARCH_TYPE;
AllHandles Protocol and SearchKey are ignored and the function returns an array of every handle in the system.
ByRegisterNotify SearchKey supplies the Registration value returned by EFI_BOOT_SERVICES.RegisterProtocolNotify()
. The function returns the next handle that is new for the registration. Only one handle is returned at a time,
starting with the ﬁrst, and the caller must loop until no more handles are returned. Protocol is ignored for this
search type.
ByProtocol All handles that support Protocol are returned. SearchKey is ignored for this search type.
The LocateHandle() function returns an array of handles that match the SearchType request. If the input value of
BufferSize is too small, the function returns EFI_BUFFER_TOO_SMALL and updates BufferSize to the size of the
buffer needed to obtain the array.
EFI_SUCCESS The array of handles was returned.
EFI_NOT_FOUND No handles match the search.
EFI_BUFFER_TOO_SMALL TheBufferSize is too small for the result. BufferSize has been updated with
the size needed to complete the request.
EFI_INV ALID_PARAMETER SearchType is not a member of EFI_LOCATE_SEARCH_TYPE.
EFI_INV ALID_PARAMETER SearchType is ByRegisterNotify and SearchKey is NULL.
EFI_INV ALID_PARAMETER SearchType is ByProtocol and ProtocoL is NULL.
EFI_INV ALID_PARAMETER One or more matches are found and BufferSize is NULL.
EFI_INV ALID_PARAMETER BufferSize is large enough for the result and Buffer is NULL.
7.3.7 EFI_BOOT_SERVICES.HandleProtocol()
Summary
Queries a handle to determine if it supports a speciﬁed protocol.
Prototype
typedef
(EFIAPI *EFI_HANDLE_PROTOCOL) (
OUT VOID **Interface
);
Handle The handle being queried. If Handle is NULL, then EFI_INV ALID_PARAMETER is returned. Type
EFI_HANDLE is deﬁned in the EFI_BOOT_SERVICES.InstallProtocolInterface() function description.
Protocol The published unique identiﬁer of the protocol. It is the caller’s responsibility to pass in a valid GUID.
For a description of valid GUID values, see “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the
heading “RFC 4122”. Type EFI_GUID is deﬁned in the InstallProtocolInterface() function description.
7.3. Protocol Handler Services 168Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Interface Supplies the address where a pointer to the corresponding Protocol Interface is returned. NULL will be
returned in * Interface if a structure is not associated with Protocol .
The HandleProtocol() function queries Handle to determine if it supports Protocol . If it does, then on return Interface
points to a pointer to the corresponding Protocol Interface. Interface can then be passed to any protocol service to
identify the context of the request.
The HandleProtocol() function is still available for use by old EFI applications and drivers. However, all new appli-
cations and drivers should use EFI_BOOT_SERVICES.OpenProtocol() in place of HandleProtocol(). The following
code fragment shows a possible implementation of HandleProtocol() using OpenProtocol(). The variable EﬁCoreIm-
ageHandle is the image handle of the EFI core.
HandleProtocol (
)
{
returnOpenProtocol (
Handle,
Protocol,
Interface,
EfiCoreImageHandle,
NULL,
EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL
);
}
EFI_SUCCESS The interface information for the speciﬁed protocol was returned.
EFI_UNSUPPORTED The device does not support the speciﬁed protocol.
EFI_INV ALID_PARAMETER Handle is NULL.
EFI_INV ALID_PARAMETER Interface is NULL.
7.3.8 EFI_BOOT_SERVICES.LocateDevicePath()
Summary
Locates the handle to a device on the device path that supports the speciﬁed protocol.
Prototype
typedef
(EFIAPI *EFI_LOCATE_DEVICE_PATH) (
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,
OUT EFI_HANDLE *Device
);
7.3. Protocol Handler Services 169Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Protocol The protocol to search for. Type EFI_GUID is deﬁned in the
DevicePath On input, a pointer to a pointer to the device path. On output, the device path pointer is modi-
ﬁed to point to the remaining part of the device path–that is, when the function ﬁnds the closest handle,
it splits the device path into two parts, stripping off the front part, and returning the remaining portion.
EFI_DEVICE_PATH_PROTOCOL is deﬁned in EFI Device Path Protocol .
Device A pointer to the returned device handle. Type EFI_HANDLE is deﬁned in the InstallProtocolInterface()
The LocateDevicePath() function locates all devices on DevicePath that support Protocol and returns the handle to the
device that is closest to DevicePath .DevicePath is advanced over the device path nodes that were matched.
This function is useful for locating the proper instance of a protocol interface to use from a logical parent device driver.
For example, a target device driver may issue the request with its own device path and locate the interfaces to perform
I/O on its bus. It can also be used with a device path that contains a ﬁle path to strip off the ﬁle system portion of the
device path, leaving the ﬁle path and handle to the ﬁle system driver needed to access the ﬁle.
If the handle for DevicePath supports the protocol (a direct match), the resulting device path is advanced to the device
path terminator node. If DevicePath is a multi-instance device path, the function will operate on the ﬁrst instance.
EFI_SUCCESS The resulting handle was returned.
EFI_NOT_FOUND No handles matched the search.
EFI_INV ALID_PARAMETER Protocol is NULL
EFI_INV ALID_PARAMETER DevicePath is NULL.
EFI_INV ALID_PARAMETER A handle matched the search and Device is NULL.
7.3.9 EFI_BOOT_SERVICES.OpenProtocol()
Summary
Queries a handle to determine if it supports a speciﬁed protocol. If the protocol is supported by the han-
dle, it opens the protocol on behalf of the calling agent. This is an extended version of the EFI boot service
EFI_BOOT_SERVICES.HandleProtocol() .
Prototype
typedef
(EFIAPI *EFI_OPEN_PROTOCOL) (
OUT VOID **Interface OPTIONAL,
IN EFI_HANDLE AgentHandle,
IN EFI_HANDLE ControllerHandle,
IN UINT32 Attributes
);
Handle The handle for the protocol interface that is being opened.

Summary
Prototype
typedef
);
7.3. Protocol Handler Services 170Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
heading “RFC 4122”.
returned in *Interface if a structure is not associated with Protocol. This parameter is optional, and will be
ignored if Attributes is EFI_OPEN_PROTOCOL_TEST_PROTOCOL.
AgentHandle The handle of the agent that is opening the protocol interface speciﬁed by Protocol and Inter-
face. For agents that follow the UEFI Driver Model , this parameter is the handle that contains the
EFI_DRIVER_BINDING_PROTOCOL instance that is produced by the UEFI driver that is opening the pro-
tocol interface. For UEFI applications, this is the image handle of the UEFI application that is opening the
protocol interface. For applications that use HandleProtocol() to open a protocol interface, this parameter is the
image handle of the EFI ﬁrmware.
ControllerHandle If the agent that is opening a protocol is a driver that follows the UEFI Driver Model , then this
parameter is the controller handle that requires the protocol interface. If the agent does not follow the UEFI
Driver Model , then this parameter is optional and may be NULL.
Attributes The open mode of the protocol interface speciﬁed by Handle andProtocol . See “Related Deﬁnitions” for
the list of legal attributes.
This function opens a protocol interface on the handle speciﬁed by Handle for the protocol speciﬁed by Protocol . The
ﬁrst three parameters are the same as EFI_BOOT_SERVICES.HandleProtocol() . The only difference is that the agent
that is opening a protocol interface is tracked in an EFI’s internal handle database. The tracking is used by the UEFI
Driver Model , and also used to determine if it is safe to uninstall or reinstall a protocol interface.
The agent that is opening the protocol interface is speciﬁed by AgentHandle ,ControllerHandle , and Attributes . If
the protocol interface can be opened, then AgentHandle ,ControllerHandle , and Attributes are added to the list of
agents that are consuming the protocol interface speciﬁed by Handl andProtocol . In addition, the protocol interface is
returned in Interface , and EFI_SUCCESS is returned. If Attributes is TEST_PROTOCOL, then Interface is optional,
and can be NULL.
There are a number of reasons that this function call can return an error. If an error is returned, then AgentHandle ,
ControllerHandle , and Attributes are not added to the list of agents consuming the protocol interface speciﬁed by
Handle andProtocol .Interface is returned unmodiﬁed for all error conditions except EFI_UNSUPPORTED and
EFI_ALREADY_STARTED, NULL will be returned in * Interface when EFI_UNSUPPORTED and Attributes
is not EFI_OPEN_PROTOCOL_TEST_PROTOCOL, the protocol interface will be returned in * Interface when
EFI_ALREADY_STARTED.
The following is the list of conditions that must be checked before this function can return EFI_SUCCESS :
• IfProtocol is NULL, then EFI_INV ALID_PARAMETER is returned.
• IfInterface is NULL and Attributes is not TEST_PROTOCOL, then EFI_INV ALID_PARAMETER is returned.
• IfHandle is NULL, then EFI_INV ALID_PARAMETER is returned.
• IfHandle does not support Protocol, then EFI_UNSUPPORTED is returned.
• IfAttributes is not a legal value, then EFI_INV ALID_PARAMETER is returned. The legal values are listed in
“Related Deﬁnitions.”
• If Attributes is BY_CHILD_CONTROLLER, BY_DRIVER, EXCLUSIVE, or BY_DRIVER|EXCULSIVE,
andAgentHandle is NULL, then EFI_INV ALID_PARAMETER is returned.
• IfAttributes is BY_CHILD_CONTROLLER, BY_DRIVER, or BY_DRIVER|EXCULSIVE, and Controller-
Handle is NULL, then EFI_INV ALID_PARAMETER is returned.
• If Attributes is BY_CHILD_CONTROLLER and Handle is identical to ControllerHandle , then
EFI_INV ALID_PARAMETER is returned.
7.3. Protocol Handler Services 171Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• IfAttributes is BY_DRIVER, BY_DRIVER EXCLUSIVE, or EXCLUSIVE, and there are any items on the
open list of the protocol interface with an attribute of EXCLUSIVE or BY_DRIVER|EXCLUSIVE, then
EFI_ACCESS_DENIED is returned.
• If Attributes is BY_DRIVER, and there are any items on the open list of the protocol interface with
an attribute of BY_DRIVER, and AgentHandle is the same agent handle in the open list item, then
EFI_ALREADY_STARTED is returned.
• If Attributes is BY_DRIVER, and there are any items on the open list of the protocol interface with an
attribute of BY_DRIVER, and AgentHandle is different than the agent handle in the open list item, then
• IfAttributes is BY_DRIVER EXCLUSIVE, and there are any items on the open list of the protocol interface
with an attribute of BY_DRIVER|EXCLUSIVE, and AgentHandle is the same agent handle in the open list
item, then EFI_ALREADY_STARTED is returned.
with an attribute of BY_DRIVER|EXCLUSIVE, and AgentHandle is different than the agent handle in the open
list item, then EFI_ACCESS_DENIED is returned.
• If Attributes is BY_DRIVER|EXCLUSIVE or EXCLUSIVE, and there is an item on the
open list of the protocol interface with an attribute of BY_DRIVER, then the boot service
EFI_BOOT_SERVICES.DisconnectController() is called for the driver on the open list. If there is an item in the
open list of the protocol interface with an attribute of BY_DRIVER remaining after the DisconnectController()
call has been made, EFI_ACCESS_DENIED is returned.
#define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL 0x00000001
#define EFI_OPEN_PROTOCOL_GET_PROTOCOL 0x00000002
#define EFI_OPEN_PROTOCOL_TEST_PROTOCOL 0x00000004
#define EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER 0x00000008
#define EFI_OPEN_PROTOCOL_BY_DRIVER 0x00000010
#define EFI_OPEN_PROTOCOL_EXCLUSIVE 0x00000020
The following is the list of legal values for the Attributes parameter, and how each value is used.
BY_HANDLE_PROTOCOL Used in the implementation of EFI_BOOT_SERVICES.HandleProtocol() . Since
EFI_BOOT_SERVICES.OpenProtocol() performs the same function as HandleProtocol() with additional functionality,
HandleProtocol() can simply call OpenProtocol() with this Attributes value.
GET_PROTOCOL Used by a driver to get a protocol interface from a handle. Care must be taken when us-
ing this open mode because the driver that opens a protocol interface in this manner will not be informed if the
protocol interface is uninstalled or reinstalled. The caller is also not required to close the protocol interface with
EFI_BOOT_SERVICES.CloseProtocol() .
TEST_PROTOCOL Used by a driver to test for the existence of a protocol interface on a handle. Interface is optional
for this attribute value, so it is ignored, and the caller should only use the return status code. The caller is also not
required to close the protocol interface with CloseProtocol().
BY_CHILD_CONTROLLER Used by bus drivers to show that a protocol interface is being used by one of the
child controllers of a bus. This information is used by the boot service EFI_BOOT_SERVICES.ConnectController()
to recursively connect all child controllers and by the boot service EFI_BOOT_SERVICES.DisconnectController() to
get the list of child controllers that a bus driver created.
BY_DRIVER Used by a driver to gain access to a protocol interface. When this mode is used, the driver’s Stop()
function will be called by EFI_BOOT_SERVICES.DisconnectController() if the protocol interface is reinstalled or
uninstalled. Once a protocol interface is opened by a driver with this attribute, no other drivers will be allowed to open
the same protocol interface with the BY_DRIVER attribute.
7.3. Protocol Handler Services 172Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BY_DRIVER|EXCLUSIVE Used by a driver to gain exclusive access to a protocol interface. If any other drivers
have the protocol interface opened with an attribute of BY_DRIVER, then an attempt will be made to remove them
with DisconnectController().
EXCLUSIVE Used by applications to gain exclusive access to a protocol interface. If any drivers have the protocol
interface opened with an attribute of BY_DRIVER, then an attempt will be made to remove them by calling the driver’s
Stop() function.
EFI_SUCCESS An item was added to the open list for the protocol interface, and the proto-
col interface was returned in Interface .
EFI_INV ALID_PARAMETER Interface is NULL, and Attributes is not TEST_PROTOCOL.
EFI_UNSUPPORTED Handle does not support Protocol .
EFI_INV ALID_PARAMETER Attributes is not a legal value.
EFI_INV ALID_PARAMETER Attributes is BY_CHILD_CONTROLLER and AgentHandle is NULL.

EFI_INV ALID_PARAMETER Attributes is BY_DRIVER and AgentHandle is NULL.
EFI_INV ALID_PARAMETER Attribute is BY_DRIVEREXCLUSIVE and AgentHandle is NULL.
EFI_INV ALID_PARAMETER Attributes is EXCLUSIVE and AgentHandle is NULL.
EFI_INV ALID_PARAMETER Attributes is BY_CHILD_CONTROLLER and ControllerHandle is NULL.
EFI_INV ALID_PARAMETER Attributes is BY_DRIVER and ControllerHandle is NULL.
EFI_INV ALID_PARAMETER Attributes is BY_DRIVEREXCLUSIVE and ControllerHandle is NULL.
EFI_INV ALID_PARAMETER Attributes is BY_CHILD_CONTROLLER and Handle is identical to Con-
trollerHandle .
EFI_ACCESS_DENIED Attributes is BY_DRIVER and there is an item on the open list with an
attribute of BY_DRIVEREXCLUSIVE or EXCLUSIVE.
EFI_ACCESS_DENIED Attributes is BY_DRIVEREXCLUSIVE and there is an item on the open
list with an attribute of EXCLUSIVE.
EFI_ACCESS_DENIED Attributes is EXCLUSIVE and there is an item on the open list with an
EFI_ALREADY_STARTED Attributes is BY_DRIVER and there is an item on the open list with an
attribute of BY_DRIVER whose agent handle is the same as AgentHandle .
EFI_ACCESS_DENIED Attributes is BY_DRIVER and there is an item on the open list with an at-
tribute of BY_DRIVER whose agent handle is different than AgentHandle .
EFI_ALREADY_STARTED Attributes is BY_DRIVEREXCLUSIVE and there is an item on the open
list with an attribute of BY_DRIVEREXCLUSIVE whose agent handle is
the same as AgentHandle .
different than AgentHandle .
EFI_ACCESS_DENIED Attributes is BY_DRIVEREXCLSUIVE or EXCLUSIVE and there are
items in the open list with an attribute of BY_DRIVER that could not be
removed when EFI_BOOT_SERVICES.DisconnectController() was called
for that open item.
Examples
EFI_HANDLE ImageHandle;
EFI_DRIVER_BINDING_PROTOCOL *This;
extern EFI_GUID gEfiXyzIoProtocol;
7.3. Protocol Handler Services 173Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_XYZ_IO_PROTOCOL *XyzIo;
//
// EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL example
// Retrieves the XYZ I/O Protocol instance from ControllerHandle
// The application that isopening the protocol isidentified by ImageHandle
// Possible returnstatus codes:
// EFI_SUCCESS : The protocol was opened andreturned inXyzIo
// EFI_UNSUPPORTED : The protocol is notpresent on ControllerHandle
//
ControllerHandle,
&gEfiXyzIoProtocol,
&XyzIo,
NULL,
);
//
// EFI_OPEN_PROTOCOL_GET_PROTOCOL example
// The driver that isopening the protocol isidentified by the
// Driver Binding Protocol instance This. This->DriverBindingHandle
// identifies the agent that isopening the protocol interface, andit
//isopening this protocol on behalf of ControllerHandle.
//
&XyzIo,
This->DriverBindingHandle,
);
//
// EFI_OPEN_PROTOCOL_TEST_PROTOCOL example
// Tests to see ifthe XYZ I/O Protocol ispresent on ControllerHandle
//
NULL,
EFI_OPEN_PROTOCOL_TEST_PROTOCOL
7.3. Protocol Handler Services 174Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
//
// EFI_OPEN_PROTOCOL_BY_DRIVER example
// Opens the XYZ I/O Protocol on ControllerHandle
// EFI_ALREADY_STARTED : The protocol isalready opened by the driver
// EFI_ACCESS_DENIED : The protocol ismanaged by a different driver
//
&XyzIo,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
//
// EFI_OPEN_PROTOCOL_BY_DRIVER \| EFI_OPEN_PROTOCOL_EXCLUSIVE example
// Driver Binding Protocol instance This.This->DriverBindingHandle
// EFI_SUCCESS : The protocol was opened andreturned inXyzIo. If //
a different driver had the XYZ I/O Protocol opened
// BY_DRIVER, then that driver was disconnected to
// allow this driver to open the XYZ I/O Protocol.
// EFI_ACCESS_DENIED : The protocol ismanaged by a different driver that //
already has the protocol opened withan EXCLUSIVE // attribute.
//
&XyzIo,
EFI_OPEN_PROTOCOL_BY_DRIVER \| EFI_OPEN_PROTOCOL_EXCLUSIVE
);
7.3. Protocol Handler Services 175Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.3.10 EFI_BOOT_SERVICES.CloseProtocol()
Summary
Closes a protocol on a handle that was opened using EFI_BOOT_SERVICES.OpenProtocol() .
Prototype
typedef
(EFIAPI *EFI_CLOSE_PROTOCOL) (
IN EFI_HANDLE ControllerHandle
);
Handle The handle for the protocol interface that was previously opened with OpenProtocol(), and is now being
closed.
AgentHandle The handle of the agent that is closing the protocol interface. For agents that follow the UEFI Driver
Model , this parameter is the handle that contains the EFI_DRIVER_BINDING_PROTOCOL instance that is
produced by the UEFI driver that is opening the protocol interface. For UEFI applications, this is the image
handle of the UEFI application. For applications that used EFI_BOOT_SERVICES.HandleProtocol() to open
the protocol interface, this will be the image handle of the EFI ﬁrmware.
ControllerHandle If the agent that opened a protocol is a driver that follows the UEFI Driver Model , then this
parameter is the controller handle that required the protocol interface. If the agent does not follow the UEFI
This function updates the handle database to show that the protocol instance speciﬁed by Handle andProtocol is no
longer required by the agent and controller speciﬁed AgentHandle andControllerHandle.
IfHandle orAgentHandle is NULL, then EFI_INV ALID_PARAMETER is returned. If ControllerHandle is not
NULL, and ControllerHandle is NULL, then EFI_INV ALID_PARAMETER is returned. If Protocol is NULL, then
If the interface speciﬁed by Protocol is not supported by the handle speciﬁed by Handle , then EFI_NOT_FOUND is
returned.
If the interface speciﬁed by Protocol is supported by the handle speciﬁed by Handle , then a check is made to see
if the protocol instance speciﬁed by Protocol andHandle was opened by AgentHandle andControllerHandle with
EFI_BOOT_SERVICES.OpenProtocol() . If the protocol instance was not opened by AgentHandle andControllerHan-
dle, then EFI_NOT_FOUND is returned. If the protocol instance was opened by AgentHandle andControllerHandle ,
then all of those references are removed from the handle database, and EFI_SUCCESS is returned.
EFI_SUCCESS The protocol instance was closed.
EFI_INV ALID_PARAMETER AgentHandle is NULL.

returned.
7.3. Protocol Handler Services 176Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 7.23 – continued from previous page
EFI_INV ALID_PARAMETER ControllerHandle is not NULL and ControllerHandle is NULL.
EFI_NOT_FOUND Handle does not support the protocol speciﬁed by Protocol .
EFI_NOT_FOUND The protocol interface speciﬁed by Handle andProtocol is not currently
open by AgentHandle andControllerHandle .
Examples
//
// Close the XYZ I/O Protocol that was opened on behalf of ControllerHandle
//
Status = gBS->CloseProtocol (
ControllerHandle
);
//
// Close the XYZ I/O Protocol that was opened withBY_HANDLE_PROTOCOL
//
NULL
);
7.3.11 EFI_BOOT_SERVICES.OpenProtocolInformation()
Summary
Retrieves the list of agents that currently have a protocol interface opened.
Prototype
typedef
(EFIAPI *EFI_OPEN_PROTOCOL_INFORMATION) (
OUT EFI_OPEN_PROTOCOL_INFORMATION_ENTRY **EntryBuffer,
OUT UINTN *EntryCount
);
Handle The handle for the protocol interface that is being queried.
7.3. Protocol Handler Services 177Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EntryBuffer A pointer to a buffer of open protocol information in the form of
EFI_OPEN_PROTOCOL_INFORMATION_ENTRY structures. See “Related Deﬁnitions” for the decla-
ration of this type. The buffer is allocated by this service, and it is the caller’s responsibility to free this buffer
when the caller no longer requires the buffer’s contents.
EntryCount A pointer to the number of entries in EntryBuffer .
EFI_HANDLE AgentHandle;
EFI_HANDLE ControllerHandle;
UINT32 OpenCount;
} EFI_OPEN_PROTOCOL_INFORMATION_ENTRY;
This function allocates and returns a buffer of EFI_OPEN_PROTOCOL_INFORMATION_ENTRY structures. The
buffer is returned in EntryBuffer , and the number of entries is returned in EntryCount .
If the interface speciﬁed by Protocol is not supported by the handle speciﬁed by Handle, then EFI_NOT_FOUND is
returned.
If the interface speciﬁed by Protocol is supported by the handle speciﬁed by Handle, then EntryBuffer is allocated
with the boot service EFI_BOOT_SERVICES.AllocatePool() , and EntryCount is set to the number of entries in Entry-
Buffer . Each entry of EntryBuffer is ﬁlled in with the image handle, controller handle, and attributes that were passed
toEFI_BOOT_SERVICES.OpenProtocol() when the protocol interface was opened. The ﬁeld OpenCount shows the
number of times that the protocol interface has been opened by the agent speciﬁed by ImageHandle ,ControllerHandle ,
andAttributes . After the contents of EntryBuffer have been ﬁlled in, EFI_SUCCESS is returned. It is the caller’s re-
sponsibility to call EFI_BOOT_SERVICES.FreePool() onEntryBuffer when the caller no longer required the contents
ofEntryBuffer .
If there are not enough resources available to allocate EntryBuffer , then EFI_OUT_OF_RESOURCES is returned.
EFI_SUCCESS The open protocol information was returned in EntryBuffer , and the number
of entries was returned EntryCount .
EFI_OUT_OF_RESOURCES There are not enough resources available to allocate EntryBuffer .
Examples
See example in the EFI_BOOT_SERVICES.LocateHandleBuffer() function description for an example on how Lo-
cateHandleBuffer(), OpenProtocol(), and EFI_BOOT_SERVICES.OpenProtocolInformation() can be used to traverse
the entire handle database.
7.3. Protocol Handler Services 178Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.3.12 EFI_BOOT_SERVICES.ConnectController()
Summary
Connects one or more drivers to a controller.
Prototype
typedef
(EFIAPI *EFI_CONNECT_CONTROLLER) (
IN EFI_HANDLE *DriverImageHandle OPTIONAL,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL,
);
ControllerHandle The handle of the controller to which driver(s) are to be connected.
DriverImageHandle A pointer to an ordered list handles that support the EFI_DRIVER_BINDING_PROTOCOL.
The list is terminated by a NULL handle value. These handles are candidates for the Driver Binding Protocol(s)
that will manage the controller speciﬁed by ControllerHandle . This is an optional parameter that may be NULL.
This parameter is typically used to debug new drivers.
RemainingDevicePath A pointer to the device path that speciﬁes a child of the controller speciﬁed by
ControllerHandle . This is an optional parameter that may be NULL. If it is NULL, then handles
for all the children of ControllerHandle will be created. This parameter is passed unchanged to
theEFI_DRIVER_BINDING_PROTOCOL.Supported() andEFI_DRIVER_BINDING_PROTOCOL.Start() ser-
vices of the EFI_DRIVER_BINDING_PROTOCOL attached to ControllerHandle .
troller speciﬁed by ControllerHandle have been created. If FALSE , then the tree of controllers is only expanded
one level.
This function connects one or more drivers to the controller speciﬁed by ControllerHandle . If ControllerHandle
is NULL, then EFI_INV ALID_PARAMETER is returned. If there are no EFI_DRIVER_BINDING_PROTOCOL
instances present in the system, then return EFI_NOT_FOUND. If there are not enough resources available to complete
this function, then EFI_OUT_OF_RESOURCES is returned.
If the platform supports user authentication, as speciﬁed in User Identiﬁcation the device path associated with
ControllerHandle is checked against the connect permissions in the current user proﬁle. If forbidden, then
EFI_SECURITY_VIOLATION is returned. Then, before connecting any of the DriverImageHandles , the device
path associated with the handle is checked against the connect permissions in the current user proﬁle.
IfRecursive isFALSE , then this function returns after all drivers have been connected to ControllerHandle . IfRecur-
siveisTRUE , then ConnectController() is called recursively on all of the child controllers of ControllerHandle . The
child controllers can be identiﬁed by searching the handle database for all the controllers that have opened Controller-
Handle with an attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
This functions uses ﬁve precedence rules when deciding the order that drivers are tested against controllers. These ﬁve
rules from highest precedence to lowest precedence are as follows:
1.Context Override : DriverImageHandle is an ordered list of handles that support the
EFI_DRIVER_BINDING_PROTOCOL. The highest priority image handle is the ﬁrst element of the list,
and the lowest priority image handle is the last element of the list. The list is terminated with a NULL image
handle.
7.3. Protocol Handler Services 179Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2.Platform Driver Override : If an EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL instance is present in
the system, then the EFI Platform Driver Override Protocol service of this protocol is used to retrieve an
ordered list of image handles for ControllerHandle . From this list, the image handles found in rule (1) above
are removed. The ﬁrst image handle returned from GetDriver() has the highest precedence, and the last image
handle returned from GetDriver() has the lowest precedence. The ordered list is terminated when GetDriver()
returns EFI_NOT_FOUND. It is legal for no image handles to be returned by GetDriver(). There can be at most
a single instance in the system of the EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL. If there is more
than one, then the system behavior is not deterministic.
3.Driver Family Override Search : The list of available driver image handles can be found by using the
boot service EFI_BOOT_SERVICES.LocateHandle() with a SearchType ofByProtocol for the GUID of the
EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL. From this list, the image handles found in rules (1), and
(2) above are removed. The remaining image handles are sorted from highest to lowest based on the value
returned from the GetVersion() function of the EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL associated
with each image handle.
4.Bus Speciﬁc Driver Override : If there is an instance of the EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL

attached to ControllerHandle , then the EFI Platform Driver Override Protocol service of this protocol is used
to retrieve an ordered list of image handle for ControllerHandle . From this list, the image handles found in
rules (1), (2), and (3) above are removed. The ﬁrst image handle returned from GetDriver() has the highest
precedence, and the last image handle returned from GetDriver() has the lowest precedence. The ordered list
is terminated when GetDriver() returns EFI_NOT_FOUND. It is legal for no image handles to be returned by
GetDriver().
5.Driver Binding Search : The list of available driver image handles can be found by using the boot
service EFI_BOOT_SERVICES.LocateHandle() with a SearchType ofByProtocol for the GUID of the
EFI_DRIVER_BINDING_PROTOCOL. From this list, the image handles found in rules (1), (2), (3), and (4)
above are removed. The remaining image handles are sorted from highest to lowest based on the Version ﬁeld
of the EFI_DRIVER_BINDING_PROTOCOL instance associated with each image handle.
Each of the ﬁve groups of image handles listed above is tested against ControllerHandle in order by using the
EFI_DRIVER_BINDING_PROTOCOL.Supported() .RemainingDevicePath is passed into Supported() unmodiﬁed.
The ﬁrst image handle whose Supported() service returns EFI_SUCCESS is marked so the image handle will not
be tried again during this call to ConnectController(). Then, EFI_DRIVER_BINDING_PROTOCOL.Start() service
of the EFI_DRIVER_BINDING_PROTOCOL is called for ControllerHandle . Once again, RemainingDevicePath is
passed in unmodiﬁed. Every time Supported() returns EFI_SUCCESS, the search for drivers restarts with the highest
precedence image handle. This process is repeated until no image handles pass the Supported() check.
If at least one image handle returned EFI_SUCCESS from its Start() service, then EFI_SUCCESS is returned.
If no image handles returned EFI_SUCCESS from their Start() service then EFI_NOT_FOUND is returned unless
RemainingDevicePath is not NULL, and RemainingDevicePath is an End Node . In this special case, EFI_SUCCESS
is returned because it is not an error to fail to start a child controller that is speciﬁed by an End Device Path Node.
EFI_SUCCESS One or more drivers were connected to ControllerHandle.
EFI_SUCCESS No drivers were connected to ControllerHandle, but RemainingDevicePath
is not NULL, and it is an End Device Path Node.
EFI_INV ALID_PARAMETER ControllerHandle is NULL.
EFI_NOT_FOUND There are no EFI_DRIVER_BINDING_PROTOCOL instances present in
the system.
EFI_NOT_FOUND No drivers were connected to ControllerHandle.
EFI_SECURITY_VIOLATION The user has no permission to start UEFI device drivers on the device path
associated with the ControllerHandle or speciﬁed by the RemainingDevi-
cePath .
7.3. Protocol Handler Services 180Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Examples
//
// Connect All Handles Example
// The following example recursively connects all controllers in a platform.
//
UINTN HandleCount;
EFI_HANDLE *HandleBuffer;
UINTN HandleIndex;
//
// Retrieve the list of all handles from the handle database
//
Status = gBS->LocateHandleBuffer (
NULL,
NULL,
&HandleCount,
&HandleBuffer
);
if (!EFI_ERROR (Status)) {
for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
Status = gBS->ConnectController (
HandleBuffer[HandleIndex],
NULL,
NULL,
TRUE
);
}
gBS->FreePool(HandleBuffer);
}
//
// Connect Device Path Example
// The following example walks the device path nodes of a device path, and
// connects only the drivers required to force a handle with that device path
// to be present in the handle database. This algorithms guarantees that
// only the minimum number of devices and drivers are initialized.
//
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath;
EFI_HANDLE Handle;
do {
//
// Find the handle that best matches the Device Path. If it is only a
// partial match the remaining part of the device path is returned in
// RemainingDevicePath.
//
RemainingDevicePath = DevicePath;
Status = gBS->LocateDevicePath (
&gEfiDevicePathProtocolGuid,
&RemainingDevicePath,
7.3. Protocol Handler Services 181Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
&Handle
);
if (EFI_ERROR(Status)) {
return EFI_NOT_FOUND;
}
//
// Connect all drivers that apply to Handle and RemainingDevicePath
// If no drivers are connected Handle, then return EFI_NOT_FOUND
// The Recursive flag is FALSE so only one level will be expanded.
//
Handle,
NULL,
RemainingDevicePath,
FALSE
);
}
//
// Loop until RemainingDevicePath is an empty device path
//
} while (!IsDevicePathEnd (RemainingDevicePath));
//
// A handle with DevicePath exists in the handle database
//
return EFI_SUCCESS;
7.3.13 EFI_BOOT_SERVICES.DisconnectController()
Summary
Disconnects one or more drivers from a controller.
Prototype
typedef
(EFIAPI *EFI_DISCONNECT_CONTROLLER) (
IN EFI_HANDLE DriverImageHandle OPTIONAL,
IN EFI_HANDLE ChildHandle OPTIONAL
);
ControllerHandle The handle of the controller from which driver(s) are to be disconnected.
DriverImageHandle The driver to disconnect from ControllerHandle . IfDriverImageHandle is NULL, then all the
drivers currently managing ControllerHandle are disconnected from ControllerHandle .
ChildHandle The handle of the child to destroy. If ChildHandle is NULL, then all the children of ControllerHandle
are destroyed before the drivers are disconnected from ControllerHandle .
7.3. Protocol Handler Services 182Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function disconnects one or more drivers from the controller speciﬁed by ControllerHandle . IfDriverImageHan-
dleis NULL, then all of the drivers currently managing ontrollerHandle are disconnected from ControllerHandle . If
DriverImageHandle is not NULL, then only the driver speciﬁed by DriverImageHandle is disconnected from Con-
trollerHandle . IfChildHandle is NULL, then all of the children of ControllerHandle are destroyed before the drivers
are disconnected from ControllerHandle . IfChildHandle is not NULL, then only the child controller speciﬁed by
ChildHandle is destroyed. If ChildHandle is the only child of ControllerHandle , then the driver speciﬁed by Driver-
ImageHandle will be disconnected from ontrollerHandle . A driver is disconnected from a controller by calling the
Stop() service of the EFI_DRIVER_BINDING_PROTOCOL. The EFI_DRIVER_BINDING_PROTOCOL is on the
driver image handle, and the handle of the controller is passed into the Stop() service. The list of drivers manag-
ing a controller, and the list of children for a speciﬁc controller can be retrieved from the handle database with the
boot service EFI_BOOT_SERVICES.OpenProtocolInformation() . If all the required drivers are disconnected from
ControllerHandle , then EFI_SUCCESS is returned.
IfControllerHandle is NULL, then EFI_INV ALID_PARAMETER is returned. If no drivers are managing Controller-
Handle , then EFI_SUCCESS is returned. If DriverImageHandle is not NULL, and DriverImageHandle isnot a valid
EFI_HANDLE , then EFI_INV ALID_PARAMETER is returned. If DriverImageHandle is not NULL, and Driver-
ImageHandle is not currently managing ControllerHandle , then EFI_SUCCESS is returned. If ChildHandle is not
NULL, and ChildHandle isnot a valid EFI_HANDLE , then EFI_INV ALID_PARAMETER is returned. If there are
not enough resources available to disconnect drivers from ControllerHandle , then EFI_OUT_OF_RESOURCES is
returned.
EFI_SUCCESS One or more drivers were disconnected from the controller.
EFI_SUCCESS On entry, no drivers are managing ControllerHandle .
EFI_SUCCESS DriverImageHandle is not NULL, and on entry DriverImageHandle is not
managing ControllerHandle .
EFI_INV ALID_PARAMETER DriverImageHandle is not NULL, and it is not a valid EFI_HANDLE.
EFI_INV ALID_PARAMETER ChildHandle is not NULL, and it is not a valid EFI_HANDLE.
EFI_OUT_OF_RESOURCES There are not enough resources available to disconnect any drivers from
ControllerHandle.
EFI_DEVICE_ERROR The controller could not be disconnected because of a device error.
EFI_INV ALID_PARAMETER DriverImageHandle does not support the
EFI_DRIVER_BINDING_PROTOCOL.
Examples
//
// Disconnect All Handles Example
// The following example recursively disconnects all drivers from all
// controllers in a platform
//
//
//

Examples
//
//
//
//
7.3. Protocol Handler Services 183Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NULL,
NULL,
);
Status = gBS->DisconnectController (
NULL,
NULL
);
}
7.3.14 EFI_BOOT_SERVICES.ProtocolsPerHandle()
Summary
Retrieves the list of protocol interface GUIDs that are installed on a handle in a buffer allocated from pool.
Prototype
typedef
(EFIAPI *EFI_PROTOCOLS_PER_HANDLE) (
OUT EFI_GUID ***ProtocolBuffer,
OUT UINTN *ProtocolBufferCount
);
Handle The handle from which to retrieve the list of protocol interface GUIDs.
ProtocolBuffer A pointer to the list of protocol interface GUID pointers that are installed on Handle . This buffer is
allocated with a call to the Boot Service EFI_BOOT_SERVICES.AllocatePool() . It is the caller’s responsibility
to call the Boot Service EFI_BOOT_SERVICES.FreePool() when the caller no longer requires the contents of
ProtocolBuffer .
ProtocolBufferCount A pointer to the number of GUID pointers present in ProtocolBuffer .
The ProtocolsPerHandle() function retrieves the list of protocol interface GUIDs that are installed on Handle . The list
is returned in ProtocolBuffer, and the number of GUID pointers in ProtocolBuffer is returned in ProtocolBufferCount .
IfHandle is NULL or Handle is NULL, then EFI_INV ALID_PARAMETER is returned.
IfProtocolBuffer is NULL, then EFI_INV ALID_PAREMETER is returned.
IfProtocolBufferCount is NULL, then EFI_INV ALID_PARAMETER is returned.
If there are not enough resources available to allocate ProtocolBuffer , then EFI_OUT_OF_RESOURCES is returned.
7.3. Protocol Handler Services 184Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The list of protocol interface GUIDs installed on Handle was returned in
ProtocolBuffer . The number of protocol interface GUIDs was returned in
ProtocolBufferCount .
EFI_INV ALID_PARAMETER ProtocolBuffer is NULL.
EFI_INV ALID_PARAMETER ProtocolBufferCount is NULL.
EFI_OUT_OF_RESOURCES There is not enough pool memory to store the results.
Examples
cateHandleBuffer(), EFI_BOOT_SERVICES.ProtocolsPerHandle() ,EFI_BOOT_SERVICES.OpenProtocol() . and
EFI_BOOT_SERVICES.OpenProtocolInformation() can be used to traverse the entire handle database.
7.3.15 EFI_BOOT_SERVICES.LocateHandleBuffer()
Summary
Returns an array of handles that support the requested protocol in a buffer allocated from pool.
Prototype
typedef
(EFIAPI *EFI_LOCATE_HANDLE_BUFFER) (
OUT UINTN *NoHandles,
OUT EFI_HANDLE **Buffer
);
SearchType Speciﬁes which handle(s) are to be returned.
Protocol Provides the protocol to search by. This parameter is only valid for a SearchType ofByProtocol .
SearchKey Supplies the search key depending on the SearchType .
NoHandles The number of handles returned in Buffer .
Buffer A pointer to the buffer to return the requested array of handles that support Protocol . This buffer is allocated
with a call to the Boot Service EFI_BOOT_SERVICES.AllocatePool() . It is the caller’s responsibility to call the
Boot Service EFI_BOOT_SERVICES.FreePool() when the caller no longer requires the contents of Buffer.
The LocateHandleBuffer() function returns one or more handles that match the SearchType request. Buffer is allocated
from pool, and the number of entries in Buffer is returned in NoHandles . Each SearchType is described below:
AllHandles
Protocol andSearchKey are ignored and the function returns an array of every handle in the system.
ByRegisterNotify
SearchKey supplies the Registration returned by EFI_BOOT_SERVICES.RegisterProtocolNotify() . The function re-
turns the next handle that is new for the Registration. Only one handle is returned at a time, and the caller must loop
until no more handles are returned. Protocol is ignored for this search type.
7.3. Protocol Handler Services 185Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
All handles that support Protocol are returned. SearchKey is ignored for this search type.
IfNoHandles is NULL, then EFI_INV ALID_PARAMETER is returned.
IfBuffer is NULL, then EFI_INV ALID_PARAMETER is returned.
If there are no handles in the handle database that match the search criteria, then EFI_NOT_FOUND is returned.
If there are not enough resources available to allocate Buffer , then EFI_OUT_OF_RESOURCES is returned.
EFI_SUCCESS The array of handles was returned in Buffer , and the number of handles in
Buffer was returned in NoHandles .
EFI_INV ALID_PARAMETER NoHandles is NULL
EFI_INV ALID_PARAMETER Buffer is NULL
EFI_OUT_OF_RESOURCES There is not enough pool memory to store the matching results.
Examples
//
// The following example traverses the entire handle database. First all of
// the handles in the handle database are retrieved by using
// LocateHandleBuffer(). Then it uses ProtocolsPerHandle() to retrieve the
// list of protocol GUIDs attached to each handle. Then it uses OpenProtocol()
// to get the protocol instance associated with each protocol GUID on the
// handle. Finally, it uses OpenProtocolInformation() to retrieve the list of
// agents that have opened the protocol on the handle. The caller of these
// functions must make sure that they free the return buffers with FreePool()
// when they are done.
//
EFI_GUID **ProtocolGuidArray;
UINTN ArrayCount;
UINTN ProtocolIndex;
EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo;
UINTN OpenInfoCount;
UINTN OpenInfoIndex;
//
//
NULL,
NULL,
);
7.3. Protocol Handler Services 186Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// Retrieve the list of all the protocols on each handle
//
Status = gBS->ProtocolsPerHandle (
&ProtocolGuidArray,
&ArrayCount
);
for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) {
//
// Retrieve the protocol instance for each protocol
//
ProtocolGuidArray[ProtocolIndex],
&Instance,
NULL,
);
//
// Retrieve the list of agents that have opened each protocol
//
Status = gBS->OpenProtocolInformation (
&OpenInfo,
&OpenInfoCount
);
for (OpenInfoIndex=0;OpenInfoIndex<OpenInfoCount;OpenInfoIndex++) {
//
// HandleBuffer[HandleIndex] is the handle
// ProtocolGuidArray[ProtocolIndex] is the protocol GUID
// Instance is the protocol instance for the protocol
// OpenInfo[OpenInfoIndex] is an agent that has opened a protocol
//
}
if (OpenInfo != NULL) {
gBS->FreePool(OpenInfo);
}
}
}
if (ProtocolGuidArray != NULL) {
gBS->FreePool(ProtocolGuidArray);
}
}
}
if (HandleBuffer != NULL) {
gBS->FreePool (HandleBuffer);
}
}
7.3. Protocol Handler Services 187Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.3.16 EFI_BOOT_SERVICES.LocateProtocol()
Summary
Returns the ﬁrst protocol instance that matches the given protocol.
Prototype
typedef
(EFIAPI *EFI_LOCATE_PROTOCOL) (
IN VOID *Registration OPTIONAL,
);
Protocol Provides the protocol to search for.
Registration Optional registration key returned from EFI_BOOT_SERVICES.RegisterProtocolNotify() . IfRegistra-
tionis NULL, then it is ignored.
Interface On return, a pointer to the ﬁrst interface that matches Protocol andRegistration .
The LocateProtocol() function ﬁnds the ﬁrst device handle that support Protocol , and returns a pointer to the protocol
interface from that handle in Interface . If no protocol instances are found, then Interface is set to NULL.
IfInterface is NULL, then EFI_INV ALID_PARAMETER is returned.
IfProtocol is NULL, then EFI_INV ALID_PARAMETER is returned.
IfRegistration is NULL, and there are no handles in the handle database that support Protocol , then
EFI_NOT_FOUND is returned.
IfRegistration is not NULL, and there are no new handles for Registration , then EFI_NOT_FOUND is returned.

);
EFI_SUCCESS A protocol instance matching Protocol was found and returned in Interface .
EFI_INV ALID_PARAMETER Interface is NULL. Protocol is NULL.
EFI_NOT_FOUND No protocol instances were found that match Protocol and Registration .
7.3.17 EFI_BOOT_SERVICES.InstallMultipleProtocolInterfaces()
Summary
Installs one or more protocol interfaces into the boot services environment.
Prototype
typedef
EFIAPI \ *EFI_INSTALL_MULTIPLE_PROTOCOL_INTERFACES) (
...
);
7.3. Protocol Handler Services 188Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Handle The pointer to a handle to install the new protocol interfaces on, or a pointer to NULL if a new handle is to
be allocated.
. . . A variable argument list containing pairs of protocol GUIDs and protocol interfaces.
This function installs a set of protocol interfaces into the boot services environment. It removes arguments from
the variable argument list in pairs. The ﬁrst item is always a pointer to the protocol’s GUID, and the sec-
ond item is always a pointer to the protocol’s interface. These pairs are used to call the boot service, see
EFI_BOOT_SERVICES.InstallProtocolInterface() to add a protocol interface to Handle . IfHandle is NULL on entry,
then a new handle will be allocated. The pairs of arguments are removed in order from the variable argument list until
a NULL protocol GUID value is found. If any errors are generated while the protocol interfaces are being installed,
then all the protocols installed prior to the error will be uninstalled with the boot service
EFI_BOOT_SERVICES.UninstallProtocolInterface() before the error is returned. The same GUID cannot
be installed more than once onto the same handle.
It is illegal to have two handles in the handle database with identical device paths. This service performs a test
to guarantee a duplicate device path is not inadvertently installed on two different handles. Before any protocol
interfaces are installed onto Handle, the list of GUID/pointer pair parameters are searched to see if a Device Path
Protocol instance is being installed. If a Device Path Protocol instance is going to be installed onto Handle, then
a check is made to see if a handle is already present in the handle database with an identical Device Path Protocol
instance. If an identical Device Path Protocol instance is already present in the handle database, then no protocols are
installed onto Handle, and EFI_ALREADY_STARTED is returned.
EFI_SUCCESS All the protocol interfaces were installed.
EFI_ALREADY_STARTED A Device Path Protocol instance was passed in that is already present in the
handle database.
EFI_OUT_OF_RESOURCES There was not enough memory in pool to install all the protocols.
EFI_INV ALID_PARAMETER Protocol is already installed on the handle speciﬁed by Handle .
7.3.18 EFI_BOOT_SERVICES.UninstallMultipleProtocolInterfaces()
Summary
Removes one or more protocol interfaces into the boot services environment.
Prototype
typedef
EFIAPI*EFI_UNINSTALL_MULTIPLE_PROTOCOL_INTERFACES) (
...
);
Handle The handle to remove the protocol interfaces from.
7.3. Protocol Handler Services 189Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function removes a set of protocol interfaces from the boot services environment. It removes arguments
from the variable argument list in pairs. The ﬁrst item is always a pointer to the protocol’s GUID, and the
second item is always a pointer to the protocol’s interface. These pairs are used to call the boot service
EFI_BOOT_SERVICES.UninstallProtocolInterface() to remove a protocol interface from Handle. The pairs of ar-
guments are removed in order from the variable argument list until a NULL protocol GUID value is found. If all
of the protocols are uninstalled from Handle, then EFI_SUCCESS is returned. If any errors are generated while the
protocol interfaces are being uninstalled, then the protocols uninstalled prior to the error will be reinstalled with the
boot service EFI_BOOT_SERVICES.InstallProtocolInterface() and the status code EFI_INV ALID_PARAMETER is
returned.
EFI_SUCCESS All the protocol interfaces were removed.
EFI_INV ALID_PARAMETER One of the protocol interfaces was not previously installed on Handle.
7.4 Image Services
Three types of images can be loaded: UEFI applications written ( UEFI Applications , UEFI boot services drivers
(UEFI Drivers ), and EFI runtime drivers ( UEFI Drivers ) . A UEFI OS Loader ( UEFI OS Loaders ) is a type of UEFI
application. The most signiﬁcant difference between these image types is the type of memory into which they are
loaded by the ﬁrmware’s loader. See the Table, below, Image Type Differences Summary summarizes the differences
between images.
Table 7.30: Image Type Differences Summary
UEFI Application UEFI Boot Service
DriverUEFI Runtime Driver
Description A transient application
that is loaded during
boot services time. UEFI
applications are either
unloaded when they
complete (see UEFI
Applications , or they
take responsibility for
the continued operation
of the system via Exit-
BootServices() (see UEFI
OS Loaders . The UEFI
applications are loaded in
sequential order by the
boot manager, but one
UEFI application may
dynamically load another.A program that is loaded
into boot services mem-
ory and stays resident un-
til boot services terminate.
SeeUEFI Drivers .A program that is loaded into runtime
services memory and stays resident dur-
ing runtime. The memory required for
a UEFI runtime services driver must be
performed in a single memory allocation,
and marked as EﬁRuntimeServicesData.
(Note that the memory only stays res-
ident when booting an EFI-compatible
operating system. Legacy operating sys-
tems will reuse the memory.) See UEFI
Drivers .
Loaded
into mem-
ory typeEﬁLoaderCode, EﬁLoad-
erDataEﬁBootServicesCode,
EﬁBootServicesDataEﬁRuntimeServicesCode, EﬁRuntime-
ServicesData
7.4. Image Services 190Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 7.30 – continued from previous page
Default
pool al-
locations
from
memory
typeEﬁLoaderData EﬁBootServicesData EﬁRuntimeServicesData
Exit behav-
iorWhen an application exits,
ﬁrmware frees the mem-
ory used to hold its image.When a UEFI boot ser-
vice driver exits with an
error code, ﬁrmware frees
the memory used to hold
its image. When a UEFI
boot service driver’s en-
try point completes with
EFI_SUCCESS, the im-
age is retained in memory.When a UEFI runtime driver exits with
an error code, ﬁrmware frees the mem-
ory used to hold its image. When
a UEFI runtime services driver’s en-
try point completes with EFI_SUCCESS,
the image is retained in memory.
Notes This type of image would
not install any protocol in-
terfaces or handles.This type of image would
typically use InstallProto-
colInterface().A UEFI runtime driver can only allo-
cate runtime memory during boot ser-
vices time. Due to the complexity of per-
forming a virtual relocation for a runtime
image, this driver type is discouraged un-
less it is absolutely required.
Most UEFI images are loaded by the boot manager. When a UEFI application or UEFI driver is installed, the in-
stallation procedure registers itself with the boot manager for loading. However, in some cases a UEFI applica-
tion or UEFI driver may want to programmatically load and start another UEFI image. This can be done with the
EFI_BOOT_SERVICES.LoadImage() andEFI_BOOT_SERVICES.StartImage() interfaces. UEFI drivers may only
load UEFI applications during the UEFI driver’s initialization entry point. The Table, below, Image Functions lists the
functions that make up Image Services.
Table 7.31: Image Functions
LoadImage Boot Loads an EFI image into memory.
StartImage Boot Transfers control to a loaded image’s entry point.
UnloadImage Boot Unloads an image.
EFI_IMAGE_ENTRY_POINT Boot Prototype of an EFI Image’s entry point.
Exit Boot Exits the image’s entry point.
ExitBootServices Boot Terminates boot services.
The Image boot services have been modiﬁed to take advantage of the information that is now being tracked with the
EFI_BOOT_SERVICES.OpenProtocol() andEFI_BOOT_SERVICES.CloseProtocol() boot services. Since the usage
of protocol interfaces is being tracked with these new boot services, it is now possible to automatically close protocol
interfaces when a UEFI application or a UEFI driver is unloaded or exited.
7.4. Image Services 191Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.4.1 EFI_BOOT_SERVICES.LoadImage()
Summary
Loads an EFI image into memory.
Prototype
typedef
(EFIAPI *EFI_IMAGE_LOAD) (
IN BOOLEAN BootPolicy,
IN EFI_HANDLE ParentImageHandle,

Summary
Prototype
typedef
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath OPTIONAL,
IN VOID *SourceBuffer OPTIONAL
IN UINTN SourceSize,
OUT EFI_HANDLE *ImageHandle
);
BootPolicy IfTRUE , indicates that the request originates from the boot manager, and that the boot manager is at-
tempting to load DevicePath as a boot selection. Ignored if SourceBuffer is not NULL.
ParentImageHandle The caller’s image handle. Type EFI_HANDLE is deﬁned in the
EFI_BOOT_SERVICES.InstallProtocolInterface() function description. This ﬁeld is used to initialize the
ParentHandle ﬁeld of the EFI Loaded Image Protocol for the image that is being loaded.
DevicePath TheDeviceHandle speciﬁc ﬁle path from which the image is loaded. EFI_DEVICE_PATH_PROTOCOL
is deﬁned in EFI Device Path Protocol .
SourceBuffer If not NULL, a pointer to the memory location containing a copy of the image to be loaded.
SourceSize The size in bytes of SourceBuffer. Ignored if SourceBuffer is NULL.
ImageHandle Pointer to the returned image handle that is created when the image is successfully loaded. Type
EFI_HANDLE is deﬁned in the InstallProtocolInterface() function description.
#define EFI_HII_PACKAGE_LIST_PROTOCOL_GUID \
{ 0x6a1ee763, 0xd47a, 0x43b4, \
{ 0xaa, 0xbe, 0xef, 0x1d, 0xe2, 0xab, 0x56, 0xfc } }
typedef EFI_HII_PACKAGE_LIST_HEADER *EFI_HII_PACKAGE_LIST_PROTOCOL;
The LoadImage() function loads an EFI image into memory and returns a handle to the image. The image is loaded in
one of two ways.
• IfSourceBuffer is not NULL, the function is a memory-to-memory load in which SourceBuffer points to the
image to be loaded and SourceSize indicates the image’s size in bytes. In this case, the caller has copied the
image into SourceBuffer and can free the buffer once loading is complete. The DevicePath is optional in this
case. A DevicePath should still be provided since certain portions of ﬁrmware may use it to make certain
security policy decisions.
• If SourceBuffer is NULL, the function is a ﬁle copy operation that uses the
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL .
7.4. Image Services 192Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If there is no instance of EFI_SIMPLE_FILE_SYSTEM_PROTOCOL associated with ﬁle path,
then this function will attempt to use EFI_LOAD_FILE_PROTOCOL ( BootPolicy isTRUE ) or
EFI_LOAD_FILE2_PROTOCOL, and then EFI_LOAD_FILE_PROTOCOL ( BootPolicy isFALSE ).
In all cases, this function will use the instance of these protocols associated with the handle that most closely matches
DevicePath will be used. See the boot service description for more information on how the closest handle is located.
• In the case of EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, the path name from the File Path Media Device
Path node(s) of DevicePath is used.
• In the case of EFI_LOAD_FILE_PROTOCOL, the remaining device path nodes of DevicePath and the BootPol-
icyﬂag are passed to the EFI_LOAD_FILE_PROTOCOL function. The default image responsible for booting is
loaded when DevicePath speciﬁes only the device (and there are no further device nodes). For more information
see the discussion of EFI_LOAD_FILE_PROTOCOL .
• In the case of EFI_LOAD_FILE2_PROTOCOL, the behavior is the same as above, except that it is only used if
BootOption isFALSE . For more information, see the discussion of the EFI_LOAD_FILE2_PROTOCOL.
• If the platform supports driver signing, as speciﬁed in Image Execution Information Table
and the image signature is not valid, then information about the image is recorded in the
EFI_IMAGE_EXECUTION_INFO_TABLE (see Using the Image Execution Information Table in sec-
tion 32.4.2. {cross-reference needed} and EFI_SECURITY_VIOLATION is returned.
• If the platform supports user authentication, as described in User Identiﬁcation and loading of images on the
speciﬁed FilePath is forbidden in the current user proﬁle, then the information about the image is recorded (see
Deferred Execution in Image Execution Information Table and EFI_SECURITY_VIOLATION is returned.
Once the image is loaded, ﬁrmware creates and returns an EFI_HANDLE that identiﬁes the image and supports EFI
Loaded Image Protocol and the EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL. The caller may ﬁll in the
image’s “load options” data, or add additional protocol support to the handle before passing control to the newly
loaded image by calling EFI_BOOT_SERVICES.StartImage() . Also, once the image is loaded, the caller either starts
it by calling StartImage() or unloads it by calling EFI_BOOT_SERVICES.UnloadImage() .
Once the image is loaded, LoadImage() installs EFI_HII_PACKAGE_LIST_PROTOCOL on the handle if the image
contains a custom PE/COFF resource with the type ‘HII’. The protocol’s interface pointer points to the HII package
list which is contained in the resource’s data. The format of this is in EFI_HII_PACKAGE_HEADER .
EFI_SUCCESS Image was loaded into memory correctly.
EFI_NOT_FOUND Both SourceBuffer andDevicePath are NULL.
EFI_INV ALID_PARAMETER ImageHandle is NULL.
EFI_INV ALID_PARAMETER ParentImageHandle is NULL.
EFI_UNSUPPORTED The image type is not supported.
EFI_OUT_OF_RESOURCES Image was not loaded due to insufﬁcient resources.
EFI_LOAD_ERROR Image was not loaded because the image format was corrupt or not under-
stood.
EFI_DEVICE_ERROR Image was not loaded because the device returned a read error.
EFI_ACCESS_DENIED Image was not loaded because the platform policy prohibits the image from
being loaded. NULL is returned in ImageHandle .
EFI_SECURITY_VIOLATION Image was loaded and an ImageHandle was created with a valid
EFI_LOADED_IMAGE_PROTOCOL. However, the current platform pol-
icy speciﬁes that the image should not be started.
7.4. Image Services 193Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.4.2 EFI_BOOT_SERVICES.StartImage()
Summary
Transfers control to a loaded image’s entry point.
Prototype
typedef
(EFIAPI *EFI_IMAGE_START) (
OUT UINTN *ExitDataSize,
OUT CHAR16 **ExitData OPTIONAL
);
ImageHandle Handle of image to be started. Type EFI_HANDLE is deﬁned in the
ExitDataSize Pointer to the size, in bytes, of ExitData . IfExitData is NULL, then this parameter is ignored and the
contents of ExitDataSize are not modiﬁed.
ExitData Pointer to a pointer to a data buffer that includes a Null-terminated string, optionally followed by additional
binary data. The string is a description that the caller may use to further indicate the reason for the image’s exit.
The StartImage() function transfers control to the entry point of an image that was loaded by
EFI_BOOT_SERVICES.LoadImage() . The image may only be started one time.
Control returns from StartImage() when the loaded image’s EFI_IMAGE_ENTRY_POINT returns or when the loaded
image calls EFI_BOOT_SERVICES.Exit() When that call is made, the ExitData buffer and ExitDataSize from Exit()
are passed back through the ExitData buffer and ExitDataSize in this function. The caller of this function is responsible
for returning the ExitData buffer to the pool by calling EFI_BOOT_SERVICES.FreePool() when the buffer is no longer
needed. Using Exit() is similar to returning from the image’s EFI_IMAGE_ENTRY_POINT except that Exit() may
also return additional ExitData . Exit() function description deﬁnes clean up procedure performed by the ﬁrmware
once loaded image returns control.
To maintain compatibility with UEFI drivers that are written to the EFI 1.02 Speciﬁcation , StartImage() must monitor
the handle database before and after each image is started. If any handles are created or modiﬁed when an image is
started, then EFI_BOOT_SERVICES.ConnectController() must be called with the Recursive parameter set to TRUE
for each of the newly created or modiﬁed handles before StartImage() returns.
EFI_INV ALID_PARAMETER ImageHandle is either an invalid image handle or the image has already
been initialized with StartImage
Exit code from image Exit code from image.
EFI_SECURITY_VIOLATION The current platform policy speciﬁes that the image should not be started.
7.4. Image Services 194Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.4.3 EFI_BOOT_SERVICES.UnloadImage()
Summary
Unloads an image.
Prototype
typedef
(EFIAPI *EFI_IMAGE_UNLOAD) (
);
ImageHandle Handle that identiﬁes the image to be unloaded.
The UnloadImage() function unloads a previously loaded image.
There are three possible scenarios. If the image has not been started, the function unloads the image and returns
EFI_SUCCESS.
If the image has been started and has an Unload() entry point, control is passed to that entry point. If the image’s unload

Summary
Prototype
typedef
);
function returns EFI_SUCCESS, the image is unloaded; otherwise, the error returned by the image’s unload function
is returned to the caller. The image unload function is responsible for freeing all allocated memory and ensuring that
there are no references to any freed memory, or to the image itself, before returning EFI_SUCCESS.
If the image has been started and does not have an Unload() entry point, the function returns EFI_UNSUPPORTED.
All of the protocols that were opened by ImageHandle using the boot service EFI_BOOT_SERVICES.OpenProtocol()
are automatically closed with the boot service EFI_BOOT_SERVICES.CloseProtocol() . If all of the open protocols are
closed, then EFI_SUCCESS is returned. If any call to CloseProtocol() fails, then the error code from CloseProtocol()
is returned.
EFI_SUCCESS The image has been unloaded.
EFI_UNSUPPORTED The image has been started, and does not support unload.
EFI_INV ALID_PARAMETER ImageHandle is not a valid image handle.
Exit code from Unload handler Exit code from the image’s unload function.
7.4.4 EFI_IMAGE_ENTRY_POINT
Summary
This is the declaration of an EFI image entry point. This can be the entry point to an application written to this
speciﬁcation, an EFI boot service driver, or an EFI runtime driver.
Prototype
typedef
7.4. Image Services 195Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
ImageHandle Handle that identiﬁes the loaded image. Type EFI_HANDLE is deﬁned in the
SystemTable System Table for this image. Type EFI_SYSTEM_TABLE is deﬁned in EFI System Table
An image’s entry point is of type EFI_IMAGE_ENTRY_POINT. After ﬁrmware loads an image into memory, control
is passed to the image’s entry point. The entry point is responsible for initializing the image. The image’s Image-
Handle is passed to the image. The ImageHandle provides the image with all the binding and data information it
needs. This information is available through protocol interfaces. However, to access the protocol interfaces on Im-
ageHandle requires access to boot services functions. Therefore, EFI_BOOT_SERVICES.LoadImage() passes to the
EFI_IMAGE_ENTRY_POINT a SystemTable that is inherited from the current scope of LoadImage().
All image handles support the EFI Loaded Image Protocol and the EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL.
These protocol can be used to obtain information about the loaded image’s state–for example, the device from which
the image was loaded and the image’s load options. In addition, the ImageHandle may support other protocols
provided by the parent image.
If the image supports dynamic unloading, it must supply an unload function in the
EFI_LOADED_IMAGE_PROTOCOL structure before returning control from its entry point.
In general, an image returns control from its initialization entry point by calling EFI_BOOT_SERVICES.Exit() or by
returning control from its entry point. If the image returns control from its entry point, the ﬁrmware passes control to
Exit() using the return code as the ExitStatus parameter to Exit().
See Exit() below for entry point exit conditions.
7.4.5 EFI_BOOT_SERVICES.Exit()
Summary
Terminates a loaded EFI image and returns control to boot services.
Prototype
typedef
(EFIAPI *EFI_EXIT) (
IN EFI_STATUS ExitStatus,
IN UINTN ExitDataSize,
IN CHAR16 *ExitData OPTIONAL
);
ImageHandle Handle that identiﬁes the image. This parameter is passed to the image on entry.
ExitStatus The image’s exit code.
ExitDataSize The size, in bytes, of ExitData . Ignored if ExitStatus is EFI_SUCCESS.
ExitData Pointer to a data buffer that includes a Null-terminated string, optionally followed by additional binary data.
The string is a description that the caller may use to further indicate the reason for the image’s exit. ExitData is
7.4. Image Services 196Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
only valid if ExitStatu is something other than EFI_SUCCESS. The ExitData buffer must be allocated by calling
EFI_BOOT_SERVICES.AllocatePool() .
The Exit() function terminates the image referenced by ImageHandle and returns control to boot services. This func-
tion may not be called if the image has already returned from its entry point ( EFI_IMAGE_ENTRY_POINT ) or if it
has loaded any child images that have not exited (all child images must exit before this image can exit).
Using Exit() is similar to returning from the image’s EFI_IMAGE_ENTRY_POINT except that Exit() may also return
additional ExitData.
When an application exits a compliant system, ﬁrmware frees the memory used to hold the image. The ﬁrmware also
frees its references to the ImageHandle and the handle itself. Before exiting, the application is responsible for freeing
any resources it allocated. This includes memory (pages and/or pool), open ﬁle system handles, and so forth. The only
exception to this rule is the ExitData buffer, which must be freed by the caller of EFI_BOOT_SERVICES.StartImage()
. (If the buffer is needed, ﬁrmware must allocate it by calling EFI_BOOT_SERVICES.AllocatePool() and must return
a pointer to it to the caller of StartImage().)
When an EFI boot service driver or runtime service driver exits, ﬁrmware frees the image only if the ExitStatus is an
error code; otherwise the image stays resident in memory. The driver must not return an error code if it has installed
any protocol handlers or other active callbacks into the system that have not (or cannot) be cleaned up. If the driver
exits with an error code, it is responsible for freeing all resources before exiting. This includes any allocated memory
(pages and/or pool), open ﬁle system handles, and so forth.
It is valid to call Exit() or UnloadImage() for an image that was loaded by EFI_BOOT_SERVICES.LoadImage() before
calling EFI_BOOT_SERVICES.StartImage() . This will free the image from memory without having started it.
IfImageHandle is a UEFI application, then all of the protocols that were opened by ImageHandle us-
ing the boot service EFI_BOOT_SERVICES.OpenProtocol() are automatically closed with the boot service
EFI_BOOT_SERVICES.CloseProtocol() . If ImageHandle is a UEFI boot service driver or UEFI runtime service
driver, and ExitStatus is an error code, then all of the protocols that were opened by ImageHandle using the boot ser-
vice OpenProtocol() are automatically closed with the boot service CloseProtocol(). If ImageHandle is a UEFI boot
service driver or UEFI runtime service driver, and ExitStatus is not an error code, then no protocols are automatically
closed by this service.
(Does not return.) Image exit. Control is returned to the StartImage() call that invoked the
image speciﬁed by ImageHandle .
EFI_SUCCESS The image speciﬁed by ImageHandle was unloaded. This condition only
occurs for images that have been loaded with LoadImage() but have not
been started with StartImage().
EFI_INV ALID_PARAMETER The image speciﬁed by ImageHandle has been loaded and started with
LoadImage() and StartImage(), but the image is not the currently execut-
ing image.
7.4. Image Services 197Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.4.6 EFI_BOOT_SERVICES.ExitBootServices()
Summary
Terminates all boot services.
Prototype
(EFIAPI *EFI_EXIT_BOOT_SERVICES) (
IN UINTN MapKey
);
ImageHandle Handle that identiﬁes the exiting image. Type EFI_HANDLE is deﬁned in the Image Execution Infor-
mation Table function description.
MapKey Key to the latest memory map.
The ExitBootServices() function is called by the currently executing UEFI OS loader image to termi-
nate all boot services. On success, the UEFI OSloader becomes responsible for the continued op-
eration of the system. All events from the EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES
and EFI_EVENT_GROUP_EXIT_BOOT_SERVICES event notiﬁcation groups as well as events of type
EVT_SIGNAL_EXIT_BOOT_SERVICES must be signaled before ExitBootServices() returns EFI_SUCCESS. The
events are only signaled once even if ExitBootServices() is called multiple times.
A UEFI OS loader must ensure that it has the system’s current memory map at the time it calls Ex-
itBootServices(). This is done by passing in the current memory map’s MapKey value as returned by
EFI_BOOT_SERVICES.GetMemoryMap() . Care must be taken to ensure that the memory map does not change be-
tween these two calls. It is suggested that GetMemoryMap() be called immediately before calling ExitBootServices().
If MapKey value is incorrect, ExitBootServices() returns EFI_INV ALID_PARAMETER and GetMemoryMap() with

ExitBootServices() must be called again. Firmware implementation may choose to do a partial shutdown of the boot
services during the ﬁrst call to ExitBootServices(). A UEFI OS loader should not make calls to any boot service
function other than Memory Allocation Services after the ﬁrst call to ExitBootServices().
On success, the UEFI OS loader owns all available memory in the system. In addition, the UEFI OS loader can
treat all memory in the map marked as EﬁBootServicesCode and EﬁBootServicesData as available free memory.
No further calls to boot service functions or EFI device-handle-based protocols may be used, and the boot services
watchdog timer is disabled. On success, several ﬁelds of the EFI System Table should be set to NULL. These include
ConsoleInHandle ,ConIn ,ConsoleOutHandle ,ConOut ,StandardErrorHandle ,StdErr , and BootServicesTable . In
addition, since ﬁelds of the EFI System Table are being modiﬁed, the 32-bit CRC for the EFI System Table must be
recomputed.
Firmware must guarantee the following order of processing:
• EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES handlers are called.
• Timer services are deactivated (timer event activity stopped).
• EVT_SIGNAL_EXIT_BOOT_SERVICES and EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES
handlers are called.
NOTE : The EVT_SIGNAL_EXIT_BOOT_SERVICES event type and EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES
event group are functionally equivalent. Firmware does not distinguish between the two while ordering the handlers.
Refer to EFI_EVENT_GROUP_EXIT_BOOT_SERVICES description in the
EFI_BOOT_SERVICES.CreateEventEx() section above for additional restrictions on EXIT_BOOT_SERVICES
handlers.
7.4. Image Services 198Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS Boot services have been terminated.
EFI_INV ALID_PARAMETER MapKey is incorrect.
7.5 Miscellaneous Boot Services
This section contains the remaining function deﬁnitions for boot services not deﬁned elsewhere but which are required
to complete the deﬁnition of the EFI environment. The Table, below, lists the Miscellaneous Boot Services Functions.
Table 7.37: Miscellaneous Boot Services Functions
SetWatchDogTimer Boot Resets and sets a watchdog timer used during boot services time.
Stall Boot Stalls the processor.
CopyMem Boot Copies the contents of one buffer to another buffer.
SetMem Boot Fills a buffer with a speciﬁed value.
GetNextMonotonicCount Boot Returns a monotonically increasing count for the platform.
InstallConﬁgurationTable Boot Adds, updates, or removes a conﬁguration table from the EFI Sys-
tem Table.
CalculateCrc32 Boot Computes and returns a 32-bit CRC for a data buffer.
TheEFI_BOOT_SERVICES.CalculateCrc32() service was added because there are several places in EFI that 32-bit
CRCs are used. These include the EFI System Table, the EFI Boot Services Table, the EFI Runtime Services Table,
and the GUID Partition Table (GPT) structures. The CalculateCrc32() service allows new 32-bit CRCs to be computed,
and existing 32-bit CRCs to be validated.
7.5.1 EFI_BOOT_SERVICES.SetWatchdogTimer()
Summary
Sets the system’s watchdog timer.
Prototype
typedef
(EFIAPI *EFI_SET_WATCHDOG_TIMER) ((
IN UINTN Timeout,
IN UINT64 WatchdogCode,
IN UINTN DataSize,
IN CHAR16 *WatchdogData OPTIONAL
);
Timeout The number of seconds to set the watchdog timer to. A value of zero disables the timer.
WatchdogCode The numeric code to log on a watchdog timer timeout event. The ﬁrmware reserves codes 0x0000 to
0xFFFF. Loaders and operating systems may use other timeout codes.
DataSize The size, in bytes, of WatchdogData .
7.5. Miscellaneous Boot Services 199Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
WatchdogData A data buffer that includes a Null-terminated string, optionally followed by additional binary data.
The string is a description that the call may use to further indicate the reason to be logged with a watchdog
event.
The SetWatchdogTimer() function sets the system’s watchdog timer.
If the watchdog timer expires, the event is logged by the ﬁrmware. The system may then either reset with the Runtime
Service ResetSystem() or perform a platform speciﬁc action that must eventually cause the platform to be reset. The
watchdog timer is armed before the ﬁrmware’s boot manager invokes an EFI boot option. The watchdog must be set
to a period of 5 minutes. The EFI Image may reset or disable the watchdog timer as needed. If control is returned to
the ﬁrmware’s boot manager, the watchdog timer must be disabled.
The watchdog timer is only used during boot services. On successful completion of
EFI_BOOT_SERVICES.ExitBootServices() the watchdog timer is disabled.
The accuracy of the watchdog timer is +/- 1 second from the requested Timeout.
EFI_SUCCESS The timeout has been set.
EFI_INV ALID_PARAMETER The supplied WatchdogCode is invalid.
EFI_UNSUPPORTED The system does not have a watchdog timer.
EFI_DEVICE_ERROR The watch dog timer could not be programmed due to a hardware error.
7.5.2 EFI_BOOT_SERVICES.Stall()
Summary
Induces a ﬁne-grained stall.
Prototype
typedef
(EFIAPI *EFI_STALL) (
IN UINTN Microseconds
)
Microseconds The number of microseconds to stall execution.
The Stall() function stalls execution on the processor for at least the requested number of microseconds. Execution of
the processor is notyielded for the duration of the stall.
EFI_SUCCESS Execution was stalled at least the requested number of Microseconds .
7.5. Miscellaneous Boot Services 200Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.5.3 EFI_BOOT_SERVICES.CopyMem()
Summary
TheCopyMem() function copies the contents of one buffer to another buffer.
Prototype
typedef
VOID
(EFIAPI *EFI_COPY_MEM) (
IN VOID *Destination,
IN VOID *Source,
IN UINTN Length
);
Destination Pointer to the destination buffer of the memory copy.
Source Pointer to the source buffer of the memory copy.
Length Number of bytes to copy from Source to Destination.
The CopyMem() function copies Length bytes from the buffer Source to the buffer Destination .
The implementation of CopyMem() must be reentrant, and it must handle overlapping Source andDestination buffers.
This means that the implementation of CopyMem() must choose the correct direction of the copy operation based on
the type of overlap that exists between the Source andDestination buffers. If either the Source buffer or the Destination
buffer crosses the top of the processor’s address space, then the result of the copy operation is unpredictable.
The contents of the Destination buffer on exit from this service must match the contents of the Source buffer on entry
to this service. Due to potential overlaps, the contents of the Source buffer may be modiﬁed by this service. The
following rules can be used to guarantee the correct behavior:
1. If Destination andSource are identical, then no operation should be performed.
2. If Destination >Source andDestination < (Source +Length ), then the data should be copied from the Source
buffer to the Destination buffer starting from the end of the buffers and working toward the beginning of the
buffers.
3. Otherwise, the data should be copied from the Source buffer to the Destination buffer starting from the beginning
of the buffers and working toward the end of the buffers.
None.
7.5.4 EFI_BOOT_SERVICES.SetMem()
Summary
TheSetMem() function ﬁlls a buffer with a speciﬁed value.
Prototype
typedef
VOID
EFIAPI*EFI_SET_MEM) (
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IN VOID *Buffer,
IN UINT8 Value
);
Buffer Pointer to the buffer to ﬁll.
Size Number of bytes in Buffer to ﬁll.
Value Value to ﬁll Buffer with.
This function ﬁlls Size bytes of*Buffer*with Value . The implementation of SetMem() must be reentrant. If Buffer
crosses the top of the processor’s address space, the result of the SetMem() operation is unpredictable.
None.
7.5.5 EFI_BOOT_SERVICES.GetNextMonotonicCount()
Summary
Returns a monotonically increasing count for the platform.
Prototype
typedef
(EFIAPI *EFI_GET_NEXT_MONOTONIC_COUNT) (
OUT UINT64 *Count
);
Count Pointer to returned value.
The GetNextMonotonicCount() function returns a 64-bit value that is numerically larger then the last time the function
was called.
The platform’s monotonic counter is comprised of two parts: the high 32 bits and the low 32 bits. The low 32-bit value
is volatile and is reset to zero on every system reset. It is increased by 1 on every call to GetNextMonotonicCount().
The high 32-bit value is nonvolatile and is increased by one on whenever the system resets or the low 32-bit counter
overﬂows.

None.
Summary
Prototype
typedef
);
overﬂows.
EFI_SUCCESS The next monotonic count was returned.
EFI_DEVICE_ERROR The device is not functioning properly.
EFI_INV ALID_PARAMETER Count is NULL.
7.5. Miscellaneous Boot Services 202Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.5.6 EFI_BOOT_SERVICES.InstallConﬁgurationTable()
Summary
Adds, updates, or removes a conﬁguration table entry from the EFI System Table.
Prototype
typedef
(EFIAPI *EFI_INSTALL_CONFIGURATION_TABLE) (
IN EFI_GUID *Guid,
IN VOID *Table
);
Guid A pointer to the GUID for the entry to add, update, or remove.
Table A pointer to the conﬁguration table for the entry to add, update, or remove. May be NULL.
The InstallConﬁgurationTable() function is used to maintain the list of conﬁguration tables that are stored in the EFI
System Table. The list is stored as an array of (GUID, Pointer) pairs. The list must be allocated from pool memory
with PoolType set to EﬁRuntimeServicesData.
IfGuid is NULL, EFI_INV ALID_PARAMETER is returned. If Guid is valid, there are four possibilities:
• IfGuid is not present in the System Table, and Table is not NULL, then the (Guid, Table) pair is added to the
System Table. See Note below.
• IfGuid is not present in the System Table, and Table is NULL, then EFI_NOT_FOUND is returned.
• IfGuid is present in the System Table, and Table is not NULL, then the (Guid, Table) pair is updated with the
new Table value.
• IfGuid is present in the System Table, and Table is NULL , then the entry associated with Guid is removed from
If an add, modify, or remove operation is completed, then EFI_SUCCESS is returned.
Note :If there is not enough memory to perform an add operation, then EFI_OUT_OF_RESOURCES is returned .
EFI_SUCCESS The ( Guid, Table ) pair was added, updated, or removed.
EFI_INV ALID_PARAMETER Guid is NULL.
EFI_NOT_FOUND An attempt was made to delete a nonexistent entry.
EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation.
7.5. Miscellaneous Boot Services 203Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
7.5.7 EFI_BOOT_SERVICES.CalculateCrc32()
Summary
Computes and returns a 32-bit CRC for a data buffer.
Prototype
typedef
(EFIAPI *EFI_CALCULATE_CRC32)
IN VOID *Data,
OUT UINT32 *Crc32
);
Data A pointer to the buffer on which the 32-bit CRC is to be computed.
DataSize The number of bytes in the buffer Data .
Crc32 The 32-bit CRC that was computed for the data buffer speciﬁed by Data and DataSize.
This function computes the 32-bit CRC for the data buffer speciﬁed by Data and *DataSize . If the 32-bit CRC is
computed, then it is returned in Crc32 and EFI_SUCCESS is returned.
IfData is NULL, then EFI_INV ALID_PARAMETER is returned.
IfCrc32 is NULL, then EFI_INV ALID_PARAMETER is returned.
IfDataSize is 0, then EFI_INV ALID_PARAMETER is returned.
EFI_SUCCESS The 32-bit CRC was computed for the data buffer and returned in Crc32 .
EFI_INV ALID_PARAMETER Data is NULL.
EFI_INV ALID_PARAMETER Crc32 is NULL.
EFI_INV ALID_PARAMETER DataSize is 0.
7.5. Miscellaneous Boot Services 204CHAPTER
EIGHT
SERVICES — RUNTIME SERVICES
This section discusses the fundamental services that are present in a compliant system. The services are deﬁned by
interface functions that may be used by code running in the EFI environment. Such code may include protocols that
manage device access or extend platform capability, as well as applications running in the preboot environment and
EFI OS loaders.
Two types of services are described here:
•Boot Services . Functions that are available before a successful call to
EFI_BOOT_SERVICES.ExitBootServices(), described in EFI_BOOT_SERVICES.ExitBootServices() .
•Runtime Services . Functions that are available before and after any call to ExitBootServices() . These functions
ory. On entry, an image is provided a pointer to a system table which contains the Boot Services dispatch table and
the UEFI OS loader, however, may or may not choose to call ExitBootServices(). This choice may in part depend upon
whether or not such code is designed to make continued use of EFI boot services or the boot services environment.
The rest of this section discusses individual functions. Runtime Services fall into these categories:
• Runtime Rules and Restrictions ( Runtime Services Rules and Restrictions )
• Variable Services ( Exception for Machine Check, INIT, and NMI )
• Time Services ( Time Services )
• Virtual Memory Services ( Virtual Memory Services )
• Miscellaneous Services ( Miscellaneous Runtime Services )
205Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
8.1 Runtime Services Rules and Restrictions
All of the Runtime Services may be called with interrupts enabled if desired. The Runtime Service functions will
internally disable interrupts when it is required to protect access to hardware resources. The interrupt enable control
bit will be returned to its entry state after the access to the critical hardware resources is complete.
All callers of Runtime Services are restricted from calling the same or certain other Runtime Service functions prior
to the completion and return of a previous Runtime Service call. These restrictions apply to:
• Runtime Services that have been interrupted
• Runtime Services that are active on another processor.
Callers are prohibited from using certain other services from another processor or on the same processor following an
interrupt as speciﬁed in Rules for Reentry Into Runtime Services . For this table ‘Busy’ is deﬁned as the state when a
Runtime Service has been entered and has not returned to the caller.
The consequence of a caller violating these restrictions is undeﬁned except for certain special cases described below.
Table 8.1: Rules for Reentry Into Runtime Services
If previous call is busy in Forbidden to call
Any SetVirtualAddressMap()
ConvertPointer() ConvertPointer()
SetVariable(),
UpdateCapsule(),
SetTime()
SetWakeupTime(),
GetNextHighMonotonicCount()ResetSystem()
GetVariable()
GetNextVariableName()
SetVariable()
QueryVariableInfo()
UpdateCapsule()
QueryCapsuleCapabilities()
GetNextHighMonotonicCount()GetVariable(),
GetNextVariableName(),
QueryVariableInfo(),
QueryCapsuleCapabilities(),
GetNextHighMonotonicCount()
GetTime()
SetTime()
GetWakeupTime()
SetWakeupTime()GetTime()
SetTime()
SetWakeupTime()
If any EFI_RUNTIME_SERVICES* calls are not supported for use by the OS at runtime, an
EFI_RT_PROPERTIES_TABLE conﬁguration table should be published describing which runtime services are
supported at runtime ( EFI Conﬁguration Table & Properties Table ). Note that this is merely a hint to the OS, which
it is free to ignore, and so the platform is still required to provide callable implementations of unsupported runtime
services that simply return EFI_UNSUPPORTED.
8.1. Runtime Services Rules and Restrictions 206Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
8.1.1 Exception for Machine Check, INIT, and NMI
Certain asynchronous events (e.g., NMI on IA-32 and x64 systems, Machine Check and INIT on Itanium systems) can
not be masked and may occur with any setting of interrupt enabled. These events also may require OS level handler’s
involvement that may involve the invocation of some of the runtime services (see below).

SetTime()
If SetVirtualAddressMap() has been called, all calls to runtime services after Machine Check, INIT, or NMI, must be
made using the virtual address map set by that call.
A Machine Check may have interrupted a runtime service (see below). If the OS determines that the Machine Check
is recoverable, the OS level handler must follow the normal restrictions in the Table Rules for Reentry Into Runtime
Services .
If the OS determines that the Machine Check is non-recoverable, the OS level handler may ignore the normal restric-
tions and may invoke the runtime services described in the Table Functions that may be called after Machine Check,
INIT and NMI even in the case where a previous call was busy. The system ﬁrmware will honor the new runtime
service call(s) and the operation of the previous interrupted call is not guaranteed. Any interrupted runtime functions
will not be restarted.
The INIT and NMI events follow the same restrictions.
NOTE :On Itanium systems, the OS Machine Check Handler must not call ResetSystem(). If a reset is required, the
OS Machine Check Handler may request SAL to reset upon return to SAL_CHECK .
The platform implementations are required to clear any runtime services in progress in order to enable the OS handler
to invoke these runtime services even in the case where a previous call was busy. In this case, the proper operation of
the original interrupted call is not guaranteed.
Table 8.2: Functions that may be called after Machine Check, INIT and
NMI
Function Called after Machine Check, INIT and NMI
GetTime() Yes, even if previously busy
GetVariable() Yes, even if previously busy
GetNextVariableName() Yes, even if previously busy
QueryVariableInfo() Yes, even if previously busy
SetVariable() Yes, even if previously busy
UpdateCapsule() Yes, even if previously busy
QueryCapsuleCapabilities() Yes, even if previously busy
ResetSystem() Yes, even if previously busy
8.2 Variable Services
Variables are deﬁned as key/value pairs that consist of identifying information plus attributes (the key) and arbitrary
data (the value). Variables are intended for use as a means to store data that is passed between the EFI environment
implemented in the platform and EFI OS loaders and other applications that run in the EFI environment.
Although the implementation of variable storage is not deﬁned in this speciﬁcation, variables must be persistent in
most cases. This implies that the EFI implementation on a platform must arrange it so that variables passed in for
storage are retained and available for use each time the system boots, at least until they are explicitly deleted or
overwritten. Provision of this type of nonvolatile storage may be very limited on some platforms, so variables should
be used sparingly in cases where other means of communicating information cannot be used.
The Table below lists the variable services functions described in this section:
8.2. Variable Services 207Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 8.3: Variable Services Functions
GetVariable Runtime Returns the value of a variable.
GetNextVariableName Runtime Enumerates the current variable names.
SetVariable Runtime Sets the value of a variable.
QueryVariableInfo Runtime Returns information about the EFI variables
8.2.1 GetVariable()
Summary
Returns the value of a variable.
Prototype
typedef
GetVariable (
IN CHAR16 *VariableName,
IN EFI_GUID *VendorGuid,
OUT UINT32 *Attributes OPTIONAL,
IN OUT UINTN *DataSize,
OUT VOID *Data OPTIONAL
);
VariableName A Null-terminated string that is the name of the vendor’s variable.
VendorGuid A unique identiﬁer for the vendor. Type EFI_GUID is deﬁned in the
Attributes If not NULL, a pointer to the memory location to return the attributes bitmask for the variable. See
“Related Deﬁnitions.” If not NULL, then Attributes is set on output both when EFI_SUCCESS and when
EFI_BUFFER_TOO_SMALL is returned.
DataSize On input, the size in bytes of the return Data buffer. On output the size of data returned in Data.
Data The buffer to return the contents of the variable. May be NULL with a zero DataSize in order to determine the
size buffer needed.
// Variable Attributes
#define EFI_VARIABLE_NON_VOLATILE 0x00000001
#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002
#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004
#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008 \
//This attribute isidentified by the mnemonic 'HR' elsewhere
//inthis specification.
#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010
//NOTE: EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS isdeprecated
//andshould be considered reserved.
#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS \0x00000020
#define EFI_VARIABLE_APPEND_WRITE 0x00000040
#define EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS 0x00000080
8.2. Variable Services 208Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//This attribute indicates that the variable payload begins
//withan EFI_VARIABLE_AUTHENTICATION_3 structure, and
//potentially more structures asindicated by fields of this
//structure. See definition below and inSetVariable().
Each vendor may create and manage its own variables without the risk of name conﬂicts by using a unique
VendorGuid. When a variable is set its Attributes are supplied to indicate how the data variable should be
stored and maintained by the system. The attributes affect when the variable may be accessed and volatil-
ity of the data. If EFI_BOOT_SERVICES.ExitBootServices() has already been executed, data variables with-
out the EFI_V ARIABLE_RUNTIME_ACCESS attribute set will not be visible to GetVariable() and will return an
EFI_NOT_FOUND error.
If the Data buffer is too small to hold the contents of the variable, the error EFI_BUFFER_TOO_SMALL is returned
and DataSize is set to the required buffer size to obtain the data.
The EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS and the EFI_V ARIABLE_ AU-
THENTICATED_WRITE_ACCESS attributes may both be set in the returned Attributes bitmask parameter of a
GetVariable() call, though it should be noted that the EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS at-
tribute is deprecated and should no longer be used. The EFI_V ARIABLE_APPEND_WRITE attribute will never be
set in the returned Attributes bitmask parameter.
Variables stored with the EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS attribute set will return
metadata in addition to variable data when GetVariable() is called. If a GetVariable() call indicates that this attribute
is set, the GetVariable() payload must be interpreted according to the metadata headers. In addition to the headers
described in SetVariable(), the following header is used to indicate what certiﬁcate may be currently associated with a
variable.
//
// EFI_VARIABLE_AUTHENTICATION_3_CERT_ID descriptor
//
// An extensible structure to identify a unique x509 cert
// associated witha given variable
//
#define EFI_VARIABLE_AUTHENTICATION_3_CERT_ID_SHA256 1
UINT8 Type;
UINT32 IdSize;
// UINT8 Id[IdSize];
} EFI_VARIABLE_AUTHENTICATION_3_CERT_ID;
Type Identiﬁes the type of ID that is returned and how the ID should be interpreted.
IdSize Indicates the size of the Id buffer that follows this ﬁeld in the structure.
Id (Not a formal structure member) This is a unique identiﬁer for the associated certiﬁcate as deﬁned by the Type
ﬁeld. For CERT_ID_SHA256, the buffer will be a SHA-256 digest of the tbsCertiﬁcate (To Be Signed Certiﬁcate
data deﬁned in x509) data for the cert.
When the attribute EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS is set, the Data buffer shall be
interpreted as follows:
// NOTE: “||” indicates concatenation.
// Example: EFI_V ARIABLE_AUTHENTICATION_3_TIMESTAMP_TYPE
8.2. Variable Services 209Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_V ARIABLE_AUTHENTICATION_3 || EFI_TIME || EFI_V ARIABLE_AUTHENTICATION_3_CERT_ID ||
Data
// Example: EFI_VARIABLE_AUTHENTICATION_3_NONCE_TYPE
EFI_V ARIABLE_AUTHENTICATION_3 || EFI_V ARIABLE_AUTHENTICATION_3_NONCE ||
EFI_V ARIABLE_AUTHENTICATION_3_CERT_ID || Data
NOTE :The MetadataSize ﬁeld of the EFI_VARIABLE_AUTHENTICATION_3 structure in each of these examples
does not include any WIN_CERTIFICATE_UEFI_GUID structures. These structures are used in the SetVariable()
interface, not GetVariable(), as described in the above examples .
EFI_SUCCESS The function completed successfully.
EFI_NOT_FOUND The variable was not found.
EFI_BUFFER_TOO_SMALL The DataSize is too small for the result. DataSize has been updated with
the size needed to complete the request. If Attributes is not NULL, then the

Data
attributes bitmask for the variable has been stored to the memory location
pointed-to by Attributes .
EFI_INV ALID_PARAMETER VariableName is NULL.
EFI_INV ALID_PARAMETER VendorGuid is NULL.
EFI_INV ALID_PARAMETER DataSize is NULL.
EFI_INV ALID_PARAMETER TheDataSize is not too small and Data is NULL.
EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error.
EFI_SECURITY_VIOLATION The variable could not be retrieved due to an authentication failure.
EFI_UNSUPPORTED After ExitBootServices() has been called, this return code may be returned if
no variable storage is supported. The platform should describe this runtime
service as unsupported at runtime via an EFI_RT_PROPERTIES_TABLE
8.2.2 GetNextVariableName()
Summary
Enumerates the current variable names.
Prototype
typedef
GetNextVariableName (
IN OUT UINTN *VariableNameSize,
IN OUT CHAR16 *VariableName,
IN OUT EFI_GUID *VendorGuid
);
VariableNameSize The size of the VariableName buffer. The size must be large enough to ﬁt input string supplied in
VariableName buffer.
VariableName On input, supplies the last VariableName that was returned by * GetNextVariableName(). On output,
returns the Null-terminated string of the current variable.
VendorGuid On input, supplies the last VendorGuid that was returned by GetNextVariableName(). On
output, returns the VendorGuid of the current variable. Type EFI_GUID is deﬁned in the
8.2. Variable Services 210Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetNextVariableName() is called multiple times to retrieve the VariableName and VendorGuid of all variables cur-
rently available in the system. On each call to GetNextVariableName() the previous results are passed into the inter-
face, and on output the interface returns the next variable name data. When the entire variable list has been returned,
the error EFI_NOT_FOUND is returned.
Note that if EFI_BUFFER_TOO_SMALL is returned, the VariableName buffer was too small for the next variable.
When such an error occurs, the VariableNameSize is updated to reﬂect the size of buffer needed. In all cases when
calling GetNextVariableName() the VariableNameSize must not exceed the actual buffer size that was allocated for
VariableName. The VariableNameSize must not be smaller the size of the variable name string passed to GetNextVari-
ableName() on input in the VariableName buffer.
To start the search, a Null-terminated string is passed in VariableName; that is, VariableName is a pointer to a Null
character. This is always done on the initial call to GetNextVariableName(). When VariableName is a pointer to a Null
character, VendorGuid is ignored. GetNextVariableName() cannot be used as a ﬁlter to return variable names with a
speciﬁc GUID. Instead, the entire list of variables must be retrieved, and the caller may act as a ﬁlter if it chooses. Calls
toSetVariable() between calls to GetNextVariableName() may produce unpredictable results. If a VariableName buffer
on input is not a Null-terminated string, EFI_INV ALID_PARAMETER is returned. If input values of VariableName
andVendorGuid are not a name and GUID of an existing variable, EFI_INV ALID_PARAMETER is returned.
Once EFI_BOOT_SERVICES.ExitBootServices() is performed, variables that are only visible during boot services will
no longer be returned. To obtain the data contents or attribute for a variable returned by GetNextVariableName(), the
GetVariable() interface is used.
EFI_NOT_FOUND The next variable was not found.
EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the result. VariableNameSize has
been updated with the size needed to complete the request.
EFI_INV ALID_PARAMETER VariableNameSize is NULL.
EFI_INV ALID_PARAMETER The input values of VariableName andVendorGuid are not a name and
GUID of an existing variable.
EFI_INV ALID_PARAMETER Null-terminator is not found in the ﬁrst VariableNameSize bytes of the input
EFI_DEVICE_ERROR The variable name could not be retrieved due to a hardware error.
EFI_UNSUPPORTED After ExitBootServices() has been called, this return code may be
returned if no variable storage is supported. The platform should
describe this runtime service as unsupported at runtime via an
EFI_RT_PROPERTIES_TABLE conﬁguration table.
8.2. Variable Services 211Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
8.2.3 SetVariable()
Summary
Sets the value of a variable. This service can be used to create a new variable, modify the value of an existing variable,
or to delete an existing variable.
Prototype
typedef
SetVariable (
IN UINT32 Attributes,
IN VOID *Data
);
VariableName A Null-terminated string that is the name of the vendor’s variable. Each VariableName is unique for
each VendorGuid .VariableName must contain 1 or more characters. If VariableName is an empty string, then
Attributes Attributes bitmask to set for the variable. Refer to the GetVariable() function description.
DataSize The size in bytes of the Data buffer. Unless the EFI_V ARIABLE_APPEND_WRITE,
EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS, EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS,
or EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute is set, a size of zero
causes the variable to be deleted. When the EFI_V ARIABLE_APPEND_WRITE attribute is set, then a
SetVariable() call with a DataSize of zero will not cause any change to the variable value (the timestamp
associated with the variable may be updated however, even if no new data value is provided;see the description
of the EFI_V ARIABLE_AUTHENTICATION_2 descriptor below). In this case the DataSize will not be zero
since the EFI_V ARIABLE_AUTHENTICATION_2 descriptor will be populated).
Data The contents for the variable.
// NOTE: This interface is deprecated and should no longer be
used!
//
// EFI_VARIABLE_AUTHENTICATION descriptor
//
// A counter-based authentication method descriptor template
//
UINT64 MonotonicCount;
WIN_CERTIFICATE_UEFI_GUID AuthInfo;
} EFI_VARIABLE_AUTHENTICATION;
8.2. Variable Services 212Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
MonotonicCount Included in the signature of AuthInfo. Used to ensure freshness/no replay. Incremented during
each “Write” access.
AuthInfo Provides the authorization for the variable access. It is a signature across the variable data and the Mono-
tonic Count value. Caller uses Private key that is associated with a public key that has been provisioned via the
key exchange.
//
// EFI_VARIABLE_AUTHENTICATION_2 descriptor
//
// A time-based authentication method descriptor template
//
EFI_TIME TimeStamp;
} EFI_VARIABLE_AUTHENTICATION_2;
TimeStamp Time associated with the authentication descriptor. For the TimeStamp value, components Pad1 ,
Nanosecond ,TimeZone ,Daylight andPad2 shall be set to 0. This means that the time shall always be expressed
in GMT.
AuthInfo Provides the authorization for the variable access. Only a CertType of EFI_CERT_TYPE_PKCS7_GUID
is accepted.
//
// EFI_VARIABLE_AUTHENTICATION_3 descriptor
//
// An extensible implementation of the Variable Authentication
// structure.
//
#define EFI_VARIABLE_AUTHENTICATION_3_TIMESTAMP_TYPE 1
#define EFI_VARIABLE_AUTHENTICATION_3_NONCE_TYPE 2
UINT8 Version;
UINT32 MetadataSize;
} EFI_VARIABLE_AUTHENTICATION_3;
Version This ﬁeld is used in case the EFI_V ARIABLE_AUTHENTICATION_3 structure itself ever requires updat-
ing. For now, it is hardcoded to “0x1”.
Type Declares what structure immediately follows this structure in the Variable Data payload. For
EFI_V ARIABLE_AUTHENTICATION_3_TIMESTAMP_TYPE, it will be an instance of EFI_TIME (for
the TimeStamp). For EFI_V ARIABLE_AUTHENTICATION_3_NONCE_TYPE the structure will be an
instance of EFI_V ARIABLE_AUTHENTICATION_3_NONCE. This structure is deﬁned below. Note
that none of these structures contains a WIN_CERTIFICATE_UEFI_GUID structure. See Using the
EFI_VARIABLE_AUTHENTICATION_3 descriptor for an explanation of structure sequencing.
MetadataSize Declares the size of all variable authentication metadata (data related to the authentication of the
variable that is not variable data itself), including this header structure, and type-speciﬁc structures (eg.

EFI_V ARIABLE_AUTHENTICATION_3_NONCE), and any WIN_CERTIFICATE_UEFI_GUID structures.
Flags
Bitﬁeld indicating any optional conﬁguration for this call. Currently, the only deﬁned value is: #deﬁne
EFI_V ARIABLE_ENHANCED_AUTH_FLAG_UPDATE_CERT 0x00000001 The presence of this ﬂag on
SetVariable() indicates that there are two instances of the WIN_CERTIFICATE_UEFI_GUID structure
8.2. Variable Services 213Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
following the type-speciﬁc structures. The ﬁrst instance describes the new cert to be set as the authority for the
variable. The second is the signed data to authorize the current updated.
NOTE: All other bits are currently Reserved on SetVariable().
NOTE : All ﬂags are reserved on GetVariable().
//
// EFI_VARIABLE_AUTHENTICATION_3_NONCE descriptor
//
// A nonce-based authentication method descriptor template. This
// structure will always be followed by a
// WIN_CERTIFICATE_UEFI_GUID structure.
//
UINT32 NonceSize;
// UINT8 Nonce[NonceSize];
} EFI_VARIABLE_AUTHENTICATION_3_NONCE;
NonceSize Indicates the size of the Nonce buffer that follows this ﬁeld in the structure. Must not be 0.
Nonce (Not a formal structure member) Unique, random value that guarantees a signed payload cannot be shared
between multiple machines or machine families. On SetVariable(), if the Nonce ﬁeld is all 0’s, the host ma-
chine will try to use an internally generated random number. Will return EFI_UNSUPPORTED if not possible.
Also, on SetVariable() if the variable already exists and the nonce is identical to the current nonce, will return
EFI_INV ALID_PARAMETER.
Variables are stored by the ﬁrmware and may maintain their values across power cycles. Each vendor may create and
manage its own variables without the risk of name conﬂicts by using a unique VendorGuid .
Each variable has Attributes that deﬁne how the ﬁrmware stores and maintains the data value. If the
EFI_V ARIABLE_NON_VOLATILE attribute is not set, the ﬁrmware stores the variable in normal memory and it
is not maintained across a power cycle. Such variables are used to pass information from one component to another.
An example of this is the ﬁrmware’s language code support variable. It is created at ﬁrmware initialization time for
access by EFI components that may need the information, but does not need to be backed up to nonvolatile storage.
EFI_V ARIABLE_NON_VOLATILE variables are stored in ﬁxed hardware that has a limited storage capacity; some-
times a severely limited capacity. Software should only use a nonvolatile variable when absolutely necessary. In
addition, if software uses a nonvolatile variable it should use a variable that is only accessible at boot services time if
possible.
A variable must contain one or more bytes of Data. Unless the EFI_V ARIABLE_APPEND_WRITE,
EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS, or EFI_V ARIABLE_ENHANCED
_AUTHENTICATED_ACCESS attribute is set (see below), using SetVariable() with a DataSize of zero will cause the
entire variable to be deleted. The space consumed by the deleted variable may not be available until the next power
cycle.
If a variable with matching name, GUID, and attributes already exists, its value is updated.
The Attributes have the following usage rules:
• If a preexisting variable is rewritten with different attributes, SetVariable() shall not modify the variable and
shall return EFI_INV ALID_PARAMETER. The only exception to this is when the only attribute differing is
8.2. Variable Services 214Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_V ARIABLE_APPEND_WRITE. In such cases the call’s successful outcome or not is determined by the
actual value being written. There are two exceptions to this rule:
— If a preexisting variable is rewritten with no access attributes speciﬁed, the variable will be deleted.
— EFI_V ARIABLE_APPEND_WRITE attribute presents a special case. It is acceptable to rewrite the variable
with or without EFI_V ARIABLE_APPEND_WRITE attribute.
• Setting a data variable with no access attributes causes it to be deleted.
• EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated and should not be used. Platforms
should return EFI_UNSUPPORTED if a caller to SetVariable() speciﬁes this attribute.
• Unless the EFI_V ARIABLE_APPEND_WRITE, EFI_V ARIABLE_TIME_BASED_AUTHENTICATED
_WRITE_ACCESS, or EFI_V ARIABLE_ENHANCED_AUTHENTICATED_WRITE_ACCESS attribute is
set, setting a data variable with zero DataSize speciﬁed, causes it to be deleted.
• Runtime access to a data variable implies boot service access. Attributes that have
EFI_V ARIABLE_RUNTIME_ACCESS set must also have EFI_V ARIABLE_BOOTSERVICE_ACCESS
set. The caller is responsible for following this rule.
• Once EFI_BOOT_SERVICES.ExitBootServices() is performed, data variables that did not have
EFI_V ARIABLE_RUNTIME_ACCESS set are no longer visible to GetVariable() .
• Once ExitBootServices() is performed, only variables that have EFI_V ARIABLE_RUNTIME_ACCESS and
EFI_V ARIABLE_NON_VOLATILE set can be set with SetVariable(). Variables that have runtime access
but that are not nonvolatile are read-only data variables once ExitBootServices() is performed. When the
EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS attribute is set in a SetVariable() call, the au-
thentication shall use the EFI_V ARIABLE_AUTHENTICATION_3 descriptor, which will be followed by any
descriptors indicated in the Type and Flags ﬁelds.
• When the EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute is set in a Set-
Variable() call, the authentication shall use the EFI_V ARIABLE_AUTHENTICATION_2 descriptor.
• If both the EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS and the
EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS attribute are set in a SetVariable() call,
then the ﬁrmware must return EFI_INV ALID_PARAMETER.
• If the EFI_V ARIABLE_APPEND_WRITE attribute is set in a SetVariable() call, then any existing variable
value shall be appended with the value of the Data parameter. If the ﬁrmware does not support the append
operation, then the SetVariable() call shall return EFI_INV ALID_PARAMETER.
• If the EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute is set in
a SetVariable() call, and ﬁrmware does not support signature type of the certiﬁcate included in
the EFI_V ARIABLE_AUTHENTICATION_2 descriptor, then the SetVariable() call shall return
EFI_INV ALID_PARAMETER. The list of signature types supported by the ﬁrmware is deﬁned by the
SignatureSupport variable. Signature type of the certiﬁcate is deﬁned by its digest and encryption algorithms.
• If the EFI_V ARIABLE_HARDWARE_ERROR_RECORD attribute is set, VariableName andVendorGuid must
comply with the rules stated in Hardware Error Record Variables andHardware Error Record Persistence
Usage . Otherwise, the SetVariable() call shall return EFI_INV ALID_PARAMETER.
•Globally Deﬁned Variables must be created with the attributes deﬁned in the Table Global Variables . If a
globally deﬁned variable is created with the wrong attributes, the result is indeterminate and may vary between
implementations.
• If using the EFI_V ARIABLE_ENHANCED_AUTHETICATED_ACCESS interface to update the cert authority
for a given variable, it is valid for the Data region of the payload to be empty. This would update the cert without
modifying the data itself. If the Data region is empty AND no NewCert is speciﬁed, the variable will be deleted
(assuming all authorizations are veriﬁed).
8.2. Variable Services 215Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Secure Boot Policy Variable must be created with the EFI_V ARIABLE_TIME_BASED_AUTHENTICATED
_WRITE_ACCESS attribute set, and the authentication shall use the EFI_V ARIABLE_AUTHENTICATION_2
descriptor. If the appropriate attribute bit is not set, then the ﬁrmware shall return
The only rules the ﬁrmware must implement when saving a nonvolatile variable is that it has actually been saved to
nonvolatile storage before returning EFI_SUCCESS, and that a partial save is not performed. If power fails during a
call to SetVariable() the variable may contain its previous value, or its new value. In addition there is no read, write,
or delete security protection.
To delete a variable created with the EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS at-
tribute, SetVariable must be used with attributes matching the existing variable and the DataSize set to the size of
theAuthInfo descriptor. The Data buffer must contain an instance of the AuthInfo descriptor which will be validated
according to the steps in the appropriate section above referring to updates of Authenticated variables. An attempt
to delete a variable created with the EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS at-
tribute for which the prescribed AuthInfo validation fails or when called using DataSize of zero will fail with an
EFI_SECURITY_VIOLATION status.

To delete a variable created with the EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS attribute, Set-
Variable must be used with attributes matching the existing variable and the DataSize set to the size of the
entire payload including all descriptors and certiﬁcates. The Data buffer must contain an instance of the
EFI_V ARIABLE_AUTHENTICATION_3 descriptor which will indicate how to validate the payload according to the
description in Using the EFI_VARIABLE_AUTHENTICATION_3 descriptor . An attempt to delete a variable created
with the EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS attribute for which the prescribed validation
fails or when called using DataSize of zero will fail with an EFI_SECURITY_VIOLATION status.
EFI_SUCCESS The ﬁrmware has successfully stored the variable and its data as deﬁned by
the Attributes.
EFI_INV ALID_PARAMETER An invalid combination of attribute bits, name, and GUID was supplied, or
theDataSize exceeds the maximum allowed.
EFI_INV ALID_PARAMETER VariableName is an empty string.
EFI_OUT_OF_RESOURCES Not enough storage is available to hold the variable and its data.
EFI_DEVICE_ERROR The variable could not be saved due to a hardware failure.
EFI_WRITE_PROTECTED The variable in question is read-only.
EFI_WRITE_PROTECTED The variable in question cannot be deleted.
EFI_SECURITY_VIOLATION
The variable could not be written due to
EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS or
EFI_V ARI ABLE_TIME_BASED_AUTHENTICATED_WRITE_ACESS
being set, but the payload does NOT pass the validation check carried out
by the ﬁrmware.
EFI_NOT_FOUND The variable trying to be updated or deleted was not found.
EFI_UNSUPPORTED This call is not supported by this platform at the time the call is made. The
platform should describe this runtime service as unsupported at runtime via
an EFI_RT_PROPERTIES_TABLE conﬁguration table.
8.2. Variable Services 216Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
8.2.4 QueryVariableInfo()
Summary
Returns information about the EFI variables.
Prototype
typedef
QueryVariableInfo (
OUT UINT64 *MaximumVariableStorageSize,
OUT UINT64 *RemainingVariableStorageSize,
OUT UINT64 *MaximumVariableSize
);
Attributes Attributes bitmask to specify the type of variables on which to return information. Refer to the GetVari-
able() function description. The EFI_V ARIABLE_APPEND_WRITE attribute, if set in the attributes bitmask,
will be ignored.
MaximumVariableStorageSize On output the maximum size of the storage space available for the EFI variables
associated with the attributes speciﬁed.
RemainingVariableStorageSize Returns the remaining size of the storage space available for EFI variables associ-
ated with the attributes speciﬁed.
MaximumVariableSize Returns the maximum size of an individual EFI variable associated with the attributes spec-
iﬁed.
The QueryVariableInfo() function allows a caller to obtain the information about the maximum size of the storage
space available for the EFI variables, the remaining size of the storage space available for the EFI variables and the
maximum size of each individual EFI variable, associated with the attributes speciﬁed.
TheMaximumVariableSize value will reﬂect the overhead associated with the saving of a single EFI variable with the
exception of the overhead associated with the length of the string name of the EFI variable.
The returned MaximumVariableStorageSize ,RemainingVariableStorageSize ,MaximumVariableSize information may
change immediately after the call based on other runtime activities including asynchronous error events. Also, these
values associated with different attributes are not additive in nature.
After the system has transitioned into runtime (after ExitBootServices() is called), an implementation may not be able
to accurately return information about the Boot Services variable store. In such cases, EFI_INV ALID_PARAMETER
should be returned.
EFI_SUCCESS Valid answer returned.
EFI_INV ALID_PARAMETER An invalid combination of attribute bits was supplied
EFI_UNSUPPORTED
The attribute is not supported on this platform, and the
MaximumVariableStorageSize ,
RemainingVariableStorageSize ,
MaximumVariableSize are undeﬁned.
8.2. Variable Services 217Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
8.2.5 Using the EFI_VARIABLE_AUTHENTICATION_3 descriptor
When the attribute EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS is set, the payload buffer (passed
into SetVariable() as “Data”) shall be constructed as follows:
// NOTE: “[ ]” indicates an optional element.
EFI_V ARIABLE_AUTHENTICATION_3 || EFI_TIME || [ NewCert ] || SigningCert || Data
// Example: EFI_V ARIABLE_AUTHENTICATION_3_NONCE_TYPE FI_V ARIABLE_AUTHENTICATION_3 ||
EFI_V ARIABLE_AUTHENTICATION_3_NONCE || [ NewCert ] || SigningCert || Data
In this example, NewCert and SigningCert are both instances of WIN_CERTIFICATE_UEFI_GUID. The presence of
NewCert is indicated by the EFI_V ARIABLE_AUTHENTICATION_3.Flags ﬁeld (see Deﬁnition in SetVariable()). If
provided – and assuming the payload passes all integrity and security veriﬁcations — this cert will be set as the new
authority for the underlying variable, even if the variable is being newly created.
The NewCert element must have a CertType of EFI_CERT_TYPE_PKCS7_GUID, and the CertData must be a DER-
encoded SignedData structure per PKCS#7 version 1.5 (RFC 2315), which shall be supported both with and without a
DER-encoded ContentInfo structure per PKCS#7 version 1.5. When creating the SignedData structure, the following
steps shall be followed:
1. Create a WIN_CERTIFICATE_UEFI_GUID structure where CertType is set to
EFI_CERT_TYPE_PKCS7_GUID.
2. Use the x509 cert being added as the new authority to sign its own tbsCertiﬁcate data.
3. Construct a DER-encoded PKCS #7 version 1.5 SignedData (see [RFC2315]) with the signed content as follows:
a - SignedData.version shall be set to 1.
b - SignedData.digestAlgorithms shall contain the digest algorithm used when preparing the signature.
c - SignedData.contentInfo.contentType shall be set to id-data.
d - SignedData.contentInfo.content shall be the tbsCertiﬁcate data that was signed for the new x509 cert.
e - SignedData.certiﬁcates shall contain, at a minimum, the signer’s DER-encoded X.509 certiﬁcate.
f - SignedData.crls is optional.
g - SignedData.signerInfos shall be constructed as:
• SignerInfo.version shall be set to 1.
• SignerInfo.issuerAndSerial shall be present and as in the signer’s certiﬁcate.
• SignerInfo.authenticatedAttributes shall not be present.
• SignerInfo.digestEncryptionAlgorithm shall be set to the algorithm used to sign the data.
• SignerInfo.encryptedDigest shall be present.
• SignerInfo.unauthenticatedAttributes shall not be present.
4. Set the CertData ﬁeld to the DER-encoded PKCS#7 SignedData value.
8.2. Variable Services 218Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
A caller to SetVariable() attempting to create, update, or delete a variable with the
EFI_V ARIABLE_ENHANCED_AUTHENTICATED_ACCESS set shall perform the following steps to create
the SignedData structure for SigningCert:
1. Create an EFI_V ARIABLE_AUTHENTICATION_3 Primary Descriptor with the following values:
a - Version shall be set appropriate to theversion of metadata headers being used (currently 1).
b - Type should be set based on caller speciﬁcations (see EFI_V ARIABLE_AUTHENTICATION_3 descriptor
under SetVariable()).
c - MetadataSize can be ignored for now, and will be updated when constructing the ﬁnal payload.
d - Flags shall be set based on caller speciﬁcations.
2. A Secondary Descriptor may need to be created based on the Type.
a - For EFI_V ARIABLE_AUTHENTICATION_3_TIMESTAMP_TYPE type,this will be an instance of
EFI_TIME set to thecurrent time.
b - For EFI_V ARIABLE_AUTHENTICATION_3_NONCE_TYPE type, this will be an instance of
EFI_V ARIABLE_AUTHENTICATION_3_NONCE updated with NonceSize set based on caller speciﬁcations
(must not be zero), and Nonce (informal structure member) set to:
• All zeros to request that the platform create a random nonce.
• Caller speciﬁed value for a pre-generated nonce.
3. Hash a serialization of the payload. Serialization shall contain the following elements in this order:
a - VariableName, VendorGuid, Attributes, and theSecondary Descriptor if it exists for this Type.
b - Variable’s new value (ie. the Data parameter’s new variable content).
c - If this is an update to or deletion of a variable with type EFI_V ARIABLE_AUTHENTICATION_3_NONCE,
serialize the current nonce. The current nonce is the one currently associated with this variable, not the one in
the Secondary Descriptor. Serialize only the nonce buffer contents, not the size or any additional data. If this is
an attempt to create a new variable (ie. there is no current nonce), skip this step.

d - If the authority cert for this variable is being updated and the
EFI_V ARIABLE_AUTHENTICATION_3.Flags ﬁeld indicates the presence of a NewCert structure, seri-
alize the entire NewCert structure (described at the beginning of this section).
4. Sign the resulting digest.
5. Create a WIN_CERTIFICATE_UEFI_GUID structure where CertType is set to
6. Construct a DER-encoded PKCS #7 version 1.5 SignedData (see [RFC2315]) following the steps described for
NewCert (step 3), above, with the following exception:
a - SignedData.contentInfo.content shall beabsent (the content is provided in the Data parameterto the SetVari-
able() call)
7. Construct the ﬁnal payload for SetVariable() according to the descriptions for “payload buffer” at the beginning
of this section.
8. Update the EFI_V ARIABLE_AUTHENTICATION_3.MetadataSize ﬁeld to include all parts of the ﬁnal payload
except “Data”.
Firmware that implements the SetVariable() services and supports the EFI_V ARIABLE_ENHANCED _AUTHENTI-
CATED_ACCESS attribute shall do the following in response to being called:
1. Read the EFI_V ARIABLE_AUTHENTICATION_3 descriptor to determine what type of authentication isbeing
performed and how to parse the rest of the payload.
8.2. Variable Services 219Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2. Verify that SigningCert.CertType EFI_CERT_TYPE_PKCS7_GUID.
a - If EFI_V ARIABLE_AUTHENTICATION_3.Flags ﬁeld indicates presence of a NewCert, verify that-
NewCert.CertType is EFI_CERT_TYPE_PKCS7_GUID.
b - If either fails, return EFI_INV ALID_PARAMETER.
3. If the variable already exists, verify that the incoming type matches the existing type.
4. Verify that any EFI_TIME structures have Pad1, Nanosecond, TimeZone, Daylight, and Pad2 ﬁelds set to zero.
5. If EFI_V ARIABLE_AUTHENTICATION_3_NONCE_TYPE:
a - Verify that NonceSize is greater than zero.If zero, return EFI_INV ALID_PARAMETER.
b - If incoming nonce is all zeros, conﬁrm that platform supports generating random nonce. If unsupported,
return EFI_UNSUPPORTED.
c - If nonce is speciﬁed and variable already exists, verify that incoming nonce does not match existing nonce.
If identical, return EFI_INV ALID_PARAMETER.
6. If EFI_V ARIABLE_AUTHENTICATION_3_TIMESTAMP_TYPE and variable already exists, verify that new
timestamp is chronologically greater than current timestamp.
7. Verify the payload signature by:
a - Parsing entire payload according to descriptors.
b - Using descriptor contents (and, if necessary, metadata from existing variable) to construct the serialization
described previously in this section (step 3 of the SetVariable() instructions).
c - Compute the digest and compare with the result of applying the SigningCert’s public key to the signature.
8. If the variable already exists, verify that the SigningCert authority is the same as the authority already associated
with the variable.
9. If NewCert is provided, verify the NewCert signature by:
a - Parsing entire payload according todescriptors.
b - Compute a digest of the tbsCertiﬁcate of x509 certiﬁcate in NewCert and compare with the result of applying
NewCert’s public key to the signature.
c - If this fails, return EFI_SECURITY_VIOLATION.
8.2.6 Using the EFI_VARIABLE_AUTHENTICATION_2 descriptor
When the attribute EFI_V ARIABLE_TIME_BASED_AUTHENTICATED _WRITE_ACCESS is set, then the Data
buffer shall begin with an instance of a complete (and serialized).
EFI_V ARIABLE_AUTHENTICATION_2 descriptor. The descriptor shall be followed by the new variable value and
DataSize shall reﬂect the combined size of the descriptor and the new variable value. The authentication descriptor is
not part of the variable data and is not returned by subsequent calls to GetVariable().
A caller that invokes the SetVariable() service with the EFI_V ARIABLE_TIME_BASED_AUTHENTICATED
_WRITE_ACCESS attribute set shall do the following prior to invoking the service:
1. Create a descriptor
Create an EFI_V ARIABLE_AUTHENTICATION_2 descriptor where:
• TimeStamp is set to the current time.
8.2. Variable Services 220Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NOTE :In certain environments a reliable time source may not be available. In this case, an implementation
may still add values to an authenticated variable since the EFI_VARIABLE_APPEND_WRITE attribute, when
set, disables timestamp veriﬁcation (see below). In these instances, the special time value where every
component of the EFI_TIME struct including the Day and Month is set to 0 shall be used .
• AuthInfo.CertType is set to EFI_CERT_TYPE_PKCS7_GUID.
2. Hash the serialization of the values of the VariableName, VendorGuid and Attributes parameters of the SetVari-
able() call and the TimeStamp component of the EFI_V ARIABLE_AUTHENTICATION_2 descriptor followed
by the variable’s new value (i.e. the Data parameter’s new variable content). That is, digest = hash (Variable-
Name, VendorGuid, Attributes, TimeStamp, DataNew_variable_content). The NULL character terminating the
VariableName value shall not be included in the hash computation.
3. Sign the resulting digest using a selected signature scheme (e.g. PKCS #1 v1.5)
4. Construct a DER-encoded SignedData structure per PKCS#7 version 1.5 (RFC 2315), which shall be supported
both with and without a DER-encoded ContentInfo structure per PKCS#7 version 1.5, with the signed content
as follows:
a - SignedData.version shall be set to 1
b - SignedData.digestAlgorithms shall contain the digest algorithm used when preparing the signature. Digest
algorithms of SHA-256, SHA-384, SHA-512 are accepted.
c - SignedData.contentInfo.contentType shall be set to id-data
d - SignedData.contentInfo.content shall be absent (the content is provided in the Data parameter to the SetVari-
— SignerInfo.version shall be set to 1
— SignerInfo.issuerAndSerial shall be present and as in the signer’s certiﬁcate — Signer-
Info.authenticatedAttributes shall not be present.
— SignerInfo.digestEncryptionAlgorithm shall be set to the algorithm used to sign the data.
— SiginerInfo.encryptedDigest shall be present
— SignerInfo.unauthenticatedAttributes shall not be present.
5. Set AuthInfo.CertData to the DER-encoded PKCS #7 SignedData value.
6. Construct Data parameter: Construct the SetVariable()’s Data parameter by concatenating the com-
plete, serialized EFI_V ARIABLE_AUTHENTICATION_2 descriptor with the new value of the variable
(DataNew_variable_content).
Firmware that implements the SetVariable() service and supports the EFI_V ARIABLE_TIME_BASED _AUTHEN-
TICATED_WRITE_ACCESS attribute shall do the following in response to being called:
1. Verify that the correct AuthInfo.CertType (EFI_CERT_TYPE_PKCS7_GUID) has been used and that theAu-
thInfo.CertData value parses correctly as a PKCS #7SignedData value
2. Verify that Pad1, Nanosecond, TimeZone, Daylight and Pad2 components of the TimeStamp value are set to
zero. Unless the EFI_V ARIABLE_APPEND_WRITE attribute is set, verify that the TimeStamp value is later
than the current timestamp value associated with the variable.
8.2. Variable Services 221Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3. If the variable SetupMode==1, and the variable is a secure boot policy variable, then the ﬁrmware implemen-
tation shall consider the checks in the following steps 4 and 5 to have passed, and proceed with updating the
variable value as outlined below.
4. Verify the signature by:
— extracting the EFI_V ARIABLE_AUTHENTICATION_2 descriptor from the Data buffer;
— using the descriptor contents and other parameters to (a) construct the input to the digest algorithm; (b)
computing the digest; and (c) comparing the digest with the result of applying the signer’s public key to the
signature.
5. If the variable is the global PK variable or the global KEK variable, verify that the signature has been made with
the current Platform Key.
• If the variable is the “db”, “dbt”, “dbr”, or “dbx” variable mentioned in step 3, verify that the signer’s
certiﬁcate chains to a certiﬁcate in the Key Exchange Key database (or that the signature was made with
the current Platform Key).
• If the variable is the “OsRecoveryOrder” or “OsRecovery####” variable mentioned in step 3, verify that
the signer’s certiﬁcate chains to a certiﬁcate in the “dbr” database or the Key Exchange Key database, or
that the signature was made with the current Platform Key.
• Otherwise, if the variable is none of the above, it shall be designated a Private Authenticated Variable.
If the Private Authenticated Variable does not exist, then the CN of the signing certiﬁcate’s Subject and
the hash of the tbsCertiﬁcate of the top-level issuer certiﬁcate (or the signing certiﬁcate itself if no other

certiﬁcates are present or the certiﬁcate chain is of length 1) in SignedData.certiﬁcates is registered for
use in subsequent veriﬁcations of this variable. Implementations may store just a single hash of these two
elements to reduce storage requirements. If the Private Authenticated variable previously existed, that the
signer’s certiﬁcate chains to the information previously associated with the variable. Observe that because
no revocation list exists for them, if any member of the certiﬁcate chain is compromised, the only method
to revoke trust in a certiﬁcate for a Private Authenticated Variable is to delete the variable, re-issue all
certiﬁcate authorities in the chain, and re-create the variable using the new certiﬁcate chain. As such,
the remaining beneﬁts may be strong identiﬁcation of the originator, or compliance with some certiﬁcate
authority policy. Further note that the PKCS7 bundle for the authenticated variable update must contain
the signing certiﬁcate chain, through and including the full certiﬁcate of the desired trust anchor. The trust
anchor might be a mid-level certiﬁcate or root, though many roots may be unsuitable trust anchors due to
the number of CAs they issue for different purposes. Some tools require non-default parameters to include
the trust anchor certiﬁcate.
The driver shall update the value of the variable only if all of these checks pass. If any of the checks fails, ﬁrmware
must return EFI_SECURITY_VIOLATION.
The ﬁrmware shall perform an append to an existing variable value only if the EFI_V ARIABLE_APPEND_WRITE
attribute is set.
For variables with the GUID EFI_IMAGE_SECURITY_DATABASE_GUID (i.e. where the data buffer is formatted as
EFI_SIGNATURE_LIST), the driver shall not perform an append of EFI_SIGNATURE_DATA values that are already
part of the existing variable value.
NOTE: This situation is not considered an error, and shall in itself not cause a status code other than EFI_SUCCESS
to be returned or the timestamp associated with the variable not to be updated .
The ﬁrmware shall associate the new timestamp with the updated value (in the case when the
EFI_V ARIABLE_APPEND_WRITE attribute is set, this only applies if the new TimeStamp value is later than
the current timestamp associated with the variable).
If the variable did not previously exist, and is not one of the variables listed in step 3 above, then ﬁrmware shall
associate the signer’s public key with the variable for future veriﬁcation purposes.
8.2. Variable Services 222Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
8.2.7 Using the EFI_VARIABLE_AUTHENTICATION descriptor
NOTE :This interface is deprecated and should no longer be used! It will be removed from future versions of the spec .
When the attribute EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS is set, but the
EFI_V ARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS is not set (i.e. when the
EFI_V ARIABLE_AUTHENTICATION descriptor s used), then the* Data buffer shall begin with an instance
of the authentication descriptor AuthInfo prior to the data payload and DataSize should reﬂect the data and descriptor
size. The authentication descriptor is not part of the variable data and is not returned by the subsequent calls to
GetVariable . The caller shall digest the Monotonic Count value and the associated data for the variable update using
the SHA-256 1-way hash algorithm. The ensuing the 32-byte digest will be signed using the private key associated w/
the public 2048-bit RSA key PublicKey described in the EFI_CERT_BLOCK_RSA_2048_SHA256 structure.
The WIN_CERTIFICATE shall be used to describe the signature of the variable *Data. In addition, the signature will
also include the MonotonicCount value to guard against replay attacks. The MonotonicCount value must be increased
by the caller prior to an update of the *Data* when the EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS is
set.
From the EFI_CERT_BLOCK_RSA_2048_SHA256, the HashType will be EFI_SHA256_HASH* and the ANY-
SIZE_ARRAY of Signature will be 256.The WIN_CERTIFICATE_PKCS1_15 could have been used but was not
for the following reason: There are possibly various different principals to create authenticated variables, so the
public key corresponding to a given principal is added to the EFI_CERT_BLOCK_RSA_2048_SHA256 within the
WIN_CERTIFICATE. This does not lend cryptographic value so much as it provides something akin to a handle for
the platform ﬁrmware to use during its veriﬁcation operation.
The MonotonicCount value must be strictly greater for each successive variable update operation. This allows for
ensuring freshness of the update operation and defense against replay attacks (i.e., if someone had the value of a
former AuthInfo , such as a Man-in-the-Middle they could not re-invoke that same update session). For maintenance,
the party who initially provisioned the variable (i.e., caller of SetVariable) and set the monotonic count will have to
pass the credential (key-pair and monotonic count) to any party who is delegated to make successive updates to the
variable with the EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS set. This 3-tuple of {public key, private
key, monotonic count} becomes part of the management metadata for these access-controlled items.
The responsibility of the caller that invokes the SetVariable() service with the
EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS attribute will do the following prior to invoking the
service:
• Update the Monotonic Count value.
• Hash the variable contents (Data, Size, Monotonic count) using the HashType in the AuthInfo structure.
• Sign the resultant hash of above step using a caller private key and create the digital signature Signature . Ensure
that the public key associated with signing private key is in the AuthInfo structure.
• Invoke SetVariables with EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS attribute set.
The responsibility of the ﬁrmware that implements the SetVariable() service and supports the
EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS attribute will do the following in response to being
called:
• The ﬁrst time it uses SetVariable with the EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS attribute
set. Use the public key in the AuthInfo structure for subsequent veriﬁcation.
• Compare the public key in the AuthInfo structure with the public key passed in on the ﬁrst invocation.
• Verify the digital signature Signature of the signed hash using the stored public key associated with the variable.
• Compare the veriﬁcation of the signature with the instance generated by the caller
• If comparison fails, return EFI_SECURITY_VIOLATION.
8.2. Variable Services 223Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Compare the new monotonic count and ensure that it is greater than the last SetVariable operation with the
EFI_V ARIABLE_AUTHENTICATED_WRITE_ACCESS attribute set.
• If new monotonic count is not strictly greater, then return EFI_SECURITY_VIOLATION.
NOTE :Special processing by SetVariable() for Secure Boot variables and the Platform Key is deﬁned in Firmware/OS
Key Exchange: Creating Trust Relationships .
8.2.8 Hardware Error Record Persistence
This section deﬁnes how Hardware Error Record Persistence is to be implemented. By implementing support for
Hardware Error Record Persistence, the platform enables the OS to utilize the EFI Variable Services to save hard-
ware error records so they are persistent and remain available across OS sessions until they are explicitly cleared or
overwritten by their creator.
8.2.8.1 Hardware Error Record Non-Volatile Store
A platform which implements support hardware error record persistence is required to guarantee some amount of NVR
is available to the OS for saving hardware error records. The platform communicates the amount of space allocated
for error records via the QueryVariableInfo routine as described in Appendix P.
8.2.8.2 Hardware Error Record Variables
This section deﬁnes a set of Hardware Error Record variables that have architecturally deﬁned meanings. In addition
to the deﬁned data content, each such variable has an architecturally deﬁned attribute that indicates when the data
variable may be accessed. The variables with an attribute of HR are stored in the portion of NVR allocated for
error records. NV , BS and RT have the meanings deﬁned in section 3.2. All hardware error record variables use the
EFI_HARDWARE_ERROR_V ARIABLE VendorGuid:
#define EFI_HARDWARE_ERROR_VARIABLE\
{0x414E6BDD,0xE47B,0x47cc,{0xB2,0x44,0xBB,0x61,0x02,0x0C,0xF5,0x16}}
Table 8.8: Hardware Error Record Persistence Variables
HwErrRec#### NV , BS, RT, HR A hardware error record. #### is a printed hex value. No 0x or h is
included in the hex value
The HwErrRec#### variable contains a hardware error record. Each HwErrRec#### variable is the name “HwErrRec”

appended with a unique 4-digit hexadecimal number. For example, HwErrRec0001, HwErrRec0002, HwErrRecF31A,
etc. The HR attribute indicates that this variable is to be stored in the portion of NVR allocated for error records.
8.2.8.3 Common Platform Error Record Format
Error record variables persisted using this interface are encoded in the Common Platform Error Record format, which
is described in appendix N of the UEFI Speciﬁcation . Because error records persisted using this interface conform to
this standardized format, the error information may be used by entities other than the OS.
8.2. Variable Services 224Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
8.3 Time Services
This section contains function deﬁnitions for time-related functions that are typically needed by operating systems at
runtime to access underlying hardware that manages time information and services. The purpose of these interfaces is
to provide operating system writers with an abstraction for hardware time devices, thereby relieving the need to access
legacy hardware devices directly. There is also a stalling function for use in the preboot environment. Time Services
Functions lists the time services functions described in this section:
Table 8.9: Time Services Functions
GetTime Runtime Returns the current time and date, and the time-keeping capabilities
of the platform.
SetTime Runtime Sets the current local time and date information.
GetWakeupTime Runtime Returns the current wakeup alarm clock setting.
SetWakeupTime Runtime Sets the system wakeup alarm clock time
8.3.1 GetTime()
Summary
Returns the current time and date information, and the time-keeping capabilities of the hardware platform.
Prototype
typedef
GetTime (
OUT EFI_TIME *Time,
OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL
);
Time A pointer to storage to receive a snapshot of the current time. Type EFI_TIME is deﬁned in “Related Deﬁni-
tions.”
Capabilities An optional pointer to a buffer to receive the real time clock device’s capabilities. Type
EFI_TIME_CAPABILITIES is deﬁned in “Related Deﬁnitions.”
//************************************************
//EFI_TIME
// This represents the current time information
UINT16 Year; // 1900 - 9999
UINT8 Month; // 1 - 12
UINT8 Day; // 1 - 31
UINT8 Hour; // 0 - 23
UINT8 Minute; // 0 - 59
UINT8 Second; // 0 - 59
UINT8 Pad1;
UINT32 Nanosecond; // 0 - 999,999,999
INT16 TimeZone; // --1440 to 1440 or 2047
8.3. Time Services 225Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT8 Daylight;
UINT8 Pad2;
} EFI_TIME;
// Bit Definitions for EFI_TIME.Daylight. See below.
#define EFI_TIME_ADJUST_DAYLIGHT 0x01
#define EFI_TIME_IN_DAYLIGHT 0x02
// Value Definition for EFI_TIME.TimeZone. See below.
#define EFI_UNSPECIFIED_TIMEZONE 0x07FF
Year, Month, Day The current local date.
Hour, Minute, Second, Nanosecond The current local time. Nanoseconds report the current fraction of a second in
the device. The format of the time is hh:mm:ss.nnnnnnnnn . A battery backed real time clock device maintains
the date and time.
TimeZone The time’s offset in minutes from UTC. If the value is EFI_UNSPECIFIED_TIMEZONE, then the time
is interpreted as a local time. The TimeZone is the number of minutes that the local time is relative to UTC. To
calculate the TimeZone value, follow this equation: Localtime = UTC - TimeZone.
To further illustrate this, an example is given below:
PST (Paciﬁc Standard Time is 12PM) = UTC (8PM) - 8 hours (480 minutes)
In this case, the value for Timezone would be 480 if referencing PST.
Daylight A bitmask containing the daylight savings time information for the time.
The EFI_TIME_ADJUST_DAYLIGHT bit indicates if the time is affected by daylight savings time or not. This
value does not indicate that the time has been adjusted for daylight savings time. It indicates only that it should
be adjusted when the EFI_TIME enters daylight savings time.
If EFI_TIME_IN_DAYLIGHT is set, the time has been adjusted for daylight savings time.
All other bits must be zero.
When entering daylight saving time, if the time is affected, but hasn’t been adjusted (DST = 1), use the new
calculation:
1. The date/time should be increased by the appropriate amount.
2. The TimeZone should be decreased by the appropriate amount (EX: +480 changes to +420 when moving
from PST to PDT).
3. The Daylight value changes to 3.
When exiting daylight saving time, if the time is affected and has been adjusted (DST = 3), use the new calcu-
lation:
1. The date/time should be decreased by the appropriate amount.
2. The TimeZone should be increased by the appropriate amount.
3. The Daylight value changes to 1.
8.3. Time Services 226Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_TIME_CAPABILITIES
// This provides the capabilities of the
// real time clock device asexposed through the EFI
interfaces.
UINT32 Resolution;
UINT32 Accuracy;
BOOLEAN SetsToZero;
} EFI_TIME_CAPABILITIES;
Resolution Provides the reporting resolution of the real-time clock device in counts per second. For a normal PC-AT
CMOS RTC device, this value would be 1 Hz, or 1, to indicate that the device only reports the time to the
resolution of 1 second.
Accuracy Provides the timekeeping accuracy of the real-time clock in an error rate of 1E-6 parts per million. For a
clock with an accuracy of 50 parts per million, the value in this ﬁeld would be 50,000,000.
SetsToZero ATRUE indicates that a time set operation clears the device’s time below the Resolution reporting level.
AFALSE indicates that the state below the Resolution level of the device is not cleared when the time is set.
Normal PC-AT CMOS RTC devices set this value to FALSE .
The GetTime() function returns a time that was valid sometime during the call to the function. While the returned
EFI_TIME structure contains TimeZone and Daylight savings time information, the actual clock does not maintain
these values. The current time zone and daylight saving time information returned by GetTime() are the values that
were last set via SetTime() .
The GetTime() function should take approximately the same amount of time to read the time each time it is called. All
reported device capabilities are to be rounded up.
During runtime, if a PC-AT CMOS device is present in the platform the caller must synchronize access to the device
before calling GetTime().
EFI_SUCCESS The operation completed successfully.
EFI_INV ALID_PARAMETER Time is NULL.
EFI_DEVICE_ERROR The time could not be retrieved due to a hardware error.
anEFI_RT_PROPERTIES_TABLE conﬁguration table.
8.3.2 SetTime()
Summary
Sets the current local time and date information.
Prototype
typedef
SetTime (
8.3. Time Services 227Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_TIME *Time
);
Time A pointer to the current time. Type EFI_TIME is deﬁned in the GetTime() function description. Full error
checking is performed on the different ﬁelds of the EFI_TIME structure (refer to the EFI_TIME deﬁnition in
the GetTime() function description for full details), and EFI_INV ALID_PARAMETER is returned if any ﬁeld
is out of range.
The SetTime() function sets the real time clock device to the supplied time, and records the current time zone and
daylight savings time information. The SetTime() function is not allowed to loop based on the current time. For
example, if the device does not support a hardware reset for the sub-resolution time, the code is not to implement the
feature by waiting for the time to wrap.
before calling SetTime().
EFI_INV ALID_PARAMETER A time ﬁeld is out of range.
EFI_DEVICE_ERROR The time could not be set due to a hardware error.
8.3.3 GetWakeupTime()
Summary
Returns the current wakeup alarm clock setting.
Prototype
typedef

Summary
Prototype
typedef
GetWakeupTime (
OUT BOOLEAN *Enabled,
OUT BOOLEAN *Pending,
OUT EFI_TIME *Time
);
Enabled Indicates if the alarm is currently enabled or disabled.
Pending Indicates if the alarm signal is pending and requires acknowledgement.
Time The current alarm setting. Type EFI_TIME is deﬁned in the GetTime() function description.
The alarm clock time may be rounded from the set alarm clock time to be within the resolution of the alarm clock
device. The resolution of the alarm clock device is deﬁned to be one second.
8.3. Time Services 228Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
before calling GetWakeupTime().
EFI_SUCCESS The alarm settings were returned.
EFI_INV ALID_PARAMETER Enabled is NULL.
EFI_INV ALID_PARAMETER Pending is NULL.
EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
8.3.4 SetWakeupTime()
Summary
Sets the system wakeup alarm clock time.
Prototype
typedef
SetWakeupTime (
IN BOOLEAN Enable,
IN EFI_TIME *Time OPTIONAL
);
Enable Enable or disable the wakeup alarm.
Time If Enable is TRUE , the time to set the wakeup alarm for. Type EFI_TIME is deﬁned in the GetTime() function
description. If Enable is FALSE , then this parameter is optional, and may be NULL.
Setting a system wakeup alarm causes the system to wake up or power on at the set time. When the alarm ﬁres, the
alarm signal is latched until it is acknowledged by calling SetWakeupTime() to disable the alarm. If the alarm ﬁres
before the system is put into a sleeping or off state, since the alarm signal is latched the system will immediately wake
up. If the alarm ﬁres while the system is off and there is insufﬁcient power to power on the system, the system is
powered on when power is restored.
For an ACPI-aware operating system, this function only handles programming the wakeup alarm for the desired
wakeup time. The operating system still controls the wakeup event as it normally would through the ACPI Power
Management register set.
The resolution for the wakeup alarm is deﬁned to be 1 second.
before calling SetWakeupTime().
EFI_SUCCESS IfEnable isTRUE , then the wakeup alarm was enabled. If Enable is
FALSE , then the wakeup alarm was disabled.
8.3. Time Services 229Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 8.13 – continued from previous page
EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
8.4 Virtual Memory Services
This section contains function deﬁnitions for the virtual memory support that may be optionally used by an operating
system at runtime. If an operating system chooses to make EFI runtime service calls in a virtual addressing mode
instead of the ﬂat physical mode, then the operating system must use the services in this section to switch the EFI
runtime services from ﬂat physical addressing to virtual addressing. Virtual Memory Functions lists the virtual memory
service functions described in this section. The system ﬁrmware must follow the processor-speciﬁc rules outlined in
IA-32 Platforms through AArch64 Platforms in the layout of the EFI memory map to enable the OS to make the
Table 8.14: Virtual Memory Functions
SetVirtualAddressMap Runtime Used by an OS loader to convert from physical addressing to virtual addressing.
ConvertPointer Runtime Used by EFI components to convert internal pointers when switching to virtual addressing.
8.4.1 SetVirtualAddressMap()
Summary
Changes the runtime addressing mode of EFI ﬁrmware from physical to virtual.
Prototype
typedef
SetVirtualAddressMap (
IN UINTN MemoryMapSize,
IN UINTN DescriptorSize,
IN UINT32 DescriptorVersion,
IN EFI_MEMORY_DESCRIPTOR *VirtualMap
);
MemoryMapSize The size in bytes of VirtualMap .
DescriptorSize The size in bytes of an entry in the VirtualMap.
DescriptorVersion The version of the structure entries in VirtualMap.
VirtualMap An array of memory descriptors which contain new virtual address mapping information for all run-
time ranges. Type EFI_MEMORY_DESCRIPTOR is deﬁned in the EFI_BOOT_SERVICES.GetMemoryMap()
The SetVirtualAddressMap() function is used by the OS loader. The function can only be called at
runtime, and is called by the owner of the system’s memory map: i.e., the component which called
8.4. Virtual Memory Services 230Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_BOOT_SERVICES.ExitBootServices() . All events of type EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
must be signaled before SetVirtualAddressMap() returns.
This call changes the addresses of the runtime components of the EFI ﬁrmware to the new virtual addresses supplied
in the VirtualMap. The supplied VirtualMap must provide a new virtual address for every entry in the memory map at
ExitBootServices() that is marked as being needed for runtime usage. All of the virtual address ﬁelds in the VirtualMap
must be aligned on 4 KiB boundaries.
The call to SetVirtualAddressMap() must be done with the physical mappings. On successful return from this function,
the system must then make any future calls with the newly assigned virtual mappings. All address space mappings
must be done in accordance to the cacheability ﬂags as speciﬁed in the original address map.
When this function is called, all events that were registered to be signaled on an address map change are notiﬁed.
Each component that is notiﬁed must update any internal pointers for their new addresses. This can be done with the
ConvertPointer() function. Once all events have been notiﬁed, the EFI ﬁrmware reapplies image “ﬁx-up” information
to virtually relocate all runtime images to their new addresses. In addition, all of the ﬁelds of the EFI Runtime Services
Table except SetVirtualAddressMap and ConvertPointer must be converted from physical pointers to virtual pointers
using the ConvertPointer() service. The SetVirtualAddressMap() and ConvertPointer() services are only callable in
physical mode, so they do not need to be converted from physical pointers to virtual pointers. Several ﬁelds of the EFI
System Table must be converted from physical pointers to virtual pointers using the ConvertPointer() service. These
ﬁelds include FirmwareVendor, RuntimeServices, and ConﬁgurationTable. Because contents of both the EFI Runtime
Services Table and the EFI System Table are modiﬁed by this service, the 32-bit CRC for the EFI Runtime Services
Table and the EFI System Table must be recomputed.
A virtual address map may only be applied one time. Once the runtime system is in virtual mode, calls to this function
EFI_SUCCESS The virtual address map has been applied.
EFI_UNSUPPORTED EFI ﬁrmware is not at runtime, or the EFI ﬁrmware is already in virtual
address mapped mode.
EFI_INV ALID_PARAMETER DescriptorSize orDescriptorVersion is invalid.
EFI_NO_MAPPING A virtual address was not supplied for a range in the memory map that
requires a mapping.
EFI_NOT_FOUND A virtual address was supplied for an address that is not found in the mem-
ory map.
8.4.2 ConvertPointer()
Summary
Determines the new virtual address that is to be used on subsequent memory accesses.
Prototype
typedef
ConvertPointer (
IN UINTN DebugDisposition,
IN VOID **Address
);
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DebugDisposition Supplies type information for the pointer being converted. See “Related Deﬁnitions.”
Address A pointer to a pointer that is to be ﬁxed to be the value needed for the new virtual address mappings being
applied.
// EFI_OPTIONAL_PTR
#define EFI_OPTIONAL_PTR 0x00000001
The ConvertPointer() function is used by an EFI component during the SetVirtualAddressMap() operation. Convert-

Summary
Prototype
typedef
);
applied.
Pointer() must be called using physical address pointers during the execution of SetVirtualAddressMap().
The ConvertPointer() function updates the current pointer pointed to by Address to be the proper value for the new
address map. Only runtime components need to perform this operation. The EFI_BOOT_SERVICES.CreateEvent()
function is used to create an event that is to be notiﬁed when the address map is changing. All pointers the component
has allocated or assigned must be updated.
If the EFI_OPTIONAL_PTR ﬂag is speciﬁed, the pointer being converted is allowed to be NULL.
Once all components have been notiﬁed of the address map change, ﬁrmware ﬁxes any compiled in pointers that are
embedded in any runtime image.
EFI_SUCCESS The pointer pointed to by Address was modiﬁed.
EFI_NOT_FOUND The pointer pointed to by Address was not found to be part of the current
memory map. This is normally fatal.
EFI_INV ALID_PARAMETER Address is NULL.
EFI_INV ALID_PARAMETER *Address is NULL and DebugDisposition does not have the
EFI_OPTIONAL_PTR bit set.
8.5 Miscellaneous Runtime Services
This section contains the remaining function deﬁnitions for runtime services not deﬁned elsewhere but which are
required to complete the deﬁnition of the EFI environment. The Table, below, lists the Miscellaneous Runtime Services
.
Miscellaneous Runtime Services
Table 8.17: Miscellaneous Runtime Services
GetNextHighMonotonicCount Runtime Returns the next high 32 bits of the platform’s monotonic counter.
ResetSystem Runtime Resets the entire platform.
UpdateCapsule Runtime Pass capsules to the ﬁrmware. The ﬁrmware may process the capsules im-
mediately or return a value to be passed into Reset System that will cause
the capsule to be processed by the ﬁrmware as part of the reset process.
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Table 8.17 – continued from previous page
QueryCapsuleCapabilities Runtime Returns if the capsule can be supported via UpdateCapsule()
8.5.1 Reset System
This section describes the reset system runtime service and its associated data structures.
8.5.1.1 ResetSystem()
Summary
Resets the entire platform. If the platform supports See ref:EFI_RESET_NOTIFICATION_PROTOCOL , then prior to
completing the reset of the platform, all of the pending notiﬁcations must be called.
Prototype
typedef
VOID
(EFIAPI \ *EFI_RESET_SYSTEM) (
IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus,
IN VOID *ResetData OPTIONAL
);
ResetType The type of reset to perform. Type EFI_RESET_TYPE is deﬁned in “Related Deﬁnitions” below.
ResetStatus The status code for the reset. If the system reset is part of a normal operation, the status code would be
EFI_SUCCESS. If the system reset is due to some type of failure the most appropriate EFI Status code would
be used.
DataSize The size, in bytes, of ResetData .
ResetData For a ResetType of EﬁResetCold, EﬁResetWarm, or EﬁResetShutdown the data buffer starts with a Null-
terminated string, optionally followed by additional binary data. The string is a description that the caller may
use to further indicate the reason for the system reset. For a ResetType of EﬁResetPlatformSpeciﬁc the data
buffer also starts with a Null-terminated string that is followed by an EFI_GUID that describes the speciﬁc type
of reset to perform.
// EFI_RESET_TYPE
EfiResetCold,
EfiResetWarm,
EfiResetShutdown
EfiResetPlatformSpecific
} EFI_RESET_TYPE;
The ResetSystem() function resets the entire platform, including all processors and devices, and reboots the system.
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Calling this interface with ResetType of EﬁResetCold causes a system-wide reset. This sets all circuitry within the
system to its initial state. This type of reset is asynchronous to system operation and operates without regard to cycle
boundaries. EﬁResetCold is tantamount to a system power cycle.
Calling this interface with ResetType of EﬁResetWarm causes a system-wide initialization. The processors are set
to their initial state, and pending cycles are not corrupted. If the system does not support this reset type, then an
EﬁResetCold must be performed.
Calling this interface with ResetType of EﬁResetShutdown causes the system to enter a power state equivalent to the
ACPI G2/S5 or G3 states. If the system does not support this reset type, then when the system is rebooted, it should
exhibit the EﬁResetCold attributes.
Calling this interface with ResetType of EﬁResetPlatformSpeciﬁc causes a system-wide reset. The exact type of
the reset is deﬁned by the EFI_GUID that follows the Null-terminated Unicode string passed into ResetData . If the
platform does not recognize the EFI_GUID in ResetData the platform must pick a supported reset type to perform.The
platform may optionally log the parameters from any non-normal reset that occurs.
The ResetSystem() function does not return.
8.5.2 Get Next High Monotonic Count
This section describes the GetNextHighMonotonicCount runtime service and its associated data structures.
8.5.2.1 GetNextHighMonotonicCount()
Summary
Returns the next high 32 bits of the platform’s monotonic counter.
Prototype
typedef
GetNextHighMonotonicCount (
OUT UINT32 *HighCount
);
HighCount Pointer to returned value.
The GetNextHighMonotonicCount() function returns the next high 32 bits of the platform’s monotonic counter.
The platform’s monotonic counter is comprised of two 32-bit quantities: the high 32 bits and the low 32 bits. During
boot service time the low 32-bit value is volatile: it is reset to zero on every system reset and is increased by 1 on
every call to GetNextMonotonicCount(). The high 32-bit value is nonvolatile and is increased by 1 whenever the
system resets, whenever GetNextHighMonotonicCount() is called, or whenever the low 32-bit count (returned by
GetNextMonoticCount()) overﬂows.
TheEFI_BOOT_SERVICES.GetNextMonotonicCount() function is only available at boot services time. If the operat-
ing system wishes to extend the platform monotonic counter to runtime, it may do so by utilizing GetNextHighMono-
tonicCount(). To do this, before calling EFI_BOOT_SERVICES.ExitBootServices() the operating system would call
GetNextMonotonicCount() to obtain the current platform monotonic count. The operating system would then provide
an interface that returns the next count by:
• Adding 1 to the last count.
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• Before the lower 32 bits of the count overﬂows, call GetNextHighMonotonicCount(). This will increase the
high 32 bits of the platform’s nonvolatile portion of the monotonic count by 1.
This function may only be called at Runtime.
EFI_SUCCESS The next high monotonic count was returned.
EFI_INV ALID_PARAMETER HighCount is NULL.
8.5.3 Update Capsule
This runtime function allows a caller to pass information to the ﬁrmware. Update Capsule is commonly used to update
the ﬁrmware FLASH or for an operating system to have information persist across a system reset.
8.5.3.1 UpdateCapsule()
Summary
Passes capsules to the ﬁrmware with both virtual and physical mapping. Depending on the intended consumption,
the ﬁrmware may process the capsule immediately. If the payload should persist across a system reset, the reset
value returned from EFI_QueryCapsuleCapabilities must be passed into Reset System and will cause the capsule to
be processed by the ﬁrmware as part of the reset process.
Prototype
typedef
UpdateCapsule (
IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
IN UINTN CapsuleCount,
IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL
);
CapsuleHeaderArray Virtual pointer to an array of virtual pointers to the capsules being passed into update capsule.
Each capsules is assumed to stored in contiguous virtual memory. The capsules in the CapsuleHeaderArray
must be the same capsules as the ScatterGatherList . The CapsuleHeaderArray must have the capsules in the
same order as the ScatterGatherList .
CapsuleCount Number of pointers to EFI_CAPSULE_HEADER in CapsuleHeaderArray .

Prototype
typedef
);
ScatterGatherList Physical pointer to a set of EFI_CAPSULE_BLOCK_DESCRIPTOR that describes the location
in physical memory of a set of capsules. See “Related Deﬁnitions” for an explanation of how more than one
capsule is passed via this interface. The capsules in the ScatterGatherList must be in the same order as the
CapsuleHeaderArray . This parameter is only referenced if the capsules are deﬁned to persist across system
reset.
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UINT64 Length;
union {
EFI_PHYSICAL_ADDRESS DataBlock;
EFI_PHYSICAL_ADDRESS ContinuationPointer;
}Union;
} EFI_CAPSULE_BLOCK_DESCRIPTOR;
Length Length in bytes of the data pointed to by DataBlock/ContinuationPointer.
DataBlock Physical address of the data block. This member of the union is used if Length is not equal to zero.
ContinuationPointer Physical address of another block of EFI_CAPSULE_BLOCK_DESCRIPTOR structures.
This member of the union is used if Length is equal to zero. If ContinuationPointer is zero this entry repre-
sents the end of the list.
This data structure deﬁnes the ScatterGatherList list the OS passes to the ﬁrmware. ScatterGatherList represents an
array of structures and is terminated with a structure member whose Length is 0 and DataBlock physical address is
0. If Length is 0 and DataBlock physical address is not 0, the speciﬁed physical address is known as a “continuation
pointer” and it points to a further list of EFI_CAPSULE_BLOCK_DESCRIPTOR structures. A continuation pointer
is used to allow the scatter gather list to be contained in physical memory that is not contiguous. It also is used to
allow more than a single capsule to be passed at one time.
EFI_GUID CapsuleGuid;
UINT32 CapsuleImageSize;
} EFI_CAPSULE_HEADER;
CapsuleGuid A GUID that deﬁnes the contents of a capsule.
HeaderSize The size of the capsule header. This may be larger than the size of the EFI_CAPSULE_HEADER since
CapsuleGuid may imply extended header entries.
Flags The Flags[15:0] bits are deﬁned by CapsuleGuid. Flags[31:16] are deﬁned by this speciﬁcation.
CapsuleImageSize Size in bytes of the capsule (including capsule header).
#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000
#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE 0x00020000
#define CAPSULE_FLAGS_INITIATE_RESET 0x00040000
NOTE :A capsule which has the CAPSULE_FLAGS_INITIATE_RESET Flag must have CAP-
SULE_FLAGS_PERSIST_ACROSS_RESET set in its header as well. Firmware that encounters a capsule
which has the CAPSULE_FLAGS_INITIATE_RESET Flag set in its header will initiate a reset of the platform which
is compatible with the passed-in capsule request and will not return back to the caller .
UINT32 CapsuleArrayNumber;
VOID* CapsulePtr[1];
} EFI_CAPSULE_TABLE;
CapsuleArrayNumber The number of entries in the array of capsules.
CapsulePtr A pointer to an array of capsules that contain the same CapsuleGuid value. Each CapsulePtr points to an
instance of an EFI_CAPSULE_HEADER, with the capsule data concatenated on its end.
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The UpdateCapsule() function allows the operating system to pass information to ﬁrmware. The UpdateCapsule()
function supports passing capsules in operating system virtual memory back to ﬁrmware. Each capsule is contained in
a contiguous virtual memory range in the operating system, but both a virtual and physical mapping for the capsules
are passed to the ﬁrmware.
If a capsule has the CAPSULE_FLAGS_PERSIST_ACROSS_RESET Flag set in its header, the ﬁrmware will process
the capsules after system reset. The caller must ensure to reset the system using the required reset value obtained from
QueryCapsuleCapabilities. If this ﬂag is not set, the ﬁrmware will process the capsules immediately.
A capsule which has the CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE Flag must have CAP-
SULE_FLAGS_PERSIST_ACROSS_RESET set in its header as well. Firmware that processes a capsule that
has the CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE Flag set in its header will coalesce the contents of
the capsule from the ScatterGatherList into a contiguous buffer and must then place a pointer to this coalesced
capsule in the EFI System Table after the system has been reset. Agents searching for this capsule will look in the
EFI_CONFIGURATION_TABLE and search for the capsule’s GUID and associated pointer to retrieve the data after
the reset.
Flag Firmware Behavior
Table 8.19: Flag Firmware Behavior
Flags Firmware Behavior
No Speciﬁcation deﬁned ﬂags Firmware attempts to immediately processes or launch the
capsule. If capsule is not recognized, can expect an error.
CAPSULE_FLAGS_PERSIST_ACROSS_RESET Firmware will attempt to process or launch the capsule
across a reset. If capsule is not recognized, can expect an er-
ror. If the processing requires a reset which is unsupported
by the platform, expect an error.
CAPSULE_FLAGS_PERSIST_ACROSS_RESET
+ CAP-
SULE_FLAGS_POPULATE_SYSTEM_TABLEFirmware will coalesce the capsule from the ScatterGath-
erList into a contiguous buffer and place a pointer to the
coalesced capsule in the EFI System Table. Platform recog-
nition of the capsule type is not required. If the action re-
quires a reset which is unsupported by the platform, expect
an error.
+ CAPSULE_FLAGS_INITIATE_RESETFirmware will attempt to process or launch the capsule
across a reset. The ﬁrmware will initiate a reset which is
compatible with the passed-in capsule request and will not
return back to the caller. If the capsule is not recognized,
can expect an error. If the processing requires a reset which
is unsupported by the platform, expect an error.
+ CAPSULE_FLAGS_INITIATE_RESET
+ CAP-
SULE_FLAGS_POPULATE_SYSTEM_TABLEThe ﬁrmware will initiate a reset which is compatible with
the passed-in capsule request and not return back to the
caller. Upon resetting, the ﬁrmware will coalesce the cap-
sule from the ScatterGatherList into a contiguous buffer and
place a pointer to the coalesced capsule in the EFI System
Table. Platform recognition of the capsule type is not re-
quired. If the action requires a reset which is unsupported
The EFI System Table entry must use the GUID from the CapsuleGuid ﬁeld of the EFI_CAPSULE_HEADER. The
EFI System Table entry must point to an array of capsules that contain the same CapsuleGuid value. The array must
be preﬁxed by a UINT32 that represents the size of the array of capsules.
The set of capsules is pointed to by ScatterGatherList and CapsuleHeaderArray so the ﬁrmware will know both the
physical and virtual addresses of the operating system allocated buffers. The scatter-gather list supports the situation
where the virtual address range of a capsule is contiguous, but the physical addresses are not.
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On architectures where the processor’s view of main memory is incoherent with the caches when the memory man-
agement unit is disabled, callers to UpdateCapsule() must perform cache maintenance to main memory on each
ScatterGatherList element before calling UpdateCapsule() . This requirement only applies after the OS has called
ExitBootServices() .
If any of the capsules that are passed into this function encounter an error, the entire set of capsules will not be
processed and the error encountered will be returned to the caller.
EFI_SUCCESS Valid capsule was passed. If CAP-
SULE_FLAGS_PERSIST_ACROSS_RESET is not set, the capsule
has been successfully processed by the ﬁrmware.
EFI_INV ALID_PARAMETER CapsuleSize , or an incompatible set of ﬂags were set in the capsule header.
EFI_INV ALID_PARAMETER CapsuleCount is 0
EFI_DEVICE_ERROR The capsule update was started, but failed due to a device error.
EFI_UNSUPPORTED The capsule type is not supported on this platform.
EFI_OUT_OF_RESOURCES When ExitBootServices() has been previously called this error indicates the
capsule is compatible with this platform but is not capable of being submit-
ted or processed in runtime. The caller may resubmit the capsule prior to
ExitBootServices().
EFI_OUT_OF_RESOURCES When ExitBootServices() has not been previously called then this error in-
dicates the capsule is compatible with this platform but there are insufﬁcient
resources to process.
8.5.3.2 Capsule Deﬁnition
A capsule is simply a contiguous set of data that starts with an EFI_CAPSULE_HEADER. The CapsuleGuid ﬁeld in
the header deﬁnes the format of the capsule.

The capsule contents are designed to be communicated from an OS-present environment to the system ﬁrmware. To
allow capsules to persist across system reset, a level of indirection is required for the description of a capsule, since the
OS primarily uses virtual memory and the ﬁrmware at boot time uses physical memory. This level of abstraction is ac-
complished via the EFI_CAPSULE_BLOCK_DESCRIPTOR. The EFI_CAPSULE_BLOCK_DESCRIPTOR allows
the OS to allocatecontiguous virtual address space and describe this address space to the ﬁrmware as a discontinuous
set of physical address ranges. The ﬁrmware is passed both physical and virtual addresses and pointers to describe the
capsule so the ﬁrmware can process the capsule immediately or defer processing of the capsule until after a system
reset.
In most instruction sets and OS architecture, allocation of physical memory is possible only on a “page” granularity
(which can range for 4 KiB to at least 1 MiB). The EFI_CAPSULE_BLOCK_DESCRIPTOR must have the following
properties to ensure the safe and well deﬁned transition of the data:
• Each new capsule must start on a new page of memory.
• All pages except for the last must be completely ﬁlled by the capsule.
– It is legal to pad the header to make it consume an entire page of data to enable the passing of page aligned
data structures via a capsule. The last page must have at least one byte of capsule in it.
• Pages must be naturally aligned
• Pages may not overlap on another
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• Firmware may never make an assumption about the page sizes the operating system is using.
Multiple capsules can be concatenated together and passed via a single call to UpdateCap-
sule().The physical address description of capsules are concatenated by converting the terminating
EFI_CAPSULE_BLOCK_DESCRIPTOR entry of the 1st capsule into a continuation pointer by making it
point to the EFI_CAPSULE_BLOCK_DESCRIPTOR that represents the start of the 2nd capsule. There is only a
single terminating EFI_CAPSULE_BLOCK_DESCRIPTOR entry and it is at the end of the last capsule in the chain.
The following algorithm must be used to ﬁnd multiple capsules in a single scatter gather list:
• Look at the capsule header to determine the size of the capsule
– The ﬁrst Capsule header is always pointed to by the ﬁrst EFI_CAPSULE_BLOCK_DESCRIPTOR entry
• Walk the EFI_CAPSULE_BLOCK_DESCRIPTOR list keeping a running count of the size each entry repre-
sents.
• If the EFI_CAPSULE_BLOCK_DESCRIPTOR entry is a continuation pointer and the running current capsule
size count is greater than or equal to the size of the current capsule this is the start of the next capsule.
• Make the new capsules the current capsule and repeat the algorithm.
Figure, below, shows a Scatter-Gather list of EFI_CAPSULE_BLOCK_DESCRIPTOR structures that de-
scribes two capsules. The left side of the ﬁgure shows OS view of the capsules as two separate contiguous
virtual memory buffers. The center of the ﬁgure shows the layout of the data in system memory. The
right hand side of the ﬁgure shows the ScatterGatherList list passed into the ﬁrmware. Since there are two
capsules two independent EFI_CAPSULE_BLOCK_DESCRIPTOR lists exist that were joined together
via a continuation pointer in the ﬁrst list.
Fig. 8.1: Scatter-Gather List of EFI_CAPSULE_BLOCK_DESCRIPTOR Structures
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8.5.3.3 EFI_MEMORY_RANGE_CAPSULE_GUID
This capsule structure deﬁnition provides a means by which a third-party component (e.g. OS) can describe to ﬁrmware
regions in memory should be left untouched across the next reset.
Support for this capsule is optional. For platforms that support this capsule, they must
advertise EFI_MEMORY_RANGE_CAPSULE in the EFI Conﬁguration table using the
EFI_MEMORY_RANGE_CAPSULE_GUID as the GUID in the GUID/pointer pair.
// {0DE9F0EC-88B6-428F-977A-258F1D0E5E72}
#define EFI_MEMORY_RANGE_CAPSULE_GUID \
{ 0xde9f0ec, 0x88b6, 0x428f, \
{ 0x97, 0x7a, 0x25, 0x8f, 0x1d, 0xe, 0x5e, 0x72 } }
A memory range descriptor.
typedef struct
EFI_PHYSICAL_ADDRESS Address;
} EFI_MEMORY_RANGE;
Address Physical address of memory location being described.
Length Length in bytes.
The capsule descriptor that describes the memory ranges a platform ﬁrmware should leave untouched.
EFI_CAPSULE_HEADER Header;
UINT32 OsRequestedMemoryType;
UINT64 NumberOfMemoryRanges;
EFI_MEMORY_RANGE MemoryRanges[];
} EFI_MEMORY_RANGE_CAPSULE;
Header
Header.CapsuleGuid = EFI_MEMORY_RANGE_CAPSULE_GUID
Header.Flags = CAPSULE_FLAGS_PERSIST_ACROSS_RESET
OsRequestedMemoryType
Must be in the 0x80000000-0xFFFFFFFF range
When UEFI Firmware processes the capsule, contents described in MemoryRanges[] will show up as
OsRequestedMemoryType values in the EFI Memory Map.
NumberofMemoryRanges Number of MemoryRanges[] entries. Must be a value of 1 or greater.
MemoryRanges[] An array of memory ranges. Equivalent to MemoryRanges[NumberOfMemoryRanges].
For a platform that intends to support the EFI_MEMORY_RANGE_CAPSULE, it must ad-
vertise EFI_MEMORY_RANGE_CAPSULE_RESULT in the EFI Conﬁguration table using the
UINT64 FirmwareMemoryRequirement;
} EFI_MEMORY_RANGE_CAPSULE_RESULT
FirmwareMemoryRequirement The maximum amount of memory in bytes that the UEFI ﬁrmware requires to
initialize.
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NumberofMemoryRanges Will be 0 if no EFI_MEMORY_RANGE_CAPSULE has been processed.
If a EFI_MEMORY_RANGE_CAPSULE was processed, this number will be identical to the
EFI_MEMORY_RANGE_CAPSULE.NumberOfMemoryRanges value.
8.5.3.4 QueryCapsuleCapabilities()
Summary
Returns if the capsule can be supported via UpdateCapsule().
Prototype
typedef
QueryCapsuleCapabilities (
OUT UINT64 *MaximumCapsuleSize,
OUT EFI_RESET_TYPE *ResetType
);
The capsules are assumed to stored in contiguous virtual memory.
CapsuleCount* Number of pointers to EFI_CAPSULE_HEADER in CapsuleHeaderArray .
MaximumCapsuleSize On output the maximum size in bytes that UpdateCapsule() can support as an argument to
UpdateCapsule() via CapsuleHeaderArray and ScatterGatherList. Undeﬁned on input.
ResetType Returns the type of reset required for the capsule update. Undeﬁned on input.
The QueryCapsuleCapabilities() function allows a caller to test to see if a capsule or capsules can be updated via
UpdateCapsule(). The Flags values in the capsule header and size of the entire capsule is checked.
If the caller needs to query for generic capsule capability a fake EFI_CAPSULE_HEADER can be constructed
where CapsuleImageSize is equal to HeaderSize that is equal to sizeof (EFI_CAPSULE_HEADER). To deter-
mine reset requirements, CAPSULE_FLAGS_PERSIST_ACROSS_RESET should be set in the Flags ﬁeld of the
EFI_CAPSULE_HEADER.
EFI_INV ALID_PARAMETER MaximumCapsuleSize is NULL.
EFI_UNSUPPORTED The capsule type is not supported on this platform, and MaximumCapsule-
Size and ResetType are undeﬁned.
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8.5.4 Exchanging information between the OS and Firmware
The ﬁrmware and an Operating System may exchange information through the OsIndicationsSupported and the
OSIndications variables as follows:
• The OsIndications variable returns a UINT64 bitmask owned by the OS and is used to indicate which features
the OS wants ﬁrmware to enable or which actions the OS wants the ﬁrmware to take. The OS will supply this
data with a SetVariable() call.
• The OsIndicationsSupported variable returns a UINT64 bitmask owned by the ﬁrmware and indicates which of
the OS indication features and actions that the ﬁrmware supports. This variable is recreated by ﬁrmware every
boot, and cannot be modiﬁed by the OS.

The EFI_OS_INDICATIONS_BOOT_TO_FW_UI bit can be set in the OsIndicationsSupported variable
by the ﬁrmware, if the ﬁrmware supports OS requests to stop at a ﬁrmware user interface. The
EFI_OS_INDICATIONS_BOOT_TO_FW_UI bit can be set by the OS in the OsIndications variable, if the OS desires
for the ﬁrmware to stop at a ﬁrmware user interface on the next boot. Once the ﬁrmware consumes this bit in the
OsIndications variable and stops at the ﬁrmware user interface, the ﬁrmware should clear the bit from the OsIndica-
tions variable in order to acknowledge to the OS that the information was consumed and, more importantly, to prevent
the ﬁrmware user interface from showing again on subsequent boots.
The EFI_OS_INDICATIONS_TIMESTAMP_REVOCATION bit can be set in the OSIndicationsSupported variable
by the ﬁrmware, if the ﬁrmware supports timestamp based revocation and the ” dbt” uthorized timestamp database
variable.
The EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED bit is set in OsIndicationsSupported variable if plat-
form supports processing of Firmware Management Protocol update capsule as deﬁned in Dependency Expression
Instruction Set . If set in OsIndications variable, the EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED bit
has no function and is cleared on the next reboot.
The EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED bit in OsIndicationsSupported variable
is set if platform supports processing of ﬁle capsules per Delivery of Capsules via ﬁle on Mass Storage Device .
When submitting capsule via the Mass Storage Device method of Delivery of Capsules via ﬁle on Mass Storage Device ,
the bit EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED in OsIndications variable must be set
by submitter to trigger processing of submitted capsule on next reboot. This bit will be cleared from OsIndications by
system ﬁrmware in all cases during processing following reboot.
The EFI_OS_INDICATIONS_CAPSULE_RESULT_V AR_SUPPORTED bit is set in OsIndicationsSupported vari-
able if platform supports reporting of deferred capsule processing by creation of result variable as deﬁned in UEFI
variable reporting on the Success or any Errors encountered in processing of capsules after restart . This bit has no
function if set in OsIndications .
The EFI_OS_INDICATIONS_START_OS_RECOVERY bit is set in the OsIndicationsSupported variable if the plat-
form supports both the ability for an OS to indicate that OS-deﬁned recovery should commence upon reboot, as well
as support for the short-form File Path Media Device Path (See Load Option Processing ). If this bit is set in OsIndi-
cations , the platform ﬁrmware must bypass processing of the BootOrder variable during boot, and skip directly to
OS-deﬁned recovery ( OS-Deﬁned Boot Option Recovery ) followed by Platform-deﬁned recovery ( Platform-Deﬁned
Boot Option Recovery ). System ﬁrmware must clear this bit in OsIndications when it starts OS-deﬁned recovery.
The EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY bit is set in the OsIndicationsSupported variable
if the platform supports both the ability for an OS to indicate that Platform-deﬁned recovery should commence upon
reboot, as well as support for the short-form File Path Media Device Path ( Load Option Processing ). If this bit is
set in OsIndications , the platform ﬁrmware must bypass processing of the BootOrder variable during boot, and skip
directly to Platform-Deﬁned Boot Option Recovery . System ﬁrmware must clear this bit in OsIndications when it
starts Platform-deﬁned recovery.
In all cases, if either of EFI_OS_INDICATIONS_START_OS_RECOVERY or
EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY is set in OsIndicationsSupported , both must be
8.5. Miscellaneous Runtime Services 242Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
set and supported.
The EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH bit is set in the OsIndications variable by submit-
ter to trigger collecting current conﬁguration and reporting the refreshed data to EFI System Conﬁguration Table on
next boot. If not set, platform will not collect current conﬁguration but report the cached conﬁguration data to EFI
System Conﬁguration Table. The conﬁguration data shall be installed to EFI System Conﬁguration Table using the
format of EFI_JSON_CAPSULE_CONFIG_DATA deﬁned in Deﬁned JSON Capsule Data Structure . This bit will be
cleared from OsIndications by system ﬁrmware once the refreshed data is reported.
If set in the OsIndicationsSupported variable, the EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH bit
#define EFI_OS_INDICATIONS_BOOT_TO_FW_UI 0x0000000000000001
#define EFI_OS_INDICATIONS_TIMESTAMP_REVOCATION \ 0x0000000000000002
#define EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED 0x0000000000000004
#define EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED \ 0x0000000000000008
#define EFI_OS_INDICATIONS_CAPSULE_RESULT_VAR_SUPPORTED 0x0000000000000010
#define EFI_OS_INDICATIONS_START_OS_RECOVERY 0x0000000000000020
#define EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY \ 0x0000000000000040
˓→#define EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH \
˓→0x0000000000000080
8.5.5 Delivery of Capsules via ﬁle on Mass Storage Device
As an alternative to the UpdateCapsule() runtime API, capsules of any type supported by platform may also be de-
livered to ﬁrmware via a ﬁle within the EFI system partition on the mass storage device targeted for boot. Capsules
staged using this method are processed on the next system restart. This method is only available when booting from
mass storage devices which are formatted with GPT and contain an EFI System Partition in the device image. System
ﬁrmware will search for capsule when EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED bit in
OsIndications is set as described in Exchanging information between the OS and Firmware .
The directory EFIUpdateCapsule (letter case ignored) within the active EFI System Partition is deﬁned for delivery of
capsule to ﬁrmware. The binary structure of a capsule ﬁle on mass storage device is identical to the contents of cap-
sule delivered via the EFI RunTime API except that fragmentation using EFI_CAPSULE_BLOCK_DESCRIPTOR
is not supported and the single capsule must be stored in contiguous bytes within the ﬁle starting with
EFI_CAPSULE_HEADER. The size of the ﬁle must equal EFI_CAPSULE_HEADER. CapsuleImageSize or error
will be generated and the capsule ignored. Only a single capsule with a single EFI_CAPSULE_HEADER may be
submitted within a ﬁle but more than one ﬁle each containing a capsule may be submitted during a single restart.
The ﬁle name of the capsule shall be chosen by submitter using 8-bit ASCII characters appropriate to the ﬁle system
of the EFI system partition ( System Partition ). After examination and processing of a ﬁle placed in this directory the
ﬁle will (if possible) be deleted by ﬁrmware. The deletion is performed in case of successful processing and also in
the case of error but failure to successfully delete is not itself a reportable error.
More than one capsule ﬁle each containing a single capsule image may be stored in the speciﬁed directory. In case
of multiple ﬁles, the system ﬁrmware shall process ﬁles in alphabetical order using sort based on CHAR16 numerical
value of ﬁle name characters, compared left to right. Lower case letter characters will be converted to upper case
before compare. When comparing ﬁle names of unequal length, the space character shall be used to pad shorter ﬁle
names. In case of ﬁle name containing one or more period characters (.), the right-most period, and the text to the right
8.5. Miscellaneous Runtime Services 243Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
of the right-most period in the ﬁle name, will be removed before compare. In case of any ﬁle names with identical text
after excluding any text after the right-most period, the order of processing shall be determined by sorting of any text
found to right of the right-most period in ﬁle name string.
If a capsule processing is terminated by error any remaining additional capsule ﬁles will be processed normally.
The directory EFIUpdateCapsule is checked for capsules only within the EFI system partition on the device speciﬁed
in the active boot option determine by reference to BootNext variable or BootOrder variable processing. The active
Boot Variable is the variable with highest priority BootNext or within BootOrder that refers to a device found to be
present. Boot variables in BootOrder but referring to devices not present are ignored when determining active boot
variable.
The device to be checked for EFIUpdateCapsule is identiﬁed by reference to FilePathList ﬁeld within the selected
active Boot#### variable. The system ﬁrmware is not required to check mass storage devices that do not contain boot
target that is highest priority for boot nor to check a second EFI system partition not the target of the active boot
variable.

variable.
variable.
In all cases that a capsule is identiﬁed for processing the system is restarted after capsule processing is completed. In
case where BootNext variable was set, this variable is cleared when capsule processing is performed without actual
boot of the variable indicated.
8.5.6 UEFI variable reporting on the Success or any Errors encountered in process-
ing of capsules after restart
In cases where the processing of capsules is (1) delivered by call to UpdateCapsule() API but deferred to next restart,
or (2) when capsules are delivered via mass storage device, a UEFI variable is created by ﬁrmware to indicate to
capsule provider the status of the capsule processing. In the case were multiple capsules are delivered in calls to
UpdateCapsule(), or multiple ﬁles on disk as described in Delivery of Capsules via ﬁle on Mass Storage Device , or
when a capsule contains multiple payloads as described in Dependency Expression Instruction Set , a separate result
variable will be created for each capsule payload processed. The ﬁrmware will over-write result variables when
calculated variable name already exists. However, to avoid unnecessarily consuming system variable store the result
variable should be deleted by capsule provider after result status is examined.
UEFI variable reports will not be used when the entirety of capsule processing occurs within the call to UpdateCap-
sule() function.
The reporting variable attributes will be EFI_V ARIABLE_NON_VOLATILE +
EFI_V ARIABLE_BOOTSERVICE_ACCESS + EFI_V ARIABLE_RUNTIME_ACCESS.
The Vendor GUID of the reporting variable will be EFI_CAPSULE_REPORT_GUID. The name of the reporting
variable will be CapsuleNNNN where NNNN is 4-digit hex number chosen by the ﬁrmware. The values of NNNN will
be incremented by ﬁrmware starting at Capsule0000 and continuing up to the platform-deﬁned maximum.
The platform will publish the platform maximum in a read-only variable named EFI_CAPSULE_REPORT_GUID:
CapsuleMax . The contents of CapsuleMax will be the string “CapsuleNNNN” where NNNN is the highest value used
by platform before rolling over to Capsule0000 .The platform will also publish the name of the last variable created in
EFI_CAPSULE_REPORT_GUID: CapsuleLast .
When creating a new result variable, any previous variable with the same name will be overwritten. In case where
variable storage is limited system ﬁrmware may optionally delete oldest report variables to create free space. If
sufﬁcient variable space cannot be freed the variable is not created.
Table 8.22: Variables Using EFI_CAPSULE_REPORT_GUID
Variable Name Attributes Internal Format
Capsule0000, Capsule0001, . . .
up to maxNV , BS, RT EFI_CAP SULE_RESULT_V ARIABLE
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Table 8.22 – continued from previous page
CapsuleMax BS, RT, Read-Only CHAR16[11] (no zero terminator)
CapsuleLast NV , BS, RT, Read-Only CHAR16[11] (no zero terminator)
8.5.6.1 EFI_CAPSULE_REPORT_GUID
// {39B68C46-F7FB-441B-B6EC-16B0F69821F3}
#define EFI_CAPSULE_REPORT_GUID \
{ 0x39b68c46, 0xf7fb, 0x441b, \
{0xb6, 0xec, 0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3 }};
8.5.6.1.1 Structure of the Capsule Processing ResultVariable
The Capsule Processing Result Variable contents always begin with the
EFI_CAPSULE_RESULT_V ARIABLE_HEADER structure. The value of CapsuleGuid determines any addi-
tional data that may follow within the instance of the Result Variable contents. For some values of CapsuleGuid no
additional data may be deﬁned.
As noted below, VariableTotalSize is the size of complete result variable including the entire header and any additional
data required for particular CapsuleGuid types.
UINT32 VariableTotalSize;
UINT32 Reserved; // foralignment
EFI_TIME CapsuleProcessed;
EFI_STATUS CapsuleStatus;
} EFI_CAPSULE_RESULT_VARIABLE_HEADER;
VariableTotalSize Size in bytes of the variable including any data beyond header as speciﬁed by CapsuleGuid .
CapsuleGuid Guid from EFI_CAPSULE_HEADER
CapsuleProcessed Timestamp using system time when processing completed.
CapsuleStatus Result of the capsule processing. Exact interpretation of any error code may depend upon type of
capsule processed.
8.5.6.1.2 Additional Structure When CapsuleGuid is EFI_FIRMWARE_MANAGEMENT_CAPSULE
_ID_GUID
The capsule Processing Result Variable contents always begin with EFI_CAPSULE_RESULT_V ARIABLE_HEADER.
When CapsuleGuid is EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID, the header is followed by addi-
tional data as deﬁned by EFI_CAPSULE_RESULT_V ARIABLE_FMP.
UINT8 PayloadIndex;
UINT8 UpdateImageIndex;
EFI_GUID UpdateImageTypeId;
// CHAR16 CapsuleFileName [];
// CHAR16 CapsuleTarget [];
} EFI_CAPSULE_RESULT_VARIABLE_FMP;
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Version The version of this structure, currently 0x00000001.
PayloadIndex The index, starting from zero, of the payload within the FMP capsule which was processed to generate
this report.
UpdateImageIndex TheUpdateImageIndex from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER
(after unsigned conversion from UINT8 to UINT16).
UpdateImageTypeId TheUpdateImageTypeId Guid from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER.
CapsuleFileName In case of capsule loaded from disk, the zero-terminated array containing ﬁle name of capsule that
was processed. In case of capsule submitted directly to UpdateCapsule() there is no ﬁle name, and this ﬁeld is
required to contain a single 16-bit zero character which is included in VariableTotalSize .
CapsuleTarget This ﬁeld will contain a zero-terminated CHAR16 string containing the text representation of the
device path of device publishing Firmware Management Protocol (if present). In case where device path is not
present and the target is not otherwise known to ﬁrmware, or when payload was blocked by policy, or skipped,
this ﬁeld is required to contain a single 16-bit zero character which is included in VariableTotalSize .
8.5.6.1.3 Additional Structure When CapsuleGuid is EFI_JSON_CAPSULE_ID_GUID
The Capsule Processing Result Variable contents always begin with EFI_CAPSULE_RESULT_V ARIABLE_HEADER.
When CapsuleGuid is EFI_JSON_CAPSULE_ID_GUID, the header is followed by additional data as deﬁned by
EFI_CAPSULE_RESULT_V ARIABLE_JSON.
UINT32 CapsuleId;
UINT32 RespLength;
UINT8 Resp[];
} EFI_CAPSULE_RESULT_VARIABLE_JSON;
CapsuleId
The unique identiﬁer of the capsule whose processing result is recorded in this variable.
0x00000000 - 0xEFFFFFFF - Implementation Reserved
0xF0000000 - 0xFFFFFFFF - Speciﬁcation Reserved
#deﬁne REDFISH_DEFINED_JSON_SCHEMA 0xF000000
The JSON payload shall conform to a Redﬁsh-deﬁned JSON schema, see DMTF-Redﬁsh Speciﬁcation.
RespLength The length of Resp in bytes.
Resp Variable length buffer containing the replied JSON payload to the caller who delivered JSON capsule to system.
The deﬁnition of the JSON schema used in the replied payload is beyond the scope of this speciﬁcation.
Table 8.23: Status Codes Returned in CapsuleStatus
EFI_SUCCESS Valid capsule was passed and the capsule has been successfully processed
EFI_INV ALID_PARAMETER Invalid capsule size, or an incompatible set of ﬂags were set in the capsule
header. In the case of a capsule ﬁle, the ﬁle size was not valid or an error
was detected in the internal structure of the ﬁle.
EFI_ACCESS_DENIED Image within capsule was not loaded because the platform policy prohibits
the image from being loaded.
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Table 8.23 – continued from previous page
EFI_LOAD_ERROR For capsule with included driver, no driver with correct format for the plat-
form was found.
EFI_UNSUPPORTED The capsule type is not supported on this platform. Or the capsule internal
structures were not recognized as valid by the platform.
EFI_OUT_OF_RESOURCES There were insufﬁcient resources to process the capsule.
EFI_NOT_READY Capsule payload blocked by platform policy.
EFI_ABORTED Capsule payload was skipped.
8.5. Miscellaneous Runtime Services 247CHAPTER
NINE
PROTOCOLS - EFI LOADED IMAGE
This section deﬁnes EFI_LOADED_IMAGE_PROTOCOL and the EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL.
Respectively, these protocols describe an Image that has been loaded into memory and speciﬁes the device path used
when a PE/COFF image was loaded through the EFI Boot Service LoadImage(). These descriptions include the

NINE
source from which the image was loaded, the current location of the image in memory, the type of memory allocated
for the image, and the parameters passed to the image when it was invoked.
9.1 EFI Loaded Image Protocol
9.1.1 EFI_LOADED_IMAGE_PROTOCOL
Summary
Can be used on any image handle to obtain information about the loaded image.
GUID
#define EFI_LOADED_IMAGE_PROTOCOL_GUID \
{0x5B1B31A1,0x9562,0x11d2,\
{0x8E,0x3F,0x00,0xA0,0xC9,0x69,0x72,0x3B}}
Revision Number
#define EFI_LOADED_IMAGE_PROTOCOL_REVISION 0x1000
EFI_HANDLE ParentHandle;
EFI_System_Table *SystemTable;
// Source location of the image
EFI_HANDLE DeviceHandle;
EFI_DEVICE_PATH_PROTOCOL *FilePath;
VOID *Reserved;
// Image’s load options
UINT32 LoadOptionsSize;
VOID *LoadOptions;
// Location where image was loaded
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VOID *ImageBase;
UINT64 ImageSize;
EFI_MEMORY_TYPE ImageCodeType;
EFI_MEMORY_TYPE ImageDataType;
EFI_IMAGE_UNLOAD Unload;
} EFI_LOADED_IMAGE_PROTOCOL;
Revision Deﬁnes the revision of the EFI_LOADED_IMAGE_PROTOCOL structure. All future revisions will be
backward compatible to the current revision.
ParentHandle Parent image’s image handle. NULL if the image is loaded directly from the ﬁrmware’s boot manager.
Type EFI_HANDLE is deﬁned in Services – Boot Services.
SystemTable The image’s EFI system table pointer. Type EFI_SYSTEM_TABLE deﬁned in EFI System Table .
DeviceHandle The device handle that the EFI Image was loaded from. Type EFI_HANDLE is deﬁned in Services –
Boot Services.
FilePath A pointer to the ﬁle path portion speciﬁc to DeviceHandle that the EFI Image was loaded from.
Reserved Reserved. DO NOT USE.
LoadOptionsSize The size in bytes of LoadOptions.
LoadOptions A pointer to the image’s binary load options. See the OptionalData parameter in the Load Options
section of the Boot Manager chapter for information on the source of the LoadOptions data.
ImageBase The base address at which the image was loaded.
ImageSize The size in bytes of the loaded image.
ImageCodeType The memory type that the code sections were loaded as. Type EFI_MEMORY_TYPE is deﬁned in
Services – Boot Services.
ImageDataType The memory type that the data sections were loaded as. Type EFI_MEMORY_TYPE is deﬁned in in
Unload Function that unloads the image - see Section 9.1.2.
Each loaded image has an image handle that supports EFI_LOADED_IMAGE_PROTOCOL. When an image is
started, it is passed the image handle for itself. The image can use the handle to obtain its relevant image data stored
in the EFI_LOADED_IMAGE_PROTOCOL structure, such as its load options.
9.1.2 EFI_LOADED_IMAGE_PROTOCOL.Unload()
Summary
Unloads an image from memory.
Prototype
typedef
);
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ImageHandle The handle to the image to unload. Type EFI_HANDLE Driver Model Boot Services
The Unload() function is a callback that a driver registers to do cleanup when the UnloadImage boot service function
is called.
EFI_SUCCESS The image was unloaded.
EFI_INV ALID_PARAMETER TheImageHandle was not valid.
9.2 EFI Loaded Image Device Path Protocol
9.2.1 EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL
Summary
When installed, the Loaded Image Device Path Protocol speciﬁes the device path that was used when a PE/COFF
image was loaded through the EFI Boot Service LoadImage().
GUID
#define EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID \
{0xbc62157e,0x3e33,0x4fec,\
{0x99,0x20,0x2d,0x3b,0x36,0xd7,0x50,0xdf}}
The Loaded Image Device Path Protocol uses the same protocol interface structure as the Device Path Protocol deﬁned
in Chapter 9. The only difference between the Device Path Protocol and the Loaded Image Device Path Protocol is
the protocol GUID value.
The Loaded Image Device Path Protocol must be installed onto the image handle of a PE/COFF image loaded through
the EFI Boot Service LoadImage(). A copy of the device path speciﬁed by the DevicePath parameter to the EFI Boot
Service LoadImage() is made before it is installed onto the image handle. It is legal to call LoadImage() for a buffer
in memory with a NULL DevicePath parameter. In this case, the Loaded Image Device Path Protocol is installed with
a NULL interface pointer.
9.2. EFI Loaded Image Device Path Protocol 250CHAPTER
TEN
PROTOCOLS – DEVICE PATH PROTOCOL
This section contains the deﬁnition of the device path protocol and the information needed to construct and manage
device paths in the UEFI environment. A device path is constructed and used by the ﬁrmware to convey the location
of important devices, such as the boot device and console, consistent with the software-visible topology of the system.
10.1 Device Path Overview
ADevice Path is used to deﬁne the programmatic path to a device. The primary purpose of a Device Path is to allow
an application, such as an OS loader, to determine the physical device that the interfaces are abstracting.
A collection of device paths is usually referred to as a name space. ACPI, for example, is rooted around a name space
that is written in ASL (ACPI Source Language). Given that EFI does not replace ACPI and defers to ACPI when ever
possible, it would seem logical to utilize the ACPI name space in EFI. However, the ACPI name space was designed
for usage at operating system runtime and does not ﬁt well in platform ﬁrmware or OS loaders. Given this, EFI deﬁnes
its own name space, called a Device Path .
A Device Path is designed to make maximum leverage of the ACPI name space. One of the key structures in the
Device Path deﬁnes the linkage back to the ACPI name space. The Device Path also is used to ﬁll in the gaps where
ACPI defers to buses with standard enumeration algorithms. The Device Path is able to relate information about
which device is being used on buses with standard enumeration mechanisms. The Device Path is also used to deﬁne
the location on a medium where a ﬁle should be, or where it was loaded from. A special case of the Device Path can
also be used to support the optional booting of legacy operating systems from legacy media.
The Device Path was designed so that the OS loader and the operating system could tell which devices the platform
ﬁrmware was using as boot devices. This allows the operating system to maintain a view of the system that is consistent
with the platform ﬁrmware. An example of this is a “headless” system that is using a network connection as the boot
device and console. In such a case, the ﬁrmware will convey to the operating system the network adapter and network
protocol information being used as the console and boot device in the device path for these devices.
10.2 EFI Device Path Protocol
This section provides a detailed description of EFI_DEVICE_PATH_PROTOCOL.
Summary
Can be used on any device handle to obtain generic path/location information concerning the physical device or logical
device. If the handle does not logically map to a physical device, the handle may not necessarily support the device
path protocol. The device path describes the location of the device the handle is for. The size of the Device Path can
be determined from the structures that make up the Device Path.
GUID
251Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_DEVICE_PATH_PROTOCOL_GUID \
{0x09576e91,0x6d3f,0x11d2,\
{0x8e,0x39,0x00,0xa0,0xc9,0x69,0x72,0x3b}}
// EFI_DEVICE_PATH_PROTOCOL
typedef struct _EFI_DEVICE_PATH_PROTOCOL {
UINT8 SubType;
UINT8 Length[2];
} EFI_DEVICE_PATH_PROTOCOL;
The executing UEFI Image may use the device path to match its own device drivers to the particular device. Note
that the executing UEFI OS loader and UEFI application images must access all physical devices via Boot Services
device handles until EFI_BOOT_SERVICES.ExitBootServices() is successfully called. A UEFI driver may access only
a physical device for which it provides functionality.
10.3 Device Path Nodes
There are six major types of Device Path nodes:
• Hardware Device Path. This Device Path deﬁnes how a device is attached to the resource domain of a system,
where resource domain is simply the shared memory, memory mapped I/O, and I/O space of the system.
• ACPI Device Path. This Device Path is used to describe devices whose enumeration is not described in an
industry-standard fashion. These devices must be described using ACPI AML in the ACPI name space; this
Device Path is a linkage to the ACPI name space.

• Messaging Device Path. This Device Path is used to describe the connection of devices outside the resource
domain of the system. This Device Path can describe physical messaging information such as a SCSI ID, or
abstract information such as networking protocol IP addresses.
• Media Device Path. This Device Path is used to describe the portion of a medium that is being abstracted by a
boot service. For example, a Media Device Path could deﬁne which partition on a hard drive was being used.
• BIOS Boot Speciﬁcation Device Path. This Device Path is used to point to boot legacy operating systems; it is
based on the BIOS Boot Speciﬁcation Version 1.01. See References for details on obtaining this speciﬁcation.
• End of Hardware Device Path. Depending on the Sub-Type, this Device Path node is used to indicate the end of
the Device Path instance or Device Path structure.
10.3. Device Path Nodes 252Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.1 Generic Device Path Structures
A Device Path is a variable-length binary structure that is made up of variable-length generic Device Path nodes.
Generic Device Path Node Structure deﬁnes the structure of a variable-length generic Device Path node and the lengths
of its components. The table (below) deﬁnes the type and sub-type values corresponding to the Device Paths described
inDevice Path Nodes ; all other type and sub-type values are Reserved.
Table 10.1: Generic Device Path Node Structure
Type 0 1
Type 0x01 - Hardware Device Path
Type 0x02 - ACPI Device Path
Type 0x03 - Messaging Device Path
Type 0x04 - Media Device Path
Type 0x05 - BIOS Boot Speciﬁcation Device Path
Type 0x7F - End of Hardware Device Path
Sub-Type 1 1 Sub-Type - Varies by Type. (See table below)
Length 2 2 Length of this structure in bytes. Length is 4 + nbytes.
Speciﬁc Device Path Data 4 n Speciﬁc Device Path data. Type and Sub-Type deﬁne
type of data. Size of data is included in Length.
A Device Path is a series of generic Device Path nodes. The ﬁrst Device Path node starts at byte offset zero of the
Device Path. The next Device Path node starts at the end of the previous Device Path node. Therefore all nodes are
byte-packed data structures that may appear on any byte boundary. All code references to device path notes must
assume all ﬁelds are unaligned. Since every Device Path node contains a length ﬁeld in a known place, it is possible
to traverse Device Path nodes that are of an unknown type. There is no limit to the number, type, or sequence of nodes
in a Device Path.
A Device Path is terminated by an End of Hardware Device Path node. This type of node has two sub-types ( Device
Path End Structure ):
•End This Instance of a Device Path (sub-type 0x01). This type of node terminates one Device Path instance and
denotes the start of another. This is only required when an environment variable represents multiple devices.
An example of this would be the ConsoleOut environment variable that consists of both a VGA console and
serial output console. This variable would describe a console output stream that is sent to both VGA and serial
concurrently and thus has a Device Path that contains two complete Device Paths.
•End Entire Device Path (sub-type 0xFF). This type of node terminates an entire Device Path. Software searches
for this sub-type to ﬁnd the end of a Device Path. All Device Paths must end with this sub-type.
Table 10.2: Device Path End Structure
Type 0 1 Type 0x7F - End of Hardware Device Path
Sub-Type 1 1 Sub-Type 0xFF - End Entire Device Path, or Sub-Type 0x01 - End
This Instance of a Device Path and start a new Device Path
Length 2 2 Length of this structure in bytes. Length is 4 bytes.
10.3. Device Path Nodes 253Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.2 Hardware Device Path
This Device Path deﬁnes how a device is attached to the resource domain of a system, where resource domain is
simply the shared memory, memory mapped I/O, and I/O space of the system. It is possible to have multiple levels of
Hardware Device Path such as a PCCARD device that was attached to a PCCARD PCI controller.
10.3.2.1 PCI Device Path
The Device Path for PCI deﬁnes the path to the PCI conﬁguration space address for a PCI device. There is one PCI
Device Path entry for each device and function number that deﬁnes the path from the root PCI bus to the device.
Because the PCI bus number of a device may potentially change, a ﬂat encoding of single PCI Device Path entry
cannot be used. An example of this is when a PCI device is behind a bridge, and one of the following events occurs:
• OS performs a Plug and Play conﬁguration of the PCI bus.
• A hot plug of a PCI device is performed.
• The system conﬁguration changes between reboots.
The PCI Device Path entry must be preceded by an ACPI Device Path entry that uniquely identiﬁes the PCI root bus.
The programming of root PCI bridges is not deﬁned by any PCI speciﬁcation and this is why an ACPI Device Path
entry is required.
Table 10.3: PCI Device Path
Type 0 1 Type 1 - Hardware Device Path
Sub-Type 1 1 Sub-Type 1 - PCI
Length 2 2 Length of this structure is 6 bytes
Function 4 1 PCI Function Number
Device 5 1 PCI Device Number
10.3.2.2 PCCARD Device Path
Pccard Device Path
Table 10.4: PCCARD Device Path
Sub-Type 1 1 Sub-Type 2 - PCCARD
Length 2 2 Length of this structure in bytes. Length is 5 bytes.
Function Number 4 1 Function Number (0 = First Function)
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10.3.2.3 Memory Mapped Device Path
Table 10.5: Memory Mapped Device Path
Type 0 1 Type 1 - Hardware Device Path.
Sub-Type 1 1 Sub-Type 3 - Memory Mapped.
Length 2 2 Length of this structure in bytes. Length is 24 bytes.
Memory Type 4 4 EFI_MEMORY_TYPE. Type
EFI_MEMORY_TYPE is deﬁned in the
EFI_BOOT_SERVICES.AllocatePages() function
Start Address 8 8 Starting Memory Address.
End Address 16 8 Ending Memory Address.
10.3.2.4 Vendor Device Path
The Vendor Device Path allows the creation of vendor-deﬁned Device Paths. A vendor must allocate a Vendor GUID
for a Device Path. The Vendor GUID can then be used to deﬁne the contents on the n bytes that follow in the Vendor
Device Path node.
Table 10.6: Vendor-Deﬁned Device Path
Sub-Type 1 1 Sub-Type 4 - Vendor.
Length 2 2 Length of this structure in bytes. Length is 20 + n bytes.
Vendor_GUID 4 16 Vendor-assigned GUID that deﬁnes the data that fol-
lows.
Vendor Deﬁned Data 20 n Vendor-deﬁned variable size data.
10.3.2.5 Controller Device Path
Table 10.7: Controller Device Path
Mnemonic Byte Offset Byte Length Description
Sub-Type 1 1 Sub-Type 5 - Controller.
Length 2 2 Length of this structure in bytes. Length is 8 bytes.
Controller
Number4 4 Controller number.
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10.3.2.6 BMC Device Path
The Device Path for a Baseboard Management Controller (BMC) host interface.
Table 10.8: BMC Device Path
Sub-Type 1 1 Sub Type 6 - BMC
Length 2 2 Length of this structure in bytes. Length is 13 bytes.
Interface Type 4 1 The Baseboard Management Controller (BMC) host interface type:
0x00: Unknown 0x01: KCS: Keyboard Controller Style 0x02:
SMIC: Server Management Interface Chip 0x03: BT: Block Trans-
fer
Base Address 5 8 Base address (either memory-mapped or I/O) of the BMC. If the le
ast-signiﬁcant bit of the ﬁeld is a 1, the address is in I/O space; oth-
erwise, the address is memory-mapped. Refer to the IPMI Interface
Speciﬁcation for usage details.
10.3.3 ACPI Device Path
This Device Path contains ACPI Device IDs that represent a device’s Plug and Play Hardware ID and its corresponding
unique persistent ID. The ACPI IDs are stored in the ACPI _HID, _CID, and _UID device identiﬁcation objects that
are associated with a device. The ACPI Device Path contains values that must match exactly the ACPI name space
that is provided by the platform ﬁrmware to the operating system. Refer to the ACPI speciﬁcation for a complete
description of the _HID, _CID, and _UID device identiﬁcation objects.
The _HID and _CID values are optional device identiﬁcation objects that appear in the ACPI name space. If only
_HID is present, the _HID must be used to describe any device that will be enumerated by the ACPI driver. The _CID,
if present, contains information that is important for the OS to attach generic driver (e.g., PCI Bus Driver), while the

_HID contains information important for the OS to attach device-speciﬁc driver. The ACPI bus driver only enumerates
a device when no standard bus enumerator exists for a device.
The _UID object provides the OS with a serial number-style ID for a device that does not change across reboots. The
object is optional, but is required when a system contains two devices that report the same _HID. The _UID only needs
to be unique among all device objects with the same _HID value. If no _UID exists in the APCI name space for a
_HID the value of zero must be stored in the _UID ﬁeld of the ACPI Device Path.
The ACPI Device Path is only used to describe devices that are not deﬁned by a Hardware Device Path. An _HID
(along with _CID if present) is required to represent a PCI root bridge, since the PCI speciﬁcation does not deﬁne the
programming model for a PCI root bridge. There are two subtypes of the ACPI Device Path: a simple subtype that
only includes the _HID and _UID ﬁelds, and an extended subtype that includes the _HID, _CID, and _UID ﬁelds.
The ACPI Device Path node only supports numeric 32-bit values for the _HID and _UID values. The Expanded ACPI
Device Path node supports both numeric and string values for the _HID, _UID, and _CID values. As a result, the ACPI
Device Path node is smaller and should be used if possible to reduce the size of device paths that may potentially be
stored in nonvolatile storage. If a string value is required for the _HID ﬁeld, or a string value is required for the _UID
ﬁeld, or a _CID ﬁeld is required, then the Expanded ACPI Device Path node must be used. If a string ﬁeld of the
Expanded ACPI Device Path node is present, then the corresponding numeric ﬁeld is ignored.
The _HID and _CID ﬁelds in the ACPI Device Path node and Expanded ACPI Device Path node are stored as a 32-
bit compressed EISA-type IDs. The following macro can be used to compute these EISA-type IDs from a Plug and
Play Hardware ID. The Plug and Play Hardware IDs used to compute the _HID and _CID ﬁelds in the EFI device
path nodes must match the Plug and Play Hardware IDs used to build the matching entries in the ACPI tables. The
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compressed EISA-type IDs produced by this macro differ from the compressed EISA-type IDs stored in ACPI tables.
As a result, the compressed EISA-type IDs from the ACPI Device Path nodes cannot be directly compared to the
compressed EISA-type IDs from the ACPI table.
#define EFI_PNP_ID(ID) (UINT32)(((ID) << 16) | 0x41D0)
#define EISA_PNP_ID(ID) EFI_PNP_ID(ID)
Table 10.9: ACPI Device Path
Type 0 1 Type 2 - ACPI Device Path.
Sub-Type 1 1 Sub-Type 1 ACPI Device Path.
Length 2 2 Length of this structure in bytes. Length is 12 bytes.
_HID 4 4 Device’s PnP hardware ID stored in a numeric 32-bit compressed
EISA-type ID. This value must match the corresponding _HID in
the ACPI name space.
_UID 8 4 Unique ID that is required by ACPI if two devices have the same
_HID. This value must also match the corresponding _UID/_HID
pair in the ACPI name space. Only the 32-bit numeric value type
of _UID is supported; thus strings must not be used for the _UID in
Table 10.10: Expanded ACPI Device Path
Sub-Type 1 1 Sub-Type 2 Expanded ACPI Device Path.
Length 2 2 Length of this structure in bytes. Minimum length is 19 bytes. The
actual size will depend on the size of the _HIDSTR, _UIDSTR, and
_CIDSTR ﬁelds.
pair in the ACPI name space.
_CID 12 4 Device’s compatible PnP hardware ID stored in a numeric 32-bit
compressed EISA-type ID. This value must match at least one of
the compatible device IDs returned by the corresponding _CID in
_HIDSTR 16 >=1 Device’s PnP hardware ID stored as a null-terminated ASCII string.
This value must match the corresponding _HID in the ACPI name
space. If the length of this string not including the null-terminator is
0, then the _HID ﬁeld is used. If the length of this null-terminated
string is greater than 0, then this ﬁeld supersedes the _HID ﬁeld.
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Table 10.10 – continued from previous page
_UIDSTR Varies >=1 Unique ID that is required by ACPI if two devices have the same
pair in the ACPI name space. This value is stored as a null-
terminated ASCII string. If the length of this string not including
the null-terminator is 0, then the _UID ﬁeld is used. If the length
of this null-terminated string is greater than 0, then this ﬁeld super-
sedes the _UID ﬁeld. The Byte Offset of this ﬁeld can be computed
by adding 16 to the size of the _HIDSTR ﬁeld.
_CIDSTR Varies >=1 Device’s compatible PnP hardware ID stored as a null-terminated
ASCII string. This value must match at least one of the compatible
device IDs returned by the corresponding _CID in the ACPI name
space. If the length of this string not including the null-terminator
is 0, then the _CID ﬁeld is used. If the length of this null-terminated
string is greater than 0, then this ﬁeld supersedes the _CID ﬁeld.
The Byte Offset of this ﬁeld can be computed by adding 16 to the
sum of the sizes of the _HIDSTR and _UIDSTR ﬁelds.
10.3.3.1 ACPI _ADR Device Path
The _ADR device path is used to contain video output device attributes to support the Graphics Output Protocol. The
device path can contain multiple _ADR entries if multiple video output devices are displaying the same output.
Table 10.11: ACPI _ADR Device Path
Type 0 1 Type 2 - ACPI Device Path
Sub-Type 1 1 Sub-Type3 _ADR Device Path
Length 2 2 Length of this structure in bytes. Minimum length is 8.
_ADR 4 4 _ADR value. For video output devices the value of this ﬁeld comes
from Table B-2 ACPI 3.0 speciﬁcation. At least one _ADR value is
required
Additional _ADR 8 N This device path may optionally contain more than one _ADR entry.
10.3.3.2 NVDIMM Device Path
This device path describes an NVDIMM device using the ACPI 6.0 speciﬁcation deﬁned NFIT Device Handle as the
identiﬁer.
Table 10.12: NVDIMM Device Path
Sub-Type 1 1 Sub-type 4 - NVDIMM Device
Length 2 2 8 - Single NFIT Device Handle is supported.
NFIT Device Han-
dle4 4 NFIT Device Handle - Unique physical identiﬁer. See ACPI De-
ﬁned Devices and Device Speciﬁc Objects section, NVDIMM De-
vices sub-chapter for the speciﬁc deﬁnition of the ﬁelds utilized for
this handle.
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10.3.4 Messaging Device Path
This Device Path is used to describe the connection of devices outside the resource domain of the system. This Device
Path can describe physical messaging information like SCSI ID, or abstract information like networking protocol IP
addresses.
10.3.4.1 ATAPI Device Path
Table 10.13: ATAPI Device Path
Type 0 1 Type 3 - Messaging Device Path
Sub-Type 1 1 Sub-Type 1 - ATAPI
PrimarySecondary 4 1 Set to zero for primary or one for secondary
SlaveMaster 5 1 Set to zero for master or one for slave mode
Logical Unit Num-
ber6 2 Logical Unit Number
10.3.4.2 SCSI Device Path
Table 10.14: SCSI Device Path
Sub-Type 1 1 Sub-Type 2 - SCSI
Target ID 4 2 Target ID on the SCSI bus (PUN)
ber6 2 Logical Unit Number ( LUN)
10.3.4.3 Fibre Channel Device Path
Table 10.15: Fibre Channel Device Path
Sub-Type 1 1 Sub-Type 3 - Fibre Channel
Reserved 4 4 Reserved
World Wide Name 8 8 Fibre Channel World Wide Name
ber16 8 Fibre Channel Logical Unit Number
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Table 10.16: Fibre Channel Ex Device Path
Sub-Type 1 1 Sub-Type 21 - Fibre Channel Ex
World Wide Name 8 8 8 byte array containing Fibre Channel End Device Port Name
(a.k.a., World Wide Name)

ber16 8 8 byte array containing Fibre Channel Logical Unit Number
The Fibre Channel Ex device path clariﬁes the deﬁnition of the Logical Unit Number ﬁeld to conform with the T-10
SCSI Architecture Model 4 speciﬁcation. The 8 byte Logical Unit Number ﬁeld in the device path must conform with
a logical unit number returned by a SCSI REPORT LUNS command.
When the Fibre Channel Ex Device Path is used with the Extended SCSI Pass Thru Protocol the UINT64 LUN
argument must be converted to the eight byte array Logical Unit Number ﬁeld in the device path by treating the eight
byte array as an EFI UINT64.For example a Logical Unit Number array of { 0,1,2,3,4,5,6,7 } becomes a UINT64 of
0x0706050403020100.
When an application client displays or otherwise makes a 64-bit LUN visible to a user, it should be done in confor-
mance with SAM-4. SAM-4 requires a LUN to be displayed in hexadecimal format with byte 0 ﬁrst (i.e., on the left)
and byte 7 last (i.e., on the right) regardless of the internal representation of the LUN. UEFI deﬁnes all data structures
a “little endian” and SCSI deﬁnes all data structures as “big endian”.Fibre Channel Ex Device Path Example shows
an example device path for a Fibre Channel controller on a typical UEFI platform. This Fibre Channel Controller is
connected to the port 0 of the root hub, and its interface number is 0. The Fibre Channel Host Controller is a PCI
device whose PCI device number 0x1F and PCI function 0x00. So, the whole device path for this Fibre Channel Con-
troller consists an ACPI Device Path Node, a PCI Device Path Node, a Fibre Channel Device Path Node and a Device
Path End Structure. The _HID and _UID must match the ACPI table description of the PCI Root Bridge. The Fibre
Channel WWN and LUN were picked to show byte order and they are not typical real world values. The shorthand
notation for this device path is:
PciRoot(0)/PCI(31,0)/FibreEx(0x0001020304050607, 0x0001020304050607)
Table 10.17: Fibre Channel Ex Device Path Example
Byte Off-
setByte
LengthData Description
0 1 0x02 Generic Device Path Header - Type ACPI Device Path
1 1 0x01 Sub type - ACPI Device Path
2 2 0x0C Length - 0x0C bytes
4 4 0x41D0,
0x0A03_HID PNP0A03 - 0x41D0 represents the compressed string ‘PNP’ and is
encoded in the low order bytes. The compression method is described in
the ACPI Speciﬁcation.
8 4 0x0000 _UID
12 1 0x01 Generic Device Path Header - Type Hardware Device Path
13 1 0x01 Sub type - PCI
14 2 0x06 Length - 0x06 bytes
16 1 0x0 PCI Function
17 1 0x1F PCI Device
18 1 0x03 Generic Device Path Header - Type Message Device Path
19 1 0x15 Sub type - Fibre Channel Ex
20 2 0x14 Length - 20 bytes
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Table 10.17 – continued from previous page
21 1 0x00 8 byte array containing Fibre Channel End Device Port Name (a.k.a., World
Wide Name)
22 1 0x01
23 1 0x02
24 1 0x03
25 1 0x04
26 1 0x05
27 1 0x06
28 1 0x07
29 1 0x00 8 byte array containing Fibre Channel Logical Unit Number
30 1 0x01
31 1 0x02
32 1 0x03
33 1 0x04
34 1 0x05
35 1 0x06
36 1 0x07
37 1 0x7F Generic Device Path Header - Type End of Hardware Device Path
38 1 0xFF Sub type - End of Entire Device Path
39 2 0x04 Length - 0x04 bytes
10.3.4.4 1394 Device Path
Table 10.18: 1394 Device Path
Sub-Type 1 1 Sub-Type 4 - 1394
Length 2 2 Length of this structure in bytes. Length is 16 bytes.
GUID18 8 1394 Global Unique ID (GUID)1
Note :1The usage of the term GUID is per the 1394 speciﬁcation. This is not the same as the EFI_GUID type deﬁned
in the EFI Speciﬁcation .
10.3.4.5 USB Device Paths
Table 10.19: USB Device Paths
Sub-Type 1 1 Sub-Type 5 - USB
Length 2 2 Length of this structure in bytes. Length is 6 bytes.
USB Parent Port
Number4 1 USB Parent Port Number
Interface 5 1 USB Interface Number
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10.3.4.5.1 USB Device Path Example
USB Device Path Example shows an example device path for a USB controller on a desktop platform. This USB
Controller is connected to the port 0 of the root hub, and its interface number is 0. The USB Host Controller is a PCI
device whose PCI device number 0x1F and PCI function 0x02. So, the whole device path for this USB Controller
consists an ACPI Device Path Node, a PCI Device Path Node, a USB Device Path Node and a Device Path End
Structure. The _HID and _UID must match the ACPI table description of the PCI Root Bridge. The shorthand
PciRoot(0)/PCI(31,2)/USB(0,0).
Table 10.20: USB Device Path Examples
Byte Off-
setByte
lengthData Description
0x00 0x01 0x02 Generic Device Path Header - Type ACPI Device Path
0x01 0x01 0x01 Sub type - ACPI Device Path
0x02 0x02 0x0C Length - 0x0C bytes
0x04 0x04 0x41D0,
0x08 0x04 0x0000 _UID
0x0C 0x01 0x01 Generic Device Path Header - Type Hardware Device Path
0x0D 0x01 0x01 Sub type - PCI
0x0E 0x02 0x06 Length - 0x06 bytes
0x10 0x01 0x02 PCI Function
0x11 0x01 0x1F PCI Device
0x12 0x01 0x03 Generic Device Path Header - Type Message Device Path
0x13 0x01 0x05 Sub type - USB
0x14 0x02 0x06 Length - 0x06 bytes
0x16 0x01 0x00 Parent Hub Port Number
0x17 0x01 0x00 Controller Interface Number
0x18 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x19 0x01 0xFF Sub type - End of Entire Device Path
0x1A 0x02 0x04 Length - 0x04 bytes
Another example is a USB Controller (interface number 0) that is connected to port 3 of a USB Hub Controller
(interface number 0), and this USB Hub Controller is connected to the port 1 of the root hub. The shorthand notation
for this device path is:
PciRoot(0)/PCI(31,2)/USB(1,0)/USB(3,0).
See table (below) showing the device path for this USB Controller.
Table 10.21: Another USB Device Path Example
Byte Off-
setByte
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Table 10.21 – continued from previous page
0x16 0x01 0x01 Parent Hub Port Number
0x18 0x01 0x03 Generic Device Path Header - Type Message Device Path
0x19 0x01 0x05 Sub type - USB
0x1A 0x02 0x06 Length - 0x06 bytes
0x1C 0x01 0x03 Parent Hub Port Number
0x1D 0x01 0x00 Controller Interface Number
0x1E 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x1F 0x01 0xFF Sub type - End of Entire Device Path
0x20 0x02 0x04 Length - 0x04 bytes
10.3.4.6 SATA Device Path
Table 10.22: SATA Device Path
Sub-Type 1 1 Sub-Type 18 - SATA
Length 2 2 Length of this structure in bytes. Length is 10 bytes.
HBA Port Number 4 2 The HBA port number that facilitates the connection to
the device or a port multiplier. The value 0xFFFF is
reserved.
Port Multiplier Port Number 6 2 The Port multiplier port number that facilitates the con-
nection to the device. Must be set to 0xFFFF if the de-
vice is directly connected to the HBA.
Logical Unit Number 8 2 Logical Unit Number.
10.3.4.7 USB Device Paths (WWID)
This device path describes a USB device using its serial number.
Speciﬁcations, such as the USB Mass Storage class, bulk-only transport subclass, require that some portion of the
sufﬁx of the device’s serial number be unique with respect to the vendor and product id for the device. So, in order to
avoid confusion and overlap of WWID’s, the interface’s class, subclass, and protocol are included.
Table 10.23: USB WWID Device Path
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Table 10.23 – continued from previous page
Sub-Type 1 1 Sub-Type 16- USB WWID
Length 2 2 Length of this structure in bytes. Length is 10+
• Interface Number4 2 USB interface number
• Device Vendor Id6 2 USB vendor id of the device

• Device Product Id8 2 USB product id of the device
• Serial Number10 n Last 64-or-fewer UTF-16 characters of the USB serial
number. The length of the string is determined by the
Length ﬁeld less the offset of the Serial Number ﬁeld
(10)
Devices that do not have a serial number string must use the USB Device Path (type 5) as described in USB Device
Path Example .
Including the interface as part of this node allows distinction for multi-interface devices, e.g., an HID interface and a
Mass Storage interface on the same device, or two Mass Storage interfaces.
Load Option Processing deﬁnes special rules for processing the USB WWID Device Path. These special rules enable
a device location to change and still have the system boot from the device.
10.3.4.8 Device Logical Unit
For some classes of devices, such as USB Mass Storage, it is necessary to specify the Logical Unit Number (LUN),
since a single device may have multiple logical units. In order to boot from one of these logical units of the device,
the Device Logical Unit device node is appended to the device path. The EFI path node subtype is deﬁned, as in the
Table below.
Table 10.24: Device Logical Unit
Sub-Type 1 1 Sub-Type 17 - Device Logical unit
Length 2 2 Length of this structure in bytes. Length is 5
LUN 4 1 Logical Unit Number for the interface
Load Option Processing deﬁnes special rules for processing the USB Class Device Path. These special rules enable a
device location to change and still have the system recognize the device.
Globally Deﬁned Variables deﬁnes how the ConIn ,ConOut , and ErrOut variables are processed and contains special
rules for processing the USB Class device path. These special rules allow all USB keyboards to be speciﬁed as valid
input devices.
Table 10.25: USB Class Device Path
Type 0 1 Type 3 - Messaging Device Path.
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Table 10.25 – continued from previous page
Sub-Type 1 1 Sub-Type 15 - USB Class.
Length 2 2 Length of this structure in bytes. Length is 11 bytes.
Vendor ID 4 2 Vendor ID assigned by USB-IF. A value of 0xFFFF will match any
Vendor ID.
Product ID 6 2 Product ID assigned by USB-IF. A value of 0xFFFF will match any
Product ID.
Device Class 8 1 The class code assigned by the USB-IF. A value of 0xFF will match
any class code.
Device Subclass 9 1 The subclass code assigned by the USB-IF. A value of 0xFF will
match any subclass code.
Device Protocol 10 1 The protocol code assigned by the USB-IF. A value of 0xFF will
match any protocol code.
10.3.4.9 I 2O Device Path
Table 10.26: I 2O Device Path
Sub-Type 1 1 Sub-Type 6 - I2O Random Block Storage Class
TID 4 4 Target ID (TID) for a device
10.3.4.10 MAC Address Device Path
Table 10.27: MAC Address Device Path
Sub-Type 1 1 Sub-Type 11 - MAC Address for a network interface
Length 2 2 Length of this structure in bytes. Length is 37 bytes.
MAC Address 4 32 The MAC address for a network interface padded with 0s
IfType 36 1 Network interface type(i.e., 802.3, FDDI). See RFC 3232
10.3.4.11 IPv4 Device Path
Previous versions of the speciﬁcation only deﬁned a 19 byte IPv4 device path. To access ﬁelds at off-set 19 or greater,
the size of the device path must be checked ﬁrst.
Table 10.28: IPv4 Device Path
Sub-Type 1 1 Sub-Type 12 - IPv4
Length 2 2 Length of this structure in bytes. Length is 27 bytes.
Local IP Address 4 4 The local IPv4 address
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Table 10.28 – continued from previous page
Remote IP Address 8 4 The remote IPv4 address
Local Port 12 2 The local port number
Remote Port 14 2 The remote port number
Protocol 16 2 The network protocol(i.e., UDP, TCP). See RFC 3232
StaticIPAddress 18 1
0x00 - The Source IP Address was assigned though DHCP
0x01 - The Source IP Address is statically bound
G atewayIPAddress 19 4 The Gateway IP Address
Subnet Mask 23 4 Subnet mask
10.3.4.12 IPv6 Device Path
Table 10.29: IPv6 Device Path
Sub-Type 1 1 Sub-Type 13 - IPv6
Length 2 2 Length of this structure in bytes. Length is 60 bytes.
Local IP Address 4 16 The local IPv6 address
Remote IP Address 20 16 The remote IPv6 address
Local Port 36 2 The local port number
Remote Port 38 2 The remote port number
Protocol 40 2 The network protocol (i.e., UDP, TCP). See RFC 3232
IPAddressOrigin 42 1
0x00 - The Local IP Address was manually conﬁgured.
0x01 - The Local IP Address is assigned through IPv6 stateless
auto -conﬁguration.
0x02 - The Local IP Address is assigned through IPv6stateful
conﬁguration.
PreﬁxLength 43 1 The Preﬁx Length
GatewayIPAddress 44 16 The Gateway IP Address
10.3.4.13 2. VLAN device path node
Table 10.30: VLAN device path node
Sub-Type 1 1 Sub-Type 20 - Vlan (802.1q)
Length 2 2 Length of this device node
Vlanid 4 2 VLAN identiﬁer (0-4094)
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10.3.4.14 InﬁniBand Device Path
Table 10.31: InﬁniBand Device Path
Sub-Type 1 1 Sub-Type 9 - InﬁniBand
Length 2 2 Length of this structure in bytes. Length is 48 bytes.
Resource Flags 4 4
Flags to help identify/manage InﬁniBand device path
elements:
• Bit 0: IOC/Service (0b = IOC, 1b = Service)
• Bit 1: Extend Boot Environment
• Bit 2: Console Protocol
• Bit 3: Storage Protocol
• Bit 4: Network Protocol
All other bits are reserved.
PORT GID 8 16 128-bit Global Identiﬁer for remote fabric port
IOC GUID/Service ID 24 8 64-bit unique identiﬁer to remote IOC or server process.
Interpretation of ﬁeld speciﬁed by Resource Flags (bit
0)
Target Port ID 32 8 64-bit persistent ID of remote IOC port
Device ID 40 8 64-bit persistent ID of remote device
Note :The usage of the terms GUID and GID is per the InﬁniBand Speciﬁcation. The term GUID is not the same as
theEFI_GUID type deﬁned in this EFI Speciﬁcation .
10.3.4.15 UART Device Path
Table 10.32: UART Device Path
Type 0 1 Type 3 – Messaging Device Path
Sub-Type 1 1 Sub-Type 14 – UART
Length 2 2 Length of this structure in bytes. Length is 19 bytes.
Baud Rate 8 8 The baud rate setting for the UART style device. A value of 0 means
that the device’s default baud rate will be used.
Data Bits 16 1 The number of data bits for the UART style device. A value of 0
means that the device’s default number of data bits will be used.
10.3. Device Path Nodes 267Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 10.32 – continued from previous page
Parity 17 1
The parity setting for the UART style device.
Parity 0x00 - Default Parity
Parity 0x01 - No Parity
Parity 0x02 - Even Parity
Parity 0x03 - Odd Parity
Parity 0x04 - Mark Parity
Parity 0x05 - Space Parity
Stop Bits 18 1
The number of stop bits for the UART style device.
Stop Bits 0x00 - Default Stop Bits
Stop Bits 0x01 - 1 Stop Bit
Stop Bits 0x02 - 1.5 Stop Bits
Stop Bits 0x03 - 2 Stop Bits
10.3.4.16 Vendor-Deﬁned Messaging Device Path
Table 10.33: Vendor-Deﬁned Messaging Device Path
Sub-Type 1 1 Sub-Type 10 - Vendor
Vendor GUID 4 16 Vendor-assigned GUID that deﬁnes the data that follows
Vendor Deﬁned Data 20 n Vendor-deﬁned variable size data
The following GUIDs are used with a Vendor-Deﬁned Messaging Device Path to describe the transport protocol for
use with PC-ANSI, VT-100, VT-100+, and VT-UTF8 terminals. Device paths can be constructed with this node as the
last node in the device path. The rest of the device path describes the physical device that is being used to transmit and
receive data. The PC-ANSI, VT-100, VT-100+, and VT-UTF8 GUIDs deﬁne the format of the data that is being sent
though the physical device. Additional GUIDs can be generated to describe additional transport protocols.
#define EFI_PC_ANSI_GUID\
{0xe0c14753,0xf9be,0x11d2,{0x9a,0x0c,0x00,0x90,0x27,0x3f,0xc1,0x4d}}
#define EFI_VT_100_GUID\
{0xdfa66065,0xb419,0x11d3,{0x9a,0x2d,0x00,0x90,0x27,0x3f,0xc1,0x4d}}
#define EFI_VT_100_PLUS_GUID\
{0x7baec70b,0x57e0,0x4c76,{0x8e,0x87,0x2f,0x9e,0x28,0x08,0x83,0x43}}
#define EFI_VT_UTF8_GUID\

{0xad15a0d6,0x8bec,0x4acf,{0xa0,0x73,0xd0,0x1d,0xe7,0x7e,0x2d,0x88}}
10.3. Device Path Nodes 268Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.4.17 UART Flow Control Messaging Path
The UART messaging device path deﬁned in the EFI 1.02 speciﬁcation does not contain a provision for ﬂow control.
Therefore, a new device path node is needed to declare ﬂow control characteristics. It is a vendor-deﬁned messaging
node which may be appended to the UART node in a device path. It has the following deﬁnition:
#define DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL \
{0x37499a9d,0x542f,0x4c89,{0xa0,0x26,0x35,0xda,0x14,0x20,0x94,0xe4}}
Table 10.34: UART Flow Control Messaging Device Path
Vendor GUID 4 16 DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL
Flow_Control_Map 20 4
Bitmap of supported ﬂow control types.
• Bit 0 set indicates hardware ﬂow control.
• Bit 1 set indicates Xon/Xoff ﬂow control.
• All other bits are reserved and are clear.
A debugport driver that implements Xon/Xoff ﬂow control would produce a device path similar to the following:
PciRoot(0)/Pci(0x1f,0)/ACPI(PNP0501,0)/UART(115200,N,8,1)/UartFlowCtrl(2)/DebugPort()
Note : If no bits are set in the Flow_Control_Map, this indicates there is no ﬂow control and is equivalent to leaving
the ﬂow control node out of the device path completely.
10.3.4.18 Serial Attached SCSI (SAS) Device Path
This section deﬁnes the device node for Serial Attached SCSI (SAS) devices.
Table 10.35: SAS Messaging Device Path Structure
Type 0 1 Type -3 Messaging
Sub Type 1 1 10 ( Vendor)
Length 2 2 Length of this Structure.
Vendor GUID 4 16 d487dd b4-008b-11d9-af dc-001083ffca4d
Reserved 20 4 Reserved for future use.
SAS Address 24 8 SAS Address for Serial Attached SCSI Target.
Logical Unit Number 32 8 SAS Logical Unit Number.
SAS/SATA device and Topology
Info40 2 More Information about the device and its interconnect
Relative Target Port 42 2 Relative Target Port (RTP)
Summary
The device node represented by the structure in the table above shall be appended after the Hardware Device Path
10.3. Device Path Nodes 269Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
node in the device path.
There are two cases for boot devices connected with SAS HBA’s. Each of the cases is described below with an example
of the expected Device Path for these.
• SAS Device anywhere in an SAS domain accessed through SSP Protocol.
PciRoot(0)/PCI(1,0)/Sas(0x31000004CF13F6BD, 0)
The ﬁrst 64-bit number represents the SAS address of the target SAS device.
The second number is the boot LUN of the target SAS device.
The third number is the Relative Target Port (RTP)
• SATA Device connected directly to a HBA port.
PciRoot(0)/PCI(1,0)/Sas(0x31000004CF13F6BD)
The ﬁrst number represents either a real SAS address reserved by the HBA for above connections, or a fake but unique
SAS address generated by the HBA to represent the SATA device.
10.3.4.18.1 Device and Topology Information
First Byte (At offset 40 into the structure):
Bits 0:3:
Value 0x0 -> No Additional Information about device topology.
Value 0x1 -> More Information about device topology valid in this byte.
Value 0x2 -> More Information about device topology valid in this and next 1 byte.
Values 0x3 thru 0xF -> Reserved.
Bits 4:5: Device Type ( Valid only if the More Information ﬁeld above is non-zero)
Value 0x0 -> SAS Internal Device
Value 0x1 -> SATA Internal Device
Value 0x2 -> SAS External Device
Value 0x3 -> SATA External Device
Bits 6:7: Topology / Interconnect (Valid only if the More Information ﬁeld above is non-zero)
Value 0x0 -> Direct Connect (Connected directly with the HBA Port/Phy)
Value 0x1 -> Expander Connect (Connected thru/via one or more Expanders)
Value 0x2 and 0x3 > Reserved
10.3. Device Path Nodes 270Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.4.18.2 Device and Topology Information
Second Byte (At offset 41 into the structure). Valid only if bits 0-3 of More Information in Byte 40 have a value of 2:
Bits 0-7: Internal Drive/Bay Id (Only applicable if Internal Drive is indicated in Device Type)
Value 0x0 thru 0xFF -> Drive 1 thru Drive 256
10.3.4.18.3 Relative Target Port
At offset 42 into the structure:
This two-byte ﬁeld shall contain the “Relative Target Port” of the target SAS port. Relative Target Port can be obtained
by performing an INQUIRY command to VPD page 0x83 in the target. Implementation of RTP is mandatory for SAS
targets as deﬁned in Section 10.2.10 of sas1r07 speciﬁcation (or later).
NOTE :If a LUN is seen thru multiple RTPs in a given target, then the UEFI driver shall create separate device path
instances for both paths. RTP in the device path shall distinguish these two device path instantiations .
NOTE :Changing the values of the SAS/SATA device topology information or the RTP ﬁelds of the device path will
make UEFI think this is a different device .
10.3.4.18.4 Examples Of Correct Device Path Display Format
Case 1: When Additional Information is not Valid or Not Present (Bits 0:3 of Byte 40 have a value of 0)
PciRoot(0)/PCI(1,0)/SAS(0x31000004CF13F6BD, 0)
Case 2: When Additional Information is Valid and present (Bits 0:3 of Byte 40 have a value of 1 or 2)
• If Bits 4-5 of Byte 40 (Device and Topology information) indicate an SAS device (Internal or External) i.e., has
values 0x0 or 0x2, then the following format shall be used.
PciRoot(0)/PCI(1,0)/SAS(0x31000004CF13F6BD, 0, SAS)
• If Bits 4-5 of Byte 40 (Device and Topology information) indicate a SATA device (Internal or External) i.e., has
a value of 0x1 or 0x3, then the following format shall be used.
ACPI(PnP)/PCI(1,0)/SAS(0x31000004CF13F6BD, SATA)
10.3.4.19 Serial Attached SCSI (SAS) Extended Device Path
This section deﬁnes the extended device node for Serial Attached SCSI (SAS) devices. In this device path the SAS
Address and LUN are now deﬁned as arrays to remove the need to endian swap the values.
Table 10.36: SAS Extended Messaging Device Path Structure
Sub Type 1 1 Sub-type 22 SAS Ex
Length 2 2 Length of this Structure. 32 bytes
SAS Address 4 8 8-byte array of the SAS Address for Serial Attached
SCSI Target Port.
10.3. Device Path Nodes 271Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 10.36 – continued from previous page
Logical Unit Number 20 8 8-byte array of the SAS Logical Unit Number.
Info28 2 More Information about the device and its interconnect
Relative Target Port 30 2 Relative Target Port (RTP)
The SAS Ex device path clariﬁes the deﬁnition of the Logical Unit Number ﬁeld to conform with the T-10 SCSI
Architecture Model 4 speciﬁcation. The 8 byte Logical Unit Number ﬁeld in the device path must conform with a
logical unit number returned by a SCSI REPORT LUNS command.
When the SAS Device Path Ex is used with the Extended SCSI Pass Thru Protocol, the UINT64 LUN must be
converted to the eight byte array Logical Unit Number ﬁeld in the device path by treating the eight byte array
as an EFI UINT64. For example, a Logical Unit Number array of { 0,1,2,3,4,5,6,7 } becomes a UINT64 of
When an application client displays or otherwise makes a 64-bit LUN (8 byte array) visible to a user, it should be done
in conformance with SAM-4. SAM-4 requires a LUN to be displayed in hexadecimal format with byte 0 ﬁrst (i.e., on
the left) and byte 7 last (i.e., on the right) regardless of the internal representation of the LUN. UEFI deﬁnes all data
structures a “little endian” and SCSI deﬁnes all data structures as “big endian”.
10.3.4.20 iSCSI Device Path
Table 10.37: iSCSI Device Path Node (Base Information)
Sub-Type 1 1 Sub-Type 19 - (iSCSI)
Length 2 2 Length of this structure in bytes. Length is (18 + n) bytes
Protocol 4 2 Network Protocol (0 = TCP, 1+ = reserved)
Options 6 2 iSCSI Login Options
ber8 8 8 byte array containing the iSCSI Logical Unit Number
Target Portal group
tag16 2 iSCSI Target Portal group tag the initiator intends to establish a ses-
sion with.
iSCSI Target Name 18 n iSCSI NodeTarget Name. The length of the name is determined by
subtracting the offset of this ﬁeld from Length.
10.3.4.20.1 iSCSI Login Options
The iSCSI Device Node Options describe the iSCSI login options for the key values:
Bits 0:1:
0 = No Header Digest
2 = Header Digest Using CRC32C
Bits 2-3:
0 = No Data Digest
2 = Data Digest Using CRC32C
Bits 4-9:
10.3. Device Path Nodes 272Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Reserved for future use
Bits 10-11:
0 = AuthMethod_CHAP
2 = AuthMethod_None
Bit 12:
0 = CHAP_BI
1 = CHAP_UNI

sion with.
Bits 0:1:
Bits 2-3:
Bits 4-9:
Bit 12:
0 = CHAP_BI
For each speciﬁc login key, none, some or all of the deﬁned values may be conﬁgured. If none of the options are
deﬁned for a speciﬁc key, the iSCSI driver shall propose “None” as the value. If more than one option is conﬁgured
for a speciﬁc key, all the conﬁgured values will be proposed (ordering of the values is implementation dependent).
• Portal Group Tag: deﬁnes the iSCSI portal group the initiator intends to establish Session with.
• Logical Unit Number: deﬁnes the 8 byte SCSI LUN. The Logical Unit Number ﬁeld must conform to the T-10
SCSI Architecture Model 4 speciﬁcation. The 8 byte Logical Unit Number ﬁeld in the device path must conform
with a logical unit number returned by a SCSI REPORT LUNS command.
• iSCSI Target Name: deﬁnes the iSCSI Target Name for the iSCSI Node. The size of the iSCSI Target Name can
be up to a maximum of 223 bytes.
10.3.4.20.2 Device Path Examples
Some examples for the Device Path for the case the boot device connected to iSCSI bootable controller:
• With IPv4 conﬁguration:
PciRoot(0)/Pci(19|0)/Mac( 001320F5FA77,0x01)/
IPv4(192.168.0.100,TCP,Static,192.168.0.1)/ iSCSI(iqn.1991-
05.com.microsoft:iscsitarget-iscsidisk-target,0x1,0x0, None,None,None,TCP)/
HD(1,GPT,15E39A00-1DD2-1000-8D7F-00A0C92408FC,0x22,0x2710000)
Table 10.38: IPv4 conﬁguration
Byte
0x00 1 0x02 Generic Device Path Header - Type ACPI Device Path
0x01 1 0x01 Sub type - ACPI Device Path
0x02 2 0x0C Length - 0x0C bytes
0x04 4
0x41D0,
0x0A03_HID PNP0A03 - 0x41D0 represents the compressed
string ‘PNP’ and is encoded in the low order bytes. The
compression method is described in the ACPI Speciﬁ-
cation.
0x08 4 0x0000 _UID
0x0C 1 0x01 Generic Device Path Header - Type Hardware Device
Path
0x0D 1 0x01 Sub type - PCI
0x0E 2 0x06 Length - 0x06 bytes
0x10 1 0x0 PCI Function
0x11 1 0x19 PCI Device
0x12 1 0x03 Generic Device Path Header - Messaging Device Path
10.3. Device Path Nodes 273Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 10.38 – continued from previous page
0x13 1 0x0B Sub type - MAC Address Device path
0x14 2 0x25 Length - 0x25
0x16 32
0x00, 0x13, 0x20, 0xF5,
0xFA, 0x77,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00MAC address for a network interface padded with zeros
0x36 1 0x01 Network Interface Type - other
0x37 1 0x03 Generic Device Path Header - Messaging Device Path
0x38 1 0x0c Sub type - IPv4
0x39 2 0x1B Length - 27
0x3b 4 0xC0, 0xA8, 0x00, 0x01 Local IPv4 address - 192.168.0.1
0x3F 4 0xC0, 0xA8, 0x00, 0x64 Remote IPv4 address - 192.168.0.100
0x43 2 0x0000 Local Port Number - 0
0x45 2 0x0CBC Remote Port Number - 3260
0x47 2 0x6 Network Protocol. See RFC 3232. TCP
0x49 1 1 Static IP Address
0x4A 4 Gateway IP Address
0x4E 4 Subnet mask
0x52 1 0x03 Generic Device Path Header - Messaging Device Path
0x53 1 0x13 Sub type - iSCSI
0x54 2 0x49 Length - 0x49
10.3. Device Path Nodes 274Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
0x56 2 0x00 Network Protocol
0x58 2 0x800 iSCSI Login Options - AuthMethod_None
0x5A 8
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00iSCSI LUN
0x62 2 0x01 Target Portal group tag
0x64 55 0x69, 0x71, 0x6E, 0x2E,
0x31, 0x39, 0x39, 0x31,
0x2D, 0x30, 0x35, 0x2E,
0x63, 0x6F, 0x6D, 0x2E,
0x6D, 0x69, 0x63, 0x72,
0x6F, 0x73, 0x6F, 0x66,
0x74,iSCSI node name.
0x64
(cont.)55 (cont.) 0x3A, 0x69, 0x73, 0x63,
0x73, 0x69, 0x74, 0x61,
0x72, 0x67, 0x65, 0x74,
0x2D, 0x69, 0x73, 0x63,
0x73, 0x69, 0x64, 0x69,
0x73, 0x6B, 0x2D, 0x74,
0x61, 0x72, 0x67, 0x65,
0x74, 0x00iSCSI node name (cont.)
0x9B 1 0x04 Generic Device Path Header - Media Device Path
0x9C 1 0x01 Sub type - Hard Drive
0x9D 2 0x2A Length - 0x2a
0x9F 4 0x1 Partition Number
0xA3 8 0x22 Partition Start
0xAB 8 0x2710000 Partition Size
10.3. Device Path Nodes 275Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
0xB3 16
0x00,
0x9A,
0xE3,
0x15,
0xD2,
0x1D,
0x00,
0x10,
0x8D,
0x7F,
0x00,
0xA0,
0xC9,
0x24, 0x08, xFCPartition Signature
0xC3 1 0x02 Partition Format - GPT
0xC4 1 0x02 Signature Type - GUID
0xC5 1 0x7F Generic Device Path Header - Type End of Hardware
Device Path
0xC6 1 0xFF Sub type - End of Entire Device Path
0xC7 2 0x04 Length - 0x04 bytes
• With IPv6 conﬁguration:
PciRoot(0x0)/Pci(0x1C,0x2)/Pci(0x0,0x0)/MAC(001517215593,0x0)/
IPv6(2001:4898:000A:1005:95A6:EE6C:BED3:4859,TCPDHCP,2001:4898:000A:1005:0215
:17FF:FE21:5593)/iSCSI(iqn.1991-05.com.microsoft:iscsiipv6-ipv6test-
target,0x1,0x0, None,None,None,TCP)/HD(1,MBR,0xA0021243,0x800,0x2EE000)
Table 10.39: IPv6 conﬁguration
Byte
0x04 4 0x41D0, 0x0A03 _HID PNP0A03 - 0x41D0 represents the compressed string ‘PNP’
and is encoded in the low order bytes. The compression method is
described in the ACPI Speciﬁcation.
0x0C 1 0x01 Generic Device Path Header - Type Hardware Device Path
0x10 1 0x02 PCI Function
0x11 1 0x1C PCI Device
0x12 1 0x01 Generic Device Path Header - Type Hardware Device Path
0x13 1 0x01 Sub type - PCI
0x14 2 0x06 Length - 0x06 bytes
0x16 1 0x00 PCI Function
10.3. Device Path Nodes 276Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 10.39 – continued from previous page
0x17 1 0x00 PCI Device
0x18 1 0x03 Generic Device Path Header - Messaging Device Path
0x19 1 0x0B Sub type - MAC Address Device path
0x1A 2 0x25 Length - 0x25
0x1C 32
0x00, 0x15,
0x17, 0x21,
0x55, 0x93,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x3C 1 0x01 Network Interface Type - other
0x3D 1 0x03 Generic Device Path Header - Messaging Device Path
0x3E 1 0x0C Sub type - IPv6
0x3F 2 0x3C Length - 0x3C
10.3. Device Path Nodes 277Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
0x41 16
0x20, 0x01,
0x48, 0x98,
0x00, 0x0A,
0x10, 0x05,
0x02, 0x15,
0x17, 0xFF, 0xFE,
0x21, 0x55, 0x93Local IPv6 address - 2001:4898 :000A:1005:0215
:17FF:FE21:5593
0x51 16
0x95, 0xA6,
0xEE, 0x6C,
0xBE, 0xD3,
0x48, 0x59Remote IPv6 address - 2001:4898 :000A:1005:95A6
:EE6C:BED3:4859
0x61 2 0x0000 Local Port Number - 0
0x63 2 0x0CBC Remote Port Number - 3260
0x65 2 0x6 Network Protocol. See RFC 3232. TCP
0x66 1 1 IP Address Origin
0x67 1 The Preﬁx Length
0x68 16 The Gateway IP Address
0x78 1 0x03 Generic Device Path Header - Messaging Device Path
0x79 1 0x13 Sub type - iSCSI
0x7A 2 0x46 Length - 0x46
0x7C 2 0x00 Network Protocol
0x7E 2 0x800 iSCSI Login Options - AuthMethod_None
0x81 8
0x00
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x89 2 0x01 Target Portal group tag
10.3. Device Path Nodes 278Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
0x8B 52
0x69, 0x71,
0x6E, 0x2E,
0x31, 0x39,
0x39, 0x31,
0x2D, 0x30,
0x35, 0x2E,
0x63, 0x6F,
0x6D, 0x2E,
0x6D, 0x69,
0x63, 0x72,
0x6F, 0x73,
0x6F, 0x66,
0x74, 0x3A,
0x69, 0x73,
0x63, 0x73,
0x69, 0x69,
0x70, 0x76,iSCSI node name.
0x8B
(cont.)52
(cont.) 0x36, 0x2D,
0x69, 0x70,
0x76, 0x36,
0x74, 0x65,
0x73, 0x74,
0x2D, 0x74,
0x61, 0x72,
0x67, 0x65,
0xBF 1 0x04 Generic Device Path Header - Media Device Path
0xC0 1 0x01 Sub type - Hard Drive
0xC1 2 0x2A Length - 0x2a
0xC3 4 0x1 Partition Number
0xC7 8 0x800 Partition Start
0xCF 8 0x2EE000 Partition Size
10.3. Device Path Nodes 279Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
0xDF 16
0x43, 0x12,
0x02, 0xA0,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00Partition Signature
0xEF 1 0x01 Partition Format - MBR
0xF0 1 0x01 Signature Type - 32bit signature
0xF1 1 0x7F Generic Device Path Header - Type End of Hardware Device Path
0xF2 1 0xFF Sub type - End of Entire Device Path
0xF3 2 0x04 Length - 0x04 bytes
10.3.4.21 NVM Express namespace messaging device path node
Table 10.40: NVM Express Namespace Device Path
Sub-Type 1 1 Sub Type 23 - NVM Express Namespace
Namespace Identi-
ﬁer4 4 Namespace identiﬁer (NSID). The values of 0 and 0xFFFFFFFF are
invalid.
IEEE Extended
Unique Identiﬁer8 8 This ﬁeld contains the IEEE Extended Unique Identiﬁer (EUI-64).

0xDF 16
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
invalid.
Devices without an EUI-64 value must initialize this ﬁeld with a
value of 0.
Refer to the latest NVM Express® Base Speciﬁcation for descriptions of Namespace Identiﬁer (NSID) and IEEE
Extended Unique Identiﬁer (EUI-64): See “Links to UEFI-Related Documents” (http://www.nvmexpress.org/index)
under the heading “NVM Express® Speciﬁcations”.
Note: When an application client displays or otherwise makes the EUI-64 identiﬁers visible to a user, the values
should be displayed in hexadecimal format with byte 7 ﬁrst (i.e., on the left) and byte 0 last (i.e., on the right) regardless
of the internal representation of the EUI-64.
10.3. Device Path Nodes 280Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.4.22 Uniform Resource Identiﬁers (URI) Device Path
Refer to RFC 3986 for details on the URI contents.
Table 10.41: URI Device Path
Sub-Type 1 1 Sub Type 24 - Universal Resource Identiﬁer (URI) De-
vice Path
Length 2 2 Length of this structure in bytes. Length is 4 + n bytes.
. . . 4 n Instance of the URI pursuant to RFC 3986. For an
empty URI, Length is 4 bytes.
10.3.4.23 UFS (Universal Flash Storage) device messaging devicepath node
Table 10.42: UFS Device Path
Sub-Type 1 1 Sub-Type 25 - UFS
Target ID 4 1 Target ID on the UFS interface (PUN).
LUN 5 1 Logical Unit Number (LUN).
Refer to the UFS 2.0 speciﬁcation for additional LUN descriptions: See “Links to UEFI-Related Documents” ( http:
//ueﬁ.org/ueﬁ ) under the heading “UFS 2.0 Speciﬁcation”.
•PUN ﬁeld : According to current available UFS 2.0 spec, the topology is one device per UFS port. A topology
to support multiple devices on a single interface is planned for future revision. So suggest to reserve/introduce
this ﬁeld to support multiple devices per UFS port. This value should be 0 for current UFS2.0 spec compliance.
•LUN ﬁeld : This ﬁeld is used to specify up to 8 normal LUNs(0-7) and 4 well-known LUNs(81h, D0h, B0h and
C4h). For those well-known LUNs, the BIT7 is set. See Figure 10.2 of UFS 2.0 spec for details.
10.3.4.24 SD (Secure Digital) Device Path
Table 10.43: SD Device Path
Sub-Type 1 1 Sub-Type 26 - SD
Slot Number 4 1 Slot Number
10.3. Device Path Nodes 281Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.4.25 EFI Bluetooth Device Path
Table 10.44: EFI Bluetooth Device Path
Sub-Type 1 1 Sub-Type 27 - Bluetooth
Bluetooth
Device Address4 6 48-bit Bluetooth device address.
10.3.4.26 Wireless Device Path
Table 10.45: Wi-Fi Device Path
Sub-Type 1 1 Sub Type 28 - Wi-Fi Device Path
Length 2 2 Length of this structure in bytes. Length is 36 bytes.
SSID 4 32 SSID in octet string
10.3.4.27 eMMC (Embedded Multi-Media Card) Device Path
Table 10.46: eMMC Device Path
Sub-Type 1 1 Sub-Type 29 - eMMC
10.3.4.28 EFI BluetoothLE Device Path
Table 10.47: EFI BluetoothLE Device Path
Sub-Type 1 1 Sub-Type 30 - BluetoothLE
Length 2 2 Length of this structure in bytes. Length is 11
bytes.
Bluetooth Device Address 4 6 48-bit Bluetooth device address
Address Type 10 1
0x00 - Public Device Address |
0x01 - Random Device Address
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10.3.4.29 DNS Device Path
Table 10.48: DNS Device Path
Sub-Type 1 1 Sub-Type 31 - DNS Device Path
Length 2 2 Length of this structure in bytes. Length is 5 + n bytes.
IsIPv6 4 1 0x00 - The DNS server address is IPv4 address. 0x01 -
The DNS server address is IPv6 address.
. . . 5 n One or more instances of the DNS server address in
EFI_IP_ADDRESS.
10.3.4.30 NVDIMM Namespace path
This device path describes a bootable NVDIMM namespace that is deﬁned by a namespace label. The presence of this
type of device path indicates that UEFI supports booting to the namespace including any address abstraction speciﬁed
by the namespace label. Refer to the NVDIMM Label Protocol section to retrieve relevant details about the namespace.
Table 10.49: NVDIMM Namespace Device Path
Type 0 1 Type 3 - Messaging Device
Sub-Type 1 1 Sub-type 32 - NVDIMM Namespace
Length 2 2 20 - Single namespace UUID is supported.
Uuid 4 16 Namespace unique label identiﬁer UUID. See the Uuid
description in the NVDIMM Label Protocol - Label def-
initions section for details on this ﬁeld.
10.3.4.31 REST Service Device Path
Table 10.50: REST Service Device Path
Type 0 1 Type 0x03 - Messaging Device Path
Sub-Type 1 1 Sub-Type 33- REST Service Device Path
REST Service 4 1 0x01 = Redﬁsh REST Service - 0x02 = OData REST
Service
Access Mode 5 1 (0x01) In-Band REST Service, - (0x02) Out-of-band
REST Service.
Device path example of Out-of-band Redﬁsh REST Service through NIC:
PciRoot(0x2)/Pci(0x2,0x0)/Pci(0x0,0x0)/MAC(FD19FA100672,0x0)/
IPv4(0.0.0.0,0x0,DHCP,0.0.0.0,0.0.0.0,0.0.0.0)/RestService(1,2)
10.3. Device Path Nodes 283Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 10.51: Vendor-Speciﬁc REST Service Device Path
Length 2 2 Length of this structure in bytes. Length is 21 + n bytes.
REST Service 4 1 0xFF = Vendor speciﬁc REST Service
Access Mode 5 1 (0x01) In-Band REST Service, (0x02) Out-of-band
Vendor speciﬁc REST service
GUID6 16 GUID of vendor speciﬁc REST service.
Vendor deﬁned data 22 n Vendor-deﬁned data.
Device path example of In-band vendor-speciﬁc REST Service through BMC:
PciRoot(0x2)/Pci(0x2,0x0)/Pci(0x0,0x0)/BMC(0,0xf0000000)/RestService(0xff, 1,
00000000-0000-0000-0000000000000000,0,0)
10.3.4.32 NVMe over Fabric (NVMe-oF) Namespace Device Path
This device path describes a bootable NVMe-oF™ namespace that is deﬁned by a unique Namespace and Subsystem
NQN identity.
Table 10.52: NVMe over Fabric (NVMe-oF) Namespace Device Path
Type 00 1 Type 3 – Messaging Device Path
Sub-Type 01 1 Sub-Type 34 - NVMe-oF Namespace Device Path
Length 02 2 Length of this Structure in bytes. Length is 20+n bytes where n is the
length of the SubsystemNQN
NIDT 04 1 Namespace Identiﬁer Type (NIDT), for globally unique type values de-
ﬁned in the CNS 03h NIDT ﬁeld (1h, 2h, or 3h) by the NVM Express®
Base Speciﬁcation®.
NID 05 16 Namespace Identiﬁer (NID), a globally unique val-ue deﬁned in the
Namespace Identiﬁcation De-scriptor list (CNS 03h) by the NVM Ex-
press® Base Speciﬁcation in big endian format.
SubsystemNQN 21 n Unique identiﬁer of an NVM subsystem stored as a null-terminated UTF-
8 string of n-bytes in compli-ance with the NVMe Qualiﬁed Name in the
NVM Express® Base Speciﬁcation. Subsystem NQN is used for purposes
of identiﬁcation and authentica-tion. Maximum length of 224 bytes.
Refer to the latest NVM Express® Base Speciﬁcation for descriptions of Subsystem NQN and Namespace Identiﬁer:
See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “NVM Express® Speciﬁcations.””
10.3. Device Path Nodes 284Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.4.33 NVMe over Fabric (NVMe-oF) Namespace Device Path Example
Device path example of NVMe-oF connection to a NVM Subsystem with IPv4 conﬁguration and NSUUID (RFC
4122) as NID:
PciRoot(0)/Pci(19|0)/Mac(001320F5FA77,0x01)/IPv4(192.168.0.100,TCP,Static,192.168.0.
˓→1)/
NVMEoF(nqn.1991-05.org.uefi:nvmeoftarget-nvmeofdisk-target,urn:uuid:4eff7f8e-d353-
˓→4e9b-a4ec-deea8eab84d7)/
Table 10.53: NVMe over Fabric (NVMe-oF) Namespace Device Path
Example
Byte
0x00 1 0x02 Generic Device Path Header – Type ACPI Device Path
0x01 1 0x01 Sub-Type – ACPI Device Path
0x02 2 0x0C Length – 12 bytes
0x04 4 0x41D0, 0x0A03 _HID PNP0A03 – 0x41D0 represents the compressed string ‘PNP’

˓→1)/
Example
Byte
0x0C 1 0x01 Generic Device Path Header – Type Hardware Device Path
0x0D 1 0x01 Sub-Type – PCI
0x0E 2 0x06 Length – 6 bytes
0x10 1 0x00 PCI Function
0x12 1 0x03 Generic Device Path Header – Messaging Device Path
0x13 1 0x0B Sub-Type – MAC Address Device path
0x14 2 0x25 Length – 37 bytes
0x16 32 0x00, 0x13, 0x20,
0xF5, 0xFA, 0x77,
0x00, 0x00, 0x00,
0x00, 0x00MAC address for a network interface padded with zeros
0x37 1 0x03 Generic Device Path Header – Messaging Device Path
0x38 1 0x0C Sub-Type – IPv4
0x39 2 0x1B Length – 27 bytes
0x3b 4 0xC0, 0xA8, 0x00,
0x01Local IPv4 address – 192.168.0.1
0x3F 4 0xC0, 0xA8, 0x00,
0x64Remote IPv4 address – 192.168.0.100
0x43 2 0x0000 Local Port Number – 0
0x45 2 0x0CBC Remote Port Number – 3260
0x47 2 0x06 Network Protocol. See RFC 3232. TCP
10.3. Device Path Nodes 285Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 10.53 – continued from previous page
0x52 1 0x03 Generic Device Path Header – Messaging Device Path
0x53 1 0x34 Sub-Type 34 - NVMe-oF Device Path
0x54 2 0x48 Length – 72 bytes
0x56 1 0x03 Namespace Identiﬁer Type (NIDT) – 03h – Namespace UUID
0x57 16 0x4E, 0xFF, 0x7F,
0x8E, 0xD3, 0x53,
0x4E, 0x9B, 0xA4,
0xEC, 0xDE, 0xEA,
0x8E, 0xAB, 0x84,
0xD7Namespace Identiﬁer (NID) - as per RFC 4122
0x67 52 0x6E, 0x71, 0x6E,
0x2E, 0x31, 0x39,
0x39, 0x31, 0x2D,
0x30, 0x35, 0x2E,
0x6F, 0x72, 0x67,
0x2E, 0x75, 0x65,
0x66, 0x69, 0x3A,
0x6E, 0x76, 0x6D,
0x65, 0x6F, 0x66,
0x74, 0x61, 0x72,
0x67, 0x65, 0x74,
0x2D, 0x6E, 0x76,
0x6D, 0x65, 0x6F,
0x66, 0x64, 0x69,
0x73, 0x6B, 0x2D,
0x00SubsystemNQN
0x9B 1 0x04 Generic Device Path Header – Media Device Path
0x9C 1 0x01 Sub-Type – Hard Drive
0x9D 2 0x2A Length – 42 bytes
0x9F 4 0x01 Partition Number
0xB3 16 0x00, 0x9A, 0xE3,
0x15, 0xD2, 0x1D,
0x00, 0x10, 0x8D,
0x7F, 0x00, 0xA0,
0xC9, 0x24, 0x08,
0xFCPartition Signature
0xC3 1 0x02 Partition Format – GPT
0xC4 1 0x02 Signature Type – GUID
0xC5 1 0xFF Generic Device Path Header – End of Hardware Device Path
0xC6 1 0xFF Sub-Type – End of Entire Device Path
0xC7 2 0x04 Length – 4 bytes
10.3. Device Path Nodes 286Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.5 Media Device Path
This Device Path is used to describe the portion of the medium that is being abstracted by a boot service. An example
of Media Device Path would be deﬁning which partition on a hard drive was being used.
10.3.5.1 Hard Drive
The Hard Drive Media Device Path is used to represent a partition on a hard drive. Each partition has at least Hard
Drive Device Path node, each describing an entry in a partition table. EFI supports MBR and GPT partitioning
formats. Partitions are numbered according to their entry in their respective partition table, starting with 1. Partitions
are addressed in EFI starting at LBA zero. A partition number of zero can be used to represent the raw hard drive or a
raw extended partition
The partition format is stored in the Device Path to allow new partition formats to be supported in the future. The Hard
Drive Device Path also contains a Disk Signature and a Disk Signature Type. The disk signature is maintained by the
OS and only used by EFI to partition Device Path nodes. The disk signature enables the OS to ﬁnd disks even after
they have been physically moved in a system.
Load Option Processing deﬁnes special rules for processing the Hard Drive Media Device Path. These special rules
enable a disk’s location to change and still have the system boot from the disk.
Table 10.54: Hard Drive Media Device Path
Type 0 1 Type 4 — Media Device Path
Sub-Type 1 1 Sub-Type 1 — Hard Drive
Length 2 2 Length of this structure in bytes. Length is 42 bytes.
Partition Number 4 4 Describes the entry in a partition table, starting with entry 1. Parti-
tion number zero represents the entire device. Valid partition num-
bers for a MBR partition are [1, 4]. Valid partition numbers for a
GPT partition are [1, NumberOfPar titionEntries].
Partition Start 8 8 Starting LBA of the partition on the hard drive
Partition Size 16 8 Size of the partition in units of Logical Blocks
Partition Signature 24 16 Signature unique to this partition: If SignatureType is 0, this ﬁeld
has to be initialized with 16 zeroes. If SignatureType is 1, the MBR
signature is stored in the ﬁrst 4 bytes of this ﬁeld. The other 12 bytes
are initialized with zeroes. If SignatureType is 2, this ﬁeld contains
a 16 byte signature.
Partition Format 40 1 Partition Format: (Unused values reserved) 0x01 - PC-AT compat-
ible legacy MBR ( Legacy MBR ) . Partition Start and Partition Size
come from Parti tionStartingLBA andPartitionSizeInLBA for the
partition.0x02—GUID Partition Table
Signature Type 41 1 Type of Disk Signature: (Unused values reserved) 0x00 - No Disk
Signature. 0x01 - 32-bit signature from address 0x1b8 of the type
0x01 MBR. 0x02 - GUID signature.
10.3. Device Path Nodes 287Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.5.2 CD-ROM Media Device Path
The CD-ROM Media Device Path is used to deﬁne a system partition that exists on a CD-ROM. The CD-ROM is
assumed to contain an ISO-9660 ﬁle system and follow the CD-ROM “El Torito” format. The Boot Entry number
from the Boot Catalog is how the “El Torito” speciﬁcation deﬁnes the existence of bootable entities on a CD-ROM. In
EFI the bootable entity is an EFI System Partition that is pointed to by the Boot Entry.
Table 10.55: CD-ROM Media Device Path
Type 0 1 Type 4 - Media Device Path.
Sub-Type 1 1 Sub-Type 2 - CD-ROM “El Torito” Format.
Boot Entry 4 4 Boot Entry number from the Boot Catalog. The Ini-
tial/Default entry is deﬁned as zero.
Partition Start 8 8 Starting RBA of the partition on the medium. CD-
ROMs use Relative logical Block Addressing.
Partition Size 16 8 Size of the partition in units of Blocks, also called Sec-
tors.
10.3.5.3 Vendor-Deﬁned Media Device Path
Table 10.56: Vendor-Deﬁned Media Device Path
Sub-Type 1 1 Sub-Type 3 - Vendor.
Vendor GUID 4 16 Vendor-assigned GUID that deﬁnes the data that fol-
lows.
10.3.5.4 File Path Media Device Path
Table 10.57: File Path Media Device Path
Sub-Type 1 1 Sub-Type 4 - File Path.
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Table 10.57 – continued from previous page
Path Name 4 N A NULL-terminated Path string including directory and
ﬁle names. The length of this string n can be determined
by subtracting 4 from the Length entry. A device path
may contain one or more of these nodes. Each node can
optionally add a “" separator to the beginning and/or the
end of the Path Name string. The complete path to a
ﬁle can be found by logically concatenating all the Path
Name strings in the File Path Media Device Path nodes.
This is typically used to describe the directory path in
one node, and the ﬁlename in another node.
Rules for Path Name conversion:
• When concatenating two Path Names, ensure that the resulting string does not contain a double-separator “\”. If
it does, convert that double-separator to a single-separator.
• In the case where a Path Name which has no end separator is being concatenated to a Path Name with no
beginning separator, a separator will need to be inserted between the Path Names.
• Single ﬁle path nodes with no directory path data are presumed to have their ﬁles located in the root directory
of the device.
10.3.5.5 Media Protocol Device Path
The Media Protocol Device Path is used to denote the protocol that is being used in a device path at the location of the
path speciﬁed. Many protocols are inherent to the style of device path.
Table 10.58: Media Protocol Media Device Path
Sub-Type 1 1 Sub-Type 5 - Media Protocol.
Length 2 2 Length of this structure in bytes. Length is 20 bytes.
Protocol GUID 4 16 The ID of the protocol.
10.3.5.6 PIWG Firmware File
This type is used by systems implementing the UEFI PI Speciﬁcation to describe a ﬁrmware ﬁle. The exact format
and usage are deﬁned in that speciﬁcation.
Table 10.59: PIWG Firmware File Device Path

Sub-Type 1 1 Sub-Type 6 - PIWG Firmware File.
. . . 4 n Contents are deﬁned in the UEFI PI Speciﬁcation.
10.3. Device Path Nodes 289Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.3.5.7 PIWG Firmware Volume
This type is used by systems implementing the UEFI PI Speciﬁcation to describe a ﬁrmware volume. The exact format
Table 10.60: PIWG Firmware V olume Device Path
Sub-Type 1 1 Sub-Type 7 - PIWG Firmware V olume.
10.3.5.8 Relative Offset Range
This device path node speciﬁes a range of offsets relative to the ﬁrst byte available on the device. The starting offset is
the ﬁrst byte of the range and the ending offset is the last byte of the range (not the last byte + 1).
Table 10.61: Relative Offset Range
Type 0 1 Type 4 - Media Device Path
Sub-Type 1 1 Sub-Type 8 - Relative Offset Range
Length 2 2 Length of this structure in bytes.
Reserved 4 4 Reserved for future use.
Starting Offset 8 8 Offset of the ﬁrst byte, relative to the parent device node.
Ending Offset 16 8 Offset of the last byte, relative to the parent device node.
10.3.5.9 RAM Disk
Table 10.62: RAM Disk Device Path
Sub-Type 1 1 Sub Type 9 - RAM Disk Device Path
Length 2 2 Length of this structure in bytes. Length is 38 bytes.
Starting Address 4 8 Starting Memory Address.
Ending Address 12 8 Ending Memory Address.
Disk Type GUID 20 16 GUID that deﬁnes the type of the RAM Disk. The
GUID can be any of the values deﬁned below, or a ven-
dor deﬁned GUID.
Disk Instance 36 2 RAM Disk instance number, if supported. The default
value is zero.
The following GUIDs are used with a RAM Disk Device Path to describe the RAM Disk Type. Additional GUIDs can
be generated to describe additional RAM Disk Types. The Disk Type GUID values used in the RAM Disk device path
must match the corresponding values in the Address Range Type GUID of the ACPI NFIT table. Refer to the ACPI
speciﬁcation for details.
This GUID deﬁnes a RAM Disk supporting a raw disk format in volatile memory:
10.3. Device Path Nodes 290Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_VIRTUAL_DISK_GUID \
{ 0x77AB535A,0x45FC,0x624B,\
{0x55,0x60,0xF7,0xB2,0x81,0xD1,0xF9,0x6E }}
This GUID deﬁnes a RAM Disk supporting an ISO image in volatile memory:
#define EFI_VIRTUAL_CD_GUID \
{ 0x3D5ABD30,0x4175,0x87CE,\
{0x6D,0x64,0xD2,0xAD,0xE5,0x23,0xC4,0xBB }}
This GUID deﬁnes a RAM Disk supporting a raw disk format in persistent memory:
#define EFI_PERSISTENT_VIRTUAL_DISK_GUID \
{ 0x5CEA02C9,0x4D07,0x69D3,\
{0x26,0x9F,0x44,0x96,0xFB,0xE0,0x96,0xF9 }}
This GUID deﬁnes a RAM Disk supporting an ISO image in persistent memory:
#define EFI_PERSISTENT_VIRTUAL_CD_GUID \
{ 0x08018188,0x42CD,0xBB48,\
{0x10,0x0F,0x53,0x87,0xD5,0x3D,0xED,0x3D }}
10.3.6 BIOS Boot Speciﬁcation Device Path
This Device Path is used to describe the booting of non-EFI-aware operating systems. This Device Path is based on
the IPL and BCV table entry data structures deﬁned in Appendix A of the BIOS Boot Speciﬁcation . The BIOS Boot
Speciﬁcation Device Path deﬁnes a complete Device Path and is not used with other Device Path entries. This Device
Path is only needed to enable platform ﬁrmware to select a legacy non-EFI OS as a boot option.
Table 10.63: BIOS Boot Speciﬁcation Device Path
Type 0 1 Type 5 - BIOS Boot Speciﬁcation Device Path.
Sub-Type 1 1 Sub-Type 1 - BIOS Boot Speciﬁcation Version 1.01.
Length 2 2 Length of this structure in bytes. Length is 8 + n bytes.
Device Type 4 2 Device Type as deﬁned by the BIOS Boot Speciﬁcation.
Status Flag 6 2 Status Flags as deﬁned by the BIOS Boot Speciﬁcation
Description String 8 n A null-terminated ASCII string that describes the boot device to a
user. The size of this string ncan be determined by subtracting 8
from the Length entry.
Example BIOS Boot Speciﬁcation Device Types include:
• 00h = Reserved
• 01h = Floppy
• 02h = Hard Disk
• 03h = CD-ROM
• 04h = PCMCIA
• 05h = USB
• 06h = Embedded network
10.3. Device Path Nodes 291Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• 07h..7Fh = Reserved
• 80h = BEV device
• 81h..FEh = Reserved
• FFh = Unknown
NOTE :When UEFI Secure Boot is enabled, attempts to boot non-UEFI OS shall fail ;Firmware/OS Key Exchange:
10.4 Device Path Generation Rules
10.4.1 Housekeeping Rules
The Device Path is a set of Device Path nodes. The Device Path must be terminated by an End of Device Path node
with a sub-type of End the Entire Device Path. A NULL Device Path consists of a single End Device Path Node. A
Device Path that contains a NULL pointer and no Device Path structures is illegal.
All Device Path nodes start with the generic Device Path structure. Unknown Device Path types can be skipped when
parsing the Device Path since the length ﬁeld can be used to ﬁnd the next Device Path structure in the stream. Any
future additions to the Device Path structure types will always start with the current standard header. The size of a
Device Path can be determined by traversing the generic Device Path structures in each header and adding up the total
size of the Device Path. This size will include the four bytes of the End of Device Path structure.
Multiple hardware devices may be pointed to by a single Device Path. Each hardware device will contain a complete
Device Path that is terminated by the Device Path End Structure. The Device Path End Structures that do not end the
Device Path contain a sub-type of End This Instance of the Device Path. The last Device Path End Structure contains
a sub-type of End Entire Device Path.
10.4.2 Rules with ACPI _HID and _UID
As described in the ACPI speciﬁcation, ACPI supports several different kinds of device identiﬁcation objects, including
_HID, _CID and _UID. The _UID device identiﬁcation objects are optional in ACPI and only required if more than
one _HID exists with the same ID. The ACPI Device Path structure must contain a zero in the _UID ﬁeld if the ACPI
name space does not implement _UID. The _UID ﬁeld is a unique serial number that persists across reboots.
If a device in the ACPI name space has a _HID and is described by a _CRS (Current Resource Setting) then it should
be described by an ACPI Device Path structure. A _CRS implies that a device not mapped by any other standard.
A _CRS is used by ACPI to make a nonstandard device into a Plug and Play device. The conﬁguration methods in
the ACPI name space allow the ACPI driver to conﬁgure the device in a standard fashion. The presence of a _CID
determines whether the ACPI Device Path node or the Expanded ACPI Device Path node should be used.
See Table below.
Table 10.64: ACPI_CRS to EFI Device Path Mapping
ACPI _CRS Item EFI Device Path
PCI Root Bus ACPI Device Path: _HID PNP0A03, _UID
Floppy ACPI Device Path: _HID PNP0604, _UID drive select encoding 0-3
Keyboard ACPI Device Path: _HID PNP0301, _UID 0
Serial Port ACPI Device Path: _HID PNP0501, _UID Serial Port COM number
0-3
Parallel Port ACPI Device Path: _HID PNP0401, _UID LPT number 0-3
10.4. Device Path Generation Rules 292Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Support of root PCI bridges requires special rules in the EFI Device Path. A root PCI bridge is a PCI device usually
contained in a chipset that consumes a proprietary bus and produces a PCI bus. In typical desktop and mobile systems
there is only one root PCI bridge. On larger server systems there are typically multiple root PCI bridges. The operation
of root PCI bridges is not deﬁned in any current PCI speciﬁcation. A root PCI bridge should not be confused with a
PCI to PCI bridge that both consumes and produces a PCI bus. The operation and conﬁguration of PCI to PCI bridges
is fully speciﬁed in current PCI speciﬁcations.
Root PCI bridges will use the plug and play ID of PNP0A03, This will be stored in the ACPI Device Path _HID ﬁeld,
or in the Expanded ACPI Device Path _CID ﬁeld to match the ACPI name space. The _UID in the ACPI Device Path
structure must match the _UID in the ACPI name space.
10.4.3 Rules with ACPI _ADR
If a device in the ACPI name space can be completely described by a _ADR object then it will map to an EFI ACPI,
Hardware, or Message Device Path structure. A _ADR method implies a bus with a standard enumeration algorithm.
If the ACPI device has a _ADR and a _CRS method, then it should also have a _HID method and follow the rules for
using _HID. See the table below as it relates the ACPI _ADR bus deﬁnition to the EFI Device Path:

Table 10.65: ACPI _ADR to EFI Device Path Mapping
ACPI _ADR Bus EFI Device Path
EISA Not supported
Floppy Bus ACPI Device Path: _HID PNP0604, _UID drive select encoding 0-3
IDE Controller ATAPI Message Device Path: Maser/Slave : LUN
IDE Channel ATAPI Message Device Path: Maser/Slave : LUN
PCI PCI Hardware Device Path
PCMCIA Not Supported
PC CARD PC CARD Hardware Device Path
SMBus Not Supported
SATA bus SATA Messaging Device Path
10.4.4 Hardware vs. Messaging Device Path Rules
Hardware Device Paths are used to deﬁne paths on buses that have a standard enumeration algorithm and that relate
directly to the coherency domain of the system. The coherency domain is deﬁned as a global set of resources that is
visible to at least one processor in the system. In a typical system this would include the processor memory space, IO
space, and PCI conﬁguration space.
Messaging Device Paths are used to deﬁne paths on buses that have a standard enumeration algorithm, but are not
part of the global coherency domain of the system. SCSI and Fibre Channel are examples of this kind of bus. The
Messaging Device Path can also be used to describe virtual connections over network-style devices. An example
would be the TCP/IP address of an internet connection.
Thus Hardware Device Path is used if the bus produces resources that show up in the coherency resource domain of
the system. A Message Device Path is used if the bus consumes resources from the coherency domain and produces
resources out side the coherency domain of the system.
10.4. Device Path Generation Rules 293Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.4.5 Media Device Path Rules
The Media Device Path is used to deﬁne the location of information on a medium. Hard Drives are subdivided into
partitions by the MBR and a Media Device Path is used to deﬁne which partition is being used. A CD-ROM has
boot partitions that are deﬁned by the “El Torito” speciﬁcation, and the Media Device Path is used to point to these
partitions.
AEFI_BLOCK_IO_PROTOCOL is produced for both raw devices and partitions on devices. This
allows the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL protocol to not have to understand media for-
mats. The EFI_BLOCK_IO_PROTOCOL for a partition contains the same Device Path as the parent
EFI_BLOCK_IO_PROTOCOL for the raw device with the addition of a Media Device Path that deﬁnes which
partition is being abstracted.
The Media Device Path is also used to deﬁne the location of a ﬁle in a ﬁle system. This Device Path is used to load
ﬁles and to represent what ﬁle an image was loaded from.
10.4.6 Other Rules
The BIOS Boot Speciﬁcation Device Path is not a typical Device Path. A Device Path containing the BIOS Boot Spec-
iﬁcation Device Path should only contain the required End Device Path structure and no other Device Path structures.
The BIOS Boot Speciﬁcation Device Path is only used to allow the EFI boot menus to boot a legacy operating system
from legacy media.
The EFI Device Path can be extended in a compatible fashion by assigning your own vendor GUID to a Hardware,
Messaging, or Media Device Path. This extension is guaranteed to never conﬂict with future extensions of this speci-
ﬁcation.
The EFI speciﬁcation reserves all undeﬁned Device Path types and subtypes. Extension is only permitted using a
Vendor GUID Device Path entry.
10.5 Device Path Utilities Protocol
This section describes the EFI_DEVICE_PATH_UTILITIES_PROTOCOL, which aids in creating and manipulating
device paths.
10.5.1 EFI_DEVICE_PATH_UTILITIES_PROTOCOL
Summary
Creates and manipulates device paths and device nodes.
GUID
// {0379BE4E-D706-437d-B037-EDB82FB772A4}
#define EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID \
{0x379be4e,0xd706,0x437d,\
{0xb0,0x37,0xed,0xb8,0x2f,0xb7,0x72,0xa4 }}
typedef struct _EFI_DEVICE_PATH_UTILITIES_PROTOCOL {
EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE GetDevicePathSize;
EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH DuplicateDevicePath;
EFI_DEVICE_PATH_UTILS_APPEND_PATH AppendDevicePath;
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EFI_DEVICE_PATH_UTILS_APPEND_NODE AppendDeviceNode;
EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE AppendDevicePathInstance;
EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE GetNextDevicePathInstance;
EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE IsDevicePathMultiInstance;
EFI_DEVICE_PATH_UTILS_CREATE_NODE CreateDeviceNode;
} EFI_DEVICE_PATH_UTILITIES_PROTOCOL;
GetDevicePathSize Returns the size of the speciﬁed device path, in bytes.
DuplicateDevicePath Duplicates a device path structure.
AppendDeviceNode Appends the device node to the speciﬁed device path.
AppendDevicePath Appends the device path to the speciﬁed device path.
AppendDevicePathInstance Appends a device path instance to another device path.
GetNextDevicePathInstance Retrieves the next device path instance from a device path data structure.
IsDevicePathMultiInstance Returns TRUE if this is a multi-instance device path.
CreateDeviceNode Allocates memory for a device node with the speciﬁed type and sub-type.
The EFI_DEVICE_PATH_UTILITIES_PROTOCOL provides common utilities for creating a manipulating device
paths and device nodes.
10.5.2 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.GetDevicePathSize()
Summary
Returns the size of the device path, in bytes.
Prototype
typedef
UINTN
(EFIAPI *EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE) (
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
);
DevicePath Points to the start of the EFI device path.
This function returns the size of the speciﬁed device path, in bytes, including the end-of-path tag. If DevicePath is
NULL then zero is returned.
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10.5.3 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.DuplicateDevicePath()
Summary
Create a duplicate of the speciﬁed path.
Prototype
typedef
EFI_DEVICE_PATH_PROTOCOL *
(EFIAPI *EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH) (
);
DevicePath Points to the source device path.
This function creates a duplicate of the speciﬁed device path. The memory is allocated from EFI boot services memory.
It is the responsibility of the caller to free the memory allocated. If DevicePath is NULL then NULL will be returned
and no memory will be allocated.
Returns
This function returns a pointer to the duplicate device path or NULL if there was insufﬁcient memory.
10.5.4 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.AppendDevicePath()
Summary
Create a new path by appending the second device path to the ﬁrst.
Prototype
typedef
(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_PATH) (
IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1 ,
IN CONST EFI_DEVICE_PATH_PROTOCOL *Src2
);
Src1 Points to the ﬁrst device path.
Src2 Points to the second device path.
This function creates a new device path by appending a copy of the second device path to a copy of the ﬁrst device
path in a newly allocated buffer. Only the end-of-device-path device node from the second device path is retained. If
Src1 is NULL and Src2 is non-NULL , then a duplicate of Src2 is returned. If Src1 is non-NULL and Src2 is NULL,
then a duplicate of Src1 is returned. If Src1 andSrc2 are both NULL, then a copy of an end-of-device-path is returned.
The memory is allocated from EFI boot services memory. It is the responsibility of the caller to free the memory
allocated.
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Returns
This function returns a pointer to the newly created device path or NULL if memory could not be allocate.
10.5.5 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.AppendDeviceNode()
Summary
Creates a new path by appending the device node to the device path.
Prototype
typedef
(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_NODE) (
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode
);
DevicePath
Points to the device path.
DeviceNode
Points to the device node.
This function creates a new device path by appending a copy of the speciﬁed device node to a copy of the speciﬁed
device path in an allocated buffer. The end-of-device-path device node is moved after the end of the appended device
node. If DeviceNode is NULL then a copy of DevicePath is returned. If DevicePath is NULL then a copy of DeviceN-
ode, followed by an end-of-device path device node is returned. If both DeviceNode andDevicePath are NULL then
a copy of an end-of-device-path device node is returned.

Summary
Prototype
typedef
);
Returns
This function returns a pointer to the allocated device path, or NULL if there was insufﬁcient memory.
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10.5.6 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.AppendDevicePathInstance()
Summary
Creates a new path by appending the speciﬁed device path instance to the speciﬁed device path.
Prototype
typedef
(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE) (
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathInstance
);
DevicePath Points to the device path. If NULL, then ignored.
DevicePathInstance Points to the device path instance
This function creates a new device path by appending a copy of the speciﬁed device path instance to a copy of the
speciﬁed device path in an allocated buffer. The end-of-device-path device node is moved after the end of the appended
device node and a new end-of-device-path-instance node is inserted between. If DevicePath is NULL, then a copy if
DevicePathInstance is returned instead.
Returns
This function returns a pointer to the newly created device path or NULL if DevicePathInstance is NULL or there was
insufﬁcient memory.
10.5.7 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.GetNextDevicePathInstance()
Summary
Creates a copy of the current device path instance and returns pointer to the next device path instance.
Prototype
typedef
(EFIAPI *EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE) (
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathInstance,
OUT UINTN *DevicePathInstanceSize *OPTIONAL
);
DevicePathInstance On input, this holds the pointer to the current device path instance. On output, this holds the
pointer to the next device path instance or NULL if there are no more device path instances in the device path.
DevicePathInstanceSize On output, this holds the size of the device path instance, in bytes or zero, if DevicePathIn-
stance is NULL. If NULL, then the instance size is not output.
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This function creates a copy of the current device path instance. It also updates DevicePathInstance to point to the
next device path instance in the device path (or NULL if no more) and updates DevicePathInstanceSize to hold the
size of the device path instance copy.
Returns
This function returns a pointer to the copy of the current device path instance or NULL if DevicePathInstance was
NULL on entry or there was insufﬁcient memory.
10.5.8 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.CreateDeviceNode()
Summary
Creates a device node
Prototype
typedef
(EFIAPI *EFI_DEVICE_PATH_UTILS_CREATE_NODE) (
IN UINT8 NodeType,
IN UINT8 NodeSubType,
IN UINT16 NodeLength
);
NodeType NodeType is the device node type (EFI_DEVICE_PATH_PROTOCOL.Type) for the new device node.
NodeSubType NodeSubType is the device node sub-type (EFI_DEVICE_PATH_PROTOCOL.SubType) for the new
device node.
NodeLength NodeLength is the length of the device node (EFI_DEVICE_PATH_PROTOCOL.Length) for the new
This function creates a new device node in a newly allocated buffer.
Returns
This function returns a pointer to the created device node or NULL if NodeLength is less than the size of the header or
there was insufﬁcient memory.
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10.5.9 EFI_DEVICE_PATH_UTILITIES_PROTOCOL.IsDevicePathMultiInstance()
Summary
Returns whether a device path is multi-instance.
Prototype
typedef
BOOLEAN
(EFIAPI *EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE) (
);
This function returns whether the speciﬁed device path has multiple path instances.
EFI_DEVICE_PATH_PROTOCOL* is deﬁned in EFI Device Path Protocol .
Returns
This function returns TRUE if the device path has more than one instance or FALSE if it is empty or contains only a
single instance.
10.6 EFI Device Path Display Format Overview
This section describes the recommended conversion between an EFI Device Path Protocol and text. It also describes
standard protocols for implementing these. The goals are:
• Standardized display format. This allows documentation and test tools to understand output coming from drivers
provided by multiple vendors.
• Increase Readability. Device paths need to be read by people, so the format should be in a form which can be
deciphered, maintaining as much as possible the industry standard means of presenting data. In this case, there
are two forms, a display-only form and a parse-able form.
• Round-trip conversion from text to binary form and back to text without loss, if desired.
• Ease of command-line parsing. Since device paths can appear on the command-lines of UEFI applications
executed from a shell, the conversion format should not prohibit basic command-line processing, either by the
application or by a shell.
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10.6.1 Design Discussion
The following subsections describe the design considerations for conversion to and from the EFI Device Path Protocol
binary format and its corresponding text form.
10.6.1.1 Standardized Display Format
Before the UEFI 2.0, there was no standardized format for the conversion from the EFI Device Path protocol and text.
Some de-facto standards arose, either as part of the standard implementation or in descriptive text in the EFI Device
Driver Writer’s Guide, although they didn’t agree. The standardized format attempts to maintain at least the spirit of
these earlier ideas.
10.6.1.2 Readability
Since these are conversions to text and, in many cases, users have to read and understand the text form of the EFI
Device Path, it makes sense to make them as readable as reasonably possible. Several strategies are used to accomplish
this:
• Creating simpliﬁed forms for well-known device paths. For example, a PCI root Bridge can be represented as
Acpi(PNP0A03,0), but makes more sense as PciRoot(0). When converting from text to binary form, either form
is accepted, but when converting from binary form to text, the latter is preferred.
• Omitting the conversion of ﬁelds which have empty or default values. By doing this, the average display length
is greatly shortened, which improves readability.
10.6.1.3 Round-Trip Conversion
The conversions speciﬁed here guarantee at least that conversion to and from the binary representation of the EFI
Device Path will be semantically identical.
Text-to-Binary-Conversion
Text 1ð Binary 1ð Text 2ð Binary 2
In the above conversion, the process described in this section is applied to Text1, converting it to Binary1. Subse-
quently, Binary1 is converted to Text2. Finally, the Text2 is converted to Binary2. In these cases, Binary1 and Binary2
will always be identical. Text1 and Text2 may or may not be identical. This is the result of the fact that the text
representation has, in some cases, more than one way of representing the same EFI Device Path node.
Binary to Text Conversion
Binary 1ð Text 1ð Binary 2ðText 2
In the above conversion, the process described in this section is applied to Binary1, converting it to Text1. Subse-
quently, Text1 is converted to Binary2. Finally, Binary2 is converted to Text2. In these cases, Binary1 and Binary2
will always be identical and Text1 and Text2 will always be identical.
Another consideration in round-trip conversion is potential ambiguity in parsing. This happens when the text represen-
tation could be converted into more than type of device node, thus requiring information beyond that contained in the
text representation in order to determine the correct conversion to apply. In the case of EFI Device Paths, this causes
problems primarily with literal strings in the device path, such as those found in ﬁle names, volumes or directories.

For example, the ﬁle name Acpi(PNP0A03,0) might be a legal FAT32 ﬁle name. However, in parsing this, it is not
clear whether it refers to an Acpi device node or a ﬁle name. Thus, it is ambiguous. In order to prevent ambiguity,
certain characters may only be used for device node keywords and may not be used in ﬁle names or directories.
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10.6.1.4 Command-Line Parsing
Applications written to this speciﬁcation need to accept the text representation of EFI device paths as command-line
parameters, possibly in the context of a command-prompt or shell. In order to do this, the text representation must
follow simple guidelines concerning its format.
Command-line parsing generally involves three separate concepts: substitution, redirection and division.
In substitution, the invoker of the application modiﬁes the actual contents of the command-line before it is passed to
the application. For example:
copy*.xyz
In redirection, the invoker of the application gleans from the command line parameters which it uses to, for example,
redirect or pipe input or output. For example:
echo This text iscopied to a file >abc
dir | more
Finally, in division, the invoker or the application startup code divides the command-line up into individual arguments.
The following line, for example, has (at least) three arguments, divided by whitespace:
copy /b file1.info file2.info
10.6.1.5 Text Representation Basics
This section describes the basic rules for the text representation of device nodes and device paths. The formal grammar
describing appears later.
The text representation of a device path (or text device path) consists of one or more text device nodes, each preceded
by a ‘/’ or ‘\’ character. The behavior of a device path where the ﬁrst node is not preceded by one of these characters
is undeﬁned. Some implementations may treat it as a relative path from a current working directory.
Spaces are not allowed at any point within the device path, except when contained in double quotes ("). The ‘|’ (bar),
‘<’ (less than) and ‘>’ (greater than) characters are likewise reserved for use by the shell.
Device Path Text Representation
device-path:=\device-node
/device-node
\device-path device-node
/device-path device-node
There are two types of text device nodes : ﬁle-name/directory or canonical. Canonical text device nodes are preﬁxed by
an option name consisting of only alphanumerical characters, followed by a parenthesis, followed by option-speciﬁc
parameters separated by a ‘,’ (comma). File names and directories have no preﬁxes.
Text Device Node Names
device-node :=standard-device-node | file-name/directory
standard-device-node :=option-name(option-parameters)
file-name/directory := any character except'/''\''|''>''<'
The canonical device node can have zero or more option parameters between the parentheses. Multiple option param-
eters are separated by a comma. The meaning of the option parameters depends primarily on the option name, then
the parameter-identiﬁer (if present) and then the order of appearance in the parameter list. The parameter identiﬁer
allows the text representation to only contain the non-default option parameter value, even if it would normally appear
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fourth in the list of option parameters. Missing parameters do not require the comma unless needed as a placeholder
to correctly increment the parameter count for a subsequent parameter.
Consider:
AcpiEx(HWP0002, PNP0A03,0)
Which could also be written:
AcpiEx(HWP0002,CID=PNP0A03) or
AcpiEx(HWP0002,PNP0A03)
Since CID and UID are optional parameters. Or consider:
Acpi(HWP0002,0)
Acpi(HWP0002)
Since UID is an optional parameter.
Device Node Option Names
option-name :=alphanumerical characters string
option-parameters :=option-parameter
option-parameters,option-parameter
option-parameter :=parameter-value
parameter-identifier=parameter-value
10.6.1.6 Text Device Node Reference
In each of the following table rows, a speciﬁc device node type and sub-type are given, along with the most general
form of the text representation. Any parameters for the device node are listed in italics. In each case, the type is listed
and along with it what is required or optional, and any default value, if applicable. On subsequent lines, alternate
representations are listed. In general, these alternate representations are simpliﬁed by the assumption that one or more
of the parameters is set to a speciﬁc value.
Parameter Types
This section describes the various types of option parameter values.
Table 10.66: EFI Device Path Option Parameter Values
GUID An EFI GUID in standard format xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx. (See
Appendix A)
Keyword In some cases, one of a series of keywords must be listed.
Integer Unless otherwise speciﬁed, this indicates an unsigned integer in the range of 0 to
2^32-1. The value is decimal, unless preceded by “0x” or “0X”, in which case it is
hexadecimal.
EISAID A seven character text identiﬁer in the format used by the ACPI speciﬁcation. The
ﬁrst three characters must be alphabetic, either upper or lower case. The second four
characters are hexadecimal digits, either numeric, upper case or lower case. Option-
ally, it can be the number 0.
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Table 10.66 – continued from previous page
String Series of alphabetic, numeric and punctuation characters not including a right paren-
thesis ‘)’, bar ‘
HexDump Series of bytes, represented by two hexadecimal characters per byte. Unless otherwise
indicated, the size is only limited by the length of the device node.
IPv4 Address Series of four integer values (each between 0-255), separated by a ‘.’ Optionally,
followed by a ‘:’ and an integer value between 0-65555. If the ‘:’ is not present, then
the port value is zero.
IPv6 Address IPv6 Address is expressed in the format [address]:port. The ‘address’ is expressed in
the way deﬁned in RFC4291 Section 2.2. The ‘:port’ after the [address] is optional. If
present, the ‘port’ is an integer value between 0-65535 to represent the port number,
or else, port number is zero.
Table 10.67: Device Node Table
Device Node
Type/SubType/OtherDescription
(when type is not
recognized)Path (type, subtype, data )
The type is an integer from 0-255.
The sub-type is an integer from 0-255.
The data is a hex dump.
Type: 1 (Hardware
Device Path)
(when subtype is not
recognized)HardwarePath (subtype, data)
The subtype is an integer from 0-255.
SubType: 1 (PCI)Pci(Device, Function)
The Device is an integer from 0-31 and is required.
The Function is an integer from 0-7 and is required.
SubType: 2 (PcPcard)PcCard (Function)
The Function is an integer from 0-255 and is required.
SubType: 3 (Memory
Mapped)MemoryMapped (EﬁMemoryType,StartingAddress, EndingAddress )
The EﬁMemoryType is a 32-bit integer and is required.
The StartingAddress and EndingAddress are both 64-bit integers and are both
required.
Type: 1 (Hardware Device
Path) SubType: 4 (Ven-
dor)VenHw(Guid, Data)
The Guid is a GUID and is required.
The Data is a Hex Dump and is optional. The default value is zero bytes.
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Table 10.67 – continued from previous page
SubType: 5 (Controller)Ctrl(Controller)
Controller is an integer and is required.
SubType: 6 (BMC)BMC (Type,Address)
The Type is an integer from 0-255, and is required.
The Address is an unsigned 64-bit integer, and is required.
Type: 2 (ACPI Device
Path)
recognized)AcpiPath(subtype, data) The subtype is an integer from 0-255. The data is a hex
dump.
Path)
SubType: 1 (ACPI Device
Path)Acpi(HID,UID)
The HID parameter is an EISAID and is required.
The UID parameter is an integer and is optional. The default value is zero.
Path)
Path) HID=PNP0A03PciRoot(UID) |
The UID parameter is an integer. It is optional but required for display. The default
Path)
Path) HID=PNP0A08PcieRoot(UID)
Path)
Path) HID=PNP0604Floppy(UID)
The UID parameter is an integer. It is optional for input but required for display. The
default value is zero.
Path)
Path) HID=PNP0301Keyboard(UID)

Path)
dump.
Path)
Path)
Path)
Path)
Path)
default value is 0.
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Path)
Path) HID=PNP0501Serial(UID)
Path)
Path) HID=PNP0401ParallelPort(UID)
Path)
SubType: 2 (ACPI
Expanded Device Path)AcpiEx( HID,CID,UID,HIDSTR,CIDSTR,UIDSTR)
AcpiEx(HID ,(CID Only)
The HID parameter is an EISAID. The default value is 0. Either HID or HIDSTR
must be present.
The CID parameter is an EISAID. The default value is 0. Either CID must be 0 or
CIDSTR must be empty.
The UID parameter is an integer. The default value is 0. Either UID must be 0 or
UIDSTR must be empty.
The HIDSTR is a string. The default value is the empty string. Either HID or
HIDSTR must be present.
The CIDSTR is a string. The default value is an empty string. Either CID must be 0
or CIDSTR must be empty.
The UIDSTR is a string. The default value is an empty string. Either UID must be 0
or UIDSTR must be empty.
Path)
Expanded Device Path)
HIDSTR=empty
CIDSTR=empty
UID STR!=emptyAcpiExp(HID,CID,UIDSTR)
The HID parameter is an EISAID. It is required.
The CID parameter is an EISAID. It is optional and has a default value of 0.
The UIDSTR parameter is a string. If UID is 0 and UIDSTR is empty, then use
AcpiEx format.
Path)
HID=PNP0A03 or
CID=PNP0A03 and
HID != PNP0A08.PciRoot(UID|UIDSTR) (Display Only)
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Path)
HID=PNP0A08 or
CID=PNP0A08.PcieRoot(UID|UIDSTR) (Display Only)
Path)
SubType: 3 (ACPI ADR
Device Path)AcpiAdr(DisplayDevice[, DisplayDevice. . . ])
TheDisplayDevice parameter is an Integer. There may be one or more, separated by
a comma.
Type: 3 MessagingPath
recognized)Msg( subtype, data )
Thesubtype is an integer from 0-255.
Thedata is a hex dump.
Type: 3 (Messaging
SubType: 1 (ATAPI)Ata(Controller,Drive,LUN )
Ata(LUN) (Display only)
The Controller is either an integer with a value of 0 or 1 or else the keyword Primary
(0) or Secondary (1). It is required.
The Drive is either an integer with the value of 0 or 1 or else the keyword Master (0)
or Slave (1). It is required.
The LUN is a 16-bit integer. It is required.
Type: 3 (Messaging De-
vice Path) SubType: 2
(SCSI)Scsi (PUN,LUN )
The*PUN* is an integer between 0 and 65535 and is required.
TheLUN is an integer between 0 and 65535 and is required.
SubType: 3 (Fibre
Channel)Fibre (WWN,LUN)
The WWN is a 64-bit unsigned integer and is required.
The LUN is a 64-bit unsigned integer and is required.
SubType: 21 (Fibre
Channel Ex)FibreEx (WWN,LUN)
The WWN is an 8 byte array that is displayed in hexadecimal format with byte 0 ﬁrst
(i.e., on the left) and byte 7 last (i.e., on the right), and is required.
The LUN is an 8 byte array that is displayed in hexadecimal format with byte 0 ﬁrst
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SubType: 4 (1394)I1394 (GUID )
TheGUID is a GUID and is required.
SubType: 5 (USB)USB (Port,Interface )
ThePort is an integer between 0 and 255 and is required.
TheInterface is an integer between 0 and 255 and is required.
SubType: 6 (I2O)I2O (TID)
The TID is an integer and is required.
SubType: 9 (Inﬁniband)Inﬁniband (Flags, Guid, ServiceId, TargetId, DeviceId )
Flags is an integer.
Guid is a guid.
ServiceId, TargetId andDeviceId are 64-bit unsigned integers.
All ﬁelds are required.
SubType: 10 (Vendor)VenMsg(Guid, Data)
The Data is a Hex Dump and is option.
The default value is zero bytes.
SubType: 10 (Vendor)
GUID=
EFI_PC_ANSI_GUIDVenPcAnsi()
GUID=
EFI_VT_100_GIUDVenVt100 ()
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GUID=
EFI_VT_100_PLUS_GUIDVenVt100Plus ()
GUID=
EFI_VT_UTF8_GUIDVenUtf8 ()
GUID=DEVICE
_PATH_MESSAGING
_UART_FLOW
_CONTROLUartFlowCtrl (Value )
TheValue is either an integer with the value 0, 1 or 2 or the keywords XonXoff (2)
orHardware (1) or None (0).
SubType: 10 (Serial
Attached SCSI)
Vendor GUID: d48
7ddb4-008b-11d9-afdc-
001083ffca4dSAS (Address, LUN, RTP , SASSATA, Location, Connect, DriveBay, Reserved )
The Address is a 64-bit unsigned integer representing the SAS Address and is
required.
The LUN is a 64-bit unsigned integer representing the Logical Unit Number and is
optional. The default value is 0.
The RTP is a 16-bit unsigned integer representing the Relative Target Port and is
The SASSATA is a keyword SAS or SATA or NoTopology or an unsigned 16-bit
integer and is optional. The default is NoTopology. If NoTopology or an integer are
speciﬁed, then Location, Connect and DriveBay are prohibited. If SAS or SATA is
speciﬁed, then Location and Connect are required, but DriveBay is optional. If an
integer is speciﬁed, then the topology information is ﬁlled with the integer value.
The Location is an integer between 0 and 1 or else the keyword Internal (0) or
External (1) and is optional. If SASSATA is an integer or NoToplogy, it is
prohibited. The default value is 0.
The Connect is an integer between 0 and 3 or else the keyword Direct (0) or
Expanded (1) and is optional. If SASSATA is an integer or NoTopology, it is
The DriveBay is an integer between 1 and 256 and is optional unless SASSATA is an
integer or NoTopology, in which case it is prohibited. The Reserved ﬁeld is an
integer and is optional. The default value is 0.
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GUID=EFI_DEBUGPORT
_PROTOCOL_GUIDDebugPort()
SubType: 11 (MAC
Address)MAC(MacAddr, IfType)
The MacAddr is a Hex Dump and is required. If IfType is 0 or 1, then the MacAddr
must be exactly six bytes.
The IfType is an integer from 0-255 and is optional. The default is zero.
SubType: 12 (IPv4)IPv4(RemoteIp, Protocol, Type, LocalIp, GatewayIPAddress, SubnetMask)
IPv4(RemoteIp) (Display Only)
The RemoteIp is an IP Address and is required.
The Protocol is an integer between 0 and 255 or else the keyword UDP (17) or TCP
(6). The default value is UDP.
The Type is a keyword, either Static (1) or DHCP (0). It is optional. The default
value is DHCP.
The LocalIp is an IP Address and is optional. The default value is all zeroes.
The GatewayIPAddress is an IP Address and is optional. The default value is all
zeroes.
The SubnetMask is an IP Address and is optional. The default value is all zeroes.
SubType: 13 (IPv6)IPv6(RemoteIp, Protocol, IPAddressOrigin, LocalIp, GatewayIPAddress,
SubnetMask)
IPv6(RemoteIp) (Display Only)
The RemoteIp is an IPv6 Address and is required.
The IPAddressOrigin is a keyword, could be Static (0), StatelessAutoConﬁgure (1),
or StatefulAutoConﬁgure (2). The LocalIp is the IPv6 Address and is optional. The
default value is all zeroes.
The GatewayIPAddress is an IP Address. The PreﬁxLength is the preﬁx length of the
Local IPv6 Address.
The GatewayIPAddress is the IPv6 Address of the Gateway.
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zeroes.
SubType: 14 (UART)Uart(Baud, DataBits, Parity, StopBits)
The Baud is a 64-bit integer and is optional. The default value is 115200.
The DataBits is an integer from 0 to 255 and is optional. The default value is 8.
The Parity is either an integer from 0-255 or else a keyword and should be D (0), N
(1), E (2), O (3), M (4) or S (5). It is optional. The default value is 0.
The StopBits is a either an integer from 0-255 or else a keyword and should be D (0),
1 (1), 1.5 (2), 2 (3). It is optional. The default value is 0.
Parity and StopBits can either be two integers or two keywords. Mixing formats is
prohibited.
SubType: 15 (USB Class)UsbClass (VID,PID,Class,SubClass,Protocol)
The VID is an integer between 0 and 65535 and is optional. The default value is
0xFFFF.
The PID is an integer between 0 and 65535 and is optional. The default value is
0xFFFF.
The Class is an integer between 0 and 255 and is optional. The default value is 0xFF.
The SubClass is an integer between 0 and 255 and is optional. The default value is
0xFF.
The Protocol is an integer between 0 and 255 and is optional. The default value is
0xFF.
SubType: 15 (USB Class)
Class 1Us bAudio(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 2UsbCDCC ontrol(VID,PID,SubClass,Protocol)
The VID is an optional integer between 0 and 65535 and is optional. The default
value is 0xFFFF.
The PID is an optional integer between 0 and 65535 and is optional. The default
The SubClass is an optional integer between 0 and 255 and is optional. The default
value is 0xFF.
The Protocol is an optional integer between 0 and 255 and is optional. The default
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Class 3UsbHID(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 6Us bImage(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 7UsbP rinter(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 8UsbMassS torage(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
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Class 9UsbHub(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 10UsbC DCData(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 11UsbSma rtCard(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 14Us bVideo(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
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Class 220Us bDiagnostic(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 224UsbWi reless(VID,PID,SubClass,Protocol)
0xFFFF.
0xFFFF.
0xFF.
0xFF.
Class 254
SubClass: 1UsbDevic eFirmwareUpdate(VID,PID,Protocol)
0xFFFF.
0xFFFF.
0xFF.
Class 254
SubClass: 2UsbIrdaBridge(VID,PID,Protocol)
0xFFFF.
0xFFFF.
0xFF.
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Class 254
SubClass: 3UsbTes tAndMeasurement(VID,PID,Protocol)
0xFFFF.
0xFFFF.
0xFF.
SubType: 16 (USB
WWID Class)UsbWwi d(VID,PID,InterfaceNumber,”WWID”)
The VID is an integer between 0 and 65535 and is required.
The PID is an integer between 0 and 65535 and is required.
The InterfaceNumber is an integer between 0 and 255 and is required.
The WWID is a string and is required.
SubType: 17 (Logical

0xFF.
Class 254
0xFFFF.
0xFFFF.
0xFF.
Unit Class)Unit(LUN)
The LUN is an integer and is required.
SubType: 18 (SATA)Sata(HPN, PMPN, LUN)
The HPN is an integer between 0 and 65534 and is required.
The PMPN is an integer between 0 and 65535 and is optional. If not provided, the
default is 0xFFFF, which implies no port multiplier.
The LUN is a 16-bit integer. It is required. Note that LUN is applicable to ATAPI
devices only, and most ATAPI devices assume LUN=0
Device Path) SubType:
19 (iSCSI)iSCSI(TargetName, PortalGroup, LUN, HeaderDigest, DataDigest, Authentication,
Protocol)
The TargetName is a string and is required.
PortalGroup is an unsigned 16-bit integer and is required.
(i.e., on the left) and byte 7 last (i.e, on the right), and is required.
The HeaderDigest is a keyword None or CRC32C is optional. The default is None.
The DataDigest is a keyword None or CRC32C is optional. The default is None.
The Authentication is a keyword None or CHAP_BI or CHAP_UNI and optional.
The default is None.
The Protocol deﬁnes the network protocol used by iSCSI and is optional. The
default is TCP.
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SubType: 20 (VLAN)Vlan (VlanId)
SubType: 22 (Serial
Attached SCSI Ex)SasEx (Address, LUN, RTP , SASSATA, Location, Connect, DriveBay)
TheAddress is an 8 byte array that is displayed in hexadecimal format with byte 0
ﬁrst (i.e., on the left) and byte 7 last (i.e., on the right), and is required.
TheLUN is an 8 byte array that is displayed in hexadecimal format with byte 0 ﬁrst
(i.e., on the left) and byte 7 last (i.e., on the right), and is optional. The default value
is 0.
TheRTP is a 16-bit unsigned integer representing the Relative Target Port and is
TheSASSATA is a keyword SAS or SATA orNoTopology or an unsigned 16-bit
speciﬁed, then Location ,Connect andDriveBay are prohibited. If SASorSATA is
TheLocation is an integer between 0 and 1 or else the keyword Internal (0) or
External (1) and is optional. If SASSATA is an integer or NoToplogy , it is prohibited.
The default value is 0.
TheConnect is an integer between 0 and 3 or else the keyword Direct (0) or
Expanded (1) and is optional. If SASSATA is an integer or NoTopology , it is
TheDriveBay is an integer between 1 and 256 and is optional unless SASSATA is an
integer or NoTopology , in which case it is prohibited.
SubType: 23 (NVM
Express Namespace)NVMe(NSID,EUI)
The NSID is a namespace identiﬁer that is displayed in hexadecimal format with an
integer value between 0 and 0xFFFFFFFF.
The EUI is the IEEE Extended Unique Identiﬁer (EUI-64) that is displayed in
hexadecimal format represented as a set of octets separated by dashes (hexadecimal
notation), e.g., FF-FF-FF-FF-FF-FF-FF-FF.
SubType: 24 (URI)Uri(Uri)
TheUriis optional.
SubType: 25 (Universal
Flash Storage)UFS (PUN,LUN )
ThePUN is 0 for current UFS2.0 spec. For future UFS specs which support multiple
devices on a UFS port, it would reﬂect the device ID on the UFS port.
TheLUN is 0-7 for common LUNs or 81h, D0h, B0h and C4h for well-known
LUNs supported by UFS.
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SubType: 26 (SD)SD(Slot Number )
SlotNumber is an integer. It is optional and has a default value of 0.
SubType: 27 (Bluetooth)Bluetooth(BD_ADDR)
BD_ADDR is HEX dump of 48-bit Bluetooth device address.
SubType: 28 (Wi-Fi)Wi-Fi (SSID)
TheSSID is a string and is required.
SubType: 29 (eMMC)eMMC (SlotNumber)
SubType: 30
(BluetoothLE)BluetoothLE(BD_ADDR, AddressType)
AddressType is an integer.
SubType: 31 (DNS)Dns(DnsServerIp[, DnsServerIp. . . ])
DnsServerIp is optional. It is the IP address of DNS server.
SubType: 32 (NVDIMM
Service)RestService(RestExServiceType, AccessMode)
SubType: 33 (REST
For vendor-speciﬁc REST service:
RestService(RestExServiceType, AccessMode,
VendorRestServiceGuid,
VendorDeﬁnedData)
RestExServiceType is 0xff in this case.
10.6. EFI Device Path Display Format Overview 317Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SubType: 34 (NVMe-oF
Namespace)NVMEoF(SubsystemNQN, NID)
SubsystemNQN – Maximum 224 byte unique subsystem identiﬁer including null
termination in compliance with the NVM Express® Base Speciﬁcation.
NID – Globally unique identiﬁer deﬁned by the value of the Namespace Identiﬁer
(NID) deﬁned by the Namespace Identiﬁcation Descriptor from the NVM Express®
Base Speciﬁcation.
Type: 4 (Media Device
Path)
recognized)MediaPath(subtype, data)
The subtype is an integer from 0-255 and is required. The data is a hex dump.
Path)
SubType: 1 (Hard Drive)H D(Partition,Type,Signature,Start, Size)
HD(Partition,Type,Signature) (Display Only)
The Partition is an integer representing the partition number. It is optional and the
default is 0. If Partition is 0, then Start and Size are prohibited. The Type is an
integer between 0-255 or else the keyword MBR (1) or GPT (2). The type is optional
and the default is 2.
Signature is an integer if Type is 1 or else GUID if Type is 2. The signature is
required.
The Start is a 64-bit unsigned integer. It is prohibited if Partition is 0.
Otherwise it is required.
The Size is a 64-bit unsigned integer. It is prohibited if Partition is 0.
Path)
SubType: 2 (CD-ROM)CDROM(Entry,Start,Size)
CDROM(Entry) (Display Only)
The Entry is an integer representing the Boot Entry from the Boot Catalog. It is
optional and the default is 0.
The Start is a 64-bit integer and is required.
The Size is a 64-bit integer and is required.
Type: 4 (Media | Device
Path)
SubType: 3 (Vendor)VenMedia(GUID, Data)
The Guid is a GUID and is required. |
The Data is a Hex Dump and is option. The default value is zero bytes.
Path)
SubType: 4 (File Path)String
The String is the ﬁle path and is a string.
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Path)
SubType: 5 (Media
Protocol)Media(Guid)
Path)
SubType: 6 (PIWG
Firmware File)Contents are deﬁned in the UEFI PI Speciﬁcation .
Path)
SubType: 7 (PIWG
Firmware V olume)Contents are deﬁned in the UEFI PI Speciﬁcation .
Path)
SubType: 8 (Relative
Offset Range)Offset (StartingOffset,EndingOffset )
TheStartingOffset is an unsigned 64-bit integer. The EndingOffset is an unsigned
64-bit integer.
Path)
SubType: 9 (RAM Disk)RamDisk (StartingAddress ,EndingAddress ,DiskInstance ,DiskTypeGuid )
TheStartingAddress andEndingAddress are both 64-bit integers and are both
required.
TheDiskInstance is a 16-bit integer and is optional. The default value is 0.
TheDiskTypeGuid is a GUID and is required.
Path)
SubType: 9 (RAM Disk)
Disk Type GUID=
EFI_VIRTUAL_DISK
_GUIDVirtualDisk StartingAddress ,EndingAddress ,DiskInstance )
required.
Path)
EFI_VIRTUAL_CD
_GUIDVirtualCD (StartingAddress ,EndingAddress ,DiskInstance )
required.
10.6. EFI Device Path Display Format Overview 319Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Path)

required.
Path)
required.
Path)
required.
Path)
EFI_PERSISTENT
_VIRTUAL_DISK
_GUIDPersistentVirtualDisk (StartingAddress ,EndingAddress ,DiskInstance )
required.
Path)
_VIRTUAL_CD_GUIDPersistentVirtualCD
(StartingAddress ,
EndingAddress ,
DiskInstance )
required.
Type: 5 (Media Device
Path)
recognized)BbsPath(subtype, data)
Type: 5 (BIOS Boot
Speciﬁcation Device
Path)
SubType: 1 (BBS 1.01)BBS(Type,Id,Flags)
BBS(Type, Id) (Display Only)
The Type is an integer from 0-65535 or else one of the following keywords: Floppy
(1), HD (2), CDROM (3), PCMCIA (4), USB (5), Network (6). It is required.
The Id is a string and is required.
The Flags are an integer and are optional. The default value is 0.
10.6.2 Device Path to Text Protocol
10.6.2.1 EFI_DEVICE_PATH_TO_TEXT_PROTOCOL
Summary
Convert device nodes and paths to text.
GUID
#define EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID \
{0x8b843e20,0x8132,0x4852,\
{0x90,0xcc,0x55,0x1a,0x4e,0x4a,0x7f,0x1c}}
10.6. EFI Device Path Display Format Overview 320Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct _EFI_DEVICE_PATH_TO_TEXT_PROTOCOL {
EFI_DEVICE_PATH_TO_TEXT_NODE ConvertDeviceNodeToText;
EFI_DEVICE_PATH_TO_TEXT_PATH ConvertDevicePathToText;
} EFI_DEVICE_PATH_TO_TEXT_PROTOCOL;
ConvertDeviceNodeToText Converts a device node to text.
ConvertDevicePathToText Converts a device path to text.
The EFI_DEVICE_PATH_TO_TEXT_PROTOCOL provides common utility functions for converting device nodes
and device paths to a text representation.
10.6.3 EFI_DEVICE_PATH_TO_TEXT_PROTOCOL.ConvertDeviceNodeToText()
Summary
Convert a device node to its text representation.
Prototype
typedef
CHAR16*
(EFIAPI *EFI_DEVICE_PATH_TO_TEXT_NODE) (
IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode,
IN BOOLEAN DisplayOnly,
IN BOOLEAN AllowShortcuts
);
DeviceNode Points to the device node to be converted.
DisplayOnly IfDisplayOnly isTRUE , then the shorter text representation of the display node is used, where appli-
cable. If DisplayOnly isFALSE , then the longer text representation of the display node is used.
AllowShortcuts IfAllowShortcuts isTRUE , then the shortcut forms of text representation for a device node can be
used, where applicable.
The ConvertDeviceNodeToText function converts a device node to its text representation and copies it into a newly
allocated buffer.
TheDisplayOnly parameter controls whether the longer (parseable) or shorter (display-only) form of the conversion
is used.
The AllowShortcuts isFALSE , then the shortcut forms of text representation for a device node cannot be used. A
shortcut form is one which uses information other than the type or subtype.
EFI_DEVICE_PATH_PROTOCOL is deﬁned in EFI Device Path Protocol
Returns
10.6. EFI Device Path Display Format Overview 321Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function returns the pointer to the allocated text representation of the device node data or else NULL if DeviceN-
odewas NULL or there was insufﬁcient memory.
10.6.4 EFI_DEVICE_PATH_TO_TEXT_PROTOCOL.ConvertDevicePathToText()
Summary
Convert a device path to its text representation.
Prototype
typedef
CHAR16*
(EFIAPI *EFI_DEVICE_PATH_TO_TEXT_PATH) (
);
DeviceNode Points to the device path to be converted.
AllowShortcuts The AllowShortcuts isFALSE , then the shortcut forms of text representation for a device node
cannot be used.
This function converts a device path into its text representation and copies it into an allocated buffer.
is used.
Returns
This function returns a pointer to the allocated text representation of the device node or NULL if DevicePath was
NULL or there was insufﬁcient memory.
10.6. EFI Device Path Display Format Overview 322Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
10.6.5 Device Path from Text Protocol
10.6.5.1 EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL
Summary
Convert text to device paths and device nodes.
GUID
#define EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL_GUID \
{0x5c99a21,0xc70f,0x4ad2,\
{0x8a,0x5f,0x35,0xdf,0x33,0x43,0xf5, 0x1e}}
typedef struct _EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL {
EFI_DEVICE_PATH_FROM_TEXT_NODE ConvertTextToDevicNode;
EFI_DEVICE_PATH_FROM_TEXT_PATH ConvertTextToDevicPath;
} EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL;
ConvertTextToDeviceNode Converts text to a device node.
ConvertTextToDevicePath Converts text to a device path.
TheEFI_DEVICE_PATH_FROM_TEXT_PROTOCOL provides common utilities for converting text to device paths
and device nodes.
10.6.5.2 EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL.ConvertTextToDeviceNode()
Summary
Convert text to the binary representation of a device node.
Prototype
typedef
(EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_NODE) (
IN CONST CHAR16 * TextDeviceNode
);
TextDeviceNode TextDeviceNode points to the text representation of a device node. Conversion starts with the ﬁrst
character and continues until the ﬁrst non-device node character.
This function converts text to its binary device node representation and copies it into an allocated buffer.
10.6. EFI Device Path Display Format Overview 323Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Returns
This function returns a pointer to the EFI device node or NULL if TextDeviceNode is NULL or there was insufﬁcient
memory.
10.6.5.3 EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL.ConvertTextToDevicePath(
Summary
Convert a text to its binary device path representation.
Prototype
typedef
(EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_PATH) (
IN CONST CHAR16 * TextDevicePath
);
TextDevicePath TextDevicePath points to the text representation of a device path. Conversion starts with the ﬁrst
character and continues until the ﬁrst non-device path character.
This function converts text to its binary device path representation and copies it into an allocated buffer.
Returns
This function returns a pointer to the allocated device path or NULL if TextDevicePath is NULL or there was insufﬁ-
cient memory.
10.6. EFI Device Path Display Format Overview 324CHAPTER
ELEVEN
PROTOCOLS — UEFI DRIVER MODEL
EFI drivers that follow the UEFI Driver Model are not allowed to search for controllers to manage. When a speciﬁc
controller is needed, the EFI boot service EFI_BOOT_SERVICES.ConnectController() is used along with the EFI
Driver Binding Protocol services to identify the best drivers for a controller. Once ConnectController() has identiﬁed
the best drivers for a controller, the start service in the EFI_DRIVER_BINDING_PROTOCOL is used by ConnectCon-
troller() to start each driver on the controller. Once a controller is no longer needed, it can be released with the EFI
boot service EFI_BOOT_SERVICES.DisconnectController() .DisconnectController() calls the stop service in each
EFI_DRIVER_BINDING_PROTOCOL to stop the controller.
The driver initialization routine of an UEFI driver is not allowed to touch any device hardware. Instead, it just installs
an instance of the EFI_DRIVER_BINDING_PROTOCOL on the ImageHandle of the UEFI driver. The test to deter-

ELEVEN
mine if a driver supports a given controller must be performed in as little time as possible without causing any side
effects on any of the controllers it is testing. As a result, most of the controller initialization code is present in the start
and stop services of the EFI_DRIVER_BINDING_PROTOCOL .
11.1 EFI Driver Binding Protocol
This section provides a detailed description of the EFI_DRIVER_BINDING_PROTOCOL . This protocol is produced
by every driver that follows the UEFI Driver Model, and it is the central component that allows drivers and controllers
to be managed. It provides a service to test if a speciﬁc controller is supported by a driver, a service to start managing a
controller, and a service to stop managing a controller. These services apply equally to drivers for both bus controllers
and device controllers.
11.1.1 EFI_DRIVER_BINDING_PROTOCOL
Summary
Provides the services required to determine if a driver supports a given controller. If a controller is supported, then it
also provides routines to start and stop the controller.
GUID
#define EFI_DRIVER_BINDING_PROTOCOL_GUID \
{0x18A031AB,0xB443,0x4D1A,\
{0xA5,0xC0,0x0C,0x09,0x26,0x1E,0x9F,0x71}}
typedef struct \_EFI_DRIVER_BINDING_PROTOCOL {
EFI_DRIVER_BINDING_PROTOCOL_SUPPORTED Supported;
EFI_DRIVER_BINDING_PROTOCOL_START Start;
325Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_DRIVER_BINDING_PROTOCOL_STOP Stop;
EFI__HANDLE ImageHandle;
EFI_HANDLE DriverBindingHandle;
} EFI_DRIVER_BINDING_PROTOCOL;
Supported Tests to see if this driver supports a given controller. This service is called by the EFI boot service
EFI_BOOT_SERVICES.ConnectController() . In order to make drivers as small as possible, there are a few
calling restrictions for this service. ConnectController() must follow these calling restrictions. If any other agent
wishes to call EFI_DRIVER_BINDING_PROTOCOL.Supported() it must also follow these calling restrictions.
See the Supported() function description.
Start Starts a controller using this driver. This service is called by the EFI boot service ConnectController(). In order
to make drivers as small as possible, there are a few calling restrictions for this service. ConnectController() must
follow these calling restrictions. If any other agent wishes to call EFI_DRIVER_BINDING_PROTOCOL.Start()
it must also follow these calling restrictions. See the Start() function description.
Stop Stops a controller using this driver. This service is called by the EFI boot service
EFI_BOOT_SERVICES.DisconnectController() . In order to make drivers as small as possible, there are
a few calling restrictions for this service. DisconnectController() must follow these calling restrictions. If
any other agent wishes to call EFI_DRIVER_BINDING_PROTOCOL.Stop() it must also follow these calling
restrictions. See the Stop() function description.
Version The version number of the UEFI driver that produced the EFI_DRIVER_BINDING_PROTOCOL. This ﬁeld
is used by the EFI boot service ConnectController() to determine the order that driver’s Supported() service
will be used when a controller needs to be started. EFI Driver Binding Protocol instances with higher Version
values will be used before ones with lower Version values. The Version values of 0x0-0x0f and 0xfffffff0-
0xffffffff are reserved for platform/OEM speciﬁc drivers. The Version values of 0x10-0xffffffef are reserved for
IHV-developed drivers.
ImageHandle The image handle of the UEFI driver that produced this instance of the
DriverBindingHandle The handle on which this instance of the EFI_DRIVER_BINDING_PROTOCOL is installed.
In most cases, this is the same handle as ImageHandle. However, for UEFI drivers that produce more than one
instance of the EFI_DRIVER_BINDING_PROTOCOL, this value may not be the same as ImageHandle.
TheEFI_DRIVER_BINDING_PROTOCOL provides a service to determine if a driver supports a given controller. If
a controller is supported, then it also provides services to start and stop the controller. All UEFI drivers are required
to be reentrant so they can manage one or more controllers. This requires that drivers not use global variables to
store device context. Instead, they must allocate a separate context structure per controller that the driver is managing.
Bus drivers must support starting and stopping the same bus multiple times, and they must also support starting and
stopping all of their children, or just a subset of their children.
11.1. EFI Driver Binding Protocol 326Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.1.2 EFI_DRIVER_BINDING_PROTOCOL.Supported()
Summary
Tests to see if this driver supports a given controller. If a child device is provided, it further tests to see if this driver
supports creating a handle for the speciﬁed child device.
Prototype
typedef
(EFIAPI *EFI_DRIVER_BINDING_PROTOCOL_SUPPORTED) (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
);
This A pointer to the EFI Driver Binding Protocol instance.
ControllerHandle The handle of the controller to test. This handle must support a protocol interface that supplies
an I/O abstraction to the driver. Sometimes just the presence of this I/O abstraction is enough for the driver to
determine if it supports ControllerHandle. Sometimes, the driver may use the services of the I/O abstraction to
determine if this driver supports ControllerHandle.
RemainingDevicePath A pointer to the remaining portion of a device path. For bus drivers, if this parameter is not
NULL, then the bus driver must determine if the bus controller speciﬁed by ControllerHandle and the child
controller speciﬁed by RemainingDevicePath are both supported by this bus driver.
This function checks to see if the driver speciﬁed by This supports the device speciﬁed by ControllerHan-
dle. Drivers will typically use the device path attached to ControllerHandle and/or the services from the
bus I/O abstraction attached to ControllerHandle to determine if the driver supports ControllerHandle . This
function may be called many times during platform initialization. In order to reduce boot times, the tests
performed by this function must be very small, and take as little time as possible to execute. This func-
tion must not change the state of any hardware devices, and this function must be aware that the device
speciﬁed by ControllerHandle may already be managed by the same driver or a different driver. This func-
tion must match its calls to EFI_BOOT_SERVICES.AllocatePages() with EFI_BOOT_SERVICES.FreePages()
, EFI_BOOT_SERVICES.AllocatePool() with EFI_BOOT_SERVICES.FreePool() , and
EFI_BOOT_SERVICES.OpenProtocol() with EFI_BOOT_SERVICES.CloseProtocol() . Since ControllerHandle
may have been previously started by the same driver, if a protocol is already in the opened state, then it must not
be closed with CloseProtocol() . This is required to guarantee the state of ControllerHandle is not modiﬁed by this
function.
If any of the protocol interfaces on the device speciﬁed by ControllerHandle that are required by the driver speciﬁed
by This are already open for exclusive access by a different driver or application, then EFI_ACCESS_DENIED is
returned.
If any of the protocol interfaces on the device speciﬁed by ControllerHandle that are required by the driver spec-
iﬁed by This are already opened by the same driver, then EFI_ALREADY_STARTED is returned. However, if the
driver speciﬁed by This is a bus driver, then it is not an error, and the bus driver should continue with its test of
ControllerHandle andRemainingDevicePath . This allows a bus driver to create one child handle on the ﬁrst call
toEFI_DRIVER_BINDING_PROTOCOL.Supported() andEFI_DRIVER_BINDING_PROTOCOL.Start() , and create
additional child handles on additional calls to Supported() andStart() .This also allows a bus driver to create no child
handle on the ﬁrst call to Supported() andStart() by specifying an End of Device Path Node RemainingDevicePath ,
and create additional child handles on additional calls to Supported() andStart() .
If ControllerHandle is not supported by This, then EFI_UNSUPPORTED is returned.
11.1. EFI Driver Binding Protocol 327Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If This is a bus driver that creates child handles with an EFI Device Path Protocol , then ControllerHandle must support
theEFI_DEVICE_PATH_PROTOCOL . If it does not, then EFI_UNSUPPORTED is returned.
If ControllerHandle is supported by This, and This is a device driver, then EFI_SUCCESS is returned.
If ControllerHandle is supported by This, and This is a bus driver, and RemainingDevicePath is NULL or the ﬁrst

Device Path Node is the End of Device Path Node, then EFI_SUCCESS is returned.
If ControllerHandle is supported by This, and This is a bus driver, and RemainingDevicePath is not NULL , then
RemainingDevicePath must be analyzed. If the ﬁrst node of RemainingDevicePath is the End of Device Path Node
or an EFI Device Path node that the bus driver recognizes and supports, then EFI_SUCCESS is returned. Otherwise,
EFI_UNSUPPORTED is returned.
The Supported() function is designed to be invoked from the EFI boot service
EFI_BOOT_SERVICES.ConnectController() . As a result, much of the error checking on the parameters to
Supported() has been moved into this common boot service. It is legal to call Supported() from other locations, but
the following calling restrictions must be followed or the system behavior will not be deterministic.
ControllerHandle must be a valid EFI_HANDLE . If RemainingDevicePath is not NULL , then it must be a pointer to
a naturally aligned EFI_DEVICE_PATH_PROTOCOL .
EFI_SUCCESS The device speciﬁed by ControllerHandle and RemainingDevicePath is sup-
ported by the driver speciﬁed by This.
EFI_ALREADY_STARTED The device speciﬁed by ControllerHandle and RemainingDevicePath is al-
ready being managed by the driver speciﬁed by This.
EFI_ACCESS_DENIED The device speciﬁed by ControllerHandle and RemainingDevicePath is al-
ready being managed by a different driver or an application that requires
exclusive access.
EFI_UNSUPPORTED The device speciﬁed by ControllerHandle and RemainingDevicePath is not
supported by the driver speciﬁed by This.
Examples
EFI_HANDLE DriverImageHandle;
EFI_DRIVER_BINDING_PROTOCOL *DriverBinding;
//
// Use the DriverImageHandle to get the Driver Binding protocol instance
//
DriverImageHandle,
&gEfiDriverBindingProtocolGuid,
&DriverBinding,
NULL,
);
}
//
// EXAMPLE #1
11.1. EFI Driver Binding Protocol 328Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// Use the Driver Binding Protocol instance to test to see ifthe
// driver specified by DriverImageHandle supports the controller
// specified by ControllerHandle
//
Status = DriverBinding->Supported (
DriverBinding,
NULL
);
//
// EXAMPLE #2
//
// The RemainingDevicePath parameter can be used to initialize only
// the minimum devices required to boot. For example, maybe we only
// want to initialize 1 hard disk on a SCSI channel. If DriverImageHandle
//isa SCSI Bus Driver, andControllerHandle isa SCSI Controller, and
// we only want to create a child handle forPUN=3andLUN=0, then the
// RemainingDevicePath would be SCSI(3,0)/END. The following example
// would returnEFI_SUCCESS ifthe SCSI driver supports creating the
// child handle forPUN=3, LUN=0. Otherwise it would returnan error.
//
RemainingDevicePath
);
Pseudo Code
Listed below are the algorithms for the EFI_DRIVER_BINDING_PROTOCOL.Supported() function for three dif-
ferent types of drivers. How the EFI_DRIVER_BINDING_PROTOCOL.Start() function of a driver is implemented
can affect how the Supported() function is implemented. All of the services in the EFI Driver Binding Protocol
need to work together to make sure that all resources opened or allocated in Supported() andStart() are released in
EFI_DRIVER_BINDING_PROTOCOL.Stop()
The ﬁrst algorithm is a simple device driver that does not create any additional handles. It only attaches one or more
protocols to an existing handle. The second is a bus driver that always creates all of its child handles on the ﬁrst call to
Start() . The third is a more advanced bus driver that can either create one child handles at a time on successive calls
toStart() , or it can create all of its child handles or all of the remaining child handles in a single call to Start() .
Device Driver:
1. Ignore the parameter RemainingDevicePath .
2. Open all required protocols with EFI_BOOT_SERVICES.OpenProtocol() . A standard driver should use an
Attribute ofEFI_OPEN_PROTOCOL_BY_DRIVER . If this driver needs exclusive access to a protocol interface,
and it requires any drivers that may be using the protocol interface to disconnect, then the driver should use an
Attribute ofEFI_OPEN_PROTOCOL_BY_DRIVER | EFI_OPEN_PROTOCOL_EXCLUSIVE .
3. If any of the calls to OpenProtocol() in (2) returned an error, then close all of the protocols opened in (2)
with EFI_BOOT_SERVICES.CloseProtocol() , and return the status code from the call to OpenProtocol() that
returned an error.
4. Use the protocol instances opened in (2) to test to see if this driver supports the controller. Sometimes, just the
presence of the protocols is enough of a test. Other times, the services of the protocols opened in (2) are used to
11.1. EFI Driver Binding Protocol 329Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
further check the identity of the controller. If any of these tests fails, then close all the protocols opened in (2)
with CloseProtocol() and return EFI_UNSUPPORTED .
5. Close all protocols opened in (2) with CloseProtocol() .
6. Return EFI_SUCCESS .
Bus Driver that creates all of its child handles on the ﬁrst call to Start():
1. Check the contents of the ﬁrst Device Path Node of RemainingDevicePath to make sure it is the End of
Device Path Node or a legal Device Path Node for this bus driver’s children. If it is not, then return
EFI_UNSUPPORTED .
4. Use the protocol instances opened in (2) to test to see if this driver supports the controller. Sometimes, just
the presence of the protocols is enough of a test. Other times, the services of the protocols opened in (2)
are used to further check the identity of the controller. If any of these tests fails, then close all the protocols
opened in (2) with CloseProtocol() and return EFI_UNSUPPORTED . #. Close all protocols opened in (2) with
CloseProtocol() .
5. Return EFI_SUCCESS .
Bus Driver that is able to create all or one of its child handles on each call to Start():
2. Open all required protocols with OpenProtocol() . A standard driver should use an Attribute of
EFI_OPEN_PROTOCOL_BY_DRIVER . If this driver needs exclusive access to a protocol interface, and it re-
quires any drivers that may be using the protocol interface to disconnect, then the driver should use an Attribute
ofEFI_OPEN_PROTOCOL_BY_DRIVER | EFI_OPEN_PROTOCOL_EXCLUSIVE .
3. If any of the calls to OpenProtocol() in (2) failed with an error other than EFI_ALREADY_STARTED , then
close all of the protocols opened in (2) that did not return EFI_ALREADY_STARTED with CloseProtocol() , and
return the status code from the OpenProtocol() call that returned an error.
that did not return EFI_ALREADY_STARTED with CloseProtocol() and return EFI_UNSUPPORTED .
5. Close all protocols opened in (2) that did not return EFI_ALREADY_STARTED with CloseProtocol() .
Listed below is sample code of the EFI_DRIVER_BINDING_PROTOCOL.Supported() function of device driver for
a device on the XYZ bus. The XYZ bus is abstracted with the EFI_XYZ_IO_PROTOCOL . Just the presence of the
EFI_XYZ_IO_PROTOCOL on ControllerHandle is enough to determine if this driver supports ControllerHandle. The
gBSvariable is initialized in this driver’s entry point.:ref: eﬁ-system-table .
11.1. EFI Driver Binding Protocol 330Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
AbcSupported (

)
{
&XyzIo,
);
}
gBS->CloseProtocol (
);
}
11.1.3 EFI_DRIVER_BINDING_PROTOCOL.Start()
Summary
Starts a device controller or a bus controller. The Start() and eﬁ-driver-binding-protocol-stop-protocols-ueﬁ-driver-
model mirror each other.
Prototype
typedef
(EFIAPI *EFI_DRIVER_BINDING_PROTOCOL_START) (
);
This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
ControllerHandle The handle of the controller to start. This handle must support a protocol interface that supplies
an I/O abstraction to the driver.
11.1. EFI Driver Binding Protocol 331Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
RemainingDevicePath A pointer to the remaining portion of a device path. For a bus driver, if this parameter is
NULL, then handles for all the children of Controller are created by this driver.
If this parameter is not NULL and the ﬁrst Device Path Node is not the End of Device Path Node, then only the
handle for the child device speciﬁed by the ﬁrst Device Path Node of RemainingDevicePath is created by this
driver.
If the ﬁrst Device Path Node of RemainingDevicePath is the End of Device Path Node, no child handle is created
by this driver.
This function starts the device speciﬁed by Controller with the driver speciﬁed by
This. Whatever resources are allocated in Start() must be freed in Stop() . For ex-
ample, every EFI_BOOT_SERVICES.AllocatePool() , EFI_BOOT_SERVICES.AllocatePages() ,
EFI_BOOT_SERVICES.OpenProtocol() , and EFI_BOOT_SERVICES.InstallProtocolInterface() in Start()
must be matched with a EFI_BOOT_SERVICES.FreePool() ,EFI_BOOT_SERVICES.FreePages() ,
EFI_BOOT_SERVICES.CloseProtocol() , and EFI_BOOT_SERVICES.UninstallProtocolInterface() inStop()
.
If Controller is started, then EFI_SUCCESS is returned.
IfController could not be started, but can potentially be repaired with conﬁguration or repair op-
erations using the EFI_DRIVER_HEALTH_PROTOCOL and this driver produced an instance of the
EFI_DRIVER_HEALTH_PROTOCOL forController , then return EFI_SUCCESS .
IfController cannot be started due to a device error and the driver does not produce the
EFI_DRIVER_HEALTH_PROTOCOL forController , then return EFI_DEVICE_ERROR .
If the driver does not support Controller then EFI_DEVICE_ERROR is returned. This condition will only be met if
Supported() returns EFI_SUCCESS and a more extensive supported check in Start() fails.
If there are not enough resources to start the device or bus speciﬁed by Controller , then EFI_OUT_OF_RESOURCES
If the driver speciﬁed by This is a device driver, then RemainingDevicePath is ignored.
If the driver speciﬁed by This is a bus driver, and RemainingDevicePath isNULL , then all of the children of Controller
are discovered and enumerated, and a device handle is created for each child.
If the driver speciﬁed by This is a bus driver, and RemainingDevicePath is not NULL and begins with
the End of Device Path node, then the driver must not enumerate any of the children of Controller
nor create any child device handle. Only the controller initialization should be performed. If the
driver implements EFI_DRIVER_DIAGNOSTICS2_PROTOCOL ,EFI_COMPONENT_NAME2_PROTOCOL
, EFI_SERVICE_BINDING_PROTOCOL , EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL , or
EFI_DRIVER_HEALTH_PROTOCOL , the driver still should install the implemented protocols. If the driver
supports EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL, the driver still should retrieve and
process the conﬁguration information.
If the driver speciﬁed by This is a bus driver that is capable of creating one child handle at a time and RemainingDe-
vicePath is not NULL and does not begin with the End of Device Path node, then an attempt is made to create the
device handle for the child device speciﬁed by RemainingDevicePath. Depending on the bus type, all of the child
devices may need to be discovered and enumerated, but at most only the device handle for the one child speciﬁed by
RemainingDevicePath shall be created.
TheStart() function is designed to be invoked from the EFI boot service EFI_BOOT_SERVICES.ConnectController()
(Section 7.3.12). As a result, much of the error checking on the parameters to Start() has been moved into this common
boot service. It is legal to call Start() from other locations, but the following calling restrictions must be followed or
the system behavior will not be deterministic:
•ControllerHandle must be a valid EFI_HANDLE .
11.1. EFI Driver Binding Protocol 332Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• If RemainingDevicePath is not NULL , then it must be a pointer to a naturally aligned
EFI_DEVICE_PATH_PROTOCOL .
• Prior to calling Start() ,EFI_DRIVER_BINDING_PROTOCOL.Supported() function for the driver speci-
ﬁed by This must have been called with the same calling parameters, and Supported() must have returned
EFI_SUCCESS .
EFI_SUCCESS The device was started.
EFI_SUCCESS The device could not be started because the device needs to be conﬁgured
by the user or requires a repair operation, and the driver produced the Driver
Health Protocol that will return the required conﬁguration and repair oper-
ations for this device.
EFI_DEVICE_ERROR The driver does not produce the Driver Health Protocol and the device could
not be started due to a device error.
EFI_DEVICE_ERROR The driver produces the Driver Health Protocol, and the driver does not
support the device.
Examples
//
// Use the DriverImageHandle to get the Driver Binding Protocol instance
//
NULL,
);
if (EFI_ERROR (Status)) {
return Status;
}
//
//
// Use the Driver Binding Protocol instance to test to see if the
//
NULL
);
Status = DriverBinding->Start (
11.1. EFI Driver Binding Protocol 333Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NULL
);
}
//
//
// is a SCSI Bus Driver, and ControllerHandle is a SCSI Controller, and
// we only want to create a child handle for PUN=3 and LUN=0, then the
// would return EFI_SUCCESS if the SCSI driver supports creating the
// child handle for PUN=3, LUN=0. Otherwise it would return an error.
//
);
);
}
Listed below are the algorithms for the EFI_DRIVER_BINDING_PROTOCOL.Supported() function for three different
types of drivers. How the EFI_DRIVER_BINDING_PROTOCOL.Start() function of a driver is implemented can affect
how the EFI_DRIVER_BINDING_PROTOCOL.Supported() function is implemented. All of the services in the EFI
Driver Binding Protocol need to work together to make sure that all resources opened or allocated in Supported() and
Start() are released in EFI_DRIVER_BINDING_PROTOCOL.Stop() .
protocols to an existing handle. The second is a simple bus driver that always creates all of its child handles on the
ﬁrst call to Start() . It does not attach any additional protocols to the handle for the bus controller. The third is a more
advanced bus driver that can either create one child handles at a time on successive calls to Start() , or it can create all

of its child handles or all of the remaining child handles in a single call to Start() . Once again, it does not attach any
additional protocols to the handle for the bus controller.
1. Ignore the parameter RemainingDevicePath ..
Attribute ofEFI_OPEN_PROTOCOL_BY_DRIVER | EFI_OPEN_PROTOCOL_EXCLUSIVE . It must use the
same Attribute value that was used in Supported() .
11.1. EFI Driver Binding Protocol 334Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
4. Initialize the device speciﬁed by ControllerHandle . If the driver does not support the device speciﬁed
byControllerHandle , then close all of the protocols opened in (2) with CloseProtocol() , and return
EFI_DEVICE_ERROR . If the driver does support the device speciﬁed by ControllerHandle and an error is
detected, and that error can not be resolved with the EFI_DRIVER_HEALTH_PROTOCOL , then close all of
the protocols opened in (2) with CloseProtocol() , and return EFI_DEVICE_ERROR . If the driver does sup-
port the device speciﬁed by ControllerHandle and an error is detected, and that error can be resolved with the
EFI_DRIVER_HEALTH_PROTOCOL , then produce the EFI_DRIVER_HEALTH_PROTOCOL forController-
Handle and make sure EFI_SUCCESS is returned from Start() . In this case, depending on the type of error
detected, not all of the following steps may be completed
5. Allocate and initialize all of the data structures that thisdriver requires to manage the device speciﬁed
by*ControllerHandle* . This would include space for publicprotocols and space for any additional private
datastructures that are related to ControllerHandle . If anerror occurs allocating the resources, then close all of
theprotocols opened in (2) with CloseProtocol() , and return EFI_OUT_OF_RESOURCES .
6. Install all the new protocol interfaces onto ControllerHandle using
EFI_BOOT_SERVICES.InstallMultipleProtocolInterfaces() (Section 7.3.17). If an error occurs, close all
of the protocols opened in (1)with CloseProtocol() , and return the error from InstallMultipleProtocolInter-
faces() .
7. Return EFI_SUCCESS .
1. Ignore the parameter RemainingDevicePath . with the exception that if the ﬁrst Device Path Node is the End of
Device Path Node, skip steps 5-8.
2. Open all required protocols with EFI_BOOT_SERVICES.OpenProtocol() .A standard driver should use an At-
tribute ofEFI_OPEN_PROTOCOL_BY_DRIVER . If this driver needsexclusive access to a protocol interface,
and it requiresany drivers that may be using the protocol interface todisconnect, then the driver should use an
Attribute of*EFI_OPEN_PROTOCOL_BY_DRIVER | EFI_OPEN_PROTOCOL_EXCLUSIVE*. It must use
the same Attribute value that was used in Supported() EFI_DRIVER_BINDING_PROTOCOL.Supported() .
3. If any of the calls to OpenProtocol() in (2) returned anerror, then close all of the protocols opened in (2) with
EFI_BOOT_SERVICES.CloseProtocol() , and return the status code from the call to OpenProtocol() that re-
turned an error.
4. Initialize the device speciﬁed by ControllerHandle . Ifthe driver does not support the device speciﬁed
by*ControllerHandle* , then close all of the protocols openedin (2) with CloseProtocol() , and return
EFI_DEVICE_ERROR . If the driver does support the devicespeciﬁed by ControllerHandle and an error is
detected, and that error can not be resolved with the EFI_DRIVER_HEALTH_PROTOCOL , then close all
of theprotocols opened in (2) with CloseProtocol() , and return EFI_DEVICE_ERROR . If the driver does
support the devicespeciﬁed by ControllerHandle and an error is detected,and that error can be resolved with
theEFI_DRIVER_HEALTH_PROTOCOL , then produce the*EFI_DRIVER_HEALTH_PROTOCOL* for Con-
trollerHandle and make sure EFI_SUCCESS is returned from Start() . In this case, depending on the type of
error detected, not all ofthe following steps may be completed.
5. Discover all the child devices of the bus controller speciﬁed by ControllerHandle .
6. If the bus requires it, allocate resources to all the child devices of the bus controller speciﬁed by ControllerHan-
dle.
7. FOR each child C of ControllerHandle :
• Allocate and initialize all of the data structures that thisdriver requires to manage the child device C. This
wouldinclude space for public protocols and space for any additional private data structures that are related
11.1. EFI Driver Binding Protocol 335Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
to the child device C. If an error occurs allocating the resources,then close all of the protocols opened in
(2) with CloseProtocol() , and return EFI_OUT_OF_RESOURCES .
• If the bus driver creates device paths for the child devices, then create a device path for the child C
basedupon the device path attached to ControllerHandle .
• Initialize the child device C. If an error occurs, close all of the protocols opened in (2) with CloseProtocol()
, and return EFI_DEVICE_ERROR .
• Create a new handle for C, and install the protocol interfaces for child device C using
EFI_BOOT_SERVICES.InstallMultipleProtocolInterfaces() . This may include the EFI Device Path Pro-
tocol .
• Call OpenProtocol() on behalf of the child C with an Attribute of
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER .
8. END FOR
9. If the bus driver also produces protocols on ControllerHandle , then install all the new protocol interfaces onto
ControllerHandle using InstallMultipleProtocolInterfaces() . If an error occurs, close all of the protocols opened
in (2) with CloseProtocol() , and return the error from InstallMultipleProtocolInterfaces() .
10. Return EFI_SUCCESS .
1. Open all required protocols with EFI_BOOT_SERVICES.OpenProtocol() . A standard driver should use an
same Attribute value that was used in Supported() EFI_DRIVER_BINDING_PROTOCOL.Supported() .
2. If any of the calls to OpenProtocol() in (1) returned an error, then close all of the protocols opened in (1)
3. Initialize the device speciﬁed by ControllerHandle . If the driver does not support the device speciﬁed
byControllerHandle , then close all of the protocols opened in (1) with CloseProtocol() , and return
the protocols opened in (1) with CloseProtocol() , and return EFI_DEVICE_ERROR . If the driver does sup-
detected, not all of the following steps may be completed.
4. IF RemainingDevicePath is not NULL , THEN
a – C is the child device speciﬁed by RemainingDevicePath . If the ﬁrst Device Path Node is the End of Device
Path Node, proceed to step 6.
b – Allocate and initialize all of the data structures that this driver requires to manage the child device C. This
would include space for public protocols and space for any additional private data structures that are related to
the child device C. If an error occurs allocating the resources, then close all of the protocols opened in (1) with
CloseProtocol() , and return EFI_OUT_OF_RESOURCES .
c – If the bus driver creates device paths for the child devices, then create a device path for the child C based
upon the device path attached to ControllerHandle .
d – Initialize the child device C.
11.1. EFI Driver Binding Protocol 336Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
e – Create a new handle for C, and install the protocol interfaces for child device C using

EFI_BOOT_SERVICES.InstallMultipleProtocolInterfaces() . This may include the EFI Device Path Protocol .
f – Call OpenProtocol() on behalf of the child C with an Attribute of
ELSE
a – Discover all the child devices of the bus controller speciﬁed by ControllerHandle .
b – If the bus requires it, allocate resources to all the child devices of the bus controller speciﬁed by Controller-
Handle .
c – FOR each child C of ControllerHandle
Allocate and initialize all of the data structures that this driver requires to manage the child device C. This
If the bus driver creates device paths for the child devices, then create a device path for the child C based upon
the device path attached to ControllerHandle .
Initialize the child device C.
Create a new handle for C, and install the protocol interfaces for child device C using InstallMultipleProtocol-
Interfaces() . This may include the EFI_DEVICE_PATH_PROTOCOL .
Call EFI_BOOT_SERVICES.OpenProtocol() on behalf of the child C with an Attribute of *
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER* .
d – END FOR
5. END IF
6. If the bus driver also produces protocols on ControllerHandle , then install all the new protocol interfaces onto
Listed below is sample code of the EFI_DRIVER_BINDING_PROTOCOL.Start() function of a device driver for a
device on the XYZ bus. The XYZ bus is abstracted with the EFI_XYZ_IO_PROTOCOL . This driver does allow the
EFI_XYZ_IO_PROTOCOL to be shared with other drivers, and just the presence of the EFI_XYZ_IO_PROTOCOL
on ControllerHandle is enough to determine if this driver supports ControllerHandle. This driver installs the
EFI_ABC_IO_PROTOCOL on ControllerHandle. The gBS variable is initialized in this driver’s entry point as shown
in the UEFI Driver Model examples in UEFI Driver Model .
extern EFI_GUID gEfiAbcIoProtocol;
AbcStart (
)
{
11.1. EFI Driver Binding Protocol 337Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_ABC_DEVICE AbcDevice;
//
// Open the Xyz I/O Protocol that this driver consumes
//
&XyzIo,
);
}
//
// Allocate andzero a private data structure forthe Abc device.
//
sizeof (EFI_ABC_DEVICE),
&AbcDevice
);
goto ErrorExit;
}
ZeroMem (AbcDevice, sizeof (EFI_ABC_DEVICE));
//
// Initialize the contents of the private data structure forthe Abc device.
// This includes the XyzIo protocol instance andother private data fields
//andthe EFI_ABC_IO_PROTOCOL instance that will be installed.
//
AbcDevice->Signature = EFI_ABC_DEVICE_SIGNATURE;
AbcDevice->XyzIo = XyzIo;
AbcDevice->PrivateData1 = PrivateValue1;
AbcDevice->PrivateData2 = PrivateValue2;
. . .
AbcDevice->PrivateDataN = PrivateValueN;
AbcDevice->AbcIo.Revision = EFI_ABC_IO_PROTOCOL_REVISION;
AbcDevice->AbcIo.Func1 = AbcIoFunc1;
AbcDevice->AbcIo.Func2 = AbcIoFunc2;
. . .
AbcDevice->AbcIo.FuncN = AbcIoFuncN;
AbcDevice->AbcIo.Data1 = Value1;
AbcDevice->AbcIo.Data2 = Value2;
. . .
AbcDevice->AbcIo.DataN = ValueN;
//
// Install protocol interfaces forthe ABC I/O device.
//
11.1. EFI Driver Binding Protocol 338Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Status = gBS->InstallMultipleProtocolInterfaces (
&ControllerHandle,
&gEfiAbcIoProtocolGuid, &AbcDevice->AbcIo,
NULL
);
}
ErrorExit:
//
// When there isan error, the private data structures need to be freed and
// the protocols that were opened need to be closed.
//
if(AbcDevice != NULL) {
gBS->FreePool (AbcDevice);
}
&gEfiXyzIoProtocolGuid,
);
}
11.1.4 EFI_DRIVER_BINDING_PROTOCOL.Stop()
Summary
Stops a device controller or a bus controller. The EFI_DRIVER_BINDING_PROTOCOL.Start() andStop() services of
theEFI_DRIVER_BINDING_PROTOCOL.Stop() mirror each other.
Prototype
typedef
(EFIAPI *EFI_DRIVER_BINDING_PROTOCOL_STOP) (
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer OPTIONAL
);
This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. Type
EFI_DRIVER_BINDING_PROTOCOL is deﬁned in EFI Driver Binding Protocol .
ControllerHandle A handle to the device being stopped. The handle must support a bus speciﬁc I/O protocol for the
driver to use to stop the device.
NumberOfChildren The number of child device handles in ChildHandleBuffer.
ChildHandleBuffer An array of child handles to be freed. May be NULL if NumberOfChildren is 0.
11.1. EFI Driver Binding Protocol 339Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function performs different operations depending on the parameter NumberOfChildren. If NumberOfChil-
dren is not zero, then the driver speciﬁed by This is a bus driver, and it is being requested to free one or
more of its child handles speciﬁed by NumberOfChildren and ChildHandleBuffer. If all of the child handles
are freed, then EFI_SUCCESS is returned. If NumberOfChildren is zero, then the driver speciﬁed by This
is either a device driver or a bus driver, and it is being requested to stop the controller speciﬁed by Con-
trollerHandle. If ControllerHandle is stopped, then EFI_SUCCESS is returned. In either case, this function
is required to undo what was performed in Start() . Whatever resources are allocated in Start() must be freed
inStop() . For example, every EFI_BOOT_SERVICES.AllocatePool() ,EFI_BOOT_SERVICES.AllocatePages()
,EFI_BOOT_SERVICES.OpenProtocol() , and EFI_BOOT_SERVICES.InstallProtocolInterface() inStart()
.
If ControllerHandle cannot be stopped, then EFI_DEVICE_ERROR is returned. If, for some reason, there are not
enough resources to stop ControllerHandle, then EFI_OUT_OF_RESOURCES is returned.
The Stop() function is designed to be invoked from the EFI boot service
EFI_BOOT_SERVICES.DisconnectController() . As a result, much of the error checking on the parameters to
Stop() has been moved into this common boot service. It is legal to call Stop() from other locations, but the following
calling restrictions must be followed or the system behavior will not be deterministic.
•ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this same driver’s
EFI_DRIVER_BINDING_PROTOCOL.Start() function.
• The ﬁrst NumberOfChildren handles of ChildHandleBuffer must all be a valid EFI_HANDLE . In addi-
tion, all of these handles must have been created in this driver’s Start() function, and the Start() func-
tion must have called EFI_BOOT_SERVICES.OpenProtocol() onControllerHandle with an Attribute of
EFI_SUCCESS The device was stopped.
EFI_DEVICE_ERROR The device could not be stopped due to a device error.
Examples
EFI_HANDLE ChildHandle;
//
//
NULL,
);
11.1. EFI Driver Binding Protocol 340Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
}
//
// Use the Driver Binding Protocol instance to free the child
// specified by ChildHandle. Then, use the Driver Binding
// Protocol to stop ControllerHandle.
//
Status = DriverBinding->Stop (
1,
&ChildHandle
);

Examples
//
//
NULL,
);
}
//
//
1,
);
0,
NULL
);
1. Uninstall all the protocols that were installed onto ControllerHandle in
EFI_DRIVER_BINDING_PROTOCOL.Start() .
2. Close all the protocols that were opened on behalf of ControllerHandle inStart() .
3. Free all the structures that were allocated on behalf of ControllerHandle inStart() .
4. Return EFI_SUCCESS .
1. IF NumberOfChildren is zero THEN:
• Uninstall all the protocols that were installed onto ControllerHandle inStart() .
• Close all the protocols that were opened on behalf of ControllerHandle inStart() .
• Free all the structures that were allocated on behalf of ControllerHandle inStart() .
2. ELSE
• FOR each child C in ChildHandleBuffer : Uninstall all the protocols that were installed onto C in Start()
. Close all the protocols that were opened on behalf of C in Start() . Free all the structures that were
allocated on behalf of C in Start() .
• END FOR
3. END IF
4. Return EFI_SUCCESS.
Listed below is sample code of the EFI_DRIVER_BINDING_PROTOCOL.Stop() function of a device driver for a
11.1. EFI Driver Binding Protocol 341Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_ABC_IO_PROTOCOL on ControllerHandle in EFI_DRIVER_BINDING_PROTOCOL.Start() . The gBSvariable
is initialized in this driver’s entry point.:ref: eﬁ-system-table_eﬁ_system_table . extern EFI_GUID
AbcStop (
)
{
EFI_ABC_IO AbcIo;
//
// Get our context back
//
&gEfiAbcIoProtocolGuid,
&AbcIo,
);
return EFI_UNSUPPORTED;
}
//
// Use Containment Record Macro to get AbcDevice structure from
// a pointer to the AbcIo structure within the AbcDevice structure.
//
AbcDevice = ABC_IO_PRIVATE_DATA_FROM_THIS (AbcIo);
//
// Uninstall the protocol installed in Start()
//
NULL
);
//
// Close the protocol opened in Start()
//
11.1. EFI Driver Binding Protocol 342Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
//
// Free the structure allocated in Start().
//
}
}
11.2 EFI Platform Driver Override Protocol
This section provides a detailed description of the EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL . This pro-
tocol can override the default algorithm for matching drivers to controllers.
EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL
Summary
This protocol matches one or more drivers to a controller. A platform driver produces this protocol, and it is installed
on a separate handle. This protocol is used by the EFI_BOOT_SERVICES.ConnectController() boot service to select
the best driver for a controller. All of the drivers returned by this protocol have a higher precedence than drivers found
from an EFI Bus Speciﬁc Driver Override Protocol or drivers found from the general UEFI driver Binding search
algorithm. If more than one driver is returned by this protocol, then the drivers are returned in order from highest
precedence to lowest precedence.
GUID
#define EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL_GUID \
{0x6b30c738,0xa391,0x11d4,\
{0x9a,0x3b,0x00,0x90,0x27,0x3f,0xc1,0x4d}}
typedef struct _EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL {
EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER GetDriver;
EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER_PATH GetDriverPath;
EFI_PLATFORM_DRIVER_OVERRIDE_DRIVER_LOADED DriverLoaded;
} EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL;
GetDriver Retrieves the image handle of a platform override driver for a controller in the system. See the
EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriver() function description.
GetDriverPath Retrieves the device path of a platform override driver for a controller in the system. See the Get-
DriverPath() EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriverPath() function description.
DriverLoaded This function is used after a driver has been loaded using a device path returned by
EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriverPath() This function associates a device path
to an image handle, so the image handle can be returned the next time that GetDriver() is called for the same con-
troller. See the DriverLoaded() EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.DriverLoaded() func-
tion description.
11.2. EFI Platform Driver Override Protocol 343Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL is used by the EFI boot service
EFI_BOOT_SERVICES.ConnectController() to determine if there is a platform speciﬁc driver override for a
controller that is about to be started. The bus drivers in a platform will use a bus deﬁned matching algorithm for
matching drivers to controllers. This protocol allows the platform to override the bus driver’s default driver matching
algorithm. This protocol can be used to specify the drivers for on-board devices whose drivers may be in a system
ROM not directly associated with the on-board controller, or it can even be used to manage the matching of drivers
and controllers in add-in cards. This can be very useful if there are two adapters that are identical except for the
revision of the driver in the adapter’s ROM. This protocol, along with a platform conﬁguration utility, could specify
which of the two drivers to use for each of the adapters.
The drivers that this protocol returns can be either in the form of an image handle or a device path.
EFI_BOOT_SERVICES.ConnectController() can only use image handles, so ConnectController() is required to use the
EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriver() . A different component, such as the Boot Man-
ager, will have to use the GetDriverPath() EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriverPath() ser-
vice to retrieve the list of drivers that need to be loaded from I/O devices. Once a driver has been loaded and started, this
same component can use the DriverLoaded() EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.DriverLoaded()
service to associate the device path of a driver with the image handle of the loaded driver. Once this association
has been established, the image handle can then be returned by the GetDriver() service the next time it is called by
ConnectController() .
11.2.1 EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriver()
Summary
Retrieves the image handle of the platform override driver for a controller in the system.
Prototype
typedef
(EFIAPI *EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER) (
IN EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
);
This A pointer to the EFI Platform Driver Override Protocol instance.
ControllerHandle The device handle of the controller to check if a driver override exists.
DriverImageHandle On input, a pointer to the previous driver image handle returned by GetDriver(). On output,
a pointer to the next driver image handle. Passing in a NULL, will return the ﬁrst driver image handle for
This function is used to retrieve a driver image handle that is selected in a platform speciﬁc manner. The ﬁrst driver
image handle is retrieved by passing in a DriverImageHandle value of NULL . This will cause the ﬁrst driver image
handle to be returned in DriverImageHandle. On each successive call, the previous value of DriverImageHandle
must be passed in. If a call to this function returns a valid driver image handle, then EFI_SUCCESS is returned.
This process is repeated until EFI_NOT_FOUND is returned. If a DriverImageHandle is passed in that was not
returned on a prior call to this function, then EFI_INVALID_PARAMETER is returned. If ControllerHandle is NULL ,
then EFI_INVALID_PARAMETER is returned. The ﬁrst driver image handle has the highest precedence, and the last
11.2. EFI Platform Driver Override Protocol 344Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

driver image handle has the lowest precedence. This ordered list of driver image handles is used by the boot service
EFI_BOOT_SERVICES.ConnectController() to search for the best driver for a controller.
EFI_SUCCESS The driver override for ControllerHandle was returned in DriverImageHan-
dle.
EFI_NOT_FOUND A driver override for ControllerHandle was not found.
EFI_INV ALID_PARAMETER The handle speciﬁed by ControllerHandle is not a valid handle.
EFI_INV ALID_PARAMETER DriverImageHandle is not a handle that was returned on a previous call to
11.2.2 EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriverPath()
Summary
Retrieves the device path of the platform override driver for a controller in the system.
Prototype
typedef
(EFIAPI *EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER_PATH) (
IN OUT EFI_DEVICE_PATH_PROTOCOL **DriverImagePath
);
DriverImagePath On input, a pointer to the previous driver device path returned by GetDriverPath(). On output, a
pointer to the next driver device path. Passing in a pointer to NULL, will return the ﬁrst driver device path for
This function is used to retrieve a driver device path that is selected in a platform speciﬁc manner. The ﬁrst driver
device path is retrieved by passing in a DriverImagePath value that is a pointer to NULL . This will cause the ﬁrst
driver device path to be returned in DriverImagePath. On each successive call, the previous value of DriverImagePath
must be passed in. If a call to this function returns a valid driver device path, then EFI_SUCCESS is returned.
This process is repeated until EFI_NOT_FOUND is returned. If a DriverImagePath is passed in that was not re-
turned on a prior call to this function, then EFI_INVALID_PARAMETER is returned. If ControllerHandle is NULL ,
then EFI_INVALID_PARAMETER is returned. The ﬁrst driver device path has the highest precedence, and the last
driver device path has the lowest precedence. This ordered list of driver device paths is used by a platform speciﬁc
component, such as the EFI Boot Manager, to load and start the platform override drivers by using the EFI boot ser-
vices EFI_BOOT_SERVICES.LoadImage() andEFI_BOOT_SERVICES.StartImage() . Each time one of these drivers
is loaded and started, the DriverLoaded() EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.DriverLoaded() ser-
vice is called.
EFI_SUCCESS The driver override for ControllerHandle was returned in DriverImagePath.
11.2. EFI Platform Driver Override Protocol 345Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 11.5 – continued from previous page
EFI_UNSUPPORTED The operation is not supported.
EFI_INV ALID_PARAMETER DriverImagePath is not a device path that was returned on a previous call to
GetDriverPath().
11.2.3 EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.DriverLoaded()
Summary
Used to associate a driver image handle with a device path that was returned on a prior call to the GetDriverPath()
EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriverPath() service. This driver image handle will then
be available through the EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriver() service.
Prototype
typedef
(EFIAPI *EFI_PLATFORM_DRIVER_OVERRIDE_DRIVER_LOADED) (
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath,
IN EFI_HANDLE DriverImageHandle
);
ControllerHandle The device handle of a controller. This must match the controller handle that was used in a prior
call to GetDriver() to retrieve DriverImagePath.
DriverImagePath A pointer to the driver device path that was returned in a prior call to GetDriverPath().
DriverImageHandle The driver image handle that was returned by EFI_BOOT_SERVICES.LoadImage() when the
driver speciﬁed by DriverImagePath was loaded into memory.
This function associates the image handle speciﬁed by DriverImageHandle with the device path of a driver speciﬁed
by DriverImagePath. DriverImagePath must be a value that was returned on a prior call to GetDriverPath() for the
controller speciﬁed by ControllerHandle. Once this association has been established, then the service GetDriver()
must return DriverImageHandle as one of the override drivers for the controller speciﬁed by ControllerHandle.
If the association between the image handle speciﬁed by DriverImageHandle and the device path speciﬁed by Driver-
ImagePath is established for the controller speciﬁed by ControllerHandle, then EFI_SUCCESS is returned. If Con-
trollerHandle is NULL , or DriverImagePath is not a valid device path, or DriverImageHandle is NULL , then
EFI_INVALID_PARAMETER is returned. If DriverImagePath is not a device path that was returned on a prior call
toEFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL.GetDriver() for the controller speciﬁed by ControllerHan-
dle, then EFI_NOT_FOUND is returned.
EFI_SUCCESS The association between DriverImagePath and DriverImageHandle was es-
tablished for the controller speciﬁed by ControllerHandle.
11.2. EFI Platform Driver Override Protocol 346Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 11.6 – continued from previous page
EFI_NOT_FOUND DriverImagePath is not a device path that was returned on a prior call to
GetDriverPath() for the controller speciﬁed by ControllerHandle.
EFI_INV ALID_PARAMETER ControllerHandle is not a valid device handle.
EFI_INV ALID_PARAMETER DriverImagePath is not a valid device path.
EFI_INV ALID_PARAMETER DriverImageHandle is not a valid image handle.
11.3 EFI Bus Speciﬁc Driver Override Protocol
This section provides a detailed description of the EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL . Bus
drivers that have a bus speciﬁc algorithm for matching drivers to controllers are required to produce this protocol for
each controller. For example, a PCI Bus Driver will produce an instance of this protocol for every PCI controller that
has a PCI option ROM that contains one or more UEFI drivers. The protocol instance is attached to the handle of the
PCI controller.
11.3.1 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL
Summary
This protocol matches one or more drivers to a controller. This protocol is produced by a bus driver, and it is installed
on the child handles of buses that require a bus speciﬁc algorithm for matching drivers to controllers. This protocol
is used by the EFI_BOOT_SERVICES.ConnectController() boot service to select the best driver for a controller. All
of the drivers returned by this protocol have a higher precedence than drivers found in the general EFI Driver Binding
search algorithm, but a lower precedence than those drivers returned by the EFI Platform Driver Override Protocol. If
more than one driver image handle is returned by this protocol, then the drivers image handles are returned in order
from highest precedence to lowest precedence.
GUID
#define EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL_GUID \
{0x3bc1b285,0x8a15,0x4a82,\
{0xaa,0xbf,0x4d,0x7d,0x13,0xfb,0x32,0x65}}
typedef struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL {
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_GET_DRIVER GetDriver;
} EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL;
GetDriver Uses a bus speciﬁc algorithm to retrieve a driver image handle for a controller. See the
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL.GetDriver() function description.
TheEFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL provides a mechanism for bus drivers to override the
default driver selection performed by the ConnectController() boot service. This protocol is attached to the handle
of a child device after the child handle is created by the bus driver. The service in this protocol can return a bus
speciﬁc override driver to ConnectController() .ConnectController() must call this service until all of the bus speciﬁc
override drivers have been retrieved. ConnectController() uses this information along with the EFI Platform Driver
Override Protocol and all of the EFI Driver Binding protocol instances to select the best drivers for a controller. Since
a controller can be managed by more than one driver, this protocol can return more than one bus speciﬁc override
driver.
11.3. EFI Bus Speciﬁc Driver Override Protocol 347Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.3.2 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL.GetDriver()
Summary

driver.
Summary
Uses a bus speciﬁc algorithm to retrieve a driver image handle for a controller.
Prototype
typedef
(EFIAPI *EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_GET_DRIVER) (
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
);
This A pointer to the EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL instance.
DriverImageHandle On input, a pointer to the previous driver image handle returned by GetDriver(). On output, a
pointer to the next driver image handle. Passing in a NULL, will return the ﬁrst driver image handle.
This function is used to retrieve a driver image handle that is selected in a bus speciﬁc manner. The ﬁrst driver image
handle is retrieved by passing in a DriverImageHandle value of NULL . This will cause the ﬁrst driver image handle
to be returned in DriverImageHandle. On each successive call, the previous value of DriverImageHandle must be
passed in. If a call to this function returns a valid driver image handle, then EFI_SUCCESS is returned. This process
is repeated until EFI_NOT_FOUND is returned. If a DriverImageHandle is passed in that was not returned on a prior
call to this function, then EFI_INVALID_PARAMETER is returned. The ﬁrst driver image handle has the highest
precedence, and the last driver image handle has the lowest precedence. This ordered list of driver image handles is
used by the boot service EFI_BOOT_SERVICES.ConnectController() to search for the best driver for a controller.
EFI_SUCCESS A bus speciﬁc override driver is returned in DriverImageHandle.
EFI_NOT_FOUND The end of the list of override drivers was reached. A bus speciﬁc override
driver is not returned in DriverImageHandle.
11.4 EFI Driver Diagnostics Protocol
This section provides a detailed description of the EFI_DRIVER_DIAGNOSTICS2_PROTOCOL . This is a protocol
that allows a UEFI driver to perform diagnostics on a controller that the driver is managing.
11.4. EFI Driver Diagnostics Protocol 348Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.4.1 EFI_DRIVER_DIAGNOSTICS2_PROTOCOL
Summary
Used to perform diagnostics on a controller that a UEFI
GUID
#define EFI_DRIVER_DIAGNOSTICS_PROTOCOL_GUID \
{0x4d330321,0x025f,0x4aac,\
{0x90,0xd8,0x5e,0xd9,0x00,0x17,0x3b,0x63}}
typedef struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL {
EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS RunDiagnostics;
CHAR8 *SupportedLanguages;
} EFI_DRIVER_DIAGNOSTICS2_PROTOCOL;
RunDiagnostics Runs diagnostics on a controller. See the RunDiagnostics()
EFI_DRIVER_DIAGNOSTICS2_PROTOCOL.RunDiagnostics() function description.
SupportedLanguages A Null-terminated ASCII string that contains one or more supported language codes. This is
the list of language codes that this protocol supports. The number of languages supported by a driver is up to the
driver writer. SupportedLanguages is speciﬁed in RFC 4646 format. Formats — Language Codes and Language
Code Arrays for the format of language codes and language code arrays.
TheEFI_DRIVER_DIAGNOSTICS2_PROTOCOL is used by a platform management utility to allow the user to run
driver speciﬁc diagnostics on a controller. This protocol is optionally attached to the image handle of driver in the
driver’s entry point. The platform management utility can collect all the EFI_DRIVER_DIAGNOSTICS2_PROTOCOL
instances present in the system, and present the user with a menu of the controllers that have diagnostic capabilities.
This platform management utility is invoked through a platform component such as the EFI Boot Manager.
11.4.2 EFI_DRIVER_DIAGNOSTICS2_PROTOCOL.RunDiagnostics()
Summary
Runs diagnostics on a controller.
Prototype
typedef
(EFIAPI *EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS) (
IN EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *This,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN EFI_DRIVER_DIAGNOSTIC_TYPE DiagnosticType,
IN CHAR8 *Language,
OUT EFI_GUID **ErrorType,
OUT UINTN *BufferSize,
OUT CHAR16 **Buffer
);
11.4. EFI Driver Diagnostics Protocol 349Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This A pointer to the EFI_DRIVER_DIAGNOSTICS2_PROTOCOL instance.
ControllerHandle The handle of the controller to run diagnostics on.
ChildHandle The handle of the child controller to run diagnostics on. This is an optional parameter that may be
NULL. It will be NULL for device drivers. It will also be NULL for a bus drivers that attempt to run diagnostics
on the bus controller. It will not be NULL for a bus driver that attempts to run diagnostics on one of its child
controllers.
DiagnosticType Indicates type of diagnostics to perform on the controller speciﬁed by ControllerHandle and Child-
Handle. See “Related Deﬁnitions” for the list of supported types.
Language A pointer to a Null-terminated ASCII string array indicating the language. This is the language in which
the optional error message should be returned in Buffer, and it must match one of the languages speciﬁed in
SupportedLanguages. The number of languages supported by a driver is up to the driver writer. Language is
speciﬁed in RFC 4646 language code format. Formats — Language Codes and Language Code Arrays
Callers of interfaces that require RFC 4646 language codes to retrieve a Unicode string must use the RFC 4647
algorithm to lookup the Unicode string with the closest matching RFC 4646 language code.
ErrorType A GUID that deﬁnes the format of the data returned in Buffer.
BufferSize The size, in bytes, of the data returned in Buffer.
Buffer A buffer that contains a Null-terminated string plus some additional data whose format is deﬁned by Er-
rorType. Buffer is allocated by this function with EFI_BOOT_SERVICES.AllocatePool() , and it is the caller’s
responsibility to free it with a call to EFI_BOOT_SERVICES.FreePool() .
This function runs diagnostics on the controller speciﬁed by ControllerHandle and ChildHandle. DiagnoticType spec-
iﬁes the type of diagnostics to perform on the controller speciﬁed by ControllerHandle and ChildHandle. If the driver
speciﬁed by This does not support the language speciﬁed by Language, then EFI_UNSUPPORTED is returned. If
the controller speciﬁed by ControllerHandle and ChildHandle is not supported by the driver speciﬁed by This, then
EFI_UNSUPPORTED is returned. If the diagnostics type speciﬁed by DiagnosticType is not supported by this driver,
then EFI_UNSUPPORTED is returned. If there are not enough resources available to complete the diagnostic, then
EFI_OUT_OF_RESOURCES is returned. If the controller speciﬁed by ControllerHandle and ChildHandle passes the
diagnostic, then EFI_SUCCESS is returned. Otherwise, EFI_DEVICE_ERROR is returned.
If the language speciﬁed by Language is supported by this driver, then status information is returned in ErrorType,
BufferSize, and Buffer. Buffer contains a Null-terminated string followed by additional data whose format is deﬁned
by ErrorType. BufferSize is the size of Buffer is bytes, and it is the caller’s responsibility to call FreePool() on Buffer
when the caller is done with the return data. If there are not enough resources available to return the status information,
then EFI_OUT_OF_RESOURCES is returned.
// EFI_DRIVER_DIAGNOSTIC_TYPE
EfiDriverDiagnosticTypeStandard = 0,
EfiDriverDiagnosticTypeExtended = 1,
EfiDriverDiagnosticTypeManufacturing = 2,
EfiDriverDiagnosticTypeCancel = 3,
EfiDriverDiagnosticTypeMaximum
} EFI_DRIVER_DIAGNOSTIC_TYPE;
EﬁDriverDiagnosticTypeStandard
11.4. EFI Driver Diagnostics Protocol 350Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Performs standard diagnostics on the controller. This diagnostic type is required to be supported by all
implementations of this protocol.
EﬁDriverDiagnosticTypeExtended
This is an optional diagnostic type that performs diagnostics on the controller that may take an extended
amount of time to execute.
EﬁDriverDiagnosticTypeManufacturing
This is an optional diagnostic type that performs diagnostics on the controller that are suitable for a
manufacturing and test environment.
EﬁDriverDiagnosticTypeCancel
This is an optional diagnostic type that would only be used in the situation where an EFI_NOT_READY
had been returned by a previous call to RunDiagnostics() and there is a desire to cancel the current running
diagnostics operation.
EFI_SUCCESS The controller speciﬁed by ControllerHandle and ChildHandle passed the
diagnostic.
EFI_ACCESS_DENIED The request for initiating diagnostics was unable to be completed due to
some underlying hardware or software state.
EFI_INV ALID_PARAMETER ControllerHandle is NULL .

EFI_INV ALID_PARAMETER The driver speciﬁed by This is not a device driver, and ChildHandle is not
NULL .
EFI_INV ALID_PARAMETER Language is NULL.
EFI_INV ALID_PARAMETER ErrorType is NULL.
EFI_INV ALID_PARAMETER BufferSize isNULL .
EFI_UNSUPPORTED The driver speciﬁed by This does not support running diagnostics for the
controller speciﬁed by ControllerHandle and ChildHandle.
EFI_UNSUPPORTED The driver speciﬁed by This does not support the type of diagnostic speci-
ﬁed by DiagnosticType.
EFI_UNSUPPORTED The driver speciﬁed by This does not support the language speciﬁed by
Language.
EFI_OUT_OF_RESOURCES There are not enough resources available to complete the diagnostics.
EFI_OUT_OF_RESOURCES There are not enough resources available to return the status information in
ErrorType, BufferSize, and Buffer.
EFI_DEVICE_ERROR The controller speciﬁed by ControllerHandle and ChildHandle did not pass
the diagnostic.
EFI_NOT_READY The diagnostic operation was started, but not yet completed.
11.5 EFI Component Name Protocol
This section provides a detailed description of the EFI_COMPONENT_NAME2_PROTOCOL . This is a protocol that
allows an driver to provide a user readable name of a UEFI Driver, and a user readable name for each of the controllers
that the driver is managing. This protocol is used by platform management utilities that wish to display names of
components. These names may include the names of expansion slots, external connectors, embedded devices, and
add-in devices.
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11.5.1 EFI_COMPONENT_NAME2_PROTOCOL
Summary
Used to retrieve user readable names of drivers and controllers managed by UEFI Drivers.
GUID
#define EFI_COMPONENT_NAME2_PROTOCOL_GUID \
{0x6a7a5cff, 0xe8d9, 0x4f70,\
{0xba, 0xda, 0x75, 0xab, 0x30,0x25, 0xce, 0x14}}
typedef struct _EFI_COMPONENT_NAME2_PROTOCOL {
EFI_COMPONENT_NAME_GET_DRIVER_NAME GetDriverName;
EFI_COMPONENT_NAME_GET_CONTROLLER_NAME GetControllerName;
} EFI_COMPONENT_NAME2_PROTOCOL;
GetDriverName Retrieves a string that is the user readable name of the driver. See the GetDriverName()
EFI_COMPONENT_NAME2_PROTOCOL.GetDriverName() function description.
GetControllerName Retrieves a string that is the user readable name of a controller that is being managed by a
driver. See the GetControllerName() EFI_COMPONENT_NAME2_PROTOCOL.GetControllerName() function
SupportedLanguages A Null-terminated ASCII string array that contains one or more supported language codes.
This is the list of language codes that this protocol supports. The number of languages supported by a driver is
up to the driver writer. SupportedLanguages is speciﬁed in RFC 4646 format. Formats — Language Codes and
Language Code Arrays
The EFI_COMPONENT_NAME2_PROTOCOL is used retrieve a driver’s user readable name and the names of all
the controllers that a driver is managing from the driver’s point of view. Each of these names is returned as a Null-
terminated string. The caller is required to specify the language in which the string is returned, and this language must
be present in the list of languages that this protocol supports speciﬁed by SupportedLanguages.
11.5.2 EFI_COMPONENT_NAME2_PROTOCOL.GetDriverName()
Summary
Retrieves a string that is the user readable name of the driver.
Prototype
typedef
EFIAPI*EFI_COMPONENT_NAME_GET_DRIVER_NAME) (
IN EFI_COMPONENT_NAME2_PROTOCOL *This,
OUT CHAR16 **DriverName
);
This A pointer to the EFI_COMPONENT_NAME2_PROTOCOL instance.
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Language A pointer to a Null-terminated ASCII string array indicating the language. This is the language of the driver
name that the caller is requesting, and it must match one of the languages speciﬁed in SupportedLanguages. The
number of languages supported by a driver is up to the driver writer. Language is speciﬁed in RFC 4646 language
code format. Formats — Language Codes and Language Code Arrays for the format of language codes.
DriverName A pointer to the string to return. This string is the name of the driver speciﬁed by This in the language
speciﬁed by Language.
This function retrieves the user readable name of a driver in the form of a string. If the driver speciﬁed by This has a
user readable name in the language speciﬁed by Language, then a pointer to the driver name is returned in DriverName,
andEFI_SUCCESS is returned. If the driver speciﬁed by This does not support the language speciﬁed by Language,
then EFI_UNSUPPORTED is returned.
EFI_SUCCESS The string for the user readable name in the language speciﬁed by Language
for the driver speciﬁed by This was returned in DriverName.
EFI_INV ALID_PARAMETER DriverName is NULL.
Language.
11.5.3 EFI_COMPONENT_NAME2_PROTOCOL.GetControllerName()
Summary
Retrieves a string that is the user readable name of the controller that is being managed by a driver.
Prototype
typedef
(EFIAPI *EFI_COMPONENT_NAME_GET_CONTROLLER_NAME) (
OUT CHAR16 **ControllerName
);
ControllerHandle The handle of a controller that the driver speciﬁed by This is managing. This handle speciﬁes the
controller whose name is to be returned.
ChildHandle The handle of the child controller to retrieve the name of. This is an optional parameter that may be
NULL. It will be NULL for device drivers. It will also be NULL for bus drivers that attempt to retrieve the name
of the bus controller. It will not be NULL for a bus driver that attempts to retrieve the name of a child controller.
Language A pointer to a Null- terminated ASCII string array indicating the language. This is the language of the
controller name that the caller is requesting, and it must match one of the languages speciﬁed in SupportedLan-
guages. The number of languages supported by a driver is up to the driver writer. Language is speciﬁed in RFC
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4646 language code format. Formats — Language Codes and Language Code Arrays for the format of language
codes.
ControllerName A pointer to the string to return. This string is the name of the controller speciﬁed by Controller-
Handle and ChildHandle in the language speciﬁed by Language from the point of view of the driver speciﬁed
by This.
This function retrieves the user readable name of the controller speciﬁed by ControllerHandle and ChildHandle in the
form of a string. If the driver speciﬁed by This has a user readable name in the language speciﬁed by Language, then
a pointer to the controller name is returned in ControllerName, and EFI_SUCCESS is returned.
If the driver speciﬁed by This is not currently managing the controller speciﬁed by ControllerHandle and ChildHandle,
If the driver speciﬁed by This does not support the language speciﬁed by Language, then EFI_UNSUPPORTED is
returned.
EFI_SUCCESS The string for the user readable name speciﬁed by This, ControllerHandle,
ChildHandle, and Language was returned in ControllerName.
NULL .
EFI_INV ALID_PARAMETER ControllerName is NULL.
EFI_UNSUPPORTED The driver speciﬁed by This is a device driver and ChildHandle is not NULL
.
EFI_UNSUPPORTED The driver speciﬁed by This is not currently managing the controller speci-
ﬁed by ControllerHandle andChildHandle .
Language .
11.6 EFI Service Binding Protocol
This section provides a detailed description of the EFI_SERVICE_BINDING_PROTOCOL . This protocol may be
produced only by drivers that follow the UEFI Driver Model. Use this protocol with the EFI Driver Binding Pro-
tocol to produce a set of protocols related to a device. The EFI_DRIVER_BINDING_PROTOCOL supports simple

NULL .
.
Language .
layering of protocols on a device, but it does not support more complex relationships such as trees or graphs. The
EFI_SERVICE_BINDING_PROTOCOL provides a member function to create a child handle with a new protocol in-
stalled on it, and another member function to destroy a previously created child handle. These member functions apply
equally to all drivers.
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11.6.1 EFI_SERVICE_BINDING_PROTOCOL
Summary
Provides services that are required to create and destroy child handles that support a given set of protocols.
GUID
This protocol does not have its own GUID. Instead, drivers for other protocols will deﬁne a GUID that shares the same
protocol interface as the EFI_SERVICE_BINDING_PROTOCOL . The protocols deﬁned in this document that have
this property include for example the following:
• EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL
• EFI_ARP_SERVICE_BINDING_PROTOCOL
• EFI_EAP_SERVICE_BINDING_PROTOCOL
• EFI_IP4_SERVICE_BINDING_PROTOCOL
• EFI_TCP4_SERVICE_BINDING_PROTOCOL
• EFI_UDP4_SERVICE_BINDING_PROTOCOL
• EFI_MTFTP4_SERVICE_BINDING_PROTOCOL
• EFI_DHCP4_SERVICE_BINDING_PROTOCOL
• EFI_REST_EX_SERVICE_BINDING_PROTOCOL
typedef struct _EFI_SERVICE_BINDING_PROTOCOL {
EFI_SERVICE_BINDING_CREATE_CHILD CreateChild;
EFI_SERVICE_BINDING_DESTROY_CHILD DestroyChild;
} EFI_SERVICE_BINDING_PROTOCOL;
CreateChild Creates a child handle and installs a protocol. See the
EFI_SERVICE_BINDING_PROTOCOL.CreateChild() function description.
DestroyChild Destroys a child handle with a protocol installed on it. See the
EFI_SERVICE_BINDING_PROTOCOL.DestroyChild() function description.
TheEFI_SERVICE_BINDING_PROTOCOL provides member functions to create and destroy child handles. A driver
is responsible for adding protocols to the child handle in CreateChild() and removing protocols in DestroyChild() . It
is also required that the CreateChild() function opens the parent protocol BY_CHILD_CONTROLLER to establish
the parent-child relationship, and closes the protocol in DestroyChild() .The pseudo code for CreateChild() andDe-
stroyChild() is provided to specify the required behavior, not to specify the required implementation. Each consumer
of a software protocol is responsible for calling CreateChild() when it requires the protocol and calling DestroyChild()
when it is ﬁnished with that protocol.
11.6.2 EFI_SERVICE_BINDING_PROTOCOL.CreateChild()
Summary
Creates a child handle and installs a protocol.
Prototype
typedef
(EFIAPI *EFI_SERVICE_BINDING_CREATE_CHILD) (
IN EFI_SERVICE_BINDING_PROTOCOL *This,
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IN OUT EFI_HANDLE *ChildHandle
);
This Pointer to the EFI_SERVICE_BINDING_PROTOCOL instance.
ChildHandle Pointer to the handle of the child to create. If it is a pointer to NULL , then a new handle is created. If
it is a pointer to an existing UEFI handle, then the protocol is added to the existing UEFI handle.
The CreateChild() function installs a protocol on ChildHandle . IfChildHandle is a pointer to NULL , then a new
handle is created and returned in ChildHandle . IfChildHandle is not a pointer to NULL , then the protocol installs on
the existing ChildHandle .
EFI_SUCCESS The protocol was added to ChildHandle .
EFI_INV ALID_PARAMETER ChildHandle isNULL .
EFI_OUT_OF_RESOURCES There are not enough resources available to create the child.
Other The child handle was not created.
Examples
The following example shows how a consumer of the EFI ARP Protocol would use the CreateChild() function of the
EFI_SERVICE_BINDING_PROTOCOL to create a child handle with the EFI ARP Protocol installed on that handle.
EFI_HII_HANDLE ControllerHandle;
EFI_ARP_SERVICE_BINDING_PROTOCOL *ArpSb;
EFI_ARP_PROTOCOL *Arp;
//
// Get the ArpServiceBinding Protocol
//
&gEfiArpServiceBindingProtocolGuid,
(VOID \**)&ArpSb,
DriverBindingHandle,
);
}
//
// Initialize a ChildHandle
//
ChildHandle = NULL;
//
// Create a ChildHandle withthe Arp Protocol
//
Status = ArpSb->CreateChild (ArpSb, &ChildHandle);
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}
//
// Retrieve the Arp Protocol from ChildHandle
//
ChildHandle,
&gEfiArpProtocolGuid,
(VOID**)&Arp,
);
}
The following is the general algorithm for implementing the CreateChild() function:
1. Allocate and initialize any data structures that are required to produce the requested protocol on a child handle.
If the allocation fails, then return EFI_OUT_OF_RESOURCES .
2. Install the requested protocol onto ChildHandle . If ChildHandle is a pointer to NULL , then the requested
protocol installs onto a new handle.
3. Open the parent protocol BY_CHILD_CONTROLLER to establish the parent-child relationship. If the parent
protocol cannot be opened, then destroy the ChildHandle created in step 2, free the data structures allocated in
step 1, and return an error.
4. Increment the number of children created by CreateChild() .
Listed below is sample code of the CreateChild() function of the EFI ARP Protocol driver. This driver looks up its
private context data structure from the instance of the EFI_SERVICE_BINDING_PROTOCOL produced on the handle
for the network controller. After retrieving the private context data structure, the driver can use its contents to build
the private context data structure for the child being created. The EFI ARP Protocol driver then installs the EFI_ARP
_PROTOCOL onto ChildHandle .
EFIAPI
ArpServiceBindingCreateChild (
IN EFI_HANDLE *ChildHandle
)
{
ARP_PRIVATE_DATA *Private;
ARP_PRIVATE_DATA *PrivateChild;
//
// Retrieve the Private Context Data Structure
//
Private = ARP\_PRIVATE_DATA_FROM_SERVICE_BINDING_THIS (This);
//
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// Create a new child
//
PrivateChild = EfiLibAllocatePool (sizeof (ARP\_PRIVATE_DATA));
if(PrivateChild == NULL) {
returnEFI_OUT_OF_RESOURCES;
}
//
// Copy Private Context Data Structure
//
gBS->CopyMem (PrivateChild, Private, sizeof (ARP\_PRIVATE_DATA));
//
// Install Arp onto ChildHandle
//
&gEfiArpProtocolGuid, &PrivateChild->Arp,
NULL
);
gBS->FreePool (PrivateChild);
}
Private->ChildHandle,
&gEfiManagedNetworkProtocolGuid,
(VOID**)&PrivateChild->ManagedNetwork,
gArpDriverBinding.DriverBindingHandle,
*ChildHandle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
);
ArpSB->DestroyChild (This, ChildHandle);
}
//
// Increase number of children created
//
Private->NumberCreated++;
}
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11.6.3 EFI_SERVICE_BINDING_PROTOCOL.DestroyChild()
Summary
Destroys a child handle with a protocol installed on it.
Prototype
typedef
(EFIAPI *EFI_SERVICE_BINDING_DESTROY_CHILD) (
IN EFI_HANDLE ChildHandle
);
ChildHandle Handle of the child to destroy.
The DestroyChild() function does the opposite of CreateChild() . It removes a protocol that was installed by Cre-
ateChild() from ChildHandle . If the removed protocol is the last protocol on ChildHandle , then ChildHandle is
destroyed.
EFI_SUCCESS The protocol was removed from ChildHandle .
EFI_UNSUPPORTED ChildHandle does not support the protocol that is being removed.
EFI_INV ALID_PARAMETER ChildHandle is not a valid UEFI handle.
EFI_ACCESS_DENIED The protocol could not be removed from the ChildHandle because its ser-
vices are being used.
Other The child handle was not destroyed.
Examples
The following example shows how a consumer of the EFI ARP Protocol would use the DestroyChild() function of the
EFI_SERVICE_BINDING_PROTOCOL to destroy a child handle with the EFI ARP Protocol installed on that handle.
EFI_ARP\_SERVICE_BINDING_PROTOCOL *Arp;
//

Examples
//
// Get the Arp Service Binding Protocol
//
(VOID**)&ArpSb,
);
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}
//
// Destroy the ChildHandle withthe Arp Protocol
//
Status = ArpSb->DestroyChild (ArpSb, ChildHandle);
}
The following is the general algorithm for implementing the DestroyChild() function:
1. Retrieve the protocol from ChildHandle . If this retrieval fails, then return EFI_SUCCESS because the child has
already been destroyed.
2. If this call is a recursive call to destroy the same child, then return EFI_SUCCESS .
3. Close the parent protocol with CloseProtocol() .
4. Set a ﬂag to detect a recursive call to destroy the same child.
5. Remove the protocol from ChildHandle . If this removal fails, then reopen the parent protocol and clear the ﬂag
to detect a recursive call to destroy the same child.
6. Free any data structures that allocated in CreateChild() .
7. Decrement the number of children that created with CreateChild() .
8. Return EFI_SUCCESS .
Listed below is sample code of the DestroyChild() function of the EFI ARP Protocol driver. This driver looks up its
for the network controller. The driver attempts to retrieve the EFI_ARP _PROTOCOL from ChildHandle . If that
fails, then EFI_SUCCESS is returned. The EFI_ARP _PROTOCOL is then used to retrieve the private context data
structure for the child. The private context data stores the ﬂag that detects if DestroyChild() is being called recursively.
If a recursion is detected, then EFI_SUCCESS is returned. Otherwise, the EFI_ARP _PROTOCOL is removed from
ChildHandle , the number of children are decremented, and EFI_SUCCESS is returned.
EFIAPI
ArpServiceBindingDestroyChild (
)
{
//
//
//
// Retrieve Arp Protocol from ChildHandle
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//
);
}
//
// Retrieve Private Context Data Structure
//
PrivateChild = ARP_PRIVATE_DATA_FROM_ARP_THIS (Arp);
if(PrivateChild->Destroy) {
}
//
// Close the ManagedNetwork Protocol
//
Private-> ChildHandle,
ChildHandle
);
PrivateChild->Destroy = TRUE;
//
// Uninstall Arp from ChildHandle
//
NULL
);
//
// Uninstall failed, so reopen the parent Arp Protocol and
//returnan error
//
PrivateChild->Destroy = FALSE;
gBS->OpenProtocol (
);
}
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//
// Free Private Context Data Structure
//
//
// Decrease number of children created
//
Private -> NumberCreated --;
11.7 EFI Platform to Driver Conﬁguration Protocol
This section provides a detailed description of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL
. This is a protocol that is optionally produced by the platform and optionally consumed by a UEFI Driver in its Start()
function. This protocol allows the driver to receive conﬁguration information as part of being started.
11.7.1 EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL
Summary
Used to retrieve conﬁguration information for a device that a UEFI driver is about to start.
GUID
#define EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL_GUID \
{ 0x642cd590, 0x8059, 0x4c0a,\
{ 0xa9, 0x58, 0xc5, 0xec, 0x07, 0xd2, 0x3c, 0x4b } }
typedef struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL {
EFI_PLATFORM_TO_DRIVER_CONFIGURATION_QUERY Query;
EFI_PLATFORM_TO_DRIVER_CONFIGURATION_RESPONSE Response;
} EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL;
Query Called by the UEFI Driver Start() function to get conﬁguration information from the platform.
Response Called by the UEFI Driver Start() function to let the platform know how UEFI driver processed the data
return from Query.
The EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL is used by the UEFI
driver to query the platform for conﬁguration information. The UEFI driver calls
EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL.Query() multiple times to get conﬁg-
uration information from the platform. For every call to Query() there must be a matching call to
EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL.Response() so the UEFI driver can inform
the platform how it used the information passed in from Query().
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It’s legal for a UEFI driver to use Response() to inform the platform it does not understand the data returned via
Query() and thus no action was taken.
11.7.2 EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL.Query()
Summary
Allows the UEFI driver to query the platform for conﬁguration information needed to complete the drivers Start()
operation.
Prototype
typedef
(EFIAPI *EFI_PLATFORM_TO_DRIVER_CONFIGURATION_QUERY) (
IN EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL *This,
IN UINTN *Instance,
OUT EFI_GUID **ParameterTypeGuid,
OUT VOID **ParameterBlock,
OUT UINTN *ParameterBlockSize
);
This A pointer to the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL instance.
ControllerHandle The handle the platform will return conﬁguration information about.
ChildHandle The handle of the child controller to return information on. This is an optional parameter that may be
NULL. It will be NULL for device drivers, and for bus drivers that attempt to get options for the bus controller.
It will not be NULL for a bus driver that attempts to get options for one of its child controllers.
Instance Pointer to the Instance value. Zero means return the ﬁrst query data. The caller should increment this value
by one each time to retrieve successive data.
ParameterTypeGuid AnEFI_GUID that deﬁnes the contents of ParameterBlock. UEFI drivers must use the Param-
eterTypeGuid to determine how to parse the ParameterBlock.The caller should not attempt to free Parameter-
TypeGuid .
ParameterBlock The platform returns a pointer to the ParameterBlock structure which contains details about the
conﬁguration parameters speciﬁc to the ParameterTypeGuid . This structure is deﬁned based on the protocol
and may be different for different protocols. UEFI driver decodes this structure and its contents based on
ParameterTypeGuid .ParameterBlock is allocated by the platform and the platform is responsible for freeing
theParameterBlock after Response is called.
ParameterBlockSize The platform returns the size of the ParameterBlock in bytes.
The UEFI driver must call Query early in the Start() function before any time consuming operations are performed. If
ChildHandle is NULL the driver is requesting information from the platform about the ControllerHandle that is being
started. Information returned from Query may lead to the drivers Start() function failing.
If the UEFI driver is a bus driver and producing a ChildHandle the driver must call Query after the child handle has
been created and an EFI_DEVICE_PATH_PROTOCOL has been placed on that handle, but before any time consuming
operation is performed. If information return by Query may lead the driver to decide to not create the ChildHandle.
The driver must then cleanup and remove the ChildHandle from the system.
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The UEFI driver repeatedly calls Query, processes the information returned by the platform, and calls Response

passing in the arguments returned from Query. The Instance value passed into Response must be the same value
passed to the corresponding call to Query. The UEFI driver must continuously call Query and Response until
EFI_NOT_FOUND is returned by Query.
If the UEFI driver does not recognize the ParameterTypeGuid , it calls Response with a ConﬁgurationAction ofEﬁ-
PlatformConﬁgurationActionUnsupportedGuid . The UEFI driver must then continue calling Query andResponse
until EFI_NOT_FOUND is returned by Query . This gives the platform an opportunity to pass additional conﬁguration
settings using a different ParameterTypeGuid that may be supported by the driver.
AnInstance value of zero means the ﬁrst ParameterBLock in the set of unprocessed parameter blocks. The driver
should increment the Instance value by one for each successive call to Query .
EFI_SUCCESS The platform return parameter information for ControllerHandle.
EFI_NOT_FOUND No more unread Instance exists.
EFI_INV ALID_PARAMETER Instance is NULL.
EFI_DEVICE_ERROR A device error occurred while attempting to return parameter block infor-
mation for the controller speciﬁed by ControllerHandle and ChildHandle.
EFI_OUT_RESOURCES There are not enough resources available to set the conﬁguration options for
the controller speciﬁed by ControllerHandle and ChildHandle.
11.7.3 EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL.Response()
Summary
Tell the platform what actions where taken by the driver after processing the data returned from Query.
Prototype
typedef
(EFIAPI *EFI_PLATFORM_TO_DRIVER_CONFIGURATION_RESPONSE) (
IN EFI_GUID *ParameterTypeGuid,
IN VOID *ParameterBlock,
IN UINTN ParameterBlockSize,
IN EFI_PLATFORM_CONFIGURATION_ACTION ConfigurationAction
);
ControllerHandle The handle the driver is returning conﬁguration information about.
Instance Instance data passed to EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL.Query() .
ParameterTypeGuid ParameterTypeGuid returned from Query.
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ParameterBlock ParameterBlock returned from Query.
ParameterBlockSize The ParameterBlock size returned from Query.
ConﬁgurationAction The driver tells the platform what action is required for ParameterBlock to take effect. See
“Related Deﬁnitions” for a list of actions.
The UEFI driver repeatedly calls Query, processes the information returned by the platform, and calls Response pass-
ing in the arguments returned from Query. The UEFI driver must continuously call Query until EFI_NOT_FOUND
is returned. For every call to Query that returns EFI_SUCCESS a corresponding call to Response is required passing
in the same ContollerHandle, ChildHandle, Instance, ParameterTypeGuid, ParameterBlock, and ParameterBlockSize.
The UEFI driver may update values in ParameterBlock based on rules deﬁned by ParameterTypeGuid.
The platform is responsible for freeing ParameterBlock and the UEFI driver must not try to free it.
EfiPlatformConfigurationActionNone = 0,
EfiPlatformConfigurationActionStopController = 1,
EfiPlatformConfigurationActionRestartController = 2,
EfiPlatformConfigurationActionRestartPlatform = 3,
EfiPlatformConfigurationActionNvramFailed = 4,
EfiPlatformConfigurationActionUnsupportedGuid = 5,
EfiPlatformConfigurationActionMaximum
} EFI_PLATFORM_CONFIGURATION_ACTION;
EﬁPlatformConﬁgurationActionNone
The controller speciﬁed by ControllerHandle is still in a usable state, it’s conﬁguration has been updated via parsing
theParameterBlock . If required by the parameter block and the module supports an NVRAM store the conﬁgura-
tion information from ParameterBlock was successfully saved to the NVRAM. No actions are required before this
controller can be used again with the updated conﬁguration settings.
EﬁPlatformConﬁgurationStopController
The driver has detected that the controller speciﬁed by ControllerHandle is not in a usable state, and it needs to
be stopped. The calling agent can use the EFI_BOOT_SERVICES.DisconnectController() service to perform this
operation, and it should be performed as soon as possible.
EﬁPlatformConﬁgurationRestartController
This controller speciﬁed by ControllerHandle needs to be stopped and restarted before it can be used again. The
calling agent can use the DisconnectController() andEFI_BOOT_SERVICES.ConnectController() services to perform
this operation. The restart operation can be delayed until all of the conﬁguration options have been set.
EﬁPlatformConﬁgurationRestartPlatform
A conﬁguration change has been made that requires the platform to be restarted before the controller speciﬁed by
ControllerHandle can be used again. The calling agent can use the ResetSystem() services to perform this operation.
The restart operation can be delayed until all of the conﬁguration options have been set.
EﬁPlatformConﬁgurationActionNvramFailed
The controller speciﬁed by ControllerHandle is still in a usable state; its conﬁguration has been updated via parsing the
ParameterBlock . The driver tried to update the driver’s private NVRAM store with information from ParameterBlock
and failed. No actions are required before this controller can be used again with the updated conﬁguration settings,
but these conﬁguration settings are not guaranteed to persist after ControllerHandle is stopped.
EﬁPlatformConﬁgurationActionUnsupportedGuid
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The controller speciﬁed by ControllerHandle is still in a usable state; its conﬁguration has not been updated via pars-
ing the ParameterBlock. The driver did not support the ParameterBlock format identiﬁed by ParameterTypeGuid. No
actions are required before this controller can be used again. On additional Query calls from this ControllerHan-
dle, the platform should stop returning a ParameterBlock qualiﬁed by this same ParameterTypeGuid. If no other
ParameterTypeGuid is supported by the platform, Query should return EFI_NOT_FOUND.
EFI_NOT_FOUND Instance was not found.
11.7.4 DMTF SM CLP ParameterTypeGuid
The following parameter protocol ParameterTypeGuid provides the support for parameters communicated through the
DMTF SM CLP Speciﬁcation 1.0 Final Standard to be used to conﬁgure the UEFI driver.
In this section the producer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL is platform
ﬁrmware and the consumer is the UEFI driver.
Note :If future versions of the DMTF SM CLP Speciﬁcation require changes to the parameter block deﬁnition, newer
ParameterTypeGuid will be used .
GUID
#define EFI_PLATFORM_TO_DRIVER_CONFIGURATION_CLP_GUID \
{0x345ecc0e, 0xcb6, 0x4b75, \
{0xbb, 0x57, 0x1b, 0x12, 0x9c, 0x47, 0x33,0x3e}}
Parameter Block
CHAR8 *CLPCommand;
UINT32 CLPCommandLength;
CHAR8 *CLPReturnString; *
UINT32 CLPReturnStringLength;
UINT8 CLPCmdStatus;
UINT8 CLPErrorValue;
UINT16 CLPMsgCode;
} EFI_CONFIGURE_CLP_PARAMETER_BLK;
Structure Member Deﬁnitions
CLPCommand A pointer to the null-terminated UTF-8 string that speciﬁes the DMTF SM CLP command line that
the driver is required to parse and process when this function is called. See the DMTF SM CLP Speciﬁcation
1.0Final Standard for details on the format and syntax of the CLP command line string. CLPCommand buffer
is allocated by the producer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL.
CLPCommandLength The length of the CLP Command in bytes.
CLPReturnString A pointer to the null-terminated UTF-8 string that indicates the CLP return status that the driver
is required to provide to the calling agent. The calling agent may parse and/or pass this for processing and
user feedback. The SM CLP Command Response string buffer is ﬁlled in by the UEFI driver in the “key-
word=value” format described in the SM CLP Speciﬁcation (see section 3.table 101, “Output Data”), unless
otherwise requested via the SM CLP -output option in the Command Line string buffer. UEFI driver’s support
for this default “keyword=value” output format is required if the UEFI driver supports this protocol, while sup-

port for other SM CLP output formats is optional. (The UEFI Driver should set CLPCmdStatus=2 (COMMAND
11.7. EFI Platform to Driver Conﬁguration Protocol 366Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PROCESSING FAILED) and CLPErrorValue=249 (OUTPUT FORMAT NOT SUPPORTED) if the SM CLP
-output option requested by the caller is not supported by the UEFI Driver.).
CLPReturnString* buffer is allocated by the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL
and undeﬁned prior to the call to Response ().
CLPReturnStringLength The length of the CLP return status string in bytes.
CLPCmdStatus SM CLP Command Status (see DMTF SM CLP Speciﬁcation 1.0 Final Standard - Table 4)
CLPErrorValue SM CLP Processing Error Value (see DMTF SM CLP Speciﬁcation 1.0 Final Standard - Table 6).
This ﬁeld is ﬁlled in by the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL
and undeﬁned prior to the call to Response() .
CLPMsgCode
Bit 15: OEM Message Code Flag
0 = Message Code is an SM CLP Probable Cause Value. (see SM CLP Speciﬁcation Table 11)
Bits 14-0: Message Code
11.8 EFI Driver Supported EFI Version Protocol
11.8.1 EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL
Summary
Provides information about the version of the EFI speciﬁcation that a driver is following. This protocol is required for
EFI drivers that are on PCI and other plug in cards.
GUID
#define EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL_GUID \
{ 0x5c198761, 0x16a8, 0x4e69, \
{ 0x97, 0x2c, 0x89, 0xd6, 0x79, 0x54, 0xf8, 0x1d } }
typedef struct _EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL {
UINT32 FirmwareVersion;
} EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL;
Length The size, in bytes, of the entire structure. Future versions of this speciﬁcation may grow the size of the
structure.
FirmwareVersion The latest version of the UEFI Speciﬁcation that this driver conforms to. Refer to the
EFI_SPECIFICATION_VERSION deﬁnition in EFI System Table .
The EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL provides a mechanism for an EFI driver to publish
the version of the EFI speciﬁcation it conforms to. This protocol must be placed on the drivers image handle when the
driver’s entry point is called.
11.8. EFI Driver Supported EFI Version Protocol 367Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.9 EFI Driver Family Override Protocol
11.9.1 Overview
This section deﬁnes the Driver Family Override Protocol, and contains the following:
• Description and code deﬁnitions of the Driver Family Override Protocol.
• Required updates to the EFI Boot Services ConnectController().
• Typical production of the Driver Family Override Protocol by an EFI Driver that follows the EFI Driver Model.
The Driver Family Override Protocol provides a method for an EFI Driver to opt-in to a higher priority rule for
connecting drivers to controllers in the EFI Boot Service ConnectController() . This new rule is higher priority than
the Bus Speciﬁc Driver Override Protocol rule and lower priority than the Platform Driver Override Rule.
The Driver Family Override Protocol is a backwards compatible extension to the EFI Driver Model and is only avail-
able during boot time. The Driver Family Override Protocol may be optionally produced by a driver that follows the
EFI Driver Model. If this protocol is produced, it must be installed onto the Driver Image Handle. Drivers that follow
the EFI Driver Model typically install the EFI Driver Binding Protocol onto the driver’s image handle. In this case, the
Driver Family Override Protocol must also be installed onto the driver’s image handle. If a single EFI Driver produces
more than one instance of the EFI Driver Binding Protocol, then the Driver Family Override Protocol must be installed
onto the same handle as the EFI Driver Binding Protocol that is associated with the Driver Family Override Protocol.
Since it is legal for a single EFI Driver to produce multiple EFI Driver Binding Protocol instances, it is also legal for
a single EFI Driver to produce multiple Driver Family Override Protocol instances.
11.9.1.1 EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL
Summary
When installed, the Driver Family Override Protocol informs the UEFI Boot Service ConnectController() that this
driver is higher priority than the list of drivers returned by the Bus Speciﬁc Driver Override Protocol.
GUID
#define EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL_GUID \
{0xb1ee129e,0xda36,0x4181,\
{0x91,0xf8,0x04,0xa4,0x92,0x37,0x66,0xa7}}
typedef struct \_EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL {
EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION GetVersion;
} EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL;
GetVersion Retrieves the version of the driver that is used by the EFI Boot Service ConnectController() to sort the set
of Driver Binding Protocols in order from highest priority to lowest priority. For drivers that support the Driver
Family Override Protocol, those drivers are sorted so that the drivers with higher values returned by GetVersion()
are high priority that drivers that return lower values from GetVersion() .
This protocol contains a single service that returns a version value for the driver that produces this protocol. High
values are higher priority than lower values when evaluated by the EFI Boot Service ConnectController() . This is
an optional protocol that may be produced by an EFI Driver that follows the EFI Driver Model. If this protocol is
produced, it must be installed onto a handle that also contains the EFI Driver Binding Protocol.
11.9. EFI Driver Family Override Protocol 368Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If this protocol is not produced by an EFI Driver, then the rules used to connect a driver to a controller from highest
priority to lowest priority are as follows:
• Context Override
• Platform Driver Override
• Bus Speciﬁc Driver Override Protocol
• Driver Binding Search
If this protocol is produced by an EFI Driver, then the rules used to connect a driver to a controller from highest priority
to lowest priority are as follows:
• Driver Family Override
• Bus Speciﬁc Driver Override
11.9.1.2 EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL.GetVersion()
Summary
Retrieves the version of the driver that is used by the EFI Boot Service ConnectController() to sort the set of Driver
Binding Protocols in order from highest priority to lowest priority. For drivers that support the Driver Family Override
Protocol, those drivers are sorted so that the drivers with higher values returned by GetVersion() are high priority that
drivers that return lower values from GetVersion() .
Prototype
typedef
UINT32
(EFIAPI *EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION) (
IN EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL *This
);
This A pointer to the EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL instance.
This function returns the version value associated with the driver speciﬁed by This.
11.10 EFI Driver Health Protocol
This section contains the basic deﬁnitions of the Driver Health Protocol.
11.10. EFI Driver Health Protocol 369Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.10.1 EFI_DRIVER_HEALTH_PROTOCOL
Summary
When installed, the Driver Health Protocol produces a collection of services that allow the health status for a controller
to be retrieved. If a controller is not in a usable state, status messages may be reported to the user, repair operations
can be invoked, and the user may be asked to make software and/or hardware conﬁguration changes. All display, as
well as interaction, with the user must be handled by the consumer of the Driver Health Protocol.
The Driver Health Protocol must be installed onto the same handle as the associated Driver Binding handle.
GUID
#define EFI_DRIVER_HEALTH_PROTOCOL_GUID \
{0x2a534210,0x9280,0x41d8,\
{0xae,0x79,0xca,0xda,0x01,0xa2,0xb1,0x27 }}
typedef struct _EFI_DRIVER_HEALTH_PROTOCOL {
EFI_DRIVER_HEALTH_GET_HEALTH_STATUS GetHealthStatus;
EFI_DRIVER_HEALTH_REPAIR Repair;
} EFI_DRIVER_HEALTH_PROTOCOL;
GetHealthStatus Retrieves the health status of a controller in the platform. This function can also optionally return
warning messages, error messages, and an HII Form that may be used to repair a controller that is not properly
conﬁgured.
Repair Performs a repair operation on a controller in the platform. This function can optionally report repair progress
information back to the platform.
The Driver Health Protocol is optionally produced by a driver that follows the EFI Driver Model. If an EFI Driver
needs to report health status to the platform, provide warning or error messages to the user, perform length repair
operations, or request the user to make hardware or software conﬁguration changes, then the Driver Health Protocol

must be produced.
A controller that is managed by driver that follows the EFI Driver Model and produces the Driver Health Protocol must
report the current health of the controllers that the driver is currently managing. The controller can initially be healthy,
failed, require repair, or require conﬁguration. If a controller requires conﬁguration, and the user make conﬁguration
changes, the controller may then need to be reconnected or the system may need to be rebooted for the conﬁguration
changes to take effect. Figure 2-1 below shows all the possible health states of a controller, the set of initial states, the
set of terminal states, and the legal transitions between the health states.
11.10.2 EFI_DRIVER_HEALTH_PROTOCOL.GetHealthStatus()
Summary
Retrieves the health status of a controller in the platform. This function can also optionally return warning messages,
error messages, and an HII Form that may be used to repair a controller that is not proper conﬁgured.
Prototype
typedef
(EFIAPI *EFI_DRIVER_HEALTH_GET_HEALTH_STATUS) (
11.10. EFI Driver Health Protocol 370Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 11.1: Driver Health Status States
IN EFI_DRIVER_HEALTH_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle, OPTIONAL
IN EFI_HANDLE ChildHandle, OPTIONAL
OUT EFI_DRIVER_HEALTH_STATUS *HealthStatus,
OUT EFI_DRIVER_HEALTH_HII_MESSAGE **MessageList, OPTIONAL
OUT EFI_HII_HANDLE *FormHiiHandle OPTIONAL
);
This A pointer to the EFI_DRIVER_HEALTH_PROTOCOL instance.
ControllerHandle The handle of the controller to retrieve the health status on. This is an optional parameter that may
beNULL . If this parameter is NULL , then the value of ChildHandle is ignored, and the combined health status
of all the devices that the driver is managing is returned.
ChildHandle The handle of the child controller to retrieve the health status on. This is an optional parameter that
may be NULL. It will be NULL for device drivers. It will also be NULL for bus drivers when an attempt is
made to collect the health status of the bus controller. If will not be NULL when an attempt is made to collect
the health status for a child controller produced by the driver. If ControllerHandle is NULL, then this parameter
is ignored.
HealthStatus A pointer to the health status that is returned by this function. The health status for the controller
speciﬁed by ControllerHandle andChildHandle is returned.
MessageList A pointer to an array of warning or error messages associated with the controller speciﬁed by Con-
trollerHandle andChildHandle . This is an optional parameter that may be NULL .MessageList is allocated by
11.10. EFI Driver Health Protocol 371Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
this function with the EFI Boot Service AllocatePool() , and it is the caller’s responsibility to free MessageList
with the EFI Boot Service FreePool() . Each message is speciﬁed by tuple of an EFI_HII_HANDLE and an
EFI_STRING_ID . The array of messages is terminated by tuple containing a EFI_HII_HANDLE with a value
ofNULL . The EFI_HII_STRING_PROTOCOL.GetString() function can be used to retrieve the warning or error
message as a Null-terminated string in a speciﬁc language. Messages may be returned for any of the HealthSta-
tusvalues except EﬁDriverHealthStatusReconnectRequired andEﬁDriverHealthStatusRebootRequired .
FormHiiHandle A pointer to the HII handle containing the HII form used when conﬁguration is required. The HII
handle is associated with the controller speciﬁed by ControllerHandle andChildHandle . If this is NULL , then
no HII form is available. An HII handle will only be returned with a HealthStatus value of E ﬁDriverHealthSta-
tusConﬁgurationRequired .
This function returns the health status associated with the controller speciﬁed by ControllerHandle andChildHandle.
If ControllerHandle is NULL, and if the EFI driver is not managing any controller then EFI_UNSUPPORTED is
returned. If ControllerHandle is not NULL and the driver speciﬁed by This is not currently managing the controller
speciﬁed by ControllerHandle andChildHandle , then EFI_UNSUPPORTED is returned. If HealthStatus isNULL ,
then EFI_INVALID_PARAMETER is returned.
IfControllerHandle isNULL , then the cumulative health status of all the controllers managed by the EFI driver is
returned. If all the controller manages by the driver are healthy, then EﬁDriverHealthStatusHealthy must be returned
inHealthStatus . If one or more of the controllers managed by the EFI Driver is not healthy, then EﬁDriverHealthSta-
tusFailed must be returned.
IfControllerHandle is not NULL andChildHandle isNULL , then the health status of the controller speciﬁed by
ControllerHandle is returned in HealthStatus andEFI_SUCCESS is returned.
IfControllerHandle is not NULL andChildHandle is not NULL , then the health status of the child controller speciﬁed
byControllerHandle andChildHandle is returned in HealthStatus andEFI_SUCCESS is returned.
IfMessageList isNULL , then no messages are returned from this function.
IfMessageList is not NULL , and HealthStatus isEﬁDriverHealthStatusReconnectRequired orEﬁDriverHealthStatus-
RebootRequired then no messages are returned and *MessageList must be set to NULL .
IfMessageList is not NULL , and there are no warning or error messages associated with the controller speciﬁed by
ControllerHandle andChildHandle , then *MessageList must be set to NULL .
IfMessageList is not NULL , and there are one or more warning or error messages associated with the con-
troller speciﬁed by ControllerHandle andChildHandle , then *MessageList must point to a buffer allocated with
the EFI Boot Service AllocatePool() . The number of EFI_DRIVER_HEALTH_HII_MESSAGE structures allocated
in the buffer must be one more than the total number of warning or error messages, and the HiiHandle ﬁeld of
the last EFI_DRIVER_HEALTH_HII_MESSAGE structure must be set to NULL to terminate the list of messages.
It is the caller’s responsibility to free the buffer returned in *MessageList using the EFI Boot Service FreeP-
ool() . Each message is speciﬁed by an EFI_HII_HANDLE and an EFI_STRING_ID . The caller may use the
EFI_HII_STRING_PROTOCOL.GetString() function to convert each message into a Null-terminated string that can
may be displayed on a console device.
IfFormHiiHandle isNULL , then no forms are returned from this function.
IfFormHiiHandle is not NULL , and HealthStatus is not EﬁDriverHealthStatusConﬁgurationRequired , then no forms
are returned and *FormHiiHandle must be set to NULL .
IfFormHiiHandle is not NULL , and FormSetGuid is not NULL , and HealthStatus isEﬁDriverHealthStatusConﬁgu-
rationRequired , then FormHiiHandle is assigned to the HII handle which contains the HII form required to perform
the conﬁguration operation.
If ControllerHandle is NULL, and there are no devices being managed by the driver then EFI_UNSUPPORTED is
returned.
11.10. EFI Driver Health Protocol 372Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_DRIVER_HEALTH_STATUS
EfiDriverHealthStatusHealthy,
EfiDriverHealthStatusRepairRequired,
EfiDriverHealthStatusConfigurationRequired,
EfiDriverHealthStatusFailed,
EfiDriverHealthStatusReconnectRequired,
EfiDriverHealthStatusRebootRequired
} EFI_DRIVER_HEALTH_STATUS;
EﬁDriverHealthStatusHealthy
The controller is in a healthy state.
EﬁDriverHealthStatusRepairRequired
The controller requires a repair operation that will take an extended period of time to perform. The EFI Boot Manager
is required to call the Repair() function when this state is detected. After the Repair() function completed, the health
status may be EﬁDriverHealthStatusHealthy ,EﬁDriverHealthStatusConﬁgurationRequired , orEﬁDriverHealthSta-
tusFailed .
EﬁDriverHealthStatusConﬁgurationRequired
The controller requires the user to make software or hardware conﬁguration changes in order to put the controller
into a healthy state. The set of software conﬁguration changes are speciﬁed by the FormHiiHandle and FormSetGuid
parameters. The EFI Boot Manager may call the EFI_FORM_BROWSER2_PROTOCOL.SendForm() function to
display conﬁguration information and allow the user to make the required conﬁguration changes. The HII form is
the ﬁrst enabled form in the form set class EFI_HII_DRIVER_HEALTH_FORMSET_GUID , which is installed on the
returned HII handle FormHiiHandle . The MessageList parameter may be used to identify additional user conﬁguration
operations required to place the controller in a healthy state. After the FormHiiHandle andMessageList have been
processed by the EFI Boot Manager, the health status may be EﬁDriverHealthStatusHealthy ,
EﬁDriverHealthStatusConﬁgurationRequired ,
EﬁDriverHealthStatusRepairRequired ,

EﬁDriverHealthStatusFailed ,
EﬁDriverHealthStatusReconnectRequired , or
EﬁDriverHealthStatusRebootRequired .
EﬁDriverHealthStatusFailed
The controller is in a failed state, and there no actions that can place the controller into a healthy state. This controller
can not be used as a boot device and no boot devices behind this controller can be used as a boot device.
EﬁDriverHealthStatusReconnectRequired
A hardware and/or software conﬁguration changewas performed by the user, and the controller needs to bereconnected
before the controller can be placed in ahealthy state. The EFI Boot Manager is required to callthe EFI Boot Service
DisconnectController() followed bythe EFI Boot Service ConnectController() to reconnect thecontroller.
EﬁDriverHealthStatusRebootRequired
A hardware and/or software conﬁguration change was performed by the user, and the controller requires the entire
platform to be rebooted before the controller can be placed in a healthy state. The EFI Boot Manager should complete
11.10. EFI Driver Health Protocol 373Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
the conﬁguration and repair operations on all the controllers that are not in a healthy state before rebooting the system.
// EFI_DRIVER_HEALTH_HII_MESSAGE
EFI_HII_HANDLE HiiHandle;
EFI_STRING_ID StringId;
UINT64 MessageCode;
} EFI_DRIVER_HEALTH_HII_MESSAGE;
HiiHandle TheEFI_HII_HANDLE that was returned by EFI_HII_DATABASE_PROTOCOL.NewPackageList() when
the string pack containing StringId was registered with the HII Database.
StringId The identiﬁer for a single string token in the string pack associated with HiiHandle.
MessageCode 64-bit numeric value of the warning/error speciﬁed by this message. A value of 0x0000000000000000
is used to indicate that MessageCode is not speciﬁed.
The values 0x0000000000000001 to0x0fffffffffffffff are reserved for allocation by the UEFI Speciﬁcation.
The values 0x1000000000000000 to0x1fffffffffffffff are reserved for IHV-developed drivers.
The values 0x8000000000000000 to0x8fffffffffffffff is reserved for platform/OEM drivers.
All other values are reserved and should not be used.
EFI_SUCCESS The health status of the controller speciﬁed by ControllerHandle and Child-
Handle was returned in HealthStatus. A list of warning and error messages
may be optionally returned in MessageList, and an HII Form may be op-
tionally speciﬁed by FormHiiHandle.
EFI_UNSUPPORTED ControllerHandle is not NULL, and the controller speciﬁed by Controller-
Handle and ChildHandle is not currently being managed by the driver spec-
iﬁed by This.
EFI_UNSUPPORTED ControllerHandle is NULL and there are no devices being managed by the
driver.
EFI_INV ALID_PARAMETER HealthStatus is NULL.
EFI_OUT_OF_RESOURCES MessageList is not NULL, and there are not enough resource available to
allocate memory for MessageList.
11.10.3 EFI_DRIVER_HEALTH_PROTOCOL.Repair()
Summary
Performs a repair operation on a controller in the platform. This function can optionally report repair progress infor-
mation back to the platform.
Prototype
typedef
(EFIAPI *EFI_DRIVER_HEALTH_REPAIR) (
11.10. EFI Driver Health Protocol 374Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_DRIVER_HEALTH_REPAIR_NOTIFY RepairNotify OPTIONAL
);
ControllerHandle The handle of the controller to repair.
ChildHandle The handle of the child controller to repair. This is an optional parameter that may be NULL . It will be
NULL for device drivers. It will also be NULL for bus drivers when an attempt is made to repair a bus controller.
If will not be NULL when an attempt is made to repair a child controller produced by the driver.
RepairNotify A notiﬁcation function that may be used by a driver to report the progress of the repair operation. This
is an optional parameter that may be NULL .
This function repairs the controller speciﬁed by ControllerHandle and ChildHandle . If the driver speci-
ﬁed by This is not currently managing the controller speciﬁed by ControllerHandle and ChildHandle , then
EFI_UNSUPPORTED is returned. If there are not enough resource available to complete the repair operation, then
EFI_OUT_OF_RESOURCES is returned. Otherwise, EFI_SUCCESS is returned. A return value of EFI_SUCCESS
does not guarantee that the controller is in a healthy state. The EFI Boot Manager must call the GetHealthStatus()
function to determine the result of the repair operation.
IfRepairNotify is not NULL , and the repair operation requires an extended period of time to execute, then the driver
performing the repair operation may intermittently call the RepairNotify function to inform the EFI Boot Manager of
the progress of the repair operation. The RepairNotify function take two parameters to specify the current progress
value and the limit value. These two values may be used by the EFI Boot Manager to present status information for
the current repair operation.
// EFI_DRIVER_HEALTH_REPAIR_NOTIFY
typedef
(EFIAPI *EFI_DRIVER_HEALTH_REPAIR_NOTIFY) (
IN UINTN Value,
IN UINTN Limit
);
Value A value between 0 and Limit that identiﬁes the current progress of the repair operation.
Limit The maximum value of Value for the current repair operation. If Limit is 0, then the completion progress is
indeterminate. For example, a driver that wants to specify progress in percent would use a Limit value of 100.
EFI_SUCCESS An attempt to repair the controller speciﬁed by ControllerHandle and Child-
Handle was performed. The result of the repair operation can bet deter-
mined by calling GetHealthStatus().
ﬁed by ControllerHandle and ChildHandle.
EFI_OUT_OF_RESOURCES There are not enough resources to perform the repair operation.
11.10. EFI Driver Health Protocol 375Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.10.4 UEFI Boot Manager Algorithms
This section contains example algorithms that a UEI Boot Manager or UEFI Application could use to interact with
one or more instances of the EFI Driver Health Protocol present in the platform.
11.10.4.1 All Controllers Healthy
This section contains example algorithms that a UEFI Boot Manager or UEFI Application could use to interact with
The following algorithm collects all the EFI Driver Health Protocols currently present in the EFI Handle Database, and
queries each EFI Driver Health Protocol to determine if one or more of the controllers managed by each EFI Driver
Health Protocol instance are not healthy. The variable AllHealthy isTRUE if all the controllers in the platform are
healthy. AllHealthy isFALSE if one of more of the controllers in the platform are not healthy.
UINTN NoHandles;
EFI_HANDLE *Handles;
UINTN Index;
EFI_DRIVER_HEALTH_PROTOCOL *DriverHealth;
BOOLEAN AllHealthy;
ByProtocol,
&gEfiDriverHealthProtocolGuid,
NULL,
&NoHandles,
&Handles
);
return;
}
AllHealthy = TRUE;
for (Index = 0; Index < NoHandles; Index++) {
Status = gBS->HandleProtocol (
Handles[Index],
(VOID \ )&DriverHealth
);
Status = DriverHealth->GetHealthStatus (
DriverHealth,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL
);
AllHealthy = FALSE;
}
}
}
11.10. EFI Driver Health Protocol 376Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.10.4.2 Process a Controller Until Terminal StateReached
The following algorithm processes a single controller using the EFI Driver Health Protocol associated with that con-
troller. This algorithm continues to query the GetHealthStatus() service until one of the legal terminal states of the
EFI Driver Health Protocol is reached. This may require the processing of HII Messages, HII Form, and invocation of
repair operations.
EFI_DRIVER_HEALTH_HEALTH_STATUS HealthStatus;
EFI_DRIVER_HEALTH_HII_MESSAGE *MessageList;
EFI_HII_HANDLE FormHiiHandle;
do {
HealthStatus = EfiDriverHealthStatusHealthy;
&HealthStatus,
&MessageList,
&FormHiiHandle
);
ProcessMessages (MessageList);

}
}
}
do {
);
if(HealthStatus == EfiDriverHealthStatusRepairRequired) {
Status = DriverHealth->Repair (
RepairNotify
);
}
if(HealthStatus == EfiDriverHealthStatusConfigurationRequired) {
ProcessForm (FormHiiHandle
}
}while(HealthStatus == EfiDriverHealthStatusConfigurationRequired ||
HealthStatus == EfiDriverHealthStatusRepairRequired);
//
// Check forRebootRequired orReconnectRequired
//
11.10.4.3 Repair Notiﬁcation Function
The following is an example repair notiﬁcation function.
VOID
RepairNotify (
UINTN Value,
UINTN Limit
)
{
UINTN Percent;
if(Limit == 0) {
11.10. EFI Driver Health Protocol 377Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Print (L"Repair Progress Undefined \n\r");
}else{
Percent = Value *100 / Limit;
Print (L"Repair Progress = %3d%%", Percent);
}
}
11.10.4.4 Process Message List
The following algorithm processes a set of messages returned by the GetHealthStatus() service of the EFI Driver
Health Protocol.
UINTN MessageIndex;
EFI_HII_STRING_PROTOCOL *HiiString;
EFI_STRING MessageString [200];
for (MessageIndex = 0;
MessageList[MessageIndex].HiiHandle != 0;
MessageIndex++) {
MessageLength = sizeof (MessageString);
Status = HiiString->GetString (
HiiString,
NULL,
MessageList[MessageIndex].HiiHandle,
MessageList[MessageIndex].StringId,
MessageString
&MessageLength,
NULL
);
// Log or Print or Display MessageString
}
}
11.10.4.5 Process HII Form
The following algorithm processes an HII Form returned by the GetHealthStatus() service of the EFI Driver Health
Protocol.
EFI_FORM_BROWSER2_PROTOCOL *FormBrowser;
Status = FormBrowser->SendForm (
FormBrowser,
&FormHiiHandle,
1,
&gEfiHiiDriverHealthFormsetGuid,
,
0,
11.10. EFI Driver Health Protocol 378Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NULL,
NULL
);
11.10.5 UEFI Driver Algorithms
A UEFI Driver that supports the EFI Driver Health Protocol will typically make the following changes:
11.10.5.1 Driver Entry Point Updates
Install Driver Health Protocol on the driver image handle.
Register HII String/IFR packs with the HII Database.
• HII String/IFR packs can also be carried in a PE/COFF image extension eliminating the need for the driver to
perform the registration
• The HII String and HII Forms may be produced dynamically when the GetHealthStatus() service is called.
11.10.5.2 Add global variable
Add global variable to track combined health status of all controllers managed by the driver. The variable is TRUE if
all the controllers managed by the driver are healthy. The variable is FALSE if one or more controllers managed by
the drover are not healthy.
11.10.5.3 Update private context structure
Update private context structure to track health status of each controller managed by the driver. This may also include
the current set of HII Strings and HII Forms associated with the controllers that are not healthy.
11.10.5.4 Implement GetHealthStatus() service
Implement GetHealthStatus() service of the EFI Driver Health Protocol
• Make sure only legal state transitions are implemented
• Evaluate conﬁguration data and repair status
• Return HII Strings for message(s) associated with thecurren t state
• If conﬁguration required, return HII Form to be processed
11.10. EFI Driver Health Protocol 379Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.10.5.5 Implement Repair() service
Implement Repair() service of the EFI Driver Health Protocol
• Calling Repair Notiﬁcation callback is optional, but recommended.
• Update health status in private context structure before returning
11.11 EFI Adapter Information Protocol
This section provides a detailed description of the EFI_ADAPTER_INFORMATION_PROTOCOL . The EFI Adapter
Information Protocol is used to dynamically and quickly discover or set device information for an adapter. The
discovery of information and state of an adapter should be quick and only return dynamic information. The information
should never be cached or stale. The setting information for the adapter should also be fast and simple. The only
information that should be set is operating state information, like setting a speed. This protocol is meant to be light
weight and non-blocking.
11.11.1 EFI_ADAPTER_INFORMATION_PROTOCOL
Summary
Since this protocol will return and set information for the adapter, the adapter device driver must publish the
EFI_ADAPTER_INFORMATION_PROTOCOL .
There are many kinds of adapters. The set and get adapter information functions should be used to determine the
current state of the adapter, or to set a state for an adapter, like device speed.
GUID
#define EFI_ADAPTER_INFORMATION_PROTOCOL_GUID \
{ 0xE5DD1403, 0xD622, 0xC24E, \
{ 0x84, 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 } }
typedef struct _EFI_ADAPTER_INFORMATION_PROTOCOL {
EFI_ADAPTER_INFO_GET_INFO GetInformation;
EFI_ADAPTER_INFO_SET_INFO SetInformation;
EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES GetSupportedTypes;
} EFI_ADAPTER_INFORMATION_PROTOCOL;
GetInformation Gets device state information from adapter. See GetInformation() for more function description.
SetInformation Sets device information for adapter. See SetInformation() for more function description.
GetSupportedTypes Gets a list of supported information types for this instance of the protocol.
TheEFI_ADAPTER_INFORMATION_PROTOCOL is used to get or set the state for an adapter.
11.11. EFI Adapter Information Protocol 380Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.11.2 EFI_ADAPTER_INFORMATION_PROTOCOL.EFI_ADAPTER_GET_INFO()
Summary
Returns the current state information for the adapter.
Prototype
typedef
(EFIAPI *EFI_ADAPTER_INFO_GET_INFO) (
IN EFI_ADAPTER_INFORMATION_PROTOCOL *This,
IN EFI_GUID *InformationType,
OUT VOID **InformationBlock,
OUT UINTN *InformationBlockSize
);
This A pointer to the EFI_ADAPTER_INFORMATION_PROTOCOL instance.
InformationType A pointer to an EFI_GUID that deﬁnes the contents of InformationBlock . The caller must use the
InformationType to specify the information it needs to retrieve from this service and to determine how to parse
theInformationBlock . The driver should not attempt to free InformationType .
InformationBlock This service returns a pointer to the buffer with the InformationBlock structure which contains
details about the data speciﬁc to InformationType . This structure is deﬁned based on the type of data returned,
and will be different for different data types. This service and caller decode this structure and its contents based
onInformationType . This buffer is allocated by this service, and it is the responsibility of the caller to free it
after using it. Ignored if InformationBlockSize is 0.
InformationBlockSize The driver returns the size of the InformationBlock in bytes.
TheGetInformation() function returns information of type InformationType from the adapter. If an adapter does not
support the requested informational type, then EFI_UNSUPPORTED is returned. If an adapter does not contain
Information for the requested InformationType, it ﬁlls InformationBlockSize with 0 and returns EFI_NOT_FOUND.
EFI_SUCCESS TheInformationType information was retrieved.
EFI_UNSUPPORTED TheInformationType is not known.
EFI_NOT_FOUND Information is not available for the requested information type.
EFI_DEVICE_ERROR The device reported an error.
EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources
EFI_INV ALID_PARAMETER This isNULL
EFI_INV ALID_PARAMETER InformationBlock isNULL
EFI_INV ALID_PARAMETER InformationBlockSize isNULL
11.11. EFI Adapter Information Protocol 381Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11.11.3 EFI_ADAPTER_INFORMATION_PROTOCOL.EFI_ADAPTER_INFO_SET_INFO()
Summary
Sets state information for an adapter.
Prototype
typedef
(EFIAPI *EFI_ADAPTER_INFO_SET_INFO) (
IN VOID *InformationBlock,
IN UINTN InformationBlockSize
);
InformationType to specify the information it wants the service.
InformationBlock A pointer to the InformationBlock structure which contains details about the data speciﬁc to Infor-
mationType . This structure is deﬁned based on the type of data sent, and will be different for different data types.
The driver and caller decode this structure and its contents based on InformationType . This buffer is allocated

Summary
Prototype
typedef
);
by the caller. It is the responsibility of the caller to free it after the caller has set the requested parameters.
InformationBlockSize The size of the InformationBlock in bytes.
TheSetInformation() function sends information of type InformationType for an adapter. If an adapter does not support
the requested informational type, then EFI_UNSUPPORTED is returned.
EFI_SUCCESS The information was received and interpreted successfully.
EFI_WRITE_PROTECTED The InformationType cannot be modiﬁed using
EFI_ADAPTER_INFO_SET_INFO()
11.11.4 EFI_ADAPTER_INFORMATION_PROTOCOL. EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES()
Summary
Get a list of supported information types for this instance of the protocol.
Prototype
typedef
(EFIAPI *EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES) (
11.11. EFI Adapter Information Protocol 382Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
OUT EFI_GUID **InfoTypesBuffer,
OUT UINTN *InfoTypesBufferCount
) ;
InfoTypesBuffer A pointer to the array of InformationType GUIDs that are supported by This. This buffer is allocated
by this service, and it is the responsibility of the caller to free it after using it
InfoTypesBufferCount A pointer to the number of GUIDs present in InfoTypesBuffer .
TheGetSupportedTypes() function returns a list of InformationType GUIDs that are supported on an adapter with this
instance of EFI_ADAPTER_INFORMATION_PROTOCOL . The list is returned in InfoTypesBuffer , and the number
of GUID pointers in InfoTypesBuffer is returned in InfoTypesBufferCount .
EFI_SUCCESS The list of information type GUIDs that are supported on this adapter was
returned in InfoTypesBuffer . The number of information type GUIDs was
returned in InfoTypesBufferCount .
EFI_INV ALID_PARAMETER InfoTypesBuffer isNULL
EFI_INV ALID_PARAMETER InfoTypesBufferCount isNULL
EFI_OUT_OF_RESOURCES There is not enough pool memory to store the results
11.12 EFI Adapter Information Protocol Information Types
Note :In addition to the information block types deﬁned in this section, driver writers may deﬁne additional infor-
mation type blocks for their own use provided all such blocks are each identiﬁed by a unique GUID created by the
deﬁner .
Clients of the protocol should ignore any unrecognized block types returned by GetSupportedTypes() .
11.12.1 Network Media State
For network adapters, the EFI_ADAPTER_INFORMATION_PROTOCOL must be installed on the same handle as
the UNDI protocol. If SNP or MNP protocol, instead of the UNDI protocol, is installed on adapter handle, then the
EFI_ADAPTER_INFORMATION_PROTOCOL must be installed on the same handle as the SNP or MNP protocol.
InformationType
#define EFI_ADAPTER_INFO_MEDIA_STATE_GUID \
{0xD7C74207, 0xA831, 0x4A26 \
{0xB1,0xF5,0xD1,0x93,0x06,0x5C,0xE8,0xB6}}
Corresponding InformationBlock :
11.12. EFI Adapter Information Protocol Information Types 383Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_STATUS MediaState;
} EFI_ADAPTER_INFO_MEDIA_STATE;
MediaState Returns the current media state status. MediaState can have any of the following values:
EFI_SUCCESS : There is media attached to the network adapter.
EFI_NOT_READY : This detects a bounced state. There was media attached to the network adapter, but it was
removed and is trying to attach to the network adapter again. If re-attached, the status will be updated to
EFI_SUCCESS later.
EFI_NO_MEDIA : There is not any media attached to the network adapter.
11.12.2 Network Boot
For iSCSI and FCoE HBA adapters, the EFI_ADAPTER_INFORMATION_PROTOCOL must be installed on the same
handle as the EFI_EXT_SCSI_PASS_THRU_PROTOCOL . When the EFI_EXT_SCSI_PASS_THRU_PROTOCOL
cannot be installed because the adapter was not adequately conﬁgured, or if the relevant SCSI bus han-
dles cannot be produced, this information must be installed on the controller handle that has been passed to
the adapter Pass Thru Driver’s EFI_DRIVER_BINDING_PROTOCOL.Start() function . This will typically be
a handle with the EFI_PCI_IO_PROTOCOL and EFI_DEVICE_PATH_PROTOCOL . If the handle with the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL is produced at a later time, the information on the controller handle must
be uninstalled so as to avoid duplicate information.
#define EFI_ADAPTER_INFO_NETWORK_BOOT_GUID \
{0x1FBD2960, 0x4130, 0x41E5,\
{0x94,0xAC,0xD2, 0xCF, 0x03, 0x7F, 0xB3, 0x7C}}
Corresponding InformationBlock
BOOLEAN iSsciIpv4BootCapablity;
BOOLEAN iScsiIpv6BootCapablity;
BOOLEAN FCoeBootCapablity;
BOOLEAN OffloadCapability;
BOOLEAN iScsiMpioCapability
BOOLEAN iScsiIpv4Boot;
BOOLEAN iScsiIpv6Boot;
BOOLEAN FCoeBoot;
} EFI_ADAPTER_INFO_NETWORK_BOOT;
iScsiIpv4BootCapablity TRUE if the adapter supports booting from iSCSI IPv4 targets.
iScsiIpv6BootCapablity TRUE if the adapter supports booting from iSCSI IPv6 targets.
FCoeBootCapablity TRUE if the adapter supports booting from FCoE targets.
OfﬂoadCapability TRUE if the adapter supports an ofﬂoad engine (such as TCP Ofﬂoad Engine (TOE) for its iSCSI
or FCoE boot operations.
11.12. EFI Adapter Information Protocol Information Types 384Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
iScsiMpioCapability TRUE if the adapter supports multipath I/O (MPIO) for its iSCSI boot operations.
iScsiIpv4Boot TRUE if the adapter is currently conﬁgured to boot from iSCSI IPv4 targets.
iScsiIpv6Boot TRUE if the adapter is currently conﬁgured to boot from iSCSI IPv6 targets.
FCoeBoot TRUE if the adapter is currently conﬁgured to boot from FCoE targets.
Note :The adapter should set the iScsiIpv4BootCapablity, iScsiIpv6BootCapablity, or FCoeBootCapablity ﬁelds to
TRUE if it supports that boot capability, even if that capability is currently disabled or not conﬁgured .
11.12.3 SAN MAC Address
Summary
This information block for the EFI_ADAPTER_INFORMATION_PROTOCOL supports ascertaining the SAN MAC
address for an FCOE-aware network interface controller. This address is the Fabric-Provided MAC Address (FPMA)
that gets assigned to the adapter port after the fabric login.
Note :An instance of the EFI_ADAPTER_INFORMATION_PROTOCOL supporting this GUID must be installed on
the same handle as the EFI_EXT_SCSI_PASS_THRU_PROTOCOL when it is produced. However, this address is
available to the adapter only when the fabric login has occurred, so in cases where the login cannot happen, where
the adapter was not adequately conﬁgured, or if the relevant SCSI bus handles cannot be produced, this information
type may not be produced .
SAN MAC address information InformationType
#define EFI_ADAPTER_INFO_SAN_MAC_ADDRESS_GUID \
{0x114da5ef, 0x2cf1, 0x4e12,\
{0x9b, 0xbb, 0xc4, 0x70, 0xb5, 0x52, 0x05, 0xd9}}
EFI_MAC_ADDRESS SanMacAddress;
} EFI_ADAPTER_INFO_SAN_MAC_ADDRESS;
SanMacAddress Returns the SAN MAC address for the adapter.
11.12.4 IPV6 Support from UNDI
For network adapters, the EFI_ADAPTER_INFORMATION_PROTOCOL must be installed on the same handle as the
UNDI protocol.
•Ipv6Support returns capability of UNDI to support IPV6 trafﬁc.
•Ipv6Support can have any of the following values: :
TRUE : The UNDI supports IPV6.
FALSE : This UNDI does not support IPV6 trafﬁc.
Information Type
#define EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT_GUID \
{ 0x4bd56be3, 0x4975, 0x4d8a, \
{0xa0, 0xad, 0xc4, 0x91, 0x20, 0x4b, 0x5d, 0x4d}}
11.12. EFI Adapter Information Protocol Information Types 385Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BOOLEAN Ipv6Support;
} EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT;
11.12.5 Network Media Type
#define EFI_ADAPTER_INFO_MEDIA_TYPE_GUID \
{ 0x8484472f, 0x71ec, 0x411a, \
{ 0xb3, 0x9c, 0x62, 0xcd, 0x94, 0xd9, 0x91, 0x6e }}
Corresponding InformationBlock:
UINT8 MediaType;
} EFI_ADAPTER_INFO_MEDIA_TYPE;
MediaType indicates the current media type, and can have any of the following values:
1: Ethernet Network Adapter
2: Ethernet Wireless Network Adapter
3~255: Reserved
11.12.6 Coherent Device Attribute Table (CDAT) Type
This section deﬁnes Adapter Information Protocol type for Coherent Device Attribute Table (CDAT). Compute Express

Link (CXL) and other CPU-to-Memory interconnects enable coherent memory devices or coherent accelerator devices
to be attached to the CPU. Unlike memory DIMMs, the system software or ﬁrmware may not have apriori knowledge
of the attributes of memory located on these devices and would beneﬁt from the device directly exposing the NUMA
attributes such as latency and bandwidth characteristics. The necessary data structures are deﬁned in the Coherent
Device Attribute Table (CDAT) structures. For more information, refer to “Links to UEFI-Related Documents” (*
http://ueﬁ.org/ueﬁ ) under the heading “Coherent Device Attribute Table (CDAT) Speciﬁcation”.
Note :For CXL devices that support coherent memory, the EFI_ADAPTER_INFORMATION_PROTOCOL instance
supporting this type may be installed by the EFI driver associated with this device on the device controller handle.
This may happen during the driver initialization in the EFI_IMAGE_ENTRY_POINT of the driver, allowing for the
CDAT structures to be published without relying on the Driver Model platform connect policy .
#define EFI_ADAPTER_INFO_CDAT_TYPE_GUID \\
{0x77af24d1, 0xb6f0, 0x42b9, \\
{0x83, 0xf5, 0x8f, 0xe6, 0xe8, 0x3e, 0xb6, 0xf0}}
11.12. EFI Adapter Information Protocol Information Types 386Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINTN CdatSize;
UINT8 Cdat[];
} EFI_ADAPTER_INFO_CDAT_TYPE_TYPE;
CdatSize of the Cdat structure, in bytes.
CdatCoherent Device Attribute Table (CDAT) structures.
11.12. EFI Adapter Information Protocol Information Types 387CHAPTER
TWELVE
PROTOCOLS — CONSOLE SUPPORT
This section explores console support protocols, including SimpleText Input, Simple Text Output, Simple Pointer,
Serial IO, andGraphics Output protocols.
12.1 Console I/O Protocol
This section deﬁnes the Console I/O protocol. This protocol isused to handle input and output of text-based information
intended for the system user during the operation of code in the boot services environment. Also included here are the
deﬁnitions of three console devices: one for input and one each for normal output and errors.
These interfaces are speciﬁed by function call deﬁnitions to allow maximum ﬂexibility in implementation. For ex-
ample, there is no requirement for compliant systems to have a keyboard or screen directly connected to the system.
Implementations may choose to direct information passed using these interfaces in arbitrary ways provided that the se-
mantics of the functions are preserved (in other words, provided that the information is passed to and from the system
user).
12.1.1 Overview
The UEFI console is built out of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL and the
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL . These two protocols implement a basic text-based console that
allows platform ﬁrmware, applications written to this speciﬁcation, and UEFI OS loaders to present information
to and receive input from a system administrator. The UEFI console supported 16-bit Unicode character codes, a
simple set of input control characters (Scan Codes), and a set of output-oriented programmatic interfaces that give
functionality equivalent to an intelligent terminal. The console does not support pointing devices on input or bitmaps
on output.
This speciﬁcation requires that the EFI_SIMPLE_TEXT_INPUT_PROTOCOL support the same languages as the cor-
responding EFI_ SIMPLE_TEXT_OUTPUT_PROTOCOL . The EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL is rec-
ommended to support at least the printable Basic Latin Unicode character set to enable standard terminal emulation
software to be used with an EFI console. The Basic Latin Unicode character set implements a superset of ASCII that
has been extended to 16-bit characters. Any number of other Unicode character sets may be optionally supported.
388Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
12.1.2 ConsoleIn Deﬁnition
TheEFI_SIMPLE_TEXT_INPUT_PROTOCOL deﬁnes an input stream that contains Unicode characters and required
EFI scan codes. Only the control characters deﬁned in Supported Unicode Control Characters have meaning in the
Unicode input or output streams. The control characters are deﬁned to be characters U+0000 through U+001F. The
input stream does not support any software ﬂow control.
Table 12.1: Supported Unicode Control Characters
Mnemonic Unicode Description
Null U+0000 Null character ignored when received.
BS U+0008 Backspace. Moves cursor left one column. If the cursor is at the left
margin, no action is taken.
TAB U+0x0009 Tab.
LF U+000A Linefeed. Moves cursor to the next line.
CR U+000D Carriage Return. Moves cursor to left margin of the current line.
The input stream supports Scan Codes in addition to Unicode characters. If the Scan Code is set to 0x00 then the
Unicode character is valid and should be used. If the Scan Code is set to a non-0x00 value it represents a special key
as deﬁned by the Table EFI Scan Codes for EFI_SIMPLE_TEXT_INPUT_PROTOCOL .
12.2 Simple Text Input Ex Protocol
The Simple Text Input Ex protocol deﬁnes an extension to the Simple Text Input protocol which enables various new
capabilities describes in this section.
12.2.1 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL
Summary
This protocol is used to obtain input from the ConsoleIn device. The EFI speciﬁcation requires
that the EFI_SIMPLE_TEXT_INPUT_PROTOCOL supports the same languages as the corresponding
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.
GUID
#define EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID \
{0xdd9e7534, 0x7762, 0x4698, \
{0x8c, 0x14, 0xf5, 0x85, 0x17, 0xa6, 0x25, 0xaa}}
typedef struct _EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL {
EFI_INPUT_RESET_EX Reset;
EFI_INPUT_READ_KEY_EX ReadKeyStrokeEx;
EFI_EVENT WaitForKeyEx;
EFI_SET_STATE SetState;
EFI_REGISTER_KEYSTROKE_NOTIFY RegisterKeyNotify;
EFI_UNREGISTER_KEYSTROKE_NOTIFY UnregisterKeyNotify;
} EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL;
Reset Reset the ConsoleIn device. See Reset().
12.2. Simple Text Input Ex Protocol 389Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ReadKeyStrokeEx Returns the next input character. See ReadKeyStrokeEx() .
WaitForKeyEx Event to use with WaitForEvent() to wait for a key to be available. An Event will only be triggered if
KeyData.Key has information contained within it.
SetState Set the EFI_KEY_TOGGLE_STATE state settings for the input device.
RegisterKeyNotify Register a notiﬁcation function to be called when a given key sequence is hit.
UnregisterKeyNotify Removes a speciﬁc notiﬁcation function.
TheEFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL is used on the ConsoleIn device. It is an extension to the Simple
Text Input protocol which allows a variety of extended shift state information to be returned.
12.2.2 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.Reset()
Summary
Resets the input device hardware.
Prototype
typedef
(EFIAPI *EFI_INPUT_RESET_EX) (
IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,
IN BOOLEAN ExtendedVerification
);
This A pointer to the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL instance. Type
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL is deﬁned in this section.
ExtendedVeriﬁcation Indicates that the driver may perform a more exhaustive veriﬁcation operation of the device
during reset.
TheReset() function resets the input device hardware.
The implementation of Reset is required to clear the contents of any input queues resident in memory used for buffering
keystroke data and put the input stream in a known empty state.
As part of initialization process, the ﬁrmware/device will make a quick but reasonable attempt to verify that the device
is functioning. If the ExtendedVeriﬁcation ﬂag is TRUE the ﬁrmware may take an extended amount of time to verify
the device is operating on reset. Otherwise the reset operation is to occur as quickly as possible.
The hardware veriﬁcation process is not deﬁned by this speciﬁcation and is left up to the platform ﬁrmware or driver
to implement.
EFI_SUCCESS The device was reset.
EFI_DEVICE_ERROR The device is not functioning correctly and could not be reset.
12.2. Simple Text Input Ex Protocol 390Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
12.2.3 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.ReadKeyStrokeEx()
Summary
Reads the next keystroke from the input device.
Prototype
typedef
(EFIAPI *EFI_INPUT_READ_KEY_EX) (
OUT EFI_KEY_DATA *KeyData
);
KeyData A pointer to a buffer that is ﬁlled in with the keystroke state data for the key that was pressed. Type
EFI_KEY_DATA is deﬁned in “Related Deﬁnitions” below.
//******************************************
// EFI_KEY_DATA
EFI_INPUT_KEY Key;
EFI_KEY_STATE KeyState;
} EFI_KEY_DATA

Summary
Prototype
typedef
);
Key The EFI scan code and Unicode value returned from the input device.
KeyState The current state of various toggled attributes as well as input modiﬁer values.
//*****************************************************
// EFI_KEY_STATE
//
// Any Shift orToggle State that isvalid should have
// high order bit set.
//
typedef struct EFI_KEY_STATE {
UINT32 KeyShiftState;
EFI_KEY_TOGGLE_STATE KeyToggleState;
} EFI_KEY_STATE;
KeyShiftState Reﬂects the currently pressed shift modiﬁers for the input device. The returned value is valid only if
the high order bit has been set.
KeyToggleState Reﬂects the current internal state of various toggled attributes. The returned value is valid only if
#define EFI_SHIFT_STATE_VALID 0x80000000
#define EFI_RIGHT_SHIFT_PRESSED 0x00000001
#define EFI_LEFT_SHIFT_PRESSED 0x00000002
#define EFI_RIGHT_CONTROL_PRESSED 0x00000004
#define EFI_LEFT_CONTROL_PRESSED 0x00000008
12.2. Simple Text Input Ex Protocol 391Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_RIGHT_ALT_PRESSED 0x00000010
#define EFI_LEFT_ALT_PRESSED 0x00000020
#define EFI_RIGHT_LOGO_PRESSED 0x00000040
#define EFI_LEFT_LOGO_PRESSED 0x00000080
#define EFI_MENU_KEY_PRESSED 0x00000100
#define EFI_SYS_REQ_PRESSED 0x00000200
// EFI_KEY_TOGGLE_STATE
typedef UINT8 EFI_KEY_TOGGLE_STATE;
#define EFI_TOGGLE_STATE_VALID 0x80
#define EFI_KEY_STATE_EXPOSED 0x40
#define EFI_SCROLL_LOCK_ACTIVE 0x01
#define EFI_NUM_LOCK_ACTIVE 0x02
#define EFI_CAPS_LOCK_ACTIVE 0x04
The ReadKeyStrokeEx() function reads the next keystroke from the input device. If there is no pending keystroke
the function returns EFI_NOT_READY . If there is a pending keystroke, then KeyData.Key.ScanCode is the EFI scan
code deﬁned in EFI Scan Codes for EFI_SIMPLE_TEXT_INPUT_PROTOCOL . The KeyData.Key.UnicodeChar is
the actual printable character or is zero if the key does not represent a printable character (control key, function key,
etc.). The KeyData.KeyState is the modiﬁer shift state for the character reﬂected in KeyData.Key.UnicodeChar or
KeyData.Key.ScanCode. This function mirrors the behavior of ReadKeyStroke( in the Simple Input Protocol in that a
keystroke will only be returned when KeyData.Key has data within it.
When interpreting the data from this function, it should be noted that if a class of printable characters that are normally
adjusted by shift modiﬁers (e.g. Shift Key + “f” key) would be presented solely as a KeyData.Key.UnicodeChar
without the associated shift state. So in the previous example of a Shift Key + “f” key being pressed, the only pertinent
data returned would be KeyData.Key.UnicodeChar with the value of “F”. This of course would not typically be the case
for non-printable characters such as the pressing of the Right Shift Key + F10 key since the corresponding returned
data would be reﬂected both in the KeyData.KeyState.KeyShiftState andKeyData.Key.ScanCode values.
UEFI drivers which implement the EFI_SIMPLE_TEXT_INPUT_EX protocol are required to return KeyData.Key and
KeyData.KeyState values. These drivers must always return the most current state of KeyData.KeyState.KeyShiftState
andKeyData.KeyState.KeyToggleState . It should also be noted that certain input devices may not be able to produce
shift or toggle state information, and in those cases the high order bit in the respective Toggle and Shift state ﬁelds
should not be active.
If the EFI_KEY_STATE_EXPOSED bit is turned on, then this instance of the EFI_SIMPLE_INPUT_EX_PROTOCOL
supports the ability to return partial keystrokes. With EFI_KEY_STATE_EXPOSED bit enabled, the ReadKeyStrokeEx
function will allow the return of incomplete keystrokes such as the holding down of certain keys which are expressed
as a part of KeyState when there is no Keydata.
EFI_SUCCESS The keystroke information was returned.
EFI_NOT_READY There was no keystroke data available.. Current KeyData.KeyState values
are exposed.
EFI_DEVICE_ERROR The keystroke information was not returned due to hardware errors.
EFI_UNSUPPORTED The device does not support the ability to read keystroke data.
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12.2.4 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.SetState()
Summary
Set certain state for the input device.
Prototype
typedef
(EFIAPI \ *EFI_SET_STATE) (
IN EFI_KEY_TOGGLE_STATE *KeyToggleState
);
KeyToggleState Pointer to the EFI_KEY_TOGGLE_STATE to set the state for the in-
put device. Type EFI_KEY_TOGGLE_STATE is deﬁned in “Related Deﬁnitions” for
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.ReadKeyStrokeEx() , above.
The SetState() function allows the input device hardware to have state settings adjusted. By calling the SetState()
function with the EFI_KEY_STATE_EXPOSED bit active in the KeyToggleState parameter, this will enable the
ReadKeyStrokeEx function to return incomplete keystrokes such as the holding down of certain keys which are
expressed as a part of KeyState when there is no Key data.
EFI_SUCCESS The device state was set appropriately.
EFI_DEVICE_ERROR The device is not functioning correctly and could not have the setting ad-
justed.
EFI_UNSUPPORTED The device does not support the ability to have its state set or the requested
state change was not supported.
12.2.5 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.RegisterKeyNotify()
Summary
Register a notiﬁcation function for a particular keystroke for the input device.
Prototype
typedef
(EFIAPI *EFI_REGISTER_KEYSTROKE_NOTIFY) (
IN EFI_KEY_DATA *KeyData,
IN EFI_KEY_NOTIFY_FUNCTION KeyNotificationFunction,
OUT VOID **NotifyHandle
);
This
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A pointer to the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL instance. Type
KeyData
A pointer to a buffer that is ﬁlled in with the keystroke information for the key that was pressed. If KeyData.Key,
KeyData.KeyState.KeyToggleState and KeyData.KeyState.KeyShiftState are 0, then any incomplete keystroke will
trigger a notiﬁcation of the KeyNotiﬁcationFunction.
KeyNotiﬁcationFunction
Points to the function to be called when the key sequence is typed speciﬁed by KeyData . This notiﬁcation function
should be called at <= TPL_CALLBACK. SeeEFI_KEY_NOTIFY_FUNCTION below.
NotifyHandle
Points to the unique handle assigned to the registered notiﬁcation.
TheRegisterKeystrokeNotify() function registers a function which will be called when a speciﬁed keystroke will occur.
The keystroke being speciﬁed can be for any combination of KeyData.Key orKeyData.KeyState information.
// EFI_KEY_NOTIFY
typedef
(EFIAPI \ *EFI_KEY_NOTIFY_FUNCTION) (
IN EFI_KEY_DATA *KeyData
);
EFI_SUCCESS Key notify was registered successfully.
EFI_OUT_OF_RESOURCES Unable to allocate necessary data structures.
12.2.6 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.UnregisterKeyNotify()
Summary
Remove the notiﬁcation that was previously registered.
Prototype
typedef
(EFIAPI *EFI_UNREGISTER_KEYSTROKE_NOTIFY) (
IN VOID *NotificationHandle
);
**Parameters **
NotiﬁcationHandle The handle of the notiﬁcation function being unregistered.
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TheUnregisterKeystrokeNotify() function removes the notiﬁcation which was previously registered.
EFI_SUCCESS Key notify was unregistered successfully.
EFI_INV ALID_PARAMETER The NotiﬁcationHandle is invalid.
12.3 Simple Text Input Protocol
The Simple Text Input protocol deﬁnes the minimum input required to support the ConsoleIn device.
12.3.1 EFI_SIMPLE_TEXT_INPUT_PROTOCOL
Summary
GUID
#define EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID \
{0x387477c1,0x69c7,0x11d2,\

Summary
GUID
typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL {
EFI_INPUT_RESET Reset;
EFI_INPUT_READ_KEY ReadKeyStroke;
EFI_EVENT WaitForKey;
} EFI_SIMPLE_TEXT_INPUT_PROTOCOL;
Reset Reset the ConsoleIn device, EFI_SIMPLE_TEXT_INPUT_PROTOCOL.Reset() .
ReadKeyStroke Returns the next input character, EFI_SIMPLE_TEXT_INPUT_PROTOCOL.ReadKeyStroke() .
WaitForKey Event to use with EFI_BOOT_SERVICES.WaitForEvent() to wait for a key to be available.
TheEFI_SIMPLE_TEXT_INPUT_PROTOCOL is used on the ConsoleIn device. It is the minimum required protocol
for ConsoleIn.
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12.3.2 EFI_SIMPLE_TEXT_INPUT_PROTOCOL.Reset()
Summary
Prototype
typedef
(EFIAPI *EFI_INPUT_RESET) (
IN EFI_SIMPLE_TEXT_INPUT_PROTOCOL *This,
);
This A pointer to the EFI_SIMPLE_TEXT_INPUT_PROTOCOL instance. Type
EFI_SIMPLE_TEXT_INPUT_PROTOCOL is deﬁned in EFI_SIMPLE_TEXT_INPUT_PROTOCOL
The Reset() function resets the input device hardware.
12.3.3 EFI_SIMPLE_TEXT_INPUT_PROTOCOL.ReadKeyStroke()
Summary
Prototype
typedef
(EFIAPI \ *EFI_INPUT_READ_KEY) (
OUT EFI_INPUT_KEY *Key
);
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Key A pointer to a buffer that is ﬁlled in with the keystroke information for the key that was pressed. Type
EFI_INPUT_KEY is deﬁned in “Related Deﬁnitions” below.
Related Definitions
// EFI_INPUT_KEY
UINT16 ScanCode;
CHAR16 UnicodeChar;
} EFI_INPUT_KEY;
The ReadKeyStroke() function reads the next keystroke from the input device. If there is no pending keystroke the
function returns EFI_NOT_READY . If there is a pending keystroke, then ScanCode is the EFI scan code deﬁned in
EFI Scan Codes for EFI_SIMPLE_TEXT_INPUT_PROTOCOL . The UnicodeChar is the actual printable character or
is zero if the key does not represent a printable character (control key, function key, etc.).
Table 12.8: :widths: 35 70 :class: longtable
EFI_NOT_READY There was no keystroke data available.
12.3.4 ConsoleOut or StandardError
The EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL must implement the same Unicode code pages as the
EFI_SIMPLE_TEXT_INPUT_PROTOCOL . The protocol must also support the Unicode control characters deﬁned in
Supported Unicode Control Characters . The EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL supports special manipu-
lation of the screen by programmatic methods and therefore does not support the EFI scan codes deﬁned in EFI Scan
Codes for EFI_SIMPLE_TEXT_INPUT_PROTOCOL .
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12.4 Simple Text Output Protocol
The Simple Text Output protocol deﬁnes the minimum requirements for a text-based ConsoleOut device. The EFI
speciﬁcation requires that the EFI_SIMPLE_TEXT_INPUT_PROTOCOL support the same languages as the corre-
sponding EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.
12.4.1 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL
Summary
This protocol is used to control text-based output devices.
GUID
#define EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID \
{0x387477c2,0x69c7,0x11d2,\
typedef struct _EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL {
EFI_TEXT_RESET Reset;
EFI_TEXT_STRING OutputString;
EFI_TEXT_TEST_STRING TestString;
EFI_TEXT_QUERY_MODE QueryMode;
EFI_TEXT_SET_MODE SetMode;
EFI_TEXT_SET_ATTRIBUTE SetAttribute;
EFI_TEXT_CLEAR_SCREEN ClearScreen;
EFI_TEXT_SET_CURSOR_POSITION SetCursorPosition;
EFI_TEXT_ENABLE_CURSOR EnableCursor;
SIMPLE_TEXT_OUTPUT_MODE *Mode;
} EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL;
Reset Reset the ConsoleOut device. EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.Reset() .
OutputString Displays the string on the device at the current cursor location. See OutputString()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.OutputString() .
TestString Tests to see if the ConsoleOut device supports this string. See TestString()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.TestString() .
QueryMode Queries information concerning the output device’s supported text mode. See QueryMode()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.QueryMode() .
SetMode Sets the current mode of the output device. EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetMode() .
SetAttribute Sets the foreground and background color of the text that is output.
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetAttribute() .
ClearScreen Clears the screen with the currently set background color. See ClearScreen()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.ClearScreen() .
SetCursorPosition Sets the current cursor position. See SetCursorPosition()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetCursorPosition() .
EnableCursor Turns the visibility of the cursor on/off. See EnableCursor()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.EnableCursor() .
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Mode Pointer to SIMPLE_TEXT_OUTPUT_MODE data. Type SIMPLE_TEXT_OUTPUT_MODE is deﬁned in
“Related Deﬁnitions” below.
The following data values in the SIMPLE_TEXT_OUTPUT_MODE interface are read-only and are changed by using
the appropriate interface functions:
MaxMode The number of modes supported by QueryMode() and SetMode().
Mode The text mode of the output device(s).
Attribute The current character output attribute.
CursorColumn The cursor’s column.
CursorRow The cursor’s row.
CursorVisible The cursor is currently visible or not.
// SIMPLE_TEXT_OUTPUT_MODE
INT32 MaxMode;
// current settings
INT32 Mode;
INT32 Attribute;
INT32 CursorColumn;
INT32 CursorRow;
BOOLEAN CursorVisible;
} SIMPLE_TEXT_OUTPUT_MODE;
The SIMPLE_TEXT_OUTPUT protocol is used to control text-based output devices. It is the minimum required
protocol for any handle supplied as the ConsoleOut or StandardError device. In addition, the minimum supported text
mode of such devices is at least 80 x 25 characters.
A video device that only supports graphics mode is required to emulate text mode functionality. Out-
put strings themselves are not allowed to contain any control codes other than those deﬁned in Sup-
ported Unicode Control Characters . Positional cursor placement is done only via the SetCursorPosition()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetCursorPosition() function. It is highly recommended that text output
to the StandardError device be limited to sequential string outputs. (That is, it is not recommended to use ClearScreen()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.ClearScreen() orSetCursorPosition() on output messages to Standard-
Error.)
If the output device is not in a valid text mode at the time of the EFI_BOOT_SERVICES.HandleProtocol() call, the
device is to indicate that its CurrentMode is -1. On connecting to the output device the caller is required to verify the
mode of the output device, and if it is not acceptable to set it to something it can use.
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12.4.2 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.Reset()
Summary
Resets the text output device hardware.
Prototype
typedef
(EFIAPI \ *EFI_TEXT_RESET) (
IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This,
);
This A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL instance. Type

Error.)
Summary
Prototype
typedef
);
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL is deﬁned in the “Related Deﬁnitions” of
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL
The Reset() function resets the text output device hardware. The cursor position is set to (0, 0), and the screen is
cleared to the default background color for the output device.
EFI_SUCCESS The text output device was reset.
EFI_DEVICE_ERROR The text output device is not functioning correctly and could not be reset.
12.4.3 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.OutputString()
Summary
Writes a string to the output device.
Prototype
typedef
(EFIAPI *EFI_TEXT_STRING) (
IN CHAR16 *String
);
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL is deﬁned in the “Related Deﬁnitions” of Simple Text Output
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Protocol .
String The Null-terminated string to be displayed on the output device(s). All output devices must also support the
Unicode drawing character codes deﬁned in “Related Deﬁnitions.”
// UNICODE DRAWING CHARACTERS
#define BOXDRAW_HORIZONTAL 0x2500
#define BOXDRAW_VERTICAL 0x2502
#define BOXDRAW_DOWN_RIGHT 0x250c
#define BOXDRAW_DOWN_LEFT 0x2510
#define BOXDRAW_UP_RIGHT 0x2514
#define BOXDRAW_UP_LEFT 0x2518
#define BOXDRAW_VERTICAL_RIGHT 0x251c
#define BOXDRAW_VERTICAL_LEFT 0x2524
#define BOXDRAW_DOWN_HORIZONTAL 0x252c
#define BOXDRAW_UP_HORIZONTAL 0x2534
#define BOXDRAW_VERTICAL_HORIZONTAL 0x253c
#define BOXDRAW_DOUBLE_HORIZONTAL 0x2550
#define BOXDRAW_DOUBLE_VERTICAL 0x2551
#define BOXDRAW_DOWN_RIGHT_DOUBLE 0x2552
#define BOXDRAW_DOWN_DOUBLE_RIGHT 0x2553
#define BOXDRAW_DOUBLE_DOWN_RIGHT 0x2554
#define BOXDRAW_DOWN_LEFT_DOUBLE 0x2555
#define BOXDRAW_DOWN_DOUBLE_LEFT 0x2556
#define BOXDRAW_DOUBLE_DOWN_LEFT 0x2557
#define BOXDRAW_UP_RIGHT_DOUBLE 0x2558
#define BOXDRAW_UP_DOUBLE_RIGHT 0x2559
#define BOXDRAW_DOUBLE_UP_RIGHT 0x255a
#define BOXDRAW_UP_LEFT_DOUBLE 0x255b
#define BOXDRAW_UP_DOUBLE_LEFT 0x255c
#define BOXDRAW_DOUBLE_UP_LEFT 0x255d
#define BOXDRAW_VERTICAL_RIGHT_DOUBLE 0x255e
#define BOXDRAW_VERTICAL_DOUBLE_RIGHT 0x255f
#define BOXDRAW_DOUBLE_VERTICAL_RIGHT 0x2560
#define BOXDRAW_VERTICAL_LEFT_DOUBLE 0x2561
#define BOXDRAW_VERTICAL_DOUBLE_LEFT 0x2562
#define BOXDRAW_DOUBLE_VERTICAL_LEFT 0x2563
#define BOXDRAW_DOWN_HORIZONTAL_DOUBLE 0x2564
#define BOXDRAW_DOWN_DOUBLE_HORIZONTAL 0x2565
#define BOXDRAW_DOUBLE_DOWN_HORIZONTAL 0x2566
#define BOXDRAW_UP_HORIZONTAL_DOUBLE 0x2567
#define BOXDRAW_UP_DOUBLE_HORIZONTAL 0x2568
#define BOXDRAW_DOUBLE_UP_HORIZONTAL 0x2569
#define BOXDRAW_VERTICAL_HORIZONTAL_DOUBLE 0x256a
#define BOXDRAW_VERTICAL_DOUBLE_HORIZONTAL 0x256b
#define BOXDRAW_DOUBLE_VERTICAL_HORIZONTAL 0x256c
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// EFI Required Block Elements Code Chart
#define BLOCKELEMENT_FULL_BLOCK 0x2588
#define BLOCKELEMENT_LIGHT_SHADE 0x2591
// EFI Required Geometric Shapes Code Chart
#define GEOMETRICSHAPE_UP_TRIANGLE 0x25b2
#define GEOMETRICSHAPE_RIGHT_TRIANGLE 0x25ba
#define GEOMETRICSHAPE_DOWN_TRIANGLE 0x25bc
#define GEOMETRICSHAPE_LEFT_TRIANGLE 0x25c4
// EFI Required Arrow shapes
#define ARROW_UP 0x2191
#define ARROW_DOWN 0x2193
The OutputString() EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.OutputString() function writes a string to the output
device. This is the most basic output mechanism on an output device. The String is displayed at the current cursor lo-
cation on the output device(s) and the cursor is advanced according to the rules listed in EFI Cursor Location/Advance
Rules .
Table 12.10: EFI Cursor Location/Advance Rules
Null U+0000 Ignore the character, and do not move the cursor.
BS U+0008 If the cursor is not at the left edge of the display, then move the cursor left one column.
LF U+000A If the cursor is at the bottom of the display, then scroll the display one row, and do not
update the cursor position. Otherwise, move the cursor down one row.
CR U+000D Move the cursor to the beginning of the current row.
Other U+XXXX Print the character at the current cursor position and move the cursor right one column.
If this moves the cursor past the right edge of the display, then the line should wrap
to the beginning of the next line. This is equivalent to inserting a CR and an LF. Note
that if the cursor is at the bottom of the display, and the line wraps, then the display
will be scrolled one line.
Note :If desired, the system’s NVRAM environment variables may be used at install time to determine the conﬁgured
locale of the system or the installation procedure can query the user for the proper language support. This is then
used to either install the proper EFI image/loader or to conﬁgure the installed image’s strings to use the proper text
for the selected locale .
EFI_SUCCESS The string was output to the device.
EFI_DEVICE_ERROR The device reported an error while attempting to output the text.
EFI_UNSUPPORTED The output device’s mode is not currently in a deﬁned text mode.
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Table 12.11 – continued from previous page
EFI_WARN_UNKNOWN_GLYPH This warning code indicates that some of the characters in the string could
not be rendered and were skipped.
12.4.4 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.TestString()
Summary
Veriﬁes that all characters in a string can be output to the target device.
Prototype
typedef
(EFIAPI *EFI_TEXT_TEST_STRING) (
);
Protocol .
String The Null-terminated string to be examined for the output device(s).
The TestString() function veriﬁes that all characters in a string can be output to the target device.
This function provides a way to know if the desired character codes are supported for rendering on the
output device(s). This allows the installation procedure (or EFI image) to at least select character codes
that the output devices are capable of displaying. Since the output device(s) may be changed between
boots, if the loader cannot adapt to such changes it is recommended that the loader call OUTPUTSTRING()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.OutputString() with the text it has and ignore any “unsupported” error
codes. Devices that are capable of displaying the Unicode character codes will do so.
EFI_SUCCESS The device(s) are capable of rendering the output string.
EFI_UNSUPPORTED Some of the characters in the string cannot be rendered by one or more of
the output devices mapped by the EFI handle.
12.4.5 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.QueryMode()
Summary
Returns information for an available text mode that the output device(s) supports.
Prototype
typedef
(EFIAPI *EFI_TEXT_QUERY_MODE) (
IN UINTN ModeNumber,
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OUT UINTN *Columns,
OUT UINTN *Rows
);
Protocol .
ModeNumber The mode number to return information on.
Columns, Rows Returns the geometry of the text output device for the request ModeNumber.
The QueryMode() function returns information for an available text mode that the output device(s) supports.

Summary
Prototype
typedef
);
Protocol .
It is required that all output devices support at least 80x25 text mode. This mode is deﬁned to be mode 0. If the output
devices support 80x50, that is deﬁned to be mode 1. All other text dimensions supported by the device will follow as
modes 2 and above. If an output device supports modes 2 and above, but does not support 80x50, then querying for
mode 1 will return EFI_UNSUPPORTED .
EFI_SUCCESS The requested mode information was returned.
EFI_DEVICE_ERROR The device had an error and could not complete the request.
EFI_UNSUPPORTED The mode number was not valid.
12.4.6 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetMode()
Summary
Sets the output device(s) to a speciﬁed mode.
Prototype
typedef
(*EFIAPI EFI_TEXT_SET_MODE) (
IN UINTN ModeNumber
);
Protocol .
ModeNumber The text mode to set.
The SetMode() function sets the output device(s) to the requested mode. On success the device is in the geometry for
the requested mode, and the device has been cleared to the current background color with the cursor at (0,0).
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EFI_SUCCESS The requested text mode was set.
12.4.7 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetAttribute()
Summary
Sets the background and foreground colors for the OutputString(), EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.OutputString()
and ClearScreen() EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.ClearScreen() functions.
Prototype
typedef
(EFIAPI *EFI_TEXT_SET_ATTRIBUTE) (
IN UINTN Attribute
);
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL is deﬁned inthe “Related Deﬁnitions” Simple Text Output
Protocol .
Attribute The attribute to set. Bits 0..3 are the foreground color, and bits 4..6 are the background color. All other bits
are reserved. See “Related Deﬁnitions” below.
//*******************************************************
#define EFI_BLACK 0x00
#define EFI_BLUE 0x01
#define EFI_GREEN 0x02
#define EFI_CYAN 0x03
#define EFI_RED 0x04
#define EFI_MAGENTA 0x05
#define EFI_BROWN 0x06
#define EFI_LIGHTGRAY 0x07
#define EFI_BRIGHT 0x08
#define EFI_DARKGRAY(EFI_BLACK \| EFI_BRIGHT) 0x08
#define EFI_LIGHTBLUE 0x09
#define EFI_LIGHTGREEN 0x0A
#define EFI_LIGHTCYAN 0x0B
#define EFI_LIGHTRED 0x0C
#define EFI_LIGHTMAGENTA 0x0D
#define EFI_YELLOW 0x0E
#define EFI_WHITE 0x0F
#define EFI_BACKGROUND_BLACK 0x00
#define EFI_BACKGROUND_BLUE 0x10
#define EFI_BACKGROUND_GREEN 0x20
#define EFI_BACKGROUND_CYAN 0x30
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#define EFI_BACKGROUND_RED 0x40
#define EFI_BACKGROUND_MAGENTA 0x50
#define EFI_BACKGROUND_BROWN 0x60
#define EFI_BACKGROUND_LIGHTGRAY 0x70
//
// Macro to accept color values intheir raw form to create
// a value that represents both a foreground andbackground
// color ina single byte.
// For Foreground, andEFI_\*valueisvalidfrom EFI_BLACK (0x00)
// to EFI_WHITE (0x0F).
// For Background, only EFI_BLACK, EFI_BLUE, EFI_GREEN,
// EFI_CYAN, EFI_RED, EFI_MAGENTA, EFI_BROWN, andEFI_LIGHTGRAY
// are acceptable.
//
// Donotuse EFI_BACKGROUND_xxx values withthis macro.
//#define EFI_TEXT_ATTR(Foreground,Background) \
((Foreground) | ((Background) << 4))
The SetAttribute() function sets the background and foreground colors for the Out-
putString() EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.OutputString() and ClearScreen()
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.ClearScreen() functions.
The color mask can be set even when the device is in an invalid text mode.
Devices supporting a different number of text colors are required to emulate the above colors to the best of the device’s
EFI_SUCCESS The requested attributes were set.
12.4.8 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.ClearScreen()
Summary
Clears the output device(s) display to the currently selected background color.
Prototype
typedef
(EFIAPI \ *EFI_TEXT_CLEAR_SCREEN) (
IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This
);
Protocol .
The ClearScreen() function clears the output device(s) display to the currently selected background color. The cursor
position is set to (0, 0).
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EFI_UNSUPPORTED The output device is not in a valid text mode.
12.4.9 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetCursorPosition()
Summary
Sets the current coordinates of the cursor position.
Prototype
typedef
(EFIAPI *EFI_TEXT_SET_CURSOR_POSITION) (
IN UINTN Column,
IN UINTN Row
);
Protocol .
Column, Row The position to set the cursor to. Must greater than or equal to zero and less than the number of
columns and rows returned by EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.QueryMode() .
The SetCursorPosition() function sets the current coordinates of the cursor position. The upper left corner of the screen
is deﬁned as coordinate (0, 0).
EFI_UNSUPPORTED The output device is not in a valid text mode, or the cursor position is invalid
for the current mode.
12.4.10 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.EnableCursor()
Summary
Makes the cursor visible or invisible.
Prototype
typedef
(EFIAPI *EFI_TEXT_ENABLE_CURSOR) (
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IN BOOLEAN Visible
);
Protocol .
Visible IfTRUE , the cursor is set to be visible. If FALSE , the cursor is set to be invisible.
The EnableCursor() function makes the cursor visible or invisible.
EFI_DEVICE_ERROR The device had an error and could not complete the request or the device
does not support changing the cursor mode.
EFI_UNSUPPORTED The output device does not support visibility control of the cursor.
12.5 Simple Pointer Protocol
This section deﬁnes the Simple Pointer Protocol and a detailed description of the
EFI_SIMPLE_POINTER_PROTOCOL. The intent of this section is to specify a simple method for accessing
pointer devices. This would include devices such as mice and trackballs.
The EFI_SIMPLE_POINTER_PROTOCOL allows information about a pointer device to be retrieved. This would
include the status of buttons and the motion of the pointer device since the last time it was accessed. This protocol is
attached the device handle of a pointer device, and can be used for input from the user in the preboot environment.
12.5.1 EFI_SIMPLE_POINTER_PROTOCOL
Summary
Provides services that allow information about a pointer device to be retrieved.
GUID
#define EFI_SIMPLE_POINTER_PROTOCOL_GUID \
{0x31878c87,0xb75,0x11d5,\
{0x9a,0x4f,0x00,0x90,0x27,0x3f,0xc1,0x4d}}
typedef struct \_EFI_SIMPLE_POINTER_PROTOCOL {
EFI_SIMPLE_POINTER_RESET Reset;
EFI_SIMPLE_POINTER_GET_STATE GetState;
EFI_EVENT WaitForInput;
EFI_SIMPLE_INPUT_MODE *Mode;
} EFI_SIMPLE_POINTER_PROTOCOL;
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Reset Resets the pointer device. EFI_SIMPLE_POINTER_PROTOCOL.Reset() function description.
GetState Retrieves the current state of the pointer device, EFI_SIMPLE_POINTER_PROTOCOL.GetState() function
WaitForInput Event to use with EFI_BOOT_SERVICES.WaitForEvent() to wait for input from the pointer device.

Summary
GUID
Mode Pointer to EFI_SIMPLE_POINTER_MODE data. The type EFI_SIMPLE_POINTER_MODE is deﬁned in
// EFI_SIMPLE_POINTER_MODE
UINT64 ResolutionX;
UINT64 ResolutionY;
UINT64 ResolutionZ;
BOOLEAN LeftButton;
BOOLEAN RightButton;
} EFI_SIMPLE_POINTER_MODE;
The following data values in the EFI_SIMPLE_POINTER_MODE interface are read-only and are changed by using
ResolutionX The resolution of the pointer device on the x-axis in counts/mm. If 0, then the pointer device does not
support an x-axis.
ResolutionY The resolution of the pointer device on the y-axis in counts/mm. If 0, then the pointer device does not
support a y-axis.
ResolutionZ The resolution of the pointer device on the z-axis in counts/mm. If 0, then the pointer device does not
support a z-axis.
LeftButton TRUE if a left button is present on the pointer device. Otherwise FALSE .
RightButton TRUE if a right button is present on the pointer device. Otherwise FALSE .
The EFI_SIMPLE_POINTER_PROTOCOL provides a set of services for a pointer device that can use used as an input
device from an application written to this speciﬁcation. The services include the ability to reset the pointer device,
retrieve get the state of the pointer device, and retrieve the capabilities of the pointer device.
12.5.2 EFI_SIMPLE_POINTER_PROTOCOL.Reset()
Summary
Resets the pointer device hardware.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_POINTER_RESET) (
IN EFI_SIMPLE_POINTER_PROTOCOL *This,
);
12.5. Simple Pointer Protocol 409Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This A pointer to the EFI_SIMPLE_POINTER_PROTOCOL instance. Type EFI_SIMPLE_POINTER_PROTOCOL
is deﬁned in Simple Pointer Protocol .
This Reset() function resets the pointer device hardware. As part of initialization process, the ﬁrmware/device will
make a quick but reasonable attempt to verify that the device is functioning. If the ExtendedVeriﬁcation ﬂag is TRUE
the ﬁrmware may take an extended amount of time to verify the device is operating on reset. Otherwise the reset
operation is to occur as quickly as possible. The hardware veriﬁcation process is not deﬁned by this speciﬁcation and
is left up to the platform ﬁrmware or driver to implement.
12.5.3 EFI_SIMPLE_POINTER_PROTOCOL.GetState()
Summary
Retrieves the current state of a pointer device.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_POINTER_GET_STATE)
OUT EFI_SIMPLE_POINTER_STATE *State
);
is deﬁned in is deﬁned in the “Related Deﬁnitions” of Simple Pointer Protocol
State A pointer to the state information on the pointer device. Type EFI_SIMPLE_POINTER_STATE is deﬁned in
// EFI_SIMPLE_POINTER_STATE
INT32 RelativeMovementX;
INT32 RelativeMovementY;
INT32 RelativeMovementZ;
} EFI_SIMPLE_POINTER_STATE;
RelativeMovementX The signed distance in counts that the pointer device has been moved along the x-axis. The
actual distance moved is RelativeMovementX / ResolutionX millimeters. If the ResolutionX ﬁeld of the
EFI_SIMPLE_POINTER_MODE see EFI_SIMPLE_POINTER_PROTOCOL structure is 0, then this pointer
device does not support an x-axis, and this ﬁeld must be ignored.
12.5. Simple Pointer Protocol 410Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
RelativeMovementY The signed distance in counts that the pointer device has been moved along the y-axis. The
actual distance moved is RelativeMovementY / ResolutionY millimeters. If the ResolutionY ﬁeld of the
device does not support a y-axis, and this ﬁeld must be ignored.
RelativeMovementZ The signed distance in counts that the pointer device has been moved along the z-axis. The
actual distance moved is RelativeMovementZ / ResolutionZ millimeters. If the ResolutionZ ﬁeld of the
EFI_SIMPLE_POINTER_MODE structure is 0, then this pointer device does not support a z-axis, and this
ﬁeld must be ignored.
LeftButton IfTRUE , then the left button of the pointer device is being pressed. If FALSE , then the left button of
the pointer device is not being pressed. If the LeftButton ﬁeld of the EFI_SIMPLE_POINTER_MODE see
EFI_SIMPLE_POINTER_PROTOCOL structure is FALSE , then this ﬁeld is not valid, and must be ignored.
RightButton IfTRUE , then the right button of the pointer device is being pressed. If FALSE , then the right button
of the pointer device is not being pressed. If the RightButton ﬁeld of the EFI_SIMPLE_POINTER_MODE
structure is FALSE , then this ﬁeld is not valid, and must be ignored.
The GetState() function retrieves the current state of a pointer device. This includes information on the buttons
associated with the pointer device and the distance that each of the axes associated with the pointer device has been
moved. If the state of the pointer device has not changed since the last call to GetState(), then EFI_NOT_READY
is returned. If the state of the pointer device has changed since the last call to GetState(), then the state information
is placed in State, and EFI_SUCCESS is returned. If a device error occurs while attempting to retrieve the state
information, then EFI_DEVICE_ERROR is returned.
EFI_SUCCESS The state of the pointer device was returned in State.
EFI_NOT_READY The state of the pointer device has not changed since the last call to Get-
State().
EFI_DEVICE_ERROR A device error occurred while attempting to retrieve the pointer device’s
current state.
12.6 EFI Simple Pointer Device Paths
AnEFI Simple Pointer Device Paths must be installed on a handle for its services to be available to drivers and
applications written to this speciﬁcation. In addition to the EFI_SIMPLE_POINTER_PROTOCOL, an EFI Device
Path Protocol must also be installed on the same handle. EFI Device Path Protocol for a detailed description of the
EFI_DEVICE_PATH_PROTOCOL.
A device path describes the location of a hardware component in a system from the processor’s point of view. This
includes the list of busses that lie between the processor and the pointer controller. The UEFI Speciﬁcation takes
advantage of the ACPI Speciﬁcation to name system components. The following set of examples eﬁ-device-path-
protocolshows sample device paths for a PS/2* mouse, a serial mouse, and a USB mouse.
The Table below shows an example device path for a PS/2 mouse that is located behind a PCI to ISA bridge that is
located at PCI device number 0x07 and PCI function 0x00, and is directly attached to a PCI root bridge. This device
path consists of an ACPI Device Path Node for the PCI Root Bridge, a PCI Device Path Node for the PCI to ISA
bridge, an ACPI Device Path Node for the PS/2 mouse, and a Device Path End Structure. The _HID and _UID of the
ﬁrst ACPI Device Path Node must match the ACPI table description of the PCI Root Bridge. The shorthand notation
ACPI(PNP0A03,0)/PCI(7,0)/ACPI(PNP0F03,0):
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Table 12.20: PS/2 Mouse Device Path
Byte
0x0A03_HID PNP0A03 - 0x41D0 represents a compressed string ‘PNP’ and
is in the low order bytes. The compression method is described in the
ACPI Speciﬁcation.
0x10 0x01 0x00 PCI Function
0x11 0x01 0x07 PCI Device
0x12 0x01 0x02 Generic Device Path Header - Type ACPI Device Path
0x13 0x01 0x01 Sub type - ACPI Device Path
0x14 0x02 0x0C Length - 0x0C bytes
0x16 0x04 0x41D0,
0x0F03_HID PNP0A03 - 0x41D0 represents a compressed string ‘PNP’ and
0x1A 0x04 0x0000 _UID

Serial Mouse Device Path shows an example device path for a serial mouse that is located on COM 1 behind a PCI
to ISA bridge that is located at PCI device number 0x07 and PCI function 0x00. The PCI to ISA bridge is directly
attached to a PCI root bridge, and the communications parameters for COM 1 are 1200 baud, no parity, 8 data bits, and
1 stop bit. This device path consists of an ACPI Device Path Node for the PCI Root Bridge, a PCI Device Path Node
for the PCI to ISA bridge, an ACPI Device Path Node for COM 1, a UART Device Path Node for the communications
parameters, an ACPI Device Path Node for the serial mouse, and a Device Path End Structure. The _HID and _UID
of the ﬁrst ACPI Device Path Node must match the ACPI table description of the PCI Root Bridge. The shorthand
ACPI(PNP0A03,0)/PCI(7,0)/ACPI(PNP0501,0)/UART(1200,N,8,1)/ACPI(PNP0F01,0)
Table 12.21: Serial Mouse Device Path
Byte Offset Byte Length Data Description
0x04 0x04 0x41D0, |
0x0A03_HID PNP0A03 - 0x41D0 represents the compressed string
‘PNP’ and is encoded in the low order bytes. The compression
method is described in the ACPI Speciﬁcation.
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Table 12.21 – continued from previous page
0x0501_HID PNP0501 - 0x41D0 represents the compressed string
0x1E 0x01 0x03 Generic Device Path Header - Messaging Device Path
0x1F 0x01 0x0E Sub type - UART Device Path
0x20 0x02 0x13 Length - 0x13 bytes
0x22 0x04 0x00 Reserved
0x26 0x08 1200 Baud Rate
0x2E 0x01 0x08 Data Bits
0x2F 0x01 0x01 Parity
0x30 0x01 0x01 Stop Bits
0x31 0x01 0x02 Generic Device Path Header - Type ACPI Device Path
0x32 0x01 0x01 Sub type - ACPI Device Path
0x33 0x02 0x0C Length - 0x0C bytes
0x35 0x04 0x41D0,
0x0F01_HID PNP0F01 - 0x41D0 represents the compressed string
0x39 0x04 0x0000 _UID
0x3D 0x01 0x7F Generic Device Path Header - Type End of Hardware Device
Path
0x3E 0x01 0xFF Sub type - End of Entire Device Path
0x3F 0x02 0x04 Length - 0x04 bytes
SeeUSB Mouse Device Path shows an example device path for a USB mouse that is behind a PCI to USB host
controller that is located at PCI device number 0x07 and PCI function 0x02. The PCI to USB host controller is
directly attached to a PCI root bridge. This device path consists of an ACPI Device Path Node for the PCI Root
Bridge, a PCI Device Path Node for the PCI to USB controller, a USB Device Path Node, and a Device Path End
Structure. The _HID and _UID of the ﬁrst ACPI Device Path Node must match the ACPI table description of the PCI
Root Bridge. The shorthand notation for this device path is:
ACPI(PNP0A03,0)/PCI(7,2)/USB(0,0)
Table 12.22: USB Mouse Device Path
0x0A03_HID PNP0A03 - 0x41D0 represents a compressed
string ‘PNP’ and is in the low order bytes.
0x0C 0x01 0x01 Generic Device Path Header - Type Hardware Device
Path
12.6. EFI Simple Pointer Device Paths 413Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 12.22 – continued from previous page
0x12 0x01 0x03 Generic Device Path Header - Type Messaging Device
Path
0x16 0x01 0x00 USB Port Number
0x17 0x01 0x00 USB Endpoint Number
0x18 0x01 0x7F Generic Device Path Header - Type End of Hardware
12.7 Absolute Pointer Protocol
This section deﬁnes the Absolute Pointer Protocol and a detailed description of the
EFI_ABSOLUTE_POINTER_PROTOCOL . The intent of this section is to specify a simple method for access-
ing absolute pointer devices. This would include devices like touch screens, and digitizers.
TheEFI_ABSOLUTE_POINTER_PROTOCOL allows information about a pointer device to be retrieved. This would
include the status of buttons and the coordinates of the pointer device on the last time it was activated. This protocol
is attached to the device handle of an absolute pointer device, and can be used for input from the user in the preboot
environment.
Supported devices may return 1, 2, or 3 axis of information. The Z axis may optionally be used to return pressure data
measurements derived from user pen force.
All supported devices must support a touch-active status. Supported devices may optionally support a second input
button, for example a pen side-button.
12.7.1 EFI_ABSOLUTE_POINTER_PROTOCOL
Summary
Provides services that allow information about an absolute pointer device to be retrieved.
GUID
#define EFI_ABSOLUTE_POINTER_PROTOCOL_GUID \
{0x8D59D32B, 0xC655, 0x4AE9, \
{0x9B, 0x15, 0xF2, 0x59, 0x04, 0x99, 0x2A, 0x43}}
typedef struct _EFI_ABSOLUTE_POINTER_PROTOCOL {
EFI_ABSOLUTE_POINTER_RESET Reset;
EFI_ABSOLUTE_POINTER_GET_STATE GetState;
EFI_ABSOLUTE_POINTER_MODE *Mode;
} EFI_ABSOLUTE_POINTER_PROTOCOL;
Reset Resets the pointer device. See the Reset() function description.
GetState Retrieves the current state of the pointer device. See the GetState() function description.
12.7. Absolute Pointer Protocol 414Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
WaitForInput Event to use with WaitForEvent() to wait for input from the pointer device.
Mode Pointer to EFI_ABSOLUTE_POINTER_MODE data. The type EFI_ABSOLUTE_POINTER_MODE is de-
ﬁned in “Related Deﬁnitions” below.
// EFI_ABSOLUTE_POINTER_MODE
UINT64 AbsoluteMinX;
UINT64 AbsoluteMinY;
UINT64 AbsoluteMinZ;
UINT64 AbsoluteMaxX;
UINT64 AbsoluteMaxY;
UINT64 AbsoluteMaxZ;
} EFI_ABSOLUTE_POINTER_MODE;
The following data values in the EFI_ABSOLUTE_POINTER_MODE interface are read-only and are changed by
using the appropriate interface functions:
AbsoluteMinX The Absolute Minimum of the device on the x-axis
AbsoluteMinY The Absolute Minimum of the device on the y -axis.
AbsoluteMinZ The Absolute Minimum of the device on the z-axis.
AbsoluteMaxX The Absolute Maximum of the device on the x-axis. If 0, and the AbsoluteMinX is 0, then the pointer
device does not support a x-axis.
AbsoluteMaxY The Absolute Maximum of the device on the y -axis. If 0, and the AbsoluteMinY is 0, then the
pointer device does not support a y-axis.
AbsoluteMaxZ The Absolute Maximum of the device on the z-axis. If 0, and the AbsoluteMinZ is 0, then the pointer
device does not support a z-axis.
Attributes The following bits are set as needed (or’d together) to indicate the capabilities of the device supported.
The remaining bits are undeﬁned and should be returned as 0.
#define EFI_ABSP_SupportsAltActive 0x00000001
#define EFI_ABSP_SupportsPressureAsZ 0x00000002
EFI_ABSP_SupportsAltActive
If set, indicates this device supports an alternate button input.
EFI_ABSP_SupportsPressureAsZ
If set, indicates this device returns pressure data inparameter CurrentZ.
The driver is not permitted to return all zeros for all three pairs of Min and Max as this would indicate no axis
The EFI_ABSOLUTE_POINTER_PROTOCOL provides a set of services for a pointer device that can be used as
an input device from an application written to this speciﬁcation. The services include the ability to reset the pointer
device, retrieve the state of the pointer device, and retrieve the capabilities of the pointer device. In addition certain
data items describing the device are provided.
12.7. Absolute Pointer Protocol 415Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
12.7.2 EFI_ABSOLUTE_POINTER_PROTOCOL.Reset()
Summary
Prototype
typedef
(EFIAPI *EFI_ABSOLUTE_POINTER_RESET) (
IN EFI_ABSOLUTE_POINTER_PROTOCOL *This,
);

Summary
Prototype
typedef
);
This A pointer to the EFI_ABSOLUTE_POINTER_PROTOCOL instance. Type
EFI_ABSOLUTE_POINTER_PROTOCOL is deﬁned in this section.
operation is to occur as quickly as possible.
Codes Returned
12.7.3 EFI_ABSOLUTE_POINTER_PROTOCOL.GetState()
Summary
Prototype
typedef
(EFIAPI *EFI_ABSOLUTE_POINTER_GET_STATE) (
OUT EFI_ABSOLUTE_POINTER_STATE *State
);
This A pointer to EFI_ABSOLUTE_POINTER_PROTOCOL instance. Type
EFI_ABSOLUTE_POINTER_PROTOCOL is deﬁned in EFI_ABSOLUTE_POINTER_PROTOCOL .
State A pointer to the state information on the pointer device. Type EFI_ABSOLUTE_POINTER_STATE is deﬁned
in “Related Deﬁnitions” below.
12.7. Absolute Pointer Protocol 416Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_ABSOLUTE_POINTER_STATE
UINT64 CurrentX;
UINT64 CurrentY;
UINT64 CurrentZ;
UINT32 ActiveButtons;
} EFI_ABSOLUTE_POINTER_STATE;
CurrentX The unsigned position of the activation on the x axis If the AboluteMinX and the AboluteMaxX ﬁelds
of the EFI_ABSOLUTE_POINTER_MODE structure are both 0, then this pointer device does not support an
x-axis, and this ﬁeld must be ignored.
CurrentY The unsigned position of the activation on the y axis If the AboluteMinY and the AboluteMaxY ﬁelds
of the EFI_ABSOLUTE_POINTER_MODE structure are both 0, then this pointer device does not support a
y-axis, and this ﬁeld must be ignored.
CurrentZ The unsigned position of the activation on the z axis, or the pressure measurement. If the AboluteMinZ
and the AboluteMaxZ ﬁelds of the EFI_ABSOLUTE_POINTER_MODE structure are both 0, then this pointer
device does not support a z-axis, and this ﬁeld must be ignored.
ActiveButtons Bits are set to 1 in this structure item to indicate that device buttons are active.
//*****************************
//definitions of bits within ActiveButtons
#define EFI_ABSP_TouchActive 0x00000001
#define EFI_ABS_AltActive 0x00000002
EFI_ABSP_TouchActive This bit issetifthe touch sensor isactive
EFI_ABS_AltActive This bit issetifthe alt sensor, such aspen-side button, is
˓→active.
The GetState() function retrieves the current state of a pointer device. This includes information on the active state
associated with the pointer device and the current position of the axes associated with the pointer device. If the
state of the pointer device has not changed since the last call to GetState() , then EFI_NOT_READY is returned. If
the state of the pointer device has changed since the last call to GetState() , then the state information is placed in
State, and EFI_SUCCESS is returned. If a device error occurs while attempting to retrieve the state information, then
EFI_DEVICE_ERROR is returned.
EFI_SUCCESS The state of the pointer device was returned in State .
State() .
12.7. Absolute Pointer Protocol 417Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
12.8 Serial I/O Protocol
This section deﬁnes the Serial I/O protocol. This protocol is used to abstract byte stream devices.
12.8.1 EFI_SERIAL_IO_PROTOCOL
Summary
This protocol is used to communicate with any type of character-based I/O device.
GUID
#define EFI_SERIAL_IO_PROTOCOL_GUID \
{0xBB25CF6F,0xF1D4,0x11D2,\
{0x9a,0x0c,0x00,0x90,0x27,0x3f,0xc1,0xfd}}
#define EFI_SERIAL_IO_PROTOCOL_REVISION 0x00010000
#define EFI_SERIAL_IO_PROTOCOL_REVISION1p1 0x00010001
EFI_SERIAL_RESET Reset;
EFI_SERIAL_SET_ATTRIBUTES SetAttributes;
EFI_SERIAL_SET_CONTROL_BITS SetControl;
EFI_SERIAL_GET_CONTROL_BITS GetControl;
EFI_SERIAL_WRITE Write;
EFI_SERIAL_READ Read;
SERIAL_IO_MODE *Mode;
CONST EFI_GUID *DeviceTypeGuid; // Revision 1.1
} EFI_SERIAL_IO_PROTOCOL;
Revision The revision to which the EFI_SERIAL_IO_PROTOCOL adheres. All future revisions must be backwards
compatible. If a future version is not back wards compatible, it is not the same GUID.
Reset Resets the hardware device.
SetAttributes Sets communication parameters for a serial device. These include the baud rate, receive FIFO depth,
transmit/receive time out, parity, data bits, and stop bit attributes.
SetControl Sets the control bits on a serial device. These include Request to Send and Data Terminal Ready.
GetControl Reads the status of the control bits on a serial device. These include Clear to Send, Data Set Ready, Ring
Indicator, and Carrier Detect.
Write Sends a buffer of characters to a serial device.
Read Receives a buffer of characters from a serial device.
Mode Pointer to SERIAL_IO_MODE data. Type SERIAL_IO_MODE is deﬁned in “Related Deﬁnitions” below.
DeviceTypeGuid Pointer to a GUID identifying the device connected to the serial port. This ﬁeld is NULL when
the protocol is installed by the serial port driver and may be populated by a platform driver for a serial port
with a known device attached. The ﬁeld will remain NULL if there is no platform serial device identiﬁcation
information available.
12.8. Serial I/O Protocol 418Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// SERIAL_IO_MODE
UINT32 ControlMask;
// current Attributes
UINT32 Timeout;
UINT64 BaudRate;
UINT32 ReceiveFifoDepth;
UINT32 DataBits;
UINT32 Parity;
UINT32 StopBits;
} SERIAL_IO_MODE;
The data values in the SERIAL_IO_MODE are read-only and are updated by the code that produces the
EFI_SERIAL_IO_PROTOCOL functions:
ControlMask A mask of the Control bits that the device supports. The device must always support the Input Buffer
Empty control bit.
Timeout If applicable, the number of microseconds to wait before timing out a Read or Write operation.
BaudRate If applicable, the current baud rate setting of the device; otherwise, baud rate has the value of zero to
indicate that device runs at the device’s designed speed.
ReceiveFifoDepth The number of characters the device will buffer on input.
DataBits The number of data bits in each character.
Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked as each character is transmitted or
received. If the device does not support parity the value is the default parity value.
StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character. If the device does not support
stop bits the value is the default stop bit value.
// EFI_PARITY_TYPE
DefaultParity,
NoParity,
EvenParity,
OddParity,
MarkParity,
SpaceParity
} EFI_PARITY_TYPE;
// EFI_STOP_BITS_TYPE
DefaultStopBits,
OneStopBit, // 1 stop bit
OneFiveStopBits, // 1.5 stop bits
TwoStopBits // 2 stop bits
} EFI_STOP_BITS_TYPE;
12.8. Serial I/O Protocol 419Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The Serial I/O protocol is used to communicate with UART-style serial devices. These can be standard UART serial
ports in PC-AT systems, serial ports attached to a USB interface, or potentially any character-based I/O device.
The Serial I/O protocol can control byte I/O style devices from a generic device, to a device with features such as a
UART. As such many of the serial I/O features are optional to allow for the case of devices that do not have UART
controls. Each of these options is called out in the speciﬁc serial I/O functions.
The default attributes for all UART-style serial device interfaces are: 115,200 baud, a 1 byte receive FIFO, a

1,000,000 microsecond timeout per character, no parity, 8 data bits, and 1 stop bit. Flow control is the respon-
sibility of the software that uses the protocol. Hardware ﬂow control can be implemented through the use of
theEFI_SERIAL_IO_PROTOCOL.GetControl() andEFI_SERIAL_IO_PROTOCOL.SetControl() functions (described
below) to monitor and assert the ﬂow control signals. The XON/XOFF ﬂow control algorithm can be implemented in
software by inserting XON and XOFF characters into the serial data stream as required.
Special care must be taken if a signiﬁcant amount of data is going to be read from a serial device. Since UEFI drivers
are polled mode drivers, characters received on a serial device might be missed. It is the responsibility of the software
that uses the protocol to check for new data often enough to guarantee that no characters will be missed. The required
polling frequency depends on the baud rate of the connection and the depth of the receive FIFO.
12.8.2 Serial Device Identiﬁcation
Serial device identiﬁcation is accomplished through the interaction of three distinct drivers. The serial port driver binds
to the serial port hardware and produces the EFI_SERIAL_IO_PROTOCOL. At the time the protocol is produced the
DeviceTypeGuid ﬁeld is NULL.
During the UEFI Driver Binding process a platform driver, with a EFI_DRIVER_BINDING_PROTOCOL Version
ﬁeld in the range of 0xfffffff0 to 0xffffffff can check for the presence of the EFI_SERIAL_IO_PROTOCOL and
any other necessary information in Supported() to check if the serial port instance is recognized for the purposes of
provide serial device identiﬁcation information. If the port instance is recognized then EFI_SUCCESS will be returned
from Supported(). Since the driver binding Version ﬁeld is higher than any device driver the platform’s serial device
identiﬁcation driver binding instance will have Start() called. This function will write the DeviceTypeGuid with a
value that identiﬁes the attached serial device.
When the driver binding process continues the serial device driver can use the DeviceTypeGuid ﬁeld to determine the
serial device connected to the port is supported.
Serial device drivers for non-terminal devices that will co-exist with backwards-compatible terminal drivers must
check that the EFI_SERIAL_IO_PROTOCOL Revision ﬁeld is at least 0x00010001 and compare the DeviceTypeGuid
in their driver binding Supported() function. Terminal drivers provide backwards compatibility by assuming a Terminal
device is present when a protocol instance Revision is the original 0x00010000 value. Terminal drivers may also
assume a Terminal device is present if the DeviceTypeGuid is NULL for cases where the platform does not provide
serial identiﬁcation information.
12.8.3 Serial Device Type GUIDs
#define EFI_SERIAL_TERMINAL_DEVICE_TYPE_GUID \
{ 0x6ad9a60f, 0x5815, 0x4c7c, \
{ 0x8a, 0x10, 0x50, 0x53, 0xd2, 0xbf, 0x7a, 0x1b } }
The EFI_SERIAL_TERMINAL_DEVICE_TYPE_GUID describes a serial terminal type device suitable for use as a
UEFI console.
Vendors may deﬁne and use additional GUIDs for other serial device types.
12.8. Serial I/O Protocol 420Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 12.1: Serial Device Identiﬁcation Driver Relationships
12.8.3.1 EFI_SERIAL_IO_PROTOCOL.Reset()
Summary
Resets the serial device.
Prototype
typedef
(EFIAPI *EFI_SERIAL_RESET) (
IN EFI_SERIAL_IO_PROTOCOL *This
);
This
A pointer to the EFI_SERIAL_IO_PROTOCOL instance. Type EFI_SERIAL_IO_PROTOCOL is deﬁned in Serial
I/O Protocol .
The Reset() function resets the hardware of a serial device.
EFI_SUCCESS The serial device was reset.
EFI_DEVICE_ERROR The serial device could not be reset.
12.8.3.2 EFI_SERIAL_IO_PROTOCOL.SetAttributes()
Summary
Sets the baud rate, receive FIFO depth, transmit/receive time out, parity, data bits, and stop bits on a serial device.
(EFIAPI *EFI_SERIAL_SET_ATTRIBUTES) (
IN EFI_SERIAL_IO_PROTOCOL *This,
IN UINT64 BaudRate,
IN UINT32 ReceiveFifoDepth,
IN UINT32 Timeout
IN EFI_PARITY_TYPE Parity,
IN UINT8 DataBits,
IN EFI_STOP_BITS_TYPE StopBits
);
This A pointer to the EFI_SERIAL_IO_PROTOCOL instance. Type EFI_SERIAL_IO_PROTOCOL is deﬁned in
Serial I/O Protocol .
BaudRate The requested baud rate. A BaudRate value of 0 will use the device’s default interface speed.
ReceiveFifoDepth The requested depth of the FIFO on the receive side of the serial interface. A ReceiveFifoDepth
value of 0 will use the device’s default FIFO depth.
Timeout The requested time out for a single character in microseconds. This timeout applies to both the transmit and
receive side of the interface. A Timeout value of 0 will use the device’s default time out value.12.8. Serial I/O Protocol 421Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Parity The type of parity to use on this serial device. A Parity value of DefaultParity will use the device’s default
parity value. Type EFI_PARITY_TYPE is deﬁned in “Related Deﬁnitions” in Serial I/O Protocol
DataBits The number of data bits to use on this serial device. A DataBits value of 0 will use the device’s default data
bit setting.
StopBits The number of stop bits to use on this serial device. A StopBits value of DefaultStopBits will use the
device’s default number of stop bits. Type EFI_STOP_BITS_TYPE is deﬁned in “Related Deﬁnitions” in Serial
The SetAttributes() function sets the baud rate, receive-FIFO depth, transmit/receive time out, parity, data bits, and
stop bits on a serial device.
The controller for a serial device is programmed with the speciﬁed attributes. If the Parity, DataBits, or StopBits values
are not valid, then an error will be returned. If the speciﬁed BaudRate is below the minimum baud rate supported by
the serial device, an error will be returned. The nearest baud rate supported by the serial device will be selected without
exceeding the BaudRate parameter. If the speciﬁed ReceiveFifoDepth is below the smallest FIFO size supported by
the serial device, an error will be returned. The nearest FIFO size supported by the serial device will be selected
without exceeding the ReceiveFifoDepth parameter.
EFI_SUCCESS The new attributes were set on the serial device.
EFI_INV ALID_PARAMETER One or more of the attributes has an unsupported value.
EFI_DEVICE_ERROR The serial device is not functioning correctly.
12.8.3.3 EFI_SERIAL_IO_PROTOCOL.SetControl()
Summary
Sets the control bits on a serial device.
Prototype
typedef
(EFIAPI *EFI_SERIAL_SET_CONTROL_BITS) (
IN UINT32 Control
);
Control Sets the bits of Control that are settable. See “Related Deﬁnitions” below.
// CONTROL BITS
#define EFI_SERIAL_CLEAR_TO_SEND 0x0010
#define EFI_SERIAL_DATA_SET_READY 0x0020
#define EFI_SERIAL_RING_INDICATE 0x0040
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#define EFI_SERIAL_CARRIER_DETECT 0x0080
#define EFI_SERIAL_REQUEST_TO_SEND 0x0002
#define EFI_SERIAL_DATA_TERMINAL_READY 0x0001
#define EFI_SERIAL_INPUT_BUFFER_EMPTY 0x0100
#define EFI_SERIAL_OUTPUT_BUFFER_EMPTY 0x0200
#define EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE 0x1000
#define EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE 0x2000
#define EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE 0x4000
The SetControl() function is used to assert or deassert the control signals on a serial device. The following signals are
set according their bit settings:
• Request to Send
• Data Terminal Ready
Only the REQUEST_TO_SEND, DATA_TERMINAL_READY , HARDWARE_LOOPBACK_ENABLE, SOFT-
WARE_LOOPBACK_ENABLE, and HARDWARE_FLOW_CONTROL_ENABLE bits can be set with SetControl().
All the bits can be read with EFI_SERIAL_IO_PROTOCOL.GetControl() .
EFI_SUCCESS The new control bits were set on the serial device.
EFI_UNSUPPORTED The serial device does not support this operation.
12.8.3.4 EFI_SERIAL_IO_PROTOCOL.GetControl()
Summary
Retrieves the status of the control bits on a serial device.
Prototype
typedef
(EFIAPI *EFI_SERIAL_GET_CONTROL_BITS) (
OUT UINT32 *Control
);
Control A pointer to return the current control signals from the serial device. See “Related Deﬁnitions” below.

Summary
Prototype
typedef
);
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The GetControl() function retrieves the status of the control bits on a serial device.
EFI_SUCCESS The control bits were read from the serial device.
12.8.3.5 EFI_SERIAL_IO_PROTOCOL.Write()
Summary
Writes data to a serial device.
Prototype
typedef
(EFIAPI *EFI_SERIAL_WRITE) (
);
SeeSerial I/O Protocol .
BufferSize On input, the size of the Buffer. On output, the amount of data actually written.
Buffer The buffer of data to write.
The Write() function writes the speciﬁed number of bytes to a serial device. If a time out error occurs while data is
being sent to the serial port, transmission of this buffer will terminate, and EFI_TIMEOUT will be returned. In all
cases the number of bytes actually written to the serial device is returned in BufferSize.
EFI_SUCCESS The data was written.
EFI_TIMEOUT The data write was stopped due to a timeout.
12.8. Serial I/O Protocol 424Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
12.8.3.6 EFI_SERIAL_IO_PROTOCOL.Read()
Summary
Reads data from a serial device.
Prototype
typedef
(EFIAPI *EFI_SERIAL_READ) (
OUT VOID *Buffer
);
BufferSize On input, the size of the Buffer. On output, the amount of data returned in Buffer.
Buffer The buffer to return the data into.
The Read() function reads a speciﬁed number of bytes from a serial device. If a time out error or an overrun error
is detected while data is being read from the serial device, then no more characters will be read, and an error will be
returned. In all cases the number of bytes actually read is returned in BufferSize.
EFI_SUCCESS The data was read.
EFI_DEVICE_ERROR The serial device reported an error.
EFI_TIMEOUT The operation was stopped due to a timeout or overrun.
12.9 Graphics Output Protocol
The goal of this section is to replace the functionality that currently exists with VGA hardware and its corresponding
video BIOS. The Graphics Output Protocol is a software abstraction and its goal is to support any foreseeable graphics
hardware and not require VGA hardware, while at the same time also lending itself to implementation on the current
generation of VGA hardware.
Graphics output is important in the pre-boot space to support modern ﬁrmware features. These features include the
display of logos, the localization of output to any language, and setup and conﬁguration screens.
Graphics output may also be required as part of the startup of an operating system. There are potentially times in
modern operating systems prior to the loading of a high performance OS graphics driver where access to graphics
output device is required. The Graphics Output Protocol supports this capability by providing the EFI OS loader
access to a hardware frame buffer and enough information to allow the OS to draw directly to the graphics output
device.
TheEFI_GRAPHICS_OUTPUT_PROTOCOL : supports three member functions to support the limited graphics needs
of the pre-boot environment. These member functions allow the caller to draw to a virtualized frame buffer, retrieve
the supported video modes, and to set a video mode. These simple primitives are sufﬁcient to support the general
needs of pre-OS ﬁrmware code.
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TheEFI_GRAPHICS_OUTPUT_PROTOCOL also exports enough information about the current mode for operating
system startup software to access the linear frame buffer directly.
The interface structure for the Graphics Output protocol is deﬁned in this section. A unique Graphics Output protocol
must represent each video frame buffer in the system that is driven out to one or more video output devices.
12.9.1 Blt Buffer
The basic graphics operation in the EFI_GRAPHICS_OUTPUT_PROTOCOL is the Block Transfer or Blt. The Blt
operation allows data to be read or written to the video adapter’s video memory. The Blt operation abstracts the video
adapters hardware implementation by introducing the concept of a software Blt buffer.
The frame buffer abstracts the video display as an array of pixels. Each pixels location on the video display is deﬁned
by its X and Y coordinates. The X coordinate represents a scan line. A scan line is a horizontal line of pixels on the
display. The Y coordinate represents a vertical line on the display. The upper left hand corner of the video display is
deﬁned as (0, 0) where the notation (X, Y) represents the X and Y coordinate of the pixel. The lower right corner of
the video display is represented by (Width -1, Height -1).
The software Blt buffer is structured as an array of pixels. Pixel (0, 0) is the ﬁrst element of the software Blt buffer.
The Blt buffer can be thought of as a set of scan lines. It is possible to convert a pixel location on the video display to
the Blt buffer using the following algorithm: Blt buffer array index = Y * Width + X.
Each software Blt buffer entry represents a pixel that is comprised of a 32-bit quantity. The color
components of Blt buffer pixels are in PixelBlueGreenRedReserved8BitPerColor format as deﬁned by
EFI_GRAPHICS_OUTPUT_BLT_PIXEL. The byte values for the red, green, and blue components represent the
color intensity. This color intensity value range from a minimum intensity of 0 to maximum intensity of 255.
Fig. 12.2: Software BLT Buffer
12.9. Graphics Output Protocol 426Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
12.9.2 EFI_GRAPHICS_OUTPUT_PROTOCOL
Summary
Provides a basic abstraction to set video modes and copy pixels to and from the graphics controller’s frame buffer. The
linear address of the hardware frame buffer is also exposed so software can write directly to the video hardware.
GUID
#define EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID \
{0x9042a9de,0x23dc,0x4a38,\
{0x96,0xfb,0x7a,0xde,0xd0,0x80,0x51,0x6a}}
typedef struct EFI_GRAPHICS_OUTPUT_PROTCOL {
EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE QueryMode;
EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE SetMode;
EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT Blt;
EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode;
} EFI_GRAPHICS_OUTPUT_PROTOCOL;
QueryMode Returns information for an available graphics mode that the graphics device and the set of active video
output devices supports.
SetMode Set the video device into the speciﬁed mode and clears the visible portions of the output display to black.
BltSoftware abstraction to draw on the video device’s frame buffer.
Mode Pointer to EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE data. Type
EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE is deﬁned in “Related Deﬁnitions” below.
UINT32 RedMask;
UINT32 GreenMask;
UINT32 BlueMask;
UINT32 ReservedMask;
} EFI_PIXEL_BITMASK;
If a bit issetinRedMask, GreenMask, orBlueMask then those bits of the pixel
˓→represent the corresponding color. Bits inRedMask, GreenMask, BlueMask, and
˓→ReserverdMask must notover lap bit positions. The values forthe red, green, and
˓→blue components inthe bit mask represent the color intensity. The color
˓→intensities must increase asthe color values fora each color mask increase witha
˓→minimum intensity of all bits ina color mask clear to a maximum intensity of all
˓→bitsina color mask set.
PixelRedGreenBlueReserved8BitPerColor,
PixelBlueGreenRedReserved8BitPerColor,
PixelBitMask,
PixelBltOnly,
PixelFormatMax
} EFI_GRAPHICS_PIXEL_FORMAT;
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PixelRedGreenBlueReserved8BitPerColor A pixel is 32-bits and byte zero represents red, byte one represents
green, byte two represents blue, and byte three is reserved. This is the deﬁnition for the physical frame buffer.
The byte values for the red, green, and blue components represent the color intensity. This color intensity value

range from a minimum intensity of 0 to maximum intensity of 255.
PixelBlueGreenRedReserved8BitPerColor A pixel is 32-bits and byte zero represents blue, byte one represents
green, byte two represents red, and byte three is reserved. This is the deﬁnition for the physical frame buffer.
PixelBitMask The pixel deﬁnition of the physical frame buffer is deﬁned by EFI_PIXEL_BITMASK.
PixelBltOnly This mode does not support a physical frame buffer.
Valid EFI_GRAPHICS_PIXEL_FORMAT enum values are less than this value.
UINT32 HorizontalResolution;
UINT32 VerticalResolution;
EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
EFI_PIXEL_BITMASK PixelInformation;
UINT32 PixelsPerScanLine;
} EFI_GRAPHICS_OUTPUT_MODE_INFORMATION;
Version The version of this data structure. A value of zero represents the
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure as deﬁned in this speciﬁcation. Future
version of this speciﬁcation may extend this data structure in a backwards compatible way and increase the
value of Version.
HorizontalResolution The size of video screen in pixels in the X dimension.
VerticalResolution The size of video screen in pixels in the Y dimension.
PixelFormat Enumeration that deﬁnes the physical format of the pixel. A value of PixelBltOnly implies that a linear
frame buffer is not available for this mode.
PixelInformation This bit-mask is only valid if PixelFormat is set to PixelPixelBitMask. A bit being set deﬁnes what
bits are used for what purpose such as Red, Green, Blue, or Reserved.
PixelsPerScanLine Deﬁnes the number of pixel elements per video memory line. For performance reasons, or due
to hardware restrictions, scan lines may be padded to an amount of memory alignment. These padding pixel
elements are outside the area covered by HorizontalResolution and are not visible. For direct frame buffer
access, this number is used as a span between starts of pixel lines in video memory. Based on the size of an
individual pixel element and PixelsPerScanline , the offset in video memory from pixel element (x, y) to pixel
element (x, y+1) has to be calculated as “sizeof( PixelElement ) * PixelsPerScanLine”, not “sizeof( PixelElement
) * HorizontalResolution”, though in many cases those values can coincide. This value can depend on video
hardware and mode resolution. GOP implementation is responsible for providing accurate value for this ﬁeld.
Note :The following code sample is an example of the intended ﬁeld usage :
INTN
GetPixelElementSize (
IN EFI_PIXEL_BITMASK *PixelBits
)
{
INTN HighestPixel = -1;
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INTN BluePixel;
INTN RedPixel;
INTN GreenPixel;
INTN RsvdPixel;
BluePixel = FindHighestSetBit (PixelBits->BlueMask);
RedPixel = FindHighestSetBit (PixelBits->RedMask);
GreenPixel = FindHighestSetBit (PixelBits->GreenMask);
RsvdPixel = FindHighestSetBit (PixelBits->ReservedMask);
HighestPixel = max (BluePixel, RedPixel);
HighestPixel = max (HighestPixel, GreenPixel);
HighestPixel = max (HighestPixel, RsvdPixel);
returnHighestPixel;
}
EFI_PHYSICAL_ADDRESS NewPixelAddress;
EFI_PHYSICAL_ADDRESS CurrentPixelAddress *;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION OutputInfo;
INTN PixelElementSize;
switch (OutputInfo.PixelFormat) {
case PixelBitMask:
PixelElementSize =
GetPixelElementSize (&OutputInfo.PixelInformation);
break;
case PixelBlueGreenRedReserved8BitPerColor:
case PixelRedGreenBlueReserved8BitPerColor:
sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL);
break;
}
//
// NewPixelAddress after execution points to the pixel
// positioned one line below the one pointed by
// CurrentPixelAddress
//
NewPixelAddress = CurrentPixelAddress +
(PixelElementSize *
OutputInfo.PixelsPerScanLine);
End of note code sample.
UINT32 MaxMode;
UINT32 Mode;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;
UINTN SizeOfInfo;
EFI_PHYSICAL_ADDRESS FrameBufferBase;
UINTN FrameBufferSize;
} EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE;
The EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE is read-only and values are only changed by using the appro-
priate interface functions:
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MaxMode The number of modes supported by QueryMode() and EFI_GRAPHICS_OUTPUT_PROTOCOL.SetMode()_.
Mode Current Mode of the graphics device. Valid mode numbers are 0 to MaxMode -1.
Info Pointer to read-only EFI_GRAPHICS_OUTPUT_MODE_INFORMATION data.
SizeOfInfo Size of Info structure in bytes. Future versions of this speciﬁcation may increase the size of the
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION data.
FrameBufferBase Base address of graphics linear frame buffer. Info contains information required to allow software
to draw directly to the frame buffer without using Blt().Offset zero in FrameBufferBase represents the upper left
pixel of the display.
FrameBufferSize Amount of frame buffer needed to support the active mode as deﬁned by PixelsPerScanLine x
VerticalResolution xPixelElementSize .
The EFI_GRAPHICS_OUTPUT_PROTOCOL provides a software abstraction to allow pixels to be drawn directly to
the frame buffer. The EFI_GRAPHICS_OUTPUT_PROTOCOL is designed to be lightweight and to support the basic
needs of graphics output prior to Operating System boot.
12.9.2.1 EFI_GRAPHICS_OUTPUT_PROTOCOL.QueryMode()
Summary
Returns information for an available graphics mode that the graphics device and the set of active video output devices
supports.
Prototype
typedef
(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE) (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber,
OUT UINTN *SizeOfInfo
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info
);
This TheEFI_GRAPHICS_OUTPUT_PROTOCOL instance. Type EFI_GRAPHICS_OUTPUT_PROTOCOL is de-
ﬁned in this section.
ModeNumber The mode number to return information on. The current mode and valid modes are read-only values
in the Mode structure of the EFI_GRAPHICS_OUTPUT_PROTOCOL .
SizeOfInfo A pointer to the size, in bytes, of the Info buffer.
Info A pointer to a callee allocated buffer that returns information about ModeNumber.
The QueryMode() function returns information for an available graphics mode that the graphics device and
the set of active video output devices supports. If ModeNumber is not between 0 and MaxMode - 1,
then EFI_INV ALID_PARAMETER is returned. MaxMode is available from the Mode structure of the
EFI_GRAPHICS_OUTPUT_PROTOCOL.
The size of the Info structure should never be assumed and the value of SizeOfInfo is the only valid way to know the
size of Info.
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If the EFI_GRAPHICS_OUTPUT_PROTOCOL is installed on the handle that represents a single video output device,
then the set of modes returned by this service is the subset of modes supported by both the graphics controller and the
video output device.
If the EFI_GRAPHICS_OUTPUT_PROTOCOL is installed on the handle that represents a combination of video
output devices, then the set of modes returned by this service is the subset of modes supported by the graphics controller
and the all of the video output devices represented by the handle.
EFI_SUCCESS Valid mode information was returned.
EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the video mode.
EFI_INV ALID_PARAMETER ModeNumber is not valid.
12.9.2.2 EFI_GRAPHICS_OUTPUT_PROTOCOL.SetMode()
Summary
Set the video device into the speciﬁed mode and clears the visible portions of the output display to black.
Prototype
typedef
(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE) (
IN UINT32 ModeNumber
);
ModeNumber Abstraction that deﬁnes the current video mode. The current mode and valid modes are read-only
values in the Mode structure of the EFI_GRAPHICS_OUTPUT_PROTOCOL .
This SetMode() function sets the graphics device and the set of active video output devices to the video mode speciﬁed
by ModeNumber. If ModeNumber is not supported EFI_UNSUPPORTED is returned.
If a device error occurs while attempting to set the video mode, then EFI_DEVICE_ERROR is returned. Otherwise,
the graphics device is set to the requested geometry, the set of active output devices are set to the requested geometry,
the visible portion of the hardware frame buffer is cleared to black, and EFI_SUCCESS is returned.
EFI_SUCCESS The graphics mode speciﬁed by ModeNumber was selected.

EFI_UNSUPPORTED ModeNumber is not supported by this device.
12.9. Graphics Output Protocol 431Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
12.9.2.3 EFI_GRAPHICS_OUTPUT_PROTOCOL.Blt()
Summary
Blt a rectangle of pixels on the graphics screen. Blt stands for BLock Transfer.
Prototype
UINT8 Blue;
UINT8 Green;
UINT8 Red;
UINT8 Reserved;
} EFI_GRAPHICS_OUTPUT_BLT_PIXEL;
EfiBltVideoFill,
EfiBltVideoToBltBuffer,
EfiBltBufferToVideo,
EfiBltVideoToVideo,
EfiGraphicsOutputBltOperationMax
} EFI_GRAPHICS_OUTPUT_BLT_OPERATION;
typedef
(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT) (
IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta OPTIONAL
);
This TheEFI_GRAPHICS_OUTPUT_PROTOCOL instance.
BltBuffer The data to transfer to the graphics screen. Size is at least
Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL).
BltOperation The operation to perform when copying BltBuffer on to the graphics screen.
SourceX The X coordinate of the source for the BltOperation. The origin of the screen is 0, 0 and that is the upper
left-hand corner of the screen. SourceY The Y coordinate of the source for the BltOperation. The origin of the
screen is 0, 0 and that is the upper left-hand corner of the screen.
DestinationX The X coordinate of the destination for the BltOperation. The origin of the screen is 0, 0 and that is the
upper left-hand corner of the screen.
DestinationY The Y coordinate of the destination for the BltOperation. The origin of the screen is 0, 0 and that is the
Width The width of a rectangle in the blt rectangle in pixels. Each pixel is represented by an
EFI_GRAPHICS_OUTPUT_BLT_PIXEL element.
Height The height of a rectangle in the blt rectangle in pixels. Each pixel is represented by an
12.9. Graphics Output Protocol 432Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Delta Not used for EﬁBltVideoFill or the EﬁBltVideoToVideo operation. If a Delta of zero is used, the entire BltBuffer
is being operated on. If a subrectangle of the BltBuffer is being used then Delta represents the number of bytes
in a row of the BltBuffer.
The Blt() function is used to draw the BltBuffer rectangle onto the video screen.
The BltBuffer represents a rectangle of Height by Width pixels that will be drawn on the graphics screen using the
operation speciﬁed by BltOperation. The Delta value can be used to enable the BltOperation to be performed on a
sub-rectangle of the BltBuffer.
Blt Operation Table describes the BltOperations that are supported on rectangles. Rectangles have coordinates (left,
upper) (right, bottom):
Table 12.32: Blt Operation Table
Blt Operation Operation
Eﬁbltvideoﬁll Write data from the BltBuffer pixel (0,0) directly to every pixel of the video display rectangle
(DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). Only one pixel
will be used from the BltBuffer. Delta is NOT used.
Eﬁbltvideotobltbuffer Read data from the video display rectangle (SourceX, SourceY) (SourceX + Width, SourceY +
Height) and place it in the BltBuffer rectangle (DestinationX, DestinationY ) (DestinationX +
Width, DestinationY + Height). If DestinationX or DestinationY is not zero then Delta must be
set to the length in bytes of a row in the BltBuffer.
Eﬁbltbuffertovideo Write data from the BltBuffer rectangle (SourceX, SourceY) (SourceX + Width, SourceY +
Height) directly to the video display rectangle (DestinationX, DestinationY) (DestinationX +
Width, DestinationY + Height). If SourceX or SourceY is not zero then Delta must be set to
the length in bytes of a row in the BltBuffer.
Eﬁbltvideotovideo Copy from the video display rectangle (SourceX, SourceY) (SourceX + Width, SourceY +
Height) to the video display rectangle(DestinationX, DestinationY) (DestinationX + Width,
DestinationY + Height. The BltBuffer and Delta are not used in this mode. There is no limita-
tion on the overlapping of the source and destination rectangles.
EFI_SUCCESS BltBuffer was drawn to the graphics screen.
EFI_INV ALID_PARAMETER BltOperation is not valid.
12.9.2.4 EFI_EDID_DISCOVERED_PROTOCOL
Summary
This protocol contains the EDID information retrieved from a video output device.
GUID
#define EFI_EDID_DISCOVERED_PROTOCOL_GUID \
{0x1c0c34f6,0xd380,0x41fa,\
{0xa0,0x49,0x8a,0xd0,0x6c,0x1a,0x66,0xaa}}
UINT32 SizeOfEdid;
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UINT8 *Edid;
} EFI_EDID_DISCOVERED_PROTOCOL;
Parameter
SizeOfEdid The size, in bytes, of the Edid buffer. 0 if no EDID information is available from the video output device.
Otherwise, it must be a minimum of 128 bytes.
Edid A pointer to a read-only array of bytes that contains the EDID information for a video output device. This
pointer is NULL if no EDID information is available from the video output device. The minimum size of a
valid Edid buffer is 128 bytes. EDID information is deﬁned in the E-EDID EEPROM speciﬁcation published
by VESA ( www.vesa.org <www.vesa.org>__ )
EFI_EDID_DISCOVERED_PROTOCOL represents the EDID information that is returned from a video output de-
vice. If the video output device does not contain any EDID information, then the SizeOfEdid ﬁeld must set to zero
and the Edid ﬁeld must be set to NULL. The EFI_EDID_DISCOVERED_PROTOCOL must be placed on every child
handle that represents a possible video output device. The EFI_EDID_DISCOVERED_PROTOCOL is never placed
on child handles that represent combinations of two or more video output devices.
12.9.2.5 EFI_EDID_ACTIVE_PROTOCOL
Summary
This protocol contains the EDID information for an active video output device. This is either the EDID information
retrieved from the EFI_EDID_OVERRIDE_PROTOCOL if an override is available, or an identical copy of the EDID
information from the EFI_EDID_DISCOVERED_PROTOCOL if no overrides are available.
GUID
#define EFI_EDID_ACTIVE_PROTOCOL_GUID \
{0xbd8c1056,0x9f36,0x44ec,\
{0x92,0xa8,0xa6,0x33,0x7f,0x81,0x79,0x86}}
} EFI_EDID_ACTIVE_PROTOCOL;
Parameter
Edid A pointer to a read-only array of bytes that contains the EDID information for an active video output device.
This pointer is NULL if no EDID information is available for the video output device. The minimum size of a
by VESA ( www.vesa.org ).
When the set of active video output devices attached to a frame buffer are selected, the
EFI_EDID_ACTIVE_PROTOCOL must be installed onto the handles that represent the each of those active
video output devices. If the EFI_EDID_OVERRIDE_PROTOCOL has override EDID information for an active video
output device, then the EDID information speciﬁed by GetEdid() is used for the EFI_EDID_ACTIVE_PROTOCOL.
12.9. Graphics Output Protocol 434Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Otherwise, the EDID information from the EFI_EDID_DISCOVERED_PROTOCOL is used for the
EFI_EDID_ACTIVE_PROTOCOL. Since all EDID information is read-only, it is legal for the pointer as-
sociated with the EFI_EDID_ACTIVE_PROTOCOL to be the same as the pointer associated with the
EFI_EDID_DISCOVERED_PROTOCOL when no overrides are present.
12.9.2.6 EFI_EDID_OVERRIDE_PROTOCOL
Summary
This protocol is produced by the platform to allow the platform to provide EDID information to the producer of the
Graphics Output protocol.
GUID
#define EFI_EDID_OVERRIDE_PROTOCOL_GUID \
{0x48ecb431,0xfb72,0x45c0,\
{0xa9,0x22,0xf4,0x58,0xfe,0x04,0x0b,0xd5}}
typedef struct _EFI_EDID_OVERRIDE_PROTOCOL {
EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID GetEdid;
} EFI_EDID_OVERRIDE_PROTOCOL;
Parameter
GetEdid Returns EDID values and attributes that the Video BIOS must use
12.9.2.7 EFI_EDID_OVERRIDE_PROTOCOL.GetEdid()
Summary
Returns policy information and potentially a replacement EDID for the speciﬁed video output device.
Prototype
typedef
(EFIAPI \ *EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID) (
IN EFI_EDID_OVERRIDE_PROTOCOL *This,

Summary
GUID
Parameter
Summary
Prototype
typedef
IN EFI_HANDLE *ChildHandle,
OUT UINT32 *Attributes,
OUT UINTN *EdidSize,
OUT UINT8 **Edid
);
This TheEFI_EDID_OVERRIDE_PROTOCOL.GetEdid() instance. Type EFI_EDID_OVERRIDE_PROTOCOL is
deﬁned in Rules for PCI/AGP Devices .
ChildHandle A pointer to a child handle that represents a possible video output device.
Attributes A pointer to the attributes associated with ChildHandle video output device.
12.9. Graphics Output Protocol 435Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EdidSize A pointer to the size, in bytes, of the Edid buffer.
Edid A pointer to the callee allocated buffer that contains the EDID information associated with ChildHandle. If
EdidSize is 0, then a pointer to NULL is returned.
Note : the (EFI_HANDLE ) type of the “ChildHandle” parameter is an historical typing error in the UEFI speciﬁ-
cation. To match existent practice however, implementors and callers of the protocol are now expected to conform
to the declaration of the parameter as written. That is, callers must pass the address of an EFI_HANDLE object as
“ChildHandle”, and implementors must dereference “ChildHandle” for ﬁnding the EFI_HANDLE object .
#define EFI_EDID_OVERRIDE_DONT_OVERRIDE 0x01
#define EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG 0x02
Table 12.34: Attributes Deﬁnition Table
Attribute Bit EdidSize Operation
EFI_EDID_OVERRIDE_DONT_OVERRIDE=0 0 No override support device.
EFI_EDID_OVERRIDE_DONT_OVERRIDE=0 != 0 Always use returned display device.
EFI_EDID_OVERRIDE_DONT_OVERRIDE!=0 0 No override support for the display device.
EFI_EDID_OVERRIDE_DONT_OVERRIDE!=0 != 0 Only use returned override EDID if the dis-
play device has no EDID or the EDID is in-
correct. Otherwise, use the EDID from the
display device.
EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG=0 0 No hot plug support for the display device.
AGraphics Output protocol will not be in-
stalled if no display device is not present.
EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG=0 != 0 No hot plug support for the display de-
vice. The returned override EDID should be
used according to the EFI_EDID_O VER-
RIDE_DONT_OVERRIDE attribute bit if
the display device is present.
EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG!=0 0 Invalid. The client of this protocol will not
enable hot plug for the display device, and
a Graphics Output protocol will not be in-
stalled if no other display is present.
EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG!=0 != 0 Enable hot plug for the display device. A
Graphics Output protocol will be installed
even if the display device is not present.
This protocol is optionally provided by the platform to override or provide EDID information and/or output device
display properties to the producer of the Graphics Output protocol. If ChildHandle does not represent a video output
device, or there are no override for the video output device speciﬁed by ChildHandle, then EFI_UNSUPPORTED is
returned. Otherwise, the Attributes, EdidSize, and Edid parameters are returned along with a status of EFI_SUCCESS.
The Attributes Deﬁnition Table deﬁnes the behavior for the combinations of the Attribute and EdidSize parameters
when EFI_SUCCESS is returned.
EFI_SUCCESS Valid over rides returned for ChildHandle.
EFI_UNSUPPORTED ChildHandle has no over rides.
12.9. Graphics Output Protocol 436Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
12.10 Rules for PCI/AGP Devices
A UEFI driver that produces the Graphics Output Protocol must follow the UEFI driver model,
produce an EFI Driver Binding Protocol , and follow the rules on implementing the Supported()
EFI_DRIVER_BINDING_PROTOCOL.Supported() ,eﬁ-driver-binding-protocol-Start-protocols-ueﬁ-driver-model ,
and :ref:eﬁ-driver-binding-protocol-Stop-protocols-ueﬁ-driver-model `. The Start() function must not update the video
output device in any way that is visible to the user. The Start() function must create child handle for each physical
video output device and each supported combination of video output devices. The driver must retrieve the EDID
information from each physical video output device and produce a EFI_EDID_DISCOVERED_PROTOCOL on the
child handle that corresponds each physical video output device. The following summary describes the common ini-
tialization steps for a driver that produces the EFI_GRAPHICS_OUTPUT_PROTOCOL. This summary assumes the
graphics controller supports a single frame buffer. If a graphics device supports multiple frame buffers, then handles
for the frame buffers must be created ﬁrst, and then the handles for the video output devices can be created as children
of the frame buffer handles.
Summary of Initialization Steps:
• “If RemainingDevicePath isNULL or the ﬁrst Device Path Node is the End of Device Path Node, then Sup-
ported() returns EFI_SUCCESS . Otherwise, if the ﬁrst node of RemainingDevicePath is not an ACPI _ADR
node or the ﬁrst two nodes of RemainingDevicePath are not a Controller node followed by an ACPI _ADR node,
then Supported() returns EFI_UNSUPPORTED .
• “If Supported() returned EFI_SUCCESS , system calls Start() .
• “If RemainingDevicePath isNULL , then a default set of active video output devices are selected by the driver.
• “If the ﬁrst Device Path Node of RemainingDevicePath is the End of Device Path Node, then skip to the “The
EFI Driver must provide EFI_COMPONENT_NAME2_PROTOCOL ” step.
• Start() function creates a ChildHandle for each physical video output device and installs the
EFI_DEVICE_PATH_PROTOCOL onto the created ChildHandle. The EFI_DEVICE_PATH_PROTOCOL is
constructed by appending an ACPI _ADR device path node describing the physical video output device to the
end of the device path installed on the ControllerHandle passed into Start().
• Start()function retrieves EDID information for each physical video output device and installs the
EFI_EDID_DISCOVERED_PROTOCOL onto the ChildHandle for each physical video output device. If no
EDID data is available from the video output device, then SizeOfEdid is set to zero, and Edid is set to NULL.
• Start()function create a ChildHandle for each valid combination of two or more video output devices, and installs
the EFI_DEVICE_PATH_PROTOCOL onto the created ChildHandle. The EFI_DEVICE_PATH_PROTOCOL
is constructed by appending an ACPI _ADR device path node describing the combination of video output
devices to the end of the device path installed on the ControllerHandle passed into Start(). The ACPI _ADR
entry can represent complex topologies of devices and it is possible to have more than one ACPI _ADR entry in
a single device path node. Support of complex video output device topologies is an optional feature.
• Start()function evaluates the RemainingDevicePath to select the set of active video output devices. If Remain-
ingDevicePath is NULL, then Start() selects a default set of video output devices. If RemainingDevicePath is not
NULL, and ACPI _ADR device path node of RemainingDevicePath does not match any of the created ChildHan-
dles, then Start()must destroy all its ChildHandles and return EFI_UNSUPPORTED. Otherwise, Start() selects
the set of active video output devices speciﬁed by the ACPI _ADR device path node in RemainingDevicePath.
• Start() retrieves the ChildHandle associated with each active video output device. Only
ChildHandles that represent a physical video output device are considered. Start() calls the
EFI_EDID_OVERRIDE_PROTOCOL.GetEdid() service passing in ChildHandle. Depending on the re-
turn values from GetEdid(), either the override EDID information or the EDID information from the
EFI_EDID_DISCOVERED_PROTOCOL on ChildHandle is selected. See GetEdid() for a detailed description
of this decision. The selected EDID information is used to produce the EFI_EDID_ACTIVE_PROTOCOL, and
that protocol is installed onto ChildHandle.
12.10. Rules for PCI/AGP Devices 437Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Start() retrieves the one ChildHandle that represents the entire set of active video output devices. If this set is a
single video output device, then this ChildHandle will be the same as the one used in the previous step. If this
set is a combination of video output devices, then this will not be one of the ChildHandles used in the previous
two steps. The EFI_GRAPHICS_OUTPUT_PROTOCOL is installed onto this ChildHandle.
• The QueryMode() service of the EFI_GRAPHICS_OUTPUT_PROTOCOL returns the set of modes that both
the graphics controller and the set of active video output devices all support. If a different set of active video
output device is selected, then a different set of modes will likely be produced by QueryMode().
• Start()function optionally initializes video frame buffer hardware. The EFI driver has the option of delaying this
operation until SetMode() is called.
• The EFI Driver must provide EFI_COMPONENT_NAME2_PROTOCOL GetControllerName() support for
ControllerHandle and all the ChildHandles created by this driver. The name returned for ControllerHandle

must return the name of the graphics device. The name returned for each of the ChildHandles allow the user to
pick output display settings and should be constructed with this in mind.
• The EFI Driver’s Stop() function must cleanly undo what the Start() function created.
• An EFI_GRAPHICS_OUTPUT_PROTOCOL must be implemented for every video frame buffer that exists on
a video adapter. In most cases there will be a single EFI_GRAPHICS_OUTPUT_PROTOCOL placed on one
of the a children of the ControllerHandle passed into the EFI_DRIVER_BINDING.Start() function.
If a single PCI device/function contains multiple frame buffers the EFI_GRAPHICS_OUTPUT_PROTOCOL must
create child handles of the PCI handle that inherit its PCI device path and appends a controller device path node. The
handles for the video output devices are children of the handles that represent the frame buffers.
A video device can support an arbitrary number of geometries, but it must support one or more of the following modes
to conform to this speciﬁcation:
Onboard graphics device
• A mode required in a platform design guide
• Native mode of the display
Plug in graphics device
• 800 x 600 with 32-bit color depth or 640 x 480 with 32-bit color depth and a pixel format described by Pix-
elRedGreenBlueReserved8BitPerColor or PixelBlueGreenRedReserved8BitPerColor.
If graphics output device supports both landscape and portrait mode displays it must return a different mode via
QueryMode(). For example landscape mode could be 800 horizontal and 600 vertical while the equivalent portrait
mode would be 600 horizontal and 800 vertical.
12.10. Rules for PCI/AGP Devices 438CHAPTER
THIRTEEN
PROTOCOLS – MEDIA ACCESS
13.1 Load File Protocol
The Load File protocol is used to obtain ﬁles, that are primarily boot options, from arbitrary devices.
13.1.1 EFI_LOAD_FILE_PROTOCOL
Summary
Used to obtain ﬁles, that are primarily boot options, from arbitrary devices.
GUID
#define EFI_LOAD_FILE_PROTOCOL_GUID \
{0x56EC3091,0x954C,0x11d2,\
{0x8e,0x3f,0x00,0xa0, 0xc9,0x69,0x72,0x3b}}
typedef struct _EFI_LOAD_FILE_PROTOCOL {
EFI_LOAD_FILE LoadFile;
} EFI_LOAD_FILE_PROTOCOL;
LoadFile Causes the driver to load the requested ﬁle. See the EFI_LOAD_FILE_PROTOCOL.LoadFile() function
The EFI_LOAD_FILE_PROTOCOL is a simple protocol used to obtain ﬁles from arbitrary devices.
When the ﬁrmware is attempting to load a ﬁle, it ﬁrst attempts to use the device’s Simple File System protocol to read
the ﬁle. If the ﬁle system protocol is found, the ﬁrmware implements the policy of interpreting the File Path value of
the ﬁle being loaded. If the device does not support the ﬁle system protocol, the ﬁrmware then attempts to read the ﬁle
via the EFI_LOAD_FILE_PROTOCOL and the LoadFile() function. In this case the LoadFile() function implements
the policy of interpreting the File Path value.
439Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
13.1.2 EFI_LOAD_FILE_PROTOCOL.LoadFile()
Summary
Causes the driver to load a speciﬁed ﬁle.
Prototype
typedef
(EFIAPI *EFI_LOAD_FILE) (
IN EFI_LOAD_FILE_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN VOID *Buffer OPTIONAL
);
This Indicates a pointer to the calling context. Type EFI_LOAD_FILE_PROTOCOL is deﬁned in Load File Protocol .
FilePath The device speciﬁc path of the ﬁle to load. Type EFI_DEVICE_PATH_PROTOCOL is deﬁned in EFI
Device Path Protocol .
tempting to load FilePath as a boot selection. If FALSE , then FilePath must match an exact ﬁle to be loaded.
BufferSize On input the size of Buffer in bytes. On output with a return code of EFI_SUCCESS, the amount of data
transferred to Buffer. On output with a return code of EFI_BUFFER_TOO_SMALL, the size of Buffer required
to retrieve the requested ﬁle.
Buffer The memory buffer to transfer the ﬁle to. If Buffer is NULL, then the size of the requested ﬁle is returned in
BufferSize.
The LoadFile() function interprets the device-speciﬁc FilePath parameter, returns the entire ﬁle into Buffer, and sets
BufferSize to the amount of data returned. If Buffer is NULL , then the size of the ﬁle is returned in BufferSize. If
Buffer is not NULL , and BufferSize is not large enough to hold the entire ﬁle, then EFI_BUFFER_TOO_SMALL is
returned, and BufferSize is updated to indicate the size of the buffer needed to obtain the ﬁle. In this case, no data is
returned in Buffer.
If BootPolicy is FALSE the FilePath must match an exact ﬁle to be loaded. If no such ﬁle exists, EFI_NOT_FOUND
is returned. If BootPolicy is FALSE , and an attempt is being made to perform a network boot through the PXE Base
Code protocol, EFI_UNSUPPORTED is returned.
If BootPolicy is TRUE the ﬁrmware’s boot manager is attempting to load an EFI image that is a boot selection. In
this case, FilePath contains the ﬁle path value in the boot selection option. Normally the ﬁrmware would implement
the policy on how to handle an inexact boot ﬁle path; however, since in this case the ﬁrmware cannot interpret the ﬁle
path, the LoadFile() function is responsible for implementing the policy. For example, in the case of a network boot
through the PXE Base Code protocol, FilePath merely points to the root of the device, and the ﬁrmware interprets this
as wanting to boot from the ﬁrst valid loader. The following is a list of events that LoadFile() will implement for a
PXE boot:
• Perform DHCP.
• Optionally prompt the user with a menu of boot selections.
• Discover the boot server and the boot ﬁle.
• Download the boot ﬁle into Buffer and update BufferSize with the size of the boot ﬁle.
13.1. Load File Protocol 440Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If the boot ﬁle downloaded from boot server is not an UEFI-formatted executable, but a binary image which contains
a UEFI-compliant ﬁle system, then EFI_WARN_FILE_SYSTEM is returned, and a new RAM disk mapped on the
returned Buffer is registered.
EFI_SUCCESS The ﬁle was loaded.
EFI_UNSUPPORTED The device does not support the provided BootPolicy.
EFI_INV ALID_PARAMETER FilePath is not a valid device path, or BufferSize is NULL.
EFI_NO_MEDIA No medium was present to load the ﬁle.
EFI_DEVICE_ERROR The ﬁle was not loaded due to a device error.
EFI_NO_RESPONSE The remote system did not respond.
EFI_NOT_FOUND The ﬁle was not found.
EFI_ABORTED The ﬁle load process was manually cancelled.
EFI_BUFFER_TOO_SMALL The BufferSize is too small to read the current directory entry. BufferSize
has been updated with the size needed to complete the request.
EFI_WARN_FILE_SYSTEM The resulting Buffer contains UEFI-compliant ﬁle system.
13.2 Load File 2 Protocol
The Load File 2 protocol is used to obtain ﬁles from arbitrary devices that are not boot options.
13.2.1 EFI_LOAD_FILE2_PROTOCOL
Summary
Used to obtain ﬁles from arbitrary devices but are not used as boot options.
GUID
#define EFI_LOAD_FILE2_PROTOCOL_GUID \
{ 0x4006c0c1, 0xfcb3, 0x403e, \
{ 0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d }}
typedef EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE2_PROTOCOL;
LoadFile Causes the driver to load the requested ﬁle. See the LoadFile() functional description.
TheEFI_LOAD_FILE2_PROTOCOL is a simple protocol used to obtain ﬁles from arbitrary devices that are not boot
options. It is used by LoadImage() when its BootOption parameter is FALSE and the FilePath does not have an instance
of the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL .
13.2. Load File 2 Protocol 441Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
13.2.2 EFI_LOAD_FILE2_PROTOCOL.LoadFile()
Summary
Prototype
The same prototype as EFI_LOAD_FILE_PROTOCOL.LoadFile() .
This Indicates a pointer to the calling context.
FilePath The device speciﬁc path of the ﬁle to load.
BootPolicy Should always be FALSE .
transferred to Buffer . On output with a return code of EFI_BUFFER_TOO_SMALL, the size of Buffer required
Buffer The memory buffer to transfer the ﬁle to. If Buffer isNULL, then no the size of the requested ﬁle is returned
inBufferSize .
TheLoadFile() function interprets the device-speciﬁc FilePath parameter, returns the entire ﬁle into Buffer, and sets
BufferSize to the amount of data returned. If Buffer isNULL, then the size of the ﬁle is returned in BufferSize . If
Buffer is not NULL, andBufferSize is not large enough to hold the entire ﬁle, then EFI_BUFFER_TOO_SMALL is

returned in Buffer .
FilePath contains the ﬁle path value in the boot selection option. Normally the ﬁrmware would implement the policy
on how to handle an inexact boot ﬁle path; however, since in this case the ﬁrmware cannot interpret the ﬁle path, the
LoadFile() function is responsible for implementing the policy.
EFI_UNSUPPORTED BootPolicy is TRUE .
13.2. Load File 2 Protocol 442Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
13.3 File System Format
The ﬁle system supported by the Extensible Firmware Interface is based on the FAT ﬁle system. EFI deﬁnes a speciﬁc
version of FAT that is explicitly documented and testable. Conformance to the EFI speciﬁcation and its associate
reference documents is the only deﬁnition of FAT that needs to be implemented to support EFI. To differentiate the
EFI ﬁle system from pure FAT, a new partition ﬁle system type has been deﬁned.
EFI encompasses the use of FAT32 for a system partition, and FAT12 or FAT16 for removable media. The FAT32
system partition is identiﬁed by an OSType value other than that used to identify previous versions of FAT. This unique
partition type distinguishes an EFI deﬁned ﬁle system from a normal FAT ﬁle system. The ﬁle system supported by
EFI includes support for long ﬁle names.
The deﬁnition of the EFI ﬁle system will be maintained by speciﬁcation and will not evolve over time to deal with
errata or variant interpretations in OS ﬁle system drivers or ﬁle system utilities. Future enhancements and compatibility
enhancements to FAT will not be automatically included in EFI ﬁle systems. The EFI ﬁle system is a target that is
ﬁxed by the EFI speciﬁcation, and other speciﬁcations explicitly referenced by the EFI speciﬁcation.
For more information about the EFI ﬁle system and ﬁle image format, visit the web site from which this document
was obtained.
13.3.1 System Partition
A System Partition is a partition in the conventional sense of a partition on a legacy system. For a hard disk, a partition
is a contiguous grouping of sectors on the disk where the starting sector and size are deﬁned by the Master Boot Record
(MBR), which resides on LBA 0 (i.e., the ﬁrst sector of the hard disk) ( LBA 0 Format ), or the GUID Partition Table
(GPT), which resides on logical block 1 (the second sector of the hard disk) ( GPT overview ). For a diskette (ﬂoppy)
drive, a partition is deﬁned to be the entire media. A System Partition can reside on any media that is supported by
EFI Boot Services.
A System Partition supports backward compatibility with legacy systems by reserving the ﬁrst block (sector) of the
partition for compatibility code. On legacy systems, the ﬁrst block (sector) of a partition is loaded into memory and
execution is transferred to this code. EFI ﬁrmware does not execute the code in the MBR. The EFI ﬁrmware contains
knowledge about the partition structure of various devices, and can understand legacy MBR, GPT, and “El Torito.”
The System Partition contains directories, data ﬁles, and UEFI Images. UEFI Images can contain a OS Loader, an
driver to extend platform ﬁrmware capability, or an application that provides a transient service to the system. Appli-
cations written to this speciﬁcation could include things such as a utility to create partitions or extended diagnostics.
A System Partition can also support data ﬁles, such as error logs, that can be deﬁned and used by various OS or system
ﬁrmware software components.
13.3.1.1 File System Format
The ﬁrst block (sector) of a partition contains a data structure called the BIOS Parameter Block (BPB) that deﬁnes
the type and location of FAT ﬁle system on the drive. The BPB contains a data structure that deﬁnes the size of the
media, the size of reserved space, the number of FAT tables, and the location and size of the root directory (not used in
FAT32). The ﬁrst block (sector) also contains code that will be executed as part of the boot process on a legacy system.
This code in the ﬁrst block (sector) usually contains code that can read a ﬁle from the root directory into memory and
transfer control to it. Since EFI ﬁrmware contains a ﬁle system driver, EFI ﬁrmware can load any ﬁle from the ﬁle
system with out nhe FAT32, FAT16, and FAT12 variants of the EFI ﬁle system. What variant of EFI FAT to use is
deﬁned by the size of the media. The rules deﬁning theeeding to execute any code from the media.
The EFI ﬁrmware must support the FAT32, FAT16, and FAT12 variants of the EFI ﬁle system. What variant of EFI
FAT to use is deﬁned by the size of the media. The rules deﬁning the relationship between media size and FAT variants
is deﬁned in the speciﬁcation for the EFI ﬁle system.
13.3. File System Format 443Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The UEFI system partition FAT32 Data region should be aligned to the physical block boundary and optimal transfer
length granularity of the device ( GPT overview ). This is controlled by the BPB_RsvdSecCnt ﬁeld and the applicable
BPB_FATSz ﬁeld (e.g., formatting software may set the BPB_RsvdSecCnt ﬁeld to a value that results in alignment
and/or may set the BPB_FATSz ﬁeld to a value that ensures alignment).
13.3.1.2 File Names
FAT stores ﬁle names in two formats. The original FAT format limited ﬁle names to eight characters with three
extension characters. This type of ﬁle name is called an 8.3, pronounced eight dot three, ﬁle name. FAT was extended
to include support for long ﬁle names (LFN).
FAT 8.3 ﬁle names are always stored as uppercase ASCII characters. LFN can either be stored as ASCII or UCS-2
characters and are stored case sensitive. The string that was used to open or create the ﬁle is stored directly into LFN.
FAT deﬁnes that all ﬁles in a directory must have a unique name, and unique is deﬁned as a case insensitive match.
The following are examples of names that are considered to be the same and cannot exist in a single directory:
• “ThisIsAnExampleDirectory.Dir”
• “thisisanexamppledirectory.dir”
• THISISANEXAMPLEDIRECTORY .DIR
• ThisIsAnExampleDirectory.DIR
Note :Although the FAT32 speciﬁcation allows ﬁle names to be encoded using UTF-16, this speciﬁcation only recog-
nizes the UCS-2 subset for the purposes of sorting or collation .
13.3.1.3 Directory Structure
An EFI system partition that is present on a hard disk must contain an EFI deﬁned directory in the root directory.
This directory is named EFI. All OS loaders and applications will be stored in subdirectories below EFI. Applications
that are loaded by other applications or drivers are not required to be stored in any speciﬁc location in the EFI system
partition. The choice of the subdirectory name is up to the vendor, but all vendors must pick names that do not collide
with any other vendor’s subdirectory name. This applies to system manufacturers, operating system vendors, BIOS
vendors, and third party tool vendors, or any other vendor that wishes to install ﬁles on an EFI system partition. There
must also only be one executable EFI image for each supported processor architecture in each vendor subdirectory.
This guarantees that there is only one image that can be loaded from a vendor subdirectory by the EFI Boot Manager.
If more than one executable EFI image is present, then the boot behavior for the system will not be deterministic.
There may also be an optional vendor subdirectory called BOOT.
This directory contains EFI images that aide in recovery if the boot selections for the software installed on the EFI
system partition are ever lost. Any additional UEFI-compliant executables must be in subdirectories below the vendor
subdirectory. The following is a sample directory structure for an EFI system partition present on a hard disk.
\EFI
\<OS Vendor 1 Directory>
<OS Loader Image>
\<OS Vendor 2 Directory>
...
\<OS Vendor N Directory>
\<OEM Directory>
<OEM Application Image>
\<BIOS Vendor Directory>
13.3. File System Format 444Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
<BIOS Vendor Application Image>
\<Third Party Tool Vendor Directory>
<Third Party Tool Vendor Application Image>
\BOOT
BOOT{machine type short name}.EFI
For removable media devices there must be only one UEFI-compliant system partition, and that partition must contain

\EFI
...
\BOOT
an UEFI-deﬁned directory in the root directory. The directory will be named EFI. All OS loaders and applications
will be stored in a subdirectory below EFI called BOOT. There must only be one executable EFI image for each
supported processor architecture in the BOOT directory. For removable media to be bootable under EFI, it must be
built in accordance with the rules laid out in Removable Media Boot Behavior . This guarantees that there is only one
image that can be automatically loaded from a removable media device by the EFI Boot Manager. Any additional EFI
executables must be in directories other than BOOT. The following is a sample directory structure for an EFI system
partition present on a removable media device.
\EFI
\BOOT
13.3.2 Partition Discovery
This speciﬁcation requires the ﬁrmware to be able to parse the Legacy MBR ), GUID Partition Table (GPT)( GPT
overview ), and El Torito ( ISO-9660 and El Torito ) logical device volumes. The EFI ﬁrmware produces a logical
EFI_BLOCK_IO_PROTOCOL device for:
• each GUID Partition Entry (see table 16 in 5.3.3) with bit 1 set to zero;
• each El Torito logical device volume; and
• if no GPT is present, each partition found in the legacy MBR partition tables.
LBA zero of the EFI_BLOCK_IO_PROTOCOL device will correspond to the ﬁrst logical block of the partition.
See Nesting of Legacy MBR Partition Records . If a GPT Partition Entry has Attribute bit 1 set then a logical
EFI_BLOCK_IO_PROTOCOL device must not be created.
Fig. 13.1: Nesting of Legacy MBR Partition Records
The following is the order in which a block device must be scanned to determine if it contains partitions. When a
check for a valid partitioning scheme succeeds, the search terminates.
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1. Check for GUID Partition Table Headers.
2. Follow ISO-9660 speciﬁcation to search for ISO-9660 volume structures on the magic LBA.
3. Check for an “El Torito” volume extension and follow the “El Torito” CD-ROM speciﬁcation.
4. If none of the above, check LBA 0 for a legacy MBR partition table.
5. No partition found on device.
If a disk contains a recognized RAID structure (e.g. DDF structure as deﬁned in The Storage Networking Industry
Association Common RAID Disk Data Format Speciﬁcation– see Glossary), the data on the disk must be ignored,
unless the driver is using the RAID structure to produce a logical RAID volume.
EFI supports the nesting of legacy MBR partitions, by allowing any legacy MBR partition to contain more legacy MBR
partitions. This is accomplished by supporting the same partition discovery algorithm on every logical block device. It
should be noted that the GUID Partition Table does not allow nesting of GUID Partition Table Headers. Nesting is not
needed since a GUID Partition Table Header can support an arbitrary number of partitions (the addressability limits of
a 64-bit LBA are the limiting factor).
13.3.2.1 ISO-9660 and El Torito
IS0-9660 is the industry standard low level format used on CD-ROM and DVD-ROM. The CD-ROM format is com-
pletely described by the “El Torito” Bootable CD-ROM Format Speciﬁcation Version 1.0. To boot from a CD-ROM
or DVD-ROM in the boot services environment, an EFI System partition is stored in a “no emulation” mode as deﬁned
by the “El Torito” speciﬁcation. A Platform ID of 0xEF indicates an EFI System Partition. The Platform ID is in either
the Section Header Entry or the Validation Entry of the Booting Catalog as deﬁned by the “El Torito” speciﬁcation.
EFI differs from “El Torito” “no emulation” mode in that it does not load the “no emulation” image into memory and
jump to it. EFI interprets the “no emulation” image as an EFI system partition. EFI interprets the Sector Count in the
Initial/Default Entry or the Section Header Entry to be the size of the EFI system partition. If the value of Sector Count
is set to 0 or 1, EFI will assume the system partition consumes the space from the beginning of the “no emulation”
image to the end of the CD-ROM.
A DVD-ROM image formatted as required by the UDF 2.0 speciﬁcation (OSTA Universal Disk Format Speciﬁcation,
Revision 2.0) shall be booted by UEFI if:
• the DVD-ROM image conforms to the “UDF Bridge” format deﬁned in the UDF 2.0 speciﬁcation, and
• the DVD-ROM image contains exactly one ISO-9660 ﬁle system, and
• the ISO-9660 ﬁle system conforms to the “El Torito” Bootable CD-ROM Format Speciﬁcation.
Booting from a DVD-ROM that satisﬁes the above requirements is accomplished using the same methods as booting
from a CD-ROM: the ISO-9660 ﬁle system shall be booted.
Since the EFI ﬁle system deﬁnition does not use the same Initial/Default entry as a legacy CD-ROM it is possible to
boot personal computers using an EFI CD-ROM or DVD-ROM. The inclusion of boot code for personal computers is
optional and not required by EFI.
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13.3.3 Number and Location of System Partitions
UEFI does not impose a restriction on the number or location of System Partitions that can exist on a system. System
Partitions are discovered when required by UEFI ﬁrmware by examining the partition GUID and verifying that the
contents of the partition conform to the FAT ﬁle system as deﬁned in File System Format . Further, UEFI implementa-
tions may allow the use of conforming FAT partitions which do not use the ESP GUID. Partition creators may prevent
UEFI ﬁrmware from examining and using a speciﬁc partition by setting bit 1 of the Partition Attributes (see 5.3.3)
which will exclude the partition as a potential ESP.
Software installation may choose to create and locate an ESP on each target OS boot disk, or may choose to create a
single ESP independent of the location of OS boot disks and OS partitions. It is outside of the scope of this speciﬁ-
cation to attempt to coordinate the speciﬁcation of size and location of an ESP that can be shared by multiple OS or
Diagnostics installations, or to manage potential namespace collisions in directory naming in a single (central) ESP.
13.3.4 Media Formats
This section describes how booting from different types of removable media is handled. In general the rules are
consistent regardless of a media’s physical type and whether it is removable or not.
13.3.4.1 Removable Media
Removable media may contain a standard FAT12, FAT16, or FAT32 ﬁle system.
Booting from a removable media device can be accomplished the same way as any other boot. The boot ﬁle path
provided to the boot manager can consist of a UEFI application image to load, or can merely be the path to a removable
media device. In the ﬁrst case, the path clearly indicates the image that is to be loaded. In the later case, the boot
manager implements the policy to load the default application image from the device.
For removable media to be bootable under EFI, it must be built in accordance with the rules laid out in Removable
Media Boot Behavior
13.3.4.2 Diskette
EFI bootable diskettes follow the standard formatting conventions used on personal computers. The diskette contains
only a single partition that complies to the EFI ﬁle system type. For diskettes to be bootable under EFI, it must be built
in accordance with the rules laid out in Removable Media Boot Behavior .
Since the EFI ﬁle system deﬁnition does not use the code in the ﬁrst block of the diskette, it is possible to boot personal
computers using a diskette that is also formatted as an EFI bootable removable media device. The inclusion of boot
code for personal computers is optional and not required by EFI.
Diskettes include the legacy 3.5-inch diskette drives as well as the newer larger capacity removable media drives such
as an Iomega* Zip,* Fujitsu MO, or MKE LS-120/SuperDisk*.
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13.3.4.3 Hard Drive
Hard drives may contain multiple partitions as deﬁned in See Partition Discovery on partition discovery. Any partition
on the hard drive may contain a ﬁle system that the EFI ﬁrmware recognizes. Images that are to be booted must be
stored under the EFI subdirectory as deﬁned in System Partition andPartition Discovery .
EFI code does not assume a ﬁxed block size.
Since EFI ﬁrmware does not execute the MBR code and does not depend on the BootIndicator ﬁeld in the legacy MBR
partition records, the hard disk can still boot and function normally.
13.3.4.4 CD-ROM and DVD-ROM
A CD-ROM or DVD-ROM may contain multiple partitions as deﬁned in System Partition andPartition Discovery and
in the “El Torito” speciﬁcation.
Since the EFI ﬁle system deﬁnition does not use the same Initial/Default entry as a legacy CD-ROM, it is possible to
13.3.4.5 Network

To boot from a network device, the Boot Manager uses the Load File Protocol to perform a
EFI_LOAD_FILE_PROTOCOL.LoadFile() on the network device. This uses the PXE Base Code Protocol to per-
form DHCP and Discovery. This may result in a list of possible boot servers along with the boot ﬁles available on each
server. The Load File Protocol for a network boot may then optionally produce a menu of these selections for the user
to choose from. If this menu is presented, it will always have a timeout, so the Load File Protocol can automatically
boot the default boot selection. If there is only one possible boot ﬁle, then the Load File Protocol can automatically
attempt to load the one boot ﬁle.
The Load File Protocol will download the boot ﬁle using the MTFTP service in the PXE Base Code Protocol. The
downloaded image must be an EFI image that the platform supports.
13.4 Simple File System Protocol
The Simple File System protocol allows code running in the EFI boot services environment to obtain ﬁle based
access to a device. EFI_SIMPLE_FILE_SYSTEM_PROTOCOL is used to open a device volume and return an
EFI_FILE_PROTOCOL that provides interfaces to access ﬁles on a device volume.
13.4.1 EFI_SIMPLE_FILE_SYSTEM_PROTOCOL
Summary
Provides a minimal interface for ﬁle-type access to a device.
GUID
#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \
{0x0964e5b22,0x6459,0x11d2,\
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#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION 0x00010000
typedef struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL {
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_OPEN_VOLUME OpenVolume;
} EFI_SIMPLE_FILE_SYSTEM_PROTOCOL;
Revision The version of the EFI_FILE_PROTOCOL. The version speciﬁed by this speciﬁcation is 0x00010000. All
future revisions must be backwards compatible. If a future version is not backwards compatible, it is not the
same GUID.
OpenVolume Opens the volume for ﬁle I/O access. See the OpenV olume() EFI_SIMPLE_FILE SYS-
TEM_PROTOCOL.OpenVolume() function description.
The EFI_SIMPLE_FILE_SYSTEM_PROTOCOL provides a minimal interface for ﬁle-type access to a device. This
protocol is only supported on some devices.
Devices that support the Simple File System protocol return an EFI_FILE_PROTOCOL. The only function of this
interface is to open a handle to the root directory of the ﬁle system on the volume. Once opened, all accesses to the
volume are performed through the volume’s ﬁle handles, using the EFI_FILE_PROTOCOL protocol. The volume is
closed by closing all the open ﬁle handles.
The ﬁrmware automatically creates handles for any block device that supports the following ﬁle system formats:
• FAT12
• FAT16
• FAT32
13.4.2 EFI_SIMPLE_FILE SYSTEM_PROTOCOL.OpenVolume()
Summary
Opens the root directory on a volume.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_OPEN_VOLUME) (
IN EFI_SIMPLE_FILE_SYSTEM PROTOCOL *This,
OUT EFI_FILE_PROTOCOL **Root
);
This A pointer to the volume to open the root directory of. See the type EFI_SIMPLE_FILE_SYSTEM_PROTOCOL
Root A pointer to the location to return the opened ﬁle handle for the root directory. See the type see
EFI_FILE_PROTOCOL description.
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The OpenV olume() function opens a volume, and returns a ﬁle handle to the volume’s root directory. This handle is
used to perform all other ﬁle I/O operations. The volume remains open until all the ﬁle handles to it are closed.
If the medium is changed while there are open ﬁle handles to the volume, all ﬁle handles to the volume will return
EFI_MEDIA_CHANGED. To access the ﬁles on the new medium, the volume must be reopened with OpenV ol-
ume(). If the new medium is a different ﬁle system than the one supplied in the EFI_HANDLE’s DevicePath for the
EFI_SIMPLE_SYSTEM_PROTOCOL, OpenV olume() will return EFI_UNSUPPORTED.
EFI_SUCCESS The ﬁle volume was opened.
EFI_UNSUPPORTED The volume does not support the requested ﬁle system type.
EFI_NO_MEDIA The device has no medium.
EFI_VOLUME_CORRUPTED The ﬁle system structures are corrupted.
EFI_ACCESS_DENIED The service denied access to the ﬁle.
EFI_OUT_OF_RESOURCES The ﬁle volume was not opened.
EFI_MEDIA_CHANGED The device has a different medium in it or the medium is no longer sup-
ported. Any existing ﬁle handles for this volume are no longer valid. To
access the ﬁles on the new medium, the volume must be reopened with
OpenV olume().
13.5 File Protocol
The protocol and functions described in this section support access to EFI-supported ﬁle systems.
13.5.1 EFI_FILE_PROTOCOL
Summary
Provides ﬁle based access to supported ﬁle systems.
#define EFI_FILE_PROTOCOL_REVISION 0x00010000
#define EFI_FILE_PROTOCOL_REVISION2 0x00020000
#define EFI_FILE_PROTOCOL_LATEST_REVISION EFI_FILE_PROTOCOL_REVISION2
typedef struct_EFI_FILE_PROTOCOL {
EFI_FILE_OPEN Open;
EFI_FILE_CLOSE Close;
EFI_FILE_DELETE Delete;
EFI_FILE_READ Read;
EFI_FILE_WRITE Write;
EFI_FILE_GET_POSITION GetPosition;
EFI_FILE_SET_POSITION SetPosition;
EFI_FILE_GET_INFO GetInfo;
EFI_FILE_SET_INFO SetInfo;
EFI_FILE_FLUSH Flush;
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EFI_FILE_OPEN_EX OpenEx; // Added forrevision 2
EFI_FILE_READ_EX ReadEx; // Added forrevision 2
EFI_FILE_WRITE_EX WriteEx; // Added forrevision 2
EFI_FILE_FLUSH_EX FlushEx; // Added forrevision 2
} EFI_FILE_PROTOCOL;
Revision The version of the EFI_FILE_PROTOCOL interface. The version speciﬁed by this speciﬁcation is
EFI_FILE_PROTOCOL_LATEST_REVISION . Future versions are required to be backward compatible to ver-
sion 1.0.
Open Opens or creates a new ﬁle. See the EFI_FILE_PROTOCOL.Open() function description.
Close Closes the current ﬁle handle. See the EFI_FILE_PROTOCOL.Close() function description.
Delete Deletes a ﬁle. See the EFI_FILE_PROTOCOL.Delete() function description.
Read Reads bytes from a ﬁle. See the EFI_FILE_PROTOCOL.Read() function description.
Write Writes bytes to a ﬁle. See the EFI_FILE_PROTOCOL.Write() function description.
GetPosition Returns the current ﬁle position. See the EFI_FILE_PROTOCOL.GetPosition() function description.
SetPosition Sets the current ﬁle position. See the EFI_FILE_PROTOCOL.SetPosition() function description.
GetInfo Gets the requested ﬁle or volume information. See the EFI_FILE_PROTOCOL.GetInfo() function descrip-
tion.
SetInfo Sets the requested ﬁle information. See the EFI_FILE_PROTOCOL.SetInfo() function description.
Flush Flushes all modiﬁed data associated with the ﬁle to the device. See the EFI_FILE_PROTOCOL.Flush() func-
OpenEx Opens a new ﬁle relative to the source directory’s location.
ReadEx Reads data from a ﬁle.
WriteEx Writes data to a ﬁle.
FlushEx Flushes all modiﬁed data associated with a ﬁle to a device.
The EFI_FILE_PROTOCOL provides ﬁle IO access to supported ﬁle systems.
An EFI_FILE_PROTOCOL provides access to a ﬁle’s or directory’s contents, and is also a reference to a location in
the directory tree of the ﬁle system in which the ﬁle resides. With any given ﬁle handle, other ﬁles may be opened
relative to this ﬁle’s location, yielding new ﬁle handles.
On requesting the ﬁle system protocol on a device, the caller gets the EFI_FILE_PROTOCOL to the vol-
ume. This interface is used to open the root directory of the ﬁle system when needed. The caller must
EFI_FILE_PROTOCOL.Close() the ﬁle handle to the root directory, and any other opened ﬁle handles before ex-
iting. While there are open ﬁles on the device, usage of underlying device protocol(s) that the ﬁle system is
abstracting must be avoided. For example, when a ﬁle system that is layered on a EFI_DISK_IO_PROTOCOL
EFI_BLOCK_IO_PROTOCOL , direct block access to the device for the blocks that comprise the ﬁle system must
be avoided while there are open ﬁle handles to the same device.
A ﬁle system driver may cache data relating to an open ﬁle. A Flush() function is provided that ﬂushes all dirty data
in the ﬁle system, relative to the requested ﬁle, to the physical medium. If the underlying device may cache data, the
ﬁle system must inform the device to ﬂush as well.
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Implementations must account for cases where there is pending queued asynchronous I/O when a call is received on
a blocking protocol interface. In these cases the pending I/O will be processed and completed before the blocking
function is executed so that operation are carried out in the order they were requested.
13.5.2 EFI_FILE_PROTOCOL.Open()
Summary

Summary
Opens a new ﬁle relative to the source ﬁle’s location.
Prototype
typedef
(EFIAPI *EFI_FILE_OPEN) (
IN EFI_FILE_PROTOCOL *This,
OUT EFI_FILE_PROTOCOL **NewHandle,
IN CHAR16 *FileName,
IN UINT64 OpenMode,
IN UINT64 Attributes
);
This A pointer to the EFI_FILE_PROTOCOL instance that is the ﬁle handle to the source location. This would
typically be an open handle to a directory. See the type EFI_FILE_PROTOCOL description.
NewHandle A pointer to the location to return the opened handle for the new ﬁle. See the type
FileName The Null-terminated string of the name of the ﬁle to be opened. The ﬁle name may contain the following
path modiﬁers: “", “.”, and “..”.
OpenMode The mode to open the ﬁle. The only valid combinations that the ﬁle may be opened with are: Read,
Read/Write, or Create/Read/Write. See “Related Deﬁnitions” below.
Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these are the attribute bits for the newly created
ﬁle. See “Related Deﬁnitions” below.
// Open Modes
#define EFI_FILE_MODE_READ 0x0000000000000001
#define EFI_FILE_MODE_WRITE 0x0000000000000002
#define EFI_FILE_MODE_CREATE 0x8000000000000000
// File Attributes
#define EFI_FILE_READ_ONLY 0x0000000000000001
#define EFI_FILE_HIDDEN 0x0000000000000002
#define EFI_FILE_SYSTEM 0x0000000000000004
#define EFI_FILE_RESERVED 0x0000000000000008
#define EFI_FILE_DIRECTORY 0x0000000000000010
#define EFI_FILE_ARCHIVE 0x0000000000000020
#define EFI_FILE_VALID_ATTR 0x0000000000000037
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The Open()function opens the ﬁle or directory referred to by FileName relative to the location of This and returns a
NewHandle. The FileName may include the following path modiﬁers:
“\”
If the ﬁlename starts with a “\” the relative location is the root directory that This resides on; otherwise “" separates
name components. Each name component is opened in turn, and the handle to the last ﬁle opened is returned.
“.”
Opens the current location.
“..”
Opens the parent directory for the current location. If the location is the root directory the request will return an error,
as there is no parent directory for the root directory.
If EFI_FILE_MODE_CREATE is set, then the ﬁle is created in the directory. If the ﬁnal location of FileName does
not refer to a directory, then the operation fails. If the ﬁle does not exist in the directory, then a new ﬁle is created. If
the ﬁle already exists in the directory, then the existing ﬁle is opened.
If the medium of the device changes, all accesses (including the File handle) will result in EFI_MEDIA_CHANGED.
To access the new medium, the volume must be reopened.
EFI_SUCCESS The ﬁle was opened.
EFI_NOT_FOUND The speciﬁed ﬁle could not be found on the device.
ported.
EFI_WRITE_PROTECTED An attempt was made to create a ﬁle, or open a ﬁle for write when the media
is write-protected.
EFI_OUT_OF_RESOURCES Not enough resources were available to open the ﬁle.
EFI_VOLUME_FULL The volume is full.
13.5.3 EFI_FILE_PROTOCOL.Close()
Summary
Closes a speciﬁed ﬁle handle.
Prototype
typedef
(EFIAPI *EFI_FILE_CLOSE) (
IN EFI_FILE_PROTOCOL *This
);
This A pointer to the EFI_FILE_PROTOCOL instance that is the ﬁle handle to close. See the type
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The Close() function closes a speciﬁed ﬁle handle. All “dirty” cached ﬁle data is ﬂushed to the device, and the ﬁle is
closed. In all cases the handle is closed. The operation will wait for all pending asynchronous I/O requests to complete
before completing.
EFI_SUCCESS The ﬁle was closed.
13.5.4 EFI_FILE_PROTOCOL.Delete()
Summary
Closes and deletes a ﬁle.
Prototype
typedef
(EFIAPI *EFI_FILE_DELETE) (
);
This A pointer to the EFI_FILE_PROTOCOL instance that is the handle to the ﬁle to delete. See the type
The Delete() function closes and deletes a ﬁle. In all cases the ﬁle handle is closed. If the ﬁle cannot be deleted, the
warning code EFI_WARN_DELETE_FAILURE is returned, but the handle is still closed.
EFI_SUCCESS The ﬁle was closed and deleted, and the handle was closed.
EFI_WARN_DELETE_FAILURE The handle was closed, but the ﬁle was not deleted.
13.5.5 EFI_FILE_PROTOCOL.Read()
Summary
Reads data from a ﬁle.
Prototype
typedef
(EFIAPI *EFI_FILE_READ) (
);
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This A pointer to the EFI_FILE_PROTOCOL instance that is the ﬁle handle to read data from. See the type
BufferSize On input, the size of the Buffer. On output, the amount of data returned in Buffer. In both cases, the size
ismeasured in bytes.
Buffer The buffer into which the data is read.
The Read() function reads data from a ﬁle.
If This is not a directory, the function reads the requested number of bytes from the ﬁle at the ﬁle’s current position
and returns them in Buffer. If the read goes beyond the end of the ﬁle, the read length is truncated to the end of the
ﬁle. The ﬁle’s current position is increased by the number of bytes returned.
If This is a directory, the function reads the directory entry at the ﬁle’s current position and returns the entry in Buffer.
If the Buffer is not large enough to hold the current directory entry, then EFI_BUFFER_TOO_SMALL is returned
and the current ﬁle position is not updated. BufferSize is set to be the size of the buffer needed to read the entry. On
success, the current position is updated to the next directory entry. If there are no more directory entries, the read
returns a zero-length buffer. EFI_FILE_INFO is the structure returned as the directory entry.
EFI_DEVICE_ERROR An attempt was made to read from a deleted ﬁle.
EFI_DEVICE_ERROR On entry, the current ﬁle position is beyond the end of the ﬁle.
13.5.6 EFI_FILE_PROTOCOL.Write()
Summary
Writes data to a ﬁle.
Prototype
typedef
(EFIAPI *EFI_FILE_WRITE) (
);
This A pointer to the EFI_FILE_PROTOCOL instance that is the ﬁle handle to write data to. See the type
BufferSize On input, the size of the Buffer. On output, the amount of data actually written. In both cases, the size is
measured in bytes.
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The Write() function writes the speciﬁed number of bytes to the ﬁle at the current ﬁle position. The current ﬁle position
is advanced the actual number of bytes written, which is returned in BufferSize. Partial writes only occur when there
has been a data error during the write attempt (such as “ﬁle space full”). The ﬁle is automatically grown to hold the
data if required.
Direct writes to opened directories are not supported.
EFI_UNSUPPORT Writes to open directory ﬁles are not supported.
EFI_DEVICE_ERROR An attempt was made to write to a deleted ﬁle.
EFI_WRITE_PROTECTED The ﬁle or medium is write-protected.
EFI_ACCESS_DENIED The ﬁle was opened read only.
13.5.7 EFI_FILE_PROTOCOL.OpenEx()
Summary
Opens a new ﬁle relative to the source directory’s location.
Prototype
typedef
(EFIAPI *EFI_FILE_OPEN_EX) (
IN UINT64 Attributes,
IN OUT EFI_FILE_IO_TOKEN *Token
);
EFI_FILE_PROTOCOL description

Summary
Prototype
typedef
);
EFI_FILE_PROTOCOL description. For asynchronous I/O, this pointer must remain valid for the duration
of the asynchronous operation.
Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these are the attribute bits for the
Token A pointer to the token associated with the transaction. Type EFI_FILE_IO_TOKEN is deﬁned in “Related
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TheOpenEx() function opens the ﬁle or directory referred to by FileName relative to the location of This and returns
aNewHandle . The FileName may include the path modiﬁers described previously in Open() .
IfEFI_FILE_MODE_CREATE is set, then the ﬁle is created in the directory. If the ﬁnal location of FileName does
If the medium of the device changes, all accesses (including the Filehandle) will result in EFI_MEDIA_CHANGED .
If an error is returned from the call to OpenEx() and non-blocking I/O is being requested, the Event associated with
this request will not be signaled. If the call to OpenEx() succeeds then the Event will be signaled upon completion of
the open or if an error occurs during the processing of the request. The status of the read request can be determined
from the Status ﬁeld of the Token once the event is signaled.
UINTN BufferSize;
VOID *Buffer;
} EFI_FILE_IO_TOKEN;
Event IfEvent isNULL , then blocking I/O is performed. If Event is not NULL and non-blocking I/O is supported,
then non-blocking I/O is performed, and Event will be signaled when the read request is completed. The
caller must be prepared to handle the case where the callback associated with Event occurs before the original
asynchronous I/O request call returns.
Status Deﬁnes whether or not the signaled event encountered an error.
BufferSize
For OpenEx() : Not Used, ignored
For ReadEx() :On input, the size of the Buffer . On output, the amount of data returned in Buffer . In both cases,
the size is measured in bytes.
For WriteEx() : On input, the size of the Buffer . On output, the amount of data actually written. In both cases,
For FlushEx() : Not used, ignored
Buffer
For OpenEx(): Not Used, ignored
For ReadEx() : The buffer into which the data is read.
For WriteEx() : The buffer of data to write.
For FlushEx() : Not Used, ignored
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EFI_SUCCESS
Returned from the call OpenEx()
IfEvent is NULL (blocking I/O): The ﬁle was opened successfully.
IfEvent is not NULL (asynchronous I/O): The request was successfully
queued for processing.
Event will be signaled upon completion. Returned in the token after
signaling Event
The ﬁle was opened successfully.
EFI_NOT_FOUND The device has no medium.
EFI_NO_MEDIA The speciﬁed ﬁle could not be found on the device.
EFI_OUT_OF_RESOURCES Unable to queue the request or open the ﬁle due to lack of resources.
13.5.8 EFI_FILE_PROTOCOL.ReadEx()
Summary
Prototype
typedef
(EFIAPI *EFI_FILE_READ_EX) (
);
TheReadEx() function reads data from a ﬁle.
and returns them in Buffer . If the read goes beyond the end of the ﬁle, the read length is truncated to the end of the
If This is a directory, the function reads the directory entry at the ﬁle’s current position and returns the entry in* Buffer .
If the Buffer is not large enough to hold the current directory entry, then EFI_BUFFER_TOO_SMALL is returned and
the current ﬁle position is not updated. BufferSize is set to be the size of the buffer needed to read the entry. On success,
the current position is updated to the next directory entry. If there are no more directory entries, the read returns a
zero-length buffer. EFI_FILE_INFO is the structure returned as the directory entry.
If non-blocking I/O is used the ﬁle pointer will be advanced based on the order that read requests were submitted.
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If an error is returned from the call to ReadEx() and non-blocking I/O is being requested, the Event associated with
this request will not be signaled. If the call to ReadEx() succeeds then the Event will be signaled upon completion of
the read or if an error occurs during the processing of the request. The status of the read request can be determined
Returned from the call ReadEx()
IfEvent is NULL (blocking I/O):
The data was read successfully.
IfEvent is not NULL (asynchronous I/O):
The request was successfully queued for processing. Event will be
signaled upon completion.
Returned in the token after signaling Event
EFI_OUT_OF_RESOURCES Unable to queue the request due to lack of resources.
13.5.9 EFI_FILE_PROTOCOL.WriteEx()
Summary
Prototype
typedef
(EFIAPI *EFI_FILE_WRITE_EX) (
);
Deﬁnitions” above.
The WriteEx() function writes the speciﬁed number of bytes to the ﬁle at the current ﬁle position. The current ﬁle
position is advanced the actual number of bytes written, which is returned in BufferSize . Partial writes only occur
when there has been a data error during the write attempt (such as “ﬁle space full”). The ﬁle is automatically grown to
hold the data if required.
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If non-blocking I/O is used the ﬁle pointer will be advanced based on the order that write requests were submitted.
If an error is returned from the call to WriteEx() and non-blocking I/O is being requested, the Event associated with
this request will not be signaled. If the call to WriteEx() succeeds then the Event will be signaled upon completion of
the write or if an error occurs during the processing of the request. The status of the write request can be determined
Returned from the call WriteEx()
The data was written successfully.
The request was successfully queued for processing. Event will be signaled
upon completion.
EFI_UNSUPPORTED Writes to open directory ﬁles are not supported.

13.5.10 EFI_FILE_PROTOCOL.FlushEx()
Summary
Flushes all modiﬁed data associated with a ﬁle to a device.
Prototype
typedef
(EFIAPI *EFI_FILE_FLUSH_EX) (
);
This A pointer to the EFI_FILE_PROTOCOL instance that is the ﬁle handle to ﬂush. See the type
Deﬁnitions” above. The BufferSize andBuffer ﬁelds are not used for a FlushEx operation.
TheFlushEx() function ﬂushes all modiﬁed data associated with a ﬁle to a device.
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For non-blocking I/O all writes submitted before the ﬂush request will be ﬂushed.
If an error is returned from the call to FlushEx() and non-blocking I/O is being requested, the Event associated with
this request will not be signaled.
Returned from the call FlushEx()
The data was ﬂushed successfully.
EFI_ACCESS_DENIED The ﬁle was opened read-only.
13.5.11 EFI_FILE_PROTOCOL.SetPosition()
Summary
Sets a ﬁle’s current position.
Prototype
typedef
(EFIAPI *EFI_FILE_SET_POSITION) (
IN UINT64 Position
);
This A pointer to the EFI_FILE_PROTOCOL instance that is the he ﬁle handle to set the requested position on. See
the type EFI_FILE_PROTOCOL description.
Position The byte position from the start of the ﬁle to set.
The SetPosition() function sets the current ﬁle position for the handle to the position supplied. With the exception
of seeking to position 0xFFFFFFFFFFFFFFFF, only absolute positioning is supported, and seeking past the end of
the ﬁle is allowed (a subsequent write would grow the ﬁle). Seeking to position 0xFFFFFFFFFFFFFFFF causes the
current position to be set to the end of the ﬁle.
If This is a directory, the only position that may be set is zero. This has the effect of starting the read process of the
directory entries over.
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EFI_SUCCESS The position was set.
EFI_UNSUPPORTED The seek request for nonzero is not valid on open directories.
EFI_DEVICE_ERROR An attempt was made to set the position of a deleted ﬁle.
13.5.12 EFI_FILE_PROTOCOL.GetPosition()
Summary
Returns a ﬁle’s current position.
Prototype
typedef
(EFIAPI *EFI_FILE_GET_POSITION) (
OUT UINT64 *Position
);
This A pointer to the EFI_FILE_PROTOCOL instance that is the ﬁle handle to get the current position on. See the
type EFI_FILE_PROTOCOL description.
Position The address to return the ﬁle’s current position value.
The GetPosition() function returns the current ﬁle position for the ﬁle handle. For directories, the current ﬁle position
has no meaning outside of the ﬁle system driver and as such the operation is not supported. An error is returned if This
is a directory.
EFI_SUCCESS The position was returned.
EFI_UNSUPPORTED The request is not valid on open directories.
EFI_DEVICE_ERROR An attempt was made to get the position from a deleted ﬁle.
13.5.13 EFI_FILE_PROTOCOL.GetInfo()
Summary
Returns information about a ﬁle.
Prototype
typedef
(EFIAPI *EFI_FILE_GET_INFO) (
);
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This A pointer to the EFI_FILE_PROTOCOL instance that is the ﬁle handle the requested information is for. See the
InformationType The type identiﬁer for the information being requested. Type EFI_GUID is deﬁned on page 181.
See the EFI_FILE_INFO andEFI_FILE_SYSTEM_INFO descriptions for the related GUID deﬁnitions.
BufferSize On input, the size of Buffer. On output, the amount of data returned in Buffer. In both cases, the size is
Buffer A pointer to the data buffer to return. The buffer’s type is indicated by InformationType.
The GetInfo() function returns information of type InformationType for the requested ﬁle. If the ﬁle does not support
the requested information type, then EFI_UNSUPPORTED is returned. If the buffer is not large enough to ﬁt the
requested structure, EFI_BUFFER_TOO_SMALL is returned and the BufferSize is set to the size of buffer that is
required to make the request.
The information types deﬁned by this speciﬁcation are required information types that all ﬁle systems must support.
EFI_SUCCESS The information was set.
EFI_UNSUPPORTED The InformationType is not known.
EFI_BUFFER_TOO_SMALL
The BufferSize is too small to read the current directory entry.
BufferSize has been updated with the size needed to complete the request.
13.5.14 EFI_FILE_PROTOCOL.SetInfo()
Summary
Sets information about a ﬁle.
Prototype
typedef
(EFIAPI *EFI_FILE_SET_INFO) (
IN UINTN BufferSize,
);
This A pointer to the EFI_FILE_PROTOCOL instance that is the ﬁle handle the information is for. See the type
InformationType The type identiﬁer for the information being set. Type EFI_GUID is deﬁned in page 181. See the
EFI_FILE_INFO andEFI_FILE_SYSTEM_INFO descriptions in this section for the related GUID deﬁnitions.
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BufferSize The size, in bytes, of Buffer
Buffer A pointer to the data buffer to write. The buffer’s type is indicated by InformationType.
The SetInfo() function sets information of type InformationType on the requested ﬁle. Because a read-only ﬁle can be
opened only in read-only mode, an InformationType ofEFI_FILE_INFO_ID can be used with a read-only ﬁle because
this method is the only one that can be used to convert a read-only ﬁle to a read-write ﬁle. In this circumstance, only
theAttribute ﬁeld of the EFI_FILE_INFO structure may be modiﬁed. One or more calls to SetInfo() to change the
Attribute ﬁeld are permitted before it is closed. The ﬁle attributes will be valid the next time the ﬁle is opened with
Open() .
AnInformationType ofEFI_FILE_SYSTEM_INFO_ID orEFI_FILE_SYSTEM_VOLUME_LABEL_ID may not be
used on read-only media.
EFI_WRITE_PROTECTED InformationType isEFI_FILE_INFO_ID and the media is read-only.
EFI_WRITE_PROTECTED InformationType isEFI_FILE_PROTOCOL_SYSTEM_INFO_ID and the
media is read only.
EFI_WRITE_PROTECTED InformationType isEFI_FILE_SYSTEM_VOLUME_LABEL_ID and the
media is read-only.
EFI_ACCESS_DENIED An attempt is made to change the name of a ﬁle to a ﬁle that is already
present.
EFI_ACCESS_DENIED An attempt is being made to change the EFI_FILE_DIRECTORY Attribute .
EFI_ACCESS_DENIED An attempt is being made to change the size of a directory.
EFI_ACCESS_DENIED InformationType isEFI_FILE_INFO_ID and the ﬁle was opened read-only
and an attempt is being made to modify a ﬁeld other than Attribute .
EFI_BAD_BUFFER_SIZE BufferSize is smaller than the size of the type indicated by InformationType.
13.5.15 EFI_FILE_PROTOCOL.Flush()
Summary
Prototype
typedef
(EFIAPI *EFI_FILE_FLUSH) (
);
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The Flush() function ﬂushes all modiﬁed data associated with a ﬁle to a device.
EFI_SUCCESS The data was ﬂushed.

Summary
Prototype
typedef
);
13.5.16 EFI_FILE_INFO
Summary
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.SetInfo() and
EFI_FILE_PROTOCOL.GetInfo() to set or get generic ﬁle information.
GUID
#define EFI_FILE_INFO_ID \
{0x09576e92,0x6d3f,0x11d2,\
{0x8e39,0x00,0xa0,0xc9,0x69,0x72,0x3b}}
UINT64 Size;
UINT64 FileSize;
UINT64 PhysicalSize;
EFI_TIME CreateTime;
EFI_TIME LastAccessTime;
EFI_TIME ModificationTime;
CHAR16 FileName [];
} EFI_FILE_INFO;
// File Attribute Bits
Size Size of the EFI_FILE_INFO structure, including the Null-terminated FileName string.
FileSize The size of the ﬁle in bytes.
PhysicalSize The amount of physical space the ﬁle consumes on the ﬁle system volume.
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CreateTime The time the ﬁle was created.
LastAccessTime The time when the ﬁle was last accessed.
ModiﬁcationTime The time when the ﬁle’s contents were last modiﬁed.
Attribute The attribute bits for the ﬁle. See “Related Deﬁnitions” above.
FileName The Null-terminated name of the ﬁle. For a root directory, the name is an empty string.
The EFI_FILE_INFO data structure supports EFI_FILE_PROTOCOL.GetInfo() and
EFI_FILE_PROTOCOL.SetInfo() requests. In the case of SetInfo(), the following additional rules apply:
• On directories, the ﬁle size is determined by the contents of the directory and cannot be changed by setting
FileSize. On directories, FileSize is ignored during a SetInfo().
• The PhysicalSize is determined by the FileSize and cannot be changed. This value is ignored during a SetInfo()
request.
• The EFI_FILE_DIRECTORY attribute bit cannot be changed. It must match the ﬁle’s actual type.
• A value of zero in CreateTime, LastAccess, or ModiﬁcationTime causes the ﬁelds to be ignored (and not up-
dated).
13.5.17 EFI_FILE_SYSTEM_INFO
Summary
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo() to get information about
the system volume, and EFI_FILE_PROTOCOL.SetInfo() to set the system volume’s volume label.
GUID
#define EFI_FILE_SYSTEM_INFO_ID \
{0x09576e93,0x6d3f,0x11d2,0x8e39,0x00,0xa0,0xc9,0x69,0x72,\
0x3b}
BOOLEAN ReadOnly;
UINT64 VolumeSize;
UINT64 FreeSpace;
UINT32 BlockSize;
CHAR16 VolumeLabel[];
} EFI_FILE_SYSTEM_INFO;
Size Size of the EFI_FILE_SYSTEM_INFO structure, including he Null-terminated V olumeLabel string.
ReadOnly TRUE if the volume only supports read access.
VolumeSize The number of bytes managed by the ﬁle system.
FreeSpace The number of available bytes for use by the ﬁle system.
BlockSize The nominal block size by which ﬁles are typically grown.
VolumeLabel The Null-terminated string that is the volume’s label.
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The EFI_FILE_SYSTEM_INFO data structure is an information structure that can be obtained on the root di-
rectory ﬁle handle. The root directory ﬁle handle is the ﬁle handle ﬁrst obtained on the initial call to the
EFI_BOOT_SERVICES.HandleProtocol() function to open the ﬁle system interface. All of the ﬁelds are read-
only except for V olumeLabel. The system volume’s V olumeLabel can be created or modiﬁed by calling
EFI_FILE_PROTOCOL.SetInfo() with an updated V olumeLabel ﬁeld.
13.5.18 EFI_FILE_SYSTEM_VOLUME_LABEL
Summary
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo() or
EFI_FILE_PROTOCOL.SetInfo() to get or set information about the system’s volume label.
GUID
#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \
{0xdb47d7d3,0xfe81,0x11d3,0x9a35,\
{0x00,0x90,0x27,0x3f,0xC1,0x4d}}
} EFI_FILE_SYSTEM_VOLUME_LABEL;
The EFI_FILE_SYSTEM_VOLUME_LABEL data structure is an information structure that can be obtained on the
root directory ﬁle handle. The root directory ﬁle handle is the ﬁle handle ﬁrst obtained on the initial call to the
EFI_BOOT_SERVICES.HandleProtocol() function to open the ﬁle system interface. The system volume’s V olumeLa-
bel can be created or modiﬁed by calling EFI_FILE_PROTOCOL.SetInfo() with an updated V olumeLabel ﬁeld.
13.6 Tape Boot Support
13.6.1 Tape I/O Support
This section deﬁnes the Tape I/O Protocol and standard tape header format. These enable the support of booting from
tape on UEFI systems. This protocol is used to abstract the tape drive operations to support applications written to this
speciﬁcation.
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13.6.2 Tape I/O Protocol
This section deﬁnes the Tape I/O Protocol and its functions. This protocol is used to abstract the tape drive operations
to support applications written to this speciﬁcation.
13.6.2.1 EFI_TAPE_IO_PROTOCOL
Summary
The EFI Tape IO protocol provides services to control and access a tape device.
GUID
#define EFI_TAPE_IO_PROTOCOL_GUID \
{0x1e93e633,0xd65a,0x459e, \
{0xab,0x84,0x93,0xd9,0xec,0x26,0x6d,0x18}}
typedef struct_EFI_TAPE_IO_PROTOCOL {
EFI_TAPE_READ TapeRead;
EFI_TAPE_WRITE TapeWrite;
EFI_TAPE_REWIND TapeRewind;
EFI_TAPE_SPACE TapeSpace;
EFI_TAPE_WRITEFM TapeWriteFM;
EFI_TAPE_RESET TapeReset;
} EFI_TAPE_IO_PROTOCOL;
TapeRead Read a block of data from the tape. See the EFI_TAPE_IO_PROTOCOL.TapeRead() description.
TapeWrite Write a block of data to the tape. See the EFI_TAPE_IO_PROTOCOL.TapeWrite() description.
TapeRewind Rewind the tape. See the EFI_TAPE_IO_PROTOCOL.TapeRewind() description.
TapeSpace Position the tape. See the EFI_TAPE_IO_PROTOCOL.TapeSpace() description.
TapeWriteFM Write ﬁlemarks to the tape. See the EFI_TAPE_IO_PROTOCOL.TapeWriteFM() description.
TapeReset Reset the tape device or its parent bus. See the EFI_TAPE_IO_PROTOCOL.TapeReset() description.
The EFI_TAPE_IO_PROTOCOL provides basic sequential operations for tape devices. These include read, write,
rewind, space, write ﬁlemarks and reset functions. Per this speciﬁcation, a boot application uses the services of this
protocol to load the bootloader image from tape.
No provision is made for controlling or determining media density or compression settings. The protocol relies on
devices to behave normally and select settings appropriate for the media loaded. No support is included for tape
partition support, setmarks or other tapemarks such as End of Data. Boot tapes are expected to use normal variable or
ﬁxed block size formatting and ﬁlemarks.
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13.6.2.2 EFI_TAPE_IO_PROTOCOL.TapeRead()
Summary
Reads from the tape.
Prototype
typedef
(EFIAPI *EFI_TAPE_READ) (
IN EFI_TAPE_IO_PROTOCOL *This,
);
This A pointer to the EFI_TAPE_IO_PROTOCOL instance.
BufferSize Size of the buffer in bytes pointed to by Buffer
Buffer Pointer to the buffer for data to be read into.
This function will read up to BufferSize bytes from media into the buffer pointed to by Buffer using an implementation-
speciﬁc timeout. BufferSize will be updated with the number of bytes transferred.
Each read operation for a device that operates in variable block size mode reads one media data block. Unread bytes
which do not ﬁt in the buffer will be skipped by the next read operation. The number of bytes transferred will be
limited by the actual media block size. Best practice is for the buffer size to match the media data block size. When a
ﬁlemark is encountered in variable block size mode the read operation will indicate that 0 bytes were transferred and
the function will return an EFI_END_OF_FILE error condition.
In ﬁxed block mode the buffer is expected to be a multiple of the data block size. Each read operation for a device
that operates in ﬁxed block size mode may read multiple media data blocks. The number of bytes transferred will be
limited to an integral number of complete media data blocks. BufferSize should be evenly divisible by the device’s
ﬁxed block size. When a ﬁlemark is encountered in ﬁxed block size mode the read operation will indicate that the

number of bytes transferred is less than the number of blocks that would ﬁt in the provided buffer (possibly 0 bytes
transferred) and the function will return an EFI_END_OF_FILE error condition.
Two consecutive ﬁlemarks are normally used to indicate the end of the last ﬁle on the media.
The value speciﬁed for BufferSize should correspond to the actual block size used on the media. If necessary, the value
forBufferSize may be larger than the actual media block size.
Specifying a BufferSize of 0 is valid but requests the function to provide read-related status information instead of
actual media data transfer. No data will be attempted to be read from the device however this operation is classiﬁed as
an access for status handling. The status code returned may be used to determine if a ﬁlemark has been encountered
by the last read request with a non-zero size, and to determine if media is loaded and the device is ready for reading.
ANULL value for Buffer is valid when BufferSize is zero.
EFI_SUCCESS Data was successfully transferred from the media.
EFI_END_OF_FILE A ﬁlemark was encountered which limited the data transferred by the read
operation or the head is positioned just after a ﬁlemark.
EFI_NO_MEDIA No media is loaded in the device.
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Table 13.17 – continued from previous page
EFI_MEDIA_CHANGED The media in the device was changed since the last access. The transfer was
aborted since the current position of the media may be incorrect.
EFI_DEVICE_ERROR A device error occurred while attempting to transfer data from the media.
EFI_INV ALID_PARAMETER ANULL Buffer was speciﬁed with a non-zero BufferSize or the device is
operating in ﬁxed block size mode and the BufferSize was not a multiple of
device’s ﬁxed block size
EFI_NOT_READY The transfer failed since the device was not ready (e.g. not online). The
transfer may be retried at a later time.
EFI_UNSUPPORTED The device does not support this type of transfer.
EFI_TIMEOUT The transfer failed to complete within the timeout speciﬁed.
13.6.2.3 EFI_TAPE_IO_PROTOCOL.TapeWrite()
Summary
Write to the tape.
Prototype
Typedef EFI_STATUS
(EFIAPI *EFI_TAPE_WRITE) (
IN UINTN *BufferSize,
);
BufferSize Size of the buffer in bytes pointed to by Buffer .
Buffer Pointer to the buffer for data to be written from.
This function will write BufferSize bytes from the buffer pointed to by Buffer to media using an implementation-
speciﬁc timeout.
Each write operation for a device that operates in variable block size mode writes one media data block of BufferSize
bytes.
Each write operation for a device that operates in ﬁxed block size mode writes one or more media data blocks of the
device’s ﬁxed block size. BufferSize must be evenly divisible by the device’s ﬁxed block size.
Although sequential devices in variable block size mode support a wide variety of block sizes, many issues may be
avoided in I/O software, adapters, hardware and ﬁrmware if common block sizes are used such as: 32768, 16384,
8192, 4096, 2048, 1024, 512, and 80.
BufferSize will be updated with the number of bytes transferred.
When a write operation occurs beyond the logical end of media an EFI_END_OF_MEDIA error condition will occur.
Normally data will be successfully written and BufferSize will be updated with the number of bytes transferred. Ad-
ditional write operations will continue to fail in the same manner. Excessive writing beyond the logical end of media
should be avoided since the physical end of media may be reached.
Specifying a BufferSize of 0 is valid but requests the function to provide write-related status information instead of
actual media data transfer. No data will be attempted to be written to the device however this operation is classiﬁed as
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an access for status handling. The status code returned may be used to determine if media is loaded, writable and if
the logical end of media point has been reached. A NULL value for Buffer is valid when BufferSize is zero.
EFI_SUCCESS Data was successfully transferred to the media.
EFI_END_OF_MEDIA The logical end of media has been reached. Data may have been success-
fully transferred to the media.
EFI_WRITE_PROTECTED The media in the device is write-protected. The transfer was aborted since
a write cannot be completed.
operating in ﬁxed block size mode and BufferSize was not a multiple of
device’s ﬁxed block size.
13.6.2.4 EFI_TAPE_IO_PROTOCOL.TapeRewind()
Summary
Rewinds the tape.
Prototype
typedef
(EFIAPI *EFI_TAPE_REWIND) (
);
This function will rewind the media using an implementation-speciﬁc timeout. The function will check if the media
was changed since the last access and reinstall the EFI_TAPE_IO_PROTOCOL interface for the device handle if
needed.
EFI_SUCCESS The media was successfully repositioned.
EFI_DEVICE_ERROR A device error occurred while attempting to reposition the media.
EFI_NOT_READY Repositioning the media failed since the device was not ready (e.g. not
online). The transfer may be retried at a later time.
EFI_UNSUPPORTED The device does not support this type of media repositioning.
EFI_TIMEOUT Repositioning of the media did not complete within the timeout speciﬁed.
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13.6.2.5 EFI_TAPE_IO_PROTOCOL.TapeSpace()
Summary
Positions the tape.
Prototype
typedef
(EFIAPI *EFI_TAPE_SPACE) (
IN INTN Direction,
IN UINTN Type
);
Direction Direction and number of data blocks or ﬁlemarks to space over on media.
Type Type of mark to space over on media.
This function will position the media using an implementation-speciﬁc timeout.
A positive Direction value will indicate the number of data blocks or ﬁlemarks to forward space the media. A negative
Direction value will indicate the number of data blocks or ﬁlemarks to reverse space the media.
The following Type marks are mandatory:
Type of Tape Mark MarkType
BLOCK 0
FILEMARK 1
Space operations position the media past the data block or ﬁlemark. Forward space operations leave media positioned
with the tape device head after the data block or ﬁlemark. Reverse space operations leave the media positioned with
the tape device head before the data block or ﬁlemark.
If beginning of media is reached before a reverse space operation passes the requested number of data blocks or ﬁle-
marks an EFI_END_OF_MEDIA error condition will occur. If end of recorded data or end of physical media is reached
before a forward space operation passes the requested number of data blocks or ﬁlemarks an EFI_END_OF_MEDIA
error condition will occur. An EFI_END_OF_MEDIA error condition will not occur due to spacing over data blocks
or ﬁlemarks past the logical end of media point used to indicate when write operations should be limited.
EFI_END_OF_MEDIA Beginning or end of media was reached before the indicated number of data
blocks or ﬁlemarks were found.
EFI_MEDIA_CHANGED The media in the device was changed since the last access. Reposition-
ing the media was aborted since the current position of the media may be
incorrect.
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Table 13.21 – continued from previous page

13.6.2.6 EFI_TAPE_IO_PROTOCOL.TapeWriteFM()
Summary
Writes ﬁlemarks to the media.
Prototype
typedef
(EFIAPI *EFI_TAPE_WRITEFM) (
IN UINTN Count
);
Count Number of ﬁlemarks to write to the media.
This function will write ﬁlemarks to the tape using an implementation-speciﬁc timeout.
Writing ﬁlemarks beyond logical end of tape does not result in an error condition unless physical end of media is
reached.
13.6.2.7 EFI_TAPE_IO_PROTOCOL.TapeReset()
Summary
Resets the tape device.
Prototype
typedef
(EFIAPI *EFI_TAPE_RESET) (
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);
ExtendedVeriﬁcation Indicates whether the parent bus should also be reset.
This function will reset the tape device. If ExtendedVeriﬁcation is set to TRUE , the function will reset the par-
ent bus (e.g., SCSI bus). The function will check if the media was changed since the last access and reinstall the
EFI_TAPE_IO_PROTOCOL interface for the device handle if needed. Note media needs to be loaded and device
online for the reset, otherwise, EFI_DEVICE_ERROR is returned.
EFI_SUCCESS The bus and/or device were successfully reset.
EFI_DEVICE_ERROR A device error occurred while attempting to reset the bus and/or device.
EFI_NOT_READY The reset failed since the device and/or bus was not ready. The reset may
be retried at a later time.
EFI_UNSUPPORTED The device does not support this type of reset.
EFI_TIMEOUT The reset did not complete within the timeout allowed.
13.6.3 Tape Header Format
The boot tape will contain a Boot Tape Header to indicate it is a valid boot tape. The Boot Tape Header must be
located within the ﬁrst 20 blocks on the tape. One or more tape ﬁlemarks may appear prior to the Boot Tape Header so
that boot tapes may include tape label ﬁles. The Boot Tape Header must begin on a block boundary and be contained
completely within a block. The Boot Tape Header will have the following format:
Table 13.24: Tape Header Formats
Bytes
(Dec)Value Purpose
0-7 0x544f4f4220494645 Signature (‘EFI BOOT’ in ASCII)
8-11 1 Revision
12-15 1024 Tape Header Size in bytes
16-19 calculated Tape Header CRC
20-35 { 0x8befa29a,
0x3511, 0x4cf7, {
0xa2, 0xeb, 0x5f,
0xe3, 0x7c, 0x3b,
0xf5, 0x5b } }EFI Boot Tape GUID (same for all EFI Boot Tapes, like EFI Disk GUID)
36-51 User Deﬁned EFI Boot Tape Type GUID (bootloader / OS speciﬁc, like EFI Partition Type
GUID)
52-67 User Deﬁned EFI Boot Tape Unique GUID (unique for every EFI Boot Tape)
68-71 e.g. 2 File Number of EFI Bootloader relative to the Boot Tape Header (ﬁrst ﬁle im-
mediately after the Boot Tape Header is ﬁle number 1, ANSI labels are counted)
72-75 e.g. 0x400 EFI Bootloader Block Size in bytes
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Table 13.24 – continued from previous page
76-79 e.g. 0x20000 EFI Bootloader Total Size in bytes
80-119 e.g. HPUX 11.23 OS Version (ASCII)
120-159 e.g. Ignite-UX
C.6.2.241Application Version (ASCII)
160-169 e.g.1993-02-28 EFI Boot Tape creation date (UTC) (yyyy-mm-dd ASCII)
170-179 e.g. 13:24:55 EFI Boot Tape creation time (UTC) (hh:mm:ss in ASCII)
180-435 e.g. testsys1
(alt e.g. test-
sys1.xyzcorp.com)Computer System Name (UTF-8, ref: RFC 2044)
436-555 e.g. Primary Disas-
ter RecoveryBoot Tape Title / Comment (UTF-8, ref: RFC 2044)
556-
1023reserved
All numeric values will be speciﬁed in binary format. Note that all values are speciﬁed in Little Endian byte ordering.
The Boot Tape Header can also be represented as the following data structure:
typedef struct EFI_TAPE_HEADER {
UINT32 BootDescSize;
UINT32 BootDescCRC;
EFI_GUID TapeGUID;
EFI_GUID TapeType;
EFI_GUID TapeUnique;
UINT32 BLLocation;
UINT32 BLBlocksize;
UINT32 BLFilesize;
CHAR8 OSVersion[40];
CHAR8 AppVersion[40];
CHAR8 CreationDate[10];
CHAR8 CreationTime[10];
CHAR8 SystemName[256]; // UTF-8
CHAR8 TapeTitle[120]; // UTF-8
CHAR8 pad[468]; // pad to 1024
} EFI_TAPE_HEADER;
13.7 Disk I/O Protocol
This section deﬁnes the Disk I/O protocol. This protocol is used to abstract the block accesses of the Block I/O
protocol to a more general offset-length protocol. The ﬁrmware is responsible for adding this protocol to any Block
I/O interface that appears in the system that does not already have a Disk I/O protocol. File systems and other disk
access code utilize the Disk I/O protocol.
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13.7.1 EFI_DISK_IO_PROTOCOL
Summary
This protocol is used to abstract Block I/O interfaces.
GUID
#define EFI_DISK_IO_PROTOCOL_GUID \
{0xCE345171,0xBA0B,0x11d2,\
{0x8e,0x4F,0x00,0xa0,0xc9,0x69,0x72,0x3b}}
#define EFI_DISK_IO_PROTOCOL_REVISION 0x00010000
typedef struct _EFI_DISK_IO_PROTOCOL {
EFI_DISK_READ ReadDisk;
EFI_DISK_WRITE WriteDisk;
} EFI_DISK_IO_PROTOCOL;
Revision The revision to which the disk I/O interface adheres. All future revisions must be backwards compatible. If
a future version is not backwards compatible, it is not the same GUID.
ReadDisk Reads data from the disk. See the EFI_DISK_IO_PROTOCOL.ReadDisk() function description.
WriteDisk Writes data to the disk. See the EFI_DISK_IO_PROTOCOL.WriteDisk() function description.
The EFI_DISK_IO_PROTOCOL is used to control block I/O interfaces.
The disk I/O functions allow I/O operations that need not be on the underlying device’s block boundaries or alignment
requirements. This is done by copying the data to/from internal buffers as needed to provide the proper requests to the
block I/O device. Outstanding write buffer data is ﬂushed by using the EFI_BLOCK_IO_PROTOCOL.FlushBlocks()
function of the EFI_BLOCK_IO_PROTOCOL on the device handle.
The ﬁrmware automatically adds an EFI_DISK_IO_PROTOCOL interface to any EFI_BLOCK_IO_PROTOCOL in-
terface that is produced. It also adds ﬁle system, or logical block I/O, interfaces to any EFI_DISK_IO_PROTOCOL
interface that contains any recognized ﬁle system or logical block I/O devices. The ﬁrmware must automatically
support the following required formats:
• The EFI FAT12, FAT16, and FAT32 ﬁle system type.
• The legacy master boot record partition block. (The presence of this on any block I/O device is optional, but if
it is present the ﬁrmware is responsible for allocating a logical device for each partition).
• The extended partition record partition block.
• The El Torito logical block devices.
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13.7.2 EFI_DISK_IO_PROTOCOL.ReadDisk()
Summary
Reads a speciﬁed number of bytes from a device.
Prototype
typedef
(EFIAPI *EFI_DISK_READ) (
IN EFI_DISK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN UINT64 Offset,
);
This Indicates a pointer to the calling context. Type EFI_DISK_IO_PROTOCOL is deﬁned in the
EFI_DISK_IO_PROTOCOL description.
MediaId ID of the medium to be read.
Offset The starting byte offset on the logical block I/O device to read from.
BufferSize The size in bytes of Buffer. The number of bytes to read from the device.
Buffer A pointer to the destination buffer for the data. The caller is responsible for either having implicit or explicit
ownership of the buffer.
The ReadDisk() function reads the number of bytes speciﬁed by BufferSize from the device. All the bytes are read, or
an error is returned. If there is no medium in the device, the function returns EFI_NO_MEDIA. If the MediaId is not
the ID of the medium currently in the device, the function returns EFI_MEDIA_CHANGED.
EFI_SUCCESS The data was read correctly from the device.
EFI_DEVICE_ERROR The device reported an error while performing the read operation.

);
EFI_NO_MEDIA There is no medium in the device.
EFI_MEDIA_CHANGED The MediaId is not for the current medium.
EFI_INV ALID_PARAMETER The read request contains device addresses that are not valid for the device.
13.7.3 EFI_DISK_IO_PROTOCOL.WriteDisk()
Summary
Writes a speciﬁed number of bytes to a device.
Prototype
typedef
(EFIAPI *EFI_DISK_WRITE) (
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);
EFI_DISK_IO_PROTOCOL protocol description.
MediaId ID of the medium to be written.
Offset The starting byte offset on the logical block I/O device to write.
BufferSize The size in bytes of Buffer. The number of bytes to write to the device.
Buffer A pointer to the buffer containing the data to be written.
The WriteDisk() function writes the number of bytes speciﬁed by BufferSize to the device. All bytes are written, or
EFI_SUCCESS The data was written correctly to the device.
EFI_WRITE_PROTECTED The device cannot be written to.
EFI_DEVICE_ERROR The device reported an error while performing the write operation.
EFI_INV ALID_PARAMETER The write request contains device addresses that are not valid for the device.
13.8 Disk I/O 2 Protocol
The Disk I/O 2 protocol deﬁnes an extension to the Disk I/O protocol to enable non-blocking / asynchronous byte-
oriented disk operation.
13.8.1 EFI_DISK_IO2_PROTOCOL
Summary
This protocol is used to abstract Block I/O interfaces in a non-blocking manner.
GUID
#define EFI_DISK_IO2_PROTOCOL_GUID \
{ 0x151c8eae, 0x7f2c, 0x472c, \
{0x9e, 0x54, 0x98, 0x28, 0x19, 0x4f, 0x6a, 0x88 }}
#define EFI_DISK_IO2_PROTOCOL_REVISION 0x00020000
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typedef struct _EFI_DISK_IO2_PROTOCOL {
EFI_DISK_CANCEL_EX Cancel;
EFI_DISK_READ_EX ReadDiskEx;
EFI_DISK_WRITE_EX WriteDiskEx;
EFI_DISK_FLUSH_EX FlushDiskEx;
} EFI_DISK_IO2_PROTOCOL;
Revision The revision to which the disk I/O interface adheres. All future revisions must be backwards compatible.
Cancel Terminate outstanding requests. See the Cancel() function description.
ReadDiskEx Reads data from the disk. See the ReadDiskEx() function description.
WriteDiskEx Writes data to the disk. See the WriteDiskEx() function description.
FlushDiskEx Flushes all modiﬁed data to the physical device. See the FlushDiskEx() function description.
TheEFI_DISK_IO2_PROTOCOL is used to control block I/O interfaces.
The disk I/O functions allow I/O operations that need not be on the underlying device’s block boundaries or align-
ment requirements. This is done by copying the data to/from internal buffers as needed to provide the proper re-
quests to the block I/O device. Outstanding write buffer data is ﬂushed by using the FlushBlocksEx() function of the
EFI_BLOCK_IO2_PROTOCOL on the device handle.
The ﬁrmware automatically adds an EFI_DISK_IO2_PROTOCOL interface to any EFI_BLOCK_IO2_PROTOCOL
interface that is produced. It also adds ﬁle system, or logical block I/O, interfaces to any EFI_DISK_IO2_PROTOCOL
interface that contains any recognized ﬁle system or logical block I/O devices.
13.8.2 EFI_DISK_IO2_PROTOCOL.Cancel()
Summary
Terminate outstanding asynchronous requests to a device.
Prototype
typedef
(EFIAPI *EFI_DISK_CANCEL_EX) (
IN EFI_DISK_IO2_PROTOCOL *This
);
This Indicates a pointer to the calling context. Type EFI_DISK_IO2_PROTOCOL is deﬁned in the
EFI_DISK_IO2_PROTOCOL description.
TheCancel() function will terminate any in-ﬂight non-blocking I/O requests by signaling the EFI_DISK_IO2_TOKEN
Event and with TransactionStatus set to EFI_ABORTED. After the Cancel() function returns it is safe to free any Token
orBuffer data structures that were allocated as part of the non-blocking I/O operation.
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EFI_SUCCESS All outstanding requests were successfully terminated.
EFI_DEVICE_ERROR The device reported an error while performing the cancel operation.
13.8.3 EFI_DISK_IO2_PROTOCOL.ReadDiskEx()
Summary
Prototype
typedef
(EFIAPI *EFI_DISK_READ_EX) (
IN EFI_DISK_IO2_PROTOCOL *This,
IN OUT EFI_DISK_IO2_TOKEN *Token,
);
Token A pointer to the token associated with the transaction. Type EFI_DISK_IO2_TOKEN is deﬁned in “Related
Deﬁnitions” below. If this ﬁeld is NULL, synchronous/blocking IO is performed.
BufferSize The size in bytes of Buffer . The number of bytes to read from the device.
Buffer A pointer to the destination buffer for the data. The caller is responsible either having implicit or explicit
TheReadDiskEx() function reads the number of bytes speciﬁed by BufferSize from the device. All the bytes are read,
or an error is returned. If there is no medium in the device, the function returns EFI_NO_MEDIA . If the MediaId is
not the ID of the medium currently in the device, the function returns EFI_MEDIA_CHANGED .
If an error is returned from the call to ReadDiskEx() and non-blocking I/O is being requested, the Event associated with
this request will not be signaled. If the call to ReadDiskEx() succeeds then the Event will be signaled upon completion
of the read or if an error occurs during the processing of the request. The status of the read request can be determined
EFI_STATUS TransactionStatus;
} EFI_DISK_IO2_TOKEN;
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then non-blocking I/O is performed, and Event will be signaled when the I/O request is completed. The caller
must be prepared to handle the case where the callback associated with Event occurs before the original asyn-
chronous I/O request call returns.
TransactionStatus Deﬁnes whether or not the signaled event encountered an error.
Returned from the call ReadDiskEx()
If Event is NULL (blocking I/O):
The data was read correctly from the device.
If Event is not NULL (asynchronous I/O):
The request was successfully queued for processing.
Event will be signaled upon completion.
13.8.4 EFI_DISK_IO2_PROTOCOL.WriteDiskEx()
Summary
Prototype
typedef
(EFIAPI *EFI_DISK_WRITE_EX) (
);
Offset The starting byte offset on the logical block I/O device to write to.

Summary
Prototype
typedef
);
BufferSize The size in bytes of Buffer . The number of bytes to write to the device.
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Buffer A pointer to the source buffer for the data. The caller is responsible.
TheWriteDiskEx() function writes the number of bytes speciﬁed by BufferSize to the device. All bytes are written, or
an error is returned. If there is no medium in the device, the function returns EFI_NO_MEDIA . If the MediaId is not
the ID of the medium currently in the device, the function returns EFI_MEDIA_CHANGED .
If an error is returned from the call to WriteDiskEx() and non-blocking I/O is being requested, the Event associated
with this request will not be signaled. If the call to WriteDiskEx() succeeds then the Event will be signaled upon
completion of the write or if an error occurs during the processing of the request. The status of the write request can
be determined from the Status ﬁeld of the Token once the event is signaled.
Returned from the call WriteDiskEx()
• The data was written correctly to the device.
• The request was successfully queued for processing.
EFI_MEDIA_CHANGED TheMediaId is not for the current medium.
13.8.5 EFI_DISK_IO2_PROTOCOL.FlushDiskEx()
Summary
Flushes all modiﬁed data to the physical device.
Prototype
typedef
(EFIAPI *EFI_DISK_FLUSH_EX) (
IN OUT EFI_DISK_IO2_TOKEN *Token
);
Deﬁnitions” below. If this ﬁeld is NULL , synchronous/blocking IO is performed.
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TheFlushDiskEx() function ﬂushes all modiﬁed data to the physical device. If an error is returned from the call to
FlushDiskEx() and non-blocking I/O is being requested, the Event associated with this request will not be signaled. If
the call to FlushDiskEx() succeeds then the Event will be signaled upon completion of the ﬂush or if an error occurs
during the processing of the request. The status of the ﬂush request can be determined from the Status ﬁeld of the
Token once the event is signaled.
Returned from the call FlushDiskEx()
•The data was ﬂushed successfully to the device.
•The request was successfully queued for processing.
The data was ﬂushed successfully to the device.
EFI_DEVICE_ERROR The device reported an error while performing the ﬂush operation.
EFI_MEDIA_CHANGED The medium in the device has changed since the last access.
EFI_INV ALID_PARAMETER Token is NULL.
13.9 Block I/O Protocol
This section deﬁnes the Block I/O protocol. This protocol is used to abstract mass storage devices to allow code
running in the EFI boot services environment to access them without speciﬁc knowledge of the type of device or
controller that manages the device. Functions are deﬁned to read and write data at a block level from mass storage
devices as well as to manage such devices in the EFI boot services environment.
13.9.1 EFI_BLOCK_IO_PROTOCOL
Summary
This protocol provides control over block devices.
GUID
#define EFI_BLOCK_IO_PROTOCOL_GUID \
{0x964e5b21,0x6459,0x11d2,\
#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
#define EFI_BLOCK_IO_PROTOCOL_REVISION3 ((2<<16) | (31))
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typedef struct _EFI_BLOCK_IO_PROTOCOL {
EFI_BLOCK_IO_MEDIA *Media;
EFI_BLOCK_RESET Reset;
EFI_BLOCK_READ ReadBlocks;
EFI_BLOCK_WRITE WriteBlocks;
EFI_BLOCK_FLUSH FlushBlocks;
} EFI _BLOCK_IO_PROTOCOL;
Revision The revision to which the block IO interface adheres. All future revisions must be backwards compatible.
If a future version is not back wards compatible it is not the same GUID.
Media A pointer to the EFI_BLOCK_IO_MEDIA data for this device. Type EFI_BLOCK_IO_MEDIA is deﬁned in
Reset Resets the block device hardware. See the EFI_BLOCK_IO_PROTOCOL.Reset() function description.
ReadBlocks Reads the requested number of blocks from the device. See the
EFI_BLOCK_IO_PROTOCOL.ReadBlocks() function description.
WriteBlocks Writes the requested number of blocks to the device. See the
EFI_BLOCK_IO_PROTOCOL.WriteBlocks() function description.
FlushBlocks Flushes any cache blocks. This function is optional and only needs to be supported on block devices
that cache writes. See the EFI_BLOCK_IO_PROTOCOL.FlushBlocks() function description.
// EFI_BLOCK_IO_MEDIA
UINT32 MediaId;
BOOLEAN RemovableMedia;
BOOLEAN MediaPresent;
BOOLEAN LogicalPartition;
BOOLEAN WriteCaching;
UINT32 IoAlign;
EFI_LBA LastBlock;
EFI_LBA LowestAlignedLba; //added inRevision 2
UINT32 LogicalBlocksPerPhysicalBlock;
//added inRevision 2
UINT32 OptimalTransferLengthGranularity;
// added inRevision 3
} EFI_BLOCK_IO_MEDIA;
// EFI_LBA
typedef UINT64 EFI_LBA;
The following data values in EFI_BLOCK_IO_MEDIA are read-only and are updated by the code that produces the
EFI_BLOCK_IO_PROTOCOL functions:
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MediaId The current media ID. If the media changes, this value is changed.
RemovableMedia TRUE if the media is removable; otherwise, FALSE .
MediaPresent TRUE if there is a media currently present in the device; otherwise, FALSE . This ﬁeld shows the
media present status as of the most recent EFI_BLOCK_IO_PROTOCOL.ReadBlocks() or WriteBlocks() call.
LogicalPartition TRUE if the EFI_BLOCK_IO_PROTOCOL was produced to abstract partition structures on the
disk. FALSE if the BLOCK_IO protocol was produced to abstract the logical blocks on a hardware device.
ReadOnly TRUE if the media is marked read-only otherwise, FALSE . This ﬁeld shows the read-only status as of the
most recent EFI_BLOCK_IO_PROTOCOL.WriteBlocks() call.
WriteCaching TRUE if the WriteBlocks() function caches write data.
BlockSize The intrinsic block size of the device. If the media changes, then this ﬁeld is updated.Returns the number
of bytes per logical block. For ATA devices, this is reported in IDENTIFY DEVICE data words 117-118 (i.e.,
Words per Logical Sector) (see ATA8-ACS). For SCSI devices, this is reported in the READ CAPACITY (16)
parameter data Logical Block Length In Bytes ﬁeld (see SBC-3).
IoAlign Supplies the alignment requirement for any buffer used in a data transfer. IoAlign values of 0 and 1 mean that
the buffer can be placed anywhere in memory. Otherwise, IoAlign must be a power of 2, and the requirement is
that the start address of a buffer must be evenly divisible by IoAlign with no remainder.
LastBlock The last LBA on the device. If the media changes, then this ﬁeld is updated. For ATA devices, this
is reported in IDENTIFY DEVICE data words 60-61 (i.e., Total number of user addressable logical sectors)
(see ATA8-ACS) minus one. For SCSI devices, this is reported in the READ CAPACITY (16) parameter data
Returned Logical Block Address ﬁeld (see SBC-3) minus one.
LowestAlignedLba Only present if EFI_BLOCK_IO_PROTOCOL. Revision is greater than or equal to
EFI_BLOCK_IO_PROTOCOL_REVISION2 . Returns the ﬁrst LBA that is aligned to a physical block boundary
( See GPT overview ). Note that this ﬁeld follows the SCSI deﬁnition, not the ATA deﬁnition. If LogicalPartition
isTRUE this value will be zero.

LogicalBlocksPerPhysicalBlock Only present if EFI_BLOCK_IO_PROTOCOL. Revision is greater than or equal to
EFI_BLOCK_IO_PROTOCOL_REVISION2 . Returns the number of logical blocks per physical block ( See
GPT overview ) . Unlike the ATA and SCSI ﬁelds that provide the information for this ﬁeld, this ﬁeld does not
contain an exponential value. A value of 0 means there is either one logical block per physical block, or there
are more than one physical block per logical block. If LogicalPartition isTRUE this value will be zero.
OptimalTransferLengthGranularity Only present if EFI_BLOCK_IO_PROTOCOL .Revision is greater than or
equal to EFI_BLOCK_IO_PROTOCOL_REVISION3 . Returns the optimal transfer length granularity as a num-
ber of logical blocks ( See GPT overview ). A value of 0 means there is no reported optimal transfer length
granularity. If LogicalPartition isTRUE this value will be zero.
The LogicalPartition is TRUE if the device handle is for a partition. For media that have only one partition, the value
will always be TRUE . For media that have multiple partitions, this value is FALSE for the handle that accesses the
entire device. The ﬁrmware is responsible for adding device handles for each partition on such media.
The ﬁrmware is responsible for adding an EFI_DISK_IO_PROTOCOL interface to every
EFI_BLOCK_IO_PROTOCOL interface in the system. The EFI_DISK_IO_PROTOCOL interface allows byte-
level access to devices.
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13.9.2 EFI_BLOCK_IO_PROTOCOL.Reset()
Summary
Resets the block device hardware.
Prototype
typedef
(EFIAPI *EFI_BLOCK_RESET) (
IN EFI_BLOCK_IO_PROTOCOL *This,
);
This Indicates a pointer to the calling context. Type EFI_BLOCK_IO_PROTOCOL is deﬁned in the
EFI_BLOCK_IO_PROTOCOL description.
The Reset() function resets the block device hardware.
As part of the initialization process, the ﬁrmware/device will make a quick but reasonable attempt to verify that the
device is functioning. If the ExtendedVeriﬁcation ﬂag is TRUE the ﬁrmware may take an extended amount of time to
verify the device is operating on reset. Otherwise the reset operation is to occur as quickly as possible.
EFI_SUCCESS The block device was reset.
EFI_DEVICE_ERROR The block device is not functioning correctly and could not be reset.
13.9.3 EFI_BLOCK_IO_PROTOCOL.ReadBlocks()
Summary
Reads the requested number of blocks from the device.
Prototype
typedef
(EFIAPI *EFI_BLOCK_READ) (
IN EFI_LBA LBA,
);
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MediaId The media ID that the read request is for.
LBA The starting logical block address to read from on the device. Type EFI_LBA is deﬁned in the
BufferSize The size of the Buffer in bytes. This must be a multiple of the intrinsic block size of the device.
The ReadBlocks() function reads the requested number of blocks from the device. All the blocks are read, or an error
If there is no media in the device, the function returns EFI_NO_MEDIA. If the MediaId is not the ID for the current
media in the device, the function returns EFI_MEDIA_CHANGED. The function must return EFI_NO_MEDIA or
EFI_MEDIA_CHANGED even if LBA, BufferSize, orBuffer are invalid so the caller can probe for changes in media
state.
EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation.
EFI_NO_MEDIA There is no media in the device.
EFI_MEDIA_CHANGED The MediaId is not for the current media.
EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic block size of the
device.
EFI_INV ALID_PARAMETER The read request contains LBAs that are not valid, or the buffer is not on
proper alignment.
13.9.4 EFI_BLOCK_IO_PROTOCOL.WriteBlocks()
Summary
Writes a speciﬁed number of blocks to the device.
Prototype
typedef
(EFIAPI *EFI_BLOCK_WRITE) (
);
This Indicates a pointer to the calling context. Type is deﬁned in the See EFI_BLOCK_IO_PROTOCOL description.
MediaId The media ID that the write request is for.
LBA The starting logical block address to be written. The caller is responsible for writing to only legitimate locations.
Type EFI_LBA is deﬁned in the EFI_BLOCK_IO_PROTOCOL description.
BufferSize The size in bytes of Buffer. This must be a multiple of the intrinsic block size of the device.
13.9. Block I/O Protocol 487Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Buffer A pointer to the source buffer for the data.
The WriteBlocks() function writes the requested number of blocks to the device. All blocks are written, or an error is
returned.
state.
EFI_SUCCESS The data were written correctly to the device.
EFI_DEVICE_ERROR The device reported an error while attempting to perform the write opera-
tion.
device.
EFI_INV ALID_PARAMETER The write request contains LBAs that are not valid, or the buffer is not on
13.9.5 EFI_BLOCK_IO_PROTOCOL.FlushBlocks()
Summary
Flushes all modiﬁed data to a physical block device.
Prototype
typedef
(EFIAPI *EFI_BLOCK_FLUSH) (
IN EFI_BLOCK_IO_PROTOCOL *This
);
EFI_BLOCK_IO_PROTOCOL protocol description.
The FlushBlocks() function ﬂushes all modiﬁed data to the physical block device.
All data written to the device prior to the ﬂush must be physically written before returning EFI_SUCCESS from this
function. This would include any cached data the driver may have cached, and cached data the device may have
cached. A ﬂush may cause a read request following the ﬂush to force a device access.
EFI_SUCCESS All outstanding data were written correctly to the device.
EFI_DEVICE_ERROR The device reported an error while attempting to write data.
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13.10 Block I/O 2 Protocol
The Block I/O 2 protocol deﬁnes an extension to the Block I/O protocol which enables the ability to read and write
data at a block level in a non-blocking manner.
13.10.1 EFI_BLOCK_IO2_PROTOCOL
Summary
GUID
#define EFI_BLOCK_IO2_PROTOCOL_GUID \
{0xa77b2472, 0xe282, 0x4e9f, \
{0xa2, 0x45, 0xc2, 0xc0, 0xe2, 0x7b, 0xbc, 0xc1}}
typedef struct _EFI_BLOCK_IO2_PROTOCOL {
EFI_BLOCK_RESET_EX Reset;
EFI_BLOCK_READ_EX ReadBlocksEx;
EFI_BLOCK_WRITE_EX WriteBlocksEx;
EFI_BLOCK_FLUSH_EX FlushBlocksEx;
} EFI_BLOCK_IO2_PROTOCOL;
theEFI_BLOCK_IO_PROTOCOL section.
Reset Resets the block device hardware. See the EFI_BLOCK_IO_PROTOCOL.Reset() function description follow-
ing below.
ReadBlocksEx Reads the requested number of blocks from the device. See the EFI_BLOCK_IO2_PROTOCOL
WriteBlocksEx Writes the requested number of blocks to the device. See the
EFI_BLOCK_IO2_PROTOCOL.WriteBlocksEx() function description.
FlushBlocksEx Flushes any cache blocks. This function is optional and only needs to be supported on block devices
that cache writes. See the EFI_BLOCK_IO2_PROTOCOL.FlushBlocksEx() function description.
13.10.2 EFI_BLOCK_IO2_PROTOCOL.Reset()
Summary
Prototype
typedef

ing below.
Summary
Prototype
typedef
(EFIAPI *EFI_BLOCK_RESET_EX) (
IN EFI_BLOCK_IO2_PROTOCOL *This,
);
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This Indicates a pointer to the calling context. Type EFI_BLOCK_IO2_PROTOCOL is deﬁned in the
EFI_BLOCK_IO2_PROTOCOL description.
TheReset() function resets the block device hardware.
The Reset() function will terminate any in-ﬂight non-blocking I/O requests by signaling an EFI_ABORTED in the
TransactionStatus member of the EFI_BLOCK_IO2_TOKEN for the non-blocking I/O. After the Reset() function
returns it is safe to free any Token orBuffer data structures that were allocated to initiate the non-blocking I/O requests
that were in-ﬂight for this device.
13.10.3 EFI_BLOCK_IO2_PROTOCOL.ReadBlocksEx()
Summary
Prototype
typedef
(EFIAPI *EFI_BLOCK_READ_EX) (
IN OUT EFI_BLOCK_IO2_TOKEN *Token,
);
Token A pointer to the token associated with the transaction. Type EFI_BLOCK_IO2_TOKEN is deﬁned in “Related
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TheReadBlocksEx() function reads the requested number of blocks from the device. All the blocks are read, or an
error is returned.
state.
IfEFI_DEVICE_ERROR, EFI_NO_MEDIA,*_or *EFI_MEDIA_CHANGED is returned and non-blocking I/O is be-
ing used, the Event associated with this request will not be signaled.
} EFI_BLOCK_IO2_TOKEN;
then non-blocking I/O is performed, and Event will be signaled when the read request is completed.
TransactionStatus Deﬁnes whether the signaled event encountered an error.
EFI_SUCCESS The read request was queued if Token-> Event is not NULL . The data was
read correctly from the device if theToken-> Event is NULL .
EFI_MEDIA_CHANGED TheMediaId is not for the current media.
EFI_BAD_BUFFER_SIZE TheBufferSize parameter is not a multiple of the intrinsic block size of the
device.
13.10.4 EFI_BLOCK_IO2_PROTOCOL.WriteBlocksEx()
Summary
Prototype
typedef
(EFIAPI *EFI_BLOCK_WRITE_EX) (
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);
Type EFI_LBA is deﬁned in the EFI_BLOCK_IO2_PROTOCOL description.
Token A pointer to the token associated with the transaction. Type EFI_BLOCK_IO2_TOKEN is deﬁned in
EFI_BLOCK_IO2_PROTOCOL.ReadBlocksEx() “Related Deﬁnitions”.
BufferSize The size in bytes of Buffer . This must be a multiple of the intrinsic block size of the device.
The WriteBlocksEx() function writes the requested number of blocks to the device. All blocks are written, or an error
state.
IfEFI_DEVICE_ERROR, EFI_NO_MEDIA, * _EFI_WRITE_PROTECTED* or EFI_MEDIA_CHANGED is re-
turned and non-blocking I/O is being used, the Event associated with this request will not be signaled.
then non-blocking I/O is performed, and Event will be signaled when the write request is completed.
EFI_SUCCESS The write request was queued if Event is not NULL. The data was written
correctly to the device if the Event is NULL.
tion.
device.
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Table 13.35 – continued from previous page
13.10.5 EFI_BLOCK_IO2_PROTOCOL.FlushBlocksEx()
Summary
Prototype
typedef
(EFIAPI *EFI_BLOCK_FLUSH_EX) (
);
EFI_BLOCK_IO2_PROTOCOL protocol description.
then non-blocking I/O is performed, and Event will be signaled when the ﬂush request is completed.
TheFlushBlocksEx() function ﬂushes all modiﬁed data to the physical block device.
IfEFI_DEVICE_ERROR, EFI_NO_MEDIA, EFI_WRITE_PROTECTED orEFI_MEDIA_CHANGED is returned and
non-blocking I/O is being used, the Event associated with this request will not be signaled.

EFI_SUCCESS The ﬂush request was queued if Event is not NULL . All outstanding data
was written correctly to the device if the Event is NULL .
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Table 13.36 – continued from previous page
13.11 Inline Cryptographic Interface Protocol
13.11.1 EFI_BLOCK_IO_CRYPTO_PROTOCOL
Summary
The UEFI Inline Cryptographic Interface protocol provides services to abstract access to inline cryptographic capabil-
ities.
The usage model of this protocol is similar to the one of the EFI_STORAGE_SECURITY_COMMAND_PROTOCOL
where FDE (Full Disk Encryption) solutions leave ESP partition unprotected (unencrypted) allowing storage clients to
continue using EFI_BLOCK_IO_PROTOCOL orEFI_BLOCK_IO2_PROTOCOL protocol interfaces to load OS boot
components from ESP partition. For other partitions boot apps (including OS boot app) that are enlightened to take
advantage of inline cryptographic capability will be empowered to use this new protocol.
GUID
#define EFI_BLOCK_IO_CRYPTO_PROTOCOL_GUID \
{0xa00490ba,0x3f1a,0x4b4c,\
{0xab,0x90,0x4f,0xa9,0x97,0x26,0xa1,0xe8}}
typedef struct _EFI_BLOCK_IO_CRYPTO_PROTOCOL {
EFI_BLOCK_IO_CRYPTO_RESET Reset;
EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES GetCapabilities;
EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION SetConfiguration;
EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION GetConfiguration;
EFI_BLOCK_IO_CRYPTO_READ_DEVICE_EXTENDED ReadExtended;
EFI_BLOCK_IO_CRYPTO_WRITE_DEVICE_EXTENDED WriteExtended;
EFI_BLOCK_IO_CRYPTO_FLUSH FlushBlocks;
} EFI_BLOCK_IO_CRYPTO_PROTOCOL;
Reset Reset the block device hardware.
GetCapabilities Get the current capabilities of the ICI.
SetConﬁguration Set the conﬁguration for the ICI instance.
GetConﬁguration Get the conﬁguration for the ICI instance.
ReadExtended Provide an extended version of the storage device read command.
WriteExtended Provide an extended version of the storage device write command.
that cache writes.
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Some functions deﬁned for this protocol require the caller to specify the device capabilities, keys and/or attributes of
the keys to be used. These parameters must be consistent with the supported capabilities as reported by the device.
EFI_GUID Algorithm;
UINT64 KeySize;
UINT64 CryptoBlockSizeBitMask;
} EFI_BLOCK_IO_CRYPTO_CAPABILITY;
Algorithm GUID of the algorithm.
KeySize Speciﬁes KeySize in bits used with this Algorithm.
CryptoBlockSizeBitMask Speciﬁes bitmask of block sizes supported by this algorithm. Bit j being set means that
2^j bytes crypto block size is supported.
#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_XTS \
{0x2f87ba6a,\
0x5c04,0x4385,0xa7,0x80,0xf3,0xbf,0x78,0xa9,0x7b,0xec}
EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_XTS GUID represents Inline Cryptographic Interface capability sup-
porting AES XTS crypto algorithm as described in IEEE Std 1619-2007: IEEE Standard for Cryptographic Protection
of Data on Block-Oriented Storage Devices.
EFI_BLOCK_IO_CRYPTO_IV_INPUT Header;
UINT64 CryptoBlockNumber;
UINT64 CryptoBlockByteSize;
} EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_XTS;
EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_XTS structure is used as CryptoIvInput parameter to the ReadExtended
and WriteExtended methods for Inline Cryptographic Interface supporting and using AES XTS algorithm with IV
input as deﬁned for AES XTS algorithm. IO operation (read or write) range should consist of one or more blocks
ofCryptoBlockByteSize size. CryptoBlockNumber is used as the AES XTS IV for the ﬁrst crypto block and is incre-
mented by one for each consecutive crypto block in the IO operation range.
#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_CBC_MICROSOFT_BITLOCKER \
{0x689e4c62,\
0x70bf,0x4cf3,0x88,0xbb,0x33,0xb3,0x18,0x26,0x86,0x70}
EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_CBC_MICROSOFT_BITLOCKER GUID represents Inline Crypto-
graphic Interface capability supporting AES CBC crypto algorithm in the non-diffuser mode as described in following
Microsoft white paper, section 4: See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ ) under the heading
“Inline Cryptographic Interface–Bit Locker Cipher”. It is important to note that when excluding diffuser operations
(A diffuser and B diffuser) described in the above document one should also exclude derivation of sector key and
XOR-ing it with plaintext as that operation is part of the diffuser part of the algorithm and does not belong to the
AES-CBC Microsoft BitLocker algorithm being referred to here.
UINT64 CryptoBlockByteOffset;
} EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_CBC_MICROSOFT_BITLOCKER;
EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_CBC_MICROSOFT_BITLOCKER structure is used to pass as CryptoIv-
Input parameter to the ReadExtended and WriteExtended methods for Inline Cryptographic Interface supporting and
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using AES CBC algorithm with IV input as deﬁned for Microsoft BitLocker Drive Encryption. IO operation (read or
write) range should consist of one or more blocks of CryptoBlockByteSize size. CryptoBlockByteOffset is used as the
AES CBC Microsoft Bitlocker algorithm IV for the ﬁrst crypto block and is incremented by CryptoBlockByteSize for
each consecutive crypto block in the IO operation range.
UINT64 InputSize;
} EFI_BLOCK_IO_CRYPTO_IV_INPUT;
EFI_BLOCK_IO_CRYPTO_IV_INPUT structure is used as a common header in CryptoIvInput parameters passed to
the ReadExtended and WriteExtended methods for Inline Cryptographic Interface. Its purpose is to pass size of the
entire CryptoIvInput parameter memory buffer to the Inline Cryptographic Interface.
Further extensions of crypto algorithm support by Inline Cryptographic Interface should follow the same pattern
established above for the AES XTS and AES CBC Microsoft BitLocker algorithms. In particular each added crypto
algorithm should:
• Deﬁne its crypto algorithm GUID using following pattern:
#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_<algo-name> {<algo-guid>}
• Deﬁne its corresponding CryptoIvInput parameter structure and describe how it is populated for each IO opera-
tion (read / write):
<TBD> <TBD>;
} EFI_BLOCK_IO_CRYPTO_IV_INPUT_<algo-name>;
#define EFI_BLOCK_IO_CRYPTO_INDEX_ANY 0xFFFFFFFFFFFFFFFF
BOOLEAN Supported;
UINT64 KeyCount;
UINT64 CapabilityCount;
EFI_BLOCK_IO_CRYPTO_CAPABILITY Capabilities [1];
} EFI_BLOCK_IO_CRYPTO_CAPABILITIES;
Supported Is inline cryptographic capability supported on this device.
KeyCount Maximum number of keys that can be conﬁgured at the same time.
CapabilityCount Number of supported capabilities.
Capabilities Array of supported capabilities.
UINT64 Index;
EFI_GUID KeyOwnerGuid;
EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability;
VOID *CryptoKey;
} EFI_BLOCK_IO_CRYPTO_CONFIGURATION_TABLE_ENTRY;
Index Conﬁguration table index. A special Index EFI_BLOCK_IO_CRYPTO_INDEX_ANY can be used to set any
available entry in the conﬁguration table.
KeyOwnerGuid Identiﬁes the owner of the conﬁguration table entry. Entry can also be used with the Nil value to
clear key from the conﬁguration table index.
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Capability A supported capability to be used. The CryptoBlockSizeBitMask ﬁeld of the structure should have only
one bit set from the supported mask.
CryptoKey Pointer to the key. The size of the key is deﬁned by the KeySize ﬁeld of the capability speciﬁed by the
Capability parameter.
} EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY;
Index Conﬁguration table index.
KeyOwnerGuid Identiﬁes the current owner of the entry.
Capability The capability to be used. The CryptoBlockSizeBitMask ﬁeld of the structure has only one bit set from
the supported mask.
TheEFI_BLOCK_IO_CRYPTO_PROTOCOL deﬁnes a UEFI protocol that can be used by UEFI drivers and applica-
tions to perform block encryption on a storage device, such as UFS.

The EFI_BLOCK_IO_CRYPTO_PROTOCOL instance will be on the same handle as the device path of the inline
encryption device.
While this protocol is intended to abstract the encryption process for block device access, the protocol user does not
have to be aware of the speciﬁc underlying encryption hardware.
13.11.2 EFI_BLOCK_IO_CRYPTO_PROTOCOL.Reset()
Summary
Prototype
typedef
(EFIAPI *EFI_BLOCK_IO_CRYPTO_RESET) (
IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,
);
This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance.
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EFI_INV ALID_PARAMETER This isNULL .
13.11.3 EFI_BLOCK_IO_CRYPTO_PROTOCOL.GetCapabilities()
Summary
Get the capabilities of the underlying inline cryptographic interface.
Prototype
typedef EFI_STATUS
(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES) (
OUT EFI_BLOCK_IO_CRYPTO_CAPABILITIES *Capabilities
);
Capabilities Pointer to the EFI_BLOCK_IO_CRYPTO_CAPABILITIES structure.
The GetCapabilities() function determines whether pre-OS controllable inline crypto is supported by the system for
the current disk and, if so, returns the capabilities of the crypto engine.
The caller is responsible for providing the Capabilities structure with a sufﬁcient number of entries. If the structure is
too small, the EFI_BUFFER_TOO_SMALL error code is returned and the CapabilityCount ﬁeld contains the number
of entries needed to contain the capabilities.
EFI_SUCCESS The ICI is ready for use.
The Capabilities structure was too small.
The number of entries needed is returned in the CapabilityCount ﬁeld of
the structure.
EFI_NO_RESPONSE No response was received from the ICI
EFI_DEVICE_ERROR An error occurred when attempting to access the ICI
EFI_INV ALID_PARAMETER Capabilities is NULL
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13.11.4 EFI_BLOCK_IO_CRYPTO_PROTOCOL.SetConﬁguration()
Summary
Set the conﬁguration of the underlying inline cryptographic interface.
Prototype
(EFIAPI *EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION) (
IN UINT64 ConfigurationCount,
IN EFI_BLOCK_IO_CRYPTO_CONFIGURATION_TABLE_ENTRY *ConfigurationTable,
OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY
*ResultingTable OPTIONAL
);
ConﬁgurationCount Number of entries being conﬁgured with this call.
ConﬁgurationTable Pointer to a table used to populate the conﬁguration table.
ResultingTable Optional pointer to a table that receives the newly conﬁgured entries.
TheSetConﬁguration() function allows the user to set the current conﬁguration of the inline cryptographic interface
and should be called before attempting any crypto operations.
This conﬁgures the conﬁguration table entries with algorithms, key sizes and keys. Each conﬁgured entry can later be
referred to by index at the time of storage transaction.
The conﬁguration table index will refer to the combination of KeyOwnerGuid, Algorithm, and CryptoKey. Key-
OwnerGuid identiﬁes the component taking ownership of the entry. It helps components to identify their own entries,
cooperate with other owner components, and avoid conﬂicts. This Guid identiﬁer is there to help coordination between
cooperating components and not a security or synchronization feature. The Nil GUID can be used by a component to
release use of entry owned. It is also used to identify potentially available entries (see GetConﬁguration).
CryptoKey speciﬁes algorithm-speciﬁc key material to use within parameters of selected crypto capability.
This function is called infrequently - typically once, on device start, before IO starts. It can be called at
later times in cases the number of keys used on the drive is higher than what can be conﬁgured at a time
or a new key has to be added.
Components setting or changing an entry or entries for a given index or indices must ensure that IO
referencing affected indices is temporarily blocked (run-down) at the time of change.
Indices parameters in each parameter table entry allow to set only a portion of the available table entries
in the crypto module anywhere from single entry to entire table supported.
If corresponding table entry or entries being set are already in use by another owner the call should
be failed and none of the entries should be modiﬁed. The interface implementation must enforce
atomicity of this operation (should either succeed fully or fail completely without modifying state).
Note that components using GetConﬁguration command to discover available entries should be pre-
pared that by the time of calling SetConﬁguration the previously available entry may have become
occupied. Such components should be prepared to re-try the sequence of operations. Alternatively
EFI_BLOCK_IO_CRYPTO_INDEX_ANY can be used to have the implementation discover and allocate
available, if any, indices atomically.
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An optional ResultingTable pointer can be provided by the caller to receive the newly conﬁgured entries.
The array provided by the caller must have at least ConﬁgurationCount of entries.
EFI_INV ALID_PARAMETER This is NULL .
EFI_INV ALID_PARAMETER ConﬁgurationTable isNULL
EFI_INV ALID_PARAMETER ConﬁgurationCount is 0
EFI_OUT_OF_RESOURCES Could not ﬁnd the requested number of available entries in the conﬁguration
table.
13.11.5 EFI_BLOCK_IO_CRYPTO_PROTOCOL.GetConﬁguration()
Summary
Get the conﬁguration of the underlying inline cryptographic interface.
Prototype
(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION) (
IN UINT64 StartIndex,
IN EFI_GUID *KeyOwnerGuid OPTIONAL,
*ConfigurationTable
);
StartIndex Conﬁguration table index at which to start the conﬁguration query.
ConﬁgurationCount Number of entries to return in the response table.
KeyOwnerGuid Optional parameter to ﬁlter response down to entries with a given owner. A pointer to the Nil value
can be used to return available entries. Set to NULL when no owner ﬁltering is required.
ConﬁgurationTable Table of conﬁgured conﬁguration table entries (with no CryptoKey returned): conﬁguration
table index, KeyOwnerGuid, Capability. Should have sufﬁcient space to store up to ConﬁgurationCount entries.
The GetConﬁguration() function allows the user to get the conﬁguration of the inline cryptographic interface.
Retrieves, entirely or partially, the currently conﬁgured key table. Note that the keys themselves are not retrieved, but
rather just indices, owner GUIDs and capabilities.
If fewer entries than speciﬁed by ConﬁgurationCount are returned, the Index ﬁeld of the unused entries is set to
EFI_BLOCK_IO_CRYPTO_INDEX_ANY .
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EFI_INV ALID_PARAMETER This is NULL.
EFI_INV ALID_PARAMETER Conﬁguration table is NULL
EFI_INV ALID_PARAMETER StartIndex is out of bounds
13.11.6 EFI_BLOCK_IO_CRYPTO_PROTOCOL.ReadExtended()
Summary
Reads the requested number of blocks from the device and optionally decrypts them inline.
Prototype
(EFIAPI *EFI_BLOCK_IO_CRYPTO_READ_EXTENDED) (

Summary
Prototype
IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token,
IN UINT64 BufferSize,
OUT VOID *Buffer,
IN UINT64 *Index OPTIONAL,
IN VOID *CryptoIvInput OPTIONAL
);
Token A pointer to the token associated with the transaction. Type EFI_BLOCK_IO_CRYPTO_TOKEN is deﬁned in
Index A pointer to the conﬁguration table index. This is optional.
CryptoIvInput A pointer to a buffer that contains additional cryptographic parameters as required by the capability
referenced by the conﬁguration table index, such as cryptographic initialization vector.
The ReadExtended() function allows the caller to perform a storage device read operation. The function reads the
requested number of blocks from the device and then if Index is speciﬁed decrypts them inline. All the blocks are read
and decrypted (if decryption requested), or an error is returned.
If there is no media in the device, the function returns EFI_NO_MEDIA . If the MediaId is not the ID for the current
media in the device, the function returns EFI_MEDIA_CHANGED .
IfEFI_DEVICE_ERROR, EFI_NO_MEDIA, orEFI_MEDIA_CHANGED is returned and non-blocking I/O is being
used, the Event associated with this request will not be signaled.
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In addition to standard storage transaction parameters (LBA, IO size, and buffer), this command will also specify a
conﬁguration table Index andCryptoIvInput when data has to be decrypted inline by the controller after being read
from the storage device. If an Index parameter is not speciﬁed, no decryption is performed.
} EFI_BLOCK_IO_CRYPTO_TOKEN;
Event IfEvent is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O is supported,
then non- blocking I/O is performed, and Event will be signaled when the read request is completed and data
was decrypted (when Index was speciﬁed).
read correctly from the device if the Token-> Event is NULL .
EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation
and/or decryption operation.
device.
EFI_INV ALID_PARAMETER This isNULL , or the read request contains LBAs that are not valid, or the
buffer is not on proper alignment
EFI_INV ALID_PARAMETER CryptoIvInput is incorrect.
13.11.7 EFI_BLOCK_IO_CRYPTO_PROTOCOL.WriteExtended()
Summary
Optionally encrypts a speciﬁed number of blocks inline and then writes to the device.
Prototype
(EFIAPI *EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED) (
IN UINT64 *Index, OPTIONAL
);
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“Related Deﬁnitions” section for ReadExtended() function above.
TheWriteExtended() function allows the caller to perform a storage device write operation. The function encrypts the
requested number of blocks inline if Index is speciﬁed and then writes them to the device. All the blocks are encrypted
(if encryption requested) and written, or an error is returned.
conﬁguration table Index and a CryptoIvInput when data has to be encrypted inline by the controller before being
written to the storage device. If no Index parameter is speciﬁed, no encryption is performed.
EFI_SUCCESS The request to encrypt (optionally) and write was queued if Event is not
NULL . The data was encrypted (optionally) and written correctly to the
device if the Event is NULL .
EFI_DEVICE_ERROR The device reported an error while attempting to encrypt blocks or to per-
form the write operation.
device.
EFI_INV ALID_PARAMETER This is NULL, or the write request contains LBAs that are not valid, or the
buffer is not on proper alignment.
13.11.8 EFI_BLOCK_IO_CRYPTO_PROTOCOL.FlushBlocks()
Summary
Prototype
(EFIAPI *EFI_BLOCK_IO_CRYPTO_FLUSH) (
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IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token
);
TheFlushBlocks() function ﬂushes all modiﬁed data to the physical block device. Any modiﬁed data that has to be
encrypted must have been already encrypted as a part of WriteExtended() operation - inline crypto operation cannot
be a part of ﬂush operation.
13.12 Erase Block Protocol
13.12.1 EFI_ERASE_BLOCK_PROTOCOL
Summary
This protocol provides the ability for a device to expose erase functionality. This optional protocol is installed on the
same handle as the EFI_BLOCK_IO_PROTOCOL orEFI_BLOCK_IO2_PROTOCOL .
GUID
#define EFI_ERASE_BLOCK_PROTOCOL_GUID \

Summary
GUID
{0x95A9A93E, 0x A86E, 0x4926, \
{0xaa, 0xef, 0x99, 0x18, 0xe7, 0x72, 0xd9, 0x87}}
#define EFI_ERASE_BLOCK_PROTOCOL_REVISION ((2<<16) \(60))
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typedef struct _EFI_ERASE_BLOCK_PROTOCOL {
UINT32 EraseLengthGranularity;
EFI_BLOCK_ERASE EraseBlocks;
} EFI_ERASE_BLOCK_PROTOCOL;
Revision The revision to which the EFI_ERASE_BLOCK_PROTOCOL adheres. All future revisions must be back-
wards compatible. If a future version is not backwards compatible, it is not the same GUID.
EraseLengthGranularity Returns the erase length granularity as a number of logical blocks. A value of 1 means the
erase granularity is one logical block.
EraseBlocks Erase the requested number of blocks from the device. See the EraseBlocks() function description.
13.12.2 EFI_ERASE_BLOCK_PROTOCOL.EraseBlocks()
Summary
Erase a speciﬁed number of device blocks.
Prototype
Typedef
EFI_STATUS *
(EFIAPI *EFI_BLOCK_ERASE)
IN OUT EFI_ERASE_BLOCK_TOKEN *Token,
IN UINTN Size
);
This Indicates a pointer to the calling context. Type is deﬁned in the EFI_ERASE_BLOCK_PROTOCOL description.
MediaId The media ID that the erase request is for.
LBA The starting logical block address to be erased. The caller is responsible for erasing only legitimate locations.
Token A pointer to the token associated with the transaction. Type EFI_ERASE_BLOCK_TOKEN is deﬁned in
Size The size in bytes to be erased. This must be a multiple of the physical block size of the device.
TheEraseBlocks() function erases the requested number of device blocks. Upon the successful execution of Erase-
Blocks() with an EFI_SUCCESS return code, any subsequent reads of the same LBA range would return an initial-
ized/formatted value.
media in the device, the function returns EFI_MEDIA_CHANGED . The function must return EFI_NO_MEDIA or
EFI_MEDIA_CHANGED even if LBA or Size are invalid so the caller can probe for changes in media state.
It is the intention of the EraseBlocks() operation to be at least as performant as writing zeroes to each of the speciﬁed
LBA locations while ensuring the equivalent security.
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On some devices, the granularity of the erasable units is deﬁned by EraseLengthGranularity which is the smallest num-
ber of consecutive blocks which can be addressed for erase. The size of the EraseLengthGranularity is device speciﬁc
and can be obtained from EFI_ERASE_BLOCK_MEDIA structure. The ﬁelds of EFI_ERASE_MEDIA are not the same
asEFI_BLOCK_IO_MEDIA, so look at the EFI_BLOCK_IO_PROTOCOL and/or EFI_BLOCK_IO2_PROTOCOL on
the handle for the complete list of ﬁelds, if needed. For optimal performance, the starting LBA to be erased shall be
EraseLengthGranularity aligned and the Size shall be an integer multiple of an EraseLengthGranularity .
} EFI_ERASE_BLOCK_TOKEN;
Event IfEvent isNULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O is supported,
then non-blocking I/O is performed, and Event will be signaled when the erase request is completed.
EFI_SUCCESS The erase request was queued if Event is not NULL . The data was erased
correctly to the device if the Event isNULL to the device.
EFI_WRITE_PROTECTED The device cannot be erased due to write protection.
EFI_DEVICE_ERROR The device reported an error while attempting to perform the erase opera-
tion.
EFI_INV ALID_PARAMETER The erase request contains LBAs that are not valid.
13.13 ATA Pass Thru Protocol
13.13.1 EFI_ATA_PASS_THRU_PROTOCOL
This section provides a detailed description of the EFI_ATA_PASS_THRU_PROTOCOL .
Summary
Provides services that allow ATA commands to be sent to ATA Devices attached to an ATA controller. Packet-
based commands would be sent to ATAPI devices only through the Extended SCSI Pass Thru Protocol. While
theATA_PASS_THRU interface would expose an interface to the underlying ATA devices on an ATA controller,
EXT_SCSI_PASS_THRU is responsible for exposing a packet-based command interface for the ATAPI devices on
the same ATA controller.
GUID
#define EFI_ATA_PASS_THRU_PROTOCOL_GUID \
{0x1d3de7f0,0x807,0x424f,\
{0xaa,0x69,0x11,0xa5,0x4e,0x19,0xa4,0x6f}}
typedef struct _EFI_ATA_PASS_THRU_PROTOCOL {
EFI_ATA_PASS_THRU_MODE *Mode;
EFI_ATA_PASS_THRU_PASSTHRU PassThru;
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EFI_ATA_PASS_THRU_GET_NEXT_PORT GetNextPort;
EFI_ATA_PASS_THRU_GET_NEXT_DEVICE GetNextDevice;
EFI_ATA_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;
EFI_ATA_PASS_THRU_GET_DEVICE GetDevice;
EFI_ATA_PASS_THRU_RESET_PORT ResetPort;
EFI_ATA_PASS_THRU_RESET_DEVICE ResetDevice;
} EFI_ATA_PASS_THRU_PROTOCOL;
Mode A pointer to the EFI_ATA_PASS_THRU_MODE data for this ATA controller. EFI_ATA_PASS_THRU_MODE
is deﬁned in “Related Deﬁnitions” below.
PassThru Sends an ATA command to an ATA device that is connected to the ATA controller. See the PassThru()
GetNextPort Retrieves the list of legal ports for ATA devices on an ATA controller. See the GetNextPort() function
GetNextDevice Retrieves the list of legal ATA devices on a speciﬁc port of an ATA controller. See the GetNextDe-
vice() function description.
BuildDevicePath Allocates and builds a device path node for an ATA Device on an ATA controller. See the BuildDe-
vicePath() function description.
GetDevice Translates a device path node to a port and port multiplier port. See the GetDevice() function description.
ResetPort Resets an ATA port or channel (PATA). This operation resets all the ATA devices connected to the ATA
port or channel. See the ResetPort() function description.
ResetDevice Resets an ATA device that is connected to the ATA controller. See the ResetDevice() function descrip-
tion.
Note :The following data values in the EFI_ATA_PASS_THRU_MODE interface are read-only .
Attributes Additional information on the attributes of the ATA controller. See “Related Deﬁnitions” below for the
list of possible attributes.
} EFI_ATA_PASS_THRU_MODE;
#define EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001
#define EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002
#define EFI_ATA_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004
EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL If this bit is set, then the
EFI_ATA_PASS_THRU_PROTOCOL interface is for physical devices on the ATA controller.
EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL If this bit is set, then the
EFI_ATA_PASS_THRU_PROTOCOL interface is for logical devices on the ATA controller.
EFI_ATA_PASS_THRU_ATTRIBUTES_NONBLOCKIO If this bit is set, then the
EFI_ATA_PASS_THRU_PROTOCOL interface supports non blocking I/O. Every
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EFI_ATA_PASS_THRU_PROTOCOL must support blocking I/O. The support of non-blocking I/O is
optional.
TheEFI_ATA_PASS_THRU_PROTOCOL provides information about an ATA controller and the ability to send ATA
Command Blocks to any ATA device attached to that ATA controller. To send ATAPI command blocks to ATAPI
device attached to that ATA controller, use the EXT_SCSI_PASS_THRU_PROTOCOL interface.
The ATAPI devices support a small set of the non-packet-based ATA commands. The
EFI_ATA_PASS_THRU_PROTOCOL may be used to send such ATA commands to ATAPI devices.
The printable name for the controller can be provided through the EFI_COMPONENT_NAME2_PROTOCOL for
multiple languages.
The Attributes ﬁeld of the Mode member of the EFI_ATA_PASS_THRU_PROTOCOL interface tells if the inter-
face is for physical ATA devices or logical ATA devices. Drivers for non-RAID ATA controllers will set both the
EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL, and the EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL bits.
Drivers for RAID controllers that allow access to the physical devices and logical de-

optional.
vices will produce two EFI_ATA_PASS_THRU_PROTOCOL interfaces: one with the just
the EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL bit set and another with just the
EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL bit set. One interface can be used to access the physical de-
vices attached to the RAID controller, and the other can be used to access the logical devices attached to the RAID
controller for its current conﬁguration.
Drivers for RAID controllers that do not allow access to the physical devices will produce one
EFI_ATA_PASS_THROUGH_PROTOCOL interface with just the EFI_ATA_PASS_THRU_LOGICAL bit set.
The interface for logical devices can also be used by a ﬁle system driver to mount the RAID vol-
umes. An EFI_ATA_PASS_THRU_PROTOCOL with neither EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL nor
EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal conﬁguration.
The Attributes ﬁeld also contains the EFI_ATA_PASS_THRU_ATTRIBUTES_NONBLOCKIO bit. All
EFI_ATA_PASS_THRU_PROTOCOL interfaces must support blocking I/O. If this bit is set, then the interface sup-
ports both blocking I/O and non-blocking I/O.
Each EFI_ATA_PASS_THRU_PROTOCOL instance must have an associated device path. Typically this will have an
ACPI device path node and a PCI device path node, although variation will exist.
Additional information about the ATA controller can be obtained from protocols attached to the same handle as the
EFI_ATA_PASS_THRU_PROTOCOL, or one of its parent handles. This would include the device I/O abstraction used
to access the internal registers and functions of the ATA controller.
This protocol may also be used for PATA devices (or devices in a PATA-compatible mode). PATA devices are mapped
to ports and port multiplier ports using the following table:
Table 13.45: PATA device mapping to ports and portmultiplier ports
PATA Device Con-
nectionEmulated Port
NumberEmulated Port Multiplier Port Number
Primary Master 0 0
Primary Slave 0 1
Secondary Master 1 0
Secondary Slave 1 1
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13.13.2 EFI_ATA_PASS_THRU_PROTOCOL.PassThru()
Summary
Sends an ATA command to an ATA device that is attached to the ATA controller. This function supports both block-
ing I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking I/O functionality is
optional.
Prototype
typedef
(EFIAPI *EFI_ATA_PASS_THRU_PASSTHRU) (
IN EFI_ATA_PASS_THRU_PROTOCOL *This,
IN UINT16 Port,
IN UINT16 PortMultiplierPort,
IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
);
This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
Port The port number of the ATA device to send the command.
PortMultiplierPort The port multiplier port number of the ATA device to send the command. If there is no port
multiplier, then specify 0xFFFF.
Packet A pointer to the ATA command to send to the ATA device speciﬁed by Port and PortMultiplierPort . See
“Related Deﬁnitions” below for a description of EFI_ATA_PASS_THRU_COMMAND_PACKET .
Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed. If Event isNULL,
then blocking I/O is performed. If Event is not NULL and non blocking I/O is supported, then non-blocking
I/O is performed, and Event will be signaled when the ATA command completes.
EFI_ATA_STATUS_BLOCK *Asb;
EFI_ATA_COMMAND_BLOCK *Acb;
UINT64 Timeout;
VOID *InDataBuffer;
VOID *OutDataBuffer;
UINT32 InTransferLength;
UINT32 OutTransferLength;
EFI_ATA_PASS_THRU_CMD_PROTOCOL Protocol;
EFI_ATA_PASS_THRU_LENGTH Length;
} EFI_ATA_PASS_THRU_COMMAND_PACKET;
Timeout The timeout, in 100 ns units, to use for the execution of this ATA command. A Timeout value of 0 means that
this function will wait indeﬁnitely for the ATA command to execute. If Timeout is greater than zero, then this
function will return EFI_TIMEOUT if the time required to execute the ATA command is greater than Timeout .
InDataBuffer A pointer to the data buffer to transfer between the ATA controller and the ATA device for read and
bidirectional commands. For all write and non data commands where InTransferLength is 0 this ﬁeld is optional
and may be NULL . If this ﬁeld is not NULL, then it must be aligned on the boundary speciﬁed by the IoAlign
ﬁeld in the EFI_ATA_PASS_THRU_MODE structure.
OutDataBuffer A pointer to the data buffer to transfer between the ATA controller and the ATA device for write
or bidirectional commands. For all read and non data commands where OutTransferLength is 0 this ﬁeld is
13.13. ATA Pass Thru Protocol 509Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
optional and may be NULL . If this ﬁeld is not NULL, then it must be aligned on the boundary speciﬁed by the
IoAlign ﬁeld in the EFI_ATA_PASS_THRU_MODE structure.
InTransferLength On input, the size, in bytes, of InDataBuffer . On output, the number of bytes transferred between
the ATA controller and the ATA device. If InTransferLength is larger than the ATA controller can handle, no
data will be transferred, InTransferLength will be updated to contain the number of bytes that the ATA controller
is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.
OutTransferLength On Input, the size, in bytes of OutDataBuffer. On Output, the Number of bytes transferred
between ATA Controller and the ATA device. If OutTransferLength is larger than the ATA controller can handle,
no data will be transferred, OutTransferLength will be updated to contain the number of bytes that the ATA
controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.
Asb A pointer to the sense data that was generated by the execution of the ATA command. It must be aligned to the
boundary speciﬁed in the IoAlign ﬁeld in the EFI_ATA_PASS_THRU_MODE structure.
Acb A pointer to buffer that contains the Command Data Block to send to the ATA device speciﬁed by Port and
PortMultiplierPort .
Protocol Speciﬁes the protocol used when the ATA device executes the command. Type
EFI_ATA_PASS_THRU_CMD_PROTOCOL is deﬁned below.
Length Speciﬁes the way in which the ATA command length is encoded. Type EFI_ATA_PASS_THRU_LENGTH is
typedef struct _EFI_ATA_COMMAND_BLOCK {
UINT8 Reserved1[2];
UINT8 AtaCommand;
UINT8 AtaFeatures;
UINT8 AtaSectorNumber;
UINT8 AtaCylinderLow;
UINT8 AtaCylinderHigh;
UINT8 AtaDeviceHead;
UINT8 AtaSectorNumberExp;
UINT8 AtaCylinderLowExp;
UINT8 AtaCylinderHighExp;
UINT8 AtaFeaturesExp;
UINT8 AtaSectorCount;
UINT8 AtaSectorCountExp;
UINT8 Reserved2 [6];
} EFI_ATA_COMMAND_BLOCK;
typedef struct _EFI_ATA_STATUS_BLOCK {
UINT8 AtaStatus;
UINT8 AtaError;
UINT8 Reserved2;
UINT8 Reserved3[6];
} EFI_ATA_STATUS_BLOCK;
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typedef UINT8 EFI_ATA_PASS_THRU_CMD_PROTOCOL;
#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_HARDWARE_RESET 0x00
#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET 0x01
#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_NON_DATA 0x02
#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_IN 0x04
#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_OUT 0x05
#define EFI_ATA_PASS_THRU_PROTOCOL_DMA 0x06
#define EFI_ATA_PASS_THRU_PROTOCOL_DMA_QUEUED 0x07
#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_DIAGNOSTIC 0x08
#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_RESET 0x09
#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_IN 0x0A
#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_OUT 0x0B
#define EFI_ATA_PASS_THRU_PROTOCOL_FPDMA 0x0C
#define EFI_ATA_PASS_THRU_PROTOCOL_RETURN_RESPONSE 0xFF
typedef UINT8 EFI_ATA_PASS_THRU_LENGTH;
#define EFI_ATA_PASS_THRU_LENGTH_BYTES 0x80
#define EFI_ATA_PASS_THRU_LENGTH_MASK 0x70
#define EFI_ATA_PASS_THRU_LENGTH_NO_DATA_TRANSFER 0x00
#define EFI_ATA_PASS_THRU_LENGTH_FEATURES 0x10
#define EFI_ATA_PASS_THRU_LENGTH_SECTOR_COUNT 0x20
#define EFI_ATA_PASS_THRU_LENGTH_TPSIU 0x30
#define EFI_ATA_PASS_THRU_LENGTH_COUNT 0x0F
ThePassThru() function sends the ATA command speciﬁed by Packet to the ATA device speciﬁed by Port andPort-
MultiplierPort . If the driver supports non-blocking I/O and Event is not NULL, then the driver will return immediately
after the command is sent to the selected device, and will later signal Event when the command has completed.
If the driver supports non-blocking I/O and Event isNULL, then the driver will send the command to the selected
device and block until it is complete. If the driver does not support non-blocking I/O, then the Event parameter is
ignored, and the driver will send the command to the selected device and block until it is complete.

IfPacket is successfully sent to the ATA device, then EFI_SUCCESS is returned. If Packet cannot be sent because
there are too many packets already queued up, then EFI_NOT_READY is returned. The caller may retry Packet at a
later time. If a device error occurs while sending the Packet , then EFI_DEVICE_ERROR is returned. If a timeout
occurs during the execution of Packet, then EFI_TIMEOUT is returned.
IfPort orPortMultiplierPort are not in a valid range for the ATA controller, then EFI_INVALID_PARAMETER is
returned. If InDataBuffer, OutDataBuffer orAsbdo not meet the alignment requirement speciﬁed by the IoAlign ﬁeld
of the E FI_ATA_PASS_THRU_MODE structure, then EFI_INVALID_PARAMETER is returned. If any of the other
ﬁelds of Packet are invalid, then EFI_INVALID_PARAMETER is returned.
If the data buffer described by InDataBuffer andInTransferLength is too big to be transferred in a single command,
then no data is transferred and EFI_BAD_BUFFER_SIZE is returned. The number of bytes that can be transferred in
a single command are returned in InTransferLength . If the data buffer described by OutDataBuffer andOutTransfer-
Length is too big to be transferred in a single command, then no data is transferred and EFI_BAD_BUFFER_SIZE is
returned. The number of bytes that can be transferred in a single command are returned in OutTransferLength .
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If the command described in Packet is not supported by the host adapter, then EFI_UNSUPPORTED is returned.
IfEFI_SUCCESS, EFI_BAD_BUFFER_SIZE, EFI_DEVICE_ERROR, orEFI_TIMEOUT is returned, then the caller
must examine Asb.
If non-blocking I/O is being used, then the status ﬁelds in Packet will not be valid until the Event associated with
Packet is signaled.
IfEFI_NOT_READY, EFI_INVALID_PARAMETER orEFI_UNSUPPORTED is returned, then Packet was never sent,
so the status ﬁelds in Packet are not valid. If non-blocking I/O is being used, the Event associated with Packet will not
be signaled.
This function will determine if data transfer is necessary based on the Acb->Protocol andAcb->Length ﬁelds. The
Acb->AtaCommand ﬁeld is ignored except to copy it into the ATA Command register. The following table describes
special programming considerations based on the protocol speciﬁed by Acb->Protocol .
Table 13.46: Special Programming Considerations
Protocol Value Description
EFI_ATA_PASS_THRU_PROTOCOL_ATA_HARDWARE_RESET For PATA devices, then RST- is asserted. For
SATA devices, then COMRESET will be is-
sued.
EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET A software reset will be issued to the ATA
device.
EFI_AT A_PASS_THRU_PROTOCOL_PIO_DATA_IN -
EFI_ATA_PASS_THRU_PROTOCOL_FPDMAThe command is sent to the ATA device. If
the value is inappropriate for the command
speciﬁed by Acb->AtaCommand, the results
are undeﬁned.
E FI_ATA_PASS_THRU_RETURN_RESPONSE This command will only return the contents
of the ATA status block.
The ATA host and the ATA device should already be conﬁgured for the PIO, DMA, and UDMA transfer rates that are
supported by the ATA controller and the ATA device. The results of changing the device’s timings using this function
IfPacket->Length is not set to EFI_ATA_PASS_THRU_LENGTH_NO_DATA_TRANSFER, then if
EFI_ATA_PASS_THRU_LENGTH_BYTES is set in Packet->Length, then Packet->InTransferLength and Packet-
>OutTransferLength are interpreted as bytes.
EFI_ATA_PASS_THRU_LENGTH_BYTES is clear in Packet->Length, then Packet->InTransferLength andPacket-
>OutTransferLength are interpreted as blocks.
IfPacket->Length is set to EFI_ATA_PASS_THRU_LENGTH_SECTOR_COUNT, then the transfer length will be pro-
grammed into Acb->AtaSectorCount .
IfPacket->Length is set to EFI_ATA_PASS_THRU_LENGTH_TPSIU, then the transfer length will be programmed
into the TPSIU.
• For PIO data transfers, the number of sectors to transfer is 2 (Packet->Length &
EFI_ATA_PASS_THRU_LENGTH_COUNT) .
For all commands, the contents of the ATA status block will be returned in Asb.
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EFI_SUCCESS The ATA command was sent by the host. For bi-directional commands, In-
TransferLength bytes were transferred from InDataBuffer . For write and bi-
directional commands, OutTransferLength bytes were transferred by Out-
DataBuffer . See Asbfor additional status information.
EFI_BAD_BUFFER_SIZE The ATA command was not executed. The number of bytes that could be
transferred is returned in InTransferLength . For write and bi-directional
commands, OutTransferLength bytes were transferred by OutDataBuffer .
SeeAsbfor additional status information.
EFI_NOT_READY The ATA command could not be sent because there are too many ATA com-
mands already queued. The caller may retry again later.
EFI_DEVICE_ERROR A device error occurred while attempting to send the ATA command. See
Asb for additional status information.
EFI_INV ALID_PARAMETER Port, PortMultiplierPort, or the contents of Acbare invalid. The ATA com-
mand was not sent, so no additional status information is available.
EFI_UNSUPPORTED The command described by the ATA command is not supported by the host
adapter. The ATA command was not sent, so no additional status informa-
tion is available.
EFI_TIMEOUT A timeout occurred while waiting for the ATA command to execute. See
Asbfor additional status information.
13.13.3 EFI_ATA_PASS_THRU_PROTOCOL.GetNextPort()
Summary
Used to retrieve the list of legal port numbers for ATA devices on an ATA controller. These can either be the list of
ports where ATA devices are actually present or the list of legal port numbers for the ATA controller. Regardless, the
caller of this function must probe the port number returned to see if an ATA device is actually present at that location
on the ATA controller.
Prototype
typedef
(EFIAPI *EFI_ATA_PASS_THRU_GET_NEXT_PORT) (
IN OUT UINT16 *Port
);
Port On input, a pointer to the port number on the ATA controller. On output, a pointer to the next port number on
the ATA controller. An input value of 0xFFFF retrieves the ﬁrst port number on the ATA controller.
TheGetNextPort() function retrieves the port number on an ATA controller. If on input Port is 0xFFFF , then the port
number of the ﬁrst port on the ATA controller is returned in Port andEFI_SUCCESS is returned.
If Port is the port number that was returned on the previous call to GetNextPort(), then the port number of the next port
on the ATA controller is returned in Port, and EFI_SUCCESS is returned.
IfPort is not 0xFFFF and Port was not returned on the previous call to GetNextPort(), then
EFI_INVALID_PARAMETER is returned.
IfPort is the port number of the last port on the ATA controller, then EFI_NOT_FOUND is returned.
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EFI_SUCCESS The next port number on the ATA controller was returned in Port.
EFI_NOT_FOUND There are no more ports on this ATA controller.
EFI_INV ALID_PARAMETER Port is not 0xFFFF andPort was not returned on a previous call to Get-
NextPort() .
13.13.4 EFI_ATA_PASS_THRU_PROTOCOL.GetNextDevice()
Summary
Used to retrieve the list of legal port multiplier port numbers for ATA devices on a port of an ATA controller. These
can either be the list of port multiplier ports where ATA devices are actually present on port or the list of legal port
multiplier ports on that port. Regardless, the caller of this function must probe the port number and port multiplier
port number returned to see if an ATA device is actually present.
Prototype
typedef
(EFIAPI *EFI_ATA_PASS_THRU_GET_NEXT_DEVICE) (
IN OUT UINT16 *PortMultiplierPort
);
Port The port number present on the ATA controller.
PortMultiplierPort On input, a pointer to the port multiplier port number of an ATA device present on the ATA
controller. If on input a PortMultiplierPort of0xFFFF is speciﬁed, then the port multiplier port number of the
ﬁrst ATA device is returned. On output, a pointer to the port multiplier port number of the next ATA device
present on an ATA controller.
TheGetNextDevice() function retrieves the port multiplier port number of an ATA device present on a port of an ATA
controller.
IfPortMultiplierPort points to a port multiplier port number value that was returned on a previous call to GetNextDe-
vice() , then the port multiplier port number of the next ATA device on the port of the ATA controller is returned in
PortMultiplierPort, andEFI_SUCCESS is returned.

);
IfPortMultiplierPort points to 0xFFFF , then the port multiplier port number of the ﬁrst ATA device on port of the ATA
controller is returned in PortMultiplierPort andEFI_SUCCESS is returned.
IfPortMultiplierPort is not 0xFFFF and the value pointed to by PortMultiplierPort was not returned on a previous
call to GetNextDevice(), then EFI_INVALID_PARAMETER is returned.
IfPortMultiplierPort is the port multiplier port number of the last ATA device on the port of the ATA controller, then
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EFI_SUCCESS The port multiplier port number of the next ATA device on the port of the
ATA controller was returned in PortMultiplierPort .
EFI_NOT_FOUND There are no more ATA devices on this port of the ATA controller.
EFI_INV ALID_PARAMETER PortMultiplierPort is not 0xFFFF , andPortMultiplierPort was not returned
on a previous call to GetNextDevice() .
13.13.5 EFI_ATA_PASS_THRU_PROTOCOL.BuildDevicePath()
Summary
Used to allocate and build a device path node for an ATA device on an ATA controller.
Prototype
typedef
(EFIAPI *EFI_ATA_PASS_THRU_BUILD_DEVICE_PATH) (
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
Port Port speciﬁes the port number of the ATA device for which a device path node is to be allocated and built.
PortMultiplierPort The port multiplier port number of the ATA device for which a device path node is to be allocated
and built. If there is no port multiplier, then specify 0xFFFF.
DevicePath A pointer to a single device path node that describes the ATA device speciﬁed by Port andPortMultipli-
erPort . This function is responsible for allocating the buffer DevicePath with the boot service AllocatePool() . It
is the caller’s responsibility to free DevicePath when the caller is ﬁnished with DevicePath .
The BuildDevicePath() function allocates and builds a single device node for the ATA device spec-
iﬁed by Port andPortMultiplierPort . If the ATA device speciﬁed by Port and PortMultiplierPort is
not present on the ATA controller, then EFI_NOT_FOUND is returned. If DevicePath isNULL, then
EFI_INVALID_PARAMETER is returned. If there are not enough resources to allocate the device path
node, then EFI_OUT_OF_RESOURCES is returned.
Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are
initialized to describe the ATA device speciﬁed by Port andPortMultiplierPort, andEFI_SUCCESS is
returned.
EFI_SUCCESS The device path node that describes the ATA device speciﬁed by Port and
PortMultiplierPort was allocated and returned in DevicePath .
EFI_NOT_FOUND The ATA device speciﬁed by Port andPortMultiplierPort does not exist on
the ATA controller.
EFI_INV ALID_PARAMETER DevicePath isNULL .
EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath .
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13.13.6 EFI_ATA_PASS_THRU_PROTOCOL.GetDevice()
Summary
Used to translate a device path node to a port number and port multiplier port number.
Prototype
typedef
(EFIAPI *EFI_ATA_PASS_THRU_GET_DEVICE) (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT16 *Port,
OUT UINT16 *PortMultiplierPort
);
DevicePath A pointer to the device path node that describes an ATA device on the ATA controller.
Port On return, points to the port number of an ATA device on the ATA controller.
PortMultiplierPort On return, points to the port multiplier port number of an ATA device on the ATA controller.
The GetDevice() function determines the port and port multiplier port number associated with the ATA device de-
scribed by DevicePath . IfDevicePath is a device path node type that the ATA Pass Thru driver supports, then the ATA
Pass Thru driver will attempt to translate the contents DevicePath into a port number and port multiplier port number.
If this translation is successful, then that port number and port multiplier port number are returned in Port andPort-
MultiplierPort, andEFI_SUCCESS is returned.
IfDevicePath, Port, orPortMultiplierPort areNULL, then EFI_INVALID_PARAMETER is returned.
IfDevicePath is not a device path node type that the ATA Pass Thru driver supports, then EFI_UNSUPPORTED is
returned.
IfDevicePath is a device path node type that the ATA Pass Thru driver supports, but there is not a valid translation
from DevicePath to a port number and port multiplier port number, then EFI_NOT_FOUND is returned.
EFI_SUCCESS DevicePath was successfully translated to a port number and port multiplier
port number, and they were returned in Port and PortMultiplierPort .
EFI_INV ALID_PARAMETER Port isNULL
EFI_INV ALID_PARAMETER PortMultiplierPort isNULL
EFI_UNSUPPORTED This driver does not support the device path node type in DevicePath .
EFI_NOT_FOUND A valid translation from DevicePath to a port number and port multiplier
port number does not exist.
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13.13.7 EFI_ATA_PASS_THRU_PROTOCOL.ResetPort()
Summary
Resets a speciﬁc port on the ATA controller. This operation also resets all the ATA devices connected to the port.
Prototype
typedef
(EFIAPI *EFI_ATA_PASS_THRU_RESET_PORT) (
IN UINT16 *Port
);
Port The port number on the ATA controller.
TheResetChannel() function resets an a speciﬁc port on an ATA controller. This operation resets all the ATA devices
connected to that port. If this ATA controller does not support a reset port operation, then EFI_UNSUPPORTED is
returned.
If a device error occurs while executing that port reset operation, then EFI_DEVICE_ERROR is returned.
If a timeout occurs during the execution of the port reset operation, then EFI_TIMEOUT is returned.
If the port reset operation is completed, then EFI_SUCCESS is returned.
EFI_SUCCESS The ATA controller port was reset.
EFI_UNSUPPORTED The ATA controller does not support a port reset operation.
EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA port.
EFI_TIMEOUT A timeout occurred while attempting to reset the ATA port.
13.13.8 EFI_ATA_PASS_THRU_PROTOCOL.ResetDevice()
Summary
Resets an ATA device that is connected to an ATA controller.
Prototype
typedef
(EFIAPI *EFI_ATA_PASS_THRU_RESET_DEVICE) (
IN UINT16 PortMultiplierPort
Port Port represents the port number of the ATA device to be reset.
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PortMultiplierPort The port multiplier port number of the ATA device to reset. If there is no port multiplier, then
specify 0xFFFF.
The ResetDevice() function resets the ATA device speciﬁed by Port andPortMultiplierPort . If this ATA controller
does not support a device reset operation, then EFI_UNSUPPORTED is returned.
IfPort orPortMultiplierPort are not in a valid range for this ATA controller, then EFI_INVALID_PARAMETER is
returned.
If a device error occurs while executing that device reset operation, then EFI_DEVICE_ERROR is returned.
If a timeout occurs during the execution of the device reset operation, then EFI_TIMEOUT is returned.
If the device reset operation is completed, then EFI_SUCCESS is returned.
EFI_SUCCESS The ATA device speciﬁed by Port andPortMultiplierPort was reset
EFI_UNSUPPORTED The ATA controller does not support a device reset operation.
EFI_INV ALID_PARAMETER Port orPortMultiplierPort are invalid.
EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA device speciﬁed
byPort andPortMultiplierPort .
EFI_TIMEOUT A timeout occurred while attempting to reset the ATA device speciﬁed by
Port andPortMultiplierPort .
13.14 Storage Security Command Protocol
This section deﬁnes the storage security command protocol. This protocol is used to abstract mass storage devices to
allow code running in the EFI boot services environment to send security protocol commands to mass storage devices
without speciﬁc knowledge of the type of device or controller that manages the device. Functions are deﬁned to send
or retrieve security protocol deﬁned data to and from mass storage devices. This protocol shall be supported on all

physical and logical storage devices supporting the EFI_BLOCK_IO_PROTOCOL orEFI_BLOCK_IO2_PROTOCOL
in the EFI boot services environment and one of the following command sets (or their alternative) at the bus level:
• TRUSTED SEND/RECEIVE commands of the ATA8-ACS command set or its successor
• SECURITY PROTOCOL IN/OUT commands of the SPC-4 command set or its successor.
If the mass storage device is part of a RAID set, the speciﬁc physical device may not support the block IO protocols
directly, but they are supported by the logical device deﬁning the RAID set. In this case the MediaId parameter may
not be available and its value is undeﬁned for this interface.
13.14.1 EFI_STORAGE_SECURITY_COMMAND_PROTOCOL
Summary
This protocol provides ability to send security protocol commands to mass storage devices.
GUID
#define EFI_STORAGE_SECURITY_COMMAND_PROTOCOL_GUID \
{0xc88b0b6d, 0x0dfc, 0x49a7,\
{0x9c, 0xb4, 0x49, 0x7, 0x4b, 0x4c, 0x3a, 0x78}}
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typedef struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL {
EFI_STORAGE_SECURITY_RECEIVE_DATA ReceiveData;
EFI_STORAGE_SECURITY_SEND_DATA SendData;
} EFI_STORAGE_SECURITY_COMMAND_PROTOCOL;
ReceiveData Issues a security protocol command to the requested device that receives data and/or the result of one
or more commands sent by SendData . See the ReceiveData() function description.
SendData Issues a security protocol command to the requested device. See the SendData() function description.
The EFI_STORAGE_SECURITY_COMMAND_PROTOCOL is used to send security protocol commands to a mass
storage device. Two types of security protocol commands are supported. SendData sends a command with data to a
device. ReceiveData sends a command that receives data and/or the result of one or more commands sent by SendData .
The security protocol command formats supported shall be based on the deﬁnition of the SECURITY PROTOCOL
IN and SECURITY PROTOCOL OUT commands deﬁned in SPC-4. If the device uses the SCSI command set, no
translation is needed in the ﬁrmware and the ﬁrmware can package the parameters into a SECURITY PROTOCOL
IN or SECURITY PROTOCOL OUT command and send the command to the device. If the device uses a non-SCSI
command set, the ﬁrmware shall map the command and data payload to the corresponding command and payload
format deﬁned in the non-SCSI command set (for example, TRUSTED RECEIVE and TRUSTED SEND in ATA8-
ACS).
The ﬁrmware shall automatically add an EFI_STORAGE_SECURITY_COMMAND_PROTOCOL for any storage de-
vices detected during system boot that support SPC-4, ATA8-ACS or their successors.
13.14.2 EFI_STORAGE_SECURITY_COMMAND_PROTOCOL.ReceiveData()
Summary
Send a security protocol command to a device that receives data and/or the result of one or more commands sent by
SendData .
Prototype
typedef
(EFIAPI *EFI_STORAGE_SECURITY_RECEIVE_DATA) (
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL
*This,
IN UINT64 Timeout,
IN UINT8 SecurityProtocol,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN PayloadBufferSize,
OUT VOID *PayloadBuffer,
OUT UINTN *PayloadTransferSize
);
This Indicates a pointer to the calling context. Type EFI_STORAGE_SECURITY_COMMAND_PROTOCOL is de-
ﬁned in the EFI_STORAGE_SECURITY_COMMAND_PROTOCOL description.
MediaId ID of the medium to receive data from. If there is no block IO protocol supported by the physical device,
the value of MediaId is undeﬁned.
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Timeout The timeout, in 100ns units, to use for the execution of the security protocol command. A Timeout value
of 0 means that this function will wait indeﬁnitely for the security protocol command to execute. If Timeout is
greater than zero, then this function will return EFI_TIMEOUT if the time required to execute the receive data
command is greater than Timeout .
SecurityProtocolId The value of the “Security Protocol” parameter of the security protocol command to be sent.
SecurityProtocolSpeciﬁcData The value of the “Security Protocol Speciﬁc” parameter of the security protocol com-
mand to be sent. This value is in big-endian format.
PayloadBufferSize Size in bytes of the payload data buffer.
PayloadBuffer A pointer to a destination buffer to store the security protocol command speciﬁc payload data for
the security protocol command. The caller is responsible for having either implicit or explicit ownership of the
buffer.
PayloadTransferSize A pointer to a buffer to store the size in bytes of the data written to the payload data buffer.
TheReceiveData function sends a security protocol command to the given MediaId . The security protocol command
sent is deﬁned by SecurityProtocolId and contains the security protocol speciﬁc data SecurityProtocolSpeciﬁcData .
The function returns the data from the security protocol command in PayloadBuffer .
For devices supporting the SCSI command set, the security protocol command is sent using the SECURITY PROTO-
COL IN command deﬁned in SPC-4.
For devices supporting the ATA command set, the security protocol command is sent using one of the TRUSTED
RECEIVE commands deﬁned in ATA8-ACS if PayloadBufferSize is non-zero. If the PayloadBufferSize is zero, the
security protocol command is sent using the Trusted Non-Data command deﬁned in ATA8-ACS.
IfPayloadBufferSize is too small to store the available data from the security protocol command, the function shall
copy PayloadBufferSize bytes into the PayloadBuffer and return EFI_WARN_BUFFER_TOO_SMALL .
IfPayloadBuffer orPayloadTransferSize isNULL and PayloadBufferSize is non-zero, the function shall return
EFI_INVALID_PARAMETER .
If the given MediaId does not support security protocol commands, the function shall return EFI_UNSUPPORTED .
If the security protocol fails to complete within the Timeout period, the function shall return EFI_TIMEOUT .
If the security protocol command completes without an error, the function shall return EFI_SUCCESS . If the security
protocol command completes with an error, the function shall return EFI_DEVICE_ERROR .
EFI_SUCCESS The security protocol command completed successfully.
EFI_WARN_BUFFER_TOO_SMALL ThePayloadBufferSize was too small to store the available data from
the device. The PayloadBuffer contains the truncated data.
EFI_UNSUPPORTED The given MediaId does not support security protocol commands.
EFI_DEVICE_ERROR The security protocol command completed with an error.
EFI_INV ALID_PARAMETER The PayloadBuffer orPayloadTransferSize isNULL and Payload-
BufferSize is non-zero.
EFI_TIMEOUT A timeout occurred while waiting for the security protocol command
to execute.
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13.14.3 EFI_STORAGE_SECURITY_COMMAND_PROTOCOL.SendData()
Summary
Send a security protocol command to a device.
Prototype
typedef
(EFIAPI *EFI_STORAGE_SECURITY_SEND_DATA) (
*This,
IN UINT8 SecurityProtocolId,
IN VOID *PayloadBuffer
);
MediaId ID of the medium to send data to. If there is no block IO protocol supported by the physical device, the
value of MediaId is undeﬁned.
mand to be sent.
PayloadBuffer A pointer to a buffer containing the security protocol command speciﬁc payload data for the security
protocol command.
TheSendData function sends a security protocol command containing the payload PayloadBuffer to the given Medi-
aId. The security protocol command sent is deﬁned by SecurityProtocolId and contains the security protocol speciﬁc

data SecurityProtocolSpeciﬁcData . If the underlying protocol command requires a speciﬁc padding for the command
payload, the SendData function shall add padding bytes to the command payload to satisfy the padding requirements.
COL OUT command deﬁned in SPC-4.
SEND commands deﬁned in ATA8-ACS if PayloadBufferSize is non-zero. If the PayloadBufferSize is zero, the security
protocol command is sent using the Trusted Non-Data command deﬁned in ATA8-ACS.
IfPayloadBuffer isNULL andPayloadBufferSize is non-zero, the function shall return EFI_INVALID_PARAMETER .
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EFI_INV ALID_PARAMETER ThePayloadBuffer isNULL andPayloadBufferSize is non-zero.
EFI_TIMEOUT A timeout occurred while waiting for the security protocol command to
execute.
13.15 NVM Express Pass Through Protocol
13.15.1 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL
This section provides a detailed description of the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL .
Summary
This protocol provides services that allow NVM Express commands to be sent to an NVM Express controller or to a
speciﬁc namespace in a NVM Express controller. This protocol interface is optimized for storage.
GUID
#define EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL_GUID \
{ 0x52c78312, 0x8edc, 0x4233,\
{ 0x98, 0xf2, 0x1a, 0x1a, 0xa5, 0xe3, 0x88, 0xa5 } };
typedef struct _EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL {
EFI_NVM_EXPRESS_PASS_THRU_MODE *Mode;
EFI_NVM_EXPRESS_PASS_THRU_PASSTHRU PassThru;
EFI_NVM_EXPRESS_PASS_THRU_GET_NEXT_NAMESPACE GetNextNamespace;
EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;
EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE GetNamespace;
} EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL;
Mode A pointer to the EFI_NVM_EXPRESS_PASS_THRU_MODE data for this NVM Express controller.
EFI_NVM_EXPRESS_PASS_THRU_MODE is deﬁned in “Related Deﬁnitions” below.
PassThru Sends an NVM Express Command Packet to an NVM Express controller. See the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() function description.
GetNextNamespace
Retrieves the next namespace ID for this NVM Express controller. See the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function description.*
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BuildDevicePath Allocates and builds a device path node for a namespace on an NVM Express controller. See the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function description.*
GetNamespace
Translates a device path node to a namespace ID. See the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function description.
The following data values in the EFI_NVM_EXPRESS_PASS_THRU_MODE interface are read-only.
Attributes Additional information on the attributes of the NVM Express controller. See “Related Deﬁnitions” below
for the list of possible attributes.
NvmeVersion Indicates the version of the NVM Express speciﬁcation that the controller implementation supports.
The format of this ﬁeld is deﬁned in the Version ﬁeld of the Controller Registers in the NVM Express Speciﬁca-
tion.
UINT32 NvmeVersion;
} EFI_NVM_EXPRESS_PASS_THRU_MODE;
#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001
#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002
#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004
#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM 0x0008
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL If this bit is set, then the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface is for directly addressable namespaces.
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL If this bit is set, then the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface is for a single volume logical namespace
comprised of multiple namespaces.
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO If this bit is set, then the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface supports non-blocking I/O.
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM If this bit is set, then the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface supports NVM command set.
TheEFI_NVM_EXPRESS_PASS_THRU_PROTOCOL provides information about an NVM Express controller and the
ability to send NVM Express commands to an NVM Express controller or to a speciﬁc namespace in a NVM Express
• The printable name for the NVM Express controller can be provided through the*
EFI_COMPONENT_NAME_PROTOCOL and the EFI_COMPONENT_NAME2_PROTOCOL for multi-
ple languages.
The Attributes ﬁeld of the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface tells if the interface is
for physical NVM Express controllers or logical NVM Express controllers. Drivers for non-RAID NVM
Express controllers will set both the EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL, and the
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL bits.
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Drivers for RAID controllers that allow access to the physical controllers and logical controllers
will produce two EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interfaces: one with the just
the EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL bit set and another with just the
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL bit set. One interface can be used to access the
physical controllers attached to the RAID controller, and the other can be used to access the logical controllers
attached to the RAID controller for its current conﬁguration.
Drivers for RAID controllers that do not allow access to the physical controllers will
produce one EFI_NVM_EXPRESS_PASS_THROUGH_PROTOCOL interface with just the
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL bit set. The interface for logical controllers can also
be used by a ﬁle system driver to mount the RAID volumes. An EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL
with neither EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL norEFI_NVM_EXPRESS_PASS_THRU
_ATTRIBUTES_PHYSICAL set is an illegal conﬁguration.
The Attributes ﬁeld also contains the EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO bit. All
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interfaces must support blocking I/O. If this bit is set, then the in-
terface supports both blocking I/O and non-blocking I/O.
TheAttributes ﬁeld also contains the EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM bit. If this
bit is set, the controller supports the NVM Express command set.
• Each EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance must have an associated device path. Typically
this will have an ACPI device path node and a PCI device path node, although variation will exist.
13.15.2 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru()
Summary
Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports both
blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking I/O functionality
is optional.
Prototype
(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_PASSTHRU) (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
);
This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance. Type
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL is deﬁned in See NVM Express Pass Through Protocol ,
above.
NamespaceId A 32 bit namespace ID as deﬁned in the NVM Express® Base Speciﬁcation to which the NVM Express

Summary
Prototype
);
above.
Command Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF ’s (all
bytes are 0xFF ) in the namespace ID speciﬁes that the command packet should be sent to all valid namespaces.
Packet A pointer to the NVM Express Command Packet. See “Related Deﬁnitions” below for a description of
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET .
Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed. If Event is NULL,
then blocking I/O is performed. If Event is not NULL and non-blocking I/O is supported, then non-blocking I/O
is performed, and Event will be signaled when the NVM Express Command Packet completes.
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UINT64 CommandTimeout;
VOID TransferBuffer OPTIONAL;
UINT32 TransferLength OPTIONAL;
VOID *MetaDataBuffer OPTIONAL;
UINT32 MetadataLength OPTIONAL;
UINT8 QueueType;
EFI_NVM_EXPRESS_COMMAND *NvmeCmd;
EFI_NVM_EXPRESS_COMPLETION *NvmeCompletion;
} EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET;
CommandTimeout The timeout in 100 ns units to use for the execution of this NVM Express Command Packet.
ATimeout value of 0 means that this function will wait indeﬁnitely for the command to execute. If Timeout is
greater than zero, then this function will return EFI_TIMEOUT if the time required to execute the NVM Express
TransferBuffer A pointer to the data buffer to transfer between the host and the NVM Express controller for read,
write, and bi-directional commands. For all write and non-data commands where TransferLength is 0 this ﬁeld
is optional and may be NULL. If this ﬁeld is not NULL, then it must be aligned on the boundary speciﬁed by
theIoAlign ﬁeld in the EFI_NVM_EXPRESS_PASS_THRU_MODE structure.
TransferLength On input, the size in bytes of TransferBuffer*. On output, the number of bytes transferred to or from
the NVM Express controller or namespace.
MetadataBuffer A pointer to the optional metadata buffer to transfer between the host and the NVM Express con-
troller. For all commands where no metadata is transferred between the host and the controller, this ﬁeld is
optional and may be NULL. If this ﬁeld is not NULL, then it must be aligned on the boundary speciﬁed by the
IoAlign ﬁeld in the EFI_NVM_EXPRESS_PASS_THRU_MODE structure.
MetadataLength On input, the size in bytes of MetadataBuffer . On output, the number of bytes transferred to or
from the NVM Express controller or namespace.
QueueType The type of the queue that the NVMe command should be posted to. A value of 0 indicates it should be
posted to the Admin Submission Queue. A value of 1 indicates it should be posted to an I/O Submission Queue.
NvmeCmd A pointer to an NVM Express Command Packet.
NvmeCompletion The raw NVM Express completion queue entry as deﬁned in the NVM Express® Base Speciﬁca-
tion.
The PassThru() function sends the NVM Express Command Packet speciﬁed by Packet to the NVM Express controller.
If the driver supports non-blocking I/O and Event is not NULL, then the driver will return immediately after the
command is sent to the selected controller, and will later signal Event when the command has completed.
If the driver supports non-blocking I/O and Event i s NULL, then the driver will send the command to the selected
device and block until it is complete.
If the driver does not support non-blocking I/O, then the Event parameter is ignored, and the driver will send the
command to the selected device and block until it is complete.
IfPacket is successfully sent to the NVM Express controller, then EFI_SUCCESS is returned.
If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
If a timeout occurs during the execution of Packet, then EFI_TIMEOUT is returned.
IfNamespaceId is invalid for the NVM Express controller, then EFI_INVALID_PARAMETER is returned.
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IfTransferBuffer or MetadataBuffer do not meet the alignment requirement speciﬁed by the IoAlign ﬁeld of the
EFI_NVM_EXPRESS_PASS_THRU_MODE structure, then EFI_INVALID_PARAMETER is returned. If the Queue-
Type is not 0 (Admin Submission Queue) or 1 (I/O Submission Queue), then EFI_INVALID_PARAMETER is returned.
If any of the other ﬁelds of Packet are invalid, then EFI_INVALID_PARAMETER is returned.
If the data buffer described by TransferBuffer and TransferLength is too big to be transferred in a single command,
a single command are returned in TransferLength .
IfEFI_SUCCESS ,EFI_DEVICE_ERROR, orEFI_TIMEOUT is returned, then the caller must examine the Nvme-
Completion ﬁeld in Packet .
If non-blocking I/O is being used, then the NvmeCompletion ﬁeld in Packet will not be valid until the Event associated
with Packet is signaled.
IfEFI_NOT_READY, EFI_INVALID_PARAMETER, EFI_BAD_BUFFER_SIZE, or EFI_UNSUPPORTED is re-
turned, then Packet was never sent, so the NvmeCompletion ﬁeld in Packet is not valid. If non-blocking I/O is being
used, the Event associated with Packet will not be signaled.
EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength
bytes were transferred to or from TransferBuffer . See NvmeCompletion
(above) for additional status information.
EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of
bytes that could be transferred is returned in TransferLength .
EFI_NOT_READY The NVM Express Command Packet could not be sent because the con-
troller is not ready. The caller may retry again later.
EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Com-
mand Packet. See NvmeCompletion (above) for additional status informa-
tion.
EFI_INV ALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU
_COMMAND_PACKET are invalid. The NVM Express Command Packet
was not sent, so no additional status information is available.
EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not
supported by the NVM Express controller. The NVM Express Command
Packet was not sent so no additional status information is available.
EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet
to execute. See NvmeCompletion (above) for additional status information.
UINT32 OpCode: 8;
UINT32 FusedOperation: 2;
UINT32 Reserved : 22;
} NVME_CDW0;
// FusedOperation *
#define NORMAL_CMD 0x00
#define FUSED_FIRST_CMD 0x01
#define FUSED_SECOND_CMD 0x02
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NVME_CDW0 Cdw0;
UINT8 Flags;
UINT32 Nsid;
UINT32 Cdw2;
UINT32 Cdw3;
UINT32 Cdw10;
UINT32 Cdw11;
UINT32 Cdw12;
UINT32 Cdw13;
UINT32 Cdw14;
UINT32 Cdw15;
} EFI_NVM_EXPRESS_COMMAND;
// Flags
#define CDW2_VALID 0x01
#define CDW3_VALID 0x02
#define CDW10_VALID 0x04
#define CDW11_VALID 0x08
#define CDW12_VALID 0x10
#define CDW13_VALID 0x20
#define CDW14_VALID 0x40
#define CDW15_VALID 0x80
//
// This structure maps to the NVM Express specification Completion Queue Entry
//
UINT32 DW0;
UINT32 DW1;
UINT32 DW2;
UINT32 DW3;
} EFI_NVM_EXPRESS_COMPLETION;
13.15.3 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace()
Summary
Used to retrieve the next namespace ID for this NVM Express controller.
Prototype
typedef
(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_GET_NEXT_NAMESPACE) (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN OUT UINT32 *NamespaceId
);
This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
NamespaceId On input, a pointer to a valid namespace ID onthis NVM Express controller or a pointer to the
value*0xFFFFFFFF*. A pointer to the value 0xFFFFFFFF retrievesthe ﬁrst valid namespace ID on this NVM
Express controller.
13.15. NVM Express Pass Through Protocol 527Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheEFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid names-
pace ID on this NVMExpress controller. If on input the value pointed to by NamespaceId is0xFFFFFFFF , then the
ﬁrst valid namespaceID deﬁned on the NVM Express controller is returned in thelocation pointed to by NamespaceId
and a status of*EFI_SUCCESS* is returned.
If on input the value pointed to by NamespaceId is an invalidnamespace ID other than 0xFFFFFFFF , then

);
If on input the value pointed to by NamespaceId is a validnamespace ID, then the next valid namespace ID on the
NVMExpress controller is returned in the location pointed to byNamespaceId, and EFI_SUCCESS is returned.
If the value pointed to by NamespaceId is the namespace ID ofthe last namespace on the NVM Express controller,
then EFI_NOT_FOUND is returned.
EFI_SUCCESS The Namespace ID of the next Namespace was returned.
EFI_NOT_FOUND There are no more namespaces deﬁned on this controller.
EFI_INV ALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF .
13.15.4 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath()
Summary
Used to allocate and build a device path node for an NVMExpress namespace on an NVM Express controller.
Prototype
typedef
(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH) (
);
This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL*instance. Type
*EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL is deﬁned in NVM Express Pass Through Protocol .
NamespaceId The NVM Express namespace ID for which a devicepath node is to be allocated and built.
DevicePath A pointer to a single device path node thatdescribes the NVM Express namespace speciﬁed by Names-
paceId . This function is responsible for allocating the buffer*DevicePath* with the boot service AllocatePool() .
It is thecaller’s responsibility to free DevicePath when the caller isﬁnished with DevicePath .
The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single de-
vice path node for the NVM Express namespace speciﬁed by NamespaceId . If the NamespaceId is not valid, then
EFI_NOT_FOUND is returned. If DevicePath isNULL , then EFI_INVALID_PARAMETER is returned. If there are
not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned. Otherwise, De-
vicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are initialized to describe the
NVM Express namespace speciﬁed by NamespaceId, andEFI_SUCCESS is returned.
13.15. NVM Express Pass Through Protocol 528Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The device path node that describes the NVM Express namespace speciﬁed
byNamespaceId was allocated and returned in DevicePath
EFI_NOT_FOUND TheNamespaceId is not valid.
EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.
13.15.5 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace()
Summary
Used to translate a device path node to a namespace ID.
Prototype
typedef
(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE) (
OUT UINT32 *NamespaceId
);
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL is deﬁned in NVM Express Pass Through Protocol .
DevicePath A pointer to the device path node that describesan NVM Express namespace on the NVM Express con-
troller.
NamespaceId The NVM Express namespace ID contained in thedevice path node.
TheEFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID asso-
ciated with thenamespace described by DevicePath . If DevicePath is a device path node type that the NVM Ex-
press Pass Thru driversupports, then the NVM Express Pass Thru driver will attempt totranslate the contents Devi-
cePath into a namespace ID. If this translation is successful, then that namespace ID is returned in NamespaceId, and
EFI_SUCCESS is returned.
EFI_INV ALID_PARAMETER If DevicePath or NamespaceId are NULL, then
EFI_UNSUPPORTED IfDevicePath is not a device path node type that the NVM Express Pass
Thru driver supports, then EFI_UNSUPPORTED is returned.
EFI_NOT_FOUND IfDevicePath is a device path node type that the NVM Express Pass Thru
driver supports, but there is not a valid translation from DevicePath to a
namespace ID, then EFI_NOT_FOUND is returned.
13.15. NVM Express Pass Through Protocol 529Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
13.16 SD MMC Pass Thru Protocol
13.16.1 EFI_SD_MMC_PASS_THRU_PROTOCOL
This section provides a detailed description of the EFI_SD_MMC_PASS_THRU_PROTOCOL .
The protocol provides services that allow SD/eMMC commands to be sent to an SD/eMMC controller. All interfaces
anddeﬁnitions from this section apply equally to SD and eMMCcontrollers.
For the sake of brevity, the rest of this section refers only to SD devices and controllers and does not speciﬁcally
mentioneMMC devices and controllers.
GUID
#define EFI_SD_MMC_PASS_THRU_PROTOCOL_GUID \
{ 0x716ef0d9, 0xff83, 0x4f69, \
{ 0x81, 0xe9, 0x51, 0x8b, 0xd3, 0x9a, 0x8e, 0x70 } }
typedef struct _EFI_SD_MMC_PASS_THRU_PROTOCOL {
UINTN IoAlign
EFI_SD_MMC_PASS_THRU_PASSTHRU PassThru;
EFI_SD_MMC_PASS_THRU_GET_NEXT_SLOT GetNextSlot;
EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;
EFI_SD_MMC_PASS_THRU_GET_SLOT_NUMBER GetSlotNumber;
EFI_SD_MMC_PASS_THRU_RESET_DEVICE ResetDevice;
} EFI_SD_MMC_PASS_THRU_PROTOCOL;
PassThru Sends SD command to the SD controller. See the PassThru() function description.
GetNextSlot Retrieves a next slot on an SD controller. Seethe GetNextSlot() function description.
BuildDevicePath Allocates and builds a device path nodefor an SD card on the SD controller. See the BuildDevi-
cePath() function description.
GetSlotNumber Retrieves the SD card slot number based onthe input device path. See the GetSlotNumber() function
ResetDevice Resets an SD card connected to the SDcontroller. See the ResetDevice() function description.
13.16.2 EFI_SD_MMC_PASS_THRU_PROTOCOL.PassThru()
Summary
Sends SD command to an SD card that is attached to the SD controller.
Prototype
typedef
(EFIAPI *EFI_SD_MMC_PASS_THRU_PASSTHRU) (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
13.16. SD MMC Pass Thru Protocol 530Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN UINT8 Slot,
IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
);
This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
Slot The slot number of the SD card to send the command to.
Packet A pointer to the SD command data structure. See “Related Deﬁnitions” below for a description of
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET .
Event If non-blockingI/O is not supported then Event is ignored, and blocking I/O is performed. If Event isNULL,
then blockingI/O is performed. If Event is not NULL and non-blockingI/O is supported, then non-blockingI/O
is performed, and Event will be signaled when the SDcommand completes
EFI_SD_MMC_COMMAND_BLOCK *SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK *SdMmcStatusBlk;
UINT64 Timeout
} EFI_SD_MMC_PASS_THRU_COMMAND_PACKET;
SdMmcCmdBlk A pointer to a command speciﬁc data buffer allocated and ﬁlled by the caller. See “Related Deﬁni-
tions” below for a description of EFI_SD_MMC_COMMAND_BLOCK .
SdMmcStatusBlk A pointer to a command speciﬁc response data buffer allocated by the caller and ﬁlled by the
PassThru function. See “Related Deﬁnitions” below for a description of EFI_SD_MMC_STATUS_BLOCK .
Timeout The timeout, in 100 ns units, to use for the execution of this SDcommand. A Timeout value of 0 means
that this function will wait indeﬁnitely for the SDcommand to execute. If Timeout is greater than zero, then this
function will return EFI_TIMEOUT if the time required to execute the SDcommand is greater than Timeout .
InDataBuffer A pointer to a buffer for the data transferred from the SD card during processing of read and bidirec-
tional commands. For all write and non-data commands this ﬁeld is optional and may be NULL .
OutDataBuffer A pointer to a buffer for the data to be transferred to the SD card during processing of write or
bidirectional commands. For all read and non-data commands this ﬁeld is optional and may be NULL .
the SD controller and the SD device. If InTransferLength is larger than the SD controller can handle, no data

will be transferred, InTransferLength will be updated to contain the number of bytes that the SD controller is
able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.
OutTransferLength On Input, the size, in bytes of OutDataBuffer . On Output, the Number of bytes transferred
between SD Controller and the SD device. If OutTransferLength is larger than the SD controller can handle, no
data will be transferred. OutTransferLength will be updated to contain the number of bytes that the SD controller
TransactionStatus Transaction status. When PathThru() function is used in a blocking mode, the status must be the
same as the status returned by the PathThru() function. When PathThru() function is used in a non-blocking
mode, the ﬁeld is updated with the transaction status once transaction is completed.
13.16. SD MMC Pass Thru Protocol 531Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UNIT16 CommandIndex;
UINT32 CommandArgument;
UINT32 CommandType; // One of the EFI_SD_MMC_COMMAND_TYPE values
UINT32 ResponseType; // One of the EFI_SD_MMC_RESPONSE_TYPE values
} EFI_SD_MMC_COMMAND_BLOCK;
UINT32 Resp0;
UINT32 Resp1;
UINT32 Resp2;
UINT32 Resp3;
} EFI_SD_MMC_STATUS_BLOCK;
SdMmcCommandTypeBc, // Broadcast commands, no response
SdMmcCommandTypeBcr, // Broadcast commands withresponse
SdMmcCommandTypeAc, // Addressed(point-to-point) commands
SdMmcCommandTypeAdtc // Addressed(point-to-point) data transfer
// commands
} EFI_SD_MMC_COMMAND_TYPE;
SdMmcResponceTypeR1,
SdMmcResponceTypeR1b,
SdMmcResponceTypeR2,
SdMmcResponceTypeR3,
SdMmcResponceTypeR4,
SdMmcResponceTypeR5,
SdMmcResponceTypeR5b,
SdMmcResponceTypeR6,
SdMmcResponceTypeR7
} EFI_SD_MMC_RESPONSE_TYPE;
ThePassThru() function sends the SD command speciﬁed by Packet to the SD card speciﬁed by Slot.
IfPacket is successfully sent to the SD card, then EFI_SUCCESS is returned. If a device error occurs while send-
ing the Packet, then EFI_DEVICE_ERROR is returned. If Slot is not in a valid range for the SD controller, then
EFI_INVALID_PARAMETER is returned. If Packet deﬁnes a data command but both InDataBuffer andOutDataBuffer
areNULL ,EFI_INVALID_PARAMETER is returned.
EFI_SUCCESS The SD Command Packet was sent by the host.
EFI_DEVICE_ERROR A device error occurred while attempting to send the SD command Packet.
EFI_INV ALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
EFI_INV ALID_PARAMETER Packet deﬁnes a data command but both InDataBuffer andOutDataBuffer
areNULL .
EFI_NO_MEDIA SD Device not present in the Slot.
EFI_UNSUPPORTED The command described by the SD Command Packet is not supported by
the host controller.
EFI_BAD_BUFFER_SIZE TheInTransferLength orOutTransferLength exceeds the limit supported by
SD card (i.e. if the number of bytes exceed the Last LBA).
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Table 13.60 – continued from previous page
EFI_DEVICE_ERROR The command was not sent due to a device error
13.16.3 EFI_SD_MMC_PASS_THRU_PROTOCOL.GetNextSlot()
Summary
Used to retrieve next slot numbers supported by the SD controller. The function returns information about all available
slots (populated or not-populated).
Prototype
typedef
(EFIAPI *EFI_SD_MMC_PASS_THRU_GET_NEXT_SLOT) (
IN OUT UINT8 *Slot
);
This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
Slot On input, a pointer to a slot number on the SD controller. On output, a pointer to the next slot number on the SD
controller. An input value of 0xFF retrieves the ﬁrst slot number on the SD controller.
TheGetNextSlot() function retrieves the next slot number on an SD controller. If on input Slotis0xFF , then the slot
number of the ﬁrst slot on the SD controller is returned.
IfSlotis a slot number that was returned on a previous call to GetNextSlot(), then the slot number of the next slot on
the SD controller is returned.
IfSlot is not 0xFF andSlot was not returned on a previous call to GetNextSlot(), EFI_INVALID_PARAMETER is
returned.
IfSlotis the slot number of the last slot on the SD controller, then EFI_NOT_FOUND is returned.
EFI_SUCCESS The next slot number on the SD controller was returned in Slot.
EFI_NOT_FOUND There are no more slots on this SD controller
EFI_INV ALID_PARAMETER Slot is not 0xFF and Slot was not returned on a previous call to Get-
NextSlot() .
13.16.4 EFI_SD_MMC_PASS_THRU_PROTOCOL.BuildDevicePath()
Summary
Used to allocate and build a device path node for an SD card on the SD controller.
Prototype
typedef
(EFIAPI *EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH) (
13.16. SD MMC Pass Thru Protocol 533Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
Slot Speciﬁes the slot number of the SD card for which a device path node is to be allocated and built.
DevicePath A pointer to a single device path node that describes the SD card speciﬁed by Slot. This function is
responsible for allocating the buffer DevicePath with the boot service AllocatePool() . It is the caller’s responsi-
bility to free DevicePath when the caller is ﬁnished with DevicePath .
TheBuildDevicePath() function allocates and builds a single device node for the SD card speciﬁed by Slot. If the SD
card speciﬁed by Slotis not present on the SD controller, then EFI_NOT_FOUND is returned. If DevicePath is NULL,
then EFI_INVALID_PARAMETER is returned. If there are not enough resources to allocate the device path node, then
EFI_OUT_OF_RESOURCES is returned.
Otherwise, DevicePath is allocated with the boot service AllocatePool() , the contents of DevicePath are initialized to
describe the SD card speciﬁed by Slot, and EFI_SUCCESS is returned.
EFI_SUCCESS The device path node that describes the SD card speciﬁed by Slot was allo-
cated and returned in DevicePath.
EFI_NOT_FOUND The SD card speciﬁed by Slot does not exist on the SD controller
EFI_INV ALID_PARAMETER DevicePath is NULL
EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath
13.16.5 EFI_SD_MMC_PASS_THRU_PROTOCOL.GetSlotNumber()
Summary
This function retrieves an SD card slot number based on the input device path.
Prototype
typedef
(EFIAPI *EFI_SD_MMC_PASS_THRU_GET_SLOT_NUMBER) (
OUT UINT8 *Slot
);
DevicePath A pointer to the device path node that describes a SD card on the SD controller.
Slot On return, points to the slot number of an SD card on the SD controller.
13.16. SD MMC Pass Thru Protocol 534Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheGetSlotNumber() function retrieves slot number for the SD card speciﬁed by the DevicePath node. If DevicePath
is NULL, EFI_INVALID_PARAMETER is returned. If DevicePath is not a device path node type that the SD Pass
Thru driver supports, EFI_UNSUPPORTED is returned.
EFI_SUCCESS SD card slot number is returned in Slot.
EFI_INV ALID_PARAMETER Slot or DevicePath is NULL.
EFI_UNSUPPORTED DevicePath is not a device path node type that the SD Pass Thru driver
supports.
13.16.6 EFI_SD_MMC_PASS_THRU_PROTOCOL.ResetDevice()
Summary
Resets an SD card that is connected to the SD controller.
Prototype
typedef
(EFIAPI *EFI_SD_MMC_PASS_THRU_RESET_DEVICE) (
IN UINT8 Slot
);
Slot Speciﬁes the slot number of the SD card to be reset.
The ResetDevice() function resets the SD card speciﬁed by Slot. If this SD controller does not support a device
reset operation, EFI_UNSUPPORTED is returned. If Slot is not in a valid slot number for this SD controller,
If the device reset operation is completed, EFI_SUCCESS is returned.
EFI_SUCCESS The SD card speciﬁed by Slot was reset.
EFI_UNSUPPORTED The SD controller does not support a device reset operation.
EFI_INV ALID_PARAMETER Slot number is invalid.
EFI_DEVICE_ERROR The reset command failed due to a device error
13.16. SD MMC Pass Thru Protocol 535Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
13.17 RAM Disk Protocol
13.17.1 EFI_RAM_DISK_PROTOCOL
Summary
RAM disk aware application invokes this protocol to register/unregister a speciﬁed RAM disk.
GUID

Summary
GUID
#define EFI_RAM_DISK_PROTOCOL_GUID \
{ 0xab38a0df, 0x6873, 0x44a9, \
{ 0x87, 0xe6, 0xd4, 0xeb, 0x56, 0x14, 0x84, 0x49 }}
typedef struct _EFI_RAM_DISK_PROTOCOL {
EFI_RAM_DISK_REGISTER_RAMDISK Register;
EFI_RAM_DISK_UNREGISTER_RAMDISK Unregister;
} EFI_RAM_DISK_PROTOCOL;
Members
Register Register a RAM disk with speciﬁed buffer address, size and type.
Unregister Unregister the RAM disk speciﬁed by a device path.
This protocol deﬁnes a standard interface for UEFI applications, drivers and OS loaders to register/unregister a RAM
disk.
The key points are:
• The consumer of this protocol is responsible for allocating/freeing memory used by RAM Disk if needed and
deciding the initial content, as in most scenarios only the consumer knows which type and how much memory
should be used.
13.17.2 EFI_RAM_DISK_PROTOCOL.Register()
Summary
This function is used to register a RAM disk with speciﬁed address, size and type.
Prototype
typedef
(EFIAPI *EFI_RAM_DISK_REGISTER_RAMDISK) (
IN UINT64 RamDiskBase,
IN UINT64 RamDiskSize,
IN EFI_GUID *RamDiskType,
IN EFI_DEVICE_PATH *ParentDevicePath OPTIONAL,
);
RamDiskBase The base address of registered RAM disk.
13.17. RAM Disk Protocol 536Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
RamDiskSize The size of registered RAM disk.
RamDiskType The type of registered RAM disk. The GUID can be any of the values deﬁned in RAM Disk , or a
vendor deﬁned GUID.
ParentDevicePath Pointer to the parent device path. If there is no parent device path then ParentDevicePath isNULL .
DevicePath On return, points to a pointer to the device path of the RAM disk device. If ParentDevicePath is not
NULL, the returned DevicePath is created by appending a RAM disk node to the parent device path. If Parent-
DevicePath isNULL , the returned DevicePath is a RAM disk device path without appending. This function is
responsible for allocating the buffer DevicePath with the boot service AllocatePool() .
TheRegister function is used to register a speciﬁed RAM Disk. The consumer of this API is responsible for allocating
the space of the RAM disk and deciding the initial content of the RAM disk. The producer of this API is responsible
for installing the RAM disk device path and block I/O related protocols on the RAM disk device handle.
RamDiskBase, RamDiskSize andRamDiskType are used to ﬁll RAM disk device node. If RamDiskSize is 0, then
EFI_INVALID_PARAMETER is returned. If RamDiskType isNULL, then EFI_INVALID_PARAMETER is returned.
DevicePath returns the device path of the registered RAM disk. If DevicePath isNULL, then
EFI_INVALID_PARAMETER is returned. If there are not enough resources to allocate the device path node, then
EFI_OUT_OF_RESOURCES is returned. Otherwise, DevicePath is allocated with the boot service AllocatePool() . If
ParentDevicePath is not NULL theDevicePath instance is created by appending a RAM disk device node to the Par-
entDevicePath . IfParentDevicePath isNULL theDevicePath instance is a pure RAM disk device path. If the created
DevicePath instance is already present in the handle database, then EFI_ALREADY_STARTED is returned.
EFI_SUCCESS The RAM disk is registered successfully.
EFI_INV ALID_PARAMETER DevicePath orRamDiskType isNULL .
EFI_INV ALID_PARAMETER RamDiskSize is 0.
EFI_ALREADY_STARTED A Device Path Protocol instance to be created is already present in the han-
dle database.
EFI_OUT_OF_RESOURCES The RAM disk register operation fails due to resource limitation.
13.17.3 EFI_RAM_DISK_PROTOCOL.Unregister()
Summary
This function is used to unregister a RAM disk speciﬁed by DevicePath .
Prototype
typedef
(EFIAPI *EFI_RAM_DISK_UNREGISTER_RAMDISK) (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
);
DevicePath A pointer to the device path that describes a RAM Disk device.
TheUnregister function is used to unregister a speciﬁed RAM Disk. The producer of this protocol is responsible for
uninstalling the RAM disk device path and block I/O related protocols and freeing the RAM disk device handle. It is
13.17. RAM Disk Protocol 537Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
the consumer of this protocol’s responsibility to free the memory used by this RAM disk.
EFI_SUCCESS The RAM disk is unregistered successfully.
EFI_UNSUPPORTED The device speciﬁed by DevicePath is not a valid ramdisk device path and
not supported by the driver.
EFI_NOT_FOUND The RAM disk pointed by DevicePath doesn’t exist.
13.18 Partition Information Protocol
Summary
Installed along with EFI_BLOCK_IO_PROTOCOL for logical partitions. The PARTI-
TION_INFORMATION_PROTOCOL provides cached partition information for MBR and GPT partition types.
Set System to 1 for partition identiﬁed as EFI_SYSTEM_PARTITIONs, otherwise set System to 0.
Set Type to PARTITION_TYPE_OTHER for partitions that are not GPT or MBR to indicate no cached data.
GUID
#define EFI_PARTITION_INFO_PROTOCOL_GUID \
{ \
0x8cf2f62c, 0xbc9b, 0x4821, {0x80, 0x8d, 0xec, 0x9e, \
0xc4, 0x21, 0xa1, 0xa0} \
}
#define EFI_PARTITION_INFO_PROTOCOL_REVISION 0x0001000
#define PARTITION_TYPE_OTHER 0x00
#define PARTITION_TYPE_MBR 0x01
#define PARTITION_TYPE_GPT 0x02
UINT8 System;
UINT8 Reserved[7];
union {
///
/// MBR data
///
MBR_PARTITION_RECORD Mbr;
///
/// GPT data
///
EFI_PARTITION_ENTRY Gpt;
} Info;
} EFI_PARTITION_INFO_PROTOCOL;
13.18. Partition Information Protocol 538Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
See the Legacy MBR for the deﬁnition of MBR_PARTITION_RECORD.
SeeProtective MBR for the deﬁnition of EFI_PARTITION_ENTRY .
Revision Set to EFI_PARTITION_INFO_PROTOCOL_REVISION
Type Partition info type (MBR, GPT, or Other).
System If 1, partition describes an EFI System Partition.
Mbr MBR information, if type is MBR.
Gpt GPT information, if type is GPT
The EFI_PARTITION_INFO_PROTOCOL is a simple protocol used to cache the partition information for potential
File System Drivers.
Care must be taken by UEFI utilities that manipulate partitions. The utility must gain exclusive access to the physical
disk to cause the partition driver to be stopped before it changes the partition information. If the exclusive request is
not granted, then the utility must reset the system after changing the partition information.
When Type is set to PARTITION_TYPE_OTHER, data in the union Info is undeﬁned.
13.19 NVDIMM Label Protocol
13.19.1 EFI_NVDIMM_LABEL_PROTOCOL
This section provides a detailed description of the EFI_NVDIMM_LABEL_PROTOCOL. For a high-level overview
of the NVDIMM Label protocol see the Label Storage Area Description section.
Summary
Provides services that allow management of labels contained in a Label Storage Area that are associated with a speciﬁc
NVDIMM Device Path. The labels describe how the data on the NVDIMM is organized in to namespaces, the layout
being utilized, logical block size, unique label identiﬁer, label state, etc.
GUID
#define EFI_NVDIMM_LABEL_PROTOCOL_GUID \
{0xd40b6b80,0x97d5,0x4282, \
{0xbb,0x1d,0x22,0x3a,0x16,0x91,0x80,0x58}}
typedef struct _EFI_NVDIMM_LABEL_PROTOCOL {
EFI_NVDIMM_LABEL_STORAGE_INFORMATION LabelStorageInformation;
EFI_NVDIMM_LABEL_STORAGE_READ LabelStorageRead;
EFI_NVDIMM_LABEL_STORAGE_WRITE LabelStorageWrite;
}
13.19. NVDIMM Label Protocol 539Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
LabelStorageInformation Reports the size of the Label Storage Area and the maximum amount of label data that
can be read in a single call to LabelStorageRead or written in a single call to LabelStorageWrite.
LabelStorageRead Returns the label data stored for the NVDIMM at the requested offset and length in the Label
Storage Area.
LabelStorageWrite Writes the label data stored for the NVDIMM at the requested offset and length in the Label
13.19.2 EFI_NVDIMM_LABEL_PROTOCOL.LabelStorageInformation()
Summary
Retrieves the Label Storage Area size and the maximum transfer size for the LabelStorageRead and LabelStorageWrite
methods that are associated with a speciﬁc NVDIMM Device Path.
Prototype
typedef
(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_INFORMATION) (
IN EFI_NVDIMM_LABEL_PROTOCOL *This,
OUT UINT32 *SizeOfLabelStorageArea,
OUT UINT32 *MaxTransferLength
);
This A pointer to the EFI_NVDIMM_LABEL_PROTOCOL instance.
SizeOfLabelStorageArea The size of the Label Storage Area for the NVDIMM in bytes.
MaxTransferLength The maximum number of bytes that can be transferred in a single call to LabelStorageRead or
LabelStorageWrite.

Summary
Prototype
typedef
);
methods.
EFI_SUCCESS The size of theLabel Storage Area and maximum transfer size returned are
valid.
EFI_ACCESS_DENIED The Label Storage Area for the NVDIMM device is not currently accessible
EFI_DEVICE_ERROR A physical device error occurred and the data transfer failed to complete
13.19.3 EFI_NVDIMM_LABEL_PROTOCOL.LabelStorageRead()
Summary
Retrieves label data for the NVDIMM for the requested byte offset and length from within the Label Storage Area that
are associated with a speciﬁc NVDIMM Device Path.
Prototype
typedef
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(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_READ) (
IN CONST EFI_NVDIMM_LABEL_PROTOCOL *This,
IN UINT32 Offset,
IN UINT32 TransferLength,
OUT UINT8 *LabelData
);
Offset The byte offset within the Label Storage Area to read from.
TransferLength Number of bytes to read from the Label Storage Area beginning at the byte Offset speciﬁed. A
TransferLength of 0 reads no data.
LabelData The return label data read at the requested offset and length from within the Label Storage Area.
Retrieves the label data for the requested offset and length from within the Label Storage Area for the NVDIMM. See
the Label Index Block and Label Deﬁnitions sections below for details on the contents of the label data.
EFI_SUCCESS The label data from the Label Storage Area for the NVDIMM was read suc-
cessfully at the speciﬁed Offset and TransferLength and LabelData contains
valid data.
EFI_INV ALID_PARAMETER Returned if any of the following are TRUE : - Offset > SizeOfLabelStor-
ageArea reported in the LabelStorageInformation return data. - Offset +
TransferLength is > SizeOfLabelStorageArea reported in the LabelStorage-
Information return data. - TransferLength is > MaxTransferLength reported
in the LabelStorageInformation return data.
and labels cannot be read at this time.
13.19.4 EFI_NVDIMM_LABEL_PROTOCOL.LabelStorageWrite()
Summary
Writes label data for the NVDIMM for the requested byte offset and length to the Label Storage Area that are associ-
ated with a speciﬁc NVDIMM Device Path.
Prototype
typedef
(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_WRITE) (
IN UINT8 *LabelData
);
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Offset The byte offset within the Label Storage Area to write to.
TransferLength Number of bytes to write to the Label Storage Area beginning at the byte Offset speciﬁed. A
TransferLength of 0 writes no data.
LabelBuffer The label data to write at the requested offset and length from within the Label Storage Area.
Writes the label data for the requested offset and length in to the Label Storage Area for the NVDIMM. See the Label
Index Block and Label Deﬁnitions sections below for details on the contents of the label data.
EFI_SUCCESS The LabelData for the Label Storage Area for the NVDIMM was written
successfully at the speciﬁed Offset and TransferLength.
EFI_INV ALID_PARAMETER
Returned this status if any of the following are TRUE :
- Offset > SizeOfLabelStorageArea reported in the
LabelStorageInformation return data.
- Offset + LabelBufferLength is > SizeOfLabelStorageArea reported in the
- TransferLength is > MaxTransferLength reported in the
and labels cannot be written at this time.
Label Index Block Deﬁnitions
#define EFI_NVDIMM_LABEL_INDEX_SIG_LEN 16
#define EFI_NVDIMM_LABEL_INDEX_ALIGN 256
typedef struct EFI_NVDIMM_LABEL_INDEX_BLOCK {
CHAR8 Sig[EFI_NVDIMM_LABEL_INDEX_SIG_LEN];
UINT8 Flags[3];
UINT8 LabelSize;
UINT32 Seq;
UINT64 MyOff;
UINT64 MySize;
UINT64 OtherOff;
UINT64 LabelOff;
UINT32 NSlot;
UINT8 Free[];
};
SigSignature of the Index Block data structure. Must be “NAMESPACE_INDEX0”.
Flags Boolean attributes of this Label Storage Area. There are no ﬂag bits deﬁned at this time, so this ﬁeld must be
zero.
LabelSize Size of each label in bytes, 128 bytes << LabelSize. 1 means 256 bytes, 2 means 512 bytes, etc. Shall be
1 or greater.
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Seq Sequence number used to identify which of the two Index Blocks is current. Only the least-signiﬁcant two bits
of this ﬁeld are used in the current deﬁnition, rotating through the values depicted in Figure Z: Cyclic Sequence
Numbers in Label Index Block below. The other bits must be zero.
Fig. 13.2: Cyclic Sequence Numbers in Label Index Block
Each time an Index Block is written, the sequence number of the current Index Block is “incremented” by moving to
the next value clockwise as shown.
Since there are two Index Blocks, written alternatively with successive sequence numbers, the older Index Block’s
sequence number will be immediately behind (counter-clockwise to) the current Index Block’s sequence number. This
property is used during software initialization to identify the current Index Block.
The sequence number 00 is used to indicate an uninitialized or invalid Index Block. Software never writes the sequence
number 00, so a correctly check-summed Index Block with this sequence number probably indicates a critical error.
When software discovers this case it treats it as an invalid Index Block indication. If two Index Blocks with identical
sequence numbers are found, software shall treat the Index Block at the higher offset as the valid Index Block.
MyOff The offset of this Index Block in the Label Storage Area.
MySize The size of this Index Block in bytes. This ﬁeld must be a multiple of the
EFI_NVDIMM_LABEL_INDEX_ALIGN.
OtherOff The offset of the other Index Block paired with this one.
LabelOff The offset of the ﬁrst slot where labels are stored in this Label Storage Area.
NSlot The total number of slots for storing labels in this Label Storage Area. The NSlot ﬁeld is typically calculated
once at Label Storage Area initialization as described in the Initial Label Storage Area Conﬁguration description.
Major Major version number. Value shall be 1.
Minor Minor version number. Value shall be 2.
Checksum 64-bit Fletcher64 checksum of all ﬁelds in this Index Block. This ﬁeld is considered zero when the
checksum is computed. For references to the Fletcher64 algorithm see “Links to UEFI-Related Documents”
(http://ueﬁ.org/ueﬁ) under the heading “Fletcher64 Checksum Algorithm”
Free Array of unsigned bytes implementing a bitmask that tracks which label slots are free. A bit value of
0 indicates in use, 1 indicates free. The size of this ﬁeld is the number of bytes required to hold the
bitmask with NSlot bits, padded with additional zero bytes to make the Index Block size a multiple of
EFI_NVDIMM_LABEL_INDEX_ALIGN. Any bits allocated beyond NSlot bits must be zero.
The bitmask is organized where the label slot with the lowest offset in the Label Storage Area is tracked by the
least signiﬁcant bit of the ﬁrst byte of the free array. Missing from the above layout is a total count of free slots.
Since the common use case for the Label Storage Area is to read all labels during software initialization, it is
recommended that software create a total free count (or in use count, or both), maintained at run-time. Rules
for maintaining the Index Blocks are described in the Label Rules Description and Validating Index Blocks
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Description below. See the Initial Label Storage Area Conﬁguration section for a more details on how the total
number of slots are calculated.
Label Deﬁnitions
#define EFI_NVDIMM_LABEL_NAME_LEN 64
#define EFI_NVDIMM_LABEL_FLAGS_ROLABEL 0x00000001
#define EFI_NVDIMM_LABEL_FLAGS_LOCAL 0x00000002
#define EFI_NVDIMM_LABEL_FLAGS_SPACOOKIE_BOUND 0x00000010
// This reserved flag isutilized on older implementations
//andhas been deprecated. Do notuse
#define EFI_NVDIMM_LABEL_FLAGS_RESERVED 0x00000004
#define EFI_NVDIMM_LABEL_FLAGS_UPDATING 0x00000008
typedef struct EFI_NVDIMM_LABEL{
CHAR8 Name[EFI_NVDIMM_LABEL_NAME_LEN];
UINT16 NLabel;

UINT16 Position;
UINT64 SetCookie;
UINT64 LbaSize;
UINT64 Dpa;
UINT64 RawSize;
UINT32 Slot;
UINT8 Alignment;
UINT8 Reserved[3];
EFI_GUID TypeGuid;
EFI_GUID AddressAbstractionGuid;
UINT64 SPALocationCookie;
UINT8 Reserved1[80];
};
Uuid Unique Label Identiﬁer UUID per RFC 4122. This ﬁeld provides two functions. First, the namespace is
associated with a UUID that software can use to uniquely identify it and providing a way for the namespace to
be matched up with applications using it. Second, when multiple labels are required to describe a namespace,
the UUID is the mechanism used to group the labels together. See the additional descriptions below describing
the process for grouping the labels together by UUID, checking for missing labels, recovering from partial label
changes, etc.
Name NULL-terminated string using UTF-8 character formatting. The Name ﬁeld is optionally used by software to
store a more friendly name for the namespace. When this ﬁeld is unused, it contains zeros.
If there is a name for a Local Namespace, as indicated by the EFI_NVDIMM_LABEL_FLAGS_LOCAL Flags,
the name shall be stored in the ﬁrst label of the set. All Name ﬁelds in subsequent labels for that Local Names-
pace are ignored. The Name ﬁeld can be set at label creation time, or updated by following the rules in the
additional descriptions below.
Flags Boolean attributes of this namespace. See the additional description below on the use of the ﬂags. The following
values are deﬁned:
EFI_NVDIMM_LABEL_FLAGS_ROLABEL - The label is read-only. This indicates the namespace is
exported to a domain where conﬁguration changes to the label are not allowed, such as a virtual ma-
chine. This indicates that device software and manageability software should refuse to make changes
to the labels. This is a not a security mechanism, but a usability feature instead. In cases where
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EFI_NVDIMM_LABEL_FLAGS_ROLABEL is set, such as virtual machine guests, attempting to make
conﬁguration changes that affect the labels will fail (i.e. because the VM guest is not in a position to make
the change correctly). For these cases, the VMM can set the EFI_NVDIMM_LABEL_FLAGS_ROLABEL
bit on the label exposed to the guest to provide a better user experience where manageability refuses to make
changes with a friendlier error message.
EFI_NVDIMM_LABEL_FLAGS_LOCAL - When set, the complete label set is local to a single
NVDIMM Label Storage Area. When clear, the complete label set is contained on multiple NVDIMM
Label Storage Areas. If NLabel is 1, then setting this ﬂag is optional and it is implied that the
EFI_NVDIMM_LABEL_FLAGS_LOCAL ﬂag is set, as the complete label set is local to a single NVDIMM
Label Storage Area.
EFI_NVDIMM_LABEL_FLAGS_UPDATING - When set, the label set is being up-
dated. During an operation that may require updating multiple Label Storage Areas, the
EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag is used to make the update atomic across interruptions.
Updates happen in two phases, ﬁrst writing the label with the EFI_NVDIMM_LABEL_FLAGS_UPDATING
ﬂag set, second writing the updated label without the EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag.
As described in Recovery Steps for a Non-Local Label Set Description, this allows recovery actions dur-
ing software initialization to either roll back or roll forward the multiple Label Storage Area changes. If
EFI_NVDIMM_LABEL_FLAGS_LOCAL is set, the labels are contained in a single Label Storage Area and
there is no need to set EFI_NVDIMM_LABEL_FLAGS_UPDATING , since the label can be written in one
atomic operation.
EFI_NVDIMM_LABEL_FLAGS_SPACOOKIE_BOUND - When set, the SPALocationCookie in the
namespace label is valid and should match the current value in the NFIT SPA Range Structure.
NLabel Total number of labels describing this namespace. The NLabel ﬁeld contains the number of labels required
to describe a namespace.
Position Position of this label in list of labels for this namespace. See NLabel description above. In the non-local case,
each label is numbered as to its position in the list of labels using the Position ﬁeld. For example, the common
case where a namespace requires exactly one label, NLabel will be 1 and Position will be 0. If a namespace is
built on an Interleave Set that spans multiple Label Storage Areas, each Label Storage Area will contain a label
with increasing Position values to show each labels position in the set. For Local Namespaces, NLabel is valid
only for the ﬁrst label (lowest DPA) and position shall be 0 for that label. As part of organizing and validating
the labels, SW shall have organized the labels from lowest to highest DPA so the ﬁrst label in that ordered list
of labels will have the lowest DPA. Position and NLabel for all subsequent labels in that namespace shall be set
to 0xFF. See the Local Namespace description in the Validating Labels Description section for details.
SetCookie Interleave Sets and the NVDIMMs they contain are deﬁned in the NFIT and the Uuid in the label is used
to uniquely identify each interleave set. The SetCookie is utilized by SW to perform consistency checks on
the Interleave Set to verify the current physical device conﬁguration matches the original physical conﬁguration
when the labels were created for the set. The label is considered invalid if the actual label set cookie doesn’t
match the cookie stored here. The SetCookie ﬁeld in each label for that namespace is derived from data in the
NVDIMM’s Serial Presence Detect (SPD). See the SetCookie Description section below for SetCookie details.
For references to the JEDEC SPD annex see “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under
the heading “JEDEC SPD Annex”
LbaSize This is the default logical block size in bytes and may be superseded by a block size that is speciﬁed in the
AbstractionGuid.
• A non-zero value indicates the logical block size that is being emulated.
• A value of zero indicates an unspeciﬁed size and its meaning is implementation speciﬁc
Dpa The DPA is the Device Physical Address where the NVM contributing to this namespace begins on this
NVDIMM.
RawSize The extent of the DPA contributed by this label.
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Slot Current slot in the Label Storage Area where this label is stored.
Alignment Alignment hint used to advertise the preferred alignment of the data from within the namespace deﬁned
by this label.
Reserved Shall be 0
TypeGuid Range Type GUID that describes the access mechanism for the speciﬁed DPA range. The GUIDs utilized
for the type are deﬁned in the ACPI 6.0 speciﬁcation in the NVDIMM FW Interface Table (NFIT) chapter.
Those values are utilized here to describe the Type of namespace the label is describing. See the Address Range
Type GUID ﬁeld described in the System Physical Address (SPA) Range Structure table.
AddressAbstractionGuid Identiﬁes the address abstraction mechanism for this namespace. A value of 0 indicates
no mechanism used.
SPALocationCookie When creating the label, this value is set to the value from the NFIT SPA Range Structure if
the SPALocationCookie ﬂag (bit 2) is set. If EFI_NVDIMM_LABEL_FLAGS_SPACOOKIE_BOUND is set, the
SPALocationCookie value stored in the namespace label should match the current value in the NFIT SPA Range
Structure. Otherwise, the data may not be read correctly.
Reserved1 Shall be 0
Checksum 64-bit Fletcher64 checksum of all ﬁelds in this Label. This ﬁeld is considered zero when the checksum is
computed. For references to the Fletcher64 algorithm see “Links to UEFI-Related Documents” (http://ueﬁ.org/
ueﬁ) under the heading “Fletcher64 Checksum Algorithm”
SetCookie Deﬁnition
typedef struct EFI_NVDIMM_LABEL_SET_COOKIE_INFO {
typedef struct EFI_NVDIMM_LABEL_SET_COOKIE_MAP {
UINT64 RegionOffset;
UINT32 SerialNumber;
UINT16 VendorId;
UINT16 ManufacturingDate;
UINT8 ManufacturingLocation;
UINT8 Reserved[31];
} Mapping[NumberOfNvdimmsInInterleaveSet];
};
NumberOfNvdimmsInInterleaveSet The number of NVDIMMs in the interleave set. This is 1 if
EFI_NVDIMM_LABEL_FLAGS_LOCAL Flags is set indicating a Local Namespaces.
RegionOffset The Region Offset ﬁeld from the ACPI NFIT NVDIMM Region Mapping Structure for a given entry.
This determines the entry’s position in the set. Region offset is 0 for Local Namespaces.
SerialNumber The serial number of the NVDIMM, assigned by the module vendor. This ﬁeld shall be set to the
value of the NVDIMM Serial Presence Detect (SPD) Module Serial Number ﬁeld deﬁned by JEDEC with byte
0 set to SPD byte 325, byte 1 set to SPD byte 326, byte 2 set to SPD byte 327, and byte 3 set to SPD byte 328.
VendorId The identiﬁer indicating the vendor of the NVDIMM. This ﬁeld shall be set to the value of the NVDIMM

};
SPD Module Manufacturer ID Code ﬁeld with byte 0 set to DDR4 SPD byte 320 and byte 1 set to DDR4 SPD
byte 321. For references to the JEDEC SPD annex see “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ)
under the heading “JEDEC SPD Annex”
ManufacturingDate The manufacturing date of the NVDIMM, assigned by the module vendor. This ﬁeld shall be
set to the value of the NVDIMM SPD Module Manufacturing Date ﬁeld with byte 0 set to SPD byte 323 and
byte 1 set to SPD byte 324. For references to the JEDEC SPD annex see “Links to UEFI-Related Documents”
(http://ueﬁ.org/ueﬁ) under the heading “JEDEC SPD Annex”
13.19. NVDIMM Label Protocol 546Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ManufacturingLocation The manufacturing location from for the NVDIMM, assigned by the module vendor. This
ﬁeld shall be set to the value of the NVDIMM SPD Module Manufacturing Location ﬁeld (SPD byte 322). For
references to the JEDEC SPD annex see “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the
heading “JEDEC SPD Annex”
SetCookie Description This value is used to detect a change in the set conﬁguration that has rendered exist-
ing data invalid and otherwise validates that the namespace belongs to a given NVDIMM. For each set
create a data structure of the form EFI_NVDIMM_LABEL_SET_COOKIE_INFO. The SetCookie is then
calculated by sorting the Mapping[] array by RegionOffset and then taking the Fletcher64 sum of the to-
tal EFI_NVDIMM_LABEL_SET_COOKIE_INFO structure. For references to the Fletcher64 algorithm see
“Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ ) under the heading “Fletcher64 Checksum Algorithm”
13.19.5 Label Storage Area Description
Namespaces are deﬁned by Labels which are stored in the Label Storage Area(s) and accessed via means described in
the Label Rules Description.
The ﬁgure below shows the organization of the Label Storage Area. A header called the Index Block appears twice
at the top of the Label Storage Area. This provides a powerfail-safe method for updating the information in the Label
Storage Area by alternating between the two Index Blocks when writing (more details on this mechanism below).
Fig. 13.3: Organization of the Label Storage Area
Following the Index Blocks, an array for storing labels takes up the remainder of the Label Storage Area. The size
of the Label Storage Area is NVDIMM implementation speciﬁc. The Index Blocks contain a bitmap which indicates
which label slots are currently free and which are in use. The same powerfail-safe mechanism used for updating the
Index Blocks covers the update of labels in the Label Storage Area.
The powerfail-safe update mechanism uses the principle of avoiding writes to active metadata. Instead, a shadow copy
is updated and checksums and sequence numbers are used to make the last written copy active (a complete description
of this mechanism is in Updating an Existing Label Description).
Initial Label Storage Area Conﬁguration
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The size of an Index Block depends on how many label slots ﬁt into the Label Storage Area. The minimum size of
an Index Block is 256 bytes and the size must be a multiple of EFI_NVDIMM_LABEL_INDEX_ALIGN bytes. As
necessary, padding with zero bytes at the end of the structure is used to meet these size requirements. The minimum
size of the Label Storage Area is large enough to hold 2 index blocks and 2 labels. As an example, for Label Storage
Areas of 128KB and 256KB, the corresponding Index Block size is 256 or 512 bytes:
Table 13.70: Initial Label Storage Area Conﬁguration
Example : <= 256 bytes Example : > 256 bytes
Size of the Index Block
ﬁeld up to the free ﬁeld72 bytes Size of the Index Block
ﬁeld up to the free ﬁeld72 bytes
Bytes required for a bit-
mask of 1024 labels (the
number of labels that ﬁt
into a 128KB Label Stor-
age Area)128 bytes Bytes required for a bit-
mask of 2048 labels (the
into a 256KB Label Stor-
age Area)256 bytes
Padding to meet next in-
crement of 256 bytes56 bytes Padding to meet next in-
crement of 256 bytes184
Total size of the Index
Block256 bytes 512 bytes
Before Index Blocks and labels can be utilized, the software managing the Label Storage Area must determine the
total number of labels that will be supported and utilizing the description above, calculate the size of the Index Blocks
required. Once the initial Label Storage Area is written with the ﬁrst Index Blocks (typically done when the ﬁrst Label
needs to be written), the total number of slots is ﬁxed and this initial calculation is not performed again.
Label Description
Each slot in the Label Storage Area is either free or contains an active label.
In the cases where multiple labels are used to describe a namespace, the label ﬁelds NLabel and Position provide an
ordering (“label one of two, label two of two”) so that incomplete label sets can be detected.
A namespace is described by one or more labels. Local namespaces describe one or more device physical address
ranges from a single NVDIMM while non-Local namespaces describe a single SPA range that may have contributions
from 2 or more NVDIMMs. The number of labels needed to describe a non-Local namespace is equal to the number
of NVDIMMs contributing to the SPA range, 1 per-NVDIMM. For a Local namespace any number, up to the max
number of labels supported by the Index Block / Label Storage Area, of device physical address ranges in the given
NVDIMM can be described.
Label Rules Description
All the algorithms related to labels in this speciﬁcation assume single-threaded / non-reentrant execution. The algo-
rithm for updating labels guarantees that at least one slot in the Label Storage Area will be free, ensuring it is always
possible to update labels using this method.
Software shall maintain the following invariants to use the on-media data structures correctly and to inter-operate with
other software components.
At all times, the following must be TRUE :
• The size of the Label Storage Area is known (this must be TRUE even if no namespace metadata has been
written yet). The Label Storage Area size is queried from the NVDIMM.
• The Label Storage Area either contains no valid Index Blocks, indicating there are no labels on the NVDIMM
(all slots free), or the validation rules below produce a single, valid, Index Block.
• 2 free slots are required in order to add a Label. Having only a single free slot indicates that
no more labels can be added. Only fully written, active labels, and full-written labels with the
13.19. NVDIMM Label Protocol 548Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag are marked in-use by the Index Block.
• Write to active label slots are not allowed; all updates to labels must be done by writing to free slots and then
updating the Index Block to make them active.
Validating Index Blocks Description
The following tests shall pass before software considers Index Blocks valid:
• Both Index Blocks must be read successfully from the Label Storage Area.
• Any Index Block with an incorrect Sigﬁeld is invalid.
• Any Index Block with an incorrect Checksum is invalid.
• Any Index Block with an incorrect MyOff, MySize , orOtherOff ﬁeld is invalid.
• Any Index Block with a sequence number Seqof zero is invalid.
• If two valid Index Blocks remain, after passing all the above tests, and their sequence numbers match, the Index
Block at the lower offset in the Label Storage Area is invalid.
• If two Index Blocks remain, after passing all the above tests, their sequence numbers are compared and the
block whose sequence number is the predecessor of the other (immediately counter-clockwise to it, as shown in
Figure Z: Cyclic Sequence Numbers in Label Index Block in the Seqdescription) is invalid.
• If one Index Block remains, that is the current, valid block and software should make note that the next update
to the Index Block will write the other Index Block. However, if no valid Index Blocks remain, all slots are
considered free and the next update to the index will write to the lower-addressed block location (i.e. the start
of the Label Storage Area).
Validating Labels Description
The following tests shall pass before software considers individual Labels slots valid:
• The corresponding free bit for the label Slot in the Index Block Free array must be clear (i.e. label slot is active).
• The label Checksum shall validate.
• The Slot value in the Label shall match the logical slot location of the Label.
• The SetCookie ﬁeld in the label matches the expected value as described in SetCookie Deﬁnition .
• The address range type GUID TypeGuid shall match the System Physical Address Range Structure that de-
scribes the access mechanism for this namespace. For Hardware Block Namespaces it shall match the GUID
for the NVDIMM Block Data Window Region.
For Local Namespaces:

• If 2 or more labels share the same Dpa value, all labels with the duplicated value are considered invalid.
• The count of all valid labels for a given namespace Uuid shall match the NLabel value in the ﬁrst label.
• The ﬁrst label, the label with the lowest Dpa value, shall have Position 0 and non-zero NLabel value.
• All labels other than the ﬁrst have Position andNLabel set to 0xff.
Reading Labels Description
For a given NVDIMM, the following steps are used to read one or more labels for validation and namespace assembly:
Pre-condition: both Index Blocks have been read and the rules in Validating Index Blocks Description have been
followed to determine the current valid Index Block.
• Check that the label at a given slot is active. Speciﬁcally bit N is clear in the Free bitmask ﬁeld where N
corresponds to the logical slot number label.
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• Read the label in that slot at the offset given by: (2 * sizeof(EFI_NVDIMM_LABEL_INDEX_BLOCK) +
slot * sizeof(EFI_NVDIMM_LABEL))
Recovery Steps for a Non-Local Label Set Description
Given that a non-Local Label set potentially spans multiple Label Storage Areas for multiple NVDIMMs it is not
possible to guarantee that the set is updated atomically with respect to unexpected system interruption. Recovery shall
be performed before validating the set to roll the set forward to a consistent state or invalidate / free the label slots
corresponding to an inconsistent state. Note that individual Index Block updates are safe with respect to unexpected
system interruption given the sequence number mechanism for indicating the currently active Index Block.
The sequence below describes how the EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag is used when validating
a non-Local Label Set.
• Pre-condition: The labels have been read.
• For each set of labels with the same UUID, if no labels in the set are found with the
EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag set, then no recovery is required for that set.
• For the sets where EFI_NVDIMM_LABEL_FLAGS_UPDATING appear at least once, if the set is incomplete
(some NVDIMMs in the set do not contain a label in the Label Storage Area with the UUID), the recovery action
is to roll back the interrupted create operation that left this state. I.e. for each NVDIMM in the set containing a
label with the given UUID, delete the label.
• For a set where EFI_NVDIMM_LABEL_FLAGS_UPDATING appears at least once and
the set is otherwise complete (each NVDIMM in the Interleave Set contains a label
with the UUID, some with EFI_NVDIMM_LABEL_FLAGS_UPDATING set, some with
EFI_NVDIMM_LABEL_FLAGS_UPDATING clear), the recovery action is to roll forward the change
that was interrupted. I.e. for each NVDIMM in the set If EFI_NVDIMM_LABEL_FLAGS_UPDATING is
set, write an updated label with EFI_NVDIMM_LABEL_FLAGS_UPDATING clear and with the name ﬁeld
copied from the ﬁrst label in the set (the label with a Position ﬁeld of 0).
Recovery Steps for a Local Label Set Description
Given that a Local Label set is always contained in a single Label Storage Area for a single NVDIMM, labels are
added/updated atomically, as long as there is a free Label available as outlined in Label Storage Area Description
andLabel Description. EFI_NVDIMM_LABEL_FLAGS_UPDATING should not be set for Local sets and no
additional recovery is required.
Assembling Labels into Complete Sets Description
After collecting a set of labels corresponding to a given UUID and performing the recovery actions on the set, software
shall follow the steps in this section to assemble complete sets of labels representing usable namespaces:
1. Precondition: Labels have been read and the recovery actions have been taken.
2. For each set of labels with the same Uuid
a. If the set describes a non-Local namespace, it is considered complete if labels with unique Position ﬁelds
are found for every position from 0toNLabel–1 .
b. If the set describes a Local namespace, it is considered complete if a valid ﬁrst label is found, according to
the validation rules, and the number of labels in the set matches
c.NLabel .
The recovery action for the case where software ﬁnds incomplete namespaces is implementation speciﬁc.
Updating an Existing Label Description
Updating an existing label in the Label Storage Area requires the software to follow these steps:
1. Pre-conditions: the software has an updated label constructed to be written to a speciﬁc NVDIMM’s Label
Storage Area. There is at least 1 free slot in the Label Storage Area Free bitmask.
13.19. NVDIMM Label Protocol 550Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2. The software chooses a free slot from the Index Block, ﬁlls in that slot number in the label’s Slot ﬁeld
3. The software writes the updated label to that slot in the Label Storage Area
4. The software updates the Index Block by taking the current Index Block, setting the appropriate bit in the Free
ﬁeld to make the old version of the label inactive and clearing the appropriate bit in the Free ﬁeld to make
the new version active, incrementing the sequence number as shown in Figure Z: Cyclic Sequence Numbers
in Label Index Block in the Seq description, and then writing the Index Block over the inactive Index Block
location (making this location the new active Index Block if the write succeeds)
Deleting a Label Description
The software updates the Index Block by taking the current active Index Block, setting the appropriate bit in the Free
ﬁeld to make the deleted label inactive, incrementing the sequence number as shown in Figure Z: Cyclic Sequence
Numbers in Label Index Block in the Seq description, and then writing the new Index Block over the inactive Index
Block location (making this location the new active Index Block if the write succeeds)
Creating Namespaces Description
Namespace creation procedures are different for Local vs non-Local namespaces. A Local namespace is created from
1 or more DPA ranges of a single NVDIMM, while a non-Local namespace is created from a single range contributed
from multiple NVDIMMs. Both procedures share a common ﬂow for establishing new labels in an Index Block.
Writing New Labels Description
Transitioning a label slot from free to active shall follow this sequence:
1. Pre-conditions: the software has a new label constructed to be written to a speciﬁc NVDIMM’s Label Stor-
age Area. Because of the free Label rules outlined in Label Storage Area Description and Label Description,
there are at least 2 free slots in the Label Storage Area as described in the Label Rules Description and Label
Description sections. Choose a free slot from the Index Block, ﬁlls in that slot number in the label’s Slot ﬁeld
2. Write the new label to that slot in the Label Storage Area
3. Update the Index Block by taking the current Index Block, clearing the appropriate bit in the Free ﬁeld, incre-
menting the sequence number as shown in Figure Z: Cyclic Sequence Numbers in Label Index Block in the Seq
description, and then writing the Index Block over the inactive Index Block location (making this location the
new active Index Block if the write succeeds)
Creating a Non-Local Namespace
When creating a new Non-Local Namespace, the software shall follow these steps:
1. Pre-conditions: the labels to be written to each NVDIMM contributing to the namespace have been constructed,
each with a unique Position ﬁeld from 0 to NLabel–1 , and all labels with the same new UUID. All Index Blocks
involved have at least 2 label slots free as described in the Label Rules Description andLabel Description
sections.
2. For each label in the set, the label is written with the EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag set,
using the ﬂow outlined in Writing New Labels Description to its corresponding NVDIMM / Label Storage
Area.
3. For each label in the set, the label is updated with the same contents as the previous step, but with the
EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag clear, using the ﬂow outlined in Updating an Existing
Label Description .
In the case of an unexpected system interruption, the above ﬂows leave either a partial set of labels, all with the new
UUID, with the EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag set, or a complete set of labels is left where
some of them have the EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag set. The recovery steps in Recovery
Steps for a Non-Local Label Set Description comprehend these two cases so that software can determine whether the
set is consistent or needs to be invalidated.
Creating a Local Namespace
13.19. NVDIMM Label Protocol 551Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Updating labels that are all on the same NVDIMM is atomic with respect to system interruption by
nature of the Index Block update rules. Since Local namespaces reside on a single NVDIMM, the
EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag and multi-pass update described in the previous section are

not used. Software creating new Local namespaces shall follow these steps:
1. Pre-conditions: the labels to be written to the NVDIMM Label Storage Area have been constructed, whereby
Position, NLabel andSetCookie adhere to the validation rules described earlier, and all labels share the same
UUID. The Index Blocks involved have at least NLabel + 1 label slots free, so that after the new labels are
written, it will have at least 1 free label slot left.
All labels are written to free slots and made active in one step using steps similar to the ﬂow described above in Writing
New Labels Description:
a. Free slots are identiﬁed using the current Index Block, the Slot ﬁeld in each label is updated accordingly
b. All new labels are written into their free slots
c. The new Index Block is constructed so the new label slots are no longer marked free, the sequence number is
advanced as shown in Figure Z: Cyclic Sequence Numbers in Label Index Block in the Seqdescription, and
then the new Index Block is written over the inactive Index Block location (making this location the new active
Index Block if the write succeeds)
13.19.5.1 Updating the Name of a Namespace Description
Updating Local Labels
When updating the name on a Local set the sequence outlined in Writing New Labels Description must be followed
where the Name is updated before writing the updated Label.
Updating Non Local Labels
To update the Name ﬁeld associated with a non-Local Namespace, the software must follow these steps:
1. Pre-conditions: the namespace must already exist. Each NVDIMM in the namespace must have at least 1 free
slot.
2. For each NVDIMM in the namespace, the label on that NVDIMM is updated with a label with the new Name
ﬁeld and the EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag set. The “for each NVDIMM ” operation in
this step must start with the NVDIMM containing the label whose Position ﬁeld is zero.
3. For each NVDIMM in the namespace, the label is updated with the same contents as the previous step, but
with the EFI_NVDIMM_LABEL_FLAGS_UPDATING ﬂag clear, using the updating an existing label ﬂow
described above in Updating an Existing Label Description.
If the above steps are interrupted unexpectedly, the recovery steps in Recovery Steps for a Non-Local Label Set
Description handle the case where a Name update is incomplete and ﬁnish the update.
13.20 EFI UFS Device Conﬁg Protocol
13.20.1 EFI_UFS_DEVICE_CONFIG_PROTOCOL
Summary
User invokes this protocol to access the UFS device descriptors/ﬂags/attributes and conﬁgure UFS device behavior.
GUID
13.20. EFI UFS Device Conﬁg Protocol 552Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_UFS_DEVICE_CONFIG_GUID \
{ 0xb81bfab0, 0xeb3, 0x4cf9, \
{ 0x84, 0x65, 0x7f, 0xa9, 0x86, 0x36, 0x16, 0x64}}
typedef struct _EFI_UFS_DEVICE_CONFIG_PROTOCOL {
EFI_UFS_DEVICE_CONFIG_RW_DESCRIPTOR RwUfsDescriptor;
EFI_UFS_DEVICE_CONFIG_RW_FLAG RwUfsFlag;
EFI_UFS_DEVICE_CONFIG_RW_ATTRIBUTE RwUfsAttribute;
} EFI_UFS_DEVICE_CONFIG_PROTOCOL;
Members
RwUfsDescriptor Read or write speciﬁed device descriptor of a UFS device.
RwUfsFlag Read or write speciﬁed ﬂag of a UFS device.
RwUfsAttribute Read or write speciﬁed attribute of a UFS device.
This protocol aims at deﬁning a standard interface for UEFI drivers and applications to access UFS device descrip-
tors/ﬂags/attributes and conﬁgure the UFS device behavior.
13.20.2 EFI_UFS_DEVICE_CONFIG_PROTOCOL.RwUfsDescriptor()
Summary
This function is used to read or write speciﬁed device descriptor of a UFS device.
Prototype
typedef
(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_DESCRIPTOR) (
IN EFI_UFS_DEVICE_CONFIG_PROTOCOL *This,
IN BOOLEAN Read,
IN UINT8 DescId,
IN UINT8 Index,
IN UINT8 Selector,
IN OUT UINT8 Descriptor,
IN OUT UINT32 *DescSize,
);
This The pointer to the EFI_UFS_DEVICE_CONFIG_PROTOCOL instance.
Read The boolean variable to show r/w direction.
DescId The ID of device descriptor.
Index The Index of device descriptor.
Selector The Selector of device descriptor.
Descriptor The buffer of device descriptor to be read or written.
DescSize The size of device descriptor buffer. On input, the size, in bytes, of the data buffer speciﬁed by Descriptor.
On output, the number of bytes that were actually transferred.
13.20. EFI UFS Device Conﬁg Protocol 553Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The RwUfsDescriptor function is used to read/write UFS device descriptors. The consumer of this API is responsible
for allocating the data buffer pointed by Descriptor.
EFI_SUCCESS The device descriptor is read/written successfully.
EFI_INV ALID_PARAMETER This is NULL or Descriptor is NULL or DescSize is NULL.
EFI_INV ALID_PARAMETER DescId, Index and Selector are invalid combination to point to a type of
UFS device descriptor.
EFI_DEVICE_ERROR The device descriptor is not read/written successfully.
13.20.3 EFI_UFS_DEVICE_CONFIG_PROTOCOL.RwUfsFlag()
Summary
This function is used to read or write speciﬁed ﬂag of a UFS device.
Prototype
typedef
(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_FLAG) (
IN UINT8 FlagId,
IN OUT UINT8 *Flag,
);
FlagId The ID of ﬂag to be read or written.
Flag The buffer to set or clear ﬂag.
The RwUfsFlag function is used to read/write UFS ﬂag descriptors. The consumer of this API is responsible for
allocating the buffer pointed by Flag. The buffer size is 1 byte as UFS ﬂag descriptor is just a single Boolean value
that represents a TRUE orFALSE , ‘0’ or ‘1’, ON or OFF type of value.
EFI_SUCCESS The ﬂag descriptor is set/clear successfully.
EFI_INV ALID_PARAMETER This is NULL or Flag is NULL.
EFI_INV ALID_PARAMETER FlagId is an invalid UFS ﬂag ID.
EFI_DEVICE_ERROR The ﬂag is not set/clear successfully.
13.20. EFI UFS Device Conﬁg Protocol 554Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
13.20.4 EFI_UFS_DEVICE_CONFIG_PROTOCOL.RwUfsAttribute()
Summary
This function is used to read or write speciﬁed attribute of a UFS device.
Prototype
typedef
(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_ATTRIBUTE) (
IN UINT8 AttrId,
IN OUT UINT8 *Attribute,
IN OUT UINT32 *AttrSize,
);
AttrId The ID of Attribute.
Index The Index of Attribute.
Selector The Selector of Attribute.
Attribute The buffer of Attribute to be read or written.
AttrSize The size of Attribute buffer. On input, the size, in bytes, of the data buffer speciﬁed by Attribute. On output,
the number of bytes that were actually transferred.
TheRwUfsAttribute function is used to read/write UFS attributes. The consumer of this API is responsible for allocat-
ing the data buffer pointed by Attribute .
EFI_SUCCESS The attribute is read/written successfully.
EFI_INV ALID_PARAMETER This is NULL or Attribute is NULL or AttrSize is NULL.
EFI_INV ALID_PARAMETER AttrId, Index and Selector are invalid combination to point to a type of UFS
attribute.
EFI_DEVICE_ERROR The attribute is not read/written successfully.
13.20. EFI UFS Device Conﬁg Protocol 555CHAPTER
FOURTEEN
PROTOCOLS — PCI BUS SUPPORT
14.1 PCI Root Bridge I/O Support
This section and the following one (Section 14.2) describe the PCI Root Bridge I/O Protocol. This protocol provides
an I/O abstraction for a PCI Root Bridge that is produced by a PCI Host Bus Controller. A PCI Host Bus Controller
is a hardware component that allows access to a group of PCI devices that share a common pool of PCI I/O and PCI
Memory resources. This protocol is used by a PCI Bus Driver to perform PCI Memory, PCI I/O, and PCI Conﬁguration
cycles on a PCI Bus. It also provides services to perform different types of bus mastering DMA on a PCI bus. PCI
device drivers will not directly use this protocol. Instead, they will use the I/O abstraction produced by the PCI Bus
Driver. Only drivers that require direct access to the entire PCI bus should use this protocol. In particular, this chapter
deﬁnes functions for managing PCI buses, although other bus types may be supported in a similar fashion as extensions
to this speciﬁcation.
All the services described in this chapter that generate PCI transactions follow the ordering rules deﬁned in the PCI
Speciﬁcation. If the processor is performing a combination of PCI transactions and system memory transactions, then
there is no guarantee that the system memory transactions will be strongly ordered with respect to the PCI transactions.
If strong ordering is required, then processor-speciﬁc mechanisms may be required to guarantee strong ordering. Some

64-bit systems may require the use of memory fences to guarantee ordering.
14.1.1 PCI Root Bridge I/O Overview
The interfaces provided in the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL are for performing basic operations to
memory, I/O, and PCI conﬁguration space. The system provides abstracted access to basic system resources to allow
a driver to have a programmatic method to access these basic system resources.
The EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL allows for future innovation of the platform. It abstracts device-
speciﬁc code from the system memory map. This allows system designers to make changes to the system memory
map without impacting platform independent code that is consuming basic system resources.
host buses. Figure Host Bus Controllers shows a platform with nprocessors (CPUs in the ﬁgure), and a set of core
chipset components that produce mhost bridges.
Simple systems with one PCI Host Bus Controller will contain a single instance of the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL . More complex system may contain multiple instances of this pro-
tocol. It is important to note that there is no relationship between the number of chipset components in a platform and
the number of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instances. This protocol abstracts access to a PCI Root
Bridge from a software point of view, and it is attached to a device handle that represents a PCI Root Bridge. A PCI
Root Bridge is a chipset component(s) that produces a physical PCI Bus. It is also the parent to a set of PCI devices
that share common PCI I/O, PCI Memory, and PCI Prefetchable Memory regions. A PCI Host Bus Controller is
composed of one or more PCI Root Bridges.
556Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 14.1: Host Bus Controllers
A PCI Host Bridge and PCI Root Bridge are different than a PCI Segment. A PCI Segment is a collection
of up to 256 PCI busses that share the same PCI Conﬁguration Space. Depending on the chipset, a single
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL may abstract a portion of a PCI Segment, or an entire PCI Segment.
A PCI Host Bridge may produce one or more PCI Root Bridges. When a PCI Host Bridge produces multiple PCI Root
Bridges, it is possible to have more than one PCI Segment.
PCI Root Bridge I/O Protocol instances are either produced by the system ﬁrmware or by a UEFI driver. When a PCI
Root Bridge I/O Protocol is produced, it is placed on a device handle along with an EFI Device Path Protocol instance.
The ﬁgure below ( Device Handle for a PCI Root Bridge Controller ) shows a sample device handle that includes an
instance of the EFI_DEVICE_PATH_PROTOCOL and the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
Section Section 14.2 describes the PCI Root Bridge I/O Protocol in detail, and Section 14.2.19 describes how to build
device paths for PCI Root Bridges. The EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL does not abstract access to the
chipset-speciﬁc registers used to manage a PCI Root Bridge. This functionality is hidden within the system ﬁrmware
or the driver that produces the handles that represent the PCI Root Bridges.
Fig. 14.2: Device Handle for a PCI Root Bridge Controller
14.1. PCI Root Bridge I/O Support 557Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
14.1.2 Sample PCI Architectures
The PCI Root Bridge I/O Protocol is designed to provide a software abstraction for a wide variety of PCI architectures
including the ones described in this section. This section is not intended to be an exhaustive list of the PCI architectures
that the PCI Root Bridge I/O Protocol can support. Instead, it is intended to show the ﬂexibility of this protocol to
adapt to current and future platform designs.
SeeDesktop System with One PCI Root Bridge shows an example of a PCI Host Bus with one PCI Root Bridge. This
PCI Root Bridge produces one PCI Local Bus that can contain PCI Devices on the motherboard and/or PCI slots. This
would be typical of a desktop system. A higher end desktop system might contain a second PCI Root Bridge for AGP
devices. The ﬁrmware for this platform would produce one instance of the PCI Root Bridge I/O Protocol.
Fig. 14.3: Desktop System with One PCI Root Bridge
Figure Server System with Four PCI Root Bridges shows an example of a larger server with one PCI Host Bus and four
PCI Root Bridges. The PCI devices attached to the PCI Root Bridges are all part of the same coherency domain. This
means they share a common PCI I/O Space, a common PCI Memory Space, and a common PCI Prefetchable Memory
Space. Each PCI Root Bridge produces one PCI Local Bus that can contain PCI Devices on the motherboard or PCI
slots. The ﬁrmware for this platform would produce four instances of the PCI Root Bridge I/O Protocol.
The Figure Server System with Two PCI Segments , below, shows an example of a server with one PCI Host Bus and
two PCI Root Bridges. Each of these PCI Root Bridges is a different PCI Segment which allows the system to have up
to 512 PCI Buses. A single PCI Segment is limited to 256 PCI Buses. These two segments do not share the same PCI
Conﬁguration Space, but they do share the same PCI I/O, PCI Memory, and PCI Prefetchable Memory Space. This is
why it can be described by a single PCI Host Bus. The ﬁrmware for this platform would produce two instances of the
PCI Root Bridge I/O Protocol.
The Figure, Server System with Two PCI Host Buses , below, shows a server system with two PCI Host Buses and
one PCI Root Bridge per PCI Host Bus. This system supports up to 512 PCI Buses, but the PCI I/O, PCI Memory
Space, and PCI Prefetchable Memory Space are not shared between the two PCI Root Bridges. The ﬁrmware for this
platform would produce two instances of the PCI Root Bridge I/O Protocol.
14.1. PCI Root Bridge I/O Support 558Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 14.4: Server System with Four PCI Root Bridges
Fig. 14.5: Server System with Two PCI Segments
14.1. PCI Root Bridge I/O Support 559Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 14.6: Server System with Two PCI Host Buses
14.2 PCI Root Bridge I/O Protocol
This section provides detailed information on the PCI Root Bridge I/O Protocol and its functions.
14.2.1 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
Summary
Provides the basic Memory, I/O, PCI conﬁguration, and DMA interfaces that are used to abstract accesses to PCI
controllers behind a PCI Root Bridge Controller.
GUID
#define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \
{0x2F707EBB,0x4A1A,0x11d4,\
{0x9A,0x38,0x00,0x90,0x27,0x3F,0xC1,0x4D}}
typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {
EFI_HANDLE
ParentHandle;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Mem;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Pci;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM CopyMem;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP Map;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP Unmap;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER FreeBuffer;
14.2. PCI Root Bridge I/O Protocol 560Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH Flush;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration;
UINT32 SegmentNumber;
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;
ParentHandle The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.
PollMem Polls an address in memory mapped I/O space until an exit condition is met, or a timeout occurs. See the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.PollMem() function description .
PollIo Polls an address in I/O space until an exit condition is met, or a timeout occurs. See the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.PollIo() function description.
Mem.Read Allows reads from memory mapped I/O space. See the Mem.Read()
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Mem.Read() function description.
Mem.Write Allows writes to memory mapped I/O space. See the Mem.Write()
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Mem.Write() function description.
Io.Read Allows reads from I/O space. See the Io.Read() EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Io.Read() func-
Io.Write Allows writes to I/O space. See the Io.Write() EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Io.WRITE()
Pci.Read Allows reads from PCI conﬁguration space. See the Pci.Read()
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() function description.
Pci.Write Allows writes to PCI conﬁguration space. See the Pci.Write()
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() function description.

CopyMem Allows one region of PCI root bridge memory space to be copied to another region of PCI root bridge
memory space. See the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.CopyMem() function description.
Map Provides the PCI controller-speciﬁc addresses needed to access system memory for DMA. See the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map() function description.
Unmap Releases any resources allocated by Map(). See the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Unmap()
AllocateBuffer Allocates pages that are suitable for a common buffer mapping. See the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.AllocateBuffer() function description.
FreeBuffer Free pages that were allocated with AllocateBuffer(). See the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.FreeBuffer() function description.
Flush Flushes all PCI posted write transactions to system memory. See the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Flush() function description.
GetAttributes Gets the attributes that a PCI root bridge supports setting with
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.SetAttributes() , and the attributes that a PCI root bridge is
currently using. See the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() function description.
SetAttributes Sets attributes for a resource range on a PCI root bridge. See
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.SetAttributes() function description.
Conﬁguration Gets the current resource settings for this PCI root bridge. See the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Conﬁguration() function description.
14.2. PCI Root Bridge I/O Protocol 561Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SegmentNumber The segment number that this PCI root bridge resides.
// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
EfiPciWidthUint8,
EfiPciWidthUint16,
EfiPciWidthUint32,
EfiPciWidthUint64,
EfiPciWidthFifoUint8,
EfiPciWidthFifoUint16,
EfiPciWidthFifoUint32,
EfiPciWidthFifoUint64,
EfiPciWidthFillUint8,
EfiPciWidthFillUint16,
EfiPciWidthFillUint32,
EfiPciWidthFillUint64,
EfiPciWidthMaximum
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;
// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM) (
IN struct EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
);
// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM) (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN UINTN Count,
IN OUT VOID *Buffer
);
// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write;
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;
14.2. PCI Root Bridge I/O Protocol 562Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI PCI Root Bridge I/O Protocol Attribute bits
#define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001
#define EFI_PCI_ATTRIBUTE_ISA_IO 0x0002
#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO 0x0004
#define EFI_PCI_ATTRIBUTE_VGA_MEMORY 0x0008
#define EFI_PCI_ATTRIBUTE_VGA_IO 0x0010
#define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO 0x0020
#define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO 0x0040
#define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080
#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800
#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE 0x1000
#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000
#define EFI_PCI_ATTRIBUTE_ISA_IO_16 0x10000
#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000
#define EFI_PCI_ATTRIBUTE_VGA_IO_16 0x40000
EFI_PCI_ATTRIBUTE_ISA_IO_16 If this bit is set, then the PCI I/O cycles between 0x100 and 0x3FF are for-
warded onto a PCI root bridge using a 16-bit address decoder on address bits 0..15. Address bits 16..31 must be
zero. This bit is used to forward I/O cycles for legacy ISA devices onto a PCI root bridge. This bit may not be
combined with EFI_PCI_ATTRIBUTE_ISA_IO .
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 If this bit is set, then the PCI I/O write cycles for 0x3C6,
0x3C8, and 0x3C9 are forwarded onto a PCI root bridge using a 16-bit address decoder on address bits
0..15. Address bits 16..31 must be zero. This bit is used to forward I/O write cycles to the VGA palette
registers onto a PCI root bridge. This bit may not be combined with EFI_PCI_ATTRIBUTE_VGA_IO or
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO .
EFI_PCI_ATTRIBUTE_VGA_IO_16 If this bit is set, then the PCI I/O cycles in the ranges 0x3B0-0x3BB
and 0x3C0-0x3DF are forwarded onto a PCI root bridge using a 16-bit address decoder on address
bits 0..15. Address bits 16..31 must be zero. This bit is used to forward I/O cycles for a VGA con-
troller onto a PCI root bridge. This bit may not be combined with EFI_PCI_ATTRIBUTE_VGA_IO
or EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO . Because EFI_PCI_ATTRIBUTE_VGA_IO_16
also includes the I/O range described by EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 , the
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 bit is ignored if EFI_PCI_ATTRIBUTE_VGA_IO_16 is
set.
EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO If this bit is set, then the PCI I/O cycles between
0x00000000 and 0x000000FF are forwarded onto a PCI root bridge. This bit is used to forward I/O cycles
for ISA motherboard devices onto a PCI root bridge.
EFI_PCI_ATTRIBUTE_ISA_IO If this bit is set, then the PCI I/O cycles between 0x100 and 0x3FF are forwarded
onto a PCI root bridge using a 10-bit address decoder on address bits 0..9. Address bits 10..15 are not decoded,
and address bits 16..31 must be zero. This bit is used to forward I/O cycles for legacy ISA devices onto a PCI
root bridge.
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO If this bit is set, then the PCI I/O write cycles for 0x3C6, 0x3C8,
and 0x3C9 are forwarded onto a PCI root bridge using a 10 bit address decoder on address bits 0..9. Address
bits 10..15 are not decoded, and address bits 16..31 must be zero. This bit is used to forward I/O write cycles to
the VGA palette registers onto a PCI root bridge.
EFI_PCI_ATTRIBUTE_VGA_MEMORY If this bit is set, then the PCI memory cycles between 0xA0000 and
0xBFFFF are forwarded onto a PCI root bridge. This bit is used to forward memory cycles for a VGA frame
buffer onto a PCI root bridge.
EFI_PCI_ATTRIBUTE_VGA_IO If this bit is set, then the PCI I/O cycles in the ranges 0x3B0-0x3BB and
14.2. PCI Root Bridge I/O Protocol 563Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
0x3C0-0x3DF are forwarded onto a PCI root bridge using a 10-bit address decoder on address bits 0..9.
Address bits 10..15 are not decoded, and the address bits 16..31 must be zero. This bit is used to forward I/O
cycles for a VGA controller onto a PCI root bridge. Since EFI_PCI_ATTRIBUTE_ENABLE_VGA_IO
also includes the I/O range described by EFI_PCI_ATTRIBUTE_ENABLE_VGA_PALETTE_IO,
the EFI_PCI_ATTRIBUTE_ENABLE_VGA_PALETTE_IO bit is ignored if
EFI_PCI_ATTRIBUTE_ENABLE_VGA_IO is set.
EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO If this bit is set, then the PCI I/O cycles in the ranges 0x1F0-0x1F7
and 0x3F6-0x3F7 are forwarded onto a PCI root bridge using a 16-bit address decoder on address bits 0..15.
Address bits 16..31 must be zero. This bit is used to forward I/O cycles for a Primary IDE controller onto a PCI
EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO If this bit is set, then the PCI I/O cycles in the ranges 0x170-
0x177 and 0x376-0x377 are forwarded onto a PCI root bridge using a 16-bit address decoder on address bits
0..15. Address bits 16..31 must be zero. This bit is used to forward I/O cycles for a Secondary IDE controller
onto a PCI root bridge.
EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE If this bit is set, then this platform supports changing
the attributes of a PCI memory range so that the memory range is accessed in a write combining mode. By
default, PCI memory ranges are not accessed in a write combining mode.
EFI_PCI_ATTRIBUTE_MEMORY_CACHED If this bit is set, then this platform supports changing the attributes
of a PCI memory range so that the memory range is accessed in a cached mode. By default, PCI memory ranges
are accessed noncached.
EFI_PCI_ATTRIBUTE_MEMORY_DISABLE If this bit is set, then this platform supports changing the attributes
of a PCI memory range so that the memory range is disabled, and can no longer be accessed. By default, all PCI
memory ranges are enabled.

EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE This bit may only be used in the Attributes parameter to
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.AllocateBuffer() . If this bit is set, then the PCI controller that is
requesting a buffer through AllocateBuffer() is capable of producing PCI Dual Address Cycles, so it is able to
access a 64-bit address space. If this bit is not set, then the PCI controller that is requesting a buffer through
AllocateBuffer() is not capable of producing PCI Dual Address Cycles, so it is only able to access a 32-bit
address space.
// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION
EfiPciOperationBusMasterRead,
EfiPciOperationBusMasterWrite,
EfiPciOperationBusMasterCommonBuffer,
EfiPciOperationBusMasterRead64,
EfiPciOperationBusMasterWrite64,
EfiPciOperationBusMasterCommonBuffer64,
EfiPciOperationMaximum
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;
EﬁPciOperationBusMasterRead A read operation from system memory by a bus master that is not capable of
producing PCI dual address cycles.
EﬁPciOperationBusMasterWrite A write operation to system memory by a bus master that is not capable of pro-
ducing PCI dual address cycles.
EﬁPciOperationBusMasterCommonBuffer Provides both read and write access to system memory by both the
processor and a bus master that is not capable of producing PCI dual address cycles. The buffer is coherent from
both the processor’s and the bus master’s point of view.
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EﬁPciOperationBusMasterRead64 A read operation from system memory by a bus master that is capable of pro-
EﬁPciOperationBusMasterWrite64 A write operation to system memory by a bus master that is capable of produc-
ing PCI dual address cycles.
EﬁPciOperationBusMasterCommonBuffer64 Provides both read and write access to system memory by both the
processor and a bus master that is capable of producing PCI dual address cycles. The buffer is coherent from
TheEFI_PCI_ROOT_BRIDGE_IO_PROTOCOL provides the basic Memory, I/O, PCI conﬁguration, and DMA inter-
faces that are used to abstract accesses to PCI controllers. There is one EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
instance for each PCI root bridge in a system. Embedded systems, desktops, and workstations will typically only have
one PCI root bridge. High-end servers may have multiple PCI root bridges. A device driver that wishes to manage
a PCI bus in a system will have to retrieve the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance that is associ-
ated with the PCI bus to be managed. A device handle for a PCI Root Bridge will minimally contain an EFI Device
Path Protocol instance and an EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. The PCI bus driver can look
at the EFI_DEVICE_PATH_PROTOCOL instances to determine which EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
instance to use.
Bus mastering PCI controllers can use the DMA services for DMA operations. There are three basic types of bus
mastering DMA that is supported by this protocol. These are DMA reads by a bus master, DMA writes by a bus
master, and common buffer DMA. The DMA read and write operations may need to be broken into smaller chunks.
The caller of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map() must pay attention to the number of bytes that were
mapped, and if required, loop until the entire buffer has been transferred. The following is a list of the different bus
mastering DMA operations that are supported, and the sequence of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL APIs
that are used for each DMA operation type. See “Related Deﬁnitions” above for the deﬁnition of the different DMA
operation types.
DMA Bus Master Read Operation
• Call EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map() for EﬁPciOperationBusMasterRead or EﬁPciOpera-
tionBusMasterRead64.
• Program the DMA Bus Master with the DeviceAddress returned by Map().
• Start the DMA Bus Master.
• Wait for DMA Bus Master to complete the read operation.
• Call EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Unmap()
DMA Bus Master Write Operation
• Call EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map() for EﬁPciOperationBusMasterWrite or EﬁPciOpera-
• Program the DMA Bus Master with the DeviceAddress returned by EFI_PCI_IO_PROTOCOL.Map()
• Wait for DMA Bus Master to complete the write operation.
• Perform a PCI controller speciﬁc read transaction to ﬂush all PCI write buffers (See PCI Speciﬁcation Section
3.2.5.2).
• Call EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Flush()
• Call Unmap.
DMA Bus Master Common Buffer Operation
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• Call EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.AllocateBuffer() to allocate a common buffer.
• Call Map() for EﬁPciOperationBusMasterCommonBuffer or EﬁPciOperationBusMasterCommonBuffer64.
• Program the DMA Bus Master with the DeviceAddress returned by
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map() .
• The common buffer can now be accessed equally by the processor and the DMA bus master.
• Call Unmap().
• Call EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.FreeBuffer() .
14.2.2 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.PollMem()
Summary
Reads from the memory space of a PCI Root Bridge. Returns when either the polling exit criteria is satisﬁed or after
a deﬁned duration.
Prototype
typedef
);
This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL . Type EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
is deﬁned in the Section PCI Root Bridge I/O Protocol .
Width Signiﬁes the width of the memory operations. Type EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
seeRelated Deﬁnitions in the section EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL .
Address The base address of the memory operations. The caller is responsible for aligning Address if required.
Mask Mask used for the polling criteria. Bytes above Width in Mask are ignored. The bits in the bytes below Width
which are zero in Mask are ignored when polling the memory address.
Value The comparison value used for the polling exit criteria.
Delay The number of 100 ns units to poll. Note that timer available may be of poorer granularity.
Result Pointer to the last value read from the memory location.
This function provides a standard way to poll a PCI memory location. A PCI memory read operation is performed at
the PCI memory address speciﬁed by Address for the width speciﬁed by Width . The result of this PCI memory read
operation is stored in Result . This PCI memory read operation is repeated until either a timeout of Delay 100 ns units
has expired, or ( Result &Mask) is equal to Value .
This function will always perform at least one PCI memory read access no matter how small Delay may be. If Delay
is zero, then Result will be returned with a status of EFI_SUCCESS even if Result does not match the exit criteria. If
Delay expires, then EFI_TIMEOUT is returned.
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IfWidth is not EﬁPciWidthUint8 ,EﬁPciWidthUint16 ,EﬁPciWidthUint32 , or EﬁPciWidthUint64 , then
The memory operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and
memory width restrictions that a PCI Root Bridge on a platform might require. For example on some platforms, width
requests of EﬁPciWidthUint64 are not supported.
All the PCI transactions generated by this function are guaranteed to be completed before this func-
tion returns. However, if the memory mapped I/O region being accessed by this function has the
EFI_PCI_ATTRIBUTE_MEMORY_CACHED attribute set, then the transactions will follow the ordering rules de-
ﬁned by the processor architecture.
EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
EFI_INV ALID_PARAMETER Width is invalid.
EFI_INV ALID_PARAMETER Result is NULL .
EFI_TIMEOUT Delay expired before a match occurred.
14.2.3 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.PollIo()
Summary
Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is satisﬁed or after a
deﬁned duration.
Prototype
typedef
);

Summary
Prototype
typedef
);
is deﬁned in PCI Root Bridge I/O Protocol .
Width Signiﬁes the width of the I/O operations. Type EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH see
Related Deﬁnitions in the section PCI Root Bridge I/O Protocol .
Address The base address of the I/O operations. The caller is responsible for aligning Address if required.
which are zero in Mask are ignored when polling the I/O address.
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This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is performed at the PCI
I/O address speciﬁed by Address for the width speciﬁed by Width . The result of this PCI I/O read operation is stored
inResult . This PCI I/O read operation is repeated until either a timeout of Delay 100 ns units has expired, or ( Result
& Mask ) is equal to Value .
This function will always perform at least one I/O access no matter how small Delay may be. If Delay is zero, then
Result will be returned with a status of EFI_SUCCESS even if Result does not match the exit criteria. If Delay expires,
then EFI_TIMEOUT is returned.
The I/O operations are carried out exactly as requested. The caller is responsible satisfying any alignment and I/O
width restrictions that the PCI Root Bridge on a platform might require. For example on some platforms, width
requests of EﬁPciWidthUint64 do not work.
All the PCI transactions generated by this function are guaranteed to be completed before this function returns.
14.2.4 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Mem.Read()
14.2.5 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Mem.Write()
Summary
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
Prototype
typedef
);
Width Signiﬁes the width of the memory operation. Type EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH see
Address The base address of the memory operation. The caller is responsible for aligning the Address if required.
Count The number of memory operations to perform. Bytes moved is Width size * Count, starting at Address.
14.2. PCI Root Bridge I/O Protocol 568Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Buffer For read operations, the destination buffer to store the results. For write operations, the source buffer to write
data from.
TheMem.Read() , and Mem.Write() functions enable a driver to access PCI controller registers in the PCI root bridge
memory space.
IfWidth isEﬁPciWidthUint8 ,EﬁPciWidthUint16 ,EﬁPciWidthUint32 , orEﬁPciWidthUint64 , then both Address and
Buffer are incremented for each of the Count operations performed.
IfWidth isEﬁPciWidthFifoUint8 ,EﬁPciWidthFifoUint16 ,EﬁPciWidthFifoUint32 , orEﬁPciWidthFifoUint64 , then
only Buffer is incremented for each of the Count operations performed. The read or write operation is performed
Count times on the same Address .
IfWidth isEﬁPciWidthFillUint8 ,EﬁPciWidthFillUint16 ,EﬁPciWidthFillUint32 , orEﬁPciWidthFillUint64 , then
only Address is incremented for each of the Count operations performed. The read or write operation is performed
Count times from the ﬁrst element of Buffer .
All the PCI read transactions generated by this function are guaranteed to be completed before this function returns.
All the PCI write transactions generated by this function will follow the write ordering and completion rules de-
ﬁned in the PCI Speciﬁcation. However, if the memory-mapped I/O region being accessed by this function has the
EFI_PCI_ATTRIBUTE_MEMORY_CACHED attribute set, then the transactions will follow the ordering rules deﬁned
by the processor architecture.
EFI_SUCCESS The data was read from or written to the PCI root bridge.
EFI_INV ALID_PARAMETER Width is invalid for this PCI root bridge.
EFI_INV ALID_PARAMETER Buffer is NULL .
14.2.6 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Io.Read()
14.2.7 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Io.Write()
Summary
Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
Prototype
typedef
);
14.2. PCI Root Bridge I/O Protocol 569Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Address The base address of the I/O operation. The caller is responsible for aligning the Address if required.
Count The number of I/O operations to perform. Bytes moved is Width size * Count, starting at Address.
data from.
TheIo.Read() , and Io.Write() functions enable a driver to access PCI controller registers in the PCI root bridge I/O
space.
The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O
width restrictions that a PCI root bridge on a platform might require. For example on some platforms, width requests
ofEﬁPciWidthUint64 do not work.
14.2.8 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read()
14.2.9 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write()
Summary
Enables a PCI driver to access PCI controller registers in a PCI root bridge’s conﬁguration space.
Prototype
typedef
14.2. PCI Root Bridge I/O Protocol 570Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);

Summary
Prototype
typedef
);
Address The address within the PCI conﬁguration space for the PCI controller. See PCI Conﬁguration Address for
the format of Address.
Count The number of PCI conﬁguration operations to perform. Bytes moved is Width size * Count, starting at
Address.
data from.
ThePci.Read() andPci.Write() functions enable a driver to access PCI conﬁguration registers for a PCI controller.
The PCI Conﬁguration operations are carried out exactly as requested. The caller is responsible for any alignment and
PCI conﬁguration width issues that a PCI Root Bridge on a platform might require. For example on some platforms,
width requests of EﬁPciWidthUint64 do not work.
IfWidth isEﬁPciWidthFillUint8 ,EﬁPciWidthFillUint16 ,EﬁPciWidthFillUint32 , orEﬁPciWidthFillUint64 , then only
Address is incremented for each of the Count operations performed. The read or write operation is performed Count
times from the ﬁrst element of Buffer .
Table 14.5: PCI Conﬁguration Address
Register 0 1 The register number on the PCI Function.
Function 1 1 The PCI Function number on the PCI Device.
Device 2 1 The PCI Device number on the PCI Bus.
Bus 3 1 The PCI Bus number.
ExtendedRegister 4 4 The register number on the PCI Function. If this ﬁeld is zero, then the
Register ﬁeld is used for the register number. If this ﬁeld is nonzero, then
the Register ﬁeld is ignored, and the E xtendedRegister ﬁeld is used for
the register number.
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Table 14.6 – continued from previous page
14.2.10 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.CopyMem()
Summary
Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI root bridge memory
space.
Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM) (
IN UINT64 DestAddress,
IN UINT64 SrcAddress,
);
DestAddress The destination address of the memory operation. The caller is responsible for aligning the DestAddress
if required.
SrcAddress The source address of the memory operation. The caller is responsible for aligning the SrcAddress if
required.
Count The number of memory operations to perform. Bytes moved is Width size * Count, starting at DestAddress
and SrcAddress.
TheCopyMem() function enables a PCI driver to copy one region of PCI root bridge memory space to another region
of PCI root bridge memory space. This is especially useful for video scroll operation on a memory mapped video
buffer.
memory width restrictions that a PCI root bridge on a platform might require. For example on some platforms, width
IfWidth isEﬁPciIoWidthUint8 ,EﬁPciIoWidthUint16 ,EﬁPciIoWidthUint32 , orEﬁPciIoWidthUint64 , then Count
read/write transactions are performed to move the contents of the SrcAddress buffer to the DestAddress buffer. The
implementation must be reentrant, and it must handle overlapping SrcAddress andDestAddress buffers. This means
that the implementation of CopyMem() must choose the correct direction of the copy operation based on the type of
overlap that exists between the SrcAddress andDestAddress buffers. If either the SrcAddress buffer or the DestAddress
The contents of the DestAddress buffer on exit from this service must match the contents of the SrcAddress buffer on
entry to this service. Due to potential overlaps, the contents of the SrcAddress buffer may be modiﬁed by this service.
The following rules can be used to guarantee the correct behavior:
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• IfDestAddress >SrcAddress andDestAddress < (SrcAddress +Width size * Count ), then the data should be
copied from the SrcAddress buffer to the DestAddress buffer starting from the end of buffers and working toward
the beginning of the buffers.
• Otherwise, the data should be copied from the SrcAddress buffer to the DestAddress buffer starting from the
beginning of the buffers and working toward the end of the buffers.
EFI_SUCCESS The data was copied from one memory region to another memory region.
14.2.11 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map()
Summary
Provides the PCI controller-speciﬁc addresses required to access system memory from a DMA bus master.
Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP) (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
Operation Indicates if the bus master is going to read or write to system memory. Type
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION deﬁned in Section PCI Root Bridge I/O Pro-
tocol .
HostAddress The system memory address to map to the PCI controller.
NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
DeviceAddress The resulting map address for the bus master PCI controller to use to access the system memory’s
HostAddress . Type EFI_PHYSICAL_ADDRESS , deﬁned in EFI_BOOT_SERVICES.AllocatePool() . This ad-
dress cannot be used by the processor to access the contents of the buffer speciﬁed by HostAddress .
Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
14.2. PCI Root Bridge I/O Protocol 573Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheMap() function provides the PCI controller speciﬁc addresses needed to access system memory. This function is
used to map system memory for PCI bus master DMA accesses.
All PCI bus master accesses must be performed through their mapped addresses and such mappings must be freed
with EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Unmap() when complete. If the bus master access is a single read
or single write data transfer, then EﬁPciOperationBusMasterRead ,EﬁPciOperationBusMasterRead64 ,EﬁPciOp-
erationBusMasterWrite , orEﬁPciOperationBusMasterWrite64 is used and the range is unmapped to complete the
operation. If performing an EﬁPciOperationBusMasterRead orEﬁPciOperationBusMasterRead64 operation, all the
data must be present in system memory before Map() is performed. Similarly, if performing an EﬁPciOperation-
BusMasterWrite orEﬁPciOperationBusMasterWrite64 the data cannot be properly accessed in system memory until
Unmap() is performed.
Bus master operations that require both read and write access or require multiple host device interactions within

the same mapped region must use EﬁPciOperation-BusMasterCommonBuffer orEﬁPciOperationBusMasterCommon-
Buffer64 . However, only memory allocated via the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.AllocateBuffer() in-
terface can be mapped for this type of operation.
In all mapping requests the resulting NumberOfBytes actually mapped may be less than the requested amount. In this
case, the DMA operation will have to be broken up into smaller chunks. The Map() function will map as much of the
DMA operation as it can at one time. The caller may have to loop on Map() andUnmap() in order to complete a large
DMA transfer.
EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
EFI_INV ALID_PARAMETER Operation is invalid.
EFI_INV ALID_PARAMETER HostAddress isNULL .
EFI_INV ALID_PARAMETER NumberOfBytes isNULL .
EFI_INV ALID_PARAMETER DeviceAddress isNULL .
EFI_INV ALID_PARAMETER Mapping isNULL .
EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
EFI_DEVICE_ERROR The system hardware could not map the requested address.
14.2.12 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Unmap()
Summary
Completes the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map() operation and releases any corresponding re-
sources.
Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP) (
IN VOID *Mapping
);
, deﬁned in PCI Root Bridge I/O Protocol .
Mapping The mapping value returned from Map().
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TheUnmap() function completes the Map() operation and releases any corresponding resources. If the operation was
anEﬁPciOperationBusMasterWrite orEﬁPciOperationBusMasterWrite64 , the data is committed to the target system
memory. Any resources used for the mapping are freed.
EFI_SUCCESS The range was unmapped.
EFI_INV ALID_PARAMETER Mapping is not a value that was returned by Map() .
EFI_DEVICE_ERROR The data was not committed to the target system memory.
14.2.13 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.AllocateBuffer()
Summary
Allocates pages that are suitable for an EﬁPciOperationBusMasterCommonBuffer orEﬁPciOperationBusMasterCom-
monBuffer64 mapping.
Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER) (
OUT VOID **HostAddress,
);
is deﬁned in Section PCI Root Bridge I/O Protocol .
Type This parameter is not used and must be ignored.
Memory Type The type of memory to allocate, EﬁBootServicesData orEﬁRuntimeServicesData . Type
EFI_MEMORY_TYPE is deﬁned in EFI_BOOT_SERVICES.AllocatePages() .
Pages The number of pages to allocate.
HostAddress A pointer to store the base system memory address of the allocated range.
Attributes The requested bit mask of attributes for the allocated range. Only the attributes
EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE ,EFI_PCI_ATTRIBUTE_MEMORY_CACHED ,
and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function. If any other bits
are set, then EFI_UNSUPPORTED is returned. This function may choose to ignore this bit mask. The
EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE , and EFI_PCI_ATTRIBUTE_MEMORY_CACHED
attributes provide a hint to the implementation that may improve the performance of the calling driver. The
implementation may choose any default for the memory attributes including write combining, cached, both, or
neither as long as the allocated buffer can be seen equally by both the processor and the PCI bus master.
The AllocateBuffer() function allocates pages that are suitable for an EﬁPciOperationBusMasterCommonBuffer or
EﬁPciOperationBusMasterCommonBuffer64 mapping. This means that the buffer allocated by this function must
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support simultaneous access by both the processor and a PCI Bus Master. The device address that the PCI Bus Master
uses to access the buffer can be retrieved with a call to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Map() .
If the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE bit of Attributes is set, then when the buffer allocated by
this function is mapped with a call to Map() , the device address that is returned by Map() must be within the 64-bit
device address space of the PCI Bus Master.
If the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE bit of Attributes is clear, then when the buffer allocated by
this function is mapped with a call to Map() , the device address that is returned by Map() must be within the 32-bit
If the memory allocation speciﬁed by MemoryType andPages cannot be satisﬁed, then EFI_OUT_OF_RESOURCES
EFI_SUCCESS The requested memory pages were allocated.
EFI_INV ALID_PARAMETER MemoryType is invalid.
Attributes is unsupported. The only legal attribute bits are
EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE ,
EFI_PCI_ATTRIBUTE_MEMORY_CACHED , and
EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE .
EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
14.2.14 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.FreeBuffer()
Summary
Frees memory that was allocated with EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.AllocateBuffer() .
Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER) (
IN VOID *HostAddress
);
Pages The number of pages to free.
HostAddress The base system memory address of the allocated range.
TheFreeBuffer() function frees memory that was allocated with AllocateBuffer() .
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EFI_SUCCESS The requested memory pages were freed.
EFI_INV ALID_PARAMETER The memory range speciﬁed by HostAddress and Pages was not allocated
with AllocateBuffer() .
14.2.15 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Flush()
Summary
Flushes all PCI posted write transactions from a PCI host bridge to system memory.
Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH) (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
);
The Flush() function ﬂushes any PCI posted write transactions from a PCI host bridge to system memory. Posted
write transactions are generated by PCI bus masters when they perform write transactions to target addresses in system
memory.
This function does not ﬂush posted write transactions from any PCI bridges. A PCI controller speciﬁc action must be
taken to guarantee that the posted write transactions have been ﬂushed from the PCI controller and from all the PCI
bridges into the PCI host bridge. This is typically done with a PCI read transaction from the PCI controller prior to
calling Flush() .
If the PCI controller speciﬁc action required to ﬂush the PCI posted write transactions has been performed, and
this function returns EFI_SUCCESS , then the PCI bus master’s view and the processor’s view of system memory are
guaranteed to be coherent. If the PCI posted write transactions cannot be ﬂushed from the PCI host bridge, then the PCI
bus master and processor are not guaranteed to have a coherent view of system memory, and EFI_DEVICE_ERROR
EFI_SUCCESS The PCI posted write transactions were ﬂushed from the PCI host bridge to
system memory.
EFI_DEVICE_ERROR The PCI posted write transactions were not ﬂushed from the PCI host bridge
due to a hardware error.
14.2. PCI Root Bridge I/O Protocol 577Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
14.2.16 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes()
Summary
Gets the attributes that a PCI root bridge supports setting with EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.SetAttributes()
, and the attributes that a PCI root bridge is currently using. Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES) (
OUT UINT64 *Supports OPTIONAL,
OUT UINT64 *Attributes OPTIONAL
);

Summary
typedef
);
Supports A pointer to the mask of attributes that this PCI root bridge supports setting with SetAttributes(). The
available attributes are listed in See PCI Root Bridge I/O Protocol . This is an optional parameter that may be
NULL .
Attributes A pointer to the mask of attributes that this PCI root bridge is currently using. The available attributes are
listed in See PCI Root Bridge I/O Protocol . This is an optional parameter that may be NULL .
TheGetAttributes() function returns the mask of attributes that this PCI root bridge supports and the mask of attributes
that the PCI root bridge is currently using. If Supports is not NULL , then Supports is set to the mask of attributes that
the PCI root bridge supports. If Attributes is not NULL , then Attributes is set to the mask of attributes that the PCI root
bridge is currently using. If both Supports andAttributes areNULL , then EFI_INVALID_PARAMETER is returned.
Otherwise, EFI_SUCCESS is returned.
If a bit is set in Supports , then the PCI root bridge supports this attribute type, and a call can be made to SetAttributes()
using that attribute type. If a bit is set in Attributes , then the PCI root bridge is currently using that attribute type.
Since a PCI host bus may be composed of more than one PCI root bridge, different Attributes values may be returned
by different PCI root bridges.
EFI_SUCCESS If Supports is not NULL , then the attributes that the PCI root bridge sup-
ports is returned in Supports. If Attributes is not NULL , then the attributes
that the PCI root bridge is currently using is returned in Attributes.
EFI_INV ALID_PARAMETER Both Supports and Attributes are NULL .
14.2.17 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.SetAttributes()
Summary
Sets attributes for a resource range on a PCI root bridge.
Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES) (
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IN OUT UINT64 *ResourceBase OPTIONAL,
IN OUT UINT64 *ResourceLength OPTIONAL
);
This A pointer to the See EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL . Type
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL is deﬁned in See PCI Root Bridge I/O Protocol .
Attributes The mask of attributes to set. If the attribute bit MEMORY_WRITE_COMBINE, MEMORY_CACHED,
or MEMORY_DISABLE is set, then the resource range is speciﬁed by ResourceBase and ResourceLength.
If MEMORY_WRITE_COMBINE, MEMORY_CACHED, and MEMORY_DISABLE are not set, then Re-
sourceBase and ResourceLength are ignored, and may be NULL. The available attributes are listed in See PCI
Root Bridge I/O Protocol .
ResourceBase A pointer to the base address of the resource range to be modiﬁed by the attributes speciﬁed by
Attributes. On return, ResourceBase will be set the actual base address of the resource range. Not all resources
can be set to a byte boundary, so the actual base address may differ from the one passed in by the caller.
This parameter is only used if the MEMORY_WRITE_COMBINE bit, the MEMORY_CACHED bit, or the
MEMORY_DISABLE bit of Attributes is set. Otherwise, it is ignored, and may be NULL .
ResourceLength A pointer to the length of the resource range to be modiﬁed by the attributes speciﬁed by Attributes.
On return, ResourceLength will be set the actual length of the resource range. Not all resources can be set to
a byte boundary, so the actual length may differ from the one passed in by the caller. This parameter is only
used if the MEMORY_WRITE_COMBINE bit, the MEMORY_CACHED bit, or the MEMORY_DISABLE bit of
Attributes is set. Otherwise, it is ignored, and may be **NULL* .
The SetAttributes() function sets the attributes speciﬁed in Attributes for the PCI root bridge on the resource range
speciﬁed by ResourceBase andResourceLength . Since the granularity of setting these attributes may vary from re-
source type to resource type, and from platform to platform, the actual resource range and the one passed in by the
caller may differ. As a result, this function may set the attributes speciﬁed by Attributes on a larger resource range
than the caller requested. The actual range is returned in ResourceBase andResourceLength . The caller is responsible
for verifying that the actual range for which the attributes were set is acceptable.
If the attributes are set on the PCI root bridge, then the actual resource range is returned in ResourceBase andRe-
sourceLength , and EFI_SUCCESS is returned.
If the attributes speciﬁed by Attributes are not supported by the PCI root bridge, then EFI_UNSUPPORTED
is returned. The set of supported attributes for a PCI root bridge can be found by calling
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() .
If either ResourceBase orResourceLength areNULL , and a resource range is required for the attributes speciﬁed in
Attributes , then EFI_INVALID_PARAMETER is returned.
If more than one resource range is required for the set of attributes speciﬁed by Attributes , then
If there are not enough resources available to set the attributes, then EFI_OUT_OF_RESOURCES is returned.
14.2. PCI Root Bridge I/O Protocol 579Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The set of attributes speciﬁed by Attributes for the resource range speci-
ﬁed by ResourceBase and ResourceLength were set on the PCI root bridge,
and the actual resource range is returned in ResuourceBase and Resource-
Length.
EFI_UNSUPPORTED A bit is set in Attributes that is not supported by the PCI
Root Bridge. The supported attribute bits are reported by
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes()
EFI_INV ALID_PARAMETER More than one attribute bit is set in Attributes that requires a resource range.
EFI_INV ALID_PARAMETER A resource range is required, and ResourceBase is NULL .
EFI_INV ALID_PARAMETER A resource range is required, and ResourceLength is NULL .
EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the resource range
speciﬁed by BaseAddress and Length.
14.2.18 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Conﬁguration()
Summary
Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI resource descriptors.
Prototype
typedef
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION) (
OUT VOID **Resources
);
This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL, which is deﬁned in PCI Root Bridge I/O Protocol .
Resources A pointer to the resource descriptors that describe the current conﬁguration of this PCI root bridge. The
storage for the resource descriptors is allocated by this function. The caller must treat the return buffer as read-
only data, and the buffer must not be freed by the caller. See “Related Deﬁnitions” for the resource descriptors
that may be used.
There are only two resource descriptor types from the ACPI Speciﬁcation that may be used to describe the current
resources allocated to a PCI root bridge. These are the QWORD Address Space Descriptor, and the End Tag. The
QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic or ﬁxed resources.
The conﬁguration of a PCI root bridge is described in the Tables below with one or more QWORD Address Space
Descriptors followed by an End Tag which contain these two descriptor types.
Please see the ACPI Speciﬁcation for details on the ﬁeld values. The deﬁnition of the Address Space Granularity ﬁeld
in the QWORD Address Space Descriptor differs from the ACPI Speciﬁcation, and the deﬁnition in the table below is
the one that must be used.
Table 14.15: QWORD Address Space Descriptor
Byte Off-
setByte
0x00 0x01 0x8A QWORD Address Space Descriptor
0x01 0x02 0x2B Length of this descriptor in bytes not including the ﬁrst two ﬁelds
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Table 14.15 – continued from previous page
0x03 0x01
Resource Type
0 - Memory Range
1 - I/O Range
2 - Bus Number Range
0x04 0x01 General Flags
0x05 0x01 Type Speciﬁc Flags
0x06 0x08 Address Space Granularity. Used to differentiate between a 32-bit memory
request and a 64-bit memory request. For a 32-bit memory request, this
ﬁeld should be set to 32. For a 64-bit memory request, this ﬁeld should be
set to 64.
0x0E 0x08 Address Range Minimum
0x16 0x08 Address Range Maximum
0x1E 0x08 Address Translation Offset. Offset to apply to the Starting address to con-
vert it to a PCI address. This value is zero unless the HostAddress and
DeviceAddress for the root bridge are different.
0x26 0x08 Address Length
Table 14.16: End Tag
Byte Off-
setByte
0x00 0x01 0x79 End Tag
0x01 0x01 0x00 Checksum. If 0, then checksum is assumed to be valid.

0x03 0x01
set to 64.
Byte Off-
setByte
The Conﬁguration() function retrieves a set of resource descriptors that contains the current conﬁguration of this
PCI root bridge. If the current conﬁguration can be retrieved, then it is returned in Resources andEFI_SUCCESS is
returned. See “Related Deﬁnitions” below for the resource descriptor types that are supported by this function. If the
current conﬁguration cannot be retrieved, then EFI_UNSUPPORTED is returned.
EFI_SUCCESS The current conﬁguration of this PCI root bridge was returned in Resources.
EFI_UNSUPPORTED The current conﬁguration of this PCI root bridge could not be retrieved.
14.2.19 PCI Root Bridge Device Paths
SeeEFI_PCI_ROOT_BRIDGE_IO_PROTOCOL must be installed on a handle for its services to be available to
drivers. In addition to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL , anEFI Device Path Protocol must also be
installed on the same handle.
Typically, an ACPI Device Path Node is used to describe a PCI Root Bridge. Depending on the bus hierarchy in the
system, additional device path nodes may precede this ACPI Device Path Node. A desktop system will typically con-
tain only one PCI Root Bridge, so there would be one handle with a EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
and an EFI_DEVICE_PATH_PROTOCOL A server system may contain multiple PCI Root Bridges, so it
would contain a handle for each PCI Root Bridge present, and on each of those handles would be an
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL and an EFI_DEVICE_PATH_PROTOCOL . In all cases, the contents of
the ACPI Device Path Nodes for PCI Root Bridges must match the information present in the ACPI tables for that
system.
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Table below: PCI Root Bridge Device Path for a Desktop System shows an example device path for a PCI Root Bridge
in a desktop system. Today, a desktop system typically contains one PCI Root Bridge. This device path consists
of an ACPI Device Path Node, and a Device Path End Structure. The _HID and _UID must match the ACPI table
description of the PCI Root Bridge. For a system with only one PCI Root Bridge, the _UID value is usually 0x0000.
The shorthand notation for this device path is ACPI(PNP0A03,0) .
Table 14.18: PCI Root Bridge Device Path for a Desktop System
Byte Off-
setByte
0x0C 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x0D 0x01 0xFF Sub type - End of Entire Device Path
0x0E 0x02 0x04 Length - 0x04 bytes
In the Tables belows, PCI Root Bridge Device Path for Bridge #0 in a Server System through PCI Root Bridge Device
Path for Bridge #3 in a Server System show example device paths for the PCI Root Bridges in a server system with four
PCI Root Bridges. Each of these device paths consists of an ACPI Device Path Node, and a Device Path End Structure.
The _HID and _UID must match the ACPI table description of the PCI Root Bridges. The only difference between
each of these device paths is the _UID ﬁeld. The shorthand notation for these four device paths is ACPI(PNP0A03,0)
,ACPI(PNP0A03,1) ,ACPI(PNP0A03,2) , and ACPI(PNP0A03,3) .
Table 14.19: PCI Root Bridge Device Path for Bridge #0 in a Server
System
Byte Off-
setByte
Table 14.20: PCI Root Bridge Device Path for Bridge #1 in aServer
System
Byte Off-
setByte
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Table 14.20 – continued from previous page
0x08 0x04 0x0001 _UID
Table 14.21: PCI Root Bridge Device Path for Bridge #2 in aServer
System
Byte Off-
setByte
0x08 0x04 0x0002 _UID
0x0D 0x01 0xF Sub type - End of Entire Device Path
Table 14.22: PCI Root Bridge Device Path for Bridge #3 in a Server
System
Byte Off-
setByte
0x08 0x04 0x0003 _UID
The Table below, PCI Root Bridge Device Path Using Expanded ACPI Device Path , shows an example device path
for a PCI Root Bridge using an Expanded ACPI Device Path. This device path consists of an Expanded ACPI Device
Path Node, and a Device Path End Structure. The _UID and _CID ﬁelds must match the ACPI table description of
the PCI Root Bridge. For a system with only one PCI Root Bridge, the _UID value is usually 0x0000. The shorthand
notation for this device path is ACPI(12345678,0,PNP0A03) .
Table 14.23: PCI Root Bridge Device Path Using Expanded ACPI De-
vice Path
Byte Off-
setByte
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Table 14.23 – continued from previous page
0x01 0x01 0x02 Sub type - Expanded ACPI Device Path
0x02 0x02 0x10 Length - 0x10 bytes
0x04 0x04 0x1234,
0x5678_HID-device speciﬁc
0x0C 0x04 0x41D0,
0x0A03_CID PNP0A03 - 0x41D0 represents the compressed string ‘PNP’ and is
0x10 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x11 0x01 0xFF Sub type - End of Entire Device Path
0x12 0x02 0x04 Length - 0x04 bytes
14.3 PCI Driver Model
PCI Driver Model andEFI PCI I/O Protocol describe the PCI Driver Model. This includes the behavior of PCI Bus
Drivers, the behavior of a PCI Device Drivers, and a detailed description of the PCI I/O Protocol. The PCI Bus Driver
manages PCI buses present in a system, and PCI Device Drivers manage PCI controllers present on PCI buses. The
PCI Device Drivers produce an I/O abstraction that can be used to boot an EFI compliant operating system.
This document provides enough material to implement a PCI Bus Driver, and the tools required to design and imple-
ment a PCI Device Drivers. It does not provide any information on speciﬁc PCI devices.
The material contained in this section is designed to extend this speciﬁcation and the UEFI Driver Model in a way that
supports PCI device drivers and PCI bus drivers. These extensions are provided in the form of PCI-speciﬁc protocols.
This section provides the information required to implement a PCI Bus Driver in system ﬁrmware. The section also
contains the information required by driver writers to design and implement PCI Device Drivers that a platform may
need to boot a UEFI-compliant OS.
The PCI Driver Model described here is intended to be a foundation on which a PCI Bus Driver and a wide variety of
PCI Device Drivers can be created.
14.3.1 PCI Driver Initialization

There are very few differences between a PCI Bus Driver and PCI Device Driver in the entry point of the driver. The
ﬁle for a driver image must be loaded from some type of media. This could include ROM, FLASH, hard drives, ﬂoppy
drives, CD-ROM, or even a network connection. Once a driver image has been found, it can be loaded into system
memory with the Boot Service: EFI_BOOT_SERVICES.LoadImage() .LoadImage() loads a PE/COFF formatted im-
age into system memory. A handle is created for the driver, and a Loaded Image Protocol instance is placed on that
handle. A handle that contains a Loaded Image Protocol instance is called an Image Handle. At this point, the driver
After a driver has been loaded with the Boot Service EFI_BOOT_SERVICES.LoadImage() , it must be started with
the Boot Service EFI_BOOT_SERVICES.StartImage() . This is true of all types of applications and drivers that can be
loaded and started on an UEFI compliant system. The entry point for a driver that follows the UEFI Driver Model must
follow some strict rules. First, it is not allowed to touch any hardware. Instead, it is only allowed to install protocol
instances onto its own Image Handle. A driver that follows the UEFI Driver Model is required to install an instance of
the Driver Binding Protocol onto its own Image Handle. It may optionally install the Driver Diagnostics Protocol or
the Component Name Protocol. In addition, if a driver wishes to be unloadable it may optionally update the Loaded
Image Protocol to provide its own Unload() EFI_LOADED_IMAGE_PROTOCOL.Unload() function. Finally, if a
driver needs to perform any special operations when the Boot Service EFI_BOOT_SERVICES is called ( Services —
14.3. PCI Driver Model 584Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 14.7: Image Handle
Boot Services ), the driver may optionally create an event with a notiﬁcation function that is triggered when the Boot
Service ExitBootServices() is called. An Image Handle that contains a Driver Binding Protocol instance is known as
a Driver Image Handle. The Figure below, PCI Driver Image Handle , shows a possible conﬁguration for the Image
Handle from ﬁgure: Image Handle after the Boot Service StartImage() has been called.
Fig. 14.8: PCI Driver Image Handle
14.3.2 Driver Diagnostics Protocol
If a PCI Bus Driver or a PCI Device Driver requires diagnostics, then an EFI_DRIVER_DIAGNOSTICS2_PROTOCOL
must be installed on the image handle in the entry point for the driver. This protocol contains functions to perform
diagnostics on a controller. The EFI_DRIVER_DIAGNOSTICS2_PROTOCOL is not allowed to interact with the user.
Instead, it must return status information through a bffer. The functions of this protocol will be invoked by a platform
management utility.
14.3. PCI Driver Model 585Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
14.3.3 Component Name Protocol
Both a PCI Bus Driver and a PCI Device Driver are able to produce user readable names for the PCI drivers and/or
the set of PCI controllers that the PCI drivers are managing. This is accomplished by installing an instance of the
EFI_COMPONENT_NAME2_PROTOCOL on the image handle of the driver. This protocol can produce driver and
controller names in the form of a string in one of several languages. This protocol can be used by a platform man-
agement utility to display user readable names for the drivers and controllers present in a system. Please see the EFI
Driver Model Speciﬁcation for details on the EFI_COMPONENT_NAME2_PROTOCOL .
14.3.4 Driver Family Override Protocol
If a PCI Bus Driver or PCI Device Driver always wants the PCI driver delivered in a PCI Option ROM to manage the
PCI controller associated with the PCI Option ROM, then the Driver Family Override Protocol must not be produced.
If a PCI Bus Driver or PCI Device Driver always wants the PCI driver with the highest Version value in the Driver
Binding Protocol to manage all the PCI Controllers in the same family of PCI controllers, then the Driver Family
Override Protocol must be produced on the same handle as the Driver Binding Protocol.
14.3.5 PCI Bus Drivers
A PCI Bus Driver manages PCI Host Bus Controllers that can contain one or more PCI Root Bridges. PCI Host Bus
Controller shows an example of a desktop system that has one PCI Host Bus Controller with one PCI Root Bridge.
Fig. 14.9: PCI Host Bus Controller
The PCI Host Bus Controller shown above is abstracted in software with the PCI Root Bridge I/O Protocol. A PCI
Bus Driver will manage handles that contain this protocol. Device Handle for a PCI Host Bus Controller shows an
example device handle for a PCI Host Bus Controller. It contains a Device Path Protocol instance and a PCI Root
Bridge I/O Protocol Instance.
14.3. PCI Driver Model 586Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 14.10: Device Handle for a PCI Host Bus Controller
14.3.6 Driver Binding Protocol for PCI Bus Drivers
The Driver Binding Protocol contains three services. These are Supported()
EFI_DRIVER_BINDING_PROTOCOL.Supported() , EFI_DRIVER_BINDING_PROTOCOL.Start() , and
EFI_DRIVER_BINDING_PROTOCOL.Stop() .Supported() tests to see if the PCI Bus Driver can manage a de-
vice handle. A PCI Bus Driver can only manage device handles that contain the Device Path Protocol and the PCI
Root Bridge I/O Protocol, so a PCI Bus Driver must look for these two protocols on the device handle that is being
tested.
TheStart() function tells the PCI Bus Driver to start managing a device handle. The device handle should support the
protocols shown in Device Handle for a PCI Host Bus Controller . The PCI Root Bridge I/O Protocols provides access
to the PCI I/O, PCI Memory, PCI Prefetchable Memory, and PCI DMA functions. The PCI Controllers behind a PCI
Root Bridge may exist on one or more PCI Buses. The standard mechanism for expanding the number of PCI Buses
on a single PCI Root Bridge is to use PCI to PCI Bridges. Once a PCI Enumerator conﬁgures these bridges, they are
invisible to software. As a result, the PCI Bus Driver ﬂattens the PCI Bus hierarchy when it starts managing a device
handle that represents a PCI Host Controller. Physical PCI Bus Structure shows the physical tree structure for a set of
PCI Device denoted by A, B, C, D, and E. Device A and C are PCI to PCI Bridges.
Fig. 14.11: Physical PCI Bus Structure
Connecting a PCI Bus Driver shows the tree structure generated by a PCI Bus Driver before and after Start() is called.
This is a logical view of set of PCI controller, and not a physical view. The physical tree is ﬂattened, so any PCI to
PCI bridge devices are invisible. In this example, the PCI Bus Driver ﬁnds the ﬁve child PCI Controllers on the PCI
Bus from Physical PCI Bus Structure . A device handle is created for every PCI Controller including all the PCI to
PCI Bridges. The arrow with the dashed line coming into the PCI Host Bus Controller represents a link to the PCI
Host Bus Controller’s parent. If the PCI Host Bus Controller is a Root Bus Controller, then it will not have a parent.
The PCI Driver Model does not require that a PCI Host Bus Controller be a Root Bus Controller. A PCI Host Bus
14.3. PCI Driver Model 587Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Controller can be present at any location in the tree, and the PCI Bus Driver should be able to manage the PCI Host
Bus Controller.
Fig. 14.12: Connecting a PCI Bus Driver
The PCI Bus Driver has the option of creating all of its children in one call to
EFI_DRIVER_BINDING_PROTOCOL.Start() , or spreading it across several calls to Start() . In general, if it
is possible to design a bus driver to create one child at a time, it should do so to support the rapid boot capability in the
UEFI Driver Model. Each of the child device handles created in Start() must contain a Device Path Protocol instance,
a PCI I/O protocol instance, and optionally a Bus Speciﬁc Driver Override Protocol instance. The PCI I/O Protocol
is described in EFI PCI I/O Protocol . The format of device paths for PCI Controllers is described in Section 2.6, and
details on the Bus Speciﬁc Driver Override Protocol can be found in the EFI Driver Model Speciﬁcation. The Figure
below shows an example child device handle that is created by a PCI Bus Driver for a PCI Controller.
Fig. 14.13: Child Handle Created by a PCI Bus Driver
A PCI Bus Driver must perform several steps to manage a PCI Host Bus Controller, as follows:
• Initialize the PCI Host Bus Controller.
• If the PCI buses have not been initialized by a previous agent, perform PCI Enumeration on all the PCI Root
Bridges that the PCI Host Bus Controller contains. This involves assigning a PCI bus number, allocating PCI

I/O resources, PCI Memory resources, and PCI Prefetchable Memory resources.
• Discover all the PCI Controllers on all the PCI Root Bridges. If a PCI Controller is a PCI to PCI Bridge,
then the I/O and Memory bits in the Control register of the PCI Conﬁguration Header should be placed in
the enabled state. The Bus Master bit in the Control Register may be enabled by default or enabled or dis-
abled based on the needs of downstream devices for DMA access during the boot process. The PCI Bus
Driver should disable the I/O, Memory, and Bus Master bits for PCI Controllers that respond to legacy ISA
resources (e.g. VGA). It is a PCI Device Driver’s responsibility to enable the I/O, Memory, and Bus Master
bits (if they are not already enabled by the PCI bus driver) of the Control register as required with a call to
theEFI_PCI_IO_PROTOCOL.Attributes() service when the PCI Device Driver is started. A similar call to the
Attributes() service should be made when the PCI Device Driver is stopped to restore original Attributes() state,
including the I/O, Memory, and Bus Master bits of the Control register.
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• Create a device handle for each PCI Controller found. If a request is being made to start only one PCI Controller,
then only create one device handle.
• Install a Device Path Protocol instance and a PCI I/O Protocol instance on the device handle created for each
PCI Controller.
• If the PCI Controller has a PCI Option ROM, then allocate a memory buffer that is the same size as the PCI
Option ROM, and copy the PCI Option ROM contents to the memory buffer.
• If the PCI Option ROM contains any UEFI drivers, then attach a Bus Speciﬁc Driver Override Protocol to the
device handle of the PCI Controller that is associated with the PCI Option ROM.
TheEFI_DRIVER_BINDING_PROTOCOL.Stop() function tells the PCI Bus Driver to stop managing a PCI Host Bus
Controller. The Stop() function can destroy one or more of the device handles that were created on a previous call to
EFI_DRIVER_BINDING_PROTOCOL.Start() . If all of the child device handles have been destroyed, then Stop() will
place the PCI Host Bus Controller in a quiescent state. The functionality of Stop() mirrors Start() , as follows:
1. Complete all outstanding transactions to the PCIHost Bus Controller.
2. If the PCI Host Bus Controller is being stopped, then place it in a quiescent state.
3. If one or more child handles are being destroyed, then:
a. Uninstall all the protocols from the device handles for the PCI Controllers found in Start().
b. Free any memory buffers allocated for PCI Option ROMs.
c. Destroy the device handles for the PCI controllers created in Start().
14.3.7 PCI Enumeration
The PCI Enumeration process is a platform-speciﬁc operation that depends on the properties of the chipset that pro-
duces the PCI bus. As a result, details on PCI Enumeration are outside the scope of this document. A PCI Bus Driver
requires that PCI Enumeration has been performed, so it either needs to have been done prior to the PCI Bus Driver
starting, or it must be part of the PCI Bus Driver’s implementation.
14.3.8 PCI Device Drivers
PCI Device Drivers manage PCI Controllers. Device handles for PCI Controllers are created by PCI Bus Drivers. A
PCI Device Driver is not allowed to create any new device handles. Instead, it attaches protocol instance to the device
handle of the PCI Controller. These protocol instances are I/O abstractions that allow the PCI Controller to be used in
the preboot environment. The most common I/O abstractions are used to boot an EFI compliant OS.
14.3.9 Driver Binding Protocol for PCI Device Drivers
The Driver Binding Protocol contains three services. These are EFI_DRIVER_BINDING_PROTOCOL.Supported()
,EFI_DRIVER_BINDING_PROTOCOL.Start() , and EFI_DRIVER_BINDING_PROTOCOL.Stop() .Supported() tests
to see if the PCI Device Driver can manage a device handle. A PCI Device Driver can only manage device handles that
contain the Device Path Protocol and the PCI I//O Protocol, so a PCI Device Driver must look for these two protocols
on the device handle that is being tested. In addition, it needs to check to see if the device handle represents a PCI
Controller that the PCI Device Driver knows how to manage. This is typically done by using the services of the PCI
I/O Protocol to read the PCI Conﬁguration Header for the PCI Controller, and looking at the VendorId ,DeviceId , and
SubsystemId ﬁelds.
TheStart() function tells the PCI Device Driver to start managing a PCI Controller. A PCI Device Driver is not allowed
to create any new device handles. Instead, it installs one or more addition protocol instances on the device handle for
the PCI Controller. A PCI Device Driver is not allowed to modify the resources allocated to a PCI Controller. These
14.3. PCI Driver Model 589Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
resource allocations are owned by the PCI Bus Driver or some other ﬁrmware component that initialized the PCI
Bus prior to the execution of the PCI Bus Driver. This means that the PCI BARs (Base Address Registers) and the
conﬁguration of any PCI to PCI bridge controllers must not be modiﬁed by a PCI Device Driver.A PCI Bus Driver
will leave a PCI Device in a disabled safe initial state. A PCI Device Driver should save the original Attributes() state.
It is a PCI Device Driver’s responsibility to call Attributes() to enable the I/O, Memory, and Bus Master decodes if
they are not already enabled by the PCI bus driver.
TheEFI_DRIVER_BINDING_PROTOCOL.Stop() function mirrors the EFI_DRIVER_BINDING_PROTOCOL.Start()
function, so the Stop() function completes any outstanding transactions to the PCI Controller and removes the protocol
interfaces that were installed in Start() . The Figure below shows the device handle for a PCI Controller before and
after Start() is called. In this example, a PCI Device Driver is adding the Block I/O Protocol to the device handle for
the PCI Controller. It is also a PCI Device Driver’s responsibility to restore original Attributes() state, including the
I/O, Memory, and Bus Master decodes by calling EFI_PCI_IO_PROTOCOL.Attributes() .
Fig. 14.14: Connecting a PCI Device Driver
14.4 EFI PCI I/O Protocol
This section provides a detailed description of the EFI PCI I/O Protocol . This protocol is used by code, typically
drivers, running in the EFI boot services environment to access memory and I/O on a PCI controller. In particular,
functions for managing devices on PCI buses are deﬁned here.
The interfaces provided in the EFI_PCI_IO_PROTOCOL are for performing basic operations to memory, I/O, and
PCI conﬁguration space. The system provides abstracted access to basic system resources to allow a driver to have
a programmatic method to access these basic system resources. The main goal of this protocol is to provide an
abstraction that simpliﬁes the writing of device drivers for PCI devices. This goal is accomplished by providing the
following features:
• A driver model that does not require the driver to search the PCI busses for devices to manage. Instead, drivers
are provided the location of the device to manage or have the capability to be notiﬁed when a PCI controller is
discovered.
• A device driver model that abstracts the I/O addresses, Memory addresses, and PCI Conﬁguration addresses
from the PCI device driver. Instead, BAR (Base Address Register) relative addressing is used for I/O and
Memory accesses, and device relative addressing is used for PCI Conﬁguration accesses. The BAR relative
addressing is speciﬁed in the PCI I/O services as a BAR index. A PCI controller may contain a combination of
14.4. EFI PCI I/O Protocol 590Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
32-bit and 64-bit BARs. The BAR index represents the logical BAR number in the standard PCI conﬁguration
header starting from the ﬁrst BAR. The BAR index does not represent an offset into the standard PCI Conﬁg-
uration Header because those offsets will vary depending on the combination and order of 32-bit and 64-bit
BARs.
• The Device Path for the PCI device can be obtained from the same device handle that the
EFI_PCI_IO_PROTOCOL resides.
• The PCI Segment, PCI Bus Number, PCI Device Number, and PCI Function Number of the PCI device if they
are required. The general idea is to abstract these details away from the PCI device driver. However, if these
details are required, then they are available.
• Details on any nonstandard address decoding that is not covered by the PCI device’s Base Address Registers.
• Access to the PCI Root Bridge I/O Protocol for the PCI Host Bus for which the PCI device is a member.
• A copy of the PCI Option ROM if it is present in system memory.
• Functions to perform bus mastering DMA. This includes both packet based DMA and common buffer DMA.
14.4.1 EFI_PCI_IO_PROTOCOL
Summary

BARs.
Summary
Provides the basic Memory, I/O, PCI conﬁguration, and DMA interfaces that a driver uses to access its PCI controller.
GUID
#define EFI_PCI_IO_PROTOCOL_GUID \
{0x4cf5b200,0x68b8,0x4ca5,\
{0x9e,0xec,0xb2,0x3e,0x3f,0x50,0x02,0x9a}}
typedef struct _EFI_PCI_IO_PROTOCOL {
EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;
EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;
EFI_PCI_IO_PROTOCOL_ACCESS Mem;
EFI_PCI_IO_PROTOCOL_ACCESS Io;
EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;
EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;
EFI_PCI_IO_PROTOCOL_MAP Map;
EFI_PCI_IO_PROTOCOL_UNMAP Unmap;
EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;
EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;
EFI_PCI_IO_PROTOCOL_FLUSH Flush;
EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;
EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;
EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;
EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;
UINT64 RomSize;
VOID *RomImage;
} EFI_PCI_IO_PROTOCOL;
PollMem Polls an address in PCI memory space until an exit condition is met, or a timeout occurs.
EFI_PCI_IO_PROTOCOL.PollMem() function description.
14.4. EFI PCI I/O Protocol 591Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PollIo Polls an address in PCI I/O space until an exit condition is met, or a timeout occurs.
EFI_PCI_IO_PROTOCOL.PollIo() function description.
Mem.Read Allows BAR relative reads to PCI memory space. EFI_PCI_IO_PROTOCOL.MEM.READ() function
Mem.Write Allows BAR relative writes to PCI memory space. See the Mem.Write()
EFI_PCI_IO_PROTOCOL.MEM.WRITE() function description.
Io.Read Allows BAR relative reads to PCI I/O space. See the Io.Read() EFI_PCI_IO_PROTOCOL.Io.Read() func-
Io.Write Allows BAR relative writes to PCI I/O space. See the Io.Write() EFI_PCI_IO_PROTOCOL.Io.Write()
Pci.Read Allows PCI controller relative reads to PCI conﬁguration space. See the Pci.Read()
EFI_PCI_IO_PROTOCOL.Pci.Read() function description.
Pci.Write Allows PCI controller relative writes to PCI conﬁguration space. See the Pci.Write()
EFI_PCI_IO_PROTOCOL.Pci.Write() function description.
CopyMem Allows one region of PCI memory space to be copied to another region of PCI memory space.
EFI_PCI_IO_PROTOCOL.CopyMem() function description.
Map Provides the PCI controller-speciﬁc address needed to access system memory for DMA. See the
EFI_PCI_IO_PROTOCOL.Map() function description.
Unmap Releases any resources allocated by Map(). See the EFI-PCI-IO-PROTOCOL-Unmap() function description.
EFI_PCI_IO_PROTOCOL.AllocateBuffer() function description.
FreeBuffer Frees pages that were allocated with AllocateBuffer(). See the EFI_PCI_IO_PROTOCOL.FreeBuffer()
Flush Flushes all PCI posted write transactions to system memory. See the EFI_PCI_IO_PROTOCOL.Flush() func-
GetLocation Retrieves this PCI controller’s current PCI bus number, device number, and function number. See the
EFI_PCI_IO_PROTOCOL.GetLocation() function description.
Attributes Performs an operation on the attributes that this PCI controller supports. The operations include getting
the set of supported attributes, retrieving the current attributes, setting the current attributes, enabling attributes,
and disabling attributes. See the EFI_PCI_IO_PROTOCOL.Attributes() function description.
GetBarAttributes Gets the attributes that this PCI controller supports setting on a BAR using
EFI_PCI_IO_PROTOCOL.SetBarAttributes() , and retrieves the list of resource descriptors for a BAR.
See the EFI_PCI_IO_PROTOCOL.GetBarAttributes() function description.
SetBarAttributes Sets the attributes for a range of a BAR on a PCI controller. See the SetBarAttributes() function
RomSize The size, in bytes, of the ROM image.
RomImage A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible for allocating
memory for the ROM image, and copying the contents of the ROM to memory. The contents of this buffer are
either from the PCI option ROM that can be accessed through the ROM BAR of the PCI controller, or it is from a
platform-speciﬁc location. The EFI_PCI_IO_PROTOCOL.Attributes() function can be used to determine from
which of these two sources the RomImage buffer was initialized.
14.4. EFI PCI I/O Protocol 592Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_PCI_IO_PROTOCOL_WIDTH
EfiPciIoWidthUint8,
EfiPciIoWidthUint16,
EfiPciIoWidthUint32,
EfiPciIoWidthUint64,
EfiPciIoWidthFifoUint8,
EfiPciIoWidthFifoUint16,
EfiPciIoWidthFifoUint32,
EfiPciIoWidthFifoUint64,
EfiPciIoWidthFillUint8,
EfiPciIoWidthFillUint16,
EfiPciIoWidthFillUint32,
EfiPciIoWidthFillUint64,
EfiPciIoWidthMaximum
} EFI_PCI_IO_PROTOCOL_WIDTH;
#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff
// EFI_PCI_IO_PROTOCOL_POLL_IO_MEM
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM) (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
);
// EFI_PCI_IO_PROTOCOL_IO_MEM
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM) (
);
// EFI_PCI_IO_PROTOCOL_ACCESS
EFI_PCI_IO_PROTOCOL_IO_MEM Read;
EFI_PCI_IO_PROTOCOL_IO_MEM Write;
} EFI_PCI_IO_PROTOCOL_ACCESS;
14.4. EFI PCI I/O Protocol 593Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_PCI_IO_PROTOCOL_CONFIG
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG) (
);
// EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS
EFI_PCI_IO_PROTOCOL_CONFIG Read;
EFI_PCI_IO_PROTOCOL_CONFIG Write;
} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;
// EFI PCI I/O Protocol Attribute bits /
˓→********************************************************
#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004
#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010
#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020
#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080
#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100
#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200
#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000
#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000
EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 If this bit is set, then the PCI I/O cycles between 0x100 and 0x3FF are for-
warded to the PCI controller using a 16-bit address decoder on address bits 0..15. Address bits 16..31 must be
zero. This bit is used to forward I/O cycles for legacy ISA devices. If this bit is set, then the PCI Host Bus Con-
troller and all the PCI to PCI bridges between the PCI Host Bus Controller and the PCI Controller are conﬁgured
to forward these PCI I/O cycles. This bit may not be combined with EFI_PCI_IO_ATTRIBUTE_ISA_IO .
EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 If this bit is set, then the PCI I/O write cycles for 0x3C6,
0x3C8, and 0x3C9 are forwarded to the PCI controller using a 16-bit address decoder on address bits 0..15.
Address bits 16..31 must be zero. This bit is used to forward I/O write cycles to the VGA palette registers on a
PCI controller. If this bit is set, then the PCI Host Bus Controller and all the PCI to PCI bridges between the PCI
Host Bus Controller and the PCI Controller are conﬁgured to forward these PCI I/O cycles. This bit may not be
combined with EFI_PCI_IO_ATTRIBUTE_VGA_IO orEFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO .

14.4. EFI PCI I/O Protocol 594Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 If this bit is set, then the PCI I/O cycles in the ranges 0x3B0-
0x3BB and 0x3C0-0x3DF are forwarded to the PCI controller using a 16-bit address decoder on ad-
dress bits 0..15. Address bits 16..31 must be zero. This bit is used to forward I/O cycles for a VGA
controller to a PCI controller. If this bit is set, then the PCI Host Bus Controller and all the PCI
to PCI bridges between the PCI Host Bus Controller and the PCI Controller are conﬁgured to for-
ward these PCI I/O cycles. This bit may not be combined with EFI_PCI_IO_ATTRIBUTE_VGA_IO
or EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO . Because EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
also includes the I/O range described by EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 , the
EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 bit is ignored if EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
is set.
EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO If this bit is set, then the PCI I/O cycles between
0x00000000 and 0x000000FF are forwarded to the PCI controller. This bit is used to forward I/O cycles for ISA
motherboard devices. If this bit is set, then the PCI Host Bus Controller and all the PCI to PCI bridges between
the PCI Host Bus Controller and the PCI Controller are conﬁgured to forward these PCI I/O cycles.
EFI_PCI_IO_ATTRIBUTE_ISA_IO If this bit is set, then the PCI I/O cycles between 0x100 and 0x3FF are for-
warded to the PCI controller using a 10-bit address decoder on address bits 0..9. Address bits 10..15 are not
decoded, and address bits 16..31 must be zero. This bit is used to forward I/O cycles for legacy ISA devices.
If this bit is set, then the PCI Host Bus Controller and all the PCI to PCI bridges between the PCI Host Bus
Controller and the PCI Controller are conﬁgured to forward these PCI I/O cycles.
EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO If this bit is set, then the PCI I/O write cycles for 0x3C6, 0x3C8,
and 0x3C9 are forwarded to the PCI controller using a 10-bit address decoder on address bits 0..9. Address bits
10..15 are not decoded, and address bits 16..31 must be zero. This bit is used to forward I/O write cycles to the
VGA palette registers on a PCI controller. If this bit is set, then the PCI Host Bus Controller and all the PCI to
PCI bridges between the PCI Host Bus Controller and the PCI Controller are conﬁgured to forward these PCI
I/O cycles.
EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY If this bit is set, then the PCI memory cycles between 0xA0000 and
0xBFFFF are forwarded to the PCI controller. This bit is used to forward memory cycles for a VGA frame buffer
on a PCI controller. If this bit is set, then the PCI Host Bus Controller and all the PCI to PCI bridges between
the PCI Host Bus Controller and the PCI Controller are conﬁgured to forward these PCI Memory cycles.
EFI_PCI_IO_ATTRIBUTE_VGA_IO If this bit is set, then the PCI I/O cycles in the ranges 0x3B0-0x3BB and
0x3C0-0x3DF are forwarded to the PCI controller using a 10-bit address decoder on address bits 0..9. Ad-
dress bits 10..15 are not decoded, and the address bits 16..31 must be zero. This bit is used to forward I/O
cycles for a VGA controller to a PCI controller. If this bit is set, then the PCI Host Bus Controller and all
the PCI to PCI bridges between the PCI Host Bus Controller and the PCI Controller are conﬁgured to forward
these PCI I/O cycles. Since EFI_PCI_IO_ATTRIBUTE_VGA_IO also includes the I/O range described by
EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO, the EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO bit is
ignored if EFI_PCI_IO_ATTRIBUTE_VGA_IO is set.
EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO If this bit is set, then the PCI I/O cycles in the ranges 0x1F0-
0x1F7 and 0x3F6-0x3F7 are forwarded to a PCI controller using a 16-bit address decoder on address bits 0..15.
Address bits 16..31 must be zero. This bit is used to forward I/O cycles for a Primary IDE controller to a PCI
controller. If this bit is set, then the PCI Host Bus Controller and all the PCI to PCI bridges between the PCI
Host Bus Controller and the PCI Controller are conﬁgured to forward these PCI I/O cycles.
EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO If this bit is set, then the PCI I/O cycles in the ranges 0x170-
0x177 and 0x376-0x377 are forwarded to a PCI controller using a 16-bit address decoder on address bits 0..15.
Address bits 16..31 must be zero. This bit is used to forward I/O cycles for a Secondary IDE controller to a PCI
EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE If this bit is set, then this platform supports chang-
ing the attributes of a PCI memory range so that the memory range is accessed in a write combining mode. This
14.4. EFI PCI I/O Protocol 595Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
bit is used to improve the write performance to a memory buffer on a PCI controller. By default, PCI memory
ranges are not accessed in a write combining mode.
EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED If this bit is set, then this platform supports changing the at-
tributes of a PCI memory range so that the memory range is accessed in a cached mode. By default, PCI memory
ranges are accessed noncached.
EFI_PCI_IO_ATTRIBUTE_IO If this bit is set, then the PCI device will decode the PCI I/O cycles that the device
is conﬁgured to decode.
EFI_PCI_IO_ATTRIBUTE_MEMORY If this bit is set, then the PCI device will decode the PCI Memory cycles
that the device is conﬁgured to decode.
EFI_PCI_IO_ATTRIBUTE_BUS_MASTER If this bit is set, then the PCI device is allowed to act as a bus master
on the PCI bus.
EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE If this bit is set, then this platform supports changing the at-
tributes of a PCI memory range so that the memory range is disabled, and can no longer be accessed. By default,
all PCI memory ranges are enabled.
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE If this bit is set, then the PCI controller is an embedded de-
vice that is typically a component on the system board. If this bit is clear, then this PCI controller is part of an
adapter that is populating one of the systems PCI slots.
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM If this bit is set, then the PCI option ROM described by the
RomImage andRomSize ﬁelds is not from ROM BAR of the PCI controller. If this bit is clear, then the RomIm-
ageandRomSize ﬁelds were initialized based on the PCI option ROM found through the ROM BAR of the PCI
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE If this bit is set, then the PCI controller is capable of
producing PCI Dual Address Cycles, so it is able to access a 64-bit address space. If this bit is not set, then the
PCI controller is not capable of producing PCI Dual Address Cycles, so it is only able to access a 32-bit address
space.
Controller and the PCI Controller are capable of producing PCI Dual Address Cycles. If any of them is not
capable of producing PCI Dual Address Cycles, attempt to perform Set or Enable operation using Attributes()
function with this bit set will fail with the EFI_UNSUPPORTED error code.
// EFI_PCI_IO_PROTOCOL_OPERATION
EfiPciIoOperationBusMasterRead,
EfiPciIoOperationBusMasterWrite,
EfiPciIoOperationBusMasterCommonBuffer,
EfiPciIoOperationMaximum
} EFI_PCI_IO_PROTOCOL_OPERATION;
EﬁPciIoOperationBusMasterRead A read operation from system memory by a bus master.
EﬁPciIoOperationBusMasterWrite A write operation to system memory by a bus master.
EﬁPciIoOperationBusMasterCommonBuffer Provides both read and write access to system memory by both the
processor and a bus master. The buffer is coherent from both the processor’s and the bus master’s point of view.
The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI conﬁguration, and DMA interfaces that are
used to abstract accesses to PCI controllers. There is one EFI_PCI_IO_PROTOCOL instance for each PCI con-
troller on a PCI bus. A device driver that wishes to manage a PCI controller in a system will have to retrieve the
14.4. EFI PCI I/O Protocol 596Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. A device handle for a PCI controller
will minimally contain an EFI Device Path Protocol instance and an EFI_PCI_IO_PROTOCOL instance.

The caller of EFI_PCI_IO_PROTOCOL.Map() must pay attention to the number of bytes that were mapped, and if
required, loop until the entire buffer has been transferred. The following is a list of the different bus mastering DMA
operations that are supported, and the sequence of EFI_PCI_IO_PROTOCOL interfaces that are used for each DMA
operation type.
Call EFI_PCI_IO_PROTOCOL.Map() for EﬁPciIoOperationBusMasterRead.
Program the DMA Bus Master with the DeviceAddress returned by Map() .
Start the DMA Bus Master.
Wait for DMA Bus Master to complete the read operation.
Call EFI-PCI-IO-PROTOCOL-Unmap() .
Call Map() for EﬁPciOperationBusMasterWrite.
Wait for DMA Bus Master to complete the write operation.
Perform a PCI controller speciﬁc read transaction to ﬂush all PCI write buffers (See PCI Speciﬁcation Section 3.2.5.2).
Call EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Flush() .
Call Unmap() .
Call EFI_PCI_IO_PROTOCOL.AllocateBuffer() . to allocate a common buffer.
Call Map() for EﬁPciIoOperationBusMasterCommonBuffer.
The common buffer can now be accessed equally by the processor and the DMA bus master.
Call Unmap().
Call EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.FreeBuffer() .
14.4.2 EFI_PCI_IO_PROTOCOL.PollMem()
Summary
Reads from the memory space of a PCI controller. Returns when either the polling exit criteria is satisﬁed or after a
Prototype
14.4. EFI PCI I/O Protocol 597Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef
);
This A pointer to the EFI PCI I/O Protocol instance. Type EFI_PCI_IO_PROTOCOL is deﬁned in EFI PCI I/O
Protocol .
Width Signiﬁes the width of the memory operations, deﬁned in EFI PCI I/O Protocol .
BarIndex The BAR index of the standard PCI Conﬁguration header to use as the base address for the memory
operation to perform. This allows all drivers to use BAR relative addressing. The legal range for this ﬁeld is 0..5.
However, the value EFI_PCI_IO_PASS_THROUGH_BAR can be used to bypass the BAR relative addressing
and pass Offset to the PCI Root Bridge I/O Protocol unchanged. Type EFI_PCI_IO_PASS_THROUGH_BAR
is deﬁned in EFI_PCI_IO_Protocol .
Offset The offset within the selected BAR to start the memory operation.
This function provides a standard way to poll a PCI memory location. A PCI memory read operation is performed
at the PCI memory address speciﬁed by BarIndex andOffset for the width speciﬁed by Width . The result of this PCI
memory read operation is stored in Result . This PCI memory read operation is repeated until either a timeout of Delay
100 ns units has expired, or ( Result & Mask) is equal to Value .
This function will always perform at least one memory access no matter how small Delay may be. If Delay is 0, then
IfWidth is not EﬁPciIoWidthUint8 ,EﬁPciIoWidthUint16 ,EﬁPciIoWidthUint32 , or EﬁPciIoWidthUint64 , then
memory width restrictions that a PCI controller on a platform might require. For example on some platforms, width
requests of EﬁPciIoWidthUint64 do not work.
EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED attribute set, then the transactions will follow the ordering rules
deﬁned by the processor architecture.
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EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
14.4.3 EFI_PCI_IO_PROTOCOL.PollIo()
Summary
Reads from the I/O space of a PCI controller. Returns when either the polling exit criteria is satisﬁed or after a deﬁned
duration.
Prototype
typedef
);
This A pointer to the EFI_PCI_IO_PROTOCOL instance. Type EFI_PCI_IO_PROTOCOL is deﬁned in See EFI PCI
Width Signiﬁes the width of the I/O operations. Type EFI_PCI_IO_PROTOCOL_WIDTH, deﬁned in EFI PCI I/O
Protocol .
BarIndex The BAR index of the standard PCI Conﬁguration header to use as the base address for the I/O operation to
perform. This allows all drivers to use BAR relative addressing. The legal range for this ﬁeld is 0..5. However,
the value EFI_PCI_IO_PASS_THROUGH_BAR can be used to bypass the BAR relative addressing and pass
Offset to the PCI Root Bridge I/O Protocol unchanged. Type EFI_PCI_IO_PASS_THROUGH_BAR is deﬁned
inEFI_PCI_IO_Protocol .
Offset The offset within the selected BAR to start the I/O operation.
This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is performed at the PCI I/O
address speciﬁed by BarIndex andOffset for the width speciﬁed by Width . The result of this PCI I/O read operation is
14.4. EFI PCI I/O Protocol 599Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
stored in Result . This PCI I/O read operation is repeated until either a timeout of Delay 100 ns units has expired, or
(Result & Mask ) is equal to Value .
This function will always perform at least one I/O access no matter how small Delay may be. If Delay is 0, then Result
will be returned with a status of EFI_SUCCESS even if Result does not match the exit criteria. If Delay expires, then
EFI_TIMEOUT is returned.
width restrictions that the PCI controller on a platform might require. For example on some platforms, width requests
ofEﬁPciIoWidthUint64 do not work.
EFI_UNSUPPORTED Offset is not valid for the PCI BAR speciﬁed by BarIndex.
14.4.4 EFI_PCI_IO_PROTOCOL.Mem.Read()
14.4.5 EFI_PCI_IO_PROTOCOL.Mem.Write()
Summary
Enable a PCI driver to access PCI controller registers in the PCI memory space.
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_MEM) (
);
This A pointer to the See EFI_PCI_IO_PROTOCOL instance. Type EFI_PCI_IO_PROTOCOL is deﬁned in EFI PCI

Summary
Prototype
typedef
);
Width Signiﬁes the width of the memory operations. Type EFI_PCI_IO_PROTOCOL_WIDTH, deﬁned in EFI PCI
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Count The number of memory operations to perform. Bytes moved is Width size * Count, starting at Offset.
data from.
TheMem.Read() , and Mem.Write() functions enable a driver to access controller registers in the PCI memory space.
The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width
issues which the bus, device, platform, or type of I/O might require. For example on some platforms, width requests
IfWidth isEﬁPciIoWidthUint8 ,EﬁPciIoWidthUint16 ,EﬁPciIoWidthUint32 , orEﬁPciIoWidthUint64 , then both
Address andBuffer are incremented for each of the Count operations performed.
IfWidth isEﬁPciIoWidthFifoUint8 ,EﬁPciIoWidthFifoUint16 ,EﬁPciIoWidthFifoUint32 , orEﬁPciIoWidthFifoUint64
, then only Buffer is incremented for each of the Count operations performed. The read or write operation is performed
IfWidth isEﬁPciIoWidthFillUint8 ,EﬁPciIoWidthFillUint16 ,EﬁPciIoWidthFillUint32 , orEﬁPciIoWidthFillUint64 ,
then only Address is incremented for each of the Count operations performed. The read or write operation is performed
EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED attribute set, then the transactions will follow the ordering rules de-
EFI_SUCCESS The data was read from or written to the PCI controller.
EFI_UNSUPPORTED The address range speciﬁed by Offset, Width, and Count is not valid for the
PCI BAR speciﬁed by BarIndex.
14.4.6 EFI_PCI_IO_PROTOCOL.Io.Read()
14.4.7 EFI_PCI_IO_PROTOCOL.Io.Write()
Summary
Enable a PCI driver to access PCI controller registers in the PCI I/O space.
Prototype
typedef
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);
This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. Type EFI_PCI_IO_PROTOCOL is de-
ﬁned in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL .
Count The number of I/O operations to perform. Bytes moved is Width size * Count, starting at Offset.
data from.
TheIo.Read() , and Io.Write() functions enable a driver to access PCI controller registers in PCI I/O space.
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14.4.8 EFI_PCI_IO_PROTOCOL.Pci.Read()
14.4.9 EFI_PCI_IO_PROTOCOL.Pci.Write()
Summary
Enable a PCI driver to access PCI controller registers in PCI conﬁguration space.
Prototype
typedef
);
This A pointer to the See EFI PCI I/O Protocol instance. Type EFI_PCI_IO_PROTOCOL is deﬁned in See EFI PCI
Offset The offset within the PCI conﬁguration space for the PCI controller.
Count The number of PCI conﬁguration operations to perform. Bytes moved is Width size * Count, starting at Offset.
data from.
ThePci.Read() andPci.Write() functions enable a driver to access PCI conﬁguration registers for the PCI controller.
I/O width issues which the bus, device, platform, or type of I/O might require. For example on some platforms, width
14.4. EFI PCI I/O Protocol 603Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 14.28 – continued from previous page
PCI conﬁguration header of the PCI controller.

14.4.10 EFI_PCI_IO_PROTOCOL.CopyMem()
Summary
Enables a PCI driver to copy one region of PCI memory space to another region of PCI memory space.
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM) (
IN UINT8 DestBarIndex,
IN UINT64 DestOffset,
IN UINT8 SrcBarIndex,
IN UINT64 SrcOffset,
);
This A pointer to the EFI_PCI_IO_PROTOCOL instance. Type EFI_PCI_IO_PROTOCOL is deﬁned in
EFI_PCI_IO_Protocol .
DestBarIndex The BAR index of the standard PCI Conﬁguration header to use as the base address for the memory
DestOffset The destination offset within the BAR speciﬁed by DestBarIndex to start the memory writes for the copy
operation. The caller is responsible for aligning the DestOffset if required.
SrcBarIndex The BAR index of the standard PCI Conﬁguration header to use as the base address for the memory
SrcOffset The source offset within the BAR speciﬁed by SrcBarIndex to start the memory reads for the copy opera-
tion. The caller is responsible for aligning the SrcOffset if required.
Count The number of memory operations to perform. Bytes moved is Width size * Count, starting at DestOffset and
SrcOffset.
The CopyMem() function enables a PCI driver to copy one region of PCI memory space to another region of PCI
memory space on a PCI controller. This is especially useful for video scroll operations on a memory mapped video
buffer.
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read/write transactions are performed to move the contents of the SrcOffset buffer to the DestOffset buffer. The
implementation must be reentrant, and it must handle overlapping SrcOffset andDestOffset buffers. This means that
the implementation of CopyMem() must choose the correct direction of the copy operation based on the type of overlap
that exists between the SrcOffset andDestOffset buffers. If either the SrcOffset buffer or the DestOffset buffer crosses
the top of the processor’s address space, then the result of the copy operation is unpredictable.
The contents of the DestOffset buffer on exit from this service must match the contents of the SrcOffset buffer on entry
to this service. Due to potential overlaps, the contents of the SrcOffset buffer may be modiﬁed by this service. The
• IfDestOffset >SrcOffset andDestOffset < (SrcOffset +Width size * Count ), then the data should be copied from
theSrcOffset buffer to the DestOffset buffer starting from the end of buffers and working toward the beginning
of the buffers.
• Otherwise, the data should be copied from the SrcOffset buffer to the DestOffset buffer starting from the begin-
ning of the buffers and working toward the end of the buffers.
EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
EFI_UNSUPPORTED The address range speciﬁed by DestOffset, Width, and Count is not valid
for the PCI BAR speciﬁed by DestBarIndex.
EFI_UNSUPPORTED The address range speciﬁed by SrcOffset, Width, and Count is not valid for
the PCI BAR speciﬁed by SrcBarIndex.
14.4.11 EFI_PCI_IO_PROTOCOL.Map()
Summary
Provides the PCI controller-speciﬁc addresses needed to access system memory.
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP) (
IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
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);
ﬁned in See EFI PCI I/O Protocol .
EFI_PCI_IO_PROTOCOL_OPERATION is deﬁned in See EFI PCI I/O Protocol .
DeviceAddress The resulting map address for the bus master PCI controller to use to access the hosts HostAddress.
Type EFI_PHYSICAL_ADDRESS is deﬁned in EFI_BOOT_SERVICES.AllocatePool() . This address cannot
be used by the processor to access the contents of the buffer speciﬁed by HostAddress .
Mapping A resulting value to pass to EFI-PCI-IO-PROTOCOL-Unmap() .
TheEFI_PCI_IO_PROTOCOL.Map() function provides the PCI controller-speciﬁc addresses needed to access system
memory. This function is used to map system memory for PCI bus master DMA accesses.
All PCI bus master accesses must be performed through their mapped addresses and such mappings must be freed with
EFI-PCI-IO-PROTOCOL-Unmap() when complete. If the bus master access is a single read or write data transfer,
then EﬁPciIoOperationBusMasterRead orEﬁPciIoOperation-BusMasterWrite is used and the range is unmapped to
complete the operation. If performing an EﬁPciIoOperationBusMasterRead operation, all the data must be present in
system memory before the Map() is performed. Similarly, if performing an EﬁPciIoOperation-BusMasterWrite, the
data cannot be properly accessed in system memory until Unmap() is performed.
Bus master operations that require both read and write access or require multiple host device interactions within the
same mapped region must use EﬁPciIoOperation-BusMasterCommonBuffer . However, only memory allocated via the
EFI_PCI_IO_PROTOCOL.AllocateBuffer() interface can be mapped for this operation type.
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14.4.12 EFI-PCI-IO-PROTOCOL-Unmap()
Summary
Completes the EFI_PCI_IO_PROTOCOL.Map() operation and releases any corresponding resources.
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP) (
);
This A pointer to the EFI_PCI_IO_PROTOCOL instance. Type EFI_PCI_IO_PROTOCOL is deﬁned in EFI PCI I/O
Protocol .

Summary
Prototype
typedef
);
Protocol .
anEﬁPciIoOperationBusMasterWrite , the data is committed to the target system memory. Any resources used for the
mapping are freed.
14.4.13 EFI_PCI_IO_PROTOCOL.AllocateBuffer()
Summary
Allocates pages that are suitable for an EﬁPciIoOperationBusMasterCommonBuffer mapping.
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER) (
);
This A pointer to the See EFI PCI I/O Protocol instance. Type EFI_PCI_IO_PROTOCOL is deﬁned in EFI PCI I/O
Protocol .
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MemoryType The type of memory to allocate, EﬁBootServicesData or EﬁRuntimeServicesData. Type
EFI_MEMORY_TYPE is deﬁned in EFI_PCI_IO_PROTOCOL.AllocateBuffer() .
Attributes The requested bit mask of attributes for the allocated range. Only
the attributes EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE, and
EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED may be used with this function. If any
other bits are set, then EFI_UNSUPPORTED is returned. This function may choose to ig-
nore this bit mask. The EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE, and
EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED attributes provide a hint to the implementation that
may improve the performance of the calling driver. The implementation may choose any default for the memory
attributes including write combining, cached, both, or neither as long as the allocated buffer can be seen equally
by both the processor and the PCI bus master.
The AllocateBuffer() function allocates pages that are suitable for an EﬁPciIoOperationBusMasterCommonBuffer
mapping. This means that the buffer allocated by this function must support simultaneous access by both the pro-
cessor and a PCI Bus Master. The device address that the PCI Bus Master uses to access the buffer can be retrieved
with a call to EFI_PCI_IO_PROTOCOL.Map() .
If the current attributes of the PCI controller has the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE bit set,
then when the buffer allocated by this function is mapped with a call to Map() , the device address that is returned by
Map() must be within the 64-bit device address space of the PCI Bus Master. The attributes for a PCI controller can
be managed by calling EFI_PCI_IO_PROTOCOL.Attributes() .
If the current attributes for the PCI controller has the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE bit clear,
Map() must be within the 32-bit device address space of the PCI Bus Master. The attributes for a PCI controller can
be managed by calling Attributes() .
EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are MEM-
ORY_WRITE_COMBINE andMEMORY_CACHED .
14.4.14 EFI_PCI_IO_PROTOCOL.FreeBuffer()
Summary
Frees memory that was allocated with EFI_PCI_IO_PROTOCOL.AllocateBuffer() .
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER) (
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);
Protocol .
14.4.15 EFI_PCI_IO_PROTOCOL.Flush()
Summary
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH) (
IN EFI_PCI_IO_PROTOCOL *This
);
Protocol .
memory.
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14.4.16 EFI_PCI_IO_PROTOCOL.GetLocation()
Summary
Retrieves this PCI controller’s current PCI bus number, device number, and function number.
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION) (
OUT UINTN *SegmentNumber,
OUT UINTN *BusNumber,
OUT UINTN *DeviceNumber,
OUT UINTN *FunctionNumber
);
Protocol .
SegmentNumber The PCI controller’s current PCI segment number.
BusNumber The PCI controller’s current PCI bus number.
DeviceNumber The PCI controller’s current PCI device number.
FunctionNumber The PCI controller’s current PCI function number.
TheGetLocation() function retrieves a PCI controller’s current location on a PCI Host Bridge. This is speciﬁed by a
PCI segment number, PCI bus number, PCI device number, and PCI function number. These values can be used with
the PCI Root Bridge I/O Protocol to perform PCI conﬁguration cycles on the PCI controller, or any of its peer PCI
controller’s on the same PCI Host Bridge.
EFI_SUCCESS The PCI controller location was returned.
EFI_INV ALID_PARAMETER SegmentNumber is NULL .
EFI_INV ALID_PARAMETER BusNumber is NULL .
EFI_INV ALID_PARAMETER DeviceNumber is NULL .
EFI_INV ALID_PARAMETER FunctionNumber is NULL .
14.4. EFI PCI I/O Protocol 610Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
14.4.17 EFI_PCI_IO_PROTOCOL.Attributes()
Summary
Performs an operation on the attributes that this PCI controller supports. The operations include getting the set of
supported attributes, retrieving the current attributes, setting the current attributes, enabling attributes, and disabling
attributes.
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES) (
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
OUT UINT64 *Result OPTIONAL
);
Protocol .
Operation The operation to perform on the attributes for this PCI controller. Type
EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION is deﬁned in “Related Deﬁnitions” below.
Attributes The mask of attributes that are used for Set, Enable, and Disable operations. The available attributes are
listed in See EFI PCI I/O Protocol .
Result A pointer to the result mask of attributes that are returned for the Get and Supported operations. This is an

Prototype
typedef
);
Protocol .
optional parameter that may be NULL for the Set, Enable, and Disable operations. The available attributes are
listed in EFI PCI I/O Protocol .
// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION
EfiPciIoAttributeOperationGet,
EfiPciIoAttributeOperationSet,
EfiPciIoAttributeOperationEnable,
EfiPciIoAttributeOperationDisable,
EfiPciIoAttributeOperationSupported,
EfiPciIoAttributeOperationMaximum
} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;
EﬁPciIoAttributeOperationGet Retrieve the PCI controller’s current attributes, and return them in Result. If Result
is NULL, then EFI_INV ALID_PARAMER is returned. For this operation, Attributes is ignored.
EﬁPciIoAttributeOperationSet Set the PCI controller’s current attributes to Attributes. If a bit is set in Attributes
that is not supported by this PCI controller or one of its parent bridges, then EFI_UNSUPPORTED is returned.
For this operation, Result is an optional parameter that may be NULL.
EﬁPciIoAttributeOperationEnable Enable the attributes speciﬁed by the bits that are set in Attributes for this PCI
controller. Bits in Attributes that are clear are ignored. If a bit is set in Attributes that is not supported by this
PCI controller or one of its parent bridges, then EFI_UNSUPPORTED is returned. For this operation, Result is
an optional parameter that may be NULL.
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EﬁPciIoAttributeOperationDisable Disable the attributes speciﬁed by the bits that are set in Attributes for this PCI
EﬁPciIoAttributeOperationSupported Retrieve the PCI controller’s supported attributes, and return them in Result.
If Result is NULL, then EFI_INV ALID_PARAMER is returned. For this operation, Attributes is ignored.
TheAttributes() function performs an operation on the attributes associated with this PCI controller. If Operation is
greater than or equal to the maximum operation value, then EFI_INVALID_PARAMETER is returned. If Operation is
GetorSupported , and Result isNULL , then EFI_INVALID_PARAMETER is returned. If Operation isSet,Enable , or
Disable for an attribute that is not supported by the PCI controller, then EFI_UNSUPPORTED is returned. Otherwise,
the operation is performed as described in “Related Deﬁnitions” and EFI_SUCCESS is returned. It is possible for this
function to return EFI_UNSUPPORTED even if the PCI controller supports the attribute. This can occur when the
PCI root bridge does not support the attribute. For example, if VGA I/O and VGA Memory transactions cannot be
forwarded onto PCI root bridge #2, then a request by a PCI VGA driver to enable the VGA_IO andVGA_MEMORY
bits will fail even though a PCI VGA controller behind PCI root bridge #2 is able to decode these transactions.
This function will also return EFI_UNSUPPORTED if more than one PCI controller on the same PCI root bridge
has already successfully requested one of the ISA addressing attributes. For example, if one PCI VGA controller had
already requested the VGA_IO andVGA_MEMORY attributes, then a second PCI VGA controller on the same root
bridge cannot succeed in requesting those same attributes. This restriction applies to the ISA-, VGA-, and IDE-related
EFI_SUCCESS The operation on the PCI controller’s attributes was completed. If the oper-
ation was GetorSupported , then the attribute mask is returned in Result.
EFI_INV ALID_PARAMETER Operation is greater than or equal to EﬁPciIoAttributeOperationMaximum .
EFI_INV ALID_PARAMETER Operation is Getand Result is NULL .
EFI_INV ALID_PARAMETER Operation is Supported and Result is NULL .
EFI_UNSUPPORTED Operation is Set, and one or more of the bits set in Attributes are not sup-
ported by this PCI controller or one of its parent bridges.
EFI_UNSUPPORTED Operation is Enable , and one or more of the bits set in Attributes are not
supported by this PCI controller or one of its parent bridges.
EFI_UNSUPPORTED Operation is Disable , and one or more of the bits set in Attributes are not
14.4.18 EFI_PCI_IO_PROTOCOL.GetBarAttributes()
Summary
Gets the attributes that this PCI controller supports setting on a BAR using
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES) (
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OUT VOID **Resources OPTIONAL
);
Protocol .
BarIndex The BAR index of the standard PCI Conﬁguration header to use as the base address for resource range.
The legal range for this ﬁeld is 0..5.
Supports A pointer to the mask of attributes that this PCI controller supports setting for this BAR with SetBarAt-
tributes(). The list of attributes is listed in See EFI PCI I/O Protocol . This is an optional parameter that may be
NULL.
Resources A pointer to the resource descriptors that describe the current conﬁguration of this BAR of the PCI con-
troller. This buffer is allocated for the caller with the Boot Service EFI_BOOT_SERVICES.AllocatePool() . It
is the caller’s responsibility to free the buffer with the Boot Service EFI_BOOT_SERVICES.FreePool() . See
“Related Deﬁnitions” below for the resource descriptors that may be used. This is an optional parameter that
may be NULL .
resources allocated to BAR of a PCI Controller. These are the QWORD Address Space Descriptor, and the End
Tag. The QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic or
ﬁxed resources. The conﬁguration of a BAR of a PCI Controller is described with one or more QWORD Address
Space Descriptors followed by an End Tag. The Tables below contain these two descriptor types. Please see the
ACPI Speciﬁcation for details on the ﬁeld values. The ACPI Speciﬁcation does not deﬁne how to the use the Address
Translation Offset for non-bridge devices. The UEFI Speciﬁcation is extending the deﬁnition of Address Translation
Offset to support systems that have different mapping for HostAddress and DeviceAddress. The deﬁnition of the
Address Space Granularity ﬁeld in the QWORD Address Space Descriptor differs from the ACPI Speciﬁcation and
the deﬁnition in the table below is the one that must be used.
Table 14.37: QWORD Address Space Descriptor
Byte Off-
setByte
0x03 0x01
set to 64.
0x0E 0x08 Address Range Minimum. Starting address of BAR.
0x16 0x08 Address Range Maximum. Ending address of BAR.
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Table 14.37 – continued from previous page
0x1E 0x08 Address Translation Offset. Offset to apply to the Starting address of a BAR
to convert it to a PCI address. This value is zero unless the HostAddress and
DeviceAddress for the BAR are different.
Table 14.38: End Tag
Byte Off-
setByte
The GetBarAttributes() function returns in Supports the mask of attributes that the PCI controller supports setting
for the BAR speciﬁed by BarIndex . It also returns in Resources a list of resource descriptors for the BAR speciﬁed
byBarIndex . Both Supports andResources are optional parameters. If both Supports andResources areNULL ,
then EFI_INVALID_PARAMETER is returned. It is the caller’s responsibility to free Resources with the Boot Service
EFI_BOOT_SERVICES.FreePool() when the caller is done with the contents of Resources . If there are not enough
resources to allocate Resources , then EFI_OUT_OF_RESOURCES is returned.

Byte Off-
setByte
If a bit is set in Supports , then the PCI controller supports this attribute type for the BAR speciﬁed by BarIndex , and
a call can be made to EFI_PCI_IO_PROTOCOL.SetBarAttributes() using that attribute type.
EFI_SUCCESS If Supports is not NULL , then the attributes that the PCI controller supports
are returned in Supports. If Resources is not NULL , then the resource de-
scriptors that the PCI controller is currently using are returned in Resources.
EFI_OUT_OF_RESOURCES There are not enough resources available to allocate Resources.
14.4.19 EFI_PCI_IO_PROTOCOL.SetBarAttributes()
Summary
Sets the attributes for a range of a BAR on a PCI controller.
Prototype
typedef
(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES) (
IN OUT UINT64 *Offset,
IN OUT UINT64 *Length
);
Protocol .
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Attributes The mask of attributes to set for the resource range speciﬁed by BarIndex, Offset, and Length.
BarIndex The BAR index of the standard PCI Conﬁguration header to use as the base address for the resource range.
Offset A pointer to the BAR relative base address of the resource range to be modiﬁed by the attributes speciﬁed by
Attributes. On return, Offset will be set to the actual base address of the resource range. Not all resources can
be set to a byte boundary, so the actual base address may differ from the one passed in by the caller.
Length A pointer to the length of the resource range to be modiﬁed by the attributes speciﬁed by Attributes. On
return, Length will be set to the actual length of the resource range. Not all resources can be set to a byte
boundary, so the actual length may differ from the one passed in by the caller.
TheSetBarAttributes() function sets the attributes speciﬁed in Attributes for the PCI controller on the resource range
speciﬁed by BarIndex ,Offset , and Length . Since the granularity of setting these attributes may vary from resource
type to resource type, and from platform to platform, the actual resource range and the one passed in by the caller may
differ. As a result, this function may set the attributes speciﬁed by Attributes on a larger resource range than the caller
requested. The actual range is returned in Offset andLength . The caller is responsible for verifying that the actual
range for which the attributes were set is acceptable.
If the attributes are set on the PCI controller, then the actual resource range is returned in Offset andLength , and
EFI_SUCCESS is returned. Many of the attribute types also require that the state of the PCI Host Bus Controller and
the state of any PCI to PCI bridges between the PCI Host Bus Controller and the PCI Controller to be modiﬁed. This
function will only return EFI_SUCCESS is all of these state changes are made. The PCI Controller may support a
combination of attributes, but unless the PCI Host Bus Controller and the PCI to PCI bridges also support that same
combination of attributes, then this call will return an error.
If the attributes speciﬁed by Attributes , or the resource range speciﬁed by BarIndex ,Offset , and Length are not
supported by the PCI controller, then EFI_UNSUPPORTED is returned. The set of supported attributes for the PCI
controller can be found by calling EFI_PCI_IO_PROTOCOL.GetBarAttributes() .
If either Offset orLength isNULL then EFI_INVALID_PARAMETER is returned.
EFI_SUCCESS The set of attributes speciﬁed by Attributes for the resource range speciﬁed
by BarIndex, Offset, and Length were set on the PCI controller, and the
actual resource range is returned in Offset and Length.
EFI_UNSUPPORTED The set of attributes speciﬁed by Attributes is not supported by the PCI
controller for the resource range speciﬁed by BarIndex, Offset, and Length.
EFI_INV ALID_PARAMETER Offset is NULL .
EFI_INV ALID_PARAMETER Length is NULL .
speciﬁed by BarIndex, Offset, and Length.
14.4. EFI PCI I/O Protocol 615Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
14.4.20 PCI Device Paths
AnEFI_PCI_IO_PROTOCOL must be installed on a handle for its services to be available to PCI device drivers. In
addition to the EFI_PCI_IO_PROTOCOL , anEFI Device Path Protocol must also be installed on the same handle
(see chapter 9).
system, additional device path nodes may precede this ACPI Device Path Node. A PCI device path is described with
PCI Device Path Nodes. There will be one PCI Device Path node for the PCI controller itself, and one PCI Device
Path Node for each PCI to PCI Bridge that is between the PCI controller and the PCI Root Bridge.
Table PCI Device 7, Function 0 on PCI Root Bridge 0 shows an example device path for a PCI controller that is
path consists of an ACPI Device Path Node, a PCI Device Path Node, and a Device Path End Structure. The _HID and
_UID must match the ACPI table description of the PCI Root Bridge. The shorthand notation for this device path is:
ACPI(PNP0A03,0)/PCI(7,0)
Table 14.41: PCI Device 7, Function 0 on PCI Root Bridge 0
Byte Off-
setByte
0x12 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x13 0x01 0xFF Sub type - End of Entire Device Path
0x14 0x02 0x04 Length - 0x04 bytes
Table PCI Device 7, Function 0 behind PCI to PCI bridge shows an example device path for a PCI controller that
is located behind a PCI to PCI bridge at PCI device number 0x07 and PCI function 0x00. The PCI to PCI bridge is
directly attached to a PCI root bridge, and it is at PCI device number 0x05 and PCI function 0x00. This device path
consists of an ACPI Device Path Node, two PCI Device Path Nodes, and a Device Path End Structure. The _HID and
ACPI(PNP0A03,0)/PCI(5,0)/PCI(7,0).
Table 14.42: PCI Device 7, Function 0 behind PCI to PCI bridge
Byte Off-
setByte
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Table 14.42 – continued from previous page
0x11 0x01 0x05 PCI Device
0x12 0x01 0x01 Generic Device Path Header - Type Hardware Device Path
0x13 0x01 0x01 Sub type - PCI
0x16 0x01 0x00 PCI Function
0x17 0x01 0x07 PCI Device
14.4.21 PCI Option ROMs
EFI takes advantage of both the PCI Firmware Speciﬁcation and the PE/COFF Speciﬁcation to store EFI images in a
PCI Option ROM. There are several rules that must be followed when constructing a PCI Option ROM:
• A PCI Option ROM can be no larger than 16 MiB.
• A PCI Option ROM may contain one or more images.
• Each image must being on a 512-byte boundary.
• Each image must be an even multiple of 512 bytes in length. This means that images that are not an even
multiple of 512 bytes in length must be padded to the next 512-byte boundary.
• Legacy Option ROM images begin with a Standard PCI Expansion ROM Header ( Standard PCI Expansion

ROM Header (Example from PCI Firmware Speciﬁcation 3.0) (example-from-pci-ﬁrmware-speciﬁcation-3.0) .
• EFI Option ROM images begin with an EFI PCI Expansion ROM Header ( Recommended PCI Device Driver
Layout ).
• Each image must contain a PCIR data structure in the ﬁrst 64 KiB of the image.
• The image data for an EFI Option ROM image must begin in the ﬁrst 64 KiB of the image.
• The image data for an EFI Option ROM image must be a PE/COFF image or a compressed PE/COFF image
following the UEFI Compression Algorithm, and referencing Compression Source Code for the Compression
Source Code.
• The PCIR data structure must begin on a 4-byte boundary.
• If the PCI Option ROM contains a Legacy Option ROM image, it must be the ﬁrst image.
• The images are placed in the PCI Option ROM in order from highest to lowest priority. This priority is used to
build the ordered list of Driver Image Handles that are produced by the Bus Speciﬁc Driver Override Protocol
for a PCI Controller.
• xxxx When PCI device provides an EFI option ROM that is signed in accordance with Chapter 27, use of UEFI
Compression Algorithm storage option is preferred. When performing signature validation upon compressed
driver, the size returned by EFI_DECOMPRESS_PROTOCOL.GetInfo() will be used as driver size and input
14.4. EFI PCI I/O Protocol 617Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
to signature validation process. Thus any post-driver padding required to reach exact multiple of 512 bytes per
Unsigned PCI Driver Image Layout is ignored by signature validation.
• When PCI device provides an EFI option ROM that is signed in accordance with Chapter 27 and stored un-
compressed, the end of the driver for signature validation will be the assumed to be the 512-byte boundary
indicated by the ‘Initialization Size’ value in the EFI PCI Expansion ROM Header (Table EFI PCI Expansion
ROM Header ). As the signed driver may not exactly ﬁll the indicated ‘Initialization Size’, it is recommended
that the value ‘Offset to EFI Image’ (also Table EFI PCI Expansion ROM Header ) be adjusted to ensure the
last byte of the signed, uncompressed driver, coincides with the end of the ROM as indicated by ‘Initialization
Size’. And any required padding bytes are to be inserted ahead of the signed uncompressed driver image.
There are several options available when building a PCI option ROM for a PCI adapter. A PCI Option ROM can choose
to support only a legacy PC-AT platform, only an EFI compliant platform, or both. This ﬂexibility allows a migration
path from adapters that support only legacy PC-AT platforms, to adapters that support both PC-AT platforms and
EFI compliant platforms, to adapters that support only EFI compliant platforms. The following is a list of the image
combinations that may be placed in a PCI option ROM. This is not an exhaustive list. Instead, it provides what will
likely be the most common PCI option ROM layouts. EFI complaint system ﬁrmware must work with all of these PCI
option ROM layouts, plus any other layouts that are possible within the PCI Firmware Speciﬁcation. The format of a
Legacy Option ROM image is deﬁned in the PCI Firmware Speciﬁcation.
• Legacy Option ROM image
• IA-32 UEFI driver
• x64 UEFI driver
• AArch32 UEFI driver
• AArch64 UEFI driver
• RISCV32 UEFI driver
• RISCV64 UEFI driver
• RISCV128 UEFI driver
• LoongArch32 UEFI driver
• LoongArch64 UEFI driver
• Legacy Option ROM image + x64 UEFI driver
• Legacy Option ROM image + x64 UEFI driver + AArch64 UEFI driver
• x64 UEFI driver + AArch64 UEFI driver
• Itanium Processor Family UEFI driver
• EBC Driver
In addition to combinations of UEFI drivers with different processor binding, it is also possible to include multiple
drivers of different function but the same processor binding. When processing option ROM contents, all drivers of
appropriate processor binding type must be loaded and added to ordered list of drivers previously mentioned.
It is also possible to place a application written to this speciﬁcation in a PCI Option ROM. However, the PCI Bus
Driver will ignore these images. The exact mechanism by which applications can be loaded and executed from a PCI
Option ROM is outside the scope of this document.
Table 14.43: Standard PCI Expansion ROM Header (Example from PCI
Firmware Speciﬁcation 3.0)
Offset Byte
LengthValue Description
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Table 14.43 – continued from previous page
0x00 1 0x55 ROM Signature, byte 1
0x01 1 0xAA ROM Signature, byte 2
0x02-
0x1722 XX Reserved per processor architecture unique data
0x18-
0x192 XX Pointer to PCIR Data Structure
Table 14.44: PCI Expansion ROM Code Types (Example from PCI
Code Type Description
0x00 IA-32, PC-AT compatible
0x01 Open Firmware standard for PCI
0x02 Hewlett-Packard PA RISC
0x03 EFI Image
0x04-0xFF Reserved
Table 14.45: EFI PCI Expansion ROM Header
0x02 2 XXXX Initialization Size - size of this image in units of 512 bytes. The size in-
cludes this header.
0x04 4 0x0EF1 Signature from EFI image header
0x08 2 XX Subsystem value for EFI image header
0x0a 2 XX Machine type from EFI image header
0x0c 2 XX
Compression type
0x0000 - The image is uncompressed
0x0001 - The image is compressed. See the UEFI Compression Algorithm
andCompression Source Code .
0x0002 - 0xFFFF - Reserved
0x0e 8 0x00 Reserved
0x16 2 XX Offset to EFI Image
0x18 2 XX Offset to PCIR Data Structure
14.4.22 PCI Bus Driver Responsibilities
A PCI Bus Driver must scan a PCI Option ROM for PCI Device Drivers. If a PCI Option ROM is found during PCI
Enumeration, then a copy of the PCI Option ROM is placed in a memory buffer. The PCI Bus Driver will use the
memory copy of the PCI Option ROM to search for UEFI drivers after PCI Enumeration. The PCI Bus Driver will
search the list of images in a PCI Option ROM for the ones that have a Code Type of 0x03 in the PCIR Data Structure,
and a Signature of 0xEF1 in the EFI PCI Expansion ROM Header. Then, it will examine the Subsystem Type of the EFI
PCI Expansion ROM Header. If the Subsystem Type is IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER (11)
orIMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER (12), then the PCI Bus Driver can load the PCI Device Driver
from the PCI Option ROM. The Offset to EFI Image Header ﬁeld of the EFI PCI Expansion ROM Header is used
to get a pointer to the beginning of the PE/COFF image in the PCI Option ROM. The PE/COFF image may have
14.4. EFI PCI I/O Protocol 619Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
been compressed using the UEFI Compression Algorithm. If it has been compressed, then the PCI Bus Driver must
decompress the driver to a memory buffer. The Boot Service EFI_BOOT_SERVICES.LoadImage() can then be used
to load the driver. All UEFI driver images discovered in the PCI Option ROM and meeting these requirements must
be processed and loaded via LoadImage() . If the platform does not support the Machine Type of the driver, then
LoadImage() may fail.
It is the PCI Bus Driver’s responsibility to verify that the Expansion ROM Header and PCIR Data Structure are valid.
It is the responsibly of the Boot Service LoadImage() to verify that the PE/COFF image is valid. The Boot Service
LoadImage() may fail for several reasons including a corrupt PE/COFF image or an unsupported Machine Type.
If a PCI Option ROM contains one or more UEFI images, then the PCI Bus Driver must install an instance of the
EFI_LOAD_FILE2_PROTOCOL on the PCI controller handle. Then, when the PCI Bus Driver loads a PE/COFF
image from a PCI Option ROM using the Boot Service LoadImage() , the PCI Bus Driver must provide the device
path of the image being loaded. The device path of an image loaded from a PCI Option ROM must be the device
path to the PCI Controller to which the PCI Option ROM is attached followed by a Relative Offset Range node. The
Starting Offset ﬁeld of the Relative Offset Range node must be the byte offset from the beginning of the PCI Option
ROM to the beginning of the EFI Option ROM image, and the Ending Offset ﬁeld of the Relative Offset Range node
must be the byte offset from the beginning of the PCI Option ROM to the end of the EFI Option ROM image. The
table below shows an example device path for an EFI driver loaded from a PCI Option ROM. The EFI Driver starts at
offset 0x8000 into the PCI Option ROM and is 0x2000 bytes long. The shorthand notation for this device path is:
PciRoot(0)/PCI(5,0)/PCI(7,0)/ Offset(0x8000,0x9FFF)
Table 14.46: Device Path for an EFI Driver loaded from PCIO ption
ROM
Byte Off-
setByte

ROM
Byte Off-
setByte
0x18 0x01 0x04 Generic Device Path Header - Type Media Device Path
0x19 0x01 0x08 Sub type - Relative Offset Range
0x1A 0x02 0x14 Length - 0x14 bytes
0x1C 0x08 0x8000 Start Address - Offset into PCI Option ROM
0x24 0x08 0x9FFF End Address - Offset into PCI Option ROM
0x2C 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x2D 0x01 0xFF Sub type - End of Entire Device Path
0x2E 0x02 0x04 Length - 0x04 bytes
14.4. EFI PCI I/O Protocol 620Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The PCI Option ROM search may produce one or more Driver Image Handles for the PCI Controller that is associated
with the PCI Option ROM. The PCI Bus Driver is responsible for producing a Bus Speciﬁc Driver Override Protocol
instance for every PCI Controller has a PCI Option ROM that contains one or more UEFI Drivers. The Bus Speciﬁc
Driver Override Protocol produces an ordered list of Driver Image Handles. The order that the UEFI Drivers are
placed in the PCI Option ROM is the order of Driver Image Handles that must be returned by the Bus Speciﬁc Driver
Override Protocol. This gives the party that builds the PCI Option ROM control over the order that the drivers are used
in the Boot Service EFI_BOOT_SERVICES.ConnectController() .
14.4.23 PCI Device Driver Responsibilities
A PCI Device Driver should not be designed to care where it is stored. It can reside in a PCI Option ROM, the system’s
motherboard ROM, a hard drive, a CD-ROM drive, etc. All PCI Device Drivers are compiled and linked to generate
a PE/COFF image. When a PE/COFF image is placed in a PCI Option ROM, it must follow the rules outlined in See
PCI Option ROMs . The recommended image layout is to insert an EFI PCI Expansion ROM Header and a PCIR Data
Structure in front of the PE/COFF image, and pad the entire image up to the next 512-byte boundary. See Unsigned
PCI Driver Image Layout shows the format of a single PCI Device Driver that can be added to a PCI Option ROM.
Following are recommended layouts and ﬂow charts for various types of driver signage and compression states for
PCI device driver images. See Unsigned PCI Driver Image Layout shows an unsigned layout.
Fig. 14.15: Unsigned PCI Driver Image Layout
Figures Signed and Compressed PCI Driver Image Flow andSigned and Compressed PCI Driver Image Flow show a
signed and compressed PCI device driver image ﬂow chart and layout, respectively.
Figure Signed but not Compressed PCI Driver Image Flow and Figure Signed and Uncompressed PCI Driver Image
Layout show a signed but not compressed ﬂow chart and a signed and uncompressed PCI device driver image layout,
respectively.
The ﬁeld values for the EFI PCI Expansion ROM Header and the PCIR Data Structure would be as follows in this
recommended PCI Driver image layout. An image must start at a 512-byte boundary, and the end of the image must
be padded to the next 512-byte boundary.
14.4. EFI PCI I/O Protocol 621Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 14.16: Signed and Compressed PCI Driver Image Flow
Fig. 14.17: Signed and Compressed PCI Driver Image Layout
14.4. EFI PCI I/O Protocol 622Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 14.18: Signed but not Compressed PCI Driver Image Flow
Fig. 14.19: Signed and Uncompressed PCI Driver Image Layout
14.4. EFI PCI I/O Protocol 623Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 14.47: Recommended PCI Device Driver Layout
cludes this header
0x08 2
XX
0x0B
0x0CSubsystem Value from the PCI Driver’s PE/COFF Image Header
Subsystem Value for an EFI Boot Service Driver
Subsystem Value for an EFI Runtime Driver
0x0a 2
XX
0x014C
0x0200
0x0EBC
0x8664
0x01c2
0xAA64Machine type from the PCI Driver’s PE/COFF Image Header
IA-32 Machine Type
Itanium processor type
EFI Byte Code (EBC) Machine Type
X64 Machine Type
ARM Machine Type
ARM 64-bit Machine Type
0x0C 2
XXXX
0x0000
0x0001Compression Type
Uncompressed
Compressed following the UEFI Compression Algorithm .
0x0E 8 0x00 Reserved
0x16 2 0x0034 Offset to EFI Image
0x18 2 0x001C Offset to PCIR Data Structure
0x1A 2 0x0000 Padding to align PCIR Data Structure on a 4 byte boundary
0x1C 4 ‘PCIR’ PCIR Data Structure Signature
0x20 2 XXXX Vendor ID from the PCI Controller’s Conﬁguration Header
0x22 2 XXXX Device ID from the PCI Controller’s Conﬁguration Header
0x24 2 0x0000 Reserved
0x26 2 0x0018 The length if the PCIR Data Structure in bytes
0x28 1 0x00 PCIR Data Structure Revision. Value for PCI 2.2 Option ROM
0x29 3 XXXX Class Code from the PCI Controller’s Conﬁguration Header
0x2C 2 XXXX Code Image Length in units of 512 bytes. Same as Initialization Size
0x2E 2 XXXX Revision Level of the Code/Data. This ﬁeld is ignored
0x30 1 0x03 Code Type
0x31 1 XX Indicator. Bit 7 clear means another image follows. Bit 7 set means that this
image is the last image in the PCI Option ROM. Bits 0-6 are reserved.
0x00
0x80Additional images follow this image in the PCI Option ROM This image is
the last image in the PCI Option ROM
0x32 2 0x0000 Reserved
0x34 X XXXX The beginning of the PCI Device Driver’s PE/COFF Image
14.4. EFI PCI I/O Protocol 624Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
14.4.24 Nonvolatile Storage
A PCI adapter may contain some form of nonvolatile storage. Since there are no standard access mechanisms for non-
volatile storage on PCI adapters, the PCI I/O Protocol does not provide any services for nonvolatile storage. However,
a PCI Device Driver may choose to implement its own access mechanisms. If there is a private channel between a PCI
Controller and a nonvolatile storage device, a PCI Device Driver can use it for conﬁguration options or vital product
data.
Note :The ﬁelds RomImage and RomSize in the PCI I/O Protocol do not provide direct access to the PCI Option ROM
on a PCI adapter. Instead, they provide access to a copy of the PCI Option ROM in memory .If the contents of the
RomImage are modiﬁed, only the memory copy is updated .If a vendor wishes to update the contents of a PCI Option
ROM, they must provide their own utility or driver to perform this task. There is no guarantee that the BAR for the
PCI Option ROM is valid at the time that the utility or driver may execute, so the utility or driver must provide the
code required to gain write access to the PCI Option ROM contents. The algorithm for gaining write access to a PCI
Option ROM is both platform speciﬁc and adapter speciﬁc, so it is outside the scope of this document .
14.4.25 PCI Hot-Plug Events
It is possible to design a PCI Bus Driver to work with PCI Bus that conforms to the PCI Hot-Plug Speciﬁcation. There
are two levels of functionality that could be provided in the preboot environment. The ﬁrst is to initialize the PCI
Hot-Plug capable bus so it can be used by an operating system that also conforms to the PCI Hot-Plug Speciﬁcation.
This only affects the PCI Enumeration that is performed in either the PCI Bus Driver’s initialization, or a ﬁrmware
component that executes prior to the PCI Bus Driver’s initialization. None of the PCI Device Drivers need to be aware
of the fact that a PCI Controller may exist in a slot that is capable of a hot-plug event. Also, the addition, removal, and
replacement of PCI adapters in the preboot environment would not be allowed.
The second level of functionality is to actually implement the full hot-plug capability in the PCI Bus Driver. This
is not recommended because it adds a great deal of complexity to the PCI Bus Driver design with very little
added value. However, there is nothing about the PCI Driver Model that would preclude this implementation. It
would require using an event based periodic timer to monitor the hot-plug capable slots, and take advantage of
theEFI_BOOT_SERVICES.ConnectController() andEFI_BOOT_SERVICES.DisconnectController() Boot Services
to dynamically start and stop the drivers that manage the PCI controller that is being added, removed, or replaced. If
theEFI_BOOT_SERVICES.DisconnectController() Boot Service fails it must be retried via a periodic timer.
14.4. EFI PCI I/O Protocol 625CHAPTER
FIFTEEN
PROTOCOLS — SCSI DRIVER MODELS AND BUS SUPPORT

FIFTEEN
The intent of this chapter is to specify a method of providing direct access to SCSI devices. These protocols provide
services that allow a generic driver to produce the Block I/O protocol for SCSI disk devices, and allows an EFI utility to
issue commands to any SCSI device. The main reason to provide such an access is to enable S.M.A.R.T. functionality
during POST (i.e., issuing Mode Sense, Mode Select, and Log Sense to SCSI devices). This is accomplished by
using a generic API such as SCSI Pass Thru. The use of this method will enable additional functionality in the future
without modifying the EFI SCSI Pass Thru driver. SCSI Pass Thru is not limited to SCSI channels. It is applicable to
all channel technologies that utilize SCSI commands such as SCSI, ATAPI, and Fibre Channel. This chapter describes
the SCSI Driver Model. This includes the behavior of SCSI Bus Drivers, the behavior of SCSI Device Drivers, and a
detailed description of the SCSI I/O Protocol. This chapter provides enough material to implement a SCSI Bus Driver,
and the tools required to design and implement SCSI Device Drivers. It does not provide any information on speciﬁc
SCSI devices.
15.1 SCSI Driver Model Overview
The EFI SCSI Driver Stack includes the SCSI Pass Thru Driver, SCSI Bus Driver and individual SCSI Device Drivers.
SCSI Pass Thru Driver : A SCSI Pass Through Driver manages a SCSI Host Controller that contains one or more
SCSI Buses. It creates SCSI Bus Controller Handles for each SCSI Bus, and attaches Extended SCSI Pass Thru
Protocol and Device Path Protocol to each handle the driver produced. Please refer to Extended SCSI Pass Thru
Protocol and Appendix G. Using the EFI Extended SCSI Pass Thru Protocol .
SCSI Bus Driver : A SCSI Bus Driver manages a SCSI Bus Controller Handle that is created by SCSI Pass Thru
Driver. It creates SCSI Device Handles for each SCSI Device Controller detected during SCSI Bus Enumeration, and
attaches SCSI I/O Protocol and Device Path Protocol to each handle the driver produced.
SCSI Device Driver : A SCSI Device Driver manages one kind of SCSI Device. Device handles for SCSI Devices are
created by SCSI Bus Drivers. A SCSI Device Driver could be a bus driver itself, and may create child handles. But
most SCSI Device Drivers will be device drivers that do not create new handles. For the pure device driver, it attaches
protocol instance to the device handle of the SCSI Device. These protocol instances are I/O abstractions that allow
the SCSI Device to be used in the pre-boot environment. The most common I/O abstractions are used to boot an EFI
compliant OS.
626Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
15.2 SCSI Bus Drivers
A SCSI Bus Driver manages a SCSI Bus Controller Handle. A SCSI Bus Controller Handle is created by a SCSI
Pass Thru Driver and is abstracted in software with the Extended SCSI Pass Thru Protocol. A SCSI Bus Driver will
manage handles that contain this protocol. The Figure below, Device Handle for a SCSI Bus Controller , shows an
example device handle for a SCSI Bus handle. It contains a Device Path Protocol instance and a Extended SCSI Pass
Thru Protocol Instance.
Fig. 15.1: Device Handle for a SCSI Bus Controller
15.2.1 Driver Binding Protocol for SCSI Bus Drivers
The Driver Binding Protocol contains three services. These are Supported() ,Start() , and Stop() .Supported() tests
to see if the SCSI Bus Driver can manage a device handle. A SCSI Bus Driver can only manage device handle that
contain the Device Path Protocol and the Extended SCSI Pass Thru Protocol, so a SCSI Bus Driver must look for these
two protocols on the device handle that is being tested.
TheStart() function tells the SCSI Bus Driver to start managing a device handle. The device handle should support
the protocols shown in Figure Device Handle for a SCSI Bus Controller . The Extended SCSI Pass Thru Protocol
provides information about a SCSI Channel and the ability to communicate with any SCSI devices attached to that
SCSI Channel.
The SCSI Bus Driver has the option of creating all of its children in one call to Start() , or spreading it across several
calls to Start() . In general, if it is possible to design a bus driver to create one child at a time, it should do so to support
the rapid boot capability in the UEFI Driver Model. Each of the child device handles created in Start() must contain
a Device Path Protocol instance, and a SCSI I/O protocol instance. The SCSI I/O Protocol is described in EFI SCSI
I/O Protocol and Section 14.4 . The format of device paths for SCSI Devices is described in SCSI Device Paths . The
Figure below, Child Handle Created by a SCSI Bus Driver , shows an example child device handle that is created by
a SCSI Bus Driver for a SCSI Device.
A SCSI Bus Driver must perform several steps to manage a SCSI Bus.
1. Scan for the SCSI Devices on the SCSI Channel that connected to the SCSI Bus Controller. If a request is being
made to scan only one SCSI Device, then only looks for the one speciﬁed. Create a device handle for the SCSI
Device found.
2. Install a Device Path Protocol instance and a SCSI I/O Protocol instance on the device handle created for each
SCSI Device.
TheStop() function tells the SCSI Bus Driver to stop managing a SCSI Bus. The Stop() function can destroy one or
more of the device handles that were created on a previous call to Start() . If all of the child device handles have been
15.2. SCSI Bus Drivers 627Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 15.2: Child Handle Created by a SCSI Bus Driver
destroyed, then Stop() will place the SCSI Bus Controller in a quiescent state. The functionality of Stop() mirrors
Start() .
15.2.2 SCSI Enumeration
The purpose of the SCSI Enumeration is only to scan for the SCSI Devices attached to the speciﬁc SCSI channel. The
SCSI Bus driver need not allocate resources for SCSI Devices (like PCI Bus Drivers do), nor need it connect a SCSI
Device with its Device Driver (like USB Bus Drivers do). The details of the SCSI Enumeration is implementation
speciﬁc, thus is out of the scope of this document.
15.3 SCSI Device Drivers
SCSI Device Drivers manage SCSI Devices. Device handles for SCSI Devices are created by SCSI Bus Drivers. A
SCSI Device Driver could be a bus driver itself, and may create child handles. But most SCSI Device Drivers will be
device drivers that do not create new handles. For the pure device driver, it attaches protocol instance to the device
handle of the SCSI Device. These protocol instances are I/O abstractions that allow the SCSI Device to be used in the
pre-boot environment. The most common I/O abstractions are used to boot an EFI compliant OS.
15.3.1 Driver Binding Protocol for SCSI Device Drivers
to see if the SCSI Device Driver can manage a device handle. A SCSI Device Driver can only manage device handle
that contain the Device Path Protocol and the SCSI I//O Protocol, so a SCSI Device Driver must look for these two
protocols on the device handle that is being tested. In addition, it needs to check to see if the device handle represents
a SCSI Device that SCSI Device Driver knows how to manage. This is typically done by using the services of the
SCSI I/O Protocol to see whether the device information retrieved is supported by the device driver.
TheStart() function tells the SCSI Device Driver to start managing a SCSI Device. A SCSI Device Driver could be a
bus driver itself, and may create child handles. But most SCSI Device Drivers will be device drivers that do not create
new handles. For the pure device driver, it installs one or more addition protocol instances on the device handle for the
15.3. SCSI Device Drivers 628Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheStop() function mirrors the Start() function, so the Stop() function completes any outstanding transactions to the
SCSI Device and removes the protocol interfaces that were installed in Start() .
15.4 EFI SCSI I/O Protocol
This section deﬁnes the EFI SCSI I/O protocol. This protocol is used by code, typically drivers, running in the EFI
boot services environment to access SCSI devices. In particular, functions for managing devices on SCSI buses are
deﬁned here.
The interfaces provided in the EFI_SCSI_IO_PROTOCOL are for performing basic operations to access SCSI devices.
15.4.1 EFI_SCSI_IO_PROTOCOL
This section provides a detailed description of the EFI_SCSI_IO_PROTOCOL .
Summary
Provides services to manage and communicate with SCSI devices.
GUID
#define EFI_SCSI_IO_PROTOCOL_GUID \
{0x932f47e6,0x2362,0x4002,\
{0x80,0x3e,0x3c,0xd5,0x4b,0x13,0x8f,0x85}}
typedef struct _EFI_SCSI_IO_PROTOCOL {
EFI_SCSI_IO_PROTOCOL_GET_DEVICE_TYPE GetDeviceType;
EFI_SCSI_IO_PROTOCOL_GET_DEVICE_LOCATION GetDeviceLocation;
EFI_SCSI_IO_PROTOCOL_RESET_BUS ResetBus;
EFI_SCSI_IO_PROTOCOL_RESET_DEVICE ResetDevice;

Summary
GUID
EFI_SCSI_IO_PROTOCOL_EXECUTE_SCSI_COMMAND ExecuteScsiCommand;
} EFI_SCSI_IO_PROTOCOL;
GetDeviceType Retrieves the information of the device type which the SCSI device belongs to
EFI_SCSI_IO_PROTOCOL.GetDeviceType() .
GetDeviceLocation Retrieves the device location information in the SCSI bus
EFI_SCSI_IO_PROTOCOL.GetDeviceLocation() .
ResetBus Resets the entire SCSI bus the SCSI device attaches to EFI_SCSI_IO_PROTOCOL.ResetBus() .
ResetDevice Resets the SCSI Device that is speciﬁed by the device handle the SCSI I/O protocol attaches
EFI_SCSI_IO_PROTOCOL.ResetDevice() .
ExecuteScsiCommand Sends a SCSI command to the SCSI device and waits for the execution completion until an
exit condition is met, or a timeout occurs EFI_SCSI_IO_PROTOCOL.ExecuteScsiCommand() .
15.4. EFI SCSI I/O Protocol 629Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheEFI_SCSI_IO_PROTOCOL provides the basic functionalities to access and manage a SCSI Device. There is one
EFI_SCSI_IO_PROTOCOL instance for each SCSI Device on a SCSI Bus. A device driver that wishes to manage a
SCSI Device in a system will have to retrieve the EFI_SCSI_IO_PROTOCOL instance that is associated with the SCSI
Device. A device handle for a SCSI Device will minimally contain an EFI_DEVICE_PATH_PROTOCOL instance
and an EFI_SCSI_IO_PROTOCOL instance.
15.4.2 EFI_SCSI_IO_PROTOCOL.GetDeviceType()
Summary
Retrieves the device type information of the SCSI Device.
Prototype
typedef
(EFIAPI *EFI_SCSI_IO_PROTOCOL_GET_DEVICE_TYPE) (
IN EFI_SCSI_IO_PROTOCOL *This,
OUT UINT8 *DeviceType
);
This A pointer to the EFI_SCSI_IO_PROTOCOL instance. Type EFI_SCSI_IO_PROTOCOL is deﬁned in
EFI_SCSI_IO_PROTOCOL .
DeviceType A pointer to the device type information retrieved from the SCSI Device. See “Related Deﬁnitions” for
the possible returned values of this parameter.
This function is used to retrieve the SCSI device type information. This function is typically used for SCSI Device
Drivers to quickly recognize whether the SCSI Device could be managed by it.
IfDeviceType isNULL , then EFI_INVALID_PARAMETER is returned. Otherwise, the device type is returned in
DeviceType andEFI_SUCCESS is returned.
//Defined inthe SCSI Primary Commands standard (e.g., SPC-4)
//
#define EFI_SCSI_IO_TYPE_DISK 0x00 // Disk device
#define EFI_SCSI_IO_TYPE_TAPE 0x01 // Tape device
#define EFI_SCSI_IO_TYPE_PRINTER 0x02 // Printer
#define EFI_SCSI_IO_TYPE_PROCESSOR 0x03 // Processor
#define EFI_SCSI_IO_TYPE_WORM 0x04 // Write-once read-multiple
#define EFI_SCSI_IO_TYPE_CDROM 0x05 // CD or DVD device
#define EFI_SCSI_IO_TYPE_SCANNER 0x06 // Scanner device
#define EFI_SCSI_IO_TYPE_OPTICAL 0x07 // Optical memory device
#define EFI_SCSI_IO_TYPE_MEDIUMCHANGER 0x08 // Medium Changer device
#define EFI_SCSI_IO_TYPE_COMMUNICATION 0x09 // Communications device
#define MFI_SCSI_IO_TYPE_A 0x0A // Obsolete
#define MFI_SCSI_IO_TYPE_B 0x0B // Obsolete
#define MFI_SCSI_IO_TYPE_RAID 0x0C // Storage array controller
// device (e.g., RAID)
#define MFI_SCSI_IO_TYPE_SES 0x0D // Enclosure services device
#define MFI_SCSI_IO_TYPE_RBC 0x0E // Simplified direct-access
15.4. EFI SCSI I/O Protocol 630Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// device (e.g., magnetic
// disk)
#define MFI_SCSI_IO_TYPE_OCRW 0x0F // Optical card reader/
// writer device
#define MFI_SCSI_IO_TYPE_BRIDGE 0x10 // Bridge Controller
// Commands
#define MFI_SCSI_IO_TYPE_OSD 0x11 // Object-based Storage
// Device
#define EFI_SCSI_IO_TYPE_RESERVED_LOW 0x12 // Reserved (low)
#define EFI_SCSI_IO_TYPE_RESERVED_HIGH 0x1E // Reserved (high)
#define EFI_SCSI_IO_TYPE_UNKNOWN 0x1F // Unknown no device type
EFI_SUCCESS Retrieves the device type information successfully.
EFI_INV ALID_PARAMETER The DeviceType is NULL .
15.4.3 EFI_SCSI_IO_PROTOCOL.GetDeviceLocation()
Summary
Retrieves the SCSI device location in the SCSI channel.
Prototype
typedef
(EFIAPI *EFI_SCSI_IO_PROTOCOL_GET_DEVICE_LOCATION) (
IN OUT UINT8 **Target,
OUT UINT64 *Lun
);
Target A pointer to the Target Array which represents the ID of a SCSI device on the SCSI channel.
Lun A pointer to the Logical Unit Number of the SCSI device on the SCSI channel.
This function is used to retrieve the SCSI device location in the SCSI bus. The device location is determined by a
(Target, Lun) pair. This function allows a SCSI Device Driver to retrieve its location on the SCSI channel, and may
use the Extended SCSI Pass Thru Protocol to access the SCSI device directly.
IfTarget orLunisNULL , then EFI_INVALID_PARAMETER is returned. Otherwise, the device location is returned
inTarget andLun, and EFI_SUCCESS is returned.
EFI_SUCCESS Retrieves the device location successfully.
EFI_INV ALID_PARAMETER Target or Lun is NULL .
15.4. EFI SCSI I/O Protocol 631Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
15.4.4 EFI_SCSI_IO_PROTOCOL.ResetBus()
Summary
Resets the SCSI Bus that the SCSI Device is attached to.
Prototype
typedef
(EFIAPI *EFI_SCSI_IO_PROTOCOL_RESET_BUS) (
IN EFI_SCSI_IO_PROTOCOL *This
);
This function provides the mechanism to reset the whole SCSI bus that the speciﬁed SCSI Device is connected to.
Some SCSI Host Controller may not support bus reset, if so, EFI_UNSUPPORTED is returned. If a device error
occurs while executing that bus reset operation, then EFI_DEVICE_ERROR is returned. If a timeout occurs during
the execution of the bus reset operation, then EFI_TIMEOUT is returned. If the bus reset operation is completed, then
EFI_SUCCESS The SCSI bus is reset successfully.
EFI_DEVICE_ERROR Errors encountered when resetting the SCSI bus.
EFI_UNSUPPORTED The bus reset operation is not supported by the SCSI Host Controller.
EFI_TIMEOUT A timeout occurred while attempting to reset the SCSI bus.
15.4.5 EFI_SCSI_IO_PROTOCOL.ResetDevice()
Summary
Resets the SCSI Device that is speciﬁed by the device handle that the SCSI I/O Protocol is attached.
Prototype
typedef
(EFIAPI *EFI_SCSI_IO_PROTOCOL_RESET_DEVICE) (
);
This A Pointer to the EFI_SCSI_IO_PROTOCOL instance. Type EFI_SCSI_IO_PROTOCOL is deﬁned in
This function provides the mechanism to reset the SCSI Device. If the SCSI bus does not support a device reset
operation, then EFI_UNSUPPORTED is returned. If a device error occurs while executing that device reset operation,
then EFI_DEVICE_ERROR is returned. If a timeout occurs during the execution of the device reset operation, then
EFI_TIMEOUT is returned. If the device reset operation is completed, then EFI_SUCCESS is returned.
15.4. EFI SCSI I/O Protocol 632Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS Reset the SCSI Device successfully.
EFI_DEVICE_ERROR Errors are encountered when resetting the SCSI Device.
EFI_UNSUPPORTED The SCSI bus does not support a device reset operation.
EFI_TIMEOUT A timeout occurred while attempting to reset the SCSI Device.
15.4.6 EFI_SCSI_IO_PROTOCOL.ExecuteScsiCommand()
Summary
Sends a SCSI Request Packet to the SCSI Device for execution.
Prototype
typedef
(EFIAPI *EFI_SCSI_IO_PROTOCOL_EXECUTE_SCSI_COMMAND) (
IN OUT EFI_SCSI_IO_SCSI_REQUEST_PACKET *Packet,
);
This A pointer to the EFI_SCSI_IO_PROTOCOL instance. Type EFI_SCSI_IO_PROTOCOL is deﬁned in deﬁned
inEFI_SCSI_IO_PROTOCOL .
Packet The SCSI request packet to send to the SCSI Device speciﬁed by the device handle. See “Related Deﬁnitions”
for a description of EFI_SCSI_IO_SCSI_REQUEST_PACKET.
Event If the SCSI bus where the SCSI device is attached does not support non-blocking I/O, then Event is ignored,
and blocking I/O is performed. If Event is NULL, then blocking I/O is performed. If Event is not NULL and
non-blocking I/O is supported, then non-blocking I/O is performed, and Event will be signaled when the SCSI
Request Packet completes.
VOID *SenseData;
VOID *Cdb;
UINT8 CdbLength;
UINT8 DataDirection;

);
VOID *Cdb;
UINT8 HostAdapterStatus;
UINT8 TargetStatus;
UINT8 SenseDataLength;
} EFI_SCSI_IO_SCSI_REQUEST_PACKET;
Timeout The timeout, in 100 ns units, to use for the execution of this SCSI Request Packet. A Timeout value of 0
means that this function will wait indeﬁnitely for the SCSI Request Packet to execute. If Timeout is greater than
zero, then this function will return EFI_TIMEOUT if the time required to execute the SCSI Request Packet is
greater than Timeout .
15.4. EFI SCSI I/O Protocol 633Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DataBuffer A pointer to the data buffer to transfer from or to the SCSI device.
InDataBuffer A pointer to the data buffer to transfer between the SCSI controller and the SCSI device for SCSI
READ command. For all SCSI WRITE Commands this must point to NULL .
OutDataBuffer A pointer to the data buffer to transfer between the SCSI controller and the SCSI device for SCSI
WRITE command. For all SCSI READ commands this ﬁeld must point to NULL .
SenseData A pointer to the sense data that was generated by the execution of the SCSI Request Packet.
Cdb A pointer to buffer that contains the Command Data Block to send to the SCSI device.
InTransferLength On Input, the size, in bytes, of InDataBuffer . On output, the number of bytes transferred between
the SCSI controller and the SCSI device. If InTransferLength is larger than the SCSI controller can handle, no
data will be transferred, InTransferLength will be updated to contain the number of bytes that the SCSI controller
between SCSI Controller and the SCSI device. If OutTransferLength is larger than the SCSI controller can
handle, no data will be transferred, OutTransferLength will be updated to contain the number of bytes that the
SCSI controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.
CdbLength The length, in bytes, of the buffer Cdb . The standard values are 6, 10, 12, and 16, but other values are
possible if a variable length CDB is used.
DataDirection The direction of the data transfer. 0 for reads, 1 for writes. A value of 2 is Reserved for Bi-Directional
SCSI commands. For example XDREADWRITE. All other values are reserved, and must not be used.
HostAdapterStatus The status of the SCSI Host Controller that produces the SCSI bus where the SCSI device at-
tached when the SCSI Request Packet was executed on the SCSI Controller. See the possible values listed
below.
TargetStatus The status returned by the SCSI device when the SCSI Request Packet was executed. See the possible
values listed below.
SenseDataLength On input, the length in bytes of the SenseData buffer. On output, the number of bytes written to
theSenseData buffer.
//
// DataDirection
//
#define EFI_SCSI_IO_DATA_DIRECTION_READ 0
#define EFI_SCSI_IO_DATA_DIRECTION_WRITE 1
#define EFI_SCSI_IO_DATA_DIRECTION_BIDIRECTIONAL 2
//
// HostAdapterStatus
//
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_OK 0x00
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_TIMEOUT 0x0b
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_BUS_RESET 0x0e
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_PARITY_ERROR 0x0f
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_BUS_FREE 0x13
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_OTHER 0x7f
15.4. EFI SCSI I/O Protocol 634Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// TargetStatus
//
#define EFI_SCSI_IO_STATUS_TARGET_GOOD 0x00
#define EFI_SCSI_IO_STATUS_TARGET_CHECK_CONDITION 0x02
#define EFI_SCSI_IO_STATUS_TARGET_CONDITION_MET 0x04
#define EFI_SCSI_IO_STATUS_TARGET_BUSY 0x08
#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE 0x10
#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE_CONDITION_METn 0x14
#define EFI_SCSI_IO_STATUS_TARGET_RESERVATION_CONFLICT 0x18
#define EFI_SCSI_IO_STATUS_TARGET_COMMAND_TERMINATED 0x22
#define EFI_SCSI_IO_STATUS_TARGET_QUEUE_FULL 0x28
This function sends the SCSI Request Packet speciﬁed by Packet to the SCSI Device.
If the SCSI Bus supports non-blocking I/O and Event is not NULL , then this function will return immediately after
the command is sent to the SCSI Device, and will later signal Event when the command has completed. If the SCSI
Bus supports non-blocking I/O and Event isNULL , then this function will send the command to the SCSI Device and
block until it is complete. If the SCSI Bus does not support non-blocking I/O, the Event parameter is ignored, and the
function will send the command to the SCSI Device and block until it is complete.
IfPacket is successfully sent to the SCSI Device, then EFI_SUCCESS is returned.
IfPacket cannot be sent because there are too many packets already queued up, then EFI_NOT_READY is returned.
The caller may retry Packet at a later time.
If a device error occurs while sending the Packet , then EFI_DEVICE_ERROR is returned.
If a timeout occurs during the execution of Packet , then EFI_TIMEOUT is returned.
If any ﬁeld of Packet is invalid, then EFI_INVALID_PARAMETER is returned.
If the data buffer described by DataBuffer andTransferLength is too big to be transferred in a single command, then
EFI_BAD_BUFFER_SIZE is returned. The number of bytes actually transferred is returned in TransferLength .
If the command described in Packet is not supported by the SCSI Host Controller that produces the SCSI bus, then
IfEFI_SUCCESS, EFI_BAD_BUFFER_SIZE, EFI_DEVICE_ERROR , orEFI_TIMEOUT is returned, then the caller
must examine the status ﬁelds in Packet in the following precedence order: HostAdapterStatus followed by TargetSta-
tusfollowed by SenseDataLength , followed by SenseData . If non-blocking I/O is being used, then the status ﬁelds
inPacket will not be valid until the Event associated with Packet is signaled.
IfEFI_NOT_READY ,EFI_INVALID_PARAMETER orEFI_UNSUPPORTED is returned, then Packet was never sent,
EFI_SUCCESS The SCSI Request Packet was sent by the host. For read and bi-directional
commands, InTransferLength bytes were transferred to InDataBuffer . For
write and bi-directional commands, OutTransferLength bytes were trans-
ferred from OutDataBuffer . See HostAdapterStatus, TargetStatus, Sense-
DataLength, andSenseData in that order for additional status information.
15.4. EFI SCSI I/O Protocol 635Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 15.3 – continued from previous page
EFI_BAD_BUFFER_SIZE The SCSI Request Packet was not executed. For read and bi-directional
commands, the number of bytes that could be transferred is returned in
InTransferLength. For write and bi-directional commands, the number
of bytes that could be transferred is returned in OutTransferLength. See
HostAdapterStatus andTargetStatus in that order for additional status infor-
mation.
EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many
SCSI Command Packets already queued. The caller may retry again later.
EFI_DEVICE_ERROR A device error occurred while attempting to send the SCSI Request Packet.
See HostAdapterStatus, TargetStatus, SenseDataLength, and SenseData in
that order for additional status information.
EFI_INV ALID_PARAMETER The contents of CommandPacket are invalid. The SCSI Request Packet was
not sent, so no additional status information is available.
EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by
the SCSI initiator (i.e., SCSI Host Controller). The SCSI Request Packet
EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
15.5 SCSI Device Paths
AnEFI_SCSI_IO_PROTOCOL must be installed on a handle for its services to be available to SCSI device drivers. In
addition to the EFI_SCSI_IO_PROTOCOL , anEFI_DEVICE_PATH_PROTOCOL must also be installed on the same
handle. See Protocols – Device Path Protocol for detailed description of the EFI_DEVICE_PATH_PROTOCOL .
The SCSI Driver Model deﬁned in this document can support the SCSI channel generated or emulated by multiple
architectures, such as Parallel SCSI, ATAPI, Fibre Channel, InﬁniBand, and other future channel types. In this section,

there are four example device paths provided, including SCSI device path, ATAPI device path, Fibre Channel device
path and InﬁniBand device path.
15.5.1 SCSI Device Path Example
Table 15.4 shows an example device path for a SCSI device controller on a desktop platform. This SCSI device
controller is connected to a SCSI channel that is generated by a PCI SCSI host controller. The PCI SCSI host controller
generates a single SCSI channel, it is located at PCI device number 0x07 and PCI function 0x00, and is directly
attached to a PCI root bridge. The SCSI device controller is assigned SCSI Id 2, and its LUN is 0.
This sample device path consists of an ACPI Device Path Node, a PCI Device Path Node, a SCSI Node, and a Device
Path End Structure. The _HID and _UID must match the ACPI table description of the PCI Root Bridge. The shorthand
ACPI(PNP0A03,0)/PCI(7,0)/SCSI(2,0).
Table 15.4: SCSI Device Path Examples
Byte Off-
setByte
15.5. SCSI Device Paths 636Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 15.4 – continued from previous page
0x10 0x01 0x07 PCI Function
0x11 0x01 0x00 PCI Device
0x13 0x01 0x02 Sub type - SCSI
0x14 0x02 0x08 Length - 0x08 bytes
0x16 0x02 0x0002 Target ID on the SCSI bus (PUN)
0x18 0x02 0x0000 Logical Unit Number (LUN)
0x1A 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x1B 0x01 0xFF Sub type - End of Entire Device Path
0x1C 0x02 0x04 Length - 0x04 bytes
15.5.2 ATAPI Device Path Example
The Table below, ATAPI Device Path Examples , shows an example device path for an ATAPI device on a desktop
platform. This ATAPI device is connected to the IDE bus on Primary channel, and is conﬁgured as the Master device
on the channel. The IDE bus is generated by the IDE controller that is a PCI device. It is located at PCI device number
0x1F and PCI function 0x01, and is directly attached to a PCI root bridge.
This sample device path consists of an ACPI Device Path Node, a PCI Device Path Node, an ATAPI Node, and a
Device Path End Structure. The _HID and _UID must match the ACPI table description of the PCI Root Bridge. The
shorthand notation for this device path is:
ACPI(PNP0A03,0)/PCI(7,0)/ATA(Primary,Master,0).
Table 15.5: ATAPI Device Path Examples
Byte Off-
setByte
0x13 0x01 0x01 Sub type - ATAPI
15.5. SCSI Device Paths 637Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 15.5 – continued from previous page
0x16 0x01 0x00 P rimarySecondary - Set to zero for primary or one for secondary.
0x17 0x01 0x00 SlaveMaster - set to zero for master or one for slave.
0x18 0x02 0x0000 Logical Unit Number,LUN.
15.5.3 Fibre Channel Device Path Example
Section 10.3.4.3 shows an example device path for a SCSI device that is connected to a Fibre Channel Port on a
desktop platform. The Fibre Channel Port is a PCI device that is located at PCI device number 0x08 and PCI function
0x00, and is directly attached to a PCI root bridge. The Fibre Channel Port is addressed by the World Wide Number,
and is assigned as X (X is a 64bit value); the SCSI device’s Logical Unit Number is 0.
This sample device path consists of an ACPI Device Path Node, a PCI Device Path Node, a Fibre Channel Device Path
Node, and a Device Path End Structure. The _HID and _UID must match the ACPI table description of the PCI Root
Bridge. The shorthand notation for this device path is:
ACPI(PNP0A03,0)/PCI(8,0)/Fibre(X,0).
Table 15.6: Fibre Channel Device Path Examples
Byte Off-
setByte
0x10 0x01 0x08 PCI Function
0x13 0x01 0x02 Sub type - Fibre Channel
0x14 0x02 0x24 Length - 0x24 bytes
0x16 0x04 0x00 Reserved
0x1A 0x08 X Fibre Channel World Wide Number
0x22 0x08 0x00 Fibre Channel Logical Unit Number (LUN).
0x2A 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x2B 0x01 0xFF Sub type - End of Entire Device Path
0x2C 0x02 0x04 Length - 0x04 bytes
15.5. SCSI Device Paths 638Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
15.5.4 InﬁniBand Device Path Example
The Table below, InﬁniBand Device Path Examples , shows an example device path for a SCSI device in an InﬁniBand
Network. This SCSI device is connected to a single SCSI channel generated by a SCS Host Adapter, and the SCSI
Host Adapter is an end node in the InﬁniBand Network. The SCSI Host Adapter is a PCI device that is located at
PCI device number 0x07 and PCI function 0x00, and is directly attached to a PCI root bridge. The SCSI device is
addressed by the (IOU X, IOC Y , DeviceId Z) in the InﬁniBand Network. (X, Y , Z are EUI-64 compliant identiﬁers).
This sample device path consists of an ACPI Device Path Node, a PCI Device Path Node, an InﬁniBand Node, and a
ACPI(PNP0A03,0)/PCI(7,0)/Infiniband(X,Y,Z).
Table 15.7: InﬁniBand Device Path Examples
Byte Off-
setByte
0x13 0x01 0x09 Sub type - InﬁniBand
0x14 0x02 0x20 Length - 0x20 bytes
0x1A 0x08 X 64bit node GUID of the IOU
0x22 0x08 Y 64bit GUID of the IOC
0x2A 0x08 Z 64bit persistent ID of the device.
0x32 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x33 0x01 0xFF Sub type - End of Entire Device Path
0x34 0x02 0x04 Length - 0x04 bytes
15.6 SCSI Pass Thru Device Paths
AnEFI_EXT_SCSI_PASS_THRU_PROTOCOL must be installed on a handle for its services to be available to UEFI
drivers and applications. In addition to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL ,EFI Device Path Protocol
must also be installed on the same handle. See Protocols – Device Path Protocol for a detailed description of the
includes the list of busses that lie between the processor and the SCSI controller. The EFI Speciﬁcation takes advantage
of the ACPI Speciﬁcation to name system components. For the following set of examples, a PCI SCSI controller is
assumed. The examples will show a SCSI controller on the root PCI bus, and a SCSI controller behind a PCI-PCI
15.6. SCSI Pass Thru Device Paths 639Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

bridge. In addition, an example of a multichannel SCSI controller will be shown.
SeeSingle Channel PCI SCSI Controller shows an example device path for a single channel PCI SCSI controller that
is located at PCI device number 0x07 and PCI function 0x00, and is directly attached to a PCI root bridge. This device
ACPI(PNP0A03,0)/PCI(7,0).
Table 15.8: Single Channel PCI SCSI Controller
Byte Off-
setByte
The Table below, Single Channel PCI SCSI Controller Behind a PCI Bridge , shows an example device path for a
single channel PCI SCSI controller that is located behind a PCI to PCI bridge at PCI device number 0x07 and PCI
function 0x00. The PCI to PCI bridge is directly attached to a PCI root bridge, and it is at PCI device number 0x05
and PCI function 0x00. This device path consists of an ACPI Device Path Node, two PCI Device Path Nodes, and a
Table 15.9: Single Channel PCI SCSI Controller Behind a PCI Bridge
Byte Off-
setByte
15.6. SCSI Pass Thru Device Paths 640Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 15.9 – continued from previous page
Table 15.10 shows an example device path for channel #3 of a four channel PCI SCSI controller that is located behind
a PCI to PCI bridge at PCI device number 0x07 and PCI function 0x00. The PCI to PCI bridge is directly attached to
a PCI root bridge, and it is at PCI device number 0x05 and PCI function 0x00. This device path consists of an ACPI
Device Path Node, two PCI Device Path Nodes, a Controller Node, and a Device Path End Structure. The _HID and
_UID must match the ACPI table description of the PCI Root Bridge. The shorthand notation of the device paths for
all four of the SCSI channels are listed below:
ACPI(PNP0A03,0)/PCI(5,0)/PCI(7,0)/Ctrl(0)
ACPI(PNP0A03,0)/PCI(5,0)/PCI(7,0)/Ctrl(1)
ACPI(PNP0A03,0)/PCI(5,0)/PCI(7,0)/Ctrl(2)
ACPI(PNP0A03,0)/PCI(5,0)/PCI(7,0)/Ctrl(3)
The following table shows the last device path listed.
Table 15.10: Channel #3 of a PCI SCSI Controller behind a PCIBridge
Byte Off-
setByte
0x18 0x01 0x01 Generic Device Path Header - Type Hardware Device Path
0x19 0x01 0x05 Sub type - Controller
0x1A 0x02 0x08 Length - 0x08 bytes
0x1C 0x04 0x0003 Controller Number
0x20 0x01 0x7F Generic Device Path Header - Type End of Hardware Device Path
0x21 0x01 0xFF Sub type - End of Entire Device Path
0x22 0x02 0x04 Length - 0x04 bytes
15.6. SCSI Pass Thru Device Paths 641Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
15.7 Extended SCSI Pass Thru Protocol
This section deﬁnes the Extended SCSI Pass Thru Protocol. This protocol allows information about a SCSI channel
to be collected, and allows SCSI Request Packets to be sent to any SCSI devices on a SCSI channel even if those
devices are not boot devices. This protocol is attached to the device handle of each SCSI channel in a system that the
protocol supports, and can be used for diagnostics. It may also be used to build a Block I/O driver for SCSI hard drives
and SCSI CD-ROM or DVD drives to allow those devices to become boot devices. As ATAPI cmds are derived from
SCSI cmds, the above statements also are applicable for ATAPI devices attached to a ATA controller. Packet-based
commands(ATAPI cmds) would be sent to ATAPI devices only through the Extended SCSI Pass Thru Protocol.
15.7.1 EFI_EXT_SCSI_PASS_THRU_PROTOCOL
This section provides a detailed description of the EFI_EXT_SCSI_PASS_THRU_PROTOCOL .
Summary
Provides services that allow SCSI Pass Thru commands to be sent to SCSI devices attached to a SCSI channel. It also
allows packet-based commands (ATAPI cmds) to be sent to ATAPI devices attached to a ATA controller.
GUID
#define EFI_EXT_SCSI_PASS_THRU_PROTOCOL_GUID \
{0x143b7632, 0xb81b, 0x4cb7,\
{0xab, 0xd3, 0xb6, 0x25, 0xa5, 0xb9, 0xbf, 0xfe}}
typedef struct _EFI_EXT_SCSI_PASS_THRU_PROTOCOL {
EFI_EXT_SCSI_PASS_THRU_MODE *Mode;
EFI_EXT_SCSI_PASS_THRU_PASSTHRU PassThru;
EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET_LUN GetNextTargetLun;
EFI_EXT_SCSI_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;
EFI_EXT_SCSI_PASS_THRU_GET_TARGET_LUN GetTargetLun;
EFI_EXT_SCSI_PASS_THRU_RESET_CHANNEL ResetChannel;
EFI_EXT_SCSI_PASS_THRU_RESET_TARGET_LUN ResetTargetLun;
EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGE GetNextTarget;
} EFI_EXT_SCSI_PASS_THRU_PROTOCOL;
Mode A pointer to the EFI_EXT_SCSI_PASS_THRU_MODE data for this SCSI channel.
EFI_EXT_SCSI_PASS_THRU_MODE is deﬁned in “Related Deﬁnitions” below.
PassThru Sends a SCSI Request Packet to a SCSI device that is Connected to the SCSI channel. See the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL.PassThru() function description.
GetNextTargetLun Retrieves the list of legal Target IDs and LUNs for the SCSI devices on a SCSI channel. See the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetNextTargetLun() function description.
BuildDevicePath Allocates and builds a device path node for a SCSI Device on a SCSI channel. See the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL.BuildDevicePath() function description.
GetTargetLun Translates a device path node to a Target ID and LUN. See the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetTargetLun() function description.
ResetChannel Resets the SCSI channel. This operation resets all the SCSI devices connected to the SCSI channel.
See the EFI_EXT_SCSI_PASS_THRU_PROTOCOL.ResetChannel() function description.
15.7. Extended SCSI Pass Thru Protocol 642Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ResetTargetLun Resets a SCSI device that is connected to the SCSI channel. See the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL.ResetTargetLun() function description.
GetNextTartget Retrieves the list of legal Target IDs for the SCSI devices on a SCSI channel. See the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetNextTarget() function description.
The following data values in the EFI_EXT_SCSI_PASS_THRU_MODE interface are read-only.
AdapterId The Target ID of the host adapter on the SCSI channel.
Attributes Additional information on the attributes of the SCSI channel. See “Related Deﬁnitions” below for the list
of possible attributes.

UINT32*AdapterId; *
UINT32*Attributes; *
UINT32*IoAlign; *
} EFI_EXT_SCSI_PASS_THRU_MODE;
#define TARGET_MAX_BYTES 0x10
#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001
#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002
#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004
EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL If this bit is set, then the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL interface is for physical devices on the SCSI channel.
EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL If this bit is set, then the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL interface is for logical devices on the SCSI channel.
EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_NONBLOCKIO If this bit is set, then the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL interface supports non blocking I/O. Every
EFI_EXT_SCSI_PASS_THRU_PROTOCOL must support blocking I/O. The support of nonblocking I/O
The EFI_EXT_SCSI_PASS_THRU_PROTOCOL provides information about a SCSI channel and the ability to send
SCI Request Packets to any SCSI device attached to that SCSI channel. The information includes the Target ID of the
host controller on the SCSI channel and the attributes of the SCSI channel.
The printable name for the SCSI controller, and the printable name of the SCSI channel can be provided through the
EFI_COMPONENT_NAME2_PROTOCOL for multiple languages.
The Attributes ﬁeld of the EFI_EXT_SCSI_PASS_THRU_PROTOCOL interface tells if the in-
terface is for physical SCSI devices or logical SCSI devices. Drivers for non-RAID SCSI
controllers will set both the EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL , and the
EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL bits.
vices will produce two EFI_EXT_SCSI_PASS_THRU_PROTOCOL interfaces: one with the just
the EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL bit set and another with just the
EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL bit set. One interface can be used to access the physi-
cal devices attached to the RAID controller, and the other can be used to access the logical devices attached to the
RAID controller for its current conﬁguration.
15.7. Extended SCSI Pass Thru Protocol 643Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_EXT_SCSI_PASS_THROUGH_PROTOCOL interface with just the EFI_EXT_SCSI_PASS_THRU_LOGICAL bit
set. The interface for logical devices can also be used by a ﬁle system driver to mount the RAID volumes.
AnEFI_EXT_SCSI_PASS_THRU_PROTOCOL with neither EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL
norEFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal conﬁguration.
The Attributes ﬁeld also contains the EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_NONBLOCKIO bit. All
EFI_EXT_SCSI_PASS_THRU_PROTOCOL interfaces must support blocking I/O. If this bit is set, then the interface
support both blocking I/O and nonblocking I/O.
Each EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance must have an associated device path. Typically this will
have an ACPI device path node and a PCI device path node, although variation will exist. For a SCSI controller
that supports only one channel per PCI bus/device/function, it is recommended, but not required, that an additional
Controller device path node (for controller 0) be appended to the device path.
For a SCSI controller that supports multiple channels per PCI bus/device/function, it is required that a Controller
device path node be appended for each channel.
Additional information about the SCSI channel can be obtained from protocols attached to the same handle as the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL , or one of its parent handles. This would include the device I/O abstrac-
tion used to access the internal registers and functions of the SCSI controller.
15.7.2 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.PassThru()
Summary
Sends a SCSI Request Packet to a SCSI device that is attached to the SCSI channel. This function supports both
blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking I/O functionality
Prototype
typedef
(EFIAPI *EFI_EXT_SCSI_PASS_THRU_PASSTHRU) (
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
IN UINT8 *Target,
IN UINT64 Lun,
IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet,
);
This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance. Type
EFI_EXT_SCSI_PASS_THRU_PROTOCOL is deﬁned in Extended SCSI Pass Thru Protocol .
Target The Target is an array of size TARGET_MAX_BYTES and it represents the id of the SCSI device to send the
SCSI Request Packet. Each transport driver may chose to utilize a subset of this size to suit the needs of transport
target representation. For example, a Fibre Channel driver may use only 8 bytes (WWN) to represent an FC
target.
Lun The LUN of the SCSI device to send the SCSI Request Packet.
Packet A pointer to the SCSI Request Packet to send to the SCSI device speciﬁed by Target andLun. See “Related
Deﬁnitions” below for a description of EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET .
Event If nonblocking I/O is not supported then Event is ignored, and blocking I/O is performed. If Event isNULL ,
then blocking I/O is performed. If Event is not NULL and non blocking I/O is supported, then nonblocking I/O
is performed, and Event will be signaled when the SCSI Request Packet completes.
15.7. Extended SCSI Pass Thru Protocol 644Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
VOID *Cdb;
} EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET;
InDataBuffer A pointer to the data buffer to transfer between the SCSI controller and the SCSI device for read and
and may be NULL . If this ﬁeld is not NULL , then it must be aligned on the boundary speciﬁed by the IoAlign
ﬁeld in the EFI_EXT_SCSI_PASS_THRU_MODE structure.
OutDataBuffer A pointer to the data buffer to transfer between the SCSI controller and the SCSI device for write
optional and may be NULL . If this ﬁeld is not NULL , then it must be aligned on the boundary speciﬁed by the
IoAlign ﬁeld in the EFI_EXT_SCSI_PASS_THRU_MODE structure.
SenseData A pointer to the sense data that was generated by the execution of the SCSI Request Packet. If Sense-
DataLength is 0, then this ﬁeld is optional and may be NULL . It is strongly recommended that a sense data
buffer of at least 252 bytes be provided to guarantee the entire sense data buffer generated from the execution
of the SCSI Request Packet can be returned. If this ﬁeld is not NULL , then it must be aligned to the boundary
speciﬁed in the IoAlign ﬁeld in the EFI_EXT_SCSI_PASS_THRU_MODE structure.
Cdb A pointer to buffer that contains the Command Data Block to send to the SCSI device speciﬁed by Target and
Lun.

HostAdapterStatus The status of the host adapter speciﬁed by This when the SCSI Request Packet was executed on
the target device. See the possible values listed below. If bit 7 of this ﬁeld is set, then HostAdapterStatus is a
vendor deﬁned error code.
15.7. Extended SCSI Pass Thru Protocol 645Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TargetStatus The status returned by the device speciﬁed by Target andLun when the SCSI Request Packet was
executed. See the possible values listed below.
//
//
#define EFI_EXT_SCSI_DATA_DIRECTION_READ 0
#define EFI_EXT_SCSI_DATA_DIRECTION_WRITE 1
#define EFI_EXT_SCSI_DATA_DIRECTION_BIDIRECTIONAL 2
//
//
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_OK 0x00
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT 0x0b
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_BUS_RESET 0x0e
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_PARITY_ERROR 0x0f
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_BUS_FREE 0x13
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14
#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_OTHER 0x7f
//
//
#define EFI_EXT_SCSI_STATUS_TARGET_GOOD 0x00
#define EFI_EXT_SCSI_STATUS_TARGET_CHECK_CONDITION 0x02
#define EFI_EXT_SCSI_STATUS_TARGET_CONDITION_MET 0x04
#define EFI_EXT_SCSI_STATUS_TARGET_BUSY 0x08
#define EFI_EXT_SCSI_STATUS_TARGET_INTERMEDIATE 0x10
#define EFI_EXT_SCSI_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14
#define EFI_EXT_SCSI_STATUS_TARGET_RESERVATION_CONFLICT 0x18
#define EFI_EXT_SCSI_STATUS_TARGET_TASK_SET_FULL 0x28
#define EFI_EXT_SCSI_STATUS_TARGET_ACA_ACTIVE 0x30
#define EFI_EXT_SCSI_STATUS_TARGET_TASK_ABORTED 0x40
The EFI_EXT_SCSI_PASS_THRU_PROTOCOL.PassThru() function sends the SCSI Request Packet speciﬁed by
Packet to the SCSI device speciﬁed by Target andLun . If the driver supports nonblocking I/O and Event is not
NULL, then the driver will return immediately after the command is sent to the selected device, and will later signal
Event when the command has completed.
If the driver supports nonblocking I/O and Event is NULL, then the driver will send the command to the selected
If the driver does not support nonblocking I/O, then the Event parameter is ignored, and the driver will send the
IfPacket is successfully sent to the SCSI device, then EFI_SUCCESS is returned.
15.7. Extended SCSI Pass Thru Protocol 646Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If a device is not present but the target/LUN address in the packet are valid, then EFI_TIMEOUT is returned, and
HostStatus is set to EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND .
IfTarget orLun are not in a valid range for the SCSI channel, then EFI_INVALID_PARAMETER is returned. If
InDataBuffer, OutDataBuffer orSenseData do not meet the alignment requirement speciﬁed by the IoAlign ﬁeld of
theEFI_EXT_SCSI_PASS_THRU_MODE structure, then EFI_INVALID_PARAMETER is returned. If any of the other
a single command are returned in InTransferLength .
If the data buffer described by OutDataBuffer andOutTransferLength is too big to be transferred in a single command,
a single command are returned in OutTransferLength .
tusfollowed by SenseDataLength , followed by SenseData .
If nonblocking I/O is being used, then the status ﬁelds in Packet will not be valid until the Event associated with Packet
is signaled.
so the status ﬁelds in Packet are not valid. If nonblocking I/O is being used, the Event associated with Packet will not
Note :Some examples of SCSI read commands are READ, INQUIRY, and MODE_SENSE .
Note :Some examples of SCSI write commands are WRITE and MODE_SELECT .
Note :An example of a SCSI non data command is TEST_UNIT_READY .
EFI_SUCCESS The SCSI Request Packet was sent by the host. For bi-directional com-
mands, InTransferLength bytes were transferred from InDataBuffer . For
ferred by OutDataBuffer. See HostAdapterStatus, TargetStatus, Sense-
EFI_BAD_BUFFER_SIZE The SCSI Request Packet was not executed. The number of bytes that could
be transferred is returned in InTransferLength. For write and bi-directional
commands, OutTransferLength bytes were transferred by OutDataBuffer.
SeeHostAdapterStatus, TargetStatus, and in that order for additional status
SCSI Request Packets already queued. The caller may retry again later.
SeeHostAdapterStatus, TargetStatus, SenseDataLength, andSenseData in
EFI_INV ALID_PARAMETER Target, Lun, or the contents of ScsiRequestPacket are invalid. The SCSI
Request Packet was not sent, so no additional status information is available.
15.7. Extended SCSI Pass Thru Protocol 647Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 15.11 – continued from previous page
the host adapter. This includes the case of Bi-directional SCSI commands
not supported by the implementation. The SCSI Request Packet was not
sent, so no additional status information is available.
15.7.3 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetNextTargetLun()
Summary
Used to retrieve the list of legal Target IDs and LUNs for SCSI devices on a SCSI channel. These can either be the
list SCSI devices that are actually present on the SCSI channel, or the list of legal Target Ids and LUNs for the SCSI
channel. Regardless, the caller of this function must probe the Target ID and LUN returned to see if a SCSI device is
actually present at that location on the SCSI channel.
Prototype
typedef
(EFIAPI *EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET_LUN) (
IN OUT UINT64 *Lun
);
Target On input, a pointer to a legal Target ID (an array of size TARGET_MAX_BYTES) for a SCSI device present
on the SCSI channel. On output, a pointer to the next legal Target ID (an array of TARGET_MAX_BYTES ) of a
SCSI device on a SCSI channel. An input value of 0xFF ’s (all bytes in the array are 0xFF ) in the Target array
retrieves the ﬁrst legal Target ID for a SCSI device present on a SCSI channel.
Lun On input, a pointer to the LUN of a SCSI device present on the SCSI channel. On output, a pointer to the LUN
of the next SCSI device ID on a SCSI channel.
The EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetNextTargetLun() function retrieves a list of legal Target ID and
LUN of a SCSI channel. If on input a Target is speciﬁed by all 0xFF in the Target array, then the ﬁrst legal Target ID
and LUN for a SCSI device on a SCSI channel is returned in Target andLun, andEFI_SUCCESS is returned.

IfTarget andLunis a Target ID and LUN value that was returned on a previous call to GetNextTargetLun() , then the
next legal Target ID and LUN for a SCSI device on the SCSI channel is returned in Target andLun, and EFI_SUCCESS
IfTarget array is not all 0xFF’s andTarget andLunwere not returned on a previous call to GetNextTargetLun() , then
IfTarget andLunare the Target ID and LUN of the last SCSI device on the SCSI channel, then EFI_NOT_FOUND is
returned.
15.7. Extended SCSI Pass Thru Protocol 648Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The Target ID and LUN of the next SCSI device on the SCSI channel was
returned in Target andLun.
EFI_NOT_FOUND There are no more SCSI devices on this SCSI channel.
EFI_INV ALID_PARAMETER Target array is not all 0xFF ’s, and Target andLunwere not returned on a
previous call to GetNextTargetLun() .
15.7.4 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.BuildDevicePath()
Summary
Used to allocate and build a device path node for a SCSI device on a SCSI channel.
Prototype
typedef
(EFIAPI *EFI_EXT_SCSI_PASS_THRU_BUILD_DEVICE_PATH) (
IN UINT64 Lun
);
Target The Target is an array of size TARGET_MAX_BYTES and it speciﬁes the Target ID of the SCSI device for
which a device path node is to be allocated and built. Transport drivers may chose to utilize a subset of this size
to suit the representation of targets. For example, a Fibre Channel driver may use only 8 bytes (WWN) in the
array to represent a FC target.
Lun The LUN of the SCSI device for which a device path node is to be allocated and built.
DevicePath A pointer to a single device path node that describes the SCSI device speciﬁed by Target andLun. This
function is responsible for allocating the buffer DevicePath with the boot service AllocatePool() . It is the caller’s
responsibility to free DevicePath when the caller is ﬁnished with DevicePath .
TheEFI_EXT_SCSI_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device path
node for the SCSI device speciﬁed by Target andLun. If the SCSI device speciﬁed by Target andLunare not present
on the SCSI channel, then EFI_NOT_FOUND is returned. If DevicePath isNULL , then EFI_INVALID_PARAMETER
is returned. If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is
returned. Otherwise, DevicePath is allocated with the boot service AllocatePool() , the contents of DevicePath are
initialized to describe the SCSI device speciﬁed by Target andLun, and EFI_SUCCESS is returned.
EFI_SUCCESS The device path node that describes the SCSI device speciﬁed by Target and
Lunwas allocated and returned in DevicePath .
EFI_NOT_FOUND The SCSI devices speciﬁed by Target andLundoes not exist on the SCSI
channel.
EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath.
15.7. Extended SCSI Pass Thru Protocol 649Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
15.7.5 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetTargetLun()
Summary
Used to translate a device path node to a Target ID and LUN.
Prototype
typedef
(EFIAPI *EFI_EXT_SCSI_PASS_THRU_GET_TARGET_LUN) (
OUT UINT8 **Target,
);
DevicePath A pointer to the device path node that describes a SCSI device on the SCSI channel.
Lun A pointer to the LUN of a SCSI device on the SCSI channel.
TheEFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetTargetLun() function determines the Target ID and LUN associ-
ated with the SCSI device described by DevicePath . IfDevicePath is a device path node type that the SCSI Pass Thru
driver supports, then the SCSI Pass Thru driver will attempt to translate the contents DevicePath into a Target ID and
LUN. If this translation is successful, then that Target ID and LUN are returned in Target andLun, and EFI_SUCCESS
IfDevicePath ,Target , orLunareNULL , then EFI_INVALID_PARAMETER is returned.
IfDevicePath is not a device path node type that the SCSI Pass Thru driver supports, then EFI_UNSUPPORTED is
returned.
IfDevicePath is a device path node type that the SCSI Pass Thru driver supports, but there is not a valid translation
from DevicePath to a Target ID and LUN, then EFI_NOT_FOUND is returned.
EFI_SUCCESS DevicePath was successfully translated to a Target ID and LUN, and they
were returned in Target and Lun.
EFI_INV ALID_PARAMETER Target isNULL
EFI_INV ALID_PARAMETER LunisNULL
EFI_NOT_FOUND A valid translation from DevicePath to a Target ID and LUN does not exist.
15.7. Extended SCSI Pass Thru Protocol 650Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
15.7.6 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.ResetChannel()
Summary
Resets a SCSI channel. This operation resets all the SCSI devices connected to the SCSI channel.
Prototype
typedef
(EFIAPI *EFI_EXT_SCSI_PASS_THRU_RESET_CHANNEL) (
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This
);
TheEFI_EXT_SCSI_PASS_THRU_PROTOCOL.ResetChannel() function resets a SCSI channel. This operation resets
all the SCSI devices connected to the SCSI channel. If this SCSI channel does not support a reset operation, then
If a device error occurs while executing that channel reset operation, then EFI_DEVICE_ERROR is returned.
If a timeout occurs during the execution of the channel reset operation, then EFI_TIMEOUT is returned. If the channel
reset operation is completed, then EFI_SUCCESS is returned.
EFI_SUCCESS The SCSI channel was reset.
EFI_UNSUPPORTED The SCSI channel does not support a channel reset operation.
EFI_DEVICE_ERROR A device error occurred while attempting to reset the SCSI channel.
EFI_TIMEOUT A timeout occurred while attempting to reset the SCSI channel.
15.7.7 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.ResetTargetLun()
Summary
Resets a SCSI logical unit that is connected to a SCSI channel.
Prototype
typedef
(EFIAPI *EFI_EXT_SCSI_PASS_THRU_RESET_TARGET_LUN) (
);
Target The Target is an array of size TARGET_MAX_BYTE and it represents the target port ID of the SCSI device
containing the SCSI logical unit to reset. Transport drivers may chose to utilize a subset of this array to suit the
15.7. Extended SCSI Pass Thru Protocol 651Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
representation of their targets. For example a Fibre Channel driver may use only 8 bytes in the array (WWN) to
represent a FC target.
Lun The LUN of the SCSI device to reset.
TheEFI_EXT_SCSI_PASS_THRU_PROTOCOL.ResetTargetLun() function resets the SCSI logical unit speciﬁed by
Target andLun. If this SCSI channel does not support a target reset operation, then EFI_UNSUPPORTED is returned.
IfTarget orLunare not in a valid range for this SCSI channel, then EFI_INVALID_PARAMETER is returned.
If a device error occurs while executing that logical unit reset operation, then EFI_DEVICE_ERROR is returned.
If a timeout occurs during the execution of the logical unit reset operation, then EFI_TIMEOUT is returned.
If the logical unit reset operation is completed, then EFI_SUCCESS is returned.
EFI_SUCCESS The SCSI device speciﬁed by Target andLunwas reset
EFI_UNSUPPORTED The SCSI channel does not support a target reset operation.
EFI_INV ALID_PARAMETER Target orLunare invalid.
EFI_DEVICE_ERROR A device error occurred while attempting to reset the SCSI device speciﬁed
byTarget andLun.
EFI_TIMEOUT A timeout occurred while attempting to reset the SCSI device speciﬁed by
Target andLun.
15.7.8 EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetNextTarget()
Summary
Used to retrieve the list of legal Target IDs for SCSI devices on a SCSI channel. These can either be the list SCSI

Summary
devices that are actually present on the SCSI channel, or the list of legal Target IDs for the SCSI channel. Regardless,
the caller of this function must probe the Target ID returned to see if a SCSI device is actually present at that location
on the SCSI channel.
Prototype
typedef
(EFIAPI *EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET) (
);
Target On input, a pointer to the Target ID (an array of size TARGET_MAX_BYTES ) of a SCSI device present on
the SCSI channel. On output, a pointer to the Target ID (an array of TARGET_MAX_BYTES ) of the next SCSI
device present on a SCSI channel. An input value of 0xFF ’s (all bytes in the array are 0xFF ) in the Target
array retrieves the Target ID of the ﬁrst SCSI device present on a SCSI channel.
15.7. Extended SCSI Pass Thru Protocol 652Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The EFI_EXT_SCSI_PASS_THRU_PROTOCOL.GetNextTarget() function retrieves the Target ID of a SCSI device
present on a SCSI channel. If on input a Target is speciﬁed by all 0xF in the Target array, then the Target ID of the ﬁrst
SCSI device is returned in Target andEFI_SUCCESS is returned.
IfTarget is a Target ID value that was returned on a previous call to GetNextTarget() , then the Target ID of the next
SCSI device on the SCSI channel is returned in Target , and EFI_SUCCESS is returned.
IfTarget array is not all 0xFF’s and Target were not returned on a previous call to GetNextTarget() , then
IfTarget is the Target ID of the last SCSI device on the SCSI channel, then EFI_NOT_FOUND is returned.
EFI_SUCCESS The Target ID of the next SCSI device on the SCSI channel was returned in
Target .
EFI_INV ALID_PARAMETER Target array is not all 0xFF’s , and Target were not returned on a previous
call to GetNextTarget() .
15.7. Extended SCSI Pass Thru Protocol 653CHAPTER
SIXTEEN
PROTOCOLS — ISCSI BOOT
16.1 Overview
The iSCSI protocol deﬁnes a transport for SCSI data over TCP/IP. It also provides an interoperable solution that takes
advantage of existing internet infrastructure, management facilities, and addresses distance limitations. The iSCSI
protocol speciﬁcation was developed by the Internet Engineering Task Force (IETF) and is SCSI Architecture Model-
2 (SAM-2) compliant. iSCSI encapsulates block-oriented SCSI commands into iSCSI Protocol Data Units (PDU) that
traverse the network over TCP/IP. iSCSI deﬁnes a Session, the initiator and target nexus (I-T nexus), which could be
a bundle of one or more TCP connections.
Similar to other existing mass storage protocols like Fibre Channel and parallel SCSI, boot over iSCSI is an important
functionality. This document will attempt to capture the various cases for iSCSI boot and common up with generic
EFI protocol changes to address them.
16.1.1 iSCSI UEFI Driver Layering
iSCSI UEFI Drivers may exist in two different forms:
•iSCSI UEFI Driver on a NIC: The driver will be layered on top of the networking layers. It will use the
DHCP, IP, and TCP and packet level interface protocols of the UEFI networking stack. The driver will use
an iSCSI software initiator.
•iSCSI UEFI Driver on a Host Bus Adapter (HBA)that may use an ofﬂoading engine such as TOE (or anyother TCP ofﬂoad card):
The driver will be layered on top of the TOE TCP interfaces. It will use the DHCP, IP, TCP proto-
cols of the TOE. The driver will present itself as a SCSI device driver using interfaces such as
EFI_EXT_SCSI_PASS_THRU_PROTOCOL .
To help in detecting iSCSI UEFI Drivers and their capabilities, the iSCSI UEFI driver handle must include an instance
of the EFI_ADAPTER_INFORMATION_PROTOCOL with a EFI_ADAPTER_INFO_NETWORK_BOOT structure.
16.2 EFI iSCSI Initiator Name Protocol
This protocol sets and obtains the iSCSI Initiator Name. The iSCSI Initiator Name protocol builds a default iSCSI
name. The iSCSI name conﬁgures using the programming interfaces deﬁned below. Successive conﬁguration of
the iSCSI initiator name overwrites the previously existing name. Once overwritten, the previous name will not be
retrievable. Setting an iSCSI name string that is zero length is illegal. The maximum size of the iSCSI Initiator Name
is 224 bytes (including the NULL terminator).
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16.2.1 EFI_ISCSI_INITIATOR_NAME_PROTOCOL
Summary
iSCSI Initiator Name Protocol for setting and obtaining the iSCSI Initiator Name.
GUID
#define EFI_ISCSI_INITIATOR_NAME_PROTOCOL_GUID \
{0x59324945, 0xec44, 0x4c0d, \
{0xb1, 0xcd, 0x9d, 0xb1, 0x39, 0xdf, 0x07, 0x0c}}
typedef struct _EFI_ISCSI_INITIATOR_NAME_PROTOCOL {
EFI_ISCSI_INITIATOR_NAME_GET Get;
EFI_ISCSI_INITIATOR_NAME_SET Set;
} EFI_ISCSI_INITIATOR_NAME_PROTOCOL;
Get Used to retrieve the iSCSI Initiator Name.
SetUsed to set the iSCSI Initiator Name.
TheEFI_ISCSI_INIT_NAME_PROTOCOL provides the ability to get and set the iSCSI Initiator Name.
16.2.2 EFI_ISCSI_INITIATOR_NAME_PROTOCOL. Get()
Summary
Retrieves the current set value of iSCSI Initiator Name.
Prototype
(EFIAPI *EFI_ISCSI_INITIATOR_NAME_GET) (
IN EFI_ISCSI_INITIATOR_NAME_PROTOCOL *This,
);
This Pointer to the EFI_ISCSI_INITIATOR_NAME_PROTOCOL instance.
BufferSize Size of the buffer in bytes pointed to by Buffer / Actual size of the variable data buffer.
Buffer Pointer to the buffer for data to be read. The data is a null-terminated UTF-8 encoded string. The maximum
length is 223 characters, including the null-terminator.
This function will retrieve the iSCSI Initiator Name from Non-volatile memory.
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EFI_SUCCESS Data was successfully retrieved into the provided buffer and the BufferSize
was sufﬁcient to handle the iSCSI initiator name
EFI_BUFFER_TOO_SMALL BufferSize is too small for the result. BufferSize will be updated with the
size required to complete the request. Buffer will not be affected.
EFI_INV ALID_PARAMETER BufferSize isNULL .BufferSize andBuffer will not be affected.
EFI_INV ALID_PARAMETER Buffer isNULL .BufferSize andBuffer will not be affected.
EFI_DEVICE_ERROR The iSCSI initiator name could not be retrieved due to a hardware error.
16.2.3 EFI_ISCSI_INITIATOR_NAME_PROTOCOL.Set()
Summary
Sets the iSCSI Initiator Name.
Prototype
(EFIAPI *EFI_ISCSI_INITIATOR_NAME_SET) (
);
This Pointer to the EFI_ISCSI_INITIATOR_NAME_PROTOCOL instance
BufferSize Size of the buffer in bytes pointed to by Buffer.
Buffer Pointer to the buffer for data to be written. The data is a null-terminated UTF-8 encoded string. The maximum
This function will set the iSCSI Initiator Name into Non-volatile memory.
EFI_SUCCESS Data was successfully stored by the protocol
EFI_UNSUPPORTED Platform policies do not allow for data to be written
EFI_INV ALID_PARAMETER BufferSize exceeds the maximum allowed limit. BufferSize will be updated
with the maximum size required to complete the request.
EFI_INV ALID_PARAMETER Buffersize isNULL .BufferSize andBuffer will not be affected
EFI_DEVICE_ERROR The data could not be stored due to a hardware error.
EFI_OUT_OF_RESOURCES Not enough storage is available to hold the data
EFI_PROTOCOL_ERROR Input iSCSI initiator name does not adhere to RFC 3720 (and other related
protocols)
16.2. EFI iSCSI Initiator Name Protocol 656CHAPTER
SEVENTEEN
PROTOCOLS — USB SUPPORT
17.1 USB2 Host Controller Protocol
USB2 Host Controller Protocol andUSB Host Controller Protocol Overview describe the USB2 Host Controller
Protocol. This protocol provides an I/O abstraction for a USB2 Host Controller. The USB2 Host Controller is a
hardware component that interfaces to a Universal Serial Bus (USB). It moves data between system memory and
devices on the USB by processing data structures and generating transactions on the USB. This protocol is used by a
USB Bus Driver to perform all data transaction over the Universal Serial Bus. It also provides services to manage the
USB root hub that is integrated into the USB Host Controller. USB device drivers do not use this protocol directly.
Instead, they use the I/O abstraction produced by the USB Bus Driver. This protocol should only be used by drivers
that require direct access to the USB bus.

SEVENTEEN
17.1.1 USB Host Controller Protocol Overview
The USB Host Controller Protocol is used by code, typically USB bus drivers, running in the EFI boot services
environment, to perform data transactions over a USB bus. In addition, it provides an abstraction for the root hub of
the USB bus.
The interfaces provided in the EFI_USB2_HC_PROTOCOL are used to manage data transactions on a USB bus. It
also provides control methods for the USB root hub. The EFI_USB2_HC_PROTOCOL is designed to support both
USB 1.1 and USB 2.0 - compliant host controllers.
TheEFI_USB2_HC_PROTOCOL abstracts basic functionality that is designed to operate with the EHCI, UHCI and
OHCI standards. By using this protocol, a single USB bus driver can be implemented without knowing if the underly-
ing USB host controller conforms to the XHCI, EHCI, OHCI or the UHCI standards.
Each instance of the EFI_USB2_HC_PROTOCOL corresponds to a USB host controller in a platform. The protocol is
attached to the device handle of a USB host controller that is created by a device driver for the USB host controller’s
parent bus type. For example, a USB host controller that is implemented as a PCI device would require a PCI device
driver to produce an instance of the EFI_USB2_HC_PROTOCOL .
17.1.2 EFI_USB2_HC_PROTOCOL
Summary
Provides basic USB host controller management, basic data transactions over USB bus, and USB root hub access.
GUID
#define EFI_USB2_HC_PROTOCOL_GUID \
{0x3e745226,0x9818,0x45b6,\
{0xa2,0xac,0xd7,0xcd,0x0e,0x8b,0xa2,0xbc}}
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typedef struct _EFI_USB2_HC_PROTOCOL {
EFI_USB2_HC_PROTOCOL_GET_CAPABILITY GetCapability;
EFI_USB2_HC_PROTOCOL_RESET Reset;
EFI_USB2_HC_PROTOCOL_GET_STATE GetState;
EFI_USB2_HC_PROTOCOL_SET_STATE SetState;
EFI_USB2_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer;
EFI_USB2_HC_PROTOCOL_BULK_TRANSFER BulkTransfer;
EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer;
EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER SyncInterruptTransfer;
EFI_USB2_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer;
EFI_USB2_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer;
EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus;
EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature;
EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature
UINT16 MajorRevision;
UINT16 MinorRevision;
} EFI_USB2_HC_PROTOCOL;
GetCapability Retrieves the capabilities of the USB host controller. See the
EFI_USB2_HC_PROTOCOL.GetCapability() function description.
Reset Software reset of USB. See the EFI_USB2_HC_PROTOCOL.Reset() function description.
GetState Retrieves the current state of the USB host controller. See the EFI_USB2_HC_PROTOCOL.GetState()
SetState Sets the USB host controller to a speciﬁc state. See the EFI_USB2_HC_PROTOCOL.SetState() function
ControlTransfer Submits a control transfer to a target USB device. See the
EFI_USB2_HC_PROTOCOL.ControlTransfer() function description.
BulkTransfer Submits a bulk transfer to a bulk endpoint of a USB device. See the
EFI_USB2_HC_PROTOCOL.BulkTransfer() function description.
AsyncInterruptTransfer Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device. See
theEFI_USB2_HC_PROTOCOL.AsyncInterruptTransfer() function description.
SyncInterruptTransfer Submits a synchronous interrupt transfer to an interrupt endpoint of a USB device. See the
EFI_USB2_HC_PROTOCOL.SyncInterruptTransfer() function description.
IsochronousTransfer Submits isochronous transfer to an isochronous endpoint of a USB device. See the
EFI_USB2_HC_PROTOCOL.IsochronousTransfer() function description.
AsyncIsochronousTransfer Submits nonblocking USB isochronous transfer. See the
EFI_USB2_HC_PROTOCOL.AsyncIsochronousTransfer() function description.
GetRootHubPortStatus Retrieves the status of the speciﬁed root hub port. See the
EFI_USB2_HC_PROTOCOL.GetRootHubPortStatus() function description.
SetRootHubPortFeature Sets the feature for the speciﬁed root hub port. See the
EFI_USB2_HC_PROTOCOL.SetRootHubPortFeature() function description.
ClearRootHubPortFeature Clears the feature for the speciﬁed root hub port. See the
EFI_USB2_HC_PROTOCOL.ClearRootHubPortFeature() function description.
MajorRevision The major revision number of the USB host controller. The revision information indicates the release
of the Universal Serial Bus Speciﬁcation with which the host controller is compliant.
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MinorRevision The minor revision number of the USB host controller. The revision information indicates the release
The EFI_USB2_HC_PROTOCOL provides USB host controller management, basic data transactions over a USB
bus, and USB root hub access. A device driver that wishes to manage a USB bus in a system retrieves the
EFI_USB2_HC_PROTOCOL instance that is associated with the USB bus to be managed. A device handle for a USB
host controller will minimally contain an EFI Device Path Protocol instance, and an EFI_USB2_HC_PROTOCOL
instance.
17.1.3 EFI_USB2_HC_PROTOCOL.GetCapability()
Summary
Retrieves the Host Controller capabilities.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_GET_CAPABILITY) (
IN EFI_USB2_HC_PROTOCOL *This,
OUT UINT8 *MaxSpeed,
OUT UINT8 *PortNumber,
OUT UINT8 *Is64BitCapable
);
This A pointer to the EFI_USB2_HC_PROTOCOL instance. Type EFI_USB2_HC_PROTOCOL is deﬁned in USB2
Host Controller Protocol .
MaxSpeed Host controller data transfer speed; see Related Deﬁnitions below for a list of supported transfer speed
values.
PortNumber Number of the root hub ports.
Is64BitCapable TRUE if controller supports 64-bit memory addressing, FALSE otherwise.
#define EFI_USB_SPEED_FULL 0x0000
#define EFI_USB_SPEED_LOW 0x0001
#define EFI_USB_SPEED_HIGH 0x0002
#define EFI_USB_SPEED_SUPER 0x0003
EFI_USB_SPEED_LOW Low speed USB device; data bandwidth is up to 1.5 Mb/s. Supported by USB 1.1
OHCI and UHCI host controllers.
EFI_USB_SPEED_FULL Full speed USB device; data bandwidth is up to 12 Mb/s. Supported by USB 1.1
EFI_USB_SPEED_HIGH High speed USB device; data bandwidth is up to 480 Mb/s. Supported by USB
2.0 EHCI host controllers.
EFI_USB_SPEED_SUPER Super speed USB device; data bandwidth is up to 4.8Gbs. Supported by USB 3.0
XHCI host controllers.
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This function is used to retrieve the host controller capabilities. MaxSpeed indicates the maximum data transfer speed
the controller is capable of; this information is needed for the subsequent transfers. PortNumber is the number of root
hub ports, it is required by the USB bus driver to perform bus enumeration. Is64BitCapable indicates that controller is
capable of 64-bit memory access so that the host controller software can use memory blocks above 4 GiB for the data
EFI_SUCCESS The host controller capabilities were retrieved successfully.
EFI_INV ALID_PARAMETER MaxSpeed or PortNumber or Is64BitCapable is NULL .
EFI_DEVICE_ERROR An error was encountered while attempting to retrieve the capabilities.
17.1.4 EFI_USB2_HC_PROTOCOL.Reset()
Summary
Provides software reset for the USB host controller.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_RESET) (
IN UINT16 Attributes
);
Attributes A bit mask of the reset operation to perform. See Related Deﬁnitions below for a list of the supported bit
mask values.
#define EFI_USB_HC_RESET_GLOBAL 0x0001
#define EFI_USB_HC_RESET_HOST_CONTROLLER 0x0002
#define EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG 0x0004
#define EFI_USB_HC_RESET_HOST_WITH_DEBUG 0x0008
EFI_USB_HC_RESET_GLOBAL If this bit is set, a global reset signal will be sent to the USB bus. This resets all
of the USB bus logic, including the USB host controller hardware and all the devices attached on the USB bus.
EFI_USB_HC_RESET_HOST_CONTROLLER If this bit is set, the USB host controller hardware will be reset.
No reset signal will be sent to the USB bus.
EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG If this bit is set, then a global reset signal will be sent to the
USB bus. This resets all of the USB bus logic, including the USB host controller and all of the devices attached
on the USB bus. If this is an XHCI or EHCI controller and the debug port has been conﬁgured, then this will
still reset the host controller.
EFI_USB_HC_RESET_HOST_WITH_DEBUG If this bit is set, the USB host controller hardware will be reset.

If this is an XHCI or EHCI controller and the debug port has been conﬁgured, then this will still reset the host
17.1. USB2 Host Controller Protocol 660Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function provides a software mechanism to reset a USB host controller. The type of reset is speciﬁed by the
Attributes parameter. If the type of reset speciﬁed by Attributes is not valid, then EFI_INVALID_PARAMETER is
returned. If the reset operation is completed, then EFI_SUCCESS is returned. If the type of reset speciﬁed by Attributes
is not currently supported by the host controller hardware, EFI_UNSUPPORTD is returned. If a device error occurs
during the reset operation, then EFI_DEVICE_ERROR is returned.
Note : For XHCI or EHCI controllers, the EFI_USB_HC_RESET_GLOBAL and
EFI_USB_HC_RESET_HOST_CONTROLLER types of reset do not actually reset the bus if the debug port has
been conﬁgured. In these cases, the function will return EFI_ACCESS_DENIED .
EFI_SUCCESS The reset operation succeeded.
EFI_INV ALID_PARAMETER Attributes is not valid.
EFI_UNSUPPORTED The type of reset speciﬁed by Attributes is not currently supported by the
host controller hardware.
EFI_ACCESS_DENIED Reset operation is rejected due to the debug port being conﬁgured
and active; only EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG or
EFI_USB_HC_RESET_HOST_WITH_DEBUG reset Attributes can be used
to perform reset operation for this host controller.
EFI_DEVICE_ERROR An error was encountered while attempting to perform the reset operation.
17.1.5 EFI_USB2_HC_PROTOCOL.GetState()
Summary
Retrieves current state of the USB host controller.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_GET_STATE) (
OUT EFI_USB_HC_STATE *State
);
State A pointer to the EFI_USB_HC_STATE data structure that indicates current state of the USB host controller.
Type EFI_USB_HC_STATE is deﬁned in Related Deﬁnitions.
EfiUsbHcStateHalt,
EfiUsbHcStateOperational,
EfiUsbHcStateSuspend,
EfiUsbHcStateMaximum
} EFI_USB_HC_STATE;
EﬁUsbHcStateHalt The host controller is in halt state. No USB transactions can occur while in this state. The host
controller can enter this state for three reasons:
• After host controller hardware reset.
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• Explicitly set by software.
• Triggered by a fatal error such as consistency check failure.
EﬁUsbHcStateOperational The host controller is in an operational state. When in this state, the host controller can
execute bus trafﬁc. This state must be explicitly set to enable the USB bus trafﬁc.
EﬁUsbHcStateSuspend The host controller is in the suspend state. No USB transactions can occur while in this
state. The host controller enters this state for the following reasons:
• Triggered when there is no bus trafﬁc for 3 microseconds.
This function is used to retrieve the USB host controller’s current state. The USB Host Controller Protocol pub-
lishes three states for USB host controller, as deﬁned in Related Deﬁnitions below. If State isNULL , then
EFI_INVALID_PARAMETER is returned. If a device error occurs while attempting to retrieve the USB host con-
trollers current state, then EFI_DEVICE_ERROR is returned. Otherwise, the USB host controller’s current state is
returned in State , and EFI_SUCCESS is returned.
EFI_SUCCESS The state information of the host controller was returned in State.
EFI_INV ALID_PARAMETER State is NULL .
EFI_DEVICE_ERROR An error was encountered while attempting to retrieve the host controller’s
17.1.6 EFI_USB2_HC_PROTOCOL.SetState()
Summary
Sets the USB host controller to a speciﬁc state.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_SET_STATE) (
IN EFI_USB_HC_STATE State
);
State Indicates the state of the host controller that will be set. See the deﬁnition and description of the type
EFI_USB_HC_STATE in the EFI_USB2_HC_PROTOCOL.GetState() function description.
This function is used to explicitly set a USB host controller’s state. There are three states deﬁned for the USB host
controller. These are the halt state, the operational state and the suspend state. The Figure below, Software Triggered
State Transitions of a USB Host Controller , illustrates the possible state transitions:
If the state speciﬁed by State is not valid, then EFI_INVALID_PARAMETER is returned. If a device error occurs while
attempting to place the USB host controller into the state speciﬁed by State , then EFI_DEVICE_ERROR is returned.
If the USB host controller is successfully placed in the state speciﬁed by State , then EFI_SUCCESS is returned.
17.1. USB2 Host Controller Protocol 662Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 17.1: Software Triggered State Transitions of a USB Host Controller
EFI_SUCCESS The USB host controller was successfully placed in the state speciﬁed by
State.
EFI_INV ALID_PARAMETER State is invalid.
EFI_DEVICE_ERROR Failed to set the state speciﬁed by State due to device error.
17.1.7 EFI_USB2_HC_PROTOCOL.ControlTransfer()
Summary
Submits control transfer to a target USB device.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_CONTROL_TRANSFER) (
IN UINT8 DeviceAddress,
IN UINT8 DeviceSpeed,
IN UINTN MaximumPacketLength,
IN EFI_USB_DEVICE_REQUEST *Request,
IN EFI_USB_DATA_DIRECTION TransferDirection,
IN OUT VOID *Data OPTIONAL,
IN OUT UINTN *DataLength OPTIONAL,
IN UINTN TimeOut,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
OUT UINT32 *TransferResult
);
UINT8 TranslatorHubAddress,
UINT8 TranslatorPortNumber
} EFI_USB2_HC_TRANSACTION_TRANSLATOR;
17.1. USB2 Host Controller Protocol 663Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DeviceAddress Represents the address of the target device on the USB, which is assigned during USB enumeration.
DeviceSpeed Indicates device speed. See Related Deﬁnitions in GetCapability() for a list of the supported values.
MaximumPacketLength Indicates the maximum packet size that the default control transfer endpoint is capable of
sending or receiving.
Request A pointer to the USB device request that will be sent to the USB device. Refer to UsbControlTransfer()
(USB I/O Protocol ) for the deﬁnition of this function type.
TransferDirection Speciﬁes the data direction for the transfer. There are three values available, EﬁUsbDataIn, EﬁUs-
bDataOut and EﬁUsbNoData. Refer to UsbControlTransfer() (USB I/O Protocol ) for the deﬁnition of this func-
tion type.
Data A pointer to the buffer of data that will be transmitted to USB device or received from USB device.
DataLength On input, indicates the size, in bytes, of the data buffer speciﬁed by Data. On output, indicates the
amount of data actually transferred.
Translator A pointer to the transaction translator data. See “Description” for the detailed information of this data
TimeOut Indicates the maximum time, in milliseconds, which the transfer is allowed to complete.
TransferResult A pointer to the detailed result information generated by this control transfer. Refer to UsbCon-
trolTransfer() (USB I/O Protocol ) for transfer result types ( EFI_USB_ERR_x ).
This function is used to submit a control transfer to a target USB device speciﬁed by DeviceAddress . Control transfers
are intended to support conﬁguration/command/status type communication ﬂows between host and USB device.
There are three control transfer types according to the data phase. If the TransferDirection parameter is EﬁUsbNoData ,
Data isNULL , and DataLength is 0, then no data phase is present in the control transfer. If the TransferDirection
parameter is EﬁUsbDataOut , then Data speciﬁes the data to be transmitted to the device, and DataLength speciﬁes
the number of bytes to transfer to the device. In this case, there is an OUT DATA stage followed by a SETUP stage.
If the TransferDirection parameter is EﬁUsbDataIn , then Data speciﬁes the data to be received from the device, and
DataLength speciﬁes the number of bytes to receive from the device. In this case there is an IN DATA stage followed
by a SETUP stage.
Translator is necessary to perform split transactions on low-speed or full-speed devices connected to a high-speed hub.

Such transaction require the device connection information: device address and the port number of the hub that device
is connected to. This information is passed through the ﬁelds of EFI_USB2_HC_TRANSACTION_TRANSLATOR
structure. See Related Deﬁnitions for the structure ﬁeld names. Translator is passed as NULL for the USB1.1 host
controllers transfers or when the transfer is requested for high-speed device connected to USB2.0 controller.
If the control transfer has completed successfully, then EFI_SUCCESS is returned. If the transfer cannot be completed
within the timeout speciﬁed by TimeOut , then EFI_TIMEOUT is returned. If an error other than timeout occurs
during the USB transfer, then EFI_DEVICE_ERROR is returned and the detailed error code will be returned in the
TransferResult parameter.
EFI_INVALID_PARAMETER is returned if one of the following conditions is satisﬁed:
•TransferDirection is invalid.
•TransferDirection ,Data , and DataLength do not match one of the three control transfer types described above.
•Request pointer is NULL .
•MaximumPacketLength is not valid. If DeviceSpeed isEFI_USB_SPEED_LOW , then MaximumPacketLength
must be 8. If DeviceSpeed isEFI_USB_SPEED_FULL orEFI_USB_SPEED_HIGH , then MaximumPack-
etLength must be 8, 16, 32, or 64. If DeviceSpeed isEFI_USB_SPEED_SUPER , then MaximumPacketLength
must be 512.
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•TransferResult pointer is NULL .
•Translator isNULL while the requested transfer requires split transaction. The conditions of the split transac-
tions are described above in “Description” section.
EFI_SUCCESS The control transfer was completed successfully.
EFI_OUT_OF_RESOURCES The control transfer could not be completed due to a lack of resources.
EFI_INV ALID_PARAMETER Some parameters are invalid. The possible invalid parameters are described
in “Description” above.
EFI_TIMEOUT The control transfer failed due to timeout.
EFI_DEVICE_ERROR The control transfer failed due to host controller or device error. Caller
should check TransferResult for detailed error information.
17.1.8 EFI_USB2_HC_PROTOCOL.BulkTransfer()
Summary
Submits bulk transfer to a bulk endpoint of a USB device.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_BULK_TRANSFER) (
IN UINT8 EndPointAddress,
IN UINT8 DataBuffersNumber,
IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],
IN OUT UINTN *DataLength,
IN OUT UINT8 *DataToggle,
);
EndPointAddress The combination of an endpoint number and an endpoint direction of the target USB device. Each
endpoint address supports data transfer in one direction except the control endpoint (whose default endpoint
address is 0). It is the caller’s responsibility to make sure that the EndPointAddress represents a bulk endpoint.
DeviceSpeed Indicates device speed. The supported values are EFI_USB_SPEED_FULL,EFI_USB_SPEED_HIGH
orEFI_USB_SPEED_SUPER. .
MaximumPacketLength Indicates the maximum packet size the target endpoint is capable of sending or receiving.
DataBuffersNumber Number of data buffers prepared for the transfer.
Data Array of pointers to the buffers of data that will be transmitted to USB device or received from USB device.
17.1. USB2 Host Controller Protocol 665Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DataLength When input, indicates the size, in bytes, of the data buffers speciﬁed by Data . When output, indicates
the actually transferred data size.
DataToggle A pointer to the data toggle value. On input, it indicates the initial data toggle value the bulk transfer
should adopt; on output, it is updated to indicate the data toggle value of the subsequent bulk transfer.
Translator A pointer to the transaction translator data. See ControlTransfer() “Description” for the detailed informa-
tion of this data structure.
TransferResult A pointer to the detailed result information of the bulk transfer. Refer to UsbControlTransfer() in
USB I/O Protocol for transfer result types ( EFI_USB_ERR_x ).
This function is used to submit bulk transfer to a target endpoint of a USB device. The target endpoint is speciﬁed
byDeviceAddress andEndpointAddress . Bulk transfers are designed to support devices that need to communicate
relatively large amounts of data at highly variable times where the transfer can use any available bandwidth. Bulk
transfers can be used only by full-speed and high-speed devices.
High-speed bulk transfers can be performed using multiple data buffers. The number of buffers that are actually
prepared for the transfer is speciﬁed by DataBuffersNumber . For full-speed bulk transfers this value is ignored.
Data represents a list of pointers to the data buffers. For full-speed bulk transfers only the data pointed by Data[0]
shall be used. For high-speed transfers depending on DataLength there several data buffers can be used. The to-
tal number of buffers must not exceed EFI_USB_MAX_BULK_BUFFER_NUM . See Related Deﬁnitions for the
EFI_USB_MAX_BULK_BUFFER_NUM value.
The data transfer direction is determined by the endpoint direction that is encoded in the EndPointAddress parameter.
Refer to USB Speciﬁcation, Revision 2.0 on the Endpoint Address encoding.
TheDataToggle parameter is used to track target endpoint’s data sequence toggle bits. The USB provides a mechanism
to guarantee data packet synchronization between data transmitter and receiver across multiple transactions. The data
packet synchronization is achieved with the data sequence toggle bits and the DATA0/DATA1 PIDs. A bulk endpoint’s
toggle sequence is initialized to DATA0 when the endpoint experiences a conﬁguration event. It toggles between
DATA0 and DATA1 in each successive data transfer. It is host’s responsibility to track the bulk endpoint’s data toggle
sequence and set the correct value for each data packet. The input DataToggle value points to the data toggle value
for the ﬁrst data packet of this bulk transfer; the output DataToggle value points to the data toggle value for the last
successfully transferred data packet of this bulk transfer. The caller should record the data toggle value for use in
subsequent bulk transfers to the same endpoint.
If the bulk transfer is successful, then EFI_SUCCESS is returned. If USB transfer cannot be completed within the
timeout speciﬁed by Timeout , then EFI_TIMEOUT is returned. If an error other than timeout occurs during the USB
transfer, then EFI_DEVICE_ERROR is returned and the detailed status code is returned in TransferResult .
•Data isNULL .
•DataLength is 0.
•DeviceSpeed is not valid; the legal values are EFI_USB_SPEED_FULL ,EFI_USB_SPEED_HIGH, or
EFI_USB_SPEED_SUPER.
•MaximumPacketLength is not valid. The legal value of this parameter is 64 or less for full-speed, 512 or less for
high-speed, and 1024 or less for super-speed transactions.
•DataToggle points to a value other than 0 and 1.
•TransferResult isNULL .
17.1. USB2 Host Controller Protocol 666Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The bulk transfer was completed successfully.
EFI_OUT_OF_RESOURCES The bulk transfer could not be submitted due to lack of resource.
EFI_TIMEOUT The bulk transfer failed due to timeout.
EFI_DEVICE_ERROR The bulk transfer failed due to host controller or device error. Caller should
check TransferResult for detailed error information.
17.1.9 EFI_USB2_HC_PROTOCOL.AsyncInterruptTransfer()
Summary
Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER) (
IN BOOLEAN IsNewTransfer,
IN UINTN PollingInterval OPTIONAL,
IN UINTN DataLength OPTIONAL,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator OPTIONAL,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction OPTIONAL,
IN VOID *Context OPTIONAL
);

Summary
Prototype
typedef
);
address is zero). It is the caller’s responsibility to make sure that the EndPointAddress represents an interrupt
endpoint.
DeviceSpeed Indicates device speed. See Related Deﬁnitions inEFI_USB2_HC_PROTOCOL.ControlTransfer() for
a list of the supported values.
IsNewTransfer IfTRUE , an asynchronous interrupt pipe is built between the host and the target interrupt endpoint.
IfFALSE , the speciﬁed asynchronous interrupt pipe is canceled. If TRUE , and an interrupt transfer exists for
the target end point, then EFI_INVALID_PARAMETER is returned.
DataToggle A pointer to the data toggle value. On input, it is valid when IsNewTransfer isTRUE , and it indicates
the initial data toggle value the asynchronous interrupt transfer should adopt. On output, it is valid when IsNew-
17.1. USB2 Host Controller Protocol 667Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Transfer isFALSE , and it is updated to indicate the data toggle value of the subsequent asynchronous interrupt
transfer.
PollingInterval Indicates the interval, in milliseconds, that the asynchronous interrupt transfer is polled. This param-
eter is required when IsNewTransfer isTRUE .
DataLength Indicates the length of data to be received at the rate speciﬁed by PollingInterval from the target asyn-
chronous interrupt endpoint. This parameter is only required when IsNewTransfer isTRUE .
Translator A pointer to the transaction translator data.
CallBackFunction The Callback function. This function is called at the rate speciﬁed by PollingInterval . This
parameter is only required when IsNewTransfer isTRUE . Refer to UsbAsyncInterruptTransfer() inUSB I/O
Protocol for the deﬁnition of this function type.
Context The context that is passed to the CallBackFunction . This is an optional parameter and may be NULL .
This function is used to submit asynchronous interrupt transfer to a target endpoint of a USB device. The target end-
point is speciﬁed by DeviceAddress andEndpointAddress . In the USB Speciﬁcation, Revision 2.0, interrupt transfer
is one of the four USB transfer types. In the EFI_USB2_HC_PROTOCOL , interrupt transfer is divided further into
synchronous interrupt transfer and asynchronous interrupt transfer.
An asynchronous interrupt transfer is typically used to query a device’s status at a ﬁxed rate. For example, keyboard,
mouse, and hub devices use this type of transfer to query their interrupt endpoints at a ﬁxed rate. The asynchronous
interrupt transfer is intended to support the interrupt transfer type of “submit once, execute periodically.” Unless an
explicit request is made, the asynchronous transfer will never retire.
IfIsNewTransfer isTRUE , then an interrupt transfer is started at a ﬁxed rate. The rate is speciﬁed by PollingInterval ,
the size of the receive buffer is speciﬁed by DataLength , and the callback function is speciﬁed by CallBackFunction .
Context speciﬁes an optional context that is passed to the CallBackFunction each time it is called. The CallBackFunc-
tionis intended to provide a means for the host to periodically process interrupt transfer data.
IfIsNewTransfer isTRUE , and an interrupt transfer exists for the target end point, then EFI_INVALID_PARAMETER
IfIsNewTransfer isFALSE , then the interrupt transfer is canceled.
• Data transfer direction indicated by EndPointAddress is other than EﬁUsbDataIn.
•IsNewTransfer isTRUE andDataLength is 0.
•IsNewTransfer isTRUE andDataToggle points to a value other than 0 and 1.
•IsNewTransfer isTRUE andPollingInterval is not in the range 1..255.
•IsNewTransfer requested where an interrupt transfer exists for the target end point.
EFI_SUCCESS The asynchronous interrupt transfer request has been successfully submitted
or canceled.
in “Description” above. When an interrupt transfer exists for the target end
point and a new transfer is requested, EFI_INV ALID_PARAMETER is re-
turned.
17.1. USB2 Host Controller Protocol 668Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.1.10 EFI_USB2_HC_PROTOCOL.SyncInterruptTransfer()
Summary
Submits synchronous interrupt transfer to an interrupt endpoint of a USB device.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER) (
IN OUT VOID *Data,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator
);
endpoint.
DataLength On input, the size, in bytes, of the data buffer speciﬁed by Data . On output, the number of bytes
transferred.
DataToggle A pointer to the data toggle value. On input, it indicates the initial data toggle value the synchronous
interrupt transfer should adopt; on output, it is updated to indicate the data toggle value of the subsequent
synchronous interrupt transfer.
TransferResult A pointer to the detailed result information from the synchronous interrupt transfer. Refer to Usb-
ControlTransfer() inUSB I/O Protocol for transfer result types ( EFI_USB_ERR_x ).
This function is used to submit a synchronous interrupt transfer to a target endpoint of a USB device. The target
endpoint is speciﬁed by DeviceAddress andEndpointAddress . In the USB Speciﬁcation, Revision2.0, interrupt transfer
17.1. USB2 Host Controller Protocol 669Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The synchronous interrupt transfer is designed to retrieve small amounts of data from a USB device through an inter-
rupt endpoint. A synchronous interrupt transfer is only executed once for each request. This is the most signiﬁcant
difference from the asynchronous interrupt transfer.
If the synchronous interrupt transfer is successful, then EFI_SUCCESS is returned. If the USB transfer cannot be
completed within the timeout speciﬁed by Timeout , then EFI_TIMEOUT is returned. If an error other than timeout
occurs during the USB transfer, then EFI_DEVICE_ERROR is returned and the detailed status code is returned in
TransferResult .
•MaximumPacketLength is not valid. The legal value of this parameter should be 3072 or less for high-speed
device, 64 or less for a full-speed device; for a slow device, it is limited to 8 or less. For the full-speed device, it
should be 8, 16, 32, or 64; for the slow device, it is limited to 8.
EFI_SUCCESS The synchronous interrupt transfer was completed successfully.
EFI_OUT_OF_RESOURCES The synchronous interrupt transfer could not be submitted due to lack of
resource.

resource.
EFI_TIMEOUT The synchronous interrupt transfer failed due to timeout.
EFI_DEVICE_ERROR The synchronous interrupt transfer failed due to host controller or device
error. Caller should check TransferResult for detailed error information.
17.1.11 EFI_USB2_HC_PROTOCOL.IsochronousTransfer()
Summary
Submits isochronous transfer to an isochronous endpoint of a USB device.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_ISOCHRONOUS_TRANSFER) (
IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],
IN UINTN DataLength,
);
17.1. USB2 Host Controller Protocol 670Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_USB_MAX_ISO_BUFFER_NUM 7
#define EFI_USB_MAX_ISO_BUFFER_NUM1 2
address is 0). It is the caller’s responsibility to make sure that the EndPointAddress represents an isochronous
endpoint.
DeviceSpeed Indicates device speed. The supported values are EFI_USB_SPEED_FULL ,EFI_USB_SPEED_HIGH ,
orEFI_USB_SPEED_SUPER .
For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-frame
data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved.
DataLength Speciﬁes the length, in bytes, of the data to be sent to or received from the USB device.
TransferResult A pointer to the detail result information of the isochronous transfer. Refer to UsbControlTransfer()
inUSB I/O Protocol for transfer result types ( EFI_USB_ERR_x ).
This function is used to submit isochronous transfer to a target endpoint of a USB device. The target endpoint is
speciﬁed by DeviceAddress andEndpointAddress . Isochronous transfers are used when working with isochronous
date. It provides periodic, continuous communication between the host and a device. Isochronous transfers can be
used only by full-speed, high-speed, and super-speed devices.
High-speed isochronous transfers can be performed using multiple data buffers. The number of buffers that are actually
prepared for the transfer is speciﬁed by DataBuffersNumber . For full-speed isochronous transfers this value is ignored.
Data represents a list of pointers to the data buffers. For full-speed isochronous transfers only the data pointed by
Data[0] shall be used. For high-speed isochronous transfers and for the split transactions depending on DataLength
there several data buffers can be used. For the high-speed isochronous transfers the total number of buffers must not ex-
ceed EFI_USB_MAX_ISO_BUFFER_NUM . For split transactions performed on full-speed device by high-speed host
controller the total number of buffers is limited to EFI_USB_MAX_ISO_BUFFER_NUM1 SeeRelated Deﬁnitions
for the EFI_USB_MAX_ISO_BUFFER_NUM andEFI_USB_MAX_ISO_BUFFER_NUM1 values.
If the isochronous transfer is successful, then EFI_SUCCESS is returned. The isochronous transfer is designed to be
completed within one USB frame time, if it cannot be completed, EFI_TIMEOUT is returned. If an error other than
timeout occurs during the USB transfer, then EFI_DEVICE_ERROR is returned and the detailed status code will be
returned in TransferResult .
•DeviceSpeed is not one of the supported values listed above.
17.1. USB2 Host Controller Protocol 671Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
•MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed devices, and 1024
or less for high-speed and super-speed devices.
EFI_SUCCESS The isochronous transfer was completed successfully.
EFI_OUT_OF_RESOURCES The isochronous transfer could not be submitted due to lack of resource.
EFI_TIMEOUT The isochronous transfer cannot be completed within the one USB frame
time.
EFI_DEVICE_ERROR The isochronous transfer failed due to host controller or device error. Caller
EFI_UNSUPPORTED The implementation doesn’t support an Isochronous transfer function.
17.1.12 EFI_USB2_HC_PROTOCOL.AsyncIsochronousTransfer()
Summary
Submits nonblocking isochronous transfer to an isochronous endpoint of a USB device.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER) (
IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack,
);
address is zero). It is the caller’s responsibility to make sure that the EndPointAddress represents an isochronous
endpoint.
17.1. USB2 Host Controller Protocol 672Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IsochronousCallback The Callback function. This function is called if the requested isochronous transfer is com-
pleted. Refer to UsbAsyncInterruptTransfer() inUSB I/O Protocol for the deﬁnition of this function type.
Context Data passed to the IsochronousCallback function. This is an optional parameter and may be NULL .
This is an asynchronous type of USB isochronous transfer. If the caller submits a USB isochronous transfer re-
quest through this function, this function will return immediately. When the isochronous transfer completes, the
IsochronousCallback function will be triggered, the caller can know the transfer results. If the transfer is successful,
the caller can get the data received or sent in this callback function.
The target endpoint is speciﬁed by DeviceAddress andEndpointAddress . Isochronous transfers are used when working
with isochronous date. It provides periodic, continuous communication between the host and a device. Isochronous
transfers can be used only by full-speed, high-speed, and super-speed devices.
Data represents a list of pointers to the data buffers. For full-speed isochronous transfers only the data pointed

byData[0] shall be used. For high-speed isochronous transfers and for the split transactions depending on
DataLength there several data buffers can be used. For the high-speed isochronous transfers the total number of
buffers must not exceed EFI_USB_MAX_ISO_BUFFER_NUM . For split transactions performed on full-speed de-
vice by high-speed host controller the total number of buffers is limited to EFI_USB_MAX_ISO_BUFFER_NUM1
See Related Deﬁnitions in IsochronousTransfer() section for the EFI_USB_MAX_ISO_BUFFER_NUM and
EFI_USB_MAX_ISO_BUFFER_NUM1 values.
•MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed devices and 1024
EFI_SUCCESS The asynchronous isochronous transfer was completed successfully.
EFI_OUT_OF_RESOURCES The asynchronous isochronous transfer could not be submitted due to lack
of resource.
EFI_UNSUPPORTED The implementation doesn’t support Isochronous transfer function
17.1. USB2 Host Controller Protocol 673Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.1.13 EFI_USB2_HC_PROTOCOL.GetRootHubPortStatus()
Summary
Retrieves the current status of a USB root hub port.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS) (
IN UINT8 PortNumber,
OUT EFI_USB_PORT_STATUS *PortStatus
);
PortNumber Speciﬁes the root hub port from which the status is to be retrieved. This value is zero based. For
example, if a root hub has two ports, then the ﬁrst port is numbered 0, and the second port is numbered 1.
PortStatus A pointer to the current port status bits and port status change bits. The type EFI_USB_PORT_STATUS
is deﬁned in Related Deﬁnitions below.
UINT16 PortStatus;
UINT16 PortChangeStatus;
} EFI_USB_PORT_STATUS;
//**************************************************
// EFI_USB_PORT_STATUS.PortStatus bit definition
#define USB_PORT_STAT_CONNECTION 0x0001
#define USB_PORT_STAT_ENABLE 0x0002
#define USB_PORT_STAT_SUSPEND 0x0004
#define USB_PORT_STAT_OVERCURRENT 0x0008
#define USB_PORT_STAT_RESET 0x0010
#define USB_PORT_STAT_POWER 0x0100
#define USB_PORT_STAT_LOW_SPEED 0x0200
#define USB_PORT_STAT_HIGH_SPEED 0x0400
#define USB_PORT_STAT_SUPER_SPEED 0x0800
#define USB_PORT_STAT_OWNER 0x2000
// EFI_USB_PORT_STATUS.PortChangeStatus bit definition
#define USB_PORT_STAT_C_CONNECTION 0x0001
#define USB_PORT_STAT_C_ENABLE 0x0002
#define USB_PORT_STAT_C_SUSPEND 0x0004
#define USB_PORT_STAT_C_OVERCURRENT 0x0008
#define USB_PORT_STAT_C_RESET 0x0010
PortStatus Contains current port status bitmap. The root hub port status bitmap is uniﬁed with the USB hub port
status bitmap. See Table below, USB Hub Port Status Bitmap , for a reference, which is borrowed from Chapter
17.1. USB2 Host Controller Protocol 674Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11, Hub Speciﬁcation, of USB Speciﬁcation, Revision 1.1.
PortChangeStatus Contains current port status change bitmap. The root hub port change status bitmap is uniﬁed
with the USB hub port status bitmap. See Table below, Hub Port Change Status Bitmap for a reference, which
is borrowed from Chapter 11, Hub Speciﬁcation, of USB Speciﬁcation, Revision 1.1.
Table 17.10: USB Hub Port Status Bitmap
Bit Description
0
Current Connect Status: (USB_PORT_STAT_CONNECTION) This ﬁeld reﬂects whether or not
a device is currently connected to this port.
0 = No device is present
1 = A device is present on this port
1
Port Enable / Disabled: (USB_PORT_STAT_ENABLE) Ports can be enabled by software only.
Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by
software.
0 = Port is disabled
1 = Port is enabled
2
Suspend: (USB_PORT_STAT_SUSPEND) This ﬁeld indicates whether or not the device on this
port is suspended.
0 = Not suspended
1 = Suspended
3
Over-current Indicator: (USB_PORT_STAT_OVERCURRENT) This ﬁeld is used to indicate that
the current drain on the port exceeds the speciﬁed maximum.
0 = All no over-current condition exists on this port
1 = An over-current condition exists on this port
4
Reset: (USB_PORT_STAT_RESET) Indicates whether port is in reset state.
0 = Port is not in reset state
1 = Port is in reset state
5-7 Reserved These bits return 0 when read.
8
Port Power: (USB_PORT_STAT_POWER) This ﬁeld reﬂects a port’s logical, power control state.
0 = This port is in the Powered-off state
1 = This port is not in the Powered-off state
9
Low Speed Device Attached: (USB_PORT_STAT_LOW_SPEED) This is relevant only if a
device is attached.
0 = Full-speed device attached to this port
1 = Low-speed device attached to this port
17.1. USB2 Host Controller Protocol 675Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 17.10 – continued from previous page
10
High Speed Device Attached: (USB_PORT_STAT_HIGH_SPEED) This ﬁeld indicates whether
the connected device is high-speed device
0 = High-speed device is not attached to this port
1 = High-speed device attached to this port NOTE: this bit has precedence over Bit 9; if set, bit 9
must be ignored.
11
Super Speed Device Attached: (USB_PORT_STAT_SUPER_SPEED) This ﬁeld indicates
whether the connected device is a super-speed device.
0 = Super-speed device is not attached to this port.
1 = Super-speed device is attached to this port. NOTE: This bit bas precedence over Bit 9 and Bit
10; if set bits 9,10 must be ignored.
12
Reserved.
Bit returns 0 when read.
13
The host controller owns the speciﬁed port.
0 = Controller does not own the port.
1 = Controller owns the port
14-15
Reserved
These bits return 0 when read.
Table 17.11: Hub Port Change Status Bitmap
0
Connect Status Change: (USB_PORT_STAT_C_CONNECTION) Indicates a change has
occurred in the port’s Current Connect Status.
0 = No change has occurred to Current Connect status
1 = Current Connect status has changed
1
Port Enable /Disable Change: (USB_PORT_STAT_C _ENABLE)
0 = No change
1 = Port enabled/disabled status has changed
2
Suspend Change: (USB_PORT_STAT_C _SUSPEND) This ﬁeld indicates a change in the
host-visible suspend state of the attached device.
1 = Resume complete
17.1. USB2 Host Controller Protocol 676Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 17.11 – continued from previous page
3
Over-Current Indicator Change: (USB_PORT_STAT_C_OVERCURRENT)
0 = No change has occurred to Over-Current Indicator
1 = Over-Current Indicator has changed
4
Reset Change: (USB_PORT_STAT_C_RESET) This ﬁeld is set when reset processing on this
port is complete.
1 = Reset complete
5-15
Reserved.
This function is used to retrieve the status of the root hub port speciﬁed by PortNumber .
EFI_USB_PORT_STATUS found in Related Deﬁnitions EFI_USB2_HC_PROTOCOL.GetRootHubPortStatus() de-
scribes the port status of a speciﬁed USB port. This data structure is designed to be common to both a USB root hub
port and a USB hub port.
The number of root hub ports attached to the USB host controller can be determined with the function
EFI_USB2_HC_PROTOCOL.GetRootHubPortStatus() . IfPortNumber is greater than or equal to the number of ports
returned by GetRootHubPortNumber() , then EFI_INVALID_PARAMETER is returned. Otherwise, the status of the
USB root hub port is returned in PortStatus , and EFI_SUCCESS is returned.
EFI_SUCCESS The status of the USB root hub port speciﬁed by PortNumber was returned
in PortStatus.
EFI_INV ALID_PARAMETER PortNumber is invalid.
17.1.14 EFI_USB2_HC_PROTOCOL.SetRootHubPortFeature()
Summary
Sets a feature for the speciﬁed root hub port.
Prototype
typedef
(EFIAPI *EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE) (
IN EFI_USB_PORT_FEATURE PortFeature
);
17.1. USB2 Host Controller Protocol 677Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PortNumber Speciﬁes the root hub port whose feature is requested to be set. This value is zero based. For example,
if a root hub has two ports, then the ﬁrst port is number 0, and the second port is numbered 1.

Summary
Prototype
typedef
);
PortFeature Indicates the feature selector associated with the feature set request. The port feature indicator is deﬁned
inRelated Deﬁnitions and The Table below, USB Port Features .
EfiUsbPortEnable = 1,
EfiUsbPortSuspend = 2,
EfiUsbPortReset = 4,
EfiUsbPortPower = 8,
EfiUsbPortOwner = 13,
EfiUsbPortConnectChange = 16,
EfiUsbPortEnableChange = 17,
EfiUsbPortSuspendChange = 18,
EfiUsbPortOverCurrentChange = 19,
EfiUsbPortResetChange = 20
} EFI_USB_PORT_FEATURE;
The feature values speciﬁed in the enumeration variable have special meaning. Each value indicates its bit index in
the port status and status change bitmaps, if combines these two bitmaps into a 32-bit bitmap. The meaning of each
port feature is listed in Table below, USB Port Features .
Table 17.12: USB Port Features
Port Feature For SetRootHubPortFeature For Cl earRootHubPortFeature
EﬁUsbPortEnable Enable the given port of the root
hub.Disable the given port of the root
hub.
EﬁUsbPortSuspend Put the given port into suspend state. Restore the given port from the pre-
vious suspend state.
EﬁUsbPortReset Reset the given port of the root hub. Clear the RESET signal for the
given port of the root hub.
EﬁUsbPortPower Power the given port. Shutdown the power from the given
port.
EﬁUsbPortOwner N/A. Releases the port ownership of this
port to companion host controller.
Ef iUsbPortConnectChange N/A. Clear USB_P
ORT_STAT_C_CONNECTION bit
of the given port of the root hub.
E ﬁUsbPortEnableChange N/A. Clear U
SB_PORT_STAT_C_ENABLE
bit of the given port of the root hub.
Ef iUsbPortSuspendChange N/A. Clear US
B_PORT_STAT_C_SUSPEND
EﬁUsb PortOverCurrentChange N/A. Clear USB_PO
RT_STAT_C_OVERCURRENT bit
EﬁUsbPortResetChange N/A. Clear
USB_PORT_STAT_C_RESET
17.1. USB2 Host Controller Protocol 678Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function sets the feature speciﬁed by PortFeature for the USB root hub port speciﬁed by PortNumber . Setting a
feature enables that feature or starts a process associated with that feature. For the meanings about the deﬁned features,
refer to Table USB Hub Port Status Bitmap and Table Hub Port Change Status Bitmap .
EFI_USB2_HC_PROTOCOL.GetRootHubPortStatus() . If PortNumber is greater than or equal to the number of
ports returned by GetRootHubPortNumber() , then EFI_INVALID_PARAMETER is returned. If PortFeature is not
EﬁUsbPortEnable ,EﬁUsbPortSuspend ,EﬁUsbPortReset norEﬁUsbPortPower , then EFI_INVALID_PARAMETER is
returned.
EFI_SUCCESS The feature speciﬁed by PortFeature was set for the USB root hub port
speciﬁed by PortNumber.
EFI_INV ALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function.
17.1.15 EFI_USB2_HC_PROTOCOL.ClearRootHubPortFeature()
Summary
Clears a feature for the speciﬁed root hub port.
Prototype
typede
(EFIAPI *EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE) (
IN EFI_USB2_HC_PROTOCOL *This
);
This A pointer to the EFI_USB2_HC_PROTOCOL instance, which is deﬁned in USB2 Host Controller Protocol .
PortNumber Speciﬁes the root hub port whose feature is requested to be cleared. This value is zero-based. For
example, if a root hub has two ports, then the ﬁrst port is number 0, and the second port is numbered 1.
PortFeature Indicates the feature selector associated with the feature clear request. The port feature indicator
EFI_USB_PORT_FEATURE is deﬁned in Section 17.1.14 in the “Related Deﬁnitions” section, and in Table
17.12.
This function clears the feature speciﬁed by PortFeature for the USB root hub port speciﬁed by PortNumber. Clearing
a feature disables that feature or stops a process associated with that feature. For the meanings about the deﬁned
features, refer to Table USB Hub Port Status Bitmap and Table Hub Port Change Status Bitmap .
EFI_USB2_HC_PROTOCOL.GetRootHubPortStatus() . If PortNumber is greater than or equal to the num-
ber of ports returned by GetRootHubPortNumber(), then EFI_INV ALID_PARAMETER is returned. If Port-
Feature is not EﬁUsbPortEnable, EﬁUsbPortSuspend, EﬁUsbPortPower, EﬁUsbPortConnectChange, EﬁUsb-
PortResetChange, EﬁUsbPortEnableChange, EﬁUsbPortSuspendChange, or EﬁUsbPortOverCurrentChange, then
17.1. USB2 Host Controller Protocol 679Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The feature speciﬁed by PortFeature was cleared for the USB root hub port
EFI_INV ALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
17.2 USB Driver Model
17.2.1 Scope
Section USB Driver Model describes the USB Driver Model. This includes the behavior of USB Bus Drivers, the
behavior of a USB Device Drivers, and a detailed description of the EFI USB I/O Protocol. This document provides
enough material to implement a USB Bus Driver, and the tools required to design and implement USB Device Drivers.
It does not provide any information on speciﬁc USB devices.
The material contained in this section is designed to extend this speciﬁcation and the UEFI Driver Model in a way
that supports USB device drivers and USB bus drivers. These extensions are provided in the form of USB speciﬁc
protocols. This document provides the information required to implement a USB Bus Driver in system ﬁrmware. The
document also contains the information required by driver writers to design and implement USB Device Drivers that
a platform may need to boot a UEFI-compliant OS.
The USB Driver Model described here is intended to be a foundation on which a USB Bus Driver and a wide variety
of USB Device Drivers can be created. USB Driver Model Overview
The USB Driver Stack includes the USB Bus Driver, USB Host Controller Driver, and individual USB device drivers.
Fig. 17.2: USB Bus Controller Handle
In the USB Bus Driver Design, the USB Bus Controller is managed by two drivers. One is USB Host Controller Driver,
which consumes its parent bus EFI_XYZ_IO_PROTOCOL , and produces EFI_USB2_HC_PROTOCOL, and attaches
it to the Bus Controller Handle. The other one is USB Bus Driver, which consumes EFI_USB2_HC_PROTOCOL ,
and performs bus enumeration. Figure USB Bus Controller Handle shows protocols that are attached to the USB Bus
Controller Handle. Detailed descriptions are presented in the following sections.
17.2. USB Driver Model 680Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.2.2 USB Bus Driver
USB Bus Driver performs periodic Enumeration on the USB Bus. In USB bus enumeration, when a new USB con-
troller is found, the bus driver does some standard conﬁguration for that new controller, and creates a device handle
for it. The EFI_USB_IO_PROTOCOL and EFI_DEVICE_PATH_PROTOCOL are attached to the device handle so
that the USB controller can be accessed. The USB Bus Driver is also responsible for connecting USB device drivers to
USB controllers. When a USB device is detached from a USB bus, the USB bus driver will stop that USB controller,
and uninstall the EFI_USB_IO_PROTOCOL and the EFI_DEVICE_PATH_PROTOCOL from that handle. A detailed
description is given in USB Hot-Plug Event .
17.2.2.1 USB Bus Driver Entry Point
Like all other device drivers, the entry point for a USB Bus Driver attaches the EFI Driver Binding Protocol to image
handle of the USB Bus Driver.
17.2.2.2 Driver Binding Protocol for USB Bus Drivers
The Driver Binding Protocol contains three services. These are:
EFI_DRIVER_BINDING_PROTOCOL.Supported() ,
EFI_DRIVER_BINDING_PROTOCOL.Start() and
Supported() tests to see if the USB Bus Driver can manage a device handle. A USB Bus Driver can only manage a
device handle that contains EFI_USB2_HC_PROTOCOL .
The general idea is that the USB Bus Driver is a generic driver. Since there are several types of USB Host Controllers,
anEFI_USB2_HC_PROTOCOL is used to abstract the host controller interface. Actually, a USB Bus Driver only
requires an EFI_USB2_HC_PROTOCOL .
TheStart() function tells the USB Bus Driver to start managing the USB Bus. In this function, the USB Bus Driver
creates a device handle for the root hub, and creates a timer to monitor root hub connection changes.
The Stop() function tells the USB Bus Driver to stop managing a USB Host Bus Controller. The Stop() function
simply deconﬁgures the devices attached to the root hub. The deconﬁguration is a recursive process. If the device to
be deconﬁgured is a USB hub, then all USB devices attached to its downstream ports will be deconﬁgured ﬁrst, then

itself. If all of the child devices handles have been destroyed then the EFI_USB2_HC_PROTOCOL is closed. Finally,
theStop() unction will then place the USB Host Bus Controller in a quiescent state.
17.2.2.3 USB Hot-Plug Event
Hot-Plug is one of the most important features provided by USB. A USB bus driver implements this feature through
two methods. There are two types of hubs deﬁned in the USB speciﬁcation. One is the USB root hub, which is
implemented in the USB Host controller. A timer event is created for the root hub. The other one is a USB Hub. An
event is created for each hub that is correctly conﬁgured. All these events are associated with the same trigger which
is USB bus numerator.
When USB bus enumeration is triggered, the USB Bus Driver checks the source of the event. This is required because
the root hub differs from standard USB hub in checking the hub status. The status of a root hub is retrieved through
theEFI_USB2_HC_PROTOCOL , and that status of a standard USB hub is retrieved through a USB control transfer.
A detailed description of the enumeration process is presented in the next section.
17.2. USB Driver Model 681Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.2.2.4 USB Bus Enumeration
When the periodic timer or the hubs notify event is signaled, the USB Bus Driver will perform bus numeration.
1. Determine if the event is from the roothub or a standard USB hub.
2. Determine the port on which the connection change event occurred.
3. Determine if it is a connection change or a disconnection change.
4. If a connect change is detected, then a new device has been attached. Perform the following:
a – Reset and enable that port.
b – Conﬁgure the new device.
c – Parse the device conﬁguration descriptors; get all of its interface descriptors (i.e., all USB controllers), and
conﬁgure each interface.
d – Create a new handle for each interface (USB Controller) within the USB device. Attach the EFI Device Path
Protocol , and EFI_USB_IO_PROTOCOL to each handle.
e – Connect the USB Controller to a USB device driver with the Boot Service
EFI_BOOT_SERVICES.ConnectController() if applicable.
f – If the USB Controller is a USB hub, create a Hub notify event which is associated with the USB Bus
Enumerator, and submit an Asynchronous Interrupt Transfer Request ( USB I/O Protocol ).
5. If a disconnect change, then a device has been detached from the USB Bus. Perform the following:
a – If the device is not a USB Hub, then ﬁnd and deconﬁgure the USB Controllers within the de-
vice. Then, stop each USB controller with EFI_BOOT_SERVICES.DisconnectController() , and uninstall the
EFI_DEVICE_PATH_PROTOCOL and the EFI_USB_IO_PROTOCOL from the controller’s handle. If the
EFI_BOOT_SERVICES.DisconnectController() call fails this process must be retried on a subsequent timer
tick.
b – If the USB controller is USB hub controller, ﬁrst ﬁnd and deconﬁgure all its downstream USB devices
(this is a recursive process, since there may be additional USB hub controllers on the downstream ports), then
deconﬁgure USB hub controller itself.
17.2.3 USB Device Driver
A USB Device Driver manages a USB Controller and produces a device abstraction for use by a preboot application.
17.2.3.1 USB Device Driver Entry Point
Like all other device drivers, the entry point for a USB Device Driver attaches EFI Driver Binding Protocol to image
handle of the USB Device Driver.
17.2. USB Driver Model 682Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.2.3.2 Driver Binding Protocol for USB DeviceDrivers
TheSupported() tests to see if the USB Device Driver can manage a device handle. This function checks to see if a
controller can be managed by the USB Device Driver. This is done by opening the See EFI_USB_IO_PROTOCOL
bus abstraction on the USB Controller handle, and using the EFI_USB_IO_PROTOCOL services to determine if this
USB Controller matches the proﬁle that the USB Device Driver is capable of managing.
The Start() function tells the USB Device Driver to start managing a USB Controller. It opens the
EFI_USB_IO_PROTOCOL instance from the handle for the USB Controller. This protocol instance is used to per-
form USB packet transmission over the USB bus. For example, if the USB controller is USB keyboard, then the
USB keyboard driver would produce and install the EFI_SIMPLE_TEXT_INPUT_PROTOCOL to the USB controller
handle.
The Stop() function tells the USB Device Driver to stop managing a USB Controller. It removes the I/O ab-
straction protocol instance previously installed in Start() from the USB controller handle. It then closes the
EFI_USB_IO_PROTOCOL .
17.2.4 USB I/O Protocol
This section provides a detailed description of the EFI_USB_IO_PROTOCOL . This protocol is used by code, typically
drivers, running in the EFI boot services environment to access USB devices like USB keyboards, mice and mass
storage devices. In particular, functions for managing devices on USB buses are deﬁned here.
The interfaces provided in the EFI_USB_IO_PROTOCOL are for performing basic operations to access USB devices.
Typically, USB devices are accessed through the four different transfers types:
Controller Transfer Typically used to conﬁgure the USB device into an operation mode.
Interrupt Transfer Typically used to get periodic small amount of data, like USB keyboard and mouse.
Bulk Transfer Typically used to transfer large amounts of data like reading blocks from USB mass storage devices.
Isochronous Transfer Typically used to transfer data at a ﬁxed rate like voice data.
This protocol also provides mechanisms to manage and conﬁgure USB devices and controllers.
17.2.5 EFI_USB_IO_PROTOCOL
Summary
Provides services to manage and communicate with USB devices.
GUID
#define EFI_USB_IO_PROTOCOL_GUID \
{0x2B2F68D6,0x0CD2,0x44cf,\
{0x8E,0x8B,0xBB,0xA2,0x0B,0x1B,0x5B,0x75}}
17.2. USB Driver Model 683Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct _EFI_USB_IO_PROTOCOL {
EFI_USB_IO_CONTROL_TRANSFER UsbControlTransfer;
EFI_USB_IO_BULK_TRANSFER UsbBulkTransfer;
EFI_USB_IO_ASYNC_INTERRUPT_TRANSFER UsbAsyncInterruptTransfer;
EFI_USB_IO_SYNC_INTERRPUT_TRANSFER UsbSyncInterruptTransfer
EFI_USB_IO_ISOCHRONOUS_TRANSFER UsbIsochronousTransfer;
EFI_USB_IO_ASYNC_ISOCHRONOUS_TRANSFER UsbAsyncIsochronousTransfer;
EFI_USB_IO_GET_DEVICE_DESCRIPTOR UsbGetDeviceDescriptor;
EFI_USB_IO_GET_CONFIG_DESCRIPTOR UsbGetConfigDescriptor;
EFI_USB_IO_GET_INTERFACE_DESCRIPTOR UsbGetInterfaceDescriptor;
EFI_USB_IO_GET_ENDPOINT_DESCRIPTOR UsbGetEndpointDescriptor;
EFI_USB_IO_GET_STRING_DESCRIPTOR UsbGetStringDescriptor;
EFI_USB_IO_GET_SUPPORTED_LANGUAGES UsbGetSupportedLanguages;
EFI_USB_IO_PORT_RESET UsbPortReset;
} EFI_USB_IO_PROTOCOL;
UsbControlTransfer Accesses the USB Device through USB Control Transfer Pipe. See the
EFI_USB_IO_PROTOCOL.UsbControlTransfer() function description.
UsbBulkTransfer Accesses the USB Device through USB Bulk Transfer Pipe. See the
EFI_USB_IO_PROTOCOL.UsbBulkTransfer() function description.
UsbAsyncInterruptTransfer Non-block USB interrupt transfer. See the
EFI_USB_IO_PROTOCOL.UsbAsyncInterruptTransfer() function description.
UsbSyncInterruptTransfer Accesses the USB Device through USB Synchronous Interrupt Transfer Pipe. See the
EFI_USB_IO_PROTOCOL.UsbSyncInterruptTransfer() function description.
UsbIsochronousTransfer Accesses the USB Device through USB Isochronous Transfer Pipe. See the
EFI_USB_IO_PROTOCOL.UsbIsochronousTransfer() function description.
UsbAsyncIsochronousTransfer Nonblock USB isochronous transfer. See the
EFI_USB_IO_PROTOCOL.UsbAsyncIsochronousTransfer() function description.
UsbGetDeviceDescriptor Retrieves the device descriptor of a USB device. See the
EFI_USB_IO_PROTOCOL.UsbGetDeviceDescriptor() function description.
UsbGetConﬁgDescriptor Retrieves the activated conﬁguration descriptor of a USB device. See the
EFI_USB_IO_PROTOCOL.UsbGetConﬁgDescriptor() function description.
UsbGetInterfaceDescriptor
Retrieves the interface descriptor of a USB Controller. See the
EFI_USB_IO_PROTOCOL.UsbGetInterfaceDescriptor() function description.
UsbGetEndpointDescriptor
Retrieves the endpoint descriptor of a USB Controller. See the
EFI_USB_IO_PROTOCOL.UsbGetEndpointDescriptor() function description.
UsbGetStringDescriptor Retrieves the string descriptor inside a USB Device. See the
EFI_USB_IO_PROTOCOL.UsbGetStringDescriptor() function description.
UsbGetSupportedLanguages Retrieves the array of languages that the USB device supports. See the
EFI_USB_IO_PROTOCOL.UsbGetSupportedLanguages() function description.
UsbPortReset Resets and reconﬁgures the USB controller. See the EFI_USB_IO_PROTOCOL.UsbPortReset() func-

17.2. USB Driver Model 684Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The EFI_USB_IO_PROTOCOL provides four basic transfers types described in the USB 1.1 Speciﬁcation. These
include control transfer, interrupt transfer, bulk transfer and isochronous transfer. The EFI_USB_IO_PROTOCOL
also provides some basic USB device/controller management and conﬁguration interfaces. A USB device driver uses
the services of this protocol to manage USB devices.
17.2.6 EFI_USB_IO_PROTOCOL.UsbControlTransfer()
Summary
This function is used to manage a USB device with a control transfer pipe. A control transfer is typically used to
perform device initialization and conﬁguration.
Prototype
typedef
(EFIAPI *EFI_USB_IO_CONTROL_TRANSFER) (
IN EFI_USB_IO_PROTOCOL *This,
IN EFI_USB_DATA_DIRECTION Direction,
IN UINT32 Timeout,
OUT UINT32 *Status
);
This A pointer to the EFI_USB_IO_PROTOCOL instance. Type EFI_USB_IO_PROTOCOL is deﬁned in USB I/O
Protocol .
Request A pointer to the USB device request that will be sent to the USB device. See Related Deﬁnitions below.
Direction Indicates the data direction. See Related Deﬁnitions below for this type.
Timeout Indicating the transfer should be completed within this time frame. The units are in milliseconds. If Timeout
is 0, then the caller must wait for the function to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR
DataLength The size, in bytes, of the data buffer speciﬁed by Data .
Status A pointer to the result of the USB transfer.
EfiUsbDataIn,
EfiUsbDataOut,
EfiUsbNoData
} EFI_USB_DATA_DIRECTION;
//
// Error code forUSB Transfer Results
//
#define EFI_USB_NOERROR 0x0000
#define EFI_USB_ERR_NOTEXECUTE 0x0001
#define EFI_USB_ERR_STALL 0x0002
#define EFI_USB_ERR_BUFFER 0x0004
17.2. USB Driver Model 685Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_USB_ERR_BABBLE 0x0008
#define EFI_USB_ERR_NAK 0x0010
#define EFI_USB_ERR_CRC 0x0020
#define EFI_USB_ERR_TIMEOUT 0x0040
#define EFI_USB_ERR_BITSTUFF 0x0080
#define EFI_USB_ERR_SYSTEM 0x0100
UINT8 RequestType;
UINT8 Request;
UINT16 Value;
UINT16 Index;
} EFI_USB_DEVICE_REQUEST;
RequestType The ﬁeld identiﬁes the characteristics of the speciﬁc request.
Request This ﬁeld speciﬁes the particular request.
Value This ﬁeld is used to pass a parameter to USB device that is speciﬁc to the request.
Index This ﬁeld is also used to pass a parameter to USB device that is speciﬁc to the request.
Length This ﬁeld speciﬁes the length of the data transferred during the second phase of the control transfer. If it is 0,
then there is no data phase in this transfer.
This function allows a USB device driver to communicate with the USB device through a Control Transfer. There are
three control transfer types according to the data phase. If the Direction parameter is EﬁUsbNoData ,Data isNULL ,
andDataLength is 0, then no data phase exists for the control transfer. If the Direction parameter is EﬁUsbDataOut ,
then Data speciﬁes the data to be transmitted to the device, and DataLength speciﬁes the number of bytes to transfer
to the device. In this case there is an OUT DATA stage followed by a SETUP stage. If the Direction parameter is
EﬁUsbDataIn , then Data speciﬁes the data that is received from the device, and DataLength speciﬁes the number
of bytes to receive from the device. In this case there is an IN DATA stage followed by a SETUP stage. After
the USB transfer has completed successfully, EFI_SUCCESS is returned. If the transfer cannot be completed due
to timeout, then EFI_TIMEOUT is returned. If an error other than timeout occurs during the USB transfer, then
EFI_DEVICE_ERROR is returned and the detailed status code is returned in Status .
EFI_SUCCESS The control transfer has been successfully executed.
EFI_INV ALID_PARAMETER The parameter Direction is not valid.
EFI_INV ALID_PARAMETER Request is NULL .
EFI-INV ALID_PARAMETER Status is NULL .
EFI_TIMEOUT The control transfer fails due to timeout.
EFI_DEVICE_ERROR The transfer failed. The transfer status is returned in Status.
17.2. USB Driver Model 686Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.2.7 EFI_USB_IO_PROTOCOL.UsbBulkTransfer()
Summary
This function is used to manage a USB device with the bulk transfer pipe. Bulk Transfers are typically used to transfer
large amounts of data to/from USB devices.
Prototype
typedef
(EFIAPI *EFI_USB_IO_BULK_TRANSFER) (
IN UINT8 DeviceEndpoint,
);
Protocol .
DeviceEndpoint The destination USB device endpoint to which the device request is being sent. DeviceEndpoint
must be between 0x01 and 0x0F or between 0x81 and 0x8F, otherwise EFI_INV ALID_PARAMETER is re-
turned. If the endpoint is not a BULK endpoint, EFI_INV ALID_PARAMETER is returned. The MSB of this
parameter indicates the endpoint direction. The number “1” stands for an IN endpoint, and “0” stands for an
OUT endpoint.
DataLength On input, the size, in bytes, of the data buffer speciﬁed by Data. On output, the number of bytes that
were actually transferred.
Status This parameter indicates the USB transfer status.
This function allows a USB device driver to communicate with the USB device through Bulk Transfer. The transfer
direction is determined by the endpoint direction. If the USB transfer is successful, then EFI_SUCCESS is returned.
If USB transfer cannot be completed within the Timeout frame, EFI_TIMEOUT is returned. If an error other than
returned in the Status parameter.
EFI_SUCCESS The bulk transfer has been successfully executed.
EFI_INV ALID_PARAMETER If DeviceEndpoint is not valid.
EFI_INV ALID_PARAMETER Data is NULL .
EFI_INV ALID_PARAMETER DataLength is NULL .
EFI_INV ALID_PARAMETER Status is NULL .
EFI_TIMEOUT The bulk transfer cannot be completed within Timeout timeframe.
17.2. USB Driver Model 687Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 17.14 – continued from previous page
EFI_DEVICE_ERROR The transfer failed other than timeout, and the transfer status is returned in
Status.
17.2.8 EFI_USB_IO_PROTOCOL.UsbAsyncInterruptTransfer()
Summary
This function is used to manage a USB device with an interrupt transfer pipe. An Asynchronous Interrupt Transfer is
typically used to query a device’s status at a ﬁxed rate. For example, keyboard, mouse, and hub devices use this type
of transfer to query their interrupt endpoints at a ﬁxed rate.
Prototype
typedef
(EFIAPI *EFI_USB_IO_ASYNC_INTERRUPT_TRANSFER) (
IN EFI_ASYNC_USB_TRANSFER_CALLBACK InterruptCallBack OPTIONAL,
);
Protocol .
turned. If the endpoint is not an INTERRUPT endpoint, EFI_INV ALID_PARAMETER is returned. The MSB
of this parameter indicates the endpoint direction. The number “1” stands for an IN endpoint, and “0” stands for
an OUT endpoint.
IsNewTransfer IfTRUE , a new transfer will be submitted to USB controller. If FALSE , the interrupt transfer is
deleted from the device’s interrupt transfer queue. If TRUE , and an interrupt transfer exists for the target end
point, then EFI_INV ALID_PARAMETER is returned.
PollingInterval Indicates the periodic rate, in milliseconds, that the transfer is to be executed. This pa-

);
Protocol .
rameter is required when IsNewTransfer is TRUE . The value must be between 1 to 255, otherwise
EFI_INV ALID_PARAMETER is returned. The units are in milliseconds.
DataLength Speciﬁes the length, in bytes, of the data to be received from the USB device. This parameter is only
required when IsNewTransfer is TRUE .
Context Data passed to the InterruptCallback function. This is an optional parameter and may be NULL .
InterruptCallback The Callback function. This function is called if the asynchronous interrupt transfer is completed.
This parameter is required when IsNewTransfer is TRUE . See Related Deﬁnitions for the deﬁnition of this type.
typedef
(EFIAPI *EFI_ASYNC_USB_TRANSFER_CALLBACK) (
17.2. USB Driver Model 688Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN VOID *Context,
IN UINT32 Status
);
Data Data received or sent via the USB Asynchronous Transfer, if the transfer completed successfully.
DataLength The length of Data received or sent via the Asynchronous Transfer, if transfer successfully completes.
Context Data passed from EFI_USB_IO_PROTOCOL.UsbAsyncInterruptTransfer() request.
Status Indicates the result of the asynchronous transfer.
This function allows a USB device driver to communicate with a USB device with an Interrupt Transfer. Asynchronous
Interrupt transfer is different than the other four transfer types because it is a nonblocking transfer. The interrupt
endpoint is queried at a ﬁxed rate, and the data transfer direction is always in the direction from the USB device
towards the system.
the size of the receive buffer is speciﬁed by DataLength , and the callback function is speciﬁed by InterruptCallback .
EFI_SUCCESS The asynchronous USB transfer request has been successfully executed.
EFI_DEVICE_ERROR The asynchronous USB transfer request failed. When an interrupt trans-
fer exists for the target end point and a new transfer is requested,
Examples
Below is an example of how an asynchronous interrupt transfer is used. The example shows how a USB Keyboard
Device Driver can periodically receive data from interrupt endpoint.
EFI_USB_IO_PROTOCOL *UsbIo;
USB_KEYBOARD_DEV *UsbKeyboardDevice;
EFI_USB_INTERRUPT_CALLBACK *KeyboardHandle;
. . .
Status = UsbIo->UsbAsyncInterruptTransfer(
UsbIo,
UsbKeyboardDevice->IntEndpointAddress,
TRUE,
UsbKeyboardDevice->IntPollingInterval,
8,
KeyboardHandler,
UsbKeyboardDevice
);
. . .
//
// The following isthe InterruptCallback function. If there is
17.2. USB Driver Model 689Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// any results got from Asynchronous Interrupt Transfer,
// this function will be called.
//
KeyboardHandler(
IN UINT32 Result
)
{
UINTN I;
if(EFI_ERROR(Result))
{
//
// Something error during this transfer,
// just to some recovery work
//
. . .
. . .
}
UsbKeyboardDevice = (USB_KEYBOARD_DEV *)Context;
for(I = 0; I < DataLength; I++)
{
ParsedData(Data[I]);
. . .
}
}
17.2.9 EFI_USB_IO_PROTOCOL.UsbSyncInterruptTransfer()
Summary
This function is used to manage a USB device with an interrupt transfer pipe. The difference between
EFI_USB_IO_PROTOCOL.UsbAsyncInterruptTransfer() andUsbSyncInterruptTransfer() is that the Synchronous in-
terrupt transfer will only be executed one time. Once it returns, regardless of its status, the interrupt request will be
deleted in the system.
Prototype
typedef
(EFIAPI *EFI_USB_IO_SYNC_INTERRUPT_TRANSFER) (
);
17.2. USB Driver Model 690Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Protocol .
DataLength On input, then size, in bytes, of the buffer Data. On output, the amount of data actually transferred.
Timeout The time out, in milliseconds, for this transfer. If Timeout is 0, then the caller must wait for the function to
be completed until EFI_SUCCESS orEFI_DEVICE_ERROR is returned. If the transfer is not completed in this
time frame, then EFI_TIMEOUT is returned.
This function allows a USB device driver to communicate with a USB device through a synchronous interrupt transfer.
The UsbSyncInterruptTransfer() differs from EFI_USB_IO_PROTOCOL.UsbAsyncInterruptTransfer() described in
the previous section in that it is a blocking transfer request. The caller must wait for the function return, either
successfully or unsuccessfully.
EFI_SUCCESS The sync interrupt transfer has been successfully executed.
EFI_INV ALID_PARAMETER The parameter DeviceEndpoint is not valid.
EFI_TIMEOUT The transfer cannot be completed within Timeout timeframe.
Status.
17.2.10 EFI_USB_IO_PROTOCOL.UsbIsochronousTransfer()
Summary
This function is used to manage a USB device with an isochronous transfer pipe. An Isochronous transfer is typically
used to transfer streaming data.
Prototype
typedef
(EFIAPI *EFI_USB_IO_ISOCHRONOUS_TRANSFER) (
);
17.2. USB Driver Model 691Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Protocol .
turned. If the endpoint is not an ISOCHRONOUS endpoint, EFI_INV ALID_PARAMETER is returned. The
MSB of this parameter indicates the endpoint direction. The number “1” stands for an IN endpoint, and “0”
stands for an OUT endpoint.
DataLength The size, in bytes, of the data buffer speciﬁed by Data.
This function allows a USB device driver to communicate with a USB device with an Isochronous Transfer. The type
of transfer is different than the other types because the USB Bus Driver will not attempt to perform error recovery if
transfer fails. If the USB transfer is completed successfully, then EFI_SUCCESS is returned. The isochronous transfer
is designed to be completed within 1 USB frame time, if it cannot be completed, EFI_TIMEOUT is returned. If the
transfer fails due to other reasons, then EFI_DEVICE_ERROR is returned and the detailed error status is returned in
Status . If the data length exceeds the maximum payload per USB frame time, then it is this function’s responsibility to
divide the data into a set of smaller packets that ﬁt into a USB frame time. If all the packets are transferred successfully,
then EFI_SUCCESS is returned.
EFI_SUCCESS The isochronous transfer has been successfully executed.
EFI_TIMEOUT The transfer cannot be completed within the 1 USB frame time.
EFI_DEVICE_ERROR The transfer failed due to the reason other than timeout, The error status is
returned in Status.

17.2.11 EFI_USB_IO_PROTOCOL.UsbAsyncIsochronousTransfer()
Summary
This function is used to manage a USB device with an isochronous transfer pipe. An asynchronous Isochronous
transfer is a nonblocking USB isochronous transfer.
Prototype
typedef
(EFIAPI *EFI_USB_IO_ASYNC_ISOCHRONOUS_TRANSFER) (
);
17.2. USB Driver Model 692Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Protocol .
must be between 0x01 and 0x0F or between 0x81 and 0x8F, otherwise EFI_INVALID_PARAMETER is returned.
If the endpoint is not an ISOCHRONOUS endpoint, EFI_INVALID_PARAMETER is returned. The MSB of this
Context Data passed to the IsochronoisCallback() in Protocols_USB_Support.rst function. This is an optional pa-
rameter and may be NULL .
IsochronousCallback The IsochronousCallback() function. This function is called if the re-
quested isochronous transfer is completed. See the Related Deﬁnitions section of the
This is an asynchronous type of USB isochronous transfer. If the caller submits a USB isochronous transfer request
through this function, this function will return immediately. When the isochronous transfer completes, the Isochronois-
Callback() function will be triggered, the caller can know the transfer results. If the transfer is successful, the caller
can get the data received or sent in this callback function.
EFI_SUCCESS The asynchronous isochronous transfer has been successfully submitted to
EFI_OUT_OF_RESOURCES The request could not be submitted due to a lack of resources.
EFI_UNSUPPORTED The implementation doesn’t support an asynchronous Isochronous transfer
function.
17.2.12 EFI_USB_IO_PROTOCOL.UsbGetDeviceDescriptor()
Summary
Retrieves the USB Device Descriptor.
Prototype
typedef
(EFIAPI *EFI_USB_IO_GET_DEVICE_DESCRIPTOR) (
OUT EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor
);
Protocol .
DeviceDescriptor A pointer to the caller allocated USB Device Descriptor. See Related Deﬁnitions for a detailed
17.2. USB Driver Model 693Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// See USB1.1 fordetail description.
//
UINT8 Length;
UINT8 DescriptorType;
UINT16 BcdUSB;
UINT8 DeviceClass;
UINT8 DeviceSubClass;
UINT8 DeviceProtocol;
UINT8 MaxPacketSize0;
UINT16 IdVendor;
UINT16 IdProduct;
UINT16 BcdDevice;
UINT8 StrManufacturer;
UINT8 StrProduct;
UINT8 StrSerialNumber;
UINT8 NumConfigurations;
} EFI_USB_DEVICE_DESCRIPTOR;
This function is used to retrieve information about USB devices. This information includes the device class,
subclass, and the number of conﬁgurations the USB device supports. If DeviceDescriptor isNULL , then
EFI_INVALID_PARAMETER is returned. If the USB device descriptor is not found, then EFI_NOT_FOUND is
returned. Otherwise, the device descriptor is returned in DeviceDescriptor , and EFI_SUCCESS is returned.
EFI_SUCCESS The device descriptor was retrieved successfully.
EFI_INV ALID_PARAMETER DeviceDescriptor is NULL .
EFI_NOT_FOUND The device descriptor was not found. The device may not be conﬁgured.
17.2.13 EFI_USB_IO_PROTOCOL.UsbGetConﬁgDescriptor()
Summary
Retrieves the USB Device Conﬁguration Descriptor.
Prototype
typedef
(EFIAPI *EFI_USB_IO_GET_CONFIG_DESCRIPTOR) (
OUT EFI_USB_CONFIG_DESCRIPTOR *ConfigurationDescriptor
);
Protocol .
17.2. USB Driver Model 694Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ConﬁgurationDescriptor A pointer to the caller allocated USB Active Conﬁguration Descriptor. See Related Deﬁ-
nitions for a detailed description.
//
//
UINT16 TotalLength;
UINT8 NumInterfaces;
UINT8 ConfigurationValue;
UINT8 Configuration;
UINT8 Attributes;
UINT8 MaxPower;
} EFI_USB_CONFIG_DESCRIPTOR;
This function is used to retrieve the active conﬁguration that the USB device is currently using. If ConﬁgurationDe-
scriptor isNULL , then EFI_INVALID_PARAMETER is returned. If the USB controller does not contain an active
conﬁguration, then EFI_NOT_FOUND is returned. Otherwise, the active conﬁguration is returned in Conﬁgura-
tionDescriptor , and EFI_SUCCESS is returned.
EFI_SUCCESS The active conﬁguration descriptor was retrieved successfully.
EFI_INV ALID_PARAMETER ConﬁgurationDescriptor is NULL .
EFI_NOT_FOUND An active conﬁguration descriptor cannot be found. The device may not be
17.2.14 EFI_USB_IO_PROTOCOL.UsbGetInterfaceDescriptor()
Summary
Retrieves the Interface Descriptor for a USB Device Controller. As stated earlier, an interface within a USB device is
equivalently to a USB Controller within the current conﬁguration.
Prototype
typedef
(EFIAPI *EFI_USB_IO_GET_INTERFACE_DESCRIPTOR) (
OUT EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor
);
Protocol .
InterfaceDescriptor A pointer to the caller allocated USB Interface Descriptor within the conﬁguration setting. See
Related Deﬁnitions for a detailed description.
17.2. USB Driver Model 695Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
//
UINT8 InterfaceNumber;
UINT8 AlternateSetting;
UINT8 NumEndpoints;
UINT8 InterfaceClass;
UINT8 InterfaceSubClass;
UINT8 InterfaceProtocol;
UINT8 Interface;
} EFI_USB_INTERFACE_DESCRIPTOR;
This function is used to retrieve the interface descriptor for the USB controller. If InterfaceDescriptor isNULL ,
then EFI_INVALID_PARAMETER is returned. If the USB controller does not contain an interface descriptor,
then EFI_NOT_FOUND is returned. Otherwise, the interface descriptor is returned in InterfaceDescriptor , and
EFI_SUCCESS The interface descriptor retrieved successfully.
EFI_INV ALID_PARAMETER InterfaceDescriptor is NULL.
EFI_NOT_FOUND The interface descriptor cannot be found. The device may not be correctly
17.2.15 EFI_USB_IO_PROTOCOL.UsbGetEndpointDescriptor()
Summary
Retrieves an Endpoint Descriptor within a USB Controller.
Prototype
typedef
(EFIAPI *EFI_USB_IO_GET_ENDPOINT_DESCRIPTOR) (
IN UINT8 EndpointIndex,
OUT EFI_USB_ENDPOINT_DESCRIPTOR *EndpointDescriptor
);
Protocol .
EndpointIndex Indicates which endpoint descriptor to retrieve. The valid range is 0..15.
EndpointDescriptor A pointer to the caller allocated USB Endpoint Descriptor of a USB controller. See Related
Deﬁnitions for a detailed description.
17.2. USB Driver Model 696Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
//
UINT8 EndpointAddress;
UINT16 MaxPacketSize;
UINT8 Interval;
} EFI_USB_ENDPOINT_DESCRIPTOR;
This function is used to retrieve an endpoint descriptor within a USB controller. If EndpointIndex is not
in the range 0..15, then EFI_INVALID_PARAMETER is returned. If EndpointDescriptor isNULL , then
EFI_INVALID_PARAMETER is returned. If the endpoint speciﬁed by EndpointIndex does not exist within the USB
controller, then EFI_NOT_FOUND is returned. Otherwise, the endpoint descriptor is returned in EndpointDescriptor ,
andEFI_SUCCESS is returned.
EFI_SUCCESS The endpoint descriptor was retrieved successfully.
EFI_INV ALID_PARAMETER EndpointIndex is not valid.

//
//
EFI_INV ALID_PARAMETER EndpointDescriptor is NULL .
EFI_NOT_FOUND The endpoint descriptor cannot be found. The device may not be correctly
Examples
The following code fragment shows how to retrieve all the endpoint descriptors from a USB controller.
EFI_USB_INTERFACE_DESCRIPTOR InterfaceDesc;
EFI_USB_ENDPOINT_DESCRIPTOR EndpointDesc;
Status = UsbIo->GetInterfaceDescriptor (
UsbIo,
&InterfaceDesc
);
. . .
for(Index = 0; Index < InterfaceDesc.NumEndpoints; Index++) {
Status = UsbIo->GetEndpointDescriptor(
UsbIo,
Index,
&EndpointDesc
);
. . .
}
17.2. USB Driver Model 697Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.2.16 EFI_USB_IO_PROTOCOL.UsbGetStringDescriptor()
Summary
Retrieves a string stored in a USB Device.
Prototype
typedef
(EFIAPI *EFI_USB_IO_GET_STRING_DESCRIPTOR) (
IN UINT16 LangID,
IN UINT8 StringID,
OUT CHAR16 **String
);
Protocol .
LangID The Language ID for the string being retrieved. See the EFI_USB_IO_PROTOCOL.UsbGetSupportedLanguages()
function description for a more detailed description.
StringID The ID of the string being retrieved.
String A pointer to a buffer allocated by this function with EFI_BOOT_SERVICES.AllocatePool() to store the string.
If this function returns EFI_SUCCESS, it stores the string the caller wants to get. The caller should release the
string buffer with EFI_BOOT_SERVICES.FreePool() after the string is not used any more.
This function is used to retrieve strings stored in a USB device. The string to retrieve is identiﬁed by a language and an
identiﬁer. The language is speciﬁed by LangID , and the identiﬁer is speciﬁed by StringID . If the string is found, it is
returned in String , and EFI_SUCCESS is returned. If the string cannot be found, then EFI_NOT_FOUND is returned.
The string buffer is allocated by this function with AllocatePool() . The caller is responsible for calling FreePool() for
String when it is no longer required.
EFI_SUCCESS The string was retrieved successfully.
EFI_NOT_FOUND The string speciﬁed by LangID and StringID was not found.
EFI_OUT_OF_RESOURCES There are not enough resources to allocate the return buffer String.
17.2.17 EFI_USB_IO_PROTOCOL.UsbGetSupportedLanguages()
Summary
Retrieves all the language ID codes that the USB device supports.
Prototype
typedef
(EFIAPI *EFI_USB_IO_GET_SUPPORTED_LANGUAGES) (
OUT UINT16 **LangIDTable,
17.2. USB Driver Model 698Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
OUT UINT16 *TableSize
);
Protocol .
LangIDTable Language ID for the string the caller wants to get. This is a 16-bit ID deﬁned by Microsoft. This buffer
pointer is allocated and maintained by the USB Bus Driver, the caller should not modify its contents.
TableSize The size, in bytes, of the table LangIDTable .
EFI_SUCCESS The support languages were retrieved successfully.
17.2.18 EFI_USB_IO_PROTOCOL.UsbPortReset()
Summary
Resets and reconﬁgures the USB controller. This function will work for all USB devices except USB Hub Controllers.
Prototype
typedef
(EFIAPI *EFI_USB_IO_PORT_RESET) (
IN EFI_USB_IO_PROTOCOL *This
);
Protocol .
This function provides a reset mechanism by sending a RESET signal from the parent hub port. A reconﬁguration
process will happen (that includes setting the address and setting the conﬁguration). This reset function does not
change the bus topology. A USB hub controller cannot be reset using this function, because it would impact the
downstream USB devices. So if the controller is a USB hub controller, then EFI_INVALID_PARAMETER is returned.
EFI_SUCCESS The USB controller was reset.
EFI_INV ALID_PARAMETER If the controller speciﬁed by This is a USB hub.
EFI_DEVICE_ERROR An error occurred during the reconﬁguration process.
17.2. USB Driver Model 699Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.3 USB Function Protocol
This section describes the USB Function Protocol, enabling a USB Function device with a UEFI driver that implements
the protocol to communicate with a a USB Host device.
The USB Function Protocol provides an I/O abstraction for a USB Controller operating in Function mode (also com-
monly referred to as Device, Peripheral, or Target mode) and the mechanisms by which the USB Function can com-
municate with the USB Host. It is used by other UEFI drivers or applications to perform data transactions and basic
USB controller management over a USB Function port.
This simple protocol only supports USB 2.0 bulk transfers on systems with a single conﬁguration and a single interface.
It does not support isochronous or interrupt transfers, alternate interfaces, or USB 3.0 functionality. Future revisions
of this protocol may support these or additional features.
17.3.1 EFI_USBFN_IO_PROTOCOL
Summary
Provides basic data transactions and basic USB controller management for a USB Function port.
GUID
// {32D2963A-FE5D-4f30-B633-6E5DC55803CC}
#define EFI_USBFN_IO_PROTOCOL_GUID \
{0x32d2963a, 0xfe5d, 0x4f30,\
{0xb6, 0x33, 0x6e, 0x5d, 0xc5, 0x58, 0x3, 0xcc}};
#define EFI_USBFN_IO_PROTOCOL_REVISION 0x00010001
typedef struct _EFI_USBFN_IO_PROTOCOL {
EFI_USBFN_IO_DETECT_PORT DetectPort;
EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS \
ConfigureEnableEndpoints;
EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE \
GetEndpointMaxPacketSize;
EFI_USBFN_IO_GET_DEVICE_INFO GetDeviceInfo;
EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID \
GetVendorIdProductId;
EFI_USBFN_IO_ABORT_TRANSFER AbortTransfer;
EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE \
GetEndpointStallState;
EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE \
SetEndpointStallState;
EFI_USBFN_IO_EVENTHANDLER EventHandler;
EFI_USBFN_IO_TRANSFER Transfer;
EFI_USBFN_IO_GET_MAXTRANSFER_SIZE \
GetMaxTransferSize;
EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER AllocateTransferBuffer;
EFI_USBFN_IO_FREE_TRANSFER_BUFFER FreeTransferBuffer;
EFI_USBFN_IO_START_CONTROLLER StartController;
EFI_USBFN_IO_STOP_CONTROLLER StopController;
17.3. USB Function Protocol 700Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_USBFN_IO_SET_ENDPOINT_POLICY SetEndpointPolicy;
EFI_USBFN_IO_GET_ENDPOINT_POLICY GetEndpointPolicy;
} EFI_USBFN_IO_PROTOCOL;
Revision The revision to which the EFI_USBFN_IO_PROTOCOL adheres. All future revisions must be backwards
compatible. If a future version is not backwards compatible, a different GUID must be used.
DetectPort Returns information about the USB port type. See Related Deﬁnitions
EFI_USBFN_IO_PROTOCOL.DetectPort() , for more details.
ConﬁgureEnableEndpoints Initializes all endpoints based on supplied device and conﬁguration descriptors. Enables
the device by setting the run/stop bit.
GetEndpointMaxPacketSize Returns the maximum packet size of the speciﬁed endpoint.
GetDeviceInfo Returns device speciﬁc information based on the supplied identiﬁer as a Unicode string.
GetVendorIdProductId Returns the vendor-id and product-id of the device.
AbortTransfer Aborts the transfer on the speciﬁed endpoint.
GetEndpointStallState Returns the stall state on the speciﬁed endpoint.
SetEndpointStallState Sets or clears the stall state on the speciﬁed endpoint.
EventHandler This function is called repeatedly to get information on USB bus states, receive-completion and
transmit-completion events on the endpoints, and notiﬁcation on setup packet on endpoint 0.
Transfer This function handles transferring data to or from the host on the speciﬁed endpoint, depending on the
direction speciﬁed.
GetMaxTransferSize The maximum supported transfer size in bytes.
AllocateTransferBuffer Allocates a transfer buffer of the speciﬁed size that satisﬁes the controller requirements.
FreeTransferBuffer Deallocates the memory allocated for the transfer buffer by
EFI_USBFN_IO_PROTOCOL.AllocateTransferBuffer() function.
StartController This function initializes the hardware and the internal data structures. The port must not be activated
by this function.
StopController This function disables the device by deactivating the port.
SetEndpointPolicy This function sets the conﬁguration policy for the speciﬁed non-control endpoint. There are a
few calling restrictions for this function. See the EFI_USBFN_IO_PROTOCOL.SetEndpointPolicy() function
deﬁnition for more details.

GetEndpointPolicy This functions retrieves the conﬁguration policy for the speciﬁed non-control endpoint.
This protocol provides basic data transactions and USB controller management for a USB Function port. It provides a
lightweight communication mechanism between a USB Host and a USB Function in the UEFI environment.
Like other UEFI device drivers, the entry point for a USB function driver attaches
EFI_DRIVER_BINDING_PROTOCOL to image handle of EFI_USBFN_IO_PROTOCOL driver.
The driver binding protocol contains three services, Supported, Start and Stop.
TheSupported function must test to see if this driver supports a given controller.
17.3. USB Function Protocol 701Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheStart function must supply power to the USB controller if needed, initialize hardware and internal data structures,
and then return. The port must not be activated by this function.
The Stop function must disable the USB controller and power it off if needed.
17.3.2 EFI_USBFN_IO_PROTOCOL.DetectPort()
Summary
Returns information about what USB port type was attached.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_DETECT_PORT) (
IN EFI_USBFN_IO_PROTOCOL *This,
OUT EFI_USBFN_PORT_TYPE *PortType
);
This A pointer to the EFI_USBFN_IO_PROTOCOL instance.
PortType Returns the USB port type. Refer to the Related Deﬁnitions for this function below for details.
Returns information about the USB port type attached. Refer to the Related Deﬁnitions below for further details.
EFI_SUCCESS The function returned successfully.
EFI_INV ALID_PARAMETER A parameter is invalid.
EFI_DEVICE_ERROR The physical device reported an error.
EFI_NOT_READY The physical device is busy or not ready to process this request or there is
no USB port attached to the device
typedef enum _EFI_USBFN_PORT_TYPE {
EfiUsbUnknownPort = 0,
EfiUsbStandardDownstreamPort,
EfiUsbChargingDownstreamPort,
EfiUsbDedicatedChargingPort,
EfiUsbInvalidDedicatedChargingPort
} EFI_USBFN_PORT_TYPE;
Unknown Port Driver internal default port type, this is never returned by the driver with a success status code.
Standard Downstream Port Standard USB host; refer to USB Battery Charging Speciﬁcation, Revision 1.2 in Ap-
pendix Q.1 for details and the link.
Charging Downstream Port Standard USB host with special charging properties; refer to USB Battery Charging
Speciﬁcation, Revision 1.2 in Appendix Q.1 `for the details and link.
Dedicated Charging Port A wall-charger, not USB host; refer to USB Battery Charging Speciﬁcation, Revision 1.2,
in Appendix Q.1 for details and the link.
Invalid Dedicated Charging Port - Neither a USB host nor a dedicated charging port as deﬁned by the USB Battery
17.3. USB Function Protocol 702Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Charging Speciﬁcation, Revision 1.2 . in Appendix Q.1 for details and the link.) An example is a USB charger
that raises the voltages on D+/D-, causing the charger to look like an SDP even though it will never issue a setup
packet to the upstream facing port.
17.3.3 EFI_USBFN_IO_PROTOCOL.ConﬁgureEnableEndpoints()
Summary
Conﬁgures endpoints based on supplied device and conﬁguration descriptors.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS) (
IN EFI_USB_DEVICE_INFO *DeviceInfo
);
DeviceInfo A pointer to EFI_USBFN_DEVICE_INFO instance. Refer to the Related Deﬁnitions for this function
below for details.
Assuming that the hardware has already been initialized, this function conﬁgures the endpoints using the device
information supplied by DeviceInfo , activates the port, and starts receiving USB events.
This function must ignore the bMaxPacketSize0 ﬁeld of the Standard Device Descriptor and the wMaxPacketSize ﬁeld
of the Standard Endpoint Descriptor that are made available through DeviceInfo .
EFI_NOT_READY The physical device is busy or not ready to process this request.
EFI_OUT_OF_RESOURCES The request could not be completed due to lack of resources.
EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor;
EFI_USB_ENDPOINT_DESCRIPTOR **EndpointDescriptorTable;
} EFI_USB_INTERFACE_INFO;
EFI_USB_CONFIG_DESCRIPTOR *ConfigDescriptor *;
EFI_USB_INTERFACE_INFO **InterfaceInfoTable *;
} EFI_USB_CONFIG_INFO;
EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor *;
EFI_USB_CONFIG_INFO **ConfigInfoTable *;
} EFI_USB_DEVICE_INFO;
17.3. USB Function Protocol 703Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and
USB_ENDPOINT_DESCRIPTOR are deﬁned in Section USB I/O Protocol .
17.3.4 EFI_USBFN_IO_PROTOCOL.GetEndpointMaxPacketSize()
Summary
Returns the maximum packet size of the speciﬁed endpoint type for the supplied bus speed.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE) (
IN EFI_USB_ENDPOINT_TYPE EndpointType,
IN EFI_USB_BUS_SPEED BusSpeed,
OUT UINT16 *MaxPacketSize
);
EndpointType Endpoint type as deﬁned as EFI_USB_ENDPOINT_TYPE in the Related Deﬁnitions for this function
BusSpeed Bus speed as deﬁned as EFI_USB_BUS_SPEED in the Related Deﬁnitions for the EventHandle function
for details.
MaxPacketSize The maximum packet size, in bytes, of the speciﬁed endpoint type.
Returns the maximum packet size of the speciﬁed endpoint type for the supplied bus speed. If the BusSpeed is
UsbBusSpeedUnknown , the maximum speed the underlying controller supports is assumed.
This protocol currently does not support isochronous or interrupt transfers. Future revisions of this protocol may
eventually support it.
typedef enum _EFI_USB_ENDPOINT_TYPE
{
UsbEndpointControl = 0x00,
// UsbEndpointIsochronous = 0x01,
UsbEndpointBulk = 0x02,
// UsbEndpointInterrupt = 0x03
} EFI_USB_ENDPOINT_TYPE;
17.3. USB Function Protocol 704Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.3.5 EFI_USBFN_IO_PROTOCOL.GetDeviceInfo()
Summary
Returns device speciﬁc information based on the supplied identiﬁer as a Unicode string.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_GET_DEVICE_INFO) (
IN EFI_USBFN_DEVICE_INFO_ID Id,
OUT VOID *Buffer OPTIONAL
);
IdThe requested information id. Refer to the Related Deﬁnitions for this function below for details.
BufferSize On input, the size of the Buffer in bytes. On output, the amount of data returned in Buffer in bytes.
Buffer A pointer to a buffer to return the requested information as a Unicode string.
Returns device speciﬁc information based on the supplied identiﬁer as a Unicode string. If the supplied Buffer isn’t
large enough, or is NULL , the method fails with EFI_BUFFER_TOO_SMALL and the required size is returned
through BufferSize . All returned strings are in Unicode format.
AnIdofEﬁUsbDeviceInfoUnknown is treated as an invalid parameter.
One or more of the following conditions is TRUE :
• BufferSize is NULL .
• BufferSize1is not 0 and Buffer is NULL .
• Id in invalid.
EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer.
1BufferSize has been updated with the size needed to hold the request string.
typedef enum _EFI_USBFN_DEVICE_INFO_ID
{
EfiUsbDeviceInfoUnknown = 0,
EfiUsbDeviceInfoSerialNumber,
EfiUsbDeviceInfoManufacturerName,
EfiUsbDeviceInfoProductName
} EFI_USBFN_DEVICE_INFO_ID;
17.3. USB Function Protocol 705Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.3.6 EFI_USBFN_IO_PROTOCOL.GetVendorIdProductId()
Summary
Returns the vendor-id and product-id of the device.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID) (
OUT UINT16 *Vid,
OUT UINT16 *Pid
);
Vid Returned vendor-id of the device.
Pid Returned product-id of the device.

{
Summary
Prototype
typedef
);
Returns vendor-id and product-id of the device.
EFI_NOT_FOUND Unable to return the vendor-id or the product-id
Vendor IDs (VIDs) are 16-bit numbers that represent the device’s vendor company and are assigned and maintained
by the USB-IF. Product IDs (PIDs) are 16-bit numbers assigned by each vendor to the device.
17.3.7 EFI_USBFN_IO_PROTOCOL.AbortTransfer()
Summary
Aborts the transfer on the speciﬁed endpoint.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_ABORT_TRANSFER) (
IN EFI_USBFN_ENDPOINT_DIRECTION Direction
);
EndpointIndex Indicates the endpoint on which the ongoing transfer needs to be canceled.
17.3. USB Function Protocol 706Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Direction Direction of the endpoint. Refer to the Related Deﬁnitions for this function (below) for details.
Aborts the transfer on the speciﬁed endpoint. This function should fail with EFI_INVALID_PARAMETER if the
speciﬁed direction is incorrect for the endpoint.
typedef enum _EFI_USBFN_ENDPOINT_DIRECTION
{
EfiUsbEndpointDirectionHostOut = 0,
EfiUsbEndpointDirectionHostIn,
EfiUsbEndpointDirectionDeviceTx = EfiUsbEndpointDirectionHostIn,
EfiUsbEndpointDirectionDeviceRx = EfiUsbEndpointDirectionHostOut
} EFI_USBFN_ENDPOINT_DIRECTION;
17.3.8 EFI_USBFN_IO_PROTOCOL.GetEndpointStallState()
Summary
Returns the stall state on the speciﬁed endpoint.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE) (
IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
IN OUT BOOLEAN *State
);
EndpointIndex Indicates the endpoint.
Direction Direction of the endpoint. Refer to the Related Deﬁnitions for details see
EFI_USBFN_IO_PROTOCOL.AbortTransfer() .
State Boolean, true value indicates that the endpoint is in a stalled state, false otherwise.
Returns the stall state on the speciﬁed endpoint. This function would fail with EFI_INVALID_PARAMETER if the
17.3. USB Function Protocol 707Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.3.9 EFI_USBFN_IO_PROTOCOL.SetEndpointStallState()
Summary
Sets or clears the stall state on the speciﬁed endpoint.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE) (
IN BOOLEAN State
);
Direction Direction of the endpoint. Refer to the Related Deﬁnitions for the
EFI_USBFN_IO_PROTOCOL.ABORTTRANSFER() function for details.
State Requested stall state on the speciﬁed endpoint. TRUE value causes the endpoint to stall; FALSE value clears
an existing stall.
Sets or clears the stall state on the speciﬁed endpoint. This function would fail with EFI_INVALID_PARAMETER if
the speciﬁed direction is incorrect for the endpoint.
17.3.10 EFI_USBFN_IO_PROTOCOL.EventHandler()
Summary
This function is called repeatedly to get information on USB bus states, receive-completion and transmit-completion
events on the endpoints, and notiﬁcation on setup packet on endpoint 0.
Prototype
17.3. USB Function Protocol 708Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef
(EFIAPI *EFI_USBFN_IO_EVENTHANDLER) (
OUT EFI_USBFN_MESSAGE *Message,
IN OUT UINTN *PayloadSize,
OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload
);
Message Indicates the event that initiated this notiﬁcation. Refer to the Related Deﬁnitions for this function (below)
for all possible types.
PayloadSize On input, the size of the memory pointed by Payload . On output, the amount of data returned in Payload .
Payload A pointer to EFI_USBFN_MESSAGE_PAYLOAD instance to return additional payload for current message.
Refer to the Related Deﬁnitions for this function (below) for details on the type.
This function is called repeatedly to get information on USB bus states, receive-completion and transmit-
completion events on the endpoints, and notiﬁcation on setup packet on endpoint 0. A class driver must call
EFI_USBFN_IO_PROTOCOL.EventHandler() repeatedly to receive updates on the transfer status and number of
bytes transferred on various endpoints. Refer to Figure Sequence of Operations with Endpoint Policy Changes for
details.
A few messages have an associated payload that is returned in the supplied buffer. The following table describes
various messages and their payload:
Table 17.33: Payload Associated Messages and Descriptions
Message Payload Description
EﬁUsbMsgSetupPacket EFI_USB_DEVICE_REQUEST SETUP packet was received.
EﬁUsbMsgEndpointStatusChangedRx EFI_USBFN_TRANSFER_RESULT Some of the requested data has been
transmitted to the host. It is the re-
sponsibility of the class driver to de-
termine if any remaining data needs
to be re-sent. The Buffer supplied to
EFI_USBFN_IO_PROTOCOL.Transfer()
must be same as the Buffer ﬁeld of the
payload.
EﬁUsbMsgEndpointStatusChangedTx EFI_USBFN_TRANSFER_RESULT Some of the requested data has been
received from the host. It is the re-
termine if it needs to wait for any re-
maining data. The Buffer supplied to
payload.
EﬁUsbMsgBusEventReset None A RESET bus event was signaled.
EﬁUsbMsgBusEventDetach None A DETACH bus event was signaled.
EﬁUsbMsgBusEventAttach None An ATTACH bus event was signaled.
EﬁUsbMsgBusEventSuspend None A SUSPEND bus event was signaled.
EﬁUsbMsgBusEventResume None A RESUME bus event was signaled.
17.3. USB Function Protocol 709Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 17.33 – continued from previous page
EﬁUsbMsgBusEventSpeed EFI_USB_BUS_SPEED A Bus speed update was signaled.
EFI_INV ALID_PARAMETE A parameter is invalid.
EFI_BUFFER_TOO_SMALL The Supplied buffer is not large enough to hold the message payload.
typedef enum _EFI_USBFN_MESSAGE {
//
// Nothing
//
EfiUsbMsgNone = 0,
//
// SETUP packet isreceived, returned Buffer contains
// EFI_USB_DEVICE_REQUEST struct
//
EfiUsbMsgSetupPacket,
//
// Indicates that some of the requested data has been
// received from the host. It isthe responsibility of the
//class driver to determine ifit needs to wait forany
// remaining data. Returned Buffer contains
// EFI_USBFN_TRANSFER_RESULT struct containing endpoint
// number, transfer status andcount of bytes received.
//
EfiUsbMsgEndpointStatusChangedRx,
//
// transmitted to the host. It isthe responsibility of the
//class driver to determine ifanyremaining data needs to be
// resent. Returned Buffer contains
// number, transferstatus andcount of bytes sent.
//
EfiUsbMsgEndpointStatusChangedTx,
//
// DETACH bus event signaled
//
EfiUsbMsgBusEventDetach,
//
// ATTACH bus event signaled
//
EfiUsbMsgBusEventAttach,
//
// RESET bus event signaled
//
EfiUsbMsgBusEventReset,
//
17.3. USB Function Protocol 710Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// SUSPEND bus event signaled
//
EfiUsbMsgBusEventSuspend,
//
// RESUME bus event signaled
//
EfiUsbMsgBusEventResume,
//
// Bus speed updated, returned buffer indicated bus speed
// using following enumeration named EFI_USB_BUS_SPEED
//
EfiUsbMsgBusEventSpeed
} EFI_USBFN_MESSAGE;
typedef enum _EFI_USBFN_TRANSFER_STATUS {
UsbTransferStatusUnknown = 0,

//
//
//
//
//
//
//
//
//
//
//
//
//
UsbTransferStatusComplete,
UsbTransferStatusAborted,
UsbTransferStatusActive,
UsbTransferStatusNone
} EFI_USBFN_TRANSFER_STATUS;
typedef struct _EFI_USBFN_TRANSFER_RESULT {
UINTN BytesTransferred;
EFI_USBFN_TRANSFER_STATUS TransferStatus;
UINT8 EndpointIndex;
EFI_USBFN_ENDPOINT_DIRECTION Direction;
} EFI_USBFN_TRANSFER_RESULT;
typedef enum _EFI_USB_BUS_SPEED {
UsbBusSpeedUnknown = 0,
UsbBusSpeedLow,
UsbBusSpeedFull,
UsbBusSpeedHigh,
UsbBusSpeedSuper,
UsbBusSpeedMaximum = UsbBusSpeedSuper
} EFI_USB_BUS_SPEED;
typedef union _EFI_USBFN_MESSAGE_PAYLOAD {
EFI_USB_DEVICE_REQUEST udr;
EFI_USBFN_TRANSFER_RESULT utr;
EFI_USB_BUS_SPEED ubs;
} EFI_USBFN_MESSAGE_PAYLOAD;
17.3.11 EFI_USBFN_IO_PROTOCOL.Transfer()
Summary
This function handles transferring data to or from the host on the speciﬁed endpoint, depending on the direction
speciﬁed.
Prototype
typedef
17.3. USB Function Protocol 711Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
(EFIAPI *EFI_USBFN_IO_TRANSFER) (
);
EndpointIndex Indicates the endpoint on which TX or RX transfer needs to take place.
Direction Direction of the endpoint. Refer to the Related Deﬁnitions of the
BufferSize IfDirection is EﬁUsbEndpointDirectionDeviceRx: On input, the size of the Buffer in bytes. On output,
the amount of data returned in Buffer in bytes.
IfDirection is EﬁUsbEndpointDirectionDeviceTx: On input, the size of the Buffer in bytes. On output, the
amount of data transmitted in bytes.
Buffer IfDirection is EﬁUsbEndpointDirectionDeviceRx: The Buffer to return the received data.
IfDirection is EﬁUsbEndpointDirectionDeviceTx: The Buffer that contains the data to be transmitted.
Note: This buffer is allocated and freed using the EFI_USBFN_IO_PROTOCOL.ABORTTRANSFER() and
EFI_USBFN_IO_PROTOCOL.FreeTransferBuffer() functions. The caller of this function must not free or reuse
the buffer until EﬁUsbMsgEndpointStatusChangedRx orEﬁUsbMsgEndpointStatusChangedTx message was received
along with the address of the transfer buffer as part of the message payload. Refer to the function deﬁnition for
EFI_USBFN_IO_PROTOCOL.EventHandler() for more information on various messages and their payloads.
speciﬁed.
Direction Description
EﬁUsbEndpointDirectionDeviceTx Start a transmit transfer on the speciﬁed endpoint and return immediately.
EﬁUsbEndpointDirectionDeviceRx Start a receive transfer on the speciﬁed endpoint and return immediately with available data.
A class driver must call EFI_USBFN_IO_PROTOCOL.EventHandler() repeatedly to receive updates on the trans-
fer status and the number of bytes transferred on various endpoints. Upon an update of the transfer status,
theBuffer ﬁeld of the EFI_USBFN_TRANSFER_RESULT structure (as described in the function description for
EFI_USBFN_IO_PROTOCOL.EventHandler() must be initialized with the Buffer pointer that was supplied to this
method.
The overview of the call sequence is illustrated in Figure Sequence of Operations with Endpoint Policy Changes .
This function should fail with EFI_INVALID_PARAMETER if the speciﬁed direction is incorrect for the endpoint.
17.3. USB Function Protocol 712Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
17.3.12 EFI_USBFN_IO_PROTOCOL.GetMaxTransferSize()
Summary
Returns the maximum supported transfer size.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_GET_MAXTRANSFER_SIZE) (
OUT UINTN *MaxTransferSize
);
MaxTransferSize The maximum supported transfer size, in bytes.
Returns the maximum number of bytes that the underlying controller can accommodate in a single transfer.
17.3.13 EFI_USBFN_IO_PROTOCOL.AllocateTransferBuffer()
Summary
Allocates a transfer buffer of the speciﬁed size that satisﬁes the controller requirements.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (
);
Size The number of bytes to allocate for the transfer buffer.
TheAllocateTransferBuffer() function allocates a memory region of Sizebytes and returns the address of the allocated
memory that satisﬁes the underlying controller requirements in the location referenced by Buffer .
17.3. USB Function Protocol 713Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The allocated transfer buffer must be freed using a matching call EFI_USBFN_IO_PROTOCOL.FreeTransferBuffer()
function.
EFI_OUT_OF_RESOURCES The requested transfer buffer could not be allocated.
17.3.14 EFI_USBFN_IO_PROTOCOL.FreeTransferBuffer()
Summary
Deallocates the memory allocated for the transfer buffer by the EFI_USBFN_IO_PROTOCOL.AllocateTransferBuffer()
function.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_FREE_TRANSFER_BUFFER) (
);
Buffer A pointer to the transfer buffer to deallocate.
The EFI_USBFN_IO_PROTOCOL.FreeTransferBuffer() function deallocates the memory speciﬁed by Buffer . The
Buffer that is freed must have been allocated by EFI_USBFN_IO_PROTOCOL.AllocateTransferBuffer() .
17.3.15 EFI_USBFN_IO_PROTOCOL.StartController()
Summary
This function supplies power to the USB controller if needed and initializes the hardware and the internal data struc-
tures. The port must not be activated by this function
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_START_CONTROLLER) (
IN EFI_USBFN_IO_PROTOCOL *This
);
17.3. USB Function Protocol 714Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function starts the hardware by supplying power to the USB controller if needed, and initializing the hardware
and internal data structures. The port must not be activated by this function.
17.3.16 EFI_USBFN_IO_PROTOCOL.StopController()
Summary
This function stops the USB hardware device.
Prototype
typedef
(EFIAPI *EFI_USBFN_IO_STOP_CONTROLLER) (
);
17.3.16.1 Description
This function stops the USB hardware device
17.3.17 EFI_USBFN_IO_PROTOCOL.SetEndpointPolicy()
Summary
This function sets the conﬁguration policy for the speciﬁed non-control endpoint. Refer to the description for calling
restrictions.
Prototype
typedef
(EFIAPI *EFI_USBFN_SET_ENDPOINT_POLICY) (
IN UINT8 EndpointIndex
17.3. USB Function Protocol 715Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_USBFN_POLICY_TYPE PolicyType,
);
EndpointIndex Indicates the non-control endpoint for which the policy needs to be set.
EFI_USBFN_IO_PROTOCOL.AbortTransfer() function for details.
PolicyType Policy type the user is trying to set for the speciﬁed non-control endpoint. Refer to Related Deﬁnitions
for this function below for details.

Summary
Prototype
typedef
);
BufferSize The size of the Buffer in bytes.
Buffer The new value for the policy parameter that PolicyType speciﬁes. Refer to Related Deﬁnitions for this func-
tion below for details.
This function sets the conﬁguration policy for the speciﬁed non-control endpoint. This function can only be called
before EFI_USBFN_IO_PROTOCOL.StartController() or after EFI_USBFN_IO_PROTOCOL.StopController() has
been called.
EFI_UNSUPPORTED Changing this policy value is not supported.
typedef enum _EFI_USBFN_POLICY_TYPE
{
EfiUsbPolicyUndefined = 0,
EfiUsbPolicyMaxTransactionSize,
EfiUsbPolicyZeroLengthTerminationSupport,
EfiUsbPolicyZeroLengthTermination
} EFI_USBFN_POLICY_TYPE;
EﬁUsbPolicyUndeﬁned Invalid policy value that must never be used across driver boundary. If used, the function
must not return a success status code.
EﬁUsbPolicyMaxTransactionSize EﬁUsbPolicyMaxTransactionSize is only used with
EFI_USBFN_IO_PROTOCOL.GETENDPOINTPOLICY() . It provides the size of the largest single transaction
(delivery of service to an endpoint) supported by a controller. It must be greater than or equal to the maximum
transfer size that can be retrieved by calling EFI_USBFN_IO_PROTOCOL.GETMAXTRANSFERSIZE() .
GetEndpointPolicy SetEndpointPolicy
17.3. USB Function Protocol 716Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 17.41 – continued from previous page
BufferSize 4 bytes,
sizeof(UINT32)Not applicable
Return Status EFI_STATUS EFI_UNSUPPORTED
EﬁUsbPolicyZeroLengthTerminationSupport
EﬁUsbPolicyZeroLengthTerminationSupport is only used with XXX
EFI_USBFN_IO_PROTOCOL.GETENDPOINTPOLICY() . It is TRUE if the USB controller is capable of
automatically handling zero length packets when the transfer size is a multiple of USB maximum packet size
andFALSE if it is not supported by the controller.
BufferSize 1 byte, sizeof
(BOOLEAN)Not applicable
EﬁUsbPolicyZeroLengthTermination When used with EFI_USBFN_IO_PROTOCOL.GETENDPOINTPOLICY() ,
aTRUE value is returned if the USB controller hardware is conﬁgured to automatically handle zero length
packets when the transfer size is a multiple of USB maximum packet size; a FALSE value is returned if the
controller hardware is not conﬁgured to do this.
Using EFI_USBFN_IO_PROTOCOL.SETENDPOINTPOLICY() to set the EﬁUsbPolicyZeroLengthTermina-
tion policy is only applicable to USB controller hardware capable of supporting automatic zero length packet
termination. When this value is set to TRUE , the controller must be conﬁgured to handle zero length termina-
tion for the speciﬁed endpoint. When this value is set to FALSE , the controller must be conﬁgured to not handle
zero length termination for the speciﬁed endpoint.
The USB controller’s default policy must not enable automatic zero length packet termination, even if the
hardware is capable of supporting it.
(BOOLEAN)1 byte, sizeof (BOOLEAN)
Return Status EFI_STATUS EFI_STATUS
17.3.18 EFI_USBFN_IO_PROTOCOL.GetEndpointPolicy()
Summary
This function retrieves the conﬁguration policy for the speciﬁed non-control endpoint. There are no associated calling
restrictions for this function.
Prototype
typedef
(EFIAPI *EFI_USBFN_GET_ENDPOINT_POLICY) (
17.3. USB Function Protocol 717Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
EFI_USBFN_IO_PROTOCOL.Aborttransfer() function for details.
PolicyType Policy type the user is trying to retrieve for the speciﬁed non-control endpoint. Refer to the Related
Deﬁnitions for the EFI_USBFN_IO_PROTOCOL.Setendpointpolicy() function for details.
BufferSize On input, the size of Buffer in bytes. On output, the amount of data returned in Buffer in bytes.
Buffer A pointer to a buffer to return requested endpoint policy value. Refer to the Related Deﬁnitions for the
EFI_USBFN_IO_PROTOCOL.SetEndpointPolicy() function for size requirements of various policy types.
This function retrieves the conﬁguration policy for the speciﬁed non-control endpoint. This function has no calling
EFI_UNSUPPORTED The speciﬁed policy value is not supported.
EFI_BUFFER_TOO_SMALL Supplied buffer is not large enough to hold requested policy value.
17.3.19 USB Function Sequence Diagram
17.3. USB Function Protocol 718Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 17.3: Sequence of Operations with Endpoint Policy Changes17.3. USB Function Protocol 719CHAPTER
EIGHTEEN
PROTOCOLS — DEBUGGER SUPPORT
This chapter describes a minimal set of protocols and associated data structures necessary to enable the creation
of source level debuggers for EFI. It does not fully deﬁne a debugger design. Using the services described in this
document, it should also be possible to implement a variety of debugger solutions.
18.1 Overview
Efﬁcient UEFI driver and application development requires the availability of source level debugging facilities. Al-
though completely on-target debuggers are clearly possible, UEFI debuggers are generally expected to be remotely
hosted. That is to say, the debugger itself will be split between two machines, which are the host and target. A majority
of debugger code runs on the host that is typically responsible for disassembly, symbol management, source display,
and user interface. Similarly, a smaller piece of code runs on the target that establishes the communication to the host
and proxies requests from the host. The on-target code is known as the “debug agent.”
The debug agent design is subdivided further into two parts, which are the processor/platform abstraction and the
debugger host speciﬁc communication grammar. This speciﬁcation describes architectural interfaces for the former
only. Speciﬁc implementations for various debugger host communication grammars can be created that make use of
the facilities described in this speciﬁcation.
The processor/platform abstraction is presented as a pair of protocol interfaces, which are the Debug Support protocol
and the Debug Port protocol.
The Debug Support protocol abstracts the processor’s debugging facilities, namely a mechanism to manage the pro-
cessor’s context via caller-installable exception handlers.
The Debug Port protocol abstracts the device that is used for communication between the host and target. Typically
this will be a 16550 serial port, 1394 device, or other device that is nominally a serial stream.
Furthermore, a table driven, quiescent, memory-only mechanism for determining the base address of PE32+ images is
provided to enable the debugger host to determine where images are located in memory.
Aside from timing differences that occur because of running code associated with the debug agent and user initiated
changes to the machine context, the operation of the on-target debugger component must be transparent to the rest of
the system. In addition, no portion of the debug agent that runs in interrupt context may make any calls to EFI services
or other protocol interfaces.
The services described in this document do not comprise a complete debugger, rather they provide a minimal abstrac-
tion required to implement a wide variety of debugger solutions.
720Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
18.2 EFI Debug Support Protocol
This section deﬁnes the EFI Debug Support protocol which is used by the debug agent.
18.2.1 EFI Debug Support Protocol Overview
The debug-agent needs to be able to gain control of the machine when certain types of events occur; i.e., breakpoints,
processor exceptions, etc. Additionally, the debug agent must also be able to periodically gain control during operation
of the machine to check for asynchronous commands from the host. The EFI Debug Support protocol services enable
these capabilities.
The EFI Debug Support protocol interfaces produce callback registration mechanisms which are used by the debug
agent to register functions that are invoked either periodically or when speciﬁc processor exceptions. When they are

invoked by the Debug Support driver, these callback functions are passed the current machine context record. The
debug agent may modify this context record to change the machine context which is restored to the machine after the
callback function returns. The debug agent does not run in the same context as the rest of UEFI and all modiﬁcations
to the machine context are deferred until after the callback function returns.
It is expected that there will typically be two instances of the EFI Debug Support protocol in the system. One associated
with the native processor instruction set (IA-32, x64, ARM, RISC-V , LoongArch, or Itanium processor family), and
one for the EFI virtual machine that implements EFI byte code (EBC).
While multiple instances of the EFI Debug Support protocol are expected, there must never be more than one for any
given instruction set.
18.2.2 EFI_DEBUG_SUPPORT_PROTOCOL
Summary
This protocol provides the services to allow the debug agent to register callback functions that are called either peri-
odically or when speciﬁc processor exceptions occur.
GUID
#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \
{0x2755590C,0x6F3C,0x42FA,\
{0x9E,0xA4,0xA3,0xBA,0x54,0x3C,0xDA,0x25}}
EFI_INSTRUCTION_SET_ARCHITECTURE Isa;
EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;
EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;
EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;
EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;
} EFI_DEBUG_SUPPORT_PROTOCOL;
IsaDeclares the processor architecture for this instance of the EFI Debug Support protocol.
GetMaximumProcessorIndex
Returns the maximum processor index value that may be used with
EFI_DEBUG_SUPPORT_PROTOCOL.REGISTERPERIODICCALLBACK() ,
18.2. EFI Debug Support Protocol 721Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_DEBUG_SUPPORT_PROTOCOL.REGISTEREXCEPTIONCALLBACK() ,
EFI_DEBUG_SUPPORT_PROTOCOL.GETMAXIMUMPROCESSORINDEX() function description.
RegisterPeriodicCallback Registers a callback function that will be invoked periodically and asynchronously to the
execution of EFI. See the RegisterPeriodicCallback()* function description.
RegisterExceptionCallback Registers a callback function that will be called each time the speciﬁed processor ex-
ception occurs. See the RegisterExceptionCallback()* function description.
InvalidateInstructionCache Invalidate the instruction cache of the processor. This is required by processor archi-
tectures where instruction and data caches are not coherent when instructions in the code under debug has been
modiﬁed by the debug agent. EFI_DEBUG_SUPPORT_PROTOCOL.INVALIDATEINSTRUCTIONCACHE()
Refer to the Microsoft PE/COFF Speciﬁcation revision 6.2 or later for IMAGE_FILE_MACHINE deﬁnitions.
Note: At the time of publication of this speciﬁcation, the latest revision of the PE/COFF speciﬁcation was 6.2. The
deﬁnition of IMAGE_FILE_MACHINE _EBC is not included in revision 6.2 of the PE/COFF speciﬁcation. It will be
added in a future revision of the PE/COFF speciﬁcation.
//
// Machine type definition
//
IsaIa32 = IMAGE_FILE_MACHINE_I386, // 0x014C
IsaX64 = IMAGE_FILE_MACHINE_X64, // 0x8664
IsaIpf = IMAGE_FILE_MACHINE_IA64, // 0x0200
IsaEbc = IMAGE_FILE_MACHINE_EBC, // 0x0EBC
IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED // 0x1C2
IsaAArch64 = IMAGE_FILE_MACHINE_AARCH64 // 0xAA64
IsaRISCV32 = I\nMAGE_FILE_MACHINE_RISCV32 // 0x5032
IsaRISCV64 = IMAGE_FILE_MACHINE_RISCV64 // 0x5064
IsaRISCV128 = IMAGE_FILE_MACHINE_RISCV128 // 0x5128
IsaLoongArch32 = IMAGE_FILE_MACHINE_LOONGARCH32 // 0x6232
IsaLoongArch64 = IMAGE_FILE_MACHINE_LOONGARCH64 // 0x6264
} EFI_INSTRUCTION_SET_ARCHITECTURE;
The EFI Debug Support protocol provides the interfaces required to register debug agent callback functions and to
manage the processor’s instruction stream as required. Registered callback functions are invoked in interrupt context
when the speciﬁed event occurs.
The driver that produces the EFI Debug Support protocol is also responsible for saving the machine context prior to
invoking a registered callback function and restoring it after the callback function returns prior to returning to the code
under debug. If the debug agent has modiﬁed the context record, the modiﬁed context must be used in the restore
Furthermore, if the debug agent modiﬁes any of the code under debug (to set a software breakpoint for example), it
must call the InvalidateInstructionCache() function for the region of memory that has been modiﬁed.
18.2. EFI Debug Support Protocol 722Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
18.2.3 EFI_DEBUG_SUPPORT_PROTOCOL.GetMaximumProcessorIndex()
Summary
Returns the maximum value that may be used for the ProcessorIndex param-
eter in EFI_DEBUG_SUPPORT_PROTOCOL.REGISTERPERIODICCALLBACK() and
EFI_DEBUG_SUPPORT_PROTOCOL.REGISTEREXCEPTIONCALLBACK() .
Prototype
typedef
(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX) (
IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
OUT UINTN *MaxProcessorIndex
);
This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance. Type EFI_DEBUG_SUPPORT_PROTOCOL
is deﬁned in this section.
MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported processor index is re-
turned.
TheGetMaximumProcessorIndex() function returns the maximum processor index in the output parameter MaxPro-
cessorIndex . This value is the largest value that may be used in the ProcessorIndex parameter for both RegisterPeriod-
icCallback() andRegisterExceptionCallback() . All values between 0 and MaxProcessorIndex must be supported by
RegisterPeriodicCallback() andRegisterExceptionCallback() .
It is the responsibility of the caller to insure all parameters are correct. There is no provision for parameter checking
byGetMaximumProcessorIndex() . The implementation behavior when an invalid parameter is passed is not deﬁned
by this speciﬁcation.
18.2.4 EFI_DEBUG_SUPPORT_PROTOCOL.RegisterPeriodicCallback()
Summary
Registers a function to be called back periodically in interrupt context.
Prototype
typedef
(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK) (
IN UINTN ProcessorIndex,
IN EFI_PERIODIC_CALLBACK PeriodicCallback
);
is deﬁned in EFI_DEBUG_SUPPORT_PROTOCOL .
18.2. EFI Debug Support Protocol 723Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ProcessorIndex Speciﬁes which processor the callback function applies to.
PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main periodic entry point of
the debug agent. It receives as a parameter a pointer to the full context of the interrupted execution thread.
typedef
VOID (*EFI_PERIODIC_CALLBACK) (
IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
// Universal EFI_SYSTEM_CONTEXT definition
EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
EFI_SYSTEM_CONTEXT_RISCV32 *SystemContextRiscV32;
EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
EFI_SYSTEM_CONTEXT_RISCV128 *SystemContextRiscv128;
EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLongArch64;
} EFI_SYSTEM_CONTEXT;
// System context forvirtual EBC processors
UINT64 R0, R1, R2, R3, R4, R5, R6, R7;
UINT64 Flags;
UINT64 ControlFlags;
UINT64 Ip;
} EFI_SYSTEM_CONTEXT_EBC;
// System context forRISC-V 32
// Integer registers
UINT32 Zero, Ra, Sp, Gp, Tp, T0, T1, T2;
UINT32 S0FP, S1, A0, A1, A2, A3, A4, A5, A6, A7;
UINT32 S2, S3, S4, S5, S6, S7, S8, S9, S10, S11;
UINT32 T3, T4, T5, T6;
// Floating registers forF, DandQ Standard Extensions
UINT128 Ft0, Ft1, Ft2, Ft3, Ft4, Ft5, Ft6, Ft7;
UINT128 Fs0, Fs1, Fa0, Fa1, Fa2, Fa3, Fa4, Fa5, Fa6, Fa7;
UINT128 Fs2, Fs3, Fs4, Fs5, Fs6, Fs7, Fs8, Fs9, Fs10, Fs11;
UINT128 Ft8, Ft9, Ft10, Ft11;
} EFI_SYSTEM_CONTEXT_RISCV32;
// System context forRISC-V 64
UINT64 Zero, Ra, Sp, Gp, Tp, T0, T1, T2;
UINT64 S0FP, S1, A0, A1, A2, A3, A4, A5, A6, A7;
UINT64 S2, S3, S4, S5, S6, S7, S8, S9, S10, S11;
UINT64 T3, T4, T5, T6;
18.2. EFI Debug Support Protocol 724Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_SYSTEM_CONTEXT_RISCV64;
// System context forRISC-V 128

UINT128Zero, Ra, Sp, Gp, Tp, T0, T1, T2;
UINT128S0FP, S1, A0, A1, A2, A3, A4, A5, A6, A7;
UINT128S2, S3, S4, S5, S6, S7, S8, S9, S10, S11;
UINT128T3, T4, T5, T6;
} EFI_SYSTEM_CONTEXT_RISCV128;
Note: When the context record ﬁeld is larger than the register being stored in it, the upper bits of the context record
ﬁeld are unused and ignored .
// System context forIA-32 processors
UINT32 ExceptionData; // ExceptionData isadditional data pushed
// on the stack by some types of IA-32
// exceptions
EFI_FX_SAVE_STATE_IA32 FxSaveState;
UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
UINT32 Cr0, Cr1 / *Reserved */, Cr2, Cr3, Cr4;
UINT32 Eflags;
UINT32 Ldtr, Tr;
UINT32 Gdtr[2], Idtr[2];
UINT32 Eip;
UINT32 Gs, Fs, Es, Ds, Cs, Ss;
UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
} EFI_SYSTEM_CONTEXT_IA32;
// FXSAVE_STATE - FP / MMX / XMM registers
UINT16 Fcw;
UINT16 Fsw;
UINT16 Ftw;
UINT16 Opcode;
UINT16 Cs;
UINT16 Reserved1;
UINT32 DataOffset;
UINT16 Ds;
18.2. EFI Debug Support Protocol 725Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT8 Reserved2[10];
UINT8 St0Mm0[10], Reserved3[6];
UINT8 St1Mm1[10], Reserved4[6];
UINT8 St2Mm2[10], Reserved5[6];
UINT8 St3Mm3[10], Reserved6[6];
UINT8 St4Mm4[10], Reserved7[6];
UINT8 St5Mm5[10], Reserved8[6];
UINT8 St6Mm6[10], Reserved9[6];
UINT8 St7Mm7[10], Reserved10[6];
UINT8 Xmm0[16];
UINT8 Xmm1[16];
UINT8 Xmm2[16];
UINT8 Xmm3[16];
UINT8 Xmm4[16];
UINT8 Xmm5[16];
UINT8 Xmm6[16];
UINT8 Xmm7[16];
UINT8 Reserved11[14 *16];
} EFI_FX_SAVE_STATE_IA32
// System context forx64 processors
UINT64 ExceptionData; // ExceptionData is
// additional data pushed
// on the stack by some
// types of x64 64-bit
// mode exceptions
EFI_FX_SAVE_STATE_X64 FxSaveState;
UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
UINT64 Cr0, Cr1 / *Reserved */, Cr2, Cr3, Cr4, Cr8;
UINT64 Rflags;
UINT64 Ldtr, Tr;
UINT64 Gdtr[2], Idtr[2];
UINT64 Rip;
UINT64 Gs, Fs, Es, Ds, Cs, Ss;
UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
} EFI_SYSTEM_CONTEXT_X64;
UINT64 DataOffset;
UINT8 Reserved1[8];
UINT8 St0Mm0[10], Reserved2[6];
UINT8 St1Mm1[10], Reserved3[6];
UINT8 St2Mm2[10], Reserved4[6];
UINT8 St3Mm3[10], Reserved5[6];
UINT8 St4Mm4[10], Reserved6[6];
UINT8 St5Mm5[10], Reserved7[6];
UINT8 St6Mm6[10], Reserved8[6];
UINT8 St7Mm7[10], Reserved9[6];
18.2. EFI Debug Support Protocol 726Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_FX_SAVE_STATE_X64;
// System context forItanium processor family
UINT64 Reserved;
UINT64 R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
R31;
UINT64 F2[2], F3[2], F4[2], F5[2], F6[2],
F7[2], F8[2], F9[2], F10[2], F11[2],
F12[2], F13[2], F14[2], F15[2], F16[2],
F17[2], F18[2], F19[2], F20[2], F21[2],
F22[2], F23[2], F24[2], F25[2], F26[2],
F27[2], F28[2], F29[2], F30[2], F31[2];
UINT64 Pr;
UINT64 B0, B1, B2, B3, B4, B5, B6, B7;
// application registers
UINT64 ArRsc, ArBsp, ArBspstore, ArRnat;
UINT64 ArFcr;
UINT64 ArEflag, ArCsd, ArSsd, ArCflg;
UINT64 ArFsr, ArFir, ArFdr;
UINT64 ArCcv;
UINT64 ArUnat;
UINT64 ArFpsr;
UINT64 ArPfs, ArLc, ArEc;
// control registers
UINT64 CrDcr, CrItm, CrIva, CrPta, CrIpsr, CrIsr;
UINT64 CrIip, CrIfa, CrItir, CrIipa, CrIfs, CrIim;
UINT64 CrIha;
// debug registers
UINT64 Dbr0, Dbr1, Dbr2, Dbr3, Dbr4, Dbr5, Dbr6, Dbr7;
UINT64 Ibr0, Ibr1, Ibr2, Ibr3, Ibr4, Ibr5, Ibr6, Ibr7;
// virtual registers
UINT64 IntNat; // nat bits forR1-R31
} EFI_SYSTEM_CONTEXT_IPF;
//
// ARM processor context definition
//
18.2. EFI Debug Support Protocol 727Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT32 R0;
UINT32 R1;
UINT32 R2;
UINT32 R3;
UINT32 R4;
UINT32 R5;
UINT32 R6;
UINT32 R7;
UINT32 R8;
UINT32 R9;
UINT32 R10;
UINT32 R11;
UINT32 R12;
UINT32 SP;
UINT32 LR;
UINT32 PC;
UINT32 CPSR;
UINT32 DFSR;
UINT32 DFAR;
UINT32 IFSR;
} EFI_SYSTEM_CONTEXT_ARM;
//
///
/// AARCH64 processor context definition.
///
// General Purpose Registers
UINT64 X0;
UINT64 X1;
UINT64 X2;
UINT64 X3;
UINT64 X4;
UINT64 X5;
UINT64 X6;
UINT64 X7;
UINT64 X8;
UINT64 X9;
UINT64 X10;
UINT64 X11;
UINT64 X12;
UINT64 X13;
UINT64 X14;
UINT64 X15;
UINT64 X16;
UINT64 X17;
UINT64 X18;
UINT64 X19;
UINT64 X20;
UINT64 X21;
UINT64 X22;
UINT64 X23;
UINT64 X24;
UINT64 X25;
UINT64 X26;
UINT64 X27;
18.2. EFI Debug Support Protocol 728Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT64 X28;
UINT64 FP; // x29 - Frame Pointer
UINT64 LR; // x30 - Link Register
UINT64 SP; // x31 - Stack Pointer
// FP/SIMD Registers
UINT64 V0[2];
UINT64 V1[2];
UINT64 V2[2];
UINT64 V3[2];
UINT64 V4[2];
UINT64 V5[2];
UINT64 V6[2];
UINT64 V7[2];
UINT64 V8[2];
UINT64 V9[2];
UINT64 V10[2];
UINT64 V11[2];
UINT64 V12[2];
UINT64 V13[2];
UINT64 V14[2];
UINT64 V15[2];
UINT64 V16[2];
UINT64 V17[2];
UINT64 V18[2];
UINT64 V19[2];
UINT64 V20[2];
UINT64 V21[2];
UINT64 V22[2];
UINT64 V23[2];
UINT64 V24[2];
UINT64 V25[2];
UINT64 V26[2];
UINT64 V27[2];
UINT64 V28[2];
UINT64 V29[2];
UINT64 V30[2];
UINT64 V31[2];
UINT64 ELR; // Exception Link Register
UINT64 SPSR; // Saved Processor Status Register
UINT64 FPSR; // Floating Point Status Register
UINT64 ESR; // Exception syndrome register
UINT64 FAR; // Fault Address Register
} EFI_SYSTEM_CONTEXT_AARCH64;
// System context forLoongArch64 processors
UINT64 R0;
UINT64 R1;
UINT64 R2;
UINT64 R3;
UINT64 R4;
UINT64 R5;
UINT64 R6;
UINT64 R7;
UINT64 R8;
18.2. EFI Debug Support Protocol 729Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT64 R9;
UINT64 R10;
UINT64 R11;
UINT64 R12;
UINT64 R13;
UINT64 R14;
UINT64 R15;
UINT64 R16;
UINT64 R17;
UINT64 R18;
UINT64 R19;
UINT64 R20;
UINT64 R21;
UINT64 R22;
UINT64 R23;
UINT64 R24;
UINT64 R25;
UINT64 R26;
UINT64 R27;
UINT64 R28;
UINT64 R29;
UINT64 R30;
UINT64 R31;
UINT64 CRMD; // CuRrent MoDe information
UINT64 PRMD; // PRe-exception MoDe information
UINT64 EUEN; // Extended component Unit ENable
UINT64 MISC; // MISCellaneous controller
UINT64 ECFG; // Execption ConFiGuration
UINT64 ESTAT; // Exeption STATus
UINT64 ERA; // Exception Return Address
UINT64 BADV; // BAD Virtual address
UINT64 BADI; // BAD Instruction
} EFI_SYSTEM_CONTEXT_LOONGARCH64;
The RegisterPeriodicCallback() function registers and enables the on-target debug agent’s periodic entry point. To
unregister and disable calling the debug agent’s periodic entry point, call RegisterPeriodicCallback() passing a NULL
PeriodicCallback parameter.
The implementation must handle saving and restoring the processor context to/from the system context record around
calls to the registered callback function.
If the interrupt is also used by the ﬁrmware for the EFI time base or some other use, two rules must be observed. First,
the registered callback function must be called before any EFI processing takes place. Second, the Debug Support
implementation must perform the necessary steps to pass control to the ﬁrmware’s corresponding interrupt handler in
a transparent manner.
There is no quality of service requirement or speciﬁcation regarding the frequency of calls to the registered Periodic-
Callback function. This allows the implementation to mitigate a potential adverse impact to EFI timer based services
due to the latency induced by the context save/restore and the associated callback function.
byRegisterPeriodicCallback() . The implementation behavior when an invalid parameter is passed is not deﬁned by
18.2. EFI Debug Support Protocol 730Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_ALREADY_STARTED Non- NULL PeriodicCallback parameter when a callback function was pre-
viously registered.
EFI_OUT_OF_RESOURCES System has insufﬁcient memory resources to register new callback function.
18.2.5 EFI_DEBUG_SUPPORT_PROTOCOL.RegisterExceptionCallback()
Summary

Summary
Registers a function to be called when a given processor exception occurs.
Prototype
typedef
(EFIAPI *REGISTER_EXCEPTION_CALLBACK) (
IN EFI_EXCEPTION_CALLBACK ExceptionCallback,
IN EFI_EXCEPTION_TYPE ExceptionType
);
ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK* that is called when the processor
exception speciﬁed by ExceptionType occurs. Passing NULL unregisters any previously registered function
associated with ExceptionType .
ExceptionType Speciﬁes which processor exception to hook.
typedef
VOID (*EFI_EXCEPTION_CALLBACK) (
IN EFI_EXCEPTION_TYPE ExceptionType,
);
typedef INTN EFI_EXCEPTION_TYPE;
// EBC Exception types
#define EXCEPT_EBC_UNDEFINED 0
#define EXCEPT_EBC_DIVIDE_ERROR 1
#define EXCEPT_EBC_DEBUG 2
#define EXCEPT_EBC_BREAKPOINT 3
#define EXCEPT_EBC_OVERFLOW 4
#define EXCEPT_EBC_INVALID_OPCODE 5
#define EXCEPT_EBC_STACK_FAULT 6
#define EXCEPT_EBC_ALIGNMENT_CHECK 7
#define EXCEPT_EBC_INSTRUCTION_ENCODING 8
#define EXCEPT_EBC_BAD_BREAK 9
#define EXCEPT_EBC_SINGLE_STEP 10
18.2. EFI Debug Support Protocol 731Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// IA-32 Exception types
#define EXCEPT_IA32_DIVIDE_ERROR 0
#define EXCEPT_IA32_DEBUG 1
#define EXCEPT_IA32_NMI 2
#define EXCEPT_IA32_BREAKPOINT 3
#define EXCEPT_IA32_OVERFLOW 4
#define EXCEPT_IA32_BOUND 5
#define EXCEPT_IA32_INVALID_OPCODE 6
#define EXCEPT_IA32_DOUBLE_FAULT 8
#define EXCEPT_IA32_INVALID_TSS 10
#define EXCEPT_IA32_SEG_NOT_PRESENT 11
#define EXCEPT_IA32_STACK_FAULT 12
#define EXCEPT_IA32_GP_FAULT 13
#define EXCEPT_IA32_PAGE_FAULT 14
#define EXCEPT_IA32_FP_ERROR 16
#define EXCEPT_IA32_ALIGNMENT_CHECK 17
#define EXCEPT_IA32_MACHINE_CHECK 18
#define EXCEPT_IA32_SIMD 19
//
// X64 Exception types
//
#define EXCEPT_X64_DIVIDE_ERROR 0
#define EXCEPT_X64_DEBUG 1
#define EXCEPT_X64_NMI 2
#define EXCEPT_X64_BREAKPOINT 3
#define EXCEPT_X64_OVERFLOW 4
#define EXCEPT_X64_BOUND 5
#define EXCEPT_X64_INVALID_OPCODE 6
#define EXCEPT_X64_DOUBLE_FAULT 8
#define EXCEPT_X64_INVALID_TSS 10
#define EXCEPT_X64_SEG_NOT_PRESENT 11
#define EXCEPT_X64_STACK_FAULT 12
#define EXCEPT_X64_GP_FAULT 13
#define EXCEPT_X64_PAGE_FAULT 14
#define EXCEPT_X64_FP_ERROR 16
#define EXCEPT_X64_ALIGNMENT_CHECK 17
#define EXCEPT_X64_MACHINE_CHECK 18
#define EXCEPT_X64_SIMD 19
// Itanium Processor Family Exception types
#define EXCEPT_IPF_VHTP_TRANSLATION 0
#define EXCEPT_IPF_INSTRUCTION_TLB 1
#define EXCEPT_IPF_DATA_TLB 2
#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3
#define EXCEPT_IPF_ALT_DATA_TLB 4
#define EXCEPT_IPF_DATA_NESTED_TLB 5
#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6
#define EXCEPT_IPF_DATA_KEY_MISSED 7
#define EXCEPT_IPF_DIRTY_BIT 8
#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9
#define EXCEPT_IPF_DATA_ACCESS_BIT 10
#define EXCEPT_IPF_BREAKPOINT 11
#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12
// 13 - 19 reserved
#define EXCEPT_IPF_PAGE_NOT_PRESENT 20
18.2. EFI Debug Support Protocol 732Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EXCEPT_IPF_KEY_PERMISSION 21
#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22
#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23
#define EXCEPT_IPF_GENERAL_EXCEPTION 24
#define EXCEPT_IPF_DISABLED_FP_REGISTER 25
#define EXCEPT_IPF_NAT_CONSUMPTION 26
#define EXCEPT_IPF_SPECULATION 27
// 28 reserved
#define EXCEPT_IPF_DEBUG 29
#define EXCEPT_IPF_UNALIGNED_REFERENCE 30
#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31
#define EXCEPT_IPF_FP_FAULT 32
#define EXCEPT_IPF_FP_TRAP 33
#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34
#define EXCEPT_IPF_TAKEN_BRANCH 35
#define EXCEPT_IPF_SINGLE_STEP 36
// 37 - 44 reserved
#define EXCEPT_IPF_IA32_EXCEPTION 45
#define EXCEPT_IPF_IA32_INTERCEPT 46
#define EXCEPT_IPF_IA32_INTERRUPT 47
//
// ARM processor exception types
//
#define EXCEPT_ARM_RESET 0
#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
#define EXCEPT_ARM_PREFETCH_ABORT 3
#define EXCEPT_ARM_DATA_ABORT 4
#define EXCEPT_ARM_RESERVED 5
#define EXCEPT_ARM_IRQ 6
#define EXCEPT_ARM_FIQ 7
//
// For coding convenience, define the maximum valid ARM
// exception.
//
#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
///
/// AARCH64 processor exception types.
///
#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0
#define EXCEPT_AARCH64_IRQ 1
#define EXCEPT_AARCH64_FIQ 2
#define EXCEPT_AARCH64_SERROR 3
///
/// For coding convenience, define the maximum valid
/// AARCH64 exception.
///
#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR
///
/// RISC-V processor exception types.
///
#define EXCEPT_RISCV_INST_MISALIGNED 0
#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
#define EXCEPT_RISCV_ILLEGAL_INST 2
#define EXCEPT_RISCV_BREAKPOINT 3
#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
18.2. EFI Debug Support Protocol 733Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
#define EXCEPT_RISCV_INST_PAGE_FAULT 12
#define EXCEPT_RISCV_LOAD_PAGE_FAULT 13
#define EXCEPT_RISCV_STORE_AMO_PAGE_FAULT 15
///
/// RISC-V processor interrupt types.
///
#define EXCEPT_RISCV_SUPERVISOR_SOFTWARE_INT 1
#define EXCEPT_RISCV_MACHINE_SOFTWARE_INT 3
#define EXCEPT_RISCV_SUPERVISOR_TIMER_INT 5
#define EXCEPT_RISCV_MACHINE_TIMER_INT 7
#define EXCEPT_RISCV_SUPERVISOR_EXTERNAL_INT 9
#define EXCEPT_RISCV_MACHINE_EXTERNAL_INT 11
//
// LoongArch processor exception types.
//
#define EXCEPT_LOONGARCH_INT 0
#define EXCEPT_LOONGARCH_PIL 1
#define EXCEPT_LOONGARCH_PIS 2
#define EXCEPT_LOONGARCH_PIF 3
#define EXCEPT_LOONGARCH_PME 4
#define EXCEPT_LOONGARCH_PNR 5
#define EXCEPT_LOONGARCH_PNX 6
#define EXCEPT_LOONGARCH_PPI 7
#define EXCEPT_LOONGARCH_ADE 8
#define EXCEPT_LOONGARCH_ALE 9
#define EXCEPT_LOONGARCH_BCE 10
#define EXCEPT_LOONGARCH_SYS 11
#define EXCEPT_LOONGARCH_BRK 12
#define EXCEPT_LOONGARCH_INE 13
#define EXCEPT_LOONGARCH_IPE 14
#define EXCEPT_LOONGARCH_FPD 15
#define EXCEPT_LOONGARCH_SXD 16
#define EXCEPT_LOONGARCH_ASXD 17
#define EXCEPT_LOONGARCH_FPE 18
//
// LoongArch processor Interrupt types.
//
#define EXCEPT_LOONGARCH_INT_SIP0 0
#define EXCEPT_LOONGARCH_INT_SIP1 1
#define EXCEPT_LOONGARCH_INT_IP0 2
#define EXCEPT_LOONGARCH_INT_IP1 3
#define EXCEPT_LOONGARCH_INT_IP2 4
#define EXCEPT_LOONGARCH_INT_IP3 5
#define EXCEPT_LOONGARCH_INT_IP4 6
#define EXCEPT_LOONGARCH_INT_IP5 7
#define EXCEPT_LOONGARCH_INT_IP6 8
18.2. EFI Debug Support Protocol 734Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EXCEPT_LOONGARCH_INT_IP7 9
#define EXCEPT_LOONGARCH_INT_PMC 10
#define EXCEPT_LOONGARCH_INT_TIMER 11
#define EXCEPT_LOONGARCH_INT_IPI 12
//
// For coding convenience, define the maximum valid
// LoongArch interrupt.
//
#define MAX_LOONGARCH_INTERRUPT 14
TheRegisterExceptionCallback() function registers and enables an exception callback function for the speciﬁed ex-
ception. The speciﬁed exception must be valid for the instruction set architecture. To unregister the callback function
and stop servicing the exception, call RegisterExceptionCallback() passing a NULL ExceptionCallback parameter.
calls to the registered callback function. No chaining of exception handlers is allowed.
byRegisterExceptionCallback() . The implementation behavior when an invalid parameter is passed is not deﬁned by
EFI_ALREADY_STARTED Non- NULL ExceptionCallback parameter when a callback function was
previously registered.
18.2.6 EFI_DEBUG_SUPPORT_PROTOCOL.InvalidateInstructionCache()
Summary
Invalidates processor instruction cache for a memory range. Subsequent execution in this range causes a fresh memory
fetch to retrieve code to be executed.
Prototype
typedef
(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE) (
IN VOID *Start,
IN UINT64 Length
);

Summary
Prototype
typedef
);
ProcessorIndex Speciﬁes which processor’s instruction cache is to be invalidated.
Start Speciﬁes the physical base of the memory range to be invalidated.
18.2. EFI Debug Support Protocol 735Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Length Speciﬁes the minimum number of bytes in the processor’s instruction cache to invalidate.
Typical operation of a debugger may require modifying the code image that is under debug. This can occur for many
reasons, but is typically done to insert/remove software break instructions. Some processor architectures do not have
coherent instruction and data caches so modiﬁcations to the code image require that the instruction cache be explicitly
invalidated in that memory region.
TheInvalidateInstructionCache() function abstracts this operation from the debug agent and provides a general pur-
pose capability to invalidate the processor’s instruction cache.
It is the responsibility of the caller to insure all parameters are correct. There is no provision for parameter checking by
EFI_DEBUG_SUPPORT_PROTOCOL.REGISTEREXCEPTIONCALLBACK() . The implementation behavior when
an invalid parameter is passed is not deﬁned by this speciﬁcation.
18.3 EFI Debugport Protocol
This section deﬁnes the EFI Debugport protocol. This protocol is used by debug agent to communicate with the remote
debug host.
18.3.1 EFI Debugport Overview
Historically, remote debugging has typically been done using a standard UART serial port to connect the host and
target. This is obviously not possible in a legacy reduced system that does not have a UART. The Debugport protocol
solves this problem by providing an abstraction that can support many different types of debugport hardware. The
debug agent should use this abstraction to communicate with the host.
The interface is minimal with only reset, read, write, and poll abstractions. Since these functions are called in interrupt
context, none of them may call any EFI services or other protocol interfaces.
Debugport selection and conﬁguration is handled by setting defaults via an environment variable which contains a
full device path to the debug port. This environment variable is used during the debugport driver’s initialization to
conﬁgure the debugport correctly. The variable contains a full device path to the debugport, with the last node (prior
to the terminal node) being a debugport messaging node. See Debugport Device Path for details.
The driver must also produce an instance of the EFI Device Path protocol to indicate what hardware is be-
ing used for the debugport. This may be used by the OS to maintain the debugport across a call to
18.3.2 EFI_DEBUGPORT_PROTOCOL
Summary
This protocol provides the communication link between the debug agent and the remote host.
GUID
#define EFI_DEBUGPORT_PROTOCOL_GUID \
{0xEBA4E8D2,0x3858,0x41EC,\
{0xA2,0x81,0x26,0x47,0xBA,0x96,0x60,0xD0}}
18.3. EFI Debugport Protocol 736Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_DEBUGPORT_RESET Reset;
EFI_DEBUGPORT_WRITE Write;
EFI_DEBUGPORT_READ Read;
EFI_DEBUGPORT_POLL Poll;
} EFI_DEBUGPORT_PROTOCOL;
Reset Resets the debugport hardware.
Write Send a buffer of characters to the debugport device.
Read Receive a buffer of characters from the debugport device.
Poll Determine if there is any data available to be read from the debugport device.
The Debugport protocol is used for byte stream communication with a debugport device. The debugport can be a
standard UART Serial port, a USB-based character device, or potentially any character-based I/O device.
The attributes for all UART-style debugport device interfaces are deﬁned in the DEBUGPORT variable ( Debugport
Device Path ).
18.3.3 EFI_DEBUGPORT_PROTOCOL.Reset()
Summary
Resets the debugport.
Prototype
typedef
(EFIAPI *EFI_DEBUGPORT_RESET) (
IN EFI_DEBUGPORT_PROTOCOL *This
);
This A pointer to the EFI_DEBUGPORT_PROTOCOL instance. Type EFI_DEBUGPORT_PROTOCOL is deﬁned
inEFI_DEBUGPORT_PROTOCOL .
TheReset() function resets the debugport device.
It is the responsibility of the caller to insure all parameters are valid. There is no provision for parameter checking by
Reset() . The implementation behavior when an invalid parameter is passed is not deﬁned by this speciﬁcation.
EFI_SUCCESS The debugport device was reset and is in usable state.
EFI_DEVICE_ERROR The debugport device could not be reset and is unusable.
18.3. EFI Debugport Protocol 737Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
18.3.4 EFI_DEBUGPORT_PROTOCOL.Write()
Summary
Writes data to the debugport.
Prototype
typedef
(EFIAPI *EFI_DEBUGPORT_WRITE) (
IN EFI_DEBUGPORT_PROTOCOL *This,
);
Timeout The number of microseconds to wait before timing out a write operation.
BufferSize On input, the requested number of bytes of data to write. On output, the number of bytes of data actually
written.
Buffer A pointer to a buffer containing the data to write.
TheWrite() function writes the speciﬁed number of bytes to a debugport device. If a timeout error occurs while data
is being sent to the debugport, transmission of this buffer will terminate, and EFI_TIMEOUT will be returned. In all
cases the number of bytes actually written to the debugport device is returned in BufferSize .
Write() . The implementation behavior when an invalid parameter is passed is not deﬁned by this speciﬁcation.
18.3.5 EFI_DEBUGPORT_PROTOCOL.Read()
Summary
Reads data from the debugport.
Prototype
typedef
(EFIAPI *EFI_DEBUGPORT_READ) (
);
18.3. EFI Debugport Protocol 738Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Timeout The number of microseconds to wait before timing out a read operation.
BufferSize A pointer to an integer which, on input contains the requested number of bytes of data to read, and on
output contains the actual number of bytes of data read and returned in Buffer.
Buffer A pointer to a buffer into which the data read will be saved.
The Read() function reads a speciﬁed number of bytes from a debugport. If a timeout error or an overrun error is
detected while data is being read from the debugport, then no more characters will be read, and EFI_TIMEOUT will
be returned. In all cases the number of bytes actually read is returned in * BufferSize .
Read() . The implementation behavior when an invalid parameter is passed is not deﬁned by this speciﬁcation.
EFI_DEVICE_ERROR The debugport device reported an error.
18.3.6 EFI_DEBUGPORT_PROTOCOL.Poll()
Summary
Checks to see if any data is available to be read from the debugport device.
Prototype
typedef
(EFIAPI *EFI_DEBUGPORT_POLL) (
);
ThePoll() function checks if there is any data available to be read from the debugport device and returns the result.
No data is actually removed from the input stream. This function enables simpler debugger design since buffering of
reads is not necessary by the caller.
EFI_SUCCESS At least one byte of data is available to be read.
EFI_NOT_READY No data is available to be read.
EFI_DEVICE_ERROR The debugport device is not functioning correctly.
18.3. EFI Debugport Protocol 739Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
18.3.7 Debugport Device Path
The debugport driver must establish and maintain an instance of the EFI Device Path protocol for the debugport. A
graceful handoff of debugport ownership between the EFI Debugport driver and an OS debugport driver requires that
the OS debugport driver can determine the type, location, and conﬁguration of the debugport device.

The Debugport Device Path is a vendor-deﬁned messaging device path with no data, only a GUID. It is used at the
end of a conventional device path to tag the device for use as the debugport. For example, a typical UART debugport
would have the following fully qualiﬁed device path:
PciRoot(0)/Pci(0x1f,0)/ACPI(PNP0501,0)/UART(115200,N,8,1)/DebugPort()
The Vendor_GUID that deﬁnes the debugport device path is the same as the debugport protocol GUID, as deﬁned
below.
#define DEVICE_PATH_MESSAGING_DEBUGPORT \
EFI_DEBUGPORT_PROTOCOL_GUID
The Table below, Debugport Messaging Device Path , shows all ﬁelds of the debugport device path.
Table 18.1: Debugport Messaging Device Path
Sub Type 1 1 Sub Type 10 - Vendor.
Vendor_GUID 4 16 DEVICE_PATH_MESSA GING_DEBUGPORT.
18.3.8 EFI Debugport Variable
Even though there may be more than one hardware device that could function as a debugport in a system, only one
debugport may be active at a time. The DEBUGPORT variable is used to declare which hardware device will act as
the debugport, and what communication parameters it should assume.
Like all EFI variables, the DEBUGPORT variable has both a name and a GUID. The name is “DEBUGPORT.” The
GUID is the same as the EFI_DEBUGPORT_PROTOCOL_GUID :
#define EFI_DEBUGPORT_VARIABLE_NAME L"DEBUGPORT"
#define EFI_DEBUGPORT_VARIABLE_GUID EFI_DEBUGPORT_PROTOCOL_GUID
The data contained by the DEBUGPORT variable is a fully qualiﬁed debugport device path ( Debugport Device Path
).
The desired communication parameters for the debugport are declared in the DEBUGPORT variable. The debugport
driver must read this variable during initialization to determine how to conﬁgure the debug port.
To reduce the required complexity of the debugport driver, the debugport driver is not required to support all pos-
sible combinations of communication parameters. What combinations of parameters are possible is implementation
speciﬁc.
Additionally debugport drivers implemented for PNP0501 devices, that is debugport devices with a PNP0501 ACPI
node in the device path, must support the following defaults. These defaults must be used in the absence of a DEBUG-
PORT variable, or when the communication parameters speciﬁed in the DEBUGPORT variable are not supported by
the driver.
• Baud : 115200
18.3. EFI Debugport Protocol 740Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• 8 data bits
• No parity
• 1 stop bit
• No ﬂow control (See Appendix A for ﬂow control details)
In the absence of the DEBUGPORT variable, the selection of which port to use as the debug port is implementation
speciﬁc.
Future revisions of this speciﬁcation may deﬁne new defaults for other debugport types.
The debugport device path must be constructed to reﬂect the actual settings for the debugport. Any code needing
to know the state of the debug port must reference the device path rather than the DEBUGPORT variable, since the
debugport may have assumed a default setting in spite of the existence of the DEBUGPORT variable.
If it is not possible to conﬁgure the debug port using either the settings declared in the DEBUGPORT variable or the
default settings for the particular debugport type, the driver initialization must not install any protocol interfaces and
must exit with an error.
18.4 EFI Debug Support Table
This chapter deﬁnes the EFI Debug Support Table which is used by the debug agent or an external debugger to
determine loaded image information in a quiescent manner.
18.4.1 Overview
Every executable image loaded in EFI is represented by an EFI handle populated with an instance of the EFI Loaded
Image Protocol protocol. This handle is known as an “image handle.” The associated Loaded Image protocol provides
image information that is of interest to a source level debugger. Normal EFI executables can access this information
by using EFI services to locate all instances of the Loaded Image protocol.
A debugger has two problems with this scenario. First, if it is an external hardware debugger, the location of the
EFI system table is not known. Second, even if the location of the EFI system table is known, the services contained
therein are generally unavailable to a debugger either because it is an on-target debugger that is running in interrupt
context, or in the case of an external hardware debugger there is no debugger code running on the target at all.
Since a source level debugger must be capable of determining image information for all loaded images, an alternate
mechanism that does not use EFI services must be provided. Two features are added to the EFI system software to
enable this capability.
First, an alternate mechanism of locating the EFI system table is required. A check-summed structure containing the
physical address of the EFI system table is created and located on a 4M aligned memory address. A hardware debugger
can search memory for this structure to determine the location of the EFI system table.
Second, an EFI_CONFIGURATION_TABLE is published that leads to a database of pointers to all instances of the
Loaded Image protocol. Several layers of indirection are used to allow dynamically managing the data as images are
loaded and unloaded. Once the address of the EFI system table is known, it is possible to discover a complete and
accurate list of EFI images. (Note that the EFI core itself must be represented by an instance of the Loaded Image
protocol.)
Debug Support Table Indirection and Pointer Usage illustrates the table indirection and pointer usage.
18.4. EFI Debug Support Table 741Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 18.1: Debug Support Table Indirection and Pointer Usage
18.4.2 EFI System Table Location
The EFI system table can be located by an off-target hardware debugger by searching for the
EFI_SYSTEM_TABLE_POINTER structure. The EFI_SYSTEM_TABLE_POINTER structure is located on
a 4M boundary as close to the top of physical memory as feasible. It may be found searching for the
EFI_SYSTEM_TABLE_SIGNATURE on each 4M boundary starting at the top of memory and scanning down.
When the signature is found, the entire structure must veriﬁed using the Crc32 ﬁeld. The 32-bit CRC of the entire
structure is calculated assuming the Crc32 ﬁeld is zero. This value is then written to the Crc32 ﬁeld.
typedef struct _EFI_SYSTEM_TABLE_POINTER {
EFI_PHYSICAL_ADDRESS EfiSystemTableBase;
UINT32 Crc32;
} EFI_SYSTEM_TABLE_POINTER;
Signature A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE (see the EFI 1.0 speciﬁca-
tion).
EﬁSystemTableBase The physical address of the EFI system table.
Crc32 A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid.
18.4.3 EFI Image Info
TheEFI_DEBUG_IMAGE_INFO_TABLE is an array of pointers to EFI_DEBUG_IMAGE_INFO unions. Each mem-
ber of an EFI_DEBUG_IMAGE_INFO union is a pointer to a data structure representing a particular image type.
For each image that has been loaded, there is an appropriate image data structure with a pointer to it stored in the
EFI_DEBUG_IMAGE_INFO_TABLE . Data structures for normal images and SMM images are deﬁned. All other
image types are reserved for future use.
The process of locating the EFI_DEBUG_IMAGE_INFO_TABLE begins with an EFI conﬁguration table.
18.4. EFI Debug Support Table 742Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// EFI_DEBUG_IMAGE_INFO_TABLE configuration table
// GUID declaration - {49152E77-1ADA-4764-B7A2-7AFEFED95E8B}
//
#define EFI_DEBUG_IMAGE_INFO_TABLE_GUID \
{0x49152E77,0x1ADA,0x4764,\
{0xB7,0xA2,0x7A,0xFE,0xFE,0xD9,0x5E,0x8B }}
The conﬁguration table leads to an EFI_DEBUG_IMAGE_INFO_TABLE_HEADER structure that contains a
pointer to the EFI_DEBUG_IMAGE_INFO_TABLE and some status bits that are used to control access to the
EFI_DEBUG_IMAGE_INFO_TABLE when it is being updated.
//
// UpdateStatus bits
//
#define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01
#define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02
volatile UINT32 UpdateStatus;
UINT32 TableSize;
EFI_DEBUG_IMAGE_INFO *EfiDebugImageInfoTable;
} EFI_DEBUG_IMAGE_INFO_TABLE_HEADER;
UpdateStatus UpdateStatus is used by the system to indicate the state of the debug image info table.
The EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS bit must be set when the table is being modiﬁed.
Software consuming the table must qualify the access to the table with this bit.
The EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED bit is always set by software that modiﬁes the table.
It may be cleared by software that consumes the table once the entire table has been read. It is essentially a

//
//
sticky version of the EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS bit and is intended to provide
an efﬁcient mechanism to minimize the number of times the table must be scanned by the consumer.
TableSize The number of EFI_DEBUG_IMAGE_INFO elements in the array pointed to by EﬁDebugImageInfoTable .
EﬁDebugImageInfoTable A pointer to the ﬁrst element of an array of EFI_DEBUG_IMAGE_INFO structures.
#define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01
UINT32 *ImageInfoType;
EFI_DEBUG_IMAGE_INFO_NORMAL *NormalImage;
} EFI_DEBUG_IMAGE_INFO;
UINT32 ImageInfoType;
EFI_LOADED_IMAGE_PROTOCOL *LoadedImageProtocolInstance;
} EFI_DEBUG_IMAGE_INFO_NORMAL;
ImageInfoType Indicates the type of image info structure. For PE32 EFI images, this is set to
EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL.
LoadedImageProtocolInstance A pointer to an instance of the loaded image protocol for the associated image.
ImageHandle Indicates the image handle of the associated image.
18.4. EFI Debug Support Table 743CHAPTER
NINETEEN
PROTOCOLS — COMPRESSION ALGORITHM SPECIFICATION
In EFI ﬁrmware storage, binary codes/data are often compressed to save storage space. These compressed codes/data
are extracted into memory for execution at boot time. This demands an efﬁcient lossless compression/decompression
algorithm. The compressor must produce small compressed images, and the decompressor must operate fast enough
to avoid delays at boot time.
This chapter describes in detail the UEFI compression/decompression algorithm, as well as the EFI Decompress
Protocol. The EFI Decompress Protocol provides a standard decompression interface for use at boot time.
19.1 Algorithm Overview
In this chapter, the term “character” denotes a single byte and the term “string” denotes a series of concatenated
characters.
The compression/decompression algorithm used in EFI ﬁrmware storage is a combination of the LZ77 algorithm and
Huffman Coding. The LZ77 algorithm replaces a repeated string with a pointer to the previous occurrence of the
string. Huffman Coding encodes symbols in a way that the more frequently a symbol appears in a text, the shorter the
code that is assigned to it.
The compression process contains two steps:
• The ﬁrst step is to ﬁnd repeated strings (using LZ77 algorithm) and produce intermediate data.
Beginning with the ﬁrst character, the compressor scans the source data and determines if the characters starting
at the current position can form a string previously appearing in the text. If a long enough matching string is
found, the compressor will output a pointer to the string. If the pointer occupies more space than the string itself,
the compressor will output the original character at the current position in the source data. Then the compressor
advances to the next position and repeats the process. To speed up the compression process, the compressor
dynamically maintains a String Info Log to record the positions and lengths of strings encountered, so that
string comparisons are performed quickly by looking up the String Info Log.
Because a compressor cannot have unlimited resources, as the compression continues the compressor removes
“old” string information. This prevents the String Info Log from becoming too large. As a result, the algorithm
can only look up repeated strings within the range of a ﬁxed-sized “sliding window” behind the current position.
In this way, a stream of intermediate data is produced which contains two types of symbols: the Original
Characters (to be preserved in the decompressed data), and the Pointers (representing a previous string). A
Pointer consists of two elements: the String Position and the String Length , representing the location and the
length of the target string, respectively.
• To improve the compression ratio further, Huffman Coding is utilized as the second step.
The intermediate data (consisting of original characters and pointers) is divided into Blocks so that the com-
pressor can perform Huffman Coding on a Block immediately after it is generated; eliminating the need for a
second pass from the beginning after the intermediate data has been generated. Also, since symbol frequency
744Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
distribution may differ in different parts of the intermediate data, Huffman Coding can be optimized for each
speciﬁc Block. The compressor determines Block Size for each Block according to the speciﬁcations deﬁned in
Data Format .
In each Block, two symbol sets are deﬁned for Huffman Coding. The Char&Len Set consists of the Original
Characters plus the String Lengths and the Position Set consists of String Positions (Note that the two elements
of a Pointer belong to separate symbol sets). The Huffman Coding schemes applied on these two symbol sets
are independent.
The algorithm uses “canonical” Huffman Coding so a Huffman tree can be represented as an array of code
lengths in the order of the symbols in the symbol set. This code length array represents the Huffman Coding
scheme for the symbol set. Both the Char&Len Set code length array and the Position Set code length array
appear in the Block Header.
Huffman coding is used on the code length array of the Char&Len Set to deﬁne a third symbol set. The Extra
Set is deﬁned based on the code length values in the Char&Len Set code length array. The code length array
for the Huffman Coding of Extra Set also appears in the Block Header together with the other two code length
arrays. For exact format of the Block Header, Block Header .
The decompression process is straightforward given that the compression process is known. The decompressor scans
the compressed data and decodes the symbols one by one, according to the Huffman code mapping tables generated
from code length arrays. Along the process, if it encounters an original character, it outputs it; if it encounters a pointer,
it looks it up in the already decompressed data and outputs the associated string.
19.2 Data Format
This section describes in detail the format of the compressed data produced by the compressor. The compressed data
serves as input to the decompressor and can be fully extracted to the original source data.
19.2.1 Bit Order
In computer data representation, a byte is the minimum unit and there is no differentiation in the order of bits within a
byte. However, the compressed data is a sequence of bits rather than a sequence of bytes and as a result the order of
bits in a byte needs to be deﬁned. In a compressed data stream, the higher bits are deﬁned to precede the lower bits in
a byte. The Figure, below, Bit Sequence of Compressed Data illustrates a compressed data sequence written as bytes
from left to right. For each byte, the bits are written in an order with bit 7 (the highest bit) at the left and bit 0 (the
lowest bit) at the right. Concatenating the bytes from left to right forms a bit sequence.
Fig. 19.1: Bit Sequence of Compressed Data
The bits of the compressed data are actually formed by a sequence of data units. These data units have variable bit
lengths. The bits of each data unit are arranged so that the higher bit of the data unit precedes the lower bit of the data
unit.
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19.2.2 Overall Structure
The compressed data begins with two 32-bit numerical ﬁelds: the compressed size and the original size. The com-
pressed data following these two ﬁelds is composed of one or more Blocks. Each Block is a unit for Huffman Coding
with a coding scheme independent of the other Blocks. Each Block is composed of a Block Header containing the
Huffman code trees for this Block and a Block Body with the data encoded using the coding scheme deﬁned by the
Huffman trees. The compressed data is terminated by an additional byte of zero.
The overall structure of the compressed data is shown in Compressed Data Structure .
Fig. 19.2: Compressed Data Structure
Note the following:
• Blocks are of variable lengths.
• Block lengths are counted by bits and not necessarily divisible by 8. Blocks are tightly packed (there are no
padding bits between blocks). Neither the starting position nor ending position of a Block is necessarily at a
byte boundary. However, if the last Block is not terminated at a byte boundary, there should be some bits of 0 to
ﬁll up the remaining bits of the last byte of the block, before the terminator byte of 0.
• Compressed Size =
Size in bytes of (Block 0 + Block 1 +. . . + Block N + Filling Bits (if any) + Terminator).
• Original Size is the size in bytes of original data.
• Both Compressed Size and Original Size are “little endian” (starting from the least signiﬁcant byte).
19.2.3 Block Structure
A Block is composed of a Block Header and a Block Body, as shown in the ﬁgure below. These two parts are
packed tightly (there are no padding bits between them). The lengths in bits of Block Header and Block Body are not
necessarily divisible by eight.
Fig. 19.3: Block Structure

19.2. Data Format 746Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
19.2.3.1 Block Header
The Block Header contains the Huffman encoding information for this block. Since “canonical” Huffman Coding is
being used, a Huffman tree is represented as an array of code lengths in increasing order of the symbols in the symbol
set. Code lengths are limited to be less than or equal to 16 bits. This requires some extra handling of Huffman codes
in the compressor, which is described in Block Structure .
There are three code length arrays for three different symbol sets in the Block Header: one for the Extra Set, one for
the Char&Len Set, and one for the Position Set.
The Block Header is composed of the tightly packed (no padding bits) ﬁelds described in the Table, below, Block
Header Fields .
Table 19.1: Block Header Fields
Field Name Length (bits) Description
Block Size 16
The size of this Block. Block Size
is deﬁned as the number of original
characters plus the number of
pointers that appear in the Block
Body:
Block Size = Number of Original
Characters in the Block Body
+ Number of Pointers in the Block
Body.
Extra Set Code Length Array Size 5
The number of code lengths in the
Extra Set Code Length Array.
The Extra Set Code Length Array
contains code lengths of the Extra
Set in increasing order of the
symbols, and if all symbols greater
than a certain symbol have zero
code length, the Extra Set Code
Length Array terminates at the last
nonzero code length symbol.
Since there are 19 symbols in the
Extra Set (see the description of the
Char&Len Set Code Length Array),
the maximum Extra Set Code
Length Array Size is 19.
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Table 19.1 – continued from previous page
Extra Set Code Length Array Variable
If Extra Set Code Length Array
Size is 0, then this ﬁeld is a 5-bit
value that represents the only
Huffman code used.
Size is not 0, then this ﬁeld is an
encoded form of a concatenation of
code lengths in increasing order of
the symbols.
The concatenation of Code lengths
are encoded as follows:
If a code length is less than 7, then
it is encoded as a 3-bit value;
If a code length is equal to or
greater than 7, then it is encoded as
a series of “1”s followed by a
terminating “0.” The number of
“1”s = Code length - 4. For
example, code length “ten” is
encoded as “1111110”; code length
“seven” is encoded as “1110.”
After the third length of the code
length concatenation, a 2-bit value
is used to indicate the number of
consecutive zero lengths
immediately after the third length.
(Note this 2-bit value only appears
once after the third length, and does
NOT appear multiple times after
every 3rd length.)
This 2-bit value ranges from 0 to 3.
For example, if the 2-bit value is
“00,” then it means there are no
zero lengths at the point, and
following encoding starts from the
fourth code length;
if the 2-bit value is “10” then it
means the fourth and ﬁfth length
are zero and following encoding
starts from the sixth code length.
19.2. Data Format 748Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Position Set Code Length Array
Size4
Position Set Code Length Array.
The Position Set Code Length
Array contains code lengths of
Position Set in increasing order of
the symbols in the Position Set, and
if all symbols greater than a certain
symbol have zero code length, the
terminates at the last nonzero code
length symbol.
Since there are 14 symbols in the
Position Set (see 3.3.2),
the maximum Position Set Code
Length Array Size is 14.
19.2. Data Format 749Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Char&Len Set Code Length Array Variable
If Char&Len Set Code Length
Array Size is 0, then this ﬁeld is a
9-bit value that represents the only
Array Size is not 0, then this ﬁeld is
an encoded form of a concatenation
of code lengths in increasing order
of the symbols. The concatenation
of Code lengths are two-step
encoded:
Step 1:
If a code length is not zero, then it
is encoded as “code length + 2”;
If a code length is zero, then the
number of consecutive zero lengths
starting from this code length is
counted —
• If the count is equal to or less than
2, then the code “0” is used for each
zero length;
• if the count is greater than 2 and
less than 19, then the code “1”
followed by a 4-bit value of “count
- 3” is used for these consecutive
zero lengths;
• if the count is equal to 19, then it
is treated as “1 + 18,” and a code
“0” and a code “1” followed by a
4-bit value of “15” are used for
these consecutive zero lengths;
• if the count is greater than 19,
then the code “2” followed by a
9-bit value of “count - 20” is used
for these consecutive zero lengths.
Step 2:
The second step encoding is a
Huffman encoding of the codes
produced by ﬁrst step.
(While encoding codes “1” and “2,”
their appended values are not
encoded and preserved in the
resulting text).
The code lengths of generated
Huffman tree are just the contents
of the Extra Set Code Length Array.
continues on next page19.2. Data Format 750Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Size4
Position Set (see 3.3.2), the
maximum Position Set Code
Position Set Code Length Array Variable
If Position Set Code Length Array
it is encoded as a normal 3-bit
value;
example, code length “10” is
“7” is encoded as “1110.”
19.2. Data Format 751Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
19.2.3.2 Block Body
The Block Body is simply a mixture of Original Characters and Pointers, while each Pointer has two elements: String
Length preceding String Position. All these data units are tightly packed together.
Fig. 19.4: Block Body
The Original Characters, String Lengths and String Positions are all Huffman coded using the Huffman trees presented
in the Block Header, with some additional variations. The exact format is described below:
An Original Character is a byte in the source data. A String Length is a value that is greater than 3 and less than 257
(this range should be ensured by the compressor). By calculating “(String Length - 3) | 0x100,” a value set is obtained
that ranges from 256 to 509. By combining this value set with the value set of Original Characters (0 ~ 255), the
Char&Len Set (ranging from 0 to 509) is generated for Huffman Coding.
A String Position is a value that indicates the distance between the current position and the target string. The String
Position value is deﬁned as “Current Position - Starting Position of the target string - 1.” The String Position value
ranges from 0 to 8190 (so 8192 is the “sliding window” size, and this range should be ensured by the compressor).
The lengths of the String Position values (in binary form) form a value set ranging from 0 to 13 (it is assumed that
value 0 has length of 0). This value set is the Position Set for Huffman Coding. The full representation of a String
Position value is composed of two consecutive parts: one is the Huffman code for the value length; the other is the
actual String Position value of “length - 1” bits (excluding the highest bit since the highest bit is always “1”). For
example, String Position value 18 is represented as: Huffman code for “5” followed by “0010.” If the value length is 0
or 1, then no value is appended to the Huffman code. This kind of representation favors small String Position values,
which is a hint for compressor design.
19.3 Compressor Design
The compressor takes the source data as input and produces a compressed image. This section describes the design
used in one possible implementation of a compressor that follows the UEFI Compression Algorithm. The source code

that illustrates an implementation of this speciﬁc design is listed in Appendix H.
19.3.1 Overall Process
The compressor scans the source data from the beginning, character by character. As the scanning proceeds, the
compressor generates Original Characters or Pointers and outputs the compressed data packed in a series of Blocks
representing individual Huffman coding units.
The compressor maintains a String Info Log containing data that facilitates string comparison. Old data items are
deleted and new data items are inserted regularly.
The compressor does not output a Pointer immediately after it sees a matching string for the current position. Instead,
it delays its decision until it gets the matching string for the next position. The compressor has two criteria at hand:
one is that the former match length should be no shorter than three characters; the other is that the former match length
should be no shorter than the latter match length.
Only when these two criteria are met does the compressor output a Pointer to the former matching string.
The overall process of compression can be described by following pseudo code:
19.3. Compressor Design 752Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Set the Current Position at the beginning of the source data;
Delete the outdated string info from the String Info Log;
Search the String Info Log formatching string;
Add the string info of the current position into the String Info Log;
WHILEnotend of source data DO
Remember the last match;
Advance the Current Position by 1;
Delete the outdated String Info from the String Info Log;
Add the string info of the Current Position into the String Info Log;
IF the last match isshorter than 3 characters orthis match islonger than
the last match THEN
Call Output() *to output the character at the previous position asan
Original Character;
ELSE
Call Output() *to output a Pointer to the last matching string;
WHILE (--last match length) > 0 DO
Delete the outdated piece of string info from the String Info Log;
ENDWHILE
ENDIF
ENDWHILE
The Output() is the function that is responsible for generating Huffman codes and Blocks. It accepts an Original
Character or a Pointer as input and maintains a Block Buffer to temporarily store data units that are to be Huffman
coded. The following pseudo code describes the function:
FUNCTION NAME: Output
INPUT: an Original Character ora Pointer
Put the Original Character orthe Pointer into the Block Buffer;
Advance the Block Buffer position pointer by 1;
IF the Block Buffer isfull THEN
Encode the Char&Len Set inthe Block buffer;
Encode the Position Set inthe Block buffer;
Encode the Extra Set;
Output the Block Header containing the code length arrays;
Output the Block Body containing the Huffman encoded Original Characters and
Pointers;
Reset the Block Buffer position pointer to point to the beginning of the Block
˓→buffer;
ENDIF
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19.3.2 String Info Log
The provision of the String Info Log is to speed up the process of ﬁnding matching strings. The design of this has
signiﬁcant impact on the overall performance of the compressor. This section describes in detail how String Info Log
is implemented and the typical operations on it.
19.3.2.1 Data Structures
The String Info Log is implemented as a set of search trees. These search trees are dynamically updated as the
compression proceeds through the source data. The structure of a typical search tree is depicted in the Figure, below,
String Info Log Search Tree .
Fig. 19.5: String Info Log Search Tree
There are three types of nodes in a search tree: the root node, internal nodes, and leaves. The root node has a
“character” attribute, which represents the starting character of a string. Each edge also has a “character” attribute,
which represents the next character in the string. Each internal node has a “level” attribute, which indicates the
character on any edge that leads to its child nodes is the “level + 1”th character in the string. Each internal node or leaf
has a “position” attribute that indicates the string’s starting position in the source data.
To speed up the tree searching, a hash function is used. Given the parent node and the edge-character, the hash function
will quickly ﬁnd the expected child node.
19.3.2.2 Searching the Tree
Traversing the search tree is performed as follows:
The following example uses the search tree shown in the Figure, above, String Info Log Search Tree . Assume that the
current position in the source data contains the string “camxrsxpj. . . .”
1. The starting character “c” is used to ﬁnd the root of the tree. The next character “a” is used to follow the edge
from node 1 to node 2. The “position” of node 2 is 500, so a string starting with “ca” can be found at position
500. The string at the current position is compared with the string starting at position 500.
2. Node 2 is at Level 3; so at most three characters are compared. Assume that the three-character comparison
passes.
19.3. Compressor Design 754Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3. The fourth character “x” is used to follow the edge from Node 2 to Node 5. The position value of node 5 is 400,
which means there is a string located in position 400 that starts with “cam” and the character at position 403 is
an “x.”
4. Node 5 is at Level 8, so the ﬁfth to eighth characters of the source data are compared with the string starting at
position 404. Assume the strings match.
5. At this point, the ninth character “p” has been reached. It is used to follow the edge from Node 5 to Node 7.
6. This process continues until a mismatch occurs, or the length of the matching strings exceeds the predeﬁned
MAX_MATCH_LENGTH. The most recent matching string (which is also the longest) is the desired matching
string.
19.3.2.3 Adding String Info
String info needs to be added to the String Info Log for each position in the source data. Each time a search for a
matching string is performed, the new string info is inserted for the current position. There are several cases that can
be discussed:
1. No root is found for the ﬁrst character. A new tree is created with the root node labeled with the starting character
and a child leaf node with its edge to the root node labeled with the second character in the string. The “position”
value of the child node is set to the current position.
2. One root node matches the ﬁrst character, but the second character does not match any edge extending from the
root node. A new child leaf node is created with its edge labeled with the second character. The “position” value
of the new leaf child node is set to the current position.
3. A string comparison succeeds with an internal node, but a matching edge for the next character does not exist.
This is similar to (2) above. A new child leaf node is created with its edge labeled with the character that does
not exist. The “position” value of the new leaf child node is set to the current position.
4. A string comparison exceeds MAX_MATCH_LENGTH. Note: This only happens with leaf nodes. For this
case, the “position” value in the leaf node is updated with the current position.
5. If a string comparison with an internal node or leaf node fails (mismatch occurs before the “Level + 1”th
character is reached or MAX_MATCH_LENGTH is exceeded), then a “split” operation is performed as follows:
Suppose a comparison is being performed with a level 9 Node, at position 350, and the current position is 1005.
If the sixth character at position 350 is an “x” and the sixth character at position 1005 is a “y,” then a mismatch
will occur. In this case, a new internal node and a new child node are inserted into the tree, as depicted in Node
Split .
19.3.2.4 Deleting String Info
The String Info Log will grow as more and more string information is logged. The size of the String Info Log must
be limited, so outdated information must be removed on a regular basis. A sliding window is maintained behind the
current position, and the searches are always limited within the range of the sliding window. Each time the current
position is advanced, outdated string information that falls outside the sliding window should be removed from the
tree. The search for outdated string information is simpliﬁed by always updating the nodes’ “position” attribute when
searching for matching strings.
19.3. Compressor Design 755Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 19.6: Node Split
The b) portion of Node Split has two new inserted nodes, which reﬂects the new string information that was found at the current
position. The process splits the old node into two child nodes, and that is why this operation is called a “split.”

19.3. Compressor Design 756Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
19.3.3 Huffman Code Generation
Another major component of the compressor design is generation of the Huffman Code.
Huffman Coding is applied to the Char&Len Set, the Position Set, and the Extra Set. The Huffman Coding used here
has the following features:
• The Huffman tree is represented as an array of code lengths (“canonical” Huffman Coding);
• The maximum code length is limited to 16 bits.
The Huffman code generation process can be divided into three steps. These are the generation of Huffman tree, the
adjustment of code lengths, and the code generation.
19.3.3.1 Huffman Tree Generation
This process generates a typical Huffman tree. First, the frequency of each symbol is counted, and a list of nodes is
generated with each node containing a symbol and the symbol’s frequency. The two nodes with the lowest frequency
values are merged into a single node. This new node becomes the parent node of the two nodes that are merged. The
frequency value of this new parent node is the sum of the two child nodes’ frequency values. The node list is updated
to include the new parent node but exclude the two child nodes that are merged. This process is repeated until there is
a single node remaining that is the root of the generated tree.
19.3.3.2 Code Length Adjustment
The leaf nodes of the tree generated by the previous step represent all the symbols that were generated. Traditionally
the code for each symbol is found by traversing the tree from the root node to the leaf node. Going down a left edge
generates a “0,” and going down a right edge generates a “1.” However, a different approach is used here. The number
of codes of each code length is counted. This generates a 16-element LengthCount array, with LengthCount[i] =
Number Of Codes whose Code Length is i. Since a code length may be longer than 16 bits, the sixteenth entry of the
LengthCount array is set to the Number Of Codes whose Code Length is greater than or equal to 16.
The LengthCount array goes through further adjustment described by following code:
INT32 i, k;
UINT32 cum;
cum = 0;
for(i = 16; i > 0; i--) {
cum += LengthCount[i] << (16 - i);
}
while(cum != (1U << 16)) {
LengthCount[16]--;
for(i = 15; i > 0; i--) {
if(LengthCount[i] != 0) {
LengthCount[i]--;
LengthCount[i+1] += 2;
break;
}
}
cum--;
}
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19.3.3.3 Code Generation
In the previous step, the count of each length was obtained. Now, each symbol is going to be assigned a code. First, the
length of the code for each symbol is determined. Naturally, the code lengths are assigned in such a way that shorter
codes are assigned to more frequently appearing symbols. A CodeLength array is generated with CodeLength[i] =
the code length of symbol i. Given this array, a code is assigned to each symbol using the algorithm described by the
pseudo code below (the resulting codes are stored in array Code such that Code[i] = the code assigned to symbol i):
INT32 i;
UINT16 Start[18];
Start[1] = 0;
for(i = 1; i <= 16; i++) {
Start[i + 1] = (UINT16)((Start[i] + LengthCount[i]) << 1);
}
for(i = 0; i < NumberOfSymbols; i++) {
Code[i] = Start[CodeLength[i]]++;
}
The code length adjustment process ensures that no code longer than the designated length will be generated. As long
as the decompressor has the CodeLength array at hand, it can regenerate the codes.
19.4 Decompressor Design
The decompressor takes the compressed data as input and produces the original source data. The main tasks for the
decompressor are decoding Huffman codes and restoring Pointers to the strings to which they point.
The following pseudo code describes the algorithm used in the design of a decompressor. The source code that
illustrates an implementation of this design is listed in Appendix I.
WHILEnotend of data DO
IF at block boundary THEN
Readinthe Extra Set Code Length Array;
Generate the Huffman code mapping table forthe Extra Set;
Readin anddecode the Char&Len Set Code Length Array;
Generate the Huffman code mapping table forthe Char&Len Set;
Readinthe Position Set Code Length Array;
Generate the Huffman code mapping table forthe Position Set;
ENDIF
Get next code;
Look the code up inthe Char&Len Set code mapping table.
Store the result asC;
IF C < 256 (it represents an Original Character) THEN
Output this character;
ELSE (it represents a String Length)
Transform C to be the actual String Length value;
Get next code andlook it up inthe Position Set code mapping table, and
withsome additional transformation, store the result asP;
Output C characters starting from the position "Current Position - P";
ENDIF
ENDWHILE
19.4. Decompressor Design 758Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
19.5 Decompress Protocol
This section provides a detailed description of the EFI_DECOMPRESS_PROTOCOL .
19.5.1 EFI_DECOMPRESS_PROTOCOL
Summary
Provides a decompression service.
GUID
#define EFI_DECOMPRESS_PROTOCOL_GUID \
{0xd8117cfe,0x94a6,0x11d4,\
{0x9a,0x3a,0x00,0x90,0x27,0x3f,0xc1,0x4d}}
typedef struct _EFI_DECOMPRESS_PROTOCOL {
EFI_DECOMPRESS_GET_INFO GetInfo;
EFI_DECOMPRESS_DECOMPRESS Decompress;
} EFI_DECOMPRESS_PROTOCOL;
GetInfo Given the compressed source buffer, this function retrieves the size of the uncompressed des-
tination buffer and the size of the scratch buffer required to perform the decompression. It is
the caller’s responsibility to allocate the destination buffer and the scratch buffer prior to calling
EFI_DECOMPRESS_PROTOCOL.Decompress() . See the EFI_DECOMPRESS_PROTOCOL.GetInfo() func-
Decompress Decompresses a compressed source buffer into an uncompressed destination buffer. It is the caller’s re-
sponsibility to allocate the destination buffer and a scratch buffer prior to making this call. See the Decompress()
TheEFI_DECOMPRESS_PROTOCOL provides a decompression service that allows a compressed source buffer in
memory to be decompressed into a destination buffer in memory. It also requires a temporary scratch buffer to perform
the decompression. The GetInfo() function retrieves the size of the destination buffer and the size of the scratch buffer
that the caller is required to allocate. The Decompress() function performs the decompression. The scratch buffer can
be freed after the decompression is complete.
19.5.2 EFI_DECOMPRESS_PROTOCOL.GetInfo()
Summary
Given a compressed source buffer, this function retrieves the size of the uncompressed buffer and the size of the scratch
buffer required to decompress the compressed source buffer.
Prototype
typedef
(EFIAPI *EFI_DECOMPRESS_GET_INFO) (
IN EFI_DECOMPRESS_PROTOCOL *This,
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IN UINT32 SourceSize,
OUT UINT32 *DestinationSize,
OUT UINT32 *ScratchSize
);
This A pointer to the EFI_DECOMPRESS_PROTOCOL instance. Type EFI_DECOMPRESS_PROTOCOL is de-
ﬁned in EFI_DECOMPRESS_PROTOCOL .
Source The source buffer containing the compressed data.
SourceSize The size, in bytes, of the source buffer.
DestinationSize A pointer to the size, in bytes, of the uncompressed buffer that will be generated when the com-
pressed buffer speciﬁed by Source andSourceSiz e is decompressed.
ScratchSize A pointer to the size, in bytes, of the scratch buffer that is required to decompress the compressed buffer
speciﬁed by Source andSourceSize .
The GetInfo() function retrieves the size of the uncompressed buffer and the temporary scratch buffer required to
decompress the buffer speciﬁed by Source and SourceSize . If the size of the uncompressed buffer or the size
of the scratch buffer cannot be determined from the compressed data speciﬁed by Source andSourceData , then
EFI_INVALID_PARAMETER is returned. Otherwise, the size of the uncompressed buffer is returned in Destina-
tionSize , the size of the scratch buffer is returned in ScratchSize , and EFI_SUCCESS is returned.
The GetInfo() function does not have scratch buffer available to perform a thorough checking of the validity of the
source data. It just retrieves the “Original Size” ﬁeld from the beginning bytes of the source data and output it as
DestinationSize . And ScratchSize is speciﬁc to the decompression implementation.
EFI_SUCCESS The size of the uncompressed data was returned in DestinationSize and the
size of the scratch buffer was returned in ScratchSize.
EFI_INV ALID_PARAMETER The size of the uncompressed data or the size of the scratch buffer cannot be
determined from the compressed data speciﬁed by Source andSourceSize .
19.5.3 EFI_DECOMPRESS_PROTOCOL.Decompress()
Summary
Decompresses a compressed source buffer.
Prototype
typedef

Summary
Prototype
typedef
(EFIAPI *EFI_DECOMPRESS_DECOMPRESS) (
IN OUT VOID *Destination,
IN UINT32 DestinationSize,
IN OUT VOID *Scratch,
19.5. Decompress Protocol 760Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN UINT32 ScratchSize
);
SourceSize The size of source data.
Destination On output, the destination buffer that contains the uncompressed data.
DestinationSize The size of the destination buffer. The size of the destination buffer needed is obtained from
EFI_DECOMPRESS_PROTOCOL.GetInfo() .
Scratch A temporary scratch buffer that is used to perform the decompression.
ScratchSize The size of scratch buffer. The size of the scratch buffer needed is obtained from GetInfo() .
TheDecompress() function extracts decompressed data to its original form.
This protocol is designed so that the decompression algorithm can be implemented without using any memory
services. As a result, the Decompress() function is not allowed to call EFI_BOOT_SERVICES.AllocatePool() or
EFI_BOOT_SERVICES.AllocatePages() in its implementation. It is the caller’s responsibility to allocate and free the
Destination and Scratch buffers.
If the compressed source data speciﬁed by Source andSourceSize is successfully decompressed into Destination ,
then EFI_SUCCESS is returned. If the compressed source data speciﬁed by Source andSourceSize is not in a valid
compressed data format, then EFI_INVALID_PARAMETER is returned.
EFI_SUCCESS Decompression completed successfully, and the uncompressed buffer is re-
turned in Destination .
EFI_INV ALID_PARAMETER The source buffer speciﬁed by Source andSourceSize is corrupted (not in a
valid compressed format).
19.5. Decompress Protocol 761CHAPTER
TWENTY
PROTOCOLS — ACPI PROTOCOLS
20.1 EFI_ACPI_TABLE_PROTOCOL
Summary
This protocol may be used to install or remove an ACPI table from a platform.
GUID
#define EFI_ACPI_TABLE_PROTOCOL_GUID \
{0xffe06bdd, 0x6107, 0x46a6,\
{0x7b, 0xb2, 0x5a, 0x9c, 0x7e, 0xc5, 0x27, 0x5c}}
typedef struct _EFI_ACPI_TABLE_PROTOCOL {
EFI_ACPI_TABLE_INSTALL_ACPI_TABLE InstallAcpiTable;
EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE UninstallAcpiTable;
} EFI_ACPI_TABLE_PROTOCOL;
InstallAcpiTable Installs an ACPI table into the system.
UninstallAcpiTable Removes a previously installed ACPI table from the system.
TheEFI_ACPI_TABLE_PROTOCOL provides the ability for a component to install and uninstall ACPI tables from a
platform.
20.2 EFI_ACPI_TABLE_PROTOCOL.InstallAcpiTable()
Summary
Installs an ACPI table into the RSDT/XSDT.
Prototype
typedef
(EFIAPI *EFI_ACPI_TABLE_INSTALL_ACPI_TABLE) (
IN EFI_ACPI_TABLE_PROTOCOL *This,
IN VOID *AcpiTableBuffer,
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IN UINTN AcpiTableBufferSize,
OUT UINTN *TableKey,
);
This A pointer to a EFI_ACPI_TABLE_PROTOCOL .
AcpiTableBuffer A pointer to a buffer containing the ACPI table to be installed.
AcpiTableBufferSize Speciﬁes the size, in bytes, of the AcpiTableBuffer buffer.
TableKey Returns a key to refer to the ACPI table.
The InstallAcpiTable() function allows a caller to install an ACPI table. The ACPI table may either by a System
Description Table or the FACS. For all tables except for the DSDT and FACS, a copy of the table will be linked by the
RSDT/XSDT. For the FACS and DSDT, the pointer to a copy of the table will be updated in the FADT, if present.
To prevent namespace collision, ACPI tables may be created using UEFI ACPI table format, UEFI ACPI Data Table .
If this protocol is used to install a table with a signature already present in the system, the new table will not replace
the existing table. It is a platform implementation decision to add a new table with a signature matching an existing
table or disallow duplicate table signatures and return EFI_ACCESS_DENIED .
On successful output, TableKey is initialized with a unique key. Its value may be used in a subsequent call to Unin-
stallAcpiTable to remove an ACPI table.
On successful output, the EFI_ACPI_TABLE_PROTOCOL will ensure that the checksum ﬁeld is correct for both the
RSDT/XSDT table and the copy of the table being installed that is linked by the RSDT/XSDT.
On successful completion, this function reinstalls the relevant EFI_CONFIGURATION_TABLE pointer to the RSDT.
EFI_SUCCESS The table was successfully inserted
EFI_INV ALID_PARAMETER TheAcpiTableBuffer isNULL , the TableKey isNULL ;theAcpiTableBuffer-
Size, and the size ﬁeld embedded in the ACPI table pointed to by AcpiTable-
Buffer are not in sync.
EFI_OUT_OF_RESOURCES Insufﬁcient resources exist to complete the request.
EFI_ACCESS_DENIED The table signature matches a table already present in the system and plat-
form policy does not allow duplicate tables of this type.
20.3 EFI_ACPI_TABLE_PROTOCOL.UninstallAcpiTable()
Summary
Removes an ACPI table from the RSDT/XSDT.
Prototype
typedef
(EFIAPI *EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE) (
IN UINTN TableKey,
);
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TableKey Speciﬁes the table to uninstall. The key was returned from InstallAcpiTable() .
TheUninstallAcpiTable() function allows a caller to remove an ACPI table. The routine will remove its reference from
the RSDT/XSDT. A table is referenced by the TableKey parameter returned from a prior call to InstallAcpiTable() .
EFI_NOT_FOUND TableKey does not refer to a valid key for a table entry.
20.3. EFI_ACPI_TABLE_PROTOCOL.UninstallAcpiTable() 764CHAPTER
TWENTYONE
PROTOCOLS — STRING SERVICES
21.1 Unicode Collation Protocol
This section deﬁnes the Unicode Collation protocol. This protocol is used to allow code running in the boot services
environment to perform lexical comparison functions on Unicode strings for given languages.
21.1.1 EFI_UNICODE_COLLATION_PROTOCOL
Summary
Is used to perform case-insensitive comparisons of strings.
GUID
#define EFI_UNICODE_COLLATION_PROTOCOL2_GUID \
{0xa4c751fc, 0x23ae, 0x4c3e, \
{0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49}}
EFI_UNICODE_COLLATION_STRICOLL StriColl;
EFI_UNICODE_COLLATION_METAIMATCH MetaiMatch;
EFI_UNICODE_COLLATION_STRLWR StrLwr;
EFI_UNICODE_COLLATION_STRUPR StrUpr;
EFI_UNICODE_COLLATION_FATTOSTR FatToStr;
EFI_UNICODE_COLLATION_STRTOFAT StrToFat;
} EFI_UNICODE_COLLATION_PROTOCOL;
StriColl Performs a case-insensitive comparison of two Null-terminated strings. See the
EFI_UNICODE_COLLATION_PROTOCOL.StriColl() function description.
MetaiMatch Performs a case-insensitive comparison between a Null-terminated pattern string and a Null-terminated
string. The pattern string can use the ‘?’ wildcard to match any character, and the ‘*’ wildcard to match any
substring. See the EFI_UNICODE_COLLATION_PROTOCOL.MetaiMatch() function description.
StrLwr Converts all the characters in a Null-terminated string to lowercase characters. See the
EFI_UNICODE_COLLATION_PROTOCOL.StrLwr() function description.
StrUpr Converts all the characters in a Null-terminated string to uppercase characters. See the
EFI_UNICODE_COLLATION_PROTOCOL.StrUpr() function description.
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FatToStr Converts an 8.3 FAT ﬁle name using an OEM character set to a Null-terminated string. See the
EFI_UNICODE_COLLATION_PROTOCOL.FatToStr() function description.
StrToFat Converts a Null-terminated string to legal characters in a FAT ﬁlename using an OEM character set. See
theEFI_UNICODE_COLLATION_PROTOCOL.StrToFat() function description.
SupportedLanguages A Null-terminated ASCII string array that contains one or more language codes. This array is
speciﬁed in RFC 4646 format. See Formats — Language Codes and Language Code Arrays
The EFI_UNICODE_COLLATION_PROTOCOL is used to perform case-insensitive comparisons of strings.
One or more of the EFI_UNICODE_COLLATION_PROTOCOL instances may be present at one time.
Each protocol instance can support one or more language codes. The language codes supported in the
EFI_UNICODE_COLLATION_PROTOCOL are declared in SupportedLanguages .

TheSupportedLanguages is a Null-terminated ASCII string array that contains one or more supported language codes.
This is the list of language codes that this protocol supports. See Formats — Language Codes and Language Code
Arrays for the format of language codes and language code arrays.
The main motivation for this protocol is to help support ﬁle names in a ﬁle system driver. When a ﬁle is opened, a
ﬁle name needs to be compared to the ﬁle names on the disk. In some cases, this comparison needs to be performed
in a case-insensitive manner. In addition, this protocol can be used to sort ﬁles from a directory or to perform a
case-insensitive ﬁle search.
21.1.2 EFI_UNICODE_COLLATION_PROTOCOL.StriColl()
Summary
Performs a case-insensitive comparison of two Null-terminated strings.
Prototype
typedef
INTN
(EFIAPI *EFI_UNICODE_COLLATION_STRICOLL) (
IN EFI_UNICODE_COLLATION_PROTOCOL *This,
IN CHAR16 *s1,
IN CHAR16 *s2
);
This A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance. Type
EFI_UNICODE_COLLATION_PROTOCOL is deﬁned above.
s1A pointer to a Null-terminated string.
s2A pointer to a Null-terminated string.
The StriColl() function performs a case-insensitive comparison of two Null-terminated strings.
This function performs a case-insensitive comparison between the string s1 and the string s2 using the rules for the
language codes that this protocol instance supports. If s1 is equivalent to s2, then 0 is returned. If s1 is lexically less
than s2, then a negative number will be returned. If s1 is lexically greater than s2, then a positive number will be
returned. This function allows strings to be compared and sorted.
21.1. Unicode Collation Protocol 766Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
0 s1 is equivalent to s2.
> 0 s1 is lexically greater than s2.
< 0 s1 is lexically less than s2.
21.1.3 EFI_UNICODE_COLLATION_PROTOCOL.MetaiMatch()
Summary
Performs a case-insensitive comparison of a Null-terminated pattern string and a Null-terminated string.
Prototype
typedef
BOOLEAN
(EFIAPI *EFI_UNICODE_COLLATION_METAIMATCH) (
IN CHAR16 *String,
IN CHAR16 *Pattern
);
String A pointer to a Null-terminated string.
Pattern A pointer to a Null-terminated string.
The MetaiMatch() function performs a case-insensitive comparison of a Null-terminated pattern string and a Null-
terminated string.
This function checks to see if the pattern of characters described by Pattern are found in String . The pattern check is
a case-insensitive comparison using the rules for the language codes that this protocol instance supports. If the pattern
match succeeds, then TRUE is returned. Otherwise FALSE is returned. The following syntax can be used to build the
string Pattern:
* Match 0 or more characters.
? Match any one character.
[<char1><char2>...<charN>] Match any character in the set.
[<char1>-<char2>] Match any character between <char1> and<char2>.
<char> Match the character <char>.
Following is an example pattern for English:
*.FW Matches all strings that end in ".FW" or .fw" or ".Fw"
˓→or ".fW."
[a-z] Match any letter in the alphabet.
[!@#$%^& *()] Match any one of these symbols.
z Match the character "z" or "Z."
D?.* Match the character "D" or "d"
followed by any character
followed by a "." followed by any string.
21.1. Unicode Collation Protocol 767Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TRUE Pattern was found in String.
FALSE Pattern was not found in String.
21.1.4 EFI_UNICODE_COLLATION_PROTOCOL.StrLwr()
Summary
Converts all the characters in a Null-terminated string to lowercase characters.
Prototype
typedef
VOID
(EFIAPI *EFI_UNICODE_COLLATION_STRLWR) (
IN OUT CHAR16 *String
);
This function walks through all the characters in String, and converts each one to its lowercase equivalent if it has one.
The converted string is returned in String .
21.1.5 EFI_UNICODE_COLLATION_PROTOCOL.StrUpr()
Summary
Converts all the characters in a Null-terminated string to uppercase characters.
Prototype
typedef
VOID
(EFIAPI *EFI_UNICODE_COLLATION_STRUPR) (
);
This functions walks through all the characters in String, and converts each one to its uppercase equivalent if it has
one. The converted string is returned in String .
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21.1.6 EFI_UNICODE_COLLATION_PROTOCOL.FatToStr()
Summary
Converts an 8.3 FAT ﬁle name in an OEM character set to a Null-terminated string.
Prototype
typedef
VOID
(EFIAPI *EFI_UNICODE_COLLATION_FATTOSTR) (
IN UINTN FatSize,
IN CHAR8 *Fat,
OUT CHAR16 *String
);
FatSize The size of the string Fat in bytes.
Fat A pointer to a Null-terminated string that contains an 8.3 ﬁle name encoded using an 8-bit OEM character set.
String A pointer to a Null-terminated string. The string must be allocated in advance to hold FatSize characters.
This function converts the string speciﬁed by Fatwith length FatSize to the Null-terminated string speciﬁed by String
. The characters in Fatare from an OEM character set.
21.1.7 EFI_UNICODE_COLLATION_PROTOCOL.StrToFat()
Summary
Converts a Null-terminated string to legal characters in a FAT ﬁlename using an OEM character set.
Prototype
typedef
BOOLEAN
(EFIAPI *EFI_UNICODE_COLLATION_STRTOFAT) (
OUT CHAR8 *Fat
);
Fat A pointer to a string that contains the converted version of String using legal FAT characters from an OEM
character set.
21.1. Unicode Collation Protocol 769Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function converts the characters from String into legal FAT characters in an OEM character set and stores then in
the string Fat. This conversion continues until either FatSize bytes are stored in Fat,or the end of String is reached.
The characters ‘.’ (period) and ‘ ’ (space) are ignored for this conversion. Characters that map to an illegal FAT
character are substituted with an ‘_’. If no valid mapping from a character to an OEM character is available, then it
is also substituted with an ‘_’. If any of the character conversions are substituted with a ‘_’, then TRUE is returned.
Otherwise FALSE is returned.
TRUE One or more conversions failed and were substituted with ‘_’.
FALSE None of the conversions failed.
21.2 Regular Expression Protocol
This section deﬁnes the Regular Expression Protocol. This protocol is used to match Unicode strings against Regular
Expression patterns.
21.2.1 EFI_REGULAR_EXPRESSION_PROTOCOL
Summary
GUID
#define EFI_REGULAR_EXPRESSION_PROTOCOL_GUID \
{ 0xB3F79D9A, 0x436C, 0xDC11,\
{ 0xB0, 0x52, 0xCD, 0x85, 0xDF, 0x52, 0x4C, 0xE6 } }
EFI_REGULAR_EXPRESSION_MATCH MatchString;
EFI_REGULAR_EXPRESSION_GET_INFO GetInfo;
} EFI_REGULAR_EXPRESSION_PROTOCOL;
MatchString Search the input string for anything that matches the regular expression.
GetInfo Returns information about the regular expression syntax types supported by the implementation.
21.2.2 EFI_REGULAR_EXPRESSION_PROTOCOL.MatchString()
Summary
Checks if the input string matches to the regular expression pattern.
Prototype
typedef
EFIAPI*EFI_REGULAR_EXPRESSION_MATCH) (
IN EFI_REGULAR_EXPRESSION_PROTOCOL *This,
21.2. Regular Expression Protocol 770Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN CHAR16 *Pattern,
IN EFI_REGEX_SYNTAX_TYPE *SyntaxType, OPTIONAL
OUT BOOLEAN *Result,
OUT EFI_REGEX_CAPTURE **Captures, OPTIONAL
OUT UINTN *CapturesCount
);
This A pointer to the EFI_REGULAR_EXPRESSION_PROTOCOL instance. Type
EFI_REGULAR_EXPRESSION_PROTOCOL is deﬁned in above.
String A pointer to a NULL terminated string to match against the regular expression string speciﬁed by Pattern .

Summary
Prototype
typedef
);
Pattern A pointer to a NULL terminated string that represents the regular expression.
SyntaxType A pointer to the EFI_REGEX_SYNTAX_TYPE that identiﬁes the regular expression syntax type to use.
May be NULL in which case the function will use its default regular expression syntax type.
Result On return, points to TRUE if String fully matches against the regular expression Pattern using the regular
expression SyntaxType . Otherwise, points to FALSE .
Captures A Pointer to an array of EFI_REGEX_CAPTURE objects to receive the captured groups in the event of a
match. The full sub-string match is put in Captures [0], and the results of N capturing groups are put in Captures
[1:N]. If Captures is NULL, then this function doesn’t allocate the memory for the array and does not build up
the elements. It only returns the number of matching patterns in CapturesCount . If Captures is not NULL, this
function returns a pointer to an array and builds up the elements in the array. CapturesCount is also updated to
the number of matching patterns found. It is the caller’s responsibility to free the memory pool in Captures and
in each CapturePtr in the array elements.
CapturesCount On output, CapturesCount is the number of matching patterns found in String. Zero means no
matching patterns were found in the string.
The MatchString() function performs a matching of a Null-terminated input string with the NULL terminated pattern
string. The pattern string syntax type is optionally identiﬁed in SyntaxType .
This function checks to see if String fully matches against the regular expression described by Pattern. The pattern
check is performed using regular expression rules that are supported by this implementation, as indicated in the return
value of GetInfo function. If the pattern match succeeds, then TRUE is returned in Result . Otherwise FALSE is
returned.
CONST CHAR16 *CapturePtr;
UINTN Length;
} EFI_REGEX_CAPTURE;
*CapturePtr Pointer to the start of the captured sub-expression within matched String.
Length Length of captured sub-expression.
EFI_SUCCESS The regular expression string matching completed successfully.
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Table 21.1 – continued from previous page
EFI_UNSUPPORTED The regular expression syntax speciﬁed by SyntaxType is not supported by
this driver.
EFI_DEVICE_ERROR The regular expression string matching failed due to a hardware or ﬁrmware
error.
EFI_INV ALID_PARAMETER String, Pattern, Result, or CapturesCount is NULL.
21.2.3 EFI_REGULAR_EXPRESSION_PROTOCOL.GetInfo()
Summary
Returns information about the regular expression syntax types supported by the implementation.
Prototype
typedef
EFIAPI*EFI_REGULAR_EXPRESSION_GET_INFO) (
IN OUT UINTN *RegExSyntaxTypeListSize,
OUT EFI_REGEX_SYNTAX_TYPE *RegExSyntaxTypeList
);
This A pointer to the EFI_REGULAR_EXPRESSION_PROTOCOL instance.
RegExSyntaxTypeListSize On input, the size in bytes of RegExSyntaxTypeList . On output with a return code of
EFI_SUCCESS , th e size in bytes of the data returned in RegExSyntaxTypeList . On output with a return code
ofEFI_BUFFER_TOO_SMALL, the size of RegExSyntaxTypeList required to obtain the list.
RegExSyntaxTypeList A caller-allocated memory buffer ﬁlled by the driver with one EFI_REGEX_SYNTAX_TYPE
element for each supported regular expression syntax type. The list must not change across multiple calls to the
same driver. The ﬁrst syntax type in the list is the default type for the driver.
This function returns information about supported regular expression syntax types. A driver implementing the
EFI_REGULAR_EXPRESSION_PROTOCOL need not support more than one regular expression syntax type, but
shall support a minimum of one regular expression syntax type.
typedef EFI_GUID EFI_REGEX_SYNTAX_TYPE;
EFI_SUCCESS The regular expression syntax types list was returned successfully.
EFI_UNSUPPORTED The service is not supported by this driver.
EFI_DEVICE_ERROR The list of syntax types could not be retrieved due to a hardware or ﬁrmware
error.
EFI_BUFFER_TOO_SMALL The buffer RegExSyntaxTypeList is too small to hold the result.
EFI_INV ALID_PARAMETER RegExSyntaxTypeListSize is NULL.
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21.2.4 EFI Regular Expression Syntax Type Deﬁnitions
Summary
This sub-section provides EFI_GUID values for a selection of EFI_REGULAR_EXPRESSION_PROTOCOL syntax
types. The types listed are optional, not meant to be exhaustive and may be augmented by vendors or other industry
standards.
Prototype
For regular expression rules speciﬁed in the POSIX Extended Regular Expression (ERE) Syntax:
#define EFI_REGEX_SYNTAX_TYPE_POSIX_EXTENDED_GUID \
{0x5F05B20F, 0x4A56, 0xC231,\
{ 0xFA, 0x0B, 0xA7, 0xB1, 0xF1, 0x10, 0x04, 0x1D }}
For regular expression rules speciﬁed in the Perl standard:
#define EFI_REGEX_SYNTAX_TYPE_PERL_GUID \
{0x63E60A51, 0x497D, 0xD427,\
{ 0xC4, 0xA5, 0xB8, 0xAB, 0xDC, 0x3A, 0xAE, 0xB6 }}
For regular expression rules speciﬁed in the ECMA 262 Speciﬁcation:
#define EFI_REGEX_SYNTAX_TYPE_ECMA_262_GUID \
{ 0x9A473A4A, 0x4CEB, 0xB95A, 0x41,\
{ 0x5E, 0x5B, 0xA0, 0xBC, 0x63, 0x9B, 0x2E }}
For regular expression rules speciﬁed in the POSIX Extended Regular Expression (ERE) Syntax, where the Pattern
and String input strings need to be converted to ASCII:
#define EFI_REGEX_SYNTAX_TYPE_POSIX_EXTENDED_ASCII_GUID \
{0x3FD32128, 0x4BB1, 0xF632, \
{ 0xBE, 0x4F, 0xBA, 0xBF, 0x85, 0xC9, 0x36, 0x76 }}
For regular expression rules speciﬁed in the Perl standard, where the Pattern and String input strings nees to be
converted to ASCII:
#define EFI_REGEX_SYNTAX_TYPE_PERL_ASCII_GUID \
{0x87DFB76D, 0x4B58, 0xEF3A, \
{ 0xF7, 0xC6, 0x16, 0xA4, 0x2A, 0x68, 0x28, 0x10 }}
For regular expression rules speciﬁed in the ECMA 262 Speciﬁcation, where the Pattern and String input strings need
to be converted to ASCII:
#define EFI_REGEX_SYNTAX_TYPE_ECMA_262_ASCII_GUID \
{ 0xB2284A2F, 0x4491, 0x6D9D, \
{ 0xEA, 0xB7, 0x11, 0xB0, 0x67, 0xD4, 0x9B, 0x9A }}
SeeReferences for more information.
21.2. Regular Expression Protocol 773CHAPTER
TWENTYTWO
EFI BYTE CODE VIRTUAL MACHINE
This section deﬁnes an EFI Byte Code (EBC) Virtual Machine that can provide platform- and processor-independent
mechanisms for loading and executing EFI device drivers.
22.1 Overview
The current design for option ROMs that are used in personal computer systems has been in place since 1981. Attempts
to change the basic design requirements have failed for a variety of reasons. The EBC Virtual Machine described in
this chapter is attempting to help achieve the following goals:
• Abstract and extensible design
• Processor independence
• OS independence
• Build upon existing speciﬁcations when possible
• Facilitate the removal of legacy infrastructure
• Exclusive use of EFI Services
One way to satisfy many of these goals is to deﬁne a pseudo or virtual machine that can interpret a predeﬁned instruc-
tion set. This will allow the virtual machine to be ported across processor and system architectures without changing
or recompiling the option ROM. This speciﬁcation deﬁnes a set of machine level instructions that can be generated by
a C compiler.
The following sections are a detailed description of the requirements placed on future option ROMs.
22.1.1 Processor Architecture Independence
Option ROM images shall be independent of supported 32-bit and supported 64-bit architectures. In order to abstract
the architectural differences between processors option ROM images shall be EBC. This model is presented below:
• 64-bit C source code
• The EFI EBC image is the ﬂashed image
• The system BIOS implements the EBC interpreter
• The interpreter handles 32 vs. 64 bit issues
Current Option ROM technology is processor dependent and heavily reliant upon the existence of the PC-AT in-
frastructure. These dependencies inhibit the evolution of both hardware and software under the veil of “backward
compatibility.” A solution that isolates the hardware and support infrastructure through abstraction will facilitate the
uninhibited progression of technology.
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22.1.2 OS Independent
Option ROMs shall not require or assume the existence of a particular OS.
22.1.3 EFI Compliant
Option ROM compliance with EFI requires (but is not limited to) the following:
• Little endian layout
• Single-threaded model with interrupt polling if needed
• Where EFI provides required services, EFI is used exclusively. These include:
— Console I/O
— Memory Management
— Timer services
— Global variable access
• When an Option ROM provides EFI services, the EFI speciﬁcation is strictly followed:
— Service/protocol installation
— Calling conventions
— Data structure layouts

— Guaranteed return on services
22.1.4 Coexistence of Legacy Option ROMs
The infrastructure shall support coexistent Legacy Option ROM and EBC Option ROM images. This case would
occur, for example, when a Plug and Play Card has both Legacy and EBC Option ROM images ﬂashed. The details of
the mechanism used to select which image to load is beyond the scope of this document. Basically, a legacy System
BIOS would not recognize an EBC Option ROM and therefore would never load it. Conversely, an EFI Firmware
Boot Manager would only load images that it supports.
The EBC Option ROM format must utilize a legacy format to the extent that a Legacy System BIOS can:
• Determine the type of the image, in order to ignore the image. The type must be incompatible with currently
deﬁned types.
• Determine the size of the image, in order to skip to the next image.
22.1.5 Relocatable Image
An EBC option ROM image shall be eligible for placement in any system memory area large enough to accommodate
it.
Current option ROM technology requires images to be shadowed in system memory address range 0xC0000 to
0xEFFFF on a 2048 byte boundary. This dependency not only limits the number of Option ROMs, it results in
unused memory fragments up to 2 KiB.
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22.1.6 Size Restrictions Based on Memory Available
EBC option ROM images shall not be limited to a predetermined ﬁxed maximum size.
Current option ROM technology limits the size of a preinitialization option ROM image to 128 KiB (126 KiB actual).
Additionally, in the DDIM an image is not allowed to grow during initialization. It is inevitable that 64-bit solutions
will increase in complexity and size. To avoid revisiting this issue, EBC option ROM size is only limited by available
system memory. EFI memory allocation services allow device drivers to claim as much memory as they need, within
limits of available system memory.
The PCI speciﬁcation limits the size of an image stored in an option ROM to 16 MB. If the driver is stored on the
hard drive then the 16MB option ROM limit does not apply. In addition, the PE/COFF object format limits the size of
images to 2 GB.
22.2 Memory Ordering
The term memory ordering refers to the order in which a processor issues reads (loads) and writes (stores) out onto
the bus to system memory. The EBC Virtual Machine enforces strong memory ordering, where reads and writes are
issued on the system bus in the order they occur in the instruction stream under all circumstances.
22.3 Virtual Machine Registers
The EBC virtual machine utilizes a simple register set. There are two categories of VM registers: general purpose
registers and dedicated registers. All registers are 64-bits wide. There are eight (8) general-purpose registers (R0-R7),
which are used by most EBC instructions to manipulate or fetch data. The Table below, General Purpose VM Registers
, lists the general-purpose registers in the VM and the conventions for their usage during execution.
Table 22.1: General Purpose VM Registers
Index Register Description
0 R0 Points to the top of the stack
1-
3R1-R3 Preserved across calls
4-
7R4-R7 Scratch, not preserved across calls
Register R0 is used as a stack pointer and is used by the CALL ,RET ,PUSH , and POP instructions. The VM
initializes this register to point to the incoming arguments when an EBC image is started or entered. This register
may be modiﬁed like any other general purpose VM register using EBC instructions. Register R7 is used for function
return values.
Unlike the general-purpose registers, the VM dedicated registers have speciﬁc purposes. There are two dedicated
registers: the instruction pointer (IP), and the ﬂags (Flags) register. Specialized instructions provide access to the ded-
icated registers. These instructions reference the particular dedicated register by its assigned index value. Dedicated
VM Registers lists the dedicated registers and their corresponding index values.
Table 22.2: Dedicated VM Registers
0 FLAGS
Bit | Description
0 | C = Condition code
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1 | SS = Single step
2..63 | Reserved
1 IP Points to current instruction
2..7 Reserved Not deﬁned
The VM Flags register contains VM status and context ﬂags. VM Flags Register lists the descriptions of the bits in the
Flags register.
Table 22.3: VM Flags Register
Bit Flag Description
0 C Condition code. Set to 1 if the result of the last compare was TRUE , or set to 0 if the last
compare was FALSE . Used by conditional JMP instructions.
1 S Single-step. If set, causes the VM to generate a single-step exception after executing each
instruction. The bit is not cleared by the VM following the exception.
2..63 — Reserved
The VM IP register is used as an instruction pointer and holds the address of the currently executing EBC instruction.
The virtual machine will update the IP to the address of the next instruction on completion of the current instruction,
and will continue execution from the address indicated in IP. The IP register can be moved into any general-purpose
register (R0-R7). Data manipulation and data movement instructions can then be used to manipulate the value. The
only instructions that may modify the IP are the JMP ,CALL , and RET instructions. Since the instruction set is
designed to use words as the minimum instruction entity, the low order bit (bit 0) of IP is always cleared to 0. If a JMP,
CALL, or RET instruction causes bit 0 of IP to be set to 1, then an alignment exception occurs.
22.4 Natural Indexing
The natural indexing mechanism is the critical functionality that enables EBC to be executed unchanged on 32- or
64-bit systems. Natural indexing is used to specify the offset of data relative to a base address. However, rather than
specifying the offset as a ﬁxed number of bytes, the offset is encoded in a form that speciﬁes the actual offset in two
parts: a constant offset, and an offset speciﬁed as a number of natural units (where one natural unit = sizeof (VOID
*)). These two values are used to compute the actual offset to data at runtime. When the VM decodes an index during
execution, the resultant offset is computed based on the natural processor size. The encoded indexes themselves may
be 16, 32, or 64 bits in size. The Table below describes the ﬁelds in a natural index encoding.
Table 22.4: Index Encoding
Bit # Description
N Sign bit (sign), most signiﬁcant bit
N-3..N-1 Bits assigned to natural units (w)
A..N-4 Constant units (c)
0..A-1 Natural units (n)
As shown in the Table above for a given encoded index, the most signiﬁcant bit (bit N) speciﬁes the sign of the resultant
offset after it has been calculated. The sign bit is followed by three bits (N-3..N-1) that are used to compute the width
of the natural units ﬁeld (n). The value (w) from this ﬁeld is multiplied by the index size in bytes to determine the
actual width (A) of the natural units ﬁeld (n). Once the width of the natural units ﬁeld has been determined, then
the natural units (n) and constant units (c) can be extracted. The offset is then calculated at runtime according to the
following equation:
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Offset = (c + n *(sizeof (VOID *)))*sign
The following sections describe each of these ﬁelds in more detail.
22.4.1 Sign Bit
The sign bit determines the sign of the index once the offset calculation has been performed. All index computations
using “n” and “c” are done with positive numbers, and the sign bit is only used to set the sign of the ﬁnal offset
computed.
22.4.2 Bits Assigned to Natural Units
This 3-bit ﬁeld that is used to determine the width of the natural units ﬁeld. The units vary based on the size of the
index according to the Table, below, Index Size in Index Encoding . For example, for a 16-bit index, the value contained
in this ﬁeld would be multiplied by 2 to get the actual width of the natural-units ﬁeld.
Table 22.5: Index Size in Index Encoding
Index Size Units
16 bits 2 bits
32 bits 4 bits
64 bits 8 bits
22.4.3 Constant
The constant is the number of bytes in the index that do not scale with processor size. When the index is a 16-bit value,
the maximum constant is 4095. This index is achieved when the bits assigned to natural units is 0.
22.4.4 Natural Units
Natural units are used when a structure has ﬁelds that can vary with the architecture of the processor. Fields that
precipitate the use of natural units include pointers and EFI INTN and UINTN data types. The size of one pointer or
INTN/UINTN equals one natural unit. The natural units ﬁeld in an index encoding is a count of the number of natural
ﬁelds whose sizes (in bytes) must be added to determine a ﬁeld offset.
As an example, assume that a given EBC instruction speciﬁes a 16-bit index of 0xA048. This breaks down into:

• Sign bit (bit 15) = 1 (negative offset)
• Bits assigned to natural units (w, bits 14-12) = 2. Multiply by index size in bytes = 2 x 2 = 4 (A)
• c = bits 11-4 = 4
• n = bits 3-0 = 8
On a 32-bit machine, the offset is then calculated to be:
• Offset = (4 + 8 * 4) * -1 = -36
• On a 64-bit machine, the offset is calculated to be:
• Offset = (4 + 8 * 8) * -1 = -68
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22.5 EBC Instruction Operands
The VM supports an EBC instruction set that performs data movement, data manipulation, branching, and other
miscellaneous operations typical of a simple processor. Most instructions operate on two operands, and have the
general form:
INSTRUCTION Operand1, Operand2
Typically, instruction operands will be one of the following:
• Direct
• Indirect
• Indirect with index
• Immediate
The following subsections explain these operands.
22.5.1 Direct Operands
When a direct operand is speciﬁed for an instruction, the data to operate upon is contained in one of the VM general-
purpose registers R0-R7. Syntactically, an example of direct operand mode could be the ADD instruction:
ADD64 R1, R2
This form of the instruction utilizes two direct operands. For this particular instruction, the VM would take the contents
of register R2, add it to the contents of register R1, and store the result in register R1.
22.5.2 Indirect Operands
When an indirect operand is speciﬁed, a VM register contains the address of the operand data. This is sometimes
referred to as register indirect, and is indicated by preﬁxing the register operand with “@.” Syntactically, an example
of an indirect operand mode could be this form of the ADD instruction:
ADD32 R1, @R2
For this instruction, the VM would take the 32-bit value at the address speciﬁed in R2, add it to the contents of register
R1, and store the result in register R1.
22.5.3 Indirect with Index Operands
When an indirect with index operand is speciﬁed, the address of the operand is computed by adding the contents of
a register to a decoded natural index that is included in the instruction. Typically with indexed addressing, the base
address will be loaded in the register and an index value will be used to indicate the offset relative to this base address.
Indexed addressing takes the form:
@ R 1(+n,+c)
where:
• R 1is one of the general-purpose registers (R0-R7) which contains the base address
• +n is a count of the number of “natural” units offset. This portion of the total offset is computed at runtime as
(n * sizeof (VOID *))
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• +c is a byte offset to add to the natural offset to resolve the total offset
The values of n and c can be either positive or negative, though they must both have the same sign. These values get
encoded in the indexes associated with EBC instructions as shown in Index Encoding . Indexes can be 16-, 32-, or
64-bits wide depending on the instruction. An example of indirect with index syntax would be:
ADD32 R1, @R2(+1, +8)
This instruction would take the address in register R2, add (8 + 1 * sizeof (VOID *)), read the 32-bit value at the
address, add the contents of R1 to the value, and store the result back to R1.
22.5.4 Immediate Operands
Some instructions support an immediate operand, which is simply a value included in the instruction encoding. The
immediate value may or may not be sign extended, depending on the particular instruction. One instruction that
supports an immediate operand is MOVI . An example usage of this instruction is:
MOVIww R1, 0x1234
This instruction moves the immediate value 0x1234 directly into VM register R1. The immediate value is contained
directly in the encoding for the MOVI instruction.
22.6 EBC Instruction Syntax
Most EBC instructions have one or more variations that modify the size of the instruction and/or the behavior of the
instruction itself. These variations will typically modify an instruction in one or more of the following ways:
• The size of the data being operated upon
• The addressing mode for the operands
• The size of index or immediate data
• To represent these variations syntactically in this speciﬁcation the following conventions are used:
• Natural indexes are indicated with the “Index” keyword, and may take the form of “Index16,” “Index32,” or “In-
dex64” to indicate the size of the index value supported. Sometimes the form Index16|32|64 is used here, which
is simply a shorthand notation for Index16|Index32|Index64. A natural index is encoded per Index Encoding is
resolved at runtime.
• Immediate values are indicated with the “Immed” keyword, and may take the form of “Immed16,” “Immed32,”
or “Immed64” to indicate the size of the immediate value supported. The shorthand notation Immed16|32|64 is
sometimes used when different size immediate values are supported.
• Terms in brackets [ ] are required.
• Terms in braces { } are optional.
• Alternate terms are separated by a vertical bar |.
• The form R1 and R2 represent Operand 1 register and Operand 2 register respectfully, and can typically be any
VM general-purpose register R0-R7.
• Within descriptions of the instructions, brackets [ ] enclosing a register and/or index indicate that the contents
of the memory pointed to by the enclosed contents are used.
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22.7 Instruction Encoding
Most EBC instructions take the form:
INSTRUCTION R1, R2 Index|Immed
For those instructions that adhere to this form, the binary encoding for the instruction will typically consist of an
opcode byte, followed by an operands byte, followed by two or more bytes of immediate or index data. Thus the
instruction stream will be:
(1 Byte Opcode) + (1 Byte Operands) + (Immediate data|Index data)
22.7.1 Instruction Opcode Byte Encoding
The ﬁrst byte of an instruction is the opcode byte, and an instruction’s actual opcode value consumes 6 bits of this
byte. The remaining two bits will typically be used to indicate operand sizes and/or presence or absence of index or
immediate data. The Table, below, Opcode Byte Encoding deﬁnes the bits in the opcode byte for most instructions,
and their usage.
Table 22.6: Opcode Byte Encoding
Bit Sym Description
6..7 Modiﬁers
One or more of:
Index or immediate data present/absent
Operand size
Index or immediate data size
0..5 Op Instruction opcode
For those instructions that use bit 7 to indicate the presence of an index or immediate data and bit 6 to indicate the size
of the index or immediate data, if bit 7 is 0 (no immediate data), then bit 6 is ignored by the VM. Otherwise, unless
otherwise speciﬁed for a given instruction, setting unused bits in the opcode byte results in an instruction encoding
exception when the instruction is executed. Setting the modiﬁers ﬁeld in the opcode byte to reserved values will also
result in an instruction encoding exception.
22.7.2 Instruction Operands Byte Encoding
The second byte of most encoded instructions is an operand byte, which encodes the registers for the instruction
operands and whether the operands are direct or indirect. The Table below, Operand Byte Encoding deﬁnes the
encoding for the operand byte for these instructions. Unless otherwise speciﬁed for a given instruction, setting unused
bits in the operand byte results in an instruction encoding exception when the instruction is executed. Setting ﬁelds in
the operand byte to reserved values will also result in an instruction encoding exception.
Table 22.7: Operand Byte Encoding
7
0 = Operand 2 is direct
1 = Operand 2 is indirect
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Table 22.7 – continued from previous page
4..6 Operand 2 register
3
0 = Operand 1 is direct
1 = Operand 1 is indirect
0..2 Operand 1 register
22.7.3 Index/Immediate Data Encoding
Following the operand bytes for most instructions is the instruction’s immediate data. The immediate data is, depend-
ing on the instruction and instruction encoding, either an unsigned or signed literal value, or an index encoded using
natural encoding. In either case, the size of the immediate data is speciﬁed in the instruction encoding.
For most instructions, the index/immediate value in the instruction stream is interpreted as a signed immediate value
if the register operand is direct. This immediate value is then added to the contents of the register to compute the
instruction operand. If the register is indirect, then the data is usually interpreted as a natural index ( NATURAL
INDEXING ) and the computed index value is added to the contents of the register to get the address of the operand.
22.8 EBC Instruction Set
The following sections describe each of the EBC instructions in detail. Information includes an assembly-language

syntax, a description of the instruction functionality, binary encoding, and any limitations or unique behaviors of the
instruction.
22.8.1 ADD
Syntax :
ADD[32|64] {@}R1, {@}R2 {Index16|Immed16}
Adds two signed operands and stores the result to Operand 1. The operation can be performed on either 32-bit
(ADD32) or 64-bit (ADD64) operands.
Operation :
Operand 1 <= Operand 1 + Operand 2
Table 22.8: ADD Instruction Encoding
BYTE Description
0 Bit Description
7
0 = Immediate/index absent
1 = Immediate/index present
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Table 22.8 – continued from previous page
6
0 = 32-bit operation
1 = 64-bit operation
0..5 Opcode = 0x0C
1 Bit Description
7
0 = Operand 2 direct
1 = Operand 2 indirect
4..6 Operand 2
3
0 = Operand 1 direct
1 = Operand 1 indirect
0..2 Operand 1
2..3 Optional 16-bit immediate
data/index
Behaviors and Restrictions
• If Operand 2 is indirect, then the immediate data is interpreted as an index and the Operand 2 value is fetched
from memory as a signed value at address [R2 + Index16].
• If Operand 2 is direct, then the immediate data is considered a signed immediate value and is added to the R2
register contents such that Operand 2 = R2 + Immed16.
• If the instruction is ADD32 and Operand 1 is direct, then the result is stored back to the Operand 1 register with
the upper 32 bits cleared.
22.8.2 AND
Syntax
AND[32|64] {@}R1, {@}R2 {Index16|Immed16}
Performs a logical AND operation on two operands and stores the result to Operand 1. The operation can be performed
on either 32-bit (AND32) or 64-bit (AND64) operands.
Operation
Operand 1 <= Operand 1 AND Operand 2
Table 22.9: AND Instruction Encoding
7
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Table 22.9 – continued from previous page
6
0..5 Opcode = 0x14
7
3
• If Operand 2 is indirect, then the immediate data is interpreted as an index, and the Operand 2 value is fetched
from memory as an unsigned value at address [R2 + Index16].
• If Operand 2 is direct, then the immediate data is considered a signed immediate value and is added to the
• If the instruction is AND32 and Operand 1 is direct, then the result is stored to the Operand 1 register with the
upper 32 bits cleared.
22.8.3 ASHR
Syntax
ASHR[32|64] {@}R1, {@}R2 {Index16|Immed16}
Performs an arithmetic right-shift of a signed 32-bit (ASHR32) or 64-bit (ASHR64) operand and stores the result back
to Operand 1
Operation
Operand 1 <= Operand 1 SHIFT-RIGHT Operand 2
Table 22.10: ASHR Instruction Encoding
7
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Table 22.10 – continued from previous page
6
0..5 Opcode = 0x19
7
3
from memory as a signed value at address [R2+ Index16].
• If the instruction is ASHR32, and Operand 1 is direct, then the result is stored back to the Operand 1 register
with the upper 32 bits cleared.
22.8.4 BREAK
Syntax :
BREAK [breakcode]
The BREAK instruction is used to perform special processing by the VM. The break code speciﬁes the functionality
to perform.
BREAK 0 - Runaway program break. This indicates that the VM is likely executing code from cleared memory. This
results in a bad break exception.
BREAK 1 - Get virtual machine version. This instruction returns the 64-bit virtual machine revision number in VM
register R7. The encoding is shown in the Tables, below, VM Version Format andBREAK Instruction Encoding . A
VM that conforms to this version of the speciﬁcation should return a version number of 0x00010000.
Table 22.11: VM Version Format
Bits Description
63-32 Reserved = 0
31..16 VM major version
15..0 VM minor version
22.8. EBC Instruction Set 785Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BREAK 3 - Debug breakpoint. Executing this instruction results in a debug break exception. If a debugger is attached
or available, then it may halt execution of the image.
BREAK 4 - System call. There are no system calls supported for use with this break code, so the VM will ignore the
instruction and continue execution at the following instruction.
BREAK 5 - Create thunk. This causes the interpreter to create a thunk for the EBC entry point whose 32-bit IP-
relative offset is stored at the 64-bit address in VM register R7. The interpreter then replaces the contents of the
memory location pointed to by R7 to point to the newly created thunk. Since all EBC IP-relative offsets are relative to
the next instruction or data object, the original offset is off by 4, so must be incremented by 4 to get the actual address
of the entry point.
BREAK 6 - Set compiler version. An EBC C compiler can insert this break instruction into an executable to set the
compiler version used to build an EBC image. When the VM executes this instruction it takes the compiler version
from register R7 and may perform version compatibility checking. The compiler version number follows the same
format as the VM version number returned by the BREAK 1 instruction.
Table 22.12: BREAK Instruction Encoding
Byte Description
0 Opcode = 0x00
1
0 = Runaway program break
1 = Get virtual machine version
3 = Debug breakpoint
4 = System call
5 = Create thunk
6 = Set compiler version
• Executing an undeﬁned BREAK code results in a bad break exception.
• Executing BREAK 0 results in a bad break exception.
22.8.5 CALL
Syntax :
CALL32{EX}{a} {@}R1 {Immed32|Index32}
CALL64{EX}{a} Immed64
The CALL instruction pushes the address of the following instruction on the stack and jumps to a subroutine. The
subroutine may be either EBC or native code, and may be to an absolute or IP-relative address. CALL32 is used
to jump directly to EBC code within a given application, whereas CALLEX is used to jump to external code (either
native or EBC), which requires thunking. Functionally, the CALL does the following:
R0 = R0 - 8;
PUSH64 ReturnAddress
if(Opcode.ImmedData64Bit) {
if(Operands.EbcCall) {
IP = Immed64;
}else{
22.8. EBC Instruction Set 786Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NativeCall (Immed64);
}
}else{
if(Operand1 != R0) {
Addr = Operand1;
}else{
Addr = Immed32;
}
if(Operands.RelativeAddress) {
IP += Addr + SizeOfThisInstruction;
}else{
IP = Addr
}
}else{
NativeCall (IP + Addr)
}else{
NativeCall (Addr)
}
}
R0 <= R0 - 16
[R0] <= IP + SizeOfThisInstruction
IP <= IP + SizeOfThisInstruction + Operand 1 (relative CALL)
IP <= Operand 1 (absolute CALL)
Table 22.13: CALL Instruction Encoding
7
0 = Immediate/index data absent
1 = Immediate/index data present
6
0 = CALL32 with 32-bit immediate data/index if present
1 = CALL64 with 64-bit immediate data
0..5 Opcode = 0x03
6..7 Reserved = 0
5
0 = Call to EBC
1 = Call to native code
4
0 = Absolute address
1 = Relative address
22.8. EBC Instruction Set 787Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.13 – continued from previous page
3
2..5 Optional 32-bit in-
dex/immediate for CALL32
2..9 Required 64-bit immediate
data for CALL64
BEHA VIOR AND RESTRICTIONS
• For the CALL32 forms, if Operand 1 is indirect, then the immediate data is interpreted as an index, and the
Operand 1 value is fetched from memory address [R1 + Index32].
• For the CALL32 forms, if Operand 1 is direct, then the immediate data is considered a signed immediate value
and is added to the Operand 1 register contents such that Operand 1 = R1 + Immed32.
• For the CALLEX forms, the VM must ﬁx up the stack pointer and execute a call to native code in a manner

5
4
3
compatible with the native code such that the callee is able to access arguments passed on the VM stack..
• For the CALLEX forms, the value returned by the callee should be returned in R7.
• For the CALL64 forms, the Operand 1 ﬁelds are ignored.
• If Byte7:Bit6 = 1 (CALL64), then Byte1:Bit4 is assumed to be 0 (absolute address)
• For CALL32 forms, if Operand 1 register = R0, then the register operand is ignored and only the immediate
data is used in the calculation of the call address.
• Prior to the call, the VM will decrement the stack pointer R0 by 16 bytes, and store the 64-bit return address on
the stack.
• Offsets for relative calls are relative to the address of the instruction following the CALL instruction.
22.8.6 CMP
Syntax
CMP[32|64][eq|lte|gte|ulte|ugte] R1, {@}R2 {Index16|Immed16}
The CMP instruction is used to compare Operand 1 to Operand 2. Supported comparison modes are =, <=, >=,
unsigned <=, and unsigned >=. The comparison size can be 32 bits (CMP32) or 64 bits (CMP64). The effect of this
instruction is to set or clear the condition code bit in the Flags register per the comparison results. The operands are
compared as signed values except for the CMPulte and CMPugte forms.
CMPeq: Flags.C <= (Operand 1 == Operand 2)
CMPlte: Flags.C <= (Operand 1 <= Operand 2)
CMPgte: Flags.C <= (Operand 1 >= Operand 2)
CMPulte: Flags.C <= (Operand 1 <= Operand 2) (unsigned)
CMPugte: Flags.C <= (Operand 1>= Operand 2) (unsigned)
22.8. EBC Instruction Set 788Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.14: CMP Instruction Encoding
7
6
0 = 32-bit comparison
1 = 64-bit comparison
0..5
Opcode
0x05 = CMPeq compare equal
0x06 = CMPlte compare signed less then/equal
0x07 = CMPgte compare signed greater than/equal
0x08 = CMPulte compare unsigned less than/equal
0x09 = CMPugte compare unsigned greater than/equal
7
3 Reserved = 0
from memory address [R2 + Index16].
• Only register direct is supported for Operand 1.
22.8.7 CMPI
Syntax
CMPI[32|64]{w|d}[eq|lte|gte|ulte|ugte] {@}R1 {Index16}, Immed16|Immed32
Compares two operands, one of which is an immediate value, for =, <=, >=, unsigned <=, or unsigned >=, and sets or
clears the condition ﬂag bit in the Flags register accordingly. Comparisons can be performed on a 32-bit (CMPI32) or
64-bit (CMPI64) basis. The size of the immediate data can be either 16 bits (CMPIw) or 32 bits (CMPId).
22.8. EBC Instruction Set 789Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
CMPIeq: Flags.C <= (Operand 1 == Operand 2)
CMPIlte: Flags.C <= (Operand 1 <= Operand 2)
CMPIgte: Flags.C <= (Operand 1 >= Operand 2)
CMPIulte: Flags.C <= (Operand 1 <= Operand 2)
CMPIugte: Flags.C <= (Operand 1>= Operand 2)
Table 22.15: CMPI Instruction Encoding
7
0 = 16-bit immediate data
1 = 32-bit immediate data
6
0..5
Opcode
0x2D = CMPIeq compare equal
0x2E = CMPIlte compare signed less then/equal
0x2F = CMPIgte compare signed greater than/equal
0x30 = CMPIulte compare unsigned less than/equal
0x31 = CMPIugte compare unsigned greater than/equal
5..7 Reserved = 0
4
0 = Operand 1 index absent
1 = Operand 1 index present
3
2..3 Optional 16-bit Operand 1
index
2..3/4..5 16-bit immediate data
2..5/4..7 32-bit immediate data
• The immediate data is fetched as a signed value.
• If the immediate data is smaller than the comparison size, then the immediate data is sign-extended appropriately.
• If Operand 1 is direct, and an Operand 1 index is speciﬁed, then an instruction encoding exception is generated.
22.8. EBC Instruction Set 790Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.8 DIV
Syntax :
DIV[32|64] {@}R1, {@}R2 {Index16|Immed16}
Performs a divide operation on two signed operands and stores the result to Operand 1. The operation can be performed
on either 32-bit (DIV32) or 64-bit (DIV64) operands.
Operand 1 <= Operand 1 / Operand 2
Table 22.16: DIV Instruction Encoding
7
6
0..5 Opcode = 0x10
7
3
• If Operand 2 is direct, then the immediate data is considered a signed value and is added to the register contents
such that Operand 2 = R2 + Immed16
• If the instruction is DIV32 form, and Operand 1 is direct, then the upper 32 bits of the result are set to 0 before
storing to the Operand 1 register.
• A divide-by-0 exception occurs if Operand 2 = 0.
22.8. EBC Instruction Set 791Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.9 DIVU
Syntax :
DIVU[32|64] {@}R1, {@}R2 {Index16|Immed16}
Performs a divide operation on two unsigned operands and stores the result to Operand 1. The operation can be
performed on either 32-bit (DIVU32) or 64-bit (DIVU64) operands.
Table 22.17: DIVU Instruction Encoding
7
6
0..5 Opcode = 0x11
7
3
• If Operand 2 is indirect, then the immediate data is interpreted as an index, and the value is fetched from memory
as an unsigned value at address [R2+ Index16].
• If Operand 2 is direct, then the immediate data is considered an unsigned value and is added to the Operand 2
register contents such that Operand 2 = R2 + Immed16
• For the DIVU32 form, if Operand 1 is direct then the upper 32 bits of the result are set to 0 before storing back
to the Operand 1 register.
22.8. EBC Instruction Set 792Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.10 EXTNDB
Syntax :
EXTNDB[32|64] {@}R1, {@}R2 {Index16|Immed16}
Sign-extend a byte value and store the result to Operand 1. The byte can be signed extended to 32 bits (EXTNDB32)
or 64 bits (EXTNDB64).
Operand 1 <= (sign extended) Operand 2
Table 22.18: EXTNDB Instruction Encoding
7
6
0..5 Opcode = 0x1A
7
3
• If Operand 2 is indirect, then the immediate data is interpreted as an index, and the byte Operand 2 value is
fetched from memory as a signed value at address [R2 + Index16].
• If Operand 2 is direct, then the immediate data is considered a signed immediate value, is added to the signed-
extended byte from the Operand 2 register, and the byte result is sign extended to 32 or 64 bits.
• If the instruction is EXTNDB32 and Operand 1 is direct, then the 32-bit result is stored in the Operand 1 register
22.8. EBC Instruction Set 793Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.11 EXTNDD
Syntax :
EXTNDD[32|64] {@}R1, {@}R2 {Index16|Immed16}
Sign-extend a 32-bit Operand 2 value and store the result to Operand 1. The Operand 2 value can be extended to 32
bits (EXTNDD32) or 64 bits (EXTNDD64).
Operation
Table 22.19: EXTNDD Instruction Encoding
7
6
0..5 Opcode = 0x1C
7
3

Syntax :
Operation
7
6
7
3
• If Operand 2 is indirect, then the immediate data is interpreted as an index, and the 32-bit value is fetched from
memory as a signed value at address [R2 + Index16].
• If Operand 2 is direct, then the immediate data is considered a signed immediate value such that Operand 2 =
R2 + Immed16, and the value is sign extended to 32 or 64 bits accordingly.
• If the instruction is EXTNDD32 and Operand 1 is direct, then the result is stored in the Operand 1 register with
22.8. EBC Instruction Set 794Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.12 EXTNDW
Syntax
EXTNDW[32|64] {@}R1, {@}R2 {Index16|Immed16}
Sign-extend a 16-bit Operand 2 value and store the result back to Operand 1. The value can be signed extended to 32
bits (EXTNDW32) or 64 bits (EXTNDW64).
Operation
Table 22.20: EXTNDW Instruction Encoding
7
6
0..5 Opcode = 0x1B
7
3
• If Operand 2 is indirect, then the immediate data is interpreted as an index, and the word value is fetched from
• If the instruction is EXTNDW32 and Operand 1 is direct, then the 32-bit result is stored in the Operand 1 register
22.8. EBC Instruction Set 795Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.13 JMP
Syntax
JMP32{cs|cc} {@}R1 {Immed32|Index32}
JMP64{cs|cc} Immed64
The JMP instruction is used to conditionally or unconditionally jump to a relative or absolute address and continue
executing EBC instructions. The condition test is done using the condition bit in the VM Flags register. The JMP64
form only supports an immediate value that can be used for either a relative or absolute jump. The JMP32 form adds
support for indirect addressing of the JMP offset or address. The JMP is implemented as:
if(ConditionMet) {
if(Operand.RelativeJump) {
IP += Operand1 + SizeOfThisInstruction;
}else{
IP = Operand1;
}
}
Operation
IP <= Operand 1 (absolute address)
IP <= IP + SizeOfThisInstruction + Operand 1 (relative address)
Table 22.21: JMP Instruction Encoding
7
6
0 = JMP32
1 = JMP64
0..5 Opcode = 0x01
7
0 = Unconditional jump
1 = Conditional jump
6
0 = Jump if Flags.C is clear (cc)
1 = Jump if Flags.C is set (cs)
5 Reserved = 0
4
22.8. EBC Instruction Set 796Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.21 – continued from previous page
3
2..5 Optional 32-bit immediate
data/index for JMP32
2..9 64-bit immediate data for
JMP64
• Operand 1 ﬁelds are ignored for the JMP64 forms
• If the instruction is JMP32, and Operand 1 register = R0, then the register contents are assumed to be 0.
• If the instruction is JMP32, and Operand 1 is indirect, then the immediate data is interpreted as an index, and
the jump offset or address is fetched as a 32-bit signed value from address [R1 + Index32]
• If the instruction is JMP32, and Operand 1 is direct, then the immediate data is considered a signed immediate
value such that Operand 1 = R1 + Immed32
• If the jump is unconditional, then Byte1:Bit6 (condition) is ignored
• If the instruction is JMP64, and Byte0:Bit7 is clear (no immediate data), then an instruction encoding exception
is generated.
• If the instruction is JMP32, and Operand 2 is indirect, then the Operand 2 value is read as a natural value from
memory address [R1 + Index32]
• An alignment check exception is generated if the jump is taken and the target address is odd.
22.8.14 JMP8
Syntax
JMP8{cs|cc} Immed8
Conditionally or unconditionally jump to a relative offset and continue execution. The offset is a signed one-byte
offset speciﬁed in the number of words. The offset is relative to the start of the following instruction.
Operation
IP = IP + SizeOfThisInstruction + (Immed8 *2)
Table 22.22: JMP8 Instruction Encoding
7
22.8. EBC Instruction Set 797Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.22 – continued from previous page
6
0..5 Opcode = 0x02
1 Immediate data (signed word
offset)
• If the jump is unconditional, then Byte0:Bit6 (condition) is ignored
22.8.15 LOADSP
Syntax
LOADSP [Flags], R2
This instruction loads a VM dedicated register with the contents of a VM general-purpose register R0-R7. The dedi-
cated register is speciﬁed by its index as shown in Dedicated VM Registers .
Operation
Operand 1 <= R2
Table 22.23: LOADSP Instruction Encoding
0..5 Opcode = 0x29
1 7 Reserved
4..6 Operand 2 general purpose register
3 Reserved
0..2 Operand 1 dedicated register index
• Attempting to load any register (Operand 1) other than the Flags register results in an instruction encoding
exception.
• Specifying a reserved dedicated register index results in an instruction encoding exception.
• If Operand 1 is the Flags register, then reserved bits in the Flags register are not modiﬁed by this instruction.
22.8. EBC Instruction Set 798Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.16 MOD
Syntax
MOD[32|64] {@}R1, {@}R2 {Index16|Immed16}
Perform a modulus on two signed 32-bit (MOD32) or 64-bit (MOD64) operands and store the result to Operand 1.
Operation
Operand 1 <= Operand 1 MOD Operand 2
Table 22.24: MOD Instruction Encoding
7
6
0..5 Opcode = 0x12
7
3
• If Operand 2 = 0, then a divide-by-zero exception is generated.
22.8. EBC Instruction Set 799Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.17 MODU
Syntax
MODU[32|64] {@}R1, {@}R2 {Index16|Immed16}
Perform a modulus on two unsigned 32-bit (MODU32) or 64-bit (MODU64) operands and store the result to Operand
1.
Operation
Table 22.25: MODU Instruction Encoding
7
6
0..5 Opcode = 0x13
7
3
• If Operand 2 is direct, then the immediate data is considered an unsigned immediate value such that Operand 2
= R2 + Immed16.
22.8. EBC Instruction Set 800Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.18 MOV
Syntax
MOV[b|w|d|q]{w|d} {@}R1 {Index16|32}, {@}R2 {Index16|32}
MOVqq {@}R1 {Index64}, {@}R2 {Index64}
This instruction moves data from Operand 2 to Operand 1. Both operands can be indexed, though both indexes are the
same size. In the instruction syntax for the ﬁrst form, the ﬁrst variable character indicates the size of the data move,
which can be 8 bits (b), 16 bits (w), 32 bits (d), or 64 bits (q). The optional character indicates the presence and size of
the index value(s), which may be 16 bits (w) or 32 bits (d). The MOVqq instruction adds support for 64-bit indexes.
Operation
Operand 1 <= Operand 2
Table 22.26: MOV Instruction Encoding

Syntax
Operation
7
6
0 = Operand 2 index absent
1 = Operand 2 index present
0..5
0x1D = MOVbw opcode
0x1E = MOVww opcode
0x1F = MOVdw opcode
0x20 = MOVqw opcode
0x21 = MOVbd opcode
0x22 = MOVwd opcode
0x23 = MOVdd opcode
0x24 = MOVqd opcode
0x28 = MOVqq opcode
7
3
22.8. EBC Instruction Set 801Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.26 – continued from previous page
2..3 Optional Operand 1 16-bit
index
2..3/4..5 Optional Operand 2 16-bit
index
2..5 Optional Operand 1 32-bit
index
2..5/6..9 Optional Operand 2 32-bit
index
2..9 Optional Operand 1 64-bit
index (MOVqq)
2..9/10..17 Optional Operand 2 64-bit
• If an index is speciﬁed for Operand 1, and Operand 1 is direct, then an instruction encoding exception is gener-
ated.
22.8.19 MOVI
Syntax
MOVI[b|w|d|q][w|d|q] {@}R1 {Index16}, Immed16|32|64
This instruction moves a signed immediate value to Operand 1. In the instruction syntax, the ﬁrst variable character
speciﬁes the width of the move, which may be 8 bits (b), 16 bits (w), 32-bits (d), or 64 bits (q). The second variable
character speciﬁes the width of the immediate data, which may be 16 bits (w), 32 bits (d), or 64 bits (q).
Operation
Table 22.27: MOVI Instruction Encoding
6..7
0 = Reserved
1 = Immediate data is 16 bits (w)
2 = Immediate data is 32 bits (d)
3 = Immediate data is 64 bits (q)
0..5 Opcode = 0x37
7 Reserved = 0
6
22.8. EBC Instruction Set 802Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.27 – continued from previous page
4..5
0 = 8 bit (b) move
1 = 16 bit (w) move
2 = 32 bit (d) move
3 = 64 bit (q) move
3
2..3 Optional 16-bit index
2..9/4..11 64-bit immediate data
• Specifying an index value with Operand 1 direct results in an instruction encoding exception.
• If the immediate data is smaller than the move size, then the value is sign-extended to the width of the move.
• If Operand 1 is a register, then the value is stored to the register with bits beyond the move size cleared.
22.8.20 MOVIn
Syntax
MOVIn[w|d|q] {@}R1 {Index16}, Index16|32|64
This instruction moves an indexed value of form (+n,+c) to Operand 1. The index value is converted from (+n, +c)
format to a signed offset per the encoding described in Index Encoding . The size of the Operand 2 index data can be
16 (w), 32 (d), or 64 (q) bits.
Operation
Operand 1 <= Operand 2 (index value)
Table 22.28: MOVIn Instruction Encoding
6..7
1 = Operand 2 index value is 16 bits (w)
2 = Operand 2 index value is 32 bits (d)
0..5 Opcode = 0x38
7 Reserved
22.8. EBC Instruction Set 803Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.28 – continued from previous page
6
4..5 Reserved = 0
3
index
2..3/4..5 16-bit Operand 2 index
2..5/4..7 32-bit Operand 2 index
2..9/4..11 64-bit Operand 2 index
• Specifying an Operand 1 index when Operand 1 is direct results in an instruction encoding exception.
• The Operand 2 index is sign extended to the size of the move if necessary.
• If the Operand 2 index size is smaller than the move size, then the value is truncated.
• If Operand 1 is direct, then the Operand 2 value is sign extended to 64 bits and stored to the Operand 1 register.
22.8.21 MOVn
Syntax
MOVn{w|d} {@}R1 {Index16|32}, {@}R2 {Index16|32}
This instruction loads an unsigned natural value from Operand 2 and stores the value to Operand 1. Both operands can
be indexed, though both operand indexes are the same size. The operand index(s) can be 16 bits (w) or 32 bits (d).
Operation
Operand1 <= (UINTN)Operand2
Table 22.29: MOVn Instruction Encoding
7
6
22.8. EBC Instruction Set 804Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.29 – continued from previous page
0..5
0x32 = MOVnw opcode
0x33 = MOVnd opcode
7
3
index
index
index
index
• If an index is speciﬁed for Operand 2, and Operand 2 register is direct, then the Operand 2 index value is added
to the register contents such that Operand 2 = (UINTN)(R2 + Index).
ated.
• If Operand 1 is direct, then the Operand 2 value will be 0-extended to 64 bits on a 32-bit machine before storing
22.8.22 MOVREL
Syntax
MOVREL[w|d|q] {@}R1 {Index16}, Immed16|32|64
This instruction fetches data at an IP-relative immediate offset (Operand 2) and stores the result to Operand 1. The
offset is a signed offset relative to the following instruction. The fetched data is unsigned and may be 16 (w), 32 (d),
or 64 (q) bits in size.
Operation
Operand 1 <= [IP + SizeOfThisInstruction + Immed]
22.8. EBC Instruction Set 805Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.30: MOVREL Instruction Encoding
6..7
0..5 Opcode = 0x39
6
3
index
2..3/4..5 16-bit immediate offset
2..5/4..7 32-bit immediate offset
2..9/4..11 64-bit immediate offset
• If an Operand 1 index is speciﬁed and Operand 1 is direct, then an instruction encoding exception is generated.
22.8.23 MOVsn
Syntax
MOVsn{w} {@}R1, {Index16}, {@}R2 {Index16|Immed16}
MOVsn{d} {@}R1 {Index32}, {@}R2 {Index32|Immed32}
Moves a signed natural value from Operand 2 to Operand 1. Both operands can be indexed, though the indexes are the
same size. Indexes can be either 16 bits (MOVsnw) or 32 bits (MOVsnd) in size.
Operation
Table 22.31: MOVsn Instruction Encoding
22.8. EBC Instruction Set 806Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.31 – continued from previous page
7
6
0 = Operand 2 index/immediate data absent
1 = Operand 2 index/immediate data present
0..5
0x25 = MOVsnw opcode
0x26 = MOVsnd opcode
7
3
index (MOVsnw)
2..3/4..5 Optional 16-bit Operand 2
2..5 Optional 32-bit Operand
1 index/immediate data
(MOVsnd)
2..5/6..9 Optional 32-bit Operand
2 index/immediate data
(MOVsnd)
• If Operand 2 is direct, and Operand 2 index/immediate data is speciﬁed, then the immediate value is read as a
signed immediate value and is added to the contents of Operand 2 register such that Operand 2 = R2 + Immed.
• If Operand 2 is indirect, and Operand 2 index/immediate data is speciﬁed, then the immediate data is interpreted
as an index and the Operand 2 value is fetched from memory as a signed value at address [R2 + Index16].
ated.
• If Operand 1 is direct, then the Operand 2 value is sign-extended to 64-bits on 32-bit native machines.
22.8. EBC Instruction Set 807Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.24 MUL
Syntax
MUL[32|64] {@}R1, {@}R2 {Index16|Immed16}
Perform a signed multiply of two operands and store the result back to Operand 1. The operands can be either 32 bits
(MUL32) or 64 bits (MUL64).
Operation
Operand 1 <= Operand *Operand 2
Table 22.32: MUL Instruction Encoding
7
0 = Operand 2 immediate/index absent
1 = Operand 2 immediate/index present
6

ated.
Syntax
Operation
7
6
0..5 Opcode = 0x0E
7
3
2..3 Optional 16-bit Operand 2
immediate data/index
Operand 2 register contents such that Operand 2 = R2 + Immed16.
• If the instruction is MUL32, and Operand 1 is direct, then the result is stored to Operand 1 register with the
22.8. EBC Instruction Set 808Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.25 MULU
Syntax
MULU[32|64] {@}R1, {@}R2 {Index16|Immed16}
Performs an unsigned multiply of two 32-bit (MULU32) or 64-bit (MULU64) operands, and stores the result back to
Operand 1.
Operation
Table 22.33: MULU Instruction Encoding
7
6
0..5 Opcode = 0x0F
7
3
• If the instruction is MULU32 and Operand 1 is direct, then the result is written to the Operand 1 register with
22.8. EBC Instruction Set 809Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.26 NEG
Syntax
NEG[32|64] {@}R1, {@}R2 {Index16|Immed16}
Multiply Operand 2 by negative 1, and store the result back to Operand 1. Operand 2 is a signed value and fetched as
either a 32-bit (NEG32) or 64-bit (NEG64) value.
Operation
Operand 1 <= -1 *Operand 2
Table 22.34: NEG Instruction Encoding
7
6
0..5 Opcode = 0x0B
7
3
• If the instruction is NEG32 and Operand 1 is direct, then the result is stored in Operand 1 register with the upper
32-bits cleared.
22.8. EBC Instruction Set 810Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.27 NOT
Syntax
NOT[32|64] {@}R1, {@}R2 {Index16|Immed16}
Performs a logical NOT operation on Operand 2, an unsigned 32-bit (NOT32) or 64-bit (NOT64) value, and stores the
result back to Operand 1.
Operation
Operand 1 <= NOT Operand 2
Table 22.35: NOT Instruction Encoding
7
6
0..5 Opcode = 0x0A
7
3
• If the instruction is NOT32 and Operand 1 is a register, then the result is stored in the Operand 1 register with
22.8. EBC Instruction Set 811Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.28 OR
Syntax
OR[32|64] {@}R1, {@}R2 {Index16|Immed16}
Performs a bit-wise OR of two 32-bit (OR32) or 64-bit (OR64) operands, and stores the result back to Operand 1.
Operation
Operand 1 <= Operand 1 OR Operand 2
Table 22.36: OR Instruction Encoding
7
6
0..5 Opcode = 0x15
7
3
• If the instruction is OR32 and Operand 1 is direct, then the result is stored to Operand 1 register with the upper
32 bits cleared.
22.8. EBC Instruction Set 812Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.29 POP
Syntax
POP[32|64] {@}R1 {Index16|Immed16}
This instruction pops a 32-bit (POP32) or 64-bit (POP64) value from the stack, stores the result to Operand 1, and
adjusts the stack pointer R0 accordingly.
Operation
Operand 1 <= [R0]
R0 <= R0 + 4 (POP32)
R0 <= R0 + 8 (POP64)
Table 22.37: POP Instruction Encoding
7
6
0..5 Opcode = 0x2C
7..4 Reserved = 0
3
• If Operand 1 is direct, and an index/immediate data is speciﬁed, then the immediate data is read as a signed
value and is added to the value popped from the stack, and the result stored to the Operand 1 register.
• If Operand 1 is indirect, then the immediate data is interpreted as an index, and the value popped from the stack
is stored to address [R1 + Index16].
• If the instruction is POP32, and Operand 1 is direct, then the popped value is sign-extended to 64 bits before
22.8. EBC Instruction Set 813Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.30 POPn
Syntax
POPn {@}R1 {Index16|Immed16}
Read an unsigned natural value from memory pointed to by stack pointer R0, adjust the stack pointer accordingly, and
store the value back to Operand 1.
Operation
Operand 1 <= (UINTN)[R0]
R0 <= R0 + sizeof (VOID *)
Table 22.38: POPn Instruction Encoding
7
6 Reserved = 0
0..5 Opcode = 0x36
3
• If Operand 1 is direct, and an index/immediate data is speciﬁed, then the immediate data is fetched as a signed
value and is added to the value popped from the stack and the result is stored back to the Operand 1 register.
• If Operand 1 is indirect, and an index/immediate data is speciﬁed, then the immediate data is interpreted as a
natural index and the value popped from the stack is stored at [R1 + Index16].
• If Operand 1 is direct, and the instruction is executed on a 32-bit machine, then the result is stored to the Operand
1 register with the upper 32 bits cleared.
22.8. EBC Instruction Set 814Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.31 PUSH
Syntax
PUSH[32|64] {@}R1 {Index16|Immed16}
Adjust the stack pointer R0 and store a 32-bit (PUSH32) or 64-bit (PUSH64) Operand 1 value on the stack.
Operation
R0 <= R0 - 4 (PUSH32)
R0 <= R0 - 8 (PUSH64)
[R0] <= Operand 1
Table 22.39: PUSH Instruction Encoding
7
6
0..5 Opcode = 0x2B
3

Syntax
Operation
7
6
3
value and is added to the Operand 1 register contents such that Operand 1 = R1 + Immed16.
natural index and the pushed value is read from [R1 + Index16].
22.8. EBC Instruction Set 815Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.32 PUSHn
Syntax
PUSHn {@}R1 {Index16|Immed16}
Adjust the stack pointer R0, and store a natural value on the stack.
Operation
R0 <= R0 - sizeof (VOID *)
Table 22.40: PUSHn Instruction Encoding
7
0..5 Opcode = 0x35
3
natural index and the Operand 1 value pushed is fetched from [R1 + Index16].
22.8.33 RET
Syntax
RET
This instruction fetches the return address from the stack, sets the IP to the value, adjusts the stack pointer register R0,
and continues execution at the return address. If the RET is a ﬁnal return from the EBC driver, then execution control
returns to the caller, which may be EBC or native code.
Operation
22.8. EBC Instruction Set 816Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IP <= [R0]
R0 <= R0 + 16
Table 22.41: RET Instruction Encoding
0..5 Opcode = 0x04
1 Reserved = 0
• An alignment exception will be generated if the return address is not aligned on a 16-bit boundary.
22.8.34 SHL
Syntax
SHL[32|64] {@}R1, {@}R2 {Index16|Immed16}
Left-shifts Operand 1 by Operand 2 bit positions and stores the result back to Operand 1. The operand sizes may be
either 32-bits (SHL32) or 64 bits (SHL64).
Operation
Operand 1 <= Operand 1 << Operand 2
Table 22.42: SHL Instruction Encoding
7
6
0..5 Opcode = 0x17
7
3
22.8. EBC Instruction Set 817Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.42 – continued from previous page
• If the instruction is SHL32, and Operand 1 is direct, then the result is stored to the Operand 1 register with the
22.8.35 SHR
Syntax
SHR[32|64] {@}R1, {@}R2 {Index16|Immed16}
Right-shifts unsigned Operand 1 by Operand 2 bit positions and stores the result back to Operand 1. The operand sizes
may be either 32-bits (SHR32) or 64 bits (SHR64).
Operation
Operand 1 <= Operand 1 >> Operand 2
Table 22.43: SHR Instruction Encoding
7
6
0..5 Opcode = 0x18
7
3
22.8. EBC Instruction Set 818Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 22.43 – continued from previous page
• If the instruction is SHR32, and Operand 1 is direct, then the result is stored to the Operand 1 register with the
22.8.36 STORESP
Syntax
STORESP R1, [IP|Flags]
This instruction transfers the contents of a dedicated register to a general-purpose register. See the Table, below,
Dedicated VM Registers for the VM dedicated registers and their corresponding index values.
Operation
Table 22.44: STORESP Instruction Encoding
0..5 Opcode = 0x2A
1 7 Reserved = 0
4..6 Operand 2 dedicated register index
0..2 Operand 1 general purpose register
• Specifying an invalid dedicated register index results in an instruction encoding exception.
22.8. EBC Instruction Set 819Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.37 SUB
Syntax
SUB[32|64] {@}R1, {@}R2 {Index16|Immed16}
Subtracts a 32-bit (SUB32) or 64-bit (SUB64) signed Operand 2 value from a signed Operand 1 value of the same
size, and stores the result to Operand 1.
Operation
Operand 1 <= Operand 1 - Operand 2
Table 22.45: SUB Instruction Encoding
7
6
0..5 Opcode = 0x0D
7
3
• If the instruction is SUB32 and Operand 1 is direct, then the result is stored to the Operand 1 register with the
22.8. EBC Instruction Set 820Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.8.38 XOR
Syntax
XOR[32|64] {@}R1, {@}R2 {Index16|Immed16}
Performs a bit-wise exclusive OR of two 32-bit (XOR32) or 64-bit (XOR64) operands, and stores the result back to
Operand 1.
Operation
Operand 1 <= Operand 1 XOR Operand 2
Table 22.46: XOR Instruction Encoding
7
6
0..5 Opcode = 0x16
7
3
• If the instruction is XOR32 and Operand1 is direct, then the result is stored to the Operand 1 register with the
upper 32-bits cleared.
22.8. EBC Instruction Set 821Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.9 Runtime and Software Conventions
22.9.1 Calling Outside VM
Calls can be made to routines in other modules that are native or in another VM. It is the responsibility of the calling
VM to prepare the outgoing arguments correctly to make the call outside the VM. It is also the responsibility of the
VM to prepare the incoming arguments correctly for the call from outside the VM. Calls outside the VM must use the
CALLEX CALL instruction.
22.9.2 Calling Inside VM
Calls inside VM can be made either directly using the CALL orCALLEX instructions. Using direct CALL instructions
is an optimization.
22.9.3 Parameter Passing
Parameters are pushed on the VM stack per the CDECL calling convention. Per this convention, the last argument in
the parameter list is pushed on the stack ﬁrst, and the ﬁrst argument in the parameter list is pushed on the stack last.

All parameters are stored or accessed as natural size (using naturally sized instruction) except 64-bit integers, which
are pushed as 64-bit values. 32-bit integers are pushed as natural size (since they should be passed as 64-bit parameter
values on 64-bit machines).
22.9.4 Return Values
Return values of 8 bytes or less in size are returned in general-purpose register R7. Return values larger than 8 bytes
are not supported.
22.9.5 Binary Format
PE32+ format will be used for generating binaries for the VM. A VarBss section will be included in the binary image.
All global and static variables will be placed in this section. The size of the section will be based on worst-case 64-bit
pointers. Initialized data and pointers will also be placed in the VarBss section, with the compiler generating code to
initialize the values at runtime.
22.10 Architectural Requirements
This section provides a high level overview of the architectural requirements that are necessary to support execution
of EBC on a platform.
22.9. Runtime and Software Conventions 822Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.10.1 EBC Image Requirements
All EBC images will be PE32+ format. Some minor additions to the format will be required to support EBC images.
See the Microsoft Portable Executable and Common Object File Format Speciﬁcation pointed to in References for
details of this image ﬁle format.
A given EBC image must be executable on different platforms, independent of whether it is a 32- or 64-bit processor.
All EBC images should be driver implementations.
22.10.2 EBC Execution Interfacing Requirements
EBC drivers will typically be designed to execute in an (usually preboot) EFI environment. As such, EBC drivers must
be able to invoke protocols and expose protocols for use by other drivers or applications. The following execution
transitions must be supported:
• EBC calling EBC
• EBC calling native code
• Native code calling EBC
• Native code calling native code
• Returning from all the above transitions
Obviously native code calling native code is available by default, so is not discussed in this document.
To maintain backward compatibility with existing native code, and minimize the overhead for non-EBC drivers calling
EBC protocols, all four transitions must be seamless from the application perspective. Therefore, drivers, whether EBC
or native, shall not be required to have any knowledge of whether or not the calling code, or the code being called, is
native or EBC compiled code. The onus is put on the tools and interpreter to support this requirement.
22.10.3 Interfacing Function Parameters Requirements
To allow code execution across protocol boundaries, the interpreter must ensure that parameters passed across execu-
tion transitions are handled in the same manner as the standard parameter passing convention for the native processor.
22.10.4 Function Return Requirements
The interpreter must support standard function returns to resume execution to the caller of external protocols. The
details of this requirement are speciﬁc to the native processor. The called function must not be required to have any
knowledge of whether or not the caller is EBC or native code.
22.10.5 Function Return Values Requirements
The interpreter must support standard function return values from called protocols. The exact implementation of this
functionality is dependent on the native processor. This requirement applies to return values of 64 bits or less. The
called function must not be required to have any knowledge of whether or not the caller is EBC or native code. Note
that returning of structures is not supported.
22.10. Architectural Requirements 823Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.11 EBC Interpreter Protocol
The EFI EBC protocol provides services to execute EBC images, which will typically be loaded into option ROMs.
22.11.1 EFI_EBC_PROTOCOL
Summary
This protocol provides the services that allow execution of EBC images.
GUID
#define EFI_EBC_PROTOCOL_GUID \
{0x13ac6dd1,0x73d0,0x11d4,\
{0xb0,0x6b,0x00,0xaa,0x00,0xbd,0x6d,0xe7}}
typedef struct _EFI_EBC_PROTOCOL {
EFI_EBC_CREATE_THUNK CreateThunk;
EFI_EBC_UNLOAD_IMAGE UnloadImage;
EFI_EBC_REGISTER_ICACHE_FLUSH RegisterICacheFlush;
EFI_EBC_GET_VERSION GetVersion;
} EFI_EBC_PROTOCOL;
CreateThunk Creates a thunk for an EBC image entry point or protocol service, and returns a pointer to the thunk.
See the EFI_EBC_PROTOCOL.CreateThunk() function description.
UnloadImage Called when an EBC image is unloaded to allow the interpreter to perform any cleanup associated with
the image’s execution. See the EFI_EBC_PROTOCOL.UnloadImage() function description.
RegisterICacheFlush Called to register a callback function that the EBC interpreter can call to ﬂush the proces-
sor instruction cache after creating thunks. See the EFI_EBC_PROTOCOL.RegisterICacheFlush() function
GetVersion Called to get the version of the associated EBC interpreter. See the EFI_EBC_PROTOCOL.GetVersion()
The EFI EBC protocol provides services to load and execute EBC images, which will typically be loaded
into option ROMs. The image loader will load the EBC image, perform standard relocations, and invoke the
EFI_EBC_PROTOCOL.CreateThunk() service to create a thunk for the EBC image’s entry point. The image can
then be run using the standard EFI start image services.
22.11.2 EFI_EBC_PROTOCOL.CreateThunk()
Summary
Creates a thunk for an EBC entry point, returning the address of the thunk.
Prototype
22.11. EBC Interpreter Protocol 824Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef
(EFIAPI *EFI_EBC_CREATE_THUNK) (
IN EFI_EBC_PROTOCOL *This,
IN VOID *EbcEntryPoint,
OUT VOID **Thunk
);
This A pointer to the EFI_EBC_PROTOCOL instance. This protocol is deﬁned in EBC Interpreter Protocol .
ImageHandle Handle of image for which the thunk is being created.
EbcEntryPoint Address of the actual EBC entry point or protocol service the thunk should call.
Thunk Returned pointer to a thunk created.
A PE32+ EBC image, like any other PE32+ image, contains an optional header that speciﬁes the entry point for image
execution. However for EBC images this is the entry point of EBC instructions, so is not directly executable by the
native processor. Therefore when an EBC image is loaded, the loader must call this service to get a pointer to native
code (thunk) that can be executed which will invoke the interpreter to begin execution at the original EBC entry point.
EFI_INV ALID_PARAMETER Image entry point is not 2-byte aligned.
EFI_OUT_OF_RESOURCES Memory could not be allocated for the thunk.
22.11.3 EFI_EBC_PROTOCOL.UnloadImage()
Summary
Called prior to unloading an EBC image from memory.
Prototype
typedef
(EFIAPI *EFI_EBC_UNLOAD_IMAGE) (
);
ImageHandle Image handle of the EBC image that is being unloaded from memory.
This function is called after an EBC image has exited, but before the image is actually unloaded. It is intended to
provide the interpreter with the opportunity to perform any cleanup that may be necessary as a result of loading and
executing the image.
22.11. EBC Interpreter Protocol 825Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_INV ALID_PARAMETER Image handle is not recognized as belonging to an EBC image that has been
executed.
22.11.4 EFI_EBC_PROTOCOL.RegisterICacheFlush()
Summary
Registers a callback function that the EBC interpreter calls to ﬂush the processor instruction cache following creation
of thunks.
Prototype
typedef
(*EFI_EBC_REGISTER_ICACHE_FLUSH) (
IN EFI_EBC_PROTOCOL **This,
IN EBC_ICACHE_FLUSH *Flush
);
Flush Pointer to a function of type EBC_ICACH_FLUSH. See “Related Deﬁnitions” below for a detailed description
of this type.
typedef
(*EBC_ICACHE_FLUSH) (
IN EFI_PHYSICAL_ADDRESS Start,
);
Start The beginning physical address to ﬂush from the processor’s instruction cache.
Length The number of bytes to ﬂush from the processor’s instruction cache.
This is the prototype for the Flush callback routine. A pointer to a routine of this type is passed to the EBC
EFI_EBC_REGISTER_ICACHE_FLUSH protocol service.
An EBC image’s original PE32+ entry point is not directly executable by the native processor. Therefore to execute

of thunks.
Prototype
typedef
);
typedef
);
an EBC image, a thunk (which invokes the EBC interpreter for the image’s original entry point) must be created for
the entry point, and the thunk is executed when the EBC image is started. Since the thunks may be created on-the-
ﬂy in memory, the processor’s instruction cache may require to be ﬂushed after thunks are created. The caller to
this EBC service can provide a pointer to a function to ﬂush the instruction cache for any thunks created after the
EFI_EBC_PROTOCOL.CreateThunk() service has been called. If an instruction-cache ﬂush callback is not provided
to the interpreter, then the interpreter assumes the system has no instruction cache, or that ﬂushing the cache is not
required following creation of thunks.
22.11. EBC Interpreter Protocol 826Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.11.5 EFI_EBC_PROTOCOL.GetVersion()
Summary
Called to get the version of the interpreter.
Prototype
typedef
(*EFI_EBC_GET_VERSION) (
OUT UINT64 *Version
);
Version Pointer to where to store the returned version of the interpreter.
This function is called to get the version of the loaded EBC interpreter. The value and format of the returned version
is identical to that returned by the EBC BREAK 1 instruction.
EFI_INV ALID_PARAMETER Version pointer is NULL .
22.12 EBC Tools
22.12.1 EBC C Compiler
This section describes the responsibilities of the EBC C compiler. To fully specify these responsibilities requires that
the thunking mechanisms between EBC and native code be described.
22.12.2 C Coding Convention
The EBC C compiler supports only the C programming language. There is no support for C++, inline assembly,
ﬂoating point types/operations, or C calling conventions other than CDECL.
Pointer type in C is supported only as 64-bit pointer. The code should be 64-bit pointer ready (not assign pointers to
integers and vice versa).
The compiler does not support user-deﬁned sections through pragmas.
Global variables containing pointers that are initialized will be put in the uninitialized VarBss section and the compiler
will generate code to initialize these variables during load time. The code will be placed in an init text section. This
compiler-generated code will be executed before the actual image entry point is executed.
22.12. EBC Tools 827Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.12.3 EBC Interface Assembly Instructions
The EBC instruction set includes two forms of a CALL instruction that can be used to invoke external protocols. Their
assembly language formats are:
CALLEX Immed64
CALLEX32 {@}R1 {Immed32}
Both forms can be used to invoke external protocols at an absolute address speciﬁed by the immediate data and/or
register operand. The second form also supports jumping to code at a relative address. When one of these instructions
is executed, the interpreter is responsible for thunking arguments and then jumping to the destination address. When
the called function returns, code begins execution at the EBC instruction following the CALL instruction. The process
by which this happens is called thunking. Later sections describe this operation in detail.
22.12.4 Stack Maintenance and Argument Passing
There are several EBC assembly instructions that directly manipulate the stack contents and stack pointer. These
instructions operate on the EBC stack, not the interpreter stack. The instructions include the EBC PUSH ,POP ,
PUSHN , and POPN , and all forms of the MOV instructions.
These instructions must adjust the EBC stack pointer in the same manner as equivalent instructions of the native
instruction set. With this implementation, parameters pushed on the stack by an EBC driver can be accessed normally
for stack-based native code. If native code expects parameters in registers, then the interpreter thunking process must
transfer the arguments from EBC stack to the appropriate processor registers. The process would need to be reversed
when native code calls EBC.
22.12.5 Native to EBC Arguments Calling Convention
The calling convention for arguments passed to EBC functions follows the standard CDECL calling convention. The
arguments must be pushed as their native size. After the function arguments have been pushed on the stack, execution
is passed to the called EBC function. The overhead of thunking the function parameters depends on the standard
parameter passing convention for the host processor. The implementation of this functionality is left to the interpreter.
22.12.6 EBC to Native Arguments Calling Convention
When EBC makes function calls via function pointers, the EBC C compiler cannot determine whether the calls are
to native code or EBC. It therefore assumes that the calls are to native code, and emits the appropriate EBC CALL
instructions. To be compatible with calls to native code, the calling convention of EBC calling native code must follow
the parameter passing convention of the native processor. The EBC C compiler generates EBC instructions that push
all arguments on the stack. The interpreter is then responsible for performing the necessary thunking. The exact
implementation of this functionality is left to the interpreter.
22.12. EBC Tools 828Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.12.7 EBC to EBC Arguments Calling Convention
If the EBC C compiler is able to determine that a function call is to a local function, it can emit a standard EBC CALL
instruction. In this case, the function arguments are passed as described in the other sections of this speciﬁcation.
22.12.8 Function Returns
When EBC calls an external function, the thunking process includes setting up the host processor stack or registers such
that when the called function returns, execution is passed back to the EBC at the instruction following the call. The
implementation is left to the interpreter, but it must follow the standard function return process of the host processor.
Typically this will require the interpreter to push the return address on the stack or move it to a processor register prior
to calling the external function.
22.12.9 Function Return Values
EBC function return values of 8 bytes or less are returned in VM general-purpose register R7. Returning values larger
than 8 bytes on the stack is not supported. Instead, the caller or callee must allocate memory for the return value, and
the caller can pass a pointer to the callee, or the callee can return a pointer to the value in the standard return register
R7.
If an EBC function returns to native code, then the interpreter thunking process is responsible for transferring the
contents of R7 to an appropriate location such that the caller has access to the value using standard native code.
Typically the value will be transferred to a processor register. Conversely, if a native function returns to an EBC
function, the interpreter is responsible for transferring the return value from the native return memory or register
location into VM register R7.
22.12.10 Thunking
Thunking is the process by which transitions between execution of native and EBC are handled. The major issues that
must be addressed for thunking are the handling of function arguments, how the external function is invoked, and how
return values and function returns are handled. The following sections describe the thunking process for the possible
transitions.
22.12.10.1 Thunking EBC to Native Code
By deﬁnition, all external calls from within EBC are calls to native code. The EBC CALL instructions are used to
make these calls. A typical application for EBC calling native code would be a simple “Hello World” driver. For a
UEFI driver, the code could be written as shown below.
EFI_STATUS EfiMain (
IN EFI_SYSTEM_TABLE *ST
)
{
ST->ConOut->OutputString(ST->ConOut, L"Hello World!");
}
This C code, when compiled to EBC assembly, could result in two PUSHn instructions to push the parameters on
the stack, some code to get the absolute address of the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.OutputString()
function, then a CALLEX instruction to jump to native code. Typical pseudo assembly code for the function call could
be something like the following:
22.12. EBC Tools 829Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PUSHn _HelloString
PUSHn _ConOut
MOVnw R1, _OutputString
CALLEX64 R1
The interpreter is responsible for executing the PUSHn instructions to push the arguments on the EBC stack when
interpreting the PUSHn instructions. When the CALLEX instruction is encountered, it must thunk to external native
code. The exact thunking mechanism is native processor dependent. For example, a supported 32-bit thunking imple-

)
{
}
mentation could simply move the system stack pointer to point to the EBC stack, then perform a CALL to the absolute
address speciﬁed in VM register R1. However, the function calling convention for the Itanium processor family calls
for the ﬁrst 8 function arguments being passed in registers. Therefore, the Itanium processor family thunking mecha-
nism requires the arguments to be copied from the EBC stack into processor registers. Then a CALL can be performed
to jump to the absolute address in VM register R1. Note that since the interpreter is not aware of the number of argu-
ments to the function being called, the maximum amount of data may be copied from the EBC stack into processor
registers.
22.12.10.2 Thunking Native Code to EBC
An EBC driver may install protocols for use by other EBC drivers, or UEFI drivers or applications. These protocols
provide the mechanism by which external native code can call EBC. Typical C code to install a generic protocol is
shown below.
EFI_STATUS Foo(UINT32 Arg1, UINT32 Arg2);
MyProtInterface->Service1 = Foo;
Status = LibInstallProtocolInterfaces (&Handle, &MyProtGUID, MyProtInterface, NULL);
To support thunking native code to EBC, the EBC compiler resolves all EBC function pointers using one level of
indirection. In this way, the address of an EBC function actually becomes the address of a piece of native (thunk)
code that invokes the interpreter to execute the actual EBC function. As a result of this implementation, any time the
address of an EBC function is taken, the EBC C compiler must generate the following:
• A 64-bit function pointer data object that contains the actual address of the EBC function
• EBC initialization code that is executed before the image entry point that will execute EBC BREAK 5 instruc-
tions to create thunks for each function pointer data object
• Associated relocations for the above
So for the above code sample, the compiler must generate EBC initialization code similar to the following. This code
is executed prior to execution of the actual EBC driver’s entry point.
MOVqq R7, Foo_pointer ; get address of Foo pointer
BREAK 5 ; create a thunk forthe function
The BREAK instruction causes the interpreter to create native thunk code elsewhere in memory, and then modify the
memory location pointed to by R7 to point to the newly created thunk code for EBC function Foo. From within EBC,
when the address of Foo is taken, the address of the thunk is actually returned. So for the assignment of the protocol
Service1 above, the EBC C compiler will generate something like the following:
MOVqq R7, Foo_pointer ; get address of Foo function pointer
MOVqq R7, @R7; one level of indirection
22.12. EBC Tools 830Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
MOVn R6, _MyProtInterface->Service1 ; get address of variable
MOVqq@R6, R7 ; address of thunk to ->Service1
22.12.10.3 Thunking EBC to EBC
EBC can call EBC via function pointers or protocols. These two mechanisms are treated identically by the EBC C
compiler, and are performed using EBC CALL instructions. For EBC to call EBC, the EBC being called must have
provided the address of the function. As described above, the address is actually the address of native thunk code
for the actual EBC function. Therefore, when EBC calls EBC, the interpreter assumes native code is being called
so prepares function arguments accordingly, and then makes the call. The native thunk code assumes native code is
calling EBC, so will basically “undo” the preparation of function arguments, and then invoke the interpreter to execute
the actual EBC function of interest.
22.12.11 EBC Linker
New constants must be deﬁned for use by the linker in processing EBC images. For EBC images, the linker must set
the machine type in the PE ﬁle header accordingly to indicate that the image contains EBC.
#define IMAGE_FILE_MACHINE_EBC 0x0EBC
In addition, the linker must support EBC images with of the following subsystem types as set in a PE32+ optional
header:
#define IMAGE_SUBSYSTEM_EFI_APPLICATION 10
#define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
#define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12
For EFI EBC images and object ﬁles, the following relocation types must be supported:
// No relocations required
#define IMAGE_REL_EBC_ABSOLUTE 0x0000
// 32-bit address w/o image base
#define IMAGE_REL_EBC_ADDR32NB 0x0001
// 32-bit relative address from byte following relocs
#define IMAGE_REL_EBC_REL32 0x0002
// Section table index
#define IMAGE_REL_EBC_SECTION 0x0003
// Offset within section
#define IMAGE_REL_EBC_SECREL 0x0004
The ADDR32NB relocation is used internally to the linker when RV As are emitted. It also is used for version resources
which probably will not be used. The REL32 relocation is for PC relative addressing on code. The SECTION and
SECREL relocations are used for debug information.
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22.12.12 Image Loader
The EFI image loader is responsible for loading an executable image into memory and applying relocation infor-
mation so that an image can execute at the address in memory where it has been loaded prior to execution of the
image. For EBC images, the image loader must also invoke the interpreter protocol to create a thunk for the image
entry point and return the address of this thunk. After loading the image in this manner, the image can be exe-
cuted in the standard manner. To implement this functionality, only minor changes will be made to EFI service
EFI_BOOT_SERVICES.LoadImage() , and no changes should be made to EFI_BOOT_SERVICES.StartImage() .
After the image is unloaded, the EFI image load service must call the EBC EFI_BOOT_SERVICES.UnloadImage()
service to perform any cleanup to complete unloading of the image. Typically this will include freeing up any memory
allocated for thunks for the image during load and execution.
22.12.13 Debug Support
The interpreter must support debugging in an EFI environment per the EFI debug support protocol.
22.13 VM Exception Handling
This section lists the different types of exceptions that the VM may assert during execution of an EBC image. If a
debugger is attached to the EBC driver via the EFI debug support protocol, then the debugger should be able to capture
and identify the exception type. If a debugger is not attached, then depending on the severity of the exception, the
interpreter may do one of the following:
• Invoke the EFI ASSERT() macro, which will typically display an error message and halt the system
• Sit in a while(1) loop to hang the system
• Ignore the exception and continue execution of the image (minor exceptions only)
It is a platform policy decision as to the action taken in response to EBC exceptions. The following sections describe
the exceptions that may be generated by the VM.
22.13.1 Divide By 0 Exception
A divide-by-0 exception can occur for the EBC instructions DIV ,DIVU ,MOD , and MODU .
22.13.2 Debug Break Exception
A debug break exception occurs if the VM encounters a BREAK instruction with a break code of 3.
22.13.3 Invalid Opcode Exception
An invalid opcode exception will occur if the interpreter encounters a reserved opcode during execution.
22.13. VM Exception Handling 832Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
22.13.4 Stack Fault Exception
A stack fault exception can occur if the interpreter detects that function nesting within the interpreter or system inter-
rupts was sufﬁcient to potentially corrupt the EBC image’s stack contents. This exception could also occur if the EBC
driver attempts to adjust the stack pointer outside the range allocated to the driver.
22.13.5 Alignment Exception
An alignment exception can occur if the particular implementation of the interpreter does not support unaligned ac-
cesses to data or code. It may also occur if the stack pointer or instruction pointer becomes misaligned.
22.13.6 Instruction Encoding Exception
An instruction encoding exception can occur for the following:
• For some instructions, if an Operand 1 index is speciﬁed and Operand 1 is direct
• If an instruction encoding has reserved bits set to values other than 0
• If an instruction encoding has a ﬁeld set to a reserved value.
22.13.7 Bad Break Exception
A bad break exception occurs if the VM encounters a BREAK instruction with a break code of 0, or any other unrec-
ognized or unsupported break code.
22.13.8 Undeﬁned Exception
An undeﬁned exception can occur for other conditions detected by the VM. The cause of such an exception is depen-
dent on the VM implementation, but will most likely include internal VM faults.
22.14 Option ROM Formats
The new option ROM capability is designed to be a departure from the legacy method of formatting an option ROM.
PCI local bus add-in cards are the primary targets for this design although support for future bus types will be added

as necessary. EFI EBC drivers can be stored in option ROMs or on hard drives in an EFI system partition.
The new format deﬁned for the UEFI speciﬁcation is intended to coexist with legacy format PCI Expansion ROM
images. This provides the ability for IHVs to make a single option ROM binary that contains both legacy and new
format images at the same time. This is important for the ability to have single add-in card SKUs that can work in
a variety of systems both with and without native support for UEFI. Support for multiple image types in this way
provides a smooth migration path during the period before widespread adoption of UEFI drivers as the primary means
of support for software needed to accomplish add-in card operation in the pre-OS boot timeframe.
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22.14.1 EFI Drivers for PCI Add-in Cards
The location mechanism for UEFI drivers in PCI option ROM containers is described fully in
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL . Readers should refer to this section for complete
details of the scheme and associated data structures.
22.14.2 Non-PCI Bus Support
EFI expansion ROMs are not supported on any other bus besides PCI local bus in the current revision of the UEFI
This means that support for UEFI drivers in legacy ISA add-in card ROMs is explicitly excluded.
Support for UEFI drivers to be located on add-in card type devices for future bus designs other than PCI local bus will
be added to future revisions of the UEFI speciﬁcation. This support will depend upon the speciﬁcations that govern
such new bus designs with respect to the mechanisms deﬁned for support of driver code on devices.
22.14. Option ROM Formats 834CHAPTER
TWENTYTHREE
FIRMWARE UPDATE AND REPORTING
The UEFI Firmware Management Protocol provides an abstraction for device to provide ﬁrmware management sup-
port. The base requirements for managing device ﬁrmware images include identifying ﬁrmware image revision level
and programming the image into the device. The protocol for managing ﬁrmware provides the following services.
• Get the attributes of the current ﬁrmware image. Attributes include revision level.
• Get a copy of the current ﬁrmware image. As an example, this service could be used by a management applica-
tion to facilitate a ﬁrmware roll-back.
• Program the device with a ﬁrmware image supplied by the user.
• Label all the ﬁrmware images within a device with a single version.
When UEFI Firmware Management Protocol (FMP) instance is intended to perform the update of an option ROM
loaded from a PCI or PCI Express device, it is recommended that the FMP instance be attached to the handle with
EFI_LOADED_IMAGE_PROTOCOL for said Option ROM.
When the FMP instance is intended to update internal device ﬁrmware, or a combination of device ﬁrmware and
Option ROM, the FMP instance may instead be attached to the Controller handle of the device. However in the case
where multiple devices represented by multiple controller handles are served by the same ﬁrmware store, only a single
Controller handle should expose FMP. In all cases a speciﬁc updatable hardware ﬁrmware store must be represented
by exactly one FMP instance.
Care should be taken to ensure that the FMP instance reports current version data that accurately represents the actual
contents of the ﬁrmware store of the device exposing FMP, because in some cases the device driver currently operating
the device may have been loaded from another device or media.
23.1 Firmware Management Protocol
23.1.1 EFI_FIRMWARE_MANAGEMENT_PROTOCOL
Summary
Firmware Management application invokes this protocol to manage device ﬁrmware.
GUID
// {86C77A67-0B97-4633-A187-49104D0685C7}
#define EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID \
{ 0x86c77a67, 0xb97, 0x4633, \
{0xa1, 0x87, 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7 }}
Protocol
835Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct \_EFI_FIRMWARE_MANAGEMENT_PROTOCOL {
EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE_INFO GetImageInfo;
EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE GetImage;
EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_IMAGE SetImage;
EFI_FIRMWARE_MANAGEMENT_PROTOCOL_CHECK_IMAGE CheckImage;
EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_PACKAGE_INFO GetPackageInfo;
EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_PACKAGE_INFO SetPackageInfo;
} EFI_FIRMWARE_MANAGEMENT_PROTOCOL;
Members
GetImageInfo Returns information about the current ﬁrmware image(s) of the device.
GetImage Retrieves a copy of the current ﬁrmware image of the device.
SetImage Updates the device ﬁrmware image of the device.
CheckImage Checks if the ﬁrmware image is valid for the device.
GetPackageInfo Returns information about the current ﬁrmware package.
SetPackageInfo Updates information about the ﬁrmware package.
23.1.2 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo()
Summary
Returns information about the current ﬁrmware image(s) of the device.
Protocol
typedef
(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE_INFO) (
IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This,
IN OUT UINTN *ImageInfoSize,
IN OUT EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageInfo,
OUT UINT8 *DescriptorCount,
OUT UINT32 *PackageVersion,
OUT CHAR16 **PackageVersionName
) ;
This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
ImageInfoSize A pointer to the size, in bytes, of the ImageInfo buffer. On input, this is the size of the buffer allocated
by the caller. On output, it is the size of the buffer returned by the ﬁrmware if the buffer was large enough, or
the size of the buffer needed to contain the image(s) information if the buffer was too small.
ImageInfo A pointer to the buffer in which ﬁrmware places the current image(s) information. The information is
an array of EFI_FIRMWARE_IMAGE_DESCRIPTOR , see “Related Deﬁnitions”. May be NULL with a zero
ImageInfoSize in order to determine the size of the buffer needed.
EFI_FIRMWARE_IMAGE_DESCRIPTOR. See “Related Deﬁnitions”.
DescriptorCount A pointer to the location in which ﬁrmware returns the number of descriptors or ﬁrmware images
within this device.
23.1. Firmware Management Protocol 836Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_FIRMWARE_IMAGE_DESCRIPTOR.
PackageVersion A version number that represents all the ﬁrmware images in the device. The format is vendor speciﬁc
and new version must have a greater value than the old version. If PackageVersion is not supported, the value
is 0xFFFFFFFF. A value of 0xFFFFFFFE indicates that package version comparison is to be performed using
PackageVersionName . A value of 0xFFFFFFFD indicates that package version update is in progress.
PackageVersionName A pointer to a pointer to a null-terminated string representing the package version name. The
buffer is allocated by this function with AllocatePool(), and it is the caller’s responsibility to free it with a call
toFreePool() .
//*************************************************************
// EFI_FIRMWARE_IMAGE_DESCRIPTOR
UINT8 ImageIndex;
EFI_GUID ImageTypeId;
UINT64 ImageId
CHAR16 *ImageIdName;
CHAR16 *VersionName;
UINTN Size;
UINT64 AttributesSupported;
UINT64 AttributesSetting;
UINT64 Compatibilities;
//Introduced withDescriptorVersion 2+
UINT32 LowestSupportedImageVersion; \
//Introduced withDescriptorVersion 3+
UINT32 LastAttemptVersion;
UINT32 LastAttemptStatus;
UINT64 HardwareInstance;
//Introduced withDescriptorVersion 4+
EFI_FMP_DEP *Dependencies;
} EFI_FIRMWARE_IMAGE_DESCRIPTOR;
ImageIndex A unique number identifying the ﬁrmware image within the device. The number is between 1 and
DescriptorCount.
ImageTypeId A unique GUID identifying the ﬁrmware image type.
ImageId A unique number identifying the ﬁrmware image.
ImageIdName A pointer to a null-terminated string representing the ﬁrmware image name.
Version Identiﬁes the version of the device ﬁrmware. The format is vendor speciﬁc and new version must have a
greater value than an old version.
VersionName A pointer to a null-terminated string representing the ﬁrmware image version name.
Size Size of the image in bytes. If size=0, then only ImageIndex andImageTypeId are valid.
AttributesSupported Image attributes that are supported by this device. See “Image Attribute Deﬁnitions” for pos-
sible returned values of this parameter. A value of 1 indicates the attribute is supported and the current setting
value is indicated in AttributesSetting . A value of 0 indicates the attribute is not supported and the current setting
value in AttributesSetting is meaningless.

AttributesSetting Image attributes. See “Image Attribute Deﬁnitions” for possible returned values of this parameter.
23.1. Firmware Management Protocol 837Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Compatibilities Image compatibilities. See “Image Compatibility Deﬁnitions” for possible returned values of this
parameter.
LowestSupportedImageVersion Describes the lowest ImageDescriptor version that the device will accept. Only
present in version 2 or higher.
LastAttemptVersion Describes the version that was last attempted to update. If no update attempted the value will
be 0. If the update attempted was improperly formatted and no version number was available then the value will
be zero. Only present in version 3 or higher.
LastAttemptStatus Describes the status that was last attempted to update. If no update has been at-
tempted the value will be LAST_ATTEMPT_STATUS_SUCCESS . See “Related Deﬁnitions” in
EFI_SYSTEM_RESOURCE_TABLE for Last Attempt Status values. Only present in version 3 or higher.
HardwareInstance An optional number to identify the unique hardware instance within the system for devices that
may have multiple instances (Example: a plug in pci network card). This number must be unique within the
namespace of the ImageTypeId GUID and ImageIndex . For FMP instances that have multiple descriptors for
a single hardware instance, all descriptors must have the same HardwareInstance value. This number must be
consistent between boots and should be based on some sort of hardware identiﬁed unique id (serial number,
etc) whenever possible. If a hardware based number is not available the FMP provider may use some other
characteristic such as device path, bus/dev/function, slot num, etc for generating the HardwareInstance . For
implementations that will never have more than one instance a zero can be used. A zero means the FMP provider
is not able to determine a unique hardware instance number or a hardware instance number is not needed. Only
present in version 3 or higher.
Dependencies A pointer to an array of FMP depex expression op-codes that are terminated by an
EFI_FMP_DEP_END op-code.
// Image Attribute Definitions
#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE 0x0000000000000001
#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002
#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004
#define IMAGE_ATTRIBUTE_IN_USE 0x0000000000000008
#define IMAGE_ATTRIBUTE_UEFI_IMAGE 0x0000000000000010
#define IMAGE_ATTRIBUTE_DEPENDENCY 0x0000000000000020
The attribute IMAGE_ATTRIBUTE_DEPENDENCY indicates that there is an EFI_FIRMWARE_IMAGE_DEP section
associated with the image. See “Image Attribute - Dependency”.
// Image Attribute - Dependency
UINT8 Dependencies[];
} EFI_FIRMWARE_IMAGE_DEP;
Dependencies An array of FMP depex expression op-codes that are terminated by an END op-code (see related
deﬁnitions below.)
The attribute IMAGE_ATTRIBUTE_IMAGE_UPDATABLE indicates this device supports ﬁrmware image update.
The attribute IMAGE_ATTRIBUTE_RESET_REQUIRED indicates a reset of the device is required for the new
ﬁrmware image to take effect after a ﬁrmware update. The device is the device hosting the ﬁrmware image.
The attribute IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED indicates authentication is required to perform
the following image operations: GetImage(), SetImage(), andCheckImage() . See “Image Attribute - Authentication”.
23.1. Firmware Management Protocol 838Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The attribute I MAGE_ATTRIBUTE_IN_USE indicates the current state of the ﬁrmware image. This distinguishes
ﬁrmware images in a device that supports redundant images.
The attribute IMAGE_ATTRIBUTE_UEFI_IMAGE indicates that this image is an EFI compatible image.
// Image Compatibility Definitions
#define IMAGE_COMPATIBILITY_CHECK_SUPPORTED 0x0000000000000001
Values from 0x0000000000000002 thru 0x000000000000FFFF are reserved for future assignments.
Values from 0x0000000000010000 thru 0xFFFFFFFFFFFFFFFF are used by ﬁrmware vendor for compatibility check.
// Descriptor Version exposed by GetImageInfo() function
#define EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION 3
// Image Attribute - Authentication Required
} EFI_FIRMWARE_IMAGE_AUTHENTICATION;
MonotonicCount It is included in the signature of AuthInfo . It is used to ensure freshness/no replay. It is incremented
during each ﬁrmware image operation.
AuthInfo Provides the authorization for the ﬁrmware image operations.
If the image has dependencies associated with it, a signature across the image data will be created by including
the Monotonic Count followed by the dependency values. If there are no dependencies, the signature will be
across the image data and the Monotonic Count value.
Caller uses the private key that is associated with a public key that has been provisioned via the key
exchange. Because this is deﬁned as a signature, WIN_CERTIFICATE_UEFI_GUID. CertType must be
EFI_CERT_TYPE_PKCS7_GUID .
GetImageInfo() is the only required function. GetImage() ,SetImage(), CheckImage(), GetPackageInfo(), andSetPack-
ageInfo() shall return EFI_UNSUPPORTED if not supported by the driver.
A package can have one to many ﬁrmware images. The ﬁrmware images can have the same version naming or different
version naming. PackageVersion may be used as the representative version for all the ﬁrmware images. PackageVer-
sion can be obtained from GetPackageInfo(). PackageVersion is also available in GetImageInfo() asGetPackageInfo()
is optional. It also ensures the package version is in sync with the versions of the images within the package by
returning the package version and image version(s) in a single function call.
The value of ImageTypeID is implementation speciﬁc. This feature facilitates vendor to target a single ﬁrmware release
to cover multiple products within a product family. As an example, a vendor has an initial product A and then later
developed a product B that is of the same product family. Product A and product B will have the same ImageTypeID
to indicate ﬁrmware compatibility between the two products.
To determine image attributes, software must use both AttributesSupported andAttributesSetting . An attribute setting
inAttributesSetting is meaningless if the corresponding attribute is not supported in AttributesSupported .
Compatibilities are used to ensure the targeted ﬁrmware image supports the current hardware conﬁguration. Com-
patibilities are set based on the current hardware conﬁguration and ﬁrmware update policy should match the current
23.1. Firmware Management Protocol 839Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
settings to those supported by the new ﬁrmware image, and only permits update to proceed if the new ﬁrmware image
settings are equal or greater than the current hardware conﬁguration settings. For example, if this function returns
Compatibilities = 0x0000000000070001 and the new ﬁrmware image supports settings=0x0000000000030001, then
the update policy should block the ﬁrmware update and notify the user that updating the hardware with the new
ﬁrmware image may render the hardware inoperable. This situation usually occurs when updating the hardware with
an older version of ﬁrmware.
The authentication support leverages the authentication scheme employed in variable authentication. Please reference
EFI_VARIABLE_AUTHENTICATION in the “Variable Services” section of “Services - Runtime Services” chapter.
IfIMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED is supported and clear, then authentication is not required
to perform the ﬁrmware image operations. In ﬁrmware image operations, the image pointer points to the start of the
ﬁrmware image and the image size is the ﬁrmware image.
Fig. 23.1: Firmware Image with no Authentication Support
IfIMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED is supported and set, then authentication is required to
perform the ﬁrmware image operations. In ﬁrmware image operations, the image pointer points to the start of the
authentication data and the image size is the size of the authentication data and the size of the ﬁrmware image.
Fig. 23.2: Firmware Image with Authentication Support
IfIMAGE_ATTRIBUTE_DEPENDENCY is supported and set, then there are dependencies associated with the image.

See the Dependency Expression Instruction Set for details on the format of the dependency op-codes and how they are
to be used.
23.1. Firmware Management Protocol 840Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 23.3: Firmware Image with Dependency/AuthenticationSupport
EFI_SUCCESS The image information was successfully returned.
EFI_BUFFER_TOO_SMALL TheImageInfo buffer was too small. The current buffer size needed to hold
the image(s) information is returned in ImageInfoSize.
EFI_INV ALID_PARAMETER ImageInfoSize is not too small and ImageInfo is NULL.
EFI_INV ALID_PARAMETER ImageInfoSize is non-zero and DescriptorVersion isNULL .
EFI_INV ALID_PARAMETER ImageInfoSize is non-zero and DescriptorCount isNULL .
EFI_INV ALID_PARAMETER ImageInfoSize is non-zero and DescriptorSize isNULL .
EFI_INV ALID_PARAMETER ImageInfoSize is non-zero and PackageVersion isNULL .
EFI_INV ALID_PARAMETER ImageInfoSize is non-zero and PackageVersionName isNULL .
EFI_DEVICE_ERROR Valid information could not be returned. Possible corrupted image.
23.1.3 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImage()
Summary
Retrieves a copy of the current ﬁrmware image of the device.
Protocol
typedef
(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE) (
IN UINT8 ImageIndex,
OUT VOID *Image,
IN OUT UINTN *ImageSize
) ;
ImageIndex A unique number identifying the ﬁrmware image(s) within the device. The number is between 1 and
DescriptorCount .
Image Points to the buffer where the current image is copied to. May be NULL with a zero ImageSize in order to
determine the size of the buffer needed.
ImageSize On entry, points to the size of the buffer pointed to by Image, in bytes. On return, points to the length of
the image, in bytes.
None
This function allows a copy of the current ﬁrmware image to be created and saved. The saved copy could later been
used, for example, in ﬁrmware image recovery or rollback.
Note: Not all implementations of GetImage() will return what can be sent to SetImage(). Image validity can be
veriﬁed by using the CheckImage() API to verify if the returned Image can be used for SetImage().
Status Codes Returned23.1. Firmware Management Protocol 841Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The current image was successfully copied to the buffer.
EFI_BUFFER_TOO_SMALL The buffer speciﬁed by ImageSize is too small to hold the image. The cur-
rent buffer size needed to hold the image is returned in ImageSize .
EFI_INV ALID_PARAMETER TheImageSize is not too small and Image is NULL
EFI_NOT_FOUND The current image is not copied to the buffer.
EFI_SECURITY_VIOLATION The operation could not be completed due to an image corruption. If the
image is able to be read, the Image buffer will be updated with the retrieved
image contents.
EFI_DEVICE_ERROR The image could not be read.
23.1.4 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage()
Summary
Updates the ﬁrmware image of the device.
Protocol
typedef
(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_IMAGE) (
IN CONST VOID *Image,
IN UINTN ImageSize,
IN CONST VOID *VendorCode,
IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress,
OUT CHAR16 **AbortReason
) ;
Image Points to the new image.
ImageSize Size of the new image in bytes.
VendorCode This enables vendor to implement vendor-speciﬁc ﬁrmware image update policy. Null indicates the
caller did not specify the policy or use the default policy.
Progress A function used by the driver to report the progress of the ﬁrmware update.
AbortReason A pointer to a pointer to a null-terminated string providing more details for the aborted operation. The
typedef
(EFIAPI *EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS) (
IN UINTN Completion
) ;
23.1. Firmware Management Protocol 842Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Completion A value between 1 and 100 indicating the current completion progress of the ﬁrmware update. Comple-
tion progress is reported as from 1 to 100 percent. A value of 0 is used by the driver to indicate that progress
reporting is not supported.
OnEFI_SUCCESS, SetImage() continues to do the callback if supported. On NOT EFI_SUCCESS, SetImage() dis-
continues the callback and completes the update and returns.
This function updates the hardware with the new ﬁrmware image.
This function returns EFI_UNSUPPORTED if the ﬁrmware image is not updatable.
If the ﬁrmware image is updatable, the function should perform the following minimal validations before proceeding
to do the ﬁrmware image update.
• Validate the image authentication if image has attribute IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED .
The function returns EFI_SECURITY_VIOLATION if the validation fails.
• Validate the image is a supported image for this device. The function returns EFI_ABORTED if the image is
unsupported. The function can optionally provide more detailed information on why the image is not a supported
image.
• Validate the data from VendorCode if not null. Image validation must be performed before VendorCode data
validation. VendorCode data is ignored or considered invalid if image validation failed. The function returns
EFI_ABORTED if the data is invalid.
VendorCode enables vendor to implement vendor-speciﬁc ﬁrmware image update policy. Null if the caller did not
specify the policy or use the default policy. As an example, vendor can implement a policy to allow an option to
force a ﬁrmware image update when the abort reason is due to the new ﬁrmware image version is older than the
current ﬁrmware image version or bad image checksum. Sensitive operations such as those wiping the entire ﬁrmware
image and render the device to be non-functional should be encoded in the image itself rather than passed with the
VendorCode .
AbortReason enables vendor to have the option to provide a more detailed description of the abort reason to the caller.
EFI_SUCCESS The device was successfully updated with the new image.
EFI_ABORTED The operation is aborted.
EFI_INV ALID_PARAMETER TheImage was NULL.
EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
23.1.5 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.CheckImage()
Summary
Checks if the ﬁrmware image is valid for the device.
Protocol
typedef
(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_CHECK_IMAGE) (
23.1. Firmware Management Protocol 843Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
OUT UINT32 *ImageUpdatable
) ;
ImageUpdatable Indicates if the new image is valid for update. It also provides, if available, additional information
if the image is invalid. See “Related Deﬁnitions”.
//**************************************************************
// ImageUpdatable Definitions
#define IMAGE_UPDATABLE_VALID 0x0000000000000001
#define IMAGE_UPDATABLE_INVALID 0x0000000000000002
#define IMAGE_UPDATABLE_INVALID_TYPE 0x0000000000000004
#define IMAGE_UPDATABLE_INVALID_OLD 0x0000000000000008
#define IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE \ 0x0000000000000010
IMAGE_UPDATABLE_V ALID indicates SetImage() will accept the new image and update the device with the new
image.The version of the new image could be higher or lower than the current image. SetImage VendorCode i s
optional but can be used for vendor speciﬁc action.
IMAGE_UPDATABLE_INV ALID indicates SetImage() will reject the new image. No additional information is
provided for the rejection.
IMAGE_UPDATABLE_INV ALID_TYPE indicates SetImage() will reject the new image. The rejection is due to
the new image is not a ﬁrmware image recognized for this device.
IMAGE_UPDATABLE_INV ALID_OLD indicates SetImage() will reject the new image. The rejection is due to the
new image version is older than the current ﬁrmware image version in the device. The device ﬁrmware update

policy does not support ﬁrmware version downgrade.
IMAGE_UPDATABLE_V ALID_WITH_VENDOR_CODE indicates SetImage() will accept and update the new
image only if a correct VendorCode is provided or else image would be rejected and SetImage will return
appropriate error.
This function allows ﬁrmware update application to validate the ﬁrmware image without invoking the SetImage() ﬁrst.
Please see SetImage() for the type of image validations performed.
EFI_SUCCESS The image was successfully checked.
23.1. Firmware Management Protocol 844Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.1.6 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetPackageInfo()
Summary
Returns information about the ﬁrmware package.
Protocol
typedef
(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_PACKAGE_INFO) (
IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL * *This,
OUT CHAR16 **PackageVersionName,
OUT UINT32 *PackageVersionNameMaxLen
OUT UINT64 *AttributesSupported,
OUT UINT64 *AttributesSetting
) ;
PackageVersionNameMaxLen The maximum length of package version name if device supports update of package
version name. A value of 0 indicates the device does not support update of package version name. Length is the
number of Unicode characters, including the terminating null character.
AttributesSupported Package attributes that are supported by this device. See “Package Attribute Deﬁnitions” for
possible returned values of this parameter. A value of 1 indicates the attribute is supported and the current setting
value is indicated in AttributesSetting. A value of 0 indicates the attribute is not supported and the current setting
AttributesSetting Package attributes. See “Package Attribute Deﬁnitions” for possible returned values of this param-
eter.
// Package Attribute Definitions
#define PACKAGE_ATTRIBUTE_VERSION_UPDATABLE 0x0000000000000001
#define PACKAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002
#define PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004
The attribute PACKAGE_ATTRIBUTE_VERSION_UPDATABLE indicates this device supports the update of the
ﬁrmware package version.
The attribute PACKAGE_ATTRIBUTE_RESET_REQUIRED indicates a reset of the device is required for the new
package info to take effect after an update.
The attribute PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED indicates authentication is required to up-
date the package info.
23.1. Firmware Management Protocol 845Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function returns package information.
EFI_SUCCESS The package information was successfully returned.
23.1.7 EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetPackageInfo()
Summary
Updates information about the ﬁrmware package.
Protocol
typedef
(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_PACKAGE_INFO) (
IN UINT32 PackageVersion,
IN CONST CHAR16 *PackageVersionName
) ;
Image Points to the authentication image. Null if authentication is not required.
ImageSize Size of the authentication image in bytes. 0 if authentication is not required.
caller did not specify this policy or use the default policy.
PackageVersion The new package version.
PackageVersionName A pointer to the new null-terminated Unicode string representing the package version name.
The string length is equal to or less than the value returned in PackageVersionNameMaxLen .
This function updates package information.
This function returns EFI_UNSUPPORTED if the package information is not updatable.
VendorCode enables vendor to implement vendor-speciﬁc package information update policy. Null if the caller did
not specify this policy or use the default policy.
EFI_SUCCESS The device was successfully updated with the new package information
EFI_INV ALID_PARAMETER ThePackageVersionName length is longer than the value returned in Pack-
ageVersionNameMaxLen .
23.1. Firmware Management Protocol 846Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.2 Dependency Expression Instruction Set
The following topics describe each of the ﬁrmware management protocol dependency expression (depex) opcodes
in detail. Information includes a description of the instruction functionality, binary encoding, and any limitations or
unique behaviors of the instruction.
Several of the opcodes require a GUID operand. The GUID operand is a 16-byte value that
matches the type EFI_GUID that is described in Chapter 2 of the UEFI 2.0 speciﬁcation. These
GUIDs represent the EFI_FIRMWARE_IMAGE_DESCRIPTOR .ImageTypeId that are exposed by an
EFI_FIRMWARE_MANAGE_PROTOCOL instance. A dependency expression is a packed byte stream of op-
codes and operands. As a result, some of the GUID operands will not be aligned on natural boundaries. Care must be
taken on processor architectures that do allow unaligned accesses.
The dependency expression is stored in a packed byte stream using postﬁx notation. As a dependency expression is
evaluated, the operands are pushed onto a stack. Operands are popped off the stack to perform an operation. After
the last operation is performed, the value on the top of the stack represents the evaluation of the entire dependency
expression. If a push operation causes a stack overﬂow, then the entire dependency expression evaluates to FALSE .
If a pop operation causes a stack underﬂow, then the entire dependency expression evaluates to FALSE . Reasonable
implementations of a dependency expression evaluator should not make arbitrary assumptions about the maximum
stack size it will support. Instead, it should be designed to grow the dependency expression stack as required. In
addition, FMP images that contain dependency expressions should make an effort to keep their dependency expressions
as small as possible to help reduce the size of the FMP image.
All opcodes are 8-bit values, and if an invalid opcode is encountered, then the entire dependency expression evaluates
toFALSE .
When the dependency expression is being evaluated and a GUID speciﬁed cannot be found, then the result of the
conditional operation evaluates to FALSE .
If, when evaluating two popped values from the stack, it is determined that they are of different types (e.g. BOOLEAN
value and 32-bit value), then the entire dependency expression evaluates to FALSE .
If an END opcode is not present in a dependency expression, then the entire dependency expression evaluates to
FALSE .
The ﬁnal evaluation of the dependency expression results in either a TRUE orFALSE result.
Table 23.4: Dependency Expression Opcode Summary
Opcode Description
0x00 Push FMP GUID (1 op-code + 16 bytes)
0x01 Push 32-bit version value
0x02 Declare NULL-terminated string (Human-readable Version)
0x03 AND – Pop 2 BOOLEAN values and Push TRUE if both are TRUE .
0x04 OR – Pop 2 BOOLEAN values and Push TRUE if either are TRUE .
0x05 NOT – Pop BOOLEAN value Push NOT of BOOLEAN value.
0x06 Push TRUE
0x07 Push FALSE
0x08 EQ – Pop 2 32-bit version values and push TRUE if equal.
0x09 GT - Pop 2 32-bit version values and push TRUE if ﬁrst value is greater than the second.
0x0A GTE - Pop 2 32-bit version values and push TRUE if ﬁrst value is greater than or equal to the second.
0x0B LT - Pop 2 32-bit version values and push TRUE if ﬁrst value is less than the second.

FALSE .
0x0C LTE - Pop 2 32-bit version values and push TRUE if ﬁrst value is less than or equal to the second.
0x0D END
0x0E DECLARE_LENGTH - declares a 32-bit byte length of the entire dependency expression
23.2. Dependency Expression Instruction Set 847Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.2.1 PUSH_GUID
Syntax
PUSH_GUID <FMP GUID>
Pushes the GUID value onto the stack. This GUID should be exposed by an
EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance. The GUID should match one of the
EFI_FIRMWARE_IMAGE_DESCRIPTOR . ImageTypeId values exposed through the GetImageInfo() function.
Operation
1. Search through all instances of the EFI_FIRMWARE_MANAGEMENT_PROTOCOL .
a - In each instance, use the GetImageInfo() function to retrieve the ImageInfo->ImageTypeId value and ensure
it matches the GUID speciﬁed in the op-code.
b - If it doesn’t match the GUID and no other instances match either, POP all values from the stack and PUSH
FALSE onto the stack when evaluating a conditional operation involving the missing GUID.
2. Having found the matching EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance, use the GetImageInfo()
function and push the ImageInfo->Version value onto the stack.
Table 23.5: PUSH_GUID Instruction Encoding
0 0x00
1..16 A 16-byte GUID that represents an ImageTypeId in an FMP instance. The format is the same
as type EFI_GUID .
None.
23.2.2 PUSH_VERSION
Syntax
PUSH_VERSION <32-bit Version>
Pushes the 32-bit version value to compare against onto the stack. This value will be used to compare against Version
values exposed through the GetImageInfo() function.
Table 23.6: PUSH_VERSION Instruction Encoding
0 0x01
1..4 A 32-bit version to compare against.
None.
23.2. Dependency Expression Instruction Set 848Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.2.3 DECLARE_VERSION_NAME
Syntax
DECLARE_VERSION_NAME <NULL-terminated string>
Declares an optional null-terminated version string that is the equivalent of the VersionName in the
EFI_FIRMWARE_MANAGEMENT_DESCRIPTOR . Due to the OEM/IHV-speciﬁc format of version strings, this null-
terminated string will not be used for purposes of comparison. Only the 32-bit integer values will be used for compar-
isons.
Table 23.7: DECLARE_VERSION_NAME Instruction Encoding
0 0x02
1..n A null-terminated UNICODE string.
None.
23.2.4 AND
Syntax
AND
Pops two Boolean operands off the stack, performs a Boolean AND operation between the two operands, and pushes
the result back onto the stack.
Operation
Operand1 <= POP Boolean stack element
Operand2 <= POP Boolean stack element
Result <= Operand1 AND Operand2
PUSH Result
Table 23.8: AND Instruction Encoding
0 0x03
None.
23.2. Dependency Expression Instruction Set 849Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.2.5 OR
Syntax
OR
Pops two Boolean operands off the stack, performs a Boolean OR operation between the two operands, and pushes the
result back onto the stack.
Operation
Result <= Operand1 OR Operand2
Table 23.9: OR Instruction Encoding
0 0x04
None.
23.2.6 NOT
Syntax
NOT
Pops a Boolean operand off the stack, performs a Boolean NOT operation on the operand, and pushes the result back
onto the stack.
Operation
Operand <= POP Boolean stack element
Result <= NOT Operand PUSH Result
Table 23.10: NOT Instruction Encoding
0 0x05
None.
23.2. Dependency Expression Instruction Set 850Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.2.7 TRUE
Syntax
**TRUE**
Pushes a Boolean TRUE onto the stack.
Operation
PUSH**TRUE**
Table 23.11: TRUE Instruction Encoding
0 0x06
None.
23.2.8 FALSE
Syntax
**FALSE**
Pushes a Boolean FALSE onto the stack.
Operation
PUSH**FALSE**
Table 23.12: FALSE Instruction Encoding
0 0x07
None.
23.2.9 EQ
Syntax
EQ
Pops two 32-bit operands off the stack, performs a Boolean equals comparison operation between the two operands,
and pushes the result back onto the stack.
Operation
23.2. Dependency Expression Instruction Set 851Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Operand1 ? POP 32-bit stack element
Operand2 ? POP 32-bit stack element
Result ? Operand1 EQ Operand2
Table 23.13: EQ Instruction Encoding
0 0x08
None.
23.2.10 GT
Syntax
GT
Pops two 32-bit operands off the stack, performs a Boolean greater-than comparison operation between the two
operands, and pushes the result back onto the stack.
Operation
Operand1 <= POP 32-bit stack element
Operand2 <= POP 32-bit stack element
Result <= Operand1 GT Operand2
Table 23.14: GT Instruction Encoding
0 0x09
None.
23.2.11 GTE
Syntax
GTE
Pops two 32-bit operands off the stack, performs a Boolean greater-than-or-equal comparison operation between the
two operands, and pushes the result back onto the stack.
Operation
23.2. Dependency Expression Instruction Set 852Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Result ? Operand1 GTE Operand2
Table 23.15: GTE Instruction Encoding
0 0x0A
None.
23.2.12 LT
Syntax
LT
Pops two 32-bit operands off the stack, performs a Boolean less-than comparison operation between the two operands,
Operation
Result ? Operand1 LT Operand2
Table 23.16: LT Instruction Encoding
0 0x0B
None.
23.2.13 LTE
Syntax
LTE
Pops two 32-bit operands off the stack, performs a Boolean less-than-or-equal comparison operation between the two
Operation
23.2. Dependency Expression Instruction Set 853Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Result ? Operand1 LTE Operand2
Table 23.17: LTE Instruction Encoding
0 0x0C
None.
23.2.14 END
Syntax
END
Pops the ﬁnal result of the dependency expression evaluation off the stack and exits the dependency expression evalu-
ator.
Operation
POP Result
RETURN Result
Table 23.18: END Instruction Encoding
0 0x0D
This opcode must be the last one in a dependency expression.
23.2.15 DECLARE_LENGTH
Syntax
DECLARE_LENGTH <32-bit Length>
Declares an 32-bit byte length of the entire dependency expression.
23.2. Dependency Expression Instruction Set 854Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 23.19: DECLARE_LENGTH Instruction Encoding
0
0X0e 1..4
A 32-bit byte length for the entire dependency expression.
This opcode must be the ﬁrst one in a dependency expression.
23.3 Delivering Capsules Containing Updates toFirmware Manage-
ment Protocol
Summary
This section deﬁnes a method for delivery of a Firmware Management Protocol deﬁned update using the UpdateCap-
sule runtime API.
23.3.1 EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID
GUID
// {6DCBD5ED-E82D-4C44-BDA1-7194199AD92A}
#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \
{0x6dcbd5ed, 0xe82d, 0x4c44, \
{0xbd, 0xa1, 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a }}
This GUID is used in the CapsuleGuid ﬁeld of EFI_CAPSULE_HEADER struct within a capsule constructed accord-
ing to the deﬁnitions of section Capsule Deﬁnition . Use of this GUID indicates a capsule with body conforming to the
additional structure deﬁned in DEFINED FIRMWARE MANAGEMENT PROTOCOL DATA CAPSULE STRUCTURE
.
When delivered to platform ﬁrmware QueryCapsuleCapabilities() the capsule will be examined according to the struc-
ture deﬁned in DEFINED FIRMWARE MANAGEMENT PROTOCOL DATA CAPSULE STRUCTURE . and if it is
possible for the platform to process EFI_SUCCESS will be returned.
When delivered to platform ﬁrmware UpdateCapsule() the capsule will be examined according to the structure deﬁned
inDEFINED FIRMWARE MANAGEMENT PROTOCOL DATA CAPSULE STRUCTURE . and if it is possible for the
platform to process the update will be processed.
By deﬁnition Firmware Management protocol services are not available in EFI runtime and depending upon plat-

.
form capabilities, EFI runtime delivery of this capsule may not be supported and may return an error when deliv-
ered in EFI runtime with CAPSULE_FLAGS_PERSIST_ACROSS_RESET bit deﬁned. However any platform sup-
porting this capability is required to accept this form of capsule in Boot Services, including optional use of CAP-
SULE_FLAGS_PERSIST_ACROSS_RESET bit.
23.3. Delivering Capsules Containing Updates toFirmware Management Protocol 855Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.3.2 DEFINED FIRMWARE MANAGEMENT PROTOCOL DATA CAPSULE STRUC-
TURE
Structure of the Capsule Body
Generic EFI Capsule Body is deﬁned in Capsule Deﬁnition . When an EFI Capsule is identi-
ﬁed by EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID, the internal structure of the capsule _
_FIRMWARE_MANAGEMENT_CAPSULE_HEADER followed by optional EFI drivers to be loaded by the platform
and optional binary payload items to be processed and passed to Firmware Management Protocol image update func-
tion. Each binary payload item is preceded by EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER .
Internal capsule structure diagram follows.
Fig. 23.4: Optional Scatter-Gather Construction of Capsule Submitted to Update Capsule()
UINT16 EmbeddedDriverCount;
UINT16 PayloadItemCount;
// UINT64 ItemOffsetList[];
} EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER;
Version Version of the structure, initially 0x00000001.
EmbeddedDriverCount The number of drivers included in the capsule and the number of corresponding offsets
stored in ItemOffsetList array. This ﬁeld may be zero in the case where no driver is required.
23.3. Delivering Capsules Containing Updates toFirmware Management Protocol 856Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 23.5: Capsule Header and Firmware Management Capsule Header
Fig. 23.6: Firmware Management and Firmware Image Management headers
23.3. Delivering Capsules Containing Updates toFirmware Management Protocol 857Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PayloadItemCount The number of payload items included in the capsule and the number of corresponding offsets
stored in the ItemOffsetList array. This ﬁeld may be zero in the case where no binary payload object is required
to accomplish the update.
ItemOffsetList Variable length array of dimension [ EmbeddedDriverCount +PayloadItemCount ] containing offsets
of each of the drivers and payload items contained within the capsule. The offsets of the items are calculated
relative to the base address of the EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER struct. Offset may
indicate structure begins on any byte boundary. Offsets in the array must be sorted in ascending order with all
drivers preceding all binary payload elements.
UINT8 reserved_bytes[3];
UINT32 UpdateImageSize;
UINT32 UpdateVendorCodeSize;
UINT64 UpdateHardwareInstance; //Introduced inv2
UINT64 ImageCapsuleSupport; //Introduced inv3
} EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER;
Version Version of the structure, initially 0x00000003 .
UpdateImageTypeId Used to identify device ﬁrmware targeted by this update. This guid is matched by system
ﬁrmware against ImageTypeId ﬁeld within a EFI_FIRMWARE_IMAGE_DESCRIPTOR returned by an instance
ofEFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo() in the system.
UpdateImageIndex Passed as ImageIndex in call to EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage()
UpdateImageSize Size of the binary update image which immediately follows this structure. Passed as ImageSize
toEFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage() . This size may or may not include Firmware
Image Authentication information.
UpdateVendorCodeSize Size of the VendorCode bytes which optionally immediately follow bi-
nary update image in the capsule. Pointer to these bytes passed in VendorCode to
EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage() . If UpdateVendorCodeSize is zero, then
VendorCode is null in SetImage() call.
UpdateHardwareInstance The HardwareInstance to target with this update. If value is zero it means match all
HardwareInstances . This ﬁeld allows update software to target only a single device in cases where there are more
than one device with the same ImageTypeId GUID. This header is outside the signed data of the Authentication
Info structure and therefore can be modiﬁed without changing the Auth data.
ImageCapsuleSupport A 64-bit bitmask that determines what sections are added to the payload.
#define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001
#define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002
TheEFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER structure is located at the lowest offset within the body
of the capsule identiﬁed by EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID . The structure is variable length
with the number of element offsets within of the ItemOffsetList array determined by the count of drivers within the
capsule plus the count of binary payload elements. It is expected that drivers whose presence is indicated by non-zero
EmbeddedDriverCount will be used to supply an implementation of EFI_FIRMWARE_MANAGEMENT_PROTOCOL
for devices that lack said protocol within the image to be updated.
Each payload item contained within the capsule body is preceded by a
EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER struct used to provide infor-
23.3. Delivering Capsules Containing Updates toFirmware Management Protocol 858Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
mation required to prepare the payload item as an image for delivery to a instance of
EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage() function.
NOTE :[Caution] The capsule identiﬁed by EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID uses packed
structures and structure ﬁelds may not be naturally aligned within the capsule buffer as delivered. Drivers and binary
payload elements may start on byte boundary with no padding. Processing ﬁrmware may need to copy content elements
during capsule unpacking in order to achieve any required natural alignment.
23.3.3 Firmware Processing of the Capsule Identiﬁed by
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID
1. Capsule is presented to system ﬁrmware via call to UpdateCapsule() or using mass storage delivery procedure
ofDelivery of Capsules via ﬁle on Mass Storage Device . The capsule must be constructed to consist of a
single EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER structure with the 0 or more drivers and 0 or
more binary payload items. However a capsule in which driver count and payload count are both zero is not
processed.
2. Capsule is recognized by EFI_CAPSULE_HEADER member CapsuleGuid
equal to EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID . CAP-
SULE_FLAGS_POPULATE_SYSTEM_TABLE ﬂag must be 0.
3. If system is not in boot services and platform does not support persistence of capsule across reset when initiated
within EFI Runtime, EFI_OUT_OF_RESOURCES error is returned.
4. If device requires hardware reset to unlock ﬂash write protection, CAP-
SULE_FLAGS_PERSIST_ACROSS_RESET and optionally CAPSULE_FLAGS_INITIATE_RESET should
be set to 1 in the EFI_CAPSULE_HEADER .
5. When reset is requested using CAPSULE_FLAGS_PERSIST_ACROSS_RESET, the capsule is processed in Boot
Services, before the EFI_EVENT_GROUP_READY_TO_BOOT event.
6. All scatter-gather fragmentation is removed by the platform ﬁrmware and the capsule is processed as a contigu-
ous buffer.
7. Examining EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER, ifEmbeddedDriverCount is non-zero,
for each of the included drivers up to indicated count, the portion of the capsule body starting at the offset
indicated by ItemOffsetList[n] and continuing for a size encompassing all bytes up to the next element’s offset
stored in ItemOffsetList[n+1] or the end of the capsule, will be copied to a buffer. The driver contained within
the capsule body may not be naturally aligned and the exact driver size in bytes should be respected to ensure
successful security validation. In the case where a driver is last element in the ItemOffsetList array, the driver size
may be calculated by reference to body size as calculated from CapsuleImageSize inEFI_CAPSULE_HEADER
8. Each extracted driver is placed into a buffer and passed to LoadImage() . The driver image passed to LoadImage()
must successfully pass all image format, platform type, and security checks including those related to UEFI
secure boot, if enabled on the platform. After LoadImage() returns the processing of the capsule is continued
with next driver if present until all drivers have been passed to LoadImage() . The driver being installed must
check for matching hardware and instantiate any required protocols during call to EFI_IMAGE_ENTRY_POINT .
In case where matching hardware is not found the driver should exit with error. In case where capsule creator

has preference as to which of several included drivers to be made resident, later drivers in the capsule should
conﬁrm earlier driver successfully loaded and then exit with load error.
9. After driver processing is complete the platform ﬁrmware examines PayloadItemCount, and if
zero the capsule processing is complete. Otherwise platform ﬁrmware sequentially locates each
EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER found within the capsule and processes ac-
cording to steps 10-14.
10. For all instances of EFI_FIRMWARE_MANAGEMENT_PROTOCOL in the system, GetImageInfo() is called to
return arrays of EFI_FIRMWARE_IMAGE_DESCRIPTOR structures.
23.3. Delivering Capsules Containing Updates toFirmware Management Protocol 859Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11. Find the matching FMP instance(s):
a – If the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER is version 1 or it is ver-
sion 2 with UpdateHardwareInstance set to 0, then system ﬁrmware will use only the ImageTypeId
to determine a match. For each instance of EFI_FIRMWARE_MANAGEMENT_PROTOCOL that re-
turns a EFI_FIRMWARE_IMAGE_DESCRIPTOR containing an ImageTypeId GUID that matches the Up-
dateImageTypeId GUID within EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER, the system
ﬁrmware will call SetImage() function within that instance. In some cases there may be more than one instance
of matching EFI_FIRMWARE_MANAGEMENT_PROTOCOL when multiple matching devices are installed in
the system and all instances will be checked for GUID match and SetImage() call if match is successful.
b – If the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER is version 2 and contains a non-
zero value in the UpdateHardwareInstance ﬁeld, then system ﬁrmware will use both ImageTypeId andHard-
wareInstance to determine a match. For the instance of EFI_FIRMWARE_MANAGEMENT_PROTOCOL
that returns a EFI_FIRMWARE_IMAGE_DESCRIPTOR containing an ImageTypeId GUID that matches
theUpdateImageTypeId GUID and a HardwareInstance matching the UpdateHardwareInstance within
EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER, the system ﬁrmware will call the SetIm-
age() function within that instance. There will never be more than one instance since the ImageId must be
unique.
12. In the situation where platform conﬁguration or policy prohibits the processing of a capsule or individual FMP
payload, the error EFI_NOT_READY will be returned in capsule result variable CapsuleStatus ﬁeld. Other-
wise SetImage() parameters are constructed using the UpdateImageIndex, UpdateImageSize andUpdateVendor-
CodeSize ﬁelds within EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER . In the case of cap-
sule containing multiple payloads, or a payload matching multiple FMP instances, a separate Capsule Result
Variable will be created with the results of each call to SetImage() . If any call to SetImage() selected per above
matching algorithm returns an error, the processing of additional FMP instances or payload items in that capsule
will be skipped and EFI_ABORTED returned in Capsule Result Variable for each potential call to SetImage()
that was skipped.
13.SetImage() performs any required image authentication as described in that functions deﬁnition within this
chapter.
14. Note: if multiple separate component updates including multiple ImageIndex values are required then additional
EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER structures and image binaries are included
within the capsule.
15. After all items in the capsule are processed the system is restarted by the platform ﬁrmware.
23.4 EFI System Resource Table
23.4.1 EFI_SYSTEM_RESOURCE_TABLE
Summary
The EFI System Resource Table (ESRT) provides an optional mechanism for identifying device and system ﬁrmware
resources for the purposes of targeting ﬁrmware updates to those resources. Each entry in the ESRT describes a
device or system ﬁrmware resource that canbe targeted by a ﬁrmware capsule update. Each entry in the ESRT
will also be used to report status of the last attempted update. See EFI Conﬁguration Table & Properties Table for
description of how to publish ESRT using EFI_CONFIGURATION_TABLE . The ESRT shall be stored in memory of
type EﬁBootServicesData . See Update Capsule andDelivery of Capsules via ﬁle on Mass Storage Device for details
on delivery of updates to devices listed in ESRT.
GUID
23.4. EFI System Resource Table 860Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_SYSTEM_RESOURCE_TABLE_GUID \
{ 0xb122a263, 0x3661, 0x4f68,\
{ 0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 }}
Table Structure
UINT32 FwResourceCount;
UINT32 FwResourceCountMax;
UINT64 FwResourceVersion;
//EFI_SYSTEM_RESOURCE_ENTRY Entries[];
} EFI_SYSTEM_RESOURCE_TABLE;
Members
FwResourceCount The number of ﬁrmware resources in the table, must not be zero.
FwResourceCountMax The maximum number of resource array entries that can be within the table without reallo-
cating the table, must not be zero.
FwResourceVersion The version of the EFI_SYSTEM_RESOURCE_ENTRY entities used in this table. This ﬁeld
should be set to 1. See EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION .
Entries Array of EFI_SYSTEM_RESOURCE_ENTRY
// Current Entry Version
#define EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION 1
EFI_GUID FwClass;
UINT32 FwType;
UINT32 FwVersion;
UINT32 LowestSupportedFwVersion;
UINT32 CapsuleFlags;
} EFI_SYSTEM_RESOURCE_ENTRY;
FwClass The ﬁrmware class ﬁeld contains a GUID that identiﬁes a ﬁrmware component that can be updated via
UpdateCapsule(). This GUID must be unique within all entries of the ESRT.
FwType Identiﬁes the type of ﬁrmware resource. See “Firmware Type Deﬁnitions” below for possible values.
FwVersion The ﬁrmware version ﬁeld represents the current version of the ﬁrmware resource, value must always
increase as a larger number represents a newer version.
LowestSupportedFwVersion The lowest ﬁrmware resource version to which a ﬁrmware resource can be rolled back
for the given system/device. Generally this is used to protect against known and ﬁxed security issues.
CapsuleFlags The capsule ﬂags ﬁeld contains the CapsuleGuid ﬂags (bits 0- 15) as deﬁned in the
EFI_CAPSULE_HEADER that will be set in the capsule header.
LastAttemptVersion The last attempt version ﬁeld describes the last ﬁrmware version for which an update was
attempted (uses the same format as Firmware Version).
Last Attempt Version is updated each time an UpdateCapsule() is attempted for an ESRT entry and is preserved
across reboots (non-volatile). However, in cases where the attempt version is not recorded due to limitations in
the update process, the ﬁeld shall set to zero after a failed update. Similarly, in the case of a removable device,
this value is set to 0 in cases where the device has not been updated since being added to the system.
23.4. EFI System Resource Table 861Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
LastAttemptStatus The last attempt status ﬁeld describes the result of the last ﬁrmware update attempt for the
ﬁrmware resource entry.
LastAttemptStatus is updated each time an UpdateCapsule() is attempted for an ESRT entry and is preserved
across reboots (non-volatile).
If a ﬁrmware update has never been attempted or is unknown, for example after fresh insertion of a removable
device, LastAttemptStatus must be set to Success.
//
// Firmware Type Definitions
//
#define ESRT_FW_TYPE_UNKNOWN 0x00000000
#define ESRT_FW_TYPE_SYSTEMFIRMWARE 0x00000001
#define ESRT_FW_TYPE_DEVICEFIRMWARE 0x00000002
#define ESRT_FW_TYPE_UEFIDRIVER 0x00000003
//
// Last Attempt Status Values
//
#define LAST_ATTEMPT_STATUS_SUCCESS 0x00000000
#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x00000001
#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000002
#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION 0x00000003
#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT 0x00000004
#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR 0x00000005
#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC 0x00000006
#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT 0x00000007
#define LAST_ATTEMPT_STATUS_ERROR_UNSATISFIED_DEPENDENCIES 0x00000008
// The LastAttemptStatus values of 0x1000 - 0x4000 are reserved forvendor usage.
#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000
#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00004000
23.4.2 Adding and Removing Devices from the ESRT
ESRT entries must be updated by System Firmware before handoff to the Operating System under the following
conditions. Devices and systems that support hot swapping (once the OS has been loaded) will not get their ESRT
entries updated until the next reboot and execution of ESRT updating logic in the UEFI space.
•Required : System ﬁrmware is responsible for updating the FirmwareVersion, LowestSupportedFirmwareVer-

sion, LastAttemptVersion andLastAttemptStatus values in the ESRT any time UpdateCapsule is called and a
ﬁrmware update attempt is made for the corresponding ESRT entry.
•Required : the ESRT must be updated each time a conﬁguration change is detected by system ﬁrmware, such as
when a device is added or removed from the system.
•Optional : all devices in the ESRT should be polled for any conﬁguration changes any time UpdateCapsule is
called.
23.4. EFI System Resource Table 862Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.4.3 ESRT and Firmware Management Protocol
Although the ESRT does not require ﬁrmware to use Firmware Management Protocol for updates it is designed to
work with and extend the capabilities of FMP. The ESRT can be used to represent system and device ﬁrmware ser-
viced by capsules that have an implementation speciﬁc format as well as devices that support Firmware Management
Protocol and that are serviced by capsules formatted as described in Dependency Expression Instruction Set , Deliv-
ering Capsules Containing Updates to Firmware Management Protocol. For system expansion devices, the task of
building ESRT table entries is to be performed by the system ﬁrmware based upon FMP data published by the device.
23.4.4 Mapping Firmware Management Protocol Descriptors to ESRT Entries
Firmware management Protocol descriptors deﬁne most of the information needed for an ESRT entry. The table below
helps identify which members map to which ﬁelds. Some members are dependent on certain versions of FMP and it is
left to system ﬁrmware to resolve any mappings when information is not present in the FMP instance. FMP descriptors
should only be mapped to ESRT entries if the following are true:
• An entry with the same ImageTypeId is not already in the ESRT.
•AttributesSupported andAttributesSetting have the IMAGE_ATTRIBUTE_IN_USE bit set.
• In the case where DescriptorCount returned by GetImageInfo() is greater than one, ﬁrmware shall populate the
ESRT according to system policy, noting however that multiple ESRT entries with identical FwClass values are
not permitted.
Table 23.20: ESRT and FMP Fields
ESRT Field FMP Field Comment
FwClass ImageTypeId The ImageTypeId GUID from the Firmware Man-
agement Protocol instance for a device is used as
the Firmware Class GUID in the ESRT. Where there
are multiple identical devices in the system, system
ﬁrmware must create a mapping to ensure that the ESRT
FwClass GUIDs are unique and consistent.
FwVersion Version Represents the current version of device ﬁrmware for an
FMP instance.
LowestSupported FwVer-
sionLowestSupported Im-
ageVersion
LastAttemptVersion LastAttemptVersion To be set after the completion of a ﬁrmware update at-
tempt. In descriptor v3+ only. Default value is 0.
LastAttemptStatus LastAttemptStatus To be set after the completion of a ﬁrmware update at-
tempt. In descriptor v3+ only. Default value is SUC-
CESS.
23.4. EFI System Resource Table 863Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.5 Delivering Capsule Containing JSON payload
Summary
This section deﬁnes a method for delivery of JSON payload to perform ﬁrmware conﬁguration or ﬁrmware update
using the UpdateCapsule runtime API or using mass storage delivery.
23.5.1 EFI_JSON_CAPSULE_ID_GUID
GUID
// {67D6F4CD-D6B8-4573-BF4A-DE5E252D61AE}
#define EFI_JSON_CAPSULE_ID_GUID \
{0x67d6f4cd, 0xd6b8, 0x4573, \
{0xbf, 0x4a, 0xde, 0x5e, 0x25, 0x2d, 0x61, 0xae }}
ing to the deﬁnitions of Update Capsule . Use of this GUID indicates a capsule with body conforming to the additional
structure deﬁned in Deﬁned JSON Capsule Data Structure .
ture deﬁned in Deﬁned JSON Capsule Data Structure , and if it is possible for the platform to process that then
EFI_SUCCESS will be returned.
inDeﬁned JSON Capsule Data Structure , and if it is possible for the platform to process that the update will be
By deﬁnition, ﬁrmware conﬁguration and ﬁrmware update are not available in EFI runtime. Depending on plat-
form capabilities, EFI runtime delivery of the capsule may not be supported, and may return an error when delivered
in EFI runtime with CAPSULE_FLAGS_PERSIST_ACROSS_RESET bit deﬁned. However, any platform support-
ing this capability is required to accept this form of capsule in Boot Services, including optional use of the CAP-
23.5.2 Deﬁned JSON Capsule Data Structure
A generic EFI Capsule Body is deﬁned in Update Capsule . When an EFI Capsule is identiﬁed by
EFI_JSON_CAPSULE_ID_GUID, the internal structure of the capsule header is deﬁned in this section, see
EFI_JSON_CAPSULE_HEADER. Note that if multiple JSON capsules are delivered together, each JSON capsule
should contain one EFI_CAPSULE_HEADER and one EFI_JSON_CAPSULE_HEADER separately.
UINT32 PayloadLength;
UINT8 Payload[];
} EFI_JSON_CAPSULE_HEADER;
#pragma pack ()
23.5. Delivering Capsule Containing JSON payload 864Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
CapsuleId The unique identiﬁer of this capsule.
PayloadLength The length of the JSON payload immediately following this header, in bytes.
Payload Variable length buffer containing the JSON payload that should be parsed and applied to the system. The
deﬁnition of the JSON schema used in the payload is beyond the scope of this speciﬁcation.
TheEFI_JSON_CAPSULE_HEADER structure is located at the lowest offset within the body of the capsule identiﬁed
byEFI_JSON_CAPSULE_ID_GUID . It is expected that drivers which process the JSON payload have the speciﬁc
knowledge of the JSON schema used in the payload. The drivers should parse the JSON payload ﬁrstly to understand
whether the capsule wants to perform ﬁrmware conﬁgure or ﬁrmware update then route the JSON payload to corre-
sponding modules. For instance, the capsule may be delivered to EFI_FIRMWARE_MANAGEMENT_PROTOCOL
instance to update the ﬁrmware image.
Structure of the Conﬁguration Data
During the system boot, current conﬁguration data or cached conﬁguration data is reported to the
EFI System Conﬁguration Table with EFI_JSON_CONFIG_DATA_TABLE_GUID according to the value of
EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH bit in OsIndications . The structure to record the con-
ﬁguration data is deﬁned in this section, see EFI_JSON_CAPSULE_CONFIG_DATA .
UINT32 TotalLength;
EFI_JSON_CONFIG_DATA_ITEM ConfigDataList[];
} EFI_JSON_CAPSULE_CONFIG_DATA;
TotalLength The total length of EFI_JSON_CAPSULE_CONFIG_DATA , in bytes.
ConﬁgDataList Array of conﬁguration data groups. Type EFI_JSON_CONFIG_DATA_ITEM is deﬁned below.
UINT32 ConfigDataLength;
UINT8 ConfigData[];
} EFI_JSON_CONFIG_DATA_ITEM;
ConﬁgDataLength The length of the following ConﬁgData, in bytes.
ConﬁgData Variable length buffer containing the JSON payload that describes one group of conﬁguration data within
current system. The deﬁnition of the JSON schema used in this payload is beyond the scope of this speciﬁcation.
For supporting multiple groups of conﬁguration data, a list of EFI_JSON_CONFIG_DATA_ITEM are included in
EFI_JSON_CAPSULE_CONFIG_DATA and each item indicates one group of conﬁguration data. It is expected that
particular drivers have the speciﬁc knowledge of the JSON schema used in the payload so that they can describe
system conﬁguration data in JSON then install to the EFI System Conﬁguration Table. The drivers should check
EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH bit in OsIndications to understand whether they need
collect current conﬁguration ﬁrstly.
23.5. Delivering Capsule Containing JSON payload 865Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
23.5.3 Firmware Processing of the Capsule Identiﬁed by
EFI_JSON_CAPSULE_ID_GUID
ofDelivery of Capsules via ﬁle on Mass Storage Device . The capsule must be constructed to consist of a single
EFI_JSON_CAPSULE_HEADER structure with JSON payload follows. A capsule in which PayloadLength is
zero will not be processed.
2. Capsule is recognized by EFI_CAPSULE_HEADER member CapsuleGuid equal to
EFI_JSON_CAPSULE_ID_GUID .CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE ﬂag must be 0.

SULE_FLAGS_PERSIST_ACROSS_RESET and optionally CAPSULE_FLAGS_INITIATE_RESET should be
set to 1 in the EFI_CAPSULE_HEADER.
5. When reset is requested using CAPSULE_FLAGS_PERSIST_ACROSS_RESET, the capsule is processed in
Boot Services, before the EFI_EVENT_GROUP_READY_TO_BOOT event.
7. When a capsule identiﬁed by EFI_JSON_CAPSULE_ID_GUID is received, the system ﬁrmware
shall place a pointer to the coalesced capsule in the EFI System Conﬁguration Table with
EFI_JSON_CAPSULE_DATA_TABLE_GUID before loading any third party modules such as option ROM.
If multiple capsules identiﬁed by EFI_JSON_CAPSULE_ID_GUID are received, the system ﬁrmware shall
place a list of pointers to the capsules, preceded by a UINTN that represents the number of pointers, in the EFI
System Conﬁguration Table with EFI_JSON_CAPSULE_DATA_TABLE_GUID before loading any third party
modules such as option ROM. The UINTN and each pointer must be naturally aligned.
8. The system conﬁguration driver should check EFI System Conﬁguration Table and parse the JSON payload, to
identify the conﬁguration data type of JSON payload, and route the JSON payload to corresponding modules.
The corresponding capsule pointer shall be removed from the EFI System Conﬁguration Table and also be
cleared after it is processed.
9. The processing result shall be installed to EFI System Conﬁguration Table using the format of
EFI_CAPSULE_RESULT_V ARIABLE_HEADER and EFI_CAPSULE_RESULT_V ARIABLE_JSON de-
ﬁned in Section 8.5.6 with EFI_JSON_CAPSULE_RESULT_TABLE_GUID. If the capsule is delivered via
mass storage device, the process result shall be recorded by using UEFI variables as described in UEFI variable
reporting on the Success or any Errors encountered in processing of capsules after restart .
23.5. Delivering Capsule Containing JSON payload 866CHAPTER
TWENTYFOUR
NETWORK PROTOCOLS — SNP, PXE, BIS AND HTTP BOOT
24.1 Simple Network Protocol
This section deﬁnes the Simple Network Protocol. This protocol provides a packet level interface to a network adapter.
24.1.1 EFI_SIMPLE_NETWORK_PROTOCOL
Summary
The EFI_SIMPLE_NETWORK_PROTOCOL provides services to initialize a network interface, transmit packets,
receive packets, and close a network interface.
GUID
#define EFI_SIMPLE_NETWORK_PROTOCOL_GUID \
{0xA19832B9,0xAC25,0x11D3,\
{0x9A,0x2D,0x00,0x90,0x27,0x3f,0xc1,0x4d}}
#define EFI_SIMPLE_NETWORK_PROTOCOL_REVISION 0x00010000
typedef struct \_EFI_SIMPLE_NETWORK_PROTOCOL\_ {
EFI_SIMPLE_NETWORK_START Start;
EFI_SIMPLE_NETWORK_STOP Stop;
EFI_SIMPLE_NETWORK_INITIALIZE Initialize;
EFI_SIMPLE_NETWORK_RESET Reset;
EFI_SIMPLE_NETWORK_SHUTDOWN Shutdown;
EFI_SIMPLE_NETWORK_RECEIVE_FILTERS ReceiveFilters;
EFI_SIMPLE_NETWORK_STATION_ADDRESS StationAddress;
EFI_SIMPLE_NETWORK_STATISTICS Statistics;
EFI_SIMPLE_NETWORK_MCAST_IP_TO_MAC MCastIpToMac;
EFI_SIMPLE_NETWORK_NVDATA NvData;
EFI_SIMPLE_NETWORK_GET_STATUS GetStatus;
EFI_SIMPLE_NETWORK_TRANSMIT Transmit;
EFI_SIMPLE_NETWORK_RECEIVE Receive;
EFI_EVENT WaitForPacket;
EFI_SIMPLE_NETWORK_MODE *Mode;
} EFI_SIMPLE_NETWORK_PROTOCOL;
867Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Revision Revision of the EFI_SIMPLE_NETWORK_PROTOCOL. All future revisions must be backwards compat-
ible. If a future version is not backwards compatible it is not the same GUID.
Start Prepares the network interface for further command operations. No other
EFI_SIMPLE_NETWORK_PROTOCOL interface functions will operate until this call is made. See the
EFI_SIMPLE_NETWORK.Start() function description.
Stop Stops further network interface command processing. No other EFI_SIMPLE_NETWORK_PROTOCOL
interface functions will operate after this call is made until another Start() call is made. See the
EFI_SIMPLE_NETWORK.Stop() function description.
Initialize Resets the network adapter and allocates the transmit and receive buffers. See the
EFI_SIMPLE_NETWORK.Initialize() function description.
Reset Resets the network adapter and reinitializes it with the parameters provided in the previous call to Initialize() .
See the EFI_SIMPLE_NETWORK.Reset() function description.
Shutdown Resets the network adapter and leaves it in a state safe for another driver to initialize. The memory buffers
assigned in the Initialize() call are released. After this call, only the Initialize() or Stop() calls may be used. See
theEFI_SIMPLE_NETWORK.Shutdown() function description.
ReceiveFilters Enables and disables the receive ﬁlters for the network interface and, if supported, man-
ages the ﬁltered multicast HW MAC (Hardware Media Access Control) address list. See the
EFI_SIMPLE_NETWORK.ReceiveFilters() function description.
StationAddress Modiﬁes or resets the current station address, if supported. See the
EFI_SIMPLE_NETWORK.StationAddress() function description.
Statistics Collects statistics from the network interface and allows the statistics to be reset. See the
EFI_SIMPLE_NETWORK.Statistics() function description.
MCastIpToMac Maps a multicast IP address to a multicast HW MAC address. See the
EFI_SIMPLE_NETWORK.MCastIPtoMAC() function description.
NvData Reads and writes the contents of the NVRAM devices attached to the network interface. See the
EFI_SIMPLE_NETWORK.NvData() function description.
GetStatus Reads the current interrupt status and the list of recycled transmit buffers from the network interface. See
theEFI_SIMPLE_NETWORK.GetStatus() function description.
Transmit Places a packet in the transmit queue. See EFI_SIMPLE_NETWORK.Transmit() function description.
Receive Retrieves a packet from the receive queue, along with the status ﬂags that describe the packet type. See the
EFI_SIMPLE_NETWORK.Receive() function description.
WaitForPacket Event used with EFI_BOOT_SERVICES.WaitForEvent() to wait for a packet to be received.
Mode Pointer to the EFI_SIMPLE_NETWORK_MODE data for the device. See “Related Deﬁnitions” below.
// EFI_SIMPLE_NETWORK_MODE
//
// Note that the fields inthis data structure are read-only
//andare updated by the code that produces the
// EFI_SIMPLE_NETWORK_PROTOCOL
// functions. All these fields must be discovered
//ina protocol instance of
// EFI_DRIVER_BINDING_PROTOCOL.Start().
24.1. Simple Network Protocol 868Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT32 State;
UINT32 HwAddressSize;
UINT32 MediaHeaderSize;
UINT32 MaxPacketSize;
UINT32 NvRamSize;
UINT32 NvRamAccessSize;
UINT32 ReceiveFilterMask;
UINT32 ReceiveFilterSetting;
UINT32 MaxMCastFilterCount;
UINT32 MCastFilterCount;
EFI_MAC_ADDRESS MCastFilter[MAX_MCAST_FILTER_CNT];
EFI_MAC_ADDRESS CurrentAddress;
EFI_MAC_ADDRESS BroadcastAddress;
EFI_MAC_ADDRESS PermanentAddress;
UINT8 IfType;
BOOLEAN MacAddressChangeable;
BOOLEAN MultipleTxSupported;
BOOLEAN MediaPresentSupported;
} EFI_SIMPLE_NETWORK_MODE;
State Reports the current state of the network interface (see EFI_SIMPLE_NETWORK_STATE WORK_STATE
below). When an EFI_SIMPLE_NETWORK_PROTOCOL driver initializes a network interface, the network
interface is left in the EﬁSimpleNetworkStopped state.
HwAddressSize The size, in bytes, of the network interface’s HW address.
MediaHeaderSize The size, in bytes, of the network interface’s media header.
MaxPacketSize The maximum size, in bytes, of the packets supported by the network interface.
NvRamSize The size, in bytes, of the NVRAM device attached to the network interface. If an NVRAM device is not
attached to the network interface, then this ﬁeld will be zero. This value must be a multiple of NvramAccessSize .
NvRamAccessSize The size that must be used for all NVRAM reads and writes. The start address for NVRAM read
and write operations and the total length of those operations, must be a multiple of this value. The legal values
for this ﬁeld are 0, 1, 2, 4, and 8. If the value is zero, then no NVRAM devices are attached to the network
ReceiveFilterMask The multicast receive ﬁlter settings supported by the network interface.
ReceiveFilterSetting The current multicast receive ﬁlter settings. See “Bit Mask Values for ReceiveFilterSetting ”
below.
MaxMCastFilterCount The maximum number of multicast address receive ﬁlters supported by the driver. If this
value is zero, then ReceiveFilters() cannot modify the multicast address receive ﬁlters. This ﬁeld may be less
than MAX_MCAST_FILTER_CNT (see below).

below.
MCastFilterCount The current number of multicast address receive ﬁlters.
MCastFilter Array containing the addresses of the current multicast address receive ﬁlters.
CurrentAddress The current HW MAC address for the network interface.
BroadcastAddress The current HW MAC address for broadcast packets.
PermanentAddress The permanent HW MAC address for the network interface.
IfType The interface type of the network interface. See RFC 3232, section “Number Hardware Type.”
MacAddressChangeable TRUE if the HW MAC address can be changed.
24.1. Simple Network Protocol 869Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
MultipleTxSupported TRUE if the network interface can transmit more than one packet at a time.
MediaPresentSupported TRUE if the presence of media can be determined; otherwise FALSE . IfFALSE ,Medi-
aPresent cannot be used.
MediaPresent TRUE if media are connected to the network interface; othrwise FALSE . This ﬁeld shows the media
present status as of the most recent GetStatus() call.
// EFI_SIMPLE_NETWORK_STATE
EfiSimpleNetworkStopped,
EfiSimpleNetworkStarted,
EfiSimpleNetworkInitialized,
EfiSimpleNetworkMaxState
} EFI_SIMPLE_NETWORK_STATE;
// MAX_MCAST_FILTER_CNT
#define MAX_MCAST_FILTER_CNT 16
// Bit Mask Values forReceiveFilterSetting.
//
// Note that all other bit values are reserved.
#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST 0x01
#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST 0x02
#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST 0x04
#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS 0x08
#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10
The EFI_SIMPLE_NETWORK_PROTOCOL protocol is used to initialize access to a network adapter. Once the
network adapter initializes, the EFI_SIMPLE_NETWORK_PROTOCOL protocol provides services that allow packets
to be transmitted and received. This provides a packet level interface that can then be used by higher level drivers to
produce boot services like DHCP, TFTP, and MTFTP. In addition, this protocol can be used as a building block in a
full UDP and TCP/IP implementation that can produce a wide variety of application level network interfaces. See the
Preboot Execution Environment (PXE) Speciﬁcation for more information.
NOTE The underlying network hardware may only be able to access 4 GiB (32-bits) of system memory. Any requests
to transfer data to/from memory above 4 GiB with 32-bit network hardware will be double-buffered (using intermediate
buffers below 4 GiB) and will reduce performance .
NOTE The same handle can have an instance of the EFI_ADAPTER_INFORMATION_PROTOCOL with a
EFI_ADAPTER_INFO_MEDIA_STATE type structure .
24.1. Simple Network Protocol 870Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.1.2 EFI_SIMPLE_NETWORK.Start()
Summary
Changes the state of a network interface from “stopped” to “started.”
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_START) (
IN EFI_SIMPLE_NETWORK_PROTOCOL *This
);
This A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
This function starts a network interface. If the network interface successfully starts, then EFI_SUCCESS will be
returned.
EFI_SUCCESS The network interface was started.
EFI_ALREADY_STARTED The network interface is already in the started state.
EFI_INV ALID_PARAMETER This parameter was NULL or did not point to a valid
EFI_SIMPLE_NETWORK_PROTOCOL structure.
EFI_DEVICE_ERROR The command could not be sent to the network interface.
EFI_UNSUPPORTED This function is not supported by the network interface.
24.1.3 EFI_SIMPLE_NETWORK.Stop()
Summary
Changes the state of a network interface from “started” to “stopped.”
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_STOP) (
);
This function stops a network interface. This call is only valid if the network interface is in the started state. If the
network interface was successfully stopped, then EFI_SUCCESS will be returned.
EFI_SUCCESS The network interface was stopped.
24.1. Simple Network Protocol 871Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.1 – continued from previous page
EFI_NOT_STARTED The network interface has not been started.
24.1.4 EFI_SIMPLE_NETWORK.Initialize()
Summary
Resets a network adapter and allocates the transmit and receive buffers required by the network interface; optionally,
also requests allocation of additional transmit and receive buffers.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_INITIALIZE) (
IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN UINTN ExtraRxBufferSize OPTIONAL,
IN UINTN ExtraTxBufferSize OPTIONAL
);
ExtraRxBufferSize The size, in bytes, of the extra receive buffer space that the driver should allocate for the network
interface. Some network interfaces will not be able to use the extra buffer, and the caller will not know if it is
actually being used.
ExtraTxBufferSize The size, in bytes, of the extra transmit buffer space that the driver should allocate for the network
This function allocates the transmit and receive buffers required by the network interface. If this allocation fails,
then EFI_OUT_OF_RESOURCES is returned. If the allocation succeeds and the network interface is successfully
initialized, then EFI_SUCCESS will be returned.
EFI_SUCCESS The network interface was initialized.
EFI_OUT_OF_RESOURCES There was not enough memory for the transmit and receive buffers.
EFI_UNSUPPORTED The increased buffer size feature is not supported.
24.1. Simple Network Protocol 872Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.1.5 EFI_SIMPLE_NETWORK.Reset()
Summary
Resets a network adapter and reinitializes it with the parameters that were provided in the previous call to
EFI_SIMPLE_NETWORK.Initialize() .
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_RESET) (
);
This function resets a network adapter and reinitializes it with the parameters that were provided in the previous
call to Initialize(). The transmit and receive queues are emptied and all pending interrupts are cleared. Receive
ﬁlters, the station address, the statistics, and the multicast-IP-to-HW MAC addresses are not reset by this call. If the
network interface was successfully reset, then EFI_SUCCESS will be returned. If the driver has not been initialized,
EFI_DEVICE_ERROR will be returned.
EFI_SUCCESS The network interface was reset.
EFI_INV ALID_PARAMETER One or more of the parameters has an unsupported value.
24.1.6 EFI_SIMPLE_NETWORK.Shutdown()
Summary
Resets a network adapter and leaves it in a state that is safe for another driver to initialize.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_SHUTDOWN) (
);
24.1. Simple Network Protocol 873Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function releases the memory buffers assigned in the EFI_SIMPLE_NETWORK.Initialize() call. Pending
transmits and receives are lost, and interrupts are cleared and disabled. After this call, only the Initialize() and
EFI_SIMPLE_NETWORK.Stop() calls may be used. If the network interface was successfully shutdown, then

Summary
Prototype
typedef
);
EFI_SUCCESS will be returned. If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
EFI_SUCCESS The network interface was shutdown.
24.1.7 EFI_SIMPLE_NETWORK.ReceiveFilters()
Summary
Manages the multicast receive ﬁlters of a network interface.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_RECEIVE_FILTERS) (
IN UINT32 Enable,
IN UINT32 Disable,
IN BOOLEAN ResetMCastFilter,
IN UINTN MCastFilterCnt OPTIONAL,
IN EFI_MAC_ADDRESS MCastFilter OPTIONAL,
);
Enable A bit mask of receive ﬁlters to enable on the network interface.
Disable A bit mask of receive ﬁlters to disable on the network interface. For backward compatibility with EFI 1.1
platforms, the EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit must be set when the ResetMCastFilter
parameter is TRUE .
ResetMCastFilter Set to TRUE to reset the contents of the multicast receive ﬁlters on the network interface to their
default values.
MCastFilterCnt Number of multicast HW MAC addresses in the new MCastFilter list. This value must be less than
or equal to the MCastFilterCnt ﬁeld of EFI_SIMPLE_NETWORK_MODE. This ﬁeld is optional if ResetM-
CastFilter isTRUE .
MCastFilter A pointer to a list of new multicast receive ﬁlter HW MAC addresses. This list will replace any existing
multicast HW MAC address list. This ﬁeld is optional if ResetMCastFilter isTRUE .
This function is used enable and disable the hardware and software receive ﬁlters for the underlying network device.
The receive ﬁlter change is broken down into three steps:
• The ﬁlter mask bits that are set (ON) in the Enable parameter are added to the current receive ﬁlter settings.
24.1. Simple Network Protocol 874Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• The ﬁlter mask bits that are set (ON) in the Disable parameter are subtracted from the updated receive ﬁlter
settings.
• If the resulting receive ﬁlter setting is not supported by the hardware a more liberal setting is selected.
If the same bits are set in the Enable and Disable parameters, then the bits in the Disable parameter takes precedence.
If the ResetMCastFilter parameter is TRUE , then the multicast address list ﬁlter is disabled (irregardless of what other
multicast bits are set in the Enable and Disable parameters). The SNP->Mode->MCastFilterCount ﬁeld is set to zero.
The Snp->Mode->MCastFilter contents are undeﬁned.
After enabling or disabling receive ﬁlter settings, software should verify the new settings by checking the Snp->Mode-
>ReceiveFilterSettings, Snp->Mode->MCastFilterCount and Snp->Mode->MCastFilter ﬁelds.
Note :Some network drivers and/or devices will automatically promote receive ﬁlter settings if the requested setting
can not be honored. For example, if a request for four multicast addresses is made and the underlying hardware only
supports two multicast addresses the driver might set the promiscuous or promiscuous multicast receive ﬁlters instead.
The receiving software is responsible for discarding any extra packets that get through the hardware receive ﬁlters.
Note :To disable all receive ﬁlter hardware, the network driver must be Shutdown() and Stopped(). Calling Receive-
Filters() with Disable set to Snp->Mode->ReceiveFilterSettings will make it so no more packets are returned by the
Receive() function, but the receive hardware may still be moving packets into system memory before inspecting and
discarding them. Unexpected system errors, reboots and hangs can occur if an OS is loaded and the network devices
are not Shutdown() and Stopped() .
IfResetMCastFilter isTRUE, then the multicast receive ﬁlter list on the network interface will be reset to the default
multicast receive ﬁlter list. If ResetMCastFilter isFALSE , and this network interface allows the multicast receive ﬁlter
list to be modiﬁed, then the MCastFilterCnt andMCastFilter are used to update the current multicast receive ﬁlter list.
The modiﬁed receive ﬁlter list settings can be found in the MCastFilter ﬁeld of EFI_SIMPLE_NETWORK_MODE
inNetwork Protocols — SNP , PXE, BIS and HTTP Boot . If the network interface does not allow the multicast receive
ﬁlter list to be modiﬁed, then EFI_INV ALID_PARAMETER will be returned. If the driver has not been initialized,
If the receive ﬁlter mask and multicast receive ﬁlter list have been successfully updated on the network interface,
EFI_SUCCESS The multicast receive ﬁlter list was updated.
24.1. Simple Network Protocol 875Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.5 – continued from previous page
• One or more of the following conditions is TRUE :
•This isNULL
• There are bits set in Enable that are not set in
Snp->Mode->ReceiveFilterMask
• There are bits set in Disable that are not set in
• Multicast is being enabled (the EFI
_SIMPLE_NETWORK_RECEIVE_MULTICAST bit is set in Enable, it is
not set in Disable, and ResetMCastFilter is FALSE ) and MCastFilterCount
is zero
• Multicast is being enabled and MCastFilterCount is greater than
Snp->Mode->MaxMCastFilterCount
• Multicast is being enabled and MCastFilter is NULL
• Multicast is being enabled and one or more of the addresses in the
MCastFilter list are not valid multicast MAC addresses
EFI_DEVICE_ERROR
• The network interface has been started but has not been initialized
• An unexpected error was returned by the underlying network driver or
device
24.1.8 EFI_SIMPLE_NETWORK.StationAddress()
Summary
Modiﬁes or resets the current station address, if supported.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_STATION_ADDRESS) (
IN BOOLEAN Reset,
IN EFI_MAC_ADDRESS *New OPTIONAL
);
Reset Flag used to reset the station address to the network interface’s permanent address.
New New station address to be used for the network interface.
This function modiﬁes or resets the current station address of a network interface, if supported. If Reset isTRUE , then
the current station address is set to the network interface’s permanent address. If Reset isFALSE , and the network
interface allows its station address to be modiﬁed, then the current station address is changed to the address speciﬁed
byNew. If the network interface does not allow its station address to be modiﬁed, then EFI_INV ALID_PARAMETER
24.1. Simple Network Protocol 876Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
will be returned. If the station address is successfully updated on the network interface, EFI_SUCCESS will be
returned. If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
EFI_SUCCESS The network interface’s station address was updated.
EFI_NOT_STARTED The Simple Network Protocol interface has not been started by calling
Start() .
EFI_INV ALID_PARAMETER TheNew station address was not accepted by the NIC.
EFI_INV ALID_PARAMETER Reset isFALSE andNew isNULL .
EFI_DEVICE_ERROR The Simple Network Protocol interface has not been initialized by calling
Initialize() .
EFI_DEVICE_ERROR An error occurred attempting to set the new station address.
EFI_UNSUPPORTED The NIC does not support changing the network interface’s station address.
24.1.9 EFI_SIMPLE_NETWORK.Statistics()
Summary
Resets or collects the statistics on a network interface.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_STATISTICS) (
IN OUT UINTN *StatisticsSize OPTIONAL,
OUT EFI_NETWORK_STATISTICS *StatisticsTable OPTIONAL
);
Reset Set to TRUE to reset the statistics for the network interface.
StatisticsSize On input the size, in bytes, of StatisticsTable. On output the size, in bytes, of the resulting table of
statistics.
StatisticsTable A pointer to the EFI_NETWORK_STATISTICS in Network Protocols — SNP , PXE, BIS and HTTP
Boot structure that contains the statistics. Type EFI_NETWORK_STATISTICS is deﬁned in “Related Deﬁni-
tions” below.
// EFI_NETWORK_STATISTICS
//
// Any statistic value that is-1is notavailable
// on the device and isto be ignored.

Summary
Prototype
typedef
);
//
UINT64 RxTotalFrames;
UINT64 RxGoodFrames;
UINT64 RxUndersizeFrames;
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UINT64 RxOversizeFrames;
UINT64 RxDroppedFrames;
UINT64 RxUnicastFrames;
UINT64 RxBroadcastFrames;
UINT64 RxMulticastFrames;
UINT64 RxCrcErrorFrames;
UINT64 RxTotalBytes;
UINT64 TxTotalFrames;
UINT64 TxGoodFrames;
UINT64 TxUndersizeFrames;
UINT64 TxOversizeFrames;
UINT64 TxDroppedFrames;
UINT64 TxUnicastFrames;
UINT64 TxBroadcastFrames;
UINT64 TxMulticastFrames;
UINT64 TxCrcErrorFrames;
UINT64 TxTotalBytes;
UINT64 Collisions;
UINT64 UnsupportedProtocol;
UINT64 RxDuplicatedFrames;
UINT64 RxDecryptErrorFrames;
UINT64 TxErrorFrames;
UINT64 TxRetryFrames;
} EFI_NETWORK_STATISTICS;
RxTotalFrames Total number of frames received. Includes frames with errors and dropped frames.
RxGoodFrames Number of valid frames received and copied into receive buffers.
RxUndersizeFrames Number of frames below the minimum length for the communications device.
RxOversizeFrames Number of frames longer than the maximum length for the communications device.
RxDroppedFrames Valid frames that were dropped because receive buffers were full.
RxUnicastFrames Number of valid unicast frames received and not dropped.
RxBroadcastFrames Number of valid broadcast frames received and not dropped.
RxMulticastFrames Number of valid multicast frames received and not dropped.
RxCrcErrorFrames Number of frames with CRC or alignment errors.
RxTotalBytes Total number of bytes received. Includes frames with errors and dropped frames.
TxTotalFrames Total number of frames transmitted. Includes frames with errors and dropped frames.
TxGoodFrames Number of valid frames transmitted and copied into receive buffers.
TxUndersizeFrames Number of frames below the minimum length for the media. This would be less than 64 for
Ethernet.
TxOversizeFrames Number of frames longer than the maximum length for the media. This would be greater than
1500 for Ethernet.
TxDroppedFrames Valid frames that were dropped because receive buffers were full.
TxUnicastFrames Number of valid unicast frames transmitted and not dropped.
TxBroadcastFrames Number of valid broadcast frames transmitted and not dropped.
TxMulticastFrames Number of valid multicast frames transmitted and not dropped.
TxCrcErrorFrames Number of frames with CRC or alignment errors.
24.1. Simple Network Protocol 878Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TxTotalBytes Total number of bytes transmitted. Includes frames with errors and dropped frames.
Collisions Number of collisions detected on this subnet.
UnsupportedProtocol Number of frames destined for unsupported protocol.
RxDuplicatedFrames Number of valid frames received that were duplicated.
RxDecryptErrorFrames Number of encrypted frames received that failed to decrypt.
TxErrorFrames Number of frames that failed to transmit after exceeding the retry limit.
TxRetryFrames Number of frames transmitted successfully after more than one attempt.
This function resets or collects the statistics on a network interface. If the size of the statistics table speciﬁed by
StatisticsSize is not big enough for all the statistics that are collected by the network interface, then a partial buffer of
statistics is returned in StatisticsTable, StatisticsSize is set to the size required to collect all the available statistics, and
IfStatisticsSize is big enough for all the statistics, then StatisticsTable will be ﬁlled, StatisticsSize will be set to the
size of the returned StatisticsTable structure, and EFI_SUCCESS is returned. If the driver has not been initialized,
IfReset isFALSE , and both StatisticsSize andStatisticsTable are NULL, then no operations will be performed, and
IfReset isTRUE , then all of the supported statistics counters on this network interface will be reset to zero.
EFI_SUCCESS The requested operation succeeded.
Start() .
EFI_BUFFER_TOO_SMALL StatisticsSize is not NULL andStatisticsTable isNULL . The current buffer
size that is needed to hold all the statistics is returned in StatisticsSize .
EFI_BUFFER_TOO_SMALL StatisticsSize is not NULL andStatisticsTable is not NULL . The current
buffer size that is needed to hold all the statistics is returned in Statistic-
sSize . A partial set of statistics is returned in StatisticsTable .
EFI_INV ALID_PARAMETER StatisticsSize isNULL andStatisticsTable is not NULL .
EFI_DEVICE_ERROR An error was encountered collecting statistics from the NIC.
EFI_UNSUPPORTED The NIC does not support collecting statistics from the network interface.
24.1.10 EFI_SIMPLE_NETWORK.MCastIPtoMAC()
Summary
Converts a multicast IP address to a multicast HW MAC address.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_MCAST_IP_TO_MAC) (
IN BOOLEAN IPv6,
24.1. Simple Network Protocol 879Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_IP_ADDRESS *IP,
OUT EFI_MAC_ADDRESS *MAC
);
IPv6 Set to TRUE if the multicast IP address is IPv6 [RFC 2460]. Set to FALSE if the multicast IP address is IPv4
[RFC 791].
IPThe multicast IP address that is to be converted to a multicast HW MAC address.
MAC The multicast HW MAC address that is to be generated from IP.
This function converts a multicast IP address to a multicast HW MAC address for all packet transactions. If the
mapping is accepted, then EFI_SUCCESS will be returned.
EFI_SUCCESS The multicast IP address was mapped to the multicast HW MAC address.
Start() .
EFI_INV ALID_PARAMETER IPisNULL .
EFI_INV ALID_PARAMETER MAC isNULL .
EFI_INV ALID_PARAMETER IPdoes not point to a valid IPv4 or IPv6 multicast address.
EFI_UNSUPPORTED IPv6 isTRUE and the implementation does not support IPv6 multicast to
MAC address conversion.
24.1.11 EFI_SIMPLE_NETWORK.NvData()
Summary
Performs read and write operations on the NVRAM device attached to a network interface.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_NVDATA) (
IN BOOLEAN ReadWrite,
IN UINTN Offset,
);
ReadWrite TRUE for read operations, FALSE for write operations.
24.1. Simple Network Protocol 880Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Offset Byte offset in the NVRAM device at which to start the read or write operation. This must be a multiple of
NvRamAccessSize and less than NvRamSize . (See EFI_SIMPLE_NETWORK_MODE in Network Protocols
— SNP , PXE, BIS and HTTP Boot .
BufferSize The number of bytes to read or write from the NVRAM device. This must also be a multiple of 2.
Buffer A pointer to the data buffer.
This function performs read and write operations on the NVRAM device attached to a network interface. If ReadWrite
isTRUE , a read operation is performed. If ReadWrite isFALSE , a write operation is performed.
Offset speciﬁes the byte offset at which to start either operation. Offset must be a multiple of NvRamAccessSize, and it
must have a value between zero and NvRamSize .
BufferSize speciﬁes the length of the read or write operation. BufferSize must also be a multiple of NvRamAccessSize,
andOffset +BufferSize must not exceed NvRamSize .
If any of the above conditions is not met, then EFI_INV ALID_PARAMETER will be returned.
If all the conditions are met and the operation is “read,” the NVRAM device attached to the network interface will be
read into Buffer and EFI_SUCCESS will be returned. If this is a write operation, the contents of Buffer will be used to
update the contents of the NVRAM device attached to the network interface and EFI_SUCCESS will be returned.
EFI_SUCCESS The NVRAM access was performed.
• The This parameter is NULL
• The This parameter does not point to a valid
EFI_SIMPLE_NETWORK_PROTOCOL structure
• The Offset parameter is not a multiple of
EFI_SIMPLE_NETWORK_MODE. NvRamAccessSize
• The Offset parameter is not less than EFI_SIMPLE_NETWORK_MODE.
NvRamSize

NvRamSize
• The BufferSize parameter is not a multiple of
TheBuffer parameter is NULL
24.1.12 EFI_SIMPLE_NETWORK.GetStatus()
Summary
Reads the current interrupt status and recycled transmit buffer status from a network interface.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_GET_STATUS) (
24.1. Simple Network Protocol 881Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
OUT UINT32 *InterruptStatus OPTIONAL,
OUT VOID **TxBuf OPTIONAL
);
InterruptStatus A pointer to the bit mask of the currently active interrupts (see “Related Deﬁnitions”). If this is
NULL, the interrupt status will not be read from the device. If this is not NULL, the interrupt status will be read
from the device. When the interrupt status is read, it will also be cleared. Clearing the transmit interrupt does
not empty the recycled transmit buffer array.
TxBuf Recycled transmit buffer address. The network interface will not transmit if its internal recycled transmit
buffer array is full. Reading the transmit buffer does not clear the transmit interrupt. If this is NULL, then the
transmit buffer status will not be read. If there are no transmit buffers to recycle and TxBuf is not NULL, *
TxBuf will be set to NULL.
// Interrupt Bit Mask Settings forInterruptStatus.
#define EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT 0x01
#define EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT 0x02
#define EFI_SIMPLE_NETWORK_COMMAND_INTERRUPT 0x04
#define EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT 0x08
This function gets the current interrupt and recycled transmit buffer status from the network interface. The inter-
rupt status is returned as a bit mask in InterruptStatus . IfInterruptStatus is NULL, the interrupt status will not be
read. Upon successful return of the media status, the MediaPresent ﬁeld of EFI_SIMPLE_NETWORK_MODE will
be updated to reﬂect any change of media status.Upon successful return of the media status, the MediaPresent ﬁeld
ofEFI_SIMPLE_NETWORK_MODE will be updated to reﬂect any change of media status. If TxBuf is not NULL, a
recycled transmit buffer address will be retrieved. If a recycled transmit buffer address is returned in TxBuf, then the
buffer has been successfully transmitted, and the status for that buffer is cleared. If the status of the network interface is
successfully collected, EFI_SUCCESS will be returned. If the driver has not been initialized, EFI_DEVICE_ERROR
will be returned.
EFI_SUCCESS The status of the network interface was retrieved.
24.1. Simple Network Protocol 882Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.1.13 EFI_SIMPLE_NETWORK.Transmit()
Summary
Places a packet in the transmit queue of a network interface.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_TRANSMIT) (
IN UINTN HeaderSize,
IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
IN EFI_MAC_ADDRESS *DestAddr OPTIONAL,
IN UINT16 *Protocol OPTIONAL,
);
HeaderSize The size, in bytes, of the media header to be ﬁlled in by the Transmit() function. If HeaderSize is nonzero,
then it must be equal to This->Mode->MediaHeaderSize and the DestAddr andProtocol parameters must not
be NULL.
BufferSize The size, in bytes, of the entire packet (media header and data) to be transmitted through the network
Buffer A pointer to the packet (media header followed by data) to be transmitted. This parameter cannot be NULL.
IfHeaderSize is zero, then the media header in Buffer must already be ﬁlled in by the caller. If HeaderSize is
nonzero, then the media header will be ﬁlled in by the Transmit() function.
SrcAddr The source HW MAC address. If HeaderSize is zero, then this parameter is ignored. If HeaderSize is
nonzero and SrcAddr is NULL, then This->Mode->CurrentAddress is used for the source HW MAC address.
DestAddr The destination HW MAC address. If HeaderSize is zero, then this parameter is ignored.
Protocol The type of header to build. If HeaderSize is zero, then this parameter is ignored. See RFC 3232, section
“Ether Types,” for examples.
This function places the packet speciﬁed by Header andBuffer on the transmit queue. If HeaderSize is nonzero and
HeaderSize is not equal to This->Mode->MediaHeaderSize, then EFI_INV ALID_PARAMETER will be returned. If
BufferSize is less than This->Mode->MediaHeaderSize, then EFI_BUFFER_TOO_SMALL will be returned. If Buffer
is NULL, then EFI_INV ALID_PARAMETER will be returned. If HeaderSize is nonzero and DestAddr orProtocol
is NULL, then EFI_INV ALID_PARAMETER will be returned. If the transmit engine of the network interface is
busy, then EFI_NOT_READY will be returned. If this packet can be accepted by the transmit engine of the network
interface, the packet contents speciﬁed by Buffer will be placed on the transmit queue of the network interface, and
EFI_SUCCESS will be returned. EFI_SIMPLE_NETWORK.GetStatus() can be used to determine when the packet
has actually been transmitted. The contents of the Buffer must not be modiﬁed until the packet has actually been
transmitted.
The Transmit() function performs nonblocking I/O. A caller who wants to perform blocking I/O, should call Trans-
mit(), and then GetStatus() until the transmitted buffer shows up in the recycled transmit buffer.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
24.1. Simple Network Protocol 883Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The packet was placed on the transmit queue.
EFI_NOT_READY The network interface is too busy to accept this transmit request.
EFI_BUFFER_TOO_SMALL TheBufferSize parameter is too small.
24.1.14 EFI_SIMPLE_NETWORK.Receive()
Summary
Receives a packet from a network interface.
Prototype
typedef
(EFIAPI *EFI_SIMPLE_NETWORK_RECEIVE) (
OUT UINTN *HeaderSize OPTIONAL,
OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
OUT EFI_MAC_ADDRESS *DestAddr OPTIONAL,
OUT UINT16 *Protocol OPTIONAL
);
HeaderSize The size, in bytes, of the media header received on the network interface. If this parameter is NULL,
then the media header size will not be returned.
BufferSize On entry, the size, in bytes, of Buffer. On exit, the size, in bytes, of the packet that was received on the
network interface.
Buffer A pointer to the data buffer to receive both the media header and the data.
SrcAddr The source HW MAC address. If this parameter is NULL, the HW MAC source address will not be extracted
from the media header.
DestAddr The destination HW MAC address. If this parameter is NULL, the HW MAC destination address will not
be extracted from the media header.
Protocol The media header type. If this parameter is NULL, then the protocol will not be extracted from the media
header. See RFC 1700 section “Ether Types” for examples.
This function retrieves one packet from the receive queue of a network interface. If there are no packets on the receive
queue, then EFI_NOT_READY will be returned. If there is a packet on the receive queue, and the size of the packet
is smaller than BufferSize, then the contents of the packet will be placed in Buffer, andBufferSize will be updated with
the actual size of the packet. In addition, if SrcAddr, DestAddr, andProtocol are not NULL, then these values will be
extracted from the media header and returned. EFI_SUCCESS will be returned if a packet was successfully received.
IfBufferSize is smaller than the received packet, then the size of the receive packet will be placed in BufferSize and
24.1. Simple Network Protocol 884Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

EFI_BUFFER_TOO_SMALL will be returned. If the driver has not been initialized, EFI_DEVICE_ERROR will be
returned.
EFI_SUCCESS The received data was stored in Buffer, andBufferSize has been updated to
the number of bytes received.
EFI_NOT_READY No packets have been received on the network interface.
EFI_BUFFER_TOO_SMALL BufferSize is too small for the received packets. BufferSize has been updated
to the required size.
• The BufferSize parameter is NULL
• The Buffer parameter is NULL
24.2 Network Interface Identiﬁer Protocol
This is an optional protocol that is used to describe details about the software layer that is used to produce the Simple
Network Protocol. This protocol is only required if the underlying network interface is 16-bit UNDI, 32/64-bit S/W
UNDI, or H/W UNDI. It is used to obtain type and revision information about the underlying network interface.
An instance of the Network Interface Identiﬁer protocol must be created for each physical external network interface
that is controlled by the !PXE structure. The !PXE structure is deﬁned in the 32/64-bit UNDI Speciﬁcation in Appendix
E.
24.2.1 EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL
Summary
An optional protocol that is used to describe details about the software layer that is used to produce the Simple Network
Protocol.
GUID
#define EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_GUID_31 \
{0x1ACED566, 0x76ED, 0x4218,\
{0xBC, 0x81, 0x76, 0x7F, 0x1F, 0x97, 0x7A, 0x89}}
#define EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION \ 0x00020000
24.2. Network Interface Identiﬁer Protocol 885Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT64 Id;
UINT64 ImageAddr;
UINT32 ImageSize;
CHAR8 StringId[4];
UINT8 MajorVer;
UINT8 MinorVer;
BOOLEAN Ipv6Supported;
UINT16 IfNum;
} EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL;
Revision The revision of the EFI_NETWORK_INTERFACE_IDENTIFIER protocol.
IdAddress of the ﬁrst byte of the identifying structure for this network interface. This is only valid when the network
interface is started (see EFI_SIMPLE_NETWORK.Start() ). When the network interface is not started, this ﬁeld
is set to zero.
16-bit UNDI and 32/64-bit S/W UNDI:
Idcontains the address of the ﬁrst byte of the copy of the !PXE structure in the relocated UNDI code segment.
See the Preboot Execution Environment (PXE) Speciﬁcation and Appendix E.
H/W UNDI:
Idcontains the address of the !PXE structure.
ImageAddr Address of the unrelocated network interface image.
16-bit UNDI:
ImageAddr is the address of the PXE option ROM image in upper memory.
32/64-bit S/W UNDI:
ImageAddr is the address of the unrelocated S/W UNDI image.
H/W UNDI:
ImageAddr contains zero.
ImageSize Size of unrelocated network interface image.
ImageSize is the size of the PXE option ROM image in upper memory.
ImageSize is the size of the unrelocated S/W UNDI image.
H/W UNDI:
ImageSize contains zero.
StringId A four-character ASCII string that is sent in the class identiﬁer ﬁeld of option 60 in DHCP. For a Type of
EﬁNetworkInterfaceUndi, this ﬁeld is “UNDI.”
Type Network interface type. This will be set to one of the values in EFI_NETWORK_INTERFACE_TYPE (see
“Related Deﬁnitions” below).
MajorVer Major version number.
24.2. Network Interface Identiﬁer Protocol 886Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
MajorVer comes from the third byte of the UNDIRev ﬁeld in the UNDI ROM ID structure. Refer to the Preboot
Execution Environment (PXE) Speciﬁcation.
32/64-bit S/W UNDI and H/W UNDI:
MajorVer comes from the Major ﬁeld in the !PXE structure. See Appendix E.
MinorVer Minor version number.
MinorVer comes from the second byte of the UNDIRev ﬁeld in the UNDI ROM ID structure. Refer to the
Preboot Execution Environment (PXE) Speciﬁcation.
MinorVer comes from the Minor ﬁeld in the !PXE structure. See Appendix E.
Ipv6Supported TRUE if the network interface supports IPv6; otherwise FALSE .
IfNum The network interface number that is being identiﬁed by this Network Interface Identiﬁer Protocol. This ﬁeld
must be less than or equal to the (IFcnt | IFcntExt <<8 ) ﬁeld in the !PXE structure.
// EFI_NETWORK_INTERFACE_TYPE
EfiNetworkInterfaceUndi = 1
} EFI_NETWORK_INTERFACE_TYPE;
The EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL is used by EFI_PXE_BASE_CODE_PROTOCOL
and OS loaders to identify the type of the underlying network interface and to locate its initial entry point.
24.3 PXE Base Code Protocol
This section deﬁnes the Preboot Execution Environment (PXE) Base Code protocol, which is used to access PXE-
compatible devices for network access and network booting. For more information about PXE, see “Links to UEFI-
Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “Preboot Execution Environment (PXE) Speciﬁcation”.
24.3.1 EFI_PXE_BASE_CODE_PROTOCOL
Summary
TheEFI_PXE_BASE_CODE_PROTOCOL is used to control PXE-compatible devices. The features of these devices
are deﬁned in the Preboot Execution Environment (PXE) Speciﬁcation. An EFI_PXE_BASE_CODE_PROTOCOL
will be layered on top of an EFI_MANAGED_NETWORK_PROTOCOL protocol in order to perform packet level
transactions. The EFI_PXE_BASE_CODE_PROTOCOL handle also supports the See EFI_LOAD_FILE_PROTOCOL
protocol. This provides a clean way to obtain control from the boot manager if the boot path is from the remote device.
GUID
#define EFI_PXE_BASE_CODE_PROTOCOL_GUID \
{0x03C4E603,0xAC28,0x11d3,\
{0x9A,0x2D,0x00,0x90,0x27,0x3F,0xC1,0x4D}}
24.3. PXE Base Code Protocol 887Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_PXE_BASE_CODE_PROTOCOL_REVISION 0x00010000
EFI_PXE_BASE_CODE_START Start;
EFI_PXE_BASE_CODE_STOP Stop;
EFI_PXE_BASE_CODE_DHCP Dhcp;
EFI_PXE_BASE_CODE_DISCOVER Discover;
EFI_PXE_BASE_CODE_MTFTP Mtftp;
EFI_PXE_BASE_CODE_UDP_WRITE UdpWrite;
EFI_PXE_BASE_CODE_UDP_READ UdpRead;
EFI_PXE_BASE_CODE_SET_IP_FILTER SetIpFilter;
EFI_PXE_BASE_CODE_ARP Arp;
EFI_PXE_BASE_CODE_SET_PARAMETERS SetParameters;
EFI_PXE_BASE_CODE_SET_STATION_IP SetStationIp;
EFI_PXE_BASE_CODE_SET_PACKETS SetPackets;
EFI_PXE_BASE_CODE_MODE *Mode;
} EFI_PXE_BASE_CODE_PROTOCOL;
Revision The revision of the EFI_PXE_BASE_CODE_PROTOCOL. All future revisions must be backwards com-
patible. If a future version is not backwards compatible it is not the same GUID.
Start Starts the PXE Base Code Protocol. Mode structure information is not valid and no other Base Code Protocol
functions will operate until the Base Code is started. See the EFI_PXE_BASE_CODE_PROTOCOL.Start()
Stop Stops the PXE Base Code Protocol. Mode structure information is unchanged by this func-
tion. No Base Code Protocol functions will operate until the Base Code is restarted. See the
EFI_PXE_BASE_CODE_PROTOCOL.Stop() function description.
Dhcp Attempts to complete a DHCPv4 D.O.R.A. (discover / offer / request / acknowledge) or DHCPv6 S.A.R.R
(solicit / advertise / request / reply) sequence. See the EFI_PXE_BASE_CODE_PROTOCOL.Dhcp() function
Discover Attempts to complete the PXE Boot Server and/or boot image discovery sequence. See the
EFI_PXE_BASE_CODE_PROTOCOL.Discover() function description.
Mtftp Performs TFTP and MTFTP services. See the EFI_PXE_BASE_CODE_PROTOCOL.Mtftp() function descrip-
tion.
UdpWrite Writes a UDP packet to the network interface. See the EFI_PXE_BASE_CODE_PROTOCOL.UdpWrite()
UdpRead Reads a UDP packet from the network interface. See the
EFI_PXE_BASE_CODE_PROTOCOL.UdpRead() function description.
SetIpFilter Updates the IP receive ﬁlters of the network device. See the
EFI_PXE_BASE_CODE_PROTOCOL.SetIpFilter() function description.
Arp Uses the ARP protocol to resolve a MAC address. See the EFI_PXE_BASE_CODE_PROTOCOL.Arp() function
SetParameters Updates the parameters that affect the operation of the PXE Base Code Protocol. See the
EFI_PXE_BASE_CODE_PROTOCOL.SetParameters() function description.
24.3. PXE Base Code Protocol 888Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SetStationIp Updates the station IP address and subnet mask values. See the
EFI_PXE_BASE_CODE_PROTOCOL.SetStationIp() function description.

tion.
SetPackets Updates the contents of the cached DHCP and Discover packets. See the
EFI_PXE_BASE_CODE_PROTOCOL.SetPackets() function description.
Mode Pointer to the EFI_PXE_BASE_CODE_MODE for this device. The EFI_PXE_BASE_CODE_MODE struc-
ture is deﬁned in “Related Deﬁnitions” below.
// Maximum ARP andRoute Entries
#define EFI_PXE_BASE_CODE_MAX_ARP\_ENTRIES 8
#define EFI_PXE_BASE_CODE_MAX_ROUTE_ENTRIES 8
// EFI_PXE_BASE_CODE_MODE
//
// The data values inthis structure are read-only and
// are updated by the code that produces the
// EFI_PXE_BASE_CODE_PROTOCOLfunctions.
*********************************************************
BOOLEAN Started;
BOOLEAN Ipv6Available;
BOOLEAN UsingIpv6;
BOOLEAN BisSupported;
BOOLEAN BisDetected;
BOOLEAN AutoArp;
BOOLEAN SendGUID;
BOOLEAN DhcpDiscoverValid;
BOOLEAN DhcpAckReceivd;
BOOLEAN ProxyOfferReceived;
BOOLEAN PxeDiscoverValid;
BOOLEAN PxeReplyReceived;
BOOLEAN PxeBisReplyReceived;
BOOLEAN IcmpErrorReceived;
BOOLEAN TftpErrorReceived;
BOOLEAN MakeCallbacks;
UINT8 TTL;
UINT8 ToS;
EFI_IP_ADDRESS StationIp;
EFI_IP_ADDRESS SubnetMask;
EFI_PXE_BASE_CODE_PACKET DhcpDiscover;
EFI_PXE_BASE_CODE_PACKET DhcpAck;
EFI_PXE_BASE_CODE_PACKET ProxyOffer;
EFI_PXE_BASE_CODE_PACKET PxeDiscover;
EFI_PXE_BASE_CODE_PACKET PxeReply;
EFI_PXE_BASE_CODE_PACKET PxeBisReply;
EFI_PXE_BASE_CODE_IP_FILTER IpFilter;
UINT32 ArpCacheEntries;
EFI_PXE_BASE_CODE_ARP\_ENTRY ArpCache[EFI_PXE_BASE_CODE_MAX_ARP_ENTRIES];
UINT32 RouteTableEntries;
EFI_PXE_BASE_CODE_ROUTE_ENTRY RouteTable[EFI_PXE_BASE_CODE_MAX_ROUTE_ENTRIES];
EFI_PXE_BASE_CODE_ICMP_ERROR IcmpError;
EFI_PXE_BASE_CODE_TFTP_ERROR TftpError;
24.3. PXE Base Code Protocol 889Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_PXE_BASE_CODE_MODE;
Started TRUE if this device has been started by calling EFI_PXE_BASE_CODE_PROTOCOL.Start() . This ﬁeld is
set to TRUE by the Start() function and to FALSE by the EFI_PXE_BASE_CODE_PROTOCOL.Stop() func-
tion.
Ipv6Available TRUE if the UNDI protocol supports IPv6.
Ipv6Supported TRUE if this PXE Base Code Protocol implementation supports IPv6.
UsingIpv6 TRUE if this device is currently using IPv6. This ﬁeld is set by the Start() function.
BisSupported TRUE if this PXE Base Code implementation supports Boot Integrity Services (BIS). This ﬁeld is set
by the Start() function.
BisDetected TRUE if this device and the platform support Boot Integrity Services (BIS). This ﬁeld is set by the
Start() function.
AutoArp TRUE for automatic ARP packet generation; FALSE otherwise. This ﬁeld is initialized to TRUE by Start()
and can be modiﬁed with the EFI_PXE_BASE_CODE_PROTOCOL.SetParameters() function.
SendGUID This ﬁeld is used to change the Client Hardware Address (chaddr) ﬁeld in the DHCP and Discovery
packets. Set to TRUE to send the SystemGuid (if one is available). Set to FALSE to send the client NIC MAC
address. This ﬁeld is initialized to FALSE by Start() and can be modiﬁed with the SetParameters() function.
DhcpDiscoverValid This ﬁeld is initialized to FALSE by the Start() function and set to TRUE when the
EFI_PXE_BASE_CODE_PROTOCOL.Dhcp() function completes successfully. When TRUE , the DhcpDis-
cover ﬁeld is valid. This ﬁeld can also be changed by the EFI_PXE_BASE_CODE_PROTOCOL.SetPackets()
function.
DhcpAckReceived This ﬁeld is initialized to FALSE by the EFI_PXE_BASE_CODE_PROTOCOL.Start() func-
tion and set to TRUE when the EFI_PXE_BASE_CODE_PROTOCOL.Dhcp() function completes suc-
cessfully. When TRUE , the DhcpAck ﬁeld is valid. This ﬁeld can also be changed by the
EFI_PXE_BASE_CODE_PROTOCOL.SetPackets() function.
ProxyOfferReceived This ﬁeld is initialized to FALSE by the Start() function and set to TRUE when the Dhcp()
function completes successfully and a proxy DHCP offer packet was received. When TRUE , the ProxyOffer
packet ﬁeld is valid. This ﬁeld can also be changed by the SetPackets() function.
PxeDiscoverValid When TRUE , the PxeDiscover packet ﬁeld is valid. This ﬁeld is set to FALSE by the Start() and
Dhcp() functions, and can be set to TRUE orFALSE by the EFI_PXE_BASE_CODE_PROTOCOL.Discover()
and SetPackets() functions.
PxeReplyReceived When TRUE , the PxeReply packet ﬁeld is valid. This ﬁeld is set to FALSE by the Start() and
Dhcp() functions, and can be set to TRUE orFALSE by the Discover() and SetPackets() functions.
PxeBisReplyReceived When TRUE , the PxeBisReply packet ﬁeld is valid. This ﬁeld is set to FALSE by the Start()
and Dhcp() functions, and can be set to TRUE orFALSE by the Discover() and SetPackets() functions.
IcmpErrorReceived Indicates whether the IcmpError ﬁeld has been updated. This ﬁeld is reset
toFALSE by the Start(), Dhcp(), Discover(), EFI_PXE_BASE_CODE_PROTOCOL.Mtftp() ,
EFI_PXE_BASE_CODE_PROTOCOL.UdpRead() , EFI_PXE_BASE_CODE_PROTOCOL.UdpWrite()
andEFI_PXE_BASE_CODE_PROTOCOL.Arp() functions. If an ICMP error is received, this ﬁeld will be set
toTRUE after the IcmpError ﬁeld is updated.
TftpErrorReceived Indicates whether the TftpError ﬁeld has been updated. This ﬁeld is reset to FALSE by the
Start() and Mtftp() functions. If a TFTP error is received, this ﬁeld will be set to TRUE after the TftpError ﬁeld
is updated.
24.3. PXE Base Code Protocol 890Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
MakeCallbacks When FALSE , callbacks will not be made. When TRUE , make callbacks to the PXE Base Code
Callback Protocol. This ﬁeld is reset to FALSE by the Start() function if the PXE Base Code Callback Protocol
is not available. It is reset to TRUE by the Start() function if the PXE Base Code Callback Protocol is available.
TTL The “time to live” ﬁeld of the IP header. This ﬁeld is initialized to DEFAULT_TTL (See “Related Deﬁnitions”)
by the Start() function and can be modiﬁed by the EFI_PXE_BASE_CODE_PROTOCOL.SetParameters() func-
tion.
ToS The type of service ﬁeld of the IP header. This ﬁeld is initialized to DEFAULT_ToS (See “Re-
lated Deﬁnitions”) by EFI_PXE_BASE_CODE_PROTOCOL.Start() , and can be modiﬁed with the
EFI_PXE_BASE_CODE_PROTOCOL.SetParameters() function.
StationIp The device’s current IP address. This ﬁeld is initialized to a zero address by Start() .
This ﬁeld is set when the EFI_PXE_BASE_CODE_PROTOCOL.Dhcp() function completes success-
fully. This ﬁeld can also be set by the EFI_PXE_BASE_CODE_PROTOCOL.SetStationIp() func-
tion. This ﬁeld must be set to a valid IP address by either Dhcp() or SetStationIp() be-
fore the EFI_PXE_BASE_CODE_PROTOCOL.Discover() ,EFI_PXE_BASE_CODE_PROTOCOL.Mtftp()
,EFI_PXE_BASE_CODE_PROTOCOL.UdpRead() ,EFI_PXE_BASE_CODE_PROTOCOL.UdpWrite() and
EFI_PXE_BASE_CODE_PROTOCOL.Arp() functions are called.
SubnetMask The device’s current subnet mask. This ﬁeld is initialized to a zero address by the Start() function. This
ﬁeld is set when the Dhcp() function completes successfully. This ﬁeld can also be set by the SetStationIp()
function. This ﬁeld must be set to a valid subnet mask by either Dhcp() orSetStationIp() before the Discover(),
Mtftp(), UdpRead(), UdpWrite(), orArp() functions are called.
DhcpDiscover Cached DHCP Discover packet. This ﬁeld is zero-ﬁlled by the Start() function, and is set
when the Dhcp() function completes successfully. The contents of this ﬁeld can replaced by the
DhcpAck Cached DHCP Ack packet. This ﬁeld is zero-ﬁlled by the Start() function, and is set when the Dhcp()
function completes successfully. The contents of this ﬁeld can be replaced by the SetPackets() function.
ProxyOffer Cached Proxy Offer packet. This ﬁeld is zero-ﬁlled by the Start() function, and is set when the Dhcp()
PxeDiscover Cached PXE Discover packet. This ﬁeld is zero-ﬁlled by the Start() function, and is set when the
Discover() function completes successfully. The contents of this ﬁeld can be replaced by the SetPackets()
function.
PxeReply Cached PXE Reply packet. This ﬁeld is zero-ﬁlled by the Start() function, and is set when the Discover()
PxeBisReply Cached PXE BIS Reply packet. This ﬁeld is zero-ﬁlled by the Start() function, and is set when the
Discover() function completes successfully. This ﬁeld can be replaced by the SetPackets() function.
IpFilter The current IP receive ﬁlter settings. The receive ﬁlter is disabled and the number of IP re-
ceive ﬁlters is set to zero by the EFI_PXE_BASE_CODE_PROTOCOL.Start() function, and is set by the
EFI_PXE_BASE_CODE_PROTOCOL.SetIpFilter() function.
ArpCacheEntries The number of valid entries in the ARP cache. This ﬁeld is reset to zero by the Start() function.
ArpCache Array of cached ARP entries.

function.
RouteTableEntries The number of valid entries in the current route table. This ﬁeld is reset to zero by the Start()
function.
RouteTable Array of route table entries.
IcmpError ICMP error packet. This ﬁeld is updated when an ICMP error is received and is undeﬁned until the ﬁrst
ICMP error is received. This ﬁeld is zero-ﬁlled by the Start() function.
24.3. PXE Base Code Protocol 891Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TftpError TFTP error packet. This ﬁeld is updated when a TFTP error is received and is undeﬁned until the ﬁrst
TFTP error is received. This ﬁeld is zero-ﬁlled by the Start() function.
// EFI_PXE_BASE_CODE_UDP_PORT
typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
// EFI_IPv4_ADDRESS andEFI_IPv6_ADDRESS
UINT8 Addr[4];
} EFI_IPv4_ADDRESS;
UINT8 Addr[16];
} EFI_IPv6_ADDRESS;
// EFI_IP_ADDRESS
UINT32 Addr[4];
EFI_IPv4_ADDRESS v4;
EFI_IPv6_ADDRESS v6;
} EFI_IP_ADDRESS;
// EFI_MAC_ADDRESS
UINT8 Addr[32];
} EFI_MAC_ADDRESS;
24.3.2 DHCP Packet Data Types
This section deﬁnes the data types for DHCP packets, ICMP error packets, and TFTP error packets. All of these are
byte-packed data structures.
NOTE: All the multibyte ﬁelds in these structures are stored in network order .
// EFI_PXE_BASE_CODE_DHCPV4_PACKET
UINT8 BootpOpcode;
UINT8 BootpHwType;
UINT8 BootpHwAddrLen;
UINT8 BootpGateHops;
UINT32 BootpIdent;
UINT16 BootpSeconds;
UINT16 BootpFlags;
UINT8 BootpCiAddr[4];
UINT8 BootpYiAddr[4];
UINT8 BootpSiAddr[4];
UINT8 BootpGiAddr[4];
24.3. PXE Base Code Protocol 892Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT8 BootpHwAddr[16];
UINT8 BootpSrvName[64];
UINT8 BootpBootFile[128];
UINT32 DhcpMagik;
UINT8 DhcpOptions[56];
} EFI_PXE_BASE_CODE_DHCPV4_PACKET;
//***********************************************
// DHCPV6 Packet structure
UINT32 MessageType:8;
UINT32 TransactionId:24;
UINT8 DhcpOptions[1024];
} EFI_PXE_BASE_CODE_DHCPV6_PACKET;
// EFI_PXE_BASE_CODE_PACKET
UINT8 Raw[1472];
EFI_PXE_BASE_CODE_DHCPV4_PACKET Dhcpv4;
EFI_PXE_BASE_CODE_DHCPV6_PACKET Dhcpv6;
} EFI_PXE_BASE_CODE_PACKET;
// EFI_PXE_BASE_CODE_ICMP_ERROR
UINT8 Code;
UINT16 Checksum;
union {
UINT32 reserved;
UINT32 Mtu;
UINT32 Pointer;
struct {
UINT16 Identifier;
UINT16 Sequence;
} Echo;
} u;
UINT8 Data[494];
} EFI_PXE_BASE_CODE_ICMP_ERROR;
// EFI_PXE_BASE_CODE_TFTP_ERROR
UINT8 ErrorCode;
CHAR8 ErrorString[127];
} EFI_PXE_BASE_CODE_TFTP_ERROR;
24.3. PXE Base Code Protocol 893Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.3.3 IP Receive Filter Settings
This section deﬁnes the data types for IP receive ﬁlter settings.
#define EFI_PXE_BASE_CODE_MAX_IPCNT8
// EFI_PXE_BASE_CODE_IP_FILTER
UINT8 Filters;
UINT8 IpCnt;
UINT16 reserved;
EFI_IP_ADDRESS IpList[EFI_PXE_BASE_CODE_MAX_IPCNT];
} EFI_PXE_BASE_CODE_IP_FILTER;
#define EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP 0x0001
#define EFI_PXE_BASE_CODE_IP_FILTER_BROADCAST 0x0002
#define EFI_PXE_BASE_CODE_IP_FILTER_PROMISCUOUS 0x0004
#define EFI_PXE_BASE_CODE_IP_FILTER_PROMISCUOUS_MULTICAST 0x0008
24.3.4 ARP Cache Entries
This section deﬁnes the data types for ARP cache entries, and route table entries.
// EFI_PXE_BASE_CODE_ARP\_ENTRY
EFI_IP_ADDRESS IpAddr;
EFI_MAC_ADDRESS MacAddr;
} EFI_PXE_BASE_CODE_ARP\_ENTRY;
// EFI_PXE_BASE_CODE_ROUTE_ENTRY
EFI_IP_ADDRESS GwAddr;
} EFI_PXE_BASE_CODE_ROUTE_ENTRY;
24.3.5 Filter Operations for UDP Read/Write Functions
This section deﬁnes the types of ﬁlter operations that can be used with the
EFI_PXE_BASE_CODE_PROTOCOL.UdpRead() and EFI_PXE_BASE_CODE_PROTOCOL.UdpWrite() func-
tions.
#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_SRC_IP 0x0001
#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_SRC_PORT 0x0002
#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_DEST_IP 0x0004
#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_DEST_PORT 0x0008
#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_USE_FILTER 0x0010
#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_MAY_FRAGMENT 0x0020
24.3. PXE Base Code Protocol 894Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define DEFAULT_TTL 16
#define DEFAULT_ToS 0
The following table deﬁnes values for the PXE DHCP and Bootserver Discover packet tags that are speciﬁc to the
UEFI environment. Complete deﬁnitions of all PXE tags are deﬁned in the Table below, “PXE DHCP Options (Full
List),” in the PXE Speciﬁcation.
Table 24.13: PXE Tag Deﬁnitions for EFI
Tag
NameTag # Length Data Field
Client
Net-
work
Inter-
face
Identi-
ﬁer94
[0x5E]3
[0x03]Type (1), MajorVer (1), MinorVer (1)
Type is a one byte ﬁeld that identiﬁes the network interface that will be used by the
downloaded program. Type is followed by two one byte version number ﬁelds,
MajorVer and MinorVer.
Type
UNDI (1) = 0x01
Versions
16-bit UNDI: MajorVer = 0x02. MinorVer = 0x00
PXE-2.0 16-bit UNDI: MajorVer = 0x02, MinorVer = 0x01
32/64-bit UNDI & H/W UNDI: MajorVer = 0x03, MinorVer = 0x00
Client
Sys-
tem
Archi-
tec-
ture93
[0x5D]2
[0x02]Type (2)
Type is a two byte, network order, ﬁeld that identiﬁes the processor and
programming environment of the client system.
For the various architecture type encodings, see the table “Processor Architecture
Types” at “Links to UEFI-Related Documents” ( http:// ueﬁ.org/ueﬁ) under the
heading “Processor Architecture Types”
Class
Identi-
ﬁer60
[0x3C]32
[0x20]“PXE Client:Arch:xxx xx:UNDI:yyyzzz”
“PXEClient:. . . ” is used to identify communication between PXE clients and servers.
Information from tags 93 & 94 is embedded in the Class Identiﬁer string. (The
strings deﬁned in this tag are case sensitive and must not be NU LL-terminated.)
xxxxx = ASCII representation of Client System Architecture.
yyyzzz = ASCII representation of Client Network Interface Identiﬁer
version numbers MajorVer(yyy) and MinorVer(zzz).
Example
“PX EClient:Arch:00 002:UNDI:00300” identiﬁes an IA64 PC w/ 32/64-bit UNDI
The basic mechanisms and ﬂow for remote booting in UEFI are identical to the remote boot functionality described
in detail in the PXE Speciﬁcation. However, the actual execution environment, linkage, and calling conventions are
replaced and enhanced for the UEFI environment.
The DHCP Option for the Client System Architecture is used to inform the DHCP server if the client is a UEFI
24.3. PXE Base Code Protocol 895Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
environment in supported systems. The server may use this information to provide default images if it does not have a
speciﬁc boot proﬁle for the client.
The DHCP Option for Client Network Interface Identiﬁer is used to inform the DHCP server of the client underlying
network interface information. If the NII protocol is present, such information will be acquired by this protocol.
Otherwise, Type = 0x01, MajorVer=0x03, MinorVer=0x00 will be the default value.
A handle that supports EFI_PXE_BASE_CODE_PROTOCOL is required to support EFI_LOAD_FILE_PROTOCOL
. The EFI_LOAD_FILE_PROTOCOL function is used by the ﬁrmware to load ﬁles from devices that do not support
ﬁle system type accesses. Speciﬁcally, the ﬁrmware’s boot manager invokes LoadFile() with BootPolicy being TRUE
when attempting to boot from the device. The ﬁrmware then loads and transfers control to the downloaded PXE
boot image. Once the remote image is successfully loaded, it may utilize the EFI_PXE_BASE_CODE_PROTOCOL

interfaces, or even the EFI_SIMPLE_NETWORK_PROTOCOL interfaces, to continue the remote process.
24.3.6 EFI_PXE_BASE_CODE_PROTOCOL.Start()
Summary
Enables the use of the PXE Base Code Protocol functions.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_START) (
IN EFI_PXE_BASE_CODE_PROTOCOL *This,
IN BOOLEAN UseIpv6
);
This Pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
UseIpv6 Speciﬁes the type of IP addresses that are to be used during the session that is being started. Set to TRUE
for IPv6 addresses, and FALSE for IPv4 addresses.
This function enables the use of the PXE Base Code Protocol functions. If the Started ﬁeld of the
EFI_PXE_BASE_CODE_MODE structure is already TRUE , then EFI_ALREADY_STARTED will be returned.
IfUseIpv6 isTRUE , then IPv6 formatted addresses will be used in this session. If UseIpv6 isFALSE , then
IPv4 formatted addresses will be used in this session. If UseIpv6 isTRUE , and the Ipv6Supported ﬁeld of the
EFI_PXE_BASE_CODE_MODE structure is FALSE , then EFI_UNSUPPORTED will be returned. If there is
not enough memory or other resources to start the PXE Base Code Protocol, then EFI_OUT_OF_RESOURCES
will be returned. Otherwise, the PXE Base Code Protocol will be started, and all of the ﬁelds of the
EFI_PXE_BASE_CODE_MODE structure will be initialized as follows:
Started Set to TRUE.
Ipv6Supported Unchanged.
Ipv6Available Unchanged.
UsingIpv6 Set to *UseIpv6*.
BisSupported Unchanged.
BisDetected Unchanged.
AutoArp Set to TRUE.
SendGUID Set to FALSE.
TTL Set to DEFAULT_TTL.
ToS Set to DEFAULT_ToS.
DhcpCompleted Set to FALSE.
24.3. PXE Base Code Protocol 896Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ProxyOfferReceived Set to FALSE.
StationIp Set to an address of all zeros.
SubnetMask Set to a subnet mask of all zeros.
DhcpDiscover Zero-filled.
DhcpAck Zero-filled.
ProxyOffer Zero-filled.
PxeDiscoverValid Set to FALSE.
PxeDiscover Zero-filled.
PxeReplyValid Set to FALSE.
PxeReply Zero-filled.
PxeBisReplyValid Set to FALSE.
PxeBisReply Zero-filled.
IpFilter Set the *Filters*field to 0 andthe*IpCnt*field to 0.
ArpCacheEntries Set to 0.
ArpCache Zero-filled.
RouteTableEntries Set to 0.
RouteTable Zero-filled.
IcmpErrorReceived Set to FALSE.
IcmpError Zero-filled.
TftpErroReceived Set to FALSE.
TftpError Zero-filled.
MakeCallback Set to TRUE ifthe PXE Base Code Callback Protocol is
available. Set to FALSE ifthe PXE Base Code Callback
Protocol is notavailable.
EFI_SUCCESS The PXE Base Code Protocol was started.
EFI_INV ALID_PARAMETER The This parameter is NULL or does not point to a valid
EFI_PXE_BASE_CODE_PROTOCOL structure.
EFI_UNSUPPORTED UseIpv6 isTRUE, but the Ipv6Supported ﬁeld of the EFI_PX
E_BASE_CODE_MODE structure is FALSE .
EFI_ALREADY_STARTED The PXE Base Code Protocol is already in the started state.
EFI_DEVICE_ERROR The network device encountered an error during this operation.
EFI_OUT_OF_RESOURCES Could not allocate enough memory or other resources to start the PXE Base
Code Protocol.
24.3.7 EFI_PXE_BASE_CODE_PROTOCOL.Stop()
Summary
Disables the use of the PXE Base Code Protocol functions.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_STOP) (
IN EFI_PXE_BASE_CODE_PROTOCOL *This
);
24.3. PXE Base Code Protocol 897Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function stops all activity on the network device. All the resources allocated in
EFI_PXE_BASE_CODE_PROTOCOL.Start() are released, the Started ﬁeld of the EFI_PXE_BASE_CODE_MODE
structure is set to FALSE and EFI_SUCCESS is returned. If the Started ﬁeld of the EFI_PXE_BASE_CODE_MODE
structure is already FALSE , then EFI_NOT_STARTED will be returned.
EFI_SUCCESS The PXE Base Code Protocol was stopped.
EFI_NOT_STARTED The PXE Base Code Protocol is already in the stopped state.
24.3.8 EFI_PXE_BASE_CODE_PROTOCOL.Dhcp()
Summary
Attempts to complete a DHCPv4 D.O.R.A. (discover / offer / request / acknowledge) or DHCPv6 S.A.R.R (solicit /
advertise / request / reply) sequence.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_DHCP) (
IN BOOLEAN SortOffers
);
SortOffers TRUE if the offers received should be sorted. Set to FALSE to try the offers in the order that they are
received.
This function attempts to complete the DHCP sequence. If this sequence is completed, then EFI_SUCCESS is re-
turned, and the DhcpCompleted, ProxyOfferReceived, StationIp, SubnetMask, DhcpDiscover, DhcpAck, andProxyOf-
ferﬁelds of the EFI_PXE_BASE_CODE_MODE structure are ﬁlled in.
IfSortOffers isTRUE , then the cached DHCP offer packets will be sorted before they are tried. If SortOffers is
FALSE , then the cached DHCP offer packets will be tried in the order in which they are received. Please see the
Preboot Execution Environment (PXE) Speciﬁcation for additional details on the implementation of DHCP.
This function can take at least 31 seconds to timeout and return control to the caller. If the DHCP sequence does not
complete, then EFI_TIMEOUT will be returned.
If the Callback Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then the
DHCP sequence will be stopped and EFI_ABORTED will be returned.
EFI_SUCCESS Valid DHCP has completed.
EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state.
24.3. PXE Base Code Protocol 898Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.16 – continued from previous page
EFI_OUT_OF_RESOURCES Could not allocate enough memory to complete the DHCP Protocol.
EFI_ABORTED The callback function aborted the DHCP Protocol.
EFI_TIMEOUT The DHCP Protocol timed out.
EFI_ICMP_ERROR An ICMP error packet was received during the DHCP session. The ICMP
error packet has been cached in the EFI_PXE_BASE_CODE_MODE. Icm-
pError packet structure. Information about ICMP packet contents can be
found in RFC 792.
EFI_NO_RESPONSE Valid PXE offer was not received.
24.3.9 EFI_PXE_BASE_CODE_PROTOCOL.Discover()
Summary
Attempts to complete the PXE Boot Server and/or boot image discovery sequence.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_DISCOVER) (
IN UINT16 Type,
IN UINT16 *Layer,
IN BOOLEAN UseBis,
IN EFI_PXE_BASE_CODE_DISCOVER_INFO *Info OPTIONAL
);
Type The type of bootstrap to perform. See “Related Deﬁnitions” below.
Layer Pointer to the boot server layer number to discover, which must be PXE_BOOT_LAYER_INITIAL when
a new server type is being discovered. This is the only layer type that will perform multicast and broadcast
discovery. All other layer types will only perform unicast discovery. If the boot server changes Layer, then the
new Layer will be returned.
UseBis TRUE if Boot Integrity Services are to be used. FALSE otherwise.
Info Pointer to a data structure that contains additional information on the type of discovery operation that is to be
performed. If this ﬁeld is NULL, then the contents of the cached DhcpAck andProxyOffer packets will be used.
// Bootstrap Types
#define EFI_PXE_BASE_CODE_BOOT_TYPE_BOOTSTRAP 0
#define EFI_PXE_BASE_CODE_BOOT_TYPE_MS_WINNT_RIS 1
#define EFI_PXE_BASE_CODE_BOOT_TYPE_INTEL_LCM 2
#define EFI_PXE_BASE_CODE_BOOT_TYPE_DOSUNDI 3
24.3. PXE Base Code Protocol 899Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_PXE_BASE_CODE_BOOT_TYPE_NEC_ESMPRO 4
#define EFI_PXE_BASE_CODE_BOOT_TYPE_IBM_WSoD 5
#define EFI_PXE_BASE_CODE_BOOT_TYPE_IBM_LCCM 6
#define EFI_PXE_BASE_CODE_BOOT_TYPE_CA_UNICENTER_TNG 7
#define EFI_PXE_BASE_CODE_BOOT_TYPE_HP_OPENVIEW 8
#define EFI_PXE_BASE_CODE_BOOT_TYPE_ALTIRIS_9 9
#define EFI_PXE_BASE_CODE_BOOT_TYPE_ALTIRIS_10 10
#define EFI_PXE_BASE_CODE_BOOT_TYPE_ALTIRIS_11 11
#define EFI_PXE_BASE_CODE_BOOT_TYPE_NOT_USED_12 12
#define EFI_PXE_BASE_CODE_BOOT_TYPE_REDHAT_INSTALL 13
#define EFI_PXE_BASE_CODE_BOOT_TYPE_REDHAT_BOOT 14
#define EFI_PXE_BASE_CODE_BOOT_TYPE_REMBO 15
#define EFI_PXE_BASE_CODE_BOOT_TYPE_BEOBOOT 16
//
// Values 17 through 32767 are reserved.
// Values 32768 through 65279 are forvendor use.

//
// Values 65280 through 65534 are reserved.
//
#define EFI_PXE_BASE_CODE_BOOT_TYPE_PXETEST 65535
#define EFI_PXE_BASE_CODE_BOOT_LAYER_MASK 0x7FFF
#define EFI_PXE_BASE_CODE_BOOT_LAYER_INITIAL 0x0000
// EFI_PXE_BASE_CODE_DISCOVER_INFO
BOOLEAN UseMCast;
BOOLEAN UseBCast;
BOOLEAN UseUCast;
BOOLEAN MustUseList;
EFI_IP_ADDRESS ServerMCastIp;
UINT16 IpCnt;
EFI_PXE_BASE_CODE_SRVLIST SrvList[IpCnt];
} EFI_PXE_BASE_CODE_DISCOVER_INFO;
// EFI_PXE_BASE_CODE_SRVLIST
UINT16 Type;
BOOLEAN AcceptAnyResponse;
UINT8 reserved;
} EFI_PXE_BASE_CODE_SRVLIST;
This function attempts to complete the PXE Boot Server and/or boot image discovery sequence. If this se-
quence is completed, then EFI_SUCCESS is returned, and the PxeDiscoverValid, PxeDiscover, PxeReplyReceived,
andPxeReply ﬁelds of the EFI_PXE_BASE_CODE_MODE in Network Protocols — SNP , PXE, BIS and HTTP
Boot structure are ﬁlled in. If UseBis isTRUE , then the PxeBisReplyReceived and PxeBisReply ﬁelds of the
EFI_PXE_BASE_CODE_MODE structure will also be ﬁlled in. If UseBis isFALSE , then PxeBisReplyValid will
be set to FALSE .
In the structure referenced by parameter Info, the PXE Boot Server list, SrvList[], has two uses: It is the Boot Server
IP address list used for unicast discovery (if the UseUCast ﬁeld is TRUE ), and it is the list used for Boot Server
24.3. PXE Base Code Protocol 900Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
veriﬁcation (if the MustUseList ﬁeld is TRUE ). Also, if the MustUseList ﬁeld in that structure is TRUE and the
AcceptAnyResponse ﬁeld in the SrvList[] array is TRUE , any Boot Server reply of that type will be accepted. If the
AcceptAnyResponse ﬁeld is FALSE , only responses from Boot Servers with matching IP addresses will be accepted.
This function can take at least 10 seconds to timeout and return control to the caller. If the Discovery sequence does not
complete, then EFI_TIMEOUT will be returned. Please see the Preboot Execution Environment (PXE) Speciﬁcation
for additional details on the implementation of the Discovery sequence.
If the Callback Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then the Dis-
covery sequence is stopped and EFI_ABORTED will be returned.
EFI_SUCCESS The Discovery sequence has been completed.
One or more of the following conditions was TRUE :
• The This parameter was NULL
• The This parameter did not point to a valid
EFI_PXE_BASE_CODE_PROTOCOL structure
• The Layer parameter was NULL
• The Info->ServerMCastIp parameter does not contain a valid multicast
IP address
• The Info->UseUCast parameter is not FALSE and the Info->IpCnt
parameter is zero
One or more of the IP addresses in the Info->SrvList[] array is not a valid
unicast IP address.
EFI_OUT_OF_RESOURCES Could not allocate enough memory to complete Discovery.
EFI_ABORTED The callback function aborted the Discovery sequence.
EFI_TIMEOUT The Discovery sequence timed out.
EFI_ICMP_ERROR An ICMP error packet was received during the PXE discov-
ery session. The ICMP error packet has been cached in the
EFI_PXE_BASE_CODE_MODE. IcmpError packet structure. Infor-
mation about ICMP packet contents can be found in RFC 792.
24.3.10 EFI_PXE_BASE_CODE_PROTOCOL.Mtftp()
Summary
Used to perform TFTP and MTFTP services.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_MTFTP) (
IN EFI_PXE_BASE_CODE_TFTP_OPCODE Operation,
IN OUT VOID *BufferPtr, OPTIONAL
IN BOOLEAN Overwrite,
IN OUT UINT64 *BufferSize,
IN UINTN *BlockSize, OPTIONAL
24.3. PXE Base Code Protocol 901Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_IP_ADDRESS *ServerIp,
IN CHAR8 *Filename, OPTIONAL
IN EFI_PXE_BASE_CODE_MTFTP_INFO *Info, OPTIONAL
IN BOOLEAN DontUseBuffer
);
Operation The type of operation to perform. See “Related Deﬁnitions” below for the list of operation types.
BufferPtr A pointer to the data buffer. Ignored for read ﬁle if DontUseBuffer isTRUE .
Overwrite Only used on write ﬁle operations. TRUE if a ﬁle on a remote server can be overwritten.
BufferSize For get-ﬁle-size operations, BufferSize returns the size of the requested ﬁle. For read-ﬁle and write-ﬁle
operations, this parameter is set to the size of the buffer speciﬁed by the BufferPtr parameter. For read-ﬁle
operations, if EFI_BUFFER_TOO_SMALL is returned, BufferSize returns the size of the requested ﬁle.
BlockSize The requested block size to be used during a TFTP transfer. This must be at least 512. If this ﬁeld is
NULL, then the largest block size supported by the implementation will be used.
ServerIp The TFTP / MTFTP server IP address.
Filename A Null-terminated ASCII string that speciﬁes a directory name or a ﬁle name. This is ignored by MTFTP
read directory.
Info Pointer to the MTFTP information. This information is required to start or join a multicast TFTP session. It is
also required to perform the “get ﬁle size” and “read directory” operations of MTFTP. See “Related Deﬁnitions”
below for the description of this data structure.
DontUseBuffer Set to FALSE for normal TFTP and MTFTP read ﬁle operation. Setting this to TRUE will cause
TFTP and MTFTP read ﬁle operations to function without a receive buffer, and all of the received packets are
passed to the Callback Protocol which is responsible for storing them. This ﬁeld is only used by TFTP and
MTFTP read ﬁle.
// EFI_PXE_BASE_CODE_TFTP_OPCODE
EFI_PXE_BASE_CODE_TFTP_FIRST,
EFI_PXE_BASE_CODE_TFTP_GET_FILE_SIZE,
EFI_PXE_BASE_CODE_TFTP_READ_FILE,
EFI_PXE_BASE_CODE_TFTP_WRITE_FILE,
EFI_PXE_BASE_CODE_TFTP_READ_DIRECTORY,
EFI_PXE_BASE_CODE_MTFTP_GET_FILE_SIZE,
EFI_PXE_BASE_CODE_MTFTP_READ_FILE,
EFI_PXE_BASE_CODE_MTFTP_READ_DIRECTORY,
EFI_PXE_BASE_CODE_MTFTP_LAST
} EFI_PXE_BASE_CODE_TFTP_OPCODE;
// EFI_PXE_BASE_CODE_MTFTP_INFO
EFI_IP_ADDRESS MCastIp;
EFI_PXE_BASE_CODE_UDP_PORT CPort;
24.3. PXE Base Code Protocol 902Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_PXE_BASE_CODE_UDP_PORT SPort;
UINT16 ListenTimeout;
UINT16 TransmitTimeout;
} EFI_PXE_BASE_CODE_MTFTP_INFO;
MCastIp File multicast IP address. This is the IP address to which the server will send the requested ﬁle.
CPort Client multicast listening port. This is the UDP port to which the server will send the requested ﬁle.
SPort Server multicast listening port. This is the UDP port on which the server listens for multicast open requests
and data acks.
ListenTimeout The number of seconds a client should listen for an active multicast session before requesting a new
multicast session.
TransmitTimeout The number of seconds a client should wait for a packet from the server before retransmitting the
previous open request or data ack packet.
This function is used to perform TFTP and MTFTP services. This includes the TFTP operations to get the size of a
ﬁle, read a directory, read a ﬁle, and write a ﬁle. It also includes the MTFTP operations to get the size of a ﬁle, read
a directory, and read a ﬁle. The type of operation is speciﬁed by Operation . If the callback function that is invoked
during the TFTP/MTFTP operation does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE,
then EFI_ABORTED will be returned.
For read operations, the return data will be placed in the buffer speciﬁed by BufferPtr . If BufferSize is too small
to contain the entire downloaded ﬁle, then EFI_BUFFER_TOO_SMALL will be returned and BufferSize will be set
to zero or the size of the requested ﬁle (the size of the requested ﬁle is only returned if the TFTP server supports
TFTP options). If BufferSize is large enough for the read operation, then BufferSize will be set to the size of the
downloaded ﬁle, and EFI_SUCCESS will be returned. Applications using the PxeBc.Mtftp() services should use the
get-ﬁle-size operations to determine the size of the downloaded ﬁle prior to using the read-ﬁle operations–especially
when downloading large (greater than 64 MiB) ﬁles–instead of making two calls to the read-ﬁle operation. Following

this recommendation will save time if the ﬁle is larger than expected and the TFTP server does not support TFTP
option extensions. Without TFTP option extension support, the client has to download the entire ﬁle, counting and
discarding the received packets, to determine the ﬁle size.
For write operations, the data to be sent is in the buffer speciﬁed by BufferPtr .BufferSize speciﬁes the number of bytes
to send. If the write operation completes successfully, then EFI_SUCCESS will be returned.
For TFTP “get ﬁle size” operations, the size of the requested ﬁle or directory is returned in BufferSize, and
EFI_SUCCESS will be returned. If the TFTP server does not support options, the ﬁle will be downloaded into a
bit bucket and the length of the downloaded ﬁle will be returned. For MTFTP “get ﬁle size” operations, if the MTFTP
server does not support the “get ﬁle size” option, EFI_UNSUPPORTED will be returned.
This function can take up to 10 seconds to timeout and return control to the caller. If the TFTP sequence does not
complete, EFI_TIMEOUT will be returned.
TFTP sequence is stopped and EFI_ABORTED will be returned.
The format of the data returned from a TFTP read directory operation is a null-terminated ﬁlename followed by
a null-terminated information string, of the form “size year-month-day hour:minute:second” (i.e., %d %d-%d-%d
%d:%d:%f - note that the seconds ﬁeld can be a decimal number), where the date and time are UTC. For an MTFTP
read directory command, there is additionally a null-terminated multicast IP address preceding the ﬁlename of the form
%d.%d.%d.%d for IP v4. The ﬁnal entry is itself null-terminated, so that the ﬁnal information string is terminated with
two null octets.
24.3. PXE Base Code Protocol 903Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The TFTP/MTFTP operation was completed.
• The Operation parameter was not one of the listed
EFI_PXE_BASE_CODE_TFTP_OPCODE constants
• The BufferPtr parameter was NULL and the DontUseBuffer parameter
wasFALSE
• The BufferSize parameter was NULL
• The BlockSize parameter was not NULL and * BlockSize was less than
512
• The ServerIp parameter was NULL or did not contain a valid unicast IP
address
• The Filename parameter was NULL for a ﬁle transfer or information
request
• The Info parameter was NULL for a multicast request
The Info->MCastIp parameter is not a valid multicast IP address
EFI_BUFFER_TOO_SMALL The buffer is not large enough to complete the read operation.
EFI_ABORTED The callback function aborted the TFTP/MTFTP operation.
EFI_TIMEOUT The TFTP/MTFTP operation timed out.
EFI_TFTP_ERROR A TFTP error packet was received during the MTFTP session. The TFTP
error packet has been cached in the EFI_PXE_BASE_CODE_MODE. Tft-
pError packet structure. Information about TFTP error packet contents can
be found in RFC 1350.
EFI_ICMP_ERROR An ICMP error packet was received during the MTFTP session. The ICMP
24.3.11 EFI_PXE_BASE_CODE_PROTOCOL.UdpWrite()
Summary
Writes a UDP packet to the network interface.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_UDP_WRITE) (
IN UINT16 OpFlags,
IN EFI_IP_ADDRESS *DestIp,
IN EFI_PXE_BASE_CODE_UDP_PORT *DestPort,
IN EFI_IP_ADDRESS *GatewayIp, OPTIONAL
IN EFI_IP_ADDRESS *SrcIp, OPTIONAL
24.3. PXE Base Code Protocol 904Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN OUT EFI_PXE_BASE_CODE_UDP_PORT *SrcPort, OPTIONAL
IN UINTN *HeaderSize, OPTIONAL
IN VOID *HeaderPtr, OPTIONAL
IN VOID *BufferPtr
);
OpFlags The UDP operation ﬂags. If MAY_FRAGMENT is set, then if required, this UDP write operation may be
broken up across multiple packets.
DestIp The destination IP address.
DestPort The destination UDP port number.
GatewayIp The gateway IP address. If DestIp is not in the same subnet as StationIp, then this gateway IP address
will be used. If this ﬁeld is NULL, and the DestIp is not in the same subnet as StationIp, then the RouteTable
will be used.
SrcIp The source IP address. If this ﬁeld is NULL, then StationIp will be used as the source IP address.
SrcPort The source UDP port number. If OpFlags has ANY_SRC_PORT set or SrcPort is NULL, then a source UDP
port will be automatically selected. If a source UDP port was automatically selected, and SrcPort is not NULL,
then it will be returned in SrcPort .
HeaderSize An optional ﬁeld which may be set to the length of a header at HeaderPtr to be preﬁxed to the data at
BufferPtr.
HeaderPtr IfHeaderSize is not NULL, a pointer to a header to be preﬁxed to the data at BufferPtr .
BufferSize A pointer to the size of the data at BufferPtr .
BufferPtr A pointer to the data to be written.
This function writes a UDP packet speciﬁed by the (optional HeaderPtr and) BufferPtr parameters to the network
interface. The UDP header is automatically built by this routine. It uses the parameters OpFlags, DestIp, DestPort,
GatewayIp, SrcIp, andSrcPort to build this header. If the packet is successfully built and transmitted through the net-
work interface, then EFI_SUCCESS will be returned. If a timeout occurs during the transmission of the packet, then
EFI_TIMEOUT will be returned. If an ICMP error occurs during the transmission of the packet, then the IcmpError-
Received ﬁeld is set to TRUE , the IcmpError ﬁeld is ﬁlled in and EFI_ICMP_ERROR will be returned. If the Callback
Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then EFI_ABORTED will
be returned.
EFI_SUCCESS The UDP Write operation was completed.
24.3. PXE Base Code Protocol 905Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.19 – continued from previous page
• Reserved bits in the OpFlags parameter were not set to zero - The DestIp
parameter was NULL
• The DestPort parameter was NULL
• The GatewayIp parameter was not NULL and did not contain a valid
• The HeaderSize parameter was not NULL and * HeaderSize is zero
• The HeaderSize parameter was not zero and the HeaderPtr parameter
was *NULL
• The BufferSize parameter was not zero and the BufferPtr parameter was
*NULL
EFI_BAD_BUFFER_SIZE The buffer is too long to be transmitted.
EFI_ABORTED The callback function aborted the UDP Write operation.
EFI_TIMEOUT The UDP Write operation timed out.
EFI_ICMP_ERROR An ICMP error packet was received during the UDP write
session. The ICMP error packet has been cached in the
24.3.12 EFI_PXE_BASE_CODE_PROTOCOL.UdpRead()
Summary
Reads a UDP packet from the network interface.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_UDP_READ) (
IN OUT EFI_IP_ADDRESS *DestIp, OPTIONAL
IN OUT EFI_PXE_BASE_CODE_UDP_PORT *DestPort, OPTIONAL
IN OUT EFI_IP_ADDRESS *SrcIp, OPTIONAL
);
OpFlags The UDP operation ﬂags.
24.3. PXE Base Code Protocol 906Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SrcIp The source IP address.
SrcPort The source UDP port number.
HeaderSize An optional ﬁeld which may be set to the length of a header to be put in HeaderPtr .
HeaderPtr IfHeaderSize is not NULL, a pointer to a buffer to hold the HeaderSize bytes which follow the UDP
header.
BufferSize On input, a pointer to the size of the buffer at BufferPtr . On output, the size of the data written to BufferPtr .
BufferPtr A pointer to the data to be read.

);
header.
This function reads a UDP packet from a network interface. The data contents are returned in (the optional HeaderPtr
and) BufferPtr, and the size of the buffer received is returned in BufferSize . If the input BufferSize is smaller than the
UDP packet received (less optional HeaderSize ), it will be set to the required size, and EFI_BUFFER_TOO_SMALL
will be returned. In this case, the contents of BufferPtr are undeﬁned, and the packet is lost. If a UDP packet
is successfully received, then EFI_SUCCESS will be returned, and the information from the UDP header will be
returned in DestIp, DestPort, SrcIp, andSrcPort if they are not NULL. Depending on the values of OpFlags and the
DestIp, DestPort, SrcIp, andSrcPort input values, different types of UDP packet receive ﬁltering will be performed.
The following tables summarize these receive ﬁlter operations.
Destination IP Filter Operation
Table 24.20: Destination IP Filter Operation
OpFlags
USE_FILTEROpFlags
ANY_DEST_IPDestIp Action
0 0 NULL Receive a packet sent to StationIp .
0 1 NULL Receive a packet sent to any IP address.
1 x NULL Receive a packet whose destination IP address passes
the IP ﬁlter.
0 0 not
NULLReceive a packet whose destination IP address matches
DestIp .
0 1 not
NULLReceive a packet sent to any IP address and, return the
destination IP address in DestIp .
1 x not
NULLReceive a packet whose destination IP address passes
the IP ﬁlter, and return the destination IP address in Des-
tIp.
Table 24.21: Destination UDP Port Filter Operation
OpFlags
ANY_DEST_PORTDestPort Action
0 NULL Return E FI_INVALID_PARAMETER .
1 NULL Receive a packet sent to any UDP port.
0 not NULL Receive a packet whose destination Port matches DestPort .
1 not NULL Receive a packet sent to any UDP port, and return the destination
port in DestPort
24.3. PXE Base Code Protocol 907Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.22: Source IP Filter Operation
OpFlags
ANY_SRC_IPSrcIp Action
1 NULL Receive a packet sent from any IP address.
0 not NULL Receive a packet whose source IP address matches SrcIp .
1 not NULL Receive a packet sent from any IP address, and return the source IP address in
SrcIp .
Table 24.23: Source UDP Port Filter Operation
OpFlags
ANY_SRC_PORTSrcPort Action
1 NULL Receive a packet sent from any UDP port.
0 not NULL Receive a packet whose source UDP port matches SrcPort .
1 not NULL Receive a packet sent from any UDP port, and return the source
UPD port in SrcPort .
EFI_SUCCESS The UDP Read operation was completed.
• Reserved bits in the OpFlags parameter were not set to zero
• The HeaderSize parameter is not NULL and * HeaderSize is zero
• The HeaderSize parameter is not NULL L and the HeaderPtr parameter is
NULL
• The BufferPtr parameter is NULL
EFI_BUFFER_TOO_SMALL The packet is larger than Buffer can hold.
EFI_ABORTED The callback function aborted the UDP Read operation.
EFI_TIMEOUT The UDP Read operation timed out.
24.3.13 EFI_PXE_BASE_CODE_PROTOCOL.SetIpFilter()
Summary
Updates the IP receive ﬁlters of a network device and enables software ﬁltering.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_SET_IP_FILTER) (
24.3. PXE Base Code Protocol 908Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_PXE_BASE_CODE_IP_FILTER *NewFilter
);
NewFilter Pointer to the new set of IP receive ﬁlters.
The NewFilter ﬁeld is used to modify the network device’s current IP receive ﬁlter settings and to enable a soft-
ware ﬁlter. This function updates the IpFilter ﬁeld of the EFI_PXE_BASE_CODE_MODE in Network Protocols
— SNP , PXE, BIS and HTTP Boot structure with the contents of NewIpFilter . The software ﬁlter is used when the
USE_FILTER in OpFlags is set to EFI_PXE_BASE_CODE_PROTOCOL.UdpRead() . The current hardware ﬁlter
remains in effect no matter what the settings of OpFlags are, so that the meaning of ANY_DEST_IP set in OpFlags
to UdpRead() is from those packets whose reception is enabled in hardware - physical NIC address (unicast), broad-
cast address, logical address or addresses (multicast), or all (promiscuous). UdpRead() does not modify the IP ﬁlter
settings.
EFI_PXE_BASE_CODE_PROTOCOL.Dhcp() , EFI_PXE_BASE_CODE_PROTOCOL.Discover() , and
EFI_PXE_BASE_CODE_PROTOCOL.Mtftp() set the IP ﬁlter, and return with the IP receive ﬁlter list emptied
and the ﬁlter set to EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP. If an application or driver wishes to
preserve the IP receive ﬁlter settings, it will have to preserve the IP receive ﬁlter settings before these calls,
and use EFI_PXE_BASE_CODE_PROTOCOL.SetIpFilter() to restore them after the calls. If incompatible
ﬁltering is requested (for example, PROMISCUOUS with anything else) or if the device does not support a
requested ﬁlter setting and it cannot be accommodated in software (for example, PROMISCUOUS not supported),
EFI_INV ALID_PARAMETER will be returned. The IPlist ﬁeld is used to enable IPs other than the StationIP. They
may be multicast or unicast. If IPcnt is set as well as EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP, then both
the StationIP and the IPs from the IPlist will be used.
EFI_SUCCESS The IP receive ﬁlter settings were updated.
• One or more of the following conditions was TRUE :
• The NewFilter parameter was NULL
• The NewFilter ->IPlist [] array contains one or more broadcast IP
addresses
EFI_NOT_STARTED The PXE Base Code Protocol is not in the started state.
24.3. PXE Base Code Protocol 909Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.3.14 EFI_PXE_BASE_CODE_PROTOCOL.Arp()
Summary
Uses the ARP protocol to resolve a MAC address.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_ARP) (
IN EFI_IP_ADDRESS *IpAddr,
IN EFI_MAC_ADDRESS *MacAddr OPTIONAL
);
IpAddr Pointer to the IP address that is used to resolve a MAC address. When the MAC address is resolved, the
ArpCacheEntries andArpCache ﬁelds of the EFI_PXE_BASE_CODE_MODE in Network Protocols — SNP ,
PXE, BIS and HTTP Boot structure are updated.
MacAddr If not NULL, a pointer to the MAC address that was resolved with the ARP protocol.
This function uses the ARP protocol to resolve a MAC address. The UsingIpv6 ﬁeld of the
EFI_PXE_BASE_CODE_MODE structure is used to determine if IPv4 or IPv6 addresses are being used. The IP
address speciﬁed by IpAddr is used to resolve a MAC address in the case of IPv4; the concept of Arp is not supported
in IPv6, though.
If the ARP protocol succeeds in resolving the speciﬁed address, then the ArpCacheEntries andArpCache ﬁelds of the
EFI_PXE_BASE_CODE_MODE structure are updated, and EFI_SUCCESS is returned. If MacAddr is not NULL,
the resolved MAC address is placed there as well.
If the PXE Base Code protocol is in the stopped state, then EFI_NOT_STARTED is returned. If the ARP protocol
encounters a timeout condition while attempting to resolve an address, then EFI_TIMEOUT is returned. If the Call-
back Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then EFI_ABORTED
EFI_SUCCESS The IP or MAC address was resolved.
One or more of the following conditions was :
• The IpAddr parameter was NULL
EFI_TIMEOUT The ARP Protocol encountered a timeout condition.
EFI_ABORTED The callback function aborted the ARP Protocol.
EFI_UNSUPPORTED When Mode->UsingIpv6 is TRUE because the Arp is a concept special for
IPv4.
24.3. PXE Base Code Protocol 910Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.3.15 EFI_PXE_BASE_CODE_PROTOCOL.SetParameters()
Summary
Updates the parameters that affect the operation of the PXE Base Code Protocol.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_SET_PARAMETERS) (
IN BOOLEAN *NewAutoArp, OPTIONAL
IN BOOLEAN *NewSendGUID, OPTIONAL

IPv4.
Summary
Prototype
typedef
IN UINT8 *NewTTL, OPTIONAL
IN UINT8 *NewToS, OPTIONAL
IN BOOLEAN *NewMakeCallback OPTIONAL
);
NewAutoArp If not NULL, a pointer to a value that speciﬁes whether to replace the current value of AutoARP .TRUE
for automatic ARP packet generation, FALSE otherwise. If NULL, this parameter is ignored.
NewSendGUID If not NULL, a pointer to a value that speciﬁes whether to replace the current value of SendGUID .
TRUE to send the SystemGUID (if there is one) as the client hardware address in DHCP; FALSE to send
client NIC MAC address. If NULL, this parameter is ignored. If NewSendGUID isTRUE and there is no
SystemGUID, then EFI_INV ALID_PARAMETER is returned.
NewTTL If not NULL, a pointer to be used in place of the current value of TTL, the “time to live” ﬁeld of the IP
header. If NULL, this parameter is ignored.
NewToS If not NULL, a pointer to be used in place of the current value of ToS, the “type of service” ﬁeld of the IP
NewMakeCallback If not NULL, a pointer to a value that speciﬁes whether to replace the current value of the
MakeCallback ﬁeld of the Mode structure. If NULL, this parameter is ignored. If the Callback Protocol is not
available EFI_INV ALID_PARAMETER is returned.
This function sets parameters that affect the operation of the PXE Base Code Protocol. The parameter speciﬁed by
NewAutoArp is used to control the generation of ARP protocol packets. If NewAutoArp isTRUE , then ARP Protocol
packets will be generated as required by the PXE Base Code Protocol. If NewAutoArp isFALSE , then no ARP
Protocol packets will be generated. In this case, the only mappings that are available are those stored in the ArpCache
of the EFI_PXE_BASE_CODE_MODE in Network Protocols — SNP , PXE, BIS and HTTP Boot structure. If there
are not enough mappings in the ArpCache to perform a PXE Base Code Protocol service, then the service will fail.
This function updates the AutoArp ﬁeld of the EFI_PXE_BASE_CODE_MODE structure to NewAutoArp .
TheEFI_PXE_BASE_CODE_PROTOCOL.SetParameters() call must be invoked after a Callback Protocol is installed
to enable the use of callbacks.
EFI_SUCCESS The new parameters values were updated.
24.3. PXE Base Code Protocol 911Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.27 – continued from previous page
• The NewSendGUID parameter is not NULL and * NewSendGUID is
TRUE and a system GUID could not be located
• The NewMakeCallback parameter is not NULL and * NewMakeCallback
isTRUE and an EFI _PXE_BASE_CODE_CALLBACK_PROTOCOL
could not be located on the network device handle.
24.3.16 EFI_PXE_BASE_CODE_PROTOCOL.SetStationIp()
Summary
Updates the station IP address and/or subnet mask values of a network device.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_SET_STATION_IP) (
IN EFI_IP_ADDRESS *NewStationIp, OPTIONAL
IN EFI_IP_ADDRESS *NewSubnetMask OPTIONAL
);
NewStationIp Pointer to the new IP address to be used by the network device. If this ﬁeld is NULL, then the StationIp
address will not be modiﬁed.
NewSubnetMask Pointer to the new subnet mask to be used by the network device. If this ﬁeld is NULL, then the
SubnetMask will not be modiﬁed.
This function updates the station IP address and/or subnet mask values of a network device.
The NewStationIp ﬁeld is used to modify the network device’s current IP address. If NewStationIP is NULL,
then the current IP address will not be modiﬁed. Otherwise, this function updates the StationIp ﬁeld of the
EFI_PXE_BASE_CODE_MODE in Network Protocols — SNP , PXE, BIS and HTTP Boot structure with NewSta-
tionIp .
TheNewSubnetMask ﬁeld is used to modify the network device’s current subnet mask. If NewSubnetMask is NULL,
then the current subnet mask will not be modiﬁed. Otherwise, this function updates the SubnetMask ﬁeld of the
EFI_PXE_BASE_CODE_MODE structure with NewSubnetMask .
EFI_SUCCESS The new station IP address and/or subnet mask were updated.
24.3. PXE Base Code Protocol 912Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.28 – continued from previous page
• The This s parameter was NULL
• The NewStationIp parameter is not NULL and * NewStationIp is not a
valid unicast IP address
• The NewSubnetMask parameter is not NULL and * NewSubnetMask does
not contain a valid IP subnet mask
24.3.17 EFI_PXE_BASE_CODE_PROTOCOL.SetPackets()
Summary
Updates the contents of the cached DHCP and Discover packets.
Prototype
typedef
(EFIAPI *EFI_PXE_BASE_CODE_SET_PACKETS) (
IN BOOLEAN *NewDhcpDiscoverValid, OPTIONAL
IN BOOLEAN *NewDhcpAckReceived, OPTIONAL
IN BOOLEAN *NewProxyOfferReceived, OPTIONAL
IN BOOLEAN *NewPxeDiscoverValid, OPTIONAL
IN BOOLEAN *NewPxeReplyReceived, OPTIONAL
IN BOOLEAN *NewPxeBisReplyReceived, OPTIONAL
IN EFI_PXE_BASE_CODE_PACKET *NewDhcpDiscover, OPTIONAL
IN EFI_PXE_BASE_CODE_PACKET *NewDhcpAck, OPTIONAL
IN EFI_PXE_BASE_CODE_PACKET *NewProxyOffer, OPTIONAL
IN EFI_PXE_BASE_CODE_PACKET *NewPxeDiscover, OPTIONAL
IN EFI_PXE_BASE_CODE_PACKET *NewPxeReply, OPTIONAL
IN EFI_PXE_BASE_CODE_PACKET *NewPxeBisReply OPTIONAL
);
NewDhcpDiscoverValid Pointer to a value that will replace the current DhcpDiscoverValid ﬁeld. If NULL, this
parameter is ignored.
NewDhcpAckReceived Pointer to a value that will replace the current DhcpAckReceived ﬁeld. If NULL, this param-
eter is ignored.
NewProxyOfferReceived Pointer to a value that will replace the current ProxyOfferReceived ﬁeld. If NULL, this
NewPxeDiscoverValid Pointer to a value that will replace the current ProxyOfferReceived ﬁeld. If NULL, this pa-
rameter is ignored.
NewPxeReplyReceived Pointer to a value that will replace the current PxeReplyReceived ﬁeld. If NULL, this param-
24.3. PXE Base Code Protocol 913Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NewPxeBisReplyReceived Pointer to a value that will replace the current PxeBisReplyReceived ﬁeld. If NULL, this
NewDhcpDiscover Pointer to the new cached DHCP Discover packet contents. If NULL, this parameter is ignored.
NewDhcpAck Pointer to the new cached DHCP Ack packet contents. If NULL, this parameter is ignored.
NewProxyOffer Pointer to the new cached Proxy Offer packet contents. If NULL, this parameter is ignored.
NewPxeDiscover Pointer to the new cached PXE Discover packet contents. If NULL, this parameter is ignored.
NewPxeReply Pointer to the new cached PXE Reply packet contents. If NULL, this parameter is ignored.
NewPxeBisReply Pointer to the new cached PXE BIS Reply packet contents. If NULL, this parameter is ignored.
The pointers to the new packets are used to update the contents of the cached packets in the
EFI_PXE_BASE_CODE_MODE structure.
EFI_SUCCESS The cached packet contents were updated.
TheThis parameter did not point to a valid
24.3.18 Netboot6
For IPv4, PXE drivers typically install a LoadFile protocol on the NIC handle. In the case of supporting both IPv4
and IPv6 where two PXE Base Code and LoadFile protocol instances need be produced, the PXE driver will have
to create two child handles and install EFI_LOAD_FILE_PROTOCOL, EFI_SIMPLE_NETWORK_PROTOCOL and
PXE_BASE_CODE_PROTOCOL on each child handle. To distinguish these two child handles, an IP device path node
can be appended to the parent device path, for example:
PciRoot(0x0)/Pci(0x19,0x0)/MAC(001320F4B4FF,0x0)/IPv4(...)
PciRoot(0x0)/Pci(0x19,0x0)/MAC(001320F4B4FF,0x0)/IPv6(...)
These two instances allow for the boot manager to decide a preference of IPv6 versus IPv4 since the IETF and other
bodies do not speak to this policy choice.
24.3.18.1 DHCP6 options for PXE
In IPv4-based PXE, as deﬁned by the rfc2131, rfc2132 and rfc4578, and described by the PXE2.1 speciﬁcation and
the UEFI speciﬁcation, there are the following PXE related options/ﬁelds in DHCPv4 packet:

• siaddr ﬁeld/ServerAddress option (54) - next server address.
• BootFileName option (67
• ) – NBP ﬁle name.
• BootFileSize option (13)
• – NBP ﬁle size.
24.3. PXE Base Code Protocol 914Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• ClassIdentiﬁer (60)
• – PXE client tag.
• ClientSystemArchitectureType option (93)
• – client architecture type.
• ClientNetworkInterface Identiﬁer option (94)
• – client network interface identiﬁer.
In IPv6-based PXE, or ‘netboot6’, there are the following PXE related options in the DHCPv6 packet:
• BootFileURL option - OPT_BOOTFILE_URL (59) — next server address and NBP (Network Bootable Pro-
gram) ﬁle name.
• BootFileParameters option
• – OPT_BOOTFILE_PARAM (60) — NBP ﬁle size.
• VendorClass option (16)
• ClientSystemArchitectureType option — OPTION_CLIENT_ARCH_TYPE (61) — client architecture type.
• ClientNetworkInterfaceIdentiﬁer option (
• 62). – client network interface identiﬁer.
The BootFileURL option is used to deliver the next server address or the next server address with NBP ﬁle name.
As an example where the next server address delivered only: “tftp://{[}FEDC:BA98:7654:3210:FEDC:BA98:7654:
3210{]};mode=octet”.
As an example where the next server address and BOOTFILE_NAME delivered both: “tftp://{[}FEDC:BA98:7654:
3210:FEDC:BA98:7654:3210{]}/ BOOTFILE_NAME ;mode=octet”.
The BootFileParameters option is used to deliver the NBP ﬁle size with the unit of 512-octet blocks. The maximum
of the NBP ﬁle size is 65535 * 512 bytes.
As an example where the NBP ﬁle size is 1600 * 512 bytes:
para-len 1 = 4
parameter 1 = "1600"
The VendorClass option is used to deliver the PXE client tag.
As an example where the client architecture is EFI-X64 and the client network interface identiﬁer is UNDI:
Enterprise-number = (343)
Vendor-class-data = "PXEClient:Arch:00006:UNDI:003016"
#define DUID-UUID 4
The Netboot6 client will use the DUID-UUID to report the platform identiﬁer as part of the netboot6 DHCP options.
24.3. PXE Base Code Protocol 915Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.3.18.2 IPv6-based PXE boot
As PXE 2.1 speciﬁcation describes step-by-step synopsis of the IPv4-based PXE process, Figure 1 describes the
corresponding synopsis for netboot6.
Fig. 24.1: IPv6-based PXE Boot
24.3.18.2.1 Step 1.
The client multicasts a SOLICIT message to the standard DHCP6 port (547). It contains the following:
• A tag for client UNDI version.
• A tag for the client system architecture.
• A tag for PXE client, Vendor Class data set to
• “PXEClient:Arch:xxxxx:UNDI:yyyzzz”.
24.3.18.2.2 Step 2.
The DHCP6 or Proxy DHCP6 service responds by sending a ADVERTISE message to the client on the standard
DHCP6 reply port (546). If this is a Proxy DHCP6 service, the next server (Boot Server) address is delivered by Boot
File URL option. If this is a DHCP6 service, the new assigned client address is delivered by IA option. The extension
tags information will be conveyed via the VENDOR OPTS ﬁeld.
24.3. PXE Base Code Protocol 916Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.3.18.2.3 Steps 3 and 4.
If the client selects an address from a DHCP6 service, then it must complete the standard DHCP6 process by sending
a REQUEST for the address back to the service and then waiting for an REPLY from the service.
24.3.18.2.4 Step 5.
The client multicasts a REQUEST message to the Boot Server port 4011, it contains the following:
• A tag for PXE client, Vendor Class option, set to
24.3.18.2.5 Step 6.
The Boot Server unicasts a REPLY message back to the client on the client port. It contains the following:
• A tag for NBP ﬁle name.
• A tag for NBP ﬁle size if needed.
24.3.18.2.6 Step 7.
The client requests the NBP ﬁle using TFTP (port 69).
24.3.18.2.7 Step 8.
The NBP ﬁle, dependent on the client’s CPU architecture, is downloaded into client’s memory.
24.3.18.3 Proxy DHCP6
The netboot6 DHCP6 options may be supplied by the DHCP6 service or a Proxy DHCP6 service. This Proxy DHCP6
service may reside on the same server as the DHCP6 service, or it ma be located on a separate server. A Proxy DHCP6
service on the same server as the DHCP6 service is illustrated in Figure 2. In this case, the Proxy DHCP6 service is
listening to UDP port (4011), and communication with the Proxy DHCP6 service occurs after completing the standard
DHCP6 process. Proxy DHCP6 uses port (4011) because is cannot share port (547) with the DHCP6 service. The
netboot6 client knows how to interrogate the Proxy DHCP6 service because the ADVERTISE from the DHCP6 service
contains a VendorClass option “PXEClient” tag without a BootFileURL option (including NBP ﬁle name). The client
will not request option 16 ( OPTION_VENDOR_CLASS ) in ORO, but server must still reply with “PXEClient” in
order to inform the client to start the Proxy DHCPv6 mode. The client will accept just the string “PXEClient” as
sufﬁcient, the server need not echo back the entire OPTION_VENDOR_CLASS .
The Figure below, IPv6-based PXE boot (DHCP6 and ProxyDHCP6reside on the different server) illustrates the case
of a Proxy DHCP6 service and the DHCP6 service on different servers. In this case, the Proxy DHCP6 service listens
to UDP port (547) and responds in parallel with DHCP6 service.
24.3. PXE Base Code Protocol 917Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 24.2: Netboot6 (DHCP6 and ProxyDHCP6 reside on the same server)
24.3. PXE Base Code Protocol 918Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 24.3: IPv6-based PXE boot (DHCP6 and ProxyDHCP6reside on the different server)
24.3. PXE Base Code Protocol 919Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.4 PXE Base Code Callback Protocol
This protocol is a speciﬁc instance of the PXE Base Code Callback Protocol that is invoked when the PXE Base Code
Protocol is about to transmit, has received, or is waiting to receive a packet. The PXE Base Code Callback Protocol
must be on the same handle as the PXE Base Code Protocol.
24.4.1 EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL
Summary
Protocol that is invoked when the PXE Base Code Protocol is about to transmit, has received, or is waiting to receive
a packet.
GUID
#define EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_GUID \
{0x245DCA21,0xFB7B,0x11d3,\
{0x8F,0x01,0x00,0xA0, 0xC9,0x69,0x72,0x3B}}
#define EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_REVISION \\
0x00010000
EFI_PXE_CALLBACK Callback;
} EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL;
Revision The revision of the EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL. All future revisions must be
backwards compatible. If a future revision is not backwards compatible, it is not the same GUID.
Callback Callback routine used by the PXE Base Code EFI_PXE_BASE_CODE_PROTOCOL.Dhcp()
,EFI_PXE_BASE_CODE_PROTOCOL.Discover() ,EFI_PXE_BASE_CODE_PROTOCOL.Mtftp() ,
EFI_PXE_BASE_CODE_PROTOCOL.UdpWrite() , and EFI_PXE_BASE_CODE_PROTOCOL.Arp() func-
tions.
24.4.2 EFI_PXE_BASE_CODE_CALLBACK.Callback()
Summary
Callback function that is invoked when the PXE Base Code Protocol is about to transmit, has received, or is waiting
to receive a packet.
Prototype
typedef
EFI_PXE_BASE_CODE_CALLBACK_STATUS
(*EFI_PXE_CALLBACK) (
IN EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL *This,
IN EFI_PXE_BASE_CODE_FUNCTION Function,
IN BOOLEAN Received,
24.4. PXE Base Code Callback Protocol 920Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN UINT32 PacketLen,
IN EFI_PXE_BASE_CODE_PACKET *Packet OPTIONAL
);
This Pointer to the See EFI_PXE_BASE_CODE_PROTOCOL instance.
Function The PXE Base Code Protocol function that is waiting for an event.
Received TRUE if the callback is being invoked due to a receive event. FALSE if the callback is being invoked due
to a transmit event.
PacketLen The length, in bytes, of Packet . This ﬁeld will have a value of zero if this is a wait for receive event.
Packet IfReceived isTRUE , a pointer to the packet that was just received; otherwise a pointer to the packet that is
about to be transmitted. This ﬁeld will be NULL if this is not a packet event.
// EFI_PXE_BASE_CODE_CALLBACK_STATUS
EFI_PXE_BASE_CODE_CALLBACK_STATUS_FIRST,
EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE,
EFI_PXE_BASE_CODE_CALLBACK_STATUS_ABORT,
EFI_PXE_BASE_CODE_CALLBACK_STATUS_LAST
} EFI_PXE_BASE_CODE_CALLBACK_STATUS;
// EFI_PXE_BASE_CODE_FUNCTION
EFI_PXE_BASE_CODE_FUNCTION_FIRST,
EFI_PXE_BASE_CODE_FUNCTION_DHCP,

EFI_PXE_BASE_CODE_FUNCTION_DISCOVER,
EFI_PXE_BASE_CODE_FUNCTION_MTFTP,
EFI_PXE_BASE_CODE_FUNCTION_UDP_WRITE,
EFI_PXE_BASE_CODE_FUNCTION_UDP_READ,
EFI_PXE_BASE_CODE_FUNCTION_ARP,
EFI_PXE_BASE_CODE_FUNCTION_IGMP,
EFI_PXE_BASE_CODE_PXE_FUNCTION_LAST
} EFI_PXE_BASE_CODE_FUNCTION;
This function is invoked when the PXE Base Code Protocol is about to transmit, has received, or is waiting to receive
a packet. Parameters Function andReceived specify the type of event. Parameters PacketLen andPacket specify the
packet that generated the event. If these ﬁelds are zero and NULL respectively, then this is a status update callback.
If the operation speciﬁed by Function is to continue, then CALLBACK_STATUS_CONTINUE should be returned. If
the operation speciﬁed by Function should be aborted, then CALLBACK_STATUS_ABORT should be returned. Due
to the polling nature of UEFI device drivers, a callback function should not execute for more than 5 ms.
The EFI_PXE_BASE_CODE_PROTOCOL.SetParameters() function must be called after a Callback Protocol is in-
stalled to enable the use of callbacks.
24.4. PXE Base Code Callback Protocol 921Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.5 Boot Integrity Services Protocol
This section deﬁnes the Boot Integrity Services (BIS) protocol, which is used to check a digital signature of a data
block against a digital certiﬁcate for the purpose of an integrity and authorization check. BIS is primarily used by
the Preboot Execution Environment (PXE) Base Code protocol See EFI_PXE_BASE_CODE_PROTOCOL to check
downloaded network boot images before executing them. BIS is a UEFI Boot Service Driver, so its services are also
available to applications written to this speciﬁcation until the time of EFI_BOOT_SERVICES.ExitBootServices() .
More information about BIS can be found in the Boot Integrity Services Application Programming Interface Version
1.0.
This section deﬁnes the Boot Integrity Services Protocol. This protocol is used to check a digital signature of a data
block against a digital certiﬁcate for the purpose of an integrity and authorization check.
24.5.1 EFI_BIS_PROTOCOL
Summary
The EFI_BIS_PROTOCOL is used to check a digital signature of a data block against a digital certiﬁcate for the
purpose of an integrity and authorization check.
GUID
#define EFI_BIS_PROTOCOL_GUID \
{0x0b64aab0,0x5429,0x11d4,\
{0x98,0x16,0x00,0xa0,0xc9,0x1f,0xad,0xcf}}
typedef struct \_EFI_BIS_PROTOCOL {
EFI_BIS_INITIALIZE Initialize;
EFI_BIS_SHUTDOWN Shutdown;
EFI_BIS_FREE Free;
EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE
˓→GetBootObjectAuthorizationCertificate;
EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG
˓→GetBootObjectAuthorizationCheckFlag;
EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN
˓→GetBootObjectAuthorizationUpdateToken;
EFI_BIS_GET_SIGNATURE_INFO GetSignatureInfo;
EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION UpdateBootObjectAuthorization;
EFI_BIS_VERIFY_BOOT_OBJECT VerifyBootObject;
EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL VerifyObjectWithCredential;
} EFI_BIS_PROTOCOL;
Initialize Initializes an application instance of the EFI_BIS protocol, returning a handle for the application instance.
Other functions in the EFI_BIS protocol require a valid application instance handle obtained from this function.
See the EFI_BIS_PROTOCOL.Initialize() function description.
Shutdown Ends the lifetime of an application instance of the EFI_BIS protocol, invalidating its application instance
handle. The application instance handle may no longer be used in other functions in the EFI_BIS protocol. See
theEFI_BIS_PROTOCOL.Shutdown() function description.
Free Frees memory structures allocated and returned by other functions in the EFI_BIS protocol. See the
EFI_BIS_PROTOCOL.Free() function description.
24.5. Boot Integrity Services Protocol 922Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetBootObjectAuthorizationCertiﬁcate Retrieves the current digital certiﬁcate (if any) used by the EFI_BIS pro-
tocol as the source of authorization for verifying boot objects and altering conﬁguration parameters. See the
EFI_BIS_PROTOCOL.GetBootObjectAuthorizationCertiﬁcate() function description.
GetBootObjectAuthorizationCheckFlag Retrieves the current setting of the authorization check ﬂag
that indicates whether or not authorization checks are required for boot objects. See the
EFI_BIS_PROTOCOL.GetBootObjectAuthorizationCheckFlag() function description.
GetBootObjectAuthorizationUpdateToken Retrieves an uninterpreted token whose value gets included and signed
in a subsequent request to alter the conﬁguration parameters, to protect against attempts to “replay” such a
request. See the EFI_BIS_PROTOCOL.GetBootObjectAuthorizationUpdateToken() function description.
GetSignatureInfo Retrieves information about the digital signature algorithms supported and the identity of the in-
stalled authorization certiﬁcate, if any. See the EFI_BIS_PROTOCOL.GetSignatureInfo() function description.
UpdateBootObjectAuthorization Requests that the conﬁguration parameters be altered by installing
or removing an authorization certiﬁcate or changing the setting of the check ﬂag. See the
EFI_BIS_PROTOCOL.UpdateBootObjectAuthorization() function description.
VerifyBootObject Veriﬁes a boot object according to the supplied digital signature and the current authorization
certiﬁcate and check ﬂag setting. See the EFI_BIS_PROTOCOL.VerifyBootObject() function description.
VerifyObjectWithCredential Veriﬁes a data object according to a supplied digital signature and a supplied digital
certiﬁcate. See the EFI_BIS_PROTOCOL.VerifyObjectWithCredential() function description.
The EFI_BIS_PROTOCOL provides a set of functions as deﬁned in this section. There is no physical device associated
with these functions, however, in the context of UEFI every protocol operates on a device. Accordingly, BIS installs
and operates on a single abstract device that has only a software representation.
24.5.2 EFI_BIS_PROTOCOL.Initialize()
Summary
Initializes the BIS service, checking that it is compatible with the version requested by the caller. After this call, other
BIS functions may be invoked.
Prototype
typedef
(EFIAPI *EFI_BIS_INITIALIZE)(
IN EFI_BIS_PROTOCOL *This,
OUT BIS_APPLICATION_HANDLE *AppHandle,
IN OUT EFI_BIS_VERSION *InterfaceVersion,
IN EFI_BIS_DATA *TargetAddress
);
This A pointer to the EFI_BIS_PROTOCOL object. The protocol implementation may rely on the actual pointer value
and object location, so the caller must not copy the object to a new location.
AppHandle The function writes the new BIS_APPLICATION_HANDLE if successful, otherwise it writes NULL .
The caller must eventually destroy this handle by calling EFI_BIS_PROTOCOL.Shutdown() . Type
BIS_APPLICATION_HANDLE is deﬁned in “Related Deﬁnitions” below.
InterfaceVersion On input, the caller supplies the major version number of the interface version desired. The minor
version number supplied on input is ignored since interface compatibility is determined solely by the major
24.5. Boot Integrity Services Protocol 923Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
version number. On output, both the major and minor version numbers are updated with the major and minor
version numbers of the interface (and underlying implementation). This update is done whether or not the
initialization was successful. Type EFI_BIS_VERSION is deﬁned in “Related Deﬁnitions” below.
TargetAddress Indicates a network or device address of the BIS platform to connect to. Local-platform BIS imple-
mentations require that the caller sets TargetAddress.Data toNULL, but otherwise ignores this parameter. BIS
implementations that redirect calls to an agent at a remote address must deﬁne their own format and interpreta-
tion of this parameter outside the scope of this document. For all implementations, if the TargetAddress is an
unsupported value, the function fails with the error EFI_UNSUPPORTED . Type EFI_BIS_DATA is deﬁned in
// BIS_APPLICATION_HANDLE
typedef VOID *BIS_APPLICATION_HANDLE;
This type is an opaque handle representing an initialized instance of the BIS interface. A
BIS_APPLICATION_HANDLE value is returned by the Initialize() function as an “out” parameter. Other BIS
functions take a BIS_APPLICATION_HANDLE as an “in” parameter to identify the BIS instance.
// EFI_BIS_VERSION
typedef struct \_EFI_BIS_VERSION {
UINT32 Major;
UINT32 Minor;
} EFI_BIS_VERSION;
Major This describes the major BIS version number. The major version number deﬁnes version compatibility. That
is, when a new version of the BIS interface is created with new capabilities that are not available in the previous

interface version, the major version number is increased.
Minor This describes a minor BIS version number. This version number is increased whenever a new BIS imple-
mentation is built that is fully interface compatible with the previous BIS implementation. This number may be
reset when the major version number is increased.
This type represents a version number of the BIS interface. This is used as an “in out” parameter of the Initialize()
function for a simple form of negotiation of the BIS interface version between the caller and the BIS implementation.
// EFI_BIS_VERSION predefined values
// Use these values to initialize EFI_BIS_VERSION.Major
//andto interpret results of Initialize.
#define BIS_CURRENT_VERSION_MAJOR BIS_VERSION_1
#define BIS_VERSION_1 1
These C preprocessor macros supply values for the major version number of an EFI_BIS_VERSION . At the time
of initialization, a caller supplies a value to request a BIS interface version. On return, the (IN OUT) parameter is
over-written with the actual version of the interface.
// EFI_BIS_DATA
//
// EFI_BIS_DATA instances obtained from BIS must be freed by
// calling `EFI_BIS_PROTOCOL.Free() `_.
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typedef struct \_EFI_BIS_DATA {
UINT8 *Data;
} EFI_BIS_DATA;
Length The length of the data buffer in bytes.
Data A pointer to the raw data buffer.
This type deﬁnes a structure that describes a buffer. BIS uses this type to pass back and forth most large objects such
as digital certiﬁcates, strings, etc. Several of the BIS functions allocate a EFI_BIS_DATA* and return it as an “out”
parameter. The caller must eventually free any allocated EFI_BIS_DATA* using the EFI_BIS_PROTOCOL.Free()
function.
This function must be the ﬁrst BIS function invoked by an application. It passes back a
BIS_APPLICATION_HANDLE value that must be used in subsequent BIS functions. The handle must be
eventually destroyed by a call to the EFI_BIS_PROTOCOL.Shutdown() function, thus ending that handle’s lifetime.
After the handle is destroyed, BIS functions may no longer be called with that handle value. Thus all other BIS
functions may only be called between a pair of EFI_BIS_PROTOCOL.Initialize() andShutdown() functions.
There is no penalty for calling Initialize() multiple times. Each call passes back a distinct handle value. Each distinct
handle must be destroyed by a distinct call to Shutdown() . The lifetimes of handles created and destroyed with these
functions may be overlapped in any way.
EFI_INCOMPATIBLE_VERSION
TheInterfaceVersion.Major requested by the caller was not compatible
with the interface version of the implementation.
TheInterfaceVersion.Major has been updated with the current interface
version.
EFI_UNSUPPORTED This is a local-platform implementation and TargetAddress.Data was not
NULL, orTargetAddress.Data was any other value that was not supported
by the implementation.
EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
The function encountered an unexpected internal failure while initializing
a cryptographic software module, or
No cryptographic software module with compatible version was found, or
A resource limitation was encountered while using a cryptographic
software module.
24.5. Boot Integrity Services Protocol 925Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.30 – continued from previous page
TheThis parameter supplied by the caller is NULL or does not reference a
valid EFI_BIS_PROTOCOL object, or
TheAppHandle parameter supplied by the caller is NULL or an invalid
memory reference, or
TheInterfaceVersion parameter supplied by the caller is NULL or an
invalid memory reference, or
TheTargetAddress parameter supplied by the caller is NULL or an invalid
memory reference.
24.5.3 EFI_BIS_PROTOCOL.Shutdown()
Summary
Shuts down an application’s instance of the BIS service, invalidating the application handle. After this call, other BIS
functions may no longer be invoked using the application handle value.
Prototype
typedef
(EFIAPI *EFI_BIS_SHUTDOWN)(
IN BIS_APPLICATION_HANDLE AppHandle
);
AppHandle An opaque handle that identiﬁes the caller’s instance of initialization of the BIS service. Type
BIS_APPLICATION_HANDLE is deﬁned in the EFI_BIS_PROTOCOL.Initialize() function description.
This function shuts down an application’s instance of the BIS service, invalidating the application handle. After this
call, other BIS functions may no longer be invoked using the application handle value.
This function must be paired with a preceding successful call to the Initialize() function. The lifetime of an application
handle extends from the time the handle was returned from Initialize() until the time the handle is passed to Shutdown() .
If there are other remaining handles whose lifetime is still active, they may still be used in calling BIS functions.
The caller must free all memory resources associated with this AppHandle that were allocated and returned from
other BIS functions before calling Shutdown() . Memory resources are freed using the EFI_BIS_PROTOCOL.Free()
function. Failure to free such memory resources is a caller error, however, this function does not return an error code
under this circumstance. Further attempts to access the outstanding memory resources cause unspeciﬁed results.
EFI_NO_MAPPING TheAppHandle parameter is not or is no longer a valid application instance
handle associated with the EFI_BIS protocol.
24.5. Boot Integrity Services Protocol 926Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.31 – continued from previous page
The function encountered an unexpected internal error while returning
resources associated with a cryptographic software module, or
The function encountered an internal error while trying to shut down a
cryptographic software module.
24.5.4 EFI_BIS_PROTOCOL.Free()
Summary
Frees memory structures allocated and returned by other functions in the EFI_BIS protocol.
Prototype
typedef
(EFIAPI *EFI_BIS_FREE)(
IN BIS_APPLICATION_HANDLE AppHandle,
IN EFI_BIS_DATA *ToFree
);
ToFree AnEFI_BIS_DATA* and associated memory block to be freed. This EFI_BIS_DATA* must have been allo-
cated by one of the other BIS functions. Type EFI_BIS_DATA is deﬁned in the Initialize() function description.
This function deallocates an EFI_BIS_DATA* and associated memory allocated by one of the other BIS functions.
Callers of other BIS functions that allocate memory in the form of an EFI_BIS_DATA* must eventually call this
function to deallocate the memory before calling the EFI_BIS_PROTOCOL.Shutdown() function for the application
handle under which the memory was allocated. Failure to do so causes unspeciﬁed results, and the continued correct
operation of the BIS service cannot be guaranteed.
EFI_INV ALID_PARAMETER TheToFree parameter is not or is no longer a memory resource associated
with this AppHandle .
24.5. Boot Integrity Services Protocol 927Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.5.5 EFI_BIS_PROTOCOL.GetBootObjectAuthorizationCertiﬁcate()
Summary
Retrieves the certiﬁcate that has been conﬁgured as the identity of the organization designated as the source of autho-
rization for signatures of boot objects.
Prototype
typedef
(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE)(
OUT EFI_BIS_DATA **Certificate
);
Certiﬁcate The function writes an allocated EFI_BIS_DATA* containing the Boot Object Authorization Certiﬁ-

Summary
Prototype
typedef
);
cate object. The caller must eventually free the memory allocated by this function using the function
EFI_BIS_PROTOCOL.Free() . Type EFI_BIS_DATA is deﬁned in the Initialize() function description.
This function retrieves the certiﬁcate that has been conﬁgured as the identity of the organization designated as the
source of authorization for signatures of boot objects.
EFI_NOT_FOUND There is no Boot Object Authorization Certiﬁcate currently installed.
EFI_INV ALID_PARAMETER TheCertiﬁcate parameter supplied by the caller is NULL or an invalid mem-
ory reference.
24.5.6 EFI_BIS_PROTOCOL.GetBootObjectAuthorizationCheckFlag()
Summary
Retrieves the current status of the Boot Authorization Check Flag.
Prototype
typedef
(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG)(
OUT BOOLEAN *CheckIsRequired
);
24.5. Boot Integrity Services Protocol 928Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
CheckIsRequired The function writes the value TRUE if a Boot Authorization Check is currently required on this
platform, otherwise the function writes FALSE .
This function retrieves the current status of the Boot Authorization Check Flag (in other words, whether or not a Boot
Authorization Check is currently required on this platform).
EFI_INV ALID_PARAMETER TheCheckIsRequired parameter supplied by the caller is NULL or an invalid
24.5.7 EFI_BIS_PROTOCOL.GetBootObjectAuthorizationUpdateToken()
Summary
Retrieves a unique token value to be included in the request credential for the next update of any parameter in the Boot
Object Authorization set (Boot Object Authorization Certiﬁcate and Boot Authorization Check Flag).
Prototype
typedef
(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN)(
OUT EFI_BIS_DATA **UpdateToken
);
UpdateToken The function writes an allocated EFI_BIS_DATA* containing the new unique update token
value. The caller must eventually free the memory allocated by this function using the function
This function retrieves a unique token value to be included in the request credential for the next update of any parameter
in the Boot Object Authorization set (Boot Object Authorization Certiﬁcate and Boot Authorization Check Flag). The
token value is unique to this platform, parameter set, and instance of parameter values. In particular, the token changes
to a new unique value whenever any parameter in this set is changed.
EFI_DEVICE_ERROR The function encountered an unexpected internal error in a cryptographic
24.5. Boot Integrity Services Protocol 929Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.35 – continued from previous page
EFI_INV ALID_PARAMETER The UpdateToken parameter supplied by the caller is NULL or an invalid
24.5.8 EFI_BIS_PROTOCOL.GetSignatureInfo()
Summary
Retrieves a list of digital certiﬁcate identiﬁer, digital signature algorithm, hash algorithm, and key-length combinations
that the platform supports.
Prototype
typedef
(EFIAPI *EFI_BIS_GET_SIGNATURE_INFO)(
OUT EFI_BIS_DATA **SignatureInfo
);
SignatureInfo The function writes an allocated EFI_BIS_DATA* containing the array of
EFI_BIS_SIGNATURE_INFO structures representing the supported digital certiﬁcate identiﬁer, algorithm, and
key length combinations. The caller must eventually free the memory allocated by this function using the
function EFI_BIS_PROTOCOL.Free() . Type EFI_BIS_DATA is deﬁned in the Initialize() function description.
Type EFI_BIS_SIGNATURE_INFO is deﬁned in “Related Deﬁnitions” below.
// EFI_BIS_SIGNATURE_INFO
typedef struct \_EFI_BIS_SIGNATURE_INFO {
BIS_CERT_ID CertificateID;
BIS_ALG_ID AlgorithmID;
UINT16 KeyLength;
} EFI_BIS_SIGNATURE_INFO;
CertiﬁcateID A shortened value identifying the platform’s currently conﬁgured Boot Object Authorization Certiﬁ-
cate, if one is currently conﬁgured. The shortened value is derived from the certiﬁcate as deﬁned in the Related
Deﬁnition for BIS_CERT_ID below. If there is no certiﬁcate currently conﬁgured, the value is one of the re-
served BIS_CERT_ID_XXX values deﬁned below. Type BIS_CERT_ID and its predeﬁned reserved values are
deﬁned in “Related Deﬁnitions” below.
AlgorithmID A predeﬁned constant representing a particular digital signature algorithm. Often this represents a
combination of hash algorithm and encryption algorithm, however, it may also represent a standalone digital
signature algorithm. Type BIS_ALG_ID and its permitted values are deﬁned in “Related Deﬁnitions” below.
KeyLength The length of the public key, in bits, supported by this digital signature algorithm.
This type deﬁnes a digital certiﬁcate, digital signature algorithm, and key-length combination that may be supported
by the BIS implementation. This type is returned by GetSignatureInfo() to describe the combination(s) supported by
the implementation.
24.5. Boot Integrity Services Protocol 930Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// BIS_GET_SIGINFO_COUNT macro
// Tells how many EFI_BIS_SIGNATURE_INFO elements are contained
//ina EFI_BIS_DATA struct pointed to by the provided
// EFI_BIS_DATA *.
#define BIS_GET_SIGINFO_COUNT(BisDataPtr) \
((BisDataPtr)->Length/sizeof(EFI_BIS_SIGNATURE_INFO))
BisDataPtr Supplies the pointer to the target EFI_BIS_DATA structure.
(return value) The number of EFI_BIS_SIGNATURE_INFO elements contained in the array.
This macro computes how many EFI_BIS_SIGNATURE_INFO elements are contained in an EFI_BIS_DATA structure
returned from GetSignatureInfo() . The number returned is the count of items in the list of supported digital certiﬁcate,
digital signature algorithm, and key-length combinations.
// BIS_GET_SIGINFO_ARRAY macro
// Produces a EFI_BIS_SIGNATURE_INFO *from agiven
// EFI_BIS_DATA. *
#define BIS_GET_SIGINFO_ARRAY(BisDataPtr) \
((EFI_BIS_SIGNATURE_INFO *)(BisDataPtr)->Data)
(return value) The pointer to the EFI_BIS_SIGNATURE_INFO array, cast as an EFI_BIS_SIGNATURE_INFO* .
This macro returns a pointer to the EFI_BIS_SIGNATURE_INFO array contained in an EFI_BIS_DATA structure
returned from GetSignatureInfo() representing the list of supported digital certiﬁcate, digital signature algorithm, and
key-length combinations.
// BIS_CERT_ID
typedef UINT32 BIS_CERT_ID;
This type represents a shortened value that identiﬁes the platform’s currently conﬁgured Boot Object Authorization
Certiﬁcate. The value is the ﬁrst four bytes, in “little-endian” order, of the SHA-1 hash of the certiﬁcate, except that the
most-signiﬁcant bits of the second and third bytes are reserved, and must be set to zero regardless of the outcome of the

hash function. This type is included in the array of values returned from the GetSignatureInfo() function to indicate the
required source of a signature for a boot object or a conﬁguration update request. There are a few predeﬁned reserved
values with special meanings as described below.
// BIS_CERT_ID predefined values
// Currently defined values forEFI_BIS_SIGNATURE_INFO.
// CertificateId.
#define BIS_CERT_ID_DSA BIS_ALG_DSA //CSSM_ALGID_DSA
#define BIS_CERT_ID_RSA_MD5 BIS_ALG_RSA_MD5 //CSSM_ALGID_MD5_WITH_RSA
These C preprocessor symbols provide values for the BIS_CERT_ID type. These values are used when the platform
has no conﬁgured Boot Object Authorization Certiﬁcate. They indicate the signature algorithm that is supported by
the platform. Users must be careful to avoid constructing Boot Object Authorization Certiﬁcates that transform to
BIS_CERT_ID values that collide with these predeﬁned values or with the BIS_CERT_ID values of other Boot Object
Authorization Certiﬁcates they use.
24.5. Boot Integrity Services Protocol 931Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// BIS_CERT_ID_MASK
// The following isa mask value that gets applied to the
// truncated hash of a platform Boot Object Authorization
// Certificate to create the CertificateId. A CertificateId
// must nothave any bits set to the value 1 other than bits in
// this mask.
#define BIS_CERT_ID_MASK (0xFF7F7FFF)
This C preprocessor symbol may be used as a bit-wise “AND” value to transform the ﬁrst four bytes (in little-endian
order) of a SHA-1 hash of a certiﬁcate into a certiﬁcate ID with the “reserved” bits properly set to zero.
// BIS_ALG_ID
typedef UINT16 BIS_ALG_ID;
This type represents a digital signature algorithm. A digital signature algorithm is often composed of a particular
combination of secure hash algorithm and encryption algorithm. This type also allows for digital signature algorithms
that cannot be decomposed. Predeﬁned values for this type are as deﬁned below.
// BIS_ALG_ID predefined values
// AlgorithmID. The exact numeric values come from"Common
// Data Security Architecture (CDSA) Specification."
#define BIS_ALG_DSA (41) //CSSM_ALGID_DSA
#define BIS_ALG_RSA_MD5 (42) //CSSM_ALGID_MD5_WITH_RSA
These values represent the two digital signature algorithms predeﬁned for BIS. Each implementation of BIS must
support at least one of these digital signature algorithms. Values for the digital signature algorithms are chosen by an
industry group known as The Open Group. Developers planning to support additional digital signature algorithms or
deﬁne new digital signature algorithms should refer to The Open Group for interoperable values to use.
This function retrieves a list of digital certiﬁcate identiﬁer, digital signature algorithm, hash algorithm, and key-length
combinations that the platform supports. The list is an array of (certiﬁcate id, algorithm id, key length) triples, where
the certiﬁcate id is derived from the platform’s Boot Object Authorization Certiﬁcate as described in the Related
Deﬁnition for BIS_CERT_ID above, the algorithm id represents the combination of signature algorithm and hash
algorithm, and the key length is expressed in bits. The number of array elements can be computed using the Length
ﬁeld of the retrieved EFI_BIS_DATA* .
The retrieved list is in order of preference. A digital signature algorithm for which the platform has a currently
conﬁgured Boot Object Authorization Certiﬁcate is preferred over any digital signature algorithm for which there is
not a currently conﬁgured Boot Object Authorization Certiﬁcate. Thus the ﬁrst element in the list has a CertiﬁcateID
representing a Boot Object Authorization Certiﬁcate if the platform has one conﬁgured. Otherwise the CertiﬁcateID
of the ﬁrst element in the list is one of the reserved values representing a digital signature algorithm.
24.5. Boot Integrity Services Protocol 932Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.36 – continued from previous page
The function encountered an unexpected internal error in a cryptographic
software module, or
The function encountered an unexpected internal consistency check failure
(possible corruption of stored Boot Object Authorization Certiﬁcate).
EFI_INV ALID_PARAMETER The SignatureInfo parameter supplied by the caller is NULL or an invalid
24.5.9 EFI_BIS_PROTOCOL.UpdateBootObjectAuthorization()
Summary
Updates one of the conﬁgurable parameters of the Boot Object Authorization set (Boot Object Authorization Certiﬁ-
cate or Boot Authorization Check Flag).
Prototype
typedef
(EFIAPI *EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION)(
IN EFI_BIS_DATA *RequestCredential,
OUT EFI_BIS_DATA **NewUpdateToken
);
RequestCredential This is a Signed Manifest with embedded attributes that carry the details of the requested update.
The required syntax of the Signed Manifest is described in the Related Deﬁnition for Manifest Syntax below.
The key used to sign the request credential must be the private key corresponding to the public key in the
platform’s conﬁgured Boot Object Authorization Certiﬁcate. Authority to update parameters in the Boot Object
Authorization set cannot be delegated.
If there is no Boot Object Authorization Certiﬁcate, the request credential may be signed with any private key.
In this case, this function interacts with the user in a platform-speciﬁc way to determine whether the operation
should succeed. Type EFI_BIS_DATA is deﬁned in the Initialize() function description.
NewUpdateToken The function writes an allocated EFI_BIS_DATA* containing the new unique update to-
ken value. The caller must eventually free the memory allocated by this function using the function
//**********************************************************
// Manifest Syntax
The Signed Manifest consists of three parts grouped together into an Electronic Shrink Wrap archive as described
in [SM spec]: a manifest ﬁle, a signer’s information ﬁle, and a signature block ﬁle. These three parts, along with
examples are described in the following sections. In these examples, text in parentheses is a description of the text
24.5. Boot Integrity Services Protocol 933Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
that would appear in the signed manifest. Text outside of parentheses must appear exactly as shown. Also note that
manifest ﬁles and signer’s information ﬁles must conform to a 72-byte line-length limit. Continuation lines (lines
beginning with a single “space” character) are used for lines longer than 72 bytes. The examples given here follow
this rule for continuation lines.
Note that the manifest ﬁle and signer’s information ﬁle parts of a Signed Manifest are ASCII text ﬁles. In cases where
these ﬁles contain a base-64 encoded string, the string is an ASCII string before base-64 encoding.
// Manifest File Example
The manifest ﬁle must include a section referring to a memory-type data object with the reserved name as shown in
the example below. This data object is a zero-length object whose sole purpose in the manifest is to serve as a named
collection point for the attributes that carry the details of the requested update. The attributes are also contained in the
manifest ﬁle. An example manifest ﬁle is shown below.
Manifest-Version: 2.0
ManifestPersistentId: (base-64 representation of a unique GUID)
Name: memory:UpdateRequestParameters
Digest-Algorithms: SHA-1
SHA-1-Digest: (base-64 representation of a SHA-1 digest of zero-length buffer)

X-Intel-BIS-ParameterSet: (base-64 representation of BootObjectAuthorizationSetGUID)
X-Intel-BIS-ParameterSetToken: (base-64 representation of the current update token)
X-Intel-BIS-ParameterId: (base-64 representation of
"BootObjectAuthorizationCertificate" or
"BootAuthorizationCheckFlag")
X-Intel-BIS-ParameterValue: (base-64 representation of certificate or
single-byte boolean flag)
A line-by-line description of this manifest ﬁle is as follows.
This is a standard header line that all signed manifests have. It must appear exactly as shown.
The left-hand string must appear exactly as shown. The right-hand string must be a unique GUID for every manifest
ﬁle created. The Win32 function UuidCreate() can be used for this on Win32 systems. The GUID is a binary value that
must be base-64 encoded. Base-64 is a simple encoding scheme for representing binary values that uses only printing
characters. Base-64 encoding is described in [BASE-64].
This identiﬁes the manifest section that carries a dummy zero-length data object serving as the collection point for
the attribute values appearing later in this manifest section (lines preﬁxed with ” X-Intel-BIS- “). The string ” mem-
ory:UpdateRequestParameters ” must appear exactly as shown.
This enumerates the digest algorithms for which integrity data is included for the data object. These are required even
though the data object is zero-length. For systems with DSA signing, SHA-1 hash, and 1024-bit key length, the digest
algorithm must be ” SHA-1 .” For systems with RSA signing, MD5 hash, and 512-bit key length, the digest algorithm
must be ” MD5 .” Multiple algorithms can be speciﬁed as a whitespace-separated list. For every digest algorithm XXX
listed, there must also be a corresponding XXX-Digest line.
24.5. Boot Integrity Services Protocol 934Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Gives the corresponding digest value for the dummy zero-length data object. The value is base-64 encoded. Note that
for both MD5 and SHA-1, the digest value for a zero-length data object is not zero.
A named attribute value that distinguishes updates of BIS parameters from updates of other parameters. The left-hand
attribute-name keyword must appear exactly as shown. The GUID value for the right-hand side is always the same,
and can be found under the preprocessor symbol BOOT_OBJECT_AUTHORIZATION_PARMSET_GUIDVALUE . The
representation inserted into the manifest is base-64 encoded.
Note the ” X-Intel-BIS- ” preﬁx on this and the following attributes. The ” X-” part of the preﬁx was chosen to avoid
collisions with future reserved keywords deﬁned by future versions of the signed manifest speciﬁcation. The ” Intel-
BIS- ” part of the preﬁx was chosen to avoid collisions with other user-deﬁned attribute names within the user-deﬁned
attribute name space.
A named attribute value that makes this update of BIS parameters different from any other on the same
target platform. The left-hand attribute-name keyword must appear exactly as shown. The value for the
right-hand side is generally different for each update-request manifest generated. The value to be base-64
encoded is retrieved through the functions EFI_BIS_PROTOCOL.GetBootObjectAuthorizationUpdateToken() or
EFI_BIS_PROTOCOL.UpdateBootObjectAuthorization() .
A named attribute value that indicates which BIS parameter is to be updated. The left-hand attribute-name keyword
must appear exactly as shown. The value for the right-hand side is the base-64 encoded representation of one of the
two strings shown.
X-Intel-BIS-ParameterValue: (base-64 representation of
certificate or
A named attribute value that indicates the new value to be set for the indicated parameter. The left-hand attribute-name
keyword must appear exactly as shown. The value for the right-hand side is the appropriate base-64 encoded new value
to be set. In the case of the Boot Object Authorization Certiﬁcate, the value is the new digital certiﬁcate raw data. A
zero-length value removes the certiﬁcate altogether. In the case of the Boot Authorization Check Flag, the value is a
single-byte Boolean value, where a nonzero value “turns on” the check and a zero value “turns off” the check.
// Signer’s Information File Example
The signer’s information ﬁle must include a section whose name matches the reserved data object section name of the
section in the Manifest ﬁle. This section in the signer’s information ﬁle carries the integrity data for the attributes in
the corresponding section in the manifest ﬁle. An example signer’s information ﬁle is shown below.
Signature-Version: 2.0
SignerInformationPersistentId: (base-64 representation of a unique GUID)
SignerInformationName: BIS_UpdateManifestSignerInfoName
24.5. Boot Integrity Services Protocol 935Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SHA-1-Digest: (base-64 representation of a SHA-1 digest of the
corresponding manifest section)
A line-by-line description of this signer’s information ﬁle is as follows.
The left-hand string must appear exactly as shown. The right-hand string must be a unique GUID for every signer’s
information ﬁle created. The Win32 function UuidCreate() can be used for this on Win32 systems. The GUID is a
binary value that must be base-64 encoded. Base-64 is a simple encoding scheme for representing binary values that
uses only printing characters. Base-64 encoding is described in [BASE-64].
The left-hand string must appear exactly as shown. The right-hand string must appear exactly as shown.
This identiﬁes the section in the signer’s information ﬁle corresponding to the section with the same name in the
manifest ﬁle described earlier. The string ” memory:UpdateRequestParameters ” must appear exactly as shown.
This enumerates the digest algorithms for which integrity data is included for the corresponding manifest section.
Strings identifying digest algorithms are the same as in the manifest ﬁle. The digest algorithms speciﬁed here must
match those speciﬁed in the manifest ﬁle. For every digest algorithm XXX listed, there must also be a corresponding
XXX-Digest line.
SHA-1-Digest: (base-64 representation of a SHA-1 digest of the corresponding manifest
˓→section)
Gives the corresponding digest value for the corresponding manifest section. The value is base-64 encoded. Note
that for the purpose of computing the hash of the manifest section, the manifest section starts at the beginning of the
opening ” Name: ” keyword and continues up to, but not including, the next section’s ” Name: ” keyword or the
end-of-ﬁle. Thus the hash includes the blank line(s) at the end of a section and any newline(s) preceding the next ”
Name: ” keyword or end-of-ﬁle.
// Signature Block File Example
A signature block ﬁle is a raw binary ﬁle (not base-64 encoded) that is a PKCS#7 deﬁned format signature block. The
signature block covers exactly the contents of the signer’s information ﬁle. There must be a correspondence between
the name of the signer’s information ﬁle and the signature block ﬁle. The base name matches, and the three-character
extension is modiﬁed to reﬂect the signature algorithm used according to the following rules:
• DSA signature algorithm (which uses SHA-1 hash): extension is DSA.
• RSA signature algorithm with MD5 hash: extension is RSA.
So for example with a signer’s information ﬁle name of “myinfo.SF,” the corresponding DSA signature block ﬁle name
would be “myinfo.DSA.”
24.5. Boot Integrity Services Protocol 936Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The format of a signature block ﬁle is deﬁned in [PKCS].
// "X-Intel-BIS-ParameterSet" Attribute value
// Binary Value of "X-Intel-BIS-ParameterSet" Attribute.
// (Value isBase-64 encoded inactual signed manifest).

#define BOOT_OBJECT_AUTHORIZATION_PARMSET_GUID \
{0xedd35e31,0x7b9,0x11d2,{0x83,0xa3,0x0,0xa0,0xc9,0x1f,0xad,0xcf}}
This preprocessor symbol gives the value for an attribute inserted in signed manifests to distinguish updates of BIS
parameters from updates of other parameters. The representation inserted into the manifest is base-64 encoded.
This function updates one of the conﬁgurable parameters of the Boot Object Authorization set (Boot Object Autho-
rization Certiﬁcate or Boot Authorization Check Flag). It passes back a new unique update token that must be included
in the request credential for the next update of any parameter in the Boot Object Authorization set. The token value
is unique to this platform, parameter set, and instance of parameter values. In particular, the token changes to a new
unique value whenever any parameter in this set is changed.
24.5. Boot Integrity Services Protocol 937Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.37 – continued from previous page
The signed manifest supplied as the RequestCredential parameter was
invalid (could not be parsed), or
The signed manifest supplied as the RequestCredential parameter failed to
verify using the installed Boot Object Authorization Certiﬁcate or the
signer’s Certiﬁcate in RequestCredential, or Platform-speciﬁc
authorization failed, or The signed manifest supplied as the
RequestCredential parameter did not include the X-Intel-BIS-ParameterSet
attribute value, or
TheX-Intel-BIS-ParameterSet attribute value supplied did not match the
required GUID value, or
The signed manifest supplied as the RequestCredential parameter did not
include the X-Intel-BIS-ParameterSetToken attribute value, or
TheX-Intel-BIS-ParameterSetToken attribute value supplied did not match
the platform’s current update-token value, or
include the X-Intel-BIS-ParameterId attribute value, or
TheX-Intel-BIS-ParameterId attribute value supplied did not match one of
the permitted values, or
include the X-Intel-BIS-ParameterValue attribute value, or
Any other required attribute value was missing, or
The new certiﬁcate supplied was too big to store, or
The new certiﬁcate supplied was invalid (could not be parsed), or
The new certiﬁcate supplied had an unsupported combination of key
algorithm and key length, or
The new check ﬂag value supplied is the wrong length (1 byte), or
include a signer certiﬁcate, or
include the manifest section named ” memory:UpdateRequestParameters, ”
or
The signed manifest supplied as the RequestCredential parameter had a
signing certiﬁcate with an unsupported public-key algorithm, or
The manifest section named
“memory:UpdateRequestParameters ” did not include a digest with a
digest algorithm corresponding to the signing certiﬁcate’s public key
algorithm, or
The zero-length data object referenced by the manifest section named
“memory:UpdateRequestParameters ” did not verify with the digest
supplied in that manifest section, or
include a signer’s information ﬁle with the SignerInformationName
identifying attribute value ” * BIS_UpdateManifestSignerInfoName,*” or
There were no signers associated with the identiﬁed signer’s information
ﬁle, or
There was more than one signer associated with the identiﬁed signer’s
information ﬁle, or
Any other unspeciﬁed security violation occurred.
24.5. Boot Integrity Services Protocol 938Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
An unexpected internal error occurred while analyzing the new certiﬁcate’s
key algorithm, or
An unexpected internal error occurred while attempting to retrieve the
public key algorithm of the manifest’s signer’s certiﬁcate, or
An unexpected internal error occurred in a cryptographic software module.
TheRequestCredential parameter supplied by the caller is NULL or an
TheRequestCredential.Data parameter supplied by the caller is NULL or
an invalid memory reference, or
TheNewUpdateToken parameter supplied by the caller is NULL or an
invalid memory reference.
24.5.10 EFI_BIS_PROTOCOL.VerifyBootObject()
Summary
Veriﬁes the integrity and authorization of the indicated data object according to the indicated credentials.
Prototype
typedef
(EFIAPI *EFI_BIS_VERIFY_BOOT_OBJECT)(
IN EFI_BIS_DATA *Credentials,
IN EFI_BIS_DATA *DataObject,
OUT BOOLEAN *IsVerified
);
Credentials A Signed Manifest containing veriﬁcation information for the indicated data object. The Manifest sig-
nature itself must meet the requirements described below. This parameter is optional if a Boot Authorization
Check is currently not required on this platform ( Credentials.Data may be NULL ), otherwise this parameter is
required. The required syntax of the Signed Manifest is described in the Related Deﬁnition for Manifest Syntax
below. Type EFI_BIS_DATA is deﬁned in the Initialize() function description.
DataObject An in-memory copy of the raw data object to be veriﬁed. Type EFI_BIS_DATA is deﬁned in the Initial-
ize() function description.
IsVeriﬁed The function writes TRUE if the veriﬁcation succeeded, otherwise FALSE .
24.5. Boot Integrity Services Protocol 939Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The Signed Manifest consists of three parts grouped together into an Electronic Shrink Wrap archive as described in
[SM spec]: a manifest ﬁle, a signer’s information ﬁle, and a signature block ﬁle. These three parts along with examples
are described in the following sections. In these examples, text in parentheses is a description of the text that would
appear in the signed manifest. Text outside of parentheses must appear exactly as shown. Also note that manifest
ﬁles and signer’s information ﬁles must conform to a 72-byte line-length limit. Continuation lines (lines beginning
with a single “space” character) are used for lines longer than 72 bytes. The examples given here follow this rule for
continuation lines.
the example below. This data object is the Boot Object to be veriﬁed. An example manifest ﬁle is shown below.
Name: memory:BootObject
SHA-1-Digest: (base-64 representation of a SHA-1 digest of the boot object)
This identiﬁes the section that carries the integrity data for the Boot Object. The string ” memory:BootObject ” must

appear exactly as shown. Note that the Boot Object cannot be found directly from this manifest. A caller verifying
the Boot Object integrity must load the Boot Object into memory and specify its memory location explicitly to this
veriﬁcation function through the DataObject parameter.
This enumerates the digest algorithms for which integrity data is included for the data object. For systems with DSA
signing, SHA-1 hash, and 1024-bit key length, the digest algorithm must be ” SHA-1 .” For systems with RSA signing,
MD5 hash, and 512-bit key length, the digest algorithm must be ” MD5 .” Multiple algorithms can be speciﬁed as a
whitespace-separated list. For every digest algorithm XXX listed, there must also be a corresponding XXX-Digest line.
Gives the corresponding digest value for the data object. The value is base-64 encoded.
24.5. Boot Integrity Services Protocol 940Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
section in the Manifest ﬁle. This section in the signer’s information ﬁle carries the integrity data for the corresponding
section in the manifest ﬁle. An example signer’s information ﬁle is shown below.
SignerInformationName: BIS_VerifiableObjectSignerInfoName
manifest ﬁle described earlier. The string ” memory:BootObject ” must appear exactly as shown.
24.5. Boot Integrity Services Protocol 941Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function veriﬁes the integrity and authorization of the indicated data object according to the indicated credentials.
The rules for successful veriﬁcation depend on whether or not a Boot Authorization Check is currently required on
this platform.
If a Boot Authorization Check is not currently required on this platform, no authorization check is performed. How-
ever, the following rules are applied for an integrity check:
• In this case, the credentials are optional. If they are not supplied ( Credentials.Data isNULL ), no integrity
check is performed, and the function returns immediately with a “success” indication and IsVeriﬁed isTRUE .
• If the credentials are supplied ( Credentials.Data is other than NULL ), integrity checks are performed as follows:
— Verify the credentials - The credentials parameter is a valid signed Manifest, with a single signer. The signer’s
identity is included in the credential as a certiﬁcate.
— Verify the data object - The Manifest must contain a section named ” memory:BootObject, ” with associated
veriﬁcation information (in other words, hash value). The hash value from this Manifest section must match the
hash value computed over the speciﬁed DataObject data.
—If these checks succeed, the function returns with a “success” indication and * IsVeriﬁed* is TRUE . Otherwise,
IsVeriﬁed isFALSE and the function returns with a “security violation” indication.
If a Boot Authorization Check is currently required on this platform, authorization and integrity checks are performed.
The integrity check is the same as in the case above, except that it is required. The following rules are applied:
• Verify the credentials - The credentials parameter is required in this case ( Credentials.Data must be other than
NULL ). The credentials parameter is a valid Signed Manifest, with a single signer. The signer’s identity is
included in the credential as a certiﬁcate.
• Verify the data object - The Manifest must contain a section named ” memory:BootObject, ” with associated
• Do Authorization check — This happens one of two ways depending on whether or not the platform currently
has a Boot Object Authorization Certiﬁcate conﬁgured.
— If a Boot Object Authorization Certiﬁcate is not currently conﬁgured, this function interacts with the user in
a platform-speciﬁc way to determine whether the operation should succeed.
— If a Boot Object Authorization Certiﬁcate is currently conﬁgured, this function uses the Boot Object Autho-
rization Certiﬁcate to determine whether the operation should succeed. The public key certiﬁed by the signer’s
certiﬁcate must match the public key in the Boot Object Authorization Certiﬁcate conﬁgured for this platform.
The match must be direct, that is, the signature authority cannot be delegated along a certiﬁcate chain.
24.5. Boot Integrity Services Protocol 942Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
— If these checks succeed, the function returns with a “success” indication and IsVeriﬁed isTRUE . Otherwise,
Note that if a Boot Authorization Check is currently required on this platform this function always performs an autho-
rization check, either through platform-speciﬁc user interaction or through a signature generated with the private key
corresponding to the public key in the platform’s Boot Object Authorization Certiﬁcate.
TheCredentials parameter supplied by the caller is NULL or an invalid
memory reference,
or
The Boot Authorization Check is currently required on this platform and
theCredentials.Data parameter supplied by the caller is NULL or an

or
invalid memory reference,
or
TheDataObject parameter supplied by the caller is NULL or an invalid
or
TheDataObject.Data parameter supplied by the caller is NULL or an
or
TheIsVeriﬁed parameter supplied by the caller is NULL or an invalid
The signed manifest supplied as the Credentials parameter was invalid
(could not be parsed),
or
The signed manifest supplied as the Credentials parameter failed to verify
using the installed Boot Object Authorization Certiﬁcate or the signer’s
Certiﬁcate in Credentials,
or
Platform-speciﬁc authorization failed,
or
Any other required attribute value was missing,
or
The signed manifest supplied as the Credentials parameter did not include
a signer certiﬁcate, or
24.5. Boot Integrity Services Protocol 943Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.38 – continued from previous page
the manifest section named ” memory:BootObject, ”
or
The signed manifest supplied as the Credentials parameter had a signing
certiﬁcate with an unsupported public-key algorithm,
or
The manifest section named ” memory:BootObject ” did not include a
digest with a digest algorithm corresponding to the signing certiﬁcate’s
public key algorithm,
or
The data object supplied as the DataObject parameter and referenced by
the manifest section named ” memory:BootObject ” did not verify with the
digest supplied in that manifest section,
or
a signer’s information ﬁle with the SignerInformationName identifying
attribute value ” BI S_VeriﬁableObjectSignerInfoName, ” or
ﬁle,
or
information ﬁle,
or
The platform’s check ﬂag is “on” (requiring authorization checks) but the
Credentials.Data supplied by the caller is NULL,
or
public key algorithm of the manifest’s signer’s certiﬁcate,
or
24.5.11 EFI_BIS_PROTOCOL.VerifyObjectWithCredential()
Summary
Veriﬁes the integrity and authorization of the indicated data object according to the indicated credentials and authority
certiﬁcate.
Prototype
typedef
(EFIAPI *EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL)(
24.5. Boot Integrity Services Protocol 944Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_BIS_DATA *SectionName,
IN EFI_BIS_DATA *AuthorityCertificate,
);
Credentials A Signed Manifest containing veriﬁcation information for the indicated data object. The Manifest signa-
ture itself must meet the requirements described below. The required syntax of the Signed Manifest is described
in the Related Deﬁnition of Manifest Syntax below. Type EFI_BIS_DATA is deﬁned in the Initialize() function
SectionName An ASCII string giving the section name in the manifest holding the veriﬁcation information (in other
words, hash value) that corresponds to DataObject . Type EFI_BIS_DATA is deﬁned in the Initialize() function
AuthorityCertiﬁcate A digital certiﬁcate whose public key must match the signer’s public key which is found in the
credentials. This parameter is optional ( AuthorityCertiﬁcate.Data may be NULL ). Type EFI_BIS_DATA is
deﬁned in the EFI_BIS_PROTOCOL.Initialize() function description.
IsVeriﬁed The function writes TRUE if the veriﬁcation was successful. Otherwise, the function writes FALSE .
The manifest ﬁle must include a section referring to a memory-type data object with the caller-chosen name as shown
in the example below. This data object is the Data Object to be veriﬁed. An example manifest ﬁle is shown below.
Name: (a memory-type data object name)
24.5. Boot Integrity Services Protocol 945Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SHA-1-Digest: (base-64 representation of a SHA-1 digest of the data object)
This identiﬁes the section that carries the integrity data for the target Data Object. The right-hand string must obey
the syntax for memory-type references, that is, it is of the form ” memory:SomeUniqueName .” The ” memory: ”
part of this string must appear exactly. The ” SomeUniqueName ” part is chosen by the caller. It must be unique
within the section names in this manifest ﬁle. The entire ” memory:SomeUniqueName ” string must match exactly the
corresponding string in the signer’s information ﬁle described below. Furthermore, this entire string must match the
value given for the SectionName parameter to this function. Note that the target Data Object cannot be found directly
from this manifest. A caller verifying the Data Object integrity must load the Data Object into memory and specify its
memory location explicitly to this veriﬁcation function through the DataObject parameter.

24.5. Boot Integrity Services Protocol 946Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
manifest ﬁle described earlier. The right-hand string must match exactly the corresponding string in the manifest ﬁle
described above.
24.5. Boot Integrity Services Protocol 947Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function veriﬁes the integrity and authorization of the indicated data object according to the indicated credentials
and authority certiﬁcate. Both an integrity check and an authorization check are performed. The rules for a successful
integrity check are:
• Verify the credentials - The credentials parameter is a valid Signed Manifest, with a single signer. The signer’s
• Verify the data object - The Manifest must contain a section with the name as speciﬁed by the SectionName
parameter, with associated veriﬁcation information (in other words, hash value). The hash value from this
Manifest section must match the hash value computed over the data speciﬁed by the DataObject parameter of
this function.
The authorization check is optional. It is performed only if the AuthorityCertiﬁcate.Data parameter is other than NULL
. If it is other than NULL, the rules for a successful authorization check are:
• The AuthorityCertiﬁcate parameter is a valid digital certiﬁcate. There is no requirement regarding the signer
(issuer) of this certiﬁcate.
• The public key certiﬁed by the signer’s certiﬁcate must match the public key in the AuthorityCertiﬁcate . The
match must be direct, that is, the signature authority cannot be delegated along a certiﬁcate chain.
If all of the integrity and authorization check rules are met, the function returns with a “success” indication and
IsVeriﬁed isTRUE . Otherwise, it returns with a nonzero speciﬁc error code and IsVeriﬁed isFALSE .
TheCredentials.Data parameter supplied by the caller is NULL or an
TheCredentials.Length supplied by the caller is zero, or The DataObject
parameter supplied by the caller is NULL or an invalid memory reference,
or
TheSectionName parameter supplied by the caller is NULL or an invalid
TheSectionName.Data parameter supplied by the caller is NULL or an
TheSectionName.Length supplied by the caller is zero, or
TheAuthorityCertiﬁcate parameter supplied by the caller is NULL or an
24.5. Boot Integrity Services Protocol 948Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 24.39 – continued from previous page
TheCredentials.Data supplied by the caller is NULL, or
TheAuthorityCertiﬁcate supplied by the caller was invalid (could not be
parsed), or
The signed manifest supplied as Credentials failed to verify using the
AuthorityCertiﬁcate supplied by the caller or the manifest’s signer’s
certiﬁcate, or
the manifest section named according to SectionName, or
certiﬁcate with an unsupported public-key algorithm, or
The manifest section named according to SectionName did not include a
public key algorithm, or
the manifest section named according to SectionName did not verify with
the digest supplied in that manifest section, or
ﬁle, or
24.6 DHCP options for ISCSI on IPV6
Option 59 is the iSCSI Root path
The format of the root path is “iscsi:”<servername>”:”<protocol>”:”<port>”:”<LUN>”:”<targetname>
This is per the description in IETF RFC 4173. See https://ueﬁ.org/ueﬁ#RFC4173 for a link to this document.
Option 60 is the DHCP Server address.
This is formatted the same as parameter 1 in OPT_BOOTFILE_PARAM (60) of the IPv6 address of the DHCP server
(IETF RFC 5970). See `<https://ueﬁ.org/ueﬁ>__ `a link to this document.*
24.6. DHCP options for ISCSI on IPV6 949Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.7 HTTP Boot
24.7.1 Boot from URL
Elsewhere in this speciﬁcation there is deﬁned a discoverable network boot using DHCP as a control channel allowing

a ﬁrmware client machine export its architecture type, and then have the boot server response with a binary image. For
the UEFI architecture types deﬁned in “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading
“IANA DHCPv6 parameters”, the binary image on the boot service is a UEFI-formatted executable with a machine
subsystem type that corresponds to the UEFI ﬁrmware on the client machine, or it could be mounted as a RAM disk
which contains a UEFI-compliant ﬁle system ( See File System Format ). This binary image is often referred to as
a “Network Boot Program” (NBP). The UEFI client machine that downloads the NBP uses the IPV4 or IPV6 TFTP
protocol to address the indicated server, depending upon if DHCP4 or DHCP6 was used initially, in order to download
images such as 64-bit UEFI (type 0x07).
This section deﬁnes a related method indicated by other codes in the DHCP options, in which the name and path of
the NBP are speciﬁed as a URI string in one of several formats specifying protocol and unique name identifying the
NBP for the speciﬁed protocol. In this method the NBP will be downloaded via IPV4 or IPV6 HTTP protocol if the
tag indicates x64 UEFI HTTP Boot (type code 0x0f for x86 and 0x10 for x64).
In the future other protocols such as FTP or NFS could be encoded with both new tag types and corresponding URIs
(e.g., ‘ftp://nbp.eﬁ or nfs://nbp.eﬁ, respectively). However, assignment of these type codes has not yet occurred.
The rest of this section will describe ‘HTTP Boot’ as one example of ‘boot from URI’. It is expected that the procedure
can be extended as additional protocol type codes are deﬁned.
Please reference the deﬁnitions of EFI_DNS4_PROTOCOL andEFI_DNS6_PROTOCOL elsewhere in this document.
In systems that also support one of both of these protocols, the target URI can be speciﬁed using Internet domain name
format understood by DNS servers supporting the appropriate RFC speciﬁcations.
Also, elsewhere in this document, the PXE2.1 and UEFI2.4 netboot6 sections talk about the ‘boot from TFTP’ method
of ‘boot from URI.’
The following RFC documents documents should be consulted for network message details related to the processes
described in this chapter:
1. RFC1034 - “Domain Names - Concepts and Facilities”,
2. RFC 1035 - “Domain Names - Implementation and Speciﬁcation”,
3. RFC 3513 - “Internet Protocol Version 6 (IPv6) Addressing Architecture”, , April 2003.
4. RFC 3596 - DNS Extensions to Support IP Version 6
5. RFC 2131 - Dynamic Host Conﬁguration Protocol
6. RFC 2132 - DHCP options and BOOTP Vendor Extensions
7. RFC 5970 - DHCPv6 Options for Network Boot
8. RFC 4578 - Dynamic Host Conﬁguration Protocol (DHCP) Options for the Intel Preboot eXecution Environ-
ment (PXE)
9. RFC 3986 - Uniform Resource Identiﬁers (URI): Generic Syntax, IETF, 2005
10. RFC 3004 - The User Class option
11. RFC3315 - Dynamic Host Conﬁguration Protocol for IPv6 (DHCPv6)
12. RFC3646 - DNS Conﬁguration options for Dynamic Host Conﬁguration Protocol for IPv6 (DHCPv6)
13. RFC2246 - TLS protocol Version 1.0
24.7. HTTP Boot 950Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.7.2 Concept conﬁguration for a typical HTTP Bootscenario
HTTP Boot is client-server communication based application. It combines the DHCP, DNS, and HTTP protocols to
provide the capability for system deployment and conﬁguration over the network. This new capability can be utilized
as a higher-performance replacement for tftp-based PXE boot methods of network deployment.
24.7.2.1 Use in Corporate environment
Fig. 24.4: HTTP Boot Network Topology Concept -Corporate Environment
A typical network conﬁguration which supports UEFI HTTP Boot may involve one or more UEFI client systems, and
several server systems. The Figure above show a typical HTTP Boot network topology for a corporate environment.
•UEFI HTTP Boot Client initiates the communication between the client and different server system.
•DHCP server with HTTPBoot extension for boot service discovery. Besides the standard host conﬁguration
information (such as address/subnet/gateway/name-server, etc. . . ), the DHCP server with the extensions can
also provide the discovery of URI locations for boot images on the HTTP server.
•HTTP server could be located either inside the corporate environment or across networks, such as on the
Internet. The boot resource itself is deployed on the HTTP server. In this example, “http://webserver/boot/boot.
eﬁ” is used as the boot resource. Such an application is also called a Network Boot Program (NBP). NBPs are
used to setup the client system, which may include installation of an operating system, or running a service OS
for maintenance and recovery tasks.
•DNS server is optional; and provides standard domain name resolution service.
24.7.2.2 Use case in Home environment
In a corporate environment, a standard DHCP server can be enhanced to support the HTTPBoot extension. In a
home network, generally only an optional standard DHCP server may be available for host conﬁguration information
assignment. The Figure, below, shows the concept network topology for a typical home PC environment.
Fig. 24.5: HTTP Boot Network Topology Concept2 — Homeenvironments
24.7. HTTP Boot 951Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UEFI HTTP Boot Client initiates the communication between the client and different servers. In the home conﬁgura-
tion however, the client will expect the boot resource information to be available from a source other than the standard
DHCP server, and that source does not typically have HTTPBoot extensions. Instead of DHCP, the boot URI could be
created by a UEFI application or extracted from text entered by a user.
DHCP server is optional, and if available in the network,* provides the standard service to assign host conﬁguration
information to the UEFI Client (e.g. address/subnet/gateway/name-server/etc.). In case the standard DHCP server is
not available, the same host conﬁguration information should be provided by a UEFI application or extracted from
text entered by a user prior to the client initiating the communication.
DNS Server is optional, and provides standard domain name resolution service.
24.7.3 Protocol Layout for UEFI HTTP Boot Clientconcept conﬁguration for a typi-
cal HTTP Boot scenario
This ﬁgure illustrates the UEFI network layers related to how the HTTP Boot works.
The HTTP Boot driver is layered on top of a UEFI Network stack implementation. It consumes DHCP service to
do the Boot service discovery, and DNS service to do domain name resolution if needed. It also consumes HTTP
serviced to retrieve images from the HTTP server. The functionality needed in the HTTP Boot scenario is limited to
client initiated requests to download the boot image.
TLS is consumed if HTTPS functionality is needed. The TLS design is covered in EFI TLS Protocol .
The HTTP Boot driver produces LoadFile protocol and device path protocol. BDS will provide the boot options for
the HTTP Boot. Once a boot option for HTTP boot is executed, a particular network interface is selected. HTTP Boot
driver will perform all steps on that interface and it is not required to use other interfaces.
24.7.3.1 Device Path
If both IPv4 and IPv6 are supported, the HTTP Boot driver should create two child handles, with LoadFile and
DevicePath installed on each child handle. For the device path, an IP device path node and a BootURI device path are
appended to the parent device path, for example:
PciRoot(0x0)/Pci(0x19, 0x0)/MAC(001230F4B4FF, 0x0)/IPv4(0.0.0.0, 0, DHCP, 0.0.0.0, 0.0.0.0, 0.0.0.0)/Uri()
PciRoot(0x0)/Pci(0x19, 0x0)/MAC(001230F4B4FF, 0x0)/IPv6(::/128, 0, Static, ::/128, ::/128, 0)/Uri()
Also, after retrieving the boot resource information and IP address, the BootURI device path node will be updated to
include the BootURI information. For example, if the NBP is a UEFI-formatted executable, the device patch will be
updated to
PciRoot(0x0)/Pci(0x19, 0x0)/MAC(001230F4B4FF, 0x0)/IPv4(192.168.1.100, TCP, DHCP, 192.168.1.5,
192.168.1.1, 255.255.255.0)/Uri(http://192.168.1.100/shell.eﬁ)
PciRoot(0x0)/Pci(0x19, 0x0)/MAC(001230F4B4FF, 0x0)/IPv6(2015::100, TCP, StatefulAutoConﬁgure, 2015::5,
2015::10, 64)/UriI(http://2015::100/shell.eﬁ)
These two instances allow for the boot manager to decide a preference of IPv6 versus IPv4.
If the NBP is a binary image which could be mounted as a RAM disk, the device path will be updated to
192.168.1.1, 255.255.255.0)/Uri(http://192.168.1.100/boot.iso [^])
2015::10, 64)/Uri (http://2015::100/boot.iso)
In this case, the HTTP Boot driver will register RAM disk with the downloaded NBP, by appending a RamDisk device
node to the device path above, like

updated to
24.7. HTTP Boot 952Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 24.6: UEFI HTTP Boot Protocol Layout
24.7. HTTP Boot 953Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
192.168.1.1, 255.255.255.0)/Uri(http://192.168.1.100/boot.iso )/RamDisk(0x049EA000, 0x5DEA000, 0,
3D5ABD30-4175-87CE-6D64-D2ADE523C4BB)
2015::10, 64)/Uri (http://2015::100/boot.iso)/ RamDisk(0x049EA000, 0x5DEA000, 0, 3D5ABD30-4175-87CE-
6D64-D2ADE523C4BB)
In some cases, Uri includes a host name and DNS become mandatory for translating the name to the IP address of
the host. The HTTP Boot driver may append DNS device path node immediately before Uri device path node, for
example:
192.168.1.1, 255.255.255.0)/Dns(192.168.22.100, 192.168.22.101)/Uri(http://www.bootserver.com/boot.iso )/
RamDisk(0x049EA000, 0x5DEA000, 0, 3D5ABD30-4175-87CE-6D64-D2ADE523C4BB)
2015::10, 64)/Dns(2016::100, 2016::101)/Uri (http:// www.bootserver.com/ boot.iso)/ RamDisk(0x049EA000,
0x5DEA000, 0, 3D5ABD30-4175-87CE-6D64-D2ADE523C4BB)
If HTTP Boot driver cannot obtain the DNS server addresses, it should not append an empty DNS device path node.
The boot manager could use the example device paths to match the device which produces a device path protocol
including a URI device path node in the system, without matching the Speciﬁc Device Path data in IP device path
node and URI device path node, because the IP device path node and URI device path node might be updated by
HTTP Boot driver in different scenarios.
The BootURI information could be retrieved from a DHCP server with HTTPBoot extension, or from a boot option
which includes a short-form URI device path, or from a boot option which includes a URI device path node, or created
by a UEFI application or extracted from text entered by a user.
Once the HTTP Boot driver retrieves the BootURI information from the short-form URI device path, it will perform all
other steps for HTTP boot except retrieving the BootURI from DHCP server. Also, when the short-form URI device
path is inputted to HTTP Boot driver via LoadFile protocol, the HTTP Boot driver should expand the short-form
URI device path to above example device path after retrieving IP address conﬁguration (address, subnet, gateway, and
optionally the name-server) from the DHCP server. In case of the home environment with no DHCP server, the same
information may be provisioned by OEM or input by the end user through Setup Options. The IP and optional DNS
device path nodes, constructed with this information and preﬁxed to the short-form URI device path, can be inputted
to the HTTP Boot driver via LoadFile protocol. The name server information in the form of DNS device path node
is optional, and is used only when the BootURI contains the server name or FQDN. The HTTP Boot driver will then
consume the information in the device path and initiate the necessary communication.
Once the HTTP Boot driver retrieves the BootURI information from a boot option which includes a URI device path
node, it should retrieve the IP address conﬁguration from the IP device path node of the same boot option. If the IP
address conﬁguration or BootURI information is empty, the HTTP Boot driver could retrieve the required information
from DHCP server. If the IP address conﬁguration or BootURI information is not empty but invalid, the HTTP boot
process will fail.
The HTTP Boot block diagram ( UEFI HTTP Boot Protocol Layout ) describes a suggested implementation for HTTP
Boot. Other implementation can create their own HTTP Netboot Driver which meets the requirements for their netboot
methodology
24.7. HTTP Boot 954Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.7.4 Concept of Message Exchange in a typical HTTPBoot scenario (IPv4 in Cor-
porate Environment)
In summary, the newly installed networked client machine (UEFI HTTP Boot Client) should be able to enter a hetero-
geneous network, acquire a network address from a DHCP server, and then download an NBP to set itself up.
The concept of HTTP Boot message exchange sequence is as follows. The client initiates the DHCPv4 D.O.R.A
process by broadcasting a DHCPDISCOVER containing the extension that identiﬁes the request as coming from a
client that implements the HTTP Boot functionality. Assuming that a DHCP server or a Proxy DHCP server im-
plementing this extension is available, after several intermediate steps, besides the standard conﬁguration such as
address/subnet/router/dns-server, boot resource location will be provided to the client system in the format of a URI.
The URI points to the NBP which is appropriate for this client hardware conﬁguration. A boot option is created, and
if selected by the system logic the client then uses HTTP to download the NBP from the HTTP server into memory.
Finally, the client executes the downloaded NBP image from memory. This image can then consume other UEFI
interfaces for further system setup.
Fig. 24.7: HTTP Boot Overall Flow
24.7.4.1 Message exchange between EFI Client and DHCPserver using DHCP Client Extensions
24.7.4.1.1 Client broadcast
The client broadcasts a DHCP Discover message to the standard DHCP port (67).
An option ﬁeld in this packet contains the following:
• Fill DHCP option 55 - Parameter Requested List option
– Address conﬁguration, Server information, Name server, Vendor class identiﬁer
• A DHCP option 97: UUID/GUID-based Client Identiﬁer
• A DHCP option 94: Client Network Identiﬁer Option
– If support UNDI, ﬁll this option (Refer RFC5970)
24.7. HTTP Boot 955Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• A DHCP option 93: the client system architecture (Refer [Arch-Type])
– 0x0F - x86 UEFI HTTP Boot
– 0x10 - x64 UEFI HTTP Boot
• A DHCP option 60, Vendor Class ID, set to “HTTPClient:Arch:XXXX:UNDI:YYYZZZ”
DHCP server response
The DHCP server responds by sending DHCPOFFER message on standard DHCP reply port (68).
The HTTP Boot Client may possibly receive multiple DHCPOFFER packets from different sources of DHCP Services,
possibly from DHCP Services which recognize the HTTP extensions or from Standard DHCP Services.
A service recognizing HTTP extensions must respond with an offer that has Option 60 (Vendor class identiﬁer) pa-
rameter set to “HTTPClient”, in response to the Vendor class identiﬁer requested in option 55 in the DHCP Discover
message.
Each message contains standard DHCP parameters: an IP address for the client and any other parameters that the
administrator might have conﬁgured on the DHCP or Proxy DHCP Service. The DHCP service or Proxy DHCP
which recognizes the HTTPBoot extension will provide DHCPOFFER with HTTPClient extensions. If this is a Proxy
DHCP service, then the client IP address ﬁeld is (0.0.0.0). If this is from a DHCP service, then the returned client IP
address ﬁeld is valid.
From the received DHCPOFFER(s), the client records the information as follows:
• Client IP address (and other parameters) offered by a standard DHCP/BOOTP services.
• If Boot URI information is provided thru ‘ﬁle’ ﬁeld in DHCP Header or option 67, then the client will record
the information as well.
• Optional Name-server information if URI is displayed using domain-name
– Timeout : After Client sent out the DHCP Discover packet, the Client will wait for a timeout to collect
enough DHCP Offers. If failed to retrieve all the required information, the DHCP Discover will be retried,
at most four times. The four timeout mechanisms is 4, 8, 16 and 32 seconds respectively,
– Priority : Among all the received DHCPOFFERs, the Priority is considered as follows:
24.7.5 Priority1
Choose the DHCPOFFER that provides all required information:
<IP address conﬁguration, Boot URI conﬁguration, Name-server conﬁguration (if domain-name used in Boot URI)>
If Boot URI and IP address conﬁguration provided in different DHCPOFFER, Using 5 DHCPOFFER as example for
priority description
• Packet1 - DHCPOFFER, provide <IP address conﬁguration, Name server>
• Packet2 - DHCPOFFER, provide <IP address conﬁguration>
• Packet3 - DHCPOFFER, provide <domain-name expressed URI>
• Packet4 - DHCPOFFER, provide <IP address expressed URI>
• Packet5 - DHCPOFFER, provide <IP address, domain-name expressed URI>
Then,
24.7. HTTP Boot 956Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.7.6 Priority2
Choose the DHCPOFFER from different packet, ﬁrstly ﬁnd out URI info represented in IP address mode, then choose
DHCPOFFER which provide IP address conﬁguration
In this example, the chosen DHCPOFFER packet is packet4 + packet1 / packet 2 (packet 1/2 take same priority,

Then,
implementation can make its own implementation choice)
24.7.7 Priority3
Choose the DHCPOFFER from different packet, ﬁrstly ﬁnd out URI info represented in domain-name mode, then
choose DHCPOFFER which provide <IP address conﬁguration, domain-name expressed URI>
In this example, the chosen DHCPOFFER packet is packet3 / packet5 + packet1
NOTE :If packet5, then client IP address assigned by Packet5 will be override by IP address in packet1.
24.7.8 Priority4
If failed to retrieve <Boot URI / IP address / (on-demand) Name-server> information through all received DHCPOF-
FERs, this is deemed as FAILED-CONFIGURATION
Assuming the boot image is in the boot subdirectory of the web server root, the supported URI could be one of below
formats. [RFC3986] where ‘/boot/’ is replaced by administrator-created directory, and ‘image’ is the ﬁle name of the
NBP.
http://reg-name:port/boot/image
http://ipv4address:port/boot/image
http://ipv6address:port/boot/image
In the URL example, Port is optional if web service is provided through port 80 for the HTTP data transfer. Commonly,
the reg-name use DNS as name registry mechanism.
After retrieving the boot URI through Device Path , if IP address (either IPv4 or IPv6 address) is provided, the HTTP
Boot Client can directly use that address for next step HTTP transfer. If a reg-name is provided in the URI, the HTTP
Boot Client driver need initiate DNS process ( See Message in DNS Query/Reply ) to resolve its IP address.
DHCP Request
The HTTP Boot Client selects an IP address offered by a DHCP Service, and then it completes the standard DHCP
protocol by sending a DHCP Request packet for the address to the DHCP Server and waiting for acknowledgement
from the DHCP server.
DHCP ACK
The server acknowledges the IP address by sending DHCP ACK packet to the client.
24.7. HTTP Boot 957Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.7.8.1 Message exchange between UEFI Client and DHCPserver not using DHCP Client Exten-
sions
In a home environment, because the Boot URI Information will not be provided by the DHCP Offers, we need other
channels to provide this information. The implementation suggestion is provisioning this information by OEM or input
by end user through Setup Options, henceforth, the UEFI Boot Client already know the Boot URI before contacting
the DHCP server.
The message exchange between the EFI Client and DHCP server will be standard DHCP D.O.R.A to obtain <IP
address, Name-server>.
In the case of a home environment without a DHCP server, the above message exchange is not needed, and the UEFI
HTTP Boot Client will have the <IP address, Name-server> provisioned by OEM or input by the end user through
Setup Options.
24.7.8.2 Message in DNS Query/Reply
The DNS Query/Reply is a standard process deﬁned in DNS Protocol [RFC 1034, RFC 1035]. Multiple IP address
might be retrieved from the DNS process. It’s the HTTP Boot Client driver’s responsibility to select proper IP address
automatically or expose user interface for customer to decide proper IP address.
24.7.8.3 Message in HTTP Download
In the HTTP Boot scenario, HTTP GET message is used to get image from the Web server.
24.7.9 Concept of Message Exchange in HTTP Bootscenario (IPv6)
24.7.9.1 Message exchange between EFI Client andDHCPv6 server with DHCP Client extensions
24.7.9.1.1 Client multicast a DHCPv6 Solicit messageto the standard DHCPv6 port (547)
Besides the options required for address auto-conﬁguration, option ﬁeld in this packet also contains the following:
• Fill DHCPv6 Option 6 - Option Request Option
— Request server to supply option 59 (OPT_BOOTFILE_URL), option 60 ( OPT_BOOTFILE_PARAM), op-
tion 23 (OPT_DNS_SERVERS), option 16 (OPTION_VENDOR_CLASS).
• A DHCPv6 option 1, Client identiﬁer
• A DHCPv6 option 16, Vendor Class ID, set to “HTTPClient:Arch:XXXX:UNDI:YYYZZZ”
• A DHCPv6 option 61: the client system architecture (Refer [Arch-Type])
— 0x0F - x86 UEFI HTTP Boot
— 0x10 - x64 UEFI HTTP Boot
• A DHCPv6 option 62: Client Network Identiﬁer Option
— If support UNDI, ﬁll this option (Refer RFC5970)
24.7. HTTP Boot 958Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.7.9.1.2 Server unicast DHCPv6 Advertisement to theClient to the DHCPv6 port (546)
The HTTP Boot Client will receive multiple advertisements from different sources of DHCPv6 Services, possibly
from DHCPv6 Services which recognize the HTTP extensions or from Standard DHCPv6 Services.
A DHCPv6 service recognizing HTTP extensions must respond with an Advertisement that has Option 16 (OP-
TION_VENDOR_CLASS) parameter set to “HTTPClient”, in response to the OPTION_VENDOR_CLASS requested
in Option 6 in the DHCPv6 Solicit message.
Each message contains standard DHCP parameters: Identify Association (IA) option which conveys information
including <IP address, lifetime, etc. . . >. Name server option conveys the DNS server address. The DHCP service
or Proxy DHCP which recognizes the HTTPBoot extension will provide DHCPv6 Advertisement with HTTPClient
extensions, including Boot URI and Optional Boot Parameters.
• Client IP address (and other parameters) provide through IA option
• Boot URI provided thru option 59
• Optional BootFile Parameter provided through option 60 (if no other parameter needed for this boot URI, this
option can be eliminated)
• Optional Name-server information provided through option 23, if URI is displayed using domain-name.
24.7.9.1.3 Client multicast DHCPv6 Request to the selected DHCP Advertisement to conﬁrm the
IPaddress assigned by that server
This packet is the same with the DHCPv6 Solicit packet except for the message type is Request.
24.7.9.1.4 Server unicast the DHCPv6 Reply toacknowledge the Client IP address for the UEFI HTTP-
Client
24.7.9.2 Message exchange between UEFI Client andDHCPv6 server not using DHCP Client Exten-
sions
In a home environment, the Boot URI Information will not be provided by the DHCPv6 Offers, we need other channels
to provide this information. Like what is described in Message exchange between UEFI Client and DHCPserver not
using DHCP Client Extensions , the implementation suggestion is provisioning this information by OEM or input by
end user through Setup Options, henceforth, the UEFI Boot Client already know the Boot URI before contacting the
DHCP server.
The message exchange between the EFI Client and DHCP server will be standard DHCP S.A.R.R. to obtain <IP
In the case of a home environment without a DHCPv6 server, the above message exchange is not needed, and the UEFI
24.7. HTTP Boot 959Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
24.7.9.3 Message exchange between UEFI Client and DNS6server
The DNS Query/Reply for domain name resolution is the same process as described in See Message in DNS
Query/Reply .
24.7.9.4 Message in HTTP Download
HTTP Download process is the same process as described in Message in HTTP Download .
24.7.10 EFI HTTP Boot Callback Protocol
This section deﬁnes the EFI HTTP Boot Callback Protocol that is invoked when the HTTP Boot driver is about to
transmit or has received a packet. The EFI HTTP Boot Callback Protocol must be installed on the same handle as the
Load File Protocol for the HTTP Boot.
24.7.11 EFI_HTTP_BOOT_CALLBACK_PROTOCOL
Summary
Protocol that is invoked when the HTTP Boot driver is about to transmit or has received a packet.
GUID
#define EFI_HTTP_BOOT_CALLBACK_PROTOCOL_GUID \
{0xba23b311, 0x343d, 0x11e6, {0x91, 0x85, 0x58,0x20, 0xb1, 0xd6, 0x52, 0x99}}
typedef struct \_EFI_HTTP_BOOT_CALLBACK_PROTOCOL {
EFI_HTTP_BOOT_CALLBACK Callback;
} EFI_HTTP_BOOT_CALLBACK_PROTOCOL;
Callback Callback routine used by the HTTP Boot driver.
24.7.12 EFI_HTTP_BOOT_CALLBACK_PROTOCOL.Callback()
Summary
Callback function that is invoked when the HTTP Boot driver is about to transmit or has received a packet.
Prototype
typedef
(EFIAPI *EFI_HTTP_BOOT_CALLBACK) (
IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL *This,
IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPE DataType,
IN UINT32 DataLength,
IN VOID *Data OPTIONAL
);
24.7. HTTP Boot 960Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This Pointer to the EFI_HTTP_BOOT_CALLBACK_PROTOCOL instance.
DataType The event that occurs in the current state. Type EFI_HTTP_BOOT_CALLBACK_DATA_TYPE is deﬁned
below.
DataLength The length in bytes of the buffer pointed to by Data .
Data A pointer to the buffer of data, the data type is speciﬁed by DataType .
//**********************************************
// EFI_HTTP_BOOT_CALLBACK_DATA_TYPE

Summary
Prototype
typedef
);
below.
HttpBootDhcp4,
HttpBootDhcp6,
HttpBootHttpRequest,
HttpBootHttpResponse,
HttpBootHttpEntityBody,
HttpBootTypeMax
} EFI_HTTP_BOOT_CALLBACK_DATA_TYPE;
HttpBootDhcp4 Data points to a DHCP4 packet which is about to transmit or has received.
HttpBootDhcp6 Data points to a DHCP6 packet which is about to be transmit or has received.
HttpBootHttpRequest Data points to an EFI_HTTP_MESSAGE structure, which contians a HTTP request message
to be transmitted.
HttpBootHttpResponse Data points to an EFI_HTTP_MESSAGE structure, which contians a received HTTP re-
sponse message.
HttpBootHttpEntityBody Part of the entity body has been received from the HTTP server. Data points to the buffer
of the entity body data.
This function is invoked when the HTTP Boot driver is about to transmit or has received packet. Parameters DataType
andReceived specify the type of event and the format of the buffer pointed to by Data . Due to the polling nature of
UEFI device drivers, this callback function should not execute for more than 5 ms. The returned status code determines
the behavior of the HTTP Boot driver.
EFI_SUCCESS Tells the HTTP Boot driver to continue the HTTP Boot process.
EFI_ABORTED Tells the HTTP Boot driver to abort the current HTTP Boot process.
24.7. HTTP Boot 961CHAPTER
TWENTYFIVE
NETWORK PROTOCOLS - MANAGED NETWORK
25.1 EFI Managed Network Protocol
This chapter deﬁnes the EFI Managed Network Protocol. It is split into the following two main sections:
• Managed Network Service Binding Protocol (MNSBP)
• Managed Network Protocol (MNP)
The MNP provides raw (unformatted) asynchronous network packet I/O services. These services make it possible for
multiple-event-driven drivers and applications to access and use the system network interfaces at the same time.
25.1.1 EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL
Summary
The MNSBP is used to locate communication devices that are supported by an MNP driver and to create and destroy
instances of the MNP child protocol driver that can use the underlying communications device.
The EFI Service Binding Protocol in EFI Services Binding deﬁnes the generic Service Binding Protocol functions.
This section discusses the details that are speciﬁc to the MNP.
GUID
#define EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL_GUID \
{0xf36ff770,0xa7e1,0x42cf,\
{0x9e,0xd2,0x56,0xf0,0xf2,0x71,0xf4,0x4c}}
A network application (or driver) that requires shared network access can use one of the protocol handler services,
such as BS->LocateHandleBuffer() , to search for devices that publish an MNSBP GUID. Each device with a published
MNSBP GUID supports MNP and may be available for use.
After a successful call to the EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL.CreateChild() func-
tion, the child MNP driver instance is in an unconﬁgured state; it is not ready to send and receive data packets.
Before a network application terminates execution, every successful call to the
EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched
with a call to the EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
962Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
25.1.2 EFI_MANAGED_NETWORK_PROTOCOL
Summary
The MNP is used by network applications (and drivers) to perform raw (unformatted) asynchronous network packet
I/O.
GUID
#define EFI_MANAGED_NETWORK_PROTOCOL_GUID\
{0x7ab33a91, 0xace5, 0x4326,\
{0xb5, 0x72, 0xe7, 0xee, 0x33, 0xd3, 0x9f, 0x16}}
typedef struct \_EFI_MANAGED_NETWORK_PROTOCOL {
EFI_MANAGED_NETWORK_GET_MODE_DATA GetModeData;
EFI_MANAGED_NETWORK_CONFIGURE Configure;
EFI_MANAGED_NETWORK_MCAST_IP_TO_MAC McastIpToMac;
EFI_MANAGED_NETWORK_GROUPS Groups;
EFI_MANAGED_NETWORK_TRANSMIT Transmit;
EFI_MANAGED_NETWORK_RECEIVE Receive;
EFI_MANAGED_NETWORK_CANCEL Cancel;
EFI_MANAGED_NETWORK_POLL Poll;
} EFI_MANAGED_NETWORK_PROTOCOL;
GetModeData Returns the current MNP child driver operational parameters. May also support returning underlying
Simple Network Protocol (SNP) driver mode data. See the GetModeData() function description.
Conﬁgure Sets the Conﬁgure() function description.
McastIpToMac Translates a software (IP) multicast address to a hardware (MAC) multicast address. This function
may be unsupported in some MNP implementations. See the McastIpToMac() function description.
Groups Enables and disables receive ﬁlters for multicast addresses. This function may be unsupported in some MNP
implementations. See the Groups() function description.
Transmit Places asynchronous outgoing data packets into the transmit queue. See the Transmit() function description.
Receive Places an asynchronous receiving request into the receiving queue. See the Receive() function description.
Cancel Aborts a pending transmit or receive request. See the Cancel() function description.
Poll Polls for incoming data packets and processes outgoing data packets. See the Poll() function description.
The services that are provided by MNP child drivers make it possible for multiple drivers and applications to send and
receive network trafﬁc using the same network device.
Before any network trafﬁc can be sent or received, the EFI_MANAGED_NETWORK_PROTOCOL.Conﬁgure() func-
tion must initialize the operational parameters for the MNP child driver instance. Once conﬁgured, data packets can
be received and sent using the following functions:
• EFI_MANAGED_NETWORK_PROTOCOL.Transmit()
• EFI_MANAGED_NETWORK_PROTOCOL.Receive()
• EFI_MANAGED_NETWORK_PROTOCOL.Poll()
25.1. EFI Managed Network Protocol 963Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
25.1.3 EFI_MANAGED_NETWORK_PROTOCOL.GetModeData()
Summary
Returns the operational parameters for the current MNP child driver. May also support returning the underlying SNP
driver mode data.
Prototype
typedef
(EFIAPI *EFI_MANAGED_NETWORK_GET_MODE_DATA) (
IN EFI_MANAGED_NETWORK_PROTOCOL *This,
OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL,
OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL
);
This Pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
MnpConﬁgData Pointer to storage for MNP operational parameters. Type
EFI_MANAGED_NETWORK_CONFIG_DATA is deﬁned in “Related Deﬁnitions” below.
SnpModeData Pointer to storage for SNP operational parameters. This feature may be unsupported. Type
EFI_SIMPLE_NETWORK_MODE is deﬁned in the EFI_SIMPLE_NETWORK_PROTOCOL .
The GetModeData() function is used to read the current mode data (operational parameters) from the MNP or the
underlying SNP.
// EFI_MANAGED_NETWORK_CONFIG_DATA
UINT32 ReceivedQueueTimeoutValue;
UINT32 TransmitQueueTimeoutValue;
UINT16 ProtocolTypeFilter;
BOOLEAN EnableUnicastReceive;
BOOLEAN EnableMulticastReceive;
BOOLEAN EnableBroadcastReceive;
BOOLEAN EnablePromiscuousReceive;
BOOLEAN FlushQueuesOnReset;
BOOLEAN EnableReceiveTimestamps;
BOOLEAN DisableBackgroundPolling;
} EFI_MANAGED_NETWORK_CONFIG_DATA;
ReceivedQueueTimeoutValue Timeout value for a UEFI one-shot timer event. A packet that has not been removed
from the MNP receive queue by a call to EFI_MANAGED_NETWORK_PROTOCOL.Poll() will be dropped if
its receive timeout expires. If this value is zero, then there is no receive queue timeout. If the receive queue ﬁlls
up, then the device receive ﬁlters are disabled until there is room in the receive queue for more packets. The
startup default value is 10,000,000 (10 seconds).
TransmitQueueTimeoutValue Timeout value for a UEFI one-shot timer event. A packet that has not been removed
from the MNP transmit queue by a call to EFI_MANAGED_NETWORK_PROTOCOL.Poll() will be dropped if
its transmit timeout expires. If this value is zero, then there is no transmit queue timeout. If the transmit queue
ﬁlls up, then the EFI_MANAGED_NETWORK_PROTOCOL.Transmit() function will return EFI_NOT_READY
until there is room in the transmit queue for more packets. The startup default value is 10,000,000 (10 seconds).
25.1. EFI Managed Network Protocol 964Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ProtocolTypeFilter Ethernet type II 16-bit protocol type in host byte order. Valid values are zero and 1,500 to 65,535.
Set to zero to receive packets with any protocol type. The startup default value is zero.
EnableUnicastReceive Set to TRUE to receive packets that are sent to the network device MAC address. The startup
default value is FALSE .
EnableMulticastReceive Set to TRUE to receive packets that are sent to any of the active multicast groups. The
startup default value is FALSE .
EnableBroadcastReceive Set to TRUE to receive packets that are sent to the network device broadcast address. The

EnablePromiscuousReceive Set to TRUE to receive packets that are sent to any MAC address. Note that setting this
ﬁeld to TRUE may cause packet loss and degrade system performance on busy networks. The startup default
value is FALSE .
FlushQueuesOnReset Set to TRUE to drop queued packets when the conﬁguration is changed. The startup default
EnableReceiveTimestamps Set to TRUE to timestamp all packets when they are received by the MNP. Note that
timestamps may be unsupported in some MNP implementations. The startup default value is FALSE .
DisableBackgroundPolling Set to TRUE to disable background polling in this MNP instance. Note that background
polling may not be supported in all MNP implementations. The startup default value is FALSE , unless back-
ground polling is not supported.
EFI_UNSUPPORTED The requested feature is unsupported in this MNP implementation.
EFI_NOT_STARTED This MNP child driver instance has not been conﬁgured. The default values
are returned in MnpConﬁgData if it is not NULL .
Other The mode data could not be read.
25.1.4 EFI_MANAGED_NETWORK_PROTOCOL.Conﬁgure()
Summary
Sets or clears the operational parameters for the MNP child driver.
Prototype
typedef
(EFIAPI *EFI_MANAGED_NETWORK_CONFIGURE) (
IN EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL
);
MnpConﬁgData Pointer to conﬁguration data that will be assigned to the MNP child driver instance.
IfNULL , the MNP child driver instance is reset to startup defaults and all pending transmit
and receive requests are ﬂushed. Type EFI_MANAGED_NETWORK_CONFIG_DATA is deﬁned in
EFI_MANAGED_NETWORK_PROTOCOL.GetModeData() .
25.1. EFI Managed Network Protocol 965Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheConﬁgure() function is used to set, change, or reset the operational parameters for the MNP child driver instance.
Until the operational parameters have been set, no network trafﬁc can be sent or received by this MNP child driver
instance. Once the operational parameters have been reset, no more trafﬁc can be sent or received until the operational
parameters have been set again.
Each MNP child driver instance can be started and stopped independently of each other by setting or resetting their
receive ﬁlter settings with the Conﬁgure() function.
After any successful call to Conﬁgure() , the MNP child driver instance is started. The internal periodic timer (if
supported) is enabled. Data can be transmitted and may be received if the receive ﬁlters have also been enabled.
NOTE: If multiple MNP child driver instances will receive the same packet because of overlapping receive ﬁlter
settings, then the ﬁrst MNP child driver instance will receive the original packet and additional instances will receive
copies of the original packet .
NOTE: WARNING :Receive ﬁlter settings that overlap will consume extra processor and/or DMA resources and
degrade system and network performance .
•This isNULL .
•MnpConﬁgData.ProtocolTypeFilter is not valid.
• The operational data for the MNP child driver instance is unchanged.
EFI_OUT_OF_RESOURCES
Required system resources (usually memory) could not be allocated.
The MNP child driver instance has been reset to startup defaults.
The requested feature is unsupported in this [MNP] implementation.
The operational data for the MNP child driver instance is unchanged.
An unexpected network or system error occurred.
Other The MNP child driver instance has been reset to startup defaults.
25.1.5 EFI_MANAGED_NETWORK_PROTOCOL.McastIpToMac()
Summary
Translates an IP multicast address to a hardware (MAC) multicast address. This function may be unsupported in some
MNP implementations.
Prototype
typedef
(EFIAPI *EFI_MANAGED_NETWORK_MCAST_IP_TO_MAC) (
25.1. EFI Managed Network Protocol 966Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN BOOLEAN Ipv6Flag,
IN EFI_IP_ADDRESS *IpAddress,
OUT EFI_MAC_ADDRESS *MacAddress
);
Ipv6Flag Set to TRUE to if IpAddress is an IPv6 multicast address.
Set to FALSE ifIpAddress is an IPv4 multicast address.
IpAddress Pointer to the multicast IP address (in network byte order) to convert.
MacAddress Pointer to the resulting multicast MAC address.
TheMcastIpToMac() function translates an IP multicast address to a hardware (MAC) multicast address.
This function may be implemented by calling the underlying EFI_SIMPLE_NETWORK.MCastIpToMac() function,
which may also be unsupported in some MNP implementations.
One of the following conditions is TRUE :
•IpAddress isNULL .
• *IpAddress is not a valid multicast IP address.
•MacAddress isNULL .
EFI_NOT_STARTED This MNP child driver instance has not been conﬁgured.
EFI_DEVICE_ERROR An unexpected network or system error occurred.
Other The address could not be converted.
25.1.6 EFI_MANAGED_NETWORK_PROTOCOL.Groups()
Summary
Enables and disables receive ﬁlters for multicast address. This function may be unsupported in some MNP implemen-
tations.
Prototype
typedef
(EFIAPI *EFI_MANAGED_NETWORK_GROUPS) (
IN BOOLEAN JoinFlag,
IN EFI_MAC_ADDRESS *MacAddress OPTIONAL
);
25.1. EFI Managed Network Protocol 967Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
JoinFlag
Set to TRUE to join this multicast group.
Set to FALSE to leave this multicast group.
MacAddress Pointer to the multicast MAC group (address) to join or leave.
TheGroups() function only adds and removes multicast MAC addresses from the ﬁlter list. The MNP driver does not
transmit or process Internet Group Management Protocol (IGMP) packets.
IfJoinFlag isFALSE andMacAddress isNULL , then all joined groups are left.
EFI_SUCCESS The requested operation completed successfully.
•JoinFlag isTRUE andMacAddress isNULL .
• *MacAddress is not a valid multicast MAC address.
The MNP multicast group settings are unchanged.
EFI_ALREADY_STARTED The supplied multicast group is already joined.
EFI_NOT_FOUND The supplied multicast group is not joined.
Other The requested operation could not be completed. The MNP multicast group
settings are unchanged.
25.1.7 EFI_MANAGED_NETWORK_PROTOCOL.Transmit()
Summary
Places asynchronous outgoing data packets into the transmit queue.
Prototype
typedef
(EFIAPI *EFI_MANAGED_NETWORK_TRANSMIT) (
IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token
);
25.1. EFI Managed Network Protocol 968Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Token Pointer to a token associated with the transmit data descriptor. Type
EFI_MANAGED_NETWORK_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions” below.
The Transmit() function places a completion token into the transmit packet queue. This function is always asyn-
chronous.
The caller must ﬁll in the Token.Event andToken.TxData ﬁelds in the completion token, and these ﬁelds cannot
beNULL . When the transmit operation completes, the MNP updates the Token.Status ﬁeld and the Token.Event is
signaled.
NOTE There may be a performance penalty if the packet needs to be defragmented before it can be transmitted by the
network device. Systems in which performance is critical should review the requirements and features of the underlying
communications device and drivers .
//****************************************************
// EFI_MANAGED_NETWORK_COMPLETION_TOKEN
union {
EFI_MANAGED_NETWORK_RECEIVE_DATA *RxData;
EFI_MANAGED_NETWORK_TRANSMIT_DATA *TxData;
} Packet;
} EFI_MANAGED_NETWORK_COMPLETION_TOKEN;

chronous.
signaled.
union {
} Packet;
Event This Event will be signaled after the Status ﬁeld is updated by the MNP. The type of Event must
beEVT_NOTIFY_SIGNAL . The Task Priority Level (TPL) of Event must be lower than or equal to
TPL_CALLBACK.
Status
This ﬁeld will be set to one of the following values:
EFI_SUCCESS: The receive or transmit completed successfully.
EFI_ABORTED: The receive or transmit was aborted.
EFI_TIMEOUT: The transmit timeout expired.
EFI_DEVICE_ERROR: There was an unexpected system or network error.
EFI_NO_MEDIA: There was a media error
RxData When this token is used for receiving, RxData is a pointer to the
EFI_MANAGED_NETWORK_RECEIVE_DATA .
TxData When this token is used for transmitting, TxData is a pointer to the
EFI_MANAGED_NETWORK_TRANSMIT_DATA .
TheEFI_MANAGED_NETWORK_COMPLETION_TOKEN structure is used for both transmit and receive operations.
When it is used for transmitting, the Event andTxData ﬁelds must be ﬁlled in by the MNP client. After the transmit
operation completes, the MNP updates the Status ﬁeld and the Event is signaled.
When it is used for receiving, only the Event ﬁeld must be ﬁlled in by the MNP client. After a packet is received, the
MNP ﬁlls in the RxData andStatus ﬁelds and the Event is signaled.
// EFI_MANAGED_NETWORK_RECEIVE_DATA
25.1. EFI Managed Network Protocol 969Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_TIME Timestamp;
EFI_EVENT RecycleEvent;
UINT32 PacketLength;
UINT32 HeaderLength;
UINT32 AddressLength;
UINT32 DataLength;
BOOLEAN roadcastFlag;
BOOLEAN MulticastFlag;
BOOLEAN PromiscuousFlag;
UINT16 ProtocolType;
VOID *DestinationAddress;
VOID *SourceAddress;
VOID *MediaHeader;
VOID *PacketData;
} EFI_MANAGED_NETWORK_RECEIVE_DATA;
Timestamp System time when the MNP received the packet. Timestamp is zero ﬁlled if receive timestamps are
disabled or unsupported.
RecycleEvent MNP clients must signal this event after the received data has been processed so that the receive queue
storage can be reclaimed. Once RecycleEvent is signaled, this structure and the received data that is pointed to
by this structure must not be accessed by the client.
PacketLength Length of the entire received packet (media header plus the data).
HeaderLength Length of the media header in this packet.
AddressLength Length of a MAC address in this packet.
DataLength Length of the data in this packet.
BroadcastFlag Set to TRUE if this packet was received through the broadcast ﬁlter. (The destination MAC address
is the broadcast MAC address.)
MulticastFlag Set to TRUE if this packet was received through the multicast ﬁlter. (The destination MAC address is
in the multicast ﬁlter list.)
PromiscuousFlag Set to TRUE if this packet was received through the promiscuous ﬁlter. (The destination address
does not match any of the other hardware or software ﬁlter lists.)
ProtocolType 16-bit protocol type in host byte order. Zero if there is no protocol type ﬁeld in the packet header.
DestinationAddress Pointer to the destination address in the media header.
SourceAddress Pointer to the source address in the media header.
MediaHeader Pointer to the ﬁrst byte of the media header.
PacketData Pointer to the ﬁrst byte of the packet data (immediately following media header).
AnEFI_MANAGED_NETWORK_RECEIVE_DATA structure is ﬁlled in for each packet that is received by the MNP.
If multiple instances of this MNP driver can receive a packet, then the receive data structure and the received packet
are duplicated for each instance of the MNP driver that can receive the packet.
// EFI_MANAGED_NETWORK_TRANSMIT_DATA
EFI_MAC_ADDRESS *DestinationAddress OPTIONAL;
25.1. EFI Managed Network Protocol 970Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_MAC_ADDRESS *SourceAddress OPTIONAL;
UINT16 ProtocolType OPTIONAL;
UINT16 HeaderLength OPTIONAL;
UINT16 FragmentCount;
EFI_MANAGED_NETWORK_FRAGMENT_DATA FragmentTable[1];
} EFI_MANAGED_NETWORK_TRANSMIT_DATA;
DestinationAddress Pointer to the destination MAC address if the media header is not included in FragmentTable[] .
IfNULL , then the media header is already ﬁlled in FragmentTable[] .
SourceAddress Pointer to the source MAC address if the media header is not included in FragmentTable[] . Ignored
ifDestinationAddress isNULL .
ProtocolType The protocol type of the media header in host byte order. Ignored if DestinationAddress isNULL .
DataLength Sum of all FragmentLength ﬁelds in FragmentTable[] minus the media header length.
HeaderLength Length of the media header if it is included in the FragmentTable . Must be zero if DestinationAddress
is not NULL .
FragmentCount Number of data fragments in FragmentTable[] . This ﬁeld cannot be zero.
FragmentTable Table of data fragments to be transmitted. The ﬁrst byte of the ﬁrst entry in FragmentTable[]
is also the ﬁrst byte of the media header or, if there is no media header, the ﬁrst byte of payload. Type
EFI_MANAGED_NETWORK_FRAGMENT_DATA is deﬁned below.
TheEFI_MANAGED_NETWORK_TRANSMIT_DATA structure describes a (possibly fragmented) packet to be trans-
mitted.
TheDataLength ﬁeld plus the HeaderLength ﬁeld must be equal to the sum of all of the FragmentLength ﬁelds in the
FragmentTable .
If the media header is included in FragmentTable[] , then it cannot be split between fragments.
// EFI_MANAGED_NETWORK_FRAGMENT_DATA
UINT32 FragmentLength;
VOID *FragmentBuffer;
} EFI_MANAGED_NETWORK_FRAGMENT_DATA;
FragmentLength Number of bytes in the FragmentBuffer . This ﬁeld may not be set to zero.
FragmentBuffer Pointer to the fragment data. This ﬁeld may not be set to NULL .
TheEFI_MANAGED_NETWORK_FRAGMENT_DATA structure describes the location and length of a packet frag-
ment to be transmitted.
EFI_SUCCESS The transmit completion token was cached.
25.1. EFI Managed Network Protocol 971Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 25.5 – continued from previous page
•Token isNULL .
•Token.Event isNULL .
•Token.TxData is NULL .
•Token.TxData.DestinationAddress is not NULL
and Token.TxData.HeaderLength is zero.
•Token.TxData.FragmentCount is zero.
•(Token.TxData.HeaderLength + Token.TxData.DataLength) is not equal
to the sum of the Token.TxDat a.FragmentTable[].FragmentLength ﬁelds.
• One or more of the
Token.TxDat a.FragmentTable[].FragmentLength ﬁelds is zero.
Token.TxData.Frag mentTable[].FragmentBufferﬁelds isNULL .
•Token.TxData.DataLength is greater than MTU
EFI_ACCESS_DENIED The transmit completion token is already in the transmit queue.
EFI_OUT_OF_RESOURCES The transmit data could not be queued due to a lack of system resources
(usually memory).
An unexpected system or network error occurred.
EFI_NOT_READY The transmit request could not be queued because the transmit queue is full.
EFI_NO_MEDIA There was a media error.
25.1.8 EFI_MANAGED_NETWORK_PROTOCOL.Receive()
Summary
Places an asynchronous receiving request into the receiving queue.
Prototype
typedef
(EFIAPI *EFI_MANAGED_NETWORK_RECEIVE) (
);
Token
Pointer to a token associated with the receive data descriptor. Type
EFI_MANAGED_NETWORK_COMPLETION_TOKEN is deﬁned in
EFI_MANAGED_NETWORK_PROTOCOL.Transmit() .
25.1. EFI Managed Network Protocol 972Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheReceive() function places a completion token into the receive packet queue. This function is always asynchronous.
The caller must ﬁll in the Token.Event ﬁeld in the completion token, and this ﬁeld cannot be NULL . When the receive
operation completes, the MNP updates the Token.Status andToken.RxData ﬁelds and the Token.Event is signaled.
EFI_SUCCESS The receive completion token was cached.
•Token.Event isNULL

EFI_DEVICE_ERROR An unexpected system or network error occurred. The MNP child driver
instance has been reset to startup defaults.
EFI_ACCESS_DENIED The receive completion token was already in the receive queue.
EFI_NOT_READY The receive request could not be queued because the receive queue is full.
25.1.9 EFI_MANAGED_NETWORK_PROTOCOL.Cancel()
Summary
Aborts an asynchronous transmit or receive request.
Prototype
typedef
(EFIAPI *EFI_MANAGED_NETWORK_CANCEL)(
IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token OPTIONAL
);
Token
Pointer to a token that has been issued by
EFI_MANAGED_NETWORK_PROTOCOL.Transmit() or
EFI_MANAGED_NETWORK_PROTOCOL.Receive() . IfNULL , all pending tokens are aborted. Type
TheCancel() function is used to abort a pending transmit or receive request. If the token is in the transmit or receive
request queues, after calling this function, Token.Status will be set to EFI_ABORTED and then Token.Event will be
signaled. If the token is not in one of the queues, which usually means that the asynchronous operation has completed,
this function will not signal the token and EFI_NOT_FOUND is returned.
25.1. EFI Managed Network Protocol 973Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The asynchronous I/O request was aborted and Token.Event was signaled.
When Token isNULL , all pending requests were aborted and their events
were signaled.
EFI_NOT_FOUND When Token is not NULL , the asynchronous I/O request was not found in
the transmit or receive queue. It has either completed or was not issued by
Transmit() andReceive() .
25.1.10 EFI_MANAGED_NETWORK_PROTOCOL.Poll()
Summary
Polls for incoming data packets and processes outgoing data packets.
Prototype
typedef
(EFIAPI *EFI_MANAGED_NETWORK_POLL) (
IN EFI_MANAGED_NETWORK_PROTOCOL *This
);
ThePoll() function can be used by network drivers and applications to increase the rate that data packets are moved
between the communications device and the transmit and receive queues.
Normally, a periodic timer event internally calls the Poll() function. But, in some systems, the periodic timer event may
not call Poll() fast enough to transmit and/or receive all data packets without missing packets. Drivers and applications
that are experiencing packet loss should try calling the Poll() function more often.
EFI_SUCCESS Incoming or outgoing data was processed.
EFI_NOT_READY No incoming or outgoing data was processed. Consider increasing the
polling rate.
EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. Consider in-
creasing the polling rate.
25.1. EFI Managed Network Protocol 974CHAPTER
TWENTYSIX
NETWORK PROTOCOLS — BLUETOOTH
26.1 EFI Bluetooth Host Controller Protocol
26.1.1 EFI_BLUETOOTH_HC_PROTOCOL
Summary
This protocol abstracts the Bluetooth host controller layer.message transmit and receive.
GUID
#define EFI_BLUETOOTH_HC_PROTOCOL_GUID \
{ 0xb3930571, 0xbeba, 0x4fc5,
{ 0x92, 0x3, 0x94, 0x27, 0x24, 0x2e, 0x6a, 0x43 }}
typedef struct _EFI_BLUETOOTH_HC_PROTOCOL {
EFI_BLUETOOTH_HC_SEND_COMMAND SendCommand;
EFI_BLUETOOTH_HC_RECEIVE_EVENT ReceiveEvent;
EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT AsyncReceiveEvent;
EFI_BLUETOOTH_HC_SEND_ACL_DATA SendACLData;
EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA ReceiveACLData;
EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA AsyncReceiveACLData;
EFI_BLUETOOTH_HC_SEND_SCO_DATA SendSCOData;
EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA ReceiveSCOData;
EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA AsyncReceiveSCOData;
} EFI_BLUETOOTH_HC_PROTOCOL;
SendCommand Send HCI command packet. See the SendCommand() function description.
ReceiveEvent Receive HCI event packets. See the ReceiveEvent() function description.
AsyncReceiveEvent Non-blocking receive HCI event packets. See the AsyncReceiveEvent() function description.
SendACLData Send HCI ACL (asynchronous connection-oriented) data packets. See the SendACLData() function
ReceiveACLData Receive HCI ACL data packets. See the ReceiveACLData() function description.
AsyncReceiveACLData Non-blocking receive HCI ACL data packets. See the AsyncReceiveACLData() function
SendSCOData Send HCI synchronous (SCO and eSCO) data packets. See the SendSCOData() function description.
975Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ReceiveSCOData Receive HCI synchronous data packets. See the ReceiveSCOData() function description.
AsyncReceiveSCOData Non-blocking receive HCI synchronous data packets. See the AsyncReceiveSCOData()
The EFI_BLUETOOTH_HC_PROTOCOL is used to transmit or receive HCI layer data packets. For detail of
different HCI packet (command, event, ACL, SCO), please refer to Bluetooth speciﬁcation.
26.1.2 BLUETOOTH_HC_PROTOCOL.SendCommand()
Summary
Send HCI command packet.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_SEND_COMMAND)(
IN EFI_BLUETOOTH_HC_PROTOCOL *This,
IN UINTN Timeout
);
This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
BufferSize On input, indicates the size, in bytes, of the data buffer speciﬁed by Buffer . On output, indicates the
Buffer A pointer to the buffer of data that will be transmitted to Bluetooth host controller.
is 0, then the caller must wait for the function to be completed until EFI_SUCCESS orEFI_DEVICE_ERROR
The SendCommand() function sends HCI command packet. Buffer holds the whole HCI command packet, including
OpCode, OCF, OGF, parameter length, and parameters. When this function is returned, it just means the HCI command
packet is sent, it does not mean the command is success or complete. Caller might need to wait a command status
event to know the command status, or wait a command complete event to know if the command is completed. (see in
Bluetooth speciﬁcation, HCI Command Packet for more detail).
EFI_SUCCESS The HCI command packet is sent successfully.
BufferSize is NULL.
*BufferSize is 0.
Buffer is NULL.
EFI_TIMEOUT Sending HCI command packet fail due to timeout.
26.1. EFI Bluetooth Host Controller Protocol 976Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 26.1 – continued from previous page
EFI_DEVICE_ERROR Sending HCI command packet fail due to host controller or device error.
26.1.3 BLUETOOTH_HC_PROTOCOL.ReceiveEvent()
Summary
Receive HCI event packet.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_EVENT)(
);
Buffer A pointer to the buffer of data that will be received from Bluetooth host controller.
The ReceiveEvent() function receives HCI event packet. Buffer holds the whole HCI event packet, including Event-
Code , parameter length, and parameters. (See in Bluetooth speciﬁcation, HCI Event Packet for more detail.)
EFI_SUCCESS The HCI event packet is received successfully.
•BufferSize is NULL.
• *BufferSize is 0.
•Buffer is NULL.
EFI_TIMEOUT Receiving HCI event packet fail due to timeout.
EFI_DEVICE_ERROR Receiving HCI event packet fail due to host controller or device error.
26.1. EFI Bluetooth Host Controller Protocol 977Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.1.4 BLUETOOTH_HC_PROTOCOL.AsyncReceiveEvent()
Summary
Receive HCI event packet in non-blocking way.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT) (

Summary
Prototype
typedef
IN UINTN PollingInterval,
IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback,
);
IsNewTransfer IfTRUE, a new transfer will be submitted. If FALSE, the request is deleted.
PollingInterval Indicates the periodic rate, in milliseconds, that the transfer is to be executed.
DataLength Speciﬁes the length, in bytes, of the data to be received.
Callback The callback function. This function is called if the asynchronous transfer is completed.
Context Data passed into Callback function. This is optional parameter and may be NULL .
The AsyncReceiveEvent() function receives HCI event packet in non-blocking way. Data inCallback function holds
the whole HCI event packet, including EventCode , parameter length, and parameters. (See in Bluetooth speciﬁcation,
HCI Event Packet for more detail.)
typedef
(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK) (
);
Data Data received via asynchronous transfer.
DataLength The length of Data in bytes, received via asynchronous transfer.
Context Context passed from asynchronous transfer request.
EFI_SUCCESS The HCI asynchronous receive request is submitted successfully.
26.1. EFI Bluetooth Host Controller Protocol 978Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 26.3 – continued from previous page
• IfIsNewTransfer isTRUE, and an asynchronous receive request already
exists.
26.1.5 BLUETOOTH_HC_PROTOCOL.SendACLData()
Summary
Send HCI ACL data packet.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_SEND_ACL_DATA)(
);
The SendACLData() function sends HCI ACL data packet. Buffer holds the whole HCI ACL data packet, including
Handle, PB ﬂag, BC ﬂag, data length, and data. (See in Bluetooth speciﬁcation, HCI ACL Data Packet for more
detail.)
The SendACLData() function andReceiveACLData() function just send and receive data payload from application
layer. In order to protect the payload data, the Bluetooth bus is required to call HCI_Set_Connection_Encryption
command to enable hardware based encryption after authentication completed, according to pairing mode and host
capability.
EFI_SUCCESS The HCI ACL data packet is sent successfully.
26.1. EFI Bluetooth Host Controller Protocol 979Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 26.4 – continued from previous page
EFI_TIMEOUT Sending HCI ACL data packet fail due to timeout.
EFI_DEVICE_ERROR Sending HCI ACL data packet fail due to host controller or device error.
26.1.6 BLUETOOTH_HC_PROTOCOL.ReceiveACLData()
Summary
Receive HCI ACL data packet.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA)(
);
The ReceiveACLData() function receives HCI ACL data packet. Buffer holds the whole HCI ACL data packet,
including Handle, PB ﬂag, BC ﬂag, data length, and data. (See in Bluetooth speciﬁcation, HCI ACL Data Packet for
more detail.)
EFI_SUCCESS The HCI ACL data packet is received successfully.
EFI_TIMEOUT Receiving HCI ACL data packet fail due to timeout.
26.1. EFI Bluetooth Host Controller Protocol 980Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 26.5 – continued from previous page
EFI_DEVICE_ERROR Receiving HCI ACL data packet fail due to host controller or device error.
26.1.7 BLUETOOTH_HC_PROTOCOL.AsyncReceiveACLData()
Summary
Receive HCI ACL data packet in non-blocking way.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA) (
);
IsNewTransfer
IfTRUE, a new transfer will be submitted.
IfFALSE, the request is deleted.
Context Data passed into Callback function. This is optional parameter and may be NULL.
The AsyncReceiveACLData() function receives HCI ACL data packet in non-blocking way. Data inCallback holds
the whole HCI ACL data packet, including Handle, PB ﬂag, BC ﬂag, data length, and data. (See in Bluetooth speciﬁ-
cation, HCI ACL Data Packet for more detail.)
exists.
26.1. EFI Bluetooth Host Controller Protocol 981Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.1.8 BLUETOOTH_HC_PROTOCOL.SendSCOData()
Summary
Send HCI SCO data packet.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_SEND_SCO_DATA)(
);
The SendSCOData() function sends HCI SCO data packet. Buffer holds the whole HCI SCO data packet, including
ConnectionHandle ,PacketStatus ﬂag, data length, and data. (See in Bluetooth speciﬁcation, HCI Synchronous Data
Packet for more detail.)
EFI_SUCCESS The HCI SCO data packet is sent successfully.
EFI_UNSUPPORTED The implementation does not support HCI SCO transfer.
EFI_TIMEOUT Sending HCI SCO data packet fail due to timeout.
EFI_DEVICE_ERROR Sending HCI SCO data packet fail due to host controller or device error.
26.1. EFI Bluetooth Host Controller Protocol 982Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.1.9 BLUETOOTH_HC_PROTOCOL.ReceiveSCOData()
Summary
Receive HCI SCO data packet.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA)(
);

Summary
Prototype
typedef
);
The ReceiveSCOData() function receives HCI SCO data packet. Buffer holds the whole HCI SCO data packet, in-
cluding ConnectionHandle, PacketStatus ﬂag, data length, and data. (See in Bluetooth speciﬁcation, HCI Synchronous
Data Packet for more detail.)
EFI_SUCCESS The HCI SCO data packet is received successfully.
EFI_TIMEOUT Receiving HCI SCO data packet fail due to timeout.
EFI_DEVICE_ERROR Receiving HCI SCO data packet fail due to host controller or device error.
26.1. EFI Bluetooth Host Controller Protocol 983Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.1.10 BLUETOOTH_HC_PROTOCOL.AsyncReceiveSCOData()
Summary
Receive HCI SCO data packet in non-blocking way.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA) (
);
The AsyncReceiveSCOData() function receives HCI SCO data packet in non-blocking way. Data inCallback holds
the whole HCI SCO data packet, including ConnectionHandle ,PacketStatus ﬂag, data length, and data. (See in
Bluetooth speciﬁcation, HCI SCO Data Packet for more detail.)
exists.
26.1. EFI Bluetooth Host Controller Protocol 984Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.2 EFI Bluetooth Bus Protocol
26.2.1 EFI_BLUETOOTH_IO_SERVICE_BINDING_PROTOCOL
Summary
The EFI Bluetooth IO Service Binding Protocol is used to locate EFI Bluetooth IO Protocol drivers to create and
destroy child of the driver to communicate with other Bluetooth device by using Bluetooth IO protocol.
GUID
#define EFI_BLUETOOTH_IO_SERVICE_BINDING_PROTOCOL_GUID \
{ 0x388278d3, 0x7b85, 0x42f0,\
{ 0xab, 0xa9, 0xfb, 0x4b, 0xfd, 0x69, 0xf5, 0xab }
The Bluetooth IO consumer need locate EFI_BLUETOOTH_IO_SERVICE_BINDING_PROTOCOL and
call CreateChild() to create a new child of EFI_BLUETOOTH_IO_PROTOCOL instance. Then use
EFI_BLUETOOTH_IO_PROTOCOL for Bluetooth communication. After use, the Bluetooth IO consumer
need call DestroyChild() to destroy it.
26.2.2 EFI_BLUETOOTH_IO_PROTOCOL
Summary
This protocol provides service for Bluetooth L2CAP (Logical Link Control and Adaptation Protocol) and SDP (Service
Discovery Protocol).
GUID
#define EFI_BLUETOOTH_IO_PROTOCOL_GUID \
{ 0x467313de, 0x4e30, 0x43f1,\
{ 0x94, 0x3e, 0x32, 0x3f, 0x89, 0x84, 0x5d, 0xb5 }}
typedef struct _EFI_BLUETOOTH_IO_PROTOCOL {
EFI_BLUETOOTH_IO_GET_DEVICE_INFO GetDeviceInfo;
EFI_BLUETOOTH_IO_GET_SDP_INFO GetSdpInfo;
EFI_BLUETOOTH_IO_L2CAP_RAW_SEND L2CapRawSend;
EFI_BLUETOOTH_IO_L2CAP_RAW_RECEIVE L2CapRawReceive;
EFI_BLUETOOTH_IO_L2CAP_RAW_ASYNC_RECEIVE\ L2CapRawAsyncReceive;
EFI_BLUETOOTH_IO_L2CAP_SEND L2CapSend;
EFI_BLUETOOTH_IO_L2CAP_RECEIVE L2CapReceive;
EFI_BLUETOOTH_IO_L2CAP_ASYNC_RECEIVE L2CapAsyncReceive;
EFI_BLUETOOTH_IO_L2CAP_CONNECT L2CapConnect;
EFI_BLUETOOTH_IO_L2CAP_DISCONNECT L2CapDisconnect;
EFI_BLUETOOTH_IO_L2CAP_REGISTER_SERVICE\ L2CapRegisterService;
}
EFI_BLUETOOTH_IO_PROTOCOL;
GetDeviceInfo Get Bluetooth device Information. See theGetDeviceInfo()* function description.
GetSdpInfo Get Bluetooth device SDP information. See the GetSdpInfo() function description.
26.2. EFI Bluetooth Bus Protocol 985Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
L2CapRawSend Send L2CAP message (including L2CAP header). See the L2CapRawSend() function description.
L2CapRawReceive Receive L2CAP message (including L2CAP header). See the L2CapRawReceive() function de-
L2CapRawAsyncReceive Non-blocking receive L2CAP message (including L2CAP header). See the
L2CapRawAsyncReceive() function description.
L2CapSend Send L2CAP message (excluding L2CAP header) to a speciﬁc channel. See the L2CapSend() function
L2CapReceive Receive L2CAP message (excluding L2CAP header) from a speciﬁc channel. See the
L2CapRawReceive() function description.
L2CapAsyncReceive Non-blocking receive L2CAP message (excluding L2CAP header) from a speciﬁc channel.
See the L2CapRawAsyncReceive() function description.
L2CapConnect Do L2CAP connection. See the L2CapConnect() function description.
L2CapDisconnect Do L2CAP disconnection. See the L2CapDisconnect() function description.
L2CapRegisterService Register L2CAP callback function for special channel. See the L2CapRegisterService() func-
The EFI_BLUETOOTH_IO_PROTOCOL provides services in L2CAP protocol and SDP protocol. For detail of
L2CAP packet format, and SDP service, please refer to Bluetooth speciﬁcation.
26.2.3 BLUETOOTH_IO_PROTOCOL.GetDeviceInfo
Summary
Get Bluetooth device information.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_GET_DEVICE_INFO)(
IN EFI_BLUETOOTH_IO_PROTOCOL *This,
OUT UINTN *DeviceInfoSize,
OUT VOID **DeviceInfo
);
This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
DeviceInfoSize A pointer to the size, in bytes, of the DeviceInfo buffer.
DeviceInfo A pointer to a callee allocated buffer that returns Bluetooth device information. Callee allocates this buffer
by using EFI Boot Service AllocatePool() .
The GetDeviceInfo() function returns Bluetooth device information. The size of DeviceInfo structure should never
be assumed and the value of DeviceInfoSize is the only valid way to know the size of DeviceInfo .
26.2. EFI Bluetooth Bus Protocol 986Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BLUETOOTH_ADDRESS BD_ADDR;
UINT8 PageScanRepetitionMode;
BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice;
UINT16 ClockOffset;
UINT8 RSSI;
UINT8 ExtendedInquiryResponse [240];
} EFI_BLUETOOTH_DEVICE_INFO;
Version The version of the structure. A value of zero represents the EFI_BLUETOOTH_DEVICE_INFO structure as
deﬁned here. Future version of this speciﬁcation may extend this data structure in a backward compatible way
and increase the value of Version .
BD_ADDR 48bit Bluetooth device address.
PageScanRepetitionMode* Bluetooth PageScanRepetitionMode. See Bluetooth speciﬁcation for detail.
ClassOfDevice Bluetooth ClassOfDevice. See Bluetooth speciﬁcation for detail.
ClockOffset Bluetooth CloseOffset. See Bluetooth speciﬁcation for detail.
RSSI Bluetooth RSSI. See Bluetooth speciﬁcation for detail.
ExtendedInquiryResponse Bluetooth ExtendedInquiryResponse. See Bluetooth speciﬁcation for detail.
UINT8 Address [6];
} BLUETOOTH_ADDRESS;
UINT8 FormatType:2;
UINT8 MinorDeviceClass:6;
UINT16 MajorDeviceClass:5;
UINT16 MajorServiceClass:11;
} BLUETOOTH_CLASS_OF_DEVICE;
EFI_SUCCESS The Bluetooth device information is returned successfully.
EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth device informa-
tion.
26.2.4 BLUETOOTH_IO_PROTOCOL.GetSdpInfo
Summary
Get Bluetooth SDP information.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_GET_SDP_INFO)(
OUT UINTN *SdpInfoSize,
OUT VOID **SdpInfo
);
26.2. EFI Bluetooth Bus Protocol 987Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SdpInfoSize A pointer to the size, in bytes, of the SdpInfo buffer.
SdpInfo A pointer to a callee allocated buffer that returns Bluetooth SDP information. Callee allocates this buffer by
using EFI Boot Service AllocatePool() .
The GetSdpInfo() function returns Bluetooth SDP information. The size of SdpInfo structure should never be as-
sumed and the value of SdpInfoSize is the only valid way to know the size of SdpInfo .
EFI_SUCCESS The Bluetooth SDP information is returned successfully.

tion.
Summary
Prototype
typedef
);
EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth SDP information.
26.2.5 BLUETOOTH_IO_PROTOCOL.L2CapRawSend
Summary
Send L2CAP message (including L2CAP header).
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_SEND)(
);
Buffer A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer.
EFI iSCSI Initiator Name Protocol sends L2CAP layer message (including L2CAP header). Buffer holds the whole
L2CAP message, including Length, ChannelID, and information payload. (See the Bluetooth speciﬁcation, L2CAP
Data Packet Format for more details.)
EFI_SUCCESS The L2CAP message is sent successfully.
26.2. EFI Bluetooth Bus Protocol 988Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 26.12 – continued from previous page
One or more of the following conditions is TRUE:
• BufferSize is NULL.
• BufferSize is 0.
• Buffer is NULL.
EFI_TIMEOUT Sending L2CAP message fail due to timeout.
EFI_DEVICE_ERROR Sending L2CAP message fail due to host controller or device error.
26.2.6 BLUETOOTH_IO_PROTOCOL.L2CapRawReceive
Summary
Receive L2CAP message (including L2CAP header).
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_RECEIVE)(
);
Buffer A pointer to the buffer of data that will be received from Bluetooth L2CAP layer.
The L2CapRawReceive() function receives L2CAP layer message (including L2CAP header). Buffer holds the
whole L2CAP message, including Length, ChannelID, and information payload. (See in Bluetooth speciﬁcation,
L2CAP Data Packet Format for more detail.)
EFI_SUCCESS The L2CAP message is received successfully.
EFI_TIMEOUT Receiving L2CAP message fail due to timeout.
26.2. EFI Bluetooth Bus Protocol 989Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 26.13 – continued from previous page
EFI_DEVICE_ERROR Receiving L2CAP message fail due to host controller or device error.
26.2.7 BLUETOOTH_IO_PROTOCOL.L2CapRawAsyncReceive
Summary
Receive L2CAP message (including L2CAP header) in non-blocking way.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_ASYNC_RECEIVE)(
IN EFI_BLUETOOTH_IO_ASYNC_FUNC_CALLBACK Callback,
);
The L2CapRawAsyncReceive() function receives L2CAP layer message (including L2CAP header) in non-blocking
way. Data inCallback function holds the whole L2CAP message, including Length, ChannelID, and information
payload. (See in Bluetooth speciﬁcation, L2CAP Data Packet Format for more detail.)
typedef
(EFIAPI *EFI_BLUETOOTH_IO_ASYNC_FUNC_CALLBACK) (
IN UINT16 ChannelID,
);
ChannelID Bluetooth L2CAP message channel ID.
26.2. EFI Bluetooth Bus Protocol 990Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The L2CAP asynchronous receive request is submitted successfully.
exists.
26.2.8 BLUETOOTH_IO_PROTOCOL.L2CapSend
Summary
Send L2CAP message (excluding L2CAP header) to a speciﬁc channel.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_SEND)(
);
Handle A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to send.
The L2CapSend() function sends L2CAP layer message (excluding L2CAP header) to Bluetooth channel indicated
byHandle .Buffer only holds information payload. (See in Bluetooth speciﬁcation, L2CAP Data Packet Format for
EFI_NOT_FOUND Handle is invalid or not found.
26.2. EFI Bluetooth Bus Protocol 991Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 26.15 – continued from previous page
26.2.9 BLUETOOTH_IO_PROTOCOL.L2CapReceive
Summary
Receive L2CAP message (excluding L2CAP header) from a speciﬁc channel.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RECEIVE)(
OUT VOID **Buffer,
);
Handle A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to receive.
BufferSize Indicates the size, in bytes, of the data buffer speciﬁed by Buffer .
Buffer A pointer to the buffer of data that will be received from Bluetooth L2CAP layer. Callee allocates this buffer
The L2CapReceive() function receives L2CAP layer message (excluding L2CAP header) from Bluetooth channel
indicated by Handle .Buffer only holds information payload. (See in Bluetooth speciﬁcation, L2CAP Data Packet
Format for more detail.)
26.2. EFI Bluetooth Bus Protocol 992Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 26.16 – continued from previous page
26.2.10 BLUETOOTH_IO_PROTOCOL.L2CapAsyncReceive
Summary
Receive L2CAP message (including L2CAP header) in non-blocking way from a speciﬁc channel.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_ASYNC_RECEIVE)(

Summary
Prototype
typedef
IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK Callback,
The L2CapAsyncReceive() function receives L2CAP layer message (excluding L2CAP header) in non-blocking
way from Bluetooth channel indicated by Handle .Data inCallback function only holds information payload. (See in
Bluetooth speciﬁcation, L2CAP Data Packet Format for more detail.)
typedef
(EFIAPI *EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK) (
);
26.2. EFI Bluetooth Bus Protocol 993Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• If an asynchronous receive request already exists on same Handle .
26.2.11 BLUETOOTH_IO_PROTOCOL.L2CapConnect
Summary
Do L2CAP connection.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_CONNECT)(
OUT EFI_HANDLE *Handle,
IN UINT16 Psm,
IN UINT16 Mtu,
);
Handle A handle to indicate this L2CAP connection.
Psm Bluetooth PSM. See Bluetooth speciﬁcation for detail.
Mtu Bluetooth MTU. See Bluetooth speciﬁcation for detail.
Callback The callback function. This function is called whenever there is message received in this channel.
The L2CapConnect() function does all necessary steps for Bluetooth L2CAP layer connection in blocking way. It
might take long time. Once this function is returned Handle is created to indicate the connection.
EFI_SUCCESS The Bluetooth L2CAP layer connection is created successfully.
•Handle is NULL.
EFI_DEVICE_ERROR A hardware error occurred trying to do Bluetooth L2CAP connection.
26.2. EFI Bluetooth Bus Protocol 994Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.2.12 BLUETOOTH_IO_PROTOCOL.L2CapDisconnect
Summary
Do L2CAP disconnection.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_DISCONNECT)(
IN EFI_HANDLE Handle
);
The L2CapDisconnect() function does all necessary steps for Bluetooth L2CAP layer disconnection in blocking way.
It might take long time. Once this function is returned Handle is no longer valid.
EFI_SUCCESS The Bluetooth L2CAP layer disconnection is created successfully.
EFI_DEVICE_ERROR A hardware error occurred trying to do Bluetooth L2CAP disconnection.
26.2.13 BLUETOOTH_IO_PROTOCOL.L2CapRegisterService
Summary
Register L2CAP callback function for special channel.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_REGISTER_SERVICE)(
);
Handle
26.2. EFI Bluetooth Bus Protocol 995Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Callback The callback function. This function is called whenever there is message received in this channel. NULL
means unregister.
The L2CapRegisterService() function registers L2CAP callback function for a special channel. Once this function
is returned Handle is created to indicate the connection.
EFI_SUCCESS The Bluetooth L2CAP callback function is registered successfully.
EFI_ALREADY_STARTED The callback function already exists when register.
EFI_NOT_FOUND The callback function does not exist when unregister.
26.3 EFI Bluetooth Conﬁguration Protocol
26.3.1 EFI_BLUETOOTH_CONFIG_PROTOCOL
Summary
This protocol abstracts user interface conﬁguration for Bluetooth device.
GUID
#define EFI_BLUETOOTH_CONFIG_PROTOCOL_GUID \
{ 0x62960cf3, 0x40ff, 0x4263,\
{ 0xa7, 0x7c, 0xdf, 0xde, 0xbd, 0x19, 0x1b, 0x4b }}
typedef struct _EFI_BLUETOOTH_CONFIG_PROTOCOL {
EFI_BLUETOOTH_CONFIG_INIT Init;
EFI_BLUETOOTH_CONFIG_SCAN Scan;
EFI_BLUETOOTH_CONFIG_CONNECT Connect;
EFI_BLUETOOTH_CONFIG_DISCONNECT Disconnect;
EFI_BLUETOOTH_CONFIG_GET_DATA GetData;
EFI_BLUETOOTH_CONFIG_SET_DATA SetData;
EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA GetRemoteData;
EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK RegisterPinCallback;
EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK RegisterGetLinkKeyCallback;
EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK RegisterSetLinkKeyCallback;
EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK
˓→RegisterLinkConnectCompleteCallback;
} EFI_BLUETOOTH_CONFIG_PROTOCOL;
Init Initialize Bluetooth host controller and local device. See the Init() function description.
Scan Scan Bluetooth device. See the Scan() function description.
Connect Connect one Bluetooth device. See the Connect() function description.
Disconnect Disconnect one Bluetooth device. See the Disconnect() function description.
GetData Get Bluetooth conﬁguration data. See the GetData() function description.
26.3. EFI Bluetooth Conﬁguration Protocol 996Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SetData Set Bluetooth conﬁguration data. See the SetData() function description.
GetRemoteData Get remote Bluetooth device data. See the GetRemoteData() function description.
RegisterPinCallback Register PIN callback function. See the RegisterPinCallback() function description.
RegisterGetLinkKeyCallback Register get link key callback function. See the RegisterGetLinkKeyCallback() func-
RegisterSetLinkKeyCallback Register set link key callback function. See the RegisterSetLinkKeyCallback() func-
RegisterLinkConnectCompleteCallback Register link connect complete callback function. See the Register-
LinkConnectCompleteCallback() function description.
The EFI_BLUETOOTH_CONFIG_PROTOCOL abstracts the Bluetooth conﬁguration. User can use Bluetooth
conﬁguration to interactive with Bluetooth bus driver.
26.3.2 BLUETOOTH_CONFIG_PROTOCOL.Init
Summary
Initialize Bluetooth host controller and local device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_INIT)(
IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This
);
This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
TheInit() function initializes Bluetooth host controller and local device.
EFI_SUCCESS The Bluetooth host controller and local device is initialized successfully.
EFI_DEVICE_ERROR A hardware error occurred trying to initialize the Bluetooth host controller
and local device.
26.3.3 BLUETOOTH_CONFIG_PROTOCOL.Scan
Summary
Scan Bluetooth device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN)(
26.3. EFI Bluetooth Conﬁguration Protocol 997Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
IN BOOLEAN ReScan,
IN UINT8 ScanType,
IN EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION Callback
);
ReScan IfTRUE, a new scan request is submitted no matter there is scan result before. If FALSE and there is scan
result, the previous scan result is returned and no scan request is submitted.
ScanType Bluetooth scan type, Inquiry and/or Page. See Bluetooth speciﬁcation for detail.
Callback The callback function. This function is called if a Bluetooth device is found during scan process.
The Scan() function scans Bluetooth device. When this function is returned, it just means scan request is submitted.

);
It does not mean scan process is started or ﬁnished. Whenever there is a Bluetooth device is found, the Callback
function will be called. Callback function might be called before this function returns or after this function returns.
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION) (
IN EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION *CallbackInfo
);
Context Context passed from scan request.
CallbackInfo Data related to scan result. NULL CallbackInfo means scan complete.
typedef
BLUETOOTH_ADDRESS BDAddr;
UINT8 RemoteDeviceState;
UINT8 RemoteDeviceName[BLUETOOTH_HCI_COMMAND_LOCAL_
˓→READABLE_NAME_MAX_SIZE];
} EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION;
#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248
EFI_SUCCESS The Bluetooth scan request is submitted.
EFI_DEVICE_ERROR A hardware error occurred trying to scan the Bluetooth device.
26.3. EFI Bluetooth Conﬁguration Protocol 998Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.3.4 BLUETOOTH_CONFIG_PROTOCOL.Connect
Summary
Connect a Bluetooth device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_CONNECT)(
IN BLUETOOTH_ADDRESS *BD_ADDR
);
BD_ADDR The address of Bluetooth device to be connected.
The Connect() function connects a Bluetooth device. When this function is returned successfully, a new
EFI_BLUETOOTH_IO_PROTOCOL is created.
EFI_SUCCESS The Bluetooth device is connected successfully.
EFI_ALREADY_STARTED The Bluetooth device is already connected.
EFI_NOT_FOUND The Bluetooth device is not found.
EFI_DEVICE_ERROR A hardware error occurred trying to connect the Bluetooth device.
26.3.5 BLUETOOTH_CONFIG_PROTOCOL.Disconnect
Summary
Disconnect a Bluetooth device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_DISCONNECT)(
IN BLUETOOTH_ADDRESS *BD_ADDR,
IN UINT8 *Reason
);
Reason Bluetooth disconnect reason. See Bluetooth speciﬁcation for detail.
The Disconnect() function disconnects a Bluetooth device. When this function is returned successfully, the
EFI_BLUETOOTH_IO_PROTOCOL associated with this device is destroyed and all services associated are stopped.
26.3. EFI Bluetooth Conﬁguration Protocol 999Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The Bluetooth device is disconnected successfully.
EFI_NOT_STARTED The Bluetooth device is not connected.
EFI_DEVICE_ERROR A hardware error occurred trying to disconnect the Bluetooth device.
26.3.6 BLUETOOTH_CONFIG_PROTOCOL.GetData
Summary
Get Bluetooth conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_GET_DATA) (
IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,
IN OUT VOID *Data
);
DataType Conﬁguration data type.
DataSize On input, indicates the size, in bytes, of the data buffer speciﬁed by Data . On output, indicates the amount
of data actually returned.
Data A pointer to the buffer of data that will be returned.
The GetData() function returns Bluetooth conﬁguration data. For remote Bluetooth device conﬁguration data, please
useGetRemoteData() function with valid BD_ADDR.
EfiBluetoothConfigDataTypeDeviceName, / *Relevant forLE*/
EfiBluetoothConfigDataTypeClassOfDevice,
EfiBluetoothConfigDataTypeRemoteDeviceState, / *Relevant forLE*/
EfiBluetoothConfigDataTypeSdpInfo,
EfiBluetoothConfigDataTypeBDADDR, / *Relevant forLE*/
EfiBluetoothConfigDataTypeDiscoverable, / *Relevant forLE*/
EfiBluetoothConfigDataTypeControllerStoredPairedDeviceList,
EfiBluetoothConfigDataTypeAvailableDeviceList,
EfiBluetoothConfigDataTypeRandomAddress, / *Relevant forLE*/
EfiBluetoothConfigDataTypeRSSI, / *Relevant forLE*/
EfiBluetoothConfigDataTypeAdvertisementData, / *Relevant forLE*/
EfiBluetoothConfigDataTypeIoCapability, / *Relevant forLE*/
EfiBluetoothConfigDataTypeOOBDataFlag, / *Relevant forLE*/
EfiBluetoothConfigDataTypeKeyType, / *Relevant forLE*/
EfiBluetoothConfigDataTypeEncKeySize, / *Relevant forLE*/
26.3. EFI Bluetooth Conﬁguration Protocol 1000Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EfiBluetoothConfigDataTypeMax,
} EFI_BLUETOOTH_CONFIG_DATA_TYPE;
EﬁBluetoothConﬁgDataTypeAdvertisementDataReport Advertisement report. Data structure is UNIT8[] .
EﬁBluetoothConﬁgDataTypeKeyType KeyType of Authentication Requirements ﬂag of local device as UINT8, in-
dicating requested security properties. See Bluetooth speciﬁcation 3.H.3.5.1. BIT0: MITM, BIT1: SC.
EﬁBluetoothConﬁgDataTypeDeviceName Local/Remote Bluetooth device name. Data structure is zero terminated
CHAR8[] .
EﬁBluetoothConﬁgDataTypeClassOfDevice nLocal/Remote Bluetooth device ClassOfDevice. Data structure is
BLUETOOTH_CLASS_OF_DEVICE .
EﬁBluetoothConﬁgDataTypeRemoteDeviceState Remove Bluetooth device state. Data structure is
EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE .
EﬁBluetoothConﬁgDataTypeSdpInfo Local/Remote Bluetooth device SDP information. Data structure is UINT8[] .
EﬁBluetoothConﬁgDataTypeBDADDR Local Bluetooth device address. Data structure is BLUE-
TOOTH_ADDRESS .
EﬁBluetoothConﬁgDataTypeDiscoverable Local Bluetooth discoverable state. Data structure is UINT8 . (Page scan
and/or Inquiry scan)
EﬁBluetoothConﬁgDataTypeControllerStoredPairedDeviceList Local Bluetooth controller stored paired device
list. Data structure is BLUETOOTH_ADDRESS[] .
EﬁBluetoothConﬁgDataTypeAvailableDeviceList Local available device list. Data structure is BLUE-
TOOTH_ADDRESS[] .
typedef EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE UINT32;
#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_CONNECTED 0x1
#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_PAIRED 0x2
#define BLUETOOTH_HCI_LINK_KEY_SIZE 16
EFI_SUCCESS The Bluetooth conﬁguration data is returned successfully.
• DataSize is NULL.
• * DataSize is not 0 and Data is NULL
EFI_UNSUPPORTED The DataType is unsupported.
EFI_NOT_FOUND The DataType is not found.
EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer. DataSize has been updated with
26.3. EFI Bluetooth Conﬁguration Protocol 1001Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.3.7 BLUETOOTH_CONFIG_PROTOCOL.SetData
Summary
Set Bluetooth conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_SET_DATA) (
);
DataSize Indicates the size, in bytes, of the data buffer speciﬁed by Data .
Data A pointer to the buffer of data that will be set.
The SetData() function sets local Bluetooth device conﬁguration data. Not all DataType can be set.
EFI_SUCCESS The Bluetooth conﬁguration data is set successfully.
•DataSize is 0.
•Data is NULL.
EFI_UNSUPPORTED TheDataType is unsupported.
EFI_WRITE_PROTECTED Cannot set conﬁguration data.
26.3.8 BLUETOOTH_CONFIG_PROTOCOL.GetRemoteData
Summary
Get remove Bluetooth device conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA) (
IN BLUETOOTH_ADDRESS *BDAddr,
);
26.3. EFI Bluetooth Conﬁguration Protocol 1002Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BDAddr Remote Bluetooth device address.
The GetRemoteData() function returns remote Bluetooth device conﬁguration data.
EFI_SUCCESS The remote Bluetooth device conﬁguration data is returned successfully.

Prototype
typedef
);
26.3.9 BLUETOOTH_CONFIG_PROTOCOL.RegisterPinCallback
Summary
Register PIN callback function.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK) (
IN EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK_FUNCTION *Callback,
);
Callback The callback function. NULL means unregister.
The RegisterPinCallback() function registers Bluetooth PIN callback function. The Bluetooth conﬁguration driver
must call RegisterPinCallback() to register a callback function. During pairing, Bluetooth bus driver must trig-
ger this callback function, and Bluetooth conﬁguration driver must handle callback function according to Call-
26.3. EFI Bluetooth Conﬁguration Protocol 1003Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
backType during pairing. Both Legacy pairing and SSP (secure simple pairing) are required to be supported. See
EFI_BLUETOOTH_PIN_CALLBACK_TYPE below for detail of each pairing mode.
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK_FUNCTION) (
IN EFI_BLUETOOTH_CONFIG_PROTOCOL * *This,
IN VOID * *Context,
IN EFI_BLUETOOTH_PIN_CALLBACK_TYPE *CallbackType,
IN VOID * *InputBuffer,
IN UINTN *InputBufferSize,
OUT VOID ** *OutputBuffer,
OUT UINTN * *OutputBufferSize
);
Context Context passed from registration.
CallbackType* Callback type in EFI_BLUETOOTH_PIN_CALLBACK_TYPE .
InBuffer A pointer to the buffer of data that is input from callback caller.
InputBufferSize Indicates the size, in bytes, of the data buffer speciﬁed by InBuffer .
OutputBuffer A pointer to the buffer of data that will be output from callback callee. Callee allocates this buffer by
OutputBufferSize* Indicates the size, in bytes, of the data buffer speciﬁed by OutputBuffer .
EfiBluetoothCallbackTypeUserPasskeyNotification,
EfiBluetoothCallbackTypeUserConfirmationRequest,
EfiBluetoothCallbackTypeOOBDataRequest,
EfiBluetoothCallbackTypePinCodeRequest,
EfiBluetoothCallbackTypeMax,
} EFI_BLUETOOTH_PIN_CALLBACK_TYPE;
EﬁBluetoothCallbackTypeUserPasskeyNotiﬁcation For SSP - passkey entry. Input buffer is Passkey (4 bytes). No
output buffer. See Bluetooth HCI command for detail.
EﬁBluetoothCallbackTypeUserConﬁrmationRequest For SSP - just work and numeric comparison. Input buffer
is numeric value (4 bytes). Output buffer is BOOLEAN (1 byte). See Bluetooth HCI command for detail.
EﬁBluetoothCallbackTypeOOBDataRequest For SSP - OOB. See Bluetooth HCI command for detail.
EﬁBluetoothCallbackTypePinCodeRequest For legacy paring. No input buffer. Output buffer is PIN code (<= 16
bytes). See Bluetooth HCI command for detail.
EFI_SUCCESS The PIN callback function is registered successfully.
26.3. EFI Bluetooth Conﬁguration Protocol 1004Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.3.10 BLUETOOTH_CONFIG_PROTOCOL.RegisterGetLinkKeyCallback
Summary
Register get link key callback function.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK) (
IN EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION Callback,
);
The RegisterGetLinkKeyCallback() function registers Bluetooth get link key callback function. The Bluetooth
conﬁguration driver may call RegisterGetLinkKeyCallback() to register a callback function. When Bluetooth bus
driver get Link_Key_Request_Event, Bluetooth bus driver must trigger this callback function if it is registered.
Then the callback function in Bluetooth conﬁguration driver must pass link key to Bluetooth bus driver. When
the callback function is returned Bluetooth bus driver gets link key and must send HCI_Link_Key_Request_Reply
to remote device. If this GetLinkKey callback function is not registered or Bluetooth conﬁguration driver
fails to return a valid link key, the Bluetooth bus driver must send HCI_Link_Key_Request_Negative_Reply
to remote device. The original link key is passed by Bluetooth bus driver to Bluetooth conﬁguration
driver by using EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION . The Blue-
tooth conﬁguration driver need save link key to a non-volatile safe place. (See Bluetooth speciﬁcation,
HCI_Link_Key_Request_Reply)
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION)
(
OUT UINT8 LinkKey[BLUETOOTH_HCI_LINK_KEY_SIZE]
);
CallbackType Callback type in EFI_BLUETOOTH_PIN_CALLBACK_TYPE .
BDAddr A pointer to Bluetooth device address.
LinkKey A pointer to the buffer of link key.
26.3. EFI Bluetooth Conﬁguration Protocol 1005Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The link key callback function is registered successfully.
26.3.11 BLUETOOTH_CONFIG_PROTOCOL.RegisterSetLinkKeyCallback
Summary
Register set link key callback function.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK) (
IN EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION *Callback,
);
The RegisterSetLinkKeyCallback() function registers Bluetooth link key callback function. The Blue-
tooth conﬁguration driver may call RegisterSetLinkKeyCallback() to register a callback function to get link
key from Bluetooth bus driver. When Bluetooth bus driver gets Link_Key_Notiﬁcation_Event, Blue-
tooth bus driver must call this callback function if it is registered. Then the callback function in
Bluetooth conﬁguration driver must save link key to a safe place. This link key will be used by
EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION later. (See Bluetooth spec-
iﬁcation, Link_Key_Notiﬁcation_Event)
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION) (
IN UINT8 LinkKey[BLUETOOTH_HCI_LINK_KEY_SIZE]
);
26.3. EFI Bluetooth Conﬁguration Protocol 1006Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.3.12 BLUETOOTH_CONFIG_PROTOCOL.RegisterLinkConnectCompleteCallback
Summary
Register link connect complete callback function.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK) (
IN EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK_FUNCTION Callback,
);
Callback The callback function. NULL means unregister. to CallbackType deﬁned by
EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE .
The RegisterLinkConnectCompleteCallback() function registers Bluetooth link connect complete callback func-
tion. The Bluetooth Conﬁguration driver may call RegisterLinkConnectCompleteCallback() to register a callback
function. During pairing, Bluetooth bus driver must trigger this callback function to report device state, if it is regis-
tered. Then Bluetooth Conﬁguration driver will get information on device connection, according
typedef
(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK_FUNCTION) (

);
typedef
IN EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE CallbackType,
IN VOID *InputBuffer,
IN UINTN InputBufferSize
);
CallbackType Callback type in EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE .
InputBuffer A pointer to the buffer of data that is input from callback caller.
InputBufferSize Indicates the size, in bytes, of the data buffer speciﬁed by InputBuffer .
EfiBluetoothConnCallbackTypeDisconnected,
EfiBluetoothConnCallbackTypeConnected,
EfiBluetoothConnCallbackTypeAuthenticated,
26.3. EFI Bluetooth Conﬁguration Protocol 1007Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EfiBluetoothConnCallbackTypeEncrypted,
} EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE;
EﬁBluetoothConnCallbackTypeDisconnected This callback is called when Bluetooth receive Disconnec-
tion_Complete event. Input buffer is Event Parameters of Disconnection_Complete Event deﬁned in Bluetooth
EﬁBluetoothConnCallbackTypeConnected This callback is called when Bluetooth receive Connection_Complete
event. Input buffer is Event Parameters of Connection_Complete Event deﬁned in Bluetooth speciﬁcation.
EﬁBluetoothConnCallbackTypeAuthenticated This callback is called when Bluetooth receive Authentica-
tion_Complete event. Input buffer is Event Parameters of Authentication_Complete Event deﬁned in Bluetooth
EﬁBluetoothConnCallbackTypeEncrypted This callback is called when Bluetooth receive Encryption_Change
event. Input buffer is Event Parameters of Encryption_Change Event deﬁned in Bluetooth speciﬁcation.
EFI_SUCCESS The link connect complete callback function is registered successfully.
26.4 EFI Bluetooth Attribute Protocol
26.4.1 EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL
Summary
This protocol provides service for Bluetooth ATT (Attribute Protocol) and GATT (Generic Attribute Proﬁle) based
GUID
#define EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL_GUID \
{ 0x898890e9, 0x84b2, 0x4f3a, { 0x8c, 0x58, 0xd8, 0x57, 0x78, 0x13, 0xe0, 0xac }}
„ code-block:
typedef struct _EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL {
EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST SendRequest;
EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION
˓→RegisterForServerNotification;
EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO GetServiceInfo;
EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO GetDeviceInfo;
} EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL;
SendRequest Send a “REQUEST” or “COMMAND” message to remote server and receive a “RESPONSE” mes-
sage for “REQUEST” from remote server according to Bluetooth attribute protocol data unit (PDU). See the
SendRequest() function description.
RegisterForServerNotiﬁcation Register or unregister a server initiated PDU, such as “NOTIFICATION” or “IN-
DICATION” on a characteristic value on remote server. See the RegisterForServerInitiatedMessage() function
26.4. EFI Bluetooth Attribute Protocol 1008Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetServiceInfo Get discovered service data information from connected remote device. See GetServiceInfo() func-
GetDeviceInfo Get the device information. See GetDeviceInfo() function description.
The EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL provides services in ATT protocol and GATT proﬁle. For
detail of ATT protocol, and GATT proﬁle, please refer to Bluetooth speciﬁcation.
26.4.2 BLUETOOTH_ATTRIBUTE_PROTOCOL.SendRequest
Summary
Send a “REQUEST” or “COMMAND” message to remote server and receive a “RESPONSE” message for “RE-
QUEST” from remote server according to Bluetooth attribute protocol data unit (PDU).
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST)(
IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,
IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION Callback,
);
This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
Data Data of a REQUEST or COMMAND message. The ﬁrst byte is the attribute PDU related opcode, followed by
opcode speciﬁc ﬁelds. See Bluetooth speciﬁcation, V ol 3, Part F, Attribute Protocol.
DataLength The length of Data in bytes.
Callback Callback function to notify the RESPONSE is received to the caller, with the response buffer. Caller must
check the response buffer content to know if the request action is success or fail. It may be NULL if the data is
a COMMAND.
Context Data passed into Callback function. It is optional parameter and may be NULL.
The SendRequest() function sends a “REQUEST” or “COMMAND” message to remote server and receive a “RE-
SPONSE” message for “REQUEST” from remote server according to Bluetooth attribute protocol data unit (PDU). In
most cases, this interface is used to read attributes from remote device, or write attributes to remote device.
typedef
(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION) (
);
26.4. EFI Bluetooth Attribute Protocol 1009Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Data Data received. The ﬁrst byte is the attribute opcode, followed by opcode speciﬁc ﬁelds. See Bluetooth speci-
ﬁcation, V ol 3, Part F, Attribute Protocol. It might be a normal RESPONSE message, or ERROR RESPONSE
message.
DataLength The length of* Data in bytes.
Context The context passed from the callback registration request.*
EFI_SUCCESS The request is sent successfully.
One or more parameters are invalid due to following conditions:
• The Buffer is NULL.
• The BufferLength is 0.
• The opcode in Buffer is not a valid OPCODE according to Bluetooth
• The Callback is NULL.
EFI_DEVICE_ERROR Sending the request failed due to the host controller or the device error.
EFI_NOT_READY A GATT operation is already underway for this device
EFI_UNSUPPORTED The attribute does not support the corresponding operation
26.4.3 BLUETOOTH_ATTRIBUTE_PROTOCOL.RegisterForServerNotiﬁcation
Summary Register or unregister a server initiated message, such as NOTIFICATION or INDICATION, on a charac-
teristic value on remote server.
Prototype
code-block:
typedef
(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION)
(
IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER *CallbackParameter,
);
CallbackParameter The parameter of the callback.
Callback Callback function for server initiated attribute protocol. NULL callback function means unregister the
server initiated callback.
26.4. EFI Bluetooth Attribute Protocol 1010Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The RegisterForServerNotiﬁcation() function can be issued to request Bluetooth to register or unregister a server
initiated message, such as notiﬁcation or indication, on a characteristic value on remote server. It can only be done if
the characteristic supports that operation.
UINT16 AttributeHandle;
} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION;
} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION;
UINT8 AttributeOpCode;
union {
EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION Notification;
EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION Indication;
} Parameter;
} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER;
Version The version of the structure. A value of zero represents the
EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER structure as deﬁned here. Future ver-
sion of this speciﬁcation may extend this data structure in a backward compatible way and increase the value of
Version.
AttributeOpCode The attribute opcode for server initiated attribute protocol. See Bluetooth speciﬁcation, V ol 3, Part
F, Attribute Protocol.
AttributeHandle The attribute handle for notiﬁcation or indication.
EFI_SUCCESS The callback function is registered or unregistered successfully
EFI_INV ALID_PARAMETER The attribute opcode is not server initiated message opcode. See Bluetooth
speciﬁcation, V ol 3, Part F, Attribute Protocol.
EFI_ALREADY_STARTED A callback function is already registered on the same attribute opcode and
attribute handle, when the Callback is not NULL.
EFI_NOT_STARTED A callback function is not registered on the same attribute opcode and at-
tribute handle, when the Callback is NULL.

Version.
EFI_UNSUPPORTED The attribute does not support notiﬁcation
26.4.4 BLUETOOTH_ATTRIBUTE_PROTOCOL.GetServiceInfo
Summary
Get Bluetooth discovered service information.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO)(
OUT UINTN *ServiceInfoSize,
26.4. EFI Bluetooth Attribute Protocol 1011Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
OUT VOID **ServiceInfo
);
ServiceInfoSize A pointer to the size, in bytes, of the ServiceInfo buffer.
ServiceInfo A pointer to a callee allocated buffer that returns Bluetooth discovered service information. Callee allo-
cates this buffer by using EFI Boot Service AllocatePool() .
The GetServiceInfo() function returns Bluetooth discovered service information. The size of ServiceInfo structure
should never be assumed and the value of ServiceInfoSize is the only valid way to know the size of ServiceInfo . The
ServiceInfo buffer is a list Bluetooth service information structures deﬁned below.
union {
UINT16 Uuid16;
UINT32 Uuid32;
UINT8 Uuid128[16];
} Data;
} EFI_BLUETOOTH_UUID;
Length The length of Bluetooth UUID data. The valid value is 2, 4, or 16.
Uuid16 The 16-bit Bluetooth UUID data.
Uuid32 The 32-bit Bluetooth UUID data.
Uuid128 The 128-bit Bluetooth UUID data.
EFI_BLUETOOTH_UUID Type;
EFI_BLUETOOTH_ATTRIBUTE_PERMISSION AttributePermission;
} EFI_BLUETOOTH_ATTRIBUTE_HEADER;
Type The type of this structure. It must be EFI_BLUETOOTH_UUID. See Bluetooth GATT deﬁnition. Primary
Service is 0x2800. Secondary Service is 0x2801. Include Service is 0x2802. Characteristic is 0x2803. Charac-
teristic Descriptor is 0x2900.
Length The length of this structure.
AttributeHandle The handle of the service declaration. See Bluetooth speciﬁcation.
AttributePermission The permission of the attribute. This ﬁeld is only valid for the attribute of the local device. This
ﬁeld should be ignored for the attribute of the remote device.
//
// Bluetooth Attribute Permission
//
struct {
26.4. EFI Bluetooth Attribute Protocol 1012Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT16 Readable : 1;
UINT16 ReadEncryption : 1;
UINT16 ReadAuthentication : 1;
UINT16 ReadAuthorization : 1;
UINT16 ReadKeySize : 5;
UINT16 Reserved1 : 7;
UINT16 Writeable : 1;
UINT16 WriteEncryption : 1;
UINT16 WriteAuthentication : 1;
UINT16 WriteAuthorization : 1;
UINT16 WriteKeySize : 5;
UINT16 Reserved2 : 7;
} Permission;
UINT32 Data32;
} EFI_BLUETOOTH_ATTRIBUTE_PERMISSION;
Readable The attribute is readable.
ReadEncryption The encryption is required on read.
ReadAuthentication The authentication is required on read.
ReadAuthorization The authorization is required on read.
ReadKeySize The size of key in bytes on read.
Writeable The attribute is writeable.
WriteEncryption The encryption is required on write.
WriteAuthentication The authentication is required on write.
WriteAuthorization The authorization is required on write.
WriteKeySize The size of key in bytes on write.
EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
UINT16 EndGroupHandle;
EFI_BLUETOOTH_UUID ServiceUuid;
} EFI_BLUETOOTH_GATT_PRIMARY_SERVICE_INFO;
EndGroupHandle The handle of the last attribute within the service deﬁnition. See Bluetooth speciﬁcation.
Header The header of this structure.
UINT16 StartGroupHandle;
} EFI_BLUETOOTH_GATT_INCLUDE_SERVICE_INFO;
UINT8 CharacteristicProperties;
UINT16 CharacteristicValueHandle;
EFI_BLUETOOTH_UUID CharacteristicUuid;
} EFI_BLUETOOTH_GATT_CHARACTERISTIC_INFO;
26.4. EFI Bluetooth Attribute Protocol 1013Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_BLUETOOTH_UUID CharacteristicDescriptorUuid;
} EFI_BLUETOOTH_GATT_CHARACTERISTIC_DESCRIPTOR_INFO;
EFI_SUCCESS The Bluetooth discovered service information is returned successfully.
EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth discovered ser-
vice information.
26.4.5 BLUETOOTH_ATTRIBUTE_PROTOCOL.GetDeviceInfo
Summary
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO)(
);
DeviceInfo A pointer to a callee allocated buffer that returns Bluetooth device information. Callee allo-
cates this buffer by using EFI Boot Service AllocatePool() . If this device is Bluetooth classic de-
vice, EFI_BLUETOOTH_DEVICE_INFO should be used. If this device is Bluetooth LE device,
EFI_BLUETOOTH_LE_DEVICE_INFO should be used.
UINT8 Address[6];
} BLUETOOTH_LE_ADDRESS;
BLUETOOTH_LE_ADDRESS BD_ADDR;
26.4. EFI Bluetooth Attribute Protocol 1014Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BLUETOOTH_LE_ADDRESS DirectAddress;
UINTN AdvertismentDataSize;
VOID *AdvertismentData;
} EFI_BLUETOOTH_LE_DEVICE_INFO;
Version The version of the structure. A value of zero represents th* e EFI_BLUETOOTH_LE_DEVICE_INFO
structure as deﬁned here. Future version of this speciﬁcation may extend this data structure in a backward
compatible way and increase the value of Version .
BD_ADDR 48bit Bluetooth device address and 1byte address type.
DirectAddress 48bit random device address and 1byte address type.
AdvertisementDataSize The size of AdvertisementData in bytes.
AdvertisementData Bluetooth LE advertisement data. See Bluetooth speciﬁcation for detail.
tion.
26.4.6 EFI_BLUETOOTH_ATTRIBUTE_SERVICE_BINDING_PROTOCOL
Summary
The EFI Bluetooth ATTRIBUTE Service Binding Protocol is used to locate EFI Bluetooth ATTRIBUTE Protocol
drivers to create and destroy child of the driver to communicate with other Bluetooth device by using Bluetooth
ATTRIBUTE protocol.
GUID
#define EFI_BLUETOOTH_ATTRIBUTE_SERVICE_BINDING_PROTOCOL_GUID \
{ \
0x5639867a, 0x8c8e, 0x408d, 0xac, 0x2f, 0x4b, 0x61, 0xbd, 0xc0, 0xbb, 0xbb \
}
The Bluetooth ATTRIBUTE consumer need locate EFI_BLUETOOTH_ATTRIBUTE_SERVICE_BINDING_PROTOCOL
and call CreateChild() to create a new child of EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance. Then use
EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL for Bluetooth communication. After use, the Bluetooth AT-
TRIBUTE consumer need call DestroyChild() to destroy it.
26.4. EFI Bluetooth Attribute Protocol 1015Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.5 EFI Bluetooth LE Conﬁguration Protocol
26.5.1 EFI_BLUETOOTH_LE_CONFIG_PROTOCOL
Summary
This protocol abstracts user interface conﬁguration for BluetoothLe device.
GUID
#define EFI_BLUETOOTH_LE_CONFIG_PROTOCOL_GUID \
{ 0x8f76da58, 0x1f99, 0x4275, { 0xa4, 0xec, 0x47, 0x56, 0x51, 0x5b, 0x1c, 0xe8 }}
typedef struct _EFI_BLUETOOTH_LE_CONFIG_PROTOCOL {
EFI_BLUETOOTH_LE_CONFIG_INIT Init;
EFI_BLUETOOTH_LE_CONFIG_SCAN Scan;
EFI_BLUETOOTH_LE_CONFIG_CONNECT Connect;
EFI_BLUETOOTH_LE_CONFIG_DISCONNECT Disconnect;
EFI_BLUETOOTH_LE_CONFIG_GET_DATA GetData;
EFI_BLUETOOTH_LE_CONFIG_SET_DATA SetData;
EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA GetRemoteData;
EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_AUTH_CALLBACK RegisterSmpAuthCallback;
EFI_BLUETOOTH_LE_CONFIG_SEND_SMP_AUTH_DATA SendSmpAuthData;
EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK
˓→RegisterSmpGetDataCallback;
EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK
˓→RegisterSmpSetDataCallback;
EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK
RegisterLinkConnectCompleteCallback;
} EFI_BLUETOOTH_LE_CONFIG_PROTOCOL;
Init Initialize BluetoothLE host controller and local device. See the Init() function description.

Scan Scan BluetoothLE device. See the Scan() function description.
Connect Connect one BluetoothLE device. See the Connect() function description.
Disconnect Disconnect one BluetoothLE device. See the Disconnect() function description.
GetData Get BluetoothLE conﬁguration data. See the GetData() function description.
SetData Set BluetoothLE conﬁguration data. See the SetData() function description.
GetRemoteData Get remote BluetoothLE device data. See the GetRemoteData() function description.
RegisterSmpAuthCallback Register Security Manager Callback function. This function will be called from Blue-
tooth BUS driver whenever user interaction is required for security protocol authorization/authentication. See
theRegisterSmpAuthCallback() function description.
SendSmpAuthData Send user input (Authentication/Authorization) such as passkey, conﬁrmation (yes/no) in re-
sponse to pairing request. See the SendSmpAuthData() function description.
RegisterSmpGetDataCallback Register a callback function to get SMP related data. See the RegisterSmpGetData-
Callback() function description.
RegisterSmpSetDataCallback Register a callback function to set SMP related data. See the RegisterSmpGetData-
26.5. EFI Bluetooth LE Conﬁguration Protocol 1016Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The EFI_BLUETOOTH_LE_CONFIG_PROTOCOL abstracts the BluetoothLE conﬁguration. User can use Blue-
toothLE conﬁguration to interactive with BluetoothLE bus driver.
26.5.2 BLUETOOTH_LE_CONFIG_PROTOCOL.Init
Summary
Initialize BluetoothLE host controller and local device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_INIT)(
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This
);
This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
TheInit() function initializes BluetoothLE host controller and local device.
EFI_SUCCESS The BluetoothLE host controller and local device is initialized successfully.
EFI_DEVICE_ERROR A hardware error occurred trying to initialize the BluetoothLE host con-
troller and local device.
26.5.3 BLUETOOTH_LE_CONFIG_PROTOCOL.Scan
Summary
Scan BluetoothLE device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN)(
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
IN UIN32 Timeout;
IN EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER *ScanParameter, OPTIONAL
IN EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION Callback,
);
26.5. EFI Bluetooth LE Conﬁguration Protocol 1017Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Timeout Duration in milliseconds for which to scan.
ScanParameter If it is not NULL, the ScanParameter is used to perform a scan by the BluetoothLE bus driver. If it is
NULL, the default parameter is used.
Callback The callback function. This function is called if a BluetoothLE device is found during scan process.
The Scan() function scans BluetoothLE device. When this function is returned, it just means scan request is sub-
mitted. It does not mean scan process is started or ﬁnished. Whenever there is a BluetoothLE device is found, the
Callback function will be called. Callback function might be called before this function returns or after this function
returns.
// Scan parameter
UINT8 ScanType;
UINT16 ScanInterval;
UINT16 ScanWindow;
UINT8 ScanningFilterPolicy;
// Scan result filter
UINT8 AdvertisementFlagFilter;
} EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER;
EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER structure as deﬁned here. Future version of
this speciﬁcation may extend this data structure in a backward compatible way and increase the value of
Version.
ScanType Passive scanning or active scanning. See Bluetooth speciﬁcation.
ScanInterval Recommended scan interval to be used while performing scan.
ScanWindow Recommended scan window to be used while performing a scan.
ScanningFilterPolicy Recommended scanning ﬁlter policy to be used while performing a scan.
AdvertisementFlagFilter This is one byte ﬂag to serve as a ﬁlter to remove unneeded scan result. For example, set
BIT0 means scan in LE Limited Discoverable Mode. Set BIT1 means scan in LE General Discoverable Mode.
See Supplement to Bluetooth Core Speciﬁcation.
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION) (
IN EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION *CallbackInfo
);
26.5. EFI Bluetooth LE Conﬁguration Protocol 1018Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BLUETOOTH_LE_ADDRESS BDAddr;
INT8 RSSI;
UINTN AdvertisementDataSize;
VOID *AdvertisementData;
} EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION;
26.5.4 BLUETOOTH_LE_CONFIG_PROTOCOL.Connect
Summary
Connect a BluetoothLE device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT)(
IN BOOLEAN AutoReconnect,
IN BOOLEAN DoBonding;
IN EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER *ConnectParameter, OPTIONAL
IN BLUETOOTH_LE_ADDRESS *BD_ADDR
);
AutoReconnect IfTRUE . the BluetoothLE host controller needs to do an auto reconnect. If FALSE, the BluetoothLE
host controller does not do an auto reconnect.
DoBonding IfTRUE, the BluetoothLE host controller needs to do a bonding. If FALSE, the BluetoothLE host con-
troller does not do a bonding.
ConnectParameter If it is not NULL, the ConnectParameter is used to perform a scan by the BluetoothLE bus driver.
If it is NULL, the default parameter is used.
BD_ADDR The address of the BluetoothLE device to be connected.
26.5. EFI Bluetooth LE Conﬁguration Protocol 1019Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT16 ConnIntervalMin;
UINT16 ConnIntervalMax;
UINT16 ConnLatency;
UINT16 SupervisionTimeout;
} EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER;
EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER structure as deﬁned here. Future version
of this speciﬁcation may extend this data structure in a backward compatible way and increase the value of
Version.
ScanInterval Recommended scan interval to be used while performing scan before connect.
ScanWindow Recommended scan window to be used while performing a connection.
ConnIntervalMin Minimum allowed connection interval. Shall be less than or equal to ConnIntervalMax.
ConnIntervalMax Maximum allowed connection interval. Shall be greater than or equal to ConnIntervalMin.
ConnLatency Slave latency for the connection in number of connection events.
SupervisionTimeout Link supervision timeout for the connection.
EFI_SUCCESS The BluetoothLE device is connected successfully.
EFI_ALREADY_STARTED The BluetoothLE device is already connected.
EFI_NOT_FOUND The BluetoothLE device is not found.
EFI_DEVICE_ERROR A hardware error occurred trying to connect the BluetoothLE device.
26.5.5 BLUETOOTH_LE_CONFIG_PROTOCOL.Disconnect
Summary
Disconnect a BluetoothLE device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_DISCONNECT)(
IN BLUETOOTH_LE_ADDRESS *BD_ADDR,
IN UINT8 Reason
);
BD_ADDR The address of BluetoothLE device to be connected.
Reason BluetoothLE disconnect reason. See Bluetooth speciﬁcation for detail.
The Disconnect() function disconnects a BluetoothLE device. When this function is returned successfully, the
EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL associated with this device is destroyed and all services associated
are stopped.

Summary
Prototype
typedef
);
26.5. EFI Bluetooth LE Conﬁguration Protocol 1020Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The BluetoothLE device is disconnected successfully.
EFI_NOT_STARTED The BluetoothLE device is not connected.
EFI_DEVICE_ERROR A hardware error occurred trying to disconnect the BluetoothLE device.
26.5.6 BLUETOOTH_LE_CONFIG_PROTOCOL.GetData
Summary
Get BluetoothLE conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_DATA) (
);
The GetData() function returns BluetoothLE conﬁguration data. For remote BluetoothLE device conﬁguration data,
please use GetRemoteData() function with valid BD_ADDR.
EFI_SUCCESS The BluetoothLE conﬁguration data is returned successfully.
•DataSize is NULL.
• *DataSize is 0.
EFI_NOT_FOUND TheDataType is not found.
26.5. EFI Bluetooth LE Conﬁguration Protocol 1021Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.5.7 BLUETOOTH_LE_CONFIG_PROTOCOL.SetData
Summary
Set BluetoothLE conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SET_DATA) (
);
The SetData() function sets local BluetoothLE device conﬁguration data. Not all DataType can be set.
EFI_SUCCESS The BluetoothLE conﬁguration data is set successfully.
26.5.8 BLUETOOTH_LE_CONFIG_PROTOCOL.GetRemoteData
Summary
Get remove BluetoothLE device conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA) (
IN BLUETOOTH_LE_ADDRESS *BDAddr,
);
26.5. EFI Bluetooth LE Conﬁguration Protocol 1022Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BDAddr Remote BluetoothLE device address.
The GetRemoteData() function returns remote BluetoothLE device conﬁguration data.
EFI_SUCCESS The remote BluetoothLE device conﬁguration data is returned successfully.
26.5.9 BLUETOOTH_LE_CONFIG_PROTOCOL.RegisterSmpAuthCallback
Summary
Register Security Manager Protocol callback function for user authentication/authorization.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK)(
IN EFI_BLUETOOTH_LE_SMP_CALLBACK Callback,
);
Callback Callback function for user authentication/authorization.
Context Data passed into callback function. This is optional parameter and may be NULL.
The RegisterSmpAuthCallback() function register Security Manager Protocol callback function for user authenti-
cation/authorization.
26.5. EFI Bluetooth LE Conﬁguration Protocol 1023Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef
(EFIAPI *EFI_BLUETOOTH_LE_SMP_CALLBACK) (
IN EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE EventDataType,
);
EventDataType Event data type in EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE .
Data A pointer to the buffer of data.
EfiBlutoothSmpAuthorizationRequestEvent,
EfiBlutoothSmpPasskeyReadyEvent,
EfiBlutoothSmpPasskeyRequestEvent,
EfiBlutoothSmpOOBDataRequestEvent,
EfiBlutoothSmpNumericComparisonEvent,
} EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE;
EﬁBlutoothSmpAuthorizationRequestEvent It indicates an authorization request. No data is associated with the
callback input. In the output data, the application should return the authorization value. The data structure is
BOOLEAN. TRUE means YES. FALSE means NO.
EﬁBlutoothSmpPasskeyReadyEvent It indicates that a passkey has been generated locally by the driver, and the
same passkey should be entered at the remote device. The callback input data is the passkey of type UINT32, to
be displayed by the application. No output data should be returned.
EﬁBlutoothSmpPasskeyRequestEvent It indicates that the driver is requesting for the passkey has been generated at
the remote device. No data is associated with the callback input. The output data is the passkey of type UINT32,
to be entered by the user.
EﬁBlutoothSmpOOBDataRequestEvent It indicates that the driver is requesting for the passkey that has been pre-
shared out-of-band with the remote device. No data is associated with the callback input. The output data is the
stored OOB data of type UINT8[16].
EﬁBlutoothSmpNumericComparisonEvent In indicates that a number have been generated locally by the bus
driver, and also at the remote device, and the bus driver wants to know if the two numbers match. The call-
back input data is the number of type UINT32. The output data is conﬁrmation value of type BOOLEAN.
TRUE means comparison pass. FALSE means comparison fail.
EFI_SUCCESS The SMP callback function is registered successfully.
26.5. EFI Bluetooth LE Conﬁguration Protocol 1024Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.5.10 BLUETOOTH_LE_CONFIG_PROTOCOL.SendSmpAuthData
Summary
Send user authentication/authorization to remote device.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA)(
);
DataSize The size of Data in bytes, of the data buffer speciﬁed by Data .
Data A pointer to the buffer of data that will be sent. The data format depends on the type of SMP event data being
responded to. See EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE .
The SendSmpAuthData() function sends user authentication/authorization to remote device. It should be used to
send these information after the caller gets the request data from the callback function by RegisterSmpAuthCallback
().
EFI_SUCCESS The SMP authorization data is sent successfully.
EFI_NOT_READY SMP is not in the correct state to receive the auth data
26.5.11 BLUETOOTH_LE_CONFIG_PROTOCOL.RegisterSmpGetDataCallback
Summary
Register a callback function to get SMP related data.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK )(

().
Summary
Prototype
typedef
IN EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK Callback,
);
26.5. EFI Bluetooth LE Conﬁguration Protocol 1025Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Callback Callback function for SMP get data.
The RegisterSmpGetDataCallback() function registers a callback function to get SMP related data.
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK) (
IN EFI_BLUETOOTH_LE_SMP_DATA_TYPE DataType,
OUT VOID *Data
);
BDAddr Remote BluetoothLE device address. For Local device setting, it should be NULL.
DataType Data type in EFI_BLUETOOTH_LE_SMP_DATA_TYPE .
// For local device only
EfiBluetoothSmpLocalIR, / *If Key hierarchy issupported */
EfiBluetoothSmpLocalER, / *If Key hierarchy issupported */
EfiBluetoothSmpLocalDHK, / *If Key hierarchy issupported. OPTIONAL */
// For peer specific
EfiBluetoothSmpKeysDistributed = 0x1000,
EfiBluetoothSmpKeySize,
EfiBluetoothSmpKeyType,
EfiBluetoothSmpPeerLTK,
EfiBluetoothSmpPeerIRK,
EfiBluetoothSmpPeerCSRK,
EfiBluetoothSmpPeerRand,
EfiBluetoothSmpPeerEDIV,
EfiBluetoothSmpPeerSignCounter,
EfiBluetoothSmpLocalLTK, / *If Key hierarchy notsupported */
EfiBluetoothSmpLocalIRK, / *If Key hierarchy notsupported */
EfiBluetoothSmpLocalCSRK, / *If Key hierarchy notsupported */
EfiBluetoothSmpLocalSignCounter,
EfiBluetoothSmpLocalDIV,
EfiBluetoothSmpPeerAddressList,
EfiBluetoothSmpMax,
} EFI_BLUETOOTH_LE_SMP_DATA_TYPE;
EﬁBlutoothSmpLocalIR It is a 128-bit Identity Root (IR) key to generate IRK. Data structure is UINT8[16]. See
Bluetooth speciﬁcation. This is only required when Bluetooth key hierarchy is supported. This type is for the
local device only.
26.5. EFI Bluetooth LE Conﬁguration Protocol 1026Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EﬁBlutoothSmpLocalER It is a 128-bit Encryption Root (ER) key to generate LTK and CSRK. Data structure is
UINT8[16]. See Bluetooth speciﬁcation. This is only required when Bluetooth key hierarchy is supported. This
type is for the local device only.
EﬁBlutoothSmpLocalDHK It is a 128-bit Diversiﬁer Hiding Key (DHK) to generate EDIV . Data structure is
UINT8[16].See Bluetooth speciﬁcation. This is only required when Bluetooth key hierarchy is supported. This
EﬁBlutoothSmpKeysDistributed It is LE Key Distribution Format. Data structure is UINT8. See Bluetooth speciﬁ-
cation. This is the peer device speciﬁc information.
EﬁBlutoothSmpKeySize It indicates the size of keys in bytes. It is the negotiated key size between local device and
peer device. Data structure is UINTN. This is the peer device speciﬁc information.
EﬁBlutoothSmpKeyType Indicates support for MITM/Secure connection. It is the negotiated Authentication Re-
quirements between local device and peer device. See Bluetooth Spec 3.H.3.5.1. Data structure is UINT8.
BIT0: MITM, BIT1: SC. This is the peer device speciﬁc information.
EﬁBlutoothSmpPeerLTK It is a 128-bit Long-Term Key (LTK) to generate the contributory session key for an en-
crypted connection. Data structure is UINT8[16]. See Bluetooth speciﬁcation. This is the peer device speciﬁc
EﬁBlutoothSmpPeerIRK It is a 128-bit Identity Resolving Key (IRK) to generate and resolve random addresses.
Data structure is UINT8[16]. See Bluetooth speciﬁcation. This is the peer device speciﬁc information.
EﬁBlutoothSmpPeerCSRK It is a 128-bit Connection-Signature Resolving Key (CSRK) to sign data and verify
signatures on the receiving device. Data structure is UINT8[16]. See Bluetooth speciﬁcation. This is the peer
device speciﬁc information.
EﬁBlutoothSmpPeerRand It is a 64-bit Random number (Rand) to identify the LTK distributed during LE legacy
pairing. Data structure is UINT64. See Bluetooth speciﬁcation. This is the peer device speciﬁc information.
EﬁBlutoothSmpPeerEDIV It is a 16-bit Encrypted Diversiﬁer (EDIV) to identify the LTK distributed during LE
legacy pairing. Data structure is UINT16. See Bluetooth speciﬁcation. This is the peer device speciﬁc informa-
tion.
EﬁBlutoothSmpPeerSignCounter It is a 32-bit Sign Counter to assist MAC generation. Data structure is UINT32.
See Bluetooth speciﬁcation. This is the peer device speciﬁc information.
EﬁBlutoothSmpLocakLTK It is a 128-bit Long-Term Key (LTK) to generate the contributory session key for an
encrypted connection. Data structure is UINT8[16]. See Bluetooth speciﬁcation. This is only required when
Bluetooth key hierarchy is not supported. This is the peer speciﬁc local device information.
EﬁBlutoothSmpLocalIRK It is a 128-bit Identity Resolving Key (IRK) to generate and resolve random addresses.
Data structure is UINT8[16]. See Bluetooth speciﬁcation. This is only required when Bluetooth key hierarchy
is not supported. This is the peer speciﬁc local device information.
EﬁBlutoothSmpLocalCSRK It is a 128-bit Connection-Signature Resolving Key (CSRK) to sign data and verify
signatures on the receiving device. Data structure is UINT8[16]. See Bluetooth speciﬁcation. This is only
required when Bluetooth key hierarchy is not supported. This is the peer speciﬁc local device information.
EﬁBlutoothSmpLocalSignCounter It is a 32-bit Sign Counter to assist MAC generation. Data structure is UINT32.
See Bluetooth speciﬁcation. This is the peer speciﬁc local device information.
EﬁBlutoothSmpLocalDIV It is a 16-bit Diversiﬁer (DIV) to be used as index to recover LTK. Data structure is
UINT16. See Bluetooth speciﬁcation. This is the peer speciﬁc local device information.
EﬁBluetoothSmpPeerAddressList A list of Bluetooth peer addresses that have been connected before.
The data structure is BLUETOOTH_LE_ADDRESS[]. The data size must be a multiple of
sizeof(BLUETOOTH_LE_ADDRESS).
26.5. EFI Bluetooth LE Conﬁguration Protocol 1027Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The SMP get data callback function is registered successfully.
26.5.12 BLUETOOTH_LE_CONFIG_PROTOCOL.RegisterSmpSetDataCallback
Summary
Register a callback function to set SMP related data.
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK )(
IN EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK Callback,
);
Callback Callback function for SMP set data.
The RegisterSmpSetDataCallback() function registers a callback function to set SMP related data.
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK) (
IN EFI_BLUETOOTH_LE_SMP_DATA_TYPE Type,
);
26.5. EFI Bluetooth LE Conﬁguration Protocol 1028Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
26.5.13 BLUETOOTH_LE_CONFIG_PROTOCOL.RegisterLinkConnectCompleteCallback
Summary
Prototype
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK) (

Summary
Prototype
typedef
IN EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK Callback,
);
function. During pairing, Bluetooth bus driver must trigger this callback function to report device state, if it is reg-
istered. Then Bluetooth Conﬁguration driver will get information on device connection, according to CallbackType
deﬁned by EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE.
typedef
(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK) (
);
BDAddr A pointer to BluetoothLE device address.
26.5. EFI Bluetooth LE Conﬁguration Protocol 1029Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
2876 .. _network-protocols-vlan-eap-wi-ﬁ-and-supplicant:
26.5. EFI Bluetooth LE Conﬁguration Protocol 1030CHAPTER
TWENTYSEVEN
NETWORK PROTOCOLS — VLAN, EAP, WI-FI AND SUPPLICANT
27.1 VLAN Conﬁguration Protocol
27.1.1 EFI_VLAN_CONFIG_PROTOCOL
Summary
This protocol is to provide manageability interface for VLAN conﬁguration.
GUID
#define EFI_VLAN_CONFIG_PROTOCOL_GUID \
{0x9e23d768, 0xd2f3, 0x4366, \
{0x9f, 0xc3, 0x3a, 0x7a, 0xba, 0x86, 0x43, 0x74}}
typedef struct _EFI_VLAN_CONFIG_PROTOCOL {
EFI_VLAN_CONFIG_SET Set;
EFI_VLAN_CONFIG_FIND Find;
EFI_VLAN_CONFIG_REMOVE Remove;
} EFI_VLAN_CONFIG_PROTOCOL;
SetCreate new VLAN device or modify conﬁguration parameter of an already-conﬁgured VLAN
Find Find conﬁguration information for speciﬁed VLAN or all conﬁgured VLANs.
Remove Remove a VLAN device.
This protocol is to provide manageability interface for VLAN setting. The intended VLAN tagging implementation is
IEEE802.1Q.
1031Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.1.2 EFI_VLAN_CONFIG_PROTOCOL.Set()
Summary
Create a VLAN device or modify the conﬁguration parameter of an already-conﬁgured VLAN
Prototype
typedef
(EFIAPI *EFI_VLAN_CONFIG_SET) (
IN EFI_VLAN_CONFIG_PROTOCOL *This,
IN UINT16 VlanId,
IN UINT8 Priority
);
This Pointer to EFI_VLAN_CONFIG_PROTOCOL instance.
VlanId A unique identiﬁer (1-4094) of the VLAN which is being created or modiﬁed, or zero (0).
Priority 3 bit priority in VLAN header. Priority 0 is default value. If VlanId is zero (0), Priority is ignored.
TheSet() function is used to create a new VLAN device or change the VLAN conﬁguration parameters. If the VlanId
hasn’t been conﬁgured in the physical Ethernet device, a new VLAN device will be created. If a VLAN with this
VlanId is already conﬁgured, then related conﬁguration will be updated as the input parameters.
IfVlanId is zero, the VLAN device will send and receive untagged frames. Otherwise, the VLAN device will send
and receive VLAN-tagged frames containing the VlanId.
IfVlanId is out of scope of (0-4094), EFI_INVALID_PARAMETER is returned
IfPriority is out of the scope of (0-7), then EFI_INVALID_PARAMETER is returned.
If there is not enough system memory to perform the registration, then EFI_OUT_OF_RESOURCES is returned.
EFI_SUCCESS The VLAN is successfully conﬁgured
One or more of following conditions is TRUE
• This is NULL
• VlanId is an invalid VLAN Identiﬁer
• Priority is invalid
EFI_OUT_OF_RESOURCES There is not enough system memory to perform the registration.
27.1. VLAN Conﬁguration Protocol 1032Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.1.3 EFI_VLAN_CONFIG_PROTOCOL.Find()
Summary
Find conﬁguration information for speciﬁed VLAN or all conﬁgured VLANs.
Prototype
typedef
(EFIAPI *EFI_VLAN_CONFIG_FIND) (
IN UINT16 *VlanId, OPTIONAL
OUT UINT16 *NumberOfVlan,
OUT EFI_VLAN_FIND_DATA **Entries
);
VlanId Pointer to VLAN identiﬁer. Set to NULL to ﬁnd all conﬁgured VLANs
NumberOfVlan The number of VLANs which is found by the speciﬁed criteria
Entries The buffer which receive the VLAN conﬁguration. Type EFI_VLAN_FIND_DATA is deﬁned below.
TheFind() function is used to ﬁnd the conﬁguration information for matching VLAN and allocate a buffer into which
those entries are copied.
// EFI_VLAN_FIND_DATA
UINT16 VlanId;
UINT8 Priority;
} EFI_VLAN_FIND_DATA;
VlanId Vlan Identiﬁer
Priority Priority of this VLAN
EFI_SUCCESS The VLAN is successfully found
• Speciﬁed VlanId is invalid
EFI_NOT_FOUND No matching VLAN is found
27.1. VLAN Conﬁguration Protocol 1033Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.1.4 EFI_VLAN_CONFIG_PROTOCOL.Remove()
Summary
Remove the conﬁgured VLAN device
Prototype
typedef
(EFIAPI *EFI_VLAN_CONFIG_REMOVE) (
IN UINT16 VlanId
);
VlanId Identiﬁer (0-4094) of the VLAN to be removed.
TheRemove() function is used to remove the speciﬁed VLAN device. If the VlanId is out of the scope of (0-4094),
EFI_INVALID_PARAMETER is returned. If speciﬁed VLAN hasn’t been previously conﬁgured, EFI_NOT_FOUND
EFI_SUCCESS The VLAN is successfully removed
•VlanId is an invalid parameter.
EFI_NOT_FOUND The to-be-removed VLAN does not exist
27.2 EAP Protocol
This section deﬁnes the EAP protocol. This protocol is designed to make the EAP framework conﬁgurable and
extensible. It is intended for the supplicant side.
27.2.1 EFI_EAP_PROTOCOL
Summary
This protocol is used to abstract the ability to conﬁgure and extend the EAP framework.
GUID
#define EFI_EAP_PROTOCOL_GUID \
{ 0x5d9f96db, 0xe731, 0x4caa,\
{0xa0, 0x0d, 0x72, 0xe1, 0x87, 0xcd, 0x77, 0x62 }}
27.2. EAP Protocol 1034Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct _EFI_EAP_PROTOCOL {
EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD SetDesiredAuthMethod;
EFI_EAP_REGISTER_AUTHENTICATION_METHOD RegisterAuthMethod;
} EFI_EAP_PROTOCOL;
SetDesiredAuthMethod Set the desired EAP authentication method for the Port. See the SetDesiredAuthMethod()
RegisterAuthMethod Register an EAP authentication method. See the RegisterAuthMethod() function description.
EFI_EAP_PROTOCOL is used to conﬁgure the desired EAP authentication method for the EAP framework and extend
the EAP framework by registering new EAP authentication method on a Port. The EAP framework is built on a per-
Port basis. Herein, a Port means a NIC. For the details of EAP protocol, please refer to RFC 2284.
//
// Type forthe identification number assigned to the Port by the
// System inwhich the Port resides.
//
typedef VOID *EFI_PORT_HANDLE;
27.2.2 EFI_EAP.SetDesiredAuthMethod()
Summary
Set the desired EAP authentication method for the Port.
Prototype
typedef
(EFIAPI *EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD) (
IN struct _EFI_EAP_PROTOCOL *This,
IN UINT8 EapAuthType
);
This A pointer to the EFI_EAP_PROTOCOL instance that indicates the calling context. Type EFI_EAP_PROTOCOL
is deﬁned in Section 1.1.
EapAuthType The type of the desired EAP authentication method for the Port. It should be the type value deﬁned
by RFC. See RFC 2284 for details. Current valid values are deﬁned in “Related Deﬁnitions”.
//
// EAP Authentication Method Type (RFC 3748)

//
//
Summary
Prototype
typedef
);
//
//
#define EFI_EAP_TYPE_TLS 13 / *REQUIRED - RFC 5216 */
TheSetDesiredAuthMethod() function sets the desired EAP authentication method indicated by EapAuthType for the
Port.
27.2. EAP Protocol 1035Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IfEapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is returned.
If the EAP authentication method of EapAuthType is unsupported, then it will return EFI_UNSUPPORTED.
EFI_SUCCESS The desired EAP authentication method is set successfully.
EFI_INV ALID_PARAMETER EapAuthType is an invalid EAP authentication type.
EFI_UNSUPPORTED The EAP authentication method of EapAuthType is unsupported by the
Port.
27.2.3 EFI_EAP.RegisterAuthMethod()
Summary
Register an EAP authentication method.
Prototype
typedef
(EFIAPI *EFI_EAP_REGISTER_AUTHENTICATION_METHOD) (
IN UINT8 EapAuthType,
IN EFI_EAP_BUILD_RESPONSE_PACKET Handler
);
EapAuthType The type of the EAP authentication method to register. It should be the type value deﬁned by RFC.
See RFC 2284 for details. Current valid values are deﬁned in the SetDesiredAuthMethod() function description.
Handler The handler of the EAP authentication method to register. Type EFI_EAP_BUILD_RESPONSE_PACKET
is deﬁned in “Related Deﬁnitions”.
typedef
(EFIAPI *EFI_EAP_BUILD_RESPONSE_PACKET) (
IN EFI_PORT_HANDLE PortNumber
IN UINT8 *RequestBuffer,
IN UINTN RequestSize,
IN UINT8 *Buffer,
IN OUT UINTN *BufferSize
);
Routine Description: Build EAP response packet in response to the EAP request packet speciﬁed by (RequestBuffer,
RequestSize).
Arguments
PortNumber — Speciﬁed the Port where the EAP request packet comes.
RequestBuffer — Pointer to the most recently received EAP-Request packet.
RequestSize — Packet size in bytes for the most recently received EAP-Request packet.
Buffer — Pointer to the buffer to hold the built packet.
27.2. EAP Protocol 1036Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BufferSize — Pointer to the buffer size in bytes. On input, it is the
buffer size provided by the caller. On output, it is the buffer size
in fact needed to contain the packet.
Returns: EFI_SUCCESS — The required EAP response packet is built successfully. Others — Failures are encoun-
tered during the packet building process.
TheRegisterAuthMethod() function registers the user provided EAP authentication method, the type of which is Ea-
pAuthType and the handler of which is Handler.
EFI_SUCCESS The EAP authentication method of EapAuthType is registered successfully.
27.2.4 EAPManagement Protocol
This section deﬁnes the EAP management protocol. This protocol is designed to provide ease of management and
ease of test for EAPOL state machine. It is intended for the supplicant side. It conforms to IEEE 802.1x speciﬁcation.
27.2.5 EFI_EAP_MANAGEMENT_PROTOCOL
Summary
This protocol provides the ability to conﬁgure and control EAPOL state machine, and retrieve the status and the
statistics information of EAPOL state machine.
GUID
#define EFI_EAP_MANAGEMENT_PROTOCOL_GUID \
{ 0xbb62e663, 0x625d, 0x40b2, \
{ 0xa0, 0x88, 0xbb, 0xe8, 0x36, 0x23, 0xa2, 0x45 }
typedef struct _EFI_EAP_MANAGEMENT_PROTOCOL {
EFI_EAP_GET_SYSTEM_CONFIGURATION GetSystemConfiguration;
EFI_EAP_SET_SYSTEM_CONFIGURATION SetSystemConfiguration;
EFI_EAP_INITIALIZE_PORT InitializePort;
EFI_EAP_USER_LOGON UserLogon;
EFI_EAP_USER_LOGOFF UserLogoff;
EFI_EAP_GET_SUPPLICANT_STATUS GetSupplicantStatus;
EFI_EAP_SET_SUPPLICANT_CONFIGURATION SetSupplicantConfiguration;
EFI_EAP_GET_SUPPLICANT_STATISTICS GetSupplicantStatistics;
} EFI_EAP_MANAGEMENT_PROTOCOL;
GetSystemConﬁguration Read the system conﬁguration information associated with the Port. See the GetSystem-
Conﬁguration() function description.
27.2. EAP Protocol 1037Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SetSystemConﬁguration Set the system conﬁguration information associated with the Port. See the SetSystemCon-
ﬁguration() function description.
InitializePort Cause the EAPOL state machines for the Port to be initialized. See the InitializePort() function de-
UserLogon Notify the EAPOL state machines for the Port that the user of the System has logged on. See the UserL-
ogon() function description.
UserLogoff Notify the EAPOL state machines for the Port that the user of the System has logged off. See the
UserLogoff() function description.
GetSupplicantStatus Read the status of the Supplicant PAE state machine for the Port, including the current state
and the conﬁguration of the operational parameters. See the GetSupplicantStatus() function description.
SetSupplicantConﬁguration Set the conﬁguration of the operational parameter of the Supplicant PAE state machine
for the Port. See the SetSupplicantConﬁguration() function description.
GetSupplicantStatistics Read the statistical information regarding the operation of the Supplicant associated with
the Port. See the GetSupplicantStatistics() function description.
TheEFI_EAP_MANAGEMENT protocol is used to control, conﬁgure and monitor EAPOL state machine on a Port.
EAPOL state machine is built on a per-Port basis. Herein, a Port means a NIC. For the details of EAPOL, please refer
to IEEE 802.1x speciﬁcation.
27.2.6 EFI_EAP_MANAGEMENT.GetSystemConﬁguration()
Summary
Read the system conﬁguration information associated with the Port.
Prototype
typedef
(EFIAPI *EFI_EAP_GET_SYSTEM_CONFIGURATION) (
IN struct _EFI_EAP_MANAGEMENT_PROTOCOL *This,
OUT BOOLEAN *SystemAuthControl,
OUT EFI_EAPOL_PORT_INFO *PortInfo OPTIONAL
);
This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL instance that indicates the calling context. Type
EFI_EAP_MANAGEMENT_PROTOCOL is deﬁned in EAPManagement Protocol .
SystemAuthControl Returns the value of the SystemAuthControl parameter of the System. TRUE means Enabled.
FALSE means Disabled.
PortInfo Returns EFI_EAPOL_PORT_INFO structure to describe the Port’s information. This parameter can be
NULL to ignore reading the Port’s information. Type EFI_EAPOL_PORT_INFO is deﬁned in “Related Deﬁni-
tions”.
//
// PAE Capabilities
//
#define PAE_SUPPORT_AUTHENTICATOR 0x01
27.2. EAP Protocol 1038Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define PAE_SUPPORT_SUPPLICANT 0x02
typedef struct _EFI_EAPOL_PORT_INFO {
EFI_PORT_HANDLE PortNumber;
UINT8 ProtocolVersion;
UINT8 PaeCapabilities;
} EFI_EAPOL_PORT_INFO;
PortNumber The identiﬁcation number assigned to the Port by the System in which the Port resides.
ProtocolVersion The protocol version number of the EAPOL implementation supported by the Port.
PaeCapabilities The capabilities of the PAE associated with the Port. This ﬁeld indicates whether Authenticator
functionality, Supplicant functionality, both, or neither, is supported by the Port’s PAE.
TheGetSystemConﬁguration() function reads the system conﬁguration information associated with the Port, including
the value of the SystemAuthControl parameter of the System is returned in SystemAuthControl and the Port’s infor-
mation is returned in the buffer pointed to by PortInfo. The Port’s information is optional. If P ortInfo isNULL, then
reading the Port’s information is ignored.
IfSystemAuthControl isNULL, then EFI_INVALID_PARAMETER is returned.
EFI_SUCCESS The system conﬁguration information of the Port is read successfully.
EFI_INV ALID_PARAMETER SystemAuthControl is NULL.
27.2.7 EFI_EAP_MANAGEMENT.SetSystemConﬁguration()
Summary
Set the system conﬁguration information associated with the Port.
Prototype
typedef
(EFIAPI *EFI_EAP_SET_SYSTEM_CONFIGURATION) (
IN BOOLEAN SystemAuthControl
);
SystemAuthControl The desired value of the SystemAuthControl parameter of the System. TRUE means Enabled.
TheSetSystemConﬁguration() function sets the value of the SystemAuthControl parameter of the System to SystemAu-
thControl.
27.2. EAP Protocol 1039Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

Summary
Prototype
typedef
);
EFI_SUCCESS The system conﬁguration information of the Port is set successfully.
27.2.8 EFI_EAP_MANAGEMENT.InitializePort()
Summary
Cause the EAPOL state machines for the Port to be initialized.
Prototype
typedef
(EFIAPI *EFI_EAP_INITIALIZE_PORT) (
IN struct _EFI_EAP_MANAGEMENT_PROTOCOL *This
);
The InitializePort() function causes the EAPOL state machines for the Port.
EFI_SUCCESS The Port is initialized successfully.
27.2.9 EFI_EAP_MANAGEMENT.UserLogon()
Summary
Notify the EAPOL state machines for the Port that the user of the System has logged on.
Prototype
typedef
(EFIAPI *EFI_EAP_USER_LOGON) (
);
This A pointer to the E FI_EAP_MANAGEMENT_PROTOCOL instance that indicates the calling context. Type
The UserLogon() function notiﬁes the EAPOL state machines for the Port.
EFI_SUCCESS The Port is notiﬁed successfully.
27.2. EAP Protocol 1040Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.2.10 EFI_EAP_MANAGEMENT.UserLogoff()
Summary
Notify the EAPOL state machines for the Port that the user of the System has logged off.
Prototype
typedef
(EFIAPI *EFI_EAP_USER_LOGOFF) (
);
The UserLogoff() function notiﬁes the EAPOL state machines for the Port.
27.2.11 EFI_EAP_MANAGEMENT.GetSupplicantStatus()
Summary
Read the status of the Supplicant PAE state machine for the Port, including the current state and the conﬁguration of
the operational parameters.
Prototype
typedef
(EFIAPI *EFI_EAP_GET_SUPPLICANT_STATUS) (
OUT EFI_EAPOL_SUPPLICANT_PAE_STATE *CurrentState,
IN OUT EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION *Configuration OPTIONAL
);
CurrentState Returns the current state of the Supplicant PAE state machine for the Port. Type
EFI_EAPOL_SUPPLICANT_PAE_STATE is deﬁned in “Related Deﬁnitions”.
Conﬁguration Returns the conﬁguration of the operational parameters of the Supplicant PAE state machine for the
Port as required. This parameter can be NULL to ignore reading the conﬁguration. On input, Conﬁguration.
ValidFieldMask speciﬁes the operational parameters to be read. On output, Conﬁguration returns the conﬁgu-
ration of the required operational parameters. Type EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION is
deﬁned in “Related Deﬁnitions”.
27.2. EAP Protocol 1041Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// Supplicant PAE state machine (IEEE Std 802.1X Section 8.5.10)
//
typedef enum _EFI_EAPOL_SUPPLICANT_PAE_STATE {
Logoff,
Disconnected,
Connecting,
Acquired,
Authenticating,
Held,
Authenticated,
MaxSupplicantPaeState
} EFI_EAPOL_SUPPLICANT_PAE_STATE;
//
// Definitions forValidFieldMask
//
#define AUTH_PERIOD_FIELD_VALID 0x01
#define HELD_PERIOD_FIELD_VALID 0x02
#define START_PERIOD_FIELD_VALID 0x04
#define MAX_START_FIELD_VALID 0x08
typedef struct _EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION {
UINT8 ValidFieldMask;
UINTN AuthPeriod;
UINTN HeldPeriod;
UINTN StartPeriod;
UINTN MaxStart;
} EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION;
ValidFieldMask Indicates which of the following ﬁelds are valid.
AuthPeriod The initial value for the authWhile timer. Its default value is 30 s.
HeldPeriod The initial value for the heldWhile timer. Its default value is 60 s.
StartPeriod The initial value for the startWhen timer. Its default value is 30 s.
MaxStart The maximum number of successive EAPOL-Start messages will be sent before the Supplicant assumes
that there is no Authenticator present. Its default value is 3.
TheGetSupplicantStatus() function reads the status of the Supplicant PAE state machine for the Port, including the
current state CurrentState and the conﬁguration of the operational parameters Conﬁguration. The conﬁguration of
the operational parameters is optional. If Conﬁguration isNULL, then reading the conﬁguration is ignored. The
operational parameters in Conﬁguration to be read can also be speciﬁed by Conﬁguration. ValidFieldMask.
IfCurrentState isNULL, then EFI_INVALID_PARAMETER is returned.
EFI_SUCCESS The status of the Supplicant PAE state machine for the Port is read success-
fully.
EFI_INV ALID_PARAMETER CurrentState isNULL.
27.2. EAP Protocol 1042Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.2.12 EFI_EAP_MANAGEMENT.SetSupplicantConﬁguration()
Summary
Set the conﬁguration of the operational parameter of the Supplicant PAE state machine for the Port.
Prototype
typedef
(EFIAPI *EFI_EAP_SET_SUPPLICANT_CONFIGURATION) (
IN EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION *Configuration
);
Conﬁguration The desired conﬁguration of the operational parameters of the Supplicant PAE state machine for
the Port as required. Type EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION is deﬁned in the GetSup-
plicantStatus() function description.
The SetSupplicantConﬁguration() function sets the conﬁguration of the operational parameter of the Supplicant PAE
state machine for the Port to Conﬁguration. The operational parameters in Conﬁguration to be set can be speciﬁed by
Conﬁguration.ValidFieldMask.
If Conﬁguration is NULL, then EFI_INV ALID_PARAMETER is returned.
EFI_SUCCESS The conﬁguration of the operational parameter of the Supplicant PAE state
machine for the Port is set successfully.
EFI_INV ALID_PARAMETER Conﬁguration isNULL.
27.2.13 EFI_EAP_MANAGEMENT.GetSupplicantStatistics()
Summary
Read the statistical information regarding the operation of the Supplicant associated with the Port.
Prototype
typedef
(EFIAPI *EFI_EAP_GET_SUPPLICANT_STATISTICS) (
OUT EFI_EAPOL_SUPPLICANT_PAE_STATISTICS *Statistics
);
Statistics Returns the statistical information regarding the operation of the Supplicant for the Port. Type
EFI_EAPOL_SUPPLICANT_PAE_STATISTICS is deﬁned in “Related Deﬁnitions”.
27.2. EAP Protocol 1043Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// Supplicant Statistics (IEEE Std 802.1X Section 9.5.2)
//
typedef struct _EFI_EAPOL_SUPPLICANT_PAE_STATISTICS {
UINTN EapolFramesReceived;
UINTN EapolFramesTransmitted;
UINTN EapolStartFramesTransmitted;
UINTN EapolLogoffFramesTransmitted;
UINTN EapRespIdFramesTransmitted;
UINTN EapResponseFramesTransmitted;
UINTN EapReqIdFramesReceived;
UINTN EapRequestFramesReceived;
UINTN InvalidEapolFramesReceived;
UINTN EapLengthErrorFramesReceived;
UINTN LastEapolFrameVersion;
UINTN LastEapolFrameSource;
} EFI_EAPOL_SUPPLICANT_PAE_STATISTICS;
EapolFramesReceived The number of EAPOL frames of any type that have been received by this Supplicant.
EapolFramesTransmitted The number of EAPOL frames of any type that have been transmitted by this Supplicant.
EapolStartFramesTransmitted The number of EAPOL Start frames that have been transmitted by this Supplicant.
EapolLogoffFramesTransmitted The number of EAPOL Logoff frames that have been transmitted bythis Suppli-
cant.
EapRespIdFramesTransmitted The number of EAP Resp/Id frames that have been transmitted by this Supplicant.
EapResponseFramesTransmitted The number of valid EAP Response frames (other than Resp/Id frames) that have
been transmitted by this Supplicant.
EapReqIdFramesReceived The number of EAP Req/Id frames that have been received by this Supplicant.
EapRequestFramesReceived The number of EAP Request frames (other than Rq/Id frames) that have been received
by this Supplicant.
InvalidEapolFramesReceived The number of EAPOL frames that have been received by this Supplicant in which
the frame type is not recognized.
EapLengthErrorFramesReceived The number of EAPOL frames that have been received by this Supplicant in
which the Packet Body Length ﬁeld (7.5.5) is invalid.

cant.
LastEapolFrameVersion The protocol version number carried in the most recently received EAPOL frame.
LastEapolFrameSource The source MAC address carried in the most recently received EAPOL frame.
TheGetSupplicantStatistics() function reads the statistical information Statistics regarding the operation of the Sup-
plicant associated with the Port.
IfStatistics isNULL, then EFI_INVALID_PARAMETER is returned.
EFI_SUCCESS The statistical information regarding the operation of the Supplicant for the
Port is read successfully.
EFI_INV ALID_PARAMETER Statistics isNULL.
27.2. EAP Protocol 1044Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.2.14 EFI EAP Management2 Protocol
27.2.14.1 EFI_EAP_MANAGEMENT2_PROTOCOL
Summary
This protocol provides the ability to conﬁgure and control EAPOL state machine, and retrieve the information, status
and the statistics information of EAPOL state machine.
GUID
#define EFI_EAP_MANAGEMENT2_PROTOCOL_GUID \
{ 0x5e93c847, 0x456d, 0x40b3, \
{ 0xa6, 0xb4, 0x78, 0xb0, 0xc9, 0xcf, 0x7f, 0x20 }}
typedef struct _EFI_EAP_MANAGEMENT2_PROTOCOL {
...... // Same asEFI_EAP_MANAGEMENT_PROTOCOL
EFI_EAP_GET_KEY GetKey;
} EFI_EAP_MANAGMENT2_PROTOCOL;
GetKey Provide Key information parsed from EAP packet. See the GetKey() function description.
TheEFI_EAP_MANAGEMENT2_PROTOCOL is used to control, conﬁgure and monitor EAPOL state machine on a
Port, and return information of the Port. EAPOL state machine is built on a per-Port basis. Herein, a Port means a
NIC. For the details of EAPOL, please refer to IEEE 802.1x speciﬁcation.
27.2.15 EFI_EAP_MANAGEMENT2_PROTOCOL.GetKey()
Summary
Return key generated through EAP process.
Prototype
typedef
(EFIAPI *EFI_EAP_GET_KEY)(
IN EFI_EAP_MANAGEMENT2_PROTOCOL *This,
IN OUT UINT8 *Msk,
IN OUT UINTN *MskSize,
IN OUT UINT8 *Emsk,
IN OUT UINT8 *EmskSize
);
This Pointer to the EFI_EAP_MANAGEMENT2_PROTOCOL instance.
Msk Pointer to MSK (Master Session Key) buffer.
MskSize MSK buffer size.
Emsk Pointer to EMSK (Extended Master Session Key) buffer.
EmskSize EMSK buffer size.
27.2. EAP Protocol 1045Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheGetKey() function return the key generated through EAP process, so that the 802.11 MAC layer driver can use
MSK to derive more keys, e.g. PMK (Pairwise Master Key).
•Msk is NULL.
•MskSize is NULL.
•Emsk is NULL.
•EmskSize is NULL.
EFI_NOT_READY MSK and EMSK are not generated in current session yet.
27.2.16 EFI EAP Conﬁguration Protocol
27.2.16.1 EFI_EAP_CONFIGURATION_PROTOCOL
Summary
This protocol provides a way to set and get EAP conﬁguration.
GUID
#define EFI_EAP_CONFIGURATION_PROTOCOL_GUID \
{ 0xe5b58dbb, 0x7688, 0x44b4, \
{ 0x97, 0xbf, 0x5f, 0x1d, 0x4b, 0x7c, 0xc8, 0xdb }}
typedef struct _EFI_EAP_CONFIGURATION_PROTOCOL {
EFI_EAP_CONFIGURATION_SET_DATA SetData;
EFI_EAP_CONFIGURATION_GET_DATA GetData;
} EFI_EAP_CONFIGURATION_PROTOCOL;
SetData Set EAP conﬁguration data. See the SetData() function description.
GetData Get EAP conﬁguration data. See the GetData() function description.
TheEFI_EAP_CONFIGURATION_PROTOCOL is designed to provide a way to set and get EAP conﬁguration, such
as Certiﬁcate, private key ﬁle.
27.2. EAP Protocol 1046Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.2.17 EFI_EAP_CONFIGURATION_PROTOCOL.SetData()
Summary
Set EAP conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_EAP_CONFIGURATION_SET_DATA)(
IN EFI_EAP_CONFIGURATION_PROTOCOL *This,
IN EFI_EAP_TYPE EapType,
IN EFI_EAP_CONFIG_DATA_TYPE DataType,
IN UINTN DataSize
);
This Pointer to the EFI_EAP_CONFIGURATION_PROTOCOL instance.
EapType EAP type. See EFI_EAP_TYPE.
DataType Conﬁguration data type. See EFI_EAP_CONFIG_DATA_TYPE
Data Pointer to conﬁguration data.
DataSize Total size of conﬁguration data.
TheSetData() function sets EAP conﬁguration to non-volatile storage or volatile storage.
//
// Make sure it notconflict withany real EapTypeXXX
//
#define EFI_EAP_TYPE_ATTRIBUTE 0
// EFI_EAP_TYPE_ATTRIBUTE
EfiEapConfigEapAuthMethod,
EfiEapConfigEapSupportedAuthMethod,
// EapTypeIdentity
EfiEapConfigIdentityString,
// EapTypeEAPTLS/EapTypePEAP
EfiEapConfigEapTlsCACert,
EfiEapConfigEapTlsClientCert,
EfiEapConfigEapTlsClientPrivateKeyFile,
EfiEapConfigEapTlsClientPrivateKeyFilePassword,\\
// ASCII format, Volatile
EfiEapConfigEapTlsCipherSuite,
EfiEapConfigEapTlsSupportedCipherSuite,
// EapTypeMSChapV2
EfiEapConfigEapMSChapV2Password, // UNICODE format, Volatile
// EapTypePEAP
EfiEapConfigEap2ndAuthMethod,
// More...
} EFI_EAP_CONFIG_DATA_TYPE;
27.2. EAP Protocol 1047Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// EFI_EAP_TYPE
//
typedef UINT8 EFI_EAP_TYPE;
#define EFI_EAP_TYPE_IDENTITY 1
#define EFI_EAP_TYPE_NOTIFICATION 2
#define EFI_EAP_TYPE_NAK 3
#define EFI_EAP_TYPE_MD5CHALLENGE 4
#define EFI_EAP_TYPE_OTP 5
#define EFI_EAP_TYPE_GTC 6
#define EFI_EAP_TYPE_EAPTLS 13
#define EFI_EAP_TYPE_EAPSIM 18
#define EFI_EAP_TYPE_TTLS 21
#define EFI_EAP_TYPE_PEAP 25
#define EFI_EAP_TYPE_MSCHAPV2 26
#define EFI_EAP_TYPE_EAP_EXTENSION 33
......
EFI_SUCCESS The EAP conﬁguration data is set successfully.
EFI_UNSUPPORTED TheEapType orDataType is unsupported.
EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
27.2.18 EFI_EAP_CONFIGURATION_PROTOCOL.GetData()
Summary
Get EAP conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_EAP_CONFIGURATION_GET_DATA)(
IN OUT UINTN *DataSize
);
27.2. EAP Protocol 1048Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DataSize Total size of conﬁguration data. On input, it means the size of Data * buffer. On output, it
means the size of copied *Data buffer if EFI_SUCCESS, and means the size of desired Data buffer if
EFI_BUFFER_TOO_SMALL.
TheGetData() function gets EAP conﬁguration.
EFI_SUCCESS The EAP conﬁguration data is got successfully.
EFI_NOT_FOUND The EAP conﬁguration data is not found.
27.3 EFI Wireless MAC Connection Protocol
27.3.1 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL
Summary
This protocol provides management service interfaces of 802.11 MAC layer. It is used by network applications (and
drivers) to establish wireless connection with an access point (AP).
GUID
#define EFI_WIRELESS_MAC_CONNECTION_PROTOCOL_GUID \
{ 0xda55bc9, 0x45f8, 0x4bb4, \
{ 0x87, 0x19, 0x52, 0x24, 0xf1, 0x8a, 0x4d, 0x45 }}
typedef struct _EFI_WIRELESS_MAC_CONNECTION_PROTOCOL {
EFI_WIRELESS_MAC_CONNECTION_SCAN Scan;
EFI_WIRELESS_MAC_CONNECTION_ASSOCIATE Associate;
EFI_WIRELESS_MAC_CONNECTION_DISASSOCIATE Disassociate;
EFI_WIRELESS_MAC_CONNECTION_AUTHENTICATE Authenticate;
EFI_WIRELESS_MAC_CONNECTION_DEAUTHENTICATE Deauthenticate;
} EFI_WIRELESS_MAC_CONNECTION_PROTOCOL;
Scan Determine the characteristics of the available BSSs. See the Scan() function description.
Associate Places an association request with a speciﬁc peer MAC entity. See the Associate() function description.
Disassociate Reports a disassociation with a speciﬁc peer MAC entity. See the Disassociate() function description.
Authenticate Requests authentication with a speciﬁc peer MAC entity. See the Authenticate() function description.
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Deauthenticate Invalidates an authentication relationship with a peer MAC entity. See the Deauthenticate() function
TheEFI_WIRELESS_MAC_CONNECTION_PROTOCOL is designed to provide management service interfaces for
the EFI wireless network stack to establish wireless connection with AP. An EFI Wireless MAC Connection Protocol
instance will be installed on each communication device that the EFI wireless network stack runs on.
27.3.2 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Scan()
Summary

Summary
Request a survey of potential BSSs that administrator can later elect to try to join.
Prototype
typedef
(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_SCAN)(
IN EFI_WIRELESS_MAC_CONNECTION_PROTOCOL *This,
IN EFI_80211_SCAN_DATA_TOKEN *Data
);
This Pointer to the EFI_WIRELESS_MAC_CONNECTION_PROTOCOL
Data Pointer to the scan token. Type EFI_80211_SCAN_DATA_TOKEN is deﬁned in “Related Deﬁnitions” below.
TheScan() function returns the description of the set of BSSs detected by the scan process. Passive scan operation is
performed by default.
// EFI_80211_SCAN_DATA_TOKEN
EFI_80211_SCAN_DATA *Data;
EFI_80211_SCAN_RESULT_CODE ResultCode;
EFI_80211_SCAN_RESULT *Result;
} EFI_80211_SCAN_DATA_TOKEN;
Event This Event will be signaled after the Status ﬁeld is updated by the EFI Wireless MAC Connection Protocol
driver. The type of Event must be EFI_NOTIFY_SIGNAL.
Status Will be set to one of the following values:
EFI_SUCCESS : Scan operation completed successfully.
EFI_NOT_FOUND : Failed to ﬁnd available BSS.
EFI_DEVICE_ERROR : An unexpected network or system error occurred.
EFI_ACCESS_DENIED : The scan operation is not completed due to some underlying hardware or software
state.
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EFI_NOT_READY : The scan operation is started but not yet completed.
Data Pointer to the scan data. Type EFI_80211_SCAN_DATA is deﬁned below.
ResultCode Indicates the scan state. Type EFI_80211_SCAN_RESULT_CODE is deﬁned below.
Result Indicates the scan result. It is caller’s responsibility to free this buffer. Type EFI_80211_SCAN_RESULT is
TheEFI_80211_SCAN_DATA_TOKEN structure is deﬁned to support the process of determining the characteristics of
the available BSSs. As input, the Data ﬁeld must be ﬁlled in by the caller of EFI Wireless MAC Connection Protocol.
After the scan operation completes, the EFI Wireless MAC Connection Protocol driver updates the Status, ResultCode
andResult ﬁeld and the Event is signaled.
// EFI_80211_SCAN_DATA
EFI_80211_BSS_TYPE BSSType;
EFI_80211_MAC_ADDRESS BSSId;
UINT8 SSIdLen;
UINT8 *SSId;
BOOLEAN PassiveMode;
UINT32 ProbeDelay;
UINT32 *ChannelList;
UINT32 MinChannelTime;
UINT32 MaxChannelTime;
EFI_80211_ELEMENT_REQ *RequestInformation;
EFI_80211_ELEMENT_SSID *SSIDList;
EFI_80211_ACC_NET_TYPE AccessNetworkType;
UINT8 *VendorSpecificInfo;
} EFI_80211_SCAN_DATA;
BSSType Determines whether infrastructure BSS, IBSS, MBSS, or all, are included in the scan. Type
EFI_80211_BSS_TYPE is deﬁned below.
BSSId Indicates a speciﬁc or wildcard BSSID. Use all binary 1s to represent all SSIDs. Type
EFI_80211_MAC_ADDRESS is deﬁned below.
SSIdLen Length in bytes of the SSId. If zero, ignore the SSId ﬁeld.
SSId Speciﬁes the desired SSID or the wildcard SSID. Use NULL to represent all SSIDs.
PassiveMode Indicates passive scanning if TRUE.
ProbeDelay The delay in microseconds to be used prior to transmitting a Probe frame during active scanning. If zero,
the value can be overridden by an implementation-dependent default value.
ChannelList Speciﬁes a list of channels that are examined when scanning for a BSS. If set to NULL, all valid channels
will be scanned.
MinChannelTime Indicates the minimum time in TU to spend on each channel when scanning. If zero, the value
can be overridden by an implementation-dependent default value.
MaxChannelTime Indicates the maximum time in TU to spend on each channel when scanning. If zero, the value
RequestInformation Points to an optionally present element. This is an optional parameter and may be NULL. Type
EFI_80211_ELEMENT_REQ is deﬁned below.
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SSIDList Indicates one or more SSID elements that are optionally present. This is an optional parameter and may be
NULL. Type EFI_80211_ELEMENT_SSID is deﬁned below.
AccessNetworkType Speciﬁes a desired speciﬁc access network type or the wildcard access network type. Use 15 as
wildcard access network type. Type EFI_80211_ACC_NET_TYPE is deﬁned below.
VendorSpeciﬁcInfo Speciﬁes zero or more elements. This is an optional parameter and may be NULL.
// EFI_80211_BSS_TYPE
IeeeInfrastructureBSS,
IeeeIndependentBSS,
IeeeMeshBSS,
IeeeAnyBss
} EFI_80211_BSS_TYPE;
The EFI_80211_BSS_TYPE is deﬁned to enumerate BSS type.
// EFI_80211_MAC_ADDRESS
UINT8 Addr[6];
} EFI_80211_MAC_ADDRESS;
The EFI_80211_MAC_ADDRESS is deﬁned to record a 48-bit MAC address.
// EFI_80211_ELEMENT_REQ
EFI_80211_ELEMENT_HEADER Hdr;
UINT8 RequestIDs[1];
} EFI_80211_ELEMENT_REQ;
Hdr Common header of an element. Type EFI_80211_ELEMENT_HEADER is deﬁned below.
RequestIDs Start of elements that are requested to be included in the Probe Response frame. The elements are listed
in order of increasing element ID.
// EFI_80211_ELEMENT_HEADER
UINT8 ElementID;
} EFI_80211_ELEMENT_HEADER;
ElementID A unique element ID deﬁned in IEEE 802.11 speciﬁcation.
Length Speciﬁes the number of octets in the element body.
// EFI_80211_ELEMENT_SSID
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UINT8 SSId [32];
} EFI_80211_ELEMENT_SSID;
Hdr Common header of an element.
SSId Service set identiﬁer. If Hdr.Length is zero, this ﬁeld is ignored.
// EFI_80211_ACC_NET_TYPE
IeeePrivate = 0,
IeeePrivatewithGuest = 1,
IeeeChargeablePublic = 2,
IeeeFreePublic = 3,
IeeePersonal = 4,
IeeeEmergencyServOnly = 5,
IeeeTestOrExp = 14,
IeeeWildcard = 15
} EFI_80211_ACC_NET_TYPE;
TheEFI_80211_ACC_NET_TYPE records access network types deﬁned in IEEE 802.11 speciﬁcation.
// EFI_80211_SCAN_RESULT_CODE
ScanSuccess,
ScanNotSupported
} EFI_80211_SCAN_RESULT_CODE;
ScanSuccess The scan operation ﬁnished successfully.
ScanNotSupported The scan operation is not supported in current implementation.
// EFI_80211_SCAN_RESULT
UINTN NumOfBSSDesp;
EFI_80211_BSS_DESCRIPTION **BSSDespSet;
UINTN NumofBSSDespFromPilot;
EFI_80211_BSS_DESP_PILOT **BSSDespFromPilotSet;
} EFI_80211_SCAN_RESULT;
NumOfBSSDesp The number of EFI_80211_BSS_DESCRIPTION in BSSDespSet. If zero, BSSDespSet should be
ignored.
BSSDespSet Points to zero or more instances of EFI_80211_BSS_DESCRIPTION. Type
EFI_80211_BSS_DESCRIPTION is deﬁned below.
NumOfBSSDespFromPilot The number of EFI_80211_BSS_DESP_PILOT in BSSDespFromPilotSet. If zero,
BSSDespFromPilotSet should be ignored.
BSSDespFromPilotSet Points to zero or more instances of EFI_80211_BSS_DESP_PILOT. Type
EFI_80211_BSS_DESP_PILOT is deﬁned below.
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// EFI_80211_BSS_DESCRIPTION
EFI_80211_MAC_ADDRESS *BSSId;
UINT16 BeaconPeriod;
UINT64 Timestamp;
UINT16 CapabilityInfo;
UINT8 *BSSBasicRateSet;
UINT8 *OperationalRateSet;
EFI_80211_ELEMENT_COUNTRY *Country;
EFI_80211_ELEMENT_RSN RSN;
UINT8 RCPIMeasurement;
UINT8 RSNIMeasurement;
UINT8 *RequestedElements;
UINT8 *BSSMembershipSelectorSet;
EFI_80211_ELEMENT_EXT_CAP *ExtCapElement;
} EFI_80211_BSS_DESCRIPTION;
BSSId Indicates a speciﬁc BSSID of the found BSS.
SSId Speciﬁes the SSID of the found BSS. If NULL, ignore SSIdLen ﬁeld.
SSIdLen Length in bytes of the SSId. If zero, ignore SSId ﬁeld.
BSSType Speciﬁes the type of the found BSS.

BeaconPeriod The beacon period in TU of the found BSS.
Timestamp The timestamp of the received frame from the found BSS.
CapabilityInfo The advertised capabilities of the BSS.
BSSBasicRateSet The set of data rates that shall be supported by all STAs that desire to join this BSS.
OperationalRateSet The set of data rates that the peer STA desires to use for communication within the BSS.
Country The information required to identify the regulatory domain in which the peer STA is located. Type
EFI_80211_ELEMENT_COUNTRY is deﬁned below.
RSN The cipher suites and AKM suites supported in the BSS. Type EFI_80211_ELEMENT_RSN is deﬁned below.
RSSI Speciﬁes the RSSI of the received frame.
RCPIMeasurement Speciﬁes the RCPI of the received frame.
RSNIMeasurement Speciﬁes the RSNI of the received frame.
RequestedElements Speciﬁes the elements requested by the request element of the Probe Request frame. This is an
optional parameter and may be NULL.
BSSMembershipSelectorSet Speciﬁes the BSS membership selectors that represent the set of features that shall be
supported by all STAs to join this BSS.
ExtCapElement Speciﬁes the parameters within the Extended Capabilities element that are supported by the MAC
entity. This is an optional parameter and may be NULL. Type EFI_80211_ELEMENT_EXT_CAP is deﬁned
below.
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// EFI_80211_ELEMENT_COUNTRY
UINT8 CountryStr [3];
EFI_80211_COUNTRY_TRIPLET CountryTriplet[1];
} EFI_80211_ELEMENT_COUNTRY;
CountryStr Speciﬁes country strings in 3 octets.
CountryTriplet Indicates a triplet that repeated in country element. The number of triplets is determined by the
Hdr.Length ﬁeld.
// EFI_80211_COUNTRY_TRIPLET
EFI_80211_COUNTRY_TRIPLET_SUBBAND Subband;
EFI_80211_COUNTRY_TRIPLET_OPERATE Operating;
} EFI_80211_COUNTRY_TRIPLET;
Subband The subband triplet.
Operating The operating triplet.
// EFI_80211_COUNTRY_TRIPLET_SUBBAND
UINT8 FirstChannelNum;
UINT8 NumOfChannels;
UINT8 MaxTxPowerLevel;
} EFI_80211_COUNTRY_TRIPLET_SUBBAND;
FirstChannelNum Indicates the lowest channel number in the subband. It has a positive integer value less than 201.
NumOfChannels Indicates the number of channels in the subband.
MaxTxPowerLevel Indicates the maximum power in dBm allowed to be transmitted.
// EFI_80211_COUNTRY_TRIPLET_OPERATE
UINT8 OperatingExtId;
UINT8 OperatingClass;
UINT8 CoverageClass;
} EFI_80211_COUNTRY_TRIPLET_OPERATE;
OperatingExtId Indicates the operating extension identiﬁer. It has a positive integer value of 201 or greater.
OperatingClass Index into a set of values for radio equipment set of rules.
CoverageClass Speciﬁes an AirPropagationTime characteristics used in BSS operation. Refer the deﬁnition of an
AirPropagationTime in IEEE 802.11 speciﬁcation.
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// EFI_80211_ELEMENT_RSN
EFI_80211_ELEMENT_DATA_RSN *Data;
} EFI_80211_ELEMENT_RSN;
Data Points to RSN element. Type EFI_80211_ELEMENT_DATA_RSN is deﬁned below. The size of a RSN element
is limited to 255 octets.
// EFI_80211_ELEMENT_DATA_RSN
UINT32 GroupDataCipherSuite;
//UINT16 PairwiseCipherSuiteCount;
//UINT32 PairwiseCipherSuiteList [PairwiseCipherSuiteCount];
//UINT16 AKMSuiteCount;
//UINT32 AKMSuiteList [AKMSuiteCount];
//UINT16 RSNCapabilities;
//UINT16 PMKIDCount;
//UINT8 PMKIDList [PMKIDCount][16];
//UINT32 GroupManagementCipherSuite;
} EFI_80211_ELEMENT_DATA_RSN;
Version Indicates the version number of the RSNA protocol. Value 1 is deﬁned in current IEEE 802.11 speciﬁcation.
GroupDataCipherSuite Speciﬁes the cipher suite selector used by the BSS to protect group address frames.
PairwiseCipherSuiteCount Indicates the number of pairwise cipher suite selectors that are contained in PairwiseCi-
pherSuiteList.
PairwiseCipherSuiteList Contains a series of cipher suite selectors that indicate the pairwise cipher suites contained
in this element.
AKMSuiteCount Indicates the number of AKM suite selectors that are contained in AKMSuiteList.
AKMSuiteList Contains a series of AKM suite selectors that indicate the AKM suites contained in this element.
RSNCapabilities Indicates requested or advertised capabilities.
PMKIDCount Indicates the number of PKMIDs in the PMKIDList.
PMKIDList Contains zero or more PKMIDs that the STA believes to be valid for the destination AP.
GroupManagementCipherSuite Speciﬁes the cipher suite selector used by the BSS to protect group addressed ro-
bust management frames.
// EFI_80211_ELEMENT_EXT_CAP
UINT8 Capabilities[1];
} EFI_80211_ELEMENT_EXT_CAP;
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Capabilities Indicates the capabilities being advertised by the STA transmitting the element. This is a bit ﬁeld with
variable length. Refer to IEEE 802.11 speciﬁcation for bit value.
// EFI_80211_BSS_DESP_PILOT
UINT8 ConCapInfo;
UINT8 ConCountryStr[2];
UINT8 Channel;
EFI_80211_MULTIPLE_BSSID *MultipleBSSID;
} EFI_80211_BSS_DESP_PILOT;
ConCapInfo One octet ﬁeld to report condensed capability information.
ConCountryStr Two octet’s ﬁeld to report condensed country string.
OperatingClass Indicates the operating class value for the operating channel.
Channel Indicates the operating channel.
Interval Indicates the measurement pilot interval in TU.
MultipleBSSID Indicates that the BSS is within a multiple BSSID set.
// EFI_80211_MULTIPLE_BSSID
UINT8 Indicator;
EFI_80211_SUBELEMENT_INFO SubElement[1];
} EFI_80211_MULTIPLE_BSSID;
Indicator Indicates the maximum number of BSSIDs in the multiple BSSID set. When Indicator is set to n, 2n is the
maximum number.
SubElement Contains zero or more sub-elements. Type EFI_80211_SUBELEMENT_INFO is deﬁned below.
// EFI_80211_SUBELEMENT_INFO
UINT8 SubElementID;
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UINT8 Data[1];
} EFI_80211_SUBELEMENT_INFO;
SubElementID Indicates the unique identiﬁer within the containing element or sub-element.
Length Speciﬁes the number of octets in the Data ﬁeld.
Data A variable length data buffer.
•This is NULL.
•Data ->Data is NULL.
EFI_UNSUPPORTED One or more of the input parameters are not supported by this implementa-
tion.
EFI_ALREADY_STARTED The scan operation is already started.
27.3.3 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Associate()
Summary
Request an association with a speciﬁed peer MAC entity that is within an AP.
Prototype
typedef
(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_ASSOCIATE)(
IN EFI_80211_ASSOCIATE_DATA_TOKEN *Data
);
This Pointer to the EFI_WIRELESS_MAC_CONNECTION_PROTOCOL instance.
Data Pointer to the association token. Type EFI_80211_ASSOCIATE_DATA_TOKEN is deﬁned in Related Deﬁni-
tions below.
TheAssociate() function provides the capability for MAC layer to become associated with an AP.

tion.
Summary
Prototype
typedef
);
// EFI_80211_ASSOCIATE_DATA_TOKEN
EFI_80211_ASSOCIATE_DATA Data;
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EFI_80211_ASSOCIATE_RESULT_CODE ResultCode;
EFI_80211_ASSOCIATE_RESULT Result;
} EFI_80211_ASSOCIATE_DATA_TOKEN;
Status Will be set to one of the following values: EFI_SUCCESS: Association operation completed successfully.
EFI_DEVICE_ERROR: An unexpected network or system error occurred.
Data Pointer to the association data. Type EFI_80211_ASSOCIATE_DATA is deﬁned below.
ResultCode Indicates the association state. Type EFI_80211_ASSOCIATE_RESULT_CODE is deﬁned below.
Result Indicates the association result. It is caller’s responsibility to free this buffer. Type
EFI_80211_ASSOCIATE_RESULT* is deﬁned below.
The EFI_80211_ASSOCIATE_DATA_TOKEN structure is deﬁned to support the process of association with a speci-
ﬁed AP. As input, the Data ﬁeld must be ﬁlled in by the caller of EFI Wireless MAC Connection Protocol. After the
association operation completes, the EFI Wireless MAC Connection Protocol driver updates the Status, ResultCode
// EFI_80211_ASSOCIATE_DATA
UINT32 FailureTimeout;
UINT32 ListenInterval;
EFI_80211_ELEMENT_SUPP_CHANNEL *Channels;
EFI_80211_ELEMENT_EXT_CAP ExtCapElement;
} EFI_80211_ASSOCIATE_DATA;
BSSId Speciﬁes the address of the peer MAC entity to associate with.
CapabilityInfo Speciﬁes the requested operational capabilities to the AP in 2 octets.
FailureTimeout Speciﬁes a time limit in TU, after which the associate procedure is terminated.
ListenInterval Speciﬁes if in power save mode, how often the STA awakes and listens for the next beacon frame in
TU.
Channels Indicates a list of channels in which the STA is capable of operating. Type
EFI_80211_ELEMENT_SUPP_CHANNEL is deﬁned below.
RSN The cipher suites and AKM suites selected by the STA.
entity. This is an optional parameter and may be NULL.
// EFI_80211_ELEMENT_SUPP_CHANNEL
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EFI_80211_ELEMENT_SUPP_CHANNEL_TUPLE Subband[1];
} EFI_80211_ELEMENT_SUPP_CHANNEL;
Subband Indicates one or more tuples of (ﬁrst channel, number of channels). Type
EFI_80211_ELEMENT_SUPP_CHANNEL_TUPLE is deﬁned below.
// EFI_80211_ELEMENT_SUPP_CHANNEL_TUPLE
UINT8 FirstChannelNumber;
UINT8 NumberOfChannels;
} EFI_80211_ELEMENT_SUPP_CHANNEL_TUPLE;
FirstChannelNumber The ﬁrst channel number in a subband of supported channels.
NumberOfChannels The number of channels in a subband of supported channels.
// EFI_80211_ASSOCIATE_RESULT_CODE
AssociateSuccess,
AssociateRefusedReasonUnspecified,
AssociateRefusedCapsMismatch,
AssociateRefusedExtReason,
AssociateRefusedAPOutOfMemory,
AssociateRefusedBasicRatesMismatch,
AssociateRejectedEmergencyServicesNotSupported,
AssociateRefusedTemporarily
} EFI_80211_ASSOCIATE_RESULT_CODE;
TheEFI_80211_ASSOCIATE_RESULT_CODE records the result responses to the association request, which are de-
ﬁned in IEEE 802.11 speciﬁcation.
// EFI_80211_ASSOCIATE_RESULT
UINT16 AssociationID;
UINT8 RCPIValue;
UINT8 RSNIValue;
EFI_80211_ELEMENT_TIMEOUT_VAL TimeoutInterval;
} EFI_80211_ASSOCIATE_RESULT;
BSSId Speciﬁes the address of the peer MAC entity from which the association request was received.
CapabilityInfo Speciﬁes the operational capabilities advertised by the AP.
AssociationID Speciﬁes the association ID value assigned by the AP.
RCPIValue Indicates the measured RCPI of the corresponding association request frame. It is an optional parameter
and is set to zero if unavailable.
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RSNIValue Indicates the measured RSNI at the time the corresponding association request frame was received. It is
an optional parameter and is set to zero if unavailable.
TimeoutInterval Speciﬁes the timeout interval when the result code is AssociateRefusedTemporarily .
// EFI_80211_ELEMENT_TIMEOUT_VAL
UINT32 Value;
} EFI_80211_ELEMENT_TIMEOUT_VAL;
Type Speciﬁes the timeout interval type.
Value Speciﬁes the timeout interval value.
tion.
EFI_ALREADY_STARTED The association process is already started.
EFI_NOT_READY Authentication is not performed before this association process.
EFI_NOT_FOUND The speciﬁed peer MAC entity is not found.
27.3.4 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Disassociate()
Summary
Request a disassociation with a speciﬁed peer MAC entity.
Prototype
typedef
(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_DISASSOCIATE)(
IN EFI_80211_DISASSOCIATE_DATA_TOKEN *Data
);
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Data Pointer to the disassociation token. Type EFI_80211_DISASSOCIATE_DATA_TOKEN is deﬁned in Related
Deﬁnitions below.
TheDisassociate() function is invoked to terminate an existing association. Disassociation is a notiﬁcation and cannot
be refused by the receiving peer except when management frame protection is negotiated and the message integrity
check fails.
// EFI_80211_DISASSOCIATE_DATA_TOKEN
EFI_80211_DISASSOCIATE_DATA *Data;
EFI_80211_DISASSOCIATE_RESULT_CODE ResultCode;
} EFI_80211_DISASSOCIATE_DATA_TOKEN;
EFI_SUCCESS: Disassociation operation completed successfully.
EFI_ACCESS_DENIED: The disassociation operation is not completed due to some underlying hardware or
software state.
EFI_NOT_READY: The disassociation operation is started but not yet completed.
Data Pointer to the disassociation data. Type EFI_80211_DISASSOCIATE_DATA is deﬁned below.
ResultCode Indicates the disassociation state. Type EFI_80211_DISASSOCIATE_RESULT_CODE is deﬁned be-
low.
// EFI_80211_DISASSOCIATE_DATA
EFI_80211_REASON_CODE ReasonCode;
} EFI_80211_DISASSOCIATE_DATA;
BSSId Speciﬁes the address of the peer MAC entity with which to perform the disassociation process.

low.
ReasonCode Speciﬁes the reason for initiating the disassociation process.
VendorSpeciﬁcInfo Zero or more elements, may be NULL.
// EFI_80211_REASON_CODE
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Ieee80211UnspecifiedReason = 1,
Ieee80211PreviousAuthenticateInvalid = 2,
Ieee80211DeauthenticatedSinceLeaving = 3,
Ieee80211DisassociatedDueToInactive = 4,
Ieee80211DisassociatedSinceApUnable = 5,
Ieee80211Class2FrameNonauthenticated = 6,
Ieee80211Class3FrameNonassociated = 7,
Ieee80211DisassociatedSinceLeaving = 8,
// ...
} EFI_80211_REASON_CODE;
Note :The reason codes are deﬁned in chapter 8.4.1.7 Reason Code ﬁeld, IEEE 802.11-2012.
// EFI_80211_DISASSOCIATE_RESULT_CODE
DisassociateSuccess,
DisassociateInvalidParameters
} EFI_80211_DISASSOCIATE_RESULT_CODE;
DisassociateSuccess Disassociation process completed successfully.
DisassociateInvalidParameters Disassociation failed due to any input parameter is invalid.
EFI_ALREADY_STARTED The disassociation process is already started.
EFI_NOT_READY The disassociation service is invoked to a nonexistent association relation-
ship.
27.3.5 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Authenticate()
Summary
Request the process of establishing an authentication relationship with a peer MAC entity.
Prototype
typedef
(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_AUTHENTICATE)(
IN EFI_80211_AUTHENTICATE_DATA_TOKEN *Data
);
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Data Pointer to the authentication token. Type EFI_80211_AUTHENTICATE_DATA_TOKEN is deﬁned in Related
The Authenticate() function requests authentication with a speciﬁed peer MAC entity. This service might be time-
consuming thus is designed to be invoked independently of the association service.
// EFI_80211_AUTHENTICATE_DATA_TOKEN
EFI_80211_AUTHENTICATE_DATA *Data;
EFI_80211_AUTHENTICATE_RESULT_CODE ResultCode;
EFI_80211_AUTHENTICATE_RESULT Result;
} EFI_80211_AUTHENTICATE_DATA_TOKEN;
EFI_PROTOCOL_ERROR: Peer MAC entity rejects the authentication.
EFI_NO_RESPONSE: Peer MAC entity does not response the authentication request.
EFI_ACCESS_DENIED: The authentication operation is not completed due to some underlying hardware or
EFI_NOT_READY: The authentication operation is started but not yet completed.
Data Pointer to the authentication data. Type EFI_80211_AUTHENTICATE_DATA is deﬁned below.
ResultCode Indicates the association state. Type EFI_80211_AUTHENTICATE_RESULT_CODE is deﬁned below.
EFI_80211_AUTHENTICATE_RESULT is deﬁned below.
// EFI_80211_AUTHENTICATION_DATA
EFI_80211_AUTHENTICATION_TYPE AuthType;
UINT8 *FTContent;
UINT8 *SAEContent;
} EFI_80211_AUTHENTICATE_DATA;
BSSId Speciﬁes the address of the peer MAC entity with which to perform the authentication process.
27.3. EFI Wireless MAC Connection Protocol 1064Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
AuthType Speciﬁes the type of authentication algorithm to use during the authentication process.
FailureTimeout Speciﬁes a time limit in TU after which the authentication procedure is terminated.
FTContent Speciﬁes the set of elements to be included in the ﬁrst message of the FT authentication sequence, may
be NULL.
SAEContent Speciﬁes the set of elements to be included in the SAE Commit Message or SAE Conﬁrm Message,
may be NULL.
// EFI_80211_AUTHENTICATION_TYPE
OpenSystem,
SharedKey,
FastBSSTransition,
SAE
} EFI_80211_AUTHENTICATION_TYPE;
OpenSystem Open system authentication, admits any STA to the DS.
SharedKey Shared Key authentication relies on WEP to demonstrate knowledge of a WEP encryption key.
FastBSSTransition FT authentication relies on keys derived during the initial mobility domain association to authen-
ticate the stations.
SAE SAE authentication uses ﬁnite ﬁeld cryptography to prove knowledge of a shared password.
// EFI_80211_AUTHENTICATION_RESULT_CODE
AuthenticateSuccess,
AuthenticateRefused,
AuthenticateAnticLoggingTokenRequired,
AuthenticateFiniteCyclicGroupNotSupported,
AuthenticationRejected,
AuthenticateInvalidParameter
} EFI_80211_AUTHENTICATE_RESULT_CODE;
The result code indicates the result response to the authentication request from the peer MAC entity.
// EFI_80211_AUTHENTICATION_RESULT
} EFI_80211_AUTHENTICATE_RESULT;
BSSId Speciﬁes the address of the peer MAC entity from which the authentication request was received.
FTContent Speciﬁes the set of elements to be included in the second message of the FT authentication sequence,
27.3. EFI Wireless MAC Connection Protocol 1065Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
•Data Data is NULL.
tion.
EFI_ALREADY_STARTED The authentication process is already started.
27.3.6 EFI_WIRELESS_MAC_CONNECTION_PROTOCOL.Deauthenticate()
Summary
Invalidate the authentication relationship with a peer MAC entity.
Prototype
typedef
(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_DEAUTHENTICATE)(
IN EFI_80211_DEAUTHENTICATE_DATA_TOKEN *Data
);
This Pointer to the EFI_WIRELESS_MAC_CONNECTION _PROTOCOL instance.
Data Pointer to the deauthentication token. Type EFI_80211_DEAUTHENTICATE_DATA_TOKEN is deﬁned in
Related Deﬁnitions below.
TheDeauthenticate() function requests that the authentication relationship with a speciﬁed peer MAC entity be invali-
dated. Deauthentication is a notiﬁcation and when it is sent out the association at the transmitting station is terminated.
// EFI_80211_DEAUTHENTICATE_DATA_TOKEN
EFI_80211_DEAUTHENTICATE_DATA *Data;
} EFI_80211_DEAUTHENTICATE_DATA_TOKEN;
27.3. EFI Wireless MAC Connection Protocol 1066Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS: Deauthentication operation completed successfully.
EFI_ACCESS_DENIED:The deauthentication operation is not completed due to some underlying hardware or

EFI_NOT_READY: The deauthentication operation is started but not yet completed.
Data Pointer to the deauthentication data. Type EFI_80211_DEAUTHENTICATE_DATA is deﬁned below.
// EFI_80211_DEAUTHENTICATE_DATA
} EFI_80211_DEAUTHENTICATE_DATA;
BSSId Speciﬁes the address of the peer MAC entity with which to perform the deauthentication process.
ReasonCode Speciﬁes the reason for initiating the deauthentication process.
EFI_ALREADY_STARTED The deauthentication process is already started.
EFI_NOT_READY The deauthentication service is invoked to a nonexistent association or au-
thentication relationship.
27.4 EFI Wireless MAC Connection II Protocol
This section provides a detailed description of EFI Wireless MAC Connection II Protocol.
27.4. EFI Wireless MAC Connection II Protocol 1067Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.4.1 EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL
Summary
The EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL provides network management service interfaces for
802.11 network stack. It is used by network applications (and drivers) to establish wireless connection with a wireless
network.
GUID
#define EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL_GUID \
{ 0x1b0fb9bf, 0x699d, 0x4fdd, \
{ 0xa7, 0xc3, 0x25, 0x46, 0x68, 0x1b, 0xf6, 0x3b }}
typedef struct _EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL {
EFI_WIRELESS_MAC_CONNECTION_II_GET_NETWORKS GetNetworks;
EFI_WIRELESS_MAC_CONNECTION_II_CONNECT_NETWORK ConnectNetwork;
EFI_WIRELESS_MAC_CONNECTION_II_DISCONNECT_NETWORK DisconnectNetwork;
} EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL;
GetNetworks Get a list of nearby detectable wireless network. See the GetNetworks() function description.
ConnectNetwork Places a connection request with a speciﬁc wireless network. See the ConnectNetwork() function
DisconnectNetwork Places a disconnection request with a speciﬁc wireless network. See the DisconnectNetwork()
The EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL is designed to provide management service inter-
faces for the EFI wireless network stack to establish relationship with a wireless network (identiﬁed by
EFI_80211_NETWORK deﬁned below). An EFI Wireless MAC Connection II Protocol instance will be installed
on each communication device that the EFI wireless network stack runs on.
27.4.2 EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL.GetNetworks()
Summary
Request a survey of potential wireless networks that administrator can later elect to try to join.
Prototype
typedef
(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_GET_NETWORKS)(
IN EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL *This,
IN EFI_80211_GET_NETWORKS_TOKEN *Token
);
This Pointer to the EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL instance.
Token Pointer to the token for getting wireless network. Type EFI_80211_GET_NETWORKS_TOKEN is deﬁned in
27.4. EFI Wireless MAC Connection II Protocol 1068Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheGetNetworks() function returns the description of a list of wireless networks detected by wireless UNDI driver.
This function is always non-blocking. If the operation succeeds or fails due to any error, the Token->Event will be
signaled and Token->Status will be updated accordingly. The caller of this function is responsible for inputting SSIDs
in case of searching hidden networks.
// EFI_80211_GET_NETWORKS_TOKEN
EFI_80211_GET_NETWORKS_DATA *Data;
EFI_80211_GET_NETWORKS_RESULT *Result;
} EFI_80211_GET_NETWORKS_TOKEN;
Event If the status code returned by GetNetworks() is EFI_SUCCESS, then this Event will be signaled after the
Status ﬁeld is updated by the EFI Wireless MAC Connection Protocol II driver. The type of Event must be
EFI_NOTIFY_SIGNAL.
EFI_SUCCESS: The operation completed successfully.
EFI_NOT_FOUND: Failed to ﬁnd available wireless networks.
EFI_ACCESS_DENIED: The operation is not completed due to some underlying hardware or software state.
EFI_NOT_READY: The operation is started but not yet completed.
Data Pointer to the input data for getting networks. Type EFI_80211_GET_NETWORKS_DATA is deﬁned below.
Result Indicates the scan result. It is caller’s responsibility to free this buffer. Type
EFI_80211_GET_NETWORKS_RESULT is deﬁned below.
// EFI_80211_GET_NETWORKS_DATA
UINT32 NumOfSSID;
EFI_80211_SSID SSIDList[1];
} EFI_80211_GET_NETWORKS_DATA;
NumOfSSID The number of EFI_80211_SSID in SSIDList. If zero, SSIDList should be ignored.
SSIDList The SSIDList is a pointer to an array of EFI_80211_SSID instances. The number of entries is speciﬁed by
NumOfSSID. The array should only include SSIDs of hidden networks. It is suggested that the caller inputs less
than 10 elements in the SSIDList. It is the caller’s responsibility to free this buffer. Type EFI_80211_SSID is
#define EFI_MAX_SSID_LEN 32
// EFI_80211_SSID
27.4. EFI Wireless MAC Connection II Protocol 1069Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT8 SSId[EFI_MAX_SSID_LEN];
} EFI_80211_SSID;
SSId Speciﬁes the service set identiﬁer.
// EFI_80211_GET_NETWORKS_RESULT
UINT8 NumOfNetworkDesc;
EFI_80211_NETWORK_DESCRIPTION NetworkDesc[1];
} EFI_80211_GET_NETWORKS_RESULT;
NumOfNetworkDesc The number of elements in NetworkDesc. If zero, NetworkDesc should be ignored.
NetworkDesc The NetworkDesc is a variable-length array of elements of type
EFI_80211_NETWORK_DESCRIPTION. Type EFI_80211_NETWORK_DESCRIPTION is deﬁned be-
low.
// EFI_80211_NETWORK_DESCRIPTION
EFI_80211_NETWORK Network;
UINT8 NetworkQuality;
} EFI_80211_NETWORK_DESCRIPTION;
Network Speciﬁes the found wireless network. Type EFI_80211_NETWORK is deﬁned below.
NetworkQuality Indicates the network quality as a value between 0 to 100, where 100 indicates the highest network
quality.
// EFI_80211_NETWORK
EFI_80211_SSID SSId;
EFI_80211_AKM_SUITE_SELECTOR *AKMSuite;
EFI_80211_CIPHER_SUITE_SELECTOR *CipherSuite;
} EFI_80211_NETWORK;
BSSType Speciﬁes the type of the BSS. Type EFI_80211_BSS_TYPE is deﬁned below.
SSId Speciﬁes the SSID of the BSS. Type EFI_80211_SSID is deﬁned above.
AKMSuite Pointer to the AKM suites supported in the wireless network. Type
EFI_80211_AKM_SUITE_SELECTOR is deﬁned below.
CipherSuite Pointer to the cipher suites supported in the wireless network. Type
EFI_80211_CIPHER_SUITE_SELECTOR is deﬁned below.
27.4. EFI Wireless MAC Connection II Protocol 1070Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheEFI_80211_BSS_TYPE is deﬁned to enumerate BSS type.
// EFI_80211_SUITE_SELECTOR
UINT8 Oui[3];
UINT8 SuiteType;
} EFI_80211_SUITE_SELECTOR;
Oui Organization Unique Identiﬁer, as deﬁned in IEEE 802.11 standard, usually set to 00-0F-AC.
SuiteType Suites types, as deﬁned in IEEE 802.11 standard.
//***********************************************************
// EFI_80211_AKM_SUITE_SELECTOR
//************************************************************
UINT16 AKMSuiteCount;
EFI_80211_SUITE_SELECTOR AKMSuiteList[1];

} EFI_80211_AKM_SUITE_SELECTOR;
AKMSuiteCount Indicates the number of AKM suite selectors that are contained in AKMSuiteList. If zero, the
AKMSuiteList is ignored.
AKMSuiteList A variable-length array of AKM suites, as deﬁned in IEEE 802.11 standard, Table 8-101. The number
of entries is speciﬁed by AKMSuiteCount.
// EFI_80211_CIPHER_SUITE_SELECTOR
UINT16 CipherSuiteCount;
EFI_80211_SUITE_SELECTOR CipherSuiteList[1];
} EFI_80211_CIPHER_SUITE_SELECTOR;
CipherSuiteCount Indicates the number of cipher suites that are contained in CipherSuiteList. If zero, the Cipher-
SuiteList is ignored.
CipherSuiteList A variable-length array of cipher suites, as deﬁned in IEEE 802.11 standard, Table 8-99. The number
of entries is speciﬁed by CipherSuiteCount.
EFI_SUCCESS The operation started, and an event will eventually be raised for the caller.
27.4. EFI Wireless MAC Connection II Protocol 1071Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 27.18 – continued from previous page
This is NULL.
Token is NULL.
EFI_UNSUPPORTED One or more of the input parameters is not supported by this implementa-
tion.
EFI_ALREADY_STARTED The operation of getting wireless network is already started.
27.4.3 EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL.ConnectNetwork()
Summary
Connect a wireless network speciﬁed by a particular SSID, BSS type and Security type.
Prototype
typedef
(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_CONNECT_NETWORK)(
IN EFI_80211_CONNECT_NETWORK_TOKEN *Token
);
Token Pointer to the token for connecting wireless network. Type EFI_80211_CONNECT_NETWORK_TOKEN is
deﬁned in Related Deﬁnitions below.
TheConnectNetwork() function places a request to wireless UNDI driver to connect a wireless network speciﬁed by
a particular SSID, BSS type, Authentication method and cipher. This function will trigger wireless UNDI driver to
perform authentication and association process to establish connection with a particular Access Point for the speciﬁed
network. This function is always non-blocking. If the connection succeeds or fails due to any error, the Token->Event
will be signaled and Token->Status will be updated accordingly.
After having signaled a successful connection completion, the UNDI driver will update the network connection state
using the network media state information type in the EFI_ADAPTER_INFORMATION_PROTOCOL. If needed, the
caller should use EFI_ADAPTER_INFORMATION_PROTOCOL to regularly get the network media state to ﬁnd if the
UNDI driver is still connected to the wireless network ( EFI_SUCCESS ) or not ( EFI_NO_MEDIA ).
Generally a driver or application in WiFi stack would provide user interface to end user to manage proﬁles for se-
lecting which wireless network to join and other state management. This module should prompt the user to select
a network and input WiFi security data such as certiﬁcate, private key ﬁle, password, etc. Then the module should
deploy WiFi security data through EFI Supplicant Protocol and/ or EFI EAP Conﬁguration Protocol before calling
ConnectNetwork() function.
// EFI_80211_CONNECT_NETWORK_TOKEN
27.4. EFI Wireless MAC Connection II Protocol 1072Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_80211_CONNECT_NETWORK_DATA *Data;
EFI_80211_CONNECT_NETWORK_RESULT_CODE ResultCode;
} EFI_80211_CONNECT_NETWORK_TOKEN;
Event If the status code returned by ConnectNetwork() is EFI_SUCCESS, then this Event will be signaled after the
Data Pointer to the connection data. Type EFI_80211_CONNECT_NETWORK_DATA is deﬁned below.
ResultCode Indicates the connection state. Type EFI_80211_CONNECT_NETWORK_RESULT_CODE is deﬁned
below.
TheEFI_80211_CONNECT_NETWORK_TOKEN structure is deﬁned to support the process of determining the char-
acteristics of the available networks. As input, the Data ﬁeld must be ﬁlled in by the caller of EFI Wireless MAC
Connection II Protocol. After the operation completes, the EFI Wireless MAC Connection II Protocol driver updates
theStatus andResultCode ﬁeld and the Event is signaled.
// EFI_80211_CONNECT_NETWORK_DATA
EFI_80211_NETWORK *Network;
} EFI_80211_CONNECT_NETWORK_DATA;
Network Speciﬁes the wireless network to connect to. Type EFI_80211_NETWORK is deﬁned above.
FailureTimeout Speciﬁes a time limit in seconds that is optionally present, after which the connection establishment
procedure is terminated by the UNDI driver. This is an optional parameter and may be 0. Values of 5 seconds
or higher are recommended.
// EFI_80211_CONNECT_NETWORK_RESULT_CODE
ConnectSuccess,
ConnectRefused,
ConnectFailed,
ConnectFailureTimeout,
ConnectFailedReasonUnspecified
} EFI_80211_CONNECT_NETWORK_RESULT_CODE;
ConnectSuccess The connection establishment operation ﬁnished successfully.
27.4. EFI Wireless MAC Connection II Protocol 1073Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ConnectRefused The connection was refused by the Network.
ConnectFailed The connection establishment operation failed (i.e, Network is not detected).
ConnectFailureTimeout The connection establishment operation was terminated on timeout.
ConnectFailedReasonUnspeciﬁed The connection establishment operation failed on other reason.
EFI_SUCCESS The operation started successfully. Results will be notiﬁed eventually.
tion.
EFI_ALREADY_STARTED The connection process is already started.
EFI_NOT_FOUND The speciﬁed wireless network is not found.
27.4.4 EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL.DisconnectNetwork()
Summary
Request a disconnection withcurrent connected wireless network.
Prototype
typedef
(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_DISCONNECT_NETWORK)(
IN EFI_80211_DISCONNECT_NETWORK_TOKEN *Token
);
Token Pointer to the token for disconnecting wireless network. Type
EFI_80211_DISCONNECT_NETWORK_TOKEN is deﬁned in Related Deﬁnitions below.
TheDisconnectNetwork() function places a request to wireless UNDI driver to disconnect from the wireless network
it is connected to. This function will trigger the wireless UNDI driver to perform disassociation and deauthentication
process to terminate an existing connection. This function is always non-blocking. After wireless UNDI driver re-
ceived acknowledgment frame from AP and freed up corresponding resources, the Token->Event will be signaled and
Token->Status will be updated accordingly.
// EFI_80211_DISCONNECT_NETWORK_TOKEN
27.4. EFI Wireless MAC Connection II Protocol 1074Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_80211_DISCONNECT_NETWORK_TOKEN;
Event If the status code returned by DisconnectNetwork() is EFI_SUCCESS, then this Event will be signaled after
the Status ﬁeld is updated by the EFI Wireless MAC Connection Protocol II driver. The type of Event must be
EFI_SUCCESS: The operation completed successfully

tion.
EFI_NOT_FOUND Not connected to a wireless network.
27.5 EFI Supplicant Protocol
This section deﬁnes the EFI Supplicant Protocol.
27.5.1 Supplicant Service Binding Protocol
27.5.2 EFI_SUPPLICANT_SERVICE_BINDING_PROTOCOL
Summary
The EFI Supplicant Service Binding Protocol is used to locate EFI Supplicant Protocol drivers to create and destroy
child of the driver to communicate with other host using Supplicant protocol.
GUID
#define EFI_SUPPLICANT_SERVICE_BINDING_PROTOCOL_GUID \
{ 0x45bcd98e, 0x59ad, 0x4174, \
{ 0x95, 0x46, 0x34, 0x4a, 0x7, 0x48, 0x58, 0x98 }}
27.5. EFI Supplicant Protocol 1075Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
A module that requires supplicant services can call one of the protocol handler services, such as BS-
>LocateHandleBuffer(), to search devices that publish an EFI Supplicant Service Binding Protocol GUID. Such
device supports the EFI Supplicant Protocol and may be available for use. After a successful call to the
EFI_SUPPLICANT_SERVICE_BINDING_PROTOCOL.CreateChild() function, the newly created child EFI Suppli-
cant Protocol driver is in an un-conﬁgured state; it is not ready to do any operation until conﬁgured via SetData().
Every successful call to the EFI_SUPPLICANT_SERVICE_BINDING_PROTOCOL.CreateChild() function must be
matched with a call to the EFI_SUPPLICANT_SERVICE_BINDING_PROTOCOL.DestroyChild() function to release
the protocol driver.
27.5.3 Supplicant Protocol
27.5.4 EFI_SUPPLICANT_PROTOCOL
Summary
This protocol provides services to process authentication and data encryption/decryption for security management.
GUID
#define EFI_SUPPLICANT_PROTOCOL_GUID \
{ 0x54fcc43e, 0xaa89, 0x4333, \
{ 0x9a, 0x85, 0xcd, 0xea, 0x24, 0x5, 0x1e, 0x9e }}
typedef struct _EFI_SUPPLICANT_PROTOCOL {
EFI_SUPPLICANT_BUILD_RESPONSE_PACKET BuildResponsePacket;
EFI_SUPPLICANT_PROCESS_PACKET ProcessPacket;
EFI_SUPPLICANT_SET_DATA SetData;
EFI_SUPPLICANT_GET_DATA GetData;
} EFI_SUPPLICANT_PROTOCOL;
BuildResponsePacket This API processes security data for handling key management. See the BuildResponsePa-
cket() function description.
ProcessPacket This API processes frame for encryption or decryption. See the ProcessPacket() function description.
SetData This API sets the information needed during key generated in handshake. See the SetData() function de-
GetData This API gets the information generated in handshake. See the GetData() function description.
TheEFI_SUPPLICANT_PROTOCOL is designed to provide uniﬁed place for WIFI and EAP security management.
Both PSK authentication and 802.1X EAP authentication can be managed via this protocol and driver or application
as a consumer can only focus on about packet transmitting or receiving. For 802.1X EAP authentication, an instance
ofEFI_EAP_CONFIGURATION_PROTOCOL must be installed to the same handle as the EFI Supplicant Protocol.
27.5. EFI Supplicant Protocol 1076Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.5.5 EFI_SUPPLICANT_PROTOCOL.BuildResponsePacket()
Summary
BuildResponsePacket() is called during STA and AP authentication is in progress. Supplicant derives the PTK or
session keys depend on type of authentication is being employed.
Prototype
typedef
(EFIAPI *EFI_SUPPLICANT_BUILD_RESPONSE_PACKET)(
IN EFI_SUPPLICANT_PROTOCOL *This,
IN UINT8 *RequestBuffer, OPTIONAL
IN UINTN RequestBufferSize, OPTIONAL
OUT UINT8 *Buffer,
);
This Pointer to the EFI_SUPPLICANT_PROTOCOL instance.
RequestBuffer Pointer to the most recently received EAPOL packet. NULL means the supplicant need initiate the
EAP authentication session and send EAPOL-Start message.
RequestSize Packet size in bytes for the most recently received EAPOL packet. 0 is only valid when RequestBuffer
isNULL.
Buffer Pointer to the buffer to hold the built packet.
BufferSize Pointer to the buffer size in bytes. On input, it is the buffer size provided by the caller. On output, it is the
buffer size in fact needed to contain the packet.
The consumer calls BuildResponsePacket() when it receives the security frame. It simply passes the data to supplicant
to process the data. It could be WPA-PSK which starts the 4-way handshake, or WPA-EAP ﬁrst starts with Au-
thentication process and then 4-way handshake, or 2-way group key handshake. In process of authentication, 4-way
handshake or group key handshake, Supplicant needs to communicate with its peer (AP/AS) to ﬁll the output buffer
parameter. Once the 4 way handshake or group key handshake is over, and PTK (Pairwise Transient keys) and GTK
(Group Temporal Key) are generated.
EFI_SUCCESS The required EAPOL packet is built successfully.
•RequestBuffer isNULL, butRequestSize is NOT 0.
•RequestSize is 0.
•Buffer isNULL, butRequestBuffer is NOT 0.
•BufferSize isNULL.
EFI_BUFFER_TOO_SMALL BufferSize is too small to hold the response packet.
EFI_NOT_READY Current EAPOL session state is NOT ready to build ResponsePacket.
27.5. EFI Supplicant Protocol 1077Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
27.5.6 EFI_SUPPLICANT_PROTOCOL.ProcessPacket()
Summary
ProcessPacket() is called to Supplicant driver to encrypt or decrypt the data depending type of authentication type.
Prototype
typedef
(EFIAPI *EFI_SUPPLICANT_PROCESS_PACKET)(
IN OUT EFI_SUPPLICANT_FRAGMENT_DATA **FragmentTable,
IN UINT32 *FragmentCount,
IN EFI_SUPPLICANT_CRYPT_MODE CryptMode
);
FragmentTable Pointer to a list of fragment. The caller will take responsible to handle the original FragmentTable
while it may be reallocated in Supplicant driver.
FragmentCount Number of fragment.
CryptMode Crypt mode.
ProcessPacket() is responsible for encrypting or decrypting the data trafﬁc as per authentication type. The consumer
routes the data frame as it is to Supplicant module and encrypts or decrypts packet with updated length comes as output
parameter. Supplicant holds the derived PTK and GTKs and uses this key to encrypt or decrypt the network trafﬁc.
If the Supplicant driver does not support any encryption and decryption algorithm, then EFI_UNSUPPORTED is
returned.
// EFI_SUPPLICANT_FRAGMENT_DATA
} EFI_SUPPLICANT_FRAGMENT_DATA;
FragmentLength Length of data buffer in the fragment.
FragmentBuffer Pointer to the data buffer in the fragment.
// EFI_SUPPLICANT_CRYPT_MODE
EfiSupplicantEncrypt,
EfiSupplicantDecrypt,
} EFI_SUPPLICANT_CRYPT_MODE;
EﬁSupplicantEncrypt Encrypt data provided in the fragment buffers.
EﬁSupplicantDecrypt Decrypt data provided in the fragment buffers.
27.5. EFI Supplicant Protocol 1078Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
•FragmentTable is NULL.
•FragmentCount is NULL.
•CryptMode is invalid.
EFI_NOT_READY Current supplicant state is NOT Authenticated.
EFI_ABORTED Something wrong decryption the message.
EFI_UNSUPPORTED This API is not supported.
27.5.7 EFI_SUPPLICANT_PROTOCOL.SetData()
Summary
Set Supplicant conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_SUPPLICANT_SET_DATA)(
IN EFI_SUPPLICANT_DATA_TYPE DataType,
);
This Pointer to the EFI_ SUPPLICANT _PROTOCOL instance.
DataType The type of data.
Data Pointer to the buffer to hold the data.
DataSize Pointer to the buffer size in bytes.
The SetData() function sets Supplicant conﬁguration. For example, Supplicant driver need to know Password and
TargetSSIDName to calculate PSK. Supplicant driver need to know StationMac and TargetSSIDMac to calculate
PTK. Then it can derive KCK(key conﬁrmation key) which is needed to calculate MIC, and KEK(key encryption key)
which is needed to unwrap GTK.

Summary
Prototype
typedef
);
// EFI_SUPPLICANT_DATA_TYPE
//
// Session Configuration
//
EfiSupplicant80211AKMSuite,
27.5. EFI Supplicant Protocol 1079Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EfiSupplicant80211GroupDataCipherSuite,
EfiSupplicant80211PairwiseCipherSuite,
EfiSupplicant80211PskPassword,
EfiSupplicant80211TargetSSIDName,
EfiSupplicant80211StationMac,
EfiSupplicant80211TargetSSIDMac,
//
// Session Information
//
EfiSupplicant80211PTK,
EfiSupplicant80211GTK,
EfiSupplicantState,
EfiSupplicant80211LinkState,
EfiSupplicantKeyRefresh,
//
//
EfiSupplicant80211SupportedAKMSuites,
EfiSupplicant80211SupportedSoftwareCipherSuites,
EfiSupplicant80211SupportedHardwareCipherSuites,
//
//
EfiSupplicant80211IGTK,
EfiSupplicant80211PMK,
EfiSupplicantDataTypeMaximum
} EFI_SUPPLICANT_DATA_TYPE;
EﬁSupplicant80211AKMSuite Current authentication type in use. The corresponding Data is of type
EFI_80211_AKM_SUITE_SELECTOR.
EﬁSupplicant80211GroupDataCipherSuite Group data encryption type in use. The corresponding Data is of type
EFI_80211_CIPHER_SUITE_SELECTOR.
EﬁSupplicant80211PairwiseCipherSuite Pairwise encryption type in use. The corresponding Data is of type
EﬁSupplicant80211PskPassword PSK password. The corresponding Data is a NULL-terminated ASCII string.
EﬁSupplicant80211TargetSSIDName Target SSID name. The corresponding Data is of type EFI_80211_SSID.
EﬁSupplicant80211StationMac Station MAC address. The corresponding Data is of type
EFI_80211_MAC_ADDRESS.
EﬁSupplicant80211TargetSSIDMac Target SSID MAC address. The corresponding Data is 6 bytes MAC address.
EﬁSupplicant80211PTK 802.11 PTK. The corresponding Data is of type EFI_SUPPLICANT_KEY .
EﬁSupplicant80211GTK 802.11 GTK. The corresponding Data is of type EFI_SUPPLICANT_GTK_LIST.
EﬁSupplicantState Supplicant state. The corresponding Data is EFI_EAPOL_SUPPLICANT_PAE_STATE.
EﬁSupplicant80211LinkState 802.11 link state. The corresponding Data is EFI_80211_LINK_STATE.
EﬁSupplicantKeyRefresh Flag indicates key is refreshed. The corresponding Data is
EFI_SUPPLICANT_KEY_REFRESH.
27.5. EFI Supplicant Protocol 1080Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EﬁSupplicant80211SupportedAKMSuites Supported authentication types. The corresponding Data is of type
EﬁSupplicant80211SupportedSoftwareCipherSuites Supported software encryption types provided by supplicant
driver. The corresponding Data is of type EFI_80211_CIPHER_SUITE_SELECTOR.
EﬁSupplicant80211SupportedHardwareCipherSuites Supported hardware encryption types provided by wireless
UNDI driver. The corresponding Data is of type EFI_80211_CIPHER_SUITE_SELECTOR.
EﬁSupplicant80211IGTK 802.11 Integrity GTK. The corresponding Data is of type
EFI_SUPPLICANT_GTK_LIST.
EﬁSupplicant80211IPMK 802.11 PMK. The corresponding Data is 32 bytes pairwise master key.
// EFI_80211_LINK_STATE
Ieee80211UnauthenticatedUnassociated,
Ieee80211AuthenticatedUnassociated,
Ieee80211PendingRSNAuthentication,
Ieee80211AuthenticatedAssociated
} EFI_80211_LINK_STATE;
Ieee80211UnauthenticatedUnassociated Indicates initial start state, unauthenticated, unassociated.
Ieee80211AuthenticatedUnassociated Indicates authenticated, unassociated.
Ieee80211PendingRSNAuthentication Indicates authenticated and associated, but pending RSN authentication.
Ieee80211AuthenticatedAssociated Indicates authenticated and associated.
// EFI_SUPPLICANT_KEY_REFRESH
BOOLEAN GTKRefresh;
} EFI_SUPPLICANT_KEY_REFRESH;
GTKRefresh If TRUE, indicates GTK is just refreshed after a successful call to
EFI_SUPPLICANT_PROTOCOL.BuildResponsePacket().
// EFI_SUPPLICANT_GTK_LIST
UINT8 GTKCount;
EFI_SUPPLICANT_KEY GTKList[1];
} EFI_SUPPLICANT_GTK_LIST;
GTKCount Indicates the number of GTKs that are contained in GTKList.
GTKList A variable-length array of GTKs of type EFI_SUPPLICANT_KEY . The number of entries is speciﬁed by
GTKCount
#define EFI_MAX_KEY_LEN 64
// EFI_SUPPLICANT_KEY
27.5. EFI Supplicant Protocol 1081Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT8 Key[EFI_MAX_KEY_LEN];
UINT8 KeyLen;
UINT8 KeyId;
EFI_SUPPLICANT_KEY_TYPE KeyType;
EFI_80211_MAC_ADDRESS Addr;
UINT8 Rsc[8];
UINT8 RscLen;
BOOLEAN IsAuthenticator;
EFI_80211_SUITE_SELECTOR CipherSuite;
EFI_SUPPLICANT_KEY_DIRECTION Direction;
} EFI_SUPPLICANT_KEY;
The EFI_SUPPLICANT_KEY descriptor is deﬁned in the IEEE 802.11 standard, section 6.3.19.1.2.
Key The key value.
KeyLen Length in bytes of the Key. Should be up to EFI_MAX_KEY_LEN.
KeyId The key identiﬁer.
KeyType Deﬁnes whether this key is a group key, pairwise key, PeerKey, or Integrity Group.
Addr The value is set according to the KeyType.
RSC The Receive Sequence Count value.
RscLen Length in bytes of the Rsc. Should be up to 8.
IsAuthenticator Indicates whether the key is conﬁgured by the Authenticator or Supplicant. The value true indicates
Authenticator.
CipherSuite The cipher suite required for this association.
Direction Indicates the direction for which the keys are to be installed.
// EFI_SUPPLICANT_KEY_TYPE (IEEE Std 802.11
// Section 6.3.19.1.2)
Group,
Pairwise,
PeerKey,
IGTK
} EFI_SUPPLICANT_KEY_TYPE;
The EFI_SUPPLICANT_KEY_TYPE is deﬁned in the IEEE 802.11 speciﬁcation.
// EFI_SUPPLICANT_KEY_DIRECTION (IEEE Std 802.11
Receive,
Transmit,
Both
} EFI_SUPPLICANT_KEY_DIRECTION;
Receive Indicates that the keys are being installed for the receive direction.
27.5. EFI Supplicant Protocol 1082Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Transmit Indicates that the keys are being installed for the transmit direction.
Both Indicates that the keys are being installed for both the receive and transmit directions.
EFI_SUCCESS The Supplicant conﬁguration data is set successfully.
27.5.8 EFI_SUPPLICANT_PROTOCOL.GetData()
Summary
Get Supplicant conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_SUPPLICANT_GET_DATA)(
OUT UINT8 *Data, OPTIONAL
);
Data Pointer to the buffer to hold the data. Ignored if DataSize is 0.
DataSize Pointer to the buffer size in bytes. On input, it is the buffer size provided by the caller. On output, it is the
TheGetData() function gets Supplicant conﬁguration. The typical example is PTK and GTK derived from handshake.
The wireless NIC can support software encryption or hardware encryption. If the consumer uses software encryption,
it can call ProcessPacket() to get result. If the consumer supports hardware encryption, it can get PTK and GTK via
GetData() and program to hardware register.
EFI_SUCCESS The Supplicant conﬁguration data is got successfully.
27.5. EFI Supplicant Protocol 1083Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 27.24 – continued from previous page
• This is NULL.
• Data is NULL if DataSize is not zero.
EFI_NOT_FOUND The Supplicant conﬁguration data is not found.
EFI_BUFFER_TOO_SMALL The size of Data is too small for the speciﬁed conﬁguration data and the
required size is returned in DataSize.
27.5. EFI Supplicant Protocol 1084CHAPTER
TWENTYEIGHT
NETWORK PROTOCOLS — TCP, IP, IPSEC, FTP, TLS AND
CONFIGURATIONS
28.1 EFI TCPv4 Protocol
This section deﬁnes the EFI TCPv4 (Transmission Control Protocol version 4) Protocol.
28.1.1 TCP4 Service Binding Protocol

28.1.2 EFI_TCP4_SERVICE_BINDING_PROTOCOL
Summary
The EFI TCPv4 Service Binding Protocol is used to locate EFI TCPv4 Protocol drivers to create and destroy child of
the driver to communicate with other host using TCP protocol.
GUID
#define EFI_TCP4_SERVICE_BINDING_PROTOCOL_GUID \
{0x00720665,0x67EB,0x4a99,\
{0xBA,0xF7,0xD3,0xC3,0x3A,0x1C,0x7C,0xC9}}
A network application that requires TCPv4 I/O services can call one of the protocol handler services, such as BS-
>LocateHandleBuffer(), to search devices that publish an EFI TCPv4 Service Binding Protocol GUID. Such device
supports the EFI TCPv4 Protocol and may be available for use.
After a successful call to the EFI_TCP4_SERVICE_BINDING_PROTOCOL .CreateChild() function, the newly cre-
ated child EFI TCPv4 Protocol driver is in an un-conﬁgured state; it is not ready to do any operation except Poll() send
and receive data packets until conﬁgured as the purpose of the user and perhaps some other indispensable function
belonged to TCPv4 Protocol driver is called properly.
Every successful call to the EFI_TCP4_SERVICE_BINDING_PROTOCOL .CreateChild() function must be matched
with a call to the EFI_TCP4_SERVICE_BINDING_PROTOCOL.DestroyChild() function to release the protocol driver.
1085Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.1.3 TCP4 Protocol
28.1.4 EFI_TCP4_PROTOCOL
Summary
The EFI TCPv4 Protocol provides services to send and receive data stream.
GUID
#define EFI_TCP4_PROTOCOL_GUID \
{0x65530BC7,0xA359,0x410f,\
{0xB0,0x10,0x5A,0xAD,0xC7,0xEC,0x2B,0x62}}
typedef struct _EFI_TCP4_PROTOCOL {
EFI_TCP4_GET_MODE_DATA GetModeData;
EFI_TCP4_CONFIGURE Configure;
EFI_TCP4_ROUTES Routes;
EFI_TCP4_CONNECT Connect;
EFI_TCP4_ACCEPT Accept;
EFI_TCP4_TRANSMIT Transmit;
EFI_TCP4_RECEIVE Receive;
EFI_TCP4_CLOSE Close;
EFI_TCP4_CANCEL Cancel;
EFI_TCP4_POLL Poll;
} EFI_TCP4_PROTOCOL;
GetModeData Get the current operational status. See the GetModeData() function description.
Conﬁgure Initialize, change, or brutally reset operational settings of the EFI TCPv4 Protocol. See the Conﬁgure()
Routes Add or delete routing entries for this TCP4 instance. See the Routes() function description.
Connect Initiate the TCP three-way handshake to connect to the remote peer conﬁgured in this TCP instance. The
function is a nonblocking operation. See the Connect() function description.
Accept Listen for incoming TCP connection request. This function is a nonblocking operation. See the Accept()
Transmit Queue outgoing data to the transmit queue. This function is a nonblocking operation. See the Transmit()
Receive Queue a receiving request token to the receive queue. This function is a nonblocking operation. See the
Receive() function description.
Close Gracefully disconnecting a TCP connection follow RFC 793 or reset a TCP connection. This function is a
nonblocking operation. See the Close() function description.
Cancel Abort a pending connect, listen, transmit or receive request. See the Cancel() function description.
Poll Poll to receive incoming data and transmit outgoing TCP segments. See the Poll() function description.
TheEFI_TCP4_PROTOCOL deﬁnes the EFI TCPv4 Protocol child to be used by any network drivers or applications
to send or receive data stream. It can either listen on a speciﬁed port as a service or actively connected to remote peer
as a client. Each instance has its own independent settings, such as the routing table.
28.1. EFI TCPv4 Protocol 1086Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Note :In this document, all IPv4 addresses and incoming/outgoing packets are stored in network byte order. All other
parameters in the functions and data structures that are deﬁned in this document are stored in host byte order unless
explicitly speciﬁed .
28.1.5 EFI_TCP4_PROTOCOL.GetModeData()
Summary
Get the current operational status.
Prototype
typedef
(EFIAPI *EFI_TCP4_GET_MODE_DATA) (
IN EFI_TCP4_PROTOCOL *This,
OUT EFI_TCP4_CONNECTION_STATE *Tcp4State OPTIONAL,
OUT EFI_TCP4_CONFIG_DATA *Tcp4ConfigData OPTIONAL,
OUT EFI_IPv4_MODE_DATA *Ip4ModeData OPTIONAL,
);
This Pointer to the EFI_TCP4_PROTOCOL instance.
Tcp4State Pointer to the buffer to receive the current TCP state. Type EFI_TCP4_CONNECTION_STATE is deﬁned
Tcp4ConﬁgData Pointer to the buffer to receive the current TCP conﬁguration. Type EFI_TCP4_CONFIG_DATA is
Ip4ModeData Pointer to the buffer to receive the current IPv4 conﬁguration data used by the TCPv4 instance. Type
EFI_IP4_MODE_DATA is deﬁned in EFI_IP4_PROTOCOL .GetModeData() .
MnpConﬁgData Pointer to the buffer to receive the current MNP conﬁguration data used indi-
rectly by the TCPv4 instance. Type EFI_MANAGED_NETWORK_CONFIG_DATA is deﬁned in
SnpModeData Pointer to the buffer to receive the current SNP conﬁguration data used indirectly by the TCPv4
instance. Type EFI_SIMPLE_NETWORK_MODE is deﬁned in the EFI_SIMPLE_NETWORK_PROTOCOL .
TheGetModeData() function copies the current operational settings of this EFI TCPv4 Protocol instance into user-
supplied buffers. This function can also be used to retrieve the operational setting of underlying drivers such as IPv4,
MNP, or SNP.
Related Deﬁnition
BOOLEAN UseDefaultAddress;
EFI_IPv4_ADDRESS StationAddress;
EFI_IPv4_ADDRESS SubnetMask;
UINT16 StationPort;
EFI_IPv4_ADDRESS RemoteAddress;
UINT16 RemotePort;
BOOLEAN ActiveFlag;
} EFI_TCP4_ACCESS_POINT;
28.1. EFI TCPv4 Protocol 1087Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UseDefaultAddress Set to TRUE to use the default IP address and default routing table. If the default IP address
is not available yet, then the underlying EFI IPv4 Protocol driver will use EFI_IP4_CONFIG2_PROTOCOL to
retrieve the IP address and subnet information.
StationAddress The local IP address assigned to this EFI TCPv4 Protocol instance. The EFI TCPv4 and EFI IPv4
Protocol drivers will only deliver incoming packets whose destination addresses exactly match the IP address.
Not used when UseDefaultAddress isTRUE .
SubnetMask The subnet mask associated with the station address. Not used when UseDefaultAddress isTRUE .
StationPort The local port number to which this EFI TCPv4 Protocol instance is bound. If the instance doesn’t care
the local port number, set StationPort to zero to use an ephemeral port.
RemoteAddress The remote IP address to which this EFI TCPv4 Protocol instance is connected. If ActiveFlag is
FALSE (i.e., a passive TCPv4 instance), the instance only accepts connections from the RemoteAddress . If
ActiveFlag isTRUE the instance is connected to the RemoteAddress, i.e., outgoing segments will be sent to this
address and only segments from this address will be delivered to the application. When ActiveFlag isFALSE it
can be set to zero and means that incoming connection request from any address will be accepted.
RemotePort The remote port to which this EFI TCPv4 Protocol instance is connects or connection request from
which is accepted by this EFI TCPv4 Protocol instance. If ActiveFlag isFALSE it can be zero and means
that incoming connection request from any port will be accepted. Its value can not be zero when ActiveFlag is
TRUE .
ActiveFlag Set it to TRUE to initiate an active open. Set it to FALSE to initiate a passive open to act as a server.
UINT32 ReceiveBufferSize;
UINT32 SendBufferSize;
UINT32 MaxSynBackLog;
UINT32 ConnectionTimeout;
UINT32 DataRetries;
UINT32 FinTimeout;
UINT32 TimeWaitTimeout;
UINT32 KeepAliveProbes;
UINT32 KeepAliveTime;
UINT32 KeepAliveInterval;
BOOLEAN EnableNagle;
BOOLEAN EnableTimeStamp;
BOOLEAN EnableWindowScaling;
BOOLEAN EnableSelectiveAck;
BOOLEAN EnablePathMtuDiscovery;
} EFI_TCP4_OPTION;
ReceiveBufferSize The size of the TCP receive buffer.
SendBufferSize The size of the TCP send buffer.
MaxSynBackLog The length of incoming connect request queue for a passive instance. When set to zero, the value
is implementation speciﬁc.
ConnectionTimeout The maximum seconds a TCP instance will wait for before a TCP connection established. When
set to zero, the value is implementation speciﬁc.
DataRetries The number of times TCP will attempt to retransmit a packet on an established connection. When set to
zero, the value is implementation speciﬁc.
FinTimeout How many seconds to wait in the FIN_WAIT_2 states for a ﬁnal FIN ﬂag before the TCP instance
is closed. This timeout is in effective only if the application has called Close() to disconnect the connection
completely. It is also called FIN_WAIT_2 timer in other implementations. When set to zero, it should be
disabled because the FIN_WAIT_2 timer itself is against the standard.

28.1. EFI TCPv4 Protocol 1088Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TimeWaitTimeout How many seconds to wait in TIME_WAIT state before the TCP instance is closed. The timer is
disabled completely to provide a method to close the TCP connection quickly if it is set to zero. It is against the
related RFC documents.
KeepAliveProbes The maximum number of TCP keep-alive probes to send before giving up and resetting the con-
nection if no response from the other end. Set to zero to disable keep-alive probe.
KeepAliveTime The number of seconds a connection needs to be idle before TCP sends out periodical keep-alive
probes. When set to zero, the value is implementation speciﬁc. It should be ignored if keep-alive probe is
disabled.
KeepAliveInterval The number of seconds between TCP keep-alive probes after the periodical keep-alive probe if
no response. When set to zero, the value is implementation speciﬁc. It should be ignored if keep-alive probe is
disabled.
EnableNagle Set it to TRUE to enable the Nagle algorithm as deﬁned in RFC896. Set it to FALSE to disable it.
EnableTimeStamp Set it to TRUE to enable TCP timestamps option as deﬁned in RFC7323. Set to FALSE to
disable it.
EnableWindowScaling Set it to TRUE to enable TCP window scale option as deﬁned in RFC7323. Set it to FALSE
to disable it.
EnableSelectiveAck Set it to TRUE to enable selective acknowledge mechanism described in RFC 2018. Set it to
FALSE to disable it. Implementation that supports SACK can optionally support DSAK as deﬁned in RFC
2883.
EnablePathMtudiscovery Set it to TRUE to enable path MTU discovery as deﬁned in RFC 1191. Set to FALSE to
Option setting with digital value will be modiﬁed by driver if it is set out of the implementation speciﬁc range and an
implementation speciﬁc default value will be set accordingly.
//*************************************************
// EFI_TCP4_CONFIG_DATA
// Receiving Filters
// I/O parameters
UINT8 TypeOfService;
UINT8 TimeToLive;
// Access Point
EFI_TCP4_ACCESS_POINT AccessPoint;
// TCP Control Options
EFI_TCP4_OPTION ControlOption;
} EFI_TCP4_CONFIG_DATA;
TypeOfService TypeOfService ﬁeld in transmitted IPv4 packets.
TimeToLive TimeToLive ﬁeld in transmitted IPv4 packets.
AccessPoint Used to specify TCP communication end settings for a TCP instance.
ControlOption Used to conﬁgure the advance TCP option for a connection. If set to NULL, implementation speciﬁc
options for TCP connection will be used.
// EFI_TCP4_CONNECTION_STATE
28.1. EFI TCPv4 Protocol 1089Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Tcp4StateClosed = 0,
Tcp4StateListen = 1,
Tcp4StateSynSent = 2,
Tcp4StateSynReceived = 3,
Tcp4StateEstablished = 4,
Tcp4StateFinWait1 = 5,
Tcp4StateFinWait2 = 6,
Tcp4StateClosing = 7,
Tcp4StateTimeWait = 8,
Tcp4StateCloseWait = 9,
Tcp4StateLastAck = 10
} EFI_TCP4_CONNECTION_STATE;
EFI_SUCCESS The mode data was read.
EFI_NOT_STARTED No conﬁguration data is available because this instance hasn’t been started.
28.1.6 EFI_TCP4_PROTOCOL.Conﬁgure()
Summary
Initialize or brutally reset the operational parameters for this EFI TCPv4 instance.
Prototype
typedef
(EFIAPI *EFI_TCP4_CONFIGURE) (
IN EFI_TCP4_CONFIG_DATA *TcpConfigData OPTIONAL
);
TcpConﬁgData Pointer to the conﬁgure data to conﬁgure the instance.
TheConﬁgure() function does the following:
• Initialize this EFI TCPv4 instance, i.e., initialize the communication end setting, specify active open or passive
open for an instance.
• Reset this TCPv4 instance brutally, i.e., cancel all pending asynchronous tokens, ﬂush transmission and receiv-
ing buffer directly without informing the communication peer.
No other TCPv4 Protocol operation can be executed by this instance until it is conﬁgured properly. For an active
TCP4 instance, after a proper conﬁguration it may call Connect() to initiates the three-way handshake. For a passive
TCP4 instance, its state will transit to Tcp4StateListen after conﬁguration, and Accept() may be called to listen the
incoming TCP connection request. If TcpConﬁgData is set to NULL, the instance is reset. Resetting process will be
28.1. EFI TCPv4 Protocol 1090Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
done brutally, the state machine will be set to Tcp4StateClosed directly, the receive queue and transmit queue will be
ﬂushed, and no trafﬁc is allowed through this instance.
EFI_SUCCESS The operational settings are set, changed, or reset successfully.
EFI_NO_MAPPING When using a default address, conﬁguration (through DHCP, BOOTP,
RARP, etc.) is not ﬁnished yet.
One or more following conditions are TRUE:
• TcpConﬁgData
-> AccessPoint.StationAddress isn’t a valid unicast IPv4 address
when TcpConﬁgData
-> AccessPoint.UseDefaultAddress is FALSE.
-> AccessPoint.SubnetMask isn’t a valid IPv4 address mask when
TcpConﬁgData
-> AccessPoint.UseDefaultAddress is FALSE. The subnet mask
must be contiguous.
-> AccessPoint.RemoteAddress isn’t a valid unicast IPv4 address.
-> AccessPoint.RemoteAddress is zero or TcpConﬁgData
-> AccessPoint.RemotePort is zero when TcpConﬁgData
-> AccessPoint.ActiveFlag is TRUE.
• A same access point has been conﬁgured in other TCP instance properly.
EFI_ACCESS_DENIED Conﬁguring TCP instance when it is conﬁgured without calling Conﬁgure()
with NULL to reset it.
EFI_UNSUPPORTED One or more of the control options are not supported in the implementation.
EFI_OUT_OF_RESOURCES Could not allocate enough system resources when executing Conﬁgure() .
28.1.7 EFI_TCP4_PROTOCOL.Routes()
Summary
Add or delete routing entries.
Prototype
typedef
(EFIAPI *EFI_TCP4_ROUTES) (
IN BOOLEAN DeleteRoute,
IN EFI_IPv4_ADDRESS *SubnetAddress,
IN EFI_IPv4_ADDRESS *SubnetMask,
IN EFI_IPv4_ADDRESS *GatewayAddress
);
28.1. EFI TCPv4 Protocol 1091Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DeleteRoute Set it to TRUE to delete this route from the routing table. Set it to FALSE to add this route to the
routing table. DestinationAddress andSubnetMask are used as the keywords to search route entry.
SubnetAddress The destination network.
SubnetMask The subnet mask of the destination network.
GatewayAddress The gateway address for this route. It must be on the same subnet with the station address unless a
direct route is speciﬁed.
TheRoutes() function adds or deletes a route from the instance’s routing table.
The most speciﬁc route is selected by comparing the SubnetAddress with the destination IP address’s arithmetical AND
to the SubnetMask .
The default route is added with both SubnetAddress andSubnetMask set to 0.0.0.0. The default route matches all
destination IP addresses if there is no more speciﬁc route.
Direct route is added with GatewayAddress set to 0.0.0.0. Packets are sent to the destination host if its address can be
found in the Address Resolution Protocol (ARP) cache or it is on the local subnet. If the instance is conﬁgured to use
default address, a direct route to the local network will be added automatically.
Each TCP instance has its own independent routing table. Instance that uses the default IP address will have a copy of
theEFI_IP4_CONFIG2_PROTOCOL ’s routing table. The copy will be updated automatically whenever the IP driver
reconﬁgures its instance. As a result, the previous modiﬁcation to the instance’s local copy will be lost.
The priority of checking the route table is speciﬁc with IP implementation and every IP implementation must comply
with RFC 1122.
Note: There is no way to set up routes to other network interface cards (NICs) because each NIC has its own inde-
pendent network stack that shares information only through EFI TCP4 variable.
EFI_NOT_STARTED The EFI TCPv4 Protocol instance has not been conﬁgured.
EFI_NO_MAPPING When using a default address, conﬁguration (DHCP, BOOTP, RARP, etc.)
is not ﬁnished yet.
•SubnetAddress isNULL .
•SubnetMask isNULL .
•GatewayAddress isNULL .
•SubnetAddress is not NULL a valid subnet address.
•SubnetMask is not a valid subnet mask.
•GatewayAddress is not a valid unicast IP address or it is not in the same
subnet.

subnet.
EFI_OUT_OF_RESOURCES Could not allocate enough resources to add the entry to the routing table.
EFI_NOT_FOUND This route is not in the routing table.
EFI_ACCESS_DENIED The route is already deﬁned in the routing table.
EFI_UNSUPPORTED The TCP driver does not support this operation.
28.1. EFI TCPv4 Protocol 1092Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.1.8 EFI_TCP4_PROTOCOL.Connect()
Summary
Initiate a nonblocking TCP connection request for an active TCP instance.
Prototype
typedef
(EFIAPI *EFI_TCP4_CONNECT) (
IN EFI_TCP4_CONNECTION_TOKEN *ConnectionToken,
);
ConnectionToken Pointer to the connection token to return when the TCP three way handshake ﬁnishes. Type
EFI_TCP4_CONNECTION_TOKEN is deﬁned in “Related Deﬁnition” below.
The Connect() function will initiate an active open to the remote peer conﬁgured in current TCP instance if it is
conﬁgured active. If the connection succeeds or fails due to any error, the ConnectionToken->CompletionToken.Event
will be signaled and ConnectionToken->CompletionToken.Status will be updated accordingly. This function can only
be called for the TCP instance in Tcp4StateClosed state. The instance will transfer into Tcp4StateSynSent if the
function returns EFI_SUCCESS. If TCP three way handshake succeeds, its state will become Tcp4StateEstablished,
otherwise, the state will return to Tcp4StateClosed .
// EFI_TCP4_COMPLETION_TOKEN
} EFI_TCP4_COMPLETION_TOKEN;
Event TheEvent to signal after request is ﬁnished and Status ﬁeld is updated by the EFI TCPv4 Protocol driver. The
type of Event must be EVT_NOTIFY_SIGNAL, and its Task Priority Level (TPL) must be lower than or equal to
TPL_CALLBACK .
Status The variable to receive the result of the completed operation. EFI_NO_MEDIA . There was a media error
The EFI_TCP4_COMPLETION_TOKEN is used as a common header for various asynchronous tokens.
// EFI_TCP4_CONNECTION_TOKEN
EFI_TCP4_COMPLETION_TOKEN CompletionToken;
} EFI_TCP4_CONNECTION_TOKEN;
Status TheStatus in the CompletionToken will be set to one of the following values if the active open succeeds or an
unexpected error happens:
EFI_SUCCESS. The active open succeeds and the instance is in Tcp4StateEstablished .
28.1. EFI TCPv4 Protocol 1093Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_CONNECTION_RESET. The connect fails because the connection is reset either by instance itself or
communication peer.
EFI_CONNECTION_REFUSED : The connect fails because this connection is initiated with an active open
and the connection is refused.
EFI_ABORTED. The active open was aborted.
EFI_TIMEOUT. The connection establishment timer expired and no more speciﬁc information is available.
EFI_NETWORK_UNREACHABLE. The active open fails because an ICMP network unreachable error is
received.
EFI_HOST_UNREACHABLE. The active open fails because an ICMP host unreachable error is received.
EFI_PROTOCOL_UNREACHABLE. The active open fails because an ICMP protocol unreachable error is
received.
EFI_PORT_UNREACHABLE. The connection establishment timer times out and an ICMP port unreachable
error is received.
EFI_ICMP_ERROR. The connection establishment timer timeout and some other ICMP error is received.
EFI_DEVICE_ERROR. An unexpected system or network error occurred.
EFI_SUCCESS The connection request is successfully initiated and the state of this TCPv4
instance has been changed to Tcp4StateSynSent .
EFI_NOT_STARTED This EFI TCPv4 Protocol instance has not been conﬁgured.
EFI_ACCESS_DENIED
One or more of the following conditions are TRUE:
• This instance is not conﬁgured as an active one.
• This instance is not in Tcp4StateClosed state.
One or more of the following are TRUE :
•ConnectionToken isNULL .
•ConnectionToken ->CompletionToken .Event isNULL .
EFI_OUT_OF_RESOURCES The driver can’t allocate enough resource to initiate the active open.
28.1. EFI TCPv4 Protocol 1094Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.4 – continued from previous page
EFI_DEVICE_ERROR An unexpected system or network error occurred.
28.1.9 EFI_TCP4_PROTOCOL.Accept()
Summary
Listen on the passive instance to accept an incoming connection request. This is a nonblocking operation.
Prototype
typedef
(EFIAPI *EFI_TCP4_ACCEPT) (
IN EFI_TCP4_LISTEN_TOKEN *ListenToken
);
ListenToken Pointer to the listen token to return when operation ﬁnishes. Type EFI_TCP4_LISTEN_TOKEN is
deﬁned in “Related Deﬁnition” below.
// EFI_TCP4_LISTEN_TOKEN
EFI_HANDLE NewChildHandle;
} EFI_TCP4_LISTEN_TOKEN;
Status TheStatus inCompletionToken will be set to the following value if accept ﬁnishes:
EFI_SUCCESS . A remote peer has successfully established a connection to thisinstance. A new TCP
instance has also been created for the connection.
EFI_CONNECTION_RESET . The accept fails because the connection is reset either by instance itself or
EFI_ABORTED . The accept request has been aborted.
NewChildHandle The new TCP instance handle created for the established connection.
TheAccept() function initiates an asynchronous accept request to wait for an incoming connection on the passive TCP
instance. If a remote peer successfully establishes a connection with this instance, a new TCP instance will be created
and its handle will be returned in ListenToken->NewChildHandle . The newly created instance is conﬁgured by inher-
iting the passive instance’s conﬁguration and is ready for use upon return. The instance is in the Tcp4StateEstablished
state.
28.1. EFI TCPv4 Protocol 1095Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheListenToken->CompletionToken.Event will be signaled when a new connection is accepted, user aborts the listen
or connection is reset.
This function only can be called when current TCP instance is in Tcp4StateListen state.
EFI_SUCCESS The listen token has been queued successfully.
• This instance is not a passive instance.
• This instance is not in Tcp4StateListen state.
• The same listen token has already existed in the listen token queue of this
TCP instance.
•ListenToken isNULL .
•ListentToken->CompletionToken.Event isNULL .
EFI_OUT_OF_RESOURCES Could not allocate enough resource to ﬁnish the operation.
EFI_DEVICE_ERROR Any unexpected and not belonged to above category error.
28.1.10 EFI_TCP4_PROTOCOL.Transmit()
Summary
Queues outgoing data into the transmit queue.
Prototype
typedef
(EFIAPI *EFI_TCP4_TRANSMIT) (
IN EFI_TCP4_IO_TOKEN *Token
);
Token Pointer to the completion token to queue to the transmit queue. Type EFI_TCP4_IO_TOKEN is deﬁned in
TheTransmit() function queues a sending request to this TCPv4 instance along with the user data. The status of the
token is updated and the event in the token will be signaled once the data is sent out or some error occurs.
// EFI_TCP4_IO_TOKEN
28.1. EFI TCPv4 Protocol 1096Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
union {
EFI_TCP4_RECEIVE_DATA *RxData;
EFI_TCP4_TRANSMIT_DATA *TxData;
} Packet;
} EFI_TCP4_IO_TOKEN;
Status When transmission ﬁnishes or meets any unexpected error it will be set to one of the following values:
EFI_SUCCESS. The receiving or transmission operation completes successfully.
EFI_CONNECTION_FIN : The receiving operation fails because the communication peer has closed the
connection and there is no more data in the receive buffer of the instance.
EFI_CONNECTION_RESET. The receiving or transmission operation fails because this connection is reset
either by instance itself or communication peer.
EFI_ABORTED. The receiving or transmission is aborted.

union {
} Packet;
EFI_TIMEOUT. The transmission timer expires and no more speciﬁc information is available.
EFI_NETWORK_UNREACHABLE. The transmission fails because an ICMP network unreachable error is
received.
EFI_HOST_UNREACHABLE. The transmission fails because an ICMP host unreachable error is received.
EFI_PROTOCOL_UNREACHABLE. The transmission fails because an ICMP protocol unreachable error is
received.
EFI_PORT_UNREACHABLE. The transmission fails and an ICMP port unreachable error is received.
EFI_ICMP_ERROR. The transmission fails and some other ICMP error is received.
EFI_DEVICE_ERROR. An unexpected system or network error occurs.
EFI_NO_MEDIA. There was a media error
28.1. EFI TCPv4 Protocol 1097Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
RxData When this token is used for receiving, RxData is a pointer to EFI_TCP4_RECEIVE_DATA . Type
EFI_TCP4_RECEIVE_DATA is deﬁned below.
TxData When this token is used for transmitting, TxData is a pointer to EFI_TCP4_TRANSMIT_DATA . Type
EFI_TCP4_TRANSMIT_DATA is deﬁned below.
TheEFI_TCP4_IO_TOKEN structures are used for both transmit and receive operations.
When used for transmitting, the CompletionToken.Event andTxData ﬁelds must be ﬁlled in by the user. After the
transmit operation completes, the CompletionToken.Status ﬁeld is updated by the instance and the Event is signaled.
• When used for receiving, the CompletionToken.Event andRxData ﬁelds must be ﬁlled in by the user. After a
receive operation completes, RxData andStatus are updated by the instance and the Event is signaled.
*******************************************************
// TCP4 Token Status definition
//
#define EFI_CONNECTION_FIN EFIERR (104)
#define EFI_CONNECTION_RESET EFIERR (105)
#define EFI_CONNECTION_REFUSED EFIERR (106)
NOTE :EFIERR() sets the maximum bit. Similar to how error codes are described in Status Codes .
// EFI_TCP4_RECEIVE_DATA
BOOLEAN UrgentFlag;
UINT32 FragmentCount;
EFI_TCP4_FRAGMENT_DATA FragmentTable[1];
} EFI_TCP4_RECEIVE_DATA;
UrgentFlag Whether those data are urgent. When this ﬂag is set, the instance is in urgent mode. The implementations
of this speciﬁcation should follow RFC793 to process urgent data, and should NOT mix the data across the urgent
point in one token.
DataLength When calling Receive() function, it is the byte counts of all Fragmentbuffer in FragmentTable allocated
by user. When the token is signaled by TCPv4 driver it is the length of received data in the fragments.
FragmentCount Number of fragments.
FragmentTable An array of fragment descriptors. Type EFI_TCP4_FRAGMENT_DATA is deﬁned below.
When TCPv4 driver wants to deliver received data to the application, it will pick up the ﬁrst queued receiving token,
update its Token->Packet.RxData then signal the Token->CompletionToken.Event .
• The FragmentBuffers inFragmentTable are allocated by the application when calling Receive() function and
received data will be copied to those buffers by the driver. FragmentTable may contain multiple buffers that are
NOT in the continuous memory locations. The application should combine those buffers in the FragmentTable
to process data if necessary.
// EFI_TCP4_FRAGMENT_DATA
} EFI_TCP4_FRAGMENT_DATA;
28.1. EFI TCPv4 Protocol 1098Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_TCP4_FRAGMENT_DATA allows multiple receive or transmit buffers to be speciﬁed. The purpose of this struc-
ture is to provide scattered read and write.
// EFI_TCP4_TRANSMIT_DATA
BOOLEAN Push;
BOOLEAN Urgent;
} EFI_TCP4_TRANSMIT_DATA;
Push IfTRUE, data must be transmitted promptly, and the PUSH bit in the last TCP segment created will be set. If
FALSE, data transmission may be delay to combine with data from subsequent Transmit() s for efﬁciency.
Urgent The data in the fragment table are urgent and urgent point is in effect if TRUE . Otherwise those data are NOT
considered urgent.
DataLength Length of the data in the fragments.
FragmentTable A array of fragment descriptors. Type EFI_TCP4_FRAGMENT_DATA is deﬁned above.
The EFI TCPv4 Protocol user must ﬁll this data structure before sending a packet. The packet may contain multiple
buffers in non-continuous memory locations.
EFI_SUCCESS The data has been queued for transmission.
•Token->CompletionToken.Event isNULL .
•Token->Packet.TxData isNULL .
•Token->Packet.FragmentCount is zero.
•Token->Packet.DataLength is not equal to the sum of fragment lengths.
• A transmit completion token with the same Token->
CompletionToken.Event was already in the transmission queue.
• The current instance is in Tcp4StateClosed state.
• The current instance is a passive one and it is in Tcp4StateListen state.
• User has called Close() to disconnect this connection.
28.1. EFI TCPv4 Protocol 1099Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.6 – continued from previous page
EFI_NOT_READY The completion token could not be queued because the transmit queue is
full.
EFI_OUT_OF_RESOURCES Could not queue the transmit data because of resource shortage.
EFI_NETWORK_UNREACHABLE There is no route to the destination network or address.
28.1.10.1 EFI_TCP4_PROTOCOL.Receive()
Summary
Places an asynchronous receive request into the receiving queue.
Prototype
typedef
(EFIAPI *EFI_TCP4_RECEIVE) (
);
Token Pointer to a token that is associated with the receive data descriptor. Type EFI_TCP4_IO_TOKEN is deﬁned
inEFI_TCP4_PROTOCOL .Transmit() .
The caller must allocate the Token->CompletionToken.Event and the FragmentBuffer used to receive data. He also
must ﬁll the DataLength which represents the whole length of all FragmentBuffer . When the receive operation com-
pletes, the EFI TCPv4 Protocol driver updates the Token->CompletionToken.Status andToken->Packet.RxData ﬁelds
and the Token->CompletionToken.Event is signaled. If got data the data and its length will be copy into the Fragment-
Table, in the same time the full length of received data will be recorded in the DataLength ﬁelds. Providing a proper
notiﬁcation function and context for the event will enable the user to receive the notiﬁcation and receiving status. That
notiﬁcation function is guaranteed to not be re-entered.
28.1. EFI TCPv4 Protocol 1100Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.7 – continued from previous page
•Token->Packet.RxData isNULL .
•Token->Packet.RxData->DataLength is0.
• The Token->Packet .RxData->DataLength is not the sum of all
FragmentBuffer length in FragmentTable.
EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of system
resources (usually memory).
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI TCPv4 Protocol
• A receive completion token with the same
Token->CompletionToken.Event was already in the receive queue.

EFI_CONNECTION_FIN The communication peer has closed the connection and there is no any
buffered data in the receive buffer of this instance.
28.1.11 EFI_TCP4_PROTOCOL.Close()
Summary
Disconnecting a TCP connection gracefully or reset a TCP connection. This function is a nonblocking operation.
Prototype
typedef
(EFIAPI *EFI_TCP4_CLOSE)(
IN EFI_TCP4_CLOSE_TOKEN *CloseToken
);
CloseToken Pointer to the close token to return when operation ﬁnishes. Type EFI_TCP4_CLOSE_TOKEN is deﬁned
in “Related Deﬁnition” below.
// EFI_TCP4_CLOSE_TOKEN
28.1. EFI TCPv4 Protocol 1101Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BOOLEAN AbortOnClose;
} EFI_TCP4_CLOSE_TOKEN;
Status When close ﬁnishes or meets any unexpected error it will be set to one of the following values:
EFI_SUCCESS. The close operation completes successfully.
EFI_ABORTED. User called conﬁgure with NULL without close stopping.
AbortOnClose Abort the TCP connection on close instead of the standard TCP close process when it is set to TRUE .
This option can be used to satisfy a fast disconnect.
Initiate an asynchronous close token to TCP driver. After Close() is called, any buffered transmission data will be sent
by TCP driver and the current instance will have a graceful close working ﬂow described as RFC 793 if AbortOnClose
is set to FALSE, otherwise, a rest packet will be sent by TCP driver to fast disconnect this connection. When the close
operation completes successfully the TCP instance is in Tcp4StateClosed state, all pending asynchronous operation is
signaled and any buffers used for TCP network trafﬁc is ﬂushed.
EFI_SUCCESS TheClose() is called successfully.
•Conﬁgure() has been called with TcpConﬁgData set to NULL and this
function has not returned.
• Previous Close() call on this instance has not ﬁnished.
•CloseToken isNULL .
•CloseToken->CompletionToken .Event isNULL .
28.1. EFI TCPv4 Protocol 1102Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.1.12 EFI_TCP4_PROTOCOL.Cancel()
Summary
Abort an asynchronous connection, listen, transmission or receive request.
Prototype
typedef
(EFIAPI *EFI_TCP4_CANCEL)(
IN EFI_TCP4_COMPLETION_TOKEN *Token OPTIONAL
);
Token Pointer to a token that has been issued by
EFI_TCP4_PROTOCOL.Connect() ,
EFI_TCP4_PROTOCOL.Accept() ,
EFI_TCP4_PROTOCOL.Transmit() or
EFI_TCP4_PROTOCOL.Receive() . IfNULL , all pending tokens issued by above four functions will be
aborted. Type
EFI_TCP4_COMPLETION_TOKEN is deﬁned in
EFI_TCP4_PROTOCOL.Connect() .
The Cancel() function aborts a pending connection, listen, transmit or receive request. If Token is not NULL and
the token is in the connection, listen, transmission or receive queue when it is being cancelled, its Token->Status will
be set to EFI_ABORTED and then Token->Event will be signaled. If the token is not in one of the queues, which
usually means that the asynchronous operation has completed, EFI_NOT_FOUND is returned. If Token isNULL all
asynchronous token issued by Connect(), Accept(), Transmit() andReceive() will be aborted.
EFI_SUCCESS The asynchronous I/O request is aborted and Token->Event is signaled.
EFI_NOT_STARTED This instance hasn’t been conﬁgured.
EFI_NO_MAPPING When using the default address, conﬁguration (DHCP, BOOTP, RARP, etc.)
hasn’t ﬁnished yet.
EFI_NOT_FOUND The asynchronous I/O request isn’t found in the transmission or receive
queue. It has either completed or wasn’t issued by Transmit() andReceive() .
EFI_UNSUPPORTED The implementation does not support this function.
28.1. EFI TCPv4 Protocol 1103Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.1.13 EFI_TCP4_PROTOCOL.Poll()
Summary
Poll to receive incoming data and transmit outgoing segments.
Prototype
typedef
(EFIAPI *EFI_TCP4_POLL) (
IN EFI_TCP4_PROTOCOL *This
);
ThePoll() function increases the rate that data is moved between the network and application and can be called when
the TCP instance is created successfully. Its use is optional.
In some implementations, the periodical timer in the MNP driver may not poll the underlying communications device
fast enough to avoid drop packets. Drivers and applications that are experiencing packet loss should try calling the
Poll() function in a high frequency.
EFI_NOT_READY No incoming or outgoing data is processed.
EFI_TIMEOUT Data was dropped out of the transmission or receive queue. Consider in-
28.2 EFI TCPv6 Protocol
This section deﬁnes the EFI TCPv6 (Transmission Control Protocol version 6) Protocol.
28.2.1 TCPv6 Service Binding Protocol
28.2.2 EFI_TCP6_SERVICE_BINDING_PROTOCOL
Summary
The EFI TCPv6 Service Binding Protocol is used to locate EFI TCPv6 Protocol drivers to create and destroy protocol
child instance of the driver to communicate with other host using TCP protocol.
GUID
#define EFI_TCP6_SERVICE_BINDING_PROTOCOL_GUID \
{0xec20eb79,0x6c1a,0x4664,\
{0x9a,0x0d,0xd2,0xe4,0xcc,0x16,0xd6, 0x64}}
28.2. EFI TCPv6 Protocol 1104Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
A network application that requires TCPv6 I/O services can call one of the protocol handler services, such as BS-
>LocateHandleBuffer(), to search devices that publish an EFI TCPv6 Service Binding Protocol GUID. Such device
supports the EFI TCPv6 Protocol and may be available for use.
After a successful call to the EFI_TCP6_SERVICE_BINDING_PROTOCOL.CreateChild() function, the newly
created child EFI TCPv6 Protocol driver is in an un-conﬁgured state; it is not ready to do any operation except Poll()
send and receive data packets until conﬁgured.
Every successful call to the EFI_TCP6_SERVICE_BINDING_PROTOCOL.CreateChild() function must be
matched with a call to the EFI_TCP6_SERVICE_BINDING_PROTOCOL.DestroyChild() function to release the
protocol driver.
28.2.3 TCPv6 Protocol
28.2.4 EFI_TCP6_PROTOCOL
Summary
The EFI TCPv6 Protocol provides services to send and receive data stream.
GUID
#define EFI_TCP6_PROTOCOL_GUID \
{0x46e44855,0xbd60,0x4ab7,\
{0xab,0x0d,0xa6,0x79,0xb9,0x44,0x7d,0x77}}
typedef struct _EFI_TCP6_PROTOCOL {
EFI_TCP6_GET_MODE_DATA GetModeData;
EFI_TCP6_CONFIGURE Configure;
EFI_TCP6_CONNECT Connect;
EFI_TCP6_ACCEPT Accept;
EFI_TCP6_TRANSMIT Transmit;
EFI_TCP6_RECEIVE Receive;
EFI_TCP6_CLOSE Close;
EFI_TCP6_CANCEL Cancel;
EFI_TCP6_POLL Poll;
} EFI_TCP6_PROTOCOL;
Conﬁgure Initialize, change, or brutally reset operational settings of the EFI TCPv6 Protocol. See the Conﬁgure()
Accept Listen for incoming TCP connection requests. This function is a nonblocking operation. See the Accept()
28.2. EFI TCPv6 Protocol 1105Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Close Gracefully disconnect a TCP connection follow RFC 793 or reset a TCP connection. This function is a non-
blocking operation. See the Close() function description.

TheEFI_TCP6_PROTOCOL deﬁnes the EFI TCPv6 Protocol child to be used by any network drivers or applications
to send or receive data stream. It can either listen on a speciﬁed port as a service or actively connect to remote peer as
a client. Each instance has its own independent settings.
Note :Byte Order: In this document, all IPv6 addresses and incoming/outgoing packets are stored in network byte
order. All other parameters in the functions and data structures that are deﬁned in this document are stored in host
byte order unless explicitly speciﬁed .
28.2.5 EFI_TCP6_PROTOCOL.GetModeData()
Summary
Prototype
typedef
(EFIAPI *EFI_TCP6_GET_MODE_DATA) (
IN EFI_TCP6_PROTOCOL *This,
OUT EFI_TCP6_CONNECTION_STATE *Tcp6State OPTIONAL,
OUT EFI_TCP6_CONFIG_DATA *Tcp6ConfigData OPTIONAL,
OUT EFI_IPv6_MODE_DATA *Ip6ModeData OPTIONAL,
);
This Pointer to the EFI_TCP6_PROTOCOL instance.
Tcp6State The buffer in which the current TCP state is returned. Type EFI_TCP6_CONNECTION_STATE is deﬁned
Tcp6ConﬁgData The buffer in which the current TCP conﬁguration is returned. Type EFI_TCP6_CONFIG_DATA
Ip6ModeData The buffer in which the current IPv6 conﬁguration data used by the TCP instance is returned. Type
EFI_IP6_MODE_DATA is deﬁned in EFI_IP6_PROTOCOL.GetModeData() .
MnpConﬁgData The buffer in which the current MNP conﬁguration data used indirectly by the
TCP instance is returned. Type EFI_MANAGED_NETWORK_CONFIG_DATA is deﬁned in
SnpModeData The buffer in which the current SNP mode data used indirectly by the TCP instance is returned. Type
The GetModeData() function copies the current operational settings of this EFI TCPv6 Protocol instance into user-
supplied buffers. This function can also be used to retrieve the operational setting of underlying drivers such as IPv6,
28.2. EFI TCPv6 Protocol 1106Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_IPv6_ADDRESS StationAddress;
EFI_IPv6_ADDRESS RemoteAddress;
} EFI_TCP6_ACCESS_POINT;
StationAddress The local IP address assigned to this TCP instance. The EFI TCPv6 driver will only deliver incoming
packets whose destination addresses exactly match the IP address. Set to zero to let the underlying IPv6 driver
choose a source address. If not zero it must be one of the conﬁgured IP addresses in the underlying IPv6 driver.
StationPort The local port number to which this EFI TCPv6 Protocol instance is bound. If the instance doesn’t care
RemoteAddress The remote IP address to which this EFI TCPv6 Protocol instance is connected. If ActiveFlag is
FALSE (i.e., a passive TCPv6 instance), the instance only accepts connections from the RemoteAddress . If
ActiveFlag isTRUE the instance will connect to the RemoteAddress, i.e., outgoing segments will be sent to this
address and only segments from this address will be delivered to the application. When ActiveFlag isFALSE, it
can be set to zero and means that incoming connection requests from any address will be accepted.
RemotePort The remote port to which this EFI TCPv6 Protocol instance connects or from which connection request
will be accepted by this EFI TCPv6 Protocol instance. If ActiveFlag isFALSE it can be zero and means that
incoming connection request from any port will be accepted. Its value can not be zero when ActiveFlag is
TRUE .
ActiveFlag Set it to TRUE to initiate an active open. Set it to FALSE to initiate a passive open to act as a
server.
// EFI_TCP6_OPTION
} EFI_TCP6_OPTION;
28.2. EFI TCPv6 Protocol 1107Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
disabled.
disabled.
2883.
// EFI_TCP6_CONFIG_DATA
UINT8 TrafficClass;
UINT8 HopLimit;
EFI_TCP6_ACCESS_POINT AccessPoint;
EFI_TCP6_OPTION *ControlOption;
} EFI_TCP6_CONFIG_DATA;
TrafﬁcClass TrafﬁcClass ﬁeld in transmitted IPv6 packets.
HopLimit HopLimit ﬁeld in transmitted IPv6 packets.
28.2. EFI TCPv6 Protocol 1108Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_TCP6_CONNECTION_STATE
Tcp6StateClosed = 0,
Tcp6StateListen = 1,
Tcp6StateSynSent = 2,
Tcp6StateSynReceived = 3,
Tcp6StateEstablished = 4,
Tcp6StateFinWait1 = 5,
Tcp6StateFinWait2 = 6,
Tcp6StateClosing = 7,
Tcp6StateTimeWait = 8,
Tcp6StateCloseWait = 9,
Tcp6StateLastAck = 10
} EFI_TCP6_CONNECTION_STATE;
28.2.6 EFI_TCP6_PROTOCOL.Conﬁgure()
Summary
Initialize or brutally reset the operational parameters for this TCP instance.
Prototype
typedef
(EFIAPI *EFI_TCP6_CONFIGURE) (
IN EFI_TCP6_CONFIG_DATA *Tcp6ConfigData OPTIONAL
);

Summary
Prototype
typedef
);
Tcp6ConﬁgData Pointer to the conﬁgure data to conﬁgure the instance.
• Initialize this TCP instance, i.e., initialize the communication end settings and specify active open or passive
• Reset this TCP instance brutally, i.e., cancel all pending asynchronous tokens, ﬂush transmission and receiving
buffer directly without informing the communication peer.
No other TCPv6 Protocol operation except Poll() can be executed by this instance until it is conﬁgured properly. For
an active TCP instance, after a proper conﬁguration it may call Connect() to initiates the three-way handshake. For a
passive TCP instance, its state will transit to Tcp6StateListen after conﬁguration, and Accept() may be called to listen
28.2. EFI TCPv6 Protocol 1109Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
the incoming TCP connection requests. If Tcp6ConﬁgData is set to NULL, the instance is reset. Resetting process will
be done brutally, the state machine will be set to Tcp6StateClosed directly, the receive queue and transmit queue will
be ﬂushed, and no trafﬁc is allowed through this instance.
EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source address
for this instance, but no source address was available for use.
One or more of the following conditions are TRUE :
•Tcp6Conﬁg Data->AccessPoint.StationAddress is neither zero nor one of
the conﬁgured IP addresses in the underlying IPv6 driver.
•Tcp6Conﬁ gData->AccessPoint.RemoteAddress isn’t a valid unicast IPv6
address.
•Tcp6Conﬁ gData->AccessPoint.RemoteAddress is zero or Tcp6Co
nﬁgData->AccessPoint.RemotePort is zero when Tcp6Co
nﬁgData->AccessPoint.ActiveFlag isTRUE .
28.2.7 EFI_TCP6_PROTOCOL.Connect()
Summary
Prototype
typedef
(EFIAPI *EFI_TCP6_CONNECT) (
IN EFI_TCP6_CONNECTION_TOKEN *ConnectionToken
);
ConnectionToken Pointer to the connection token to return when the TCP three-way handshake ﬁnishes. Type
EFI_TCP6_CONNECTION_TOKEN is deﬁned in Related Deﬁnition below.
be called for the TCP instance in Tcp6StateClosed state. The instance will transfer into Tcp6StateSynSent if the
28.2. EFI TCPv6 Protocol 1110Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
function returns EFI_SUCCESS . If TCP three-way handshake succeeds, its state will become Tcp6StateEstablished,
otherwise, the state will return to Tcp6StateClosed .
// EFI_TCP6_COMPLETION_TOKEN
} EFI_TCP6_COMPLETION_TOKEN;
Event The Event to signal after request is ﬁnished and Status ﬁeld is updated by the EFI TCPv6 Protocol driver. The
type of Event must be EVT_NOTIFY_SIGNAL .
Status The result of the completed operation. EFI_NO_MEDIA . There was a media error
TheEFI_TCP6_COMPLETION_TOKEN is used as a common header for various asynchronous tokens.
// EFI_TCP6_CONNECTION_TOKEN
EFI_TCP6_COMPLETION_TOKEN CompletionToken;
} EFI_TCP6_CONNECTION_TOKEN;
EFI_SUCCESS : The active open succeeds and the instance’s state is Tcp6StateEstablished.
EFI_CONNECTION_RESET : The connect fails because the connection is reset either by instance itself or
the communication peer.
EFI_CONNECTION_REFUSED: The receiving or transmission operation fails because this connection is
refused.
EFI_ABORTED: The active open is aborted.
EFI_TIMEOUT: The connection establishment timer expires and no more speciﬁc information is available.
EFI_NETWORK_UNREACHABLE : The active open fails because an ICMP network unreachable error is
received.
EFI_HOST_UNREACHABLE : The active open fails because an ICMP host unreachable error is received.
EFI_PROTOCOL_UNREACHABLE : The active open fails because an ICMP protocol unreachable error is
received.
28.2. EFI TCPv6 Protocol 1111Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_PORT_UNREACHABLE : The connection establishment timer times out and an ICMP port unreachable
EFI_ICMP_ERROR : The connection establishment timer times out and some other ICMP error is received.
EFI_DEVICE_ERROR : An unexpected system or network error occurred.
EFI_SECURITY_VIOLATION : The active open was failed because of IPSec policy check.
EFI_SUCCESS The connection request is successfully initiated and the state of this TCP
instance has been changed to Tcp6StateSynSent .
EFI_NOT_STARTED This EFI TCPv6 Protocol instance has not been conﬁgured.
• This instance is not in Tcp6StateClosed state.
One or more of the following are TRUE: .This isNULL .
•ConnectionToken->CompletionToken.Event isNULL .
28.2.8 EFI_TCP6_PROTOCOL.Accept()
Summary
Prototype
typedef
(EFIAPI *EFI_TCP6_ACCEPT) (
IN EFI_TCP6_LISTEN_TOKEN *ListenToken
);
ListenToken Pointer to the listen token to return when operation ﬁnishes. Type EFI_TCP6_LISTEN_TOKEN is
deﬁned in Related Deﬁnition below.
28.2. EFI TCPv6 Protocol 1112Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_TCP6_LISTEN_TOKEN
} EFI_TCP6_LISTEN_TOKEN;
EFI_SUCCESS : A remote peer has successfully established a connection to this instance. A new TCP
EFI_CONNECTION_RESET : The accept fails because the connection is reset either by instance itself or
EFI_ABORTED : The accept request has been aborted.
EFI_SECURITY_VIOLATION : The accept operation was failed because of IPSec policy check.
The Accept() function initiates an asynchronous accept request to wait for an incoming connection on the passive
TCP instance. If a remote peer successfully establishes a connection with this instance, a new TCP instance will
be created and its handle will be returned in ListenToken->NewChildHandle . The newly created instance is conﬁg-
ured by inheriting the passive instance’s conﬁguration and is ready for use upon return. The new instance is in the
Tcp6StateEstablished state.
This function only can be called when current TCP instance is in Tcp6StateListen state.
One or more of the following are TRUE:
• This instance is not in Tcp6StateListen state.

28.2. EFI TCPv6 Protocol 1113Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.14 – continued from previous page
28.2.9 EFI_TCP6_PROTOCOL.Transmit()
Summary
Prototype
typedef
(EFIAPI *EFI_TCP6_TRANSMIT) (
IN EFI_TCP6_IO_TOKEN *Token
);
Token Pointer to the completion token to queue to the transmit queue. Type EFI_TCP6_IO_TOKEN is deﬁned in
TheTransmit() function queues a sending request to this TCP instance along with the user data. The status of the token
is updated and the event in the token will be signaled once the data is sent out or some error occurs.
// EFI_TCP6_IO_TOKEN
union {
EFI_TCP6_RECEIVE_DATA *RxData;
EFI_TCP6_TRANSMIT_DATA *TxData;
} Packet;
} EFI_TCP6_IO_TOKEN;
EFI_SUCCESS: The receiving or transmission operation completes successfully.
EFI_CONNECTION_FIN: The receiving operation fails because the communication peer has closed the
28.2. EFI TCPv6 Protocol 1114Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_CONNECTION_RESET: The receiving or transmission operation fails because this connection is reset
either by instance itself or the communication peer.
EFI_ABORTED: The receiving or transmission is aborted.
EFI_TIMEOUT: The transmission timer expires and no more speciﬁc information is available.
EFI_NETWORK_UNREACHABLE: The transmission fails because an ICMP network unreachable error is
received.
EFI_HOST_UNREACHABLE: The transmission fails because an ICMP host unreachable error is received.
EFI_PROTOCOL_UNREACHABLE: The transmission fails because an ICMP protocol unreachable error is
received.
EFI_PORT_UNREACHABLE: The transmission fails and an ICMP port unreachable error is received.
EFI_ICMP_ERROR: The transmission fails and some other ICMP error is received.
EFI_DEVICE_ERROR: An unexpected system or network error occurs.
EFI_SECURITY_VIOLATION : The receiving or transmission operation was failed because of IPSec policy
check.
RxData When this token is used for receiving, RxData is a pointer to EFI_TCP6_RECEIVE_DATA . Type
EFI_TCP6_RECEIVE_DATA is deﬁned below.
TxData When this token is used for transmitting, TxData is a pointer to EFI_TCP6_TRANSMIT_DATA . Type
EFI_TCP6_TRANSMIT_DATA is deﬁned below.
The EFI_TCP6_IO_TOKEN structure is used for both transmit and receive operations.
When used for transmitting, the CompletionToken.Event and TxData ﬁelds must be ﬁlled in by the user. After the
When used for receiving, the CompletionToken.Event and RxData ﬁelds must be ﬁlled in by the user. After a receive
operation completes, RxData and Status are updated by the instance and the Event is signaled.
// EFI_TCP6_RECEIVE_DATA
EFI_TCP6_FRAGMENT_DATA FragmentTable[1];
} EFI_TCP6_RECEIVE_DATA;
UrgentFlag Whether the data is urgent. When this ﬂag is set, the instance is in urgent mode. The implementations of
this speciﬁcation should follow RFC793 to process urgent data, and should NOT mix the data across the urgent
DataLength When calling Receive() function, it is the byte counts of all Fragmentbuffer inFragmentTable allocated
by user. When the token is signaled by TCPv6 driver it is the length of received data in the fragments.
FragmentTable An array of fragment descriptors. Type EFI_TCP6_FRAGMENT_DATA is deﬁned below.
When TCPv6 driver wants to deliver received data to the application, it will pick up the ﬁrst queued receiving token,
The FragmentBuffer inFragmentTable is allocated by the application when calling Receive() function and received
data will be copied to those buffers by the driver. FragmentTable may contain multiple buffers that are NOT in the
continuous memory locations. The application should combine those buffers in the FragmentTable to process data if
necessary.
28.2. EFI TCPv6 Protocol 1115Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_TCP6_FRAGMENT_DATA
} EFI_TCP6_FRAGMENT_DATA;
FragmentBuffer Pointer to the data buffer in the fragment. EFI_TCP6_FRAGMENT_DATA allows multiple receive
or transmit buffers to be speciﬁed. The purpose of this structure is to provide scattered read and write.
// EFI_TCP6_TRANSMIT_DATA
} EFI_TCP6_TRANSMIT_DATA;
FALSE, data transmission may be delayed to combine with data from subsequent Transmit() s for efﬁciency.
FragmentTable An array of fragment descriptors. Type EFI_TCP6_FRAGMENT_DATA is deﬁned above.
The EFI TCPv6 Protocol user must ﬁll this data structure before sending a packet. The packet may contain multiple
28.2. EFI TCPv6 Protocol 1116Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.15 – continued from previous page
• The current instance is in Tcp6StateClosed state.
• The current instance is a passive one and it is in Tcp6StateListen state.
full.
28.2.10 EFI_TCP6_PROTOCOL.Receive()
Summary
Prototype
typedef
(EFIAPI *EFI_TCP6_RECEIVE) (
);
Token Pointer to a token that is associated with the receive data descriptor. Type EFI_TCP6_IO_TOKEN is deﬁned
inEFI_TCP6_PROTOCOL.Transmit() .
TheReceive () function places a completion token into the receive packet queue. This function is always asynchronous.
The caller must allocate the Token->CompletionToken.Event and the FragmentBuffer used to receive data. The caller
also must ﬁll the DataLength which represents the whole length of all FragmentBuffer . When the receive operation
completes, the EFI TCPv6 Protocol driver updates the Token->CompletionToken.Status andToken->Packet.RxData
ﬁelds and the Token->CompletionToken.Event is signaled. If got data the data and its length will be copied into the
FragmentTable, at the same time the full length of received data will be recorded in the DataLength ﬁelds. Providing

);
a proper notiﬁcation function and context for the event will enable the user to receive the notiﬁcation and receiving
status. That notiﬁcation function is guaranteed to not be re-entered.
28.2. EFI TCPv6 Protocol 1117Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.16 – continued from previous page
•Token->Packet.RxData->DataLength is 0.
• The Token->Packet.RxData->DataLength is not the sum of all
FragmentBuffer length in FragmentTable .
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI TCPv6 Protocol
28.2.11 EFI_TCP6_PROTOCOL.Close()
Summary
Prototype
typedef
(EFIAPI *EFI_TCP6_CLOSE)(
IN EFI_TCP6_CLOSE_TOKEN *CloseToken
);
CloseToken Pointer to the close token to return when operation ﬁnishes. Type EFI_TCP6_CLOSE_TOKEN is deﬁned
in Related Deﬁnition below.
// EFI_TCP6_CLOSE_TOKEN
28.2. EFI TCPv6 Protocol 1118Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_TCP6_CLOSE_TOKEN;
EFI_SUCCESS : The close operation completes successfully.
EFI_ABORTED : User called conﬁgure with NULL without close stopping.
EFI_SECURITY_VIOLATION : The close operation was failed because of IPSec policy check
operation completes successfully the TCP instance is in Tcp6StateClosed state, all pending asynchronous operations
are signaled and any buffers used for TCP network trafﬁc are ﬂushed.
•CloseToken orCloseToken->CompletionToken.Event is already in use.
•CloseToken->CompletionToken.Event isNULL .
28.2. EFI TCPv6 Protocol 1119Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.2.12 EFI_TCP6_PROTOCOL.Cancel()
Summary
Prototype
typedef
(EFIAPI *EFI_TCP6_CANCEL)(
IN EFI_TCP6_COMPLETION_TOKEN *Token OPTIONAL
);
EFI_TCP6_PROTOCOL.Connect(),
EFI_TCP6_PROTOCOL.Accept(),
EFII_TCP6_PROTOCOL.Transmit() or
EFI_TCP6_PROTOCOL.Receive() . IfNULL , all pending tokens issued by above four functions will be
EFI_TCP6_COMPLETION_TOKEN is deﬁned in
EFI_TCP6_PROTOCOL.Connect() .
TheCancel() function aborts a pending connection, listen, transmit or receive request. If Token is not NULL and the
token is in the connection, listen, transmission or receive queue when it is being cancelled, its T oken->Status will
28.2. EFI TCPv6 Protocol 1120Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.2.13 EFI_TCP6_PROTOCOL.Poll()
Summary
Prototype
typedef
(EFIAPI *EFI_TCP6_POLL) (
IN EFI_TCP6_PROTOCOL *This
);
28.3 EFI IPv4 Protocol
This section deﬁnes the EFI IPv4 (Internet Protocol version 4) Protocol interface. It is split into the following three
main sections:
•EFI IPv4 Service Binding Protocol
•EFI IPv4 Variable
•EFI IPv4 Protocol
The EFI IPv4 Protocol provides basic network IPv4 packet I/O services, which includes support for a subset of the
Internet Control Message Protocol (ICMP) and may include support for the Internet Group Management Protocol
(IGMP).
The EFI IPv4 Protocol supports IPv4 classless IP addressing, and deprecates the original IPv4 classful IP addressing.
Please see links to the following RFC documents at http://ueﬁ.org/ueﬁ :
1. RFC 1122 — “Requirements for Internet Hosts –Communication Layers”,**
2. RFC 4632 — “Classless Inter-domain Routing (CIDR): The Internet Address Assignment and Aggregation
Plan”,
28.3. EFI IPv4 Protocol 1121Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3. RFC 3021 — “Using 31-Bit Preﬁxes on IPv4 Point-to-Point Links”
28.3.1 IP4 Service Binding Protocol
28.3.2 EFI_IP4_SERVICE_BINDING_PROTOCOL
Summary
The EFI IPv4 Service Binding Protocol is used to locate communication devices that are supported by an EFI IPv4
Protocol driver and to create and destroy instances of the EFI IPv4 Protocol child protocol driver that can use the
underlying communications device.
GUID
#define EFI_IP4_SERVICE_BINDING_PROTOCOL_GUID \
{0xc51711e7,0xb4bf,0x404a,\
{0xbf,0xb8,0x0a,0x04,0x8e,0xf1,0xff,0xe4}}
A network application that requires basic IPv4 I/O services can use one of the protocol handler services, such as BS-
>LocateHandleBuffer(), to search for devices that publish an EFI IPv4 Service Binding Protocol GUID. Each device

Plan”,
Summary
GUID
with a published EFI IPv4 Service Binding Protocol GUID supports the EFI IPv4 Protocol and may be available for
use.
After a successful call to the EFI_IP4_SERVICE_BINDING_PROTOCOL .CreateChild() function, the newly created
child EFI IPv4 Protocol driver is in an unconﬁgured state; it is not ready to send and receive data packets.
EFI_IP4_SERVICE_BINDING_PROTOCOL .CreateChild() function must be matched with a call to the
EFI_IP4_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
28.3.3 IP4 Protocol
28.3.4 EFI_IP4_PROTOCOL
Summary
The EFI IPv4 Protocol implements a simple packet-oriented interface that can be used by drivers, daemons, and
applications to transmit and receive network packets.
GUID
#define EFI_IP4_PROTOCOL_GUID \
{0x41d94cd2,0x35b6,0x455a,\
{0x82,0x58,0xd4,0xe5,0x13,0x34,0xaa,0xdd}}
typedef struct _EFI_IP4_PROTOCOL {
EFI_IP4_GET_MODE_DATA GetModeData;
EFI_IP4_CONFIGURE Configure;
EFI_IP4_GROUPS Groups;
EFI_IP4_ROUTES Routes;
EFI_IP4_TRANSMIT Transmit;
EFI_IP4_RECEIVE Receive;
28.3. EFI IPv4 Protocol 1122Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_IP4_CANCEL Cancel;
EFI_IP4_POLL Poll;
} EFI_IP4_PROTOCOL;
GetModeData Gets the current operational settings for this instance of the EFI IPv4 Protocol driver. See the Get-
ModeData() function description.
Conﬁgure Changes or resets the operational settings for the EFI IPv4 Protocol. See the Conﬁgure() function descrip-
tion.
Groups Joins and leaves multicast groups. See the Groups() function description.
Routes Adds and deletes routing table entries. See the Routes() function description.
Transmit Places outgoing data packets into the transmit queue. See the Transmit() function description.
Receive Places a receiving request into the receiving queue. See the Receive() function description.
The EFI_IP4_PROTOCOL deﬁnes a set of simple IPv4, ICMPv4, and IGMPv4 services that can be used by any
network protocol driver, daemon, or application to transmit and receive IPv4 data packets.
NOTE: All the IPv4 addresses that are described in EFI_IP4_PROTOCOL are stored in network byte order. Both
incoming and outgoing IP packets are also in network byte order. All other parameters that are deﬁned in functions
or data structures are stored in host byte order .
28.3.5 EFI_IP4_PROTOCOL.GetModeData()
Summary
Gets the current operational settings for this instance of the EFI IPv4 Protocol driver.
Prototype
typedef
(EFIAPI *EFI_IP4_GET_MODE_DATA) (
IN EFI_IP4_PROTOCOL *This,
OUT EFI_IP4_MODE_DATA *Ip4ModeData OPTIONAL,
);
This Pointer to the EFI_IP4_PROTOCOL instance.
Ip4ModeData Pointer to the EFI IPv4 Protocol mode data structure. Type EFI_IP4_MODE_DATA is deﬁned in
MnpConﬁgData Pointer to the managed network conﬁguration data struc-
ture. Type EFI_MANAGED_NETWORK_CONFIG_DATA is deﬁned in
28.3. EFI IPv4 Protocol 1123Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SnpData Pointer to the simple network mode data structure. Type EFI_SIMPLE_NETWORK_MODE is deﬁned in
theEFI_SIMPLE_NETWORK_PROTOCOL .
The GetModeData() function returns the current operational mode data for this driver instance. The data ﬁelds in
EFI_IP4_MODE_DATA are read only. This function is used optionally to retrieve the operational mode data of under-
lying networks or drivers.
// EFI_IP4_MODE_DATA
BOOLEAN IsStarted;
EFI_IP4_CONFIG_DATA ConfigData;
BOOLEAN IsConfigured;
UINT32 GroupCount;
EFI_IPv4_ADDRESS *GroupTable;
UINT32 RouteCount;
EFI_IP4_ROUTE_TABLE RouteTable;
UINT32 IcmpTypeCount;
EFI_IP4_ICMP_TYPE *IcmpTypeList;
} EFI_IP4_MODE_DATA;
IsStarted Set to TRUE after this EFI IPv4 Protocol instance has been successfully conﬁgured with operational pa-
rameters by calling the Conﬁgure() interface when EFI IPv4 Protocol instance is stopped All other ﬁelds in this
structure are undeﬁned until this ﬁeld is TRUE .
Set to FALSE when the instance’s operational parameter has been reset.
MaxPackeSize The maximum packet size, in bytes, of the packet which the upper layer driver could feed.
ConﬁgData Current conﬁguration settings. Undeﬁned until IsStarted isTRUE . Type EFI_IP4_CONFIG_DATA is
IsConﬁgured Set to TRUE when the EFI IPv4 Protocol instance has a station address and subnet mask. If it is using
the default address, the default address has been acquired.
Set to FALSE when the EFI IPv4 Protocol driver is not conﬁgured.
GroupCount Number of joined multicast groups. Undeﬁned until IsConﬁgured isTRUE .
GroupTable List of joined multicast group addresses. Undeﬁned until IsConﬁgured isTRUE .
RouteCount Number of entries in the routing table. Undeﬁned until IsConﬁgured isTRUE .
RouteTable Routing table entries. Undeﬁned until IsConﬁgured isTRUE . Type EFI_IP4_ROUTE_TABLE is deﬁned
below.
IcmpTypeCount Number of entries in the supported ICMP types list.
IcmpTypeList Array of ICMP types and codes that are supported by this EFI IPv4 Protocol driver. Type
EFI_IP4_ICMP_TYPE is deﬁned below.
TheEFI_IP4_MODE_DATA structure describes the operational state of this IPv4 interface.
// EFI_IP4_CONFIG_DATA
28.3. EFI IPv4 Protocol 1124Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT8 DefaultProtocol;
BOOLEAN AcceptAnyProtocol;
BOOLEAN AcceptIcmpErrors;
BOOLEAN AcceptBroadcast;
BOOLEAN AcceptPromiscuous;
BOOLEAN DoNotFragment;
BOOLEAN RawData;
UINT32 ReceiveTimeout;
UINT32 TransmitTimeout;
} EFI_IP4_CONFIG_DATA;
DefaultProtocol The default IPv4 protocol packets to send and receive. Ignored when AcceptPromiscuous isTRUE .
An updated list of protocol numbers can be found at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ)
under the heading “IANA Assigned Internet Protocol Numbers list”.
AcceptAnyProtocol Set to TRUE to receive all IPv4 packets that get through the receive ﬁlters. Set to FALSE to
receive only the DefaultProtocol IPv4 packets that get through the receive ﬁlters. Ignored when AcceptPromis-
cuous isTRUE .
AcceptIcmpErrors Set to TRUE to receive ICMP error report packets. Ignored when AcceptPromiscuous orAccep-
tAnyProtocol isTRUE .
AcceptBroadcast Set to TRUE to receive broadcast IPv4 packets. Ignored when AcceptPromiscuous isTRUE . Set
toFALSE to stop receiving broadcast IPv4 packets.
AcceptPromiscuous Set to TRUE to receive all IPv4 packets that are sent to any hardware address or any protocol
address. Set to FALSE to stop receiving all promiscuous IPv4 packets.
UseDefaultAddress Set to TRUE to use the default IPv4 address and default routing table. If the default IPv4 address
is not available yet, then the EFI IPv4 Protocol driver will use EFI_IP4_CONFIG2_PROTOCOL to retrieve the
IPv4 address and subnet information. (This ﬁeld can be set and changed only when the EFI IPv4 driver is
transitioning from the stopped to the started states.)
StationAddress The station IPv4 address that will be assigned to this EFI IPv4Protocol instance. The EFI IPv4
Protocol driver will deliver only incoming IPv4 packets whose destination matches this IPv4 address exactly.
Address 0.0.0.0 is also accepted as a special case in which incoming packets destined to any station IP address
are always delivered. When EFI_IP4_CONFIG_DATA is used in Conﬁgure (), it is ignored if UseDefaultAd-
dress isTRUE; When EFI_IP4_CONFIG_DATA is used in GetModeData (), it contains the default address if
UseDefaultAddress isTRUE and the default address has been acquired.
SubnetMask The subnet address mask that is associated with the station address. When EFI_IP4_CONFIG_DATA
is used in Conﬁgure (), it is ignored if UseDefaultAddress isTRUE ; When EFI_IP4_CONFIG_DATA is used
inGetModeData (), it contains the default subnet mask if UseDefaultAddress isTRUE and the default address
has been acquired.
DoNotFragment State of the DoNotFragment bit in transmitted IPv4 packets.

RawData Set to TRUE to send and receive unformatted packets. The other IPv4 receive ﬁlters are still applied.
Fragmentation is disabled for RawData mode. NOTE: Unformatted packets include the IP header and payload.
The media header is appended automatically for outgoing packets by underlying network drivers.
28.3. EFI IPv4 Protocol 1125Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ReceiveTimeout The timer timeout value (number of microseconds) for the receive timeout event to be associated
with each assembled packet. Zero means do not drop assembled packets.
TransmitTimeout The timer timeout value (number of microseconds) for the transmit timeout event to be associated
with each outgoing packet. Zero means do not drop outgoing packets.
TheEFI_IP4_CONFIG_DATA structure is used to report and change IPv4 session parameters.
// EFI_IP4_ROUTE_TABLE
EFI_IPv4_ADDRESS SubnetAddress;
EFI_IPv4_ADDRESS GatewayAddress;
} EFI_IP4_ROUTE_TABLE;
SubnetAddress The subnet address to be routed.
SubnetMask The subnet mask. If ( DestinationAddress &SubnetMask == SubnetAddress ), then the packet is to be
directed to the GatewayAddress .
GatewayAddress The IPv4 address of the gateway that redirects packets to this subnet. If the IPv4 address is 0.0.0.0,
then packets to this subnet are not redirected.
EFI_IP4_ROUTE_TABLE is the entry structure that is used in routing tables.
// EFI_IP4_ICMP_TYPE
} EFI_IP4_ICMP_TYPE
Type The type of ICMP message. See RFC 792 and RFC 950.
Code The code of the ICMP message, which further describes the different ICMP message formats under the same
Type. See RFC 792 and RFC 950.
EFI_IP4_ICMP_TYPE is used to describe those ICMP messages that are supported by this EFI IPv4 Protocol driver.
EFI_OUT_OF_RESOURCES The required mode data could not be allocated.
28.3.6 EFI_IP4_PROTOCOL.Conﬁgure()
Summary
Assigns an IPv4 address and subnet mask to this EFI IPv4 Protocol driver instance.
Prototype
typedef
(EFIAPI *EFI_IP4_CONFIGURE) (
28.3. EFI IPv4 Protocol 1126Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_IP4_CONFIG_DATA *IpConfigData OPTIONAL
);
IpConﬁgData Pointer to the EFI IPv4 Protocol conﬁguration data structure. Type EFI_IP4_CONFIG_DATA is de-
ﬁned in EFI_IP4_PROTOCOL .GetModeData() .
TheConﬁgure() function is used to set, change, or reset the operational parameters and ﬁlter settings for this EFI IPv4
Protocol instance. Until these parameters have been set, no network trafﬁc can be sent or received by this instance.
Once the parameters have been reset (by calling this function with IpConﬁgData set to NULL ), no more trafﬁc can
be sent or received until these parameters have been set again. Each EFI IPv4 Protocol instance can be started and
stopped independently of each other by enabling or disabling their receive ﬁlter settings with the Conﬁgure() function.
When IpConﬁgData.UseDefaultAddress is set to FALSE, the new station address will be appended as an alias ad-
dress into the addresses list in the EFI IPv4 Protocol driver. While set to TRUE, Conﬁgure() will trigger the
EFI_IP4_CONFIG2_PROTOCOL to retrieve the default IPv4 address if it is not available yet. Clients could fre-
quently call GetModeData() to check the status to ensure that the default IPv4 address is ready.
If operational parameters are reset or changed, any pending transmit and receive requests will be cancelled. Their
completion token status will be set to EFI_ABORTED and their events will be signaled.
EFI_SUCCESS The driver instance was successfully opened.
EFI_IP_ADDRESS_CONFLICT There is an address conﬂict in response to the Arp invocation
•IpConﬁgData.StationAddress is not a unicast IPv4 address.
•IpConﬁgData.SubnetMask is not a valid IPv4 subnet mask.
• A conﬁguration protocol (DHCP, BOOTP, RARP, etc.) could not be
located when clients choose to use the default IPv4 address. This EFI IPv4
Protocol implementation does not support this requested ﬁlter or timeout
setting.
EFI_OUT_OF_RESOURCES The EFI IPv4 Protocol driver instance data could not be allocated.
EFI_ALREADY_STARTED The interface is already open and must be stopped before the IPv4 address
or subnet mask can be changed. The interface must also be stopped when
switching to/from raw packet mode.
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI IPv4 Protocol
driver instance is not opened.
28.3. EFI IPv4 Protocol 1127Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.3.7 EFI_IP4_PROTOCOL.Groups()
Summary
Joins and leaves multicast groups.
Prototype
typedef
(EFIAPI *EFI_IP4_GROUPS) (
IN EFI_IPv4_ADDRESS *GroupAddress OPTIONAL
);
JoinFlag Set to TRUE to join the multicast group session and FALSE to leave.
GroupAddress Pointer to the IPv4 multicast address.
The Groups() function is used to join and leave multicast group sessions. Joining a group will enable reception of
matching multicast packets. Leaving a group will disable the multicast packet reception.
IfJoinFlag isFALSE andGroupAddress isNULL, all joined groups will be left.
One or more of the following is TRUE:
•JoinFlag isTRUE andGroupAddress isNULL .
•GroupAddress is not NULL and ** GroupAddress* is not a multicast
IPv4 address.
EFI_NOT_STARTED This instance has not been started.
EFI_OUT_OF_RESOURCES System resources could not be allocated.
EFI_UNSUPPORTED This EFI IPv4 Protocol implementation does not support multicast groups.
EFI_ALREADY_STARTED The group address is already in the group table (when JoinFlag isTRUE ).
EFI_NOT_FOUND The group address is not in the group table (when JoinFlag isFALSE ).
28.3. EFI IPv4 Protocol 1128Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.3.8 EFI_IP4_PROTOCOL.Routes()
Summary
Adds and deletes routing table entries.
Prototype
typedef
(EFIAPI *EFI_IP4_ROUTES) (
);
DeleteRoute Set to TRUE to delete this route from the routing table. Set to FALSE to add this route to the routing
table. SubnetAddress andSubnetMask are used as the key to each route entry.
SubnetAddress The address of the subnet that needs to be routed.
SubnetMask The subnet mask of SubnetAddress .
GatewayAddress The unicast gateway IPv4 address for this route.
TheRoutes() function adds a route to or deletes a route from the routing table.
Routes are determined by comparing the SubnetAddress with the destination IPv4 address arithmetically AND -ed with
theSubnetMask . The gateway address must be on the same subnet as the conﬁgured station address.
The default route is added with SubnetAddress andSubnetMask both set to 0.0.0.0. The default route matches all
destination IPv4 addresses that do not match any other routes.
AGatewayAddress that is zero is a nonroute. Packets are sent to the destination IP address if it can be found in the
ARP cache or on the local subnet. One automatic nonroute entry will be inserted into the routing table for outgoing
packets that are addressed to a local subnet (gateway address of 0.0.0.0).
Each EFI IPv4 Protocol instance has its own independent routing table. Those EFI IPv4 Protocol in-
stances that use the default IPv4 address will also have copies of the routing table that was provided by the
EFI_IP4_CONFIG2_PROTOCOL, and these copies will be updated whenever the EIF IPv4 Protocol driver recon-
ﬁgures its instances. As a result, client modiﬁcation to the routing table will be lost.
NOTE :There is no way to set up routes to other network interface cards because each network interface card has its
own independent network stack that shares information only through EFI IPv4 variable.

EFI_NOT_STARTED The driver instance has not been started.
28.3. EFI IPv4 Protocol 1129Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.23 – continued from previous page
• *SubnetAddress is not a valid subnet address.
• *SubnetMask is not a valid subnet mask.
• *GatewayAddress is not a valid unicast IPv4 address.
EFI_OUT_OF_RESOURCES Could not add the entry to the routing table.
EFI_NOT_FOUND This route is not in the routing table (when DeleteRoute isTRUE ).
EFI_ACCESS_DENIED The route is already deﬁned in the routing table (when DeleteRoute is
FALSE ).
28.3.9 EFI_IP4_PROTOCOL.Transmit()
Summary
Places outgoing data packets into the transmit queue.
Prototype
typedef
(EFIAPI *EFI_IP4_TRANSMIT) (
IN EFI_IP4_COMPLETION_TOKEN *Token
);
Token Pointer to the transmit token. Type EFI_IP4_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions”
below.
TheTransmit() function places a sending request in the transmit queue of this EFI IPv4 Protocol instance. Whenever
the packet in the token is sent out or some errors occur, the event in the token will be signaled and the status is updated.
// EFI_IP4_COMPLETION_TOKEN
union {
EFI_IP4_RECEIVE_DATA *RxData;
EFI_IP4_TRANSMIT_DATA *TxData;
} Packet;
} EFI_IP4_COMPLETION_TOKEN;
28.3. EFI IPv4 Protocol 1130Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Event This Event will be signaled after the Status ﬁeld is updated by the EFI IPv4 Protocol driver. The type of
Event must be EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of Event must be lower than or equal to
EFI_SUCCESS. The receive or transmit completed successfully.
EFI_ABORTED. The receive or transmit was aborted.
EFI_TIMEOUT. The transmit timeout expired.
EFI_ICMP_ERROR. An ICMP error packet was received.
EFI_NO_MEDIA . There was a media error
RxData When this token is used for receiving, RxData is a pointer to the EFI_IP4_RECEIVE_DATA . Type
EFI_IP4_RECEIVE_DATA is deﬁned below.
TxData When this token is used for transmitting, TxData is a pointer to the EFI_IP4_TRANSMIT_DATA . Type
EFI_IP4_TRANSMIT_DATA is deﬁned below.
EFI_IP4_COMPLETION_TOKEN structures are used for both transmit and receive operations.
When the structure is used for transmitting, the Event andTxData ﬁelds must be ﬁlled in by the EFI IPv4 Protocol
client. After the transmit operation completes, EFI IPv4 Protocol updates the Status ﬁeld and the Event is signaled.
When the structure is used for receiving, only the Event ﬁeld must be ﬁlled in by the EFI IPv4 Protocol client. After a
packet is received, the EFI IPv4 Protocol ﬁlls in the RxData andStatus ﬁelds and the Event is signaled. If the packet is
an ICMP error message, the Status is set to EFI_ICMP_ERROR, and the packet is delivered up as usual. The protocol
from the IP head in the ICMP error message is used to de-multiplex the packet.
// EFI_IP4_RECEIVE_DATA
EFI_EVENT RecycleSignal;
EFI_IP4_HEADER *Header;
UINT32 OptionsLength;
VOID *Options;
EFI_IP4_FRAGMENT_DATA FragmentTable[1];
} EFI_IP4_RECEIVE_DATA;
TimeStamp Time when the EFI IPv4 Protocol driver accepted the packet. TimeStamp is zero ﬁlled if receive times-
tamps are disabled or unsupported.
RecycleSignal After this event is signaled, the receive data structure is released and must not be referenced.
28.3. EFI IPv4 Protocol 1131Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
HeaderLength Length of the IPv4 packet header. Zero if ConﬁgData.RawData isTRUE .
Header Pointer to the IPv4 packet header. If the IPv4 packet was fragmented, this argument is a pointer to the header
in the ﬁrst fragment. NULL ifConﬁgData.RawData isTRUE . Type EFI_IP4_HEADER is deﬁned below.
OptionsLength Length of the IPv4 packet header options. May be zero.
Options Pointer to the IPv4 packet header options. If the IPv4 packet was fragmented, this argument is a pointer to
the options in the ﬁrst fragment. May be NULL .
DataLength Sum of the lengths of IPv4 packet buffers in FragmentTable . May be zero.
FragmentCount Number of IPv4 payload (or raw) fragments. If ConﬁgData.RawData isTRUE, this count is the
number of raw IPv4 fragments received so far. May be zero.
FragmentTable Array of payload (or raw) fragment lengths and buffer pointers. If ConﬁgData.RawData isTRUE,
each buffer points to a raw IPv4 fragment and thus IPv4 header and options are included in each buffer. Other-
wise, IPv4 headers and options are not included in these buffers. Type EFI_IP4_FRAGMENT_DATA is deﬁned
below.
The EFI IPv4 Protocol receive data structure is ﬁlled in when IPv4 packets have been assembled (or when raw packets
have been received). In the case of IPv4 packet assembly, the individual packet fragments are only veriﬁed and are not
reorganized into a single linear buffer.
TheFragmentTable contains a sorted list of zero or more packet fragment descriptors. The referenced packet fragments
may not be in contiguous memory locations.
// EFI_IP4_HEADER
UINT8 HeaderLength:4;
UINT8 Version:4;
UINT16 Identification;
UINT16 Fragmentation;
UINT8 Protocol;
EFI_IPv4_ADDRESS SourceAddress;
EFI_IPv4_ADDRESS DestinationAddress;
} EFI_IP4_HEADER;
The ﬁelds in the IPv4 header structure are deﬁned in the Internet Protocol version 4 speciﬁcation, which can be
found at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ ) under the heading “Internet Protocol version 4
Speciﬁcation”.
// EFI_IP4_FRAGMENT_DATA
} EFI_IP4_FRAGMENT_DATA;
FragmentLength Length of fragment data. This ﬁeld may not be set to zero.
FragmentBuffer Pointer to fragment data. This ﬁeld may not be set to NULL .
28.3. EFI IPv4 Protocol 1132Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheEFI_IP4_FRAGMENT_DATA structure describes the location and length of the IPv4 packet fragment to transmit
or that has been received.
// EFI_IP4_TRANSMIT_DATA
EFI_IP4_OVERRIDE_DATA *OverrideData;
VOID *OptionsBuffer;
UINT32 TotalDataLength;
} EFI_IP4_TRANSMIT_DATA;
DestinationAddress The destination IPv4 address. Ignored if RawData isTRUE .
OverrideData If not NULL, the IPv4 transmission control override data. Ignored if RawData isTRUE . Type
EFI_IP4_OVERRIDE_DATA is deﬁned below.
OptionsLength Length of the IPv4 header options data. Must be zero if the IPv4 driver does not support IPv4 options.
Ignored if RawData isTRUE .
OptionsBuffer Pointer to the IPv4 header options data. Ignored if OptionsLength is zero. Ignored if RawData is
TRUE .
TotalDataLength Total length of the FragmentTable data to transmit.
FragmentCount Number of entries in the fragment data table.
FragmentTable Start of the fragment data table. Type EFI_IP4_FRAGMENT_DATA is deﬁned above.
TheEFI_IP4_TRANSMIT_DATA structure describes a possibly fragmented packet to be transmitted.
// EFI_IP4_OVERRIDE_DATA
} EFI_IP4_OVERRIDE_DATA;
SourceAddress Source address override.
GatewayAddress Gateway address to override the one selected from the routing table. This address must be on the
same subnet as this station address. If set to 0.0.0.0, the gateway address selected from routing table will not be
overridden.
Protocol Protocol type override.
TypeOfService Type-of-service override.
TimeToLive Time-to-live override.

DoNotFragment Do-not-fragment override.
The information and ﬂags in the override data structure will override default parameters or settings for one Transmit()
function call.
28.3. EFI IPv4 Protocol 1133Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
•Token isNULL ..
•Token.Packet.TxData isNULL ..
•Token.Packet.TxData.OverrideData. GatewayAddress in the override
data structure is not a unicast IPv4 address if OverrideData is not NULL ..
•Token.Packet.TxData.OverrideData .SourceAddress is not a unicast IPv4
address if OverrideData is not NULL .
•Token.Packet.OptionsLength is not zero and Token.Packet.OptionsBuffer
isNULL ..
•Token.Packet.FragmentCount is zero.
• One or more of the Tok en.Packet.TxData.FragmentTable[].
FragmentLength ﬁelds is zero.
FragmentBuffer ﬁelds is NULL .
•Tok en.Packet.TxData.TotalDataLength is zero or not equal to the sum of
fragment lengths.
• The IP header in FragmentTable is not a well-formed header when
RawData isTRUE .
EFI_ACCESS_DENIED The transmit completion token with the same Token.Event was already in
the transmit queue.
full.
EFI_NOT_FOUND Not route is found to destination address.
EFI_OUT_OF_RESOURCES Could not queue the transmit data.
EFI_BUFFER_TOO_SMALL Tok en.Packet.TxData.TotalDataLength is too short to transmit.
EFI_BAD_BUFFER_SIZE The length of the IPv4 header + option length + total data length is
greater than MTU (or greater than the maximum packet size if * To-
ken.Packet.TxData.OverrideData. DoNotFragment* is TRUE .)
28.3.10 EFI_IP4_PROTOCOL.Receive()
Summary
Places a receiving request into the receiving queue.
Prototype
typedef
(EFIAPI *EFI_IP4_RECEIVE) (
28.3. EFI IPv4 Protocol 1134Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
Token Pointer to a token that is associated with the receive data descriptor. Type EFI_IP4_COMPLETION_TOKEN
is deﬁned in “Related Deﬁnitions” of above Transmit() .
TheToken.Event ﬁeld in the completion token must be ﬁlled in by the caller and cannot be NULL . When the receive
operation completes, the EFI IPv4 Protocol driver updates the Token.Status andToken.Packet.RxData ﬁelds and the
Token.Event is signaled.
EFI_NOT_STARTED This EFI IPv4 Protocol instance has not been started.
EFI_ACCESS_DENIED The receive completion token with the same Token.Event was already in the
receive queue.
EFI_ICMP_ERROR An ICMP error packet was received.
28.3.11 EFI_IP4_PROTOCOL.Cancel()
Summary
Abort an asynchronous transmit or receive request.
Prototype
typedef
(EFIAPI *EFI_IP4_CANCEL)(
IN EFI_IP4_COMPLETION_TOKEN *Token OPTIONAL
);
28.3. EFI IPv4 Protocol 1135Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Token Pointer to a token that has been issued by EFI_IP4_PROTOCOL .Transmit() or
EFI_IP4_PROTOCOL .Receive(). If NULL, all pending tokens are aborted. Type
EFI_IP4_COMPLETION_TOKEN is deﬁned in EFI_IP4_PROTOCOL.Transmit() .
The Cancel() function is used to abort a pending transmit or receive request. If the token is in the transmit or receive
request queues, after calling this function, Token->Status will be set to EFI_ABORTED and then Token->Event will
be signaled. If the token is not in one of the queues, which usually means the asynchronous operation has completed,
EFI_SUCCESS The asynchronous I/O request was aborted and Token.->Event was signaled.
When Token isNULL, all pending requests were aborted and their events
EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was not found in
28.3.12 EFI_IP4_PROTOCOL.Poll()
Summary
Prototype
typedef
(EFIAPI *EFI_IP4_POLL) (
IN EFI_IP4_PROTOCOL *This
);
ThePoll() function polls for incoming data packets and processes outgoing data packets. Network drivers and appli-
cations can call the EFI_IP4_PROTOCOL .Poll() function to increase the rate that data packets are moved between
the communications device and the transmit and receive queues.
In some systems the periodic timer event may not poll the underlying communications device fast enough to transmit
and/or receive all data packets without missing incoming packets or dropping outgoing packets. Drivers and applica-
tions that are experiencing packet loss should try calling the EFI_IP4_PROTOCOL .Poll() function more often.
28.3. EFI IPv4 Protocol 1136Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.4 EFI IPv4 Conﬁguration Protocol
This section provides a detailed description of the EFI IPv4 Conﬁguration Protocol.
IMPORTANT NOTICE: The EFI_IP4_CONFIG_PROTOCOL has been replaced with the new
EFI_IP4_CONFIG2_PROTOCOL .
• All new designs based on this speciﬁcation should exclusively use EFI_IP4_CONFIG2_PROTOCOL .
• The EFI_IP4_CONFIG_PROTOCOL will be removed in the next revision of this speciﬁcation.
28.4.1 EFI_IP4_CONFIG_PROTOCOL
IMPORTANT NOTICE : The EFI_IP4_CONFIG_PROTOCOL has been replaced with the new
Summary
TheEFI_IP4_CONFIG_PROTOCOL driver performs platform- and policy-dependent conﬁguration for the EFI IPv4
Protocol driver.
GUID
#define EFI_IP4_CONFIG_PROTOCOL_GUID \
{0x3b95aa31,0x3793,0x434b,\
{0x86,0x67,0xc8,0x07,0x08,0x92,0xe0,0x5e}}
typedef struct _EFI_IP4_CONFIG_PROTOCOL {
EFI_IP4_CONFIG_START Start;
EFI_IP4_CONFIG_STOP Stop;
EFI_IP4_CONFIG_GET_DATA GetData;
} EFI_IP4_CONFIG_PROTOCOL;
Start Starts running the conﬁguration policy for the EFI IPv4 Protocol driver. See the Start() function description.
Stop Stops running the conﬁguration policy for the EFI IPv4 Protocol driver. See the Stop() function description.
GetData Returns the default conﬁguration data (if any) for the EFI IPv4 Protocol driver. See the GetData() function
28.4. EFI IPv4 Conﬁguration Protocol 1137Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
In an effort to keep platform policy code out of the EFI IPv4 Protocol driver, the EFI_IP4_CONFIG_PROTOCOL
driver will be used as the central repository of any platform- and policy-speciﬁc conﬁguration for the EFI IPv4 Protocol
driver.
An EFI IPv4 Conﬁguration Protocol interface will be installed on each communications device handle that is managed
by the platform setup policy. The driver that is responsible for creating EFI IPv4 variable must open the EFI IPv4

driver.
Conﬁguration Protocol driver interface BY_DRIVER|EXCLUSIVE .
An example of a conﬁguration policy decision for the EFI IPv4 Protocol driver would be to use a static IP ad-
dress/subnet mask pair on the platform management network interface and then use dynamic IP addresses that are
conﬁgured by DHCP on the remaining network interfaces.
28.4.2 EFI_IP4_CONFIG_PROTOCOL.Start()
Summary
Starts running the conﬁguration policy for the EFI IPv4 Protocol driver.
Prototype
typedef
(EFIAPI *EFI_IP4_CONFIG_START) (
IN EFI_IP4_CONFIG_PROTOCOL *This,
IN EFI_EVENT DoneEvent,
IN EFI_EVENT ReconfigEvent
);
This Pointer to the EFI_IP4_CONFIG_PROTOCOL instance.
DoneEvent Event that will be signaled when the EFI IPv4 Protocol driver conﬁguration policy completes execution.
This event must be of type EVT_NOTIFY_SIGNAL .
ReconﬁgEvent Event that will be signaled when the EFI IPv4 Protocol driver conﬁguration needs to be updated. This
event must be of type EVT_NOTIFY_SIGNAL .
TheStart () function is called to determine and to begin the platform conﬁguration policy by the EFI IPv4 Protocol
driver. This determination may be as simple as returning EFI_UNSUPPORTED if there is no EFI IPv4 Protocol driver
conﬁguration policy. It may be as involved as loading some defaults from nonvolatile storage, downloading dynamic
data from a DHCP server, and checking permissions with a site policy server.
Starting the conﬁguration policy is just the beginning. It may ﬁnish almost instantly or it may take several minutes be-
fore it fails to retrieve conﬁguration information from one or more servers. Once the policy is started, drivers should use
theDoneEvent parameter to determine when the conﬁguration policy has completed. EFI_IP4_CONFIG_PROTOCOL
.GetData() must then be called to determine if the conﬁguration succeeded or failed.
Until the conﬁguration completes successfully, EFI IPv4 Protocol driver instances that are attempting to use default
conﬁgurations must return EFI_NO_MAPPING .
28.4. EFI IPv4 Conﬁguration Protocol 1138Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Once the conﬁguration is complete, the EFI IPv4 Conﬁguration Protocol driver signals DoneEvent . The conﬁgura-
tion may need to be updated in the future, however; in this case, the EFI IPv4 Conﬁguration Protocol driver must
signal ReconﬁgEvent, and all EFI IPv4 Protocol driver instances that are using default conﬁgurations must return
EFI_NO_MAPPING until the conﬁguration policy has been rerun.
EFI_SUCCESS The conﬁguration policy for the EFI IPv4 Protocol driver is now running.
One or more of the following parameters is NULL:
•This
•DoneEvent
•ReconﬁgEvent
EFI_ALREADY_STARTED The conﬁguration policy for the EFI IPv4 Protocol driver was already
started.
EFI_DEVICE_ERROR An unexpected system error or network error occurred.
EFI_UNSUPPORTED This interface does not support the EFI IPv4 Protocol driver conﬁguration.
28.4.3 EFI_IP4_CONFIG_PROTOCOL.Stop()
Summary
Stops running the conﬁguration policy for the EFI IPv4 Protocol driver.
Prototype
typedef
(EFIAPI *EFI_IP4_CONFIG_STOP) (
IN EFI_IP4_CONFIG_PROTOCOL *This
);
TheStop () function stops the conﬁguration policy for the EFI IPv4 Protocol driver. All conﬁguration data will be lost
after calling Stop() .
EFI_SUCCESS The conﬁguration policy for the EFI IPv4 Protocol driver has been stopped.
EFI_NOT_STARTED The conﬁguration policy for the EFI IPv4 Protocol driver was not started.
28.4. EFI IPv4 Conﬁguration Protocol 1139Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.4.4 EFI_IP4_CONFIG_PROTOCOL.GetData()
Summary
Returns the default conﬁguration data (if any) for the EFI IPv4 Protocol driver.
Prototype
typedef
(EFIAPI *EFI_IP4_CONFIG_GET_DATA) (
IN OUT UINTN *IpConfigDataSize,
OUT EFI_IP4_IPCONFIG_DATA *IpConfigData OPTIONAL
);
IpConﬁgDataSize On input, the size of the IpConﬁgData buffer. On output, the count of bytes that were written into
theIpConﬁgData buffer.
IpConﬁgData Pointer to the EFI IPv4 Conﬁguration Protocol driver conﬁguration data structure. Type
EFI_IP4_IPCONFIG_DATA is deﬁned in “Related Deﬁnitions” below.
TheGetData () function returns the current conﬁguration data for the EFI IPv4 Protocol driver after the conﬁguration
policy has completed.
// EFI_IP4_IPCONFIG_DATA
UINT32 RouteTableSize;
EFI_IP4_ROUTE_TABLE *RouteTable OPTIONAL;
} EFI_IP4_IPCONFIG_DATA;
StationAddress Default station IP address, stored in network byte order.
SubnetMask Default subnet mask, stored in network byte order.
RouteTableSize Number of entries in the following RouteTable . May be zero.
RouteTable Default routing table data (stored in network byte order). Ignored if RouteTableSize is zero. Type
EFI_IP4_ROUTE_TABLE is deﬁned in EFI_IP4_PROTOCOL .GetModeData() .
EFI_IP4_IPCONFIG_DATA contains the minimum IPv4 conﬁguration data that is needed to start basic network com-
munication. The StationAddress andSubnetMask must be a valid unicast IP address and subnet mask.
IfRouteTableSize is not zero, then RouteTable contains a properly formatted routing table for the StationAddress /
SubnetMask, with the last entry in the table being the default route.
28.4. EFI IPv4 Conﬁguration Protocol 1140Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The EFI IPv4 Protocol driver conﬁguration has been returned.
EFI_NOT_STARTED The conﬁguration policy for the EFI IPv4 Protocol driver is not running.
EFI_NOT_READY EFI IPv4 Protocol driver conﬁguration is still running.
EFI_ABORTED EFI IPv4 Protocol driver conﬁguration could not complete.
*IpConﬁgDataSize is smaller than the conﬁguration data buffer or
IpConﬁgData isNULL .
28.5 EFI IPv4 Conﬁguration II Protocol
This section provides a detailed description of the EFI IPv4 Conﬁguration II Protocol.
28.5.1 EFI_IP4_CONFIG2_PROTOCOL
Summary
TheEFI_IP4_CONFIG2_PROTOCOL provides the mechanism to set and get various types of conﬁgurations for the
EFI IPv4 network stack.
GUID
#define EFI_IP4_CONFIG2_PROTOCOL_GUID \
{ 0x5b446ed1, 0xe30b, 0x4faa,\
{ 0x87, 0x1a, 0x36, 0x54, 0xec, 0xa3, 0x60, 0x80 }}
typedef struct _EFI_IP4_CONFIG2_PROTOCOL {
EFI_IP4_CONFIG2_SET_DATA SetData;
EFI_IP4_CONFIG2_GET_DATA GetData;
EFI_IP4_CONFIG2_REGISTER_NOTIFY RegisterDataNotify;
EFI_IP4_CONFIG2_UNREGISTER_NOTIFY UnregisterDataNotify;
} EFI_IP4_CONFIG2_PROTOCOL;
SetData Set the conﬁguration for the EFI IPv4 network stack running on the communication device this EFI IPv4
Conﬁguration II Protocol instance manages. See the SetData() function description.
GetData Get the conﬁguration for the EFI IPv4 network stack running on the communication device this EFI IPv4
Conﬁguration II Protocol instance manages. See the GetData() function description.
RegiseterDataNotify Register an event that is to be signaled whenever a conﬁguration process on the speciﬁed con-
ﬁguration data is done.
UnregisterDataNotify Remove a previously registered event for the speciﬁed conﬁguration data.
TheEFI_IP4_CONFIG2_PROTOCOL is designed to be the central repository for the common conﬁgurations and the
administrator conﬁgurable settings for the EFI IPv4 network stack.
28.5. EFI IPv4 Conﬁguration II Protocol 1141Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
An EFI IPv4 Conﬁguration II Protocol instance will be installed on each communication device that the EFI IPv4
network stack runs on.

NOTE: All the network addresses described in EFI_IP4_CONFIG2_PROTOCOL are stored in network byte order.
All other parameters deﬁned in functions or data structures are stored in host byte order .
28.5.2 EFI_IP4_CONFIG2_PROTOCOL.SetData()
Summary
Set the conﬁguration for the EFI IPv4 network stack running on the communication device this EFI IPv4 Conﬁguration
II Protocol instance manages.
Prototype
typedef
(EFIAPI *EFI_IP4_CONFIG2_SET_DATA) (
IN EFI_IP4_CONFIG2_PROTOCOL *This,
IN EFI_IP4_CONFIG2_DATA_TYPE DataType,
);
This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
DataType The type of data to set. Type EFI_IP4_CONFIG2_DATA_TYPE is deﬁned in “Related Deﬁnitions” below.
DataSize Size of the buffer pointed to by Data in bytes.
Data The data buffer to set. The type of the data buffer is associated with the DataType . The various types are deﬁned
This function is used to set the conﬁguration data of type DataType for the EFI IPv4 network stack running on the
communication device this EFI IPv4 Conﬁguration II Protocol instance manages. The successfully conﬁgured data is
valid after system reset or power-off.
The DataSize is used to calculate the count of structure instances in the Data for some DataType that multiple structure
instances are allowed.
This function is always non-blocking. When setting some type of conﬁguration data, an asynchronous process is
invoked to check the correctness of the data, such as doing address conﬂict detection on the manually set local IPv4
address. EFI_NOT_READY is returned immediately to indicate that such an asynchronous process is invoked and
the process is not ﬁnished yet. The caller willing to get the result of the asynchronous process is required to call
RegisterDataNotify() to register an event on the speciﬁed conﬁguration data. Once the event is signaled, the caller can
callGetData() to get back the conﬁguration data in order to know the result. For other types of conﬁguration data that
do not require an asynchronous conﬁguration process, the result of the operation is immediately returned.
//*********************************************
// EFI_IP4_CONFIG2_DATA_TYPE
Ip4Config2DataTypeInterfaceInfo,
Ip4Config2DataTypePolicy,
28.5. EFI IPv4 Conﬁguration II Protocol 1142Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Ip4Config2DataTypeManualAddress,
Ip4Config2DataTypeGateway,
Ip4Config2DataTypeDnsServer,
Ip4Config2DataTypeMaximum
} EFI_IP4_CONFIG2_DATA_TYPE;
Ip4Conﬁg2DataTypeInterfaceInfo The interface information of the communication device this EFI IPv4 Conﬁg-
uration II Protocol instance manages. This type of data is read only. The corresponding Data is of type
EFI_IP4_CONFIG2_INTERFACE_INFO .
Ip4Conﬁg2DataTypePolicy The general conﬁguration policy for the EFI IPv4 network stack running on the com-
munication device this EFI IPv4 Conﬁguration II Protocol instance manages. The policy will affect other con-
ﬁguration settings. The corresponding Data is of type EFI_IP4_CONFIG2_POLICY .
Ip4Conﬁg2DataTypeManualAddress The station addresses set manually for the EFI IPv4 network stack. It
is only conﬁgurable when the policy is Ip4Conﬁg2PolicyStatic . The corresponding Data is of type
EFI_IP4_CONFIG2_MANUAL_ADDRESS . When DataSize is 0 and Data isNULL, the existing conﬁguration
is cleared from the EFI IPv4 Conﬁguration II Protocol instance.
Ip4Conﬁg2DataTypeGateway The gateway addresses set manually for the EFI IPv4 network stack running on the
communication device this EFI IPv4 Conﬁguration II Protocol manages. It is not conﬁgurable when the policy
isIp4Conﬁg2PolicyDhcp . The gateway addresses must be unicast IPv4 addresses. The corresponding Data is
a pointer to an array of EFI_IPv4_ADDRESS instances. When DataSize is 0 and Data isNULL, the existing
conﬁguration is cleared from the EFI IPv4 Conﬁguration II Protocol instance.
Ip4Conﬁg2DataTypeDnsServer The DNS server list for the EFI IPv4 network stack running on the communi-
cation device this EFI IPv4 Conﬁguration II Protocol manages. It is not conﬁgurable when the policy is
Ip4Conﬁg2PolicyDhcp .The DNS server addresses must be unicast IPv4 addresses. The corresponding Data
is a pointer to an array of EFI_IPv4_ADDRESS instances. When DataSize is 0 and Data isNULL, the existing
// EFI_IP4_CONFIG2_INTERFACE_INFO related definitions
#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32
// EFI_IP4_CONFIG2_INTERFACE_INFO
CHAR16 Name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE];
EFI_MAC_ADDRESS HwAddress;
} EFI_IP4_CONFIG2_INTERFACE_INFO;
Name The name of the interface. It is a NULL-terminated Unicode string.
IfType The interface type of the network interface. See RFC 1700, section “Number Hardware Type”.
HwAddressSize The size, in bytes, of the network interface’s hardware address.
HwAddress The hardware address for the network interface.
StationAddress The station IPv4 address of this EFI IPv4 network stack.
28.5. EFI IPv4 Conﬁguration II Protocol 1143Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SubnetMask The subnet address mask that is associated with the station address.
RouteTableSize Size of the following RouteTable, in bytes. May be zero.
RouteTable The route table of the IPv4 network stack runs on this interface. Set to NULL if RouteTableSize is zero.
Type EFI_IP4_ROUTE_TABLE is deﬁned in EFI_IP4_PROTOCOL.GetModeData() .
TheEFI_IP4_CONFIG2_INTERFACE_INFO structure describes the operational state of the interface this EFI IPv4
Conﬁguration II Protocol instance manages. This type of data is read-only. When reading, the caller allocated buffer
is used to return all of the data, i.e., the ﬁrst part of the buffer is EFI_IP4_CONFIG2_INTERFACE_INFO and the
followings are the route table if present. The caller should NOT free the buffer pointed to by RouteTable, and the
caller is only required to free the whole buffer if the data is not needed any more.
// EFI_IP4_CONFIG2_POLICY
Ip4Config2PolicyStatic,
Ip4Config2PolicyDhcp,
Ip4Config2PolicyMax
} EFI_IP4_CONFIG2_POLICY;
Ip4Conﬁg2PolicyStatic Under this policy, the Ip4Conﬁg2DataTypeManualAddress, Ip4Conﬁg2DataTypeGateway
andIp4Conﬁg2DataTypeDnsServer conﬁguration data are required to be set manually. The EFI IPv4 Protocol
will get all required conﬁguration such as IPv4 address, subnet mask and gateway settings from the EFI IPv4
Conﬁguration II protocol.
Ip4Conﬁg2PolicyDhcp Under this policy, the Ip4Conﬁg2DataTypeManualAddress, Ip4Conﬁg2DataTypeGateway
andIp4Conﬁg2DataTypeDnsServer conﬁguration data are not allowed to set via SetData() . All of these conﬁg-
urations are retrieved from DHCP server or other auto-conﬁguration mechanism.
The EFI_IP4_CONFIG2_POLICY deﬁnes the general conﬁguration policy the EFI IPv4 Conﬁguration II Protocol
supports. The default policy for a newly detected communication device is beyond the scope of this document. An
implementation might leave it to platform to choose the default policy.
The conﬁguration data of type Ip4Conﬁg2DataTypeManualAddress, Ip4Conﬁg2DataTypeGateway and
Ip4Conﬁg2DataTypeDnsServer will be ﬂushed if the policy is changed from Ip4Conﬁg2PolicyStatic to
Ip4Conﬁg2PolicyDhcp .
// EFI_IP4_CONFIG2_MANUAL_ADDRESS
EFI_IPv4_ADDRESS Address;
} EFI_IP4_CONFIG2_MANUAL_ADDRESS;
Address The IPv4 unicast address.
SubnetMask The subnet mask.
The EFI_IP4_CONFIG2_MANUAL_ADDRESS structure is used to set the station address information for the EFI
IPv4 network stack manually when the policy is Ip4Conﬁg2PolicyStatic .
TheEFI_IP4_CONFIG2_DATA_TYPE includes current supported data types; this speciﬁcation allows future exten-
sion to support more data types.
28.5. EFI IPv4 Conﬁguration II Protocol 1144Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The speciﬁed conﬁguration data for the EFI IPv4 network stack is set suc-
cessfully.
•This isNULL.
• One or more ﬁelds in Data andDataSize do not match the requirement of
the data type indicated by DataType .

EFI_WRITE_PROTECTED The speciﬁed conﬁguration data is read-only or the speciﬁed conﬁguration
data can not be set under the current policy.
EFI_ACCESS_DENIED Another set operation on the speciﬁed conﬁguration data is already in pro-
cess.
EFI_NOT_READY An asynchronous process is invoked to set the speciﬁed conﬁguration data
and the process is not ﬁnished yet.
EFI_BAD_BUFFER_SIZE TheDataSize does not match the size of the type indicated by DataType .
EFI_UNSUPPORTED This DataType is not supported.
28.5.3 EFI_IP4_CONFIG2_PROTOCOL.GetData()
Summary
Get the conﬁguration data for the EFI IPv4 network stack running on the communication device this EFI IPv4 Con-
ﬁguration II Protocol instance manages.
Prototype
typedef
(EFIAPI *EFI_IP4_CONFIG2_GET_DATA) (
);
DataType The type of data to get. Type EFI_IP4_CONFIG2_DATA_TYPE is deﬁned in
EFI_IP4_CONFIG2_PROTOCOL.SetData().
DataSize On input, in bytes, the size of Data . On output, in bytes, the size of buffer required to store the speciﬁed
conﬁguration data.
Data The data buffer in which the conﬁguration data is returned. The type of the data buffer is
associated with the DataType . Ignored if DataSize is 0. The various types are deﬁned in
EFI_IP4_CONFIG2_PROTOCOL.SetData() .
This function returns the conﬁguration data of type DataType for the EFI IPv4 network stack running on the commu-
nication device this EFI IPv4 Conﬁguration II Protocol instance manages.
28.5. EFI IPv4 Conﬁguration II Protocol 1145Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The caller is responsible for allocating the buffer used to return the speciﬁed conﬁguration data and the required size
will be returned to the caller if the size of the buffer is too small.
EFI_NOT_READY is returned if the speciﬁed conﬁguration data is not ready due to an already in progress asyn-
chronous conﬁguration process. The caller can call RegisterDataNotify() to register an event on the speciﬁed conﬁg-
uration data. Once the asynchronous conﬁguration process is ﬁnished, the event will be signaled and a subsequent
GetData() call will return the speciﬁed conﬁguration data.
EFI_SUCCESS The speciﬁed conﬁguration data is got successfully.
EFI_INV ALID_PARAMETER*
One or more of the followings are TRUE:
• This is NULL .
• DataSize is NULL .
•Data isNULL ifDataSize is not zero.
required size is returned in DataSize .
EFI_NOT_READY The speciﬁed conﬁguration data is not ready due to an already in progress
asynchronous conﬁguration process.
EFI_NOT_FOUND The speciﬁed conﬁguration data is not found.
28.5.4 EFI_IP4_CONFIG2_PROTOCOL.RegisterDataNotify ()
Summary
Register an event that is to be signaled whenever a conﬁguration process on the speciﬁed conﬁguration data is done.
Prototype
typedef
(EFIAPI *EFI_IP4_CONFIG2_REGISTER_NOTIFY) (
);
DataType The type of data to unregister the event for. Type EFI_IP4_CONFIG2_DATA_TYPE is deﬁned in
Event The event to register.
This function registers an event that is to be signaled whenever a conﬁguration process on the speciﬁed conﬁguration
data is done. An event can be registered for different DataType simultaneously and the caller is responsible for
determining which type of conﬁguration data causes the signaling of the event in such case.
28.5. EFI IPv4 Conﬁguration II Protocol 1146Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The notiﬁcation event for the speciﬁed conﬁguration data is registered.
EFI_INV ALID_PARAMETER This isNULL or Event is NULL .
EFI_UNSUPPORTED The conﬁguration data type speciﬁed by DataType is not supported.
EFI_ACCESS_DENIED TheEvent is already registered for the DataType .
28.5.5 EFI_IP4_CONFIG2_PROTOCOL.UnregisterDataNotify ()
Summary
Remove a previously registered event for the speciﬁed conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_IP4_CONFIG2_UNREGISTER_NOTIFY) (
);
DataType The type of data to remove the previously registered event for. Type EFI_IP4_CONFIG2_DATA_TYPE is
deﬁned in EFI_IP4_CONFIG2_PROTOCOL.SetData().
Event The event to unregister.
This function removes a previously registered event for the speciﬁed conﬁguration data.
EFI_SUCCESS The event registered for the speciﬁed conﬁguration data is removed.
EFI_INV ALID_PARAMETER This isNULL orEvent isNULL .
EFI_NOT_FOUND TheEvent has not been registered for the speciﬁed DataType .
28.6 EFI IPv6 Protocol
This section deﬁnes the EFI IPv6 (Internet Protocol version 6) Protocol interface. It is split into the following three
• EFI IPv6 Service Binding Protocol
• EFI IPv6 Variable
• EFI IPv6 Protocol
The EFI IPv6 Protocol provides basic network IPv6 packet I/O services, which includes support for Neighbor Dis-
covery Protocol (ND), Multicast Listener Discovery Protocol (MLD), and a subset of the Internet Control Message
Protocol (ICMPv6).
28.6. EFI IPv6 Protocol 1147Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.6.1 IPv6 Service Binding Protocol
28.6.2 EFI_IP6_SERVICE_BINDING_PROTOCOL
Summary
The EFI IPv6 Service Binding Protocol is used to locate communication devices that are supported by an EFI IPv6
Protocol driver and to create and destroy EFI IPv6 Protocol child instances of the IP6 driver that can use the underlying
communications device.
GUID
#define EFI_IP6_SERVICE_BINDING_PROTOCOL _GUID \
{0xec835dd3,0xfe0f,0x617b,\
{0xa6,0x21,0xb3,0x50,0xc3,0xe1,0x33,0x88}}
A network application that requires basic IPv6 I/O services can use one of the protocol handler services, such as BS-
>LocateHandleBuffer(), to search for devices that publish an EFI IPv6 Service Binding Protocol GUID. Each device
with a published EFI IPv6 Service Binding Protocol GUID supports the EFI IPv6 Protocol and may be available for
use.
After a successful call to the EFI_IP6_SERVICE_BINDING_PROTOCOL.CreateChild() function, the newly created
child EFI IPv6 Protocol driver is in an un-conﬁgured state; it is not ready to send and receive data packets.
EFI_IP6_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_IP6_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
28.6.3 IPv6 Protocol
28.6.4 EFI_IP6_PROTOCOL
Summary
The EFI IPv6 Protocol implements a simple packet-oriented interface that can be used by drivers, daemons, and
GUID
#define EFI_IP6_PROTOCOL_GUID \
{0x2c8759d5,0x5c2d,0x66ef,\
{0x92,0x5f,0xb6,0x6c,0x10,0x19,0x57,0xe2}}
typedef struct _EFI_IP6_PROTOCOL {
EFI_IP6_GET_MODE_DATA GetModeData;
EFI_IP6_CONFIGURE Configure;
EFI_IP6_GROUPS Groups;
EFI_IP6_ROUTES Routes;
EFI_IP6_NEIGHBORS Neighbors;
EFI_IP6_TRANSMIT Transmit;
EFI_IP6_RECEIVE Receive;
EFI_IP6_CANCEL Cancel;
EFI_IP6_POLL Poll;
} EFI_IP6_PROTOCOL;
28.6. EFI IPv6 Protocol 1148Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetModeData Gets the current operational settings for this instance of the EFI IPv6 Protocol driver. See the Get-
Conﬁgure Changes or resets the operational settings for the EFI IPv6 Protocol. See the Conﬁgure() function descrip-
tion.
Neighbors Adds and deletes neighbor cache entries. See the Neighbors() function description.
TheEFI_IP6_PROTOCOL deﬁnes a set of simple IPv6, and ICMPv6 services that can be used by any network protocol

tion.
driver, daemon, or application to transmit and receive IPv6 data packets.
NOTE: Byte Order: All the IPv6 addresses that are described in EFI_IP6_PROTOCOL are stored in network byte
order. Both incoming and outgoing IP packets are also in network byte order. All other parameters that are deﬁned in
functions or data structures are stored in host byte order .
28.6.5 EFI_IP6_PROTOCOL.GetModeData()
Summary
Gets the current operational settings for this instance of the EFI IPv6 Protocol driver.
Prototype
(EFIAPI *EFI_IP6_GET_MODE_DATA) (
IN EFI_IP6_PROTOCOL *This,
OUT EFI_IP6_MODE_DATA *Ip6ModeData OPTIONAL,
);
This Pointer to the EFI_IP6_PROTOCOL instance.
Ip6ModeData Pointer to the EFI IPv6 Protocol mode data structure. Type EFI_IP6_MODE_DATA is deﬁned in
28.6. EFI IPv6 Protocol 1149Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_IP6_MODE_DATA are read only. This function is used optionally to retrieve the operational mode data of under-
//***************************************
// EFI_IP6_MODE_DATA
EFI_IP6_CONFIG_DATA ConfigData;
UINT32 AddressCount;
EFI_IP6_ADDRESS_INFO *AddressList;
EFI_IPv6_ADDRESS *GroupTable;
EFI_IP6_ROUTE_TABLE *RouteTable;
UINT32 NeighborCount;
EFI_IP6_NEIGHBOR_CACHE *NeighborCache;
UINT32 PrefixCount;
EFI_IP6_ADDRESS_INFO *PrefixTable;
EFI_IP6_ICMP_TYPE *IcmpTypeList;
} EFI_IP6_MODE_DATA;
IsStarted Set to TRUE after this EFI IPv6 Protocol instance is started. All other ﬁelds in this structure are undeﬁned
until this ﬁeld is TRUE . Set to FALSE when the EFI IPv6 Protocol instance is stopped.
ConﬁgData Current conﬁguration settings. Undeﬁned until IsStarted isTRUE . Type EFI_IP6_CONFIG_DATA is
IsConﬁgured Set to TRUE when the EFI IPv6 Protocol instance is conﬁgured. The instance is conﬁgured when it
has a station address and corresponding preﬁx length. Set to FALSE when the EFI IPv6 Protocol instance is not
AddressCount Number of conﬁgured IPv6 addresses on this interface.
AddressList List of currently conﬁgured IPv6 addresses and corresponding preﬁx lengths assigned to this interface.
It is caller’s responsibility to free this buffer. Type EFI_IP6_ADDRESS_INFO is deﬁned below.
GroupTable List of joined multicast group addresses. It is caller’s responsibility to free this buffer. Undeﬁned until
IsConﬁgured isTRUE .
RouteTable Routing table entries. It is caller’s responsibility to free this buffer. Type EFI_IP6_ROUTE_TABLE is
NeighborCount Number of entries in the neighbor cache. Undeﬁned until IsConﬁgured isTRUE .
NeighborCache Neighbor cache entries. It is caller’s responsibility to free this buffer. Undeﬁned until IsConﬁgured
isTRUE . Type EFI_IP6_NEIGHBOR_CACHE is deﬁned below.
PreﬁxCount Number of entries in the preﬁx table. Undeﬁned until IsConﬁgured isTRUE .
28.6. EFI IPv6 Protocol 1150Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PreﬁxTable On-link Preﬁx table entries. It is caller’s responsibility to free this buffer. Undeﬁned until IsConﬁgured
isTRUE . Type EFI_IP6_ADDRESS_INFO is deﬁned below.
IcmpTypeList Array of ICMP types and codes that are supported by this EFI IPv6 Protocol driver. It is caller’s
responsibility to free this buffer. Type EFI_IP6_ICMP_TYPE is deﬁned below.
// EFI_IP6_CONFIG_DATA
EFI_IPv6_ADDRESS DestinationAddress;
UINT32 FlowLabel;
} EFI_IP6_CONFIG_DATA;
DefaultProtocol For the IPv6 packet to send and receive, this is the default value of the ‘Next Header’ ﬁeld in the
last IPv6 extension header or in the IPv6 header if there are no extension headers. Ignored when AcceptPromis-
cuous isTRUE . An updated list of protocol numbers can be found at “Links to UEFI-Related Documents” (
http://ueﬁ.org/ueﬁ) under the heading “IANA Assigned Internet Protocol Numbers”. The following values are
illegal: 0 (IPv6 Hop-by-Hop Option), 1(ICMP), 2(IGMP), 41(IPv6), 43(Routing Header for IPv6), 44(Fragment
Header for IPv6), 59(No Next Header for IPv6), 60(Destination Options for IPv6), 124(ISIS over IPv4).
AcceptAnyProtocol Set to TRUE to receive all IPv6 packets that get through the receive ﬁlters. Set to FALSE to
receive only the DefaultProtocol IPv6 packets that get through the receive ﬁlters. Ignored when AcceptPromis-
AcceptPromiscuous Set to TRUE to receive all IPv6 packets that are sent to any hardware address or any protocol
address. Set to FALSE to stop receiving all promiscuous IPv6 packets.
DestinationAddress The destination address of the packets that will be transmitted. Ignored if it is unspeciﬁed.
StationAddress The station IPv6 address that will be assigned to this EFI IPv6 Protocol instance. This ﬁeld can
be set and changed only when the EFI IPv6 driver is transitioning from the stopped to the started states. If
the StationAddress is speciﬁed, the EFI IPv6 Protocol driver will deliver only incoming IPv6 packets whose
destination matches this IPv6 address exactly. The StationAddress is required to be one of currently conﬁgured
IPv6 addresses. An address containing all zeroes is also accepted as a special case. Under this situation, the
IPv6 driver is responsible for binding a source address to this EFI IPv6 protocol instance according to the source
address selection algorithm. Only incoming packets destined to the selected address will be delivered to the user.
And the selected station address can be retrieved through later GetModeData() call. If no address is available
for selecting, EFI_NO_MAPPING will be returned, and the station address will only be successfully bound to
this EFI IPv6 protocol instance after IP6ModeData.IsConﬁgured changed to TRUE .
TrafﬁcClass TrafﬁcClass ﬁeld in transmitted IPv6 packets. Default value is zero.
FlowLabel FlowLabel ﬁeld in transmitted IPv6 packets. Default value is zero.
28.6. EFI IPv6 Protocol 1151Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The EFI_IP6_CONFIG_DATA structure is used to report and change IPv6 session parameters.
// EFI_IP6_ADDRESS_INFO
EFI_IPv6_ADDRESS Address;
UINT8 PrefixLength;
} EFI_IP6_ADDRESS_INFO;
Address The IPv6 address.
PreﬁxLength The length of the preﬁx associated with the Address .
// EFI_IP6_ROUTE_TABLE
EFI_IPv6_ADDRESS Gateway;
EFI_IPv6_ADDRESS Destination;
} EFI_IP6_ROUTE_TABLE;
Gateway The IPv6 address of the gateway to be used as the next hop for packets to this preﬁx. If the IPv6 address is
all zeros, then the preﬁx is on-link.
Destination The destination preﬁx to be routed.
PreﬁxLength The length of the preﬁx associated with the Destination .
EFI_IP6_ROUTE_TABLE is the entry structure that is used in routing tables.
// EFI_IP6_NEIGHBOR_CACHE
EFI_IPv6_ADDRESS Neighbor;

EFI_MAC_ADDRESS LinkAddress;
EFI_IP6_NEIGHBOR_STATE State;
} EFI_IP6_NEIGHBOR_CACHE;
Neighbor The on-link unicast / anycast IP address of the neighbor.
LinkAddress Link-layer address of the neighbor.
State State of this neighbor cache entry.
EFI_IP6_NEIGHBOR_CACHE is the entry structure that is used in neighbor cache. It records a set of entries about
individual neighbors to which trafﬁc has been sent recently.
// EFI_IP6_NEIGHBOR_STATE
EfiNeighborInComplete,
28.6. EFI IPv6 Protocol 1152Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EfiNeighborReachable,
EfiNeighborStale,
EfiNeighborDelay,
EfiNeighborProbe
} EFI_IP6_NEIGHBOR_STATE;
Following is a description of the ﬁelds in the above enumeration.
EﬁNeighborInComplete Address resolution is being performed on this entry. Specially, Neighbor Solicitation has
been sent to the solicited-node multicast address of the target, but corresponding Neighbor Advertisement has
not been received.
EﬁNeighborReachable Positive conﬁrmation was received that the forward path to the neighbor was functioning
properly.
EﬁNeighborStale Reachable Time has elapsed since the last positive conﬁrmation was received. In this state, the
forward path to the neighbor was functioning properly.
EﬁNeighborDelay This state is an optimization that gives upper-layer protocols additional time to provide reachabil-
ity conﬁrmation.
EﬁNeighborProbe A reachability conﬁrmation is actively sought by retransmitting Neighbor Solicitations every Re-
transTimer milliseconds until a reachability conﬁrmation is received.
// EFI_IP6_ICMP_TYPE
} EFI_IP6_ICMP_TYPE;
Type The type of ICMP message. See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading
“Internet Control Message Protocol Version 6 (ICMPv6) Parameters” for the complete list of ICMP message
type.
Type. See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “Internet Control Mes-
sage Protocol Version 6 (ICMPv6) Parameters” for details for code of ICMP message.
EFI_IP6_ICMP_TYPE is used to describe those ICMP messages that are supported by this EFI IPv6 Protocol driver.
// ICMPv6 type definitions forerror messages
#define ICMP_V6_DEST_UNREACHABLE 0x1
#define ICMP_V6_PACKET_TOO_BIG 0x2
#define ICMP_V6_TIME_EXCEEDED 0x3
#define ICMP_V6_PARAMETER_PROBLEM 0x4
// ICMPv6 type definition forinformational messages
#define ICMP_V6_ECHO_REQUEST 0x80
#define ICMP_V6_ECHO_REPLY 0x81
#define ICMP_V6_LISTENER_QUERY 0x82
#define ICMP_V6_LISTENER_REPORT 0x83
#define ICMP_V6_LISTENER_DONE 0x84
28.6. EFI IPv6 Protocol 1153Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define ICMP_V6_ROUTER_SOLICIT 0x85
#define ICMP_V6_ROUTER_ADVERTISE 0x86
#define ICMP_V6_NEIGHBOR_SOLICIT 0x87
#define ICMP_V6_NEIGHBOR_ADVERTISE 0x88
#define ICMP_V6_REDIRECT 0x89
#define ICMP_V6_LISTENER_REPORT_2 0x8F
// ICMPv6 code definitions forICMP_V6_DEST_UNREACHABLE
#define ICMP_V6_NO_ROUTE_TO_DEST 0x0
#define ICMP_V6_COMM_PROHIBITED 0x1
#define ICMP_V6_BEYOND_SCOPE 0x2
#define ICMP_V6_ADDR_UNREACHABLE 0x3
#define ICMP_V6_PORT_UNREACHABLE 0x4
#define ICMP_V6_SOURCE_ADDR_FAILED 0x5
#define ICMP_V6_ROUTE_REJECTED 0x6
// ICMPv6 code definitions forICMP_V6_TIME_EXCEEDED
#define ICMP_V6_TIMEOUT_HOP_LIMIT 0x0
#define ICMP_V6_TIMEOUT_REASSEMBLE 0x1
// ICMPv6 code definitions forICMP_V6_PARAMETER_PROBLEM
#define ICMP_V6_ERRONEOUS_HEADER 0x0
#define ICMP_V6_UNRECOGNIZE_NEXT_HDR 0x1
#define ICMP_V6_UNRECOGNIZE_OPTION 0x2
28.6.6 EFI_IP6_PROTOCOL.Conﬁgure()
Summary
Assign IPv6 address and other conﬁguration parameter to this EFI IPv6 Protocol driver instance.
Prototype
typedef
(EFIAPI *EFI_IP6_CONFIGURE) (
IN EFI_IP6_CONFIG_DATA *Ip6ConfigData OPTIONAL
);
28.6. EFI IPv6 Protocol 1154Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Ip6ConﬁgData Pointer to the EFI IPv6 Protocol conﬁguration data structure. Type EFI_IP6_CONFIG_DATA is
deﬁned in EFI_IP6_PROTOCOL.GetModeData().
TheConﬁgure() function is used to set, change, or reset the operational parameters and ﬁlter settings for this EFI IPv6
Once the parameters have been reset (by calling this function with Ip6ConﬁgData set to NULL ), no more trafﬁc can
be sent or received until these parameters have been set again. Each EFI IPv6 Protocol instance can be started and
IfIp6ConﬁgData.StationAddress is a valid non-zero IPv6 unicast address, it is required to be one of the currently
conﬁgured IPv6 addresses list in the EFI IPv6 drivers, or else EFI_INVALID_PARAMETER will be returned. If
Ip6ConﬁgData.StationAddress is unspeciﬁed, the IPv6 driver will bind a source address according to the source ad-
dress selection algorithm. Clients could frequently call GetModeData() to check get currently conﬁgured IPv6 address
list in the EFI IPv6 driver. If both Ip6ConﬁgData.StationAddress andIp6ConﬁgData.Destination are unspeciﬁed,
when transmitting the packet afterwards, the source address ﬁlled in each outgoing IPv6 packet is decided based on
the destination of this packet.
This isNULL .
Ip6ConﬁgData.StationAddress is neither zero nor a unicast IPv6 address.
Ip6ConﬁgData.StationAddress is neither zero nor one of the conﬁgured IP
addresses in the EFI IPv6 driver.
Ip6ConﬁgData.DefaultProtocol is illegal.
EFI_OUT_OF_RESOURCES The EFI IPv6 Protocol driver instance data could not be allocated.
EFI_NO_MAPPING The IPv6 driver was responsible for choosing a source address for this in-
stance, but no source address was available for use.
EFI_ALREADY_STARTED The interface is already open and must be stopped before the IPv6 address
or preﬁx length can be changed.
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI IPv6 Protocol
Default protocol speciﬁed through
Ip6ConﬁgData.DefaulProtocol isn’t supported.
28.6. EFI IPv6 Protocol 1155Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.6.7 EFI_IP6_PROTOCOL.Groups()
Summary
Prototype
typedef
(EFIAPI *EFI_IP6_GROUPS) (
IN EFI_IPv6_ADDRESS *GroupAddress OPTIONAL
);
GroupAddress Pointer to the IPv6 multicast address.
matching multicast packets. Leaving a group will disable reception of matching multicast packets. Source-Speciﬁc
Multicast isn’t required to be supported.
JoinFlag isTRUE andGroupAddress isNULL
GroupAddress is not NULL and * GroupAddress is not a multicast IPv6
address.
GroupAddress is not NULL and * GroupAddress is in the range of SSM
destination address.

);
address.
EFI_UNSUPPORTED This EFI IPv6 Protocol implementation does not support multicast groups.
28.6. EFI IPv6 Protocol 1156Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.6.8 EFI_IP6_PROTOCOL.Routes()
Summary
Prototype
typedef
(EFIAPI *EFI_IP6_ROUTES) (
IN EFI_IPv6_ADDRESS *Destination OPTIONAL,
IN UINT8 PrefixLength,
IN EFI_IPv6_ADDRESS *GatewayAddress OPTIONAL
);
table. Destination, PreﬁxLength andGateway are used as the key to each route entry.
Destination The address preﬁx of the subnet that needs to be routed.
PreﬁxLength The preﬁx length of Destination . Ignored if Destination is NULL .
GatewayAddress The unicast gateway IPv6 address for this route.
Routes are determined by comparing the leftmost PreﬁxLength bits of Destination with the destination IPv6 address
arithmetically. The gateway address must be on the same subnet as the conﬁgured station address.
The default route is added with Destination andPreﬁxLegth both set to all zeros. The default route matches all
destination IPv6 addresses that do not match any other routes.
All EFI IPv6 Protocol instances share a routing table.
own independent network stack that shares information only through the EFI IPv6 variable .
When DeleteRoute isTRUE , both Destination andGatewayAddress are
NULL
When DeleteRoute isFALSE, either Destination orGatewayAddress is
NULL
*GatewayAddress is not a valid unicast IPv6 address.
*GatewayAddress is one of the local conﬁgured IPv6 addresses.
28.6. EFI IPv6 Protocol 1157Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.38 – continued from previous page
FALSE ).
28.6.9 EFI_IP6_PROTOCOL.Neighbors()
Summary
Add or delete Neighbor cache entries.
Prototype
typedef
(EFIAPI *EFI_IP6_NEIGHBORS) (
IN BOOLEAN DeleteFlag,
IN EFI_IPv6_ADDRESS *TargetIp6Address,
IN EFI_MAC_ADDRESS *TargetLinkAddress OPTIONAL
IN BOOLEAN Override
);
DeleteFlag Set to TRUE to delete the speciﬁed cache entry, set to FALSE to add (or update, if it already exists and
Override isTRUE ) the speciﬁed cache entry. TargetIp6Address is used as the key to ﬁnd the requested cache
entry.
TargetIp6Address Pointer to Target IPv6 address.
TargetLinkAddress Pointer to link-layer address of the target. Ignored if NULL .
Timeout Time in 100-ns units that this entry will remain in the neighbor cache, it will be deleted after Timeout. A
value of zero means that the entry is permanent. A non-zero value means that the entry is dynamic.
Override IfTRUE, the cached link-layer address of the matching entry will be overridden and updated; if FALSE,
EFI_ACCESS_DENIED will be returned if a corresponding cache entry already existed.
TheNeighbors() function is used to add, update, or delete an entry from neighbor cache.
IPv6 neighbor cache entries are typically inserted and updated by the network protocol driver as network trafﬁc is
processed. Most neighbor cache entries will time out and be deleted if the network trafﬁc stops. Neighbor cache
entries that were inserted by Neighbors() may be static (will not timeout) or dynamic (will time out).
The implementation should follow the neighbor cache timeout mechanism which is deﬁned in RFC4861. The default
neighbor cache timeout value should be tuned for the expected network environment.
28.6. EFI IPv6 Protocol 1158Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.39 – continued from previous page
This is NULL .
TargetIpAddress isNULL .
*TargetLinkAddress is invalid when not NULL.
*TargetIpAddress is not a valid unicast IPv6 address.
*TargetIpAddress is one of the local conﬁgured IPv6 addresses.
EFI_OUT_OF_RESOURCES Could not add the entry to the neighbor cache.
EFI_NOT_FOUND This entry is not in the neighbor cache (when DeleteFlag isTRUE or when
DeleteFlag isFALSE while TargetLinkAddress isNULL. ).
EFI_ACCESS_DENIED The to-be-added entry is already deﬁned in the neighbor cache, and that
entry is tagged as un-overridden (when DeleteFlag isFALSE ).
28.6.10 EFI_IP6_PROTOCOL.Transmit()
Summary
Prototype
typedef
(EFIAPI *EFI_IP6_TRANSMIT) (
IN EFI_IP6_COMPLETION_TOKEN *Token
);
Token Pointer to the transmit token. Type EFI_IP6_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions”
below.
TheTransmit( ) function places a sending request in the transmit queue of this EFI IPv6 Protocol instance. Whenever
// EFI_IP6_COMPLETION_TOKEN
union {
EFI_IP6_RECEIVE_DATA *RxData;
EFI_IP6_TRANSMIT_DATA *TxData;
} Packet;
} EFI_IP6_COMPLETION_TOKEN;
28.6. EFI IPv6 Protocol 1159Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Event This Event will be signaled after the Status ﬁeld is updated by the EFI IPv6 Protocol driver. The type of Event
must be EFI_NOTIFY_SIGNAL .
EFI_ICMP_ERROR: An ICMP error packet was received.
EFI_DEVICE_ERROR: An unexpected system or network error occurred.
EFI_SECURITY_VIOLATION: The transmit or receive was failed because of an IPsec policy check.
RxData When the Token is used for receiving, RxData is a pointer to the EFI_IP6_RECEIVE_DATA . Type
EFI_IP6_RECEIVE_DATA is deﬁned below.
TxData When the Token is used for transmitting, TxData is a pointer to the EFI_IP6_TRANSMIT_DATA . Type
EFI_IP6_TRANSMIT_DATA is deﬁned below.
EFI_IP6_COMPLETION_TOKEN structures are used for both transmit and receive operations.
When the structure is used for transmitting, the Event andTxData ﬁelds must be ﬁlled in by the EFI IPv6 Protocol
client. After the transmit operation completes, the EFI IPv6 Protocol driver updates the Status ﬁeld and the Event is
signaled.
When the structure is used for receiving, only the Event ﬁeld must be ﬁlled in by the EFI IPv6 Protocol client. After a
packet is received, the EFI IPv6 Protocol driver ﬁlls in the RxData and Status ﬁelds and the Event is signaled
//*******************************************
// EFI_IP6_RECEIVE_DATA
typedef struct _EFI_IP6_RECEIVE_DATA {
EFI_IP6_HEADER *Header;
EFI_IP6_FRAGMENT_DATA FragmentTable[1];
} EFI_IP6_RECEIVE_DATA;
TimeStamp Time when the EFI IPv6 Protocol driver accepted the packet. TimeStamp is zero ﬁlled if timestamps are
disabled or unsupported .
HeaderLength Length of the IPv6 packet headers, including both the IPv6 header and any extension headers.
28.6. EFI IPv6 Protocol 1160Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Header Pointer to the IPv6 packet header. If the IPv6 packet was fragmented, this argument is a pointer to the header
in the ﬁrst fragment. Type EFI_IP6_HEADER is deﬁned below.

DataLength Sum of the lengths of IPv6 packet buffers in FragmentTable. May be zero.
FragmentCount Number of IPv6 payload fragments. May be zero.
FragmentTable Array of payload fragment lengths and buffer pointers. Type EFI_IP6_FRAGMENT_DATA is de-
ﬁned below.
The EFI IPv6 Protocol receive data structure is ﬁlled in when IPv6 packets have been assembled. In the case of IPv6
packet assembly, the individual packet fragments are only veriﬁed and are not reorganized into a single linear buffer.
//****************************************
// EFI_IP6_HEADER
typedef struct _EFI_IP6_HEADER {
UINT8 TrafficClassH:4;
UINT8 FlowLabelH:4;
UINT8 TrafficClassL:4;
UINT16 FlowLabelL;
UINT16 PayloadLength;
UINT8 NextHeader;
EFI_IPv6_ADDRESS SourceAddress;
} EFI_IP6_HEADER;
#pragma pack
The ﬁelds in the IPv6 header structure are deﬁned in the Internet Protocol version6 speciﬁcation, which can be found
at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “Internet Protocol version 6 Speciﬁca-
tion”.
// EFI_IP6_FRAGMENT_DATA
typedef struct _EFI_IP6_FRAGMENT_DATA {
} EFI_IP6_FRAGMENT_DATA;
TheEFI_IP6_FRAGMENT_DATA structure describes the location and length of the IPv6 packet fragment to transmit
// EFI_IP6_TRANSMIT_DATA
typedef struct _EFI_IP6_TRANSMIT_DATA {
EFI_IP6_OVERRIDE_DATA *OverrideData;
UINT32 ExtHdrsLength;
28.6. EFI IPv6 Protocol 1161Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
VOID *ExtHdrs;
UINT32 FragmentCount
} EFI_IP6_TRANSMIT_DATA;
DestinationAddress The destination IPv6 address. If it is unspeciﬁed, ConﬁgData.DestinationAddress will be used
instead.
OverrideData If not NULL, the IPv6 transmission control override data. Type EFI_IP6_OVERRIDE_DATA is deﬁned
below.
ExtHdrsLength Total length in byte of the IPv6 extension headers speciﬁed in ExtHdrs
ExtHdrs Pointer to the IPv6 extension headers. The IP layer will append the required extension headers if they are
not speciﬁed by ExtHdrs. Ignored if ExtHdrsLength is zero.
NextHeader The protocol of ﬁrst extension header in ExtHdrs . Ignored if ExtHdrsLength is zero.
DataLength Total length in bytes of the FragmentTable data to transmit.
FragmentTable Start of the fragment data table. Type EFI_IP6_FRAGMENT_DATA is deﬁned above.
TheEFI_IP6_TRANSMIT_DATA structure describes a possibly fragmented packet to be transmitted.
// EFI_IP6_OVERRIDE_DATA
typedef struct _EFI_IP6_OVERRIDE_DATA {
} EFI_IP6_OVERRIDE_DATA;
HopLimit Hop-Limit override.
FlowLabel Flow-Label override.
EFI_NO_MAPPING The IPv6 driver was responsible for choosing a source address for this trans-
mission, but no source address was available for use.
28.6. EFI IPv6 Protocol 1162Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.40 – continued from previous page
•Token.Packet.TxData isNULL .
•Token.Packet.ExtHdrsLength is not zero and
Token.Packet.ExtHdrs isNULL .
Token.Packet.TxDat FragmentTable[].FragmentLength ﬁelds is zero.
• One or more of the Token.Packet.TxDat FragmentTable[].FragmentBuffer
ﬁelds is NULL .
•Token.Packet.TxData.DataLength is zero or not equal to the sum of
•Token.Packet.TxData.DestinationAddress is non-zero when
DestinationAddress is conﬁgured as non-zero when doing Conﬁgure() for
this EFI IPv6 protocol instance.
•Token. Packet.TxData.DestinationAddress is unspeciﬁed when
DestinationAddress is unspeciﬁed when doing Conﬁgure() for this EFI
IPv6 protocol instance.
full.
EFI_NOT_FOUND No route was found to destination address.
EFI_BUFFER_TOO_SMALL Token.Packet.TxData.DataLength is too short to transmit.
EFI_BAD_BUFFER_SIZE IfToken.Packet.TxData.DataLength is beyond the maximum that which can
be described through the Fragment Offset ﬁeld in Fragment header when
performing fragmentation.
28.6.11 EFI_IP6_PROTOCOL.Receive()
Summary
Prototype
typedef
(EFIAPI *EFI_IP6_RECEIVE) (
);
28.6. EFI IPv6 Protocol 1163Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Token Pointer to a token that is associated with the receive data descriptor. Type EFI_IP6_COMPLETION_TOKEN
operation completes, the EFI IPv6 Protocol driver updates the Token.Status andToken.Packet.RxData ﬁelds and the
EFI_NOT_STARTED This EFI IPv6 Protocol instance has not been started.
EFI_NO_MAPPING When IP6 driver responsible for binding source address to this instance,
while no source address is available for use.
Token isNULL .
Token.Event isNULL .
28.6.12 EFI_IP6_PROTOCOL.Cancel()
Summary
Abort an asynchronous transmits or receive request.
Prototype
typedef
(EFIAPI *EFI_IP6_CANCEL)(
IN EFI_IP6_COMPLETION_TOKEN *Token OPTIONAL
);
Token Pointer to a token that has been issued by EFI_IP6_PROTOCOL.Transmit() or
EFI_IP6_PROTOCOL.Receive() . If NULL, all pending tokens are aborted. Type
EFI_IP6_COMPLETION_TOKEN is deﬁned in EFI_IP6_PROTOCOL.Transmit() .
28.6. EFI IPv6 Protocol 1164Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The asynchronous I/O request was aborted and Token->Event was signaled.

28.6.13 EFI_IP6_PROTOCOL.Poll()
Summary
Prototype
typedef
(EFIAPI *EFI_IP6_POLL) (
IN EFI_IP6_PROTOCOL *This
);
cations can call the EFI_IP6_PROTOCOL.Poll() function to increase the rate that data packets are moved between the
communications device and the transmit and receive queues.
tions that are experiencing packet loss should try calling the EFI_IP6_PROTOCOL.Poll() function more often.
28.6. EFI IPv6 Protocol 1165Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.7 EFI IPv6 Conﬁguration Protocol
This section provides a detailed description of the EFI IPv6 Conﬁguration Protocol.
28.7.1 EFI_IP6_CONFIG_PROTOCOL
Summary
TheEFI_IP6_CONFIG_PROTOCOL provides the mechanism to set and get various types of conﬁgurations for the
EFI IPv6 network stack.
GUID
#define EFI_IP6_CONFIG_PROTOCOL_GUID \
{0x937fe521,0x95ae,0x4d1a,\
{0x89,0x29,0x48,0xbc,0xd9,0x0a,0xd3,0x1a}
typedef struct _EFI_IP6_CONFIG_PROTOCOL {
EFI_IP6_CONFIG_SET_DATA SetData;
EFI_IP6_CONFIG_GET_DATA GetData;
EFI_IP6_CONFIG_REGISTER_NOTIF RegisterDataNotify;
EFI_IP6_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify;
} EFI_IP6_CONFIG_PROTOCOL;
SetData Set the conﬁguration for the EFI IPv6 network stack running on the communication device this EFI IPv6
Conﬁguration Protocol instance manages. See the SetData() function description.
GetData Get the conﬁguration or register an event to monitor the change of the conﬁguration for the EFI IPv6 network
stack running on the communication device this EFI IPv6 Conﬁguration Protocol instance manages. See the
GetData() function description.
TheEFI_IP6_CONFIG_PROTOCOL is designed to be the central repository for the common conﬁgurations and the
administrator conﬁgurable settings for the EFI IPv6 network stack.
An EFI IPv6 Conﬁguration Protocol instance will be installed on each communication device that the EFI IPv6 network
stack runs on.
28.7. EFI IPv6 Conﬁguration Protocol 1166Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.7.2 EFI_IP6_CONFIG_PROTOCOL.SetData()
Summary
Set the conﬁguration for the EFI IPv6 network stack running on the communication device this EFI IPv6 Conﬁguration
Protocol instance manages.
Prototype
typedef
(EFIAPI *EFI_IP6_CONFIG_SET_DATA) (
IN EFI_IP6_CONFIG_PROTOCOL *This,
IN EFI_IP6_CONFIG_DATA_TYPE DataType,
);
This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
DataType The type of data to set. Type EFI_IP6_CONFIG_DATA_TYPE is deﬁned in “Related Deﬁnitions” below.
This function is used to set the conﬁguration data of type DataType for the EFI IPv6 network stack running on the
communication device this EFI IPv6 Conﬁguration Protocol instance manages.
TheDataSize is used to calculate the count of structure instances in the Data for some DataType that multiple structure
invoked to check the correctness of the data, such as doing Duplicate Address Detection on the manually set local
IPv6 addresses. EFI_NOT_READY is returned immediately to indicate that such an asynchronous process is invoked
and the process is not ﬁnished yet. The caller willing to get the result of the asynchronous process is required to call
// EFI_IP6_CONFIG_DATA_TYPE
Ip6ConfigDataTypeInterfaceInfo,
Ip6ConfigDataTypeAltInterfaceId,
Ip6ConfigDataTypePolicy,
Ip6ConfigDataTypeDupAddrDetectTransmits,
Ip6ConfigDataTypeManualAddress,
Ip6ConfigDataTypeGateway,
Ip6ConfigDataTypeDnsServer,
Ip6ConfigDataTypeMaximum
} EFI_IP6_CONFIG_DATA_TYPE;
28.7. EFI IPv6 Conﬁguration Protocol 1167Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Ip6ConﬁgDataTypeInterfaceInfo The interface information of the communication device this EFI IPv6 Conﬁg-
uration Protocol instance manages. This type of data is read only. The corresponding Data is of type
EFI_IP6_CONFIG_INTERFACE_INFO .
Ip6ConﬁgDataTypeAltInterfaceId The alternative interface ID for the communication device this EFI IPv6 Conﬁg-
uration Protocol instance manages if the link local IPv6 address generated from the interfaced ID based on the
default source the EFI IPv6 Protocol uses is a duplicate address. The length of the interface ID is 64 bit. The
corresponding Data is of type EFI_IP6_CONFIG_INTERFACE_ID .
Ip6ConﬁgDataTypePolicy The general conﬁguration policy for the EFI IPv6 network stack running on the communi-
cation device this EFI IPv6 Conﬁguration Protocol instance manages. The policy will affect other conﬁguration
settings. The corresponding Data is of type EFI_IP6_CONFIG_POLICY .
Ip6ConﬁgDataTypeDupAddrDetectTransmits The number of consecutive Neighbor Solicitation messages sent
while performing Duplicate Address Detection on a tentative address. A value of zero indicates that Du-
plicate Address Detection will not be performed on tentative addresses. The corresponding Data is of type
EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS .
Ip6ConﬁgDataTypeManualAddress The station addresses set manually for the EFI IPv6 network stack. It is only
conﬁgurable when the policy is Ip6ConﬁgPolicyManual . The corresponding Data is a pointer to an array of
EFI_IPv6_ADDRESS instances. When DataSize is 0 and Data isNULL, the existing conﬁguration is cleared
from the EFI IPv6 Conﬁguration Protocol instance.
Ip6ConﬁgDataTypeGateway The gateway addresses set manually for the EFI IPv6 network stack running on the
communication device this EFI IPv6 Conﬁguration Protocol manages. It is not conﬁgurable when the policy is
Ip6ConﬁgPolicyAutomatic . The gateway addresses must be unicast IPv6 addresses. The corresponding Data is
a pointer to an array of EFI_IPv6_ADDRESS instances. When DataSize is 0 and Data isNULL, the existing
conﬁguration is cleared from the EFI IPv6 Conﬁguration Protocol instance.
Ip6ConﬁgDataTypeDnsServer The DNS server list for the EFI IPv6 network stack running on the communi-
cation device this EFI IPv6 Conﬁguration Protocol manages. It is not conﬁgurable when the policy is
Ip6ConﬁgPolicyAutomatic .The DNS server addresses must be unicast IPv6 addresses. The corresponding Data
is a pointer to an array of EFI_IPv6_ADDRESS instances. When DataSize is 0 and Data isNULL, the existing
// EFI_IP6_CONFIG_INTERFACE_INFO
CHAR16 Name[32];
UINT32 AddressInfoCount;
EFI_IP6_ADDRESS_INFO *AddressInfo;
} EFI_IP6_CONFIG_INTERFACE_INFO;
Name The name of the interface. It is a NULL-terminated string.
IfType The interface type of the network interface. See RFC 3232, section “Number Hardware Type”.

AddressInfoCount Number of EFI_IP6_ADDRESS_INFO structures pointed to by AddressInfo.
AddressInfo Pointer to an array of EFI_IP6_ADDRESS_INFO instances which contain the local IPv6 addresses
and the corresponding preﬁx length information. Set to NULL ifAddressInfoCount is zero. Type
28.7. EFI IPv6 Conﬁguration Protocol 1168Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_IP6_ADDRESS_INFO is deﬁned in EFI_IP6_PROTOCOL.GetModeData() .
RouteCount Number of route table entries in the following RouteTable .
RouteTable The route table of the IPv6 network stack runs on this interface. Set to NULL ifRouteCount is zero.
Type EFI_IP6_ROUTE_TABLE is deﬁned in EFI_IP6_PROTOCOL.GetModeData() .
The EFI_IP6_CONFIG_INTERFACE_INFO structure describes the operational state of the interface this EFI IPv6
Conﬁguration Protocol instance manages. This type of data is read-only. When reading, the caller allocated buffer
is used to return all of the data, i.e., the ﬁrst part of the buffer is EFI_IP6_CONFIG_INTERFACE_INFO and the
followings are the array of EFI_IP6_ADDRESS_INFO and the route table if present. The caller should NOT free the
buffer pointed to by AddressInfo or RouteTable, and the caller is only required to free the whole buffer if the data is
not needed any more.
// EFI_IP6_CONFIG_INTERFACE_ID
UINT8 Id[8];
} EFI_IP6_CONFIG_INTERFACE_ID;
TheEFI_IP6_CONFIG_INTERFACE_ID structure describes the 64-bit interface ID.
// EFI_IP6_CONFIG_POLICY
Ip6ConfigPolicyManual,
Ip6ConfigPolicyAutomatic
} EFI_IP6_CONFIG_POLICY;
Ip6ConﬁgPolicyManual Under this policy, the IpI6ConﬁgDataTypeManualAddress, Ip6ConﬁgDataTypeGateway
andIp6ConﬁgDataTypeDnsServer conﬁguration data are required to be set manually. The EFI IPv6 Protocol
will get all required conﬁguration such as address, preﬁx and gateway settings from the EFI IPv6 Conﬁguration
protocol.
Ip6ConﬁgPolicyAutomatic Under this policy, the IpI6ConﬁgDataTypeManualAddress, Ip6ConﬁgDataTypeGateway
andIp6ConﬁgDataTypeDnsServer conﬁguration data are not allowed to set via SetData() . All of these conﬁgu-
rations are retrieved from some auto conﬁguration mechanism. The EFI IPv6 Protocol will use the IPv6 stateless
address autoconﬁguration mechanism and/or the IPv6 stateful address autoconﬁguration mechanism described
in the related RFCs to get address and other conﬁguration information.
TheEFI_IP6_CONFIG_POLICY deﬁnes the general conﬁguration policy the EFI IPv6 Conﬁguration Protocol sup-
ports. The default policy for a newly detected communication device is beyond the scope of this document. An
The conﬁguration data of type IpI6ConﬁgDataTypeManualAddress, Ip6ConﬁgDataTypeGateway and
Ip6ConﬁgDataTypeDnsServer will be ﬂushed if the policy is changed from Ip6ConﬁgPolicyManual to
Ip6ConﬁgPolicyAutomatic .
// EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS
UINT32 DupAddrDetectTransmits;
} EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS;
TheEFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS structure describes the number of consecutive Neigh-
bor Solicitation messages sent while performing Duplicate Address Detection on a tentative address. The default value
28.7. EFI IPv6 Conﬁguration Protocol 1169Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
for a newly detected communication device is 1.
// EFI_IP6_CONFIG_MANUAL_ADDRESS
BOOLEAN IsAnycast;
} EFI_IP6_CONFIG_MANUAL_ADDRESS;
Address The IPv6 unicast address.
IsAnycast Set to TRUE ifAddress is anycast.
PreﬁxLength The length, in bits, of the preﬁx associated with this Address .
The EFI_IP6_CONFIG_MANUAL_ADDRESS structure is used to set the station address information for the EFI
IPv6 network stack manually when the policy is Ip6ConﬁgPolicyManual.
EFI_SUCCESS The speciﬁed conﬁguration data for the EFI IPv6 network stack is set suc-
cess.
28.7.3 EFI_IP6_CONFIG_PROTOCOL.GetData()
Summary
Get the conﬁguration data for the EFI IPv6 network stack running on the communication device this EFI IPv6 Con-
ﬁguration Protocol instance manages.
Prototype
typedef
(EFIAPI *EFI_IP6_CONFIG_GET_DATA) (
28.7. EFI IPv6 Conﬁguration Protocol 1170Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
DataType The type of data to get. Type EFI_IP6_CONFIG_DATA_TYPE is deﬁned in
EFI_IP6_CONFIG_PROTOCOL.SetData() .
This function returns the conﬁguration data of type DataType for the EFI IPv6 network stack running on the commu-
nication device this EFI IPv6 Conﬁguration Protocol instance manages.
•DataSize isNULL .
•Data isNULL if *DataSize is not zero.
28.7.4 EFI_IP6_CONFIG_PROTOCOL.RegisterDataNotify ()
Summary
Prototype
typedef
(EFIAPI *EFI_IP6_CONFIG_REGISTER_NOTIFY) (
28.7. EFI IPv6 Conﬁguration Protocol 1171Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
DataType The type of data to unregister the event for. Type EFI_IP6_CONFIG_DATA_TYPE is deﬁned in
EFI_INV ALID_PARAMETER This is NULL or Event is NULL .

);
EFI_ACCESS_DENIED The Event is already registered for the DataType.
28.7.5 EFI_IP6_CONFIG_PROTOCOL.UnregisterDataNotify()
Summary
Prototype
typedef
(EFIAPI *EFI_IP6_CONFIG_UNREGISTER_NOTIFY) (
);
DataType The type of data to remove the previously registered event for. Type EFI_IP6_CONFIG_DATA_TYPE is
deﬁned in EFI_IP6_CONFIG_PROTOCOL.SetD ata().
28.7. EFI IPv6 Conﬁguration Protocol 1172Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_INV ALID_PARAMETER This is NULL or Event is NULL
EFI_NOT_FOUND The event has not been registered for the speciﬁed DataType.
28.8 IPsec
28.8.1 IPsec Overview
IPsec is a framework of open standards that provides data conﬁdentiality, data integrity, data authentication and replay
protection between participating peers. A set of security services is provided by IPsec for trafﬁc at the IP layer, in both
the IPv4 and IPv6 environment. To the stronger, IPV6 requires IPSec support.
IPsec is documented in a series of Internet RFCs. The overall IPsec architecture and implementation are guided by
“Security Architecture for the Internet Protocol”, RFC 4301.
Two different security protocols - Authentication Header (AH, described in RFC 4302) and Encapsulated Security
Payload (ESP, described in RFC 4303) - are used to provide package-level security for IP datagram.
This section attempts to capture the generic conﬁguration for an IPsec implementation in an EFI environment.
28.8.2 EFI IPsec Conﬁguration Protocol
This section provides a detailed description of the EFI IPsec Conﬁguration Protocol. This protocol sets and obtains
the IPsec conﬁguration information.
28.8.3 EFI_IPSEC_CONFIG_PROTOCOL
Summary
TheEFI_IPSEC_CONFIG_PROTOCOL provides the mechanism to set and retrieve security and policy related infor-
mation for the EFI IPsec protocol driver.
GUID
#define EFI_IPSEC_CONFIG_PROTOCOL_GUID \
{0xce5e5929,0xc7a3,0x4602,\
{0xad,0x9e,0xc9,0xda,0xf9,0x4e,0xbf,0xcf}}
typedef struct _EFI_IPSEC_CONFIG_PROTOCOL {
EFI_IPSEC_CONFIG_SET_DATA SetData;
EFI_IPSEC_CONFIG_GET_DATA GetData;
EFI_IPSEC_CONFIG_GET_NEXT_SELECTOR GetNextSelector;
EFI_IPSEC_CONFIG_REGISTER_NOTIFY RegisterDataNotify;
EFI_IPSEC_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify;
} EFI_IPSEC_CONFIG_PROTOCOL;
SetData Set the conﬁguration and control information for the EFI IPsec protocol driver. See the SetData() function
GetData Look up and retrieve the IPsec conﬁguration data. See the GetData() function description.
28.8. IPsec 1173Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetNextSelector Enumerates the current IPsec conﬁguration data entry selector. See the GetNextSelector() function
RegiseterNotify Register an event that is to be signaled whenever a conﬁguration process on the speciﬁed IPsec
conﬁguration data is done.
UnregisterNotify Remove a registered event for the speciﬁed IPsec conﬁguration data.
TheEFI_IPSEC_CONFIG_PROTOCOL provides the ability to set and lookup the IPsec SAD (Security Association
Database), SPD (Security Policy Database) data entry and conﬁgure the security association management protocol
such as IKEv2. This protocol is used as the central repository of any policy-speciﬁc conﬁguration for EFI IPsec driver.
EFI_IPSEC_CONFIG_PROTOCOL can be bound to both IPv4 and IPv6 stack. User can use this protocol for IPsec
conﬁguration in both IPv4 and IPv6 environment.
28.8.4 EFI_IPSEC_CONFIG_PROTOCOL.SetData()
Summary
Set the security association, security policy and peer authorization conﬁguration information for the EFI IPsec driver.
Prototype
typedef
(EFIAPI *EFI_IPSEC_CONFIG_SET_DATA) (
IN EFI_IPSEC_CONFIG_PROTOCOL *This,
IN EFI_IPSEC_CONFIG_DATA_TYPE DataType,
IN EFI_IPSEC_CONFIG_SELECTOR *Selector
IN EFI_IPSEC_CONFIG_SELECTOR *InsertBefore OPTIONAL
);
This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
InsertBefore Pointer to one entry selector which describes the expected position the new data entry will be added. If
InsertBefore isNULL, the new entry will be appended the end of database.
DataType The type of data to be set. Type EFI_IPSEC_CONFIG_DATA_TYPE is deﬁned in “Related Deﬁnitions”
below.
Selector Pointer to an entry selector on operated conﬁguration data speciﬁed by DataType . ANULL Selector causes
the entire speciﬁed-type conﬁguration information to be ﬂushed.
Data The data buffer to be set. The structure of the data buffer is associated with the DataType . The various types are
This function is used to set the IPsec conﬁguration information of type DataType for the EFI IPsec driver.
The IPsec conﬁguration data has a unique selector/identiﬁer separately to identify a data entry. The selector structure
depends on DataType’s deﬁnition.
Using SetData() with a Data ofNULL causes the IPsec conﬁguration data entry identiﬁed by DataType and Selector
to be deleted.
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// EFI_IPSEC_CONFIG_DATA_TYPE
IPsecConfigDataTypeSpd,
IPsecConfigDataTypeSad,
IPsecConfigDataTypePad,
IPsecConfigDataTypeMaximum
} EFI_IPSEC_CONFIG_DATA_TYPE;
IPsecConﬁgDataTypeSpd The IPsec Security Policy Database (aka SPD) setting. In IPsec, an essential element of
Security Association (SA) processing is underlying SPD that speciﬁes what services are to be offered to IP
datagram and in what fashion. The SPD must be consulted during the processing of all trafﬁc (inbound and out-
bound), including trafﬁc not protected by IPsec, that traverses the IPsec boundary. With this DataType, SetData()
function is to set the SPD entry information, which may add one new entry, delete one existed entry or ﬂush the
whole database according to the parameter values. The corresponding Data is of type EFI_IPSEC_SPD_DATA .
IPsecConﬁgDataTypeSad The IPsec Security Association Database (aka SAD) setting. A SA is a simplex con-
nection that affords security services to the trafﬁc carried by it. Security services are afforded to an SA
by the use of AH, or ESP, but not both. The corresponding Data is of type EFI_IPSEC_SA_DATA2 or
EFI_IPSEC_SAD_DATA. Compared with EFI_IPSEC_SA_DATA, theEFI_IPSEC_SA_DATA2 contains the ex-
tra Tunnel Source Address and Tunnel Destination Address thus it is recommended to be use if the implemen-
tation supports tunnel mode.
IPsecConﬁgDataTypePad The IPsec Peer Authorization Database (aka PAD) setting, which provides the link be-
tween the SPD and a security association management protocol. The PAD entry speciﬁes the authentication
protocol (e.g. IKEv1, IKEv2) method used and the authentication data. The corresponding Data is of type
EFI_IPSEC_PAD_DATA .
// EFI_IPSEC_CONFIG_SELECTOR
EFI_IPSEC_SPD_SELECTOR SpdSelector;
EFI_IPSEC_SA_ID SaId;
EFI_IPSEC_PAD_ID PadId;
} EFI_IPSEC_CONFIG_SELECTOR;
The EFI_IPSEC_CONFIG_SELECTOR describes the expected IPsec conﬁguration data selector of type
EFI_IPSEC_CONFIG_DATA_TYPE .
// EFI_IPSEC_SPD_SELECTOR
typedef struct _EFI_IPSEC_SPD_SELECTOR {
UINT32 LocalAddressCount;
EFI_IP_ADDRESS_INFO *LocalAddress;
UINT32 RemoteAddressCount;
EFI_IP_ADDRESS_INFO *RemoteAddress;
UINT16 NextLayerProtocol;
// Several additional selectors depend on the ProtoFamily
UINT16 LocalPort;
UINT16 LocalPortRange;
UINT16 RemotePortRange;
} EFI_IPSEC_SPD_SELECTOR;
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LocalAddressCount Speciﬁes the actual number of entries in LocalAddress .
LocalAddress A list of ranges of IPv4 or IPv6 addresses, which refers to the addresses being protected by IPsec
policy.
RemoteAddressCount Speciﬁes the actual number of entries in RemoteAddress .
RemoteAddress A list of ranges of IPv4 or IPv6 addresses, which are peer entities to LocalAddress .
NextLayerProtocol Next layer protocol. Obtained from the IPv4 Protocol or the IPv6 Next Header ﬁelds. The next
layer protocol is whatever comes after any IP extension headers that are present. A zero value is a wildcard that
matches any value in NextLayerProtocol ﬁeld.

policy.
LocalPort Local Port if the Next Layer Protocol uses two ports (as do TCP, UDP, and others). A zero value is a
wildcard that matches any value in LocalPort ﬁeld.
LocalPortRange A designed port range size. The start port is LocalPort, and the total number of ports is described
byLocalPortRange . This ﬁeld is ignored if NextLayerProtocol does not use ports.
RemotePort Remote Port if the Next Layer Protocol uses two ports. A zero value is a wildcard that matches any
value in RemotePort ﬁeld.
RemotePortRange A designed port range size. The start port is RemotePort, and the total number of ports is described
byRemotePortRange . This ﬁeld is ignored if NextLayerProtocol does not use ports.
NOTE :TheLocalPort andRemotePort selectors have different meaning depending on the NextLayerProtocol ﬁeld.
for example, if NextLayerProtocol value is ICMP , LocalPort andRemotePort describe the ICMP message type and
code. This is described in section 4.4.1.1 of RFC 4301).
// EFI_IP_ADDRESS_INFO
typedef struct _EFI_IP_ADDRESS_INFO {
EFI_IP_ADDRESS Address;
} EFI_IP_ADDRESS_INFO;
Address The IPv4 or IPv6 address.
#define MAX_PEERID_LEN 128
// EFI_IPSEC_SPD_DATA
typedef struct _EFI_IPSEC_SPD_DATA {
UINT8 *Name[MAX_PEERID_LEN];
UINT32 PackageFlag;
EFI_IPSEC_TRAFFIC_DIR TrafficDirection;
EFI_IPSEC_ACTION Action;
EFI_IPSEC_PROCESS_POLICY *ProcessingPolicy;
UINTN SaIdCount;
EFI_IPSEC_SA_ID *SaId[1];
} EFI_IPSEC_SPD_DATA;
Name A null-terminated ASCII name string which is used as a symbolic identiﬁer for an IPsec Local or Remote
address. The Name is optional, and can be NULL .
PackageFlag Bit-mapped list describing Populate from Packet ﬂags. When creating a SA, if PackageFlag bit is set to
TRUE , instantiate the selector from the corresponding ﬁeld in the package that triggered the creation of the SA,
else from the value(s) in the corresponding SPD entry. The PackageFlag bit setting for corresponding selector
ﬁeld of EFI_IPSEC_SPD_SELECTOR:
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Bit 0: EFI_IPSEC_SPD_SELECTOR .LocalAddress
Bit 1: EFI_IPSEC_SPD_SELECTOR .RemoteAddress
Bit 2: EFI_IPSEC_SPD_SELECTOR .NextLayerProtocol
Bit 3: EFI_IPSEC_SPD_SELECTOR .LocalPort
Bit 4: EFI_IPSEC_SPD_SELECTOR .RemotePort
Others: Reserved.
TrafﬁcDirection The trafﬁc direction of data gram.
Action Processing choices to indicate which action is required by this policy.
ProcessingPolicy The policy and rule information for a SPD entry. The type EFI_IPSEC_PROCESSPOLICY is
deﬁned in below.
SaIdCount Speciﬁes the actual number of entries in SaId list.
SaId Pointer to the SAD entry used for the trafﬁc processing. The existed SAD entry links indicate this is the manual
key case.
// EFI_IPSEC_TRAFFIC_DIR
EfiIPsecInBound,
EfiIPsecOutBound
} EFI_IPSEC_TRAFFIC_DIR;
TheEFI_IPSEC_TRAFFIC_DIR represents the directionality in an SPD entry. The EﬁIPsecInBound refers to trafﬁc
entering an IPsec implementation via the unprotected interface or emitted by the implementation on the unprotected
side of the boundary and directed towards the protected interface. The EﬁIPsecOutBound refers to trafﬁc entering the
implementation via the protected interface, or emitted by the implementation on the protected side of the boundary
and directed toward the unprotected interface.
// EFI_IPSEC_ACTION
EfiIPsecActionDiscard,
EfiIPsecActionBypass,
EfiIPsecActionProtect
} EFI_IPSEC_ACTION;
For any inbound or outbound datagram, EFI_IPSEC_ACTION represents three possible processing choices:
EﬁIPsecActionDiscard Refers to trafﬁc that is not allowed to traverse the IPsec boundary (in the direction speciﬁed
byEFI_IPSEC_TRAFFIC_DIR ;
EﬁIPsecActionByPass Refers to trafﬁc that is allowed to cross the IPsec boundary without protection.
EﬁIPsecActionProtect Refers to trafﬁc that is afforded IPsec protection, and for such trafﬁc the SPD must specify
the security protocols to be employed, their mode, security service options, and the cryptographic algorithms to
be used.
// EFI_IPSEC_PROCESS_POLICY
typedef struct _EFI_IPSEC_PROCESS_POLICY {
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BOOLEAN ExtSeqNum;
BOOLEAN SeqOverflow;
BOOLEAN FragCheck;
EFI_IPSEC_SA_LIFETIME SaLifetime;
EFI_IPSEC_MODE Mode;
EFI_IPSEC_TUNNEL_OPTION *TunnelOption;
EFI_IPSEC_PROTOCOL_TYPE Proto;
UINT8 AuthAlgoId;
UINT8 EncAlgoId;
} EFI_IPSEC_PROCESS_POLICY;
If required action of an SPD entry is EﬁIPsecActionProtect, theEFI_IPSEC_PROCESS_POLICY structure describes
a policy list for trafﬁc processing.
ExtSeqNum Extended Sequence Number. Is this SA using extended sequence numbers. 64 bit counter is used if
TRUE .
SeqOverﬂow A ﬂag indicating whether overﬂow of the sequence number counter should generate an auditable event
and prevent transmission of additional packets on the SA, or whether rollover is permitted.
FragCheck Is this SA using stateful fragment checking. TRUE represents stateful fragment checking.
SaLifetime A time interval after which a SA must be replaced with a new SA (and new SPI) or terminated. The type
EFI_IPSEC_SA_LIFETIME is deﬁned in below.
Mode IPsec mode: tunnel or transport
TunnelOption Tunnel Option. TunnelOption is ignored if Mode is EﬁIPsecTransport . The type
EFI_IPSEC_TUNNEL_OPTION is deﬁned in below
Proto IPsec protocol: AH or ESP
AuthAlgoId Cryptographic algorithm type used for authentication
EncAlgoId Cryptographic algorithm type used for encryption. EncAlgo isNULL when IPsec protocol is AH. For
ESP protocol, EncAlgo can also be used to describe the algorithm if a combined mode algorithm is used.
// EFI_IPSEC_SA_LIFETIME
typedef struct _EFI_IPSEC_SA_LIFETIME {
UINT64 ByteCount;
UINT64 SoftLifetime;
UINT64 HardLifetime
} EFI_IPSEC_SA_LIFETIME;
EFI_IPSEC_SA_LIFETIME deﬁnes the lifetime of an SA, which represents when a SA must be replaced or terminated.
A value of all 0 for each ﬁeld removes the limitation of a SA lifetime.
ByteCount The number of bytes to which the IPsec cryptographic algorithm can be applied. For ESP, this is the
encryption algorithm and for AH, this is the authentication algorithm. The ByteCount includes pad bytes for
cryptographic operations.
SoftLifetime A time interval in second that warns the implementation to initiate action such as setting up a replace-
ment SA.
HardLifetime A time interval in second when the current SA ends and is destroyed.
// EFI_IPSEC_MODE
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EfiIPsecTransport,
EfiIPsecTunnel
} EFI_IPSEC_MODE;
There are two modes of IPsec operation: transport mode and tunnel mode. In EﬁIPsecTransport mode, AH and ESP
provide protection primarily for next layer protocols; In EﬁIPsecTunnel mode, AH and ESP are applied to tunneled IP
packets.
EfiIPsecTunnelClearDf,
EfiIPsecTunnelSetDf,
EfiIPsecTunnelCopyDf
} EFI_IPSEC_TUNNEL_DF_OPTION;
The option of copying the DF bit from an outbound package to the tunnel mode header that it emits, when trafﬁc is
carried via a tunnel mode SA. This applies to SAs where both inner and outer headers are IPv4. The value can be:
EﬁIPsecTunnelClearDf: Clear DF bit from inner header
EﬁIPsecTunnelSetDf: Set DF bit from inner header
EﬁIPsecTunnelCopyDf: Copy DF bit from inner header
// EFI_IPSEC_TUNNEL_OPTION
typedef struct _EFI_IPSEC_TUNNEL_OPTION {
EFI_IP_ADDRESS LocalTunnelAddress;
EFI_IP_ADDRESS RemoteTunnelAddress;
EFI_IPSEC_TUNNEL_DF_OPTION DF;
} EFI_IPSEC_TUNNEL_OPTION;
LocalTunnelAddress Local tunnel address when IPsec mode is EﬁIPsecTunnel
RemoteTunnelAddress Remote tunnel address when IPsec mode is EﬁIPsecTunnel
DFThe option of copying the DF bit from an outbound package to the tunnel mode header that it emits, when trafﬁc
is carried via a tunnel mode SA.
// EFI_IPSEC_PROTOCOL_TYPE

EfiIPsecAH,
EfiIPsecESP
} EFI_IPSEC_PROTOCOL_TYPE;
IPsec protocols deﬁnition. EﬁIPsecAH is the IP Authentication Header protocol which is speciﬁed in RFC 4302.
EﬁIPsecESP is the IP Encapsulating Security Payload which is speciﬁed in RFC 4303.
// EFI_IPSEC_SA_ID
typedef struct _EFI_IPSEC_SA_ID {
UINT32 Spi;
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EFI_IP_ADDRESS DestAddress;
} EFI_IPSEC_SA_ID;
A triplet to identify an SA, consisting of the following members:
Spi Security Parameter Index (aka SPI). An arbitrary 32-bit value that is used by a receiver to identity the SA to which
an incoming package should be bound.
DestAddress Destination IP address.
// EFI_IPSEC_SA_DATA
typedef struct _EFI_IPSEC_SA_DATA {
UINT64 SNCount;
UINT8 AntiReplayWindows;
EFI_IPSEC_ALGO_INFO AlgoInfo;
UINT32 PathMTU;
EFI_IPSEC_SPD_SELECTOR *SpdSelector;
BOOLEAN ManualSet
} EFI_IPSEC_SA_DATA;
The data items deﬁned in one SAD entry:
SNCount Sequence Number Counter. A 64-bit counter used to generate the sequence number ﬁeld in AH or ESP
headers.
ReplayWindows Anti-Replay Window. A 64-bit counter and a bit-map used to determine whether an inbound AH or
ESP packet is a replay.
AlgoInfo AH/ESP cryptographic algorithm, key and parameters.
SaLifeTime Lifetime of this SA.
PathMTU Any observed path MTU and aging variables. The Path MTU processing is deﬁned in section 8 of RFC
4301.
SpdSelector Link to one SPD entry.
ManualSet Indication of whether it’s manually set or negotiated automatically. If ManualSet isFALSE, the corre-
sponding SA entry is inserted through IKE protocol negotiation.
// EFI_IPSEC_SA_DATA2
typedef struct _EFI_IPSEC_SA_DATA2 {
BOOLEAN ManualSet;
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EFI_IP_ADDRESS TunnelSourceAddress;
EFI_IP_ADDRESS TunnelDestinationAddress
} EFI_IPSEC_SA_DATA2;
headers.
4301.
ManualSet Indication of whether it’s manually set or negotiated automatically. If ManualSet is FALSE , the corre-
sponding SA entry is inserted through IKE protocol negotiation
TunnelSourceAddress The tunnel header IP source address.
TunnelDestinationAddress The tunnel header IP destination address.
// EFI_IPSEC_ALGO_INFO
EFI_IPSEC_AH_ALGO_INFO AhAlgoInfo;
EFI_IPSEC_ESP_ALGO_INFO EspAlgoInfo;
} EFI_IPSEC_ALGO_INFO;
// EFI_IPSEC_AH_ALGO_INFO
typedef struct _EFI_IPSEC_AH_ALGO_INFO {
UINTN KeyLength;
VOID *Key;
} EFI_IPSEC_AH_ALGO_INFO;
The security algorithm selection for IPsec AH authentication. The required authentication algorithm is speciﬁed in
RFC 4305.
// EFI_IPSEC_ESP_ALGO_INFO
typedef struct _EFI_IPSEC_ESP_ALGO_INFO {
UINTN EncKeyLength;
VOID *EncKey;
UINTN AuthKeyLength;
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VOID *AuthKey;
} EFI_IPSEC_ESP_ALGO_INFO;
The security algorithm selection for IPsec ESP encryption and authentication. The required authentication algorithm
is speciﬁed in RFC 4305. EncAlgoId ﬁelds can also specify an ESP combined mode algorithm (e.g. AES with CCM
mode, speciﬁed in RFC 4309), which provides both conﬁdentiality and authentication services.
// EFI_IPSEC_PAD_ID
typedef struct _EFI_IPSEC_PAD_ID {
BOOLEAN PeerIdValid;
union {
EFI_IP_ADDRESS_INFO IpAddress;
UINT8 PeerId [MAX_PEERID_LEN];
} Id;
} EFI_IPSEC_PAD_ID;
The entry selector for IPsec PAD that represents how to authenticate each peer. EFI_IPSEC_PAD_ID speciﬁes the
identiﬁer for PAD entry, which is also used for SPD lookup.
IpAddress Pointer to the IPv4 or IPv6 address range.
PeerId Pointer to a null-terminated ASCII string representing the symbolic names. A PeerId can be a DNS name,
Distinguished Name, RFC 822 email address or Key ID (speciﬁed in section 4.4.3.1 of RFC 4301)
// EFI_IPSEC_PAD_DATA
typedef struct _EFI_IPSEC_PAD_DATA {
EFI_IPSEC_AUTH_PROTOCOL_TYPE AuthProtocol;
EFI_IPSEC_AUTH_METHOD AuthMethod;
BOOLEAN IkeIdFlag;
UINTN AuthDataSize;
VOID *AuthData;
UINTN RevocationDataSize;
VOID *RevocationData;
} EFI_IPSEC_PAD_DATA;
The data items deﬁned in one PAD entry:
AuthProtocol Authentication Protocol for IPsec security association management
AuthMethod Authentication method used.
IkeIdFlag The IKE ID payload will be used as a symbolic name for SPD lookup if IkeIdFlag isTRUE . Otherwise,
the remote IP address provided in trafﬁc selector payloads will be used.
AuthDataSize The size of Authentication data buffer, in bytes.
AuthData Buffer for Authentication data, (e.g., the pre-shared secret or the trust anchor relative to which the peer’s
certiﬁcate will be validated).
RevocationDataSize The size of RevocationData, in bytes.
RevocationData Pointer to CRL or OCSP data, if certiﬁcates are used for authentication method.
// EFI_IPSEC_AUTH_PROTOCOL
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EfiIPsecAuthProtocolIKEv1,
EfiIPsecAuthProtocolIKEv2,
EfiIPsecAuthProtocolMaximum
} EFI_IPSEC_AUTH_PROTOCOL_TYPE;
EFI_IPSEC_AUTH_PROTOCOL_TYPE deﬁnes the possible authentication protocol for IPsec security association
management.
// EFI_IPSEC_AUTH_METHOD
EfiIPsecAuthMethodPreSharedSecret,
EfiIPsecAuthMethodCertificates,
EfiIPsecAuthMethodMaximum
} EFI_IPSEC_AUTH_METHOD;
EﬁIPsecAuthMethodPreSharedScret Using Pre-shared Keys for manual security associations.
EﬁIPsecAuthMethodCertiﬁcates IKE employs X.509 certiﬁcates for SA establishment.
EFI_SUCCESS The speciﬁed conﬁguration entry data is set successfully.
EFI_UNSUPPORTED The speciﬁed DataType is not supported.
EFI_OUT_OF_RESOURCES The required system resource could not be allocated.
28.8.5 EFI_IPSEC_CONFIG_PROTOCOL.GetData()
Summary
Return the conﬁguration value for the EFI IPsec driver.
Prototype
typedef
(EFIAPI *EFI_IPSEC_CONFIG_GET_DATA) (
IN EFI_IPSEC_CONFIG_SELECTOR *Selector,
);
DataType The type of data to retrieve. Type
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EFI_IPSEC_CONFIG_DATA_TYPE is deﬁned i
EFI_IPSEC_CONFIG_PROTOCOL.SetData() .
Selector Pointer to an entry selector which is an identiﬁer of the IPsec conﬁguration data entry. Type
EFI_IPSEC_CONFIG_SELECTOR is deﬁned in the
EFI_IPSEC_CONFIG_PROTOCOL.SetData() function description.
DataSize On output the size of data returned in Data .
Data The buffer to return the contents of the IPsec conﬁguration data. The type of the data buffer is associated with
theDataType .

Summary
Prototype
typedef
);
This function lookup the data entry from IPsec database or IKEv2 conﬁguration information. The expected data type
and unique identiﬁcation are described in DataType and Selector parameters.
•Selector isNULL .
EFI_NOT_FOUND The conﬁguration data speciﬁed by Selector is not found.
28.8.6 EFI_IPSEC_CONFIG_PROTOCOL.GetNextSelector()
Summary
Enumerates the current selector for IPsec conﬁguration data entry.
Prototype
typedef
(EFIAPI *EFI_IPSEC_CONFIG_GET_NEXT_SELECTOR) (
IN OUT UINTN *SelectorSize,
IN OUT EFI_IPSEC_CONFIG_SELECTOR *Selector,
);
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DataType The type of IPsec conﬁguration data to retrieve. Type EFI_IPSEC_CONFIG_DATA_TYPE is deﬁned in
SelectorSize The size of the Selector buffer.
Selector On input, supplies the pointer to last Selector that was returned by GetNextSelector (). On output, returns
one copy of the current entry Selector of a given DataType . Type EFI_IPSEC_CONFIG_SELECTOR is deﬁned
in the EFI_IPSEC_CONFIG_PROTOCOL.SetData() function description.
This function is called multiple times to retrieve the entry Selector in IPsec conﬁguration database. On each call
toGetNextSelector(), the next entry Selector are retrieved into the output interface. If the entire IPsec conﬁguration
database has been iterated, the error EFI_NOT_FOUND is returned. If the Selector buffer is too small for the next
Selector copy, an EFI_BUFFER_TOO_SMALL error is returned, and SelectorSize is updated to reﬂect the size of
buffer needed.
On the initial call to GetNextSelector() to start the IPsec conﬁguration database search, a pointer to the buffer with
all zero value is passed in Selector . Calls to SetData() between calls to GetNextSelector may produce unpredictable
results.
•SelectorSize isNULL .
EFI_NOT_FOUND The next conﬁguration data entry was not found.
EFI_BUFFER_TOO_SMALL TheSelectorSize is too small for the result. This parameter has been updated
with the size needed to complete the search request.
28.8.7 EFI_IPSEC_CONFIG_PROTOCOL.RegisterDataNotify ()
Summary
Register an event that is to be signaled whenever a conﬁguration process on the speciﬁed IPsec conﬁguration informa-
tion is done.
Prototype
typedef
(EFIAPI *EFI_IPSEC_CONFIG_REGISTER_NOTIFY) (
);
DataType The type of data to be registered the event for. Type EFI_IPSEC_CONFIG_DATA_TYPE is deﬁned in
28.8. IPsec 1185Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Event The event to be registered.
This function registers an event that is to be signaled whenever a conﬁguration process on the speciﬁed IPsec conﬁgu-
ration data is done (e.g. IPsec security policy database conﬁguration is ready). An event can be registered for different
DataType simultaneously and the caller is responsible for determining which type of conﬁguration data causes the
signaling of the event in such case.
EFI_SUCCESS The event is registered successfully.
EFI_UNSUPPORTED The notify registration unsupported or the speciﬁed DataType is not sup-
ported.
28.8.8 EFI_IPSEC_CONFIG_PROTOCOL.UnregisterDataNotify ()
Summary
Remove the speciﬁed event that is previously registered on the speciﬁed IPsec conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_IPSEC_CONFIG_UNREGISTER_NOTIFY) (
);
DataType The conﬁguration data type to remove the registered event for. Type EFI_IPSEC_CONFIG_DATA_TYPE
is deﬁned in EFI_IPSEC_CONFIG_PROTOCOL.SetData() function description.
Event The event to be unregistered.
EFI_SUCCESS The event is removed successfully.
EFI_NOT_FOUND TheEvent speciﬁed by DataType could not be found in the database.
ported.
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28.8.9 EFI IPsec Protocol
This section provides a detailed description of the EFI_IPSEC_PROTOCOL . This protocol handles IPsec-protected
trafﬁc.*
28.8.10 EFI_IPSEC_PROTOCOL
Summary
TheEFI_IPSEC_PROTOCOL is used to abstract the ability to deal with the individual packets sent and received by
the host and provide packet-level security for IP datagram.
GUID
#define EFI_IPSEC_PROTOCOL_GUID \
{0xdfb386f7,0xe100,0x43ad,\
{0x9c,0x9a,0xed,0x90,0xd0,0x8a,0x5e,0x12 }}
typedef struct _EFI_IPSEC_PROTOCOL {
EFI_IPSEC_PROCESS Process;
EFI_EVENT DisabledEvent;
BOOLEAN DisabledFlag;
} EFI_IPSEC_PROTOCOL;
Process Handle the IPsec message.
DisabledEvent Event signaled when the interface is disabled.
DisabledFlag State of the interface.
The EFI_IPSEC_PROTOCOL provides the ability for securing IP communications by authenticating and/or encrypt-
ing each IP packet in a data stream.
EFI_IPSEC_PROTOCOL can be consumed by both the IPv4 and IPv6 stack. A user can employ this protocol for
IPsec package handling in both IPv4 and IPv6 environment.
28.8.11 EFI_IPSEC_PROTOCOL.Process()
Summary
Handles IPsec packet processing for inbound and outbound IP packets.
Prototype
typedef
(EFIAPI *EFI_IPSEC_PROCESS) (
IN EFI_IPSEC_PROTOCOL *This,
IN EFI_HANDLE NicHandle,
IN UINT8 IpVer,
IN OUT VOID *IpHead,
IN UINT8 *LastHead,
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IN VOID *OptionsBuffer,
IN UINT32 OptionsLength,
IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable,
IN EFI_IPSEC_TRAFFIC_DIR TrafficDirection,
OUT EFI_EVENT *RecycleSignal
)
// EFI_IPSEC_FRAGMENT_DATA
typedef struct _EFI_IPSEC_FRAGMENT_DATA {
} EFI_IPSEC_FRAGMENT_DATA;
EFI_IPSEC_FRAGMENT_DATA deﬁnes the instances of packet fragments.
This Pointer to the EFI_IPSEC_PROTOCOL instance.
NicHandle Instance of the network interface.
IpVer IPV4 or IPV6.
IpHead Pointer to the IP Header.
LastHead The protocol of the next layer to be processed by IPsec.
OptionsBuffer Pointer to the options buffer.
OptionsLength Length of the options buffer.
FragmentTable Pointer to a list of fragments.
TrafﬁcDirection Trafﬁc direction.
RecycleSignal Event for recycling of resources.
The EFI_IPSEC_PROCESS process routine handles each inbound or outbound packet. The behavior is that it can
perform one of the following actions: bypass the packet, discard the packet, or protect the packet.
EFI_SUCCESS The packet was bypassed and all buffers remain the same.
EFI_SUCCESS The packet was protected.
EFI_ACCESS_DENIED The packet was discarded.
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28.8.12 EFI IPsec2 Protocol
This section provides a detailed description of the EFI_IPSEC2_PROTOCOL . This protocol handles IPsec-protected
trafﬁc.
28.8.13 EFI_IPSEC2_PROTOCOL
Summary
TheEFI_IPSEC2_PROTOCOL is used to abstract the ability to deal with the individual packets sent and received by
the host and provide packet-level security for IP datagram..
GUID
#define EFI_IPSEC2_PROTOCOL_GUID \
{0xa3979e64, 0xace8, 0x4ddc, \
{0xbc, 0x07, 0x4d, 0x66, 0xb8, 0xfd, 0x09, 0x77}};
typedef struct _EFI_IPSEC2_PROTOCOL {
EFI_IPSEC_PROCESSEXT ProcessExt;
} EFI_IPSEC2_PROTOCOL;

trafﬁc.
Summary
GUID
ProcessExt Handle the IPsec message with the extension header processing support.
TheEFI_IPSEC2_PROTOCOL provides the ability for securing IP communications by authenticating and/or encrypt-
EFI_IPSEC2_PROTOCOL can be consumed by both the IPv4 and IPv6 stack. A user can employ this protocol for
28.8.14 EFI_IPSEC2_PROTOCOL.ProcessExt()
Summary
Handles IPsec processing for both inbound and outbound IP packets. Compare with Process() in
EFI_IPSEC_PROTOCOL, this interface has the capability to process Option(Extension Header).
Prototype
Typedef
(EFIAPI *EFI_IPSEC_PROCESSEXT) (
IN EFI_IPSEC2_PROTOCOL *This,
28.8. IPsec 1189Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN OUT UINT8 *LastHead,
IN OUT VOID **OptionsBuffer,
IN OUT UINT32 *OptionsLength,
IN OUT UINT32 *FragmentCount,
)
This Pointer to the EFI_IPSEC2_PROTOCOL instance.
IpVer IP version.IPV4 or IPV6.
IpHead Pointer to the IP Header it is either the EFI_IP4_HEADER orEFI_IP6_HEADER .On input, it contains the
IP header. On output,
1. in tunnel mode and the trafﬁc direction is inbound, the buffer will be reset to zero by IPsec;
2. in tunnel mode and the trafﬁc direction is outbound, the buffer will reset to be the tunnel IP header.
3. in transport mode, the related ﬁelders (like payload length, Next header) in IP header will be modiﬁed
according to the condition.
LastHead For IP4, it is the next protocol in IP header. For IP6 it is the Next Header of the last extension header.
OptionsBuffer On input, it contains the options (extensions header) to be processed by IPsec. On output,
1. in tunnel mode and the trafﬁc direction is outbound, it will be set to NULL, and that means this contents
was wrapped after inner header and should not be concatenated after tunnel header again;
2. in transport mode and the trafﬁc direction is inbound, if there are IP options (extension headers) protected
by IPsec, IPsec will concatenate the those options after the input options (extension headers);
3. on other situations, the output of contents of OptionsBuffer might be same with input’s. The caller should
take the responsibility to free the buffer both on input and on output.
OptionsLength On input, the input length of the options buffer. On output, the output length of the options buffer.
FragmentTable Pointer to a list of fragments. On input, these fragments contain the IP payload. On output,
1. in tunnel mode and the trafﬁc direction is inbound, the fragments contain the whole IP payload which is
from the IP inner header to the last byte of the packet;*
2. in tunnel mode and the trafﬁc direction is the outbound, the fragments contains the whole encapsulated
payload which encapsulates the whole IP payload between the encapsulated header and encapsulated trailer
ﬁelds.*
3. in transport mode and the trafﬁc direction is inbound, the fragments contains the IP payload which is from
the next layer protocol to the last byte of the packet;*
4. in transport mode and the trafﬁc direction is outbound, the fragments contains the whole encapsulated
payload which encapsulates the next layer protocol information between the encapsulated header and
encapsulated trailer ﬁelds.*
28.8. IPsec 1190Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheEFI_IPSEC_PROCESSEXT process routine handles each inbound or outbound packet with the support of options
(extension headers) processing. The behavior is that it can perform one of the following actions: bypass the packet,
discard the packet, or protect the packet.
EFI_SUCCESS The packet was processed by IPsec successfully.
EFI_NOT_READY The IKE negotiation is invoked and the packet was discarded.
One of more of following are TRUE
IfOptionsBuffer isNULL;
IfOptionsLength isNULL;
IfFragmentTable isNULL;
IfFragmentCount isNULL;
28.9 Network Protocol - EFI FTP Protocol
This section deﬁnes the EFI FTPv4 (File Transfer Protocol version 4) Protocol that interfaces over EFI FTPv4 Protocol
28.9.1 EFI_FTP4_SERVICE_BINDING_PROTOCOL Summary
Summary
TheEFI_FTP4_SERVICE_BINDING_PROTOCOL is used to locate communication devices that are supported by an
EFI FTPv4 Protocol driver and to create and destroy instances of the EFI FTPv4 Protocol child protocol driver that
can use the underlying communication device.
GUID
#define EFI_FTP4_SERVICE_BINDING_PROTOCOL_GUID \
{0xfaaecb1, 0x226e, 0x4782,\
{0xaa, 0xce, 0x7d, 0xb9, 0xbc, 0xbf, 0x4d, 0xaf}}
A network application or driver that requires FTPv4 I/O services can use one of the protocol handler services, such as
BS->LocateHandleBuffer(), to search for devices that publish an EFI FTPv4 Service Binding Protocol GUID. Each
device with a published EFI FTPv4 Service Binding Protocol GUID supports the EFI FTPv4 Protocol service and may
be available for use.
After a successful call to the EFI_FTP4_SERVICE_BINDING_PROTOCOL.CreateChild() function, the newly created
child EFI FTPv4 Protocol driver instance is in an unconﬁgured state; it is not ready to transfer data.
EFI_FTP4_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_FTP4_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
Each instance of the EFI FTPv4 Protocol driver can support one ﬁle transfer operation at a time. To download two
ﬁles at the same time, two instances of the EFI FTPv4 Protocol driver will need to be created.
28.9. Network Protocol - EFI FTP Protocol 1191Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NOTE :Byte Order: f not speciﬁcally speciﬁed, the IP addresses used in the EFI_FTP4_PROTOCOL are in network
byte order and the ports are in host byte order .
28.9.2 EFI_FTP4_PROTOCOL
Summary
The EFI FTPv4 Protocol provides basic services for client-side FTP (File Transfer Protocol) operations.
GUID
#define EFI_FTP4_PROTOCOL_GUID \
{0xeb338826, 0x681b, 0x4295,\
{0xb3, 0x56, 0x2b, 0x36, 0x4c, 0x75, 0x7b, 0x09}}
typedef struct _EFI_FTP4_PROTOCOL {
EFI_FTP4_GET_MODE_DATA GetModeData;
EFI_FTP4_CONNECT Connect;
EFI_FTP4_CLOSE Close;
EFI_FTP4_CONFIGURE Configure;
EFI_FTP4_READ_FILE ReadFile;
EFI_FTP4_WRITE_FILE WriteFile;
EFI_FTP4_READ_DIRECTORY ReadDirectory;
EFI_FTP4_POLL Poll;
} EFI_FTP4_PROTOCOL;
GetModeData Reads the current operational settings. See the GetModeData() function description.
Connect Establish control connection with the FTP server by using the TELNET protocol according to FTP protocol
deﬁnition. See the Connect() function description
Close Gracefully disconnecting a FTP control connection This function is a nonblocking operation. See the Close()
Conﬁgure Sets and clears operational parameters for an FTP child driver. See the Conﬁgure() function description.
ReadFile Downloads a ﬁle from an FTPv4 server. See the ReadFile() function description.
WriteFile Uploads a ﬁle to an FTPv4 server. This function may be unsupported in some EFI implementations. See
theWriteFile() function description.
ReadDirectory Download a related ﬁle “directory” from an FTPv4 server. This function may be unsupported in some
implementations. See the ReadDirectory() function description.
28.9. Network Protocol - EFI FTP Protocol 1192Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.9.3 EFI_FTP4_PROTOCOL.GetModeData()
Summary
Gets the current operational settings.
Prototype
typedef
(EFIAPI *EFI_FTP4_GET_MODE_DATA)(
IN EFI_FTP4_PROTOCOL *This,
OUT EFI_FTP4_CONFIG_DATA *ModeData
);
This Pointer to the EFI_FTP4_PROTOCOL instance.
ModeData Pointer to storage for the EFI FTPv4 Protocol driver mode data. Type EFI_FTP4_CONFIG_DATA
is deﬁned in “Related Deﬁnitions” below. The string buffers for Username and Password in
EFI_FTP4_CONFIG_DATA are allocated by the function, and the caller should take the responsibility to free
the buffer later.
The GetModeData() function reads the current operational settings of this EFI FTPv4 Protocol driver instance.
EFI_FTP4_CONFIG_DATA is deﬁned in the EFI_FTP4_PROTOCOL.Conﬁgure .

Summary
Prototype
typedef
);
EFI_SUCCESS This function is called successfully.
•ModeData isNULL .
EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started.
28.9.4 EFI_FTP4_PROTOCOL.Connect()
Summary
Initiate a FTP connection request to establish a control connection with FTP server
Prototype
typedef
(EFIAPI *EFI_FTP4_CONNECT) (
IN EFI_FTP4_CONNECTION_TOKEN *Token
);
28.9. Network Protocol - EFI FTP Protocol 1193Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Token Pointer to the token used to establish control connection.
// EFI_FTP4_CONNECTION_TOKEN
} EFI_FTP4_CONNECTION_TOKEN;
Event The Event to signal after the connection is established and Status ﬁeld is updated by the EFI FTP v4 Protocol
driver. The type of Event must be EVENT_NOTIFY_SIGNAL, and its Task Priority Level (TPL) must be lower
than or equal to TPL_CALLBACK . If it is set to NULL, this function will not return until the function completes
Status The variable to receive the result of the completed operation.
EFI_SUCCESS The FTP connection is established successfully.
EFI_ACCESS_DENIED The FTP server denied the access the user’s request to access it.
EFI_CONNECTION_RESET The connect fails because the connection is reset either by instance itself or
EFI_TIMEOUT The connection establishment timer expired and no more speciﬁc informa-
EFI_NETWORK_UNREACHABLE The active open fails because an ICMP network unreachable error is re-
ceived.
EFI_HOST_UNREACHABLE The active open fails because an ICMP host unreachable error is received.
EFI_PROTOCOL_UNREACHABLE The active open fails because an ICMP protocol unreachable error is re-
ceived.
EFI_PORT_UNREACHABLE The connection establishment timer times out and an ICMP port unreach-
able error is received.
EFI_ICMP_ERROR The connection establishment timer timeout and some other ICMP error is
received.
The Connect() function will initiate a connection request to the remote FTP server with the corresponding connection
token. If this function returns EFI_SUCCESS, the connection sequence is initiated successfully. If the connection
succeeds or failed due to any error, the Token->Event will be signaled and Token->Status will be updated accordingly.
EFI_SUCCESS The connection sequence is successfully initiated.
28.9. Network Protocol - EFI FTP Protocol 1194Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.57 – continued from previous page
2This is NULL.
2Token is NULL.
2Token->Event is NULL.
28.9.5 EFI_FTP4_PROTOCOL.Close()
Summary
Disconnecting a FTP connection gracefully.
Prototype
typedef
(EFIAPI *EFI_FTP4_CLOSE)(
);
Token Pointer to the token used to close control connection.
TheClose() function will initiate a close request to the remote FTP server with the corresponding connection token. If
this function returns EFI_SUCCESS, the control connection with the remote FTP server is closed.
EFI_SUCCESS The close request is successfully initiated.
• ConnectionToken is NULL .
• ConnectionToken->Event is NULL .
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Table 28.58 – continued from previous page
28.9.6 EFI_FTP4_PROTOCOL.Conﬁgure()
Summary
Sets or clears the operational parameters for the FTP child driver.
Prototype
typedef
(EFIAPI *EFI_FTP4_CONFIGURE) (
IN EFI_FTP4_CONFIG_DATA *FtpConfigData OPTIONAL
);
FtpConﬁgData Pointer to conﬁguration data that will be assigned to the FTP child driver instance. If NULL, the FTP
child driver instance is reset to startup defaults and all pending transmit and receive requests are ﬂushed.
// EFI_FTP4_CONFIG_DATA
UINT8 *Username;
UINT8 *Password;
BOOLEAN Active;
BOOLEAN UseDefaultSetting;
EFI_IPv4_ADDRESS StationIp;
EFI_IPv4_ADDRESS GatewayIp;
EFI_IPv4_ADDRESS ServerIp;
UINT16 ServerPort;
UINT16 AltDataPort;
UINT8 RepType;
UINT8 FileStruct;
UINT8 TransMode;
} EFI_FTP4_CONFIG_DATA;
Username Pointer to a ASCII string that contains user name. The caller is responsible for freeing Username after
GetModeData() is called.
Password Pointer to a ASCII string that contains password. The caller is responsible for freeing Password after
Active Set it to TRUE to initiate an active data connection. Set it to FALSE to initiate a passive data connection.
UseDefaultSetting Boolean value indicating if default network setting used.
StationIp IP address of station if UseDefaultSetting isFALSE .
SubnetMask Subnet mask of station if UseDefaultSetting isFALSE .
GatewayIp IP address of gateway if UseDefaultSetting isFALSE .
28.9. Network Protocol - EFI FTP Protocol 1196Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ServerIp IP address of FTPv4 server.
ServerPort FTPv4 server port number of control connection, and the default value is 21 as convention.
ALtDataPort FTPv4 server port number of data connection. If it is zero, use ( ServerPort - 1) by convention.
RepType A byte indicate the representation type. The right 4 bit is used for ﬁrst parameter, the left 4 bit is use for
second parameter
• For the ﬁrst parameter, 0x0 = image, 0x1 = EBCDIC, 0x2 = ASCII, 0x3 = local
• For the second parameter, 0x0 = Non-print, 0x1 = Telnet format effectors, 0x2 = Carriage Control
• If it is a local type, the second parameter is the local byte byte size.
• If it is a image type, the second parameter is undeﬁned.
FileStruct Deﬁnes the ﬁle structure in FTP used. 0x00 = ﬁle, 0x01 = record, 0x02 = page
TransMode Deﬁnes the transfer mode used in FTP. 0x00 = stream, 0x01 = Block, 0x02 = Compressed
TheConﬁgure() function will conﬁgure the connected FTP session with the conﬁguration setting speciﬁed in FtpCon-
ﬁgData . The conﬁguration data can be reset by calling Conﬁgure() with FtpConﬁgData set to NULL .
EFI_SUCCESS The FTPv4 driver was conﬁgured successfully.
•FtpConﬁgData.RepType is invalid.
•FtpConﬁgData.FileStruct in invalid.
•FtpConﬁgData.TransMode is invalid.
• IP address in FtpConﬁgData is invalid.
has not ﬁnished yet.
EFI_UNSUPPORTED One or more of the conﬁguration parameters are not supported by this im-
plementation.
EFI_OUT_OF_RESOURCES The EFI FTPv4 Protocol driver instance data could not be allocated.
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI FTPv4 Protocol
driver instance is not conﬁgured.
28.9.7 EFI_FTP4_PROTOCOL.ReadFile()
Summary
Downloads a ﬁle from an FTPv4 server.
Prototype
typedef
(EFIAPI *EFI_FTP4_READ_FILE)(
28.9. Network Protocol - EFI FTP Protocol 1197Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_FTP4_COMMAND_TOKEN *Token
);
Token Pointer to the token structure to provide the parameters that are used in this operation. Type
EFI_FTP4_COMMAND_TOKEN is deﬁned in “Related Deﬁnitions” below.

Summary
Prototype
typedef
);
// EFI_FTP4_COMMAND_TOKEN
UINT8 *Pathname;
UINT64 DataBufferSize;
VOID *DataBuffer;
EFI_FTP4_DATA_CALLBACK DataCallback;
VOID *Context;
} EFI_FTP4_COMMAND_TOKEN;
Event TheEvent to signal after request is ﬁnished and Status ﬁeld is updated by the EFI FTP v4 Protocol driver. The
TPL_CALLBACK . If it is set to NULL, related function must wait until the function completes
Pathname Pointer to a null-terminated ASCII name string.
DataBuffersize The size of data buffer in bytes
DataBuffer Pointer to the data buffer. Data downloaded from FTP server through connection is downloaded here.
DataCallback Pointer to a callback function. If it is receiving function that leads to inbound data, the callback
function is called when databuffer is full. Then, old data in the data buffer should be ﬂushed and new data is
stored from the beginning of data buffer. If it is a transmit function that lead to outbound data and DataBufferSize
ofData inDataBuffer has been transmitted, this callback function is called to supply additional data to be
transmitted. The size of additional data to be transmitted is indicated in DataBufferSize, again. If there is no
data remained, DataBufferSize should be set to 0
Context Pointer to the parameter for DataCallback .
EFI_SUCCESS — The FTP command is completed successfully.
EFI_ACCESS_DENIED — The FTP server denied the access to the requested ﬁle.
EFI_CONNECTION_RESET — The connect fails because the connection is reset either by instance itself or
EFI_TIMEOUT — The connection establishment timer expired and no more speciﬁc information is available.
28.9. Network Protocol - EFI FTP Protocol 1198Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_NETWORK_UNREACHABLE — The active open fails because an ICMP network unreachable error is
received.
EFI_HOST_UNREACHABLE — The active open fails because an ICMP host unreachable error is received.
EFI_PROTOCOL_UNREACHABLE — The active open fails because an ICMP protocol unreachable error
is received.
EFI_PORT_UNREACHABLE — The connection establishment timer times out and an ICMP port
unreachable error is received.
EFI_ICMP_ERROR — The connection establishment timer timeout and some other ICMP error is received.
EFI_DEVICE_ERROR — An unexpected system or network error occurred.
// EFI_FTP4_DATA_CALLBACK
typedef
(EFIAPI *EFI_FTP4_DATA_CALLBACK)(
IN EFI_FTP4_COMMAND_TOKEN *Token,
);
EFI_FTP4_COMMAND_TOKEN is deﬁned in “Related Deﬁnitions” above.
The ReadFile() function is used to initialize and start an FTPv4 download process and optionally wait for completion.
When the download operation completes, whether successfully or not, the Token.Status ﬁeld is updated by the EFI
FTPv4 Protocol driver and then Token.Event is signaled (if it is not NULL).
Data will be downloaded from the FTPv4 server into Token.DataBuffer. If the ﬁle size is larger than To-
ken.DataBufferSize, Token.DataCallback will be called to allow for processing data and then new data will be placed
at the beginning of Token.DataBuffer.
EFI_SUCCESS The data ﬁle is being downloaded successfully.
28.9. Network Protocol - EFI FTP Protocol 1199Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.60 – continued from previous page
One or more of the parameters is not valid.
• Token is NULL .
• Token. Pathname is NULL .
• Token. DataBuffer is NULL .
• Token. DataBufferSize is 0.
EFI_DEVICE_ERROR An unexpected network error or system error occurred.
28.9.8 EFI_FTP4_PROTOCOL.WriteFile()
Summary
Uploads a ﬁle from an FTPv4 server.
Prototype
typedef
(EFIAPI *EFI_FTP4_WRITE_FILE)(
);
EFI_FTP4_COMMAND_TOKEN is deﬁned in ” EFI_FTP4_READ_FILE ” .
TheWriteFile() function is used to initialize and start an FTPv4 upload process and optionally wait for completion.
When the upload operation completes, whether successfully or not, the Token.Status ﬁeld is updated by the EFI FTPv4
Protocol driver and then Token.Event is signaled (if it is not NULL ).
Data to be uploaded to server is stored into Token.DataBuffer .Token.DataBufferSize is the number bytes to be trans-
ferred. If the ﬁle size is larger than Token.DataBufferSize, Token.DataCallback will be called to allow for processing
data and then new data will be placed at the beginning of Token.DataBuffer .Token.DataBufferSize is updated to re-
ﬂect the actual number of bytes to be transferred. Token.DataBufferSize is set to 0 by the call back to indicate the
completion of data transfer.
EFI_SUCCESS The data ﬁle is being uploaded successfully.
EFI_UNSUPPORTED The operation is not supported by this implementation.
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Table 28.61 – continued from previous page
28.9.9 EFI_FTP4_PROTOCOL.ReadDirectory()
Summary
Download a data ﬁle “directory” from a FTPv4 server. May be unsupported in some EFI implementations.
Prototype
typedef
(EFIAPI *EFI_FTP4_READ_DIRECTORY) (
);
The ReadDirectory() function is used to return a list of ﬁles on the FTPv4 server that logically (or operationally)
related to Token.Pathname, and optionally wait for completion. When the download operation completes, whether
successfully or not, the Token.Status ﬁeld is updated by the EFI FTPv4 Protocol driver and then Token.Event is signaled
(if it is not NULL ).
Data will be downloaded from the FTPv4 server into Token.DataBuffer . If the ﬁle size is larger than To-
at the beginning of Token.DataBuffer .
EFI_SUCCESS The ﬁle list information is being downloaded successfully.
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Table 28.62 – continued from previous page
•Token isNULL.
•Token .DataBuffer isNULL.
•Token .DataBufferSize is 0.
28.9.10 EFI_FTP4_PROTOCOL.Poll()
Summary
Prototype
typedef
(EFIAPI *EFI_FTP4_POLL) (
IN EFI_FTP4_PROTOCOL *This
);

Summary
Prototype
typedef
);
In some systems, the periodic timer event in the managed network driver may not poll the underlying communications
device fast enough to transmit and/or receive all data packets without missing incoming packets or dropping outgoing
packets. Drivers and applications that are experiencing packet loss should try calling the Poll() function more often.
EFI_NOT_STARTED This EFI FTPv4 Protocol instance has not been started.
28.9. Network Protocol - EFI FTP Protocol 1202Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.10 EFI TLS Protocols
28.10.1 EFI TLS Service Binding Protocol
28.10.1.1 EFI_TLS_SERVICE_BINDING_PROTOCOL
Summary
The EFI TLS Service Binding Protocol is used to locate EFI TLS Protocol drivers to create and destroy child of the
driver to communicate with other host using TLS protocol.
GUID
#define EFI_TLS_SERVICE_BINDING_PROTOCOL_GUID \
{ \
0x952cb795, 0xff36, 0x48cf, 0xa2, 0x49, 0x4d, 0xf4, 0x86, 0xd6, 0xab, 0x8d \
}
The TLS consumer need locate EFI_TLS_SERVICE_BINDING_PROTOCOL and call CreateChild() to create
a new child of EFI_TLS_PROTOCOL and EFI_TLS_CONFIGURATION_PROTOCOL instance. Then usE
EFI_TLS_CONFIGURATION_PROTOCOL to set TLS conﬁguration data, and use EFI_TLS_PROTOCOL to start
TLS session. After use, the TLS consumer needs to call DestroyChild() to destroy it.
28.10.2 EFI TLS Protocol
28.10.2.1 EFI_TLS_PROTOCOL
Summary
This protocol provides the ability to manage TLS session.
GUID
#define EFI_TLS_PROTOCOL_GUID \
{ 0xca959f, 0x6cfa, 0x4db1, \
{0x95, 0xbc, 0xe4, 0x6c, 0x47, 0x51, 0x43, 0x90 }}
typedef struct _EFI_TLS_PROTOCOL {
EFI_TLS_SET_SESSION_DATA SetSessionData;
EFI_TLS_GET_SESSION_DATA GetSessionData;
EFI_TLS_BUILD_RESPONSE_PACKET BuildResponsePacket;
EFI_TLS_PROCESS_PACKET ProcessPacket;
} EFI_TLS_PROTOCOL;
SetSessionData Set TLS session data. See the SetSessionData () function description.
GetSessionData Get TLS session data. See the GetSessionData () function description.
BuildResponsePacket Build response packet according to TLS state machine. This function is only valid for alert,
handshake and change_cipher_spec content type. See the BuildResponsePacket () function description.
28.10. EFI TLS Protocols 1203Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ProcessPacket Decrypt or encrypt TLS packet during session. This function is only valid after session connected and
for application_data content type. See the ProcessPacket () function description.
TheEFI_TLS_PROTOCOL is used to create, destroy and manage TLS session. For detail of TLS, please refer to TLS
related RFC.
28.10.3 EFI_TLS_PROTOCOL.SetSessionData ()
Summary
Set TLS session data.
Prototype
typedef
(EFIAPI *EFI_TLS_SET_SESSION_DATA)(
IN EFI_TLS_PROTOCOL *This,
IN EFI_TLS_SESSION_DATA_TYPE DataType,
);
This Pointer to the EFI_TLS_PROTOCOL instance.
DataType TLS session data type. See EFI_TLS_SESSION_DATA_TYPE
Data Pointer to session data.
DataSize Total size of session data.
TheSetSessionData() function set data for a new TLS session. All session data should be set before BuildResponseP-
acket() invoked.
// EFI_TLS_SESSION_DATA_TYPE
EfiTlsVersion,
EfiTlsConnectionEnd,
EfiTlsCipherList,
EfiTlsCompressionMethod,
EfiTlsExtensionData,
EfiTlsVerifyMethod,
EfiTlsSessionID,
EfiTlsSessionState,
EfiTlsClientRandom,
EfiTlsServerRandom,
EfiTlsKeyMaterial,
EfiTlsVerifyHost,
EfiTlsSessionDataTypeMaximum
} EFI_TLS_SESSION_DATA_TYPE;
28.10. EFI TLS Protocols 1204Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EﬁTlsVersion TLS session Version. The corresponding Data is of type EFI_TLS_VERSION .
EﬁTlsConnectionEnd TLS session as client or as server. The corresponding Data is of
EFI_TLS_CONNECTION_END .
EﬁTlsCipherList A priority list of preferred algorithms for the TLS session. The corresponding Data is a list of
EFI_TLS_CIPHER.
EﬁTlsCompressionMethod TLS session compression method. The corresponding Data is of type
EFI_TLS_COMPRESSION .
EﬁTlsExtensionData TLS session extension data. The corresponding Data is a list of type EFI_TLS_EXTENDION .
EﬁTlsVerifyMethod TLS session verify method. The corresponding Data is of type EFI_TLS_VERIFY .
EﬁTlsSessionID TLS session data session ID. For SetSessionData(), it is TLS session ID used for session resumption.
ForGetSessionData(), it is the TLS session ID used for current session. The corresponding Data is of type
EFI_TLS_SESSION_ID .
EﬁTlsSessionState TLS session data session state. The corresponding Data is of type EFI_TLS_SESSION_STATE .
EﬁTlsClientRandom TLS session data client random. The corresponding Data is of type EFI_TLS_RANDOM .
EﬁTlsServerRandom TLS session data server random. The corresponding Data is of type EFI_TLS_RANDOM .
EﬁTlsKeyMaterial TLS session data key material. The corresponding Data is of type EFI_TLS_MASTER_SECRET .
EﬁTlsVerifyHost TLS session hostname for validation which is used to verify whether the name within the
peer certiﬁcate matches a given host name. This parameter is invalid when EﬁTlsVerifyMethod is
EFI_TLS_VERIFY_NONE . The corresponding Data is of type EFI_TLS_VERIFY_HOST .
// EFI_TLS_VERSION
UINT8 Major;
UINT8 Minor;
} EFI_TLS_VERSION;
Note: The TLS version deﬁnition is from latest TLS RFC.
// EFI_TLS_CONNECTION_END
EfiTlsClient,
EfiTlsServer,
} EFI_TLS_CONNECTION_END;
TLS connection end is to deﬁne TLS session as client or as server.
// EFI_TLS_CIPHER
UINT8 Data1;
UINT8 Data2;
} EFI_TLS_CIPHER;
28.10. EFI TLS Protocols 1205Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NOTE: The deﬁnition of EFI_TLS_CIPHER is from RFC 5246 A.4.1.Hello Messages. The value of EFI_TLS_CIPHER
is from TLS Cipher Suite Registry of IANA .
// EFI_TLS_COMPRESSION
typedef UINT8 EFI_TLS_COMPRESSION;
NOTE: The value of EFI_TLS_COMPRESSION deﬁnition is from RFC 3749.
// EFI_TLS_EXTENSION
UINT16 ExtensionType;
UINT8 Data [];
} EFI_TLS_EXTENSION;
NOTE: The deﬁnition of EFI_TLS_EXTENSION is from RFC 5246 A.4.1. Hello Messages.
// EFI_TLS_VERIFY
typedef UINT32 EFI_TLS_VERIFY;
#define EFI_TLS_VERIFY_NONE 0x0
#define EFI_TLS_VERIFY_PEER 0x1
#define EFI_TLS_VERIFY_FAIL_IF_NO_PEER_CERT 0x2
#define EFI_TLS_VERIFY_CLIENT_ONCE 0x4
The consumer needs to use either EFI_TLS_VERIFY_NONE or EFI_TLS_VERIFY_PEER .
EFI_TLS_VERIFY_FAIL_IF_NO_PEER_CERT and EFI_TLS_VERIFY_CLIENT_ONCE can be ORed with
EFI_TLS_VERIFY_PEER .EFI_TLS_VERIFY_FAIL_IF_NO_PEER_CERT is only meaningful in the server mode,
which means the TLS session will fail if the client certiﬁcate is absent. EFI_TLS_VERIFY_CLIENT_ONCE means
the TLS session only veriﬁes the client once, and doesn’t request a certiﬁcate during re-negotiation.
// EFI_TLS_VERIFY_HOST
EFI_TLS_VERIFY_HOST_FLAG Flags;
CHAR8 *HostName;
} EFI_TLS_VERIFY_HOST;
Flags The host name validation ﬂags. The ﬂags arguments can be ORed.
HostName The speciﬁed host name to be veriﬁed.
// EFI_TLS_VERIFY_HOST_FLAG
typedef UINT32 EFI_TLS_VERIFY_HOST_FLAG;
#define EFI_TLS_VERIFY_FLAG_NONE 0x00
#define EFI_TLS_VERIFY_FLAG_ALWAYS_CHECK_SUBJECT 0x01
#define EFI_TLS_VERIFY_FLAG_NO_WILDCARDS 0x02
#define EFI_TLS_VERIFY_FLAG_NO_PARTIAL_WILDCARDS 0x04
#define EFI_TLS_VERIFY_FLAG_MULTI_LABEL_WILDCARDS 0x08
28.10. EFI TLS Protocols 1206Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_TLS_VERIFY_FLAG_SINGLE_LABEL_SUBDOMAINS 0x10
#define EFI_TLS_VERIFY_FLAG_NEVER_CHECK_SUBJECT 0x20

EFI_TLS_VERIFY_FLAG_NONE means no additional ﬂags set for hostname validation. Wildcards are supported
and they match only in the left-most label.
EFI_TLS_VERIFY_FLAG_ALWAYS_CHECK_SUBJECT means to always check the Subject Distinguished
Name (DN) in the peer certiﬁcate even if the certiﬁcate contains Subject Alternative Name (SAN).
EFI_TLS_VERIFY_FLAG_NO_WILDCARDS means to disable the match of all wildcards.
EFI_TLS_VERIFY_FLAG_NO_PARTIAL_WILDCARDS means to disable the “*” as wildcard in labels that have
a preﬁx or sufﬁx (e.g. “www*” or “*www”).
EFI_TLS_VERIFY_FLAG_MULTI_LABEL_WILDCARDS allows the “*” to match more than one labels. Oth-
erwise, only matches a single label.
EFI_TLS_VERIFY_FLAG_SINGLE_LABEL_SUBDOMAINS restricts to only match direct child sub-domains
which start with “.”. For example, a name of “.example.com” would match “www.example.com” with this ﬂag, but
would not match “www.sub.example.com”.
EFI_TLS_VERIFY_FLAG_NEVER_CHECK_SUBJECT means never check the Subject Distinguished Name
(DN) even there is no Subject Alternative Name (SAN) in the certiﬁcate.
If both EFI_TLS_VERIFY_FLAG_ALWAYS_CHECK_SUBJECT andEFI_TLS_VERIFY_FLAG_NEVER_CHECK_SUBJECT
are speciﬁed, EFI_INVALID_PARAMETER will be returned. If EFI_TLS_VERIFY_FLAG_NO_WILDCARDS is set
with EFI_TLS_VERIFY_FLAG_NO_PARTIAL_WILDCARDS orEFI_TLS_VERIFY_FLAG_MULTI_LABEL_WILDCARDS,
EFI_INVALID_PARAMETER will be returned.
// EFI_TLS_RANDOM
UINT32 GmtUnixTime;
UINT8 RandomBytes[28];
} EFI_TLS_RANDOM;
NOTE: The deﬁnition of EFI_TLS_RANDOM is from RFC 5246 A.4.1. Hello Messages .
// EFI_TLS_MASTER_SECRET
UINT8*Data[48];
} EFI_TLS_MASTER_SECRET;
NOTE: The deﬁnition of EFI_TLS_MASTER_SECRETE is from RFC 5246 8.1. Computing the Master Secret .
// EFI_TLS_SESSION_ID
#define MAX_TLS_SESSION_ID_LENGTH 32
UINT8 Data[MAX_TLS_SESSION_ID_LENGTH];
} EFI_TLS_SESSION_ID;
NOTE: The deﬁnition of EFI_TLS_SESSION_ID is from RFC 5246 A.4.1. Hello Messages.
28.10. EFI TLS Protocols 1207Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_TLS_SESSION_STATE
Typedef enum {
EfiTlsSessionNotStarted,
EfiTlsSessionHandShaking,
EfiTlsSessionDataTransferring,
EfiTlsSessionClosing,
EfiTlsSessionError,
EfiTlsSessionStateMaximum
} EFI_TLS_SESSION_STATE;
The deﬁnition of EFI_TLS_SESSION_STATE is below:
When a new child of TLS protocol is created, the initial state of TLS session is EﬁTlsSessionNotStarted .
The consumer can call BuildResponsePacket() with NULL to get ClientHello to start the TLS session. Then the status
isEﬁTlsSessionHandShaking .
During handshake, the consumer need call BuildResponsePacket() with input data from peer, then get response packet
and send to peer. After handshake ﬁnish, the TLS session status becomes EﬁTlsSessionDataTransferring, and consume
can use ProcessPacket() for data transferring.
Finally, if consumer wants to active close TLS session, consumer need call SetSessionData to set TLS session state to
EﬁTlsSessionClosing, and call BuildResponsePacket() with NULL to get CloseNotify alert message, and sent it out.
If any error happen during parsing ApplicationData content type, EFI_ABORT will be returned by ProcessPacket(),
and TLS session state will become EﬁTlsSessionError . Then consumer need call BuildResponsePacket() with NULL
to get alert message and sent it out.
EFI_SUCCESS The TLS session data is set successfully.
If the DataType is one of below:
•EﬁTlsClientRandom
•EﬁTlsServerRandom
•EﬁTlsKeyMaterial
EFI_NOT_READY Current TLS session state is NOT EﬁTlsSessionStateNotStarted .
28.10. EFI TLS Protocols 1208Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.10.4 EFI_TLS_PROTOCOL.GetSessionData ()
Summary
Get TLS session data.
Prototype
typedef
(EFIAPI *EFI_TLS_GET_SESSION_DATA)(
IN OUT VOID *Data, OPTIONAL
);
DataSize Total size of session data. On input, it means the size of Data buffer. On output, it means the size of copied
Data buffer if EFI_SUCCESS, and means the size of desired Data buffer if EFI_BUFFER_TOO_SMALL .
The GetSessionData() function return the TLS session information.
EFI_SUCCESS The TLS session data is got successfully.
• Data is NULL if *DataSize is not zero.
EFI_NOT_FOUND The TLS session data is not found.
EFI_NOT_READY The DataType is not ready in current session state.
EFI_BUFFER_TOO_SMALL The buffer is too small to hold the data.
28.10.5 EFI_TLS_PROTOCOL.BuildResponsePacket ()
Summary
Build response packet according to TLS state machine. This function is only valid for alert, handshake and
change_cipher_spec content type.
Prototype
typedef
(EFIAPI *EFI_TLS_BUILD_RESPONSE_PACKET)(
28.10. EFI TLS Protocols 1209Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN UINTN RequestSize, OPTIONAL
OUT UINT8 *Buffer, OPTIONAL
);
RequestBuffer Pointer to the most recently received TLS packet. NULL means TLS need initiate the TLS session
and response packet need to be ClientHello.
RequestSize Packet size in bytes for the most recently received TLS packet. 0 is only valid when RequestBuffer is
NULL.
TheBuildResponsePacket() function builds TLS response packet in response to the TLS request packet speciﬁed by
RequestBuffer andRequestSize . IfRequestBuffer is NULL and RequestSize is 0, and TLS session status is EﬁTlsSes-
sionNotStarted, the TLS session will be initiated and the response packet needs to be ClientHello. If RequestBuffer
is NULL and RequestSize is 0, and TLS session status is EﬁTlsSessionClosing, the TLS session will be closed and
response packet needs to be CloseNotify. If RequestBuffer is NULL and RequestSize is 0, and TLS session status is
EﬁTlsSessionError, the TLS session has errors and the response packet needs to be Alert message based on error type.
EFI_SUCCESS The required TLS packet is built successfully.
•RequestBuffer isNULL butRequestSize is NOT 0.
•RequestSize is 0 but RequestBuffer isNOT NULL .
•BufferSize isNULL .
•Buffer isNULL .ifBufferSize is not zero.
EFI_NOT_READY Current TLS session state is NOT ready to build ResponsePacket .
EFI_ABORTED Something wrong build response packet.
28.10. EFI TLS Protocols 1210Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.10.6 EFI_TLS_PROTOCOL.ProcessPacket ()
Summary
Decrypt or encrypt TLS packet during session. This function is only valid after session connected and for applica-
tion_data content type.
Prototype
typedef
(EFIAPI *EFI_TLS_PROCESS_PACKET)(
IN OUT EFI_TLS_FRAGMENT_DATA **FragmentTable,
IN EFI_TLS_CRYPT_MODE CryptMode
);
while it may be reallocated in TLS driver. If CryptMode isEﬁTlsEncrypt, on input these fragments contain the
TLS header and plain text TLS APP payload; on output these fragments contain the TLS header and cypher text
TLS APP payload. If CryptMode isEﬁTlsDecrypt, on input these fragments contain the TLS header and cypher
text TLS APP payload; on output these fragments contain the TLS header and plain text TLS APP payload.

Summary
Prototype
typedef
);
TheProcessPacket () function process each inbound or outbound TLS APP packet.
// EFI_TLS_FRAGMENT_DATA
} EFI_TLS_FRAGMENT_DATA;
// EFI_TLS_CRYPT_MODE
EfiTlsEncrypt,
EfiTlsDecrypt,
} EFI_TLS_CRYPT_MODE;
EﬁTlsEncrypt Encrypt data provided in the fragment buffers.
EﬁTlsDecrypt Decrypt data provided in the fragment buffers.
28.10. EFI TLS Protocols 1211Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
•FragmentTable isNULL .
•FragmentCount isNULL .
•CryptoMode is invalid.
EFI_NOT_READY Current TLS session state is NOT EﬁTlsSessionDataTransferring.
EFI_ABORTED Something wrong decryption the message. TLS session status will become
EﬁTlsSessionError. The caller need call BuildResponsePacket() to generate
Error Alert message and send it out.
EFI_OUT_OF_RESOURCES No enough resource to ﬁnish the operation.
28.10.7 EFI TLS Conﬁguration Protocol
28.10.7.1 EFI_TLS_CONFIGURATION_PROTOCOL
Summary
This protocol provides a way to set and get TLS conﬁguration.
GUID
#define EFI_TLS_CONFIGURATION_PROTOCOL_GUID \
{ 0x1682fe44, 0xbd7a, 0x4407, \
{0xb7, 0xc7, 0xdc, 0xa3, 0x7c, 0xa3, 0x92, 0x2d }}
typedef struct _EFI_TLS_CONFIGURATION_PROTOCOL {
EFI_TLS_CONFIGURATION_SET_DATA SetData;
EFI_TLS_CONFIGURATION_GET_DATA GetData;
} EFI_TLS_CONFIGURATION_PROTOCOL;
SetData Set TLS conﬁguration data. See the SetData() function description.
GetData Get TLS conﬁguration data. See the GetData() function description.
TheEFI_TLS_CONFIGURATION_PROTOCOL is designed to provide a way to set and get TLS conﬁguration, such
28.10. EFI TLS Protocols 1212Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
28.10.8 EFI_TLS_CONFIGURATION_PROTOCOL.SetData()
Summary
Set TLS conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_TLS_CONFIGURATION_SET_DATA)(
IN EFI_TLS_CONFIGURATION_PROTOCOL *This,
IN EFI_TLS_CONFIG_DATA_TYPE DataType,
);
This Pointer to the EFI_TLS_CONFIGURATION_PROTOCOL instance.
DataType Conﬁguration data type. See EFI_TLS_CONFIG_DATA_TYPE
TheSetData() function sets TLS conﬁguration to non-volatile storage or volatile storage.
// EFI_TLS_CONFIG_DATA_TYPE
EfiTlsConfigDataTypeHostPublicCert,
EfiTlsConfigDataTypeHostPrivateKey,
EfiTlsConfigDataTypeCACertificate,
EfiTlsConfigDataTypeCertRevocationList,
EfiTlsConfigDataTypeMaximum
} EFI_TLS_CONFIG_DATA_TYPE;
EﬁTlsConﬁgDataTypeHostPublicCert Local host conﬁguration data: public certiﬁcate data.This data should be
DER-encoded binary X.509 certiﬁcate or PEM-encoded X.509 certiﬁcate.
EﬁTlsConﬁgDataTypeHostPrivateKey Local host conﬁguration data: private key data.
EﬁTlsConﬁgDataTypeCACertiﬁcate CA certiﬁcate to verify peer. This data should be PEM-encoded RSA or
PKCS#8 private key.
EﬁTlsConﬁgDataTypeCertRevocationList CA-supplied Certiﬁcate Revocation List data. This data should be DER-
encoded CRL data.
EFI_SUCCESS The TLS conﬁguration data is set successfully.
28.10. EFI TLS Protocols 1213Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 28.68 – continued from previous page
28.10.9 EFI_TLS_CONFIGURATION_PROTOCOL.GetData()
Summary
Get TLS conﬁguration data.
Prototype
typedef
(EFIAPI *EFI_TLS_CONFIGURATION_GET_DATA)(
);
DataSize Total size of conﬁguration data. On input, it means the size of Data buffer. On output, it means the size of
copied Data buffer if EFI_SUCCESS, and means the size of desired Data buffer if EFI_BUFFER_TOO_SMALL .
TheGetData() function gets TLS conﬁguration.
EFI_SUCCESS The TLS conﬁguration data is got successfully.
•DataSize isNULL
EFI_NOT_FOUND The TLS conﬁguration data is not found.
28.10. EFI TLS Protocols 1214CHAPTER
TWENTYNINE
NETWORK PROTOCOLS — ARP, DHCP, DNS, HTTP AND REST
29.1 ARP Protocol
This section deﬁnes the EFI Address Resolution Protocol (ARP) Protocol interface. It is split into the following two
• ARP Service Binding Protocol (ARPSBP)
• ARP Protocol (ARP)
ARP provides a generic implementation of the Address Resolution Protocol that is described in RFCs 826 and 1122.
For RFCs can be found see “Links to UEFI-Related Documents” ( ueﬁ.org/ueﬁ ) under the heading “IETF” (RFCs 826
and 1122) for details for code of ICMP message.
29.1.1 EFI_ARP_SERVICE_BINDING_PROTOCOL
Summary
The ARPSBP is used to locate communication devices that are supported by an ARP driver and to create and destroy
instances of the ARP child protocol driver.
This section discusses the details that are speciﬁc to the ARP.
GUID
#define EFI_ARP_SERVICE_BINDING_PROTOCOL_GUID \
{0xf44c00ee,0x1f2c,0x4a00,\
{0xaa,0x09,0x1c,0x9f,0x3e,0x08,0x00,0xa3}}
A network application (or driver) that requires network address resolution can use one of the protocol handler services,
such as BS->LocateHandleBuffer(), to search for devices that publish a ARPSBP GUID. Each device with a published
ARPSBP GUID supports ARP and may be available for use.
After a successful call to the EFI_ARP _SERVICE_BINDING_PROTOCOL.CreateChild() function, the child ARP
driver instance is in an unconﬁgured state; it is not ready to resolve addresses.
All child ARP driver instances that are created by one EFI_ARP _SERVICE_BINDING_PROTOCOL instance will
share an ARP cache to improve efﬁciency.
EFI_ARP _SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
1215Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_ARP _SERVICE_BINDING_PROTOCOL.DestroyChild() function.
NOTE :All the network addresses that are described in EFI_ARP_PROTOCOL are stored in network byte order. Both
incoming and outgoing ARP packets are also in network byte order. All other parameters that are deﬁned in functions
29.1.2 EFI_ARP_PROTOCOL
Summary
ARP is used to resolve local network protocol addresses into network hardware addresses.
GUID
#define EFI_ARP_PROTOCOL_GUID \
{0xf4b427bb,0xba21,0x4f16,\
{0xbc,0x4e,0x43,0xe4,0x16,0xab,0x61,0x9c}}
typedef struct _EFI_ARP_PROTOCOL {
EFI_ARP_CONFIGURE Configure;
EFI_ARP_ADD Add;
EFI_ARP_FIND Find;
EFI_ARP_DELETE Delete;
EFI_ARP_FLUSH Flush;
EFI_ARP_REQUEST Request;
EFI_ARP_CANCEL Cancel;
} EFI_ARP_PROTOCOL;
Conﬁgure Adds a new station address (protocol type and network address) to the ARP cache. See the Conﬁgure()
Add Manually inserts an entry to the ARP cache for administrative purpose. See the Add() function description.
Find Locates one or more entries in the ARP cache. See the Find() function description.
Delete Removes an entry from the ARP cache. See the Delete() function description.
Flush Removes all dynamic ARP cache entries of a speciﬁed protocol type. See the Flush() function description.
Request Starts an ARP request session. See the Request() function description.
Cancel Abort previous ARP request session. See the Cancel() function description.
TheEFI_ARP _PROTOCOL deﬁnes a set of generic ARP services that can be used by any network protocol driver to

resolve subnet local network addresses into hardware addresses. Normally, a periodic timer event internally sends and
receives packets for ARP. But in some systems where the periodic timer is not supported, drivers and applications that
are experiencing packet loss should try calling the Poll() function of the EFI Managed Network Protocol frequently.
NOTE : Add() and Delete() are typically used for administrative purposes, such as denying trafﬁc to and from a
speciﬁc remote machine, preventing ARP requests from coming too fast, and providing static address pairs to save
time. Find() is also used to update an existing ARP cache entry .
29.1. ARP Protocol 1216Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.1.3 EFI_ARP_PROTOCOL.Conﬁgure()
Summary
Assigns a station address (protocol type and network address) to this instance of the ARP cache.
Prototype
typedef
(EFIAPI *EFI_ARP_CONFIGURE) (
IN EFI_ARP_PROTOCOL *This,
IN EFI_ARP_CONFIG_DATA *ConfigData OPTIONAL
);
This A pointer to the EFI_ARP _PROTOCOL instance.
ConﬁgData A pointer to the EFI_ARP _CONFIG_DATA structure. Type EFI_ARP _CONFIG_DATA is deﬁned in
The Conﬁgure() function is used to assign a station address to the ARP cache for this instance of the ARP driver.
Each ARP instance has one station address. The EFI_ARP _PROTOCOL driver will respond to ARP requests that
match this registered station address. A call to Conﬁgure() with the ConﬁgData ﬁeld set to NULL will reset this ARP
instance.
Once a protocol type and station address have been assigned to this ARP instance, all the following ARP functions
will use this information. Attempting to change the protocol type or station address to a conﬁgured ARP instance will
result in errors.
// EFI_ARP_CONFIG_DATA
UINT16 SwAddressType;
UINT8 SwAddressLength;
VOID *StationAddress;
UINT32 EntryTimeOut;
UINT32 RetryCount;
UINT32 RetryTimeOut;
} EFI_ARP_CONFIG_DATA;
SwAddressType 16-bit protocol type number in host byte order. For more information see “Links to UEFI-Related
Documents” ( ueﬁ.org/ueﬁ ) under the heading “16-bit protocol type numbers”.
SwAddressLength Length in bytes of the station’s protocol address to register.
StationAddress Pointer to the ﬁrst byte of the protocol address to register. For example, if SwAddressType is 0x0800
(IP), then StationAddress points to the ﬁrst byte of this station’s IP address stored in network byte order.
EntryTimeOut The timeout value in 100-ns units that is associated with each new dynamic ARP cache entry. If it is
set to zero, the value is implementation-speciﬁc.
RetryCount The number of retries before a MAC address is resolved. If it is set to zero, the value is implementation-
speciﬁc.
29.1. ARP Protocol 1217Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
RetryTimeOut The timeout value in 100-ns units that is used to wait for the ARP reply packet or the timeout value
between two retries. Set to zero to use implementation-speciﬁc value.
EFI_SUCCESS The new station address was successfully registered.
•SwAddressLength is zero when ConﬁgData is not NULL .
•StationAddress isNULL when ConﬁgData is not NULL .
EFI_ACCESS_DENIED TheSwAddressType, SwAddressLength, orStationAddress is different from
the one that is already registered.
EFI_OUT_OF_RESOURCES Storage for the new StationAddress could not be allocated.
29.1.4 EFI_ARP_PROTOCOL.Add()
Summary
Inserts an entry to the ARP cache.
Prototype
typedef
(EFIAPI *EFI_ARP_ADD) (
IN BOOLEAN DenyFlag,
IN VOID *TargetSwAddress OPTIONAL,
IN VOID *TargetHwAddress OPTIONAL,
IN UINT32 TimeoutValue,
IN BOOLEAN Overwrite
);
This A pointer to the EFI_ARP _PROTOCOL instance..
DenyFlag
Set to TRUE if this entry is a “deny” entry.
Set to FALSE if this entry is a “normal” entry.
TargetSwAddress Pointer to a protocol address to add (or deny). May be set to NULL ifDenyFlag isTRUE .
TargetHwAddress Pointer to a hardware address to add (or deny). May be set to NULL ifDenyFlag is*TRUE .*
TimeoutValue Time in 100-ns units that this entry will remain in the ARP cache. A value of zero means that the entry
is permanent. A nonzero value will override the one given by Conﬁgure() if the entry to be added is dynamic
entry.
Overwrite
IfTRUE, the matching cache entry will be overwritten with the supplied parameters.
IfFALSE, EFI_ACCESS_DENIED is returned if the corresponding cache entry already exists.
29.1. ARP Protocol 1218Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheAdd() function is used to insert entries into the ARP cache.
ARP cache entries are typically inserted and updated by network protocol drivers as network trafﬁc is processed. Most
ARP cache entries will time out and be deleted if the network trafﬁc stops. ARP cache entries that were inserted by
theAdd() function may be static (will not time out) or dynamic (will time out).
Default ARP cache timeout values are not covered in most network protocol speciﬁcations (although RFC 1122 comes
pretty close) and will only be discussed in general in this speciﬁcation. The timeout values that are used in the EFI
Sample Implementation should be used only as a guideline. Final product implementations of the EFI network stack
should be tuned for their expected network environments.
TheAdd() function can insert the following two types of entries into the ARP cache:
• “Normal” entries
• “Deny” entries
“Normal” entries must have both a TargetSwAddress andTargetHwAddress and are used to resolve network protocol
addresses into network hardware addresses. Entries are keyed by TargetSwAddress. Each TargetSwAddress can have
only one TargetHwAddress. ATargetHwAddress may be referenced by multiple TargetSwAddress entries.
“Deny” entries may have a TargetSwAddress or aTargetHwAddress, but not both. These entries tell the ARP driver to
ignore any trafﬁc to and from (and to) these addresses. If a request comes in from an address that is being denied, then
the request is ignored.
If a normal entry to be added matches a deny entry of this driver, Overwrite decides whether to remove the matching
deny entry. On the other hand, an existing normal entry can be removed based on the value of Overwrite if a deny
entry to be added matches the existing normal entry. Two entries are matched only when they have the same addresses
or when one of the normal entry addresses is the same as the address of a deny entry.
EFI_SUCCESS The entry has been added or updated.
DenyFlag isFALSE andTargetHwAddress isNULL .
DenyFlag isFALSE andTargetSwAddress isNULL .
TargetHwAddress isNULL andTargetSwAddress isNULL
Both TargetSwAddress andTargetHwAddress are not NULL when
DenyFlag isTRUE .
EFI_OUT_OF_RESOURCES The new ARP cache entry could not be allocated.
EFI_ACCESS_DENIED The ARP cache entry already exists and Overwrite is not TRUE .
EFI_NOT_STARTED The ARP driver instance has not been conﬁgured.
29.1.5 EFI_ARP_PROTOCOL.Find()
Summary
Locates one or more entries in the ARP cache.
Prototype
typedef
(EFIAPI *EFI_ARP_FIND) (
29.1. ARP Protocol 1219Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN BOOLEAN BySwAddress,
IN VOID *AddressBuffer OPTIONAL,
OUT UINT32 *EntryLength OPTIONAL,
OUT UINT32 *EntryCount OPTIONAL,
OUT EFI_ARP_FIND_DATA **Entries OPTIONAL,
IN BOOLEAN Refresh
);
BySwAddress
Set to TRUE to look for matching software protocol addresses.
Set to FALSE to look for matching hardware protocol addresses.
AddressBuffer Pointer to address buffer. Set to NULL to match all addresses.
EntryLength The size of an entry in the entries buffer. To keep the EFI_ARP _FIND_DATA structure properly
aligned, this ﬁeld may be longer than sizeof(EFI_ARP _FIND_DATA) plus the length of the software and hard-
ware addresses.
EntryCount The number of ARP cache entries that are found by the speciﬁed criteria.
Entries Pointer to the buffer that will receive the ARP cache entries. Type EFI_ARP _FIND_DATA is deﬁned in
Refresh Set to TRUE to refresh the timeout value of the matching ARP cache entry.
TheFind() function searches the ARP cache for matching entries and allocates a buffer into which those entries are
copied. The ﬁrst part of the allocated buffer is EFI_ARP _FIND_DATA, following which are protocol address pairs
and hardware address pairs.

When ﬁnding a speciﬁc protocol address ( BySwAddress isTRUE andAddressBuffer is not NULL ), the ARP cache
timeout for the found entry is reset if Refresh is set to TRUE . If the found ARP cache entry is a permanent entry, it is
not affected by Refresh.
// EFI_ARP_FIND_DATA
UINT32 Size;
BOOLEAN DenyFlag;
BOOLEAN StaticFlag;
UINT16 HwAddressType;
UINT8 HwAddressLength;
} EFI_ARP_FIND_DATA;
Size Length in bytes of this entry.
DenyFlag
29.1. ARP Protocol 1220Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
StaticFlag
Set to TRUE if this entry will not time out.
Set to FALSE if this entry will time out.
HwAddressType 16-bit ARP hardware identiﬁer number.
SwAddressType 16-bit protocol type number.
HwAddressLength Length of the hardware address.
SwAddressLength Length of the protocol address.
EFI_SUCCESS The requested ARP cache entries were copied into the buffer.
• Both EntryCount andEntryLength areNULL , when Refresh isFALSE .
EFI_NOT_FOUND No matching entries were found.
29.1.6 EFI_ARP_PROTOCOL.Delete()
Summary
Removes entries from the ARP cache.
Prototype
typedef
(EFIAPI *EFI_ARP_DELETE) (
IN VOID *AddressBuffer OPTIONAL
);
Set to TRUE to delete matching protocol addresses.
Set to FALSE to delete matching hardware addresses.
AddressBuffer Pointer to the address buffer that is used as a key to look for the cache entry. Set to NULL to delete
all entries.
The Delete() function removes speciﬁed ARP cache entries.
29.1. ARP Protocol 1221Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The entry was removed from the ARP cache.
EFI_NOT_FOUND The speciﬁed deletion key was not found.
29.1.7 EFI_ARP_PROTOCOL.Flush()
Summary
Removes all dynamic ARP cache entries that were added by this interface.
Prototype
typedef
(EFIAPI *EFI_ARP_FLUSH) (
IN EFI_ARP_PROTOCOL *This
);
TheFlush() function deletes all dynamic entries from the ARP cache that match the speciﬁed software protocol type.
EFI_SUCCESS The cache has been ﬂushed.
EFI_NOT_FOUND There are no matching dynamic cache entries.
29.1.8 EFI_ARP_PROTOCOL.Request()
Summary
Starts an ARP request session.
Prototype
typedef
(EFIAPI *EFI_ARP_REQUEST) (
IN EFI_EVENT ResolvedEvent OPTIONAL,
OUT VOID *TargetHwAddress
);
TargetSwAddress Pointer to the protocol address to resolve.
29.1. ARP Protocol 1222Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ResolvedEvent Pointer to the event that will be signaled when the address is resolved or some error occurs.
TargetHwAddress Pointer to the buffer for the resolved hardware address in network byte order. The buffer must be
large enough to hold the resulting hardware address. TargetHwAddress must not be NULL .
The Request() function tries to resolve the TargetSwAddress and optionally returns a TargetHwAddress if it already
exists in the ARP cache.
If the registered SwAddressType (see EFI_ARP _PROTOCOL.Add() ) is IPv4 or IPv6 and the Tar-
getSwAddress is a multicast address, then the TargetSwAddress is resolved using the underlying
EFI_MANAGED_NETWORK_PROTOCOL.McastIpToMac() function.
If the TargetSwAddress isNULL, then the network interface hardware broadcast address is returned immediately in
TargetHwAddress.
If the ResolvedEvent is not NULL and the address to be resolved is not in the ARP cache, then the event will be
signaled when the address request completes and the requested hardware address is returned in the TargetHwAddress.
If the timeout expires and the retry count is exceeded or an unexpected error occurs, the event will be signaled to notify
the caller, which should check the TargetHwAddress to see if the requested hardware address is available. If it is not
available, the TargetHwAddress is ﬁlled by zero.
If the address to be resolved is already in the ARP cache and resolved, then the event will be signaled immediately if
it is not NULL, and the requested hardware address is also returned in TargetHwAddress.
EFI_SUCCESS The data was copied from the ARP cache into the TargetHwAddress buffer.
This isNULL
TargetHwAddress isNULL
EFI_ACCESS_DENIED The requested address is not present in the normal ARP cache but is present
in the deny address list. Outgoing trafﬁc to that address is forbidden.
EFI_NOT_READY The request has been started and is not ﬁnished.
EFI_UNSUPPORTED The requested conversion is not supported in this implementation or conﬁg-
uration.
29.1.9 EFI_ARP_PROTOCOL.Cancel()
Summary
Cancels an ARP request session.
Prototype
typedef
(EFIAPI *EFI_ARP_CANCEL) (
IN EFI_EVENT ResolvedEvent OPTIONAL
);
29.1. ARP Protocol 1223Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TargetSwAddress Pointer to the protocol address in previous request session.
ResolvedEvent Pointer to the event that is used as the notiﬁcation event in previous request session.
TheCancel() function aborts the previous ARP request (identiﬁed by This, TargetSwAddress andResolvedEvent ) that
is issued by EFI_ARP _PROTOCOL.Request(). If the request is in the internal ARP request queue, the request is
aborted immediately and its ResolvedEvent is signaled. Only an asynchronous address request needs to be canceled.
IfTargeSwAddress andResolveEvent are both NULL, all the pending asynchronous requests that have been issued by
This instance will be cancelled and their corresponding events will be signaled.
EFI_SUCCESS The pending request session(s) is/are aborted and corresponding event(s)
is/are signaled.
•TargetSwAddress is not NULL andResolvedEvent isNULL
•TargetSwAddress isNULL andResolvedEvent is not NULL
EFI_NOT_FOUND The request is not issued by EFI_ARP _PROTOCOL.Request().
29.2 EFI DHCPv4 Protocol
This section provides a detailed description of the EFI_DHCP4_PROTOCOL and the
EFI_DHCP4_SERVICE_BINDING_PROTOCOL. The EFI DHCPv4 Protocol is used to collect conﬁguration
information for the EFI IPv4 Protocol drivers and to provide DHCPv4 server and PXE boot server discovery services.
29.2.1 EFI_DHCP4_SERVICE_BINDING_PROTOCOL
Summary
The EFI DHCPv4 Service Binding Protocol is used to locate communication devices that are supported by an EFI
DHCPv4 Protocol driver and to create and destroy EFI DHCPv4 Protocol child driver instances that can use the
GUID
#define EFI_DHCP4_SERVICE_BINDING_PROTOCOL_GUID \
{0x9d9a39d8,0xbd42,0x4a73,\
{0xa4,0xd5,0x8e,0xe9,0x4b,0xe1,0x13,0x80}}
A network application or driver that requires basic DHCPv4 services can use one of the protocol handler services, such
asBS->LocateHandleBuffer(), to search for devices that publish an EFI DHCPv4 Service Binding Protocol GUID.
Each device with a published EFI DHCPv4 Service Binding Protocol GUID supports the EFI DHCPv4 Protocol and
may be available for use.
29.2. EFI DHCPv4 Protocol 1224Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
After a successful call to the EFI_DHCP4_SERVICE_BINDING_PROTOCOL .CreateChild() function, the newly
created EFI DHCPv4 Protocol child driver instance is ready to be used by a network application or driver.
Before a network application or driver terminates execution, every successful call to the
EFI_DHCP4_SERVICE_BINDING_PROTOCOL .CreateChild() function must be matched with a call to the
EFI_DHCP4_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
29.2.2 EFI_DHCP4_PROTOCOL
Summary
This protocol is used to collect conﬁguration information for the EFI IPv4 Protocol drivers and to provide DHCPv4

Summary
server and PXE boot server discovery services.
GUID
#define EFI_DHCP4_PROTOCOL_GUID \
{0x8a219718,0x4ef5,0x4761,\
{0x91,0xc8,0xc0,0xf0,0x4b,0xda,0x9e,0x56}}
typedef struct _EFI_DHCP4_PROTOCOL {
EFI_DHCP4_GET_MODE_DATA GetModeData;
EFI_DHCP4_CONFIGURE Configure;
EFI_DHCP4_START Start;
EFI_DHCP4_RENEW_REBIND RenewRebind;
EFI_DHCP4_RELEASE Release;
EFI_DHCP4_STOP Stop;
EFI_DHCP4_BUILD Build;
EFI_DHCP4_TRANSMIT_RECEIVE TransmitReceive;
EFI_DHCP4_PARSE Parse;
} EFI_DHCP4_PROTOCOL;
GetModeData Gets the EFI DHCPv4 Protocol driver status and operational data. See the GetModeData() function
Conﬁgure Initializes, changes, or resets operational settings for the EFI DHCPv4 Protocol driver. See the Conﬁgure()
Start Starts the DHCP conﬁguration process. See the Start() function description.
RenewRebind Tries to manually extend the lease time by sending a request packet. See the RenewRebind() function
Release Releases the current conﬁguration and returns the EFI DHCPv4 Protocol driver to the initial state. See the
Release() function description.
Stop Stops the DHCP conﬁguration process no matter what state the driver is in. After being stopped, this driver will
not automatically communicate with the DHCP server. See the Stop() function description.
Build Puts together a DHCP or PXE packet. See the Build() function description.
TransmitReceive Transmits a DHCP or PXE packet and waits for response packets. See the TransmitReceive()
Parse Parses the packed DHCP or PXE option data. See the Parse() function description.
29.2. EFI DHCPv4 Protocol 1225Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The EFI_DHCP4_PROTOCOL is used to collect conﬁguration information for the EFI IPv4 Protocol driver and pro-
vide DHCP server and PXE boot server discovery services.
Byte Order Note
All the IPv4 addresses that are described in EFI_DHCP4_PROTOCOL are stored in network byte order. Both incom-
ing and outgoing DHCP packets are also in network byte order. All other parameters that are deﬁned in functions or
data structures are stored in host byte order
29.2.3 EFI_DHCP4_PROTOCOL.GetModeData()
Summary
Returns the current operating mode and cached data packet for the EFI DHCPv4 Protocol driver.
Prototype
typedef
(EFIAPI *EFI_DHCP4_GET_MODE_DATA)(
IN EFI_DHCP4_PROTOCOL *This,
OUT EFI_DHCP4_MODE_DATA *Dhcp4ModeData
);
This Pointer to the EFI_DHCP4_PROTOCOL instance.
Dhcp4ModeData Pointer to storage for the EFI_DHCP4_MODE_DATA structure. Type
EFI_DHCP4_MODE_DATA is deﬁned in “Related Deﬁnitions” below.
TheGetModeData() function returns the current operating mode and cached data packet for the EFI DHCPv4 Protocol
driver.
// EFI_DHCP4_MODE_DATA
EFI_DHCP4_STATE State;
EFI_DHCP4_CONFIG_DATA ConfigData;
EFI_IPv4_ADDRESS ClientAddress;
EFI_MAC_ADDRESS ClientMacAddress;
EFI_IPv4_ADDRESS ServerAddress;
EFI_IPv4_ADDRESS RouterAddress;
UINT32 LeaseTime;
EFI_DHCP4_PACKET *ReplyPacket;
} EFI_DHCP4_MODE_DATA;
State The EFI DHCPv4 Protocol driver operating state. Type EFI_DHCP4_STATE is deﬁned below.
ConﬁgData The conﬁguration data of the current EFI DHCPv4 Protocol driver instance. Type
EFI_DHCP4_CONFIG_DATA is deﬁned in EFI_DHCP4_PROTOCOL .Conﬁgure().
29.2. EFI DHCPv4 Protocol 1226Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ClientAddress The client IP address that was acquired from the DHCP server. If it is zero, the DHCP acquisition has
not completed yet and the following ﬁelds in this structure are undeﬁned.
ClientMacAddress The local hardware address.
ServerAddress The server IP address that is providing the DHCP service to this client.
RouterAddress The router IP address that was acquired from the DHCP server. May be zero if the server does not
offer this address.
SubnetMask The subnet mask of the connected network that was acquired from the DHCP server.
LeaseTime The lease time (in 1-second units) of the conﬁgured IP address. The value 0xFFFFFFFF means that the
lease time is inﬁnite. A default lease of 7 days is used if the DHCP server does not provide a value.
ReplyPacket The cached latest DHCPACK or DHCPNAK or BOOTP REPLY packet. May be NULL if no packet is
cached.
The EFI_DHCP4_MODE_DATA structure describes the operational data of the current DHCP procedure.
// EFI_DHCP4_STATE
Dhcp4Stopped = 0x0,
Dhcp4Init = 0x1,
Dhcp4Selecting = 0x2,
Dhcp4Requesting = 0x3,
Dhcp4Bound = 0x4
Dhcp4Renewing = 0x5,
Dhcp4Rebinding = 0x6,
Dhcp4InitReboot = 0x7,
Dhcp4Rebooting = 0x8
} EFI_DHCP4_STATE;
Table 29.8: DHCP4 Enumerations
Field Description
Dhcp4Stopped The EFI DHCPv4 Protocol driver is stopped and
EFI_DHCP4_PROTOCOL.Conﬁgure() needs to be called. The rest of the
EFI_DHCP4_MODE_DATA structure is undeﬁned in this state.
Dhcp4Init The EFI DHCPv4 Protocol driver is inactive and EFI_DHCP4_PROTOCOL.Start()
needs to be called. The rest of the EFI_DHCP4_MODE_DATA structure is undeﬁned
in this state.
Dhcp4Selecting The EFI DHCPv4 Protocol driver is collecting DHCP offer packets from DHCP
servers. The rest of the EFI_DHCP4_MODE_DATA structure is undeﬁned in this
state.
Dhcp4Requesting The EFI DHCPv4 Protocol driver has sent the request to the DHCP server and is wait-
ing for a response. The rest of the EFI_DHCP4_MODE_DATA structure is undeﬁned
Dhcp4Bound The DHCP conﬁguration has completed. All of the ﬁelds in the
EFI_DHCP4_MODE_DATA structure are deﬁned.
Dhcp4Renewing The DHCP conﬁguration is being renewed and another request has been sent out,
but it has not received a response from the server yet. All of the ﬁelds in the
EFI_DHCP4_MODE_DATA structure are available but may change soon.
Dhcp4Rebinding The DHCP conﬁguration has timed out and the EFI DHCPv4 Protocol driver is trying
to extend the lease time. The rest of the EFI_DHCP4_MODE structure is undeﬁned
29.2. EFI DHCPv4 Protocol 1227Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.8 – continued from previous page
Dhcp4InitReboot The EFI DHCPv4 Protocol driver is initialized with a previously allocated or known
IP address. EFI_DHCP4_PROTOCOL.Start() needs to be called to start the conﬁgu-
ration process. The rest of the EFI_DHCP4_MODE_DATA structure is undeﬁned in
this state.
Dhcp4Rebooting The EFI DHCPv4 Protocol driver is seeking to reuse the previously allo-
cated IP address by sending a request to the DHCP server. The rest of the
EFI_DHCP4_STATE deﬁnes the DHCP operational states that are described in RFC 2131, which can be obtained at
“Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “RFC 2131”.
A variable number of EFI DHCPv4 Protocol driver instances can coexist but they share the same state machine. More
precisely, each communication device has a separate DHCP state machine if there are multiple communication devices.
Each EFI DHCPv4 Protocol driver instance that is created by the same EFI DHCPv4 Service Binding Protocol driver
instance shares the same state machine. In this document, when we refer to the state of EFI DHCPv4 Protocol driver,
we actually refer to the state of the communication device from which the current EFI DHCPv4 Protocol Driver
instance is created.
// EFI_DHCP4_PACKET
struct{
EFI_DHCP4_HEADER Header;
UINT32 Magik;
UINT8 Option[1];
} Dhcp4;
} FI_DHCP4_PACKET;
Size Size of the EFI_DHCP4_PACKET buffer.
Length Length of the EFI_DHCP4_PACKET from the ﬁrst byte of the Header ﬁeld to the last byte of the Option[]
ﬁeld.
Header DHCP packet header.
Magik DHCP magik cookie in network byte order.
Option Start of the DHCP packed option data. EFI_DHCP4_PACKET deﬁnes the format of DHCPv4 packets. See
RFC 2131 for more information.
EFI_SUCCESS The mode data was returned.
29.2. EFI DHCPv4 Protocol 1228Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.2.4 EFI_DHCP4_PROTOCOL.Conﬁgure()
Summary
Initializes, changes, or resets the operational settings for the EFI DHCPv4 Protocol driver.
Prototype
typedef
(EFIAPI *EFI_DHCP4_CONFIGURE) (
IN EFI_DHCP4_CONFIG_DATA *Dhcp4CfgData OPTIONAL
);
Dhcp4CfgData Pointer to the EFI_DHCP4_CONFIG_DATA. Type EFI_DHCP4_CONFIG_DATA is deﬁned in “Re-
lated Deﬁnitions” below.

ﬁeld.
Summary
Prototype
typedef
);
TheConﬁgure() function is used to initialize, change, or reset the operational settings of the EFI DHCPv4 Protocol
driver for the communication device on which the EFI DHCPv4 Service Binding Protocol is installed. This function
can be successfully called only if both of the following are true:
• This instance of the EFI DHCPv4 Protocol driver is in the Dhcp4Stopped, Dhcp4Init, Dhcp4InitReboot, or
Dhcp4Bound states.
• No other EFI DHCPv4 Protocol driver instance that is controlled by this EFI DHCPv4 Service Binding Protocol
driver instance has conﬁgured this EFI DHCPv4 Protocol driver.
When this driver is in the Dhcp4Stopped state, it can transfer into one of the following two possible initial states:
•Dhcp4Init
•Dhcp4InitReboot
The driver can transfer into these states by calling Conﬁgure() with a non- NULL Dhcp4CfgData. The driver will
transfer into the appropriate state based on the supplied client network address in the ClientAddress parameter and
DHCP options in the OptionList parameter as described in RFC 2131.
When Conﬁgure() is called successfully while Dhcp4CfgData is set to NULL, the default conﬁguring data will be
reset in the EFI DHCPv4 Protocol driver and the state of the EFI DHCPv4 Protocol driver will not be changed. If one
instance wants to make it possible for another instance to conﬁgure the EFI DHCPv4 Protocol driver, it must call this
function with Dhcp4CfgData set to NULL .
// EFI_DHCP4_CONFIG_DATA
UINT32 DiscoverTryCount;
UINT32 *DiscoverTimeout;
UINT32 RequestTryCount;
UINT32 *RequestTimeout;
EFI_DHCP4_CALLBACK Dhcp4Callback;
VOID *CallbackContext;
29.2. EFI DHCPv4 Protocol 1229Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT32 OptionCount;
EFI_DHCP4_PACKET_OPTION **OptionList;
} EFI_DHCP4_CONFIG_DATA;
DiscoverTryCount Number of times to try sending a packet during the Dhcp4SendDiscover event and waiting for a
response during the Dhcp4RcvdOffer event. (This value is also the number of entries in the DiscoverTimeout
array.) Set to zero to use the default try counts and timeout values.
DiscoverTimeout Maximum amount of time (in seconds) to wait for returned packets in each of the retries. Timeout
values of zero will default to a timeout value of one second. Set to NULL to use default timeout values.
RequestTryCount Number of times to try sending a packet during the Dhcp4SendReques t event and waiting for a
response during the Dhcp4RcvdAck event before accepting failure. (This value is also the number of entries in
theRequestTimeout array.) Set to zero to use the default try counts and timeout values.
RequestTimeout Maximum amount of time (in seconds) to wait for return packets in each of the retries. Timeout
ClientAddress For a DHCPDISCOVER, setting this parameter to the previously allocated IP address will cause the
EFI DHCPv4 Protocol driver to enter the Dhcp4InitReboot state. Also, set this ﬁeld to 0.0.0.0 to enter the
Dhcp4Init state.For a DHCPINFORM this parameter should be set to the client network address which was
assigned to the client during a DHCPDISCOVER.
Dhcp4Callback The callback function to intercept various events that occurred in the DHCP conﬁguration process.
Set to NULL to ignore all those events. Type EFI_DHCP4_CALLBACK is deﬁned below.
CallbackContext Pointer to the context that will be passed to Dhcp4Callback when it is called.
OptionCount Number of DHCP options in the OptionList.
OptionList List of DHCP options to be included in every packet that is sent during the Dhcp4SendDiscover event.
Pad options are appended automatically by DHCP driver in outgoing DHCP packets. If OptionList itself contains
pad option, they are ignored by the driver. OptionList can be freed after EFI_DHCP4_PROTOCOL .Conﬁgure()
returns. Ignored if OptionCount is zero. Type EFI_DHCP4_PACKET_OPTION is deﬁned below.
// EFI_DHCP4_CALLBACK
typedef EFI_STATUS ( *EFI_DHCP4_CALLBACK)(
IN EFI_DHCP4_STATE CurrentState,
IN EFI_DHCP4_EVENT Dhcp4Event,
IN EFI_DHCP4_PACKET *Packet, OPTIONAL
OUT EFI_DHCP4_PACKET **NewPacket OPTIONAL
);
This Pointer to the EFI DHCPv4 Protocol instance that is used to conﬁgure this callback function.
Context Pointer to the context that is initialized by EFI_DHCP4_PROTOCOL .Conﬁgure().
CurrentState The current operational state of the EFI DHCPv4 Protocol driver. Type EFI_DHCP4_STATE is deﬁned
inEFI_DHCP4_PROTOCOL .GetModeData().
Dhcp4Event The event that occurs in the current state, which usually means a state transition. Type
EFI_DHCP4_EVENT is deﬁned below.
Packet The DHCP packet that is going to be sent or already received. May be NULL if the event has no asso-
ciated packet. Do not cache this packet except for copying it. Type EFI_DHCP4_PACKET is deﬁned in
EFI_DHCP4_PROTOCOL .GetModeData().
29.2. EFI DHCPv4 Protocol 1230Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NewPacket The packet that is used to replace the above Packet. Do not set this pointer exactly to the above Packet or
a modiﬁed Packet. NewPacket can be NULL if the EFI DHCPv4 Protocol driver does not expect a new packet
to be returned. The user may set NewPacket toNULL if no replacement occurs.
EFI_DHCP4_CALLBACK is provided by the consumer of the EFI DHCPv4 Protocol driver to intercept events that
occurred in the conﬁguration process. This structure provides advanced control of each state transition of the DHCP
process. The returned status code determines the behavior of the EFI DHCPv4 Protocol driver. There are three possible
returned values, which are described in the following table.
EFI_SUCCESS Tells the EFI DHCPv4 Protocol driver to continue the DHCP process. When
it is in the Dhcp4Selecting state, it tells the EFI DHCPv4 Protocol driver to
stop collecting additional packets. The driver will exit the Dhcp4Selecting
state and enter the Dhcp4Requesting state.
EFI_NOT_READY Only used in the Dhcp4Selecting state. The EFI DHCPv4 Protocol driver
will continue to wait for more packets until the retry timeout expires.
EFI_ABORTED Tells the EFI DHCPv4 Protocol driver to abort the current process and re-
turn to the Dhcp4Init orDhcp4InitReboot state.
// EFI_DHCP4_EVENT
Dhcp4SendDiscover = 0x01,
Dhcp4RcvdOffer = 0x02,
Dhcp4SelectOffer = 0x03,
Dhcp4SendRequest = 0x04,
Dhcp4RcvdAck = 0x05,
Dhcp4RcvdNak = 0x06,
Dhcp4SendDecline = 0x07,
Dhcp4BoundCompleted = 0x08,
Dhcp4EnterRenewing = 0x09,
Dhcp4EnterRebinding = 0x0a,
Dhcp4AddressLost = 0x0b,
Dhcp4Fail = 0x0c
} EFI_DHCP4_EVENT;
Dhcp4SendDiscover The packet to start the conﬁguration sequence is about to be sent. The packet is passed to
Dhcp4Callback and can be modiﬁed or replaced in Dhcp4Callback.
Dhcp4RcvdOffer A reply packet was just received. This packet is passed to Dhcp4Callback, which may copy this
packet and cache it for selecting a task later. If the callback returns EFI_SUCCESS, this driver will ﬁnish the
selecting state. If EFI_NOT_READY is returned, this driver will continue to wait for additional reply packets
until the timer expires. In either case, Dhcp4SelectOffer will occur for the user to select an offer.
Dhcp4SelectOffer It is time for Dhcp4Callback to select an offer. This driver passes the latest received DHCPOFFER
packet to the callback. The Dhcp4Callback may store one packet in the NewPacket parameter of the function
that was selected from previously received DHCPOFFER packets. If the latest packet is the selected one or if
the user does not care about it, no extra overhead is needed. Simply skipping this event is enough.
Dhcp4SendRequest A request packet is about to be sent. The user can modify or replace this packet.
Dhcp4RcvdAck A DHCPACK packet was received and will be passed to Dhcp4Callback. The callback may decline
this DHCPACK packet by returning EFI_ABORTED. In this case, the EFI DHCPv4 Protocol driver will proceed
to the Dhcp4SendDecline event.
29.2. EFI DHCPv4 Protocol 1231Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Dhcp4RcvdNak A DHCPNAK packet was received and will be passed to Dhcp4Callback. The EFI DHCPv4 Pro-
tocol driver will then return to the Dhcp4Init state no matter what status code is returned from the callback
function.
Dhcp4SendDecline A decline packet is about to be sent. Dhcp4Callback can modify or replace this packet.The EFI

function.
DHCPv4 Protocol driver will then be set to the Dhcp4Init state.
Dhcp4BoundCompleted The DHCP conﬁguration process has completed. No packet is associated with this event.
Dhcp4EnterRenewing It is time to enter the Dhcp4Renewing state and to contact the server that originally issued the
network address. No packet is associated with this event.
Dhcp4EnterRebinding It is time to enter the Dhcp4Rebinding state and to contact any server. No packet is associated
with this event.
Dhcp4AddressLost The conﬁgured IP address was lost either because the lease has expired, the user released the
conﬁguration, or a DHCPNAK packet was received in the Dhcp4Renewing orDhcp4Rebinding state. No packet
is associated with this event.
Dhcp4Fail The DHCP process failed because a DHCPNAK packet was received or the user aborted the DHCP process
at a time when the conﬁguration was not available yet. No packet is associated with this event.
// EFI_DHCP4_HEADER
UINT8 OpCode;
UINT8 HwType;
UINT8 HwAddrLen;
UINT8 Hops;
UINT32 Xid;
UINT16 Seconds;
UINT16 Reserved;
EFI_IPv4_ADDRESS ClientAddr;
EFI_IPv4_ADDRESS YourAddr;
EFI_IPv4_ADDRESS ServerAddr;
EFI_IPv4_ADDRESS GatewayAddr;
UINT8 ClientHwAddr[16];
CHAR8 ServerName[64];
CHAR8 BootFileName[128];
} EFI_DHCP4_HEADER;
OpCode Message type. 1 = BOOTREQUEST, 2 = BOOTREPLY .
HwType Hardware address type.
HwAddrLen Hardware address length.
Hops Maximum number of hops (routers, gateways, or relay agents) that this DHCP packet can go through before it
is dropped.
Xid DHCP transaction ID.
Seconds Number of seconds that have elapsed since the client began address acquisition or the renewal process.
Reserved Reserved for future use.
ClientAddr Client IP address from the client.
YourAddr Client IP address from the server.
29.2. EFI DHCPv4 Protocol 1232Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ServerAddr IP address of the next server in bootstrap.
GatewayAddr Relay agent IP address.
ClientHwAddr Client hardware address.
ServerName Optional server host name.
BootFileName Boot ﬁle name.
EFI_DHCP4_HEADER describes the semantics of the DHCP packet header. This packet header is in network byte
order.
// EFI_DHCP4_PACKET_OPTION
} EFI_DHCP4_PACKET_OPTION;
OpCode DHCP option code.
Length Length of the DHCP option data. Not present if OpCode is 0 or 255.
Data Start of the DHCP option data. Not present if OpCode is 0 or 255 or if Length is zero.
The DHCP packet option data structure is used to reference option data that is packed in the DHCP packets. Use
caution when accessing multibyte ﬁelds because the information in the DHCP packet may not be properly aligned for
the machine architecture.
EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Init or
Dhcp4InitReboot state, if the original state of this driver was
Dhcp4Stopped, Dhcp4Init, Dhcp4InitReboot, orDhcp4Bound and the value
ofDhcp4CfgData was not NULL . Otherwise, the state was left unchanged.
EFI_ACCESS_DENIED This instance of the EFI DHCPv4 Protocol driver was not in the
Dhcp4Stopped, Dhcp4Init, Dhcp4InitReboot, orDhcp4Bound state.
EFI_ACCESS_DENIED Another instance of this EFI DHCPv4 Protocol driver is already in a valid
conﬁgured state.
One or more following conditions are TRUE :
•DiscoverTryCount > 0 and DiscoverTimeout isNULL
•RequestTryCount > 0 and RequestTimeout isNULL .
•OptionCount >0 and OptionList isNULL .
•ClientAddress is not a valid unicast address.
29.2. EFI DHCPv4 Protocol 1233Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.2.5 EFI_DHCP4_PROTOCOL.Start()
Summary
Starts the DHCP conﬁguration process.
Prototype
typedef
(EFIAPI *EFI_DHCP4_START) (
IN EFI_EVENT CompletionEvent OPTIONAL
);
CompletionEvent If not NULL, indicates the event that will be signaled when the EFI DHCPv4 Protocol driver
is transferred into the Dhcp4Bound state or when the DHCP process is aborted. EFI_DHCP4_PROTOCOL
.GetModeData() can be called to check the completion status. If NULL, EFI_DHCP4_PROTOCOL.Start() will
wait until the driver is transferred into the Dhcp4Bound state or the process fails.
TheStart() function starts the DHCP conﬁguration process. This function can be called only when the EFI DHCPv4
Protocol driver is in the Dhcp4Init orDhcp4InitReboot state.
If the DHCP process completes successfully, the state of the EFI DHCPv4 Protocol driver will be transferred through
Dhcp4Selecting andDhcp4Requesting to the Dhcp4Bound state. The CompletionEvent will then be signaled if it is
notNULL .
If the process aborts, either by the user or by some unexpected network error, the state is restored to the Dhcp4Init
state. The Start() function can be called again to restart the process.
Refer to RFC 2131 for precise state transitions during this process. At the time when each event occurs in this process,
the callback function that was set by EFI_DHCP4_PROTOCOL .Conﬁgure() will be called and the user can take this
opportunity to control the process.
EFI_SUCCESS The DHCP conﬁguration process has started, or it has completed when
CompletionEvent isNULL .
EFI_NOT_STARTED The EFI DHCPv4 Protocol driver is in the Dhcp4Stopped state.
EFI_DHCP4_PROTOCOL .Conﬁgure() needs to be called.
EFI_TIMEOUT The DHCP conﬁguration process failed because no response was received
from the server within the speciﬁed timeout value.
EFI_ABORTED The user aborted the DHCP process.
EFI_ALREADY_STARTED Some other EFI DHCPv4 Protocol instance already started the DHCP pro-
cess.
29.2. EFI DHCPv4 Protocol 1234Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.2.6 EFI_DHCP4_PROTOCOL.RenewRebind()
Summary
Extends the lease time by sending a request packet.
Prototype
typedef
(EFIAPI *EFI_DHCP4_RENEW_REBIND) (
IN BOOLEAN RebindRequest,
);
RebindRequest IfTRUE, this function broadcasts the request packets and enters the Dhcp4Rebinding state. Other-
wise, it sends a unicast request packet and enters the Dhcp4Renewing state.
CompletionEvent If not NULL, this event is signaled when the renew/rebind phase completes or some error oc-
curs. EFI_DHCP4_PROTOCOL .GetModeData() can be called to check the completion status. If NULL,
EFI_DHCP4_PROTOCOL.RenewRebind() will busy-wait until the DHCP process ﬁnishes.
TheRenewRebind() function is used to manually extend the lease time when the EFI DHCPv4 Protocol driver is in
theDhcp4Bound state and the lease time has not expired yet. This function will send a request packet to the previ-
ously found server (or to any server when RebindRequest isTRUE ) and transfer the state into the Dhcp4Renewing
state (or Dhcp4Rebinding when RebindingRequest isTRUE ). When a response is received, the state is returned to
Dhcp4Bound.
If no response is received before the try count is exceeded (the RequestTryCount ﬁeld that is speciﬁed in
EFI_DHCP4_CONFIG_DATA ) but before the lease time that was issued by the previous server expires, the driver
will return to the Dhcp4Bound state and the previous conﬁguration is restored. The outgoing and incoming packets
can be captured by the EFI_DHCP4_CALLBACK function.
EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Renewing state or is
back to the Dhcp4Bound state.
EFI_TIMEOUT There was no response from the server when the try count was exceeded.
EFI_ACCESS_DENIED The driver is not in the Dhcp4Bound state.
29.2. EFI DHCPv4 Protocol 1235Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.2.7 EFI_DHCP4_PROTOCOL.Release()
Summary
Releases the current address conﬁguration.
Prototype
typedef
(EFIAPI *EFI_DHCP4_RELEASE) (
IN EFI_DHCP4_PROTOCOL *This
);
TheRelease() function releases the current conﬁgured IP address by doing either of the following:

Summary
Prototype
typedef
);
• Sending a DHCPRELEASE packet when the EFI DHCPv4 Protocol driver is in the Dhcp4Bound state
• Setting the previously assigned IP address that was provided with the EFI_DHCP4_PROTOCOL .Conﬁgure()
function to 0.0.0.0 when the driver is in Dhcp4InitReboot state
After a successful call to this function, the EFI DHCPv4 Protocol driver returns to the Dhcp4Init state and any subse-
quent incoming packets will be discarded silently.
EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Init phase.
EFI_ACCESS_DENIED The EFI DHCPv4 Protocol driver is not in the Dhcp4Bound or
Dhcp4InitReboot state.
29.2.8 EFI_DHCP4_PROTOCOL.Stop()
Summary
Stops the DHCP conﬁguration process.
Prototype
typedef
(EFIAPI *EFI_DHCP4_STOP) (
);
TheStop() function is used to stop the DHCP conﬁguration process. After this function is called successfully, the EFI
DHCPv4 Protocol driver is transferred into the Dhcp4Stopped state. EFI_DHCP4_PROTOCOL .Conﬁgure() needs to
29.2. EFI DHCPv4 Protocol 1236Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
be called before DHCP conﬁguration process can be started again. This function can be called when the EFI DHCPv4
Protocol driver is in any state.
EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Stopped state.
29.2.9 EFI_DHCP4_PROTOCOL.Build()
Summary
Builds a DHCP packet, given the options to be appended or deleted or replaced.
Prototype
typedef
(EFIAPI *EFI_DHCP4_BUILD) (
IN EFI_DHCP4_PACKET *SeedPacket,
IN UINT32 DeleteCount,
IN UINT8 *DeleteList OPTIONAL,
IN UINT32 AppendCount,
IN EFI_DHCP4_PACKET_OPTION *AppendList[] OPTIONAL,
OUT EFI_DHCP4_PACKET **NewPacket
);
SeedPacket Initial packet to be used as a base for building new packet. Type EFI_DHCP4_PACKET is deﬁned in
DeleteCount Number of opcodes in the DeleteList.
DeleteList List of opcodes to be deleted from the seed packet. Ignored if DeleteCount is zero.
AppendCount Number of entries in the OptionList.
AppendList Pointer to a DHCP option list to be appended to SeedPacket. IfSeedPacket also contains options
in this list, they are replaced by new options (except pad option). Ignored if AppendCount is zero. Type
EFI_DHCP4_PACKET_OPTION is deﬁned in EFI_DHCP4_PROTOCOL .Conﬁgure().
NewPacket Pointer to storage for the pointer to the new allocated packet. Use the EFI Boot Service FreePool() on
the resulting pointer when done with the packet.
TheBuild() function is used to assemble a new packet from the original packet by replacing or deleting existing options
or appending new options. This function does not change any state of the EFI DHCPv4 Protocol driver and can be
used at any time.
EFI_SUCCESS The new packet was built.
EFI_OUT_OF_RESOURCES Storage for the new packet could not be allocated.
29.2. EFI DHCPv4 Protocol 1237Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.16 – continued from previous page
•SeedPacket isNULL .
•SeedPacket is not a well-formed DHCP packet.
•AppendCount is not zero and AppendList isNULL .
•DeleteCount is not zero and DeleteList isNULL .
•NewPacket isNULL
• Both DeleteCount andAppendCount are zero and NewPacket is not
NULL .
29.2.10 EFI_DHCP4_PROTOCOL.TransmitReceive()
Summary
Transmits a DHCP formatted packet and optionally waits for responses.
Prototype
typedef
(EFIAPI *EFI_DHCP4_TRANSMIT_RECEIVE) (
IN EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN *Token
);
Token Pointer to the EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN structure. Type
EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN is deﬁned in “Related Deﬁnitions” below.
TheTransmitReceive() function is used to transmit a DHCP packet and optionally wait for the response from servers.
This function does not change the state of the EFI DHCPv4 Protocol driver and thus can be used at any time.
// EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN
EFI_EVENT CompletionEvent;
UINT32 ListenPointCount;
EFI_DHCP4_LISTEN_POINT *ListenPoints;
UINT32 TimeoutValue;
EFI_DHCP4_PACKET *Packet;
UINT32 ResponseCount;
29.2. EFI DHCPv4 Protocol 1238Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_DHCP4_PACKET *ResponseList;
} EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN;
Status The completion status of transmitting and receiving. Possible values are described in the “Status Codes Re-
turned” table below. When CompletionEvent isNULL, this status is the same as the one returned by the Trans-
mitReceive() function.
CompletionEvent If not NULL, the event that will be signaled when the collection process completes. If NULL, this
function will busy-wait until the collection process competes.
RemoteAddress Pointer to the server IP address. This address may be a unicast, multicast, or broadcast address.
RemotePort Server listening port number. If zero, the default server listening port number (67) will be used.
GatewayAddress Pointer to the gateway address to override the existing setting.
ListenPointCount The number of entries in ListenPoints. If zero, the default station address and port number 68 are
used.
ListenPoints An array of station address and port number pairs that are used as receiving ﬁlters. The ﬁrst entry is
also used as the source address and source port of the outgoing packet. Type EFI_DHCP4_LISTEN_POINT is
TimeoutValue Number of seconds to collect responses. Zero is invalid.
Packet Pointer to the packet to be transmitted. Type EFI_DHCP4_PACKET is deﬁned in EFI_DHCP4_PROTOCOL
.GetModeData().
ResponseCount Number of received packets.
ResponseList Pointer to the allocated list of received packets. The caller must use the EFI Boot Service FreePool()
when done using the received packets.
// EFI_DHCP4_LISTEN_POINT
EFI_IPv4_ADDRESS ListenAddress;
UINT16 ListenPort;
} EFI_DHCP4_LISTEN_POINT;
ListenAddress Alternate listening address. It can be a unicast, multicast, or broadcast address. The TransmitReceive()
function will collect only those packets that are destined to this address.
SubnetMask The subnet mask of above listening unicast/broadcast IP address. Ignored if ListenAddress is a multicast
address. If it is 0.0.0.0, the subnet mask is automatically computed from unicast ListenAddress. Cannot be
0.0.0.0 ifListenAddress is direct broadcast address on subnet.
ListenPort Alternate station source (or listening) port number. If zero, then the default station port number (68) will
be used.
EFI_SUCCESS The packet was successfully queued for transmission.
29.2. EFI DHCPv4 Protocol 1239Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.17 – continued from previous page
•Token.RemoteAddress is zero.
•Token.Packet isNULL .
•Token.Packet is not a well-formed DHCP packet.
• The transaction ID in Token.Packet is in use by another DHCP process.
EFI_NOT_READY The previous call to this function has not ﬁnished yet. Try to call this func-
tion after collection process completes.
EFI_NO_MAPPING The default station address is not available yet.
EFI_UNSUPPORTED The implementation doesn’t support this function
Others Some other unexpected error occurred.
29.2.11 EFI_DHCP4_PROTOCOL.Parse()
Summary
Parses the packed DHCP option data.
Prototype
typedef
(EFIAPI *EFI_DHCP4_PARSE) (
IN EFI_DHCP4_PACKET *Packet
IN OUT UINT32 *OptionCount,
IN OUT EFI_DHCP4_PACKET_OPTION *PacketOptionList[] OPTIONAL
);
Packet Pointer to packet to be parsed. Type EFI_DHCP4_PACKET is deﬁned in EFI_DHCP4_PROTOCOL .Get-
ModeData().
OptionCount On input, the number of entries in the PacketOptionList. On output, the number of entries that were
written into the PacketOptionList.

Summary
Prototype
typedef
);
PacketOptionList List of packet option entries to be ﬁlled in. End option or pad options are not included. Type
The Parse() function is used to retrieve the option list from a DHCP packet. If *OptionCount isn’t zero, and there is
enough space for all the DHCP options in the Packet, each element of PacketOptionList is set to point to somewhere in
the Packet->Dhcp4.Option where a new DHCP option begins. If RFC3396 is supported, the caller should reassemble
the parsed DHCP options to get the ﬁnial result. If *OptionCount is zero or there isn’t enough space for all of them,
the number of DHCP options in the Packet is returned in OptionCount.
29.2. EFI DHCPv4 Protocol 1240Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The packet was successfully parsed.
• Packet is NULL.
• Packet is not a well-formed DHCP packet.
• OptionCount is NULL.
• *OptionCount is smaller than the number of options that were found in
the Packet.
• PacketOptionList is NULL.
EFI_OUT_OF_RESOURCE The packet is failed to parse because of resource shortage.
29.3 EFI DHCP6 Protocol
This section provides a detailed description of the EFI_DHCP6_PROTOCOL and the
EFI_DHCP6_SERVICE_BINDING_PROTOCOL.
29.3.1 DHCP6 Service Binding Protocol
29.3.2 EFI_DHCP6_SERVICE_BINDING_PROTOCOL
Summary
The EFI DHCPv6 Service Binding Protocol is used to locate communication devices that are supported by an EFI
DHCPv6 Protocol driver and to create and destroy EFI DHCPv6 Protocol child instances that can use the underlying
GUID
#define EFI_DHCP6_SERVICE_BINDING_PROTOCOL _GUID \
{0x9fb9a8a1,0x2f4a,0x43a6,\
{0x88,0x9c,0xd0,0xf7,0xb6,0xc4,0x7a,0xd5}}
A network application or driver that requires basic DHCPv6 services can use one of the protocol handler services, such
asBS->LocateHandleBuffer(), to search for devices that publish an EFI DHCPv6 Service Binding Protocol GUID.
Each device with a published EFI DHCPv6 Service Binding Protocol GUID supports the EFI DHCPv6 Protocol and
After a successful call to the EFI_DHCP6_SERVICE_BINDING_PROTOCOL.CreateChild() function, the newly cre-
ated EFI DHCPv6 Protocol child instance is ready to be used by a network application or driver.
EFI_DHCP6_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_DHCP6_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
29.3. EFI DHCP6 Protocol 1241Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.3.3 DHCP6 Protocol
29.3.4 EFI_DHCP6_PROTOCOL
Summary
The EFI DHCPv6 Protocol is used to get IPv6 addresses and other conﬁguration parameters from DHCPv6 servers.
GUID
#define EFI_DHCP6_PROTOCOL_GUID \
{0x87c8bad7,0x595,0x4053,\
{0x82,0x97,0xde,0xde,0x39,0x5f,0x5d,0x5b}}
typedef struct _EFI_DHCP6_PROTOCOL {
EFI_DHCP6_GET_MODE_DATA GetModeData;
EFI_DHCP6_CONFIGURE Configure;
EFI_DHCP6_START Start;
EFI_DHCP6_INFO_REQUEST InfoRequest;
EFI_DHCP6_RENEW_REBIND RenewRebind;
EFI_DHCP6_DECLINE Decline;
EFI_DHCP6_RELEASE Release;
EFI_DHCP6_STOP Stop;
EFI_DHCP6_PARSE Parse;
} EFI_DHCP6_PROTOCOL;
GetModeData Get the current operating mode data and conﬁguration data for the EFI DHCPv6 Protocol instance.
See the GetModeData() function description.
Conﬁgure Initialize or clean up the conﬁguration data for the EFI DHCPv6 Protocol instance. See the Conﬁgure()
Start Start the DHCPv6 S.A.R.R process. See the Start() function description.
InfoRequest Request conﬁguration parameters without the assignment of any IPv6 addresses to the client. See the
InfoRequest() function description.
RenewRebind Tries to manually extend the valid and preferred lifetimes for the IPv6 addresses of the conﬁgured IA
by sending Renew or Rebind packet. See the RenewRebind() function description.
Decline Inform that one or more addresses assigned by a DHCPv6 server are already in use by another node. See the
Decline() function description.
Release Release one or more addresses associated with the conﬁgured IA. See the Release() function description.
Stop Stop the DHCPv6 S.A.R.R process. See the Stop() f unction description.
Parse Parses the option data in the DHCPv6 packet. See the Parse() function description.
NOTE: Byte Order: All the IPv6 addresses that are described in EFI_DHCP6_PROTOCOL are stored in network
byte order. Both incoming and outgoing DHCPv6 packets are also in network byte order. All other parameters that
are deﬁned in functions or data structures are stored in host byte order
29.3. EFI DHCP6 Protocol 1242Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.3.5 EFI_DHCP6_PROTOCOL.GetModeData ()
Summary
Retrieve the current operating mode data and conﬁguration data for the EFI DHCPv6 Protocol instance.
Prototype
typedef
(EFIAPI *EFI_DHCP6_GET_MODE_DATA)(
IN EFI_DHCP6_PROTOCOL *This,
OUT EFI_DHCP6_MODE_DATA *Dhcp6ModeData *OPTIONAL,
OUT EFI_DHCP6_CONFIG_DATA *Dhcp6ConfigData *OPTIONAL
);
This Pointer to the EFI_DHCP6_PROTOCOL instance.
Dhcp6ModeData Pointer to the DHCPv6 mode data structure. The caller is responsible for freeing this structure and
each reference buffer. Type EFI_DHCP6_MODE_DATA is deﬁned in “Related Deﬁnitions” below.
Dhcp6ConﬁgData Pointer to the DHCPv6 conﬁguration data structure. The caller is responsible for
freeing this structure and each reference buffer. Type EFI_DHCP6_CONFIG_DATA is deﬁned in
EFI_DHCP6_PROTOCOL.Conﬁgure().
// EFI_DHCP6_MODE_DATA
EFI_DHCP6_DUID *ClientId;
EFI_DHCP6_IA *Ia;
} EFI_DHCP6_MODE_DATA;
ClientId Pointer to the DHCPv6 unique identiﬁer. The caller is responsible for freeing this buffer. Typ e
EFI_DHCP6_DUI D is deﬁned below.
IaPointer to the conﬁgured IA of current instance. The caller can free this buffer after using it. Type EFI_DHCP6_IA
is deﬁned below.
// EFI_DHCP6_DUID
UINT8 Duid[1];
} EFI_DHCP6_DUID;
Length Length of DUID in octets.
Duid Array of DUID octets.
The EFI_DHCP6_DUID structure is to specify DHCPv6 unique identiﬁer for either DHCPv6 client or DHCPv6
server. The DUID-UUID shall be used for all transactions.
29.3. EFI DHCP6 Protocol 1243Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_DHCP6_IA
EFI_DHCP6_IA_DESCRIPTOR Descriptor;
EFI_DHCP6_STATE State;
EFI_DHCP6_PACKACT *ReplyPacket;
UINT32 IaAddressCount;
EFI_DHCP6_IA_ADDRESS IaAddress[1];
} EFI_DHCP6_IA;
Descriptor The descriptor for IA. Type EFI_DHCP6_IA_DESCRIPTOR is deﬁned below.
State The state of the conﬁgured IA. Type EFI_DHCP6_STATE is deﬁned below.
ReplyPacket Pointer to the cached latest Reply packet. May be NULL if no packet is cached.
IaAddressCount Number of IPv6 addresses of the conﬁgured IA.
IaAddress List of the IPv6 addresses of the conﬁgured IA. When the state of the conﬁgured IA is in Dhcp6Bound,
Dhcp6Renewing andDhcp6Rebinding, the IPv6 addresses are usable. Type EFI_DHCP6_IA_ADDRESS is
// EFI_DHCP6_IA_DESCRIPTOR
UINT32 IaId;
} EFI_DHCP6_IA_DESCRIPTOR;
Type Type for an IA.
IaId The identiﬁer for an IA.
#define EFI_DHCP6_IA_TYPE_NA 3
#define EFI_DHCP6_IA_TYPE_TA 4
EFI_DHCP6_IA_TYPE_NA An IA which carries assigned not temporary address.
EFI_DHCP6_IA_TYPE_TA An IA which carries assigned temporary address.
// EFI_DHCP6_STATE
Dhcp6Init = 0x0,
Dhcp6Selecting = 0x1,
Dhcp6Requesting = 0x2,
Dhcp6Declining = 0x3,
Dhcp6Confirming = 0x4,
Dhcp6Releasing = 0x5,
Dhcp6Bound = 0x6,
Dhcp6Renewing = 0x7,
Dhcp6Rebinding = 0x8
} EFI_DHCP6_STATE;
The Table below, Field Descriptions , describes the ﬁelds in the above enumeration.
29.3. EFI DHCP6 Protocol 1244Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.19: Field Descriptions

Dhcp6Init The EFI DHCPv6 Protocol instance is conﬁgured, and start() needs to be called
Dhcp6Selecting A Solicit packet is sent out to discover DHCPv6 server, and the EFI DHCPv6 Protocol
instance is collecting Advertise packets.
Dhcp6Requesting A Request is sent out to the DHCPv6 server, and the EFI DHCPv6 Protocol instance
is waiting for Reply packet.
Dhcp6Declining A Decline packet is sent out to indicate one or more addresses of the conﬁgured IA
are in use by another node, and the EFI DHCPv6 Protocol instance is waiting for
Reply packet.
Dhcp6Conﬁrming A Conﬁrm packet is sent out to conﬁrm the IPv6 addresses of the conﬁgured IA, and
the EFI DHCPv6 Protocol instance is waiting for Reply packet
Dhcp6Releasing A Release packet is sent out to release one or more IPv6 addresses of the conﬁgured
IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.
Dhcp6Bound The DHCPv6 S.A.R.R process is completed for the conﬁgured IA.
Dhcp6Renewing A Renew packet is sent out to extend lifetime for the IPv6 addresses of the conﬁgured
Dhcp6Rebinding A Rebind packet is sent out to extend lifetime for the IPv6 addresses of the conﬁgured
// EFI_DHCP6_IA_ADDRESS
EFI_IPv6_ADDRESS IpAddress;
UINT32 PreferredLifetime;
UINT32 ValidLifetime;
} EFI_DHCP6_IA_ADDRESS;
IpAddress The IPv6 address.
PreferredLifetime The preferred lifetime in unit of seconds for the IPv6 address.
ValidLifetime The valid lifetime in unit of seconds for the IPv6 address.
TheEFI_DHCP6_IA_ADDRESS structure is specify IPv6 address associated with an IA.
// EFI_DHCP6_PACKET
struct{
EFI_DHCP6_HEADER Header;
} Dhcp6;
} EFI_DHCP6_PACKET;
Size Size of the EFI_DHCP6_PACKET buffer.
Length Length of the EFI_DHCP6_PACKET from the ﬁrst byte of the Header ﬁeld to the last byte of the Option[]
ﬁeld.
Header The DHCPv6 packet header.
Option Start of the DHCPv6 packed option data.
29.3. EFI DHCP6 Protocol 1245Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_DHCP6_PACKET deﬁnes the format of the DHCPv6 packet. See RFC 3315 for more information.
// EFI_DHCP6_HEADER
} EFI_DHCP6_HEADER;
TransactionId The DHCPv6 transaction ID.
MessageType The DHCPv6 message type.
EFI_DHCP6_HEADER deﬁnes the format of the DHCPv6 header. See RFC 3315 for more information.
EFI_ACCESS_DENIED The EFI DHCPv6 Protocol instance has not been conﬁgured when
Dhcp6ConﬁgData is not NULL .
• Both Dhcp6ConﬁgData andDhcp6ModeData areNULL .
29.3.6 EFI_DHCP6_PROTOCOL.Conﬁgure ()
Summary
Initialize or clean up the conﬁguration data for the EFI DHCPv6 Protocol instance.
Prototype
typedef
(EFIAPI *EFI_DHCP6_CONFIGURE) (
IN EFI_DHCP6_CONFIG_DATA *Dhcp6CfgData OPTIONAL
);
Dhcp6CfgData Pointer to the DHCPv6 conﬁguration data structure. Type EFI_DHCP6_CONFIG_DATA is deﬁned
TheConﬁgure() function is used to initialize or clean up the conﬁguration data of the EFI DHCPv6 Protocol instance
• When Dhcp6CfgData is not NULL andConﬁgure() is called successfully, the conﬁguration data will be initial-
ized in the EFI DHCPv6 Protocol instance and the state of the conﬁgured IA will be transferred into Dhcp6Init.
29.3. EFI DHCP6 Protocol 1246Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• When Dhcp6CfgData isNULL andConﬁgure() is called successfully, the conﬁguration data will be cleaned up
and no IA will be associated with the EFI DHCPv6 Protocol instance.
To update the conﬁguration data for an EFI DCHPv6 Protocol instance, the original data must be cleaned up before
setting the new conﬁguration data.
// EFI_DHCP6_CONFIG_DATA
EFI_DHCP6_CALLBACK Dhcp6Callback;
EFI_DHCP6_PACKET_OPTION **OptionList;
EFI_DHCP6_IA_DESCRIPTOR IaDescriptor;
EFI_EVENT IaInfoEvent;
BOOLEAN ReconfigureAccept;
BOOLEAN RapidCommit;
EFI_DHCP6_RETRANSMISSION *SolicitRetransmission;
} EFI_DHCP6_CONFIG_DATA;
Dhcp6Callback The callback function is to intercept various events that occur in the DHCPv6 S.A.R.R process. Set
to NULL to ignore all those events. Type EFI_DHCP6_CALLBACK is deﬁned below.
CallbackContext Pointer to the context that will be passed to Dhcp6Callback.
OptionCount Number of the DHCPv6 options in the OptionList.
OptionList The buffer can be freed after EFI_DHCP6_PROTOCOL. Conﬁgure() returns. Ignored if OptionCount is
zero. OptionList should not contain Client Identiﬁer option and any IA option, which will be appended by EFI
DHCPv6 Protocol instance automatically. Type EFI_DHCP6_PACKET_OPTION is deﬁned below.
IaDescriptor The descriptor for the IA of the EFI DHCPv6 Protocol instance. Type EFI_DHCP6_IA_DESCRIPTOR
IaInfoEvent If not NULL, the event will be signaled when any IPv6 address information of the conﬁgured IA is
updated, including IPv6 address, preferred lifetime and valid lifetime, or the DHCPv6 S.A.R.R process fails.
Otherwise, Start(), renewrebind(), decline(), release() and s top() will be blocking operations, and they will wait
for the exchange process completion or failure.
ReconﬁgureAccept IfTRUE, the EFI DHCPv6 Protocol instance is willing to accept Reconﬁgure packet. Otherwise,
it will ignore it. Reconﬁgure Accept option can not be speciﬁed through OptionList parameter.
RapidCommit IfTRUE, the EFI DHCPv6 Protocol instance will send Solicit packet with Rapid Commit option.
Otherwise, Rapid Commit option will not be included in Solicit packet. Rapid Commit option can not be
speciﬁed through OptionList parameter.
SolicitRetransmission Parameter to control Solicit packet retransmission behavior. Type
EFI_DHCP6_RETRANSMISSION is deﬁned in “Related Deﬁnition” below. The buffer can be freed
after EFI_DHCP6_PROTOCOL. Conﬁgure() returns.
// EFI_DHCP6_CALLBACK
typedef EFI_STATUS (EFIAPI *EFI_DHCP6_CALLBACK)(
IN EFI_DHCP6_STATE CurrentState,
29.3. EFI DHCP6 Protocol 1247Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_DHCP6_EVENT Dhcp6Event,
IN EFI_DHCP6_PACKET *Packet,
OUT EFI_DHCP6_PACKET **NewPacket OPTIONAL
);
This Pointer to the EFI_DHCP6_PROTOCOL instance that is used to conﬁgure this callback function.
Context Pointer to the context that is initialized by EFI_DHCP6_PROTOCOL.Conﬁgure().
CurrentState The current state of the conﬁgured IA. Type EFI_DHCP6_STATE is deﬁned in
EFI_DHCP6_PROTOCOL.GetModeData().
Dhcp6Event The event that occurs in the current state, which usually means a state transition. Type
EFI_DHCP6_EVENT is deﬁned below.
Packet Pointer to the DHCPv6 packet that is about to be sent or has been received. The EFI DHCPv6
Protocol instance is responsible for freeing the buffer. Type EFI_DHCP6_PACKET is deﬁned in
NewPacket Pointer to the new DHCPv6 packet to overwrite the Packet. NewPacket can not share the buffer with
Packet. If *NewPacket is not NULL, the EFI DHCPv6 Protocol instance is responsible for freeing the buffer.
EFI_DHCP6_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol instance to intercept events that
occurs in the DHCPv6 S.A.R.R process. There are two possible returned values, which are described in the following
table.
Table 29.21: Callback Return Values
EFI_SUCCESS Tell the EFI DHCPv6 Protocol instance to continue the DHCPv6 S.A.R.R process.
EFI_ABORTED Tell the EFI DHCPv6 Protocol instance to abort the DHCPv6 S.A.R.R process, and
the state of the conﬁgured IA will be transferred to Dhcp6Init.
// EFI_DHCP6_PACKET_OPTION
UINT16 OpCode;
UINT16 OpLen;
} EFI_DHCP6_PACKET_OPTION;
OpCode The DHCPv6 option code, stored in network order.

table.
OpLen Length of the DHCPv6 option data, stored in network order. From the ﬁrst byte to the last byte of the Data
ﬁeld.
Data The data for the DHCPv6 option.
EFI_DHCP6_PACKET_OPTION deﬁnes the format of the DHCPv6 option, stored in network order. See RFC 3315
for more information. This data structure is used to reference option data that is packed in the DHCPv6 packet.
// EFI_DHCP6_EVENT
Dhcp6SendSolicit = 0x0,
29.3. EFI DHCP6 Protocol 1248Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Dhcp6RcvdAdvertise = 0x1,
Dhcp6SelectAdvertise = 0x2,
Dhcp6SendRequest = 0x3,
Dhcp6RcvdReply = 0x4,
Dhcp6RcvdReconfigure = 0x5,
Dhcp6SendDecline = 0x6,
Dhcp6SendConfirm = 0x7,
Dhcp6SendRelease = 0x8,
Dhcp6SendRenew = 0x9,
Dhcp6SendRebind = 0xa
} EFI_DHCP6_EVENT;
Dhcp6SendSolicit A Solicit packet is about to be sent. The packet is passed to Dhcp6Callback and can be modiﬁed
or replaced in Dhcp6Callback.
Dhcp6RcvdAdvertise An Advertise packet is received and will be passed to Dhcp6Callback.
Dhcp6SelectAdvertise It is time for Dhcp6Callback to determine whether select the default Advertise packet by RFC
3315 policy, or overwrite it by speciﬁc user policy.
Dhcp6SendRequest A Request packet is about to be sent. The packet is passed to Dhcp6Callback and can be modi-
ﬁed or replaced in Dhcp6Callback.
Dhcp6RcvdReply A Reply packet is received and will be passed to Dhcp6Callback.
Dhcp6RcvdReconﬁgure A Reconﬁgure packet is received and will be passed to Dhcp6Callback.
Dhcp6SendDecline A Decline packet is about to be sent. The packet is passed to Dhcp6Callback and can be modiﬁed
Dhcp6SendConﬁrm A Conﬁrm packet is about to be sent. The packet is passed to Dhcp6Callback and can be
modiﬁed or replaced in Dhcp6Callback.
Dhcp6SendRelease A Release packet is about to be sent. The packet is passed to Dhcp6Callback and can be modiﬁed
Dhcp6SendRenew A Renew packet is about to be sent. The packet is passed to Dhcp6Callback and can be modiﬁed
Dhcp6SendRebind A Rebind packet is about to be sent. The packet is passed to Dhcp6Callback and can be modiﬁed
// EFI_DHCP6_RETRANSMISSION
UINT32 Irt;
UINT32 Mrc;
UINT32 Mrt;
UINT32 Mrd;
} EFI_DHCP6_RETRANSMISSION;
IrtInitial retransmission timeout.
Mrc Maximum retransmission count for one packet. If Mrc is zero, there’s no upper limit for retransmission count.
Mrt Maximum retransmission timeout for each retry. It’s the upper bound of the number of retransmission timeout.
IfMrtis zero, there is no upper limit for retransmission timeout.
Mrd Maximum retransmission duration for one packet. It’s the upper bound of the numbers the client may retransmit
a message. If Mrd is zero, there’s no upper limit for retransmission duration.
29.3. EFI DHCP6 Protocol 1249Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
One or more following conditions are TRUE
•OptionCount > 0 and OptionList isNULL .
•OptionList is not NULL, and Client Id option, Reconﬁgure Accept option,
Rapid Commit option or any IA option is speciﬁed in the OptionList.
•IaDescriptor. Type is neither EFI_DHCP6_IA_TYPE_NA nor
EFI_DHCP6_IA_TYPE_NA.
•IaDescriptor is not unique.
• Both IaInfoEvent andSolicitRetransmission areNULL .
•SolicitRetransmission is not NULL, and both
SolicitRetransmission->Mrc andSolicitRetransmission->Mrd are zero.
EEFI_ACCESS_DENIED
The EFI DHCPv6 Protocol instance has been already conﬁgured when
Dhcp6CfgData is not NULL .
The EFI DHCPv6 Protocol instance has already started the DHCPv6
S.A.R.R when Dhcp6CfgData isNULL .
29.3.7 EFI_DHCP6_PROTOCOL.Start ()
Summary
Start the DHCPv6 S.A.R.R process.
Prototype
typedef
(EFIAPI *EFI_DHCP6_START) (
IN EFI_DHCP6_PROTOCOL *This
);
The Start() function starts the DHCPv6 S.A.R.R process. This function can be called only when the state of the
conﬁgured IA is in the Dhcp6Init state. If the DHCPv6 S.A.R.R process completes successfully, the state of the
conﬁgured IA will be transferred through Dhcp6Selecting andDhcp6Requesting toDhcp6Bound state. The update of
the IPv6 addresses will be notiﬁed through EFI_DHCP6_CONFIG_DATA.IaInfoEvent. At the time when each event
occurs in this process, the callback function set by EFI_DHCP6_PROTOCOL.Conﬁgure() will be called and the user
can take this opportunity to control the process. If EFI_DHCP6_CONFIG_DATA.IaInfoEvent isNULL, theStart()
function call is a blocking operation. It will return after the DHCPv6 S.A.R.R process completes or aborted by users.
If the process is aborted by system or network error, the state of the conﬁgured IA will be transferred to Dhcp6Init.
TheStart() function can be called again to restart the process.
29.3. EFI DHCP6 Protocol 1250Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The DHCPv6 S.A.R.R process is completed and at least one
IPv6 address has been bound to the conﬁgured IA when E
FI_DHCP6_CONFIG_DATA.IaInfoEvent isNULL . The DHCPv6 S.A.R.R
process is started when E FI_DHCP6_CONFIG_DATA.IaInfoEvent is not
NULL .
EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn’t been conﬁgured.
EFI_ALREADY_STARTED The DHCPv6 S.A.R.R process has already started.
EFI_NO_RESPONSE The DHCPv6 S.A.R.R process failed because of no response.
EFI_NO_MAPPING No IPv6 address has been bound to the conﬁgured IA after the DHCPv6
S.A.R.R process.
EFI_ABORTED The DHCPv6 S.A.R.R process aborted by user.
29.3.8 EFI_DHCP6_PROTOCOL.InfoRequest ()
Summary
Request conﬁguration information without the assignment of any IA addresses of the client.
Prototype
Typedef
(EFIAPI *EFI_DHCP6_INFO_REQUEST) (
IN BOOLEAN SendClientId,
IN EFI_DHCP6_PACKET_OPTION *OptionRequest,
IN UINT32 OptionCount,
IN EFI_DHCP6_PACKET_OPTION *OptionList[] OPTIONAL,
IN EFI_DHCP6_RETRANSMISSION *Retransmission,
IN EFI_EVENT TimeoutEvent OPTIONAL,
IN EFI_DHCP6_INFO_CALLBACK ReplyCallback,
IN VOID *CallbackContext OPTIONAL
);
SendClientId IfTRUE, the EFI DHCPv6 Protocol instance will build Client Identiﬁer option and include it into
Information Request packet. If FALSE, Client Identiﬁer option will not be included. Client Identiﬁer option can
not be speciﬁed through OptionList parameter.
OptionRequest Pointer to the Option Request option in the Information Request packet. Option Request option can
OptionCount Number of options in OptionList.
OptionList List of other DHCPv6 options. These options will be appended to the Option Request option. The caller
is responsible for freeing this buffer. Type is deﬁned in EFI_DHCP6_PROTOCOL.GetModeData().
29.3. EFI DHCP6 Protocol 1251Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Retransmission Parameter to control Information Request packet retransmission behavior. Type
after EFI_DHCP6_PROTOCOL.InfoRequest() returns.
TimeoutEvent If not NULL, this event is signaled when the information request exchange aborted because of no
response. If NULL, the function call is a blocking operation; and it will return after the information-request
exchange process ﬁnish or aborted by users.
ReplyCallback The callback function is to intercept various events that occur in the Information Request exchange
process. It should not be set to NULL . Type EFI_DHCP6_INFO_CALLBACK is deﬁned below.
CallbackContext Pointer to the context that will be passed to ReplyCallback.
TheInfoRequest() function is used to request conﬁguration information without the assignment of any IPv6 address of
the client. Client sends out Information Request packet to obtain the required conﬁguration information, and DHCPv6
server responds with Reply packet containing the information for the client. The received Reply packet will be passed
to the user by ReplyCallback function. If user returns EFI_NOT_READY from ReplyCallback, the EFI DHCPv6 Pro-
tocol instance will continue to receive other Reply packets unless timeout according to the Retransmission parameter.

Otherwise, the Information Request exchange process will be ﬁnished successfully if user returns EFI_SUCCESS from
ReplyCallback .
typedef EFI_STATUS (EFIAPI *EFI_DHCP6_INFO_CALLBACK)(
);
Context Pointer to the context that is initialized in the EFI_DHCP6_PROTOCOL.InfoRequest ().
Packet Pointer to Reply packet that has been received. The EFI DHCPv6 Protocol instance is responsible for freeing
the buffer. Type EFI_DHCP6_PACKET is deﬁned in EFI_DHCP6_PROTOCOL.GetModeData().
EFI_DHCP6_INFO_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol instance to intercept
events that occurs in the DHCPv6 Information Request exchange process. There are three possible returned values,
which are described in the following table.
EFI_SUCCESS Tell the EFI DHCPv6 Protocol instance to ﬁnish Information Request exchange pro-
cess.
EFI_NOT_READY Tell the EFI DHCPv6 Protocol instance to continue Information Request exchange
process.
EFI_ABORTED Tell the EFI DHCPv6 Protocol instance to abort the Information Request exchange
process
EFI_SUCCESS The DHCPv6 information request exchange process completed when Time-
outEvent isNULL . Information Request packet has been sent to DHCPv6
server when TimeoutEvent is not NULL .
29.3. EFI DHCP6 Protocol 1252Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.25 – continued from previous page
•OptionRequest isNULL orOptionRequest->OpCode is invalid.
•OptionList is not NULL, and Client Identify option or Option Request
option is speciﬁed in the OptionList.
•Retransmission isNULL .
• Both Retransmission->Mrc andRetransmission->Mrd are zero.
•ReplyCallback isNULL .
EFI_NO_RESPONSE The DHCPv6 information request exchange process failed because of no
response, or not all requested-options are responded by DHCPv6 servers
when Timeout happened.
EFI_ABORTED The DHCPv6 information request exchange process aborted by user.
29.3.9 EFI_DHCP6_PROTOCOL.RenewRebind ()
Summary
Manually extend the valid and preferred lifetimes for the IPv6 addresses of the conﬁgured IA and update other conﬁg-
uration parameters by sending Renew or Rebind packet.
Prototype
typedef
(EFIAPI *EFI_DHCP6_RENEW_REBIND) (
IN BOOLEAN RebindRequest
);
RebindRequest IfTRUE, it will send Rebind packet and enter the Dhcp6Rebinding state. Otherwise, it will send
Renew packet and enter the Dhcp6Renewing state.
TheRenewRebind () function is used to manually extend the valid and preferred lifetimes for the IPv6 addresses of
the conﬁgured IA and update other conﬁguration parameters by sending Renew or Rebind packet.
• When RebindRequest is FALSE and the state of the conﬁgured IA is Dhcp6Bound, it will send Renew packet
to the previously DHCPv6 server and transfer the state of the conﬁgured IA to Dhcp6Renewing. If valid Reply
packet received, the state transfers to Dhcp6Bound and the valid and preferred timer restarts. If fails, the state
transfers to Dhcp6Bound but the timer continues.
• When RebindRequest is TRUE and the state of the conﬁgured IA is Dhcp6Bound, it will send Rebind packet.
If valid Reply packet received, the state transfers to Dhcp6Bound and the valid and preferred timer restarts. If
fails, the state transfers to Dhcp6Init and the IA can’t be used.
29.3. EFI DHCP6 Protocol 1253Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The DHCPv6 renew/rebind exchange process has completed and at least
one IPv6 address of the conﬁgured IA has been bound again when
EFI_DHCP6_CONFIG_DATA.IaInfoEvent isNULL .
The EFI DHCPv6 Protocol instance has sent Renew or Rebind packet
when EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL .
EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn’t been conﬁgured, or the state of the
conﬁgured IA is not in Dhcp6Bound.
EFI_ALREADY_STARTED
The state of the conﬁgured IA has already entered Dhcp6Renewing when
RebindRequest isFALSE .
The state of the conﬁgured IA has already entered Dhcp6Rebinding when
RebindRequest isTRUE .
EFI_NO_RESPONSE The DHCPv6 renew/rebind exchange process failed because of no response.
renew/rebind exchange process.
EFI_ABORTED The DHCPv6 renew/rebind exchange process aborted by user.
29.3.10 EFI_DHCP6_PROTOCOL.Decline ()
Summary
Inform that one or more IPv6 addresses assigned by a server are already in use by another node.
Prototype
typedef
(EFIAPI *EFI_DHCP6_DECLINE) (
IN UINT32 AddressCount,
IN EFI_IPv6_ADDRESS *Addresses
);
AddressCount Number of declining IPv6 addresses.
Addresses Pointer to the buffer stored all the declining IPv6 addresses.
The Decline () function is used to manually decline the assignment of IPv6 addresses, which have been already
used by another node. If all IPv6 addresses of the conﬁgured IA are declined through this function, the state of the
IA will switch through Dhcp6Declining toDhcp6Init, otherwise, the state of the IA will restore to Dhcp6Bound
after the declining process. The Decline () can only be called when the IA is in Dhcp6Bound state. If the
EFI_DHCP6_CONFIG_DATA.IaInfoEvent isNULL, this function is a blocking operation. It will return after the
declining process ﬁnishes, or aborted by user.
29.3. EFI DHCP6 Protocol 1254Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The DHCPv6 decline exchange process has completed when
E FI_DHCP6_CONFIG_DATA.IaInfoEvent isNULL . The EFI
DHCPv6 Protocol instance has sent Decline packet when E
FI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL .
•AddressCount is zero or Addresses isNULL .
EFI_NOT_FOUND Any speciﬁed IPv6 address is not correlated with the conﬁgured IA for this
instance.
EFI_ABORTED The DHCPv6 decline exchange process aborted by user.
29.3.11 EFI_DHCP6_PROTOCOL.Release ()
Summary
Release one or more IPv6 addresses associated with the conﬁgured IA for current instance.
Prototype
typedef
(EFIAPI *EFI_DHCP6_RELEASE) (
);
AddressCount Number of releasing IPv6 addresses.
Addresses Pointer to the buffer stored all the releasing IPv6 addresses. Ignored if AddressCount is zero.
The Release () function is used to manually release the one or more IPv6 address. If AddressCount is zero, it will
release all IPv6 addresses of the conﬁgured IA. If all IPv6 addresses of the IA are released through this function,
the state of the IA will switch through Dhcp6Releasing toDhcp6Init, otherwise, the state of the IA will restore to
Dhcp6Bound after the releasing process. The Release () can only be called when the IA is in Dhcp6Bound state. If
theEFI_DHCP6_CONFIG_DATA.IaInfoEvent isNULL, the function is a blocking operation. It will return after the
releasing process ﬁnishes, or aborted by user.
EFI_SUCCESS The DHCPv6 release exchange process has completed when
DHCPv6 Protocol instance has sent Release packet when E
29.3. EFI DHCP6 Protocol 1255Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.28 – continued from previous page
•AddressCount is not zero and Addresses isNULL .
instance.
EFI_ABORTED The DHCPv6 release exchange process aborted by user.
29.3.12 EFI_DHCP6_PROTOCOL.Stop ()
Summary
Stop the DHCPv6 S.A.R.R process.
Prototype
typedef
(EFIAPI *EFI_DHCP6_STOP) (

instance.
Summary
Prototype
typedef
);
TheStop () function is used to stop the DHCPv6 S.A.R.R process. If this function is called successfully, all the IPv6
addresses of the conﬁgured IA will be released and the state of the conﬁgured IA will be transferred to Dhcp6Init.
EFI_SUCCESS The DHCPv6 S.A.R.R process has been stopped when E
FI_DHCP6_CONFIG_DATA.IaInfoEvent isNULL . The EFI DHCPv6
Protocol instance has sent Release packet if need release or has been
stopped if needn’t, when E FI_DHCP6_CONFIG_DATA.IaInfoEvent is not
NULL .
29.3. EFI DHCP6 Protocol 1256Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.3.13 EFI_DHCP6_PROTOCOL.Parse ()
Summary
Parse the option data in the DHCPv6 packet.
Prototype
typedef
(EFIAPI *EFI_DHCP6_PARSE) (
IN EFI_DHCP6_PACKET_OPTION *PacketOptionList[] OPTIONAL
);
This Pointer to the EFI_DHCP6_PROTOCOL i nstance.
Packet Pointer to packet to be parsed. Type EFI_DHCP6_PACKET is deﬁned in
OptionCount On input, the number of entries in the PacketOptionList. On output, the number of DHCPv6 options
in the Packet.
PacketOptionList List of pointers to the DHCPv6 options in the Packet. Type EFI_DHCP6_PACKET_OPTION
is deﬁned in EFI_DHCP6_PROTOCOL.Conﬁg ure(). The OpCode andOpLen inEFI_DHCP6_PACKET_O
PTION are both stored in network byte order.
TheParse() function is used to retrieve the option list in the DHCPv6 packet.
•Packet isNULL .
•Packet is not a well-formed DHCPv6 packet.
•OptionCount isNULL .
• *OptionCount is not zero and PacketOptionList isNULL .
EFI_BUFFER_TOO_SMALL *OptionCount is smaller than the number of options that were found in the
Packet.
29.3. EFI DHCP6 Protocol 1257Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.4 EFI DNSv4 Protocol
This section deﬁnes the EFI Domain Name Service Binding Protocol interface. It is split into the following two main
sections.
• DNSv4 Service Binding Protocol (DNSv4SB)
• DNSv4 Protocol (DNSv4)
29.4.1 EFI_DNS4_SERVICE_BINDING_PROTOCOL
Summary
The DNSv4SB is used to locate communication devices that are supported by a DNS driver and to create and destroy
instances of the DNS child protocol driver.
This section discusses the details that are speciﬁc to the DNSv4.
GUID
#define EFI_DNS4_SERVICE_BINDING_PROTOCOL_GUID \
{ 0xb625b186, 0xe063, 0x44f7,\
{ 0x89, 0x5, 0x6a, 0x74, 0xdc, 0x6f, 0x52, 0xb4}}
A network application (or driver) that requires network address resolution can use one of the protocol handler ser-
vices, such as BS->LocateHandleBuffer(), to search for devices that publish a DNSV4SB GUID. Each device with a
published DNSV4SB GUID supports DNS and may be available for use.
After a successful call to the EFI_DNS4_SERVICE_BINDING_PROTOCOL.CreateChild() function, the child DNS
EFI_DNS4_SERVICE_BINDING_PROTOCOL.CreateChi ld() function must be matched with a call to the
EFI_DNS4_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
NOTE :All the network addresses that are described in EFI_DNS4_PROTOCOL are stored in network byte order.
Both incoming and outgoing DNS packets are also in network byte order. All other parameters that are deﬁned in
29.4.2 EFI_DNS4_PROTOCOL
Summary
This protocol provides the function to get the host name and address mapping, also provides pass through interface to
retrieve arbitrary information from DNS.
The EFI_DNS4_Protocol is primarily intended to retrieve host addresses using the standard DNS protocol (RFC1035),
and support for this protocol is required. Implementations may optionally also support local network name resolution
methods such as LLMNR (RFC4795) however DNS queries shall always take precedence, and any use of local network
name protocols would be restricted to cases where resolution using DNS protocol fails.
As stated above, all instances of EFI_DNS4_Protocol will utilize a common DNS cache containing the successful
results of previous queries on any interface. However, it should be noted that every instance of EFI_DNS4_Protocol
is associated with a speciﬁc network device or interface, and that all network actions initiated using a speciﬁc instance
of the DNS protocol will occur only via use of the associated network interface. This means, in a system with multiple
29.4. EFI DNSv4 Protocol 1258Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
network interfaces, that a speciﬁc DNS server will often only be reachable using a speciﬁc network instance, and
therefore the protocol user will need to take steps to insure the DNS instance associated with the proper network
interface is used. Or alternatively, the caller may perform DNS functions against all interfaces until successful result
is achieved.
GUID
#define EFI_DNS4_PROTOCOL_GUID \
{ 0xae3d28cc, 0xe05b, 0x4fa1,\
{0xa0, 0x11, 0x7e, 0xb5, 0x5a, 0x3f, 0x14, 0x1 }}
typedef struct _EFI_DNS4_PROTOCOL {
EFI_DNS4_GET_MODE_DATA GetModeData;
EFI_DNS4_CONFIGURE Configure;
EFI_DNS4_HOST_NAME_TO_IP HostNameToIp;
EFI_DNS4_IP_TO_HOST_NAME IpToHostName;
EFI_DNS4_GENERAL_LOOKUP GeneralLookUp;
EFI_DNS4_UPDATE_DNS_CACHE UpdateDnsCache;
EFI_DNS4_POLL Poll;
EFI_DNS4_CANCEL Cancel;
} EFI_DNS4_PROTOCOL;
29.4.3 EFI_DNS4_PROTOCOL.GetModeData()
Summary
Retrieve the current mode data of this DNS instance.
Prototype
typedef
(EFIAPI *EFI_DNS4_GET_MODE_DATA)(
IN EFI_DNS4_PROTOCOL *This,
OUT EFI_DNS4_MODE_DATA *DnsModeData
);
This function is used to retrieve DNS mode data for this DNS instance.
Parameter
This Pointer to EFI_DNS4_PROTOCOL instance.
DnsModeData Pointer to the caller-allocated storage for the EFI_DNS4_MODE_DATA structure.
// EFI_DNS4_MODE_DATA
EFI_DNS4_CONFIG_DATA DnsConfigData;
UINT32 DnsServerCount;
EFI_IPv4_ADDRESS *DnsServerList;
UINT32 DnsCacheCount;
29.4. EFI DNSv4 Protocol 1259Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_DNS4_CACHE_ENTRY *DnsCacheList;
} EFI_DNS4_MODE_DATA;
DnsConﬁgData The current conﬁguration data of this instance. Type EFI_DNS4_CONFIG_DATA is deﬁned below.
DnsServerCount Number of conﬁgured DNS servers.
DnsServerList Pointer to common list of addresses of all conﬁgured DNS server used by EFI_DNS4_PROTOCOL
instances. List will include DNS servers conﬁgured by this or any other EFI_DNS4_PROTOCOL instance. The
storage for this list is allocated by the driver publishing this protocol, and must be freed by the caller.
DnsCacheCount Number of DNS Cache entries. The DNS Cache is shared among all DNS instances.
DnsCacheList Pointer to a buffer containing DnsCacheCount DNS Cache entry structures. The storage for this list
is allocated by the driver publishing this protocol and must be freed by caller.
// EFI_DNS4_CONFIG_DATA
UINTN DnsServerListCount;
BOOLEAN EnableDnsCache;
UINT32 RetryInterval;
} EFI_DNS4_CONFIG_DATA;
DnsServerListCount Count of the DNS servers. When used with GetModeData(), this ﬁeld is the count of originally
conﬁgured servers when Conﬁgure() was called for this instance. When used with Conﬁgure() this is the count
of caller-supplied servers. If the DnsServerListCount is zero, the DNS server conﬁguration will be retrieved
from DHCP server automatically.
DnsServerList Pointer to DNS server list containing DnsServerListCount entries or NULL if DnsServerListCount is
0. For Conﬁgure(), this will be NULL when there are no caller-supplied server addresses, and, the DNS instance
will retrieve DNS server from DHCP Server. The provided DNS server list is recommended to be ﬁlled up in
the sequence of preference. When used with GetModeData(), the buffer containing the list will be allocated by
the driver implementing this protocol and must be freed by the caller. When used with Conﬁgure(), the buffer
containing the list will be allocated and released by the caller.

UseDefaultSetting Set to TRUE to use the default IP address/subnet mask and default routing table.
<http://www.iana.org/assignments/protocol-numbers>__
EnableDnsCache IfTRUE, enable DNS cache function for this DNS instance. If FALSE, all DNS query will not
lookup local DNS cache.
Protocol Use the protocol number deﬁned in “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the
heading ” IANA Protocol Numbers”. Only TCP or UDP are supported, and other protocol values are invalid.
An implementation can choose to support only UDP, or both TCP and UDP.
StationIp IfUseDefaultSetting isFALSE indicates the station address to use.
SubnetMask IfUseDefaultSetting isFALSE indicates the subnet mask to use.
LocalPort Local port number. Set to zero to use the automatically assigned port number.
29.4. EFI DNSv4 Protocol 1260Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
RetryCount Retry number if no response received after RetryInterval.
RetryInterval Minimum interval of retry is 2 second. If the retry interval is less than 2 second, then use the 2 second.
// EFI_DNS4_CACHE_ENTRY
CHAR16 *HostName;
EFI_IPv4_ADDRESS *IpAddress;
} EFI_DNS4_CACHE_ENTRY;
HostName Host name.
IpAddress IP address of this host.
Timeout Time in second unit that this entry will remain in DNS cache. A value of zero means that this entry is perma-
nent. A nonzero value will override the existing one if this entry to be added is dynamic entry. Implementations
may set its default timeout value for the dynamically created DNS cache entry after one DNS resolve succeeds.
EFI_NOT_STARTED When DnsConﬁgData is queried, no conﬁguration data is available because
this instance has not been conﬁgured.
EFI_INV ALID_PARAMETER This isNULL orDnsModeData isNULL .
EFI_OUT_OF_RESOURCES Failed to allocate needed resources.
29.4.4 EFI_DNS4_PROTOCOL.Conﬁgure()
Summary
Conﬁgures this DNS instance.
Prototype
typedef
(EFIAPI *EFI_DNS4_CONFIGURE)(
IN EFI_DNS4_CONFIG_DATA *DnsConfigData
);
This function is used to conﬁgure DNS mode data for this DNS instance.
DnsConﬁgData Pointer to caller-allocated buffer containing EFI_DNS4_CONFIG_DATA structure containing the
desired Conﬁguration data. If NULL, the driver will reinitialize the protocol instance to the unconﬁgured state.
29.4. EFI DNSv4 Protocol 1261Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.32 – continued from previous page
EFI_UNSUPPORTED The designated protocol is not supported.
EFI_INV ALID_PARAMTER
The StationIp address provided in DnsConﬁgData is not a valid unicast.
DnsServerList isNULL while DnsServerListCount is not ZERO .
DnsServerListCount isZERO while DnsServerList is not NULL .
EFI_OUT_OF_RESOURCES The DNS instance data or required space could not be allocated.
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI DNSv4 Protocol
instance is not conﬁgured.
EFI_ALREADY_STARTED Second call to Conﬁgure() with DnsConﬁgData. To reconﬁgure the instance
the caller must call Conﬁgure() with NULL ﬁrst to return driver to uncon-
ﬁgured state.
29.4.5 EFI_DNS4_PROTOCOL.HostNameToIp()
Summary
Host name to host address translation.
Prototype
typedef
(EFIAPI *EFI_DNS4_HOST_NAME_TO_IP) (
IN CHAR16 *HostName,
IN EFI_DNS4_COMPLETION_TOKEN *Token
);
Parameter
Hostname Pointer to buffer containing fully-qualiﬁed Domain Name including Hostname. To resolve successfully,
characters within the FQDN string must be chosen according to the format and from within the set of ASCII
characters authorized by DNS speciﬁcations. Any translation required for reference to domains or hostnames
deﬁned as containing Unicode characters, for example use of Punycode, must be performed by caller.
Token Pointer to the caller-allocated completion token to return at the completion of the process to translate host
name to host address. Type EFI_DNS4_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions” below.
// EFI_DNS4_COMPLETION_TOKEN
union {
DNS_HOST_TO_ADDR_DATA *H2AData;
DNS_ADDR_TO_HOST_DATA *A2HData;
29.4. EFI DNSv4 Protocol 1262Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DNS_GENERAL_LOOKUP_DATA *GLookupData;
} RspData;
} EFI_DNS4_COMPLETION_TOKEN;
Event This Event will be signaled after the Status ﬁeld is updated by the EFI DNS protocol driver. The type of Event
must be EFI_NOTIFY_SIGNAL.
Status Will be set to one of the following values.
EFI_SUCCESS : The host name to address translation completed successfully.
EFI_NOT_FOUND : No matching Resource Record (RR) is found.
EFI_TIMEOUT : No DNS server reachable, or RetryCount was exhausted without response from all speciﬁed
DNS servers.
EFI_NO_MEDIA : There was a media error.
RetryCount Retry number if no response received after RetryInterval. If zero, use the parameter conﬁgured through
Dns.Conﬁgure() interface.
If zero, use the parameter conﬁgured through Dns.Conﬁgure() interface.
H2AData When the Token is used for host name to address translation, H2AData is a pointer to the
DNS_HOST_TO_ADDR_DATA. Type DNS_HOST_TO_ADDR_DATA is deﬁned below.
A2HData When the Token is used for host address to host name translation, A2HData is a pointer to the
DNS_ADDR_TO_HOST_DATA. Type DNS_ADDR_TO_HOST_DATA is deﬁned below.
GLookupDATA When the Token is used for a general lookup function, GLookupDATA is a pointer to the
DNS_GENERAL_LOOKUP_DATA. Type DNS_GENERAL_LOOKUP_DATA is deﬁned below.
EFI_DNS4_COMPLETION_TOKEN structures are used for host name to address translation, host address to name
translation and general lookup operation, the Event, RetryCount andRetryInterval ﬁelds ﬁled must be ﬁlled by the EFI
DNS4 Protocol Client. After the operation completes, the EFI DNS4 protocol driver ﬁll in the RspData andStatus
ﬁeld and the Event is signaled.
// DNS_HOST_TO_ADDR_DATA
UINT32 IpCount;
EFI_IPv4_Address *IpList;
} DNS_HOST_TO_ADDR_DATA;
IpCount Number of the returned IP addresses.
IpList Pointer to the all the returned IP addresses.
// DNS_ADDR_TO_HOST_DATA
} DNS_ADDR_TO_HOST_DATA;
29.4. EFI DNSv4 Protocol 1263Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
HostName Pointer to the primary name for this host address. It’s the caller’s responsibility to free the response
memory.
// DNS_GENERAL_LOOKUP_DATA
UINTN RRCount;
DNS_RESOURCE_RECORD *RRList;
} DNS_GENERAL_LOOKUP_DATA;
RRCount Number of returned matching RRs.
RRList Pointer to the all the returned matching RRs. It’s caller responsibility to free the allocated memory to hold
the returned RRs.
// DNS_RESOURCE_RECORD
CHAR8 *QName;
UINT16 QType;
UINT16 QClass;
UINT32 TTL;
UINT16 DataLength;
CHAR8 *RData;
} DNS_RESOURCE_RECORD;
QName The Owner name.
QType The Type Code of this RR.
QClass The CLASS code of this RR.
TTL 32 bit integer which specify the time interval that the resource record may be cached before the source of the
information should again be consulted. Zero means this RR cannot be cached.
DataLength 16 big integer which specify the length of RData .
RData A string of octets that describe the resource, the format of this information varies according to QType and
QClass* difference.
TheHostNameToIp () function is used to translate the host name to host IP address. A type A query is used to get the
one or more IP addresses for this host.
EFI_SUCCESS The operation was queued successfully.
One or more of the following conditions is TRUE
Token. Event is. NULL
HostName isNULL .HostName string is unsupported format.
EFI_NO_MAPPING There’s no source address is available for use.

29.4. EFI DNSv4 Protocol 1264Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.33 – continued from previous page
29.4.6 EFI_DNS4_PROTOCOL.IpToHostName()
Summary
IPv4 address to host name translation also known as Reverse DNS lookup.
Prototype
typedef
(EFIAPI *EFI_DNS4_IP_TO_HOST_NAME) (
IN EFI_IPv4_ADDRESS IpAddress,
);
Parameter
IpAddress IP address.
Token Pointer to the caller-allocated completion used token to translate host address to host name. Type
EFI_DNS4_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions” of above HostNameToIp().
TheIpToHostName () function is used to translate the host address to host name. A type PTR query is used to get the
primary name of the host. Support of this function is optional.
EFI_UNSUPPORTED This function is not supported
Token . Event is. NULL
IpAddress is not valid IP address.
EFI_ALREADY_STARTED This Token is being used in another DNS session.
29.4. EFI DNSv4 Protocol 1265Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.4.7 EFI_DNS4_PROTOCOL.GeneralLookUp()
Summary
Retrieve arbitrary information from the DNS server.
Prototype
typedef
(EFIAPI *EFI_DNS4_GENERAL_LOOKUP) (
IN CHAR8 *QName,
IN UINT16 QType,
IN UINT16 QClass,
);
This GeneralLookUp() function retrieves arbitrary information from the DNS. The caller supplies a QNAME, QTYPE,
andQCLASS, and all of the matching RRs are returned. All RR content (e.g., TTL) was returned. The caller need
parse the returned RR to get required information. This function is optional.
QName Pointer to Query Name.
QType Query Type.
QClass Query Name.
Token Point to the caller-allocated completion token to retrieve arbitrary information. Type
EFI_DNS4_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions” of above HostNameToIp ().
EFI_UNSUPPORTED This function is not supported. Or the requested QType is not supported
QName isNULL .
29.4. EFI DNSv4 Protocol 1266Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.4.8 EFI_DNS4_PROTOCOL.UpdateDnsCache()
Summary
This function is used to update the DNS Cache.
Prototype
typedef
(EFIAPI *EFI_DNS4_UPDATE_DNS_CACHE) (
IN BOOLEAN Override,
IN EFI_DNS4_CACHE_ENTRY DnsCacheEntry
);
DeleteFlag IfFALSE, this function is to add one entry to the DNS Cache. If TRUE, this function will delete matching
DNS Cache entry.
Override IfTRUE, the matching DNS cache entry will be overwritten with the supplied parameter. If FALSE,
EFI_ACCESS_DENIED will be returned if the entry to be added is already exists.
DnsCacheEntry Pointer to DNS Cache entry.
TheUpdateDnsCache() function is used to add/delete/modify DNS cache entry. DNS cache can be normally dynam-
ically updated after the DNS resolve succeeds. This function provided capability to manually add/delete/modify the
DNS cache.
DnsCacheEntry.HostName isNULL .
DnsCacheEntry.IpAddress isNULL .
DnsCacheEntry.Timeout is zero.
EFI_ACCESS_DENIED The DNS cache entry already exists and Override is not TRUE .
29.4.9 EFI_DNS4_PROTOCOL.Poll()
Summary
Prototype
typedef
(EFIAPI *EFI_DNS4_POLL) (
29.4. EFI DNSv4 Protocol 1267Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_DNS4_PROTOCOL *This
);
EFI_NOT_STARTED This EFI DNS Protocol instance has not been started.
29.4.10 EFI_DNS4_PROTOCOL.Cancel()
Summary
Abort an asynchronous DNS operation, including translation between IP and Host, and general look up behavior.
Prototype
EFI Protocol
typedef
(EFIAPI *EFI_DNS4_CANCEL) (
);
EFI_DNS4_PROTOCOL.HostNameToIp() ,
EFI_DNS4_PROTOCOL.IpToHostName() or
EFI_DNS4_PROTOCOL.GeneralLookUp(). IfNULL , all pending tokens are aborted.
29.4. EFI DNSv4 Protocol 1268Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheCancel() function is used to abort a pending resolution request. After calling this function, Token.Status will be
set to EFI_ABORTED and then Token.Event will be signaled. If the token is not in one of the queues, which usually
means that the asynchronous operation has completed, this function will not signal the token and EFI_NOT_FOUND
EFI_SUCCESS The asynchronous DNS operation was aborted and Token->Event is sig-
naled.
EFI_NOT_STARTED This EFI DNS4 Protocol instance has not been started.
EFI_NOT_FOUND When Token is not NULL , and the asynchronous DNS operation was not
found in the transmit queue. It was either completed or was not issued by
HostNameToIp(), IpToHostName() orGeneralLookUp().
29.5 EFI DNSv6 Protocol
This section deﬁnes the EFI DNSv6 (Domain Name Service version 6) Protocol. It is split into the following two main
sections.
• DNSv6 Service Binding Protocol (DNSv6SB)
• DNSv6 Protocol (DNSv6)
29.5.1 DNS6 Service Binding Protocol
29.5.2 EFI_DNS6_SERVICE_BINDING_PROTOCOL
Summary
The DNSv6SB is used to locate communication devices that are supported by a DNS driver and to create and destroy
This section discusses the details that are speciﬁc to the DNSv6.
GUID
#define EFI_DNS6_SERVICE_BINDING_PROTOCOL_GUID \
{ 0x7f1647c8, 0xb76e, 0x44b2,\
{ 0xa5, 0x65, 0xf7, 0xf, 0xf1, 0x9c, 0xd1, 0x9e}}
such as BS->LocateHandleBuffer(), to search for devices that publish a DNSv6SB GUID. Each device with a published
DNSv6SB GUID supports DNSv6 and may be available for use.
After a successful call to the EFI_DNS6_SERVICE_BINDING_PROTOCOL.CreateChild() function, the child DNS
driver instance is in an un-conﬁgured state; it is not ready to resolve addresses.
EFI_DNS6_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_DNS6_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
29.5. EFI DNSv6 Protocol 1269Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NOTE :All the network addresses that are described in EFI_DNS6_PROTOCOL are stored in network byte order.
29.5.3 DNS6 Protocol
29.5.4 EFI_DNS6_PROTOCOL
Summary

Summary
This protocol provides the function to get the host name and address mapping, also provide pass through interface to
retrieve arbitrary information from DNSv6.
The EFI_DNS6_Protocol is primarily intended to retrieve host addresses using the standard DNS protocol (RFC3596),
As stated above, all instances of EFI_DNS6_Protocol will utilize a common DNS cache containing the successful
results of previous queries on any interface. However, it should be noted that every instance of EFI_DNS6_Protocol
GUID
#define EFI_DNS6_PROTOCOL_GUID \
{ 0xca37bc1f, 0xa327, 0x4ae9,\
{ 0x82, 0x8a, 0x8c, 0x40, 0xd8, 0x50, 0x6a, 0x17 }}
typedef struct _EFI_DNS6_PROTOCOL {
EFI_DNS6_GET_MODE_DATA GetModeData;
EFI_DNS6_CONFIGURE Configure;
EFI_DNS6_HOST_NAME_TO_IP HostNameToIp;
EFI_DNS6_IP_TO_HOST_NAME IpToHostName;
EFI_DNS6_GENERAL_LOOKUP GeneralLookUp;
EFI_DNS6_UPDATE_DNS_CACHE UpdateDnsCache;
EFI_DNS6_POLL Poll;
EFI_DNS6_CANCEL Cancel;
} EFI_DNS6_PROTOCOL;
29.5. EFI DNSv6 Protocol 1270Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.5.5 EFI_DNS6_PROTOCOL.GetModeData()
Summary
Retrieve mode data of this DNS instance.
Prototype
typedef
(EFIAPI *EFI_DNS6_GET_MODE_DATA)(
IN EFI_DNS6_PROTOCOL *This,
OUT EFI_DNS6_MODE_DATA *DnsModeData
);
Parameter
This Pointer to EFI_DNS6_PROTOCOL instance.
DnsModeData Pointer to the caller-allocated storage for the EFI_DNS6_MODE_DATA data.
// EFI_DNS6_MODE_DATA
EFI_DNS6_CONFIG_DATA DnsConfigData;
EFI_IPv6_ADDRESS *DnsServerList;
EFI_DNS6_CACHE_ENTRY *DnsCacheList;
} EFI_DNS6_MODE_DATA;
DnsConﬁgData The conﬁguration data of this instance. Type EFI_DNS6_CONFIG_DATA is deﬁned below.
DnsServerCount Number of conﬁgured DNS6 servers.
DnsServerList Pointer to common list of addresses of all conﬁgured DNS server used by EFI_DNS6_PROTOCOL
instances. List will include DNS servers conﬁgured by this or any other EFI_DNS6_PROTOCOL instance. The
storage for this list is allocated by the driver publishing this protocol, and must be freed by the caller
DnsCacheCount Number of DNS Cache entries. The DNS Cache is shared among all DNS6 instances.
// EFI_DNS6_CONFIG_DATA
EFI_IPv6_ADDRESS StationIp;
29.5. EFI DNSv6 Protocol 1271Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_DNS6_CONFIG_DATA;
IsDnsServerAuto IfTRUE, the DNS server conﬁguration will be retrieved from DHCP server. If
FALSE, the DNS server conﬁguration will be manually conﬁgured through call of DNSv6.Conﬁgure()
<http://www.iana.org/assignments/protocol-numbers>__ interface.
Protocol Use the protocol number deﬁned in Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the
heading “IANA Protocol Numbers”. Only TCP or UDP are supported, and other protocol values are invalid. An
implementation can choose to support only UDP, or both TCP and UDP.
StationIp The local IP address to use. Set to zero to let the underlying IPv6 driver choose a source address. If not
zero it must be one of the conﬁgured IP addresses in the underlying IPv6 driver.
DnsServerCount Count of the DNS servers. When used with GetModeData(), this ﬁeld is the count of originally
DnsServerList Pointer to DNS server list containing DnsServerListCount entries or NULL ifDnsServerListCount is
0. For Conﬁgure(), this will be NULL when there are no caller-supplied server addresses and the DNS instance
// EFI_DNS6_CACHE_ENTRY
EFI_IPv6_ADDRESS *IpAddress;
} EFI_DNS6_CACHE_ENTRY;
HostName Host name. This should be interpreted as Unicode characters.
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Table 29.39 – continued from previous page
EFI_INV ALID_PARAMETER This is NULL orDnsModeData isNULL .
EFI_OUT_OF_RESOURCE Failed to allocate needed resources.
29.5.6 EFI_DNS6_PROTOCOL.Conﬁgure()
Summary
Conﬁgure this DNS instance
Prototype
typedef
(EFIAPI *EFI_DNS6_CONFIGURE)(
IN EFI_DNS6_CONFIG_DATA *DnsConfigData
);
TheConﬁgure() function is used to set and change the conﬁguration data for this EFI DNSv6 Protocol driver instance.
Reset the DNS instance if DnsConﬁgData isNULL .
DnsConﬁgData Pointer to the conﬁguration data structure. Type
EFI_DNS6_CONFIG_DATA is deﬁned in
EFI_DNS6_PROTOCOL.GetModeData() . All associated storage to be allocated and released by caller.
The StationIp address provided in DnsConﬁgData is not zero and not a
valid unicast.
DnsServerList isNULL while DnsServerListCount is not ZERO.
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI DNSv6 Protocol
29.5. EFI DNSv6 Protocol 1273Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.5.7 EFI_DNS6_PROTOCOL.HostNameToIp()
Summary
Host name to host address translation
Prototype
typedef
(EFIAPI *EFI_DNS6_HOST_NAME_TO_IP) (
IN EFI_DNS6_COMPLETION_TOKEN *Token
);
Parameter

Summary
Prototype
typedef
);
Parameter
Token Point to the completion token to translate host name to host address. Type
EFI_DNS6_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions” below.
// EFI_DNS6_COMPLETION_TOKEN
union {
DNS6_HOST_TO_ADDR_DATA *H2AData;
DNS6_ADDR_TO_HOST_DATA *A2HData;
DNS6_GENERAL_LOOKUP_DATA *GLookupData;
} RspData;
} EFI_DNS6_COMPLETION_TOKEN;
Event This Event will be signaled after the Status ﬁeld is updated by the EFI DNSv6 protocol driver. The type of
Event must be EFI_NOTIFY_SIGNAL.
29.5. EFI DNSv6 Protocol 1274Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
RetryCount The parameter conﬁgured through DNSv6.Conﬁgure() interface. Retry number if no response received
after RetryInterval.
RetryInterval The parameter conﬁgured through DNSv6.Conﬁgure() interface. Minimum interval of retry is 2 sec-
ond. If the retry interval is less than 2 second, then use the 2 second.
DNS6_HOST_TO_ADDR_DATA. Type DNS6_HOST_TO_ADDR_DATA is deﬁned below.
DNS6_ADDR_TO_HOST_DATA. Type DNS6_ADDR_TO_HOST_DATA is deﬁned below.
DNS6_GENERAL_LOOKUP_DATA. Type DNS6_GENERAL_LOOKUP_DATA is deﬁned below.
EFI_DNS6_COMPLETION_TOKEN structures are used for host name to address translation, host address to name
translation and general lookup operation, the Event ﬁled must be ﬁlled by the EFI DNSv6 Protocol Client. If the
caller attempts to reuse Token before the completion event is triggered or canceled, EFI_ALREADY_STARTED will be
returned. After the operation completes, the EFI DNSv6 protocol driver ﬁll in the RspData andStatus ﬁeld and the
Event is signaled.
// DNS6_HOST_TO_ADDR_DATA
EFI_IPv6_ADDRESS *IpList;
} DNS6_HOST_TO_ADDR_DATA;
IpCount Number of the returned IP address
IpList Pointer to the all the returned IP address
// DNS6_ADDR_TO_HOST_DATA
} DNS6_ADDR_TO_HOST_DATA;
memory.
// DNS6_GENERAL_LOOKUP_DATA
DNS6_RESOURCE_RECORD *RRList;
} DNS6_GENERAL_LOOKUP_DATA;
the returned RRs
// DNS6_RESOURCE_RECORD
29.5. EFI DNSv6 Protocol 1275Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} DNS6_RESOURCE_RECORD;
QType The Type Code of this RR
QClass difference.
TheHostNameToIp () function is used to translate the host name to host IP address. A type AAAA record query is
used to get the one or more IPv6 addresses for this host.
Token. Event is NULL .
HostName isNULL or buffer contained unsupported characters.
29.5.8 EFI_DNS6_PROTOCOL.IpToHostName()
Summary
Host address to host name translation
Prototype
typedef
(EFIAPI *EFI_DNS6_IP_TO_HOST_NAME) (
IN EFI_IPv6_ADDRESS IpAddress,
29.5. EFI DNSv6 Protocol 1276Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
Parameter
Token Point to the completion token to translate host address to host name. Type
EFI_DNS6_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions” of above HostNameToIp ().
primary name of the host. Implementation can choose to support this function or not.
Token .Event is.NULL
IpAddress is not valid IP address .
29.5.9 EFI_DNS6_PROTOCOL.GeneralLookUp()
Summary
This function provides capability to retrieve arbitrary information from the DNS server.
Prototype
typedef
(EFIAPI *EFI_DNS6_GENERAL_LOOKUP) (
);
parse the returned RR to get required information. The function is optional. Implementation can choose to support it
or not.
29.5. EFI DNSv6 Protocol 1277Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Token Point to the completion token to retrieve arbitrary information. Type EFI_DNS6_COMPLETION_TOKEN is
deﬁned in “Related Deﬁnitions” of above HostNameToIp ().
29.5.10 EFI_DNS6_PROTOCOL.UpdateDnsCache()
Summary
This function is to update the DNS Cache.
Prototype
typedef
(EFIAPI *EFI_DNS6_UPDATE_DNS_CACHE) (
IN EFI_DNS6_CACHE_ENTRY DnsCacheEntry
);
DeleteFlag IfFALSE , this function is to add one entry to the DNS Cache. If TRUE , this function will delete matching
Override IfTRUE , the matching DNS cache entry will be overwritten with the supplied parameter. If FALSE ,
EFI_ACCESS_DENIED will be returned if the entry to be added is already existed.

Summary
Prototype
typedef
);
29.5. EFI DNSv6 Protocol 1278Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DNS cache.
DnsCacheEntry.Timeout isZERO .
29.5.11 EFI_DNS6_PROTOCOL.POLL()
Summary
Prototype
typedef
(EFIAPI *EFI_DNS6_POLL) (
IN EFI_DNS6_PROTOCOL *This
);
29.5. EFI DNSv6 Protocol 1279Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.5.12 EFI_DNS6_PROTOCOL.Cancel()
typedef
(EFIAPI *EFI_DNS6_CANCEL) (
);
EFI_DNS6_PROTOCOL.HostNameToIp (),
EFI_DNS6_PROTOCOL.IpToHostName() or
EFI_DNS6_PROTOCOL.GeneralLookUp(). IfNULL , all pending tokens are aborted.
naled.
EFI_NOT_STARTED This EFI DNS6 Protocol instance has not been started.
EFI_NOT_FOUND When Token is not NULL and the asynchronous DNS operation was not
found in the transmit queue, It is either completed or was not issued by
29.6 EFI HTTP Protocols
This section deﬁnes the EFI HTTP Protocol interface. It is split into the following two main sections.
• HTTP Service Binding Protocol (HTTPSB)
• HTTP Protocol (HTTP)
29.6. EFI HTTP Protocols 1280Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.6.1 HTTP Service Binding Protocol
29.6.1.1 EFI_HTTP_SERVICE_BINDING_PROTOCOL
Summary
The HTTPSB is used to locate communication devices that are supported by a HTTP driver and to create and destroy
instances of the HTTP child protocol driver.
This section discusses the details that are speciﬁc to the HTTP.
GUID
#define EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID \
{0xbdc8e6af, 0xd9bc, 0x4379,\
{0xa7, 0x2a, 0xe0, 0xc4, 0xe7, 0x5d, 0xae, 0x1c}}
A network application (or driver) that requires HTTP communication service can use one of the protocol handler
services, such as BS->LocateHandleBuffer(), to search for devices that publish a HTTPSB GUID. Each device with a
published HTTP SB GUID supports HTTP Service Binding Protocol and may be available for use.
After a successful call to the EFI_HTTP_SERVICE_BINDING_PROTOCOL.CreateChild() function, the child HTTP
driver instance is in an uninitialized state; it is not ready to initiate HTTP data transfer.
EFI_HTTP_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the E
FI_HTTP_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
29.6.2 EFI HTTP Protocol Speciﬁc Deﬁnitions
29.6.3 EFI_HTTP_PROTOCOL
Protocol GUID
#define EFI_HTTP_PROTOCOL_GUID \
{0x7A59B29B, 0x910B, 0x4171,\
{0x82, 0x42, 0xA8, 0x5A, 0x0D, 0xF2, 0x5B, 0x5B}}
typedef struct _EFI_HTTP_PROTOCOL {
EFI_HTTP_GET_MODE_DATA GetModeData;
EFI_HTTP_CONFIGURE Configure;
EFI_HTTP_REQUEST Request;
EFI_HTTP_CANCEL Cancel;
EFI_HTTP_RESPONSE Response;
EFI_HTTP_POLL Poll;
} EFI_HTTP_PROTOCOL;
GetModeData Gets the current operational status. See the GetModeData() function description.
Conﬁgure Initialize, change, or reset operational settings in the EFI HTTP protocol instance. See Conﬁgure() for
29.6. EFI HTTP Protocols 1281Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Request Queue a request token into the transmit queue. This function is a non-blocking operation. See Request() for
Cancel Abort a pending request or response operation. See Cancel() for function description.
Response Queue a response token into the receive queue. This function is a non-blocking operation. See Response()
for function description.
Poll Poll to receive incoming HTTP response and transmit outgoing HTTP request. See Poll() for function description.
The EFI HTTP protocol is designed to be used by EFI drivers and applications to create and transmit HTTP Requests,
as well as handle HTTP responses that are returned by a remote host. This EFI protocol uses and relies on an underlying
EFI TCP protocol.
29.6.4 EFI_HTTP_PROTOCOL.GetModeData()
Summary
Returns the operational parameters for the current HTTP child instance.
typedef
(EFIAPI *EFI_HTTP_GET_MODE_DATA)(
IN EFI_HTTP_PROTOCOL *This,
OUT EFI_HTTP_CONFIG_DATA *HttpConfigData
);
This Pointer to EFI_HTTP_PROTOCOL instance.
HttpConﬁgData Pointer to the buffer for operational parameters of this HTTP instance. Type
EFI_HTTP_CONFIG_DATA is deﬁned in “Related Deﬁnitions” below. It is the responsibility of the
caller to allocate the memory for HttpConﬁgData and HttpConﬁgData->AccessPoint.IPv6Node/IPv4Node.
In fact, it is recommended to allocate sufﬁcient memory to record IPv6Node since it is big enough for all
possibilities.
TheGetModeData() function is used to read the current mode data (operational parameters) for this HTTP protocol
instance.
EFI_SUCCESS Operation succeeded
HttpConﬁgData isNULL .
Http ConﬁgData->AccessPoint.IPv4Node or
Http ConﬁgData->AccessPoint.IPv6Node isNULL
EFI_NOT_STARTED This EFI HTTP Protocol instance has not been started.
29.6. EFI HTTP Protocols 1282Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_HTTP_CONFIG_DATA
EFI_HTTP_VERSION HttpVersion;
UINT32 TimeOutMillisec;
BOOLEAN LocalAddressIsIPv6;
union {
EFI_HTTPv4_ACCESS_POINT *IPv4Node;
EFI_HTTPv6_ACCESS_POINT *IPv6Node;
} AccessPoint;
} EFI_HTTP_CONFIG_DATA;
HttpVersion HTTP version that this instance will support.
TimeOutMillsec Time out (in milliseconds) when blocking for requests.
LocalAddressIsIPv6 Deﬁnes behavior of EFI DNS and TCP protocols consumed by this instance. If FALSE,
this instance will use EFI_DNS4_PROTOCOL andEFI_TCP4_PROTOCOL. IfTRUE , this instance will use
EFI_DNS6_PROTOCOL andEFI_TCP6_PROTOCOL.
IPv4Node When LocalAddressIsIPv6 is FALSE, this points to the local address, subnet, and port used by the under-
lying TCP protocol.
IPv6Node When LocalAddressIsIPv6 isTRUE , this points to the local IPv6 address and port used by the underlying
TCP protocol.
// EFI_HTTP_VERSION
HttpVersion10,
HttpVersion11,
HttpVersionUnsupported
} EFI_HTTP_VERSION;
// EFI_HTTPv4_ACCESS_POINT

EFI_IPv4_ADDRESS LocalAddress;
EFI_IPv4_ADDRESS LocalSubnet;
} EFI_HTTPv4_ACCESS_POINT;
UseDefaultAddress Set to TRUE to instruct the EFI HTTP instance to use the default address information in every
TCP connection made by this instance. In addition, when set to TRUE ,LocalAddress andLocalSubnet are
ignored.
LocalAddress IfUseDefaultAddress is set to FALSE , this deﬁnes the local IP address to be used in every TCP
connection opened by this instance.
LocalSubnet IfUseDefaultAddress is set to FALSE , this deﬁnes the local subnet to be used in every TCP connection
opened by this instance.
LocalPort This deﬁnes the local port to be used in every TCP connection opened by this instance.
29.6. EFI HTTP Protocols 1283Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_HTTPv6_ACCESS_POINT
EFI_IPv6_ADDRESS LocalAddress;
} EFI_HTTPv6_ACCESS_POINT;
LocalAddress Local IP address to be used in every TCP connection opened by this instance.
LocalPort Local port to be used in every TCP connection opened by this instance.
29.6.5 EFI_HTTP_PROTOCOL.Conﬁgure()
Summary
Initialize or brutally reset the operational parameters for this EFI HTTP instance.
typedef
(EFIAPI *EFI_HTTP_CONFIGURE)(
IN EFI_HTTP_CONFIG_DATA *HttpConfigData OPTIONAL
);
HttpConﬁgData Pointer to the conﬁgure data to conﬁgure the instance.
• When HttpConﬁgData is not NULL Initialize this EFI HTTP instance by conﬁguring timeout, local address,
port, etc.
• When HttpConﬁgData isNULL, reset this EFI HTTP instance by closing all active connections with remote
hosts, canceling all asynchronous tokens, and ﬂush request and response buffers without informing the appro-
priate hosts.
No other EFI HTTP function can be executed by this instance until the Conﬁgure() function is executed and returns
successfully.
EFI_SUCCESS Operation succeeded.
29.6. EFI HTTP Protocols 1284Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 29.48 – continued from previous page
HttpConﬁgData->LocalAddressIsIPv6 isFALSE and
HttpConﬁgData->AccessPoint.IPv4Node isNULL .
HttpConﬁgData->LocalAddressIsIPv6 isTRUE and
HttpConﬁgData->AccessPoint.IPv6Node isNULL .
EFI_ALREADY_STARTED Reinitialize this HTTP instance without calling Conﬁgure() with NULL to
reset it.
EFI_OUT_OF_RESOURCES Could not allocate enough system resources when executing Conﬁgure().
EFI_UNSUPPORTED One or more options in ConﬁgData are not supported in the implementation.
29.6.6 EFI_HTTP_PROTOCOL.Request()
Summary
TheRequest() function queues an HTTP request to this HTTP instance, similar to* Transmit() function in the EFI TCP
driver. When the HTTP request is sent successfully, or if there is an error, Status in token will be updated and* Event
will be signaled.
Typedef
(EFIAPI *EFI_HTTP_REQUEST) (
IN EFI_HTTP_TOKEN *Token
);
Token Pointer to storage containing HTTP request token. Type EFI_HTTP_TOKEN is deﬁned in “Related Deﬁni-
// EFI_HTTP_TOKEN
EFI_HTTP_MESSAGE *Message;
} EFI_HTTP_TOKEN;
Event This Event will be signaled after the Status ﬁeld is updated by the EFI HTTP Protocol driver. The type of
Status Status will be set to one of the following value if the HTTP request is successfully sent or if an unexpected
error occurs:
29.6. EFI HTTP Protocols 1285Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS : The HTTP request was successfully sent to the remote host.
EFI_HTTP_ERROR : The response message was successfully received but contains a HTTP error. The
response status code is returned in Token.
EFI_ABORTED : The HTTP request was canceled by the caller and removed from the transmit queue.
EFI_TIMEOUT : The HTTP request timed out before reaching the remote host.
Message Pointer to storage containing HTTP message data.
// EFI_HTTP_MESSAGE
union {
EFI_HTTP_REQUEST_DATA *Request;
EFI_HTTP_RESPONSE_DATA *Response;
} Data;
UINTN HeaderCount;
EFI_HTTP_HEADER *Headers;
UINTN BodyLength;
VOID *Body;
} EFI_HTTP_MESSAGE;
Request When the token is used to send a HTTP request, Request is a pointer to storage that contains such data as
URL and HTTP method.
Response When used to await a response, Response points to storage containing HTTP response status code.
HeaderCount Number of HTTP header structures in Headers list. On request, this count is provided by the caller.
On response, this count is provided by the HTTP driver.
Headers Array containing list of HTTP headers. On request, this array is populated by the caller. On response, this
array is allocated and populated by the HTTP driver. It is the responsibility of the caller to free this memory on
both request and response.
BodyLength Length in bytes of the HTTP body. This can be zero depending on the HttpMethod type. Body Body
associated with the HTTP request or response. This can be NULL depending on the HttpMethod type.
The HTTP driver will prepare a request string from the information contained in and queue it to the underlying TCP
instance to be sent to the remote host. Typically, all ﬁelds in the structure will contain content (except Body and
BodyLength when HTTP method is not POST or PUT), but there is a special case when using PUT or POST to send
large amounts of data. Depending on the size of the data, it may not be able to be stored in a contiguous block of
memory, so the data will need to be provided in chunks. In this case, if Body is not NULL andBodyLength is non-zero
and all other ﬁelds are NULL or0,the HTTP driver will queue the data to be sent to the last remote host that a token was
successfully sent. If no previous token was sent successfully, this function will return EFI_INVALID_PARAMETER.
The HTTP driver is expected to close existing (if any) underlying TCP instance and create new TCP instance if
the host name in the request URL is different from previous calls to Request(). This is consistent with RFC 2616
recommendation that HTTP clients should attempt to maintain an open TCP connection between client and host.
// EFI_HTTP_REQUEST_DATA
EFI_HTTP_METHOD Method;
CHAR16 *Url;
} EFI_HTTP_REQUEST_DATA;
29.6. EFI HTTP Protocols 1286Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Method The HTTP method (e.g. GET, POST) for this HTTP Request.
Url The URI of a remote host. From the information in this ﬁeld, the HTTP instance will be able to determine whether
to use HTTP or HTTPS and will also be able to determine the port number to use. If no port number is speciﬁed,
port 80 (HTTP) is assumed. See RFC 3986 for more details on URI syntax.
// EFI_HTTP_METHOD
HttpMethodGet,
HttpMethodPost,
HttpMethodPatch,
HttpMethodOptions,
HttpMethodConnect,
HttpMethodHead,
HttpMethodPut,
HttpMethodDelete,
HttpMethodTrace,
HttpMethodMax
} EFI_HTTP_METHOD;
// EFI_HTTP_RESPONSE_DATA
EFI_HTTP_STATUS_CODE StatusCode;
} EFI_HTTP_RESPONSE_DATA;
StatusCode Response status code returned by the remote host.
// EFI_HTTP_HEADER
CHAR8 *FieldName;
CHAR8 *FieldValue;
} EFI_HTTP_HEADER;
FieldName NULL terminated string which describes a ﬁeld name. See RFC 2616 Section 14 for detailed information
about ﬁeld names.
FieldValue NULL terminated string which describes the corresponding ﬁeld value. See RFC 2616 Section 14 for
detailed information about ﬁeld values.
HTTP_STATUS_UNSUPPORTED_STATUS = 0,
HTTP_STATUS_100_CONTINUE,
HTTP_STATUS_101_SWITCHING_PROTOCOLS,
HTTP_STATUS_200_OK,
HTTP_STATUS_201_CREATED,
HTTP_STATUS_202_ACCEPTED,

HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION,
HTTP_STATUS_204_NO_CONTENT,
HTTP_STATUS_205_RESET_CONTENT,
HTTP_STATUS_206_PARTIAL_CONTENT,
HTTP_STATUS_300_MULTIPLE_CHOICES,
29.6. EFI HTTP Protocols 1287Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
HTTP_STATUS_301_MOVED_PERMANENTLY,
HTTP_STATUS_302_FOUND,
HTTP_STATUS_303_SEE_OTHER,
HTTP_STATUS_304_NOT_MODIFIED,
HTTP_STATUS_305_USE_PROXY,
HTTP_STATUS_307_TEMPORARY_REDIRECT,
HTTP_STATUS_400_BAD_REQUEST,
HTTP_STATUS_401_UNAUTHORIZED,
HTTP_STATUS_402_PAYMENT_REQUIRED,
HTTP_STATUS_403_FORBIDDEN,
HTTP_STATUS_404_NOT_FOUND,
HTTP_STATUS_405_METHOD_NOT_ALLOWED,
HTTP_STATUS_406_NOT_ACCEPTABLE,
HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED,
HTTP_STATUS_408_REQUEST_TIME_OUT,
HTTP_STATUS_409_CONFLICT,
HTTP_STATUS_410_GONE,
HTTP_STATUS_411_LENGTH_REQUIRED,
HTTP_STATUS_412_PRECONDITION_FAILED,
HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE,
HTTP_STATUS_414_REQUEST_URI_TOO_LARGE,
HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE,
HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED,
HTTP_STATUS_417_EXPECTATION_FAILED,
HTTP_STATUS_500_INTERNAL_SERVER_ERROR,
HTTP_STATUS_501_NOT_IMPLEMENTED,
HTTP_STATUS_502_BAD_GATEWAY,
HTTP_STATUS_503_SERVICE_UNAVAILABLE,
HTTP_STATUS_504_GATEWAY_TIME_OUT,
HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED,
HTTP_STATUS_308_PERMANENT_REDIRECT
} EFI_HTTP_STATUS_CODE;
EFI_SUCCESS Outgoing data was processed.
EFI_TIMEOUT Data was dropped out of the transmit or receive queue.
Token->Message isNULL .
Token->Message->Body is not NULL ,
Token->Message->BodyLength is non-zero, and
Token->Message->Data isNULL , but a previous call to Request() has not
been completed successfully.
EFI_OUT_OF_RESOURCES Could not allocate enough system resources.
EFI_UNSUPPORTED The HTTP method is not supported in current implementation.
29.6. EFI HTTP Protocols 1288Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.6.7 EFI_HTTP_PROTOCOL.Cancel()
Summary
Abort an asynchronous HTTP request or response token.
typedef
(EFIAPI *EFI_HTTP_CANCEL)(
IN EFI_HTTP_TOKEN *Token,
);
Token Point to storage containing HTTP request or response token.
TheCancel() function aborts a pending HTTP request or response transaction. If Token is not NULL and the token is in
transmit or receive queues when it is being cancelled, its Token->Status will be set to EFI_ABORTED and then Token-
>Event will be signaled. If the token is not in one of the queues, which usually means that the asynchronous operation
has completed, EFI_NOT_FOUND is returned. If Token isNULL , all asynchronous tokens issued by Request() or
Response() will be aborted.
EFI_SUCCESS Request and Response queues are successfully ﬂushed.
EFI_NOT_FOUND The asynchronous request or response token is not found.
29.6.8 EFI_HTTP_PROTOCOL.Response()
Summary
The Response() function queues an HTTP response to this HTTP instance, similar to Receive() function in the EFI
TCP driver. When the HTTP response is received successfully, or if there is an error, Status in token will be updated
andEvent will be signaled.
typedef
(EFIAPI *EFI_HTTP_RESPONSE) (
);
29.6. EFI HTTP Protocols 1289Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Token Pointer to storage containing HTTP response token. See Request() function for the deﬁnition of
EFI_HTTP_TOKEN.
The HTTP driver will queue a receive token to the underlying TCP instance. When data is received in the underlying
TCP instance, the data will be parsed and Token will be populated with the response data. If the data received from the
remote host contains an incomplete or invalid HTTP header, the HTTP driver will continue waiting (asynchronously)
for more data to be sent from the remote host before signaling Event in Token.
It is the responsibility of the caller to allocate a buffer for Body and specify the size in BodyLength. If the remote host
provides a response that contains a content body, up to BodyLength bytes will be copied from the receive buffer into
Body andBodyLength will be updated with the amount of bytes received and copied to Body. This allows the client
to download a large ﬁle in chunks instead of into one contiguous block of memory. Similar to HTTP request, if Body
is not NULL andBodyLength is non-zero and all other ﬁelds are NULL or0,the HTTP driver will queue a receive
token to underlying TCP instance. If data arrives in the receive buffer, up to BodyLength bytes of data will be copied
toBody. The HTTP driver will then update BodyLength with the amount of bytes received and copied to Body.
If the HTTP driver does not have an open underlying TCP connection with the host speciﬁed in the response URL,
Response() will return EFI_ACCESS_DENIED. This is consistent with RFC 2616 recommendation that HTTP clients
should attempt to maintain an open TCP connection between client and host.
EFI_SUCCESS Allocation succeeded
EFI_NOT_STARTED This EFI HTTP Protocol instance has not been initialized.
Token->Message->Body is not NULL, Token->Message->BodyLength is
non-zero, and Token->Message->Data isNULL, but a previous call to
Response() has not been completed successfully
EFI_ACCESS_DENIED An open TCP connection is not present with the host speciﬁed by response
URL.
29.6.9 EFI_HTTP_PROTOCOL.Poll()
typedef
(EFIAPI *EFI_HTTP_POLL) (
IN EFI_HTTP_PROTOCOL *This
);
29.6. EFI HTTP Protocols 1290Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
between the communication devices and the transmit and receive queues. In some systems, the periodic timer event
in the managed network driver may not poll the underlying communications device fast enough to transmit and/or
receive all data packets without missing incoming packets or dropping outgoing packets. Drivers and applications that
are experiencing packet loss should try calling the Poll() function more often.
29.6.9.1 Usage Examples
Here is an example of a client making a HTTP Request to download a driver bundle from Intel Driver Download
Center. This example includes sample code for how to support a client that is behind a HTTP proxy server.
#include <Uefi.h>
#include <HttpProtocol.h>
#define BUFFER_SIZE 0x100000
BOOLEAN gRequestCallbackComplete = FALSE;
BOOLEAN gResponseCallbackComplete = FALSE;
VOID
EFIAPI
RequestCallback(
)
{
gRequestCallbackComplete = TRUE;
}
VOID
EFIAPI
ResponseCallback(
)
{
gResponseCallbackComplete = TRUE;
}
EFIAPI
HttpClientMain(
)
{
EFI_SERVICE_BINDING_PROTOCOL *ServiceBinding;
EFI_HANDLE *Handle;
29.6. EFI HTTP Protocols 1291Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_HTTP_PROTOCOL *HttpProtocol;
EFI_HTTP_CONFIG_DATA ConfigData;
EFI_HTTPv4_ACCESS_POINT IPv4Node;
EFI_HTTP_REQUEST_DATA RequestData;
EFI_HTTP_HEADER RequestHeader;
EFI_HTTP_MESSAGE RequestMessage;
EFI_HTTP_TOKEN RequestToken;
EFI_HTTP_RESPONSE_DATA ResponseData;
EFI_HTTP_MESSAGE ResponseMessage;
EFI_HTTP_TOKEN ResponseToken;
UINT8 *Buffer;
EFI_TIME Baseline;
EFI_TIME Current;
UINTN Timer;
UINTN ContentDownloaded;
UINTN ContentLength;
BUFFER_SIZE,
(VOID**)&Buffer
);
// TODO: Handle error...
Status = gBS->LocateProtocol(
&gEfiHttpServiceBindingProtocolGuid,
NULL,
&ServiceBinding
);

)
{
);
NULL,
);
Status = ServiceBinding->CreateChild(ServiceBinding, &Handle);
Status = gBS->HandleProtocol(Handle, &gEfiHttpProtocolGuid, &HttpProtocol);
ConfigData.HttpVersion = HttpVersion11;
ConfigData.TimeOutMillisec = 0; // Indicates default timeout period
ConfigData.LocalAddressIsIPv6 = FALSE;
ZeroMem(&IPv4Node, sizeof(IPv4Node));
IPv4Node.UseDefaultAddress = TRUE; // Obtain IP address from DHCP
ConfigData.AccessPoint.IPv4Node = &IPv4Node;
// The HTTP driver must first be configured before requests orresponses can
// be processed. This isthe same forother network protocols such asTCP.
Status = HttpProtocol->Configure(HttpProtocol, &ConfigData);
// This request message isinitialized to request a sample driver bundle
//from Intel 's driver download center. To download a file, we use HTTP GET.
RequestData.Method = HttpMethodGet;
// URI where the file islocated that we want to download.
RequestData.Url = L" \\
29.6. EFI HTTP Protocols 1292Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
http://downloadmirror.intel.com/23418/a08/ FYKH-Win8.1-64bit-Driver-Bundle-Sep2014.zip
˓→";
// This header tells the HTTP driver to relay the HTTP request
// via a proxy server. This header isjust used to demonstrate
// how to relay through a proxy withthis driver. The method
//forobtaining the proxy address isup to the client. The
// HTTP driver does NOT resolve this on its own.
RequestHeader.FieldName = "Host";
RequestHeader.FieldValue = "my.proxyserver.com";
// Message format just contains a pointer to the request data
//andbody info, ifapplicable. In the case of HTTP GET, body
//is notrelevant.
RequestMessage.Data.Request = &RequestData;
// Just one header being provided inthe HTTP message.
RequestMessage.HeaderCount = 1;
RequestMessage.Headers = &RequestHeader;
RequestMessage.BodyLength = 0;
RequestMessage.Body = NULL;
// Token format issimilar to the token format inEFI TCP protocol.
RequestToken.Event = NULL;
Status = gBS->CreateEvent(
EVT_NOTIFY_SIGNAL,
TPL_CALLBACK,
RequestCallback,
NULL,
&RequestToken.Event
);
RequestToken.Status = EFI_SUCCESS;
RequestToken.Message = &RequestMessage;
gRequestCallbackComplete = FALSE;
// Finally, make HTTP request.
Status = HttpProtocol->Request(HttpProtocol, &RequestToken);
Status = gRT->GetTime(&Baseline, NULL);
// Optionally, wait for a certain amount of time before cancelling
// the request. In this case, we'll allow the network stack 10
// seconds to send the request successfully.
for (Timer = 0; !gRequestCallbackComplete && Timer < 10; ) {
// Give the HTTP driver some motivation...
HttpProtocol->Poll(HttpProtocol);
// In practice, a call to GetTime() only fails when the total
// elapsed time between the last call to to GetTime() is less
// than the resolution of one tick (e.g. 1 second, depending
// on capabilities of hardware). We only care to check the time
// when the call succeeds.
29.6. EFI HTTP Protocols 1293Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
if (!EFI_ERROR(gRT->GetTime(&Current, NULL)) &&
Current.Second != Baseline.Second)
{
// One second has passed, so update Current time and
// increment the counter.
Baseline = Current;
++Timer;
}
}
// Cancel request if we did not get a notification from the HTTP
// driver in a timely manner.
if (!gRequestCallbackComplete) {
Status = HttpProtocol->Cancel(HttpProtocol, &RequestToken);
// TODO: Handle error and exit condition...
}
// Assuming we succeed in our request...
// This response message is different that request in that the
// HTTP driver is responsible for allocating the headers during
// a response instead of the caller.
ResponseData.StatusCode = HTTP_STATUS_UNSUPPORTED_STATUS;
ResponseMessage.Data.Response = &ResponseData;
// HeaderCount will be updated by the HTTP driver on response.
ResponseMessage.HeaderCount = 0;
// Headers will be populated by the driver on response.
ResponseMessage.Headers = NULL;
// BodyLength maximum limit is defined by the caller. On response,
// the HTTP driver will update BodyLength to the total number of
// bytes copied to Body. This number will never exceed the initial
// maximum provided by the caller.
ResponseMessage.BodyLength = BUFFER_SIZE;
ResponseMessage.Body = Buffer;
// Token format is similar to the token format in EFI TCP protocol.
ResponseToken.Event = NULL;
NULL,
&ResponseToken,
&ResponseToken.Event
);
ResponseToken.Status = EFI_SUCCESS;
ResponseToken.Message = &ResponseMessage;
gResponseCallbackComplete = FALSE;
Status = HttpProtocol->Response(HttpProtocol, &ResponseToken);
29.6. EFI HTTP Protocols 1294Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// Optionally, wait for a certain amount of time before cancelling.
for (Timer = 0; !gResponseCallbackComplete && Timer < 10; ) {
{
++Timer;
}
}
// Remove response token from queue if we did not get a notification
// from the remote host in a timely manner.
if (!gResponseCallbackComplete) {
Status = HttpProtocol->Cancel(HttpProtocol, &ResponseToken);
}
// Assuming we successfully received a response...
for (Index = 0; Index < ResponseMessage.HeaderCount; ++Index) {
// We can parse the length of the file from the ContentLength header.
if (!AsciiStriCmp(ResponseMessage.Headers[Index].FieldName, "Content-Length")) {
ContentLength =
AsciiStrDecimalToUintn(ResponseMessage.Headers[Index].FieldValue);
}
}
ContentDownloaded = ResponseMessage.BodyLength;
// TODO:
// Downloaded data exists in Buffer[0..ResponseMessage.BodyLength].
// At this point, depending on business use case, the content can
// be written to a file, stored on the heap, etc.
while (ContentDownloaded < ContentLength) {
// If we make it here, we haven't yet downloaded the whole file and
// need to keep going.
ResponseMessage.Data.Response = NULL;
if (ResponseMessage.Headers != NULL) {
// No sense hanging onto this anymore.
FreePool(ResponseMessage.Headers);
}
ZeroMem(Buffer, BUFFER_SIZE);
// ResponseMessage.Body still points to Buffer.
// The HTTP driver accepts a token where Data, Headers, and
// HeaderCount are all 0 or NULL. The driver will wait for a
// response from the last remote host which a transaction occurred
// and copy the response directly into Body, updating BodyLength
// with the total amount copied (downloaded).
29.6. EFI HTTP Protocols 1295Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
{
++Timer;
}
}
}
ContentDownloaded += ResponseMessage.BodyLength;
// TODO:
// Append data to a file, heap memory, etc.
}
// Perform any necessary cleanup and handling of downloaded file
// assuming we succeeded at downloading the content. Depending on
// where the data was stored as per business need, that data can
// be consumed at this point. For example, if the data was stored
// to a file system, the file can be opened and consumed.
}
29.6.10 HTTP Utilities Protocol
Summary
This section deﬁnes the EFI HTTP Utilities Protocol interface.
29.6.11 EFI_HTTP_UTILITIES_PROTOCOL
#define EFI_HTTP_UTILITIES_PROTOCOL_GUID \
{ 0x3E35C163, 0x4074, 0x45DD,\
{ 0x43, 0x1E, 0x23, 0x98, 0x9D, 0xD8, 0x6B, 0x32 }}
29.6. EFI HTTP Protocols 1296Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct _EFI_HTTP_UTILITIES_PROTOCOL {
EFI_HTTP_UTILS_BUILD Build;

// TODO:
}
}
Summary
EFI_HTTP_UTILS_PARSE Parse;
} EFI_HTTP_UTILITIES_PROTOCOL;
Build Create HTTP header based on a combination of seed header, ﬁelds to delete, and ﬁelds to append.
Parse Parses HTTP header and produces an array of key/value pairs.
The EFI HTTP utility protocol is designed to be used by EFI drivers and applications to parse HTTP headers from
a byte stream. This driver is neither dependent on network connectivity, nor the existence of an underlying network
infrastructure.
29.6.12 EFI_HTTP_UTILITIES_PROTOCOL.Build()
Summary
Provides ability to add, remove, or replace HTTP headers in a raw HTTP message.
typedef
(EFIAPI *EFI_HTTP_UTILS_BUILD) (
IN EFI_HTTP_UTILITIES_PROTOCOL *This,
IN UINTN SeedMessageSize
IN VOID *SeedMessage, OPTIONAL
IN UINTN DeleteCount
IN CHAR8 *DeleteList[], OPTIONAL
IN UINTN AppendCount
IN EFI_HTTP_HEADER *AppendList[], OPTIONAL
OUT UINTN *NewMessageSize,
OUT VOID **NewMessage,
);
This Pointer to EFI_HTTP_UTILITIES_PROTOCOL instance.
SeedMessageSize Size of the initial HTTP header. This can be zero.
SeedMessage Initial HTTP header to be used as a base for building a new HTTP header. If NULL, SeedMessageSize
DeleteCount Number of null-terminated HTTP header ﬁeld names in DeleteList.
DeleteList List of null-terminated HTTP header ﬁeld names to remove from SeedMessage. Only the ﬁeld names are
in this list because the ﬁeld values are irrelevant to this operation.
AppendCount Number of header ﬁelds in AppendList.
AppendList List of HTTP headers to populate NewMessage with. If SeedMessage is not NULL, AppendList will be
appended to the existing list from SeedMessage inNewMessage
NewMessageSize Pointer to number of header ﬁelds in NewMessage.
NewMessage Pointer to a new list of HTTP headers based on
29.6. EFI HTTP Protocols 1297Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The Build() function is used to manage the headers portion of an HTTP message by providing the ability to add,
remove, or replace HTTP headers.
EFI_SUCCESS Add, remove, and replace operations succeeded.
EFI_OUT_OF_RESOURCES Could not allocate memory for NewMessage.
29.6.13 EFI_HTTP_UTILITIES_PROTOCOL.Parse()
Summary
Parse HTTP header into array of key/value pairs.
typedef
(EFIAPI *EFI_HTTP_UTILS_PARSE) (
IN CHAR8 *HttpMessage,
IN UINTN HttpMessageSize,
OUT EFI_HTTP_HEADER **HeaderFields,
OUT UINTN *FieldCount
);
HttpMessage Contains raw unformatted HTTP header string.
HttpMessageSize Size of HTTP header.
HeaderFields Array of key/value header pairs.
FieldCount Number of headers in HeaderFields.
TheParse() function is used to transform data stored in HttpHeader into a list of ﬁelds paired with their corresponding
values.
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Table 29.54 – continued from previous page
•HttpMessage isNULL
•HeaderFields isNULL
•FieldCount isNULL
29.7 EFI REST Support Overview
EFI REST(EX) protocols are designed to support REST communication between EFI REST client applications/drivers
and REST services. EFI REST client tool uses EFI REST(EX) protocols to send/receive resources to/from REST
service to manage systems, conﬁgure systems or manipulate resources on REST service. Due to HTTP protocol is
commonly used to communicate with REST service in practice, EFI REST(EX) protocols adopt HTTP as the message
format to send and receive REST service resource.
EFI REST(EX) driver instance abstracts EFI REST client functionality and provides underlying interface to commu-
nicate with REST service. EFI REST(EX) driver instance knows how to communicate with REST service through
certain interface after the corresponding conﬁguration is initialized. EFI REST support provides two REST relevant
protocols, one is EFI REST protocol which was introduced in UEFI spec 2.5 for providing light-weight EFI REST
capability. Another one is EFI REST EX protocol, which is introduced in UEFI spec 2.8 for providing more interop-
erability between EFI REST client and REST service.
EFI REST and EFI REST EX protocols are not required to coexist on a platform, system integrator determines which
EFI REST relevant protocol to be supported on system according to the platform demands. EFI REST support is to
provide interoperability between EFI REST client and REST service. The authentication of accessing to REST service
is not handled by EFI REST relevant protocols. Different REST service has its own authentication method. EFI REST
client has to follow the speciﬁcation deﬁned by REST service for the authentication process.
Multiple EFI REST(EX) driver instances can be installed on a platform to communicate with different types of REST
services or various underlying interfaces to REST services. REST service can be located on the platform locally, or
off platform in the remote server. The system integrator can implement In-band EFI REST(EX) driver instance for the
on-platform REST service communications or Out-of-band EFI REST(EX) driver instance for the off-platform REST
service communications.
29.7.1 EFI REST Support Scenario 1 (PlatformManagement)
The following ﬁgure represents a platform which has BMC on board, with the REST service deployed like Redﬁsh
service. The In-band EFI REST(EX) protocol (right one) is used by EFI REST client to manage this platform. This
platform can also be managed in out of band like from the remote OS REST client. The left one is Out of band
EFI REST(EX) protocol which communicate with other REST services like Redﬁsh service in which the resource is
belong to other platforms.
29.7. EFI REST Support Overview 1299Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 29.1: EFI REST Support, Single Protocol
29.7. EFI REST Support Overview 1300Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 29.2: EFI REST Support, Multiple Protocols
29.7. EFI REST Support Overview 1301Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 29.3: EFI REST Support, BMC on Board
29.7. EFI REST Support Overview 1302Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.2 EFI REST Support Scenario 2 (PlatformManagement)
The following ﬁgure represents a platform which uses remote Redﬁsh service for the platform management. If treats
the resource in remote Redﬁsh service as a part of this platform, the In-band EFI REST(EX) protocol could be im-
plemented to communicate with remote Redﬁsh service. This platform can also be managed in out of band from the
remote OS REST client.
Fig. 29.4: EFI REST Support, Redﬁsh Service
A variety of possible EFI REST(EX) protocol usages are delineated as below. The EFI REST(EX) driver instance could
communicate with REST service through underlying interface like EFI network stack, platform speciﬁc interface to
BMC or others. The working model of EFI REST support depends on the implementation of EFI REST(EX) driver
instance and the design of platform.
29.7. EFI REST Support Overview 1303Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 29.5: EFI REST Support, Protocol Usages
29.7.3 EFI REST Protocol
This section deﬁnes the EFI REST Protocol interface.
29.7.3.1 EFI REST Protocol Deﬁnitions
29.7.4 EFI_REST_PROTOCOL
#define EFI_REST_PROTOCOL_GUID \
{0x0DB48A36, 0x4E54, 0xEA9C,\
{ 0x9B, 0x09, 0x1E, 0xA5, 0xBE, 0x3A, 0x66, 0x0B }}
typedef struct _EFI_REST_PROTOCOL {
EFI_REST_SEND_RECEIVE SendReceive;
EFI_REST_GET_TIME GetServiceTime;
} EFI_REST_PROTOCOL;
RestSendReceive Provides an HTTP-like interface to send and receive resources from a REST service.
GetServiceTime Returns the current time of the REST service.
The EFI REST protocol is designed to be used by EFI drivers and applications to send and receive resources from
a RESTful service. This protocol abstracts REST (Representational State Transfer) client functionality. This EFI
protocol could be implemented to use an underlying EFI HTTP protocol, or it could rely on other interfaces that
abstract HTTP access to the resources.
29.7. EFI REST Support Overview 1304Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.5 EFI_REST_PROTOCOL.SendReceive()
Summary
Provides a simple HTTP-like interface to send and receive resources from a REST service.
typedef
(EFIAPI *EFI_REST_SEND_RECEIVE)(
IN EFI_REST_PROTOCOL *This,

Summary
typedef
IN EFI_HTTP_MESSAGE *RequestMessage,
OUT EFI_HTTP_MESSAGE *ResponseMessage
);
This Pointer to EFI_REST_PROTOCOL instance for a particular REST service.
RequestMessage Pointer to the REST request data for this resource
ResponseMessage Pointer to the REST response data obtained for this requested.
The SendReceive() function sends a REST request to this REST service, and returns a REST response when the
data is retrieved from the service. Both of the REST request and response messages are represented in format of
EFI_HTTP_MESSAGE. RequestMessage contains the request to the REST resource identiﬁed by UrlRequestMessage-
>Data.Request->Url . The ResponseMessage is the returned response for that request, including the ﬁnal HTTP status
code, headers and teh REST resource represented in the message body.
The memory buffers pointed by ResponseMessage->Data.Response, ResponseMessage->Headers and R
esponseMessage->Body are allocated by this function, and it is the caller’s responsibility to free the buffer when
the caller no longer requires the buffer’s contents.
It’s the REST protocol’s responsibility to handle HTTP layer details and return the REST resource to the caller, when
this function is implemented by using an underlying EFI HTTP protocol. For example, if an HTTP interim response
(Informational 1xx in HTTP 1.1) is received from server, the REST protocol should deal with it and keep waiting for
the ﬁnal response, instead of return the interim response to the caller. Same principle should be observed if the REST
protocol relies on other interfaces.
EFI_SUCCESS operation succeeded
EFI_INV ALID_PARAMETER This, RequestMessage, orResponseMessage areNULL .
EFI_TIMEOUT Receiving response message fail due to timeout.
29.7. EFI REST Support Overview 1305Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.6 EFI_REST_PROTOCOL.GetServiceTime()
typedef
(EFIAPI *EFI_REST_GET_TIME)(
);
This Pointer to EFI_REST_PROTOCOL instance.
Time A pointer to storage to receive a snapshot of the current time of the REST service.
TheGetServiceTime() function is an optional interface to obtain the current time from this REST service instance. If
this REST service does not support retrieving the time, this function returns EFI_UNSUPPORTED.
EFI_INV ALID_PARAMETER This orTime areNULL .
EFI_UNSUPPORTED The RESTful service does not support returning the time
29.7.7 EFI REST EX Protocol
This section deﬁnes the EFI REST EX Protocol interfaces. It is split into the following two main sections:
• REST EX Service Binding Protocol (RESTEXSB)
• REST EX Protocol (REST EX)
29.7.7.1 REST EX Service Binding Protocol
29.7.8 EFI_REST_EX_SERVICE_BINDING_PROTOCOL
Summary
The RESTEXSB is used to locate the REST services those are supported by a REST EX driver instances and to create
and destroy instances of REST EX child protocol driver.
The EFI Service Binding Protocol in EFI Service Binding Protocol deﬁnes the generic Service Binding Protocol
functions. This section discusses the details that are speciﬁc to the REST EX.
GUID
#define EFI_REST_EX_SERVICE_BINDING_PROTOCOL_GUID \
{0x456bbe01, 0x99d0, 0x45ea, \
{0xbb, 0x5f, 0x16, 0xd8, 0x4b, 0xed, 0xc5, 0x59}}
A REST service client application (or driver) that communicates to REST service can use one of protocol handler
services, such as BS->LocateHandleBuffer(), to search for devices that publish a RESTEXSB GUID. Each device
with a published RESTEXSB GUID supports REST EX Service Binding Protocol and may be available for use.
29.7. EFI REST Support Overview 1306Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
After a successful call to the EFI_REST_EX_SERVICE_BINDING_PROTOCOL.CreateChild() function, the child
REST EX driver is in the unconﬁgured state. It is not ready to communicate with REST service at this moment. The
child instance is ready to use to communicate with REST service after the successful Conﬁgure() is invoked. For EFI
REST drivers which don’t require additional conﬁguration process, Conﬁgure() is unnecessary to be invoked before
using its child instance. This depends on EFI REST EX driver speciﬁc implementation.
Before a REST service client application terminates execution, every successful call to the
EFI_REST_EX_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_REST_EX_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
29.7.8.1 REST EX Protocol Speciﬁc Deﬁnitions
29.7.9 EFI_REST_EX_PROTOCOL
#define EFI_REST_EX_PROTOCOL_GUID \
{0x55648b91, 0xe7d, 0x40a3, \
{0xa9, 0xb3, 0xa8, 0x15, 0xd7, 0xea, 0xdf, 0x97}}
typedef struct _EFI_REST_EX_PROTOCOL {
EFI_REST_EX_GET_SERVICE GetService;
EFI_REST_EX_GET_MODE_DATA GetModeData;
EFI_REST_EX_CONFIGURE Configure;
EFI_REST_EX_ASYNC_SEND_RECEIVE AyncSendReceive;
EFI_REST_EX_EVENT_SERVICE EventService;
} EFI_REST_EX_PROTOCOL;
SendReceive Provides an HTTP-like interface to send and receive resources from a REST service. The functional-
ity of this function is same as EFI_REST_PROTOCOL.SendReceive(). Refer to section EFI REST Protocol
Deﬁnitions for more details.
GetServiceTime Returns the current time of the REST service. The functionality of this function is same as
EFI_REST_PROTOCOL.GetServiceTime(). Refer to 29.7.1.1 for the details.
GetService This function returns the type and location of REST service.
GetModeData This function returns operational conﬁguration of current EFI REST EX child instance.
Conﬁgure This function is used to conﬁgure EFI REST EX child instance.
AyncSendReceive Provides an HTTP-like interface to send and receive resources. The resource returned from REST
service is sent to client in asynchronously.
EventService Provides an interface to subscribe event of speciﬁc resource changes on REST service.
The REST EX protocol is designed to use by REST service client applications or drivers to communicate with REST
service. REST EX protocol enhances the REST protocol and provides comprehensive interfaces to REST service
clients. Akin to REST protocol, REST EX driver instance uses HTTP message for the REST request and response.
However, the underlying mechanism of REST EX is not necessary to be HTTP-aware. The underlying mechanism
could be any protocols according to the REST service mechanism respectively. REST EX protocol could be used to
communicate with In-band or Out-of-band REST service depends on the platform-speciﬁc implementation.
29.7. EFI REST Support Overview 1307Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.10 EFI_REST_EX_PROTOCOL.SendReceive()
Summary
typedef
IN EFI_REST_EX_PROTOCOL *This,
);
Refer to EFI REST Protocol Deﬁnitions for the details.
EFI_DEVICE_ERROT An unexpected system or network error occurred.
EFI_NOT_READY The conﬁguration of this instance is not set yet. Conﬁgure() must be exe-
cuted and returns successfully prior to invoke this function.
29.7.11 EFI_REST_EX_PROTOCOL.GetService()
Summary
This function returns the information of REST service provided by this EFI REST EX driver instance.
Protocol Interface
typedef
(EFIAPI *EFI_REST_EX_GET_SERVICE)(
OUT EFI_REST_EX_SERVICE_INFO **RestExServiceInfo
);
This This is the EFI_REST_EX_PROTOCOL instance.
RestExServiceInfo Pointer to receive a pointer to EFI_REST_EX_SERVICE_INFO structure. The format
ofEFI_REST_EX_SERVICE_INFO is version controlled for the future extension. The version of
EFI_REST_EX_SERVICE_INFO structure is returned in the header within this structure. EFI REST
client refers to the correct format of structure according to the version number. The pointer to
EFI_REST_EX_SERVICE_INFO is a memory block allocated by EFI REST EX driver instance. That is caller’s
responsibility to free this memory when this structure is no longer needed. Refer to Related Deﬁnitions below
for the deﬁnitions of EFI_REST_EX_SERVICE_INFO structure.
29.7. EFI REST Support Overview 1308Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

typedef
);
This function returns the information of REST service provided by this REST EX driver instance. The information
such as the type of REST service and the access mode of REST EX driver instance (In-band or Out-of-band) are
described in EFI_REST_EX_SERVICE_INFO structure. For the vendor-speciﬁc REST service, vendor-speciﬁc REST
service information is returned in VendorSpecifcData. Besides the REST service information provided by REST EX
driver instance, EFI_DEVICE_PATH_PROTOCOL of the REST service is also provided on the handle of REST EX
driver instance.
EFI REST client can get the information of REST service from REST service EFI device path node in
EFI_DEVICE_PATH_PROTOCOL .EFI_DEVICE_PATH_PROTOCOL which installed on REST EX driver instance
indicates where the REST service is located, such as BMC Device Path, IPV4, IPV6 or others. Refer to REST Service
Device Path for details of the REST service device path node, which is the sub-type (Sub-type = 32) of Messaging
Device Path (type 3).
REST EX driver designer is well know what REST service this REST EX driver instance intends to communicate
with. The designer also well know this driver instance is used to talk to BMC through speciﬁc platform mechanism or
talk to REST server through UEFI HTTP protocol. REST EX driver is responsible to ﬁll up the correct information
inEFI_REST_EX_SERVICE_INFO. EFI_REST_EX_SERVICE_INFO is referred by EFI REST clients to pickup the
proper EFI REST EX driver instance to get and set resource. GetService() is a basic and mandatory function which
must be able to use even Conﬁgure() is not invoked in previously.
//EFI_REST_EX_SERVICE_INFO_HEADER
EFI_REST_EX_SERVICE_INFO_VER RestServiceInfoVer;
} EFI_REST_EX_SERVICE_INFO_HEADER;
Length The length of entire EFI_REST_EX_SERVICE_INFO structure. Header size is included.
RestServiceInfoVer The version of this EFI_REST_SERVICE_INFO structure. See below deﬁnitions of
EFI_REST_EX_SERVICE_INFO_VER.
//EFI_REST_EX_SERVICE_INFO_VER
} EFI_REST_EX_SERVICE_INFO_VER;
Major The major version of EFI_REST_EX_SERVICE_INFO.
Minor The minor version of EFI_REST_EX_SERVICE_INFO.
//EFI_REST_EX_SERVICE_INFO
EFI_REST_EX_SERVICE_INFO is version controlled for the future extensions. Any new information added to this
structure requires version increased. EFI REST EX driver instance must provides the correct version of structure in
EFI_REST_EX_SERVICE_INFO_VER when it returns EFI_REST_EX_SERVICE_INFO to caller.
29.7. EFI REST Support Overview 1309Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_REST_EX_SERVICE_INFO_HEADER EfiRestExServiceInfoHeader;
EFI_REST_EX_SERVICE_INFO_V_1_0 EfiRestExServiceInfoV10;
} EFI_REST_EX_SERVICE_INFO;
//EFI_REST_EX_SERVICE_INFO v1.0
EFI_REST_EX_SERVICE_TYPE RestExServiceType;
EFI_REST_EX_SERVICE_ACCESS_MODE RestServiceAccessMode;
EFI_GUID VendorRestServiceName;
UINT32 VendorSpecificDataLength;
UINT8 *VendorSpecifcData;
EFI_REST_EX_CONFIG_TYPE RestExConfigType;
UINT8 RestExConfigDataLength;
} EFI_REST_EX_SERVICE_INFO_V_1_0;
EﬁRestExServiceInfoHeader The header of EFI_REST_EX_SERVICE_INFO.
RestExServiceType The REST service type. See below deﬁnition.
RestServiceAccessMode The access mode of REST service. See below deﬁnition.
VendorRestServiceName The name of vendor-speciﬁc REST service. This ﬁeld is only valid if RestExServiceType
is EFI_REST_EX_SERVICE_VENDOR_SPECIFIC.
VendorSpeciﬁcDataLength The length of vendor-speciﬁc REST service information. This ﬁeld is only valid if
RestExServiceType is EFI_REST_EX_SERVICE_VENDOR_SPECIFIC.
VendorSpecifcData A pointer to vendor-speciﬁc REST service information. This ﬁeld is only valid if RestExService-
Type is EFI_REST_EX_SERVICE_VENDOR_SPECIFIC. The memory buffer pointed by VendorSpecifcData
is allocated by EFI REST EX driver instance and must be freed by EFI REST client when it is no longer need.
RestExConﬁgType The type of conﬁguration of REST EX driver instance. See GetModeData()and Conﬁgure() for
the details.
RestExConﬁgDataLength The length of REST EX conﬁguration data.
// EFI_REST_EX_SERVICE_TYPE
EFI_REST_EX_SERVICE_UNSPECIFIC = 1,
EFI_REST_EX_SERVICE_REDFISH,
EFI_REST_EX_SERVICE_ODATA,
EFI_REST_EX_SERVICE_VENDOR_SPECIFIC = 0xff,
EFI_REST_EX_SERVICE_TYPE_MAX
} EFI_REST_EX_SERVICE_TYPE;
EFI_REST_EX_SERVICE_UNSPECIFIC indicates this EFI REST EX driver instance is not used to communicate
with any particular REST service. The EFI REST EX driver instance which reports this service type is REST service
independent and only provides SendReceive()function to EFI REST client. EFI REST client uses this function to send
and receive HTTP message to any target URI and handles the follow up actions by itself. The EFI REST EX driver
instance in this type must returns EFI_UNSUPPORTED in below REST EX protocol interfaces, GetServiceTime(),
AyncSendReceive() and EventService().
29.7. EFI REST Support Overview 1310Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_REST_EX_SERVICE_REDFISH indicates this EFI REST EX driver instance is used to communicate with Red-
ﬁsh REST service.
EFI_REST_EX_SERVICE_ODATA indicates this EFI REST EX driver instance is used to communicate with Odata
REST service.
EFI_REST_EX_SERVICE_VENDOR_SPECIFIC indicates this EFI REST EX driver instance is used to communicate
with vendor-speciﬁc REST service.
// EFI_REST_EX_SERVICE_ACCESS_MODE
EFI_REST_EX_SERVICE_IN_BAND_ACCESS = 1,
EFI_REST_EX_SERVICE_OUT_OF_BAND_ACCESS = 2,
EFI_REST_EX_SERVICE_ACCESS_MODE_MAX
} EFI_REST_EX_SERVICE_ACCESS_MODE;
EFI_REST_EX_SERVICE_IN_BAND_ACCESS mode indicates the REST service is invoked in In-band mechanism in
the scope of platform. In most of cases, the In-band mechanism is used to communicate with REST service on platform
through some particular devices like BMC, Embedded Controller and other infrastructures built on the platform.
EFI_REST_EX_SERVICE_OUT_OF_BAND_ACCESS mode indicates the REST service is invoked in Out-of-band
mechanism. The REST service is located out of platform scope. In most of cases, the Out-of-band mechanism is used
to communicate with REST service on other platforms through network or other protocols.
// EFI_REST_EX_CONFIG_TYPE
EFI_REST_EX_CONFIG_TYPE_HTTP,
EFI_REST_EX_CONFIG_TYPE_UNSPECIFIC,
EFI_REST_EX_CONFIG_TYPE_MAX
} EFI_REST_EX_CONFIG_TYPE;
EFI_REST_EX_CONFIG_TYPE_HTTP indicates the format of the REST EX conﬁguration is
EFI_REST_EX_HTTP_CONFIG_DATA. RestExConﬁgDataLength of this type is the size of
EFI_REST_EX_HTTP_CONFIG_DATA. This conﬁguration type is used for the HTTP-aware EFI REST EX
// EFI_REST_EX_HTTP_CONFIG_DATA
EFI_HTTP_CONFIG_DATA HttpConfigData;
UINT32 SendReceiveTimeout;
} EFI_REST_EX_HTTP_CONFIG_DATA;
HttpConﬁgData Parameters to conﬁgure the HTTP child instance.
SendReceiveTimeout Time out (in milliseconds) when blocking for response after send out request message in
EFI_REST_EX_PROTOCOL.SendReceive().
EFI_REST_EX_CONFIG_TYPE_UNSPECIFIC indicates the format of REST EX conﬁguration is unspeciﬁc. Res-
tExConﬁgDataLength of this type depends on the implementation of non HTTP-aware EFI REST EX driver instance
such as BMC EFI REST EX driver instance. The format of conﬁguration for this type refers to the system/platform
spec which is out of UEFI scope.
29.7. EFI REST Support Overview 1311Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS EFI_REST_EX_SERVICE_INFO is returned in RestExServiceInfo.
EFI_UNSUPPORTED This function is not supported in this REST EX Protocol driver instance.
29.7.12 EFI_REST_EX_PROTOCOL.GetModeData()
Summary

Summary
This function returns operational conﬁguration of current EFI REST EX child instance.
typedef
(EFIAPI *EFI_REST_EX_GET_MODE_DATA)(
OUT EFI_REST_EX_CONFIG_DATA *RestExConfigData
);
RestExConﬁgData Pointer to receive a pointer to EFI_REST_EX_CONFIG_DATA. The memory allocated for con-
ﬁguration data should be freed by caller. See Related Deﬁnitions for the details.
This function returns the current conﬁguration of EFI REST EX child instance. The format of operational con-
ﬁguration depends on the implementation of EFI REST EX driver instance. For example, HTTP-aware EFI
REST EX driver instance uses EFI HTTP protocol as the underlying protocol to communicate with the REST
service. In this case, the type of conﬁguration EFI_REST_EX_CONFIG_TYPE_HTTP is returned from Get-
Service(). EFI_REST_EX_HTTP_CONFIG_DATA is used as EFI REST EX conﬁguration format and returned
to the EFI REST client. For those non HTTP-aware REST EX driver instances, the type of conﬁguration
EFI_REST_EX_CONFIG_TYPE_UNSPECIFIC is returned from GetService(). In this case, the format of returning
data could be non-standard. Instead, the format of conﬁguration data is a system/platform speciﬁc deﬁnition such as a
BMC mechanism used in EFI REST EX driver instance. EFI REST client and EFI REST EX driver instance have to
refer to the speciﬁc system /platform spec which is out of UEFI scope.
//EFI_REST_EX_CONFIG_DATA
typedef UINT8 *EFI_REST_EX_CONFIG_DATA;
cuted and return successfully prior to invoke this function
29.7. EFI REST Support Overview 1312Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.13 EFI_REST_EX_PROTOCOL.Conﬁgure()
Summary
This function is used to conﬁgure EFI REST EX child instance.
typedef
(EFIAPI *EFI_REST_EX_CONFIGURE)(
IN EFI_REST_EX_CONFIG_DATA RestExConfigData
);
RestExConﬁgData Pointer to EFI_REST_EX_CONFIG_DATA. See Related Deﬁnitions in GetModeData() protocol
This function is used to conﬁgure the setting of underlying protocol of REST EX child instance. The type of
conﬁguration is according to the implementation of EFI REST EX driver instance. For example, HTTP-aware
EFI REST EX driver instance uses EFI HTTP protocol as the undying protocol to communicate with REST ser-
vice. The type of conﬁguration is EFI_REST_EX_CONFIG_TYPE_HTTP andRestExConﬁgData is in the format of
EFI_REST_EX_HTTP_CONFIF_DATA.
Akin to HTTP conﬁguration, REST EX child instance can be conﬁgure to use different HTTP local access point for
the data transmission. Multiple REST clients may use different conﬁguration of HTTP to distinguish themselves, such
as to use the different TCP port. For those non HTTP-aware REST EX driver instance, the type of conﬁguration is
EFI_REST_EX_CONFIG_TYPE_UNSPECIFIC. RestExConﬁgData refers to the non industrial standard. Instead, the
format of conﬁguration data is system/platform speciﬁc deﬁnition such as BMC. In this case, EFI REST client and EFI
REST EX driver instance have to refer to the speciﬁc system/platform spec which is out of the UEFI scope. Besides
GetService() function, no other EFI REST EX functions can be executed by this instance until Conﬁgure() is executed
and returns successfully. All other functions must returns EFI_NOT_READY if this instance is not conﬁgured yet. Set
RestExConﬁgData toNULL means to put EFI REST EX child instance into the unconﬁgured state.
EFI_SUCCESS EFI_REST_EX_CONFIG_DATA is set in successfully.
EFI_DEVICE_ERROR Conﬁguration for this REST EX child instance is failed with the given
EFI_REST_EX_CONFIG_DATA
Usage Example
Below illustrations show the usage cases of using different EFI REST EX child instances to communicate with REST
service.
29.7. EFI REST Support Overview 1313Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
In the above case, EFI REST Client A and B use HTTP-aware EFI REST EX driver instance to get and send resource.
These two EFI REST clients conﬁgure the child instance with speciﬁc TCP port. Therefore the data transmission
through HTTP can delivered to the proper EFI REST clients.
In the above case, EFI REST Client A creates two EFI REST EX child instances and conﬁgures those child instances
to connect to two BMCs respectively.
29.7.14 EFI_REST_EX_PROTOCOL.AsyncSendReceive()
Summary
This function sends REST request to REST service and signal caller’s event asynchronously when the ﬁnal response
is received by REST EX Protocol driver instance. The essential design of this function is to handle asynchronous
send/receive implicitly according to REST service asynchronous request mechanism. Caller will get the notiﬁcation
once the ﬁnal response is returned from the REST service.
typedef
(EFIAPI *EFI_REST_EX_ASYNC_SEND_RECEIVE)(
IN EFI_HTTP_MESSAGE *RequestMessage OPTIONAL,
IN EFI_REST_EX_TOKEN *RestExToken,
IN UINTN *TimeOutInMilliSeconds OPTIONAL
);
RequestMessage This is the REST request message sent to the REST service. Set RequestMessage toNULL to
cancel the previous asynchronous request associated with the corresponding RestExToken. See descriptions for
RestExToken REST EX token which REST EX Protocol instance uses to notify REST client the status of response
of asynchronous REST request. See related deﬁnition of EFI_REST_EX_TOKEN.
TimeOutInMilliSeconds The pointer to the timeout in milliseconds which REST EX Protocol driver instance refers
as the duration to drop asynchronous REST request. NULL pointer means no timeout for this REST request.
REST EX Protocol driver signals caller’s event with EFI_STATUS set to EFI_TIMEOUT inRestExToken if
REST EX Protocol can’t get the response from REST service within TimeOutInMilliSeconds.
29.7. EFI REST Support Overview 1314Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function is used to send REST request with asynchronous REST service response within certain timeout declared.
REST service sometime takes long time to create resource. Sometimes REST service returns response to REST client
late because of the shortage of bandwidth or bad network quality. To prevent from unfriendly user experience due
to system stuck while waiting for the response from REST service, EFI_REST_EX_PROTOCOL.AsyncSendReceive()
provides the capability to send asynchronous REST request. Caller sends the REST request and still can execute some
other processes on background while waiting the event signaled by REST EX Protocol driver instance.
The implementation of underlying mechanism of asynchronous REST request depends on the mechanism of REST
service. HTTP protocol, In-Band management protocol and other protocols has its own way to support asynchronous
REST request. Similar to EFI_REST_EX_PROTOCOL .SendReceive(), It’s the REST EX protocol’s responsibility to
handle the implementation details and return only the REST resource to the caller. REST EX Protocol driver instance
which doesn’t support asynchronous REST request can just return EFI_UNSUPPORTED to caller. Also, this function
must returns EFI_UNSUPPORTED ifEFI_REST_EX_SERVICE_TYPE returned in EFI_REST_EX_SERVICE_INFO
from GetService() is EFI_REST_EX_SERVICE_UNSPECIFIC.
REST clients do not have to know the preprocessors of asynchronous REST request between REST EX Protocol driver
instance and REST service. The responsibility of REST EX Protocol driver instance is to monitor the status of resource
readiness and to signal caller’s RestExToken when the status of returning resource is ready. REST EX Protocol driver
instance sets Status ﬁeld in RestExToken toEFI_SUCCESS and sets ResponseMessage pointer to the ﬁnal response
from REST service. Then signal caller’s event to notify REST client the desired REST resource is received. REST EX
Protocol driver instance also has to create an EFI timer to handle the timeout situation. REST EX Protocol driver must
drops the asynchronous REST request once the timeout is expired. In this case, REST EX Protocol driver instance sets
Status ﬁeld in RestExToken to EFI_TIMEOUT and signal caller’s event token.

REST EX Protocol driver instance must has capability to cancel the in process asynchronous REST request when
caller asks to terminate speciﬁc asynchronous REST request. REST EX Protocol driver instance may not have capa-
bility to force REST service to cancel the speciﬁc request, however, REST EX Protocol driver instance at lease least
can clean up its own internal resource of asynchronous REST request. Caller has to set RequestMessage to NULL
with RestExToken set to EFI_REST_EX_TOKEN which was successfully sent to this function previously. REST EX
Protocol driver instance ﬁnds the given EFI_REST_EX_TOKEN from its private database and clean up the associated
resource if EFI_REST_EX_TOKEN is an in-process asynchronous REST request. REST EX Protocol driver instance
then sets Status ﬁeld in RestExToken to EFI_ABORT and signal caller’s event to indicate the asynchronous REST
request has been canceled.
REST EX Protocol driver instance maintains the internal property, state machine, status of transfer of each asyn-
chronous REST request. REST EX Protocol driver instance has to clean up the internal resource associated with each
asynchronous REST request no matter the transfer is ended with success or fail.
There are two phases of asynchronous REST request. One is the preprocessor of establishing asynchronous REST
request between REST EX Protocol driver instance and REST service. Another phase is to retrieve the ﬁnal response
from REST service and send to REST client.
//EFI_REST_EX_TOKEN
EFI_HTTP_MESSAGE *ResponseMessage;
} EFI_REST_EX_TOKEN;
Event This event will be signaled after the Status ﬁeld is updated by the EFI REST EX Protocol driver instance. The
type of Event must be EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of Event must be lower than or
equal to TPL_CALLBACK, which allows other events to be notiﬁed.
Status Status will be set to one of the following values if the REST EX Protocol driver instance gets the response
29.7. EFI REST Support Overview 1315Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
from the REST service successfully, or if an unexpected error occurs:
EFI_SUCCESS : The resource gets a response from REST service successfully. ResponseMessage points to the
response in HTTP message structure.
EFI_ABORTED : The asynchronous REST request was canceled by the caller.
EFI_TIMEOUT : The asynchronous REST request timed out before receiving a response from the REST
service.
EFI_DEVICE_ERROR : An unexpected error occurred.
ResponseMessage The REST response message pointed to by this pointer is only valid when Status is
EFI_SUCCESS. The memory buffers pointed to by ResponseMessage, ResponseMessage->Data.Response,
ResponseMessage->Headers andResponseMessage->Body are allocated by the EFI REST EX driver instance,
and it is the caller’s responsibility to free the buffer when the caller no longer requires the buffer’s contents.
EFI_SUCCESS Asynchronous REST request is established.
EFI_UNSUPPORTED This REST EX Protocol driver instance doesn’t support asynchronous re-
quest.
EFI_TIMEOUT Asynchronous REST request is not established and timeout is expired.
EFI_ABORT Previous asynchronous REST request has been canceled.
EFI_DEVICE_ERROR Otherwise, returns EFI_DEVICE_ERROR for other errors according to
HTTP Status Code.
29.7.15 EFI_REST_EX_PROTOCOL.EventService()
Summary
This function sends REST request to a REST Event service and signals caller’s event token asynchronously when the
URI resource change event is received by REST EX Protocol driver instance. The essential design of this function
is to monitor event implicitly according to REST service event service mechanism. Caller will get the notiﬁcation if
certain resource is changed.
typedef
(EFIAPI *EFI_REST_EX_EVENT_SERVICE)(
IN EFI_REST_EX_TOKEN *RestExToken
);
RequestMessage This is the HTTP request message sent to REST service. Set RequestMessage to NULL to cancel
the previous event service associated with the corresponding RestExToken. See descriptions for the details.
RestExToken REST EX token which REST EX Protocol driver instance uses to notify REST client the URI resource
29.7. EFI REST Support Overview 1316Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
which monitored by REST client has been changed. See the related deﬁnition of EFI_REST_EX_TOKEN in
EFI_REST_EX_PROTOCOL.AsyncSendReceive().
This function is used to subscribe an event through REST Event service if REST service supports event service.
This function listens on resource change of speciﬁc REST URI resource. The type of URI resource change event
is varied and REST service speciﬁc, such as URI resource updated, resource added, resource removed, alert, etc.
The way to subscribe REST Event service is also REST service speciﬁc, usually described in HTTP body. With
the implementation of EFI_REST_EX_PROTOCOL.EventService(), REST client can register an REST EX token of
particular URI resource change, usually of a time critical nature, until subscription is deleted from REST Event service.
The implementation of underlying mechanism of REST Event service depends on the interface of REST EX Protocol
driver instance. HTTP protocol, In-Band management protocols or other protocols can have its own implementation
to support REST Event Service request. REST EX Protocol driver instance has knowledge of how to handle the REST
Event service. The REST client creates and submits an HTTP-like header/body content in RequestMessage which
required by REST Event services. How does REST EX Protocol driver instance handle REST Event service and mon-
itor event is REST service-speciﬁc. REST EX driver instance can just returns EFI_UNSUPPORTED if REST service
has no event capability. Also, this function must returns EFI_UNSUPPORTED ifEFI_REST_EX_SERVICE_TYPE
returned in EFI_REST_EX_SERVICE_INFO from GetService() isEFI_REST_EX_SERVICE_UNSPECIFIC.
The REST EX Protocol driver instance is responsible to monitor the resource change event pushed from REST ser-
vice. REST EX Protocol driver instance signals caller’s RestExToken when the event of resource change is pushed to
REST EX Protocol driver instance. The way how REST service pushes event to REST EX Protocol driver instance is
implementation-speciﬁc and transparent to REST client. REST EX Protocol driver instance sets Status ﬁeld in RestEx-
Token toEFI_SUCCESS and sets ResponseMessage pointer to the event resource returned from REST Event service.
Then REST EX Protocol driver instance signals caller’s event to notify REST client a new REST event is received.
REST EX Protocol driver instance also responsible to terminate event subscription and clear up the internal resource
associated with REST Event service if the status of subscription resource is returned error.
REST EX Protocol driver instance must has capability to remove event subscription created by REST client. Caller
has to set RequestMessage to NULL with RestExToken set to EFI_REST_EX_TOKEN which was successfully sent to
this function previously. REST EX Protocol driver instance ﬁnds the given EFI_REST_EX_TOKEN from its private
database and delete the associated event from REST service.
quest.
EFI_ABORT Previous asynchronous REST request has been canceled or event subscrip-
tion has been delete from service
29.7. EFI REST Support Overview 1317Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.15.1 Usage Example (HTTP-aware REST EX Protocol DriverInstance)
The following code example shows how a consumer of REST EX driver would use EFI REST EX ServiceBinding
Protocol and EFI REST EX Protocol to send and receive the resources from a REST service.
UINTN HandleNum;
EFI_REST_EX_SERVICE_BINDING_PROTOCOL *RestExService;
EFI_HANDLE RestExChild;
EFI_REST_EX_PROTOCOL *RestEx;
EFI_REST_EX_SERVICE_INFO *RestExServiceInfo;
EFI_REST_EX_CONFIG_DATA RestExConfigData;
//
// Locate all the handles withRESTEX ServiceBinding Protocol.
//

//
//
&gEfiRestExServiceBindingProtocolGuid,
NULL,
&HandleNum,
);
if(EFI_ERROR (Status) || (HandleNum == 0)) {
returnEFI_ABORTED;
}
for(Index = 0; Index < HandleNum; Index++) {
//
// Get the RESTEX ServiceBinding Protocol
//
HandleBuffer[Index],
(VOID**) &RestExService,
NULL,
);
}
//
// Create the corresponding REST EX child
//
Status = RestExService->CreateChild (RestExService, &RestExChild);
}
//
// Retrieve the REST EX Protocol from child handle
29.7. EFI REST Support Overview 1318Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
RestExChild,
&gEfiRestExProtocolGuid,
(VOID**) &RestEx,
NULL,
);
goto ON_EXIT;
}
//
// Get the information of REST service provided by this EFI REST EX driver
//
Status = RestEx->GetService (
RestEx,
&RestExServiceInfo
);
}
//
// Check whether this REST EX service ispreferred by consumer:
// 1. RestServiceAccessMode is EFI_REST_EX_SERVICE_OUT_OF_BAND_ACCESS.
// 2. RestServiceType isEFI_REST_EX_SERVICE_REDFISH.
// 3. RestExConfigType isEFI_REST_EX_CONFIG_TYPE_HTTP.
//
if(RestExServiceInfo-> REfiRestExServiceInfoV10.estServiceAccessMode ==
EFI_REST_EX_SERVICE_OUT_OF_BAND_ACCESS &&
RestExServiceInfo-> EfiRestExServiceInfoV10.RestServiceType ==
EFI_REST_EX_SERVICE_REDFISH &&
RestExServiceInfo-> EfiRestExServiceInfoV10.RestExConfigType ==
EFI_REST_EX_CONFIG_TYPE_HTTP) {
break;
}
}
//
// Make sure we have found the preferred REST EX driver.
//
if(Index == HandleNum) {
}
//
// Configure the RESTEX instance.
//
Status = RestEx->Configure (
RestEx,
RestExConfigData
);
29.7. EFI REST Support Overview 1319Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
}
//
// Send andreceive the resources from aREST service.
//
Status = RestEx->SendReceive (
RestEx,
&RequestMessage,
&ResponseMessage
);
}
ON_EXIT:
RestExService->DestroyChild (RestExService, RestExChild);
29.7.15.1.1 EFI_REST_EX_PROTOCOL.AsyncSendReceive()
To those HTTP-aware underlying mechanisms of the REST EX Protocol driver instance and “respond-async” prefer
header aware REST service, REST EX Protocol driver instance adds additional HTTP Prefer header ﬁeld (Refer to
IEFT RFC7240) which is set to “respond-async” in the RequestMessage. HTTP 202 Accepted Status Code is returned
from REST service which indicates the REST request is accepted by REST service, however, the ﬁnal result is left
unknown. The way how REST service returns ﬁnal response to REST EX Protocol driver instance is REST service
implementation-speciﬁc and transparent to the REST client. Whether or not the REST service has a proper response to
“respond-async” is REST service implementation-speciﬁc. AsyncSendReceive() must returns EFI_UNSUPPORTED
if the REST service that the REST EX instance communicates with is incapable of asynchronous response.
REST EX Protocol driver instance must returns EFI_SUCCESS to caller once it gets HTTP 202 Accepted Status Code
from REST service. The HTTP Location header ﬁeld can be returned in HTTP 202 Accepted Status Code. REST EX
Protocol driver instance may create an EFI timer to poll the status of URI returned in HTTP Location header ﬁeld. The
content of URI which pointed by HTTP Location header is REST service implementation-speciﬁc and not deﬁned in
REST EX Protocol speciﬁcation. REST EX Protocol driver instance provider should have knowledge about how to
poll the status of returning resource from given HTTP Location header.
The following ﬂowchart describes the ﬂow of establishing asynchronous REST request on HTTP-aware infrastructure:
Once the asynchronous REST request is established, REST EX Protocol driver instance starts to poll the status of ﬁnal
response on the URI returned in HTTP Location header in HTTP 202 Accepted Status code.
29.7.15.1.2 EFI_REST_EX_PROTOCOL.EventService()
The REST client creates and submits an HTTP-like header/body content in RequestMessage which are required by
REST Event services. The REST Event Service will return an HTTP 201 (CREATED) and the Location header in the
response shall contain a URI giving the location of newly created subscription resource.
The following ﬂowchart describes the ﬂow of subscribing to a REST Event service on HTTP-aware infrastructure:
Once the REST request is submitted successfully and REST EX Protocol driver instance gets the HTTP 201, REST
EX Protocol driver instance starts to monitor whether resource event change is pushed to REST EX Protocol driver
instance from REST service.
29.7. EFI REST Support Overview 1320Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7. EFI REST Support Overview 1321Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.16 EFI_REST_EX_PROTOCOL.EventService()
29.7.17 EFI REST JSON Resource to C Structure Converter
29.7.17.1 Overview
EFI REST JSON Structure Protocol is designed as the centralized REST JSON Resource IN-Structure OUT (JSON-IN
Structure-OUT in short) and vice versa converter for EFI REST client drivers or EFI REST client applications. This
protocol provides the registration function which is invoked by upper layer EFI driver to register converter as the plug-
in converter for the well-known REST JSON resource. The EFI driver which provide REST JSON resource to structure
converter is EFI REST JSON structure converter producer. In the other hand, EFI drivers or applications which utilize
EFI REST JSON Structure protocol is the consumer of EFI REST JSON structure converter. The convert producer is
required to register its converter functions with predeﬁned REST JSON resource namespace and data type. EFI REST
JSON Structure Protocol maintains the database of all plug-in converter and dispatches the consumer request to proper
REST JSON resource structure converter. EFI REST JSON Structure Protocol doesn’t have knowledge about the exact
structure for the particular REST JSON resource. It just dispatches JSON resource to the correct convert functions and
returns the pointer of structure generated by convert producer. This protocol reduces the burdens of JSON resource
29.7. EFI REST Support Overview 1322Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7. EFI REST Support Overview 1323Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7. EFI REST Support Overview 1324Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
parsing effort. This also provides the easier way to refer to speciﬁc REST JSON property using native C structure
reference. Below ﬁgure delineates the software stack of EFI REST JSON resource to structure converter architecture.
29.7.17.2 EFI REST JSON Structure Protocol
Summary
EFI REST JSON Structure Protocol provides function to converter producer for the registration of REST JSON re-
source structure converter. This protocol also provides functions of JSON-IN Structure-OUT and vice versa to con-
verter consumer.
#define EFI_REST_JSON_STRUCTURE_PROTOCOL_GUID \
{ 0xa9a048f6, 0x48a0, 0x4714, {0xb7, 0xda, 0xa9, 0xad,
0x87, 0xd4, 0xda, 0xc9}}
typedef struct _EFI_REST_JSON_STRUCTURE_PROTOCOL {
EFI_REST_JSON_STRUCTURE_REGISTER Register;
EFI_REST_JSON_STRUCTURE_TO_STRUCTURE ToStructure;
EFI_REST_JSON_STRUCTURE_TO_JSON ToJson;
EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE DestoryStructure;
} EFI_REST_JSON_STRUCTURE_PROTOCOL;
Register Register REST JSON structure converter producer.
ToStructure JSON-IN Structure-OUT function.
ToJson Structure-IN JSON-OUT function.
DestoryStructure Destroy JSON structure returned from ToStructure function.
Each plug-in JSON resource to structure converter is required to register itself into
EFI_REST_JSON_STRUCTURE_PROTOCOL. The plug-in JSON resource to structure converter has to pro-

29.7. EFI REST Support Overview 1325Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
vide corresponding functions for ToStructure(), ToJson() and DestoryStructure() for the speciﬁc REST JSON
resource. EFI_REST_JSON_STRUCTURE_PROTOCOL maintains converter producer using the JSON resource
type and version information when registration. The ToStructure(), ToJson() andDestoryStructure() provided by
EFI_REST_JSON_STRUCTURE_PROTOCOL is published to converter consumer for JSON-IN Structure-OUT and
vice versa conversion. EFI_REST_JSON_STRUCTURE_PROTOCOL is responsible for dispatching consumer request
to the proper converter producer.
29.7.18 EFI_REST_JSON_STRUCTURE.Register ()
Summary
This function provides REST JSON resource to structure converter registration.
typedef
(EFIAPI *EFI_REST_JSON_STRUCTURE_REGISTER)(
IN EFI_REST_JSON_STRUCTURE_PROTOCOL *This,
IN EFI_REST_JSON_STRUCTURE_SUPPORTED *JsonStructureSupported,
IN EFI_REST_JSON_STRUCTURE_TO_STRUCTURE ToStructure,
IN EFI_REST_JSON_STRUCTURE_TO_JSON ToJson,
IN EFI_REST_JSON_DESTORY_STRUCTURE DestroyStructure
);
This This is the EFI_REST_JSON_STRUCTURE_PROTOCOL instance.
JsonStructureSupported The type and version of REST JSON resource which this converter supports.
ToStructure The function to convert REST JSON resource to structure.
ToJson The function to convert REST JSON structure to JSON in text format.
DestroyStructure Destroy REST JSON structure returned in ToStructure() function.
This function is invoked by REST JSON resource to structure converter to register JSON-IN Structure-OUT, Structure-
IN JSON-OUT and destroy JSON structure functionalities. The converter producer has to correctly specify REST re-
source supporting information in EFI_REST_JSON_STRUCTURE_SUPPORTED. The information includes the type
name, revision and data type of REST resource. Multiple REST JSON resource to structure converters may supported
in one drive, refer to below related deﬁnition.
typedef CHAR8 *EFI_REST_JSON_RESOURCE_TYPE_DATATYPE;
// EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE
typedef struct _EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE {
CHAR8 *ResourceTypeName;
CHAR8 *MajorVersion;
CHAR8 *MinorVersion;
CHAR8 *ErrataVersion;
} EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE;
29.7. EFI REST Support Overview 1326Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ResourceTypeName CHAR8 pointer to the name of this REST JSON Resource.
MajorVersion CHAR8 pointer to the string of REST JSON Resource major version.
MinorVersion CHAR8 pointer to the string of REST JSON Resource minor version.
ErrataVersion CHAR8 pointer to the string of REST JSON Resource errata version.
// EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER
typedef struct _EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER {
EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE Namespace;
EFI_REST_JSON_RESOURCE_TYPE_DATATYPE Datatype;
} EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER;
Namespace Name space of this REST JSON resource.
Datatype CHAR8 pointer to the string of data type, could be NULL if there is no data type for this REST JSON
resource.
// EFI_REST_JSON_STRUCTURE_SUPPORTED
typedef struct _EFI_REST_JSON_STRUCTURE_SUPPORTED{
EFI_REST_JSON_STRUCTURE_SUPPORTED *Next;
EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER JsonResourceType;
} EFI_REST_JSON_STRUCTURE_SUPPORTED;
Next Pointer to next EFI_REST_JSON_STRUCTURE_SUPPORTED.
JsonResourceType Information of REST JSON resource this converter supports.
EFI_SUCCESS Converter is successfully registered
One or more of the following is TRUE :
JsonStructureSupported isNULL .
ResourceTypeName inJsonStructureSupported structure is a NULL string
ToStructure isNULL .
ToJason isNULL .
DestroyStructure isNULL .
EFI_ALREADY_STARTED If the JSON resource to structure converter is already registered for this type
and revision of JSON resource.
EFI_OUT_OF_RESOURCE Not enough resource for the converter registration
29.7. EFI REST Support Overview 1327Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.19 EFI_REST_JSON_STRUCTURE.ToStructure ()
Summary
JSON-IN Structure-OUT function. Convert the given REST JSON resource into structure.
typedef
(EFIAPI *EFI_REST_JSON_STRUCTURE_TO_STRUCTURE)(
IN EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER *JsonRsrcIdentifier
OPTIONAL,
IN CHAR8 *ResourceJsonText,
OUT EFI_REST_JSON_STRUCTURE_HEADER **JsonStructure
);
JsonRsrcIdentiﬁer This indicates the resource type and version is given in ResourceJsonText. IfJsonRsrcIdentiﬁer is
NULL , means the JSON resource type and version information of given ResourceJsonText is unsure. User would
like to have EFI_REST_JSON_STRUCTURE_PROTOCOL to look for the proper JSON structure converter.
ResourceJsonText REST JSON resource in text format.
JsonStructure Pointer to receive the pointer to EFI_REST_JSON_STRUCTURE_HEADER, refer to related deﬁnition
for the details.
This function converts the given JSON resource in text format into predeﬁned structure. The deﬁnition of structure for-
mat is not the scope of EFI_REST_JSON_STRUCTURE_PROTOCOL. EFI_REST_JSON_STRUCTURE_PROTOCOL
is a centralized JSON-IN Structure-OUT converter which maintain the registration of a variety of JSON resource
to structure converters. The structure deﬁnition and the corresponding C header ﬁle are written and released by
3rd party, OEM, organization or any open source communities. The JSON resource to structure converter (con-
vert producer) may be released in the source format or binary format. The convert producer registers itself to
EFI_REST_JSON_STRUCTURE_PROTOCOL uses Register() and provides EFI JSON resource to structure and vice
versa conversion. Consumer has to destroy JsonStructure using DestoryStructure() function. Resource allocated for
JsonStructure will be released and cleaned up by converter producer.
When JsonRsrcIdentiﬁer is a non NULL pointer, ResourceTypeName in
EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE must be a non NULL string, however the revision in
EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE and data type in EFI_REST_JSON_RESOURCE_TYPE could
beNULL string if REST JSON resource is non version controlled or no data type is deﬁned. If JsonRsrcIdentiﬁer is
a non NULL pointer, EFI_REST_JSON_STRUCTURE_PROTOCOL looks for the proper converter from its database.
Invokes the ToStructure() provided by the converter to convert JSON resource to structure.
Another scenario is JsonRsrcIdentiﬁer may passed in as NULL , this means the JSON resource type and version in-
formation of given ResourceJsonText is unsure. In this case, EFI_REST_JSON_STRUCTURE_PROTOCOL invokes
and passes ResourceJsonText toToStructure() of each registered converter with JsonRsrcIdentiﬁer set to NULL . Con-
verter producer may or may not automatically determine REST JSON resource type and version. Converter pro-
ducer should return EFI_UNSUPPORTED if it doesn’t support automatically recognition of REST JSON resource.
Or converter producer can recognize the given REST JSON resource by parsing the certain properties. This de-
pends on the implementation of JSON resource to structure converter. If one of the registered converter produc-
ers can recognize the given ResourceJsonText, theJsonRsrcIdentiﬁer inEFI_REST_JSON_STRUCTURE_HEADER
is ﬁlled up with the proper REST JSON resource type, version and data type. With the information provided in
EFI_REST_JSON_STRUCTURE_HEADER, consumer has idea about what the exact type of REST JSON structure is.
29.7. EFI REST Support Overview 1328Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_REST_JSON_STRUCTURE_HEADER
typedef struct _EFI_REST_JSON_STRUCTURE_HEADER {
EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER JsonRsrcIdentifier;
//
// Follow by a pointer points to JSON structure, the content inthe
// JSON structure isimplementation-specific according to converter producer.
//
VOID *JsonStructurePointer;
} EFI_REST_JSON_STRUCTURE_HEADER;
JsonRsrcIdentiﬁer Information of REST JSON structure returned from this converter.
JsonStructurePointer Pointers to JSON structure, the content in the JSON structure is implementation-speciﬁc ac-
cording to the converter producer.
EFI_SUCCESS Pointer to JSON structure is returned in JsonStructure
ResourceJsonText isNULL .

//
//
JsonRsrcIdentiﬁer is not NULL, but the
ResourceTypeName inJsonRsrcIdentiﬁer isNULL .
JsonStructure isNULL .
EFI_NOT_FOUND No proper JSON resource to structure convert found.
29.7.20 EFI_REST_JSON_STRUCTURE.ToJson ()
Summary
Structure-IN JSON-OUT function. Convert the given REST JSON structure into JSON text. The deﬁnition of structure
format is not the scope of EFI_REST_JSON_STRUCTURE_PROTOCOL. The structure deﬁnition and the correspond-
ing C header ﬁle are written and released by 3rd party, OEM, organization or any open source communities. Consumer
has to free the memory block allocated for ResourceJsonText if the JSON resource is no longer needed.
typedef
(EFIAPI *EFI_REST_JSON_STRUCTURE_TO_JSON)(
IN EFI_REST_JSON_STRUCTURE_HEADER *JsonStructureHeader,
OUT CHAR8 **ResourceJsonText
);
29.7. EFI REST Support Overview 1329Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
JsonStructureHeader The point to EFI_REST_JSON_STRUCTURE_HEADER structure.
EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER inEFI_REST_JSON_STRUCTURE_HEADER must
exactly describes the JSON resource type and revision referred by this JSON structure. ResourceTypeName in
JsonRsrcIdentiﬁer must be non NULL pointer pointes to string. Revision and data type in JsonRsrcIdentiﬁer
could be NULL if REST JSON resource is not version controlled and or data type deﬁnition.
ResourceJsonText Pointer to receive REST JSON resource in text format.
This functions converts the given REST JSON structure into REST JSON text format resource.
EFI_SUCCESS Pointer to JSON resource in text format is returned in ResourceJsonText
JsonStructureHeader isNULL
EFI_NOT_FOUND No proper JSON structure convert found to convert JSON structure to JSON
text format.
29.7.21 EFI_REST_JSON_STRUCTURE.DestroyStructure ()
Summary
This function destroys the REST JSON structure.
typedef
(EFIAPI *EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE)(
IN EFI_REST_JSON_STRUCTURE_HEADER *JsonStructureHeader
);
This function destroys the JSON structure generated by ToStructure() function. REST JSON resource structure con-
verter is responsible for freeing and cleaning up all resource associated with the give JSON structure.
EFI_SUCCESS JSON structure is successfully destroyed.
•This is null.
•JsonStructureHeader isNULL .
EFI_NOT_FOUND No proper JSON structure converter found to destroy JSON structure.
29.7. EFI REST Support Overview 1330Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
29.7.21.1 EFI Redﬁsh JSON Structure Converter
For writing and using an EFI Redﬁsh JSON Structure Converter, see Section 31.2, using the
EFI_REST_JSON_STRUCTURE_PROTOCOL protocol.
29.7. EFI REST Support Overview 1331CHAPTER
THIRTY
NETWORK PROTOCOLS — UDP AND MTFTP
30.1 EFI UDP Protocol
This chapter deﬁnes the EFI UDP (User Datagram Protocol) Protocol that interfaces over the EFI IP Protocol, and the
EFI MTFTP Protocol interface that is built upon the EFI UDP Protocol. Protocols for version 4 and version 6 of UDP
and MTFTP are included.
30.1.1 UDP4 Service Binding Protocol
30.1.1.1 EFI_UDP4_SERVICE_BINDING_PROTOCOL
Summary
The EFI UDPv4 Service Binding Protocol is used to locate communication devices that are supported by an EFI
UDPv4 Protocol driver and to create and destroy instances of the EFI UDPv4 Protocol child protocol driver that can
use the underlying communications device.
GUID
#define EFI_UDP4_SERVICE_BINDING_PROTOCOL_GUID \
{0x83f01464,0x99bd,0x45e5,\
{0xb3,0x83,0xaf,0x63,0x05,0xd8,0xe9,0xe6}}
A network application that requires basic UDPv4 I/O services can use one of the protocol handler services, such as
BS->LocateHandleBuffer() , to search for devices that publish a EFI UDPv4 Service Binding Protocol GUID. Each
device with a published EFI UDPv4 Service Binding Protocol GUID supports the EFI UDPv4 Protocol and may be
available for use.
After a successful call to the EFI_UDP4_SERVICE_BINDING_PROTOCOL .CreateChild() function, the newly cre-
ated child EFI UDPv4 Protocol driver is in an unconﬁgured state; it is not ready to send and receive data packets.
Before a network application terminates execution every successful call to the
EFI_UDP4_SERVICE_BINDING_PROTOCOL .CreateChild() function must be matched with a call to the
EFI_UDP4_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
1332Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
30.1.2 UDP4 Protocol
30.1.2.1 EFI_UDP4_PROTOCOL
Summary
The EFI UDPv4 Protocol provides simple packet-oriented services to transmit and receive UDP packets.
GUID
#define EFI_UDP4_PROTOCOL_GUID \
{0x3ad9df29,0x4501,0x478d,\
{0xb1,0xf8,0x7f,0x7f,0xe7,0x0e,0x50,0xf3}}
typedef struct _EFI_UDP4_PROTOCOL {
EFI_UDP4_GET_MODE_DATA GetModeData;
EFI_UDP4_CONFIGURE Configure;
EFI_UDP4_GROUPS Groups;
EFI_UDP4_ROUTES Routes;
EFI_UDP4_TRANSMIT Transmit;
EFI_UDP4_RECEIVE Receive;
EFI_UDP4_CANCEL Cancel;
EFI_UDP4_POLL Poll;
} EFI_UDP4_PROTOCOL;
Conﬁgure Initializes, changes, or resets operational settings for the EFI UDPv4 Protocol. See the Conﬁgure() func-
Routes Add and deletes routing table entries. See the Routes() function description.
Transmit Queues outgoing data packets into the transmit queue. This function is a nonblocked operation. See the
Transmit() function description.
Receive Places a receiving request token into the receiving queue. This function is a nonblocked operation. See the
TheEFI_UDP4_PROTOCOL deﬁnes an EFI UDPv4 Protocol session that can be used by any network drivers, ap-
plications, or daemons to transmit or receive UDP packets. This protocol instance can either be bound to a speciﬁed
port as a service or connected to some remote peer as an active client. Each instance has its own settings, such as the
routing table and group table, which are independent from each other.
NOTE :In this document, all IPv4 addresses and incoming/outgoing packets are stored in network byte order. All
other parameters in the functions and data structures that are deﬁned in this document are stored in host byte order .
30.1. EFI UDP Protocol 1333Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
30.1.2.2 EFI_UDP4_PROTOCOL.GetModeData()
Summary
Reads the current operational settings.
Prototype
typedef
(EFIAPI *EFI_UDP4_GET_MODE_DATA) (
IN EFI_UDP4_PROTOCOL *This,
OUT EFI_UDP4_CONFIG_DATA *Udp4ConfigData OPTIONAL,
);
This Pointer to the EFI_UDP4_PROTOCOL instance.
Udp4ConﬁgData Pointer to the buffer to receive the current conﬁguration data. Type EFI_UDP4_CONFIG_DATA
Ip4ModeData* Pointer to the EFI IPv4 Protocol mode data structure. Type EFI_IP4_MODE_DATA is deﬁned in
EFI_IP4_PROTOCOL .GetModeData() .
SnpModeData Pointer to the simple network mode data structure. Type EFI_SIMPLE_NETWORK_MODE is deﬁned
in the EFI_SIMPLE_NETWORK_PROTOCOL .
TheGetModeData() function copies the current operational settings of this EFI UDPv4 Protocol instance into user-
supplied buffers. This function is used optionally to retrieve the operational mode data of underlying networks or
drivers.
// EFI_UDP4_CONFIG_DATA
//Receiving Filters
BOOLEAN AcceptAnyPort;
BOOLEAN AllowDuplicatePort;
30.1. EFI UDP Protocol 1334Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

drivers.
} EFI_UDP4_CONFIG_DATA;
AcceptBroadcast Set to TRUE to accept broadcast UDP packets.
AcceptPromiscuous Set to TRUE to accept UDP packets that are sent to any address.
AcceptAnyPort Set to TRUE to accept UDP packets that are sent to any port.
AllowDuplicatePort Set to TRUE to allow this EFI UDPv4 Protocol child instance to open a port number that is
already being used by another EFI UDPv4 Protocol child instance.
DoNotFragment Set to TRUE to disable IP transmit fragmentation.
ReceiveTimeout The receive timeout value (number of microseconds) to be associated with each incoming packet.
Zero means do not drop incoming packets.
TransmitTimeout The transmit timeout value (number of microseconds) to be associated with each outgoing packet.
Zero means do not drop outgoing packets.
retrieve the IP address and subnet information. Ignored for incoming ﬁltering if AcceptPromiscuous is set to
TRUE .
StationAddress The station IP address that will be assigned to this EFI UDPv4 Protocol instance. The EFI UDPv4
and EFI IPv4 Protocol drivers will only deliver incoming packets whose destination matches this IP address
exactly. Address 0.0.0.0 is also accepted as a special case in which incoming packets destined to any station
IP address are always delivered. Not used when UseDefaultAddress isTRUE . Ignored for incoming ﬁltering if
AcceptPromiscuous isTRUE .
SubnetMask The subnet address mask that is associated with the station address. Not used when UseDefaultAddress
isTRUE .
StationPort The port number to which this EFI UDPv4 Protocol instance is bound. If a client of the EFI UDPv4
Protocol does not care about the port number, set StationPort to zero. The EFI UDPv4 Protocol driver will
assign a random port number to transmitted UDP packets. Ignored if AcceptAnyPort is set to TRUE .
RemoteAddress The IP address of remote host to which this EFI UDPv4 Protocol instance is connecting. If Re-
moteAddress is not 0.0.0.0, this EFI UDPv4 Protocol instance will be connected to RemoteAddress; i.e., out-
going packets of this EFI UDPv4 Protocol instance will be sent to this address by default and only incoming
packets from this address will be delivered to client. Ignored for incoming ﬁltering if AcceptPromiscuous is
TRUE .
RemotePort The port number of the remote host to which this EFI UDPv4 Protocol instance is connecting. If it is not
zero, outgoing packets of this EFI UDPv4 Protocol instance will be sent to this port number by default and only
incoming packets from this port will be delivered to client. Ignored if RemoteAddress is 0.0.0.0 and ignored for
incoming ﬁltering if AcceptPromiscuous isTRUE .
30.1. EFI UDP Protocol 1335Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.1 – continued from previous page
EFI_NOT_STARTED When Udp4ConﬁgData is queried, no conﬁguration data is available be-
cause this instance has not been started.
30.1.2.3 EFI_UDP4_PROTOCOL.Conﬁgure()
Summary
• Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv4 Protocol.
Prototype
typedef
(EFIAPI *EFI_UDP4_CONFIGURE) (
IN EFI_UDP4_CONFIG_DATA *UdpConfigData OPTIONAL
);
UdpConﬁgData Pointer to the buffer to receive the current mode data.
TheConﬁgure() function is used to do the following:
• Initialize and start this instance of the EFI UDPv4 Protocol.
• Change the ﬁltering rules and operational parameters.
• Reset this instance of the EFI UDPv4 Protocol.
Until these parameters are initialized, no network trafﬁc can be sent or received by this instance. This instance can be
also reset by calling Conﬁgure() with UdpConﬁgData set to NULL . Once reset, the receiving queue and transmitting
queue are ﬂushed and no trafﬁc is allowed through this instance.
With different parameters in UdpConﬁgData ,Conﬁgure() can be used to bind this instance to speciﬁed port.
EFI_SUCCESS The conﬁguration settings were set, changed, or reset successfully.
•UdpConﬁgData.StationAddress is not a valid unicast IPv4 address.
•UdpConﬁgData.SubnetMask is not a valid IPv4 address mask. The
subnet mask must be contiguous.
•UdpConﬁgData.RemoteAddress is not a valid unicast IPv4 address if it is
not zero.
30.1. EFI UDP Protocol 1336Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.2 – continued from previous page
EFI_ALREADY_STARTED The EFI UDPv4 Protocol instance is already started/conﬁgured and must be
stopped/reset before it can be reconﬁgured. Only TypeOfService ,TimeTo-
Live,DoNotFragment ,ReceiveTimeout , and TransmitTimeout can be recon-
ﬁgured without stopping the current instance of the EFI UDPv4 Protocol.
EFI_ACCESS_DENIED UdpConﬁgData. AllowDuplicatePort isFALSE and UdpConﬁg-
Data.StationPort is already used by other instance.
EFI_OUT_OF_RESOURCES The EFI UDPv4 Protocol driver cannot allocate memory for this EFI
UDPv4 Protocol instance.
EFI_DEVICE_ERROR An unexpected network or system error occurred and this instance was not
opened.
30.1.2.4 EFI_UDP4_PROTOCOL.Groups()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP4_GROUPS) (
IN EFI_IPv4_ADDRESS *MulticastAddress OPTIONAL
);
JoinFlag Set to TRUE to join a multicast group. Set to FALSE to leave one or all multicast groups.
MulticastAddress Pointer to multicast group address to join or leave.
TheGroups() function is used to enable and disable the multicast group ﬁltering.
If the JoinFlag isFALSE and the MulticastAddress isNULL , then all currently joined groups are left.
EFI_NOT_STARTED The EFI UDPv4 Protocol instance has not been started.
EFI_OUT_OF_RESOURCES Could not allocate resources to join the group.
• JoinFlag is TRUE and MulticastAddress is NULL.
• JoinFlag is TRUE and *MulticastAddress is not a valid multicast address.
EFI_ALREADY_STARTED The group address is already in the group table (when JoinFlag is TRUE).
30.1. EFI UDP Protocol 1337Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.3 – continued from previous page
EFI_NOT_FOUND The group address is not in the group table (when JoinFlag is FALSE).
30.1.2.5 EFI_UDP4_PROTOCOL.Routes()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP4_ROUTES) (
);
table. DestinationAddress andSubnetMask are used as the key to each route entry.
SubnetAddress The destination network address that needs to be routed.
GatewayAddress The gateway IP address for this route.
Routes are determined by comparing the SubnetAddress with the destination IP address and arithmetically AND -ing
it with the SubnetMask . The gateway address must be on the same subnet as the conﬁgured station address.
destination IP addresses that do not match any other routes.
A zero GatewayAddress is a nonroute. Packets are sent to the destination IP address if it can be found in the Address
Resolution Protocol (ARP) cache or on the local subnet. One automatic nonroute entry will be inserted into the routing
table for outgoing packets that are addressed to a local subnet (gateway address of 0.0.0.0).
Each instance of the EFI UDPv4 Protocol has its own independent routing table. Instances of the EFI

UDPv4 Protocol that use the default IP address will also have copies of the routing table provided by the
EFI_IP4_CONFIG2_PROTOCOL . These copies will be updated automatically whenever the IP driver reconﬁgures
its instances; as a result, the previous modiﬁcation to these copies will be lost.
NOTE :There is no way to set up routes to other network interface cards (NICs) because each NIC has its own
independent network stack that shares information only through EFI UDP4 Variable.
30.1. EFI UDP Protocol 1338Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.4 – continued from previous page
•SubnetAddress is not a valid subnet address.
•GatewayAddress is not a valid unicast IP address.
30.1.2.6 EFI_UDP4_PROTOCOL.Transmit()
Summary
Queues outgoing data packets into the transmit queue.
Prototype
typedef
(EFIAPI *EFI_UDP4_TRANSMIT) (
IN EFI_UDP4_COMPLETION_TOKEN *Token
);
Token Pointer to the completion token that will be placed into the transmit queue. Type
EFI_UDP4_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions” below.
TheTransmit() function places a sending request to this instance of the EFI UDPv4 Protocol, alongside the transmit
data that was ﬁlled by the user. Whenever the packet in the token is sent out or some errors occur, the Token.Event will
be signaled and Token.Status is updated. Providing a proper notiﬁcation function and context for the event will enable
the user to receive the notiﬁcation and transmitting status.
// EFI_UDP4_COMPLETION_TOKEN
union {
30.1. EFI UDP Protocol 1339Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_UDP4_RECEIVE_DATA *RxData;
EFI_UDP4_TRANSMIT_DATA *TxData;
} Packet;
} EFI_UDP4_COMPLETION_TOKEN;
Event This Event will be signaled after the Status ﬁeld is updated by the EFI UDPv4 Protocol driver. The type of
Event must be EVT_NOTIFY_SIGNAL . The Task Priority Level (TPL) of Event must be lower than or equal to
EFI_SUCCESS. The receive or transmit operation completed successfully.
EFI_NETWORK_UNREACHABLE. The destination network is unreachable. RxData is set to NULL in this
situation.
EFI_HOST_UNREACHABLE. The destination host is unreachable. RxData is set to NULL in this situation.
EFI_PROTOCOL_UNREACHABLE. The UDP protocol is unsupported in the remote system. RxData is set to
NULL in this situation.
EFI_PORT_UNREACHABLE. No service is listening on the remote port. RxData is set to NULL in this
EFI_ICMP_ERROR. Some other Internet Control Message Protocol (ICMP) error report was received. For
example, packets are being sent too fast for the destination to receive them and the destination sent an ICMP
source quench report. RxData is set to NULL in this situation.
EFI_NO_MEDIA . There was a media error.
RxData When this token is used for receiving, RxData is a pointer to EFI_UDP4_RECEIVE_DATA . Type
EFI_UDP4_RECEIVE_DATA is deﬁned below.
TxData When this token is used for transmitting, TxData is a pointer to EFI_UDP4_TRANSMIT_DATA . Type
EFI_UDP4_TRANSMIT_DATA is deﬁned below.
TheEFI_UDP4_COMPLETION_TOKEN structures are used for both transmit and receive operations.
When used for transmitting, the Event andTxData ﬁelds must be ﬁlled in by the EFI UDPv4 Protocol client. After the
transmit operation completes, the Status ﬁeld is updated by the EFI UDPv4 Protocol and the Event is signaled.
• When used for receiving, only the Event ﬁeld must be ﬁlled in by the EFI UDPv4 Protocol client. After a packet
is received, RxData andStatus are ﬁlled in by the EFI UDPv4 Protocol and the Event is signaled.
• The ICMP related status codes ﬁlled in Status are deﬁned as follows:
// UDP4 Token Status definition
#define EFI_NETWORK_UNREACHABLE EFIERR(100)
#define EFI_HOST_UNREACHABLE EFIERR(101)
#define EFI_PROTOCOL_UNREACHABLE EFIERR(102)
#define EFI_PORT_UNREACHABLE EFIERR(103)
// EFI_UDP4_RECEIVE_DATA
30.1. EFI UDP Protocol 1340Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_UDP4_SESSION_DATA UdpSession;
EFI_UDP4_FRAGMENT_DATA FragmentTable[1];
} EFI_UDP4_RECEIVE_DATA;
TimeStamp Time when the EFI UDPv4 Protocol accepted the packet. TimeStamp is zero ﬁlled if timestamps are
disabled or unsupported
RecycleSignal Indicates the event to signal when the received data has been processed.
UdpSession The UDP session data including SourceAddress ,SourcePort ,DestinationAddress , and DestinationPort .
Type EFI_UDP4_SESSION_DATA is deﬁned below.
DataLength The sum of the fragment data length.
FragmentCount Number of fragments. May be zero.
FragmentTable Array of fragment descriptors. IP and UDP headers are included in these buffers if Conﬁg-
Data.RawData isTRUE . Otherwise they are stripped. May be zero. Type EFI_UDP4_FRAGMENT_DATA
EFI_UDP4_RECEIVE_DATA is ﬁlled by the EFI UDPv4 Protocol driver when this EFI UDPv4 Protocol instance
receives an incoming packet. If there is a waiting token for incoming packets, the CompletionToken.Packet.RxData
ﬁeld is updated to this incoming packet and the CompletionToken.Event is signaled. The EFI UDPv4 Protocol client
must signal the RecycleSignal after processing the packet.
•FragmentTable could contain multiple buffers that are not in the continuous memory locations. The EFI UDPv4
Protocol client might need to combine two or more buffers in FragmentTable to form their own protocol header.
// EFI_UDP4_SESSION_DATA
UINT16 SourcePort;
UINT16 DestinationPort;
} EFI_UDP4_SESSION_DATA;
SourceAddress Address from which this packet is sent. If this ﬁeld is set to zero when sending packets, the address
that is assigned in EFI_UDP4_PROTOCOL .Conﬁgure() is used.
SourcePort Port from which this packet is sent. It is in host byte order. If this ﬁeld is set to zero when sending
packets, the port that is assigned in EFI_UDP4_PROTOCOL .Conﬁgure() is used. If this ﬁeld is set to zero and
unbound, a call to EFI_UDP4_PROTOCOL.Transmit() will fail.
DestinationAddress Address to which this packet is sent.
DestinationPort Port to which this packet is sent. It is in host byte order. If this ﬁeld is set to zero and unconnected,
the call to EFI_UDP4_PROTOCOL .Transmit() will fail.
The EFI_UDP4_SESSION_DATA is used to retrieve the settings when receiving packets or to override the existing
settings of this EFI UDPv4 Protocol instance when sending packets.
30.1. EFI UDP Protocol 1341Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_UDP4_FRAGMENT_DATA
} EFI_UDP4_FRAGMENT_DATA;
FragmentLength Length of the fragment data buffer.
FragmentBuffer Pointer to the fragment data buffer.
EFI_UDP4_FRAGMENT_DATA allows multiple receive or transmit buffers to be speciﬁed. The purpose of this struc-
ture is to avoid copying the same packet multiple times.
// EFI_UDP4_TRANSMIT_DATA
EFI_UDP4_SESSION_DATA *UdpSessionData;
EFI_IPv4_ADDRESS *GatewayAddress;
} EFI_UDP4_TRANSMIT_DATA;

UdpSessionData If not NULL , the data that is used to override the transmitting settings. Type
EFI_UDP4_SESSION_DATA is deﬁned above.
GatewayAddress The next-hop address to override the setting from the routing table.
DataLength Sum of the fragment data length. Must not exceed the maximum UDP packet size.
FragmentTable Array of fragment descriptors. Type EFI_UDP4_FRAGMENT_DATA is deﬁned above.
The EFI UDPv4 Protocol client must ﬁll this data structure before sending a packet. The packet may contain multiple
buffers that may be not in a continuous memory location.
EFI_NOT_STARTED This EFI UDPv4 Protocol instance has not been started.
30.1. EFI UDP Protocol 1342Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.5 – continued from previous page
•Token.Packet.TxData.FragmentCount is zero.
•Token.Packet.TxData.DataLength is not equal to the sum of fragment
lengths.
• One or more of the Token.Packet.TxDat
a.FragmentTable[].FragmentLength ﬁelds is zero.
a.FragmentTable[].FragmentBuffer ﬁelds is NULL .
•Token.Packet.TxData. GatewayAddress is not a unicast IPv4 address if it
•Token.Packet.TxD ata.UdpSessionData.SourceAddress is not a valid
unicast IPv4 address or Token.Packet.TxData.U
dpSessionData.DestinationAddress is zero if the UdpSessionData is not
NULL .
full.
EFI_NOT_FOUND There is no route to the destination network or address.
EFI_BAD_BUFFER_SIZE The data length is greater than the maximum UDP packet size. Or the length
of the IP header + UDP header + data length is greater than MTU if DoNot-
Fragment isTRUE .
30.1.2.7 EFI_UDP4_PROTOCOL.Receive()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP4_RECEIVE) (
);
Token Pointer to a token that is associated with the receive data descriptor. Type
EFI_UDP4_COMPLETION_TOKEN is deﬁned in EFI_UDP4_PROTOCOL .Transmit() .
30.1. EFI UDP Protocol 1343Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
operation completes, the EFI UDPv4 Protocol driver updates the Token.Status andToken.Packet.RxData ﬁelds and
theToken.Event is signaled. Providing a proper notiﬁcation function and context for the event will enable the user to
receive the notiﬁcation and receiving status. That notiﬁcation function is guaranteed to not be re-entered.
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI UDPv4 Protocol
EFI_ACCESS_DENIED A receive completion token with the same Token.Event was already in the
30.1.2.8 EFI_UDP4_PROTOCOL.Cancel()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP4_CANCEL)(
IN EFI_UDP4_COMPLETION_TOKEN *Token OPTIONAL
);
Token Pointer to a token that has been issued by EFI_UDP4_PROTOCOL .Transmit() or
EFI_UDP4_PROTOCOL.Receive() .If NULL , all pending tokens are aborted. Type
EFI_UDP4_COMPLETION_TOKEN is deﬁned in EFI_UDP4_PROTOCOL.Transmit() .
30.1. EFI UDP Protocol 1344Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
When Token isNULL , all pending requests are aborted and their events are
signaled.
30.1.2.9 EFI_UDP4_PROTOCOL.Poll()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP4_POLL) (
IN EFI_UDP4_PROTOCOL *This
);
30.1. EFI UDP Protocol 1345Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
30.2 EFI UDPv6 Protocol
This section deﬁnes the EFI UDPv6 (User Datagram Protocol version 6) Protocol that interfaces over the EFI IPv6
Protocol.
30.2.1 UDP6 Service Binding Protocol
30.2.1.1 EFI_UDP6_SERVICE_BINDING_PROTOCOL
Summary
The EFI UDPv6 Service Binding Protocol is used to locate communication devices that are supported by an EFI
UDPv6 Protocol driver and to create and destroy instances of the EFI UDPv6 Protocol child instance that uses the
GUID
#define EFI_UDP6_SERVICE_BINDING_PROTOCOL_GUID \
{0x66ed4721, 0x3c98, 0x4d3e,\
{0x81, 0xe3, 0xd0, 0x3d, 0xd3, 0x9a, 0x72, 0x54}}
Descriptopn
A network application that requires basic UDPv6 I/O services can use one of the protocol handler services, such as
BS->LocateHandleBuffer() , to search for devices that publish a EFI UDPv6 Service Binding Protocol GUID. Each
device with a published EFI UDPv6 Service Binding Protocol GUID supports the EFI UDPv6 Protocol and may be
After a successful call to the EFI_UDP6_SERVICE_BINDING_PROTOCOL.CreateChild() function, the newly cre-
ated child EFI UDPv6 Protocol driver is in an un-conﬁgured state; it is not ready to send and receive data packets.
EFI_UDP6_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_UDP6_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
30.2.2 EFI UDP6 Protocol
30.2.2.1 EFI_UDP6_PROTOCOL
Summary
The EFI UDPv6 Protocol provides simple packet-oriented services to transmit and receive UDP packets.
GUID
#define EFI_UDP6_PROTOCOL_GUID \
{0x4f948815, 0xb4b9, 0x43cb,\
{0x8a, 0x33, 0x90, 0xe0, 0x60, 0xb3, 0x49, 0x55}}
typedef struct _EFI_UDP6_PROTOCOL {
EFI_UDP6_GET_MODE_DATA GetModeData;
EFI_UDP6_CONFIGURE Configure;
EFI_UDP6_GROUPS Groups;

Summary
GUID
30.2. EFI UDPv6 Protocol 1346Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_UDP6_TRANSMIT Transmit;
EFI_UDP6_RECEIVE Receive;
EFI_UDP6_CANCEL Cancel;
EFI_UDP6_POLL Poll;
} EFI_UDP6_PROTOCOl;
Conﬁgure Initializes, changes, or resets operational settings for the EFI UDPv6 Protocol. See the Conﬁgure() func-
Transmit Queues outgoing data packets into the transmit queue. This function is a non-blocked operation. See the
Receive Places a receiving request token into the receiving queue. This function is a non-blocked operation. See the
TheEFI_UDP6_PROTOCOL deﬁnes an EFI UDPv6 Protocol session that can be used by any network drivers, appli-
cations, or daemons to transmit or receive UDP packets. This protocol instance can either be bound to a speciﬁed port
as a service or connected to some remote peer as an active client. Each instance has its own settings, such as group
table, that are independent from each other.
Note: Byte Order: In this document, all IPv6 addresses and incoming/outgoing packets are stored in network byte
order. All other parameters in the functions and data structures that are deﬁned in this document are stored in host byte
order.
30.2.2.2 EFI_UDP6_PROTOCOL.GetModeData()
Summary
Read the current operational settings.
Prototype
typedef
(EFIAPI *EFI_UDP6_GET_MODE_DATA) (
IN EFI_UDP6_PROTOCOL *This,
OUT EFI_UDP6_CONFIG_DATA *Udp6ConfigData OPTIONAL,
);
This Pointer to the EFI_UDP6_PROTOCOL instance.
30.2. EFI UDPv6 Protocol 1347Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Udp6ConﬁgData The buffer in which the current UDP conﬁguration data is returned. Type
EFI_UDP6_CONFIG_DATA is deﬁned in “Related Deﬁnitions” below.
Ip6ModeData The buffer in which the current EFI IPv6 Protocol mode data is returned. Type
MnpConﬁgData The buffer in which the current managed network conﬁguration data
is returned. Type EFI_MANAGED_NETWORK_CONFIG_DATA is deﬁned in
SnpModeData The buffer in which the simple network mode data is returned. Type
EFI_SIMPLE_NETWORK_MODE is deﬁned in the EFI_SIMPLE_NETWORK Protocol.
TheGetModeData() function copies the current operational settings of this EFI UDPv6 Protocol instance into user-
drivers.
********************************************************
// EFI_UDP6_CONFIG_DATA
//
//I/O parameters
;
;
//Access Point
} EFI_UDP6_CONFIG_DATA;
AllowDuplicatePort Set to TRUE to allow this EFI UDPv6 Protocol child instance to open a port number that is
already being used by another EFI UDPv6 Protocol child instance.
30.2. EFI UDPv6 Protocol 1348Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
StationAddress The station IP address that will be assigned to this EFI UDPv6 Protocol instance. The EFI UDPv6
and EFI IPv6 Protocol drivers will only deliver incoming packets whose destination matches this IP address
exactly. Address 0:/128 is also accepted as a special case. Under this situation, underlying IPv6 driver is
responsible for binding a source address to this EFI IPv6 protocol instance according to source address selection
algorithm. Only incoming packet from the selected source address is delivered. This ﬁeld can be set and changed
only when the EFI IPv6 driver is transitioning from the stopped to the started states. If no address is available for
selecting, the EFI IPv6 Protocol driver will use EFI_IP6_CONFIG_PROTOCOL to retrieve the IPv6 address.
StationPort The port number to which this EFI UDPv6 Protocol instance is bound. If a client of the EFI UDPv6
Protocol does not care about the port number, set StationPort to zero. The EFI UDPv6 Protocol driver will
assign a random port number to transmitted UDP packets. Ignored it if AcceptAnyPort isTRUE .
RemoteAddress The IP address of remote host to which this EFI UDPv6 Protocol instance is connecting. If Re-
moteAddress is not 0:/128, this EFI UDPv6 Protocol instance will be connected to RemoteAddress; i.e., outgoing
packets of this EFI UDPv6 Protocol instance will be sent to this address by default and only incoming packets
from this address will be delivered to client. Ignored for incoming ﬁltering if AcceptPromiscuous isTRUE .
RemotePort The port number of the remote host to which this EFI UDPv6 Protocol instance is connecting. If it is not
zero, outgoing packets of this EFI UDPv6 Protocol instance will be sent to this port number by default and only
incoming packets from this port will be delivered to client. Ignored if RemoteAddress is 0:/128 and ignored for
EFI_NOT_STARTED When Udp6ConﬁgData is queried, no conﬁguration data is available be-
30.2.2.3 EFI_UDP6_PROTOCOL.Conﬁgure()
Summary
Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv6 Protocol.
Prototype
typedef
(EFIAPI *EFI_UDP6_CONFIGURE) (
IN EFI_UDP6_CONFIG_DATA *UdpConfigData OPTIONAL
);
UdpConﬁgData Pointer to the buffer contained the conﬁguration data.
• Initialize and start this instance of the EFI UDPv6 Protocol.
• Reset this instance of the EFI UDPv6 Protocol.
30.2. EFI UDPv6 Protocol 1349Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UdpConﬁgData.StationAddress neither zero nor one of the conﬁgured IP
addresses in the underlying IPv6 driver.
UdpConﬁgData.RemoteAddress is not a valid unicast IPv6 address if it is
not zero.
EFI_ALREADY_STARTED The EFI UDPv6 Protocol instance is already started/conﬁgured and must
be stopped/reset before it can be reconﬁgured. Only TrafﬁcClass ,HopLimit ,
ReceiveTimeout , and TransmitTimeout can be reconﬁgured without stopping
the current instance of the EFI UDPv6 Protocol.
EFI_OUT_OF_RESOURCES The EFI UDPv6 Protocol driver cannot allocate memory for this EFI
UDPv6 Protocol instance.
opened.
30.2.2.4 EFI_UDP6_PROTOCOL.Groups()
Summary
Prototype
typedef

not zero.
opened.
Summary
Prototype
typedef
(EFIAPI *EFI_UDP6_GROUPS) (
IN EFI_IPv6_ADDRESS *MulticastAddress OPTIONAL
);
TheGroups () function is used to join or leave one or more multicast group.
30.2. EFI UDPv6 Protocol 1350Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_NOT_STARTED The EFI UDPv6 Protocol instance has not been started.
JoinFlag isTRUE andMulticastAddress is*NULL* .
JoinFlag isTRUE and **MulticastAddress* is not a valid multicast
address.
30.2.2.5 EFI_UDP6_PROTOCOL.Transmit()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP6_TRANSMIT) (
IN EFI_UDP6_COMPLETION_TOKEN *Token
);
EFI_UDP6_COMPLETION_TOKEN is deﬁned in “Related Deﬁnitions” below.
TheTransmit() function places a sending request to this instance of the EFI UDPv6 Protocol, alongside the transmit
// EFI_UDP6_COMPLETION_TOKEN
union {
EFI_UDP6_RECEIVE_DATA *RxData;
30.2. EFI UDPv6 Protocol 1351Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_UDP6_TRANSMIT_DATA *TxData;
} Packet;
} EFI_UDP6_COMPLETION_TOKEN;
Event This Event will be signaled after the Status ﬁeld is updated by the EFI UDPv6 Protocol driver. The type of
Event must be EVT_NOTIFY_SIGNAL .
EFI_SUCCESS : The receive or transmit operation completed successfully.
EFI_ABORTED : The receive or transmit was aborted.
EFI_TIMEOUT : The transmit timeout expired.
EFI_NETWORK_UNREACHABLE : The destination network is unreachable. RxData is set to NULL in this
EFI_HOST_UNREACHABLE : The destination host is unreachable. RxData is set to NULL in this situation.
EFI_PROTOCOL_UNREACHABLE : The UDP protocol is unsupported in the remote system. RxData is set to
EFI_PORT_UNREACHABLE : No service is listening on the remote port. RxData is set to NULL in this
EFI_ICMP_ERROR : Some other Internet Control Message Protocol (ICMP) error report was received. For
EFI_SECURITY_VIOLATION : The transmit or receive was failed because of IPsec policy check.
RxData When this token is used for receiving, RxData is a pointer to EFI_UDP6_RECEIVE_DATA . Type
EFI_UDP6_RECEIVE_DATA is deﬁned below.
TxData When this token is used for transmitting, TxData is a pointer to EFI_UDP6_TRANSMIT_DATA . Type
EFI_UDP6_TRANSMIT_DATA is deﬁned below.
TheEFI_UDP6_COMPLETION_TOKEN structures are used for both transmit and receive operations.
When used for transmitting, the Event andTxData ﬁelds must be ﬁlled in by the EFI UDPv6 Protocol client. After the
transmit operation completes, the Status ﬁeld is updated by the EFI UDPv6 Protocol and the Event is signaled.
When used for receiving, only the Event ﬁeld must be ﬁlled in by the EFI UDPv6 Protocol client. After a packet is
received, RxData andStatus are ﬁlled in by the EFI UDPv6 Protocol and the Event is signaled.
// EFI_UDP6_RECEIVE_DATA
EFI_UDP6_SESSION_DATA UdpSession;
EFI_UDP6_FRAGMENT_DATA FragmentTable [1];
} EFI_UDP6_RECEIVE_DATA;
TimeStamp Time when the EFI UDPv6 Protocol accepted the packet. TimeStamp is zero ﬁlled if timestamps are
30.2. EFI UDPv6 Protocol 1352Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UdpSession The UDP session data including SourceAddress ,SourcePort ,DestinationAddress , and DestinationPort.
Type EFI_UDP6_SESSION_DATA is deﬁned below.
FragmentCount Number of fragments. Maybe zero.
FragmentTable Array of fragment descriptors. Maybe zero. Type EFI_UDP6_FRAGMENT_DATA is deﬁned below.
EFI_UDP6_RECEIVE_DATA is ﬁlled by the EFI UDPv6 Protocol driver when this EFI UDPv6 Protocol instance
ﬁeld is updated to this incoming packet and the CompletionToken.Event is signaled. The EFI UDPv6 Protocol client
FragmentTable could contain multiple buffers that are not in the continuous memory locations. The EFI UDPv6
// EFI_UDP6_SESSION_DATA
} EFI_UDP6_SESSION_DATA;
SourceAddress Address from which this packet is sent. This ﬁled should not be used when sending packets.
SourcePort Port from which this packet is sent. It is in host byte order. This ﬁled should not be used when sending
packets.
DestinationAddress Address to which this packet is sent. When sending packet, it’ll be ignored if it is zero.
DestinationPort Port to which this packet is sent. When sending packet, it’ll be ignored if it is zero.
The EFI_UDP6_SESSION_DATA is used to retrieve the settings when receiving packets or to override the existing
settings (only DestinationAddress and DestinationPort can be overridden) of this EFI UDPv6 Protocol instance when
sending packets.
//*********************************************************
// EFI_UDP6_FRAGMENT_DATA
} EFI_UDP6_FRAGMENT_DATA;
EFI_UDP6_FRAGMENT_DATA allows multiple receive or transmit buffers to be speciﬁed. The purpose of this struc-
// EFI_UDP6_TRANSMIT_DATA
30.2. EFI UDPv6 Protocol 1353Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_UDP6_SESSION_DATA *UdpSessionData;
} EFI_UDP6_TRANSMIT_DATA;
UdpSessionData If not NULL , the data that is used to override the transmitting settings.Only the two ﬁled UdpSes-
sionData.DestinationAddress andUdpSessionData.DestionPort can be used as the transmitting setting ﬁled. Type
EFI_UDP6_SESSION_DATA is deﬁned above.
FragmentTable Array of fragment descriptors. Type EFI_UDP6_FRAGMENT_DATA is deﬁned above.
The EFI UDPv6 Protocol client must ﬁll this data structure before sending a packet. The packet may contain multiple

EFI_NOT_STARTED This EFI UDPv6 Protocol instance has not been started.
Token.Packet.TxData isNULL .
Token.Packet.TxData.FragmentCount is zero.
Token.Packet.TxData.DataLength is not equal to the sum of fragment
lengths.
One or more of the Token.Packet.TxDat
Token.Packet.TxData.UdpSessionData. DestinationAddress is not zero and
is not valid unicast Ipv6 address if UdpSessionData is not NULL .
Token.Packet.TxData.UdpSessionData is NULL and this instance’s
UdpConﬁgData. RemoteAddress is unspeciﬁed.
Token.Packet.TxData. UdpSessionData.DestinationAddress is non-zero
when DestinationAddress is conﬁgured as non-zero when doing
Conﬁgure() for this EFI Udp6 protocol instance.
Token.Packet.TxData.UdpSesionData.DestinationAddress is zero when
Udp6 protocol instance
30.2. EFI UDPv6 Protocol 1354Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.12 – continued from previous page
full.
EFI_BAD_BUFFER_SIZE The data length is greater than the maximum UDP packet size.
30.2.2.6 EFI_UDP6_PROTOCOL.Receive()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP6_RECEIVE) (
IN EFI_UDP6_COMPLETION_TOKEN *Token*
);
EFI_UDP6_COMPLETION_TOKEN is deﬁned in EFI_UDP6_PROTOCOL.Transmit() .
operation completes, the EFI UDPv6 Protocol driver updates the Token.Status andToken.Packet.RxData ﬁelds and
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI UDPv6 Protocol
30.2. EFI UDPv6 Protocol 1355Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.13 – continued from previous page
30.2.2.7 EFI_UDP6_PROTOCOL.Cancel()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP6_CANCEL)(
IN EFI_UDP6_COMPLETION_TOKEN *Token OPTIONAL
);
Token Pointer to a token that has been issued by EFI_UDP6_PROTOCOL.Transmit() or
EFI_UDP6_PROTOCOL.Receive() .If NULL , all pending tokens are aborted. Type
signaled.
30.2. EFI UDPv6 Protocol 1356Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
30.2.2.8 EFI_UDP6_PROTOCOL.Poll()
Summary
Prototype
typedef
(EFIAPI *EFI_UDP6_POLL) (
IN EFI_UDP6_PROTOCOL *This
);
30.3 EFI MTFTPv4 Protocol
The following sections deﬁnes the EFI MTFTPv4 Protocol interface that is built upon the EFI UDPv4 Protocol.
30.3.1 EFI_MTFTP4_SERVICE_BINDING_PROTOCOL
Summary
The EFI MTFTPv4 Service Binding Protocol is used to locate communication devices that are supported by an EFI
MTFTPv4 Protocol driver and to create and destroy instances of the EFI MTFTPv4 Protocol child protocol driver that
can use the underlying communications device.
GUID
#define EFI_MTFTP4_SERVICE_BINDING_PROTOCOL_GUID \
{0x2e800be,0x8f01,0x4aa6,\
{0x94,0x6b,0xd7,0x13,0x88,0xe1,0x83,0x3f}}
A network application or driver that requires MTFTPv4 I/O services can use one of the protocol handler services, such
asBS->LocateHandleBuffer() , to search for devices that publish an EFI MTFTPv4 Service Binding Protocol GUID.
30.3. EFI MTFTPv4 Protocol 1357Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Each device with a published EFI MTFTPv4 Service Binding Protocol GUID supports the EFI MTFTPv4 Protocol
service and may be available for use.
After a successful call to the EFI_MTFTP4_SERVICE_BINDING_PROTOCOL.CreateChild() function, the newly
created child EFI MTFTPv4 Protocol driver instance is in an unconﬁgured state; it is not ready to transfer data.
EFI_MTFTP4_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_MTFTP4_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
Each instance of the EFI MTFTPv4 Protocol driver can support one ﬁle transfer operation at a time. To download two
ﬁles at the same time, two instances of the EFI MTFTPv4 Protocol driver will need to be created.
30.3.2 EFI_MTFTP4_PROTOCOL
Summary
The EFI MTFTPv4 Protocol provides basic services for client-side unicast and/or multicast TFTP operations.
GUID
#define EFI_MTFTP4_PROTOCOL_GUID \
{0x78247c57,0x63db,0x4708,\
{0x99,0xc2,0xa8,0xb4,0xa9,0xa6,0x1f,0x6b}}
typedef struct _EFI_MTFTP4_PROTOCOL {
EFI_MTFTP4_GET_MODE_DATA GetModeData;
EFI_MTFTP4_CONFIGURE Configure;
EFI_MTFTP4_GET_INFO GetInfo;
EFI_MTFTP4_PARSE_OPTIONS ParseOptions;
EFI_MTFTP4_READ_FILE ReadFile;
EFI_MTFTP4_WRITE_FILE WriteFile;
EFI_MTFTP4_READ_DIRECTORY ReadDirectory;
EFI_MTFTP4_POLL Poll;
} EFI_MTFTP4_PROTOCOL;

Summary
GUID
Conﬁgure Initializes, changes, or resets the operational settings for this instance of the EFI MTFTPv4 Protocol driver.
See the Conﬁgure() function description.
GetInfo Retrieves information about a ﬁle from an MTFTPv4 server. See the GetInfo() function description.
ParseOptions Parses the options in an MTFTPv4 OACK (options acknowledgement) packet. See the ParseOptions()
ReadFile Downloads a ﬁle from an MTFTPv4 server. See the ReadFile() function description.
WriteFile Uploads a ﬁle to an MTFTPv4 server. This function may be unsupported in some EFI implementations.
See the WriteFile() function description.
ReadDirectory Downloads a related ﬁle “directory” from an MTFTPv4 server. This function may be unsupported in
some EFI implementations. See the ReadDirectory() function description.
30.3. EFI MTFTPv4 Protocol 1358Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheEFI_MTFTP4_PROTOCOL is designed to be used by UEFI drivers and applications to transmit and receive data
ﬁles. The EFI MTFTPv4 Protocol driver uses the underlying EFI UDPv4 Protocol driver and EFI IPv4 Protocol driver.
30.3.3 EFI_MTFTP4_PROTOCOL.GetModeData()
Summary
Prototype
typedef
(EFIAPI *EFI_MTFTP4_GET_MODE_DATA)(
IN EFI_MTFTP4_PROTOCOL *This,
OUT EFI_MTFTP4_MODE_DATA *ModeData
);
This Pointer to the EFI_MTFTP4_PROTOCOL instance.
ModeData Pointer to storage for the EFI MTFTPv4 Protocol driver mode data. Type EFI_MTFTP4_MODE_DATA
TheGetModeData() function reads the current operational settings of this EFI MTFTPv4 Protocol driver instance.
// EFI_MTFTP4_MODE_DATA
EFI_MTFTP4_CONFIG_DATA ConfigData;
UINT8 SupportedOptionCount;
UINT8 **SupportedOptions;
UINT8 UnsupportedOptionCount;
UINT8 **UnsupportedOptions;
} EFI_MTFTP4_MODE_DATA;
ConﬁgData The conﬁguration data of this instance. Type EFI_MTFTP4_CONFIG_DATA is deﬁned below.
SupportedOptionCount The number of option strings in the following SupportedOptions array.
SupportedOptions An array of pointers to null-terminated ASCII option strings that are recognized and supported
by this EFI MTFTPv4 Protocol driver implementation.
UnsupportedOptionCount An array of pointers to null-terminated ASCII option strings that are recognized but not
supported by this EFI MTFTPv4 Protocol driver implementation.
UnsupportedOptions An array of option strings that are recognized but are not supported by this EFI MTFTPv4
Protocol driver implementation.
TheEFI_MTFTP4_MODE_DATA structure describes the operational state of this instance.
30.3. EFI MTFTPv4 Protocol 1359Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_MTFTP4_CONFIG_DATA
UINT16 InitialServerPort;
UINT16 TryCount;
UINT16 TimeoutValue;
} EFI_MTFTP4_CONFIG_DATA;
UseDefaultSetting Set to TRUE to use the default station address/subnet mask and the default route table informa-
tion.
StationIp IfUseDefaultSetting isFALSE , indicates the station address to use.
SubnetMask IfUseDefaultSetting isFALSE , indicates the subnet mask to use.
GatewayIp IfUseDefaultSetting isFALSE , indicates the gateway IP address to use.
ServerIp The IP address of the MTFTPv4 server.
InitialServerPort The initial MTFTPv4 server port number. Request packets are sent to this port. This number is
almost always 69 and using zero defaults to 69.
TryCount The number of times to transmit MTFTPv4 request packets and wait for a response.
TimeoutValue The number of seconds to wait for a response after sending the MTFTPv4 request packet.
TheEFI_MTFTP4_CONFIG_DATA structure is used to report and change MTFTPv4 session parameters.
EFI_SUCCESS The conﬁguration data was successfully returned.
EFI_INV ALID_PARAMETER This isNULL orModeData isNULL .
30.3.4 EFI_MTFTP4_PROTOCOL.Conﬁgure()
Summary
Initializes, changes, or resets the default operational setting for this EFI MTFTPv4 Protocol driver instance.
Prototype
typedef
(EFIAPI *EFI_MTFTP4_CONFIGURE)(
IN EFI_MTFTP4_CONFIG_DATA *MtftpConfigData OPTIONAL
);
30.3. EFI MTFTPv4 Protocol 1360Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
MtftpConﬁgData Pointer to the conﬁguration data structure. Type EFI_MTFTP4_CONFIG_DATA is deﬁned in
EFI_MTFTP4_PROTOCOL .GetModeData() .
The Conﬁgure() function is used to set and change the conﬁguration data for this EFI MTFTPv4 Protocol driver
instance. The conﬁguration data can be reset to startup defaults by calling Conﬁgure() with MtftpConﬁgData set to
NULL . Whenever the instance is reset, any pending operation is aborted. By changing the EFI MTFTPv4 Protocol
driver instance conﬁguration data, the client can connect to different MTFTPv4 servers. The conﬁguration parameters
inMtftpConﬁgData are used as the default parameters in later MTFTPv4 operations and can be overridden in later
operations.
EFI_SUCCESS The EFI MTFTPv4 Protocol driver was conﬁgured successfully.
•MtftpConﬁgData.UseDefaultSetting isFALSE and
MtftpConﬁgData.StationIp is not a valid IPv4 unicast address.
•MtftpCoﬁgData.UseDefaultSetting isFALSE and
MtftpConﬁgData.SubnetMask is invalid.
•MtftpCoﬁgData.ServerIp is not a valid IPv4 unicast address.
MtftpConﬁgData.GatewayIp is not a valid IPv4 unicast address or is not in
the same subnet with station address.
EFI_ACCESS_DENIED The EFI conﬁguration could not be changed at this time because there is
one MTFTP background operation in progress.
EFI_UNSUPPORTED A conﬁguration protocol (DHCP, BOOTP, RARP, etc.) could not be located
when clients choose to use the default address settings.
EFI_OUT_OF_RESOURCES The EFI MTFTPv4 Protocol driver instance data could not be allocated.
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI MTFTPv4 Pro-
tocol driver instance is not conﬁgured.
30.3.5 EFI_MTFTP4_PROTOCOL.GetInfo()
Summary
Gets information about a ﬁle from an MTFTPv4 server.
Prototype
typedef
(EFIAPI *EFI_MTFTP4_GET_INFO)(
IN EFI_MTFTP4_OVERRIDE_DATA *OverrideData OPTIONAL,
IN UINT8 *Filename,
IN UINT8 *ModeStr OPTIONAL,
IN UINT8 OptionCount,
30.3. EFI MTFTPv4 Protocol 1361Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN EFI_MTFTP4_OPTION *OptionList OPTIONAL,
OUT UINT32 *PacketLength,
OUT EFI_MTFTP4_PACKET **Packet OPTIONAL
);
OverrideData Data that is used to override the existing parameters. If NULL , the default parameters that were set
in the EFI_MTFTP4_PROTOCOL .Conﬁgure() function are used. Type EFI_MTFTP4_OVERRIDE_DATA is
Filename Pointer to a null-terminated ASCII ﬁle name string.
ModeStr Pointer to a null-terminated ASCII mode string. If NULL , “octet” will be used.
OptionCount Number of option/value string pairs in OptionList .
OptionList Pointer to array of option/value string pairs. Ignored if OptionCount is zero. Type
EFI_MTFTP4_OPTION is deﬁned in “Related Deﬁnitions” below.
PacketLength The number of bytes in the returned packet.
Packet The pointer to the received packet. This buffer must be freed by the caller. Type EFI_MTFTP4_PACKET is
TheGetInfo() function assembles an MTFTPv4 request packet with options; sends it to the MTFTPv4 server; and may
return an MTFTPv4 OACK, MTFTPv4 ERROR, or ICMP ERROR packet. Retries occur only if no response packets
are received from the MTFTPv4 server before the timeout expires.
// EFI_MTFTP_OVERRIDE_DATA
} EFI_MTFTP4_OVERRIDE_DATA;

GatewayIp IP address of the gateway. If set to 0.0.0.0, the default gateway address that was set by the
EFI_MTFTP4_PROTOCOL .Conﬁgure() function will not be overridden.
ServerIp IP address of the MTFTPv4 server. If set to 0.0.0.0, it will use the value that was set by the
EFI_MTFTP4_PROTOCOL .Conﬁgure() function.
ServerPort MTFTPv4 server port number. If set to zero, it will use the value that was set by the
TryCount Number of times to transmit MTFTPv4 request packets and wait for a response. If set to zero, it will use
the value that was set by the EFI_MTFTP4_PROTOCOL .Conﬁgure() function.
TimeoutValue Number of seconds to wait for a response after sending the MTFTPv4 request packet. If set to zero, it
will use the value that was set by the EFI_MTFTP4_PROTOCOL .Conﬁgure() function.
30.3. EFI MTFTPv4 Protocol 1362Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The EFI_MTFTP4_OVERRIDE_DATA structure is used to override the existing parameters that were set by the
// EFI_MTFTP4_OPTION
UINT8 *OptionStr;
UINT8 *ValueStr;
} EFI_MTFTP4_OPTION;
OptionStr Pointer to the null-terminated ASCII MTFTPv4 option string.
ValueStr Pointer to the null-terminated ASCII MTFTPv4 value string.
// EFI_MTFTP4_PACKET
EFI_MTFTP4_REQ_HEADER Rrq, Wrq;
EFI_MTFTP4_OACK_HEADER Oack;
EFI_MTFTP4_DATA_HEADER Data;
EFI_MTFTP4_ACK_HEADER Ack;
// This field should be ignored andtreated asreserved
EFI_MTFTP4_DATA8_HEADER Data8;
EFI_MTFTP4_ACK8_HEADER Ack8;
EFI_MTFTP4_ERROR_HEADER Error;
} EFI_MTFTP4_PACKET;
// EFI_MTFTP4_REQ_HEADER
UINT8 Filename[1];
} EFI_MTFTP4_REQ_HEADER;
// EFI_MTFTP4_OACK_HEADER
} EFI_MTFTP4_OACK_HEADER;
// EFI_MTFTP4_DATA_HEADER
UINT16 Block;
} EFI_MTFTP4_DATA_HEADER;
30.3. EFI MTFTPv4 Protocol 1363Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_MTFTP4_ACK_HEADER
UINT16 Block[1];
} EFI_MTFTP4_ACK_HEADER;
// EFI_MTFTP4_DATA8_HEADER
UINT64 Block;
} EFI_MTFTP4_DATA8_HEADER;
// EFI_MTFTP4_ACK8_HEADER
UINT64 Block[1];
} EFI_MTFTP4_ACK8_HEADER;
// EFI_MTFTP4_ERROR_HEADER
UINT16 ErrorCode;
UINT8 ErrorMessage[1];
} EFI_MTFTP4_ERROR_HEADER;
Table, below, Descriptions of Parameters in MTFTPv4 PacketStructures describes the parameters that are listed in the
MTFTPv4 packet structure deﬁnitions above. All the above structures are byte packed. The pragmas may vary from
compiler to compiler. The MTFTPv4 packet structures are also used by the following functions:
•EFI_MTFTP4_PROTOCOL .ReadFile()
•EFI_MTFTP4_PROTOCOL .WriteFile()
•EFI_MTFTP4_PROTOCOL .ReadDirectory()
• The EFI MTFTPv4 Protocol packet check callback functions
NOTE :Both incoming and outgoing MTFTPv4 packets are in network byte order. All other parameters deﬁned in
Table 30.18: Descriptions of Parameters in MTFTPv4 PacketStructures
Data Structure Parameter Description
30.3. EFI MTFTPv4 Protocol 1364Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.18 – continued from previous page
EFI_MTFTP4_PACKET OpCode Type of packets as deﬁned by the MTFTPv4 packet op-
codes. Opcode values are deﬁned below.
Rrq, Wrq Read request or write request packet header. See the de-
scription for EFI_MTFTP4_REQ_HEADER below in
this table
Oack Option acknowledge packet header. See the description
for EFI_MTFTP4_OACK_HEADER below in this ta-
ble.
Data Data packet header. See the description for
EFI_MTFTP4_DATA_HEADER below in this table.
Ack Acknowledgement packet header. See the description
for EFI_MTFTP4_ACK_HEADER below in this table.
Data8
This ﬁeld should be ignored and treated as reserved.
Data packet header with big block number. See the
description for EFI_MTFTP4_DATA8_HEADER
below in this table.
Ack8
Acknowledgement header with big block number. See
the description for EFI_MTFTP4_ACK8_HEADER
Error Error packet header. See the description for
EFI_MTFTP4_ERROR_HEADER below in this table.
EFI_MTFTP4_REQ_HEADER OpCode For this packet type, OpCode =
EFI_MTFTP4_OPCODE_RRQ for a read request
or OpCode = EFI_MTFTP4_OPCODE_WRQ for a
write request.
Filename The ﬁle name to be downloaded or uploaded.
EFI_MTFTP4_OACK_HEADER OpCode For this packet type, OpCode =
EFI_MTFTP4_OPCODE_OACK.
Data The option strings in the option acknowledgement
packet.
EFI_MTFTP4_DATA_HEADER OpCode For this packet type, OpCode =
EFI_MTFTP4_OPCODE_DATA.
Block Block number of this data packet.
Data The content of this data packet.
EFI_MTFTP4_ACK_HEADER OpCode For this packet type, OpCode =
EFI_MTFTP4_OPCODE_ACK.
Block The block number of the data packet that is being ac-
knowledged.
30.3. EFI MTFTPv4 Protocol 1365Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_MTFTP4_DATA8_HEADER OpCode
For this packet type, OpCode =
EFI_MTFTP4_OPCODE_DATA8.
Block
The block number of data packet.
Data
The content of this data packet.
EFI_MTFTP4_ACK8_HEADER OpCode
EFI_MTFTP4_OPCODE_ACK8.
Block
The block number of the data packet that is being
acknowledged.
EFI_MTFTP4_ERROR_HEADER OpCode For this packet type, OpCode =
EFI_MTFTP4_OPCODE_ERROR.
ErrorCode The error number as deﬁned by the MTFTPv4 packet
error codes. Values for ErrorCode are deﬁned below.
ErrorMessage Error message string.
//
// MTFTP Packet OpCodes
//
#define EFI_MTFTP4_OPCODE_RRQ 1
#define EFI_MTFTP4_OPCODE_WRQ 2
#define EFI_MTFTP4_OPCODE_DATA 3
#define EFI_MTFTP4_OPCODE_ACK 4
#define EFI_MTFTP4_OPCODE_ERROR 5
#define EFI_MTFTP4_OPCODE_OACK 6
#define EFI_MTFTP4_OPCODE_DIR 7
//This field should be ignored andtreated asreserved.
#define EFI_MTFTP4_OPCODE_DATA8 8
#define EFI_MTFTP4_OPCODE_ACK8 9
Following is a description of the ﬁelds in the above deﬁnition.
30.3. EFI MTFTPv4 Protocol 1366Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_MTFTP4_OPCODE_RRQ The MTFTPv4 packet is a read request.
EFI_MTFTP4_OPCODE_WRQ The MTFTPv4 packet is a write request.
EFI_MTFTP4_OPCODE_DATA The MTFTPv4 packet is a data packet.
EFI_MTFTP4_OPCODE_ACK The MTFTPv4 packet is an acknowledgement packet.
EFI_MTFTP4_OPCODE_ERROR The MTFTPv4 packet is an error packet.
EFI_MTFTP4_OPCODE_OACK The MTFTPv4 packet is an option acknowledgement packet.
EFI_MTFTP4_OPCODE_DIR The MTFTPv4 packet is a directory query packet.
EFI_MTFTP4_OPCODE_DATA8
The MTFTPv4 packet is a data packet with a big block number.
EFI_MTFTP4_OPCODE_ACK8
The MTFTPv4 packet is an acknowledgement packet with a big block
number.
//
// MTFTP ERROR Packet ErrorCodes
//
#define EFI_MTFTP4_ERRORCODE_NOT_DEFINED 0
#define EFI_MTFTP4_ERRORCODE_FILE_NOT_FOUND 1
#define EFI_MTFTP4_ERRORCODE_ACCESS_VIOLATION 2
#define EFI_MTFTP4_ERRORCODE_DISK_FULL 3
#define EFI_MTFTP4_ERRORCODE_ILLEGAL_OPERATION 4
#define EFI_MTFTP4_ERRORCODE_UNKNOWN_TRANSFER_ID 5
#define EFI_MTFTP4_ERRORCODE_FILE_ALREADY_EXISTS 6
#define EFI_MTFTP4_ERRORCODE_NO_SUCH_USER 7
#define EFI_MTFTP4_ERRORCODE_REQUEST_DENIED 8

number.
//
//
EFI_MTFTP4_ERRORCODE_NOT_DEFINED The error code is not deﬁned. See the error
message in the packet (if any) for details.
EFI_MTFTP4_ERRORCODE_FILE_NOT_FOUND The ﬁle was not found.
EFI_MTFTP4_ERRORCODE_ACCESS_VIOLATION There was an access violation.
EFI_MTFTP4_ERRORCODE_DISK_FULL The disk was full or its allocation was ex-
ceeded.
EFI_MTFTP4_ERRORCODE_ILLEGAL_OPERATION The MTFTPv4 operation was illegal.
EFI_MTFTP4_ERRORCODE_UNKNOWN_TRANSFER_ID The transfer ID is unknown.
EFI_MTFTP4_ERRORCODE_FILE_ALREADY_EXISTS The ﬁle already exists.
EFI_MTFTP4_ERRORCODE_NO_SUCH_USER There is no such user.
EFI_MTFTP4_ERRORCODE_REQUEST_DENIED The request has been denied due to option
negotiation.
EFI_SUCCESS An MTFTPv4 OACK packet was received and is in the Packet .
30.3. EFI MTFTPv4 Protocol 1367Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.21 – continued from previous page
•Filename isNULL .
•OptionCount is not zero and OptionList isNULL .
• One or more options in OptionList have wrong format.
•PacketLength isNULL .
• One or more IPv4 addresses in OverrideData are not valid unicast IPv4
addresses if OverrideData is not NULL and the addresses are not set to all
zero.
• One or more options in the OptionList are in the unsupported list of
structure EFI_MTFTP4_MODE_DATA .
EFI_NOT_STARTED The EFI MTFTPv4 Protocol driver has not been started.
EFI_ACCESS_DENIED The previous operation has not completed yet.
EFI_TFTP_ERROR An MTFTPv4 ERROR packet was received and is in the Packet .
EFI_NETWORK_UNREACHABLE An ICMP network unreachable error packet was received and the Packet is
set to NULL .
EFI_HOST_UNREACHABLE An ICMP host unreachable error packet was received and the Packet is set
toNULL .
EFI_PROTOCOL_UNREACHABLE An ICMP protocol unreachable error packet was received and the Packet is
EFI_PORT_UNREACHABLE An ICMP port unreachable error packet was received and the Packet is set
toNULL .
EFI_ICMP_ERROR Some other ICMP ERROR packet was received and the Packet is set to
NULL .
EFI_PROTOCOL_ERROR An unexpected MTFTPv4 packet was received and is in the Packet .
EFI_TIMEOUT No responses were received from the MTFTPv4 server.
30.3.6 EFI_MTFTP4_PROTOCOL.ParseOptions()
Summary
Parses the options in an MTFTPv4 OACK packet.
Prototype
typedef
(EFIAPI *EFI_MTFTP4_PARSE_OPTIONS)(
IN EFI_MTFTP4_PACKET *Packet,
OUT UINT32 *OptionCount,
30.3. EFI MTFTPv4 Protocol 1368Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
OUT EFI_MTFT4P_OPTION **OptionList OPTIONAL
);
PacketLen Length of the OACK packet to be parsed.
Packet Pointer to the OACK packet to be parsed. Type EFI_MTFTP4_PACKET is deﬁned in
EFI_MTFTP4_PROTOCOL .GetInfo() .
OptionCount Pointer to the number of options in following OptionList .
OptionList Pointer to EFI_MTFTP4_OPTION storage. Call the EFI Boot Service FreePool() to release the Op-
tionList if the options in this OptionList are not needed any more. Type EFI_MTFTP4_OPTION is deﬁned in
TheParseOptions() function parses the option ﬁelds in an MTFTPv4 OACK packet and returns the number of options
that were found and optionally a list of pointers to the options in the packet.
If one or more of the option ﬁelds are not valid, then EFI_PROTOCOL_ERROR is returned and **OptionCount* and
**OptionList* stop at the last valid option.
EFI_SUCCESS The OACK packet was valid and the OptionCount andOptionList parame-
ters have been updated.
•PacketLen is 0.
•Packet isNULL orPacket is not a valid MTFTPv4 packet.
EFI_NOT_FOUND No options were found in the OACK packet.
EFI_OUT_OF_RESOURCES Storage for the OptionList array cannot be allocated.
EFI_PROTOCOL_ERROR One or more of the option ﬁelds is invalid.
30.3.7 EFI_MTFTP4_PROTOCOL.ReadFile()
Summary
Downloads a ﬁle from an MTFTPv4 server.
Prototype
typedef
(EFIAPI *EFI_MTFTP4_READ_FILE)(
IN EFI_MTFTP4_TOKEN *Token
);
30.3. EFI MTFTPv4 Protocol 1369Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_MTFTP4_TOKEN is deﬁned in “Related Deﬁnitions” below.
TheReadFile() function is used to initialize and start an MTFTPv4 download process and optionally wait for comple-
tion. When the download operation completes, whether successfully or not, the Token.Status ﬁeld is updated by the
EFI MTFTPv4 Protocol driver and then Token.Event is signaled (if it is not NULL ).
Data can be downloaded from the MTFTPv4 server into either of the following locations:
• A ﬁxed buffer that is pointed to by Token.Buffer
• A download service function that is pointed to by Token.CheckPacket
If both Token.Buffer andToken.CheckPacket are used, then Token.CheckPacket will be called ﬁrst. If the call is suc-
cessful, the packet will be stored in Token.Buffer .
// EFI_MTFTP4_TOKEN
EFI_MTFTP4_OVERRIDE_DATA *OverrideData;
UINT8 *Filename;
UINT8 *ModeStr;
EFI_MTFTP4_OPTION *OptionList;
UINT64 BufferSize;
EFI_MTFTP4_CHECK_PACKET CheckPacket;
EFI_MTFTP4_TIMEOUT_CALLBACK TimeoutCallback;
EFI_MTFTP4_PACKET_NEEDED PacketNeeded;
} EFI_MTFTP4_TOKEN;
Status The status that is returned to the caller at the end of the operation to indicate whether this operation completed
successfully. Deﬁned Status values are listed below.
Event The event that will be signaled when the operation completes. If set to NULL , the corresponding function will
wait until the read or write operation ﬁnishes. The type of Event must be EVT_NOTIFY_SIGNAL . The Task
Priority Level (TPL) of Event must be lower than or equal to TPL_CALLBACK .
OverrideData If not NULL , the data that will be used to override the existing conﬁgure data. Type
EFI_MTFTP4_OVERRIDE_DATA is deﬁned in EFI_MTFTP4_PROTOCOL .GetInfo() .
Filename Pointer to the null-terminated ASCII ﬁle name string.
ModeStr Pointer to the null-terminated ASCII mode string. If NULL , “octet” is used.
OptionCount Number of option/value string pairs.
OptionList Pointer to an array of option/value string pairs. Ignored if OptionCount is zero. Both a remote server
and this driver implementation should support these options. If one or more options are unrecognized by this
implementation, it is sent to the remote server without being changed. Type EFI_MTFTP4_OPTION is deﬁned
inEFI_MTFTP4_PROTOCOL .GetInfo() .
BufferSize On input, the size, in bytes, of Buffer . On output, the number of bytes transferred
30.3. EFI MTFTPv4 Protocol 1370Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Buffer Pointer to the data buffer. Data that is downloaded from the MTFTPv4 server is stored here. Data that is
uploaded to the MTFTPv4 server is read from here. Ignored if BufferSize is zero.
Context Pointer to the context that will be used by CheckPacket, TimeoutCallback andPacketNeeded.
CheckPacket Pointer to the callback function to check the contents of the received packet. Type
EFI_MTFTP4_CHECK_PACKET is deﬁned below.
TimeoutCallback Pointer to the function to be called when a timeout occurs. Type
EFI_MTFTP4_TIMEOUT_CALLBACK is deﬁned below.
PacketNeeded Pointer to the function to provide the needed packet contents. Only used in WriteFile() operation.
Type EFI_MTFTP4_PACKET_NEEDED is deﬁned below.
TheEFI_MTFTP4_TOKEN structure is used for both the MTFTPv4 reading and writing operations. The caller uses
this structure to pass parameters and indicate the operation context. After the reading or writing operation completes,
the EFI MTFTPv4 Protocol driver updates the Status parameter and the Event is signaled if it is not NULL . The
following table lists the status codes that are returned in the Status parameter.
EFI_SUCCESS The data ﬁle has been transferred successfully.
EFI_BUFFER_TOO_SMALL BufferSize is not large enough to hold the downloaded data in downloading
process.

process.
EFI_ABORTED Current operation is aborted by user.
EFI_NETWORK_UNREACHABLE An ICMP network unreachable error packet was received.
EFI_NETWORK_UNREACHABLE AnICMP host unreachable error packet was received.
EFI_NETWORK_UNREACHABLE An ICMP protocol unreachable error packet was received.
EFI_NETWORK_UNREACHABLE An ICMP port unreachable error packet was received .
EFI_ICMP_ERROR Some other ICMP ERROR packet was received.
EFI_TFTP_ERROR An MTFTPv4 ERROR packet was received.
// EFI_MTFTP4_CHECK_PACKET
typedef
(EFIAPI *EFI_MTFTP4_CHECK_PACKET)(
IN EFI_MTFTP4_TOKEN *Token,
IN UINT16 PacketLen,
IN EFI_MTFTP4_PACKET *Packet
);
Token The token that the caller provided in the EFI_MTFTP4_PROTOCOL .ReadFile(), WriteFile() orReadDirec-
tory() function. Type EFI_MTFTP4_TOKEN is deﬁned in EFI_MTFTP4_PROTOCOL.ReadFile() .
PacketLen Indicates the length of the packet.
Packet Pointer to an MTFTPv4 packet. Type EFI_MTFTP4_PACKET is deﬁned in EFI_MTFTP4_PROTOCOL .Get-
Info() .
30.3. EFI MTFTPv4 Protocol 1371Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_MTFTP4_CHECK_PACKET is a callback function that is provided by the caller to intercept the
EFI_MTFTP4_OPCODE_DATA orEFI_MTFTP4_OPCODE_DATA8 packets processed in the
EFI_MTFTP4_PROTOCOL .ReadFile() function, and alternatively to intercept
EFI_MTFTP4_OPCODE_OACK orEFI_MTFTP4_OPCODE_ERROR packets during a call to
EFI_MTFTP4_PROTOCOL.ReadFile() ,WriteFile() orReadDirectory() . Whenever an MTFTPv4 packet with the
type described above is received from a server, the EFI MTFTPv4 Protocol driver will call
EFI_MTFTP4_CHECK_PACKET function to let the caller have an opportunity to process this packet. Any status
code other than EFI_SUCCESS that is returned from this function will abort the transfer process.
// EFI_MTFTP4_TIMEOUT_CALLBACK
typedef
(EFIAPI *EFI_MTFTP4_TIMEOUT_CALLBACK)(
);
Token The token that is provided in the EFI_MTFTP4_PROTOCOL .ReadFile() or
EFI_MTFTP4_PROTOCOL.WriteFile() orEFI_MTFTP4_PROTOCOL.ReadDirectory() functions by the
caller. Type EFI_MTFTP4_TOKEN is deﬁned in EFI_MTFTP4_PROTOCOL.ReadFile() .
EFI_MTFTP4_TIMEOUT_CALLBACK is a callback function that the caller provides to capture the
timeout event in the EFI_MTFTP4_PROTOCOL .ReadFile() ,EFI_MTFTP4_PROTOCOL.WriteFile() or
EFI_MTFTP4_PROTOCOL.ReadDirectory() functions. Whenever a timeout occurs, the EFI MTFTPv4 Proto-
col driver will call the EFI_MTFTP4_TIMEOUT_CALLBACK function to notify the caller of the timeout event. Any
status code other than EFI_SUCCESS that is returned from this function will abort the current download process.
// EFI_MTFTP4_PACKET_NEEDED
typedef
(EFIAPI *EFI_MTFTP4_PACKET_NEEDED)(
IN OUT UINT16 *Length,
);
Token The token provided in the EFI_MTFTP4_PROTOCOL .WriteFile() by the caller.
Length Indicates the length of the raw data wanted on input, and the length the data available on output.
Buffer Pointer to the buffer where the data is stored.
EFI_MTFTP4_PACKET_NEEDED is a callback function that the caller provides to feed data to the
EFI_MTFTP4_PROTOCOL .WriteFile() function. EFI_MTFTP4_PACKET_NEEDED provides another mechanism
for the caller to provide data to upload other than a static buffer. The EFI MTFTP4 Protocol driver always calls
EFI_MTFTP4_PACKET_NEEDED to get packet data from the caller if no static buffer was given in the initial call to
EFI_MTFTP4_PROTOCOL.WriteFile() function. Setting **Length* to zero signals the end of the session. Returning
a status code other than EFI_SUCCESS aborts the session.
30.3. EFI MTFTPv4 Protocol 1372Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The data ﬁle is being downloaded.
•Token.Filename isNULL .
•Token.OptionCount is not zero and Token.OptionList isNULL .
• One or more options in Token.OptionList have wrong format.
•Token.Buffer andToken.CheckPacket are both NULL .
• One or more IPv4 addresses in Token.OverrideData are not valid unicast
IPv4 addresses if Token.OverrideData is not NULL and the addresses are
not set to all zero.
• One or more options in the Token.OptionList are in the unsupported list
of structure EFI_MTFTP4_MODE_DATA .
EFI_ALREADY_STARTED This Token is being used in another MTFTPv4 session.
30.3.8 EFI_MTFTP4_PROTOCOL.WriteFile()
Summary
Sends a data ﬁle to an MTFTPv4 server. May be unsupported in some EFI implementations.
Prototype
typedef
(EFIAPI *EFI_MTFTP4_WRITE_FILE)(
);
Token Pointer to the token structure to provide the parameters that are used in this function. Type
EFI_MTFTP4_TOKEN is deﬁned in EFI_MTFTP4_PROTOCOL .ReadFile() .
TheWriteFile() function is used to initialize an uploading operation with the given option list and optionally wait for
completion. If one or more of the options is not supported by the server, the unsupported options are ignored and a
30.3. EFI MTFTPv4 Protocol 1373Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
standard TFTP process starts instead. When the upload process completes, whether successfully or not, Token.Event
is signaled, and the EFI MTFTPv4 Protocol driver updates Token.Status .
The caller can supply the data to be uploaded in the following two modes:
• Through the user-provided buffer
• Through a callback function
With the user-provided buffer, the Token.BufferSize ﬁeld indicates the length of the buffer, and the driver will upload
the data in the buffer. With an EFI_MTFTP4_PACKET_NEEDED callback function, the driver will call this callback
function to get more data from the user to upload. See the deﬁnition of EFI_MTFTP4_PACKET_NEEDED for more
information. These two modes cannot be used at the same time. The callback function will be ignored if the user
provides the buffer.
EFI_SUCCESS The upload session has started.
•Token.Buffer andToken.PacketNeeded are both NULL .
EFI_ALREADY_STARTED This Token is already being used in another MTFTPv4 session.
30.3. EFI MTFTPv4 Protocol 1374Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
30.3.9 EFI_MTFTP4_PROTOCOL.ReadDirectory()
Summary
Downloads a data ﬁle “directory” from an MTFTPv4 server. May be unsupported in some EFI implementations.
Prototype
typedef
(EFIAPI *EFI_MTFTP4_READ_DIRECTORY)(
);

Summary
Prototype
typedef
);
TheReadDirectory() function is used to return a list of ﬁles on the MTFTPv4 server that are logically (or operationally)
related to Token.Filename . The directory request packet that is sent to the server is built with the option list that was
provided by caller, if present.
The ﬁle information that the server returns is put into either of the following locations:
The returned directory listing in the Token.Buffer orEFI_MTFTP4_PACKET consists of a list of two or three variable-
length ASCII strings, each terminated by a null character, for each ﬁle in the directory. If the multicast option is
involved, the ﬁrst ﬁeld of each directory entry is the static multicast IP address and UDP port number that is associated
with the ﬁle name. The format of the ﬁeld is ip:ip:ip:ip:port . If the multicast option is not involved, this ﬁeld and its
terminating null character are not present.
The next ﬁeld of each directory entry is the ﬁle name and the last ﬁeld is the ﬁle information string. The information
string contains the ﬁle size and the create/modify timestamp. The format of the information string is ﬁlesize yyyy-
mm-dd hh:mm:ss:ffff . The timestamp is Coordinated Universal Time (UTC; also known as Greenwich Mean Time
[GMT]).
EFI_SUCCESS The MTFTPv4 related ﬁle “directory” has been downloaded.
EFI_UNSUPPORTED The EFI MTFTPv4 Protocol driver does not support this function.
30.3. EFI MTFTPv4 Protocol 1375Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.26 – continued from previous page
One or more of these conditions is TRUE :
Token.Buffer andToken.CheckPacket are both **NULL*.
EFI_UNSUPPORTED One or more options in the Token.OptionList are in the unsupported list of
30.3.10 EFI_MTFTP4_PROTOCOL.POLL()
Summary
Prototype
typedef
(EFIAPI *EFI_MTFTP4_POLL) (
IN EFI_MTFTP4_PROTOCOL *This
);
30.3. EFI MTFTPv4 Protocol 1376Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.27 – continued from previous page
EFI_NOT_STARTED This EFI MTFTPv4 Protocol instance has not been started.
30.4 EFI MTFTPv6 Protocol
This section deﬁnes the EFI MTFTPv6 Protocol interface that is built upon the EFI UDPv6 Protocol.
30.4.1 MTFTP6 Service Binding Protocol
30.4.1.1 EFI_MTFTP6_SERVICE_BINDING_PROTOCOL
Summary
The EFI MTFTPv6 Service Binding Protocol is used to locate communication devices that are supported by an EFI
MTFTPv6 Protocol driver and to create and destroy instances of the EFI MTFTPv6 Protocol child instance that can
GUID
#define EFI_MTFTP6_SERVICE_BINDING_PROTOCOL_GUID \
{0xd9760ff3,0x3cca,0x4267,\
{0x80,0xf9,0x75,0x27,0xfa,0xfa,0x42,0x23}}
A network application or driver that requires MTFTPv6 I/O services can use one of the protocol handler services, such
asBS->LocateHandleBuffer() , to search for devices that publish an EFI MTFTPv6 Service Binding Protocol GUID.
Each device with a published EFI MTFTPv6 Service Binding Protocol GUID supports the EFI MTFTPv6 Protocol
After a successful call to the EFI_MTFTP6_SERVICE_BINDING_PROTOCOL.CreateChild() function, the newly
created child EFI MTFTPv6 Protocol driver instance is in the un-conﬁgured state; it is not ready to transfer data.
EFI_MTFTP6_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_MTFTP6_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
Each instance of the EFI MTFTPv6 Protocol driver can support one ﬁle transfer operation at a time. To download two
ﬁles at the same time, two instances of the EFI MTFTPv6 Protocol driver need to be created.
30.4. EFI MTFTPv6 Protocol 1377Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
30.4.2 MTFTP6 Protocol
30.4.2.1 EFI_MTFTP6_PROTOCOL
Summary
The EFI MTFTPv6 Protocol provides basic services for client-side unicast and/or multicast TFTP operations.
GUID
#define EFI_MTFTP6_PROTOCOL_GUID \
{0xbf0a78ba,0xec29,0x49cf,\
0xa1,0xc9,0x7a,0xe5,0x4e,0xab,0x6a,0x51}}
typedef struct _EFI_MTFTP6_PROTOCOL {
EFI_MTFTP6_GET_MODE_DATA GetModeData;
EFI_MTFTP6_CONFIGURE Configure;
EFI_MTFTP6_GET_INFO GetInfo;
EFI_MTFTP6_PARSE_OPTIONS ;
EFI_MTFTP6_READ_FILE ReadFile;
EFI_MTFTP6_WRITE_FILE WriteFile;
EFI_MTFTP6_READ_DIRECTORY ReadDirectory;
EFI_MTFTP6_POLL Poll;
} EFI_MTFTP6_PROTOCOL;
Conﬁgure Initializes, changes, or resets the operational settings for this instance of the EFI MTFTPv6 Protocol driver.
GetInfo Retrieves information about a ﬁle from an MTFTPv6 server. See the GetInfo() function description. Parses
the options in an MTFTPv6 OACK (options acknowledgement) packet. See the ()function description.
ReadFile Downloads a ﬁle from an MTFTPv6 server. See the ReadFile() function description.
WriteFile Uploads a ﬁle to an MTFTPv6 server. This function may be unsupported in some EFI implementations.
ReadDirectory Downloads a related ﬁle directory from an MTFTPv6 server. This function may be unsupported in
TheEFI_MTFTP6_PROTOCOL is designed to be used by UEFI drivers and applications to transmit and receive data
ﬁles. The EFI MTFTPv6 Protocol driver uses the underlying EFI UDPv6 Protocol driver and EFI IPv6 Protocol driver.
30.4. EFI MTFTPv6 Protocol 1378Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
30.4.2.2 EFI_MTFTP6_PROTOCOL.GetModeData()
Summary
Prototype
typedef
(EFIAPI *EFI_MTFTP6_GET_MODE_DATA)(
IN EFI_MTFTP6_PROTOCOL *This,
OUT EFI_MTFTP6_MODE_DATA *ModeData
);
This Pointer to the EFI_MTFTP6_PROTOCOL instance.
ModeData The buffer in which the EFI MTFTPv6 Protocol driver mode data is returned. Type
EFI_MTFTP6_MODE_DATA is deﬁned in “Related Deﬁnitions” below.
TheGetModeData () function reads the current operational settings of this EFI MTFTPv6 Protocol driver instance.
// EFI_MTFTP6_MODE_DATA
EFI_MTFTP6_CONFIG_DATA ConfigData;

Summary
Prototype
typedef
);
} EFI_MTFTP6_MODE_DATA;
ConﬁgData The conﬁguration data of this instance. Type EFI_MTFTP6_CONFIG_DATA is deﬁned below.
SupportedOptions An array of null-terminated ASCII option strings that are recognized and supported by this EFI
MTFTPv6 Protocol driver implementation. The buffer is read only to the caller and the caller should NOT free
the buffer.
TheEFI_MTFTP6_MODE_DATA structure describes the operational state of this instance.
// EFI_MTFTP6_CONFIG_DATA
EFI_IPv6_ADDRESS ServerIp;
} EFI_MTFTP6_CONFIG_DATA;
30.4. EFI MTFTPv6 Protocol 1379Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ServerIp The IP address of the MTFTPv6 server.
InitialServerPort The initial MTFTPv6 server port number. Request packets are sent to this port. This number is
TryCount The number of times to transmit MTFTPv6 request packets and wait for a response.
TimeoutValue The number of seconds to wait for a response after sending the MTFTPv6 request packet.
TheEFI_MTFTP6_CONFIG_DATA structure is used to retrieve and change MTFTPv6 session parameters.
30.4.2.3 EFI_MTFTP6_PROTOCOL.Conﬁgure()
Summary
Initializes, changes, or resets the default operational setting for this EFI MTFTPv6 Protocol driver instance.
Prototype
typedef
(EFIAPI *EFI_MTFTP6_CONFIGURE)(
IN EFI_MTFTP6_CONFIG_DATA *MtftpConfigData OPTIONAL
);
MtftpConﬁgData Pointer to the conﬁguration data structure. Type EFI_MTFTP6_CONFIG_DATA is deﬁned in
EFI_MTFTP6_PROTOCOL.GetModeData().
The Conﬁgure () function is used to set and change the conﬁguration data for this EFI MTFTPv6 Protocol driver
instance. The conﬁguration data can be reset to startup defaults by calling Conﬁgure () with MtftpConﬁgData set to
NULL. Whenever the instance is reset, any pending operation is aborted. By changing the EFI MTFTPv6 Protocol
driver instance conﬁguration data, the client can connect to different MTFTPv6 servers. The conﬁguration parameters
inMtftpConﬁgData are used as the default parameters in later MTFTPv6 operations and can be overridden in later
EFI_SUCCESS The EFI MTFTPv6 Protocol instance was conﬁgured successfully.
30.4. EFI MTFTPv6 Protocol 1380Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.29 – continued from previous page
•MtftpConﬁgData.StationIp is neither zero nor one of the conﬁgured IP
•MtftpCoﬁgData.ServerIp is not a valid IPv6 unicast address.
• The conﬁguration could not be changed at this time because there is some
MTFTP background operation in progress.
•MtftpCoﬁgData.LocalPort is already in use.
EFI_OUT_OF_RESOURCES The EFI MTFTPv6 Protocol driver instance data could not be allocated.
EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI MTFTPv6 Pro-
30.4.2.4 EFI_MTFTP6_PROTOCOL.GetInfo()
Summary
Get information about a ﬁle from an MTFTPv6 server.
Prototype
typedef
(EFIAPI *EFI_MTFTP6_GET_INFO)(
IN EFI_MTFTP6_OVERRIDE_DATA *OverrideData OPTIONAL,
IN EFI_MTFTP6_OPTION *OptionList OPTIONAL,
OUT EFI_MTFTP6_PACKET **Packet OPTIONAL
);
in the EFI_MTFTP6_PROTOCOL .Conﬁgure () function are used. Type EFI_MTFTP6_OVERRIDE_DATA is
Filename Pointer to an null-terminated ASCII ﬁle name string.
ModeStr Pointer to an null-terminated ASCII mode string. If NULL , octet will be used.
EFI_MTFTP6_OPTION is deﬁned in “Related Deﬁnitions” below.
30.4. EFI MTFTPv6 Protocol 1381Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Packet The pointer to the received packet. This buffer must be freed by the caller. Type EFI_MTFTP6_PACKET is
TheGetInfo() function assembles an MTFTPv6 request packet with options, sends it to the MTFTPv6 server, and may
return an MTFTPv6 OACK, MTFTPv6 ERROR, or ICMP ERROR packet. Retries occur only if no response packets
are received from the MTFTPv6 server before the timeout expires.
} EFI_MTFTP6_OVERRIDE_DATA;
ServerIp IP address of the MTFTPv6 server. If set to all zero, the value that was set by the
EFI_MTFTP6_PROTOCOL.Conﬁgure() function will be used.
ServerPort MTFTPv6 server port number. If set to zero, it will use the value that was set by the
EFI_MTFTP6_PROTOCOL.Conﬁgure() function.
TryCount Number of times to transmit MTFTPv6 request packets and wait for a response. If set to zero, the value
that was set by the EFI_MTFTP6_PROTOCOL.Conﬁgure() function will be used.
TimeoutValue Number of seconds to wait for a response after sending the MTFTPv6 request packet. If set to zero,
the value that was set by the EFI_MTFTP6_PROTOCOL.Conﬁgure() function will be used.
The EFI_MTFTP6_OVERRIDE_DATA structure is used to override the existing parameters that were set by the
// EFI_MTFTP6_OPTION
} EFI_MTFTP6_OPTION;
OptionStr Pointer to the null-terminated ASCII MTFTPv6 option string.
ValueStr Pointer to the null-terminated ASCII MTFTPv6 value string.
//********************************************
// EFI_MTFTP6_PACKET
EFI_MTFTP6_REQ_HEADER Rrq;
EFI_MTFTP6_REQ_HEADER Wrq;
EFI_MTFTP6_OACK_HEADER Oack;
EFI_MTFTP6_DATA_HEADER Data;
EFI_MTFTP6_ACK_HEADER Ack;
30.4. EFI MTFTPv6 Protocol 1382Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// This field should be ignored andtreated asreserved.
EFI_MTFTP6_DATA8_HEADER Data8;
EFI_MTFTP6_ACK8_HEADER Ack8;
EFI_MTFTP6_ERROR_HEADER Error;
} EFI_MTFTP6_PACKET;
// EFI_MTFTP6_REQ_HEADER
} EFI_MTFTP6_REQ_HEADER;
// EFI_MTFTP6_OACK_HEADER
} EFI_MTFTP6_OACK_HEADER;
// EFI_MTFTP6_DATA_HEADER
} EFI_MTFTP6_DATA_HEADER;
// EFI_MTFTP6_ACK_HEADER
} EFI_MTFTP6_ACK_HEADER;
// EFI_MTFTP6_DATA8_HEADER
} EFI_MTFTP6_DATA8_HEADER;
// EFI_MTFTP6_ACK8_HEADER

30.4. EFI MTFTPv6 Protocol 1383Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_MTFTP6_ACK8_HEADER;
// EFI_MTFTP6_ERROR_HEADER
} EFI_MTFTP6_ERROR_HEADER;
Table 1 below describes the parameters that are listed in the MTFTPv6 packet structure deﬁnitions above. All the
above structures are byte packed. The pragmas may vary from compiler to compiler. The MTFTPv6 packet structures
are also used by the following functions:
•EFI_MTFTP6_PROTOCOL.ReadFile()
•EFI_MTFTP6_PROTOCOL.WriteFile()
•EFI_MTFTP6_PROTOCOL.ReadDirectory()
• The EFI MTFTPv6 Protocol packet check callback functions
NOTE :BYTE ORDER :Both incoming and outgoing MTFTPv6 packets are in network byte order. All other param-
eters deﬁned in functions or data structures are stored in host byte order .
Table 30.30: Descriptions of Parameters in MTFTPv6 PacketStructures
EFI_MTFTP6_PACKET OpCode Type of packets as deﬁned by the MTFTPv6 packet op-
Rrq, Wrq Read request or write request packet header. See the
description for EFI_MTFTP6_REQ_HEADER below in
this table.
forEFI_MTFTP6_OACK_HEADER below in this table.
EFI_MTFTP6_DATA_HEADER below in this table.
forEFI_MTFTP6_ACK_HEADER below in this table.
Data8 This ﬁeld should be ignored and treated as reserved.
Data packet header with big block number. See the de-
scription for EFI_MTFTP6_DATA8_HEADER below in
Ack8 This ﬁeld should be ignored and treated as reserved. Ac-
knowledgement header with big block number. See the
description for EFI_MTFTP6_ACK8_HEADER below
in this table.
EFI_MTFTP6_ERROR_HEADER below in this table.
30.4. EFI MTFTPv6 Protocol 1384Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.30 – continued from previous page
EFI_MTFTP6_REQ_HEADER OpCode For this packet type, OpCode =
EFI_MTFTP6_OPCODE_RRQ for a read request
orOpCode = EFI_MTFTP6_OPCODE_WRQ for a
EFI_MTFTP6_OACK_HEADER OpCode For this packet type OpCode =
EFI_MTFTP6_OPCODE_OACK .
packet.
EFI_MTFTP6_DATA_HEADER OpCode For this packet type OpCode =
EFI_MTFTP6_OPCODE_DATA .
EFI_MTFTP6_ACK_HEADER OpCode For this packet type OpCode =
EFI_MTFTP6_OPCODE_ACK .
EFI_MTFTP6_DATA8_HEADER OpCode This ﬁeld should be ignored and treated as
reserved. For this packet type, OpCode =
EFI_MTFTP6_OPCODE_DATA8 .
Block
Data
EFI_MTFTP6_ACK8_HEADER OpCode For this packet type OpCode =
EFI_MTFTP6_OPCODE_ACK8 .
Block The block number of the data packet that is being
EFI_MTFTP6_ERROR_HEADER OpCode For this packet type OpCode =
EFI_MTFTP6_OPCODE_ERROR .
ErrorCode The error number as deﬁned by the MTFTPv6 packet
//
//
#define EFI_MTFTP6_OPCODE_RRQ 1
#define EFI_MTFTP6_OPCODE_WRQ 2
#define EFI_MTFTP6_OPCODE_DATA 3
#define EFI_MTFTP6_OPCODE_ACK 6
#define EFI_MTFTP6_OPCODE_ERROR 5
#define EFI_MTFTP6_OPCODE_OACK 6
#define EFI_MTFTP6_OPCODE_DIR 7
30.4. EFI MTFTPv6 Protocol 1385Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.31: MTFTP Packet OpCode Descriptions
MTFTP Packet OpCode Description
EFI_MTFTP6_OPCODE_RRQ The MTFTPv6 packet is a read request.
EFI_MTFTP6_OPCODE_WRQ The MTFTPv6 packet is a write request.
EFI_MTFTP6_OPCODE_DATA The MTFTPv6 packet is a data packet.
EFI_MTFTP6_OPCODE_ACK The MTFTPv6 packet is an acknowledgement packet.
EFI_MTFTP6_OPCODE_ERROR The MTFTPv6 packet is an error packet.
EFI_MTFTP6_OPCODE_OACK The MTFTPv6 packet is an option acknowledgement packet.
EFI_MTFTP6_OPCODE_DIR The MTFTPv6 packet is a directory query packet.
EFI_MTFTP6_OPCODE_DATA8
The MTFTPv6 packet is a data packet with a big block number.
EFI_MTFTP6_OPCODE_ACK8
The MTFTPv6 packet is an acknowledgement packet with a big block
number.
//
//
#define EFI_MTFTP6_ERRORCODE_NOT_DEFINED 0
#define EFI_MTFTP6_ERRORCODE_FILE_NOT_FOUND 1
#define EFI_MTFTP6_ERRORCODE_ACCESS_VIOLATION 2
#define EFI_MTFTP6_ERRORCODE_DISK_FULL 3
#define EFI_MTFTP6_ERRORCODE_ILLEGAL_OPERATION 4
#define EFI_MTFTP6_ERRORCODE_UNKNOWN_TRANSFER_ID 5
#define EFI_MTFTP6_ERRORCODE_FILE_ALREADY_EXISTS 6
#define EFI_MTFTP6_ERRORCODE_NO_SUCH_USER 7
#define EFI_MTFTP6_ERRORCODE_REQUEST_DENIED 8
Table 30.32: MTFTP ERROR Packet ErrorCode Descriptions
MTFTP ERROR Packet ErrorCodes Description
E FI_MTFTP6_ERRORCODE_NOT_DEFINED The error code is not deﬁned. See the error message in
the packet (if any) for details.
EFI_ MTFTP6_ERRORCODE_FILE_NOT_FOUND The ﬁle was not found.
EFI_MT FTP6_ERRORCODE_ACCESS_VIOLATION There was an access violation.
EFI_MTFTP6_ERRORCODE_DISK_FULL The disk was full or its allocation was exceeded.
EFI_MTF TP6_ERRORCODE_ILLEGAL_OPERATION The MTFTPv6 operation was illegal.
EFI_MTFTP 6_ERROR-
CODE_UNKNOWN_TRANSFER_IDThe transfer ID is unknown.
CODE_FILE_ALREADY_EXISTSThe ﬁle already exists.
EF I_MTFTP6_ERRORCODE_NO_SUCH_USER There is no such user.
EFI_ MTFTP6_ERRORCODE_REQUEST_DENIED The request has been denied due to option negotiation.
EFI_SUCCESS An MTFTPv6 OACK packet was received and is in the Packet .
30.4. EFI MTFTPv6 Protocol 1386Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 30.33 – continued from previous page
•OverrideData.ServerIp is not a valid unicast IPv6 address and not set to
all zero.
EFI_UNSUPPORTED One or more options in the OptionList are unsupported by this implementa-
tion.
EFI_NOT_STARTED The EFI MTFTPv6 Protocol driver has not been started.
EFI_TFTP_ERROR An MTFTPv6 ERROR packet was received and is in the Packet .
EFI_NETWORK_UNREACHABLE An ICMP host unreachable error packet was received and the Packet is set
toNULL .
EFI_NETWORK_UNREACHABLE An ICMP protocol unreachable error packet was received and the Packet is
EFI_NETWORK_UNREACHABLE An ICMP port unreachable error packet was received and the Packet is set
toNULL .
NULL .
EFI_PROTOCOL_ERROR An unexpected MTFTPv6 packet was received and is in the Packet .
EFI_TIMEOUT No responses were received from the MTFTPv6 server.
30.4.2.5 EFI_MTFTP6_PROTOCOL.ParseOptions()
Summary
Parse the options in an MTFTPv6 OACK packet.
Prototype
typedef
(EFIAPI *EFI_MTFTP6_PARSE_OPTIONS)(
IN EFI_MTFTP6_PACKET *Packet,
OUT EFI_MTFTP6_OPTION **OptionList OPTIONAL
);
30.4. EFI MTFTPv6 Protocol 1387Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Packet Pointer to the OACK packet to be parsed. Type EFI_MTFTP6_PACKET is deﬁned in
EFI_MTFTP6_PROTOCOl.GetInfo() .
OptionCount Pointer to the number of options in the following OptionList .

NULL .
Summary
Prototype
typedef
);
OptionList Pointer to EFI_MTFTP6_OPTION storage. Each pointer in the OptionList points to the correspond-
ing MTFTP option buffer in the Packet . Call the EFI Boot Service FreePool() to release the OptionList
if the options in this OptionList are not needed any more. Type EFI_MTFTP6_OPTION is deﬁned in
EFI_MTFTP6_PROTOCOL.GetInfo() .
TheParseOptions( ) function parses the option ﬁelds in an MTFTPv6 OACK packet and returns the number of options
If one or more of the option ﬁelds are not valid, then EFI_PROTOCOL_ERROR is returned and * OptionCount and *
OptionList stop at the last valid option.
•Packet isNULL orPacket is not a valid MTFTPv6 packet.
EFI_OUT_OF_RESOURCES Storage for the OptionList array can not be allocated.
30.4.2.6 EFI_MTFTP6_PROTOCOL.ReadFile()
Summary
Download a ﬁle from an MTFTPv6 server.
Prototype
typedef
(EFIAPI *EFI_MTFTP6_READ_FILE)(
IN EFI_MTFTP6_TOKEN *Token
);
EFI_MTFTP6_TOKEN is deﬁned in “Related Deﬁnitions” below.
30.4. EFI MTFTPv6 Protocol 1388Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheReadFile() function is used to initialize and start an MTFTPv6 download process and optionally wait for comple-
EFI MTFTPv6 Protocol driver and then Token.Event is signaled if it is not NULL .
Data can be downloaded from the MTFTPv6 server into either of the following locations:
// EFI_MTFTP6_TOKEN
EFI_MTFTP6_OVERRIDE_DATA OverrideData;
EFI_MTFTP6_OPTION OptionList;
EFI_MTFTP6_CHECK_PACKET CheckPacket;
EFI_MTFTP6_TIMEOUT_CALLBACK TimeoutCallback;
EFI_MTFTP6_PACKET_NEEDED PacketNeeded;
} EFI_MTFTP6_TOKEN;
wait until the read or write operation ﬁnishes. The type of Event must be EVT_NOTIFY_SIGNAL .
EFI_MTFTP6_OVERRIDE_DATA is deﬁned in EFI_MTFTP6_PROTOCOL .GetInfo().
ModeStr Pointer to the null-terminated ASCII mode string. If NULL , octet is used.
implementation, it is sent to the remote server without being changed. Type EFI_MTFTP6_OPTION is deﬁned
inEFI_MTFTP6_PROTOCOL .GetInfo().
BufferSize On input, the size, in bytes, of Buffer . On output, the number of bytes transferred.
Buffer Pointer to the data buffer. Data that is downloaded from the MTFTPv6 server is stored here. Data that is
uploaded to the MTFTPv6 server is read from here. Ignored if BufferSize is zero.
Context Pointer to the context that will be used by CheckPacket ,TimeoutCallback andPacketNeeded .
EFI_MTFTP6_CHECK_PACKET is deﬁned below.
30.4. EFI MTFTPv6 Protocol 1389Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_MTFTP6_TIMEOUT_CALLBACK is deﬁned below.
Type EFI_MTFTP6_PACKET_NEEDED is deﬁned below.
The EFI_MTFTP6_TOKEN structure is used for both the MTFTPv6 reading and writing operations.
The caller uses this structure to pass parameters and indicate the operation context. After the reading or writing
operation completes, the EFI MTFTPv6 Protocol driver updates the Status parameter and the Event is signaled if it is
not NULL. The following table lists the status codes that are returned in the Status parameter.
Status Codes Returned in the Status Parameter
EFI_BUFFER_TOO_SMALL BufferSize is not zero but not large enough to hold the downloaded data in
downloading process.
EFI_NETWORK_UNREACHABLE An ICMP host unreachable error packet was received.
EFI_NETWORK_UNREACHABLE An ICMP port unreachable error packet was received.
EFI_TFTP_ERROR An MTFTPv6 ERROR packet was received.
// EFI_MTFTP6_CHECK_PACKET
typedef
(EFIAPI *EFI_MTFTP6_CHECK_PACKET)(
IN EFI_MTFTP6_TOKEN *Token,
IN EFI_MTFTP6_PACKET *Packet
);
Token The token that the caller provided in the EFI_MTFTP6_PROTOCOl.ReadFile() ,WriteFile() orReadDirec-
tory() function. Type EFI_MTFTP6_TOKEN is deﬁned in EFI_MTFTP6_PROTOCOL.ReadFile() .
Packet
Pointer to an MTFTPv6 packet. Type EFI_MTFTP6_PACKET is deﬁned in
EFI_MTFTP6_CHECK_PACKET is a callback function that is provided by the caller to intercept the
EFI_MTFTP6_OPCODE_DATA or
EFI_MTFTP6_OPCODE_DATA8 packets processed in the
EFI_MTFTP6_PROTOCOL.ReadFile() function, and alternatively to intercept
EFI_MTFTP6_OPCODE_OACK orEFI_MTFTP6_OPCODE_ERROR packets during a call to
30.4. EFI MTFTPv6 Protocol 1390Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_MTFTP6_PROTOCOL.ReadFile() ,WriteFile() orReadDirectory() . Whenever an MTFTPv6 packet with
the type described above is received from a server, the EFI MTFTPv6 Protocol driver will call
EFI_MTFTP6_CHECK_PACKET function to let the caller have an opportunity to process this packet. Any
status code other than EFI_SUCCESS that is returned from this function will abort the transfer process.
// EFI_MTFTP6_TIMEOUT_CALLBACK
typedef
(EFIAPI *EFI_MTFTP6_TIMEOUT_CALLBACK)(
);
Token
The token that is provided in the
EFI_MTFTP6_PROTOCOL.ReadFile() or
EFI_MTFTP6_PROTOCOL.ReadDirectory() functions by the caller. Type
EFI_MTFTP6_TOKEN is deﬁned in
EFI_MTFTP6_PROTOCOL.ReadFile() .
EFI_MTFTP6_TIMEOUT_CALLBACK is a callback function that the caller provides to capture the
timeout event in the EFI_MTFTP6_PROTOCOL.ReadFile() ,EFI_MTFTP6_PROTOCOL.WriteFile() or
EFI_MTFTP6_PROTOCOL.ReadDirectory() functions. Whenever a timeout occurs, the EFI MTFTPv6 Proto-
col driver will call the EFI_MTFTP6_TIMEOUT_CALLBACK function to notify the caller of the timeout event. Any
// EFI_MTFTP6_PACKET_NEEDED
typedef
(EFIAPI *EFI_MTFTP6_PACKET_NEEDED)(
IN EFI_MTFTP6_TOKEN Token,

Token
typedef
);
Token The token provided in the EFI_MTFTP6_PROTOCOL.WriteFile() by the caller.
EFI_MTFTP6_PACKET_NEEDED is a callback function that the caller provides to feed data to the
EFI_MTFTP6_PROTOCOL.WriteFile() function. EFI_MTFTP6_PACKET_NEEDED provides another mechanism
for the caller to provide data to upload other than a static buffer. The EFI MTFTP6 Protocol driver always calls
EFI_MTFTP6_PACKET_NEEDED to get packet data from the caller if no static buffer was given in the initial call to
EFI_MTFTP6_PROTOCOL.WriteFile() function. Setting **Length* to zero signals the end of the session. Returning
30.4. EFI MTFTPv6 Protocol 1391Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
•Token.OverrideData.ServerIp is not a valid unicast IPv6 address and not
set to all zero.
EFI_UNSUPPORTED One or more options in the Token.OptionList are not supported by this im-
EFI_ALREADY_STARTED This Token is being used in another MTFTPv6 session.
30.4.2.7 EFI_MTFTP6_PROTOCOL.WriteFile()
Summary
Send a ﬁle to an MTFTPv6 server. May be unsupported in some implementations.
Prototype
typedef
(EFIAPI *EFI_MTFTP6_WRITE_FILE)(
);
EFI_MTFTP6_TOKEN is deﬁned in EFI_MTFTP6_PROTOCOL.ReadFile() .
is signaled, and the EFI MTFTPv6 Protocol driver updates Token.Status .
30.4. EFI MTFTPv6 Protocol 1392Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
the data in the buffer. With an EFI_MTFTP6_PACKET_NEEDED callback function, the driver will call this callback
function to get more data from the user to upload. See the deﬁnition of EFI_MTFTP6_PACKET_NEEDED for more
EFI_ALREADY_STARTED This Token is already being used in another MTFTPv6 session.
30.4.2.8 EFI_MTFTP6_PROTOCOL.ReadDirectory()
Summary
Download a data ﬁle directory from an MTFTPv6 server. May be unsupported in some implementations.
Prototype
typedef
(EFIAPI *EFI_MTFTP6_READ_DIRECTORY)(
);
30.4. EFI MTFTPv6 Protocol 1393Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheReadDirectory() function is used to return a list of ﬁles on the MTFTPv6 server that are logically (or operationally)
cessful, the packet will be stored in Token.Buffer.
The returned directory listing in the Token.Buffer orEFI_MTFTP6_PACKET consists of a list of two or three variable-
[GMT]).
EFI_SUCCESS The MTFTPv6 related ﬁle “directory” has been downloaded.
EFI_UNSUPPORTED The EFI MTFTPv6 Protocol driver does not support this function.
30.4. EFI MTFTPv6 Protocol 1394Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
30.4.2.9 EFI_MTFTP6_PROTOCOL.Poll()
Summary
Prototype
typedef
(EFIAPI *EFI_MTFTP6_POLL) (
IN EFI_MTFTP6_PROTOCOL *This
);

Summary
Prototype
typedef
);
EFI_NOT_STARTED This EFI MTFTPv6 Protocol instance has not been started.
30.4. EFI MTFTPv6 Protocol 1395CHAPTER
THIRTYONE
EFI REDFISH SERVICE SUPPORT
31.1 EFI Redﬁsh Discover Protocol
31.1.1 Overview
The purpose of the EFI Redﬁsh Discover is to provide a mechanism for EFI Redﬁsh clients to acquire the DMTF
Redﬁsh® services provided on the platform or network. See the Redﬁsh Developer Hub at https://redﬁsh.dmtf.org/
for ofﬁcial Redﬁsh schema and speciﬁcations. Redﬁsh services can be discovered according to Redﬁsh Host Interface
(SMBIOS type 42) reported on platform, or optionally using Simple Service Discovery Protocol (SSDP) message
over UDP port 1900 to search Redﬁsh services which were joined well-known multicast group addresses. EFI Redﬁsh
Discover driver discovers Redﬁsh services and creates EFI REST EX protocol instance for each Redﬁsh service it
found. It also conﬁgures EFI REST EX protocol instance according to the Redﬁsh service information described in
Redﬁsh Host Interface or the response of UPnP M-SEARCH request (deﬁned in UPnP Device Architecture, which
can be obtained at “Links to UEFI-Related Documents” http://ueﬁ.org/ueﬁ).
EFI Redﬁsh Discover Protocol behaves as a middle protocol which abstracts the creation and conﬁguration of EFI
REST EX instance from EFI Redﬁsh clients.
• EFI Redﬁsh Discover Protocol uses EFI UDP protocol to send SSDP message to verify or discover Redﬁsh
services. For the Redﬁsh service reported by SMBIOS type 42h, EFI Redﬁsh Discover Protocol can optionally
unicast M-SEARCH request to Redﬁsh service in order to verify the existence of service.
• EFI Redﬁsh Discover Protocol can optionally provide the functionality of discovering Redﬁsh services through
each network interface installed on platform. Prior to acquiring the list of ready-to-use EFI REST EX protocol
instances, the consumer of this protocol can get the network interface list and decide which interface is used for
the multicast transmission. EFI Redﬁsh Discover Protocol multicasts M-SEARCH request to multicast group
addresses then collects M-SEARCH responses from Redﬁsh services in asynchronous or synchronous manner.
• EFI Redﬁsh Discover Protocol provides the information of each network interface installed on platform through
GetNetworkInterfaceList()function. The information such as MAC address, subnet ID, subset mask and VLAN
ID of network interface could be utilized by upper-layer EFI application or driver to identify network interface
used for Redﬁsh service discovery. EFI Redﬁsh Discover Protocol abstracts EFI network stack to user which
means this protocol should not require user to conﬁgure UDP before utilizing services. Network conﬁguration
of network interface such as station IP address, subnet ID, subnet mask and other operational parameters should
be conﬁgured through system ﬁrmware speciﬁc implementation (for example system utility). This protocol
should simply use UDP default station properties.
Multicast across internetworks is handled by multicast router and is not in the scope of EFI Redﬁsh Discover Protocol.
The implementation of upper-layer user interface is system ﬁrmware design-speciﬁc.
• EFI Redﬁsh Discovery Protocol is the helper driver to discover Redﬁsh services on platform or network. The
upper level EFI Redﬁsh client could provide its own implementation of how to utilize information returned
from this protocol. Such as network interface selection UI, create Redﬁsh host interface (SMBIOS type 42h)
according to Redﬁsh services information, conﬁgure system BIOS setting using Redﬁsh service or etc.
1396Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
31.1.2 EFI Redﬁsh Discover Driver
A Redﬁsh Discover Driver installs the Redﬁsh Discover Protocol and EFI Driver Binding Protocol in its driver entry
point.
The Driver Binding Protocol contains three services. These are Supported() ,Start() , and Stop() .Supported() tests to
see if the Redﬁsh Discover Driver can manage a device handle. A Redﬁsh Discover Driver can manage device handle
that contain the EFI REST EX Service Binding Protocol, EFI UDP4 Service Binding Protocol or EFI UDP6 Service
Binding Protocol, so a Redﬁsh Discover Driver must look for these three protocols on the device handle that is being
tested, and return success if any of them is presented.
The Start() function tells the Redﬁsh Discover Driver to start managing a device driver. The device handle should
support at least one of the service binding protocols checked in Supported() .The Redﬁsh Discover Driver should
create a child handle for each service binding protocol, and open these children with BY_DRIVER attribute.
TheStop() function tells the Redﬁsh Discover Driver to stop managing a device driver. The Stop() function can destroy
one or more of the device handles (or its child handles) that being managed by Redﬁsh Discover Driver. A Redﬁsh
Discover Driver should stop the in-process discovery and destroy corresponding child handle which was created in a
previous call to Start() , or in AcquireRedﬁshService() .
31.1.3 EFI Redﬁsh Discover Client
An EFI Redﬁsh client invokes EFI Redﬁsh Discover Protocol to acquire the ready-to-use EFI REST EX protocol
instance.
Below is the conceptual ﬁgure of mechanism of EFI Redﬁsh Discover Protocol. The ﬁrst scenario is unicast M-
SEARCH to verify Redﬁsh service reported in SMBIOS type 42h. ..
1. EFI Redﬁsh client invokes EFI Redﬁsh Discover Protocol to acquire ready-to-use EFI REST EX for communi-
cating with Redﬁsh services reported in Redﬁsh Host Interface (SMBIOS type 42h)
2. EFI Redﬁsh Discover Protocol optionally veriﬁes the existence of Redﬁsh service by unicasting M-SEARCH to
Redﬁsh service according to the Redﬁsh service information provided in Redﬁsh Host Interface.
3. 3EFI Redﬁsh Discover Protocol creates and conﬁgures REST EX instance for Redﬁsh service according to the
Redﬁsh service information provided in Redﬁsh Host Interface.
4. EFI Redﬁsh clients communicate with Redﬁsh service using EFI REST EX instance returned from EFI Redﬁsh
Discover protocol.
EFI Redﬁsh client passes EFI_REDFISH_DISCOVERED_TOKEN and the discovery options to EFI Redﬁsh Discover
Protocol. EFI_EVENT is created by EFI Redﬁsh client for retrieving EFI_REDFISH_DISCOVERED_LIST once EFI
Redﬁsh Discover Protocol optionally veriﬁes Redﬁsh service reported by Redﬁsh Host Interface. EFI Redﬁsh client
31.1. EFI Redﬁsh Discover Protocol 1397Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
can listen to the notiﬁcation of veriﬁed Redﬁsh service in asynchronous or synchronous according to the setting of
options indicated in EFI_REDFISH_DISCOVER_FLAG .
The second scenario is optionally provided by EFI Redﬁsh Discover Protocol, which is multicast M-SEARCH to
discover Redﬁsh services.
1. EFI Redﬁsh client gets the list of network interfaces if it would like to discover Redﬁsh services on the certain
network.
2. EFI Redﬁsh client invokes EFI Redﬁsh Discover Protocol to acquire ready-to-use EFI REST EX for communi-
cating with Redﬁsh services.
3. EFI Redﬁsh Discover Protocol discovers Redﬁsh services through SSDP over UDP.
Protocol. EFI_EVENT is created by EFI Redﬁsh client for retrieving EFI_REDFISH_DISCOVERED_LIST when
any time EFI Redﬁsh Discover Protocol discovers new Redﬁsh service. EFI Redﬁsh client can listen to the notiﬁ-
cation of new found Redﬁsh service in asynchronous or synchronous according to the setting of options indicated
inEFI_REDFISH_DISCOVER_FLAG . Setting Timeout to zero in EFI_REDFISH_DISCOVERED_TOKEN to wait-
ing for the new discovered Redﬁsh service in synchronously, otherwise asynchronous notiﬁcation happens when new
Redﬁsh service is discovered by EFI Redﬁsh Discover Protocol.
31.1. EFI Redﬁsh Discover Protocol 1398Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
31.1.4 EFI Redﬁsh Discover Protocol
Summary
This protocol is utilized by EFI Redﬁsh clients to acquire the list of Redﬁsh services provided on platform or network.
#define EFI_REDFISH_DISCOVER_PROTOCOL_GUID \
{0x5db12509, 0x4550, 0x4347,
{0x96, 0xb3, 0x73, 0xc0, 0xff, 0x6e, 0x86, 0x9f}}
typedef struct _EFI_REDFISH_DISCOVER_PROTOCOL {
EFI_REDFISH_DISCOVER_NETWORK_LIST GetNetworkInterfaceList;
EFI_REDFISH_DISCOVER_ACQUIRE_SERVICE AcquireRedfishService;
EFI_REDFISH_DISCOVER_ABORT_ACQUIRE AbortAcquireRedfishService;

Summary
EFI_REDFISH_DISCOVER_RELEASE_SERVICE ReleaseRedfishService;
} EFI_REDFISH_DISCOVER_PROTOCOL;
GetNetworkInterfaceList Get the list of network interfaces on which Redﬁsh services could be discovered.
AcquireRedﬁshService Acquire the list of Redﬁsh services.
AbortAcquireRedﬁshService Abort Redﬁsh services acquire process.
ReleaseRedﬁshService Release Redﬁsh services acquired from AcquireRedﬁshService().
31.1. EFI Redﬁsh Discover Protocol 1399Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI Redﬁsh Discover Protocol provides a mechanism for EFI Redﬁsh clients to acquire the Redﬁsh services provided
on the platform or network as described before.
31.1.4.1 EFI_REDFISH_DISCOVER_PROTOCOL.GetNetworkInterfaceList()
Summary
Get the currently available list of network interfaces on which Redﬁsh services could be discovered.
typedef
(EFIAPI *EFI_REDFISH_DISCOVER_NETWORK_LIST)(
IN EFI_REDFISH_DISCOVER_PROTOCOL *This,
OUT UINTN *NumberOfNetworkInterfaces,
OUT EFI_REDFISH_DISCOVER_NETWORK_INTERFACE **NetworkInterfaces
);
This This is the EFI_REDFISH_DISCOVER_PROTOCOL instance.
ImageHandle EFI image to get network list. The image handle is caller’s image handle.
NumberOfNetworkInterfaces Number of network interfaces in NetworkInterfaces.
NetworkInterfaces It’s an array of instances. The number of entries in NetworkInterfaces is indicated by Num-
berOfNetworkInterfaces. Caller has to release the memory allocated by Redﬁsh discover protocol with a call to
EFI_BOOT_SERVICES.FreePool().
This function is used to get the list of network interfaces which can be used to send SSDP message over UDP
protocol for the Redﬁsh services discovery. The entry in NetworkInterfaces could be used as the parameter to
EFI_REDFISH_DISCOVER_PROTOCOL .AcquireRedﬁshService function for discovering Redﬁsh service on speciﬁc
Related Description
// EFI_REDFISH_DISCOVER_NETWORK_INTERFACE
EFI_MAC_ADDRESS MacAddress;
BOOLEAN IsIpv6;
EFI_IP_ADDRESS SubnetId;
UINT8 SubnetPrefixLength;
} EFI_REDFISH_DISCOVER_NETWORK_INTERFACE;
MacAddress MAC address of this network interface.
IsIpv6 If TRUE, indicates the network interface is running IPv6. Otherwise the network interface is running IPv4.
SubnetId Subnet of this network.
31.1. EFI Redﬁsh Discover Protocol 1400Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SubnetPreﬁxLength Subnet preﬁx-length for IPv4 and IPv6.
VlanId VLAN ID of this network interface.
EFI_SUCCESS Network interface is returned in NetworkInterfaces and the number of net-
work interfaces is returned in NumbermOfNetworkInterfaces successfully.
EFI_INV ALID_PARAMETER One of below parameters is NULL. ImageHandle ,NumberOfNetworkInter-
faces , and NetworkInterfaces
EFI_UNSUPPORTED Unable to return network interface list.
EFI_NOT_FOUND No network interfaces are found.
EFI_OUT_OF_RESOURCE Not enough resources to return network interfaces to caller.
31.1.4.2 EFI_REDFISH_DISCOVER_PROTOCOL.AcquireRedﬁshService()
Summary
This function acquires the list of discovered Redﬁsh services.
typedef
(EFIAPI *EFI_REDFISH_DISCOVER_ACQUIRE_SERVICE)(
IN EFI_REDFISH_DISCOVER_NETWORK_INTERFACE *TargetNetworkInterface OPTIONAL,
IN EFI_REDFISH_DISCOVER_FLAG Flags,
IN EFI_REDFISH_DISCOVERED_TOKEN *Token
);
ImageHandle EFI image acquires Redﬁsh service discovery. The image handle is caller’s image handle.
TargetNetworkInterface The target Network Interface which is used to discover Redﬁsh services. Set to NULL to
discover Redﬁsh services on all network interfaces.
Flags Options of Redﬁsh service discovery.
Token
EFI_REDFISH_DISCOVERED_TOKEN instance. The memory of
EFI_REDFISH_DISCOVERED_LIST and the strings in
EFI_REDFISH_DISCOVERED_INFORMATION are all allocated by
AcquireRedﬁshService() and must be freed when caller invokes
ReleaseRedﬁshService() .
This function is used to acquire the list of Redﬁsh services which are discovered according to Redﬁsh Host Interface or
through SSDP over UDP. Redﬁsh services discovery through SSDP over UDP could be achieved via network interface
speciﬁed in TargetNetworkInterface or via all network interfaces if TargetNetworkInterface is speciﬁed as NULL.
EFI_REDFISH_DISCOVERED_LIST is returned to EFI Redﬁsh client by signaling the EFI event created by client.
Each of EFI handle in EFI_REDFISH_DISCOVERED_LIST has the corresponding EFI REST EX instance installed
on it. Each REST EX instance is a child instance which is created through EFI REST EX service binding protocol and
31.1. EFI Redﬁsh Discover Protocol 1401Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
used by EFI Redﬁsh client for communicating with speciﬁc Redﬁsh service. In AcquireRedﬁshService(), UDP child
is created and opened to do SSDP discovery. This UDP child will be destroyed right away after the discovery is done.
AcquireRedﬁshService()also creates and opens REST EX child to conﬁgures REST EX instance according to Redﬁsh
service information retuned in M-SEARCH response or Redﬁsh Host Interface. REST EX child must be closed after
REST EX child is conﬁgured. EFI Redﬁsh client must open REST EX instance from RedﬁshRestExHandle returned
inEFI_REDFISH_DISCOVERED_INFORMATION and close REST EX instance once EFI Redﬁsh client is no longer
communicating with Redﬁsh service.
// EFI_REDFISH_DISCOVER_FLAG
#define EFI_REDFISH_DISCOVER_HOST_INTERFACE 0x00000001
#define EFI_REDFISH_DISCOVER_SSDP 0x00000002
#define EFI_REDFISH_DISCOVER_SSDP_UDP6 0x00000004
#define EFI_REDFISH_DISCOVER_KEEP_ALIVE 0x00000008
#define EFI_REDFISH_DISCOVER_RENEW 0x00000010
#define EFI_REDFISH_DISCOVER_VALIDATION 0x80000000
#define EFI_REDFISH_DISCOVER_DURATION_MASK 0x0f000000
EFI_REDFISH_DISCOVER_FLAG is used to indicate the options when EFI Redﬁsh clients acquire Redﬁsh dis-
cover list through this protocol. Redﬁsh Discover Protocol discovers Redﬁsh service according to Redﬁsh Host
Interface when EFI_REDFISH_DISCOVER_HOST_INTERFACE is set to TRUE . Redﬁsh Discover Protocol also
optionally discovers Redﬁsh services using SSDP UPnP M-SEARCH request through UDP Port 1900. Redﬁsh
Discover Protocol returns EFI_INVALID_PARAMETER if none of EFI_REDFISH_DISCOVER_HOST_INTERFACE
andEFI_REDFISH_DISCOVER_SSDP is set to TRUE . Set EFI_REDFISH_DISCOVER_SSDP_UDP6 to indicate
using IPv6 as internet protocol. For the Redﬁsh service discovery according to Redﬁsh Host Interface, Red-
ﬁsh service information like IP address is descripted in Redﬁsh Host Interface. EFI Redﬁsh client can set
EFI_REDFISH_DISCOVER_VALIDATION toTRUE to ask Redﬁsh Discover Protocol to validate this Redﬁsh ser-
vice using IP address described in Redﬁsh Host Interface. Redﬁsh Discover Protocol unicasts UPnP M-SEARCH
request to the target Redﬁsh service and verify the response message to determine if the target Redﬁsh service is
existing or not. EFI_REDFISH_DISCOVER_VALIDATION doesn’t affect the SSDP discovery. For Redﬁsh SSDP
discovery, the responses of the multicast UPnP M-SEARCH request imply the valid Redﬁsh services are existing.
According to UPnP device architecture, the maximum waiting time of the response to UPnP M-
SEARCH request is indicated in MX message header. The value is greater or equal to 1 to less
than 5 inclusive in second. In order to give the chance to those Redﬁsh services which do not
respond to M-SEARCH in time, set EFI_REDFISH_DISCOVER_KEEP_ALIVE toTRUE to tell Red-
ﬁsh Discover Protocol keeps to sending multicast M-SEARCH request. The duration of periodi-
cal multicast request is declared in EFI_REDFISH_DISCOVER_DURATION_MASK . The value indicated in
EFI_REDFISH_DISCOVER_DURATION_MASK means 2 to the power of duration. The valid value of duration is
greater or equal to 3 and less or equal to 15. The corresponding duration is 8 to 2^15 seconds. Minimum duration is
set to 8 seconds in order to keep the duration out of scope of MX value deﬁned in UPnP device architecture. Duration
is only valid when EFI_REDFISH_DISCOVER_KEEP_ALIVE is set to TRUE andEFI_REDFISH_DISCOVER_SSDP
is set to TRUE .
Redﬁsh Discover Protocol maintains an internal database of Redﬁsh services it found. It also maintains the EFI image
which owns the EFI REST EX instance of discovered Redﬁsh services. Redﬁsh Discover Protocol only signals EFI
Redﬁsh client with new found of Redﬁsh services instead of notifying EFI Redﬁsh client the duplicate Redﬁsh services
found earlier, unless EFI_REDFISH_DISCOVER_RENEW is set to TRUE. Set EFI_REDFISH_DISCOVER_RENEW

toTRUE forces Redﬁsh Discover Protocol to notify EFI Redﬁsh clients all found Redﬁsh services, even the Redﬁsh
service which was already discovered and notiﬁed previously.
31.1. EFI Redﬁsh Discover Protocol 1402Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_REDFISH_DISCOVERED_TOKEN
#define REDFISH_DISCOVER_TOKEN_SIGNATURE SIGNATURE_32 ('R', 'F', 'T', 'S')
UINT32 Signature
EFI_REDFISH_DISCOVERED_LIST DiscoveredList;
UINTN Timeout;
} EFI_REDFISH_DISCOVERED_TOKEN;
EFI_REDFISH_DISCOVERED_TOKEN is created by EFI Redﬁsh client and passed to AcquireRedﬁshService() .
Signature The token signature should be the value of REDFISH_DISCOVER_TOKEN_SIGNATURE deﬁned above.
DiscoveredList Structure of EFI_REDFISH_DISCOVERED_LIST to retrieve the discovered Redﬁsh services.
Event EFI event at the TPL_CALLBACK level created by EFI Redﬁsh client, which is used to be notiﬁed when
Redﬁsh services are discovered or any errors occurred during discovery.
Timeout The timeout value declared in EFI_REDFISH_DISCOVERED_TOKEN determines the seconds to drop dis-
covery process. Basically, the nearby Redﬁsh services must give the response in >=1 and <= 5 seconds. The
valid timeout value used for the asynchronous discovery is >= 1 and <= 5 seconds. Set the timeout to zero means
to discover Redﬁsh service synchronously.
// EFI_REDFISH_DISCOVERED_LIST
UINTN NumberOfServiceFound;
EFI_REDFISH_DISCOVERED_INSTANCE *RedfishInstances;
} EFI_REDFISH_DISCOVERED_LIST;
The content of EFI_REDFISH_DISCOVERED_LIST is ﬁlled by AcquireRedﬁshService() before signaling Event.
NumberOfServiceFound must be set to 0 and RedﬁshInstances must be NULL when client invokes AcquireRedﬁsh-
Service() . The memory block for RedﬁshInstances is allocated by the EFI Redﬁsh Discover Protocol,and will be freed
by the EFI Redﬁsh Discover Protocol as well in ReleaseRedﬁshService() .
NumberOfServiceFound Number of Redﬁsh services are discovered.
RedﬁshInstances Pointer to EFI_REDFISH_DISCOVERED_INSTANCE , number of Redﬁsh services are discovered
is indicated in NumberOfServiceFound.
// EFI_REDFISH_DISCOVERED_INSTANCE
EFI_REDFISH_DISCOVERED_INFORMATION Information;
} EFI_REDFISH_DISCOVERED_INSTANCE;
This structure describes the status and the information of discovered Redﬁsh service.
31.1. EFI Redﬁsh Discover Protocol 1403Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Status EFI status code of Redﬁsh service discovery.
Information The information of Redﬁsh service discovered. The information is only valid when Status is
EFI_SUCCESS. Refer to below description of EFI_REDFISH_DISCOVERED_INSTANCE .
// EFI_REDFISH_DISCOVERED_INFORMATION
EFI_HANDLE RedfishRestExHandle;
BOOLEAN IsIPv6;
EFI_IP_ADDRESS RedfishHostIpAddress;
UINT16 RedfishVersion;
CHAR16 *Location;
CHAR16 *Uuid;
CHAR16 *Os;
CHAR16 *OsVersion;
CHAR16 *Product;
CHAR16 *ProductVersion;
BOOLEAN UseHttps;
} EFI_REDFISH_DISCOVERED_INFORMATION;
This structure describes each Redﬁsh service information. The corresponding EFI REST EX protocol instance is
also created and conﬁgured by EFI Redﬁsh Discover Protocol for EFI Redﬁsh client. The memory allocated for the
information in this structure will be freed by EFI Redﬁsh Discover Protocol in ReleaseRedﬁshService() .
RedﬁshRestExHandle EFI handle which has EFI REST EX protocol instance installed on it. The EFI REST EX
protocol instance is already conﬁgured by EFI Redﬁsh Discover Protocol through EFI_REST_EX_PROTOCOL
.Conﬁgure() according to the Redﬁsh host information discovered through Redﬁsh Host Interface or SSDP.
IsIPv6 Indicates the Redﬁsh service is reached via IPv6 protocol.
RedﬁshHostIpAddress Redﬁsh service host IP address.
RedﬁshVersion Redﬁsh service version. The high byte of RedﬁshVersion is the major Redﬁsh service version, low
byte is the minor Redﬁsh version. For example 0x100 is Redﬁsh service. Redﬁsh service version is acquired
from “ST” header in the response of M-SEARCH request.
Location Redﬁsh service host location, this information is acquired from “Server” header returned in the response of
M-SEARCH request.
Uuid The UUID of Redﬁsh service, this information is acquired from “USN” header deﬁned in UPnP Device Archi-
tecture speciﬁcation.
OsThe OS provides Redﬁsh service, this information is acquired from “Server” header returned in the response of M-
SEARCH request. Below is the response in “Server” header deﬁned in UPnP Device Architecture speciﬁcation.
SERVER:OS/version UPnP/1.1 product/version OsVersion Redﬁsh service OS version, this information is ac-
quired from “Server” header returned in the response of M-SEARCH request. Below is the response in “Server”
header deﬁned in UPnP Device Architecture speciﬁcation. SERVER:OS/version UPnP/1.1 product/version
Product Product name, this information is extracted from “Server” header returned in the response of M-SEARCH
request. Below is the response in “Server” header deﬁned in UPnP Architecture Device speciﬁcation.
SERVER:OS/version UPnP/1.1 product/version
ProductVersion Product version, this information is acquired from “Server” header returned in the response of M-
31.1. EFI Redﬁsh Discover Protocol 1404Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
| SERVER:OS/version UPnP/1.1 product/version UseHttps Indicates the Redﬁsh service is reached via HTTPS
protocol.
EFI_SUCCESS Acquire for Redﬁsh service list is successful.
EFI_INV ALID_PARAMATER
ImageHandle isNULL .
Flags is 0 or the improper bit combination of option is set in Flag.
Token->Timeout is greater than 5 seconds.
Token->Event isNULL .
On input,
•Token->DiscoveredList.NumberOfServiceFound is not 0, or
•Token-> DiscoveredList->RedﬁshInstances is not NULL .
Others Fail to acquire the list of Redﬁsh service.
31.1.4.3 EFI_REDFISH_DISCOVER_PROTOCOL.AbortAcquireRedﬁshService()
Summary
This function aborts Redﬁsh service discovery on the given network interface.
typedef
(EFIAPI *EFI_REDFISH_DISCOVER_ABORT_ACQUIRE)(
IN*EFI_REDFISH_DISCOVER_NETWORK_INTERFACE *TargetNetworkInterface OPTIONAL
);
TargetNetworkInterface The target Network Interface on which Redﬁsh services discovery is in process. NULL to
abort Redﬁsh service discovery on all network interfaces.
InAbortAcquireRedﬁshService() , to abort the in-process Redﬁsh service, discovery is required for preventing unex-
pected behaviors from happening. This function has to cancel in-process SSDP, the unicast over Udp4/Udp6, close
Udp4/Udp6 protocol and destroy the Udp4/Udp6 child. Also closes REST EX opened for conﬁguring REST EX child
instance.
31.1. EFI Redﬁsh Discover Protocol 1405Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS Redﬁsh service discovery is aborted.
-This isNULL .
31.1.4.4 EFI_REDFISH_DISCOVER_PROTOCOL.ReleaseRedﬁshService()
Summary
This function releases the list of Redﬁsh services discovered previously.
typedef
(EFIAPI *EFI_REDFISH_DISCOVER_RELEASE_SERVICE)(
IN EFI_REDFISH_DISCOVERED_LIST *List
);
List The pointer to EFI_REDFISH_DISCOVERED_LIST which lists the Redﬁsh services to release.
The Redﬁsh services which listed in List will be released in ReleaseRedﬁshService() . All memory blocks which were
allocated for Redﬁsh service information will be freed in this function. EFI REST EX protocol instance which was
created in AcquireRedﬁshService() will be also destroyed in ReleaseRedﬁshService() . The Redﬁsh service listed in
**List* is not required to be identical or in the same order with EFI_REDFISH_DISCOVERED_LIST retuned from
AcquireRedﬁshService() . List is ﬂexible to list any Redﬁsh services which were discovered by AcquireRedﬁshSer-

Summary
typedef
);
vice() earlier. In ReleaseRedﬁshService(), free the resource allocated for the discovered Redﬁsh service indicated in
EFI_REDFISH_DISCOVERED_LIST .
EFI_SUCCESS The Redﬁsh services listed in **List* are released successfully.
-ListisNULL .
- Invalid settings in *List.
31.1. EFI Redﬁsh Discover Protocol 1406Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
31.1.5 Implementation Examples
31.1.5.1 Processes to Discover Redﬁsh Services
The following ﬂowchart delineates the EFI Redﬁsh client processes of utilizing EFI Discover Protocol to discover
Redﬁsh service, abort discovery and release discovered Redﬁsh service instance.
31.1.5.2 Network Interface Conﬁguration
The EFI Redﬁsh Discover Protocol provides a Redﬁsh service discovery function to discover Redﬁsh service through
SMBIOS type 42 or optionally discover Redﬁsh service on speciﬁc network interface. EFI Redﬁsh Clients (EFI driver
or EFI Application) can utilize the discover function to acquire Redﬁsh service and manipulate Redﬁsh properties to
manage a system. For example, applying BIOS settings on the systems managed by Redﬁsh Service. The system could
be the one that runs EFI Redﬁsh Client, or other systems on the network. If Redﬁsh service is discovered according to
SMBIOS type 42, then the platform developer has to create an SMBIOS type 42 entry with host (station) and Redﬁsh
Service information (Refer to DSP0270, Redﬁsh Host Interface Speciﬁcation). Besides discovering Redﬁsh service
using SMBIOS type 42, Redﬁsh services can be also discovered by using SSDP over UDP. However, the network
interface must be conﬁgured using either DHCP or static conﬁguration prior to discovery of Redﬁsh services. If the
network interface is conﬁgured statically, then at least the IP address and Subnet mask must be conﬁgured for the
station. The VLAN ID and new route entry may need to be conﬁgured depending on the networking environment if
Below is the implementation example for conﬁguring network interface. Network interface could be conﬁgured in
platform-implementation method. For example, platform developer can provide HII network options in BIOS setup
utility. Network interface could be conﬁgured in statically or dynamically (DHCP) manner and the conﬁguration
could be stored in EFI variables or any platform non-volatile storage which may consumed by network stacks when
each time system boot. This makes sure certain network interface is conﬁgured properly before EFI Redﬁsh Clients
utilizing EFI Redﬁsh Discover Protocol.
The alternative of conﬁguring network stack is system boots to EFI Shell and execute ifconﬁg shell command. This
conﬁgures the settings of certain network interfaces. After this, network interface is ready to process Redﬁsh service
31.1. EFI Redﬁsh Discover Protocol 1407Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
discovery by EFI Redﬁsh Clients. However, this method requires user to conﬁgure network interface when each time
system boot to EFI shell, unless other implementations of ifconﬁg EFI shell command is provided.
Once EFI Redﬁsh Client is launched, it gets network interface information using EFI Redﬁsh Discover protocol. EFI
Redﬁsh Client may provide selection UI of network interfaces for Redﬁsh service discovery. EFI Redﬁsh Client could
manipulate Redﬁsh properties such as BIOS Attributes on the discovered Redﬁsh services for system management
or deployment. EFI Redﬁsh Client can also optionally maintain the information, location and other properties of
discovered Redﬁsh services in non-volatile storage for next system boots afterward.
31.2 EFI Redﬁsh JSON Structure Converter
31.2.1 The Guidance of Writing EFI Redﬁsh JSONStructure Converter
To provide interoperability between the Redﬁsh service and the EFI environment, EFI Redﬁsh JSON structure con-
verters for each Redﬁsh schema namespace should be implemented for EFI Redﬁsh clients. This recommendation of
writing EFI Redﬁsh JSON structure converters is necessary to unify the implementation and capability of the convert-
ers.
• One converter supports one Redﬁsh schema resource type; write the converter based on Redﬁsh resource type.
Using Redﬁsh schema as an example:
— AccountService.v1_0_0.json: RedﬁshAccountService_V1_0_0_Dxe driver
— AttributeRegistry.v1_2_0.json: RedﬁshAttributeRegistry_V1_2_0_Dxe driver
— EthernetInterface.v1_4_0.json : EthernetInterface_V1_4_0_Dxe driver
• Redﬁsh JSON structure converter can be delivered in source code package or binary (library or EFI driver)
format.
31.2. EFI Redﬁsh JSON Structure Converter 1408Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• A C header ﬁle must be released with the Redﬁsh JSON structure converter package. The package could be
provisioned to conform to any EFI implementation, such as EFI EDKII open source.
• Provide documents which can describe the usage of structure members deﬁned in REST JSON structure.
• The documentation can be published with a source code package, binary package, web site, online help, etc.
• Write the converter as an EFI DXE driver, and utilize EFI_REST_JSON_STRUCTURE_PROTOCOL to register
the converter to provide the corresponding EFI_REST_JSON_STRUCTURE_PROTOCOL functions:
—ToStructure()
—ToJson()
—DestoryStructure()
• FI_REST_JSON_RESOURCE_TYPE_IDENTIFIER
Namespace
ResourceTypeName: String to Redﬁsh schema resource type.
MajorVersion: String to Redﬁsh schema major version, NULL string for non version controlled schema.
MinorVersion: String to Redﬁsh schema minor version, NULL string for non version controlled schema.
ErrataVersion: String to Redﬁsh schema errata version, NULL string for non version controlled schema. Datatype
Datatype
String to data type deﬁned in Redﬁsh schema
Examples
AccountService.v1_0_0.json
Namespace
ResourceTypeName: “AccountService” MajorVersion:”1” MinorVersion:”0” ErrataVErsion:”0”
Datatype: “AccountService”
Namespace
ResourceTypeName: “ComputerSystemCollection” MajorVersion:NULL MinorVersion:NULL ErrataVErsion:NULL
Datatype: “ComputerSystemCollection”
• Determine Redﬁsh resource type according to the given JsonRsrcIdentiﬁer. If the given JsonRsrcIdentiﬁer is
non-NULL, the Redﬁsh resource structure converter must convert the JSON resource to the Redﬁsh JSON
structure according to the resource type and revision speciﬁed in JsonRsrcIdentiﬁer. The converter should not
refer to the resource type and revision according to Redﬁsh namespace and datatype indicated in “odata.type” in
JSON text resource. This prevents from the returned structure format is different with what consumer expects.
• Automatically determine the Redﬁsh resource type. If the given JsonRsrcIdentiﬁer is NULL, the EFI
Redﬁsh JSON structure converter should check the namespace and datatype indicated in “odata.type”
in the JSON text resource. Parse this identiﬁer property to retrieve the corresponding Redﬁsh schema
name space and data type, then decode the JSON text resource into the corresponding structure.
EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER in JsonStructure returned to consumer should be ﬁlled
with the correct Redﬁsh schema resource type information following the guidance mentioned above.
31.2. EFI Redﬁsh JSON Structure Converter 1409Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• All structure members for Redﬁsh schema must be declared as C pointers. With this, the converter consumer
can get the partial Redﬁsh JSON properties from the converter. The consumer just initializes certain structure
members, and the converter producer only converts non-NULL pointers in the given structure into corresponding
Redﬁsh JSON properties in text format.
31.2.2 The Guidance of Using EFI Redﬁsh JSON Structure Converter
The consumer of EFI Redﬁsh JSON structure converter utilizes EFI_REST_JSON_STRUCTURE_PROTOCOL for
converting Redﬁsh JSON resource to Redﬁsh JSON structure and vice versa.
Refer to the converter document to include the C header ﬁle of the Redﬁsh JSON structure converter into the build
process. For example, include the converter’s EDKII package into an EFI module INF ﬁle for the C header ﬁle
reference, or follow the build rule of other EFI implementations.
There are two ways for a consumer to convert JSON resources using the
EFI_REST_JSON_STRUCTURE_PROTOCOL:
• Setup the crorect Redﬁsh namespace and datatype in EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER.
This makes sure the EFI REST JSON Structure Protocol uses the exact converter that the consumer prefers
for the conversion. In this case, the Redﬁsh namespace and datatype indicated in “odata.type” in the
EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER is set to NULL. This means the converter may recog-
nize the Redﬁsh namespace and datatype indicated in “odata.type” in the JSON text resource, and converts it to

the C structure it supports. In this case, the consumer has to be careful when using a C structure pointer to refer
to the Redﬁsh JSON structure.
• EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER set to NULL means the returned structure format
may not be in the same form as the consumer’s expectation. The consumer then has to check the
EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER for the Redﬁsh namespace and datatype, and use the
correct prototype for structure reference.
31.2. EFI Redﬁsh JSON Structure Converter 1410CHAPTER
THIRTYTWO
SECURE BOOT AND DRIVER SIGNING
32.1 Secure Boot
This protocol is intended to provide access for generic authentication information associated with speciﬁc device paths.
The authentication information is conﬁgurable using the deﬁned interfaces. Successive conﬁguration of the authenti-
cation information will overwrite the previously conﬁgured information. Once overwritten, the previous authentication
information will not be retrievable.
32.1.1 EFI_AUTHENTICATION_INFO_PROTOCOL
Summary
This protocol is used on any device handle to obtain authentication information associated with the physical or logical
device.
GUID
#define EFI_AUTHENTICATION_INFO_PROTOCOL_GUID \
{0x7671d9d0,0x53db,0x4173,\
{0xaa,0x69,0x23,0x27,0xf2,0x1f,0x0b,0xc7}}
typedef struct _EFI_AUTHENTICATION_INFO_PROTOCOL {
EFI_AUTHENTICATION_INFO_PROTOCOL_GET Get;
EFI_AUTHENTICATION_INFO_PROTOCOL_SET Set;
} EFI_AUTHENTICATION_INFO_PROTOCOL;
Get() Used to retrieve the Authentication Information associated with the controller handle
Set() Used to set the Authentication information associated with the controller handle
TheEFI_AUTHENTICATION_INFO_PROTOCOL provides the ability to get and set the authentication information
associated with the controller handle.
1411Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
32.1.2 EFI_AUTHENTICATION_INFO_PROTOCOL.Get()
Summary
Retrieves the Authentication information associated with a particular controller handle.
Prototype
typedef
(EFIAPI *EFI_AUTHENTICATION_INFO_PROTOCOL_GET) (
IN EFI_AUTHENTICATION_INFO_PROTOCOL *This,
);
This Pointer to the EFI_AUTHENTICATION_INFO_PROTOCOL
ControllerHandle Handle to the Controller
Buffer Pointer to the authentication information. This function is responsible for allocating the buffer and it is the
caller’s responsibility to free buffer when the caller is ﬁnished with buffer.
This function retrieves the Authentication Node for a given controller handle.
EFI_SUCCESS Successfully retrieved Authentication information for the given Controller-
Handle
EFI_INV ALID_PARAMETER No matching Authentication information found for the given Controller-
Handle
EFI_DEVICE_ERROR The authentication information could not be retrieved due to a hardware
error.
32.1.3 EFI_AUTHENTICATION_INFO_PROTOCOL.Set()
Summary
Set the Authentication information for a given controller handle.
Prototype
typedef
(EFIAPI *EFI_AUTHENTICATION_INFO_PROTOCOL_SET) (
IN EFI_AUTHENTICATION_INFO_PROTOCOL **This,
IN EFI_HANDLE *ControllerHandle
IN VOID **Buffer
);
ControllerHandle Handle to the controller.
32.1. Secure Boot 1412Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Buffer Pointer to the authentication information.
This function sets the authentication information for a given controller handle. If the authentication node exists corre-
sponding to the given controller handle this function overwrites the previously present authentication information.
EFI_SUCCESS Successfully set the Authentication node information for the given Con-
EFI_UNSUPPORTED If the platform policies do not allow setting of the Authentication informa-
tion.
EFI_DEVICE_ERROR The authentication node information could not be conﬁgured due to a hard-
ware error.
EFI_OUT_OF_RESOURCES Not enough storage is available to hold the data.
32.1.4 Authentication Nodes
The authentication node is associated with speciﬁc controller paths. There can be various types of authentication
nodes, each describing a particular authentication method and associated properties.
32.1.5 Generic Authentication Node Structures
An authentication node is a variable length binary structure that is made up of variable length authentication infor-
mation. The Table below deﬁnes the generic structure. The Authentication type GUID deﬁnes the corresponding
authentication node.
Table 32.2: Generic Authentication Node Structure
Type GUID 0 16 Authentication Type GUID
Length 16 2 Length of this structure in bytes.
Speciﬁc Au-
thentication
Data18 n Speciﬁc Authentication Data. Type deﬁnes the authen-
tication method and associated type of data. Size of the
data is included in the length.
All Authentication Nodes are byte-packed data structures that may appear on any byte boundary. All code references
to Authentication Nodes must assume all ﬁelds are UNALIGNED. Since every Authentication Node contains a length
ﬁeld in a known place, it is possible to traverse Authentication Node of unknown type.
32.1.6 CHAP (using RADIUS) Authentication Node
This Authentication Node type deﬁnes the CHAP authentication using RADIUS information.
GUID
#define EFI_AUTHENTICATION_CHAP_RADIUS_GUID \
{0xd6062b50,0x15ca,0x11da,\
{0x92,0x19,0x00,0x10,0x83,0xff,0xca,0x4d}}
Node Deﬁnition
32.1. Secure Boot 1413Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 32.3: CHAP Authentication Node Structure using RADIUS
Type 0 16 EFI_A UTHENTICATION_C HAP_RADIUS_GUID
Length 16 2 Length of this structure in bytes. Total length is
58+P+Q+R+S+T
RADIUS IP Ad-
dress18 16 Radius IPv4 or IPv6 Address
Reserved 34 2 Reserved
NAS IP Address 36 16 NAS IPv4 or IPv6 Address
NAS Secret Length 52 2 NAS Secret LengthP
NAS Secret 54 p NAS Secret
CHAP Secret
Length54+P 2 CHAP Secret Length Q
CHAP Secret 56+P q CHAP Secret
CHAP Name
Length56 +Q 2 CHAP Name Length R
CHAP Name 58+P+Q r CHAP Name String
Reverse CHAP
Name Length58+P+Q+R 2 Reverse CHAP Name length
Name60+P+Q+R S Reverse CHAP Name
Reverse CHAP Se-
cret Length60+P+Q+R+S 2 Reverse CHAP Length
cret62+P+Q+R+S T Reverse CHAP Secret
Summary
RADIUS IP Address. . . RADIUS Server IPv4 or IPv6 Address
NAS IP Address. . . Network Access Server IPv4 or IPv6 Address (OPTIONAL)
NAS Secret Length. . . Network Access Server Secret Length in bytes (OPTIONAL)
NAS Secret. . . Network Access Server secret (OPTIONAL)
CHAP Secret Length. . . CHAP Initiator Secret length in bytes
CHAP Secret. . . CHAP Initiator Secret
CHAP Name. . . Length CHAP Initiator Name Length in bytes
CHAP Name CHAP Initiator Name
Reverse CHAP name length Reverse CHAP name length
Reverse CHAP Name Reverse CHAP name
Reverse CHAP Secret Length Reverse CHAP secret length
Reverse CHAP Secret Reverse CHAP secret
CHAP (using local database)Authentication Node
This Authentication Node type deﬁnes CHAP using local database information.
GUID
#define EFI_AUTHENTICATION_CHAP_LOCAL_GUID \
{0xc280c73e,0x15ca,0x11da,\
{0xb0,0xca,0x00,0x10,0x83,0xff,0xca,0x4d}}
32.1. Secure Boot 1414Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 32.4: CHAP Authentication Node Structure using Local Database
Type 0 16 EFI_AUTHENTICATION_CHAP_LOCAL_GUID
Reserved 18 2 Reserved for future use
User Secret
Length20 2 User Secret Length
User Secret 22 p User Secret
User Name
Length22+p 2 User Name Length
User Name 24+p q User Name
Length24+p+q 2 CHAP Secret Length
CHAP Secret 26+p+q r CHAP Secret
CHAP Name
Length26+p+q+r 2 CHAP Name Length
CHAP Name 28+p+q+r s CHAP Name String
Secret Length60+P+Q+R+S 2 Reverse CHAP Length
Secret62+P+Q+R+S T Reverse CHAP Secret
Summary
User Secret Length. . . User Secret Length in bytes
User Secret. . . User Secret
User Name Length. . . User Name Length in bytes
User Name. . . User Name
CHAP Name Length. . . CHAP Initiator Name Length in bytes
CHAP Name. . . CHAP Initiator Name
32.1. Secure Boot 1415Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
32.2 UEFI Driver Signing Overview
This section describes a means of generating a digital signature for a UEFI executable, embedding that digital signature

Summary
within the UEFI executable and verifying that the digital signature is from an authorized source. The UEFI speciﬁ-
cation provides a standard format for executables. These executables may be located on un-secured media (such as
a hard drive or unprotected ﬂash device) or may be delivered via a un-secured transport layer (such as a network) or
originate from a un-secured port (such as ExpressCard device or USB device). In each of these cases, the system
provider may decide to authenticate either the origin of the executable or its integrity (i.e., it has not been tampered
with). This section describes a means of doing so.
32.2.1 Digital Signatures
As a rule, digital signatures require two pieces: the data (often referred to as the message) and a public/private key
pair. In order to create a digital signature, the message is processed by a hashing algorithm to create a hash value. This
hash value is, in turn, encrypted using a signature algorithm and the private key to create the digital signature.
Fig. 32.1: Creating A Digital Signature
In order to verify a signature, two pieces of data are required: the original message and the public key. First, the hash
must be calculated exactly as it was calculated when the signature was created. Then the digital signature is decoded
using the public key and the result is compared against the computed hash. If the two are identical, then you can be
sure that message data is the one originally signed and it has not been tampered with.
32.2. UEFI Driver Signing Overview 1416Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 32.2: Veriying a Digital Signature
32.2. UEFI Driver Signing Overview 1417Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
32.2.2 Embedded Signatures
The signatures used for digital signing of UEFI executables are embedded directly within the executable itself. Within
the header is an array of directory entries. Each of these entries points to interesting places within the executable
image. The ﬁfth data directory entry contains a pointer to a list of certiﬁcates along with the length of the certiﬁcate
areas. Each certiﬁcate may contain a digital signature used for validating the driver. The following diagram illustrates
how certiﬁcates are embedded in the PE/COFF ﬁle:
Fig. 32.3: Embedded Digital Certiﬁcates
Within the PE/COFF optional header is a data directory. The 5th entry, if ﬁlled, points to a list of certiﬁcates. Normally,
these certiﬁcates are appended to the end of the ﬁle.
32.2.3 Creating Image Digests from Images
One of the pieces required for creating a digital signature is the image digest. For a detailed description on how
to create image digests from PE/COFF images, refer to the “Creating the PE Image Hash” section of the Microsoft
Authenticode Format speciﬁcation (see References).
32.2.4 Code Deﬁnitions
This section describes data structures used for signing UEFI executables.
32.2.4.1 WIN_CERTIFICATE
Summary
TheWIN_CERTIFICATE structure is part of the PE/COFF speciﬁcation.
Prototype
typedef struct _WIN_CERTIFICATE {
UINT32 dwLength;
UINT16 wRevision;
32.2. UEFI Driver Signing Overview 1418Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT16 wCertificateType;
//UINT8 bCertificate[ANYSIZE_ARRAY];
} WIN_CERTIFICATE;
dwLength The length of the entire certiﬁcate, including the length of the header, in bytes.
wRevision The revision level of the WIN_CERTIFICATE structure. The current revision level is 0x0200.
wCertiﬁcateType The certiﬁcate type. See WIN_CERT_TYPE_xxx for the UEFI certiﬁcate types. The UEFI speciﬁ-
cation reserves the range of certiﬁcate type values from 0x0EF0 to 0x0EFF.
bCertiﬁcate The actual certiﬁcate. The format of the certiﬁcate depends on wCertiﬁcateType . The format of the
UEFI certiﬁcates is deﬁned below.
#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002
#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0
#define WIN_CERT_TYPE_EFI_GUID 0x0EF1
This structure is the certiﬁcate header. There may be zero or more certiﬁcates.
• If the wCertiﬁcateType ﬁeld is set to WIN_CERT_TYPE_EFI_PKCS115, then the certiﬁcate follows the format
described in WIN_CERTIFICATE_EFI_PKCS1_15 .
• If the wCertiﬁcateType ﬁeld is set to WIN_CERT_TYPE_EFI_GUID, then the certiﬁcate follows the format
described in WIN_CERTIFICATE_UEFI_GUID .
• If the wCertiﬁcateType ﬁeld is set to WIN_CERT_TYPE_PKCS_SIGNED_DATA then the certiﬁcate is formatted
as described in the Authenticode speciﬁcation.
These certiﬁcates can be validated using the contents of the signature database described in Signature Database . The
following table illustrates the relationship between the certiﬁcates and the signature types in the database.
NOTE :In the case of a WIN_CERT_TYPE_PKCS_SIGNED_DATA ( orWIN_CERT_TYPE_EFI_GUID where
CertType = EFI_CERT_TYPE_PKCS7_GUID) certiﬁcate, a match can occur against an entry in the authorized sig-
nature database (or the forbidden signature database; UEFI Image Variable GUID & Variable Name )at any level of
the chain of X.509 certiﬁcates present in the certiﬁcate, and matches can occur against any of the applicable signature
types deﬁned in (Firmware/OS Key Exchange: Passing Public Keys .
Table 32.5: PE/COFF Certiﬁcates Types and UEFI Signature Database
Certiﬁcate Types
Image Certiﬁcate Type Veriﬁed Using Signature Database Type
WIN_CERT_TYPE_EFI_PKCS115
(Signature Size = 256 bytes)EFI_CERT_RSA2048_GUID (public key)
WIN_CERT_TYPE_EFI_GUID
(CertType = E
FI_CERT_TYPE_RSA2048_SHA256_GUID*)EFI_CERT_RSA2048_GUID (public key).
32.2. UEFI Driver Signing Overview 1419Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 32.5 – continued from previous page
(CertType = EFI_CERT_TYPE_PKCS7_GUID)*EFI_CERT_X509_GUID
EFI_CERT_RSA2048_GUID (when applicable)
EFI_CERT_X509_SHA256_GUID (when applicable)
EFI_CERT_X509_SHA384_GUID (when applicable)
EFI_CERT_X509_SHA512_GUID (when applicable)
WIN_CERT_TYPE_PKCS_SIGNED_DATA
EFI_CERT_X509_GUID
(Always applicable regardless of whether a certiﬁcate is
present or not) EFI_CERT_SHA1_GUID ,
EFI_CERT_SHA224_GUID ,
EFI_CERT_SHA256_GUID ,
EFI_CERT_SHA384_GUID ,
EFI_CERT_SHA512_GUID
In this case, the database contains the hash of the
image.
32.2.4.2 WIN_CERTIFICATE_EFI_PKCS1_15
Summary
Certiﬁcate which encapsulates the RSASSA_PKCS1-v1_5 digital signature.
Prototype
typedef struct _WIN_CERTIFICATE_EFI_PKCS1_15 {
WIN_CERTIFICATE Hdr;
EFI_GUID HashAlgorithm;
// UINT8 Signature[ANYSIZE_ARRAY];
} WIN_CERTIFICATE_EFI_PKCS1_15;
Hdr This is the standard WIN_CERTIFICATE header, where wCertiﬁcateType is set to
WIN_CERT_TYPE_EFI_PKCS1_15 .
HashAlgorithm This is the hashing algorithm which was performed on the UEFI executable when creating
the digital signature. It is one of the enumerated values pre-deﬁned in EFI Hash Algorithms . See
EFI_HASH_ALGORITHM_x .
Signature This is the actual digital signature. The size of the signature is the same size as the key (2048-bit key is
256 bytes) and can be determined by subtracting the length of the other parts of this header from the total length
of the certiﬁcate as found in Hdr.dwLength .
TheWIN_CERTIFICATE_UEFI_PKCS1_15 structure is derived from WIN_CERTIFICATE and encapsulates the in-
formation needed to implement the RSASSA-PKCS1-v1_5 digital signature algorithm as speciﬁed in RFC2437, sec-
tions 8-9.
32.2. UEFI Driver Signing Overview 1420Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
32.2.4.3 WIN_CERTIFICATE_UEFI_GUID
Summary
Certiﬁcate which encapsulates a GUID-speciﬁc digital signature.
Prototype
typedef struct _WIN_CERTIFICATE_UEFI_GUID {
EFI_GUID CertType;
UINT8 CertData[ANYSIZE_ARRAY];
} WIN_CERTIFICATE_UEFI_GUID;
WIN_CERT_TYPE_EFI_GUID .
CertType This is the unique id which determines the format of the CertData .
CertData This is the certiﬁcate data. The format of the data is determined by the CertType .
#define EFI_CERT_TYPE_RSA2048_SHA256_GUID
{0xa7717414, 0xc616, 0x4977, \
{0x94, 0x20, 0x84, 0x47, 0x12, 0xa7, 0x35, 0xbf}}
#define EFI_CERT_TYPE_PKCS7_GUID
{0x4aafd29d, 0x68df, 0x49ee, \
{0x8a, 0xa9, 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7}}
typedef struct _EFI_CERT_BLOCK_RSA_2048_SHA256 {
EFI_GUID HashType;
UINT8 PublicKey[256];
UINT8 Signature[256];
} EFI_CERT_BLOCK_RSA_2048_SHA256;
PublicKey The RSA exponent e for this structure is 0x10001.
Signature This signature block is PKCS 1 version 1.5 formatted.
The WIN_CERTIFICATE_UEFI_GUID certiﬁcate type allows new types of certiﬁcates to be developed for driver

authentication without requiring a new certiﬁcate type. The CertType deﬁnes the format of the CertData, which length
is deﬁned by the size of the certiﬁcate less the ﬁxed size of the WIN_CERTIFICATE_UEFI_GUID structure.
• If CertType isEFI_CERT_TYPE_RSA2048_SHA256_GUID then the structure which follows has the format
speciﬁed by EFI_CERT_BLOCK_RSA_2048_SHA256 .
• IfCertType isEFI_CERT_TYPE_PKCS7_GUID then the CertData component shall contain a DER-encoded
PKCS #7 version 1.5 [RFC2315] SignedData value.
32.2. UEFI Driver Signing Overview 1421Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
32.3 Firmware/OS Key Exchange: Creating Trust Relationships
This section describes a means of creating a trust relationship between the platform owner, the platform ﬁrmware,
and an operating system. This trust relationship enables the platform ﬁrmware and one or more operating systems to
exchange information in a secure manner. The trust relationship uses two types of asymmetric key pairs:
Platform Key (PK) The platform key establishes a trust relationship between the platform owner and the platform
ﬁrmware. The platform owner enrolls the public half of the key (PKpub) into the platform ﬁrmware. The
platform owner can later use the private half of the key (PKpriv) to change platform ownership or to enroll a
Key Exchange Key. See “Enrolling The Platform Key” and “Clearing The Platform Key” for more information.
Key Exchange Key (KEK) Key exchange keys establish a trust relationship between the operating system and the
platform ﬁrmware. Each operating system (and potentially, each 3rd party application which need to commu-
nicate with platform ﬁrmware) enrolls a public key (KEKpub) into the platform ﬁrmware. See “Enrolling Key
Exchange Keys” for more information.
While no Platform Key is enrolled, the SetupMode variable shall be equal to 1. While SetupMode == 1, the platform
ﬁrmware shall not require authentication in order to modify the Platform Key, Key Enrollment Key, OsRecoveryOrder,
OsRecovery####, and image security databases.
After the Platform Key is enrolled, the SetupMode variable shall be equal to 0. While SetupMode == 0, the platform
ﬁrmware shall require authentication in order to modify the Platform Key, Key Enrollment Key, OsRecoveryOrder,
While no Platform Key is enrolled, and while the variable AuditMode == 0, the platform is said to be operating in
setup mode.
After the Platform Key is enrolled, and while the variable AuditMode == 0, the platform is operating in user mode. The
platform will continue to operate in user mode until the Platform Key is cleared, or the system is transitioned to either
Audit or Deployed Modes. See “Clearing The Platform Key,” “Transitioning to Audit Mode,” and “Transitioning to
Deployed Mode” for more information.
Audit Mode enables programmatic discovery of signature list combinations that successfully authenticate installed
EFI images without the risk of rendering a system unbootable. Chosen signature lists conﬁgurations can be tested to
ensure the system will continue to boot after the system is transitioned out of Audit Mode. Details on how to transition
to Audit Mode are detailed below in the section “Transitioning to Audit Mode.” After transitioning to Audit Mode,
signature enforcement is disabled such that all images are initialized and enhanced Image Execution Information Table
(IEIT) logging is performed including recursive validation for multi-signed images.
Deployed Mode is the most secure mode. For details on transitioning to Deployed Mode see the section “Transitioning
to Deployed Mode” below. By design, both User Mode and Audit Mode support unauthenticated transitions to De-
ployed Mode. However, to move from Deployed Mode to any other mode requires a secure platform-speciﬁc method,
or deleting the PK, which is authenticated.
Secure Boot Mode transitions to User Mode or Deployed Mode shall take effect immediately. Mode transitions to
Setup Mode or Audit Mode may either take effect immediately (recommended) or after a reset. For implementations
that require a reset, the mode transition shall be processed prior to the initialization of the SecureBoot variable, and
the SetVariable() workﬂow shall be as follows:
1. If the variable has an authenticated attribute, it shall be authenticated as speciﬁed, and failure will result in
immediate termination of this workﬂow by returning the appropriate error.
2. Check secure storage to determine if a Secure Boot Mode transition is already queued. If a transition is already
queued, terminate this workﬂow by returning EFI_ALREADY_STARTED
3. Queue the request to secure storage
4. The Secure Boot Mode and Policy variables SHALL remain unchanged
5. Return EFI_WARN_RESET_REQUIRED.
32.3. Firmware/OS Key Exchange: Creating Trust Relationships 1422Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
6. After reboot, if the transition is successful, Secure Boot Mode and Policy variables will change accordingly. If
the transition to lower security modes is rejected or fail, the workﬂow is terminated and the Secure Boot Mode
and Policy variables remain unchanged
Fig. 32.4: Secure Boot Modes
32.3.1 Enrolling The Platform Key
The platform owner enrolls the public half of the Platform Key (PKpub) by calling the UEFI Boot Service SetVariable()
as speciﬁed in Using the EFI_VARIABLE_AUTHENTICATION_3 descriptor . If the platform is in setup mode, then
the new PKpub may be signed with its PKpriv counterpart. If the platform is in user mode, then the new PKpub must
be signed with the current PKpriv. When the platform is in setup mode, a successful enrollment of a Platform Key
shall cause the platform to immediately transition to user mode.
The authenticated PK variable can always be read but can only be written if the platform is in setup mode, or if the
platform is in user mode and the provided PKpub is signed with the current PKpriv.
The name and GUID of the Platform Key variable are speciﬁed in Globally Deﬁned Variables “Globally Deﬁned
Variables” The variable has the format of a signature database as described in “Signature Database” below, with
exactly one entry.
The platform vendor may provide a default PKpub in the PKDefault variable described in Globally Deﬁned Variables .
32.3. Firmware/OS Key Exchange: Creating Trust Relationships 1423Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This variable is formatted identically to the Platform Key variable. If present, this key may optionally be used as the
public half of the Platform Key when transitioning from setup mode to user mode. If so, it may be read, placed within
anEFI_VARIABLE_AUTHENTICATION2 structure and copied to the Platform Key variable using the SetVariable()
call.
32.3.2 Clearing The Platform Key
The platform owner clears the public half of the Platform Key (PKpub) by deleting the Platform Key variable using
UEFI Runtime Service SetVariable() . The data buffer submitted to the SetVariable() must be signed with the current
PKpriv; Exception for Machine Check, INIT, and NMI for details. The name and GUID of the Platform Key variable
are speciﬁed in Globally Deﬁned Variables , “Globally Deﬁned Variables” The platform key may also be cleared using
a secure platform-speciﬁc method. When platform key is cleared, the global variable SetupMode must also be updated
to 1.
32.3.3 Transitioning to Audit Mode
To enter Audit Mode, a new UEFI variable AuditMode is set to 1. Entering Audit Mode has the side effect of changing
SetupMode == 1, PK is cleared, and the new DeployedMode == 0.
NOTE :The AuditMode variable is only writable before ExitBootServices() is called when the system is notin De-
ployed Mode . See Secure Boot Modes for more details.
32.3.4 Transitioning to Deployed Mode
To enter Deployed Mode from Audit Mode, set the variable PK. To enter Deployed Mode from User Mode, set the
variable DeployedMode to 1. This transition takes effect immediately with no reset required. Entering Deployed Mode
has the side effect of changing SetupMode == 0, AuditMode == 0 and is made read-only, and DeployedMode == 1
and is made read-only. See Secure Boot Modes for more details.
32.3.5 Enrolling Key Exchange Keys
Key exchange keys are stored in a signature database as described in “Signature Database” below. The signature
database is stored as an authenticated UEFI variable.
The platform owner enrolls the key exchange keys by either calling SetVariable() as speciﬁed in Using the
EFI_VARIABLE_AUTHENTICATION_3 descriptor with the EFI_VARIABLE_APPEND_WRITE attribute set and the
Data parameter containing the new key(s), or by reading the database using GetVariable(), appending the new
key exchange key to the existing keys and then writing the database using SetVariable() as speciﬁed in Using the
EFI_VARIABLE_AUTHENTICATION_3 descriptor without the EFI_VARIABLE_APPEND_WRITE attribute set.

The authenticated UEFI variable that stores the key exchange keys (KEKs) can always be read but only be written if:
• The platform is in user mode and the provided variable data is signed with the current PK priv;orif
• The platform is in setup mode (in this case the variable can be written without a signature validation, but the
SetVariable() call needs to be formatted in accordance with the procedure for authenticated variables in Using
the EFI_VARIABLE_AUTHENTICATION_3 descriptor )
The name and GUID of the Key Exchange Key variable are speciﬁed in Globally Deﬁned Variables , “Globally Deﬁned
Variables.” The platform vendor may provide a default set of Key Exchange Keys in the KEKDefault variable described
inGlobally Deﬁned Variables . If present, these keys (or a subset) may optionally be used when performing the initial
enrollment of Key Exchange Keys. If any are to be used, they may be parsed from the variable and enrolled as
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32.3.6 Platform Firmware Key Storage Requirements
This section describes the platform ﬁrmware storage requirements of the different types of keys.
Platform Keys: The public key must be stored in non-volatile storage which is tamper and delete resistant.
Key Exchange Keys: The public key must be stored in non-volatile storage which is tamper resistant. Careful consid-
eration should be given to the security and conﬁguration of any out-of-band management agent (e.g. hypervisor
or service processor) such that the platform cannot exploit the management agent in order to circumvent Secure
Boot.
32.4 Firmware/OS Key Exchange: Passing Public Keys
This section describes a means of passing public keys from the OS to the platform ﬁrmware so that these keys can
be used to securely pass information between the OS and the platform ﬁrmware. Typically, the OS has been unable
to communicate sensitive information or enforce any sort of policy because of the possibility of spooﬁng by a mali-
cious software agent. That is, the platform ﬁrmware has been unable to trust the OS. By enrolling these public keys,
authorized by the platform owner, the platform ﬁrmware can now check the signature of data passed by the operating
system. Of course if the malicious software agent is running as part of the OS, such as a rootkit, then any communica-
tion between the ﬁrmware and operating system still remains the subject of spooﬁng as the malicious code has access
to the key exchange key.
32.4.1 Signature Database
32.4.1.1 EFI_SIGNATURE_DATA
Summary
The format of a signature database.
Prototype
typedef struct _EFI_SIGNATURE_DATA {
EFI_GUID SignatureOwner;
UINT8 SignatureData [_];
} EFI_SIGNATURE_DATA;
typedef struct _EFI_SIGNATURE_LIST {
EFI_GUID SignatureType;
UINT32 SignatureListSize;
UINT32 SignatureHeaderSize;
UINT32 SignatureSize;
// UINT8 SignatureHeader [SignatureHeaderSize];
// EFI_SIGNATURE_DATA Signatures [__][SignatureSize];
} EFI_SIGNATURE_LIST;
Members
SignatureListSize Total size of the signature list, including this header.
SignatureType Type of the signature. GUID signature types are deﬁned in “Related Deﬁnitions” below.
SignatureHeaderSize Size of the signature header which precedes the array of signatures.
SignatureSize Size of each signature. Must be at least the size of EFI_SIGNATURE_DATA .
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SignatureHeader Header before the array of signatures. The format of this header is speciﬁed by the SignatureType .
Signatures An array of signatures. Each signature is SignatureSize bytes in length. The format of the signature is
deﬁned by the SignatureType .
SignatureOwner An identiﬁer which identiﬁes the agent which added the signature to the list.
The signature database consists of zero or more signature lists. The size of the signature database can be determined
by examining the size of the UEFI variable.
Each signature list is a list of signatures of one type, identiﬁed by SignatureType . The signature list contains a header
and then an array of zero or more signatures in the format speciﬁed by the header. The size of each signature in the
signature list is speciﬁed by SignatureSize .
Each signature has an owner SignatureOwner, which is a GUID identifying the agent which inserted the signature
in the database. Agents might include the operating system or an OEM-supplied driver or application. Agents may
examine this ﬁeld to understand whether they should manage the signature or not.
Fig. 32.5: Signature Lists
#define EFI_CERT_SHA256_GUID \
{ 0xc1c41626, 0x504c, 0x4092, \
{ 0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28 } };
This identiﬁes a signature containing a SHA-256 hash. The SignatureHeader size shall always be 0. The SignatureSize
shall always be 16 (size of SignatureOwner component) + 32 bytes.
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#define EFI_CERT_RSA2048_GUID \
{ 0x3c5766e8, 0x269c, 0x4e34, \
{ 0xaa, 0x14, 0xed, 0x77, 0x6e, 0x85, 0xb3, 0xb6 } };
This identiﬁes a signature containing an RSA-2048 key. The key (only the modulus since the public key exponent is
known to be 0x10001) shall be stored in big-endian order.
TheSignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of SignatureOwner compo-
nent) + 256 bytes.
#define EFI_CERT_RSA2048_SHA256_GUID \
{ 0xe2b36190, 0x879b, 0x4a3d, \
{ 0xad, 0x8d, 0xf2, 0xe7, 0xbb, 0xa3, 0x27, 0x84 } };
This identiﬁes a signature containing a RSA-2048 signature of a SHA-256 hash. The SignatureHeader size shall
always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) + 256 bytes.
#define EFI_CERT_SHA1_GUID \
{ 0x826ca512, 0xcf10, 0x4ac9, \
{ 0xb1, 0x87, 0xbe, 0x01, 0x49, 0x66, 0x31, 0xbd } };
This identiﬁes a signature containing a SHA-1 hash. The SignatureSize shall always be 16 (size of SignatureOwner
component) + 20 bytes.
#define EFI_CERT_RSA2048_SHA1_GUID \
{ 0x67f8444f, 0x8743, 0x48f1, \
{ 0xa3, 0x28, 0x1e, 0xaa, 0xb8, 0x73, 0x60, 0x80 } };
This identiﬁes a signature containing a RSA-2048 signature of a SHA-1 hash. The SignatureHeader size shall always
be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) + 256 bytes.
#define *EFI_CERT_X509_GUID *\
{ 0xa5c059a1, 0x94e4, 0x4aa7, \
{ 0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72 } };
This identiﬁes a signature based on a DER-encoded X.509 certiﬁcate. If the signature is an X.509 certiﬁcate then
veriﬁcation of the signature of an image should validate the public key certiﬁcate in the image using certiﬁcate path
veriﬁcation, up to this X.509 certiﬁcate as a trusted root. If the signature is in a device signature variable, this signature
is one root certiﬁcate authority (CA) certiﬁcate or an intermediate certiﬁcate for the device. The SignatureHeader size
shall always be 0. The SignatureSize may vary but shall always be 16 (size of the SignatureOwner component) + the
size of the certiﬁcate itself.
NOTE :This means that each certiﬁcate will normally be in a separate EFI_SIGNATURE_LIST.
#define EFI_CERT_SHA224_GUID \
{ 0xb6e5233, 0xa65c, 0x44c9, \
{0x94, 0x07, 0xd9, 0xab, 0x83, 0xbf, 0xc8, 0xbd} };
This identiﬁes a signature containing a SHA-224 hash. The SignatureHeader size shall always be 0. The SignatureSize
shall always be 16 (size of SignatureOwner component) + 28 bytes.
#define EFI_CERT_SHA384_GUID \
{ 0xff3e5307, 0x9fd0, 0x48c9, \
{0x85, 0xf1, 0x8a, 0xd5, 0x6c, 0x70, 0x1e, 0x01}};
This identiﬁes a signature containing a SHA-384 hash. The SignatureHeader size shall always be 0. The SignatureSize
shall always be 16 (size of SignatureOwner component) + 48 bytes.
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#define EFI_CERT_SHA512_GUID \
{ 0x93e0fae, 0xa6c4, 0x4f50, \
{0x9f, 0x1b, 0xd4, 0x1e, 0x2b, 0x89, 0xc1, 0x9a}}
This identiﬁes a signature containing a SHA-512 hash. The SignatureHeader size shall always be 0. The SignatureSize
shall always be 16 (size of SignatureOwner component) + 64 bytes.
#define EFI_CERT_X509_SHA256_GUID \
{ 0x3bd2a492, 0x96c0, 0x4079, \
{ 0xb4, 0x20, 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed } };
Prototype
typedef struct _EFI_CERT_X509_SHA256 {
EFI_SHA256_HASH ToBeSignedHash;
EFI_TIME TimeOfRevocation;
} EFI_CERT_X509_SHA256;
Members
ToBeSignedHash The SHA256 hash of an X.509 certiﬁcate’s To-Be-Signed contents.
TimeOfRevocation The time that the certiﬁcate shall be considered to be revoked.
This identiﬁes a signature containing the SHA256 hash of an X.509 certiﬁcate’s To-Be-Signed contents, and a
time of revocation. If the signature is in a device signature variable, this signature is a SHA256 hash of a root

Prototype
Members
certiﬁcate authority (CA) certiﬁcate or an intermediate certiﬁcate for the device. The SignatureHeader size shall
always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component) + 48 bytes for an
EFI_CERT_X509_SHA256 structure. If the TimeOfRevocation is non-zero, the certiﬁcate should be considered
to be revoked from that time and onwards, and otherwise the certiﬁcate shall be considered to always be revoked.
#define EFI_CERT_X509_SHA384_GUID \
{ 0x7076876e, 0x80c2, 0x4ee6, \
{ 0xaa, 0xd2, 0x28, 0xb3, 0x49, 0xa6, 0x86, 0x5b } };
Prototype
typedef struct _EFI_CERT_X509_SHA384 {
EFI_SHA384_HASH ToBeSignedHash;
} EFI_CERT_X509_SHA384;
Members
ToBeSignedHash The SHA384 hash of an X.509 certiﬁcate’s To-Be-Signed contents.
This identiﬁes a signature containing the SHA384 hash of an X.509 certiﬁcate’s To-Be-Signed contents, and a time
of revocation. If the signature is in a device signature variable, this signature is a SHA384 hash of a root certiﬁcate
authority (CA) certiﬁcate or an intermediate certiﬁcate for the device. The SignatureHeader size shall always be 0. The
SignatureSize shall always be 16 (size of the SignatureOwner component) + 64 bytes for an EFI_CERT_X509_SHA384
structure. If the TimeOfRevocation is non-zero, the certiﬁcate should be considered to be revoked from that time and
onwards, and otherwise the certiﬁcate shall be considered to always be revoked.
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#define EFI_CERT_X509_SHA512_GUID \
{ 0x446dbf63, 0x2502, 0x4cda, \
{ 0xbc, 0xfa, 0x24, 0x65, 0xd2, 0xb0, 0xfe, 0x9d } };
Prototype
typedef struct _EFI_CERT_X509_SHA512 {
EFI_SHA512_HASH ToBeSignedHash;
} EFI_CERT_X509_SHA512;
Members
ToBeSignedHash The SHA512 hash of an X.509 certiﬁcate’s To-Be-Signed contents.
This identiﬁes a signature containing the SHA512 hash of an X.509 certiﬁcate’s To-Be-Signed contents, and a time
of revocation. If the signature is in a device signature variable, this signature is a SHA512 hash of a root certiﬁcate
SignatureSize shall always be 16 (size of the SignatureOwner component) + 80 bytes for an EFI_CERT_X509_SHA512
#define EFI_CERT_EXTERNAL_MANAGEMENT_GUID \
{ 0x452e8ced, 0xdfff, 0x4b8c, \
{ 0xae, 0x01, 0x51, 0x18, 0x86, 0x2e, 0x68, 0x2c } };
This SignatureType describes a pseudo-signature which will not facilitate authentication. It is only meaningful within
a signature list used for authenticating writes through SetVariable(), and is only effective if it is the only signature
present in that signature list. It allows a signature list to be populated without providing any means for SetVariable()
to succeed. This signature type is intended for use on a platform with an external out-of-band management agent (e.g.
hypervisor or service processor). When a platform is conﬁgured such that only signatures of this SignatureType are
available for authenticating writes to a variable, that variable may only be modiﬁed by the external management agent
using a platform-speciﬁc interface.
When a write may be authenticated using any signature from multiple signature lists, the presence of this signature in
one of those signature lists does not inhibit the use of signatures present in the other signature lists. For example, if
this signature is placed in PK, an attempt to write to db using SetVariable() will still succeed if it is signed by a valid
KEKpriv, but a write to PK or KEK through SetVariable() cannot succeed because no PKpriv exists.
nent) + 1 byte. The one byte of SignatureData exists only for compatibility reasons; It should be written as zero, and
any value read should be ignored.
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32.4.2 Image Execution Information Table
Summary
When AuditMode==0, if the image’s signature is not found in the authorized database, or is found in the
forbidden database, the image will not be started and instead, information about it will be placed in the
EFI_IMAGE_EXECUTION_INFO_TABLE (see section 32.5.3.1). {cross-reference needed}
When AuditMode==1, an EFI_IMAGE_EXECUTION_INFO element is created in the
EFI_IMAGE_EXECUTION_INFO_TABLE for every certiﬁcate found in the certiﬁcate table of every image
that is validated.
Additionally for every image, an element will be created in the table for every EFI_CERT_SHAXXX that is
supported by the platform. The contents of* Action for each element are determined by comparing that spe-
ciﬁc element’s Signature (which will contain exactly 1 EFI_SIGNATURE_DATA ) to the currently-conﬁgured
image security databases and policies, and shall be either EFI_IMAGE_EXECUTION_AUTH_SIG_PASSED ,
EFI_IMAGE_EXECUTION_AUTH_SIG_FAILED , EFI_IMAGE_EXECUTION_AUTH_SIG_NOT_FOUND ,
EFI_IMAGE_EXECUTION_AUTH_SIG_FOUND , orEFI_IMAGE_EXECUTION_POLICY_FAILED .
Finally, because the system is in Audit Mode, all modules are initialized even if they fail to authenticate, and the
EFI_IMAGE_EXECUTION_INITIALIZED bit shall be set in Action for all elements.
Prototype
EFI_IMAGE_EXECUTION_ACTION Action;
// CHAR16 Name [__];
// EFI_DEVICE_PATH_PROTOCOL DevicePath;
// EFI_SIGNATURE_LIST Signature;
} EFI_IMAGE_EXECUTION_INFO;
Action Describes the action taken by the ﬁrmware regarding this image. Type EFI_IMAGE_EXECUTION_ACTION
is described in “Related Deﬁnitions” below.
InfoSize Size of all of the entire structure.
Name If this image was a UEFI device driver (for option ROM, for example) this is the null-terminated, user-friendly
name for the device. If the image was for an application, then this is the name of the application. If this cannot
be determined, then a simple NULL character should be put in this position.
DevicePath Image device path. The image device path typically comes from the Loaded Image Device Path Protocol
installed on the image handle. If image device path cannot be determined, a simple end-of-path device node
should be put in this position.
Signature Zero or more image signatures. If the image contained no signatures, then this ﬁeld is empty.The type
WIN_CERTIFICATE is deﬁned in chapter 26.
Prototype
UINTN NumberOfImages;
EFI_IMAGE_EXECUTION_INFO InformationInfo[__]
} EFI_IMAGE_EXECUTION_INFO_TABLE;
NumberOfImages Number of EFI_IMAGE_EXECUTION_INFO structures.
InformationInfo NumberOfImages instances of EFI_IMAGE_EXECUTION_INFO structures.
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typedef UINT32 EFI_IMAGE_EXECUTION_ACTION;
#define EFI_IMAGE_EXECUTION_AUTHENTICATION 0x00000007
#define EFI_IMAGE_EXECUTION_AUTH_UNTESTED 0x00000000
#define EFI_IMAGE_EXECUTION_AUTH_SIG_FAILED 0x00000001
#define EFI_IMAGE_EXECUTION_AUTH_SIG_PASSED 0x00000002
#define EFI_IMAGE_EXECUTION_AUTH_SIG_NOT_FOUND 0x00000003
#define EFI_IMAGE_EXECUTION_AUTH_SIG_FOUND 0x00000004
#define EFI_IMAGE_EXECUTION_POLICY_FAILED 0x00000005
#define EFI_IMAGE_EXECUTION_INITIALIZED 0x00000008
This structure describes an image in the EFI System Conﬁguration Table. It is only required in the case where image
signatures are being checked and the image was not initialized because its signature failed, when AuditMode==1, or
was not found in the signature database andan authorized user or the owner would not authorize its execution. It may
be used in other cases as well.
In these cases, the information about the image is copied into the EFI System Conﬁguration Table. Information about
other images which were successfully initialized may also be included as well, but this is not required.
TheAction ﬁeld describes what action the ﬁrmware took with regard to the image and what other information it has
about the image, including the device which it is related to.
First, this ﬁeld describes the results of the ﬁrmware’s attempt to authenticate the image.
Table 32.6: Authentication Attempt Status Codes
Authentication attempt status Condition met
EFI_IMAGE_EXECUTION_AUTH_UNTESTED The image contained no certiﬁcates
EFI_IMAGE_EXECUTION_AUTH_SIG_FAILED
The image has at least one certiﬁcate, and either:
• An image certiﬁcate is in the forbidden
database, or

• A digest of an image certifcate is in the for-
bidden database, or
• The image signature check failed.
EFI_IMAGE_EXECUTION_AUTH_SIG_PASSED
• An image certifcate is in authroized
database.
• The image digest is in the authorized
database.
EFI_IMAGE_EXECUTION_AUTH_SIG_NOT_FOUND
The image has at least one certifcate, and:
• the image certiﬁcate is not found in the au-
thorized database, and
• the image digest is not in the authorized
database.
EFI_IMAGE_EXECUTION_AUTH_SIG_FOUND The image has at least one certiﬁcate, and the image
digest is in the forbidden database.
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Table 32.6 – continued from previous page
EFI_IMAGE_EXECUTION_POLICY_FAILED Authentication failed because of (unspeciﬁed) ﬁrmware
security policy.
Second, this ﬁeld describes whether the image was initialized or not.
This table can be used by an agent which executes later to audit which images were not loaded and perhaps query
other sources to discover whether the image should be authorized. If so, the agent can use the method described in
“Signature Database Update” to update the Signature Database with the image’s signature. Switching the system into
Audit Mode generates a more verbose table which provides additional insights to this agent.
If an attempt to boot a legacy non-UEFI OS takes place when the system is in User Mode, the OS load
shall fail and a corresponding EFI_IMAGE_EXECUTION_INFO entry shall be created with Action set to
EFI_IMAGE_EXECUTION_AUTH_UNTESTED, Name set to the NULL-terminated “Description String” from the
BIOS Boot Speciﬁcation Device Path and DevicePath set to the BIOS Boot Speciﬁcation Device Path ( BIOS Boot
Speciﬁcation Device Path ).
32.5 Firmware/OS Crypto Algorithm Exchange
The ﬁrmware and an Operating System may exchange information through the CryptoIndicationsSupported, Cryp-
toIndicationsActivated and the CryptoIndications variables as follows:
• The CryptoIndications variable returns an EFI_CRYPTO_INDICATION structure owned by the OS and is used
to indicate which crypto algorithms the OS wants ﬁrmware to activate. The algorithm bitmap in CryptoIndica-
tions must be a subset of the algorithm bitmap in the CryptoIndicationsSupported variable. The OS will supply
this data with a SetVariable()call. The OS should set one bit. If the OS sets more than one bit, then the ﬁrmware
shall support all those algorithms. Because this variable can be written by any entity, the ﬁrmware shall validate
the data before use it. For example, any bits beyond the supported bitmask shall be treated as illegal. The
ﬁrmware may also combine other validation before accepting the new conﬁguration, such as physical present
user action, etc. If error is detected, the ﬁrmware may choose to notify end user, ignore this request, or reset to
manufacture state, etc. The detailed validation process or error remediation is out of scope of this speciﬁcation.
• The CryptoIndicationsSupported variable returns an EFI_CRYPTO_INDICATION structure owned by the
ﬁrmware and indicates which crypto algorithms are supported by the ﬁrmware supports. This variable is recre-
ated by ﬁrmware every boot and cannot be modiﬁed by the OS.
• The CryptoIndicationsActivated variable returns an EFI_CRYPTO_INDICATION structure owned by the
ﬁrmware and indicates which crypto algorithms are supported by the ﬁrmware activates. The algorithm bitmap
in CryptoIndicationsActivated must be a subset of the algorithm bitmap in the CryptoIndicationsSupported vari-
able. This variable is recreated by ﬁrmware every boot and cannot be modiﬁed by the OS.
UINT64 HashAlgorithmBitmap;
UINT64 AsymAlgorithmBitmap;
} EFI_CRYPTO_INDICATION;
#define EFI_CRYPTO_INDICATION_VERSION_1 0x00000001
#define EFI_CRYPTO_INDICATION_HASH_SHA_256 0x1
#define EFI_CRYPTO_INDICATION_HASH_SHA_384 0x2
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#define EFI_CRYPTO_INDICATION_ASYM_RSASSA_2048 0x1
#define EFI_CRYPTO_INDICATION_ASYM_RSASSA_3072 0x2
#define EFI_CRYPTO_INDICATION_ASYM_RSAPSS_3072 0x10
#define EFI_CRYPTO_INDICATION_ASYM_ECDSA_ECC_NIST_P256 0x40
#define EFI_CRYPTO_INDICATION_ASYM_ECDSA_ECC_NIST_P384 0x80
#define EFI_CRYPTO_INDICATION_ASYM_RSASSA_4096 0x4
#define EFI_CRYPTO_INDICATION_ASYM_RSAPSS_4096 0x20
The EFI_CRYPTO_INDICATION_HASH_SHA_256 bit means SHA-256 hash algorithm.
The EFI_CRYPTO_INDICATION_HASH_SHA_384 bit means SHA-384 hash algorithm.
The EFI_CRYPTO_INDICATION_ASYM_RSASSA_2048 bit means a signature algorithm defined in
˓→section 8.2 (RSASSAPKCS1-v1_5) inRFC8017. The key size is2048 bits.
The EFI_CRYPTO_INDICATION_ASYM_RSASSA_3072 bit means a signature algorithm defined in
˓→section 8.2 (RSASSAPKCS1-v1_5) inRFC8017. The key size is3072 bits.
The EFI_CRYPTO_INDICATION_ASYM_RSAPSS_3072 bit means a signature algorithm defined in
˓→section 8.1 (RSASSAPSS) inRFC8017. The key size is3072 bits.
The EFI_CRYPTO_INDICATION_ASYM_ECDSA_ECC_NIST_P256 bit means a signature algorithm
˓→defined insection 6 (ECDSA) inFIPS 186-4. The key size is256 bits.
The EFI_CRYPTO_INDICATION_ASYM_ECDSA_ECC_NIST_P384 bit means a signature algorithm
˓→defined insection 6 (ECDSA) inFIPS 186-4. The key size is384 bits.
Note: The platform ﬁrmware shall balance the security and compatibility. Supporting old algorithm such as
EFI_CRYPTO_INDICATION_HASH_SHA_256 and/or EFI_CRYPTO_INDICATION_ASYM_RSASSA_2048 in
CryptoIndicationsSupported variable may cause insecure conﬁguration or potential downgrade attack. These algo-
rithms should only be used for compatibility consideration. A secure conﬁguration should not use any deprecated
algorithms.
32.6 UEFI Image Validation
32.6.1 Overview
This section describes a way to use the platform ownership model described in the previous section and the key
exchange mechanism to allow the ﬁrmware to authenticate a UEFI image, such as an OS loader or an option ROM,
using the digital signing mechanisms described here.
The hand-off between the platform ﬁrmware and the operating system is a critical part of ensuring secure boot. Since
there are large numbers of operating systems and a large number of minor variations in the loaders for those operating
systems, it is difﬁcult to carry all possible keys or signatures within the ﬁrmware as it ships. This requires some sort
of update mechanism, to identify the proper loader. But, as with any update mechanism, there is the risk of allowing
malicious software to “authenticate” itself, posing as the real operating system.
Likewise, there are a large number of potential 3rd-party UEFI applications, drivers and option ROMs and it is difﬁcult
to carry all possible keys or signatures within the ﬁrmware as it ships.
The mechanism described here requires that the platform ﬁrmware maintain a signature database, with entries for each
authorized UEFI image (the authorized UEFI signature database). The signature database is a single UEFI Variable.
It also requires that the platform ﬁrmware maintain a signature database with entries for each forbidden UEFI image.
This signature database is also a single UEFI variable.
32.6. UEFI Image Validation 1433Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The signature database is checked when the UEFI Boot Manager is about to start a UEFI image. If the UEFI image’s
signature is not found in the authorized database, or is found in the forbidden database, the UEFI image will be
deferred and information placed in the Image Execution Information Table. In the case of OS Loaders, the next boot
option will be selected. The signature databases may be updated by the ﬁrmware, by a pre-OS application or by an OS
application or driver.
If a ﬁrmware supports the EFI_CERT_X509_SHA*_GUID signature types, it should support the RFC3161 timestamp
speciﬁcation. Images whose signature matches one of these types in the forbidden signature database shall only be
considered forbidden if the ﬁrmware either does not support timestamp veriﬁcation, or the signature type has a time of
revocation equal to zero, or the timestamp does not pass veriﬁcation against the authorized timestamp and forbidden
signature databases, or ﬁnally the signature type’s time of revocation is less than or equal to the time recorded in the
image signature’s timestamp. If the timestamp’s signature is authorized by the authorized timestamp database and
the time recorded in the timestamp is less than the time of revocation, the image shall not be considered forbidden
provided it is not forbidden by any other entry in the forbidden signature database. Finally, this requires that ﬁrmware
supporting timestamp veriﬁcation must support the authorized timestamp database and have a suitable time stamping

authority certiﬁcate in that database.
32.6.2 Authorized User
Anauthorized user (for the purposes of UEFI image security) is one who possesses a key exchange key (KEKpriv).
This key is used to sign updates to the signature databases.
32.6.3 Signature Database Update
The Authorized, Forbidden, Timestamp, and Recovery signature databases are stored as UEFI authenticated variables
(see Variable Services in Exception for Machine Check, INIT, and NMI ) with the GUID
EFI_IMAGE_SECURITY_DATABASE_GUID and the names
EFI_IMAGE_SECURITY_DATABASE,
EFI_IMAGE_SECURITY_DATABASE1,
EFI_IMAGE_SECURITY_DATABASE2, and
EFI_IMAGE_SECURITY_DATABASE3, respectively.
These authenticated UEFI variables that store the signature databases (db, dbx, dbr, or dbt) can always be read but can
only be written if:
• The platform is in user mode and the provided variable data is signed with the private half of a previously
enrolled key exchange key (KEKpriv *), or the platform private key (PK priv);
or if
• The platform is in setup mode (in this case the variables can be written without a signature validation, but the
The signature databases are in the form of Signature Databases, as described in “Signature Database” above.
The platform vendor may provide a default set of entries for the Signature Database in the dbDefault, dbxDefault,
dbtDefault, and dbrDefault variables described in Globally Deﬁned Variables . If present, these keys (or a subset) may
optionally be used when performing the initial enrollment of signature database entries. If any are to be used, they
may be parsed from the variable and enrolled as described below.
32.6. UEFI Image Validation 1434Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If, when adding a signature to the signature database, SetVariable() returns EFI_OUT_OF_RESOURCES, indicating
there is no more room, the updater may discard the new signature or it may decide to discard one of the database
entries. These authenticated UEFI variables that store the signature databases (db, or dbx, dbt, or dbr) can always be
read but can only be written if:
The following diagram illustrates the process for adding a new signature by the OS or an application that has access to
a previously enrolled key exchange key using SetVariable() . In the diagram, the EFI_VARIABLE_APPEND_WRITE
attribute is not used. If EFI_VARIABLE_APPEND_WRITE had been used, then steps 2 and 3 could have been omitted
and step 7 would have included setting the EFI_VARIABLE_APPEND_WRITE attribute.
1. The procedure begins by generating a new signature, in the format described by the Signature Database.
2. Call GetVariable() using EFI_IMAGE_SECURITY_DATABASE_GUID for the*VendorGuid* parameter and
EFI_IMAGE_SECURITY_DATABASE for the VariableName parameter.
3. If the variable exists, go to step 5.
4. Create an empty authorized signature database.
5. Create a new buffer which contains the authorized signature database, along with the new signature appended
to the end.
6. Sign the new signature database using the private half of the Key Exchange Key as described in SetVariable() .
7. Update the authorized signature database using the UEFI Runtime Service SetVariable() .
8. If there was no error, go to step 11.
9. If there was an error because of no more resources, determine whether the database can be shrunk any more.
The algorithm by which an agent decides which signatures may be safely removed is agent-speciﬁc. In most
cases, agents should not remove signatures where the SignatureOwner ﬁeld is not the agent’s. If not, then go to
step 11, discarding the new signature.
10. If the signature database could be shrunk further, then remove the entries and go to step 6.
11. Exit.
32.6.3.1 Using The Image Execution Information Table
During the process of loading UEFI images, the ﬁrmware must gather information about which UEFI images were not
started. The ﬁrmware may additionally gather information about UEFI images which were started. The information
is used to create the IEFI_IMAGE_EXECUTION_INFO_TABLE, which is added to the EFI System Conﬁguration
Table and assigned the GUID EFI_IMAGE_SECURITY_DATABASE_GUID.
For each UEFI image, the following information is collected:
• The image hash.
• The user-friendly name of the UEFI image (if known)
• The device path
• The action taken on the device (was it initialized or why was it rejected).
For more information, see the Image Execution Information Table deﬁnition above ( Image Execution Information
Table ).
32.6. UEFI Image Validation 1435Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 32.6: Process for Adding a New Signature by the OS
32.6. UEFI Image Validation 1436Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
32.6.3.2 Firmware Policy
The ﬁrmware may approve UEFI images for other reasons than those speciﬁed here. For example: whether the image
is in the system ﬂash, whether the device providing the UEFI image is secured (in a case, etc.) or whether the image
contains another type of platform-supported digital signature.
32.6.3.3 Authorization Process
This section describes the process by which an unknown UEFI image might be authorized to run. Implementations
are not required to support all portions of this. For example, an implementation might defer all UEFI image or none.
1. Reset. This is when the platform begins initialization during boot.
2. Key Store Initialization. During the ﬁrmware initialization and before any signed UEFI images are initialized,
the platform ﬁrmware must validate the signature database.
3. UEFI Image Validation Succeeded? During initialization of an UEFI image, the UEFI Boot Manager decides
whether or not the UEFI image should be initialized. By comparing the calculated UEFI image signature against
that in one of the signature databases, the ﬁrmware can determine if there is a match.
The security database dbmust either contain an entry with a hash value of the image (with a supported hash type), or it
must contain an entry with a certiﬁcate against which an entry in the image’s certiﬁcate table can be veriﬁed. In either
case veriﬁcation must not succeed if the security database dbx contains any record with:
– A. Any entry with SignatureListType ofEFI_CERT_SHA256_GUID with any SignatureData containing the SHA-
256 hash of the binary.
– B. Any entry with SignatureListType ofEFI_CERT_X509_SHA256, EFI_CERT_X509_SHA384, or
EFI_CERT_X509_SHA512, with any SignatureData which reﬂects the To-Be-Signed hash included in any cer-
tiﬁcate in the signing chain of the signature being veriﬁed.
– C. Any entry with SignatureListType ofEFI_CERT_X509_GUID, with SignatureData which contains a certiﬁcate
with the same Issuer, Serial Number, and To-Be-Signed hash included in any certiﬁcate in the signing chain of the
signature being veriﬁed.
Multiple signatures are allowed to exist in the binary’s certiﬁcate table (as per PE/COFF Section “Attribute Certiﬁcate
Table”). Only one hash or signature is required to be present in dbin order to pass validation, so long as neither the
hash of the binary nor any present signature is reﬂected in dbx.
Then, based on this match or its own policy, the ﬁrmware can decide whether or not to launch the UEFI image.
4. Start UEFI Image. If the UEFI Image is approved, then it is launched normally.
5. UEFI Image Not Approved. If the UEFI image was not approved the platform ﬁrmware may use other methods
to discover if the UEFI image is authorized, such as consult a disk-based catalog or ask an authorized user. The
result can be one of three responses: Yes, No or Defer.
6. UEFI Image Signature Added To Signature Database. If the user approves of the UEFI image, then the UEFI
image’s signature is saved in the ﬁrmware’s signature database. If user approval is supported, then the ﬁrmware
be able to update of the Signature Database. For more information, see Signature Database Update.
7. Go To Next Boot Option. If an UEFI image is rejected, then the next boot option is selected normally and go to
step 3. This is in the case where the image is listed as a boot option.
8. UEFI Image Signature Passed In System Conﬁguration Table. If user defers, then the UEFI image signature is
copied into the Image Execution Information Table in the EFI System Conﬁguration Table which is available to
the operating system.
9. OS Application Validates UEFI Image. An OS application determines whether the image is valid.
10. UEFI Image Signature Added To Signature Database. For more information, see Signature Database Update.
32.6. UEFI Image Validation 1437Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 32.7: Authorization Process Flow
32.6. UEFI Image Validation 1438Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
11. End.
32.7 Device Authentication
32.7.1 Overview

11. End.
This section describes a way to use the platform ownership model to authenticate a platform device during platform
boot.
The platform ﬁrmware need maintain a device signature database (devdb), which includes a list of a root CA cer-
tiﬁcate or an intermediate certiﬁcate for the device. The root CA certiﬁcate or the intermediate certiﬁcate is used to
authenticate the device. The device signature database is a single UEFI authenticated variable.
A device root CA certiﬁcate in the device signature database may be revoked. In this case, the platform ﬁrmware
should update the device signature database to remove the old certiﬁcate and add a new certiﬁcate.
During the system boot, when a bus or device driver discovers a device, it follows below steps:
• The bus or device driver checks if the device authentication boot mode is enabled by reading L”devAuthBoot”
variable. If the variable shows the device authentication boot mode is enabled, then the bus or device driver need
perform following steps.
• The bus or device driver may consult a policy to see if it need authenticate this device. The policy is platform
speciﬁc. It could be all external devices, all PCI devices, devices attached on certain ports, etc.
• The bus or device driver gets the device identity information, such as a device certiﬁcate or certiﬁcate chain. For
example, the Secure Protocol and Data Model (SPDM) GET_CERTIFICATE command.
• The bus or device driver veriﬁes if the certiﬁcate chain is anchored by any root CA certiﬁcate or any intermediate
certiﬁcate in the device signature database.
• The bus or device driver generates a nonce and uses a challenge/response protocol to verify if the device owns the
private key associated with the device certiﬁcate. For example, the SPDM CHALLENGE or KEY_EXCHANGE
command.
• After the bus or device driver passes all veriﬁcation for the device, the bus or device driver then enables the
device on the UEFI ﬁrmware environment. For example, a PCI bus driver will assign bus number, allocate PCI
IO/MMIO bar, and install EFI_PCI_IO_PROTOCOL for the PCI device.
• If any veriﬁcation fails, the bus or device driver ignores this device and notiﬁes the platform. The platform
ﬁrmware may take a platform speciﬁc action for the device or the platform. For example, a platform may ignore
the device. A platform may disconnect or disable the PCI device. Or a platform may reboot the system or halt
The device authentication ﬂow only veriﬁes the identity of the device and ensure it is a known device. But it does not
verify if a device contains the latest certiﬁcate or if the device has the latest ﬁrmware.
• A device leaf certiﬁcate may be revoked. The device signature database does not need to be updated. This can
be detected by the attestation. For example, if the platform enables trusted boot ﬂow and the platform ﬁrmware
extends the device certiﬁcate chain to the trust platform module (TPM) platform conﬁguration register (PCR). A
veriﬁer can get the device certiﬁcate and check the known certiﬁcate revocation list (CRL) to see if it is revoked.
• A device may include an old version ﬁrmware. It is not related to the device signature database. This is also be
detected by the attestation. For example, the platform ﬁrmware may extend the device ﬁrmware measurement
to TPM PCR. A veriﬁer can get the device ﬁrmware information and compare it with the known good device
integrity measurement.
32.7. Device Authentication 1439Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• In both above cases, a platform may deﬁne its own policy to perform more veriﬁcation. For example, a platform
may enroll a small set of known revoked certiﬁcate. Or a platform may enroll the minimal secure version number
for some speciﬁc devices.
32.7.2 Authorized User
An authorized user (for the purposes of UEFI device authentication) is one who possesses a platform key (PKpriv).
This key is used to sign updates to the device signature databases.
32.7.3 Device Signature Database Update
The Authorized device signature databases are stored as UEFI authenticated variables (see Variable Services in Section
8.1.1) with the GUID EFI_DEVICE_SECURITY_DATABASE_GUID.
These authenticated UEFI variables that store the device signature databases (devdb) can always be read but can only
be written if:
• The platform is in user mode and the provided variable data is signed with the private half of the platform private
key (PKpriv); or if
SetVariable() call needs to be formatted in accordance with the procedure for authenticated variables in Section
8.2.1)
The platform vendor may provide a default set of entries for the Signature Database in the devdbDefault variable
described in Section 3.3. The ﬂow to update the device signature database (devdb) is exactly same as the ﬂow to
update the image signature databases, which is described in Section 32.5.3.
32.8 Code Deﬁnitions
32.8.1 UEFI Image Variable GUID & Variable Name
Summary
Constants used for UEFI signature database variable access.
Prototype
#define EFI_IMAGE_SECURITY_DATABASE_GUID \
{ 0xd719b2cb, 0x3d3a, 0x4596, \
{ 0xa3, 0xbc, 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f }}
#define EFI_IMAGE_SECURITY_DATABASE L"db"
#define EFI_IMAGE_SECURITY_DATABASE1 L"dbx"
#define EFI_IMAGE_SECURITY_DATABASE2 L"dbt"
#define EFI_IMAGE_SECURITY_DATABASE3 L"dbr"
• This GUID and name are used when calling the EFI Runtime Services GetVariable() andSetVariable() .
• The EFI_IMAGE_SECURITY_DATABASE_GUID andEFI_IMAGE_SECURITY_DATABASE are used to re-
trieve and change the authorized signature database.
• The EFI_IMAGE_SECURITY_DATABASE_GUID andEFI_IMAGE_SECURITY_DATABASE1 are used to re-
trieve and change the forbidden signature database.
32.8. Code Deﬁnitions 1440Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• The EFI_IMAGE_SECURITY_DATABASE_GUID andEFI_IMAGE_SECURITY_DATABASE2 are used to re-
trieve and change the authorized timestamp signature database.
• The EFI_IMAGE_SECURITY_DATABASE_GUID andEFI_IMAGE_SECURITY_DATABASE3 are used to re-
trieve and change the authorized recovery signature database.
• Firmware shall support the EFI_VARIABLE_APPEND_WRITE ﬂag () Exception for Machine Check, INIT, and
NMI ) for the UEFI signature database variables.
• The signature database variables db, dbt, dbx, and dbr must be stored in tamper-resistant non-volatile storage.
32.8.2 UEFI Device Signature Variable GUID and Variable Name
Summary
Constants used for UEFI device signature database variable access.
Prototype
#define EFI_DEVICE_SECURITY_DATABASE_GUID \
{0xb9c2b4f4, 0xbf5f, 0x462d, 0x8a, 0xdf, 0xc5, 0xc7, 0xa, 0xc3, 0x5d, 0xad}
v#define EFI_DEVICE_SECURITY_DATABASE L”devdb”
• This GUID and name are used when calling the EFI Runtime Services GetVariable() and SetVariable().
• The EFI_DEVICE_SECURITY_DATABASE_GUID and EFI_DEVICE_SECURITY_DATABASE are used to
retrieve and change the authorized device signature database.
• Firmware shall support the EFI_V ARIABLE_APPEND_WRITE ﬂag (see Section 8.1.1) for the UEFI device
signature database variables.
• The device signature database variable dbdev must be stored in tamper-resistant nonvolatile storage.
32.8. Code Deﬁnitions 1441CHAPTER
THIRTYTHREE
HUMAN INTERFACE INFRASTRUCTURE OVERVIEW
This section deﬁnes the core code and services that are required for an implementation of the Human Interface Infras-
tructure (HII). This speciﬁcation does the following:
• Describes the basic mechanisms to manage user input
• Provides code deﬁnitions for the HII-related protocols, functions, and type deﬁnitions that are architecturally
required by the UEFI Speciﬁcation
33.1 Goals
This chapter describes the mechanisms by which UEFI-compliant systems manage user input. The major areas de-
scribed include the following:
• String and font management.
• User input abstractions (for keyboards and mice)
• Internal representations of the forms (in the HTML sense) that are used for running a preboot setup.
• External representations (and derivations) of the forms that are used to pass conﬁguration information to runtime
applications, and the mechanisms to allow the results of those applications to be driven back into the ﬁrmware.
General goals include:
• Simpliﬁed localization, the process by which the interface is adapted to a particular language.
• A “forms” representation mechanism that is rich enough to support the complex conﬁguration issues encoun-
tered by platform developers, including stock keeping unit (SKU) management and interrelationships between
questions in the forms.
• Deﬁnition of a mechanism to allow most or all the conﬁguration of the system to be performed during boot,
at runtime, and remotely. Where possible, the forms describing the conﬁguration should be expressed using
existing standards such as XML.
• Ability for the different drivers (including those from add-in cards) and applications to contribute forms, strings,

and fonts in a uniform manner while still allowing innovation in the look and feel for Setup.
Support user-interface on a wide range of display devices:
• Local text display
• Local graphics display
• Remote text display
• Remote graphics display
• Web browser
1442Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• OS-present GUI
Support automated conﬁguration without a display.
33.2 Design Discussion
This section describes the basic concepts behind the Human Interface Infrastructure. This is a set of protocols that al-
low a UEFI driver to provide the ability to register user interface and conﬁguration content with the platform ﬁrmware.
Unlike legacy option ROMs, the conﬁguration of drivers and controllers is delayed until a platform management utility
chooses to use the services of these protocols. UEFI drivers are not allowed to perform setup-like operations outside
the context of these protocols. This means that a driver is not allowed to interact with the user outside the context of
this protocol.
The following example shows a basic platform conﬁguration or “setup” model. The drivers and applications install
elements (such as fonts, strings, images and forms) into the HII Database, which acts as a central repository for the
entire platform. The Forms Browser uses these elements to render the user interface on the display devices and receive
information from the user via HID devices. When complete, the changes made by the user in the Forms Browser are
saved, either to the UEFI global variable storage–( GetVariable() andSetVariable()– or to variable storage provided
by the individual drivers.
Fig. 33.1: Platform Conﬁguration Overview
33.2. Design Discussion 1443Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.1 Drivers And Applications
The user interface elements in the form of package lists are carried by the drivers and applications. Drivers and applica-
tions can create the package lists dynamically, or they can be pre-built and carried as resources in the driver/application
image.
If they are stored as resources, then an editor can be used to modify the user interface elements without recompiling.
For example, display elements can be modiﬁed or deleted, new languages added, and default values modiﬁed.
Fig. 33.2: HII Resources In Drivers & Applications
The means by which the string, font, image and form resources are created is beyond the scope of this speciﬁcation.
The following diagram shows a few possible implementations. In both cases, the GUI design is an optional element
and the user-interface elements are stored within a text-based resource ﬁle. Eventually, this source ﬁle is converted
into a RES ﬁle (PE/COFF Resource Section) which can be linked with the main application.
33.2.1.1 Platform and Driver Conﬁguration
The intent is for this speciﬁcation to enable the conﬁguration of various target components in the system. The nor-
mally arduous task of managing user interface and conﬁguration can be greatly simpliﬁed for the consumers of such
functionality by enabling the platform to comprehend some standard user interactions.
33.2.1.2 Pre-O/S applications
There are various scenarios where a platform component must interact in some fashion with the user. Examples of
this are when presenting a user with several choices of information (e.g. boot menu) and sending information to the
display (e.g. system status, logo, etc.).
33.2.1.3 Description of User Interface Components
Various components listed in this speciﬁcation are described in greater detail in their own sections. The user interface
is composed of several distinct components illustrated below.
33.2.1.4 Forms
This component describes what type of content needs to be displayed to the user by means of a binary encoding
(i.e., Internal Forms Representation) and also has added context information such as how to validate certain input and
further describes where to store such input if it is intended to be non-volatile. Applications such as a browser or script
engine may use the information with the forms to validate conﬁguration setting values with or without a user interface.
33.2. Design Discussion 1444Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.3: Creating UI Resources With Resource Files
33.2. Design Discussion 1445Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.4: Creating UI Resources With Intermediate Source Representation
33.2. Design Discussion 1446Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.5: The Platform and Standard User Interactions
Fig. 33.6: User and Platform Component Interaction
Fig. 33.7: User Interface Components
33.2. Design Discussion 1447Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.1.5 Strings
The strings are the text-based (UCS-2 encoded) representations of the information typically being referenced by the
forms. The intent of this infrastructure is also to seamlessly enable multiple language support. To that end the strings
have the appropriate language designators to differentiate one language from another.
33.2.1.6 Images/Fonts
Since most content is typically intended to have the ability to be rendered on the local system, the human interface
infrastructure also supports the ability for images and fonts to be accepted and used by the underlying user interface
components.
33.2.1.7 Consumers of the user interface data
The ultimate consumer of the user interface information will be some type of forms browser or forms processor. There
are several usage scenarios which should be supported by this speciﬁcation. These are illustrated below:
33.2.1.8 Connected forms browser/processor
The ability to have the forms processing engine render content when directly connected to the target platform should be
apparent. From the forms processing engine perspective, this could be the local machine or a machine that is network
attached. In either case, there is a constructed agent which feeds the material to the forms processor for purposes of
rendering the user interface and interacting with the user. Note that a forms processor could simply act on the forms
data without ever having to render the user interface and interact with the user. This situation is much more akin to
script processing and should be a very supportable situation.
Fig. 33.8: Connected Forms Browser/Processor
33.2.1.9 Disconnected Forms Browser/Processor
By enabling the ability to import and export a platform’s settings, this infrastructure can also enable the ability for
ofﬂine conﬁguration. In this instance, a forms processor can interpret a given platform’s form data and enable (either
through user interaction or through automated scripting) the changing of conﬁguration settings. These settings can
then be applied to the target platform when a connection is established.
33.2. Design Discussion 1448Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.9: Disconnected Forms Browser/Processor
33.2.1.10 O/S-Present Forms Browser/Processor
When it is desired that the forms data be used in the presence of an O/S, this speciﬁcation describes a means by which
to support this capability. By being able to encapsulate the data and export it through standard means such that an
O/S agent (e.g. forms browser/processor) can retrieve it, O/S-present usage models can be made available for further
value-add implementations.
Fig. 33.10: O/S-Present Forms Browser/Processor
33.2.1.11 Where are the Results Stored
The forms data encodes how to store the changes per conﬁguration question. The ability to save data to the platform as
well as to a proprietary on-board store is provided. The premise is that each of the target non-volatile store components
(e.g. motherboard, add-in device, etc.) would advertise an interface as described in this speciﬁcation so that the forms
browser/processor can route changes to the appropriate target.
33.2.2 Localization
Localization is the process by which the interface is adapted to a particular language. The table below discusses issues
with localization and provides possible solutions.
Table 33.1: Localization Issues
Issue Example Solution Comment
33.2. Design Discussion 1449Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 33.1 – continued from previous page
Directional dis-
playRight to left
printing for
Hebrew.Printing di-
rection is a
function of the
language.The display engine may or may not support all display
techniques. If a language supports a display mechanism
that the display engine does not, the language that uses
the font must be selected.
Punctuation Punctuation
is directional.
A comma in
a right-to-left
language is
different from
a comma in
a left-to-right
language.Character
choice is the
choice of the
author or trans-
lator.
Line breakage Rules vary from
language to lan-
guage.The UEFI pre-
boot GUI per-
forms little or no

A comma in
a comma in
lator.
formatting.The runtime display depends on the runtime browser
and is not deﬁned here.
Date and time Most Europeans
would write
July 4, 1776,
as 4/7/1776
while the
United States
would write it
7/4/1776 and
others would
write 1776/7/4.
The separator
characters be-
tween the parts
of both date and
time vary as
well.Generally left to
the creator of
the user inter-
face.
Numbers 12,345.67 in
one language
is presented as
12.345,67 in
another.Print only inte-
gers and do not
insert separator
characters.This solution is gaining acceptance around the world as
more people use computers.
33.2.3 User Input
To limit the number of required glyphs, we must also limit the amount and type of user input.
User input generally comes from the following main types of devices:
• Keyboards
• Mouse-like pointing devices
Input from other devices, such as limited keys on a front panel, can be handled two ways:
• Treat the limited keys as special-purpose devices with completely unique interfaces.
• Programmatically make the limited keys mimic a keyboard or mouse-like pointing device.
33.2. Design Discussion 1450Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.11: Platform Data Storage
Pointing devices require no localization. They are universally understood by the subset of the world population ad-
dressed in this speciﬁcation. For example, if a person does not know how to use a mouse or other pointing device, it is
probably not a good idea to allow that person to change a system’s conﬁguration.
On the other hand, keyboards are localized at the keycaps but not in the electronics. In other words, a French keyboard
and a German keyboard might have very different keys but the software inside the keyboard–let alone the software in
the system at the other end of the wire–cannot know which set of keycaps are installed.
This speciﬁcation proposes to solve this issue by using the keys that are common between keyboards and ignoring
language-speciﬁc keys. Keys that are available on USB keyboards in preboot mode include the following:
• Function keys (F1 - F12)
• Number keys (0-9)
• “Upside down T” cursor keys (the arrows, home, end, page up, page down)
• Numeric keypad keys
• The Enter, Space, Tab, and Esc keys
• Modiﬁer keys (shifts, alts, controls, Windows*)
• Number lock
The scan codes for these keys do not vary from language to language. These keys are the standard keys used for
browser navigation although most end-users are unaware of this fact. Help for form-entry-speciﬁc keys must be
provided to enable a useful keys-only interface. The one case where other, language-speciﬁc keys may be used is to
enter passwords. Because passwords are never displayed, there is no requirement to translate scan code to Unicode
character codes (keyboard localization) or scan codes to font glyphs.
Additional data can be provided to enable a richer set of input characters. This input is necessary to support features
such as arbitrary text input and passwords.
33.2. Design Discussion 1451Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.4 Keyboard Layout
33.2.4.1 Keyboard Mapping
UEFI’s keyboard mapping loosely based deﬁnitions on ISO 9995. It bases the naming mechanism on the ﬁgure
below. The keys highlighted in brown are the keys that nearly all keyboard layouts use for customizations. However,
customization does not necessarily mean that all the keys are different. In fact, most of the keys are likely to be the
same. When modifying the mapping, one can normally reference the keys in brown as the likely candidates (for whom
to create modiﬁcations).
Fig. 33.12: Keyboard Layout
Instead of referencing keys in hardware-speciﬁc ways such as scan codes, the HII speciﬁcation deﬁnes an EFI_KEY
enumeration that allows for a simple method of referencing this hardware abstraction. Type EFI_KEY is deﬁned in
EFI_HII_DATABASE_PROTOCOL.GetKeyboardLayout() . It also provides a way to update the keyboard layout with
a great deal of ﬂexibility. Any of the keys can be mapped to any 16-bit Unicode character code or control code value.
When deﬁning the values for a particular key, there are six elements that are pertinent to the key:
Key name — The EFI_KEY enumeration deﬁnes the names of the above keys.
Unicode Character Code — Deﬁnes the Unicode Character Code (if any) of the named key.
Shifted UnicodeCharacter Code — Deﬁnes the Unicode Character Code (if any) of the named key while the shift
modiﬁer key is being pressed
Alt-GR Unicode Character Code — Deﬁnes the Unicode Character Code (if any) of the named key while the Alt-GR
modiﬁer key (if any) is being pressed.
Shifted Alt-GR UnicodeCharacter Code — Deﬁnes the Unicode Character Code (if any) of the named key while
the Shift and Alt-GR modiﬁer key (if any) is being pressed.
Modiﬁer key value — Deﬁnes the nonprintable special function that this key has assigned to it.
• Under normal circumstances, a key that has any Unicode character code deﬁnitions generally has a modiﬁer key
value of EFI_NULL_MODIFIER. This value means the key has no special function other than the printing of a
character. An exception to the rule is if any of the Unicode character codes have a value of 0xFFFF. Although
rarely used, this value is the one case in which a key might have both a printable character and an active control
key value.
An example of this exception would be the numeric keypad’s insert key. The deﬁnition for this key on a standard US
keyboard is as follows:
Key = EfiKeyZero
Unicode = 0x0030 (basically a ‘0’)
ShiftedUnicode = 0xFFFF (the exception to the rule)
AltGrUnicode = 0x0000
ShiftedAltGrUnicode = 0x0000
Modifier = EFI_INSERT_MODIFIER
33.2. Design Discussion 1452Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This key is one of the few keys that, under normal circumstances, prints something out but also has a special function.
These special functions are generally limited to the numeric keypad; however, this general limitation does not prevent
someone from having the ﬂexibility of deﬁning these types of variations.
33.2.4.2 Modiﬁer Keys
The deﬁnitions of the modiﬁer keys allow for special functionality that is not necessarily accomplished by a printable
character. Many of these modiﬁer keys are ﬂags to toggle certain state bits on and off inside of a keyboard driver.
An example is EFI_CAPS_LOCK_MODIFIER . This state being active could alter what the typing of a particular
key produces. Other control keys, such as EFI_LEFT_ARROW_MODIFIER andEFI_END_MODIFIER , affect
the position of the cursor. One modiﬁer key is likely unfamiliar to most people who exclusively use US keyboards,
and that key is the EFI_ALT_GR_MODIFIER key. This key’s primary purpose is to activate a secondary type of
shift modiﬁer that exposes additional printable characters on certain keys. In some keyboard layouts, this key does not
exist and is normally the EFI_RIGHT_ALT_MODIFIER key. None of the other modiﬁer key functions should be a
mystery to someone familiar with the usage of a standard computer keyboard.
An example of a few descriptor entries would be as follows:
Layout = {
EfiKeyLCtrl,0,0,0,0, *EFI_LEFT_CONTROL_MODIFIER, *//Left control
// key
EfiKeyA0,0,0,0,0,EFI_NULL_MODIFIER, //Not defined
// windows key
EfiKeySpaceBar,0x0020,0x0020,0x0020,0x0020,EFI_NULL_MODIFIER
//(Space Bar)
}
See “Related Deﬁnitions” in EFI_HII_DATABASE_PROTOCOL.GetKeyboardLayout() for the deﬁned modiﬁer val-
ues.
33.2.4.3 Non-Spacing Keys
Non-spacing keys are a concept that provides the ability to ORtogether an accent key and another printable character.
Non-spacing keys are deﬁned as special types of modiﬁer characters. They are typically accent keys that do not
advance the cursor and in essence are a type of modiﬁer key in that they maintain some level of state.
The way a person uses a non-spacing key is that the non-spacing key that maybe has the function of overlaying an
umlaut (two dots) onto whatever the next character might be. The user presses the umlaut non-spacing key and follows
it with a capital A, which yields an “Ä.”
//
// If it’s a dead key, we need to pass a list of physical key
// names, each with a unicode, shifted, altgr, shiftedaltgr
// character code. Each key name will have a Modifier value of
// EFI_NS_KEY_MODIFIER for the first entry, and then the list of
// EFI_NS_KEY_DEPENDENCY_MODIFIER physical key descriptions.
// This eventually will lead to the next normal non-modifier key
// definition.
//
// This requires defining an additional Modifier value of
// EFI_NS_KEY_DEPENDENCY_MODIFIER to signify
// EFI_NS_KEY_MODIFIER children definitions.
//
33.2. Design Discussion 1453Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// The keyboard driver (consumer of the layouts) will know that
// any key definitions with the EFI_NS_KEY_DEPENDENCY_MODIFIER

//
//
//
// modifier do not redefine the value of the specified EFI_KEY.
// They are simply used as a special case augmentation to the
// original EFI_NS_KEY_MODIFIER.
//
// It is an error condition to define a
// EFI_NS_KEY_MODIFIER without having all the
// EFI_NS_KEY_DEPENDENCY_MODIFIER keys defined serially.
//
Layout = {
EfiKeyE0, 0, 0, 0, 0, EFI_NS_KEY_MODIFIER,
EfiKeyC1, 0x00E2, 0x00C2, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER,
EfiKeyD3, 0x00EA, 0x00CA, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER,
EfiKeyD8, 0x00EC, 0x00CC, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER,
EfiKeyD9, 0x00F4, 0x00D4, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER,
EfiKeyD7, 0x00FB, 0x00CB, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER
}
In the above example, a key located at E0 is designated as a dead key. Using a common German keyboard layout as
the example, a circumﬂex accent “^” is deﬁned as a dead key at the E0 location. The A, E, I, O, and U characters are
valid keys that can be pressed after the dead key and will produce a valid printable character. These characters are
located at C1, D3, D8, D9, and D7 respectively.
The results of the Layout deﬁnition provided above would allow for the production of the following characters:
âÂêÊîÎôÔûÛ.
33.2.5 Forms
This speciﬁcation describes how a UEFI driver or application may present a forms (or dialogs) based interface. The
forms-based interface assumes that each window or screen consists of some window dressing (title & buttons) and
a list of questions. These questions represent individual conﬁguration settings for the application or driver, although
several GUI controls may be used for one question.
Fig. 33.13: Forms-based Interface Example
The forms are stored in the HII database, along with the strings, fonts and images. The various attributes of the forms
and questions are encoded in IFR (Internal Forms Representation)–with each object and attribute a byte stream.
Other applications (so-called “Forms Processors”) may use the information within the forms to validate conﬁguration
setting values without a user interface at all.
33.2. Design Discussion 1454Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The Forms Browser provides a forms-based user interface which understands how to read the contents of the forms,
interact with the user, and save the resulting values. The Forms Browser uses forms data installed by an application
or driver during initialization in the HII database. The Forms Browser organizes the forms so that a user may navigate
between the forms, select the individual questions and change the values using the HID and display devices. When the
user has ﬁnished making modiﬁcations, the Forms Browser saves the values, either to the global EFI variable store or
else to a private variable store provided by the driver or application.
Fig. 33.14: Platform Conﬁguration Overview
33.2.5.1 Form Sets
Form sets are logically-related groups of forms.
Attributes
Each forms set has the following attributes:
Form Set Identiﬁer – Uniquely identiﬁes the form set within a package list using a GUID. The Form Set Identiﬁer,
along with a device path, uniquely identiﬁes a form set in a system.
Form Set Class Identiﬁer – Optional array of up to three GUIDs which identify how the form set should
be used or classiﬁed. The list of standard form set classes is found in the “Related Deﬁnitions” section of
EFI_FORM_BROWSER2_PROTOCOL.SendForm().
Title – Title text for the form set.
Help – Help text for the form set.
Image – Optional title image for the form set.
Animation – Optional title animation for the form set.
Within a form set, there is one parent form and zero or more child forms. The parent form is the ﬁrst enabled, visible
form in the form set. The child forms are the second or later enabled, visible forms in the form set. In general, the
Forms Browser will provide a means to navigate to the parent form. A Cross-Reference is used to navigate between
forms within a form set or between forms in different form sets.
33.2. Design Discussion 1455Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Variable stores are declared within a form set. Variable stores describe the means for retrieval and storage of conﬁgu-
ration settings, and location information within that variable store. For more information, see Storage .
Default stores are declared within a form set. Default stores group together different types of default settings (normal,
manufacturing, etc.) and give them a name. See Defaults for more information.
The form set can control whether or not to process an individual form by nesting it inside of an EFI_IFR_DISABLE_IF
expression. Enable/Disable-1 for more information. The form set can control whether or not to display an individual
form by nesting it inside of an EFI_IFR_SUPPRESS_IF expression.
Syntax
The form set consists of an EFI_IFR_FORM_SET object, where the body consists of
form-set := EFI_IFR_FORM_SET form-set-list
form-set-list := form form-set-list|
EFI_IFR_IMAGE form-set-list |
EFI_IFR_ANIMATION form-set-list |
EFI_IFR_VARSTORE form-set-list |
EFI_IFR_VARSTORE_EFI form-set-list |
EFI_IFR_VARSTORE_NAME_VALUE form-set-list |
EFI_IFR_DEFAULTSTORE form-set-list |
EFI_IFR_DISABLE_IF expression form-set-list |
<empty>
EFI_IFR_SUPPRESS_IF expression form-set-list | <empty>
33.2.5.2 Forms
Forms are logically-related groups of statements (including questions) designed to be displayed together.
Each form has the following attributes:
Form Identiﬁer — A 16-bit unsigned integer, which uniquely identiﬁes the form within the form set. The Form
Identiﬁer, along with the device path and Form Set Identiﬁer, uniquely identiﬁes a form within a system.
Title — Title text for the form. The Forms Browser may use this text to describe the nature and purpose of the form
in a window title.
Image — Optional title image for the form. The Forms Browser may use this image to display the nature and purpose
of the form in a window title.
Animation — Optional title animation for the form set.
Modal — If a form is modal, then the on-form interaction must be completed prior to navigating to another form. See
“User Interaction”, User Interaction .
The form can control whether or not to process a statement by nesting it inside of an EFI_IFR_DISABLE_IF expres-
sion. See Enable/Disable-2 for more information.
The form can control whether a particular statement is selectable by nesting it inside of an EFI_IFR_GRAY_OUT_IF
expression. Statements that cannot be selected are displayed by Form Browsers, but cannot be selected by a user.
EFI_IFR_GRAY_OUT_IF causes statements to be displayed with some visual indication. See Evaluation Of Selectable
Statements for more information.
The form can control whether to display a statement by nesting it inside of an EFI_IFR_SUPPRESS_IF expression.
SeeEFI_IFR_SUPPRESS_IF for more information.
Syntax
The form consists of an EFI_IFR_FORM object, where the body consists of:
33.2. Design Discussion 1456Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
form := EFI_IFR_FORM form-tag-list |
EFI_IFR_FORM_MAP form-tag-list
form-tag-list := form-tag form-tag-list |
<empty>
form-tag := EFI_IFR_IMAGE |
EFI_IFR_ANIMATION |
EFI_IFR_LOCKED |
EFI_IFR_RULE |
EFI_IFR_MODAL_TAG |
statement |
question |
cond-statement-list |
<empty>
statement-list := statement statement-list |
question statement-list |
<empty>
cond-statement-list := EFI_IFR_DISABLE_IF expression
statement-list |
EFI_IFR_SUPPRESS_IF expression statement-list |
EFI_IFR_GRAY_OUT_IF expression statement-list |
question-list := question question-list |
<empty>
Other unknown opcodes are permitted, but will be ignored.
33.2.5.2.1 Enable/Disable-1
Disabled forms will not be processed at all by a Forms Processor. Forms are enabled unless:
• The form nests inside an EFI_IFR_DISABLE_IF expression which evaluated to FALSE .
• The disabling of forms is evaluated during Forms Processor initialization and is not re-evaluated.
33.2.5.2.2 Modiﬁability
Forms can be locked so that a Forms Editor will not change it. Forms are unlocked unless:
• The form has an EFI_IFR_LOCKED in its scope. The locking of statement is evaluated only during Forms
Editor initialization.
33.2.5.2.3 Visibility
Suppressed forms will not be displayed. Forms are visible unless:
• The form is disabled ( Questions )
• The form is nested inside an EFI_IFR_SUPPRESS_IF expression which evaluates to FALSE .
33.2. Design Discussion 1457Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.3 Statements
All displayable items within the body of a form are statements. Statements provide information or capabilities to the
user. Questions ( Questions ) are a specialized form of statement with a value. Statements are used only by Forms
Browsers and are ignored by other Forms Processors.
Statements have the following attributes:
Prompt — The text that will be displayed with the statement.
Help — The extended descriptive text that can be displayed with the statement.

Image — The optional image that will be displayed with the statement.
Animation — The optional animation that will be displayed with the statement.
Other than Questions, there are three types of statements:
• Static Text/Image
• Subtitle
• Cross-Reference
Syntax
statement:= subtitle | static-text | reset button
statement-tag-list := statement-tag statement-tag-list |
<empty>
statement-tag := EFI_IFR_IMAGE |
EFI_IFR_LOCKED
EFI_IFR_ANIMATION
33.2.5.3.1 Display
Statement display depends on the Forms Browser. Statements do not describe how the statement must be displayed
but rather provide resources (such as text and images) for use by the Forms Browser. The Forms Browser uses this
information to create the necessary user interface.
The Forms Browser may use the visibility ( Visibility-1 ) or selectability ( Evaluation Of Selectable Statements ) of the
statements to change the way the item is displayed. The EFI_IFR_GRAY_OUT_IF expression explicitly requires that
nested statements have visual differentiation from normal statements.
33.2.5.3.2 Enable/Disable-2
Statements which have been disabled will not be processed at all by a Forms Processor. Statements are enabled unless:
• The parent statement or question is disabled.
• The statement is nested inside an EFI_IFR_DISABLE_IF expression which evaluated to FALSE .
• The disabling of statements is evaluated during Forms Browser initialization and is not re-evaluated.
33.2. Design Discussion 1458Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.3.3 Visibility-1
Suppressed statements will not be displayed. Statements are displayed unless:
• The parent statement or question is suppressed.
• The statement is disabled Enable/Disable-1
• The statement is nested inside an EFI_IFR_SUPPRESS_IF expression which evaluates to FALSE .
The suppression of the statements is evaluated during Forms Browser initialization. Subsequently, the suppression of
statements is reevaluated each time a value in any question on the selected form has changed.
33.2.5.3.4 Evaluation of Selectable Statements
A user in a Forms Browser can choose statements which are selectable. Statements are selectable unless:
• The parent statement or question is not selectable.
• The statement is suppressed Enable/Disable-2
• The statement is nested inside an EFI_IFR_GRAY_OUT_IF expression which evaluated to FALSE .
The evaluation of selectable statements takes place during Forms Browser initialization. Subsequently, selectable
statements are reevaluated each time a value in any question on the selected form has changed.
33.2.5.3.5 Modiﬁability
A statement can be locked so that a Forms Editor will not change it. Statements are unlocked unless:
• The parent form or parent statement/question is locked.
• The statement has an EFI_IFR_LOCKED in its scope.
The locking of a statement is evaluated only during Forms Editor initialization.
33.2.5.3.6 Static Text/Image
The Forms Browser displays the speciﬁed prompt, the speciﬁed text and (optionally) the image, but has no user
interaction.
Syntax
static-text:= EFI_IFR_TEXT statement-tag-list
33.2.5.3.7 Subtitle
The subtitle is a means of visually grouping questions by providing a separator, some optional separating text, and an
optional image.
Syntax
subtitle:= EFI_IFR_SUBTITLE statement-tag-list
33.2. Design Discussion 1459Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.3.8 Reset Button
Reset Buttons have the following attributes:
Default Id — Speciﬁes the default set to use when restoring defaults to the current form.
Syntax
reset button : = EFI_IFR_RESET_BUTTON statement-tag-list
33.2.5.4 Questions
Questions are statements which have a value. The value corresponds to a conﬁguration setting for the platform or for
a device. The question uniquely identiﬁes the conﬁguration setting, describes the possible values, the way the value is
stored, and how the question should be displayed.
Questions have the following attributes (in addition to those of statements):
Question Identiﬁer — A 16-bit unsigned integer which uniquely identiﬁes the question within the form set in which
it appears. The Question Identiﬁer, along with the device path and Form Set Identiﬁer, uniquely identiﬁes a question
within a system.
Default Value — The value used when the user requests that defaults be loaded.
Manufacturing Value — The value used when the user requests that manufacturing defaults are loaded.
Value — Each question has a current value. See Values for more information.
Value Format — The format used to store a question’s value.
Value Storage — The means by which values are stored. See Storage Requirements for more information.
Refresh Identiﬁers — Zero or more GUIDs associated with an event group initialized by the Forms Browser when the
form set containing the question is opened. If the event group associated with the GUID is signaled (see SignalEvent()
), then the question value will be updated from storage.
Refresh Interval — The minimum number of seconds that must pass before the Forms Browser will automatically
update the current question value from storage. The default value is zero, indicating there will be no automatic refresh.
Validation — New values assigned to questions can be validated, using validation expressions, or, if connected, using
a callback. See Validation for more information.
Callback — If set, the callback will be called when the question’s value is changed. In some cases, the presence of
these callbacks prevents the question’s value from being edited while disconnected. The question can control whether
a particular option can be displayed by nesting it inside of an EFI_IFR_SUPPRESS_IF expression. Form Browsers
do not display Suppressed Options, but Suppressed Options may still be examined by Form Processors.
Syntax
question:= action-button | boolean | date | number | ordered-list | string | time |
cross-reference
question-tag-list:= question-tag question-tag-list |
<empty>
question-tag := statement-tag |
EFI_IFR_INCONSISTENT_IF expression |
EFI_IFR_NO_SUBMIT_IF expression |
EFI_IFR_WARNING_IF expression |
33.2. Design Discussion 1460Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_IFR_DISABLE_IF expression question-list |
EFI_IFR_REFRESH_ID RefreshEventGroupId |
EFI_IFR_REFRESH |
EFI_IFR_VARSTORE_DEVICE
question-option-tag := EFI_IFR_SUPPRESS_IF expression |
EFI_IFR_VALUE optional-expression |
EFI_IFR_READ expression |
EFI_IFR_WRITE expression |
default |
option
question-option-list := question-tag question-option-list |
question-option-tag question-option-list |
<empty>
Other unknown opcodes are permitted but are ignored.
33.2.5.4.1 Values
Question values are a data type listed in Data Types . During initialization of the Forms Processor or Forms Browser,
the values of all enabled questions are retrieved. If the value cannot be retrieved, then the question’s value is Undeﬁned.
A question with the value of type Undeﬁned will be suppressed. This suppression will be reevaluated based on Value
Refresh or when any question value on the selected form is changed.
When the form is submitted, the modiﬁed values are written to Value Storage. When the form is reset, the question
value is set to the default question value. If there is no default question value, the question value is unchanged.
When a question value is retrieved, the following process is used:
1. Set the this internal constant to have the samevalue as the one read from the question’s storage.**
2. If present, change the current question value to the value returned by a question’s nested EFI_IFR_READ oper-
ator.
When a question value is changed, the following process is used:
1. Set the this internal constant to have the samevalue as the current question value.
2. If present, evaluate the question’s nested EFI_IFR_WRITE (EFI_IFR_WRITE ) operator.
3. Write the value to the question’s storage
33.2.5.4.2 Storage Requirements
Question storage requirements describe the type and size of storage for the value. These storage requirements describe
whether the question’s value will be stored as an EFI global variable or using driver local storage. It also describes
whether the value is packed together with other values in a buffer, or passed as a name-value pair. See Storage for
more information.
33.2. Design Discussion 1461Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.15: Question Value Retrieval Process
33.2. Design Discussion 1462Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.16: Question Value Change Process
33.2. Design Discussion 1463Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.4.3 Display
Question display depends on the Forms Browser. Questions do not describe how the question must be displayed.
Instead, questions provide resources (such as text and images) and information about visibility and the ability to edit

the question. The Forms Browser uses these to create the necessary user interface. Questions can have prompt text,
help text and (optionally) an image. The prompt text usually describes the nature of the question. Help text is displayed
either in a special display area or only at the request of the user. Questions can also have hints which describe how to
visually organize the information
33.2.5.4.4 Action Button
Action buttons are buttons which cause a pre-deﬁned conﬁguration string to process immediately. There is no storage
directly associated with the button.
Action buttons have no additional attributes other than the common question attributes).
Storage — There is no storage associated with the action button.
Results — There are no results associated with the action button.If used in an expression, the question value will
always be Undeﬁned.
Syntax
action-button:= EFI_IFR_ACTION question-tag-list
33.2.5.4.5 Boolean
Boolean questions are those that allow a choice between TRUE andFALSE . The question’s value is Boolean.
In general, construct questions so that the prompt text asks questions resulting in ‘yes/enabled/on’ is ‘true’ and
‘no/disabled/off’ is ‘false’.
Boolean questions may be displayed as a check box, two radio buttons, a selection list, a list box, or a drop list box.
Boolean questions have no additional attributes other than the common question attributes:
Storage — If the boolean question uses Buffer storage or EFI Variable (see Storage ), then the size is exactly one byte,
with the FALSE condition is zero and the TRUE value is 1.
Results — The results are represented as either 0 ( FALSE ) or 1 ( TRUE ).
Syntax
boolean := EFI_IFR_CHECKBOX question-option-list
33.2. Design Discussion 1464Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.4.6 Date
Date questions allow modiﬁcation of part or all of a standard calendar date. The format of the date display depends on
the Forms Browser and any localization.
Date questions have the following attributes:
Year Suppressed — The year will not be displayed or updated.
Month Suppressed — The month will not be displayed or updated.
Day Suppressed — The day will not be displayed or updated.
UEFI Storage — In addition to normal question Value Storage, Date questions can optionally be instructed to save the
date to either the system time or system wake-up time using the UEFI runtime services SetTime() orSetWakeupTime().
In this case, the date and time will be read ﬁrst, the modiﬁcations made and changes will be written back.
Conversion to and from strings to a date depends on the system localization.
The date value is stored an EFI_HII_TIME structure. The TimeZone ﬁeld is always set to
EFI_UNSPECIFIED_TIMEZONE. The Daylight ﬁeld is always set to zero. The contents of the other ﬁelds
are undetermined.
Storage — If the date question uses Buffer storage or EFI Variable storage ( Storage ), then the stored result will
occupy exactly the size of EFI_HII_DATE.
Results — Results for date questions are represented as a hex dump of the EFI_HII_DATE structure. If used in a
question, the value will be a buffer containing the contents of the EFI_HII_DATE structure.
Syntax
date := EFI_IFR_DATE question-option-list
33.2.5.4.7 Number
Number questions allow modiﬁcation of an integer value up to 64-bits. Number questions can also specify pre-deﬁned
options.
Number questions have the following attributes:
Radix — Hint describes the output radix of numbers. The possible values are unsigned decimal, signed decimal or
hexadecimal. Numbers displayed in hexadecimal will be preﬁxed by ‘0x’
Minimum Value — The minimum unsigned value which can be accepted for this question.
Maximum Value — The maximum unsigned value which can be accepted for this question.
Skip Value — Deﬁnes the minimum increment between values.
Storage — If the number question uses Buffer storage or EFI Variable storage ( Storage ), then the buffer size speciﬁed
by must be 1, 2, 4 or 8. Also, the Forms Processor will do implicit error checking to make sure that the signed or
unsigned value can be stored in the Buffer without lost of signiﬁcant bits. For example, if the buffer size is 1 byte,
then the largest unsigned integer value would be 255. Likewise, the largest signed integer value would be 127 and
the smallest signed integer value would be -128. The Forms Processor will automatically detect this as an error and
generate an appropriate error.
Results — The results are represented as string versions of unsigned hexadecimal values.
33.2. Design Discussion 1465Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Syntax
number := EFI_IFR_NUMERIC question-option-list |
EFI_IFR_ONE_OF question-option-list
33.2.5.4.8 Set
Sets are questions where n containers can be ﬁlled with any of m pre-deﬁned choices. This supports both lists where
a given value can only appear in one of the slots or where the same choice can appear many times.
Each of the containers takes the form of an option which a name, a value and (optionally) an image.
Set questions have the following attributes:
Container Count — Speciﬁes the number of available selectable options.
Unique — If set, then each choice may be used at most, once.
NoEmpty — All slots must be ﬁlled with a non-zero value.
Storage — The set questions are stored as a Buffer with one byte for each Container.
Results
Each Container value is represented as two characters, one for each nibble. All hexadecimal characters (a-f) are in
lower-case.
The results are represented as a series of Container values, starting with the lowest Container.
Syntax
ordered-list := EFI_IFR_ORDERED_LIST question-option-list
Options
Set questions treat the values speciﬁed by nested EFI_IFR_ONE_OF_OPTION values as the value for a single Con-
tainer, not the entire question storage. This is different from other question types.
Defaults
Set questions treat the default values speciﬁed by nested EFI_IFR_DEFAULT orEFI_IFR_ONE_OF_OPTION op-
codes as the default value for all Containers. The default values must be of type EFI_IFR_TYPE_BUFFER, with each
byte in the buffer corresponding to a single Container value, starting with the ﬁrst container. If the buffer contains
fewer bytes than MaxContainers, then the remaining Containers will be set to a value of 0.
Default values returned from the ALTCFG section when ExtractConﬁg() is called ﬁll the storage starting with the ﬁrst
container.
33.2.5.4.9 String
String questions allow modiﬁcation of a string.
String questions have the following attributes:
Minimum Length — Hint describes the minimum length of the string, in characters.
Maximum Length — Hint describes the maximum length of the string, in characters.
33.2. Design Discussion 1466Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Multi-Line — Hint describes that the string might contain multiple lines.
Output Mask — If set, the text entered will not be displayed.
Storage — The string questions are stored as a NULL -terminated string. If the time question uses Buffer or EFI
Variable storage ( Storage ), then the buffer size must exceed the size of the NULL-terminated string. If the string is
shorter than the length of the buffer, the remainder of the buffer is ﬁlled with NULL characters.
Results — Results for string questions are represented as hex dump of the string, including the terminating NULL
character.
Syntax
string := EFI_IFR_STRING question-option-list |
EFI_IFR_PASSWORD question-option-list
33.2.5.4.10 Cross-Reference
Cross-reference questions provide a selectable means by which users navigate to other forms and/or other questions.
The form and question can be in the current form set, another form set or even in a form associated with a different
device. If the speciﬁed form or question does not exist, the button is not selectable, is grayed-out, or is suppressed.
Cross references can have the following attributes:
Form Identiﬁer — The identiﬁer of the target form.
Form Set Identiﬁer — Optionally speciﬁes an alternate form-set which contains the target form. If speciﬁed, then
the focus will be on form within the form set speciﬁed by Form Identiﬁer. If the Form Identiﬁer is not speciﬁed, then
the ﬁrst form in the Form Set is used.
Question Identiﬁer — Optionally speciﬁes the question identiﬁer of the target question on the target form. If speciﬁed
then focus will be placed on the question speciﬁed by this question identiﬁer. Otherwise, the focus will be on the ﬁrst
question within the speciﬁed form.
Device Path — Optionally, the device path which contains the Form Identiﬁer. Otherwise, the device path associated
with the form set containing this cross-reference will be used.
Storage — Storage is optional for a cross-reference question. It is only present when the cross-reference question
does not supply any target (i.e., REF5). If the question uses Buffer or EFI Variable storage ( Storage ), then the buffer
size must be exactly the size of the EFI_HII_REF structure.

Results — Results for cross-reference questions are represented as a hex dump of the question identiﬁer, form iden-
tiﬁer, form set GUID and null-terminated device path text. If used in a question, the question value will be a buffer
containing the EFI_HII_REF structure..
Syntax
*cross-reference *:=*EFI_IFR_REF * *statement-tag-list *
33.2. Design Discussion 1467Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.4.11 Time
Time questions allow modiﬁcation of part or all of a time. The format of the time display depends on the Forms
Browser and any localization.
Time questions have the following attributes:
Hour Suppressed — The hour will not be displayed or updated.
Minute Suppressed — The minute will not be displayed or updated.
Second Suppressed — The second will not be displayed or updated.
UEFI Storage — In addition to normal question Value Storage, time questions can be instructed to save the time to
either the system time or system wake-up time using the UEFI runtime services SetTime orSetWakeupTime. In these
instances, the date and time is read ﬁrst, the modiﬁcations made and changes are then written back.
Conversion to and from strings to a time depends on the system localization.
The time value is stored as part of an EFI_HII_TIME structure. The contents of the other ﬁelds are undetermined.
Storage — If the time question uses Buffer or EFI Variable storage ( Storage ), then the buffer size must be exactly
the size of the EFI_HII_TIME structure..
Results — Results for time questions are represented as a hex dump of the EFI_HII_TIME structure. If used in a
question, the value will be a buffer containing the contents of the EFI_HII_TIME structure.
Syntax
time := EFI_IFR_TIME question-option-list
33.2.5.5 Options
Use Options within questions to give text or graphic description of a particular question value. They may also describe
the choices in the set data type.
Options have the following attributes:
Text — The text for the option.
Image — The optional image for the option.
Animation — The optional animation for the option.
Value — The value for the option.
Default — If set, this is the option selected when the user asks for the defaults. Only one visible option can have this
bit set within a question’s scope.
Manufacturing Default — If set, this is the option selected when manufacturing defaults are set. Only one visible
option can have this bit set within a question’s scope.
Syntax
option:= EFI_IFR_ONE_OF_OPTION option-tag-list
option-tag-list := option-tag option-tag-list |
<empty>
option-tag:= EFI_IFR_IMAGE
33.2. Design Discussion 1468Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.5.1 Visibility
Options which have been suppressed will not be displayed. Options are displayed unless:
• The parent question is suppressed.
• The option is nested inside an EFI_IFR_SUPPRESS_IF expression which evaluated to FALSE .
The suppression of the options is evaluated each time the option is displayed.
33.2.5.6 Storage
Question values are stored in Variable Stores, which are application, platform or device repositories for conﬁguration
settings. In many cases, this is non-volatile storage. In other cases, it holds only the current behavior of a driver or
application.
Question values are retrieved from the variable store when the form is initialized. They are updated periodically based
on question settings and stored back in the variable store when the form is submitted.
It is possible for a question to have no associated Variable Store. This happens when the VarStoreId associ-
ated with the question is set to zero and, for Date/Time questions, the UEFI Storage is disabled. For questions
with no associated Variable Store, the question must either support the RETRIEVE and CHANGED callback ac-
tions ( EFI_HII_CONFIG_ACCESS_PROTOCOL.CallBack() ) or contain an embedded READ or WRITE opcode:
EFI_HII_IFR_READ_OP andEFI_IFR_WRITE_OP (EFI_IFR_READ andEFI_IFR_WRITE ).
Because the value associated with a question contained in a Variable Store can be shared by multiple questions, the
questions must all treat the shared information as compatible data types.There are four types of variable stores:
Buffer Storage — With buffer storage, the application, platform or driver provides the deﬁnition of a buffer
which contains the values for one or more questions. The size of the entire buffer is deﬁned in the
EFI_IFR_VARSTORE deﬁnition. Each question deﬁnes a ﬁeld in the buffer by providing an offset within
the buffer and the size of the required storage. These variable stores are exposed by the app/driver us-
ing the EFI_HII_CONFIG_ACCESS_PROTOCOL, which is installed on the same handle as the package list.
Question values are retrieved via EFI_HII_CONFIG_ACCESS_PROTOCOL.ExtractConﬁg() and updated via
EFI_HII_CONFIG_ACCESS_PROTOCOL.RouteConﬁg(). Rather than access the buffer as a whole, Buffer Storage
Variable Stores access each ﬁeld independently, via a list of one or more (ﬁeld offset, value) pairs encoded as variable
length text strings as deﬁned for the EFI_HII_CONFIG_ACCESS_PROTOCOL.
Name/Value Storage — With name/value storage, the application provides a string which contains the
encoded values for a single question. These variable stores are exposed by the app/driver using the
EFI_HII_CONFIG_ACCESS_PROTOCOL, which is installed on the same handle as the package list.
EFI Variable Storage — This is a specialized form of Buffer Storage, which uses the EFI runtime services GetVari-
able() andSetVariable() to access the entire buffer deﬁned for the Variable Store as a single binary object.
EFI Date/Time Storage — For date and time-related questions, the question values can be retrieved using the EFI
runtime services GetTime() andGetWakeupTime() and stored using the EFI runtime services SetTime() andSetWake-
upTime().
The following table summarizes the types of information needed for each type of storage and where it is retrieved
from.
Table 33.2: Information for Types of Storage
Storage Type Information Type Where It Comes From
None Driver Handle Handle speciﬁed with NewPackageList() or derived from
EFI_IFR_VARSTORE_DEVICE.DevicePath
33.2. Design Discussion 1469Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 33.2 – continued from previous page
Buffer Storage Driver Handle Handle speciﬁed with NewPackageList() or derived from
Variable ID
Variable store speciﬁed by
EFI_IFR_QUESTION_HEADER.VarStoreId.
EFI_IFR_V ARSTORE_DEVICE.DevicePath*
Variable Name
EFI_IFR_QUESTION_HEADER.VarStoreId
Variable Store Off-
setVariable store offset speciﬁed by
EFI_IFR_QUESTION_HEADER.VarOffset.
Name/Value Stor-
ageDriver Handle Handle speciﬁed with NewPackageList() or derived from
Variable name speciﬁed by
EFI_IFR_QUESTION_HEADER.VarStoreInfo.VarName.
EFI Variable Stor-
ageDriver Handle None
EFI_Variable GUID
(for Variable Ser-
vices)EFI variable GUID speciﬁed by EFI_IFR_VARSTORE_EFI.Guid.
EFI_Variable Name
vices)EFI variable name speciﬁed by EFI_IFR_VARSTORE_EFI.Name.
EFI_IFR_QUESTION_HEADER.VarStoreInfo.VarOffset.
EFI Date/Time Stor-
Variable ID None
Variable Name None
33.2. Design Discussion 1470Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.7 Expressions
This section describes the expressions used in various expressions in IFR. The expressions are encoded using normal
IFR opcodes, but in RPN (Reverse Polish Notation) where the operands occur before the operator.
The opcodes fall into these categories:
Unary operators. — Functions taking a single sub-expression.
Binary operators. — Functions taking two sub-expressions.
Ternary operators. — Functions taking three sub-expressions.
Built-in functions. — Operators taking zero or more sub-expressions.
Constants. — Numeric and string constants.
Question Values. — Speciﬁed by their question identiﬁer.
All integer operations are performed at 64-bit precision.
33.2.5.7.1 Expression Encoding
Expressions are usually encoded within the scope of another binary object. If the expression consists of more than a
single opcode, the ﬁrst opcode should open a scope ( Header.Scope = 1) and use an EFI_IFR_END opcode to close
the scope in order to make sure they can be skipped,
33.2.5.7.2 Expression Stack
When evaluating expressions, the Forms Processor uses a stack to hold intermediate values. Each operator either
pushes a value on the stack, pops a value from the stack, or both. For example, the EFI_IFR_ONE operator pushes

the integer value 1 on the expression stack. The EFI_IFR_ADD operator pops two integer values from the expression
stack, adds them together, and pushes the result back on the stack.
After evaluating an expression, there should be only one value left on the expression stack.
33.2.5.7.3 Rules
Rules are pre-deﬁned expressions attached to the form. These rules may be used in any expression within the form’s
scope. Each rule is given a unique identiﬁer (0-255) when it is created by EFI_IFR_RULE . This same identiﬁer is
used when the rule is referred to in an expression with EFI_IFR_RULE_REF .
To save space, rules are intended to allow manual or automatic extraction of common sub-expressions from form
expressions.
33.2.5.7.4 Data Types
The expressions use ﬁve basic data types:
Boolean —TRUE orFALSE .
Unsigned Integer — 64-bit unsigned integer.
String — Null-terminated string.
Buffer — Fixed size array of unsigned 8-bit integers.
33.2. Design Discussion 1471Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Undeﬁned — Undetermined value. Used when the value cannot be calculated or for run-time errors.
Data conversion is not implicit. Explicit data conversion can be performed using the EFI_IFR_TO_STRING ,
EFI_IFR_TO_UINT andEFI_IFR_TO_BOOLEAN .
The Date and Time question values are converted to the Buffer data type ﬁlled with the EFI_HII_DATE and
EFI_HII_TIME structure contents (respectively).
The Ref question values are converted to the Buffer data type and ﬁlled with the EFI_HII_REF and structure contents.
Syntax
The expressions have the following syntax:
expression := built- in-function |
constant |
expression unary-op |
expression expression binary-op |
expression expression expression ternary-op
expression-pair-list
EFI_IFR_MAP
expression-pair-list := expression-pair-list expression expression |
<empty>
optional-expression := expression |
<empty>
built-in-function := EFI_IFR_DUP |
EFI_IFR_EQ_ID_VAL |
EFI_IFR_EQ_ID_ID |
EFI_IFR_EQ_ID_VAL_LIST |
EFI_IFR_GET |
EFI_IFR_QUESTION_REF1 |
EFI_IFR_QUESTION_REF3 |
EFI_IFR_RULE_REF |
EFI_IFR_STRING_REF1 |
EFI_IFR_THIS |
EFI_IFR_SECURITY
constant := EFI_IFR_FALSE |
EFI_IFR_ONE |
*EFI_IFR_ONES |
EFI_IFR_TRUE |
EFI_IFR_UINT8 |
EFI_IFR_UINT16 |
EFI_IFR_UINT32 |
EFI_IFR_UINT64 |
EFI_IFR_UNDEFINED |
EFI_IFR_VERSION |
EFI_IFR_ZERO
binary-op := EFI_IFR_ADD |
EFI_IFR_AND |
EFI_IFR_BITWISE_AND |
EFI_IFR_BITWISE_OR |
EFI_IFR_CATENATE |
EFI_IFR_DIVIDE |
EFI_IFR_EQUAL |
EFI_IFR_GREATER_EQUAL |
EFI_IFR_GREATER_THAN |
EFI_IFR_LESS_EQUAL |
33.2. Design Discussion 1472Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_IFR_LESS_THAN |
EFI_IFR_MATCH |
EFI_IFR_MATCH2 |
EFI_IFR_MODULO |
EFI_IFR_MULTIPLY |
EFI_IFR_NOT_EQUAL |
EFI_IFR_OR |
EFI_IFR_SHIFT_LEFT |
EFI_IFR_SHIFT_RIGHT |
EFI_IFR_SUBTRACT |
unary-op := EFI_IFR_LENGTH |
EFI_IFR_NOT |
EFI_IFR_BITWISE_NOT |
EFI_IFR_QUESTION_REF2 |
EFI_IFR_SET |
EFI_IFR_STRING_REF2 |
EFI_IFR_TO_BOOLEAN |
EFI_IFR_TO_STRING |
EFI_IFR_TO_UINT |
EFI_IFR_TO_UPPER |
EFI_IFR_TO_LOWER
ternary-op := EFI_IFR_CONDITIONAL |
EFI_IFR_FIND |
EFI_IFR_MID |
EFI_IFR_TOKEN |
EFI_IFR_SPAN
33.2.5.8 Defaults
To ensure consistent behavior when a platform attempts to restore settings to defaults, each question op-code must
have an active default setting. Defaults are pre-deﬁned question values. The question values may be changed to
their defaults either through a Forms Processor-deﬁned means or when the user selects an EFI_IFR_RESET_BUTTON
statement ( Reset Button ).
Each question may have zero or more default values, with each default value used for different purposes. For example,
there might be a “standard” default value, a default value used for manufacturing and a “safe” default value. A group
of default values used to conﬁgure a platform or device for a speciﬁc purpose is called default store.
Default Stores
There are three standard default stores:
Standard Defaults — These are the defaults used to prepare the system/device for normal operation.
Manufacturing Defaults — These are the defaults used to prepare the system/device for manufacturing.
Safe Defaults — These are the defaults used to boot the system in a “safe” or low-risk mode.
Attributes — Default stores have the following attributes:
Name
Each default store has a user-readable name
Identiﬁer
A 16-bit unsigned integer. The values between 0x0000 and 0x3fff are reserved for use by the UEFI speciﬁcation. The
values between 0x4000 and 0x7fff are reserved for platform providers. The values between 0x8000 and 0xbfff are
reserved for hardware vendors. The values between 0xc000 and 0xffff are reserved for ﬁrmware vendors.
33.2. Design Discussion 1473Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_HII_DEFAULT_CLASS_STANDARD 0x0000
#define EFI_HII_DEFAULT_CLASS_MANUFACTURING 0x0001
#define EFI_HII_DEFAULT_CLASS_SAFE 0x0002
#define EFI_HII_DEFAULT_CLASS_PLATFORM_BEGIN 0x4000
#define EFI_HII_DEFAULT_CLASS_PLATFORM_END 0x7fff
#define EFI_HII_DEFAULT_CLASS_HARDWARE_BEGIN 0x8000
#define EFI_HII_DEFAULT_CLASS_HARDWARE_END 0xbfff
#define EFI_HII_DEFAULT_CLASS_FIRMWARE_BEGIN 0xc000
#define EFI_HII_DEFAULT_CLASS_FIRMWARE_END 0xffff
Users of these ranges are encouraged to use the speciﬁcation deﬁned ranges for maximum interoperability. Ques-
tions or platforms may support defaults for only a sub-set of the possible default stores. Support for default store 0
(“standard”) is recommended.
Defaulting
When retrieving the default values for a question, the Forms Processor uses one of the following (listed from highest
priority to lowest priority):
1. The value returned from the Callback() memberfunction of the Conﬁg Access protocol associated with the
question when called with the Action set to one of the*EFI_BROWSER_ACTION_DEFAULT_x* values ( EFI
HII Conﬁguration Access Protocol ) . It is recommended that this form only be used for questionswhere the
default value alters dynamically at runtime.**
2. The value returned in the Response parameter of the ConﬁgAccess() member function (using the ALTCFG
form). See String Syntax .
3. The value speciﬁed by an EFI_IFR_DEFAULT opcodes appear within the scope of a question. (
EFI_IFR_DEFAULT )
4. One of the Options ( Options ) has its Standard Default or Manufacturing Default attribute set.
5. For Boolean questions, the Standard Default or Manufacturing Default values in the Flags ﬁeld. ( Boolean ).
Syntax
Default := EFI_IFR_DEFAULT
default-tag := EFI_IFR_VALUE |
<empty>
33.2.5.9 Validation
Validation is the process of determining whether a value can be applied to a conﬁguration setting. Validation takes
place at three different points in the editing process: edit-level, question-level and form-level.
33.2.5.9.1 Edit-Level Validation
First, it takes place while the value is being edited with a Forms Browser. The Forms Browser may optionally reject
values selected by the user which would fail Question-Level validation. For example, the Forms Browser may limit
the length of strings entered so that they meet the Minimum and Maximum Length.
33.2. Design Discussion 1474Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.9.2 Question-Level Validation
Second, it takes place when the value has changed, normally when the user attempts to leave the control, navigate
between the portions of the control or selects one of the option values. At this point, an error occurs if:
• For a String ( String ), if the string length is less than the Minimum Length, then the Forms Processor generates
an error.
• For a String ( String ), if the string length is greater than the Maximum Length, then the Forms Processor
generates an error.
• For a Number ( Number ), if the number cannot ﬁt in the speciﬁed variable storage without loss of signiﬁcant
bits, then the Forms Processor generates an error.
• For all questions, if an EFI_IFR_INCONSISTENT_IF evaluates to TRUE , then the Forms Processor will display
the speciﬁed error text.
• For all questions, if an EFI_IFR_WARNING_IF evaluates to TRUE , then the Forms Processor will display the
speciﬁed warning text.
33.2.5.9.3 Form-Level Validation
Third, it takes place when exiting the form or when the values are submitted. The error occurs under two conditions:
• For all questions, if an EFI_IFR_NO_SUBMIT_IF evaluates to TRUE , then the Forms Processor will display
• If a Forms Processor such as a script processor performs Form-Level validation, where the concept of a form is
not maintained, then the Form-Level validation must occur before processing question values from other forms
or before completion of the conﬁguration session.
33.2.5.10 Forms Processing
Forms Processors interpret the IFR in order to extract information about conﬁguration settings. This section describes
how the IFR should be interpreted and how errors should be handled.
33.2.5.10.1 Error Handling

The Forms Processor may encounter problems in interpreting the IFR. This section describes the standard ways of
handling these issues:
Unknown Opcodes. — Unknown opcodes have a type which is not recognized by the Forms Processor. In general,
the Forms Processor ignores the opcode, along with any nested opcodes.
Malformed Opcodes. — Malformed objects have a length which is less than the minimum length for that object type.
In this case, the entire form is disabled.
Extended Opcodes. — Extended objects have a length longer than that expected by the Forms Processor. In this case,
the Forms Processor interprets the object normally and ignores the extra data.
Malformed Forms Sets — Malformed forms sets occur when an object’s length would cause it extend beyond the
end of the forms set, or when the end of the forms set occurs while a scope is still open. In this case, the entire forms
set is ignored.
Reserved Bits Set. — The Forms Processor should ignore all set reserved bits.
33.2. Design Discussion 1475Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.11 Forms Editing
This section describes considerations for Forms Editors, which are a specialized Forms Processor which can create
and manipulate form lists, forms and questions in their binary form.
33.2.5.11.1 Locking
Locking indicates that a question or statement,–along with its related options, prompts, help text or images–should not
be moved or edited. A statement or question is locked when the IFR_LOCKED opcode is found within its scope.
UEFI-compliant Forms Editors must allow statements or questions within an image to be locked, but should not allow
them to be unlocked. UEFI-compliant Forms Editors must not allow modiﬁcation of locked statements or questions
or any of their associated data (including options, text or images).
NOTE: This mechanism cannot prevent unauthorized modiﬁcation. However, it does clearly state the intent of the
driver creator that they should not be modiﬁed .
33.2.5.11.2 Moving Forms
When forms are moved between form sets, the related data (such as forms, variable stores and default stores) need to
have their references renumbered to avoid conﬂicts with identiﬁers in the new form set. For forms, these include:
•EFI_IFR_FORM orEFI_IFR_FORM_MAP (and all references in EFI_IFR_REF )
•EFI_IFR_DEFAULTSTORE (and all references in EFI_IFR_DEFAULT )
•EFI_IFR_VARSTORE_x (and all references within question headers)
33.2.5.11.3 Moving Questions
When questions are moved between form sets, the related data (such as images and strings) need to be moved and
references to results-processing and storage may need to be revised. For example:
String and Images. — If the question is being moved to another form set, then all strings and images associated with
the question must be moved to the package list containing the form set and removed from the current one.
Form Set. — If the question is moved to a package list installed by a different driver, then the
EFI_IFR_VAR_STORAGE_DEVICE (EFI_IFR_VARSTORE_DEVICE ) should be nested in the scope of the ques-
tion, describing the driver installation device path.
Question References. — If a question value in another form set is referred to in any expressions
(such as EFI_IFR_INCONSISTENT_IF orEFI_IFR_NO_SUBMIT_IF orEFI_IFR_WARNING_IF ) us-
ing either EFI_IFR_QUESTION_REF2 (EFI_IFR_Question_REF2 ) or EFI_IFR_QUESTION_REF1 (
EFI_IFR_Question_REF1 ) then these must be converted to a form of EFI_IFR_QUESTION_REF3
(EFI_IFR_Question_REF3 ) specifying the EFI_GUID of the form set and/or the device path of the package
list containing the form set wherein the question referred to is deﬁned.
When questions are moved between forms, whether in the same form list or another form list, question behavior reliant
on the current form may need revision. One example is the use of EFI_IFR_RULE_REF in expressions. Here, rules
are shortcuts for common expressions used in a form. If a question is moved to another form, the references to any
rules in expressions must be replaced by the expression itself.
33.2. Design Discussion 1476Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.5.12 Forms Processing & Security Privileges
The IFR provides a way for a Forms Processor to identify which forms, statements, questions and even question values
are available only to users with speciﬁc privilege levels and enforce those privilege levels.
Setup access security privileges are described in terms of GUIDs. The current user proﬁle either has the speciﬁed priv-
ilege or it does not. The EFI_IFR_SECURITY opcode returns whether or not the current user proﬁle has the speciﬁed
setup access privilege. Combined with the expressions such as EFI_IFR_DISABLE_IF , EFI_IFR_SUPPRESS_IF ,
EFI_IFR_GRAY_OUT_IF , EFI_IFR_WARNING_IF , EFI_IFR_INCONSISTENT_IF and EFI_IFR_NOSUBMIT_IF ,
the author of a form can control access to speciﬁc forms, statements and questions, or even control whether speciﬁc
values are valid.
Forms Processors on systems with multiple setup-related user privilege levels must support report these correctly when
processing the EFI_IFR_SECURITY opcode.
Forms Processors on systems which support the UEFI User Authentication proposal must correctly inquire from the
current user proﬁle whether or not it has security privileges on EFI_USER_INFO_ACCESS_SETUP andUser Manager
Protocol onEFI_USER_MANAGER_PROTOCOL.GetInfo() ).
Forms Processors on systems which support re-identiﬁcation during the platform conﬁguration process must
support reevaluation of the EFI_IFR_SUPPRESS_IF and EFI_IFR_GRAY_OUT_IF upon receipt of notiﬁca-
tion that the current user proﬁle has been changed by using the UEFI Boot Service CreateEventEx() and the
EFI_USER_PROFILE_CHANGED_EVENT_GUID.
33.2.6 Strings
Strings in the UEFI environment are deﬁned using UCS-2, which is a 16-bit-per-character representation. For user-
interface purposes, strings are one of the types of resources which can be installed into the HII Database ( HII Database
).
In order to facilitate localization, users reference strings by an identiﬁer unique to the package list which the driver
installed. Each identiﬁer may have several translations associated with it, such as English, French, and Traditional
Chinese. When displaying a string, the Forms Browser selects the actual text to display based on the current platform
language setting.
The actual text for each language is stored separately (in a separate package), which makes it possible to add and
remove language support just by including or excluding the appropriate package.
Each string may have font information, including the font family name, font size and font style, associated with it. Not
all platforms or displays can support fonts and styles beyond the system default font ( Fonts ), so the font information
associated with the string should be viewed as a set of hints.
33.2.6.1 Conﬁguration Language Paradigm
This speciﬁcation uses the RFC 4646 language naming scheme to identify the language that a given string is associated
with. Since RFC 4646 allows for the same Primary language tags to contain a large variation of subtags (e.g. regions),
a best matching language algorithm is deﬁned in RFC 4647. Callers of interfaces that require RFC 4646 language
codes to retrieve a Unicode string, must use the RFC 4647 algorithm to lookup the Unicode string with the closest
matching RFC 4646 language code.
Since the majority of strings discussed in this speciﬁcation are associated with generating a user interface, the lan-
guages that are typically associated with strings have commonly deﬁned languages such as en-US, zh-Hant, and it-IT.
The RFC 4646 standard also reserves for private use languages preﬁxed with a value of “x”.
NOTE :This speciﬁcation deﬁnes for its own purposes one of these private use areas as a special-purpose language
that components can use for extracting information out of. Assume that any private-use languages encountered by
33.2. Design Discussion 1477Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.17: String Identiﬁers
33.2. Design Discussion 1478Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
a compliant implementation will likely consider those languages as conﬁguration languages, and the associated be-
havior when referencing those languages will be platform speciﬁc .Working with a UEFI Conﬁguration Language
describes an example of such a use.
33.2.6.2 Unicode Usage
This section describes how different aspects of the Unicode speciﬁcation related to the strings within this speciﬁcation.
33.2.6.2.1 Private Use Area
Unicode deﬁnes a private use area of 6500 characters that may be deﬁned for local uses. Suggested uses include Egyp-
tian Hieroglyphics; see Developing International Software For Windows 95* and Windows NT* for more information.
UEFI prohibits use of this area in a UEFI environment. This is because a centralized font database accumulated from

the various drivers (a valid implementation) would end up with collisions in the private use area, and, generally, an
XML browser could not display these characters.
33.2.6.2.2 Surrogate Area
The Unicode speciﬁcation has two 16-bit character representations: UCS-2 and UTF-16. The UEFI speciﬁcation
uses UCS-2. The primary difference is that UTF-16 deﬁnes surrogate areas (see page 56 in Professional XML ) that
allow for expanded character representations of the 16-bit Unicode. These character representations are very similar
to Double Byte Character Set (DBCS)–2048 Unicode values split into two groups (D800-DBFF and DC00-DFFF).
They are deﬁned as having 16 additional bits of value to make up the character, for a total of about one million extra
characters. UEFI does not support surrogate characters.
33.2.6.2.3 Non-Spacing Characters
Unicode uses the concept of a nonspacing character. These glyphs are used to add accents, and so on, to other
characters by what amounts to logically OR’ing the glyph over the previous glyph. There does not appear to be
any predictable range in the Unicode encoding to determine nonspacing characters, yet these characters appear in
many languages. Further, these characters enable spelling of several languages including many African languages and
Vietnamese.
33.2.6.2.4 Common Control Codes
This speciﬁcation allows the encoding of font display information within the strings using special control charac-
ters. These control codes are meant as display hints, and different platforms may ignore them, depending on display
In single-byte encoding, these are in the form 0x7F 0xyy or0x7F 0x0y 0xzz. Single-byte encoding is used only when
coupled with the Standard Compression Scheme for Unicode, described in String Encoding .
In double-byte encoding, these are in the form 0xF6yy, 0xF7zz or0xF8zz. When converted to UCS-2, all control codes
should use the 0xFxyy form.
Table 33.3: Common Control Codes for Font Display Information
Value Description Single-Byte Encod-
ingDouble-Byte En-
coding
33.2. Design Discussion 1479Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 33.3 – continued from previous page
0x00 Font Family Select. The subsequent text will be dis-
played in the font speciﬁed by the following byte.0x7F 0x00 0xzz 0xF7zz
0x01 Font Size Select. The subsequent text will be displayed
in the point size, in half points, speciﬁed by the follow-
ing byte.0x7F 0x01 0xzz 0xF8zz
0x20 Bold On. 0x7F 0x20 0xF620
0x21 Bold Off 0x7F 0x21 0xF621
0x22 Italic On 0x7F 0x22 0xF622
0x23 Italic Off 0x7F 0x23 0xF623
0x24 Underline On 0x7F 0x24 0xF624
0x25 Underline Off 0x7F 0x25 0xF625
0x26 Emboss ON 0x7F 0x26 0xF626
0x27 Emboss OFF 0x7F 0x27 0xF627
0x28 Shadow ON 0x7F 0x28 0xF628
0x29 Shadow OFF 0x7F 0x29 0xF629
0x2A DblUnderline ON 0x7F 0x2A 0xF62A
0x2B DblUnderline OFF 0x7F 0x2B 0xF62B
33.2.6.2.5 Line Breaks
This section describes the use of control characters to determine where break opportunities within strings. These
guidelines are based on Unicode Technical Report #14, but are signiﬁcantly simpliﬁed.
Spaces
In general, any of the following space characters is a line-break opportunity:
0020 SPACE
1680 OGHAM SPACE MARK
2000 EN QUAD
2001 EM QUAD
2002 EN SPACE
2003 EM SPACE
2004 THREE-PER-EM SPACE
2005 FOUR-PER-EM SPACE
2006 SIX-PER-EM SPACE
2008 PUNCTUATION SPACE
2009 THIN SPACE
200A HAIR SPACE
205F MEDIUM MATHEMATICAL SPACE
When a space is desired without a line-break opportunity, one of the following spaces should be used:
00A0 NO-BREAK SPACE (NBSP)
202F NARROW NO-BREAK SPACE (NNBSP)
In-Word Break Opportunities
In some cases, allowing line-breaks in a word is desirable. These line break opportunities should be explicitly described
using one of the characters from the following list:
33.2. Design Discussion 1480Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
200B ZERO WIDTH SPACE (ZWSP)
Hyphens
The following characters are hyphens and other characters which describe line break opportunities after the character.
058A ARMENIAN HYPHEN
2010 HYPHEN
2012 FIGURE DASH
2013 EN DASH
0F0B TIBETAN MARK INTERSYLLABIC TSHEG
1361 ETHIOPIC WORDSPACE
17D5 KHMER SIGN BARIYOOSAN
The following characters describe line break opportunities before and after them, but not between a pair of them:
2014 EM DASH
The following characters describe a hyphen which is not a line-breaking opportunity:
2011 NON-BREAKING HYPHEN (NBHY)
The following characters force a line-break:
Table 33.10: Mandatory Breaks
000A NEW LINE
000C FORM FEED
000D CARRIAGE RETURN
2028 LINE SEPARATOR
2029 PARAGRAPH SEPARATOR
33.2.7 Fonts
This section describes how fonts are used within the UEFI environment.
UEFI describes a standard font, which is required for all systems which support text display on bitmapped output
devices. The standard font (named ‘system’) is a ﬁxed pitch font, where all characters are either narrow (8x19) or
wide (16x19). UEFI also allows for display of other fonts, both ﬁxed-pitch and variable-pitch. Platform support for
these fonts is optional.
UEFI fonts are described using either the Simpliﬁed Font Package ( Simpliﬁed Font Package ) or the normal Font
Package ( Font Package ).
33.2. Design Discussion 1481Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.7.1 Font Attributes
Fonts have the following attributes:
Font Name — The font name describes, in broad terms, the visual style of the font. For example, “Arial” or “Times
New Roman” The standard font always has the name “sysdefault”.
Font Size — The font size describes the maximum height of the character cell, in p** — s. The standard font always
has the font size of 19.
Font Style — The font style describes standard visual modiﬁes to the base visual style of a font. Supported font styles
include: bold, italic, underline, double-underline, embossed, outline and shadowed. Some font styles may also be
simulated by the font rendering engine. The standard font always has no additional font styles.
33.2.7.2 Limiting Glyphs
Strings in the UEFI environment can be presented in environments with very different limitations. The most con-
strained environment is in the ﬁrmware phases prior to discovery of a boot device with a system partition. The main
limitation in this environment is storage space. If unexpected strings could be displayed before system partition avail-
ability, the UEFI environment would have to store glyphs for all characters in a Unicode font. After system partition
discovery, all glyphs could be made available.
Careful user interface design can limit to a manageable number, the quantity of unexpected characters that the system
could be called on to display. Knowing what strings the ﬁrmware is going to display limits the number of glyphs it is
required to carry.
In addition, carefully designed ﬁrmware can support a system where a limited number of strings are displayed before
system partition availability. This may be done while enabling the input and display of large numbers of charac-
ters/glyphs using a full font ﬁle stored on the system partition. In such a situation, the designer must ensure that
enough information can be displayed. The designer must also insure that the conﬁguration can be changed using only
information from ﬁrmware-based non-volatile storage to obtain access to a satisfactory system partition.
UEFI requires platform support of a font containing the basic Latin character set.
While the system ﬁrmware will carry this standard font, there might be times when a UEFI application or driver re-
quires the printing of a character not contained within the platform ﬁrmware. In this case, a UEFI driver or application
can carry this font data and add it to the font already present in the HII Database. New font glyphs are accepted when
there is no font glyph deﬁnition for the Unicode character already in the speciﬁed font.
In addition the standard system font and fonts extended by UEFI applications or drivers, it is possible for drivers that
implement the EFI HII Font Glyph Generator Protocol to render additional font glyphs with speciﬁc font name, style,
and size information, and add the new font packages to the HII Database. That is when HII Font Ex searches the glyph
block in the existing HII font packages, it will try to locate EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL
protocol for generating the corresponding glyph block and inserting the new glyph block into HII font package if
the glyph block information is not exist in any HII font package. The HII font package which the new glyph block
inserted can be an existing HII font package or a new HII font package created by HII Font Ex according to the
EFI_FONT_DISPLAY_INFO of character.
The ﬁgure below shows how fonts interact with the HII database and UEFI drivers, even if the font does not already
exist in the database.
33.2. Design Discussion 1482Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.18: Fonts
33.2.7.3 Fixed Font Description

To allow a UEFI application or driver to extend the existing fonts with additional characters, the UEFI driver must be
able to provide characters that ﬁt aesthetically with the system font. For this reason the capability to deﬁne attributes
of different fonts and to suggest a reasonable default target for these parameters is important.
Fonts can vary in width, style, baseline, height, size, and so on. The ﬁxed font deﬁnition includes white space and the
glyph data, as well as the positioning of the glyph data. This prevents characters of different ﬁxed fonts from being
adjusted at runtime to ﬁt aesthetically together. To provide UEFI drivers with a basic description of how to design
ﬁxed font characters, a subset of industry standard font terms are deﬁned below:
baseline — The distance from upper left corner of cell to the base of the Caps (A, B, C,. . . )
cap_height — The distance from the base of the Caps to the top of the Caps
x_height — The distance from the baseline to the top of the lower case ‘x’
descender — The distance some characters extended below the baseline (g, j, p, q, y)
ascender — The distance from the top of the lower case ‘x’ to the tall lower case characters (b, d, f, h, k, l)
The following ﬁgure illustrates the font description terms:
This 8x19 system font example (above), follows the original VGA 8x16 deﬁnition and creating double wide vertical
lines, giving a bold look to the font (style = bold). Along with matching the 8x19 base system font, if a UEFI driver
wants to extend the DBCS (Double Byte Character Set) font, it must be aware of the parameters that describe the
16x19 font, as shown below.
This 16x19 font example (above) has a style of plain (single width vertical lines) instead of bold like the 8x19 font,
since there is not enough horizontal resolution to cleanly deﬁne the DBCS glyphs. The 16x19 ASCII characters have
33.2. Design Discussion 1483Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.19: Font Description Terms
Fig. 33.20: 16 x 19 Font Parameters
33.2. Design Discussion 1484Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
also been designed in a style matching the DBCS characters, allowing them to ﬁt aesthetically together. Note that the
default 16x19 ﬁxed width characters are not stored like 1-bit images, one row after another; but instead stored with the
left column (19 bytes) ﬁrst, followed by the right column (19 bytes) of character data. The ﬁgure below shows how
the characters of the previous ﬁgure would be laid out in the font structure.
Fig. 33.21: Font Structure Layout
33.2.7.3.1 System Fixed Font Design Guidelines
To allow a UEFI application or driver to extend the ﬁxed font character set, the UEFI system fonts must adhere, at
least roughly, to the design guidelines in the table below:
Table 33.11: Guidelines for UEFI System Fonts
Term 8 x 19 Font 16 x 19 Font
baseline 15 pixels 14 pixels
cap_height 12 pixels 11 pixels
x_height 8 pixels 7 pixels
descender 3 pixels 4 pixels
ascender 4 pixels 4 pixels
In the table above lists the terms in priority order. The most critical guideline to match is the baseline, followed by
cap_height and x_height. The terms descender and ascender are not as critical to the aesthetic look of the font as are
the other terms. These font design parameters are only guidelines. Failing to match them will not prevent reasonable
operation of a UEFI driver that attempting to extend the system font.
33.2. Design Discussion 1485Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.7.4 Proportional Fonts Description
Unlike the ﬁxed fonts, proportional fonts do not have a predeﬁned character cell; instead the character cell is created
based on the characters that are being displayed in the current line. In a proportional font only the glyph data is
deﬁned, no whitespace. Instead, the proportional font deﬁnes ﬁve parameters (Width, Height, Offset_X, Offset_Y , &
Advance), which allow the glyph data to be position in the character cell and calculate the origin of the next character.
In the ﬁgure below, you can see these parameters (in ‘[. . . ]’) for the characters shown, in addition you can see the
actual byte storage (the padding to the nearest byte is shown shaded).
Fig. 33.22: Proportional Font Parameters and Byte Padding
To determine font baseline, scan all font glyphs calculating sum of Height and Offset_Y for each glyph. The largest
value of the sum deﬁnes location of the baseline.
The font line height is calculated by adding baseline with the largest by absolute value negative Offset_Y among all
the font glyphs.
33.2.7.4.1 Aligning Glyphs to the Baseline
To display a line of proportional glyphs, baseline andline height have to be determined. If all the characters to be
displayed are from the same font, the baseline and line height are the baseline andline height of the font.
If the characters being displayed are from different fonts, scan glyphs of the characters to be displayed calculating sum
of Height and Offset_Y for each glyph. The largest value of the sum deﬁnes location of the baseline.
Theline height is calculated by adding baseline with the largest by absolute value negative Offset_Y among all the
characters to be displayed.
As shown in the following ﬁgure, once the baseline value is found it is added to the starting position of the line to
calculate the Origin. From the Origin, each and every glyph can be generated based on the individual glyph parameters,
including the calculation of the next glyph’s Origin.
Fig. 33.23: Aligning Glyphs
33.2. Design Discussion 1486Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The starting position (upper left hand corner) of the glyph is deﬁned by (Origin_X + Offset_X), (Origin_Y - (Offset_Y
+ Height)). The Origin of the next glyph is deﬁned by (Origin_X + Advance), (Origin_Y).
In addition to determining the line height and baseline values; the scan of the characters also calculates the line width
by totaling up all of the advance values.
33.2.7.4.2 Proportional Font Design Guidelines
This method of aligning glyphs to a baseline allows one to place wildly different characters correctly position on a
single line. However there still is a need for the system proportional fonts to roughly adhere to overall font height (19
pixels high character cells) and the placement of the baseline at the bottom of the Caps (if applicable or about 5 pixels
up from the bottom of the character cell). These guidelines are not as critical as the ﬁxed font guidelines, since the
character cell height are deﬁned at runtime, based on what else is displayed with that character.
33.2.8 Images
The format of the images to be stored in the Human Interface Infrastructure (HII) database have been created to
conform to the industry standard 1-bit, 4-bit, 8-bit, and 24-bit video memory layouts. The 24-bit and 32-bit display
systems have the exact same display capabilities and the exact same pixel deﬁnition. The difference is that the 32-bit
pixels are DWORD aligned for improve CPU efﬁciency when accessing video memory. The extra byte that is inserted
from the 24-bit and the 32-bit layout has no bearing on the actual screen.
Video memory is arranged left-to-right, and then top-to-bottom. In a 1-bit or monochrome display, the most signiﬁcant
bit of the ﬁrst byte deﬁnes the screen’s upper left most pixel. In a 4-bit or 16 color, display the most signiﬁcant nibble
of the ﬁrst byte deﬁnes the screen’s upper left most pixel. In a 8-bit or 256 color display, the ﬁrst byte deﬁnes the
screen’s upper left most pixel.
In both the 24-bit and 32-bit TrueColor displays, the ﬁrst three bytes deﬁnes the screen’s upper left most pixel. The
ﬁrst byte is the pixel’s blue component value, the next byte is the pixel’s green component value, and the third byte is
the pixel’s red component value (B,G,R). Each color component value can vary from 0x00 (color off) to 0xFF (color
full on), allowing 16.8 millions colors that can be speciﬁed. In the 32-bit TrueColor display modes, the fourth byte is
a don’t care.
33.2.8.1 Converting to a 32-bit Display
The UEFI recommended video mode for computer-like devices uses a 32-bit Linear Frame Buffer video mode. All
images stored in the HII database will need conversion to 32-bit before display.
To display a 24-bit image into 32-bit video memory, a pixel of the image is retrieved (read DWORD value advance
pixel offset by 3) and then written to the video memory (write DWORD value advance pixel offset by 4).
To display any of the non-TrueColor images (1-bit, 4-bit, and 8-bit), there is an extra step of indirection through the
palette deﬁnition to get the TrueColor pixel value. First retrieve the palette index value by isolating the corresponding
bits, then index into the associated palette to retrieve the 24-bit (B,G,R) color entry (read DWORD value), then write it

to the video memory (write DWORD value advance pixel offset by 4). For this reason, the palette color entry deﬁnition
is deﬁned exactly the same as the image color pixel (B,G,R).
33.2. Design Discussion 1487Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.8.2 Non-TrueColor Displays
It is possible to display the HII database images on non-TrueColor video modes. You cannot however, display images
beyond the bit depth of the target screen resolution. For example you would be able to display 1-bit, 4-bit, and 8-bit
images in a 256 color video mode. To do this you must create a global palette (256 entries), by merging all images
color needs to a best ﬁt palette and then programming the hardware palette with that data.
The hardware palette color deﬁnition (R,G,B) is backwards from the screen pixel deﬁnition (B,G,R), and will have
to be swapped before programming. In addition, the hardware palette may only support 6-bit of magnitude per color
component instead of the 8-bit deﬁned in the palette information section; therefore the values will have to be shifted
before writing.
33.2.9 HII Database
The Human Interface Infrastructure (HII) database is the resource that serves as the repository of all the form, string,
image and font data for the system. Drivers that contain information that is appropriate for the database will export
this data to the HII database.
For example, one driver might contain all the motherboard-speciﬁc data (the traditional “Setup” for the system).
Additionally, add-in cards may contain their own drivers, which, in turn, have their own Setup-related data. All of
the drivers that contain Setup-related data would export their information to the HII database, as shown in the ﬁgure
below.
Fig. 33.24: HII Database
33.2.10 Forms Browser
The UEFI Forms Browser is the service that reads the contents of the HII Database and interprets the forms data in
order to present it to the user. For example, the Forms Browser can be used to gather all setup-related data and presents
it to the user. This service also takes the user input and allows for changes to be saved into non-volatile storage.
The ﬁgure below shows the relationship between the HII database, UEFI drivers, and the UEFI Forms Browser.
33.2. Design Discussion 1488Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.25: Setup Browser
33.2.10.1 User Interaction
The Forms Browser implementer has great ﬂexibility as to the type of actual user interface provided. For example,
while required to support some forms of navigation ( EFI_FORM_BROWSER2_PROTOCOL.SendForm() or the cross-
reference question), it may optionally support additional navigation capabilities, such as a back button or a menu bar.
This section describes the rules to which the Forms Browser user-interaction must conform.
33.2.10.1.1 Forms Browser Details
The forms browser maintains a collection of one or more forms. The forms browser is required to provide navigation
for these forms if there is more than one ( EFI_FORM_BROWSER2_PROTOCOL , “Form Browser Protocol”).
The forms browser maintains one or more active forms . An active form is any form where the forms browser is
maintaining a set of question values. A form is considered active after all question values have been read from storage
and the* EFI_BROWSER_ACTION_FORM_OPEN action has been sent to all questions on the form which require
callback. A form is considered inactive after all question values have been either discarded or written to storage
and the EFI_BROWSER_ACTION_FORM_CLOSE action has been sent to all questions on the form which require
callback.
The forms browser maintains a selected form. The selected form contains the selected question and indicates the
primary area of user interaction.
The standards form navigation behaviors are:
Navigate Forms. — When the user chooses this required behavior, a new form is selected and, if any questions on
the form are selectable ( Evaluation of Selectable Statements ), a question is selected. Forms browsers are required
to provide navigation to (at least) the ﬁrst form in all form sets when FormId is zero ( Form Browser Protocol ). This
behavior cannot be selected if the current form is modal (see Forms , “Forms”).
Exit Browser/Discard All. — When the user chooses this optional behavior, the question values for active
33.2. Design Discussion 1489Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
forms are discarded, the active forms are deactivated and the forms browser exits with an action request of
EFI_BROWSER_ACTION_REQUEST_EXIT. This behavior cannot be selected if the current form is modal ( Forms ).
Exit Browser/Submit All. — When the user chooses optional behavior, the question values are writ-
ten to storage, the active forms are deactivated and the forms browser exits with an action request of
EFI_BROWSER_ACTION_REQUEST_SUBMIT orEFI_BROWSER_ACTION_REQUEST_RESET. This behavior
cannot be selected if the current form is modal ( Forms , “Forms”).
Default. — When the user chooses this optional behavior, the current question values for the questions on the focus
form are updated from one of the default stores and then the EFI_IFR_BROWSER_ACTION_REQUEST_DEFAULT_x
action is sent for each of the questions with the Callback attribute. This behavior can be initiated by a Reset Button
question ( Reset Button ).
33.2.10.1.2 Selected Form
When a form is made active, the forms browser sends the EFI_BROWSER_ACTION_FORM_OPEN for all ques-
tions supporting callback, retrieves the current question values, saves those as the original question values and begins
refreshing any questions that support it.
The forms browser maintains a current question value for each question on active forms. The current question value
is the last value that the forms browser read from storage/callback ( Values ) or the last value committed by the user.
The form is considered modiﬁed if any of the current question values are modiﬁed (see Questions, below). The forms
browser refreshes the current question values of at least questions on the selected with a non-zero refresh interval.
The forms browser maintains a selected question on the selected form. The selected question is the primary focus of
the user’s interaction. When a form is selected, the forms browser must choose a selectable question ( Evaluation of
Selectable Statements , “Evaluation of Selectable Statements”) as the selected question, if one is present on the form.
The standard active form behaviors are:
Exit Browser/Discard All. —When the user chooses this required behavior, the question values for active
EFI_BROWSER_ACTION_REQUEST_EXIT . This behavior can be initiated by the function associated with a ques-
tion with the Callback attribute.
Exit Browser/ Submit All. — When the user chooses this required behavior, the current question values for ac-
tive forms are validated (see nosubmitif, EFI_IFR_NOT_EQUAL ) and, if successful, question values for active
forms are written to storage, the active forms are deactivated and the forms browser exits with an action request
ofEFI_BROWSER_ACTION_REQUEST_SUBMIT. This behavior can be initiated by the function associated with a
question with the Callback attribute.
Exit Browser/Discard All/Reset Platform. —When the user chooses this required behavior, the question values
for active forms are discarded, the active forms are deactivated and the form browser exits with an action request
of EFI_BROWSER_ACTION_REQUEST_RESET . This behavior can be initiated by the function associated with a
Exit Form/Submit Form. — Apply Form. When the user chooses this required behavior, the question values for the
selected form are validated (see ->nosubmitif, BUGBUG<-) and, if successful, question values for the selected form
are written to storage and the selected form is deselected. This behavior can be initiated by the function associated
with a question with the Callback attribute.
Exit Form/Discard Form. — When the user chooses this required behavior, the question values for the selected form
are discarded and the selected form is deselected. This behavior can be initiated by the function associated with a
Apply Form. — When the user chooses this required behavior, the question values for the selected form are validated
(see nosubmitif, BUGBUG) and, if successful, question values for the selected form are written to storage. This
behavior can be initiated by the function associated with a question with the Callback attribute.
33.2. Design Discussion 1490Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Discard Form. — When the user chooses this required behavior, the question values for the selected form are
discarded. This behavior can be initiated by the function associated with a question with the Callback attribute.

Default. — When the user chooses this required behavior, the current question values for the questions on the selected
form are updated from a default store. This behavior can be initiated by a Reset Button question (see Reset Button ).
Navigate To Question. — When the user chooses this required behavior, the selected question is deselected and
another question on the same form is selected. The types of navigation provided between questions on the same form
are beyond the scope of this speciﬁcation.
Navigate To Form. — When the user chooses this required behavior, the selected form is deselected and the form
speciﬁed by the question is selected. This behavior can be initiated by a Cross-Reference question. Note that this
behavior is distinct from the Navigate Forms behavior described in Forms Navigation.
From these basic behaviors, more complex behaviors can be constructed. For example, a forms browser might check
whether the form is modiﬁed and, if so, prompt the user to select between the Exit Browser/Discard All and Exit
Browser/Submit All behaviors.
33.2.10.1.3 Selected Question
When the user navigates to a question or the forms browser selects a form with a selectable question, the forms browser
places the question in the static state. When the user is choosing another question values for the selected question (by
typing or from a menu or other means), the forms browser places the question in the changing state. When the user
ﬁnalizes selection of a question value the forms browser returns the question to the static state.
The forms browser refreshes all questions in at least the selected form with a non-zero refresh interval that are not
modiﬁed. Typically, a forms browser will not update the displayed question value while the selected question is in the
changing state, but will when the selected question is in the static state. A question is considered modiﬁed if there
is storage associated with the question (i.e., a variable store was speciﬁed) and the current question value is different
from the original question value.
The standard active question behaviors are:
Change — When the user chooses this required behavior, the forms browser places the selected question in the
changing state and allows the user to specify a new current question value for the active question. For example,
selecting items in a drop box or beginning to type a new value in an edit box.
With some question types and user interface styles, this behavior is hidden from the user. For example, with check
boxes or radio buttons as found in most windowed user-interfaces, the user changes and commits the value with one
action. Likewise, with action buttons, selecting the action button implies both the question value and the commit
action.
This behavior corresponds to the CHANGING browser action request for questions that support callback.
Commit — When the user chooses this required behavior, the forms browser validates the speciﬁed question value
(see EFI_IPF_INCONSISTENT_IF ,EFI_IFR_INCONSISTENT_IF ) and, if successful, places the selected question
in the static state and updates the current question value to that speciﬁed while in the changing state. If the selected
question’s current question value is different than the selected question’s original question value, the selected question
is considered modiﬁed. The form browser must then re-evaluate the modiﬁability, selectability and visibility of other
questions in the selected form.
This behavior corresponds to the CHANGED browser action request for questions that support callback.
Discard — When the user chooses this required behavior, the forms browser places the question in the changed state.
33.2. Design Discussion 1491Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.11 Conﬁguration Settings
In order to save user changes to conﬁguration settings after the system reset or power-off, there must be some form of
non-volatile storage available. There are two types of non-volatile storage: system non-volatile storage or add-in card
non-volatile storage. Both types are supported.
In general, settings are not saved to non-volatile storage until the user speciﬁcally directs the Forms Browser to do so.
There are exceptions, such as when operating in a batch or script mode, setting a system password, and updating the
system date and time. The underlying platform support dictates whether or not hardware conﬁguration changes are
committed immediately.
As shown in the ﬁgure below, when a system reset occurs, the ﬁrmware’s initialization routines will launch the UEFI
drivers (e.g. option ROMs). Drivers enabled to take direction from a non-volatile setting read the updated settings
during their initialization.
Fig. 33.26: Storing Conﬁguration Settings
33.2. Design Discussion 1492Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.11.1 OS Runtime Utilization
Due to the static nature of the data that is contained in the HII Database and the fact that certain classes of non-volatile
storage can be updated during OS run-time, it is possible for an application running under an OS to read the HII
information, make conﬁguration changes and even make changes.
The ﬁgure below shows how an OS makes use of the HII database during runtime. In this case, the contents of the HII
Database is exported to a buffer. The pointer to the buffer is placed in the EFI System Conﬁguration Table, where it
can be retrieved by an OS application.
Fig. 33.27: OS Runtime Utilization
The process used to allow an OS application to use this is as follows:
Drivers/applications in the system register user interface data into the HII Database
When the platform transitions from pre-boot to runtime phases of operation, the HII ExportPackageLists() is called to
export the contents of the HII Database into a runtime buffer.
This runtime buffer is advertised in the UEFI Conﬁguration Table using the HII Database Protocol’s GUID so that an
OS application can ﬁnd the data.
The HII ExportConﬁg() is called to export the current conﬁguration into a runtime buffer.
This runtime buffer is advertised in the UEFI Conﬁguration Table using the HII Conﬁguration Routing Protocol’s
GUID so that an OS application can ﬁnd the data.
When an O/S application wants to display pre-boot conﬁguration content, it searches the UEFI Conﬁguration Table
for the HII Database Protocol’s GUID entry and renders the contents from the runtime buffer which it points to.
If the OS application needs to update the system conﬁguration, the conﬁguration information can be updated.
For those conﬁguration settings which are stored in UEFI variables (i.e., using GetVariable() andSetVariable() ), the
application can update these using the abstraction provided by the operating system.
For those conﬁguration settings which are not stored in UEFI variables, the OS application can use the UEFI Update-
Capsule runtime service to change the conﬁguration.
33.2. Design Discussion 1493Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.2.11.2 Working with a UEFI Conﬁguration Language
By deﬁning the concept of a language that may provide hints to a consumer that the string payload may contain pre-
deﬁned standard keyword content, the user of this solution can export their conﬁguration data for evaluation. This
evaluation enables the consumer to determine if a particular platform supports a given conﬁguration language, and
in-turn be able to adjust known settings that are stored in a platform-speciﬁc manner. An example of this is illustrated
below which uses various component described in this and the other HII chapters of this speciﬁcation. In the example,
a ﬁctional technology called XYZ exists, and this particular platform supports it. The question is, how does a standard
application which is not privy to the platform’s construction know how this setting is stored? To-date, this is not a
reasonably solvable problem, but in the illustration below, this example shows how one might go about solving this
issue.
Fig. 33.28: Standard Application Obtaining Setting Example
33.2.12 Form Callback Logic
Since it has been the design intent that the forms processor not need to understand the underlying hardware imple-
mentations or design paradigms of the platform, there were certain needs that could only be met by calling a more
platform knowledgeable component. In this case, the component would typically be associated with some hardware
device (e.g. motherboard, add-in card, etc.). To facilitate this interaction, some formal interfaces were declared for
more platform-speciﬁc components to advertise and the forms processor could then call.
Note that the need for the forms processor to call into an alternate component driver should be limited as much as
possible. The two primary reasons for this are the cases where off-line or O/S-present conﬁguration is important.
33.2. Design Discussion 1494Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

issue.
The three ﬂow charts which follow describe the typical decisions that a forms processor would make with regards to
handling processes which necessitate a callback.
33.2.13 Driver Model Interaction
The ability for a UEFI driver to interact with a target controller is abstracted through the Conﬁguration Access Protocol.
If a particular piece of hardware managed by a controller needs conﬁguration services, it is the responsibility of that
controller to provide this conﬁguration abstraction for the given device. Regardless of whether a device driver or bus
driver is abstracting the hardware conﬁguration, the interaction with a conﬁgured device is identical.
Note that the ability for a driver to provide these access protocols might be done fairly early in the initialization
process. Depending on the hardware capabilities, one might be advantaged in providing conﬁguration access very
early so that being able to determine a given device’s current settings can be done without a full enumeration of certain
bus devices. Also note that the same recommendations that are made in the DriverBinding sections should still be
maintained. These cover the Supported, Started, and Stopped functions.
33.2.14 Human Interface Component Interactions
The ﬁgure below depicts the model used inside a common deployment of HII to manage human interface components.
33.2.15 Standards Map Forms
Conﬁguration settings are conﬁguration settings. But the way in which they are controlled is driven by different
requirements. For example, the UEFI HII infrastructure focuses primarily on the way in which the conﬁguration
settings can be browsed and manipulated by a user. Other standards such as the DMTF Command-Line Protocol,
focus on the way in which conﬁguration settings can be manipulated via text commands.
Each conﬁguration method tends to view the conﬁguration settings a different way. In the end, they are changing
the same conﬁguration setting, but their means of exposing the control differs. The means by which a conﬁguration
method (HII, DMTF, WMI, SNMP, etc.) exposes an individual conﬁguration setting is called a question.
In many cases, there is a one-to-one mapping between the questions exposed by these different conﬁguration methods.
That is, a question, as exposed by one conﬁguration method matches the semantic meaning of the conﬁguration setting
exactly.
However, in other cases, there is not a one-to-one mapping. These cases break down into three broad categories:
1. Value Shift. In this case, the conﬁguration setting has the same scope as the question exposed by aconﬁguration
method, but the values used to describethem are different. It may be as simple as 1=5, 2=6, 3=7,etc. or something
more complicated, where “ON”=1 and”OFF”=0.**
2. One-To-Many. In this case, the conﬁguration setting maps to two or more questions exposed by a conﬁguration
meth od. For example the conﬁguration setting might have the following enumerated values:
a. 0 = Disable Serial Port
b. 1 = Enable Serial Port, I/O Port 0x3F8, IRQ 4
c. 2 = Enable Serial Port, I/O Port 0x2F8, IRQ 3
d. 3 = Enable Serial Port, I/O Port 0x3E8, IRQ 4
But in the conﬁguration method, the serial port is controlled by three separate questions:
• Question #1: 0 = disable, 1 = enable
33.2. Design Discussion 1495Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.29: Typical Forms Processor Decisions Necessitating a Callback (1)33.2. Design Discussion 1496Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.30: Typical Forms Processor Decisions Necessitatinga Callback (2)
33.2. Design Discussion 1497Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.31: Typical Forms Processor Decisions Necessitatinga Callback (3)33.2. Design Discussion 1498Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.32: Driver Model Interactions
Fig. 33.33: Managing Human Interface Components
33.2. Design Discussion 1499Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• Question #2: I/O Port (disabled if Question #1 = 0)
• Question #3: IRQ (disabled if Question #1 = 0)
Changing the conﬁguration method question #1 to a value of 0 requires that the conﬁguration setting be set to 0. In
this case, there is the possibly of data loss. After changing the conﬁguration setting to 0, the information about the I/O
port and IRQ are not preserved.
So, in order to change the conﬁguration setting to the value of 1 would require three of the conﬁguration method’s
questions to change value: Question #1=1, Question #2=0x3F8, Question #3=IRQ 4.
Fig. 33.34: EFI IFR Form Set conﬁguration
3. Many-To-One. In this case, the conditions are reversed from the example described in #2 above. Now there are
three conﬁguration settings which map to a single conﬁguration method question.
For example, the conﬁguration settings are described using three separate questions:
a. Question #1: 0 = disable, 1 = enable
b. Question #2: I/O Port (disabled if Question #1 = 0)
c. Question #3: IRQ (disabled if Question #1 = 0).
But in the conﬁguration method, the serial port is controlled by a single question with the following enumerated values:
e. 4 = Enable Serial Port, I/O Port 0x2E8, IRQ 3
So, in order to change the conﬁguration method to the value of 1 would require three conﬁguration settings to change
value: Question #1=1, Question #2=0x3F8, Question #3=IRQ 4.
Some conﬁguration settings may involve more than one of these mappings.
33.2. Design Discussion 1500Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.35: EFI IFR Form Set Question Changes
Standards map forms describe the questions exposed by these other conﬁguration methods and how they map back to
the conﬁguration settings exposed by the UEFI drivers. Each standards map form describes the mapping for a single
conﬁguration method, along with that conﬁguration method’s name and version.
The questions within standards map forms are encoded using IFR in the same fashion as those within other UEFI
forms. The prompt strings for these questions are tied back to the names for those questions within the conﬁguration
method (e.g., DMTF CLP).
33.2.15.1 Create A Question’s Value By Combing MultipleConﬁguration Settings
Rather than reading directly from storage, these standards map questions retrieve their value using the EFI_IFR_READ
(EFI_IFR_Read ) operator. This operator can aggregate a value from more than one conﬁguration settings using
EFI_IFR_GET (EFI_IFR_Get ). This operator can also change the type (integer, string, Boolean) of the value so that,
say, a conﬁguration setting with a type of integer can be represented in a standards map form as a string.
For example, to map a single question to three conﬁguration settings (CS1, CS2 and CS3) as described in scenario #3
inStrings , above would have the following truth table:
Table 33.12: Truth Table: Mapping A Single Question To Three Conﬁg-
uration Settings
CS1 CS2 CS3 Q
FALSE X X 0
TRUE 0x3F8 4 1
TRUE 0x2F8 3 2
TRUE 0x3E8 4 3
TRUE 0x2E8 3 4
TRUE any other value any other value Undeﬁned
These become the following equations:
x0: Get (CS1) ? x1 : 0
x1: ((Get(CS2) & 0xF00) >> 8) == Get(CS3) + 1 ? x2 : Undefined
x2: Map(Get(CS2),0x3f8,1,0x2F8,2,0x3E8,3,0x2E8,4)
33.2.15.2 Changing Multiple Conﬁguration Settings FromOne Question’s Value
Rather than writing directly to storage, these standards map questions change their value using the EFI_IFR_WRITE
(EFI_IFR_Write ) operator. This operator can, in turn, use the EFI_IFR_SET (EFI_IFR_Set ) operator to change
one or more conﬁguration settings. This operator can also change the type (integer, string, Boolean, etc.) of the value
written so that, say, a conﬁguration setting with a type of integer can be represented in a standards map form as a string
question.
For example, in example #2 above, the following table applies:
Table 33.13: Multiple Conﬁguration Settings Example #2
FALSE X X 0
TRUE 0x3E8 3 2
TRUE 0x2F8 4 3
TRUE 0x2E8 3 433.2. Design Discussion 1501Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Set (CS1,Q != 0) &&
Set (CS2,Map(this,1,0x3F8,2,0x3E8,3,0x2F8,4,0x2E8)) &&
Set (CS3,Map(this,1,4,2,3,3,4,4,3)
33.2.15.3 Value Shifting
Value shifting is facilitated by the EFI_IFR_MAP ( EFI_IFR_Map ) operator. If this operator ﬁnds a value in a list, it
replaces it with another value from the list, even if the other value is a different type.
For example, consider the following list of values
Table 33.14: Values
1 PEI Module
2 DXE Boot Service Driver
3 DXE Runtime Driver
10 UEFI Boot Service Driver
11 UEFI Runtime Driver
12 UEFI Application
If the integer value 10 were supplied, the value “UEFI Boot Service Driver” would be returned. If the integer value 20

question.
FALSE X X 0
were supplied, Undeﬁned would be returned.
33.2.15.4 Prompts
In standards map forms, the prompts can be used as the key words for the conﬁguration method. They should be
speciﬁed in the language i-ueﬁ unless there are multiple translations available. Other standards may use the question
identiﬁers as the means of identifying the standard question.
33.3 Code Deﬁnitions
This section describes the binary encoding of the different package types:
• Font Package
• Simpliﬁed Font Package
• String Package
• Image Package
• Device Path Package
• Keyboard Layout Package
• GUID Package
• Forms Package
33.3. Code Deﬁnitions 1502Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.1 Package Lists and Package Headers
33.3.1.1 EFI_HII_PACKAGE_HEADER
Summary
The header found at the start of each package.
Prototype
UINT32 Length:24;
UINT32 Type:8;
UINT8 Data[... ];
} EFI_HII_PACKAGE_HEADER;
Members
Length The size of the package in bytes.
Type The package type. See EFI_HII_PACKAGE_TYPE_x, below.
Data The package data, the format of which is determined by Type.
Each package starts with a header, as deﬁned above, which indicates the size and type of the package. When
added to a pointer pointing to the start of the header, Length points at the next package. The package lists form
a package list when concatenated together and terminated with an EFI_HII_PACKAGE_HEADER with a Type of
EFI_HII_PACKAGE_END.
The type EFI_HII_PACKAGE_TYPE_GUID is used for vendor-deﬁned HII packages, whose contents are determined
by the Guid.
The range of package types starting with EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN through
EFI_HII_PACKAGE_TYPE_SYSTEM_END are reserved for system ﬁrmware implementers.
#define EFI_HII_PACKAGE_TYPE_ALL 0x00
#define EFI_HII_PACKAGE_TYPE_GUID 0x01
#define EFI_HII_PACKAGE_FORMS 0x02
#define EFI_HII_PACKAGE_STRINGS 0x04
#define EFI_HII_PACKAGE_FONTS 0x05
#define EFI_HII_PACKAGE_IMAGES 0x06
#define EFI_HII_PACKAGE_SIMPLE_FONTS 0x07
#define EFI_HII_PACKAGE_DEVICE_PATH 0x08
#define EFI_HII_PACKAGE_KEYBOARD_LAYOUT 0x09
#define EFI_HII_PACKAGE_ANIMATIONS 0x0A
#define EFI_HII_PACKAGE_END 0xDF
#define EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN 0xE0
#define EFI_HII_PACKAGE_TYPE_SYSTEM_END 0xFF
Table 33.15: Package Types
Package Type Description
EFI_HII_PACKAGE_TYPE_ALL Pseudo-package type used when exporting package
lists. See ExportPackageList().
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Table 33.15 – continued from previous page
EFI_HII_PACKAGE_TYPE_GUID Package type where the format of the data is speci-
ﬁed using a GUID immediately following the package
header.
EFI_HII_PACKAGE_FORMS Forms package.
EFI_HII_PACKAGE_STRINGS Strings package
EFI_HII_PACKAGE_FONTS Fonts package.
EFI_HII_PACKAGE_IMAGES Images package.
EFI_HII_PACKAGE_SIMPLE_FONTS Simpliﬁed (8x19, 16x19) Fonts package
EFI_HII_PACKAGE_DEVICE_PATH Binary-encoded device path.
EFI_HII_PACKAGE_END Used to mark the end of a package list.
EFI_HII_PACKAGE_ANIMATIONS Animations package.
EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN. . .
EFI_HII_PACKAGE_TYPE_SYSTEM_ENDPackage types reserved for use by platform ﬁrmware
33.3.1.2 EFI_HII_PACKAGE_LIST_HEADER
Summary
The header found at the start of each package list.
Prototype
EFI_GUID PackageListGuid;
UINT32 PackagLength;
} EFI_HII_PACKAGE_LIST_HEADER;
Members
PackageListGuid The unique identiﬁer applied to the list of packages which follows.
PackageLength The size of the package list (in bytes), including the header.
This header uniquely identiﬁes the package list and is placed in front of a list of packages. Package lists with the same
PackageListGuid value should contain the same data set. Updated versions should have updated GUIDs.
33.3.2 Simpliﬁed Font Package
The simpliﬁed font package describes the font glyphs for the standard 8x19 pixel (narrow) and 16x19 (wide) fonts.
Other fonts should be described using the normal Font Package.
A simpliﬁed font package consists of a header and two types of glyph structures–standard-width (narrow) and wide
glyphs.
33.3. Code Deﬁnitions 1504Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.2.1 EFI_HII_SIMPLE_FONT_PACKAGE_HDR
Summary
A simpliﬁed font package consists of a font header followed by a series of glyph structures.
Prototype
typedef struct _EFI_HII_SIMPLE_FONT_PACKAGE_HDR {
EFI_HII_PACKAGE_HEADER Header;
UINT16 NumberOfNarrowGlyphs;
UINT16 NumberOfWideGlyphs;
EFI_NARROW_GLYPH NarrowGlyphs[];
EFI_WIDE_GLYPH WideGlyphs[];
} EFI_HII_SIMPLE_FONT_PACKAGE_HDR;
Members
Header The header contains a Length and Type ﬁeld. In the case of a font package, the type will be
EFI_HII_PACKAGE_SIMPLE_FONTS and the length will be the total size of the font package including the
size of the narrow and wide glyphs. See EFI_HII_PACKAGE_HEADER .
NumberOfNarrowGlyphs The number of NarrowGlyphs that are included in the font package.
NumberOfWideGlyphs The number of WideGlyphs that are included in the font package.
NarrowGlyphs An array of EFI_NARROW_GLYPH entries. The number of entries is speciﬁed by NumberOfNar-
rowGlyphs.
WideGlyphs An array of EFI_WIDE_GLYPH entries. The number of entries is speciﬁed by NumberOfWideG-
lyphs. To calculate the offset of WideGlyphs, use the offset of NarrowGlyphs and add the size of
EFI_NARROW_GLYPH multiplied by the NumberOfNarrowGlyphs.
The glyphs must be sorted by Unicode character code.
It is up to developers who manage fonts to choose efﬁcient mechanisms for accessing fonts. The contiguous presenta-
tion can easily be used because narrow and wide glyphs are not intermixed, so a binary search is possible (hence the
requirement that the glyphs be sorted by weight).
33.3.2.2 EFI_NARROW_GLYPH
Summary
TheEFI_NARROW_GLYPH has a preferred dimension (w x h) of 8 x 19 pixels.
Prototype
CHAR16 UnicodeWeight;
UINT8 GlyphCol1[EFI_GLYPH_HEIGHT];
} EFI_NARROW_GLYPH;
Members
UnicodeWeight The Unicode representation of the glyph. The term weight is the technical term for a character code.
Attributes The data element containing the glyph deﬁnitions; see “Related Deﬁnitions” below.
33.3. Code Deﬁnitions 1505Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GlyphCol1 The column major glyph representation of the character. Bits with values of one indicate that the corre-
sponding pixel is to be on when normally displayed; those with zero are off.
Glyphs are represented by two structures, one each for the two sizes of glyphs. The narrow glyph (
EFI_NARROW_GLYPH ) is the normal glyph used for text display.
// Contents of EFI_NARROW_GLYPH.Attributes
#define EFI_GLYPH_NON_SPACING 0x01
#define EFI_GLYPH_WIDE 0x02
#define EFI_GLYPH_HEIGHT 19
#define EFI_GLYPH_WIDTH 8
Following is a description of the ﬁelds in the above deﬁnition:
EFI_GLYPH_NON_SPACING This symbol is to be printed “on top of” ( OR’d with) the previous glyph beforedis-
play.
EFI_GLYPH_WIDE This symbol uses 16x19 formats rather than 8x19.
33.3.2.3 EFI_WIDE_GLYPH
Summary
TheEFI_WIDE_GLYPH has a preferred dimension (w x h) of 16 x 19 pixels, which is large enough to accommodate
logographic characters.
Prototype
UINT8 GlyphCol2[EFI_GLYPH_HEIGHT];
UINT8 Pad[3];
} EFI_WIDE_GLYPH;
Members
Attributes The data element containing the glyph deﬁnitions; see “Related Deﬁnitions” in EFI_NARROW_GLYPH
for attribute values.
GlyphCol1 and GlyphCol2 The column major glyph representation of the character. Bits with values of one indicate
that the corresponding pixel is to be on when normally displayed; those with zero are off.
Pad Ensures that sizeof (EFI_WIDE_GLYPH) is twice the sizeof (EFI_NARROW_GLYPH). The contents of Padmust
be zero.
Glyphs are represented via the two structures, one each for the two sizes of glyphs. The wide glyph (
EFI_WIDE_GLYPH ) is large enough to display logographic characters.
33.3. Code Deﬁnitions 1506Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.3 Font Package
The font package describes the glyphs for a single font with a single family, size and style. The package has two parts:
a ﬁxed header and the glyph blocks. All structures described here are byte packed.
33.3.3.1 Fixed Header
The ﬁxed header consists of a standard record header and then the character values in this section, the ﬂags (including
the encoding method) and the offsets of the glyph information, the glyph bitmaps and the character map.
typedef struct _EFI_HII_FONT_PACKAGE_HDR {
UINT32 HdrSize;
UINT32 GlyphBlockOffset;
EFI_HII_GLYPH_INFO Cell;
EFI_HII_FONT_STYLE FontStyle;
CHAR16 FontFamily[];
} EFI_HII_FONT_PACKAGE_HDR;

be zero.
Header The standard package header, where Header.Type =EFI_HII_PACKAGE_FONTS.
HdrSize Size of this header.
GlyphBlockOffset The offset, relative to the start of this header, of a series of variable-length glyph blocks, each
describing information about the bitmap associated with a glyph.
Cell This contains the measurement of the widest and tallest characters in the font ( Cell.Width andCell.Height ). It
also contains the default offset to the horizontal and vertical origin point of the character cell ( Cell.OffsetX and
Cell.OffsetY ). Finally, it contains the default AdvanceX.
FontStyle The design style of the font, 1 bit per style. See EFI_HII_FONT_STYLE.
FontFamily The null-terminated string with the name of the font family to which the font belongs.
typedef UINT32 EFI_HII_FONT_STYLE;
#define EFI_HII_FONT_STYLE_NORMAL 0x00000000
#define EFI_HII_FONT_STYLE_BOLD 0x00000001
#define EFI_HII_FONT_STYLE_ITALIC 0x00000002
#define EFI_HII_FONT_STYLE_EMBOSS 0x00010000
#define EFI_HII_FONT_STYLE_OUTLINE 0x00020000
#define EFI_HII_FONT_STYLE_SHADOW 0x00040000
#define EFI_HII_FONT_STYLE_UNDERLINE 0x00080000
#define EFI_HII_FONT_STYLE_DBL_UNDER 0x00100000
33.3.3.2 Glyph Information
For each Unicode character code, the glyph information gives the glyph bitmap, the character size and the position of
the bitmap relative to the origin of the character cell. The glyph information is encoded as a series of blocks, each with
a single byte header. The blocks must be processed in order.
Each block begins with a single byte, which contains the block type.
Prototype
33.3. Code Deﬁnitions 1507Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.36: Glyph Information Encoded in Blocks
33.3. Code Deﬁnitions 1508Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct _EFI_HII_GLYPH_BLOCK {
UINT8 BlockType;
UINT8 BlockBody[];
} EFI_HII_GLYPH_BLOCK;
Members
The following table describes the different block types:
Name Value Description
EFI_HII_GIBT_END 0x00 The end of the glyph information.
EFI_HII_GIBT_GLYPH 0x10 Glyph information for a single character value, bit-
packed.
EFI_HII_GIBT_GLYPHS 0x11 Glyph information for multiple character values.
EFI_HII_GIBT_GLYPH_DEFAULT 0x12
Glyph information for a single character value,
using the default character cell information.
EFI_HII_GIBT_GLYPHS_DEFAULT 0x13
Glyph information for multiple character values, using
the
default character cell information.
EFI_HII_GIBT_GLYPH_V ARIABILITY 0x14 Glyph information for the
_GIBT_GLYPH_V ARIABILITY variable glyph.
EFI_HII_GIBT_DUPLICATE 0x20
Create a duplicate of an existing glyph but
with a new character value.
EFI_HII_GIBT_SKIP2 0x21 Skip a number (1-65535) character values.
EFI_HII_GIBT_SKIP1 0x22 Skip a number (1-255) character values.
EFI_HII_GIBT_DEFAULTS 0x23 Set default glyph information for subsequent glyph
blocks.
EFI_HII_GIBT_EXT1 0x30 For future expansion (one byte length ﬁeld)
EFI_HII_GIBT_EXT2 0x31 For future expansion (two byte length ﬁeld)
EFI_HII_GIBT_EXT4 0x32 For future expansion (four byte length ﬁeld)
In order to recreate all glyphs, start at the ﬁrst block and process them all until a EFI_HII_GIBT_END block is found.
When processing the glyph blocks, each block refers to the current character value ( CharValueCurrent ), which is
initially set to one (1).
Glyph blocks of an unknown type should be skipped. If they cannot be skipped, then processing halts.
typedef struct _EFI_HII_GLYPH_INFO {
UINT16 Width;
UINT16 Height;
INT16 OffsetX;
INT16 OffsetY;
INT16 AdvanceX;
} EFI_HII_GLYPH_INFO;
33.3. Code Deﬁnitions 1509Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.37: Glyph Block Processing
33.3. Code Deﬁnitions 1510Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Width Width of the character or character cell, in pixels. For ﬁxed-pitch fonts, this is the same as the advance.
Height Height of the character or character cell, in pixels.
OffsetX Offset to the horizontal edge of the character cell.
OffsetY Offset to the vertical edge of the character cell.
AdvanceX Number of pixels to advance to the right when moving from the origin of the current glyph to the origin
of the next glyph.
33.3.3.2.1 EFI_HII_GIBT_DEFAULTS
Summary
Changes the default character cell information.
Prototype
typedef struct _EFI_HII_GIBT_DEFAULTS_BLOCK {
EFI_HII_GLYPH_BLOCK Header;
} EFI_HII_GIBT_DEFAULTS_BLOCK;
Members
Header Standard glyph block header, where Header.BlockType =EFI_HII_GIBT_DEFAULTS.
Cell The new default cell information which will be applied to all subsequent GLYPH_DEFAULT and
GLYPHS_DEFAULT blocks.
Changes the default cell information used for subsequent EFI_HII_GIBT_GLYPH_DEFAULT and
EFI_HII_GIBT_GLYPHS_DEFAULT glyph blocks. The cell information described by Cell remains in effect
until the next EFI_HII_GIBT_DEFAULTS is found. Prior to the ﬁrst EFI_HII_GIBT_DEFAULTS block, the cell
information in the ﬁxed header are used.
33.3.3.2.2 EFI_HII_GIBT_DUPLICATE
Summary
Assigns a new character value to a previously deﬁned glyph.
Prototype
typedef struct _EFI_HII_GIBT_DUPLICATE_BLOCK {
CHAR16 CharValue;
} EFI_HII_GIBT_DUPLICATE_BLOCK;
Members
Header Standard glyph block header, where Header.BlockType =EFI_HII_GIBT_DUPLICATE.
CharValue The previously deﬁned character value with the exact same glyph.
Indicates that the glyph with character value CharValueCurrent has the same glyph as a previously deﬁned character
value and increments CharValueCurrent by one.
33.3. Code Deﬁnitions 1511Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.3.2.3 EFI_HII_GIBT_END
Summary
Marks the end of the glyph information.
Prototype
typedef struct _EFI_GLYPH_GIBT_END_BLOCK {
} EFI_GLYPH_GIBT_END_BLOCK;
Members
Header Standard glyph block header, where Header.BlockType =EFI_HII_GIBT_END.
Any glyphs with a character value greater than or equal to CharValueCurrent are empty.
33.3.3.2.4 EFI_HII_GIBT_EXT1, EFI_HII_GIBT_EXT2,EFI_HII_GIBT_EXT4
Summary
Future expansion block types which have a length byte.
Prototype
typedef struct _EFI_HII_GIBT_EXT1_BLOCK {
UINT8 BlockType2;
} EFI_HII_GIBT_EXT1_BLOCK;
typedef struct _EFI_HII_GIBT_EXT2_BLOCK {
} EFI_HII_GIBT_EXT2_BLOCK;
typedef struct _EFI_HII_GIBT_EXT4_BLOCK {
} EFI_HII_GIBT_EXT4_BLOCK;
Members
Header Standard glyph block header, where Header.BlockType =EFI_HII_GIBT_EXT1, EFI_HII_GIBT_EXT2 or
EFI_HII_GIBT_EXT4.
Length Size of the glyph block, in bytes.
BlockType2 Indicates the type of extended block. Currently all extended block types are reserved for future expan-
sion.
These are reserved for future expansion, with length bytes included so that they can be easily skipped.
33.3. Code Deﬁnitions 1512Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.3.2.5 EFI_HII_GIBT_GLYPH
Summary
Provide the bitmap for a single glyph.
Prototype
typedef struct _EFI_HII_GIBT_GLYPH_BLOCK {
UINT8 BitmapData[1];
} EFI_HII_GIBT_GLYPH_BLOCK;
Members
Header Standard glyph block header, where Header.BlockType =EFI_HII_GIBT_GLYPH.
Cell Contains the width and height of the encoded bitmap ( Cell.Width andCell.Height ), the number of pixels (signed)
right of the character cell origin where the left edge of the bitmap should be placed ( Cell.OffsetX ), the number
of pixels above the character cell origin where the top edge of the bitmap should be placed ( Cell.OffsetY ) and
the number of pixels (signed) to move right to ﬁnd the origin for the next character cell ( Cell.AdvanceX ).
GlyphCount The number of glyph bitmaps.
BitmapData The bitmap data speciﬁes a series of pixels, one bit per pixel, left-to-right, top-to-bottom. Each glyph
bitmap only encodes the portion of the bitmap enclosed by its character-bounding box, but the entire glyph is
padded out to the nearest byte. The number of bytes per bitmap can be calculated as: (( Cell.Width + 7)/8) *
Cell.Height.
This block provides the bitmap for the character with the value CharValueCurrent and increments CharValueCurrent
by one. Each glyph contains a glyph width and height, a drawing offset, number of pixels to advance after drawing
and then the encoded bitmap.
33.3.3.2.6 EFI_HII_GIBT_HII_GLYPHS
Summary
Provide the bitmaps for multiple glyphs with the same cell information
Prototype
typedef struct _EFI_HII_GIBT_GLYPHS_BLOCK {
UINT16 Count
} EFI_HII_GIBT_GLYPHS_BLOCK;
Members
Header Standard glyph block header, where Header.BlockType =EFI_HII_GIBT_GLYPHS.

Summary
Prototype
Members
33.3. Code Deﬁnitions 1513Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
BitmapData The bitmap data speciﬁes a series of pixels, one bit per pixel, left-to-right, top-to-bottom, for each glyph.
Each glyph bitmap only encodes the portion of the bitmap enclosed by its character-bounding box. The number
of bytes per bitmap can be calculated as: (( Cell.Width + 7)/8) *Cell.Height.
Provides the bitmaps for the characters with the values CharValueCurrent through CharValueCurrent +Count -1 and
increments CharValueCurrent byCount. These glyphs have identical cell information and the encoded bitmaps are
exactly the same number of byes.
33.3.3.2.7 EFI_HII_GIBT_GLYPH_DEFAULT
Summary
Provide the bitmap for a single glyph, using the default cell information.
Prototype
typedef struct _EFI_HII_GIBT_GLYPH_DEFAULT_BLOCK {
UINT8 BitmapData[];
} EFI_HII_GIBT_GLYPH_DEFAULT_BLOCK;
Members
Header Standard glyph block header, where Header.BlockType =EFI_HII_GIBT_GLYPH_DEFAULT.
bitmap only encodes the portion of the bitmap enclosed by its character-bounding box. The number of bytes per
bitmap can be calculated as: (( Global.Cell.Width + 7)/8) *Global.Cell.Height.
Provides the bitmap for the character with the value CharValueCurrent and increments CharValueCurrent by 1. This
glyph uses the default cell information. The default cell information is found in the font header or the most recently
processed EFI_HII_GIBT_DEFAULTS.
33.3.3.2.8 EFI_HII_GIBT_GLYPHS_DEFAULT
Summary
Provide the bitmaps for multiple glyphs with the default cell information
Prototype
typedef struct _EFI_HII_GIBT_GLYPHS_DEFAULT_BLOCK {
UINT16 Count;
UINT8 BitmapData [];
} EFI_HII_GIBT_GLYPHS_DEFAULT_BLOCK;
**Members**
Header Standard glyph block header, where Header.BlockType =EFI_HII_GIBT_GLYPHS_DEFAULT.
Count Number of glyphs in the glyph block.
33.3. Code Deﬁnitions 1514Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
of bytes per bitmap can be calculated as: (( Global.Cell.Width + 7)/8) *Global.Cell.Height.
increments CharValueCurrent byCount. These glyphs use the default cell information and the encoded bitmaps have
33.3.3.2.9 EFI_HII_GIBT_SKIPx
Summary
Increments the current character value CharValueCurrent by the number speciﬁed.
Prototype
typedef struct _EFI_HII_GIBT_SKIP2_BLOCK {
UINT16 SkipCount;
} EFI_HII_GIBT_SKIP2_BLOCK;
typedef struct _EFI_HII_GIBT_SKIP1_BLOCK {
UINT8 SkipCount;
} EFI_HII_GIBT_SKIP1_BLOCK;
Members
Header Standard glyph block header, where BlockType =EFI_HII_GIBT_SKIP1 orEFI_HII_GIBT_SKIP2.
SkipCount The unsigned 8- or 16-bit value to add to CharValueCurrent .
33.3.3.2.10 EFI_HII_GIBT_GLYPH_VARIABILITY
// EFI_HII_GIBT_GLYPH_VARIABILITY (0x14)
typedef struct _EFI_HII_GIBT_VARIABILITY_BLOCK {
UINT8 GlyphPackInBits;
UINT8 BitmapData [1];
} EFI_HII_GIBT_VARIABILITY_BLOCK;
Members
Header Standard glyph block header, where Blocktype = EFI_HII_GIBT_GLYPH_V ARIABILITY .
Cell Contains the width and height of the encoded bitmap (Cell.Width and Cell.Height), the number of pixels (signed)
right of the character cell origin where the left edge of the bitmap should be placed (Cell.OffsetX), the number
33.3. Code Deﬁnitions 1515Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
of pixels above the character cell origin where the top edge of the bitmap should be placed (Cell.OffsetY) and
the number of pixels (signed) to move right to ﬁnd the origin for the next character cell (Cell.AdvanceX).
GlyphPackInBits This describes the bit length for each pixel in glyph. With this, the length of BitmapData can be
determined according to GlyphPackInBits, cell.with and cell.height.
The valid value is GIBT_V ARIABILITY_BLOCK_1_BIT,
GIBT_VARIABILITY_BLOCK_2_BIT,
GIBT_VARIABILITY_BLOCK_4_BIT,
GIBT_VARIABILITY_BLOCK_8_BIT,
GIBT_VARIABILITY_BLOCK_16_BIT,
GIBT_VARIABILITY_BLOCK_24_BIT,
GIBT_VARIABILTY_BLOCK_32_BIT
HII Font Ex protocol has no idea about how to decode the bitmap of glyph if the glyph
is declared as EFI_HII_GIBT_GLYPH_VARIABLITY. The bitmap decoding is resolved in
EFI_HII_FONT_GLPHY_GENERATOR_PROTOCOL. This ﬁeld is used to determine the length of en-
tire glyph block.
BitmapData The raw data of the glyph pixels. The format of the glyph pixel depends on the glyph generator. Only
EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL knows how to draw the glyph.
Fig. 33.38: EFI_HII_GIBT_GLYPH_V ARIABLITY Glyph Drawing Processing
33.3. Code Deﬁnitions 1516Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.4 Device Path Package
Summary
The device path package is used to carry a device path associated with the package list.
Prototype
typedef struct _EFI_HII_DEVICE_PATH_PACKAGE {
//EFI_DEVICE_PATH_PROTOCOL DevicePath [];
} EFI_HII_DEVICE_PATH_PACKAGE;
Header The standard package header, where Header.Type = EFI_HII_PACKAGE_DEVICE_PATH.
DevicePath The Device Path description associated with the driver handle that provided the content sent to the HII
database.
This package is created by NewPackageList() when the package list is ﬁrst added to the HII database by locating the
EFI_DEVICE_PATH_PROTOCOL attached to the driver handle passed in to that function.
33.3.5 GUID Package
The GUID package is used to carry data where the format is deﬁned by a GUID.
Prototype
typedef struct _EFI_HII_GUID_PACKAGE_HDR {
EFI_GUID Guid;
// Data per GUID definition may follow
} EFI_HII_GUID_PACKAGE_HDR;
Members
Header The standard package header, where Header.Type =EFI_HII_PACKAGE_TYPE_GUID.
Guid Identiﬁer which describes the remaining data within the package.
This is a free-form package type designed to allow extensibility by allowing the format to be speciﬁed using Guid. .
33.3.6 String Package
The Strings package record describes the mapping between string identiﬁers and the actual text of the strings them-
selves. The package consists of three parts: a ﬁxed header, the string information and the font information.
33.3. Code Deﬁnitions 1517Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.6.1 Fixed Header
The ﬁxed header consists of a standard record header and then the string identiﬁers contained in this section and the
offsets of the string and language information.
Prototype
typedef struct _EFI_HII_STRING_PACKAGE_HDR {
UINT32 StringInfoOffset;
CHAR16 LanguageWindow[16];
EFI_STRING_ID LanguageName;
CHAR8 Language [... ];
} EFI_HII_STRING_PACKAGE_HDR;
Members
Header The standard package header, where Header.Type =EFI_HII_PACKAGE_STRINGS.
StringInfoOffset Offset, relative to the start of this header, of the string information.
LanguageWindow Speciﬁes the default values placed in the static and dynamic windows before processing each
SCSU-encoded string.
LanguageName String identiﬁer within the current string package of the full name of the language speciﬁed by
Language .
Language The null-terminated ASCII string that speciﬁes the language of the strings in the package. The languages
are described as speciﬁed by Formats — Language Codes and Language Code Arrays .
#define UEFI_CONFIG_LANG "x-UEFI"
#define UEFI_CONFIG_LANG_2 "x-i-UEFI"
33.3.6.2 String Information
For each string identiﬁer, the string information gives the string’s text and font. The string information is encoded
as a series of blocks, each with a single byte header. The blocks must be processed in order, using the current string

Language .
identiﬁer ( StringIdCurrent ), which is set initially to one (1). Processing continues until an EFI_SIBT_END block is
found.
The types of blocks are: string blocks, duplicate blocks, font blocks, and skip blocks. String blocks specify the text
and font for the current string identiﬁer and increment to the next string identiﬁer. Duplicate blocks copy the text of
a previous string identiﬁer and increment to the next string identiﬁer. Skip bocks skip string identiﬁers, leaving them
blank.
} EFI_HII_STRING_BLOCK;
33.3. Code Deﬁnitions 1518Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.39: String Information Encoded in Blocks
33.3. Code Deﬁnitions 1519Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_HII_SIBT_END 0x00 The end of the string information.
EFI_HII_SIBT_STRING_SCSU 0x10 Single string using default font information.
EFI_HII_SIBT_STRING_SCSU_FONT 0x11 Single string with font information.
EFI_HII_SIBT_STRINGS_SCSU 0x12 Multiple strings using default font information.
EFI_HII_SIBT_STRINGS_SCSU_FONT 0x13 Multiple strings with font information.
EFI_HII_SIBT_STRING_UCS2 0x14 Single UCS-2 string using default font information.
EFI_HII_SIBT_STRING_UCS2_FONT 0x15 Single UCS-2 string with font information
EFI_HII_SIBT_STRINGS_UCS2 0x16 Multiple UCS-2 strings using default font information.
EFI_HII_SIBT_STRINGS_UCS2_FONT 0x17 Multiple UCS-2 strings with font information.
EFI_HII_SIBT_DUPLICATE 0x20 Create a duplicate of an existing string.
EFI_HII_SIBT_SKIP2 0x21 Skip a certain number of string identiﬁers.
EFI_HII_SIBT_SKIP1 0x22 Skip a certain number of string identiﬁers.
EFI_HII_SIBT_EXT1 0x30 For future expansion (one byte length ﬁeld)
EFI_HII_SIBT_EXT2 0x31 For future expansion (two byte length ﬁeld)
EFI_HII_SIBT_EXT4 0x32 For future expansion (four byte length ﬁeld)
EFI_HII_SIBT_FONT 0x40 Font information.
When processing the string blocks, each block type refers and modiﬁes the current string identiﬁer ( StringIdCurrent
).
33.3.6.2.1 EFI_HII_SIBT_DUPLICATE
Summary
Creates a duplicate of a previously deﬁned string.
Prototype
typedef struct _EFI_HII_SIBT_DUPLICATE_BLOCK {
EFI_HII_STRING_BLOCK Header;
} EFI_HII_SIBT_DUPLICATE_BLOCK;
Members
Header Standard string block header, where Header.BlockType = EFI_HII_SIBT_DUPLICATE.
StringId The string identiﬁer of a previously deﬁned string with the exact same string text.
Indicates that the string with string identiﬁer StringIdCurrent is the same as a previously deﬁned string and increments
StringIdCurrent by one.
33.3. Code Deﬁnitions 1520Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.40: String Block Processing: Base Processing
33.3. Code Deﬁnitions 1521Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.41: String Block Processing: SCSU Processing
33.3.6.2.2 EFI_HII_SIBT_END
Summary
Marks the end of the string information.
Prototype
typedef struct _EFI_HII_SIBT_END_BLOCK {
} EFI_HII_SIBT_END_BLOCK;
Members
Header Standard extended header, where Header.Header.BlockType =EFI_HII_SIBT_EXT2 andHeader.BlockType2
=EFI_HII_SIBT_FONT.
BlockType2 Indicates the type of extended block. See String Information for a list of all block types.
Any strings with a string identiﬁer greater than or equal to StringIdCurrent are empty.
33.3. Code Deﬁnitions 1522Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.42: String Block Processing: UTF Processing
33.3. Code Deﬁnitions 1523Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.6.2.3 EFI_HII_SIBT_EXT1, EFI_HII_SIBT_EXT2,EFI_HII_SIBT_EXT4
Summary
Prototype
typedef struct _EFI_HII_SIBT_EXT1_BLOCK {
} EFI_HII_SIBT_EXT1_BLOCK;
typedef struct _EFI_HII_SIBT_EXT2_BLOCK {
} EFI_HII_SIBT_EXT2_BLOCK;
typedef struct _EFI_HII_SIBT_EXT4_BLOCK {
} EFI_HII_SIBT_EXT4_BLOCK;
Members
Header Standard string block header, where Header.BlockType = EFI_HII_SIBT_EXT1, EFI_HII_SIBT_EXT2 or
EFI_HII_SIBT_EXT4.
Length Size of the string block, in bytes.
33.3.6.2.4 EFI_HII_SIBT_FONT
Summary
Provide information about a single font.
Prototype
typedef struct _EFI_HII_SIBT_FONT_BLOCK {
EFI_HII_SIBT_EXT2_BLOCK Header;
UINT8 FontId;
UINT16 FontSize;
CHAR16 FontName[...];
} EFI_HII_SIBT_FONT_BLOCK;
Members
Header Standard extended header, where Header.BlockType2 =EFI_HII_SIBT_FONT.
FontId Font identiﬁer, which must be unique within the string package.
33.3. Code Deﬁnitions 1524Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
FontSize Character cell size, in pixels, of the font.
FontStyle Font style. Type EFI_HII_FONT_STYLE is deﬁned in “Related Deﬁnitions” in
EFI_HII_FONT_PACKAGE_HDR.
FontName Null-terminated font family name.
Associates a font identiﬁer FontId with a font name FontName, sizeFontSize and style FontStyle. This font identiﬁer
may be used with the string blocks. The font identiﬁer 0 is the default font for those string blocks which do not specify
a font identiﬁer.
33.3.6.2.5 EFI_HII_SIBT_SKIP1
Summary
Skips string identiﬁers.
Prototype
typedef struct _EFI_HII_SIBT_SKIP1_BLOCK {
} EFI_HII_SIBT_SKIP1_BLOCK;
Members
Header Standard string block header, where Header.BlockType = EFI_HII_SIBT_SKIP1.
SkipCount The unsigned 8-bit value to add to StringIdCurrent.
Increments the current string identiﬁer StringIdCurrent by the number speciﬁed.
33.3.6.2.6 EFI_HII_SIBT_SKIP2
Summary
Skips string ids.
Prototype
typedef struct _EFI_HII_SIBT_SKIP2_BLOCK {
} EFI_HII_SIBT_SKIP2_BLOCK;
Members
Header Standard string block header, where Header.BlockType =EFI_HII_SIBT_SKIP2.
SkipCount The unsigned 16-bit value to add to StringIdCurrent.
33.3. Code Deﬁnitions 1525Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.6.2.7 EFI_HII_SIBT_STRING_SCSU
Summary
Describe a string encoded using SCSU, in the default font.
Prototype
typedef struct _EFI_HII_SIBT_STRING_SCSU_BLOCK {
UINT8 StringText[];
} EFI_HII_SIBT_STRING_SCSU_BLOCK;
Members
Header Standard header where Header.BlockType =EFI_HII_SIBT_STRING_SCSU.
StringText The string text is a null-terminated string, which is assigned to the string identiﬁer StringIdCurrent.
This string block provides the SCSU-encoded text for the string in the default font with string identiﬁer StringIdCurrent
and increments StringIdCurrent by one.
33.3.6.2.8 EFI_HII_SIBT_STRING_SCSU_FONT
Summary
Describe a string in the speciﬁed font.
Prototype
typedef struct _EFI_HII_SIBT_STRING_SCSU_FONT_BLOCK {
UINT8 FontIdentifier;
} EFI_HII_SIBT_STRING_SCSU_FONT_BLOCK;
Members
Header Standard string block header, where Header.BlockType = EFI_HII_SIBT_STRING_SCSU_FONT.
FontIdentiﬁer The identiﬁer of the font to be used as the starting font for the entire string. The identiﬁer must
either be 0 for the default font or an identiﬁer previously speciﬁed by an EFI_HII_SIBT_FONT block. Any
string characters that deviates from this font family, size or style must provide an explicit control character. See
Common Control Codes .
StringText The string text is a null-terminated encoded string, which is assigned to the string identiﬁer StringIdCur-
rent.
This string block provides the SCSU-encoded text for the string in the font speciﬁed by FontIdentiﬁer with string
identiﬁer StringIdCurrent and increments StringIdCurrent by one.
33.3. Code Deﬁnitions 1526Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.6.2.9 EFI_HII_SIBT_STRINGS_SCSU
Summary
Describe strings in the default font.
Prototype
typedef struct _EFI_HII_SIBT_STRINGS_SCSU_BLOCK {
UINT16 StringCount;
} EFI_HII_SIBT_STRINGS_SCSU_BLOCK;
Members
Header Standard header where Header.BlockType =EFI_HII_SIBT_STRINGS_SCSU
StringCount Number of strings in StringText.
StringText The strings, where each string is a null-terminated encoded string.

rent.
Summary
Prototype
Members
This string block provides the SCSU-encoded text for StringCount strings which have the default font and which have
sequential string identiﬁers. The strings are assigned the identiﬁers, starting with StringIdCurrent and continuing
through StringIdCurrent +StringCount - 1. StringIdCurrent is incremented by StringCount.
33.3.6.2.10 EFI_HII_SIBT_STRINGS_SCSU_FONT
Summary
Describe strings in the speciﬁed font.
Prototype
typedef struct _EFI_HII_SIBT_STRINGS_SCSU_FONT_BLOCK {
} EFI_HII_SIBT_STRINGS_SCSU_FONT_BLOCK;
Members
Header Standard header where Header.BlockType =EFI_HII_SIBT_STRINGS_SCSU_FONT.
This string block provides the SCSU-encoded text for StringCount strings which have the font speciﬁed by FontIdenti-
ﬁerand which have sequential string identiﬁers. The strings are assigned the identiﬁers, starting with StringIdCurrent
and continuing through StringIdCurrent +StringCount - 1.StringIdCurrent is incremented by StringCount.
33.3. Code Deﬁnitions 1527Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.6.2.11 EFI_HII_SIBT_STRING_UCS2
Summary
Describe a string in the default font.
Prototype
typedef struct _EFI_HII_SIBT_STRING_UCS2_BLOCK {
CHAR16 StringText[];
} EFI_HII_SIBT_STRING_UCS2_BLOCK;
Members
Header Standard header where Header.BlockType =EFI_HII_SIBT_STRING_UCS2.
StringText The string text is a null-terminated UCS-2 string, which is assigned to the string identiﬁer StringIdCurren
t.
This string block provides the UCS-2 encoded text for the string in the default font with string identiﬁer StringIdCur-
rentand increments StringIdCurrent by one.
33.3.6.2.12 EFI_HII_SIBT_STRING_UCS2_FONT
Summary
Prototype
typedef struct _EFI_HII_SIBT_STRING_UCS2_FONT_BLOCK {
} EFI_HII_SIBT_STRING_UCS2_FONT_BLOCK;
Members
Header Standard header where Header.BlockType =EFI_HII_SIBT_STRING_UCS2_FONT.
StringText The string text is a null-terminated UCS-2 string, which is assigned to the string identiﬁer StringIdCurrent.
This string block provides the UCS-2 encoded text for the string in the font speciﬁed by FontIdentiﬁer with string
33.3. Code Deﬁnitions 1528Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.6.2.13 EFI_HII_SIBT_STRINGS_UCS2
Summary
Describes strings in the default font.
Prototype
typedef struct _EFI_HII_SIBT_STRINGS_UCS2_BLOCK {
} EFI_HII_SIBT_STRINGS_UCS2_BLOCK;
Members
Header Standard header where Header.BlockType =EFI_HII_SIBT_STRINGS_UCS2.
StringText The string text is a series of null-terminated UCS-2 strings, which are assigned to the string identiﬁers
StringIdCurren t.toStringIdCurrent +StringCount - 1 .
This string block provides the UCS-2 encoded text for the strings in the default font with string identiﬁers StringId-
Current toStringIdCurrent +StringCount - 1 and increments StringIdCurrent byStringCount.
33.3.6.2.14 EFI_HII_SIBT_STRINGS_UCS2_FONT
Summary
Describes strings in the speciﬁed font.
Prototype
typedef struct _EFI_HII_SIBT_STRINGS_UCS2_FONT_BLOCK {
} EFI_HII_SIBT_STRINGS_UCS2_FONT_BLOCK;
Members
Header Standard header where Header.BlockType =EFI_HII_SIBT_STRINGS_UCS2_FONT.
StringIdCurren t.through StringIdCurrent +StringCount - 1.
This string block provides the UCS-2 encoded text for the strings in the font speciﬁed by FontIdentiﬁer with string
identiﬁers StringIdCurrent toStringIdCurrent +StringCount - 1 and increments StringIdCurrent byStringCount.
33.3. Code Deﬁnitions 1529Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.6.3 String Encoding
Each of the following sections describes part of how string text is encoded.
33.3.6.3.1 Standard Compression Scheme for Unicode (SCSU)
The Unicode consortium provides a standard text compression algorithm, which minimizes the amount of stor-
age required for multiple-language strings. For more information, see “Links to UEFI-Related Documents” (
http://ueﬁ.org/ueﬁ) under the heading “Unicode Compression Scheme”.
This speciﬁcation extends the technique described in the following ways:
• The strings use the control code 0x7F to introduce the control codes described in Common Control Codes . The
following byte is the control code. The character value 0x7F will be encoded as 0x01 (SQ0) 0x7F.
• The language information contains default static and dynamic code windows, whereas SCSU provides ﬁxed
values for these.
• Characters between 0xF000 and 0xFCFF should be rejected.
33.3.6.3.2 Unicode 2-Byte Encoding (UCS-2)
The Unicode consortium provides a standard encoding algorithm, which takes two bytes per character. For more
information see “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) under the heading “Unicode Consortium”.
Characters between 0xF000 and 0xFCFF should be rejected.
33.3.7 Image Package
The Image package record describes the mapping between image identiﬁers and the pixels of the image themselves.
The package consists of three parts: a ﬁxed header, image information and the palette information.
33.3.7.1 Fixed Header
Summary
The ﬁxed header consists of a standard record header and the offsets of the image and palette information.
Prototype
typedef struct _EFI_HII_IMAGE_PACKAGE_HDR {
UINT32 ImageInfoOffset;
UINT32 PaletteInfoOffset;
} EFI_HII_IMAGE_PACKAGE_HDR;
Members
Header Standard package header, where Header.Type =EFI_HII_PACKAGE_IMAGES.
ImageInfoOffset Offset, relative to this header, of the image information. If this is zero, then there are no images in
the package.
PaletteInfoOffset Offset, relative to this header, of the palette information. If this is zero, then there are no palettes
in the image package.
33.3. Code Deﬁnitions 1530Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.7.2 Image Information
For each image identiﬁer, the image information gives the bitmap and the relevant palette. The image information is
encoded as a series of blocks, each with a single byte header. The blocks must be processed in order. Each block
begins with a single byte, which contains the block type.
Fig. 33.43: Image Information Encoded in Blocks
Prototype
typedef struct _EFI_HII_IMAGE_BLOCK {
} EFI_HII_IMAGE_BLOCK;
33.3. Code Deﬁnitions 1531Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 33.18: Block Types
EFI_HII_IIBT_END 0x00 The end of the image information.
EFI_HII_IIBT_IMAGE_1BIT 0x10 1-bit w/palette
EFI_HII_IIBT_IMAGE_1BIT_TRANS 0x11 1-bit w/palette & transparency
EFI_HII_IIBT_IMAGE_4BIT 0x12 4-bit w/palette
EFI_HII_IIBT_IMAGE_4BIT_TRANS 0x13 4-bit w/palette & transparency
EFI_HII_IIBT_IMAGE_8BIT 0x14 8-bit w/palette
EFI_HII_IIBT_IMAGE_8BIT_TRANS 0x15 8-bit w/palette & transparency
EFI_HII_IIBT_IMAGE_24BIT 0x16 24-bit RGB
EFI _HII_IIBT_IMAGE_24BIT_TRANS 0x17 24-bit RGB w/transparency
EFI_HII_IIBT_IMAGE_JPEG 0x18 JPEG encoded image
EFI_HII_IIBT_IMAGE_PNG 0x19 PNG encoded image
EFI_HII_IIBT_DUPLICATE 0x20 Duplicate an existing image identiﬁer
EFI_HII_IIBT_SKIP2 0x21 Skip a certain number of image identiﬁers.
EFI_HII_IIBT_SKIP1 0x22 Skip a certain number of image identiﬁers.

EFI_HII_IIBT_EXT1 0x30 For future expansion (one byte length ﬁeld)
EFI_HII_IIBT_EXT2 0x31 For future expansion (two byte length ﬁeld)
EFI_HII_IIBT_EXT4 0x32 For future expansion (four byte length ﬁeld)
In order to recreate all images, start at the ﬁrst block and process them all until an EFI_HII_IIBT_END_BLOCK block
is found. When processing the image blocks, each block refers to the current image identiﬁer ( ImageIdCurrent ),
which is initially set to one (1).
Image blocks of an unknown type should be skipped. If they cannot be skipped, then processing halts.
33.3.7.2.1 EFI_HII_IIBT_END
Summary
Marks the end of the image information.
Prototype
# define EFI_HII_IIBT_END 0x00
typedef struct _EFI_HII_IIBT_END_BLOCK {
EFI_HII_IMAGE_BLOCK Header;
} EFI_HII_IIBT_END_BLOCK;
Members
Header Standard image block header, where Header.BlockType =EFI_HII_IIBT_END_BLOCK.
Any images with an image identiﬁer greater than or equal to ImageIdCurrent are empty.
33.3. Code Deﬁnitions 1532Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.7.2.2 EFI_HII_IIBT_EXT1, EFI_HII_IIBT_EXT2,EFI_HII_IIBT_EXT4
Summary
Generic preﬁx for image information with a 1-byte length.
Prototype
#define EFI_HII_IIBT_EXT1 0x30
typedef struct _EFI_HII_IIBT_EXT1_BLOCK {
} EFI_HII_IIBT_EXT1_BLOCK;
#define EFI_HII_IIBT_EXT2 0x31
typedef struct _EFI_HII_IIBT_EXT2_BLOCK {
} EFI_HII_IIBT_EXT2_BLOCK;
#define EFI_HII_IIBT_EXT4 0x32
typedef struct _EFI_HII_IIBT_EXT4_BLOCK {
} EFI_HII_IIBT_EXT4_BLOCK;
Members
Header Standard image block header, where Header.BlockType =EFI_HII_IIBT_EXT1_BLOCK,
EFI_HII_IIBT_EXT2_BLOCK orEFI_HII_IIBT_EXT4_BLOCK.
Length Size of the image block, in bytes, including the image block header.
BlockType2 Indicates the type of extended block. See Image Information for a list of all block types.
Future extensions for image records which need a length-byte length use this preﬁx.
33.3.7.2.3 EFI_HII_IIBT_IMAGE_1BIT
Summary
One bit-per-pixel graphics image with palette information.
Prototype
typedef struct _EFI_HII_IIBT_IMAGE_1BIT_BASE {
} EFI_HII_IIBT_IMAGE_1BIT_BASE;
#define EFI_HII_IIBT_IMAGE_1BIT 0x10
33.3. Code Deﬁnitions 1533Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct _EFI_HII_IIBT_IMAGE_1BIT_BLOCK {
UINT8 PaletteIndex;
EFI_HII_IIBT_IMAGE_1BIT_BASE Bitmap;
} EFI_HII_IIBIT_IMAGE_1BIT_BLOCK;
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_IMAGE_1BIT.
Width Width of the bitmap in pixels.
Height Height of the bitmap in pixels.
Bitmap The bitmap speciﬁes a series of pixels, one bit per pixel, left-to-right, top-to-bottom, and is padded out to the
nearest byte. The number of bytes per bitmap can be calculated as: (( Width + 7)/8) * Height.
PaletteIndex Index of the palette in the palette information.
This record assigns the 1-bit-per-pixel bitmap data to the ImageIdCurrent identiﬁer and increment ImageIdCurrent by
one. The image’s upper left hand corner pixel is the most signiﬁcant bit of the ﬁrst bitmap byte. An example of a
EFI_HII_IIBT_IMAGE_1BIT structure is shown below:
0x01 ; Palette Index
0x000B ; Width
0x0013 ; Height
10000000b,00000000b ; Bitmap
11000000b,00000000b
11100000b,00000000b
11110000b,00000000b
11111000b,00000000b
11111100b,00000000b
11111110b,00000000b
11111111b,00000000b
11111111b,10000000b
11111111b,11000000b
11111111b,11100000b
11101111b,00000000b
11001111b,00000000b
10000111b,10000000b
00000111b,10000000b
00000011b,11000000b
00000001b,10000000b
33.3. Code Deﬁnitions 1534Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.7.2.4 EFI_HII_IIBT_IMAGE_1BIT_TRANS
Summary
One bit-per-pixel graphics image with palette information and transparency.
Prototype
#define EFI_HII_IIBT_IMAGE_1BIT_TRANS 0x11
typedef struct _EFI_HII_IIBT_IMAGE_1BIT_TRANS_BLOCK {
} EFI_HII_IIBT_IMAGE_1BIT_TRANS_BLOCK;
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_IMAGE_1BIT_TRANS.
This record assigns the 1-bit-per-pixel bitmap data to the ImageIdCurrent identiﬁer and increment ImageId-
Current by one. The data in the EFI_HII_IIBT_IMAGE_1BIT_TRANS structure is exactly the same as the
EFI_HII_IIBT_IMAGE_1BIT structure, the difference is how the data is treated.
The bitmap pixel value 0 is the ‘transparency’ value and will not be written to the screen. The bitmap pixel value 1
will be translated to the color speciﬁed by Palette.
33.3.7.2.5 EFI_HII_IIBT_IMAGE_24BIT
Summary
A 24 bit-per-pixel graphics image.
Prototype
#define EFI_HII_IIBT_IMAGE_24BIT 0x16
typedef struct _EFI_HII_IIBT_IMAGE_24BIT_BASE
EFI_HII_RGB_PIXEL Bitmap[... ];
} EFI_HII_IIBT_IMAGE_24BIT_BASE;
typedef struct _EFI_HII_IIBT_IMAGE_24BIT_BLOCK {
EFI_HII_IIBT_IMAGE_24BIT_BASE Bitmap;
Members
33.3. Code Deﬁnitions 1535Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_IMAGE_24BIT.
Bitmap The bitmap speciﬁes a series of pixels, 24 bits per pixel, left-to-right, top-to-bottom. The number of bytes
per bitmap can be calculated as: (Width * 3) * Height. Type EFI_HII_RGB_PIXEL is deﬁned in “Related
This record assigns the 24-bit-per-pixel bitmap data to the ImageIdCurrent identiﬁer and increment ImageIdCurrent
by one. The image’s upper left hand corner pixel is composed of the ﬁrst three bitmap bytes. The ﬁrst byte is the
pixel’s blue component value, the next byte is the pixel’s green component value, and the third byte is the pixel’s
red component value (B,G,R). Each color component value can vary from 0x00 (color off) to 0xFF (color full on),
allowing 16.8 millions colors that can be speciﬁed.
typedef struct _EFI_HII_RGB_PIXEL {
UINT8 b;
UINT8 g;
UINT8 r;
} EFI_HII_RGB_PIXEL;
bThe relative intensity of blue in the pixel’s color, from off (0x00) to full-on (0xFF).
g The relative intensity of green in the pixel’s color, from off (0x00) to full-on (0xFF).
r The relative intensity of red in the pixel’s color, from off (0x00) to full-on (0xFF).
33.3.7.2.6 EFI_HII_IIBT_IMAGE_24BIT_TRANS
Summary
A 24 bit-per-pixel graphics image with transparency.
Prototype
#define _EFI_HII_IIBT_IMAGE_24BIT_TRANS 0x17
typedef struct EFI_HII_IIBT_IMAGE_24BIT_TRANS_BLOCK {
} EFI_HII_IIBT_IMAGE_24BIT_TRANS_BLOCK;
Members
Header Standard image header, where Hea der.BlockType =EFI_HII_IIBT_IMAGE_24BIT_TRANS.
per bitmap can be calculated as: (Width * 3) * Height.
by one. The data in the EFI_HII_IMAGE_24BIT_TRANS structure is exactly the same as the EFI_HII_IMAGE_24BIT
structure, the difference is how the data is treated.
33.3. Code Deﬁnitions 1536Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The bitmap pixel value 0x00, 0x00, 0x00 is the ‘transparency’ value and will not be written to the screen. All other
bitmap pixel values will be written as deﬁned to the screen. Since the ‘transparency’ value replaces true black, for
image to display black they should use the color 0x00, 0x00, 0x01 (very dark red)
33.3.7.2.7 EFI_HII_IIBT_IMAGE_4BIT
Summary
Four bits-per-pixel graphics image with palette information.
Prototype
typedef struct _EFI_HII_IIBT_IMAGE_4BIT_BASE {
UINT8 Data[...];
} EFI_HII_IIBT_IMAGE_4BIT_BASE;
#define EFI_HII_IIBT_IMAGE_4BIT 0x12
typedef struct _EFI_HII_IIBT_IMAGE_4BIT_BLOCK {
EFI_HII_IIBT_IMAGE_4BIT_BASE Bitmap;
} EFI_HII_IIBT_IMAGE_4BIT_BLOCK;
Members

Summary
Prototype
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_IMAGE_4BIT.
Bitmap The bitmap speciﬁes a series of pixels, four bits per pixel, left-to-right, top-to-bottom, and is padded out to
the nearest byte. The number of bytes per bitmap can be calculated as: (( Width + 1)/2) * Height.
This record assigns the 4-bit-per-pixel bitmap data to the ImageIdCurrent identiﬁer using the speciﬁed palette and
increment ImageIdCurrent by one. The image’s upper left hand corner pixel is the most signiﬁcant nibble of the ﬁrst
bitmap byte.
33.3.7.2.8 EFI_HII_IIBT_IMAGE_4BIT_TRANS
Summary
Four bits-per-pixel graphics image with palette information and transparency.
Prototype
#define EFI_HII_IIBT_IMAGE_4BIT_TRANS 0x13
typedef struct _EFI_HII_IIBT_IMAGE_4BIT_TRANS_BLOCK {
33.3. Code Deﬁnitions 1537Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_HII_IIBT_IMAGE_4BIT_TRANS_BLOCK;
Members
Header Standard image header, where Header.BlockType =EFI_HII-IIBT_IMAGE_4BIT_TRANS.
increment ImageIdCurrent by one. The data in the EFI_HII-IMAGE_4BIT_TRANS structure is exactly the same as the
EFI_HII-IMAGE_4BIT structure, the difference is how the data is treated.
The bitmap pixel value 0 is the ‘transparency’ value and will not be written to the screen. All the other bitmap pixel
values will be translated to the color speciﬁed by Palette.
33.3.7.2.9 EFI_HII-IIBT_IMAGE_8BIT
Summary
Eight bits-per-pixel graphics image with palette information.
Prototype
#define EFI_HII-IIBT_IMAGE_8BIT 0x14
typedef struct _EFI_HII-IIBT_IMAGE_8BIT_BASE {
} EFI_HII-IIBT_IMAGE_8BIT_BASE;
typedef struct _EFI_HII-IIBT_IMAGE_8BIT_BLOCK {
EFI_HII-IMAGE_BLOCK Header;
EFI_HII-IIBT_IMAGE_8BIT_BASE Bitmap;
} EFI_HII-IIBT_IMAGE_8BIT_BLOCK;
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_IMAGE_8BIT.
Bitmap The bitmap speciﬁes a series of pixels, eight bits per pixel, left-to-right, top-to-bottom. The number of bytes
per bitmap can be calculated as: Width *Height .
This record assigns the 8-bit-per-pixel bitmap data to the ImageIdCurrent identiﬁer using the speciﬁed palette and
increment ImageIdCurrent by one. The image’s upper left hand corner pixel is the ﬁrst bitmap byte.
33.3. Code Deﬁnitions 1538Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.7.2.10 EFI_HII_IIBT_IMAGE_8BIT_TRANS
Summary
Eight bits-per-pixel graphics image with palette information and transparency.
Prototype
#define EFI_HII_IIBT_IMAGE_8BIT_TRANS 0x15
typedef struct _EFI_HII_IIBT_IMAGE_8BIT_TRANS_BLOCK {
EFI_HII_IIBT_IMAGE_8BIT_BASE Bitmap;
} EFI_HII_IIBT_IMAGE_8BIT_TRANS_BLOCK;
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_IMAGE_8BIT_TRANS.
per bitmap can be calculated as: Width *Height.
increment ImageIdCurrent by one. The data in the EFI_HII_IMAGE_8BIT_TRANS structure is exactly the same as
theEFI_HII_IMAGE_8BIT structure, the difference is how the data is treated.
EFI_HII_IIBT_DUPLICATE %%%%%%%%%%%%%%%%%%%%%%5
Summary
Assigns a new character value to a previously deﬁned image.
Prototype
#define EFI_HII_IIBT_DUPLICATE 0x20
typedef struct _EFI_HII_IIBT_DUPLICATE_BLOCK {
EFI_IMAGE_ID ImageId;
} EFI_HII_IIBT_DUPLICATE_BLOCK;
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_DUPLICATE.
ImageId The previously deﬁned image ID with the exact same image.
Indicates that the image with image ID ImageValueCurrent has the same image as a previously deﬁned image ID and
increments ImageValueCurrent by one.
33.3. Code Deﬁnitions 1539Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.7.2.11 EFI_HII_IIBT_IMAGE_JPEG
Summary
A true-color bitmap is encoded with JPEG image compression.
Prototype
#define EFI_HII_IIBT_IMAGE_JPEG 0x18
typedef struct _EFI_HII_IIBT_JPEG_BLOCK {
} EFI_HII_IIBT_JPEG;
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_IMAGE_JPEG.
Size Speciﬁes the size of the JPEG encoded data.
Data JPEG encoded data with ‘JFIF’ signature at offset 6 in the data block. The JPEG encoded data, speciﬁes type of
encoding and ﬁnal size of true-color image.
This record assigns the JPEG image data to the ImageIdCurrent identiﬁer and increment ImageIdCurrent by one. The
JPEG decoder is only required to cover the basic JPEG encoding types, which are produced by standard available
paint packages (for example: MSPaint under Windows from Microsoft). This would include JPEG encoding of high
(1:1:1) and medium (4:1:1) quality with only three components (R,G,B) - no support for the special gray component
encoding.
33.3.7.2.12 EFI_HII_IIBT_SKIP1
Summary
Skips image IDs.
Prototype
#define EFI_HII_IIBT_SKIP1 0x22
typedef struct _EFI_HII_IIBT_SKIP1_BLOCK {
} EFI_HII_IIBT_SKIP1_BLOCK;
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_SKIP1.
SkipCount The unsigned 8-bit value to add to ImageIdCurrent.
Increments the current image ID ImageIdCurrent by the number speciﬁed.
33.3. Code Deﬁnitions 1540Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.7.2.13 EFI_HII_IIBT_SKIP2
Summary
Prototype
#define EFI_HII_IIBT_SKIP2 0x21
typedef struct _EFI_HII_IIBT_SKIP2_BLOCK {
} EFI_HII_IIBT_SKIP2_BLOCK;
Members
Header Standard image header, where Header.BlockType =EFI_HII_IIBT_SKIP2.
SkipCount The unsigned 16-bit value to add to ImageIdCurrent.
33.3.7.2.14 EFI_HII_IIBT_PNG_BLOCK
Add a new image block structure for EFI_HII_IIBT_IMAGE_PNG . This supports the PNG image format in EFI HII
image database.
// EFI_HII_IIBT_IMAGE_PNG(0x19)
typedef struct _EFI_HII_IIBT_PNG_BLOCK {
} EFI_IIBT_PNG_BLOCK;
Members
Header Standard image block header, where H eader.locktype =EFI_HII_IIBT_IMAGE_PNG.
Size Size of the PNG image.
Data The raw data of the PNG image ﬁle.
33.3. Code Deﬁnitions 1541Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.7.3 Palette Information
Summary
This section describes the palette information within an image package.
Prototype
typedef struct _EFI_HII_IMAGE_PALETTE_INFO_HEADER {
UINT16 PaletteCount;
} EFI_HII_IMAGE_PALETTE_INFO_HEADER;
Members
PaletteCount Number of palettes.
This ﬁxed header is followed by zero or more variable-length palette information records. The structures are assigned
a number 1 to n.
33.3.7.3.1 Palette Information Records
Summary
A single palette
Prototype
typedef struct _EFI_HII_IMAGE_PALETTE_INFO {
UINT16 PaletteSize;
EFI_HII_RGB_PIXEL PaletteValue[_];
} EFI_HII_IMAGE_PALETTE_INFO;
Members
PaletteSize Size of the palette information.
PaletteValue Array of color values. Type EFI_HII_RGB_PIXEL is described in “Related Deﬁnitions” in
EFI_HII_IIBT_IMAGE_24BIT.
Each palette information record is an array of 24-bit color structures. The ﬁrst entry ( PaletteValue[0] ) corresponds
to color 0 in the source image; the second entry ( PaletteValue[1] ) corresponds to color 1, etc. Each palette entry
is a three byte entry, with the ﬁrst byte equal to the blue component of the color, followed by green, and ﬁnally red

Members
Summary
Prototype
Members
(B,G,R). Each color component value can vary from 0x00 (color off) to 0xFF (color full on), allowing 16.8 millions
colors that can be speciﬁed.
A black & white 1-bit image would have the following palette structure:
Fig. 33.44: Palette Structure of a Black & White, One-BitImage
33.3. Code Deﬁnitions 1542Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
A 4-bit image would have the following palette structure:
Fig. 33.45: Palette Structure of a Four-Bit Image
The image palette must only contain the palette entries speciﬁed in the bitmap. The bitmap should allocate each color
index starting from 0x00, so the palette information can be as small as possible. The following is an example of a
palette structure of a 4-bit image that only uses 6 colors:
Each palette entry speciﬁes each unique color in the image. The above ﬁgure would be typical of light blue logo on a
black background, with several shades of blue for anti-aliasing the blue logo on the black background.
33.3.8 Forms Package
The Forms package is used to carry forms-based encoding data.
Prototype
typedef struct _EFI_HII_FORM_PACKAGE_HDR {
EFI_HII_PACKAGE_HEADER *Header;
//EFI_IFR_OP_HEADER *OpCodeHeader;
//More op-codes follow
} EFI_HII_FORM_PACKAGE_HDR;
Header The standard package header, where Header.Type = EFI_HII_PACKAGE_FORMS.
OpCodeHeader The header for the ﬁrst of what will be a series of op-codes associated with the forms data described
in this package. The syntax of the forms can be referenced in Forms .
33.3. Code Deﬁnitions 1543Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.46: Palette Structure of a Four-Bit, Six-ColorImage
This is a package type designed to represent Internal Forms Representation (IFR) objects as a collection of op-codes
33.3.8.1 Binary Encoding
The IFR is a binary encoding for HII-related objects. Every object has (at least) three attributes:
Opcode. The enumeration of all of the different HII-related objects.
Length. The length of the opcode itself (2-127 bytes).
Scope. If set, this opens up a new scope. Certain objects describe attributes or capabilities which only apply to the
current scope rather than the entire form. The scope extends up to the special END opcode, which marks the end of
the current scope.
The binary objects are encoded as byte stream. Every object begins with a standard header ( EFI_IFR_OP_HEADER
), which describes the opcode type, length and scope.
The simple binary object consists of a standard header, which contains a single 8-bit opcode, a 7-bit length and a 1-bit
nesting indicator. The length speciﬁes the number of bytes in the opcode, including the header. The simple binary
object may also have zero or more bytes of ﬁxed, object-speciﬁc, data.
Fig. 33.47: Simple Binary Object
When the Scope bit is set, it marks the beginning of a new scope which applies to all subsequent opcodes until the
matching EFI_IFR_END opcode is found to close the scope. Those opcodes may, in turn, open new scopes as well,
creating nested scopes.
33.3. Code Deﬁnitions 1544Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.2 Standard Headers
33.3.8.2.1 EFI_IFR_OP_HEADER
Summary
Standard opcode header
Prototype
typedef struct _EFI_IFR_OP_HEADER {
UINT8 Length:7;
UINT8 Scope:1;
} EFI_IFR_OP_HEADER;
Members
OpCode Deﬁnes which type of operation is being described by this header. See Opcode Reference for a list of IFR
opcodes.
Length Deﬁnes the number of bytes in the opcode, including this header.
Scope If this bit is set, the opcode begins a new scope, which is ended by an EFI_IFR_END opcode.
Forms are represented in a binary format roughly similar to processor instructions.
Each header contains an opcode, a length and a scope indicator.
IfScope indicator is set, the scope exists until it reaches a corresponding EFI_IFR_END opcode. Scopes may be
nested within other scopes.
typedef UINT16 EFI_QUESTION_ID;
typedef UINT16 EFI_IMAGE_ID;
typedef UINT16 EFI_STRING_ID;
typedef UINT16 EFI_FORM_ID;
typedef UINT16 EFI_VARSTORE_ID;
typedef UINT16 EFI_ANIMATION_ID;
33.3.8.2.2 EFI_IFR_QUESTION_HEADER
Summary
Standard question header.
Prototype
typedef struct _EFI_IFR_QUESTION_HEADER {
EFI_IFR_STATEMENT_HEADER Header;
EFI_QUESTION_ID QuestionId;
EFI_VARSTORE_ID VarStoreId;
union {
EFI_STRING_ID VarName;
UINT16 VarOffset;
} VarStoreInfo;
33.3. Code Deﬁnitions 1545Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} EFI_IFR_QUESTION_HEADER;
Members
Header The standard statement header.
QuestionId The unique value that identiﬁes the particular question being deﬁned by the opcode. The value of zero is
reserved.
Flags A bit-mask that determines which unique settings are active for this question. See “Related Deﬁnitions” below
for the meanings of the individual bits.
VarStoreId Speciﬁes the identiﬁer of a previously declared variable store to use when storing the question’s value. A
value of zero indicates no associated variable store.
VarStoreInfo IfVarStoreId refers to Buffer Storage ( EFI_IFR_VARSTORE orEFI_IFR_VARSTORE_EFI ), then
VarStoreInfo contains a 16-bit Buffer Storage offset ( VarOffset ). IfVarStoreId refers to Name/Value Storage (
EFI_IFR_VARSTORE_NAME_VALUE ), then VarStoreInfo contains the String ID of the name ( VarName ) for
this name/value pair.
This is the standard header for questions.
// Flags values
#define EFI_IFR_FLAG_READ_ONLY 0x01
#define EFI_IFR_FLAG_CALLBACK 0x04
#define EFI_IFR_FLAG_RESET_REQUIRED 0x10
#define EFI_IFR_FLAG_REST_STYLE 0x20
#define EFI_IFR_FLAG_RECONNECT_REQUIRED 0x40
#define EFI_IFR_FLAG_OPTIONS_ONLY 0x80
EFI_IFR_FLAG_READ_ONLY The question is read-only
EFI_IFR_FLAG_CALLBACK Designates if a particular opcode is to be treated as
something that will initiate a callback to a registered
driver.
EFI_IFR_FLAG_RESET_REQUIRED If a particular choice is modiﬁed, designates that a re-
turn ﬂag will be activated upon exiting of the browser,
which indicates that the changes that the user requested
require a reset to enact.
EFI_IFR_FLAG_REST_STYLE Designates if a question supports REST architec-
tural style operation. This ﬂag can be omit-
ted if the formset class guid already contains
EFI_HII_REST_STYLE_FORMSET_GUID.
EFI_IFR_FLAG_RECONNECT_REQUIRED If a particular choice is modiﬁed, designates that a re-
turn ﬂag will be activated upon exiting of the formset
or the browser, which indicates that the changes that the
user requested require a reconnect to enact.
EFI_IFR_FLAG_OPTIONS_ONLY For questions with options, this indicates that only the
options will be available for user choice.
33.3. Code Deﬁnitions 1546Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.2.3 EFI_IFR_STATEMENT_HEADER
Summary
Standard statement header.
Prototype
typedef struct _EFI_IFR_STATEMENT_HEADER {
EFI_STRING_ID Prompt;
EFI_STRING_ID Help;
} EFI_IFR_STATEMENT_HEADER;
Members
Prompt The string identiﬁer of the prompt string for this particular statement. The value 0 indicates no prompt string.
Help The string identiﬁer of the help string for this particular statement. The value 0 indicates no help string.
This is the standard header for statements, including questions.
33.3.8.3 Opcode Reference
This section describes each of the IFR opcode encodings in detail. The table below lists the opcodes in numeric order
while the reference section lists them in alphabetic order.
Table 33.20: IFR Opcodes
Opcode Value Description
EFI_IFR_FORM_OP 0x01 Form
EFI_IFR_SUBTITLE_OP 0x02 Subtitle statement
EFI_IFR_TEXT_OP 0x03 Static text/image statement
EFI_IFR_IMAGE_OP 0x04 Static image.
EFI_IFR_ONE_OF_OP 0x05 One-of question
EFI_IFR_CHECKBOX_OP 0x06 Boolean question
EFI_IFR_NUMERIC_OP 0x07 Numeric question
EFI_IFR_PASSWORD_OP 0x08 Password string question
EFI_IFR_ONE_OF_OPTION_OP 0x09 Option
EFI_IFR_SUPPRESS_IF_OP 0x0A Suppress if conditional
EFI_IFR_LOCKED_OP 0x0B Marks statement/question as locked
EFI_IFR_ACTION_OP 0x0C Button question
EFI _IFR_RESET_BUTTON_OP 0x0D Reset button statement
EFI_IFR_FORM_SET_OP 0x0E Form set
EFI_IFR_REF_OP 0x0F Cross-reference statement
EFI_IFR_NO_SUBMIT_IF_OP 0x10 Error checking conditional
EFI_IF R_INCONSISTENT_IF_OP 0x11 Error checking conditional
EFI_IFR_EQ_ID_VAL_OP 0x12 Return TRUE if question value equals UINT16
EFI_IFR_EQ_ID_ID_OP 0x13 Return TRUE if question value equals another
question value
EFI_I FR_EQ_ID_VAL_LIST_OP 0x14 Return TRUE if question value is found in list
of UINT16s
EFI_IFR_AND_OP 0x15 Push TRUE if both sub-expressions returns
TRUE .
33.3. Code Deﬁnitions 1547Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 33.20 – continued from previous page

of UINT16s
TRUE .
EFI_IFR_OR_OP 0x16 Push TRUE if either sub-expressions returns
TRUE .
EFI_IFR_NOT_OP 0x17 Push FALSE if sub-expression returns TRUE ,
otherwise return TRUE .
EFI_IFR_RULE_OP 0x18 Create rule in current form.
EFI_IFR_GRAY_OUT_IF_OP 0x19 Nested statements, questions or options will not
be selectable if expression returns TRUE .
EFI_IFR_DATE_OP 0x1A Date question.
EFI_IFR_TIME_OP 0x1B Time question.
EFI_IFR_STRING_OP 0x1C String question
EFI_IFR_REFRESH_OP 0x1D Interval for refreshing a question
EFI_IFR_DISABLE_IF_OP 0x1E Nested statements, questions or options will not
be processed if expression returns TRUE .
EFI_IFR_ANIMATION_OP 0x1F Animation associated with question statement,
form or form set.
EFI_IFR_TO_LOWER_OP 0x20 Convert a string on the expression stack to
lower case.
EFI_IFR_TO_UPPER_OP 0x21 Convert a string on the expression stack to up-
per case.
EFI_IFR_MAP_OP 0x22 Convert one value to another by selecting a
match from a list.
EFI _IFR_ORDERED_LIST_OP 0x23 Set question
EFI_IFR_VARSTORE_OP 0x24 Deﬁne a buffer-style variable storage.
EFI_IFR_VA RSTORE_NAME_VALUE_OP 0x25 Deﬁne a name/value style variable storage.
EFI _IFR_VARSTORE_EFI_OP 0x26 Deﬁne a UEFI variable style variable storage.
EFI_IF R_VARSTORE_DEVICE_OP 0x27 Specify the device path to use for variable stor-
age.
EFI_IFR_VERSION_OP 0x28 Push the revision level of the UEFI Speciﬁca-
tion to which this Forms Processor is compli-
ant.
EFI_IFR_END_OP 0x29 Marks end of scope.
EFI_IFR_MATCH_OP 0x2A Push TRUE if string matches a pattern.
EFI_IFR_GET_OP 0x2B Return a stored value.
EFI_IFR_SET_OP 0x2C Change a stored value.
EFI_IFR_READ_OP 0x2D Provides a value for the current question or de-
fault.
EFI_IFR_WRITE 0x2E Change a value for the current question.
EFI_IFR_EQUAL_OP 0x2F Push TRUE if two expressions are equal.
EFI_IFR_NOT_EQUAL_OP 0x30 Push TRUE if two expressions are not equal.
EFI _IFR_GREATER_THAN_OP 0x31 Push TRUE if one expression is greater than
another expression.
EFI_ IFR_GREATER_EQUAL_OP 0x32 Push TRUE if one expression is greater than or
equal to another expression.
EFI_IFR_LESS_THAN_OP 0x33 Push TRUE if one expression is less than an-
other expression.
EFI_IFR_LESS_EQUAL_OP 0x34 Push TRUE if one expression is less than or
EFI_IFR_BITWISE_AND_OP 0x35 Bitwise-AND two unsigned integers and push
the result.
EFI_IFR_BITWISE_OR_OP 0x36 Bitwise-OR two unsigned integers and push the
result.
33.3. Code Deﬁnitions 1548Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_IFR_BITWISE_NOT_OP 0x37 Bitwise-NOT an unsigned integer and push the
result.
EFI_IFR_SHIFT_LEFT_OP 0x38 Shift an unsigned integer left by a number of
bits and push the result.
EFI_IFR_SHIFT_RIGHT_OP 0x39 Shift an unsigned integer right by a number of
EFI_IFR_ADD_OP 0x3A Add two unsigned integers and push the result.
EFI_IFR_SUBTRACT_OP 0x3B Subtract two unsigned integers and push the re-
sult.
EFI_IFR_MULTIPLY_OP 0x3C Multiply two unsigned integers and push the re-
sult.
EFI_IFR_DIVIDE_OP 0x3D Divide one unsigned integer by another and
push the result.
EFI_IFR_MODULO_OP 0x3E Divide one unsigned integer by another and
push the remainder.
EFI_IFR_RULE_REF_OP 0x3F Evaluate a rule
EFI_ IFR_QUESTION_REF1_OP 0x40 Push a question’s value
EFI_ IFR_QUESTION_REF2_OP 0x41 Push a question’s value
EFI_IFR_UINT8_OP 0x42 Push an 8-bit unsigned integer
EFI_IFR_UINT16_OP 0x43 Push a 16-bit unsigned integer.
EFI_IFR_UINT32_OP 0x44 Push a 32-bit unsigned integer
EFI_IFR_UINT64_OP 0x45 Push a 64-bit unsigned integer.
EFI_IFR_TRUE_OP 0x46 Push a boolean TRUE .
EFI_IFR_FALSE_OP 0x47 Push a boolean FALSE
EFI_IFR_TO_UINT_OP 0x48 Convert expression to an unsigned integer
EFI_IFR_TO_STRING_OP 0x49 Convert expression to a string
EFI_IFR_TO_BOOLEAN_OP 0x4A Convert expression to a boolean.
EFI_IFR_MID_OP 0x4B Extract portion of string or buffer
EFI_IFR_FIND_OP 0x4C Find a string in a string.
EFI_IFR_TOKEN_OP 0x4D Extract a delimited byte or character string
from buffer or string.
EFI_IFR_STRING_REF1_OP 0x4E Push a string
EFI_IFR_STRING_REF2_OP 0x4F Push a string
EFI_IFR_CONDITIONAL_OP 0x50 Duplicate one of two expressions depending on
result of the ﬁrst expression.
EFI_IFR_QUESTION_REF3_OP 0x51 Push a question’s value from a different form.
EFI_IFR_ZERO_OP 0x52 Push a zero
EFI_IFR_ONE_OP 0x53 Push a one
EFI_IFR_ONES_OP 0x54 Push a 0xFFFFFFFFFFFFFFFF.
EFI_IFR_UNDEFINED_OP 0x55 Push Undeﬁned
EFI_IFR_LENGTH_OP 0x56 Push length of buffer or string.
EFI_IFR_DUP_OP 0x57 Duplicate top of expression stack
EFI_IFR_THIS_OP 0x58 Push the current question’s value
EFI_IFR_SPAN_OP 0x59 Return ﬁrst matching/non-matching character
in a string
EFI_IFR_VALUE_OP 0x5A Provide a value for a question
EFI_IFR_DEFAULT_OP 0x5B Provide a default value for a question.
EFI_IFR_DEFAULTSTORE_OP 0x5C Deﬁne a Default Type Declaration
EFI_IFR_FORM_MAP_OP 0x5D Create a standards-map form.
EFI_IFR_CATENATE_OP 0x5E Push concatenated buffers or strings.
EFI_IFR_GUID_OP 0x5F An extensible GUIDed op-code
33.3. Code Deﬁnitions 1549Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_IFR_SECURITY_OP 0x60 Returns whether current user proﬁle contains
speciﬁed setup access privileges.
EFI_IFR_MODAL_TAG_OP 0x61 Specify current form is modal
EFI_IFR_REFRESH_ID_OP 0x62 Establish an event group for refreshing a forms-
based element.
EFI_IFR_WARNING_IF 0x63 Warning conditional
EFI_IFR_MATCH2_OP 0x64 Push TRUE if string matches a Regular Ex-
pression pattern.
Code Deﬁnitions
Each of the following sections gives a detailed description of the opcodes’ behavior.
33.3.8.3.1 EFI_IFR_ACTION
Summary
Create an action button.
Prototype
#define EFI_IFR_ACTION_OP 0x0C
typedef struct _EFI_IFR_ACTION {
EFI_IFR_OP_HEADER Header;
EFI_IFR_QUESTION_HEADER Question;
EFI_STRING_ID QuestionConfig;
} EFI_IFR_ACTION;
typedef struct _EFI_IFR_ACTION_1 {
} _EFI_IFR_ACTION_1;
Members
Header The standard opcode header, where Header.OpCode = EFI_IFR_ACTION_OP .
Question The standard question header. See EFI_IFR_QUESTION_HEADER (EFI_IFR_QUESTION_HEADER )
for more information.
QuestionConﬁg The results string which is in <ConﬁgResp> format will be processed when the button is selected
by the user.
Creates an action question. When the question is selected, the conﬁguration string speciﬁed by QuestionConﬁg will
be processed. If QuestionConﬁg is 0 or is not present, then no no conﬁguration string will be processed. This is useful
when using an action button only for the callback.
If the question is marked read-only (see EFI_IFR_QUESTION_HEADER ) then the action question cannot be selected.
33.3. Code Deﬁnitions 1550Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.2 EFI_IFR_ANIMATION
Summary
Creates an image for a statement or question.
Prototype
#define EFI_IFR_ANIMATION_OP 0x1F
typedef struct _EFI_IFR_ANIMATION {
EFI_ANIMATION_ID Id;
} EFI_IFR_ANIMATION;
Members
Header Standard opcode header, where Header.OpCode isEFI_IFR_ANIMATION_OP
IdAnimation identiﬁer in the HII database.
Associates an animation from the HII database with the current question, statement or form. If the speciﬁed animation
does not exist in the HII database.
33.3.8.3.3 EFI_IFR_ADD
Summary
Pops two unsigned integers, adds them and pushes the result.
Prototype
#define EFI_IFR_ADD_OP 0x3a
typedef struct _EFI_IFR_ADD {
} EFI_IFR_ADD;
Members
Header Standard opcode header, where Header.OpCode = EFI_IFR_ADD_OP .
This opcode performs the following actions:
1. Pop two values from the expression stack. Theﬁrst popped is the right-hand value. The secondpopped is the
left-hand value.
2. If the two values do not evaluate to unsigned integers, push Undeﬁned.
3. Zero-extend the left-hand andright-hand values to 64-bits.
4. Add the left-hand value to right-hand value.
5. Push the lower 64-bits of the result. Overﬂow is ignored.
33.3. Code Deﬁnitions 1551Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.4 EFI_IFR_AND
Summary
Pops two booleans, push TRUE if both are TRUE, otherwise push FALSE.
Prototype
#define EFI_IFR_AND_OP 0x15
typedef struct _EFI_IFR_AND {
} EFI_IFR_AND;
Members
Header The standard opcode header, where Header.OpCode = EFI_IFR_AND_OP .
1. Pop two expressions from the expressionstack.
2. If the two expressions cannot be evaluated as boolean, push Undeﬁned.
3. If both expressions evaluate to TRUE, then push TRUE. Otherwise, push FALSE.
33.3.8.3.5 EFI_IFR_BITWISE_AND
Summary
Pops two unsigned integers, perform bitwise AND and push the result.
Prototype
#define EFI_IFR_BITWISE_AND_OP 0x35
typedef struct _EFI_IFR_BITWISE_AND {

Summary
Prototype
Members
Summary
Prototype
} EFI_IFR_BITWISE_AND;
Members
Header The standard opcode header, where Header.OpCode = EFI_IFR_BITWISE_AND_OP .
2. If the two expressions cannot be evaluated as unsigned integers, push Undeﬁned.
3. Otherwise, zero-extend the unsigned integers to 64-bits.
4. Perform a bitwise-AND on the two values.
5. Push the result.
33.3. Code Deﬁnitions 1552Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.6 EFI_IFR_BITWISE_NOT
Summary
Pop an unsigned integer, perform a bitwise NOT and push the result.
Prototype
#define EFI_IFR_BITWISE_NOT_OP 0x37
typedef struct _EFI_IFR_BITWISE_NOT {
} EFI_IFR_BITWISE_NOT;
Members
Header The standard opcode header, where Header.OpCode = EFI_IFR_BITWISE_NOT_OP .
1. Pop an expression from the expression stack.
2. If the expression cannot be evaluated as an unsigned integer, push Undeﬁned.
3. Otherwise, zero-extend the unsigned integer to 64-bits.
4. Perform a bitwise-NOT on the value.
33.3.8.3.7 EFI_IFR_BITWISE_OR
Summary
Pops two unsigned integers, perform bitwise OR and push the result.
Prototype
#define EFI_IFR_BITWISE_OR_OP 0x36
typedef struct _EFI_IFR_BITWISE_OR {
} EFI_IFR_BITWISE_OR;
Members
Header Standard opcode header, where OpCode isEFI_IFR_BITWISE_OR_OP .
4. Perform a bitwise-OR of the two values.
33.3. Code Deﬁnitions 1553Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.8 EFI_IFR_CATENATE
Summary
Pops two buffers or strings, concatenates them and pushes the result.
Prototype
#define EFI_IFR_CATENATE_OP 0x5e
typedef struct _EFI_IFR_CATENATE {
} EFI_IFR_CATENATE;
Members
Header Standard opcode header, where OpCode isEFI_IFR_CATENATE_OP .
1. Pop two expressions from the expressionstack. The ﬁrst expression popped is the left valueand the second value
popped is the right value.
2. If the left or right values cannot be evaluated as a string or a buffer, push Undeﬁned. If the left or right values
are of different types, then push Undeﬁned.
3. If the left and right values are strings, push a new string which contains the contents of the left string (without
the NULL terminator) followed by the contents of the right string on to the expression stack.
4. If the left and right values are buffers, push a new buffer that contains the contents of the left buffer followed by
the contents of the right buffer on to the expression stack.
33.3.8.3.9 EFI_IFR_CHECKBOX
Summary
Creates a boolean checkbox.
Prototype
#define EFI_IFR_CHECKBOX_OP 0x06
typedef struct _EFI_IFR_CHECKBOX {
} EFI_IFR_CHECKBOX;
Members
Header The standard question header, where Header.OpCode = EFI_IFR_CHECKBOX_OP .
Flags Flags that describe the behavior of the question. All undeﬁned bits should be zero. See
EFI_IFR_CHECKBOX_x in “Related Deﬁnitions” for more information.
Creates a Boolean checkbox question and adds it to the current form. The checkbox has two values: FALSE if the box
is not checked and TRUE if it is.
33.3. Code Deﬁnitions 1554Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
There are three ways to specify defaults for this question: the Flags ﬁeld (lowest priority), one or more nested
EFI_IFR_ONE_OF_OPTION, or nested EFI_IFR_DEFAULT (highest priority).
An image may be associated with the question using a nested EFI_IFR_IMAGE. An animation may be associated with
the option using a nested EFI_IFR_ANIMATION.
#define EFI_IFR_CHECKBOX_DEFAULT 0x01
#define EFI_IFR_CHECKBOX_DEFAULT_MFG 0x02
33.3.8.3.10 EFI_IFR_CONDITIONAL
Summary
Pops two values and a boolean, pushes one of the values depending on the boolean.
Prototype
#define EFI_IFR_CONDITIONAL_OP 0x50
typedef struct _EFI_IFR_CONDITIONAL {
} EFI_IFR_CONDITIONAL;
Members
Header Standard opcode header, where OpCode isEFI_IFR_CONDITIONAL_OP .
# Pop three values from the expression stack.The ﬁrst value popped is the right value. The secondexpression popped
is the middle value. The lastexpression popped is the left value.
1. If the left value cannot be evaluated as a boolean, push Undeﬁned.
2. If the left expression evaluates to TRUE, push the right value.
3. Otherwise, push the middle value.
33.3.8.3.11 EFI_IFR_DATE
Summary
Create a date question.
Prototype
#define EFI_IFR_DATE_OP 0x1A
typedef struct _EFI_IFR_DATE {
} EFI_IFR_DATE;
Members
Header The sequence that deﬁnes the type of opcode as well as the length of the opcode being deﬁned.
Header.OpCode = EFI_IFR_DATE_OP .
33.3. Code Deﬁnitions 1555Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Question The standard question header. See EFI_IFR_QUESTION_HEADER for more information.
Flags Flags that describe the behavior of the question. All undeﬁned bits should be zero.
#define EFI_QF_DATE_YEAR_SUPPRESS 0x01
#define EFI_QF_DATE_MONTH_SUPPRESS 0x02
#define EFI_QF_DATE_DAY_SUPPRESS 0x04
#define EFI_QF_DATE_STORAGE 0x30
For*QF_DATE_STORAGE, *there are currently three valid values:
#define QF_DATE_STORAGE_NORMAL 0x00
#define QF_DATE_STORAGE_TIME 0x10
#define QF_DATE_STORAGE_WAKEUP 0x20
Create a Date question ( Date ) and add it to the current form.
There are two ways to specify defaults for this question: one or more nested EFI_IFR_ONE_OF_OPTION (lowest
priority) or nested EFI_IFR_DEFAULT (highest priority). An image may be associated with the option using a nested
EFI_IFR_IMAGE . An animation may be associated with the question using a nested EFI_IFR_ANIMATION.
33.3.8.3.12 EFI_IFR_DEFAULT
Summary
Provides a default value for the current question
Prototype
#define EFI_IFR_DEFAULT_OP 0x5b
typedef struct _EFI_IFR_DEFAULT {
UINT16 DefaultId;
EFI_IFR_TYPE_VALUE Value;
} EFI_IFR_DEFAULT;
typedef struct _EFI_IFR_DEFAULT_2 {
} EFI_IFR_DEFAULT_2;
Members
Header The sequence that deﬁnes the type of opcode as well as the length of the opcode being deﬁned. For this tag,
Header.OpCode = EFI_IFR_DEFAULT_OP .
DefaultId Identiﬁes the default store for this value. The default store must have previously been created using
EFI_IFR_DEFAULTSTORE.
Type The type of data in the Value ﬁeld. See EFI_IFR_TYPE_x inEFI_IFR_ONE_OF_OPTION.
Value The default value. The actual size of this ﬁeld depends on Type. IfType isEFI_IFR_TYPE_OTHER, then the
default value is provided by a nested EFI_IFR_VALUE.
33.3. Code Deﬁnitions 1556Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This opcode speciﬁes a default value for the current question. There are two forms. The ﬁrst ( EFI_IFR_DEFAULT
) assumes that the default value is a constant, embedded directly in the Value member. The second (
EFI_IFR_DEFAULT_2 ) assumes that the default value is speciﬁed using a nested EFI_IFR_VALUE opcode.
33.3.8.3.13 EFI_IFR_DEFAULTSTORE
Summary
Provides a declaration for the type of default values that a question can be associated with.
Prototype
#define EFI_IFR_DEFAULTSTORE_OP 0x5c
typedef struct _EFI_IFR_DEFAULTSTORE {
EFI_STRING_ID DefaultName;
} EFI_IFR_DEFAULTSTORE;
Members
Header.OpCode = EFI_IFR_DEFAULTSTORE_OP
DefaultName A string token reference for the human readable string associated with the type of default being de-
clared.
DefaultId The default identiﬁer, which is unique within the current form set. The default identiﬁer creates a group of
defaults. See Attributes, listed under xxxx Defaults for the default identiﬁer ranges.
Declares a class of default which can then have question default values associated with.
AnEFI_IFR_DEFAULTSTORE with a speciﬁed DefaultId must appear in the IFR before it can be referenced by an
EFI_IFR_DEFAULT.
33.3.8.3.14 EFI_IFR_DISABLE_IF
Summary
Disable all nested questions and expressions if the expression evaluates to TRUE.
Prototype
#define EFI_IFR_DISABLE_IF_OP 0x1e
typedef struct _EFI_IFR_DISABLE_IF {
} EFI_IFR_DISABLE_IF;
Members

Members
clared.
Summary
Prototype
Members
Header The byte sequence that deﬁnes the type of opcode as well as the length of the opcode being deﬁned.
Header.OpCode = EFI_IFR_DISABLE_IF_OP .
All nested statements, questions, options or expressions will not be processed if the expression appearing as the ﬁrst
nested object evaluates to TRUE . If the expression consists of more than a single opcode, then the ﬁrst opcode in the
expression must have the Scope bit set and the expression must end with EFI_IFR_END.
33.3. Code Deﬁnitions 1557Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
When this opcode appears under a form set, the expression must only rely on constants. When this opcode appears
under a form, the expression may rely on question values in the same form which are not inside of an EFI_DISABLE_IF
expression.
33.3.8.3.15 EFI_IFR_DIVIDE
Summary
Pops two unsigned integers, divide one by the other and pushes the result.
Prototype
#define EFI_IFR_DIVIDE_OP 0x3d
typedef struct _EFI_IFR_DIVIDE {
} EFI_IFR_DIVIDE;
Members
Header Standard opcode header, where OpCode is EFI_IFR_DIVIDE .
1. Pop two expressions from the expressionstack. The ﬁrst popped is the right-hand expression.The second popped
is the left-hand expression.**
2. If the two expressions do not evaluate to unsigned integers, push Undeﬁned. If the right-hand expression is
equal to zero, push Undeﬁned.
3. Zero-extend the left-hand and right-hand expressions to 64-bits.
4. Divide the left-hand value to right-hand expression.
33.3.8.3.16 EFI_IFR_DUP
Summary
Duplicate the top value on the expression stack.
Prototype
#define EFI_IFR_DUP_OP 0x57
typedef struct _EFI_IFR_DUP {
} EFI_IFR_DUP;
Members
Header Standard opcode header, where OpCode isEFI_IFR_DUP _OP.
Duplicate the top expression on the expression stack.
NOTE: This opcode is usually used as an optimization by the tools to help eliminate common sub-expression calcula-
tion and make smaller expressions.
33.3. Code Deﬁnitions 1558Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.17 EFI_IFR_END
Summary
End of the current scope.
Prototype
#define EFI_IFR_END_OP 0x29
typedef struct _EFI_IFR_END {
} EFI_IFR_END;
Members
Header Standard opcode header, where OpCode isEFI_IFR_END_OP .
Marks the end of the current scope.
33.3.8.3.18 EFI_IFR_EQUAL
Summary
Pop two values, compare and push TRUE if equal, FALSE if not.
Prototype
#define EFI_IFR_EQUAL_OP 0x2f
typedef struct _EFI_IFR_EQUAL {
} EFI_IFR_EQUAL;
Members
Header Standard opcode header, where OpCode isEFI_IFR_EQUAL_OP .
The opcode performs the following actions:
1. Pop two values from the expression stack.
2. If the two values are not strings, Booleans or unsigned integers, push Undeﬁned.
3. If the two values are of different types, push Undeﬁned.
4. Compare the two values. Strings are compared lexicographically.
5. If the two values are equal then push TRUE on the expression stack. If they are not equal, push FALSE .
33.3. Code Deﬁnitions 1559Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.19 EFI_IFR_EQ_ID_ID
Summary Push TRUE if the two questions have the same value or FALSE if they are not equal.
Prototype
#define EFI_IFR_EQ_ID_ID_OP 0x13
typedef struct _EFI_IFR_EQ_ID_ID {
EFI_QUESTION_ID QuestionId1;
EFI_QUESTION_ID QuestionId2;
} EFI_IFR_EQ_ID_ID;
Members
Header Standard opcode header, where OpCode isEFI_IFR_EQ_ID_ID_OP .
QuestionId1, QuestionId2 Speciﬁes the identiﬁer of the questions whose values will be compared.
Evaluate the values of the speciﬁed questions ( QuestionId1, QuestionId2 ). If the two values cannot be evaluated
or cannot be converted to comparable types, then push Undeﬁned. If they are equal, push TRUE. Otherwise push
FALSE.
33.3.8.3.20 EFI_IFR_EQ_ID_VAL_LIST
Summary
Push TRUE if the question’s value appears in a list of unsigned integers.
Prototype
#define EFI_IFR_EQ_ID_VAL_LIST_OP 0x14
typedef struct _EFI_IFR_EQ_ID_VAL_LIST {
UINT16 ListLength;
UINT16 ValueList[1];
} EFI_IFR_EQ_ID_VAL_LIST;
Members
Header Standard opcode header, where OpCode isEFI_IFR_EQ_ID_VAL_LIST_OP .
QuestionId Speciﬁes the identiﬁer of the question whose value will be compared.
ListLength Number of entries in ValueList.
ValueList Zero or more unsigned integer values to compare against.
Evaluate the value of the speciﬁed question ( QuestionId ). If the speciﬁed question cannot be evaluated as an unsigned
integer, then push Undeﬁned. If the value can be found in ValueList, then push TRUE. Otherwise push FALSE.
33.3. Code Deﬁnitions 1560Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.21 EFI_IFR_EQ_ID_VAL
Summary
Push TRUE if a question’s value is equal to a 16-bit unsigned integer, otherwise FALSE .
Prototype
#define EFI_IFR_EQ_ID_VAL_OP 0x12
typedef struct _EFI_IFR_EQ_ID_VAL {
} EFI_IFR_EQ_ID_VAL;
Members
Header Standard opcode header, where OpCode isEFI_IFR_EQ_ID_VAL_OP .
Value Unsigned integer value to compare against.
integer, then push Undeﬁned. If they are equal, push TRUE. Otherwise push FALSE.
33.3.8.3.22 EFI_IFR_FALSE
Summary
Push a FALSE on to the expression stack.
Prototype
#define EFI_IFR_FALSE_OP 0x47
typedef struct _EFI_IFR_FALSE {
} EFI_IFR_FALSE;
Members
Header.OpCode = EFI_IFR_FALSE_OP
33.3. Code Deﬁnitions 1561Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.23 EFI_IFR_FIND
Summary
Pop two strings and an unsigned integer, ﬁnd one string in the other and the index where found.
Prototype
#define EFI_IFR_FIND_OP 0x4c
typedef struct _EFI_IFR_FIND {
UINT8 Format;
} EFI_IFR_FIND;
Members
Header Standard opcode header, where OpCode isEFI_IFR_FIND_OP .
Format The following ﬂags govern the matching criteria:
#define EFI_IFR_FF_CASE_SENSITIVE 0x00
#define EFI_IFR_FF_CASE_INSENSITIVE 0x01
1. Pop three expressions from the expressionstack. The ﬁrst expression popped is the right-handvalue and the
second value popped is the middle valueand the last value popped is the left-hand value.
2. If the left-hand or middle values cannot be evaluated as a string, push Undeﬁned. If the third expression cannot
be evaluated as an unsigned integer, push Undeﬁned.
3. The left-hand value is the string to search. The middle value is the string to compare with. The right-hand
expression is the zero-based index of the search. |
4. If the string is found, push the zero-based index of the found string.
5. Otherwise, if the string is not found or the right-hand value speciﬁes a value which is greater-than or equal to
the length of the left-hand value’s string, push 0xFFFFFFFFFFFFFFFF.
33.3.8.3.24 EFI_IFR_FORM
Summary
Creates a form.
Prototype
#define EFI_IFR_FORM_OP 0x01
typedef struct _EFI_IFR_FORM {
EFI_FORM_ID FormId;
EFI_STRING_ID FormTitle;
} EFI_IFR_FORM;
Members
33.3. Code Deﬁnitions 1562Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Header.OpCode = EFI_IFR_FORM_OP .
FormId The form identiﬁer, which uniquely identiﬁes the form within the form set. The form identiﬁer, along with
the device path and form set GUID, uniquely identiﬁes a form within a system.
FormTitle The string token reference to the title of this particular form.
A form is the encapsulation of what amounts to a browser page. The header deﬁnes a FormId, which is referenced by
the form set, among others. It also deﬁnes a FormTitle, which is a string to be used as the title for the form.
33.3.8.3.25 EFI_IFR_FORM_MAP
Summary
Creates a standards map form.
Prototype
#define EFI_IFR_FORM_MAP_OP 0x5D
typedef struct _EFI_IFR_FORM_MAP_METHOD {
EFI_STRING_ID MethodTitle;
EFI_GUID MethodIdentifier;
} EFI_IFR_FORM_MAP_METHOD;
typedef struct _EFI_IFR_FORM_MAP {
//EFI_IFR_FORM_MAP_METHOD Methods[];
} EFI_IFR_FORM_MAP;
Header.OpCode = EFI_IFR_FORM_MAP_OP .
FormId The unique identiﬁer for this particular form.
Methods One or more conﬁguration method’s name and unique identiﬁer.

Summary
Prototype
MethodTitle The string identiﬁer which provides the human-readable name of the conﬁguration method for this
standards map form.
MethodIdentiﬁer Identiﬁer which uniquely speciﬁes the conﬁguration methods associated with this standards map
form. See “Related Deﬁnitions” for current identiﬁers.
A standards map form describes how the conﬁguration settings are represented for a conﬁguration method identiﬁed
byMethodIdentiﬁer. It also deﬁnes a FormTitle, which is a string to be used as the title for the form.
#define EFI_HII_STANDARD_FORM_GUID \
{ 0x3bd2f4ec, 0xe524, 0x46e4, \
{ 0xa9, 0xd8, 0x51, 0x01, 0x17, 0x42, 0x55, 0x62 } }
AnEFI_IFR_FORM_MAP where the method identiﬁer is EFI_HII_STANDARD_FORM_GUID is semantically iden-
tical to a normal EFI_IFR_FORM.
33.3. Code Deﬁnitions 1563Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.26 EFI_IFR_FORM_SET
Summary
The form set is a collection of forms that are intended to describe the pages that will be displayed to the user.
Prototype
#define EFI_IFR_FORM_SET_OP 0x0E
typedef struct _EFI_IFR_FORM_SET {
EFI_STRING_ID FormSetTitle;
//EFI_GUID ClassGuid[_];
} EFI_IFR_FORM_SET;
Members
Header.OpCode = EFI_IFR_FORM_SET_OP .
Guid The unique GUID value associated with this particular form set. Type EFI_GUID is deﬁned in InstallProtocol-
Interface() in this speciﬁcation.
FormSetTitle The string token reference to the title of this particular form set.
Help The string token reference to the help of this particular form set.
Flags Flags which describe additional features of the form set. Bits 0:1 = number of members in ClassGuid. Bits 2:7
= Reserved. Should be set to zero.
ClassGuid Zero to four class identiﬁers. The standard class identiﬁers are described in
EFI_HII_FORM_BROWSER2_PROTOCOL.SendForm(). They do not need to be unique in the form
set.
The form set consists of a header and zero or more forms.
33.3.8.3.27 EFI_IFR_GET
Summary
Return a stored value.
Prototype
#define EFI_IFR_GET_OP 0x2B
typedef struct _EFI_IFR_GET {
union {
UINT8 VarStoreType;
} EFI_IFR_GET;
33.3. Code Deﬁnitions 1564Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Header.OpCode = EFI_IFR_GET_OP .
VarStoreId Speciﬁes the identiﬁer of a previously declared variable store to use when retrieving the value.
VarStoreInfo Depending on the type of variable store selected, this contains either a 16-bit Buffer Storage offset (
VarOffset ) or a Name/Value or EFI Variable name ( VarName ).
VarStoreType Speciﬁes the type used for storage. The storage types EFI_IFR_TYPE_x are deﬁned in
EFI_IFR_ONE_OF_OPTION.
This operator takes the value from storage and pushes it on to the expression stack. If the value could not be retrieved
from storage, then Undeﬁned is pushed on to the expression stack.
The type of value retrieved from storage depends on the setting of VarStoreType, as described in the following table:
Table 33.21: VarStoreType Descriptions
VarStoreType Storage Description
EFI_IFR_TYPE_NUM_SIZE_8 8-bit unsigned integer
EFI_IFR_TYPE_NUM_SIZE_16 16-bit unsigned integer
EFI_IFR_TYPE_NUM_SIZE_32 32-bit unsigned integer
EFI_IFR_TYPE_NUM_SIZE_64 64-bit unsigned integer
EFI_IFR_TYPE_BOOLEAN 8-bit boolean (0 = FALSE , 1 = TRUE )
EFI_IFR_TYPE_TIME EFI_HII_TIME
EFI_IFR_TYPE_DATE EFI_HII_DATE
EFI_IFR_TYPE_STRING Null-terminated string
EFI_IFR_TYPE_OTHER Invalid
EFI_IFR_TYPE_ACTION Null-Terminated string
EFI_IFR_TYPE_UNDEFINED Invalid
EFI_IFR_TYPE_BUFFER Buffer
EFI_IFR_TYPE_REF EFI_HII_REF
33.3.8.3.28 EFI_IFR_GRAY_OUT_IF
Summary
Creates a group of statements or questions which are conditionally grayed-out.
Prototype
#define EFI_IFR_GRAY_OUT_IF_OP 0x19
typedef struct _EFI_IFR_GRAY_OUT_IF {
} EFI_IFR_GRAY_OUT_IF;
Members
Header.OpCode = EFI_IFR_GRAY_OUT_IF_OP .
All nested statements or questions will be grayed out (not selectable and visually distinct) if the expression appearing
as the ﬁrst nested object evaluates to TRUE. If the expression consists of more than a single opcode, then the ﬁrst
33.3. Code Deﬁnitions 1565Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
opcode in the expression must have the Scope bit set and the expression must end with EFI_IFR_END.
Different browsers may support this option to varying degrees. For example, HTML has no similar construct so it may
not support this facility.
33.3.8.3.29 EFI_IFR_GREATER_EQUAL
Summary
Pop two values, compare, push TRUE if ﬁrst is greater than or equal the second, otherwise push FALSE.
Prototype
#define EFI_IFR_GREATER_EQUAL_OP 0x32
typedef struct _EFI_IFR_GREATER_EQUAL {
} EFI_IFR_GREATER_EQUAL;
Members
Header Standard opcode header, where OpCode isEFI_IFR_GREATER_EQUAL _OP.
1. Pop two values from the expression stack. Theﬁrst value popped is the right-hand value and thesecond value
popped is the left-hand value.
2. If the two values do not evaluate to string, boolean or unsigned integer, push Undeﬁned.
3. If the two values do not evaluate to the same type, push Undeﬁned.
5. If the left-hand value is greater than or equal to the right-hand value, push TRUE. Otherwise push FALSE .
33.3.8.3.30 EFI_IFR_GREATER_THAN
Summary
Pop two values, compare, push TRUE if ﬁrst is greater than the second, otherwise push FALSE.
Prototype
#define EFI_IFR_GREATER_THAN_OP 0x31
typedef struct _EFI_IFR_GREATER_THAN {
EFI_IFR_OP_HEADER *Header;
} EFI_IFR_GREATER_THAN;
Members
Header Standard opcode header, where OpCode isEFI_IFR_GREATER_THAN _OP
33.3. Code Deﬁnitions 1566Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
5. If the left-hand value is greater than the right-hand value, push TRUE. Otherwise push FALSE.
33.3.8.3.31 EFI_IFR_GUID
Summary
A GUIDed operation. This op-code serves as an extensible op-code which can be deﬁned by the Guid value to have
various functionality. It should be noted that IFR browsers or scripts which cannot interpret the meaning of this
GUIDed op-code will skip it.
Prototype
#define EFI_IFR_GUID_OP 0x5F
typedef struct _EFI_IFR_GUID {
//Optional Data Follows
} EFI_IFR_GUID;
Header.OpCode = EFI_IFR_GUID_OP
Guid The GUID value for this op-code. This ﬁeld is intended to deﬁne a particular type of special-purpose function,
and the format of the data which immediately follows the Guid ﬁeld (if any) is deﬁned by that particular GUID.
33.3.8.3.32 EFI_IFR_IMAGE
Summary
Prototype
#define EFI_IFR_IMAGE_OP 0x04
typedef struct _EFI_IFR_IMAGE {
EFI_IMAGE_ID Id;
} EFI_IFR_IMAGE;
Members
IdImage identiﬁer in the HII database.
Speciﬁes the image within the HII database.
33.3. Code Deﬁnitions 1567Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.33 EFI_IFR_INCONSISTENT_IF
Summary
Creates a validation expression and error message for a question.
Prototype
#define EFI_IFR_INCONSISTENT_IF_OP 0x011
typedef struct _EFI_IFR_INCONSISTENT_IF {
EFI_STRING_ID Error;
} EFI_IFR_INCONSISTENT_IF;
Members
Header.OpCode = EFI_IFR_INCONSISTENT_IF_OP .
Error The string token reference to the string that will be used for the consistency check message.
This tag uses a Boolean expression to allow the IFR creator to check options in a richer manner than provided by
the question tags themselves. For example, this tag might be used to validate that two options are not using the same
address or that the numbers that were entered align to some pattern (such as leap years and February in a date input
ﬁeld). The tag provides a string to be used in a error display to alert the user to the issue. Inconsistency tags will

Summary
Prototype
Members
be evaluated when the user traverses from tag to tag. The user should not be allowed to submit the results of a form
inconsistency.
33.3.8.3.34 EFI_IFR_LENGTH
Summary
Pop a string or buffer, push its length.
Prototype
#define EFI_IFR_LENGTH_OP 0x56
typedef struct _EFI_IFR_LENGTH {
} EFI_IFR_LENGTH;
Members
Header Standard opcode header, where OpCode isEFI_IFR_LENGTH_OP .
1. Pop a value from the expression stack.
2. If the value cannot be evaluated as a buffer or string, then push Undeﬁned.
3. If the value can be evaluated as a buffer, push the length of the buffer, in bytes.
4. If the value can be evaluated as a string, push the length of the string, in characters.
33.3. Code Deﬁnitions 1568Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.35 EFI_IFR_LESS_EQUAL
Summary
Pop two values, compare, push TRUE if ﬁrst is less than or equal to the second, otherwise push FALSE.
Prototype
#define EFI_IFR_LESS_EQUAL_OP 0x34
typedef struct _EFI_IFR_LESS_EQUAL {
} EFI_IFR_LESS_EQUAL;
Members
Header Standard opcode header, where OpCode isEFI_IFR_LESS_EQUAL _OP.
1. Pop two values from the expression stack. The ﬁrst value popped is the right-hand value and the second value
5. If the left-hand value is less than or equal to the right-hand value, push TRUE. Otherwise push FALSE.
33.3.8.3.36 EFI_IFR_LESS_THAN
Summary
Pop two values, compare, push TRUE if the ﬁrst is less than the second, otherwise push FALSE.
Prototype
#define EFI_IFR_LESS_THAN_OP 0x33
typedef struct _EFI_IFR_LESS_THAN {
} EFI_IFR_LESS_THAN;
Members
Header Standard opcode header, where OpCode isEFI_IFR_LESS_THAN _OP.
5. If the left-hand value is less than the right-hand value, push TRUE. Otherwise push FALSE.
33.3. Code Deﬁnitions 1569Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.37 EFI_IFR_LOCKED
Summary
Speciﬁes that the statement or question is locked.
Prototype
#define EFI_IFR_LOCKED_OP 0x0B
typedef struct _EFI_IFR_LOCKED {
} EFI_IFR_LOCKED;
Header Standard opcode header, where Header.Opcode isEFI_IFR_LOCKED_OP .
Members
None
The presence of EFI_IFR_LOCKED indicates that the statement or question should not be modiﬁed by a Forms Editor.
33.3.8.3.38 EFI_IFR_MAP
Summary
Pops value, compares against an array of comparison values, pushes the corresponding result value.
Prototype
#define EFI_IFR_MAP_OP 0x22
typedef struct _EFI_IFR_MAP {
} EFI_IFR_MAP;
Header.OpCode = EFI_IFR_MAP_OP
This operator contains zero or more expression pairs nested within its scope. Each expression pair contains a match
expression and a return expression.
1. This operator pops a single value from theexpression stack.
2. Compare this value against the evaluated result of each of the match expressions.
3. If there is a match, then the evaluated result of the corresponding return expression is pushed on to the expression
stack.
4. If there is no match, then Undeﬁned is pushed.
33.3. Code Deﬁnitions 1570Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.39 EFI_IFR_MATCH
Summary
Pop a source string and a pattern string, push TRUE if the source string matches the pattern speciﬁed by the pattern
string, otherwise push FALSE.
Prototype
#define EFI_IFR_MATCH_OP 0x2a
typedef struct _EFI_IFR_MATCH {
} EFI_IFR_MATCH;
Members
Header Standard opcode header, where Header.Opcode isEFI_IFR_MATCH_OP .
1. Pop two values from the expression stack. Theﬁrst value popped is the string and the second valuepopped is the
pattern.
2. If the string or the pattern cannot be evaluated as a string, then push Undeﬁned.
3. Process the string and pattern using the MetaiMatch function of the
EFI_UNICODE_COLLATION2_PROTOCOL.
4. If the result is TRUE, then push TRUE.
5. If the result is FALSE, then push FALSE.
33.3.8.3.40 EFI_IFR_MID
Summary
Pop a string or buffer and two unsigned integers, push an extracted portion of the string or buffer.
Prototype
#define EFI_IFR_MID_OP 0x4b
typedef struct _EFI_IFR_MID {
} EFI_IFR_MID;
Members
Header Standard opcode header, where OpCode isEFI_IFR_MID_OP .
1. Pop three values from the expression stack.The ﬁrst value popped is the right value and thesecond value popped
is the middle value and the lastexpression popped is the left value.**
2. If the left value cannot be evaluated as a string or a buffer, push Undeﬁned. If the middle or right value cannot
be evaluated as unsigned integers, push Undeﬁned.
3. If the left value is a string, then the middle value is the 0-based index of the ﬁrst character in the string to extract
and the right value is the length of the string to extract. If the right value is zero or the middle value is greater
than or equal the string’s length, then push an Empty string. Push the extracted string on the expression stack.
If the right value would cause extraction to extend beyond the end of the string, then only the characters up to
and include the last character of the string are in the pushed result.
33.3. Code Deﬁnitions 1571Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
4. If the left value is a buffer, then the middle value is the 0-based index of the ﬁrst byte in the buffer to extract and
the right value is the length of the buffer to extract. If the right value is zero or the middle value is greater than
the buffer’s length, then push an empty buffer. Push the extracted buffer on the expression stack. If the right
value would cause extraction to extend beyond the end of the buffer, then only the bytes up to and include the
last byte of the buffer are in the pushed result.
33.3.8.3.41 EFI_IFR_MODAL_TAG
Summary
Specify that the current form is a modal form.
Prototype
#define EFI_IFR_MODAL_TAG_OP 0x61
typedef struct _EFI_IFR_MODAL_TAG {
} EFI_IFR_MODAL_TAG;
Members
Header Standard opcode header, where OpCode isEFI_IFR_MODAL_TAG _OP.
When this opcode is present within the scope of a form, the form is modal; if the opcode is not present, the form is not
modal.
A “modal” form is one that requires speciﬁc user interaction before it is deactivated. Examples of modal forms include
error messages or conﬁrmation dialogs.
When a modal form is activated, it is also selected. A modal form is deactivated only when one of the following
occurs:
• The user chooses a “Navigate To Form” behavior (deﬁned in Selected Form , “Selected Form”). Note that this
is distinct from the “Navigate Forms” behavior.
• A question in the form requires callback, and the callback returns one of the following ActionRequest values
(deﬁned in EFI_HII_CONFIG_ACCESS_PROTOCOL.CallBack() ):
—EFI_BROWSER_ACTION_REQUEST_RESET
—EFI_BROWSER_ACTION_REQUEST_SUBMIT
—EFI_BROWSER_ACTION_REQUEST_EXIT
—EFI_BROWSER_ACTION_REQUEST_FORM_SUBMIT_EXIT
—EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD_EXIT
A modal form cannot be deactivated using other navigation behaviors, including:
• Navigate Forms
• Exit Browser/Discard All (except when initiated by a callback as indicated above)
• Exit Browser/Submit All (except when initiated by a callback as indicated above)
• Exit Browser/Discard All/Reset Platform (except when initiated by a callback as indicated above)
33.3. Code Deﬁnitions 1572Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.42 EFI_IFR_MODULO
Summary
Pop two unsigned integers, divide one by the other and push the remainder.
Prototype
#define EFI_IFR_MODULO_OP 0x3e
typedef struct _EFI_IFR_MODULO {
} EFI_IFR_MODULO;
Members
Header Standard opcode header, where OpCode isEFI_IFR_MODULO _OP.

Summary
Prototype
Members
2. If the two values do not evaluate to unsigned integers, push Undeﬁned. If the right-hand value to 0, push
Undeﬁned.
3. Zero-extend the values to 64-bits. Then, divide the left-hand value by the right-hand value.
4. Push the difference between the left-hand value and the product of the right-hand value and the calculated
quotient.
33.3.8.3.43 EFI_IFR_MULTIPLY
Summary
Multiply one unsigned integer by another and push the result.
Prototype
#define EFI_IFR_MULTIPLY_OP 0x3c
typedef struct _EFI_IFR_MULTIPLY {
} EFI_IFR_MULTPLY;
Members
Header Standard opcode header, where OpCode isEFI_IFR_MULTIPLY_OP .
1. Pop two values from the expression stack. Theﬁrst value popped is the right-hand expression andthe second
value popped is the left-hand expression.
3. Zero-extend the values to 64-bits. Then, multiply the right-hand value by the left-hand value. Push the lower
64-bits of the result.
33.3. Code Deﬁnitions 1573Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.44 EFI_IFR_NOT
Summary
Pop a boolean and, if TRUE, push FALSE. IfFALSE, push TRUE.
Prototype
#define EFI_IFR_NOT_OP 0x17
typedef struct _EFI_IFR_NOT {
} EFI_IFR_NOT;
Members
Header.OpCode = EFI_IFR_NOT_OP .
1. Pop one value from the expression stack.
2. If the value cannot be evaluated as a Boolean, push Undeﬁned.
3. If the value evaluates to TRUE, then push FALSE. Otherwise, push TRUE.
33.3.8.3.45 EFI_IFR_NOT_EQUAL
Summary
Pop two values, compare and push TRUE if not equal, otherwise push FALSE.
Prototype
#define EFI_IFR_NOT_EQUAL_OP 0x30
typedef struct _EFI_IFR_NOT_EQUAL {
} EFI_IFR_NOT_EQUAL;
Members
Header* Standard opcode header, where OpCode isEFI_IFR_NOT_EQUAL_OP .
5. If the two values are not equal then push TRUE on the expression stack. If they are equal, push FALSE .
33.3. Code Deﬁnitions 1574Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.46 EFI_IFR_NO_SUBMIT_IF
Summary
Prototype
#define EFI_IFR_NO_SUBMIT_IF_OP 0x10
typedef struct _EFI_IFR_NO_SUBMIT_IF {
} EFI_IFR_NO_SUBMIT_IF;
Members
Header.OpCode = EFI_IFR_NO_SUBMIT_IF_OP .
Creates a conditional expression which will be evaluated when the form is submitted. If the conditional evaluates to
TRUE , then the error message Error will be displayed to the user and the user will be prevented from submitting the
form.
33.3.8.3.47 EFI_IFR_NUMERIC
Summary
Creates a number question.
Prototype
#define EFI_IFR_NUMERIC_OP 0x07
typedef struct _EFI_IFR_NUMERIC {
union {
struct {
UINT8 MinValue;
UINT8 MaxValue;
UINT8 Step;
} u8;
struct {
UINT16 MinValue;
UINT16 MaxValue;
UINT16 Step;
} u16;
struct {
UINT32 MinValue;
UINT32 MaxValue;
UINT32 Step;
} u32;
struct {
UINT64 MinValue;
33.3. Code Deﬁnitions 1575Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT64 MaxValue;
UINT64 Step;
} u64;
} data;
} EFI_IFR_NUMERIC;
Members
Header.OpCode = EFI_IFR_NUMERIC_OP .
Question The standard question header. xxxx See EFI_IFR_QUESTION_HEADER for more information.
Flags Speciﬁes ﬂags related to the numeric question. See “Related Deﬁnitions”
MinValue The minimum value to be accepted by the browser for this opcode. The size of the data ﬁeld may vary
from 8 to 64 bits.
MaxValue The maximum value to be accepted by the browser for this opcode. The size of the data ﬁeld may vary
Step Deﬁnes the amount to increment or decrement the value each time a user requests a value change. If the step
value is 0, then the input mechanism for the numeric value is to be free-form and require the user to type in the
actual value. The size of the data ﬁeld may vary from 8 to 64 bits.
Creates a number question on the current form, with built-in error checking and default information. The storage size
depends on the EFI_IFR_NUMERIC_SIZE portion of the Flags ﬁeld.
#define EFI_IFR_NUMERIC_SIZE 0x03
#define EFI_IFR_NUMERIC_SIZE_1 0x00
#define EFI_IFR_NUMERIC_SIZE_2 0x01
#define EFI_IFR_NUMERIC_SIZE_4 0x02
#define EFI_IFR_NUMERIC_SIZE_8 0x03
#define EFI_IFR_DISPLAY 0x30
#define EFI_IFR_DISPLAY_INT_DEC 0x00
#define EFI_IFR_DISPLAY_UINT_DEC 0x10
#define EFI_IFR_DISPLAY_UINT_HEX 0x20
EFI_IFR_NUMERIC_SIZE — Speciﬁes the size of the numeric value, the storage required and the size of the
MinValue, MaxValue andStep values in the opcode header.
EFI_IFR_DISPLAY — The value will be displayed in signed decimal, unsigned decimal or unsigned hexadecimal.
Input is still allowed in any form.
NOTE: IFR expressions do not support signed types (Data Types Data Types). The value of a numeric question is
treated during expression evaluation as an unsigned integer even if EFI_IFR_DISPLAY_INT_DEC ﬂag is speciﬁed.
However, the EFI_IFR_DISPLAY_INT_DEC ﬂag is taken into consideration while validating question’s current or
default value against MinValue andMaxValue. When EFI_IFR_DISPLAY_INT_DEC ﬂag is speciﬁed, forms proces-
sor must treat MinValue, MaxValue, current question value, and default question value as signed integers .
33.3. Code Deﬁnitions 1576Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.48 EFI_IFR_ONE
Summary
Push a one on to the expression stack.
Prototype
#define EFI_IFR_ONE_OP 0x53
typedef struct _EFI_IFR_ONE {
} EFI_IFR_ONE;
Members
Header.OpCode = EFI_IFR_ONE_OP
33.3.8.3.49 EFI_IFR_ONES
Summary
Push 0xFFFFFFFFFFFFFFFF on to the expression stack.
Prototype
#define EFI_IFR_ONES_OP 0x54
typedef struct _EFI_IFR_ONES {
} EFI_IFR_ONES;
Members
Header.OpCode = EFI_IFR_ONES_OP
33.3.8.3.50 EFI_IFR_ONE_OF
Summary
Creates a select-one-of question.
Prototype
#define EFI_IFR_ONE_OF_OP 0x05
typedef struct _EFI_IFR_ONE_OF {
EFI_IFR_QUESTION_HEADER *Question;
33.3. Code Deﬁnitions 1577Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
union {
struct {
} u8;
struct {
} u16;
struct {
} u32;
struct {
} u64;
} data;
} EFI_IFR_ONE_OF;
Members
Header.OpCode = EFI_IFR_ONE_OF_OP .
Flags Speciﬁes ﬂags related to the numeric question. See “Related Deﬁnitions” in EFI_IFR_NUMERIC.
from 8 to 64 bits, depending on the size speciﬁed in Flags

} u32;
struct {
} u64;
} data;
Members
actual value. The size of the data ﬁeld may vary from 8 to 64 bits, depending on the size speciﬁed in Flags
This opcode creates a select-on-of object, where the user must select from one of the nested options. This is identical
toEFI_IFR_NUMERIC.
33.3. Code Deﬁnitions 1578Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.51 EFI_IFR_ONE_OF_OPTION
Summary
Creates a pre-deﬁned option for a question.
Prototype
#define EFI_IFR_ONE_OF_OPTION_OP 0x09
typedef struct _EFI_IFR_ONE_OF_OPTION {
EFI_STRING_ID Option;
} EFI_IFR_ONE_OF_OPTION;
Members
Header.OpCode = EFI_IFR_ONE_OF_OPTION_OP .
Option The string token reference to the option description string for this particular opcode.
Flags Speciﬁes the ﬂags associated with the current option. See EFI_IFR_OPTION_x.
Type Speciﬁes the type of the option’s value. See EFI_IFR_TYPE.
Value The union of all of the different possible values. The actual contents (and size) of the ﬁeld depends on Type.
UINT8 u8; // EFI_IFR_TYPE_NUM_SIZE_8
UINT16 u16; // EFI_IFR_TYPE_NUM_SIZE_16
UINT32 u32; // EFI_IFR_TYPE_NUM_SIZE_32
UINT64 u64; // EFI_IFR_TYPE_NUM_SIZE_64
BOOLEAN b; // EFI_IFR_TYPE_BOOLEAN
EFI_HII_TIME time; // EFI_IFR_TYPE_TIME
EFI_HII_DATE date; // EFI_IFR_TYPE_DATE
EFI_STRING_ID string; // EFI_IFR_TYPE_STRING,EFI_IFR_TYPE_ACTION
EFI_HII_REF ref; // EFI_IFR_TYPE_REF
// UINT8 buffer[]; // EFI_IFR_TYPE_BUFFER
} EFI_IFR_TYPE_VALUE;
UINT8 Hour;
UINT8 Minute;
UINT8 Second;
} EFI_HII_TIME;
UINT16 Year;
UINT8 Month;
UINT8 Day; //
} EFI_HII_DATE;
33.3. Code Deﬁnitions 1579Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_GUID FormSetGuid;
EFI_STRING_ID DevicePath;
} EFI_HII_REF;
#define EFI_IFR_TYPE_NUM_SIZE_8 0x00
#define EFI_IFR_TYPE_NUM_SIZE_16 0x01
#define EFI_IFR_TYPE_NUM_SIZE_32 0x02
#define EFI_IFR_TYPE_NUM_SIZE_64 0x03
#define EFI_IFR_TYPE_BOOLEAN 0x04
#define EFI_IFR_TYPE_TIME 0x05
#define EFI_IFR_TYPE_DATE 0x06
#define EFI_IFR_TYPE_STRING 0x07
#define EFI_IFR_TYPE_OTHER 0x08
#define EFI_IFR_TYPE_UNDEFINED 0x09
#define EFI_IFR_TYPE_ACTION 0x0A
#define EFI_IFR_TYPE_BUFFER 0x0B
#define EFI_IFR_TYPE_REF 0x0C
#define EFI_IFR_OPTION_DEFAULT 0x10
#define EFI_IFR_OPTION_DEFAULT_MFG 0x20
Create a selection for use in any of the questions.
The value is encoded within the opcode itself, unless EFI_IFR_TYPE_OTHER is speciﬁed, in which case the value is
determined by a nested EFI_IFR_VALUE.
An image may be associated with the option using a nested EFI_IFR_IMAGE. An animation may be associated with
the question using a nested EFI_IFR_ANIMATION.
33.3.8.3.52 EFI_IFR_OR
Summary
Pop two Booleans, push TRUE if either is TRUE. Otherwise push FALSE.
Prototype
#define EFI_IFR_OR_OP 0x16
typedef struct _EFI_IFR_OR {
} EFI_IFR_OR;
Members
Header.OpCode = EFI_IFR_OR _OP.
2. If either value does not evaluate as a Boolean, then push Undeﬁned.
3. If either value evaluates to TRUE, then push TRUE . Otherwise, push FALSE.
33.3. Code Deﬁnitions 1580Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.53 EFI_IFR_ORDERED_LIST
Summary
Creates a set question using an ordered list.
Prototype
#define EFI_IFR_ORDERED_LIST_OP 0x23
typedef struct _EFI_IFR_ORDERED_LIST {
UINT8 MaxContainers;
} EFI_IFR_ORDERED_LIST;
Members
Header.OpCode = EFI_IFR_ORDERED_LIST_OP .
MaxContainers The maximum number of entries for which this tag will maintain an order. This value also identiﬁes
the size of the storage associated with this tag’s ordering array.
Flags A bit-mask that determines which unique settings are active for this opcode.
Create an ordered list question in the current form. One thing to note is that valid values for the options in ordered lists
should never be a 0. The value of 0 is used to determine if a particular “slot” in the array is empty. Therefore, if in the
previous example 3 was followed by a 4 and then followed by a 0, the valid options to be displayed would be 3 and 4
only.
#define EFI_IFR_UNIQUE_SET 0x01
#define EFI_IFR_NO_EMPTY_SET 0x02
These ﬂags determine whether all entries in the list must be unique ( EFI_IFR_UNIQUE_SET ) and whether there can
be any empty items in the ordered list ( EFI_IFR_NO_EMPTY_SET ).
33.3.8.3.54 EFI_IFR_PASSWORD
Summary
Creates a password question
Prototype
#define EFI_IFR_PASSWORD_OP 0x08
typedef struct _EFI_IFR_PASSWORD {
33.3. Code Deﬁnitions 1581Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT16 MinSize;
UINT16 MaxSize;
} EFI_IFR_PASSWORD;
Members
Header.OpCode = EFI_IFR_PASSWORD_OP .
MinSize The minimum number of characters that can be accepted for this opcode.
MaxSize The maximum number of characters that can be accepted for this opcode.
Creates a password question in the current form.
An image may be associated with the option using a nested EFI_IFR_IMAGE. An animation may be associated
with the question using a nested EFI_IFR_ANIMATION.*The password question has two modes of operation. The
ﬁrst is when the Header.Flags has the *EFI_IFR_FLAG_CALLBACK bit not set. If the bit isn’t set, the browser
will handle all password operations itself, including string comparisons as needed. If the password question has the
EFI_IFR_FLAG_CALLBACK bit set, then there will be a formal handshake initiated between the browser and the
registered driver that would accept the callback. See the ﬂowchart represented in the Figures, below, for details.
(This ﬂowchart is provided in two parts because of page formatting but should be viewed as a single continuous chart.)
33.3.8.3.55 EFI_IFR_QUESTION_REF1
Summary
Push a question’s value on the expression stack.
Prototype
#define EFI_IFR_QUESTION_REF1_OP 0x40
typedef struct _EFI_IFR_QUESTION_REF1 {
} EFI_IFR_QUESTION_REF1;
Members
Header.OpCode = EFI_IFR_QUESTION_REF1_OP .
QuestionId The question’s identiﬁer, which must be unique within the form set.
Push the value of the question speciﬁed by QuestionId on to the expression stack. If the question’s value cannot be
determined or the question does not exist, then push Undeﬁned.
33.3. Code Deﬁnitions 1582Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.48: Password Flowchart (part one)
33.3. Code Deﬁnitions 1583Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 33.49: Password Flowchart (part two)
33.3. Code Deﬁnitions 1584Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.56 EFI_IFR_QUESTION_REF2
Summary
Pop an integer from the expression stack, convert it to a question id, and push the question value associated with that
question id onto the expression stack.
Prototype
#define EFI_IFR_QUESTION_REF2_OP 0x41
typedef struct _EFI_IFR_QUESTION_REF2 {
} EFI_IFR_QUESTION_REF2;
Members
Header.OpCode = EFI_IFR_QUESTION_REF2_OP .
1. Pop an integer from the expression stack
2. Convert it to a question id
3. Push the question value associated with that question id onto the expression stack.

Summary
Prototype
Members
If the popped expression cannot be evaluated as an unsigned integer or the value of the unsigned integer is greater than
0xFFFF, then push Undeﬁned onto the expression stack in step 3. If the value of the question speciﬁed by the unsigned
integer, after converted to a question id, cannot be determined or the question does not exist, also push Undeﬁned onto
the expression stack in step 3.
33.3.8.3.57 EFI_IFR_QUESTION_REF3
Summary
Prototype
#define EFI_IFR_QUESTION_REF3_OP 0x51
typedef struct _EFI_IFR_QUESTION_REF3 {
} EFI_IFR_QUESTION_REF3;
typedef struct _EFI_IFR_QUESTION_REF3_2 {
} EFI_IFR_QUESTION_REF3_2;
typedef struct _EFI_IFR_QUESTION_REF3_3 {
} EFI_IFR_QUESTION_REF3_3;
Members
33.3. Code Deﬁnitions 1585Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Header.OpCode = EFI_IFR_QUESTION_REF3_OP .
DevicePath Speciﬁes the text representation of the device path containing the form set where the question is deﬁned.
If this is not present or the value is 0 then the device path installed on the EFI_HANDLE which was registered
with the form set containing the current question is used.
Guid Speciﬁes the GUID of the form set where the question is deﬁned. If the value is Nil or this ﬁeld is not present,
then the current form set is used (if DevicePath is 0) or the only form set attached to the device path speciﬁed
byDevicePath is used. If the value is Nil and there is more than one form set on the speciﬁed device path, then
the value Undeﬁned will be pushed.
This version allows question values from other forms to be referenced in expressions.
33.3.8.3.58 EFI_IFR_READ
Summary
Provides a value for the current question or default.
Prototype
#define EFI_IFR_READ_OP 0x2D
typedef struct _EFI_IFR_READ {
} EFI_IFR_READ;
Header.OpCode = EFI_IFR_READ_OP
After reading the value for the current question (if any storage was speciﬁed) and setting the thisconstant (see
EFI_IFR_THIS ), this expression will be evaluated (if present) to return the value. If the FormId andQuestionId
are either both not present, or are both set to zero, then the link does nothing.
33.3. Code Deﬁnitions 1586Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.59 EFI_IFR_REF
Summary
Creates a cross-reference statement.
Prototype
#define EFI_IFR_REF_OP 0x0F
typedef struct _EFI_IFR_REF {
} EFI_IFR_REF;
typedef struct _EFI_IFR_REF2 {
} EFI_IFR_REF2;
typedef struct _EFI_IFR_REF3 {
EFI_GUID FormSetId;
} EFI_IFR_REF3;
typedef struct _EFI_IFR_REF4 {
} EFI_IFR_REF4;
typedef struct _EFI_IFR_REF5 {
} EFI_IFR_REF5;
Members
Header.OpCode = EFI_IFR_REF_OP .
Question Standard question header. xxxx See EFI_IFR_QUESTION_HEADER
FormId The form to which this link is referring. If this is zero, then the link is on the current form. If this is missing,
then the link is determined by the nested EFI_IFR_VALUE.
QuestionId The question on the form to which this link is referring. If this ﬁeld is not present (determined by the
length of the opcode) or the value is zero, then the link refers to the top of the form.
FormSetId The form set to which this link is referring. If it is all zeroes or not present, and DevicePath is not present,
then the link is to the current form set. If it is all zeroes (or not present) and the DevicePath is present, then the
33.3. Code Deﬁnitions 1587Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
link is to the ﬁrst form set associated with the DevicePath.
DevicePath The string identiﬁer that speciﬁes the string containing the text representation of the device path to which
the form set containing the form speciﬁed by FormId . If this ﬁeld is not present (determined by the opcode’s
length) or the value is zero, then the link refers to the current page. The format of the device path string that this
ﬁeld references is compatible with the Text format that is speciﬁed in the Text Device Node Reference ( Text
Device Node Reference )
Creates a user-selectable link to a form or a question on a form. There are several forms of this opcode which are
distinguished by the length of the opcode.
33.3.8.3.60 EFI_IFR_REFRESH
Summary
Mark a question for periodic refresh.
Prototype
#define EFI_IFR_REFRESH_OP 0x1d
typedef struct _EFI_IFR_REFRESH {
UINT8 RefreshInterval;
} EFI_IFR_REFRESH;
Members
Header.OpCode = EFI_IFR_REFRESH_OP .
RefreshInterval Minimum number of seconds before the question value should be refreshed. A value of zero indi-
cates the question should not be refreshed automatically.
When placed within the scope of a question, it will force the question’s value to be refreshed at least every RefreshIn-
terval seconds. The value may be refreshed less often, depending on browser policy or capabilities.
33.3.8.3.61 EFI_IFR_REFRESH_ID
Summary
Mark an Question for an asynchronous refresh.
Prototype
#define EFI_IFR_REFRESH_ID_OP 0x62
typedef struct _EFI_IFR_REFRESH_ID {
EFI_GUID RefreshEventGroupId;
} EFI_IFR_REFRESH_ID;
Members
Header.OpCode = EFI_IFR_REFRESH_ID_OP .
33.3. Code Deﬁnitions 1588Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
RefreshEventGroupId The GUID associated with the event group which will be used to initiate a re-evaluation of
an element in a set of forms.
This tag op-code must be placed within the scope of a question or a form. If within the scope of a question and the
event is signaled which belongs to the RefreshEventGroupId, the question will be refreshed. More than one question
may share the same Event Group.
If the tag op-code is placed within the scope of an EFI_IFR_FORM op-code and the event is signaled which belongs
to the RefreshEventGroupId, the entire form’s contents will be refreshed.
• If the contents within a form had an EFI_IFR_REFRESH_ID tag op-code placed within the scope of the form,
and an event is signalled, all questions associated with the RefreshEventGroupId are marked for refresh. The
Forms Browser will update the question value from storage, reparse the forms from the HII database and, at
some time later, reﬂect that change if the question is displayed.
When interpreting this op-code, a browser must do the following actions:
• The browser will create an event group via CreateEventEx() based on the speciﬁed RefreshEventGroupId when
the form set which contains the op-code is opened by the browser.
• When an event is signaled, all questions associated with the RefreshEventGroupId are marked for refresh. The
Forms Browser will update the question value from storage and, at some time later, update the question’s display.
• The browser will close the event group which was previously created when the form set which contains the
op-code is closed by the browser.
33.3.8.3.62 EFI_IFR_RESET_BUTTON
Summary
Create a reset or submit button on the current form.
Prototype
#define EFI_IFR_RESET_BUTTON_OP 0x0d
typedef struct _EFI_IFR_RESET_BUTTON {

Summary
Prototype
EFI_IFR_STATEMENT_HEADER Statement;
EFI_DEFAULT_ID DefaultId;
} EFI_IFR_RESET_BUTTON;
typedef UINT16 EFI_DEFAULT_ID;
Members
Header The standard header, where Header.OpCode = EFI_IFR_RESET_BUTTON_OP .
Statement Standard statement header, including the prompt and help text.
DefaultId Speciﬁes the set of default store to use when restoring the defaults to the questions on this form. xxxx See
EFI_IFR_DEFAULTSTORE for more information.
This opcode creates a user-selectable button that resets the question values for all questions on the current form to
the default values speciﬁed by DefaultId. IfEFI_IFR_FLAGS_CALLBACK is set in the question header, then the
callback associated with the form set will be called. An image may be associated with the statement using a nested
EFI_IFR_IMAGE. An animation may be associated with the statement using a nested EFI_IFR_ANIMATION.
33.3. Code Deﬁnitions 1589Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.63 EFI_IFR_RULE
Summary
Create a rule for use in a form and associate it with an identiﬁer.
Prototype
#define EFI_IFR_RULE_OP 0x18
typedef struct _EFI_IFR_RULE {
UINT8 RuleId;
} EFI_IFR_RULE;
Members
Header.OpCode = EFI_IFR_RULE_OP .
RuleId Unique identiﬁer for the rule. There can only one rule within a form with the speciﬁed RuleId. If another
already exists, then the form is marked as invalid.
Create a rule, which associates an expression with an identiﬁer and attaches it to the currently opened form. These
rules allow common sub-expressions to be re-used within a form.
33.3.8.3.64 EFI_IFR_RULE_REF
Summary
Evaluate a form rule and push its result on the expression stack.
Prototype
#define EFI_IFR_RULE_REF_OP 0x3f
typedef struct _EFI_IFR_RULE_REF {
} EFI_IFR_RULE_REF;
Members
Header.OpCode = EFI_IFR_RULE_REF_OP .
RuleId The rule’s identiﬁer, which must be unique within the form.
Look up the rule speciﬁed by RuleId and push the evaluated result on the expression stack. If the speciﬁed rule does
not exist, then push Undeﬁned.
33.3. Code Deﬁnitions 1590Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.65 EFI_IFR_SECURITY
Summary
Push TRUE if the current user proﬁle contains the speciﬁed setup access permissions.
Prototype
#define EFI_IFR_SECURITY_OP 0x60
typedef struct _EFI_IFR_SECURITY {
EFI_GUID Permissions;
} EFI_IFR_SECURITY;
Members
Header Standard opcode header, where Header.Op =EFI_IFR_SECURITY_OP .
Permissions Security permission level.
This opcode pushes whether or not the current user proﬁle contains the speciﬁed setup access permissions. This
opcode can be used in expressions to disable, suppress or gray-out forms, statements and questions. It can also be used
in checking question values to disallow or allow certain values.
1. If the current user proﬁle contains thespeciﬁed setup access permissions, then push TRUE.*Otherwise, push
**FALSE.*
33.3.8.3.66 EFI_IFR_SET
Summary
Change a stored value.
Prototype
#define EFI_IFR_SET_OP 0x2C
typedef struct _EFI_IFR_SET {
union {
} EFI_IFR_SET;
Header.OpCode = EFI_IFR_SET_OP .
VarStoreId Speciﬁes the identiﬁer of a previously declared variable store to use when storing the question’s value.
33.3. Code Deﬁnitions 1591Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This operator pops an expression from the expression stack. The expression popped is the value.
The value is stored into the variable store identiﬁed by VarStoreId andVarStoreInfo.
If the value could be stored successfully, then TRUE is pushed on to the expression stack. Otherwise, FALSE is
pushed on the expression stack.
33.3.8.3.67 EFI_IFR_SHIFT_LEFT
Summary
Pop two unsigned integers, shift one left by the number of bits speciﬁed by the other and push the result.
Prototype
#define EFI_IFR_SHIFT_LEFT_OP 0x38
typedef struct _EFI_IFR_SHIFT_LEFT {
} EFI_IFR_SHIFT_LEFT;
Members
Header Standard opcode header, where OpCode isEFI_IFR_SHIFT_LEFT _OP.
3. Shift the left-hand value left by the number of bits speciﬁed by the right-hand value and push the result.
33.3.8.3.68 EFI_IFR_SHIFT_RIGHT
Summary
Pop two unsigned integers, shift one right by the number of bits speciﬁed by the other and push the result.
Prototype
#define EFI_IFR_SHIFT_RIGHT_OP 0x39
typedef struct _EFI_IFR_SHIFT_RIGHT {
} EFI_IFR_SHIFT_RIGHT;
Members
Header Standard opcode header, where OpCode isEFI_IFR_SHIFT_RIGHT _OP.
33.3. Code Deﬁnitions 1592Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3. Shift the left-hand value right by the number of bits speciﬁed by the right-hand value and push the result.
33.3.8.3.69 EFI_IFR_SPAN
Summary
Pop two strings and an unsigned integer, ﬁnd the ﬁrst character from one string that contains characters found in
another and push its index.
Prototype
#define EFI_IFR_SPAN_OP 0x59
typedef struct _EFI_IFR_SPAN {
} EFI_IFR_SPAN;
Members
Header.OpCode = EFI_IFR_SPAN_OP .
Flags Speciﬁes whether to ﬁnd the ﬁrst matching string ( EFI_IFR_FLAGS_FIRST_MATCHING ) or the ﬁrst non-
matching string ( EFI_IFR_FLAGS_FIRST_NON_MATCHING ).
is the middle value and the lastvalue popped is the left expression.
2. If the left or middle values cannot be evaluated as a string, push Undeﬁned. If the right value cannot be evaluated
as an unsigned integer, push Undeﬁned.
3. The left string is the string to scan. The middle string consists of character pairs representing the low-end of a
range and the high-end of a range of characters. The right unsigned integer represents the starting location for
the scan.
4. The operation will push the zero-based index of the ﬁrst character after the right value which falls within
any one of the ranges ( EFI_IFR_FLAGS_FIRST_MATCHING ) or falls within none of the ranges (
EFI_IFR_FLAGS_FIRST_NON_MATCHING ).
#define EFI_IFR_FLAGS_FIRST_MATCHING 0x00
#define EFI_IFR_FLAGS_FIRST_NON_MATCHING 0x01
33.3. Code Deﬁnitions 1593Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.70 EFI_IFR_STRING
Summary
Deﬁnes the string question.
Prototype
#define EFI_IFR_STRING_OP 0x1C
typedef struct _EFI_IFR_STRING {
UINT8 MinSize;
UINT8 MaxSize;
} EFI_IFR_STRING;
Members
Header.OpCode = EFI_IFR_STRING_OP .
Flags Flags which control the string editing behavior. See “Related Deﬁnitions” below.
This creates a string question. The minimum length is MinSize and the maximum length is MaxSize characters.

Members
priority) or nested EFI_IFR_DEFAULT (highest priority).
IfEFI_IFR_STRING_MULTI_LINE is set, it is a hint to the Forms Browser that multi-line text can be allowed. If it is
clear, then multi-line editing should not be allowed.
#define EFI_IFR_STRING_MULTI_LINE 0x01
33.3.8.3.71 EFI_IFR_STRING_REF1
Summary
Push a string on the expression stack.
Prototype
#define EFI_IFR_STRING_REF1_OP 0x4e
typedef struct _EFI_IFR_STRING_REF1 {
} EFI_IFR_STRING_REF1;
33.3. Code Deﬁnitions 1594Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Members
Header.OpCode = EFI_IFR_STRING_REF1_OP .
StringId The string’s identiﬁer, which must be unique within the package list.
Push the string speciﬁed by StringId on to the expression stack. If the string does not exist, then push an empty string.
33.3.8.3.72 EFI_IFR_STRING_REF2
Summary
Pop a string identiﬁer, push the associated string.
Prototype
#define EFI_IFR_STRING_REF2_OP 0x4f
typedef struct _EFI_IFR_STRING_REF2 {
} EFI_IFR_STRING_REF2;
Members
Header.OpCode = EFI_IFR_STRING_REF2_OP .
2. If the value cannot be evaluated as an unsigned integer or the value of the unsigned integer is greater than
0xFFFF, push Undeﬁned.
3. If the string speciﬁed by the value (converted to a string identiﬁer) cannot be determined or the string does not
exist, push an empty string.
4. Otherwise, push the string on to the expression stack.
33.3.8.3.73 EFI_IFR_SUBTITLE
Summary
Creates a sub-title in the current form.
Prototype
#define EFI_IFR_SUBTITLE_OP 0x02
typedef struct _EFI_IFR_SUBTITLE {
} EFI_IFR_SUBTITLE;
Members
33.3. Code Deﬁnitions 1595Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Header.OpCode = EFI_IFR_SUBTITLE_OP .
Flags Identiﬁes speciﬁc behavior for the sub-title.
Subtitle strings are intended to be used by authors to separate sections of questions into semantic groups. If
Header.Scope is set, then the Forms Browser may further distinguish the end of the semantic group as including
only those statements and questions which are nested.
IfEFI_IFR_FLAGS_HORIZONTAL is set, then this provides a hint that the nested statements or questions should be
horizontally arranged. Otherwise, they are assumed to be vertically arranged.
An image may be associated with the statement using a nested EFI_IFR_IMAGE. An animation may be associated
with the statement using a nested EFI_IFR_ANIMATION.
#define EFI_IFR_FLAGS_HORIZONTAL 0x01
33.3.8.3.74 EFI_IFR_SUBTRACT
Summary
Pop two unsigned integers, subtract one from the other, push the result.
Prototype
#define EFI_IFR_SUBTRACT_OP 0x3b
typedef struct _EFI_IFR_SUBTRACT {
} EFI_IFR_SUBTRACT;
Members
Header Standard opcode header, where Header.OpCode isEFI_IFR_SUBTRACT _OP.
This opcode performs the following operations:
3. Zero-extend the values to 64-bits.
4. Subtract the right-hand value from the left-hand value.
5. Push the lower 64-bits of the result.
33.3. Code Deﬁnitions 1596Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.75 EFI_IFR_SUPPRESS_IF
Summary
Creates a group of statements or questions which are conditionally invisible.
Prototype
#define EFI_IFR_SUPPRESS_IF_OP 0x0a
typedef struct _EFI_IFR_SUPPRESS_IF {
} EFI_IFR_SUPPRESS_IF;
Members
Header.OpCode = EFI_IFR_SUPPRESS_IF_OP .
The suppress tag causes the nested objects to be hidden from the user if the expression appearing as the ﬁrst nested ob-
ject evaluates to TRUE . If the expression consists of more than a single opcode, then the ﬁrst opcode in the expression
must have the Scope bit set and the expression must end with EFI_IFR_END.
This display form is maintained until the scope for this opcode is closed.
33.3.8.3.76 EFI_IFR_TEXT
Summary
Creates a static text and image.
Prototype
#define EFI_IFR_TEXT_OP 0x03
typedef struct _EFI_IFR_TEXT {
EFI_STRING_ID TextTwo;
} EFI_IFR_TEXT;
Members
Header.OpCode = EFI_IFR_TEXT_OP .
Statement Standard statement header.
TextTwo The string token reference to the secondary string for this opcode.
This is a static text/image statement.
with the question using a nested EFI_IFR_ANIMATION.
33.3. Code Deﬁnitions 1597Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.77 EFI_IFR_THIS
Summary
Push current question’s value.
Prototype
#define EFI_IFR_THIS_OP 0x58
typedef struct _EFI_IFR_THIS {
} EFI_IFR_THIS;
Members
Header.OpCode = EFI_IFR_THIS_OP .
Push the current question’s value.
33.3.8.3.78 EFI_IFR_TIME
Summary
Create a Time question.
Prototype
#define EFI_IFR_TIME_OP 0x1b
typedef struct _EFI_IFR_TIME {
} EFI_IFR_TIME;
Members
Header Basic question information. Header.Opcode =EFI_IFR_TIME_OP .
QF_TIME_HOUR_SUPPRESS 0x01
QF_TIME_MINUTE_SUPPRESS 0x02
QF_TIME_SECOND_SUPPRESS 0x04
QF_TIME_STORAGE 0x30
ForQF_TIME_STORAGE, there are currently three valid values:
QF_TIME_STORAGE_NORMAL 0x00
QF_TIME_STORAGE_TIME 0x10
33.3. Code Deﬁnitions 1598Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
QF_TIME_STORAGE_WAKEUP 0x20
Create a Time question xxxx ( Time ) and add it to the current form.
33.3.8.3.79 EFI_IFR_TOKEN
Summary
Pop two strings and an unsigned integer, then push the nth section of the ﬁrst string using delimiters from the second
string.
Prototype
#define EFI_IFR_TOKEN_OP 0x4d
typedef struct _EFI_IFR_TOKEN {
} EFI_IFR_TOKEN;
Members
Header Standard opcode header, where OpCode isEFI_IFR_TOKEN_OP .
1. Pop three values from the expression stack. The ﬁrst value popped is the right value and the second value popped
is the middle value and the last value popped is the left value.
3. The ﬁrst value is the string. The second value is a string, where each character is a valid delimiter. The third
value is the zero-based index.
4. Push the nth delimited sub-string on to the expression stack (0 = left of the ﬁrst delimiter). The end of the string
always acts a the ﬁnal delimiter.
5. The no such string exists, an empty string is pushed.
33.3.8.3.80 EFI_IFR_TO_BOOLEAN
Summary
Pop a value, convert to Boolean and push the result.
Prototype
#define EFI_IFR_TO_BOOLEAN_OP 0x4A
typedef struct _EFI_IFR_TO_BOOLEAN{
} EFI_IFR_TO_BOOLEAN;
Members
33.3. Code Deﬁnitions 1599Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Header.OpCode = EFI_IFR_TO_BOOLEAN_OP
1. Pop a value from the expression stack. If thevalue is Undeﬁned or cannot be evaluated as aBoolean, push
Undeﬁned. Otherwise push the Boolean onthe expression stack.
2. When converting from an unsigned integer, zero will be converted to FALSE and any other value will be
converted to TRUE.
3. When converting from a string, if case-insensitive compare with “true” is True, then push TRUE. If a case-

Summary
Prototype
Members
insensitive compare with “false” is TRUE, then push False. Otherwise, push Undeﬁned.
4. When converting from a buffer, if the buffer is all zeroes, then push FALSE.* Otherwise push **TRUE.
33.3.8.3.81 EFI_IFR_TO_LOWER
Summary
Convert a string on the expression stack to lower case.
Prototype
#define EFI_IFR_TO_LOWER_OP 0x20
typedef struct _EFI_IFR_TO_LOWER {
} EFI_IFR_TO_LOWER;
Members
Header.OpCode = EFI_IFR_TO_LOWER_OP
Pop an expression from the expression stack. If the expression is Undeﬁned or cannot be evaluated as a
string, push Undeﬁned. Otherwise, convert the string to all lower case using the StrLwr function of the
EFI_UNICODE_COLLATION2_PROTOCOL and push the string on the expression stack.
33.3.8.3.82 EFI_IFR_TO_STRING
Summary
Pop a value, convert to a string, push the result.
Prototype
#define EFI_IFR_TO_STRING_OP 0x49
typedef struct _EFI_IFR_TO_STRING{
} EFI_IFR_TO_STRING;
Members
Header.OpCode = EFI_IFR_TO_STRING_OP
33.3. Code Deﬁnitions 1600Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Format When converting from unsigned integers, these ﬂags control the format:
0 = unsigned decimal
1 = signed decimal
2 = hexadecimal (lower-case alpha)
3 = hexadecimal (upper-case alpha)
When converting from a buffer, these ﬂags control the format:
0 = ASCII
8 = UCS-2
1. Pop a value from the expression stack.**
#. If the value is Undeﬁned or cannot be evaluated as a string, push Undeﬁned.
1. Convert the value to a string. When converting from an unsigned integer, the number will be converted to a
unsigned decimal string (Format = 0), signed decimal string (Format = 1) or a hexadecimal string (Format = 2
or 3).
When converting from a boolean, the boolean will be converted to “True” (True) or “False” (False). When converting
from a buffer, each 8-bit (Format = 0) or 16-bit (Format = 8) value will be converted into a character and appended to
the string, up until the end of the buffer or a NULL character. 4. Push the result.
33.3.8.3.83 EFI_IFR_TO_UINT
Summary
Pop a value, convert to an unsigned integer, push the result.
Prototype
#define EFI_IFR_TO_UINT_OP 0x48
typedef struct _EFI_IFR_TO_UINT {
} EFI_IFR_TO_UINT;
Members
Header.OpCode = EFI_IFR_TO_UINT_OP
2. If the value is Undeﬁned or cannot be evaluated as an unsigned integer, push Undeﬁned.
33.3. Code Deﬁnitions 1601Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3. Convert the value to an unsigned integer. When converting from a boolean, if TRUE , push 1 and if FALSE , push
0. When converting from a string, whitespace is skipped. The preﬁx ‘0x’ or ‘0X’ indicates to convert from a
hexadecimal string while the preﬁx ‘-‘ indicates conversion from a signed integer string. When converting from
a buffer, if the buffer is greater than 8 bytes in length, push Undeﬁned. Otherwise, zero-extend the contents of
the buffer to 64-bits.
4. Push the result.
33.3.8.3.84 EFI_IFR_TO_UPPER
Summary
Convert a string on the expression stack to upper case.
Prototype
#define EFI_IFR_TO_UPPER_OP 0x21
typedef struct _EFI_IFR_TO_UPPER {
} EFI_IFR_TO_UPPER;
Members
Header.OpCode = EFI_IFR_TO_UPPER_OP
string, push Undeﬁned. Otherwise, convert the string to all upper case using the StrUpr function of the
33.3.8.3.85 EFI_IFR_TRUE
Summary
Push a TRUE on to the expression stack.
Prototype
#define EFI_IFR_TRUE_OP 0x46
typedef struct _EFI_IFR_TRUE {
} EFI_IFR_TRUE;
Members
Header.OpCode = EFI_IFR_TRUE_OP
33.3. Code Deﬁnitions 1602Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.86 EFI_IFR_UINT8, EFI_IFR_UINT16,EFI_IFR_UINT32, EFI_IFR_UINT64
Summary
Push an unsigned integer on to the expression stack.
Prototype
#define EFI_IFR_UINT8_OP 0x42
typedef struct _EFI_IFR_UINT8 {
UINT8 Value;
} EFI_IFR_UINT8;
#define EFI_IFR_UINT16_OP 0x43
typedef struct _EFI_IFR_UINT16 {
} EFI_IFR_UINT16;
#define EFI_IFR_UINT32_OP 0x44
typedef struct _EFI_IFR_UINT32 {
} EFI_IFR_UINT32;
#define EFI_IFR_UINT64_OP 0x45
typedef struct _EFI_IFR_UINT64 {
UINT64 Value;
} EFI_IFR_UINT64;
Members
For this tag, Header.OpCode = EFI_IFR_UINT8_OP , EFI_IFR_UINT16_OP , EFI_IFR_UINT32_OP or
EFI_IFR_UINT64_OP .
Value The unsigned integer.
Push the speciﬁed unsigned integer, zero-extended to 64-bits, on to the expression stack.
33.3.8.3.87 EFI_IFR_UNDEFINED
Summary
Push an Undeﬁned to the expression stack.
Prototype
#define EFI_IFR_UNDEFINED_OP 0x55
typedef struct _EFI_IFR_UNDEFINED {
} EFI_IFR_UNDEFINED;
Members
33.3. Code Deﬁnitions 1603Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Header.OpCode = EFI_IFR_UNDEFINED_OP
Push Undeﬁned on to the expression stack.
33.3.8.3.88 EFI_IFR_VALUE
Summary
Prototype
#define EFI_IFR_VALUE_OP 0x5a
typedef struct _EFI_IFR_VALUE {
} EFI_IFR_VALUE;
Members
Header.OpCode = EFI_IFR_VALUE_OP
Creates a value for the current question or default with no storage. The value is the result of the expression nested in
the scope.
If used for a question, then the question will be read-only.
33.3.8.3.89 EFI_IFR_VARSTORE
Summary
Creates a variable storage short-cut for linear buffer storage.
Prototype
#define EFI_IFR_VARSTORE_OP 0x24
UINT16 Size;
//UINT8 Name[];
} EFI_IFR_VARSTORE;
Members
Header The byte sequence that deﬁnes the type of opcode as well as the length of the opcode being deﬁned. For this
tag,Header.OpCode =EFI_IFR_VARSTORE_OP .
Guid The variable’s GUID deﬁnition. This ﬁeld comprises one half of the variable name, with the other half being
the human-readable aspect of the name, which is represented by the string immediately following the Size ﬁeld.
Type EFI_GUID is deﬁned in InstallProtocolInterface() in this speciﬁcation.
33.3. Code Deﬁnitions 1604Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
VarStoreId The variable store identiﬁer, which is unique within the current form set. This ﬁeld is the value that
uniquely identify this instance from others. Question headers refer to this value to designate which is the active
variable that is being used. A value of zero is invalid.
Size The size of the variable store.
Name A null-terminated ASCII string that speciﬁes the name associated with the variable store. The ﬁeld is not
actually included in the structure but is included here to help illustrate the encoding of the opcode. The size of
the string, including the null termination, is included in the opcode’s header size.
This opcode describes a Buffer Storage Variable Store within a form set. A question can select this variable store by
setting the VarStoreId ﬁeld in its opcode header.
AnEFI_IFR_VARSTORE with a speciﬁed VarStoreId must appear in the IFR before it can be referenced by a question.
33.3.8.3.90 EFI_IFR_VARSTORE_NAME_VALUE
Summary
Creates a variable storage short-cut for name/value storage.
Prototype
#define EFI_IFR_VARSTORE_NAME_VALUE_OP 0x25
typedef struct _EFI_IFR_VARSTORE_NAME_VALUE {
} EFI_IFR_VARSTORE_NAME_VALUE;
Members
tag,Header.OpCode =EFI_IFR_VARSTORE_NAME_VALUE_OP .

Summary
Prototype
Members
the human-readable aspect of the name, which is speciﬁed in the VariableName ﬁeld in the question’s header
(see EFI_IFR_QUESTION_HEADER ). Type EFI_GUID is deﬁned in InstallProtocolInterface() in the UEFI
Speciﬁcation.
uniquely identiﬁes this variable store deﬁnition instance from others. Question headers refer to this value to
designate which is the active variable that is being used. A value of zero is invalid.
This opcode describes a Name/Value Variable Store within a form set. A question can select this variable store by
setting the VarStoreId ﬁeld in its question header.
AnEFI_IFR_VARSTORE_NAME_VALUE with a speciﬁed VarStoreId must appear in the IFR before it can be refer-
enced by a question.
33.3. Code Deﬁnitions 1605Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.91 EFI_IFR_VARSTORE_EFI
Summary
Creates a variable storage short-cut for EFI variable storage.
Prototype
#define EFI_IFR_VARSTORE_EFI_OP 0x26
typedef struct _EFI_IFR_VARSTORE_EFI {
UINT32 Attributes
} EFI_IFR_VARSTORE_EFI;
Members
tag,Header.OpCode =EFI_IFR_VARSTORE_EFI_OP .
Guid The EFI variable’s GUID deﬁnition. This ﬁeld comprises one half of the EFI variable name, with the other half
being the human-readable aspect of the name, which is speciﬁed in the Name ﬁeld below. Type EFI_GUID is
deﬁned in InstallProtocolInterface() in this speciﬁcation.
Attributes Speciﬁes the ﬂags to use for the variable.
Name A null-terminated ASCII string that speciﬁes one half of the EFI name for this variable store. The other half is
speciﬁed in the Guid ﬁeld (above). The Name ﬁeld is not actually included in the structure but is included here
to help illustrate the encoding of the opcode. The size of the string, including the null termination, is included
in the opcode’s header size.
This opcode describes an EFI Variable Variable Store within a form set. The Guid and Name speciﬁed here will be
used with GetVariable() andSetVariable().
• A question can select this variable store by setting the VarStoreId ﬁeld in its question header.
• A question can refer to a speciﬁc offset within the EFI Variable using the VarOffset ﬁeld in its question header.
•Name must be converted to a CHAR16 string before it is passed to GetVariable() orSetVariable(). An
EFI_IFR_VARSTORE_EFI with a speciﬁed VarStoreId must appear in the IFR before it can be referenced by a
question.
33.3. Code Deﬁnitions 1606Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.92 EFI_IFR_VARSTORE_DEVICE
Summary
Select the device which contains the variable store.
Prototype
#define EFI_IFR_VARSTORE_DEVICE_OP 0x27
typedef struct _EFI_IFR_VARSTORE_DEVICE {
} EFI_IFR_VARSTORE_DEVICE;
Members
tag,Header.OpCode =EFI_IFR_VARSTORE_DEVICE_OP .
DevicePath Speciﬁes the string which contains the device path of the device where the variable store resides.
This opcode describes the device path where a variable store resides. Normally, the Forms Processor ﬁnds the variable
store on the handle speciﬁed when the HII database function NewPackageList() was called. However, if this opcode is
found in the scope of a question, the handle speciﬁed by the text device path DevicePath is used instead.
33.3.8.3.93 EFI_IFR_VERSION
Summary
Push the version of the UEFI speciﬁcation to which the Forms Processor conforms.
Prototype
#define EFI_IFR_VERSION_OP 0x28
typedef struct _EFI_IFR_VERSION {
} EFI_IFR_VERSION;
Members
Header.OpCode = EFI_IFR_VERSION_OP .
Returns the revision level of the UEFI speciﬁcation with which the Forms Processor is compliant as a 16-bit unsigned
integer, with the form:
[15:8] Major revision
[7:4] Tens digit of the minor revision
[3:0] Ones digit of the minor revision
The ﬁelds of the version have the following correlation with the revision of the UEFI system table.
Major revision: EFI_SYSTEM_TABLE_REVISION >> 16
33.3. Code Deﬁnitions 1607Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Tens digit of the minor revision: (EFI_SYSTEM_TABLE_REVISION & 0xFFFF)/10
Ones digit of the minor revision: (EFI_SYSTEM_TABLE_REVISION & 0xFFFF)%10
33.3.8.3.94 EFI_IFR_WRITE
Summary
Change a value for the current question.
Prototype
#define EFI_IFR_WRITE_OP 0x2E
typedef struct _EFI_IFR_WRITE {
} EFI_IFR_WRITE;
Header.OpCode = EFI_IFR_WRITE_OP
Before writing the value of the current question to storage (if any storage was speciﬁed), the thisconstant is set (see
EFI_IFR_THIS ) and then this expression is evaluated.
33.3.8.3.95 EFI_IFR_ZERO
Summary
Push a zero on to the expression stack.
Prototype
#define EFI_IFR_ZERO_OP 0x52
typedef struct _EFI_IFR_ZERO {
} EFI_IFR_ZERO;
Members
Header.OpCode = EFI_IFR_ZERO_OP
33.3. Code Deﬁnitions 1608Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.8.3.96 EFI_IFR_WARNING_IF
Summary
Creates a validation expression and warning message for a question.
Prototype
#define EFI_IFR_WARNING_IF_OP 0x063
typedef struct _EFI_IFR_WARNING_IF {
EFI_STRING_ID Warning;
UINT8 TimeOut;
} EFI_IFR_WARNING_IF;
Members
Header.OpCode = EFI_IFR_WARNING_IF_OP .
Warning The string token reference to the string that will be used for the warning check message.
TimeOut The number of seconds for the warning message to be displayed before it is timed out or acknowledged by
the user. A value of zero indicates that the message is displayed indeﬁnitely until the user acknowledges it.
This tag uses a Boolean expression to allow the IFR creator to check options in a question, and provide a warning
message if the expression is TRUE . For example, this tag might be used to give a warning if the user attempts to
disable a security setting, or change the value of a sensitive question. The tag provides a string to be used in a warning
display to alert the user of the consequences of changing the question value. Warning tags will be evaluated when
the user traverses from tag to tag. The browser must display the warning text message and not allow the form to be
submitted until either the user acknowledges the message (with some key press for instance) or the number of seconds
in TimeOut elapses. Unlike inconsistency tags, the user should still be allowed to submit the results of a form even if
the warning expression evaluates to TRUE .
33.3.8.3.97 EFI_IFR_MATCH2
Summary
Pop a source string and a pattern string, push TRUE if the source string matches the Regular Expression pattern
speciﬁed by the pattern string, otherwise push FALSE .
Prototype
#define EFI_IFR_MATCH2_OP 0x64
typedef struct _EFI_IFR_MATCH2 {
EFI_GUID SyntaxType;
} EFI_IFR_MATCH2;
Members
Header Standard opcode header, where Header.Opcode isEFI_IFR_MATCH2_OP .
SyntaxType A GUID that identiﬁes the regular expression syntax type to use for the pattern string. See
EFI_REGULAR_EXPRESSION_PROTOCOL for current syntax deﬁnitions.
33.3. Code Deﬁnitions 1609Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
1. Pop two values from the expression stack. Theﬁrst value popped is the string and the secondvalue popped is the
pattern.
3. Call GetInfo function of each instance of EFI_REGULAR_EXPRESSION_PROTOCOL, looking for a Syntax-

Prototype
Members
pattern.
Type that is listed in the set of supported regular expression syntax types returned by RegExSyntaxTypeList. If
the type speciﬁed by SyntaxType is not supported in any of the EFI_REGULAR_EXPRESSION_PROTOCOL
instances, or no EFI_REGULAR_EXPRESSION_PROTOCOL instance was found, push Undeﬁned.
4. Process the string and pattern using the MatchString function of the
EFI_REGULAR_EXPRESSION_PROTOCOL instance that supports the SyntaxType, where SyntaxType is
theSyntaxType input to MatchString.
5. If the returned regular expression Result isTRUE , then push TRUE.
6. If the return regular expression Result isFALSE, then push FALSE.
NOTE: To ensure interoperability, drivers that publish HII IFR Forms packages should check the system capabil-
ities by calling the GetInfo function of each EFI_REGULAR_EXPRESSION_PROTCOL instance during initial-
ization. If the required regular expression syntax type is not supported, the driver may install its own instance of
EFI_REGULAR_EXPRESSION_PROTCOL to add the support. The driver may also choose to fall back to other
methods of validation, such as using EFI_IFR_MATCH or callbacks .
33.3.9 Keyboard Package
// EFI_HII_KEYBOARD_PACKAGE_HDR
EFI_HII_PACKAGE_HDR Header;
UINT16 LayoutCount;
//EFI_HII_KEYBOARD_LAYOUT Layout[];
} EFI_HII_KEYBOARD_PACKAGE_HDR;
Header The general pack header which deﬁnes both the type of pack and the length of the entire pack.
LayoutCount The number of keyboard layouts contained in the entire keyboard pack.
Layout An array of LayoutCount number of keyboard layouts.
33.3.10 Animations Package
The Animation package record describes how, when, and which EFI images to display. The package consists of two
parts: a ﬁxed header and the animation information.
33.3.10.1 Animated Images Package
Summary
The ﬁxed header consists of a standard record header and the
Prototype
33.3. Code Deﬁnitions 1610Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct _EFI_HII_ANIMATION_PACKAGE_HDR {
EFI_HII_ANIMATION_PACKAGE Header;
UINT32 AnimationInfoOffset;
} EFI_HII_ANIMATION_PACKAGE_HDR;
Members
Header Standard image header, where Header.BlockType = EFI_HII_PACKAGE_ANIMATIONS.
AnimationInfoOffset Offset, relative to this header, of the animation information. If this is zero, then there are no
animation sequences in the package.
33.3.10.2 Animation Information
For each animated image identiﬁer, the animation information gives a sequence of EFI images to display and
how and when to transition to the next image. The animation information is encoded as a series of blocks, with
each block preﬁxed by a single byte header ( EFI_HII_ANIMATION_BLOCK ) or one of the extension headers (
EFI_HII_AIBT_EXTx_BLOCK ). The blocks must be processed in order.
Fig. 33.50: Animation Information Encoded in Blocks
Prototype
typedef struct _EFI_HII_ANIMATION_BLOCK {
//UINT8 BlockBody[];
} EFI_HII_ANIMATION_BLOCK;
33.3. Code Deﬁnitions 1611Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 33.22: Animation Block Types
EFI_HII_AIBT_END 0x00 The end of the animation information.
EFI_HII_AIBT_OVERLAY_IMAGES 0x10 Animate sequence once by displaying the
next image in the logical window.
EFI_HII_AIBT_CLEAR_IMAGES 0x11 Animate sequence once by clearing the log-
ical window before displaying the next im-
age.
EFI_HII_AIBT_RESTORE_SCRN 0x12 Animate sequence once by clearing the
restoring the logical window before display-
ing the next image.
EFI_HII_AIBT_OVERLAY_IMAGES_LOOP 0x18 Animate repeating sequence by displaying
the next image in the logical window.
EFI_HII_AIBT_CLEAR_IMAGES_LOOP 0x19 Animate repeating sequence by clearing the
logical window before displaying the next
image.
EFI_HII_AIBT_RESTORE_SCRN_LOOP 0x1A Animate repeating sequence by clearing the
EFI_HII_AIBT_DUPLICATE 0x20 Duplicate an existing animation identiﬁer
EFI_HII_AIBT_SKIP2 0x21 Skip a certain number of animation identi-
ﬁers.
EFI_HII_AIBT_SKIP1 0x22 Skip a certain number of animation identi-
ﬁers.
EFI_HII_AIBT_EXT1 0x30 For future expansion (one byte length ﬁeld)
EFI_HII_AIBT_EXT2 0x31 For future expansion (two byte length ﬁeld)
EFI_HII_AIBT_EXT4 0x32 For future expansion (four byte length ﬁeld)
In order to recreate all animation sequences, start at the ﬁrst block and process them all until either an
EFI_HII_AIBT_END block is found. When processing the animation blocks, each block refers to the current ani-
mation identiﬁer ( AnimationIdCurrent ), which is initially set to one (1).
Animation blocks of an unknown type should be skipped. If they cannot be skipped, then processing halts.
33.3.10.2.1 EFI_HII_AIBT_END
Summary
Marks the end of the animation information.
Prototype
None
Members
Header Standard animation header, where Header.BlockType = EFI_HII_AIBT_END.
Discussion
Any animation sequences with an animation identiﬁer greater than or equal to AnimationIdCurrent are empty. There
is no additional data.
33.3. Code Deﬁnitions 1612Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.10.2.2 EFI_HII_AIBT_EXT1, EFI_HII_AIBT_EXT2,EFI_HII_AIBT_EXT4
Summary
Generic preﬁx for animation information with a 1-byte,2-byte or 4-byte length.
Prototype
typedef struct _EFI_HII_AIBT_EXT1_BLOCK {
EFI_HII_ANIMATION_BLOCK Header;
} EFI_HII_AIBT_EXT1_BLOCK;
typedef struct _EFI_HII_AIBT_EXT2_BLOCK {
} EFI_HII_AIBT_EXT2_BLOCK;
typedef struct _EFI_HII_AIBT_EXT4_BLOCK {
} EFI_HII_AIBT_EXT4_BLOCK;
Members
Header Standard animation header, where Header.BlockType = EFI_HII_AIBT_EXT1, EFI_HII_AIBT_EXT2, or
EFI_HII_AIBT_EXT4.
Length Size of the animation block, in bytes, including the animation block header.
BlockType2 The block type, as described in Table 33.18
These records are used for variable sized animation records which need an explicit length.
33.3.10.2.3 EFI_HII_AIBT_OVERLAY_IMAGES
Summary
An animation block to describe an animation sequence that does not cycle, and where one image is simply displayed
over the previous image.
Prototype
typedef struct _EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK {
EFI_IMAGE_ID DftImageId;
UINT16 CellCount;
EFI_HII_ANIMATION_CELL AnimationCell[];
} EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK;
Members
DftImageId This is image that is to be reference by the image protocols, if the animation function is not supported
or disabled. This image can be one particular image from the animation sequence (if any one of the animation
33.3. Code Deﬁnitions 1613Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
frames has a complete image) or an alternate image that can be displayed alone. If the value is zero, no image is
displayed.
Width The overall width of the set of images (logical window width).
Height The overall height of the set of images (logical window height).
CellCount The number of EFI_HII_ANIMATION_CELL contained in the animation sequence.
AnimationCell An array of CellCount animation cells. The type EFI_HII_ANIMATION_CELL is deﬁned in “Related
This record assigns the animation sequence data to the AnimationIdCurrent identiﬁer and increment AnimationIdCur-
rentby one. This animation sequence is meant to be displayed only once (it is not a repeating sequence). Each image
in the sequence will remain on the screen for the speciﬁed delay before the next image in the sequence is displayed.
The header type (either BlockType in EFI_HII_ANIMATION_BLOCK or BlockType2 in
EFI_HII_AIBT_EXTx_BLOCK ) will be set to EFI_HII_AIBT_OVERLAY_IMAGES.
typedef struct _EFI_HII_ANIMATION_CELL {
UINT16 OffsetX;
UINT16 OffsetY;
UINT16 Delay;
} EFI_HII_ANIMATION_CELL;
OffsetX The X offset from the upper left hand corner of the logical window to position the indexed image.
OffsetY The Y offset from the upper left hand corner of the logical window to position the indexed image.
ImageId The image to display at the speciﬁed offset from the upper left hand corner of the logical window.
Delay The number of milliseconds to delay after displaying the indexed image and before continuing on to the next
linked image. If value is zero, no delay.
The logical window deﬁnition allows the animation to be centered, even though the ﬁrst image might be way off center
(bounds the sequence of images). All images will be clipped to the deﬁned logical window, since the logical window
is suppose to bound all images, normally there is nothing to clip. The DftImageId deﬁnition allows an alternate image
to be displayed if animation is currently not supported. The DftImageId image is to be centered in the deﬁned logical
window.
33.3.10.2.4 EFI_HII_AIBT_CLEAR_IMAGES

window.
Summary
An animation block to describe an animation sequence that does not cycle, and where the logical window is cleared to
the speciﬁed color before the next image is displayed.
Prototype
typedef struct _EFI_HII_AIBT_CLEAR_IMAGES_BLOCK {
33.3. Code Deﬁnitions 1614Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_HII_RGB_PIXEL BackgndColor;
} EFI_HII_AIBT_CLEAR_IMAGES_BLOCK;
Members
BackgndColor The color to clear the logical window to before displaying the indexed image.
Deﬁnitions” in EFI_HII_AIBT_OVERLAY_IMAGES.
rent by one. This animation sequence is meant to be displayed only once (it is not a repeating sequence). Each image
in the sequence will remain on the screen for the speciﬁed delay before the logical window is cleared to the speciﬁed
color (BackgndColor) and the next image is displayed. The logical window is also cleared to the speciﬁed color before
displaying the DftImageId image.
EFI_HII_AIBT_EXTx_BLOCK) will be set to EFI_HII_AIBT_CLEAR_IMAGES.
33.3.10.2.5 EFI_HII_AIBT_RESTORE_SCRN
Summary
An animation block to describe an animation sequence that does not cycle, and where the screen is restored to the
original state before the next image is displayed.
Prototype
typedef struct _EFI_HII_AIBT_RESTORE_SCRN_BLOCK {
} EFI_HII_AIBT_RESTORE_SCRN_BLOCK;
Members
33.3. Code Deﬁnitions 1615Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
rentby one. This animation sequence is meant to be displayed only once (it is not a repeating sequence). Before the
ﬁrst image is displayed, the entire deﬁned logical window is saved to a buffer. Then each image in the sequence will
remain on the screen for the speciﬁed delay before the logical window is restored to the original state and the next
image is displayed.
If memory buffers are not available to save the logical window, this structure is treated as
EFI_HII_AIBT_CLEAR_IMAGES structure, with the BackgndColor value set to black.
EFI_HII_AIBT_EXTx_BLOCK ) will be set to EFI_HII_AIBT_RESTORE_SCRN.
33.3.10.2.6 EFI_HII_AIBT_OVERLAY_IMAGES_LOOP
Summary
An animation block to describe an animation sequence that continuously cycles, and where one image is simply
displayed over the previous image.
Prototype
typedef EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK
EFI_HII_AIBT_OVERLAY_IMAGES_LOOP_BLOCK {
} EFI_HII_AIBT_OVERLAY_IMAGES_LOOP_BLOCK;
Members
Deﬁnitions” in EFI_HII_AIBT_OVERLAY_IMAGES
33.3. Code Deﬁnitions 1616Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
rent by one. This animation sequence is meant to continuously cycle until stopped or paused. Each image in the
sequence will remain on the screen for the speciﬁed delay before the next image in the sequence is displayed.
EFI_HII_AIBT_EXTx_BLOCK ) will be set to EFI_HII_AIBT_OVERLAY_IMAGES_LOOP .
33.3.10.2.7 EFI_HII_AIBT_CLEAR_IMAGES_LOOP
Summary
An animation block to describe an animation sequence that continuously cycles, and where the logical window is
cleared to the speciﬁed color before the next image is displayed.
Prototype
typedef EFI_HII_AIBT_CLEAR_IMAGES_BLOCK EFI_HII_AIBT_CLEAR_IMAGES_LOOP_BLOCK {
} EFI_HII_AIBT_CLEAR_IMAGES_LOOP_BLOCK;
Members
sequence will remain on the screen for the speciﬁed delay before the logical window is cleared to the speciﬁed color
(BackgndColor) and the next image is displayed. The logical window is also cleared to the speciﬁed color before
EFI_HII_AIBT_EXTx_BLOCK ) will be set to EFI_HII_AIBT_CLEAR_IMAGES_LOOP .
33.3. Code Deﬁnitions 1617Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.10.2.8 EFI_AIBT_RESTORE_SCRN_LOOP
Summary
An animation block to describe an animation sequence that continuously cycles, and where the screen is restored to
the original state before the next image is displayed.
Prototype
typedef EFI_HII_AIBT_RESTORE_SCRN_LOOP_BLOCK
EFI_HII_AIBT_RESTORE_SCRN_LOOP_BLOCK {
} EFI_HII_AIBT_RESTORE_SCRN_LOOP_BLOCK;
Members
Header Standard image header, where Header.BlockType = EFI_HII_AIBT_RESTORE_SCRN_LOOP .

Prototype
Members
rent by one. This animation sequence is meant to continuously cycle until stopped or paused. Before the ﬁrst image
is displayed, the entire deﬁned logical window is saved to a buffer. Then each image in the sequence will remain
on the screen for the speciﬁed delay before the logical window is restored to the original state and the next image is
EFI_HII_AIBT_CLEAR_IMAGES_LOOP structure, with the BackgndColor value set to black.
EFI_HII_AIBT_EXTx_BLOCK ) will be set to EFI_HII_AIBT_RESTORE_SCRN_LOOP .
33.3. Code Deﬁnitions 1618Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
33.3.10.2.9 EFI_HII_AIBT_DUPLICATE
Summary
Assigns a new character value to a previously deﬁned animation sequence.
Prototype
typedef struct _EFI_HII_AIBT_DUPLICATE_BLOCK {
EFI_ANIMATION_ID AnimationId;
} EFI_HII_AIBT_DUPLICATE_BLOCK;
Members
AnimationId The previously deﬁned animation ID with the exact same animation information.
Indicates that the animation sequence with animation ID AnimationIdCurrent has the same animation information as
a previously deﬁned animation ID and increments AnimationIdCurrent by one.
EFI_HII_AIBT_EXTx_BLOCK ) will be set to EFI_HII_AIBT_DUPLICATE.
33.3.10.2.10 EFI_HII_AIBT_SKIP1
Summary
Skips animation IDs.
Prototype
typedef struct _EFI_HII_AIBT_SKIP1_BLOCK {
} EFI_HII_AIBT_SKIP1_BLOCK;
Members
SkipCount The unsigned 8-bit value to add to AnimationIdCurrent.
Increments the current animation ID AnimationIdCurrent by the number speciﬁed. The header type (either
BlockType inEFI_HII_ANIMATION_BLOCK orBlockType2 inEFI_HII_AIBT_EXTx_BLOCK ) will be set to
EFI_HII_AIBT_SKIP1.
33.3.10.2.11 EFI_HII_AIBT_SKIP2
Summary
Prototype
typedef struct _EFI_HII_AIBT_SKIP2_BLOCK {
} EFI_HII_AIBT_SKIP2_BLOCK;
Members
33.3. Code Deﬁnitions 1619Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
SkipCount The unsigned 16-bit value to add to AnimationIdCurrent.
Increments the current animation ID AnimationIdCurrent by the number speciﬁed.
EFI_HII_AIBT_EXTx_BLOCK ) will be set to EFI_HII_AIBT_SKIP2.
33.3. Code Deﬁnitions 1620CHAPTER
THIRTYFOUR
HII PROTOCOLS
This section provides code deﬁnitions for the HII-related protocols, functions, and type deﬁnitions, which are the
required architectural mechanisms by which UEFI-compliant systems manage user input. The major areas described
include the following:
• Font management.
• String management.
• Image management.
• Database management.
34.1 Font Protocol
34.1.1 EFI_HII_FONT_PROTOCOL
Summary
Interfaces which retrieve font information.
GUID
#define EFI_HII_FONT_PROTOCOL_GUID \
{ 0xe9ca4775, 0x8657, 0x47fc, \
{0x97, 0xe7, 0x7e, 0xd6, 0x5a, 0x8, 0x43, 0x24 }}
Protocol
typedef struct _EFI_HII_FONT_PROTOCOL {
EFI_HII_STRING_TO_IMAGE StringToImage;
EFI_HII_STRING_ID_TO_IMAGE StringIdToImage;
EFI_HII_GET_GLYPH GetGlyph;
EFI_HII_GET_FONT_INFO GetFontInfo;
} EFI_HII_FONT_PROTOCOL;
Members
StringToImage, StringIdToImage Render a string to a bitmap or to the display.
GetGlyph Return a speciﬁc glyph in a speciﬁc font.
GetFontInfo Return font information for a speciﬁc font.
1621Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.1.2 EFI_HII_FONT_PROTOCOL.StringToImage()
Summary
Renders a string to a bitmap or to the display.
Prototype
typedef
(EFIAPI *EFI_HII_STRING_TO_IMAGE) (
IN CONST EFI_HII_FONT_PROTOCOL *This,
IN EFI_HII_OUT_FLAGS Flags,
IN CONST EFI_STRING String,
IN CONST EFI_FONT_DISPLAY_INFO *StringInfo OPTIONAL,
IN OUT EFI_IMAGE_OUTPUT **Blt,
IN UINTN BltX,
IN UINTN BltY,
OUT EFI_HII_ROW_INFO **RowInfoArray OPTIONAL,
OUT UINTN *RowInfoArraySize OPTIONAL,
OUT UINTN *ColumnInfoArray OPTIONAL
):
This A pointer to the EFI_HII_FONT_PROTOCOL instance.
Flags Describes how the string is to be drawn. EFI_HII_OUT_FLAGS is deﬁned in Related Deﬁnitions, below.
String Points to the null-terminated string to be displayed.
StringInfo Points to the string output information, including the color and font. If NULL, then the string will be
output in the default system font and color.
BltIf this points to a non-NULL on entry, this points to the image, which is Blt.Width pixels wide and Blt.Height
pixels high. The string will be drawn onto this image and EFI_HII_OUT_FLAG_CLIP is implied. If this points
to a NULL on entry, then a buffer will be allocated to hold the generated image and the pointer updated on exit.
It is the caller’s responsibility to free this buffer.
BltX, BltY Speciﬁes the offset from the left and top edge of the image of the ﬁrst character cell in the image.
RowInfoArray If this is non-NULL on entry, then on exit, this will point to an allocated buffer containing row
information and RowInfoArraySize will be updated to contain the number of elements. This array describes the
characters which were at least partially drawn and the heights of the rows. It is the caller’s responsibility to free
this buffer.
RowInfoArraySize If this is non-NULL on entry, then on exit it contains the number of elements in RowInfoArray.
ColumnInfoArray If this is non-NULL, then on return it will be ﬁlled with the horizontal offset for each character
in the string on the row where it is displayed. Non-printing characters will have the offset ~0. The caller
is responsible to allocate a buffer large enough so that there is one entry for each character in the string, not
including the null-terminator. It is possible when character display is normalized that some character cells
overlap.
This function renders a string to a bitmap or the screen using the speciﬁed font, color and options. It either draws
the string and glyphs on an existing bitmap, allocates a new bitmap or uses the screen. The strings can be clipped or
wrapped. Optionally, the function also returns the information about each row and the character position on that row.
IfEFI_HII_OUT_FLAG_CLIP is set, then text will be formatted only based on explicit line breaks and all pixels
which would lie outside the bounding box speciﬁed by Blt.Width andBlt.Height are ignored. The information in
34.1. Font Protocol 1622Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
theRowInfoArray only describes characters which are at least partially displayed. For the ﬁnal row, the RowInfoAr-
ray.LineHeight andRowInfoArray.BaseLine may describe pixels which are outside the limit speciﬁed by Blt. Height
(unless EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is speciﬁed) even though those pixels were not drawn. The LineWidth
may describe pixels which are outside the limit speciﬁed by Blt.Width (unless EFI_HII_OUT_FLAG_CLIP_CLEAN_X
is speciﬁed) even though those pixels were not drawn.
IfEFI_HII_OUT_FLAG_CLIP_CLEAN_X is set, then it modiﬁes the behavior of EFI_HII_OUT_FLAG_CLIP so
that if a character’s right-most on pixel cannot ﬁt, then it will not be drawn at all. This ﬂag requires that
EFI_HII_OUT_FLAG_CLIP be set.
IfEFI_HII_OUT_FLAG_CLIP_CLEAN_Y is set, then it modiﬁes the behavior of EFI_HII_OUT_FLAG_CLIP
so that if a row’s bottom-most pixel cannot ﬁt, then it will not be drawn at all. This ﬂag requires that
IfEFI_HII_OUT_FLAG_WRAP is set, then text will be wrapped at the right-most line-break opportunity prior
to a character whose right-most extent would exceed Blt.Width. If no line-break opportunity can be found,
then the text will behave as if EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set. This ﬂag cannot be used with
EFI_HII_OUT_FLAG_CLIP_CLEAN_X.
IfEFI_HII_OUT_FLAG_TRANSPARENT is set, then StringInfo.BackgroundColor is ignored and all “off” pixels in
the character’s drawn will use the pixel value from Blt.This ﬂag cannot be used if Bltis NULL upon entry.
IfEFI_HII_IGNORE_IF_NO_GLYPH is set, then characters which have no glyphs are not drawn. Otherwise, they
are replaced with Unicode character code 0xFFFD (REPLACEMENT CHARACTER).
IfEFI_HII_IGNORE_LINE_BREAK is set, then explicit line break characters will be ignored.
IfEFI_HII_DIRECT_TO_SCREEN is set, then the string will be written directly to the output device speciﬁed by
Screen. Otherwise the string will be rendered to the bitmap speciﬁed by Bitmap .
typedef UINT32 EFI_HII_OUT_FLAGS;
#define EFI_HII_OUT_FLAG_CLIP 0x00000001

#define EFI_HII_OUT_FLAG_WRAP 0x00000002
#define EFI_HII_OUT_FLAG_CLIP_CLEAN_Y 0x00000004
#define EFI_HII_OUT_FLAG_CLIP_CLEAN_X 0x00000008
#define EFI_HII_OUT_FLAG_TRANSPARENT 0x00000010
#define EFI_HII_IGNORE_IF_NO_GLYPH 0x00000020
#define EFI_HII_IGNORE_LINE_BREAK 0x00000040
#define EFI_HII_DIRECT_TO_SCREEN 0x00000080
typedef CHAR16 *EFI_STRING;
typedef struct _EFI_HII_ROW_INFO {
UINTN StartIndex;
UINTN EndIndex;
UINTN LineHeight;
UINTN LineWidth;
UINTN BaselineOffset;
} EFI_HII_ROW_INFO;
StartIndex The index of the ﬁrst character in the string which is displayed on the line.
EndIndex The index of the last character in the string which is displayed on the line.
LineHeight The height of the line, in pixels.
LineWidth The width of the text on the line, in pixels.
BaselineOffset The font baseline offset in pixels from the bottom of the row, or 0 if none.
34.1. Font Protocol 1623Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The string was successfully updated.
EFI_OUT_OF_RESOURCES Unable to allocate an output buffer for RowInfoArray orBlt.
EFI_INV ALID_PARAMETER TheString orBltwas NULL.
EFI_INV ALID_PARAMETER Flags were invalid combination
34.1.3 EFI_HII_FONT_PROTOCOL.StringIdToImage()
Summary
Render a string to a bitmap or the screen containing the contents of the speciﬁed string.
Prototype
typedef
(EFIAPI *EFI_HII_STRING_ID_TO_IMAGE) (
IN EFI_HII_HANDLE PackageList,
IN EFI_STRING_ID StringId,
IN CONST CHAR8 * Language,
);
PackageList The package list in the HII database to search for the speciﬁed string.
StringId The string’s id, which is unique within PackageList.
Language Points to the language for the retrieved string. If NULL, then the current system language is used.
BltIf this points to a non-NULL on entry, this points to the image, which is Blt.Width pixels wide and Height pixels
high. The string will be drawn onto this image and EFI_HII_OUT_FLAG_CLIP is implied. If this points to a
NULL on entry, then a buffer will be allocated to hold the generated image and the pointer updated on exit. It is
the caller’s responsibility to free this buffer.
BltX, BltY Speciﬁes the offset from the left and top edge of the output image of the ﬁrst character cell in the image.
34.1. Font Protocol 1624Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ColumnInfoArray If non-NULL, on return it is ﬁlled with the horizontal offset for each character in the string on the
row where it is displayed. Non-printing characters will have the offset ~0. The caller is responsible to allocate a
buffer large enough so that there is one entry for each character in the string, not including the null-terminator.
It is possible when character display is normalized that some character cells overlap.
This function renders a string as a bitmap or to the screen and can clip or wrap the string. The bitmap is either supplied
by the caller or else is allocated by the function. The strings are drawn with the font, size and style speciﬁed and can
be drawn transparently or opaquely. The function can also return information about each row and each character’s
position on the row.
IfEFI_HII_OUT_FLAG_CLIP is set, then text will be formatted only based on explicit line breaks and all pixels which
would lie outside the bounding box speciﬁed by Width andHeight are ignored. The information in the RowInfoArray
only describes characters which are at least partially displayed. For the ﬁnal row, the LineHeight and BaseLine may
describe pixels which are outside the limit speciﬁed by Height (unless EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is
speciﬁed) even though those pixels were not drawn.
EFI_HII_OUT_FLAG_CLIP be set. If EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is set, then it modiﬁes the behav-
ior of EFI_HII_OUT_FLAG_CLIP so that if a row’s bottom most pixel cannot ﬁt, then it will not be drawn at all. This
ﬂag requires that EFI_HII_OUT_FLAG_CLIP be set.
to a character whose right-most extent would exceed Width. If no line-break opportunity can be found,
EFI_HII_OUT_FLAG_CLIP_CLEAN_X .
IfEFI_HII_OUT_FLAG_TRANSPARENT is set, then BackgroundColor is ignored and all “off” pixels in the charac-
ter’s glyph will use the pixel value from Blt.This ﬂag cannot be used if Bltis NULL upon entry.
Screen. Otherwise the string will be rendered to the bitmap speciﬁed by Bitmap.
EFI_INV ALID_PARAMETER TheStringId orPackageList wasNULL.
EFI_INV ALID_PARAMETER Flags were invalid combination.
EFI_NOT_FOUND TheStringId is not in the speciﬁed PackageList. The speciﬁed PackageList
is not in the Database.
34.1. Font Protocol 1625Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.1.4 EFI_HII_FONT_PROTOCOL.GetGlyph()
Summary
Return image and information about a single glyph.
Prototype
typedef
(EFIAPI *EFI_HII_GET_GLYPH) (
IN CHAR16 Char,
IN CONST EFI_FONT_DISPLAY_INFO *StringInfo,
OUT EFI_IMAGE_OUTPUT **Blt;
OUT UINTN *Baseline OPTIONAL;
);
Char Character to retrieve.
StringInfo Points to the string font and color information or NULL if the string should use the default system font
and color.
BltThus must point to a NULL on entry. A buffer will be allocated to hold the output and the pointer updated on exit.
It is the caller’s responsibility to free this buffer.On return, only Blt.Width, Blt.Height, andBlt.Image.Bitmap are
valid.
Baseline Number of pixels from the bottom of the bitmap to the baseline.
Convert the glyph for a single character into a bitmap.
EFI_SUCCESS Glyph bitmap created.
EFI_OUT_OF_RESOURCES Unable to allocate the output buffer Blt.
EFI_WARN_UNKNOWN_GLYPH The glyph was unknown and was replaced with the glyph for Unicode char-
acter code 0xFFFD.
EFI_INV ALID_PARAMETER Bltis NULL or * Bltis !Null
34.1.5 EFI_HII_FONT_PROTOCOL.GetFontInfo()
Summary
Return information about a particular font.
Prototype
typedef
(EFIAPI *EFI_HII_GET_FONT_INFO) (
IN OUT EFI_FONT_HANDLE *FontHandle,
IN CONST EFI_FONT_DISPLAY_INFO *StringInfoIn,OPTIONAL
34.1. Font Protocol 1626Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
OUT EFI_FONT_DISPLAY_INFO **StringInfoOut,
IN CONST EFI_STRING String OPTIONAL
);
typedef VOID *EFI_FONT_HANDLE;
FontHandle On entry, points to the font handle returned by a previous call to GetFontInfo() or points to NULL to
start with the ﬁrst font. On return, points to the returned font handle or points to NULL if there are no more
matching fonts.
StringInfoIn Upon entry, points to the font to return information about. If NULL, then the information about the
system default font will be returned.

Summary
Prototype
typedef
);
StringInfoOut Upon return, contains the matching font’s information. If NULL, then no information is returned.
This buffer is allocated with a call to the Boot Service AllocatePool(). It is the caller’s responsibility to call the
Boot Service FreePool() when the caller no longer requires the contents of StringInfoOut.
String Points to the string which will be tested to determine if all characters are available. If NULL , then any font is
acceptable.
This function iterates through fonts which match the speciﬁed font, using the speciﬁed criteria. If String is non-NULL,
then all of the characters in the string must exist in order for a candidate font to be returned.
EFI_SUCCESS Matching font returned successfully.
EFI_NOT_FOUND No matching font was found.
EFI_OUT_OF_RESOURCES There were insufﬁcient resources to complete the request.
34.2 EFI HII Font Ex Protocol
The EFI HII Font Ex protocol deﬁnes an extension to the EFI HII Font protocol which enables various new capabilities
described in this section.
34.2.1 EFI_HII_FONT_EX_PROTOCOL
Summary
Interfaces which retrieve the font information.
GUID
#define EFI_HII_FONT_EX_PROTOCOL_GUID \
{ 0x849e6875, 0xdb35, 0x4df8, 0xb4, \
{0x1e, 0xc8, 0xf3, 0x37, 0x18, 0x7, 0x3f }}
Protocol
34.2. EFI HII Font Ex Protocol 1627Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef struct _EFI_HII_FONT_EX_PROTOCOL {
EFI_HII_STRING_TO_IMAGE_EX StringToImageEx;
EFI_HII_STRING_ID_TO_IMAGE_EX StringIdToImageEx;
EFI_HII_GET_GLYPH_EX GetGlyphEx;
EFI_HII_GET_FONT_INFO_EX GetFontInfoEx;
EFI_HII_GET_GLYPH_INFO GetGlyphInfo;
} EFI_HII_FONT_EX_PROTOCOL;
Members
StringToImageEx, StringIdToImageEx Render a string to a bitmap or to the display. This function will try to use
the external font glyph generator for generating the glyph if it can’t ﬁnd the glyph in the font database.
GetGlphyEx Return a speciﬁc glyph in a speciﬁc font. This function will try to use the external font glyph generator
for generating the glyph if it can’t ﬁnd the glyph in the font database.
GetFontInfoEx Return the font information for a speciﬁc font, this protocol invokes original
EFI_HII_FONT_PROTOCOL.GetFontInfo() implicitly.
GetGlphyInfoEx Return the glyph information for the single glyph.
34.2.2 EFI_HII_FONT_EX_PROTOCOL.StringToImageEx()
Summary
Render a string to a bitmap or to the display. The prototype of this extension function is the same with
EFI_HII_FONT_PROTOCOL.StringToImage().
Protocol
typedef
(EFIAPI *EFI_HII_STRING_TO_IMAGE_EX)(
IN CONST EFI_HII_FONT_EX_PROTOCOL *This,
);
Same with EFI_HII_FONT_PROTOCOL.STRINGTOIMAGE() .
This function is similar to EFI_HII_FONT_PROTOCOL.StringToImage(). The difference is that this func-
tion will locate all EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL instances that are installed in the sys-
tem when the glyph in the string with the given font information is not found in the current HII glyph
database. The function will attempt to generate the glyph information and the bitmap using the ﬁrst
EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL instance that supports the requested font information in the
EFI_FONT_DISPLAY_INFO.
Status Codes Returned — Same with EFI_HII_FONT_PROTOCOL.STRINGTOIMAGE() .
34.2. EFI HII Font Ex Protocol 1628Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.2.3 EFI_HII_FONT_EX_PROTOCOL.StringIdToImageEx()
Summary
Render a string to a bitmap or the screen containing the contents of the speciﬁed string. The prototype of this extension
function is the same with EFI_HII_FONT_PROTOCOL.STRINGTOIMAGE() .
Protocol
typedef
(EFIAPI *EFI_HII_STRING_ID_TO_IMAGE_EX)(
IN CONST CHAR8 *Language,
);
This function is similar to EFI_HII_FONT_PROTOCOL.StringIdToImage().*The difference is that this func-
tion will locate all *EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL instances that are installed in the sys-
EFI_FONT_DISPLAY_INFO .
34.2.4 EFI_HII_FONT_EX_PROTOCOL.GetGlyphEx()
Summary
Return image and baseline about a single glyph. The prototype of this extension function is the same with
EFI_HII_FONT_PROTOCOL.GETGLYPH() .
Protocol
typedef
(EFIAPI *EFI_HII_GET_GLYPH_EX)(
IN UINTN Baseline OPTIONAL
);
34.2. EFI HII Font Ex Protocol 1629Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Parameters — Same with EFI_HII_FONT_PROTOCOL.GETGLYPH() .
The difference is that this function will locate all EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL instances
that are installed in the system when the glyph in the string with the given font information is not found in the
current HII glyph database. The function will attempt to generate the glyph information and the bitmap using the
ﬁrst EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL instance that supports the requested font information in
theEFI_FONT_DISPLAY_INFO.
Status Codes Returned — Same as EFI_HII_FONT_PROTOCOL.GETGLYPH() .
34.2.5 EFI_HII_FONT_EX_PROTOCOL.GetFontInfoEx()
Summary
Return information about a particular font. The prototype of this extension function is the same with
Protocol
typedef
(EFIAPI *EFI_HII_GET_FONT_INFO_EX)(
IN CONST EFI_FONT_DISPLAY_INFO *StringInfoIn, OPTIONAL
);
Parameters — Same with EFI_HII_FONT_PROTOCOL.GETFONTINFO() .
Same with EFI_HII_FONT_PROTOCOL.GETFONTINFO() . This protocol invokes
EFI_HII_FONT_PROTOCOL.GETFONTINFO() . implicitly.
Status Codes Returned — Same as EFI_HII_FONT_PROTOCOL.GETFONTINFO() .
34.2.6 EFI_HII_FONT_EX_PROTOCOL.GetGlyphInfo()
Summary
The function returns the information of the single glyph.
Protocol
typedef
(EFIAPI *EFI_HII_GET_GLYPH_INFO)(
IN CONST EFI_FONT_DISPLAY_INFO *FontDisplayInfo,
OUT EFI_HII_GLYPH_INFO * GlyphInfo
);
This EFI_HII_FONT_EX_PROTOCOL instance.
34.2. EFI HII Font Ex Protocol 1630Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Char Information of Character to retrieve.
FontDisplayInfo Font display information of this character.
GlyphInfo Pointer to retrieve the glyph information.
This function returns the glyph information of character in the speciﬁc font family. This function will locate all
EFI_HII_FONT_GLYPH_GENERATOR protocol instances that are installed in the system, and attempt to use them if
it can’t ﬁnd the glyph information in the font database. It returns EFI_UNSUPPORTED if neither the font database nor
any instances of the EFI_HII_FONT_GLYPH_GENRATOR protocols support the font glyph in the speciﬁc font family.
Otherwise, the EFI_HII_GLYPH_INFO is returned in GlyphInfo. This function only returns the glyph geometry
information instead of allocating the buffer for EFI_IMAGE_OUTPUT and drawing the glyph in the buffer.
Fig. 34.1: Glyph Example
EFI_SUCCESS The glyph information was returned to GlyphInfo .
EFI_OUT_OF_RESOURCES Memory allocation failed in this function.
EFI_NOT_FOUND The input character was not found in the database.
EFI_UNSUPPORTED The font is not supported.
EFI_INV ALID_PARAMETER TheGlyphInfo orFontDisplayInfo was NULL.
34.2.7 Code Deﬁnitions
34.2.7.1 EFI_FONT_DISPLAY_INFO
Summary
Describes font output-related information.
Prototype
typedef struct _EFI_FONT_DISPLAY_INFO {
EFI_GRAPHICS_OUTPUT_BLT_PIXEL ForegroundColor;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL BackgroundColor;
EFI_FONT_INFO_MASK FontInfoMask;
EFI_FONT_INFO FontInfo
} EFI_FONT_DISPLAY_INFO;
Members
34.2. EFI HII Font Ex Protocol 1631Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

Summary
Prototype
Members
FontInfo The font information. Type EFI_FONT_INFO is deﬁned in EFI_HII_STRING_PROTOCOL.NewString().
ForegroundColor The color of the “on” pixels in the glyph in the bitmap.
BackgroundColor The color of the “off” pixels in the glyph in the bitmap.
FontInfoMask The font information mask determines which portion of the font information will be used and what to
do if the speciﬁc font is not available.
This structure is used for describing the way in which a string should be rendered in a particular font. FontInfo speciﬁes
the basic font information and ForegroundColor andBackgroundColor specify the color in which they should be
displayed. The ﬂags in FontInfoMask describe where the system default should be supplied instead of the speciﬁed
information. The ﬂags also describe what options can be used to make a match between the font requested and the
font available.
IfEFI_FONT_INFO_SYS_FONT is speciﬁed, then the font name in FontInfo is ignored and the system font name is
used. This ﬂag cannot be used with EFI_FONT_INFO_ANY_FONT.
IfEFI_FONT_INFO_SYS_SIZE is speciﬁed, then the font height speciﬁed in FontInfo is ignored and the system font
height is used instead. This ﬂag cannot be used with EFI_FONT_INFO_ANY_SIZE.
IfEFI_FONT_INFO_SYS_STYLE is speciﬁed, then the font style in FontInfo is ignored and the system font style is
used. This ﬂag cannot be used with EFI_FONT_INFO_ANY_STYLE.
IfEFI_FONT_INFO_SYS_FORE_COLOR is speciﬁed, then ForegroundColor is ignored and the system foreground
color is used.
IfEFI_FONT_INFO_SYS_BACK_COLOR is speciﬁed, then BackgroundColor is ignored and the system background
IfEFI_FONT_INFO_RESIZE is speciﬁed, then the system may attempt to stretch or shrink a font to meet the size
requested. This ﬂag cannot be used with EFI_FONT_INFO_ANY_SIZE.
IfEFI_FONT_INFO_RESTYLE is speciﬁed, then the system may attempt to remove some of the speciﬁed styles in
order to meet the style requested. This ﬂag cannot be used with EFI_FONT_INFO_ANY_STYLE.
IfEFI_FONT_INFO_ANY_FONT is speciﬁed, then the system may attempt to match with any font. This ﬂag cannot
be used with EFI_FONT_INFO_SYS_FONT.
IfEFI_FONT_INFO_ANY_SIZE is speciﬁed, then the system may attempt to match with any font size. This ﬂag
cannot be used with EFI_FONT_INFO_SYS_SIZE orEFI_FONT_INFO_RESIZE .
IfEFI_FONT_INFO_ANY_STYLE is speciﬁed, then the system may attempt to match with any font style. This ﬂag
cannot be used with EFI_FONT_INFO_SYS_STYLE orEFI_FONT_INFO_RESTYLE.
typedef UINT32 EFI_FONT_INFO_MASK;
#define EFI_FONT_INFO_SYS_FONT 0x00000001
#define EFI_FONT_INFO_SYS_SIZE 0x00000002
#define EFI_FONT_INFO_SYS_STYLE 0x00000004
#define EFI_FONT_INFO_SYS_FORE_COLOR 0x00000010
#define EFI_FONT_INFO_SYS_BACK_COLOR 0x00000020
#define EFI_FONT_INFO_RESIZE 0x00001000
#define EFI_FONT_INFO_RESTYLE 0x00002000
#define EFI_FONT_INFO_ANY_FONT 0x00010000
#define EFI_FONT_INFO_ANY_SIZE 0x00020000
#define EFI_FONT_INFO_ANY_STYLE 0x00040000
34.2. EFI HII Font Ex Protocol 1632Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.2.7.2 EFI_IMAGE_OUTPUT
Summary
Describes information about either a bitmap or a graphical output device.
Prototype
typedef struct _EFI_IMAGE_OUTPUT {
union {
EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap;
EFI_GRAPHICS_OUTPUT_PROTOCOL *Screen;
} Image;
} EFI_IMAGE_OUTPUT;
Members
Width Width of the output image.
Height Height of the output image.
Bitmap Points to the output bitmap.
Screen Points to the EFI_GRAPHICS_OUTPUT_PROTOCOL which describes the screen on which to draw the spec-
iﬁed string.
34.3 String Protocol
34.3.1 EFI_HII_STRING_PROTOCOL
Summary
Interfaces which manipulate string data.
GUID
#define EFI_HII_STRING_PROTOCOL_GUID \
{ 0xfd96974, 0x23aa, 0x4cdc,\
{ 0xb9, 0xcb, 0x98, 0xd1, 0x77, 0x50, 0x32, 0x2a }}
Protocol
typedef struct _EFI_HII_STRING_PROTOCOL {
EFI_HII_NEW_STRING NewString;
EFI_HII_GET_STRING GetString;
EFI_HII_SET_STRING SetString;
EFI_HII_GET_LANGUAGES GetLanguages;
EFI_HII_GET_2ND_LANGUAGES GetSecondaryLanguages;
} EFI_HII_STRING_PROTOCOL;
Members
NewString Add a new string.
GetString Retrieve a string and related string information.
SetString Change a string.
34.3. String Protocol 1633Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetLanguages List the languages for a particular package list.
GetSecondaryLanguages List supported secondary languages for a particular primary language.
34.3.2 EFI_HII_STRING_PROTOCOL.NewString()
Summary
Creates a new string in a speciﬁc language and add it to strings from a speciﬁc package list.
Prototype
typedef
(EFIAPI *EFI_HII_NEW_STRING) (
IN CONST EFI_HII_STRING_PROTOCOL *This,
OUT EFI_STRING_ID *StringId
IN CONST CHAR16 *LanguageName OPTIONAL,
IN CONST EFI_FONT_INFO *StringFontInfo
);
This A pointer to the EFI_HII_STRING_PROTOCOL instance.
PackageList Handle of the package list where this string will be added.
Language Points to the language for the new string. The language information is in the format described by Formats
— Language Codes and Language Code Arrays of the UEFI Speciﬁcation.
LanguageName Points to the printable language name to associate with the passed in Language ﬁeld. This is analo-
gous to passing in “zh-Hans” in the Language ﬁeld and LanguageName might contain “Simpliﬁed Chinese” as
the printable language.
String Points to the new null-terminated string.
StringFontInfo Points to the new string’s font information or NULL if the string should have the default system font,
size and style.
StringId On return, contains the new strings id, which is unique within PackageList. Type EFI_STRING_ID is deﬁned
inEFI_IFR_OP_HEADER .
This function adds the string String to the group of strings owned by PackageList, with the speciﬁed font information
StringFontInfo and returns a new string id. The new string identiﬁer is guaranteed to be unique within the package list.
That new string identiﬁer is reserved for all languages in the package list.
} EFI_FONT_INFO;
FontStyle The design style of the font. Type EFI_HII_FONT_STYLE is deﬁned in Fixed Header .
FontSize The character cell height, in pixels.
34.3. String Protocol 1634Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
FontName The null-terminated font family name.
Status Codes Returns
EFI_SUCCESS The new string was added successfully
EFI_OUT_OF_RESOURCES Could not add the string.
EFI_INV ALID_PARAMETER String isNULL orStringId isNULL orLanguage isNULL .
EFI_NOT_FOUND The input package list could not be found in the current database.
34.3.3 EFI_HII_STRING_PROTOCOL.GetString()
Summary
Returns information about a string in a speciﬁc language, associated with a package list.
Prototype
typedef
(EFIAPI *EFI_HII_GET_STRING) (
OUT EFI_STRING String,
IN OUT UINTN *StringSize,
OUT EFI_FONT_INFO **StringFontInfo OPTIONAL
);
Language Points to the language for the retrieved string. Callers of interfaces that require RFC 4646 language codes
to retrieve a Unicode string must use the RFC 4647 algorithm to lookup the Unicode string with the closest
StringSize On entry, points to the size of the buffer pointed to by String, in bytes. On return, points to the length of
the string, in bytes.
StringFontInfo Points to a buffer that will be callee allocated and will have the string’s font information into this
buffer. The caller is responsible for freeing this buffer. If the parameter is NULL a buffer will not be allocated
and the string font information will not be returned.
This function retrieves the string speciﬁed by StringId which is associated with the speciﬁed PackageList in the lan-
guage Language and copies it into the buffer speciﬁed by String.
If the string speciﬁed by StringId is not present in the speciﬁed PackageList, then EFI_NOT_FOUND is returned.
If the string speciﬁed by StringId is present, but not in the speciﬁed language then EFI_INVALID_LANGUAGE is
returned.
34.3. String Protocol 1635Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If the buffer speciﬁed by StringSize is too small to hold the string, then EFI_BUFFER_TOO_SMALL will be returned.
StringSize will be updated to the size of buffer actually required to hold the string.
EFI_SUCCESS The string was returned successfully.

returned.
EFI_NOT_FOUND The string speciﬁed by StringId is not available. The speciﬁed PackageList
EFI_INV ALID_LANGUAGE The string speciﬁed by StringId is available but not in the speciﬁed lan-
guage.
EFI_BUFFER_TOO_SMALL The buffer speciﬁed by StringLength is too small to hold the string.
EFI_INV ALID_PARAMETER TheLanguage orStringSize wasNULL .
EFI_INV ALID_PARAMETER The value referenced by StringLength was not zero and String wasNULL .
34.3.4 EFI_HII_STRING_PROTOCOL.SetString()
Summary
Change information about the string.
Prototype
typedef
(EFIAPI *EFI_HII_SET_STRING) (
IN CONST EFI_FONT_INFO *StringFontInfo OPTIONAL
);
PackageList The package list containing the strings.
Language Points to the language for the updated string.
StringId The string id, which is unique within PackageList.
StringFontInfo Points to the string’s font information or NULL if the string font information is not changed.
This function updates the string speciﬁed by StringId in the speciﬁed PackageList to the text speciﬁed by String and,
optionally, the font information speciﬁed by StringFontInfo . There is no way to change the font information without
changing the string text.
34.3. String Protocol 1636Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 34.8 – continued from previous page
EFI_NOT_FOUND The string speciﬁed by StringId is not in the database. The speciﬁed Pack-
ageList is not in the Database.
EFI_INV ALID_PARAMETER TheString orLanguage wasNULL .
EFI_OUT_OF_RESOURCES The system is out of resources to accomplish the task.
34.3.5 EFI_HII_STRING_PROTOCOL.GetLanguages()
Summary
Returns a list of the languages present in strings in a package list.
Prototype
typedef
(EFIAPI *EFI_HII_GET_LANGUAGES) (
IN OUT CHAR8 *Languages,
IN OUT UINTN *LanguagesSize
);
PackageList The package list to examine.
Languages Points to the buffer to hold the returned null-terminated ASCII string.
LanguageSize On entry, points to the size of the buffer pointed to by Languages, in bytes. On return, points to the
length of Languages, in bytes.
This function returns the list of supported languages, in the format speciﬁed in Formats — Language Codes and
Language Code Arrays .
EFI_SUCCESS The languages were returned successfully.
EFI_BUFFER_TOO_SMALL The LanguagesSize is too small to hold the list of supported languages.
LanguageSize is updated to contain the required size.
EFI_NOT_FOUND The speciﬁed PackageList is not in the Database.
EFI_INV ALID_PARAMETER LanguagesSize isNULL .
EFI_INV ALID_PARAMETER The value referenced by LanguagesSize is not zero and Languages is
NULL .
34.3. String Protocol 1637Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.3.6 EFI_HII_STRING_PROTOCOL.GetSecondaryLanguages()
Summary
Given a primary language, returns the secondary languages supported in a package list.
Prototype
typedef
(EFIAPI *EFI_HII_GET_2ND_LANGUAGES) (
IN CONST CHAR8 * PrimaryLanguage;
IN OUT CHAR8 *SecondaryLanguages,
IN OUT UINTN *SecondaryLanguagesSize
);
Primary Language Points to the null-terminated ASCII string that speciﬁes the primary language. Languages are
speciﬁed in the format speciﬁed in Formats — Language Codes and Language Code Arrays of the UEFI Speci-
ﬁcation.
SecondaryLanguages Points to the buffer to hold the returned null-terminated ASCII string that describes the list
of secondary languages for the speciﬁed PrimaryLanguage. If there are no secondary languages, the function
returns successfully, but this is set to NULL .
SecondaryLanguagesSize On entry, points to the size of the buffer pointed to by SecondaryLanguages, in bytes. On
return, points to the length of SecondaryLanguages in bytes.
Each string package has associated with it a single primary language and zero or more secondary languages. This
routine returns the secondary languages associated with a package list.
EFI_SUCCESS Secondary languages correctly returned
EFI_BUFFER_TOO_SMALL The buffer speciﬁed by SecondaryLanguagesSize is too small to hold the
returned information. SecondaryLanguageSize is updated to hold the size
of the buffer required.
EFI_INV ALID_LANGUAGE The language speciﬁed by FirstLanguage is not present in the speciﬁed
package list.
EFI_INV ALID_PARAMETER PrimaryLanguage or SecondaryLanguagesSize is NULL .
EFI_INV ALID_PARAMETER The value referenced by SecondaryLanguagesSize is not zero and Sec-
ondaryLanguages isNULL .
34.3. String Protocol 1638Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.4 Image Protocol
34.4.1 EFI_HII_IMAGE_PROTOCOL
Summary
Protocol which allow access to images in the images database.
GUID
#define EFI_HII_IMAGE_PROTOCOL_GUID \
{ 0x31a6406a, 0x6bdf, 0x4e46,\
{ 0xb2, 0xa2, 0xeb, 0xaa, 0x89, 0xc4, 0x9, 0x20 }}
Protocol
typedef struct _EFI_HII_IMAGE_PROTOCOL {
EFI_HII_NEW_IMAGE NewImage;
EFI_HII_GET_IMAGE GetImage;
EFI_HII_SET_IMAGE SetImage;
EFI_HII_DRAW_IMAGE DrawImage;
EFI_HII_DRAW_IMAGE_ID DrawImageId;
} EFI_HII_IMAGE_PROTOCOL;
Members
NewImage Add a new image.
GetImage Retrieve an image and related font information.
SetImage Change an image.
34.4.2 EFI_HII_IMAGE_PROTOCOL.NewImage()
Summary
Creates a new image and add it to images from a speciﬁc package list.
Prototype
typedef
(EFIAPI *EFI_HII_NEW_IMAGE) (
IN CONST EFI_HII_IMAGE_PROTOCO *This,
OUT EFI_IMAGE_ID *ImageId
IN CONST EFI_IMAGE_INPUT *Image
);
This A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
PackageList Handle of the package list where this image will be added.
ImageId On return, contains the new image id, which is unique within PackageList.
Image Points to the image.
34.4. Image Protocol 1639Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function adds the image Image to the group of images owned by PackageList, and returns a new image identiﬁer
(ImageId ).
} EFI_IMAGE_INPUT;
Flags Describe image characteristics. If EFI_IMAGE_TRANSPARENT is set, then the image was designed for
transparent display. #deﬁne EFI_IMAGE_TRANSPARENT 0x00000001
Width Image width, in pixels.
Height Image height, in pixels.
Bitmap A pointer to the actual bitmap, organized left-to-right, top-to-bottom. The size of the bitmap is Width *
Height * size of (EFI_GRAPHICS_OUTPUT_BLT_PIXEL).
EFI_SUCCESS The new image was added successfully
EFI_OUT_OF_RESOURCES Could not add the image.
EFI_INV ALID_PARAMETER Image isNULL orImageId isNULL .
EFI_NOT_FOUND ThePackageList could not be found.
34.4.3 EFI_HII_IMAGE_PROTOCOL.GetImage()
Summary
Returns information about an image, associated with a package list.
Prototype
typedef
(EFIAPI *EFI_HII_GET_IMAGE) (
IN CONST EFI_HII_IMAGE_PROTOCOL *This,
IN EFI_IMAGE_ID ImageId,
OUT EFI_IMAGE_INPUT *Image
);
PackageList The package list in the HII database to search for the speciﬁed image.
ImageId The image’s id, which is unique within PackageList.
34.4. Image Protocol 1640Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function retrieves the image speciﬁed by ImageId which is associated with the speciﬁed PackageList and copies
it into the buffer speciﬁed by Image.
If the image speciﬁed by ImageId is not present in the speciﬁed PackageList, then EFI_NOT_FOUND is returned.
The actual bitmap (I mage->Bitmap ) should not be freed by the caller and should not be modiﬁed directly.
EFI_SUCCESS The image was returned successfully.
EFI_NOT_FOUND The image speciﬁed by ImageId is not available. The speciﬁed PackageList
EFI_INV ALID_PARAMETER Image was NULL.
EFI_OUT_OF_RESOURCES The bitmap could not be retrieved because there was not enough memory.
34.4.4 EFI_HII_IMAGE_PROTOCOL.SetImage()
Summary
Change information about the image.
Prototype
typedef

Summary
Prototype
typedef
(EFIAPI *EFI_HII_SET_IMAGE) (
IN CONST EFI_IMAGE_INPUT *Image,
);
PackageList The package list containing the images.
ImageId The image id, which is unique within PackageList.
This function updates the image speciﬁed by ImageId in the speciﬁed PackageListHandle to the image speciﬁed by
Image .
EFI_SUCCESS The image was successfully updated.
EFI_NOT_FOUND The image speciﬁed by ImageId is not in the database. The speciﬁed Pack-
EFI_INV ALID_PARAMETER TheImage wasNULL .
34.4. Image Protocol 1641Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.4.5 EFI_HII_IMAGE_PROTOCOL.DrawImage()
Summary
Renders an image to a bitmap or to the display.
Prototype
typedef
(EFIAPI *EFI_HII_DRAW_IMAGE) (
IN EFI_HII_DRAW_FLAGS Flags,
);
Flags Describes how the image is to be drawn. EFI_HII_DRAW_FLAGS is deﬁned in Related Deﬁnitions, below.
Image Points to the image to be displayed.
BltIf this points to a non-NULL on entry, this points to the image, which is Width pixels wide and Height pixels
high. The image will be drawn onto this image and EFI_HII_DRAW_FLAG_CLIP is implied. If this points to a
BltX, BltY Speciﬁes the offset from the left and top edge of the image of the ﬁrst pixel in the image.
This function renders an image to a bitmap or the screen using the speciﬁed color and options. It draws the image on
an existing bitmap, allocates a new bitmap or uses the screen. The images can be clipped.
IfEFI_HII_DRAW_FLAG_CLIP is set, then all pixels drawn outside the bounding box speciﬁed by Width andHeight
are ignored.
The EFI_HII_DRAW_FLAG_TRANSPARENT ﬂag determines whether the image will be drawn transparent or
opaque. If EFI_HII_DRAW_FLAG_FORCE_TRANS is set then the image’s pixels will be drawn so that all
“off” pixels in the image will be drawn using the pixel value from BLT and all other pixels will be copied. If
EFI_HII_DRAW_FLAG_FORCE_OPAQUE is set, then the image’s pixels will be copied directly to the destination.
IfEFI_HII_DRAW_FLAG_DEFAULT is set, then the image will be drawn transparently or opaque, depending on
the image’s transparency setting (see EFI_IMAGE_TRANSPARENT). Images cannot be drawn transparently if Bltis
NULL.
IfEFI_HII_DIRECT_TO_SCREEN is set, then the image will be written directly to the output device speciﬁed by
Screen. Otherwise the image will be rendered to the bitmap speciﬁed by Bitmap.
EFI_OUT_OF_RESOURCES Unable to allocate an output buffer for Blt.
EFI_INV ALID_PARAMETER TheImage orBltwasNULL .
34.4. Image Protocol 1642Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.4.6 EFI_HII_IMAGE_PROTOCOL.DrawImageId()
Summary
Render an image to a bitmap or the screen containing the contents of the speciﬁed image.
Prototype
typedef
(EFIAPI *EFI_HII_DRAW_IMAGE_ID) (
);
BltX, BltY Speciﬁes the offset from the left and top edge of the output image of the ﬁrst pixel in the image.
If EFI_HII_DRAW_FLAG_CLIP is set, then all pixels drawn outside the bounding box speciﬁed by Width andHeight
opaque. If EFI_HII_DRAW_FLAG_FORCE_TRANS is set, then the image will be drawn so that all “off”
pixels in the image will be drawn using the pixel value from Blt and all other pixels will be copied. If
EFI_HII_DRAW_FLAG_FORCE_OPAQUE is set, then the image’s pixels will be copied directly to the destina-
tion. If EFI_HII_DRAW_FLAG_DEFAULT is set, then the image will be drawn transparently or opaque, depending
on the image’s transparency setting ( EFI_IMAGE_TRANSPARENT ). Images cannot be drawn transparently if Blt
is NULL.
If EFI_HII_DIRECT_TO_SCREEN is set, then the image will be written directly to the output device speciﬁed by
typedef UINT32 EFI_HII_DRAW_FLAGS;
#define EFI_HII_DRAW_FLAG_CLIP 0x00000001
#define EFI_HII_DRAW_FLAG_TRANSPARENT 0x00000030
#define EFI_HII_DRAW_FLAG_DEFAULT 0x00000000
34.4. Image Protocol 1643Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_HII_DRAW_FLAG_FORCE_TRANS 0x00000010
#define EFI_HII_DRAW_FLAG_FORCE_OPAQUE 0x00000020
ageList is not in the Database
34.5 EFI HII Image Ex Protocol
The EFI HII Image Ex protocol deﬁnes an extension to the EFI HII Image protocol which enables various new capa-
bilities described in this section.
34.5.1 EFI_HII_IMAGE_EX_PROTOCOL
Summary
Protocol which allows access to the images in the images database
GUID
#define EFI_HII_IMAGE_EX_PROTOCOL_GUID \
{0x1a1241e6, 0x8f19, 0x41a9, 0xbc, \
{0xe, 0xe8, 0xef,0x39, 0xe0, 0x65, 0x46}}
Protocol
typedef struct _EFI_HII_IMAGE_EX_PROTOCOL {
EFI_HII_NEW_IMAGE_EX NewImageEx;
EFI_HII_GET_IMAGE_EX GetImageEx;
EFI_HII_SET_IMAGE_EX SetImageEx;
EFI_HII_DRAW_IMAGE_EX DrawImageEx;
EFI_HII_DRAW_IMAGE_ID_EX DrawImageIdEx;
EFI_HII_GET_IMAGE_INFO GetImageInfo;
} EFI_HII_IMAGE_EX_PROTOCOL;
Members
NewImageEx Add a new image. This protocol invokes the original EFI_HII_IMAGE_PROTOCOL.NewImage() im-
plicitly.
GetImageEx Retrieve an image and the related image information. This function will try to locate the
EFI_HII_IMAGE_DECODER_PROTOCOL if the image decoder for the image is not supported by the EFI
HII image EX protocol.
SetImageEx Change information about the image, this protocol invokes original
EFI_HII_IMAGE_PROTOCOL.SetImage() implicitly.
DrawImageEx Renders an image to a bitmap or the display, this protocol invokes original
EFI_HII_IMAGE_PROTOCOL.DrawImage() implicitly.
34.5. EFI HII Image Ex Protocol 1644Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DrawImageIdEx Renders an image to a bitmap or the screen containing the contents of the speciﬁed image, this
protocol invokes original EFI_HII_IMAGE_PROTOCOL.DrawImageId() implicitly.
GetImageInfo This function retrieves the image information speciﬁed by the image ID which is associated with the
speciﬁed HII package list. This function only returns the geometry of the image instead of allocating the memory
buffer and decoding the image to the buffer.
34.5.2 EFI_HII_IMAGE_EX_PROTOCOL.NewImageEx()
Summary
The prototype of this extension function is the same with EFI_HII_IMAGE_PROTOCOL.NEWIMAGE() .
Protocol
typedef
(EFIAPI *EFI_HII_NEW_IMAGE_EX)(
IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This,
IN OUT EFI_IMAGE_INPUT *Image
);
Same with EFI_HII_IMAGE_PROTOCOL.NEWIMAGE() .
Same with EFI_HII_IMAGE_PROTOCOL.NEWIMAGE() . This protocol invokes
EFI_HII_IMAGE_PROTOCOL.NEWIMAGE() implicitly.
Status Codes Returned — Same as EFI_HII_IMAGE_PROTOCOL.NEWIMAGE()
34.5.3 EFI_HII_IMAGE_EX_PROTOCOL.GetImageEx()
Summary

Summary
Protocol
typedef
);
Summary
Return the information about the image, associated with the package list. The prototype of this extension function is
the same with EFI_HII_IMAGE_PROTOCOL.GETIMAGE()
Protocol
typedef
(EFIAPI *EFI_HII_GET_IMAGE_EX)(
);
Parameters — Same with EFI_HII_IMAGE_PROTOCOL.GETIMAGE() .
This function is similar to EFI_HII_IMAGE_PROTOCOL.GETIMAGE() . The difference is that this function will
locate all EFI_HII_IMAGE_DECODER_PROTOCOL instances installed in the system if the decoder of the certain
34.5. EFI HII Image Ex Protocol 1645Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
image type is not supported by the EFI_HII_IMAGE_EX_PROTOCOL . The function will attempt to decode the im-
age to the EFI_IMAGE_INPUT using the ﬁrst EFI_HII_IMAGE_DECODER_PROTOCOL instance that supports the
requested image type.
Status Codes Returned — Same as EFI_HII_IMAGE_PROTOCOL.GETIMAGE() .
34.5.4 EFI_HII_IMAGE_EX_PROTOCOL.SetImageEx()
Summary
Change the information about the image. The prototype of this extension function is the same with
EFI_HII_IMAGE_PROTOCOL.SetImage() .
Protocol
typedef
(EFIAPI *EFI_HII_SET_IMAGE_EX)(
);
Parameters — Same with `EFI_HII_IMAGE_PROTOCOL.SetImage() `_ .
Same with EFI_HII_IMAGE_PROTOCOL.SetImage() , this protocol invokes
Status Codes Returned — Same as EFI_HII_IMAGE_PROTOCOL.SetImage() .
34.5.5 EFI_HII_IMAGE_EX_PROTOCOL.DrawImageEx()
Summary
Renders an image to a bitmap or to the display. The prototype of this extension function is the same with
EFI_HII_IMAGE_PROTOCOL.DrawImageId() .
Protocol
typedef
(EFIAPI *EFI_HII_DRAW_IMAGE_EX)(
IN UINTN BltY
);
Same with EFI_HII_IMAGE_PROTOCOL.DrawImageId() .
34.5. EFI HII Image Ex Protocol 1646Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Same with EFI_HII_IMAGE_PROTOCOL.DrawImage() ` this protocol invokes
Status Codes Returned — Same as EFI_HII_IMAGE_PROTOCOL.DrawImage()
34.5.6 EFI_HII_IMAGE_EX_PROTOCOL.DrawImageIdEx()
Summary
Renders an image to a bitmap or the screen containing the contents of the speciﬁed image. The prototype of this
extension function is the same with EFI_HII_IMAGE_PROTOCOL.DrawImageID()
Protocol
typedef
(EFIAPI *EFI_HII_DRAW_IMAGE_ID_EX)(
);
Parameters — Same with EFI_HII_IMAGE_PROTOCOL.DrawImageID() .
This function is similar to EFI_HII_IMAGE_PROTOCOL.DrawImageID() . The difference is that this function will
Status Codes Returned — Same as EFI_HII_IMAGE_PROTOCOL.DrawImageID() .
34.5.7 EFI_HII_IMAGE_EX_PROTOCOL.GetImageInfo()
Summary
The function returns the information of the image. This function is differ from the
EFI_HII_IMAGE_EX_PROTOCOL.GetImageEx() . This function only returns the geometry of the image in-
stead of decoding the image to the buffer.
Protocol
typedef
(EFIAPI *EFI_HII_GET_IMAGE_INFO)(
OUT EFI_IMAGE_OUTPUT *Image
);
34.5. EFI HII Image Ex Protocol 1647Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This EFI_HII_IMAGE_EX_PROTOCOL instance.
PackageList The HII package list.
ImageId The HII image ID.
Image EFI_IMAGE_OUTPUT to retrieve the image information. Only Image.Width and Image.Height will be up-
dated by this function. Image.Bitmap is always set to NULL.
This function returns the image information to EFI_IMAGE_OUTPUT. Only the width and height are returned to the
EFI_IMAGE_OUTPUT instead of decoding the image to the buffer. This function is used to get the geometry of the
image. This function will try to locate all of the EFI_HII_IMAGE_DECODER_PROTOCOL installed on the system if
the decoder of image type is not supported by the EFI_HII_IMAGE_EX_PROTOCOL .
EFI_SUCCESS The image information was returned to Image.
EFI_UNSUPPORTED The format of image is not supported.
EFI_NOT_FOUND The image was not found in the database.
EFI_INV ALID_PARAMETER The Image was NULL or ImageId was 0.
34.6 EFI HII Image Decoder Protocol
For those HII image block types which don’t have the corresponding image decoder supported in EFI HII image
EX protocol, EFI_HII_IMAGE_DECODER_PROTOCOL can be used to provide the proper image decoder. There
may be more than one EFI_HII_IMAGE_DECODER_PROTOCOL instance installed in the system. Each image
decoder can decode more than on HII image block types. Whether or not the HII image block type of image is
supported by the certain image decoder is reported through the EFI_HII_IMAGE_DECODER_PROTOCOL. GetIm-
ageDecoderName() . Caller can invoke this function to verify the image is supported by the image decoder before
sending the image raw data to the image decoder. There are two image decoder names deﬁned in this speciﬁcation:
EFI_HII_IMAGE_DECODER_NAME_JPEG andEFI_HII_IMAGE_DECODER_NAME_PNG.
The image decoder protocol can publish the support for additional image decoder names other than the ones deﬁned
in this speciﬁcation. This allows the image decoder to support additional image formats that are not deﬁned by the HII
image block types. In that case, callers can send the image raw data to the image decoder protocol instance to retrieve
the image information or decode the image. Since the HII image block type of such images is not deﬁned, the image
may or may not be decoded by that decoder. The decoder can use the signature or data structures in the image raw
data is check the format before it processes the image.
TheEFI_HII_IMAGE_EX_PROTOCOL uses EFI_HII_IMAGE_DECODER_PROTOCOL as follows:
34.6.1 EFI_HII_IMAGE_DECODER_PROTOCOL.DecodeImage()
Summary
Provides the image decr for speciﬁc image ﬁle formats.
GUID
#define EFI_HII_IMAGE_DECODER_PROTOCOL_GUID \
{0x9E66F251, 0x727C, 0x418C, \
{0xBF, 0xD6, 0xC2, 0xB4, 0x25, 0x28, 0x18, 0xEA}}
34.6. EFI HII Image Decoder Protocol 1648Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 34.2: How EFI_HII_IMAGE_EX_PROTOCOL uses EFI_HII_IMAGE_DECODER_PROTOCOL
34.6. EFI HII Image Decoder Protocol 1649Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Protocol
typedef struct _EFI_HII_IMAGE_DECODER_PROTOCOL {
EFI_HII_IMAGE_DECODER_GET_NAME GetImageDecoderName;
EFI_HII_IMAGE_DECODER_GET_IMAGE_INFO GetImageInfo;
EFI_HII_IMAGE_DECODER_DECODE DecodeImage;
} EFI_HII_IMAGE_DECODER_PROTOCOL;
Members
GetImageDecodeName The function returns the decoder name.
GetImageInfo The function returns the image information
DecodeImage The function decodes the image to the EFI_IMAGE_INPUT
EFI_SUCCESS The image information was returned to Bitmap .
EFI_UNSUPPORTED The image decoder can’t decode this image.
EFI_OUT_OF_RESOURCE Not enough memory to decode this image.
EFI_INV ALID_PARAMETER TheImage wasNULL orImageRawDataSize was 0.
34.6.2 EFI_HII_IMAGE_DECODER_PROTOCOL.GetImageDecoderName()
Summary
This function returns the decoder name.
Protocol
typedef
(EFIAPI *EFI_HII_IMAGE_DECODER_GET_NAME)(
IN CONST EFI_HII_IMAGE_DECODER_PROTOCOL *This,
IN OUT EFI_GUID **DecoderName,
OUT UINT16 *NumberOfDecoderName
);
This EFI_HII_IMAGE_DECODER_PROTOCOL instance.
DecoderName Pointer to a dimension to retrieve the decoder names in EFI_GUID format. The number of the decoder
names is returned in NumberOfDecoderName.
NumberOfDecoderName Pointer to retrieve the number of decoders which supported by this decoder driver.
There could be more than one EFI_HII_IMAGE_DECODER_PROTOCOL instances installed in the system for differ-
ent image formats. This function returns the decoder name which callers can use to ﬁnd the proper image decoder for
the image. It is possible to support multiple image formats in one EFI_HII_IMAGE_DECODER_PROTOCOL. The
capability of the supported image formats is returned in DecoderName andNumberOfDecoderName.

Summary
Protocol
typedef
);
// EFI_HII_IMAGE_DECODER_NAME
34.6. EFI HII Image Decoder Protocol 1650Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_HII_IMAGE_DECODER_NAME_JPEG_GUID \
{0xefefd093, 0xd9b, 0x46eb, 0xa8, \
{0x56, 0x48, 0x35,0x7, 0x0, 0xc9, 0x8}}
#define EFI_HII_IMAGE_DECODER_NAME_PNG_GUID \\
{0xaf060190, 0x5e3a, 0x4025, 0xaf, \\
{0xbd, 0xe1, 0xf9,0x5, 0xbf, 0xaa, 0x4c}}
EFI_SUCCESS The image decoder names were returned in DecoderName.
EFI_UNSUPPORTED No image decoders found in this EFI_HII_IMAGE_DECODER instance.
34.6.3 EFI_HII_IMAGE_DECODER_PROTOCOL.GetImageInfo()
Summary
The function returns the EFI_HII_IMAGE_DECODER_IMAGE_INFO to the caller.
Protocol
typedef
(EFIAPI *EFI_HII_IMAGE_DECODER_GET_IMAGE_INFO)(
IN VOID *Image,
IN UINTN SizeOfImage,
IN OUT EFI_HII_IMAGE_DECODER_IMAGE_INFO **ImageInfo
);
Image Pointer to the image raw data
SizeOfImage Size of the entire image raw data
ImageInfo Pointer to receive the EFI_HII_IMAGE_DECODER_IMAGE_INFO
This function returns the image information of the given image raw data. This function ﬁrst checks whether the image
raw data is supported by this decoder or not. This function may go through the ﬁrst few bytes in the image raw data
for the speciﬁc data structure or the image signature. If the image is not supported by this image decoder, this function
returns EFI_UNSUPPORTED to the caller. Otherwise, this function returns the proper image information to the caller.
It is the caller’s responsibility to free then*ImageInfo*.
EFI_SUCCESS The image information was returned to ImageInfo.
EFI_UNSUPPORTED No image decoder for the given Image or the image decoder can’t decode
this image.
34.6. EFI HII Image Decoder Protocol 1651Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 34.19 – continued from previous page
EFI_OUT_OF_RESOURCE Not enough memory to decode this image for getting the image information.
EFI_INV ALID_PARAMETER The Image was NULL, SizeOfImage was 0 or the image is corrupted.
// EFI_HII_IMAGE_DECODER_COLOR_TYPE
EFI_HII_IMAGE_DECODER_COLOR_TYPE_RGB = 0,
EFI_HII_IMAGE_DECODER_COLOR_TYPE_RGBA = 1,
EFI_HII_IMAGE_DECODER_COLOR_TYPE_CMYK = 2,
EFI_HII_IMAGE_DECODER_COLOR_TYPE_UNKNOWN = 0xff,
} EFI_HII_IMAGE_DECODER_COLOR_TYPE
// EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER
typedef struct _EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER {
EFI_GUID DecoderName;
UINT16 ImageInfoSize;
UINT16 ImageWidth;
UINT16 ImageHeight;
EFI_HII_IMAGE_DECODER_COLOR_TYPE ColorType;
UINT8 ColorDepthInBits;
} EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER;
DecoderName Decoder Name
ImageInfoSize The size of entire image information structure in bytes.
ImageWidth The image width.
ImageHeight The image height.
ColorType
The color type, refer to
EFI_HII_IMAGE_DECODER_COLOR_TYPE.
ColorDepthInBits The color depth in bits.
// EFI_HII_IMAGE_DECODER_JPEG_INFO
typedef struct _EFI_HII_IMAGE_DECODER_JPEG_INFO {
EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;
UINT16 ScanType;
} EFI_HII_IMAGE_DECODER_JPEG_INFO;
Header EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER
ScanType
The scan type of the JPEG image
#deﬁne EFI_IMAGE_JPEG_SCANTYPE_PROGREESSIVE 0x01
#deﬁne EFI_IMAGE_JPEG_SCANTYPE_INTERLACED 0x02
Reserved Reserved
34.6. EFI HII Image Decoder Protocol 1652Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// EFI_HII_IMAGE_DECODER_PNG_INFO
typedef struct _EFI_HII_IMAGE_DECODER_PNG_INFO {
UINT16 Channels;
} EFI_HII_IMAGE_DECODER_PNG_INFO;
Channels Number of channels in the PNG image.
// EFI_HII_IMAGE_DECODER_OTHER_INFO
typedef struct _EFI_HII_IMAGE_DECODER_OTHER_INFO {
CHAR16 ImageExtenion[1];
//
// Variable length of image file extension name.
//
} EFI_HII_IMAGE_DECODER_OTHER_INFO;
ImageExtenion The string of the image ﬁle extension. For example, “GIF”, “TIFF” or others.
34.6.4 EFI_HII_IMAGE_DECODER_PROTOCOL.Decode()
Summary
The function decodes the image
Protocol
typedef
(EFIAPI *EFI_HII_IMAGE_DECODER_DECODE)(
IN UINTN ImageRawDataSize,
IN OUT EFI_IMAGE_OUTPUT **Bitmap,
IN BOOLEAN Transparent
);
ImageRawDataSize Size of the entire image raw data
Bitmap EFI_IMAGE_OUTPUT to receive the image or overlap the image on the original buffer.
Transparent BOOLEAN value indicates whether the image decoder has to handle the transparent image or not.
34.6. EFI HII Image Decoder Protocol 1653Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function decodes the image which the image type of this image is supported by this
EFI_HII_IMAGE_DECODER_PROTOCOL. IfBitmap is not NULL , the caller intends to put the image in the
given image buffer. That allows the caller to put an image overlap on the original image. The transparency is handled
by the image decoder because the transparency capability depends on the image format. Callers can set Transparent to
FALSE to force disabling the transparency process on the image. Forcing Transparent toFALSE may also improve
the performance of the image decoding because the image decoder can skip the transparency processing.
IfBitmap isNULL , the image decoder allocates the memory buffer for the EFI_IMAGE_OUTPUT and decodes the
image to the image buffer. It is the caller’s responsibility to free the memory for EFI_IMAGE_OUTPUT. Image
decoder doesn’t have to handle the transparency in this case because there is no background image given by the caller.
The background color in this case is all black (#00000000).
34.7 Font Glyph Generator Protocol
The EFI HII Font glyph generator protocol generates font glyphs of the requested characters according to the
given font information. This protocol is utilized by the EFI_HII_FONT_EX_PROTOCOL when the character
can’t be found in the existing glyph database. That is when glyph is not found in any HII font package,
EFI_HII_FONT_EX_PROTOCOL locates EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL to generate glyph
block and insert glyph block into HII font package. The HII font package can be an existing HII font package or
a new HII font package. This protocol can be provided by any driver that knows how to generate the glyph for a
speciﬁc font family. For example, EFI application or driver may provide “Times new roman” font glyph generator
driver. With this driver, platform can have “Times new roman” font supported on system.*
34.7.1 EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL
Summary
EFI HII Font glyph generator protocol generates the glyph of the character according to the given font information.
GUID
#define EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL_GUID \
{ 0xf7102853, 0x7787, 0x4dc2, 0xa8, \
{0xa8, 0x21, 0xb5, 0xdd, 0x5, 0xc8, 0x9b }}
Protocol
typedef struct _EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL {
EFI_GENERATE_GLYPH GenerateGlyph;
EFI_GENERATE_IMAGE GenerateGlyphImage;
} EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL;
Members
GenerateGlyph The function generates the glyph information according to the given font information.
GenerateGlyphImage The function generates the glyph image according to the given font information.
34.7. Font Glyph Generator Protocol 1654Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.7.2 EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL.GenerateGlyph()
Summary
The function generates the glyph information according to the given font information. This function returns the glyph
block in EFI_HII_GIBT_GLYPH_VARIABILITY type.
Protocol
typedef
(EFIAPI *EFI_HII_GENERATE_GLYPH)(
IN CONST EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL *This,
IN CONST EFI_FONT_DISPLAY_INFO *FontInfo,
OUT EFI_HII_GIBT_VARIABILITY_BLOCK *GlyphBlock
);
This EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL instance.
FontInfo Font display information of this character.

Members
Summary
Protocol
typedef
);
GlyphBlock Pointer to retrieve the EFI_HII_GIBT_VARIABILITY_BLOCK
This function generates the glyph information of the character in the speciﬁc font family.
EFI_HII_GIBT_VARIABILITY_BLOCK is returned to GlyphBlock ifGlyphBlock is not NULL .GlyphBlock
can be called by EFI_HII_FONT_EX_PROTOCOL to retrieve the glyph information which are provided by the font
family speciﬁc driver, or can be used to build up the HII font package if the HII font package with the speciﬁc font
family does not exist in the HII database.
EFI_SUCCESS The glyph information was returned to GlyphBlock.
EFI_INV ALID_PARAMETER The FontInfo or GlyphBloc wasNULL ,
EFI_OUT_OF_RESOURCE Not enough memory to generate the glyph information.
EFI_UNSUPPORTED The font glyph generator can’t generate the glyph for the given Char . This
may caused by the unsupported character, font name font style or font size.
34.7.3 EFI_HII_FONT_GLYPH_GENERATOR_PROTOCOL.GenerateGlyphImage()
Summary
The function generates the glyph image according to the given font information. This function returns
EFI_GRAPHICS_OUTPUT_BLT_PIXEL points to the EFI_IMAGE_OUTPUT buffer. This function is used for glyphs
which are reported in the font database as EFI_HII_GIBT_GLYPH_VARIABILITY glyph blocks.
Protocol
typedef
(EFIAPI *EFI_HII_GENERATE_GLYPH_IMAGE)(
IN CONST EFI_HII_GLYPH_INFO *Cell,
34.7. Font Glyph Generator Protocol 1655Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN UINT8 *GlyphBuffer,
IN OUT EFI_IMAGE_OUTPUT *Image,
IN INT32 *BltX,
IN INT32 *BltY,
);
Cell Pointer to EFI_HII_GLYPH_INFO
GlyphBuffer The buffer points to the bitmap of glyph. This pointer points to GlyphBlock.BitmapData which returned
from GenerateGlyph()function
FontInfo Font display information of this glyph.
Image Image output buffer to retrieve the glyph image.
BltX Together with BltY , speciﬁes the offset from the left and top edge of the image of the ﬁrst character cell in the *
Image.
BltY Together with BltX, speciﬁes the offset from the left and top edge of the image of the ﬁrst character cell in the
*Image.
Transparent IfTRUE , the Background color is ignored and all”off” pixels in the character’s drawn will use the pixel
value from * Image.
This function generates the glyph image of the character in the speciﬁc font family on the given
EFI_IMAGE_OUTPUT
EFI_SUCCESS The glyph image was generated in Image.
EFI_OUT_OF_RESOURCE Not enough memory to generate image of the given glyph.
EFI_UNSUPPORTED The font glyph generator can’t generate the glyph for the given FontInfo.
This may caused by the unsupported font name, font style or font size.
EFI_INV ALID_PARAMETER One or more parameters of Cell, GlyphBuffe, FontInfo, Image, BltX or
BltY was NULL .
34.8 Database Protocol
34.8.1 EFI_HII_DATABASE_PROTOCOL
Summary
Database manager for HII-related data structures.
GUID
#define EFI_HII_DATABASE_PROTOCOL_GUID \
{ 0xef9fc172, 0xa1b2, 0x4693,\
{ 0xb3, 0x27, 0x6d, 0x32, 0xfc, 0x41, 0x60, 0x42 }}
34.8. Database Protocol 1656Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Protocol
typedef struct _EFI_HII_DATABASE_PROTOCOL {
EFI_HII_DATABASE_NEW_PACK NewPackageList;
EFI_HII_DATABASE_REMOVE_PACK RemovePackageList;
EFI_HII_DATABASE_UPDATE_PACK UpdatePackageList;
EFI_HII_DATABASE_LIST_PACKS ListPackageLists;
EFI_HII_DATABASE_EXPORT_PACKS ExportPackageLists;
EFI_HII_DATABASE_REGISTER_NOTIFY RegisterPackageNotify;
EFI_HII_DATABASE_UNREGISTER_NOTIFY UnregisterPackageNotify;
EFI_HII_FIND_KEYBOARD_LAYOUTS FindKeyboardLayouts;
EFI_HII_GET_KEYBOARD_LAYOUT GetKeyboardLayout;
EFI_HII_SET_KEYBOARD_LAYOUT SetKeyboardLayout;
EFI_HII_DATABASE_GET_PACK_HANDLE GetPackageListHandle;
} EFI_HII_DATABASE_PROTOCOL;
Members
NewPackageList Add a new package list to the HII database.
RemovePackageList Remove a package list from the HII database.
UpdatePackageList Update a package list in the HII database.
ListPackageLists List the handles of the package lists within the HII database.
ExportPackageLists Export package lists from the HII database.
RegisterPackageNotify Register notiﬁcation when packages of a certain type are installed.
UnregisterPackageNotify Unregister notiﬁcation of packages.
FindKeyboardLayouts Retrieves a list of the keyboard layouts in the system.
GetKeyboardLayout Allows a program to extract the current keyboard layout. See the GetKeyboardLayout() func-
SetKeyboardLayout Changes the current keyboard layout. See the SetKeyboardLayout() function description.
GetPackageListHandle Return the EFI handle associated with a given package list.
34.8.2 EFI_HII_DATABASE_PROTOCOL.NewPackageList()
Summary
Adds the packages in the package list to the HII database.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_NEW_PACK) (
IN CONST EFI_HII_DATABASE_PROTOCOL *This,
IN CONST EFI_HII_PACKAGE_LIST_HEADER *PackageList,
IN CONST EFI_HANDLE DriverHandle, OPTIONAL
OUT EFI_HII_HANDLE *Handle
);
This A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
PackageList A pointer to an EFI_HII_PACKAGE_LIST_HEADER structure.
34.8. Database Protocol 1657Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DriverHandle Associate the package list with this EFI handle
Handle A pointer to the EFI_HII_HANDLE instance. Type EFI_HII_HANDLE is deﬁned in “Related Deﬁnitions”
below.
This function adds the packages in the package list to the database and returns a handle. If there is a
EFI_DEVICE_PATH_PROTOCOL associated with the DriverHandle, then this function will create a package of type
EFI_PACKAGE_TYPE_DEVICE_PATH and add it to the package list.
For each package in the package list, registered functions with the notiﬁcation type NEW_PACK and having the same
package type will be called.
For each call to NewPackageList(), there should be a corresponding call to
EFI_HII_DATABASE_PROTOCOL.RemovePackageList() .
typedef void *EFI_HII_HANDLE:
EFI_SUCCESS The package list associated with the Handle was added to the HII database.
EFI_OUT_OF_RESOURCES Unable to allocate necessary resources for the new database contents.
EFI_INV ALID_PARAMETER PackageList isNULL orHandle isNULL .
34.8.3 EFI_HII_DATABASE_PROTOCOL.RemovePackageList()
Summary
Removes a package list from the HII database.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_REMOVE_PACK) (
IN EFI_HII_HANDLE Handle
);
Handle The handle that was registered to the data that is requested for removal. Type EFI_HII_HANDLE is deﬁned
inEFI_HII_DATABASE_PROTOCOL.NewPackageList() in the Packages section.
This function removes the package list that is associated with a handle Handle from the HII database. Before removing
the package, any registered functions with the notiﬁcation type REMOVE_PACK and the same package type will be
called.
For each call to EFI_HII_DATABASE_PROTOCOL.NewPackageList() , there should be a corresponding call to Re-
movePackageList.
34.8. Database Protocol 1658Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The data associated with the Handle was removed from the HII database.
EFI_NOT_FOUND The speciﬁed Handle is not in the Database.
34.8.4 EFI_HII_DATABASE_PROTOCOL.UpdatePackageList()
Summary
Update a package list in the HII database.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_UPDATE_PACK) (
IN EFI_HII_HANDLE Handle,
);
Handle The handle that was registered to the data that is requested to be updated. Type EFI_HII_HANDLE is deﬁned
PackageList A pointer to an instance of EFI_HII_PACKAGE_LIST_HEADER.
This function updates the existing package list (which has the speciﬁed Handle ) in the HII databases, using the new
package list speciﬁed by PackageList. The update process has the following steps:
Collect all the package types in the package list speciﬁed by PackageList. A package type consists of the Type ﬁeld
ofEFI_HII_PACKAGE_HEADER and, if the Type isEFI_HII_PACKAGE_TYPE_GUID, theGuid ﬁeld, as deﬁned in
EFI_HII_GUID_PACKAGE_HDR.
Iterate through the packages within the existing package list in the HII database speciﬁed by Handle. If a package’s
type matches one of the types collected in step 1, then perform the following steps:
• Call any functions registered with the notiﬁcation type REMOVE_PACK.

• Remove the package from the package list and the HII database.
Add all of the packages within the new package list speciﬁed by PackageList, using the following steps:
• Add the package to the package list and the HII database.
• Call any functions registered with the notiﬁcation type ADD_PACK.
EFI_SUCCESS The HII database was successfully updated.
EFI_OUT_OF_RESOURCES Unable to allocate enough memory for the updated database.
EFI_INV ALID_PARAMETER PackageList wasNULL.
34.8. Database Protocol 1659Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.8.5 EFI_HII_DATABASE_PROTOCOL.ListPackageLists()
Summary
Determines the handles that are currently active in the database.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_LIST_PACKS) (
IN UINT8 PackageType,
IN CONST EFI_GUID *PackageGuid,
IN OUT UINTN *HandleBufferLength,
);
PackageType Speciﬁes the package type of the packages to list or EFI_HII_PACKAGE_TYPE_ALL for all packages
to be listed.
PackageGuid IfPackageType isEFI_HII_PACKAGE_TYPE_GUID, then this is the pointer to the GUID which must
match the Guid ﬁeld of EFI_HII_GUID_PACKAGE_HDR. Otherwise, it must be NULL .
HandleBufferLength On input, a pointer to the length of the handle buffer. On output, the length of the handle buffer
that is required for the handles found.
Handle An array of EFI_HII_HANDLE instances returned. Type EFI_HII_HANDLE is deﬁned in
EFI_HII_DATABASE_PROTOCOL.NewPackageList() in the Packages section.
This function returns a list of the package handles of the speciﬁed type that are currently active in the database. The
pseudo-type EFI_HII_PACKAGE_TYPE_ALL will cause all package handles to be listed.
EFI_SUCCESS A list of Packages was placed in Handle successfully. HandleBufferLength
is updated with the actual length.
EFI_BUFFER_TOO_SMALL The HandleBufferLength parameter indicates that Handle is too small to
support the number of handles. HandleBufferLength is updated with a value
that will enable the data to ﬁt.
EFI_INV ALID_PARAMETER HandleBufferLength wasNULL.
EFI_INV ALID_PARAMETER The value referenced by HandleBufferLength was not zero and Handle was
NULL.
EFI_INV ALID_PARAMETER PackageType is a EFI_HII_PACKAGE_TYPE_GUID butPackageGuid is
notNULL.
NULL.
EFI_NOT_FOUND No matching handles were found
34.8. Database Protocol 1660Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.8.6 EFI_HII_DATABASE_PROTOCOL.ExportPackageLists()
Summary
Exports the contents of one or all package lists in the HII database into a buffer.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_EXPORT_PACKS) (
OUT EFI_HII_PACKAGE_LIST_HEADER *Buffer
);
Handle AnEFI_HII_HANDLE that corresponds to the desired package list in the HII database to export or NULL to
indicate all package lists should be exported.
BufferSize On input, a pointer to the length of the buffer. On output, the length of the buffer that is required for the
exported data.
Buffer A pointer to a buffer that will contain the results of the export function.
This function will export one or all package lists in the database to a buffer. For each package list exported, this
function will call functions registered with EXPORT_PACK and then copy the package list to the buffer. The registered
functions may call EFI_HII_DATABASE_PROTOCOL.UpdatePackageList() to modify the package list before it is
copied to the buffer.
If the speciﬁed BufferSize is too small, then the status EFI_BUFFER_TOO_SMALL will be returned and the actual
package size will be returned in BufferSize.
EFI_SUCCESS Package exported.
EFI_BUFFER_TOO_SMALL BufferSize is too small to hold the package.
EFI_INV ALID_PARAMETER BufferSize was NULL
EFI_INV ALID_PARAMETER The value referenced by BufferSize was not zero and Buffer wasNULL .
EFI_NOT_FOUND The speciﬁed Handle could not be found in the current database.
34.8.7 EFI_HII_DATABASE_PROTOCOL.RegisterPackageNotify()
Summary
Registers a notiﬁcation function for HII database-related events.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_REGISTER_NOTIFY) (
34.8. Database Protocol 1661Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN CONST EFI_HII_DATABASE_NOTIFY PackageNotifyFn,
IN EFI_HII_DATABASE_NOTIFY_TYPE NotifyType,
OUT EFI_HANDLE *NotifyHandle
);
PackageType The package type. See EFI_HII_PACKAGE_TYPE_x in EFI_HII_PACKAGE_HEADER .
PackageNotifyFn Points to the function to be called when the event speciﬁed by NotiﬁcationType occurs. See `.
NotifyType Describes the types of notiﬁcation which this function will be receiving. See
EFI_HII_DATABASE_NOTIFY for more a list of types.
NotifyHandle Points to the unique handle assigned to the registered notiﬁcation. Can be used in
EFI_HII_DATABASE_PROTOCOL.UnregisterPackageNotify() to stop notiﬁcations.
This function registers a function which will be called when speciﬁed actions related to packages of the speciﬁed type
occur in the HII database. By registering a function, other HII-related drivers are notiﬁed when speciﬁc package types
are added, removed or updated in the HII database.
Each driver or application which registers a notiﬁcation should use EFI_HII_DATABASE_PROTOCOL.UnregisterPackageNotify()
before exiting.
If a driver registers a NULL PackageGuid when PackageType isEFI_HII_PACKAGE_TYPE_GUID, a notiﬁcation
will occur for every package of type EFI_HII_PACKAGE_TYPE_GUID that is registered.
EFI_HII_PACKAGE_HEADER is deﬁned in EFI_HII_PACKAGE_HEADER .
EFI_HII_DATABASE_NOTIFY is deﬁned in EFI_HII_DATABASE_NOTIFY .
EIF_HII_DATABASE_NOTIFY_TYPE is deﬁned in EFI_HII_DATABASE_NOTIFY_TYPE .
Returned Status Codes
EFI_SUCCESS Notiﬁcation registered successfully.
EFI_INV ALID_PARAMETER NotifyHandle isNULL.
EFI_INV ALID_PARAMETER PackageType is not an EFI_HII_PACKAGE_TYPE_GUID butPackageGuid
NULL
34.8. Database Protocol 1662Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.8.8 EFI_HII_DATABASE_PROTOCOL.UnregisterPackageNotify()
Summary
Removes the speciﬁed HII database package-related notiﬁcation.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_UNREGISTER_NOTIFY) (
IN EFI_HANDLE NotificationHandle
);
EFI_SUCCESS Invalidated
EFI_NOT_FOUND TheNotiﬁcationHandle could not be found in the database.
34.8.9 EFI_HII_DATABASE_PROTOCOL.FindKeyboardLayouts()
Summary
Retrieves a list of the keyboard layouts in the system.
Prototype
typedef
(EFIAPI *EFI_HII_FIND_KEYBOARD_LAYOUTS) (
IN OUT UINT16 *KeyGuidBufferLength,
OUT EFI_GUID *KeyGuidBuffer
);
KeyGuidBufferLength On input, a pointer to the length of the keyboard GUID buffer. On output, the length of the
handle buffer that is required for the handles found.
KeyGuidBuffer An array of keyboard layout GUID instances returned.
This routine retrieves an array of GUID values for each keyboard layout that was previously registered in the system.
EFI_SUCCESS KeyGuidBuffer was updated successfully.
34.8. Database Protocol 1663Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 34.29 – continued from previous page
EFI_BUFFER_TOO_SMALL The KeyGuidBufferLength parameter indicates that KeyGuidBuffer is too
small to support the number of GUIDs. KeyGuidBufferLength is updated
with a value that will enable the data to ﬁt.
EFI_INV ALID_PARAMETER KeyGuidBufferLength isNULL.
EFI_INV ALID_PARAMETER The value referenced by KeyGuidBufferLength is not zero and KeyGuid-
Buffer isNULL .
34.8.10 EFI_HII_DATABASE_PROTOCOL.GetKeyboardLayout()
Summary
Retrieves the requested keyboard layout.
Prototype

Summary
Prototype
typedef
(EFIAPI *EFI_HII_GET_KEYBOARD_LAYOUT) (
IN EFI_GUID *KeyGuid,
IN OUT UINIT16 *KeyboardLayoutLength,
OUT EFI_HII_KEYBOARD_LAYOUT *KeyboardLayout
);
KeyGuid A pointer to the unique ID associated with a given keyboard layout. If KeyGuid is NULL then the current
layout will be retrieved.
KeyboardLayout A pointer to a buffer containing the retrieved keyboard layout. below.
KeyboardLayoutLength On input, a pointer to the length of the KeyboardLayout buffer. On output, the length of
the data placed into KeyboardLayout.
This routine retrieves the requested keyboard layout. The layout is a physical description of the keys on a keyboard
and the character(s) that are associated with a particular set of key strokes.
// EFI_HII_KEYBOARD_LAYOUT
UINT16 LayoutLength;
UINT32 LayoutDescriptorStringOffset;
UINT8 DescriptorCount;
EFI_KEY_DESCRIPTOR Descriptors[];
} EFI_HII_KEYBOARD_LAYOUT;
LayoutLength The length of the current keyboard layout.
Guid The unique ID associated with this keyboard layout.
34.8. Database Protocol 1664Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
LayoutDescriptorStringOffset An offset location (0 is the beginning of the EFI_KEYBOARD_LAYOUT in-
stance) of the string which describes this keyboard layout. The data that is being referenced is in
EFI_DESCRIPTION_STRING_BUNDLE format.
DescriptorCount The number of Descriptor entries in this layout.
Descriptors An array of key descriptors.
// EFI_DESCRIPTION_STRING - byte packed data
CHAR16 Language[];
CHAR16 Space;
//CHAR16 DescriptionString[];
Language The language in RFC 4646 format to associate with DescriptionString.
Space A space (U-0x0020) character to force as a separator between the Language ﬁeld and the formal description
string.
DescriptionString A null-terminated description string.
// EFI_DESCRIPTION_STRING_BUNDLE - byte packed data
//
// Example: 2en-US English Keyboard<null>es-ES Keyboard en ingles<null>
// <null> = U-0000
UINT16 DescriptionCount;
EFI_DESCRIPTION_STRING DescriptionString[];
DescriptionCount The number of description strings.
DescriptionString An array of language-speciﬁc description strings.
// EFI_KEY_DESCRIPTOR
EFI_KEY Key;
CHAR16 Unicode;
CHAR16 ShiftedUnicode;
CHAR16 AltGrUnicode;
CHAR16 ShiftedAltGrUnicode;
UINT16 Modifier;
UINT16 AffectedAttribute;
} EFI_KEY_DESCRIPTOR;
// A key which isaffected by all the standard shift modifiers.
// Most keys would be expected to have this bit active.
#define EFI_AFFECTED_BY_STANDARD_SHIFT 0x0001
// This key isaffected by the caps lock so that ifa keyboard
// driver would need to disambiguate between a key which had a
// "1" defined versus a "a" character. Having this bit turned on
// would tell the keyboard driver to use the appropriate shifted // state or not.
#define EFI_AFFECTED_BY_CAPS_LOCK 0x0002
// Similar to the case of CAPS lock, ifthis bit isactive, the
34.8. Database Protocol 1665Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// keyisaffected by the num lock being turned on.
#define EFI_AFFECTED_BY_NUM_LOCK 0x0004
Key Used to describe a physical key on a keyboard. Type EFI_KEY is deﬁned below.
Unicode Unicode character code for the Key.
ShiftedUnicode Unicode character code for the key with the shift key being held down.
AltGrUnicode Unicode character code for the key with the Alt-GR being held down.
ShiftedAltGrUnicode Unicode character code for the key with the Alt-GR and shift keys being held down.
Modiﬁer Modiﬁer keys are deﬁned to allow for special functionality that is not necessarily accomplished by a print-
able character. Many of these modiﬁer keys are ﬂags to toggle certain state bits on and off inside of a keyboard
driver. Values for Modiﬁer are deﬁned below.
// EFI_KEY
EfiKeyLCtrl, EfiKeyA0, EfiKeyLAlt, EfiKeySpaceBar, EfiKeyA2,
EfiKeyA3, EfiKeyA4, EfiKeyRCtrl, EfiKeyLeftArrow,
EfiKeyDownArrow, EfiKeyRightArrow, EfiKeyZero, EfiKeyPeriod,
EfiKeyEnter, EfiKeyLShift, EfiKeyB0, EfiKeyB1, EfiKeyB2,
EfiKeyB3, EfiKeyB4, EfiKeyB5, EfiKeyB6, EfiKeyB7, EfiKeyB8,
EfiKeyB9, EfiKeyB10, EfiKeyRShift, EfiKeyUpArrow, EfiKeyOne,
EfiKeyTwo, EfiKeyThree, EfiKeyCapsLock, EfiKeyC1, EfiKeyC2,
EfiKeyC3, EfiKeyC4, EfiKeyC5, EfiKeyC6, EfiKeyC7, EfiKeyC8,
EfiKeyC9, EfiKeyC10, EfiKeyC11, EfiKeyC12, EfiKeyFour,
EfiKeyFive, EfiKeySix, EfiKeyPlus, EfiKeyTab, EfiKeyD1,
EfiKeyD2, EfiKeyD3, EfiKeyD4, EfiKeyD5, EfiKeyD6, EfiKeyD7,
EfiKeyD8, EfiKeyD9, EfiKeyD10, EfiKeyD11, EfiKeyD12, EfiKeyD13,
EfiKeyDel, EfiKeyEnd, EfiKeyPgDn, EfiKeySeven, EfiKeyEight,
EfiKeyNine, EfiKeyE0, EfiKeyE1, EfiKeyE2, EfiKeyE3, EfiKeyE4,
EfiKeyE5, EfiKeyE6, EfiKeyE7, EfiKeyE8, EfiKeyE9, EfiKeyE10,
EfiKeyE11, EfiKeyE12, EfiKeyBackSpace, EfiKeyIns, EfiKeyHome,
EfiKeyPgUp, EfiKeyNLck, EfiKeySlash, EfiKeyAsterisk,
EfiKeyMinus, EfiKeyEsc, EfiKeyF1, EfiKeyF2, EfiKeyF3, EfiKeyF4,
EfiKeyF5, EfiKeyF6, EfiKeyF7, EfiKeyF8, EfiKeyF9, EfiKeyF10,
EfiKeyF11, EfiKeyF12, EfiKeyPrint, EfiKeySLck, EfiKeyPause,
EfiKeyIntl0, EfiKeyIntl1, EfiKeyIntl2, EfiKeyIntl3,
EfiKeyIntl4, EfiKeyIntl5, EfiKeyIntl6, EfiKeyIntl7,
EfiKeyIntl8, EfiKeyIntl9
} EFI_KEY;
See the ﬁgure below for which key corresponds to the values in the enumeration above. For example, EﬁKeyLCtrl
corresponds to the left control key in the lower-left corner of the keyboard, EﬁKeyFour corresponds to the 4 key on the
numeric keypad, and EﬁKeySLck corresponds to the Scroll Lock key in the upper-right corner of the keyboard.
// Modifier values
#define EFI_NULL_MODIFIER 0x0000
#define EFI_LEFT_CONTROL_MODIFIER 0x0001
#define EFI_RIGHT_CONTROL_MODIFIER 0x0002
#define EFI_LEFT_ALT_MODIFIER 0x0003
#define EFI_RIGHT_ALT_MODIFIER 0x0004
34.8. Database Protocol 1666Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 34.3: Keyboard Layout
#define EFI_ALT_GR_MODIFIER 0x0005
#define EFI_INSERT_MODIFIER 0x0006
#define EFI_DELETE_MODIFIER 0x0007
#define EFI_PAGE_DOWN_MODIFIER 0x0008
#define EFI_PAGE_UP_MODIFIER 0x0009
#define EFI_HOME_MODIFIER 0x000A
#define EFI_END_MODIFIER 0x000B
#define EFI_LEFT_SHIFT_MODIFIER 0x000C
#define EFI_RIGHT_SHIFT_MODIFIER 0x000D
#define EFI_CAPS_LOCK_MODIFIER 0x000E
#define EFI_NUM_LOCK_MODIFIER 0x000F
#define EFI_LEFT_ARROW_MODIFIER 0x0010
#define EFI_RIGHT_ARROW_MODIFIER 0x0011
#define EFI_DOWN_ARROW_MODIFIER 0x0012
#define EFI_UP_ARROW_MODIFIER 0x0013
#define EFI_NS_KEY_MODIFIER 0x0014
#define EFI_NS_KEY_DEPENDENCY_MODIFIER 0x0015
#define EFI_FUNCTION_KEY_ONE_MODIFIER 0x0016
#define EFI_FUNCTION_KEY_TWO_MODIFIER 0x0017
#define EFI_FUNCTION_KEY_THREE_MODIFIER 0x0018
#define EFI_FUNCTION_KEY_FOUR_MODIFIER 0x0019
#define EFI_FUNCTION_KEY_FIVE_MODIFIER 0x001A
#define EFI_FUNCTION_KEY_SIX_MODIFIER 0x001B
#define EFI_FUNCTION_KEY_SEVEN_MODIFIER 0x001C
#define EFI_FUNCTION_KEY_EIGHT_MODIFIER 0x001D
#define EFI_FUNCTION_KEY_NINE_MODIFIER 0x001E
#define EFI_FUNCTION_KEY_TEN_MODIFIER 0x001F
#define EFI_FUNCTION_KEY_ELEVEN_MODIFIER 0x0020
#define EFI_FUNCTION_KEY_TWELVE_MODIFIER 0x0021
//
// Keys that have multiple control functions based on modifier
// settings are handled inthe keyboard driver implementation.
// For instance PRINT_KEY might have a modifier held down and
//isstill a nonprinting character, but might have an alternate
// control function like SYSREQUEST
//
#define EFI_PRINT_MODIFIER 0x0022
#define EFI_SYS_REQUEST_MODIFIER 0x0023
#define EFI_SCROLL_LOCK_MODIFIER 0x0024
#define EFI_PAUSE_MODIFIER 0x0025
#define EFI_BREAK_MODIFIER 0x0026
#define EFI_LEFT_LOGO_MODIFIER 0x0027
#define EFI_RIGHT_LOGO_MODIFIER 0x0028
#define EFI_MENU_MODIFIER 0x0029
34.8. Database Protocol 1667Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The keyboard layout was retrieved successfully.
EFI_NOT_FOUND The requested keyboard layout was not found.
EFI_BUFFER_TOO_SMALL TheKeyboardLayoutLength parameter indicates the KeyboardLayout is too
small to hold the keyboard layout.
EFI_INV ALID_PARAMETER KeyboardLayoutLength isNULL
EFI_INV ALID_PARAMETER The value referenced by KeyboardLayoutLength is not zero and Keyboard-
Layout is NULL.

//
34.8.11 EFI_HII_DATABASE_PROTOCOL.SetKeyboardLayout()
Summary
Sets the currently active keyboard layout.
Prototype
typedef
(EFIAPI *EFI_HII_SET_KEYBOARD_LAYOUT) (
IN EFI_GUID *KeyGuid
);
KeyGuid A pointer to the unique ID associated with a given keyboard layout.
This routine sets the default keyboard layout to the one referenced by KeyGuid. When this routine is called, an event
will be signaled of the EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID group type. This is so that agents which
are sensitive to the current keyboard layout being changed can be notiﬁed of this change.
GUID
#define EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID \
{ 0x14982a4f, 0xb0ed, 0x45b8, \
{ 0xa8, 0x11, 0x5a, 0x7a, 0x9b, 0xc2, 0x32, 0xdf }}
EFI_SUCCESS The current keyboard layout was successfully set.
EFI_NOT_FOUND The referenced keyboard layout was not found, so action was taken.
EFI_INV ALID_PARAMETER KeyGuid isNULL .
34.8. Database Protocol 1668Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
34.8.12 EFI_HII_DATABASE_PROTOCOL.GetPackageListHandle()
Summary
Return the EFI handle associated with a package list.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_GET_PACK_HANDLE) (
IN EFI_HII_HANDLE PackageListHandle,
OUT EFI_HANDLE *DriverHandle
);
PackageListHandle AnEFI_HII_HANDLE that corresponds to the desired package list in the HIIdatabase.
DriverHandle On return, contains the EFI_HANDLE which was registered with the package list in NewPackage-
List().
EFI_SUCCESS TheDriverHandle was returned successfully.
EFI_INV ALID_PARAMETER ThePackageListHandle was not valid.
EFI_INV ALID_PARAMETER TheDriverHandle must not be NULL .
34.8.13 Database Structures
34.8.13.1 EFI_HII_DATABASE_NOTIFY
Summary
Handle a registered notiﬁcation for a package change to the database.
Prototype
typedef
(EFIAPI *EFI_HII_DATABASE_NOTIFY) (
IN CONST EFI_HII_PACKAGE_HEADER *Package,
IN EFI_HII_DATABASE_NOTIFY_TYPE NotifyType
);
PackageType Package type of the notiﬁcation.
PackageGuid IfPackageType isEFI_HII_PACKAGE_TYPE_GUID, then this is the pointer to the GUID from the
Guid ﬁeld of EFI_HII_GUID_PACKAGE_HDR. Otherwise, it must be NULL .
Package Points to the package referred to by the notiﬁcation
34.8. Database Protocol 1669Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Handle The handle of the package list which contains the speciﬁed package.
NotifyType The type of change concerning the database. See EFI_HII_DATABASE_NOTIFY_TYPE .
Functions which are registered to receive notiﬁcation of database events have this prototype. The actual event is
encoded in NotifyType. The following table describes how PackageType, PackageGuid, Handle, andPackage are used
for each of the notiﬁcation types.
Notiﬁcation
TypeParameter Description
NEW_PACK PackageType andPackageGuid are the type of the new package. Package points to the new
package. Handle is the handle of the package list which is being added to the database.
REMOVE_PACK PackageType andPackageGuid are the type of the package which is being removed. Package
points to the package being removed. Handle is the package list from which the package is
being removed.
EXPORT_PACK PackageType andPackageGuid are the type of the package being exported. Package points to
the existing package in the database. Handle is the package list being exported.
ADD_PACK PackageType andPackageGuid are the type of the package being added. Package points to the
package being added. Handle is the package list to which the package is being added.
34.8.14 EFI_HII_DATABASE_NOTIFY_TYPE
typedef UINTN EFI_HII_DATABASE_NOTIFY_TYPE;
#define EFI_HII_DATABASE_NOTIFY_NEW_PACK 0x00000001
#define EFI_HII_DATABASE_NOTIFY_REMOVE_PACK 0x00000002
#define EFI_HII_DATABASE_NOTIFY_EXPORT_PACK 0x00000004
#define EFI_HII_DATABASE_NOTIFY_ADD_PACK 0x00000008
34.8. Database Protocol 1670CHAPTER
THIRTYFIVE
HII CONFIGURATION PROCESSING AND BROWSER PROTOCOL
35.1 Introduction
This section describes the data and APIs used to manage the system’s conﬁguration: the actual data that describes the
knobs and settings.
35.1.1 Common Conﬁguration Data Format
The conﬁguration data is stored as name / value string pairs. As in e.g. HTML, the name and value are separated by
‘=’ and the pairs are separated one from the next by ‘&’. The conﬁguration data structures are thus variable length
UNICODE (UCS-2) strings.
Certain names and values have limitations on their syntax to manage routing and to enable extended support for
common storage mechanisms.
35.1.2 Data Flow
There is a two-way ﬂow through the hierarchy of drivers and protocols that parallels the ﬂow in other parts of HII.
Initially, the ﬂow is from the drivers up to the HII database and on to conﬁguration applications. When changes to
conﬁguration are accepted, the ﬂow reverses itself, going from the conﬁguration applications through the HII database
protocols back to the drivers through separate protocols.
The ﬂow from driver up consists of the current and alternative (default) conﬁgurations. The ﬂow down from the
conﬁguration applications consists of changed conﬁgurations.
The protocol managed by the HII Database is known as the EFI HII Conﬁguration Routing Protocol, while the one
presented by the drivers themselves is known as the EFI HII Conﬁguration Access Protocol. The HII Conﬁguration
Routing Protocol is the only one that outside callers should invoke.
35.2 Conﬁguration Strings
The conﬁguration strings follow the same general format as HTTP argument strings, which is to say ‘&’ separated
name / value pairs. The name and value are separated by ‘=’. The strings are a subset of full HTML argument strings
and do not require quoting, the ‘%’ character sequences used to insert spaces, ampersands, equal signs, and the like
into HTTP argument strings.
1671Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
35.2.1 String Syntax
Assumptions are typical for BNF with the following extensions
Characters in single quotes, e.g. ‘a’, indicate terminals.
Square brackets immediately followed by a number n indicate that the contents are to be repeated n times, so [‘a’]4
would be “aaaa”.
An italicized non-terminal, e. g. <All Printable ASCII Characters> is used to indicate a set of terminals whose
deﬁnition is outside the scope of this document.
The syntax for conﬁguration strings is as follows.
35.2.1.1 Basic forms
<Dec19> ::= ‘1’ | ‘2’ |... | ‘9’
<DecCh> ::= ‘0’ | <Dec19>
<HexAf> ::= ‘a’ | ‘b’ | ‘c’ | ‘d’ | ‘e’ | ‘f’
<Hex1f> ::= <Dec19> | <HexAf>
<HexCh> ::= <DecCh> | <HexAf>
<Number> ::= <HexCh>+
<Alpha> ::= ‘a’ |... | ‘z’ | ‘A’ |... | ‘Z’
35.2.1.2 Types
<Guid> ::= <HexCh>32
<LabelStart> ::= <Alpha> | "_"
<LabelBody> ::= <LabelStart> | <DecCh>
<Label> ::= <LabelStart> [<LabelBody>] *
<Char> ::= <HexCh>4
<String> ::= [<Char>]+
<AltCfgId> ::= <HexCh>4
35.2.1.3 Routing elements
<GuidHdr> ::= ‘GUID=’<Guid>
<NameHdr> ::= ‘NAME=’<String>
<PathHdr> ::= ‘PATH=’<UEFI binary Device Path represented as
hex number>
<DescHdr> ::= ‘ALTCFG=’<AltCfgId>
<ConfigHdr> ::= <GuidHdr>’&’<NameHdr>’&’<PathHdr>
<AltConfigHdr> ::= <ConfigHdr> ‘&’<DescHdr>
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35.2.1.4 Body elements
<ConfigBody> ::= <ConfigElement> *
<ConfigElement> ::= ‘&’<BlockConfig> | ‘&’<NvConfig>
<BlockName> ::= ‘OFFSET=’<Number>’&WIDTH=’<Number>
<BlockConfig> ::= <BlockName>’&VALUE=’<Number>
<RequestElement> ::= ‘&’<BlockName> | ‘&’<Label>
<NvConfig> ::= <Label>’=’<String> | <Label>’=’<Number>
35.2.1.5 Conﬁguration strings
<ConfigRequest> ::= <ConfigHdr><RequestElement> *
<MultiConfigRequest> ::= <ConfigRequest>[‘&’ <ConfigRequest>] *
<ConfigResp> ::= <ConfigHdr><ConfigBody>
<AltResp> ::= <AltConfigHdr><ConfigBody>
<ConfigAltResp> ::= <ConfigResp> [‘&’ <AltResp>] *
<MultiConfigAltResp> ::= <ConfigAltResp> [‘&’ <ConfigAltResp>] *
<MultiConfigResp> ::= <ConfigResp> [‘&’<ConfigResp>] *
Notes:
The<Number> represents a data buffer and is encoded as a sequence of bytes in the format %02x in the same order
as the buffer bytes reside in memory.
The <Guid> represents a hex encoding of GUID and is encoded as a sequence of bytes in the format %02x in the
same order as the GUID bytes reside in memory.
The syntax for a <Label> is the C label (e.g. Variable) syntax.
The<ConﬁgHdr> provides routing information. The name ﬁeld is required even if non-block storage is targeted. In
these cases, it may be used as a way to distinguish like storages from one another when a driver is being used

Notes:
The <BlockName> provides addressing information for managing block (e.g. UEFI Variable) storage. The ﬁrst
number provides the byte offset into the block while the second provides the length of bytes.
The<PathHdr> presents a hex encoding of a UEFI device path. This is not the printable path since the printable path
is optional in UEFI and to enable simpler comparisons. The data is encoded as strings with the format %02x bytes in
the same order as the device path resides in RAM memory.
The<ConﬁgRequest> provides a mechanism to request the current conﬁguration for one or more elements.
The<AltCfgId> is the identiﬁer of a conﬁguration declared in the corresponding IFR.
The name ‘GUID’ is also used to separate <String> or<ConﬁgRequest> elements in the equivalent Multi version.
That is:
*GUID=...&NAME=...&...&fred=12&GUID=...&NAME=...&...&goyle=11 *
Indicates two <String>, with one ending with fred=12 .
The following are reserved <name> s and cannot be used as names in a <ConﬁgElement> :
GUID
NAME
PATH
ALTCFG
OFFSET
WIDTH
VALUE
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35.2.1.6 Keyword strings
<NameSpaceId> ::=‘NAMESPACE=’<String>’&’
<Keyword> ::=‘KEYWORD=’<String>[‘:’<DecCh>(1/4)]
<DataFilter> ::=‘Buffer’|‘Numeric’[‘:1’|‘:2’|‘:4’|‘:8’]
|‘String’|‘Boolean’|‘Date’|’Time’
<UsageFilter> ::=‘ReadOnly’|‘ReadWrite’
<Filter> ::=<UsageFilter>|<DataFilter>|<UsageFilter>
’&’<DataFilter>
<ValueRange> ::=‘&MAX=’<Number>‘&MIN=’<Number>[’&STEP=’<Number>]
<ValueOption> ::=‘&OPTIONVALUE=’<Number>’&OPTIONSTRING=’<String>
[‘&VALUETYPE=‘Numeric’[':1’|‘:2’|‘:4’|‘:8’]]
<ValueAttribute> ::=[<ValueRange>][<ValueOption> *]
<Default> ::=[‘&STANDARDDEFAULT=’<Number>]
[‘&MFGDEFAULT=’<Number>]
[‘&SAFEDEFAULT=’<Number>]
<Display> ::=’&DISPLAYNAME=’<String>
<DataType> ::=‘&DATATYPE=’<DataFilter>
<KeywordInfoFilter> ::=‘All’|[‘DataType’][‘ValueAttribute’][‘Default’]
[’DisplayName’]
<Boolean> ::=’True’|’False’
<KeywordInfoRequest> ::=’KEYWORDINFO=’<KeywordInfoFilter>
<KeywordInfoResp> ::=[<DataType>][<ValueAttribute>][<Default>][<Display>]
<KeywordRequest> ::=[<PathHdr>’&’]<Keyword>
[’&’<KeywordInfoRequest>][’&’<Filter>]
<KeywordResp> ::=<NameSpaceId><PathHdr>’&’<Keyword>’&VALUE=’<Number>
[‘&READONLY’][<KeywordInfoResp>]
<MultiKeywordRequest> ::=<KeywordRequest>[‘&’<KeywordRequest>] *
<MultiKeywordResp> ::=<KeywordResp>[‘&’<KeywordResp>] *
NOTE :For Keyword deﬁnitions, see the UEFI Conﬁguration Namespace Registry document on http://ueﬁ.org/ueﬁ.
HII Question Type HII Keyword Data Type Data information in <ValueAt-
tribute>
Numeric Numeric ValueRanges
One-Of Numeric ValueOptions
Checkbox Boolean
String String ValueRanges
Ordered-List Buffer ValueOptions
Date Date
Time Time
The<NameSpaceId> element is equivalent to the platform conﬁguration language being used for the keyword deﬁni-
tion*.
The<Keyword> element uses the ‘KEYWORD=’ name to designate that immediately following the reserved name is
a string value associated with a conﬁguration namespace keyword as deﬁned in the Conﬁguration NameSpace Registry
document ( http://ueﬁ.org/ueﬁ ).
Typically, when a Keyword is deﬁned, the value is a solitary string such as “BIOSVendor”. However, when certain
Keywords are intended to represent a setting that may have multiple instances (e.g. ChipsetSATAPortEnable), that
is when a “:<DecCh>(1/4)” sufﬁx will be appended to the keyword deﬁnition. In that case, we might see something
like: “ChipsetSATAPortEnable:5” if a particular platform had at least ﬁve SATA ports and one of the questions was
represented by the aforementioned string. It would also be reasonable to expect that there might also be a “Chipset-
SATAPortEnable:1” and a “:2”, “:3” etc.
35.2. Conﬁguration Strings 1674Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If the <PathHdr> element within <KeywordRequest> is omitted, then all instances are returned.
If the Keyboard Handler protocol knows or detects that a particular Keyword is read-only, then the <KeywordResp>
must include the “&READONLY” tag.
The<DataFilter> element speciﬁes the optional ﬁlter based on data type to use when a request is made. If no ﬁltering
is desired, then this element must be omitted from the <KeywordRequest> . Filtering is not guaranteed to work on any
platform conﬁguration language that isn’t deﬁned in the UEFI Conﬁguration Namespace Document.
DataFilter.Buffer
HII questions with EFI_IFR_TYPE_BUFFER type are treated as this type. This is most commonly represented in ‘C’
as a VOID type, or as a more complex type. Other than the EFI_IFR_TYPE_BOOLEAN andEFI_IFR_TYPE_NUM_x
data types, all of the HII conﬁguration data types are treated as a sequence of data.
DataFilter.Numeric
A sequence of data that must be interpreted as a one, two, four, or eight-byte wide numeric value. For instance, a
deﬁnition of “Numeric:2” would indicate that the keyword is a two-byte numeric value. If no byte-size designation is
speciﬁed, then the value may vary in size.
DataFilter.String
HII questions with EFI_IFR_TYPE_STRING type are treated as this type.
DataFilter.Boolean
HII questions with EFI_IFR_TYPE_BOOLEAN type are treated as this type.
DataFilter.Date
HII questions with EFI_IFR_TYPE_DATE type are treated as this type.
DataFilter.Time
HII questions with EFI_IFR_TYPE_TIME type are treated as this type.
The <UsageFilter> element deﬁnes the optional ﬁlter to use based on usage type when a request is made. If no
ﬁltering is desired, then this element must be omitted from the <KeywordRequest> .
UsageType.ReadOnly
The data for the keyword cannot be changed. It is intended solely for informational purposes, and can be used to read
a setting that may be static or dynamic (e.g. CPU temperature).
UsageType.ReadWrite
The data for the keyword can be changed.
The<KeywordInfoRequest> element allows the callers to request some additional information of the keyword to be
returned. <KeywordInfoRequest> element is used when user doesn’t know the information about the keyword and
wants to get more information about this keyword. When <KeywordInfoRequest> element is speciﬁed with <Keywor-
dRequest>, the<KeywordInfoResp> element will be speciﬁed with <KeywordResp> to return the info requested by
<KeywordInfoRequest> .
The<KeywordInfoFilter> element is used to specify the additional information that caller wants to know about the
keyword. Caller can specify any type of additional information he/she wants to know. When ‘All’ is speciﬁed, means
all the supported information need to be returned.
The<DataType> element speciﬁes the data type of a keyword, can refer to <DataFilter> for the detailed info the data
types.
The<ValueAttribute> element speciﬁes the value attribute of a keyword. Such as the value range of a keyword or the
selectable values for a keyword.
35.2. Conﬁguration Strings 1675Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
<ValueRange> element speciﬁes the variation range of a keyword value. Such as it can be speciﬁed for a keyword
used in EFI_IFR_NUMERIC_OP , EFI_IFR_STRING_OP opcode. For EFI_IFR_NUMERIC_OP opcode, it speciﬁes
the maximum value, minimum value and increment or decrement step. For EFI_IFR_STRING_OP opcode, it speciﬁes
the maximum length and minimum length of the string can be input.
<ValueOption> element speciﬁes all the (selectable) values and related string representation of these values for a
keyword. Such as it can be speciﬁed for keyword used in EFI_IFR_ONE_OF_OP , EFI_IFR_ORDERED_LIST_OP
opcode. For EFI_IFR_ONE_OF_OP , it speciﬁes the all selectable values and the string representation of the values.
The keyword value can be one of them.
ForEFI_IFR_ORDERED_LIST_OP , it speciﬁes all values and the string representation of the values. The keyword
value can be the permutation and combination of these values. And for EFI_IFR_ORDERED_LIST_OP , its data type
is Buffer, so can return the value type in a <ValueOption> to indicate the data stored in the Buffer is numeric as a one,
two, four, or eight-byte wide.
The<Default> element speciﬁes the default value of a keyword. Only the three standard defaults stores are supported
including the standard defaults, the manufacturing defaults and the Safe defaults. If the keyword doesn’t have any
type of defaults, then there is no default info returned. And if the keyword only has the standard default, then only the
standard default information will be returned.
The<Display> element speciﬁes the displayed prompt string of this keyword in the UI page.
35.2.1.6.1 An example of some basic keyword-related strings:
<KeywordRequest> to retrieve the current BIOS Vendor name:
KEYWORD=BIOSVendor
35.2.1.6.2 A possible response might look like:
x-UEFI-ns&KEYWORD=BIOSVendor&VALUE=AcmeBIOSCompany
If a request was made to retrieve all of the settings for a platform, a user would initiate a call to KeywordHandleràGet-
Data() with the KeywordString and NamespaceId being NULL .
35.2.1.6.3 A possible response might look like:

x-UEFI-ns&KEYWORD=BIOSVendor&VALUE=AcmeBIOSCompany&x-UEFI-extension
-ACME&KEYWORD=SpecialSettingX&VALUE=3
In this case, the string returned tells us that there was one discovered keyword called “BIOSVendor” under the standard
UEFI namespace and its value was “AcmeBIOS”. There was also an ACME branded namespace element which was
discovered that had a keyword called “SpecialSettingX” whose value was 3.
35.2. Conﬁguration Strings 1676Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
35.2.1.6.4 An example to get more information of a keyword:
KEYWORD=BIOSVendor&KEYWORDINFO=All
A possible response might look like:
x-UEFI-ns&KEYWORD=BIOSVendor&VALUE=AcmeBIOSCompany&DataType=String&MAX=30&MIN
=6&STANDARDDEFAULT=AcmeBIOSCompany&MFGDEFAULT=AcmeBIOSCompany
35.2.2 String Types
There are six string types. As can be seen from the BNF, the syntax of all is quite similar. The ﬁrst three are used
in communications between drivers and HII. The last three are used for analogous communication between external
applications and HII.
<ConﬁgRequest> : This string is used by HII to request the current and any alternative conﬁgurations from a driver.
It consists of routing information and only ampersand separated names.
<ConﬁgAltResp> : A string in this format is returned by the driver in response to a request to ﬁll in a <ConﬁgRequest>
string. The string consists of the current conﬁguration followed by possibly several alternative conﬁgurations. The
alternative conﬁgurations have the ALTCFG name / value pair in addition to the usual GUID, NAME, andPATH entries
in the routing preﬁx. The ALTCFG value is a Default ID which is used to describe the alternative default conﬁguration.
<ConﬁgResp> : A sting in this format is handed by the HII to the driver to cause the driver to change its conﬁguration.
It consists of routing information and name / value pairs which correspond to the questions in the driver’s IFR. Only
<ConﬁgResp> strings which refer to a driver in question may be handed to that driver. The driver shall reject all
others.
<MultiConﬁgRequest> : A string in this format is handed to HII by an external application in order to request the
current an alternate conﬁgurations of the system’s drivers. The format of this string is a series of <ConﬁgRequest>
strings separated by ampersands. The HII’s job is to separate the requests and hand them off to the appropriate drivers
(as indicated by the routing headers).
<MultiConﬁgAltResp> : A string in this format is handed back to an external application which has requested the
current and alternate conﬁgurations of the system’s drivers. The format of this string is a series of <ConﬁgAltResp>
strings separated by ampersands. The HII creates this string by concatenating the current and alternate conﬁguration
strings provided by each driver.
<MultiConﬁgResp> : A string in this format is handed to the HII in order to update the system’s conﬁguration.
Analogous to the other “Multi” string formats, its syntax is a series of ampersand separated <ConﬁgResp> strings.
Upon receipt, the HII routes the <ConﬁgResp> strings to the corresponding drivers.
35.3 EFI Conﬁguration Keyword Handler Protocol
This section provides a detailed description of the EFI Conﬁguration Keyword Handler Protocol.
35.3. EFI Conﬁguration Keyword Handler Protocol 1677Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
35.3.1 EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL
Summary
TheEFI_CONFIG_KEYWORD_HANDLER_PROTOCOL provides the mechanism to set and get the values associated
with a keyword exposed through a x-UEFI- preﬁxed conﬁguration language namespace.
GUID
#define EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL_GUID \
{ 0x0a8badd5, 0x03b8, 0x4d19,\
{0xb1, 0x28, 0x7b, 0x8f, 0x0e, 0xda, 0xa5, 0x96 }}
typedef struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL {
EFI_CONFIG_KEYWORD_HANDLER_SET_DATA SetData;
EFI_CONFIG_KEYWORD_HANDLER_GET_DATA GetData;
} EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL;
SetData Set the data associated with a particular conﬁguration namespace keyword.
GetData Get the data associated with a particular conﬁguration namespace keyword.
The EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL allows other components in the platform (e.g. Browser,
Manageability Software, etc.) to retrieve and set conﬁguration settings within the system.
Keywords are text elements which are associated with a particular conﬁguration option within the platform. These
keywords are intended to add semantic meaning to the conﬁguration option they are attached to. The text associated
for the keyword would be encoded in a UEFI conﬁguration language. These languages are like French or German
or Japanese, but are not designed for display purposes for an end-user. Instead each language serves as a namespace
for the purposes of grouping and manipulating groups of platform conﬁgurations options. See Working with a UEFI
Conﬁguration Language for more information.
NOTE: Not all conﬁguration options will be associated with a keyword. Associating a keyword with a conﬁguration
option is at the discretion of the platform and/or the hardware vendor. For more information about keyword deﬁnitions
associated with a UEFI namespace, see the UEFI Keyword Namespace Registry link in the UEFI Link Document.
35.3.2 EFI_KEYWORD_HANDLER _PROTOCOL.SetData()
Summary
Set the data associated with a particular conﬁguration namespace keyword.
Prototype
typedef
(EFIAPI *EFI_KEYWORD_HANDLER _SET_DATA) (
IN EFI_KEYWORD_HANDLER_PROTOCOL *This,
IN CONST EFI_STRING KeywordString,
OUT EFI_STRING *Progress,
OUT UINT32 *ProgressErr
);
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This Pointer to the EFI_KEYWORD_HANDLER _PROTOCOL instance.
KeywordString A null-terminated string in <MultiKeywordResp> format.
Progress On return, points to a character in the KeywordString . Points to the string’s NULL terminator if the request
was successful. Points to the most recent ‘&’ before the ﬁrst failing name / value pair (or the beginning of the
string if the failure is in the ﬁrst name / value pair) if the request was not successful.
ProgressErr If during the processing of the KeywordString there was a failure, this parameter gives additional in-
formation about the possible source of the problem. The various errors are deﬁned in “Related Deﬁnitions”
below.
This function accepts a <MultiKeywordResp> formatted string, ﬁnds the associated keyword owners, creates a <Mul-
tiConﬁgResp> string from it and forwards it to the EFI_HII_ROUTING_PROTOCOL.RouteConﬁg function.
If there is an issue in resolving the contents of the KeywordString, then the function returns an error and also sets the
Progress andProgressErr with the appropriate information about where the issue occurred and additional data about
the nature of the issue.
In the case when KeywordString containing multiple keywords, when an EFI_NOT_FOUND error is generated during
processing the second or later keyword element, the system storage associated with earlier keywords is not modi-
ﬁed. All elements of the KeywordString must successfully pass all tests for format and access prior to making any
modiﬁcations to storage.
In the case when EFI_DEVICE_ERROR is returned from the processing of a KeywordString containing multiple
keywords, the state of storage associated with earlier keywords is undeﬁned.
// Progress Errors
#define KEYWORD_HANDLER_NO_ERROR 0x00000000
#define KEYWORD_HANDLER_NAMESPACE_ID_NOT_FOUND 0x00000001
#define KEYWORD_HANDLER_MALFORMED_STRING 0x00000002
#define KEYWORD_HANDLER_KEYWORD_NOT_FOUND 0x00000004
#define KEYWORD_HANDLER_INCOMPATIBLE_VALUE_DETECTED 0x00000008
#define KEYWORD_HANDLER_ACCESS_NOT_PERMITTED 0x00000010
#define KEYWORD_HANDLER_UNDEFINED_PROCESSING_ERROR 0x80000000
TheKEYWORD_HANDLER_x values describe the error values returned in the ProgressErr ﬁeld.
If no errors were encountered, then KEYWORD_HANDLER_NO_ERROR is returned with no bits are set.
If the <NameSpaceId> speciﬁed by the KeywordString was not found in any of the registered conﬁguration data, the
KEYWORD_HANDLER_NAMESPACE_ID_NOT_FOUND bit is set.
If there was an error in the parsing of the KeywordString, the KEYWORD_HANDLER_MALFORMED_STRING bit is
set.
If there was a keyword speciﬁed in the KeywordString which was not found in any of the registered conﬁguration data,
KEYWORD_HANDLER_KEYWORD_NOT_FOUND bit is set.
If the value either passed into KeywordString (during a SetData operation) or the value discovered for the Key-
word (during a GetData operation) did not match what was known to be valid for the deﬁned keyword, the KEY-
WORD_HANDLER_INCOMPATIBLE_VALUE_DETECTED bit is set.

set.
If there was an error as a result of a violation of system policy. For example trying to write a read-only element, the
KEYWORD_HANDLER_ACCESS_NOT_PERMITTED bit is set.
35.3. EFI Conﬁguration Keyword Handler Protocol 1679Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If there was an undeﬁned type of error in processing the passed in data, the KEY-
WORD_HANDLER_UNDEFINED_PROCESSING_ERROR bit is set.
EFI_SUCCESS The speciﬁed action was completed successfully.
EFI_INV ALID_PARAMETER One or more of the following are TRUE :KeywordString isNULL . Parsing
of the KeywordString resulted in an error. See Progress andProgressErr for
more data.
EFI_NOT_FOUND An element of the KeywordString was not found. See ProgressErr for more
data.
EFI_OUT_OF_RESOURCES Required system resources could not be allocated. See ProgressErr for
more data.
EFI_ACCESS_DENIED The action violated system policy. See ProgressErr for more data.
EFI_DEVICE_ERROR An unexpected system error occurred. See ProgressErr for more data.
35.3.3 EFI_KEYWORD_HANDLER _PROTOCOL.GetData()
Summary
Get the data associated with a particular conﬁguration namespace keyword.
Prototype
typedef
(EFIAPI *EFI_KEYWORD_HANDLER _GET_DATA) (
IN CONST EFI_STRING NameSpaceId, OPTIONAL
IN CONST EFI_STRING KeywordString, OPTIONAL
OUT UINT32 *ProgressErr,
OUT EFI_STRING *Results
);
NamespaceId A null-terminated string containing the platform conﬁguration language to search through in the sys-
tem. If a NULL is passed in, then it is assumed that any platform conﬁguration language with the preﬁx of
“x-UEFI-” are searched.
KeywordString A null-terminated string in <MultiKeywordRequest> format. If a NULL is passed in the Keyword-
String ﬁeld, all of the known keywords in the system for the NameSpaceId speciﬁed are returned in the Results
ﬁeld.
ProgressErr If during the processing of the KeywordString there was a failure, this parameter gives additional infor-
mation about the possible source of the problem. See the deﬁnitions in SetData() for valid value deﬁnitions.
Results A null-terminated string in <MultiKeywordResp> format is returned which has all the values ﬁlled in for the
keywords in the KeywordString . This is a callee-allocated ﬁeld, and must be freed by the caller after being used.
35.3. EFI Conﬁguration Keyword Handler Protocol 1680Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function accepts a <MultiKeywordRequest> formatted string, ﬁnds the underlying keyword owners, creates a
<MultiConﬁgRequest> string from it and forwards it to the EFI_HII_ROUTING_PROTOCOL.ExtractConﬁg function.
If there is an issue in resolving the contents of the KeywordString, then the function returns an
EFI_INVALID_PARAMETER and also set the Progress andProgressErr with the appropriate information about where
the issue occurred and additional data about the nature of the issue.
In the case when KeywordString isNULL , or contains multiple keywords, or when EFI_NOT_FOUND is generated
while processing the keyword elements, the Results string contains values returned for all keywords processed prior to
the keyword generating the error but no values for the keyword with error or any following keywords.
EFI_INV ALID_PARAMETER One or more of the following are TRUE :Progress, ProgressErr, orResults
isNULL . Parsing of the KeywordString resulted in an error. See Progress
andProgressErr for more data.
data.
EFI_NOT_FOUND TheNamespaceId speciﬁed was not found. See ProgressErr for more data.
more data.
35.4 EFI HII Conﬁguration Routing Protocol
35.4.1 EFI_HII_CONFIG_ROUTING_PROTOCOL
Summary
The EFI HII Conﬁguration Routing Protocol manages the movement of conﬁguration data from drivers to conﬁgura-
tion applications. It then serves as the single point to receive conﬁguration information from conﬁguration applications,
routing the results to the appropriate drivers.
GUID
#define EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID \
{ 0x587e72d7, 0xcc50, 0x4f79,\
{ 0x82, 0x09, 0xca, 0x29, 0x1f, 0xc1, 0xa1, 0x0f }}
EFI_HII_EXTRACT_CONFIG ExtractConfig;
EFI_HII_EXPORT_CONFIG ExportConfig
EFI_HII_ROUTE_CONFIG RouteConfig;
EFI_HII_BLOCK_TO_CONFIG BlockToConfig;
EFI_HII_CONFIG_TO_BLOCK ConfigToBlock;
EFI_HII_GET_ALT_CFG GetAltConfig;
} EFI_HII_CONFIG_ROUTING_PROTOCOL;
None
35.4. EFI HII Conﬁguration Routing Protocol 1681Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This protocol deﬁnes the conﬁguration routing interfaces between external applications and the HII.
There may only be one instance of this protocol in the system.
35.4.2 EFI_HII_CONFIG_ROUTING_PROTOCOL.ExtractConﬁg()
Summary
This function allows a caller to extract the current conﬁguration for one or more named elements from one or more
drivers.
Prototype
typedef
(EFIAPI *EFI_HII_EXTRACT_CONFIG ) (
IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,
IN CONST EFI_STRING Request,
);
This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance.
Request A null-terminated string in <MultiConﬁgRequest> format.
Progress On return, points to a character in the Request string. Points to the string’s null terminator if request was
successful. Points to the most recent ‘&’ before the ﬁrst failing name / value pair (or the beginning of the string
if the failure is in the ﬁrst name / value pair) if the request was not successful
Results A null-terminated string in <MultiConﬁgAltResp> format which has all values ﬁlled in for the names in the
Request string.
This function allows the caller to request the current conﬁguration for one or more named elements from one or more
drivers. The resulting string is in the standard HII conﬁguration string format. If Successful Results contains an
equivalent string with “=” and the values associated with all names added in.
The expected implementation is for each <ConﬁgRequest> substring in the Request, call the HII Conﬁguration Access
Protocol ExtractConﬁg function for the driver corresponding to the <ConﬁgHdr> at the start of the <ConﬁgRequest>
substring. The request fails if no driver matches the <ConﬁgRequest> substring.
NOTE :Alternative conﬁguration strings may also be appended to the end of the current conﬁguration string. If they
are, they must appear after the current conﬁguration. They must contain the same routing (GUID, NAME, PATH) as the
current conﬁguration string. They must have an additional description indicating the type of alternative conﬁguration
the string represents , “ALTCFG=<AltCfgId>”. The<AltCfgId> is a reference to a Default ID which stipulates the
type of Default being referenced such as EFI_HII_DEFAULT_CLASS_STANDARD.
As an example, assume that the Request string is:
GUID=...&PATH=...&Fred&George&Ron&Neville
A result might be:
35.4. EFI HII Conﬁguration Routing Protocol 1682Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GUID=...&PATH=...&Fred=16&George=16&Ron=12&Neville=11&
GUID=...&PATH=...&ALTCFG=0037&Fred=12&Neville=7
NOTE :For the output Results, the value ﬁlled in the names in the Request string with <MultiConﬁgAltResp> format
may change when called multiple times due to some data being of a dynamic nature .
EFI_SUCCESS The Results string is ﬁlled with the values corresponding to all requested
names.
EFI_OUT_OF_RESOURCES Not enough memory to store the parts of the results that must be stored
awaiting possible future protocols.
EFI_NOT_FOUND Routing data doesn’t match any known driver. Progress set to the “G” in
“GUID” of the routing header that doesn’t match. Note: There is no re-
quirement that all routing data be validated before any conﬁguration extrac-
tion.
EFI_INV ALID_PARAMETER Illegal syntax. Progress set to most recent “&” before the error or the be-
ginning of the string.
EFI_INV ALID_PARAMETER The ExtractConﬁg function of the underlying HII Conﬁguration Access
Protocol returned EFI_INV ALID_PARAMETER. Progress set to most re-

names.
tion.
cent “&” before the error or the beginning of the string.
EFI_ACCESS_DENIED The action violated a system policy.
35.4.3 EFI_HII_CONFIG_ROUTING_PROTOCOL.ExportConﬁg()
Summary
This function allows the caller to request the current conﬁguration for the entirety of the current HII database and
returns the data in a null-terminated string.
Prototype
typedef
(EFIAPI *EFI_HII_EXPORT_CONFIG ) (
);
Results A null-terminated string in <MultiConﬁgAltResp> format which has all values ﬁlled in for the entirety of the
current HII database.
This function allows the caller to request the current conﬁguration for all of the current HII database. The results
include both the current and alternate conﬁgurations as described in ExtractConﬁg() above.
EFI_HII_CONFIG_ACCESS_PROTOCOL.ExtractConﬁg() interfaces below.
35.4. EFI HII Conﬁguration Routing Protocol 1683Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
names.
EFI_INV ALID_PARAMETER For example, passing in a NULL for the Results parameter would result in
this type of error.
35.4.4 EFI_HII_CONFIG_ROUTING_PROTOCOL.RouteConﬁg()
Summary
This function processes the results of processing forms and routes it to the appropriate handlers or storage.
Prototype
typedef
(EFIAPI *EFI_HII_ROUTE_CONFIG ) (
IN CONST EFI_STRING Configuration,
OUT EFI_STRING *Progress
);
Conﬁguration A null-terminated string in <MultiConﬁgResp> format.
Progress A pointer to a string ﬁlled in with the offset of the most recent ‘&’ before the ﬁrst failing name / value pair
(or the beginning of the string if the failure is in the ﬁrst name / value pair) or the terminating NULL if all was
successful.
This function routes the results of processing forms to the appropriate targets. It scans for <ConﬁgHdr> within the
string and passes the header and subsequent body to the driver whose location is described in the <ConﬁgHdr> . Many
<ConﬁgHdr> s may appear as a single request.
The expected implementation is to hand off the various <ConﬁgResp> substrings to the Conﬁguration Access Protocol
RouteConﬁg routine corresponding to the driver whose routing information is deﬁned by the <ConﬁgHdr> in turn.
EFI_SUCCESS The results have been distributed or are awaiting distribution.
EFI_INV ALID_PARAMETERS Passing in a NULL for the Conﬁguration parameter would result in this
type of error.
EFI_NOT_FOUND Target for the speciﬁed routing data was not found
35.4. EFI HII Conﬁguration Routing Protocol 1684Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
35.4.5 EFI_HII_CONFIG_ROUTING_PROTOCOL.BlockToConﬁg()
Summary
This helper function is to be called by drivers to map conﬁguration data stored in byte array (“block”) formats such as
UEFI Variables into current conﬁguration strings.
Prototype
typedef
(EFIAPI *EFI_HII_BLOCK_TO_CONFIG ) (
IN CONST EFI_STRING ConfigRequest,
IN CONST UINT8 *Block,
IN CONST UINTN BlockSize,
OUT EFI_STRING *Config,
);
ConﬁgRequest A null-terminated string in <ConﬁgRequest> format.
Block Array of bytes deﬁning the block’s conﬁguration.
BlockSize Length in bytes of Block .
Conﬁg Filled-in conﬁguration string. String allocated by the function. Returned only if call is successful. The
null-terminated string will be in <ConﬁgResp> format
This function extracts the current conﬁguration from a block of bytes. To do so, it requires that the ConﬁgRequest
string consists of a list of <BlockName> formatted names. It uses the offset in the name to determine the index into
the Block to start the extraction and the width of each name to determine the number of bytes to extract. These are
mapped to a string using the equivalent of the C “%x” format (with optional leading spaces).
The call fails if, for any (offset, width) pair in ConﬁgRequest, offset+value >= BlockSize .
EFI_SUCCESS The request succeeded. Progress points to the null terminator at the end of
theConﬁgRequest string.
EFI_OUT_OF_RESOURCES Not enough memory to allocate Conﬁg . Progress points to the ﬁrst character
ofConﬁgRequest .
EFI_INV ALID_PARAMETERS Passing in a NULL for the ConﬁgRequest orBlock parameter would result
in this type of error. Progress points to the ﬁrst character of ConﬁgRequest .
EFI_NOT_FOUND Target for the speciﬁed routing data was not found. Progress points to the
“G” in “GUID” of the errant routing data.
EFI_DEVICE_ERROR Block not large enough. Progress undeﬁned.
EFI_INV ALID_PARAMETER Encountered non <BlockName> formatted string. Block is left updated and
Progress points at the ‘&’ preceding the ﬁrst non-<BlockName>.
35.4. EFI HII Conﬁguration Routing Protocol 1685Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
35.4.6 EFI_HII_CONFIG_ROUTING_PROTOCOL.ConﬁgToBlock()
Summary
This helper function is to be called by drivers to map conﬁguration strings to conﬁgurations stored in byte array
(“block”) formats such as UEFI Variables.
Prototype
typedef
(EFIAPI *EFI_HII_CONFIG_TO_BLOCK ) (
IN CONST EFI_STRING *ConfigResp,
IN OUT CONST UINT8 *Block,
IN OUT UINTN *BlockSize,
);
ConﬁgResp A null-terminated string in <ConﬁgResp> format.
Block A possibly null array of bytes representing the current block. Only bytes referenced in the ConﬁgResp string in
the block are modiﬁed. If this parameter is null or if the * BlockSize parameter is (on input) shorter than required
by the Conﬁguration string, only the BlockSize parameter is updated and an appropriate status (see below) is
returned.
BlockSize The length of the Block in units of UINT8. On input, this is the size of the Block . On output, if successful,
contains the largest index of the modiﬁed byte in the Block, or the required buffer size if the Block is not large
enough.
Progress On return, points to an element of the ConﬁgResp string ﬁlled in with the offset of the most recent ‘&’
before the ﬁrst failing name / value pair (or the beginning of the string if the failure is in the ﬁrst name / value
pair) or the terminating NULL if all was successful.
This function maps a conﬁguration containing a series of <BlockConﬁg> formatted name value pairs in ConﬁgResp
into a Block so it may be stored in a linear mapped storage such as a UEFI Variable. If present, the function skips
GUID, NAME, andPATH in < ConﬁgResp> . It stops when it ﬁnds a non- <BlockConﬁg> name / value pair (after
skipping the routing header) or when it reaches the end of the string.
Example
Assume an existing block containing:
00 01 02 03 04 05
And the ConﬁgResp string is:
OFFSET=3WIDTH=1&VALUE=7&OFFSET=0&WIDTH=2&VALUE=AA55
The results are
55 AA 02 07 04 05
35.4. EFI HII Conﬁguration Routing Protocol 1686Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
theConﬁgResp string.
ofConﬁgResp .
EFI_INV ALID_PARAMETER Passing in a NULL for the ConﬁgResp orBlock parameter would result in
this type of error. Progress points to the ﬁrst character of ConﬁgResp .
EFI_BUFFER_TOO_SMALL Block not large enough. Progress undeﬁned. BlockSize is updated with the
required buffer size.
EFI_INV ALID_PARAMETER Encountered non <BlockName> formatted name / value pair. Block
is left updated and Progress points at the ‘&’ preceding the ﬁrst non-
<BlockName>.
35.4.7 EFI_HII_CONFIG_ROUTING_PROTOCOL.GetAltCfg()
Summary
This helper function is to be called by drivers to extract portions of a larger conﬁguration string.
Prototype
typedef

Summary
Prototype
typedef
(EFIAPI *EFI_HII_GET_ALT_CFG ) (
IN CONST EFI_STRING ConfigResp,
IN CONST EFI_GUID *Guid,
IN CONST EFI_STRING Name,
IN CONST EFI_STRING AltCfgId,
OUT EFI_STRING *AltCfgResp
);
ConﬁgResp A null-terminated string in <ConﬁgAltResp> format.
Guid A pointer to the GUID value to search for in the routing portion of the ConﬁgResp string when retrieving the
requested data. If Guid is NULL, then all GUID values will be searched for.
Name A pointer to the NAME value to search for in the routing portion of the ConﬁgResp string when retrieving the
requested data. If Name is NULL, then all Name values will be searched for.
DevicePath A pointer to the PATH value to search for in the routing portion of the ConﬁgResp string when retrieving
the requested data. If DevicePath isNULL , then all DevicePath values will be searched for.
AltCfgId A pointer to the ALTCFG value to search for in the routing portion of the ConﬁgResp string when retrieving
the requested data. If this parameter is NULL , then the current setting will be retrieved.
AltCfgResp A pointer to a buffer which will be allocated by the function which contains the retrieved string as
requested. This buffer is only allocated if the call was successful. The null-terminated string will be in <Conﬁ-
gResp> format.
35.4. EFI HII Conﬁguration Routing Protocol 1687Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function retrieves the requested portion of the conﬁguration string from a larger conﬁguration string. This function
will use the Guid, Name, andDevicePath parameters to ﬁnd the appropriate section of the ConﬁgResp string. Upon
ﬁnding this portion of the string, it will use the AltCfgId parameter to ﬁnd the appropriate instance of data in the
ConﬁgResp string. Once found, the found data will be copied to a buffer which is allocated by the function so that it
can be returned to the caller. The caller is responsible for freeing this allocated buffer.
EFI_SUCCESS The request succeeded. The requested data was extracted and placed in the
newly allocated AltCfgResp buffer.
EFI_OUT_OF_RESOURCES Not enough memory to allocate AltCfgResp .
EFI_INV ALID_PARAMETER Passing in a NULL for the ConﬁgResp orAltCfgResp would result in this
35.5 EFI HII Conﬁguration Access Protocol
35.5.1 EFI_HII_CONFIG_ACCESS_PROTOCOL
Summary
The EFI HII conﬁguration routing protocol invokes this type of protocol when it needs to forward requests to a
driver’s conﬁguration handler. This protocol is published by drivers providing and receiving conﬁguration data from
HII. The ExtractConﬁg() andRouteConﬁg() functions are typically invoked by the driver which implements the HII
Conﬁguration Routing Protocol. The Callback() function is typically invoked by the Forms Browser.
If the protocol functions modify active form set, they must not change layout and size of the existing variable stores.
The forms browser processes updated IFR package in accordance with the following rules:
1. If active form set no longer exists, the behavior is browser speciﬁc. The browser identiﬁes form set using a
combination of the form set GUID and device path associated with the package list containing the form set.
2. If form set update has been initiated by the Callback() function, the browser executes action requested by
the function. See EFI_HII_CONFIG_ACCESS_PROTOCOL.CallBack() section for additional details regarding
browser action requests.
NOTE :If browser action implies saving of the modiﬁed questions values, the browser will use uncommitted data
associated with the old form set instance. The HII Conﬁguration Access implementation is responsible for properly
handling such requests.
3. The browser performs standard processing steps that are performed on a form set prior to display-
ing it (including reading question values and generating EFI_BROWSER_ACTION_FORM_OPEN and
EFI_BROWSER_ACTION_FORM_RETRIEVE callbacks).
4. If there is an uncommitted browser data associated with an active form set, the browser applies it, matching
variable stores by their identiﬁers. If variable store no longer exists, the uncommitted data for this store is
discarded.
NOTE :Changing layout or size of the existing variable stores during form set update is not allowed and can lead to
unpredictable results.
5. The browser applies prior browsing history, matching forms by their identiﬁers. If a form saved in the browsing
history no longer exists, the behavior is browser-speciﬁc.
6. If all forms in the browsing history have been matched, the browser sets selection on a question that was active
prior to the form set update, matching question by its identiﬁer. If question does not exist, the ﬁrst question on
the form is selected.
35.5. EFI HII Conﬁguration Access Protocol 1688Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GUID
#define EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID \
{ 0x330d4706, 0xf2a0, 0x4e4f,\
{0xa3,0x69, 0xb6, 0x6f,0xa8, 0xd5, 0x43, 0x85}}
EFI_HII_ACCESS_EXTRACT_CONFIG ExtractConfig;
EFI_HII_ACCESS_ROUTE_CONFIG RouteConfig;
EFI_HII_ACCESS_FORM_CALLBACK Callback;
} EFI_HII_CONFIG_ACCESS_PROTOCOL;
None
ExtractConﬁg This function breaks apart the request strings routing them to the appropriate drivers. This function is
analogous to the similarly named function in the HII Routing Protocol.
RouteConﬁg This function breaks apart the results strings and returns conﬁguration information as speciﬁed by the
request.
Callback This function is called from the conﬁguration browser to communicate certain activities that were initiated
by a user.
This protocol provides a callable interface between the HII and drivers. Only drivers which provide IFR data to HII
are required to publish this protocol.
35.5.2 EFI_HII_CONFIG_ACCESS_PROTOCOL.ExtractConﬁg()
Summary
This function allows a caller to extract the current conﬁguration for one or more named elements from the target driver.
Prototype
typedef
(EFIAPI *EFI_HII_ACCESS_EXTRACT_CONFIG ) (
IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
);
This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL .
Request A null-terminated string in <ConﬁgRequest> format. Note that this includes the routing information as well
as the conﬁgurable name / value pairs. It is invalid for this string to be in <MultiConﬁgRequest> format.
If aNULL is passed in for the Request ﬁeld, all of the settings being abstracted by this function will be returned
in the Results ﬁeld. In addition, if a ConﬁgHdr is passed in with no request elements, all of the settings being
abstracted for that particular ConﬁgHdr reference will be returned in the Results Field.
35.5. EFI HII Conﬁguration Access Protocol 1689Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Request string. String to be allocated by the called function.
This function allows the caller to request the current conﬁguration for one or more named elements. The resulting
string is in <ConﬁgAltResp> format.
In order to support forms processors other than a Forms Browser, the conﬁguration returned by this function must not
depend on context in which the function is used. In particular, it must not depend on the current state of the Forms
Browser (including any uncommitted state information) and actions performed by the driver callbacks invoked prior
to the ExtractConﬁg call. See:numref: Connected-forms-browser-processor for more details.
Any and all alternative conﬁguration strings shall also be appended to the end of the current conﬁguration string.
If they are, they must appear after the current conﬁguration. They must contain the same routing (GUID, NAME,
PATH) as the current conﬁguration string. They must have an additional description indicating the type of alternative
conﬁguration the string represents, ” ALTCFG=<AltCfgId> “. The <AltCfgId> is a reference to a Default ID which
stipulates the type of Default being referenced such as EFI_HII_DEFAULT_CLASS_STANDARD .
GUID=...&PATH=...&Fred=16&George=16&Ron=12&Neville=11&GUID=...&PATH=...&ALTCFG=0037&
Fred=12&Neville=7

NOTE :For the output Results, the value ﬁlled in the names in the Request string with <ConﬁgAltResp> format may
change when called multiple times due to some data being of a dynamic nature.
names.
35.5. EFI HII Conﬁguration Access Protocol 1690Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 35.9 – continued from previous page
EFI_NOT_FOUND A conﬁguration element matching the routing data is not found. Progress
set to the ﬁrst character in the routing header.
EFI_INV ALID_PARAMETER Unknown name. Progress points to the “&” before the name in question.
EFI_INV ALID_PARAMETER If Results or Progress is NULL .
EFI_DEVICE_ERROR Failed to extract the current conﬁguration for one or more named elements.
35.5.3 EFI_HII_CONFIG_ACCESS_PROTOCOL.RouteConﬁg()
Summary
This function processes the results of changes in conﬁguration for the driver that published this protocol.
Prototype
typedef
(EFIAPI *EFI_HII_ACCESS_ROUTE_CONFIG ) (
);
Conﬁguration A null-terminated string in <ConﬁgResp> format.
This function applies changes in a driver’s conﬁguration. Input is a Conﬁguration, which has the routing data for this
driver followed by name / value conﬁguration pairs. The driver must apply those pairs to its conﬁgurable storage.
In order to support forms processors other than a Forms Browser, the way in which conﬁguration data is applied
must not depend on context in which the function is used. In particular, it must not depend on the current state
of the Forms Browser (including any uncommitted state information) and actions performed by the driver callbacks
invoked prior to the RouteConﬁg call. Connected Forms Browser/Processor provides additional details regarding
forms browser/processor.
If the driver’s conﬁguration is stored in a linear block of data and the driver’s name / value pairs are in <BlockConﬁg>
format, it may use the ConﬁgToBlock helper function (above) to simplify the job.
35.5. EFI HII Conﬁguration Access Protocol 1691Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 35.10 – continued from previous page
EFI_INV ALID_PARAMETER If Conﬁguration or Progress is NULL.
35.5.4 EFI_HII_CONFIG_ACCESS_PROTOCOL.CallBack()
Summary
This function is called to provide results data to the driver.
Prototype
typedef
(EFIAPI *EFI_HII_ACCESS_FORM_CALLBACK) (
IN EFI_BROWSER_ACTION Action,
IN EFI_QUESTION_ID QuestionId,
IN UINT8 Type
IN OUT EFI_IFR_TYPE_VALUE *Value,
OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest,
);
Action Speciﬁes the type of action taken by the browser. See EFI_BROWSER_ACTION_x in “Related Deﬁnitions”
below.
QuestionId A unique value which is sent to the original exporting driver so that it can identify the type of data to
expect. The format of the data tends to vary based on the opcode that generated the callback.
Type The type of value for the question. See EFI_IFR_TYPE_x inEFI_IFR_ONE_OF_OPTION .
Value A pointer to the data being sent to the original exporting driver. The type is speciﬁed by Type. Type
EFI_IFR_TYPE_VALUE is deﬁned in EFI_IFR_ONE_OF_OPTION.
ActionRequest On return, points to the action requested by the callback function. Type
EFI_BROWSER_ACTION_REQUEST is speciﬁed in SendForm() in the Form Browser Protocol.
This function is called by the forms browser in response to a user action on a question which has the
EFI_IFR_FLAG_CALLBACK bit set in the EFI_IFR_QUESTION_HEADER . The user action is speciﬁed by Action .
Depending on the action, the browser may also pass the question value using Type andValue . Upon return, the callback
function may specify the desired browser action.
The browser maintains uncommitted browser data (modiﬁed and unsaved question values) across Callback function
boundaries. Callback function may change unsaved question values using one of the following methods:
• Current question’s value may be changed by updating the Value parameter.
• Values of other questions from the active formset can be changed using
EFI_FORM_BROWSER2_PROTOCOL.BrowserCallback() interface.
NOTE :Modiﬁcation of the question values by the Callback function without notifying the browser using one of the
above mentioned methods can lead to unpredictable browser behavior.
Callback function may request conﬁguration update from the browser by returning an appropriate ActionRequest .
35.5. EFI HII Conﬁguration Access Protocol 1692Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
In order to save uncommitted data, driver should return one of the _SUBMIT actions or _APPLY action. The browser
will then write all modiﬁed question values (in case of the _SUBMIT actions) or modiﬁed question values from an
active form (in case of the _APPLY action) to storage using RouteConﬁg() function. This will include questions
modiﬁed prior to an invocation of the Callback() function as well as questions modiﬁed by the Callback() function.
The behavior of the ExtractConﬁg andRouteConﬁg functions must not depend on the actions performed by this
function.
Callback functions should return EFI_UNSUPPORTED for all values of Action that they do not support.
typedef UINTN EFI_BROWSER_ACTION;
#define EFI_BROWSER_ACTION_CHANGING 0
#define EFI_BROWSER_ACTION_CHANGED 1
#define EFI_BROWSER_ACTION_RETRIEVE 2
#define EFI_BROWSER_ACTION_FORM_OPEN 3
#define EFI_BROWSER_ACTION_FORM_CLOSE 4
#define EFI_BROWSER_ACTION_SUBMITTED 5
#define EFI_BROWSER_ACTION_DEFAULT_STANDARD 0x1000
#define EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING 0x1001
#define EFI_BROWSER_ACTION_DEFAULT_SAFE 0x1002
#define EFI_BROWSER_ACTION_DEFAULT_PLATFORM 0x2000
#define EFI_BROWSER_ACTION_DEFAULT_HARDWARE 0x3000
#define EFI_BROWSER_ACTION_DEFAULT_FIRMWARE 0x4000
The following table describes the behavior of the callback for each question type.
Table 35.11: Callback Behavior
Question Type Type Action
Action Button EFI_IFR_TYPE_ACTION No special behavior. If the short form of the opcode is
used, then the value will be a string identiﬁer of zero.
Checkbox EFI_IFR_TYPE_BOOLEAN No special behavior
Cross-
Reference EFI_IFR_TYPE_REF
EF I_IFR_TYPE_UNDEFINEDCHANGING: If EFI_UNSUPPORTED or
EFI_SUCCESS, the updated cross-reference is taken.
Any other error the cross-reference will not be taken.
CHANGED: Never called.
RETRIEVE: Called before displaying the
cross-reference. Error codes ignored. The Ref ﬁeld of
the Value parameter is initialized with the REF
question’s value prior to CHANGING and RETRIEVE.
Date EFI_IFR_TYPE_DATE No special behavior
Numeric,
One-OfEFI _IFR_TYPE_NUM_SIZE_8 ,
EFI_ IFR_TYPE_NUM_SIZE_16 ,
EFI_ IFR_TYPE_NUM_SIZE_32 ,
EFI_ IFR_TYPE_NUM_SIZE_64No special behavior.
Ordered-List EFI_IFR_TYPE_BUFFER No special behavior
String, Pass-
wordEFI_IFR_TYPE_STRING No special behavior.

Cross-
Numeric,
35.5. EFI HII Conﬁguration Access Protocol 1693Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 35.11 – continued from previous page
Time EFI_IFR_TYPE_DATE No special behavior.
The value EFI_BROWSER_ACTION_CHANGING is called before the browser changes the value in the display (for
questions which have a value) or takes an action (in the case of an action button or cross-reference). If the callback
returns EFI_UNSUPPORTED, then the browser will use the value passed to Callback() and ignore the value returned
byCallback() . If the callback returns EFI_SUCCESS, then the browser will use the value returned by Callback() . If
any other error is returned, then the browser will not update the current question value. ActionRequest is used. The
Value represents the updated value. The changes here should not be ﬁnalized until the user submits the results.
The value EFI_BROWSER_ACTION_CHANGED is called after the browser has changed its internal copy of the ques-
tion value and displayed it (if appropriate). For action buttons, this is called after the value has been processed. For
cross-references, this is never called. Errors returned are ignored. ActionRequest is used. The changes here should not
be ﬁnalized until the user submits the results.
The value EFI_BROWSER_ACTION_RETRIEVE is called after the browser has read the current question value, but
before it has been displayed. If the callback returns EFI_UNSUPPORTED or any other error then the original value is
used. If EFI_SUCCESS is returned, then the updated value is used.
The value EFI_BROWSER_ACTION_FORM_OPEN is called for each question on a form prior to its value
being retrieved or displayed. If a question appears on more than one form, and the Forms Browser sup-
ports more than one form being active simultaneously, this may be called more than once, even prior to any
EFI_BROWSER_ACTION_FORM_CLOSE callback.
NOTE : EFI_FORM_BROWSER2_PROTOCOL.BrowserCallback() cannot be used with this browser action because
question values have not been retrieved yet .
The value EFI_BROWSER_ACTION_FORM_CLOSE is called for each question on a form after the processing of any
submit actions for that form. If a question appears on more than one form, and the Forms Processor supports more
than one form being active simultaneously, this will be called more than once.
The value EFI_BROWSER_ACTION_SUBMITTED is called after Browser submits the modiﬁed question value. Ac-
tionRequest is ignored.
When Action speciﬁes one of the “default” actions, such as EFI_BROWSER_ACTION_DEFAULT_STANDARD, etc. it
indicates that the Forms Processor is attempting to retrieve the default value for the speciﬁed question. The proposed
default value is passed in using Type andValue and reﬂects the value which the Forms Processor was able to select
based on the lower-priority defaulting methods (see Defaults ). If the function returns EFI_SUCCESS, then the updated
value will be used. If the function does not have an updated default value for the speciﬁed question or speciﬁed default
store, or does not provide any support for the actions, it should return EFI_UNSUPPORTED, and the returned value
The DEFAULT_PLATFORM, DEFAULT_HARDWARE and DEFAULT_FIRMWARE represent ranges of 4096
(0x1000) possible default store identiﬁers. The DEFAULT_STANDARD represents the range of 4096 possible action
values reserved for UEFI-deﬁned default store identiﬁers. See Defaults for more information on defaults.
typedef UINTN EFI_BROWSER_ACTION_REQUEST;
#define EFI_BROWSER_ACTION_REQUEST_NONE 0
#define EFI_BROWSER_ACTION_REQUEST_RESET 1
#define EFI_BROWSER_ACTION_REQUEST_SUBMIT 2
#define EFI_BROWSER_ACTION_REQUEST_EXIT 3
#define EFI_BROWSER_ACTION_REQUEST_FORM_SUBMIT_EXIT 4
#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD_EXIT 5
#define EFI_BROWSER_ACTION_REQUEST_FORM_APPLY 6
#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD 7
#define EFI_BROWSER_ACTION_REQUEST_RECONNECT 8
#define EFI_BROWSER_ACTION_REQUEST_QUESTION_APPLY 9
35.5. EFI HII Conﬁguration Access Protocol 1694Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If the callback function returns with the ActionRequest set to _NONE, then the Forms Browser will take no special
behavior.
If the callback function returns with the ActionRequest set to _RESET, then the Forms Browser will exit and request
the platform to reset.
If the callback function returns with the ActionRequest set to _SUBMIT, then the Forms Browser will save all modiﬁed
question values to storage and exit.
If the callback function returns with the ActionRequest et to _EXIT, then the Forms Browser will discard all modiﬁed
question values and exit.
If the callback function returns with the ActionRequest set to _FORM_SUBMIT_EXIT, then the Forms Browser will
write all modiﬁed question values on the selected form to storage and then exit the selected form.
If the callback function returns with the ActionRequest set to _FORM_DISCARD_EXIT, then the Forms Browser will
discard the modiﬁed question values on the selected form and then exit the selected form.
If the callback function returns with the ActionRequest set to _FORM_APPLY , then the Forms Browser will write all
modiﬁed current question values on the selected form to storage.
If the callback function returns with the ActionRequest set to _FORM_DISCARD, then the Forms Browser will discard
the current question values on the selected form and replace them with the original question values.
If the callback function returns with the ActionRequest set to _RECONNECT, a hardware and/or software con-
ﬁguration change was performed by the user, and the controller needs to be reconnected for the driver to recog-
nize the change. Upon the user exiting the formset or the browser, the Forms Browser is required to call the EFI
Boot Service DisconnectController() followed by the EFI Boot Service ConnectController() to reconnect the con-
troller. The controller handle passed to DisconnectController() andConnectController() is the handle on which this
EFI_HII_CONFIG_ACCESS_PROTOCOL is installed.
If the callback function returns with the ActionRequest set to _QUESTION_APPLY , then the Forms Browser will write
the current modiﬁed question value on the selected form to storage.
EFI_SUCCESS The callback successfully handled the action.
EFI_DEVICE_ERROR The variable could not be saved.
EFI_UNSUPPORTED The speciﬁed Action is not supported by the callback.
35.6 Form Browser Protocol
TheEFI_FORM_BROWSER2_PROTOCOL is the interface to call for drivers to leverage the EFI conﬁguration driver
35.6.1 EFI_FORM_BROWSER2_PROTOCOL
Summary
TheEFI_FORM_BROWSER2_PROTOCOL is the interface to the UEFI conﬁguration driver. This interface will allow
the caller to direct the conﬁguration driver to use either the HII database or use the passed-in packet of data.
GUID
35.6. Form Browser Protocol 1695Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_FORM_BROWSER2_PROTOCOL_GUID \
{ 0xb9d4c360, 0xbcfb, 0x4f9b, \
{ 0x92, 0x98, 0x53, 0xc1, 0x36, 0x98, 0x22, 0x58 } }
typedef struct _EFI_FORM_BROWSER2_PROTOCOL {
EFI_SEND_FORM2 SendForm;
EFI_BROWSER_CALLBACK2 BrowserCallback;
} EFI_FORM_BROWSER2_PROTOCOL;
SendForm Browse the speciﬁed conﬁguration forms. See the SendForm() function description.
BrowserCallback Routine used to expose internal conﬁguration state of the browser. This is primarily used by
callback handler routines which were called by the browser and in-turn need to get additional information from
the browser itself. See the BrowserCallback() function description.
This protocol is the interface to call for drivers to leverage the EFI conﬁguration driver interface.
35.6.2 EFI_FORM_BROWSER2_PROTOCOL.SendForm()
Summary
Initialize the browser to display the speciﬁed conﬁguration forms.
Prototype
typedef
(EFIAPI *EFI_SEND_FORM2) (
IN CONST EFI_FORM_BROWSER2_PROTOCOL *This,
IN EFI_HII_HANDLE *Handles,
IN UINTN HandleCount,
IN CONST EFI_GUID *FormsetGuid, OPTIONAL
IN EFI_FORM_ID FormId, OPTIONAL
IN CONST EFI_SCREEN_DESCRIPTOR *ScreenDimensions, OPTIONAL
OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest OPTIONAL
);
This A pointer to the EFI_FORM_BROWSER2_PROTOCOL instance.
Handles A pointer to an array of HII handles to display. This value should correspond to the value
of the HII form package that is required to be displayed. Type EFI_HII_HANDLE is deﬁned in
EFI_HII_DATABASE_PROTOCOL.NewPackageList() inPackage Lists and Package Headers .
HandleCount The number of handles in the array speciﬁed by Handle .
FormsetGuid This ﬁeld points to the EFI_GUID which must match the Guid ﬁeld or one of the elements of the
ClassId ﬁeld in the EFI_IFR_FORM_SET op-code. If FormsetGuid isNULL, then this function will display the
form set class EFI_HII_PLATFORM_SETUP_FORMSET_GUID .

);
FormId This ﬁeld speciﬁes the identiﬁer of the form within the form set to render as the ﬁrst displayable page. If this
ﬁeld has a value of 0x0000, then the Forms Browser will render the ﬁrst enabled form in the form set.
35.6. Form Browser Protocol 1696Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ScreenDimensions Points to recommended form dimensions, including any non-content area, in characters. Type
EFI_SCREEN_DESCRIPTOR is deﬁned in “Related Deﬁnitions” below.
ActionRequested Points to the action recommended by the form.
This function is the primary interface to the Forms Browser. The Forms Browser displays the forms speciﬁed by
FormsetGuid andFormId from all of HII handles speciﬁed by Handles . If more than one form can be displayed, the
Forms Browser will provide some means for the user to navigate between the forms in addition to that provided by
cross-references in the forms themselves.
If ScreenDimensions is non-NULL, then it points to a recommended display size for the form. If browsing in text
mode, then these are recommended character positions. If browsing in graphics mode, then these values are converted
to pixel locations using the standard font size (8 pixels per horizontal character cell and 19 pixels per vertical character
cell). If ScreenDimensions is NULL the browser may choose the size based on platform policy. The browser may
choose to ignore the size based on platform policy.
If ActionRequested is non-NULL, then upon return, it points to an enumerated value (see
EFI_BROWSER_ACTION_x in “Related Deﬁnitions” below) which describes the action requested by the
user. If set to EFI_BROWSER_ACTION_NONE, then no speciﬁc action was requested by the form. If set to
EFI_BROWSER_ACTION_RESET, then the form requested that the platform be reset. The browser may, based on
platform policy, ignore such action requests.
IfFormsetGuid is set to EFI_HII_PLATFORM_SETUP_FORMSET_GUID, it indicates that the form
set contains forms designed to be used for platform conﬁguration. If FormsetGuid is set to
EFI_HII_DRIVER_HEALTH_FORMSET_GUID, it indicates that the form set contains forms designed to be
used for support of the Driver Health Protocol ( EFI Driver Health Protocol ). If FormsetGuid is set to
EFI_HII_USER_CREDENTIAL_FORMSET_GUID, it indicates that the form set contains forms designed to
be used for support of the User Credential Protocol ( Credential Provider Protocols ) IfFormsetGuid is set to
EFI_HII_REST_STYLE_FORMSET_GUID, it indicates that the form set contains forms designed to be used for
support conﬁguration of REST architectural style (see Section 29.7). Other values may be used for other applications.
// EFI_SCREEN_DESCRIPTOR
UINTN LeftColumn;
UINTN RightColumn;
UINTN TopRow;
UINTN BottomRow;
} EFI_SCREEN_DESCRIPTOR;
LeftColumn Value that designates the text column where the browser window will begin from the left-hand side of
the screen
RightColumn Value that designates the text column where the browser window will end on the right-hand side of the
screen.
TopRow Value that designates the text row from the top of the screen where the browser window will start.
BottomRow Value that designates the text row from the bottom of the screen where the browser window will end.
35.6. Form Browser Protocol 1697Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The value EFI_BROWSER_ACTION _REQUEST _NONE indicates that no speciﬁc caller action is required. The
value EFI_BROWSER_ACTION _REQUEST _RESET indicates that the caller requested a platform reset. The value
EFI_BROWSER_ACTION _REQUEST _SUBMIT indicates that a callback requested that the browser submit all values
and exit. The value EFI_BROWSER_ACTION _REQUEST _EXIT indicates that a callback requested that the browser
exit without saving all values.
#define EFI_HII_PLATFORM_SETUP_FORMSET_GUID \
{ 0x93039971, 0x8545, 0x4b04, \
{ 0xb4, 0x5e, 0x32, 0xeb, 0x83, 0x26, 0x04, 0x0e } }
#define EFI_HII_DRIVER_HEALTH_FORMSET_GUID \
{ 0xf22fc20c, 0x8cf4, 0x45eb, \
{ 0x8e, 0x06, 0xad, 0x4e, 0x50, 0xb9, 0x5d, 0xd3 } }
#define EFI_HII_USER_CREDENTIAL_FORMSET_GUID \
{ 0x337f4407, 0x5aee, 0x4b83, \
{ 0xb2, 0xa7, 0x4e, 0xad, 0xca, 0x30, 0x88, 0xcd } }
#define EFI_HII_REST_STYLE_FORMSET_GUID \
{ 0x790217bd, 0xbecf, 0x485b, \
{ 0x91, 0x70, 0x5f, 0xf7, 0x11, 0x31, 0x8b, 0x27 } }
EFI_SUCCESS The function completed successfully
EFI_NOT_FOUND No valid forms could be found to display.
35.6.3 EFI_FORM_BROWSER2_PROTOCOL.BrowserCallback()
Summary
This function is called by a callback handler to retrieve uncommitted state data from the browser.
Prototype
(EFIAPI *EFI_BROWSER_CALLBACK2 ) (
IN OUT UINTN *ResultsDataSize,
IN OUT EFI_STRING ResultsData,
IN BOOLEAN RetrieveData,
IN CONST EFI_GUID *VariableGuid, OPTIONAL
IN CONST CHAR16 *VariableName OPTIONAL
);
ResultsDataSize A pointer to the size of the buffer associated with ResultsData. On input, the size in bytes of
ResultsData . On output, the size of data returned in ResultsData .
35.6. Form Browser Protocol 1698Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ResultsData A string returned from an IFR browser or equivalent. The results string will have no routing information
in them.
RetrieveData A BOOLEAN ﬁeld which allows an agent to retrieve (if RetrieveData = TRUE ) data from the un-
committed browser state information or set (if RetrieveData = FALSE ) data in the uncommitted browser state
VariableGuid An optional ﬁeld to indicate the target variable GUID name to use.
VariableName An optional ﬁeld to indicate the target human-readable variable name.
This service is typically called by a driver’s callback routine which was in turn called by the browser. The routine
called this service in the browser to retrieve or set certain uncommitted state information that resides in the open
formsets.
EFI_BUFFER_TOO_SMALL TheResultsDataSize speciﬁed was too small to contain the results data.
EFI_UNSUPPORTED Uncommitted browser state is not available at the current stage of execution.
35.7 HII Popup Protocol
35.7.1 EFI_HII_POPUP_PROTOCOL
Summary
This protocol provides services to display a popup window.
The protocol is typically produced by the forms browser and consumed by a driver’s callback handler.
GUID
#define EFI_HII_POPUP_PROTOCOL_GUID \\
{ 0x4311edc0, 0x6054, 0x46d4, { 0x9e, 0x40, 0x89, 0x3e, 0xa9, 0x52, 0xfc, 0xcc
} }
EFI_HII_CREATE_POPUP CreatePopup;
} EFI_HII_POPUP_PROTOCOL;
Revision Protocol revision
CreatePopup Displays a popup window
#define *EFI_HII_POPUP_PROTOCOL_REVISION *1
35.7. HII Popup Protocol 1699Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
35.7.2 EFI_HII_POPUP_PROTOCOL.CreatePopup()
Summary
Displays a popup window.
Prototype
typedef
(EFIAPI *EFI_HII_CREATE_POPUP) (
IN EFI_HII_POPUP_PROTOCOL *This,
IN EFI_HII_POPUP_STYLE PopupStyle,
IN EFI_HII_POPUP_TYPE PopupType,
EFI_HII_HANDLE HiiHandle
IN EFI_STRING_ID Message,
OUT EFI_HII_POPUP_SELECTION *UserSelection OPTIONAL,
);
This A pointer to the EFI_HII_POPUP_PROTOCOL instance.
PopupStyle Popup style to use. EFI_HII_POPUP_STYLE is deﬁned in the “Related Deﬁnitions” below.
PopupType Type of the popup to display. EFI_HII_POPUP_TYPE is deﬁned in the “Related Deﬁnitions” below.
HiiHandle HII handle of the string pack containing Message
Message A message to display in the popup box.
UserSelection User selection. EFI_HII_POPUP_SELECTION is deﬁned in the “Related Deﬁnitions” below.
The CreatePopup() function displays a modal message box that contains string speciﬁed by Message . Explicit line
break characters can be used to specify a multi-line message ( Common Control Codes ). A popup window may contain
user selectable options. The option selected by a user is returned via an optional UserSelection parameter.
A list of options presented to a user is deﬁned by the PopupType .
The PopupStyle provides a hint to protocol implementation regarding nature of the message being displayed. The
function may optionally use PopupStyle to customize visual appearance of the message box.

EﬁHiiPopupTypeOk is a simple popup window with a single user selectable option that can be used to acknowledge
the message. If UserSelection is speciﬁed, it is set to EﬁHiiPopupSelectionOk.
EﬁHiiPopupTypeOkCancel is a popup window with two user selectable options: OK and Cancel.
EﬁHiiPopupTypeYesNo is a popup window with two user selectable options: Yes and No.
EﬁHiiPopupTypeYesNoCancel is a popup window with three user selectable options: Yes, No, and Cancel.
EfiHiiPopupStyleInfo,
EfiHiiPopupStyleWarning,
EfiHiiPopupStyleError
} EFI_HII_POPUP_STYLE;
EfiHiiPopupTypeOk,
EfiHiiPopupTypeOkCancel,
35.7. HII Popup Protocol 1700Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EfiHiiPopupTypeYesNo,
EfiHiiPopupTypeYesNoCancel
} EFI_HII_POPUP_TYPE;
EfiHiiPopupSelectionOk,
EfiHiiPopupSelectionCancel,
EfiHiiPopupSelectionYes,
EfiHiiPopupSelectionNo
} EFI_HII_POPUP_SELECTION;
EFI_SUCCESS The popup box was successfully displayed
EFI_INVALID_PARAMETER HiiHandle and Message do not deﬁne is a valid HII string.
EFI_INVALID_PARAMETER PopupType is not one of the values deﬁned by this speciﬁcation.
EFI_OUT_OF_RESOURCES There are not enough resources available to display the popup box.
35.7. HII Popup Protocol 1701CHAPTER
THIRTYSIX
USER IDENTIFICATION
36.1 User Identiﬁcation Overview
This section describes services which describe the current user of the platform. A user is the entity which is controlling
the behavior of the machine. The user may be an individual, a class or group of individuals or another machine.
Each user has a user proﬁle. There is always at least one user proﬁle for a machine. This proﬁle governs the behavior
of the user identiﬁcation process until a another user has been selected. The nature and deﬁnition of these privileges
are beyond the scope of this section. One user proﬁle is always active and describes the platform’s current user .
New user proﬁles are introduced into the system through enrollment. During enrollment, information about a new
user is gathered. Some of this information identiﬁes the user for speciﬁc purposes, such as a user’s name or a user’s
network domain. Other information is gathered in the form of credentials, which is information which can be used
at a later time to verify the identity of a user. Credentials are generally divided into three categories: something you
know (password), something you have (smart card, smart token, RFID), something you are (ﬁngerprint). The means
by which a platform determines the user’s identity based on credentials is user identiﬁcation .
In the simplest case, a single set of credentials are required to establish a user’s identity. This is called single-factor
authentication. In more rigorous cases, multiple credentials might be required to establish a user’s identity or different
privilege levels given if only a single factor is available. This is called multi-factor authentication.
If the credentials are checked only once, this is called static authentication. For example, a sign-on box where the user
enters a password and provides a ﬁngerprint would be examples of static authentication. However, if credentials (and
thus the user’s identity) can be changed during system execution, this is called dynamic authentication. For example,
a smart token which can be hot-removed from the system or an RFID tag which is moved in and out of range would
be examples of dynamic authentication.
The user identity manager is the optional UEFI driver which manages the process of determining the user’s identity
and storing information about the user.
The user enrollment manager is the optional application which adds or enrolls new users, gathering the necessary
information to ascertain their identity in the future.
Thecredential provider driver manages a single class of credentials. Examples include a USB ﬁngerprint sensor, a
smart card or a password. The means by which these drivers are selected and invoked is beyond the scope of this
1702Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.1.1 User Identify
The process of identifying the user occurs after platform initialization has made the services described in the EFI
System Table available. Before the Boot Manager behavior described in chapter 3, a user proﬁle must be established.
The user proﬁle established might be:
• A default user proﬁle, giving a standard set of privileges. This is similar to a “guest” login.
• A default user proﬁle, based on a User Credential Provider where Default() returns AutoLogon = TRUE .
• A speciﬁc user proﬁle, established using the Identify() function of the User Manager.
Every time the user proﬁle is modiﬁed, the User Identity Manager will signal the
EFI_EVENT_GROUP_USER_PROFILE_CHANGED event. The current user proﬁle can only be changed by
calling the User Identity Manager’s Identify() function or as the result of a credential provider calling the Notify()
function (when dynamic authentication is supported). The Identify() function changes the current user proﬁle after
examining the credentials provided by the various credential providers and comparing these against those found in the
user proﬁle database.
Fig. 36.1: User Identity
When the UEFI Boot Manager signals the EFI_EVENT_GROUP_READY_TO_BOOT event group, the User Identity
Manager publishes the current user proﬁle information in the EFI System Conﬁguration Table.
Depending on the security considerations in the implementation (see Security Considerations ), user identiﬁcation can
continue into different phases of execution.
1. Boot Manager, Once. In this scenario, identiﬁcation is permitted until the
EFI_EVENT_GROUP_READY_TO_BOOT is signaled by the Boot Manager. After this time, user
identiﬁcation is not allowed again. This is the simplest, since the user proﬁle database can be locked at this time
using a simple one-time lock.
2. Boot Manager, Multiple. In this scenario, identiﬁcation is permitted until the
EFI_EVENT_GROUP_READY_TO_BOOT is signaled by the Boot Manager. After this time, if the
boot option returns back into the Boot Manager, identiﬁcation is allowed again. This scenario requires that the
user proﬁle database only be updatable while in the Boot Manager.
36.1. User Identiﬁcation Overview 1703Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
3. Until ExitBootServices. In this scenario, identiﬁcation is permitted until the
EFI_EVENT_GROUP_EXIT_BOOT_SERVICES is signaled by the Boot Manager. This scenario requires that
the user proﬁle database cannot be updated by unauthorized executables.
36.1.2 User Proﬁles
The user proﬁles are collections of information about users. There is always a current user (and thus, a currently
selected user proﬁle). The user proﬁles are stored in a user proﬁle database.
Each user proﬁle has the following attributes:
§ User Identiﬁer
User identiﬁers are unique to a particular user proﬁle. The uniqueness of the user proﬁle identiﬁer must persist across
reboots. Credentials return this identiﬁer during the identiﬁcation process.
§ User Identiﬁcation Policy
The user identiﬁcation policy determines which credentials must be presented in order to establish the user’s identity
and set the user proﬁle as the current user proﬁle. The policy consists of a boolean expression consisting of credential
handles and the operators AND, OR and NOT. This allows the user proﬁle to be selected, for example, depending on a
password credential OR a ﬁngerprint credential. Or the proﬁle might be selected depending on a password credential
AND a ﬁngerprint credential.
§ User Privileges
The user privileges control what the user can and cannot do. For example, can the user enroll other users, boot off of
a selected device, etc.
§ User Information
User information consists of typed data records attached to the user proﬁle handle. Some of this information is non-
volatile. Some of this information may be provided by a speciﬁc credential driver. User information is classiﬁed as
public, private or protected:
• Public user information is available at any time.
• Private user information is only available while it is part of the current user proﬁle.
• Protected user information is only available once user has been authenticated by a credential provider.
Drivers and applications can be notiﬁed when the current user proﬁle is changed, by using the UEFI Boot Service
CreateEventEx() and the EFI_EVENT_GROUP_USER_PROFILE_CHANGED
User proﬁles are available while the User Identity Manager is running, but only the current user proﬁle is available
after the UEFI Boot Manager has started execution.
36.1.2.1 User Proﬁle Database
The user proﬁle database is a repository of all users known to the user identity manager. The user proﬁle database
should be maintained in non-volatile memory and this memory must be protected against corruption and erasure.

The user proﬁle database is considered “open” if the user proﬁle database can still be updated and the current proﬁle
can still be changed using the EFI User Manager Protocol. The user proﬁle database is considered “closed” if the user
proﬁle database cannot be updated nor the current user proﬁle changes using the EFI User Manager Protocol.
36.1. User Identiﬁcation Overview 1704Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.1.2.2 User Identiﬁcation Policy
The user identiﬁcation policy is a boolean expression which determines which class of credential or which credential
providers must assert the user’s identity in order to a user proﬁle to be eligible for selection as the current user proﬁle.
For example, assume that you want a password:
CredentialClass(Password)
This expression would assert TRUE if any credential provider asserts that a user has successfully entered a password.
CredentialClass(Password) && CredentialClass(Fingerprint)
This expression would require the user to present both a ﬁngerprint AND a password in order to select this user proﬁle.
CredentialClass(Password) || CredentialClass(Fingerprint)
This expression, on the other hand, allows the user to present a ﬁngerprint OR a password in order to select this user
proﬁle.
Let’s say you only want the Phoenix password provider:
CredentialClass(Password) && CredentialProvider(Phoenix)
In all of these cases, the class of credential and the provider of the credential are actually GUIDs. The standard
credential class GUIDs are assigned by this speciﬁcation. The credential provider identiﬁers are generated by the
companies creating the credential providers.
36.1.3 Credential Providers
The User Credential Provider drivers follow the UEFI driver model. During initialization, they install an instance of the
EFI Driver Binding Protocol. For hardware devices, the User Credential Provider may consume the bus I/O protocol
and produce the User Credential Protocol. For software-based User Credential Providers, the User Credential Protocol
could be installed on the image handler. The exact implementation depends on the number of separate credential types
that the User Identity Manager will display.
When Start() is called, they:
1. Install one instance of the EFI_USER_CREDENTIAL2_PROTOCOL for each simultaneous user which might be
authenticated. For example, if more than one smart token were inserted, then one instance might be created for
each token. However, for a ﬁngerprint sensor, one instance might be created for all ﬁngerprint sensors managed
by the same driver.
2. Install the user-interface forms used for interacting with the user using the HII Database Protocol. The form
must be encoded using the GUID EFI_USER_CREDENTIAL2_PROTOCOL_GUID .
3. Install the EFI HII Conﬁguration Access Protocol to handle interaction with the UEFI forms browser. This
protocol is called to retrieve the current information from the credential provider. It is also called when the user
presses OK to save the current form values. It also provides the callback functionality which allows real-time
processing of the form values.
User Credential Providers are responsible to creating a one-to-one mapping between a device, ﬁngerprint or password
and a user identiﬁer.
This speciﬁcation does not explicitly support passing of user credential information related to operating system logon
to an OS-present environment. For example, User Credential Providers may encrypt the user credential information
and pass it, either as a part of the User Information Table or the EFI System Conﬁguration Table, to an OS-present
driver or application.
36.1. User Identiﬁcation Overview 1705Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This speciﬁcation does not explicitly support OS-present update of user credential information or user identiﬁcation
policy. Such support may be implemented in many ways, including the usage of write-authenticated EFI variables (see
SetVariable() ) or capsules (see UpdateCapsule() ).
36.1.4 Security Considerations
Since the current proﬁle details a number of security-related privileges, it is important that the User Identity Manager
and User Credential Providers and the environment in which they execute are trusted.
This includes:
• Protecting the storage area where these drivers are stored
• Protecting the means by which these drivers are selected.
• Protecting the execution environment of these drivers from unveriﬁed drivers.
• The data structures used by these drivers should not be corrupted by unauthorized drivers while they are still
Fig. 36.2: User Identity Manager
In many cases, the User Identity Manager, the User Credential drivers and the on-board drivers are located in a
protected location (e.g. a write-protected ﬂash device) and the platform policy for these locations allows them to be
trusted.
However, other drivers may be loaded from unprotected location or may be loaded from devices (such as PCI cards)
or a hard drive which are easily replaced. Therefore, all drivers loaded prior to the User Identity Manager should be
veriﬁed. No unveriﬁed drivers or applications should be allowed to execute while decisions based on the current user
policy are still being made.
For example, either the default platform policy must successfully be able to verify drivers listed in the Driver#### load
options, or else the user must be identiﬁed prior to processing these drivers. Otherwise, the drivers’ execution should
be deferred. If the user proﬁle is changed through a subsequent call to Identify() or through dynamic authentication,
theDriver#### options may not be processed again.
In systems where the user proﬁle database and current user proﬁle can be protected from corruption, the user proﬁle
database is closed when the system signals the event EFI EXIT_BOOT_SERVICES_EVENT_GUID . In systems where
36.1. User Identiﬁcation Overview 1706Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
the user proﬁle database and current user proﬁle cannot be protected from corruption, the user proﬁle database is
closed when the system signals the event EFI_READY_TO_BOOT_EVENT_GUID .
36.1.5 Deferred Execution
The platform may need to defer the execution of an image because of security considerations. For example, see Load-
Image(). Information about the images which are not executed because of security considerations may be recorded and
then reported by installing an instance of the EFI_DEFERRED_IMAGE_LOAD_PROTOCOL (see Deferred Image
Load Protocol ). There may be more than one producer of the protocol.
The ﬁrmware’s boot manager may use the instances of this protocol in order to automatically load drivers whose
execution was deferred because of inadequate privileges once the current user proﬁle contains adequate security priv-
ileges.
This boot manager can reevaluate the deferred images each time that the event
EFI_EVENT_GROUP_USER_IDENTITY_CHANGED is signaled
Images which have been loaded may not be unloaded when the current user proﬁle is changed, even if the new user
proﬁle would have prevented that driver from being loaded.
36.2 User Identiﬁcation Process
This section describes the typical initialization steps required for the user identiﬁcation process.
36.2.1 User Identiﬁcation Process
1. The User Identity Manager is launched. This driver reads all of the user proﬁles from the user
proﬁle database, sets the default user proﬁle as the current proﬁle, and installs an instance of the
EFI_USER_MANAGER_PROTOCOL.
2. Each credential provider driver registers their user-interface related forms and installs an instance of the
EFI_USER_CREDENTIAL2_PROTOCOL.
3. The User Identity Manager’s Identify() function is called to select the current user.
4. The User Identity Manager enumerates all of the User Credential Providers required by the User Identiﬁcation
Policy.
a. Select the User Credential Provider which returns Default = TRUE from the Default() function. If more than
one return TRUE or none return TRUE , choose a default based on implementation-speciﬁc criteria
(last-logged-on, etc.)
b. If that credential provider also returns AutoLogon = TRUE from the Default() function, then call User(). If
no error was returned and a user proﬁle with the speciﬁed user identiﬁer exists, select the speciﬁed user proﬁle
as the current user proﬁle and jump to step 9.
5. The User Identity Manager enumerates all of the User Credential Providers required by the User Identiﬁcation
Policy:
36.2. User Identiﬁcation Process 1707Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
a. Call the Title() and (optionally) the Tile() function to retrieve the text and image indicated for each User
Credential Provider.
b. Call the Form() function to retrieve the form indicated for each User Credential Provider.
c. Create the user interface to allow the user to select between the different User Credential Providers.

Policy:
d. Highlight the default User Credential Provider, as speciﬁed in step 4.a.
6. If the user selects one of the User Credential Providers, call Select(). If AutoLogon = TRUE on return, then call
User(). If no error was returned and a user proﬁle with the speciﬁed user identiﬁer exists, select the speciﬁed
user proﬁle as the current user proﬁle and jump to step 9.
7. Interact with the user. Regular interaction can occur using the Callback() functions. If another User Credential
Provider is selected then Deselect() is called for the current User Credential Provider and Select() is called for
the newly selected User Credential Provider.
8. If the user presses OK then the User Manager will saved settings using the EFI Conﬁguration Access protocol.
Then it will call the User() function of each credential provider. If it returns successfully and one of the user
policies evaluates to TRUE , then select the speciﬁed user proﬁle as the current user proﬁle and go to step 9.
Otherwise display an error and go back.
9. Go through all of the credential providers using GetNextInfo() andGetInfo() and add the information to the
current user proﬁle.
10. Exit
36.2.2 Changing The Current User Proﬁle
This section describes the typical actions taken when the current user proﬁle is changed.
1. If there was already a valid current user proﬁle, then all records marked as private in that proﬁle are no longer
available.
2. All records marked as private in the new user proﬁle will be available.
3. The handle of the current user proﬁle is changed.
4. An event with the GUID EFI_EVENT_GROUP_USER_IDENTITY_CHANGED is signaled to indicate that the
current user proﬁle has been changed.
36.2.3 Ready To Boot
Before the boot manager is read to pass control to the boot option and signals the
EFI_EVENT_GROUP_READY_TO_BOOT event group, the User Identity Manager will publish the current
user proﬁle into the EFI System Conﬁguration Table with the EFI_USER_MANAGER_PROTOCOL_GUID . The
format is described in the User Information Table (User Information Table ). It will also save all non-volatile proﬁle
User Credential drivers with non-volatile storage should also store non-volatile credential information which has
changed.
36.2. User Identiﬁcation Process 1708Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.3 Code Deﬁnitions
36.3.1 User Manager Protocol
36.3.1.1 EFI_USER_MANAGER_PROTOCOL
Summary
Reports information about a user.
GUID
#define EFI_USER_MANAGER_PROTOCOL_GUID \
{ 0x6fd5b00c, 0xd426, 0x4283, \
{ 0x98, 0x87, 0x6c, 0xf5, 0xcf, 0x1c, 0xb1, 0xfe } };
typedef struct _EFI_USER_MANAGER_PROTOCOL {
EFI_USER_PROFILE_CREATE Create;
EFI_USER_PROFILE_DELETE Delete;
EFI_USER_PROFILE_GET_NEXT GetNext;
EFI_USER_PROFILE_CURRENT Current;
EFI_USER_PROFILE_IDENTIFY Identify;
EFI_USER_PROFILE_FIND Find;
EFI_USER_PROFILE_NOTIFY Notify;
EFI_USER_PROFILE_GET_INFO GetInfo;
EFI_USER_PROFILE_SET_INFO SetInfo;
EFI_USER_PROFILE_DELETE_INFO DeleteInfo;
EFI_USER_PROFILE_GET_NEXT_INFO GetNextInfo;
} EFI_USER_MANAGER_PROTOCOL;
Create Create a new user proﬁle.
Delete Delete an existing user proﬁle.
GetNext Cycle through all user proﬁles.
Current Return the current user proﬁle.
Identify Identify a user and set the current user proﬁle using credentials.
Find Find a user by a piece of user information.
Notify Notify the user manager driver that credential information has changed.
GetInfo Return information from a user proﬁle.
SetInfo Change information in a user proﬁle.
DeleteInfo Delete information from a user proﬁle.
GetNextInfo Cycle through all information from a user proﬁle.
This protocol manages user proﬁles.
36.3. Code Deﬁnitions 1709Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.3.1.2 EFI_USER_MANAGER_PROTOCOL.Create()
Summary
Create a new user proﬁle.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_CREATE) (
IN CONST EFI_USER_MANAGER_PROTOCOL *This,
OUT EFI_USER_PROFILE_HANDLE *User
);
This Points to this instance of the EFI_USER_MANAGER_PROTOCOL .
User On return, points to the new user proﬁle handle. The user proﬁle handle is unique only during this boot.
This function creates a new user proﬁle with only a new user identiﬁer attached and returns its handle. The user proﬁle
is non-volatile, but the handle User can change across reboots.
If the current user proﬁle does not permit creation of new user proﬁles then EFI_ACCESS_DENIED will be returned.
If creation of new user proﬁles is not supported, then EFI_UNSUPPORTED is returned.
typedef VOID *EFI_USER_PROFILE_HANDLE;
EFI_SUCCESS User proﬁle was successfully created.
EFI_ACCESS_DENIED Current user does not have sufﬁcient permissions to create a user proﬁle.
EFI_UNSUPPORTED Creation of new user proﬁles is not supported.
EFI_INV ALID_PARAMETER User isNULL .
36.3.1.3 EFI_USER_MANAGER_PROTOCOL.Delete()
Summary
Delete an existing user proﬁle.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_DELETE) (
IN EFI_USER_PROFILE_HANDLE User
);
User User proﬁle handle. Type EFI_USER_PROFILE_HANDLE is deﬁned in Create() .
36.3. Code Deﬁnitions 1710Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Delete an existing user proﬁle. If the current user proﬁle does not permit deletion of user proﬁles then
EFI_ACCESS_DENIED will be returned. If there is only a single user proﬁle then EFI_ACCESS_DENIED will be
returned. If deletion of user proﬁles is not supported, then EFI_UNSUPPORTED will be returned.
EFI_SUCCESS User proﬁle was successfully deleted.
EFI_ACCESS_DENIED Current user does not have sufﬁcient permissions to delete a user proﬁle or
there is only one user proﬁle.
EFI_UNSUPPORTED Deletion of new user proﬁles is not supported.
EFI_INV ALID_PARAMETER User does not refer to a valid user proﬁle.
36.3.1.4 EFI_USER_MANAGER_PROTOCOL.GetNext()
Summary
Enumerate all of the enrolled users on the platform.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_GET_NEXT)(
IN OUT EFI_USER_PROFILE_HANDLE *User
);
This Points to the instance of this EFI_USER_MANAGER_PROTOCOL .
User On entry, points to the previous user proﬁle handle or NULL to start enumeration. On exit, points to the next
user proﬁle handle or NULL if there are no more user proﬁles.
This function returns the next enrolled user proﬁle. To retrieve the ﬁrst user proﬁle handle, point User at a NULL.
Each subsequent call will retrieve another user proﬁle handle until there are no more, at which point User will point to
NULL.
NOTE :There is always at least one user proﬁle.
EFI_SUCCESS Next enrolled user proﬁle successfully returned.
EFI_ACCESS_DENIED Next enrolled user proﬁle was not successfully returned.
36.3. Code Deﬁnitions 1711Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.3.1.5 EFI_USER_MANAGER_PROTOCOL.Current()
Summary
Return the current user proﬁle handle.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_CURRENT)(
OUT EFI_USER_PROFILE_HANDLE *CurrentUser
);
CurrentUser On return, points to the current user proﬁle handle.
This function returns the current user proﬁle handle.
EFI_SUCCESS Current user proﬁle handle returned successfully.
EFI_INV ALID_PARAMETER CurrentUser isNULL .
36.3.1.6 EFI_USER_MANAGER_PROTOCOL.Identify()
Summary
Identify a user.
Prototype
typedef
(EFIAPI *EFI_USER_IDENTIFY) (
);
This Points to the instance of the EFI_USER_MANAGER_PROTOCOL .
User On return, points to the user proﬁle handle for the current user proﬁle.
Identify the user and, if authenticated, returns the user handle and changes the current user proﬁle.
All user information marked as private in a previously selected proﬁle is no longer available for inspection.
Whenever the current user proﬁle is changed then the an event with the GUID
EFI_EVENT_GROUP_USER_PROFILE_CHANGED is signaled.
The function can only be called at TPL_APPLICATION .
36.3. Code Deﬁnitions 1712Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_EVENT_GROUP_USER_PROFILE_CHANGED \
{ 0xbaf1e6de, 0x209e, 0x4adb, \
{ 0x8d, 0x96, 0xfd, 0x8b, 0x71, 0xf3, 0xf6, 0x83 } }
EFI_SUCCESS User was successfully identiﬁed.
EFI_ACCESS_DENIED User was not successfully identiﬁed.
36.3.1.7 EFI_USER_MANAGER_PROTOCOL.Find()
Summary
Find a user using a user information record.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_FIND)(

Summary
Prototype
typedef
IN OUT EFI_USER_PROFILE_HANDLE *User,
IN OUT EFI_USER_INFO_HANDLE *UserInfo OPTIONAL,
IN CONST EFI_USER_INFO *Info,
IN UINTN InfoSize
);
User On entry, points to the previously returned user proﬁle handle or NULL to start searching with the ﬁrst user
proﬁle. On return, points to the user proﬁle handle or NULL if not found.
UserInfo On entry, points to the previously returned user information handle or NULL to start searching with
the ﬁrst. On return, points to the user information handle of the user information record or NULL if not
found. Can be NULL, in which case only one user information record per user can be returned. Type
EFI_USER_INFO_HANDLE is deﬁned in “Related Deﬁnitions” below.
Info Points to the buffer containing the user information to be compared to the user information record.If the user
information record data is empty, then only the user information record type is compared.
IfInfoSize is 0, then the user information record data must be empty.
InfoSize The size of Info, in bytes.
This function searches all user proﬁles for the speciﬁed user information record. The search starts with the user
information record handle following UserInfo and continues until either the information is found or there are no more
user proﬁles.
A match occurs when the Info.InfoType ﬁeld matches the user information record type and the user information record
data matches a portion of Info.
36.3. Code Deﬁnitions 1713Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS User information was found. User points to the user proﬁle handle and
UserInfo points to the user information handle.
EFI_NOT_FOUND User information was not found. User points to NULL andUserInfo points
toNULL.
EFI_INV ALID_PARAMETER User isNULL . OrInfoisNULL .
typedef VOID *EFI_USER_INFO_HANDLE;
36.3.1.8 EFI_USER_MANAGER_PROTOCOL.Notify()
Summary
Called by credential provider to notify of information change.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_NOTIFY)(
IN EFI_HANDLE Changed
);
Changed Handle on which is installed an instance of the EFI_USER_CREDENTIAL2_PROTOCOL where the user
has changed.
This function allows the credential provider to notify the User Identity Manager when user status has changed.
If the User Identity Manager doesn’t support asynchronous changes in credentials, then this function should return
If current user does not exist, and the credential provider can identify a user, then make the user to be current user and
signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event.
If current user already exists, and the credential provider can identify another user, then switch current user to the
newly identiﬁed user, and signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event.
If current user was identiﬁed by this credential provider and now the credential provider cannot identify current user,
then logout current user and signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event.
EFI_SUCCESS The User Identity Manager has handled the notiﬁcation.
EFI_NOT_READY The function was called while the speciﬁed credential provider was not se-
lected.
EFI_UNSUPPORTED The User Identity Manager doesn’t support asynchronous notiﬁcations.
36.3. Code Deﬁnitions 1714Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.3.1.9 EFI_USER_MANAGER_PROTOCOL.GetInfo()
Summary
Return information attached to the user.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_GET_INFO)(
IN EFI_USER_PROFILE_HANDLE User,
IN EFI_USER_INFO_HANDLE UserInfo,
OUT EFI_USER_INFO *Info,
IN OUT UINTN *InfoSize
);
User Handle of the user whose proﬁle will be retrieved.
UserInfo Handle of the user information data record. Type EFI_USER_INFO_HANDLE is deﬁned in GetInfo() .
Info On entry, points to a buffer of at least * InfoSize bytes. On exit, holds the user information. If the buffer is too
small to hold the information, then EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain
the number of bytes actually required. Type EFI_USER_INFO is described in “Related Deﬁnitions” below.
InfoSize On entry, points to the size of Info. On return, points to the size of the user information.
This function returns user information. The format of the information is described in User Information. The function
may return EFI_ACCESS_DENIED if the information is marked private and the handle speciﬁed by User is not the
current user proﬁle. The function may return EFI_ACCESS_DENIED if the information is marked protected and the
information is associated with a credential provider for which the user has not been authenticated.
EFI_SUCCESS Information returned successfully.
EFI_ACCESS_DENIED The information about the speciﬁed user cannot be accessed by the current
user.
EFI_BUFFER_TOO_SMALL The number of bytes speciﬁed by * InfoSize is too small to hold the returned
data. The actual size required is returned in * InfoSize .
EFI_NOT_FOUND User does not refer to a valid user proﬁle or UserInfo does not refer to a
valid user info handle.
EFI_INV ALID_PARAMETER InfoisNULL orInfoSize isNULL
EFI_GUID Credential;
UINT8 InfoType;
UINT8 Reserved1;
EFI_USER_INFO_ATTRIBS InfoAttribs;
} EFI_USER_INFO;
36.3. Code Deﬁnitions 1715Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Credential The user credential identiﬁer associated with this user information or else Nil if the information is not
associated with any speciﬁc credential.
InfoType The type of user information. See EFI_USER_INFO_x_RECORD in User Information for a description of
the different types of user information.
Reserved1 Must be set to 0.
InfoAttribs The attributes of the user proﬁle information.
InfoSize The size of the user information, in bytes, including this header.
typedef UINT16 EFI_USER_INFO_ATTRIBS;
#define EFI_USER_INFO_STORAGE 0x000F
#define EFI_USER_INFO_STORAGE_VOLATILE 0x0000
#define EFI_USER_INFO_STORAGE_CREDENTIAL_NV 0x0001
#define EFI_USER_INFO_STORAGE_PLATFORM_NV 0x0002
#define EFI_USER_INFO_ACCESS 0x0070
#define EFI_USER_INFO_PUBLIC 0x0010
#define EFI_USER_INFO_PRIVATE 0x0020
#define EFI_USER_INFO_PROTECTED 0x0030
#define EFI_USER_INFO_EXCLUSIVE 0x0080
The EFI_USER_INFO_STORAGE_x values describe how the user information should be stored. If
EFI_USER_INFO_STORAGE_VOLATILE is speciﬁed, then the user proﬁle information will be lost after a reboot.
IfEFI_USER_INFO_STORAGE_CREDENTIAL_NV is speciﬁed, then the information will be stored by the driver
which created the handle Credential. If USER_INFO_STORAGE_PLATFORM_NV is speciﬁed, then the information
will be stored by the User Identity Manager in platform non-volatile storage.
There are three levels of access to information associated with the user proﬁle: public, private or pro-
tected. If EFI_USER_INFO_PUBLIC is speciﬁed, then the user proﬁle information is available always. If
EFI_USER_INFO_PRIVATE is speciﬁed, then the user proﬁle information is only available if the user has been au-
thenticated (whether or not they are the current user). If EFI_USER_INFO_PROTECTED is speciﬁed, then the user
proﬁle information is only available if the user has been authenticated and is the current user.
IfEFI_USER_INFO_EXCLUSIVE is speciﬁed then there can only be one user information record of this type in the
user proﬁle. Attempts to use SetInfo() will fail.
36.3.1.10 EFI_USER_MANAGER_PROTOCOL.SetInfo()
Summary
Add or update user information.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_SET_INFO) (
IN OUT EFI_USER_INFO_HANDLE *UserInfo,
);
36.3. Code Deﬁnitions 1716Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
User Handle of the user whose proﬁle will be changed.
UserInfo On entry, points to the handle of the user information record to change or NULL if the user information
should be added to the user proﬁle. On exit, points to the handle of the user credential information record.
Info Points to the user information. See EFI_USER_INFO for more information.
This function changes user information. If NULL is pointed to by UserInfo, then a new user information record is
created and its handle is returned in UserInfo . Otherwise, the existing one is replaced.

typedef
);
IfEFI_USER_INFO_IDENTITY_POLICY_RECORD is changed, it is the caller’s responsibility to keep it to be synced
with the information on credential providers.
IfEFI_USER_INFO_EXCLUSIVE is speciﬁed in Info and a user information record of the same type already exists
in the user proﬁle, then EFI_ACCESS_DENIED will be returned and UserInfo will point to the handle of the existing
record.
EFI_SUCCESS User proﬁle information was successfully changed/added.
EFI_ACCESS_DENIED The record is exclusive.
EFI_SECURITY_VIOLATION The current user does not have permission to change the speciﬁed user pro-
ﬁle or user information record.
36.3.1.11 EFI_USER_MANAGER_PROTOCOL.DeleteInfo()
Summary
Delete user information.
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_DELETE_INFO) (
IN EFI_USER_INFO_HANDLE UserInfo
);
User Handle of the user whose information will be deleted.
UserInfo Handle of the user information to remove.
Delete the user information attached to the user proﬁle speciﬁed by the UserInfo.
36.3. Code Deﬁnitions 1717Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS User information deleted successfully.
EFI_NOT_FOUND User information record UserInfo does not exist in the user proﬁle.
EFI_ACCESS_DENIED The current user does not have permission to delete this user information.
36.3.1.12 EFI_USER_MANAGER_PROTOCOL.GetNextInfo()
Summary
Prototype
typedef
(EFIAPI *EFI_USER_PROFILE_GET_NEXT_INFO)(
IN OUT EFI_USER_INFO_HANDLE *UserInfo
);
User Handle of the user whose information will be enumerated
UserInfo On entry, points to the previous user information handle or NULL to start enumeration. On exit, points to
the next user information handle or NULL if there is no more user information.
This function returns the next user information record. To retrieve the ﬁrst user information record handle, point
UserInfo at a NULL . Each subsequent call will retrieve another user information record handle until there are no
more, at which point UserInfo will point to NULL .
EFI_SUCCESS User information returned.
EFI_NOT_FOUND No more user information found.
EFI_INV ALID_PARAMETER UserInfo isNULL .
36.3.2 Credential Provider Protocols
36.3.2.1 EFI_USER_CREDENTIAL2_PROTOCOL
Summary
Provide support for a single class of credentials
GUID
#define EFI_USER_CREDENTIAL2_PROTOCOL_GUID \
{ 0xe98adb03, 0xb8b9, 0x4af8, \
{ 0xba, 0x20, 0x26, 0xe9, 0x11, 0x4c, 0xbc, 0xe5 } }
36.3. Code Deﬁnitions 1718Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Prototype
typedef struct _EFI_USER_CREDENTIAL2_PROTOCOL {
EFI_GUID Identifier;
EFI_GUID Type;
EFI_CREDENTIAL_ENROLL Enroll;
EFI_CREDENTIAL_FORM Form;
EFI_CREDENTIAL_TILE Tile;
EFI_CREDENTIAL_TITLE Title;
EFI_CREDENTIAL_USER User;
EFI_CREDENTIAL_SELECT Select;
EFI_CREDENTIAL_DESELECT Deselect;
EFI_CREDENTIAL_DEFAULT Default;
EFI_CREDENTIAL_GET_INFO GetInfo;
EFI_CREDENTIAL_GET_NEXT_INFO GetNextInfo;
EFI_CREDENTIAL_CAPABILITIES Capabilities;
EFI_CREDENTIAL_DELETE Delete;
} EFI_USER_CREDENTIAL2_PROTOCOL;
Identiﬁer Uniquely identiﬁes this credential provider.
Type Identiﬁes this class of User Credential Provider. See EFI_CREDENTIAL_CLASS_x in “Related Deﬁnitions”
below.
Enroll Enroll a user using this credential provider.
Form Return the form set and form identiﬁer for the form.
Tile Returns an optional bitmap image used to identify this credential provider.
Title Returns a string used to identify this credential provider.
User Returns the user proﬁle identiﬁer ascertained by using this credential.
Select Called when a credential provider is selected.
Deselect Called when a credential provider is deselected.
Default Returns whether the credential provider can provide the default credential.
GetInfo Return user information provided by the credential provider.
GetNextInfo Cycle through all user information available from the credential provider.
Capabilities Bitmask which describes the capabilities supported by the credential provider. Type
EFI_CREDENTIAL_CAPABILITIES is deﬁned in “Related Deﬁnitions” below.
Delete Delete a user on this credential provider.
Attached to a device handle, this protocol identiﬁes a single means of identifying the user.
IfEFI_CREDENTIAL_CAPABILITIES_ENROLL is speciﬁed, then this credential provider supports the ability to en-
roll new user identiﬁcation information using the Enroll() function.
#define EFI_USER_CREDENTIAL_CLASS_UNKNOWN \
{ 0x5cf32e68, 0x7660, 0x449b, \
{ 0x80, 0xe6, 0x7e, 0xa3, 0x6e, 0x3, 0xf6, 0xa8 } };
36.3. Code Deﬁnitions 1719Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_USER_CREDENTIAL_CLASS_PASSWORD \
{ 0xf8e5058c, 0xccb6, 0x4714, \
{ 0xb2, 0x20, 0x3f, 0x7e, 0x3a, 0x64, 0xb, 0xd1 } };
#define EFI_USER_CREDENTIAL_CLASS_SMART_CARD \
{ 0x5f03ba33, 0x8c6b, 0x4c24, \
{ 0xaa, 0x2e, 0x14, 0xa2, 0x65, 0x7b, 0xd4, 0x54 } };
#define EFI_USER_CREDENTIAL_CLASS_FINGERPRINT \
{ 0x32cba21f, 0xf308, 0x4cbc, \
{ 0x9a, 0xb5, 0xf5, 0xa3, 0x69, 0x9f, 0x4, 0x4a } };
#define EFI_USER_CREDENTIAL_CLASS_HANDPRINT \
{ 0x5917ef16, 0xf723, 0x4bb9, \
{ 0xa6, 0x4b, 0xd8, 0xc5, 0x32, 0xf4, 0xd8, 0xb5 } };
#define EFI_USER_CREDENTIAL_CLASS_SECURE_CARD \
{ 0x8a6b4a83, 0x42fe, 0x45d2, \
{ 0xa2, 0xef, 0x46, 0xf0, 0x6c, 0x7d, 0x98, 0x52 } };
typedef UINT64 EFI_CREDENTIAL_CAPABILITIES;
#define EFI_CREDENTIAL_CAPABILITIES_ENROLL 0x0000000000000001
36.3.2.2 EFI_USER_CREDENTIAL2_PROTOCOL.Enroll()
Summary
Enroll a user on a credential provider.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL2_ENROLL)(
IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This,
);
This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL .
User The user proﬁle to enroll.
This function enrolls a user on this credential provider. If the user exists on this credential provider, update the user
information on this credential provider; otherwise add the user information on credential provider.
EFI_SUCCESS User proﬁle was successfully enrolled
EFI_ACCESS_DENIED Current user proﬁle does not permit enrollment on the user proﬁle handle.
Either the user proﬁle cannot enroll on any user proﬁle or cannot enroll on
a user proﬁle other than the current user proﬁle.
36.3. Code Deﬁnitions 1720Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 36.9 – continued from previous page
EFI_UNSUPPORTED This credential provider does not support enrollment in the pre-OS.
EFI_DEVICE_ERROR The new credential could not be created because of a device error.
EFI_INV ALID_PARAMETER User does not refer to a valid user proﬁle handle.
36.3.2.3 EFI_USER_CREDENTIAL2_PROTOCOL.Form()
Summary
Returns the user interface information used during user identiﬁcation.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL_FORM)(
OUT EFI_HII_HANDLE *Hii,
OUT EFI_GUID *FormSetId,
OUT EFI_FORM_ID *FormId
);
HiiOn return, holds the HII database handle. Type EFI_HII_HANDLE is deﬁned in
FormSetId On return, holds the identiﬁer of the form set which contains the form used during user identiﬁcation.
FormId On return, holds the identiﬁer of the form used during user identiﬁcation.
This function returns information about the form used when interacting with the user during user identiﬁcation. The
form is the ﬁrst enabled form in the form-set class EFI_HII_USER_CREDENTIAL_FORMSET_GUID installed on the
HII handle HiiHandle . If the user credential provider does not require a form to identify the user, then this function
should return EFI_NOT_FOUND .
EFI_SUCCESS Form returned successfully.
EFI_NOT_FOUND Form not returned.
EFI_INV ALID_PARAMETER HiiisNULL orFormSetId isNULL orFormId isNULL
36.3.2.4 EFI_USER_CREDENTIAL2_PROTOCOL.Tile()
Summary
Returns bitmap used to describe the credential provider type.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL_TILE)(
36.3. Code Deﬁnitions 1721Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

Summary
Prototype
typedef
IN OUT UINTN *Width,
IN OUT UINTN *Height,
OUT EFI_IMAGE_ID *Image
);
Width On entry, points to the desired bitmap width. If NULL then no bitmap information will be returned. On exit,
points to the width of the bitmap returned.
Height On entry, points to the desired bitmap height. If NULL then no bitmap information will be returned. On exit,
points to the height of the bitmap returned.
Image On return, holds the HII image identiﬁer. Type EFI_IMAGE_ID is deﬁned in this speciﬁcation, Image Protocol
.
This optional function returns a bitmap which is less than or equal to the number of pixels speciﬁed by Width and
Height . If no such bitmap exists, then EFI_NOT_FOUND is returned.
EFI_SUCCESS Image identiﬁer returned successfully.
EFI_NOT_FOUND Image identiﬁer not returned.
EFI_INV ALID_PARAMETER HiiisNULL orImage isNULL .
36.3.2.5 EFI_USER_CREDENTIAL2_PROTOCOL.Title()
Summary
Returns string used to describe the credential provider type.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL_TITLE)(
OUT EFI_STRING_ID *String
);
HiiOn return, holds the HII database handle. TType EFI_HII_HANDLE is deﬁned in
String On return, holds the HII string identiﬁer. Type EFI_STRING_ID is deﬁned in EFI_IFR_OP_HEADER .
36.3. Code Deﬁnitions 1722Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function returns a string which describes the credential provider. If no such string exists, then EFI_NOT_FOUND
EFI_SUCCESS String identiﬁer returned successfully.
EFI_NOT_FOUND String identiﬁer not returned.
EFI_INV ALID_PARAMETER HiiisNULL orString isNULL
36.3.2.6 EFI_USER_CREDENTIAL2_PROTOCOL.User()
Summary
Return the user identiﬁer associated with the currently authenticated user.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL_USER)(
OUT EFI_USER_INFO_IDENTIFIER *Identifier
);
User The user proﬁle handle of the user proﬁle currently being considered by the user identity manager. If NULL,
then no user proﬁle is currently under consideration.
Identiﬁer On return, points to the user identiﬁer. Type EFI_USER_INFO_IDENTIFIER is deﬁned in “Related Deﬁ-
nitions” below.
This function returns the user identiﬁer of the user authenticated by this credential provider. This function is called
after the credential-related information has been submitted on a form OR after a call to Default() has returned that this
credential is ready to log on.
This function can return one of ﬁve possible responses:
• If no user proﬁle can yet be identiﬁed, then EFI_NOT_READY is returned.
• If the user has been locked out, then EFI_ACCESS_DENIED is returned.
• If the user speciﬁed by User is identiﬁed, then Identiﬁer returns with the user identiﬁer associated with that
handle and EFI_SUCCESS is returned.
• IfIdentiﬁer isNULL, then EFI_INVALID_PARAMETER is returned.
• If speciﬁed User does not refer to a valid user proﬁle, then EFI_NOT_FOUND is returned.
36.3. Code Deﬁnitions 1723Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS User identiﬁer returned successfully.
EFI_NOT_READY No user identiﬁer can be returned.
EFI_ACCESS_DENIED The user has been locked out of this user credential.
EFI_NOT_FOUND User is not NULL, and the speciﬁed user handle can’t be found in user
proﬁle database
EFI_INV ALID_PARAMETER Identiﬁer isNULL .
36.3.2.7 EFI_USER_CREDENTIAL2_PROTOCOL.Select()
Summary
Indicate that user interface interaction has begun for the speciﬁed credential.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL_SELECT)(
OUT EFI_CREDENTIAL_LOGON_FLAGS *AutoLogon
);
AutoLogon On return, points to the credential provider’s capabilities after the credential provider has been selected
by the user. Type EFI_CREDENTIAL_LOGON_FLAGS is deﬁned in “Related Deﬁnitions” below.
This function is called when a credential provider is selected by the user. If AutoLogon returns FALSE, then the user
interface will be constructed by the User Identity Manager.
typedef UINT32 EFI_CREDENTIAL_LOGON_FLAGS;
#define EFI_CREDENTIAL_LOGON_FLAG_AUTO 0x00000001
#define EFI_CREDENTIAL_LOGON_FLAG_DEFAULT 0x00000002
IfEFI_CREDENTIAL_LOGON_FLAG_AUTO is set, then the User Identity Manager may use this as a hint to try
logging on immediately. If not set, then the User Identity Manager may use this as an indication to wait for the user to
submit the information.
IfEFI_CREDENTIAL_LOGON_FLAG_DEFAULT is set, then the User Identity Manager may use this as a hint to
use this credential provider as the default credential provider. If more than one credential provider returns with
this set, then the selection is implementation speciﬁc. If EFI_CREDENTIAL_LOGON_FLAG_DEFAULT is set and
EFI_CREDENTIAL_LOGON_FLAG_AUTO is set then the User Identity Manager may uses this as a hint to log the
user on immediately.
EFI_SUCCESS Credential provider successfully selected.
EFI_INV ALID_PARAMETER AutoLogon isNULL
36.3. Code Deﬁnitions 1724Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.3.2.8 EFI_USER_CREDENTIAL2_PROTOCOL.Deselect()
Summary
Indicate that user interface interaction has ended for the speciﬁed credential.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL_DESELECT)(
IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This
);
This function is called when a credential provider is deselected by the user.
36.3.2.9 EFI_USER_CREDENTIAL2_PROTOCOL.Default()
Summary
Return the default logon behavior for this user credential.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL_DEFAULT)(
);
AutoLogon On return, holds whether the credential provider should be used by default to au-
tomatically log on the user. Type EFI_CREDENTIAL_LOGON_FLAGS is deﬁned in
EFI_USER_CREDENTIAL2_PROTOCOL.Select() .
This function reports the default login behavior regarding this credential provider.
EFI_SUCCESS Default information successfully returned.
36.3. Code Deﬁnitions 1725Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.3.2.10 EFI_USER_CREDENTIAL2_PROTOCOL.GetInfo()
Summary
Return information attached to the credential provider.
Prototype
typedef
(EFIAPI *EFI_CREDENTIAL_GET_INFO)(
);
Info On entry, points to a buffer of at least **InfoSize* bytes. On exit, holds the user information. If the buffer is too
This function returns user information.
EFI_BUFFER_TOO_SMALL The size speciﬁed by InfoSize is too small to hold all of the user information.
The size required is returned in * InfoSize .
EFI_NOT_FOUND The speciﬁed UserInfo does not refer to a valid user info handle
36.3.2.11 EFI_USER_CREDENTIAL2_PROTOCOL.GetNextInfo()
Summary
Enumerate all of the user information records on the credential provider.
Prototype
typedef
(EFIAPI *EFI_USER_CREDENTIAL_GET_NEXT_INFO)(
);
This Points to the instance of this EFI_USER_CREDENTIAL2_PROTOCOL .

Summary
Prototype
typedef
);
36.3. Code Deﬁnitions 1726Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.3.2.12 EFI_USER_CREDENTIAL2_PROTOCOL.Delete()
Summary
Delete a user on a credential provider.
Prototype
typedef
EFI_STATUS (EFIAPI *EFI_CREDENTIAL_DELETE)(
);
User The user proﬁle handle to delete.
This function deletes a user on this credential provider.
EFI_SUCCESS User proﬁle was successfully deleted .
EFI_ACCESS_DENIED Current user proﬁle does not permit deletion on the user proﬁle handle.
Either the user proﬁle cannot delete on any user proﬁle or cannot delete on
EFI_UNSUPPORTED This credential provider does not support deletion in the pre-OS.
EFI_DEVICE_ERROR The new credential could not be deleted because of a device error.
36.3. Code Deﬁnitions 1727Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.3.3 Deferred Image Load Protocol
36.3.3.1 EFI_DEFERRED_IMAGE_LOAD_PROTOCOL
Summary
Enumerates images whose load was deferred due to security considerations.
GUID
#define EFI_DEFERRED_IMAGE_LOAD_PROTOCOL_GUID \
{ 0x15853d7c, 0x3ddf, 0x43e0, \
{ 0xa1, 0xcb, 0xeb, 0xf8, 0x5b, 0x8f, 0x87, 0x2c } };
typedef struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL {
EFI_DEFERRED_IMAGE_INFO GetImageInfo();
} EFI_DEFERRED_IMAGE_LOAD_PROTOCOL;
Members
GetImageInfo Return information about a single deferred image. See GetImageInfo() for more information.
This protocol returns information about images whose load was denied because of security considerations. This
information can be used by the Boot Manager or another agent to reevaluate the images when the current security
proﬁle has been changed, such as when the current user proﬁle changes. There can be more than one instance of this
protocol installed.
36.3.3.2 EFI_DEFERRED_IMAGE_LOAD_PROTOCOL.GetImageInfo()
Summary
Returns information about a deferred image.
Prototype
typedef
(EFIAPI *EFI_DEFERRED_IMAGE_INFO)(
IN EFI_DEFERRED_IMAGE_LOAD_PROTOCOL *This,
IN UINTN ImageIndex,
OUT EFI_DEVICE_PATH_PROTOCOL **ImageDevicePath,
OUT VOID **Image,
OUT UINTN *ImageSize,
OUT BOOLEAN *BootOption
);
This Points to this instance of the EFI_DEFERRED_IMAGE_LOAD_PROTOCOL .
ImageIndex Zero-based index of the deferred index.
ImageDevicePath On return, points to a pointer to the device path of the image. The device path should not be freed
by the caller.
Image On return, points to the ﬁrst byte of the image or NULL if the image is not available. The image should not
be freed by the caller unless LoadImage() has been called successfully.
36.3. Code Deﬁnitions 1728Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ImageSize On return, the size of the image, or 0 if the image is not available.
BootOption On return, points to TRUE if the image was intended as a boot option or FALSE if it was not intended
as a boot option.
This function returns information about a single deferred image. The deferred images are numbered consecutively,
starting with 0. If there is no image which corresponds to ImageIndex, then EFI_NOT_FOUND is returned. , All
deferred images may be returned by iteratively calling this function until EFI_NOT_FOUND is returned.
Image may be NULL andImageSize set to 0 if the decision to defer execution was made because of the location of the
executable image rather than its actual contents.
EFI_SUCCESS Image information returned successfully.
EFI_NOT_FOUND ImageIndex does not refer to a valid image.
EFI_INV ALID_PARAMETER ImageDevicePath isNULL orImage isNULL orImageSize isNULL or
BootOption isNULL
36.4 User Information
This section describes the different user information and the format of the data. Each of the following records is
preﬁxed with the EFI_USER_INFO structure. The format of the record is determined by the type speciﬁed by the
InfoType ﬁeld in the structure, as listed in the table below:
Record values and descriptions
Table 36.15: Record Values and Descriptions
EFI_USER_INFO_EMPTY_RECORD 0x00 No information.
EFI_USER_INFO_NAME_RECORD 0x01 User’s name
EFI_US ER_INFO_CREATE_DATE_RECORD 0x02 Date which the user proﬁle was created.
EFI_U SER_INFO_USAGE_DATE_RECORD 0x03 Date which the user proﬁle was last modi-
ﬁed.
EFI_US ER_INFO_USAGE_COUNT_RECORD 0x04 Number of times the credential has been
used.
EFI_U SER_INFO_IDENTIFIER_RECORD 0x05 User’s unique identiﬁer *
EFI_USER_I NFO_CREDENTIAL_TYPE_RECORD 0x06 Credential type.
EFI_USER_INFO_C REDEN-
TIAL_TYPE_NAME_RECORD0x07 Credential type name.
EFI_USER_INFO_ CREDEN-
TIAL_PROVIDER_RECORD0x08 Credential provider
EFI_USER_INFO_CREDE
NTIAL_PROVIDER_NAME_RECORD0x09 Credential provider name
EFI_USER_INFO_PKCS11_RECORD 0x0A PKCS11 Data Object
EFI_USER_INFO_CBEFF_RECORD 0x0B ISO 19785 (Common Biometric Exchange
Formats Framework) Data Object
EFI_USER_INFO_FAR_RECORD 0x0C How exact a match is required for biometric
identiﬁcation, measured in percentage.
EFI_USER_INFO_RETRY_RECORD 0x0D Number of retries allowed during veriﬁca-
tion.
36.4. User Information 1729Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 36.15 – continued from previous page
EFI_USER _INFO_ACCESS_POLICY_RECORD 0x0E Access control information.
EFI_USER_I NFO_IDENTITY_POLICY_RECORD 0x0F User identity expression.
EFI_USER_INFO_GUID_RECORD 0xFF Extended proﬁle information, qualiﬁed by a
GUID in the header.
36.4.1 EFI_USER_INFO_ACCESS_POLICY_RECORD
Summary
Provides the user’s pre-OS access rights.
Prototype
#define EFI_USER_INFO_ACCESS_POLICY_RECORD 0x0E
typedef EFI_USER_INFO_ACCESS_CONTROL EFI_USER_INFO_ACCESS_POLICY;
This structure described the access policy for the user. There can be, at most, one access policy record per credential
(including NULL credential). Policy records with a credential speciﬁed means that the policy is associated speciﬁcally
with the credential.
The policy is detailed in a series of encapsulated records of type EFI_USER_INFO_ACCESS_CONTROL .
} EFI_USER_INFO_ACCESS_CONTROL;
Type Speciﬁes the type of user access control. See EFI_USER_INFO_ACCESS_x for more information.
Size Speciﬁes the size of the user access control record, in bytes, including this header.
36.4.1.1 EFI_USER_INFO_ACCESS_FORBID_LOAD
Summary
Forbids the user from booting or loading executables from the speciﬁed device path or any child device paths.
Prototype
#define EFI_USER_INFO_ACCESS_FORBID_LOAD 0x00000001
This record prohibits the user from loading any executables from zero or device paths or any child device paths. The
device paths may contain a speciﬁc executable name, in which case the prohibition applies to only that executable.
The record is a series of normal UEFI device paths (not multi-instance device paths).
This prohibition is overridden by the EFI_USER_INFO_ACCESS_PERMIT_LOAD record.
36.4. User Information 1730Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.4.1.2 EFI_USER_INFO_ACCESS_PERMIT_LOAD
Summary
Permits the user from booting or loading executables from the speciﬁed device path or any child device paths.
Prototype
#define EFI_USER_INFO_ACCESS_PERMIT_LOAD 0x00000002
This record allows the user to load executables from locations speciﬁed by zero or more device paths or child paths.
The device paths may contain speciﬁc executable names, in which case, the permission applies only to that executable.
This prohibition overrides any restrictions put in place by the EFI_USER_INFO_ACCESS_FORBID_LOAD record.
36.4.1.3 EFI_USER_INFO_ACCESS_ENROLL_SELF
Summary
Presence of this record indicates that a user can update enrollment information.
Prototype
#define EFI_USER_INFO_ACCESS_ENROLL_SELF 0x00000003
If this record is present, then the pre-OS environment will allow the user to initiate an update of authentication in-

Summary
Prototype
Summary
Prototype
formation for his/her own proﬁle, but not other user information or other user’s information. This would allow, for
example, ﬁngerprint update or password change.
There is no data for this record.
36.4.1.4 EFI_USER_INFO_ACCESS_ENROLL_OTHERS
Summary
Presence of this record indicates that a user can enroll new users.
Prototype
#define EFI_USER_INFO_ACCESS_ENROLL_OTHERS 0x00000004
If this record is present, then the pre-OS environment will allow the user to initiate enrollment of new user proﬁles. It
does not give permission to update existing user proﬁles.
36.4. User Information 1731Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.4.1.5 EFI_USER_INFO_ACCESS_MANAGE
Summary
Presence of this record indicates that a user can update the user information of any user.
Prototype
#define EFI_USER_INFO_ACCESS_MANAGE 0x00000005
If this record is present, then the pre-OS environment will allow the user to update any information about his/her own
proﬁle or other proﬁles.
36.4.1.6 EFI_USER_INFO_ACCESS_SETUP
Summary
Describes permissions usable when conﬁguring the platform.
Prototype
#define EFI_USER_INFO_ACCESS_SETUP 0x00000006
This record describes access permission for use in conﬁguring the platform using an UEFI Forms Processor using zero
or more GUIDs. There are three standard values (see below) and any number of others may be added.
Standard values for access to conﬁgure the platform
Table 36.16: Standard Values for Access to Conﬁgure the Platform
EFI_USER_INFO_ACCESS_SETUP_ADMIN_GUID System administrator only.
EFI_USER_INFO_ACCESS_SETUP_NORMAL_GUID Normal user.
EFI_USER_INFO_ACCESS_SETUP_RESTRICTED_GUID Restricted user.
#define EFI_USER_INFO_ACCESS_SETUP_ADMIN_GUID \
{ 0x85b75607, 0xf7ce, 0x471e, \
{ 0xb7, 0xe4, 0x2a, 0xea, 0x5f, 0x72, 0x32, 0xee } };
#define EFI_USER_INFO_ACCESS_SETUP_NORMAL_GUID \
{ 0x1db29ae0, 0x9dcb, 0x43bc, \
{ 0x8d, 0x87, 0x5d, 0xa1, 0x49, 0x64, 0xdd, 0xe2 } };
#define EFI_USER_INFO_ACCESS_SETUP_RESTRICTED_GUID \
{ 0xbdb38125, 0x4d63, 0x49f4, \
{ 0x82, 0x12, 0x61, 0xcf, 0x5a, 0x19, 0x0a, 0xf8 } };
36.4. User Information 1732Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.4.1.7 EFI_USER_INFO_ACCESS_FORBID_CONNECT
Summary
Forbids UEFI drivers from being started from the speciﬁed device path(s) or any child device paths.
Prototype
#define EFI_USER_INFO_ACCESS_FORBID_CONNECT 0x00000007
This record prohibits UEFI drivers from being started from the speciﬁed device path(s) or any of their child device
path(s). This is enforced in the ConnectController() function.
This record prohibits the user from loading a device driver associated with zero or more device paths or their child
paths.
This prohibition is overridden by the EFI_USER_INFO_ACCESS_PERMIT_CONNECT record.
36.4.1.8 EFI_USER_INFO_ACCESS_PERMIT_CONNECT
Summary
Permits UEFI drivers to be started on the speciﬁed device path(s) or any child device paths.
Prototype
#define EFI_USER_INFO_ACCESS_PERMIT_CONNECT 0x00000008
This record allows loading of device drivers associated with zero or more device paths or their child paths.
This prohibition overrides any restrictions put in place by the EFI_USER_INFO_ACCESS_FORBID_CONNECT
record.
36.4.1.9 EFI_USER_INFO_ACCESS_BOOT_ORDER
Summary
Modiﬁes the boot order.
Prototype
#define EFI_USER_INFO_ACCESS_BOOT_ORDER 0x00000009
typedef UINT32 EFI_USER_INFO_ACCESS_BOOT_ORDER_HDR;
#define EFI_USER_INFO_ACCESS_BOOT_ORDER_MASK 0x000F
#define EFI_USER_INFO_ACCESS_BOOT_ORDER_INSERT 0x0000
#define EFI_USER_INFO_ACCESS_BOOT_ORDER_APPEND 0x0001
#define EFI_USER_INFO_ACCESS_BOOT_ORDER_REPLACE 0x0002
#define EFI_USER_INFO_ACCESS_BOOT_ORDER_NODEFAULT 0x0010
36.4. User Information 1733Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This exclusive record allows the user proﬁle to insert new boot options at the beginning of
the boot order ( EFI_USER_INFO_ACCESS_BOOT_ORDER_INSERT ), append new boot op-
tions to the end of the boot order ( EFI_USER_INFO_ACCESS_BOOT_ORDER_APPEND )
or replace the entire boot order ( EFI_USER_INFO_ACCESS_BOOT_ORDER_REPLACE) . If
EFI_USER_INFO_ACCESS_BOOT_ORDER_NODEFAULT is speciﬁed then the Boot Manager will not attempt ﬁnd
a default boot device when the default boot order is does not lead to a bootable device.
The boot options speciﬁed by this record are still subject to the permissions speciﬁed by
EFI_USER_INFO_ACCESS_FORBID_LOAD andEFI_USER_INFO_ACCESS_PERMIT_LOAD .
The record consists of a single EFI_USER_INFO_ACCESS_BOOT_ORDER_HDR followed by zero or more UEFI
36.4.2 EFI_USER_INFO_CBEFF_RECORD
Summary
Provides standard biometric information in the format speciﬁed by the ISO 19785 (Common Biometric Exchange
Formats Framework) speciﬁcation.
Prototype
#define EFI_USER_INFO_CBEFF_RECORD 0x0B
typedef VOID *EFI_USER_INFO_CBEFF;
36.4.3 EFI_USER_INFO_CREATE_DATE_RECORD
Summary
Provides the date and time when the user proﬁle was created.
Prototype
#define EFI_USER_INFO_CREATE_DATE_RECORD 0x02
typedef EFI_TIME EFI_USER_INFO_CREATE_DATE;
The optional record describing the date and time when the user proﬁle was created. Type EFI_TIME is deﬁned in
GetTime() in this speciﬁcation.
36.4.4 EFI_USER_INFO_CREDENTIAL_PROVIDER_RECORD
Summary
Speciﬁes the credential provider.
Prototype
#define EFI_USER_INFO_CREDENTIAL_PROVIDER_RECORD 0x08
typedef EFI_GUID EFI_USER_INFO_CREDENTIAL_PROVIDER;
This record speciﬁes the credential provider via a unique GUID. The credential’s handle is found in the
EFI_USER_INFO structure associated with this user information record.
36.4. User Information 1734Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.4.5 EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME_RECORD
Summary
Speciﬁes the user-readable name of a particular credential’s provider.
Prototype
#define EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME_RECORD 0x09
typedef CHAR16 *EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME;
This record speciﬁes the null-terminated name of a particular credential provider. The credential’s handle is found in
theEFI_USER_INFO structure associated with this user information record.
36.4.6 EFI_USER_INFO_CREDENTIAL_TYPE_RECORD
Summary
Speciﬁes the type of a particular credential associated with the user proﬁle.
Prototype
#define EFI_USER_INFO_CREDENTIAL_TYPE_RECORD 0x06
typedef EFI_GUID EFI_USER_INFO_CREDENTIAL_TYPE;
This record speciﬁes the type of a particular credential. The credential’s identiﬁer is found in the Credential ﬁeld of
theEFI_USER_INFO structure. The credential types are listed with the EFI_USER_CREDENTIAL2_PROTOCOL .
36.4.7 EFI_USER_INFO_CREDENTIAL_TYPE_NAME_RECORD
Summary
Speciﬁes the user-readable name of a particular credential type.
Prototype
#define EFI_USER_INFO_CREDENTIAL_TYPE_NAME_RECORD 0x07
typedef CHAR16 *EFI_USER_INFO_CREDENTIAL_TYPE_NAME;
This record speciﬁes the null-terminated name of a particular credential type. The credential’ handle is found in the
EFI_USER_INFO structure associated with this user information record
36.4. User Information 1735Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.4.8 EFI_USER_INFO_GUID_RECORD
Summary
Provides placeholder for additional user proﬁle information identiﬁed by a GUID.
Prototype
#define EFI_USER_INFO_GUID_RECORD 0xFF
typedef EFI_GUID EFI_USER_INFO_GUID;
This record type provides extensibility by preﬁxing further data ﬁelds in the record with a GUID which identiﬁes the
format.
36.4.9 EFI_USER_INFO_FAR_RECORD
Summary
Indicates how close of a match the ﬁngerprint must be in order to be considered a match.
Prototype
#define EFI_USER_INFO_FAR_RECORD 0x0C
typedef UINT8 EFI_USER_INFO_FAR;
This record speciﬁes how accurate the ﬁngerprint template match must be in order to be considered a match, as a per-
centage from 0 (no match) to 100 (perfect match). The accuracy may be for all ﬁngerprint sensors ( EFI_USER_INFO .
Credential is zero) or for a particular ﬁngerprint sensor ( EFI_USER_INFO .Credential is non-zero).
Access:
Exclusive: No
Modify: Only with user-enrollment permissions.
Visibility: Public
36.4.10 EFI_USER_INFO_IDENTIFIER_RECORD
Summary
Provides a unique non-volatile user identiﬁer for each enrolled user.
Prototype
#define EFI_USER_INFO_IDENTIFIER_RECORD 0x05
typedef UINT8 EFI_USER_INFO_IDENTIFIER[16];
The user identiﬁer is unique to each enrolled user and non-volatile. Each user proﬁle must have exactly one of these
user information records installed. The format of the value is not speciﬁed.
Access
Exclusive: Yes
36.4. User Information 1736Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

Access:
Summary
Prototype
Access
Visibility: Public.
36.4.11 EFI_USER_INFO_IDENTITY_POLICY_RECORD
Summary
Provides the expression which determines which credentials are required to assert user identity.
Prototype
#define EFI_USER_INFO_IDENTITY_POLICY_RECORD 0x0F
} EFI_USER_INFO_IDENTITY_POLICY;
Type Speciﬁes either an operator or a data item. See EFI_USER_INFO_IDENTITY_x in “Related Deﬁnitions” below.
Length The length of this block, in bytes, including this header.
The user identity policy is an expression mad3e up of operators and data items. If the expression evaluates to TRUE,
then this user proﬁle can be selected as the current proﬁle. If the expression evaluates to FALSE, then this user proﬁle
cannot be selected as the current proﬁle.
Data items are pushed onto an expression stack. Operators pop items off of the expression stack, perform an operator
and push the results back.
NOTE :If there is no user proﬁle, then FALSE is assumed .
Access
#define EFI_USER_INFO_IDENTITY_FALSE 0x00
#define EFI_USER_INFO_IDENTITY_TRUE 0x01
#define EFI_USER_INFO_IDENTITY_CREDENTIAL_TYPE 0x02
#define EFI_USER_INFO_IDENTITY_CREDENTIAL_PROVIDER 0x03
#define EFI_USER_INFO_IDENTITY_NOT 0x10
#define EFI_USER_INFO_IDENTITY_AND 0x11
#define EFI_USER_INFO_IDENTITY_OR 0x12
Type Name Description
EFI_USER_INFO_IDENTITY_FALSE Push FALSE on to the expression stack.
EFI_USER_INFO_IDENTITY_TRUE Push TRUE on to the expression stack.
36.4. User Information 1737Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 36.17 – continued from previous page
EFI_USER_INFO_IDENTITY_CREDENTIAL_TYPE If a credential provider with the speci-
ﬁed class asserts the user’s identity, push
TRUE . Otherwise push FALSE . The
EFI_USER_INFO_IDENTITY_POLICY
structure is followed immediately by a
GUID.
EFI_USER_INFO_IDENTITY_CREDENTIAL_PROVIDER If a credential provider with the speciﬁed
provider identiﬁer asserts the user’s identity,
push TRUE . Otherwise, push FALSE . The
GUID.
EFI_USER_INFO_IDENTITY_NOT Pop a boolean off the stack. If TRUE, then
push FALSE . IfFALSE, then push TRUE .
EFI_USER_INFO_IDENTITY_AND Pop two Booleans off the stack. If both are
TRUE, then push TRUE . Otherwise push
FALSE
EFI_USER_INFO_IDENTITY_OR Pop two Booleans off the stack. If either is
FALSE .
36.4.12 EFI_USER_INFO_NAME_RECORD
Summary
Provide the user’s name for the enrolled user.
Prototype
#define EFI_USER_INFO_NAME_RECORD 0x01
typedef CHAR16 *EFI_USER_INFO_NAME;
The user’s name is a NULL -terminated string.
Access
36.4.13 EFI_USER_INFO_PKCS11_RECORD
Summary
Provides PKCS#11 credential information from a smart card.
Prototype
#define EFI_USER_INFO_PKCS11_RECORD 0x0A
36.4. User Information 1738Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.4.14 EFI_USER_INFO_RETRY_RECORD
Summary
Indicates how many attempts the user has to with a particular credential before the system prevents further attempts.
Prototype
#define EFI_USER_INFO_RETRY_RECORD 0x0D
typedef UINT8 EFI_USER_INFO_RETRY;
This record indicates the number of times the user may fail identiﬁcation with all credential providers (
EFI_USER_INFO .Credential is zero) or a particular credential provider ( EFI_USER_INFO .Credential is non-zero).
Access:
36.4.15 EFI_USER_INFO_USAGE_DATE_RECORD
Summary
Provides the date and time when the user proﬁle was selected.
Prototype
#define EFI_USER_INFO_USAGE_DATE_RECORD 0x03
typedef EFI_TIME EFI_USER_INFO_USAGE_DATE;
The optional record describing the date and time when the user proﬁle was last selected. Type EFI_TIME is deﬁned
inGetTime() in this speciﬁcation.
36.4.16 EFI_USER_INFO_USAGE_COUNT_RECORD
Summary
Provides the number of times that the user proﬁle has been selected.
Prototype
#define EFI_USER_INFO_USAGE_COUNT 0x04
typedef UINT64 EFI_USER_INFO_USAGE_COUNT;
The optional record describing the number of times that the user proﬁle was selected.
36.4. User Information 1739Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
36.5 User Information Table
Summary
A collection of EFI_USER_INFO records, preﬁxed with this header.
Prototype
} EFI_USER_INFO_TABLE;
Members
Size Total size of the user information table, in bytes.
This header is followed by a series of records. Each record is preﬁxed by the EFI_USER_INFO structure. The total
size of this header and all records is equal to Size.
36.5. User Information Table 1740CHAPTER
THIRTYSEVEN
SECURE TECHNOLOGIES
37.1 Hash Overview
For the purposes of this speciﬁcation, a hash function takes a variable length input and generates a ﬁxed length hash
value. In general, hash functions are collision-resistant, which means that it is infeasible to ﬁnd two distinct inputs
which produce the same hash value. Hash functions are generally one-way which means that it is infeasible to ﬁnd an
input based on the output hash value.
This speciﬁcation describes a protocol which allows a driver to produce a protocol which supports zero or more hash
functions.
37.1.1 Hash References
The following references deﬁne the standard means of creating the hashes used in this speciﬁcation:
Secure Hash Standard (SHS) (FIPS PUB 180-3), National Institute of Standards and Technology (October 2008).
For more information
• see “Links to UEFI-Related Documents” at http://ueﬁ.org/ueﬁ under the heading “Archived FIPS publication”.
• see “Links to UEFI-Related Documents” at http://ueﬁ.org/ueﬁ under the heading “MD5 Message-Digest Algo-
rithm”. EFI Hash Protocols
37.1.1.1 EFI_HASH_SERVICE_BINDING_PROTOCOL
Summary
The EFI Hash Service Binding Protocol is used to locate hashing services support provided by a driver and create and
destroy instances of the EFI Hash Protocol so that a multiple drivers can use the underlying hashing services.
The EFI Service Binding Protocol that is deﬁned in EFI Services Binding deﬁnes the generic Service Binding Protocol
functions. This section discusses the details that are speciﬁc to the EFI Hash Protocol.
GUID
#define EFI_HASH_SERVICE_BINDING_PROTOCOL_GUID \
{0x42881c98,0xa4f3,0x44b0,\
{0xa3,0x9d,0xdf,0xa1,0x86,0x67,0xd8,0xcd}}
An application (or driver) that requires hashing services can use one of the protocol handler services, such as BS-
>LocateHandleBuffer(), to search for devices that publish an EFI Hash Service Binding Protocol.
1741Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
After a successful call to the EFI_HASH_SERVICE_BINDING_PROTOCOL.CreateChild() function, the child EFI
Hash Protocol driver instance is ready for use. The instance of EFI_HASH_PROTOCOL must be obtained by perform-
ingHandleProtocol() against the handle returned by CreateChild(). Use of other methods, such as LocateHandle(),
Once obtained, the driver may use the EFI_HASH_PROTOCOL instance for any number of non-overlapping hash
operations. Overlapping hash operations require an additional call to EFI_HASH_SERVICE_BINDING_PROTOCOL.
CreateChild() for a new instance.
Before a driver or application terminates execution, every successful call to the
EFI_HASH_SERVICE_BINDING_PROTOCOL.CreateChild() function must be matched with a call to the
EFI_HASH_SERVICE_BINDING_PROTOCOL.DestroyChild() function.
37.1.1.2 EFI_HASH_PROTOCOL
Summary
This protocol describes standard hashing functions.
GUID
#define EFI_HASH_PROTOCOL_GUID \
{0xc5184932,0xdba5,0x46db,\
{0xa5,0xba,0xcc,0x0b,0xda,0x9c,0x14,0x35}}
typedef _EFI_HASH_PROTOCOL {
EFI_HASH_GET_HASH_SIZE GetHashSize;
EFI_HASH_HASH Hash;
} EFI_HASH_PROTOCOL;
GetHashSize Return the size of a speciﬁc type of resulting hash.
Hash Create a hash for the speciﬁed message.
This protocol allows creating a hash of an arbitrary message digest using one or more hash algorithms. The GetH-
ashSize returns the expected size of the hash for a particular algorithm and whether or not that algorithm is, in fact,
supported. The Hash actually creates a hash using the speciﬁed algorithm.
None.
37.1.1.3 EFI_HASH_PROTOCOL.GetHashSize()
Summary
Returns the size of the hash which results from a speciﬁc algorithm.
Prototype
EFIAPI
GetHashSize(
37.1. Hash Overview 1742Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN CONST EFI_HASH_PROTOCOL *This,
IN CONST EFI_GUID *HashAlgorithm,
OUT UINTN *HashSize
);
This Points to this instance of EFI_HASH_PROTOCOL.

None.
Summary
Prototype
EFIAPI
);
HashAlgorithm Points to the EFI_GUID which identiﬁes the algorithm to use. See EFI Hash Algorithms .
HashSize Holds the returned size of the algorithm’s hash.
This function returns the size of the hash which will be produced by the speciﬁed algorithm.
None
EFI_SUCCESS Hash size returned successfully.
EFI_INV ALID_PARAMETER HashSize isNULL orHashAlgorithm isNULL.
EFI_UNSUPPORTED The algorithm speciﬁed by HashAlgorithm is not supported by this driver.
37.1.1.4 EFI_HASH_PROTOCOL.Hash()
Summary
Creates a hash for the speciﬁed message text.
Prototype
EFIAPI
Hash(
IN BOOLEAN Extend,
IN CONST UINT8 *Message,
IN UINT64 MessageSize,
IN OUT EFI_HASH_OUTPUT *Hash
);
Extend Speciﬁes whether to create a new hash ( FALSE ) or extend the speciﬁed existing hash ( TRUE ).
Message Points to the start of the message.
MessageSize The size of Message, in bytes. Must be integer multiple of block size.
Hash On input, if Extend isTRUE, then this parameter holds a pointer to a pointer to an array containing the hash to
extend. If Extend isFALSE, then this parameter holds a pointer to a pointer to a caller-allocated array that will
37.1. Hash Overview 1743Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
receive the result of the hash computation. On output (regardless of the value of Extend ), the array will contain
the result of the hash computation.
This function creates the hash of the speciﬁed message text based on the speciﬁed algorithm HashAlgorithm and copies
the result to the caller-provided buffer Hash. IfExtend isTRUE, then the hash speciﬁed on input by Hash is extended.
IfExtend isFALSE, then the starting hash value will be that speciﬁed by the algorithm.
NOTE :For the all algorithms used with EFI_HASH_PROTOCOL, the following apply:
• The EFI_HASH_PROTOCOL.Hash() function does not perform padding of message data for these algorithms.
Hence, MessageSize shall always be an integer multiple of the HashAlgorithm block size, and the ﬁnal supplied
Message in a sequence of invocations shall contain caller-provided padding. This will ensure that the ﬁnal Hash
output will be the correct hash of the provided message(s).
• The result of a Hash() call for one of these algorithms when the caller does not supply message data whose
length is an integer multiple of the algorithm’s block size is a returned error.
• The EFI_HASH_OUTPUT options for these two algorithms shall be EFI_SHA1_HASH and
EFI_SHA256_HASH, respectively.
• Callers using these algorithms may consult the aforementioned Secure Hash Standard for details on how to
perform proper padding required by standard prior to ﬁnal invocation.
EFI_HASH_OUTPUT
EFI_SUCCESS Hash returned successfully.
EFI_INV ALID_PARAMETER Message orHash,HashAlgorithm i s NULL or MessageSize is 0. Message-
Sizeis not an integer multiple of block size.
Includes HashAlgorithm being passed as a null error.
EFI_UNSUPPORTED Extend isTRUE and the algorithm doesn’t support extending the hash.
37.1.2 Other Code Deﬁnitions
EFI_SHA512HASH, EFI_MD5_HASH
Summary
Data structure which holds the result of the hash.
Prototype
typedef UINT8 EFI_MD5_HASH[16];
typedef UINT8 EFI_SHA1_HASH[20];
typedef UINT8 EFI_SHA224_HASH[28];
typedef UINT8 EFI_SHA256_HASH[32];
typedef UINT8 EFI_SHA384_HASH[48];
typedef UINT8 EFI_SHA512_HASH[64];
typedef union _EFI_HASH_OUTPUT {
EFI_MD5_HASH *Md5Hash;
EFI_SHA1_HASH *Sha1Hash;
37.1. Hash Overview 1744Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SHA224_HASH *Sha224Hash;
EFI_SHA256_HASH *Sha256Hash;
EFI_SHA384_HASH *Sha384Hash;
EFI_SHA512_HASH *Sha512Hash;
} EFI_HASH_OUTPUT;
These prototypes describe the expected hash output values from the Hash function of the EFI_HASH_PROTOCOL.
None
37.1.2.2 EFI Hash Algorithms
The following table gives the EFI_GUID for standard hash algorithms and the corresponding ASN.1 OID (Object
Identiﬁer):
NOTE :Use of the following algorithms with EFI_HASH_PROTOCOL is deprecated .
• EFI_HASH_ALGORITHM_SHA1_GUID
• EFI_HASH_ALGORITHM_SHA224_GUID
• EFI_HASH_ALGORITHM_SHA256_GUID
• EFI_HASH_ALGORITHM_SHA384_GUID
• EFI_HASH_ALGORITHM_SHA512_GUID
• EFI_HASH_ALGORTIHM_MD5_GUID
Table 37.1: EFI Hash Algorithms
Algorithm EFI_GUID OID
SHA-1 (No
padding done
by imple-
mentation)#deﬁne EFI_HASH_ALGO
RITHM_SHA1_NOPAD_GUID {0x24c5dc2f,
0x53e2, 0x40ca, {0x9e, 0xd6, 0xa5, 0xd9,
0xa4, 0x9f, 0x46, 0x3b}}id-sha1 OBJECT IDENTIFIER ::= { iso(1) ide
ntiﬁed-organization( 3) oiw(14) secsig(3) algo-
rithms(2) 26 }
SHA-256
(No padding
done by
implementa-
tion)#deﬁne EFI_HASH_ALGORI
THM_SHA256_NOPAD_GUID {0x8628752a,
0x6cb7, 0x4814, {0x96, 0xfc, 0x24, 0xa8, 0x15,
0xac, 0x22, 0x26}}id-sha256 OBJECT IDENTIFIER ::= { joint-
iso-itu-t (2) country (16) us (840) organiza-
tion (1) gov (101) csor (3) nistalgorithm (4)
hashalgs (2) 1}
NOTE : For the EFI_HASH_ALGORITHM_SHA1_NOPAD_GUID and the
EFI_HASH_ALGORITHM_SHA256_NOPAD_GUID, the following apply :
length is an integer multiple of the algorithm’s block size is undeﬁned.
37.1. Hash Overview 1745Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
perform proper padding.
37.2 Hash2 Protocols
37.2.1 EFI Hash2 Service Binding Protocol
37.2.1.1 EFI_HASH2_SERVICE_BINDING_PROTOCOL
Summary
The EFI Hash2 Service Binding Protocol is used to locate EFI_HASH2_PROTOCOL hashing services support pro-
vided by a driver and create and destroy instances of the EFI_HASH2_PROTOCOL Protocol so that a multiple drivers
can use the underlying hashing services.
GUID
#define EFI_HASH2_SERVICE_BINDING_PROTOCOL_GUID \
{0xda836f8d, 0x217f, 0x4ca0, 0x99, 0xc2, 0x1c, \
0xa4, 0xe1, 0x60, 0x77, 0xea}
>LocateHandleBuffer(), to search for devices that publish an EFI_HASH2_SERVICE_BINDING_PROTOCOL.
After a successful call to the EFI_HASH2_SERVICE_BINDING_PROTOCOL member CreateChild() function,
the child instance of EFI_HASH2_PROTOCOL Protocol driver instance is ready for use. The instance of
EFI_HASH2_PROTOCOL must be obtained by performing HandleProtocol() against the handle returned by Cre-
ateChild(). Use of other methods, such as LocateHandle() is not supported.
Once obtained, the driver may use the EFI_HASH2_PROTOCOL instance for any number of non-overlapping hash
Before a driver or application using the instance terminates execution, every successful call to the
37.2.2 EFI Hash2 Protocol
37.2.2.1 EFI_HASH2_PROTOCOL
Summary
This protocol describes hashing functions for which the algorithm-required message padding and ﬁnalization
are performed by the supporting driver. In previous versions of the speciﬁcation, the algorithms supported by
EFI_HASH2_PROTOCOL were also available for use with EFI_HASH_PROTOCOL but this usage has been dep-
recated.
GUID
37.2. Hash2 Protocols 1746Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define EFI_HASH2_PROTOCOL_GUID \
{
0x55b1d734, 0xc5e1, 0x49db, 0x96, 0x47, 0xb1, 0x6a, \
0xfb, 0xe, 0x30, 0x5b}
typedef _EFI_HASH2_PROTOCOL {
EFI_HASH2_GET_HASH_SIZE GetHashSize;
EFI_HASH2_HASH Hash;
EFI_HASH2_HASH_INIT HashInit;
EFI_HASH2_HASH_UPDATE HashUpdate;
EFI_HASH2_HASH_FINAL HashFinal;

Summary
recated.
GUID
{
} EFI_HASH2_PROTOCOL;
GetHashSize Return the result size of a speciﬁc type of resulting hash.
Hash Create a ﬁnal non-extendable hash for a single message block in a single call.
HashInit Initializes an extendable multi-part hash calculation
HashUpdate Continues a hash in progress by supplying the ﬁrst or next sequential portion of the message text
HashFinal Finalizes a hash in progress by padding as required by algorithm and returning the hash output.
ashSize() function returns the expected size of the hash for a supported algorithm and an error if that algorithm is not
supported. The Hash() function creates a ﬁnal, non-extendable, hash of a single message block using the speciﬁed
algorithm. The three functions HashInit(), HashUpdate(), HashFinal(), generates the hash of a multi-part message,
with input composed of one or more message pieces.
For a speciﬁc handle representing an instance of EFI_HASH2_PROTOCOL, ifHash() is called after a call to HashInit()
and prior to the matching call to HashFinal() , the multi-part hash started by HashInit() will be canceled and calls to
HashUpdate() orHashFinal() will return an error status unless proceeded by a new call to HashInit().
NOTE :Algorithms EFI_HASH_ALGORITHM_SHA1_NOPAD andEFI_HASH_ALGORITHM_SHA256_NOPAD_GUID
are not compatible with EFI_HASH2_PROTOCOL and will return EFI_UNSUPPORTED if used with any
EFI_HASH2_PROTOCOL function.
None
NOTE :The following hash function invocations will produce identical hash results for all supported
EFI_HASH2_PROTOCOL algorithms. The data in quotes is the message .
Table 37.2: Identical Hash Results
Hash(“ABCDEF”) HashInit() HashInit ()
HashUpdate(“ABCDEF”) HashUpdate (“ABC”)
HashFinal() HashUpdate (“DE”)
HashUpdate (“F”)
HashFinal ()
37.2. Hash2 Protocols 1747Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. 37.1: Hash workﬂow
37.2. Hash2 Protocols 1748Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.2.2.2 EFI_HASH2_PROTOCOL.GetHashSize()
Summary
Prototype
EFIAPI
IN CONST EFI_HASH2_PROTOCOL *This,
);
This Points to this instance of EFI_HASH2_PROTOCOL.
HashAlgorithm Points to the EFI_GUID which identiﬁes the algorithm to use. See Other Code Deﬁnitions .
This function returns the size of the hash result buffer which will be produced by the speciﬁed algorithm.
None
EFI_INV ALID_PARAMETER This orHashSize isNULL
EFI_UNSUPPORTED The algorithm speciﬁed by HashAlgorithm is not supported by this driver
or,HashAlgorithm isNULL .
37.2.2.3 EFI_HASH2_PROTOCOL.Hash()
Summary
Creates a hash for a single message text. The hash is not extendable. The output is ﬁnal with any algorithm-required
padding added by the function.
Prototype
EFIAPI
Hash(
IN UINTN MessageSize,
IN OUT EFI_HASH2_OUTPUT *Hash
);
37.2. Hash2 Protocols 1749Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
HashAlgorithm Points to the EFI_GUID which identiﬁes the algorithm to use. See Table, Algorithms that may be
used with EFI_HASH2_PROTOCOL .
MessageSize The size of Message, in bytes.
Hash On input, points to a caller-allocated buffer of the size returned by GetHashSize() for the speciﬁed HashAlgo-
rithm. On output, the buffer holds the resulting hash computed from the message.
This function creates the hash of speciﬁed single block message text based on the speciﬁed algorithm HashAlgorithm
and copies the result to the caller-provided buffer Hash. The resulting hash cannot be extended. All padding required
byHashAlgorithm is added by the implementation.
EFI_HASH2_OUTPUT
EFI_INV ALID_PARAMETER This, orHash isNULL .
orHashAlgorithm isNull.
EFI_OUT_OF_RESOURCES Some resource required by the function is not available or MessageSize is
greater than platform maximum.
37.2.2.4 EFI_HASH2_PROTOCOL.HashInit()
Summary
This function must be called to initialize a digest calculation to be subsequently performed using the
EFI_HASH2_PROTOCOL functions HashUpdate() andHashFinal().
Prototype
EFIAPI
HashInit(
);
This Points to instance of EFI_HASH2_PROTOCOL.
used with EFI_HASH2_PROTOCOL
This function
37.2. Hash2 Protocols 1750Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS Initialized successfully.
EFI_UNSUPPORTED The algorithm speciﬁed by HashAlgorithm is not supported by this function
EFI_OUT_OF_RESOURCES Process failed due to lack of required resource.
EFI_ALREADY_STARTED This function is called when the operation in progress is still in processing
Hash(), orHashInit() is already called before and not terminated by Hash-
Final() yet on the same instance.
37.2.2.5 EFI_HASH2_PROTOCOL.HashUpdate()
Summary
Updates the hash of a computation in progress by adding a message text.
Prototype
EFIAPI
HashUpdate(
IN UINTN MessageSize
);
This function extends the hash of ongoing hash operation with the supplied message text. This function should be
called one or more times with portions of the total message text to be hashed.. A zero-length message input will return
EFI_SUCCESS and has no impacts on the ongoing hash instance.
EFI_SUCCESS Digest in progress updated successfully.
EFI_INV ALID_PARAMETER This orHash isNULL .
EFI_NOT_READY This call was not preceded by a valid call to HashInit() , or the operation
in progress was terminated by a call to Hash() orHashFinal() on the same
instance.
37.2. Hash2 Protocols 1751Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.2.2.6 EFI_HASH2_PROTOCOL.HashFinal()
Summary
Finalizes a hash operation in progress and returns calculation result. The output is ﬁnal with any necessary padding
added by the function. The hash may not be further updated or extended after HashFinal().
Prototype
EFIAPI
HashFinal(
);
Hash On input, points to a caller-allocated buffer of the size returned by GetHashSize() for the speciﬁed HashAl-
gorithm speciﬁed in preceding HashInit(). On output, the buffer holds the resulting hash computed from the
message.
This function ﬁnalizes the hash of a hash operation in progress. The resulting ﬁnal hash cannot be extended.
EFI_INV ALID_PARAMETER This orHash isNULL
EFI_NOT_READY This call was not preceded by a valid call to HashInit() and at least one
call to HashUpdate(), or the operation in progress was canceled by a call to
Hash() on the same instance.
Table 37.8: Algorithms that may be used with EFI_HASH2_PROTOCOL
EFI_GUID OID
SHA-1 #deﬁne EFI_HASH _ALGORITHM_SHA1_GUID
{0x2ae9d80f, 0x3fb2, 0x4095, { 0xb7, 0xb1, 0xe9,
0x31, 0x57, 0xb9, 0x46, 0xb6}}id-sha1 OBJECT IDENTIFIER ::= { iso(1)
identiﬁed- organization(3) oiw(14) secsig(3)
algorithms(2) 26 }
SHA-
224#deﬁne EFI_HASH _ALGORITHM_SHA224_GUI
D { 0x8df01a06, 0x9bd5, 0x4bf7, { 0xb0, 0x21, 0xdb,
0x4f, 0xd9, 0xcc, 0xf4, 0x5b } }
SHA-
256#deﬁne EFI_HASH _ALGORITHM_SHA256_GUI
D { 0x51aa59de, 0xfdf2, 0x4ea3, { 0xbc, 0x63, 0x87,
0x5f, 0xb7, 0x84, 0x2e, 0xe9 } }id-sha256 OBJECT IDENTIFIER ::= { joint-
SHA-
384#deﬁne EFI_HASH _ALGORITHM_SHA384_GUI
D { 0xefa96432, 0xde33, 0x4dd2, { 0xae, 0xe6, 0x32,
0x8c, 0x33, 0xdf, 0x77, 0x7a } }id-sha384 OBJECT IDENTIFIER ::= { joint-

SHA-
SHA-
SHA-
hashalgs (2) 2}
37.2. Hash2 Protocols 1752Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 37.8 – continued from previous page
SHA-
512#deﬁne EFI_HASH _ALGORITHM_SHA512_GUI
D { 0xcaa4381e, 0x750c, 0x4770, { 0xb8, 0x70,
0x7a, 0x23, 0xb4, 0xe4, 0x21, 0x30 } }id-sha512 OBJECT IDENTIFIER ::= { joint-
hashalgs (2) 3}
MD5 #deﬁne EFI_HA SH_ALGORTIHM_MD5_GUID {
0xaf7c79c, 0x65b5, 0x4319, { 0xb0, 0xae, 0x44,
0xec, 0x48, 0x4e, 0x4a, 0xd7 } }id-md5 OBJECT IDENTIFIER ::= { iso (1)
member-body (2) us (840) rsadsi (113549) di-
gestAlgorithm (2) 5}
NOTE :SHA-1 and MD5 are included for backwards compatibility. New driver implementations are encouraged to
consider stronger algorithms.
37.2.3 Other Code Deﬁnitions
37.2.3.1 EFI_HASH2_OUTPUT
Summary
Data structure which holds the result of the hash operation from EFI_HASH2_PROTOCOL hash operations.
Prototype
typedef UINT8 EFI_MD5_HASH2[16];
typedef UINT8 EFI_SHA1_HASH2[20];
typedef UINT8 EFI_SHA224_HASH2[28];
typedef UINT8 EFI_SHA256_HASH2[32];
typedef UINT8 EFI_SHA384_HASH2[48];
typedef UINT8 EFI_SHA512_HASH2[64];
typedef union _EFI_HASH2_OUTPUT {
EFI_MD5_HASH2 Md5Hash;
EFI_SHA1_HASH2 Sha1Hash;
EFI_SHA224_HASH2 Sha224Hash;
EFI_SHA256_HASH2 Sha256Hash;
EFI_SHA384_HASH2 Sha384Hash;
EFI_SHA512_HASH2 Sha512Hash;
} EFI_HASH2_OUTPUT;
These prototypes describe the expected hash output values from the hashing functions of the
EFI_HASH2_PROTOCOL .
None
37.3 Key Management Service
37.3.1 EFI_KEY_MANAGEMENT_SERVICE_PROTOCOL
Summary
The Key Management Service (KMS) protocol provides services to generate, store, retrieve, and manage cryptographic
keys. The intention is to specify a simple generic protocol that could be used for many implementations.
The management keys have a simple construct - they consist of key identiﬁer and key data, both of variable size.
37.3. Key Management Service 1753Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
A driver implementing the protocol may need to provide basic key service that consists of a key store and cryptographic
key generation capability. It may connect to an external key server over the network, or to a Hardware Security Module
(HSM) attached to the system it runs on, or anything else that is capable of providing the key management service.
Authentication and access control is not addressed by this protocol. It is assumed it is addressed at the system level
and done by the driver implementing the protocol, if applicable to the implementation.
GUID
#define EFI_KMS_PROTOCOL_GUID \
{0xEC3A978D,0x7C4E, 0x48FA,\
{0x9A,0xBE,0x6A,0xD9,0x1C,0xC8,0xF8,0x11}}
#define EFI_KMS_DATA_TYPE_NONE 0
#define EFI_KMS_DATA_TYPE_BINARY 1
#define EFI_KMS_DATA_TYPE_ASCII 2
#define EFI_KMS_DATA_TYPE_UNICODE 4
#define EFI_KMS_DATA_TYPE_UTF8 8
Where appropriate, EFI_KMS_DATA_TYPE values may be combined using a bitwise ‘ OR’ operation to indicate
support for multiple data types.
typedef struct _EFI_KMS_SERVICE_PROTOCOL {
EFI_KMS_GET_SERVICE_STATUS GetServiceStatus;
EFI_KMS_REGISTER_CLIENT RegisterClient;
EFI_KMS_CREATE_KEY CreateKey;
EFI_KMS_GET_KEY GetKey;
EFI_KMS_ADD_KEY AddKey;
EFI_KMS_DELETE_KEY DeleteKey;
EFI_KMS_GET_KEY_ATTRIBUTES GetKeyAttributes;
EFI_KMS_ADD_KEY_ATTRIBUTES AddKeyAttributes;
EFI_KMS_DELETE_KEY_ATTRIBUTES DeleteKeyAttributes;
EFI_KMS_GET_KEY_BY_ATTRIBUTES GetKeyByAttributes;
UINT32 ProtocolVersion;
EFI_GUID ServiceId;
CHAR16 *ServiceName;
UINT32 ServiceVersion;
BOOLEAN ServiceAvailable;
BOOLEAN ClientIdSupported;
BOOLEAN ClientIdRequired;
UINT16 ClientIdMaxSize;
UINT8 ClientNameStringTypes;
BOOLEAN ClientNameRequired;
UINT16 ClientNameMaxCount;
BOOLEAN ClientDataSupported;
UINTN ClientDataMaxSize;
BOOLEAN KeyIdVariableLenSupported;
UINTN KeyIdMaxSize;
UINTN KeyFormatsCount;
EFI_GUID *KeyFormats;
BOOLEAN KeyAttributesSupported;
UINT8 KeyAttributeIdStringTypes;
UINT16 KeyAttributeIdMaxCount;
UINTN KeyAttributesCount;
EFI_KMS_KEY_ATTRIBUTE *KeyAttributes;
} EFI_KMS_PROTOCOL;
37.3. Key Management Service 1754Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetServiceStatus Get the current status of the key management service. If the implementation has not yet connected
to the KMS, then a call to this function will initiate a connection. This is the only function that is valid for use
prior to the service being marked available.
RegisterClient Register a speciﬁc client with the KMS.
CreateKey Request the generation of a new key and retrieve it.
GetKey Retrieve an existing key.
AddKey Add a local key to the KMS database. If there is an existing key with this key identiﬁer in the KMS database,
it will be replaced with the new key.
DeleteKey Delete an existing key from the KMS database.
AddKeyAttributes Add attributes to an existing key in the KMS database.
GetKeyAttributes Get attributes for an existing key in the KMS database.
DeleteKeyAttributes Delete attributes for an existing key in the KMS database.
GetKeyByAttributes Get existing key(s) with the speciﬁed attributes.
ProtocolVersion The version of this EFI_KMS_PROTOCOL structure. This must be set to 0x00020040 for the initial
version of this protocol.
ServiceId Optional GUID used to identify a speciﬁc KMS. This GUID may be supplied by the provider, by the
implementation, or may be null. If it is null, then the*ServiceName* must not be null.
ServiceName Optional pointer to a unicode string which may be used to identify the KMS or provide other informa-
tion about the supplier.
ServiceVersion Optional 32-bit value which may be used to indicate the version of the KMS provided by the supplier.
ServiceAvailable TRUE if and only if the service is active and available for use. To avoid unnecessary delays
in POST, this protocol may be installed without connecting to the service. In this case, the ﬁrst call to the
GetServiceStatus() function will cause the implementation to connect to the supported service and mark it as
available. The capabilities of this service as deﬁned in the remainder of this protocol are not guaranteed to be
valid until the service has been marked available.
FALSE otherwise.
ClientIdSupported TRUE if and only if the service supports client identiﬁers. Client identiﬁers may be used for
auditing, access control or any other purpose speciﬁc to the implementation.
ClientIdRequired TRUE if and only if the service requires a client identiﬁer in order to process key requests.
ClientIdMaxSize The maximum size in bytes for the client identiﬁer.
ClientNameStringTypes The client name string type(s) supported by the KMS service. If client names are not
supported, this ﬁeld will be set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it will be set to the inclusive
‘OR’ of all client name formats supported. Client names may be used for auditing, access control or any other
purpose speciﬁc to the implementation.
ClientNameRequired TRUE if and only if the KMS service requires a client name to be supplied to the service.
ClientNameMaxCount The maximum number of characters allowed for the client name.
37.3. Key Management Service 1755Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ClientDataSupported TRUE if and only if the service supports arbitrary client data requests. The use of client
data requires the caller to have speciﬁc knowledge of the individual KMS service and should be used only if
absolutely necessary.
ClientDataMaxSize The maximum size in bytes for the client data. If the maximum data size is not speciﬁed by the
KMS or it is not known, then this ﬁeld must be ﬁlled with all ones.
KeyIdVariableLenSupported TRUE if variable length key identiﬁers are supported.
FALSE if a ﬁxed length key identiﬁer is supported.
KeyIdMaxLen If KeyIdVariableLenSupported is TRUE , this is the maximum supported key identiﬁer length in
bytes. Otherwise this is the ﬁxed length of key identiﬁer supported. Key ids shorter than the ﬁxed length will be
padded on the right with blanks.
KeyFormatsCount The number of key format/size GUIDs returned in the KeyFormats ﬁeld.
KeyFormats A pointer to an array of EFI_GUID values which specify key formats/sizes supported by this KMS. Each
format/size pair will be speciﬁed by a separate EFI_GUID . At least one key format/size must be supported. All
formats/sizes with the same hashing algorithm must be contiguous in the array, and for each hashing algorithm,
the key sizes must be in ascending order. See “Related Deﬁnitions” for GUIDs which identify supported key
formats/sizes.
‘This list of GUIDs supported by the KMS is not required to be exhaustive, and the KMS may provide support for
additional key formats/sizes. Users may request key information using an arbitrary GUID, but any GUID not rec-

ognized by the implementation or not supported by the KMS will return an error code of EFI_UNSUPPORTED .
KeyAttributesSupported TRUE if key attributes are supported.
FALSE if key attributes are not supported.
KeyAttributeIdStringTypes The key attribute identiﬁer string type(s) supported by the KMS service. If key at-
tributes are not supported, this ﬁeld will be set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it will be set to
the inclusive ‘OR’ of all key attribute identiﬁer string types supported. EFI_KMS_DATA_TYPE_BINARY is not
valid for this ﬁeld.
KeyAttributeIdMaxCount The maximum number of characters allowed for the client name.
KeyAttributesCount The number of predeﬁned KeyAttributes structures returned in the KeyAttributes parameter. If
the KMS does not support predeﬁned key attributes, or if it does not provide a method to obtain predeﬁned key
attributes data, then this ﬁeld must be zero.
KeyAttributes A pointer to an array of KeyAttributes structures which contains the predeﬁned attributes supported by
this KMS. Each structure must contain a valid key attribute identiﬁer and should provide any other information
as appropriate for the attribute, including a default value if one exists. This variable must be set to NULL if
theKeyAttributesCount variable is zero. It must point to a valid buffer if the KeyAttributesCount variable is
non-zero.
This list of predeﬁned attributes is not required to be exhaustive, and the KMS may provide additional predeﬁned
attributes not enumerated in this list. The implementation does not distinguish between predeﬁned and used
deﬁned attributes, and therefore, predeﬁned attributes not enumerated will still be processed to the KMS.
Functions deﬁned for this protocol typically require the caller to provide information about the client, the keys
to be processed, and/or attributes of the keys to be processed. Four structures, EFI_KMS_CLIENT_INFO,
EFI_KMS_KEY_DESCRIPTOR, EFI_KMS_DYNAMIC_ATTRIBUTE, andEFI_KMS_KEY_ATTRIBUTE deﬁne the
information to be passed to these functions.
37.3. Key Management Service 1756Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT16 ClientIdSize;
VOID *ClientId;
UINT8 ClientNameType;
UINT8 ClientNameCount;
VOID *ClientName;
} EFI_KMS_CLIENT_INFO;
ClientIdSize The size in bytes for the client identiﬁer.
ClientId Pointer to a valid client identiﬁer.
ClientNameType The client name string type used by this client. The string type set here must be one of the string
types reported in the ClientNameStringTypes ﬁeld of the KMS protocol. If the KMS does not support client
names, this ﬁeld should be set to EFI_KMS_DATA_TYPE_NONE.
ClientNameCount The size in characters for the client name. This ﬁeld will be ignored if ClientNameStringType
is set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it must contain number of characters contained in the
ClientName ﬁeld.
ClientName Pointer to a client name. This ﬁeld will be ignored if ClientNameStringType is set to
EFI_KMS_DATA_TYPE_NONE. Otherwise, it must point to a valid string of the speciﬁed type.
The key formats recognized by the KMS protocol are deﬁned by an EFI_GUID which speciﬁes a (key-algorithm, key-
size) pair. The names of these GUIDs are in the format EFI_KMS_KEY_(key-algorithm)_(key-size)_GUID, where
the key-size is expressed in bits. The key formats recognized fall into three categories, generic (no algorithm), hash
algorithms, and encrypted algorithms.
Generic Key Data:
The following GUIDs deﬁne formats that contain generic key data of a speciﬁc size in bits, but which is not associated
with any speciﬁc key algorithm(s).
#define EFI_KMS_FORMAT_GENERIC_128_GUID \
{0xec8a3d69,0x6ddf,0x4108,\
{0x94,0x76,0x73,0x37,0xfc,0x52,0x21,0x36}}
#define EFI_KMS_FORMAT_GENERIC_160_GUID \
{0xa3b3e6f8,0xefca,0x4bc1,\
{0x88,0xfb,0xcb,0x87,0x33,0x9b,0x25,0x79}}
#define EFI_KMS_FORMAT_GENERIC_256_GUID \
{0x70f64793,0xc323,0x4261,\
{0xac,0x2c,0xd8,0x76,0xf2,0x7c,0x53,0x45}}
#define EFI_KMS_FORMAT_GENERIC_512_GUID \
{0x978fe043,0xd7af,0x422e,\
{0x8a,0x92,0x2b,0x48,0xe4,0x63,0xbd,0xe6}}
#define EFI_KMS_FORMAT_GENERIC_1024_GUID \
{0x43be0b44,0x874b,0x4ead,\
{0xb0,0x9c,0x24,0x1a,0x4f,0xbd,0x7e,0xb3}}
#define EFI_KMS_FORMAT_GENERIC_2048_GUID \
{0x40093f23,0x630c,0x4626,\
{0x9c,0x48,0x40,0x37,0x3b,0x19,0xcb,0xbe}}
#define EFI_KMS_FORMAT_GENERIC_3072_GUID \
{0xb9237513,0x6c44,0x4411,\
37.3. Key Management Service 1757Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
{0xa9,0x90,0x21,0xe5,0x56,0xe0,0x5a,0xde}}
#define EFI_KMS_FORMAT_GENERIC_DYNAMIC_GUID \
{0x2156e996, 0x66de, 0x4b27, \
{0x9c, 0xc9, 0xb0, 0x9f, 0xac, 0x4d, 0x2, 0xbe}}
The EFI_KMS_FORMAT_GENERIC_DYNAMIC_GUID is deﬁned for the key data with a size not de-
ﬁned by a certain key format GUID. The key value speciﬁed by this GUID is in format of structure
EFI_KMS_FORMAT_GENERIC_DYNAMIC.
UINT32 KeySize;
UINT8 KeyData[1];
} EFI_KMS_FORMAT_GENERIC_DYNAMIC;
KeySize Length in bytes of the KeyData.
KeyData The data of the key.
Hash Algorithm Key Data:
These GUIDS deﬁne key data formats that contain data generated by basic hash algorithms with no cryptographic
properties.
#define EFI_KMS_FORMAT_MD2_128_GUID \
{0x78be11c4,0xee44,0x4a22,\
{0x9f,0x05,0x03,0x85,0x2e,0xc5,0xc9,0x78}}
#define EFI_KMS_FORMAT_MDC2_128_GUID \
{0xf7ad60f8,0xefa8,0x44a3,\
{0x91,0x13,0x23,0x1f,0x39,0x9e,0xb4,0xc7}}
#define EFI_KMS_FORMAT_MD4_128_GUID \
{0xd1c17aa1,0xcac5,0x400f,0xbe,\
{0x17,0xe2,0xa2,0xae,0x06,0x67,0x7c}}
#define EFI_KMS_FORMAT_MDC4_128_GUID \
{0x3fa4f847,0xd8eb,0x4df4,\
{0xbd,0x49,0x10,0x3a,0x0a,0x84,0x7b,0xbc}}
#define EFI_KMS_FORMAT_MD5_128_GUID \
{0xdcbc3662,0x9cda,0x4b52,\
{0xa0,0x4c,0x82,0xeb,0x1d,0x23,0x48,0xc7}}
#define EFI_KMS_FORMAT_MD5SHA_128_GUID \
{0x1c178237,0x6897,0x459e,\
{0x9d,0x36,0x67,0xce,0x8e,0xf9,0x4f,0x76}}
#define EFI_KMS_FORMAT_SHA1_160_GUID \
{0x453c5e5a,0x482d,0x43f0,\
{0x87,0xc9,0x59,0x41,0xf3,0xa3,0x8a,0xc2}}
#define EFI_KMS_FORMAT_SHA256_256_GUID \
{0x6bb4f5cd,0x8022,0x448d,\
{0xbc,0x6d,0x77,0x1b,0xae,0x93,0x5f,0xc6}}
#define EFI_KMS_FORMAT_SHA512 512_GUID \
37.3. Key Management Service 1758Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
{0x2f240e12,0xe14d,0x475c,\
{0x83,0xb0,0xef,0xff,0x22,0xd7,0x7b,0xe7}}
Encryption Algorithm Key Data:
These GUIDs deﬁne key data formats that contain data generated by cryptographic key algorithms. There may or may
not be a separate data hashing algorithm associated with the key algorithm.
#define EFI_KMS_FORMAT_AESXTS_128_GUID \
{0x4776e33f,0xdb47,0x479a,\
{0xa2,0x5f,0xa1,0xcd,0x0a,0xfa,0xb3,0x8b}}
#define EFI_KMS_FORMAT_AESXTS_256_GUID \
{0xdc7e8613,0xc4bb,0x4db0,\
{0x84,0x62,0x13,0x51,0x13,0x57,0xab,0xe2}}
#define EFI_KMS_FORMAT_AESCBC_128_GUID \
{0xa0e8ee6a,0x0e92,0x44d4,\
{0x86,0x1b,0x0e,0xaa,0x4a,0xca,0x44,0xa2}}
#define EFI_KMS_FORMAT_AESCBC_256_GUID \
{0xd7e69789,0x1f68,0x45e8,\
{0x96,0xef,0x3b,0x64,0x07,0xa5,0xb2,0xdc}}
#define EFI_KMS_FORMAT_RSASHA1_1024_GUID \
{0x56417bed,0x6bbe,0x4882,\
{0x86,0xa0,0x3a,0xe8,0xbb,0x17,0xf8,0xf9}}
#define EFI_KMS_FORMAT_RSASHA1_2048_GUID \
{0xf66447d4,0x75a6,0x463e,\
{0xa8,0x19,0x07,0x7f,0x2d,0xda,0x05,0xe9}}
#define EFI_KMS_FORMAT_RSASHA256_2048_GUID \
{0xa477af13,0x877d,0x4060,
{0xba,0xa1,0x25,0xd1,0xbe,0xa0,0x8a,0xd3}}
#define EFI_KMS_FORMAT_RSASHA256_3072_GUID \
{0x4e1356c2,0xeed,0x463f,\
{0x81,0x47,0x99,0x33,0xab 0xdb,0xc7,0xd5}}
The encryption algorithms deﬁned above have the following properties
Table 37.9: Encryption Algorithm Properties
EFI_KMS_FORMAT Encryption Description Key Data Size Hash
Func-
tion
AESXTS_128 Symmetric encryption using XTS-
AES 128 bit keysKey data is a concatenation of
two ﬁelds of equal size for a to-
tal size of 256 bitsN/A
AESXTS_256 Symmetric encryption using block ci-
pher XTS-AES 256 bit keysKey data is a concatenation of
tal size of 512 bitsN/A
AESCBC_128 Symmetric encryption using block ci-
pher AES-CBC 128 bit keys128 bits N/A
37.3. Key Management Service 1759Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 37.9 – continued from previous page
AESCBC_256 Symmetric encryption using block ci-
pher AES-CBC 256 bit keys256 bits N/A
RSASHA1_1024 Asymmetric encryption using block
cipher RSA 1024 bit keys1024 bits SHA1
RSASHA1_2048 Asymmetric encryption using block
cipher RSA 2048 bit keys2048 bits SHA1
RSASHA256_2048 Asymmetric encryption using block
cipher RSA 2048 bit keys2048 bits SHA256
RSASHA256_3072 Asymmetric encryption using block
cipher RSA 3072 bit keys3072 bits SHA256
UINT8 KeyIdentifierSize;
VOID *KeyIdentifier;
EFI_GUID KeyFormat;
VOID *KeyValue;
EFI_STATUS KeyStatus;
} EFI_KMS_KEY_DESCRIPTOR;
KeyIdentiﬁerSize The size of the KeyIdentiﬁer ﬁeld in bytes. This ﬁeld is limited to the range 0 to 255.
KeyIdentiﬁer Pointer to an array of KeyIdentiﬁerType elements.

KeyFormat An EFI_GUID which speciﬁes the algorithm and key value size for this key.
KeyValue Pointer to a key value for a key speciﬁed by the KeyFormat ﬁeld. A NULL value for this ﬁeld indicates
that no key is available.
KeyStatus Speciﬁes the results of KMS operations performed with this descriptor. This ﬁeld is used to indicate the
status of individual operations when a KMS function is called with multiple EFI_KMS_KEY_DESCRIPTOR
structures. KeyStatus codes returned for the individual key requests are:
EFI_SUCCESS Successfully processed this key.
EFI_WARN_STALE_DATA Successfully processed this key, however, the key’s parameters exceed in-
ternal policies/limits and should be replaced.
EFI_COMPROMISED_DATA Successfully processed this key, but the key may have been compromised
and must be replaced.
EFI_UNSUPPORTED Key format is not supported by the service.
EFI_OUT_OF_RESOURCES Could not allocate resources for the key processing.
EFI_TIMEOUT Timed out waiting for device or key server.
EFI_DEVICE_ERROR Device or key server error.
EFI_INV ALID_PARAMETER KeyFormat is invalid.
EFI_NOT_FOUND The key does not exist on the KMS.
#define EFI_KMS_ATTRIBUTE_TYPE_NONE 0x00
#define EFI_KMS_ATTRIBUTE_TYPE_INTEGER 0x01
#define EFI_KMS_ATTRIBUTE_TYPE_LONG_INTEGER 0x02
#define EFI_KMS_ATTRIBUTE_TYPE_BIG_INTEGER 0x03
#define EFI_KMS_ATTRIBUTE_TYPE_ENUMERATION 0x04
#define EFI_KMS_ATTRIBUTE_TYPE_BOOLEAN 0x05
#define EFI_KMS_ATTRIBUTE_TYPE_BYTE_STRING 0x06
#define EFI_KMS_ATTRIBUTE_TYPE_TEXT_STRING 0x07
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#define EFI_KMS_ATTRIBUTE_TYPE_DATE_TIME 0x08
#define EFI_KMS_ATTRIBUTE_TYPE_INTERVAL 0x09
#define EFI_KMS_ATTRIBUTE_TYPE_STRUCTURE 0x0A
#define EFI_KMS_ATTRIBUTE_TYPE_DYNAMIC 0x0B
UINT32 FieldCount;
EFI_KMS_DYNAMIC_FIELD Field[1];
} EFI_KMS_DYNAMIC_ATTRIBUTE;
FieldCount The number of members in the EFI_KMS_DYNAMIC_ATTRIBUTE structure.
Field An array of EFI_KMS_DYNAMIC_FIELD structures.
UINT16 Tag;
UINT8 KeyAttributeData[1];
} EFI_KMS_DYNAMIC_FIELD;
Tag Part of a tag-type-length triplet that identiﬁes the KeyAttributeData formatting. The deﬁnition of the value is
outside the scope of this standard and may be deﬁned by the KMS.
Type Part of a tag-type-length triplet that identiﬁes the KeyAttributeData formatting. The deﬁnition of the value is
Length Length in bytes of the KeyAttributeData.
KeyAttributeData An array of bytes to hold the attribute data associated with the KeyAttributeIdentiﬁer.
UINT8 KeyAttributeIdentifierType;
UINT8 KeyAttributeIdentifierCount;
VOID *KeyAttributeIdentifier;
UINT16 KeyAttributeInstance;
UINT16 KeyAttributeType;
UINT16 KeyAttributeValueSize;
VOID *KeyAttributeValue;
EFI_STATUS KeyAttributeStatus;
} EFI_KMS_KEY_ATTRIBUTE;
KeyAttributeIdentiﬁerType The data type used for the KeyAttributeIdentiﬁer ﬁeld. Values for this ﬁeld are deﬁned
by the EFI_KMS_DATA_TYPE constants, except that EFI_KMS_DATA_TYPE_BINARY is not valid for this
ﬁeld.
KeyAttributeIdentiﬁerCount The length of the KeyAttributeIdentiﬁer ﬁeld in units deﬁned by KeyAttributeIdenti-
ﬁerType ﬁeld. This ﬁeld is limited to the range 0 to 255.
KeyAttributeIdentiﬁer Pointer to an array of KeyAttributeIdentiﬁerType elements. For string types, there must not
be a null-termination element at the end of the array.
KeyAttributeInstance The instance number of this attribute. If there is only one instance, the value is set to one. If
this value is set to 0xFFFF (all binary 1’s) then this ﬁeld should be ignored if an output or treated as a wild card
matching any value if it is an input. If the attribute is stored with this ﬁeld, it will match any attribute request
regardless of the setting of the ﬁeld in the request. If set to 0xFFFF in the request, it will match any attribute
with the same KeyAttributeIdentiﬁer.
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KeyAttributeType The data type of the KeyAttributeValue (e.g. struct, bool, etc.). See the list of KeyAttributeType
deﬁnitions.
KeyAttributeValueSize The size in bytes of the KeyAttribute ﬁeld. A value of zero for this ﬁeld indicates that no key
attribute value is available.
KeyAttributeValue Pointer to a key attribute value for the attribute speciﬁed by the KeyAttributeIdentiﬁer ﬁeld. If
theKeyAttributeValueSize ﬁeld is zero, then this ﬁeld must be NULL.
KeyAttributeStatus Speciﬁes the results of KMS operations performed with this attribute. This ﬁeld is
used to indicate the status of individual operations when a KMS function is called with multiple
EFI_KMS_KEY_ATTRIBUTE structures. KeyAttributeStatus codes returned for the individual key attribute
requests are:
EFI_SUCCESS Successfully processed this request.
EFI_WARN_STALE_DATA Successfully processed this request, however, the key’s parameters exceed
internal policies/limits and should be replaced.
EFI_COMPROMISED_DATA Successfully processed this request, but the key may have been compro-
mised and must be replaced.
EFI_UNSUPPORTED Key attribute format is not supported by the service.
EFI_OUT_OF_RESOURCES Could not allocate resources for the request processing.
EFI_INV ALID_PARAMETER A ﬁeld in the EFI_KMS_KEY_ATTRIBUTE structure is invalid.
EFI_NOT_FOUND The key attribute does not exist on the KMS.
The EFI_KMS_SERVICE_PROTOCOL deﬁnes a UEFI protocol that can be used by UEFI drivers and applications
to access cryptographic keys associated with their operation that are stored and possibly managed by a remote key
management service (KMS). For example, a storage device driver may require a set of one or more keys to enable
access to regions on the storage devices that it manages.
The protocol can be used to request the generation of new keys from the KMS, to register locally generated keys with
the KMS, to retrieve existing keys from the KMS, and to delete obsolete keys from the KMS. It also allows the device
driver to manage attributes associated with individual keys on the KMS, and to retrieve keys based on those attributes.
A platform implementing this protocol may use internal or external key servers to provide the functionality required
by this protocol. For external servers, the protocol implementation is expected to supply and maintain the connection
parameters required to connect and authenticate to the remote server. The connection may be made during the initial
installation of the protocol, or it may be delayed until the ﬁrst GetServiceStatus() request is received.
Each client using the KMS protocol may identify itself to the protocol implementation using a
EFI_KMS_CLIENT_INFO structure. If the KMS supported by this protocol requires the client to provide a
client identiﬁer, then this structure must be provided on all function calls.
While this protocol is intended to abstract the functions associated with storing and managing keys so that the protocol
user does not have to be aware of the speciﬁc KMS providing the service, it can also be used by callers which must
interact directly with a speciﬁc KMS. For these users, the protocol manages the connection to the KMS while the user
controls the operational interface via a client data pass thru function.
TheEFI_KMS_SERVICE_PROTOCOL provides the capability for the caller to pass arbitrary data to the KMS or to
receive such data back from the KMS via parameters on most functions. The use of such data is at the discretion of
the caller, but it should only be used sparingly as it reduces the interoperability of the caller’s software.
37.3. Key Management Service 1762Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.3.2 EFI_KMS_PROTOCOL.GetServiceStatus()
Summary
Get the current status of the key management service.
Prototype
typedef
(EFIAPI *EFI_KMS_GET_SERVICE_STATUS) (
IN EFI_KMS_PROTOCOL *This
);
This Pointer to the EFI_KEY_MANAGEMENT_SERVICE_PROTOCOL instance.
TheGetServiceStatus() function allows the user to query the current status of the KMS and should be called before
attempting any operations to the KMS. If the protocol has not been marked as available, then the user must call this
function to attempt to initiate the connection to the KMS as it may have been deferred to the ﬁrst user by the system
ﬁrmware.
If the connection to the KMS has not yet been established by the system ﬁrmware, then this function will attempt to
establish the connection, update the protocol structure content as appropriate, and mark the service as available.
EFI_SUCCESS The KMS is ready for use.
EFI_NOT_READY No connection to the KMS is available.

Summary
Prototype
typedef
);
ﬁrmware.
EFI_NO_MAPPING No valid connection conﬁguration exists for the KMS.
EFI_NO_RESPONSE No response was received from the KMS.
EFI_DEVICE_ERROR An error occurred when attempting to access the KMS.
37.3.2.1 EFI_KMS_PROTOCOL.RegisterClient()
Summary
Register client information with the supported KMS.
Prototype
typedef
(EFIAPI *EFI_KMS_REGISTER_CLIENT) (
IN EFI_KMS_PROTOCOL *This,
IN EFI_KMS_CLIENT_INFO *Client,
IN OUT UINTN *ClientDataSize OPTIONAL,
IN OUT VOID **ClientData OPTIONAL
);
Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
37.3. Key Management Service 1763Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ClientDataSize Pointer to the size, in bytes, of an arbitrary block of data speciﬁed by the ClientData parameter. This
parameter may be NULL , in which case the ClientData parameter will be ignored and no data will be transferred
to or from the KMS. If the parameter is not NULL, then ClientData must be a valid pointer. If the value pointed
to is 0, no data will be transferred to the KMS, but data may be returned by the KMS. For all non-zero values
ClientData will be transferred to the KMS, which may also return data to the caller. In all cases, the value
upon return to the caller will be the size of the data block returned to the caller, which will be zero if no data is
returned from the KMS.
ClientData Pointer to a pointer to an arbitrary block of data of ClientDataSize that is to be passed directly to the KMS
if it supports the use of client data. This parameter may be NULL if and only if the ClientDataSize parameter
is also NULL. Upon return to the caller, ClientData points to a block of data of * *ClientDataSize that was
returned from the KMS. If the returned value for ClientDataSize is zero, then the returned value for ClientData
must be NULL and should be ignored by the caller. The KMS protocol consumer is responsible for freeing all
valid buffers used for client data regardless of whether they are allocated by the caller for input to the function
or by the implementation for output back to the caller.
TheRegisterClient() function registers client information with the KMS using a EFI_KMS_CLIENT_INFO structure.
There are two methods of handling client information. The caller may supply a client identiﬁer in the
EFI_KMS_CLIENT_INFO structure prior to making the call along with an optional name string. The client iden-
tiﬁer will be passed on to the KMS if it supports client identiﬁers. If the KMS accepts the client id, then the
EFI_KMS_CLIENT_INFO structure will be returned to the caller unchanged. If the KMS does not accept the client
id, it may simply reject the request, or it may supply an alternate identiﬁer of its own,
The caller may also request a client identiﬁer from the KMS by passing NULL values in the EFI_KMS_CLIENT_INFO
structure. If the KMS supports this action, it will generate the identiﬁer and return it in the structure. Otherwise, the
implementation may generate a unique identiﬁer, returning it in the structure, or it may indicate that the function is
unsupported.
TheClientDataSize andClientData parameters allow the caller to pass an arbitrary block of data to/from the KMS for
uses such as auditing or access control. The KMS protocol implementation does not alter this data block other than to
package it for transmission to the KMS. The use of these parameters is optional.
EFI_SUCCESS The client information has been accepted by the KMS.
EFI_NO_RESPONSE There was no response from the device or the key server.
EFI_ACCESS_DENIED Access was denied by the device or the key server.
EFI_OUT_OF_RESOURCES Required resources were not available to perform the function.
EFI_UNSUPPORTED The KMS does not support the use of client identiﬁers.
37.3.2.2 EFI_KMS_PROTOCOL.CreateKey()
Summary
Request that the KMS generate one or more new keys and associate them with key identiﬁers. The key value(s) is
returned to the caller.
Prototype
typedef
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(EFIAPI *EFI_KMS_CREATE_KEY) (
IN OUT UINT16 *KeyDescriptorCount,
IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors,
);
This Pointer to this EFI_KMS_PROTOCOL instance.
KeyDescriptorCount Pointer to a count of the number of key descriptors to be processed by this operation. On
return, this number will be updated with the number of key descriptors successfully processed.
KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR structures which describe the keys to be gen-
erated.
On input, the KeyIdentiﬁerSize and the KeyIdentiﬁer may specify an identiﬁer to be used for the key, but this is
not required. The KeyFormat ﬁeld must specify a key format GUID reported as supported by the KeyFormats
ﬁeld of the EFI_KMS_PROTOCOL. The value for this ﬁeld in the ﬁrst key descriptor will be considered the
default value for subsequent key descriptors requested in this operation if those key descriptors have a NULL
GUID in the key format ﬁeld.
On output, the KeyIdentiﬁerSize andKeyIdentiﬁer ﬁelds will specify an identiﬁer for the key which will be either
the original identiﬁer if one was provided, or an identiﬁer generated either by the KMS or the KMS protocol
implementation. The KeyFormat ﬁeld will be updated with the GUID used to generate the key if it was a NULL
GUID, and the KeyValue ﬁeld will contain a pointer to memory containing the key value for the generated key.
Memory for both the KeyIdentiﬁer and the KeyValue ﬁelds will be allocated with the BOOT_SERVICES_DATA
type and must be freed by the caller when it is no longer needed. Also, the KeyStatus ﬁeld must reﬂect the result
of the request relative to that key.
parameter may be NULL in which case the ClientData parameter will be ignored and no data will be transferred
ClientData Pointer to a pointer to an arbitrary block of data of * ClientDataSize that is to be passed directly to the
KMS if it supports the use of client data. This parameter may be NULL if and only if the ClientDataSize
parameter is also NULL. Upon return to the caller, * ClientData points to a block of data of * ClientDataSize
that was returned from the KMS. If the returned value for * ClientDataSize is zero, then the returned value for *
ClientData must be NULL and should be ignored by the caller. The KMS protocol consumer is responsible for
freeing all valid buffers used for client data regardless of whether they are allocated by the caller for input to the
function or by the implementation for output back to the caller.
The CreateKey() method requests the generation of one or more new keys, and key identiﬁer and key values are
returned to the caller. The support of this function is optional as some key servers do not provide a key generation
TheClient parameter identiﬁes the caller to the key management service. This identiﬁer may be used for auditing or
access control. This parameter is optional unless the KMS requires a client identiﬁer in order to perform the requested
37.3. Key Management Service 1765Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
action.
The KeyDescriptorCount andKeyDescriptors parameters are used to specify the key algorithm, size, and attributes
for the requested keys. Any number of keys may be requested in a single operation, regardless of whether the KMS
supports multiple key deﬁnitions in a single request or not. The KMS protocol implementation is responsible for
generating the appropriate requests (single/multiple) to the KMS.

action.
TheCreateKey() function will return a status which indicates the overall status of the request. Note that this may be
different from the status reported for individual key requests.
EFI_SUCCESS Successfully generated and retrieved all requested keys.
EFI_UNSUPPORTED This function is not supported by the KMS. –OR– One (or more) of the
key requests submitted is not supported by the KMS. Check individual key
request(s) to see which ones may have been processed.
EFI_OUT_OF_RESOURCES Required resources were not available for the operation.
EFI_TIMEOUT Timed out waiting for device or key server. Check individual key request(s)
to see which ones may have been processed.
EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a ClientId is required
by the server and either no id was provided or an invalid id was provided
EFI_DEVICE_ERROR An error occurred when attempting to access the KMS. Check individual
key request(s) to see which ones may have been processed.
EFI_INV ALID_PARAMETER This isNULL, ClientId is required but it is NULL ,KeyDescriptorCount is
NULL, orKeys isNULL
EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures could not be pro-
cessed properly. KeyDescriptorCount contains the number of structures
which were successfully processed. Individual structures will reﬂect the
status of the processing for that structure.
37.3.2.3 EFI_KMS_PROTOCOL.GetKey()
Summary
Retrieve an existing key.
Prototype
typedef
(EFIAPI *EFI_KMS_GET_KEY) (
);
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KeyDescriptorCount Pointer to a count of the number of keys to be processed by this operation. On return, this
number will be updated with number of keys successfully processed.
KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR structures which describe the keys to be re-
trieved from the KMS. On input, the KeyIdentiﬁerSize and the KeyIdentiﬁer must specify an identiﬁer to be used
to retrieve a speciﬁc key. All other ﬁelds in the descriptor should be NULL . On output, the KeyIdentiﬁerSize and
KeyIdentiﬁer ﬁelds will be unchanged, while the KeyFormat andKeyValue ﬁelds will be updated values associ-
ated with this key identiﬁer. Memory for the KeyValue ﬁeld will be allocated with the BOOT_SERVICES_DATA
type and must be freed by the caller when it is no longer needed. Also, the KeyStatus ﬁeld will reﬂect the result
of the request relative to the individual key descriptor.
**ClientData* will be transferred to the KMS, which may also return data to the caller. In all cases, the value
that was returned from the KMS. If the returned value for **ClientDataSize* is zero, then the returned value for
**ClientData* must be NULL and should be ignored by the caller. The KMS protocol consumer is responsible
for freeing all valid buffers used for client data regardless of whether they are allocated by the caller for input to
the function or by the implementation for output back to the caller.
TheGetKey() function retrieves one or more existing keys from the KMS and returns the key values to the caller. This
function must be supported by every KMS protocol instance.
TheClient parameter identiﬁes the caller to the key management service. It may be used for auditing or access control.
The use of this parameter is optional unless the KMS requires it in order to perform the requested action.
The KeyDescriptorCount andKeyDescriptors parameters are used to specify the identiﬁer(s) to be used to retrieve
the key values, which will be returned in the KeyFormat andKeyValue ﬁelds of each EFI_KMS_KEY_DESCRIPTOR
structure. Any number of keys may be requested in a single operation, regardless of whether the KMS supports
multiple key deﬁnitions in a single request or not. The KMS protocol implementation is responsible for generating the
appropriate requests (single/multiple) to the KMS.
The GetKey() function will return a status which indicates the overall status of the request. Note that this may be
EFI_SUCCESS Successfully retrieved all requested keys.
EFI_OUT_OF_RESOURCES Could not allocate resources for the method processing.
37.3. Key Management Service 1767Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 37.15 – continued from previous page
EFI_BUFFER_TOO_SMALL If multiple keys are associated with a single identiﬁer, and the KeyValue
buffer does not contain enough structures ( KeyDescriptorCount ) to contain
all the key data, then the available structures will be ﬁlled and KeyDescrip-
torCount will be updated to indicate the number of keys which could not be
by the server and either none or an invalid id was provided
EFI_DEVICE_ERROR Device or key server error. Check individual key request(s) to see which
ones may have been processed.
EFI_UNSUPPORTED The implementation/KMS does not support this function
37.3.2.4 EFI_KMS_PROTOCOL.AddKey()
Summary
Add a new key.
Prototype
typedef
(EFIAPI *EFI_KMS_ADD_KEY) (
);
KeyDescriptorCount Pointer to a count of the number of keys to be processed by this operation. On normal returns,
this number will be updated with number of keys successfully processed.
KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR structures which describe the keys to be
added. On input, the KeyId ﬁeld for ﬁrst key must contain valid identiﬁer data to be used for adding a key
to the KMS. The values for these ﬁelds in this key deﬁnition will be considered default values for subsequent
keys requested in this operation. A value of 0 in any subsequent KeyId ﬁeld will be replaced with the current
default value. The KeyFormat andKeyValue ﬁelds for each key to be added must contain consistent values to be
associated with the given KeyId. On return, the KeyStatus ﬁeld will reﬂect the result of the operation for each
key request.

37.3. Key Management Service 1768Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ClientData Pointer to a pointer to an arbitrary block of data of **ClientDataSize* that is to be passed directly to
the KMS if it supports the use of client data. This parameter may be NULL if and only if the ClientDataSize
parameter is also NULL. Upon return to the caller, **ClientData* points to a block of data of **ClientDataSize*
TheAddKey() function registers a new key with the key management service. The support for this method is optional,
as not all key servers support importing keys from clients.
The KeyDescriptorCount andKeyDescriptors parameters are used to specify the key identiﬁer, key format and key
data to be registered on the. Any number of keys may be registered in a single operation, regardless of whether the
KMS supports multiple key deﬁnitions in a single request or not. The KMS protocol implementation is responsible
for generating the appropriate requests (single/multiple) to the KMS.
The AddKey() function will return a status which indicates the overall status of the request. Note that this may be
EFI_SUCCESS Successfully added all requested keys.
EFI_OUT_OF_RESOURCES Could not allocate required resources.
EFI_INV ALID_PARAMETER This isNULL, ClientId is required but it is NULL ,*KeyDescriptorCount*
isNULL, orKeys isNULL
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37.3.2.5 EFI_KMS_PROTOCOL.DeleteKey()
Summary
Delete an existing key from the KMS database.
Prototype
typedef
(EFIAPI *EFI_KMS_DELETE_KEY) (
);
deleted. On input, the KeyId ﬁeld for ﬁrst key must contain valid identiﬁer data to be used for adding a key
default value. The KeyFormat andKeyValue ﬁelds are ignored, but should be 0. On return, the KeyStatus ﬁeld
will reﬂect the result of the operation for each key request.
TheDeleteKey() function deregisters an existing key from the device or KMS. The support for this method is optional,
as not all key servers support deleting keys from clients.
The KeyDescriptorCount andKeyDescriptors parameters are used to specify the key identiﬁer(s) for the keys to be
deleted. Any number of keys may be deleted in a single operation, regardless of whether the KMS supports multi-
37.3. Key Management Service 1770Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ple key deﬁnitions in a single request or not. The KMS protocol implementation is responsible for generating the
TheDeleteKey() function will return a status which indicates the overall status of the request. Note that this may be
EFI_SUCCESS Successfully deleted all requested keys.
NULL , orKeys isNULL

37.3.2.6 EFI_KMS_PROTOCOL.GetKeyAttributes()
Summary
Get one or more attributes associated with a speciﬁed key identiﬁer. If none are found, the returned attributes count
contains a value of zero.
Prototype
typedef
(EFIAPI *EFI_KMS_GET_KEY_ATTRIBUTES) (
IN UINT8 *KeyIdentifierSize,
IN CONST VOID *KeyIdentifier,
IN OUT UINT16 *KeyAttributesCount,
IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes,
);
KeyIdentiﬁerSize Pointer to the size in bytes of the KeyIdentiﬁer variable.
37.3. Key Management Service 1771Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
KeyIdentiﬁer Pointer to the key identiﬁer associated with this key.
KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE structures associated with the Key iden-
tiﬁer. If none are found, the count value is zero on return. On input this value reﬂects the number of KeyAttributes
that may be returned. On output, the value reﬂects the number of completed KeyAttributes structures found.
KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE structures associated with the Key Identiﬁer. On
input, the ﬁelds in the structure should be NULL . On output, the attribute ﬁelds will have updated values for
attributes associated with this key identiﬁer.
*ClientData will be transferred to the KMS, which may also return data to the caller. In all cases, the value
TheGetKeyAttributes() function returns one or more attributes for a key.
TheClientIdentiﬁerSize andClientIdentiﬁer parameters identify the caller to the key management service. It may be
used for auditing or access control. The use of this parameter is optional unless the KMS requires it in order to perform
the requested action.
The KeyIdentiﬁerSize andKeyIdentiﬁer parameters identify the key whose attributes are to be returned by the key
management service. They may be used to retrieve additional information about a key, whose format is deﬁned by the
KeyAttribute. Attributes returned may be of the same or different names.
package it for transmission to the KMS. The use of these parameters is optional unless the KMS requires it in order to
perform the requested action.
TheGetKeyAttributes() function will return a status which indicates the overall status of the request. Note that this
may be different from the status reported for individual key attribute requests.
EFI_SUCCESS Successfully retrieved all key attributes.
EFI_TIMEOUT Timed out waiting for device or key server. Check individual key attribute
EFI_BUFFER_TOO_SMALL If multiple key attributes are associated with a single identiﬁer, and the Key-
Attributes buffer does not contain enough structures ( KeyAttributesCount
) to contain all the key attributes data, then the available structures will be
ﬁlled and KeyAttributesCount will be updated to indicate the number of key
attributes which could not be processed.
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Table 37.18 – continued from previous page
EFI_DEVICE_ERROR Device or key server error. Check individual key attribute request(s) (i.e.,
key attribute status for each) to see which ones may have been processed.
EFI_INV ALID_PARAMETER This is NULL, ClientId is required but it is NULL, KeyIdentiﬁerSize is
NULL, orKeyIdentiﬁer isNULL, orKeyAttributes isNULL, orKeyAt-
tributesSize isNULL.
EFI_NOT_FOUND The KeyIdentiﬁer could not be found. KeyAttributesCount contains zero.
Individual structures will reﬂect the status of the processing for that struc-
ture.
37.3.2.7 EFI_KMS_PROTOCOL.AddKeyAttributes()
Summary
Add one or more attributes to a key speciﬁed by a key identiﬁer.
Prototype
typedef
(EFIAPI *EFI_KMS_ADD_KEY_ATTRIBUTES) (
IN UINT *KeyIdentifierSize,
);
KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE structures to associate with the Key. On
normal returns, this number will be updated with the number of key attributes successfully processed.
KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE structures providing the attribute information to
associate with the key. On input, the values for the ﬁelds in the structure are completely ﬁlled in. On return the
KeyAttributeStatus ﬁeld will reﬂect the result of the operation for each key attribute request.
37.3. Key Management Service 1773Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheAddKeyAttributes() function adds one or more key attributes. If this function is not supported by a KMS protocol
instance then it is assumed that there is an alternative means available for attribute management in the KMS.
TheClient parameters identify the caller to the key management service. It may be used for auditing or access control.

The KeyIdentiﬁerSize andKeyIdentiﬁer parameters identify the key whose attributes are to be modiﬁed by the key
management service
TheKeyAttributesCount andKeyAttributes parameters are used to specify the key attributes data to be registered on
the KMS. Any number of attributes may be registered in a single operation, regardless of whether the KMS supports
multiple key attribute deﬁnitions in a single request or not. The KMS protocol implementation is responsible for
generating the appropriate requests (single/multiple) to the KMS. In certain error situations, the status of each attribute
is updated indicating if that attribute was successfully registered or not.
TheAddKeyAttributes() function will return a status which indicates the overall status of the request. Note that this may
be different from the status reported for individual key attribute requests. Status codes returned for AddKeyAttributes()
are:
EFI_SUCCESS Successfully added all requested key attributes.
EFI_BUFFER_TOO_SMALL If multiple keys attributes are associated with a single key identiﬁer, and the
attributes buffer does not contain enough structures ( KeyAttributesCount )
to contain all the data, then the available structures will be ﬁlled and KeyAt-
tributesCount will be updated to indicate the number of key attributes which
could not be processed. The status of each key attribute is also updated in-
dicating success or failure for that attribute in case there are other errors for
those attributes that could be processed.
EFI_INV ALID_PARAMETER This is NULL, ClientId is required but it is NULL, KeyAttributesCount is
NULL, orKeyAttributes isNULL, orKeyIdentiﬁerSize isNULL, orKeyI-
dentifer isNULL.
37.3. Key Management Service 1774Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 37.19 – continued from previous page
EFI_NOT_FOUND The KeyIdentiﬁer could not be found. On return the KeyAttributesCount
contains the number of attributes processed. Individual structures will re-
ﬂect the status of the processing for that structure.
37.3.2.8 EFI_KMS_PROTOCOL.DeleteKeyAttributes()
Summary
Delete attributes to a key speciﬁed by a key identiﬁer.
Prototype
typedef
(EFIAPI *EFI_KMS_DELETE_KEY_ATTRIBUTES) (
IN OUT VOI **ClientData OPTIONAL
);
KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE structures associated with the Key. On
input, the count value is one or more. On normal returns, this number will be updated with the number of key
attributes successfully processed.
KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE structures associated with the key. On input, the
values for the ﬁelds in the structure are completely ﬁlled in. On return the* KeyAttributeStatus ﬁeld will reﬂect
the result of the operation for each key attribute request.
that was returned from the KMS. If the returned value for ClientDataSize is zero, then the returned value for *
*ClientData must be NULL and should be ignored by the caller. The KMS protocol consumer is responsible
37.3. Key Management Service 1775Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheDeleteKeyAttributes() function removes key attributes for a key with the key management service.
TheKeyAttributesCount andKeyAttributes parameters are used to specify the key attributes data to be deleted on the
KMS. Any number of attributes may be deleted in a single operation, regardless of whether the KMS supports multiple
key attribute deﬁnitions in a single request or not. The KMS protocol implementation is responsible for generating
the appropriate requests (single/multiple) to the KMS. In certain error situations, the status of each attribute is updated
indicating if that attribute was successfully deleted or not.
The DeleteKeyAttributes() function will return a status which indicates the overall status of the request. Note that this
may be different from the status reported for individual key attribute requests. Status codes returned for the method
are:
EFI_SUCCESS Successfully deleted all requested key attributes.
EFI_INV ALID_PARAMETER This isNULL, ClientId is required but it is NULL ,KeyAttributesCount is
NULL, orKeyAttributes isNULL, orKeyIdentiﬁerSize isNULL , orKeyI-
dentifer isNULL .
EFI_NOT_FOUND TheKeyIdentiﬁer could not be found or the attribute could not be found. On
return the KeyAttributesCount contains the number of attributes processed.

are:
ture.
37.3. Key Management Service 1776Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.3.2.9 EFI_KMS_PROTOCOL.GetKeyByAttributes()
Summary
Retrieve one or more key that has matched all of the speciﬁed key attributes.
Prototype
typedef
(EFIAPI *EFI_KMS_GET_KEY_BY_ATTRIBUTES) (
IN UINTN *KeyAttributeCount,
IN OUT UINTN *KeyDescriptorCount,
);
KeyAttributeCount Pointer to a count of the number of key attribute structures that must be matched for each re-
turned key descriptor. On input the count value is one or more. On normal returns, this number will be updated
with the number of key attributes successfully processed.
KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE structure to search for. On input, the values for
the ﬁelds in the structure are completely ﬁlled in. On return the KeyAttributeStatus ﬁeld will reﬂect the result
of the operation for each key attribute request.
KeyDescriptorCount Pointer to a count of the number of key descriptors matched by this operation. On entry, this
number will be zero. On return, this number will be updated to the number of key descriptors successfully
found.
KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR structures which describe the keys from the
KMS having the KeyAttribute(s) speciﬁed. On input, this pointer will be NULL . On output, the array will
contain an EFI_KMS_KEY_DESCRIPTOR structure for each key meeting the search criteria. Memory for the
array and all KeyValue ﬁelds will be allocated with the EﬁBootServicesData type and must be freed by the caller
when it is no longer needed. Also, the KeyStatus ﬁeld of each descriptor will reﬂect the result of the request
relative to that key descriptor.
37.3. Key Management Service 1777Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The GetKeyByAttributes() function returns the keys found by searches for matching key attribute(s). This function
must be supported by every KMS protocol instance that supports the use of key attributes as indicated in the protocol’s
KeyAttributesSupported ﬁeld.
The KeyAttributesCount andKeyAttributes parameters are used to specify the key attributes data to be searched for
on the KMS. Any number of attributes may be searched for in a single operation, regardless of whether the KMS
supports multiple key attribute deﬁnitions in a single request or not. The KMS protocol implementation is responsible
for generating the appropriate requests (single/multiple) to the KMS. In certain error situations, the status of each
attribute is updated indicating if that attribute was successfully found or not. If an attribute speciﬁes a wildcard
KeyAttributeInstance value, then the provider returns all instances of the attribute.
TheKeyDescriptorCount andKeyDescriptors parameters are used to return the EFI_KMS_KEY_DESCRIPTOR struc-
tures for keys meeting the search criteria. Any number of keys may be returned in a single operation, regardless of
whether the KMS supports multiple key deﬁnitions in a single request or not. The KMS protocol implementation is
responsible for generating the appropriate requests (single/multiple) to the KMS.
TheGetKeyByAttributes() function will return a status which indicates the overall status of the request. Note that this
may be different from the status reported for individual keys.
EFI_BUFFER_TOO_SMALL If multiple keys are associated with the attribute(s), and the KeyValue buffer
does not contain enough structures ( KeyDescriptorCount ) to contain all
the key data, then the available structures will be ﬁlled and KeyDescriptor-
Count will be updated to indicate the number of keys which could not be
EFI_INV ALID_PARAMETER This is NULL, ClientId is required but it is NULL , KeyDescriptorCount is
NULL, or KeyDescriptors is NULL or KeyAttributes is NULL, or KeyAt-
tributesCount is NULL .
EFI_NOT_FOUND One or more EFI_KMS_KEY_ATTRIBUTE structures could not be pro-
cessed properly. KeyAttributeCount contains the number of structures
37.3. Key Management Service 1778Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.4 PKCS7 Verify Protocol
37.4.1 EFI_PKCS7_VERIFY_PROTOCOL
Summary
EFI_PKCS7_VERIFY_PROTOCOL (See: http://tools.ietf.org/html/rfc2315 ) may be used to verify data signed with
PKCS#7 formatted authentication. The PKCS#7 data to be veriﬁed must be binary DER encoded. Additional infor-
mation on the supported ASN.1 formatting is provided below.
Drivers that supply PKCS7 veriﬁcation function should publish the | EFI_PKCS7_VERIFY_PROTOCOL. Drivers
wishing to use the | EFI_PKCS7_VERIFY_PROTOCOL may get a reference with LocateProtocol().
GUID
#define EFI_PKCS7_VERIFY_PROTOCOL_GUID \
{ 0x47889fb2, 0xd671, 0x4fab,\
{ 0xa0, 0xca, 0xdf, 0xe, 0x44,\ 0xdf, 0x70, 0xd6 }}
typedef struct _EFI_PKCS7_VERIFY_PROTOCOL {
EFI_PKCS7_VERIFY_BUFFER *VerifyBuffer;
EFI_PKCS7_VERIFY_SIGNATURE *VerifySignature;
} EFI_PKCS7_VERIFY_PROTOCOL;
VerifyBuffer Examine a DER-encoded PKCS7-signed memory buffer with signature containing embedded data con-
tent, or buffer with detached signature and separate data content buffer, and verify using supplied signature
lists.
VerifySignature Examine a DER-encoded PKCS7-signed memory buffer with signature and, using caller-supplied
hash value for signed data, verify using supplied signature lists.
The EFI_PKCS7_VERIFY_PROTOCOL is used to verify data signed using PKCS7 structure. PKCS7 is a general-
purpose cryptographic standard (see references). The PKCS7 data to be veriﬁed must be ASN.1 (DER) encoded. See
the Table below.
Table 37.22: Details of Supported Signature Format
Signature
Buffer Format
Details

lists.
Signature
Details
Encoding Binary DER
ASN.1 root
of Embedded
Signed DataContentInfo with SignedData content type
ASN.1 root of
Detached Signa-
tureSignedData or ContentInfo with SignedData content type
Embedded Data
TypeTypically ‘Data’ (1.2.840.113549.1.7.1) or other deﬁned OID type (however caller should not
depend upon specialized OID processing during PKCS validation.)
37.4. PKCS7 Verify Protocol 1779Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 37.22 – continued from previous page
Digest (Hash)
Algorithm (
VerifyBuffer
function)See [RFC2315] and OID deﬁnition by different standard bodies.
Digest Encryp-
tionSee [RFC2315] and OID deﬁnition by different standard bodies.
Certiﬁcate
validity datesSeeTimeStampDb description
Signature
authenticate-
dAttributesIgnored by function
Timestamping See TimeStampDb description
References
PKCS7 is deﬁned by RFC2315. For more information see “Links to UEFI-Related Documents” ( http:
//ueﬁ.org/ueﬁ ) under the heading “RFC2315 (deﬁnes PKCS7)”.
37.4.2 EFI_PKCS7_VERIFY_PROTOCOL.VerifyBuffer()
Summary
This function processes a buffer containing binary DER-encoded PKCS7 signature. The signed data content may be
embedded within the buffer or separated. Function veriﬁes the signature of the content is valid and signing certiﬁcate
was not revoked and is contained within a list of trusted signers.
Prototype
typedef
(EFIAPI *VerifyBuffer)(
IN EFI_PKCS7_VERIFY_PROTOCOL *This,
IN VOID *SignedData,
IN UINTN SignedDataSize,
IN VOID *InData OPTIONAL,
IN UINTN InDataSize
IN EFI_SIGNATURE_LIST **AllowedDb,
IN EFI_SIGNATURE_LIST **RevokedDb OPTIONAL,
IN EFI_SIGNATURE_LIST **TimeStampDb OPTIONAL,
OUT VOID *Content OPTIONAL,
IN OUT UINTN *ContentSize
);
This Pointer to EFI_PKCS7_VERIFY_PROTOCOL instance.
SignedData Points to buffer containing ASN.1 DER-encoded PKCS signature.
SignedDataSize The size of SignedData buffer in bytes.
InData In case of detached signature, Indata points to buffer containing the raw message data previously signed and
to be veriﬁed by function. In case of SignedData containing embedded data, InData must be NULL .
InDataSize
When InData is used, the size of InData buffer in bytes.
37.4. PKCS7 Verify Protocol 1780Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
When InData isNULL , this parameter must be 0.
AllowedDb Pointer to a list of pointers to EFI_SIGNATURE_LIST structures. The list is terminated by a null
pointer. The EFI_SIGNATURE_LIST structures contain lists of X.509 certiﬁcates of approved signers.
See Chapter 27 for deﬁnition of EFI_SIGNATURE_LIST. Function recognizes signer certiﬁcates of type
EFI_CERT_X509_GUID. Any hash certiﬁcate in AllowedDb list is ignored by this function. Function returns
success if signer of the buffer is within this list (and not within RevokedDb ). This parameter is required.
RevokedDb Optional pointer to a list of pointers to EFI_SIGNATURE_LIST structures. The list is terminated by a
null pointer. List of X.509 certiﬁcates of revoked signers and revoked ﬁle hashes. Except as noted in description
ofTimeStampDb, signature veriﬁcation will always fail if the signer of the ﬁle or the hash of the data component
of the buffer is in RevokedDb list. This list is optional and caller may pass Null or pointer to NULL if not
required.
TimeStampDb Optional pointer to a list of pointers to EFI_SIGNATURE_LIST structures. The list is terminated by
a null pointer. This parameter can be used to pass a list of X.509 certiﬁcates of trusted time stamp signers. This
list is optional and caller may pass Null or pointer to NULL if not required.
Content On input, points to an optional caller-allocated buffer into which the function will copy the content portion
of the ﬁle after veriﬁcation succeeds. This parameter is optional and if NULL , no copy of content from ﬁle is
performed.
ContentSize On input, points to the size in bytes of the optional buffer Content previously allocated by caller. On
output, if the veriﬁcation succeeds, the value referenced by ContentSize will contain the actual size of the content
from signed ﬁle. If ContentSize indicates the caller-allocated buffer is too small to contain content, an error is
returned, and ContentSize will be updated with the required size. This parameter must be 0 if Content is Null.
This function processes the buffer SignedData for PCKS7 veriﬁcation. The data that was signed using PKCS is
referred to as the ‘Message’. In the process of creating a signature of the message, a SHA256 or other hash of the
message bytes, called the ‘Message Digest’, is encrypted using a private key held in secret by the signer. The encrypted
hash and the X.509 public key certiﬁcate of the signer are formatted according to the ASN.1 PKCS#7 Schema (See
References). For the buffer type with the embedded data, the ASN.1 syntax is also used to wrap the data and combine
the message data with the signature structure.
The SignedData buffer must be ASN.1 DER-encoded format with structure according to the subset deﬁned in the
introduction to this protocol. Both embedded content and detached signature formats are supported. In case of em-
bedded content, SignedData contains both the PKCS7 signature structure and the message content that was signed.
In the case of detached signature, SignedData contains only the signature data and InData is used to supply the data
to be veriﬁed. To pass veriﬁcation the X.509 public certiﬁcate of the signer of the ﬁle must be found in AllowedDb
and not be present in RevokedDb. Additionally if RevokedDb contains a speciﬁc Hash signature that matches the hash
calculated for the content, the ﬁle will also fail veriﬁcation. The message content will be copied to the caller-supplied
buffer Content (when present) with ContentSize updated to reﬂect the total size in bytes of the extracted content.
TheVerifyBuffer() function performs several steps. First, the buffer containing the user-provided signature is parsed,
the content is located and a hash calculated, and the PKCS7 signature of that hash is veriﬁed by decrypting the hash
calculated at time of signing. Match of current hash with decrypted hash provides indication the structure contained
in buffer has not been modiﬁed since signing. Next the protocol function attempts to match the signing certiﬁcate
included within the signed data again the members of an (optional) list of caller-provided revoked certiﬁcates ( Re-
vokedDb ). The hash of the data is also compared against any hash items contained in RevokedDb list. Next the signing
certiﬁcate is matched against the caller-provided list of trusted signatures. If the signature is valid, the certiﬁcate or
hash are not in the revoked list, and the certiﬁcate is in the trusted list, the ﬁle passes veriﬁcation.
When TimeStampDb list is present this information modiﬁes the processing of revoked certiﬁcates found in both
AllowedDb andRevokedDb. When PCKS7 signings that are time-stamped by trusted signer in TimeStampDb list,
and which time-stamping occurred prior to the time of certiﬁcate revocation noted in certiﬁcate in RevokedDb list,
the signing will be allowed and return EFI_SUCCESS. TimeStampDb parameter is optional and may be NULL or a
pointer to NULL when not used. Except in the processing of certiﬁcates found in both AllowedDb andRevokedDb,
37.4. PKCS7 Verify Protocol 1781Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TimeStampDb is not used and time-stamping is not otherwise required for signings veriﬁed by certiﬁcate only in
AllowedDb.
NOTE: This method is intended to be suitable to implement Secure Boot image validation, and as such the contents
ofAllowedDb, RevokedDb, andTimeStampDb must also conform with the requirements of Authorization Process ,
bullet item 3 (UEFI Image Validation Succeeded) .
The veriﬁcation function can handle both embedded data or detached signature formats. In case of embedded data,
the function will optionally extract the original signed data and supply back to caller in caller-supplied buffer. For a
detached signature the caller must provide the original message data in buffer pointed to by InData. For consistency,
when both InData andContent are provided, the function will copy contents of InData toContent.
In case where the ContentSize indicated by caller is too small to contain the entire content extracted from the ﬁle,
EFI_BUFFER_TOO_SMALL error is returned, and ContentSize is updated to reﬂect the required size.
NOTE: When signing certiﬁcate is matched to AllowedDb orRevokedDb lists, a match can occur against an entry in
the list at any level of the chain of X.509 certiﬁcates present in the PCKS certiﬁcate list. This supports signing with a
certiﬁcate that chains to one of the certiﬁcates in the AllowedDb orRevokedDb lists.
None
EFI_SUCCESS Content signature was veriﬁed against hash of content, the signer’s certiﬁ-

None
cate was not found in RevokedDb, and was found in AllowedDb or if in
signer is found in both AllowedDb andRevokedDb, the signing was allowed
by reference to TimeStampDb as described above, and no hash matching
content hash was found in RevokedDb.
EFI_SECURITY_VIOLATION The SignedData buffer was correctly formatted but signer was in Re-
vokedDb or not in AllowedDb. Also returned if matching content hash found
inRevokedDb.
EFI_COMPROMISED_DATA Calculated hash differs from signed hash.
EFI_INV ALID_PARAMETER SIgnedData is NULL or SIgnedDataSize is zero. AllowedDb is NULL.
EFI_INV ALID_PARAMETER Content is not NULL and ContentSize is NULL.
EFI_ABORTED Unsupported or invalid format in TImeStampDb, RevokedDb orAllowedDb
list contents was detected.
EFI_NOT_FOUND Content not found because InData is NULL and no content embedded in
SIgnedData.
EFI_UNSUPPORTED The SignedData buffer was not correctly formatted for processing by the
function.
EFI_UNSUPPORTED Signed data embedded in SIgnedData butInData is not NULL.
EFI_BUFFER_TOO_SMALL The size of buffer indicated by ContentSize is too small to hold the content.
ContentSize updated to required size.
37.4.2.1 EFI_PKCS7_VERIFY_PROTOCOL.VerifySignature()
Summary
This function processes a buffer containing binary DER-encoded detached PKCS7 signature. The hash of the signed
data content is calculated and passed by the caller. Function veriﬁes the signature of the content is valid and signing
certiﬁcate was not revoked and is contained within a list of trusted signers.
Note: The current UEFI speciﬁcation allows for a variety of hashes. In order to be secure, the users of this protocol
37.4. PKCS7 Verify Protocol 1782Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
should loop over each hash to see if the binary signature is authorized.
Prototype
typedef
(EFIAPI *VerifySignature)(
IN VOID *Signature,
IN UINTN SignatureSize,
IN VOID *InHash,
IN UINTN InHashSize
);
Signature Points to buffer containing ASN.1 DER-encoded PKCS detached signature.
SignatureSize The size of Signature buffer in bytes.
InHash InHash points to buffer containing the caller calculated hash of the data. This parameter may not be NULL .
InHashSize The size in bytes of InHash buffer.
RevokedDb Pointer to a list of pointers to EFI_SIGNATURE_LIST structures. The list is terminated by a null pointer.
List of X.509 certiﬁcates of revoked signers and revoked ﬁle hashes. Signature veriﬁcation will always fail if
the signer of the ﬁle or the hash of the data component of the buffer is in RevokedDb list. This parameter is
optional and caller may pass Null if not required.
TimeStampDb Optional pointer to a list of pointers to EFI_SIGNATURE_LIST structures. The list is terminated by a
null pointer. This parameter can be used to pass a list of X.509 certiﬁcates of trusted time stamp counter-signers.
This function processes the buffer Signature for PCKS7 veriﬁcation using hash of the data calculated and pass by
caller in the InHash buffer. The data that was signed using PKCS is referred to as the ‘Message’. In the process of
creating a signature of the message, a hash of the message bytes, called the ‘Message Digest’, is encrypted using a
private key held in secret by the signer. The encrypted hash and the X.509 public key certiﬁcate of the signer are
formatted according to the ASN.1 PKCS#7 Schema (See References). Any data embedded within the PKCS structure
is ignored by the function. This function does not support extraction of signature from executable ﬁle formats. The
address of the PKCS Signature block must be located and passed by the called.
The hash size passed in InHashSize must match the size of the signed hash embedded within the PKCS signature
structure or an error is returned.
introduction to this protocol. Both embedded content and detached signature formats are supported however embedded
data is ignored. To pass veriﬁcation the X.509 public certiﬁcate of the signer of the ﬁle must be found in AllowedDb
and not be present in RevokedDb. Additionally, if RevokedDb contains a speciﬁc Hash signature that matches the hash
calculated for the content, the ﬁle will also fail veriﬁcation.
37.4. PKCS7 Verify Protocol 1783Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
AllowedDb andRevokedDb. When PCKS7 signings that are time-stanped by trusted signer in TimeStampDb list,
The VerifySignature() function performs several steps. First, the buffer containing the user-provided signature is
parsed, (any embedded content is ignored), and the PKCS7 signature of hash data is veriﬁed by decrypting the hash
calculated at time of signing. Match of caller provided hash with decrypted hash provides indication the signed data
has not been modiﬁed since signing. Next the protocol function attempts to match the signing certiﬁcate included
within the signed data again the members of an (optional) list of caller-provided revoked certiﬁcates ( RevokedDb ).
The hash of the data is also compared against any hash items contained in RevokedDb list. Next the signing certiﬁcate
is matched against the caller-provided list of trusted signatures. If the signature is valid, the certiﬁcate or hash are not
in the revoked list, and the certiﬁcate is in the trusted list, the ﬁle passes veriﬁcation.
Note: When a signing certiﬁcate is matched to AllowedDb or RevokedDb lists, a match can occur against an entry in
certiﬁcate that chains to one of the certiﬁcates in the AllowedDb or RevokedDb lists.
Note: Because this function uses hashes and the speciﬁcation contains a variety of hash choices, you should be aware
that the check against the RevokedDb list will improperly succeed if the signature is revoked using a different hash
algorithm. For this reason, you should either cycle through all UEFI supported hashes to see if one is forbidden, or
rely on a single hash choice only if the UEFI signature authority only signs and revokes with a single hash.
None
EFI_SUCCESS Signed hash was veriﬁed against caller-provided hash of content, the
signer’s certiﬁcate was not found in RevokedDb, and was found in Al-
lowedDb or if in signer is found in both AllowedDb andRevokedDb, the
signing was allowed by reference to TimeStampDb as described above, and
no hash matching content hash was found in RevokedDb.
EFI_COMPROMISED_DATA Caller provided hash differs from signed hash. Or, caller and encrypted hash
are different sizes.
EFI_INV ALID_PARAMETER Signature is NULL or SignatureSize is zero. InHash is NULL or InhashSize
is zero. AllowedDb is NULL.
EFI_ABORTED Unsupported or invalid format in TimeStampDb, RevokedDb orAllowedDb
EFI_UNSUPPORTED TheSignature buffer was not correctly formatted for processing by the func-
tion.
37.4. PKCS7 Verify Protocol 1784Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.5 Random Number Generator Protocol
This section deﬁnes the Random Number Generator (RNG) protocol. This protocol is used to provide random numbers
for use in applications, or entropy for seeding other random number generators. Consumers of the protocol can ensure
that drivers implementing the protocol produce RNG values in a well-known manner.

tion.
When a Deterministic Random Bit Generator (DRBG) is used on the output of a (raw) entropy source, its security
level must be at least 256 bits.
37.5.1 EFI_RNG_PROTOCOL
Summary
This protocol provides standard RNG functions. It can be used to provide random bits for use in applications, or
entropy for seeding other random number generators.
GUID
#define EFI_RNG_PROTOCOL_GUID \
{ 0x3152bca5, 0xeade, 0x433d,\
{0x86, 0x2e, 0xc0, 0x1c, 0xdc, 0x29, 0x1f, 0x44}}
typedef struct _EFI_RNG_PROTOCOL {
EFI_RNG_GET_INFO GetInfo
EFI_RNG_GET_RNG GetRNG;
} EFI_RNG_PROTOCOL;
GetInfo Returns information about the random number generation implementation.
GetRNG Returns the next set of random numbers.
This protocol allows retrieval of RNG values from an UEFI driver. The GetInfo service returns information about the
RNG algorithms the driver supports. The GetRNG service creates a RNG value using an (optionally speciﬁed) RNG
algorithm.
37.5.2 EFI_RNG_PROTOCOL.GetInfo
Summary
Returns information about the random number generation implementation.
Prototype
typedef
(EFIAPI *EFI_RNG_GET_INFO) (
IN EFI_RNG_PROTOCOL *This,
IN OUT UINTN *RNGAlgorithmListSize,
OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
);
37.5. Random Number Generator Protocol 1785Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This A pointer to the EFI_RNG_PROTOCOL instance.
RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList. On output with a return code of
EFI_SUCCESS, the size in bytes of the data returned in RNGAlgorithmList.
On output with a return code of EFI_BUFFER_TOO_SMALL, the size of RNGAlgorithmList required to obtain
the list.
RNGAlgorithmList A caller-allocated memory buffer ﬁlled by the driver with one EFI_RNG_ALGORITHM element
for each supported RNG algorithm. The list must not change across multiple calls to the same driver. The ﬁrst
algorithm in the list is the default algorithm for the driver.
This function returns information about supported RNG algorithms.
A driver implementing the RNG protocol need not support more than one RNG algorithm, but shall support a minimum
of one RNG algorithm.
typedef EFI_GUID EFI_RNG_ALGORITHM;
EFI_SUCCESS The RNG algorithm list was returned successfully.
EFI_DEVICE_ERROR The list of algorithms could not be retrieved due to a hardware or ﬁrmware
error.
EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result.
37.5.3 EFI_RNG_PROTOCOL.GetRNG
Summary
Produces and returns an RNG value using either the default or speciﬁed RNG algorithm.
Prototype
typedef
(EFIAPI *EFI_RNG_GET_RNG) (
IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
IN UINTN RNGValueLength,
OUT UINT8 *RNGValue
);
RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identiﬁes the RNG algorithm to use. May be NULL
in which case the function will use its default RNG algorithm.
RNGValueLength The length in bytes of the memory buffer pointed to by RNGValue. The driver shall return exactly
this number of bytes.
RNGValue A caller-allocated memory buffer ﬁlled by the driver with the resulting RNG value.
37.5. Random Number Generator Protocol 1786Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function ﬁlls the RNGValue buffer with random bytes from the speciﬁed RNG algorithm. The driver must not
reuse random bytes across calls to this function. It is the caller’s responsibility to allocate the RNGValue buffer.
EFI_SUCCESS The RNG value was returned successfully.
EFI_UNSUPPORTED The algorithm speciﬁed by RNGAlgorithm is not supported by this driver.
EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or ﬁrmware error.
EFI_NOT_READY There is not enough random data available to satisfy the length requested
byRNGValueLength.
EFI_INV ALID_PARAMETER RNGValue is null or RNGValueLength is zero.
37.5.4 EFI RNG Algorithm Deﬁnitions
Summary
This sub-section provides EFI_GUID values for a selection of EFI_RNG_PROTOCOL algorithms. The algorithms
listed are optional, not meant to be exhaustive and may be augmented by vendors or other industry standards.
The “raw” algorithm, when supported, is intended to provide entropy directly from the source, without it going through
some deterministic random bit generator.
Prototype
#define EFI_RNG_ALGORITHM_SP800_90_HASH_256_GUID \
{0xa7af67cb, 0x603b, 0x4d42,\
{0xba, 0x21, 0x70, 0xbf, 0xb6, 0x29, 0x3f, 0x96}}
#define EFI_RNG_ALGORITHM_SP800_90_HMAC_256_GUID \
{0xc5149b43, 0xae85, 0x4f53,\
{0x99, 0x82, 0xb9, 0x43, 0x35, 0xd3, 0xa9, 0xe7}}
#define EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID \
{0x44f0de6e, 0x4d8c, 0x4045, \
{0xa8, 0xc7, 0x4d, 0xd1, 0x68, 0x85, 0x6b, 0x9e}}
#define EFI_RNG_ALGORITHM_X9_31_3DES_GUID \
{0x63c4785a, 0xca34, 0x4012,\
{0xa3, 0xc8, 0x0b, 0x6a, 0x32, 0x4f, 0x55, 0x46}}
#define EFI_RNG_ALGORITHM_X9_31_AES_GUID \
{0xacd03321, 0x777e, 0x4d3d,\
{0xb1, 0xc8, 0x20, 0xcf, 0xd8, 0x88, 0x20, 0xc9}}
#define EFI_RNG_ALGORITHM_RAW \
{0xe43176d7, 0xb6e8, 0x4827,\
{0xb7, 0x84, 0x7f, 0xfd, 0xc4, 0xb6, 0x85, 0x61}}
37.5. Random Number Generator Protocol 1787Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.5.5 RNG References
NIST SP 800-90, “Recommendation for Random Number Generation Using Deterministic Random Bit Generators,”
March 2007. See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ ) under the heading “Recommendation for
Random Number Generation Using Deterministic Random Bit Generators”.
NIST, “Recommended Random Number Generator Based on ANSI X9.31 Appendix A.2.4 Using the 3-Key Triple
DES and AES Algorithms,” January 2005. See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ ) under the
heading “Recommended Random Number Generator Based on ANSI X9.31”.
37.6 Smart Card Reader and Smart Card Edge Protocol
The UEFI Smart Card Reader Protocol provides an abstraction for device to provide smart card reader support. This
protocol is very close to Part 5 of PC/SC workgroup speciﬁcations and provides an API to applications willing to
communicate with a smart card or a smart card reader.
37.6.1 Smart Card Reader Protocol
37.6.1.1 EFI_SMART_CARD_READER_PROTOCOL Summary
Smart card aware application invokes this protocol to get access to an inserted smart card in the reader or to the reader
itself.
GUID
#define EFI_SMART_CARD_READER_PROTOCOL_GUID \
{0x2a4d1adf, 0x21dc, 0x4b81,\
{0xa4, 0x2f, 0x8b, 0x8e, 0xe2, 0x38, 0x00, 0x60}}
typedef struct _EFI_SMART_CARD_READER_PROTOCOL {
EFI_SMART_CARD_READER_CONNECT SCardConnect;
EFI_SMART_CARD_READER_DISCONNECT SCardDisconnect;
EFI_SMART_CARD_READER_STATUS SCardStatus;
EFI_SMART_CARD_READER_TRANSMIT SCardTransmit;
EFI_SMART_CARD_READER_CONTROL SCardControl;
EFI_SMART_CARD_READER_GET_ATTRIB SCardGetAttrib;
} EFI_SMART_CARD_READER_PROTOCOL;
Members
SCardConnect Requests a connection to the smart card or smart card reader.
SCardDisconnect Closes the previously open connection.
SCardStatus Provides informations on smart card status and reader name.
SCardTransmit Exchanges data with smart card or smart card reader.
SCardControl Gives direct control to the smart card reader.
SCardGetAttrib Retrieves reader characteristics.
This protocol allows UEFI applications to communicate and get/set all necessary information to the smart card reader.
37.6. Smart Card Reader and Smart Card Edge Protocol 1788Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Overview
This document aims at deﬁning a standard way for UEFI applications to use a smart card. The key points are:
• Provide an API as close as possible to Part 5 of the existing PC/SC interface. See “Links to UEFI-Related
Documents” ( http://ueﬁ.org/ueﬁ ) under the heading “PC/SC Workgroup Speciﬁcations”.
• Remove any unnecessary complexity of PC/SC implementation in a classic OS:
— Assume no connection sharing
— No resource manager
— Reduced set of APIs
Note that this document only focuses on PC/SC Part 5 (access to smart card/smart card reader from an application).
Abstracting the smart card (Parts 6/9) is not the scope of this document.
Main differences with existing PC/SC implementation on Linux/MacOS/Windows:
• There is no resource manager, driver exposes Part 5 instead of Part 3
• It is not possible to share a smart card between UEFI applications/drivers
• Reader enumeration is different:
— On classic PC/SC, SCardListReaders is used
— In UEFI, reader list is available via OpenProtocol/ScardStatus calls
37.6.2 EFI_SMART_CARD_READER_PROTOCOL.SCardConnect()
Summary
This function requests connection to the smart card or the reader, using the appropriate reset type and protocol.
Prototype
(EFIAPI *EFI_SMART_CARD_READER_PROTOCOL_CONNECT) (

Summary
Prototype
IN EFI_SMART_CARD_READER_PROTOCOL *This,
IN UINT32 AccessMode,
IN UINT32 CardAction,
IN UINT32 PreferredProtocols,
OUT UINT32 *ActiveProtocol
);
This Indicates a pointer to the calling context. Type EFI_SMART_CARD_READER_PROTOCOL is deﬁned in the
EFI_SMART_CARD_READER_PROTOCOL description.
AccessMode See “Related Deﬁnitions” below.
CardAction
SCARD_CA_NORESET,
SCARD_CA_COLDRESET or
SCARD_CA_WARMRESET.
37.6. Smart Card Reader and Smart Card Edge Protocol 1789Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PreferredProtocols Bitmask of acceptable protocols. See “Related Deﬁnitions” below.
ActiveProtocol A ﬂag that indicates the active protocol. See “Related Deﬁnitions” below.
//
// Codes foraccess mode
//
#define SCARD_AM_READER 0x0001 // Exclusive access to reader
#define SCARD_AM_CARD 0x0002 // Exclusive access to card
//
// Codes forcard action
//
#define SCARD_CA_NORESET 0x0000 // Don’t reset card
#define SCARD_CA_COLDRESET 0x0001 // Perform a cold reset
#define SCARD_CA_WARMRESET 0x0002 // Perform a warm reset
#define SCARD_CA_UNPOWER 0x0003 // Power off the card
#define SCARD_CA_EJECT 0x0004 // Eject the card
//
// Protocol types
//
#define SCARD_PROTOCOL_UNDEFINED 0x0000
#define SCARD_PROTOCOL_T0 0x0001
#define SCARD_PROTOCOL_T1 0x0002
#define SCARD_PROTOCOL_RAW 0x0004
TheSCardConnect function requests access to the smart card or the reader. Upon success, it is then possible to call
SCardTransmit.
If AccessMode is set to SCARD_AM_READER, PreferredProtocols must be set to
SCARD_PROTOCOL_UNDEFINED and CardAction toSCARD_CA_NORESET else function fails with
EFI_INVALID_PARAMETER.
EFI_SUCCESS The requested command completed successfully.
EFI_INV ALID_PARAMETER AccessMode is not valid.
EFI_INV ALID_PARAMETER CardAction is not valid.
EFI_INV ALID_PARAMETER Invalid combination of AccessMode /CardAction /PreferredProtocols.
EFI_NOT_READY A smart card is inserted but failed to return an ATR.
EFI_UNSUPPORTED PreferredProtocols does not contain an available protocol to use.
EFI_NO_MEDIA AccessMode is set to SCARD_AM_CARD but there is no smart card in-
serted.
EFI_ACCESS_DENIED Access is already locked by a previous SCardConnect call.
EFI_DEVICE_ERROR Any other error condition, typically a reader removal.
37.6. Smart Card Reader and Smart Card Edge Protocol 1790Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.6.3 EFI_SMART_CARD_READER_PROTOCOL.SCardDisconnect()
Summary
This function releases a connection previously taken by SCardConnect.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_READER_PROTOCOL_DISCONNECT) (
IN UINT32 CardAction
);
CardAction See “Related Deﬁnitions” for CardAction inSCardConnect description.
TheSCardDisconnect function releases the lock previously taken by SCardConnect. In case the smart card has been
removed before this call, this function returns EFI_SUCCESS. If there is no previous call to SCardConnect, this
function returns EFI_SUCCESS.
EFI_INV ALID_PARAMETER CardAction value is unknown.
EFI_UNSUPPORTED Reader does not support Eject card feature (disconnect was not performed).
37.6.4 EFI_SMART_CARD_READER_PROTOCOL.SCardStatus()
Summary
This function retrieves some basic information about the smart card and reader.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_READER_PROTOCOL_STATUS) (
OUT CHAR16 *ReaderName OPTIONAL,
IN OUT UINTN *ReaderNameLength OPTIONAL,
OUT UINT32 *State OPTIONAL,
OUT UINT32 *CardProtocol OPTIONAL,
OUT UINT8 *Atr OPTIONAL,
IN OUT UINTN *AtrLength OPTIONAL
);
37.6. Smart Card Reader and Smart Card Edge Protocol 1791Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
ReaderName A pointer to a NULL terminated string that will contain the reader name.
ReaderNameLength
On input, a pointer to the variable that holds the maximal size, in bytes,of ReaderName.
On output, the required size, in bytes, for ReaderName.
State Current state of the smart card reader. See “Related Deﬁnitions” below.
CardProtocol Current protocol used to communicate with the smart card. See “Related Deﬁnitions” in SCardCon-
nect.
Atr A pointer to retrieve the ATR of the smart card.
AtrLength
On input, a pointer to hold the maximum size, in bytes, of Atr(usually 33).
On output, the required size, in bytes, for the smart card ATR.
//
// Codes forstate type
//
#define SCARD_UNKNOWN 0x0000 / *state is unknown */
#define SCARD_ABSENT 0x0001 / *Card is absent */
#define SCARD_INACTIVE 0x0002 / *Card is present and not powered */
#define SCARD_ACTIVE 0x0003 / *Card is present and powered */
TheSCardStatus function retrieves basic reader and card information.
IfReaderName, State, CardProtocol orAtrisNULL , the function does not fail but does not ﬁll in such variables.
IfEFI_SUCCESS is not returned, ReaderName andAtrcontents shall not be considered as valid.
EFI_INV ALID_PARAMETER ReaderName is not NULL but ReaderNameLength is NULL
EFI_INV ALID_PARAMETER Atris not NULL butAtrLength isNULL
EFI_BUFFER_TOO_SMALL ReaderNameLength is not big enough to hold the reader name. Reader-
NameLength has been updated to the required value.
EFI_BUFFER_TOO_SMALL AtrLength is not big enough to hold the ATR. AtrLength has been updated
to the required value.
37.6. Smart Card Reader and Smart Card Edge Protocol 1792Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.6.5 EFI_SMART_CARD_READER_PROTOCOL.SCardTransmit()
Summary
This function sends a command to the card or reader and returns its response.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_READER_PROTOCOL_TRANSMIT) (
IN UINT8 *CAPDU,
IN UINTN CAPDULength,
OUT UINT8 *RAPDU,
IN OUT UINTN *RAPDULength
);
CAPDU A pointer to a byte array that contains the Command APDU to send to the smart card or reader.
CAPDULength Command APDU size, in bytes.
RAPDU A pointer to a byte array that will contain the Response APDU.
RAPDULength On input, the maximum size, in bytes, of the Response APDU. On output, the size, in bytes, of the
Response APDU.
This function sends a command to the card or reader and returns its response. The protocol to use to communicate
with the smart card has been selected through SCardConnect call.
In case RAPDULength indicates a buffer too small to hold the response APDU, the function fails with
NOTE :the caller has to call previously SCardConnect to make sure the reader/card is not already accessed by another
application or driver .
EFI_INV ALID_PARAMETER CAPDU isNULL orCAPDULength is 0.
EFI_BUFFER_TOO_SMALL RAPDULength is not big enough to hold the response APDU. RAPDU-
Length has been updated to the required value..
EFI_NO_MEDIA There is no card in the reader.
EFI_NOT_READY Card is not powered.
EFI_PROTOCOL_ERROR A protocol error has occurred.
EFI_TIMEOUT The reader did not respond.
EFI_ACCESS_DENIED A communication with the reader/card is already pending.
37.6. Smart Card Reader and Smart Card Edge Protocol 1793Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.6.6 EFI_SMART_CARD_READER_PROTOCOL.SCardControl()
Summary
This function provides direct access to the reader.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_READER_PROTOCOL_CONTROL) (
IN UINT32 ControlCode,
IN UINT8 *InBuffer OPTIONAL,
IN UINTN InBufferLength OPTIONAL,
OUT UINT8 *OutBuffer OPTIONAL,
IN OUT UINTN *OutBufferLength OPTIONAL
);
ControlCode The control code for the operation to perform. See “Related Deﬁnitions” below.
InBuffer A pointer to the input parameters.
InBufferLength Size, in bytes, of input parameters.

Summary
Prototype
typedef
);
OutBuffer A pointer to the output parameters.
OutBufferLength
On input, maximal size, in bytes, to store output parameters.
On output, the size, in bytes, of output parameters.
This function gives direct control to send commands to the driver or the reader.
TheControlCode to use is vendor dependant; the only standard code deﬁned is the one to get PC/SC part 10 features.
See “Related Deﬁnitions” below.
InBuffer andOutbuffer may be NULL when ControlCode operation does not require them.
//
// Macro to generate a ControlCode & PC/SC part 10 control code
//
#define SCARD_CTL_CODE(code) (0x42000000 + (code))
#define CM_IOCTL_GET_FEATURE_REQUEST SCARD_CTL_CODE(3400)
37.6. Smart Card Reader and Smart Card Edge Protocol 1794Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 37.31 – continued from previous page
ControlCode requires input parameters but:
•InBuffer isNULL or InBufferLenth is NULL -or-
•InBuffer is not NULL butInBufferLenth is less than
EFI_INV ALID_PARAMETER OutBuffer is not NULL butOutBufferLength isNULL
EFI_UNSUPPORTED ControlCode is not supported.
OutBufferLength is not big enough to hold the output parameters.
OutBufferLength has been updated to the required value.
EFI_NO_MEDIA There is no card in the reader and the control code speciﬁed requires one.
EFI_NOT_READY ControlCode requires a powered card to operate.
37.6.7 EFI_SMART_CARD_READER_PROTOCOL.SCardGetAttrib()
Summary
This function retrieves a reader or smart card attribute.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_READER_PROTOCOL_GET_ATTRIB) (
IN UINT32 Attrib,
OUT UINT8 *OutBuffer,
IN OUT UINTN *OutBufferLength
);
Attrib Identiﬁer for the attribute to retrieve. See “Related Deﬁnitions” below. Note that all attributes might not be
OutBuffer A pointer to a buffer that will contain attribute data.
On input, maximal size, in bytes, to store attribute data.
On output, the size, in bytes, of attribute data.
Possibly supported attrib values are listed in the PC/SC Speciﬁcation, Part 3. See References for document link.
TheSCardGetAttrib function retrieves an attribute from the reader driver.
37.6. Smart Card Reader and Smart Card Edge Protocol 1795Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_INV ALID_PARAMETER OutBuffer isNULL orOutBufferLength is 0.
EFI_BUFFER_TOO_SMALL OutBufferLength is not big enough to hold the output parameters. Out-
BufferLength has been updated to the required value.
EFI_UNSUPPORTED Attrib is not supported.
EFI_NO_MEDIA There is no card in the reader and Attrib value requires one.
EFI_NOT_READY Attrib requires a powered card to operate.
37.6.8 Smart Card Edge Protocol
The Smart Card Edge Protocol provides an abstraction for device to provide Smart Card support.
37.6.8.1 EFI_SMART_CARD_EDGE_PROTOCOL
Summary
Smart Card aware application invokes this protocol to get access to an inserted Smart Card in the reader.
GUID
#define EFI_SMART_CARD_EDGE_PROTOCOL_GUID \
{ 0xd317f29b, 0xa325, 0x4712,\
{ 0x9b, 0xf1, 0xc6, 0x19, 0x54, 0xdc, 0x19, 0x8c } }
typedef struct _EFI_SMART_CARD_EDGE_PROTOCOL {
EFI_SMART_CARD_EDGE_GET_CONTEXT GetContext;
EFI_SMART_CARD_EDGE_CONNECT Connect;
EFI_SMART_CARD_EDGE_DISCONNECT Disconnect;
EFI_SMART_CARD_EDGE_GET_CSN GetCsn;
EFI_SMART_CARD_EDGE_GET_READER_NAME GetReaderName;
EFI_SMART_CARD_EDGE_VERIFY_PIN VerifyPin;
EFI_SMART_CARD_EDGE_GET_PIN_REMAINING GetPinRemaining;
EFI_SMART_CARD_EDGE_GET_DATA GetData;
EFI_SMART_CARD_EDGE_GET_CREDENTIAL GetCredential;
EFI_SMART_CARD_EDGE_SIGN_DATA SignData;
EFI_SMART_CARD_EDGE_DECRYPT_DATA DecryptData;
EFI_SMART_CARD_EDGE_BUILD_DH_AGREEMENT BuildDHAgreement;
} EFI_SMART_CARD_EDGE_PROTOCOL;
Members
GetContext Request the driver contex.
Connect Request a connection to the Smart Card.
Disconnect Close a previously open connection.
GetCSN Get Card Serial Number.
37.6. Smart Card Reader and Smart Card Edge Protocol 1796Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetReaderName Get name of Smart Card reader used.
VerifyPin Verify Smart Card PIN.
GetPinRemaining Get number of remaining PIN tries.
GetData Get speciﬁc data.
GetCredential Get credentials the Smart Card holds.
SignData Sign a data.
DecryptData Decrypt a data.
BuildDHAgreement Construct a DH (Difﬁe Hellman) agreement for key derivation.
This protocol allows UEFI applications to interface with a Smart Card during boot process for authentication or data
signing / decryption, especially if the application has to make use of PKI.
Overview
This document aims at deﬁning a standard way for UEFI applications to use a Smart Card in PKI (Public Key Infras-
tructure) context. The key points are:
• Each Smart Card or set of Smart Card have speciﬁc behavior.
• Smart Card applications often interface with PKCS #11 API or other cryptographic interface like CNG.
• During boot process not all the possibility of a cryptographic interface, like PKCS #11, are useful, for example
it is neither the moment to perform Smart Card administration or Smart Card provisioning nor to process debit
or credit operation with Smart Card.
Consequently this protocol focused on those points:
• Offering standard access to Smart Card functionalities that:
— Authenticate User
— Sign data
— Decrypt data
— Get certiﬁcates
• With an API that is enough close with PKCS#11 API that it could be considered as a brick to build a “tiny
PKCS#11”.
• An implementation of the protocol can be dedicated to a speciﬁc Smart Card or a speciﬁc set of Smart Card.
• An implementation of the protocol shall poll for Smart Card reader attachment and removal.
• An implementation of the protocol shall poll for Smart Card insertion and removal. On insertion the protocol
shall check if it supports this Smart Card.
Typically an implementation of this protocol will lean on a Smart Card reader protocol (
EFI_SMART_CARD_READER_PROTOCOL ).
37.6. Smart Card Reader and Smart Card Edge Protocol 1797Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.6.8.2 EFI_SMART_CARD_EDGE_PROTOCOL.GetContext()
Summary
This function retrieves the context driver.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_GET_CONTEXT) (
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,
OUT UINTN *NumberAidSupported,
IN OUT UINTN *AidTableSize OPTIONAL,
OUT SMART_CARD_AID *AidTable OPTIONAL,
OUT UINTN *NumberSCPresent,
IN OUT UINTN *CsnTableSize OPTIONAL,
OUT SMART_CARD_CSN *CsnTable OPTIONAL,
OUT UINT32 *VersionScEdgeProtocol OPTIONAL
);
This Indicates a pointer to the calling context. Type EFI_SMART_CARD_EDGE_PROTOCOL is deﬁned in the
EFI_SMART_CARD_EDGE_PROTOCOL description.
NumberAidSupported Number of AIDs this protocol supports.
AidTableSize
On input, number of items allocated for the AID table.
On output, number of items returned by protocol.
AidTable Table of the AIDs supported by the protocol.
NumberSCPresent Number of currently present Smart Cards that are supported by protocol.
CsnTableSize
On input, the number of items the buffer CSN table can contain.
On output, the number of items returned by the protocol.
CsnTable Table of the CSN of the Smart Card present and supported by protocol.
VersionScEdgeProtocol EFI_SMART_CARD_EDGE_PROTOCOL version.
//
// Maximum size fora Smart Card AID (Application IDentifier)
//
#define SCARD_AID_MAXSIZE 0x0010
//
// Size of CSN (Card Serial Number)
//
#define SCARD_CSN_SIZE 0x0010
//
//Current specification version 1.00
//
#define SMART_CARD_EDGE_PROTOCOL_VERSION_1 0x00000100
// Parameters type definition
37.6. Smart Card Reader and Smart Card Edge Protocol 1798Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
typedef UINT8 SMART_CARD_AID[SCARD_AID_MAXSIZE];
typedef UINT8 SMART_CARD_CSN[SCARD_CSN_SIZE];

//
//
//
//
//
//
//
TheGetContext function returns the context of the protocol, the application identiﬁers supported by the protocol and
the number and the CSN unique identiﬁer of Smart Cards that are present and supported by protocol.
IfAidTableSize, AidTable, CsnTableSize, CsnTable orVersionProtocol is NULL, the function does not fail but does
not ﬁll in such variables.
In case AidTableSize indicates a buffer too small to hold all the protocol AID table, only the ﬁrst AidTableSize items
of the table are returned in AidTable.
In case CsnTableSize indicates a buffer too small to hold the entire table of Smart Card CSN present, only the ﬁrst
CsnTableSize items of the table are returned in CsnTable.
VersionScEdgeProtocol returns the version of the EFI_SMART_CARD_EDGE_PROTOCOL this driver uses. For this
protocol speciﬁcation value is SMART_CARD_EDGE_PROTOCOL_VERSION_1.
In case of Smart Card removal the internal CSN list is immediately updated, even if a connection is opened with that
Smart Card.
EFI_INV ALID_PARAMETER NumberSCPresent Is NULL.
37.6.8.3 EFI_SMART_CARD_EDGE_PROTOCOL. Connect()
Summary
This function establish a connection with a Smart Card the protocol support.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_CONNECT) (
OUT EFI_HANDLE *SCardHandle,
IN UINT8 *ScardCsn OPTIONAL,
OUT UINT8 *ScardAid OPTIONAL
);
SCardHandle Handle on Smart Card connection.
ScardCsn CSN of the Smart Card the connection has to be established.
ScardAid AID of the Smart Card the connection has been established.
37.6. Smart Card Reader and Smart Card Edge Protocol 1799Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheConnect function establishes a connection with a Smart Card.
In case of success the SCardHandle can be used.
If the ScardCsn isNULL the connection is established with the ﬁrst Smart Card the protocol ﬁnds in its table of Smart
Card present and supported. Else it establish context with the Smart Card whose CSN given by ScardCsn.
IfScardAid is not NULL the function returns the Smart Card AID the protocol supports.
After a successful connect the SCardHandle will remain existing even in case Smart Card removed from Smart Card
reader, but all function invoking this SCardHandle will fail. SCardHandle is released only on Disconnect.
EFI_INV ALID_PARAMETER SCardHandle isNULL .
EFI_NO_MEDIA No Smart Card supported by protocol is present, Smart Card with CSN
ScardCsn or Reader has been removed. A Disconnect should be performed.
37.6.8.4 EFI_SMART_CARD_EDGE_PROTOCOL.Disconnect()
Summary
This function releases a connection previously established by Connect.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_DISCONNECT) (
IN EFI_HANDLE SCardHandle
);
SCardHandle Handle on Smart Card connection to release.
TheDisconnect function releases the connection previously established by a Connect. In case the Smart Card or the
Smart Card reader has been removed before this call, this function returns EFI_SUCCESS.
EFI_INV ALID_PARAMETER No connection for SCardHandle value.
37.6. Smart Card Reader and Smart Card Edge Protocol 1800Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.6.8.5 EFI_SMART_CARD_EDGE_PROTOCOL.GetCsn
Summary
This function returns the Smart Card serial number.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_GET_CSN) (
IN EFI_HANDLE SCardHandle,
OUT UINT8 Csn[SCARD_CSN_SIZE]
);
Csn The Card Serial number, 16 bytes array.
TheGetCsn function returns the 16 bytes Smart Card Serial number.
EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection has been removed. A
Disconnect should be performed.
37.6.8.6 EFI_SMART_CARD_EDGE_PROTOCOL.GetReaderName
Summary
This function returns the name of the Smart Card reader used for this connection.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_GET_READER_NAME) (
IN OUT UINTN *ReaderNameLength,
OUT CHAR16 *ReaderName OPTIONAL
);
37.6. Smart Card Reader and Smart Card Edge Protocol 1801Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
On input, a pointer to the variable that holds the maximal size, in bytes, of ReaderName.
TheGetReaderName function returns the name of the Smart Card reader used for this connection.
EFI_INV ALID_PARAMETER ReaderNameLength isNULL .
37.6.8.7 EFI_SMART_CARD_EDGE_PROTOCOL.VerifyPin()
Summary
This function authenticates a Smart Card user by presenting a PIN code.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_VERIFY_PIN) (
IN INT32 PinSize,
IN UINT8 *PinCode,
OUT BOOLEAN *PinResult,
OUT UINT32 *RemainingAttempts OPTIONAL
);
PinSize PIN code buffer size.
PinCode PIN code to present to the Smart Card.
PinResult
Result of PIN code presentation to the Smart Card.
TRUE when Smart Card founds the PIN code correct.
RemainingAttempts Number of attempts still possible.
TheVerifyPin function presents a PIN code to the Smart Card.
37.6. Smart Card Reader and Smart Card Edge Protocol 1802Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
If Smart Card found the PIN code correct the user is considered authenticated to current application, and the function
returns TRUE .
Negative or null PinSize value rejected if PinCode is not NULL
ANULL PinCode buffer means the application didn’t know the PIN, in that case:
• If PinSize value is negative the caller only wants to know if the current chain of the elements Smart Card
Edge protocol, Smart Card Reader protocol and Smart Card Reader supports the Secure Pin Entry PCSC V2
functionality.
• IfPinSize value is positive or null the caller ask to perform the verify PIN using the Secure PIN Entry function-
ality.
InPinCode buffer, the PIN value is always given in plaintext, in case of secure messaging the
SMART_CARD_EDGE_PROTOCOL will be in charge of all intermediate treatments to build the correct Smart Card
APDU.
EFI_UNSUPPORTED Pinsize < 0 and Secure PIN Entry functionality not supported.
EFI_INV ALID_PARAMETER Bad value for PinSize : value not supported by Smart Card or, negative with
PinCode not null.
EFI_INV ALID_PARAMETER PinResult isNULL .
37.6.8.8 EFI_SMART_CARD_EDGE_PROTOCOL.GetPinRemaining()
Summary
This function gives the remaining number of attempts for PIN code presentation.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_GET_PIN_REMAINING) (
OUT UINT32 *RemainingAttempts
);

Summary
Prototype
typedef
);
The number of attempts to present a correct PIN is limited and depends on Smart Card and on PIN.
This function will retrieve the number of remaining possible attempts.
37.6. Smart Card Reader and Smart Card Edge Protocol 1803Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_INV ALID_PARAMETER RemainingAttempts isNULL .
37.6.8.9 EFI_SMART_CARD_EDGE_PROTOCOL.GetData()
Summary
This function returns a speciﬁc data from Smart Card.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_GET_DATA) (
IN EFI_GUID *DataId,
);
DataId The type identiﬁer of the data to get.
DataSize
On input, in bytes, the size of Data.
On output, in bytes, the size of buffer required to store the speciﬁed data.
Data The data buffer in which the data is returned. The type of the data buffer is associated with the DataId. Ignored
ifDataSize is 0.
This function returns a data from Smart Card. The function is generic for any kind of data, but driver and application
must share an EFI_GUID that identify the data.
EFI_INV ALID_PARAMETER DataId isNULL .
EFI_INV ALID_PARAMETER DataSize isNULL.
EFI_INV ALID_PARAMETER Data isNULL , and DataSize is not zero.
37.6. Smart Card Reader and Smart Card Edge Protocol 1804Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 37.40 – continued from previous page
EFI_NOT_FOUND DataId unknown for this driver.
EFI_BUFFER_TOO_SMALL The size of Data is too small for the speciﬁed data and the required size is
returned in DataSize.
EFI_ACCESS_DENIED Operation not performed, conditions not fulﬁlled. PIN not veriﬁed.
37.6.8.10 EFI_SMART_CARD_EDGE_PROTOCOL.GetCredentials()
Summary
This function retrieve credentials store into the Smart Card.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_GET_CREDENTIAL) (
IN OUT UINTN *CredentialSize,
OUT UINT8 *CredentialList OPTIONAL
);
CredentialSize
On input, in bytes, the size of buffer to store the list of credential.
On output, in bytes, the size of buffer required to store the entire list of credentials.
CredentialList List of credentials stored into the Smart Card. A list of TLV (Tag Length Value) elements organized
in containers array.
//Type of data elements incredentials list
#define SC_EDGE_TAG_HEADER 0x0000 \
// value of tag field forheader,
// the number of containers
#define SC_EDGE_TAG_CERT 0x0001 // value of tag field for certificate
#define SC_EDGE_TAG_KEY_ID 0x0002 // value of tag field for key index
// associated withcertificate
#define SC_EDGE_TAG_KEY_TYPE 0x0003 // value of tag field for key type
#define SC_EDGE_TAG_KEY_SIZE 0x0004 // value of tag field for key size
//Length of L fields of TLV items
#define SC_EDGE_L_SIZE_HEADER 1 // size of L field for header
#define SC_EDGE_L_SIZE_CERT 2 // size of L field for certificate (big endian)
#define SC_EDGE_L_SIZE_KEY_ID 1 // size of L field for key index
#define SC_EDGE_L_SIZE_KEY_TYPE 1 // size of L field for key type
#define SC_EDGE_L_SIZE_KEY_SIZE 2 // size of L field for key size (big endian)
37.6. Smart Card Reader and Smart Card Edge Protocol 1805Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//Some TLV items have a fixed value forL field
#define SC_EDGE_L_VALUE_HEADER 1 // value of L field for header
#define SC_EDGE_L_VALUE_KEY_ID 1 // value of L field for key index
#define SC_EDGE_L_VALUE_KEY_TYPE 1 // value of L field for key type
#define SC_EDGE_L_VALUE_KEY_SIZE 2 // value of L field for key size
//Possible values forkey type
#define SC_EDGE_RSA_EXCHANGE 0x01 //RSA decryption
#define SC_EDGE_RSA_SIGNATURE 0x02 //RSA signature
#define SC_EDGE_ECDSA_256 0x03 //ECDSA signature
#define SC_EDGE_ECDSA_384 0x04 //ECDSA signature
#define SC_EDGE_ECDSA_521 0x05 //ECDSA signature
#define SC_EDGE_ECDH_256 0x06 //ECDH agreement
#define SC_EDGE_ECDH_384 0x07 //ECDH agreement
#define SC_EDGE_ECDH_521 0x08 //ECDH agreement
The function returns a series of items in TLV (Tag Length Value) format.
First TLV item is the header item that gives the number of following containers (0x00, 0x01, Nb containers).
All these containers are a series of 4 TLV items:
• The certiﬁcate item (0x01, certiﬁcate size, certiﬁcate)
• The Key identiﬁer item (0x02, 0x01, key index)
• The key type item (0x03, 0x01, key type)
• The key size item (0x04, 0x02, key size), key size in number of bits.
Numeric multi-bytes values are on big endian format, most signiﬁcant byte ﬁrst:
• The L ﬁeld value for certiﬁcate (2 bytes)
• The L ﬁeld value for key size (2 bytes)
• The value ﬁeld for key size (2 bytes)
EFI_INV ALID_PARAMETER CredentialSize isNULL .
EFI_INV ALID_PARAMETER CredentialList isNULL , ifCredentialSize is not zero.
EFI_BUFFER_TOO_SMALL The size of CredentialList is too small for the speciﬁed data and the required
size is returned in CredentialSize.
37.6. Smart Card Reader and Smart Card Edge Protocol 1806Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
37.6.8.11 EFI_SMART_CARD_EDGE_PROTOCOL.SignData()
Summary
This function signs an already hashed data with a Smart Card private key.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_SIGN_DATA) (
IN UINTN KeyId,
IN UINTN KeyType,
IN EFI_GUID *HashAlgorithm,
IN EFI_GUID *PaddingMethod,
IN UINT8 *HashedData,
OUT UINT8 *SignatureData
);
KeyId Identiﬁer of the key container, retrieved in a key index item of credentials.
KeyType The key type, retrieved in a key type item of credentials.
HashAlgorithm Hash algorithm used to hash the, one of:
•EFI_HASH_ALGORITHM_SHA1_GUID
•EFI_HASH_ALGORITHM_SHA256_GUID
•EFI_HASH_ALGORITHM_SHA384_GUID
•EFI_HASH_ALGORITHM_SHA512_GUID
PaddingMethod Padding method used jointly with hash algorithm, one of:
•EFI_PADDING_RSASSA_PKCS1V1P5_GUID
•EFI_PADDING_RSASSA_PSS_GUID
HashedData Hash of the data to sign. Size is function of the HashAlgorithm.
SignatureData Resulting signature with private key KeyId. Size is function of the KeyType and key size retrieved in
the associated key size item of credentials.
//
// Padding methods GUIDs forsignature
//
//
// RSASSA- PKCS #1-V1.5 padding method, for signature
//
#define EFI_PADDING_RSASSA_PKCS1V1P5_GUID \
{0x9317ec24,0x7cb0,0x4d0e,\
37.6. Smart Card Reader and Smart Card Edge Protocol 1807Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
{0x8b,0x32,0x2e,0xd9,0x20,0x9c,0xd8,0xaf}}
//
// RSASSA-PSS padding method, forsignature
//
#define EFI_PADDING_RSASSA_PSS_GUID \
{0x7b2349e0,0x522d,0x4f8e,\
{0xb9,0x27,0x69,0xd9,0x7c,0x9e,0x79,0x5f}}
This function signs data, actually it is the hash of these data that is given to the function.
SignatureData buffer shall be big enough for signature. Signature size is function key size and key type.
EFI_INV ALID_PARAMETER KeyId is not valid.
EFI_INV ALID_PARAMETER KeyType is not valid or not corresponding to KeyId.

//
//
//
EFI_INV ALID_PARAMETER HashAlgorithm isNULL .
EFI_INV ALID_PARAMETER HashAlgorithm is not valid.
EFI_INV ALID_PARAMETER PaddingMethod isNULL .
EFI_INV ALID_PARAMETER PaddingMethod is not valid.
EFI_INV ALID_PARAMETER HashedData isNULL .
EFI_INV ALID_PARAMETER SignatureData isNULL .
37.6.8.12 EFI_SMART_CARD_EDGE_PROTOCOL.DecryptData()
Summary
This function decrypts data with a PKI/RSA Smart Card private key.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_DECRYPT_DATA) (
IN UINTN EncryptedSize,
IN UINT8 *EncryptedData,
IN OUT UINTN *PlaintextSize,
OUT UINT8 *PlaintextData
);
37.6. Smart Card Reader and Smart Card Edge Protocol 1808Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
•EFI_PADDING_NONE_GUID
•EFI_PADDING_RSAES_PKCS1V1P5_GUID
•EFI_PADDING_RSAES_OAEP_GUID
EncryptedSize Size of data to decrypt
EncryptedData Data to decrypt
PlaintextSize
On input, in bytes, the size of buffer to store the decrypted data.
On output, in bytes, the size of buffer required to store the decrypted data.
PlaintextData Buffer for decrypted data, padding removed.
//
// Padding methods GUIDs fordecryption
//
//
// No padding, fordecryption
//
#define EFI_PADDING_NONE_GUID \
{0x3629ddb1,0x228c,0x452e,\
{0xb6,0x16,0x09,0xed,0x31,0x6a,0x97,0x00}}
//
// RSAES-PKCS #1-V1.5 padding, for decryption
//
#define EFI_PADDING_RSAES_PKCS1V1P5_GUID \
{0xe1c1d0a9,0x40b1,0x4632,\
{0xbd,0xcc,0xd9,0xd6,0xe5,0x29,0x56,0x31}}
//
// RSAES-OAEP padding, fordecryption
//
#define EFI_PADDING_RSAES_OAEP_GUID \
{0xc1e63ac4,0xd0cf,0x4ce6,\
{0x83,0x5b,0xee,0xd0,0xe6,0xa8,0xa4,0x5b}}
37.6. Smart Card Reader and Smart Card Edge Protocol 1809Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The function decrypts some PKI / RSA encrypted data with private key securely stored into the Smart Card.
TheKeyId must reference a key of type SC_EDGE_RSA_EXCHANGE.
EFI_INV ALID_PARAMETER This isNULL.
EFI_INV ALID_PARAMETER KeyId is not valid or associated key not of type
SC_EDGE_RSA_EXCHANGE.
EFI_INV ALID_PARAMETER EncryptedSize is 0.
EFI_INV ALID_PARAMETER EncryptedData isNULL .
EFI_INV ALID_PARAMETER PlaintextSize isNULL .
EFI_INV ALID_PARAMETER PlaintextData isNULL .
EFI_BUFFER_TOO_SMALL PlaintextSize is too small for the plaintext data and the required size is re-
turned in PlaintextSize.
37.6.8.13 EFI_SMART_CARD_EDGE_PROTOCOL.BuildDHAgreement()
Summary
This function performs a secret Difﬁe Hellman agreement calculation that would be used to derive a symmetric en-
cryption / decryption key.
Prototype
typedef
(EFIAPI *EFI_SMART_CARD_EDGE_BUILD_DH_AGREEMENT) (
IN UINT8 *dataQx,
IN UINT8 *dataQy,
OUT UINT8 *DHAgreement
);
dataQx Public key x coordinate. Size is the same as key size for KeyId. Stored in big endian format.
dataQy Public key y coordinate. Size is the same as key size for KeyId. Stored in big endian format.
37.6. Smart Card Reader and Smart Card Edge Protocol 1810Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DHAgreement Buffer for DH agreement computed. Size must be bigger or equal to key size for KeyId.
The function compute a DH agreement that should be diversiﬁed to generate a symmetric key to proceed encryption
or decryption.
The application and the Smart Card shall agree on the diversiﬁcation process.
The KeyId must reference a key of one of the types: SC_EDGE_ECDH_256, SC_EDGE_ECDH_384 or
SC_EDGE_ECDH_521.
EFI_INV ALID_PARAMETER dataQx isNULL .
EFI_INV ALID_PARAMETER dataQy isNULL .
EFI_INV ALID_PARAMETER DHAgreement isNULL .
37.7 Memory Protection
37.7.1 EFI_MEMORY_ATTRIBUTE PROTOCOL
Summary
This protocol abstracts the memory attributes setting or getting in UEFI environment.
GUID
#define EFI_MEMORY_ATTRIBUTE_PROTOCOL_GUID \
{0xf4560cf6, 0x40ec, 0x4b4a, 0xa1, 0x92, 0xbf, 0x1d, 0x57, 0xd0,
0xb1, 0x89}
typedef struct _EFI_MEMORY_ATTRIBUTE_PROTOCOL {
EFI_GET_MEMORY_ATTRIBUTES GetMemoryAttributes;
EFI_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;
EFI_CLEAR_MEMORY_ATTRIBUTES ClearMemoryAttributes;
} EFI_MEMORY_ATTRIBUTE_PROTOCOL;
GetMemoryAttributes Get the memory attributes for a memory region. See the GetMemoryAttrbutes()
SetMemoryAttributes Set the memory attributes for a memory region. See the SetMemoryAttrbutes()
ClearMemoryAttributes Clear the memory attributes for a memory region. See the
ClearMemoryAttrbutes() function description.
37.7. Memory Protection 1811Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
TheEFI_MEMORY_ATTRIBUTE_PROTOCOL is used to abstract memory attribute access for a memory region.
37.7.1.1 EFI_MEMORY_ATTRIBUTE_PROTOCOL.GetMemoryAttributes
Summary
This service retrieves the memory attributes of a memory region.
Prototype
typedef
(EFIAPI *EFI_GET_MEMORY_ATTRIBUTES)(
IN EFI_MEMORY_ATTRIBUTE_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
OUT UINT64 *Attributes
);
This The protocol interface pointer.
BaseAddress The physical address that is the start address of a memory region.
Length The size in bytes of the memory region.
Attributes Pointer to the bit mask of memory attributes returned. The bit mask of attributes is deﬁned in
theGetMemoryMap() function description in the UEFI 2.0 speciﬁcation. The valid Attributes is
EFI_MEMORY_R ,EFI_MEMORY_XP , andEFI_MEMORY_RO .
This function retrieves the attributes of the memory region speciﬁed by BaseAddress and Length. If different attributes
are got from different part of the memory region, EFI_NO_MAPPING will be returned.
Status Code Returned
EFI_SUCCESS The attributes are got for the memory region.
EFI_INV ALID_PARAMETER Length is zero.Attributes is NULL.
EFI_NO_MAPPING Attributes are not consistent across the memory region.
EFI_UNSUPPORTED The processor does not support one or more bytes of the memory resource
range speciﬁed by BaseAddress andLength .
37.7.1.2 EFI_MEMORY_ATTRIBUTE_PROTOCOL.SetMemoryAttributes
Summary
This service sets the memory attributes of a memory region.
Prototype
typedef
(EFIAPI *EFI_SET_MEMORY_ATTRIBUTES)(
37.7. Memory Protection 1812Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
Attributes The bit mask of memory attributes. The bit mask of attributes is deﬁned in the GetMemoryMap()
function description in the UEFI 2.0 speciﬁcation. The valid Attributes isEFI_MEMORY_RP ,

Summary
Prototype
typedef
);
EFI_MEMORY_XP , andEFI_MEMORY_RO .
This function sets the given attributes of the memory region speciﬁed by BaseAddress andLength . This function
only adds new attributes with the bit mask 1 and ignores the attributes with the bit mask 0.
EFI_SUCCESS The attributes are set for the memory region.
EFI_INV ALID_PARAMETER Length is zero.Attributes speciﬁed an illegal combination of at-
tributes that cannot be set together..
EFI_UNSUPPORTED The processor does not support one or more bytes of the memory re-
source range speciﬁed by BaseAddress andLength . The bit mask
of attributes is not supported for the memory resource range speciﬁed by
BaseAddress andLength .
EFI_OUT_OF_RESOURCES Requested attributes cannot be applied due to luck of system resources.
EFI_ACCESS_DENIED Attributes for the requested memory region are controlled by system
ﬁrmware and cannot be updated via the protocol.
37.7.1.3 EFI_MEMORY_ATTRIBUTE_PROTOCOL.ClearMemoryAttributes
Summary
This service clears the memory attributes of a memory region.
Prototype
typedef
(EFIAPI *EFI_CLEAR_MEMORY_ATTRIBUTES)(
);
37.7. Memory Protection 1813Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
This function clears the given attributes of the memory region speciﬁed by BaseAddress andLength . This
function only removes new attributes with the bit mask 1 and ignore the attributes with the bit mask 0.
EFI_SUCCESS The attributes are cleared for the memory region.
tributes that cannot be cleared together..
37.7. Memory Protection 1814CHAPTER
THIRTYEIGHT
CONFIDENTIAL COMPUTING
In conﬁdential computing, a virtual ﬁrmware may support measurement and event log based upon the hardware Trusted
Execution Environment (TEE) capability. We need way to provide the abstraction for the hardware TEEs, such as Intel
Trust Domain Extension (TDX). This document describes the interface between virtual ﬁrmware and virtual guest OS.
The interfaces deﬁned in this document are optional. If the virtual ﬁrmware does not support hardware TEE based
conﬁdential computing, then the interfaces are not required. If the virtual ﬁrmware implements a virtual TPM, then
the TCG deﬁned event log, EFI_TCG2_PROTOCOL should be used, while the interfaces deﬁned in this document
should not be published.
38.1 Virtual Platform CC Event Log
If a virtual ﬁrmware with conﬁdential computing (CC) capability supports measurement and an event is created,
virtual ﬁrmware should report the event log with the same data structure in TCG Platform Firmware Proﬁle (PFP)
speciﬁcation with EFI_TCG2_EVENT_LOG_FORMAT_TCG_2 format. The index created by the virtual ﬁrmware
in the event log should be the index for the conﬁdential computing (CC) measurement register. It is CC vendor speciﬁc.
38.2 EFI_CC_MEASUREMENT_PROTOCOL
If a virtual ﬁrmware with conﬁdential computing (CC) capability supports measurement, the
virtual ﬁrmware should produce EFI_CC_MEASUREMENT_PROTOCOL with new GUID
EFI_CC_MEASUREMENT_PROTOCOL_GUID to report event log and provide hash capability.
38.2.1 EFI_CC_MEASUREMENT_PROTOCOL
Summary
This protocol abstracts the conﬁdential computing (CC) measurement operation in UEFI guest environment.
GUID
#define EFI_CC_MEASUREMENT_PROTOCOL_GUID \
{0x96751a3d, 0x72f4, 0x41a6, {0xa7, 0x94, 0xed, 0x5d, 0xe, 0x67, 0xae, 0x6b }}
typedef struct _EFI_CC_MEASUREMENT_PROTOCOL {
EFI_CC_GET_CAPABILITY GetCapability;
EFI_CC_GET_EVENT_LOG GetEventLog;
EFI_CC_HASH_LOG_EXTEND_EVENT HashLogExtendEvent;
EFI_CC_MAP_PCR_TO_MR_INDEX MapPcrToMrIndex;
} EFI_CC_MEASUREMENT_PROTOCOL;
1815Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
GetCapability
Provide protocol capability information and state information. See the GetCapability() function description.
GetEventLog
Allow a caller to retrieve the address of a given event log and its last entry. See the GetEventLog() function description.
HashLogExtendEvent
Provide callers with an opportunity to extend and optionally log events without requiring knowledge of actual CC
command. See the HashLogExtendEvent() function description.
MapPcrToMrIndex
Provide callers information on TPM PCR to CC measurement register (MR) mapping. See the MapPcrToMrIndex()
The EFI_CC_MEASUREMENT_PROTOCOL is used to abstract the CC measurement related action in CC UEFI
guest environment.
38.2.2 EFI_CC_MEASUREMENT_PROTOCOL.GetCapability
Summary
This service provides protocol capability information and state information.
Prototype
typedef
(EFIAPI *EFI_CC_GET_CAPABILITY)(
IN EFI_CC_MEASUREMENT_PROTOCOL *This,
IN OUT EFI_CC_BOOT_SERVICE_CAPABILITY *ProtocolCapability
);
This
The protocol interface pointer.
ProtocolCapability
The caller allocates memory for an EFI_CC_BOOT_SERVICE_CAPABILITY structure and sets the size ﬁeld to the
size of the structure allocated. The callee ﬁlls in the ﬁelds with the EFI protocol capability information and the current
EFI CC state information up to the number of ﬁelds which ﬁt within the size of the structure passed in.
This function provides protocol capability information and state information.
Operation completed successfully.
38.2. EFI_CC_MEASUREMENT_PROTOCOL 1816Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 38.1 – continued from previous page
One or more of the parameters are incorrect.
The ProtocolCapability variable will not be populated.
The command was unsuccessful.
The ProtocolCapability variable is too small to hold the full response. It
will be partially populated (required Size ﬁeld will be set).
//
// Allocated size of the structure
//
UINT8 Size;
//
// Version of the EFI_CC_BOOT_SERVICE_CAPABILITY structure.
// For this version of the protocol,
// the Major version shall be set to 1
//andthe Minor version shall be set to 0.
//
EFI_CC_VERSION StructureVersion;
//
// Version of the EFI CC MEASUREMENT protocol.
//
EFI_CC_VERSION ProtocolVersion;
//
// Supported hash algorithms
//
EFI_CC_EVENT_ALGORITHM_BITMAP HashAlgorithmBitmap;
//
// Bitmap of supported event log formats
//
EFI_CC_EVENT_LOG_BITMAP SupportedEventLogs;
//
// Indicate CC type
//
EFI_CC_TYPE CcType;
} EFI_CC_BOOT_SERVICE_CAPABILITY;
} EFI_CC_VERSION;
typedef UINT32 EFI_CC_EVENT_LOG_BITMAP;
38.2. EFI_CC_MEASUREMENT_PROTOCOL 1817Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef UINT32 EFI_CC_EVENT_ALGORITHM_BITMAP;
#define EFI_CC_BOOT_HASH_ALG_SHA384 0x00000004
} EFI_CC_TYPE;
#define EFI_CC_TYPE_NONE 0
// 1~0xFF: CC vendor specific. Please refer to 38.4
38.2.3 EFI_CC_PROTOCOL.GetEventLog
Summary
This service allows a caller to retrieve the address of a given event log and its last entry.
Prototype
typedef
(EFIAPI *EFI_CC_GET_EVENT_LOG)(
IN EFI_CC_EVENT_LOG_FORMAT EventLogFormat,
OUT EFI_PHYSICAL_ADDRESS *EventLogLocation,
OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry,
OUT BOOLEAN *EventLogTruncated
);
This
EventLogFormat
The type of event log for which the information is requested.
EventLogLocation
A pointer to the memory address of the event log.
EventLogLastEntry
If the event log contains more than one entry, this is a pointer to the address of the start of the last entry in the event
log in memory.
EventLogTruncated

Summary
Prototype
typedef
);
This
If the event log is missing at least one entry because one event would have exceeded the area allocated for the event,
this value is set to TRUE. Otherwise, this value will be FALSE and the event log is complete.
This function allows a caller to retrieve the address of a given event log and its last entry.
38.2. EFI_CC_MEASUREMENT_PROTOCOL 1818Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS Operation completed successfully.
EFI_INV ALID_PARAMETER One or more of the parameters are incorrect.
typedef UINT32 EFI_CC_EVENT_LOG_FORMAT;
#define EFI_CC_EVENT_LOG_FORMAT_TCG_2 0x00000002
38.2.4 EFI_CC_MEASUREMENT_PROTOCOL.HashLogExtendEvent
Summary
This service provides callers with an opportunity to extend and optionally log events without requiring knowledge of
actual CC command.
Prototype
typedef
IN UINT64 Flags,
IN EFI_PHYSICAL_ADDRESS DataToHash,
IN UINT64 DataToHashLen,
IN EFI_CC_EVENT *EfiTdEvent
);
This
Flags
Bitmap providing additional information.
DataToHash
Physical address of the start of the data buffer to be hashed.
DataToHashLen
The length in bytes of the buffer referenced by DataToHash.
EﬁCcEvent
Pointer to the data buffer containing information about the event.
This function provides callers with an opportunity to extend and optionally log events without requiring knowledge of
actual CC command. The extend operation will occur even if the function cannot create an event log entry.
38.2. EFI_CC_MEASUREMENT_PROTOCOL 1819Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table 38.3 – continued from previous page
EFI_DEVICE_ERROR The command was unsuccessful.
EFI_VOLUME_FULL The extend operation occurred, but the event could not be written to one or
more event logs.
EFI_UNSUPPORTED The PE/COFF image type is not supported.
//
// This bit isshall be set when an event shall be extended
// butnotlogged.
//
#define EFI_CC_FLAG_EXTEND_ONLY 0x0000000000000001
//
// This bit shall be set when the intent isto measure
// a PE/COFF image.
//
#define EFI_CC_FLAG_PE_COFF_IMAGE 0x0000000000000010
typedef UINT32 EFI_CC_MR_INDEX;
//
// Size of the event header itself.
//
//
// Header version. For this version of this specification,
// the value shall be 1.
//
UINT16 HeaderVersion;
//
// Index of the MR that shall be extended.
//
EFI_CC_MR_INDEX MrIndex;
//
// Type of the event that shall be extended
// (andoptionally logged).
//
UINT32 EventType;
} EFI_CC_EVENT_HEADER;
//
// Total size of the event including the Size component,
// the header andthe Event data.
//
EFI_CC_EVENT_HEADER Header;
UINT8 Event[1];
} EFI_CC_EVENT;
38.2. EFI_CC_MEASUREMENT_PROTOCOL 1820Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
38.2.5 EFI_CC_MEASUREMENT_PROTOCOL.MapPcrToMrIndex
Summary
This service provides callers information on TPM PCR to CC measurement register (MR) mapping.
Prototype
typedef
(EFIAPI *EFI_CC_MAP_PCR_TO_MR_INDEX)(
IN TCG_PCRINDEX PcrIndex,
OUT EFI_CC_MR_INDEX *MrIndex
);
This
PcrIndex
TPM PCR index.
MrIndex
CC Measurement Register index.
This function provides callers information on TPM PCR to CC measurement register (MR) mapping. This is CC
vendor speciﬁc. Please refer to 38.4.
typedef UINT32 TCG_PCRINDEX;
38.3 EFI CC Final Events Table
All events generated after the invocation of GetEventLog SHALL be stored in an instance of an
EFI_CONFIGURATION_TABLE named by the VendorGuid of EFI_CC_FINAL_EVENTS_TABLE_GUID. The as-
sociated table contents SHALL be referenced by the VendorTable of EFI_CC_FINAL_EVENTS_TABLE.
#define EFI_CC_FINAL_EVENTS_TABLE_GUID \
{0xdd4a4648, 0x2de7, 0x4665, {0x96, 0x4d, 0x21, 0xd9, 0xef, 0x5f, 0xb4, 0x46}}
38.3. EFI CC Final Events Table 1821Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// The version of this structure. It shall be set to 1.
//
UINT64 Version;
//
// Number of events recorded after invocation of GetEventLog API
//
UINT64 NumberOfEvents;
//
// List of events of type CC_EVENT.
//
//CC_EVENT Event[1];
} EFI_CC_FINAL_EVENTS_TABLE;
//
// Crypto Agile Log Entry Format.
// Itissimilar withTCG_PCR_EVENT2 exceptMrIndex.
//
TPML_DIGEST_VALUES Digests;
UINT32 EventSize;
} CC_EVENT;
38.4 Vendor Speciﬁc Information
38.4.1 Intel Trust Domain Extension
The following table shows the TPM PCR index mapping and CC event log measurement register index interpretation
for Intel TDX, where MRTD means Trust Domain Measurement Register and RTMR means Runtime Measurement
Register.
Table 38.5: Mapping for Intel TDX
TPM PCR Index CC Event Log Measurement Register In-
dexIntel TDX Measurement Register
0 0 MRTD
1, 7 1 RTMR[0]
2~6 2 RTMR[1]
8~15 3 RTMR[2]
#define EFI_CC_TYPE_INTEL_TDX 2
38.4. Vendor Speciﬁc Information 1822CHAPTER
THIRTYNINE
MISCELLANEOUS PROTOCOLS
39.1 EFI Timestamp Protocol
39.1.1 EFI_TIMESTAMP_PROTOCOL
Summary
The Timestamp protocol provides a platform independent interface for retrieving a high resolution timestamp counter.
GUID
#define EFI_TIMESTAMP_PROTOCOL_GUID \
{ 0xafbfde41, 0x2e6e, 0x4262,\
{ 0xba, 0x65, 0x62, 0xb9, 0x23, 0x6e, 0x54, 0x95 }}
typedef struct _ EFI_TIMESTAMP_PROTOCOL {
TIMESTAMP_GET GetTimestamp;
TIMESTAMP_GET_PROPERTIES GetProperties;
} EFI_TIMESTAMP_PROTOCOL;
39.1.2 EFI_TIMESTAMP_PROTOCOL.GetTimestamp()
Summary
Retrieves the current timestamp counter value.
Prototype
typedef
UINT64
(EFIAPI *TIMESTAMP_GET) (
VOID
);
Retrieves the current value of a 64-bit free running timestamp counter.
The counter shall count up in proportion to the amount of time that has passed. The counter value will always roll over
to zero. The properties of the counter can be retrieved from GetProperties().
The caller should be prepared for the function to return the same value twice across successive calls. The counter
value will not go backwards other than when wrapping, as deﬁned by EndValue in GetProperties().
1823Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The frequency of the returned timestamp counter value must remain constant. Power management operations that
affect clocking must not change the returned counter frequency. The quantization of counter value updates may vary
as long as the value reﬂecting time passed remains consistent.
Return Value
The current value of the free running timestamp counter.
39.1.3 EFI_TIMESTAMP_PROTOCOL.GetProperties()
Summary
Obtains timestamp counter properties including frequency and value limits.
Prototype
typedef
(EFIAPI *TIMESTAMP_GET_PROPERTIES) (
OUT EFI_TIMESTAMP_PROPERTIES *Properties
);
Properties The properties of the timestamp counter. See”Related Deﬁnitions” below.
Retrieves the timestamp counter properties structure.
UINT64 Frequency;
UINT64 EndValue;
} EFI_TIMESTAMP_PROPERTIES;
Frequency The frequency of the timestamp counter in Hz.
EndValue The value that the timestamp counter ends with immediately before it rolls over. For example, a 64-bit free
running counter would have an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter would have
an EndValue of 0xFFFFFF.
EFI_SUCCESS The properties were successfully retrieved.
EFI_DEVICE_ERROR An error occurred trying to retrieve the properties of the timestamp counter
subsystem. Properties is not updated.
EFI_INV ALID_PARAMETER Properties isNULL .
39.1. EFI Timestamp Protocol 1824Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
39.2 Reset Notiﬁcation Protocol
39.2.1 EFI_RESET_NOTIFICATION_PROTOCOL
Summary
This protocol provides services to register for a notiﬁcation when ResetSystem is called.
GUID
#define EFI_RESET_NOTIFICATION_PROTOCOL_GUID \
{ 0x9da34ae0, 0xeaf9, 0x4bbf, \
{ 0x8e, 0xc3, 0xfd, 0x60, 0x22, 0x6c, 0x44, 0xbe } }
typedef struct _EFI_RESET_NOTIFICATION_PROTOCOL {

Summary
GUID
EFI_REGISTER_RESET_NOTIFY RegisterResetNotify;
EFI_UNREGISTER_RESET_NOTIFY UnRegisterResetNotify;
} EFI_RESET_NOTIFICATION_PROTOCOL;
RegisterResetNotify Register a notiﬁcation function to be called when ResetSystem() is called.
UnRegisterResetNotify Removes a reset notiﬁcation function that has been previously registered with RegisterRe-
setNotify().
39.2.2 EFI_RESET_NOTIFICATION_PROTOCOL.RegisterResetNotify()
Summary
Register a notiﬁcation function to be called when ResetSystem() is called.
Prototype
typedef
(EFIAPI *EFI_REGISTER_RESET_NOTIFY) (
IN EFI_RESET_NOTIFICATION_PROTOCOL *This,
IN EFI_RESET_SYSTEM *ResetFunction,
);
This A pointer to the EFI_RESET_NOTIFICATION_PROTOCOL instance.
ResetFunction Points to the function to be called when a ResetSystem() is executed.
The RegisterResetNotify() function registers a notiﬁcation function that is called when ResetSystem() is called and
prior to completing the reset of the platform.
The registered functions must not perform a platform reset themselves. These notiﬁcations are intended only for the
notiﬁcation of components which may need some special-purpose maintenance prior to the platform resetting.
The list of registered reset notiﬁcation functions are processed if ResetSystem() is called before ExitBootServices() .
The list of registered reset notiﬁcation functions is ignored if ResetSystem() is called after ExitBootServices() .
39.2. Reset Notiﬁcation Protocol 1825Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
EFI_SUCCESS The reset notiﬁcation function was successfully registered.
EFI_INV ALID_PARAMETER ResetFunction is NULL .
EFI_OUT_OF_RESOURCES There are not enough resources available to register the reset notiﬁcation
function.
EFI_ALREADY_STARTED The reset notiﬁcation function speciﬁed by ResetFunction has already been
registered.
39.2.3 EFI_RESET_NOTIFICATION_PROTOCOL.UnregisterResetNotify()
Summary
Unregister a notiﬁcation function.
Prototype
typedef
(EFIAPI *EFI_UNREGISTER_RESET_NOTIFY) (
IN EFI_RESET_SYSTEM *ResetFunction
);
ResetFunction The pointer to the ResetFunction being unregistered.
The UnregisterResetNotify() function removes the previously registered notiﬁcation using RegisterResetNotify().
EFI_SUCCESS The reset notiﬁcation function was unregistered.
EFI_INV ALID_PARAMETER The reset notiﬁcation function speciﬁed by ResetFunction was not previ-
ously registered using RegisterResetNotify().
39.2. Reset Notiﬁcation Protocol 1826APPENDIX
A
GUID AND TIME FORMATS
All EFI GUIDs (Globally Unique Identiﬁers) have the format described in RFC 4122 and comply with the referenced
algorithms for generating GUIDs. It should also be noted that TimeLow, TimeMid, TimeHighAndVersion ﬁelds in the
EFI are encoded as little endian. The following table deﬁnes the format of an EFI GUID (128 bits).
Table A.1: EFI GUID Format
TimeLow 0 4 The low ﬁeld of the timestamp.
TimeMid 4 2 The middle ﬁeld of the timestamp.
TimeHighAndVersion 6 2 The high ﬁeld of the timestamp multiplexed with the version number.
ClockSeqHighAndReserved 8 1 The high ﬁeld of the clock sequence multiplexed with the variant.
ClockSeqLow 9 1 The low ﬁeld of the clock sequence.
Node 10 6 The spatially unique node identiﬁer. This can be based on any IEEE 802
address obtained from a network card. If no network card exists in the
system, a crypto graphic-quality random number can be used.
This appendix for GUID deﬁnes a 60-bit timestamp format that is used to generate the GUID. All EFI time information
is stored in 64-bit structures that contain the following format: The timestamp is a 60-bit value containing a count of
100-nanosecond intervals since 00:00:00.00, 15 October 1582 (the date of Gregorian reform to the Christian calendar).
This time value will not roll over until the year 3400 AD. It is assumed that a future version of the EFI speciﬁcation
can deal with the year-3400 issue by extending this format if necessary.
This speciﬁcation also deﬁnes a standard text representation of the GUID. This format is also sometimes called the
“registry format”. It consists of 36 characters, as follows:
aabbccdd-eeff-gghh-iijj-kkllmmnnoopp:
The pairs aa-ppare two characters in the range ‘0’-‘9’, ‘a’-‘f’ or ‘A’-F’, with each pair representing a single byte
hexadecimal value.
The following table describes the relationship between the text representation and a 16-byte buffer, the structure
deﬁned in EFI GUID Format and the EFI_GUID structure.
Table A.2: Text representation relationships
String Offset
In
BufferRelationship to EFI GUID Format Relationship To EFI_GUID
aa 3 TimeLow[24:31] Data1[24:31]
bb 2 TimeLow[16:23] Data1[16:23]
cc 1 TimeLow[8:15] Data1[8:15]
1827Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table A.2 – continued from previous page
dd 0 TimeLow[0:7] Data1[0:7]
ee 5 TimeMid[8:15] Data2[8:15]
ff 4 TimeMid[0:7] Data2[0:7]
gg 7 TimeHigh AndVersion[8:15] Data3[8:15]
hh 6 TimeHig hAndVersion[0:7] Data3[0:7]
ii 8 ClockSeqHigh AndReserved[0:7] Data4[0:7]
jj 9 ClockSeqLow[0:7] Data4[8:15]
kk 10 Node[0:7] Data4[16:23]
ll 11 Node[8:15] Data4[24:31]
mm 12 Node[16:23] Data4[32:39]
nn 13 Node[24:31] Data4[40:47]
oo 14 Node[32:39] Data4[48:55]
pp 15 Node[40:47] Data4[56:63]
1828APPENDIX
B
CONSOLE
The EFI console was designed to allow input from a wide variety of devices. This appendix provides examples of the
mapping of keyboard input from various types of devices to EFI scan codes. While representative of common console
devices in use today, it is not intended to be a comprehensive list. EFI application programmers can use this table to
identify the EFI Scan Code generated by a speciﬁc key press. The description of the example device input data that
generates a EFI Scan Code may be useful to EFI driver writers, as well as showing the limitations on which EFI Scan
codes can be generated by different types of console input devices.
The EFI console was designed so that it could map to common console devices. This appendix explains how an EFI
console could map to a VGA with PC AT 101/102, PC ANSI, or ANSI X3.64 consoles.
B.1 EFI_SIMPLE_TEXT_INPUT_PROTOCOL and EFI_SIMPLE_TEXT
_INPUT_EX_PROTOCOL
Tables EFI Scan Codes for EFI_SIMPLE_TEXT_INPUT_PROTOCOL and EFI Scan Codes for
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL give examples of how input from a set of common input de-
vices is mapped to EFI scan codes. Terminals and terminal emulators generally report function and editing keys as
escape or control sequences. These sequences are formed by a control character followed by one or more additional
graphic characters that indicate what the sequence means. ANSI X3.64 terminals generally require an ANSI parser
to determine how to interpret a sequence and how to determine that the sequence is complete. These terminals can
generate sequences using either 8-bit controls or 7-bit control sequences. Older terminal types, such as the VT100+
have a simpler set of sequences that can be interpreted using simple case statements. These terminals usually generate
only 7-bit data, and 7-bit control sequences.
In the tables below, the CSI character is the 8-bit control character 0x9B, and is equivalent to the 7-bit control sequence
“ESC [” (the 0x1B control ESC followed by the left bracket character 0x5B). The sequences are shown with spaces
for readability, but do not contain the space character.
The VT100+ column represents a common class of terminal emulation that is a superset of the Digital Equipment
Corporation (DEC) VT100 terminal. This includes VT-UTF8 (Hyperterm) and PC_ANSI terminal types. The ANSI
X3.64 column shows the sequences generated by the DEC VT200 through VT500 terminals, which are an ANSI X3.64
/ ISO 6429 compliant.
The USB HID and AT 101/102 columns show the scan codes generated by two common directly attached keyboards.
These keyboards are generally used in combination with a VGA text display to form a “VGA Console”.
In the table below, the cells with N/A contained in them are simply intended to reﬂect that the key may be deﬁned
for that terminal or keyboard, but there is no industry standard or consistent mapping for the key. Some input devices
might not implement all of these keys.
1829Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table B.1: EFI Scan Codes for
EFI_SIMPLE_TEXT_INPUT_PROTOCOL
EFI Scan Code Description ANSI X3.64 /
DEC VT200-
500 (8-bit
mode)VT100+ (7-bit
mode)USB Keyboard
HID ValuesAT 101/102
Keyboard Scan
Codes
0x00 Null scan code N/A N/A 0x00 N/A
0x01 UP ARROW CSI A ESC [ A 0x52 0xe0, 0x48
0x02 DOWN AR-
ROWCSI B ESC [ B 0x51 0xe0, 0x50
0x03 RIGHT AR-
ROWCSI C ESC [ C 0x4F 0xe0, 0x4d

DEC VT200-
500 (8-bit
Codes
0x04 LEFT ARROW CSI D ESC [ D 0x50 0xe0, 0x4b
0x05 Home CSI 1 ~ ESC h 0x4A 0xe0, 0x47
0x06 End CSI 4 ~ ESC k 0x4D 0xe0, 0x4f
0x07 Insert CSI 2 ~ ESC + 0x49 0xe0, 0x52
0x08 Delete CSI 3 ~ ESC - 0x4C 0xe0, 0x53
0x09 Page Up CSI 5 ~ ESC ? 0x4B 0xe0, 0x49
0x0a Page Down CSI 6 ~ ESC / 0x4E 0xe0, 0x51
0x0b Function 1 CSI 1 1 ~ ESC 1 0x3A 0x3b
0x0c Function 2 CSI 1 2 ~ ESC 2 0x3B 0x3c
0x0d Function 3 CSI 1 3 ~ ESC 3 0x3C 0x3d
0x0e Function 4 CSI 1 4 ~ ESC 4 0x3D 0x3e
0x0f Function 5 CSI 1 5 ~ ESC 5 0x3E 0x3f
0x10 Function 6 CSI 1 7 ~ ESC 6 0x3F 0x40
0x11 Function 7 CSI 1 8 ~ ESC 7 0x40 0x41
0x12 Function 8 CSI 1 9 ~ ESC 8 0x41 0x42
0x13 Function 9 CSI 2 0 ~ ESC 9 0x42 0x43
0x14 Function 10 CSI 2 1 ~ ESC 0 0x43 0x44
0x17 Escape ESC ESC 0x29 0x01
Table B.2: EFI Scan Codes for
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL
EFI Scan Code De scription ANSI X3.64 /
DEC VT200-
500 (8-bit
Codes
0x15 Function 11 CSI 2 3 ~ ESC ! 0x44 0x57
0x16 Function 12 CSI 2 4 ~ ESC @ 0x45 0x58
0x48 Pause N/A N/A 0x48 0xe1, 0x1d,
0x45
0x68 Function 13 CSI 2 5 ~ N/A 0x68 N/A
0x69 Function 14 CSI 2 6 ~ N/A 0x69 N/A
0x6A Function 15 CSI 2 7 ~ N/A 0x6A N/A
0x6B Function 16 CSI 2 8 ~ N/A 0x6B N/A
0x6C Function 17 CSI 2 9 ~ N/A 0x6C N/A
0x6D Function 18 CSI 3 0 ~ N/A 0x6D N/A
0x6E Function 19 CSI 3 1 ~ N/A 0x6E N/A
0x6F Function 20 CSI 3 2 ~ N/A 0x6F N/A
0x70 Function 21 N/A N/A 0x70 N/A
B.1. EFI_SIMPLE_TEXT_INPUT_PROTOCOL and EFI_SIMPLE_TEXT _INPUT_EX_PROTOCOL 1830Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table B.2 – continued from previous page
0x71 Function 22 N/A N/A 0x71 N/A
0x72 Function 23 N/A N/A 0x72 N/A
0x73 Function 24 N/A N/A 0x73 N/A
0x7F Mute N/A N/A 0x7F N/A
0x80 V olume Up N/A N/A 0x80 N/A
0x81 V olume Down N/A N/A 0x81 N/A
0x100 B rightness Up N/A N/A N/A N/A
0x101 B rightness
DownN/A N/A N/A N/A
0x102 Suspend N/A N/A N/A N/A
0x103 Hibernate N/A N/A N/A N/A
0x104 Toggle Display N/A N/A N/A N/A
0x105 Recovery N/A N/A N/A N/A
0x106 Eject N/A N/A N/A N/A
0x80 00-
0xFFFFOEM Reserved N/A N/A N/A N/A
B.2 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL for PC ANSI or ANSI
X3.64 terminals
Table below deﬁnes how the programmatic methods of the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOs could be
implemented as PC ANSI or ANSI X3.64 terminals. Detailed descriptions of PC ANSI and ANSI X3.64 escape
sequences are as follows. The same type of operations can be supported via a PC AT type INT 10h interface.
Table B.3: Control Sequences to Implement
PC ANSI Codes ANSI
X3.64
CodesDescription
ESC [ 2 J CSI 2 J Clear Display Screen.
ESC [ 0 m CSI 0 m Normal Text.
ESC [ 1 m CSI 1 m Bright Text.
ESC [ 7 m CSI 7 m Reversed Text.
ESC [ 30 m CSI 30 m Black foreground, compliant with ISO Standard 6429.
ESC [ 31 m CSI 31 m Red foreground, compliant with ISO Standard 6429.
ESC [ 32 m CSI 32 m Green foreground, compliant with ISO Standard 6429.
ESC [ 33 m CSI 33 m Yellow foreground, compliant with ISO Standard 6429.
ESC [ 34 m CSI 34 m Blue foreground, compliant with ISO Standard 6429.
ESC [ 35 m CSI 35 m Magenta foreground, compliant with ISO Standard 6429.
ESC [ 36 m CSI 36 m Cyan foreground, compliant with ISO Standard 6429.
ESC [ 37 m CSI 37 m White foreground, compliant with ISO Standard 6429.
ESC [ 40 m CSI 40 m Black background, compliant with ISO Standard 6429.
ESC [ 41 m CSI 41 m Red background, compliant with ISO Standard 6429.
ESC [ 42 m CSI 42 m Green background, compliant with ISO Standard 6429.
ESC [ 43 m CSI 43 m Yellow background, compliant with ISO Standard 6429.
ESC [ 44 m CSI 44 m Blue background, compliant with ISO Standard 6429.
ESC [ 45 m CSI 45 m Magenta background, compliant with ISO Standard 6429.
ESC [ 46 m CSI 46 m Cyan background, compliant with ISO Standard 6429.
B.2. EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL for PC ANSI or ANSI X3.64 terminals 1831Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table B.3 – continued from previous page
ESC [ 47 m CSI 47 m White background, compliant with ISO Standard 6429.
ESC [ = 3 h CSI = 3 h Set Mode 80x25 color.
ESC [ row;col H CSI
row;col
HSet cursor position to row;col. Row and col are strings of ASCII digits.
Table B.4: Example Keyboard Layout
Usage EFI_KEY enum value USB Keyboard HID Val-
uesTypical AT-101 key posi-
tion
Key a and A EﬁKeyC1 0x04 31
Key b and B EﬁKeyB5 0x05 50
Key c and C EﬁKeyB3 0x06 48
Key d and D EﬁKeyC3 0x07 33
Key e and E EﬁKeyD3 0x08 19
Key f and F EﬁKeyC4 0x09 34
Key g and G EﬁKeyC5 0x0A 35
Key h and H EﬁKeyC6 0x0B 36
Key i and I EﬁKeyD8 0x0C 24
Key j and J EﬁKeyC7 0x0D 37
Key k and K EﬁKeyC8 0x0E 38
Key l and L EﬁKeyC9 0x0F 39
Key m and M EﬁKeyB7 0x10 52
Key n and N EﬁKeyB6 0x11 51
Key o and O EﬁKeyD9 0x12 25
Key p and p EﬁKeyD10 0x13 26
Key q and Q EﬁKeyD1 0x14 17
Key r and R EﬁKeyD4 0x15 20
Key s and S EﬁKeyC2 0x16 32
Key t and T EﬁKeyD5 0x17 21
Key u and U EﬁKeyD7 0x18 23
Key v and V EﬁKeyB4 0x19 49
Key w and W EﬁKeyD2 0x1A 18
Key x and X EﬁKeyB2 0x1B 47
Key y and Y EﬁKeyD6 0x1C 22
Key z and Z EﬁKeyB1 0x1D 46
Key 1 and ! EﬁKeyE1 0x1E 2
Key 2 and @ EﬁKeyE2 0x1F 3
Key 3 and # EﬁKeyE3 0x20 4
Key 4 and $ EﬁKeyE4 0x21 5
Key 5 and % EﬁKeyE5 0x22 6
Key 6 and ^ EﬁKeyE6 0x23 7
Key 7 and & EﬁKeyE7 0x24 8
Key 8 and * EﬁKeyE8 0x25 9
Key 9 and ( EﬁKeyE9 0x26 10
Key 0 and ) EﬁKeyE10 0x27 11
Enter* EﬁKeyEnter 0x28 43
Escape * EﬁKeyEsc 0x29 110
Del * / Backspace * EﬁKeyBackSpace 0x2A 15
Tab * EﬁKeyTab 0x2B 16
B.2. EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL for PC ANSI or ANSI X3.64 terminals 1832Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table B.4 – continued from previous page
Spacebar EﬁKeySpaceBar 0x2C 61
Key - and _ EﬁKeySpaceBar 0x2D 12
Key = and + EﬁKeySpaceBar 0x2E 13
Key [ and { EﬁKeySpaceBar 0x2F 27
Key ] and } EﬁKeyD12 0x30 28
Key and | EﬁKeyD13 0x31 29
Key ; and : EﬁKeyC10 0x33 40
Key ‘ and “ EﬁKeyC11 0x34 41
Key `and ~ EﬁKeyE0 0x35 1
Key , and < EﬁKeyB8 0x36 53
Key . and > EﬁKeyB9 0x37 54
Key / and ? EﬁKeyB10 0x38 55
Capslock * EﬁKeyCapsLock 0x39 30
F1* EﬁKeyF1 0x3A 112
F2* EﬁKeyF2 0x3B 113
F3* EﬁKeyF3 0x3C 114
F4* EﬁKeyF4 0x3D 115
F5* EﬁKeyF5 0x3E 116
F6* EﬁKeyF6 0x3F 117
F7* EﬁKeyF7 0x40 118
F8* EﬁKeyF8 0x41 119
F9* EﬁKeyF9 0x42 120
F10* EﬁKeyF10 0x43 121
F11* EﬁKeyF11 0x44 122
F12* EﬁKeyF12 0x45 123
PrintScreen* EﬁKeyPrint 0x46 124
ScrollLock* EﬁKeySLck 0x47 125
Pause* EﬁKeyPause 0x48 126
Insert* EﬁKeyIns 0x49 75
Home* EﬁKeyHome 0x4A 80
PageUp* EﬁKeyPgUp 0x4B 85
Delete* EﬁKeyDel 0x4C 76
End* EﬁKeyEnd 0x4D 81
PageDown* EﬁKeyPgDn 0x4E 86
RightArrow* EﬁKeyRightArrow 0x4F 89
LeftArrow* EﬁKeyLeftArrow 0x50 79
DownArrow* EﬁKeyDownArrow 0x51 84
UpArrow* EﬁKeyUpArrow 0x52 83
NumLock* EﬁKeyNLck 0x53 90
Keypad / EﬁKeySlash 0x54 95
Keypad * EﬁKeyAsterisk 0x55 100
Keypad - EﬁKeyMinus 0x56 105
Keypad + EﬁKeyPlus 0x57 106
Keypad Enter* EﬁKeyEnter 0x58 108
Keypad 1 and End* EﬁKeyOne 0x59 93
Keypad 2 and DownAr-
row*EﬁKeyTwo 0x5A 98
Keypad 3 and EﬁKeyThree PageDown* 0x5B 103
Keypad 4 and LeftArrow* EﬁKeyFour 0x5C 92
Keypad 5 EﬁKeyFive 0x5D 97
B.2. EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL for PC ANSI or ANSI X3.64 terminals 1833Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Keypad 6 and RightArrow
*EﬁKeySix 0x5E 102
Keypad 7 and Home * EﬁKeySeven 0x5F 91
Keypad 8 and UpArrow* EﬁKeyEight 0x60 96
Keypad 9 and PageUp * EﬁKeyNine 0x61 101
Keypad 0 and Insert * EﬁKeyZero 0x62 99
Keypad . and Delete * EﬁKeyPeriod 0x63 104
Menu EﬁKeyA4 0x76 n/a
LeftControl* EﬁKeyLCtrl 0xE0 58
LeftShift* EﬁKeyLShift 0xE1 44
LeftAlt* EﬁKeyLAlt 0xE2 60
LeftLogo* EﬁKeyA0 0xE3 127
RightControl* EﬁKeyRCtrl 0xE4 64
RightShift* EﬁKeyRShift 0xE5 57
RightAlt* EﬁKeyA2 0xE6 62
RightLogo* EﬁKeyA3 0xE7 128
Non-US # and ~ EﬁKeyC12 0x32 42
Non-US and | EﬁKeyIntl0 0x64 45
Non-US and _ EﬁKeyIntl1 0x87 56
Non-US ¥ and | EﬁKeyIntl3 0x89 n/a
An * indicates a non-printable character or keyboard behavior
B.2. EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL for PC ANSI or ANSI X3.64 terminals 1834APPENDIX
C
DEVICE PATH EXAMPLES
This appendix presents an example EFI Device Path and explains its relationship to the ACPI name space. An example
system design is presented along with its corresponding ACPI name space. These physical examples are mapped back
to EFI Device Paths.
C.1 Example Computer System
The Figure below, Example Computer System , represents a hypothetical computer system architecture that will be used
to discuss the construction of EFI Device Paths. The system consists of a memory controller that connects directly to
the processors’ front side bus. The memory controller is only part of a larger chipset, and it connects to a root PCI host
bridge chip, and a secondary root PCI host bridge chip. The secondary PCI host bridge chip produces a PCI bus that
contains a PCI to PCI bridge. The root PCI host bridge produces a PCI bus, and also contains USB, ATA66, and AC

C
’97 controllers. The root PCI host bridge also contains an LPC bus that is used to connect a SIO (Super IO) device.
The SIO contains a PC-AT-compatible ﬂoppy disk controller, and other PC-AT-compatible devices like a keyboard
Fig. C.1: Example Computer System
The remainder of this appendix describes how to construct a device path for three example devices from the system in
Example Computer System . The following is a list of the examples used:
• Legacy ﬂoppy
• IDE Disk
• Secondary root PCI bus with PCI to PCI bridge
1835Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The Figure below is a partial ACPI name space for the system in the Figure Example Computer System . Figure
Partial ACPI Name Space for Example System is based on Figure 5-3 in the Advanced Conﬁguration and Power
Interface Speciﬁcation .
Fig. C.2: Partial ACPI Name Space for Example System
C.2 Legacy Floppy
The legacy ﬂoppy controller is contained in the SIO chip that is connected root PCI bus host bridge chip. The root PCI
host bridge chip produces PCI bus 0, and other resources that appear directly to the processors in the system.
In ACPI this conﬁguration is represented in the _SB, system bus tree, of the ACPI name space. PCI0 is a child of _SB
and it represents the root PCI host bridge. The SIO appears to the system to be a set of ISA devices, so it is represented
as a child of PCI0 with the name ISA0. The ﬂoppy controller is represented by FLPY as a child of the ISA0 bus.
The EFI Device Path for the legacy ﬂoppy is deﬁned in the Table below, Legacy Floppy Device Path . It would contain
entries for the following things:
• Root PCI Bridge. ACPI Device Path _HID PNP0A03, _UID 0. ACPI name space \_SB\PCI0
• PCI to ISA Bridge. PCI Device Path with device and function of the PCI to ISA bridge. ACPI name space
\_SB\PCI0\ISA0
• Floppy Plug and Play ID. ACPI Device Path _HID PNP0303, _UID 0. ACPI name space \_SB\PCI0\ISA0\FLPY
• End Device Path
Table C.1: Legacy Floppy Device Path
Byte
2 2 0x0C Length
4 4 0x41D0,
0x0A03_HID PNP0A03 - 0x41D0 represents the compressed string ‘PNP’ and is encoded in
the low order bytes. The compression method is described in the ACPI Speciﬁcation.
C 1 0x01 Generic Device Path Header - Type Hardware Device Path
C.2. Legacy Floppy 1836Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table C.1 – continued from previous page
D 1 0x01 Sub type PCI Device Path
E 2 0x06 Length
10 1 0x00 PCI Function
11 1 0x10 PCI Device
12 1 0x02 Generic Device Path Header - Type ACPI Device Path
13 1 0x01 Sub type - ACPI Device Path
14 2 0x0C Length
16 4 0x41D0,
0x0303_HID PNP0303
1A 4 0x0000 _UID
1E 1 0x7F Generic Device Path Header - Type End of Hardware Device Path
1F 1 0xFF Sub type - End Device Path
20 2 0x04 Length
C.3 IDE Disk
The IDE Disk controller is a PCI device that is contained in a function of the root PCI host bridge. The root PCI host
bridge is a multi function device and has a separate function for chipset registers, USB, and IDE. The disk connected
to the IDE ATA bus is deﬁned as being on the primary or secondary ATA bus, and of being the master or slave device
on that bus.
and it represents the root PCI host bridge. The IDE controller appears to the system to be a PCI device with some
legacy properties, so it is represented as a child of PCI0 with the name IDE0. PRIM is a child of IDE0 and it represents
the primary ATA bus of the IDE controller. MAST is a child of PRIM and it represents that this device is the ATA
master device on this primary ATA bus.
The EFI Device Path for the PCI IDE controller is deﬁned in the Table IDE Disk Device Path . It would contain entries
for the following things:
• PCI IDE controller. PCI Device Path with device and function of the IDE controller. ACPI name space
\_SB\PCI0\IDE0
• ATA Address. ATA Messaging Device Path for Primary bus and Master device. ACPI name space
\_SB\PCI0\IDE0\PRIM\MAST
C.3. IDE Disk 1837Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table C.2: IDE Disk Device Path
Byte
4 4 0x41D0,
10 1 0x01 PCI Function
12 1 0x03 Generic Device Path Header - Messaging Device Path
13 1 0x01 Sub type - ATAPI Device Path
14 2 0x06 Length
16 1 0x00 Primary =0, Secondary = 1
17 1 0x00 Master = 0, Slave = 1
18 2 0x0000 LUN
1A 1 0x7F Generic Device Path Header - Type End of Hardware Device Path
1B 1 0xFF Sub type - End Device Path
1C 2 0x04 Length
C.4 Secondary Root PCI Bus with PCI to PCI Bridge
The secondary PCI host bridge materializes a second set of PCI buses into the system. The PCI buses on the secondary
PCI host bridge are totally independent of the PCI buses on the root PCI host bridge. The only relationship between
the two is they must be conﬁgured to not consume the same resources. The primary PCI bus of the secondary PCI host
bridge also contains a PCI to PCI bridge. There is some arbitrary PCI device plugged in behind the PCI to PCI bridge
in a PCI slot.
In ACPI this conﬁguration is represented in the _SB, system bus tree, of the ACPI name space. PCI1 is a child of
_SB and it represents the secondary PCI host bridge. The PCI to PCI bridge and the device plugged into the slot on
its primary bus are not described in the ACPI name space. These devices can be fully conﬁgured by following the
applicable PCI speciﬁcation.
The EFI Device Path for the secondary root PCI bridge with a PCI to PCI bridge is deﬁned in the Table Secondary
Root PCI Bus with PCI to PCI Bridge Device Path . It would contain entries for the following things:
• Root PCI Bridge. ACPI Device Path _HID PNP0A03, _UID 1. ACPI name space \_SB\PCI1
• PCI to PCI Bridge. PCI Device Path with device and function of the PCI Bridge. ACPI name space \_SB\PCI1,
PCI to PCI bridges are deﬁned by PCI speciﬁcation and not ACPI.
• PCI Device. PCI Device Path with the device and function of the PCI device. ACPI name space \_SB\PCI1,
PCI devices are deﬁned by PCI speciﬁcation and not ACPI.
• End Device Path.
C.4. Secondary Root PCI Bus with PCI to PCI Bridge 1838Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table C.3: Secondary Root PCI Bus with PCI to PCI Bridge Device Path
Byte
4 4 0x41D0,
8 4 0x0001 _UID
10 1 0x00 PCI Function for PCI to PCI bridge
11 1 0x0c PCI Device for PCI to PCI bridge
13 1 0x01 Sub type PCI Device Path
14 2 0x08 Length
16 1 0x00 PCI Function for PCI Device
17 1 0x00 PCI Device for PCI Device
18 1 0x7F Generic Device Path Header - Type End of Hardware Device Path
19 1 0xFF Sub type - End Device Path
1A 2 0x04 Length
C.5 ACPI Terms
Names in the ACPI name space that start with an underscore (“_”) are reserved by the ACPI speciﬁcation and have
architectural meaning. All ACPI names in the name space are four characters in length. The following four ACPI
names are used in this speciﬁcation.
_ADR . The Address on a bus that has standard enumeration. An example would be PCI, where the enumeration
method is described in the PCI Local Bus speciﬁcation.
_CRS . The current resource setting of a device. A _CRS is required for devices that are not enumerated in a standard
fashion. _CRS is how ACPI converts nonstandard devices into Plug and Play devices.
_HID . Represents a device’s Plug and Play hardware ID, stored as a 32-bit compressed EISA ID. _HID objects are
optional in ACPI. However, a _HID object must be used to describe any device that will be enumerated by the ACPI
driver in the OS. This is how ACPI deals with non-Plug and Play devices.
_UID . Is a serial number style ID that does not change across reboots. If a system contains more than one device that

reports the same _HID, each device must have a unique _UID. The _UID only needs to be unique for device that have
the exact same _HID value.
C.5. ACPI Terms 1839Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
C.6 EFI Device Path as a Name Space
The Figure below shows the EFI Device Path for the example system represented as a name space. The Device Path
can be represented as a name space, but EFI does support manipulating the Device Path as a name space. You can
only access Device Path information by locating the DEVICE_PATH_INTERFACE from a handle. Not all the nodes
in a Device Path will have a handle.
Fig. C.3: EFI Device Path Displayed As a Name Space
C.6. EFI Device Path as a Name Space 1840APPENDIX
D
STATUS CODES
EFI interfaces return an EFI_STATUS code. See EFI_STATUS Success Codes (High Bit Clear) ,EFI_STATUS Error
Codes (High Bit Set) ,EFI_STATUS Warning Codes (High Bit Clear) list these codes for success, errors, and warnings,
respectively. The range of status codes that have the highest bit set and the next to highest bit clear are reserved for
use by EFI. The range of status codes that have both the highest bit set and the next to highest bit set are reserved for
use by OEMs. Success and warning codes have their highest bit clear, so all success and warning codes have positive
values. The range of status codes that have both the highest bit clear and the next to highest bit clear are reserved for
use by EFI. The range of status code that have the highest bit clear and the next to highest bit set are reserved for use
by OEMs. The Table below lists the status code ranges described above.
Table D.1: EFI_STATUS Code Ranges
Supported 32-
bit RangeSupported 64-bit Architecture
RangesDescription
0x00000000-
0x1fffffff0x00000000000000 00-
0x1fffffffffffffffWarning codes reserved for use by UEFI main speciﬁ-
cation.
0x20000000-
0x3fffffff0x20000000000000 00-
0x3fffffffffffffffWarning codes reserved for use by the Platform Initial-
ization Architecture Speciﬁcation.
0x40000000-
0x7fffffff0x4000000000000000-
0x7fffffffffffffffWarning codes reserved for OEM usage.
0x80000000-
0x9fffffff0x80000000000000 00-
0x9fffffffffffffffError codes reserved for use by UEFI main spec.
0xa0000000-
0xbfffffff0xa0000000000000 00-
0xbfffffffffffffffError codes reserved for use by the Platform Initializa-
tion Architecture Speciﬁcation.
0xc0000000-
0xffffffff0xc000000000000000-
0xcfffffffffffffffError codes reserved for OEM usage.
Table D.2: EFI_STATUS Success Codes (High Bit Clear)
Mnemonic Value Description
EFI_SUCCESS 0 The operation completed successfully.
Table D.3: EFI_STATUS Error Codes (High Bit Set)
EFI_LOAD_ERROR 1 The image failed to load.
EFI_INV ALID_PARAMETER 2 A parameter was incorrect.
EFI_UNSUPPORTED 3 The operation is not supported.
EFI_BAD_BUFFER_SIZE 4 The buffer was not the proper size for the request.
1841Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table D.3 – continued from previous page
EFI_BUFFER_TOO_SMALL 5 The buffer is not large enough to hold the requested
data. The required buffer size is returned in the appro-
priate parameter when this error occurs.
EFI_NOT_READY 6 There is no data pending upon return.
EFI_DEVICE_ERROR 7 The physical device reported an error while attempting
the operation.
EFI_WRITE_PROTECTED 8 The device cannot be written to.
EFI_OUT_OF_RESOURCES 9 A resource has run out.
EFI_VOLUME_CORRUPTED 10 An inconstancy was detected on the ﬁle system causing
the operating to fail.
EFI_VOLUME_FULL 11 There is no more space on the ﬁle system.
EFI_NO_MEDIA 12 The device does not contain any medium to perform the
EFI_MEDIA_CHANGED 13 The medium in the device has changed since the last
access.
EFI_NOT_FOUND 14 The item was not found.
EFI_ACCESS_DENIED 15 Access was denied.
EFI_NO_RESPONSE 16 The server was not found or did not respond to the re-
quest.
EFI_NO_MAPPING 17 A mapping to a device does not exist.
EFI_TIMEOUT 18 The timeout time expired.
EFI_NOT_STARTED 19 The protocol has not been started.
EFI_ALREADY_STARTED 20 The protocol has already been started.
EFI_ABORTED 21 The operation was aborted.
EFI_ICMP_ERROR 22 An ICMP error occurred during the network operation.
EFI_TFTP_ERROR 23 A TFTP error occurred during the network operation.
EFI_PROTOCOL_ERROR 24 A protocol error occurred during the network operation.
EFI_INCOMPATIBLE_VERSION 25 The function encountered an internal version that was
incompatible with a version requested by the caller.
EFI_SECURITY_VIOLATION 26 The function was not performed due to a security viola-
tion.
EFI_CRC_ERROR 27 A CRC error was detected.
EFI_END_OF_MEDIA 28 Beginning or end of media was reached
EFI_END_OF_FILE 31 The end of the ﬁle was reached.
EFI_INV ALID_LANGUAGE 32 The language speciﬁed was invalid.
EFI_COMPROMISED_DATA 33 The security status of the data is unknown or compro-
mised and the data must be updated or replaced to re-
store a valid security status.
EFI_IP_ADDRESS_CONFLICT 34 There is an address conﬂict address allocation
EFI_HTTP_ERROR 35 A HTTP error occurred during the network operation.
Table D.4: EFI_STATUS Warning Codes (High Bit Clear)
EFI_WARN_UNKNOWN_GLYPH 1 The string contained one or more characters that the de-
vice could not render and were skipped.
EFI_WARN_DELETE_FAILURE 2 The handle was closed, but the ﬁle was not deleted.
EFI_WARN_WRITE_FAILURE 3 The handle was closed, but the data to the ﬁle was not
ﬂushed properly.
EFI_WARN_BUFFER_TOO_SMALL 4 The resulting buffer was too small, and the data was
truncated to the buffer size.
1842Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table D.4 – continued from previous page
EFI_WARN_STALE_DATA 5 The data has not been updated within the timeframe set
by local policy for this type of data.
EFI_WARN_FILE_SYSTEM 6 The resulting buffer contains UEFI-compliant ﬁle sys-
tem.
EFI_WARN_RESET_REQUIRED 7 The operation will be processed across a system reset.
1843APPENDIX
E
UNIVERSAL NETWORK DRIVER INTERFACES
E.1 Introduction
This appendix deﬁnes the 32/64-bit H/W and S/W Universal Network Driver Interfaces (UNDIs). These interfaces
provide one method for writing a network driver; other implementations are possible.
E.1.1 Deﬁnitions
E-1 Deﬁnitions
Table E.1: Deﬁnitions
Term Deﬁnition
BC
BaseCode
The PXE BaseCode, included as a core protocol in EFI, is comprised of a simple network
stack (UDP/IP) and a few common network protocols (DHCP, Bootserver Discovery, TFTP)
that are useful for remote booting machines.
LOM
LAN On Motherboard
This is a network device that is built onto the motherboard (or baseboard) of the machine.
NBP
Network Bootstrap Program
This is the ﬁrst program that is downloaded into a machine that has selected a PXE capable
device for remote boot services.
A typical NBP examines the machine it is running on to try to determine if the machine is
capable of running the next layer (OS or application).
If the machine is not capable of running the next layer, control is returned to the EFI boot
manager and the next boot device is selected.
If the machine is capable, the next layer is downloaded and control can then be passed to the
downloaded program.
Though most NBPs are OS loaders, NBPs can be written to be standalone applications such as
diagnostics, backup/restore, remote management agents, browsers, etc.
1844Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table E.1 – continued from previous page
NIC
Network Interface Card
Technically, this is a network device that is inserted into a bus on the motherboard or in an
expansion board. For the purposes of this document, the term NIC will be used in a generic
sense, meaning any device that enables a network connection (including LOMs and network
devices on external busses (USB, 1394, etc.)).
ROM
Read-Only Memory
When used in this speciﬁcation, ROM refers to a nonvolatile memory storage device on a NIC.
PXE
Preboot Execution Environment
The complete PXE speciﬁcation covers three areas; the client, the network and the server.
Client
• Makes network devices into bootable devices.
• Provides APIs for PXE protocol modules in EFI and for universal drivers in the OS.
Network
• Uses existing technology: DHCP, TFTP, etc.
• Adds “vendor speciﬁc” tags to DHCP to deﬁne PXE speciﬁc operation within DHCP.
• Adds multicast TFTP for high bandwidth remote boot applications.
• Deﬁnes Bootserver discovery based on DHCP packet format.
Server
•Bootserver : Responds to Bootserver discovery requests and serves up remote boot images.
•proxyDHCP : Used to ease the transition of PXE clients and servers into existing network
infrastructure. proxyDHCP provides the additional DHCP information that is needed by PXE
clients and Bootservers without making changes to existing DHCP servers.
•MTFTP : Adds multicast support to a TFTP server.
•Plug-In Modules : Example proxyDHCP and Bootservers provided in the PXE SDK

PXE
Client
Network
Server
(software development kit) have the ability to take plug-in modules (PIMs). These PIMs are
used to change/enhance the capabilities of the proxyDHCP and Bootservers.
UNDI
Universal Network Device Interface
UNDI is an architectural interface to NICs. Traditionally NICs have had custom interfaces and
custom drivers (each NIC had a driver for each OS on each platform architecture).
Two variations of UNDI are deﬁned in this speciﬁcation: H/W UNDI and S/W UNDI. H/W
UNDI is an architectural hardware interface to a NIC. S/W UNDI is a software
implementation of the H/W UNDI.
E.1. Introduction 1845Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.1.2 Referenced Speciﬁcations
When implementing PXE services, protocols, ROMs or drivers, it is a good idea to understand the related network
protocols and BIOS speciﬁcations. The Table, below includes all of the speciﬁcations referenced in this document.
Referenced Speciﬁcations
Table E.2: Referenced Speciﬁcations
Acronym Protocol/Speciﬁcation
ARP
Address Resolution Protocol
• Required reading for those implementing the PXE Base Code Protocol.
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Address
Resolution Protocol”.
Assigned Num-
bers Lists the reserved numbers used in the RFCs and in this speciﬁcation.
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Assigned
Numbers”.
BIOS
Basic Input/Output System
• Contact your BIOS manufacturer for reference and programming manuals.
BOOTP
Bootstrap Protocol -
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Bootstrap
Protocol (BOOTP)”.
These references are included for backward compatibility. BC protocol supports DHCP and
BOOTP:
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “BOOTP
Clariﬁcations and Extensions”.
Protocol (BOOTP) Interoperation Between DHCP and BOOTP”.
Required reading for those implementing the PXE Base Code Protocol BC protocol or PXE
Bootservers.
DHCP
Dynamic Host Conﬁguration Protocol
• See “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ ) under the heading “DHCP”.
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Index of
RFC (IETF)”.
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “DHCP
Reconﬁgure Extension”.
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “DHCP for
Ipv4”.
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading
“Interoperations between DHCP and BOOTP”.
Required reading for those implementing the PXE Base Code Protocol or PXE Bootservers.
E.1. Introduction 1846Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table E.2 – continued from previous page
EFI
Extensible Firmware Interface
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Intel
Developer Centers”.
Required reading for those implementing NBPs, OS loaders and preboot applications
for machines with the EFI preboot environment.
ICMP
Internet Control Message Protocol
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “ICMP for
Ipv4”.
Ipv6”. Required reading for those implementing the BC protocol.
IETF
Internet Engineering Task Force
See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Internet
Engineering Task Force (IETF)”.
This is a good starting point for obtaining electronic copies of Internet standards, drafts, and
RFCs.
IGMP
Internet Group Management Protocol
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Internet
Group Management Protocol”.
Required reading for those implementing the PXE Base Code Protocol.
IP
Internet Protocol
Ipv4: ht tp://www.ietf.org/rfc/rfc0791.txt
• “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Ipv4”.
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Ipv6”.
Required reading for those implementing the BC protocol.
MTFTP
Multicast TFTP - Deﬁned in the 16-bit PXE speciﬁcation.
PCI
Peripheral Component Interface
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Peripheral
Component Interface (PCI)”.
Source for PCI speciﬁcations. Required reading for those implementing S/W or H/W UNDI
on a PCI NIC or LOM.
E.1. Introduction 1847Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PnP
Plug-and-Play
• http://www.phoenix.com/en/support/white+papers-specs/
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Plug and
Play”.
Source for PnP speciﬁcations.
PXE
Preboot eXecution Environment
16-bit PXE v2.1:
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Preboot
eXecution Environment (PXE)”.
Required reading.
RFC
Request For Comments
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “Request
for Comments”.
TCP
Transmission Control Protocol
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “TCPv4”.
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “TCPv6”.
Required reading for those implementing the PXE Base Code Protocol .
TFTP
Trivial File Transfer Protocol
TFTP
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “TFTP
Protocol”.
Option Extension”.
Blocksize Option”.
Timeout Interval and Transfer Size Options”.
UDP
User Datagram Protocol
• See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “UDP over
IPv4”.
IPv6”.
E.1. Introduction 1848Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.1.3 OS Network Stacks
This is a simpliﬁed overview of three OS network stacks that contain three types of network drivers: Custom, S/W
UNDI and H/W UNDI. The Figure, below, depicts an application bound to an OS protocol stack, which is in turn
bound to a protocol driver that is bound to three NICs. The Table, below, Driver Types: Pros and Cons gives a brief
list of pros and cons about each type of driver implementation.
Fig. E.1: Network Stacks with Three Classes of Drivers
Driver Types: Pros and Cons
Table E.3: Driver Types: Pros and Cons
Driver Pro Con
Custom
• Can be very fast and efﬁcient. NIC vendor
tunes driver to OS & device.
• OS vendor does not have to write NIC driver.• New driver for each OS/architecture must be
maintained by NIC vendor.
• OS vendor must trust code supplied by
third-party.
• OS vendor cannot test all possible driver/NIC
versions.
• Driver must be installed before NIC can be
used.
• Possible performance sink if driver is poorly
written.
• Possible security risk if driver has back door.
E.1. Introduction 1849Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table E.3 – continued from previous page
S/W UNDI
• S/W UNDI driver is simpler than a Custom
driver. Easier to test outside of the OS
• OS vendor can tune the universal protocol
driver for best OS performance.
• NIC vendor only has to write one driver per
processor architecture.• Slightly slower than Custom or H/W UNDI
because of extra call layer between protocol
stack and NIC.
• S/W UNDI driver must be loaded before NIC
can be used.
• OS vendor has to write the universal driver.
written.
H/W UNDI
• H/W UNDI provides a common architectural
interface to all network devices.
• OS vendor controls all security and
performance issues in network stack.
• NIC vendor does not have to write any
drivers.
• NIC can be used without an OS or driver
installed (preboot management).• OS vendor has to write the universal driver
(this might also be a Pro, depending on your
point of view).
E.2 Overview
There are three major design changes between this speciﬁcation and the 16-bit UNDI in version 2.1 of the PXE
Speciﬁcation:
• A new architectural hardware interface has been added.
• All UNDI commands use the same command format.
• BC is no longer part of the UNDI ROM.
E.2.1 32/64-bit UNDI Interface

written.
H/W UNDI
drivers.
The !PXE structures are used locate and identify the type of 32/64-bit UNDI interface (H/W or S/W), as shown in the
Figure, below. These structures are normally only used by the system BIOS and universal network drivers.
Major Minor reserved
The !PXE structures used for H/W and S/W UNDIs are similar but not identical. The difference in the format is tied
directly to the differences required by the implementation. The !PXE structures for 32/64-bit UNDI are not compatible
with the !PXE structure for 16-bit UNDI.
The !PXE structure for H/W UNDI is built into the NIC hardware. The ﬁrst nine ﬁelds (from offsets 0x00 to 0x0F)
are implemented as read-only memory (or ports). The last three ﬁelds (from Len to Len + 0x0F) are implemented as
read/write memory (or ports). The optional reserved ﬁeld at 0x10 is not deﬁned in this speciﬁcation and may be used
for vendor data.
The !PXE structure for S/W UNDI can be loaded into system memory from one of three places; ROM on a NIC,
system nonvolatile storage, or external storage. Since there are no direct memory or I/O ports available in the S/W
UNDI !PXE structure, an indirect callable entry point is provided. S/W UNDI developers are free to make their
E.2. Overview 1850Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. E.2: !PXE Structures for H/W and S/W UNDI
internal designs as simple or complex as they desire, as long as all of the UNDI commands in this speciﬁcation are
implemented. Descriptions of the ﬁelds in the Table below.
Table E.4: !PXE Structure Field Deﬁnitions
Identiﬁer Value Description
Signature “!PXE” !PXE structure signature. This ﬁeld is used to locate an UNDI hardware or soft-
ware interface in system memory (or I/O) space. ‘!’ is in the ﬁrst (lowest address)
byte, ‘P’ is in the second byte, ‘X’ in the third and ‘E’ in the last. This ﬁeld must
be aligned on a 16-byte boundary (the last address byte must be zero).
Len Varies
Number of !PXE structure bytes to checksum.
When computing the checksum of this structure the Len ﬁeld MUST be used as
the number of bytes to checksum.
The !PXE structure checksum is computed by adding all of the bytes in the
structure, starting with the ﬁrst byte of the structure Signature: ‘!’.
If the 8-bit sum of all of the unsigned bytes in this structure is not zero, this is
not a valid !PXE structure.
Fudge Varies This ﬁeld is used to make the 8-bit checksum of this structure equal zero.
Rev 0x03 Revision of this structure.
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Table E.4 – continued from previous page
IFcnt Varies
This ﬁeld reports the number (minus one) of physical external network
connections that are controlled by this !PXE interface. (If there is one network
connector, this ﬁeld is zero.
If there are two network connectors, this ﬁeld is one.)
For !PXE structure revision 0x03 or higher, in addition to this ﬁeld, the value in
IFcntExt ﬁeld must be left-shifted by 8-bits and ORed with IFcnt to get the
16-bit value for the total number (minus one) of physical external network
connections that are controlled by this !PXE interface.
Major Varies
UNDI command interface. Minor revision number.
0x00 (Alpha) : This version of UNDI does not operate as a runtime driver. The
callback interface deﬁned in the UNDI Start command is required.
0x10 (Beta) :. This version of UNDI can operate as an OS runtime driver. The
callback interface deﬁned in the UNDI Start command is required
Minor Varies
IFcntExt Varies
If the !PXE structure revision 0x02 or earlier, this ﬁeld is reserved and must be
set to zero.
If the !PXE structure revision 0x03 or higher, this ﬁeld reports the upper 8-bits
of the number of physical external network connections that is controlled by this
!PXE interface.
Reserved 0x00 This ﬁeld is reserved and must be set to zero.
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Implementation Varies
Identiﬁes type of UNDI
(S/W or H/W, 32 bit or 64 bit) and what features have been implemented. The
implementation bits are deﬁned below. Undeﬁned bits must be set to zero by
UNDI implementers. Applications/drivers must not rely on the contents of
undeﬁned bits (they may change later revisions).
Bit 0x00: Command completion interrupts supported (1) or not supported (0)
Bit 0x01: Packet received interrupts supported (1) or not supported (0)
Bit 0x02: Transmit complete interrupts supported (1) or not supported (0)
Bit 0x03: Software interrupt supported (1) or not supported (0)
Bit 0x04: Filtered multicast receives supported (1) or not supported (0)
Bit 0x05: Broadcast receives supported (1) or not supported (0)
Bit 0x06: Promiscuous receives supported (1) or not supported (0)
Bit 0x07: Promiscuous multicast receives supported (1) or not supported (0)
Bit 0x08: Station MAC address settable (1) or not settable (0)
Bit 0x09: Statistics supported (1) or not supported (0)
Bit 0x0A,0x0B: NvData not available (0), read only (1), sparse write supported
(2), bulk write supported (3)
Bit 0x0C: Multiple frames per command supported (1) or not supported (0)
Bit 0x0D: Command queuing supported (1) or not supported (0) Bit 0x0E:
Command linking supported (1) or not supported (0)
Bit 0x0F: Packet fragmenting supported (1) or not supported (0)
Bit 0x10: Device can address 64 bits (1) or only 32 bits (0)
Bit 0x1E: S/W UNDI: Entry point is virtual address (1) or unsigned offset from
start of !PXE structure (0).
Bit 0x1F: Interface type: H/W UNDI (1) or S/W UNDI (0)
H/W UNDI
Fields
Reserved Varies
This ﬁeld is optional and may be used for OEM & vendor unique data. If this
ﬁeld is present its length must be a multiple of 16 bytes and must be included in
the !PXE structure checksum.
This ﬁeld, if present, will always start on a 16-byte boundary. Note: The
size/contents of the !PXE structure may change in future revisions of this
Do not rely on OEM & vendor data starting at the same offset from the
beginning of the !PXE structure.
It is recommended that the OEM & vendor data include a signature that
drivers/applications can search for.
E.2. Overview 1853Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Status Varies
UNDI operation, command and interrupt status ﬂags.
This is a read-only port. Undeﬁned status bits must be set to zero. Reading this
port does NOT clear the status.
Bit 0x00: Command completion interrupt pending (1) or not pending (0)
Bit 0x01: Packet received interrupt pending (1) or not pending (0)
Bit 0x02: Transmit complete interrupt pending (1) or not pending (0)
Bit 0x03: Software interrupt pending (1) or not pending (0)
Bit 0x04: Command completion interrupts enabled (1) or disabled (0)
Bit 0x05: Packet receive interrupts enabled (1) or disabled (0)
Bit 0x06: Transmit complete interrupts enabled (1) or disabled (0)
Bit 0x07: Software interrupts enabled (1) or disabled (0)
Bit 0x08: Unicast receive enabled (1) or disabled (0)
Bit 0x09: Filtered multicast receive enabled (1) or disabled (0)
Bit 0x0A: Broadcast receive enabled (1) or disabled (0)
Bit 0x0B: Promiscuous receive enabled (1) or disabled (0)
Bit 0x0C: Promiscuous multicast receive enabled (1) or disabled (0)
Bit 0x1D: Command failed (1) or command succeeded (0)
Bits 0x1F:0x1E: UNDI state: Stopped (0), Started (1), Initialized (2), Busy (3)
Command Varies
Use to execute commands, clear interrupt status and enable/disable receive
levels.
This is a read/write port. Read reﬂects the last write.
Bit 0x00: Clear command completion interrupt (1) or NOP (0)
Bit 0x01: Clear packet received interrupt (1) or NOP (0)
Bit 0x02: Clear transmit complete interrupt (1) or NOP (0)
Bit 0x03: Clear software interrupt (1) or NOP (0)
Bit 0x04: Command completion interrupt enable (1) or disable (0)
Bit 0x05: Packet receive interrupt enable (1) or disable (0)
Bit 0x06: Transmit complete interrupt enable (1) or disable (0)
Bit 0x07: Software interrupt enable (1) or disable (0). Setting this bit to (1) also
generates a software interrupt.
Bit 0x08: Unicast receive enable (1) or disable (0)
Bit 0x09: Filtered multicast receive enable (1) or disable (0)
Bit 0x0A: Broadcast receive enable (1) or disable (0)
Bit 0x0B: Promiscuous receive enable (1) or disable (0)
Bit 0x0C: Promiscuous multicast receive enable (1) or disable (0)
Bit 0x1F: Operation type: Clear interrupt and/or ﬁlter (0), Issue command (1)
CDBaddr Varies
Write the physical address of a CDB to this port. (Done with one 64-bit or two

32-bit writes, depending on processor architecture.)
When done, use one 32-bit write to the command port to send this address into
the command queue.
Unused upper address bits must be set to zero.
E.2. Overview 1854Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
S/W UNDI
Fields
EntryPoint Varies
S/W UNDI API entry point address.
This is either a virtual address or an offset from the start of the !PXE structure.
Protocol drivers will push the 64-bit virtual address of a CDB on the stack and
then call the UNDI API entry point.
When control is returned to the protocol driver, the protocol driver must remove
the address of the CDB from the stack.
Reserved Zero Reserved for future use.
BusTypeCnt Varies This ﬁeld is the count of 4-byte BusType entries in the next ﬁeld.
BusType Varies
This ﬁeld deﬁnes the type of bus S/W UNDI is written to support:
“PCIR,” “PCCR,” “USBR” or “1394.” This ﬁeld is formatted like the Signature
ﬁeld.
If the S/W UNDI supports more than one BusType there will be more than one
BusType identiﬁer in this ﬁeld.
E.2.1.1 Issuing UNDI Commands
How commands are written and status is checked varies a little depending on the type of UNDI (H/W or S/W) imple-
mentation being used. The command ﬂowchart shown in the Figure, below, is a high-level diagram on how commands
are written to both H/W and S/W UNDI.
E.2.2 UNDI Command Format
The format of the CDB is the same for all UNDI commands. The Figure, below, shows the structure of the CDB.
Some of the commands do not use or always require the use of all of the ﬁelds in the CDB. When ﬁelds are not used
they must be initialized to zero or the UNDI will return an error. The StatCode and StatFlags ﬁelds must always be
initialized to zero or the UNDI will return an error. All reserved ﬁelds (and bit ﬁelds) must be initialized to zero or the
UNDI will return an error. Basically, the rule is: Do it right, or don’t do it at all.
Descriptions of the CDB ﬁelds are shown in the table below.
Table E.5: UNDI CDB Field Deﬁnitions
Identiﬁer Description
OpCode
Operation Code (Function Number, Command Code, etc.)
This ﬁeld is used to identify the command being sent to the UNDI. The meanings of some of
the bits in the OpFlags and StatFlags ﬁelds, and the format of the CPB and DB structures
depends on the value in the OpCode ﬁeld. Commands sent with an OpCode value that is not
deﬁned in this speciﬁcation will not be executed and will return a StatCode of
PXE_STATCODE_INV ALID_CDB.
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Table E.5 – continued from previous page
OpFlags
Operation Flags
This bit ﬁeld is used to enable/disable different features in a speciﬁc command operation. It is
also used to change the format/contents of the CPB and DB structures. Commands sent with
reserved bits set in the OpFlags ﬁeld will not be executed and will return a StatCode of
CPBsize
Command Parameter Block Size
This ﬁeld should be set to a number that is equal to the number of bytes that will be read from
CPB structure during command execution. Setting this ﬁeld to a number that is too small will
cause the command to not be executed and a StatCode of PXE_STATCODE_INV ALID_CDB
will be returned. The contents of the CPB structure will not be modiﬁed.
DBsize
Data Block Siz
This ﬁeld should be set to a number that is equal to the number of bytes that will be written into
the DB structure during command execution. Setting this ﬁeld to a number that is smaller than
required will cause an error. It may be zero in some cases where the information is not needed.
CPBaddr
Command Parameter Block Address
For H/W UNDI, this ﬁeld must be the physical address of the CPB structure. For S/W UNDI,
this ﬁeld must be the virtual address of the CPB structure. If the operation does not have/use a
CPB, this ﬁeld must be initialized to PXE_CPBADDR_NOT_USED. Setting up this ﬁeld
incorrectly will cause command execution to fail and a StatCode of
PXE_STATCODE_INV ALID_CDB will be returned.
DBaddr
Data Block Address
For H/W UNDI, this ﬁeld must be the physical address of the DB structure. For S/W UNDI,
this ﬁeld must be the virtual address of the DB structure. If the operation does not have/use a
CPB, this ﬁeld must be initialized to PXE_DBADDR_NOT_USED. Setting up this ﬁeld
StatCode
Status Code
This ﬁeld is used to report the type of command completion: success or failure (and the type of
failure). This ﬁeld must be initialized to zero before the command is issued. The contents of
this ﬁeld is not valid until the PXE_STATFLAGS_COMMAND_COMPLETE status ﬂag is
set. If this ﬁeld is not initialized to PXE_STATCODE_INITIALIZE the UNDI command will
not execute and a StatCode of PXE_STATCODE_INV ALID_CDB will be returned.
E.2. Overview 1856Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
StatFlags
Status Flags
This bit ﬁeld is used to report command completion and identify the format, if any, of the DB
structure. This ﬁeld must be initialized to zero before the command is issued. Until the
command state changes to error or complete, all other CDB ﬁelds must not be changed. If this
ﬁeld is not initialized to PXE_STATFLAGS_INITIALIZE the UNDI command will not
execute and a StatCode of PXE_STATCODE_INV ALID_CDB will be returned. Bits 0x0F &
0x0E: Command state: Not started (0), Queued (1), Error (2), Complete (3).
IFnum
Interface Number
This ﬁeld is used to identify which network adapter (S/W UNDI) or network connector (H/W
UNDI) this command is being sent to. If an invalid interface number is given, the command
will not execute and a StatCode of PXE_STATCODE_INV ALID_CDB will be returned.
Control
Process Control
This bit ﬁeld is used to control command UNDI inter-command processing. Setting control
bits that are not supported by the UNDI will cause the command execution to fail with a
StatCode of PXE_STATCODE_INV ALID_CDB. Bit 0x00: Another CDB follows this one (1)
or this is the last or only CDB in the list (0). Bit 0x01: Queue command if busy (1), fail if busy
(0).
E.3 UNDI C Deﬁnitions
The deﬁnitions in this section are used to aid in the portability and readability of the example 32/64-bit S/W UNDI
source code and the rest of this speciﬁcation.
E.3.1 Portability Macros
These macros are used for storage and communication portability.
E.3.1.1 PXE_INTEL_ORDER or PXE_NETWORK_ORDER
This macro is used to control conditional compilation in the S/W UNDI source code. One of these deﬁnitions needs
to be uncommented in a common PXE header ﬁle.
//#define PXE_INTEL_ORDER 1 // little-endian
//#define PXE_NETWORK_ORDER 1 // big-endian
E.3. UNDI C Deﬁnitions 1857Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. E.3: Issuing UNDI Commands
E.3. UNDI C Deﬁnitions 1858Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. E.4: UNDI Command Descriptor Block (CDB)
E.3.1.2 PXE_UINT64_SUPPORT or PXE_NO_UINT64_SUPPORT
This macro is used to control conditional compilation in the PXE source code. One of these deﬁnitions must to be
uncommented in the common PXE header ﬁle.
//#define PXE_UINT64_SUPPORT 1 // UINT64 supported
//#define PXE_NO_UINT64_SUPPORT 1 // UINT64 not supported
E.3.1.3 PXE_BUSTYPE
Used to convert a 4-character ASCII identiﬁer to a 32-bit unsigned integer.
#if PXE_INTEL_ORDER
#define PXE_BUSTYPE(a,b,c,d) \
((((PXE_UINT32)(d) & 0xFF) << 24) | \
(((PXE_UINT32)(c) & 0xFF) << 16) | \
(((PXE_UINT32)(b) & 0xFF) << 8) | \
((PXE_UINT32)(a) & 0xFF))
#else
((((PXE_UINT32)(a) & 0xFF) << 24) | \
(((PXE_UINT32)(b) & 0xFF) << 16) | \
(((PXE_UINT32)(c) & 0xFF) << 8) | \
((PXE_UINT32)(f) & 0xFF))
#endif
E.3. UNDI C Deﬁnitions 1859Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// UNDI ROM ID anddevice ID signature
#define PXE_BUSTYPE_PXE PXE_BUSTYPE('!', 'P', 'X', 'E')
// BUS ROM ID signatures
#define PXE_BUSTYPE_PCI PXE_BUSTYPE('P', 'C', 'I', 'R')
#define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE('P', 'C', 'C', 'R')
#define PXE_BUSTYPE_USB PXE_BUSTYPE('U', 'S', 'B', 'R')
#define PXE_BUSTYPE_1394 PXE_BUSTYPE('1', '3', '9', '4')
E.3.1.4 PXE_SWAP_UINT16
This macro swaps bytes in a 16-bit word.
#ifdef PXE_INTEL_ORDER
#define PXE_SWAP_UINT16(n) \
((((PXE_UINT16)(n) & 0x00FF) << 8) | \
(((PXE_UINT16)(n) & 0xFF00) >> 8))
#else
#define PXE_SWAP_UINT16(n) (n)
#endif
E.3.1.5 PXE_SWAP_UINT32

#else
#endif
This macro swaps bytes in a 32-bit word.
#define PXE_SWAP_UINT32(n) \
((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
(((PXE_UINT32)(n) & 0x0000FF00) << 8) | \
(((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \
(((PXE_UINT32)(n) & 0xFF000000) >> 24)
#else
#define PXE_SWAP_UINT32(n) (n)
#endif
E.3.1.6 PXE_SWAP_UINT64
This macro swaps bytes in a 64-bit word for compilers that support 64-bit words.
#if PXE_UINT64_SUPPORT != 0
#define PXE_SWAP_UINT64(n) \
((((PXE_UINT64)(n) & 0x00000000000000FF) << 56) | \
(((PXE_UINT64)(n) & 0x000000000000FF00) << 40) | \
(((PXE_UINT64)(n) & 0x0000000000FF0000) << 24) | \
(((PXE_UINT64)(n) & 0x00000000FF000000) << 8) | \
(((PXE_UINT64)(n) & 0x000000FF00000000) >> 8) | \
E.3. UNDI C Deﬁnitions 1860Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
(((PXE_UINT64)(n) & 0x0000FF0000000000) >> 24) | \
(((PXE_UINT64)(n) & 0x00FF000000000000) >> 40) | \
(((PXE_UINT64)(n) & 0xFF00000000000000) >> 56)
#else
#define PXE_SWAP_UINT64(n) (n)
#endif
#endif // PXE_UINT64_SUPPORT
This macro swaps bytes in a 64-bit word, in place, for compilers that do not support 64-bit words. This version of the
64-bit swap macro cannot be used in expressions.
#if PXE_NO_UINT64_SUPPORT != 0
{ \
PXE_UINT32 tmp = (PXE_UINT64)(n)[1]; \
(PXE_UINT64)(n)[1] = PXE_SWAP_UINT32((PXE_UINT64)(n)[0]); \
(PXE_UINT64)(n)[0] = PXE_SWAP_UINT32(tmp); \
}
#else
#endif
#endif // PXE_NO_UINT64_SUPPORT
E.3.2 Miscellaneous Macros
E.3.2.1 Miscellaneous
#define PXE_CPBSIZE_NOT_USED 0 // zero
#define PXE_DBSIZE_NOT_USED 0 // zero
#define PXE_CPBADDR_NOT_USED (PXE_UINT64)0 // zero
#define PXE_DBADDR_NOT_USED (PXE_UINT64)0 // zero
E.3.3 Portability Types
The examples given below are just that, examples. The actual typedef instructions used in a new implementation may
vary depending on the compiler and processor architecture.
The storage sizes deﬁned in this section are critical for PXE module inter-operation. All of the portability typedefs
deﬁne little endian (Intel® format) storage. The least signiﬁcant byte is stored in the lowest memory address and the
most signiﬁcant byte is stored in the highest memory address, as shown in See Storage Types .
E.3. UNDI C Deﬁnitions 1861Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. E.5: Storage Types
E.3.3.1 PXE_CONST
The const type does not allocate storage. This type is a modiﬁer that is used to help the compiler optimize parameters
that do not change across function calls.
#define PXE_CONST const
E.3.3.2 PXE_VOLATILE
The volatile type does not allocate storage. This type is a modiﬁer that is used to help the compiler deal with variables
that can be changed by external procedures or hardware events.
#define PXE_VOLATILE volatile
E.3.3.3 PXE_VOID
The void type does not allocate storage. This type is used only to prototype functions that do not return any information
and/or do not take any parameters.
typedef void PXE_VOID;
E.3.3.4 PXE_UINT8
Unsigned 8-bit integer.
typedef unsigned char PXE_UINT8;
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E.3.3.5 PXE_UINT16
Unsigned 16-bit integer.
typedef unsigned short PXE_UINT16;
E.3.3.6 PXE_UINT32
Unsigned 32-bit integer.
typedef unsigned PXE_UINT32;
E.3.3.7 PXE_UINT64
Unsigned 64-bit integer.
typedef unsigned long PXE_UINT64;
If a 64-bit integer type is not available in the compiler being used, use this deﬁnition:
typedef PXE_UINT32 PXE_UINT64[2];
E.3.3.8 PXE_UINTN
Unsigned integer that is the default word size used by the compiler. This needs to be at least a 32-bit unsigned integer.
typedef unsigned PXE_UINTN;
E.3.4 Simple Types
The PXE simple types are deﬁned using one of the portability types from the previous section.
E.3.4.1 PXE_BOOL
Boolean (true/false) data type. For PXE zero is always false and nonzero is always true.
typedef PXE_UINT8 PXE_BOOL;
#define PXE_FALSE 0 // zero
#define PXE_TRUE (!PXE_FALSE)
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E.3.4.2 PXE_OPCODE
UNDI OpCode (command) descriptions are given in the next chapter. There are no BC OpCodes, BC protocol func-
tions are discussed later in this document.
typedef PXE_UINT16 PXE_OPCODE;
// Return UNDI operational state.
#define PXE_OPCODE_GET_STATE 0x0000
// Change UNDI operational state from Stopped to Started.
#define PXE_OPCODE_START 0x0001
// Change UNDI operational state from Started to Stopped.
#define PXE_OPCODE_STOP 0x0002
// Get UNDI initialization information.
#define PXE_OPCODE_GET_INIT_INFO 0x0003
// Get NIC configuration information.
#define PXE_OPCODE_GET_CONFIG_INFO 0x0004
// Changed UNDI operational state from Started to Initialized.
#define PXE_OPCODE_INITIALIZE 0x0005
// Reinitialize the NIC H/W.
#define PXE_OPCODE_RESET 0x0006
// Change the UNDI operational state from Initialized to Started.
#define PXE_OPCODE_SHUTDOWN 0x0007
// Read & change state of external interrupt enables.
#define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
// Read & change state of packet receive filters.
#define PXE_OPCODE_RECEIVE_FILTERS 0x0009
// Read & change station MAC address.
#define PXE_OPCODE_STATION_ADDRESS 0x000A
// Read traffic statistics.
#define PXE_OPCODE_STATISTICS 0x000B
// Convert multicast IP address to multicast MAC address.
#define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
// Read orchange nonvolatile storage on the NIC.
#define PXE_OPCODE_NVDATA 0x000D
// Get & clear interrupt status.
#define PXE_OPCODE_GET_STATUS 0x000E
// Fill media header inpacketfortransmit.
#define PXE_OPCODE_FILL_HEADER 0x000F
// Transmit packet(s).
#define PXE_OPCODE_TRANSMIT 0x0010
E.3. UNDI C Deﬁnitions 1864Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// Receive packet.
#define PXE_OPCODE_RECEIVE 0x0011
// Last valid PXE UNDI OpCode number.
#define PXE_OPCODE_LAST_VALID 0x0011
E.3.4.3 PXE_OPFLAGS
typedef PXE_UINT16 PXE_OPFLAGS;
#define PXE_OPFLAGS_NOT_USED 0x0000
// UNDI Get State
// No OpFlags
// UNDI Start
// UNDI Stop
// UNDI Get Init Info
// No Opflags
// UNDI Get Config Info
// UNDI Initialize
#define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
#define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
#define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
// UNDI Reset
#define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
E.3. UNDI C Deﬁnitions 1865Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
// UNDI Shutdown
// UNDI Interrupt Enables
// Select whether to enable ordisable external interrupt
// signals. Setting both enable anddisable will return
// PXE_STATCODE_INVALID_OPFLAGS.
#define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
#define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
#define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
#define PXE_OPFLAGS_INTERRUPT_READ 0x0000
// Enable receive interrupts. An external interrupt will be
// generated after a complete non-error packet has been received.
#define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
// Enable transmit interrupts. An external interrupt will be
// generated after a complete non-error packet has been
// transmitted.
#define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
// Enable command interrupts. An external interrupt will be
// generated when command execution stops.
#define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
// Generate software interrupt. Setting this bit generates an
// external interrupt, ifitissupported by the hardware.
#define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008

// UNDI Receive Filters
// Select whether to enable ordisable receive filters.
// Setting both enable anddisable will return
// PXE_STATCODE_INVALID_OPCODE.
#define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
#define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
#define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
#define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
// To reset the contents of the multicast MAC address filter
E.3. UNDI C Deﬁnitions 1866Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// list, set this OpFlag:
#define PXE_OPFLAGS_RECEIVE_FILTERS_RESET_MCAST_LIST 0x2000
// Enable unicast packet receiving. Packets sent to the
// current station MAC address will be received.
#define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
// Enable broadcast packet receiving. Packets sent to the
// broadcast MAC address will be received.
#define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
// Enable filtered multicast packet receiving. Packets sent to
// any of the multicast MAC addresses inthe multicast MAC
// address filter list will be received. If the filter list is
// empty, no multicast
#define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
// Enable promiscuous packet receiving. All packets will be
// received.
#define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
// Enable promiscuous multicast packet receiving. All multicast
// packets will be received.
#define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
// UNDI Station Address
#define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
#define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
#define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
// UNDI Statistics
#define PXE_OPFLAGS_STATISTICS_READ 0x0000
#define PXE_OPFLAGS_STATISTICS_RESET 0x0001
// UNDI MCast IP to MAC
// Identify the type of IP address inthe CPB.
#define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
#define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
#define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
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// UNDI NvData
// Select the type of nonvolatile data operation.
#define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
#define PXE_OPFLAGS_NVDATA_READ 0x0000
#define PXE_OPFLAGS_NVDATA_WRITE 0x0001
// UNDI Get Status
// Return current interrupt status. This will also clear any
// interrupts that are currently set. This can be used ina
// polling routine. The interrupt flags are still set and
// cleared even when the interrupts are disabled.
#define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
// Return list of transmitted buffers forrecycling. Transmit
// buffers must notbe changed orunallocated until they have
// recycled. After issuing a transmit command, wait fora
// transmit complete interrupt. When a transmit complete
// interrupt isreceived, read the transmitted buffers. Do not
// plan on getting one buffer per interrupt. Some NICs andUNDIs
// may transmit multiple buffers per interrupt.
#define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
// Return current media status.
#define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004
// UNDI Fill Header
#define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
#define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
#define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
// UNDI Transmit
// S/W UNDI only. Return after the packet has been transmitted.
// A transmit complete interrupt will still be generated andthe
// transmit buffer will have to be recycled.
#define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
#define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
#define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
#define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
#define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
#define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
E.3. UNDI C Deﬁnitions 1868Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// UNDI Receive
E.3.4.4 PXE_STATFLAGS
typedef PXE_UINT16 PXE_STATFLAGS;
#define PXE_STATFLAGS_INITIALIZE 0x0000
// Common StatFlags that can be returned by all commands.
// The COMMAND_COMPLETE andCOMMAND_FAILED status flags must be
// implemented by all UNDIs. COMMAND_QUEUED isonly needed by
// UNDIs that support command queuing.
#define PXE_STATFLAGS_STATUS_MASK 0xC000
#define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
#define PXE_STATFLAGS_COMMAND_FAILED 0x8000
#define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
#define PXE_STATFLAGS_GET_STATE_MASK 0x0003
#define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
#define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
#define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
// No additional StatFlags
#define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
#define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
#define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK 0x0002
#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED 0x0000
#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED 0x0002
E.3. UNDI C Deﬁnitions 1869Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
#define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
// If set, receive interrupts are enabled.
#define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
// If set, transmit interrupts are enabled.
#define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
// If set, command interrupts are enabled.
#define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
// If set, unicast packets will be received.
#define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
// If set, broadcast packets will be received.
#define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
// If set, multicast packets that match up withthe multicast
// address filter list will be received.
#define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
// If set, all packets will be received.
#define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
// If set, all multicast packets will be received.
#define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
E.3. UNDI C Deﬁnitions 1870Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

// Use to determine ifan interrupt has occurred.
#define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
#define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
// If set, at least one receive interrupt occurred.
#define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
// If set, at least one transmit interrupt occurred.
#define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
// If set, at least one command interrupt occurred.
#define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
// If set, at least one software interrupt occurred.
#define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
// This flag issetifthe transmitted buffer queue isempty.
// This flag will be set ifall transmitted buffer addresses
// get written into the DB.
#define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
// This flag issetifno transmitted buffer addresses were
// written into the DB. (This could be because DBsize was
// too small.)
#define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
// This flag issetifthereisno media detected
#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA 0x0040
E.3. UNDI C Deﬁnitions 1871Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// No additional StatFlags.
E.3.4.5 PXE_STATCODE
typedef PXE_UINT16 PXE_STATCODE;
#define PXE_STATCODE_INITIALIZE 0x0000
// Common StatCodes returned by all UNDI commands, UNDI protocol
// functions andBC protocol functions.
#define PXE_STATCODE_SUCCESS 0x0000
#define PXE_STATCODE_INVALID_CDB 0x0001
#define PXE_STATCODE_INVALID_CPB 0x0002
#define PXE_STATCODE_BUSY 0x0003
#define PXE_STATCODE_QUEUE_FULL 0x0004
#define PXE_STATCODE_ALREADY_STARTED 0x0005
#define PXE_STATCODE_NOT_STARTED 0x0006
#define PXE_STATCODE_NOT_SHUTDOWN 0x0007
#define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
#define PXE_STATCODE_NOT_INITIALIZED 0x0009
#define PXE_STATCODE_DEVICE_FAILURE 0x000A
#define PXE_STATCODE_NVDATA_FAILURE 0x000B
#define PXE_STATCODE_UNSUPPORTED 0x000C
#define PXE_STATCODE_BUFFER_FULL 0x000D
#define PXE_STATCODE_INVALID_PARAMETER 0x000E
#define PXE_STATCODE_INVALID_UNDI 0x000F
#define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
#define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
#define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
#define PXE_STATCODE_NO_DATA 0x0013
E.3.4.6 PXE_IFNUM
typedef PXE_UINT16 PXE_IFNUM;
// This interface number must be passed to the S/W UNDI Start
// command.
#define PXE_IFNUM_START 0x0000
// This interface number isreturned by the S/W UNDI Get State
//andStart commands ifinformation inthe CDB, CPB orDBis
// invalid.
E.3. UNDI C Deﬁnitions 1872Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define PXE_IFNUM_INVALID 0x0000
E.3.4.7 PXE_CONTROL
typedef PXE_UINT16 PXE_CONTROL;
// Setting this flag directs the UNDI to queue this command for
// later execution ifthe UNDI isbusyandit supports command
// queuing. If queuing is notsupported, a
// PXE_STATCODE_INVALID_CONTROL error isreturned. If the queue
//isfull, a PXE_STATCODE_CDB_QUEUE_FULL error isreturned.
#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
// These two bit values are used to determine ifthere are more
// UNDI CDB structures following this one. If the link bit is
// set, there must be a CDB structure following this one.
// Execution will start on the next CDB structure assoonasthis
// one completes successfully. If an error isgenerated by this
// command, execution will stop.
#define PXE_CONTROL_LINK 0x0001
#define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
E.3.4.8 PXE_FRAME_TYPE
typedef PXE_UINT8 PXE_FRAME_TYPE;
#define PXE_FRAME_TYPE_NONE 0x00
#define PXE_FRAME_TYPE_UNICAST 0x01
#define PXE_FRAME_TYPE_BROADCAST 0x02
#define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03
#define PXE_FRAME_TYPE_PROMISCUOUS 0x04
#define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05
E.3.4.9 PXE_IPV4
This storage type is always big endian, not little endian.
E.3. UNDI C Deﬁnitions 1873Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
typedef PXE_UINT32 PXE_IPV4;
E.3.4.10 PXE_IPV6
typedef struct s_PXE_IPV6 {
PXE_UINT32 *num*[4];
} PXE_IPV6;
E.3.4.11 PXE_MAC_ADDR
PXE_UINT8 *num*[32];
} PXE_MAC_ADDR;
E.3.4.12 PXE_IFTYPE
The interface type is returned by the Get Initialization Information command and is used by the BC DHCP protocol
function. This ﬁeld is also used for the low order 8-bits of the H/W type ﬁeld in ARP packets. The high order 8-bits
of the H/W type ﬁeld in ARP packets will always be set to 0x00 by the BC.
typedef PXE_UINT8 PXE_IFTYPE;
// This information is from the ARP section of RFC 3232.
// 1 Ethernet (10Mb)
// 2 Experimental Ethernet (3Mb)
// 3 Amateur Radio AX.25
// 4 Proteon ProNET Token Ring
// 5 Chaos
// 6 IEEE 802 Networks
// 7 ARCNET
// 8 Hyperchannel
// 9 Lanstar
// 10 Autonet Short Address
// 11 LocalTalk
// 12 LocalNet (IBM PCNet orSYTEK LocalNET)
// 13 Ultra link
// 14 SMDS
// 15 Frame Relay
// 16 Asynchronous Transmission Mode (ATM)
// 17 HDLC
// 18 Fibre Channel
// 19 Asynchronous Transmission Mode (ATM)
// 20 Serial Line
// 21 Asynchronous Transmission Mode (ATM)
#define PXE_IFTYPE_ETHERNET 0x01
#define PXE_IFTYPE_TOKENRING 0x04
#define PXE_IFTYPE_FIBRE_CHANNEL 0x12
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E.3.4.13 PXE_MEDIA_PROTOCOL
Protocol type. This will be copied into the media header without doing byte swapping. Protocol type numbers can be
obtained from the assigned numbers RFC 3232.
typedef UINT16 PXE_MEDIA_PROTOCOL;
E.3.5 Compound Types
All PXE structures must be byte packed.
E.3.5.1 PXE_HW_UNDI
This section deﬁnes the C structures and #deﬁnes for the !PXE H/W UNDI interface.
typedef struct s_pxe_hw_undi {
PXE_UINT32 Signature; // PXE_ROMID_SIGNATURE
PXE_UINT8 Len; // sizeof(PXE_HW_UNDI)
PXE_UINT8 Fudge; // makes 8-bit cksum equal zero
PXE_UINT8 Rev; // PXE_ROMID_REV
PXE_UINT8 IFcnt; // physical connector count
lower byte
PXE_UINT8 MajorVer; // PXE_ROMID_MAJORVER
PXE_UINT8 MinorVer; // PXE_ROMID_MINORVER
PXE_UINT8 IFcntExt; // physical connector count
upper byte
PXE_UINT8 reserved; // zero, not used
PXE_UINT32 Implementation; // implementation flags
} PXE_HW_UNDI;
// Status port bit definitions
// UNDI operation state
#define PXE_HWSTAT_STATE_MASK 0xC0000000
#define PXE_HWSTAT_BUSY 0xC0000000
#define PXE_HWSTAT_INITIALIZED 0x80000000
#define PXE_HWSTAT_STARTED 0x40000000
#define PXE_HWSTAT_STOPPED 0x00000000
// If set, last command failed
#define PXE_HWSTAT_COMMAND_FAILED 0x20000000
// If set, identifies enabled receive
filters <http://www.ietf.org/rfc/rfc1700.txt>__ `
#define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
#define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
#define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
#define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
#define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
E.3. UNDI C Deﬁnitions 1875Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// If set, identifies enabled external interrupts
#define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
#define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
#define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
#define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
// If set, identifies pending interrupts
#define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
#define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
#define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
#define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
// Command port definitions
// If set, CDB identified in CDBaddr port is given to UNDI
// If not set, other bits in this word will be processed.
#define PXE_HWCMD_ISSUE_COMMAND 0x80000000
#define PXE_HWCMD_INTS_AND_FILTS 0x00000000
// Use these to enable/disable receive filters.
#define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
#define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
#define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
#define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200

#define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
// Use these to enable/disable external interrupts
#define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
#define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
#define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
#define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
// Use these to clear pending external interrupts
#define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
#define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
#define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
#define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
E.3.5.2 PXE_SW_UNDI
This section deﬁnes the C structures and #deﬁnes for the !PXE S/W UNDI interface.
typedef struct s_pxe_sw_undi {
PXE_UINT32 Signature // PXE_ROMID_SIGNATURE
PXE_UINT8 Len; // sizeof(PXE_SW_UNDI)
PXE_UINT8 Fudge; // makes 8-bit cksum zero
PXE_UINT8 Fcnt; // physical connector count
E.3. UNDI C Deﬁnitions 1876Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
lower byte
PXE_UINT8 MajorVer // PXE_ROMID_MAJORVER
upper byte
PXE_UINT8 reserved1; // zero, notused
PXE_UINT32 Implementation; // Implementation flags
PXE_UINT64 EntryPoint; // API entry point
PXE_UINT8 reserved2[3]; // zero, notused
PXE_UINT8 BusCnt; // number of bustypes supported
PXE_UINT32 BusType[1]; // list of supported bustypes
} PXE_SW_UNDI;
E.3.5.3 PXE_UNDI
PXE_UNDI combines both the H/W and S/W UNDI types into one typedef and has #deﬁnes for common ﬁelds in
both H/W and S/W UNDI types.
typedef union u_pxe_undi {
PXE_HW_UNDI hw;
PXE_SW_UNDI sw;
} PXE_UNDI;
// Signature of !PXE structure
#define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
// !PXE structure format revision *)*
// See "Links to UEFI-Related Documents" (http://uefi.org/uefi)
// under the heading "UDP over IPv6".
#define PXE_ROMID_REV 0x02
// UNDI command interface revision. These are the values that
// get sent in option 94 (Client Network Interface Identifier) in
// the DHCP Discover and PXE Boot Server Request packets.
// under the heading "IETF Organization".
#define PXE_ROMID_MAJORVER 0x03
#define PXE_ROMID_MINORVER 0x01
// Implementation flags
#define PXE_ROMID_IMP_HW_UNDI 0x80000000
#define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
#define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
#define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
#define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
#define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
#define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
#define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
E.3. UNDI C Deﬁnitions 1877Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
#define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
#define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
#define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
#define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
#define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
#define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
#define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
#define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
#define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
#define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
#define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
#define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
#define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
E.3.5.4 PXE_CDB
PXE UNDI command descriptor block.
typedef struct s_pxe_cdb {
PXE_OPCODE OpCode;
PXE_OPFLAGS OpFlags;
PXE_UINT16 CPBsize;
PXE_UINT16 DBsize;
PXE_UINT64 CPBaddr;
PXE_UINT64 DBaddr;
PXE_STATCODE StatCode;
PXE_STATFLAGS StatFlags;
PXE_UINT16 IFnum;
PXE_CONTROL Control;
} PXE_CDB;
If the UNDI driver enables hardware VLAN support, UNDI driver could use IFnum to identify the real NICs and
VLAN created virtual NICs.
E.3.5.5 PXE_IP_ADDR
typedef union u_pxe_ip_addr {
PXE_IPV6 IPv6;
PXE_IPV4 IPv4;
} PXE_IP_ADDR;
E.3. UNDI C Deﬁnitions 1878Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.3.5.6 PXE_DEVICE
This typedef is used to identify the network device that is being used by the UNDI. This information is returned by the
Get Conﬁg Info command.
typedef union pxe_device {
// PCIandPC Card NICs are both identified using bus, device
//andfunction numbers. For PC Card, this may require PC
// Card services to be loaded inthe BIOS orpreboot
// environment.
struct {
// See S/W UNDI ROMID structure definition forPCIand
// PCC BusType definitions.
PXE_UINT32 BusType;
// Bus, device & function numbers that locate this device.
PXE_UINT16 Bus;
PXE_UINT8 Device;
PXE_UINT8 Function;
} PCI, PCC;
} PXE_DEVICE;
E.4 UNDI Commands
All 32/64-bit UNDI commands use the same basic command format, the CDB (Command Descriptor Block). CDB
ﬁelds that are not used by a particular command must be initialized to zero by the application/driver that is issu-
ing the command. (See “Links to UEFI-Related Documents” (http://ueﬁ.org/ueﬁ) under the heading “DMTF BIOS
speciﬁcations”.)
All UNDI implementations must set the command completion status ( PXE_STATFLAGS_COMMAND_COMPLETE
) after command execution completes. Applications and drivers must not alter or rely on the contents of any of the
CDB, CPB or DB ﬁelds until the command completion status is set.
All commands return status codes for invalid CDB contents and, if used, invalid CPB contents. Commands with
invalid parameters will not execute. Fix the error and submit the command again.
See the Figure, below, UNDI States, Transitions & Valid Commands describes the different UNDI states (Stopped,
Started and Initialized), shows the transitions between the states and which UNDI commands are valid in each state.
Note: All memory addresses including the CDB address, CPB address, and the DB address submitted to the S/W
UNDI by the protocol drivers must be processor-based addresses. All memory addresses submitted to the H/W UNDI
must be device based addresses.
Note: Additional requirements for S/W UNDI implementations: Processor register contents must be unchanged by
S/W UNDI command execution (The application/driver does not have to save processor registers when calling S/W
UNDI). Processor arithmetic ﬂags are undeﬁned (application/driver must save processor arithmetic ﬂags if needed).
Application/driver must remove CDB address from stack after control returns from S/W UNDI.
E.4. UNDI Commands 1879Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Fig. E.6: UNDI States, Transitions & Valid Commands
E.4. UNDI Commands 1880Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Note: Additional requirements for 32-bit network devices: All addresses given to the S/W UNDI
must be 32-bit addresses. Any address that exceeds 32 bits (4 GiB) will result in a return of one of
the following status codes: PXE_STATCODE_INV ALID_PARAMETER, PXE_STATCODE_INV ALID_CDB or
PXE_STATCODE_INV ALID_CPB.
When executing linked commands, command execution will stop at the end of the CDB list (when the
PXE_CONTROL_LINK bit is not set) or when a command returns an error status code.
Note: Buffers requested via the MemoryRequired ﬁeld in s_pxe_db_get_init_info (See DB) will be allocated via
PCI_IO.AllocateBuffer(). However, the buffers passed to various UNDI commands are not guaranteed to be allocated
via AllocateBuffer().
Note: Calls to Map_Mem() of type TO_AND_FROM_DEVICE must only be used for common DMA buffers. Such
buffers must be requested via the MemoryRequired ﬁeld in s_pxe_db_get_init_info and provided through the Initialize
command.
E.4.1 Command Linking and Queuing
When linking commands, the CDBs must be stored consecutively in system memory without any gaps in between.
Do not set the Link bit in the last CDB in the list. As shown in the Figure, below, the Link bit must be set in all other
CDBs in the list.
Fig. E.7: Linked CDBs
When the H/W UNDI is executing commands, the State bits in the Status ﬁeld in the !PXE structure will be set to
Busy (3).
E.4. UNDI Commands 1881Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
When H/W or S/W UNDI is executing commands and a new command is issued, a StatCode of
PXE_STATCODE_BUSY and a StatFlag of PXE_STATFLAG_COMMAND_FAILURE is set in the CDB. For linked
commands, only the ﬁrst CDB will be set to Busy, all other CDBs will be unchanged. When a linked command fails,
execution on the list stops. Commands after the failing command will not be run.

command.
Busy (3).
As shown in the Figure, below, when queuing commands, only the ﬁrst CDB needs to have the Queue Control ﬂag
set. If queuing is supported and the UNDI is busy and there is room in the command queue, the command (or list of
commands) will be queued.
Fig. E.8: Queued CDBs
When a command is queued a StatFlag of PXE_STATFLAG_COMMAND_QUEUED is set (if linked commands are
queued only the StatFlag of the ﬁrst CDB gets set). This signals that the command was added to the queue. Commands
in the queue will be run on a ﬁrst-in, ﬁrst-out, basis. When a command fails, the next command in the queue is run.
When a linked command in the queue fails, execution on the list stops. The next command, or list of commands, that
was added to the command queue will be run.
E.4. UNDI Commands 1882Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.2 Get State
This command is used to determine the operational state of the UNDI. An UNDI has three possible operational states:
•Stopped. A stopped UNDI is free for the taking. When all interface numbers (IFnum) for a particular S/W
UNDI are stopped, that S/W UNDI image can be relocated or removed. A stopped UNDI will accept Get State
and Start commands.
•Started. A started UNDI is in use. A started UNDI will accept Get State, Stop, Get Init Info, and Initialize
commands.
•Initialized. An initialized UNDI is in used. An initialized UNDI will accept all commands except: Start, Stop,
and Initialize.
Drivers and applications must not start using UNDIs that have been placed into the Started or Initialized states by
another driver or application.
3.0 and 3.1 S/W UNDI: No callbacks are performed by this UNDI command.
E.4.2.1 Issuing the Command
To issue a Get State command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a Get State command
OpCode PXE_OPCODE_GET_STATE
OpFlags PXE_OPFLAGS_NOT_USED
CPBsize PXE_CPBSIZE_NOT_USED
DBsize PXE_DBSIZE_NOT_USED
CPBaddr PXE_CPBADDR_NOT_USED
DBaddr PXE_DBADDR_NOT_USED
StatCode PXE_STATCODE_INITIALIZE
StatFlags PXE_STATFLAGS_INITIALIZE
IFnum A valid interface number from zero to ( !PXE.IFcnt | (!PXE.IFcntExt << 8 )).
Control Set as needed
E.4.2.2 Waiting for the Command to Execute
Monitor the upper two bits (14 & 15) in the CDB.StatFlags ﬁeld. Until these bits change to report
PXE_STATFLAGS_COMMAND_COMPLETE orPXE_STATFLAGS_COMMAND_FAILED , the command has not
been executed by the UNDI.
StatFlags Reason
COMMAND_COMPLETE Command completed successfully. StatFlags contain operational state.
COMMAND_FAILED Command failed. StatCode ﬁeld contains error code.
COMMAND_QUEUED Command has been queued. All other ﬁelds are unchanged.
INITIALIZE Command has not been executed or queued.
E.4. UNDI Commands 1883Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.2.3 Checking Command Execution Results
After command execution completes, either successfully or not, the CDB.StatCode ﬁeld contains the result of the
command execution.
StatCode Reason
SUCCESS Command completed successfully. StatFlags contain operational state.
INV ALID_CDB One of the CDB ﬁelds was not set correctly.
BUSY UNDI is already processing commands. Try again later.
QUEUE_FULL Command queue is full. Try again later.
If the command completes successfully, use PXE_STATFLAGS_GET_STATE_MASK to check the state of the UNDI.
STOPPED The UNDI is stopped.
STARTED The UNDI is started, but not initialized.
INITIALIZED The UNDI is initialized.
E.4.3 Start
This command is used to change the UNDI operational state from stopped to started. No other operational checks are
made by this command. Protocol driver makes this call for each network interface supported by the UNDI with a set
of call back routines and a unique identiﬁer to identify the particular interface. UNDI does not interpret the unique
identiﬁer in any way except that it is a 64-bit value and it will pass it back to the protocol driver as a parameter to all
the call back routines for any particular interface. If this is a S/W UNDI, the callback functions Delay(), Virt2Phys(),
Map_Mem(), UnMap_Mem(), and Sync_Mem() functions will not be called by this command.
E.4.3.1 Issuing the Command
To issue a Start command for H/W UNDI, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for a H/W UNDI Start command
OpCode PXE_OPCODE_START
To issue a Start command for S/W UNDI, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for a S/W UNDI Start command
CPBsize sizeof(PXE_CPB_START)
E.4. UNDI Commands 1884Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table E.9 – continued from previous page
CPBaddr Address of a PXE_CPB_START structure.
E.4.3.2 Preparing the CPB
For the 3.1 S/W UNDI Start command, the CPB structure shown below must be ﬁlled in and the CDB must be set to
sizeof(struct s_pxe_cpb_start_31) .
typedef struct s_pxe_cpb_start_31 {
UINT64 Delay;
//
// Address of the Delay() callback service.
// This field cannot be set to zero.
//
// VOID
// Delay(
// IN UINT64 UniqueId,
// IN UINT64 Microseconds);
//
// UNDI will never request a delay smaller than 10 microseconds
//andwill always request delays inincrements of 10
// microseconds. The Delay() callback routine must delay
// between n andn + 10 microseconds before returning control
// to the UNDI.
//
//
// Address of the Block() callback service.
//
// VOID
// Block(
// IN UINT32 Enable);
//
// UNDI may need to block multithreaded/multiprocessor access
// to critical code sections when programming oraccessing the
// network device. When UNDI needs a block, it will call the
// Block()callback service withEnable set to a non-zero value.
// When UNDI no longer needs the block, it will call Block()
//withEnable set to zero.
//
UINT64 Virt2Phys;
//
// Convert a virtual address to a physical address.
// This field can be set to zero ifvirtual andphysical
// addresses are identical.
E.4. UNDI Commands 1885Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// VOID
// Virt2Phys(
// IN UINT64 Virtual,
// OUT UINT64 PhysicalPtr);
//
// UNDI will pass in a virtual address anda pointer to storage
//fora physical address. The Virt2Phys() service converts
// the virtual address to a physical address andstores the
// resulting physical address inthe supplied buffer. If no
// conversion isneeded, the virtual address must be copied
// into the supplied physical address buffer.
//
UINT64 Mem_IO;
//
// Read/Write network device memory and/orI/O register space.
//
// VOID
// Mem_IO(
// IN UINT8 AccessType,
// IN UINT8 Length,
// IN UINT64 Port,
// IN OUT UINT64 BufferPtr);
//
// UNDI uses the Mem_IO() service to access the network device
// memory and/orI/O registers. The AccessType isone of the
// PXE_IO_xxx orPXE_MEM_xxx constants defined at the end of
// this section. The Length is1, 2, 4 or8. The Port number
//isrelative to the base memory orI/O address space forthis
// device.BufferPtr points to the data to be written to the
// Port orwill contain the data that isreadfrom the Port.
//
UINT64 Map_Mem;
//
// Map virtual memory address forDMA.
// This field can be set to zero ifthereisno mapping
// service.
//
// VOID
// Map_Mem(
// IN UINT32 Size,
// IN UINT32 Direction,
//
// When UNDI needs to perform a DMA transfer it will request a
// virtual-to-physical mapping using the Map_Mem() service. The
// Virtual parameter contains the virtual address to be mapped.
// The minimum Size of the virtual memory buffer to be mapped.
// Direction isone of the TO_DEVICE, FROM_DEVICE or
// TO_AND_FROM_DEVICE constants defined at the end of this
E.4. UNDI Commands 1886Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// section.PhysicalPtr contains the mapped physical address or
// a copy of the Virtual address ifno mapping isrequired.
//
UINT64 UnMap_Mem;
//
// Un-map previously mapped virtual memory address.
// This field can be set to zero only ifthe Map_Mem() service
//isalso set to zero.
//
// VOID
// UnMap_Mem(

//
// VOID
//
//
//
//
// VOID
// IN UINT64 PhysicalPtr);
//
// When UNDI isdonewiththe mapped memory, it will use the
// UnMap_Mem() service to release the mapped memory.
//
UINT64 Sync_Mem;
//
// Synchronise mapped memory.
//
// VOID
// Sync_Mem(
//
// When the virtual andphysical buffers need to be
// synchronized, UNDI will call the Sync_Mem() service.
//
UINT64 UniqueId;
//
// UNDI will passthis value to each of the callback services.
// A unique ID number should be generated foreach instance of
// the UNDI driver that will be using these callback services.
//
} PXE_CPB_START_31;
For the 3.0 S/W UNDI Start command, the CPB structure shown below must be ﬁlled in and the CDB must be set to
sizeof(struct s_pxe_cpb_start_30) .
typedef struct s_pxe_cpb_start_30 {
//
E.4. UNDI Commands 1887Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// VOID
// Delay(
//
//andwill always request delays inincrements of 10.
// microseconds The Delay() callback routine must delay between
// nandn + 10 microseconds before returning control to the
// UNDI.
//
//
//
// VOID
// Block(
//
//
//
//
// VOID
//
//
//
//
// VOID
// Mem_IO(
E.4. UNDI Commands 1888Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
//
} PXE_CPB_START_30;
#define TO_AND_FROM_DEVICE 0
// Provides both read andwrite access to system memory by both
// the processor anda bus master. The buffer iscoherent from
// both the processor's and the bus master's point of view.
#define FROM_DEVICE 1
// Provides a write operation to system memory by a bus master.
#define TO_DEVICE 2
// Provides a read operation from system memory by a bus master.
E.4.3.3 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. UNDI is now started.
COMMAND_QUEUED Command has been queued.
INITIALIZE Command has been not executed or queued.
E.4.3.4 Checking Command Execution Results
SUCCESS Command completed successfully. UNDI is now started.
ALREADY_STARTED The UNDI is already started.
E.4. UNDI Commands 1889Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.4 Stop
This command is used to change the UNDI operational state from started to stopped.
E.4.4.1 Issuing the Command
To issue a Stop command, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for a Stop command
OpCode PXE_OPCODE_STOP
DBaddr PXE_DBADDR_NOT_USE
StatFlags PXE_STATFLAGS_INITIALIZ
E.4.4.2 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. UNDI is now stopped.
E.4.4.3 Checking Command Execution Results
SUCCESS Command completed successfully. UNDI is now stopped.
NOT_STARTED The UNDI is not started.
NOT_SHUTDOWN The UNDI is initialized and must be shutdown before it can be stopped.
E.4. UNDI Commands 1890Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.5 Get Init Info
This command is used to retrieve initialization information that is needed by drivers and applications to initialized
UNDI.
E.4.5.1 Issuing the Command
To issue a Get Init Info command, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for a Get Init Info command
OpCode PXE_OPCODE_GET_INIT_INFO
DBsize sizeof(PXE_DB_INIT_INFO)
DBaddr Address of a PXE_DB_INIT_INFO structure.
Control Set as needed.
E.4.5.2 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. DB can be used.
E.4.5.3 Checking Command Execution Results
SUCCESS Command completed successfully. DB can be used.
E.4. UNDI Commands 1891Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.5.4 StatFlags
To determine if cable detection is supported by this UNDI/NIC, use these macros with the value returned in the
CDB.StatFlags ﬁeld:
PXE_STATFLAGS_CABLE_DETECT_MASK
PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED
PXE_STATFLAGS_CABLE_DETECT_SUPPORTED
PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK
PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED
PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED
E.4.5.5 DB
typedef struct s_pxe_db_get_init_info {
// Minimum length of locked memory buffer that must be given to
// the Initialize command. Giving UNDI more memory will

E.4.5.5 DB
// generally give better performance.
// If MemoryRequired iszero, the UNDI does notneedandwill
//notuse system memory to receive andtransmit packets.
PXE_UINT32 MemoryRequired;
// Maximum frame data length forTx/Rx excluding the media
// header.
//
PXE_UINT32 FrameDataLen;
// Supported link speeds are inunits of mega bits. Common
// ethernet values are 10, 100 and1000. Unused LinkSpeeds[]
// entries are zero filled.
PXE_UINT32 LinkSpeeds[4];
// Number of nonvolatile storage items.
PXE_UINT32 NvCount;
// Width of nonvolatile storage item inbytes. 0, 1, 2 or4
PXE_UINT16 NvWidth;
// Media header length. This isthe typical media header
// length forthis UNDI. This information isneeded when
// allocating receive andtransmit buffers.
PXE_UINT16 MediaHeaderLen;
// Number of bytes inthe NIC hardware (MAC) address.
PXE_UINT16 HWaddrLen;
// Maximum number of multicast MAC addresses inthe multicast
E.4. UNDI Commands 1892Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// MAC address filter list.
PXE_UINT16 MCastFilterCnt;
// Default number andsize of transmit andreceive buffers that
// will be allocated by the UNDI. If MemoryRequired is
// nonzero, this allocation will come out of the memory buffer
// given to the Initialize command. If MemoryRequired iszero,
// this allocation will come out of memory on the NIC.
PXE_UINT16 TxBufCnt;
PXE_UINT16 TxBufSize;
PXE_UINT16 RxBufCnt;
PXE_UINT16 RxBufSize;
// Hardware interface types defined inthe Assigned Numbers RFC
//andusedinDHCPandARP packets.
// See the PXE_IFTYPE typedef andPXE_IFTYPE_xxx macros.
PXE_UINT8 IFtype;
// Supported duplex options. This can be one ora combination
// of more than one constants defined asPXE_DUPLEX_xxxxx
// below. This value indicates the ability of UNDI to
// change/control the duplex modes of the NIC.
PXE_UINT8 SupportedDuplexModes;
// Supported loopback options. This field can be one ora
// combination of more than one constants defined as
// PXE_LOOPBACK_xxxxx #defines below. This value indicates
// the ability of UNDI to change/control the loopback modes
// of the NIC
PXE_UINT8 SupportedLoopBackModes;
} PXE_DB_GET_INIT_INFO;
#define PXE_MAX_TXRX_UNIT_ETHER 1500
#define PXE_HWADDR_LEN_ETHER 0x0006
#define PXE_DUPLEX_DEFAULT 0
#define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
#define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
#define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
#define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
E.4. UNDI Commands 1893Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.6 Get Conﬁg Info
This command is used to retrieve conﬁguration information about the NIC being controlled by the UNDI.
E.4.6.1 Issuing the Command
To issue a Get Conﬁg Info command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a Get Conﬁg Info command
OpCode PXE_OPCODE_GET_CONFIG_INFO
DBsize sizeof(PXE_DB_CONFIG_INFO)
DBaddr Address of a PXE_DB_CONFIG_INFO structure
IFnum A valid interface number from zero to (!PXE.IFcnt | (!PXE.IFcntExt << 8)).
E.4.6.2 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. DB has been written.
E.4.6.3 Checking Command Execution Results
SUCCESS Command completed successfully. DB has been written.
E.4. UNDI Commands 1894Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.6.4 DB
typedef struct s_pxe_pci_config_info {
// This isthe flag field forthe PXE_DB_GET_CONFIG_INFO union.
// For PCI bus devices, this field isset to PXE_BUSTYPE_PCI.
// This identifies the PCI network device that this UNDI
// interface isbound to.
// This isa copy of the PCI configuration space forthis
// network device.
union {
PXE_UINT8 Byte[256];
PXE_UINT16 Word[128];
PXE_UINT32 Dword[64];
} Config;
} PXE_PCI_CONFIG_INFO;
typedef struct s_pxe_pcc_config_info {
// For PCC bus devices, this field isset to PXE_BUSTYPE_PCC.
// This identifies the PCC network device that this UNDI
// This isa copy of the PCC configuration space forthis
union {
} Config;
} PXE_PCC_CONFIG_INFO;
typedef union u_pxe_db_get_config_info {
PXE_PCI_CONFIG_INFO pci;
PXE_PCC_CONFIG_INFO pcc;
E.4. UNDI Commands 1895Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} PXE_DB_GET_CONFIG_INFO;
E.4.7 Initialize
This command resets the network adapter and initializes UNDI using the parameters supplied in the CPB. The Initialize
command must be issued before the network adapter can be setup to transmit and receive packets. This command will
not enable the receive unit or external interrupts.
Once the memory requirements of the UNDI are obtained by using the Get Init Info command, a block of kernel
(nonswappable) memory may need to be allocated by the protocol driver. The address of this kernel memory must be
passed to UNDI using the Initialize command CPB. This memory is used for transmit and receive buffers and internal
processing.
Initializing the network device will take up to four seconds for most network devices and in some extreme cases
(usually poor cables) up to twenty seconds. Control will not be returned to the caller and the COMMAND_COMPLETE
status ﬂag will not be set until the NIC is ready to transmit.
E.4.7.1 Issuing the Command
To issue an Initialize command, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for an Initialize command
OpCode PXE_OPCODE_INITIALIZE
CPBsize sizeof(PXE_CPB_INITIALIZE)
DBsize sizeof(PXE_DB_INITIALIZE)
CPBaddr Address of a PXE_CPB_INITIALIZE structure.
Dbaddr Address of a PXE_DB_INITIALIZE structure.
Ifnum A valid interface number from zero to ( !PXE.IFcnt | (!PXE.IFcntExt << 8 )).
E.4.7.2 OpFlags
Cable detection can be enabled or disabled by setting one of the following OpFlags:
PXE_OPFLAGS_INITIALIZE_CABLE_DETECT
PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE
E.4. UNDI Commands 1896Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.7.3 Preparing the CPB
If the MemoryRequired ﬁeld returned in the PXE_DB_GET_INIT_INFO structure is zero, the Initialize command does
not need to be given a memory buffer or even a CPB structure. If the MemoryRequired ﬁeld is nonzero, the Initialize
command does need a memory buffer.
typedef struct s_pxe_cpb_initialize {
// Address of first (lowest) byte of the memory buffer.
// This buffer must be incontiguous physical memory andcannot
// be swapped out. The UNDI will be using this fortransmit
//andreceive buffering. This address must be a processor-
// based address forS/W UNDI anda device-based address for
// H/W UNDI.
PXE_UINT64 MemoryAddr;
// MemoryLength must be greater than orequal to MemoryRequired
// returned by the Get Init Info command.
PXE_UINT32 MemoryLength;
// Desired link speed inMbit/sec. Common ethernet values are
// 10, 100 and1000. Setting a value of zero will auto-detect
//and/oruse the default link speed (operation depends on
// UNDI/NIC functionality).
PXE_UINT32 LinkSpeed;
// Suggested number andsize of receive andtransmit buffers to
// allocate. If MemoryAddr andMemoryLength are nonzero, this
// allocation comes out of the supplied memory buffer. If
// MemoryAddr andMemoryLength are zero, this allocation comes
// out of memory on the NIC.
// If these fields are set to zero, the UNDI will allocate
// buffer counts andsizesasit sees fit.
// The following configuration parameters are optional andmust

// be zero to use the default values.
// The possible values forthese parameters are defined below.
PXE_UINT8 DuplexMode;
PXE_UINT8 LoopBackMode;
} PXE_CPB_INITIALIZE;
#define PXE_DUPLEX_AUTO_DETECT 0x00
#define PXE_FORCE_FULL_DUPLEX 0x01
E.4. UNDI Commands 1897Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define PXE_FORCE_HALF_DUPLEX 0x02
#define PXE_LOOPBACK_NORMAL 0
#define PXE_LOOPBACK_INTERNAL 1
#define PXE_LOOPBACK_EXTERNAL 2
E.4.7.4 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. UNDI and network device is now initialized.
DB has been written.
E.4.7.5 Checking Command Execution Results
SUCCESS Command completed successfully. UNDI and network device is now initialized.
DB has been written. Check StatFlags.
INV ALID_CPB One of the CPB ﬁelds was not set correctly.
ALREADY_INITIALIZED The UNDI is already initialized.
DEVICE_FAILURE The network device could not be initialized.
NVDATA_FAILURE The nonvolatile storage could not be read.
E.4.7.6 StatFlags
Check the StatFlags to see if there is an active connection to this network device. If the no media StatFlag is set, the
UNDI and network device are still initialized. PXE_STATFLAGS_INITIALIZED_NO_MEDIA
E.4. UNDI Commands 1898Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.7.7 Before Using the DB
typedef struct s_pxe_db_initialize {
// Actual amount of memory used from the supplied memory
// buffer. This may be less that the amount of memory
// supplied andmay be zero ifthe UNDI andnetwork device
// donotuse external memory buffers. Memory used by the
// UNDI andnetwork device isallocated from the lowest
// memory buffer address.
PXE_UINT32 MemoryUsed;
// Actual number andsize of receive andtransmit buffers that
// were allocated.
PXE_UINT16 RxBufSize
} PXE_DB_INITIALIZE;
E.4.8 Reset
This command resets the network adapter and reinitializes the UNDI with the same parameters provided in the Initial-
ize command. The transmit and receive queues are emptied and any pending interrupts are cleared. Depending on the
state of the OpFlags, the receive ﬁlters and external interrupt enables may also be reset.
Resetting the network device may take up to four seconds and in some extreme cases (usually poor cables) up to
twenty seconds. Control will not be returned to the caller and the COMMAND_COMPLETE status ﬂag will not be set
until the NIC is ready to transmit.
E.4.8.1 Issuing the Command
To issue a Reset command, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for a Reset command
OpCode PXE_OPCODE_RESET
OpFlags Set as needed.
CPBaddr PXE_CPBSIZE_NOT_USED
DBaddr PXE_DBSIZE_NOT_USED
E.4. UNDI Commands 1899Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.8.2 OpFlags
Normally the settings of the receive ﬁlters and external interrupt enables are unchanged by the Reset command. These
two OpFlags will alter the operation of the Reset command.
PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS
PXE_OPFLAGS_RESET_DISABLE_FILTERS
E.4.8.3 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. UNDI and network device have been reset.
Check StatFlags.
E.4.8.4 Checking Command Execution Results
SUCCESS
Command completed successfully.
UNDI and network device have been reset. Check StatFlags.
NOT_INITIALIZED The UNDI is not initialized.
NVDATA_FAILURE The nonvolatile storage is not valid.
E.4. UNDI Commands 1900Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.8.5 StatFlags
UNDI and network device are still reset. PXE_STATFLAGS_RESET_NO_MEDIA
E.4.9 Shutdown
The Shutdown command resets the network adapter and leaves it in a safe state for another driver to initialize. Any
pending transmits or receives are lost. Receive ﬁlters and external interrupt enables are reset (disabled). The memory
buffer assigned in the Initialize command can be released or reassigned.
Once UNDI has been shutdown, it can then be stopped or initialized again. The Shutdown command changes the
UNDI operational state from initializmake htmeled to started.
E.4.9.1 Issuing the Command
To issue a Shutdown command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a Shutdown command
OpCode PXE_OPCODE_SHUTDOWN
E.4.9.2 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. UNDI and network device are shutdown.
E.4. UNDI Commands 1901Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.9.3 Checking Command Execution Results
SUCCESS Command completed successfully. UNDI and network device are shutdown.
E.4.10 Interrupt Enables
The Interrupt Enables command can be used to read and/or change the current external interrupt enable settings.
Disabling an external interrupt enable prevents an external (hardware) interrupt from being signaled by the network
device, internally the interrupt events can still be polled by using the Get Status command.
E.4.10.1 Issuing the Command
To issue an Interrupt Enables command, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for an Interrupt Enables command
OpCode PXE_OPCODE_INTERRUPT_ENABLES
E.4.10.2 OpFlags
To read the current external interrupt enables settings set CDB.OpFlags to:
PXE_OPFLAGS_INTERRUPT_READ
To enable or disable external interrupts set one of these OpFlags:
PXE_OPFLAGS_INTERRUPT_DISABLE
PXE_OPFLAGS_INTERRUPT_ENABLE

When enabling or disabling interrupt settings, the following additional OpFlag bits are used to specify which types of
external interrupts are to be enabled or disabled:
E.4. UNDI Commands 1902Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PXE_OPFLAGS_INTERRUPT_RECEIVE
PXE_OPFLAGS_INTERRUPT_TRANSMIT
PXE_OPFLAGS_INTERRUPT_COMMAND
PXE_OPFLAGS_INTERRUPT_SOFTWARE
Setting PXE_OPFLAGS_INTERRUPT_SOFTWARE does not enable an external interrupt type, it generates an external
interrupt.
E.4.10.3 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. Check StatFlags.
E.4.10.4 Checking Command Execution Results
SUCCESS Command completed successfully. Check StatFlags.
E.4.10.5 StatFlags
If the command was successful, the CDB.StatFlags ﬁeld reports which external interrupt enable types are currently
set. Possible CDB.StatFlags bit settings are:
•PXE_STATFLAGS_INTERRUPT_RECEIVE
•PXE_STATFLAGS_INTERRUPT_TRANSMIT
•PXE_STATFLAGS_INTERRUPT_COMMAND
The bits set in CDB.StatFlags may be different than those that were requested in CDB.OpFlags . For example: If
transmit and receive share an external interrupt line, setting either the transmit or receive interrupt will always enable
both transmit and receive interrupts. In this case both transmit and receive interrupts will be reported in CDB.StatFlags
. Always expect to get more than you ask for!
E.4. UNDI Commands 1903Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.11 Receive Filters
This command is used to read and change receive ﬁlters and, if supported, read and change the multicast MAC address
ﬁlter list. Control will not be returned to the caller and the COMMAND_COMPLETE status ﬂag will not be set until
the NIC is ready to receive.
E.4.11.1 Issuing the Command
To issue a Receive Filters command, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for a Receive Filters command
OpCode PXE_OPCODE_RECEIVE_FILTERS
CPBsize sizeof(PXE_CPB_RECEIVE_FILTERS)
DBsize sizeof(PXE_DB_RECEIVE_FILTERS)
CPBaddr Address of PXE_CPB_RECEIVE_FILTERS structure.
DBaddr Address of PXE_DB_RECEIVE_FILTERS structure.
E.4.11.2 OpFlags
To read the current receive ﬁlter settings set the CDB.OpFlags ﬁeld to:
•PXE_OPFLAGS_RECEIVE_FILTER_READ
To change the current receive ﬁlter settings set one of these OpFlag bits:
•PXE_OPFLAGS_RECEIVE_FILTER_ENABLE
•PXE_OPFLAGS_RECEIVE_FILTER_DISABLE
When changing the receive ﬁlter settings, at least one of the OpFlag bits in this list must be selected:
•PXE_OPFLAGS_RECEIVE_FILTER_UNICAST
•PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST
•PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST
•PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS
•PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST
To clear the contents of the multicast MAC address ﬁlter list, set this OpFlag:
•PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST
E.4. UNDI Commands 1904Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.11.3 Preparing the CPB
The receive ﬁlter CPB is used to change the contents multicast MAC address ﬁlter list. To leave the multicast
MAC address ﬁlter list unchanged, set the CDB.CPBsize ﬁeld to PXE_CPBSIZE_NOT_USED andCDB.CPBaddr
toPXE_CPBADDR_NOT_USED .
To change the multicast MAC address ﬁlter list, set CDB.CPBsize to the size, in bytes, of the multicast MAC address
ﬁlter list and set CDB.CPBaddr to the address of the ﬁrst entry in the multicast MAC address ﬁlter list.
typedef struct s_pxe_cpb_receive_filters {
// List of multicast MAC addresses. This list, ifpresent,
// will replace the existing multicast MAC address filter list.
PXE_MAC_ADDR MCastList[n];
} PXE_CPB_RECEIVE_FILTERS;
E.4.11.4 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. Check StatFlags. DB is written.
E.4.11.5 Checking Command Execution Results
SUCCESS Command completed successfully. Check StatFlags. DB is written.
E.4. UNDI Commands 1905Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.11.6 StatFlags
The receive ﬁlter settings in CDB.StatFlags are:
•PXE_STATFLAGS_RECEIVE_FILTER_UNICAST
•PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST
•PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST
•PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS
•PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST
Unsupported receive ﬁlter settings in OpFlags are promoted to the next more liberal receive ﬁlter setting. For example:
If broadcast or ﬁltered multicast are requested and are not supported by the network device, but promiscuous is; the
promiscuous status ﬂag will be set.
E.4.11.7 DB
The DB is used to read the current multicast MAC address ﬁlter list. The CDB.DBsize and CDB.DBaddr ﬁelds can
be set to PXE_DBSIZE_NOT_USED and PXE_DBADDR_NOT_USED if the multicast MAC address ﬁlter list does
not need to be read. When reading the multicast MAC address ﬁlter list extra entries in the DB will be ﬁlled with zero.
typedef struct s_pxe_db_receive_filters {
// Filtered multicast MAC address list.
} PXE_DB_RECEIVE_FILTERS;
E.4.12 Station Address
This command is used to get current station and broadcast MAC addresses and, if supported, to change the current
station MAC address.
E.4.12.1 Issuing the Command
To issue a Station Address command, create a CDB and ﬁll it in as shows in the table below:
CDB Field How to initialize the CDB structure for a Station Address command
OpCode PXE_OPCODE_STATION_ADDRESS
CPBsize sizeof(PXE_CPB_STATION_ADDRESS)
DBsize sizeof(PXE_DB_STATION_ADDRESS)
CPBaddr Address of PXE_CPB_STATION_ADDRESS structure.
DBaddr Address of PXE_DB_STATION_ADDRESS structure.
E.4. UNDI Commands 1906Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.12.2 OpFlags
To read current station and broadcast MAC addresses set the OpFlags ﬁeld to:
•PXE_OPFLAGS_STATION_ADDRESS_READ
To change the current station to the address given in the CPB set the OpFlags ﬁeld to:
•PXE_OPFLAGS_STATION_ADDRESS_WRITE
To reset the current station address back to the power on default, set the OpFlags ﬁeld to:
•PXE_OPFLAGS_STATION_ADDRESS_RESET
E.4.12.3 Preparing the CPB
To change the current station MAC address the CDB.CPBsize andCDB.CPBaddr ﬁelds must be set.
typedef struct s_pxe_cpb_station_address {
// If supplied andsupported, the current station MAC address
// will be changed.
PXE_MAC_ADDR StationAddr;
} PXE_CPB_STATION_ADDRESS;
E.4.12.4 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. DB is written.
E.4.12.5 Checking Command Execution Results

SUCCESS Command completed successfully.
UNSUPPORTED The requested operation is not supported.
E.4. UNDI Commands 1907Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.12.6 Before Using the DB
The DB is used to read the current station, broadcast and permanent station MAC addresses. The CDB.DBsize and
CDB.DBaddr ﬁelds can be set to PXE_DBSIZE_NOT_USED andPXE_DBADDR_NOT_USED if these addresses do
not need to be read.
typedef struct s_pxe_db_station_address {
// Current station MAC address.
// Station broadcast MAC address.
PXE_MAC_ADDR BroadcastAddr;
// Permanent station MAC address.
PXE_MAC_ADDR PermanentAddr;
} PXE_DB_STATION_ADDRESS;
E.4.13 Statistics
This command is used to read and clear the NIC trafﬁc statistics. Before using this command check to see if statistics
is supported in the !PXE.Implementation ﬂags.
E.4.13.1 Issuing the Command
To issue a Statistics command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a Statistics command
OpCode PXE_OPCODE_STATISTICS
DBsize sizeof(PXE_DB_STATISTICS)
DBaddr Address of PXE_DB_STATISTICS structure.
E.4.13.2 OpFlags
To read the current statistics counters set the OpFlags ﬁeld to:
PXE_OPFLAGS_STATISTICS_READ
To reset the current statistics counters set the OpFlags ﬁeld to:
PXE_OPFLAGS_STATISTICS_RESET
E.4. UNDI Commands 1908Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.13.3 Waiting for the Command to Execute
PXE_STATFLAGS_COMMAND_COMPLETE orPXE_STATFLAGS_COMMAND_FAILED ,the command has not
E.4.13.4 Checking Command Execution Results
SUCCESS Command completed successfully. DB is written.
UNSUPPORTED This command is not supported.
E.4.13.5 DB
Unsupported statistics counters will be zero ﬁlled by UNDI.
typedef struct s_pxe_db_statistics {
// Bit field identifying what statistic data iscollected by
// the UNDI/NIC.
// If bit 0x00 isset, Data[0x00] iscollected.
// If bit 0x01 isset, Data[0x01] iscollected.
// If bit 0x20 isset, Data[0x20] iscollected.
// If bit 0x21 isset, Data[0x21] iscollected.
// Etc.
PXE_UINT64 Supported;
// Statistic data.
PXE_UINT64 Data[64];
} PXE_DB_STATISTICS;
// Total number of frames received. Includes frames witherrors
//anddropped frames.
#define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
// Number of valid frames received andcopied into receive
// buffers.
E.4. UNDI Commands 1909Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
#define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
// Number of frames below the minimum length forthe media.
// This would be <64 forethernet.
#define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
// Number of frames longer than the maximum length forthe
// media. This would be >1500 forethernet.
#define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
// Valid frames that were dropped because receive buffers
// were full.
#define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
// Number of valid unicast frames received and not dropped.
#define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
// Number of valid broadcast frames received and not dropped.
#define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
// Number of valid mutlicast frames received and not dropped.
#define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
// Number of frames w/ CRC oralignment errors.
#define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
// Total number of bytes received. Includes frames witherrors
#define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
// Transmit statistics.
#define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
#define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
#define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
#define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
#define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
#define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
#define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
#define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
#define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
#define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
// Number of collisions detection on this subnet.
#define PXE_STATISTICS_COLLISIONS 0x14
// Number of frames destined forunsupported protocol.
#define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
// Number of valid frames received that were duplicated.
#define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16
// Number of encrypted frames received that failed to decrypt.
#define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17
// Number of frames that failed to transmit after exceeding the
// retry limit.
#define PXE_STATISTICS_TX_ERROR_FRAMES 0x18
E.4. UNDI Commands 1910Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// Number of frames transmitted successfully after more than one
// attempt.
#define PXE_STATISTICS_TX_RETRY_FRAMES 0x19
E.4.14 MCast IP To MAC
Translate a multicast IPv4 or IPv6 address to a multicast MAC address.
E.4.14.1 Issuing the Command
To issue a MCast IP To MAC command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a MCast IP To MAC command
OpCode PXE_OPCODE_MCAST_IP_TO_MAC
CPBsize sizeof(PXE_CPB_MCAST_IP_TO_MAC)
DBsize sizeof(PXE_DB_MCAST_IP_TO_MAC)
CPBaddr Address of PXE_CPB_MCAST_IP_TO_MAC structure.
Dbaddr Address of PXE_DB_MCAST_IP_TO_MAC structure.
E.4.14.2 OpFlags
To convert a multicast IP address to a multicast MAC address the UNDI needs to know the format of the IP address.
Set one of these OpFlags to identify the format of the IP addresses in the CPB:
PXE_OPFLAGS_MCAST_IPV4_TO_MAC
PXE_OPFLAGS_MCAST_IPV6_TO_MAC
E.4.14.3 Preparing the CPB
Fill in an array of one or more multicast IP addresses. Be sure to set the CDB.CPBsize andCDB.CPBaddr ﬁelds
accordingly.
typedef struct s_pxe_cpb_mcast_ip_to_mac {
// Multicast IP address to be converted to multicast
// MAC address.
PXE_IP_ADDR IP[n];
} PXE_CPB_MCAST_IP_TO_MAC;
E.4. UNDI Commands 1911Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.14.4 Waiting for the Command to Execute
E.4.14.5 Checking Command Execution Results
E.4.14.6 Before Using the DB
The DB is where the multicast MAC addresses will be written.
typedef struct s_pxe_db_mcast_ip_to_mac {
// Multicast MAC address.
PXE_MAC_ADDR MAC[n];
} PXE_DB_MCAST_IP_TO_MAC;
E.4. UNDI Commands 1912Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.15 NvData
This command is used to read and write (if supported by NIC H/W) nonvolatile storage on the NIC. Nonvolatile

storage could be EEPROM, FLASH or battery backed RAM.
E.4.15.1 Issuing the Command
To issue a NvData command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a NvData command
OpCode PXE_OPCODE_NVDATA
CPBsize sizeof(PXE_CPB_NVDATA)
DBsize sizeof(PXE_DB_NVDATA)
CPBaddr Address of PXE_CPB_NVDATA structure.
Dbaddr Address of PXE_DB_NVDATA structure.
E.4.15.2 Preparing the CPB
There are two types of nonvolatile data CPBs, one for sparse updates and one for bulk updates. Sparse updates allow
updating of single nonvolatile storage items. Bulk updates always update all nonvolatile storage items. Check the
!PXE.Implementation ﬂags to see which type of nonvolatile update is supported by this UNDI and network device.
If you do not need to update the nonvolatile storage set the CDB.CPBsize and CDB.CPBaddr ﬁelds to
PXE_CPBSIZE_NOT_USED andPXE_CPBADDR_NOT_USED .
E.4.15.2.1 Sparse NvData CPB
typedef struct s_pxe_cpb_nvdata_sparse {
// NvData item list. Only items inthis list will be updated.
struct {
// Nonvolatile storage address to be changed.
PXE_UINT32 Addr;
// Data item to write into above storage address.
union {
PXE_UINT8 Byte;
PXE_UINT16 Word;
PXE_UINT32 Dword;
} Data;
} Item[n];
} PXE_CPB_NVDATA_SPARSE;
E.4. UNDI Commands 1913Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.15.2.2 Bulk NvData CPB
// When using bulk update, the size of the CPB structure must be
// the same size asthe nonvolatile NIC storage.
typedef union u_pxe_cpb_nvdata_bulk {
// Array of byte-wide data items.
PXE_UINT8 Byte[n];
// Array of word-wide data items.
PXE_UINT16 Word[n];
// Array of dword-wide data items.
PXE_UINT32 Dword[n];
} PXE_CPB_NVDATA_BULK;
E.4.15.3 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. Nonvolatile data is updated from CPB and/or
written to DB.
E.4.15.4 Checking Command Execution Results
SUCCESS Command completed successfully. Nonvolatile data is updated from CPB and/or
UNSUPPORTED Requested operation is unsupported.
E.4. UNDI Commands 1914Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.15.4.1 DB
Check the width and number of nonvolatile storage items. This information is returned by the Get Init Info command.
typedef struct s_pxe_db_nvdata {
// Arrays of data items from nonvolatile storage.
union {
} Data;
} PXE_DB_NVDATA;
E.4.16 Get Status
This command returns the current interrupt status and/or the transmitted buffer addresses and the current media status.
If the current interrupt status is returned, pending interrupts will be acknowledged by this command. Transmitted
buffer addresses that are written to the DB are removed from the transmitted buffer queue.
This command may be used in a polled fashion with external interrupts disabled.
E.4.16.1 Issuing the Command
To issue a Get Status command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a Get Status command
OpCode PXE_OPCODE_GET_STATUS
DBsize Sizeof(PXE_DB_GET_STATUS)
DBaddr Address of PXE_DB_GET_STATUS structure.
E.4. UNDI Commands 1915Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.16.1.1 Setting OpFlags
Set one or a combination of the OpFlags below to return the interrupt status and/or the transmitted buffer addresses
and/or the media status.
PXE_OPFLAGS_GET_INTERRUPT_STATUS
PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS
PXE_OPFLAGS_GET_MEDIA_STATUS
E.4.16.2 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. StatFlags and/or DB are updated.
E.4.16.3 Checking Command Execution Results
SUCCESS Command completed successfully. StatFlags and/or DB are updated.
E.4.16.4 StatFlags
If the command completes successfully and the PXE_OPFLAGS_GET_INTERRUPT_STATUS OpFlag was set in the
CDB, the current interrupt status is returned in the CDB.StatFlags ﬁeld and any pending interrupts will have been
cleared.
PXE_STATFLAGS_GET_STATUS_RECEIVE
PXE_STATFLAGS_GET_STATUS_TRANSMIT
PXE_STATFLAGS_GET_STATUS_COMMAND
PXE_STATFLAGS_GET_STATUS_SOFTWARE
The StatFlags above may not map directly to external interrupt signals. For example: Some NICs may combine both
the receive and transmit interrupts to one external interrupt line. When a receive and/or transmit interrupt occurs, use
the Get Status to determine which type(s) of interrupt(s) occurred.
This ﬂag is set if the transmitted buffer queue is empty. This ﬂag will be set if all transmitted buffer addresses get
written t into the DB.
E.4. UNDI Commands 1916Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY
This ﬂag is set if no transmitted buffer addresses were written into the DB.
PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN
This ﬂag is set if there is no media present.
PXE_STATFLAGS_GET_STATUS_NO_MEDIA
E.4.16.5 Using the DB
When reading the transmitted buffer addresses there should be room for at least one 64-bit address in the DB. Once a
complete transmitted buffer address is written into the DB, the address is removed from the transmitted buffer queue.
If the transmitted buffer queue is full, attempts to use the Transmit command will fail.
typedef struct s_pxe_db_get_status {
// Length of next receive frame (header + data). If this is
// zero, there isno next receive frame available.
PXE_UINT32 RxFrameLen;
// Reserved, set to zero.
PXE_UINT32 reserved;
// Addresses of transmitted buffers that need to be recycled.
PXE_UINT64 xBuffer[n];
} PXE_DB_GET_STATUS;
E.4.17 Fill Header
This command is used to ﬁll the media header(s) in transmit packet(s).
E.4.17.1 Issuing the Command
To issue a Fill Header command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a Fill Header command
OpCode PXE_OPCODE_FILL_HEADER
CPBsize PXE_CPB_FILL_HEADER
CPBaddr Address of a PXE_CPB_FILL_HEADER structure.
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Table E.44 – continued from previous page
E.4.17.2 OpFlags
Select one of the OpFlags below so the UNDI knows what type of CPB is being used.
PXE_OPFLAGS_FILL_HEADER_WHOLE
PXE_OPFLAGS_FILL_HEADER_FRAGMENTED
E.4.17.3 Preparing the CPB
If multiple frames per command are supported (see !PXE.Implementation ﬂags), multiple CPBs can be packed to-
gether. The CDB.CPBsize ﬁeld lets the UNDI know how many CPBs are packed together.

E.4.17.4 Nonfragmented Frame
typedef struct s_pxe_cpb_fill_header {
// Source anddestination MAC addresses. These will be copied
// into the media header without doing byte swapping.
PXE_MAC_ADDR SrcAddr;
PXE_MAC_ADDR DestAddr;
// Address of first byte of media header. The first byte of
// packet data follows the last byte of the media header.
PXE_UINT64 MediaHeader;
// Length of packet data inbytes (notincluding the media
// header).
PXE_UINT32 PacketLen;
// Protocol type. This will be copied into the media header
// without doing byte swapping. Protocol type numbers can be
// obtained from the Assigned Numbers RFC 3232.
PXE_UINT16 Protocol;
// Length of the media header inbytes.
} PXE_CPB_FILL_HEADER;
#define PXE_PROTOCOL_ETHERNET_IP 0x0800
#define PXE_PROTOCOL_ETHERNET_ARP 0x0806
E.4. UNDI Commands 1918Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.17.5 Fragmented Frame
typedef struct s_pxe_cpb_fill_header_fragmented {
PXE_MEDIA_PROTOCOL Protocol;
// Number of packet fragment descriptors.
PXE_UINT16 FragCnt;
// Reserved, must be set to zero.
PXE_UINT16 reserved;
// Array of packet fragment descriptors. The first byte of the
// media header isthe first byte of the first fragment.
struct {
// Address of this packet fragment.
PXE_UINT64 FragAddr;
// Length of this packet fragment.
PXE_UINT32 FragLen;
} FragDesc[n];
} PXE_CPB_FILL_HEADER_FRAGMENTED;
E.4.17.6 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. Frame is ready to transmit.
E.4. UNDI Commands 1919Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table E.45 – continued from previous page
E.4.17.7 Checking Command Execution Results
SUCCESS Command completed successfully. Frame is ready to transmit.
E.4.18 Transmit
The Transmit command is used to place a packet into the transmit queue. The data buffers given to this command are
to be considered locked and the application or universal network driver loses the ownership of those buffers and must
not free or relocate them until the ownership returns.
When the packets are transmitted, a transmit complete interrupt is generated (if interrupts are disabled, the transmit
interrupt status is still set and can be checked using the Get Status command).
Some UNDI implementations and network adapters support transmitting multiple packets with one transmit command.
If this feature is supported, multiple transmit CPBs can be linked in one transmit command.
Though all UNDIs support fragmented frames, the same cannot be said for all network devices or protocols. If
a fragmented frame CPB is given to UNDI and the network device does not support fragmented frames (see
!PXE.Implementation ﬂags), the UNDI will have to copy the fragments into a local buffer before transmitting.
E.4.18.1 Issuing the Command
To issue a Transmit command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a Transmit command
OpCode PXE_OPCODE_TRANSMIT
CPBsize sizeof(PXE_CPB_TRANSMIT)
CPBaddr Address of a PXE_CPB_TRANSMIT structure.
E.4. UNDI Commands 1920Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.18.2 OpFlags
Check the !PXE.Implementation ﬂags to see if the network device support fragmented packets. Select one of the
OpFlags below so the UNDI knows what type of CPB is being used.
PXE_OPFLAGS_TRANSMIT_WHOLE
PXE_OPFLAGS_TRANSMIT_FRAGMENTED
In addition to selecting whether or not fragmented packets are being given, S/W UNDI needs to know if it should
block until the packets are transmitted. H/W UNDI cannot block, these two OpFlag settings have no affect when used
with H/W UNDI.
PXE_OPFLAGS_TRANSMIT_BLOCK
PXE_OPFLAGS_TRANSMIT_DONT_BLOCK
E.4.18.3 Preparing the CPB
gether. The CDB.CPBsize ﬁeld lets the UNDI know how may frames are to be transmitted.
E.4.18.4 Nonfragmented Frame
typedef struct s_pxe_cpb_transmit {
// Address of first byte of frame buffer. This isalso the
// first byte of the media header. This address must be a
// processor-based address forS/W UNDI anda device-based
// address forH/W UNDI.
PXE_UINT64 FrameAddr;
// Length of the data portion of the frame buffer inbytes. Do
//notinclude the length of the media header.
PXE_UINT32 DataLen;
PXE_UINT16 MediaheaderLen;
// Reserved, must be zero.
} PXE_CPB_TRANSMIT;
E.4.18.5 Fragmented Frame
typedef struct s_pxe_cpb_transmit_fragments {
PXE_UINT32 FrameLen;
E.4. UNDI Commands 1921Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// Array of frame fragment descriptors. The first byte of the
// first fragment isalso the first byte of the media header.
struct {
// Address of this frame fragment. This address must be a
// Length of this frame fragment.
} PXE_CPB_TRANSMIT_FRAGMENTS;
E.4.18.6 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. Use the Get Status command to see when
frame buffers can be reused.
E.4.18.7 Checking Command Execution Results
SUCCESS Command completed successfully. Use the Get Status command to see when
QUEUE_FULL Command queue is full. Wait for queued commands to complete. Try again later.
BUFFER_FULL Transmit buffer is full. Call Get Status command to empty buffer.
E.4. UNDI Commands 1922Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table E.49 – continued from previous page
E.4.19 Receive
When the network adapter has received a frame, this command is used to copy the frame into driver/application storage.
Once a frame has been copied, it is removed from the receive queue.
E.4.19.1 Issuing the Command
To issue a Receive command, create a CDB and ﬁll it in as shown in the table below:
CDB Field How to initialize the CDB structure for a Receive command
OpCode PXE_OPCODE_RECEIVE

CPBsize sizeof(PXE_CPB_RECEIVE)
DBsize sizeof(PXE_DB_RECEIVE)
CPBaddr Address of a PXE_CPB_RECEIVE structure.
DBaddr Address of a PXE_DB_RECEIVE structure.
E.4.19.2 Preparing the CPB
gether. For each complete received frame, a receive buffer large enough to contain the entire unfragmented frame
needs to be described in the CPB. Note that if a smaller than required buffer is provided, only a portion of the packet is
received into the buffer, and the remainder of the packet is lost. Subsequent attempts to receive the same packet with
a corrected (larger) buffer will be unsuccessful, because the packet will have been ﬂushed from the queue.
typedef struct s_pxe_cpb_receive {
// Address of first byte of receive buffer. This isalso the
// first byte of the frame header. This address must be a
PXE_UINT64 BufferAddr;
// Length of receive buffer. This must be large enough to hold
// the received frame (media header + data). If the length of
// smaller than the received frame, data will be lost.
PXE_UINT32 BufferLen;
} PXE_CPB_RECEIVE;
E.4. UNDI Commands 1923Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
E.4.19.3 Waiting for the Command to Execute
COMMAND_COMPLETE Command completed successfully. Frames received and DB is written.
E.4.19.4 Checking Command Execution Results
SUCCESS Command completed successfully. Frames received and DB is written.
NO_DATA Receive buffers are empty.
E.4.19.5 Using the DB
If multiple frames per command are supported (see !PXE.Implementation ﬂags), multiple DBs can be packed together.
typedef struct s_pxe_db_receive {
// Source anddestination MAC addresses from media header.
// Length of received frame. May be larger than receive buffer
// size. The receive buffer will notbe overwritten. This is
// how to tell ifdata was lost because the receive buffer was
// too small.
// Protocol type from media header.
PXE_PROTOCOL Protocol;
// Length of media header inreceived frame.
// Type of receive frame.
PXE_FRAME_TYPE Type;
E.4. UNDI Commands 1924Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PXE_UINT8 reserved[7];
} PXE_DB_RECEIVE;
E.4.20 PXE 2.1 speciﬁcation wire protocol clariﬁcations
The Preboot Execution Environment (PXE) Version 2.1 speciﬁcation was published in September 1999. Since then,
this speciﬁcation has not been maintained or updated for a new version. For adapting the IPv6 stack, the deﬁnition
of an IPv6-based PXE process has been described in UEFI speciﬁcation since version 2.2. Other clariﬁcations for the
IPv4-based PXE process deﬁned in the PXE 2.1 speciﬁcation are provided in this section.
E.4.20.1 Issue #1-time-outs
Where the PXE 2.1 speciﬁcation reads:
DHCP Discover will be retried four times. The four timeouts are 4, 8, 16 and 32 seconds respectively.
If a DHCPOFFER is received without an Option #60 tag “PXEClient”, DHCP Discover will be retried on the 4-and
8-second timeouts in an attempt to receive a PXE response.
Because of spanning tree algorithms in routers, the behavior should be as follows:
This process could be iterated three times.
E.4.20.2 Issue #2 - siaddr/option 54 precedence
Boot server IP address (Read from the DHCP option 54 (server identiﬁer), if not found, use the siaddr ﬁeld.)
The behavior should be reversed, namely:
Ascertain the Boot server IP address from siaddr ﬁeld. If not found, use the value in the DHCP option 54 (server
identiﬁer).
E.4.20.3 Issue #3 - PXE Vendor Options Existence
The PXE 2.1 speciﬁcation is ambiguous about whether the following PXE Vendor Options need to be provided in
DHCP messages. These options are marked as “Required” in Table 2-1 “PXE DHCP Options (Full List)”, but other
parts of the speciﬁcation state that these options may not be supplied in certain condition.
This section clariﬁes the existence of these PXE Vendor Options:
1.PXE_DISCOVERY_CONTROL (Tag 6)
- Required, Note #3
- If this tag is not supplied all bits assumed to be 0.
E.4. UNDI Commands 1925Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The behavior should be clariﬁed as:
- This tag is not mandatory required. If not supplied, all bits are assumed to be 0.
2.PXE_BOOT_SERVERS (Tag 8)
- Required for PXE client. Note #3
- PXE_DISCOVERY_CONTROL (Tag 6), bit 2 = If set, only use/accept servers in
PXE_BOOT_SERVERS.
- This tag is required only if bit 2 of PXE_DISCOVERY_CONTROL (Tag 6) is set.
3.PXE_BOOT_MENU (Tag 9
- Required, Note #4
- Note #4: These options deﬁne the information, if any, displayed by the client during a network boot.
- This tag is required only if the PXE client wants to display boot menu information during a network
boot.
4.PXE_CREDENTIAL_TYPES (Tag 12)
- Required for security. Note #5
- This option is required for security requests and acknowledges between the client and the server.
- This tag is not required if PXE client does not apply security requests.
5.PXE_BOOT_ITEM (Tag 71)
- Required. Note #6
- If this tag is missing, type 0 and layer 0 is assumed.**
- This tag is not mandatory required. If not supplied, type 0 and layer 0 is assumed.
6.Vendor Options (Tag 43)
The PXE 2.1 speciﬁcation is not clear whether this option is required.
E.4. UNDI Commands 1926Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
- Vendor Options (Tag 43) is required only if encapsulated PXE options need be supplied.
E.4. UNDI Commands 1927APPENDIX
F
USING THE SIMPLE POINTER PROTOCOL
The Simple Pointer Protocol is intended to provide a simple mechanism for an application to interact with the user
with some type of pointer device. To keep this interface simple, many of the custom controls that are typically present
in an OS-present environment were left out. This includes the ability to adjust the double-click speed and the ability to
adjust the pointer speed. Instead, the recommendations for how the Simple Pointer Protocol should be used are listed
here.
X-Axis Movement:
If the Simple Pointer Protocol is being used to move a pointer or cursor around on an output display, the movement
along the x-axis should move the pointer or cursor horizontally.
Y-Axis Movement:
along the y-axis should move the pointer or cursor vertically.
Z-Axis Movement:
If the Simple Pointer Protocol is being used to move a pointer or cursor around on an output display, and the application
that is using the Simple Pointer Protocol supports scrolling, then the movement along the z-axis should scroll the output
display.
Double Click Speed:
If two clicks of the same button on a pointer occur in less than 0.5 seconds, then a double-click event has occurred.

here.
display.
If a the same button is pressed with more than 0.5 seconds between clicks, then this is interpreted as two single-click
events.
Pointer Speed:
The Simple Pointer Protocol returns the movement of the pointer device along an axis in counts. The Simple Pointer
Protocol also contains a set of resolution ﬁelds that deﬁne the number of counts that will be received for each millimeter
of movement of the pointer device along an axis. From these two values, the consumer of this protocol can determine
the distance the pointer device has been moved in millimeters along an axis. For most applications, movement of a
pointer device will result in the movement of a pointer on the screen. For each millimeter of motion by the pointer
device in the x-axis, the pointer on the screen will be moved 2 percent of the screen width. For each millimeter of
motion by the pointer device in the y-axis, the pointer on the screen will be moved 2 percent of the screen height.
1928APPENDIX
G
USING THE EFI EXTENDED SCSI PASS THRU PROTOCOL
This appendix describes how an EFI utility might gain access to the EFI SCSI Pass Thru interfaces. The basic con-
cept is to use the EFI_BOOT_SERVICES.LocateHandle() boot service to retrieve the list of handles that support the
EFI_EXT_SCSI_PASS_THRU_PROTOCOL . Each of these handles represents a different SCSI channel present in the
system. Each of these handles can then be used the retrieve the EFI_EXT_SCSI_PASS_THRU_PROTOCOL interface
with the EFI_BOOT_SERVICES.HandleProtocol() boot service. The EFI_EXT_SCSI_PASS_THRU_PROTOCOL in-
terface provides the services required to access any of the SCSI devices attached to a SCSI channel. The services of
theEFI_EXT_SCSI_PASS_THRU_PROTOCOL are then to loop through the Target IDs of all the SCSI devices on the
SCSI channel.
#include "efi.h"
#include "efilib.h"
#include EFI_PROTOCOL_DEFINITION(ExtScsiPassThru)
EFI_GUID gEfiExtScsiPassThruProtocolGuid =
EFI_EXT_SCSI_PASS_THRU_PROTOCOL_GUID;
UtilityEntryPoint(
EFI_HANDLE ImageHandle,
EFI_SYSTEM_TABLE SystemTable
)
{
EFI_EXT_SCSI_PASS_THRU_PROTOCOL *ExtScsiPassThruProtocol;
//
// Initialize EFI Library
//
InitializeLib (ImageHandle, SystemTable);
//
// Get list of handles that support the
// EFI_EXT_SCSI_PASS_THRU_PROTOCOL
//
NoHandles = 0;
HandleBuffer = NULL;
Status = LibLocateHandle(
&gEfiExtScsiPassThruProtocolGuid,
1929Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
NULL,
);
BS->Exit(ImageHandle,EFI_SUCCESS,0,NULL);
}
//
// Loop through all the handles that support
// EFI_EXT_SCSI_PASS_THRU
//
//
// Get the EFI_EXT_SCSI_PASS_THRU_PROTOCOL Interface
// on each handle
//
BS->HandleProtocol(
(VOID**)&ExtScsiPassThruProtocol
);
if (!EFI_ERROR(Status)) {
//
// Use the EFI_EXT_SCSI_PASS_THRU Interface to
// perform tests
//
Status = DoScsiTests(ScsiPassThruProtocol);
}
}
}
DoScsiTests(
EFI_EXT_SCSI_PASS_THRU_PROTOCOL *ExtScsiPassThruProtocol
)
{
UINT32 Target;
UINT64 Lun;
EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET Packet;
//
// Get first Target ID and LUN on the SCSI channel
//
Target = 0xffffffff;
Lun = 0;
Status = ExtScsiPassThruProtocol-> GetNextTargetLun(
ExtScsiPassThruProtocol,
&Target,
&Lun
1930Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
//
// Loop through all the SCSI devices on the SCSI channel
//
while (!EFI_ERROR (Status)) {
//
// Blocking I/O example.
// Fill in Packet before calling PassThru()
//
Status = ExtScsiPassThruProtocol->PassThru(
Target,
Lun,
&Packet,
NULL
);
//
// Non Blocking I/O
// Fill in Packet and create Event before calling PassThru()
//
Target,
Lun,
&Packet,
&Event
);
//
// Get next Target ID and LUN on the SCSI channel
//
&Target,
&Lun
);
}
}
1931APPENDIX
H
COMPRESSION SOURCE CODE
/*++
Copyright (c) 2001-2002 Intel Corporation
Module Name:
Compress.c
Abstract:
Compression routine. The compression algorithm isa mixture of LZ77
andHuffman Coding. LZ77 transforms the source data into a sequence
of Original Characters andPointers to repeated strings. This sequence
isfurther divided into Blocks andHuffman codings are applied to each Block.
Revision History:
--*/
#include <string.h>
#include <stdlib.h>
#include "eficommon.h"
//
// Macro Definitions
//
typedef INT16 NODE;
#define UINT8_MAX 0xff
#define UINT8_BIT 8
#define THRESHOLD 3
#define INIT_CRC 0
#define WNDBIT 13
#define WNDSIZ (1U << WNDBIT)
#define MAXMATCH 256
#define PERC_FLAG 0x8000U
#define CODE_BIT 16
#define NIL 0
#define MAX_HASH_VAL (3 *WNDSIZ + (WNDSIZ / 512 + 1) *UINT8_MAX)
#define HASH(p, c) ((p) + ((c) << (WNDBIT - 9)) + WNDSIZ *2)
#define CRCPOLY 0xA001
#define UPDATE_CRC(c) mCrc = mCrcTable[(mCrc ^ (c)) & 0xFF] ^ (mCrc
>> UINT8_BIT)
//
1932Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// C: the Char&Len Set; P: the Position Set; T: the exTra Set
//
#define NC (UINT8_MAX + MAXMATCH + 2 - THRESHOLD)
#define CBIT 9
#define NP (WNDBIT + 1)
#define PBIT 4
#define NT (CODE_BIT + 3)
#define TBIT 5
#if NT > NP
#define NPT NT
#else
#define NPT NP
#endif
//
// Function Prototypes
//
STATIC
VOID
PutDword(
IN UINT32 Data
);
STATIC
AllocateMemory (
);
STATIC
VOID
FreeMemory (
);
STATIC
VOID
InitSlide (
);
STATIC
NODE
Child (
IN NODE q,
IN UINT8 c
);
STATIC
VOID
MakeChild (
IN NODE q,
IN UINT8 c,
IN NODE r
);
STATIC
VOID
1933Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Split (
IN NODE Old
);
STATIC
VOID
InsertNode (
);
STATIC
VOID
DeleteNode (
);
STATIC
VOID
GetNextMatch (
);
STATIC
Encode (
);
STATIC
VOID
CountTFreq (
);
STATIC
VOID
WritePTLen (
IN INT32 n,
IN INT32 nbit,
IN INT32 Special
);
STATIC
VOID
WriteCLen (
);
STATIC
VOID
EncodeC (
IN INT32 c
);
STATIC
VOID
EncodeP (
IN UINT32 p
);
STATIC
VOID
SendBlock (
1934Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
);
STATIC
VOID
Output (
IN UINT32 c,
IN UINT32 p
);
STATIC
VOID
HufEncodeStart (
);
STATIC
VOID
HufEncodeEnd (
);
STATIC
VOID
MakeCrcTable (
);
STATIC
VOID
PutBits (
IN INT32 n,
IN UINT32 x
);
STATIC
INT32
FreadCrc (
OUT UINT8 *p,
IN INT32 n
);
STATIC
VOID
InitPutBits (
);
STATIC
VOID
CountLen (
IN INT32 i
);
STATIC
VOID
MakeLen (
IN INT32 Root
);
STATIC
VOID
1935Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DownHeap (
IN INT32 i
);
STATIC
VOID
MakeCode (
IN INT32 n,
IN UINT8 Len[],
OUT UINT16 Code[]
);
STATIC
INT32
MakeTree (
IN INT32 NParm,
IN UINT16 FreqParm[],
OUT UINT8 LenParm[],
OUT UINT16 CodeParm[]
);
//
// Global Variables
//
STATIC UINT8 *mSrc,*mDst,*mSrcUpperLimit, *mDstUpperLimit;
STATIC UINT8 *mLevel, *mText,*mChildCount, *mBuf, mCLen[NC], mPTLen[NPT], *mLen;
STATIC INT16 mHeap[NC + 1];
STATIC INT32 mRemainder, mMatchLen, mBitCount, mHeapSize, mN;
STATIC UINT32 mBufSiz = 0, mOutputPos, mOutputMask, mSubBitBuf, mCrc;
STATIC UINT32 mCompSize, mOrigSize;
STATIC UINT16 *mFreq,*mSortPtr, mLenCnt[17], mLeft[2 *NC - 1], mRight[2 *NC - 1],
mCrcTable[UINT8_MAX + 1], mCFreq[2 *NC - 1], mCTable[4096], mCCode[NC],
mPFreq[2 *NP - 1], mPTCode[NPT], mTFreq[2 *NT - 1];
STATIC NODE mPos, mMatchPos, mAvail, *mPosition, *mParent, *mPrev,*mNext = NULL;
//
// functions
//
Compress (
IN UINT8 *SrcBuffer,
IN UINT32 SrcSize,
IN UINT8 *DstBuffer,
IN OUT UINT32 *DstSize
)
/*++
Routine Description:
The main compression routine.
1936Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Arguments:
SrcBuffer - The buffer storing the source data
SrcSize - The size of the source data
DstBuffer - The buffer to store the compressed data
DstSize - On input, the size of DstBuffer; On output,
the size of the actual compressed data.
Returns:
EFI_BUFFER_TOO_SMALL - The DstBuffer istoo small. In this case,
DstSize contains the size needed.
EFI_SUCCESS - Compression issuccessful.
--*/
{
EFI_STATUS Status = EFI_SUCCESS;
//
// Initializations
//
mBufSiz = 0;
mBuf = NULL;
mText = NULL;
mLevel = NULL;
mChildCount = NULL;
mPosition = NULL;
mParent = NULL;
mPrev = NULL;
mNext = NULL;
mSrc = SrcBuffer;
mSrcUpperLimit = mSrc + SrcSize;
mDst = DstBuffer;
mDstUpperLimit = mDst + *DstSize;
PutDword(0L);
MakeCrcTable ();
mOrigSize = mCompSize = 0;
mCrc = INIT_CRC;
//
// Compress it
//
Status = Encode();

Returns:
--*/
{
//
//
//
//
}
//
// Null terminate the compressed data
1937Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
if(mDst < mDstUpperLimit) {
*mDst++ = 0;
}
//
// Fill incompressed size andoriginal size
//
PutDword(mCompSize+1);
PutDword(mOrigSize);
//
// Return
//
if(mCompSize + 1 + 8 > *DstSize) { \
*DstSize = mCompSize + 1 + 8;
returnEFI_BUFFER_TOO_SMALL;
}else{
}
}
STATIC
VOID
PutDword(
)
/*++
Put a dword to output stream
Data - the dword to put
Returns: (VOID)
--*/
{
*mDst++ = (UINT8)(((UINT8)(Data )) & 0xff);
}
*mDst++ = (UINT8)(((UINT8)(Data >> 0x08)) & 0xff);
}
*mDst++ = (UINT8)(((UINT8)(Data >> 0x10)) & 0xff);
}
1938Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
*mDst++ = (UINT8)(((UINT8)(Data >> 0x18)) & 0xff);
}
}
STATIC
AllocateMemory ()
/*++
Allocate memory spaces fordata structures used incompression process
Arguments: (VOID)
Returns:
EFI_SUCCESS - Memory isallocated successfully
EFI_OUT_OF_RESOURCES - Allocation fails
--*/
{
UINT32 i;
mText = malloc (WNDSIZ *2 + MAXMATCH);
for(i = 0; i < WNDSIZ *2 + MAXMATCH; i ++) {
mText[i] = 0;
}
mLevel = malloc ((WNDSIZ + UINT8_MAX + 1) *sizeof(*mLevel));
mChildCount = malloc ((WNDSIZ + UINT8_MAX + 1) *
sizeof(*mChildCount));
mPosition = malloc ((WNDSIZ + UINT8_MAX + 1) *sizeof(*mPosition));
mParent = malloc (WNDSIZ *2*sizeof(*mParent));
mPrev = malloc (WNDSIZ *2*sizeof(*mPrev));
mNext = malloc ((MAX_HASH_VAL + 1) *sizeof(*mNext));
mBufSiz = 16 *1024U;
while((mBuf = malloc(mBufSiz)) == NULL) {
mBufSiz = (mBufSiz / 10U) *9U;
if(mBufSiz < 4 *1024U) {
}
}
mBuf[0] = 0;
}
VOID
FreeMemory ()
/*++
Called when compression iscompleted to free memory previously allocated.
1939Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
--*/
{
if(mText) {
free (mText);
}
if(mLevel) {
free (mLevel);
}
if(mChildCount) {
free (mChildCount);
}
if(mPosition) {
free (mPosition);
}
if(mParent) {
free (mParent);
}
if(mPrev) {
free (mPrev);
}
if(mNext) {
free (mNext);
}
if(mBuf) {
free (mBuf);
}
return;
}
STATIC
VOID
InitSlide ()
/*++
Initialize String Info Log data structures
--*/
{
NODE i;
1940Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
for(i = WNDSIZ; i <= WNDSIZ + UINT8_MAX; i++) {
mLevel[i] = 1;
mPosition[i] = NIL; / *sentinel */
}
for(i = WNDSIZ; i < WNDSIZ *2; i++) {
mParent[i] = NIL;
}
mAvail = 1;
for(i = 1; i < WNDSIZ - 1; i++) {
mNext[i] = (NODE)(i + 1);
}
mNext[WNDSIZ - 1] = NIL;
for(i = WNDSIZ *2; i <= MAX_HASH_VAL; i++) {
mNext[i] = NIL;
}
}
STATIC
NODE
Child (
IN NODE q,
IN UINT8 c
)
/*++
Find child node given the parent node andthe edge character
q - the parent node
c - the edge character
Returns:
The child node (NIL if notfound)
--*/
{
NODE r;
r = mNext[HASH(q, c)];
mParent[NIL] = q; / *sentinel */
while(mParent[r] != q) {
r = mNext[r];
}
returnr;
}
STATIC
VOID
IN NODE q,
1941Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
IN UINT8 c,
IN NODE r
)
/*++
Create a new child fora given parent node.
r - the child node
--*/
{
NODE h, t;
h = (NODE)HASH(q, c);
t = mNext[h];
mNext[h] = r;
mNext[r] = t;
mPrev[t] = r;
mPrev[r] = h;
mParent[r] = q;
mChildCount[q]++;
}
STATIC
VOID
Split (
NODE Old
)
/*++
Split a node.
Old - the node to split
--*/
{
NODE New, t;
New = mAvail;
mAvail = mNext[New];
mChildCount[New] = 0;
t = mPrev[Old];
mPrev[New] = t;
1942Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
mNext[t] = New;
t = mNext[Old];
mNext[New] = t;
mPrev[t] = New;
mParent[New] = mParent[Old];
mLevel[New] = (UINT8)mMatchLen;
mPosition[New] = mPos;
MakeChild(New, mText[mMatchPos + mMatchLen], Old);
MakeChild(New, mText[mPos + mMatchLen], mPos);
}
STATIC
VOID
InsertNode ()
/*++
Insert string info forcurrent position into the String Info Log
--*/
{
NODE q, r, j, t;
UINT8 c, *t1,*t2;
if(mMatchLen >= 4) {
//
// We have just got a long match, the target tree
// can be located by MatchPos + 1. Traverse the tree
//from bottom up to get to a proper starting point.
// The usage of PERC_FLAG ensures proper node deletion
//inDeleteNode() later.
//
mMatchLen--;
r = (INT16)((mMatchPos + 1) \| WNDSIZ);
while((q = mParent[r]) == NIL) {
}
while(mLevel[q] >= mMatchLen) {
r = q; q = mParent[q];
}
t = q;
while(mPosition[t] < 0) {
mPosition[t] = mPos;
t = mParent[t];
}
if(t < WNDSIZ) {
mPosition[t] = (NODE)(mPos \| PERC_FLAG);
}
}else{
1943Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
//
// Locate the target tree
//
q = (INT16)(mText[mPos] + WNDSIZ);
c = mText[mPos + 1];
if((r = Child(q, c)) == NIL) {
MakeChild(q, c, mPos);
mMatchLen = 1;
return;
}
mMatchLen = 2;
}
//
// Traverse down the tree to find a match.
// Update Position value along the route.
// Node split orcreation isinvolved.
//
for( ; ; ) {
if(r >= WNDSIZ) {
j = MAXMATCH;
mMatchPos = r;
}else{
j = mLevel[r];
mMatchPos = (NODE)(mPosition[r] & ~PERC_FLAG);
}
if(mMatchPos >= mPos) {
mMatchPos -= WNDSIZ;
}
t1 = &mText[mPos + mMatchLen];
t2 = &mText[mMatchPos + mMatchLen];
while(mMatchLen < j) {
if(*t1 !=*t2) {
Split(r);
return;
}
mMatchLen++;
t1++;
t2++;
}
if(mMatchLen >= MAXMATCH) {
break;
}
mPosition[r] = mPos;
q = r;
if((r = Child(q, *t1)) == NIL) {
MakeChild(q, *t1, mPos);
return;
}
}
t = mPrev[r];
mPrev[mPos] = t;
mNext[t] = mPos;
t = mNext[r];
1944Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
mNext[mPos] = t;
mPrev[t] = mPos;
mParent[mPos] = q;
mParent[r] = NIL;
//
// Special usage of 'next'
//
mNext[r] = mPos;
}
STATIC
VOID
DeleteNode ()
/*++
Delete outdated string info. (The Usage of PERC_FLAG
ensures a clean deletion)
--*/
{
NODE q, r, s, t, u;
if (mParent[mPos] == NIL) {
return;
}
r = mPrev[mPos];
s = mNext[mPos];
mNext[r] = s;
mPrev[s] = r;
r = mParent[mPos];
mParent[mPos] = NIL;
if (r >= WNDSIZ || --mChildCount[r] > 1) {
return;
}
t = (NODE)(mPosition[r] & ~PERC_FLAG);
if (t >= mPos) {
t -= WNDSIZ;
}
s = t;
q = mParent[r];
while ((u = mPosition[q]) & PERC_FLAG) {
u &= ~PERC_FLAG;
if (u >= mPos) {
u -= WNDSIZ;
}
if (u > s) {
s = u;
1945Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
}
mPosition[q] = (INT16)(s \| WNDSIZ);
q = mParent[q];
}
if (q < WNDSIZ) {
}
if (u > s) {
s = u;
}
mPosition[q] = (INT16)(s \| WNDSIZ \| PERC_FLAG);
}
s = Child(r, mText[t + mLevel[r]]);
t = mPrev[s];
u = mNext[s];
mNext[t] = u;
mPrev[u] = t;
mNext[t] = s;
mPrev[s] = t;
mPrev[t] = s;
mNext[s] = t;
mParent[s] = mParent[r];
mNext[r] = mAvail;
mAvail = r;
}
STATIC
VOID
GetNextMatch ()
/*++
Advance the current position (read in new data if needed).
Delete outdated string info. Find a match string for current position.
--*/
{
INT32 n;
mRemainder--;
if (++mPos == WNDSIZ *2) {
memmove(&mText[0], &mText[WNDSIZ], WNDSIZ + MAXMATCH);
n = FreadCrc(&mText[WNDSIZ + MAXMATCH], WNDSIZ);
mRemainder += n;
mPos = WNDSIZ;
}
DeleteNode();
InsertNode();
1946Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
}
STATIC
Encode ()
/*++
The main controlling routine for compression process.
Returns:
EFI_SUCCESS - The compression is successful
EFI_OUT_0F_RESOURCES - Not enough memory for compression process
--*/
{
INT32 LastMatchLen;
NODE LastMatchPos;
Status = AllocateMemory();
FreeMemory();
}
InitSlide();
HufEncodeStart();
mRemainder = FreadCrc(&mText[WNDSIZ], WNDSIZ + MAXMATCH);
mMatchLen = 0;
if (mMatchLen > mRemainder) {
mMatchLen = mRemainder;
}
while (mRemainder > 0) {
LastMatchLen = mMatchLen;

--*/
{
INT32 n;
}
}
STATIC
Encode ()
/*++
Returns:
--*/
{
}
}
LastMatchPos = mMatchPos;
GetNextMatch();
}
if (mMatchLen > LastMatchLen \|\| LastMatchLen < THRESHOLD) {
//
// Not enough benefits are gained by outputting a pointer,
// so just output the original character
//
1947Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Output(mText[mPos - 1], 0);
} else {
//
// Outputting a pointer is beneficial enough, do it.
//
Output(LastMatchLen + (UINT8_MAX + 1 - THRESHOLD),
(mPos - LastMatchPos - 2) & (WNDSIZ - 1));
while (--LastMatchLen > 0) {
}
}
}
}
HufEncodeEnd();
}
STATIC
VOID
CountTFreq ()
/*++
Count the frequencies for the Extra Set
--*/
{
INT32 i, k, n, Count;
for (i = 0; i < NT; i++) {
mTFreq[i] = 0;
}
n = NC;
while (n > 0 && mCLen[n - 1] == 0) {
n--;
}
i = 0;
while (i < n) {
k = mCLen[i++];
if (k == 0) {
Count = 1;
while (i < n && mCLen[i] == 0) {
i++;
Count++;
}
if (Count <= 2) {
1948Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
mTFreq[0] = (UINT16)(mTFreq[0] + Count);
} else if (Count <= 18) {
mTFreq[1]++;
} else if (Count == 19) {
mTFreq[0]++;
} else {
mTFreq[2]++;
}
} else {
mTFreq[k + 2]++;
}
}
}
STATIC
VOID
IN INT32 n,
)
/*++
Outputs the code length array for the Extra Set or the Position Set.
n - the number of symbols
nbit - the number of bits needed to represent 'n'
Special - the special symbol that needs to be take care of
--*/
{
INT32 i, k;
while (n > 0 && mPTLen[n - 1] == 0) {
n--;
}
PutBits(nbit, n);
i = 0;
k = mPTLen[i++];
if (k <= 6) {
PutBits(3, k);
} else {
PutBits(k - 3, (1U << (k - 3)) - 2);
}
if (i == Special) {
while (i < 6 && mPTLen[i] == 0) {
i++;
}
PutBits(2, (i - 3) & 3);
1949Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
}
}
}
STATIC
VOID
WriteCLen ()
/*++
Outputs the code length array for Char&Length Set
--*/
{
n = NC;
n--;
}
PutBits(CBIT, n);
i = 0;
if (k == 0) {
Count = 1;
i++;
Count++;
}
for (k = 0; k < Count; k++) {
PutBits(mPTLen[0], mPTCode[0]);
}
PutBits(mPTLen[1], mPTCode[1]);
PutBits(4, Count - 3);
PutBits(4, 15);
} else {
PutBits(mPTLen[2], mPTCode[2]);
PutBits(CBIT, Count - 20);
}
} else {
PutBits(mPTLen[k + 2], mPTCode[k + 2]);
}
}
}
STATIC
1950Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
VOID
EncodeC (
IN INT32 c
)
{
PutBits(mCLen[c], mCCode[c]);
}
STATIC
VOID
EncodeP (
IN UINT32 p
)
{
UINT32 c, q;
c = 0;
q = p;
while (q) {
q >>= 1;
c++;
}
PutBits(mPTLen[c], mPTCode[c]);
if (c > 1) {
PutBits(c - 1, p & (0xFFFFU >> (17 - c)));
}
}
STATIC
VOID
SendBlock ()
/*++
Huffman code the block and output it.
Argument: (VOID)
--*/
{
UINT32 i, k, Flags, Root, Pos, Size;
Flags = 0;
Root = MakeTree(NC, mCFreq, mCLen, mCCode);
Size = mCFreq[Root];
PutBits(16, Size);
if (Root >= NC) {
CountTFreq();
Root = MakeTree(NT, mTFreq, mPTLen, mPTCode);
if (Root >= NT) {
WritePTLen(NT, TBIT, 3);
} else {
PutBits(TBIT, 0);
1951Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
PutBits(TBIT, Root);
}
WriteCLen();
} else {
PutBits(CBIT, 0);
PutBits(CBIT, Root);
}
Root = MakeTree(NP, mPFreq, mPTLen, mPTCode);
if (Root >= NP) {
WritePTLen(NP, PBIT, -1);
} else {
PutBits(PBIT, 0);
PutBits(PBIT, Root);
}
Pos = 0;
for (i = 0; i < Size; i++) {
if (i % UINT8_BIT == 0) {
Flags = mBuf[Pos++];
} else {
Flags <<= 1;
}
if (Flags & (1U << (UINT8_BIT - 1))) {
EncodeC(mBuf[Pos++] + (1U << UINT8_BIT));
k = mBuf[Pos++] << UINT8_BIT;
k += mBuf[Pos++];
EncodeP(k);
} else {
EncodeC(mBuf[Pos++]);
}
}
for (i = 0; i < NC; i++) {
mCFreq[i] = 0;
}
for (i = 0; i < NP; i++) {
mPFreq[i] = 0;
}
}
STATIC
VOID
Output (
IN UINT32 p
)
/*++
Outputs an Original Character or a Pointer
c - The original character or the 'String Length' element of a Pointer
p - The 'Position' field of a Pointer
1952Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
--*/
{
STATIC UINT32 CPos;
if ((mOutputMask >>= 1) == 0) {
mOutputMask = 1U << (UINT8_BIT - 1);
if (mOutputPos >= mBufSiz - 3 *UINT8_BIT) {
SendBlock();
mOutputPos = 0;
}
CPos = mOutputPos++;
mBuf[CPos] = 0;
}
mBuf[mOutputPos++] = (UINT8) c;
mCFreq[c]++;
if (c >= (1U << UINT8_BIT)) {
mBuf[CPos] \|= mOutputMask;
mBuf[mOutputPos++] = (UINT8)(p >> UINT8_BIT);
mBuf[mOutputPos++] = (UINT8) p;
c = 0;
while (p) {
p >>= 1;
c++;
}
mPFreq[c]++;
}
}
STATIC
VOID
HufEncodeStart ()
{
INT32 i;
}
}
mOutputPos = mOutputMask = 0;
InitPutBits();
return;
}
STATIC
VOID
HufEncodeEnd ()
{
//
// Flush remaining bits
//
PutBits(UINT8_BIT - 1, 0);
1953Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
return;
}
STATIC
VOID
MakeCrcTable ()
{
UINT32 i, j, r;
for (i = 0; i <= UINT8_MAX; i++) {
r = i;
for (j = 0; j < UINT8_BIT; j++) {
if (r & 1) {
r = (r >> 1) ^ CRCPOLY;
} else {
r >>= 1;
}
}
mCrcTable[i] = (UINT16)r;
}
}
STATIC
VOID
PutBits (
IN INT32 n,
IN UINT32 x
)
/*++
Outputs rightmost n bits of x
n - the rightmost n bits of the data is used
x - the data
--*/
{
UINT8 Temp;
if (n < mBitCount) {
mSubBitBuf \|= x << (mBitCount -= n);
} else {
Temp = (UINT8)(mSubBitBuf \| (x >> (n -= mBitCount)));
if (mDst < mDstUpperLimit) {
*mDst++ = Temp;
}
mCompSize++;
if (n < UINT8_BIT) {
1954Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
mSubBitBuf = x << (mBitCount = UINT8_BIT - n);
} else {
Temp = (UINT8)(x >> (n - UINT8_BIT));
}
mSubBitBuf = x << (mBitCount = 2 *UINT8_BIT - n);
}
}
}
STATIC
INT32
FreadCrc (
IN INT32 n
)
/*++
Read in source data
p - the buffer to hold the data
n - number of bytes to read
Returns:
number of bytes actually read
--*/
{
INT32 i;
for (i = 0; mSrc < mSrcUpperLimit && i < n; i++) {
*p++ =*mSrc++;
}
n = i;
p -= n;
mOrigSize += n;
while (--i >= 0) {
UPDATE_CRC( *p++);
}
return n;
}
STATIC
VOID
InitPutBits ()
{
mBitCount = UINT8_BIT;
1955Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
mSubBitBuf = 0;
}
STATIC
VOID
CountLen (
IN INT32 i
)
/*++
Count the number of each code length for a Huffman tree.
i - the top node
--*/
{
STATIC INT32 Depth = 0;
if (i < mN) {
mLenCnt[(Depth < 16) ? Depth : 16]++;
} else {
Depth++;
CountLen(mLeft [i]);
CountLen(mRight[i]);
Depth--;
}
}
STATIC
VOID
MakeLen (
)
/*++
Create code length array for a Huffman tree
Root - the root of the tree
--*/
{
INT32 i, k;
UINT32 Cum;
for (i = 0; i <= 16; i++) {
mLenCnt[i] = 0;
}
1956Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
CountLen(Root);
//
// Adjust the length count array so that
// no code will be generated longer than the designated length
//
Cum = 0;
for (i = 16; i > 0; i--) {
Cum += mLenCnt[i] << (16 - i);
}
while (Cum != (1U << 16)) {
mLenCnt[16]--;
for (i = 15; i > 0; i--) {
if (mLenCnt[i] != 0) {
mLenCnt[i]--;
mLenCnt[i+1] += 2;
break;
}
}
Cum--;
}
k = mLenCnt[i];
while (--k >= 0) {
mLen[*mSortPtr++] = (UINT8)i;
}
}
}
STATIC
VOID
DownHeap (
IN INT32 i
)
{
INT32 j, k;
//
// priority queue: send i-th entry down heap
//
k = mHeap[i];
while ((j = 2 *i) <= mHeapSize) {
if (j < mHeapSize && mFreq[mHeap[j]] > mFreq[mHeap[j + 1]]) {
j++;
}
if (mFreq[k] <= mFreq[mHeap[j]]) {
break;
}
mHeap[i] = mHeap[j];
i = j;
}
mHeap[i] = (INT16)k;
}
STATIC
VOID
1957Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
MakeCode (
IN INT32 n,
)
/*++
Assign code to each symbol based on the code length array

//
Cum = 0;
}
break;
}
}
Cum--;
}
}
}
}
STATIC
VOID
DownHeap (
IN INT32 i
)
{
INT32 j, k;
//
//
j++;
}
break;
}
i = j;
}
}
STATIC
VOID
MakeCode (
IN INT32 n,
)
/*++
n - number of symbols
Len - the code length array
Code - stores codes for each symbol
--*/
{
INT32 i;
for (i = 1; i <= 16; i++) {
Start[i + 1] = (UINT16)((Start[i] + mLenCnt[i]) << 1);
}
for (i = 0; i < n; i++) {
Code[i] = Start[Len[i]]++;
}
}
STATIC
INT32
MakeTree (
)
/*++
Generates Huffman codes given a frequency distribution of symbols
NParm - number of symbols
FreqParm - frequency of each symbol
LenParm - code length for each symbol
CodeParm - code for each symbol
Returns:
Root of the Huffman tree.
1958Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
--*/
{
INT32 i, j, k, Avail;
//
// make tree, calculate len[], return root
//
mN = NParm;
mFreq = FreqParm;
mLen = LenParm;
Avail = mN;
mHeapSize = 0;
mHeap[1] = 0;
for (i = 0; i < mN; i++) {
mLen[i] = 0;
if (mFreq[i]) {
mHeap[++mHeapSize] = (INT16)i;
}
}
if (mHeapSize < 2) {
CodeParm[mHeap[1]] = 0;
return mHeap[1];
}
for (i = mHeapSize / 2; i >= 1; i--) {
//
// make priority queue
//
DownHeap(i);
}
mSortPtr = CodeParm;
do {
i = mHeap[1];
if (i < mN) {
*mSortPtr++ = (UINT16)i;
}
mHeap[1] = mHeap[mHeapSize--];
DownHeap(1);
j = mHeap[1];
if (j < mN) {
*mSortPtr++ = (UINT16)j;
}
k = Avail++;
mFreq[k] = (UINT16)(mFreq[i] + mFreq[j]);
mHeap[1] = (INT16)k;
mLeft[k] = (UINT16)i;
mRight[k] = (UINT16)j;
} while (mHeapSize > 1);
MakeLen(k);
MakeCode(NParm, LenParm, CodeParm);
//
1959Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// return root
//
return k;
}
1960APPENDIX
I
DECOMPRESSION SOURCE CODE
=/*++
Decompress.c
Abstract:
Decompressor.
--*/
#include "EfiCommon.h"
#define BITBUFSIZ 16
#define BAD_TABLE -1
//
// C: Char&Len Set; P: Position Set; T: exTra Set
//
#define NC (0xff + MAXMATCH + 2 - THRESHOLD)
#if NT > NP
#else
#endif
UINT8 *mSrcBase; //Starting address of compressed data
UINT8 *mDstBase; //Starting address of decompressed data
1961Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
UINT16 mBytesRemain;
UINT16 mBitCount;
UINT16 mBitBuf;
UINT16 mSubBitBuf;
UINT16 mBufSiz;
UINT16 mBlockSize;
UINT32 mDataIdx;
UINT32 mCompSize;
UINT32 mOrigSize;
UINT32 mOutBuf;
UINT32 mInBuf;
UINT16 mBadTableFlag;
UINT8 mBuffer[WNDSIZ];
UINT16 mLeft[2 *NC - 1];
UINT16 mRight[2 *NC - 1];
UINT32 mBuf;
UINT8 mCLen[NC];
UINT8 mPTLen[NPT];
UINT16 mCTable[4096];
UINT16 mPTTable[256];
} SCRATCH_DATA;
//
//
STATIC
VOID
FillBuf (
IN SCRATCH_DATA *Sd,
IN UINT16 NumOfBits
);
STATIC
VOID
Decode (
SCRATCH_DATA *Sd,
UINT16 NumOfBytes
);
//
// Functions
//
EFIAPI
GetInfo (
OUT UINT32 *DstSize,
)
/*++
1962Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
The implementation of EFI_DECOMPRESS_PROTOCOL.GetInfo().
This - Protocol instance pointer.
Source - The source buffer containing the compressed data.
SrcSize - The size of source buffer
DstSize - The size of destination buffer.
ScratchSize - The size of scratch buffer.
Returns:
EFI_SUCCESS - The size of destination buffer and the size of scratch
buffer are successful retrieved.
EFI_INVALID_PARAMETER - The source data is corrupted
--*/
{
UINT8*Src;
*ScratchSize = sizeof (SCRATCH_DATA);
Src = Source;
if (SrcSize < 8) {
return EFI_INVALID_PARAMETER;
}
*DstSize = Src[4] + (Src[5] << 8) + (Src[6] << 16) + (Src[7] << 24);
}
EFIAPI
Decompress (
IN UINT32 DstSize,
)
/*++
The implementation of EFI_DECOMPRESS_PROTOCOL.Decompress().
This - The protocol instance.
SrcSize - The size of the source buffer
Destination - The destination buffer to store the decompressed data
1963Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
DstSize - The size of the destination buffer.
Scratch - The buffer used internally by the decompress routine. This
buffer is needed to store intermediate data.
Returns:
EFI_SUCCESS - Decompression is successful
--*/
{
UINT32 Index;
UINT32 CompSize;
UINT32 OrigSize;
UINT8 *Dst1;
SCRATCH_DATA *Sd;
UINT8 *Src;
UINT8 *Dst;
Status = EFI_SUCCESS;
Dst = Destination;
Dst1 = Dst;
if (ScratchSize < sizeof (SCRATCH_DATA)) {
}
Sd = (SCRATCH_DATA *)Scratch;
}
CompSize = Src[0] + (Src[1] << 8) + (Src[2] << 16) + (Src[3] << 24);
OrigSize = Src[4] + (Src[5] << 8) + (Src[6] << 16) + (Src[7] << 24);
if (SrcSize < CompSize + 8) {
}
Src = Src + 8;
for (Index = 0; Index < sizeof(SCRATCH_DATA); Index++) {
((UINT8*)Sd)[Index] = 0;
}
Sd->mBytesRemain = (UINT16)(-1);
Sd->mSrcBase = Src;
Sd->mDstBase = Dst;
Sd->mCompSize = CompSize;
Sd->mOrigSize = OrigSize;
//
1964Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
// Fill the first two bytes
//
FillBuf(Sd, BITBUFSIZ);
while (Sd->mOrigSize > 0) {
Count = (UINT16) (WNDSIZ < Sd->mOrigSize? WNDSIZ: Sd->mOrigSize);
Decode (Sd, Count);
if (Sd->mBadTableFlag != 0) {
//
// Something wrong with the source
//
}
for (Index = 0; Index < Count; Index ++) {
if (Dst1 < Dst + DstSize) {
*Dst1++ = Sd->mBuffer[Index];
} else {
}
}
Sd->mOrigSize -= Count;
}
Status = EFI_INVALID_PARAMETER;
} else {
}
}
STATIC
VOID
FillBuf (
)
/*++
Shift mBitBuf NumOfBits left. Read in NumOfBits of bits from source.
Sd - The global scratch data
NumOfBit - The number of bits to shift and read.
--*/
{
1965Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Sd->mBitBuf = (UINT16)(Sd->mBitBuf << NumOfBits);
while (NumOfBits > Sd->mBitCount) {
Sd->mBitBuf \|= (UINT16)(Sd->mSubBitBuf <<
(NumOfBits = (UINT16)(NumOfBits - Sd->mBitCount)));
if (Sd->mCompSize > 0) {
//
// Get 1 byte into SubBitBuf
//
Sd->mCompSize --;
Sd->mSubBitBuf = 0;
Sd->mSubBitBuf = Sd->mSrcBase[Sd->mInBuf ++];
Sd->mBitCount = 8;
} else {
}
}
Sd->mBitCount = (UINT16)(Sd->mBitCount - NumOfBits);
Sd->mBitBuf \|= Sd->mSubBitBuf >> Sd->mBitCount;
}
STATIC
UINT16
GetBits(
)
/*++
Get NumOfBits of bits out from mBitBuf. Fill mBitBuf with subsequent
NumOfBits of bits from source. Returns NumOfBits of bits that are
popped out.
Sd - The global scratch data.
NumOfBits - The number of bits to pop and read.
Returns:
The bits that are popped out.
--*/
{
UINT16 OutBits;
OutBits = (UINT16)(Sd->mBitBuf >> (BITBUFSIZ - NumOfBits));
1966Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
FillBuf (Sd, NumOfBits);
return OutBits;
}
STATIC
UINT16
MakeTable (
IN UINT16 NumOfChar,
IN UINT8 *BitLen,
IN UINT16 TableBits,
OUT UINT16 *Table
)
/*++
Creates Huffman Code mapping table according to code length array.
NumOfChar - Number of symbols in the symbol set
BitLen - Code length array
TableBits - The width of the mapping table
Table - The table
Returns:
0 - OK.
BAD_TABLE - The table is corrupted.
--*/
{
UINT16 Count[17];
UINT16 Weight[17];
UINT16*p;
UINT16 k;
UINT16 i;
UINT16 Len;
UINT16 Char;
UINT16 JuBits;
UINT16 Avail;
UINT16 NextCode;
UINT16 Mask;
for (i = 1; i <= 16; i ++) {
Count[i] = 0;
}
for (i = 0; i < NumOfChar; i++) {
Count[BitLen[i]]++;
}
1967Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

}
STATIC
UINT16
)
/*++
Returns:
0 - OK.
--*/
{
UINT16*p;
UINT16 k;
UINT16 i;
}
}
Start[i + 1] = (UINT16)(Start[i] + (Count[i] << (16 - i)));
}
if (Start[17] != 0) {/ *(1U << 16) */
return (UINT16)BAD_TABLE;
}
JuBits = (UINT16)(16 - TableBits);
for (i = 1; i <= TableBits; i ++) {
Start[i] >>= JuBits;
Weight[i] = (UINT16)(1U << (TableBits - i));
}
while (i <= 16) {
Weight[i++] = (UINT16)(1U << (16 - i));
}
i = (UINT16)(Start[TableBits + 1] >> JuBits);
if (i != 0) {
k = (UINT16)(1U << TableBits);
while (i != k) {
Table[i++] = 0;
}
}
Avail = NumOfChar;
Mask = (UINT16)(1U << (15 - TableBits));
for (Char = 0; Char < NumOfChar; Char++) {
Len = BitLen[Char];
if (Len == 0) {
continue;
}
NextCode = (UINT16)(Start[Len] + Weight[Len]);
if (Len <= TableBits) {
for (i = Start[Len]; i < NextCode; i ++) {
Table[i] = Char;
}
} else {
k = Start[Len];
p = &Table[k >> JuBits];
i = (UINT16)(Len - TableBits);
while (i != 0) {
if (*p == 0) {
Sd->mRight[Avail] = Sd->mLeft[Avail] = 0;
*p = Avail ++;
}
1968Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
if (k & Mask) {
p = &Sd->mRight[ *p];
} else {
p = &Sd->mLeft[ *p];
}
k <<= 1;
i --;
}
*p = Char;
}
Start[Len] = NextCode;
}
//
// Succeeds
//
return 0;
}
STATIC
UINT16
DecodeP (
IN SCRATCH_DATA *Sd
)
/*++
Routine description:
Decodes a position value.
Sd - the global scratch data
Returns:
The position value decoded.
--*/
{
UINT16 Val;
Val = Sd->mPTTable[Sd->mBitBuf >> (BITBUFSIZ - 8)];
if (Val >= NP) {
Mask = 1U << (BITBUFSIZ - 1 - 8);
do {
if (Sd->mBitBuf & Mask) {
Val = Sd->mRight[Val];
1969Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
} else {
Val = Sd->mLeft[Val];
}
Mask >>= 1;
} while (Val >= NP);
}
//
// Advance what we have read
//
FillBuf (Sd, Sd->mPTLen[Val]);
if (Val) {
Val = (UINT16)((1U << (Val - 1)) + GetBits (Sd, (UINT16)(Val - 1)));
}
return Val;
}
STATIC
UINT16
ReadPTLen (
IN UINT16 nn,
IN UINT16 nbit,
IN UINT16 Special
)
/*++
Routine Description
Reads code lengths for the Extra Set or the Position Set
nn - Number of symbols
nbit - Number of bits needed to represent nn
Special - The special symbol that needs to be taken care of
Returns:
0 - OK.
BAD_TABLE - Table is corrupted.
--*/
{
UINT16 n;
UINT16 c;
UINT16 i;
n = GetBits (Sd, nbit);
if (n == 0) {
c = GetBits (Sd, nbit);
1970Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
for ( i = 0; i < 256; i ++) {
Sd->mPTTable[i] = c;
}
for ( i = 0; i < nn; i++) {
Sd->mPTLen[i] = 0;
}
return 0;
}
i = 0;
c = (UINT16)(Sd->mBitBuf >> (BITBUFSIZ - 3));
if (c == 7) {
Mask = 1U << (BITBUFSIZ - 1 - 3);
while (Mask & Sd->mBitBuf) {
Mask >>= 1;
c += 1;
}
}
FillBuf (Sd, (UINT16)((c < 7) ? 3 : c - 3));
Sd->mPTLen [i++] = (UINT8)c;
c = GetBits (Sd, 2);
while ((INT16)(--c) >= 0) {
Sd->mPTLen[i++] = 0;
}
}
}
while (i < nn) {
Sd->mPTLen [i++] = 0;
}
return ( MakeTable (Sd, nn, Sd->mPTLen, 8, Sd->mPTTable) );
}
STATIC
VOID
ReadCLen (
SCRATCH_DATA *Sd
)
/*++
Reads code lengths for Char&Len Set.
1971Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
--*/
{
UINT16 n;
UINT16 c;
UINT16 i;
n = GetBits(Sd, CBIT);
if (n == 0) {
c = GetBits(Sd, CBIT);
for (i = 0; i < NC; i ++) {
Sd->mCLen[i] = 0;
}
for (i = 0; i < 4096; i ++) {
Sd->mCTable[i] = c;
}
return;
}
i = 0;
c = Sd->mPTTable[Sd->mBitBuf >> (BITBUFSIZ - 8)];
if (c >= NT) {
do {
if (Mask & Sd->mBitBuf) {
c = Sd->mRight [c];
} else {
c = Sd->mLeft [c];
}
Mask >>= 1;
}while (c >= NT);
}
//
//
FillBuf (Sd, Sd->mPTLen[c]);
if (c <= 2) {
if (c == 0) {
1972Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
c = 1;
} else if (c == 1) {
c = (UINT16)(GetBits (Sd, 4) + 3);
} else if (c == 2) {
c = (UINT16)(GetBits (Sd, CBIT) + 20);
}
Sd->mCLen[i++] = 0;
}
} else {
Sd->mCLen[i++] = (UINT8)(c - 2);
}
}
while (i < NC) {
}
MakeTable (Sd, NC, Sd->mCLen, 12, Sd->mCTable);
return;
}
STATIC
UINT16
DecodeC (
)
/*++
Decode a character/length value.
Returns:
The value decoded.
--*/
{
UINT16 j;
if (Sd->mBlockSize == 0) {
//
// Starting a new block
//
1973Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Sd->mBlockSize = GetBits(Sd, 16);
Sd->mBadTableFlag = ReadPTLen (Sd, NT, TBIT, 3);
return 0;
}
ReadCLen (Sd);
Sd->mBadTableFlag = ReadPTLen (Sd, NP, PBIT, (UINT16)(-1));
return 0;
}
}
Sd->mBlockSize --;
j = Sd->mCTable[Sd->mBitBuf >> (BITBUFSIZ - 12)];
if (j >= NC) {
Mask = 1U << (BITBUFSIZ - 1 - 12);
do {
j = Sd->mRight[j];
} else {
j = Sd->mLeft[j];
}
Mask >>= 1;
} while (j >= NC);
}
//
//
FillBuf(Sd, Sd->mCLen[j]);
return j;
}
STATIC
VOID
Decode (
)
/*++
Decode NumOfBytes and put the resulting data at starting point of mBuffer.
The buffer is circular.
NumOfBytes - Number of bytes to decode
1974Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
--*/
{
UINT16 di;
UINT16 r;
UINT16 c;
r = 0;
di = 0;
Sd->mBytesRemain --;
while ((INT16)(Sd->mBytesRemain) >= 0) {
Sd->mBuffer[di++] = Sd->mBuffer[Sd->mDataIdx++];
if (Sd->mDataIdx >= WNDSIZ) {
Sd->mDataIdx -= WNDSIZ;
}
r ++;
if (r >= NumOfBytes) {
return;
}
}
for (;;) {
c = DecodeC (Sd);
return;
}
if (c < 256) {
//
// Process an Original character
//
Sd->mBuffer[di++] = (UINT8)c;
r ++;
if (di >= WNDSIZ) {
return;
}
} else {
//
// Process a Pointer
//
c = (UINT16)(c - (UINT8_MAX + 1 - THRESHOLD));
Sd->mBytesRemain = c;
Sd->mDataIdx = (r - DecodeP(Sd) - 1) & (WNDSIZ - 1); //Make circular
di = r;
1975Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
}
r ++;
return;
}
}
}
return;
}
1976APPENDIX
J
EFI BYTE CODE VIRTUAL MACHINE OPCODE LIST
The following table lists the opcodes for EBC instructions. Note that opcodes only require 6 bits of the opcode byte
of EBC instructions. The other two bits are used for other encodings that are dependent on the particular instruction.
Table J.1: EBC Virtual Machine Opcode Summary
0x00 BREAK [break code]
0x01 JMP 32{cs {@}R1 {Immed32
0x02 JMP8 {cs Immed8
0x03 CALL 32{EX}{a} {@}R1 {Immed32
0x04 RET
0x05 CMP [32 R1, {@}R2 {Index16
0x06 CMP [32 R1, {@}R2 {Index16
0x07 CMP [32 R1, {@}R2 {Index16
0x08 CMP [32 R1, {@}R2 {Index16
0x09 CMP [32 R1, {@}R2 {Index16
0x0A NOT [32 {@}R1, {@}R2 {Index16
0x0B NEG [32 {@}R1,{@}R2 {Index16
0x0C ADD [32 {@}R1,{@}R2 {Index16
0x0D SUB [32 {@}R1,{@}R2 {Index16
0x0E MUL [32 {@}R1,{@}R2 {Index16
0x0F MULU [32 {@}R1,{@}R2 {Index16
0x10 DIV [32 {@}R1,{@}R2 {Index16
0x11 DIVU [32 {@}R1,{@}R2 {Index16
0x12 MOD [32 {@}R1,{@}R2 {Index16
0x13 MODU [32 {@}R1,{@}R2 {Index16
0x14 AND [32 {@}R1,{@}R2 {Index16
0x15 OR[32 {@}R1,{@}R2 {Index16
0x16 XOR [32 {@}R1,{@}R2 {Index16
0x17 SHL [32 {@}R1,{@}R2 {Index16
0x18 SHR [32 {@}R1,{@}R2 {Index16
0x19 ASHR [32 {@}R1,{@}R2 {Index16
0x1A EXTNDB [32 {@}R1, {@}R2 {Index16
0x1B EXTNDW [32 {@}R1,{@}R2 {Index16
0x1C EXTNDD [32 {@}R1,{@}R2 {Index16
0x1D MOV bw {@}R1 {Index16}, {@}R2 {Index16}
0x1E MOV ww {@}R1 {Index16}, {@}R2 {Index16}
0x1F MOV dw {@}R1 {Index16}, {@}R2 {Index16}
0x20 MOV qw {@}R1 {Index16}, {@}R2 {Index16}
1977Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table J.1 – continued from previous page
0x21 MOV bd {@}R1 {Index32}, {@}R2 {Index32}
0x22 MOV wd {@}R1 {Index32}, {@}R2 {Index32}
0x23 MOV dd {@}R1 {Index32}, {@}R2 {Index32}
0x24 MOV qd {@}R1 {Index32}, {@}R2 {Index32}
0x25 MOVsn w {@}R1 {Index16}, {@}R2 {Index16
0x26 MOVsn d {@}R1 {Index32}, {@}R2 {Index32
0x27 Reserved
0x28 MOV qq {@}R1 {Index64}, {@}R2 {Index64}
0x29 LOADSP [Flags], R2
0x2A STORESP R1, [IP|Flags]
0x2B PUSH [32 {@}R1 {Index16
0x2C POP [32 {@}R1 {Index16
0x2D CMPI [32 {@}R1 {Index16}, Immed16
0x2E CMPI [32 {@}R1 {Index16}, Immed16
0x2F CMPI [32 {@}R1 {Index16}, Immed16
0x30 CMPI [32 {@}R1 {Index16}, Immed16
0x31 CMPI [32 {@}R1 {Index16}, Immed16

0x32 MOVn w {@}R1 {Index16}, {@}R2 {Index16}
0x33 MOVn d {@}R1 {Index32}, {@}R2 {Index32}
0x34 Reserved
0x35 PUSHn {@}R1 {Index16
0x36 POPn {@}R1 {Index16
0x37 MOVI [b {@}R1 {Index16}, Immed16
0x38 MOVIn [w {@}R1 {Index16}, Index16
0x39 MOVREL [w {@}R1 {Index16}, Immed16
0x3A Reserved
0x3B Reserved
0x3C Reserved
0x3D Reserved
0x3E Reserved
0x3F Reserved
1978APPENDIX
K
ALPHABETIC FUNCTION LISTS
This appendix was redacted in version 2.6.
1979APPENDIX
L
EFI 1.10 PROTOCOL CHANGES AND DEPRECATION LIST
L.1 Protocol and GUID Name Changes from EFI 1.10
This appendix lists the Protocol , GUID, and revision identiﬁer name changes and the deprecated protocols compared
to the EFI Speciﬁcation 1.10. The protocols listed are not Runtime, Reentrant or MP Safe. Protocols are listed by EFI
1.10 name.
For protocols in the table whose TPL is not <= TPL_NOTIFY:
This function must be called at a TPL level less then or equal to %%%%.
%%%% is TPL_CALLBACK or TPL_APPLICATION. The <= is done via text.
Table L.1: Protocol Name changes
EFI 1.10 Protocol Name UEFI Speciﬁcation Protocol Name
EFI_LOADED_IMAGE EFI_LOADED_IMAGE_PROTOCOL
TPL <= TPL_NOTIFY
New GUID name EFI_LOADED_IMAGE_PROTOCOL_GUID
EFI_DEVICE_PATH EFI_DEVICE_PATH_PROTOCOL
New GUID name EFI_DEVICE_PATH_PROTOCOL_GUID
SIMPLE_INPUT_INTERFACE EFI_SIMPLE_INPUT_PROTOCOL
TPL <= TPL_APPLICATION
New GUID name EFI_SIMPLE_INPUT_PROTOCOL_GUID
SIMPLE_TEXT_OUTPUT_INTERFACE EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL
TPL <=TPL_CALLBACK
New GUID name EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID
SERIAL_IO_INTERFACE EFI_SERIAL_IO_PROTOCOL
New GUID name EFI_SERIAL_IO_PROTOCOL_GUID
EFI_LOAD_FILE_INTERFACE EFI_LOAD_FILE_PROTOCOL
New GUID name EFI_LOAD_FILE_PROTOCOL_GUID
EFI_FILE_IO_INTERFACE EFI_SIMPLE_FILE_SYSTEM_PROTOCOL
New GUID name EFI_FILE_SYSTEM_PROTOCOL_GUID
EFI_FILE EFI_FILE_PROTOCOL
TPL <= TPL_CALLBACK
New GUID name EFI_FILE_PROTOCOL_GUID
EFI_DISK_IO EFI_DISK_IO_PROTOCOL
1980Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table L.1 – continued from previous page
New GUID name EFI_DISK_IO_PROTOCOL_GUID
EFI_BLOCK_IO EFI_BLOCK_IO_PROTOCOL
New GUID name EFI_BLOCK_IO_PROTOCOL_GUID
UNICODE_COLLATION_INTERFACE EFI_UNICODE_COLLATION_PROTOCOL
New GUID name EFI_UNICODE_COLLATION_PROTOCOL_GUID
EFI_SIMPLE_NETWORK EFI_SIMPLE_NETWORK_PROTOCOL
New GUID name EFI_SIMPLE_NETWORK_PROTOCOL_GUID
EFI_NETWORK_INTERFACE_IDENTIFIER _IN-
TERFACEEFI_NETW ORK_INTERFACE_IDENTIFIER _PRO-
TOCOL
New GUID name EFI_NETWORK_INTERFACE_IDENTIFIER _PRO-
TOCOL_GUID
EFI_PXE_BASE_CODE EFI_PXE_BASE_CODE_PROTOCOL
New GUID name EFI_PXE_BASE_CODE _PROTOCOL_GUID
EFI_PXE_BASE_CODE_CALLBACK EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL
New GUID name EFI_PXE _BASE_CODE_CALLBACK_PROTOCOL
_GUID
EFI_DEVICE_IO_INTERFACE EFI_DEVICE_IO_PROTOCOL
New GUID name EFI_DEVICE_IO_PROTOCOL_GUID
Table L.2: Revision Identiﬁer Name Changes
EFI 1.10 Revision Identiﬁer Name UEFI Speciﬁcation Revision Identiﬁer Name
EFI_LOADED_IMAGE_INFORMATION
_REVISIONEFI_LOADED_IMAGE_PROTOCOL_REVISION
SERIAL_IO_INTERFACE_REVISION EFI_SERIAL_IO_PROTOCOL_REVISION
EFI_FILE_IO_INTERFACE_REVISION EFI_SIM PLE_FILE_SYSTEM_PROTOCOL _REVISION
EFI_FILE_REVISION EFI_FILE_PROTOCOL_REVISION
EFI_DISK_IO_INTERFACE_REVISION EFI_DISK_IO_PROTOCOL_REVISION
EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION
EFI_SIMPLE_NETWORK_INTERFACE
_REVISIONEFI_SIMPLE_NETWORK_PROTOCOL _REVISION
EFI_NETWORK_INTERFACE_IDENTIFIER
_INTERFACE_REVISIONEFI_NETWORK_INTERFACE_IDENTIFIER _PROTO-
COL_REVISION
EFI_PXE_BASE_CODE _INTER-
FACE_REVISIONEFI_PXE_BASE_CODE_PROTOCOL_REVISION
EFI_PXE_BASE_CODE_CALLBACK
_INTERFACE_REVISIONEFI_PXE_BASE_CODE_CALLBACK _PROTO-
L.1. Protocol and GUID Name Changes from EFI 1.10 1981Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
L.2 Deprecated Protocols
Device I/O Protocol - The support of the Device I/O Protocol (see EFI 1.1 Chapter 18) has been replaced by the use
of the PCI Root Bridge I/O protocols which are described in PCI Root Bridge I/O Protocol of the UEFI Speciﬁcation.
Note: certain “legacy” EFI applications such as some of the ones that reside in the EFI Toolkit assume the presence of
Device I/O.
UGA I/O + UGA Draw Protocol - The support of the UGA * Protocols (see EFI 1.1 Section 10.7) have been replaced
by the use of the EFI Graphics Output Protocol described in Protocols — Console Support of the UEFI Speciﬁcation.
USB Host Controller Protocol (version that existed for EFI 1.1) - The support of the USB Host Controller Protocol
(see EFI 1.1 Section 14.1) has been replaced by the use of a UEFI instance that covers both USB 1.1 and USB 2.0
support, and is described in Protocols — USB Support of the UEFI Speciﬁcation. It replaces the pre-existing protocol
deﬁnition.
SCSI Passthru Protocol - The support of the SCSI Passthru Protocol (see EFI 1.1 Section 13.1) has been replaced by
the use of the Extended SCSI Passthru Protocol, which is described in Section 15.7.
BIS Protocol - Remains as an optional protocol.
Driver Conﬁguration Protocol - the EFI_DRIVER_CONFIGURATION_PROTOCOL has been removed.
L.2. Deprecated Protocols 1982APPENDIX
M
FORMATS — LANGUAGE CODES AND LANGUAGE CODE ARRAYS
This appendix lists the formats for language codes and language code arrays.
M.1 Specifying individual language codes
The preferred representation of a language code is done via an RFC 4646 language code identiﬁer*.
Alias codes supported in addition to RFC 4646
Table M.1: Alias Codes Supported in Addition to RFC 4646
RFC string Supported Alias String
zh-Hans zh-chs
zh-Hant zh-cht
An RFC 4646 language code is represented as a null-terminated ASCII string.
An RFC 4646 language string must be constructed according to the tag creation rules in section 2.3 of RFC 4646. For
example, when constructing the primary language tag for a locale identiﬁer, if a 2 character ISO 639-1 language code
exists along with a 3 character ISO 639-2 language code, then the ISO 639-1 language code must be used. Further, if
an ISO 639-1 tag does not exist, then the ISO 639-2/T (Terminology) tag must be for the primary locale before an ISO
639-2/B (Bibliographic) tag may be used. See RFC 4646 for a complete discussion of this topic.
To provide backwards compatibility with preexisting EFI 1.10 drivers, a UEFI platforms may sup-
port deprecated protocols which represent languages in the ISO 639-2 format. This includes the fol-
lowing protocols: UNICODE_COLLATION_INTERFACE ,EFI_DRIVER_CONFIGURATION_PROTOCOL ,
EFI_DRIVER_DIAGNOSTICS_PROTOCOL , and EFI_COMPONENT_NAME_PROTOCOL . The deprecated Lang-
Codes andLang global variables may also be supported by a platform for backwards compatibility.
M.1.1 Specifying language code arrays:
Native RFC 4646 format array:
An array of RFC 4646 character codes is represented as a NULL terminated char8 array of RFC 4646 language code
strings. Each of these strings is delimited by a semicolon (‘;’) character. For example, an array of US English and
Traditional Chinese would be represented as the NULL-terminated string “en-us;zh-Hant”.
1983APPENDIX
N
COMMON PLATFORM ERROR RECORD (CPER)
N.1 Introduction
This appendix describes the common platform error record (CPER) format for representing platform hardware errors.
N.2 Format
The general format of the common platform error record is illustrated in the Figure below . The record consists of a
header; followed by one or more section descriptors; and for each descriptor, an associated section which may contain
either error or informational data.
Fig. N.1: Error Record Format
1984Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.1 Record Header
The record header includes information which uniquely identiﬁes a hardware error record on a given system. The
contents of the record header are described in the Table below. The header is immediately followed by an array of
one or more section descriptors. Sections may be either error sections, which contain error information retrieved from
hardware, or they may be informational sections, which contain contextual information relevant to the error. An error
record must contain at least one section.
Table N.1: Error record header
Signature Start 0 4 ASCII 4-character array “CPER” (0x43,0 x50,0x45,0x52).
Identiﬁes this structure as a hardware error record.
Revision 4 2
This is a 2-byte ﬁeld representing a major and minor
version number for the error record deﬁnition in BCD
format. The interpretation of the major and minor version
number is as follows:
• Byte 0 - Minor (01): An increase in this revision indicates
that changes to the headers and sections are backward
compatible with software that use earlier revisions.
Addition of new GUID types, errata ﬁxes or clariﬁcations

are covered by a bump up.
• Byte 1 - Major (01): An increase in this revision indicates
that the changes are not backward compatible from a
software perspective.
Signature End 6 4 Must be 0xFFFFFFFF
Section Count 10 2 This ﬁeld indicates the number of valid sections associated
with the record, corresponding to each of the following sec-
tion descriptors.
Error Severity 12 4
Indicates the severity of the error condition. The severity of
the error record corresponds to the most severe error
section.
0 - Recoverable (also called non-fatal uncorrected)
1 - Fatal
2 - Corrected
3 - Informational
All other values are reserved.
Note that severity of “Informational” indicates that the
record could be safely ignored by error handling software.
Validation Bits 16 4
This ﬁeld indicates the validity of the following ﬁelds:
• Bit 0 - If 1, the PlatformID ﬁeld contains valid information
• Bit 1 - If 1, the TimeStamp ﬁeld contains valid information
• Bit 2 - If 1, the PartitionID ﬁeld contains valid information
• Bits 3-31: Reserved, must be zero.
N.2. Format 1985Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.1 – continued from previous page
Record Length 20 4 Indicates the size of the actual error record, including the
size of the record header, all section descriptors, and section
bodies. The size may include extra buffer space to allow
for the dynamic addition of error sections descriptors and
bodies.
Timestamp 24 8
The timestamp correlates to the time when the error
information was collected by the system software and may
not necessarily represent the time of the error event. The
timestamp contains the local time in BCD format.
• Byte 7 - Byte 0:
• Byte 0: Seconds
• Byte 1: Minutes
• Byte 2: Hours
• Byte 3:
• Bit 0 - Timestamp is precise if this bit is set and correlates
to the time of the error event.
• Bit 7:1 - Reserved
• Byte 4: Day
• Byte 5: Month
• Byte 6: Year
• Byte 7: Century
Platform ID 32 16 This ﬁeld uniquely identiﬁes the platform with a GUID. The
platform’s SMBIOS UUID should be used to populate this
ﬁeld. Error analysis software may use this value to uniquely
identify a platform.
Partition ID 48 16 If the platform has multiple software partitions, system soft-
ware may associate a GUID with the partition on which the
error occurred.
Creator ID 64 16 This ﬁeld contains a GUID indicating the creator of the error
record. This value may be overwritten by subsequent owners
of the record.
N.2. Format 1986Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Type80 16
This ﬁeld holds a pre-assigned GUID value indicating the
record association with an error event notiﬁcation type. The
deﬁned types are:
CMC
{0x2DCE8BB1, 0xBDD7, 0x450e, {0xB9, 0xAD, 0x9C,
0xF4, 0xEB, 0xD4, 0xF8, 0x90}}
CPE
{0x4E292F96, 0xD843, 0x4a55, {0xA8, 0xC2, 0xD4,
0x81, 0xF2, 0x7E, 0xBE, 0xEE}}
MCE
{0xE8F56FFE, 0x919C, 0x4cc5, {0xBA, 0x88, 0x65,
0xAB, 0xE1, 0x49, 0x13, 0xBB}}
PCIe
{0xCF93C01F, 0x1A16, 0x4dfc, {0xB8, 0xBC, 0x9C,
0x4D, 0xAF, 0x67, 0xC1, 0x04}}
INIT
{0xCC5263E8, 0x9308, 0x454a, {0x89, 0xD0, 0x34, 0x0B,
0xD3, 0x9B, 0xC9, 0x8E}}
NMI
{0x5BAD89FF, 0xB7E6, 0x42c9, {0x81, 0x4A, 0xCF,
0x24, 0x85, 0xD6, 0xE9, 0x8A}}
Boot
{0x3D61A466, 0xAB40, 0x409a, {0xA6, 0x98, 0xF3,
0x62, 0xD4, 0x64, 0xB3, 0x8F}}
DMAr
{0x667DD791, 0xC6B3, 0x4c27, {0x8A, 0x6B, 0x0F,
0x8E,0x72, 0x2D, 0xEB, 0x41}}
SEA
{0x9A78788A, 0xBBE8, 0x11E4, {0x80, 0x9E, 0x67,
0x61, 0x1E, 0x5D, 0x46, 0xB0}}
SEI
{0x5C284C81, 0xB0AE, 0x4E87, {0xA3, 0x22, 0xB0,
0x4C, 0x85, 0x62, 0x43, 0x23}}
PEI
{0x09A9D5AC, 0x5204, 0x4214, {0x96, 0xE5, 0x94,
0x99, 0x2E, 0x75, 0x2B, 0xCD}}
CXL Component
{0x69293BC9, 0x41DF, 0x49A3 {0xB4, 0xBD, 0x4F,
0xB0, 0xDB, 0x30, 0x41, 0xF6}}
continues on next pageN.2. Format 1987Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Record ID 96 8 This value, when combined with the Creator ID, uniquely
identiﬁes the error record across other error records on a
given system.
Flags 104 4 Flags ﬁeld contains information that describes the error
record. See Table 2 for deﬁned ﬂags.
Persistence In-
formation108 8 This ﬁeld is produced and consumed by the creator of the
error record identiﬁed in the Creator ID ﬁeld. The format of
this ﬁeld is deﬁned by the creator and it is out of scope of
Reserved 116 12 Reserved. Must be zero.
Section De-
scriptor128 Nx72 An array of SectionCount descriptors for the associated sec-
tions. The number of valid sections is equivalent to the Sec-
tionCount. The buffer size of the record may include more
space to dynamically add additional Section Descriptors to
the error record.
Error Record Header Flags
The following table lists ﬂags that can be used to qualify an error record in the Error Record Header’s Flags ﬁeld.
Table N.2: Error Record Header Flags
Value Description
1 HW_ERROR_FLAGS_RECOVERED: Qualiﬁes an error condition as one that has been recovered by sys-
tem software.
2 HW_ERROR_FLAGS_PREVERR: Qualiﬁes an error condition as one that occurred during a previous
session. For instance, of the OS detects an error and determines that the system must be reset; it will save
the error record before stopping the system. Upon restarting the OS marks the error record with this ﬂag to
know that the error is not live.
4 HW_ERROR_FLAGS_SIMULATED: Qualiﬁes an error condition as one that was intentionally caused.
This allows system software to recognize errors that are injected as a means of validating or testing error
handling mechanisms.
N.2.1.1 Notiﬁcation Type
A notiﬁcation type identiﬁes the mechanism by which an error event is reported to system software. This information
helps consumers of error information (e.g. management applications or humans) by identifying the source of the error
information. This allows, for instance, all CMC error log entries to be ﬁltered from an error event log.
Listed below are the standard notiﬁcation types. Each standard notiﬁcation type is identiﬁed by a GUID. For error
notiﬁcation types that do not conform to one of the standard types, a platform-speciﬁc GUID may be deﬁned to identify
the notiﬁcation type.
• Machine Check Exception (MCE): {0xE8F56FFE, 0x919C, 0x4cc5, {0xBA, 0x88, 0x65, 0xAB, 0xE1, 0x49,
0x13, 0xBB}} A Machine Check Exception is a processor-generated exception class interrupt used to system
software of the presence of a fatal or recoverable error condition.
• Corrected Machine Check (CMC): {0x2DCE8BB1, 0xBDD7, 0x450e, {0xB9, 0xAD, 0x9C, 0xF4,0xEB, 0xD4,
0xF8, 0x90}} Corrected Machine Checks identify error conditions that have been corrected by hardware or
system ﬁrmware. CMCs are reported by the processor and may be reported via interrupt or by polling error
status registers.
• Corrected Platform Error (CPE): {0x4E292F96, 0xD843, 0x4a55, {0xA8, 0xC2, 0xD4, 0x81, 0xF2, 0x7E,
N.2. Format 1988Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
0xBE, 0xEE}} Corrected Platform Errors identify corrected errors from the platform (i.e., external memory
controller, system bus, etc.). CPEs can be reported via interrupt or by polling error status registers.
• Non-Maskable Interrupt (NMI): {0x5BAD89FF, 0xB7E6, 0x42c9, {0x81, 0x4A, 0xCF, 0x24, 0x85, 0xD6,
0xE9, 0x8A}} Non-Maskable Interrupts are used on X64 platforms to report fatal or recoverable platform error
conditions. NMIs are reported via interrupt vector 2 on IA32 and X64 processor architecture platforms.
• PCI Express Error (PCIe): {0xCF93C01F, 0x1A16, 0x4dfc, {0xB8, 0xBC, 0x9C, 0x4D, 0xAF, 0x67, 0xC1,
0x04}} See the PCI Express standard v1.1 for details regarding PCI Express Error Reporting. This notiﬁcation
type identiﬁes errors that were reported to the system via an interrupt on a PCI Express root port.
• INIT Record (INIT): {0xCC5263E8, 0x9308, 0x454a, {0x89, 0xD0, 0x34, 0x0B, 0xD3, 0x9B, 0xC9, 0x8E}}
IPF Platforms optionally implement a mechanism (switch or button on the chassis) by which an operator may
reset a system and have the system generate an INIT error record. This error record is documented in the
IPF SAL speciﬁcation. System software retrieves an INIT error record by querying the SAL for existing INIT
records.
• BOOT Error Record (BOOT): {0x3D61A466, 0xAB40, 0x409a, {0xA6, 0x98, 0xF3, 0x62, 0xD4, 0x64, 0xB3,
0x8F}}
The BOOT Notiﬁcation Type represents error conditions which are unhandled by system software and which
result in a system shutdown/reset. System software retrieves a BOOT error record during boot by querying the
platform for existing BOOT records. As an example, consider an x64 platform which implements a service
processor. In some scenarios, the service processor may detect that the system is either hung or is in such a
state that it cannot safely proceed without risking data corruption. In such a scenario the service processor may

records.
0x8F}}
record some minimal error information in its system event log (SEL) and unilaterally reset the machine without
notifying the OS or other system software. In such scenarios, system software is unaware of the condition that
caused the system reset. A BOOT error record would contain information that describes the error condition
that led to the reset so system software can log the information and use it for health monitoring.
• DMA Remapping Error (DMAr): {0x667DD791, 0xC6B3, 0x4c27, {0x8A, 0x6B, 0x0F, 0x8E, 0x72, 0x2D,
0xEB, 0x41}} The DMA Remapping Notiﬁcation Type identiﬁes fault conditions generated by the DMAr unit
when processing un-translated, translation and translated DMA requests. The fault conditions are reported to
the system using a message signaled interrupt.
• Synchronous External Abort (SEA): {0x9A78788A, 0xBBE8, 0x11E4, {0x80, 0x9E, 0x67, 0x61, 0x1E, 0x5D,
0x46, 0xB0}}
Synchronous External Aborts represent precise processor error conditions on ARM systems (uncorrectable
and/or recoverable) as described in D3.5 of the ARMv8 ARM reference manual. This notiﬁcation may be
triggered by one of the following scenarios: cache parity error, cache ECC error, external bus error,
micro-architectural error, data poisoning, and other platform errors.
• SError Interrupt (SEI): {0x5C284C81, 0xB0AE, 0x4E87, {0xA3, 0x22, 0xB0, 0x4C, 0x85, 0x62, 0x43, 0x23}}
SError Interrupts represent asynchronous imprecise (or possibly precise) processor error conditions on ARM
systems (corrected, uncorrectable, and recoverable) as described in D3.5 of the ARM ARM reference manual.
This notiﬁcation may be triggered by one of the following scenarios: cache parity error, cache ECC error,
external bus error, micro-architectural error, data poisoning, and other platform errors.
• Platform Error Interrupt (PEI): {0x09A9D5AC, 0x5204, 0x4214, {0x96, 0xE5, 0x94, 0x99, 0x2E, 0x75, 0x2B,
0xCD} Platform Error Interrupt represent asynchronous imprecise platform error conditions on ARM systems
that may be triggered by the following scenarios: system memory ECC error, ECC errors in system cache (e.g.
shared high-level caches), vendor speciﬁc chip errors, external platform errors.
• Compute Express Link (CXL) Component: {0x69293BC9, 0x41DF, 0x49A3 {0xB4, 0xBD, 0x4F, 0xB0, 0xDB,
0x30, 0x41, 0xF6}} This Notiﬁcation Type identiﬁes errors that were reported to the system by CXL compo-
nents that support error reporting via the CXL RAS Mailbox interface. See the CXL Speciﬁcation, Rev 2.0 or
later, for details regarding CXL Error Reporting.
N.2. Format 1989Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.1.2 Error Status
The error status deﬁnition provides the capability to abstract information from implementation-speciﬁc error registers
into generic error codes.
Table N.3: Error Status Fields
Bit Position Description
7:0 Reserved
15:8 Encoded value for the Error_Type. See Table 20 Error Types for details.
16 Address: Error was detected on the address signals or on the address portion of the transac-
tion.
17 Control: Error was detected on the control signals or in the control portion of the transaction.
18 Data: Error was detected on the data signals or in the data portion of the transaction.
19 Responder: Error was detected by the responder of the transaction.
20 Requester: Error was detected by the requester of the transaction.
21 First Error: If multiple errors are logged for a section type, this is the ﬁrst error in the chrono-
logical sequence. Setting of this bit is optional.
22 Overﬂow: Additional errors occurred and were not logged due to lack of logging resources.
63:23 Reserved.
Table N.4: Error Types
Encoding Description
1 ERR_INTERNAL Error detected internal to the component.
16 ERR_BUS Error detected in the bus.
Detailed Internal Errors
4 ERR_MEM Storage error in memory (DRAM).
5 ERR_TLB Storage error in TLB.
6 ERR_CACHE Storage error in cache.
7 ERR_FUNCTION Error in one or more functional units.
8 ERR_SELFTEST component failed self test.
9 ERR_FLOW Overﬂow or undervalue of internal queue.
Detailed Bus Errors
17 ERR_MAP Virtual address not found on IO-TLB or IO-PDIR.
18 ERR_IMPROPER Improper access error.
19 ERR_UNIMPL Access to a memory address which is not mapped to any component.
20 ERR_LOL Loss of Lockstep
21 ERR_RESPONSE Response not associated with a request
22 ERR_PARITY Bus parity error (must also set the A, C, or D Bits).
23 ERR_PROTOCOL Detection of a protocol error.
24 ERR_ERROR Detection of a PATH_ERROR
25 ERR_TIMEOUT Bus operation timeout.
26 ERR_POISONED A read was issued to data that has been poisoned.
All Others Reserved
N.2. Format 1990Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.2 Section Descriptor
Table N.5: Section Descriptor
Section Offset 0 4 Offset in bytes of the section body from the base of the record header.
Section
Length4 4 The length in bytes of the section body.
Revision 8 2
This is a 2-byte ﬁeld representing a major and minor version number for
the error record deﬁnition in BCD format. The interpretation of the
major and minor version number is as follows:
• Byte 0 — Minor (00): An increase in this revision indicates that
changes to the headers and sections are backward compatible with
software that uses earlier revisions. Addition of new GUID types, errata
ﬁxes or clariﬁcations are covered by a bump up.
• Byte 1 — Major (01): An increase in this revision indicates that the
changes are not backward compatible from a software perspective
Validation
Bits10 1
• Bit 0 - If 1, the FRUId ﬁeld contains valid information
• Bit 1 - If 1, the FRUString ﬁeld contains valid information
• Bits 7:2 - Reserved, must be zero.
Reserved 11 1 Must be zero.
N.2. Format 1991Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.5 – continued from previous page
Flags 12 4
Flag ﬁeld contains information that describes the error section as follows:
Bit 0 - Primary: If set, identiﬁes the section as the section to be
associated with the error condition. This allows for FRU determination
and for error recovery operations. By identifying a primary section, the
consumer of an error record can determine which section to focus on. It
is not always possible to identify a primary section so this ﬂag should be
taken as a hint.
Bit 1 - Containment Warning: If set, the error was not contained within
the processor or memory hierarchy and the error may have propagated to
persistent storage or network.
Bit 2 - Reset: If set, the component has been reset and must be
re-initialized or re-enabled by the operating system prior to use.
Bit 3 - Error threshold exceeded: If set, OS may choose to discontinue
use of this resource.
Bit 4 - Resource not accessible: If set, the resource could not be queried
for error information due to conﬂicts with other system software or
resources. Some ﬁelds of the section will be invalid.
Bit 5 - Latent error: If set this ﬂag indicates that action has been taken to
ensure error containment (such a poisoning data), but the error has not
been fully corrected and the data has not been consumed. System
software may choose to take further corrective action before the data is
consumed.
Bit 6 - Propagated: If set this ﬂag indicates the section is to be associated
with an error that has been propagated due to hardware poisoning. This
implies the error is a symptom of another error. It is not always possible
to ascertain whether this is the case for an error, therefore if the ﬂag is
not set, it is unknown whether the error was propagated. this helps
determining FRU when dealing with HW failures.
Bit 7 - Overﬂow: If set this ﬂag indicates the ﬁrmware has detected an
overﬂow of buffers/queues that are used to accumulate, collect, or report
errors (e.g. the error status control block exposed to the OS). When this
occurs, some error records may be lost.
Bit 8 through 31 - Reserved.
N.2. Format 1992Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Section Type 16 16
This ﬁeld holds a pre-assigned GUID value indicating that it is a section
of a particular error. The different error section types are as deﬁned
below:
Processor Generic
• {0x9876CCAD, 0x47B4, 0x4bdb, {0xB6, 0x5E, 0x16, 0xF1, 0x93,
0xC4, 0xF3, 0xDB}}
Processor Speciﬁc
• IA32/X 64:{0xDC3EA0B0, 0xA144, 0x4797, {0xB9, 0x5B, 0x53,
0xFA, 0x24, 0x2B, 0x6E, 0x1D}}
• IPF: {0xe429faf1, 0x3cb7, 0x11d4, {0xb, 0xca, 0x7, 0x00, 0x80, 0xc7,
0x3c, 0x88, 0x81}} (see footnote 1 at the end of Appendix N)
• ARM: { 0 xE19E3D16,0xBC1 1,0x11E4,{0x9C, 0xAA, 0xC2, 0x05,
0x1D, 0x5D, 0x46, 0xB0}}
NOTE: In addition to the types listed above, there may exist vendor
speciﬁc GUIDs that describe vendor speciﬁc section types.
Platform Memory
• {0xA5BC1114, 0x6F64, 0x4EDE, {0xB8, 0x63, 0x3E, 0x83, 0xED,
0x7C, 0x83, 0xB1}}
PCIe

below:
PCIe
• {0xD995E954, 0xBBC1, 0x430F, {0xAD, 0x91, 0xB4, 0x4D, 0xCB,
0x3C, 0x6F, 0x35}}
Firmware Error Record Reference
• {0x81212A96, 0x09ED, 0x4996, {0x94, 0x71, 0x8D, 0x72, 0x9C,
0x8E, 0x69, 0xED}}
PCI/PCI-X Bus
• {0xC5753963, 0x3B84, 0x4095, {0xBF, 0x78, 0xED, 0xDA, 0xD3,
0xF9, 0xC9, 0xDD}}
PCI Component/Device
• {0xEB5E4685, 0xCA66, 0x4769, {0xB6, 0xA2, 0x26, 0x06, 0x8B,
0x00, 0x13, 0x26}}
DMAr Generic
• {0x5B51FEF7, 0xC79D, 0x4434, {0x8F, 0x1B, 0xAA,
• 0x62, 0xDE, 0x3E, 0x2C, 0x64}}
Intel® VT for Directed I/O speciﬁc DMAr section
• {0x71761D37, 0x32B2, 0x45cd, {0xA7, 0xD0, 0xB0,
• 0xFE 0xDD, 0x93, 0xE8, 0xCF}}
IOMMU speciﬁc DMAr section
• {0x036F84E1, 0x7F37, 0x428c, {0xA7, 0x9E, 0x57,
• 0x5F, 0xDF, 0xAA, 0x84, 0xEC}}
Note 1 CXL Component Events CXL Component Event Log Record in
the CXL Component Events Section
N.2. Format 1993Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
FRU Id 32 16 GUID representing the FRU ID, if it exists, for the section reporting the
error. The default value is zero indicating an invalid FRU ID. System
software can use this to uniquely identify a physical device for tracking
purposes. Association of a GUID to a physical device is done by the
platform in an implemen tation-speciﬁc way (i.e., PCIe Device can lock a
GUID to a PCIe Device ID).
Section Sever-
ity48 4 This ﬁeld indicates the severity associated with the error section. 0 - Re-
coverable (also called non-fatal uncorrected) 1 - Fatal 2 - Corrected 3 -
Informational All other values are reserved. Note that severity of “Infor-
mational” indicates that the section contains extra information that can be
safely ignored by error handling software.
FRU Text 52 20 ASCII string identifying the FRU hardware.
Note:
1. For an IPF processor-speciﬁc error section, the GUID listed is the value from the SAL speciﬁcation. The format
of the data for this section is same as the Processor Device Error Info in the SAL speciﬁcation.
N.2.3 Non-standard Section Body
Information that does not conform to one the standard formats (i.e., those deﬁned in sections 2.4 through 2.9 of this
document) may be recorded in the error record in a non-standard section. The type (e.g. format) of a non-standard
section is identiﬁed by the GUID populated in the Section Descriptor’s Section Type ﬁeld. This allows the information
to be decoded by consumers if the format is externally documented. Examples of information that might be placed in
a non-standard section include the IPF raw SAL error record, Error information recorded in implementation-speciﬁc
PCI conﬁguration space, and IPMI error information recorded in an IPMI SEL.
N.2.4 Processor Error Sections
The processor error sections are divided into two different components as described below:
1. Processor Generic Error Section: This section holds information about processor errors in a generic form and
will be common across all processor architectures. An example or error information provided is the generic
information of cache, tlb, etc., errors.
2. Processor Speciﬁc Error Section: This section consists of error information, which is speciﬁc to a processor
architecture. In addition, certain processor architecture state at the time of error may also be captured in this
section. This section is unique to each processor architecture (Itanium Processor Family, IA32/X64, ARM).
N.2.4.1 Generic Processor Error Section
The Generic Processor Error Section describes processor reported hardware errors for logical processors in the system.
Section Type: {0x9876CCAD, 0x47B4, 0x4bdb, {0xB6, 0x5E, 0x16, 0xF1, 0x93, 0xC4, 0xF3, 0xDB}}
Table N.6: Processor Generic Error Section
Name Byte Offset Byte Length Description
N.2. Format 1994Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.6 – continued from previous page
Validation Bits 0 8
The validation bit mask indicates whether or not each of the
following ﬁelds is valid in this section.
Bit 0 - Processor Type Valid
Bit 1 - Processor ISA Valid
Bit 2 - Processor Error Type Valid
Bit 3 - Operation Valid
Bit 4 - Flags Valid
Bit 5 - Level Valid
Bit 6 - CPU Version Valid
Bit 7 - CPU Brand Info Valid
Bit 8 - CPU Id Valid
Bit 9 - Target Address Valid
Bit 10 - Requester Identiﬁer Valid
Bit 11 - Responder Identiﬁer Valid
Bit 12 - Instruction IP Valid
All other bits are reserved and must be zero.
Processor
Type8 1
Identiﬁes the type of the processor architecture.
0: IA32/X64
1: IA64
2: ARM
All other values reserved.
Processor ISA 9 1
Identiﬁes the type of the instruction set executing when the
error occurred:
0: IA32
1: IA64
2: X64
3: ARM A32/T32
4: ARM A64
Processor Er-
ror Type10 1
Indicates the type of error that occurred:
0x00: Unknown
0x01: Cache Error
0x02: TLB Error
0x04: Bus Error
0x08: Micro-Architectural Error
N.2. Format 1995Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Operation 11 1
Indicates the type of operation:
0: Unknown or generic
1: Data Read
2: Data Write
3: Instruction Execution
Flags 12 1
Indicates additional information about the error:
Bit 0: Restartable - If 1, program execution can be restarted
reliably after the error.
Bit 1: Precise IP - If 1, the instruction IP captured is directly
associated with the error.
Bit 2: Overﬂow - If 1, a machine check overﬂow occurred
(a second error occurred while the results of a previous
error were still in the error reporting resources).
Bit 3: Corrected - If 1, the error was corrected by hardware
and/or ﬁrmware.
Level 13 1 Level of the structure where the error occurred, with 0 being
the lowest level of cache.
Reserved 14 2 Must be zero.
CPU Version
Info16 8
This ﬁeld represents the CPU Version Information and
returns Family, Model, and stepping information (e.g. As
provided by CPUID instruction with EAX=1 input with
output values from EAX on the IA32/X64 processor or as
provided by CPUID Register 3 register - Version
Information on IA64 processors).
On ARM processors, this ﬁeld will be provided as:
Bits 127:64 - Reserved and must be zero
Bits 63:0 - MIDR_EL1 of the processor
CPU Brand
String24 128
This ﬁeld represents the null-terminated ASCII Processor
Brand String (e.g. As provided by the CPUID instruction
with EAX=0x80000002 and ECX=0x80000003 for
IA32/X64 processors or the return from
PAL_BRAND_INFO for IA64 processors).
This ﬁeld is optional for ARM processors.
N.2. Format 1996Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Processor ID 152 8
This value uniquely identiﬁes the logical processor (e.g. As
programmed into the local APIC ID register on IA32/X64
processors or programmed into the LID register on IA64
processors).
On ARM processors, this ﬁeld will be provided as
programmed in the architected MPIDR_EL1.
Target Address 160 8 Identiﬁes the target address associated with the error.
Requestor
Identiﬁer168 8 Identiﬁes the requestor associated with the error.
Responder
Identiﬁer176 8 Identiﬁes the responder associated with the error.
Instruction IP 184 8 Identiﬁes the instruction pointer when the error occurred.
N.2.4.2 IA32/X64 Processor Error Section
Type:{0xDC3EA0B0, 0xA144, 0x4797, {0xB9, 0x5B, 0x53, 0xFA, 0x24, 0x2B, 0x6E, 0x1D}}
Table N.7: Processor Error Record
Bits0 8
The validation bit mask indicates each of the following ﬁeld is valid in
this section:
Bit0 - LocalAPIC_ID Valid
Bit1 - CPUID Info Valid
Bits 2-7 - Number of Processor Error Information Structure
(PRO C_ERR_INFO_NUM)
Bit 8- 13 Number of Processor Context Information Structure
(PROC_CO NTEXT_INFO_NUM)
Bits 14-63 - Reserved
Local
APIC_ID8 8 This is the processor APIC ID programmed into the APIC ID registers.
CPUID Info 16 48 This ﬁeld represents the CPU ID structure of 48 bytes and returns Model,
Family, and stepping information as provided by the CPUID instruction
with EAX=1 input and output values from EAX, EBX, ECX, and EDX
null extended to 64-bits.
ror Info64 Nx64 This is a variable-length structure consisting of N different 64 byte
structures, each representing a single processor error information struc-
ture. The value of N ranges from 0-63 and is as indicated by PRO
C_ERR_INFO_NUM.
N.2. Format 1997Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.7 – continued from previous page
Processor
Context64+Nx64 NxX This is a variable size ﬁeld providing the information for the pro-
cessor context state such as MC Bank MSRs and general registers.
The value of N ranges from 0-63 and is as indicated by PROC_CO
NTEXT_INFO_NUM. Each processor context information structure is
padded with zeros if the size is not a multiple of 16 bytes.

Processor
N.2.4.2.1 IA32/X64 Processor Error Information Structure
As described above, the processor error section contains a collection of structures called Processor Error Information
Structures that contain processor structure speciﬁc error information. This section details the layout of the Processor
Error Information Structure and the detailed check information which is contained within.
Table N.8: IA32/X64 Processor Error Information Structure
Off-
setByte
Error Struc-
ture Type0 16
This ﬁeld holds a pre-assigned GUID indicating the type of Processor Error
Information structure. The following Processor Error Information Structure Types
have pre-deﬁned GUID.
• Cache Error Information (Cache Check)
• TLB Error Information (TLB Check)
• Bus Error Information (Bus Check)
• Micro-architecture Speciﬁc Error Information (MS Check)
Bits16 8
Bit 0 - Check Info Valid
Bit 1 - Target Address Identiﬁer Valid
Bit 2 - Requestor Identiﬁer Valid
Bit 3 - Responder Identiﬁer Valid
Bit 4 - Instruction Pointer Valid
Bits 5-63 - Reserved
Check Infor-
mation24 8 Str uctureErrorType speciﬁc error check structure.
Target Identi-
ﬁer32 8 Identiﬁes the target associated with the error.
Requestor
Identiﬁer40 8 Identiﬁes the requestor associated with the error.
Responder
Identiﬁer48 8 Identiﬁes the responder associated with the error.
Instruction
Pointer56 8 Identiﬁes the instruction executing when the error occurred.
N.2. Format 1998Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.4.2.2 IA32/X64 Cache Check Structure
Type:{0xA55701F5, 0xE3EF, 0x43de, {0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C}}
Table N.9: IA32/X64 Cache Check Structure
Field Name Bits Description
ValidationBits 15:0
Indicates which ﬁelds in the Cache Check structure are valid:
Bit 0 - Transaction Type Valid
Bit 1 - Operation Valid
Bit 2 - Level Valid
Bit 3 - Processor Context Corrupt Valid
Bit 4 - Uncorrected Valid
Bit 5 - Precise IP Valid
Bit 6 - Restartable Valid
Bit 7- Overﬂow Valid
Bits 8 - 15 Reserved
TransactionType 17:16
Type of cache error:
0 - Instruction
1 - Data Access
2 - Generic
All other values are reserved
Operation 21:18
Type of cache operation that caused the error:
0 - generic error (type of error cannot be determined)
1 - generic read (type of instruction or data request cannot be determined)
2 - generic write (type of instruction or data request cannot be determined)
3 - data read
4 - data write
5 - instruction fetch
6 - prefetch
7 - eviction
8 - snoop
Level 24:22 Cache Level
Processor Con-
text Corrupt25
This ﬁeld indicates that the processor context might have been corrupted.
0 - Processor context not corrupted
1 - Processor context corrupted
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Table N.9 – continued from previous page
Uncorrected 26
This ﬁeld indicates whether the error was corrected or uncorrected:
0: Corrected
1: Uncorrected
Precise IP 27 This ﬁeld indicates that the instruction pointer pushed onto the stack is directly asso-
ciated with the error
Restartable IP 28 This ﬁeld indicates that program execution can be restarted reliably at the instruction
pointer pushed onto the stack
Overﬂow 29
This ﬁeld indicates an error overﬂow occurred
0 - Overﬂow not occurred
1 - Overﬂow occurred
63:30 Reserved
N.2.4.2.3 IA32/X64 TLB Check Structure
Type:{0xFC06B535, 0x5E1F, 0x4562, {0x9F, 0x25, 0x0A, 0x3B, 0x9A, 0xDB, 0x63, 0xC3}}
Table N.10: IA32/X64 TLB Check Structure
Validation Bits 15:0
Indicate which ﬁelds in the Cache_Check structure are valid
Bit 6 - Restartable IP Valid
Bit 7 - Overﬂow Valid
Bit 8 - 15 Reserved
Transaction
Type17:16
Type of TLB error
2 - Generic
N.2. Format 2000Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.10 – continued from previous page
Type of TLB access operation that caused the machine check:
Level 24:22 TLB Level
PreciseIP 27 This ﬁeld indicates that the instruction pointer pushed onto the stack is directly
Restartable IP 28 This ﬁeld indicates the program execution can be restarted reliably at the instruction
pointer pushed onto the stack.
Overﬂow 29
N.2.4.2.4 IA32/X64 Bus Check Structure
Type:{0x1CF3F8B3, 0xC5B1, 0x49a2, {0xAA, 0x59, 0x5E, 0xEF, 0x92, 0xFF, 0xA6, 0x3C}}
Table N.11: IA32/X64 Bus Check Structure
N.2. Format 2001Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.11 – continued from previous page
Indicate which ﬁelds in the Bus_Check structure are valid
Bit 8 - Participation Type Valid
Bit 9 - Time Out Valid
Bit 10 - Address Space Valid
Bit 11 - 15 Reserved
Type17:16
Type of Bus error
2 - Generic
Type of bus access operation that caused the machine check:
6 - prefetch All other values are reserved.
Level 24:22 Indicate which level of the bus hierarchy the error occurred in.
PreciseIP 27 This ﬁeld indicates that the instruction pointer pushed onto the stack is directly asso-
ciated with the error.
N.2. Format 2002Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Overﬂow 29
Participation
Type31:30
Type of Participation
0 - Local Processor originated request
1 - Local processor Responded to request
2 - Local processor Observed
3 - Generic
Time Out 32 This ﬁeld indicates that the request timed out.
Address Space 34:33
0 - Memory Access
1 - Reserved
2 - I/O
3 - Other Transaction
63:35 Reserved
N.2.4.2.5 IA32/X64 MS Check Field Description
Type: {0x48AB7F57, 0xDC34, 0x4f6c, {0xA7, 0xD3, 0xB0, 0xB5, 0xB0, 0xA7, 0x43, 0x14}}
Table N.12: IA32/X64 MS Check Field Description
Bit 0 - Error Type Valid
Bit 1 - Processor Context Corrupt Valid
Bit 2 - Uncorrected Valid
Bit 3 - Precise IP Valid
Bit 4 - Restartable IP Valid
Bit 5 - Overﬂow Valid
Bit 6 - 15 Reserved
Error Type 18:16
Identiﬁes the operation that caused the error:
0 - No Error
1 - Unclassiﬁed
2 - Microcode ROM Parity Error
3 - External Error
4 - FRC Error
5 - Internal Unclassiﬁed
All other value are processor speciﬁc.
N.2. Format 2003Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.12 – continued from previous page
Processor Context Cor-
rupt19
Uncorrected 20
Precise IP 21 This ﬁeld indicates that the instruction pointer pushed onto the stack is directly
Restartable IP 22 This ﬁeld indicates the program execution can be restarted reliably at the in-
struction pointer pushed onto the stack.
Overﬂow 23

0 - No Error
rupt19
Overﬂow 23
63:24 Reserved
N.2.4.2.6 IA32/X64 Processor Context Information Structure
As described above, the processor error section contains a collection of structures called Processor Context Information
that contain processor context state speciﬁc to the IA32/X64 processor architecture. This section details the layout of
the Processor Context Information Structure and the detailed processor context type information.
Table N.13: IA32/X64 Processor Context Information
Register Context
Type0 2 bytes
Value indicating the type of processor context state being reported:
0 - Unclassiﬁed Data
1 - MSR Registers (Machine Check and other MSRs)
2 - 32-bit Mode Execution Context
3 - 64-bit Mode Execution Context
4 - FXSA VE Context
5 - 32-bit Mode Debug Registers (DR0-DR7)
6 - 64-bit Mode Debug Registers (DR0-DR7)
7 - Memory Mapped Registers
Others - Reserved
Register Array
Size2 2 bytes Represents the total size of the array for the Data Type being reported
in bytes.
MSR Address 4 4 bytes This ﬁeld contains the starting MSR address for the type 1 register
context.
MM Register Ad-
dress8 8 bytes This ﬁeld contains the starting memory address for the type 7 register
context.
N.2. Format 2004Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.13 – continued from previous page
Register Array 16 N bytes This ﬁeld will provide the contents of the actual registers or raw data.
The number of Registers or size of the raw data reported is determined
by (Array Size / 8) or otherwise speciﬁed by the context structure type
The Table below shows the register context type 2, 32-bit mode execution context.
Table N.14: IA32 Register State
Offset Length Field
0 4 bytes EAX
4 4 bytes EBX
8 4 bytes ECX
12 4 bytes EDX
16 4 bytes ESI
20 4 bytes EDI
24 4 bytes EBP
28 4 bytes ESP
32 2 bytes CS
34 2 bytes DS
36 2 bytes SS
38 2 bytes ES
40 2 bytes FS
42 2 bytes GS
44 4 bytes EFLAGS
48 4 bytes EIP
52 4 bytes CR0
56 4 bytes CR1
60 4 bytes CR2
64 4 bytes CR3
68 4 bytes CR4
72 8 bytes GDTR
80 8 bytes IDTR
88 2 bytes LDTR
90 2 bytes TR
See the Table below for the register context type 3, 64-bit mode execution context.
Table N.15: X64 Register State
0 8 bytes RAX
8 8 bytes RBX
16 8 bytes RCX
24 8 bytes RDX
32 8 bytes RSI
40 8 bytes RDI
48 8 bytes RBP
56 8 bytes RSP
64 8 bytes R8
72 8 bytes R9
N.2. Format 2005Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.15 – continued from previous page
80 8 bytes R10
88 8 bytes R11
96 8 bytes R12
104 8 bytes R13
112 8 bytes R14
120 8 bytes R15
128 2 bytes CS
130 2 bytes DS
132 2 bytes SS
134 2 bytes ES
136 2 bytes FS
138 2 bytes GS
140 4 bytes Reserved
144 8 bytes RFLAGS
152 8 bytes EIP
160 8 bytes CR0
168 8 bytes CR1
176 8 bytes CR2
184 8 bytes CR3
192 8 bytes CR4
200 8 bytes CR8
208 16 bytes GDTR
224 16 bytes IDTR
240 2 bytes LDTR
242 2 bytes TR
N.2.4.3 IA64 Processor Error Section
Refer to the Intel Itanium Processor Family System Abstraction Layer speciﬁcation for ﬁnding the IA64 speciﬁc error
section body deﬁnition.
N.2.4.4 ARM Processor Error Section
Type: {0xE19E3D16, 0xBC11, 0x11E4, {0x9C, 0xAA, 0xC2, 0x05, 0x1D, 0x5D, 0x46, 0xB0}}
The ARM Processor Error Section may contain multiple instances of error information structures associated to a single
error event. An error may propagate to other hardware components (e.g. poisoned data) or cause subsequent errors,
all of which may be captured in a single ARM processor error section. The processor context information describes
the observed state of the processor at the point of error detection.
It is optional for vendors to capture processor context information. The speciﬁcs of capturing processor context is
vendor speciﬁc. Vendors must take care when handling errors that have originated whilst a processor was executing in
a secure exception level. In those cases providing processor context information to non-secure agents could be unsafe
and lead to security attacks.
Table N.16: ARM Processor Error Section
N.2. Format 2006Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.16 – continued from previous page
Validation Bit 0 4
Bit 0 - MPIDR Valid
Bit 1 - Error afﬁnity level Valid
Bit 2 - Running State
Bit 3 - Vendor Speciﬁc Info Valid
ERR_INFO_NUM 4 2 ERR_INFO_NUM is the number of Processor Error Information
Structures (must be 1 or greater)
CONTEXT_INFO_NUM 6 2 C ONTEXT_INFO_NUM is the number of Context Information
Structures
Section Length 8 4 This describes the total size of the ARM processor error section
Error afﬁnity level 12 1
For errors that can be attributed to a speciﬁc afﬁnity level, this ﬁeld
deﬁnes the afﬁnity level at which the error was produced, detected,
and/or consumed. This is a value between 0 and 3. All other values
(4-255) are reserved
For example, a vendor may choose to deﬁne afﬁnity levels as
follows:
Level 0: errors that can be precisely attributed to a speciﬁc CPU
(e.g. due to a synchronous external abort)
Level 1: Cache parity and/or ECC errors detected at cache of
afﬁnity level 1 (e.g. only attributed to higher level cache due to
prefetching and/or error propagation)
NOTE : Detailed meanings and groupings of afﬁnity level are chip
and/or platform speciﬁc. The afﬁnity level described here must be
consistent with the platform deﬁnitions used MPIDR. For
cache/TLB errors, the cache/TLB level is provided by the
cache/TLB error structure, which may differ from afﬁnity level.
Reserved 13 3 Must be zero
MPIDR_EL1 16 8 This ﬁeld is valid for “attributable errors” that can be attributed to a
speciﬁc CPU, cache, or cluster. This is the processor’s unique ID in
MIDR_EL1 24 8 This ﬁeld provides identiﬁcation information of the chip, including
an implementer code for the device and a device ID number
Running State 32 4 Bit 0 - Processor running. If this bit is set, “PSCI State” ﬁeld must
be zero. All other bits are reserved and must be zero.
PSCI State 36 4 This ﬁeld provides PSCI state of the processor, as deﬁned in ARM
PSCI document. This ﬁeld is valid when bit 32 of “Running State”
ﬁeld is zero.
Processor Error In-
formation Structure40 Nx32 This is a variable-length structure consisting of N different 32 byte
structures (reference the Table below, ARM Processor Error Infor-
mation Structure ) , each representing a single processor error in-
formation structure. The value of N ranges from 1-255 and is as
indicated by ERR_INFO_NUM ﬁeld in this table.
N.2. Format 2007Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Processor Context 40 +
Nx32MxP This is a variable size ﬁeld consisting of M different P byte struc-
tures providing the information for the processor context state such
as general purpose registers (GPRs) and special purpose registers
(SPRs) as deﬁned in Table 266 or 267 (depending on the context
type). The value of M ranges from 0-65536 and is indicated by the
C ONTEXT_INFO_NUM ﬁeld in this table. Each processor con-
text information structure is padded with zeros if the size is not a
multiple of 16 bytes. The value of P is a variable length deﬁned by
the processor context structure per Table 266 and 267.
Vendor Speciﬁc Er-
ror Info40 +
Nx32 +
MxPvendor
speciﬁcThis is an optional variable ﬁeld provided by vendors that prefer to
provide additional details.
N.2.4.4.1 ARM Processor Error Information
As described above, the processor error section contains a collection of Processor Error Information structures that
contain processor speciﬁc error information. This section details the layout of the Processor Error Information structure
and the detailed information which is contained within.
Table N.17: ARM Processor Error Information Structure
Version 0 1 0 (revision of this table)
Length 1 1 32 (length in bytes)
Validation Bit 2 2
The validation bit mask indicates whether or not each of the following
ﬁelds is valid in this section.
Bit 0 - Multiple Error (Error Count) Valid
Bit 1 - Flags Valid
Bit 2 - Error Information Valid
Bit 3 - Virtual Fault Address
Bit 4 - Physical Fault Address
Type 4 1
Bit 1 - Cache Error
Bit 2 - TLB Error
Bit 3 - Bus Error
Bit 4 - Micro-architectural Error
N.2. Format 2008Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.17 – continued from previous page
Multiple Error
(Error Count)5 2

Type 4 1
This ﬁeld indicates whether multiple errors have occurred. In the case of
multiple error with a valid count, this ﬁeld will specify the error count.
The value of this ﬁeld is deﬁned as follows:
0: Single Error
1: Multiple Errors
2-65535: Error Count (if known)
Flags 7 1
This ﬁeld indicates ﬂags that describe the error attributes. The value of
this ﬁeld is deﬁned as follows:
Bit 0 - First error captured
Bit 1 - Last error captured
Bit 2 - Propagated
Bit 3 - Overﬂow
All other bits are reserved and must be zero
Note : The overﬂow bit indicates when ﬁrmware/hardware error buffers
experience an overﬂow, so it is possible that some error information has
been lost.
Error Infor-
mation8 8 The error information structure is speciﬁc to each error type (described in
tables below)
Virtual Fault
Address16 8 If known, this ﬁeld indicates a virtual fault address associated with the
error (e.g. when an error occurs in virtually indexed cache)
Physical Fault
Address24 8 If known, this ﬁeld indicates a physical fault address associated with the
error
See the 4 Tables directly below for more error information: Arm Cache Error Structure ,ARM TLB Error Structure ,
ARM Bus Error Structure , and ARM Processor Error Context Information Header Structure .
Table N.18: ARM Cache Error Structure
Name Bits Description
Validation Bit 15:0
Bit 4 - Corrected Valid
Bit 5 - Precise PC Valid
Bit 6 - Restartable PC Valid
N.2. Format 2009Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.18 – continued from previous page
Transaction Type 17:16
2 - Generic
8 - snooping (the processor described in this record initiated a cache snoop that
resulted in an error)
9 - snooped (The processor described in this record raised a cache error caused
by another processor or device snooping into its cache)
10 - management
Level 24:22 Cache level
Processor Context
Corrupt25
Corrected 26
1: Corrected
0: Uncorrected
Precise PC 27 This ﬁeld indicates that the program counter that is directly associated with the
error
Restartable PC 28 This ﬁeld indicates that program execution can be restarted reliably at the PC
Reserved 63:29 Must be zero
Table N.19: ARM TLB Error Structure
Validation Bit 15:0 Indicates which ﬁelds in the TLB error structure are valid: | Bit 0 - Transaction
Type Valid | Bit 1 - Operation Valid | Bit 2 - Level Valid | Bit 3 - Processor
Context Corrupt Valid | Bit 4 - Corrected Valid | Bit 5 - Precise PC Valid | Bit 6
- Restartable PC Valid | All other bits are reserved and must be zero.
N.2. Format 2010Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.19 – continued from previous page
Transaction Type 17:16 Type of TLB error: 0 - Instruction 1 - Data Access 2 - Generic All other values
are reserved
Type of TLB operation that caused the error:
7 - local management operation (the processor described in this record initiated
a TLB management operation that resulted in an error)
8 - external management operation (the processor described in this record
raised a TLB error caused by another processor or device broadcasting TLB
operations)
Level 24:22 TLB level
Corrupt25
Corrected 26 This ﬁeld indicates whether the error was corrected or uncorrected: 1: Corrected
error
Reserved 63:29 Must be zero.
Table N.20: ARM Bus Error Structure
N.2. Format 2011Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.20 – continued from previous page
Indicates which ﬁelds in the Bus error structure are valid: Bit
0 - Transaction Type Valid
Bit 7 - Participation Type Valid
Bit 8 - Time Out Valid
Bit 9 - Address Space Valid
Bit 10 - Memory Attributes Valid
Bit 11 - Access Mode valid
Type of bus error:
2 - Generic
Type of bus operation that caused the error:
Level 24:22 Afﬁnity level at which the bus error occurred
Corrupt25
error
N.2. Format 2012Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Participation Type 30:29
3 - Generic
The usage of this ﬁeld depends on the vendor, but the examples below provide
some guidance on how this ﬁeld is to be used:
If bus error occurs on an LDR instruction, the local processor originated the
request.
If the bus error occurs due to a snoop operation, local processor responded to
the request
If a bus error occurs due to cache prefetching and an SEI was sent to a
particular CPU to notify this bus error has occurred, then the local processor
only observed the error.
Time Out 31 This ﬁeld indicates that the request timed out.
Address Space 33:32
0 - External Memory Access (e.g. DDR)
1 - Internal Memory Access (e.g. internal chip ROM)
3 - Device Memory Access
Memory Access At-
tributes42:34 Memory attribute as described in the ARM ARM speciﬁcation.
Access Mode 43
Indicates whether the access was a secure or normal bus request
0 - secure
1 - normal
Note : A platform may choose to hide some or all of the error information for
errors that are consumed/detected in the secure context.
Reserved 63:44 Must be zero.
N.2.4.4.1.1 ARM Vendor Speciﬁc Micro-Architecture ErrorStructure
This is a vendor speciﬁc structure. Please refer to your hardware vendor documentation for the format of this structure.
N.2. Format 2013Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.4.4.2 ARM Processor Context Information
As described above, the processor error section contains a collection of structures called Processor Context Informa-
tion. These provide processor context state speciﬁc to the ARM processor architecture. This section details the layout
of the Processor Error Context Information Header Structure ( See Table N-21, ARM Processor Error Context Infor-
mation HeaderStructure ) and the detailed processor context type information structures ( See Table N-21 through
Table N-30).
Care must be taken when reporting context information structures. The amount of context reported depends on the
agent that is going to observe the data. The following are recommended guidelines:

1. If the error happens whilst the processor is in the secure world, EL3, Secure EL1 or secure EL0, context infor-
mation can contain sensitive data, and should not be exposed to unauthorized parties.
2. If the error information is being provided to a software agent running at EL2, then the context information
should only include any registers visible in EL2, e.g. GPR, EL1 and EL2 registers.
3. If the error information is being provided to a software agent running at EL1, then the context information
should only include any registers visible in EL1, e.g. GPR, EL1 and registers.
For context information on processor running in AArch64 mode, even though some registers are deﬁned as 4 bytes in
length, following tables provide 8 bytes space to account for possible future expansion.
Table N.21: ARM Processor Error Context Information HeaderStructure
Name Byte
Off-
setByte
Version 0 2 0 (revision of this table)
Register Con-
text Type2 2
0 — AArch32 GPRs (General Purpose Registers).
1 — AArch32 EL1 context registers
2 — AArch32 EL2 context registers
3 — Aarch32 secure context registers
4 — AArch64 GPRs
5 — AArch64 EL1 context registers
6 — Aarch64 EL2 context registers
7 — AArch64 EL3 context registers
8 — Misc. System Register Structure
Size4 4 Represents the total size of the array for the Data Type being reported in bytes.
Register Array 8 N This ﬁeld will provide the contents of the actual registers or raw data. The
contents of the array depends on the Type, with the structures described in
Tables 266 - 274.
N.2. Format 2014Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.22: ARMv8 AArch32 GPRs (Type 0)
Byte Offset Byte Length Field
0 4 R0
4 4 R1
8 4 R2
12 4 R3
16 4 R4
20 4 R5
24 4 R6
28 4 R7
32 4 R8
36 4 R9
40 4 R10
44 4 R11
48 4 R12
52 4 R13 (SP)
56 4 R14 (LR)
60 4 R15 (PC)
Table N.23: ARM AArch32 EL1 Context System Registers (Type 1)
0 4 DFAR
4 4 DFSR
8 4 IFAR
12 4 ISR
16 4 MAIR0
20 4 MAIR1
24 4 MIDR
28 4 MPIDR
32 4 NMRR
36 4 PRRR
40 4 SCTLR (NS)
44 4 SPSR
48 4 SPSR_abt
52 4 SPSR_ﬁq
56 4 SPSR_irq
60 4 SPSR_svc
64 4 SPSR_und
68 4 TPIDRPRW
72 4 TPIDRURO
76 4 TPIDRURW
80 4 TTBCR
84 4 TTBR0
88 4 TTBR1
92 4 DACR
N.2. Format 2015Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.24: ARM AArch32 EL2 Context System Registers (Type 2)
0 4 ELR_hyp
4 4 HAMAIR0
8 4 HAMAIR1
12 4 HCR
16 4 HCR2
20 4 HDFAR
24 4 HIFAR
28 4 HPFAR
32 4 HSR
36 4 HTCR
40 4 HTPIDR
44 4 HTTBR
48 4 SPSR_hyp
52 4 VTCR
56 4 VTTBR
60 4 DACR32_EL2
Table N.25: ARM AArch32 secure Context System Registers (Type3)
0 4 SCTLR (S)
4 4 SPSR_mon
Table N.26: ARMv8 AArch64 GPRs (Type 4)
0 8 X0
8 8 X1
16 8 X2
24 8 X3
32 8 X4
40 8 X5
48 8 X6
56 8 X7
64 8 X8
72 8 X9
80 8 X10
88 8 X11
96 8 X12
104 8 X13
112 8 X14
120 8 X15
128 8 X16
136 8 X17
144 8 X18
152 8 X19
160 8 X20
168 8 X21
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Table N.26 – continued from previous page
176 8 X22
184 8 X23
192 8 X24
200 8 X25
208 8 X26
216 8 X27
224 8 X28
232 8 X29
240 8 X30
248 8 SP
Table N.27: ARM AArch64 EL1 Context System Registers (Type 5)
0 8 ELR_EL1
8 8 ESR_EL1
16 8 FAR_EL1
24 8 ISR_EL1
32 8 MAIR_EL1
40 8 MIDR_EL1
48 8 MPIDR_EL1
56 8 SCTLR_EL1
64 8 SP_EL0
72 8 SP_EL1
80 8 SPSR_EL1
88 8 TCR_EL1
96 8 TPIDR_EL0
104 8 TPIDR_EL1
112 8 TPIDRRO_EL0
120 8 TTBR0_EL1
128 8 TTBR1_EL1
Table N.28: ARM AArch64 EL2 Context System Registers (Type 6)
0 8 ELR_EL2
8 8 ESR_EL2
16 8 FAR_EL2
24 8 HACR_EL2
32 8 HCR_EL2
40 8 HPFAR_EL2
48 8 MAIR_EL2
56 8 SCTLR_EL2
64 8 SP_EL2
72 8 SPSR_EL2
80 8 TCR_EL2
88 8 TPIDR_EL2
96 8 TTBR0_EL2
104 8 VTCR_EL2
112 8 VTTBR_EL2
N.2. Format 2017Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.29: ARM AArch64 EL3 Context System Registers (Type 7)
0 8 ELR_EL3
8 8 ESR_EL3
16 8 FAR_EL3
24 8 MAIR_EL3
32 8 SCTLR_EL3
40 8 SP_EL3
48 8 SPSR_EL3
56 8 TCR_EL3
64 8 TPIDR_EL3
72 8 TTBR0_EL3
The following structure (Table 275) describes additional AArch64/AArch32 miscellaneous system registers captured
from the perspective of the processor that took the hardware error exception. Each register array entry will be per
the following table. The number of register entries present in the register array is based on the register array size (i.e.
N/10).
Table N.30: ARM Misc. Context System Register (Type 8) - SingleReg-
ister Entry
Name Byte
MRS encod-
ing0 2
This ﬁeld deﬁnes MRS instruction encoding.
Bit 0:2 – Op2
Bit 3:6 - CRm
Bit 7:10 - CRn
Bit 11:13 - Op1
Bit 14 - O0
Value 2 8 Value read from system register
N.2.5 Memory Error Section
Type: {0xA5BC1114, 0x6F64, 0x4EDE, {0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, 0x83, 0xB1}}
Table N.31: Memory Error Record
N.2. Format 2018Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.31 – continued from previous page
Bits0 8
Indicates which ﬁelds in the memory error record are valid.
Bit 0 - Error Status Valid
Bit 1 - Physical Address Valid
Bit 2 - Physical Address Mask Valid
Bit 3 - Node Valid
Bit 4 - Card Valid
Bit 5 - Module Valid
Bit 6 - Bank Valid (When Bank is addressed via group/address, refer to Bit
19 and 20)
Bit 7 - Device Valid
Bit 8 - Row Valid
1 - the Row ﬁeld at Offset 42 contains row number (15:0) and row
number (17:16) are 00b
0 - the Row ﬁeld at Offset 42 is not used, or is deﬁned by
Bit 18 (Extended Row Bit 16 and 17 Valid).
Bit 9 - Column Valid
Bit 10 - Bit Position Valid
Bit 11 - Platform Requestor Id Valid
Bit 12 - Platform Responder Id Valid
Bit 13 - Memory Platform Target Valid
Bit 14 - Memory Error Type Valid
Bit 15 - Rank Number Valid
Bit 16 - Card Handle Valid
Bit 17 - Module Handle Valid
Bit 18 - Extended Row Bit 16 and 17 Valid (refer to Byte Offset 42 and 73
below)
1 - the Row ﬁeld at Offset 42 contains row number (15:0) and the
Extended ﬁeld at Offset 73 contains row number (17:16)
0 - the Extended ﬁeld at Offset 73 and the Row ﬁeld at Offset 42 are
not used, or the Rowﬁeld at Offset 42 is deﬁned by Bit 8 (Row Valid).
When this bit is set to 1, Bit 8 (Row Valid) must be set to 0.
Bit 19 - Bank Group Valid
Bit 20 - Bank Address Valid
Bit 21 - Chip Identiﬁcation Valid
Bit 22-63 Reserved
Error
Status8 8 Memory error status information. See See Error Status for error status details.
Physical
Address16 8 The physical address at which the memory error occurred.
Physical
Address
Mask24 8 Deﬁnes the valid address bits in the Physical Address ﬁeld. The mask spec-
iﬁes the granularity of the physical address which is dependent on the hw/
implementation factors such as interleaving.
Node 32 2 In a multi-node system, this value identiﬁes the node containing the memory
in error.
Card 34 2 The card number of the memory error location.
N.2. Format 2019Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Module 36 2 The module or rank number of the memory error location. (NODE, CARD,
and MODULE should provide the information necessary to identify the failing
FRU).
Bank 38 2
The bank number of the memory associated with the error.
When Bank is addressed via group/address
Bit 7:0 - Bank Address
Bit 15:8 - Bank Group
Device 40 2 The device number of the memory associated with the error.
Row 42 2 First 16 bits (15:0) of the row number of the memory error location. This ﬁeld
is valid if either “Row Valid” or “Extended Row Bit 16 and 17” Validation Bits
at Offset 0 is set to 1..
Column 44 2 The column number of the memory error location.
Bit Posi-
tion46 2 The bit position at which the memory error occurred.
Requestor
ID48 8 Hardware address of the device that initiated the transaction that took the er-
ror.
Responder
ID56 8 Hardware address of the device that responded to the transaction.
Target
ID64 8 Hardware address of the intended target of the transaction.
Memory
Error
Type72 1
Identiﬁes the type of error that occurred:
0 - Unknown
1 - No error
2 - Single-bit ECC
3 - Multi-bit ECC
4 - Single-symbol ChipKill ECC
5 - Multi-symbol ChipKill ECC
6 - Master abort
7 - Target abort
8 - Parity Error
9 - Watchdog timeout
10 - Invalid address
11 - Mirror Broken
12 - Memory Sparing
13 - Scrub corrected error
14 - Scrub uncorrected error
15 - Physical Memory Map-out event
N.2. Format 2020Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Extended 73 1
Bit 0 - Bit 16 of the row number of the memory error location.

Bit Posi-
Requestor
ror.
Responder
Target
Memory
Error
Type72 1
0 - Unknown
1 - No error
- This ﬁeld is valid if “Extended Row Bit 16 and 17” Validation Bits at Offset
0 is set to 1.
Bit 1 - Bit 17 of the row number of the memory error location.
Bit 4:2 - Reserved
Bit 7:5 - Chip Identiﬁcation.
Rank
Number74 2 The Rank number of the memory error location.
Card
Handle76 2 If bit 16 in Validation Bits is 1, this ﬁeld contains the SMBIOS handle for the
Type 16 Memory Array Structure that represents the memory card.
Module
Handle78 2 If bit 17 in Validation Bits is 1, this ﬁeld contains the SMBIOS handle for the
Type 17 Memory Device Structure that represents the Memory Module.
N.2.6 Memory Error Section 2
Type: { 0x61EC04FC, 0x48E6, 0xD813, { 0x25, 0xC9, 0x8D, 0xAA, 0x44, 0x75, 0x0B, 0x12 } };
Table N.32: Memory Error Record 2
N.2. Format 2021Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.32 – continued from previous page
Bits0 8
Bit 6 - Bank Valid
(When Bank is addressed via group/address, refer to Bit 20 and 21)
Bit 10 - Rank Valid
Bit 11 - Bit Position Valid
Bit 12 - Chip Identiﬁcation Valid
Bit 13 - Memory Error Type Valid
Bit 14 - Status Valid
Bit 15 - Requestor ID Valid
Bit 16 - Responder ID Valid
Bit 17 - Target ID Valid
Bit 18 - Card Handle Valid
Bit 19 - Module Handle Valid
Bit 20 - Bank Group Valid
Bit 21 - Bank Address Valid
Error Status 8 8 Memory error status information. See See Error Status for error status
details.
Physical Ad-
dress16 8 The physical address at which the memory error occurred.
dress Mask24 8 Deﬁnes the valid address bits in the Physical Address ﬁeld. The mask
speciﬁes the granularity of the physical address which is dependent on
the hardware implementation factors such as interleaving.
Node 32 2 In a multi-node system, this value identiﬁes the node containing the mem-
ory in error.
Module 36 2 The module number of the memory error location. (NODE, CARD, and
MODULE should provide the information necessary to identify the failing
FRU).
Bank 38 2 The bank number of the memory associated with the error. When Bank
is addressed via group/address (e.g., DDR4) Bit 7:0 - Bank Address Bit
15:8 - Bank Group
Device 40 4 The device number of the memory associated with the error.
Row 44 4 The row number of the memory error location.
Column 48 4 The column number of the memory error location.
Rank 52 4 The rank number of the memory error location.
Bit Position 56 4 The bit position at which the memory error occurred.
N.2. Format 2022Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Chip Identiﬁ-
cation60 1 The Chip Identiﬁcation. This is an encoded ﬁeld used to address the die
in 3DS packages.
Memory Error
Type61 1
0 - Unknown
1 - No error
16 - 255 Reserved
Status 62 1
Bit 0:
If set to 0, the memory error is corrected; if set to 1, the memory error is
uncorrected
Bit 1-7: Reserved values are 0
Reserved 63 1 Reserved values are 0
Requestor ID 64 8 Hardware address of the device that initiated the transaction that took the
error.
Responder ID 72 8 Hardware address of the device that responded to the transaction.
Target ID 80 8 Hardware address of the intended target of the transaction.
Card Handle 88 4 This ﬁeld contains the SMBIOS handle for the Type 16 Memory Array
Structure that represents the memory card.
Module Han-
dle92 4 This ﬁeld contains the SMBIOS handle for the Type 17 Memory Device
Structure that represents the Memory Module.
N.2. Format 2023Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.7 PCI Express Error Section
Type: {0xD995E954, 0xBBC1, 0x430F, {0xAD, 0x91, 0xB4, 0x4D, 0xCB, 0x3C, 0x6F, 0x35}}
Table N.33: PCI Express Error Record
Bits0 8
Indicates which of the following ﬁelds is valid:
Bit 0 -Port Type Valid
Bit 1 - Version Valid
Bit 2 - Command Status Valid
Bit 3 - Device ID Valid
Bit 4 - Device Serial Number Valid
Bit 5 - Bridge Control Status Valid
Bit 6 - Capability Structure Status Valid
Bit 7 - AER Info Valid
Bit 8-63 - Reserved
Port Type 8 4
PCIe Device/Port Type as deﬁned in the PCI Express capabilities
register:
0: PCI Express End Point
1: Legacy PCI End Point Device
4: Root Port 5: Upstream Switch Port
6: Downstream Switch Port
7: PCI Express to PCI/PCI-X Bridge
8: PCI/PCI-X to PCI Express Bridge
9: Root Complex Integrated Endpoint Device
10: Root Complex Event Collector
Version 12 4
PCIe Spec. version supported by the platform:
Byte 0-1: PCIe Spec. Version Number
• Byte0: Minor Version in BCD
• Byte1: Major Version in BCD
Byte2-3: Reserved
Command
Status16 4
Byte0-1: PCI Command Register
Byte2-3: PCI Status Register
Reserved 20 4 Must be zero
N.2. Format 2024Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.33 – continued from previous page
Device ID 24 16
PCIe Root Port PCI/bridge PCI compatible device number and bus
number information to uniquely identify the root port or bridge.
Default values for both the bus numbers is zero.
Byte 0-1: Vendor ID
Byte 2-3: Device ID
Byte 4-6: Class Code
Byte 7: Function Number
Byte 8: Device Number
Byte 9-10: Segment Number
Byte 11: Root Port/Bridge Primary Bus Number or device bus number
Byte 12: Root Port/Bridge Secondary Bus Number
Byte 13-14: Bit0:2: Reserved Bit3:15 Slot Number
Byte 15 Reserved
Device Serial
Number40 8
Byte 0-3: PCIe Device Serial Number Lower DW
Byte 4-7: PCIe Device Serial Number Upper DW
Bridge Con-
trol Status48 4
This ﬁeld is valid for bridges only.
Byte 0-1: Bridge Secondary Status Register
Byte 2-3: Bridge Control Register
Capability
Structure52 60
PCIe Capability Structure.
- The 60-byte structure is used to report device capabilities. This
structure is used to report the 36-byte PCIe 1.1 Capability Structure (See
Figure 7-9 of the PCI Express Base Speciﬁcation, Rev 1.1) with the last
24 bytes padded.
- This structure is also used to report the 60-byte PCIe 2.0 Capability
Structure (See Figure 7-9 of the PCI Express 2.0 Base Speciﬁcation.)
- The ﬁelds in the structure vary with different device types.
- The “Next CAP pointer” ﬁeld should be considered invalid and any
reserved ﬁelds of the structure are reserved for future use.
Note that PCIe devices without AER (PCI e_AER_INFO_STRU
CT_V ALID_BIT=0) may report status using this structure.
AER Info 112 96 PCIe Advanced Error Reporting Extended Capability Structure.
N.2. Format 2025Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.8 PCI/PCI-X Bus Error Section
Type: {0xC5753963, 0x3B84, 0x4095, {0xBF, 0x78, 0xED, 0xDA, 0xD3, 0xF9, 0xC9, 0xDD}}
Table N.34: PCI/PCI-X Bus Error Section
Bits0 8
Bit 0 -Error Status Valid
Bit 1 - Error Type Valid
Bit 2 - Bus Id Valid
Bit 3 - Bus Address Valid
Bit 4 - Bus Data Valid
Bit 5 - Command Valid
Bit 6 - Requestor Id Valid
Bit 7 - Completer Id Valid
Bit 8 - Target Id Valid
Bit 9-63 Reserved
Error Status 8 8 PCI Bus Error Status. See See Error Status for details.
Error Type 16 2
PCI Bus error Type
Byte 0:
0 - Unknown or OEM system speciﬁc error
1 - Data Parity Error
2 - System Error
3 - Master Abort
4 - Bus Timeout or No Device Present (No DEVSEL#)
5 - Master Data Parity Error
6 - Address Parity Error
7 - Command Parity Error
Byte 1: Reserved
Bus Id 18 2
Bits 0:7 - Bus Number
Bits 8:15 - Segment Number
Reserved 20 4
Bus Address 24 8 Memory or I/O address on the bus at the time of the error.
Bus Data 32 8 Data on the PCI bus at the time of the error.
Bus Com-
mand40 8
Bus command or operation at the time of the error.
Byte 7: Bits 7-1: Reserved (should be zero)
Byte 7: Bit 0: If 0, then the command is a PCI command.
If 1, the command is a PCI-X command.
N.2. Format 2026Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.34 – continued from previous page
Bus Re-
questor Id48 8 PCI Bus Requestor Id.
Bus Com-
pleter Id56 8 PCI Bus Responder Id.

Byte 0:
Bus Id 18 2
Bus Com-
mand40 8
Bus Re-
Bus Com-
Target Id 64 8 PCI Bus intended target identiﬁer.
N.2.9 PCI/PCI-X Component Error Section
Type: {0xEB5E4685, 0xCA66, 0x4769, {0xB6, 0xA2, 0x26, 0x06, 0x8B, 0x00, 0x13, 0x26}}
Table N.35: PCI/PCI-X Component Error Section
Bits0 8
Indicate which ﬁelds are valid:
Bit 1 - Id Info Valid
Bit 2 - Memory Number Valid
Bit 3 - IO Number Valid
Bit 4 - Register Data Pair Valid
Bit 5-63 Reserved
Error Status 8 8 PCI Component Error Status. See Error Status for details.
Id Info 16 16
Identiﬁcation Information:
Bytes 0-1: Vendor Id
Bytes 1-2: Device Id
Bytes 4-6: Class Code
Byte 9: Bus Number
Byte 10: Segment Number
Bytes 11-15: Reserved
Memory
Number32 4 Number of PCI Component Memory Mapped register address/data pair
values present in this structure.
IO Number 36 4 Number of PCI Component Programmed IO register address/data pair
Register Data
Pairs40 2x8xN An array of address/data pair values. The address and data information
may be from 2 to 8 bytes of actual data represented in the 8 byte array
locations.
N.2. Format 2027Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.10 Firmware Error Record Reference
Type: {0x81212A96, 0x09ED, 0x4996, {0x94, 0x71, 0x8D, 0x72, 0x9C, 0x8E, 0x69, 0xED}}
Table N.36: Firmware Error Record Reference
Firmware
Error Record
Type0 1
Identiﬁes the type of ﬁrmware error record that is referenced by this
section:
0: IPF SAL Error Record
1: SOC Firmware error record Type1 is reserved and used by Legacy
CrashLog support
2: SOC Firmware error record Type2
All other values reserved
Revision 1 1 Indicates the Header Revision. For this Revision of the speciﬁcation value
is 2.
Reserved 1 7 Must be zero.
Record Identi-
ﬁer8 8
This value uniquely identiﬁes the ﬁrmware error record referenced by
this section. This value may be used to retrieve the referenced ﬁrmware
error record using means appropriate for the error record type.
Note : value is ignored for Revision >=1 of the header and must be set to
NULL .
Record identi-
ﬁer GUID ex-
tension16 16
Note : in case if Error Record Type == 2 then this ﬁled indicates the
GUID.
For Error Record Type 0 and Type 1 this ﬁeld is ignored.
N.2.11 DMAr Error Sections
The DMAr error sections are divided into two different components as described below:
DMAr Generic Error Section: This section holds information about DMAr errors in a generic form and will be
common across all DMAr unit architectures.
Architecture speciﬁc DMAr Error Section: This section consists of DMA remapping errors speciﬁc to the archi-
tecture. In addition, certain state information of the DMAr unit is captured at the time of error. This section is
unique for each DMAr architecture (VT-d, IOMMU).
N.2. Format 2028Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.11.1 DMAr Generic Error Section
Type: {0x5B51FEF7, 0xC79D, 0x4434, {0x8F, 0x1B, 0xAA, 0x62, 0xDE, 0x3E, 0x2C, 0x64}}
Table N.37: DMAr Generic Errors
Requester-ID 0 2 Device ID associated with a fault condition
Segment
Number2 2 PCI segment associated with a device
Fault Reason 4 1
1h: Domain mapping table entry is not present
2h: Invalid domain mapping table entry
3h: DMAr unit’s attempt to access the domain mapping table resulted in
an error
4h: Reserved bit set to non-zero value in the domain mapping table
5h: DMA request to access an address beyond the device address width
6h: Invalid read or write access
7h: Invalid device request
8h: DMAr unit’s attempt to access the address translation table resulted
in an error
9h: Reserved bit set to non-zero value in the address translation table
Ah: Illegal command error
Bh: DMAr unit’s attempt to access the command buffer resulted in an
error
Other values are reserved
Access Type 5 1
0h: DMA Write
1h: DMA Read
Address Type 6 1
0h: Untranslated request
1h: Translation request
Architecture
Type7 1 1h: VT-d architecture 2h: IOMMU architecture Other values are reserved
Device Ad-
dress8 8 This ﬁeld contains the 64-bit device virtual address in the faulted DMA
request.
Reserved 16 16 Must be 0
N.2. Format 2029Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
N.2.11.2 Intel® VT for Directed I/O speciﬁc DMAr Error Section
Type: {0x71761D37, 0x32B2, 0x45cd, {0xA7, 0xD0, 0xB0, 0xFE 0xDD, 0x93, 0xE8, 0xCF}} All ﬁelds in this error
section are speciﬁc to Intel’s VT-d architecture. This error section has a ﬁxed size.
Table N.38: Intel® VT for Directed I/O speciﬁc DMAr Errors
Version 0 1 Value of version register as deﬁned in VT-d architecture
Revision 1 1 Value of revision ﬁeld in VT-d speciﬁc DMA remapping reporting structure
OemId 2 6 Value of OEM ID ﬁeld in VT-d speciﬁc DMA remapping reporting structure
Capability 8 8 Value of capability register in VT-d architecture
Extended
Capabil-
ity16 8 Value of extended capability register in VT-d architecture
Global
Com-
mand24 4 Value of Global Command register in VT-d architecture programmed by the
operating system
Global
Status28 4 Value of Global Status register in VT-d architecture
Fault
Status32 4 Value of Fault Status register in VT-d architecture
Reserved 36 12 Must be 0
Fault
record48 16 Fault record as deﬁned in the VT-d speciﬁcation
Root En-
try64 16 Value from the root entry table for the given requester-ID
Context
Entry80 16 Value from the context entry table for the given requester-ID.
Level
6 Page
Table
Entry96 8 PTE entry for device virtual address in page level 6
Level
5 Page
Table
Entry104 8 PTE entry for device virtual address in page level 5
Level
4 Page
Table
Entry112 8 PTE entry for device virtual address in page level 4
Level
3 Page
Table
Entry120 8 PTE entry for device virtual address in page level 3
Level
2 Page
Table
Entry128 8 PTE entry for device virtual address in page level 2.
N.2. Format 2030Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.38 – continued from previous page
Level
1 Page
Table
Entry136 8 PTE entry for device virtual address in page level 1
N.2.11.3 IOMMU Speciﬁc DMAr Error Section
Type: {0x036F84E1, 0x7F37, 0x428c, {0xA7, 0x9E, 0x57, 0x5F, 0xDF, 0xAA, 0x84, 0xEC}}
All ﬁelds in this error record are speciﬁc to AMD’s IOMMU speciﬁcation. This error section has a ﬁxed size.
Table N.39: IOMMU-speciﬁc DMAr Errors
Revision 0 1 Speciﬁes the IOMMU speciﬁcation revision
Reserved 1 7 Must be 0
Control 8 8 IOMMU control register
Status 16 8 IOMMU status register
Reserved 24 8 Must be 0
Event Log En-
try32 16 IOMMU fault related event log entry as deﬁned in the IOMMU speciﬁca-
tion
Reserved 48 16 Must be 0
Device Table
Entry64 32 Value from the device table for a given Requester ID
Level 6 Page
Table Entry96 8 PTE entry for device virtual address in page level 6
Level 5 Page
Table Entry104 8 PTE entry for device virtual address in page level 5
Level 4 Page
Table Entry112 8 PTE entry for device virtual address in page level 4
Level 3 Page
Table Entry120 8 PTE entry for device virtual address in page level 3
Level 2 Page
Table Entry128 8 PTE entry for device virtual address in page level 2
Level 1 Page
Table Entry136 8 PTE entry for device virtual address in page level 1
N.2.12 CCIX PER Log Error Section
Type:{0x91335EF6, 0xEBFB, 0x4478, {0xA6, 0xA6, 0x88, 0xB7, 0x28, 0xCF, 0x75, 0xD7}}
Table N.40: CCIX PER Log Error Record
Length 0 4 Length in bytes for entire structure.
N.2. Format 2031Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.40 – continued from previous page
Bits4 8
Bit 0 - CCIX Source ID Valid
Bit 1 - CCIX Port ID Valid
Bit 2 - CCIX PER Log Valid
Bit 3-63 - Reserved
CCIX Source
ID12 1
If the agent type is an HA, SA, or RA: This ﬁeld indicates the CCIX
Agent ID of the component that reported this error. In this case bits 7:6
must be zero, since Agent ID is only 6 bits.
Otherwise, this ﬁeld this speciﬁes the CCIX Device ID (i.e. in the case of
Port, CCIX Link, or device errors).
CCIX Port ID 13 1 This ﬁeld indicates the CCIX Port ID that reported this error. Bits 7:5
must be zero, since CCIX Port ID is only 5 bits.
CCIX PER
Log16 20. . . n
DWORD (32-bit) entries in CCIX PER Log Structure, as described in
Section 7.3.2 of the CCIX Base Speciﬁcation - Revision 1.0.
NOTE : The Per Log Structure contains a header describing the number
of DWORDs in the error record.

Bits4 8
ID12 1
CCIX PER
N.2.13 Compute Express Link (CXL) Protocol Error Section
Type: { 0x80B9EFB4, 0x52B5, 0x4DE3, { 0xA7, 0x77, 0x68, 0x78, 0x4B, 0x77, 0x10, 0x48 } }
Table N.41: CXL Protocol Error Section
Bit 0 - CXL Agent Type ﬁeld is valid
Bit 1 - CXL Agent Address ﬁeld is valid
Bit 2 - Device ID ﬁeld is valid
Bit 3 - Device Serial Number ﬁeld is valid
Bit 4 - Capability Structure ﬁeld is valid
Bit 5 - CXL DVSEC ﬁeld is valid
Bit 6 - CXL Error Log ﬁeld is valid
Bits 7:63 - Reserved
N.2. Format 2032Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.41 – continued from previous page
CXL Agent Type 8 1
0 - This error was detected by a CXL 1.1 device
1 - This error was detected by a CXL 1.1 host downstream port
2 - This error was detected by CXL 2.0 device
3 - This error was detected by CXL 2.0 Logical Device
4 - This error was detected by CXL 2.0 Fabric Manager
managed Logical device
5 - This error was detected by CXL 2.0 Root Port
6 - This error was detected by CXL 2.0 Downstream Switch
Port
7 - This error was detected by CXL 2.0 Upstream Switch Port
8-255 - Reserved
In this table, the term “CXL Device” is used to refer to CXL
1.1 Device, CXL 2.0 Device, CXL 2.0 Logical Device or a
CXL 2.0 Fabric Manager Managed Logical Device.
In this table, the term “CXL Port” is used to refer to CXL 1.1
host downstream port, CXL Root Port, CXL Downstream
Switch Port and Upstream Switch Port.
Reserved 9 7
Must be zero
CXL Agent Ad-
dress16 8
If this CXL agent is a CXL device, CXL Root Port, CXL
Downstream Switch Port or CXL Upstream Switch Port, then
the PCIe compatible device/function number, bus number, and
segment number information are used to uniquely identify the
Component:
Byte 0 - Function number
Byte 1 - Device number
Byte 2 - Bus number
Bytes 3-4 - Segment number
Bytes 5-7 - Reserved
If CXL agent is a CXL 1.1 host downstream port:
Byte 0-7 - CXL Port RCRB Base address
N.2. Format 2033Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Downstream Switch Port, or CXL Upstream Switch Port, then
this ﬁeld provides various identiﬁers for the device:
Bytes 0-1: Vendor ID
Bytes 2-3: Device ID
Bytes 4-5: Subsystem Vendor ID
Bytes 6-7: Subsystem Device ID
Bytes 8-9: Class Code
Byte 10-11:
Bits 0-2: Reserved
Bits 3-15: Slot Number
Byte 12-15: Reserved
Number40 8
If this CXL agent is a CXL device:
Byte 0-3: CXL Device Serial Number Lower DW
Byte 4-7: CXL Device Serial Number Upper DW
Capability Struc-
ture48 60
If this CXL agent is a CXL device, PCIe Capability Structure,
CXL Root Port, CXL Downstream Switch Port, or CXL
Upstream Switch Port, this is the PCIe Capability Structure of
the agent.
• The 60-byte structure is used to report device capabilities.
This structure is used to report the 36-byte PCIe 1.1 Capability
Structure (See Figure 7-9 of the PCI Express Base
Speciﬁcation, Rev 1.1) with the last 24 bytes padded.
• This structure is also used to report the 60-byte PCIe 2.0
Capability Structure (See Figure 7-9 of the PCI Express 2.0
Base Speciﬁcation.)
• The ﬁelds in the structure vary with different device types.
• The “Next CAP pointer” ﬁeld should be considered invalid
and any reserved ﬁelds of the structure are reserved for future
use. Note that PCIe devices without AER (PCI
e_AER_INFO_STRU CT_V ALID_BIT=0) may report status
using this structure.
CXL DVSEC
Length108 2
The length in bytes of the CXL DVSEC ﬁeld
CXL Error Log
Length110 2
The length in bytes of the CXL Error Log ﬁeld
Reserved 112 4
N.2. Format 2034Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
CXL DVSEC 116
Varies The length of this variable-length structure is deﬁned by the
CXL DVSEC Length ﬁeld.
If the CXL agent is a CXL device, this ﬁeld contains a copy of
the CXL Device DVSEC, as deﬁned by the “PCIe DVSEC for
Flex Bus Device” structure in the CXL Speciﬁcation.
If the CXL agent is a CXL port, this ﬁeld contains a copy of
the CXL Port DVSEC, as deﬁned by the “CXL DVSEC for
Flex Bus Port” structure in the CXL peciﬁcation.
CXL Error Log Varies Varies
The length of this variable-length structure is deﬁned by the
CXL Error Log Length ﬁeld. For CXL devices and CXL ports,
this ﬁeld contains a copy of the “CXL RAS Capability
Structure”, as deﬁned in the CXL Speciﬁcation.
N.2.14 CXL Component Events Section
Refer to the Events Record Format for CXL components in the CXL Speciﬁcation, Rev 2.0 or later.
• For the Section Type GUID: Refer to the Event Record Identiﬁer ﬁeld (Offset 0) of the Events Record Format
for each CXL component.
• For the CXL Component Event Log: Refer to the Common Event Record ﬁeld (Offset 16) of the Events Record
Format for each CXL component.
Table N.42: CXL Component Event Log Record
Validation Bits 4 8
Bit 0 - Device ID Valid
Bit 1 - Device Serial Number Valid
Bit 2 - CXL Component Event Log Valid
N.2. Format 2035Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table N.42 – continued from previous page
Device ID 12 12
PCIe Device Identiﬁers of CXL Component:
Byte 4: Function Number
Byte 5: Device Number
Byte 6: Bus Number
Byte 7-8: Segment Number
Byte 9-10:
Bit 0:2: Reserved
Bit 3:15 Slot Number
Byte 11 Reserved
Number24 8 Byte 0-3: PCIe Device Serial Number Lower DW Byte 4-7:
PCIe Device Serial Number Upper DW
Event Log32
•CXL Component Event Log, starting with the Common Event
Record ﬁeld corresponding to the Component speciﬁed by the
Section Type GUID. The Length of this ﬁeld may vary.
N.2. Format 2036APPENDIX
O
UEFI ACPI DATA TABLE
To prevent ACPI namespace collision, a UEFI ACPI table format is deﬁned. This allows creation of ACPI tables
without colliding with tables reserved in the namespace.
Table O.1: UEFI Table Structure
Field Byte
LengthByte
OffsetDescription
Header
Signature 4 0 ‘UEFI’ (0x55, 0x45, 0x46, 0x49). Signature for UEFI drivers that pro-
duce ACPI tables.
Length 4 4 Length, in bytes, of the entire UEFI Table
Revision 1 8 1
Checksum 1 9 Entire table must sum to zero.
OEMID 6 10 OEM ID.
OEM Table
ID8 16 For the UEFI Table, the table ID is the manufacture model ID.
OEM Revi-
sion4 24 OEM revision of UEFI table for supplied OEM Table ID.
Creator ID 4 28 Vendor ID of utility that created the table.
Creator Revi-
sion4 32 Revision of utility that created the table.
Identiﬁer 16 36 This value contains a GUID which identiﬁes the remaining table contents.
DataOffset 2 52 Speciﬁes the byte offset to the remaining data in the UEFI table.
Data X DataOffset Contains the rest of the UEFI table contents
The ﬁrst use of this UEFI ACPI table format is the SMM Communication ACPI Table. This table describes a special
software SMI that can be used to initiate inter-mode communication in the OS present environment by non-ﬁrmware
agents with SMM code.
NOTE :The use of the SMM Communication ACPI table is deprecated in UEFI spec. 2.7. This is due to the lack of
a use case for inter-mode communication by non-ﬁrmware agents with SMM code and support for initiating this form
of communication in common OSes .
Table O.2: SMM Communication ACPI Table.
Field Byte
Signature 4 0 ‘UEFI’ (0x55, 0x45, 0x46, 0x49) Signature for UEFI drivers
that produce ACPI tables.
2037Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Table O.2 – continued from previous page
Length 4 4 66+N. Length, in bytes, of the entire Table. N is a length of
the optional implementation speciﬁc data that can be included
Revision 1 8 2
OEM Table ID 8 16 For the UEFI Table, the table ID is the manufacturer model ID.
OEM Revision 4 24 OEM revision of UEFI table for supplied OEM Table ID.
Creator Revision 4 32 Revision of utility that created the table.
Identiﬁer 16 36 GUID {0xc68ed8e2, 0x9dc6, 0x4cbd, 0x9d, 0x94, 0xdb, 0x65,
\ 0xac, 0xc5, 0xc3, 0x32}
DataOffset 2 52 Must be 54 for this version of the speciﬁcation. Speciﬁes the
byte offset of the SW SMI Number ﬁeld, relative to the start
of this table. Future expansion may place additional ﬁelds be-
tween DataOffset andSW SMI Number , so this offset should
always be used to calculate the location of SW SMI Number .
SW SMI Number 4 54 Number to write into software SMI triggering port.
Buffer Ptr Address 8 58 Address of the communication buffer pointer. The pointer ad-
dress (this ﬁeld) and the pointer value (the actual address of

the communication buffer) are 64-bit physical addresses. The
creator of this table must initialize pointer value with 0. The
communication buffer must begin with the EFI_SMM_COMM
UNICATE_HEADER deﬁned in the “Related Deﬁnitions” sec-
tion below. The communication buffer must be physically con-
tiguous.
Invocation register 12 66 Generic Address Structure (GAS) which provides the address
of a register that must be written to with the address of a com-
munication buffer to invoke a management mode service. Us-
ing this method of invocation is optional, and if not present this
span of the table should be populated with zeros. See ACPI6.0
“Generic Address Structure”
O.1 Invocation method
There are two methods of invocation provided by this speciﬁcation:
1. Using invocation register
If the invocation register is non-zero, this then this method takes precedence and the SW SMI number ﬁeld
and DataOffset ﬁelds must be ignored. The invocation register entry provides the address of a register that
must be written to in order to invoke the SMM service. The caller must write the communication buffer ad-
dress into the register. This will cause an SMM invocation. Upon return from the SMM service call the
value in the register provides a return error codes from the SMM invocation. See PI/SMM V ol 4 version xx.yy
EFI_SMM_COMMUNICATION_PROTOCOL.Communicate function for valid error codes.
The invocation address ﬁeld uses generic address structure to specify the register address. GAS allows the address
space of the register to be Functional Fixed Hardware (FFH). If this address space is used please refer to CPU archi-
tecture speciﬁc documentation for ascertaining how the write to the register should be performed. For more details on
the GAS format please see the ACPI Speciﬁcation .
Note that for implementations that support concurrent invocation of SMM from multiple processors, the register
provided must be a per processor register. In such implementation, the calling execution context must not migrate
O.1. Invocation method 2038Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
from one CPU to another between writing to the register, to make the SMM call, and reading the value of the register,
to read the error return code.
2. Using the SW SMI number
This method is speciﬁc to x86 CPUs .
In order to initiate inter-mode communication OS present agent has to perform the following tasks:
• Prepare communication data buffer that starts with the EFI_SMM_COMMUNICATE_HEADER .
• Check the value of the communication buffer pointer (a value at the address speciﬁed by the Buffer Ptr Address
ﬁeld). If the pointer’s value is zero, update it with the address of the communication buffer. If the pointer’s
value is non-zero, another inter-mode communication transaction is in progress, and the current communication
attempt has to be postponed or canceled.
NOTE :These steps must be performed as an atomic transaction. For example, on IA-32/x64 platforms this can be
done using the CMPXCHG CPU instruction .
• Generate software SMI using value from the SMM Communication ACPI Table. The actual means of generating
the software SMI is platform-speciﬁc.
• Set communication buffer pointer’s value to zero.
EFI_GUID HeaderGuid;
UINTN MessageLength;
UINT8 Data[ANYSIZE_ARRAY];
} EFI_SMM_COMMUNICATE_HEADER;
HeaderGuid Allows for disambiguation of the message format. Type EFI_GUID is deﬁned in InstallProtocolInter-
face() .
MessageLength Describes the size of Data (in bytes) and does not include the size of the header.
Data Designates an array of bytes that is MessageLength in size
O.1. Invocation method 2039APPENDIX
P
HARDWARE ERROR RECORD PERSISTENCE USAGE
The OS determines if a platform implements support for Hardware Error Record Persistence by reading the HwEr-
rRecSupport globally deﬁned variable. If the attempt to read this variable returns EFI_NOT_FOUND (14), then the
OS will infer that the platform does not implement Hardware Error Record Persistence. If the attempt to read this
variable succeeds, then the OS uses the returned value to determine whether the platform supports Hardware Error
Record Persistence. A non-zero value indicates that the platform supports Hardware Error Record Persistence.
P.1 Determining space
To determine the amount of space (in bytes) guaranteed by the platform for saving hardware error records, the OS
invokes QueryVariableInfo, setting the HR bit in the Attributes bitmask.
P.2 Saving Hardware error records
To save a hardware error record, the OS invokes SetVariable, supplying EFI_HARDWARE_ERROR_V ARIABLE as
the VendorGuid and setting the HR bit in the Attributes bitmask. The VariableName will be constructed by the OS
by concatenating an index to the string “HwErrRec” (i.e., HwErrRec0001). The index portion of the variable name
is determined by reading all of the hardware error record variables currently stored on the platform and choosing an
appropriate index value based on the names of the existing variables. The platform saves the supplied Data. If insufﬁ-
cient space is present to store the record, the platform will return EFI_OUT_OF_RESOURCES, in which case, the OS
may clear an existing record and retry. A retry attempt may continue to fail with status EFI_OUT_OF_RESOURCES
if a reboot is required to coalesce resources after deletion. The OS may only save error records after ExitBootServices
is called. Firmware may also use the Hardware Error Record Persistence interface to write error records, but it may
only do so before ExitBootServices is called. If ﬁrmware uses this interface to write an error record, it must use the
VariableName format used by the OS as described above and the error records it creates must contain the ﬁrmware’s
CreatorId. Firmware may overwrite error records whose CreatorId matches the ﬁrmware’s CreatorId. Firmware may
overwrite error records that have been cleared by other components.
During OS initialization, the OS discovers the names of all persisted error record variables by enumerating the current
variable names using GetNextVariableName. Having identiﬁed the names of all error record variables, the OS will
then read and process all of the error records from the store. After the OS processes an error record, it clears the
variable if it was the creator of the variable (determined by checking the CreatorId ﬁeld of the error record).
2040Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
P.3 Clearing error record variables
To clear error record variables, the OS invokes SetVariable, supplying EFI_HARDWARE_ERROR_V ARIABLE as
the VendorGuid and setting the HR bit in the Attributes bitmask. The supplied DataSize, and Data parameters will all
be set to zero to indicate that the variable is to be cleared. The supplied VariableName identiﬁes which error record
variable is to be cleared. The OS may only clear error records after ExitBootServices has been called. The OS itself
may only clear error records which it created (e.g. error records whose CreatorId matches that of the OS). However, a
management application running on the OS may clear error records created by other components. This enables error
records created by ﬁrmware or other OSes to be cleared by the currently running OS.
P.3. Clearing error record variables 2041APPENDIX
Q
REFERENCES
Q.1 Related Information
The following publications and sources of information may be useful to you or are referred to by this speciﬁcation:
• “8802.1x Port-based access control” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “802.1X-2004, IEEE Standard for Local and Metropolitan Area Networks Port-Based Network Access Control
” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “AMD64 Architecture Programmer’s Manual” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Advanced Conﬁguration and Power Interface Speciﬁcation, 3.0”. at “Links to UEFI-Related Documents”
(http://ueﬁ.org/ueﬁ) under the heading
• “Advanced Conﬁguration and Power Interface Speciﬁcation, 4.0” at “Links to UEFI-Related Documents”
(http://ueﬁ.org/ueﬁ) .
• “Address Resolution Protocol; Refer to Appendix E, “32/ 64-Bit UNDI Speciﬁcation” at “Links to UEFI-Related
Documents” ( http://ueﬁ.org/ueﬁ) .
• “BIOS Boot Speciﬁcation Version 1.01” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “CAE Speciﬁcation [UUID], DCE 1.1:Remote Procedure Call, Document Number C706, Universal Unique
Identiﬁer Appendix” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[BASE64] RFC 1521: MIME (Multipurpose Internet Mail Extensions) Part One: Mechanisms for Spec-
ifying and Describing the Format of Internet Message Bodies “at “Links to UEFI-Related Documents”
• “Bluetooth Network Encapsulation Protocol (BNEP) Speciﬁcation, version 1.0” at “Links to UEFI-Related

• “BLUETOOTH SPECIFICATION, version 4.1” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• Bootstrap Protocol ;This reference is included for backward compatibility. BC protocol supports DHCP and
BOOTP. Refer to Appendix E, “32/ 64-Bit UNDI Speciﬁcation, RFC 0951” at “Links to UEFI-Related Docu-
ments” ( http://ueﬁ.org/ueﬁ) .
•Compute Express Link (CXL) Speciﬁcation: see download link at <https://ueﬁ.org/ueﬁ>__
https://ueﬁ.org/ueﬁ#cxl-speciﬁcation .
• [DBCS] Japanese Language DBCS (Double Byte Character Set): MS-DOS Version, Sizuoka Information In-
dustry, AX Conference, 1991.
• “[EAP] Tunneled TLS Authentication Protocol Version 1 (EAP-TTLSv1)” at “Links to UEFI-Related Docu-
2042Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• [ECMA 262] ECMA Script Language Speciﬁcation (ECMA-262) Edition 5.1”.at “Links to UEFI-Related Doc-
uments” ( http://ueﬁ.org/ueﬁ) under the heading “
• ”EFI Speciﬁcation Version 1.02 ” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• ”EFI Speciﬁcation Version 1.10 ” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “El Torito” Bootable CD-ROM Format Speciﬁcation, Version 1.0” at “Links to UEFI-Related Documents”
•Envisioning Information , Edward R. Tufte, Graphics Press, 1990.
•File Veriﬁcation Using CRC , Mark R. Nelson, Dr. Dobbs, May 1994
•HTML: The Deﬁnitive Guide , 2nd Edition, Chuck Musciano and Bill Kennedy, O’Reilly and Associates, Inc.,
1997, ISBN: 1-56592-235-2.
• ”IEEE Standard for Local and metropolitan area networks: Virtual Bridged Local Area Networks, IEEE Std
802.1Q - 2005” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• ”Information Technology – BIOS Enhanced Disk Drive Services (EDD) , working draft T13/ 1386D, Revision
5a” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• ”Intel 64 and IA=32 Architecture Software Developer’s Manual ” heading at “Links to UEFI-Related Docu-
• “iSCSI Boot Firmware Table (iBFT) as deﬁned in ACPI 3.0b Speciﬁcation , Version 1.01,” heading at “Links to
UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “ISO Standard 9995, Keyboard layouts for text and ofﬁce systems” heading at “Links to UEFI-Related Docu-
• “Itanium® Architecture Software Developer’s Manual, V olume 1: Application Architecture, Rev. 2.2,” heading
at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Itanium® Architecture Software Developer’s Manual, V olume 2: System Architecture, Rev. 2.2” heading at
“Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Itanium® Architecture Software Developer’s Manual, V olume 3: Instruction Set Reference, Rev. 2.2” heading
• “Itanium® Software Conventions and Runtime Architecture Guide” heading at “Links to UEFI-Related Docu-
• “Itanium® System Abstraction Layer Speciﬁcation” heading at “Links to UEFI-Related Documents”
• IEEE 1394 Speciﬁcation, http://www.1394ta.org/Technology/Speciﬁcations/speciﬁcations.htm
• “Internet Engineering Task Force (IETF)” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ)
. Refer to Appendix E, “32/64-Bit UNDI Speciﬁcation,” for more information.
• “ISO 639-2:1998. Codes for the Representation of Names of Languages - Part2: Alpha-3 code” heading at
• ISO/IEC 3309:1991(E), Information Technology - Telecommunications and information exchange between sys-
tems - High-level data link control (HDLC) procedures - Frame structure , International Organization For Stan-
dardization, Fourth edition 1991-06-01
• ITU-T Rec. V .42, Error-Correcting Procedures for DCEs using asynchronous-to-synchronous conversion ,
October, 1996
•JavaScript: The Deﬁnitive Guide , 3rd Edition, David Flanagan, O’Reilly and Associates, Inc., 1998, ISBN:
1-56592-392-8.
Q.1. Related Information 2043Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
•JavaScript: The Complete Reference , Thomas Powell & Fritz Schneider (McGraw-Hill/ Osborne, Emeryville
California, 2004)
• “Microsoft Extensible Firmware Initiative FAT32 File System Speciﬁcation, Version 1.03” heading at “Links to
• “Microsoft Portable Executable and Common Object File Format Speciﬁcation, Version 8.1” heading at “Links
to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Microsoft Windows Authenticode Portable Executable Signature Format, Version 1.0” heading at “Links to
• “OSTA Universal Disk Format Speciﬁcation, Revision 2.00” heading at “Links to UEFI-Related Documents”
• “PCI BIOS Speciﬁcation, Revision 3.0” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Part11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Speciﬁcations” at “Links to
• “PCI Express Base Speciﬁcation, Revision 2.1” heading at “Links to UEFI-Related Documents”
• “PCI Hot-Plug Speciﬁcation, Revision 1.0,” heading at “Links to UEFI-Related Documents”
• “PCI Local Bus Speciﬁcation, Revision 3.0” heading at “Links to UEFI-Related Documents”
• “Plug and Play BIOS Speciﬁcation, Version 1.0A,” heading at “Links to UEFI-Related Documents”
• “POST Memory Manager Speciﬁcation, Version 1.01,” heading at “Links to UEFI-Related Documents”
•Professional XML , Didier Martin, Mark Birbeck, et. al., Wrox Press, April, 2000, ISBN: 1-861003-11-0.
• [PUI] Programming the User Interface: Principles and Examples , Judith R. Brown, Steve Cunningham, John
Wiley & Sons, 1989, ISBN: 0-471-63843-9.
• “Microsoft’s PEAP version 0” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• [PKCS] The Public-Key Cryptography Standards, RSA Laboratories, Redwood City, CA: RSA Data Security,
Inc.
• “PC/SC Speciﬁcation, Part 3: Requirements for PC-Connected Interface Devices” at “Links to UEFI-Related
• “Processor Architecture Type “at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Protected EAP Protocol (PEAP)” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Protected EAP Protocol (PEAP) Version 2” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Request For Comments” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) . Refer to Ap-
pendix E, “32/64-Bit UNDI Speciﬁcation,” for more information.
• “[RFC0768] User Datagram Protocol - UDP over IPv4” heading at “Links to UEFI-Related Documents”
• “[RFC 791] Internet Protocol DARPA Internet Program Protocol (IPv4) Speciﬁcation” at “Links to UEFI-
Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[RFC0792] ICMP for Ipv4” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) . Refer to
Appendix E, “32/64-Bit UNDI Speciﬁcation,” for more information
Q.1. Related Information 2044Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• “[RFC0793] Transmission Control Protocol - TCPv4” heading at “Links to UEFI-Related Documents”
(http://ueﬁ.org/ueﬁ) . Refer to Appendix E,”32/64-Bit UNDI Speciﬁcation,” for more information.
• “[RFC 1034] Domain Names - Concepts and Facilities” at “Links to UEFI-Related Documents”
• “[RFC 1035] Domain Names - Implementation and Speciﬁcation” at “Links to UEFI-Related Documents”
• “[RFC1350] Trivial File Transfer Protocol - TFTP” heading at “Links to UEFI-Related Documents”
(http://ueﬁ.org/ueﬁ) . Refer to Appendix E, “32/64-Bit UNDI Speciﬁcation,” for more information.
• “[RFC 1700] ASSIGNED NUMBERS” ate “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[RFC 1994] PPP Challenge Handshake Authentication Protocol (CHAP)” at “Links to UEFI-Related Docu-
• “[RFC2131] Dynamic Host Conﬁguration Protocol” at “Links to UEFI-Related Documents”
• “[RFC2132] DHCP Options and BOOTP Vendor Extensions,” at “Links to UEFI-Related Documents”
• “[RFC2147] Transmission Control Protocol v6 - TCPv6” heading at “Links to UEFI-Related Documents”
(http://ueﬁ.org/ueﬁ) . Refer to Appendix E,”32/64-Bit UNDI Speciﬁcation,” for more information. Refer to
Appendix E, “32/64-Bit UNDI Speciﬁcation,” for more information.
• “[RFC2236] Internet Group Management Protocol” heading at “Links to UEFI-Related Documents”
• “[RFC 2246] The TLS Protocol Version 1.0” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[RFC2315] Cryptographic Message Syntax Version 1.5” at “Links to UEFI-Related Documents”

• “[RFC2347] TFTP Option Extension” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
Refer to Appendix E, “32/64-Bit UNDI Speciﬁcation,” for more information.
• “[RFC2348] TFTP Blocksize Option” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[RFC2349] TFTP Timeout Interval and Transfer Size Options” heading at “Links to UEFI-Related Documents”
• “[RFC 2407]The Internet IP Security Domain of Interpretation for ISAKMP” at “Links to UEFI-Related Docu-
• “[RFC 2408]Internet Security Association and Key Management Protocol(ISAKMP)” at “Links to UEFI-
• “[RFC 2409]The Internet Key Exchange (IKE)” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[RFC2454] User Datagram Protocol - UDP over IPv6” heading at “Links to UEFI-Related Documents”
• “[RFC 2459] Internet X.509 Public Key Infrastructure Certiﬁcate and CRL Proﬁle” at “Links to UEFI-Related
• “[RFC 2460] Internet Protocol, Version 6 (IPv6) Speciﬁcation” at “Links to UEFI-Related Documents”
• “[RFC2463] ICMP for Ipv6” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) . Refer to
Q.1. Related Information 2045Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• “[RFC 2759] Microsoft PPP CHAP Extensions, Version 2” at “Links to UEFI-Related Documents”
• “[RFC 2818] HTTP Over TLS” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[RFC 3004] The User Class option for DHCP” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• [RFC 3232] J. Reynolds, “Assigned Numbers: RFC 1700 is Replaced by an On-line Database”, January 2002
• “[RFC 3315] Dynamic Host Conﬁguration Protocol for IPv6 (DHCPv6)” at “Links to UEFI-Related Docu-
• “[RFC 3396] Encoding Long Options in the Dynamic Host Conﬁguration Protocol” at “Links to UEFI-Related
• “[RFC 3513] Internet Protocol Version 6 (IPv6) Addressing Architecture” at “Links to UEFI-Related Docu-
ments” ( http://ueﬁ.org/ueﬁ) under the heading.
• “[RFC 3596] DNS Extensions to Support IP Version 6” at “Links to UEFI-Related Documents”
• “[RFC 3617] Uniform Resource Identiﬁer (URI) Scheme and Applicability Statement for the Trivial File Trans-
fer Protocol (TFTP)” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[RFC 3646] DNS Conﬁguration options for Dynamic Host Conﬁguration Protocol for IPv6 (DHCPv6)” at
• “[RFC 3720] Internet Small Computer Systems Interface (iSCSI)” at “Links to UEFI-Related Documents”
• “[RFC 3748] Extensible Authentication Protocol (EAP)” at “Links to UEFI-Related Documents”
• “[RFC 3986 ]Uniform Resource Identiﬁers (URI): Generic Syntax” at “Links to UEFI-Related Documents”
• “[RFC 4173] Bootstrapping Clients using the Internet Small Computer System Interface (iSCSI) Protocol” at
• “[RFC 4301]Security Architecture for the Internet Protocol” at “Links to UEFI-Related Documents”
• “[RFC 4303]IP Encapsulation Security Payload (ESP)” at “Links to UEFI-Related Documents”
• “[RFC 4346] The Transport Layer Security (TLS) Protocol Version 1.1” at “Links to UEFI-Related Documents”
(http://ueﬁ.org/ueﬁ) under the heading.
• “[RFC 4347] Datagram Transport Layer Security” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ)
under the heading
• “[RFC4578] Dynamic Host Conﬁguration Protocol (DHCP) Options for the Intel Preboot eXecution Environ-
ment (PXE)” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “[RFC 5216] The EAP-TLS Authentication Protocol” at “Links to UEFI-Related Documents”
• “[RFC 5246] The Transport Layer Security (TLS) Protocol Version 1.2” at “Links to UEFI-Related Documents”
• “[RFC 5247] Extensible Authentication Protocol (EAP) Key Management Framework” at “Links to UEFI-
• “[RFC 5281] Extensible Authentication Protocol Tunneled Transport Layer Security Authenticated Protocol
Version 0” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
Q.1. Related Information 2046Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
• “[RFC 5970] DHCPv6 Options for Network Boot,” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ)
.
• “[RFC 6101] The Secure Sockets Layer (SSL) Protocol Version 3.0” at “Links to UEFI-Related Documents”
• “[RFC 6347] Datagram Transport Layer Security Version 1.2 (DTLS)” at “Links to UEFI-Related Documents”
• “[SM spec] Common Security: CDSA and CSSM, Version 2 (with corrigenda), was Signed Manifest Speciﬁca-
tion” at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
•Super VGA Graphics Programming Secrets , Steve Rimmer, Windcrest / McGraw-Hill, 1993, ISBN: 0-8306-
4428-8.
• “System Management BIOS Reference Speciﬁcation, Version 2.6.1” heading at “Links to UEFI-Related Docu-
•The Visual Display of Quantitative Information , Edward R. Tufte, Graphics Press, 1983.
• “The Unicode Standard, Version 5.2” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• “Universal Serial Bus PC Legacy Compatibility Speciﬁcation, Version 0.9,” heading at “Links to UEFI-Related
• “Universal Serial Bus Speciﬁcation, Revision 2.0” heading at “Links to UEFI-Related Documents”
• “USB Battery Charging Speciﬁcation” heading at “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ) .
• XML: A Primer, Simon St. Laurent, MIS:Press, 1998, ISBN:1-5582-8592-X.
Q.2 Prerequisite Speciﬁcations
In general, this speciﬁcation requires that functionality deﬁned in a number of other existing speciﬁcations be present
on a system that implements this speciﬁcation. This speciﬁcation requires that those speciﬁcations be implemented at
least to the extent that all the required elements are present.
This speciﬁcation prescribes the use and extension of previously established industry speciﬁcation tables whenever
possible. The trend to remove runtime call-based interfaces is well documented. The ACPI (Advanced Conﬁguration
and Power Interface) speciﬁcation is an example of new and innovative ﬁrmware technologies that were designed on
the premise that OS developers prefer to minimize runtime calls into ﬁrmware. ACPI focuses on no runtime calls to
the BIOS.
Q.2.1 ACPI Speciﬁcation
The interface deﬁned by the Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation is the primary OS
runtime interface for IA-32, x64 and Itanium platforms. ACPI fully deﬁnes the methodology that allows the OS to
discover and conﬁgure all platform resources. ACPI allows the description of non-Plug and Play motherboard devices
in a plug and play manner. ACPI also is capable of describing power management and hot plug events to the OS. (For
more information on ACPI, see “Links to UEFI-Related Documents” ( http://ueﬁ.org/ueﬁ ) under the heading “ACPI”;
see also http://ueﬁ.org/acpi ).
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Q.2.2 Additional Considerations for Itanium-BasedPlatforms
Any information or service that is available in Itanium architecture ﬁrmware speciﬁcations supercedes any require-
ment in the common supported 32-bit and Itanium architecture speciﬁcations listed above. The Itanium architecture
ﬁrmware speciﬁcations (currently the Itanium® System Abstraction Layer Speciﬁcation and portions of the Intel®
Itanium® Architecture Software Developer’s Manual, volumes 1-3) deﬁne the baseline functionality required for all
Itanium architecture platforms. The major addition that UEFI makes to these Itanium architecture ﬁrmware speciﬁ-
cations is that it deﬁnes a boot infrastructure and a set of services that constitute a common platform deﬁnition for
high-volume Itanium architecture-based systems to implement based on the more generalized Itanium architecture
ﬁrmware speciﬁcations.
The following speciﬁcations are the required Intel Itanium architecture speciﬁcations for all Itanium architecture-based
platforms:

Q.2. Prerequisite Speciﬁcations 2048APPENDIX
R
GLOSSARY
_ADR A reserved name in ACPI name space. It refers to an address on a bus that has standard enumeration. An
example would be PCI, where the enumeration method is described in the PCI Local Bus speciﬁcation.
_CRS A reserved name in ACPI name space. It refers to the current resource setting of a device. A _CRS is required
for devices that are not enumerated in a standard fashion. _CRS is how ACPI converts nonstandard devices into
Plug and Play devices.
_HID A reserved name in ACPI name space. It represents a device’s plug and play hardware ID and is stored as a 32-
bit compressed EISA ID. _HID objects are optional in ACPI. However, a _HID object must be used to describe
any device that will be enumerated by the ACPI driver in the OS. This is how ACPI deals with non–Plug and
Play devices.
_UID A reserved name in ACPI name space. It is a serial number style ID that does not change across reboots. If a
system contains more than one device that reports the same _HID, each device must have a unique _UID. The
_UID only needs to be unique for device that have the exact same _HID value.
ACPI Device Path A Device Path that is used to describe devices whose enumeration is not described in an industry-
standard fashion. These devices must be described using ACPI AML in the ACPI name space; this type of node
provides linkage to the ACPI name space.
ACPI Refers to the Advanced Conﬁguration and Power Interface Speciﬁcation and to the concepts and technology
it discusses. The speciﬁcation deﬁnes a new interface to the system board that enables the operating system to
implement operating system-directed power management and system conﬁguration.
Alt-GR Unicode Represents the character code of a key when the Alt-GR modiﬁer key is held down. This key (A2)
in some keyboard layouts is deﬁned as the right alternate key and serves the same function as the left alternate
key. However, in many other layouts it is a secondary modiﬁer key similar to shift. For instance, key C1 is
equated to the letter a and its Unicode character code in the typical U.K. keyboard is a non-shifted character
code of 0x0061. When holding down the Alt-GR key in conjunction with the pressing of key C1, , the value on
the same keyboard often produces an á, which is a character code 0x00E1.
Base Code (BC) The PXE Base Code, included as a core protocol in EFI, is comprised of a simple network stack
(UDP/IP) and a few common network protocols (DHCP, Bootserver Discovery, TFTP) that are useful for remote
booting machines.
BC See Base Code (BC)
Big Endian A memory architecture in which the low-order byte of a multibyte datum is at the highest address, while
the high-order byte is at the lowest address. See Little Endian.
BIOS Boot Speciﬁcation Device Path A Device Path that is used to point to boot legacy operating systems; it is
based on the BIOS Boot Speciﬁcation, Version 1.01.
BIOS Parameter Block (BPB) The ﬁrst block (sector) of a partition. It deﬁnes the type and location of the FAT File
System on a drive.
BIOS Basic Input/Output System. A collection of low-level I/O service routines.
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Block I/O Protocol A protocol that is used during boot services to abstract mass storage devices. It allows boot
services code to perform block I/O without knowing the type of a device or its controller.
Block Size The fundamental allocation unit for devices that support the Block I/O Protocol. Not less than 512 bytes.
This is commonly referred to as sector size on hard disk drives.
Boot Device The Device Handle that corresponds to the device from which the currently executing image was loaded.
Boot Manager The part of the ﬁrmware implementation that is responsible for implementing system boot policy.
Although a particular boot manager implementation is not speciﬁed in this document, such code is generally
expected to be able to enumerate and handle transfers of control to the available OS loaders as well as UEFI
applications and drivers on a given system. The boot manager would typically be responsible for interacting
with the system user, where applicable, to determine what to load during system startup. In cases where user
interaction is not indicated, the boot manager would determine what to load and, if multiple items are to be
loaded, what the sequencing of such loads would be.
This is commonly referred to as sector size on disk drives.
Boot Services Table A table that contains the ﬁrmware entry points for accessing boot services functions such as
Task Priority Services and Memory Allocation Services. The table is accessed through a pointer in the System
Table.
Boot Services Time The period of time between platform initialization and the call to ExitBootServices(). During
this time, UEFI Driver and applications are loaded iteratively and the system boots from an ordered list of EFI
OS loaders.
Boot Services The collection of interfaces and protocols that are present in the boot environment. The services
minimally provide an OS loader with access to platform capabilities required to complete OS boot. Services are
also available to drivers and applications that need access to platform capability. Boot services are terminated
once the operating system takes control of the platform.
BPB See BIOS Parameter Block (BPB).
BTT Block Translation Table: A software mechanism for adding single block write atomicity to any Block Mode
ranges or byte-addressable Persistent Memory ranges.
Callback Target function which augments the Forms Processor’s ability to evaluate or process conﬁguration settings.
Callbacks are not available when the Forms Processor is operating in a Disconnected state.
CIM See Common Information Model (CIM).
Cluster A collection of disk sectors. Clusters are the basic storage units for disk ﬁles. See File Allocation Table
(FAT).
COFF Common Object File Format, a standard ﬁle format for binary images.
Coherency Domain
(1) The global set of resources that is visible to at least one processor in a platform.
(2) The address resources of a system as seen by a processor. It consists of both system memory and I/O
space.
Common Information Model (CIM) An object-oriented schema deﬁned by the DMTF. CIM is an information
model that provides a common way to describe and share management information enterprise-wide.
Console I/O Protocol A protocol that is used during Boot Services to handle input and output of text-based informa-
tion intended for the system administrator. It has two parts, a Simple Input Protocol that is used to obtain input
from the ConsoleIn device and a Simple Text Output Protocol that is used to control text-based output devices.
The Console I/O Protocol is also known as the EFI Console I/O Protocol.
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ConsoleIn The device handle that corresponds to the device used for user input in the boot services environment.
Typically the system keyboard.
ConsoleOut The device handle that corresponds to the device used to display messages to the user from the boot
services environment. Typically a display screen.
DBCS Double Byte Character Set.
Desktop Management Interface (DMI)
A platform management information framework, built by the DMTF and designed to provide manageability for
desktop and server computing platforms by providing an interface that is:
(1) independent of any speciﬁc desktop operating system, network operating system, network protocol,
management protocol, processor, or hardware platform;
(2) easy for vendors to implement; and
(3) easily mapped to higher-level protocols.
DMTF (formerly Desktop Management Task Force) The DMTF is a standards organization comprised of compa-
nies from all areas of the computer industry. DMTF creates open manageability standards spanning diverse
emerging and traditional IT infrastructures including cloud, virtualization, network, servers and storage.
Device Handle A handle points to a list of one or more protocols that can respond to requests for services for a given
device referred to by the handle.
Device I/O Protocol A protocol that is used during boot services to access memory and I/O. Also called the EFI
Device I/O Protocol.
Device Path Instance When an environment variable represents multiple devices, it is possible for a device path to
contain multiple device paths. An example of this would be the ConsoleOut environment variable that consists

of both a VGA console and a serial output console. This environment variable would describe a console output
stream that would send output to both devices and therefore has a Device Path that consists of two complete
device paths. Each of these paths is a device path instance.
Device Path Node A variable-length generic data structure that is used to build a device path. Nodes are distinguished
by type, subtype, length, and path-speciﬁc data. See Device Path.
Device Path Protocol A protocol that is used during boot services to provide the information needed to construct and
manage Device Paths. Also called the EFI Device Path Protocol.
Device Path A variable-length binary data structure that is composed of variable-length generic device path nodes
and is used to deﬁne the programmatic path to a logical or physical device. There are six major types of device
paths: Hardware Device Path, ACPI Device Path, Messaging Device Path, Media Device Path, BIOS Boot
Speciﬁcation Device Path, and End of Hardware Device Path.
DHCP See Dynamic Host Conﬁguration Protocol (DHCP).
Disconnected The state when a Forms Processor is manipulating a form set without being connected to the Target’s
pre-OS environment. For example, after booting an OS, a Forms Processor cannot execute call-backs or read
the conﬁguration settings. For example, when running a Forms Browser while on a remote machine that is
not connected to the Target. In these cases, the Forms Processor has limited knowledge of the Target’s current
conﬁguration settings and limited or no ability to use call-backs.
Disk I/O Protocol A protocol that is used during boot services to abstract Block I/O devices to allow non-block-sized
I/O operations. Also called the EFI Disk I/O Protocol.
DMI See DBCS.
DMTF See DMTF (formerly Desktop Management Task Force).
DNS Domain Name System. A protocol used manipulating and translating hostname and IP address
DTLS Datagram Transport Layer Security. A protocol to provide communication privacy above UDP.
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Dynamic Host Conﬁguration Protocol (DHCP) A protocol that is used to get information from a conﬁguration
server. DHCP is deﬁned by the DMTF (formerly Desktop Management Task Force), not EFI.
EAP Extensible Authentication Protocol. An authentication framework which supports multiple authentication meth-
ods
EBC Image Executable EBC image following the PE32 ﬁle format.
EBC See EFI Byte Code (EBC).
EFI Extensible Firmware Interface. An interface between the operating system (OS) and the platform ﬁrmware.
EFI Byte Code (EBC) The binary encoding of instructions as output by the EBC C compiler and linker. The EBC
Image is executed by the interpreter.
EFI File A container consisting of a number of blocks that holds an image or a data ﬁle within a ﬁle system that
complies with this speciﬁcation.
EFI Hard Disk A hard disk that supports the new EFI partitioning scheme (GUID Partition).
EFI-compliant Refers to a platform that complies with this speciﬁcation.
EFI-conformant See EFI-compliant.
End of Hardware Device Path A Device Path which, depending on the subtype, is used to indicate the end of the
Device Path instance or Device Path structure.
Enhanced Mode (EM) The 64-bit architecture extension that makes up part of the Intel® Itanium® architecture.
Event Services The set of functions used to manage events. Includes EFI_BOOT_SERVICES.CheckEvent(),
EFI_BOOT_SERVICES.CreateEvent(), EFI_BOOT_SERVICES.CloseEvent(),
EFI_BOOT_SERVICES.SignalEvent(), and EFI_BOOT_SERVICES.WaitForEvent().
Event An EFI data structure that describes an “event”—for example, the expiration of a timer.
Event Services The set of functions used to manage events.Includes EFI_BOOT_SERVICES.CheckEvent(),
FAT File System The ﬁle system on which the EFI File system is based. See File Allocation Table (FAT) and GUID
Partition Table (GPT).
FAT See File Allocation Table (FAT).
File Allocation Table (FAT) A table that is used to identify the clusters that make up a disk ﬁle. File allocation tables
come in three ﬂavors: FAT12, which uses 12 bits for cluster numbers; FAT16, which uses 16 bits; and FAT32,
which allots 32 bits but only uses 28 (the other 4 bits are reserved for future use).
File Handle Protocol A component of the File System Protocol. It provides access to a ﬁle or directory. Also called
the EFI File Handle Protocol.
File System Protocol A protocol that is used during boot services to obtain ﬁle-based access to a device. It has two
parts, a Simple File System Protocol that provides a minimal interface for ﬁle-type access to a device, and a File
Handle Protocol that provides access to a ﬁle or directory.
Firmware Any software that is included in read-only memory (ROM).
Font A graphical representation corresponding to a character set, in this case Unicode. For more information and
examples, see https://en.wikipedia.org/wiki/Font.
Font glyph The individual elements of a font corresponding to single characters are called font glyphs or simply
glyphs. The ﬁrst character in each of the above three lines is a glyph for the letter “A” in three different fonts.
Form Logical grouping of questions with a unique identiﬁer.
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Form Set An HII database package describing a group of forms, including one parent form and zero or more child
forms.
Forms Browser A Forms Processor capable of displaying the user-interface information a display and interacting
with a user.
Forms Processor An application capable of reading and processing the forms data within a forms set.
Globally Unique Identiﬁer (GUID) A 128-bit value used to differentiate services and structures in the boot services
environment. The format of a GUID is deﬁned in Appendix A. See Protocol.
Glyph The individual elements of a font corresponding to single characters. May also be called font keyboard layout
glyphs. Also see font glyph above.
GPT See GUID Partition Table (GPT).
GPT disk layout: The data layout on a disk consisting of a protective MBR in LBA 0, a GPT Header in LBA 1, and
additional GPT structures and partitions in the remaining LBAs. See chapter 5.
GPTHeader The header in a GUID Partition Table (GPT). Among other things, it contains the number of GPT
Partition Entries and the ﬁrst and last LBAs that can be used for the entries.
GPT Partition Entry A data structure that characterizes a Partition in the GPT disk layout. Among other things, it
speciﬁes the starting and ending LBA of the partition.
GUID Partition Table (GPT) A data structure that describes one or more partitions. It consists of a GPTHeader and,
typically, at least one GPTPartition Entry. There are two GUID partition tables: the Primary Partition Table
(located in LBA 1 of the disk) and a Backup Partition Table (located in the last LBA of the disk). The Backup
Partition Table is a copy of the Primary Partition Table.
GPTPartition Entry A data structure that characterizes a GUID Partition. Among other things, it speciﬁes the start-
ing and ending LBA of the partition.
GUID Partition A contiguous group of sectors on an EFI Hard Disk.
Handle See Device Handle.
Hardware Device Path A Device Path that deﬁnes how a hardware device is attached to the resource domain of a
system (the resource domain is simply the shared memory, memory mapped I/O, and I/O space of the system).
HII Human Interface Infrastructure.
HII Database The centralized repository for HII-related information, organized as package lists.
HTML Hypertext Markup Language. A particular implementation of SGML focused on hypertext applications.
HTML is a fairly simple language that enables the description of pages (generally Internet pages) that include
links to other pages and other data types (such as graphics). When applied to a larger world, HTML has many
shortcomings, including localization (q.v.) and formatting issues. The HTML form concept is of particular
interest to this application.
HTTP Hypertext transfer protocol. HTTP functions as request-response protocol in the client-server computing rule.
IA-32 See Intel® Architecture-32 (IA-32).
IFR Internal Form Representation. Used to represent forms in EFI so that it can be interpreted as is or expanded
easily into XHTML.
Image Handle A handle for a loaded image; image handles support the loaded image protocol.
Image Handoff State The information handed off to a loaded image as it begins execution; it consists of the image’s
handle and a pointer to the image’s system table.
Image Header The initial set of bytes in a loaded image. They deﬁne the image’s encoding.
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Image Services The set of functions used to manage EFI images. Includes EFI_BOOT_SERVICES.LoadImage(),
EFI_BOOT_SERVICES.StartImage(), EFI_BOOT_SERVICES.UnloadImage(),

EFI_BOOT_SERVICES.Exit(), EFI_BOOT_SERVICES.ExitBootServices(), and
EFI_IMAGE_ENTRY_POINT.
Image
(1) An executable ﬁle stored in a ﬁle system that complies with this speciﬁcation. Images may be drivers,
applications or OS loaders. Also called an EFI Image.
(2) Executable binary ﬁle containing EBC and data. Output by the EBC linker.
IME Input Method Editor. A program or subprogram that is used to map keystrokes to logographic characters. For
example, IMEs are used (possibly with user intervention) to map the Kana (Hirigana or Katakana) characters on
Japanese keyboards to Kanji.
Intel® Architecture-32 (IA-32) The 32-bit and 16-bit architecture described in the Intel Architecture Software De-
veloper’s Manual. IA-32 is the architecture of the Intel® P6 family of processors, which includes the Intel®
Pentium® Pro, Pentium II, Pentium III, and Pentium 4 processors.
Intel® Itanium® Architecture The Intel architecture that has 64-bit instruction capabilities, new performance-
enhancing features, and support for the IA-32 instruction set. This architecture is described in the Itanium™
Architecture Software Developer’s Manual.
internationalization In this context, is the process of making a system usable across languages and cultures by
using universally understood symbols. Internationalization is difﬁcult due to the differences in cultures and the
difﬁculty of creating obvious symbols; for example, why does a red octagon mean “Stop”?
Interpreter The software implementation that decodes EBC binary instructions and executes them on a VM. Also
called EBC interpreter.
Keyboard layout The physical representation of a user’s keyboard. The usage of this is in conjunction to a structure
that equates the physical key(s) and the associated action it represents. For instance, key C1 is equated to the
letter a and its Unicode value in the typical U.K. keyboard is a non-shifted value of 0x0061.
LAN On Motherboard (LOM) This is a network device that is built onto the motherboard (or baseboard) of the
machine.
LBA: See Logical Block Address (LBA).
Legacy Platform A platform which, in the interests of providing backward-compatibility, retains obsolete technol-
ogy.
LFN See Long File Names (LFN).
Little Endian A memory architecture in which the low-order byte of a multibyte datum is at the lowest address, while
the high-order byte is at the highest address. See Big Endian.
Load File Protocol A protocol that is used during boot services to ﬁnd and load other modules of code.
Loaded Image Protocol A protocol that is used during boot services to obtain information about a loaded image.
Also called the EFI Loaded Image Protocol.
Loaded Image A ﬁle containing executable code. When started, a loaded image is given its image handle and can
use it to obtain relevant image data.
Localization The process of focusing a system in so that it works using the symbols of a language/culture. To a major
extent the following design is inﬂuenced by the requirements of localization.
Logical Block Address (LBA): The address of a logical block on a disk. The ﬁrst LBA on a disk is LBA 0.
Logographic A character set that uses characters to represent words or parts of words rather than syllables or sounds.
Kanji is logographic but Kana characters are not.
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LOM See LAN On Motherboard (LOM).
Long File Names (LFN) Refers to an extension to the FAT File System that allows ﬁle names to be longer than the
original standard (eight characters plus a three-character extension).
Machine Check Abort (MCA) The system management and error correction facilities built into the Intel Itanium
processors.
Master Boot Record (MBR) The data structure that resides on the LBA 0 of a hard disk and deﬁnes the partitions on
the disk.
MBR See Master Boot Record (MBR).
MBR boot code: x86 code in the ﬁrst LBA of a disk.
MBR disk layout: The data layout on a disk consisting of an MBR in LBA 0 and partitions described by the MBR in
the remaining LBAs. See chapter 5 and Appendix NEW.
MBR Partition Record A data structure that characterizes a Partition in the MBR disk layout.
MCA See Machine Check Abort (MCA).
Media Device Path A Device Path that is used to describe the portion of a medium that is being abstracted by a boot
service. For example, a Media Device Path could deﬁne which partition on a hard drive was being used.
Memory Allocation Services The set of functions used to allocate and free memory, and to retrieve the
memory map. Includes EFI_BOOT_SERVICES.AllocatePages(), EFI_BOOT_SERVICES.FreePages(),
EFI_BOOT_SERVICES.AllocatePool(), EFI_BOOT_SERVICES.FreePool(), and
EFI_BOOT_SERVICES.GetMemoryMap().
Memory Map A collection of structures that deﬁnes the layout and allocation of system memory during the boot
process. Drivers and applications that run during the boot process prior to OS control may require memory. The
boot services implementation is required to ensure that an appropriate representation of available and allocated
memory is communicated to the OS as part of the hand-off of control.
Memory Type One of the memory types deﬁned by UEFI for use by the ﬁrmware and UEFI applications. Among
others, there are types for boot services code, boot services data, Runtime Services code, and runtime services
data. Some of the types are used for one purpose before EFI_BOOT_SERVICES.ExitBootServices() is called
and another purpose after.
Messaging Device Path A Device Path that is used to describe the connection of devices outside the Coherency
Domain of the system. This type of node can describe physical messaging information (e.g., a SCSI ID) or
abstract information (e.g., networking protocol IP addresses).
Miscellaneous Service Various functions that are needed to support the EFI environment. Includes
EFI_BOOT_SERVICES.InstallConﬁgurationTable(), ResetSystem(), EFI_BOOT_SERVICES.Stall(),
EFI_BOOT_SERVICES.SetWatchdogTimer(), EFI_BOOT_SERVICES.GetNextMonotonicCount(), and
GetNextHighMonotonicCount().
MTFTP See Multicast Trivial File Transfer Protocol (MTFTP).
Multicast Trivial File Transfer Protocol (MTFTP) A protocol used to download a Network Boot Program to many
clients simultaneously from a TFTP server.
Name Space or Namespace A namespace deﬁnes a contiguously-addressed range of Non-V olatile Memory concep-
tually similar to a SCSI Logical Unit (LUN) or a NVM Express namespace. In general, a collection of device
paths; in an EFI Device Path.
Native Code Low level instructions that are native to the host processor. As such, the processor executes them directly
with no overhead of interpretation. Contrast this with EBC, which must be interpreted by native code to operate
on a VM.
NBP See Network Bootstrap Program (NBP) or Network Boot Program.
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Network Boot Program A remote boot image downloaded by a PXE client using the Trivial File Transport Protocol
(TFTP) or the Multicast Trivial File Transfer Protocol (MTFTP). See Network Bootstrap Program (NBP).
Network Bootstrap Program (NBP) This is the ﬁrst program that is downloaded into a machine that has selected a
PXE capable device for remote boot services. A typical NBP examines the machine it is running on to try to
determine if the machine is capable of running the next layer (OS or application). If the machine is not capable
of running the next layer, control is returned to the EFI boot manager and the next boot device is selected. If the
machine is capable, the next layer is downloaded and control can then be passed to the downloaded program.
Though most NBPs are OS loaders, NBPs can be written to be standalone applications such as diagnostics,
backup/restore, remote management agents, browsers, etc.
Network Interface Card (NIC) Technically, this is a network device that is inserted into a bus on the motherboard or
in an expansion board. For the purposes of this document, the term NIC will be used in a generic sense, meaning
any device that enables a network connection - including LOMs and network devices on external buses (USB,
1394, etc.).
NIC See Network Interface Card (NIC).
Non-spacing key Typically an accent key that does not advance the cursor and is used to create special characters
similar to ÄäÊê. This function is provided only on certain keyboard layouts.
NV Nonvolatile.
Package HII information with a unique type, such as strings, fonts, images or forms.
Package List Group of packages identiﬁed by a GUID.
Page Memory A set of contiguous pages. Page memory is allocated by EFI_BOOT_SERVICES.AllocatePages() and
returned by EFI_BOOT_SERVICES.FreePages().
Partition Discovery The process of scanning a block device to determine whether it contains a Partition.
Partition A contiguous set of LBAs on a disk, described by the MBR and/or GPT disk layouts.
PC-AT Refers to a PC platform that uses the AT form factor for their motherboards.
PCI Bus Driver Software that creates a handle for every PCI Controller on a PCI Host Bus Controller and installs

both the PCI I/O Protocol and the Device Path Protocol onto that handle. It may optionally perform PCI Enu-
meration if resources have not already been allocated to all the PCI Controllers on a PCI Host Bus Controller.
It also loads and starts any UEFI drivers found in any PCI Option ROMs discovered during PCI Enumeration.
If a driver is found in a PCI Option ROM, the PCI Bus Driver will also attach the Bus Speciﬁc Driver Override
Protocol to the handle for the PCI Controller that is associated with the PCI Option ROM that the driver was
loaded from.
PCI Bus A collection of up to 32 physical PCI Devices that share the same physical PCI bus. All devices on a PCI
Bus share the same PCI Conﬁguration Space.
PCI Conﬁguration Space The conﬁguration channel deﬁned by PCI to conﬁgure PCI Devices into the resource do-
main of the system. Each PCI device must produce a standard set of registers in the form of a PCI Conﬁguration
Header, and can optionally produce device speciﬁc registers. The registers are addressed via Type 0 or Type 1
PCI Conﬁguration Cycles as described by the PCI Speciﬁcation. The PCI Conﬁguration Space can be shared
across multiple PCI Buses. On most PC-AT architecture systems and typical Intel® chipsets, the PCI Conﬁgu-
ration Space is accessed via I/O ports 0xCF8 and 0xCFC. Many other implementations are possible.
PCI Controller A hardware components that is discovered by a PCI Bus Driver, and is managed by a PCI Device
Driver. PCI Functions and PCI Controller are used equivalently in this document.
PCI Device Driver Software that manages one or more PCI Controllers of a speciﬁc type. A driver will use the
PCI I/O Protocol to produce a device I/O abstraction in the form of another protocol (i.e., Block I/O, Simple
Network, Simple Input, Simple Text Output, Serial I/O, Load File).
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PCI Devices A collection of up to 8 PCI Functions that share the same PCI Conﬁguration Space. A PCI Device is
physically connected to a PCI Buses.
PCI Enumeration The process of assigning resources to all the PCI Controllers on a given PCI Host Bus Controller.
This includes PCI Bus Number assignments, PCI Interrupt assignments, PCI I/O resource allocation, the PCI
Memory resource allocation, the PCI Prefetchable Memory resource allocation, and miscellaneous PCI DMA
settings.
PCI Functions A controller that provides some type of I/O services. It consumes some combination of PCI I/O, PCI
Memory, and PCI Prefetchable Memory regions, and up to 256 bytes of the PCI Conﬁguration Space. The PCI
Function is the basic unit of conﬁguration for PCI.
PCI Host Bus Controller A chipset component that produces PCI I/O, PCI Memory, and PCI Prefetchable Memory
regions in a single Coherency Domain. A PCI Host Bus Controller is composed of one or more PCI Root
Bridges.
PCI I/O Protocol A software interface that provides access to PCI Memory, PCI I/O, and PCI Conﬁguration spaces
for a PCI Controller. It also provides an abstraction for PCI Bus Master DMA.
PCI Option ROM A ROM device that is accessed through a PCI Controller, and is described in the PCI Controller’s
Conﬁguration Header. It may contain one or more PCI Device Drivers that are used to manage the PCI Con-
troller.
PCI Root Bridge I/O Protocol A software abstraction that provides access to the PCI I/O, PCI Memory, and PCI
Prefetchable Memory regions in a single Coherency Domain.
PCI Root Bridge A chipset component(s) that produces a physical PCI Local Bus.
PCI Segment A collection of up to 256 PCI Buses that share the same PCI Conﬁguration Space. PCI Seg-
ment is deﬁned in the ACPI Speciﬁcation as the _SEG object. The SAL_PCI_CONFIG_READ and
SAL_PCI_CONFIG_WRITE procedures deﬁned in chapter 9 of the SAL Speciﬁcation deﬁne how to access
the PCI Conﬁguration Space in a system that supports multiple PCI Segments. If a system only supports a
single PCI Segment the PCI Segment number is deﬁned to be zero. The existence of PCI Segments enables the
construction of systems with greater than 256 PCI buses.
Pool Memory A set of contiguous bytes. A pool begins on, but need not end on, an “8-byte” boundary. Pool
memory is allocated in pages—that is, ﬁrmware allocates enough contiguous pages to contain the number
of bytes speciﬁed in the allocation request. Hence, a pool can be contained within a single page or extend
across multiple pages. Pool memory is allocated by EFI_BOOT_SERVICES.AllocatePool() and returned by
Preboot Execution Environment (PXE)
A means by which agents can be loaded remotely onto systems to perform management tasks in the absence of
a running OS. To enable the interoperability of clients and downloaded bootstrap programs, the client preboot
code must provide a set of services for use by a downloaded bootstrap. It also must ensure certain aspects of
the client state at the point in time when the bootstrap begins executing.
Client
- Makes network devices into bootable devices.
- Provides APIs for PXE protocol modules in EFI and for universal drivers in the OS.
Network
- Uses existing technology: DHCP, TFTP, etc.
- Adds “vendor-speciﬁc” tags to DHCP to deﬁne PXE-speciﬁc operation within DHCP.
- Adds multicast TFTP for high bandwidth remote boot applications.
- Deﬁnes Bootserver discovery based on DHCP packet format.
2057Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Server
- Bootserver: Responds to Bootserver discovery requests and serves up remote boot images.
- proxyDHCP: Used to ease the transition of PXE clients and servers into existing network infrastructure.
proxyDHCP provides the additional DHCP information that is needed by PXE clients and Bootservers without
making changes to existing DHCP servers.
- Plug-In Modules: Example proxyDHCP and Bootservers provided in the PXE SDK (software development
kit) have the ability to take plug-in modules (PIMs). These PIMs are used to change/enhance the capabilities of
the proxyDHCP and Bootservers.
Protocol Handler Services The set of functions used to manipulate handles, protocols,
and protocol interfaces. Includes EFI_BOOT_SERVICES.InstallProtocolInterface(),
EFI_BOOT_SERVICES.UninstallProtocolInterface(), EFI_BOOT_SERVICES.ReinstallProtocolInterface(),
EFI_BOOT_SERVICES.HandleProtocol(), EFI_BOOT_SERVICES.RegisterProtocolNotify(),
EFI_BOOT_SERVICES.LocateHandle(), and EFI_BOOT_SERVICES.LocateDevicePath().
Protocol Handler A function that responds to a call to a HandleProtocol request for a given handle. A protocol
handler returns a protocol interface structure.
Protocol Interface Structure The set of data deﬁnitions and functions used to access a particular type of device.
For example, BLOCK_IO is a protocol that encompasses interfaces to read and write blocks from mass storage
devices. See Protocol.
Protocol Revision Number The revision number associated with a protocol. See Protocol.
Protocol The information that deﬁnes how to access a certain type of device during boot services. A protocol consists
of a Globally Unique Identiﬁer (GUID), a protocol revision number, and a protocol interface structure. The
interface structure contains data deﬁnitions and a set of functions for accessing the device. A device can have
multiple protocols. Each protocol is accessible through the device’s handle.
PXE Base Code Protocol A protocol that is used to control PXE-compatible devices. It may be used by the
ﬁrmware’s boot manager to support booting from remote locations. Also called the EFI PXE Base Code Proto-
col.
PXE See Preboot Execution Environment (PXE).
Question IFR which describes how a single conﬁguration setting should be presented, stored, and validated.
Read-Only Memory (ROM) When used with reference to the UNDI speciﬁcation, ROM refers to a nonvolatile mem-
ory storage device on a NIC.
Reset The action which forces question values to be reset to their defaults.
ROM See Question.
Runtime Services Table A table that contains the ﬁrmware entry points for accessing runtime services functions such
as Time Services and Virtual Memory Services. The table is accessed through a pointer in the System Table.
Runtime Services Interfaces that provide access to underlying platform speciﬁc hardware that may be useful during
OS runtime, such as timers. These services are available during the boot process but also persist after the OS
loader terminates boot services.
SAL See System Abstraction Layer (SAL).
scan code A value representing the location of a key on a keyboard. Scan codes may also encode make (key press)
and break (key release) and auto-repeat information.
Serial Protocol A Protocol that is used during boot services to abstract byte stream devices-that is, to communicate
with character-based I/O devices.
SGML Standard Generalized Markup Language. A markup language for deﬁning markup languages.
2058Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10

shifted Unicode Shifted Unicode represents the Unicode character code of a key when the shift modiﬁer key is held
down. For instance, key C1 is equated to the letter a and its Unicode character code in the typical U.K. keyboard
is a non-shifted value of 0x0061. When the shift key is held down in conjunction with the pressing of key C1,
however, the value on the same keyboard often produces an A, which is a the Unicode character code 0x0041.
A Protocol that is used during boot services to abstract byte stream devices—that is, to communicate with
character-based I/O devices.
Simple File System Protocol A component of the File System Protocol. It provides a minimal interface for ﬁle-type
access to a device.
Simple Input Protocol A protocol that is used to obtain input from the ConsoleIn device. It is one of two protocols
that make up the Console I/O Protocol.
Simple Network Protocol A protocol that is used to provide a packet-level interface to a network adapter. Also called
the EFI Simple Network Protocol.
Simple Text Output Protocol A protocol that is used to control text-based output devices. It is one of two protocols
SKU Stock keeping unit. An acronym commonly used to reference a “version” of a particular platform. An example
might be “We have three different SKUs of this platform.”
SMBIOS See System Management BIOS (SMBIOS).
SNIA Storage Network Industry Association.(www.snia.org)
SNIA Common RAID Disk Data Format Storage Network Industry Association Common RAID Disk Data Format
Speciﬁcation, Revision 1.2, July 28, 2006. (www.snia.org)
SSL Secure Sockets Layer. A security protocol that provides communications privacy over the Internet. It is prede-
cessor to TLS.
StandardError The device handle that corresponds to the device used to display error messages to the user from the
boot services environment.
Status Codes Success, error, and warning codes returned by boot services and runtime services functions.
string A null-terminated array of 16-bit UCS-2 encoded Unicode characters. All strings in this speciﬁcation are
encoded using UCS-2 unless otherwise speciﬁed.
Submit The action which forces modiﬁed question values to be written back to storage.
System Abstraction Layer (SAL) Firmware that abstracts platform implementation differences, and provides the
basic platform software interface to all higher level software.
System Management BIOS (SMBIOS) A table-based interface that is required by the Wired for Management Base-
line Speciﬁcation. It is used to relate platform-speciﬁc management information to the OS or to an OS-based
management agent.
System Table Table that contains the standard input and output handles for a UEFI application, as well as pointers to
the boot services and runtime services tables. It may also contain pointers to other standard tables such as the
ACPI, SMBIOS, and SAL System tables. A loaded image receives a pointer to its system table when it begins
execution. Also called the EFI System Table.
Target The system being conﬁgured.
Task Priority Level (TPL) The boot services environment exposes three task priority levels: “normal,” “callback,”
and “notify.”
Task Priority Services The set of functions used to manipulate task priority levels. Includes
EFI_BOOT_SERVICES.RaiseTPL() and EFI_BOOT_SERVICES.RestoreTPL().
TFTP See Trivial File Transport Protocol (TFTP).
2059Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
Time Format The format for expressing time in an EFI-compliant platform. For more information, see Appendix A.
Time Services The set of functions used to manage time. Includes GetTime(), SetTime(), GetWakeupTime(), and
SetWakeupTime().
Timer Services The set of functions used to manipulate timers. Contains a single function,
EFI_BOOT_SERVICES.SetTimer().
TLS Transport Layer Security. A protocol to provide privacy and data integrity between two communicating applica-
tions above TCP.
TPL See Target.
Trivial File Transport Protocol (TFTP) A protocol used to download a Network Boot Program from a TFTP server.
UEFI Uniﬁed Extensible Firmware Interface. The interface between the operating system (OS) and the platform
ﬁrmware deﬁned by this speciﬁcation.
UEFI Application Modular code that may be loaded in the boot services environment to accomplish platform spe-
ciﬁc tasks within that environment. Examples of possible applications might include diagnostics or disaster
recovery tools shipped with a platform that run outside the OS environment. UEFI applications may be loaded
in accordance with policy implemented by the platform ﬁrmware to accomplish a speciﬁc task. Control is then
returned from the UEFI application to the platform ﬁrmware.
UEFI Boot Service Driver A UEFI driver that is loaded into boot services memory and stays resident until boot
services terminate.
UEFI Driver A module of code typically inserted into the ﬁrmware via protocol interfaces. Drivers may provide
device support during the boot process or they may provide platform services. It is important not to confuse
UEFI drivers with OS drivers that load to provide device support once the OS takes control of the platform.
UEFI OS Loader A UEFI application that is the ﬁrst piece of operating system code loaded by the ﬁrmware to
initiate the OS boot process. This code is loaded at a ﬁxed address and then executed. The OS takes control of
the system prior to completing the OS boot process by calling the interface that terminates all boot services.
UEFI Runtime Services Driver A UEFI driver that is loaded into runtime services memory and stays resident during
runtime.
Unaccepted Memory Some Virtual Machine platforms, such as AMD SEV-SNP, introduce the concept of memory
acceptance, requiring memory to be accepted before it can be used by the guest. This protects against a class of
attacks by the virtual machine platform.
UNDI See Universal Network Device Interface (UNDI).
Unicode Collation Protocol A protocol that is used during boot services to perform case-insensitive comparisons of
strings.
Unicode An industry standard internationalized character set used for human readable message display.
Universal Network Device Interface (UNDI) UNDI is an architectural interface to NICs. Traditionally NICs have
had custom interfaces and custom drivers (each NIC had a driver for each OS on each platform architecture).
Two variations of UNDI are deﬁned in this speciﬁcation: H/W UNDI and S/W UNDI. H/W UNDI is an archi-
tectural hardware interface to a NIC. S/W UNDI is a software implementation of the H/W UNDI.
Universal Serial Bus (USB) A bi-directional, isochronous, dynamically attachable serial interface for adding periph-
eral devices such as serial ports, parallel ports, and input devices on a single bus.
URI Uniform resource identiﬁer. URI is a string of characters used to identify a name of a resource.
USB Bus Driver Software that enumerates and creates a handle for each newly attached USB Controller and installs
both the USB I/O Protocol and the Device Path Protocol onto that handle, starts that device driver if applicable.
For each newly detached USB Controller, the device driver is stopped, the USB I/O Protocol and the Device
Path Protocol are uninstalled from the device handle, and the device handle is destroyed.
2060Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation, Release 2.10
USB Bus A collection of up to 127 physical USB Devices that share the same physical USB bus. All devices on a
USB Bus share the bandwidth of the USB Bus.
USB Controller A hardware component that is discovered by a USB Bus Driver, and is managed by a USB Device
Driver. USB Interface and USB Controller are used equivalently in this document.
USB Device Driver Software that manages one or more USB Controller of a speciﬁc type. A driver will use the
USB I/O Protocol to produce a device I/O abstraction in the form of another protocol (i.e., Block I/O, Simple
USB Device A USB peripheral that is physically attached to the USB Bus.
USB Enumeration A periodical process to search the USB Bus to detect if there have been any USB Controller
attached or detached. If an attach event is detected, then the USB Controllers device address is assigned, and a
child handle is created. If a detach event is detected, then the child handle is destroyed.
USB Host Controller Moves data between system memory and devices on the USB Bus by processing data structures
and generating the USB transactions. For USB 1.1, there are currently two types of USB Host Controllers: UHCI
and OHCI.
USB Hub A special USB Device through which more USB devices can be attached to the USB Bus.
USB I/O Protocol A software interface that provides services to manage a USB Controller, and services to move data
between a USB Controller and system memory.
USB Interface The USB Interface is the basic unit of a physical USB Device.
USB See Universal Serial Bus (USB).
Variable Services The set of functions used to manage variables. Includes GetVariable(), SetVariable(), and Get-
NextVariableName().

and OHCI.
Virtual Memory Services The set of functions used to manage virtual memory. Includes SetVirtualAddressMap()
and ConvertPointer().
VM The Virtual Machine, a pseudo processor implementation consisting of registers which are manipulated by the
interpreter when executing EBC instructions.
Watchdog Timer An alarm timer that may be set to go off. This can be used to regain control in cases where a code
path in the boot services environment fails to or is unable to return control by the expected path.
WfM See Wired for Management (WfM).
Wired for Management (WfM) Refers to the Wired for Management Baseline Speciﬁcation. The Speciﬁcation de-
ﬁnes a baseline for system manageability issues; its intent is to help lower the cost of computer ownership.
x64 Processors that are compatible with instruction sets and operation modes as exempliﬁed by the AMD64 or Intel®
Extended Memory 64 Technology (Intel® EM64T) architecture.
XHTML Extensible HTML. XHTML “will obey all of the grammar rules of XML (properly nested elements, quoted
attributes, and so on), while conforming to the vocabulary of HTML (the elements and attributes that are avail-
able for use ant their relationships to one another).” [PXML, pg., 153]. Although not completely deﬁned,
XHTML is basically the intersection of XML and HTML and does support forms.
XML Extensible Markup Language. A subset of SGML. Addresses many of the problems with HTML but does not
currently (1.0) support forms in any speciﬁed way.
2061 
. Copyright © 2023  Intel Corporation.  All rights reserved.   
 
Intel® Trust Domain Extensions (Intel® TDX ) Module 
TD Partitioning  Architecture Specification  
 
354807 -002US 
November 2023  
TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 2 of 52 
Section 1:  Introduction and Overview  Notices and Disclaimers  
Intel Corporation (“Intel”) provides these materials as -is, with no express or implied warranties.  
All products, dates, and figures specified are preliminary, based on current expectations, and are subject to change 
without notice.  Intel does not guarantee the availability of these interfaces in any future product .  Contact your Intel 
representative to obtain the latest Intel product specifications and roadmaps.  5 
The products described might contain design defects or errors known as errata, which might cause the product to 
deviate from published specifications.  Current, characterized errata are available on request.  
Intel technologies might require enabled hardware, software, or service activation.  Some results have been estimated 
or simulated.  Your costs and results might vary.  
No product or component can be absolutely secure.  10 
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis 
concerning Intel products described herein.  You agree to grant Intel a non -exclusive, royalty -free license to any patent 
claim thereafter dr afted that includes the subject matter disclosed herein.  
No license (express, implied, by estoppel, or otherwise) to any intellectual -property rights is granted by this document.  
This document contains information on products, services and/or processes in development .  All information provided 15 
here is subject to change without notice.  
Copies of documents that have an order number and are referenced in this document or other Intel literature may be 
obtained by calling 1 -800-548-4725 or by visiting http://www.intel.com/design/literature.htm.  
© Intel Corporation.  Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.  
Other names and brands might be claimed as the property of others.    20 
  TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 3 of 52 
Section 1:  Introduction and Overview  Table of Contents  
SECTION 1: INTRODUCTION AND OVERVIEW  ................................ ................................ ................................ ................  6 
10. About this Document  ................................ ................................ ................................ ................................ ........  7 
10.1.  Scope of this Document  ................................ ................................ ................................ ................................ .... 7 
10.2.  Document Organization  ................................ ................................ ................................ ................................ .... 7 5 
10.3.  Glossary ................................ ................................ ................................ ................................ .............................  8 
10.4.  Notation  ................................ ................................ ................................ ................................ ............................  8 
10.5.  References  ................................ ................................ ................................ ................................ .........................  8 
11. TDX TD Partitioning Overview  ................................ ................................ ................................ ...........................  9 
11.1.  Introduction  ................................ ................................ ................................ ................................ ......................  9 10 
11.2.  Security Properties  ................................ ................................ ................................ ................................ ..........  10 
11.3.  L2 VM Private Memory Management ................................ ................................ ................................ .............  11 
11.4.  L2 VM Transitions  ................................ ................................ ................................ ................................ ...........  11 
11.5.  L2 VM CPU Virtualization  ................................ ................................ ................................ ................................  12 
11.6.  L2 VM Measurement and Attestation ................................ ................................ ................................ .............  12 15 
11.7.  L2 VM Debug  ................................ ................................ ................................ ................................ ...................  12 
11.8.  TD Partitioning Interaction with TD Migration  ................................ ................................ ...............................  12 
11.9.  Intel TDX TD Partitioning Interface Functions  ................................ ................................ ................................ . 13 
11.9.1.  Host -Side (SEAMCALL Leaf) Interface Functions  ................................ ................................ .........................  13 
11.9.2.  Guest -Side (TDCALL Leaf) Interface Functions  ................................ ................................ ............................  13 20 
SECTION 2: TD PARTITIONING ARCHITECTURE SPECIFICATION  ................................ ................................ ....................  14 
20. L2 VM Non -Memory State (Metadata) and Control Structures  ................................ ................................ .........  15 
20.1.  Overview  ................................ ................................ ................................ ................................ .........................  15 
20.1.1.  Opaque L2 Control Structures ................................ ................................ ................................ .....................  15 
20.1.2.  Private Control Structures ................................ ................................ ................................ ...........................  15 25 
20.1.3.  Shared Control Structures  ................................ ................................ ................................ ...........................  15 
20.2.  Additions to Existing TD Control Structures  ................................ ................................ ................................ .... 16 
20.2.1.  TDCS  ................................ ................................ ................................ ................................ ............................  16 
20.2.2.  TDVPS  ................................ ................................ ................................ ................................ ..........................  16 
 New TDVPS Fields  ................................ ................................ ................................ ...............................  16 30 
 New Per -VM TDVPS Fields  ................................ ................................ ................................ ..................  16

 New Per -VM TDVPS Fields  ................................ ................................ ................................ ..................  16 
20.3.  Concurrency Restrictions and Enforcement  ................................ ................................ ................................ .... 17 
21. L2 VM Memory Management  ................................ ................................ ................................ ..........................  18 
21.1.  Introduction  ................................ ................................ ................................ ................................ ....................  18 
21.2.  L2 Page Aliasing  ................................ ................................ ................................ ................................ ..............  19 35 
21.2.1.  Logical View of a TD Private Page with Pages Aliases  ................................ ................................ .................  19 
21.2.2.  L2 Secure EPT Entry Partial State Diagram ................................ ................................ ................................ .. 19 
21.2.3.  L2 Page Alias Management:  TDG.MEM.PAGE.ATTR.RD/WR  ................................ ................................ ..... 20 
 Overview  ................................ ................................ ................................ ................................ .............  20 
 Adding L2 Page Aliases  ................................ ................................ ................................ ........................  21 40 
 Modifying L2 Page Attributes ................................ ................................ ................................ ..............  22 
 Removing L2 Page Aliases  ................................ ................................ ................................ ...................  22 
21.3.  Updates to SEPT Tree Management  ................................ ................................ ................................ ...............  23 
21.3.1.  Host VMM’s L2 SEPT Management Strategy  ................................ ................................ ..............................  23 TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 4 of 52 
Section 1:  Introduction and Overview  21.3.2.  Adding SEPT Pages  ................................ ................................ ................................ ................................ ...... 23 
21.3.3.  Removing SEPT Pages  ................................ ................................ ................................ ................................ . 24 
21.3.4.  Page Demotion  ................................ ................................ ................................ ................................ ...........  24 
21.3.5.  Page Promotion  ................................ ................................ ................................ ................................ ..........  24 
21.4.  Other Updates to Memory Management Interface Functions ................................ ................................ ........  24 5 
21.5.  L1 VMM Control of L2 EPT Features  ................................ ................................ ................................ ................  24 
21.6.  L2 VM TLB Invalidation  ................................ ................................ ................................ ................................ ... 25 
21.7.  L2 VM Shared Memory Management  ................................ ................................ ................................ .............  25 
21.8.  Handling EPT Violation VM Exit from L2  ................................ ................................ ................................ .........  25 
21.9.  Handling EPT Misconfiguration VM Exit from L2  ................................ ................................ ............................  26 10 
21.10.  L2 GPA -to-HPA Soft Translation  ................................ ................................ ................................ ......................  26 
22. TD VCPU Enhancements for TD Partitioning  ................................ ................................ ................................ ..... 27 
22.1.  Overview  ................................ ................................ ................................ ................................ .........................  27 
22.2.  VCPU Transitions  ................................ ................................ ................................ ................................ .............  27 
22.2.1.  L1-to-L2 VM Entry and L2 -to-L1 VM Exit:  TDG.VP.ENTER  ................................ ................................ ..........  27 15 
 TDG.VP.ENTER Inputs and Outputs  ................................ ................................ ................................ ..... 28 
 L2 State Preservation Across L1 -to-L2-to-L1 Transitions (TDG.VP.ENTER)  ................................ .........  29 
 L2 VM Exit Handling  ................................ ................................ ................................ ............................  29 
 L2-to-L1 VM Exit:  Returned L2 State  ................................ ................................ ................................ .. 29 
22.2.2.  Direct Asynchronous TD Exit from L2, and Subsequent TD Entry  ................................ ...............................  30 20 
 Asynchronous TD Exit from L2  ................................ ................................ ................................ ............  30 
 VCPU Resumption to L2 on TD Entry following a TD Exit from L2  ................................ ......................  30 
22.2.3.  TDG.VP.VMCALL:  Synchronous TD Exit from L2 and Subsequent TD Entry  ................................ ...............  30 
22.2.4.  TD Exit from L2 Routed by the Host VMM to L1 on Subsequent TD Entry  ................................ .................  31 
 Asynchronous TD Exit from L2 Routed to L1  ................................ ................................ .......................  31 25 
 Synchronous (TDG.VP.VMCALL) TD Exit from L2 Routed to L1  ................................ ...........................  31 
22.3.  L1 Posted Interrupts Handling for TD Partitioning  ................................ ................................ ..........................  32 
22.3.1.  Overview  ................................ ................................ ................................ ................................ .....................  32 
22.3.2.  Pending L1 Posted Interrupt during L1 -to-L2 Entry  ................................ ................................ ....................  32 
22.3.3.  L1 Posted Interrupt Received during L2 Run Time  ................................ ................................ ......................  33 30 
22.3.4.  L1 Posted Interrupt Received before Host -to-L2 Entry  ................................ ................................ ...............  33 
22.4.  L2 VM TLB Address Space Identifier (ASID)  ................................ ................................ ................................ ..... 34 
23. L2 VM CPU Virtualization (Non -Root Mode Operation)  ................................ ................................ ....................  35 
23.1.  General Aspects of L1 Operation as a VMM  ................................ ................................ ................................ ... 35 
23.1.1.  L1 VMM Usage of VMX Facilities  ................................ ................................ ................................ ................  35 35 
23.1.2.  Enumeration of VMX Capabilities Available to the L1 VMM  ................................ ................................ ...... 35 
23.1.3.  Unit Conversion  ................................ ................................ ................................ ................................ ..........  36 
23.1.4.  L2-to-L1 VM Exit Handling ................................ ................................ ................................ ...........................  37 
23.2.  L2 VM VCPU Initial State  ................................ ................................ ................................ ................................ . 37 
23.3.  L2 VM Run Time Environment Enumeration  ................................ ................................ ................................ ... 37 40 
23.4.  L2 VM CPU Mode Restrictions  ................................ ................................ ................................ .........................  37 
23.5.  L2 VM VCPU Instructions Restrictions  ................................ ................................ ................................ .............  38 
23.5.1.  Mechanisms of Blocking  ................................ ................................ ................................ .............................  38

23.5.1.  Mechanisms of Blocking  ................................ ................................ ................................ .............................  38 
23.5.2.  Instructions that Cause an L2 -to-L1 Exit Unconditionally  ................................ ................................ ...........  38 
23.5.3.  Instructions that Cause a #UD Unconditionally  ................................ ................................ ..........................  38 45 
23.5.4.  Instructions that Cause an L2 -to-L1 Exit  ................................ ................................ ................................ ..... 38 
23.5.5.  Other Cases of Unconditionally Blocked Instructions  ................................ ................................ .................  38 
23.6.  L2 VM Extended Feature Set  ................................ ................................ ................................ ...........................  38 
23.7.  L2 VM CR Handling  ................................ ................................ ................................ ................................ .........  39 TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 5 of 52 
Section 1:  Introduction and Overview  23.7.1.  CR0 and CR4  ................................ ................................ ................................ ................................ ................  39 
 Background:  CR0 and CR4 Execution Controls  ................................ ................................ ...................  39 
 CR0 and CR4 Enumeration to the L1 VMM  ................................ ................................ .........................  39 
 L2 CR0/4 Initial Values  ................................ ................................ ................................ ........................  40 
23.7.2.  CR3 and CR8  ................................ ................................ ................................ ................................ ................  40 5 
23.8.  L2 VM MSR Handling  ................................ ................................ ................................ ................................ ...... 40 
23.9.  L2 VM CPUID Virtualization  ................................ ................................ ................................ ............................  41 
23.10.  L2 VM Interrupt Handling and APIC Virtualization  ................................ ................................ .........................  42 
23.10.1.  L2 Virtual APIC Page Access by the L1 VMM  ................................ ................................ ...........................  43 
23.10.2.  L2 Virtual Local APIC Mode and Access by the L2 VM  ................................ ................................ ............  43 10 
23.10.3.  L2 Posted Interrupts (Not Supported)  ................................ ................................ ................................ .... 43 
23.10.4.  Virtual NMI Injection to L2 VCPU  ................................ ................................ ................................ ............  43 
23.10.5.  Handling NMI Unblocking Due to IRET  ................................ ................................ ................................ .... 43 
23.11.  Vectored Events  ................................ ................................ ................................ ................................ ..............  43 
23.11.1.  Vector -on-Entry (VOE) Injection to L2  ................................ ................................ ................................ .... 43 15 
23.11.2.  L2-to-L1 Exit during Event Delivery via IDT  ................................ ................................ .............................  44 
23.12.  Prevention of L2 VM -Induced Denial of Service  ................................ ................................ ..............................  44 
23.13.  Time Stamp Counter (TSC)  ................................ ................................ ................................ ..............................  44 
23.13.1.  L2 VM TSC Virtualization  ................................ ................................ ................................ .........................  44 
23.13.2.  L2 VM TSC Deadline Support  ................................ ................................ ................................ ..................  44 20 
23.14.  Supervisor Protection Keys (PKS)  ................................ ................................ ................................ .....................  45 
23.15.  Intel ® Total Memory Encryption (Intel ® TME) and Multi -Key Total Memory Encryption (MKTME)  ................  45 
23.15.1.  TME Virtualization  ................................ ................................ ................................ ................................ ... 45 
23.15.2.  MKTME Virtualization  ................................ ................................ ................................ .............................  46 
23.16.  Management of Idle and Blocked Conditions  ................................ ................................ ................................ . 46 25 
23.16.1.  HLT Instruction  ................................ ................................ ................................ ................................ ........  46 
23.16.2.  PAUSE Instruction and PAUSE -Loop Exiting  ................................ ................................ ............................  46 
23.16.3.  MONITOR and MWAIT Instructions  ................................ ................................ ................................ ........  46 
23.16.4.  WAITPKG:  TPAUSE, UMONITOR and UMWAIT Instructions  ................................ ................................ .. 46 
23.17.  Other Changes in TDX Non -Root Mode  ................................ ................................ ................................ ...........  46 30 
23.17.1.  L2 VM Tasking  ................................ ................................ ................................ ................................ .........  46 
23.17.2.  L2 VM PAUSE -Loop Exiting  ................................ ................................ ................................ ......................  47 
24. L2 VM Debug and Profiling Architecture  ................................ ................................ ................................ ..........  48 
24.1.  On-L2 VM Debug  ................................ ................................ ................................ ................................ .............  48 
24.1.1.  Overview  ................................ ................................ ................................ ................................ .....................  48 35 
24.1.2.  Generic Debug Handling  ................................ ................................ ................................ .............................  48 
 Context Switch  ................................ ................................ ................................ ................................ .... 48 
 IA32_DEBUGCTL MSR Virtualization  ................................ ................................ ................................ ... 48 
24.1.3.  Debug Feature -Specific Handling  ................................ ................................ ................................ ................  48 
24.2.  On-L2 VM Performance Monitoring  ................................ ................................ ................................ ................  50 40 
24.3.  L1 VMM Debug of L2 VMs  ................................ ................................ ................................ ..............................  50 
24.4.  Off-TD Debug of L2 VMs  ................................ ................................ ................................ ................................ . 50 
24.4.1.  L2 VM Debug Controls Used by the Host VMM  ................................ ................................ ..........................  50 
24.4.2.  Host VMM Access of Debuggable TD’s L2 VM State, Controls and Memory  ................................ ..............  51 
25. Guest -Side TDX Functions (TDCALL) for L2 VMs  ................................ ................................ ................................  52 45 
25.1.  TDG.VP.VMCALL  ................................ ................................ ................................ ................................ ..............  52 TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 6 of 52 
Section 1:  Introduction and Overview  SECTION  1: 
INTRODUCTION AND OVERVIEW  
 TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 7 of 52 
Section 1:  Introduction and Overview  10. About this Document  
10.1. Scope  of this Document  
This document describes the architecture and the external Application Binary Interface (ABI) of the Intel ® Trust Domain

This document describes the architecture and the external Application Binary Interface (ABI) of the Intel ® Trust Domain 
Extensions  (Intel ® TDX) module’s TD Partition ing feature, implemented using the Intel TDX Instruction Set Architecture 
(ISA) extensions . 5 
This document is part of the TDX Module Architecture Specification Set , which includes the following documents:  
Table 10.1:  TDX Module Architecture Specification Set  
 Document Name  Reference  Description  
 TDX Module  
Base Architecture Specification  [TDX Module Base 
Spec ] Base TDX module architecture overview 
and specification, covering key 
management, TD lifecycle management, 
memory management, virtualization, 
measurement and attestation, service TDs, 
debug aspects etc.  
 TDX Module  
TD Migration Architecture Specification  [TD Migration Spec]  Architecture overview and specification for 
TD migration  
→ TDX Module  
TD Partitioning  Architecture 
Specification  [TD Partitioning  
Spec]  Architecture overview and specification for 
TD Partition ing 
 TDX Module  
TDX Connect Specification  [TDX Connect  Spec ] Architecture overview and specification for 
TDX Connect  
 TDX Module  
ABI Reference Specification  [TDX Module ABI 
Spec ] Detailed TDX module Application Binary 
Interface (ABI) reference specification, 
covering the entire TDX module 
architecture  
 TDX Module  
TDX Connect ABI Reference 
Specification  [TDX Connect  ABI 
covering the TDX connect architecture  
 TDX Module ABI Reference Tables  [TDX Module ABI 
Tables]  A set of JSON format files detailing TDX 
module Application Binary Interface (ABI)  
 TDX Module ABI Incompatibilities  [TDX Module ABI 
Incompatibilities]  Description of the incompatibilities 
between TDX 1.0 and TDX 1.4/ 1.5 that may 
impact the host VMM and/or guest TDs  
 
This document is a work in progress and is subject to change based on customer feedback and internal analysis .  This 
document does not imply any product commitment from Intel to anything in terms of features and/or behaviors.  10 
Note : The contents of this document are accurate to the best of Intel’s knowledge as of the date of publication, though 
Intel does not represent that such information will remain as described indefinitely in light of future research 
and design implementations.   Intel does not commit to update this document in real time when such changes 
occur.  
10.2. Document Organization  15 
The document has multiple  sections:  
• Section 1 contains an introduction to the document, overview of TD Partition ing, scenarios and requirements.  
• Section 2 contains the Intel TDX Module TD Partition ing architecture  
• Section 3 contains updates to the TD Module ABI.  This section will eventually be merged into the [ TDX Module ABI 
Spec ]. 20 TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 8 of 52 
Section 1:  Introduction and Overview  10.3. Glossary  
For a complete TDX module glossary, see the [ TDX Module Base Spec ]. 
Table 10.2:  Intel TDX Glossary  for TD Partition ing 
Acronym  Full Name  New for 
TDX  Description  
 L2 Page 
Alias  Yes Mapping of a TD private page in an L2 VM’s GPA space  
L1 VM  Layer 1 VM  No The m ain virtual machine of the TD, which may also have the role on an L1 VMM  
L1 VMM  Layer 1 
VMM  No The m ain virtual machine of the TD, which also serves as a Virtual Machine 
Monitor (VMM) for nested L2 VM guests  
L2 VM  Layer 2 VM  No A virtual machine which is nested within a TD, and is logically a guest of the L1 
VMM  
VM Virtual 
Machine  No A virtual multi -LP processor, contained within a TD  
10.4. Notation  
See the [ TDX Module Base Spec ]. 5 
10.5. References  
See the [TDX Module Base Spec].  TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 9 of 52 
Section 1:  Introduction and Overview  11. TDX TD Partition ing Overview  
For an overview of TDX, refer to the [ TDX Module Base Spec ]. 
11.1. Introduction  
TDX TD Partition ing, as described in this document, is designed to provide a minimal environment for supporting the 
Microsoft VSM and similar  architectures.  It supports a single unmodified legacy VM and up to two additional supervisory 5 
VMs within a guest TD.  
TD Partition ing extends the base TDX architecture by allowing TDs to contain multiple virtual machines (VMs).  A TD may 
contain up to 4 VMs.  The primary VM (known as the L1 VM) may act as a virtual machine monitor (know n as the L1 
VMM) .  Up to 3 nested VMs (known as the L2 VMs)  serve as the guest of the L1 VMM.  
Host VMM
TDX-EnlightenedHost -VMM -managed access 
control, enhanced with MK -TMETDX Module -managed access 
control,  leveraging MK -TME and 
Secure EPT
Intel TDX Module
Running in SEAM Root ModeTrust Domain
TDX-Enlightened
OSUnmodified
DriversUnmodified
Applications
TDX
Guest -Side APILegacy VM
OSApplications
DriversLegacy VM
Drivers
Platform (Cores, Caches, Memory, Devices etc.)Partitioned Trust Domain
L1 VMML2 VM
Optionally 
TDX-
EnlightenedL2 VM
Unmodified 
Legacy VML2 VM
TDX-
Enlightened
TDX
Guest -Side API
TDX
Host-Side
APIL1-VMM -managed 
access control
 10 
Figure 11.1:  TDX Components  with TD Partitioning  
A TD may have one or more virtual CPUs (VCPUs).  With TD partition ing, each VCPU can run in either L1 VMM or in one 
of the L2 VMs.  Transitions between L1 VMM and L2 VMs always occur within the same VCPU.  
The diagram below shows an example of how the TD Partition ing architecture can be mapped to Microsoft’s VSM 
architecture.  15 TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 10 of 52 
Section 1:  Introduction and Overview  
Intel ConfidentialIntel TDX Names are in Black
Microsoft Hyper -V Names are in RedPartitioned Trust Domain
VTL0
VM #1 (L2 VM)VTL1
VM #2 (L2 VM)
Hypervisor
Host VMMHypervisor’
Intel TDX ModuleVM #0
(L1 VM/VMM)
Inter -VTL Transitions
L1→ L2 VM 
Entries/Exits“Paravisor ”VMCSVP #0
VCPU #0
VP #1
VCPU #1VMCS VMCS
VMCS VMCS VMCS 
Figure 11.2:  Example of TDX TD Partition ing Mapping to Microsoft’s VSM Architecture  
 
11.2. Security Properties  
SOC H/WMCHECK NP-SEAMLDR Other ACMsTDX 
ModuleHost 
VMM
BIOSLegacy
VM
SMMTDLegacy
VMLegacy
VM
All ACM’s and MCHECK are in 
the same TCB groupTD
P-SEAMLDRPartitioned
TDL1 
VMML2
VML2
VML2
VM
 5 
Figure 11.3:  TDX TCB Dependency Diagram  
Within a TD, the L1 VMM is in the TCB of L2 VMs; the L1 VMM to L2 VM relationship is similar to that of a legacy VMM to 
legacy VMs.   Other than that, TD Partition ing maintains the same security properties of the base TDX architecture.  
Note:  The L1 VMM is expected to protect itself against untrusted L2 VMs using the mechanisms provided by the TDX 
module and the underlying CPU’s VMX technology.  For example, the L1 VMM should properly assign memory 10 
access permissions to L2 VMs.  TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 11 of 52 
Section 1:  Introduction and Overview  11.3. L2 VM Private Memory Management  
TD Partition ing extends the TD private memory model such that each TD private page is managed as a single entity, with 
a single GPA mapping and state, but a separate set of attributes for each VM within the TD.  
Table 11.1:  Logical View of a TD Private Page Attributes  
Common  L1 VMM  L2 VM #1  L2 VM #2  L2 VM #3  
GPA  R=1, W=1, X=1 R, W, Xs, Xu  R, W, Xs, Xu  R, W, Xs, Xu  
HPA   SSS, VGP , PWA  SSS, VGP , PWA  SSS, VGP , PWA  
State      
 5 
• The L1 VMM and all L2 VMs share the same GPA space; however, the access rights and other attributes of pages 
within this GPA space may be different between each VM.  
• All TD private pages are mapped in the L1 VMM GPA space  with read, write and execute permissions.  
• Individual TD private pages (4KB, 2MB or 1GB) may be mapped by the L1 VMM into the GPA space of an L2 VM.  This 
mapping is called page alias .  A page alias has the same GPA  but may have different access permissions and other 10 
attributes than the L1 mapping of the same TD private page.  
GPA Space  VM #0  
L1 VMM   VM #1  
L2 VM   VM #2  
L2 VM   VM #3  
L2 VM  
Page A  RWX   R    None  
Page B  RWX   R  RWX   R 
Page C  RWX   RWX   None    
Page D  RWX   None   RWX    
Page E  RWX   RWX     R 
Page F  RWX   RWX     R 
Page G  RWX   RW    R 
Page H  RWX   RWX     R 
Figure 11.4:  Example of Page Permissions for L1 VMM and L2 VMs   
11.4. L2 VM Transitions  
With TD Partitioning, each TD VCPU can run in either L1 VMM or in one of the L2 VMs.  Inter -VM transitions always 
happen within the same VCPU.  15 
• A VCPU running in L1 VMM can initiate an L1 →L2 VM entry.  
• A VCPU running in L2 VM normally exits back to the to the L1 VMM (L2 →L1 VM exit).  
• In some cases, TD exit to the host VMM may happen directly from a VCPU running in L2 VM.

L1 VMM   VM #1  
L2 VM   VM #2  
L2 VM   VM #3  
L2 VM  
• In some cases, TD exit to the host VMM may happen directly from a VCPU running in L2 VM.  
• In such cases, the host VMM may re -enter the TD to either resume the exited L2 VM or to resume the L1 VMM.  TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 12 of 52 
SEAM Mode
TD
VCPUL1 L2
Host
VMMTDX Module
TD Entry
resuming L1
TD Exit
from L2Host -Side 
Local
FlowGuest -Side 
Local
Local
Flow
TD Exit
from L1
TD Entry
resuming L2L2→L1ExitL1→L2 
EntryHost→ TD Transitions
L1→ L2 Transitions
Local FlowsLegacy Mode
Non -Root 
ModeRoot 
Mode
TD Entry &
L2→L1 Exit 
Figure 11.5:  TDX Transitions  
11.5. L2 VM CPU Virtualization  
As a general rule, L2 VM CPU virtualization is controlled by the L1 VMM, within the feature set available to the whole TD 
and limitation imposed by the TDX architecture.   The L1 VMM virtualized CPUID and controls the virtualization of MSRs, 5 
thus controlling CPU feature enumeration, for L2 VMs.   The L1 VMM configures the L2 VCPUs’ VMCS and additional VMX 
control structures such as MSR exit bitmaps to control L2 VCPU virtualization, within the limitations imposed by the TDX 
module.  
TD Partition ing is designed to support unmodified legacy VMs running as L2 VM.  To that end, all CPU modes supported 
in VMX non -root mode are supported for L2 VMs.  10 
11.6. L2 VM Measurement and Attestation  
TD Partition ing does not modify the TDX measurement and attestation architecture.  Measurement and attestation of L2 
VMs are the responsibility of the L1 VMM.  
11.7. L2 VM Debug  
The TD Partition ing architecture enhances the off -TD debug facilities to support L2 VMs.  In addition, it enables o n-L2 VM 15 
debug  facilities for debugging an L2 VM using software that runs inside that VM, and L1 VMM debug of L2 VMs . 
11.8. TD Partition ing Interaction with TD Migration  
The TD Migration architecture is extended to support live migration of TDs that contains nested L2 VMs.  
• The whole TD is always migrated, including any L2 VMs it might have.  
• L2 VMs’ non -memory state (metadata) is migrated, as well as memory aliasing information.  20 TD Partitioning Spec  Section 1:  Introduction and Overview  354807 -002US  
November 2023  . Page 13 of 52 
Section 1:  Introduction and Overview  11.9. Intel TDX TD Partition ing Interface Functions  
11.9.1.  Host -Side (SEAMCALL Leaf) Interface  Functions  
Table 11.2:  Updated Host -Side (SEAMCALL Leaf) Interface  Functions  
Class  Interface Function Name  Leaf 
# Description  
VCPU Scope  TDH.VP.ENTER  0 Enter TDX non -root operation  
VCPU Scope  TDH.VP.FLUSH  18 Flush the address translation caches and cached TD 
VMCS associated with a TD VCPU  
Private Memory Management  TDH.MEM.PAGE.DEMOTE  15 Split a 2MB or a 1GB private TD page mapping into 512 
4KB or 2MB page mappings respectively  
Private Memory Management  TDH.MEM.PAGE.PROMOTE  23 Merge 512 consecutive 4KB or 2MB private TD page 
mappings into one 2MB or 1GB page mapping 
respectively  
Private Memory Management  TDH.MEM.PAGE.RELOCATE  5 Relocate a 4KB mapped page from its HPA to another  
Private Memory Management  TDH.MEM.PAGE.REMOVE  29 Remove a private page from a guest TD  
Private Memory Management  TDH.MEM.RANGE.BLOCK  7 Block a TD private GPA range  
Private Memory Management  TDH.MEM.RANGE.UNBLOCK  39 Remove the blocking of a TD private GPA range  
Private Memory Management  TDH.MEM.SEPT.ADD  3 Add and map a 4KB Secure EPT page to a TD  
Private Memory Management  TDH.MEM.SEPT.RD  25 Read a Secure EPT entry  
Private Memory Management  TDH.MEM.SEPT.REMOVE  30 Remove a Secure EPT page from a TD  
 
11.9.2.  Guest -Side (TDCALL Leaf) Interface  Functions  5 
Table 11.3:  New and Updated Guest -Side (TDCALL Leaf) Interface  Functions  
VCPU Scope  TDG.VP.ENTER  25 Enter L2 VCPU operation  
VCPU Scope  TDG.VP.INVEPT  26 Invalidate cached EPT translations for selected L2 VMs  
VCPU Scope  TDG.VP.INVGLA  27 Invalidate cached translations for selected pages in an 
L2 VM  
Private Memory Management  TDG.MEM.PAGE.ACCEPT  6 Accept a pending private page into the TD  
Private Memory Management  TDG.MEM.PAGE.ATTR.RD  23 Read the GPA mapping and attributes of a TD private 
page  
Private Memory Management  TDG.MEM.PAGE.ATTR.WR  24 Write the attributes of a private page  
 
 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 14 of 52 
Section 2:  TD Partitioning Architecture  SECTION 2: 
TD PARTITIONING  ARCHITECTURE SPECIFICATION  
November 2023  . Page 15 of 52 
Section 2:  TD Partitioning Architecture  20. L2 VM  Non -Memory State (Metadata)  and Control Structures  
This chapter discusses the guest TD control structures that hold non -memory state (metadata) and how they are intended 
to be used during the TD life cycle.  
20.1. Overview  
TDVPSTDCSMSR Exit 
Bitmaps
Shared
EPT TreePIDHost VMM Allocated & 
Managed, Shared HKIDNot Mapped to TD GPA, Host VMM Allocated, TDX Module Managed
TDRGlobal Private 
HKID
VM0 (L1) SEPT TreeSEPT_PAGESEPT_PAGESEPT PageTD
Context
VCPU
ContextL2
VAPICMapped to TD GPA, L1 Allocated & 
Managed, TD Private HKID
L1
VMCSL1
VAPICVCPU 
StateVCPU 
Manage.SEPT0 Root 
Page
PML L1
VE Info
HLAT
PT TreeVM1 (L2) SEPT TreeSEPT_PAGESEPT_PAGESEPT PageSEPT1 Root 
Page
VM2 (L2) SEPT TreeSEPT_PAGESEPT_PAGESEPT PageSEPT2 Root 
Page
L1 MSR Exit 
Bitmaps
L2
VMCSL2 VCPU 
Manage.L2 MSR Exit 
BitmapsTD Private HKID
TD 
Management
TD Exec. 
Control
Other TD -
Scope State
Shared
EPT TreePML
L2
VAPICHLAT
PT TreeL2
BitmapsShared
EPT TreePMLL2
VE Info
L2
VE InfoL2 MSR Exit 
Bitmaps Shadow
L2 MSR Exit 
Debug Only
 5 
Figure 20.1:  Overview of Guest TD Control Structures with TD Partition ing Support  
TD Partition ing extends the TD’s  control structure s and adds new ones to control the operation and hold the state of L2 
VMs.  All guest TD control structures reside in memory pages that are allocated by the host VMM and are addressable by 
it. 
20.1.1.  Opaque L2 Control Structures  10 
The following L2 control structure reside in memory pages that are encrypted by the TD’s private key, but are not directly 
accessible to either the L1 VMM or to the host VMM : 
L2 SEPT : Secure EPT tree for mapping the L2 VM’s GPA space.  
20.1.2.  Private Control Structures  
Multiple standard VMX control structures that are used by the L1 VMM and its L2 VM guests are mapped in the TD’s GPA 15 
space : 
• Virtual APIC page  
• VE Info page  
• HLAT page table tree  
The L1 VMM may map specific control structure pages (e.g., VE Info) in the L2 VM’s GPA space by creat ing page aliases.  20 
20.1.3.  Shared Control Structures  
Standard VMX control structures that are to be accessible by the host VMM can reside in shared memory:  
• Shared EPT  
• Page Modification Log (PML)  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 16 of 52 
Section 2:  TD Partitioning Architecture  20.2. Additions to Existing TD Control Structures  
20.2.1.  TDCS  
TDCS holds a set of L2 VM related  fields.  For each of the L2 VMs, the following fields are maintained:  
Table 20.1:  TDCS L2 VM Related Fields High Level Definition  
Field  Description  Reference  
NUM_L2VMS  Number of L2 VMs in this TD   
L2_SEPT_ROOT  Per-L2 VM Secure EPT root page   
 5 
For a detailed definition of TDCS, please see the [ TDX Module ABI Spec ]. 
20.2.2.  TDVPS  
 New TDVPS Fields  
TDVPS is extended with the following per-VCPU fields:  
Table 20.2:  New TDVPS Per-VCPU Fields High Level Definition  10 
CURR_VM  VM index currently used for this VCPU  22.2  
ACTIVE_VMCS  VM index of the active VMCS (last VMCS target of VMPTRLD).  If 
there’s no active VMCS  or the last VMPTRLD was not of one of the 
guest VMCSes , value is -1.  
 
 New Per -VM TDVPS Fields  
TDVPS is extended with the following fields, per VM : 
L2 VM Management Fields  
Table 20.3:  TDVPS Per -VM (L1 and L2) Management Fields High Level Definition  15 
VM_ LAUNCHED  A Boolean flag, indicating whether the VM (i.e., it’s VMCS) 
has been VMLAUNCH’ed on this LP since it has last been 
associated with this VCPU.  
If TRUE, VM entry should use VMRESUME.  
Else, VM entry should use VMLAUNCH.   
LP_DEPENDENT_HPA_UPDATED  Flags that the LP -dependent HPA fields have been updated.  
Cleared after new VCPU -to-LP association.   
 
Table 20.4:  TDVPS Per -VM (L2 Only)  Management  Fields High Level Definition  
L2_ENTER_GUEST_STATE _GPA  GPA of the TDG.VP.ENTER guest state  buffer   
L2_ENTER_GUEST_STATE _HPA  HPA of the TDG.VP.ENTER guest stats  buffer   
L2_VE_INFO_GPA  GPA of the L2 VE_INFO area   
L2_VE_INFO_HPA  HPA of the L2 VE_INFO area

L2_VE_INFO_HPA  HPA of the L2 VE_INFO area   
L2_VAPIC_PAGE_GPA  GPA of the L2 virtual APIC page (used by the L1 VMM)   TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 17 of 52 
Section 2:  TD Partitioning Architecture  Field  Description  Reference  
L2_VAPIC_PAGE_HPA  HPA of the L2 virtual APIC page (used by the L1 VMM)   
 
L2 VM Execution  Control Fields  
Table 20.5:  TDV PS Per-VM Execution Control Fields High Level Definition  
ENABLE_SHARED_MEM  L2 VCPU policy for using shared memory, set by the L1 
VMM  21.7  
ENABLE_TDVMCALL  Allow the L2 VM to use TDG.VP.VMCALL  22.2.3  
SHADOW_MSR_BITMAPS  Shadow MSR exit bitmaps page, defining the L2 VM 
policy for handling MSR access, set by the L1 VMM  23.8   
SHADOW _PROCBASED_EXEC_CTRL2  Shadow of the L2 VMCS “secondary processor -based 
execution controls”.  Holds the L2 policy as set by the L1 
VMM for the following bits:  
• Bit 30:  B us-lock detection  
• Bit 31:  Notification exiting  23.12   
SHADOW _NOTIFY_WINDOW  Shadow of the L2 VMCS “notify window” execution 
control.  Holds the L2 policy as set by the L1 VMM.  23.12  
TSC_DEADLINE  L2 VCPU execution deadline, set by the L1 VMM  23.13  
 
L2 VM VMX Standard Control Structures  5 
Table 20.6:  TDVPS Per -VM VMX Standard Control Structures High Level Definition  
VMCS  VMCS used when the VCPU runs in this VM   
MSR_BITMAPS  Exit bitmaps page used by the CPU   
 
For a detailed definition of TDVPS, please see the [ TDX Module ABI Spec ]. 
20.3. Concurrency Restrictions and Enforcement  
Currently, TD partitioning adds no additional concurrency restrictions to the TD’s non -memory state.  10 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 18 of 52 
Section 2:  TD Partitioning Architecture  21. L2 VM Memory Management  
This chapter described how the Intel TDX module helps manage TD private memory and guest -physical address (GPA) 
translation.  
21.1. Introduction  
Each VM in a TD uses its own SEPT tree to translate GPA to HPA.  Every TD private page must be mapped in the L1 SEPT 5 
tree; in addition, it may be mapped in one or more L2 SEPT trees.  The L2 SEPT mapping creates an alias . 
L1 GPA
L1 SEPT L2 SEPT
HPAL2 GPA
Secure EPTs (SEPTs)
•Translate GPA to HPA
•Used by the CPU (PMH)
•Accessible only by TDX module
•Not mapped in GPA space
•Memory allocated by host VMM=
Alias
 
Figure 21.1:  GPA→HPA Translation for L1 and L2 VM  
The table below summarizes  page  aliasing features . 
Table 21.1:  Page Aliasing  10 
Item  Page Aliasing  
Mechanism  TD private page is mapped in both L1 SEPT as a leaf entry and L2 SEPT as a leaf 
entry.  
SEPT Leaf Entry  L1 VMM and L2 VM see different SEPT leaf entries.  
Mapping Type and Size  Leaf:  4KB, 2MB, 1GB  
Mapping Constraints  L2 GPA == L1 GPA  
L2 mapping size == L1 mapping size  
Page Access Permission s Page access permissions for L2 may be different than its access permissions for 
L1. 
Page Attributes :  CET SSS, 
HLAT , Suppress VE  Page attributes for L2 may be different than its attributes for L1.  
Management  Page aliases are m anaged by the L1 VMM .  The host VMM is not directly 
involved . 
November 2023  . Page 19 of 52 
Section 2:  TD Partitioning Architecture  
Main (L1 VMM) SEPT Tree L2 VM SEPT Tree
Non-Aliased Pages Non-Aliased Pages Aliased PagesLegend
Secure EPT Page (PT_EPT)
Private Physical Page (PT_REG), size = 4KB, 2MB or 1GB
Page Aliases
 
Figure 21.2:  Page Aliasing  
L2 SEPT Properties  
• L2 SEPT  trees have the same number of levels (4 or 5) as the L1 SEPT.  
• Each non -free L2 SEPT entry has an applicable (same GPA and level) L1 SEPT entry.  5 
21.2. L2 Page Aliasing  
21.2.1.  Logical View of a TD Private Page with Pages Alias es 
Logically, L2 page alias es extend a private TD page attributes to include the attributes as seen by each L2 VM.  
Table 21.2:  Logical Attributes  of a TD Private Page with Page Alias es 
Common  GPA  
HPA  
Main SEPT entry state  
Per VM  L1 VMM  L2 VM #1  L2 VM #2  L2 VM #3  
 L2 SEPT entry state  L2 SEPT entry state  L2 SEPT entry state  
R, W, Xs, Xu  R, W, Xs, Xu  R, W, Xs, Xu  R, W, Xs, Xu  
 SSS, VGP , PWA  SSS, VGP , PWA  SSS, VGP , PWA  
SVE SVE SVE SVE 
 10 
The main SEPT entry state, used for memory management and TD migration, is held by the L1 SEPT entry.  Memory 
management interface functions process the L1 SEPT entry and its L2 alias SEPT entries together.  
21.2.2.  L2 Secure EPT Entry Partial State Diagram  
The L2 SEPT entry state machine is relatively simple since  the overall page state management is done using the L1 SEPT 
entry for the page.  15 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 20 of 52 
Section 2:  TD Partitioning Architecture  The diagram below is a partial state diagram which covers memory management operations for a page alias, not including 
TD migration .  TD migration does not add new states; for details, see [TD Migration Spec].  
L2_FREE
SEPT entry is not 
mapped to a physical 
pageL2_MAPPED
Page is mapped and 
accessible to guest 
TDTDG.MEM.PAGE.ATTR.WR
[non -0, L1 is MAPPED]
TDG.MEM.PAGE.ATTR.WR
[non -0, L1 is PENDING]TDH.MEM.SEPT.ADD
TDH.MEM.PAGE.DEMOTE /
Entry becomes non -leaf,
L2_NL_MAPPEDTDH.MEM.PAGE.PROMOTE
[L2_NL_MAPPED with 512 L2_MAPPED/L2_BLOCKED entries] /
Entry becomes leaf
From Non -Leaf 
Entry State 
DiagramTDH.MEM.PAGE.DEMOTE
[L1 is MAPPED] /
New leaf
TDH.MEM.PAGE.DEMOTE
[L1 is PENDING] /
New leafTo Non -Leaf 
Diagram
TDH.MEM.PAGE.REMOVE
L2_BLOCKED
Page is mapped but 
new translations are 
blockedTDH.MEM.RANGE.
BLOCK
TDH.MEM.PAGE.PROMOTETDH.MEM.PAGE.REMOVE
[TD is paused]TDH.MEM.PAGE.DEMOTE [TD is paused] /
L2_NL_MAPPED
TDH.MEM.PAGE.PROMOTE
[TD is paused]
TDH.MEM.RANGE.
UNBLOCK
[L1 is BLOCKED]TDG.MEM.PAGE.
ACCEPTTDG.MEM.PAGE.ATTR.WR [0]
TDG.MEM.PAGE.ATTR.WR [0]TDH.MEM.PAGE.PROMOTE
[L2_NL_MAPPED with
512 L2_FREE entries] /
 
Figure 21.3:  L2 Secure EPT Leaf Entry Partial State Diagram  
 5 
L2_FREE
pageL2_NL_MAPPED
SEPT page is mapped 
and new SEPT walks 
to GPA range are 
permittedTDH.MEM.SEPT.ADDTDH.MEM.PAGE.PROMOTE /
Non -leaf entry becomes
leaf, MAPPEDTDH.MEM.PAGE.DEMOTE /
Previous leaf entry becomes NL_MAPPED
From Leaf Entry 
State Diagram
To Leaf Entry 
TDH.MEM.SEPT.REMOVE[all entries are FREE]L2_NL_BLOCKED
but new SEPT walks 
blockedTDH.MEM.RANGE.BLOCK
TDH.MEM.SEPT.REMOVE
[all entries are FREE && [TD is paused]TDH.MEM.PAGE.PROMOTE [TD is paused] /
Non -leaf entry becomes leaf, MAPPED
TDH.MEM.RANGE.UNBLOCK
 
Figure 21.4:  L2 Secure EPT Non -Leaf Entry Basic Operation Partial State Diagram  
21.2.3.  L2 Page Alias Management :  TDG.MEM.PAGE. ATTR .RD/WR  
 Overview  
A TD private page is managed by the L1 VMM as a single entity, including its L1 state and attributes and any L2 page alias 10 
state and attributes.  L1 VMM operates on page attributes using the GPA mapping size as set by the host VMM (i.e., 4KB, TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 21 of 52 
Section 2:  TD Partitioning Architecture  2MB or 1GB).  This requires the L1 VMM to understand the concept of mapping size and to cooperate with the host VMM 
if there’s a need to control page attributes with a different granularity than currently configured.1 
A single interface function TDG.MEM.PAGE.ATTR.WR enables the L1 VMM to create L2 page aliases, modify their 
attributes and remove them.  The host VMM is not directly involved, except when there’s an EPT violation due to the 
need to add L2 SEPT pages.  5 
L2 aliases may be added, modified and removed from pending pages.  When the L1 VMM accepts a pending page 
(TDG.MEM.PAGE.ACCEPT) it also accepts its L2 page aliases.  
TDG.MEM.PAGE.ATTR.RD enables the L1 VMM to read L2 page attributes.  
 Adding L2 Page Alias es 
The L1 VMM  adds new L2 page alias es and sets its attributes using TDG.MEM.PAGE. ATTR.WR  with a set of attributes 10 
whose R, W, Xs or Xu bits are not all -0.  The host VMM is not directly involved .  TDG.MEM.PAGE. ATTR.WR  may encounter 
an EPT violation; in this case the  TDX module  TD-exits to the host VMM to indicate the need to add SEPT pages.   This is 
shown in the picture below.  
TD VCPU
TDX 
ModuleL1
Host VMM1.Walk L1 SEPT
2.Walk L2 SEPT (failed)L2
TDG.MEM.PAGE. ATTR. WR
(GPA , level,
attributes, attributes_mask )
EPT violation TD exitTDH.MEM.
SEPT.ADD
Add L2 SEPT 
Page @ Level
Add L2 SEPT 
Page @ LevelBuild L2 SEPT 
tree
TDH.VP.ENTER1.Walk L1 SEPT
2.Walk L2 SEPT
3.Create alias leaf entry 
and set attributesTDG.MEM.PAGE. ATTR. WR
attributes, attributes mask)Unmapped GPA 
access
VM 
entryVM 
entryRe-issue same TDCALL
TDCALL VM exit TDCALL VM exit

TD VCPU
TDX 
ModuleL1
SEPT.ADD
Add L2 SEPT 
Add L2 SEPT 
tree
access
VM 
entryVM 
1.Walk L1 SEPT
2.Page SEPT entry is 
MAPPED or PENDINGEmulated L2 →L1 VM 
exit (EPT violation)VM exit 
(EPT 
violation)
 
Figure 21.5:  Example of Adding a n L2  Page Alias where Secure EPT Build is Required  15 
The L1 VMM may add L2 page alias es to a PENDING page.  In this case, the page alias is created in a n L2_BLOCKED  state.   
When the L1 VMM accepts the page using TDG.MEM.PAGE.ACCEPT, it also accepts any page alias  it has ; the L2 page alias 
state becomes L2_MAPPED and its attributes, set by TDG.MEM .PAGE.ATTR.WR , become effective.  
The L1 VMM specifies a page size and may fail if the specified size is different than the actual SEPT mapping size.  
• If the page is mapped at a lower SEPT level than requested, TDG.MEM .PAGE.ATTR.WR returns an error code and the 20 
actual mapping size.  The L1 VMM may re -invoke TDG.MEM.PAGE.ATTR.WR specifying the actual mapping size.  
• If the page is mapped at a higher SEPT level than requested, this results in an E PT violation  TD exit, with information 
about the guest -requested mapping level.  The host VMM typically demotes the page, then re -enter the guest TD so 
TDG.MEM.PAGE.ATTR.WR is re -invoked.  
Typical Use Case  25 
Adding page aliases may be done dynamically, based on an EPT violation L2 →L1 VM exit.  
1. The L1 VMM invokes TDG.MEM.PAGE. ATTR.WR  to set non -0 L2 page attributes to a given GPA . 
2. The L2 SEPT tree is missing an EPT page to map the new alias .  The TDX module performs a  TD exit, indicating an EPT 
violation with an extended exit qualification providing the L2 VM index and other details.  
3. The host VMM invokes TDH.MEM.SEPT.ADD to build the L2 SEPT tree.  30 
4. The host VMM invokes TDH.VP.ENTER to resume the TD.  
 
1 This is not a new concept in TDX.  It already exists for TDG.MEM.PAGE.ACCEPT  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 22 of 52 
Section 2:  TD Partitioning Architecture  5. The guest state, including RIP, hasn’t been modified.  Thus, TDG.MEM.PAGE. ATTR.WR is executed  again.  This time 
the operation succeeds.  
 Modifying L2 Page Attributes  
The L1 VMM  can modify  an existing L2 page alias using TDG.MEM.PAGE. ATTR .WR with a set of attributes whose R, W, Xs 
or Xu bits are not all -0.  The L1 VMM is responsible for TLB shootdown of its L2 VM if this is required, e.g., if page access 5 
permissions are reduced.   TDG.MEM.PAGE.ATTR.WR, TDG.VP.INVEPT and TDG.VP.ENTER allow the L1 VMM  to invalidate 
cached SEPT translations after modifying page attributes.  
TD VCPUTD VCPU
INVEPT on L1 →L2 VM 
Entry (for Permission 
Reduction) Virtual IPI for TLB Shootdown (for Permission Reduction) TDX 
ModuleL1
Host VMMTDG.VP.
VMCALL
Request 
Virtual IPI
TDH.VP.
ENTER1.Walk L1 SEPT
3.Update attributesIPIL2
attributes, attributes_mask )VM 
exit
VM
entryTDG.VP.ENTER
(VM index,
VCPU index,
do_invept )
If requested, do 
INVEPT for L2 SEPT 
and emulate L1 -to-L2 
VM entryVM
entryRendezvous 
all VCPUs
Write 
local 
APICTDH.VP.
ENTEREPT violation on L1 or L2 
SEPT walk errorsVM 
entry
 
Figure 21.6:  Example of L1 VMM Modifying a Page Alias  Attributes  
The L1 VMM can update the page alias attributes of a PENDING page.  10 
Typical Us e Case  
1. The L1 VMM rendezvous all VCPUs : 
1.1. To do that, the L1 VMM requests the host VMM to issue IPIs to all the LPs running the current TD (the L1 VMM 
doesn’t directly know if a VCPU  is running  in L1 or L2  on each LP).  
1.2. Each VCPU running in L2 that receives the IPI TD -exits to the host VMM.  15 
1.3. The host VMM resumes the L1 VMM  by invoking TDH.VP.ENTER.  
2. The L1 VMM invokes TDG.MEM.PAGE.ATTR.WR to update the L2 page alias attributes.  
3. The L1 VMM resumes L2 by invoking TDG.VP.ENTER, indicating that EPT invalidation should be done before each VM 
entry . 
 Removing L2 Page Alias es 20 
The L1 VMM removes existing L2 page alias es using TDG.MEM.PAGE.ATTR.WR  with a set of attributes whose R, W, Xs 
and Xu bits are all -0.  The L1 VMM is responsible for TLB shootdown of its L2 VM.   TDG.MEM.PAGE.ATTR.WR, 
TDG.VP.INVEPT and TDG.VP.ENTER allow the guest TD to invalidate cached SEPT translations.  
Note:  Since the TD private page is still owned by the TD, there is no need for the host VMM to be involved.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 23 of 52 
Virtual IPI for TLB Shootdown (for Permission Reduction) Flushing EPT TranslationsTDG.VP.INVEPT
(VM bitmap)
Do INVEPT for the 
selected VMs’ SEPTsTDG.VP.INVEPT
selected VMs’ SEPTsTDX 
ModuleL1
VMCALL
Request 
TDH.VP.
3.Mark the leaf L2 SEPT 
entry a FREEIPIL2
(GPA, level,
exit
VM
EntryTDG.VP.INVEPT
(VM bitmap )
or
TDG.VP.INVVPID
(VM, GLA list)
selected VMs’ SEPTs
or
Do INVVPID for the 
selected VM and GLA 
listVM
all L2 VM’s 
VCPUs
Write 
local 
SEPT walk errors 
Figure 21.7:  Example of L1 VMM Removing a Page Alias  
Typical Use Case  
1. The L1 VMM rendezvous all VCPUs  
1.1. To do that, the L1 VMM requests the host VMM to issue IPIs to all the LPs running the current TD (the L1 VMM 5 
doesn’t directly know if a VCPU is running in L1 or L2 on each LP).  
1.2. Each VCPU running in L2 that receives the IPI TD -exits to the host VMM.  
1.3. The host VMM resumes the L1 VMM by invoking TDH.VP.ENTER.  
2. The L1 VMM invokes TDG.MEM.PAGE. ATTR.WR  to remove the page alias.  
3. The L1 VMM invokes TDG.VP.INVEPT or TDG.VP.INVGLA  on each VCPU to invalidate EPT  for the whole VM or for 10 
specific pages .   
21.3. Update s to SEPT Tree Management  
Secure EPT tree management interface functions are extended to support coordinated management of the L1 and 
multiple L2 SEPT trees, as described in the following sections.  
21.3.1.  Host VMM’s L2 SEPT Management Strategy  15 
The host VMM may deploy various strategies for populating the L2 SETP tree(2):  
Dense L2 SEPT Tree : The host VMM may choose to populate the L2 SEPT tree(s) as densely as the L1 SEPT tree is 
populated.  To do so, it allocate s an L2 SEPT page in each L2 SEPT tree for each L1 SEPT page.  
Sparse L2 SEPT Tree : The host VMM may choose to populate  L2 SEPT page s on demand, i.e., when the L1 VMM creates 
a page alias and there’s a need an L2 SEPT page to map it  (indicated by an EPT violation TD exit or 20 
by an explicit request from the L1 VMM using TDG.VP.VMCALL).  
The host VMM may also choose to maintain L2 SEPT trees only for a subset of the L2 VMs (e.g., if a TD is created with a 
certain number of L2 VMs, but not all of them are currently in use).  
21.3.2.  Adding SEPT Pages  
TDH.MEM.SEPT.ADD is extended to support adding of L2 SEPT pages : 25 
• The host VMM may add SEPT pages to one or more of the TD’s VMs in a single TDH.MEM.SEPT.ADD invocation.  
• To add L2 SEPT pages at a certain level, an L1 SEPT page must either already exist at that level or be added during 
the same TDH.MEM.SEPT.ADD invocation.  
• The operation is atomic, in the sense that either all requested SEPT pages are added successfully, or none is added.  
An exception to this rule is in the case of interrupted operation; see the [ TDX Module ABI Spec ] for details.  30 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 24 of 52 
Section 2:  TD Partitioning Architecture  21.3.3.  Removing SEPT Pages  
TDH.MEM.SEPT.REMOVE is extended to support removal of L2 SEPT pages.  When removing an L1 SEPT page at the 
specified GPA and level, all associated L2 SEPT pages at the same GPA and level are removed.  
21.3.4.  Page Demotion  
TDH.MEM.PAGE.DEMOTE is extended to support adding of L2 SEPT pages , which map the demoted 512 smaller -sized 5 
pages.  The host VMM may choose whether to add an L2 SEPT page only if there’s a page alias for the relevant L2 VM (to 
support the dense L2 SEPT management policy mentioned above).  
21.3.5.  Page Promotion  
TDH.MEM.PAGE.PROMOTE is extended to remove any L2 SEPT pages which map the promoted 512 smaller -sized pages.  
21.4. Other Updates to Memory Management Interface Functions  10 
Existing memory management interface functions are modified to support page aliasing as follows:  
Table 21.3:  Updates to Memory Management Functions to Support L2 Page Aliasing  
Memory Management 
Function  Description  
TDH.MEM.RANGE.BLOCK (of 
a leaf SEPT entry)  1. New:  Block all aliases (sets L2 SEPT leaf entries to L2_BLOCKED ) 
2. Block L1 mapping:  Set L1 SEPT leaf entry to *BLOCKED  
3. Record TD_EPOCH in PAMT.BEPOCH  
TDH.MEM.PAGE.REMOVE  1. New:  Remove all aliases (sets L2 SEPT leaf entries to FREE ) 
2. Set L1 SEPT leaf entry to FREE  
3. Mark PAMT as free

3. Mark PAMT as free  
TDH.MEM.PAGE.PROMOTE  1. Check that all 512 small page L1 SEPT entries have the same attributes  
and contiguous HPA mappings.  
2. New:  For each L2 SEPT tree, check that either all 512 small page aliases 
have the same attributes, or none of them exists . 
3. Promote L1 SEPT  mapping.  
4. New:  Promote applicable L2 SEPT mappings.  
TDH.MEM.PAGE.DEMOTE  1. Demote L1 SEPT  mapping.  
2. New:  For each page alias, demote L2 SEPT mapping . 
Additional SEPT pages for L2 SEPT are provided  by the host VMM  as inputs.  
TDH.MEM.PAGE.RELOCATE  1. Relocate the physical page.  
2. Updates HPA of L1 SEPT entry . 
3. New:  For each page  alias (L2 SEPT entr y), update HPA.  
TDG.MEM.PAGE.ACCEPT  Extended to accept any aliases that exist to the page . 
 
21.5. L1 VMM Control of L2 EPT Features  
The L1 VMM can enable or disable L2 EPT features by writing to the L2 VMCS (e.g., using TDG.VP.WR).  Note that these 15 
setting impact both secure EPT and shared EPT (if enabled).  
Table 21.4:  L1 VMM Control of L2 VM EPT Features  
SEPT Feature  EPT Bits  L2 VMCS  
# Name  Field Name  Bit #  Bit name  
CET 60 Supervisor shadow stack (SSS)   7 Enable SSS  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 25 of 52 
Section 2:  TD Partitioning Architecture  SEPT Feature  EPT Bits  L2 VMCS  
Mode -Based Execution 
Control (MBEC)  10 
2 Execute in user mode (Xu)  
Execute in supervisor mode (Xs)  Secondary processor -
based VM -execution 
controls  22 Mode -based execution 
control for EPT  
HLAT  57 Verify guest paging (VGP)  Tertiary processor -
controls  3 Guest -paging verification  
58 Paging -Write Access  
access (PW A) 2 EPT paging -write control  
 
21.6. L2 VM TLB Invalidation  
Two interface functions are provided for L2 TLB invalidation initiated by the L1 VMM:  
• TDH.VP.INVEPT allows the L1 VM to request invalidation of all TLB entries that belong the selected L2 VMs.  
• TDG.VP.INVGLA  allows the L1 VMM to request invalidation TLB of a list of page guest linear addresses that belon g to 5 
a specific L2 VM.  
For details, see the [ABI Spec].  
21.7. L2 VM Shared Memory Management  
Shared GPA (where SHARED bit is 1) mapping is controlled by the host VMM : 
• The host VMM may or may not use the same shared EPT tree for the L1 VMM and for one or more of the L2 VMs.   10 
• The host VMM should write each  L2 VMCS “shared EPTP” field with the HPA of the applicable shared EPT  root page.  
To provide defense -in-depth for unmodified legacy VMs running as L2 VMs, the L1 VMM can enable or disable shared 
memory access using the TDVPS.ENABLE_SHARED_MEM [VM]  field.  
21.8. Handling EPT Violation VM Exit from L2  
An EPT violation L2 VM exit can be the result of multiple  reasons and  should be handled by either the L1 VMM or the 15 
host VMM.  
EPT Violation VM 
exit from L2
Is GPA mis -
formatted?
L2→L1 VM exitIs GPA private?Walk L1 SEPT and 
find the offending 
entry
Is offending
GPA accessible 
to L1?Is offending
GPA PENDING?
TD exitNoYes
TD exitNoNo Yes
YesNo
L2→L1 VM exit L2→L1 VM exitYes
 
Figure 21.8:  Handling EPT Violation VM Exit from L2  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 26 of 52 
Section 2:  TD Partitioning Architecture  The TDX module handles such EPT violations as follows : 
1. If the offending GPA is mis -formatted, i.e., GPA bit at position higher than GPAW but lower than MAXPA is set to 1:  
1.1. TDX module completes an L2 →L1 VM exit.  
1.2. L1 VMM is expected to check the GPA vs. the virtual MAXPA value it enumerated to the L2 VM and  inject a 
#PF(PFEC.RSVD=1) to the L2 VCPU.  5 
2. Else, if the GPA is private:  
2.1. The TDX module walks the L1 SEPT tree to find the SEPT entry for the offending GPA.  
2.2. If the  offending GPA is not accessible to  L1 (i.e., to the TD as a  whole TD) in one of the following cases:  
2.2.1.  Non -leaf L1 SEPT entry state for  a containing GPA range is NL_BLOCKED.  
2.2.2.  There is no leaf L1 SEPT entry for the  page . 10 
2.2.3.  Leaf L1 SEPT entry state is FREE or REMOVED . 
2.2.4.  The page has been  blocked by the host VMM (L1 SEPT entry state is *BLOCKED) . 
2.2.5.  The page has been  blocked -for-writing by the host VMM (L1 SEPT entry state is *BLOCKEDW*) , and access 
attempt was a write . 
The TDX module complete an asynchronous TD exit, indicating an EPT violation exit from L2.  15 
2.3. Else, if the offending GPA if of a PENDING or PENDING_EXPORTED_DIRTY:  
2.3.1.  The TDX module completes an L2 →L1 VM exit.  
2.4. Else, the EPT violation’s cause is under L1 VMM control, e.g.:  
2.4.1.  The offending GPA has not been added as an alias.  
2.4.2.  The alias attributes don’t match the attempted memory access.  20 
In all the above cases, the TDX module completes an L2 →L1 VM exit.  The L1 VMM is expected to handle the 
EPT violation.  
3. Else (the GPA is shared):  
3.1. Shared GPAs are managed by the host VMM.  The TD module complete an asynchronous TD exit, indicating an 
EPT violation exit from an L2 VCPU.  25 
To handle L2 VM EPT violations, the L1 VMM can query the alias status using TDG.MEM.PAGE. ATTR .RD. 
21.9. Handling  EPT Misconfiguration VM Exit from L2  
This is similar to EPT misconfiguration VM exit from L1, as described in the [ TDX Module Base Spec ].  A n EPT 
misconfiguration on a private GPA indicates a TDX module bug and is handled as a fatal error.   EPT misconfiguration on a 
shared GPA causes a TD exit and is handled by the host VMM.  30 
21.10.  L2 GPA -to-HPA Soft Translation  
The GPAs of some structures in TD private memory are specified by the guest TD (using TDG.VP.WR and TDG.VP.ENTER).  
Such addresses are translated by the TDX module to shadow HPA values and stored in internal variables.  Using the TLB 
tracking mechanism, th e TDX model is designed to ensure  that the shadow HPA values correspond to the correct private 
GPAs whenever the CPU or the TDX module itself may use them.  35 
Table 21.5:  GPAs Specified by the Guest TD  
Address  GPA 
Stored 
in HPA 
Stored in Shadow 
HPA 
Stored in  Field  Name  Applicable When  GPA 
Mapping 
in L2  
TDG.VP.ENTER 
output memory 
operands  TDVPS  N/A TDVPS  Multiple  VCPU is entering 
to L2  
VCPU is exiting 
from L2  None  
L2 Virtual APIC 
page   TDVPS 
(shadow)  L2 VMCS  
 TDVPS  virtual -APIC address  VCPU is running 
in L2  None  
 
Notes  
• GPA mapping in L2 is not enforced by the TDX module.  The TDX module helps ensure  that the page is mapped in L1; 
it is up to the L1 VMM to ensure L2 accessibility for correct L2 VM operation.  40 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 27 of 52 
Section 2:  TD Partitioning Architecture  22. TD VCPU Enhancements for TD Partition ing 
This chapter discusses multiple items related how TD VCPUs  are enhanced to support TD Partition ing. 
22.1. Overview  
Each TD VCPU is a single logical entity with multiple modes of operation, one for each VM.  From the CPU’s perspective, 
each of the VCPU’s VM modes is controlled by its own VMCS and associated control structures.  5 
22.2. VCPU Transitions  
TDX Non -Root Mode
(Logical)TD VCPU
TDX Root Mode
(Logical)L1
Intel TDX ModuleHost VMMHost -Side 
API FunctionOtherL1 VM Exit 
Handler
SEAMCALL 
Entry 
Point
SEAMRETVMLAUNCH/
VMRESUME
TDH.VP.ENTER
(Normal)VM Exit 
Entry Point
TDG.VP.VMCALL
Save all TD State 
to TDVPS & InitAsync
TD ExitVM EntryTrap -Like
VM Exit
Fault -Like
VM ExitInstruction
Next Instruction
SEAMCALL
Next InstructionRestore TD State 
from TDVPS 
(Selected GPR/
XMM)TDH.VP.ENTER
(after
TDG.VP.VMCALL)
Restore all 
TD State 
from TDVPSTD Entry
to L1
TDVPS
(incl.
 L1 and L2 
VMCSes)LP-Scope 
State (incl. 
SEAM VMCS)
VMX Non -Root Mode VMX Root ModeL2
VMLAUNCH/
VMRESUMEVM Exit 
Entry PointVM EntryTrap -Like
VM Exit
L2 VM Exit 
Handler
Async
TD ExitVM Exit
Emulation
Save TD State to 
TDVPS and Init 
XMM)TD Entry to L2TDG.VP.ENTER
 
Figure 22.1:  TD VCPU Transitions Overview  
22.2.1.  L1-to-L2 VM Entry and L2 -to-L1 VM Exit:  TDG.VP.ENTER  
The L1 VMM can enter an L2 VCPU by invoking TDG.VP.ENTER , if its state is READY.  10 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 28 of 52 
TD VCPU
TDX
Module
L0L1
Host 
VMM1.VMPTRLD L2 VMCS
2.Restore GPRs from GPR state 
memory buffer
3.VMLAUNCH/VMRESUME L2
TDG.VP.ENTER(
vm_index ,
GPR state,
invept_flag )1.Save L1 CPU state not 
preserved by 
TDG.VP.ENTER
2.Restore L2 CPU state 
not in L2 VMCS guest 
state (excluding GPRs)
3.Prepare L2 CPU GPR 
state in a memory 
buffer (buffer most 
probably already exists)VM
exit
1.Examine exit reason, decide on VM 
exit to L1
2.Save L2 GPRs to GPR state 
3.VMPTRLD L1 VMCS
4.Advance guest RIP past TDCALL
5.VMLAUNCH/VMRESUME 1.Save L2 CPU GPRs

TD VCPU
TDX
Module
L0L1
Host 
vm_index ,
GPR state,
exit
exit to L1
2.Save L2 CPU state not in 
L2 VMCS guest state
3.Restore L1 CPU state not 
VM
exitVM
entry
VM
entry
L1→L2 entry virtualization L2→L1 exit virtualizationEmulated L1 →L2 VM entry Emulated L2 →L1 VM exit 
Figure 22.2:  Example of L1 →L2 VM Entry and Exit  
 TDG.VP.ENTER Inputs and Outputs  
Intel SDM, Vol. 3, 24.7.2  VM-Exit Controls for MSRs  
Intel SDM, Vol. 3, 24.8.2  VM-Entry Controls for MSRs  5 
Intel SDM, Vol. 3, 26.4  Loading MSRs  
Intel SDM, Vol. 3, 27.4  Saving MSRs  
Intel ConfidentialFixed -Format L2 VCPU State Buffer
RAX Value
…
R15 Value
RFLAGS value
RIP value
SSP value
GUEST_INTERRUPT_STATUSFixed -Format Values Returned in GPRs
Exit Reason
Exit Qualification
…
Interruption InformationTDG.VP.ENTERInput to 
L2 VM 
EntryOutput 
from L2 
VM ExitFixed -Format Inputs in GPRs
VM_INDEX
DO_INVEPT
…
 
Figure 22.3:  TDG.VP.ENTER Inputs and Outputs  
22.2.1.1.1.  Fixed -Format L2 Entry Guest State Buffer  10 
The state of the L2 GPR s, RFLAGS, RIP and SSP  and the L2 guest interrupt state is provided in a fixed -formal 
L2_ENTER_GUEST_STATE  buffer in the L1 VPCU’s private memory.  Immediately before L2 VM entry, TDG.VP.ENTER reads 
this buffer and sets the applicable L2 guest state values .  After L2 VM exit, if an L2→L1 exit or a TD exit is to be done, the 
TDX module  writes the L2_ENTER_GUEST_STATE  buffer with the current guest state  values.   The 
L2_ENTER_GUEST_STATE  format is defined in the [ TDX Module ABI Spec ]. 15 
22.2.1.1.2.  L2 VM Exit Information  
On L2→L1 VM exit, the most useful VM exit information fields are provided as GPR output values .  These include the 
following:  
• VM e xit reason  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 29 of 52 
Section 2:  TD Partitioning Architecture  • VM e xit qualification  
• Guest linear address  
• Guest physical address  
• GPA  
• VM-exit interruption information  5 
• IDT-vectoring information  
• VM-exit instruction information  
• Guest CS information (base, selector, limit and access rights)  
• Current privilege level (CPL)  
For details, see the TDG.VP.ENTER definition in the [ TDX Module ABI Spec ]. 10 
 L2 State Preservation Across L1 -to-L2-to-L1 Transitions (TDG.VP.ENTER)  
Intel SDM, Vol. 3, 23.4.1  Guest -State Area  
A subset of the L 2 VCPU  state is preserved across  L2 VM exit and subsequent L2 VM entry transitions.  The preserved 
state includes the following  fields, which are the fields supported by the L2 VMCS guest state area : 
• CR0, CR3, CR4, DR7, RSP, RFLAGS  15 
• CS, DS, ES, FS, GS, SS, LDTR, TR, GDTR, IDTR  
• MSRs that are stored in VMCS guest state : 
o IA32_DEBUGCTL  
o IA32_SYSENTER_CS  
o IA32_SYSENTER_ESP  20 
o IA32_SYSENTER_EIP  
o IA32_PERF_GLOBAL_CTRL (if the TD  is allowed to use it, i.e.,  ATTRIBUTES.PERFMON is 1)  
o IA32_PAT  
o IA32_EFER  
o IA32_RTIT_CTL (if the TD  is allowed to use it, i.e.,  XFAM[8]  is 1) 25 
o IA32_S_CET  (if the TD  is allowed to use it, i.e.,  XFAM[12:11]  are 11) 
o IA32_INTERRUPT_SSP_TABLE_ADDR (if the TD  is allowed to use it, i.e.,  XFAM[12:11]  are 11) 
o IA32_PKRS  (if the TD  is allowed to use it, i.e.,  ATTRIBUTES. PKS is 1) 
o IA32_SPEC_CTRL  
The L1 VMM is responsible for preserving other L 2 VCPU  state  after L2→L1 VM exit (termination of previous 30 
TDG.VP.ENTER) and restoring it  before invoking TDG.VP.ENTER.  
 L2 VM Exit Handling  
On VM exit from an L2, the TDX module examines the VM exit information and decides on a proper way to handle the 
VM exit , which may be one of the following : 
Local Flow:  Handle the L2 VM exit locally and resume the VCPU  in L2 mode .  An example of this case is #GP(0)  injection  35 
on a WRMSR VM exit from L2 . 
L2→L1 Exit:  Handle the L2 VM exit as an L2 →L1 VM exit and resume the VCPU in L1 mode .  Examples of this case are 
CPUID handling ( 23.9 ) and posted interrupt handling.  
TD Exit:  Handle the L2 VM exit as a TD exit to the host VMM.  An example of this case is physical NMI handling.  
 L2-to-L1 VM Exit:  Returned L2 State  40 
On L2 VM exit which  results in a virtual L2 →L1 VM exit, the TDX module completes the TDG.VP.ENTER operation as 
follows:  
• The TDX module dumps the content of GPRs , RFLAGS, RIP and SSP   to the fixed -format L2_ENTER_GUEST_STATE  
provided by the L1 VMM.  
• The TDX module reads the fixed -format VM exit information (VM -exit reason etc.) from the L2 VMCS and returns 45 
them in GPRs.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 30 of 52 
Section 2:  TD Partitioning Architecture  22.2.2.  Direct Asynchronous TD Exit from L2 , and Subsequent TD Entry  
 Asynchronous TD Exit from L2  
On VM exit from L2, multiple VM exit reasons lead to a TD exit to the host VMM.  In such cases , these events have no 
meaning for the TD.  They may be  physical in nature (interrupts, NMI, machine check etc.) , or they may be logical (e.g., 
EPT violation) but the TDX module determines they are a in the responsibility of the host VMM . 5 
Before exiting to the host VMM , the TDX module does the following:  
• The TDX module saves the CPU state into TDVPS; this would become the VCPU L1 state if a subsequent TD entry 
causes a virtual L2 →L1 VM entry as described below.  The identity of the exited L2 VM is recorded in 
TDVPS. CURR _VM . 
• The TDX module write s the TDG.VP.ENTER output memory operands , e.g., L2_ENTER_GUEST_STATE .  This is required 10 
since memory operands are specified by GPA.  GPA →HPA translation may no longer be valid (e.g., the page may be 
removed by the host VMM) once TD exit is done and TLB tracking variables have been update d.  For details of 
GPA→HPA translation tracking, see the [TDX Module Base Spec].  
The outputs of TDH.VP.ENTER indicate the VM and VCPU index to the host VMM.  For details, see the [ TDX Module ABI 
Spec ]. 15 
 VCPU Resumption to L2 on TD Entry following a TD Exit  from L2  
By default, the TDH.VP.ENTER following a TD exit from an L2 resumes that VCPU in L2. 
The TDX module restores the VCPU L2 state from the TDV PS, where it was saved before TD exit.  
TD VCPU
TDX
Module
L0L1
Host 
VMML2
1.Associate VCPU
2.Update TLB tracking
3.Restore non -VMCS CPU state 
from TDVPS
4.VMLAUNCH /VMRESUME 1.Examine exit reason, decide 
on async TD exit
3.Save non -VMCS CPU state in 
TDVPSVM
exitVM
entry
SEAMRET
TDH.VP.ENTER Handle TD Exit
 
Figure 22.4:  Example of Direct TD Exit from L2 and TD Entry Back to L2  20 
22.2.3.  TDG.VP.VMCALL:  Synchronous TD Exit from L2 and Subsequent TD Entry  
TDG.VP.VMCALL may be invoked by an L2  VM, if TDVPS.L2_CTLS[VM]. ENABLE_TDVMCALL  has been set to 1 by the L1 
VMM.   The behavior is similar to TDG.VP.VMCALL invoked by L1 .  The TDX module saves and restores the CPU state 
to/from TDVPS.  TD entry following a TDG.VP.VMCALL resumes the VM that exited , unless routing to L1 has been 
requested by the host VMM, as described below.  25 
Note:  The L1 VMM has no control how the L2 VM uses TDG.VP.VMCALL.  L1 should only set 
TDVPS .L2_CTLS[VM]. ENABLE_TDVMCALL  if it trusts the L2 VM to work correctly (e.g., to understand that any 
response from the host VMM is untrusted).  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 31 of 52 
Section 2:  TD Partitioning Architecture  22.2.4.  TD Exit from L2 Routed by the Host VMM to L1 on Subsequent TD Entry  
When resuming the TD after a TD exit, the host VMM can request that L1 will be resumed, by setting the RESUME_L1 
input flag of TDH.VP.ENTER.  From the point of view of the L1 VMM, the L2 →Host→L1 transition looks as a normal L2 →L1 
VM exit, except the completion status of TDG.VP.ENTER indicates TDX_L2_EXIT_HOST_ROUTED.  
If resuming into L1 after a synchronous (TDG.VP.VMCALL) TD exit , L1 is resumed (i.e., the TDG.VP.ENTER it has invoked is 5 
terminated) with a TDX_L2_EXIT_HOST_ROUTED_TDVMCALL status.  The L2 VCPU state reflects the successful 
completion of TDG.VP.VMCALL.  
RESUME_L1  is sticky.  If resumption of L1 encountered a problem that required a TD exit (e.g., an EPT violation) the 
following TD entry resumes L1 and provides the same TDX_L2_EXIT_HOST_ROUTED status.  
 Asynchronous TD Exit from L2 Routed to L1  10 
A possible use case is TD exit due to an interrupt, where this was requested by the L1 VMM for, e.g., L2 VPUs rendezvous.  
TD VCPU
TDX
Module
L0L1
Host 
VMML2
1.Restore non -VMCS CPU state 
from TDVPS
2.Update VCPU TLB tracking
4.VMLAUNCH/VMRESUME 1.Examine exit reason, decide 
TDVPSVM
exit
VM
entry
SEAMRET
(RESUME_L1)Emulated L2 →L1 VM exit
TDG.VP.
VMCALL
Request 
Virtual IPIIPI
Write 
local 
APIC
 
Figure 22.5:  Example of Direct TD Exit from L2 and TD Entry Back to L1  
In this case, the TDX module emulates the L2 →L1 VM exit behavior:

TD VCPU
TDX
Module
L0L1
Host 
VMML2
from TDVPS
TDVPSVM
exit
VM
entry
SEAMRET
TDG.VP.
VMCALL
Request 
Write 
local 
APIC
 
In this case, the TDX module emulates the L2 →L1 VM exit behavior:  
• The TDX module has already written the output memory operands of TDG.VP.ENTER as part of the TD exit from L2, 15 
as described above.  
• The TDX module updates the output GPR operands (exit information etc.) of TDG.VP.ENTER, based on the L2 VMCS.  
• TLB tracking is updated as described in the [ TDX Module Base Spec ]. 
 Synchronous (TDG.VP.VMCALL) TD Exit from L2 Routed to L1  
A possible use case if for some service requested by the L2 VM from the host VMM, which needs to be handled by the L1 20 
VMM as soon as possible after TD resumption.  
On TD entry, if the last TD exit was due to a TDG.VP.VMCALL from L2, and L1 is to be resumed, the TDX module first 
updates the L2 VCPU state as if TDG.VP.VMCALL was completed, then emulates an L2 →L1 exit.  L2’s GPR and XMM values 
are as returned by the host VMM, and RIP is advanced to the next L2 instruction.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 32 of 52 
Section 2:  TD Partitioning Architecture  22.3. L1 Posted Interrupts Handling  for TD Partitioning  
Intel SDM, Vol. 3, 29.2.1  Evaluation of Pending Virtual Interrupts  
Intel SDM, Vol. 3, 29.2.2  Virtual -Interrupt Delivery  
Intel SDM, Vol. 3, 30.6  Posted -Interrupt Processing  
22.3.1.  Overview  5 
TDX supports posting interrupts only to the L1 VMM.  When a posted -interrupt notification vector is recognized in TDX 
non-root mode, there are be three possible cases:  
• If a TD VCPU is currently running on the LP in the L1 VMM, the CPU processes the posted -interrupt descriptor as 
described in the [Intel SDM].  This case is described in the [TDX Module Base Spec].  
• During the TDG.VP.ENTER flow, if the TDX module recognizes that there is a pending posted interrupt to the L1 VMM, 10 
it aborts the L1 →L2 entry and resumes L1.  The CPU can then process the interrupt.  
• If a TD VCPU is currently running on the LP in an L2 VM, the notification vector is recognized as a normal external 
interrupt, causing a VM exit to the TDX module.  TDX module emulates the CPU’s posted interrupt injection to the 
L1 VMM.  
22.3.2.  Pending  L1 Posted Interrupt during L1-to-L2 Entry  15 
Typically, the L1 VMM will disable interrupts  delivery  (clear RFLAGS.IF) before invoking TDG.VP.ENTER to start an L1 →L2 
entry.  If a notification interrupt is delivered after RFLAGS.IF is cleared but before TDG.VP.ENTER runs, that interrupt  gets 
processed by the CPU as described in [ Intel SDM, Vol. 3, 30.6 ], but the posted virtual interrupt doesn’t get delivered yet.  
That interrupt will only be delivered once L1 resumes running.  
To prevent long interrupt latency, the TDX module detects whether there is a pending virtual interrupt during the 20 
TDG.VP.ENTER flow.  In that case, it terminates TDG.VP.ENTER and returns to L1, with a status code indicating 
TDX_PENDING_INTERRUPT .  Once running in L1 and RFLAGS.IF is set, the CPU evaluates the posted virtual interrupt vs. 
the LP’s interruptibility state and delivers it.  The L1 software doesn’t need to directly handle the L2 →L1 exit.  
TD VCPU
TDX 
ModuleL1
Host VMM 
or DeviceL2
Notification 
Interrupt NV
Post Virtual 
Interrupt PV:
Write bits 
PID.PIR[PV] 
and PID.ONTDG.VP.ENTERCPU processes the 
notification, evaluates PID 
but doesn’t deliver virtual 
interrupt
Generate 
NotificationHost VMMRFLAGS.IF = 0
Return 
TDX_PENDING_INTERRUPT 
status
Check L1 virtual RVI 
vs. L1 virtual PPRCPU delivers virtual 
interrupt
RFLAGS.IF = 1Interrupt 
Handler
 
Figure 22.6:  Pending L1 Posted Interrupt Detection during L1 -to-L2 Entry  25 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 33 of 52 
Section 2:  TD Partitioning Architecture  22.3.3.  L1 Posted Interrupt Received during L2 Run Time  
If an interrupt is posted to the L1 VMM while an L2 VM is running, there’s a need to resume L1 operation as soon as 
possible to prevent long latencies.  To do that, the TDX module emulates the CPU operation for posted interrupt 
notification, as described b elow.  
1. The physical notification interrupt received by the LP when a VCPU is running in L2 causes a VM exit to the TDX 5 
module.  
1.1. Equivalent to [ Intel SDM, Vol. 3, 30.6 , step 1 ]:  The LP acknowledges the local APIC  
2. On VM exit, the TDX module  processes the posted interrupt by emulating the CPU behavior as described in [ Intel 
SDM, Vol. 3, 30.6 , step s 2 through 7].  
2.1. If the physical interrupt vector is different than the L1 VMM’s notification vector, this is handled as a normal 10 
interrupt by a TD exit to the host VMM.  
2.2. If the posted interrupt’s priority is not higher than the L1 VMM’s current priority (in virtual PPR), then the L2 
VM is resumed.  
2.3. The TDX module emulates an L2 →L1 exit.  The returned completion code of TDG.VP.ENTER indicates 
TDX_L2_EXIT_PENDING_INTERRUPT . 15 
2.4. Once running in L1, the CPU evaluates the posted virtual interrupt vs. the LP’s interruptibility state and delivers 
it.  The L1 software doesn’t need to directly handle the L2 →L1 exit.   
TD VCPU
TDX 
ModuleL1
Host VMM 
VM 
EntryEmulated
L2→L1exit
1.Check inter. vector vs. NV
2.If (vector != NV), TD exit
3.Process posted interrupt in PID (emulate the 
CPU operation)
4.Evaluate pending virtual interrupt (emulate 
the CPU operation)VM exit
(ext. interrupt NV)
If (vector != NV),
TD exitIf PV priority is not 
higher than L1 VPPR,
Resume L2 VM
Write bits 
and PID.ONNotification 
Interrupt NVOn VM entry, 
CPU evaluates 
PID
Host VMMCPU processes the notification 
as a normal h/w interrupt, 
causing a VM exit
Generate 
NotificationCPU delivers virtual 
interrupt
Handler
 
Figure 22.7:  L1 Posted Interrupt Received during L2 Run T ime 
22.3.4.  L1 Posted Interrupt Received before Host -to-L2 Entry  20 
Typically, the host VMM runs with interrupts disabled.  If a posted interrupt notification is received when the host VMM 
is running, it is not immediately recognized;  it is only recognized after TD entry.  If the TD entry is to an L2 VM, the pos ted 
interr upt notification is processed as described above, typically ending in an L2 →L1 exit where the L1 VMM can handle 
the posted interrupt.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 34 of 52 
TD VCPU
TDX 
ModuleL1
Host VMM 
VM 
L2→L1exit
Write bits 
and PID.ONInterrupt 
Handler
Interrupt NVOn VM entry, CPU evaluates 
PID and delivers virtual 
interrupt PV
Generate 
NotificationTDH.VP.ENTERResume L2VM 
Entry
Host VMM runs with 
interrupts disabled
 
Figure 22.8:  L1 Posted Interrupt Received before Host -to-L2 Entry  
22.4. L2 VM TLB Address Space Identifier (ASID)  
See the [TDX Module Base Spec] .  Note the following points:  
• Each VM within a TD has its own EPTP, and thus its own ASID.  5 
• INVEPT, used by the TDX module as part of, e.g., TDH.VP.FLUSH, is required to be done for the EPTP of each VM 
within the TD . TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 35 of 52 
Section 2:  TD Partitioning Architecture  23. L2 VM CPU Virtualization ( Non -Root Mode Operation ) 
This chapter describes  how the Intel TDX module virtualize s the CPU to a guest TD.  
23.1. General Aspects of L1 Operation as a VMM  
23.1.1.  L1 VMM Usage of VMX Facilities  
VMX Instructions  5 
VMX instructions are not directly available to the L1 VMM.  This is indicated by CR4.VMXE (bit 13) value being 0.  Instead, 
it uses interface functions provided by the TDX module.  
• To enter into L2 VM operation, the L1 VMM invokes TDG.VP.ENTER.  
• To read and write L2 VMCS, the L1 VMM uses TDG.VP.RD and TDG.VP.WR.  
• To flush cached L2 EPT translations, the L1 VMM uses TDG.VP.INVEPT or TDG.VP.ENTER.  10 
L2 VMCS  
L2 VMCS is accessible to the L1 VMM using the metadata access interface functions TDG.VP.RD and TDG.VP.WR.   The 
TDX module controls which L2 VMCS fields can be written.  In addition, selected L2 VMCS fields are provided as 
TDG.VP.ENTER inputs and outputs.  
L2 VMCS fields, as visible to the L1 VMM, are virtual.  E.g., addresses are Guest -Physical Addresses (GPAs).  The TDX 15 
module translates the virtual values to real values stored in the L2 VMCS and used by the CPU.  
Other VMX Control Structures  
• The L2 MSR bitmaps page is not directly accessible to the L1 VMM.  Instead, it used TDG.VP.RD and TDG.VP.WR to 
access it.

L2 VMCS  
access it.  
• The L2 Virtual APIC page is mapped in the L1 VMM’s GPA space as a private page and  is directly accessible to the L1 20 
VMM.  The L1 VMM configures the address by writing its GPA to the L2 VMCS’ virtual -APIC address  field.  
• The L2 secure EPT is not directly accessible to the L1 VMM.  The L1 VMM controls L2 GPA mapping attributes (but 
not GPA -to-HPA translations) using TDG.MEM.PAGE.ATTR.WR.  
23.1.2.  Enumeration of VMX Capabilities Available to the L1 VMM  
Intel SDM, Vol. 3, Appendix A  VMX Capability Reporting Facility  25 
The virtual values of IA32_VMX_* MSRs enumerate VMX capabilities available to the L1 VMM.  Not all bits are applicable 
since, e.g., VMX instructions and EPT management are done indirectly via TDX module functions.  
Table 23.1:  Enumeration of VMX Capabilities Available to the L1 VMM  
MSR Name  MSR 
Index  Description  
IA32_VMX_BASIC  0x0480  For details, see the [ TDX Module ABI Spec ]. 
IA32_VMX_MISC  0x0485  For details, see the [ TDX Module ABI Spec ]. 
IA32_VMX_PINBASED_CTLS  0x0481  These MSRs are not used; read access results in a #VE.  Use the 
IA32_VMX_TRUE_* MSRs listed below.  IA32_VMX_PROCBASED_CTLS  0x0482  
IA32_VMX_EXIT_CTLS  0x0483  
IA32_VMX_ENTRY_CTLS  0x0484  
IA32_VMX_TRUE_PINBASED_CTLS  0x048D  
IA32_VMX_TRUE_PROCBASED_CTLS  0x048E  
IA32_VMX_PROCBASED_CTLS2  0x048B  
IA32_VMX_PROCBASED_CTLS3  0x0492  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 36 of 52 
Section 2:  TD Partitioning Architecture  MSR Name  MSR 
IA32_VMX_TRUE_EXIT_CTLS  0x048F  These MSRs enumerate L2 VMCS fields that are either fixed -0, 
fixed -1 or that can be modified by the L1 VMM.  The virtual 
values depend on the values supported by the CPU (i.e., the 
native values of the same MSRs) and on the TD configuration.   
See the section below describing non -standard behavior of 
those MSRs.  
 IA32_VMX_EXIT_CTLS 2 0x0493  
IA32_VMX_TRUE_ENTRY_CTLS  0x0490  
IA32_VMX_CR0_FIXED0  0x0486  
IA32_VMX_CR0_FIXED1  0x0487  
IA32_VMX_CR4_FIXED0  0x0488  
IA32_VMX_CR4_FIXED1  0x0489  
IA32_VMX_VMCS_ENUM  0x048A  This MSR is not used; read access results in a #VE.   
IA32_VMX_EPT_VPID_CAP  0x048C  For details, see the [ TDX Module ABI Spec ]. 
IA32_VMX_VMFUNC  0x0491  Virtualized as 0.  
 
Non -Standard Behavior of Virtual IA32_VMX_* MSRs  
In multiple cases, the L2 VMCS bit values are set based on the TD configuration and are not writable by the host VMM.  
For example, the L2 VMCS’ tertiary processor -based execution controls bit 5 (GPAW) is set based on the TD’s GPAW 
configuration; the L1 VMM can’t modify the value of thi s bit.  Such bits are enumerated by the applicable IA32_VMX_* 5 
MSR as fixed -0, even though their value may be 1.  This mean that the L1 VMM must not attempt to modify their value.  
When writing to such L2 VMCS fields using TDG.VP.WR, the L1 VMM may use the write mask parameter to avoid 
modifying any bit that is enumerated as either fixed -0 or fixed -1. 
23.1.3.  Unit Conversion  
As a rule, L1 VMM access to L2 VMCS fields and TD migration of L2 VMCS fields use virtual units (e.g., GPA, TSC ticks etc.).  10 
The values are converted to/from native units (e.g., HPA) when the L2 VMCS is written/read.  
L2 VMCS Fields Specified as Physical Address  
L2 VMCS fields that are specified as physical address are converted to/from GPA when read/written by the L1 VMM.  GPA 
to HPA conversion is discussed in [REF].  
L2 VMCS Fields Specified as TSC Ticks  15 
L2 VMCS fields that are specified using TSC tick units are converted to/from virtual TSC units when read/written by the 
L1 VMM.  Those fields are migrated using virtual TSC units so similar conversion is done for export/import.  The same 
fields are not con verted when read/written by the host VMM (for debuggable TDs) – the real h/w units are used.  These 
fields include:  
• PLE_Gap  20 
• PLE_Window  
L2 VMCS Fields Specified as Crystal Clock Ticks  
L2 VMCS fields that are specified using crystal clock tick units, as enumerated by CPUID(0x15), are converted to/from 
virtual crystal clock units when read/written by the L1 VMM.  Those fields are migrated using virtual crystal clock units so 
similar conve rsion is done for export/import.  The same fields are not converted when read/written by the host VMM – 25 
the real h/w units are used.  These fields include:  
• Instruction Timeout Control  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 37 of 52 
Section 2:  TD Partitioning Architecture  23.1.4.  L2-to-L1 VM Exit Handling  
Intel SDM, Vol. 3, 27.2.3  Information About NMI Unblocking Due to IRET  
Intel SDM, Vol. 3, 27.2.4  Information for VM Exits During Event Delivery  
The L1 VMM is expected to handle special L2 VM exit conditions that may occur in the Intel VMX architecture, such as:  
• Handling of NMI unblocking due to IRET, e.g., re -blocking NMI by updating the L2 VMCS’ guest interruptibility state  5 
field.  
• Handling of VM exit during event delivery , e.g., re -injecting the event to L2 based on the L2 VMCS ’ IDT-vectoring 
information  field etc. 
Such conditions are handled by the TDX module itself if a VM exit from L2 results in a local flow that ends by VM entry 
back into L2.  10 
23.2. L2 VM VCPU  Initial  State  
The TDX module initializes the L2 VM state of each VCPU as part of the VCPU initialization (TDH.VP.INIT).  The initial state 
is detailed in the [ TDX Module ABI Spec ]. 
The L1 VMM is responsible for properly setting  the VCPU L2 state  to the desired values, by writing to the TDVPS (including 
L2 VMCS) using the TDG.VP.WR* interface functions.  15 
23.3. L2 VM  Run Time Environment Enumeration  
The TDX module does not implement any special behavior.  The L1 VMM may virtualize CPUID leaves/sub -leaves and 
MSRs to enumerate the run time environment for its guest L2 VMs.  
23.4. L2 VM CPU Mode Restrictions  
Intel SDM, Vol. 3, 2.2  Modes of Operation  20 
Intel SDM, Vol. 3, 9.8.5  Initializing IA -32e Mode  
Intel SDM, Vol. 3, 11.5.1  Cache Control Registers and Bits  
Intel SDM, Vol. 3, 24.6.6  Guest/Host Masks and Read Shadows for CR0 and CR4  
An L2 VM r unning in TDX non -root mode may use any CPU mode available in VMX non -root mode . 
Table 23.2:  L2 VM CPU Mode Restrictions  25 
Restriction  L2 VM  
CPU and Paging 
Modes  The CPU is allowed to run in the following modes:  
• Real mode  
• Protected mode (32 -bit) with or without paging  
• IA-32e mode with paging, with the sub -modes controlled by CS.L:  
o 64-bit mode  
o Compatibility (32 -bit) mode  
Contrary to L1 VMs, CR0.PE and IA32_EFER.LME are not enforced by the TDX module.  
The L1 VMM may enforce them.  
Execute Disable  When running in IA -32e mode, the PT Execute Disable bit (63) is always enabled.  
To achieve this, IA32_EFER.NXE is enforced  to 1 , as described in the following sections.  
Caching is Always 
Enabled  The L2 VM runs in Normal Cache Mode . 
To achieve this, CR0.CD and CR0.NW are enforced to 0, as described in the following 
sections.  
The L1 VMM may set the L2 VMCS’ CR0 guest/host mask and read shadow execution 
control such that the L2 VM may attempt to set CR0.CD and CR0.NW and sees their 
virtual value as if setting was successful.  
See the following sections for details.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 38 of 52 
Section 2:  TD Partitioning Architecture   
23.5. L2 VM VCPU  Instructions Restrictions  
TDX rules for CPU instructions restrictions apply to the whole TD, i.e., i nstructions that are always blocked in the L1 VM 
are also blocked in the L2 VM .  The L1 VMM may configure further restrictions.    
Instructions  may be blocked depending on VCPU features enabled by the L1 VMM , which may virtualize CRs and MSRs to 5 
its L2 VMs.  The L1 VMM is responsible for proper feature enumeration to the L2 VM, by virtualized CPUID, CR4 and MSRs .  
The TDX module  restricts this virtualization based on the overall TD restrictions , as described in the following sections.  
23.5.1.  Mechanisms of Blocking  
• In some cases, the CPU will block (#UD) instructions based on VMX controls, CRs, MSRs and XCR0  
• In other cases, execution of instructions causes a VM exit  to the TDX module.  By default, the TDX module emulates 10 
an L2 VM exit to the L1 VMM.  
23.5.2.  Instructions that Cause an L2 -to-L1 Exit Unconditionally  
Intel SDM, Vol. 3, 25.1.2  Instructions That Cause VM Exits Unconditionally  
• Instructions that architecturally cause VM exit unconditionally:  CPUID, GETSEC, INVD, XSETBV, INVEPT, INVVPID,  
VMCALL, VMCLEAR, VMLAUNCH, VMPTRLD, VMPTRST, VMRESUME, VMXOFF, and VMXON  15 
• VMFUNC, VMREAD  and VMWRITE  
• RSM  
• SEAMCALL  
• ENCLS, ENCLV  
23.5.3.  Instructions that Cause a #UD Unconditionally  20 
• SEAMRET  
23.5.4.  Instructions that Cause an L2 -to-L1 Exit 
• String I/O (INS*, OUTS*), IN, OUT  
• HLT 
• MONITOR, MWAIT  25 
• WBINVD, INVD

• RSM  
• SEAMCALL  
• SEAMRET  
• HLT 
• WBINVD, INVD  
23.5.5.  Other Cases  of Unconditionally Blocked Instructions  
• Guest TD execution of PCONFIG results in  a #UD,  #VE or an L2→L1 VM Exit .  See 23.15  for details.  
• Guest TD execution of ENQCMD results in a #GP(0).  
• Guest TD execution of ENQCMDS when CPL is 0 results in an L2 VM exit to the L1 VMM.  Otherwise,  it results in a 30 
#GP(0).  
23.6. L2 VM Extended Feature Set  
At the whole guest TD scope, TDCS.XFAM (Extended Features Allowed Mask)  is provided as an input during guest TD 
build process.  The L1 VMM may allow its L2 VMs any subset  of the TD’s extended features allowed by XFAM . 
L1 VMM is responsible for context -switching:   saving extended state (XSAVES) before L2 VCPU entry  and r estoring it 35 
(XRSTORS) after exit . 
CR4 virtualization, MSR virtualization and instructions virtualization are discussed in the following sections .  The 
architecture helps ensure  that the L1 VMM can only enable features that are enabled for the whole TD . TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 39 of 52 
Section 2:  TD Partitioning Architecture  23.7. L2 VM CR Handling  
23.7.1.  CR0 and CR4  
Intel SDM, Vol. 3, 2.5 Control Registers  
Intel SDM, Vol. 3, 23.8  Restrictions on VMX Operation  
Intel SDM, Vol. 3, 24.6.6  Guest/Host Masks and Read Shadows for CR0 and CR4  5 
Intel SDM, Vol. 3, 25.6 Unrestricted Guests  
 Background:  CR0 and CR4 Execution Controls  
The VMCS CR0 and C4 VM -execution control fields include guest/host masks  and read shadows . 
Guest/host mask bits set to 1 correspond to bits “owned” by the host:  
• A guest attempt to set host -owned CR bit X to a value differing from bit X of the corresponding read shadow causes 10 
a VM exit.  
• Guest reads return values for host -owned bits from the corresponding read shadow.  
Guest/host mask bits cleared to 0 correspond to bits “owned” by the guest:  
• A guest attempt to modify guest -owned bit X succeeds.  
• Guest reads return values for guest -owned bits from the CR itself.  15 
For TDX, the real host is always the TDX module.  For TD Partitioning, the TDX module virtualizes the guest/host behavior 
so that the L1 VMM can configure itself as the host of L2 VM’s CR0/4  bits.  
 CR0 and CR4 Enumeration to the L1 VMM  
The virtual values of  IA32_VMX_CR 0/4_FIXED 0/1 MSRs, to enumerate to the L1 VMM which L2 guest ’s CR bits may be 
freely set , and which bits must be fixed as 0 or as 1 .  Bits enumerated as f ixed-0 or fixed -1 bits are considered to be owned 20 
by the TDX module.  O ther bits are owned by the TD (L1 VMM ). 
Enumeration is based on the following:  
• Platform capabilities, as enumerated by the real values of the same MSRs  
• Bits known to the TDX module as reserved  
• TDX architecture restrictions  25 
• TD configuration  
The table below lists CR0 bits whose enumeration is impacted by the TDX architecture and the TD configuration.  
Table 23.3:  L2 VM CR0 Enumeration to the L1 VMM  (by IA32_VMX_CR 0_FIXED 0/1)  
Bit Name  Condition  
5 NE Enumerated as fixed -1 
29 NW Enumerated as fixed -0 
30 CD Enumerated as fixed -0 
31 PG Enumerated as non -fixed  
 
The table below lists CR4 bits whose enumeration is impacted by the TDX architecture and the TD configuration.  30 
Table 23.4:  L2 VM CR4 Enumeration to the L1 VMM  (by IA32_VMX_CR 4_FIXED 0/1)  
Bit Name  Condition   
6 MCE  Enumerated as fixed -1 
13 VMXE  Enumerated as fixed -1 
14 SMXE  Enumerated as fixed -0 
19 KL If TDCS.ATTRIBUTES.KL is 0, enumerated as fixed -0 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 40 of 52 
Section 2:  TD Partitioning Architecture  Bit Name  Condition   
22 PKE If TDCS.XFAM[9] is 0, enumerated as fixed -0 
23 CET If TDCS.XFAM[12: 11] are 00, enumerated as fixed -0 
24 PKS If TDCS.ATTRIBUTES.PKS is 0, enumerated as fixed -0 
25 UINTR  If TDCS.XFAM[14] is 0, enumerated as fixed -0 
32 FRED  If virtual CPUID(0x7,1).EAX[17]  is 0, enumerated as fixed -0 
 
In addition to the above, CPUID  values  virtualized by the TDX module  enumerate the availability of multiple  CR0/CR4 bits, 
but not all of them . 
 L2 CR0/4 Initial Values  
For CR0, bits PE ( 0) and NE (5) are initialized to 1.  All the other bits are initialized to 0.  5 
For CR4, bits MCE (6) and VMXE (13)  are initialized to 1.  All the other bits are initialized to 0.  
23.7.2.  CR3 and CR8  
The L1 VMM can use the L2 VMCS controls to induce L2 →L1 exit on CR3 and/or CR8 loads and/or stores .  It has access to 
the guest CR3 and CR8 state .  The L1 VMM can also access L2 VMCS CR3-target values and CR3 -target count fields .  No 
special TDX module handling is required . 10 
23.8. L2 VM MSR Handling  
The L1 VMM configures MSR virtualization policy per VCPU per L2 VM by writing to the L2 MSR Bitmaps page,  which is 
part of TDVPS, page using  TDG.V M.WR.   The format is as specified in the [Intel SDM]:  a bit value of 1 indicates an L2 to 
L1 VM exit on MSR read or write.  A bit value of 0 indicates that no L2 to L1 VM exit is requested.  
The value written by the L1 VMM is actually saved in a shadow page.  The TDX module combines the L1 VMM’s policy 15 
with the whole TD’s MSR handling policy and sets the value in the real L2 MSR Bitmaps page, linked to the L2 VMCS and 
used by the CPU.  
Depending on the whole TD MSR virtualization policy, a VM exit to the TDX module may still happen.  In this case the TDX 
module may emulate the MSR access.  By default, in cases where for L1 it would inject a #VE, the TDX mod ule emulates 
an L2 to L1 VM exit .  This means that the L1 VMM must be ready to accept such VM exit even if it didn’t request them.  20 
The default value of the MS R exit bitmaps shadow page is all -1, i.e., L2→L1 exit on all MSR accesses.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 41 of 52 
Section 2:  TD Partitioning Architecture  Table 23.5:  Combining MSR Virtualization Policies (L2 VM  and Whole TD ) 
 Whole TD MSR Virtualization  Policy , Configured by the Host VMM  
 Direct CPU Access  MSR Virtualization  #VE 
TD MSR Exit Bitmap → 0 1 1 
L2 VM MSR 
Virtualization 
Policy, 
Configured 
by the L1 
VMM  
(Stored in 
the L2 MSR 
Exit Bitmaps 
Shadow  
Page)  0: 
No L2→L1 
Exit L2 MSR Exit 
Bitmap  → 0:  No VM exit  1:  VM exit  1:  VM exit  
L2 VCPU 
RD/WRMSR 
Handling  → RD/WRMSR executed 
by CPU  TDX module emulates 
MSR access .  May 
inject a #GP.  L2_TDX _VE_SUPPORT : 
If TDVPS.ENABLE_ 
EXTENDED_VE [VM] , 
inject #VE to L2.  
Else,  
TDX module emulates 
L2→L1 VM exit  
1:   
L2→L1 
Bitmap  → 1:  VM exit  1:  VM exit  1:  VM exit  
L2 VCPU 
RD/WRMSR 
Handling  → TDX module emulates 
L2→L1 VM exit  TDX module emulates 
 
The TDX module combines the VCPU -scope per -L2 VM’s MSR exit bitmaps shadow  page with the TD-scope  MSR exit 
bitmaps page by a bitwise -OR, to create an architectural L2 MSR exit bitmaps page, which is used by the CPU.   This 
operation is done on TD initialization and on L1 VMM writes to the L2 MSR exit bitmaps page . 5 
TDCS
TD MSR Exit 
BitmapsTDVPS
L2 MSR Exit 
Bitmaps 
Shadow
L2 MSR Exit 
Bitmaps
L2 VMCSPer L2 VMPer L2 VM
TDG.VP.WR
Bitwise ORPer TD
Per L2 VMTDH.MNG.INIT
Host VMML1 VMM
 
Figure 23.1:  MSR Virtualization Policy Configuration  
23.9. L2 VM CPUID Virtualization  
CPUID execution by an L2 VM results in a VM exit to the TDX module, which then emulates an L2 to L1 VM exit.  The L1 
VMM may then emulate the CPUID instruction and resume the L2 VM.  10 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 42 of 52 
TD VCPU
TDX 
ModuleL1
CPUID
EmulationL2
L2 VM Exit EmulationVM exit
VM EntryTDG.VP.ENTER
L2 VM Entry EmulationVM
entryCPUID
CPUID
VM
Entry
May be saved if L1 VMM 
caches CPUID informationEmulated L2 →L1 
VM exit (CPUID)Emulated L1→L2 
VM entry 
Figure 23.2:  L2 VM CPUID Virtualization  
23.10.  L2 VM Interrupt Handling and APIC Virtualizati on 
Intel SDM, Vol. 3, 2 4.6.8 Controls for APIC Virtualization  
Intel SDM, Vol. 3, 29  APIC Virtualization and Virtual Interrupts  5 
TDVPSL2 VMCS
Virtual APIC 
Address (HPA)L2 Virtual APIC
(GPA)L1 SEPT 
TranslationL2 Virtual APIC
Page
(in L1 GPA Space)L2 Virtualized
APIC Access Page
(in L2 GPA Space)
APIC Access 
Address (HPA)L2 APIC Access
(GPA)
Virtual
IA32_APIC_BASE
(GPA)L2 Virtual APIC
Page
(Physical Page)
TDG.VP .WR
L1 SEPT 
Translation
L2 APIC Base
(GPA)L2 SEPT 
TranslationTDG.VP .WRL2 Virtualized
(HPA, no actual 
access to 
memory at this 
address)L2 SEPT 
TranslationL1 SEPT 
TDG.VP .WRL1 View L2 View
L2 Virtualized APIC 
Access Page is 
required only if L2 
xAPIC mode is allowed
 
Figure 23.3:  APIC Virtualization  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 43 of 52

VM entry 
Page
(GPA)
Virtual
Page
TDG.VP .WR
L1 SEPT 
access to 
 
November 2023  . Page 43 of 52 
Section 2:  TD Partitioning Architecture  23.10.1.  L2 Virtual APIC Page Access by the L1 VMM  
Intel SDM, Vol. 3, 29.5  Virtualizing MSR -Based APIC Access  
The  L2 virtual APIC page is mapped in the L1 VMM’s GPA space and  is fully accessible to the L1 VMM.  
The L1 VMM specifies the virtual -APIC address, using TDG.VP.WR, as a private GPA in the L1 address space.  The GPA 
must be mapped in the L1 VMM’s SEPT.  The TDX module translates  this GPA to an HPA for configuring the L2 VMCS.  5 
The TDX module helps ensure  that the translated address is valid when the L2 VCPU runs , using the mechanism described 
in the [TDX Module Base Spec] . 
23.10.2.  L2 Virtual Local APIC Mode and Access by the L2 VM  
The Local APIC is virtualized to L2 V Ms in x2APIC mode (MSR access).  
23.10.3.  L2 Posted Interrupts  (Not Supported)  10 
Posting virtual interrupts to L2 VCPUs, either by the host VMM or I/O device, or by the L1 VMM, is not supported.   The 
L1 VMM can manipulate  the L2 VM’s Virtual APIC page to inject virtual interrupts.  
23.10.4.  Virtual NMI Injection  to L2 VCPU  
There is no provisioning for the host VMM to inject a virtual NMI to L2 VCPUs.  
The L1 VMM controls the L2 VMCS and can use the applicable fields (nmi -window exiting, VM -entry interruption 15 
information etc.) to inject a virtual NMI to L2 VCPUs.  
23.10.5.  Handling NMI Unblocking Due to IRET  
The L1 VMM is responsible for updating the L2 VM’s guest interruptibility state based on the indication of NMI unblocking 
due to IRET.  For VM exits due to faults, NMI unblocking due to IRET is indicated in bit 12 of the VM -exit interruption - 20 
information field.  For VM exits due to EPT violation , instruction timeout  and other reasons not applicable to TDX, it is 
indicated in bit 12 of the exit qualification.  For details, see the [Intel SDM].  
Note:  VM exits from L2 where no L2 →L1 exit happens are handled by the TDX module; the L1 VMM is not involved.  
23.11.  Vectored Events  
23.11.1.  Vector -on-Entry (VOE) Injection to L2  25 
Intel SDM, Vol. 3, 26.6.1  Vectored -Event Injection  
The L1 VMM can inject vectored event to an L2 VM using the L2 VMCS VM-entry interruption information , VM-entry 
exception error code and VM-entry instruction -length  fields.  
The L1 VMM can determine whether the event was injected successfully , based on TDG.VP.ENTER’s completion status 
and exit reason,  as follows:  30 
• If L2 VM entry fails for some reason (e.g., bad guest state) , VM-entry interruption -information remains valid and a 
subsequent L2 VM entry (e.g., after fixing bad guest state) will inject the event again .  The host VMM can determine 
this based on TDG.VP.ENTER’s completion status and exit reason.  
• If L2  VM entry succeeds but triggers a VM exit that occurs before the event is injected , this is the case of VM exit 
during event delivery via IDT, described below .  The L1 VMM typically reinjects the event.  35 
• In other cases, VM entry succeeds,  and the event is injected successfully .  Guest execution starts at the entry point 
for the handler of the injected event.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 44 of 52 
Section 2:  TD Partitioning Architecture  23.11.2.  L2-to-L1 Exit during Event Delivery via IDT  
Intel SDM, Vol. 3, 24.9.3  Information for VM Exits That Occur During Event Delivery  
Intel SDM, Vol. 3, 27.2 .4 Information for VM Exits during Event Delivery  
Intel SDM, Vol. 3, 26.5.1  Vectored -Event Injection  
The L1 VMM is responsible for handling the case where an L2 →L1 exit occurred during event delivery via IDT.  This is 5 
indicated by the  L2 VMCS  IDT-vectoring information  Valid bit (31) .  Typically, the L1 VMM re -injects the event using the 
L2 VMCS VM-entry interruption information , VM-entry exception error code and VM-entry instruction -length  fields.  
23.12.  Prevention  of L2 VM -Induced Denial of Service  
By default, h andling of L2 VM -induced denial of service is done the same way as that of the whole TD, as described in the 10 
[TDX Module Base Spec].  Bus lock detection and instruction timeout  VM exits cause a TD exit.  
23.13.  Time Stamp Counter  (TSC)  
23.13.1.  L2 VM TSC Virtualization  
The v irtual TSC frequency and value as seen by the L2 VM are the same as for the L1 VM M. 
The L2 VM has the same access restrictions to TSC MSRs as the L1 VM M.  It is not allowed to:  15 
• Write IA32_TIME_STAMP_COUNTER  
• Access IA32_TSC_ADJUST  
• Access IA32_TSC_DEADLINE  
Any access violation results in an L2→L1 VM. 
23.13.2.  L2 VM TSC Deadline Support  20 
Intel SDM, Vol. 3, 10.5.4.1  TSC-Deadline Mode  
Intel SDM, Vol. 3, 25.5.1  VMX -Preemption Timer  
Intel SDM, Vol.3, A.6  Miscellaneous Data  
The L1 VMM can set a n L2 execution  deadline, in absolute virtual TSC units.  If the L2 VCPU  is running when the deadline 
time arrives, it exits to the L1 VMM .  The TSC deadline is set using TDVPS.TSC_DEADLINE [VM]  using TDG.VP.WR.  This 25 
field has similar semantics to the IA32_TSC_DEADLINE MSR.  It provides a similar functionality as the MSR but  does not 
emulate its exact MSR behavior . 
Internally, the TDX module uses the L2 VMCS’ VMX -preemption timer fields; thus, VMX -preemption timer is not available 
directly to the L1 VMM.  
On return from TDG.VP.ENTER, the provided exit reason is VMX -preemption timer expired (52).  30 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 45 of 52 
TD VCPU
TDX
ModuleL1
Host 
VMML2 VM 
entry
flowL2
TDG.VP.ENTERVM
exit
VM
exitVM
entry
VM
entryEmulated L1 →L2 
VM entryEmulated L2 →L1 
VM exit
Set VMX 
preemption 
timerVM
exit
Set VMX 
timerVM
entry
L2 VM 
exitflowTDG.VP.WR(
TSC_DEALINE)Deadline
Write 
TDVPS .TSC_
DEADLINE
TDH.VP.ENTERTD
exit 
Figure 23.4:  TSC Deadline Handling  
Details  
• Setting TSC_DEADLINE to -1 disables its operation.  
• Setting TSC_DEADLINE to a value lower than the current virtual TSC value (e.g., 0) causes immediate L2 →L1 VM exit 5 
after L1→L2 VM entry.  
• If on L2 VM entry the TSC deadline is in the past (e.g., in the example above, the deadline passed while the host VMM 
was executing), VM entry into L2 will immediately result in a VM exit and the TDX module will emulate an L2 →L1 
exit.  
23.14.  Supervisor Protection Keys (PKS)  10 
By design, guest TD usage of Supervisor Protection Keys (PKS) is controlled by the ATTRIBUTES.PKS bit.  When PKS is 
supported by the CPU and ATTRIBUTES.PKS is set to 1, the L1 VMM may enable PKS for its L2 VMs  as follows:  
• Virtualize CPUID to enumerate PKS availability to the L2 VM.  
• Enable L2 VM setting CR4.PKS flag  by setting the L2 VMCS’ “CR4 guest/host mask” and “CR4 read shadow” fields.  
• Allow L2 VM access to the IA32_PKRS MSR  by setting the L2 MSR exit bitmaps.  The TDX module sets  L2 VMCS “load 15 
guest PKRS” control to context -switch the IA32_PKRS MSR.  
23.15.  Intel ® Total Memory Encryption ( Intel ® TME) and Multi -Key Total Memory Encryption 
(MKTME)  
Guest TDs may not directly use the Intel TME and MKTME MSRs and the PCONFIG instruction.  The Intel TDX module  
supports para -virtualiz ation of this ISA  for L2 V Ms, as described below.  20 
23.15.1.  TME Virtualization  
TME is enumerated by CPUID(0x7, 0x0).ECX[13].  The host VMM can configure the virtualization of this bit to the whole 
TD as enabled or disabled on TDH.MNG.INIT.  
The L1 VMM can virtualize CPUID(0x7, 0x0).ECX[13] to enumerate availability of TME to an L2 VM.  If TME is virtualized 
as enabled , then L2 VM  access to those MSRs causes  an L2→L1 VM exit . 25 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 46 of 52 
Section 2:  TD Partitioning Architecture  23.15.2.  MKTME Virtualization  
MKTME is enumerated by CPUID(0x7, 0x0).EDX[18].  The host VMM can configure the virtualization of this bit to the 
whole TD as enabled or disabled on TDH.MNG.INIT .  In both cases, MKTME is not actually enabled to the TD; the 
difference is in enabling para -virtualization of MKTME.  
The L1 VMM can virtualize CPUID(0x7, 0x0).EDX[18] to enumerate availability of MKTME to an L2 VM.  If MKTME is 5 
virtualized as enabled , the TDX module supports para -virtualization as follows.  The following operations cause an L2→L1 
VM exit : 
• L2 VM access to the IA32_MKTME_PARTITIONING MSR (0x87)  
• PCONFIG execution by the L2 VM  
If MKTME is virtualized as disabled, then : 10 
• Guest TD access to the IA32_MKTME_PARTITIONING MSR (0x87 ) causes  an L2→L1 VM exit . 
• PCONFIG execution by the L2 VM  causes  a #UD.  
23.16.  Management of Idle and Blocked Conditions  
Intel SDM, Vol. 3, 9.10  Management of Idle and Blocked Conditions

VM exit : 
Intel SDM, Vol. 3, 9.10  Management of Idle and Blocked Conditions  
23.16.1.  HLT Instruction  15 
HLT executed by an L2 VM results in an L2 →L1 exit.  
23.16.2.  PAUSE Instruction and PAUSE -Loop Exiting  
Intel SDM, Vol. 3, 25.1.3  Instructions That Cause VM Exits Conditionally  
L2 VMs can execute PAUSE.  The L1 VMM can set up PAUSE -loop exiting by using the L2 VMCS “PAUSE -loop exiting” , 
“PLE_Gap” and “PLE_Window”  VM-execution controls.  A PAUSE -loop VM exit from the L2 VM results in an L2 →L1 VM 20 
exit.  
23.16.3.  MONITOR and MWAIT Instructions  
By default, guest TDs are expected not to use MONITOR/MWAIT.  The virtual value of CPUID(1).ECX[3] is, by default, 0.  
Execution of MONITOR or MWAIT by an L2 VM results in an L2 →L1 exit.  
However, the host VMM may configure the guest TD to allow MONITOR/MWAIT, using the CPUID configuration table 25 
which is part the TD_PARAMS input to TDH.MNG.INIT.  Configuring the virtual value of CPUID(1).ECX[3] to 1 also enables 
the TD (and its L2 VMs) to execute MONITOR and MWAIT.  
23.16.4.  WAITPKG:  TPAUSE, UMONITOR and UMWAIT Instructions  
Intel SDM, Vol. 3, 26.1.3  Instructions That Cause VM Exits Conditionally  
As described in the [Base Spec], t he host VMM may allow guest TDs to use the TPAUSE, UMONITOR and UMWAIT 30 
instructions, if the CPU supports them, by configuring the virtual value of CPUID(7,0).ECX[5] (WAITPKG).  
If enabled, the L1 VMM has the following control over L2 VM execution:  
• The L1 VMM may control L2 VMs’ execution of TPAUSE, UMONITOR and UMWAIT instructions by writing to the L2 
VMCS’ secondary processor -based execution controls “enable user -level wait and pause” bit (26).  
• The L1 VMM may also configure an L2 →L1 exit on those instructions using the L2 VMCS’ primary processor -based 35 
execution controls “RDTSC exiting” bit (12).  
• The L1 VMM may configure L2 →L1 exit on read and/or write of IA32_UMWAIT_CONTROL (MSR 0xE1).  
23.17.  Other Changes in TDX Non -Root Mode  
23.17.1.  L2 VM Tasking  
Any task switch results in a n L2→L1 VM exit .  The L1 VMM can handle the task switch as it requires.  40 TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 47 of 52 
Section 2:  TD Partitioning Architecture  23.17.2.  L2 VM PAUSE -Loop Exiting  
The L1 VMM can set up PAUSE -loop exiting by using the L2 VMCS “PAUSE -loop exiting” , “PLE_Gap” and “PLE_Window”  
VM-execution control s.  A PAUSE -loop VM exit from the L2 VM results in an L2 →L1 VM exit.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 48 of 52 
Section 2:  TD Partitioning Architecture  24. L2 VM Debug and Profiling Architecture  
This chapter discusses how the Intel TDX module debug architecture is extended to support TD Partition ing.  The 
extended debug architecture includes the following debug facilities:  
On-L2 VM Debug : Facilities for debugging an L2 VM  using software that runs inside that VM  
L1 VMM Debug of L2 VM:  Facilities for debugging an L2 VM using software that runs inside the L1 VMM  5 
Off-TD Debug  of L2 VM : Facilities for debugging an L2 VM , which resides in a TD configured in debug mode, using 
software that runs outside the TD  
24.1. On-L2 VM  Debug  
Intel SDM, Vol. 3, 17  Debug, Branch Profile, TSC and Intel Resource Director Technology (Intel RDT) Features  
24.1.1.  Overview  10 
On-VM debug is the normal mode used to debug an L2 VM within a TD .  A debug agent resides inside the L2 VM , and it 
can interact with external entities (e.g., a debugger) via standard I/O interfaces.  It can also interact with other entities 
(e.g., a debugger) running in the L1 VMM or another L2 VM within the TD.  The Intel TDX module is designed to virtualize 
and isolate TD debug capabilities from the host VMM and other guest TDs or legacy VMs.  On -VM debug can be used for 
production or debug TDs – i.e., re gardless of the guest TD’s ATTRIBUTES.DEBUG state.  15 
As described in the [TDX Module Base FAS], g uest TDs are allowed to use almost all architectural debug and tracing 
features supported by the processor .  This applies to L2 VMs as well.  The L1 VMM may restrict the enumeration or 
enabling of debug and trace features to L2 VMs, using the standard VMX capabilities available to it.  
24.1.2.  Generic Debug Handling  
 Context Switch  20 
Context -switch for TD exits directly from an L2 VM and TD entry back to an L2 VM is handled the same way as context 
switch for the TD as a whole, as described in the [TDX Module Base FAS].  
 IA32_DEBUGCTL MSR Virtualization  
IA32_DEBUGCTL MSR is virtualized for L2 VMs similarly to how all L2 MSRs are virtualized, as described in 23.8 . 
24.1.3.  Debug Feature -Specific Handling  25 
Table 24.1:  Debug Feature -Specific Handling  
Debug Feature  How the Feature is Controlled  Handling  
Hardware 
Breakpoints  • DR7, DR0 -3 and DR6  By default, n o special handling .  L1 VMM may configure 
L2→L1 VM exit on DR access.  DR7 is context -switched  on 
L2 VM  exit/entry . 
General Detect  • DR7 bit 13 (GD)  No special handling:  DR7 is context -switched  on L2 VM 
entry/exit.  
TSX Debug  • DR7 bit 11 (RTM)  
• IA32_DEBUGCTL bit 15 (RTM)  No special handling:  DR7 and IA32_DEBUGCTL are 
context -switched  on L2 VM entry/exit.  
Single Stepping  • RFLAGS bits 18 (Trap Flag) and 
16 (Resume Flag)  
• IA32_DEBUGCTL bit 1 (BTF)  No special handling:  RFLAGS and IA32_DEBUGCTL are 
context -switched  on L2 VM entry/exit . 
Bus-Lock 
Detection  • IA32_DEBUGCTL bit 2 
(BUS_LOCK_DETECT)  No special handling:  IA32_DEBUGCTL is context -switched  
on L2 VM entry/exit . 
Software 
Breakpoints (INT3)  None  No special handling:  software breakpoints are stateless.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 49 of 52 
Section 2:  TD Partitioning Architecture  Debug Feature  How the Feature is Controlled  Handling  
Branch Trace 
Message (BTM)  • IA32_DEBUGCTL bits 6 (TR) 
and 7 (BTS)  Not allowed:  when an L2 VM  attempts to set 
IA32_DEBUGCTL[7:6] to 0x1, the Intel TDX module causes 
an L2→L1 VM exit . 
In debug mode (ATTRIBUTES.DEBUG == 1), the host VMM 
is allowed to activate BTM by setting the above bits to 
0x1.  
Branch Trace Store 
(BTS)  • IA32_DEBUGCTL bits 6 (TR), 7 
(BTS), 8 (BTINT), 9 
(BTS_OFF_OS) and 10 
(BTS_OFF_USR)  IA32_DEBUGCTL is context -switched on L2 VM entry/exit.   
IA32_DS_AREA needs to be  context -switched  by the L1 
VMM.  
Note:  
• The L2 VM  can configure BTS to raise PMI on buffer 
overflow (by setting BTINT  = 1).  However, since PMIs 
are virtualized by the host VMM, the L2 VM and L1 
VMM  should be ready to handle spurious, delayed 
and dropped PMIs.  See Perfmon discussion in 24.2 
below . 
• BTS may allow the L2 VM  to hang the machine if BTS 
record generation causes a #PF or a #GP(0), because 
the act of getting to the exception handler may 
deliver another BTS.   As described in the [TDX 
Module Base FAS], it is highly recommended that the 
host VMM enables notification TD exit .   
Processor Trace 
(PT)  • IA32_RTIT_CONTROL  
• Requires VMM’s consent on 
TD initialization by setting  
TD_PARAMS.XFAM[8] to 1  
• L1 VMM can configure 
IA32_RTIT_CONTROL 
virtualization  by requesting 
L2→L1 VM exit on MSR read 
and/or write  PT state handling as part of the extended feature set 
state is discussed in 23.6  and in the [TDX Module Base 
Spec].  
The Intel TDX module sets the following control bits the 
L2 VMCSs .  Since the setting is essential to TD and TDX 
module security, the L1 VMM can’t modify them.  
• “Conceal VMX from PT” exit control, so PIP and VMCS 
packets are not generated on L2 VM exit  
• “Conceal VMX from PT” entry control, so PIP and 
VMCS packets are not generated on L2 VM entry  
• “Conceal VMX from PT” execution control, so PIP 
packets do not report “non -root”, and PSB+ 
sequences do not include VMCS packets, during L2 
VM execution  
• “PT2GPA” execution control, so PT addresses are 
treated as GPAs  
Architectural Last 
Branch Records 
(LBRs)  • IA32_LBR_CONTROL  
TD_PARAMS.XFAM[15] to 1  
IA32_LBR_CONTROL 
virtualization by requesting 
and/or write   
Non -Architectural 
LBRs  • IA32_DEBUGCTL bit 0 (LBR)  L2 VM  attempt to set IA32_DEBUGCTL[0] is ignored by 
the CPU.  
November 2023  . Page 50 of 52 
Section 2:  TD Partitioning Architecture  24.2. On-L2 VM Performance Monitoring  
The host VMM controls whether a guest TD can use the performance monitoring ISA using the TD’s 
ATTRIBUTES.PERFMON bit.  If performance monitoring is allowed for the TD, the L1 VMM controls whether performance 
monitoring is allowed for each L2 VM, by contro lling the virtualization of the applicable MSR.  For details, see the [TDX 
Module Base FAS].  5 
24.3. L1 VMM Debug of L2 VMs

the CPU.  
24.3. L1 VMM Debug of L2 VMs  
L1 VMM is in the TCB of its L2 VMs, and thus have access to the VMX debug features as they are enabled for the whole 
TD.  The L1 VMM has access to some of the L2 VMs’ VMCSes control fields.  For many execution control s, L1 VMM access 
is read -only, because their value is essential for TD and TDX module security and correct operation.  For details, see the 
[TDX Module ABI Spec ]. 10 
24.4. Off-TD Debug  of L2 VMs  
As described in the [TDX Module Base Spec], a guest TD is defined as debuggable  if its ATTRIBUTES.DEBUG bit is 1.  In this 
mode, the host VMM can use Intel TDX functions to read and modify TD VCPU state and TD private memory, which is not 
accessible when the TD is non -debuggable.  
This definition directly extends to nested L2 VMs, as described in the table below.  15 
Table 24.2:  Off -TD Debug Interface  Extensions for TD Partition ing 
Intel TDX Function  Extensions for TD Partition ing 
TDH.MNG.RD  
TDH.MNG.WR  Access L2 VM metadata  
TDH.MEM.SEPT.RD  Read L2 Secure EPT entry  
TDH.VP.RD  
TDH.VP.WR  Access TD VCPU ’s L2  state in TDVPS (including L2 VMCS)  
 
24.4.1.  L2 VM Debug Controls Used by the Host VMM  
The host VMM can control L2 VM off -TD debug using the TDVPS L2_DEBUG_CTLS field, which is defined below.  This field 
may only be written by the host VMM if the TD is debuggable.  20 
Table 24.3:  L2_DEBUG_CTLS:  L2 VM Debug Controls  
Bit(s)  Name  Description  
0 TD_EXIT_ON_L1_TO_L2  If set, TDG.VP.ENTER will TD -exit instead of entering an L2 VM.   For 
simplicity, TD exit will happen before the L1 -->L2 transition is done.  
TDH.VP.ENTER’s completion status will be  
TDX_TD_EXIT_BEFORE_L2_ENTRY .  This TD exit is  fault -like, which allows 
the debugger to modify whatever it wishes and TD -enter to re -invoke 
TDG.VP.ENTER.  
1 TD_EXIT_ON_L2_TO_L1  If set,  VM exit from L2 which results in an L2 →L1 exit is mutated into a 
TD exit .  TDH.VP.ENTER’s completion status will be 
TDX_TD_EXIT_ON_L2_TO_L1 .  
2 TD_EXIT_ON_L2_VM_EXIT  All L2 VM exits (except fatal errors) will result in a TD exit.   
TDH.VP.ENTER’s completion status will be 
TDX_TD_EXIT_ON_L2_VM_EXIT . 
63:3  RESERVED  Reserved, must be 0  
November 2023  . Page 51 of 52 
Section 2:  TD Partitioning Architecture  24.4.2.  Host VMM Access of Debuggable TD’s L2 VM State, Controls and Memory  
When the TD is debuggable, the off -TD debugger can:  
• Read and modify L2 VMCS fields that contain guest state, VM entry load controls, VM exit save controls, and VM 
execution controls.  
• Read and modify TDVPS fields that contain additional TD VCPU’s L2 VM state and control . 5 
This may cause the next VM entry into the L2 VM  to fail due to bad guest state.  It may also generate VM exits that 
wouldn’t have happened otherwise (e.g., VM exit due to a #PF within the L2 VM, even if not configured so by the L1 
VMM ).  By default, such VM exits from L2 are routed to the L1 VMM as L2 →L1 VM entries.  However, the L1 VMM may 
not expect such VM entries.   To avoid unexpected L2 →L1 VM entries, the host VMM can set 
TDVPS.L2_DEBUG_CTLS.TD_EXIT_ON_L1_TO_L2.  With this bit set, any L2 →L1 exit is mu tated into a TD exit; the host 10 
VMM may, on the following TD entry, control whether the L2 VM or the L1 VMM is resumed, using the RESUME_L1 input 
flag of TDH.VP.ENTER.  TD Partitioning Spec  Section 2:  TD Partitioning Architecture  354807 -002US  
November 2023  . Page 52 of 52 
Section 2:  TD Partitioning Architecture  25. Guest -Side TDX Functions  (TDCALL) for L2 VMs  
Currently, the only guest -side TDX function that can be called by L2 VMs is TDG.VP.VMCALL.   
25.1. TDG.VP.VMCALL  
By default, L2 VMs can’t call TDG.VP.VMCALL.  The L1 VMM may enable TDG.VP.VMCALL usage by a specific L2 VCPU 
setting TDVPS .L2_CTLS[VM]. ENABLE_TDVMCALL  using TDG.VP.WR.  The behavior is described in 22.2.3  and 22.2.4 . 5 Document Number:  348987 -002 
  
Trust Domain Extension (TDX) Migration 
TD  Design Guide  
 
March  2023 
 
 Introduction  
 
Document Number: 348987 -002  
 
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© 202 3 Intel Corporation. All rights reserved.  Introduction   
 
Contents  
1 Introduction  ................................ ................................ ................................ ....... 6 
1.1 Background  ................................ ................................ .............................  6 
1.2 Overview  ................................ ................................ ................................  6 
1.3 Terminology  ................................ ................................ ............................  8 
2 Migration Architectural Overview  ................................ ................................ ..............  9 
2.1 TD Migration Orchestration  ................................ ................................ ..........  9 
2.2 Keys used in migration  ................................ ................................ ..............  10 
2.3 MigTD General Flow  ................................ ................................ .................  11 
3 MigTD Design Overview  ................................ ................................ .......................  14 
3.1 Design Overview  ................................ ................................ .....................  14 
3.1.1  MigTD design  ................................ ................................ ............  14 
3.1.2  MigTD layout  ................................ ................................ ............  15 
3.1.3  MigT D boot flow  ................................ ................................ ........  15 
3.2 Reproducibility  ................................ ................................ .......................  16 
3.3 Security Consideration  ................................ ................................ ..............  16 
3.3.1 Type safe language  ................................ ................................ ..... 16 
4 MigTD Mutual Authentication  ................................ ................................ ................  17 
4.1 Remote Attestation TLS  ................................ ................................ ............  17 
4.2 Attestation Flow  ................................ ................................ ......................  18 
4.3 Trust Anchor  ................................ ................................ ..........................  19 
4.4 Certificate Revocation List  ................................ ................................ ..........  20 
4.5 Certificate Structure  ................................ ................................ .................  20 
4.6 TD Report Data  ................................ ................................ .......................  21 
4.7 OID based TD Quote  ................................ ................................ ................  21

4.7 OID based TD Quote  ................................ ................................ ................  21 
4.8 Sample Certificate  ................................ ................................ ...................  22 
4.9 TD Quote API  ................................ ................................ .........................  24 
4.9.1  Get TD Quote  ................................ ................................ ............  24 
4.9.2  Verify TD Quote  ................................ ................................ .........  24 
5 MigT D Migration Policy  ................................ ................................ ........................  26 
5.1 MigTD Policy Type  ................................ ................................ ...................  26 
5.2 MigTD Policy Measurement  ................................ ................................ ........  27 
5.3 MigTD Policy Definition  ................................ ................................ .............  27 
5.3.1  MigTD Policy Property  ................................ ................................ . 27 
5.3.2  MigTD Policy Format  ................................ ................................ ... 29 
5.3.3 MigTD Policy Example  ................................ ................................ . 30 
6 MigTD Network Communication  ................................ ................................ .............  35 
6.1 TDVMCALL  ................................ ................................ ............................  35 
6.1.1  VSock info rmation  ................................ ................................ ...... 35 
6.1.2  VSock data payload  ................................ ................................ .... 36 
7 MigTD Cryptography Capability  ................................ ................................ ..............  37  
 
7.1 Cryptography  ................................ ................................ .........................  37 
7.1.1  Cryptography Algorithm  ................................ ..............................  37 
7.1.2  TLS Configuration  ................................ ................................ ...... 37 
7.2 Random Number Generation  ................................ ................................ ...... 38 
8 MigTD Binary Image  ................................ ................................ ............................  39 
8.1 Boot Firmware Volume (BFV)  ................................ ................................ ...... 39 
8.2 Configuration Firmware Volume (CFV)  ................................ ...........................  39 
9 MigTD Launch  ................................ ................................ ................................ ... 41 
9.1 MigTD initialization  ................................ ................................ ..................  41 
9.2 MigTD Hand -Off Block (HOB)  ................................ ................................ ...... 41 
9.3 MigTD teardown  ................................ ................................ .....................  41 
9.4 MigTD AP handling  ................................ ................................ ..................  41 
10 MigTD Measurement  ................................ ................................ ...........................  42 
10.1 Non -Secure Boot Mode  ................................ ................................ .............  42 
10.2 Secure Boot Mode ................................ ................................ ...................  42 
10.3 MigTD Binding  ................................ ................................ ........................  43 
11 MigTD Metadata  ................................ ................................ ................................  44 
12 Multiple TDs Migration  ................................ ................................ ........................  45 
12.1 Multi TDs Migration  ................................ ................................ ..................  45 
12.2 Multi RA -TLS connections  ................................ ................................ ..........  45 
12.2.1  Multi destination MigTDs  ................................ ..............................  45 
12.2.2  Multi source MigTDs  ................................ ................................ ... 46 
Appendix A  Reference  ................................ ................................ ................................ ........  48 
 
Figures  
Figure 1 -1:  TD Migration  ................................ ................................ ................................ ............  6 
Figure 2 -1:  TD Migration Orchestration Flow  ................................ ................................ ...................  9 
Figure 2 -2:  Migration Session Keys Setup  ................................ ................................ .....................  11 
Figure 2 -3:  Migration TD flow  ................................ ................................ ................................ .... 13 
Figure 3 -1:  Migration TD Design  ................................ ................................ ................................ . 15 
Figure 3 -2:  Migration TD Layout  ................................ ................................ ................................ . 15 
Figure 3 -3:  Migration TD Boot Flow  ................................ ................................ .............................  16 
Figure 4 -1:  MigTD with RA -TLS ................................ ................................ ................................ .. 17 
Figure 4 -2:  MigTD GetQuote Flow  ................................ ................................ ..............................  18 
Figure 4 -3:  TD Report structure  ................................ ................................ ................................ . 19 
Figure 4 -4:  MigTD VerifyQuote Flow  ................................ ................................ ...........................  19 
Figure 6 -1:  VMCALL based communication in MigTD  ................................ ................................ ....... 35 
Figure 12 -1:  Multiple TDs Migration  ................................ ................................ ............................  45 
Figure 12 -2:  Multiple Destination Migration TDs  ................................ ................................ .............  46 
Figure 12 -3:  Multiple Source Migration TDs  ................................ ................................ ..................  46 
 Introduction   
 
Tables  
Table 4 -1:  MigTD Certificate Structure  ................................ ................................ .........................  20 
Table 4 -2:  MigTD OID Field  ................................ ................................ ................................ ...... 21 
Table 4 -3:  RA -TLS OID Field  ................................ ................................ ................................ ..... 22 
Table 4 -4:  Open Enclave TLS OID Field  ................................ ................................ ........................  22 
Table 5 -1:  MigTD Policy Type ................................ ................................ ................................ .... 26 
Table 5 -2:  MigTD Polic y Property  ................................ ................................ ...............................  27 
Table 7 -1:  MigTD Cryptography Algorithm  ................................ ................................ ....................  37 
Table 7 -2:  MigTD TLS Configuration  ................................ ................................ ...........................  37 
Table 8 -1:  MigTD Policy Data  ................................ ................................ ................................ .... 39 
Table 10 -1:  TD Measurement Registers for MigTD (Non -Secure Boot)  ................................ ..................  42 
Table 10 -2:  TD Measurement Registers for MigTD (Secure Boot)  ................................ .........................  43 
 
1 Introduction  
1.1 Background  
Analogous to VM migration, a cloud -service provider may want to relocate/migrate an executing 
Trust Domain  (TD)  from a source Trust Domain Extension (TDX) platform  to a destination TDX 
platform  in the cloud environment. A cloud provider may use TD migration to meet customer 
Service Level Agreement ( SLA), while balancing cloud platform upgradability, patching and other 
serviceabil ity requirements. A TD runs in a CPU mode that protects the confidentiality of its 
memory contents and its CPU state from any other platform software, including the hosting 
Virtual Machine Monitor (VMM) . This primary security objective must be maintained w hile 
allowing the TD resource manager (the host VMM ) to migrate TDs across compatible platforms. 
As the figure below shows , the TD typically will be assigned a different key (and will be always

Introduction  
 
As the figure below shows , the TD typically will be assigned a different key (and will be always 
assigned a different ephemeral key) on the destination platfor m chosen to migrate the TD.  
Figure 1 -1 shows the TD Migration use case.  
 
5TDX-Aware 
host VMMIntel TDX Module
Running in SEAM 
Root ModeHost-Side
InterfaceTrust Domain
TDX-
OSUnmodified 
Drivers
Platform (Cores, Caches, Devices etc.)TDX-Aware 
TDX-
Drivers
Guest -Side
InterfaceLegacy VM
Drivers
Platform (Cores, Caches, Devices etc.)Destination Platform Source Platform
Interface
 
Figure 1-1:  TD Migration  
 
1.2 Overview  
In this specification, the TD being migrated is called the source TD , and the TD created as a result 
of the migration is called the destination TD . An extensible TD Migration Policy  is associated 
with a TD that is used to maintain the TD’s security posture . The TD Migration policy is enforced 
in a scalable and extensible manner using a Migration TD ( as known as  MigTD)  – which is used to Introduction   
 
perform common functions for migrating TDs. TD Migration does NOT depend on any interaction 
with the TD guest software ope rating inside the TD being migrated.  
TD contents is primarily protected and transferred by Intel TDX module using a Migration 
Session Key s (MSK s) used only for a unique Migration session for a TD.  
A Migration TD (MigTD) is used to:  
1. Evaluate potential migr ation sources and targets for adherence to the TD Migration Policy.  
2. If approved, securely transfer a Migration Session Key from the source platform to the 
destination platform to migrate assets of a specific TD.  
The host VMM need bind a MigTD to one (or mo re TDs) via a new SEAMCALL 
[TDH.SERVTD.BIND]  or SEAMCALL [TDH.SERVTD.PREBIND] . The host VMM via the Intel TDX 
module is responsible for export/import of the TD content. The host VMM and existing untrusted 
SW stack responsible for migrating the encrypted TD  content.  
Since the MigTD is in the TCB of the TD being migrated, a MigTD must be pre -bound to the target 
TD being migrated before the target TD measurement is finalized. The MigTD lifecycle does not 
have to be coincidental with the target TD . The MigTD ma y be instantiated when required for Live 
Migration, and must be bound to the target TD before Live Migration can begin . MigTD  must be 
operational until the MSK s has been successfully programmed for the target TD being migrated.  
Figure 1 -2 shows the TD Migr ation Architecture.  
Running in SEAM Root ModeHost-Side
TDX-
Drivers
Intel TDX
Guest -Host InterfaceLegacy 
VM
MigTD
TDVF -shimMigration 
Service and 
Policy 
EvaluationLegacy 
VMLegacy 
VM
TDX-Aware 
TDX-
Drivers
Intel TDX
VM
Platform (Cores, Caches, Devices etc.)MigTD
Policy 
VMLegacy 
VM
Untrusted 
network 
servicesUntrusted 
network 
services
 
Figure 1-1:  TD Migration Architecture  
The full TD migration can be found at TDX TD Migration specification. This document only 
describes the software architecture for Migration TD.   
 
1.3 Terminology  
Term  Description  
GCM  Galois/Counter Mode  
GKID  Guest Key ID  
HKID  Host Key ID  
HOB  Hand -off Block  
MigTD  Migration TD  
MigTD -s Migration TD on source platform  
MigTD -d Migration TD on destination platform.  
MKTME  Multi -Key Total Memory Encryption  
MSK  Migration Session key  
MTK  Migration Transport Key  
PAMT  Physical Address Metadata Table  
SEAM  Secure Arbitration Module  
TCB  Trust Computing Base  
TD Trust Domain  
TDVF  Trust Domain Virtual Firmware  
TDX  Trust Domain Extension  
TLS Transport Layer Security  
RA-TLS Remote Attestation TLS  
TME  Total Memory Encryption  
VKMT  Virtual Key ID  Mapping Table  
§ 
 
 Migration Architectural Overview   
 
2 Migration Architectural Overview  
2.1 TD Migration Orchestration  
Figure 2 -1 shows the TD Migration Orchestration Flow.  
 
Figure 2-1:  TD Migration Orchestration Flow  
Assuming a VM orchestrator manages Node A and Node B. The VM orchestrator decides to 
migration the TD in Node A to Node B. The Node A is migration source, and the Node B is 
migration destination. The component in Node A is named as module -s, where s means source, 
and the component in Node B is named as module -d, where d means destination.  
The high level TD migration flow is below:  
1) The VM orchestrator selects node B as the migration destination.  
2) The VMM -d in Node B notifies the MigTD -d to get ready fo r migration.  
3) The VMM -s in Node A notifies the MigTD -s to negotiate the migration session.  
4) MigTD -s reads  migration session forward key from  TDX module as migration encryption key in 
source platform. MigTD -d read s migration session backward key from  TDX module as migration 
encryption key in destination platform.  
5) MigTD -s and MigTD -d negotiate with each other, including mutual attestation, Migration Policy 
evaluation, negotiate Migration Transport Keys (MTK s) and exchange the Migration Session K eys 
(MSK s) – the migration session forward key and migration session backward key. 
 
 Migration Architectural Overview  
 
6) MigTD -s writes  migration session backward key to TDX module as migration decryption key in 
source platform. MigTD -d writes  migration session forward key to TDX module as migration 
decryption key in destination platform.  
7) TD-s in Node A is migrated to TD -d in Node B, with help of VMM and QEMU.  
8) TD-s is teardown by the VMM -s. TD-d is resumed by the VMM -d. 
9) The migration is done. The orchestrator refres hes the TD information.  
2.2 Keys used in migration  
Two  types of keys are used in MigTD.  
• Migration Transport Keys (MTK s): They are a set of keys generated during MigTD 
negotiation between source platform and destination platform. We call MigTD on source 
platform as MigTD -s, and MigTD on destination platform as MigTD -d. These keys are used 
to protect the communication messag e between MigTD -s and MigTD -d. If MigTD -s and 
MigTD -d use a network Transport Layer Security (TLS) protocol to set up  a secure session, 
then the MTKs are the TLS session keys.  
• Migration Session Keys (MSK s): They ar e a set of AES-256-GCM key s generated by TDX -
Module and exchanged by MigTD. The MSKs  are protected by the MTK s during when they 
are exchanged.  There are t wo MSKs  used  in the migration .  
• The TDX module on the source platform generates a migration session forward 
key for encrypting migration bundles by the source TDX module and decrypting 
them by the destination TDX module.  
• The TDX module on the destination platform generates a migration se ssion 
backward key  for encrypting migration bundles by the destination TDX module and 
decrypting them by the source TDX module.  
Each of the MigTDs on the source and the destination platforms reads the key generated on 
their side, known as the migration enc ryption key , from the TDX module’s target TD’s 
metadata, and transfer it on a secure like to its peer MigTD on the other side of the migration 
session.  The peer MigTD then writes the key, to be used as the migration decryption key , to 
the TDX module’s tar get TD’s metadata.  
Figure 2 -1 shows the Migration Session K eys used in migration setup.  Migration Archite ctural Overview   
 
TDX Module TDX ModuleMigrated TD  s 
Metadata
(in TDCS)Migrated TD  s 
Metadata
(in TDCS)Encryption
KeyDecryption
Key
Source
PlatformDestination
PlatformDecryption
KeyEncryption
KeyMigration TD Migration TDForward Migration Session Key
Backward Migration Session Key 
Figure 2-2:  Migration Session Keys Setup  
2.3 MigTD General Flow  
A MigTD can be launched by VMM at any time, when VMM starts migration. Once the MigTD 
transfers the MSK s to TDX module, the MigTD can be tear down.  
See below as a typical flow:  
• [MigTD -s/MigTD -d] are launched by VMM, when VMM starts migration.  
• The host VMM binds a [MigTD -s/MigTD -d] to one (or more TDs) via a new SEAMCALL 
[TDH.SERVTD.BIND ]. It gets back a binding handle. The binding handle will be part of input 
parameter for the migration information.  
• [MigTD -s/MigTD -d] build secure channel to each other, e.g. via remote att estation TLS (RA -
TLS) protocol.  
• [MigTD -s/MigTD -d] communicate with each other via network interface, such as a 
vsock interface.  
• [MigTD -s/MigTD -d] generate local QUOTE via TDG.VP.VMCALL<GET_QUOTE> and

Key
Source
• [MigTD -s/MigTD -d] generate local QUOTE via TDG.VP.VMCALL<GET_QUOTE> and 
pass the QUOTE to the peer in the TLS certificate.  
• [MigTD -s/MigTD -d] do mutual authentication, via peer QUOTE attestation.   
 
• Once RA -TLS authentication is done, [MigTD -s/MigTD -d] can derive a set of TLS 
session keys as the Migration Transport Keys (MTK s). Then the secure channel is 
set up . 
• [MigT D-s/MigTD -d] check the Migration Policy.  
• Within the secure session, [MigTD -s/MigTD -d] can check the Migration Policy to see 
if the peer is allowed to migrate.  
• [MigTD -s/MigTD -d] exchange  Migration Session Keys (MSK s) 
• [MigTD -s] reads  its own migration session forward key  via 
TDCALL<TDG.SERVTD. RD(MIG_ENC_KEY) >. 
• [MigTD -d] read s its own migration session backward key  via 
• [MigTD -s/MigTD -d] transfer its own key  via the secure channel protected by MTKs . 
• [MigTD -s] writes  peer’s migration session backward key via 
TDCALL<TDG.SERVTD. WR(MIG_DEC_KEY) >. 
• [MigTD -d] write s peer’s migration session forward key via 
• [MigTD -s/MigTD -d] can be tear down.  
  Migration Architectural Overview   
 
Figure 2 -2 shows the general Migration TD flow.  
 
Figure 2-3:  Migration TD flow  
Care must be taken that a  MigTD shall  always use TDG.SERVTD.RD to read a fresh MIG_ENC_KEY 
from TDX -Module once, after the MigTD setup a secure session with a peer  MigTD. This 
MIG_ENC_KEY shall  be erased immediately after it is sent to the peer  MigTD and shall  never be 
used again in any migra tion session including current session or other session s. This rule is for 
both source MigTD and destination MigTD.  
 
§ 
 
 MigTD Design Overview  
 
3 MigTD Design Overview  
3.1 Design Overview  
Migration TD is a lightweight bare -metal service TD. Because MigTD is in TCB, the code in MigTD 
should be as minimal as possible.  
3.1.1  MigTD design  
Figure 3 -1 shows the design of MigTD. It includes a shim layer and a core.  
• TdShim  is a generic shim layer to boot any service TD , as a transient environment.  
o TdShim includes a Reset Vector  that is the first instruction when a VMM launches a 
TD. 
• Core  is the Migration TD runtime execution environment.  
o Crypto  and TLS are used to establish a secure communication session. It should 
reuse the existing known good crypto library and TLS configuration in cluding 
version and cipher suite.  
o VSock  is a way to pass the TLS packet to the VMM and leverage the VMM network 
stack to communicate with peer MigTD.  
o VMM communication  should follow the Guest -Host Communication Interface 
(GHCI) specification.  
o Quote Attesta tion service  is used for the mutual authentication in Remote -
Attestation TLS.  
o Migration Policy  is used to evaluate the migration peer according to the predefined  
policy.  
 
MigTD Design Overview   
 
Figure 3-1:  Migration TD Design  
3.1.2  MigTD layout  
Figure 3 -2 shows the build time layout and runtime layout.  
The left -hand side shows the build time layout. The Boot Firmware Volume (BFV) include the 
TdShim and migration core.  
The right -handle side shows the runtime layout. The TdShim should be loaded to the top of 4GB 
memory where the reset vector sits. Then the TdShim will relocate the MigTD core to low 
memory space and setup x64 long mode environment. This approach is highly recommended 
because the top of 4GB is usually mapped to  a flash device. Executing code in flash device may 
bring some special restriction even in virtualization environment. All rest additional memory 
below the top of memory (TOM) can be used as heap,  and the stack can be allocated from the 
heap. Avoid using  the memory below 1MB , because the top of 1MB is also mapped to legacy 
flash ROM.  
 
Figure 3-2:  Migration TD Layout  
 
3.1.3  MigTD boot flow  
Figure 3 -3 shows the Migration TD boot flow.  
1. ResetVector in TdShim . The reset vector code should park all application processors (APs) 
to a known place and only let bootstrap processor (BSP) to initialize the environment. The 
BSP should switch to long mode, setup stack and jump to the TdShim initial program loader 
(IPL).  
2. IPL i n TdShim . When TdShim is launched, it should get the memory information internally, 
such as metadata area. Then it accepted the TD memory and set up  all required protection 
such as data execution prevention (DEP). The final step is to find the MigTD core, load it to 
low memory and jump to the MigTD core.  
 
3. Entrypoint of MigTD Core . The MigTD should initialize the final execution environment 
including he ap and interrupt vector etc. It should also initialize the vsock driver to prepare 
the communication with VMM.  
4. MigTD Core runtime . The MigTD should set up  secure communication session with peer 
MigTD. MigTD should send and receive the TLS packet via networ k socket interface, such as 
vsock. After the secure session is established, the MigTD -s will generate the Migration 
Session key and pass to MigTD -d. Then both MigTD can pass the key to the TDX module. 
After that, the MigTD can tear down.  
 
Figure 3-3:  Migration TD Boot Flow  
3.2 Reproducibility  
A service TD binary should be reproducible . Please refer to “TDX Virtual Firmware Design 
Guide” for the reproducible support.  
3.3 Security Consideration  
MigTD should adopt the Security Consideration in the “TDX Virtual Firmware Design 
Guide”.  
3.3.1  Type safe language  
The MigTD should consider use type safe language, such as Rust programming language to 
eliminate memory safety issue.  
MigTD Mutual Authentication   
 
4 MigTD Mutual Authentication  
Two Mi gTDs use mutual authentication to verify each other when they build the secure 
communication channel.  
4.1 Remote Attestation TLS  
The network TLS protocol is a standard to allow two entities create a n authenticated  secure 
session. A typical mutual authenticati on in TLS requires X.509 certificate provision. However, it is 
hard to provision a private key to MigTD. A way to resolve this problem is to use remote 
attestation TLS (RA -TLS).  
RA-TLS does not require private key or public certificate provision. The MigTD  can generate a n 
ephemeral  keypair  at runtime and include the public key in the TD report data and TD quote 
data. Then the MigTD generates an X.509  certificate at runtime, includes the TD Quote in the 
X.509 certificate, and send this TD certificate to peer  as the TLS certificate. When the peer MigTD 
receives the certificate, it gets the TD Quote, verifies the Quote, then it can trust the public key. 
Finally, the peer MigTD can use the public key to verify rest TLS messages.  
Figure 4 -1 shows the MigTD with R A-TLS.  
 
Figure 4-1:  MigTD with RA -TLS 
For more detail of RA -TLS, refer to [Intel RA -TLS]  or [Open Enclave RA -TLS].  
 
 MigTD Mutual Authentication  
 
4.2 Attestation Flow  
The MigTD attestation flow is similar to the normal TD attestation flow. Figure 4 -2 shows the flow 
to get TD Quote in MigTD.  
 
Figure 4-2:  MigTD GetQuote Flow  
With step 1~4, the MigTD gets a TDREPORT for itself. The integrity of TDREPORT is guaranteed 
by the REP ORTMACSTRUCT, which is MACed with TDX CPU with a unique MAC key. Figure 4 -3 
shows the TDREPORT structure.  
In step 5~6, the MigTD uses the TDG.VP.VMCALL<GetQuote> and try to get the Quote from the 
Quoting Enclave (QE).  
In step 7~8, the QE verifies the MAC o f the TD report with the TDX CPU . This verification  is 
needed because Quoting is requested from the VMM and is not trusted.  
In step 9~10, if the verification passed, then the QE signs the TDREPORT with its attestation key 
to generate the TD QUOTE and returns it to the MigTD via the VMM.  
Now the MigTD can include the TD Quote in the TLS certificate and send to peer.  
 
Figure 4-3:  TD Report and TD Quote structure  
Once the MigTD receives the TLS certifi cate from the peer, it extracts the TD Quote from the TLS 
certificate, and verifies integrity of the TD Quote.  Figure 4 -3 shows the TD Report and Quote . 
Please refer to Intel TDX Module v1.5 ABI  for detail of TD Report structure. Please refer to Intel 
TDX DCAP Quote Generation Library and Quote Verification Library  for detail of TD Quote 
structure . 
 
Figure 4-4:  MigTD VerifyQuote Flow  
 
4.3 Trust Anchor  
The Quote is signed by the Attestation Key by the Quoting Enclave (QE). The Attestation Key 
Certificate is signed with the Provision Certification Key (PCK) by Provision Certification Enclave 
 
Document Number: 348987 -002

(PCE), the PCK certificate is signed with PCK CA Certi ficate and the PCK CA Certificate is signed 
with Intel root CA Certificate.  See Figure 4 -4. Please refer to Intel® SGX PCK Certificate and 
Certificate Revocation List Profile Specification  for more detail.  
MigTD shall enroll the Intel Root CA certificate. And  the Intel Root CA certificate shall be 
measured as part of migration policy.  
4.4 Certificate Revocation List  
Besides Root CA certificate, the verification process shall also include the check for the revoked 
certificate.  See Figure 4 -4. 
4.5 Certificate Structure  
The TD Quote Certificate shall be generated as an DER -encoded X.509 v3 format certificate. See 
table 4 -1. 
Table 4-1:  MigTD Certificate Structure  
Certificate Field  
Field  Description  Required  
Version  Version of the encoded certificate shall be 
present and shall be version 3 ( value 0x2 ) Mandatory  
Serial Number  Serial number shall be present with a positive 
integer value.  
For example: Serial Number: 1  Mandatory  
Signature Algorithm  Signature algorithm s hall be present.  
For example: sha384WithRSAEncryption  Mandatory  
Issuer  Issuer distinguished name shall be specified.  
For example: “CN=MigTD SDK, O=mbed TLS, 
C=US”  Mandatory  
Subject  
Name  Subject name shall be present and shall 
represent the distinguished name associated 
with the certificate.  
It shall be same as Issuer.  Mandatory  
Validity  Certificate may include this attribute. If the 
validity attribute is present, the value for 
notBefore  field should be assigned the 
generalized 1970010100000 0Z time value and Mandatory  MigTD Mutual Authentication   
 
notAfter  field should be assigned the 
generalized 99991231235959Z  time value.  
Subject Public Key Info  Device public key and the algorithm shall be 
present.  
For example:  
Public Key Algorithm: rsaEncryption  
Modulus: …  
Exponent: 65537 (0x10001)  Mandatory  
X509v3 Extension:  
Basic Constraints  CA: FALSE . Optional  
Subject Key Identifier  Subject Key Identifier  Optional  
Authority Key Identifier  It should be same as Subject Key Identifier.  Optional  
Extended Key Usage  MigTD Quote Certificate indicator  
“1.2.840.113741 .1.5.5.1 .1” - Intel  Mandatory  
 
4.6 TD Report Data  
During MigTD attestation, a pair of asymmetric keys will be generated. The public key hash 
(SHA384 ) is treated nonce for TD report data.  
 
4.7 OID based TD Quote  
The MigTD Quote report is X509v3 Extension OID based data.  
Table 4-2:  MigTD OID Field  
MigTD OID Field  
OID: MigTD_qu ote_report  Quote Report  
“1.2.840.113741 .1.5.5.1 .2” - Intel  Mandatory   
 
OID:  
MigTD_event_log  EventLog Report  
“1.2.840.113741 .1.5.5.1 .3” - Intel  Mandatory  
 
NOTE: Current RA-TLS and OpenEnclave are using below fields.  
Table 4-3:  RA-TLS OID Field  
RA-TLS OID Field  
OID: 
ias_response_body_oid  Attestation Report. ias_report  
“1.2.840.113741 .1337.2” - Intel  Mandatory  
OID: ias_root_cert_oid  Attestation Report. ias_sign_ca_cert  
“1.2.840.113741 .1337.3” - Intel  Mandatory  
OID: ias_leaf_cert_oid  Attestation Report. ias_sign_cert  
“1.2.840.113741 .1337.4” - Intel  Mandatory  
OID: 
ias_report_signature_oid  Attestation Report. ias_report_signature  
“1.2.840.113741 .1337.5” - Intel  Mandatory  
Table 4-4:  Open Enclave TLS OID Field  
Open Enclave OID Field  
OID: oe_report  Quote Report  
"1.2.840.113556 .10.1.1" - Microsoft  Mandatory  
OID: oe_evidence  Attestation Report  
"1.2.840.113556 .10.1.2" - Microsoft  Mandatory  
 
4.8 Sample Certificate  
A sample structure is shown here assuming a minimum certificate structure. Field names and 
structure types match the ASN.1 names in PKCS #1 [ RFC8017] and PKCS #7 [RFC2315].  MigTD Mutual Authentication   
 
Certificate:  
    Data:  
        Version: 3 (0x2)  
        Serial Number: 1 (0x1)  
        Signature Algorithm: sha256WithRSAEncryption  
        Issuer: CN = 127.0.0.1, O = mbed TLS, C = UK  
        Validity  
            Not Before: Jan  1 00:00:00 2001 GMT  
            Not After : Dec 31 23:59:59 2030 GMT  
        Subject: CN = 127.0.0.1, O = mbed TLS, C = UK  
        Subject Public Key Info:  
            Public Key Algorithm: rsaEncryption  
                RSA Public -Key: (3072 bit)  
                Modulus:  
                    00:a7:f5:93:01:2d:c9:d6:c6:11:ca:1c:0e:ab:31:  
                    cf:51:6d:81:f6:8c:49:bc:49:ee:c2:6d:da:6c:01:  
                    1a:2d:d0:fb:23:f2:c9:c9:9b:4b:47:47:5b:96:f2:  
                    fa:00:bb:f9:a8:af:7f:73:1f:9d:c9:c7:73:88:3e:  
                    c1:98:a4:87:54:db:8b:43:bb:c1:57:76:9f:a5:d0:  
                    1c:d6:25:bc:a2:5b:fa:cd:20:ef:bd:bd:c0:13:ac:  
                    74:ef:a8:58:14:33:49:0f:9b:b5:f2:6f:3f:8c:ac:  
                    42:b3:8e:a2:03:6d:7a:dc:77:b6:fc:02:87:d6:cb:  
                    f2:43:99:c4:75:d9:a6:98:3b:96:2b:aa:c5:3d:3d:  
                    36:92:c5:e5:30:84:78:db:b4:a6:83:6a:20: ca:08:  
                    2b:00:c8:49:50:b4:ce:ad:e6:66:79:44:c4:79:40:  
                    51:62:b5:79:60:e8:56:53:88:a3:47:71:5a:49:c3:  
                    1d:de:31:c6:2b:96:f8:19:c3:4b:d1:c8:fa:c5:0c:  
                    e4:ce:c3:68:89:4b:b3:64:e6:3e:7 0:e8:1c:3f:8e:  
                    b2:08:7d:ab:50:9d:8b:f6:1f:85:85:eb:06:80:2d:  
                    f8:74:0f:0e:c2:93:9b:f4:6d:34:3f:54:1b:93:27:  
                    be:48:c1:0f:de:49:70:44:2e:ad:05:26:ca:cf:23:  
                    6d:62:7f:72:c6:e3:51:27:be:d5:ee:b5:8d:72:ce:  
                    b6:a7:50:ea:0f:38:99:4e:db:f8:3f:ee:81:e7:11:  
                    5a:b0:70:f4:31:f4:47:88:53:1d:9b:b9:6d :87:68:  
                    71:e0:79:34:bc:da:79:04:f9:fc:9c:66:a2:7b:09:  
                    e4:d4:19:90:cd:2b:0a:f8:64:f1:92:c0:da:0f:d0:  
                    e9:9e:1f:71:2d:fb:56:5c:53:ab:13:99:e7:36:ff:  
                    a6:47:d4:c8:3a:22:75:a6:b7:c8: a8:da:b9:0f:64:  
                    21:d4:e1:0e:c2:76:ce:84:e6:48:5d:9b:3d:7d:08:  
                    d0:4b:b1:fe:60:c4:db:c3:2b:4f  
                Exponent: 65537 (0x10001)  
        X509v3 extensions:  
            X509v3 Basic Constraints:  
                CA:FALSE  
            X509v3 Subject Key Identifier:  
                E0:F1:C8:11:40:8D:3A:24:C1:9C:FA:B9:31:17:08:60:2E:E3:2A:1A  
            X509v3 Authority Key Identifier:  
                keyid:E0:F1:C8:11:40:8D:3A:24:C1:9C:FA:B9:31:17:08:60:2E:E3:2A:1A  
 
            1.2.840.113741.1337.2:  
                report   
 
            1.2.840.113741.1337.3:  
                cacert  
            1.2.840.113741.1337.4:  
                signed  
            1.2.840.113741.1337.5:  
                ................................  
    Signature Algorithm: sha256WithRSAEncryption  
         33:8d:62:27:78:0c:f8:4c:24:6f:11:37:5f:54:fd:3e:8d:c4:  
         93:a9:31:ff:0e:f8:f9:88:6c:92:e2:b2:e8:d3:53:26:bd:b8:  
         03:fc:15:e6:8f:55:e4: 7a:06:77:18:87:5d:57:dc:69:dd:e8:  
         45:5a:db:22:5b:73:ab:e8:b1:0c:b3:4c:00:d5:07:22:28:cb:  
         7b:7c:87:19:5f:bc:9d:c5:28:b6:ac:e9:9e:c1:21:54:51:bc:  
         86:d0:b2:1a:41:9c:af:52:67:cc:4a:d7:3a:c1:c0:74:b8:68:  
         bf:22:bf:32:2e:72:46: 97:ba:ad:f8:77:25:a4:3e:f9:f9:49:  
         79:70:2d:a4:16:20:b1:f2:34:d9:90:0e:7b:e2:84:40:b2:99:  
         38:ce:40:4e:fc:94:1d:70:f5:93:93:a5:fa:26:42:7b:df:08:  
         cf:de:3e:ca:b8:8f:ba:61:58:b0:57:8f:60:20:96:29:32:35:  
         b3:19:e6:6b:e3:40:fc: 02:04:97:6c:64:6c:7c:b6:95:48:24:  
         a2:5a:70:0d:1f:a9:ba:d9:97:92:b3:9b:e7:46:a3:39:bf:76:  
         d4:e6:85:62:cd:f2:86:49:b1:c0:04:db:a5:de:9d:da:68:59:  
         32:33:17:ff:94:78:77:ea:dd:f0:3f:45:d2:97:e1:cf:5b:58:  
         23:1e:6a:25:fc:ce:0e: 89:d0:31:1b:f9:59:1a:34:4e:8a:bb:  
         57:2f:99:ec:f3:b2:41:ec:a2:58:60:63:0b:64:06:4b:51:5b:  
         4c:2f:fe:47:92:70:2d:4c:b2:d8:31:31:9d:5b:33:52:15:96:  
         6f:fb:4e:6e:f5:b0:39:07:f1:90:88:fd:d5:7a:71:a3:fc:cf:  
         15:ff:18:0c:15:0f:46: c6:4c:9a:dc:31:ce:7c:5c:81:19:9f:  
         b5:53:22:d1:b9:5d:d1:f2:9b:46:9a:0f:b7:7d:cb:a0:6c:fc:  
         e9:75:72:1d:df:35:f5:f7:2e:64:3c:75:5d:8c:ce:1d:18:98:  
         95:f7:30:96:57:c1  
 
4.9 TD Quote API  
4.9.1  Get TD Quote  
In MigTD mutual authentication, the RA -TLS need get the TD Quote and put it 
OID:MigTD_quote_report and create a RA -TLS certificate around it.  
4.9.2  Verify TD Quote  
In MigTD mutual authentication, the peer will get the RA -TLS certificate and verify the integrity of 
the TD Quote.  If the integrity verification fails, the TLS will be terminated.

32:33:17:ff:94:78:77:ea:dd:f0:3f:45:d2:97:e1:cf:5b:58:  
 
the TD Quote.  If the integrity verification fails, the TLS will be terminated.  
 
NOTE: The MigTD policy verification is irrelevant in TD Quote attestation. MigTD policy 
verification will be the next step after MigTD mutual authentication. The migration session key 
(MSK)  is passed after the MigTD policy verification.  MigTD Mutual Authentication   
 
§ 
 
 MigTD Migration Policy  
 
5 MigTD Migration Policy  
The MigTD need a set of migration policy to determine if it is allowed to migrate a TD from a 
source platform to a destination platform.  
5.1 MigTD Policy Type  
In general, there might be multiple types of policy:  
Table 5-1:  MigTD Policy Type  
 
Type  Policy 
Owner  Definition  Example  MigTD Action  
TDX Module Policy 
(Required)  Intel  TDX Module 
Specification  TD Global Metadata Field:  
On export: MIG_VERSION  is between 
[MIN_EXPORT_VERSION, 
MAX_EXPORT_VERSION ] 
On import: MIG_VERSION  is between 
[MIN_IMPORT_VERSION, 
MAX_IMPORT_VERSION ] 
TDX_Module’s MAJOR_VERSION/ 
MINOR_VERSION  is compatibility.  
TD’s ATTRIBUTES/XFAM/CPUID  is 
compatible.  
Reference : TDX Module Migration 
Specification.  MigTD 
optional 
checks it to 
detect error 
earlier.  
Code is 
extended to 
MRTD or 
RTMR[1] (See 
below).  
MigTD Default 
Policy 
(Recommended)  CSP  MigTD Design 
Guide  MigTD  is compatible. ( SVN, MRTD , etc.) 
Certificate  is valid and not expired. ( Root 
CA certificate , certificate revocation list ) MigTD checks 
the migration 
policy.  
Policy Data is 
RTMR[2]. (See 
below).  
MigTD Extension 
Policy (Optional)  CSP  CSP Extens ion. 
Out of scope 
of this 
document.  CSP Extension. Out of scope of this 
document.  CSP Extension. 
of this 
document.  
 MigTD Migration Policy   
 
5.2 MigTD Policy Measurement  
A MigTD should design the policy in an extensible way that the CSP/Solution vendor may add 
their own policy. The policy could be:  
• Code – executed by a common policy engine to evaluate  
o The code (a statically  linked library or a dynamic loaded module) could be part of 
MigTD Core , which  is extended to MRTD in non -SecureBoot mode or RTMR[1] in 
Secure Boot  Mode. See more details about these  two modes in Chapter 10.  
o If the MigTD checks the “TDX Module Policy” to detect the error earlier, then this 
check can be done in the code , and then there  is no need to define it as policy data.  
• Data - consumed by a commo n policy module.  
o The data could be provisioned later in Configuration Firmware Volume (CFV) of the 
MigTD , which  is extended to RTMR[2].  
o The MigTD includes the “MigTD Default Policy” in CFV, so that it can be easily 
updated. For example, the TCB SVN or QE certificate expired date. The trust anchor 
“Intel Root CA Cert” and Certificate Revocation List (CRL) shall also be included in 
CFV as part of migration policy.  
5.3 MigTD Policy Definition  
The typical MigTD policy is that the TCBs and hardware are newer than t he baseline date , which 
can be evaluated with TDX Quote attestation. Figure 4 -3 shows the TDX Quote and TD Report 
structure.  
5.3.1  MigTD Policy Property  
This document defines below default policy properties.  
Table 5-2:  MigTD Policy Property  
Family 
Name  Group Name  Property Name  Type  Comment  
MigTD  TEE_TCB_INFO 
(The integrity is 
verified with TD 
Quote)  TEE_TCB_SVN.SEAM  Integer  Intel TDX module 
SVN. (UINT16)  
MRSEAM  String  Measurement of the 
Intel TDX module. 
(48 Bytes Hash)  
MRSIGNERSEAM  String  Measurement of 
TDX module signer if 
valid. (48 Bytes 
Hash)   
 
ATTRIBUTES  Integer  Additional 
configuration 
ATTRIBUTES if valid. 
(UINT64)  
TDINFO (The 
integrity is 
Quote)  ATTRIBUTES  Integer  TD’s Attributes. 
(UINT64)  
XFAM  Integer  TD’s XFAM. (UINT64)  
MRTD  String  Measurement of the 
initial contents of 
the TD. (48 Bytes 
Hash)  
MRCONFIGID  String  Software -defined ID 
for non -owner -
defined 
configuration of the 
guest TD. (48 Bytes 
Hash)  
MROWNER  String  Software -defined ID 
for the guest TD’s 
owner. (48 Bytes 
Hash)  
MROWNERCONFIG  String  Software -defined ID 
for owner -defined 
Hash)  
RTMR0  String  Runtime extendable 
measurement 
register 0. (48 Bytes 
Hash)  
RTMR1  String  Runtime extendable 
register 1. (48 Bytes 
Hash)  
RTMR2  String  Runtime extendable 
register 2. (48 Bytes 
Hash)  
RTMR3  
 String  Runtime extendable 
register 3. (48 Bytes 
Hash)  MigTD Migration Policy   
 
EventLog (The 
integrity of 
“Digest” is 
verified with 
RTMR. The 
“Data” is verified 
with “Digest”)  Digest.TdShim  String  Digest for TDShim. 
Digest.MigTdCore  String  Digest for MigTD 
Core. (48 Bytes 
Hash)  
Digest.SecureBootKey  String  Digest for 
SecureBootKey. (48 
Bytes Hash)  
Digest.MigTdPolicy  String  Digest for 
MigTdPolicy.  
(This field is only 
valid with “self” 
string to indicate 
that the MigTdPolicy 
from source and 
destination must be 
same.)  
Data.MigTdCoreSvn  Integer  MigTD Core’s SVN. 
(UINT64)  
QE Quote (The 
Quote ) PckCert.ExpiredTime  String  Expired time for the 
PCK certificate.  
AttestationKeyCert. 
ExpiredTime  String  Expired time for the 
Attestation Key 
certificate.  
 
5.3.2  MigTD Policy Format  
MigTD should use the industry standard for the policy data format - JSON . 
 
============  
{ 
    "id": <GUID>,  
    <Family -Name>: {  
        <Group -Name>: {  
            <Property -Name>: {  
                "operation": <Operation -Name>,  
                "reference": <Reference -Value>  
            }, 
            ... 
        },  
 
        ... 
    }, 
    ... 
} 
 
Property Type  Operation -
Name  Reference -Value type  Comment  
Integer  “equal”, 
“greater -or-
equal”, 
“subset”  Integer value  Not sure if we want to 
support “greater”, “less”, 
“less -or-equal”, or 
“superset”  
String  “equal”  String value   
String  “equal”  “self”  Used to ensure two 
MigTDs have same data.  
String  “in-range”  “<integer>..<integer>”  The property shall be 
greater -or-equal than the 
begin value, and less than 
the end value.  
String  “in-time -range”  “<integer>..<integer>”  The property time shall be 
within the time range. The 
value in the time range is 
UNIX  time.  
(Unit time is the number of 
seconds that have elapsed 
since the UNIX  epoch, 
minus leap seconds; the 
UNIX  epoch is 00:00:00 
UTC on 1 January 1970.)  
 
5.3.3  MigTD Policy Example  
5.3.3.1  Sample Policy in non -SecureBoot Mode  
In this mode, we cannot know the SVN of the MigTDCore. We use policy to indicate the MigTD 
must be same.  
 
{ MigTD Migration P olicy   
 
  "id": "xxxxxxxx -xxxx -xxxx -xxxx -xxxxxxxxxxxx",  
  "MigTD": {  
    "TEE_TCB_INFO": {  
        "TEE_TCB_SVN.SEAM": {  
            "operation": “greater -or-equal”,  
            "reference": “self ” 
        }, 
        "MRSEAM": {  
            "operation": “equal”,  
            "reference": “self”  
        }, 
        "MRSIGNERSEAM": {  
        }, 
        "ATTRIBUTES": {  
            "operat ion": “equal”,  
        } 
    }, 
 
    "TDINFO": {  
        }, 
        "XFAM": {  
        }, 
 
        "MRTD": {  
        }, 
        "MRCONFIGID": {  
        }, 
        "MROWNER": {  
        }, 
        "MROWNERCONFIG": {  
            "referen ce": “self”   
 
        }, 
 
        // use RTMR  
        "RTMR0": {  
        }, 
        "RTMR1": {  
        }, 
        "RTMR2": {  
        }, 
        "RTMR3": {  
        } 
    } 
  } 
} 
5.3.3.2  Sample Policy in Secure Boot  Mode  
In this mode, we ca n know the SVN of the MigTDCore. We use policy to indicate a set of MigTD 
that the SVN in a fixed range.  
 
{ 
  "MigTd": {  
            "operation": “greater -or-equal”,

}, 
 
        }, 
 
        // use RTMR  
        "RTMR0": {  
        }, 
        "RTMR1": {  
        }, 
        "RTMR2": {  
        }, 
        "RTMR3": {  
        } 
    } 
  } 
} 
 
{ 
  "MigTd": {  
        }, 
        }, 
        }, 
        "ATTRIBUTES": {  MigTD Migration Policy   
 
        }, 
    }, 
 
        }, 
        "XFAM": {  
        }, 
 
        "MRTD": {  
        }, 
        "MRCONFIGID": { 
        }, 
        }, 
        }, 
 
    }, 
 
    "EventLog”: {  
        // Do not use RTMR, but SVN in event log  
        // Below policy means and SVN in [13, 18).  
        "Digest.TdShim": {  
        }, 
        "Digest.SecureBootKey": {  
        }, 
        "Digest.MigTdPolicy": {   
 
        }, 
        "Digest.MigTdCoreSvn": {  
            "operation": “in -range”,  
            "reference": “13..18”  
        }, 
    } 
  } 
} 
 
§ MigTD Network Communication   
 
6 MigTD Network Communication  
Two MigTD need communicate with each other to establish a secure session. Because the MigTD 
is in TCB, it is not recommended to include a full TCP/IP network stack in a MigTD. Instead, the 
MigTD should use the network stack in the untrusted VMM host environment.  
6.1 TDVMCALL  
The MigTD -s may use TDG.VP.VMC ALL<Service.MigTD.Send>  and 
TDG.VP.VMCALL<Service.MigTD.Receive>  to communicate the VMM host environment and 
pass the MigTD -to-MigTD communication packet (such as TLS packet). The VMM on the source 
platform need pass the communication packet to the VMM on destination platform. Then the 
VMM on the destination platform c an return the packet to the MigTD -d. When MigTD -d finishes 
processing the input packet, MigTD -d can return the response back to MigTD -s by using the 
same mechanism. Figure 6 -1 shows the flow.  
 
Figure 6-1:  VMCALL based communication in MigTD  
 
6.1.1  VSock information  
During MigTD launch, the VMM can pass the MIGTD_STREAM_SOCKET_INFO  HOB to the MigTD 
to allow MigTD to communicate with the agent.  
The context ID (CID) of the VMM is 2 - Well -known CID for the host. The  context ID (CID) of the 
MigTD can be retrieved from MIGTD_STREAM_SOCKET_INFO  HOB. The VMM or the MigTD can 
be client or server. The server listening port can be found in the MIGTD_STREAM_SOCKET_INFO  
HOB.  
 
 MigTD Network Communication  
 
6.1.2  VSock data payload  
The MigTD should put the TLS pa cket to the VMCALL -vsock data payload.  
 
§ MigTD Cryptography Capability   
 
7 MigTD Cryptography Capability  
MigTD needs to have cryptography for key negotiation.  
7.1 Cryptography  
7.1.1  Cryptography Algorithm  
Table 7-1:  MigTD Cryptography Algorithm  
 
Cryptography  Options  Recommendation  
Digital Signature  RSA, ECDSA  ECDSA -NIST_P384  
Key Exchange  ECDHE  ECDHE -secp384r1  
AEAD  AES-GCM, Chacha20 -Poly1305  AES-256-GCM  
Hash  SHA -2 SHA384  
7.1.2  TLS Configuration  
Table 7-2:  MigTD TLS Configuration  
 
TLS 
Configuratio
n Options  Recommendation  
Version  1.2, 1.3  1.3 
Cipher Suite  V1.3  
TLS_AES_256_GCM_SHA384  
TLS_AES_128_GCM_SHA256  
TLS_CHACHA20_POLY1305_SHA256  
 
V1.2  
TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA38
4 V1.3  
TLS_AES_256_GCM_SHA3
84  
 MigTD Cryptography Capability  
 
TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA
384 
TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA25
6 
TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA
256 
 
7.2 Random Number Generation  
The MigTD should use Intel instruction RDSEED/RDRAND  to get random number.  
 
§ MigTD Binary Image   
 
8 MigTD Binary Image  
MigTD is a customized tiny TDVF.  
8.1 Boot Firmware Volume (BFV)  
The MigTD includes one Firmware Volumes (FV) - Boot Firmware Volume. The format of FV is 
defined in  PI specification.  
The Boot Firmware Volume includes all component required during boot.  
The file system GUID must be EFI_FIRMWARE_FILE_SYSTEM2_GUID  or 
EFI_FIRMWARE_FILE_SYSTEM3_GUID , which is defined in PI specification.  
1) TD Shim  
a) ResetVector  – this component provides the entrypoint for MigTD, switch to long 
mode, and jumps to the ShimIpl. The FFS GUID must be 
EFI_FFS_VOLUME_TOP_FILE_GUID , which is defined in PI specification.  
b) ShimIpl  – This component prepares the required parameter for MigTDC ore and jump 
to the MigTDCore. Module type is EFI_FV_FILETYPE_SECURITY_CORE , which 
is defined in PI specification.  
2) MigTDCore  – The main MigTD module , which finishes all its work described in chapter 2 then 
tears down itself. MigTD core includes key exchang e cryptography capability and networking 
capability via VMM interface. File type is EFI_FV_FILETYPE_DXE_CORE , which is 
defined in PI specification.  
The BFV may include an initial static page table to assist the ResetVector switch from 32-bit 
mode to 64-bit mode.  
8.2 Configuration Firmware Volume (CFV)  
MigTD includes a Configuration Firmware Volume (CFV) to hold the migration policy data.  
The file system GUID shall  be EFI_FIRMWARE_FILE_SYSTEM2_GUID  or 
EFI_FIRMWARE_FILE_SYSTEM3_GUID , which is defined in PI specification , or 
EFI_SYSTEM_NV_DATA_FV_GUID , which is defined i n 
https://github.com/tianocore/edk2/blob/master/MdeModulePkg/Include/Guid/System
NvDat aGuid.h . 
 
Table 8-1:  MigTD Policy Data  
  
 MigTD Binary Image  
 
Item  Description  Measurement  
MigTD Policy  JSON file  RTMR[2]  
Root CA Cert 
(Trust Anchor)  One X.509 certificate.  RTMR[2]  
Certificate 
Revocation List  One Certificate Revocation List.  RTMR[2]  
Secure Boot Key  One secure boot public key.  
(only applicable for SecureBootMode)  RTMR[0]  
 
§ 
 MigTD Launch   
 
9 MigTD Launch  
MigTD launch is similar to TDVF launch.  
9.1 MigTD initialization  
The MigTD initialization is the same as TDVF initialization flow , and  starts from 32-bit protected 
mode with paging disabled, then switch to 64-bit long mode.  
9.2 MigTD Hand -Off Block (HOB)  
The TD HOB list is used to pass the information from VMM to TDVF. The HOB format is defined in 
PI specification. If the TD HOB is used, it must be extended to RTMR register.  
MigTD should ignore the TD HOB passed from VMM. The TD memory information should be 
indicated by MigTD in the metadata area.  
After launch, the MigTD sho uld call TDG.VP.VMCALL <Service.MigTD.WaitForRequest>  to get 
the new migration information.  
The MigTD could be transient or persistent, the MigTD should use TDG.VP.VMCALL 
<Service.MigTP.ReportStatus>  to report the migration status, after it programs the M SK to the 
TDX module.  
9.3 MigTD teardown  
MigTD can teardown itself after the migration is done with a special TDG.VP.VMCALL 
<Service.MigTD.Shutdown> . 
MigTD is only launched when the VMM starts to migrate.  
9.4 MigTD AP handling  
For simplicity, a MigTD may choose t o only support one processor.  
§  
 MigTD Measurement  
 
10 MigTD Measurement  
MigTD measurement is same as a normal TDVF.  
10.1 Non -Secure Boot Mode  
Usually, TD -Shim is treated as firmware code and extended to MRTD. The MigTD Core is treated 
as OS code and extended to RTMR[1]. The MigTD Po licy is treated as application code/config and 
extended to RTMR[2]. See table 10 -1. 
However, if we choose this approach, there is no way to know a secure version number (SVN) of a 
MigTD. If we want to allow a MigTD to support a different peer MigTD identif ied with SVN, then 
we need a different way – Secure Boot Mode.  
Table 10-1:  TD Measurement Registers for MigTD  (Non -Secure Boot)  
 
Typical Usage  Register  Event 
Log Extended by  Content  
Firmware Code  MRTD  NO VMM: SEAMCALL 
[TDH.MR.EXTEND]  TD-Shim  
Firmware Config  RTMR [0]  YES TD-Shim: TDCALL 
[TDG.MR.RTMR.EXTEND]  N/A 
OS code / 
Config  RTMR [1]  YES TD-Shim: TDCALL 
[TDG.MR.RTMR.EXTEND]  MigTD Core  
APP code/ 
Config  RTMR [2]  YES MigTD Core: TDCALL 
[TDG.MR.RTMR.EXTEND]  MigTD Policy (Including 
JSON style policy, Root CA 
Cert and CRL)

OS code / 
APP code/ 
Cert and CRL)  
10.2 Secure Boot Mode  
In Secure Boot Mode, only TD -Shim is extended to MRTD. TD -Shim can follow secure boot policy 
to verify the signature of MigTD and its SVN. The secure boot key is treated as firmware config 
and extended to RTMR[0]. The MigTD Core and its SVN are treated as OS code and config. They 
are extended to RTMR[1]. The MigTD policy is still treated as APP config and extended to 
RTMR[2]. See table 10 -2. 
With  this approach, the verifier can get the MigTD core SVN. If TD -Shim and secure boot key are 
same and MigTD Core and SVN are updated, the MigTD can verify peer by using the SVN.  
 MigTD Me asurement   
 
Table 10-2:  TD Measurement Registers for MigTD  (Secure Boot)  
 
[TDG.MR.RTMR.EXTEND]  Secure Boot Key  
OS code / 
[TDG.MR.RTMR.EXTEND]  MigTD Core, MigTdCore 
SVN  
APP code/ 
 
10.3 MigTD Binding  
MigTD should be bound with the target TD to be migrated. If VMM chooses to keep MigTD alive, 
the VMM can launch the MigTD at first then use of SEAMCALL[ TDH.SERVTD.BIND]  to bind the 
target TD. Then the VMM gets the TargetTD_UUI D and BindingHandle  and pass es them to 
MigTD in MIGTD_MIGRATION_INFORMATION . 
If VMM chooses to launch MigTD when it is required, then the VMM can use 
SEAMCALL [TDH.SERVTD.PREBIND]  to prebind the target TD. The VMM shall calculate the 
MigTD’s TDINFO_STRUCT then SERVTD_INFO_HASH. The SERVTD_INFO_HASH shall be input as 
parameter during prebind.  
 
§ 
  
 MigTD Metadata  
 
11  MigTD Metadata  
MigTD uses the same metadata defined as required for TDVF.  BFV and payload are required to 
indicate the MigTD image. CFV might be required, if CFV based policy is supported. The temp 
memory (stack / heap) and permanent memory are required to indicate the memory to be used 
by MigTD . TD HOB is NOT required in the MigTD . VMM shall follow the entries in TDVF descriptor 
to create the MigTD  memory one by one.  
 
§ Multiple TDs Migration   
 
12 Multiple TDs Migration  
 
12.1 Multi TDs Migration  
A VMM might need migration multiple TDs at one time. If o ne source MigTD and one destination 
MigTD set up the RA -TLS connection with mutual authentication, this connection can be used to 
migrate multiple TDs. See figure 12 -1. 
This model should be supported by default, because there is no need to set up  multiple RA -TLS 
sessions  if source MigTD and destination MigTD are same.  
 
Figure 12-1:  Multiple TDs Migration  
 
12.2 Multi RA -TLS connections  
One migration TD might support multiple RA -TLS connection sessions  to or from different 
migration TDs.  
12.2.1  Multi destination MigTDs  
In some case, a VMM might need migration multiple TDs to different platforms. As such, one 
source MigTD need setup connection to multiple destination MigTDs. See figure 12 -2. 
 
 Multiple TDs Migration  
 
Figure 12-2:  Multiple Destination Migration TDs  
12.2.2  Multi source MigTDs  
Similar to above case, a VMM might launch a destination and migration TD from different 
platforms. As such, one destination MigTD need wait for the connection f rom multiple source 
MigTDs. See figure 12 -3. 
 
Figure 12-3:  Multiple Source Migration TDs  
 
§ 
Multiple TDs Migration   
 
Appendix A  Reference  
[TDVF] Intel TDX Virtual Firmware Design Guide, 
https://software.intel.com/content/www/us/en/develop/articles/intel -trust -domain -
extensions.html   
[GHCI]  Guest Hypervisor Communication Interface  v1.5, 
extensions.html  
[TDX Module EAS]  Intel TDX Module v1.5 Base Architecture, Intel TDX Module v1.5 ABI, 
[TDX Migration]  Intel TDX Module v1.5 TD Migration Architecture, 
https://software.intel.com/content/www/us/en/develop/articles/intel -trust -doma in-
[Intel Attestation ] Intel Attestation Service , 
https://api.portal.trustedservices.intel.com/documentation  
[Intel PCK Service ] Intel Provisioning Certificate Service , 
https://api.portal.trustedservices.intel.com/prov isioning -certification   
[Intel PCK CRL ] Intel® SGX PCK Certificate and Certificate Revocation List Profile Specification, 
https://api.trustedservices.intel.com/documents/Intel_SGX_PCK_Certificate_CRL_Spec -1.5.pdf  
[Intel SGX DCAP Quote Lib ] Intel® SGX Data Center Attestatio n Primitive: ECDSA Quote Library 
API, https://download.01.org/intel -sgx/latest/dcap -
latest/linux/docs/Intel_SGX_ECDSA_QuoteLibRef erence_DCAP_API.pdf  
[Intel TDX DCAP Quote Lib ] Intel® Trust Domain Extensions Data Center Attestation Primitives 
(Intel® TDX DCAP): Quote Generation Library and Quote Verification Library , 
https://download.01.org/intel -sgx/latest/dcap -latest/linux/docs/TDX_Quoting_Library_API.pdf   
[Intel SGX DCAP  Grace Periods ] Quote Verification Grace P eriods with Intel® Software Guard 
Extensions Data Center Attestation Primi tive, 
https://www.intel.com/content/www/us/en/developer/articles/technical/grace -periods -for-intel -
sgx-dcap.html   
[JSON] JSON data model, https://www.json.org/json -en.html  
[CBOR] Concise Binary Object Representation,  http://cbor.io/  
[Intel RA -TLS] Intel Remote Attestation TLS, https://github.com/cloud -security -research/sgx -ra-
tls 
[Open Enclave RA -TLS]  open enclave Remote Attestation TLS, 
https://github.com/openenclave/openenclave/tree/ma ster/samples/attested_tls , 
https://github.com/openenclave/openenclave/blob/master/include/openenclave/attestation/att
ester.h , Multiple TDs Migration   
 
https://github.com/openenclave/openenclave/blob/master/include/openenclave/attestation/ver
ifier.h  
§  
 
Intel® TDX Module Architecture Specification:  TD 
Migration  
 
348550 -003 
TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 2 of 71 
without notice.  Intel does not guarantee the availability of these interfaces in any future product. Contact your Intel 
representative to obta in the latest Intel product specifications and roadmaps.  5 
This document contains information on products, services and/or processes in development. All information provided 15 
  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 3 of 71 
TD MIGRATION INTRODUCTION AND OVERVIEW  
 TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 4 of 71 
Section 1:  Introduction and Overview  1. About this Document  
1.1. Scope  of this Document

1.1. Scope  of this Document  
Extensions  (Intel ® TDX) module’s  Live Migration feature, implemented using the Intel TDX Instruction Set Architecture 
(ISA) extensions,  for cold  or live migration of Trust Domains in an untrusted hosted cloud environment . 5 
Table 1.1:  TDX Module Architecture Specification Set  
 TDX Module  
→  TDX Module  
 TDX Module  
TD Partitioning Architecture 
Specification  [TD Partitioning 
TD Partitioning  
 TDX Module  
 TDX Module  
 TDX Module  
 
This document is a work in progress and is subject to change based on customer feedback and internal analysis. This 
occur.  
1.2. Document Organization  15 
The document has two main sections:  
• Section 1 contains an introduction to the document , overview of TD Migration , scenarios and requirements . 
• Section 2 contains the Intel TDX Module  Migration architecture  
The detailed reference specification of TD Migration data structures and interface functions is provided in the [TDX 
Module ABI Spec ]. 20 TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 5 of 71 
Section 1:  Introduction and Overview  1.3. Glossary  
Table 1.2:  Intel TDX Module  Glossary  for TD Migration  
Acronym  Full Name  New 
for 
MigTD  Migration TD  Yes A specific type of Service TD  used to provide Live Migration capability for TD VMs. 
A Migration TD extends the TCB of the serviced tenant TD.  
MSK  Migration 
Session Key  Yes AES-GCM -256 key generated by the source MigTD and shared with the destination 
MigTD (protected by the Migration Transport key). This key helps protect  the TD 
private data and is used for export and import of the TD confidential assets.  
MTK  Migration 
Transport Key  Yes Authenticated Diffie -Helman negotiated symmetric  key generated after mutual 
attestation of the MigTDs and is used to help protect the transport of the 
Migration Session Key from the source to the destination platform.  
1.4. Notation  
1.5. References  
1.5.1.  Intel Public Documents  
See the [TDX Module Base Spec].  
1.5.2.  Intel  TDX Public Documents  
See the [TDX Module Base Spec].  10 
1.5.3.  Non -Intel Public  Documents  
Table 1.3:  Non -Intel Public Documents  
Reference  Document  Version & Date  
AES-256-GCM  NIST Special Publication 800 -38D:  Recommendation for Block 
Cipher Modes of Operation: Galois/Counter Mode (GCM) and 
GMAC  November 2007  
November 2023   . Page 6 of 71 
Section 1:  Introduction and Overview  2. TD Migration  Overview  
2.1. Introduction  
TDX-
Drivers
TDX-
Drivers
Drivers
Interface
 
Figure 2.1:  TD Migration  5 
Analogous to legacy VM migration,  a cloud -service provider (CSP) may want to relocate/migrate an executing Trust 
Domain from a source TDX platform  to a destination TDX platform  in the cloud environment.  A cloud provider may use 
TD migration to meet customer SLA, while balancing cloud platform upgradability, patching and other serviceability 
requirements.  Since a  TD runs in a CPU mode which helps protect the confidentiality of its memory contents and its CPU 
state from any other platform software, includin g the hosting Virtual Machine Monitor (VMM ), this primary security 10 
objective must be maintained while allowing the TD resource manager, i.e., the host VMM to migrate TDs across 
compatible platforms .  The TD typically may be assigned a different HKID (and will be always assigned a different 
ephemeral key) on the destination platform chosen to migrate the TD.  
In this specification, the TD being migrated is called the source TD , and the TD created as a result of the migration is called 
the destination TD .  An extensible TD Migration Policy  is associated with a TD that is used to maintain the TD’s security 15 
posture.   The TD Migration policy is enforced in a scalable and extensible manner using a specific type of Service TD  called 
the Migration TD (a .k.a. MigTD)  (introduced in the Figure 2.2 below) – which is used to provide services for migrating 
TDs.  
The TD Live Migration process (and the Migration TD) does not depend on any interaction with the TD guest software 
operating inside the TD being migrated.  20 
2.2. TD Migration Scenarios  
This section describes the usage scenarios addressed by this specification (and those explicitly out of scope). This 
specification documents the TD Migration functionality from a Live Migration (scenario described below) perspective. 
Cold Migration and oth er scenarios described below are effectively subset scenarios that are software managed via the 
Intel TDX module interface functions  in this specification.  25 
2.2.1.  Cold migration  
Cold migration with destination known and resumed such that both ends must be alive to do the handoff  
• TD image is suspended  during migration and resumed after a duration >> TCP timeout  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 7 of 71 
Section 1:  Introduction and Overview  • Useful for rolling upgrades/patch  + rebooting servers (non-reboot patches can be done without migrating the TD ), 
capacity planning  and load balancing . 
2.2.2.  Live Migration  
Live migration with destination known and resumed such that both ends must be alive to do the handoff  
• TD executing  during migration and paused for duration << TCP timeout  5 
• Customer SLA, capacity planning/load balancing  
A TD may be live migrated more than once using multiple sessions.  
2.2.3.  Image Snapshot and Jumpstart   
Pre-built Image/Jumpstart with destination unknown and TD image stored for an indeterminate amount of time . 
This usage has additional platform security requirements that are not comprehended in this specification.  Example  use 10 
cases are saving checkpoints of TDs such that TD may be pre-load ed into memory . Alternate implementations to satisfy 
this usage are possible .  E.g., the TD could un -hibernate the image itself .  This scenario/use case is out of scope for this 
specification . 
2.3. Components Involved in TD Migration  
The main components involved in TD migration are:  15 
• The TD being migrated  
• Host VMMs on the source and destination platforms  
• Migration TDs on the host and destination platforms  
Destination Platform Source Platform
Migration TD
Migrated TD
Host VMMSession 
ControlSession
Keys 
Exchange
Session 
ControlSession Control,
Keys Exchange
TDX Metadata 
APITDX Metadata

Keys 
Exchange
Session 
APITDX Metadata 
APIMigration TD
Keys 
Exchange
Session 
Control
TDX Import
APITDX Export
API
Session Control,
TD Non -Memory State,
TD Private Memory
 
Figure 2.2:  Component Involved in TD Migration  20 
A Migration TD  (MigTD) is used to  evaluate potential migration sources and targets for adherence to the TD Migration 
Policy.   The TD Migration policy enumerates TDX platform TCB requirements as well as acceptable destination Migration 
TD TCB levels.  
If TCB levels are acceptable , the Mig ration TDs on the source and destination platforms securely exchange unique per -
session Migration Session Key s (MSK s)  which are used to migrate assets of a specific TD.   The MigTD on each side reads 25 
an encryption key generated by the TDX module, as TD metadata, and transfers it to the MigTD on the other side.  That 
MigTD writes the key, as TD metadata, as the decryption key for its side.  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 8 of 71 
Section 1:  Introduction and Overview  The host VMM may bind  a MigTD to one or more TDs being migrated.  For details, see [ TDX Module  Base  Spec ]’s Service 
TDs chapter .  Since the MigTD is in the TCB of the TD being migrated, a MigTD must be pre -bound to the target TD being 
migrated before the target TD measurement is finalized.  The MigTD lifecycle does not have to be coincidental with the 
target TD – the MigTD may be instantiated when required for Live Migration, but it must be bound to the target TD before 
Live Migration can begin, and must be  operational until the migration session keys has been successfully programmed 5 
for the target TD being migrated.   The MigTD measurements are in included in the target TD’s attestation information 
structures.  
The host VMM , via the Intel TDX Module , is responsible for export/import of the TD content , and the transport of the 
protected TD content to the destination platform.    
2.4. Migrated Assets  10 
The table below shows the TD assets that are migrated.  Metadata includes TD -scope and VCPU -scope non -memory state 
(such as control state, CPU register state etc.) and memory attributes (such as GPA and access permissions).  Metadata 
is not migrated as -is; it is serialized into a migration format and re -created on the destination platform.  
Table 2.1:  Migrated TD Assets  
TD Asset  Where Held  Export Functions  Import Functions  
Immutable Non -Memory 
State (Metadata)  TDX module global  
TDR  
TDCS  TDH.EXPORT.STATE.IMMUTABLE  TDH.IMPORT.STATE.IMMUTABLE  
Mutable Non -Memory 
State (Metadata)  TDCS  
TDVPS  TDH.EXPORT.STATE.TD  
TDH.EXPORT.STATE.VP  TDH.IMPORT.STATE.TD  
TDH. IMPORT.STATE.VP  
Memory State and 
Metadata  TD private pages  
Secure EPT  TDH.EXPORT.MEM  TDH. IMPORT.MEM  
 15 
2.5. Guest TD Migration Life Cycle  Overview  
2.5.1.  Pre-Migration  
 Intel TDX Module Enumeration  
The host VMM calls the TDH.SYS. RD or TDH.SYS.RDALL  interface  function to enumerate Intel TDX Module functionality 
and learns from the TDX_FEATURES  that the Intel TDX Module supports TD Migration .  The host VMM learns details of 20 
TD migration capabilities and service TD capabilities from the other fields . TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 9 of 71 
Section 1:  Introduction and Overview  2.5.2.  Reservation and Session Setup  
TD Build
TD Skeleton CreationTypical Migration Session (1/3):  Migration TD Binding and Session Setup
3UNINITIALIZEDTD May Run on Source Platform
RUNNABLE
TDH.EXPORT.
STATE.
IMMUTABLE
TDH.IMPORT.
STATE.
IMMUTABLETDG.SERVTD.
WR(dec key)TDG.SERVTD.
WR(dec key
TDH.MNG.
CREATETDH.MNG.
ADDCXTDH.MNG.
ADDCXTDH.SERVTD.
BINDTDG.SERVTD.
RD(enc key)TDG.SERVTD.
RD(enc key)
Session k eysexchange
by Migration TDsSource DestinationTDH.SERVTD.
BINDTDH.MR.
FINALIZE
 
Figure 2.3:  Migration TD Binding and Session Setup  
 Guest TD Build , Migration TD Binding and TD Execution  on the Source  Platform  
The source TD build and execution process is described in the [ TDX Module Base Spec ].  To be migratable, the TD may be 5 
initialized, using the TDH.MNG.INIT function, with ATTRIBUTES.MIGRATABLE  bit set to 1.  
Before a migration session can begin, the  host  VMM on the source platform must use TDH.SERVTD.BIND to bind a 
Migration TD to the source TD.   The MigTD may read selected metadata fields of the source TD, e.g., its ATTRIBUTES and 
XFAM configuration, to be used in evaluating a migration policy.  
 Guest TD Initial Build  on the Destination  Platform  10 
Same as a legacy TD  build process , the host VMM creates a new guest TD by using the TDH.MNG.CREATE interface  
function.  This destination TD is setup as a “template” to receive the state of the Source Guest TD.  The  host  VMM 
programs the HKID and the HW-generated encryption key assigned to the TD into the MKTME encryption engines using 
the TDH.MNG.KEY.CONFIG interface function on each package.  The host VMM can then continue to build the TDCS by 
adding TDCS pages using the TDH.MNG.ADDCX interface function . 15 
Once the destination TDCS is built and before TD import can begin, the VMM on the destination platform must use 
TDH.SERVTD .BIND to bind  a Migration TD to the destination TD.   
 Migration Session Key Negotiation  
The Migration session keys are an ephemeral AES -256-GCM keys used for confidentiality and integrity protection of the 
TD private state exported from the source platform and imported on the destination platform, and for integrity 20 
protections of the migration session control protocol.  TD shared memory state is migrated by the untrusted host VMM 
per legacy methods – the same network transport may be used for both by the host VMM.  The Migration Session Key 
(MSK) is established by a Migration TD which is responsible for evaluation of the Migration policy for the TD being 
migrated.  
The migration TDs executing on the source and destination platforms use a TD -quote -based mutual authentication 25 
protocol to create a VMM -transport -agnostic session between them.  The Migration TDs negotiate a protected transport 
session (using Diffie -Hellman exchange).  Using this protected transport session, the migration policy can be evaluated 
by the Migration TD . 
The Service TD binding mechanism supported by the TDX module allows the Migration TD to access target TD metadata 
– specifically the Migration session keys.  The MigTD can access the TD metadata using TDG.SERVTD.RD/WR* guest -side 30 
interface functions.  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 10 of 71 
Section 1:  Introduction and Overview  The TDX modules on both the source and destination platforms generate ephemeral migration session encryption keys .  
The Migration TDs on each side uses the Service TD interface read that key and securely transfer it to the peer Migration 
TD, which uses the Service TD interface to write it as the migration session decryption key . 
After this point, the host VMM can invoke TDX Module functions such as TDH.EXPORT.* to export state at the source 
platform and TDH.IMPORT.* to import TD state at the destination platform.  The protocol is described in Ch. 5.5 in detail.  5 
2.5.3.  In-Order Memory Migration Phase  
TDX-Imposed Blackout
STATE_IMPORTTypical Migration Session (2/3):  In -Order Memory Migration
4UNINITIALIZEDTD May Run on Source Platform
RUNNABLE
MEMORY_IMPORTPAUSED_EXPORT LIVE_EXPORTIn-Order Memory Export Phase
In-Order Memory Import PhaseTDH.EXPORT.
STATE.
IMMUTABLETDH.EXPORT.
PAUSETDH.EXPORT.
TRACK(DONE)
STATE.
IMMUTABLETDH.IMPORT.
TRACK(DONE)Start
TokenSource DestinationTDH.EXPORT.
MEMTDH.EXPORT.
MEM
MEMTDH.IMPORT.
MEM
STATE.TDTDH.MNG.
ADDCXTDH.IMPORT.
STATE.VPTDH.EXPORT.
ADDCXTDH.EXPORT.
STATE.VP
 
Figure 2.4:  In-Order Migration Phase  
 TD Global Immutable Metadata (Non -Memory  State ) Migration  
Intel TDX Module  protects the confidentiality and integrity of a guest TD global state .  Control structures, which hold 10 
guest TD metadata, are not directly accessible to any software  (besides the Intel TDX Module)  or devices .  These 
structures are stored encrypted and integrity -protected in memory with the TD private key  and managed by Intel TDX 
Module  interface  functions . 
Immutable metadata is the set of TD state variables that are set by TDH.MNG.INIT, may be modified during TD build but 
are never modified after the TD’s measurement is finalized using TDH.MR.FINALIZE.  Some of these state variables control 15 
how the TD and its memory is migrated.  Therefore, the immutable TD control state is migrated before any of the TD 
memory state is migrated.

STATE.VP
 
memory state is migrated.  
TD immutable state is exported via the TDH.EXPORT.STATE.IMMUTABLE interface function  and imported on the 
destination platform via the TDH.IMPORT.STATE.IMMUTABLE interface function .  TD global immutable state migration is 
describe d in Ch. 7. 20 
 Iterative Pre-Copy of Memory State  
2.5.3.2.1.  Migration Considerations for TD Private Memory  
Intel TDX helps protect guest TD state in private memory from a malicious VMM, using MKTME (memory encryption and 
integrity protection) and the Intel TDX Module.  The Intel TDX Module performs ephemeral key id management  to enforce 
the TDX security objectives.  Memory encryption is performed by encryption engines that reside at each memory 25 
controller , with no software access (including the TDX module) to the ephemeral keys .  The memory encryption engine 
holds a table of encryption keys, in the Key Encryption Table (KET).  The encryption key selected for memory transaction s 
is based on a Host Key Identifier (HKID)  provided with the memory access transaction.  
The Intel TDX Module  API functions enable the host VMM  to manage HKID assignment to guest TDs, configure the 
memory encryption engines etc., while assuring proper operation to maintain TDX’s security objectives.   The host VMM 30 
also does not have access to the TD encryption keys.  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 11 of 71 
Section 1:  Introduction and Overview  TD Migration do es not migrate the HKID s – a free HKID is assigned to the TD created on the destination platform to 
receive migratable assets of the TD from the source platform.  All TD private memory is protected during transport from 
the source platform to the destination platform using an intermediate encryption performed using AES -GCM 256 using 
the MSK negotiated via the Migration TDs on the source and destination platform.  On the destination platform the 
memory is encrypted via the destination ephemera l key as it is imported into the destination platform memory assigned 5 
to the destination TD.  The import operation on the destination TDX module verifies and decrypts the TD private data 
using the MSK ; it uses the MKTME engine to encrypt (and integrity protect) while writing it to memory using the 
destination  TD HKID.  
During live migration, the source TD is allowed to modify private memory (until the source TD is paused by the host VMM 
to complete the last phase of migration).  To allow this, TD private memory  is migrated over a set of Migration Epochs .  10 
Migration epochs enforce TD Live migration security property S4: CSP must not be able to operate the destination TD 
on any stale state from the source TD .   The host VMM may also instantiate  multiple migration streams  for memory 
state transfer (for example to leverage multiple host hardware threads) – as long as the security invariants are not 
violated. TD Private memory migration is described in Ch. 8 in detail.  
Shared memory assigned to the TD is migrated using legacy mechanisms used by the host VMM.  15 
Encryption -based memory protection is described in the [MKTME PAS] and the ISA is described in the [Intel TDX PAS] .  TD 
migration has no change to TD key management when the Migration TD uses an independent HKID.  
2.5.3.2.2.  Migration Considerations for EPT Structures  
Guest Physical Address (GPA) space is divided into private and shared sub -spaces, determined by the SHARED bit of GPA.  
The CPU translates shared GPAs using the Shared EPT, which resides in host VMM memory, and is directly managed by 20 
the host VMM, same as with legacy VMX. The CPU translates private GPAs using a separate Secure EPT.  Secure EPT pages 
are encrypted and integrity protected with the TD’s ephemeral private key.   
As there is no guarantee of allocating the same physical memory addresses to the TD being migrated on the destination 
platform, the memory used for Secure EPT structures is not migrated across platforms .  Hence, the VMM must invoke 
the TDX module ’s TDH.MEM.SEPT .* interface functions  on the destination platform to re -create the private GPA 25 
mappings on the destination platform (per the assigned HPAs).  The Intel TDX module uses the cryptographically 
protected exported meta -data (generated via TDH.EXPORT.MEM) to verify and enforce (via the TDH.IMPORT.MEM) that 
the Secure EPT security properties from the source platform are rec -created correctly as TD private memory cont ents are 
migrated, thus preventing remap attacks during migration. TD private memory migration is described in Ch. 8 in detail.  
Even though S ecure EPT structures are not migrated, the source SEPT structures track the state of the mappings when a 30 
page is exported and then modified by the TD OS in the pre -copy stage.  The TD OS may be allowed to modify such a page 
and the TDX module enforces that the modified  and previously exported page is re -exported by the  source host  VMM  
and re -imported  by the destination host VMM.  
 Source TD Stop and Final Non -Memory State Migration   
Following pre -copy of TD private memory, the host VMM must pause the source TD for a brief period (also called the 35 
blackout period) so that the VMM may export the final control state (for all VCPUs and for the TD overall).  The VMM 
initiates this via TDH.EXPORT.PAUSE, which checks security pre -conditions and prevents TD VCPUs from executing any 
more.  It then allows ex port of final (mutable) TD non -memory state.  
 In-Order Memory State Re-Migration  Completion  
Any memory state that has been migrated must be up to date when the in -order phase completes.  If a  memory page 40 
had been migrated and its content was later updated by the running TD, it must be re -migrated.  The TDX Module 
enforces this using the commitment protocol described in 2.5.6 below . 
 TD-Scope and VCPU -Scope Mutable Non -Memory State Migration  
TD mutable non -memory state is a set of source TD state variables that might have changed since it was finalized via 
TDH.MR.FINALIZE.  Immutable non -memory state exists for the TD scope (as part of the TDR and TDCS control structures) 45 
and the VCPU scope (as part of the TDVPS control structure).  
Mutable TD state is exported by TDH.EXPORT.STATE.TD (per TD) and TDXPORT.STATE.VP (per VCPU) and imported by 
TDH.IMPORT.STATE.TD and TDH.IMPORT.STATE.VP respectively.  This is described in Ch. 7. TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 12 of 71 
Section 1:  Introduction and Overview  2.5.4.  Out-Of-Order Memory Migration Phase  
TD May Run on Destination PlatformRUNNABLETD May Not Run on Source Platform TDX-Imposed Blackout
POST_EXPORT
LIVE_IMPORT POST_IMPORT STATE_IMPORTTypical Migration Session (3/3):  Out -of-Order Memory Migration
5PAUSED_EXPORTIn-Order Memory Export Phase
MEM
MEM
MEMOut-Of-Order Memory Export Phase
Out-Of-Order Memory Import PhaseTDH.IMPORT.
COMMITTDH.EXPORT.
MEM
MEM
END
 
Figure 2.5:  Out -Of-Order Migration Phase  
 Migration of Memory State  and Commitment of Import  
Memory pages that have not been migrated during the in -order phase may be migrated during the out -of-order phase.  5 
Since the memory state on the source platform does not change at this stage, the order of migration is not enforced.  
The host VMM on the destination platform commits the import by calling TDH.IMPORT.COMMIT or TDH.IMPORT.END.  
At that point, the TD may run on the destination platform and may not run on the source platform.  
 Post -Copy of Memory State  
In some live migration scenarios, the host VMM may stage some memory state transfer to occur lazily after the 10 
destination TD has started execution.  In this case, the host VMM will be required to fetch the required pages as accesses 
occur by the destination TD – this order of access is indeterminate and will likely differ from the order in which the host 
VMM has q ueued memory state to be transferred.  
In order to support that on -demand model, the order of memory migration during this post -copy  stage  is not enforced 
by TDX.  The host VMM may implement multiple migration queues with multiple priorities for memory state transfer.  15 
For example, the host VMM on the source platform may keep a copy of each encrypted migrated page until it receives a 
confirmation from the destination that the page has been successfully imported.  If needed, that copy can be re -sent on 
a high priority que ue.  Another option is, instead of holding a copy of exported pages, to call TDH.EXPORT.MEM again on 
demand.  
Also, to simplify host VMM software for this model, the TDX module interface functions used for memory import in this 20

demand.  
Also, to simplify host VMM software for this model, the TDX module interface functions used for memory import in this 20 
post -copy stage return additional informational error codes to indicate that a stale import was attempted by the host  
VMM to account for the case where the low latency  import operation for a GPA superseded the import from the higher 
latency import queue.  
2.5.5.  Aborted Private Memory Migration  
In a live migration scenario, an error may cause CSP orchestration to abort an active TD live migration session.  In such a 25 
scenario, the host VMM on the source platform may pro -actively initiate an abort via TDH.EXPORT.ABORT .  It may also 
respond to a n about token received from the destination platform, where it may be generated by  TDH.IMPORT.ABORT 
for a late abort (after pre -copy has been completed).  In both scenarios, the host VMM must reset the state of the SEPT  
state of exported pages  on the source platform , using TDH.EXPORT.RESTORE . TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 13 of 71 
Section 1:  Introduction and Overview  2.5.6.  Commitment  
The commitment protocol is enforced by the Intel TDX Module to help ensure that a host VMM cannot violate the  security 
objectives of TD Live migration – for example,  both the destination and source TD must not continue to execute after live 
migration of the source TD to a destination TD, even if an error causes the TD migration to be aborted.  
This protocol is enforced via the following TDX Module interface function s:  5 
• On the source platform, TDH.EXPORT.PAUSE starts the blackout phase of TD live migration  and TDH.EXPORT .TRACK  
ends the blackout phase of live migration ( and marks the end  of the transfer of TD memory pre -copy, mutable TD VP 
and mutable TD global control state ). TDH.EXPORT.TRACK generates a MSK -based cryptographic ally-authenticated  
start token to allow the destination  TD to become runnable. On the destination platform, TDH.IMPORT.TRACK – 
which consumes the cryptographic start token, allows the destination TD to be un -paused.  10 
• In error scenarios, the migration process may be aborted proactively by the host on the source platform via 
TDH.EXPORT.ABORT before a start token was generated; if a start token was already generated (i.e. pre -copy 
completed), the destination platform can generate an abort token using TDH.IMPORT.ABORT which generates an 
abort token which may be consumed by TDH.EXPORT.ABORT by the source TD platform TDX Module to abort the 
migration process and again allows the source TD to become runnable again.  15 
The detailed operations are described in Ch. 5.5. 
2.6. Impact of Migration on Measurement and Attestation  
TD measurement is extended for the MigTD bound to the TD being migrated , and the ATTRIBUTES.MIGRATABLE bit is 
part of the TD attestation.  For details, see the [ TDX Module Base Spec ]. 
2.7. Intel TDX Module Managed  Control Structures  affected by Migration  20 
Intel TDX Module manages a set of control structures that are not directly accessible to untrusted host software. The 
control -structures are protected in memory using encryption and integrity (with TDX private keys). Most control 
structures are in memory a ssigned to the TD by the host VMM.  The following table describes the impact of Migration on 
the TD control structures.  See the detailed definition of these structures in the [TDX Module ABI Spec ]. 
Table 2.2:  TDX-Managed  Control Structures  25 
Scope  Name  Meaning  Migration Impact  
Platform  KOT  Key Ownership 
Table  None  
PAMT  Physical Address 
Metadata Table  PAMT.BEPOCH is used to hold migration epoch information  
Guest TD  TDR  Trust Domain 
Root  None  
TDCS  Trust Domain 
Control Structure  TD ATTRIBUTES field has a new MIGRATABLE Security attribute 
that must be set for a TD to be migratable.  
Some state is initia lized (same as legacy)  and some state is 
imported via TDH.IMPORT.STATE.IMMUTABLE and 
TDH .IMPORT.STATE.TD.  
TDCS has new Migration stream context structures associated 
with the TD setup via TDH.MIG.STREAM.CREATE . 
SEPT  Secure EPT  SEPT entry state is much extended to support tracking of 
memory export and import by the TDX module.  
TDINFO_
STRUCT  TD 
measurement  A new field SERVTD_HASH is added , see the [ TDX Module 
Base Spec ] for details.  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 14 of 71 
Section 1:  Introduction and Overview  Scope  Name  Meaning  Migration Impact  
Guest TD 
VCPU  TDVPS  Trust Domain 
Virtual Processor 
State  Some state is initiated and some state Imported via Intel TDX 
Module  API TDH.IMPORT.STATE.VP for migrating V CPU  control 
state  
 
There are new data structures introduced for TD Migration that are generated by the TDX -module (and managed by the 
VMM).  
Table 2.3:  TDX-Generated  Control Structures  
Name  Meaning  Migration impact  
MBMD  Migration Bundle 
Metadata  Common header and type information for migrated information  
GPA_LIST  GPA list of 
migrated pages  List of GPAs and associated attributes, used for memory 
migration and related memory operations  
MIGRATION_BUFFER_  
LIST  Migration buffer 
list List of  migration buffer s provided by the host VMM to hold 
migration data  
2.8. Intel TDX Module  TD Migration Interface  Functions  Overview  5 
See the [ TDX Module Base Spec ]’s overview chapter.  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 15 of 71 
Section 1:  Introduction and Overview  3. TD Migration Software Flows   
This chapter summarizes the software flows used for TD migration using Intel TDX Module interface functions . 
3.1. Typical TD Migration Flow Overview  
Source Platform   Destination Platform  
1. Create Worker Threads, disable 
device optimizations     4. Receive memory layout and 
device resource information  
2. Save memory layout and device 
resource information     5. Allocate guest memory and 
reserve resources on devices  
3. Send memory layout and 
resource  information to the 
destination host  Send Migration Information  → Receive Migration Information   
    6. Setup worker process and signal 
the completion to source host  
 TDH.SERVTD.BIND   TDH.SERVTD.BIND   
 Establish DH session between 
MigTD s using QE  → Establish DH session between 
MigTD s using QE   
7. MigTDs exchange session keys, 
version information etc.  TDG.SERVTD.RD, TDG.SERVTD.WR  → TDG.SERVTD.RD  TDG.SERVTD.WR  8. MigTDs exchange session keys, 
version information etc.  
 TDH.EXPORT.STATE.  
IMMUTABLE  → TDH.IMPORT.STATE.  
IMMUTABLE   
 Memory Pre -Export   Memory Pre -Import   
9. Run multiple  passes of memory 
walker to transfer dirty guest -
memory pages   TDH.EXPORT.BLOCKW    
10. Import TD memory contents  TDH.MEM.TRACK    
TDH.EXPORT.MEM  → TDH.IMPORT.MEM  
TDH.EXPORT.UNBLOCKW    
TDH.EXPORT.TRACK  → TDH.IMPORT.TRACK  
 TDH.EXPORT.PAUSE     
11. Export mutable state  TDH.EXPORT.STATE.TD  → TDH.IMPORT.STATE.TD  
12. Import mutable state  
TDH.EXPORT.STATE.VP  → TDH.IMPORT.STATE.VP  
 TDH.EXPORT.TRACK(start token)  → TDH.IMPORT.TRACK(start token)   
13. Export memory  TDH.EXPORT.MEM  → TDH.IMPORT.MEM  14. Import memory  
 15. (optional) Send end of export 
indication  → 16. (optional) Receive end of export 
indication   
   TDH.IMPORT.COMMIT   
    17. Resume VPs  
   18. (optional) Request post -copy of 
pages   
19. (optional) Export memory (post -
copy)  TDH.EXPORT.MEM  → TDH.IMPORT.MEM   
   TDH.IMPORT.END   
 Receive migration success 
indication   Send migration success indication   
 Indicate success to VM  
Management   Indicate success to VM  
Management   
20. Tear -down source TD      
Figure 3.1:  Typical TD Migration Flow  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 16 of 71 
Section 1:  Introduction and Overview  3.2. Successful TD Export  
The following sequence is typically used to export a TD from a source platform.  
Table 3.1:  Typical TD Export Sequence  
Migration 
Phase  Step  Description  Plurality  TDX Module Interface Function s 
In-Order 
Export  Start of 
Export 
Session  VMM  initializes MigTD (as a non-
migratable  TD) and  binds it to the source  
TD. Once  TDH.SERVTD.BIND  
VMM/orchestration sets up transport 
session between source and destination 
MigTD .  MigTDs setup their own protected 
channel . Once   
MigTDs reads the session encryption key, 
version information and other metadata 
from the source TD and send s it to the 
MigTD on the destination . Once  TDG.SERVTD.RD  
MigTD receives the session encryption key 
from the MigTD on the destination, and 
writes it as the session decryption key to 
the source TD.  It may also write the 
migration version.  Once  TDG.SERVTD.WR  
VMM starts the export session and 
exports immutable state creating a state 
migration bundle.  Once  TDH.EXPORT.STATE.IMMUTABLE  
Live  Memory 
Export  Host VMM blocks a set of pages for 
writing.  Multiple  TDH.EXPORT.BLOCKW  
Host VMM increments the TD’s TLB epoch  Once per 
migration

In-Order 
Export 
migration 
epoch  TDH.MEM.TRACK  
Host VMM starts migration epoch and 
creates epoch token migration bundle;  a 
page can be exported once per epoch.  Once per 
migration 
epoch  TDH.EXPORT.TRACK(epoch token)  
Host VMM exports, re -exports or cancels 
the export of TD private pages and creates 
a memory migration bundle.  Multiple  TDH.EXPORT.MEM  
TD write attempt to write to page blocked 
for writing results in an EPT violation.  The 
host VMM unblocks the page; if already 
exported, it will need to be re -blocked 
and re -exported.  Multiple  TDH.EXPORT.UNBLOCKW  
Mutable Non-
Memory 
State Export  VMM pauses the source TD  Once  TDH.EXPORT.PAUSE  
VMM exports mutable TD -scope state and 
creates a state migration bundle.  Once  TDH.EXPORT.STATE.TD  
VMM exports mutable VCPU -scope state 
and creates a state migration bundle.  Per VCPU  TDH.EXPORT.STATE.VP  
Out-Of-
Order 
Export  Cold  Memory 
Export  Host VMM starts the out -of-order export 
phase and creates a start token migration 
bundle.  Once  TDH.EXPORT.TRACK(start token)  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 17 of 71 
Section 1:  Introduction and Overview  Migration 
Host VMM exports TD private pages and 
creates a memory migration bundle.  Multiple  TDH.EXPORT.MEM  
TD 
Teardown  End Host VMM gets success notification from 
the destination platform, terminates the 
export session and tears down the TD on 
the source platform  Once  TDH.MNG.VPFLUSHDONE  
TDH.PHYMEM.CACHE.WB  
TDH.MNG.KEY.FREEID  
TDH.PHYMEM.PAGE.RECLAIM  
TDH.PHYMEM.PAGE.WBINVD  
 
3.3. Successful TD Import  
The following sequence is typically used to import  a TD to a destination platform.  
Table 3.2:  Typical TD Import  Sequence  
Migration 
In-Order 
Import  Start of 
Import 
Session  VMM creates the destination TD’s 
skeleton  Once  TDH.MNG.CREATE  
TDH.MNG.KEY.CONFIG  
TDH.MNG.ADDCX  
VMM  initializes MigTD (as a non -
migratable TD) and  binds it to the 
destination TD. Once  TDH.SERVTD.BIND  
channel.  Once   
from the destination TD and sends it to 
the MigTD on the source.  Once  TDG.SERVTD.RD  
from the MigTD on the source, and writes 
it as the session decryption key to the 
destination TD.  It may also write the 
VMM starts the import session and 
imports immutable state with a state 
migration bundle received from the 
source platform.  Once  TDH.IMPORT.STATE.IMMUTABLE  
Pre-Copy 
Memory 
Import  Host VMM builds the Secure EPT by 
allocating physical pages . Multiple  TDH.MEM.SEPT.ADD  
Host VMM imports TD private pages with 
a memory migration bundle received from 
the source platform.  Multiple  TDH.IMPORT.MEM  
Host VMM starts migration epoch with an 
epoch token migration bundle received 
from the source platform;  a page can be 
imported once per epoch.  Once per 
migration 
epoch  TDH.IMPORT.TRACK(epoch token)  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 18 of 71 
Mutable TD -
scope and 
VCPU -scope 
non -memory 
state import  VMM imports mutable TD -scope state 
with a state migration bundle received 
from the source platform.  Once  TDH.IMPORT.STATE.TD  
VMM creates VCPU.  Per VCPU  TDH.VP.CREATE  
VMM allocates physical pages for the 
VCPU’s TDVPS.  Multiple 
per VCPU  TDH.VP.ADDCX  
VMM imports mutable VCPU -scope state 
from the source platform.  Per VCPU  TDH.IMPORT.STATE.VP  
Out-Of-
Order 
Import  Pre-Copy 
Memory 
Import  Host VMM starts the out-of-order import 
phase with a start token migration bundle 
received from the source platform.  Once  TDH.IMPORT.TRACK(start token)  
Host VMM builds the Secure EPT by 
Post -Copy 
Memory 
Import  Host VMM commits the import session, 
allowing the TD to run on the destination 
platform.  Once  TDH.IMPORT.COMMIT  
Host VMM can execute the TD as usual.  
Memory can be imported on demand.  Per VCPU  TDH.VP.ENTER  
On EPT violation, host VMM requests a 
page import from the source platform.  Multiple  N/A 
End Host VMM terminates the import session  Once  TDH.IMPORT.END  
 
3.4. TD Import Abort  
The following sequence s are  typically used to abort an import of TD to a destination platform , if an error is detected.  
3.4.1.  TD Import Abort During the In -Order Import Phase  
Table 3.3:  Typical TD Import Sequence  Abort During In -Order Input  5 
Migration 
In-Order 
Import      
allocating physical pages . Multiple  TDH.MEM.SEPT.ADD  TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 19 of 71 
Pre-Copy 
Memory 
Import 
(Failed)  Host VMM imports TD private pages with 
the source platform.  
TDH.IMPORT.MEM returns an error status 
indicating a failed import session.  Multiple  TDH.IMPORT.MEM  
Abort Token 
Transmission 
(Optional)  VMM creates an abort token and 
transmits it to the source platform.  Once  TDH.IMPORT. ABORT  
TD 
Teardown  End Host VMM terminates the import session 
and tears down the TD on the destination  
platform  Once  TDH.MNG.VPFLUSHDONE  
 
3.4.2.  TD Import Abort During the Out -Of-Order Import Phase  
Table 3.4:  Typical TD Import Sequence Abort During Out -of-Order Input  
Migration 
In-Order 
Import      
Out-Of-
Order 
Import  Memory 
Import 
(Failed)     
Transmission  VMM creates an abort token and 
transmits it to the source platform.  Once  TDH.IMPORT.ABORT  
TD 
and tears down the TD on the destination 
 
3.5. TD Export Abort  5 
The following sequence is typically used to export a TD from a source platform, if the export is aborted.  
3.5.1.  Export Abort During the In-Order Export Phase  
Table 3.5:  Typical TD Export Sequence Abort During In-Order Export  
Migration 
   TDX Module TD Migration Spec  Section 1:   Introduction and Overview  348550 -003  
November 2023   . Page 20 of 71 
In-Order 
Export 
Session  VMM starts the export session and 
Export Abort   Host VMM aborts the export session.  Once  TDH.EXPORT. ABORT  
Source TD 
Run and 
Restore   Host VMM may run and manage the 
source TD  Multiple  TDH.VP.ENTER etc.  
Host VMM restores SEPT entries to their 
normal non -export state  Multiple  TDH.EXPORT.UNBLOCKW  
TDH.EXPORT.RESTORE  
 
3.5.2.  Export Abort During the Out -Of-Order Export Phase  
Table 3.6:  Typical TD Export Sequence Abort During Out -Of-Order Export  
Migration 
In-Order 
Export      
Out-Of-
Order 
Export      
Export Abort   Host VMM receives an abort token from 
the destination platform and abort the 
export session.  Once  TDH.EXPORT.ABORT  
Source TD 
Run and 
normal non-export state  Multiple  TDH.EXPORT.UNBLOCKW  
 
 5 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003

Source TD 
Run and 
 
Migration 
In-Order 
Export      
Out-Of-
Order 
Export      
Source TD 
Run and 
 
 5 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 21 of 71 
Section 2:  TD Migration Architecture Specification  SECTION  2: 
TD MIGRATION ARCHITECTURE SPECIFICATION  
 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 22 of 71 
Section 2:  TD Migration Architecture Specification  4. Migration TD , Migration Policy and the Extended TCB  
This chapter describes the role of the Migration TD , the migration policy it implements and the extended TCB for migrated 
TDs.  For details  of the Intel reference MigTD , refer to the [MigTD Spec].  
4.1. Extended TCB and the Migration Policy  
The TCB of a migrated TD is extended to include the Migration TD bound to it.  The Migration TD builds trust relationships 5 
with to other Migration TDs, and through them, with other platforms and their component.  Thus, it can be said that a 
migrated TD’s effective TCB extends to the whole migration pool of platforms , each with its own Migration TD, TDX 
modules etc . 
PlatformMCHECK NP-SEAMLDR Other ACMsTDX 
VMM
VM
VMLegacy
VM
P-SEAMLDRMig
TDA BA trusts B
Source PlatformDestination Platform XMig
TD
Destination Platform YMig
TDMig 
PolicyMig 
Policy
Mig 
Policy
 
Figure 4.1:  Trust Relationship with Migration TDs  10 
This extended TCB is controlled by the migration policy  implemented by the Migration TD.  TDX does not enforce any 
specific migration policy; this is up to the migration TD’s writer.  
4.2. Attestation of the Migration TD and its Migration Policy  
A migrated TD’s attestation reflects the current platform on which it is running.  I.e., calling TDG.MR.REPORT generate s 
a TDREPORT_STRUCT with CPUSVN and TEE_TCB_INFO for the current platform.   However, there is no requirement to 15 
re-attest a TD after migration.  The initial attestation, as well as attestation done at any time during the migrated TD’s 
lifetime , contains the information about the TD’s extended TCB, provided as a measurement of the Migration TD and its 
migration policy.  
A Migration TD is a private case of a Service TD , which is described in the [Base Spec].  As such, a hash of the bound 
Migration TD’s TDREPORT_STRUCT is included in the migrated TD’s TDREPORT_STRUCT (as the SERVTD_HASH field).  The 20 
service TD protocol allows, at binding time, to select which field of the TDREPORT_STRUCT is included in the calculation 
of SERVTD_HASH.  
The static components of the Migration TD, i.e., code and data added and measured during its build, are measured by its 
MRT D.  This may include, for example, a baseline migration policy.  Migration TD writers are expected to measure the 
configurable part of the  migration policy and its parameters , i.e., any change that can be made after the Migration TD 25 
build was finalized,  using one or more of the RTMRs (run time measurement registers) provided by the TDX architecture 
via the TDG.MR.RTMR.EXTEND interface function.  Those RTMRs should be included in the SERVTD_HASH calculation.  
Thus, the migration policy is attested as part  of the Migration TD, and as such, as part of the migrated TD.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 23 of 71 
Section 2:  TD Migration Architecture Specification  4.3. Inputs to the Migration TD’s Migration Policy Evaluation  
The following data can be read and evaluated by the Migration TD, as part of its migration policy evaluation.   The 
migration TD may reflect such inputs an RTMR (using TDG.MR.RTMR.EXTEND) so that it becomes part of any migrated 
TD’s attestation.  
System -Scope Information Provided by TDG.SYS.RD*  5 
System -scope  (platform and TDX module) information can be read using TDG.SYS.RD or TDG.SYS.RDALL.  Examples of 
such information are:  
• TDX features supported on this platform ( e.g., TDX_FEATURES0 field)  
• Supported TD features ( e.g., ATTRIBUTES_FIXED0/1, XFAM_FIXED0/1, CPUID_CONFIG_VALUES and 
IA32_ARCH_CAPABILITIED_CONFIG_MASK fields)  10 
• TD Migration protocol features (e.g., MIN/MAX_EXPORT/IMPORT_VERSION fields)  
The complete list of fields enumerated by TDG.SYS.RD* is provided in the [ABI Spec].  
System -Scope Information Provided by TDG.MR.REPORT  
The Migration TD may call TDG.MR.REPORT to get the TDREPORT_STRUCT, which contains information about the 
platform (CPUSVN) and the TDX module (TEE_TCB_INFO).  15 
Migration Policy Configuration  
The Migration TD’s migration policy may be configured by, e.g., the host VMM . 
4.4. Migrated TD Information Provided by TDG. SERVD .RD 
A Migration TD may  read m igrated TD  information using TDG. SERVD .RD, in order to decide whether that TD can be 
migrated to a specific destination platform .  Note that similar checks are also done by the TDX module on import, so 20 
there’s no strict requirement for the Migration TD to do them.  
Examples of such information are:  
• ATTRIBUTES_FIXED0/1  
• XFAM_FIXED0/1  
• GPAW  25 
• CPUID_VALUES  
4.5. Migration Version Setup  
Before starting a migration session, the MigTDs on the source and destination should agree on migration protocol version 
that is supported by both sides.  To do so, each MigTD can read the following fields using TDG.SYS.RD:  
• MIN_EXPORT_VERSION  30 
• MAX_EXPORT_VERSION  
• MIN_IMPORT_VERSION  
• MAX_IMPORT_VERSION  
The MigTD on each side then should write the MIG_VERSION to the migrated  TD using TDG.SERVD.WR.  
4.6. Migration Keys Exchange  35 
1. The MigTD on each side reads  the migration encryption key (MIG_ENC_KEY), which is randomly generated by the 
TDX module, using TDG.SERVTD.RD.  
2. The MigTD on each side sends the key value over a secure channel to the peer MigTD on the other side.  
A MigTD must never send the same key value to more than one peer MigTD .  Failing to do so may expose TDX to 
an attack where the same TD is migrated to more than one destination.   The MigTD should always read a new 40 
MIG_ENC_KEY value using TDG.SERVTD.RD if it needs to resend it.  
3. The MigTD on each side writes the received key value as the migration decryption key (MIG_DEC_KEY), using 
TDG.SERVTD.WR.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 24 of 71 
Section 2:  TD Migration Architecture Specification  4.7. Example Migration Session Establishment  
The goal is to stablish secure transport channel between Intel TDX Module s and MigTD s on both sides  across compatible 
platforms and reserve resources for the migration session . 
Generate 
key-pair
Intel TDX Module VMMSEAMCALL
SEAMRETIntel TDX Module VMMSEAMCALL
SEAMRET
SOURCE PLATFORM DESTINATION PLATFORMGenerate 
key-pairMigTD
verify certificate chain 
for source platformMigTDRequest QE 
certification Quote 
verification 
libraryQuotingE
nclave
Sign alias 
certificate for 
MigTDQuoting
Enclave
Sign alias 
MigTDLibvirt
(untrusted 
host 
service)Libvirt
host 
service)Logical secure channel ( OpenEnclave/ TLS with TDX Quote Support ) –Transport key
1
42
Eval Mig pol and 
Generate Mig KeyEval Mig Pol and 
Unwrap Mig Key
Migration session KeyQuote 
library
for dest platform
3
Migration session KeyRequest QE 
certification
Program Mig Key Program Mig KeyData (Migration session Key)
0TDTD
 
Figure 4.2: MigTD Transport Security Setup  5 
1. On platform 1, TD -s to be migrated is created with MIGRATABLE attribute .  TD -s is built using the legacy process.  
2. On platform 1, MigTD -s is created and built.  
3. On platform 1, MigTD -s evaluates the platform and TDX module information using TDG.SYS.RD* and 
TDG.MR.REPORT  and reflects its updated migration policy in RTMR[3], using TDG.MR.RTMR.EXTEND.  
4. The host VMM on platform 1 instantiates binds MigTDs to TD -s via an unsolicited  service TD binding using 10 
TDH.SERVTD.BIND:  
4.1. MigTD -s requests the host VMM to be bound to TD -s, using TDG.VP.VMCALL.  
4.2. The VMM invokes TDH.SERVTD.BIND to bind TD0 to MigTD -s. 
4.3. The VMM communicates the binding handle, target TD_UUID and other binding parameters to MigTD -s. 
5. The host VMM on platform 1 finalized the build of TD -s using TDH.MR.FINALIZE.  15 
6. TD-s executes on platform 1.  
7. Similar to MigTD -s above, o n platform 2, MigTD -d is created and built.  It evaluates is platform and TDX module and 
reflects in updated migration policy in RTMR[3].  
8. The cloud orchestration triggers a migration of TD -s from platform 1 to platform 2.  
9. MigTD -s may read selected metadata of TD -s (e.g., its ATTRIBUTES and XFAM) using TDG.SERVTD.RD, to use as an 20 
input to the migration policy evaluation.  
10. The host VMM initiates the migration process for the TD -s: 
10.1. The VMM creates a network transport session (nonce) with the destination platform (destination of TD 
migration) and requests a quote from the MigTD -d on destination platform.

migration) and requests a quote from the MigTD -d on destination platform.  
10.2. The VMM notifies MigTD -s of a new session providing quote for MigTD -d (from destination platform); in 25 
response MigTD -s invokes TDG.MR.REPORT and requests a QUOTE from the host VMM (to be sent to source 
platform).  
10.3. MigTD -s verifies the MigTD -d quote using a Quote Verification Library in the MigTD -s and establishes via 
Diffie -Helman a transport key for the session with destination platform (and vice -versa).  
11. MigTD -s authenticates the Migration Policy and evaluates it per the capabilities (SVN etc.) of the destination 30 
platform  (learnt via the quote) for the specified live migration session . 
12. On platform 2 , a destination TD -d skeleton is created via legacy process.  
13. On platform 2, t he host VMM may bind s MigTD -d to TD -d using TDH.SERVTD.BIND.  
14. Migration Keys Exchange:  
14.1. MigTD -s reads the Migration Forward Key (as the migration encryption key) from TD -s using TDG.SERVTD.RD.  35 
14.2. MigTD -s sends the Migration Forward Key to MigTD -d. 
14.3. On the destination platform , MigTD -d writes the Migration Forward Key (as the migration decryption key) to 
TD-d using TDG.SERVTD.WR.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 25 of 71 
Section 2:  TD Migration Architecture Specification  14.4. MigTD -d reads the Migration Backward Key (as the migration encryption key) from TD -d using 
TDG.SERVTD.RD.  
14.5. MigTD -d sends the Migration Backward Key to MigTD -s. 
14.6. On the source platform , MigTD -s writes the Migration Back ward Key (as the migration decryption key) to TD-s 
using TDG.SERVTD.WR.  5 
15. The host VMM on the source platform can now initiate the state export via TDH.EXPORT* SEAMCALLs and import 
state via TDH.IMPORT* SEAMCALLs  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 26 of 71 
Section 2:  TD Migration Architecture Specification  5. TD Migration Common Mechanisms  
This chapter describes the infrastructure used by all Import/Export APIs to migrate TD private memory and metadata.  
5.1. Migration Bundles  
This section describes the generic migration bundle structure.  Private memory migration uses an enhanced format, 
described in 8.2.6 . 5 
5.1.1.  Overview  
TD information is transported from the source platform to the destination platform  in migration bundle s.  A migration 
bundle consists of migration data , which may span one or more 4KB pages or one 2MB page, and migration  bundle  
metadata ( MBMD ).  Migration bundle transport is the responsibility of untrusted software and is out of the scope of this 
specification.  10 
Target Platform Source Platform
Migration 
Bundle 
Metadata
(MBMD)
Migrated 
Data
Migration 
BundleTDH.EXPORT.*Migration 
Bundle 
Metadata
(MBMD)
Migrated 
Data
Migration 
BundleTDH.IMPORT.*Transport
 
Figure 5.1:  Migration Bundle  
5.1.2.  Migration Data  
Migration data contains either TD private memory contents or TD non -memory state.  It is confidentiality -protected using 
AES-GCM with the TD migration key and  a running migration session counter .  Migration data is integrity -protected by its 15 
associated MBMD.  For encryption details, see 5.3. 
Note:  Migration of shared memory pages is the responsibility of untrusted software and is out of the scope of this 
specification.  
In memory, migration data occupies one or more 4KB shared memory pages, or one 2MB shared memory page, managed 
be the host VMM.  20 
5.1.3.  Migration Bundle Metadata (MBMD)  
A migration bundle metadata (MBMD) structure provides metadata for an associated migration data.  In memory, MBMD 
resides in a shared page, managed by the host VMM, and must be naturally aligned.  An MBMD is not confidentiality 
protected, but it provides i ntegrity protection for itself and for its associated migration data.  
The MBMD structure consists of a fixed header and a per -type variable part.  The header contains the following fields:  25 
SIZE:  Overall size of the MBMD structure, in bytes  
MIG_ VERSION:  Migration protocol version  
MB_TYPE:  The type of information being migrated  
MB_COUNTER:  Per-stream migration bundle counter  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 27 of 71 
Section 2:  TD Migration Architecture Specification  MIG_EPOCH:  Migration epoch number  
MIGS_INDEX : Index of the migration stream  
IV_COUNTER:  Monotonously increasing counter, used as a component in the AES -GCM IV  
The last field of each MBMD is an AES-256-GCM MAC over other MBMD fields and other  associated migration data 
(migration pages) . 5 
The detailed MBMD definition is provided i n [TDX Module ABI Spec ]. 
5.2. Export and Import Functions Interface  
Export and import functions operate on a single migration bundle at a time, which belongs to a specific migration stream.  
5.2.1.  Overview of Migration Data Format in Memory  
While in memory, a migration bundle always contains a single MBMD .  Optional migration data can be stored in multiple 10 
4KB migration buffer pages.  
5.2.2.  Migrating a Multi -Page Migration Bundle  
To export a multi -page migration bundle, the host VMM on the source platform prepares a set of migration buffer pages 
and a buffer for an MBMD in shared memory.  The required number of migration pages per TDH. EXPORT .* function is 
enumerated by TDH.SYS.INFO .  The host VMM provides the MBMD’s HPA and a list of HPA pointers to the migration 15 
pages as an input to the TDH. EXPORT * function.  
To import a multi -page migration bundle, the host VMM on the destination platform  prepares the set of migration pages 
and the MBMD, as received from the source platform, in shared memory.  The host VMM provides the MBMD’s HPA and 
a list of HPA pointers to the migration pages as an input to the TDH. IMPORT * function.  
…PAGE_HPA0
PAGE_HPA1
PAGE_HPAlast
Page ListMigration 
Bundle 
Metadata
(MBMD)
4KB
Migration
Page4KB
Migration
Page4KB
Migration
Page
Multi -Page 
Migration 
BundleTDH.EXPORT.* TDH.IMPORT.*
PAGE_HPA1
Page ListTransport
Migrated DataMigration 
Bundle 
Metadata
(MBMD)
4KB
Migration
Page4KB
Migration
Page4KB
Migration
Page
Migration 
BundleMigrated Data
 20 
Figure 5.2:  Migrating a Multi -Page Migration Bundle  
5.2.3.  Migration Functions Interruptibility  
TDH.EXPORT .* and TD H.IMPORT .* functions may take relatively long time to execute.  This is especially true for 2MB 
page migration and multiple 4KB page migration.  To avoid latency issues, such functions may be interruptible  and 
restartable .  This is supported as follows:  25 
• TDH. EXPORT .* and TDH. IMPORT .* functions are designed to synchronously check for a pending external event by 
reading MSR_INTR_PENDING (once after every pre -determined number of cycles, chosen to be smaller than the 
maximum allowed cycle latency).  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 28 of 71 
Section 2:  TD Migration Architecture Specification  • If an external event is pending, the functions store their context in the proper MIGSC  and returns with a 
TDX_INTERRUPTED_RESUMABLE completion status.  
• The host VMM is expected to call the TDH. EXPORT .* or TDH. IMPORT .* function again with the same set of inputs 
until the operation is completed successfully (completion status is TDX_SUCCESS) or some error occurs (completion 
status indicates an error).  5 
• An input flag indicates whether the invocation of a TDH. EXPORT .* or TDH. IMPORT .* function starts a new operation 
(and possibly aborts an interrupted one) or resumes an interrupted operation.  
5.3. Cryptographic Protection for Migration Data  
5.3.1.  Encryption Algorithm  
TD migration uses AES in Galois/Counter Mode (GCM) to transfer state between the source and destination platform 10 
platforms.  Per [AES -256-GCM] definitions, the TD data private memory or non -memory state temporarily held in the 
CPU cache during TDH.EXPORT.* forms the “Plaintext”, and some of the MBMD fields form the “Additional Authenticated 
Data”.  The “Plaintext” is  encrypted using a Migration key (described below).  The MAC size, also known as t, as defined 
in [AES -256-GCM], must be 128 bits.  
The Initialization Vector (IV) is 96 bits.  It is composed as described below.  Since 64 bits will never wrap around in pract ice, 15 
this helps ensure  a unique counter for each stream.  
Table 5.1:  Components of the 96 -bits IV  
Bits Size  Name  Description  
63:0  64 IV_COUNTER  Starts from 1, incremented by 1 every time AES -GCM is used to 
encrypt data and/or generate a MAC for a migration bundle.  
The counter is incremented even if the data is discarded and not 
used for migration.  
79:64  16 MIGS_INDEX  Stream index (see 5.3) 
95:80 16 RESERVED  Set to 0  
 
5.3.2.  Migration Session Keys

5.3.2.  Migration Session Keys  
Two migration session keys are used, one in each direction:  20 
• The TDX module on the source platform generates a migration session forward key for encrypting migration bundles 
by the source TDX module and decrypting them by the destination TDX module.  
• The TDX module on the destination platform generates a migration session backward  key for encrypting migration 
bundles by the destination TDX module and decrypting them by the source TDX module.  
Each of the MigTDs on the source and the destination platforms reads the key generated on their side, known as the 25 
migration encryption key , from the TDX module’s target TD’s metadata, and transfer it on a secure like to its peer MigTD 
on the other side of the migration session.  The peer MigTD then writes the key, to be used as the migration decryption 
key, to the TDX module’s target TD’s metadata.  TD metadata read and write used the Service TD protocol, as described 
in the [ TDX Module Base Spec ]. TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 29 of 71 
Section 2:  TD Migration Architecture Specification  
Metadata
Metadata
Key
Source
Backward Migration Session Key
 
Figure 5.3:  Migration Session Keys Exchange  
The migration keys properties are as follows:  
• The key strength is 256 bits . 
• A new  encryption key is generated  by the TDX module on TD creation (TDH.MNG.CREATE) and at the beginning of 5 
each migration session  (TDH.*PORT.STATE.IMMUTABLE) . 
• The encryption key is read by the MigTD from the migrated TD’s metadata using the Service TD metadata protocol, 
as described in the [ TDX Module Base Spec ]. 
• The MigTD transfer the encryption key to its peer MigTD, over a secure channel both MigTDs have created.  
• The decryption key is written by the MigTD to the migrated TD’s metadata using the Service TD metadata protocol, 10 
• The key s are accessible only by the MigTD and the Intel TDX Module.  
• On migration session start by TDH.*PORT.STATE.IMMUTABLE, the Intel TDX module copies the encryption and 
decryption  keys into working key s that are used throughout the session.  
• The key s are used by TDH.EXPORT.* /TDH.IMPORT.*  to control the migration session and migrate TD memory and 15 
non-memory . The migration stream AES -GCM protocol requires that state is migrated in -order between the source 
and destination platform.  This helps guarantee the order within each migration stream.  
• The key s are destroyed  when a TD holding them  is torn down , or when new key s are generated or  programmed .  
5.4. Migration Streams  and Migration Queues  
Migration stream  is a TDX concept .  Multiple streams allow multi -threaded, concurrent export and import, and enable 20 
the Intel TDX Module to enforce proper ordering of migration bundles during the in-order  phase where this is essential . 
Migration queue  is a host VMM  concept .  Multiple queues  allow QoS and prioritization.  E.g., Post -copy of pages on 
demand (triggered by an EPT violation on the destination platform) may have a higher priority than other post -copy of 
pages.  To avoid head -of-line blocking by waiting in the same queue as lower p riority pages, a separate high priority queue  
can be used by the host VMM.  25 
From the migration streams and migration queues perspective, a migration session is divided into two main phases:  
• In-order , where the source TD may run, and its memory and non -memory state may change.  During the in -order 
phase , the order of memory migration is critical.  A newer export of the same memory page must be imported after 
an older export of the same page.  Furthermore, for any memory page that has been migrated during the in -order 
phase , the most up -to-date version of that page must be migrated before the in-order  phase ends.  In the in-order  30 
phase, one or more migration streams are mapped to  each  migration queue . 
• Out-of-order , where the source TD does not run, and its memory and non -memory state may not change.  During 
out-of-order , the order of memory migration is not important  – except that migration bundles exported during the TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 30 of 71 
Section 2:  TD Migration Architecture Specification  in-order phase can’t be imported during the out -of-order phase .  Furthermore, the host VMM may assign exported 
pages (even multiple copies of the same exported page) to different priority queue.  This is used, e.g., for on -demand 
migration after the destination TD starts running.  
The start tokens , generated by TDH.EXPORT. TRACK  and verified by TDH.IMPORT. TRACK , serve as markers to indicate the 
end of the in-order  phase and start of the out-of-order  phase.  They are used to implement a rendezvous point, enforcing 5 
all the in-order  state (across all streams) to have been imported before the out-of-order  phase starts and the destination 
TD may execute.  
5.3 describes how the stream context held by the source and the destination platforms and the MBMD fields included in 
each migration bundle are  used to construct the non -repeated AES-GCM IV.  Note also that the same stream queues can 
be used for both in-order  and out-of-order .  The semantic use of the queues is up to the host VMM.  10 
STREAM_INDEX 
(16 bits)AES_GCM_CONTER
(64 bits)AES-256-GCM Migration Session Forward Key
TDH.EXPORT.PAGE
@ LP1
Migration 
Bundle  3TDCS
Migration 
Bundle 0
Migration 
Bundle 2TDCSEncryption
Key
Migration 
Bundle  3Migration 
Bundle 0
Migration 
Bundle 2TDH.EXPORT.PAGE
@ LP2TDH.IMPORT.PAGE
@ LP1
TDH.IMPORT.PAGE
@ LP2Source
Platform
0
(16 bits)From MBMD
AES-256-GCM IV (96 bits)
MB 0
MB_COUNTER = 0MB 3 
MB_COUNTER = 1Forward Migration Stream 0 (Default)
MB 1
MB_COUNTER = 0MB 2 
MB_COUNTER = 1Forward Migration Stream 1Migration 
Bundle 1Migration 
Bundle 1Stream 
ContextStream 
Context
Backward Migration Stream 0 (Default)AES-256-GCM Migration Session Backward Key
Decryption
Key
MB 
MB_COUNTER = 0MB 
MB_COUNTER = 1TDH.IMPORT.ABORT TDH.EXPORT.ABORT
 
Figure 5.4:  Migration Streams  
Migration streams have the following characteristics:  
• Within each stream, state is migrated in -order.  This is enforced by the MB_COUNTER field of MBMD . 
• Export or import operations using a specific migration stream must be serialized.  Concurrency is supported only 15 
between streams.  
• The host VMM should use the same stream index  to import  memory on the destination TD (which should be in 
MEMORY_IMPORT, STATE_IMPORT or RUNNABLE state).   This is enforced by TDH.IMPORT.MEM . 
• Non -memory state can only be migrated once; there is no override of older migrated non -memory state with a newer 
one.  Ordering requirements (e.g., TD -scope non -memory state must be imported before VCPU non -memory state) 20 
are enforced by the lifecycle state machine, as described in 6.2. 
• The maximum number of forward streams is implementation dependent : 
o Each stream  requires context space allocation . 
o Stream ID  requires a field in the MBMD header.  
The maximum number of forward streams is enumerated by TDH.SYS. RD*. 25 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 31 of 71 
Section 2:  TD Migration Architecture Specification  • There is one backward stream.  
5.5. Measurement and Attestation  
5.5.1.  TD Measurement Registers Migration  
TDs have two types of measurement registers:  
MRTD:  Static measurement of the TD build process and the initial contents of the TD.  This state is migrated as part of 5 
the global immutable state of the TD (via TDH.EXPORT.STATE.IMMUTABLE and 
TDH.IMPORT.STATE.IMMUTABLE).  
RTMR:  An array of general -purpose measurement registers, available to the TD software for measuring additional logic 
and data loaded into the TD at runtime.  Since this measurement covers dynamic state beyond the static state 
and can be extended by TD software via TDG.MR.RTMR.EXTEND, hence, this state is migrated only during the 10 
blackout period, as part of the TD’s mutable state (via TDH.EXPORT.STATE.TD and TDH.IMPORT.STATE.TD).  
All TD measurements are reflected in TD attestations.  
5.5.2.  TD Measurement Reporting  Changes  
The TDINFO structure is enhanced to include hashes of Service TDs’ TDINFO; for TD migration, the applicable Service TD 
is the Migration TD.  Refer to the [TDX Module Base Spec ] for a discussion of Service TDs.  15 
5.5.3.  TD Measurement Quoting  Changes  
To create a remotely verifiable attestation, the TDREPORT_STRUCT  must be converted into a Quote signed by a certified

To create a remotely verifiable attestation, the TDREPORT_STRUCT  must be converted into a Quote signed by a certified 
Quote signing key , as described in the [ TDX Module Base Spec ]. 
TDREPORT_STRUCT is HMAC’ed using an HMAC key unique to each platform and accessible only to the CPU.  This protects 
the integrity of the structure and can only be verified on the local platform  via the SGX ENCLU(EVERIFYREPORT2) 20 
instruction.  TDREPORT_STRUCT cannot be sent off platforms for verification; it first must be converted into signed 
Quotes.  
If a report is generated by TDG.MR.REPORT on the source platform, but the is migrated to a destination platform, the 
local HMAC key is different and hence the EVERIFYREPORT2 on the migrated TDG.MR.REPORT is expected to fail.  The TD 
software is typically unaware of being migrated.  It is expected to retry the TDG.MR.REPORT operation  if it fails . 25 
5.5.4.  TCB Recovery  and Migration  
The TDX architecture has several levels of TCB:  
• CPU HW level, which includes microcode patch, ACMs, and PFAT  
• Intel TDX Module  
• Attestation Enclaves, which include the TD Quoting Enclave and Provisioning Certification Enclave  30 
The TCB Recovery story is different for each level.  The existing TCB Recovery model for CPU SW level items applies 
similarly to TDX and SGX and requires a restart of the platform to take effect.   The Intel TDX Module can be unloaded 
and reloaded to refle ct an upgraded Intel TDX Module.  The enclaves can be upgraded at runtime, but if the PCE is 
upgraded, a new certificate must be downloaded . 
5.6. TDX Control Structure Updates  35 
This section discusses updates and additions to the global and TD -scope control structures.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 32 of 71 
TDCSTDCSTDXTDCX PageShared:
VMM -Managed, Shared HKIDOpaque (TD Private HKID):
VMM Allocated, Intel TDX Module Managed
TDR PageOpaque (Intel TDX Module
Global Private HKID):
VMM Allocated,
Intel TDX Module Managed
Secure EPT TreeSEPT_PAGESEPT_PAGESEPT Page
Migration Stream ContextSEPT_PAGESEPT_PAGEMIGSC 
Figure 5.5:  TD-Scope Control Structures Overview  
5.6.1.  Per-TD:  TDCS  
As described in 6.2, TD migration happens when both the source and destination TDs have their ephemeral encryption 
keys assigned and configured, and the TDCS pages have been allocated.  Thus, all migration -related metadata is stored in 5 
TDCS.  There is no change to TDR.  TDCS details are described in the [TDX Module ABI Spec ]. 
 Updates to Existing TDCS Fields  
TDCS is updated with the following migration -related fields:  
• The ATTRIBUTES field has a new MIGRATABLE bit.  
• TD state variables are enhanced to support the updated TD Operation State Machine and the new TD Migration State 10 
Machine, described in 6.2. 
• Service TD context array supports, among other, the Migration TD.  Service TDs are described in the [ TDX Module 
Base Spec ]. 
 TDCS Migration -Related Fields  
The following TDCS fields hold per -TD migration context.  The detailed specification is provided in the [TDX Module ABI 15 
Spec ]. 
Table 5.2:  TDCS Migration Context High Level Definition  
Field  Description  
MIG_KEY_SET  Set when a new MIG_KEY is written, cleared when the MIG_KEY is copied to 
MIG_WORKING_KEY  
EXPORT_COUNT  Counts the number of times this TD has been exported, included aborted export 
sessions.  
Incremented at the beginning of each export session 
(TDH.EPORT.STATE.IMMUTABLE).  
IMPORT_COUNT  Counts the number of times this TD has been imported.  
Incremented by TDH.IMPORT.COMMIT.  
MIG_EPOCH  Migration epoch  
Starts from 0 on migration session start, incremented by 1 on each epoch token.  
A value of 0xFFFFFFFF indicates out -of-order phase.  
BW_EPOCH  Blocking -for-write epoch  
Holds the value of TD_EPOCH at last time TDH.EXPORT.BLOCKW blocked a page 
for writing.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 33 of 71 
Section 2:  TD Migration Architecture Specification  Field  Description  
TOTAL_MB_COUNT  The total number of migration bundles exported or imported during the current 
migration sessions  
MIG_KEY  Migration key, as written by the Migration TD  
MIG_WORKING_KEY  Migration working key, copied from MIG_KEY at the beginning of a migration 
session and used throughout the session  
MIG_VERSION  Migration protocol version, as written by the migration TD  
MIG_WORKING_VERSION  Migration working protocol version, copied from MIG_VERSION at the beginning 
of a migration session and used throughout the session  
DIRTY_COUNT  Counts of the number of pages that must be re -exported, because their contents 
have been modified since they have been exported, before a start token may be 
generated  
MIG_COUNT  Counts the number of SEPT entries that need to be cleaned up after an aborted 
migration  
NUM_MIGS  Number of Migration Stream Context (MIGSC) pages that have been allocated  
MIGSC_LINKS  An array of links to MIGSC pages.  Each entry contains the following information:  
MIGSC_HPA : Physical address of the MIGSC page (without the HKID bits)  
INITIALIZED : A boolean flag, indicating that the migration stream has been 
initialized.  
 
5.6.2.  Secure EPT  
Secure EPT entry structure is updated as follows:  
• Multiple TDX -specific state bits, to support the many new states required for TD private memory migration (see 
Chapter 8). 5 
• Host -side entry lock bit, to support concurrent migration operations on separate Secure EPT entries without 
exclusively locking the whole Secure EPT tree.  
Secure EPT entry details are provided in the [TDX Module ABI Spec ]. 
5.6.3.  MIGSC:  Migration Stream Context  
Migration streams are defined in 5.3. 10 
MIGSC (Migration Stream Context) is an opaque control structure that holds migration stream context.  MIGSC occupies 
a single 4KB physical page, and is created using the TDH.MIG.STREAM.CREATE function.  MIGSC can only be created if a 
migration session is n ot in progress.  
Most of the migration stream context is initialized at the beginning of a new migration session by 
TDH.EXPORT.STATE.IMMUTABLE or TDH.IMPORT.STATE.IMMUTABLE.  15 
Table 5.3:  Migration Stream Context High Level Definition  
Field  Description  Initial 
Value  
IV_COUNTER  Monotonously incrementing 64b counter, used as a component in the AES -
GCM IV  
IV_COUNTER is incremented near the beginning of any TDX module 
function that creates a migration bundle, before it is used for composing an 
IV.  This is done to avoid reusing the IV value in case of a failure.  0 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 34 of 71 
Section 2:  TD Migration Architecture Specification  Field  Description  Initial 
Value  
NEXT_ MB_COUNTER  Transmitted migration bundle counter (64b)  
On export, incremented by 1 after every successful MBMD generation.  
After transitioning to the out -of-order phase by TDH.EXPORT.TRACK, bit 63 
is set to 1.  0 
EXPECTED_ MB_COUNTER  Expected received migration bundle counter (64b)  
Applicable only on the import side, during the in -order phase before a start 
token has been received on this stream.  A received MBMD’s  
MB_COUNTER must be equal or higher than EXPECTED_MB_COUNTER.  
During the out -of-order phase, the imported MBMD’s MB_COUNTER is not 
compared to EXPECTED_MB_COUNTER.  Instead, its bit 63 is checked to be 
1. 0 
AES_GCM_CONTEXT  Implementation -dependent AES -GCM context  
 N/A 
INTERRUPTED_STATE  The state of interrupted TDH.EXPORT.* or TDH.IMPORT.* interface 
function.  Includes the following:  
• Valid flag  
• Interrupted function’s leaf number  
• Interrupted function’s input operands  
• Interrupted function’s MBMD  
• Other state the needs to be saved across interruptions and 
resumptions.  N/A 
November 2023   . Page 35 of 71 
Section 2:  TD Migration Architecture Specification  6. Migration Session Control and State Machines  
This chapter discusses the TD migration session control, state machine and messaging protocol.  
6.1. Overview  
6.1.1.  Pre-Migration  
Prior to starting a migration session, the following should have happened:  5 
• The TD has been created as a skeleton (control structure pages only) on the destination platform.  
• Migration TDs should be bound as service TDs on both source and destination platforms.  
• Migration TDs must have exchanged the migration session keys and decided on migration version.  
TD Build
RUNNABLE
STATE.
IMMUTABLE
STATE.
WR(dec key
TDH.MNG.

TD Build
RUNNABLE
STATE.
IMMUTABLE
STATE.
WR(dec key
TDH.MNG.
FINALIZE
 
Figure 6.1:  Pre -Migration  10 
6.1.2.  Successful Migration Session  
Figure 6.3 below  shows an overview of a successful migration session .  This figure shows the following:  
• Migration the session control TDX Module interface functions  (TDH.EXPORT.PAUSE, TDX.EXPORT. TRACK  etc.)  
• States of the TD Operation State Machine (RUNNABLE, LIVE_EXPORT etc.) are also shown.  The state machine itself 
is discussed in 6.2.2 below . 15 
• Phases of the export and import sessions  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 36 of 71 
RUNNABLE
STATE.
STATE.
MEM
MEM
STATE.VP  
Figure 6.2:  Migration Session In -Order Phase (Success Case)  
On the source platform, an export session’s in -order export phase starts with the host VMM invoking the 
TDH.EXPORT.STATE.IMMUTABLE function.  This function creates a migration bundle that is transmitted by the host VMM 
to the destination platform, where TD H.IMPORT.STATE.IMMUTABLE is invoked to start the import session’s in -order 5 
import phase.  
TDH.EXPORT.PAUSE pauses the TD on the source platform and starts the TDX -imposed blackout period.  
TDH.EXPORT. TRACK , when invoked on the source platform, verifies proper in-order export .  TD state must have been 
exported, and if any TD private page has been exported, the latest version of that page must have been exported.  
TDH.EXPORT. TRACK (done)  ends that phase and creates a start token  migration bundle  that is transmitted by the host 10 
VMM to the destination platform, where TDH.IMPORT. TRACK (done)  is invoked to end the in -order import phase.  See 
also the discussion of migration epochs in 6.1.4 below . 
MEM
MEM
MEM
MEM
END
 
Figure 6.3:  Migration Session Out -Of-Order Phase (Success Case)  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 37 of 71 
Section 2:  TD Migration Architecture Specification  TDH.IMPORT.COMMIT, invoked on the destination platform, commits the migration session and enables the TD to run 
on it , while memory import may continue .  This also helps ensure  that the TD will not run on the source platform, since 
an abort token will not be generated.  
Optionally, TDH.IMPORT.END, invoked on the destination platform, commits the migration session and enables the TD 
to run on it if not already done by TDH.IMPORT.COMMIT.  TDH.IMPORT.END ends the migration session; memory import 5 
is no longer allowed.  
6.1.3.  Aborted Migration Session  
 Abort during the In -Order Phase  
Figure 6.4 below  shows a case where a migration session is aborted during the in -order migration phase.  
TDH.EXPORT.ABORT, invoked by the host VMM, terminates the export session and enables the TD to resume running  on 10 
the source platform.  By design, t he TD should not be able  to run on the destination platform – it is up to the host VMM 
to free up any resource allocated there.  
TD May Not Run on 
Destination PlatformTD May Run
on Source Platform
RUNNABLETDX-Imposed Blackout
STATE_IMPORTMigration Session Abort (1/2):  Abort During In -Order Memory Migration
6TD May Run
PAUSESource DestinationTDH.EXPORT.
MEM
MEM
ABORT
 
Figure 6.4:  Migration Session Control Overview (Abort During the In -Order Phase)  
 Abort during the Out -Of-Order Phase  15 
Figure 6.5 below  shows a case where a migration session is aborted during the out -of-order migration phase.   
TDH.IMPORT.ABORT is invoked by the host VMM on the destination platform.  This function terminates the import 
session and puts the TD in a state where , by design,  it should not be able to run – it is up to the host VMM to free up any 
resource allocated there.  TDH.IMPORT.ABORT also creates an abort token, which is transmitted by the host VMM back 
to the source platform.  20 
On the source platform, the host VMM invokes TDH.EXPORT.ABORT, which checks the validity of the abort token and 
enables the TD to resume running.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 38 of 71 
TD May Not Run on Destination PlatformTD May Run on Source Platform TDX-Imposed Blackout
FAILED_IMPORT POST_IMPORT STATE_IMPORTMigration Session Abort (2/2):  Abort During Out -of-Order Memory Migration
7PAUSED_EXPORTIn-Order Memory Export Phase
MEM
MEM
ABORTTDH.EXPORT.
ABORT
Abort
TokenRUNNABLE
 
Figure 6.5:  Migration Session Control Overview (Abort During the Out -Of-Order Phase)  
6.1.4.  Migration Epochs  
To help maintain proper ordering of migrated page versions, the in -order migration phase is divided to multiple migration 
epochs.  A specific page can only be migrated once per migration epoch.  This is detailed in 8.5.1.3 .  TDH.EXPORT.TRACK 5 
starts a new export epoch and creates an epoch  token  migration bundle  that is transmitted by the host VMM to the 
destination platform, where TDH.IMPORT.TRACK is invoked to a new import epoch.  The last invocations of 
TDX.EXPORT.TRACK and TDX.IMPORT.TRACK, with a parameter indicating that the in -order phase is done, start the  out-
of-order export and import phases respectively.  
Stream
1
Stream
2
Stream
3Stream
0Page
0Page
11Page
5Page
15
Page
3Page
8Page
12Page
4
Page
13Page
1Page
6Page
14
Page
2Page
7Page
10Page
9Page
6Page
12
Page
11
Page
4
Page
8Cancel
7Page
7
Page
6Cancel
8
Page
14Page
12
Page
1Page
8Page
24Page
28Page
20
Page
23Page
16Page
21Page
29
Page
18Page
17Page
26Page
19
Page
17Page
27Page
22Page
29Mig. Epoch 0 Mig. Epoch 1 Mig. Epoch 2In-Order Phase Out-Of-Order PhaseLive Migration (TD is Running on Source)Post -Copy (TD 
is Running on 
Destination)Blackout (TD is 
not Running)
Epoch
TokenEpoch
TokenStart
TokenTime
 10 
Figure 6.6:  Migration Epochs Overview  
November 2023   . Page 39 of 71 
Section 2:  TD Migration Architecture Specification  6.2. TD Migration State Machines  
6.2.1.  Overview  
The whole TD migration process happens within the TD_KEYS_CONFIGURED state of the TD life cycle state machine, 
where an HKID has been assigned to the TD and the keys have been configured on the hardware.  As a reminder, the TD 
life cycle state diagram is s hown in Figure 6.7 below .  For details, see the [ TDX Module Base Spec ]. 5 
TDH.MNG.CREATE
TD_HKID_ASSIGNED
TD private key not 
configured TDH.MNG.KEY.CONFIG
[last package]TDH.MNG.
KEY.CONFIG
[non -last
package]
TDH.PHYMEM.PAGE.RECLAIM[TDR]TDH.MNG.VPFLUSHDONE
[no associated VCPUs]
TD_TEARDOWN
TD has no HKID
TDH.MNG.KEY.FREEIDTDH.PHYMEM.
PAGE.RECLAIM
[non -TDR]TD_BLOCKED
TD private memory 
access is blocked 
and caches are 
getting flushedTDH.MNG.KEY.FREEIDTD_KEYS_CONFIGURED
TD private key is configured
TD Operation
Sub-State
 
Figure 6.7:  TD Life Cycle State Diagram  
Within the TD_KEYS_CONFIGURED state, a secondary -level TD Operation state machine  control s the overall TD 
operation , including migration . 
6.2.2.  OP_STATE:  TD Operation State Machine  10

[non -last
package]
Sub-State
 
6.2.2.  OP_STATE:  TD Operation State Machine  10 
The TD Operation state machine is shown in Figure 6.8 below .  Th e baseline  state machine is extended with new 
migration -related states and transitions, highlighted in red text and lines.  The export states are highlighted in purple and 
the import states are highlighted in blue.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 40 of 71 
UNALLOCATED
TDCS memory 
allocation
TDH.MNG.ADDCX
[non -last page]INITIALIZED
TD memory 
allocation and 
measurement, 
VCPU creationTDH.MNG.INITTDH.VP.CREATE,
TDH.VP.ADDCX,
TDH.VP.INIT
TDH.MEM.*,
TDH.MR.EXTEND
TDH.MR.FINALIZE
MEMORY_IMPORT
TD memory import
STATE_IMPORT
TD memory and 
non-memory state 
importTDH.IMPORT.
STATE.IMMUTABLE
TDH.IMPORT.STATE.TD
TDH.IMPORT.TRACK
[in-order done &&
all non -memory state imported]PAUSED_EXPORT
TD memory export, 
export
TD memory post -
copy exportTDH.EXPORT.ABORT
[good abort token]TDH.EXPORT.
TRACK
[in-order done]TDH.EXPORT.PAUSE
TDH.EXPORT.MEMTDH.EXPORT.MEM,
STATE.TD/VPTDH.IMPORT.STATE.VP,
TDH.IMPORT.MEMTDH.IMPORT.MEM
TDH.IMPORT.ABORT /
Generate abort tokenTDH.EXPORT.
ABORT
FAILED_IMPORT
Destination TD can 
only be destroyedTDH.MNG.KEY.CONFIG
[last package]
UNINITIALIZED
TDCS memory has 
been allocated TDH.MNG.ADDCX
[last page]TDH.SERVTD.BIND
(MigTD)TDH.SERVTD.BIND
(MigTD)
TRACK
[in-order
not done]
TRACK
[in-order
not done]
POST_IMPORT
Post -copy TD 
memory import
COMMIT
MEMTDH.MEM.*
RUNNABLE
TD is runnableLIVE_EXPORT
TD is runnable , live 
memory export can 
be done
LIVE_IMPORT
TD is runnable , 
post -copy memory 
import can be doneTDH.MEM.*
Generate abort token
TDH.IMPORT.*
[import failed]TDH.EXPORT.
STATE.
IMMUTABLE
TDH.MEM.*TDH.EXPORT.
STATE.
IMMUTABLE
ABORT
TDH.IMPORT.MEM
[import failed]TDH.IMPORT.
END TDH.IMPORT.ENDTDH.EXPORT.
TRACK
[in-order
not done]TDH.IMPORT.
TRACK
[in-order
not done]TDH.EXPORT.MEM
 
Figure 6.8:  TD Operation State Machine (Sub -States of TD_KEYS_CONFIGURED)  
6.2.3.  Migration TD Binding and Migration Key Assignment  
Migration TD binding (using TDH.SERVTD.BIND) must happen before a migration session can start.  This may happen 
during TD build, before the measurement has been finalized (by TDH.MR.FINALIZE) .  Alternatively, pre -binding (using 5 
TDH.SERVTD.PREBIND) can be done during TD build, and actual binding can happen later.  On the destination platform 
migration TD binding and TD import must happen before the TD is initialized (by TDH.MNG.INIT).  
Migration key assignment, done by TD G.SERVTD. WR, may happen at any time after migration TD binding , except during 
the PAUSED_EXPORT and POST_EXPORT states .  A new migration key must be written for any migration session.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 41 of 71 
Section 2:  TD Migration Architecture Specification  6.2.4.  Export Side (Source Platform)  
To begin an export session, the TD’s OP_STATE must either be RUNNABLE, indicating that its measurement has been 
finalized (by TDH.MR.FINALIZE), or LIVE_IMPORT, indicating that this TD has been previously imported.  
An export session begins with immutable TD state export (using TDH.EXPORT.STATE.IMMUTABLE).  This function copies 
the migration key to a working migration key.  It then starts the in-order export phase .  It transitions the OP_STATE to 5 
LIVE_EXPORT , allowing the source TD to continue running  normally  while private memory is being exported.  
TDH.EXPORT.PAUSE transitions the source TD ’s OP_STATE  into the PAUSED_EXPORT state.  In this state, TD private 
memory and TD state modification are prevented.  None of the TD VCPUs may be running (i.e., in TDX non -root mode), 
and no host -side (SEAMCALL) function is allowed to change any TD non -memory state that is to be exported.  Memory 
export (via TDH.EXPORT.MEM  etc.) may still continue.  Per -TD and per -VCPU mutable control state are exported using 10 
TDH.EXPORT.STATE.TD and TDH.EXPORT.STATE.VP respectively.  
At any time, the export may be aborted by the host VMM using TDH.EXPORT.ABORT, which returns the source TD to the 
RUNNABLE state, where it can continue to run normally.  No abort token is required at this phase since no start token 
has been generated and t he destination TD , by design, should not be able  to run.  
Note:  TDH.EXPORT.STATE.TD is expected to be called by the exporting host VMM prior to TDH.EXPORT.STATE.VP, but 15 
this is only enforced on the import side.  
TDH.EXPORT. TRACK (done)  generates a start token  which the host VMM transmits to the destination VMM.  It transitions 
the source TD OP_STATE  into the POST_EXPORT state, starting the out-of-order export phase .  M emory export 
(TDH.EXPORT.MEM ) may continue, to support the out-of-order  stage of the TD live migration.  
In the  TD Migration Session POST_EXPORT state, a TDH.EXPORT.ABORT with a valid abort token , received from the 20 
destination VMM, indicates that the TD , by design, should not be able to run on the destination platform.  It terminates 
the export session and returns the source TD to the RUNNABLE state, where it can continue to run normally.  
The host VMM can start tearing down the source TD at any time, by ensuring that no VCPU is associated with an LP (i.e., 
by executing TDH.VP.FLUSH for all VCPUs) and issuing TDH.MNG.VPFLUSHDONE.  Typically, it will do so in the after it gets 
a notification from the destination platform that import has been successful.  25 
6.2.5.  Import Side (Destination Platform)  
Migration TD binding (using TDH.SERVTD.BIND) and migration key assignment (using TD G.SERVTD. WR) must happen in 
the UNINITIALIZED  state, where TDCS memory has already been allocated but the destination TD has not been initialized 
yet.  This is required since the destination TD is going to be initialized by importing immutable state from the source TD.  
TDH.IMPORT.STATE.IMMUTABLE starts the in-order import phase .  It initializes the destination TD’s TDCS with imported 30 
immutable state and transitions the destination TD ’s OP_STATE  into MEMORY_IMPORT.  In this state, TD private memory 
can be imported using TDH.IMPORT.MEM  etc. 
TDH.IMPORT.STATE.TD imports the per -TD mutable state and transitions the destination TD ’s OP_STATE into  
STATE_IMPORT.  In this state, mutable VCPU state can be imported using TDH.IMPORT.STATE.VP.  TD private memory 
import also continues.  35 
Upon executing TDH.IMPORT. TRACK  with a valid start token  as operand, the destination TD’s OP_STATE  transitions into 
the POST_IMPORT  state , starting the out-of-order import phase .  Memory import (a.k.a. post -copy ) may continue, but 
pages can only be imported if their GPA is free (i.e., the Secure EPT state is FREE).  
An import failure up to this point, e.g., improper sequence of page import vs. alias import, or executing 
TDH.IMPORT. TRACK  with a bad start token received from the source platform, transitions the TD’s OP_STATE to the 40 
FAILED_IMPORT state.  In addition, the host VMM can explicitly abort the import by using TDH.IMPORT.ABORT.  In the 
FAILED_IMPORT state, the TD is designed  not to run; it can only be torn down.  TDH.IMPORT.ABORT generates an abort 
token , which can be transmitted to the source platform.  
TDH.IMPORT.COMMIT transitions the destination TD’s OP_STATE transitions into the LIVE_IMPORT state.  In this state, 
the destination TD may run normally.  Out-of-order  memory import may continue  as long as the destination TD is in the 45 
LIVE_IMPORT state.  An input failure in the LIVE_IMPORT  terminates the import session; it transitions the TD’s OP_STATE 
to the RUNNABLE state, where the TD can continue running normally.  Abort token can no longer be generated.  
TDH.IMPORT.END ends the import session and transitions the destination TD’s OP_STATE into the RUNNABLE state.  This 
transition is optional if TDH.IMPORT.COMMIT has already been executed; it removes any limitations on TD memory 
management that exist during the out -of-order import phase.  50 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 42 of 71 
Section 2:  TD Migration Architecture Specification  A new export session (TDH.EXPORT.STATE.IMMUTABLE) terminates a previous out-of-order import . 
6.2.6.  OP_STATE Concurrency Considerations  
 Export Side  
The following export functions typically result in an OP_STATE transition.  They need to run while the source TD may be 
running, therefore t hey acquire a shared  lock on the source  TD (via its TDR page) .  To avoid concurrent execution with 5 
other export functions that may result in a n OP_STATE transition, they acquire an exclusive  lock on OP_STATE itself  and 
must be serialized by the host VMM:  
• TDH.EXPORT.STATE.IMMUTABLE  
• TDH.EXPORT.ABORT

• TDH.EXPORT.ABORT  
The following export  functions typically result in an OP_STATE transition.  The source TD does not run when the execute.  10 
They acquire an exclusive  lock on the source  TD (via its TDR page) .  This implicitly locks OP_STATE itself.  These interface 
functions  must be serialized by the host VMM:  
• TDH.EXPORT.PAUSE  
• TDH.EXPORT. TRACK  
The following export functions do not result in an OP_STATE transition , but they depend on OP_STATE not changing 15 
during their execution.   They acquire a shared  lock on the source TD (via its TDR page)  and a shared  lock on OP_STATE 
itself.  
• TDH.EXPORT.BLOCKW  
• TDH.EXPORT.UNBLOCKW  
• TDH.EXPORT.MEM  20 
• TDH.EXPORT.STATE.TD  
• TDH.EXPORT.STATE.VP  
• TDH.MIG.STREAM.CREATE  
 Import Side  
The following import functions typically result in an OP_STATE transition.  They acquire an exclusive  lock on the 25 
destination TD (via its TDR page) and must be serialized by the host VMM:  
• TDH.IMPORT.STATE.IMMUTABLE  
• TDH.IMPORT.STATE.TD  
• TDH.IMPORT. TRACK  
• TDH.IMPORT.COMMIT  30 
• TDH.IMPORT.END  
• TDH.IMPORT.ABORT  
The following import functions do not typically result in an OP_STATE transition , but they may depend on OP_STATE not 
changing during their execution.   To maximize import performance, they are designed to be executed concurrently on 
multiple LPs.  The se interface function acquire a shared  lock on the destination TD (via its TDR page):  35 
• TDH.IMPORT.MEM  
• TDH.IMPORT.STATE.VP  
However, all TDH.IMPORT.* functions may result in a transition to the FAILED_IMPORT state.  For example, a 
TDH.IMPORT.MEM  on one LP might transition to FAILED_IMPORT, while a concurrent TDH.IMPORT.MEM  on another LP 
might still be in progress.   The architecture is designed to harmlessly support this case; the FAILED_IMPORT state has no 40 
direct output transition – the destination TD can only be torn down, star ting with TDH.MNG.VPFLUSHDONE which 
acquires an exclusive lock on the TD (via its TDR) and thus helps ensure  that any TDH.IMPORT.* are not in progress.  
Similarly, TDH.IMPORT.MEM  may result in a transition to the RUNNING state, in case of an import error.  The architecture 
is designed to harmlessly support this case; transitions out of the RUNNING state either acquire an exclusive lock on the 
OP_STATE or acquire an exclusive lock on the TD (via its TDR).  45 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 43 of 71 
Section 2:  TD Migration Architecture Specification  6.2.7.  Summary  
Table 6.1:  OP_STATE  Sub-States of TD_KEYS_CONFIGURED  
Sub-State  Source /  
Destination  Description  
UNALLOCATED  Both  TDCS memory is being allocated.  
UNINITIALIZED  Both  • TDCS is pending initialization.  
• On the destination platform, migration TD binding and migration 
key assignment must happen in this state.  
INIT IALIZED  Source  • TD is being built.  Memory is added and measured.  VCPUs are 
created.  
• Migration TD binding may happen in this state.  
RUNNABLE  Both  • TD can run.  
LIVE_EXPORT  Both  • TD can run.  
• Immutable non -memory state (TDH.EXPORT.STATE.IMMUTABLE) 
has been exported.  
• Live memory can be exported ( TDH.EXPORT.MEM  etc.).  
PAUSED_EXPORT  Source  • No TD VCPU may run.  
• TD memory can’t be written.  
• Memory can be export ed. 
• Mutable non -memory state is being exported.  
POST_EXPORT  Source  • Start token has been generated on all streams that were active.  
• Mutable control state has been exported.  
• No TD VCPU may run.  
• Memory can be export ed (post -copy).  
MEMORY_IMPORT  Destination  • TD memory can be imported.  
STATE_IMPORT  Destination  • TD memory can be imported.  
• TD VCPU non -memory state can be imported  
POST_IMPORT  Destination  • TD memory can be imported (post -copy).  
LIVE_IMPORT  Destination  • TD VCPUs may run.  
• TD memory can be imported (post -copy).  
FAILED_IMPORT  Destination  • Destination TD will not run.  
 
6.3. Migration Tokens  
A migration token is formatted as a Migration Bundle , with only an MBMD.  Its format is defined in  the [TDX Module ABI 5 
Spec ]. TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 44 of 71 
STATE.DONETDH.IMPORT.
STATE.DONETransport
Migration 
Bundle 
Metadata
(MBMD)
Abort TokenMigration 
Bundle 
Metadata
(MBMD)
Abort TokenTDH.EXPORT.
ABORTTransport
If FailedTDH.IMPORT.
ABORTMigration 
Bundle 
Metadata
(MBMD)
Epoch TokenMigration 
Bundle 
Metadata
(MBMD)Migration 
Bundle 
Metadata
Bundle 
Metadata
(MBMD)
Bundle 
Metadata
Bundle 
Metadata
(MBMD)TDH.EXPORT.
STATE.DONETDH.EXPORT.
TRACKTDH.IMPORT.
TRACK 
Figure 6.9:  Migration Tokens  
An epoch token  is generated by TDH.EXPORT.TRACK.  it serves as a separator between migration epochs.  A  start token  
is a special version of an epoch token which starts the out -of-order phase.  The start token helps ensure  that no newer 
version of any memory page exported prior to the start token exists on the source platform.  5 
The abort token  is generated by TDH.IMPORT.ABORT on the destination platform if import fails for any reason.  It helps 
ensure  that the TD will not run on the destination platform, and therefore may be restored on the source platform.  
6.4. Migration Protocol Versioning  
6.4.1.  Introduction  
Migration protocol version number is provided as part of the MBMD header.   Migration protocol changes may require 10 
migration version increment  and may impact source and destination compatibility .  For example , this may happen due 
to: 
• Incompatible MBMD format changes  
• New values of MBMD fields  
• New memory migration variants (e.g., support of aliases for VM nesting)  15 
• Incompatible migration session state machine changes  
Non -memory state (metadata) migration changes may also require migration version increment.  For example , this may 
happen due to :  
• New exported metadata fields  
• New values or format of exported metadata fields  20 
6.4.2.  Enumeration of Supported Migration Versions  
TDX module enumeration version support using global metadata fields that can be read by the host VMM (TDH.SYS.RD) 
and MigTD (TDG. SYS.RD).  
On export, the TDX module can work with MIG_VERSION in the range specified by the following  metadata fields : 
MAX_EXPORT_VERSION:  Maximum value of migration version supported for export  25 
MIN_EXPORT_VERSION:  Minimum value of migration version supported for export  
For example, a module may be updated to support version X for new memory migration formats for VM Nesting.  But it 
may be written to export using version X -1 if a non -VM-Nesting TD is exported to an older module.  
On import, the TDX module understands MIG_VERSION in the range specified by the following:  
MAX_IMPORT_VERSION:  Maximum value of migration version supported for export  30 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 45 of 71 
Section 2:  TD Migration Architecture Specification  MIN_IMPORT_VERSION:  Minimum value of migration version supported for import  
For example, if the module supports version X that was created to support new memory migration formats for VM 
Nesting, it can still understand version X -1 that doesn’t use the new formats.  
6.4.3.  Setting the Migration Protocol Version for a Migration Session  
Migration protocol version to be used for a migration session is set the MigTD  before the session starts.  MigTD s at the 5 
source and destination platform enumerate export and import versions support respectively, and decide on the version  
that is compatible between the platforms, to be used for the migration session.  TD-scope metadata field MIG_VERSION 
is writable by the MigTD using TDH.SERVTD.WR .  At the start of the migration session, the TDX module c opie s 
MIG_VERSION to an internal  WORKING_MIG_VERSION that is used throughout the session . 
6.5. Export Session Control Functions  10 
This section provides an overview of the export session control functions.  A detailed description is provided in [TDX 
Module ABI Spec ]. 
6.5.1.  TDH.EXPORT.STATE.IMMUTABLE  (Session Control Aspects)  
TDH.EXPORT.STATE.IMMUTABLE starts an export session.  It also exports the TD’s immutable state – that functionality is 
discussed in 7.3.1 . 15 
The host VMM is expected, prior to invoking TDH.EXPORT.STATE.IMMUTABLE, to create enough migration stream s 
contexts using TDH.MIG.STREAM.CREATE.  
Inputs  
• Source TD handle:  the TDR page HPA  
• MBMD HPA  20 
• Migration Page List HPA and size  
• Migration stream index  
• Number of migration streams that will be used during the in -order phase  
Pre-Conditions  
• TD is runnable  25

Inputs  
• TD is runnable  25 
• A new migration key has been set  
Operation (Session Control Aspects Only)  
1. Start the export session in-order  phase.  
2. Export a TD Immutable State MBMD.  The MBMD details the number of migration streams that will be used during 
the in -order phase  and the maximum number of migration streams.  30 
6.5.2.  TDH.EXPORT.PAUSE  
TDH.EXPORT.PAUSE pauses the source TD starts the TDX-enforced  blackout period .  This operation is local to the source 
platform and is not communicated to the destination platform.  
Inputs  
• Source TD handle:  the TDR page HPA  35 
Outputs  
• Success or failure status  
• TD immutable state has been exported . 
• All TD VCPUs have stopped executing  and no other TD -specific SEAMCALL is running.  40 
Operation  
• Prevent further TD entries and host -side functions that may modify the TD state.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 46 of 71 
Section 2:  TD Migration Architecture Specification  6.5.3.  TDH.EXPORT. TRACK  
TDH.EXPORT. TRACK  starts a new migration epoch .  It generate s an epoch token.  If so requested, it starts the out -of-order 
phase and generates a  start.  
Inputs  
• Source TD handle:  the TDR page HPA  5 
Outputs  
• Epoch  token migration bundle  
• The export session is in progress, but its out-of-order  phase has not begun yet.  10 
• If a start token is to be generated : 
For any page that has been exported so far, an up -to-date version of that page has been exported.  
Note:  TDH.EXPORT.TRACK does not check that all non -memory state has been exported.  This is checked on the 
destination platform by TDH.IMPORT.TRACK.  
Operation  15 
1. Start a new migration epoch . 
2. Create a n epoch token migration bundle which includes only  an MBMD.  
6.5.4.  TDH.EXPORT.ABORT  
TDH.EXPORT.ABORT aborts the export session.  If invoked during the in-order export  phase, after the TD has been paused, 
it re-enables the TD to run on the source platform.  If invoked during the out-of-order  phase, it consumes an abort token 20 
received from the destination platform; if that token is correct it enables the TD to run on the source platform.  
Inputs  
• Optional:  m igration bundle containing the abort token received from the destination platform.  
Pre-Conditions  25 
• An export session is in progress . 
• Export has not been committed by TDH.EXPORT.COMMIT . 
Operation  
• Terminate the export session:  Invalidate  all migration contexts for source TD. 
• If the export session is in the in-order  phase, re -enable the TD.  30 
• If the export session is in the out-of-order  phase, check the abort token.  If valid, re -enable the TD.  
6.6. Import Session Control Functions  
This section provides an overview of the import session control functions.  A detailed description is provided in [TDX 
6.6.1.  TDH.IMPORT.STATE.IMMUTABLE (Session Control Aspects)  35 
TDH.IMPORT.STATE.IMMUTABLE consumes a TD immutable state migration bundle and starts the import session  in-order 
phase .  It also imports the TD’s immutable state – that functionality is discussed in 7.4.1 . 
The host VMM is expected, prior to invoking TDH.IMPORT.STATE.IMMUTABLE, to parse the received MBMD, determine 
the number of migration streams required and assure that enough migration stream contexts have been created using 
TDH.MIG.STREAM.CREATE.  40 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 47 of 71 
Section 2:  TD Migration Architecture Specification  Inputs  
• Destination TD handle:  the TDR page HPA  
• MBMD HPA  
Pre-Conditions  5 
• TDCS been allocation but not initialized.  
• A new m igration key has been set . 
Operation  (Session Control Aspects Only)  
Start the import session in-order  phase.  
Any failure aborts the operation and marks the TD as IMPORT_FAILED; it will not  run. 10 
6.6.2.  TDH.IMPORT. TRACK  
TDH.IMPORT. TRACK  consumes a n epoch  token received from the source platform  and starts a new epoch.  If a start token 
is received, TDH.IMPORT.TRACK starts the import session in-order phase.  
Any failure aborts the operation and marks the TD as IMPORT_FAILED; it will not  run. 
Inputs  15 
• Migration bundle containing the epoch  token  
Outputs  
• None  20 
• The import session is in progress, but its out-of-order  phase has not begun yet.  
• The start token migration bundle is imported successfully.  
• If a start token is received, all mutable state must have been imported . 
Operation  25 
1. Starts a new migration epoch . 
2. If a start token has been received , start the out -of-order import phase.  
6.6.3.  TDH.IMPORT.COMMIT  
TDH.IMPORT.COMMIT enables the TD to run.  
Inputs  30 
Outputs  
• None  
• The import session out-of-order phase is in progress.  35 
Operation  
• Set the TD’s OP_STATE to LIVE_IMPORT, allowing it to run . 
6.6.4.  TDH.IMPORT.END  
TDH.IMPORT.END ends the import session.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 48 of 71 
Outputs  
• None  
• The import session out -of-order phase is in progress.  
Operation  
• Set the TD’s OP_STATE to RUNNABLE, ending the import session and allowing the TD to run.  
6.6.5.  TDH.IMPORT.ABORT  
TDH.IMPORT.ABORT aborts the import session (if not already aborted) and g enerate s an abort token .  The TD will not  10 
run. 
Inputs  
Outputs  
• Migration bundle containing the abort token  15 
• The import session is in progress.  
• The TD is not allowed to run yet (OP_STATE is not LIVE_IMPORT).  
Operation  
• Generate an abort token MBMD . 20 
• Set the OP_STATE  to FAILED_IMPORT.  In this state it can only be torn down.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 49 of 71 
Section 2:  TD Migration Architecture Specification  7. TD Non -Memory S tate Migration  
This chapter discuss es all non -memory state migration, immutable and mutable . 
TD-scope non -memory state resides in control structures TDR and TDCS.  TD VCPU state resides (while the VCPU is not 
running) in TDVPS, which includes the TD VMCS.  This chapter discusses how non-memory state migration  is migrated.  
7.1. TD Non -Memory State Migration Operation  5 
7.1.1.  Non -Memory State Migration Data  
Non -memory state migration data is used for migrating immutable state, at the beginning of the migration process, by 
TDH. EXPORT .STATE.IMMUTABLE  and TDH. IMPORT .STATE.IMMUTABLE , and for migrating mutable state, at the end of 
the migration process, by TDH. EXPORT .STATE.TD , T DH.IMPORT .STATE.TD ,  TDH. EXPORT .STATE.VP  and 
TDH. IMPORT .STATE.VP . 10 
The non -memory state is migrated in a way that abstracts the actual TD control structure format, allowing that format to 
remain implementation -dependent and vary between the source and destination platform s.  To support that, each of the 
state migration data’s 4KB pages contains a TD metadata list , composed of multiple field sequences .  Each field sequence 
contains a sequence header  and one or more field values . 
Metadata abstraction is discussed in the [ TDX Module Base Spec ]. 15 
TD Metadata List
Header NUM_SEQUENCES
Multiple -
Field 
SequenceSEQUENCE_HEADER(LAST_INDEX = n)
FIELD_VALUE 0
FIELD_VALUE 1
…
FIELD_VALUE n
Single -Field 
SequenceSEQUENCE_HEADER(LAST_INDEX = 0)
FIELD_VALUE
Multiple -
Field 
SequenceSEQUENCE_HEADER(LAST_INDEX = m)
…
FIELD_VALUE m
Reserved8 Bytes
4096 Bytes
 
Figure 7.1:  Non -Memory State Migration Page  
Metadata fields are exported in order of their field codes.  This enables easy identification of missing required fields on 
import.  
7.1.2.  Non -Memory State MBMD  20 
The MBMD for each non -memory state migration bundle contains the following type -specific fields:  
• Metadata type :  Immutable TD-scope metadata  or mutable L1 VCPU -scope  metadata  
• VM index and VCPU index  (if applicable).  
Details of the non -memory state MBMD are defined in  the [TDX Module ABI Spec ]. 
7.1.3.  Immutable vs. Mutable TD State  25 
In the scope of  TD migration, immutable  state i s defined as any TD state that may not change after TD build, i.e., after  
TD measurement has been finalized (by TDH.MR.FINALIZE ). TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 50 of 71

…
4096 Bytes
 
import.  
November 2023   . Page 50 of 71 
Section 2:  TD Migration Architecture Specification  Migrated immutable state  includes the following:  
• Platform -scope immutable state required so that the TDX module on the destination platform  can verify 
compatibility.  Namely, it includes the source TDX module’s version information .  
• TD-scope immutable state of the source TD  
Immutable TD state export  and import  function s (TDH. EXPORT .STATE.IMMUTABLE , TDH.IMPORT.STATE.IMMUTABLE ) 5 
start the migration session .  Migration session control is discussed in Ch. 5.5. 
Migrated mutable state  includes the following:  
• TD-scope mutable state  
• VCPU -scope mutable state  
Mutable TD state export  is done after the TD has been paused (by TDH.EXPORT.PAUSE ), and helps ensure  that the state 10 
will not change anymore until TD export completes.  TDH. EXPORT .STATE.TD  exports TD -scope mutable state, followed 
by multiple, per -VCPU TDH. EXPORT .STATE.VP s which export VCPUs mutable state.  
Mutable TD state impo rt must begin with TD -scope state import (by TDH. IMPORT .STATE.TD ), followed by multiple, per -
VCPU TDH. IMPORT .STATE.VP  which import VCPUs state.  
7.2. State Migration Rules  15 
7.2.1.  General State Export Rules  
Only  state that may be  used for import on the destination platform  is exported from the source platform.  State that is 
never imported, or that is not in use based on the TD configuration (ATTRIBUTES, XFAM and CPUID configuration), is not 
exported.  For example:  
• KeyLocker state is not exported if ATTRIBUTES.KL is not set to 1.  20 
• Only the defined VAPIC page fields are exported.  
There may be exceptions where state is exported even if it’s not explicitly imported.  This may be done for possible future 
compatibility or for simplicity of export.  For example:  
• TDX module version information – this information is exported so a future TDX module may examine it on import, to 
take some action due to possible incompatibility or bug of the exporting TDX module.  25 
7.2.2.  General State Import Rules  
In addition to the immutable or mutable classification, n on-memory state can be classi fied as migrated  and/or initialized .  
For migrated each state component, import may be mandatory  or optional .  For optionally migrated state, a default 
initial value must be specified.  
Each import function verifies that all the applicable mandatory state has been imported and  initializes the default values 30 
for state components that have not been imported.  
7.2.3.  Immutable  State Import  Rules  
TD immutable state is verified by TDH. IMPORT .STATE.IMMUTABLE  against destination platform  capabilities and Intel TDX 
module version, capabilities and configuration.  The checks are similar , but not identical, to the TD_PARAMS checks done 
on the source platform by TDH.MNG.INIT .  For example:  35 
• TD ATTRIBUTES bits must be compatible with the destination platform  and Intel TDX module configuration.  
• Any XFAM bit that was set on the source platform by TDH.MNG.INIT  must be supported by the destination platform . 
• Virtual CPUID configuration is calculated on the source platform by TDH.MNG.INIT .  This configuration is exported 
and checked on import to be compatible with the destination platform .  If a certain CPUID leaf or sub -leaf is not 
virtualized on the source platform (i.e., its execution by the TD results in a #VE), it is also not virtualized on the 40 
destination platform – even if it would be virtualized on that platform if the TD was created there.  CPUID 
virtualization, including fine -grained virtualization of sub -features, is described in the [ TDX Module Base Spec ]. 
Immutable state that can be regenerated on the destination platform  is not imported.  For example:  
• The TD’s MSR exit bitmaps are generated by TDH. IMPORT .STATE.IMMUTABLE , like the way they are generated by 
TDH.MNG.INIT  on the source platform.  45 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 51 of 71 
Section 2:  TD Migration Architecture Specification  7.2.4.  Mutable State Import  Rules  
Intel SDM, Vol. 3, 26.3.1  Checks on the Guest State Area  
Intel SDM, Vol. 3, 26.8  VM-Entry Failures During or After Loading Guest State  
 Imported State Verification  
Mutable non -memory state is verified by TDH. IMPORT .STATE.TD  and TDH. IMPORT .STATE.VP  against destination platform  5 
capabilities and Intel TDX module configuration .  For example : 
• CR0 and CR4 values are verified using the same rules used for CR0 and CR4 virtualiz ation, respectively.  This is 
required because the values of the IA32_ VMC_CR*_FIXED* MSRs  may be different between the platforms .  For 
details, see the [ TDX Module Base Spec ]. 
• CPUID virtualization state, originally calculated on TD initialization based on configuration and the capabilities of the 10 
source CPU, is verified versus the capabilities of the destination CPU.  
 Handling State that is Not Verified on Import  
In some cases, immutable VCPU state is difficult to verify during TDH. IMPORT .STATE.VP .  This may include, for example:  
• Guest MSR state saved in TDVPS  
• Guest state saved in TD VMCS  15 
In those cases, the TDX Module  reports the incompatibility on TDH.VP.ENTER  using CPU compatibility checks , as follows:  
• The Intel TDX module gracefully handle s WRMSR errors, i.e., #GP(0), that occur during the TDH.VP.ENTER  flow when 
loading guest MSR values.  In this case, the Intel TDX module marks the TD as FATAL and TDH.VP.ENTER  terminates 
with an error code.  
Note:  This is different from the current TDX 1 behavior , but may be implemented in TDX 1 due to a requirement 20 
to support host VMM writes of guest MSRs for debug TDs.  
• The Intel TDX module gracefully handles guest state checks that fail during VM entry.  In this case, the CPU behavior 
is like a VM exit, with the exit reason indicating VM-entry failure due to invalid guest state , MSR loading or a machine -
check event.  In this case, the Intel TDX module marks the TD as FATAL and TDH.VP.ENTER  terminates with an error 
code.  25 
Note:  This is different from the current TDX 1 behavior but  may be implemented in TDX 1 due to a requirement 
 State Initialized or Calculated on Import  
Many of the TD VMCS execution controls that control the host VMM interaction with the guest TD are reset to their initial 
state on import.  These include, for example:  30 
• Posted interrupt execution controls (see the [ TDX Module Base Spec ]) 
Other state is calculated on import.  For example:  
• The virtual TSC value , sampled and exported by TDH. EXPORT .STATE.TD , is used  by TDH. IMPORT .STATE.TD  to 
calculate a new TSC offset so that the virtual TSC value will continue as a monotonously incrementing value on the 
destination platform .  For details see the [ TDX Module Base Spec ]. 35 
7.3. Non -Memory State Export Functions  
7.3.1.  TDH. EXPORT .STATE.IMMUTABLE  (State Export Aspects)  
TDH. EXPORT .STATE.IMMUTABLE  exports the TD’s immutable state as a multi -page migration bundle.   It also starts the 
export session – that functionality is described in  6.5.1 . 
A detailed description of TDH.EXPORT.STATE.IMMUTABLE is provided in the [TDX Module ABI Spec ]. 40 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 52 of 71 
• MBMD HPA  
• Migration stream index  5 
• TD is runnable  
Operation  (State Export Aspects Only)  10 
1. Export the TD’s immutable state:  
1.1. Serialize and encrypt the TD exported immutable state into the multi -page migration data buffer . 
1.2. Update the MBMD with the MB type, stream index, metadata type and the MAC . 
7.3.2.  TDH. EXPORT .STATE.TD  
TDH. EXPORT .STATE.TD  exports the TD -scope mutable state as a multi -page migration bundle.  15 
A detailed description of TDH.EXPORT.STATE.TD is provided in the [TDX Module ABI Spec ]. 
Inputs  
• MBMD HPA  
• Migration Page List HPA and size  20 
• The export session is in the in -order phase and the TD has been paused  
Operation  
1. Export the TD’s mutable state:  25 
1.1. Serialize and encrypt the TD exported mutable state into the multi -page migration data buffer.  
1.2. Update the MBMD with the MB type, stream index, metadata type and the MAC.  
7.3.3.  TDH. EXPORT .STATE.VP  
TDH. EXPORT .STATE.VP  exports the VCPU -scope mutable state as a multi -page migration bundle.  
A detailed description of TDH.EXPORT.STATE.VP is provided in the [TDX Module ABI Spec ]. 30 
Inputs  
• Source VCPU handle:  the TDVPR page HPA

Inputs  
• MBMD HPA  
Operation  
Inputs  
• Source VCPU handle:  the TDVPR page HPA  
• MBMD HPA  
• Migration stream index  35 
Operation  
1. Export the VCPU’s mutable state:  
1.1. Serialize and encrypt the VCPU  exported mutable state into the multi -page migration data buffer.  40 
1.2. Update the MBMD with the MB type, stream index, metadata type and the MAC.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 53 of 71 
Section 2:  TD Migration Architecture Specification  7.4. Non -Memory State Import Functions  
7.4.1.  TDH. IMPORT .STATE.IMMUTABLE  (State Import Aspects)  
TDH. IMPORT .STATE.IMMUTABLE  imports the TD’s immutable state as a multi -page migration bundle.   It also starts the 
import session – that functionality is described in  5.5. 
A detailed description of TDH.IMPORT.STATE.IMMUTABLE is provided in the [TDX Module ABI Spec ]. 5 
Inputs  
• Destination TD  handle:  the TDR page HPA  
• MBMD HPA  
Pre-Conditions  10 
• TD has not been initialized  
Operation  (State Import Aspects Only)  
1. Initialize TDCS default values.  
2. Read MBMD into an internal buffer.  15 
3. To save internal buffer space, the steps below can be done on, e.g., one import data page at a time:  
3.1. Decrypt the TD immutable state from  the multi -page migration data buffer  into a temporary buffer.  
3.2. De-serialize the imported fields, verify, then set TDR and TDCS fields based on the imported values.  
4. Verify the calculated  MAC  versus the value read from the MBMD.  
5. Verify that all required fields have been imported.  20 
Any verification failure aborts the operation and marks the TD as IMPORT_FAILED; it will not  run. 
7.4.2.  TDH. IMPORT .STATE.TD  
TDH. IMPORT .STATE.TD  imports the TD’s mutable state as a multi -page migration bundle.  
A detailed description of TDH.IMPORT.STATE.TD is provided in the [TDX Module ABI Spec ]. 
Inputs  25 
• MBMD HPA  
• TD immutable state has been imported  30 
Operation  
1. Read MBMD into an internal buffer.  
2. To save internal buffer space, the steps below can be done on, e.g., one import data page at a time:  
2.1. Decrypt the TD mutable state from the multi -page migration data buffer into a temporary buffer.  
2.2. De-serialize the imported fields, verify, then set TDR and TDCS fields based on the imported values.  35 
3. Verify the  calculated  MAC versus the value read from the MBMD.  
4. Verify that all required fields have been imported.  
5. Allow VCPU state  import:  Set TDCS.OP_STATE to STATE_IMPORT.  
7.4.3.  TDH. IMPORT .STATE.VP  40 
TDH. IMPORT .STATE.VP  imports a VCPU mutable state as a multi -page migration bundle.  
A detailed description of TDH.IMPORT.STATE.VP is provided in the [TDX Module ABI Spec ]. TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 54 of 71 
• Destination  VCPU handle:  the TDVPR page HPA  
• MBMD HPA  
• TDVPS pages have been allocated by the host VMM, but the VCPU has not been initialized.  
• TD-scope  state has been imported  
Operation  
1. Initialize the TDVPS (including TD VMCS) default values.  
2. Read MBMD into an internal buffer.  10 
3.1. Decrypt the VCPU  mutable state from the multi -page migration data buffer into a temporary buffer.  
3.2. De-serialize the imported fields, verify, then set TDVPS (including TD VMCS)  fields based on the imported values.  
4. Verify the  calculated  MAC versus the value read from the MBMD.  
5. Verify that all required fields have been imported.  15 
November 2023   . Page 55 of 71 
Section 2:  TD Migration Architecture Specification  8. TD Private Memory  Migration  
This chapter described how Intel TDX Module  manages TD private memory and guest -physical (GPA) address translation  
meta -data migration . 
8.1. Overview  
TD private memory migration can happen in the in -order migration phase and out -of-order migration phase.  5 
During the in -order phase, the host VMM may implement live migration  pre-copy , by export ing memory content (using 
TDH.EXPORT.MEM  etc.) while the TD is running (TDCS.OP_STATE is LIVE_EXPORT).  This is not enforced by TDX;  the host 
VMM may implement  cold migration  by avoiding memory export until the TD is paused.  
During the out -of-order phase, t he host VMM may implement post -copy  by allowing the TD to run on the destination  
platform (using TDH.IMPORT.COMMIT).  This is not enforced by TDX; the host VMM can first complete all memory 10 
migration before allowing the TD to run, yet benefit from the simpler and potentially higher performance operation 
supported during the out -of-order phase.  
8.2. Achieving Memory Migration Security Objectives  
8.2.1.  General  
The key security design goal  for TD Private memory migration is to ensure integrity and freshness of the TD private 15 
memory at the destination TD after migration – this helps  ensure that a malicious VMM cannot execute the TD after 
migration with any stale or modified data.  
Integrity of memory includes the memory contents as well as the guest physical to host physical mapping and attributes 
that control TD access to private memory.  
Using PAMT and Secure EPT , Intel TDX Module enforces the following properties for TD private GPA accesses:  20 
Unique TD Association:  A physical page used as a TD private page, Secure EPT page or a control structure can only be 
assigned to single guest TD.  
Unique GPA Mapping:  A TD private page or a Secure EPT page can be mapped at most by single guest TD GPA.  
These security properties are maintained for a TD during migration with some additional functionality afforded to allow 
for live migration.  25 
• Private TD pages and S ecure EPT entries (for partitioned TDs, this includes L2 Secure EPT entries) are initialized in a 
single operation  (via TDH.IMPORT.MEM ) for pages migrated using TDH.EXPORT.MEM .  Like the pre -conditions for 
the non -migration TD H.MEM. PAGE .ADD , the parent Secure EPT entry must be free (unmapped).  
• On the source platform, a  private page may be mapped as non-writable  (a.k.a. blocked for writing)  to allow for the 
page contents to be exported .  For partitioned TDs, this any L2 mapping of a page is also mapped as non -writable.  30 
Following from previous security requirements, this mapping update also require s TLB tracking to help ensure that 
no active writable cached GPA address translations exist to the to -be-migrated GPA range.   
• For 1GB and 2MB pages, s ecure EPT mapping demotion (to a 4KB page size) is require d as a pre -condition to exporting 
contents of a page for migration . 
• The Migration key used for exporting and important TD memory and CPU state is distinct from keys used for other 35 
operations such as Paging.  
8.2.2.  Migration Epochs:  Usage of Stale Memory Copies due to Mis -Ordering  
Running the destination TD with a stale copy  of a memory page, because an older copy of a page was imported after a 
newer copy of that page, is prevented by the migration epochs mechanism.  Within each migration stream, proper 
ordering is maintained by the migration bundle counter (MB_COUNTER) of ea ch MBMD.  However, there is no intrinsic 40 
guarantee of ordering across migration streams.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 56 of 71 
Stream
1
Stream
2
Stream
3Stream
0Page
0Page
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29Mig. Epoch 0 Mig. Epoch 1 Mig. Epoch 2In-Order Phase Out-Of-Order PhaseTime
Live Migration (TD is Running on Source)Post -Copy (TD 
Epoch
Token
TRACKTDH.EXPORT.
BLOCKWTDH.EXPORT.
BLOCKW
MEM
STATE.
MEM
Export Round 0 Export Round 1 Export Round 2

Stream
1
Stream
2
Stream
3Stream
0Page
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Epoch
Token
BLOCKW
MEM
STATE.
MEM
(Final)TDH.EXPORT.
MEM
MEM
MEM
Out-Of-Order ExportTDH.EXPORT.
UNBLOCKWTDH.EXPORT.
UNBLOCKWMig. Epoch 0xFFFFFFFF
 
Figure 8.1:  Migration Epochs  
To help ensure  overall ordering, the migration session is divided to migration epochs .  A given page can only be imported, 
or its import can be cancelled, once per migration epoch.  An epoch token  serves as an epoch separator.  It provided the 
total number of migration bundles exported so far.  This helps TDH.IMPORT.TRACK, which imports the epoch token, 5 
checks that all migration bundles of the previous epoch have been received.   No migration bundle of an older epoch may 
be imported.  
The start token , which starts the out -of-order phase,  is a special version of the epoch token.  Epoch number 0xFFFFFFFF 
indicates the out -of-order phase.  
Note:  Migration epoch is a TDX concept.  It roughly corresponds to migration round  (or migration pass ) which is a 10 
usage concep t. 
8.2.3.  Preventing Usage of Stale Memory Copies due to Failure to Import  
Running the destination TD  with a stale copy  of a memory page , because the target VMM failed to import a newer copy 
of a page,  is prevented as follows : 
Newer page state can only be generated before the source TD is paused (by TDH.EXPORT.PAUSE ).   Assume for example 15 
that two versions (v1 and v2) of the same page were exported, but the destination platform’s  VMM only imports the 
older version (v1), withholding the newer one (v2) . 
The in-order phase commitment protocol is designed to ensure that the export will fail, and the destination TD  will not 
run.  TDH.EXPORT. TRACK  with a n in-order -done parameter  generates a start token that is dependent of the exact export 
sequence ; it checks that no unexported newer versions of previously exported pages remain .  Th e start  token is verified 20 
by TDH.IMPORT. TRACK ; the out-of-order migration phase may start, and the destination TD  may  run only if the start 
token verifies correctly.  For migration session control details see  Ch. 6. 
8.2.4.  Preventing Usage of Stale Memory Copies due to Failure to Export  
Running the destination TD  with a stale copy  of a memory page, because the source VMM failed to export a newer copy 
of a page, is prevented as follows:  25 
Assume for example that the source VMM exported an older version ( v1) of page but never exported a newer version  
(v2) of that page.  In this case, generating a start token by TDH.EXPORT. TRACK  is prevented .  A counter of dirty  pages 
(TDCS.DIRTY_COUNT) is accumulated by the TDX module  at source platform .  If the value of that counter is not 0, then 
TDH.EXPORT. TRACK  fails.  See 8.4.7.3  for details.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 57 of 71 
Section 2:  TD Migration Architecture Specification  8.2.5.  Preventing Usage of Stale Memory GPA Mapping and Attributes  
The destination TD is preventing from running with a copy of a memory  page with stale GPA mapping, access permissions  
and other attributes (for partitioned TD, this included L2 mapping) as follows:  
• GPA mappings  and attributes are migrated together with their respective pages.  
• Any change to GPA mappings or attributes  is considered a change to the page and requires re -migration.  5 
8.2.6.  Out-Of-Order Phase and Its Usage for Post Copy  
In the in -order import phase the VMM can import page for GPA addresses that are free, and it may also reload newer 
versions of pages to previously imported and present GPA addresses.  In the out -of-order import phase, import is only 
allowed to non -present GPA addresses.  At this stage, all memory state on the source platform is designed  to be 
immutable, and the latest version of all pages exported so far will be  imported.  Thus, the order of out -of-order import is 10 
not relevant – except that memory content exported during the in -order phase can’t be imported during the out -of-order 
phase.  This allows using a separate migration stream for high -priority, low -latency updates, e.g., to implement post -copy  
by allowing the TD to run and migrate memory pages on demand at a high priority, based on EPT violation.  
8.3. GPA Lists and Private Memory Migration Bundle  
PAGE_HPA1
Mig. Buffers ListMBMD
4KB
Migration
Page4KB
Migration
PageUp to
512 * 4KB
Encrypted 
Migration
Pages
Migration BundleTDH.EXPORT.MEM TDH.IMPORT.MEM
PAGE_HPA1
Mig. Buffers ListTransport
Migrated DataMBMD
4KB
Migration
Page4KB
Migration
PageUp to
512 * 4KB
Encrypted 
Migration
Pages
Migration BundleMigrated DataPage GPA 
List
4KB
Migration
Page4KB
Migration
PageUp to
512 * 4KB
PagesPage GPA 
List
PAGE_HPA1
PAGE_HPAlastNew Pages List*
*HPA is null for in -
place import and for 
re-importPage MAC 
ListPage MAC 
ListOptional 
Encrypted 
Page 
Attributes 
Encrypted 
Page 
List
 15 
Figure 8.2:  Private Memory Migration  
Contrary to the generic migration bundle structure  described in 5.1, private memory migration bundle is composed of 
multiple MAC -protected components:  
• MAC -protected MBMD  
• For each 4KB page : 20 
o Encrypted and MAC -protected 4KB migration buffer  
o MAC -protected page GPA and additional metadata  
o Optionally , for partitioned TDs, encrypted and MAC -protected page attributes  
This structure allows the export and import functions to process the MBMD and each page and its metadata separately, 
avoiding the need to perform SEPT walks twice and to hold intermediate SEPT entry states.  The separate parts of the 25 
migration bundle are cryptographically bound together as follows:  
• A per -stream monotonously incrementing IV_COUNTER and the migration steam index are used for calculating the 
AES-GCM IV value, as described in 5.3. TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 58 of 71 
Section 2:  TD Migration Architecture Specification  • This is first done for the migration bundle’s MBMD MAC.  
• For each page, the IV_COUNTER is incremented by 1 and a new IV value is calculated and used for the page metadata 
MAC.  
• The MBMD specifies the number of pages migrated by the migration bundle.  This helps check that the whole 
migration bundle is imported on the destination platform.  5 
8.3.1.  GPA List  
A GPA list is used as part of the private memory migration bundle.  It is also used as an input and output of multiple 
memory migration interface functions:  TDH.EXPORT.BLOCKW, TDH.EXPORT.MEM, TDH.EXPORT.RESTORE and 
TDH.IMPORT.MEM.  
A GPA list contains up to 512 entries, each containing the following information:  10 
Table 8.1:  GPA List Entry  Abstract Definition  
Field  Page Migration  
Type  4KB Page  
GPA  GPA bits 51:12  
State  MAPPED  or PENDING  
Operation  NOP, MIGRATE, REMIGRATE  or CANCEL  
 
A detailed definition of the GPA list is provided in the [ TDX Module ABI Spec ]. 
A single GPA list entry , a separate page MAC list entry and an optional separate page attributes list entry compose the 
page me tadat a. 15 
8.3.2.  Optional Page Attributes List  
If the migrated TD is partitioned  (TDCS.NUM_L2VMS is greater than 0 ), a page attributes list  is used to extend the GPA 
list with the page attribute s. 
A page attributes list  contains the same number of entries as the GPA list.  Each entry contains 3 sub -entries, one for each 
L2 VM, each containing the following information:  20 
• A flag indicating that the page attributes for this L2 VM are  valid.  
• Migratable page attributes:  R, W, Xs, Xu, SSS, VGP , PWA , SVE  
A detailed definition of the page attributes list  is provided in the [ TDX Module ABI Spec ]. 
8.3.3.  Private Memory Migration Buffer  
Migration buffer is included only if the page metadata indicates a MIGRATE or a REMIGRATE request, and the page is 25 
MAPPED .  it contains the encrypted content of the migrated page.  
8.4. TD Private  Memory Export  
8.4.1.  Typical Export Round  
Typical expected usage divides the export session to export rounds  (or passes ).  An export round may have the following 
steps:  30 
1. If the TD has not been paused by TDH.EXPORT.PAUSE, ensure TLB shootdown:  
1.1. Invoke TDH.EXPORT.BLOCKW with a list of pages to be exported.  
1.2. Invoke  TDH.MEM.TARCK . 
1.3. Issue IPIs to ensure TD re -entry on all VCPUs and TLB invalidation . 
2. Start a new migration epoch  by invoking TDH.EXPORT.TRACK . 35 
3. Invoke TDH.EXPORT.MEM with a list of pages.  
3.1. If a page is being exported, mark its list entry as MIGRATE.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 59 of 71 
Section 2:  TD Migration Architecture Specification  3.2. If a page has been exported before but need to be removed, promoted or demoted, cancel its migration by

steps:  30 
Section 2:  TD Migration Architecture Specification  3.2. If a page has been exported before but need to be removed, promoted or demoted, cancel its migration by 
marking its list entry as CANCEL.  
Note:  In the example above, steps 1 and 2 need to be performed before step 3, but there is no strict requirement for 
the order of step 2 vs. step 1.  
8.4.2.  Using the same GPA List for TDH.EXPORT.BLOCKW and TDH.EXPORT.MEM  5 
TDH.EXPORT.BLOCKW and TDH.EXPORT.MEM use GPA lists with compatible formats.  This allows the same list to be used 
for blocking and exporting memory, as follows:  
1. The host VMM on the source platform may prepare a GPA list with MIGRATE and CANCEL commands, and provide it 
as input to TDH.EXPORT.BLOCKW.  
2. TDH.EXPORT.BLOCKW will attempt to block pages whose command is MIGRATE, and update the GPA list depending 10 
on the success of the operation.  
3. The same GPA list can be provided as input to TDH.EXPORT.MEM, which then updates it depending on the success 
of the operation  and whether this is a first time export (MIGRATE) or re -export (REMIGRATE) , and adds page 
attributes information.  
PAGE_HPA1
4KB
Migration
Page4KB
Migration
PageUp to
512 * 4KB
Encrypted 
Migration
Pages
Migration BundleTDH.EXPORT.MEM
Migrated DataPage GPA & 
List
Page MAC 
ListTDH.EXPORT.BLOCKWPage GPA 
ListPage GPA 
List
TDH.MEM.TRACKUpdate operation
and statusUpdate operation,
status and attributes
 15 
Figure 8.3:  Typical Memory Export Round and the GPA List  
8.4.3.  SEPT Leaf Entry Partial State Diagram for Mapped Page Export  
Figure 8.4 below  shows a partial SEPT entry state diagram for exporting mapped pages.  The following sections describe 
the details.  20 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 60 of 71 
MAPPED
TDBLOCKEDW
new write 
translations are 
blockedTDH.EPORT.BLOCKW
[TD is not paused]
TDH.EXPORT.UNBLOCKWEXPORTED_
BLOCKEDW
Page is exported and 
blocked for writingTDH.EXPORT.MEM(MIGRATE) /
MIGRATE,
MIG_COUNT++TDH.MEM.
RANGE.BLOCK
TDH.EXPORT.MEM(MIGRATE)
[out-of-order] /
MIGRATE
EXPORTED_
DIRTY
TDTDH.EXPORT.UNBLOCKW /
DIRTY_COUNT++
TDH.EPORT.BLOCKW
EXPORTED_
DIRTY_BLOCKEDW
blocked for writingTDH.EXPORT.MEM
(MIGATE) /
REMIGRATE,
DIRTY_COUNT --
TDH.EXPORT.UNBLOCKWBLOCKED
blocked
See Leaf Entry 
TDH.EXPORT.MEM(CANCEL) /
DIRTY_COUNT --, MIG_COUNT --TDH.EXPORT.MEM(CANCEL) /
DIRTY_COUNT --, MIG_COUNT --TDH.EXPORT.RESTORE /
MIG_COUNT --TDH.EXPORT.MEM(MIGRATE)
[TD is paused] /
MIGRATE,
MIG_COUNT++
TDH.EXPORT.MEM
(MIGRATE)
TDH.EXPORT.RESTORE /
MIG_COUNT --
MIG_COUNT --TDH.EXPORT.MEM(CANCEL) /
 
Figure 8.4:  Partial SEPT Leaf Entry State Diagram for Mapped Page Export  
8.4.4.  L2 SEPT Leaf Entry Partial State Diagram for Mapped Page Export  
For partitioned TDs, m igration of page L2 attributes is done together with the page itself ; it is controlled by the L1 SEPT 
entry state.  Thus, the L2 SEPT entry state machine is quite simple, and is designed to control access to the page by the 5 
L2 VM.   Specifically, there are no additional states and transitions for page export.   When a page is blocked for writing 
(L1 SEPT state is one of the *BLOCKEW* states), the L2 SEPT entry state becomes L2_BLOCKED.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 61 of 71 
L2_MAPPED
L1 state is MAPPED 
or EXPORTED_DIRTY
L1 state is 
*BLOCKEDW*TDH.EXPORT.BLOCKW
TDH.EXPORT.UNBLOCKW TDH.EXPORT.CANCEL
TDH.EXPORT.RESTORE 
Figure 8.5:  L2 Secure EPT Leaf Entry Partial State Diagram  for Mapped Page Export  
8.4.5.  Live Export:  Blocking for Writing, TLB Tracking and Export ing a Page  
During the live export phase (when TDCS.OP_STATE is LIVE_EXPORT), exporting a private memory page requires that 
page modification must be prevented.  This includes:  5 
• Page content  
• Page attributes  
• For partitioned TDs, L2 page attributes  
To achieve this, the page ’s L1 SEPT entry and any L2 SEPT entries must be blocked for writing by TDH.EXPORT.BLOCKW.  
If the TD has not been paused, the host VMM must execute the TLB tracking sequence below, which together with the 10 
checks done by TDH.EXPORT.MEM helps ensure  that no cached TLB entries that have been created before blocking for 
writing are left.  
1. Execute TDH.EXPORT.BLOCKW on each page to be exported , blocking subsequent creation of writable TLB 
translations to that page.  Note that cached translations may still exits at this stage.  
2. Execute TDH.MEM.TRACK, advancing the TD’s epoch counter.  15 
3. Send an IPI (Inter -Processor Interrupt) to each RLP (Remote Logical Processor) on which any of the TD’s VCPUs is 
currently scheduled.  
4. Upon receiving the IPI, each RLP will TD exit to the host VMM.  
At this point the blocked pages are considered tracked for export.  Even though some LPs may still hold writable TLB 
entries to the target GPA ranges, those are designed  to be flushed on the next TD entry.   Normally, the host VMM on 20 
each RLP will treat the TD exit as spurious and will immediately re -enter the TD.  
5. Export each page using TDH.EXPORT. MEM . 
8.4.6.  Exporting a Page after the Source TD is Paused  
After the source TD is paused, no blocking is required since the TD is not running.  This reduces the amount of work that 
needs to be done by the host VMM during the TD’s blackout period.   This is shown in the dashed transitions in Figure 8.4 25 
above . 
If the export session is aborted by TDH.EXPORT.ABORT, some LPs may still hold stale TLB entries exported pages.  To help 
ensure  they are flushed on the next TD entry, TDH.EXPORT. PAUSE  advances the TD’s epoch counter, similarly to 
TDH.MEM.TRACK.  
8.4.7.  Unblocking for Write, Tracking Dirty Pages  and Re -Exporting  30 
 Overview  
During the live export phase (when TDCS.OP_STATE is LIVE_EXPORT), the source TD may attempt to write a page that has 
been blocked for writing , or to modify the page attributes (for partitioned TDs, this includes L2 attributes) .  The TDX 
migration architecture allows the host VMM to unblock the page.  The Intel TDX module tracks such pages as “dirty”.  All 
dirty pages must be re -exported by the host VMM for the in-order  migration phase to be completed.  This assures that 35 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 62 of 71 
Section 2:  TD Migration Architecture Specification  either the latest version of a page has been exported  by the time the source TD is paused , or that page has not been 
exported at all.  
 Unblocking for Write and Re-Exporting a Page  
If the  source TD attempt s to write to a page that has been blocked for writing a TD exit will occur, indicating an EPT 
violation due to a write attempt to a non -writable page . 5 
Note:  No indication is directly provided to the host VMM whether this page is blocked for writing by 
TDH.EXPORT.BLOCKW or whether writing is disabled due to some other reason.  
Host VMMIntel TDX 
ModuleGuest TD
VM Exit (EPT Violation)
TD Exit (EPT Violation)
TDH.EXPORT.UNBLOCKW
VM entryWrite attempt
(failed)
Write attempt
(success)Remove write protection, mark 
the page as dirty if exported
 
Figure 8.6:  Typical Sequence for Unblocking a Page on Guest TD Write  Attempt  
To enable access to the page, the host VMM is expected to execute TDH.EXPORT.UNBLOCKW . 10 
• If the page has not yet been exported, TDH.EXPORT.UNBLOCKW restores its SEPT entry’s original MAPPED state.  
• If the page has been exported, TDH.EXPORT.UNBLOCKW updates its SEPT state to EXPORTED_DIRTY.  This state is 
similar from the guest TD’s memory access perspective to MAPPED, but it indicates that the page is dirty and needs 
to be re -exported.  
• For partitioned TDs, i f the page has any L2 mappings , TDH.EXPORT.UNBLOCKW unblocks their L2 SEPT entries by 15 
restoring their W bit value.  
The host VMM re -exports the page by TDH.EXPORT.BLOCKW, TLB tracking and TDH.EXPORT. MEM  as described in 0 
above . 
 TDCS. DIRTY_C OUNT:  TD-Scope Dirty Page Counter  
TDCS.DIRTY_COUNT is TD-scope dirty page counter.  20 
• DIRTY_COUNT is cleared when a new migration session begins ( by TDH. EXPORT.STATE.IMMUTABLE ). 
• DIRTY_COUNT is incremented when  a page that has previously been exported in the current session  is unblocked for 
writing by TDH.EXPORT.UNBLOCKW.  
• DIRTY_COUNT is decremented when a newer version of a page, which has previously been exported in the current 
session, it exported by TDH.EXPORT.MEM . 25

above . 
session, it exported by TDH.EXPORT.MEM . 25 
For successful start token generation by TDH.EXPORT. TRACK , the value of the DIRTY_COUNT must be 0 , indicating that 
all pages exported so far have their newest pages exported.  At this point, since the source TD is paused, no newer 
versions of any page can be created , and the destination TD  can start execution.  Private pages which has not been 
exported yet in the current session may still be remaining for post copy  export .  Note that exported pages may not have 
been transported yet.  The start token MBMD ’s TOTAL_ MB field  verification enforces that all exported state has been 30 
imported (in -order) on destination  – see the [TDX Module ABI Spec ] for details . 
8.4.8.  Re-Exporting a Non -Dirty Page  
In the out -of-order phase, where strict migration order is not enforced, t he host VMM may re -export a previously 
exported page even if it has not been unblocked for writing and its contents have not been modified.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 63 of 71 
Section 2:  TD Migration Architecture Specification  This allows  a page can be re -exported and transferred to the destination platform  over a high -priority stream.  This helps 
reduce destination TD  latency while waiting for a page to be imported.  
Such an operation is tagged MIGRATE, not REMIGRATE, in the exported GPA list.  This is because the exact same version 
of the page is being exported . 
8.4.9.  Interruptible Memory  Export  5 
TDH.EXPORT.MEM  may export up to 512 4KB  pages.  To keep its latency within reasonable limit, the function is designed 
to be interruptible.  TDH.EXPORT.MEM can only be interrupted after completing the export of each page.  If 
TDH.EXPORT.MEM  detects that an interrupt is pending, it saves its intermediate state and returns with a proper status 
indication.  The host VMM is expected to re -invoke TDH.EXPORT.MEM  to complete the export operation.  
Intermediate state is saved as part of the migration stream context that has been used for the interrupted 10 
TDH.EXPORT.MEM .  Upon invocation, TDH.EXPORT.MEM  checks to see if an intermediate state has been saved, and if so, 
it checks that it is being invoked with the same input arguments  as last time when it was interrupted.  
8.4.10.  Prohibited Operations on Exported Pages  and Export Cancellation  
Once a page has been exported during the current export session, it can’t be blocked , removed, promoted , demoted  or 
relocated .  This prevents the destination platform  from using a stale copy of that page.  15 
In order to perform such memory management operations on an exported page, the host VMM must first execute 
TDH.EXPORT.MEM  indicating a CANCEL operation for the page.   No migration buffer is required for this GPA list entry.  
The When the GPA list is processed on the destination platform  by TDH.IMPORT.MEM , the previously migrated page is 
removed from the destination TD .  TDH.EXPORT.MEM restores the page SEPT entry to its pre -export MAPPED or PENDING  
state.  20 
Source
Host VMMSource
TDX Module
TDH.MEM.PAGE.BLOCK(page X)
failure indication
TDH.EXPORT.MEM(CANCEL page X)TDH.EXPORT.MEM(MIGRATE page X)Destination
Host VMMDestination
TDX Module
TDH.IMPORT.MEM(CANCEL page X)TDH.IMPORT.MEM(MIGRATE page X)Migration Bundle(MIGRATE page X)
TDH.EXPORT.TRACK
Epoch Token
Migration Bundle(CANCEL page X)
success
 
Figure 8.7:  Typical Sequence for Cancelling a Page Export  
8.4.11.  Exporting Pending Pages  
The host VMM is not directly aware if a page is in a PENDING state or not; the guest TD may accept the page by 
TDG.MEM.PAGE.ACCEPT at any time.  Thus, TDH.EXPORT.MEM  may export a pending page.  This is indicated by the GPA 25 
list entry, and no migration buffer is used since the page content is not exported .  The page attributes (including the 
optional page attributes list entry) are exported.  On the destination platform , TDH.IMPORT.MEM  creates the page in a 
PENDING state.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 64 of 71 
PENDING
Page is pending guest 
TD acceptancePENDING_
BLOCKEDW
TDH.EXPORT.UNBLOCKWPENDING_
EXPORTED_
BLOCKEDW TDH.EXPORT.MEM(MIGRATE) /
MIGRATE,
(MIGRATE) /
MIGRATE
PENDING_
EXPORTED_
DIRTYTDH.EXPORT.UNBLOCKW /
PENDING_
EXPORTED_
DIRTY_BLOCKEDWTDH.EXPORT.MEM
DIRTY_COUNT --TDH.EXPORT.UNBLOCKWPENDING_BLOCKED
Page is pending and 
blocked
MIGRATE, MIG_COUNT++
(MIGRATE)
TDG.MEM.
PAGE.ACCEPTEXPORTED_
DIRTY
TDSee Mapped 
Leaf Entry 
Export State 
Diagram
 
Figure 8.8:  Partial SEPT Leaf Entry State Diagram for Pending Page Export  
L2_MAPPED
L1 state is PENDING*
TDH.EXPORT.BLOCKWTDH.EXPORT.UNBLOCKW TDH.EXPORT.CANCEL
TDH.EXPORT.RESTORETDG.MEM.PAGE.ACCEPT
 
Figure 8.9:  L2 Secure EPT Leaf Entry Partial State Diagram  for Pending Page Export  
If the guest TD accepts a pending page that has been exported, TDG. MEM. PAGE.ACCEPT results in an EPT violation.  The 5 
host VMM is expected to call TDH.EXPORT.UNBLOCKW, which marks the page as PENDING_EXPORT_DIRTY, and resume s 
the guest TD.  TDH. MEM. PAGE.ACCEPT then re -executes; it initialized the page and updates the SEPT state to mark the 
page as EXPORTED_DIRTY  (where the page is mapped and accessible to the guest TD).   The host VMM can then re -export 
the page, as described in 8.4.7 above .  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 65 of 71 
VM entryRemove write protection, mark 
the page as dirty if exportedTDG.MEM.PAGE.ACCEPT
TDG.MEM.PAGE.ACCEPT
Success 
Figure 8.10:  Typical Sequence for Unblocking a PENDING Page on TDG.MEM.PAGE.ACCEPT Attempt  
8.4.12.  SEPT Cleanup after Export Abort  
Following an export session is aborted (by TDH.EXPORT.ABORT) the source TD is allowed to run.  However, SEPT entries 
and, for partitioned TDs, L2 SEPT entries, that have been modified during the aborted export session keep their state.  5 
Such SEPT entries must be cleaned up by the host VMM before memory management operations are allowed on them, 
and/or before a new export session is attempted , as follows : 
• Cleanup of SEPT entries that have been blocked for writing is done by TDH.EXPORT.UNBLOCKW (if the page is to be 
written) or TDH.RANGE.BLOCK (is the page is to be blocked for some memory management operation).  
• Cleanup of SEPT entries that have been exported is done by TDH.EXPORT. RESTORE . 10 
To track and enforce proper clean up, the following counter is maintained in TDCS:  
• MIG_COUNT  counts the number of leaf SEPT entries that need to be cleaned up.   L2 SEPT entries (if any) are not 
counted.  
The counter is initialized to 0.  To start a new migration session, its value must be 0.  
TDH.EXPORT.MEM  increment s MIG_COUNT  for exported pages, and decrements MIG_COUNT for export cancels .   15 
8.5. TD Private Memory Import  
8.5.1.  In-Order Import  Phase  
 Overview  of In-order Import  
During the in-order  import phase, a page may be imported multiple times.  In addition, a page import may be cancelled.  
Ordering is maintained  by the MBMD’s MB_COUNTER  and the requirement that a page can only be imported once per 20 
migration epoch . 
Once out-of-order import phase  begins , any page s that ha s been imported are designed  to be up to date.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 66 of 71 
 
FREE
mapped to the TDMAPPED
TD
PENDING
TD acceptanceTDH.IMPORT.MEM(REMIGRATE)
[mapped]TDH.IMPORT.MEM(MIGRATE)
[mapped]
TDH.IMPORT.MEM(MIGRATE)
[pending]TDH.IMPORT.MEM(CANCEL)
TDH.IMPORT.MEM(CANCEL)TDH.IMPORT.MEM(REMIGRATE)
[mapped]
TDH.IMPORT.MEM(REMIGRATE)
[pending]REMOVEDTDH.IMPORT.MEM(MIGRATE)
[mapped]
[pending]  
Figure 8.11:  Partial SEPT Entry State Diagram  for Page In -Order Import Phase  
 Memory Management During In-Order Import  
8.5.1.2.1.  TLB Tracking  During In -Order Import

FREE
TD
PENDING
[mapped]
[mapped]
[mapped]
[pending]  
8.5.1.2.1.  TLB Tracking  During In -Order Import  
During the in -order import phase, no blocking and no TLB tracking is required, since the destination TD is not running yet.  5 
8.5.1.2.2.  Secure EPT Management  During In -Order Import  
Addition and removal of Secure EPT pages are allowed during the in -order phase – they are required as part of building 
the TD on the destination platform.  
An SEPT page can only be removed if all its entries are FREE; specifically, it can’t be removed if any entry state is 
REMOVED.  10 
8.5.1.2.3.  Page Management  During In -Order Import  
Page management operations are prohibited  during the in -order import phase:  
• Page addition by TDH.MEM.PAGE.ADD and TDH.MEM.PAGE.AUG  
• Page removal by TDH.MEM.PAGE.REMOV E 
• Page promotion and demotion by TDH.MEM.PAGE.PROMOTE and TDH.MEM.PAGE.DEMOTE  15 
• Page relocation by TDH.MEM.PAGE.RELOCATE  
• GPA range blocking and unblocking by TDH.MEM.RANGE.BLOCK and TDH.MEM.RANGE.UNBLOCK  
 Enforcing a Single Import Operation per Migration Epoch  
When a page is imported during the in -order phase, the current migration epoch is recorded.  Page re -import and import 
cancel operations check the recorded migration epoch.  For the import to succeed, it should be older than the current 20 
migration epoch.  
When a page import is cancelled during the in -order  phase , the physical page is removed but its SEPT entry is put into a 
REMOVED state, and the current migration epoch is recorded.  For partitioned TDs, any L2 SEPT entries that map the 
page become L2_FREE.   Page first -time import operation check  the recorded migration epoch.  For the import to succeed, 
it should be older than the current migration epoch.  25 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 67 of 71 
 Importing L2 Page Mappings  During In -Order Import  
For partitioned TDs, L2 page mappings are imported as part of a page import, and follow these rules:  
• When a page is imported or re -imported, its L2 page mappings, if any,  are created or updated in the L2 SEPT leaf 
entry.  
• When a page is re -imported, and a previously imported page mapping  does not exist in the new import, the L2 SEPT 5 
leaf entry is set to L2_ FREE.  
• When a page import is cancelled, its L2 SEPT leaf entries , if any,  are set to L2_ FREE.  
L2_FREE
L2 SEPT entry is not 
mapped to the TDL2_MAPPED
L2 SEPT entry is 
mapped as a page 
alias and accessible 
to L2 VM
[page alias doesn  t exist]TDH.IMPORT.MEM(MIGRATE)
[mapped, page alias exists]
[mapped, page alias exists]TDH.IMPORT.MEM(REMIGRATE)
alias but not 
accessible to L2 VMTDH.IMPORT.MEM(MIGRATE)
[pending, page alias exists]
[pending, page alias exists]TDH.IMPORT.MEM(CANCEL)
[page alias doesn  t exist]
[pending, page alias exists]TDH.IMPORT.MEM(REMIGRATE)
 
Figure 8.12:  Partial L2 SEPT Leaf Entry State Diagram for L2 Page Mapping Import During the In -Order Phase  
To import a page that has L2 pages mappings, the host VMM on the destination platform must have built the L2 SEPT for 10 
the applicable L2 VMs, using TDH.MEM.SEPT.ADD, down to the proper page mapping level.  
8.5.2.  Out-of-Order import  Phase  
 Overview  of Out-of-Order Import  
When the out -of-order import phase begins, any page s that have been imported are designed  to be up to date.  A  page 
may only be imported if its GPA mapping does not exist yet (SEPT entry’s state is FREE).  An import attempt of a page that 15 
has been imported before during the out -of-order phase is dropped but not considered an error; this is normally the 
result of the same page being migrated on a high -priority queue.  Source memory state is immutable, so o rdering is not 
required.   TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 68 of 71 
FREE
pageMAPPED
TD
PENDING
TD acceptanceTDH.IMPORT.MEM(MIGRATE)
[mapped]
[pending]TDH.MEM.PAGE.DEMOTE /
NL_MAPPEDTDH.MEM.PAGE.PROMOTE[non -leaf NL_MAPPED entry] /
Entry becomes leaf, MAPPEDFrom Non -Leaf Entry 
New leaf, MAPPED
NL_MAPPEDTDH.MEM.PAGE.DEMOTE /
New leaf, PENDINGTo Non -Leaf 
Diagram
To Non -Leaf 
DiagramREMOVED
page.  If OP_STATE is 
not LIVE_IMPORT, 
equivalent to FREE.TDH.MEM.PAGE.REMOVEBLOCKED
PENDING_BLOCKED
Page is pending but 
guest TD acceptance 
is blockedTDH.MEM.RANGE.BLOCKTDH.MEM.PAGE.REMOVETDH.IMPORT.MEM(MIGRATE)
[mapped, 
previous CANCEL during in -order import]
[pending, 
 
Figure 8.13:  Partial SEPT Entry State Diagram for Page Out -of-Order Import Phase  
 Memory Management During Out -of-Order Import  
8.5.2.2.1.  TLB Tracking  During Out -of-Order Import  
During the out -of-order import phase, TLB tracking is required in the LIVE_IMPORT OP_STATE, since the TD may be 5 
running on the destination platform.  
8.5.2.2.2.  Secure EPT Management  During Out -of-Order Import  
Addition and removal of Secure EPT pages are allowed during the out -of-order phase – they are required as part of 
building the TD on the destination platform.  
An SEPT page can only be removed if all its entries are FREE; specifically, it can’t be removed if any entry state is 10 
REMOVED.  
8.5.2.2.3.  Page Addition  During Out -of-Order Import  
TDH.MEM.PAGE.ADD is prohibited  but TDH.MEM.PAGE.AUG is allowed in the LIVE_IMPORT OP_STATE.  
If a page was added locally  (TDH.MEM.PAGE.AUG),  this is equivalent to the VMM removing a page without coordinating 
with the TD, then adding a new page.  The TD should not accept (TDG.MEM.PAGE.ACCEPT)  such a page since from its 15 
point of view this is a page that already existed in its GPA space .  The secure EPT entry state for the locally added page is 
PENDING, and if a page is imported to the same GPA, import will fail.   
8.5.2.2.4.  Promotion and Demotion  During Out -of-Order Import  
Page promotion and demotion are allowed during the out -of-order phase.  TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 69 of 71 
Section 2:  TD Migration Architecture Specification  8.5.2.2.5.  Page Removal  During Out -of-Order Import  
Page removal (TDH.MEM.PAGE.REMOVE) is allowed during the out -of-order import phase .  However, the page’s SEPT 
entry is not marked as FREE  when the page is removed .  Instead, the SEPT entry  state is set to REMOVED.  The REMOVED 
state is equivalent to the FREE state, except for the following limitations that apply as long as the TD is in the LIVE_IMPORT 
OP_STATE:  5 
• Page import is not allowed  to this GPA.  
• Removal of the parent SEPT page is not allowed.  
The above limitations prevent the following attack scenario:  
1. The host VMM creates a copy of a migration bundle and saves it for later.  
2. The host VMM import a page using the migration bundle.  10 
3. The TD runs and modifies the imported page content.  
4. The host VMM removes the page.  
5. The host VMM attempt to re -import the page using the saved copy of the migration bundle.  
If the host VMM succeeded in re -importing the page, it would have rolled back the page content.  Remember we do not 
enforce order of import during the out -of-order phase.  But setting the SEPT entry state to REMOVED when the page was 15 
removed prevents this attack.  
8.5.2.2.6.  Page Relocation  During Out -of-Order Import  
Page relocation is supported at any stage without any changes.  
 Importing  L2 Page Mappings  During Out -of-Order Import  
During out -of-order import, L2 page mappings  may be created as part of a page import.  L2 SEPT leaf entries don’t need 20 
the REMOVED state; thus, the L2 state transitions are very simple.  
L2_FREE
to L2 VMTDH.IMPORT.MEM(MIGRATE)
 
Figure 8.14:  L2 SEPT Leaf Entry State Diagram for Page Out -of-Order Import Phase Partial  
8.5.3.  In-Place Import  
In-place import repurposes the physical pages holding the imported data as private memory pages that hold the 25

L2_FREE
 
In-place import repurposes the physical pages holding the imported data as private memory pages that hold the 25 
decrypted data.  This saves the host VMM on the destination platform  the need to allocate memory for the import ed 
data, at the cost of a small fixed -sized intermediate buffer that needs to be held by Intel TDX Module , and some other 
complications.  In -place import may be selected for each page imported for the first time, or following a previous CANCEL, 
but not fo r re-import of a new version of a previously imported  page.  
8.6. Secure EPT Concurrency Considerations  30 
Note:  OP_STATE related concurrency considerations are described in 6.2.6 . TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 70 of 71 
Section 2:  TD Migration Architecture Specification  To support high performance migration, memory migration interface functions are allowed to run concurrently on 
multiple LPs.  However, no concurrent operation is allowed on any single Secure EPT entry.  Interface functions that work 
on specific Secure EPT entries acquire an exclusive lock to that entry.  
8.7. Memory Migration  Interface Functions  
This section provides a short overview of the memory migration  interface functions.  A detailed specification is provided 5 
in [TDX Module ABI Spec ]. 
8.7.1.  TDH.EXPORT.BLOCKW  
TDH.EXPORT.BLOCKW blocks a list of 4KB pages  for writing, as a preparation for export.   The function records the current 
value of TD_EPOCH in TDCS.BW_EPOCH.  
Inputs  10 
• GPA list  
• Export session is in the in -order phase and the TD has not been paused yet  
See the [TDX Module ABI Spec].  
8.7.2.  TDH.EXPORT.MEM  
TDH.EXPORT.MEM  exports , re-exports or sends an export cancellation request for  a list of 4KB pages .  A page may be 
PENDING  (in which case no data is exported).  
Inputs  20 
• GPA list  
• MBMD HPA  
• Migration buffers list  HPA  
• For a partitioned TD, a page attributes list HPA  25 
• Page MAC list HPA  
• Export session is in progress  
Operation  30 
8.7.3.  TDH.EXPORT.RESTORE  
TDH.EXPORT.RESTORE restores a list of 4KB pages after an export abort.  
Inputs  
• GPA list  
• Export session is not in progress  
Operation  
See the [TDX Module ABI Spec].  40 TDX Module TD Migration Spec  Section 2:   TD Migration Architecture Specification  348550 -003  
November 2023   . Page 71 of 71 
Section 2:  TD Migration Architecture Specification  8.7.4.  TDH.EXPORT.UNBLOCKW  
TDH.EXPORT.UNBLOCKW unblocks a 4KB page that has been blocked for writing.  
Inputs  
• Source GPA and level  5 
• Either an export session is in progress but committed export phase has not begun, or the TD is allowed to run  
Operation  
8.7.5.  TDH.IMPORT.MEM  10 
TDH.IMPORT.MEM exports, re -imports or cancels a previous import for a list of 4KB pages.  
Inputs  
• GPA list  HPA  
• For partitioned TDs, page at tributes list HPA  15 
• MBMD HPA  
• Migration buffers list HPA  
• New TD pages list HPA  20 
• Import session is in progress  
Operation  
See the [TDX Module ABI Spec].   
 
Guest  Hypervisor Communication 
Interface (GHCI) for Intel® Trust Domain 
Extensions (Intel® TDX)  1.5 
348552 -004US  
March  202 3 
 
Ref. # 348552 -004US  i Disclaimers  
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others.  
  Guest -Hypervisor  Communication Interface (GHCI) Specification for Intel® TDX  1.5 
About this Document  
Ref. # 348552 -004US  ii Table of Contents  
Disc laimers  ................................ ................................ ................................ ................................ ................................ .... i 
1 About this Document  ................................ ................................ ................................ ................................ ..................  2 
1.1 SCOPE OF THIS DOCUMENT  ................................ ................................ ................................ ................................ ........................ 2 
1.2 DOCUMENT ORGANIZATION  ................................ ................................ ................................ ................................ ...................... 2 
1.3 GLOSSARY  ................................ ................................ ................................ ................................ ................................ ..................... 3 
1.4 REFERENCES  ................................ ................................ ................................ ................................ ................................ ................. 4 
2 TD -VMM Communication  ................................ ................................ ................................ ................................ .........  6 
2.1 RECAP OF INTEL ® TRUST DOMAIN EXTENSIONS (INTEL ® TDX)  ................................ ................................ .................... 6 
2.2 TD-VMM -COMMUNICATION OVERVIEW  ................................ ................................ ................................ .............................. 7 
2.3 VIRTUALIZATION EXCEPTION (#VE)  ................................ ................................ ................................ ................................ .......8 
2.4 TDCALL  AND SEAMCALL  INSTRUCTION  ................................ ................................ ................................ ........................... 9 
2.4.1 TDCALL [TDG.VP.VMCALL] leaf  ................................ ................................ ................................ ................................ 9 
3 TDG.VP.VMCALL Interface  ................................ ................................ ................................ ................................ ... 15 
3.1 TDG.VP.VMCALL<G ETTDVMCALLINFO> ................................ ................................ ................................ .....................  15 
3.2 TDG.VP.VMCALL<M APGPA>  ................................ ................................ ................................ ................................ ..........  16 
3.3 TDG.VP.VMCALL<G ETQUOTE > ................................ ................................ ................................ ................................ ....... 18 
3.4 TDG.VP.VMCALL<R EPORT FATAL ERROR > ................................ ................................ ................................ ....................  21 
3.5 TDG.VP.VMCALL<S ETUP EVENT NOTIFY INTERRUPT > ................................ ................................ ................................  23 
3.6 TDG.VP.VMCALL<I NSTRUCTION .CPUID>  ................................ ................................ ................................ ....................  23

3.6 TDG.VP.VMCALL<I NSTRUCTION .CPUID>  ................................ ................................ ................................ ....................  23 
3.7 TDG.VP.VMCALL<#VE.R EQUEST MMIO>  ................................ ................................ ................................ ....................  24 
3.8 TDG.VP.VMCALL<I NSTRUCTION .HLT>  ................................ ................................ ................................ .........................  26 
3.9 TDG.VP.VMCALL<I NSTRUCTION .IO>  ................................ ................................ ................................ .............................  27 
3.10  TDG.VP.VMCALL<I NSTRUCTION .RDMSR>  ................................ ................................ ................................ ...............  27 
3.11  TDG.VP.VMCALL<I NSTRUCTION .WRMSR>  ................................ ................................ ................................ ..............  28 
3.12  TDG.VP.VMCALL<I NSTRUCTION .WBINVD>  ................................ ................................ ................................ ............  29 
3.13  TDG.VP.VMCALL<I NSTRUCTION .PCONFIG>  ................................ ................................ ................................ ............  29 
3.14  TDG.VP.VMCALL  <SERVICE > ................................ ................................ ................................ ................................ .........  30 
3.14.1 TDG.VP.VMCALL <Service.Query> ................................ ................................ ................................ .......................  35 
3.14.2 TDG.VP.VMCALL <Service.MigTD>  ................................ ................................ ................................ .....................  35 
4 TD -Guest -Firmware Interfaces  ................................ ................................ ................................ ................................ . 45 
4.1 ACPI  MADT  MULTIPROCESSOR WAKEUP TABLE  ................................ ................................ ................................ ...........  45 
4.2 MEMORY MAP ................................ ................................ ................................ ................................ ................................ ...........  45 Guest -Hypervisor  Communication Interface (GHCI) Specification for Intel® TDX  1.5 
Ref. # 348552 -004US  iii 4.3 TD MEASUREMENT  ................................ ................................ ................................ ................................ ................................ .. 48 
4.3.1 TCG -Platform -Event Log  ................................ ................................ ................................ ................................ ..............  48 
4.3.2 EFI_CC_MEASUREMENT_PROTOCOL  ................................ ................................ ................................ ................  48 
4.3.3 CC -Event Log  ................................ ................................ ................................ ................................ ................................ ... 48 
4.4 STORAGE -VOLUME -KEY DATA ................................ ................................ ................................ ................................ .............  48 
5 TD -VMM -Communication Scenarios  ................................ ................................ ................................ ......................  50 
5.1 REQUESTING IPIS ................................ ................................ ................................ ................................ ................................ ...... 50 
5.2 TD-MEMORY CONVERSION AND MEMORY BALLOONING  ................................ ................................ ................................ . 50 
5.3 PARAVIRTUALIZED IO ................................ ................................ ................................ ................................ .............................  51 
5.4 TD ATTESTATION  ................................ ................................ ................................ ................................ ................................ ...... 51 
5.5 SERVIC E TD BINDING  ................................ ................................ ................................ ................................ ..............................  53 
5.6 TD LIVE MIGRATION  ................................ ................................ ................................ ................................ ...............................  54 
5.6.1 Pre -Migration  ................................ ................................ ................................ ................................ ................................ ... 55 
5.6.2 Reservation and Session Setup  ................................ ................................ ................................ ................................ ..... 55 
5.6.3 Iterative Pre -Copy of Memory State  ................................ ................................ ................................ ...........................  57 
5.6.4 Source TD Stop and Final Non -Memory State Migrat ion ................................ ................................ .....................  58 
5.6.5 Commitment  ................................ ................................ ................................ ................................ ................................ ...... 59 
5.6.6 Post -Copy of Memory State  ................................ ................................ ................................ ................................ ..........  59 
 
 Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  2 1 About this Document  
1.1 Scope of this Document  
Trust Domains (TDs) are used to enable confidential  host ing of  VM workloads that are 
hardware -isolated from the hosting VMM and service OS environments .  The Intel ® Trust 
Domain Extensions (Intel ® TDX ) architecture enables  isolation of the TD -CPU context and 
memory  from the hosting environment.   
This document specifies the guest (TD) to host (VMM) communication interface that will be 
utilize d for the paravirtualization interface between the TD and the VMM.  This approach helps  
the Intel TDX -architecture prevent the VMM from accessing any TD runtime state.  The TD 
must therefore volunteer information to access IO services, enumerate model -spec ific CPU 
capabilities  and measurement services , and provide feedback to the VMM on guest -OS-
triggered actions such as virtual -IPIs or shutdowns.  
 For each operation with in this interface, the recommended actions are described for the host 
VMM (informative) .  The TD and the VMM are designed to use the subfunctions, which are 
normative and described in this document.  
This document is a work in progress and is subject to change based on customer 
feedback and internal analysis.  This document does not imply any product 
commitment from Intel to anything in terms of features and/or behaviors.  
1.2 Document Organization  
Section 2  describes a general structure/ABI of the instruction TDCALL with the 
TDG.VP.VMCALL leaf used  for passing information to the VMM and receiving information from 
the VMM.   
Section 3  describes the sub -leaves of TDCALL [TDG.VP.VMCALL] that define the Application 
Binary Interface (ABI) between the TD and the  VMM for specific operations.  
Section 4  describes example flows for the main scenarios.  
Section 5  describes TD-VMM -Communication Scenarios . 
  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  3 1.3 Glossary  
Tabl e 1-1:  Intel TDX  Glossary  
Acronym  Full Name  Description  
TME  Total Memory Encryption  An SoC memory encryption/decryption engine used to encrypt 
memory contents exposed externally from the S oC using an 
ephemeral , platform key.  Memory is decrypted using the TME when 
memory contents are brought into the CPU caches.  
MKTME  Multi -Key TME  This So C capability adds support to the TME to allow software to use 
separate (one or more) keys for encryption of volatile - or persistent -
memory encryption.  When used with Intel TDX, it  can provide 
confidentiality via separate keys for memory -used TDs.  MKTME may 
be used with and without Intel TDX extensions.1 
 TD Trust Domain  Software operating in a CPU mode designed to exclude the 
host/VMM software and untrusted , platform devices from the 
operational TCB for confidentiality.  The operational TCB for a TD 
includes the CPU, the TD OS, and TD applications.  A TD’s resources 
are managed by a n Intel TDX -aware  host VMM , but its state 
protection is managed by the CPU and  is not accessible to the host 
software.  
Intel TDX  Intel TDX Architecture  Intel -CPU -instruction -set-architecture extensions to enable host 
VMM to host Trust Domains . 
Intel TDX 
module  Intel Trust Domain

software.  
Intel TDX 
module  Intel Trust Domain 
Extensions  module  Intel TDX module  is a CPU -measured software module that uses the 
instruction -set architecture for Intel TDX to  help  enforce security 
properties for hosting TDs on an Intel TDX platform .  Intel TDX 
module  exposes the Guest -Host -Communication Interface that TDs 
use to communicate with the Intel TDX module  and the host VMM.  
HKID  Host Key ID  When MKTME is activated, HKID is a key identifier for an encryption 
key used by one or more memory controller s on the platform.  When 
Intel TD X is active, the HKID space can be  partitioned into a CPU -
enforced space (for TDs) and a VMM -enforced space (for legacy 
VMs).  
- TD-Private Memory 
(Access)  TD-Private Memory can be  encrypted by the CPU using the TD -
ephemeral key (or in the future with additional , TD private keys).  
- TD-Shared Memory 
(Access)  TD-Shared Memory is  designed to be  accessible by the TD and the 
host software (and/or other TDs).  TD-Shared Memory us es MKTME 
keys managed by the VMM  for encryption . 
TDVPS  TD Virtual  Processor 
Structure  TD per -VCPU state maintained in protected memory by the Intel 
TDX . 
 
1 In this document, the term “MKTME” means both the feature and the encryption engine itself.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  4 Acronym  Full Name  Description  
TDCS  Trust  Domain  Control 
Structure  Multi -page -control structure for a TD.  By design, TDCS is encrypted 
with the TD’s ephemeral , private key , its contents are not 
arch itectural, and its location in memory is known to the VMM.  
1.4 References  
Table 1-2: Technical Documents Referenced  
# Reference Document  Version & Date  
1 Intel® 64 and IA -32 Architecture Software Developer Manual  May 2020  
2 Intel® Trust Domain Extensions  CPU  architecture specification  May 2021  
3 Intel® Trust Domain Extensions module  1.5 base  architecture 
specification  March  202 2 
4 Intel® Multi -key Total Memory Encryption (MK -TME) specification  April 2021  
5 ACPI specification , version 6. 5 August  202 2 
6 UEFI specification , version 2.10 August  202 2 
7 Intel® Trust Domain Extensions module 1.5 ABI reference 
specification  March  202 3 
8 Intel® Trust Domain Extensions module 1.5 architecture 
specification : TD Migration  March 202 3 
 
When specifying requirements or definitions, the level of commitment is specified following 
the convention of RFC 2119:  Key words for use in RFCs to indicate Requirement Levels , as 
described in the foll owing table:  
Table 1-3: Requirement and Definition Commitment Levels  
Keyword  Description  
Must  “Must ," “Required ,” or “Shall”  mean s that the definition is an absolute  
requirement of the specification.  
Must Not  “Must Not” or “Shall Not”  means that the definition is an absolute prohibition of  
the specification.  
Should  “Should” or “Recommended”  means that there may exist valid reasons in  
particular circumstances to ignore a particular item, but the full implications must be  
understood and carefully weighed before choosing a different course.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  5 Should Not  “Should Not” or the phrase “Not Recommended”  means that there may exist valid 
reasons in  particular circumstances when the particular behavior is acceptable or even 
useful, but the full  implications should be understood and the case must be carefully 
weighed before  implementing any behavior describe d with this label.  
May  “May” or “Optional”  means that an item is discretionary.   An implementation  
may choose to include the item, while another may omit the same item because of 
various  reasons.  
TD-VMM Communication  
Ref. # 348552 -004US  6 2 TD -VMM Communication  
2.1 Recap of Intel® Trust Domain Extensions ( Intel® TDX ) 
Intel ® Trust Domain Extensions ( Intel ® TDX ) is an Intel technology that extends Virtual 
Machines Extensions (VMX)  and Multi -Key Total Memory Encryption (MKTME)  with a new kind 
of virtual machine guest called Trust Domain (TD) .  A TD  is designed to run in a CPU mode 
that protects the confidentiality of TD memory contents and the TD’s  CPU state from other 
software, including the hosting Virtual -Machine Monitor (VM M), unless explicitly shared by the 
TD itself.  
The Intel TDX  module  uses  the instruction -set architecture for Intel TDX  and the MKTME  
engine  in the SOC to help serve as an intermediary between the host VMM and the guest TDs.  
The operation of this module is described in detail in  the Intel TDX -module  specification [ 3].  
The Intel TDX module  exposes the Guest -Host -Communication Interface (GHCI) for Intel 
TDX  (this  specification) that TDs must  use to communicate with both the Intel TDX module  
and the host VMM.  
As shown in the diagram below, a n Intel TDX -aware  host VMM  can launch and manage both 
guest TDs and legacy -guest  VMs.  The host  VMM can maintain legacy functionality  from the 
legacy VMs’ perspective ; the aim is for the host VMM to be  restrict ed only wit h regard to the 
TDs it manages . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  7 
5Intel TDX aware Host VMMHost VMM managed access 
control, enhanced with MKTMEIntel TDX Module managed access control,  
leveraging MKTME and Secure EPT
(uses Intel TDX ISA)Trust Domain
Intel TDX
Drivers
Intel
TDX Module
Host-Side
Intel TDX
Drivers
Intel TDX
Guest -Host Comm. InterfaceLegacy VM
Drivers
Platform (Cores, Caches, Devices etc.)Intel TDX
Guest -Host Comm. Interface 
Figure 2-1: Components of Intel ® Trust  Doma in Extension s 
2.2 TD-VMM -Communication Overview  
TD-VMM communication can occur via either asynchronous or synchronous (instruction) VM  
exits .  In response to synchronous (instruction) VM exits, Intel TDX [3] is designed to generate 
a Virtualization Exception (#VE)  [1] for instructions the TD would be  disallowed to invoke.  The 
TD-guest software may respond by using the Intel TDX -provided information directly and/or 
after further decoding of the instruction  that caused the #VE .   
The TD response must occur  via a TDCALL instruction [2] requesting that the host VMM 
provide (untrusted) services.  Ultimately, the  VMM ’s goal is  to 1) receive the service request via 
a SEAMRET invoked by the Intel TDX module , 2) complete the service requested , and 3) 
respond to the TD via SEAMCALL[TD H.VP. ENTER] to re -enter the TD.   
This document describes the mechanisms and ABI for this interaction  in various expected 
scenarios.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  8 
VMM (host)TDCALL
SEAMRETSEAMCALL
Intel TDX ModuleTD (guest)
VMRESUMEVMEXIT
(due to 
instruction)#VE
handler
Guest -Host Communication 
Interface for Intel® TDX 
Figure 2-2: TD Guest -Host communication  
 
Section 2 of this document describes the Virtualization Exception ( #VE) for Intel TDX , and 
subsequent sections describe the normative TDCALL leaves intended to get the VE 
information and request services from the host VMM.  Other  scenarios  may cause 
asynchronous VM exits to the host VMM (via SEAMRET) ; for those  scenarios , please refer to 
the Intel TDX  module  specification  [3]. 
Section 3 of this document describes the reference/informative TDCALL[ TDG.VP. VMCALL ] 
interface sub-leaves  intend ed to request services from the host VMM.   
Section 4 describes the scenarios where TD -VMM communication interfaces described in this 
specification can be applied.  
2.3 Virtualization Exception (#VE)  
Intel TDX can cause #VE to be reported to the guest -TD software in cases of disallowed 
instruction execution, such  as IO accesses.  
The goal is for the Intel TDX module , in handling #VE delivery, to follow the architectural #VE 
handling for nested #VE, as described in Intel -SDM Chapter 25.5.6.3 (Delivery of Virtualization 
Exceptions ). The TD OS should avoid instructio ns that may cause #VE in the #VE handler.  
For detailed information about virtualization exception in Intel TDX, please refer to Intel TDX 
module  Architecture specification.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  9 2.4 TDCALL  and SEAMCALL  instruction  
TDCALL is the instruction used by the guest TD soft ware (in TDX non -root mode) to invoke 
guest -side TDX functions. For detailed information about the TDCALL instruction, please refer 
to the Intel TDX module  Architecture specification.

to the Intel TDX module  Architecture specification.  
SEAMCALL is the instruction used by the host VMM to invoke host -side TDX  functions. For 
detailed information about the SEAMCALL  instruction, please refer to  the Intel TDX module  
Architecture specification.  
2.4.1  TDCALL [ TDG.VP.VMCALL ] leaf  
TDG.VP.VMCALL  is a leaf function 0 for TDCALL .  It helps  invoke services from the host VMM .  
The input operands for this leaf are programmed as defined below:   
Ref. # 348552 -004US  10 Table 2-1: TDG.VP.VMCALL -Input Operands  
Operand  Description  
RAX  TDCALL instruction leaf number per Intel TDX module Specification 
(0 - TDG.VP.VMCALL).  
RCX  A bitmap that controls which part of the guest TD GPR and XMM 
state is passed as -is to the VMM and back. Please refer to Intel TDX 
module Specification TDG.VP.VMCA LL. 
R10  Set to 0 indicates that TDG.VP.VMCALL  leaf used in R11 is defined 
in this specification.  
All other values 0x1 to 0xFFFFFFFFFFFFFFFF indicate 
TDG.VP.VMCALL  is vendor -specific (both R10 and R11) . 
R11  See each TDG.VP.VMCALL  sub-function if R10 is 0. See table 2 -3 
and table 2 -4.  
RBX, RDX, RBP , RDI, RSI, R 8, 
R9, R12 -R15  See each TDG.VP.VMCALL  sub-function for which registers must be 
used to pass values to the VMM (by setting RCX bits specified 
above) . 
Note:  Please be aware t hat RBP is usually used as a frame pointer 
according to the C language calling convention. The software 
should not use RBP as an input/output parameter and should clear 
BIT5 (RBP) in the GPR mask in RCX. The API definition in this 
document shall not use RB P. 
XMM0 –XMM15  If the corresponding bit in RCX is set to 1, the register value passed 
as-is to the host VMM on SEAMRET. Else, the register value is not 
used as an input and is preserved.  
Other  Unmodified  
 
Ref. # 348552 -004US  11 Table 2-2: TDG.VP.VMCALL -Output Operands  
RAX  TDCALL instruction return code.  Always returns Intel 
TDX_SUCCESS (0).  
RCX  Unmodified . 
R10  TDG.VP.VMCALL sub -function return value. See table 2 -6. 
0 – if no error.  
Non 0 – if error happens.  The error code is command specific.  
R11  See each TDG.VP.VMCALL sub -function.  
RBX, RDX, RBP, RDI, RSI, R8 , R9, 
R12-R15 See each TDG.VP.VMCALL sub -function  for which registers must 
be used to pass values from  the VMM (by setting RCX bits 
specified above) . 
Note:  Please be aware that RBP is usually used as a frame 
pointer according to the C language calling convention. The 
software should not use RBP as an inp ut/output parameter and 
should clear BIT5 (RBP) in the GPR mask in RCX. The API 
definition in this document shall not use RBP.  
XMM0 –XMM15  If the corresponding bit in RCX is set to 1, the register value 
passed as -is from the host VMM’s SEAMCALL(TDH.VP.ENTER) 
input. Else, the register value is unmodified.  
TDG.VP.VMCALL -Intel TDX  paravirtualization s ub-functions  (specified in R11  when R10 is set to 0) 
Table 2-3: TDG.VP.VMCALL  codes  
Sub -Function Number  Sub -Function Name  
0x10000  GetTdVmCallInfo  
0x1000 1 Map GPA  
0x10002  GetQuote , e.g., used for sending TDREPORT _STRUCT  to VMM to 
request a TD Quote  
0x10003  ReportFatalError  
0x10004  SetupEventNotifyInterrupt  
0x10005  Service  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
TD-VMM Communicatio n 
Ref. # 348552 -004US  12  
Ref. # 348552 -004US  13 Table 2-4: TDG.VP.VMCALL -Instruction -execution sub -functions  
Sub-Function Number  
Bits 15:0  Sub-Function Name  
10 Instruction.CPUID  
12 Instruction.HLT  
30 Instruction.IO  
31 Instruction.RDMSR  
32 Instruction.WRMSR  
48 #VE.RequestMMIO  
54 Instruction.WBINVD  
65 Instruction.PCONFIG  
 
Completion -Status Codes  
Table 2-5: TDCALL[ TDG.VP.VMCALL ]-Completion -Status Codes (Returned in RAX)  
Completion -Status  
Code  Value  Description  
TDX_SUCCESS  See Intel TDX -Architecture 
specification [3] for Function 
Completion Status Code.  TDCALL is successful  
TDX _OPERAND_INVALID  Illegal leaf number  
Other  See individual leaf functions . 
 
Ref. # 348552 -004US  14 Table 2-6: TDCALL[TDG.VP.VMCALL] - Sub-function Completion -Status Codes  
(specified in R10 as output when R10 is set to 0 as input ) 
Completion -Status  Code  Value  Description  
TDG.VP.VMCALL_SUCCESS  0x0 TDCALL[TDG.VP.VMCALL] sub -
function invocation was 
successful  
TDG.VP.VMCALL_RETRY  0x1 TDCALL[TDG.VP.VMCALL] sub -
function invocation must be 
retried  
TDG.VP.VMCALL _OPERAND_INVALID  0x80000000 00000000  Invalid operand to 
TDG.VP.VMCALL sub -function  
TDG.VP.VMCALL_GPA_INUSE  0x80000000 00000001  GPA already mapped  
TDG.VP.VMCALL_ALIGN_ERROR  0x80000000 00000002  Operand (address) alignment 
error  
TDG.VP.VMCALL Interface  
Ref. # 348552 -004US  15 3 TDG.VP.VMCALL  Interface  
From the perspective of the host VMM, TDCALL [ TDG.VP.VMCALL ] is a trap -like, VM exit into 
the host VMM , reported via the SEAMRET instruction flow .   
By design, a fter the SEAMRET, t he host VMM services the request specified in the parameters 
passed by the TD during the TDG.VP.VMCALL  (that are passed via SEAMRET to the VMM) , then  
resumes the TD via a SEAMCALL [TD H.VP. ENTER] invocation.  
Refer to  the Intel  TDX  CPU Architecture specification [2] for details of the SEAMCALL and 
SEAMRET instruction s.  This chapter describe s the designed sub-functions of the TDCALL  
[TDG.VP.VMCALL ] interface between the TD and the VMM.  
3.1 TDG.VP.VMCALL <GetTdVmCallInfo > 
GetTdVmCallInfo  TDG.VP.VMCALL  is used  to help request the host VMM enumerate which 
TDG.VP.VMCALL s are supported.   This leaf is reserved for enumerating capabilities defined in 
this specification.  VMMs may provide alternate enumeration sch emes using vendor -specific  
TDG.VP.VMCALL  namespace , as defined in 2.4.1 . 
Table 3-1: TDG.VP.VMCALL < GetTdVmCallInfo >-Input Operands  
R11  TDG.VP.VMCALL < GetTdVmCallInfo > sub -function per Table 2 -3. 
R12  Leaf to enumerate TDG.VP.VMCALL  functionality from this specification 
supported by the host.  
R12 must be set to 0, and successful execution of this TDG.VP.VMCALL  is 
meant to  indicate all TDG.VP.VMCALL s defined in this specification are 
supported  by the host VMM .  This register is reserv ed to extend 
TDG.VP.VMCALL  enumeration in future versions . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  16 Table 3-2: TDG.VP.VMCALL < GetTdVmCallInfo >-Output Operands  
R10  TDG.VP.VMCALL -instruction -return code.  
R11  Leaf -specific output  (when R12 is 0, will be returned as 0). 
R12  Leaf -specific output (when R12 is 0, will be returned as 0) . 
R13  Leaf -specific output (when R12 is 0, will be returned as 0) . 
R14  Leaf -specific output (when R12 is 0, will be returned as 0) . 
Table 3-3: TDG.VP.VMCALL < GetTdVmCallInfo > Status Codes  
Error Code  Value  Description  
TDG.VP.VMCALL _SUCCE
SS See value s in 
Table 2 -6 TDG.VP.VMCALL  is successful.  The TD is free to 
use the GPA as a shared , memory page.  
3.2 TDG.VP.VMCALL <Map GPA > 
Map GPA TDG.VP.VMCALL  is used to help  request the host  VMM to map a GPA range as private  
or shared -memory mappings . This API may also be used to convert page mappings from 
private to shared .  The GPA range passed in this operation  can indicate if the mapping is 
requested for a shared or private memory via the GPA.Shared bit in the start address.   
For example, to exchange data with the VMM, the TD may use this TDG.VP.VMCALL  to request 
that a GPA range be mapped as a shared memory (for example , for a paravirtualized IO)  via the 
shared EPT.  If the GPA (range) was already mapped as an active , private page, t he host VMM 
may remove the private page from the TD by following the “Removing TD Private Pages” 
seque nce in the  Intel TDX -module  specification [3 ] to safely block the mapping (s), flush the 
TLB and cache , and remove the mapping (s).  The VMM can then map the specified GPA (range) 
in the shared -EPT structure and allow the TD to access the page (s) as a shared  GPA  (range) . 
If the Start GPA specified is a private GPA (GPA.S bit is clear ), this MapGPA TDG.VP.VMCALL  
can be used to help request the host VMM map the specific , private page (s) (which mapping 
may involve converting the backing -physical page from a shared page to a private page) .  As 
intended i n this case, t he VMM must unmap the GPA from the shared -EPT region and

intended i n this case, t he VMM must unmap the GPA from the shared -EPT region and 
invalidate the TLB and caches for the TD VCPUs , to help ensure that no stale mappings exist.  
Similarly, if the shared page was assigned to  any device for use with IO, then the VMM should 
invalidate the IOTLB and purge any pending IO transactions (e.g. by queuing a wait descriptor) 
to remove stale mappings on the IO side. Then, the content of all data caches should be 
flushed.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  17 The aim is for the VMM to then follow the sequence specified in “Dynamically Adding TD 
Private Pages during TD Run Time” in the Intel TDX -module  specification [3 ] to use 
TDH.MEM.PAGE. AUG to add the GPA (s) to the TD as pending , private mapping (s) in the secure -
EPT.  When the VMM responds to this TDG.VP.VMCALL  with success, the  goal is for the  TD to 
execute TDCALL[ TDG.MEM.PAGE.ACCEPT ] to complete the process to make the page (s) 
usable as a private GPA inside the TD.  
Upon  MapGPA  from shared to priva te, the VMM needs to check if the page is mapped by the 
IOMMU page table.  If direct I/O is already enabled and the page is mapped,  MapGPA  should 
fail. This is equivalent to removing a page from a (legacy) guest with direct I/O enabled; the 
pages need to be  pinned there.  If the VMM provides  a virtual IOMMU (vIOMMU)  or cooperative 
IOMMU (coIOMMU), then the guest can indicate that it is not using that memory for DMA. In 
that case,  MapGPA  can: 1) Check that page is not pinned by  vIOMMU ; 2) Check that the page i s 
not mapped in physical IOMMU. If 1 and 2 succeed, then  unmap  and remap it.  
Table 3-4: TDG.VP.VMCALL <MapGPA> -Input Operands  
R11  TDG.VP.VMCALL <MapGPA > sub function  per Table 2 -3. 
R12  4KB -aligned Start GPA of address range (Shared bit may be set or 
clear to indicate if a shared - or private -page mapping is desired) . 
Shared -bit position is indicated by the GPA width [Guest -Physical -
Address -Width -execution control is initialized by the host VMM for the 
TD during TD H.VP. INIT ]. 
R13 Size of GPA region to be mapped (must be a multiple of 4KB ). 
Table 3-5: TDG.VP.VMCALL <MapGPA > Output Operands  
R11  GPA at which MapGPA failed  (see failure or retry reason in 
TDG.VP.VMCALL specific status code.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  18 Table 3-6: TDG.VP.VMCALL <MapGPA >-Status Codes  
TDG.VP.VMCALL_SUCCESS  See values in 
Table 2 -6 TDG.VP.VMCALL is successful.  The TD 
is free to use the GPA (range) specified . 
TDG.VP.VMCALL_RETRY  TD must retry this operation for the 
pages in the region starting at the GPA 
specified in R11.  
TDG.VP.VMCALL_INVALID_OPERAND  Invalid operand – for example, the GPA 
address is invalid (beyond GPAW) . 
TDG.VP.VMCALL_GPA_INUSE  GPA is already in use by the TD, for e.g., 
GPA used for hosting memory dedicated 
for IO. R11 specifies which GPA in the 
range specified was in use.  
TDG.VP.VMCALL_ALIGN_ERROR  Alignment error for size or Start GPA.  
3.3 TDG.VP.VMCALL <GetQuote > 
GetQuote  TDG.VP.VMCALL  is a doorbell -like interface  used  to help  send a message to the 
host  VMM to queue operations that tend to be long -running operations.  GetQuote is 
designed to invoke a  request to generate a TD-Quote signing by a service hosting TD-Quoting 
Enclave operating in the host environment  for a TD Report  passed as a parameter  by the TD .  
TDREPORT _STRUCT  is a m emory  operand  intend ed to be  sent via the GetQuote  
TDG.VP.VMCALL  to indicate the asynchronous service requested .  
For the GetQuote  operation , the goal is for the TDREPORT_STRUCT to be received by the TD 
via a prior TDCALL[ TDG.MR.REPORT ] in a buffer and placed in a shared -GPA space passed to 
the VMM  as an operand in the GetQuote  TDG.VP.VMCALL .  In the case of this operation, the 
VMM can access the TDREPORT_STRUCT , queue the operation for a service hosting  TD-
Quoting enclave , and, when completed, retur n the Quote via the same , shared -memory area .   
For the TD to invoke the TDG.VP.VMCALL <GetQuote >, the host VMM can signal the event 
completion to the TD OS via a notification interrupt t he host VMM  injects into the TD (using 
the Event -notification vector r egistered via the SetupEventNotifyInterrupt TDG.VP.VMCALL ). Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  19 Table 3-7: TDG.VP.VMCALL < GetQuote  >-Input Operands  
R11  TDG.VP.VMCALL < GetQuote  > sub -function  per Table 2 -3. 
R12  Shared GPA as inpu t – the memory contains a TDREPORT_STRUCT.  
The same buffer is used as output – the memory contains a TD Quote.  
R13  Size of shared GPA.  The size must be 4KB -aligned.  
Table 3-8: TDG.VP.VMCALL < GetQuote  >-Output Operands  
R10  TDG.VP.VMCALL  return code.  
Table 3-9: TDG.VP.VMCALL < GetQuote  >-Status Codes  
TDG.VP.VMCALL_SUCCESS  See values in Table 2 -6 TDG.VP.VMCALL is successful ly 
received by the VMM.  
This status does not mean that 
the TD Quote is  generated or 
returned.  
The caller shall wait for event -
notification to evaluate the 
output buffer to know if the TD 
Quote is generated successfully.  
TDG.VP.VMCALL_RETRY  The TD should retry the 
operation . 
TDG.VP.VMCALL_INVALID_OPERAND  Invalid operand – for example, 
the GPA may be mapped as a 
private page.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  20 Table 3-10: TDG.VP.VMCALL<GetQuote> - format of shared GPA  
Field  Offset 
(Bytes)  Length 
(bytes)  Description  
Version  0 8 Version for this structure. It must be 1.  
This field is always filled by TD.  
Status 
Code  8 8 Status Code updated by VMM before the VMM returns the VMCALL 
or interrupts the TD. See Table 3 -11. 
This field is always filled by VMM.  
Input 
Length  16 4 The length for data from TD as input. It must be equal  to or smaller 
than the size of shared GPA (R13) – 24. 
Output 
Length  20 4 The length for data from VMM as input. It must be equal or smaller 
than size of shared GPA (R13) – 24. 
Data  24 Size of 
shared 
GPA - 24 On input, the data filled by TD with input length. The data should 
include TDREPORT_STRUCT.  TD should zeroize the remaining buffer 
to avoid information leak if size of shared GPA (R13) > Input Length.  
On output, the data filled by VMM with output length. T he data 
should include TD Quote.  
Table 3-11: TDG.VP.VMCALL<GetQuote> - GetQuote Status Code  
GET_QUOTE_SUCCESS  0x0 TDG.VP.VMCALL<GetQuote> is 
successfully completed.  
GET_QUOTE_IN_FLIGHT  0xFFFFFFFF_FFFFFFFF  TDG.VP.VMCALL<GetQuote> is 
under processing. The shared 
GPA isn’t ready for TD to 
consume.  
GET_QUOTE_ERROR  0x80000000_00000000  Error without specifying any 
reason.  
GET_QUOTE_SERVICE_UNAVAILABLE  0x80000000_00000001  Quoting service isn’t available . 
 
Ref. # 348552 -004US  21 The following is a typical execution flow : 
1) Guest TD sets up notification vector via TDG.VP.VMCALL<SetupEventNotifyInterrupt>  
2) Guest TD allocates share GPA and initializes  it, and then issues 
TDG.VP.VMCALL<GetQuote>. The data field should include TDREPORT_STRUCT.  
3) VMM receiv es TDG.VP.VMCALL<GetQuote> request . It checks input operands, fields in 
shared GPA.  
4) If the input operands and fields in shared GPA are good, the VMM upda tes status code 
in shared GPA to GET_QUOTE_IN_FLIGHT and queues the request. Then, 
TDG.VP.VMCALL<GetQuote> is returned to TD.  The VMM processes the request in 
background.  
5) The VMM sends the data field  from the TD in shared GPA to a service hosting TD -
Quoti ng Enclave and receives response message from it. 
6) The VMM stores the data field in the received message in shared GPA and updates 
output length and status  code in shared GPA.  
7) The VMM notifies the TD with an interruption vector specified by 
TDG.VP.VMCALL<Se tupEventNotifyInterrupt>.  
8) The guest TD is interrupted. It checks if  the GetQuote status  code fields in shared GPA 
are not GET_QUOTE_IN_FLIGHT. If GetQuote status code is GET_QUOTE_SUCCESS, 
the data field includes the TD Q uote.  
TDG.VP.VMCALL<GetQuote> API a llows one TD to issue  multiple requests. This is  
implementation specific  as to  how many concurrent requests are allowed. The TD should be 
able to handle TDG.VP.VMCALL_RETRY  if it chooses to issue multiple requests 
simultaneously . 
3.4 TDG.VP.VMCALL <Report FatalError > 
The FatalError TDG.VP.VMCALL  can inform the host VMM  that the TD has experienced a fatal -

error state , and let the VMM access debugging information .  The output return ed by the 
TDG.VP.VMCALL  by the host VMM for Debug  and Production versions of the platform may be 
different .   
This TDG.VP.VMCALL  is intended to be used by the TD OS during early boot (in guest -
firmware execution , for example) where some instructions like I N/OUT may be avoided to  
prevent causing  a #VE . It may be also used by the TD guest post -boot when it detects an error 
(e.g., a security violation) and the TD  wants to stop reliably  with information exposed to the 
host via the TD -specific error code (and additional information as a zero -terminated string via 
the shared memory 4KB region) . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  22 Table 3-12: TDG.VP.VMCALL < ReportFatalError  >-Input Operands  
R11  TDG.VP.VMCALL < ReportFatalError  > sub -function  per Table 2 -3 
R12  Bits  Name  Description  
31:0  TD-specific error code  TD-specific error code  
Panic – 0x0. 
Values – 0x1 to 0xFFFFFFFF 
reserved . 
62:32  TD-specific extended 
error code  TD-specific extended error code.  
TD software defined.  
63 GPA Valid  Set if the TD specified additional 
information in the GPA parameter 
(R13) . 
R13  4KB -aligned GPA where additional error data is shared by the TD. The 
VMM must validate that this GPA has the Shared bit se t. In other words, 
that a shared -mapping is used, and that this is a valid mapping for the 
TD. This shared memory region is expected to hold a zero -terminated 
string.  
TD during TDH.VP.INIT].  
R14, R15, RBX, RDI, RSI, 
R8, R9, RDX  Optional error data in registers if the corresponding bit is set in RCX 
bitmap.  
The order is in the input register order  (R14 is first, R15 second, etc) . 
The information is byte sequence, LSB is filled first. Typically , ASCII  
code(0x20 -0x7e) is filled.  
Table 3-13: TDG.VP.VMCALL <Report FatalEr ror>-Output Operands  
R10  TDG.VP.VMCALL -return code.  
Table 3-14: TDG.VP.VMCALL < ReportFatalError  >-Status Codes  
TDG.VP.VMCALL_SUCCESS  See values in Table 2-6 TDG.VP.VMCALL is successful . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  23 3.5 TDG.VP.VMCALL <SetupEventNotifyInterrupt>  
The guest TD may request that the host VMM specify  which interrupt vector to use as an 
event -notify vector.  This is  designed as an untrusted operation;  thus,  the TD OS should be 
designed not to use  the event notification for trusted operations.  Example of an operation 
that can use the event notify is the host VMM signaling a device removal to the TD, in 
response to which a TD may unload a device driver .  
The host VMM should use SEAMCALL [TDWRVPS] leaf to inject an interrupt at the requested -
interrupt vector into the TD VCPU that executed TDG.VP.VMCALL 
<SetupEventNotifyInterrupt>  via the posted -interrupt descriptor.   See Intel TDX -module  
specification [3 ] for TD -interrupt handling.  
Table 3-15: TDG.VP.VMCALL < SetupEventNotifyInterrupt >-Input Operands  
R11  TDG.VP.VMCALL <Setup Event Notify Interrupt > sub -function  per 
Table 2 -3. 
R12  Interrupt vector (valid values 32:255) selected by TD . 
Table 3-16: TDG.VP.VMCALL < SetupEventNotifyInterrupt >-Output Operands  
Table 3-17: TDG.VP.VMCALL < SetupEventNotifyInterrupt  >-Status Codes  
TDG.VP.VMCALL_SUCCESS  See values in Table 2 -6. TDG.VP.VMCALL is successful . 
TDG.VP.VMCALL_INVALID_OPERAND  Invalid operand . 
3.6 TDG.VP.VMCALL <Instruction.CPUID>  
Instruction.CPUID  TDG.VP.VMCALL  is designed to enable the TD -guest to request the VMM to 
emulate  CPUID operation, especially for non -architectural , CPUID  leaves . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
TDG.VP.V MCALL Interface  
Ref. # 348552 -004US  24 Table 3-18: TDG.VP.VMCALL <Instruction.CPUID> -Input Operands  
R11  TDG.VP.VMCALL <Instruction.CPUID> -Instruction -execution sub -
functions  per Table 2 -3. 
R12  EAX  
R13  ECX  
 
Table 3-19: TDG.VP.VMCALL <Instruction.CPUID> -Output Operands  
R12  EAX  
R13  EBX  
R14  ECX  
R15  EDX  
 
Table 3-20: TDG.VP.VMCALL <Instruction.CPUID> -Status Codes  
TDG.VP.VMCALL_SUCCESS  See values in Table 2 -6 TDG.VP.VMCALL is successful . 
 
3.7 TDG.VP.VMCALL <#VE. Request MMIO>  
This TDG.VP.VMCALL  is used to help request the VMM perform emulated -MMIO -access 
operation.  The VMM may emulate MMIO space in shared -GPA space . The VMM can induce  a 
#VE on these shared -GPA accesses by mapping shared GPAs with the suppress -VE bit cleared 
in the EPT Entries corresponding  to these mappings.  
In response to the #VE, the TD can use the TDCALL[ TDG.VP.VEINFO. GET] to get the 
Virtualization -Exception -Information Fields (See  Intel TDX -module specification ) and validate 
that t he #VE  exit reason is 48 (EPT violation causing #VE).  After the TD software decodes the 
instruction causing the #VE locally  and validating the accessed region and source of access,  
the TD may choose to use this TDG.VP.VMCALL  to request MMIO read/write operations.   Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  25 The VMM may emulate the access based on the in puts provided by the TD .  However, note 
that, like other TDG.VP.VMCALL s, this TDCALL is designed as an untrusted operation and to be 
used for untrusted IO with other cryptographic protection for the TD data provided by the TD 
itself.  
 
Table 3-21: TDG.VP.VMCALL <#VE. RequestMMIO> -Input Operands  
R11  TDG.VP.VMCALL <#VE. RequestMMIO> sub -function per Table 2 -3. 
R12  Size of access. 1=1byte, 2=2bytes, 4=4bytes, 8=8bytes.  
All rest value = reserved.  
R13  Direction. 0=Read, 1=Write.  
R14  MMIO Address  
R15  Data to write, if R13 is 1.  
Table 3-22: TDG.VP.VMCALL <#VE. Request MMIO >-Output Operands  
R11  Data to read, if R13 is 0.  
Table 3-23: TDG.VP.VMCALL <#VE. Request MMIO >-Status Codes  
TDG.VP.VMCALL_SUCCESS  See values in Table 2-6 TDG.VP.VMCALL is successful . 
TDG.VP.VMCALL_INVALID_OPERAND  If invalid operands provided by 
the TD, e.g., MMIO address . 
 
Ref. # 348552 -004US  26 3.8 TDG.VP.VMCALL <Instruction.HLT>  
Instruction.HLT TDG.VP.VMCALL  is used to help  perform HLT operation.  The TD guest informs the VMM 
regarding the TD’s interrupt (blocked) status via this interface.  
Table 3-24: TDG.VP.VMCALL <Instruction.HLT> -Input Operands  
R11  TDG.VP.VMCALL <Instruction.HLT> -Instruction -execution sub -functions  
per Table 2 -3. 
R12  Interrupt Blocked Flag.  
The TD is expected to clear this flag if RFLAGS.IF == 1 or the TDCALL 
instruction (that invoked TDG.VP.TDVMCALL(Instruction.HLT)) 
immediately follows an STI instruction, otherwise this flag should be 
set. 
Table 3-25: TDG.VP.VMCALL <Instruction.HLT> -Output Operands  
Table 3-26: TDG.VP.VMCALL <Instruction.HLT> -Status Codes  
Ref. # 348552 -004US  27 3.9 TDG.VP.VMCALL <Instruction.IO>  
Instruction.IO TDG.VP.VMCALL  is used to help request the VMM perform IO operation s. 
Table 3-27: TDG.VP.VMCALL <Instruction.IO> -Input Operands  
R11  TDG.VP.VMCALL <Instruction.IO> -Instruction -execution sub -functions  per Table 2 -3. 
R12  Size of access. 1=1byte, 2=2bytes, 4=4bytes.  
R14  Port number  
Table 3-28: TDG.VP.VMCALL <Instruction.IO> -Output Operands  
Table 3-29: TDG.VP.VMCALL <Instruction.IO> -Status Codes  
TDG.VP.VMCALL_INVALID_OPERAND  Invalid -IO-Port access  
3.10 TDG.VP.VMCALL <Instruction.RDMSR>  
Instruction.RDMSR TDG.VP.VMCALL  is used  to help perform RDMSR operation.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5

Instruction.RDMSR TDG.VP.VMCALL  is used  to help perform RDMSR operation.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  28 Table 3-30: TDG.VP.VMCALL <Instruction.RDMSR> -Input Operands  
R11  TDG.VP.VMCALL <Instruction.RDMSR> Instruction execution sub -functions  
R12  MSR Index  
Table 3-31: TDG.VP.VMCALL <Instruction.RDMSR> -Output Operands  
R11  MSR Value  
Table 3-32: TDG.VP.VMCALL <Instruction.RDMSR> -Status Codes  
TDG.VP.VMCALL_SUCCESS  See values in Table 2 -
6 TDG.VP.VMCALL is successful . 
TDG.VP.VMCALL_INVALID_OPERAND  Invalid MSR rd/wr requested or 
access -denied . 
3.11 TDG.VP.VMCALL <Instruction.WRMSR>  
Instruction.WRMSR TDG.VP.VMCALL  is used to help perform WRMSR operation.  
Table 3-33: TDG.VP.VMCALL <Instruction.WRMSR> -Input Operands  
R11  TDG.VP.VMCALL <Instruction.WRMSR> -Instruction -execution sub -
R13  MSR Value  
Table 3-34: TDG.VP.VMCALL <Instruction.WRMSR> -Output Operands  
Ref. # 348552 -004US  29 Table 3-35: TDG.VP.VMCALL <Instruction.WRMSR> -Status Codes  
3.12 TDG.VP.VMCALL <Instruction. WBINVD > 
Instruction. WBINVD  TDG.VP.VMCALL is used to help perform WBINVD  operation.  
Table 3-36: TDG.VP.VMCALL<Instruction. WBINVD >-Input Operands  
R11  TDG.VP.VMCALL<Instruction. WBINVD >-Instruction -execution sub -
R12  0: WBINVD  
1: WBNOINVD  
Others: Reserved  
Table 3-37: TDG.VP.VMCALL<Instruction.W BINVD >-Output Operands  
 
Table 3-38: TDG.VP.VMCALL<Instruction.WRMSR> -Status Codes  
TDG.VP.VMCALL_INVALID_OPERAND  Invalid R12 value  requested . 
3.13 TDG.VP.VMCALL <Instruction. PCONFIG > 
Instruction.VMCALL PCONFIG is used to help  perform Instruction -PCONFIG operation.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  30 Table 3-39: TDG.VP.VMCALL <Instruction.PCONFIG> -Input Operands  
R11  TDG.VP.VMCALL <Instruction.PCONFIG> sub -function  per Table 2 -
3. 
R12  PCONFIG -Leaf function requested . 
R13, R14, R15  Leaf -specific purpose (See PCONFIG ISA definition in MKTME 
spec.  [4] 
Table 3-40: TDG.VP.VMCALL <Instruction.PCONFIG> -Output Operands  
R11  VMM -Vendor Specific  
R12, R13, R14, R15, RBX, RDI, 
RSI, R8, R9, RDX  VMM -Vendor Specific  
XMM0 –XMM15  If RCX bit 1 is set, the XMM content is set by VMM host when 
executing SEAMCALL(TDENTER).  
Otherwise , the XMM content is unmodified.  
 
Table 3-41: TDG.VP.VMCALL <Instruction.PCONFIG> -Status Codes  
TDG.VP.VMCALL_INVALID_OPERAND  If PCONFIG -operation 
requested is invalid . 
3.14 TDG.VP.VMCALL <Service>  
In Service TD scenario, there is a need to define interfaces for the command/response that 
may have long latency, such as communicating with local device via Secure Protocol and Data 
Model (SPDM), communicating with remote platform via Transport Layer Security (TLS) 
Protocol, or communicating with a Quoting Enclave (QE) on attestation or mutual 
authentication.  
There is also needed  that the VMM may notify a service TD to do some actions, such as 
Migr ation TD (MigTD).  
We define Command/Response Buffer (CRB) DMA interface.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  31 Table 3-42: TDG.VP.VMCALL < Service  >-Input Operands  
R11  TDG.VP.VMCALL<  Service  > sub -function per Table 2 -3. 
R12  Shared 4KB aligned GPA as input – the memory contains a Command.  
It could be more than one 4K pages.  
R13  Shared 4KB aligned GPA as output – the memory contains a Response.  
R14  Event notification interrupt vector - (valid values 32~255) selected by 
TD. 
0: blocking action. VMM need get response then return.  
1~31: Reserved. Should not be used.  
32~255: Non -block action. VMM can return immediately and signal the 
interrupt vector when  the response is ready.  VMM should  inject interrupt 
vector into the TD VCPU  that executed TDG.VP. VMCALL<Service>.  
R15  Timeout – Maximum wait time for the command and response.  
0 means infinite wait.  
 
Table 3-43: TDG.VP.VMCALL < Service  >-Output Operands  
R10  TDG.VP.VMCALL return code.  
 
Table 3-44: TDG.VP.VMCALL < Service  >-Status Codes  
TDG.VP.VMCALL_SUCCESS  See values in  
 TDG.VP.VMCALL is successful . 
private page. Or the interrupt 
vector is invalid.  
Ref. # 348552 -004US  32 Table 3-45: TDG.VP.VMCALL < Service  >-command buffer layout  
GUID  0 16 A unique GUID to identify the service.  
 
Length  16 4 Size in bytes of the command buffer, including the GUID 
and Length. (24 + N)  
 
Reserved  20 4 Reserved  
Data  24 N GUID specific command data.  
 
Ref. # 348552 -004US  33 Table 3-46: TDG.VP.VMCALL < Service  >-response buffer layout  
Length  16 4 Size in bytes of the response buffer, including the GUID and Length. (24 
+ N)  
When TD uses the VMCALL, this field is filled by TD to indicate the 
maximum allocated response buffer size.  
When VMM triggers interrupt vector, this field is filled by VMM to 
indicate the returned re sponse buffer size.  
Status  20 4 Common Status Code for response : 
0: Command is sent, and response is returned.  
1: Device error  
2: Timeout  
3: Response buffer too small . In this case, the Length means required 
response buffer size.  
4: Bad command buffer size  
5: Bad response buffer size  
6: Service busy  
7: Invalid Parameter  
8: Out of resource  
0xFFFFFFFE: Unsupported.  
0xFFFFFFFF: Reserved – should be filled by TD, so that TD can check 
if the response is returned by VMM.  
This field is always filled by VMM.  (*) 
Data  24 N GUID specific response data.  
(*) NOTE:  Status  field only means that the VMM sends  the command  and receives a 
response. It does not mean that the response contains  a success code.  For example, an 
SPDM responder may return an SPDM error in an SPDM  response message. The VMM will 
fill SUCCESS in this status. The SPDM requester in TD should parse the SPDM response 
message to get the SPDM error code.  
Ref. # 348552 -004US  34 The detail flow is : 
Step 1, the TD will:  
1.1) Prepare an event notification interrupt vector.  
1.2) Prepare a shared command buffer and put a command there including GUID, 
length , and data.  
1.3) Prepare a shared response buffer and put the GUID and maximum length of 
response  buffer there.  
1.4) Trigger TDVMCALL.  
Step 2, the VMM will:  
2.1) Set up  the context for this TDVMCALL <Service> (For example, save the response 
buffer and event notification interrupt vector) . 
2.2) Send command . 
2.3) Prepare for response (Interrupt or Poll) . 
2.2) return TDVMCALL to TD.  
Step 3, the TD will:  
3.1) Free the shared command buffer and make it private. (Optional, if the TD wants to 
reuse the buffer later) . 
Step 4, once VMM gets the response, the VMM will : 
4.1) Check if the Response.Length is large enough to hold the response.  
4.2) Fill the Response.Data field wi th response.  
4.3) Free the context for this TDVMCALL <Service>  
4.3) Trigger Event Notification Interrupt to TD.  
Step 5, once TD gets the event notification, the TD will : 
5.1) Read the data from the response to private.  
5.2) Free the shared response buffer and make it private. (Optional, if the TD wants to 
5.3) If the returned data includes length, offset, index, etc., apply the side channel

5.3) If the returned data includes length, offset, index, etc., apply the side channel 
mitigation, such as lfence(), before parsing the data.  
5.4) Parse the response in private mem ory. NOTE: This is from untrusted source. The 
TD must check the data before us ing it. 
TDG.VP.VMCA LL Interface  
Ref. # 348552 -004US  35 3.14.1  TDG.VP.VMCALL <Service.Query>  
This generic service is  used  to allow TD to query the capability.  
 
// {FB6FC5E1 -3378-4ACB-8964-FA5EE43B9C8A}  
#define VMCALL_SERVICE_ COMMON_GUID \ 
{0xfb6fc5e1, 0x3378, 0x4acb, 0x89, 0x64, 0xfa, 0x5e, 0xe4, 0x3b, 0x9c, 0x8a } 
Table 3-47: TDG.VP.VMCALL < Service.Query  >-command buffer layout  
Version  0 1 0: for this data structure  
Command  1 1 0: Query  
Reserved  2 2 Reserved  
GUID  4 16 The Service GUID to query  
 
Table 3-48: TDG.VP.VMCALL < Service.Query  >-response buffer layout  
Status  2 1 0: Service supported  
1: Service unsupported  
Reserved  3 1 Reserved  
 
3.14.2  TDG.VP.VMCALL <Service .MigTD > 
This is used to allow MigTD to get the migration information from VMM.  
 
#define VMCALL_SERVICE_ MIGTD_GUID \ 
{0xe60e6330, 0x1e09, 0x4387, 0xa4, 0x44, 0x8f, 0x32, 0xb8, 0xd6, 0x11, 0xe5}  
Ref. # 348552 -004US  36 3.14.2.1  TDG.VP.VMCALL <Service .MigTD.Shutdown > 
This is used to allow a service TD to shutdown itself after it finishes the task.  
Table 3-49: TDG.VP.VMCALL < Service.MigTD.Shutdown  >-command buffer layout  
Command  1 1 0: Shutdown  
No response data is required.  
 
3.14.2.2  TDG.VP.VMCALL <Service .MigTD.WaitForRequest > 
Table 3-50: TDG.VP.VMCALL < Service.MigTD.WaitForRequest  >-command buffer layout  
Command  1 1 1: Wait for request  
Ref. # 348552 -004US  37 Table 3-51: TDG.VP.VMCALL < Service.MigTD.WaitForRequest  >-response buffer layout  
Operation  2 1 0: No -op 
1: Start Migration  
2~0xFF: reserved  
 
This field is used to perform corresponding migration 
command.  
Migration 
Information  4 Variable  A HOB list. The HOB list shall not include a Phase Handoff 
Information Table  (PHIT) HOB. The HOB list shall end with 
an End of HOB List  HOB.  All HOBs in the list shall be zero 
padded to multiples of 8 bytes in length.  
The HOB list shall include Migration related GUID extension 
HOB, including MIGTD_MIGRATION_INFORMATION  HOB 
and others.  
If there is any unexpected HOB in the HOST list, the input 
shall be treated as invalid.  
3.14.2.2.1  Migration Request Information GUID Extension HOB  
This GUID extension HOB reports the migration request information.  
#define MIGTD_MIGRATION_INFORMATION _HOB_GUID \ 
{0x42b5e398, 0xa199, 0x4d30, 0xbe, 0xfc, 0xc7, 0x5a, 0xc3, 0xda, 0x5d, 0x7c}  
typedef struct {  
  UINT64               MigRequestID;  
  BOOLEAN              MigrationSource;  
  UINT8                TargetTD_UUID[32];  
  UINT64               BindingHandle;  
  UINT64               MigPolicyID;  
  UINT64               CommunicationID;  
} MIGTD_MIGRATION_INFORMATION _HOB_DATA ; 
MigRequestID  The ID for the migration request. It is used in TDG.VP.VMCALL 
<Service.MigTD.ReportStatus> in TDG.VP.VMCALL 
<Service.MigTD.Send> and TDG.VP.VMCALL <Service.MigTD.Receive> . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  38 MigrationSource  TRUE: This MigTD is MigTD -s; FALSE: This MigTD is MigTD -d. 
TargetTD _UUID  The UUID for the target TD returned from 
SEAMCALL[TDH.SERVTD.BIND] . 
BindingHandle  The BindingHandle for the MigTD and the target TD returned from 
MigPolicyID  The ID for the migration policy.  
CommunicationID  The ID for the VM M communication channel.  
 
3.14.2.2.2  Stream Socket Info GUID Extension HOB  
This GUID extension HOB reports the VMCALL based stream socket information.  
 
#define MIGTD_STREAM_SOCKET_INFO_HOB_ GUID \ 
{0x7a103b9d, 0x552b, 0x485f, 0xbb, 0x4c, 0x2f, 0x3d, 0x2e, 0x8b, 0x1e, 0xe}  
 
  UINT64               MigTdCid;  
  UINT32               MigChannelPort;  
  UINT32               QuoteServicePort;  
} MIGTD_STREAM_SOCKET_INFO _HOB_DATA ; 
CommunicationID  A unique identifier f or this communication. It can be used in 
MIGTD_MIGRATION_INFORMATION  HOB.  
MigTdCid  The context ID (CID) for the MigTD.  
MigChannelPort  The listening port of the MigTD or VMM for the migration secure 
QuoteServicePort  The listening port of the VMM for the quote service channel.  
3.14.2.2.3  Runtime Migration Policy GUID Extension HOB  
This GUID extension HOB reports the runtime migration policy.  
#define MIGTD_MIGPOLICY_HOB_ GUID \ 
{0xd64f771a, 0xf0c9, 0x4d33, 0x99, 0x8b, 0xe, 0x3d, 0x8b, 0x94, 0xa, 0x61 } 
  UINT32               MigPolicySize;  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  39   UINT8                MigPolicy[ MigPolicySize ]; 
} MIGTD_MIGPOLICY_INFO _HOB_DATA ; 
MigPolicyID  A unique identifier for this policy. It can be u sed in 
MigPolicySize  The size in bytes of the migration policy.  
MigPolicy  The migration policy data.  
Ref. # 348552 -004US  40 3.14.2.3  TDG.VP.VMCALL <Service .MigTD.ReportStatus > 
Table 3-52: TDG.VP.VMCALL < Service.MigTD.ReportStatus  >-command buffer layout  
Command  1 1 2: Report Status  
Operation  2 1 Same as the “Operation” in TDG.VP.VMCALL 
<Service.MigTD.WaitForRequest>  
Status  3 1 0: SUCCESS  
1: INVALID_PARAMETER  
2: UNSUPPORTED  
3: OUT_OF_RESOURCE  
4: TDX_MODULE_ERROR  
5: NETWORK_ERROR  
6: SECURE_SESSION_ERROR  
7: MUTUAL_ATTESTATION_ERROR  
8: MIGPOLICY_ERROR  
0xFF: MIGTD_INTERNAL_ERROR  
0x0A~0xFE: Reserved  
MigRequestID  4 8 The MigRequestID in 
MIGTD_MIGRATION_INFORMATION  HOB  
 
Table 3-53: TDG.VP.VMCALL < Service.MigTD.ReportStatus  >-response buffer layout  
Ref. # 348552 -004US  41 3.14.2.4  TDG.VP.VMCALL <Service. MigTD .Send > 
The two MigTDs use this VMCALL and next VMCALL to transmit and receive the 
communication packet to each other via the VMM.  
The communication packet is transparent to the VMM. The VMM shall treat it as binary blob 
and do es not parse it. The VMM should guarantee the connection is reliable. For example, no 
communication packet will be lost. No communication packet will arrive out of order.  
The MigTD should guarantee the communication request for one MigRequestID is sequential. 
Multiple requests for one MigRequestID at same time are not allowed. If the VMM receives 
another request whi le it is waiting for the response of the previous request with the same 
MigRequestID, the VMM shall return Service busy error status. The MigTD may send multiple 
requests for different MigRequestID at  the same time  - the VMM shall support this case and 
server all requests. If the VMM may run out of resource s to create a new context to 
communicate with the remote, the VMM shall return  an Out of resource  error status.  
If the VMM has hardware error and fails to send the command or receive the response, the 
VMM  shall return Device error  status. If the VMM fails to send the command or receive the 
response in timeout period indicated by the MigTD, the VMM shall return Timeout  status.  
The MigTD shall provide a large  enough response buffer. If the response buffer is too small to 
hold the response from the peer MigTD, the VMM shall return Receive buffer too small  error 
status.  
The MigTD shall provide a reasonable size command buffer and response buffer to allow 
VMM allocate the memory to handle the input or output. The VMM shall support at least a

status.  
VMM allocate the memory to handle the input or output. The VMM shall support at least a 
64KB  command buffer and response buffer. If the MigTD request an unreasonable larg e 
command buffer or response buffer, such as 1GB, the VMM may return Bad command 
buffer size  or Bad response buffer size  error status.  
The MigTD may input zero command buffer size, when the MigTD -d wants to wait for the 
first request message from MigTD -s. The MigTD may input zero response buffer size, 
when a MigTD sends the last handshake message to the peer. The VMM shall handle 
those cases correctly. If the MigTD inputs zero command buffer size and zero response 
buffer size at same time, the VMM shall ret urn Invalid parameter  error status.  
For the detail of stream communication flow, please refer to VMCALL stream message section.  
Ref. # 348552 -004US  42 Table 3-54: TDG.VP.VMCALL < Service.MigTD.Send  >-command buffer layout  
Command  1 1 3: Send  
Stream 
Message 
Header  12 H The stream message header. It is virtio_vsock_hdr , 
defined in Virtual I/O Device (VIRTIO) Version 1.1 
Specification 01 . 
MigTD 
communication 
packet  12 + H  N This field is only present when virtio_vsock_hdr .op 
is VIRTIO_VSOCK_OP_RW . 
Size in bytes of the MigTD communication packet to be 
sent.  
The format of the packet is defined by the MigTD. The 
VMM shall send the binary blob to the peer MigTD.  
 
Table 3-55: TDG.VP.VMCALL < Service.MigTD.Send  >-response buffer layout  
3.14.2.5  TDG.VP.VMCALL <Service. MigTD .Receive > 
Ref. # 348552 -004US  43 Table 3-56: TDG.VP.VMCALL < Service.MigTD.Receive  >-command buffer layout  
Command  1 1 4: Receive  
 
Table 3-57: TDG.VP.VMCALL < Service.MigTD.Receive  >-response buffer layout  
Stream 
Message 
defined in Virtual I/O Device (VIRTIO) Version 1.1  
MigTD 
Size in bytes of the MigTD communication packet being 
received.  
VMM shall receive the binary blob from the peer MigTD.  
3.14.2.5.1  Stream Socket Message  
A service TD may set up  a stream connection with a VMM. Either a service TD or a VMM can be 
the client or the server. Every stream message starts with a virtio_vsock_hdr , followed by 
the payload if the operation is VIRTIO_VSOCK_OP_RW . 
In order to create a stream c onnection , the client sends VIRTIO_VSOCK_OP_REQUEST  packet. If 
the server is listening, then it sends VIRTIO_VSOCK_OP_RESPONSE  packet  and the stream Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  44 connection is established. If the server is not listening or has no resource, then it sends 
VIRTIO_VSOCK _OP_RESET packet . 
Once the stream connection is established, both entities may send VIRTIO_VSOCK_OP_RW  
packet  to the peer.  
When an entity does not need send more data or receive more data, it sends 
VIRTIO_VSOCK _OP_SHUTDOWN  packe t. The peer sends VIRTIO_VSOCK _OP_RESET response to 
confirm. The stream connection is terminated. Even if the response is not received, the 
connection is still terminated with a timeout period.  
 
The VMM CID is always set to 0x2. The MigTD CID is passed from VMM dynamically. The server 
listening port of VMM or MigTD can be predefined or passed from VMM dynamically.  
When the MigTD acts as a client and the VMM acts as a server. Below communication flow is 
used:  
MigTD: {MigTdCid, VmmCid, MigTdPort , VmmListeningPort , OP_REQUEST}  
VMM: {VmmCid, MigTdCid, VmmListeningPort, MigTdPort, OP_RESPONSE}  
MigTD: {MigTdCid, VmmCid, MigTdPort, VmmListeningPort, OP_RW, payload}  
VMM: {VmmCid, MigTdCid, VmmListeningPort, MigTdPort, OP_RW, payload}  
…… 
MigTD: {MigTdCid, VmmCid, MigTdPort, VmmListeningPort, OP_SHU TDOWN}  
VMM: {VmmCid, MigTdCid, VmmListeningPort, MigTdPort, OP_RESET}  
When the MigTD acts as a server and the VMM acts as a client. Below communication flow is 
used:  
VMM: {VmmCid, MigTdCid, VmmPort , MigTdListeningPort , OP_REQUEST}  
MigTD: {MigTdCid, VmmCid,  MigTdListeningPort , VmmPort , OP_RESPONSE}  
VMM: {VmmCid, MigTdCid, VmmPort , MigTdListeningPort , OP_RW, payload}  
MigTD: {MigTdCid, VmmCid, MigTdListeningPort , VmmPort , OP_RW, payload}  
…… 
VMM: {VmmCid, MigTdCid, VmmPort , MigTdListeningPort , OP_SHUTDOWN}  
MigTD: {MigTdCid, VmmCid, MigTdListeningPort , VmmPort , OP_RESET}  
TD-Guest -Firmware Interfaces  
Ref. # 348552 -004US  45 4 TD -Guest -Firmware Interfaces  
4.1 ACPI  MADT  Multiprocessor Wakeup Table  
The guest  firmware is designed to publish a multiprocessor -wakeup structure to let the guest -
bootstrap process or wake up guest -application processors with a mailbox.  The mailbox is 
memory that the guest firmware can reserve so each guest virtual processor can have the 
guest OS send a message to them.  
For detailed information about the Multiprocessor Wakeup Table,  please refer to ACPI 6.4 
4.2 Memory Map  
The memory in the TD guest -environment can be:  
1) Private memory – SEAMCALL[ TDH.MEM.PAGE. ADD]  by VMM or TDCALL 
[TDG.MEM.PAGE. ACCEPT] by TDVF with S -bit clear in page table.  
2) Shared memory – SEAMCALL[ TDH.MEM.PAGE.ADD ] by VMM or TDCALL 
[TDG.MEM.PAGE. ACCEPT] by TDVF with S -bit set in page table.  
3) Unaccepted  memory – SEAMCALL[ TDH.MEM.PAGE.AUG ] by VMM and not accepted by 
TDVF yet.  
4) Memory -Mapped I/O  (MMIO) - Shared memory accessed via TDVF via 
TDVMCALL< #VE.RequestMMIO >. 
If a TD-memory region is private memory, the  TD owner shall have the  final UEFI -memory 
map report the region with  EfiReservedMemoryType , EfiLoaderCode , EfiLoaderData , 
EfiBootServiceCode , EfiBootServiceData , EfiRuntimeServiceCode , 
EfiRuntimeServiceData , EfiConventionalMemory , EfiACPIReclaimMemory , 
EfiACPIMemoryNVS . 
If a TD-memory region is shared memory, the TD owner shall  convert it to private memory 
before transfer to OS kernel . 
If a TD-memory region is unaccepted memory and requires TDCALL [ TDG.MEM.PAGE. ACCEPT]  in the 
TD guest OS, then the  TD owner shall have the  final UE FI-memory map report this region  with 
EfiUnacceptedMemor yType . Please refer to UEFI 2.9 specification . 
If a memory region is MMIO, it  is designed to  only be accessed via 
TDVMCALL<#VE.RequestMMIO>  and not via direct memory read or write.  Accordingly, as 
designed, t here is no need to report this region in UEFI -memory map , because no RUNTIME 
attribute is required.  The full MMIO regions are designed to  be reported in ACPI ASL code via 
memory -resource des criptors.  
Ref. # 348552 -004US  46 Table 4-1: TDVF -memory map for OS  
UEFI Memory Type  Usage  TD-Memory 
Type  OS Action  
EfiReservedMemoryTpe  Firmware -Reserved 
region, such as flash.  Private  Reserved.  
EfiLoaderCode  UEFI -Loader Code  Private  Use after EBS.  
EfiLoaderData  UEFI -Loader Data  Private  Use after EBS.  
EfiBootServicesCode  UEFI -Boot -Service Code  Private  Use after EBS.  
EfiBootServicesData  UEFI -Boot -Service Data  Private  Use after EBS.  
EfiRuntimeServicesCode  UEFI -Runtime -Service 
Code  Private  Map -virtual address. 
Reserved.  
EfiRuntimeServicesData  UEFI -Runtime -Service 
Data  Private  Map -virtual address. 
Reserved.  
EfiConventionalMemory  Freed memory (Private)  Private  Use directly.  
EfiACPIReclaimMemory  ACPI table.  Private  Use after copy ACPI 
table.  
EfiACPIMemoryNVS  Firmware Reserved for 
ACPI, such as the memory 
used in ACPI OpRegion  Private  Reserved.  
EfiMemoryMappedIO  No need to report the 
MMIO region, as no 
RUNTIME -virtual address  
is required for TD.  
The full MMIO should be 
reported in ACPI -ASL 
code.  N/A N/A 
EfiUnacceptedMemoryType  UEFI -Boot -Service Data 
(Shared Memory)

Reserved.  
Reserved.  
table.  
(Shared Memory)  
VMM -shared buffer.  Unaccepted  Use after EBS and 
converting to private 
page.  
==============  
TDCALL[TDG.VP.VMCAL
L] <MapGPA>  
TDCALL[TDG.MEM.PAG
E.ACCEPT]  
Ref. # 348552 -004US  47 For a non-UEFI system, the memory map can be reported via E820 table.  Please  refer to ACPI 
6.5 specification . 
If a TD -memory region is private memory, the TD Shim shall have the final memory map 
report the region with AddressRangeMemory , AddressRangeReserved , AddressRangeACPI , or 
AddressRangeNVS . 
If a TD -memory region is shared memory, the TD Shim shall convert it to private memory 
If a TD -memory region is unaccepted memory and requires TDCALL  [TDG.MEM.PAGE. ACCEPT]  in the 
TD guest OS, then the TD Shim shall have the final memory map report thi s region with 
AddressRangeUnaccepted . 
If a memory region is MMIO, it is designed to only be accessed via 
TDVMCALL<#VE.RequestMMIO> and not via direct memory read or write.  Accordingly, as 
designed, there is no need to report this region in the final memor y map.  
Table 4-2: TDVF  E820 memory map for OS  
E820 Memory Type  Usage  TD-Memory Type  OS Action  
AddressRangeMemory  Usable by OS.  Private  Use directly  
AddressRangeReserved  Firmware -Reserved 
AddressRangeACPI  ACPI table.  Private  Use after copy 
ACPI table.  
AddressRangeNVS  Firmware Reserved for 
AddressRangeUnaccept
ed Allocated by VMM, but 
not accepted by TD guest 
yet. Unaccepted  Use after 
convert to 
private page.  
 
Ref. # 348552 -004US  48 4.3 TD Measurement  
4.3.1  TCG -Platform -Event Log  
If TD -Guest Firmware  supports measurement and an event is created , TD-Guest Firmware  is 
designed to  report the event log with the same data st ructure in TCG -Platform -Firmware -
Profile spec ification  with EFI_TCG2_EVENT_LOG_FORMAT_TCG_2  format . 
The index  created by the TD -Guest Firmware  in the event log should be the index for the 
confidential computing (CC)  measurement register.  
Table 4-3: CC-Event -Log-PCR -Index Interpretation  for TDX  
CC Measurement 
Register Index  TDX -measurement register  
0 MRTD  
1 RTMR[0]  
2  RTMR[1]  
3  RTMR[2]  
4 RTMR[3]  
 
4.3.2  EFI_ CC_MEASUREMENT _PROTOCOL  
If TD -Guest Firmware  supports measurement, the TD  Guest Firmware  is designed to produce 
EFI_ CC_MEASUREMENT _PROTOCOL with new GUID 
EFI_CC_MEASUREMENT _PROTOCOL _GUID  to report event log and provid e hash capability.  
Please refer to UEFI 2.10 specification . 
 
4.3.3  CC-Event Log  
TD-Guest Firmware  may set up a CCEL ACPI table to pass the event -log information.  The 
event log created by  the TD owner contains the hashes to reconstruct the confidential 
computing (CC) measurement  registers.  Please refer to ACPI 6.5 specificat ion. 
 
4.4 Storage -Volume -Key Data  
In the TD-execution  environment, the storage volume will typically  be an encrypted  volume .  
In that case,  by design,  the TD-Guest Firmware will need to support quote generation and 
attestation to be able to fetch a set of storage -volume key (s) from a remote -key server during Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  49 boot and pass the key to the guest kernel.  Also by design, t he key is stored in the memory, 
and the inf ormation of the key is passed from TD -Guest Firmware  via an SVKL ACPI table.  
Please refer to ACPI 6.5 specification . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
TD-VMM -Communication Scenarios  
Ref. # 348552 -004US  50 5 TD -VMM -Communication Scenarios  
 
5.1 Requesting IPIs  
Various TD -VMM -communication scenarios require the TD to re quest that the host generate 
IPIs to TD VCPUs – for example , synchronizing , guest -TD-kernel -managed -IA-page -table 
updates.  This operation is supported via the TDCALL [ TDG.VP.VMCALL  <Instruction.WRMSR>] 
to the x2APIC ICR MSR.   
To perform a cross -VCPU IPI, the guest -TD ILP is designed to  request an operation from the 
host VMM using this TDCALL ( TDG.VP.VMCALL  <Instruction.WRMSR> ).  The VMM can then 
inject an interrupt into the guest TD’s RLPs using the posted -interrupt mechanism.  This is an 
untrusted operation;  thus,  the TD OS must track its completion and not rely on the host VMM 
to faithfully deliver IPIs to all the TD VCPUs . 
5.2 TD-memory conversion and memory ballooning  
Recall that , by design,  guest -physical memory used by a TD is encrypted with a TD -private key 
or with a VMM -managed key based on the GPA -shared bit ( GPA [ 47 or 51] based on GPAW).  A 
TD OS may operate on a fixed , private -GPA space configured by the host VMM.  Typically,  the 
OS manages a physical -page -frame database f or state of (guest) physical -memory allocations.   
Instead of expanding these PFN databases  for large swaths of shared -GPA space , the TD OS 
can manage an attribute for the state of physical memory to indicate whether it is encrypted 
with the TD-private key or a VMM key.   The TD-guest OS can then use 
TDG.VP.VMCALL (MapGPA)  so that , within the fixed -GPA map , the TD OS can request  that the 
host VMM  map Shared -IO memory aliased as shared memory in that GPA space . So in this 
case , the OS can select a page of the private -GPA space and make a 
TDG.VP.VMCALL (MapGPA (GPA ) with GPA. S=1)  to map that  GPA  using the S=1 alias .   
The VMM can then TDH.MEM.RANGE. BLOCK, TD H.MEM. TRACK , and TD H.MEM.SEPT.REMOVE  
the affected GPA from the S -EPT mapping; and t he VMM can then re -claim the page using 
direct -memory stores and map the alias -shared GPA for the TD OS in the shared EPT 
(managed by the VMM).  
At a later point, the TD OS may need to use the GPA as a private page via the same 
TDG.VP.VMCALL (MapGPA) with the GPA specified as a private GPA ( GPA. S=0) – the intent is 
for this to allow the host VMM to unlink the page from the shared EPT and then perform a 
TDH.MEM.PAGE. AUG  to set  up a pending -EPT mapping for the private GPA.  The successful 
completion of the TDG.VP.VMC ALL flow can be used by the TD guest to 
TDG.MEM.PAGE.ACCEPT  to re -initialize the page using the TD -private key and mark the S -EPT 
mapping as active.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  51 5.3 Paravirtualized IO  
The TD guest can use paravirtualized -IO interfaces (for example, using virtio API in KV M) 
exposed by the host VMM to use physical and virtual devices on the host platform that are 
managed by the VMM.  For this scenario, Virtualized  IO is typically enumerated over emulated 
PCIe (port I/O or MMIO).  The TD drivers can help  ensure that the data  passed via memory 
referenced in emulated -MMIO accesses are placed in the TD’s shared -GPA -memory space.    
Paravirtualized drivers could pre -allocate a primary -shared buffer during initialization.   
Subsequently, drivers can allocate a portion of the shared -GPA -space buffer for each 
individual transfer and reclaim the buffer after a specific transfer is completed.   In this 
scenario, the primary buffer  can expand and shrink as needed.   
Shared buffers  can be deallocated during driver -stack tear -down.  This scenario is optimal , as 
allocating shared buffer can involve at least one TDG.VP.VMCALL  (for mapping shared page) 
and TDCALL[TD G.MEM.PAGE. ACCEP T] for mapping back as a private -TD page , as described i n 
Section 4.3 . 
The guest TD may employ VMM functions for IO to participate in the emulation of MMIO 
accesses from legacy -device drivers.  To support this scenario, if the TD OS opts -in, the host 
VMM can host the emulated -device -MMIO space in shared -GPA space of the TD OS.  Legacy -
device -driver accesses to the emulated region can cause EPT violations that can be mutated 
to the TD -#VE handler , which can then support emulation of the MMIO.   
The enlightened -TD-OS-#VE handler can emulate the access causi ng the #VE by decoding the 
instruction (within the TD) and invoking the Instruction.IO functions hosted by the VMM using 
TDCALL [ TDG.VP.VMCALL  <#VE. Request MMIO >].  From that point on, like the paravirtualized 
I/O model, the TD software should ensure that d ata buffers passed via memory referenced by 
parameters  in function  TDG.VP.VMCALL  are placed in the TD’s shared -GPA space.  
5.4 TD attestation  
Goals of TD Attestation are to enable the TD OS to request a TDREPORT that contains version 
information about the Intel TDX module , measurement of the TD, along with a TD -specified 
nonce.  By design, t he TDREPORT is locally MAC’d and used to generate a quote for the TD via

nonce.  By design, t he TDREPORT is locally MAC’d and used to generate a quote for the TD via 
a quoting enclave (QE).  The remote verifier can verify the quote to  help  verify the 
trustworthiness of the TD.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  52 
Trust Domain
Host VMM
Host or Dom 0
CPU
MAC Key
TD Quoting Enclave
EVERIFYREPORT
InstructionAttest Key
Quote
(Signed)
Intel TDX
Module
SEAMREPORT
SEAM 
Measurements
DataTDREPORT
(SEAM Report 
+ TD Info)
TDCS
SEAM 
REPORT
(MACed)
TDG.MR.REPORT 
FunctionTDREPORT
+ TD Info) 
Figure 5-1: TD-Attestation flow  
 
1. Guest -TD software invokes the TDCALL( TDG.MR.REPORT )-API function.  
2. The Intel TDX module  uses the SEAMOPS[ SEAMREPORT ] instruction to create a MAC’d 
TDREPORT_STRUCT with the Intel TDX -module  measurements from CPU and TD 
measurements from the TDCS.  
3. Guest -TD software uses the TDCALL( TDG.VP.VMCALL ) interface to request the 
TDREPORT_STRUCT be converted into a Quote.  
4. The TD -Quoting enclave uses ENCL[EVERIFYREPORT2] to verify the TDREPORT_STRUCT.  
This allows the Quoting Enclave to help verify the report without requiring direct access to 
the CPU’s HMAC key.  Once the integrity of the TDREPORT_STRUCT has been verified, the 
TD-Quoting Enclave signs the TDREPORT_STR UCT body with an ECDSA -384-signing k ey. 
5. The Quote can then be used by TD software to perform a remote -attestation protocol with 
a verifying -remote party.  
Ref. # 348552 -004US  53 5.5 Service TD Binding  
Service TD  is a Trust Domain (TD) VM used to provide a dedicated service/utility.  The 
service TD extends the TCB of the tenant TD to which the TD provides service.  Migration 
TD (MigTD) is an example Service TD.  
One or more service TD s may be bound to a target TD .  Serv ice TD binding relationship has 
the following characteristics:  
• A service TD has a type  (SERVTD_TYPE).  
• A service TD may read and/or write certain target TD metadata .  Access permission to 
target TD metadata fields depends on SERVTD_TYPE.  
• Unsolicited service  TD binding  is done without target TD approval.  The target TD 
needs not be aware of the binding.  
• The target TD’s TDREPORT indicates binding to service TDs.  
• The service TD protocol consists of:  
o Binding  
o Metadata access  
• Service TD to target TD binding relati onship is many -to-many : 
o Multiple service TDs of different types may be bound to a single target TD.  
o Multiple target TDs may be bound to a single service TD.  
• A service TD may itself be a target TD to other service TDs.  
Typical Unsolicited Service TD Binding  and Metadata Access Use Case  
1. Optional Pre -Binding:   During target TD build, before calling 
SEAMCALL[TDH.MR.FINALIZE], the host VMM calls SEAMCALL[TDH.SERVTD.PREBIND] to 
write the binding fields (SERVTD_HASH etc.) in the target TD’s service TD table.  
2. Bindi ng:  Sometime later, the host VMM calls SEAMCALL[TDH.SERVTD.BIND] to bind the 
service TD.  It gets back a binding handle.  The VMM communicates the binding handle, 
target TD_UUID and other binding parameters to the service TD.  
3. Metadata Access:   The service  TD uses TDCALL[TDG.SERVTD.RD and TDG.SERVTD.WR] to 
access target TD metadata.  
4. Rebinding:   May be required , for example because  both the target TD and service TD have 
been migrated , or a new service TD instance replaces the original one.  The host VMM calls 
SEAMCALL[TDH.SERVTD.BIND] to rebind the service TD.  It gets back a binding handle.  
The VMM communicates the binding handle, target TD_UUID and other binding 
parameters to the se rvice TD.  
Ref. # 348552 -004US  54 
NOT_BOUND PRE_BOUND
TDH.SERVTD.PREBIND
[OP_STATE in {UNINITIALIZED, INITIALIZED}]
BOUNDTDH.SERVTD.BIND
[SERVTD_INFO_HASH, SERVTD_TYPE
and SERVTD_ATTR match
(per SERVTD_ATTR)]TDH.SERVTD.BIND 
Figure 5-2:  Service TD Binding State Machine  
 
For more detail on service TD, please refer to Intel TDX module  Specification.  
5.6 TD Live Migration  
Analogous to legacy VM migration,  a cloud -service provider (CSP) may want to 
relocate/migrate an executing Trust Domain from a source TDX platform  to a destination 
TDX platform  in the cloud environment.  A cloud provider may use TD migration to meet 
custom er Service Level Agreement (SLA), while balancing cloud platform upgradability, 
patching and other serviceability requirements.   
Since a  TD runs in a CPU mode that  protects the confidentiality of its memory contents and its 
CPU state from any other platfo rm software, including the hosting Virtual Machine Monitor 
(VMM ), this primary security objective should be maintained while allowing the TD resource 
manager, i.e., the host VMM to migrate TDs across compatible platforms .  The TD typically may 
be assigned a different HKID (and will be always assigned a different ephemeral key) on the 
destination platform chosen to migrate the TD.  
The TD being migrated is called the source TD , and the TD created as a result of the migration 
is called the destination TD .  An extensible TD Migration Policy  is associated with a TD that is 
used to maintain the TD’s security posture.  The TD Migration policy is enforced in a scalable 
and extensible manner using a specific type of Service TD  called the Migration TD (a .k.a. 
MigTD)  – which is used to provide services for migrating TDs.  
The TD Live Migration process (and the Migration TD) does not depend on any interaction with 
the TD guest software operating inside the TD being migrated.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  55 Figure 5 shows the lifecycle of a TD Live  Migration process and the corresponding Intel TDX 
module  APIs involved.  
TDX -controlled Blackout period
MEM
MEM 
(CANCEL)
TRACKTD may run on source Optional software -controlled downtime
(if cold migration is used)
MEM
(MIGRATE)TDH.EXPORT.
(UN)BLOCKW
MEM
(CANCEL)TDH.EXPORT.
TRACK
TD may run
on destination
Source
Platform
TDCONFIGKEYTDCONFIGKEYTDH.MNG.
CREATE
(legacy)TDH.MNG.
(legacy)
HKIDper packageTDH.MNG.
ADDCX
(legacy)TDH.IMPORT.
STATE.
IMMUTABLE
per TDCS pageTDH.EXPORT.
STATE.
IMMUTABLE
TD 
Immutable 
Config
Target
Platform
Reservation Pre-MigrationTDH.IMPORT.
TRACK
(consumes 
epoch token
–starts Out-of-
orderTDH.
EXPORT.
PAUSE
tokenTDH.EXPORT.
MEM
(MIGRATE)
MEM
Iterative pre -copy CommitmentTDH.IMPORT.
STATE.VP
STATE.TD
At this point migration is 
enabled for this TD and MigTD 
is bound to TD for attestation
MigTD 
Verifies Mig 
Policy via
TDH.SERVTD.
RDMigTD 
Policy via
TDG.
SERVTD.
RD
TD Migration 
Transport
Session
At this point the TD has been paused –
final state can be migrated and memory 
reclaimed -unless migration fails
per TD
per mig. pageper vcpu
per TDMigTD sets Mig key
TDG.SERVTD.WRTDH.EXPORT.
STATE.VP
STATE.TD
per TDper TDTD 
memory 
stateMutable 
TD VP 
State and 
TD stateTDH.MNG.
CREATE/
KEY.CONFIG/
ADDCX
(legacy)TDH.MNG.INIT
Attr.
Migratable
=1TDH.SERVTD.
[PRE]BIND
(TD,Mig TD)
[PRE]BIND
(MigTD, TD)
Stop and copy control stateTDH.EXPORT.
TRACK
(generates
Epoch Token 
–ends in order)TDH.EXPORT.
MEM
Data (TD 
Migration 
Session
Key)
MEM
Post -copyPending
TD memory 
state
Post -copyper mig. 
pageTD
memory 
state
MEMTDH.
EXPORT.
ABORT
(TD 
unpaused)
Src
TD
TeardownTDH.EXPORT.
MEM
Post -copytoken
TDH.
IMPORT.
MEM
(CANCEL)
MEM 
(CANCEL)
per mig. pageTDH.
IMPORT.
COMMITTDH.
EXPORT.
RESTORE
TRACK
TRACKMigTD sets Mig key
TDG.SERVTD.WR
TDH.MIG.STREAM.
CREATETDH.MIG.STREAM.
CREATE
 
Figure 5-3: TD Migration Lifecycle Overview  
 
5.6.1  Pre-Migration  
5.6.1.1  Intel TDX module  Enumeration  
The host VMM uses SEAMCALL[ TDH.SYS. RD] or SEAMCALL[TDH.SYS.RDALL]  to enumerate 
Intel TDX module  functionality and learns from the TDX_FEATURES that the Intel TDX module  
supports TD Migration . 
5.6.2  Reservation and Session Setup  
5.6.2.1  Source  Guest TD Build and Execution  
The host VMM uses SEAMCALL[TDH.MNG.INIT] function to initialize a TD, with 
ATTRIBUTES.MIGRATABLE  bit set to 1.  
Before a migration session can begin, the VMM on the source platform must use 
SEAMCALL[TDH.SERVTD.BIND] to bind a Migration TD to the source TD.  
5.6.2.2  Destination  Guest TD Initial Build  
The host VMM creates a new guest TD by using the SEAMCALL[ TDH.MNG.CREATE ] function.  
This destination TD is set up  as a “template” to receive the state of the Source Guest TD.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
TD-VMM -Communication Scenarios

Ref. # 348552 -004US  56 The host VMM programs the HKID and HW -genera ted encryption key assigned to the TD into 
the MKTME encryption engines , using the  SEAMCALL[ TDH.MNG.KEY.CONFIG ] function on 
each package.  
The host VMM can then continue to build the TDCS by adding TDCS pages using the 
SEAMCALL[ TDH.MNG.ADDCX ] interface func tion.  
Once the destination TDCS is built and before TD import can begin, the VMM on the 
destination platform must use SEAMCALL[TDH.SERVTD.BIND] to bind a Migration TD to the 
destination TD.   
5.6.2.3  Migration Session Key Negotiation  
The host VMMs in source platform and  destination platform notify the MigTD on the source 
and destination platform on the migration request.  
The MigTDs executing on the source and destination platforms use a TD -quote -based mutual 
authentication protocol to create a VMM -transport -agnostic secu re session between them, 
such as remote -attestation TLS (RA -TLS). Using this secure session, the migration policy can 
be evaluated by the MigTDs. After  a policy check, the Migration TD transfer s the Migration 
Session Key (MSK) to the peer. The MSK is an ep hemeral AES -256-GCM key used for 
confidentiality and integrity of the TD private state exported from the source platform and 
imported on the destination platform.   
The Service TD binding mechanism supported by the TDX module allows the Migration TD to 
access target TD metadata – specifically the Migration Session Key.  The MigTD can read/write 
the TD metadata using TDCALL[TDG.SERVTD.RD/WR*] guest -side interface functions.  The 
Migration TDs on both the source and destination platforms must use this interfa ce to 
read/write the Migration Session Key (as metadata ) to the target TD’s control structures.  
After this point, the host VMM can invoke TDX module  functions such as 
SEAMCALL[TDH.EXPORT.*] to export state at the source platform and 
SEAMCALL[TDH.IMPORT.*] to import TD state at the destination platform.  
5.6.2.4  TD Global Immutable Metadata (Non -Memory  State ) Migration  
Immutable metadata is the set of TD state variables that are set by 
SEAMCALL[TDH.MNG.INIT], may be modified during TD build but are never modified aft er the 
TD’s measurement is finalized using SEAMCALL[TDH.MR.FINALIZE]. Some of these state 
variables control how the TD and its memory are  migrated. Therefore, the immutable TD 
control state is migrated before any of the TD memory state is migrated.  
The hos t VMMs use SEAMCALL[TDH.EXPORT.STATE.IMMUTABLE] to export TD immutable 
state at the source platform and use SEAMCALL[TDH.IMPORT.STATE.IMMUTABLE] to import 
TD immutable state at the destination platform.  
Ref. # 348552 -004US  57 5.6.3  Iterative Pre-Copy of Memory State  
5.6.3.1  Migration Conside rations for TD Private Memory  
Intel TDX helps protect guest TD state in private memory from a malicious VMM, using 
MKTME (memory encryption and integrity protection) and the Intel TDX module .  The Intel 
TDX module  performs ephemeral key ID management  to enforce the TDX security objectives.  
Memory encryption is performed by encryption engines that reside at each memory 
controller , with no software access (including the TDX module) to the ephemeral keys .  The 
memory encryption engine holds a table of encryption keys, in the Key Encryption Table (KET).  
The encr yption key selected for memory transaction s is based on a Host Key Identifier (HKID)  
provided with the memory access transaction.  
The Intel TDX module  API functions enable the host VMM  to manage HKID assignment to 
guest TDs, configure the memory encryption  engines etc., while assuring proper operation to 
maintain TDX’s security objectives.   The host VMM also does not have access to the TD 
encryption keys.  
TD Migration do es not migrate the HKID s – a free HKID is assigned to the TD created on the 
destination platform to receive migratable assets of the TD from the source platform.  All TD 
private memory is protected during transport from the source platform to the destination 
platform using an intermediate encryption performed using the MSK negotiated via the 
Migration TDs on the source and destination platform.   
On the destination platform , the memory is encrypted via the destination ephemeral key as it 
is imported into the destination platform memory assigned to the destination TD.  The import 
operation on t he destination TDX module verifies and decrypts the TD private data using the 
MSK and  uses the MKTME engine to encrypt (and integrity protect) while writing it to memory 
using the destination TD HKID.  
Shared memory assigned to the TD is migrated using lega cy mechanisms used by the host 
VMM.  
5.6.3.2  Migration Considerations for EPT Structures  
Guest Physical Address (GPA) space is divided into private and shared sub -spaces, determined 
by the SHARED bit of GPA.  The CPU translates shared GPAs using the shared EPT, w hich 
resides in host VMM memory, and is directly managed by the host VMM, same as with legacy 
VMX. The CPU translates private GPAs using a separate Secure EPT.  Secure EPT pages are 
encrypted, and integrity protected with the TD’s ephemeral private key.  
As there is no guarantee of allocating the same physical memory addresses to the TD being 
migrated on the destination platform, the memory used for Secure EPT structures is not 
migrated across platforms .  Hence, the VMM must invoke the TDX module’s 
SEAMCALL[ TDH.MEM.SEPT.*] interface functions on the destination platform to re -create the 
private GPA mappings on the destination platform (per the assigned HPAs).  The Intel TDX 
module uses the cryptographically protected exported metadata  (generated via Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  58 SEAMCALL[ TDH.EXPORT.MEM]) to verify and enforce (via the SEAMCALL[TDH.IMPORT.MEM]) 
that the Secure EPT security properties from the source platform are recreated  correctly as TD 
private memory contents are migrated, thus helping prevent remap attacks during migration.  
Even though S ecure EPT structures are not migrated, the source SEPT structures track the 
state of the mappings when a page is exported and then modi fied by the TD OS in the pre -
copy stage.  The TD OS may be allowed to modify such a page and the TDX module enforces 
that the modified  and previously exported page is re -exported by the  source host  VMM  and 
re-imported by the destination host VMM.  
5.6.3.3  Post Copy :  Destination  Guest TD Execution during Memory Migration  
In a typical live migration scenario, the TD is expected to resume executing on the destination 
platform shortly after it is paused on the source platform.  The destination TD can only begin 
executi ng after the pre -copy stage completes and the destination TD control state has been 
imported – memory transfer may continue after that in a post -copy stage.   
The p re-copy stage imports the working set of memory pages ; the host VMM must have 
paused the sou rce TD, exported the final mutable control state , and imported the final 
mutable control state to the destination TD virtual processors and control state.  The Intel 
TDX module enforces the security objectives of this Commitment protocol, with the remainin g 
memory state transferred in the post -copy stage , which also happens via TDX module  
interfaces SEAMCALL[TDH.EXPORT.MEM] and SEAMCALL[TDH.IMPORT.MEM].  
5.6.4  Source TD Stop and Final Non -Memory State Migration   
Following pre -copy of TD private memory, the host V MM must pause the source TD for a brief 
period (also called the blackout period) so that the VMM may export the final control state (for 
all VCPUs and for the TD overall).  The VMM initiates this via SEAMCALL[TDH.EXPORT.PAUSE], 
which checks security pre -conditions and helps prevent TD VCPUs from executing anymore .  It 
then allows export of final (mutable) TD non -memory state.  
5.6.4.1  Final Memory State Migration  
The host VMMs use SEAMCALL[TDH.EXPORT.MEM] and SEAMCALL[TDH.IMPORT.MEM] to 
migrate memory contents during this source (and destination) TD paused state.  The TDX 
module  enforces that all exported state for the source TD must be imported before the 
destinat ion TD may run using the commitment protocol described below.  
5.6.4.2  TD-Scope and VCPU -Scope Mutable Non -Memory State migration  
TD mutable non -memory state is a set of source TD state variables that might have changed 
since it was finalized via SEAMCALL[TDH.MR.FI NALIZE]. Immutable non -memory state exists 
for the TD scope (as part of the TDR and TDCS control structures) and the VCPU scope (as part 
of the TDVPS control structure).  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 

Ref. # 348552 -004US  59 Mutable TD state is exported by SEAMCALL[TDH.EXPORT.STATE.TD] (per TD) and 
SEAMCALL[TD H.EXPORT.STATE.VP] (per VCPU) and imported by 
SEAMCALL[TDH.IMPORT.STATE.TD] and SEAMCALL[TDH.IMPORT.STATE.VP] respectively.  
5.6.5  Commitment  
The commitment protocol is enforced by the Intel TDX module  to help ensure that a host 
VMM cannot violate the security ob jectives of TD Live migration.  
This protocol is enforced via the following TDX module  interface function s:  
• On the source platform, SEAMCALL[TDH.EXPORT.PAUSE] starts the blackout phase of TD 
live migration and SEAMCALL[TDH.EXPORT.TRACK] ends the blackout p hase of live 
migration (and marks the end of the transfer of TD memory pre -copy, mutable TD VP and 
mutable TD global control state). SEAMCALL[TDH.EXPORT.TRACK] generates an MSK -
based cryptographically -authenticated start token to allow the destination TD t o become 
runnable. On the destination platform, SEAMCALL[TDH.IMPORT.TRACK] – which 
consumes the cryptographic start token, allows the destination TD to be un -paused.  
• In error scenarios, the migration process may be aborted proactively by the host on the 
source platform via SEAMCALL[TDH.EXPORT.ABORT] before a start token was generated . 
If a start token was already generated (i.e. pre -copy completed), the destination platform 
can generate an abort token using SEAMCALL[TDH.IMPORT.ABORT] . This generates an 
abort token that may be consumed by SEAMCALL[TDH.EXPORT.ABORT] from  the source 
TD platform TDX module , to abort the migration process and again allow the source TD to 
become runnable.  
5.6.6  Post -Copy of Memory State  
In some live migration scenarios, the host VMM may stage some memory state transfer to 
occur lazily after the destination TD has started execution.  In this case, the host VMM will be 
required to fetch the required pages as accesses occur by the destinati on TD – this order of 
access is indeterminate and will likely differ from the order in which the host VMM has queued 
memory state to be transferred.  
In order to support that on -demand model, the order of memory migration during this post -
copy  stage  is not enforced by TDX.  The host VMM may implement multiple migration queues 
with multiple priorities for memory state transfer.  For example, the host VMM on the source 
platform may keep a copy of each encrypted migrated page until it receives a confirmation 
from the destination that the page has been successfully imported.  If needed, that copy can 
be re -sent on a high priority queue.  Another option is, instead of holding a copy of exported 
pages, to call SEAMCALL[TDH.EXPORT.MEM] again on demand.  
Also, to simp lify host VMM software for this model, the TDX module interface functions used 
for memory import in this post -copy stage return additional informational error codes to 
indicate that a stale import was attempted by the host -VMM to account for the case where  the 
low-latency import operation for a GPA superseded the import from the higher latency import 
queue.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.5 
Ref. # 348552 -004US  60 For more detail on TD Live Migration, please refer to Intel TDX module  TD Migration 
Specification and Migration TD design guide . 
 
~~ End of document ~~  White Paper 
 
Intel® Trust Domain Extensions  
 
Table of Conten ts 
01. Introduction ................................ ... 1 
02. Intel TDX –  
Technica l Explanatio n .......................  2 
A. MEMORY CONFIDENTIALITY  
AND INTEGRITY  ..............................  3 
B. ADDRESS -TRANSLATION  
INTEGRITY  ................................ ........  4 
C. CPU -STATE  CONFIDENTIALITY  
AND INTEGRIT Y ...............................  5 
D. SECURE INTERRUPT AND  
EXCEPTION DELIVERY  ...................  5 
E. REMOTE ATTESTATION  ............  6 
F. LIVE MIGRATION  .........................  7 
G. TD PARTITIONING  ......................  8 
H. VM PRESERVING UPDATES  ...... 8 
03. Threat Model Overview  ..............  8 
04. Summar y................................ ........  8 
 01. Introduction 
Providing better protection for data in the enterprise  and cloud environment s has 
long been a high concern of IT departments, governments, and users of personal 
services. The rise in number and size of data breaches has highlighted how much 
personal data  is essential to many businesses and services that we ha ve become 
dependent on and how this datafication is being monetized by many companies. The 
security concern s around this datafication trend  were  further heightened  in 2013 
when Edward Snowden made revelations about unwarranted access to data.  
The reaction to this datafication trend by the major technology companies is changing 
their stances on the protection and privacy of data they are processing as being an 
import ant asset to protect. So much that big technology providers are now turning 
privacy into a ma rketable advantage, and the increase in the distrust of third -party 
processing vendors has increased that some are looking to become blind to the 
computations they  host.  
The release of Intel(r) Software Guard Extensions (SGX) in 2015 , put the ability to do  
application computations that were much harder to introspect by the owner of the 
platform within reach of every -day PC platforms and their server derivatives, and  it 
sparked a paradigm and a race to build -out ecosystems where this could be done at 
scale. We call this paradigm Confidential Computing.  
The main premise behind this paradigm is that those that are controlling the platform 
and those that have data on the  platform being processed are two separate entities. In 
typical installations the platform ow ner has full access to what is being processed on 
the platform. This is the hierarchical nature of memory management and access 
control on modern computing platfor ms. 
In this paper we introduce Intel® Trust Domain Extensions (I ntel® TDX). An 
architectural technology  to deploy ha rdware-isolated, Virtual Machines (VMs) called 
Trust Domains (TDs).  Intel TDX is design ed to iso late TD VMs from the Virtual-
Machine Manager (VMM), hypervisor and other no n-TD software on the host 
platform. Intel TDX may  be used  to enhance confidential computing  by helping 
protect TDs from a broad range of software attacks and which also helps reduce  the 
TD Trusted Computing Base (TCB) . Intel TDX is designed to enhan ce a platform 
user’s  control of data security and IP pr otection. Intel TDX can also enhance the 
Cloud-Service Pro viders (CSP) ability to provide managed cloud services without 
exposing tenant  data to adversaries . 
In this paper we describe Intel TDX technology and how it forms one of the pillars of 
our Confidential Compute offering . We provide details of how it helps provide 
memory confid entiality and integrity, address translation integrity, CPU state 
confidentiality and integrity, secure interrupt and exception delivery, and remote 
attestation  support . Finally , we provide a summary of the threat  model and  
mitigations against common softw are and hardware attacks provided by TDX . 
 
  White Paper | Inte l® Trust Domai n Extensions  
2  
 
02. Intel T DX – Technical Explanation 
The Intel-TDX solu tion is bui lt using a combin ation of Intel 
Virtual Machine Extensions (VMX) in struction-set-
archi tecture ( ISA) extension s, Intel total memory-
encryption multi -key, (Intel® TME -MK) technolo gy, and a 
CPU-attested software m odule. 
Intel TDX solu tion can pro vide the foll owing capabi lities to 
TDs: 
• Memory and CPU state confidentiality and i ntegrity to  
help keep the s ensitive IP and workload d ata secure 
from mo st software-based attacks and many ha rdware-
based attacks. The workload n ow h as a tool that 
supports excluding the f irmware, software, devices, and 
operators of the clo ud p latform from the trusted-
compu ting b ase (TCB). The workloads can use this tool 
to fo ster more s ecure a ccess to CPU in structions, 
security, debug, and other technologie s.  The workload 
can n ow h ave this abi lity irrespective of the clo ud 
infrastructure us ed to d eploy the workload. 
• Remote attestation enables a r elying pa rty (either the 
owner of the workload or  a us er of the s ervices pro vided 
by the workloa d) to e stablish that the workload is  
running on an I ntel-TDX-enabl ed platform located within 
a TD p rior to pro viding  that workload  data. Remote 
attestation aims to all ow the owners and consumers of 
the s ervice to digi tally d etermine the v ersion of the TCB 
on which they are  relying on to help secure their data. 
Intel TDX also augm ents defense of the TD against limited 
forms of attacks that use physi cal access to the p latform 
memory, such as off line, dynami c-rando m- access m emory 
(DRAM) analysis (e.g., cold-boot attacks) and a ctive attacks 
of D RAM i nterfaces, incl uding captu ring, m odifying,

of D RAM i nterfaces, incl uding captu ring, m odifying, 
relocating, splicing, and a liasing m emory contents. Intel 
TDX does n ot defend against replay of memory through 
physi cal attacks. 
 
Figu re 1 Trust Boundaries for TDX 
 
The VMM continues to be the resour ce man ager, and TDs 
do n ot have p rivileges to d eny s ervice to the VMM. 
Protecting a TD against denial of service by the VMM is n ot 
a security obj ective of Intel TDX. 
To help en force t he security p olicies for the TDs, a new 
mode of t he CPU c alled Se cure-Arbitration Mo de (SEAM) is 
introduced to host an Intel-provided, digitally sign ed, but 
not e ncrypted, security-services module. T he Intel-TDX 
module is hosted in a reserved, memory space identified  by t he SEAM -range register ( SEAMRR). Und er the desig n, 
the CPU only allows access to SEAM -memory range to 
softw are exe cuting insid e the SEAM -memory range, and all 
other softw are accesse s and direct-memory access (DMA) 
from devices to t his memory range are aborted. SEAM is 
also design ed to not have any memory-access privileges to 
other protected, memory region s in the platform, including 
the System -Management Mo de (SMM) memory or Intel® 
Softw are Gu ard Exte nsion s (Intel® SGX) protected memory 
(Figur e 5.2).  
 
Figu re 2 SEAM Module Flow 
 
The SEAM -memory r ange offers cryptographi c 
confidentiality protect ion usin g AES in XTS mode with an 
ephemeral 128 -bit, memory-encryption ke y and can 
operate in one of two available modes for memory 
integrity protection (to enable various memory 
configurations). Memory integrity may be enforced by 
either (the default) c ryptographic-integrity protect ion 
scheme or a log ical-integrity protection scheme. The 
cryptographic -integrity scheme uses a S HA-3-based, 
mes sage-authentication code ( MAC) (28-bit) that helps 
prevent host/system software accesses as well as detects 
state -tamper from software (e.g. , rowhammer) and some 
hardwa re attacks. The logical -integrity protection scheme 
is designed to prevent host/system software accesses 
only . 
In o rder to in stall the m odule for I ntel TDX, a ne w, Intel® 
Trusted Execution Technolo gy (Intel® TXT) authenticated- 
code m odule (ACM), called the SEAM Load er (SEAMLDR), is 
provided to h elp verify the digi tal sign ature on the I ntel 
TDX m odule and load it i nto the S EAM-memory range. By 
desig n, the me asurement and s ecurity-version num ber 
(SVN) of the m odule are r ecorded into har dware-
measurement registers by the S EAMLDR and then load ed 
into S EAM-memory range in res ponse to the VMM 
invo king the S EAMLDR ACM in o rder to load the m odule, 
which h as no persistence. The clo ud- service provider can 
additionally apply i ts own s ecurity policies on the 
acceptable version of Intel TDX that should be load ed on 
its servers.  
A S EAMCALL in struction i ntroduced for the VMM is 
design ed to p lace the CPU in S EAM-VMX-root operation 
and invo ke the m odule. The Intel TDX m odule is design ed 
to pro vide an  interface to the VMM to cre ate, delete, and 
schedule execution of TDs. The Intel TDX m odule a cts as 
the trusted intermediary  to h elp impl ement security 
policies, actions, and n ecessary mitigations for the TDs. 
White Paper | Inte l® Trust Domai n Extensions  
3  
 As pa rt of TD cre ation, the VMM pro vides the m emory 
pages for the TD code, data, and TD-associated-metadata 
structures such as the virtual-machin e-control structure 
(VMCS) and the state-save area us ed to save the TD state 
when it is n ot executing. 
Intel TDX uses I ntel® 64 archi tecture, incl uding the VMX 
archi tecture, to h elp man age the TDs. The I ntel-TDX 
module is design ed to perform VM entry to S EAM-VMX, 
non-root operation using VMRESUME and VMLAUNCH-
VMX instructions to execute the TD. 
The I ntel-TDX m odule h elps ensure that the execution 
controls active for a TD do n ot allow the VMM or other 
untrusted entities to i ntercept TD accesses to TD-assign ed 
resour ces like control r egisters, model-specific registers 
(MSRs), d ebug r egisters, performan ce-monito ring 
counters, Time-Stamp Counter, etc. The TDX m odule aims 
to impl ement security policies for the TDs. An example of 
such policy would be the m odule using the Indir ect-
Branch- Prediction Barrier (IBPB) when switching TDs to 
help keep a TD-indir ect-branch pr ediction from being 
influenced by code in a pr eviously executed TD. 
The TD would h ave full use of debug and performan ce- 
monito ring feature s if such use is authorized for the TD at 
creation. If they are n ot authorized, these features would 
be di sabled when the TD executes. Debug and 
performan ce monito ring attributes of the TD are incl uded 
in the TD- attestation r eport. 
Intel TDX is design ed to all ow a VMM to limit the features 
made available to the TD for various re asons like 
virtualizing the har dware capabi lities. Intel TDX can re strict 
capabi lities of the VMM to either hide o r all ow the TD to 
use the feature. If the VMM chooses to all ow the TD to use 
the feature, Intel TDX seeks to pr event the VMM from 
modifying the enum erations and i nformation pro vided by 
instructions like CPUID, capabi lity MS Rs, and control 
registers when accessed by the TD. The TD aims to r eliably 
use these ha rdware in structions without n eeding s pecial, 
operating-system m odifications but with simi lar 
performan ce that software in a l egacy VM would expe ct. 
Intel TDX is design ed to enforce execution controls on  the 
TD to cause execution of certain in structions like IN /OUT, 
HLT, RD/WRMSR, etc. in a TD to then cause a Virtualization 
Exception (#VE) to the TD OS, so that these instr uctions  can 
be emulated by the TD OS in a s ecure mann er for the TD 
software. 
The i ntention is that a VM exit to enter SEAM-VMX-root 
operation occurs in res ponse to certain in structions and 
events in S EAM-VMX-non-root operation. A TDCALL 
instruction is pro vided to h elp the TD call for s ervice by 
enabling a VM exit to the m odule. 
When a TD exits to the m odule, the m odule is design ed to 
save registers (e.g., the general-purpose r egisters, control 
register, MS Rs, debug r egisters, performan ce-monito ring 
counters, extended-state registers, and other CPU state 
associated with the TD) into the state-save area all ocated 
for that TD. The m odule then sc rubs these r egisters before 
returning execution control to the VMM, to h elp pr event 
leakage of TD state. When a TD is subsequently re sumed, 
the CPU state of the TD is mea nt to be restored from this state- save area by the m odule. 
A SEAMREPORT instruction is i ntroduced for the Intel TDX 
module to h elp cre ate an evidence structure—a report— 
that is c ryptog raphi cally bound to the p latform ha rdware 
with a MAC. The report structure cre ated by SEAMREPORT 
subsequently h elps generate a r emote-attestation qu ote. 
A SEAMRET in struction is i ntroduced for the m odule to 
return execution control to the VMM. 
Intel TDX 1.0 was  design ed to pro vide a TD the foll owing 
capabi lities: 
A. Memor y Confidentialit y and Integrit y 
B. Address -Translatio n Integrit y 
C. CPU -State Confidentialit y and Integrit y  
D. Secure Interrupt and Exception Delivery  
E. Remote Attestation 
Future updates will be looking to  bring new features to the 
Intel TDX module, n amely:  
F. Live Migrat ion 
G. TD Partit ioning  
H. VM Preserving Update s 
A. MEMORY CONFIDENTIALITY AND INTEGRITY 
CRYPTOGRAPHY. 
 
Intel TDX uses the TME -MK engine to enable m emory 
encryption and enhan ces it by a dding modes for integrity 
protection. Intel TDX may be enabled with a 
cryptog raphi c-integrity pr otection mode using a S HA-3 
based MAC (28-bit) on each cache line in a ddition to AES-
XTS 128-bit memory encryption. In this mode, SHA-3-256 
(KECCAK [512]) is used as  the underlying function for MAC 
generation with  the 256b output truncated to 28b for 
storage and v erification. To help prevent ciphertext 
disclosure, a 1 -bit TD -ownership tag is maintained  with 
each cache line to identify if the line is associated with a 
memory page assigned to a TD. In this mode, the TD-
ownership -bit is included in the MAC. Optionally, a logical -
integrity mode may be used , which maintain s the 1-bit TD-
ownership tag, however there is no cryptographic MAC 
maintained per cache line in th e logical -integrity  mode . 
Each key supported by TME -MK is id entified by a KeyID or 
key identifier. The CPU is design ed to pro vide a PCONFIG 
instruction us ed by the I ntel-TDX m odule to prog ram a 
CPU- generated, uniqu e, and ephemeral AES-XTS 128-bit 
key to each KeyID. The keys prog ramm ed into the TME -MK 
are tailor ed not to be accessible by s oftware or by using 
external i nterfaces to an S OC. 
FUNCTIONAL SHAR ING OF KEYID(S).  
The s et of KeyID(s) supported by TME -MK can be 
partitioned into two groups of KeyID(s) —a set of private

partitioned into two groups of KeyID(s) —a set of private 
KeyID(s) and a s et of Shar ed KeyID(s). PCONFIG is des igned 
to only al low private KeyIDs to be prog ramm ed with keys 
when called from  SEAM m ode ( i.e., by the TDX-SEAM 
module). White Paper | Inte l® Trust Domai n Extensions  
4  
 TD ACQUIRING KEYID(S).  
On TD cre ation, the m odule is i ntended to assign each TD 
a uniqu e, private KeyID (Fi g. 3.) 
Figure 3 
ACCE SS CONTROL TO PRIVATE KEYID(S).   
The CPU is design ed to di sallow software other than the 
Intel TDX m odule and TDs from ma king m emory accesses  
using a p rivate KeyID. A ttempting to a ccess a p rivate KeyID 
by s oftware ou tside the S EAM m ode would cause a p age-
fault exception ( #PF). Simi larly, DMA from d evices using a 
private KeyID would be aborted. 
 
MEMORY ENCRYPTED BY PRIVATE KEYID(S). 
 
The TD-ownership bit associated with the line in m emory 
seeks to d etect software or d evice attempts to read 
memory encrypted  with p rivate KeyID, us ing a shar ed 
KeyID, to r eveal the ciph ertext. On such invalid accesse s, 
the TME -MK r eturns a f ixed p attern to help pr event 
ciph ertext analysi s. 
When cryptographic -integrity protection  is enabled, the 
MAC helps ensure that the TD reads  back the same data it 
had last written to i ts private m emory. If the m emory 
integrity was violated per the attack model , then a 
subsequent access by a TD to that corrupted m emory 
would lead to a MAC-verification failur e. With logical -
integrity a similar p roperty is obtained fo r software attacks 
based on access control via the TD -ownership bit.  
A MAC -verification or a TD -ownership check failure would 
be fatal to the TD and lead to i ts termination, but other 
TDs and p latform s oftware would n ot be impa cted. 
Encryption  of TD-private m emory helps d efend against 
some c lasses of physi cal attacks on memory  (e.g., cold-
boot attacks). Cryptographic -integrity mode adds 
cryptographic defense to defend against software tamper 
attacks (e.g. , rowhammer) and some hardware -based 
corruption attacks. In contrast, the logical -integrity mode 
is designed to pre vent software access to TD ciphertext.  
Sophi sticated attacks such as  replay of m emory via physi cal access are not detected or pr otected-against by 
the cu rrent generation of memory protection for  Intel TDX. 
 
B. ADDRESS-TRANSLATION INTEGRITY.  
TDs h ave a ccess to two classes of m emory—private 
memory th at holds the confidential data of the TD and 
shared memory us ed to communi cate with u ntrusted 
entities external to a TD. The p rivate m emory of the TD 
improves c ryptog raphic confidentiality and i ntegrity 
protection using a uniqu e, ephemeral-memory-encryption 
key assign ed to that TD. 
Figure 4 
Shar ed m emory is us ed to communi cate with the agents 
outside the TD to perform I/O operations such as network 
access, storage services, invo king h ypervisor s ervices, etc. 
The highe st ord er bit of the gue st-physi cal address (GPA) 
is design ated as a “Shar ed” bit in o rder to indi cate if that 
GPA m aps p rivate m emory (when “Shar ed” bit is 0) or 
maps shar ed m emory (when “Shared” bit is  1). The TD is 
design ed to l ocate all its private code and d ata in p rivate 
memory  map ped using a p rivate GPA. The TD- assign ed, 
private key helps encrypt and integrity-protect all m emory 
accesses that use GPA with “Shared” bit s et to 0. All 
shared-memory accesses that use GPA with “Shar ed” bit 
set to 1 m ay be encrypted and i ntegrity-protected with the 
aid of a shar ed key that the hypervisor man ages (Figure 5). 
The VMM h elps all ocate and m ap memory us ed by the TDs 
into the GPA of the TD using an  extended-page table ( EPT) 
that provides the GPA to physi cal-address ( PA) translation. 
When a TD is executing, the design design ates that two 
EPTs will be active for the TD: a s ecure EPT us ed to 
provide p rivate GPA to PA translations and a shar ed EPT 
used to pro vide shar ed GPA to PA translations (Figure 6). 
5  
 Figure 5 
The Intel -TDX module helps provide secure -EPT 
management functions to the VMM to add or remove  
mappings from the secure EPT and enforce security 
policies aroun d those operation with the aim of preserving 
the integrity of the m emory layout. The m emory us ed to 
build s ecure EPT is design ed to be encrypted and 
integrity- protected using the uniqu e, per-TD, m emory-
encryption key. 
The CPU h elps pr event a TD from l ocating p age-table 
structures and executable code in shar ed m emory. CPU 
would cause a p age fault (#PF) on code fetches or p age- 
table a ccesses if they are in shar ed memory. 
Figure 6 The Intel-TDX m odule is design ed to mai ntain a tracking- 
data structure called Physi cal-Addres s-Metadata Table 
(PAMT) so that a p age map ped into the s ecure-EPT of a TD 
cannot be map ped into s ecure EPT of any other TD. The 
module for I ntel TDX also uses PAMT to h elp map a p age 
to only one GPA in the s ecure EPT and pro vide functions to 
the VMM to a dd 4K, 2M, or 1G translations to the s ecure 
EPT. This m odule is then design ed to track the p age sizes 
and page types in the PAMT to track the correctness of  the 
secure -EPT operations and the required invalidations  of 
TLB entries when a p age is unmap ped from the s ecure 
EPT. The PAMT helps ensure that all m emory all ocated to a 
TD is initialized to a known state before f irst access by the 
TD. 
Virtual a ddress translated to physi cal a ddresses using  
either the s ecure EPT or shar ed EPT would be cached in 
the CPU TLB. The TLB is desi gned to associate a tag with 
the translation to id entify the TD that cre ated the 
translations. 
The s ecure-EPT-based, addres s-translation archi tecture  
enables mapping large/huge pages into the s ecure /shar ed 
EPT as well as caching the translations as large/huge 
pages when approp riate. Address translations for a TD are 
simi lar to  a legacy VM and involve two levels of page walk. 
Therefore, software in a TD would incur simi lar ov erhead 
as compar ed to addres s-translation ov erhead for s oftware 
in a l egacy VM. 
C. CPU-STATE CONFIDENTIALITY & INTEGRITY  
When a TD is cre ated, the m odule for I ntel TDX would 
require the VMM to pro vide a s et of memory pages to be 
used to ho st the virtual-machin e-control structures 
(VMCS), the state- save area for the TD, etc. The goal of the 
module is to use i ts page-allocation trackers to enforce 
that these p ages h ave n ot been simultaneously  assign ed to 
other TDs by the VMM. The Intel-TDX m odule would then 
initialize and configure these structures using the TD-
assign ed, private key to h elp pro vide c ryptog raphic 
confidentiality and i ntegrity pr otection to the TD-CPU 
state (Figure 7). 
D. SECURE INTERRUPT & EXCEPTION DELIVERY 
Interrupts and exception d elivery to the TD are design ed 
to use the VMX-APIC virtualization and virtual-interrupts 
architecture. The APIC-virtualization archi tecture aims to 
provide CPU emulation of many r egisters of the APIC, track 
the state of the virtual APIC, and d eliver virtual interrupts. 
The CPU would do a ll the a bove in VMX-non-root 
operation without r equiring a VM exit from the TD. The use 
of VMX- APIC virtualization and virtual-interrupts 
archi tecture would then d eliver interrupts into TD(s) 
efficiently and avoid the n eed for m odifications to the 
operating system in the TD to emulate the APIC. 
The goal of the CPU is to track the state of the virtual APIC 
using a virtual-APIC page and r elated state in the VMCS of 
that TD. The virtual-APIC page and the VMCS would be 
initialized by the I ntel-TDX m odule using  the TD-private 
key at TD cre ation. 
6  
  
The VMX-posted-interrupts-processing archi tecture is 
design ed to all ow a VMM or d evices to d eliver virtual 
interrupts dir ectly to a TD through a posted-interrupt 
desc riptor pr ocessed by the CPU ha rdware in res ponse to  
a n otification i nterrupt. The virtual i nterrupts in the 
posted- interrupt desc riptor would then be delivered to 
the TD through the virtual APIC by the CPU . The VMX 
archi tecture is enhan ced to h elp bl ock any attempts to 
deliver exception v ectors to a TD as virtual interrupts. 
Figure 7 
The TD-interrupt-virtualization archi tecture h elps d eliver 
interrupts into a TD without violating TD assump tions such 
as interrupt p riorities and m asking. The VMX archi tecture 
is design ed to di sallow injection of exceptions  into a TD. 
Intel- TDX m odule pro vides functions the VMM can use to 
deliver virtual, no n-maskable i nterrupt ( NMI) i nto a TD 
without violating the x86 NMI archi tecture. 
E. REMOTE ATTESTATION 
Remote attestation h elps a r emote pro vider (also known as 
a relying pa rty) have incre ased confidence that the 
software is running  inside a TD, on a genuin e, Intel-TDX 
system, and  at a g iven security level, which is a lso 
referenced as the TCB version. Attestation re sults can

Figure 7 
referenced as the TCB version. Attestation re sults can 
provide: 
Data that TDs associate with itself  • The goal is for this i nformation to be pro vided by the 
software i n the TD when requesting an attestation. For 
exampl e, the TD software mig ht incl ude the pub lic key it 
would like to use to communi cate with the r elying pa rty 
as pa rt of the attestation. 
TD Measuremen ts provided by Intel -TDX module 
• At TD cre ation, the I ntel TDX m odule is design ed to 
initialize the me asurement registers for the TD. As pa rt 
of the TD cre ation, the VMM would r equest the m odule 
to add a s et of pages to the TD. The m odule would then 
extend a static- measurement register called TD-
measurement register (TDMR) with the me asurements of 
the ini tial p ages a dded to the TD along with m etadata 
associated with these p ages. It a lso s eeks to pro vide the 
TD a s et of runtime-extendabl e- measurement registers 
(RTMR ) that would be extended by the code in the TD 
with me asurements of additional code and data at 
runtime. The goal of the attestation is to incl ude all 
measurement registers. 
Details of addi tional unm easured state provided by Inte l 
TDX module 
 
• Some states of the TD, like the attributes of the TD, 
identities of the TD owner (MROWNER), etc. would not 
be measured but included in the attestation results for 
the TD. 
 
SVNs of elemen ts in TDX TCB provided by CPU HW 
• Each element of the Intel-TDX TCB would be assign ed an 
SVN. A TCB is consid ered up to date  if all components of 
the TCB have SVNs greater than or equal to a thresho ld 
published by the author of the component(s). For the 
hardware, these SVNs are known collectively as the 
CPU SVN and include the SEAMLDR SVN. The module is 
design ed to be in the TCB of the TD, and the module’s 
SVN shou ld also be reflected in the attestation. 
 
A goal of Intel TDX is to use an Elliptic-Curve-Digital- 
Sign ature-Algorithm ( ECDSA)-based, asymmetric-
attestation key representing the I ntel-TDX-TCB version in 
order to sign  an assertion (a Quote) with the information 
listed a bove. Intel TDX was design ed so that, if a 
vulnerability is mi tigated or otherwise a ddress ed by an 
update to the p latform, relying pa rties can v erify that the 
update has been in stalled. The pr ocess of updating the 
platform attestation to r eflect the u pdate is called TCB 
Recovery. A ne w attestation key would be cre ated to 
reflect the u pdate in the p latform’s attestations. The new 
TCB would be reflected in  the attestations that occur 
following the replacement of the attestation key. 
The I ntel-TDX archi tecture is design ed to u tilize an I ntel- 
SGX enclave, called the TD-quoting enclave, to generate 
the r emote attestation for a TD. The CPU would pro vide a 
new instruction, SEAMREPORT, to be invo ked only by 
Intel-TDX m odule  and cre ate an evidence structure that is 
cryptog raphi cally bound to the p latform ha rdware for 
consump tion by the TD-quoting enclave. 
The S EAMREPORT in struction is design ed to take the 
attestation i nformation pro vided by the TD software, the 
TD me asurements, and a dditional i nformation pro vided by 
the I ntel-TDX m odule as input and generate a “Report” 
structure that incl udes the SVNs of the TDX-TCB elements.  
7 White Paper | Inte l® Trust Domai n Extensions   
  
Figu re 8 
 
This “Report” structure is design ed to be integrity-
protected using a MAC. The CPU would then pro vide an 
EVERIFYREPORT2 in struction to be us ed by enclaves to 
verify the MAC on the repo rt structure to help ensure the 
repo rt structure was created on the same p latform as the 
one on which it is executing. 
The TD-quoting enclave is design ed to then generate the 
Quote for the r eport using an asymmetric attestation key. 
When a TD receives an attestation r equest, shown in Fig 8,  
from an off -platform chall enger (1), the TD would then 
request the m odule pro vides the TD a r eport (2) that 
includes the attestation i nformation along with TD-
provided data. The I ntel-TDX m odule would a lso invo ke 
the S EAMREPORT instruction (3) to r equest the CPU 
generate a “Report” structure (4) that includes the TD-
provided data, the me asurements of the TD as mai ntained 
by the m odule, and SVNs of all elements in TDX TCB. The 
report structure is design ed to be hand ed to the TD (5), 
and then the TD would r equest the VMM (6) convert the 
report into a r emote attestation (a Quote) (7, 8, and 9) by 
the TD-quoting Enclave. The TD-quoting enclave would 
then verify the MAC on the report using EVERIFYREPORT2 
and convert the r eport, if v erified, into a Quote by signing 
the r eport using the TD’s asymmetric-attestation key. The 
Quote would n ext return to the chall enger (10). Finall y, the 
challenger is design ed to use an attestation-verification 
service (11 and 12) to perform qu ote verification. 
To support attestation i nfrastructure for I ntel TDX, Intel 
has bui lt a general-certification i nfrastructure, bui lt upon 
the I ntel® Software Guard Extensions D ata Center 
Attestation P rimitives (I ntel® SGX DCAP), to h elp certify 
TD-quoting Enclaves with a certificate chain ro oted to an 
Intel-issued certificate. The foun dation of this 
infrastructure, shown in Fi g. 9, is an I ntel-provided enclave 
called the Pro visionin g- Certification Enclave (PCE), which 
is design ed to a ct as a l ocal, Certificate Authority for l ocal 
TD-quoting Enclaves ( i.e., running on the same p latform as 
each other). The TD-quoting Enclave(s) would then 
generate their own Attestation Keys using their pr efer red 
method and a lgorithm (1). The TD- quoting Enclave aims to 
provide the PCE with the attestation- public key (2). The PCE is design ed to authenticate the r equest and is sue a 
certificate-like structure id entifying the TD-quoting 
enclave and the A ttestation Key (3). This structure would 
then be sign ed by a d evice and TCB-specific, signing key 
called the Pro visionin g-Certification Key (PCK). Intel aims 
to pub lish certificates and certificate-revocation lists 
(CRLs) for the PCKs in all genuin e, Intel platforms. This 
would re sult in a compl ete, sign ature chain from the 
Quotes to an I ntel-certification authority (CA) (4). The 
resulting Quote would be verified by an yone with the 
compl ete, certificate chain and CRLs.  
Platform configuration differences such as whether 
cryptographic vs. logical -integrity mode is enabled are 
reflected via the Pro visionin g Certificates.  
Figu re 9 
F. LIVE MIGRATION  
TDX Live Migration is analogous to legacy VM migration, 
where a cloud -service provider (CSP) may wa nt to 
relocate/migrate an executing Trust Domain from a source 
TDX platform to a destination TDX platform in the cloud 
environment. The Live Migration architecture enables the 
8 White Paper | Inte l® Trust Domai n Extensions   
 hypervisor to support this flow while maintai ning the 
primary security objective  of TD memory and CPU state 
confidentiality and integrity during migration across 
compatible platforms.  
G. TD PARTITIONING  
TD Partitioning provides the ability to support unmod ified  
or unenlightened  legacy VM  as TD, thus providing CSP 
customers with the ab ility to lift and shift workloads into 
hardware isolated VMs or Trust Domains (TDs) without 
having to make any changes to the Guest OS. TD 
Partitioning extends the base TDX arc hitecture by allowing 
TDs to contain multiple  virtual machines (VMs).  A TD may 
contain up to 4 VMs.  The primary VM (known as the L1 
VM) may act as a virtual machine monitor (known as the L1 
VMM).  Up to 3 nested VMs (known as the L2 VMs) serve as 
the gue st of the L1 VMM.  
H. VM PRESERVING UPDATES  
TD Preserving Architecture provides t he ability to update 
TDX Module at runtime, while persisting TD State and 
minimum TD interruption. The Trusted Compute Base 
(TCB) associated with each TD will be recovered and a new 
TCB tied to the updated TDX Module is c onsumed as part 
of new TD(s) launch  with subsequent attestation. Existing 
TDs and their relevant metadata state will be securely 
saved in encrypted memory owned by the ACM thus 
protecting the secure surface. For  Cloud Service Providers 
(CSP), using traditi onal TDX Module update methodologie s 
will require reboot on the node, resulting in downtime in 
orders of minutes on the platform and offered Cloud 
Services. TD Preserving Update Flows will furnish updates 
in ord ers of milliseconds, this making the 99.999% Cloud 
availability goal of CSPs att ainable.  
03. Threat Model  Overview  
In order to meet the goals of Confidential Computing , 
platform owners  need the ability to isolate tenant VMs 
(Workloads) from the VMM and o ther system software on 
the platform . 
In this context TDX architecture  consider s 2 primary 
adversaries:  
1. System Software Adversary: Administrative insiders ( e.g., 
DC Admin, developer  or technician), VMM, SMM, BIOS, 
which  can launch a malicious SW -only a ttempt to either

which  can launch a malicious SW -only a ttempt to either 
extract workload secrets and assets or spoof workload 
data/memory  in an operational environment . 
2. Hardware Adversary: CSP insiders ( e.g., technician) that 
can attemp t a HW attack to extract Cloud Tenant’s 
secrets or spoof Tenants data/memor y by hooking into 
system interfaces (DDR bus).  
A System Software adversary has the abi lity to read and 
write system memory, including private memory of TDs, 
access to TD CP U state and registers, ability to execute 
from TD memory, ability to program crit ical system 
hardware devices ( e.g., DMA engines), ability to program 
page tables/EPT to c ause faults or aliasing, and the ability 
to inject virtual interrupts/exceptions into TDs. Thus, some 
examples of the software attacks include direct 
content/memory in jection, capture and replay of 
content/memory, EPT remapping attacks.  A Hardware adversar y has physical access to the platform 
and the ability to read and write the physical m emory of 
the platform. It can thus launch attacks like DRAM freeze 
attacks, where  physical memory can be read and analyzed 
offline , as well as an ability to inject conten t/overwrite 
physical memory  and capture & replay physical memory at 
same or differen t location .  TDX does not prevent al l types 
of hardware attacks rather it  uses c ryptographic 
protections  on memory to improve defenses against a 
limited set of techni ques.  
TDX uses  Intel TME -MK to provide per-VM encryption or 
confidentiality protection. However , for technologies like 
TME and TME -MK, the H ypervisor  or VMM  is within the 
trust boundary or the TCB. TDX adds integrity protection, 
etc. with the goal of having  all system software, including 
the Hypervisor , out of the trust boundary of the platform 
user’s data or the workload.  Thus , TDX would prov ide 
better protection  or mitigation  against compromised  
Hypervisor /software  attacks. But the hypervisor still 
manages and controls the platform resource allocation like 
memory for a Guest VM, so p roviding protection against 
denial -of-service  attack from compromised  VMM is out of 
scope  for TDX . Below is a table summarizing some 
common software and hardware attacks and which of 
these technologies (TME, TME -MK or TDX) provide 
mitigation against  them . 
 
04. Sum mary 
Intel is i ntroducing new  archi tectural elements to h elp 
deploy hardware isolated  VMs called trust domains (TDs). 
TDX1.0 Introduces:  
 
• Secure-Arbitration Mode (S EAM) – a new m ode of the 
CPU design ed to ho st an I ntel-provided, digi tally-sign ed, 
security-services m odule called the Intel-TDX module. 
• Shared bit in GPA to help allow TD to access shared 
memory. 
• Secure EPT designed to translate private GPA to pro vide 
addres s-translation i ntegrity and to pr event TD-code 
fetches from shar ed m emory. Encryption and i ntegrity 
protection of private-memory access using a TD-private 
key is the goal. 
Software Attacks TME TME-MK TDX
Kernel Mapping Attacks N Y Y
Freed Data Leaks N Y Y
Compromised VMM takes over memory mgmt N N Y
Capture and Replay (diff domains) N Y Y
Capture and Replay (same domain) N N Y
Direct content injection (plain text) N Y Y
Direct content injection (chosen cipher text) N N Y
Data Exfitration (extract plaintext data)
- dictionary attackN Y Y
Row Hammer attack N N Y
EPT Remapping attack N N Y
Hardware Attacks
Cold boot attacks Y Y Y
Key Wearout attacks N Y Y
Data Exfitration (extract plaintext data) N Y Y
Capture and Replay content (between domains)
- cross domain injection attackN Y Y
Capture and Replay (same domain) N N N9 White Paper | Inte l® Trust Domai n Extensions   
 • Physi cal-addres s-metadata table ( PAMT) to h elp track 
page all ocation, page ini tialization, and TLB consi stency. 
• Multi-key, total-memory-encryption ( TME -MK) engine 
design ed to pro vide m emory encryption using  AES-128- 
XTS and i ntegrity modes (cryptographic -integrity using 
28-bit MAC that also includes the TD-ownership bi t, and 
logical -integrity using only the TD -ownership bit . 
• Remote attestation design ed to pro vide evidence of 
TDexecuting  on a genuine,  Intel-TDX system and its TCB 
version. 
In order to  accelerate deployment of TDX especially for 
cloud deployments, future TDX Modules will support n ew 
features like TD Partitioning, Live Migration, and TD and 
VM preserving Host/OS updates.  
 
Intel provide s these materials as-is, with no expres s or implied warranties. 
All produ cts, dates, and figures specified are preliminary, based on current expe ctations, and are subject to change without notice. 
The products described might contain desig n defe cts or erro rs known as errata, which might cause the produ ct to deviate from publishe d specifications. Current, characterized errata are 
availab le on reque st. 
Intel technologie s might require enab led hard ware, software, or service activation. Som e results have been estimated or simulated. Your costs and results might vary. No produ ct or 
compone nt can be absolutely secure. 
© Intel Corpo ration. Intel, the Intel logo, and other Intel marks are trademar ks of Intel Corpo ration or its subsidiarie s. Other name s and brands might be claime d as the prope rty of others. 
0720/RR/MESH/PDF    343961-003US 
 UEFI Platform Initialization
Specification
Version  1.8
Mar 03, 2023CONTENTS
I Pre-EFI Initialization Core Interface
I-1 Principle of Inclusive Terminology I-2
I-2 Organization of the PEI CIS I-3
I-3 Conventions Used in this Document I-4
I-3.1 Data Structure Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-4
I-3.2 Procedure Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-4
I-3.3 Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-5
I-3.4 PPI Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-5
I-3.5 Pseudo-Code Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-5
I-4 Requirements I-6
I-5 Conventions used in this document I-7
I-5.1 Number formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-7
I-5.2 Binary prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-7
I-6 Overview I-9
I-6.1 Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-9
I-6.2 Pre-EFI Initialization (PEI) Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-10
I-6.3 PEI Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-11
I-6.4 PEI Foundation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-11
I-6.5 PEI Dispatcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-12
I-6.6 Pre-EFI Initialization Modules (PEIMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-12
I-6.7 PEIM-to-PEIM Interfaces (PPIs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-12
I-6.8 FirmwareVolumes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-13
I-7 PEI ServicesTable I-14
I-7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-14
I-7.2 PEI Services Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-14
I-8 Services -PEI I-19
I-8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-19
I-8.2 PPI Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-20
I-8.3 Boot ModeServices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-23
I-8.4 HOB Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-25
I-8.5 FirmwareVolume Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-27
I-8.6 PEI Memory Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-35
I-8.7 StatusCode Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-40
I-8.8 ResetServices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-43
iI-8.9 I/O and PCI Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-44
I-9 PEI Foundation I-45
I-9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-45
I-9.2 PEI Foundation Entry Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-47

I-9.3 PEI Calling Convention Processor Binding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-49
I-9.4 PEI Services Table Retrieval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-49
I-9.5 PEI Dispatcher Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-53
I-9.6 Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-53
I-9.7 Dependency Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-55
I-9.8 Dispatch Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-61
I-10Architectural PPIs I-66
I-10.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-66
I-10.2Required Architectural PPIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-66
I-10.3Optional Architectural PPIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-69
I-11PEIMs I-80
I-11.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-80
I-11.2PEIM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-80
I-11.3PEIM Invocation Entry Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-82
I-11.4PEIM Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-83
I-11.5PEIM-to-PEIM Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-87
I-12Additional PPIs I-89
I-12.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-89
I-12.2Required Additional PPIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-89
I-12.3Optional Additional PPIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-99
I-12.4Graphics PEIM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-155
I-13PEI to DXE Handoff I-161
I-13.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-161
I-13.2Discovery and Dispatch of the DXE Foundation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-161
I-13.3Passing the Hand-Off Block (HOB) List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-161
I-13.4Handoff Processor State to the DXE IPL PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-162
I-14Boot Paths I-163
I-14.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-163
I-14.2Code Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-163
I-14.3Normal Boot Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-164
I-14.4Recovery Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-165
I-14.5Defined Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-166
I-14.6Priority of Boot Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-166
I-14.7Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-167
I-14.8Architectural Boot Mode PPIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-168
I-14.9Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-168
I-15PEI Physical Memory Usage I-173
I-15.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-173
I-15.2Before Permanent Memory Is Installed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-173
I-15.3After Permanent Memory Is Installed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-174
I-16Special Paths Unique to the Itanium ®Processor Family I-175
I-16.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-175
I-16.2Unique Boot Paths for Itanium Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-175
iiI-16.3Min-State Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-176
I-16.4Dispatching Itanium Processor Family PEIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-178
I-17Security (SEC) Phase Information I-180
I-17.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-180
I-17.2Responsibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-180
I-17.3SEC Platform Information PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-181
I-17.4SEC HOB Data PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-182
I-17.5Health Flag Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-182
I-17.6Processor-Specific Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-184
I-18Dependency Expression Grammar I-185
I-18.1Dependency Expression Grammar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-185
I-19TE Image I-187
I-19.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-187
I-19.2PE32 Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-187
I-20TE Image Creation I-190
I-20.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-190
I-20.2TE Image Utility Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-190
I-20.3TE Image Relocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-190
I-21TE Image Loading I-191
I-21.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-191
I-21.2XIP Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-191
I-21.3Relocated Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-192
I-21.4PIC Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-192
II Driver Execution Environment Core Interface
II-1Introduction II-1
II-1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1
II-1.2 Organization of the DXE CIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1
II-1.3 Target Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-2
II-1.4 Conventions Used in this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-3
II-1.5 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-6
II-1.6 Conventions used in this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-7
II-2Overview II-8
II-2.1 Driver Execution Environment (DXE) Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-8
II-2.2 UEFI System Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-9
II-2.3 DXE Foundation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-11
II-2.4 DXE Dispatcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-11
II-2.5 DXE Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-12
II-2.6 DXE Architectural Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-12
II-2.7 Runtime Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-13
II-3Boot Manager II-14
II-3.1 Boot Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-14
II-4UEFI System Table II-15
II-4.1 DXE Services Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-15
II-4.2 UEFI Image Entry Point Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-17
iiiII-5Services - Boot Services II-27
II-5.1 Extensions to UEFI Boot Service Event Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-27
II-6Runtime Capabilities II-31
II-6.1 Additional Runtime Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-31

II-7Services - DXE Services II-32
II-7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-32
II-7.2 Global Coherency Domain Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-32
II-7.3 Dispatcher Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-56
II-8Protocols - Device Path Protocol II-60
II-8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-60
II-8.2 Firmware Volume Media Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-60
II-8.3 Firmware File Media Device Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-61
II-9DXE Foundation II-62
II-9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-62
II-9.2 Hand-Off Block (HOB) List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-62
II-9.3 DXE Foundation Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-63
II-9.4 Required DXE Foundation Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-64
II-9.5 Handing Control to DXE Dispatcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-65
II-9.6 DXE Foundation Entry Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-66
II-9.7 Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-67
II-9.8 HOB Translations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-74
II-10 DXE Dispatcher II-77
II-10.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-77
II-10.2Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-77
II-10.3The A Priori File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-78
II-10.4Firmware Volume Image Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-79
II-10.5Dependency Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-79
II-10.6Dependency Expressions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-79
II-10.7Dependency Expression Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-80
II-10.8Dependency Expression with No Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-86
II-10.9Empty Dependency Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-86
II-10.10 Dependency Expression Reverse Polish Notation (RPN) . . . . . . . . . . . . . . . . . . . . . . . . II-88
II-10.11 DXE Dispatcher State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-88
II-10.12 Example Orderings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-90
II-10.13 Security Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-91
II-11 DXE Drivers II-93
II-11.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-93
II-11.2Classes of DXE Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-93
II-12 DXE Architectural Protocols II-95
II-12.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-95
II-12.2Boot Device Selection (BDS) Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . II-96
II-12.3CPU Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-97
II-12.4Metronome Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-107
II-12.5Monotonic Counter Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-108
II-12.6Real Time Clock Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-109
II-12.7Reset Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-109
II-12.8Runtime Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-110
II-12.9Security Architectural Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-113
ivII-12.10 Timer Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-117
II-12.11 Variable Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-121
II-12.12 Variable Write Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-122
II-12.13 EFI Capsule Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-122
II-12.14 Watchdog Timer Architectural Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-123
II-13 DXE Boot Services Protocol II-127
II-13.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-127
II-13.2Conventions and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-127
II-13.3MP Services Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-128
II-13.4MP Services Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-128
II-14 DXE Runtime Protocols II-141
II-14.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-141
II-14.2Status Code Runtime Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-141
II-15 Dependency Expression Grammar II-145
II-15.1Dependency Expression Grammar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-145
II-15.2Example Dependency Expression BNF Grammar . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-145
II-15.3Sample Dependency Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-146
II-16 Appendix: Error Codes II-148
II-17 Appendix: GUID Definitions II-149
II-17.1DXE Services Table GUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-149
II-17.2HOB List GUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-149
III Shared Architectural Elements
III-1 Introduction III-1
III-1.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-1
III-1.2Target Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-1
III-1.3Conventions Used in this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-2
III-1.4Conventions used in this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-4
III-2 Firmware Storage Design Discussion III-6
III-2.1Firmware Storage Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-6
III-2.2PI Architecture Firmware File System Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-16
III-3 Firmware Storage Code Definitions III-29
III-3.1Firmware Storage Code Definitions Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-29
III-3.2Firmware Storage Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-29
III-3.3PEI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-49
III-3.4DXE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-63
III-3.5SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-88
III-4 HOB Design Discussion III-90
III-4.1Explanation of HOB Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-90
III-4.2HOB Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-91
III-4.3Example HOB Producer Phase Memory Map and Usage . . . . . . . . . . . . . . . . . . . . . . . . III-91
III-4.4HOB List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-91
III-4.5Constructing the HOB List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-92
III-5 HOB Code Definitions III-94
III-5.1HOB Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-94

vIII-5.2HOB Generic Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-95
III-5.3PHIT HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-96
III-5.4Memory Allocation HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-97
III-5.5Resource Descriptor HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-101
III-5.6GUID Extension HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-106
III-5.7Firmware Volume HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-107
III-5.8CPU HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-110
III-5.9Memory Pool HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-110
III-5.10 UEFI Capsule HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-111
III-5.11 Unused HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-112
III-5.12 End of HOB List HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-112
III-5.13 SMRAM Memory Hob . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-112
III-6 Status Codes III-114
III-6.1Status Codes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-114
III-6.2Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-114
III-6.3Types of Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-115
III-6.4Hardware Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-117
III-6.5Software Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-145
III-6.6Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-164
III-6.7Class Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-171
III-7 Report Status Code Routers III-214
III-7.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-214
III-7.2Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-214
III-8 PCD III-222
III-8.1PCD Protocol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-222
III-8.2PCD PPI Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-237
IV Management Mode Core Interface
IV-1 Overview IV-1
IV-1.1Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-1
IV-1.2Management Mode (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-2
IV-1.3MM Driver Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-2
IV-1.4Initializing Management Mode in MM Traditional Mode . . . . . . . . . . . . . . . . . . . . . . . . IV-3
IV-1.5Initializing Management Mode in MM StandaloneMode . . . . . . . . . . . . . . . . . . . . . . . . IV-6
IV-1.6Entering & Exiting MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-8
IV-1.7MM Traditional Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-8
IV-1.8MM Traditional Driver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-10
IV-1.9MM Standalone Driver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-10
IV-1.10 MM Traditional Driver Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-10
IV-1.11 MM Standalone Driver Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-11
IV-1.12 Dispatching MMI Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-11
IV-1.13 MM Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-11
IV-1.14 MM UEFI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-12
IV-2 MM Foundation Entry Point IV-14
IV-2.1EFI_MM_ENTRY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-14
IV-2.2MM_FOUNDATION_ENTRY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-15
IV-3 Management Mode System Table (MMST) IV-16
IV-3.1MMST Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-16
viIV-3.2EFI_MM_SYSTEM_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-16
IV-4 MM Protocols IV-31
IV-4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-31
IV-4.2Status Codes Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-31
IV-4.3CPU Save State Access Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-33
IV-4.4MM Save State IO Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-41
IV-4.5MM CPU I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-42
IV-4.6MM PCI I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-45
IV-4.7MM Ready to Lock Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-46
IV-4.8MM MP protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-46
IV-4.9MM Configuration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-54
IV-4.10 MM End Of PEI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-55
IV-4.11 MM UEFI Ready Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-55
IV-4.12 MM Ready To Boot Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-56
IV-4.13 MM Exit Boot Services Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-56
IV-4.14 MM Security Architecture Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-57
IV-4.15 MM End of DXE Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-57
IV-4.16 MM Handler State Notification Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-58
IV-5 UEFI Protocols IV-61
IV-5.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-61
IV-5.2EFI MM Base Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-61
IV-5.3MM Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-63
IV-5.4MM Control Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-68
IV-5.5MM Configuration Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-70
IV-5.6DXE MM Ready to Lock Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-72
IV-5.7MM Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-72
IV-6 PI PEI PPIs IV-77
IV-6.1MM Access PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-77
IV-6.2MM Control PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-81
IV-6.3EFI DELAYED DISPATCH PPI (Required) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-83
IV-6.4MM Configuration PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-86
IV-6.5MM Communication PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-87
IV-7 MM Child Dispatch Protocols IV-89
IV-7.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-89
IV-7.2MM Software Dispatch Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-89
IV-7.3MM Sx Dispatch Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-92
IV-7.4MM Periodic Timer Dispatch Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-95
IV-7.5MM USB Dispatch Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-99

IV-7.6MM General Purpose Input (GPI) Dispatch Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . IV-102
IV-7.7MM Standby Button Dispatch Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-104
IV-7.8MM Power Button Dispatch Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-107
IV-7.9MM IO Trap Dispatch Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-109
IV-7.10 HOBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-112
IV-8 Interactions with PEI, DXE, and BDS IV-114
IV-8.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-114
IV-8.2MM and DXE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-114
IV-8.3MM and PEI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-115
IV-9 Other Related Notes For Support Of MM Drivers IV-116
IV-9.1File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-116
viiIV-9.2File Type EFI_FV_FILETYPE_MM_STANDALONE . . . . . . . . . . . . . . . . . . . . . . . . . IV-117
IV-9.3File Section Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-117
IV-10 MCA/INIT/PMI Protocol IV-118
IV-10.1 Machine Check and INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-118
IV-10.2 MCA Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-118
IV-10.3 INIT Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-121
IV-10.4 PMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-122
IV-10.5 Event Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-122
IV-10.6 MCA PMI INIT Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-124
IV-11 Extended SAL Services IV-128
IV-11.1 SAL Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-128
IV-11.2 Extended SAL Boot Service Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-129
IV-11.3 Extended SAL Service Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-136
IV-11.4 Extended SAL Stall Services Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-144
IV-12 SMM SPI Protocol Stack IV-223
IV-12.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-223
IV-12.2 SMM SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-223
IV-13 Management Mode Backward Compatibility Types IV-225
IV-13.1 EFI_SMM_BASE2_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-230
V Standards
V-1Introduction V-1
V-1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-1
V-1.2 Terms Used in this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-1
V-1.3 Conventions Used in this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-5
V-1.4 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-7
V-2SMBus Host Controller Design Discussion V-8
V-2.1 SMBus Host Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-8
V-2.2 Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-8
V-2.3 SMBus Host Controller Protocol Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-9
V-2.4 SMBus Host Controller Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-9
V-3SMBus Host Controller Code Definitions V-10
V-3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-10
V-3.2 SMBus Host Controller Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-10
V-4SMBus Design Discussion V-16
V-4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-16
V-4.2 Target Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-16
V-4.3 Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-16
V-4.4 PEI SMBus PPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-17
V-5SMBus PPI Code Definitions V-18
V-5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-18
V-5.2 PEI SMBus PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-18
V-6SMBIOS Protocol V-26
V-6.1 EFI_SMBIOS_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-26
V-6.2 EFI_SMBIOS_PROTOCOL.Add() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-27
viiiV-6.3 EFI_SMBIOS_PROTOCOL.UpdateString() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-29
V-6.4 EFI_SMBIOS_PROTOCOL.Remove() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-30
V-6.5 EFI_SMBIOS_PROTOCOL.GetNext() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-30
V-7IDE Controller V-32
V-7.1 IDE Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-32
V-7.2 Design Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-32
V-7.3 Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-38
V-8S3 Resume V-58
V-8.1 S3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-58
V-8.2 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-58
V-8.3 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-58
V-8.4 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-59
V-8.5 Restoring the Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-59
V-8.6 PEI Boot Script Executer PPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-63
V-8.7 S3 Save State Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-64
V-8.8 S3 SMM Save State Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-89
V-9ACPI System Description Table Protocol V-91
V-9.1 EFI_ACPI_SDT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-91
V-10 PCI Host Bridge V-102
V-10.1PCI Host Bridge Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-102
V-10.2PCI Host Bridge Design Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-102
V-10.3PCI Host Bridge Resource Allocation Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-103
V-10.4Sample PCI Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-106
V-10.5ISA Aliasing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-109
V-10.6Programming of Standard PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . V-112
V-10.7Sample Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-113
V-10.8PCI HostBridge Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-118
V-10.9End of PCI Enumeration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-136
V-11 PCI Platform V-138
V-11.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-138
V-11.2PCI Platform Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-138
V-11.3PCI Platform Support Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-139
V-11.4PCI Platform Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-139
V-11.5Incompatible PCI Device Support Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-140
V-11.6PCI Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-141
V-12 Hot Plug PCI V-151

V-12.1HOT PLUG PCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-151
V-12.2Hot Plug PCI Initialization Protocol Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-151
V-12.3Hot Plug PCI Initialization Protocol RelatedInformation . . . . . . . . . . . . . . . . . . . . . . . . V-151
V-12.4Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-152
V-12.5Sample Implementation for a Platform Containing PCIHot Plug* Slots . . . . . . . . . . . . . . . . V-153
V-12.6PCI Hot Plug PCI Initialization Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-154
V-12.7PCI Hot Plug Request Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-161
V-12.8Sample Implementation for a Platform Containing PCIHot Plug* Slots . . . . . . . . . . . . . . . . V-163
V-13 Super I/O Protocol V-165
V-13.1Super I/O Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-165
V-14 Super I/O and ISA Host Controller Interactions V-171
ixV-14.1Design Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-171
V-14.2Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-176
V-15 CPU I/O Protocol V-188
V-15.1CPU I/O Protocol Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-188
V-15.2CPU I/O Protocol2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-188
V-15.3Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-189
V-16 Legacy Region Protocol V-194
V-16.1Legacy Region Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-194
V-16.2Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-194
V-17 I2C Protocol Stack V-201
V-17.1Design Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-201
V-17.2DXE Code definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-210
V-17.3PEI Code definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-228
V-18 SPI Protocol Stack V-243
V-18.1Design Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-243
V-18.2DXE Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-250
V-19 Appendix: Error Codes V-280
V-19.1Error Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-280
Index V-281
xUEFI Platform Initialization Specification, Release 1.8
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CONTENTS -iUEFI Platform Initialization Specification, Release 1.8
Specification Organization
ThePlatform Initialization Specification is divided into volumes to enable logical organization, future growth, and
printing convenience. The currentvolumesare as follows:
•Volume I: Pre-EFI Initialization
•Volume II: Driver Execution Environment CoreInterface
•Volume III: Shared Architectural Elements
•Volume IV: Management Mode Core Interface
•Volume V: Standards
Eachvolumeshouldbeviewedinrelationtoallothervolumes,andreadersarestronglyencouragedtoconsulttheentire
specification when researching areas of interest. Recent versions of this specification are issued as a single document
containing all five volumes, foreasier searchingof thecomplete content.
Changes in this Release
See the following Revision Historysection fora list ofchanges inthis release.
CONTENTS -iiUEFI Platform Initialization Specification, Release 1.8
Many people have contributed to the contents of this specification, including the following:
•Platform Integration Working Group (PIWG)
•Tianocore Community Members
•Others as noted in the Revision History below
Table 1:Changes in this release
Rev. Issue-Description-Submitter Affected Content
1.8 2103 Adding EFI_DELAYED_DISPATCH_FUNCTION definition and
explanationSection IV-6.3
1.8 2119 HOB Update for Memory Ranges Capable of Being Protected by
CPU Cryptographic CapabilitiesSection III-5.5.1
1.8 2147 EFI_RESOURCE_ATTRIBUTE_SP not defined in Resource De-
scriptor HOBSection III-5.5.1
1.8 2160 MP Services 2 PPI Section I-12.3.9.12
1.8 2161 Introduce unaccepted memory type, Chris Oo and others Table 9.4, Section II-
7.2.4.1, Section III-5.3.1,
Section III-5.5.1
1.8 2340 Introduction of EFI_SW_EC_FRAGMENTED_MEMORY_MAP
Status CodeTable 6.45, Section III-
6.7.4.3
1.8 2341IntroductionofEFI_PERIPHERAL_TPMPeripheralSubclassDef-
initionTable 6.14, Table 6.68,
Section III-6.7.2
1.8 2351 update PI spec revision Section I-7.2.1
Revision Issue / Description / Submitter Affected Content
1.7B 2101 Fix DXE_SPECIFICATION_MINOR_REVISION and
PEI_SERVICES_REVISION definitionsSectionI-7.2.1,SectionII-
4.1, Section IV-3.2, Man-
agement Mode Backward
Compatibility Types
1.7B 2110 Status Code Class definition, incorrect comment on OEM
rangeSection III-6.7
1.7B 2213 Clarify PEI Memory Allocation Rules Section I-15.2.1, Section
I-15.3.1, Section I-15.3.2
1.7B 2364 Inclusive language implementation - added new disclaimer
sectionSection I-1
Revision Issue / Description / Submitter
1.7A 1663 SmmSxDispatch2 to Register() is not clear
1.7A 1736 Specification of EFI_BOOT_SCRIPT_WIDTH in Save State Write
1.7A 1993 Allow MM CommBuffer to be passed as a VA
1.7A 2017 EFI_RUNTIME_EVENT_ENTRY.Event should have type EFI_EVENT, not
(EFI_EVENT*)
1.7A 2039 PI Configuration Tables Errata
1.7A 2040 EFI_SECTION_FREEFORM_SUBTYPE_GUID Errata
1.7A 2060 Add missing EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS definition
1.7A 2063 Add Index to end of PI Spec
CONTENTS -iiiUEFI Platform Initialization Specification, Release 1.8
1.7A 2071 Extended cpu topology
1.7 1848 PEI Core PEIM Migration Support Change
1.7 1856 SecCore/PeiCore BFV Requirement Change
1.7 1860 MM MP Protocol issues
1.7 1885 Add extended data for EFI_SW_DXE_BS_EC_BOOT_OPTION_LOAD_ERROR
1.7 1889 New Status Codes
1.7 1891 PEI delayed dispatch
1.7 1892 new pi spec revision

1.7 1955set(*Attributes)whenEFI_PEI_GET_VARIABLE2returnsEFI_BUFFER_TOO_SMALL
and Attributes is non-NULL
1.7 1967 New architectural PPI for PI PEI Core FV Location
1.7 1969 Incompatible Pci Ignore Option Rom
1.6A 1828 Add decorator ‘OPTIONAL’ for Attributes parameter of EFI_PEI_GET_VARIABLE2.
1.6A 1849 Issues in PI Spec Vol. 5 Ch. 18
1.6A 1857 Specifies how notifications are passed from SEC to PEI.
1.6A 1884 Variadic API issue in S3 save API
1.6A 1907 Clarification of the EFI_MM_COMMUNICATION_PROTOCOL
1.6A 1940 Clarify EFI_MM_CONFIGURATION_PROTOCOL_GUID
1.6 1567 Layered SPI bus
1.6 1648 PI Binding for RISC-V
1.6 1746 Add an FV Extended Header entry that contains the used size of the FV
1.6 1763 MM Handler state notification protocol
1.6 1764 Add additional alignment
1.6 1768 Update the PI Spec to 1.6
1.6 1777 Update Revision History
1.6 1778 Update front matter
1.5A 1587 pre permanent memory page allocation
1.5A 1665 Incorrect status code for an AP calling EFI_MP_SERVICES_PROTOCOL.SwitchBSP()
1.5A 1734 Outdated EFI spec reference in Save State Write
1.5A 1735 Several copy & paste errors in Save State Write
1.5A 1747 Clarify that MM_ACCESS_PROTOCOL should cover all MMRAM region used by the
platform
1.5 1315 SMM Environment to Support Newer Architecture/Platform Designs
1.5 1317 additional I2C PPI’s (vol5)
1.5 1321 ARM Extensions to Volume 4
1.5 1330 Add PPI to allow SEC pass HOBs into PEI
1.5 1336 Provide For Pre-DXE Initialization Of The SM Foundation
1.5 1369 Handling PEI PPI descriptor notifications from SEC
1.5 1387 Variable services errors not consistent
1.5 1390 SM stand-alone infrastructure
1.5 1396 Update SEC HOB Capabilities of 1330 with additional guidance
1.5 1413 Communicate protocol enhancements
1.5 1506 New MP protocol
1.5 1513 Need a way to propagate PEI-phase FV verification status to DXE
1.5 1563 Update MM PPIs to match existing implementations
1.5 1566 PI.next - update the specification revisions
1.5 1568 Add SD/MMC GUID to DiskInfo protocol
1.5 1592 Add EFI_FV_FILETYPE_SMM_CORE_STANDALONE file type
1.5 1593 coalesce language enhancements
1.5 1594 Pei GetVaiable M1387 issue
CONTENTS -ivUEFI Platform Initialization Specification, Release 1.8
1.5 1595 M1568 Disk Info issue
1.5 1596 M1489 GCD issue
1.5 1603 Minor erratas in Vol4 PI 1.5 draft related to ECR 0001506
1.5 1607 Update MM guid def’n to match edkII impl
1.5 1626 Add new Status Code for BDS Attempting UEFI BootOrder entries
1.5 1628 Minor feedback for PI 1.5 Vol 4 SMM Draft
1.5 1666 Graphics Device Info Hob
1.4A 1574 Fix artificial limitation in the PCD.SetSku support
1.4A 1565 Update status code to include AArch64 exception error codes
1.4A 1564 SMM Software Dispatch Protocol Errata
1.4A 1562 Errata to remove statement from DXE vol about PEI dispatch behavior
1.4A 1561 Errata to provide Equivalent of DXE-CIS Mantis 247 for the PEI-CIS
1.4A 1532 Allow S3 Resume without having installed permanent memory (via InstallPeiMemory)
1.4A 1530 errata on dxe report status code
1.4A 1529 address space granularity errata
1.4A 1525 PEI Services Table Retrieval for AArch64
1.4A 1515 EFI_PEIM_NOTIFY_ENTRY_POINT return values are undefined
1.4A 1497 Fixing language in SMMStartupThisAP
1.4A 1489 GCD Conflict errata
1.4A 1485 Minor Errata in SMM Vo2 description of SMMStartupThisAP
1.4A 1397 PEI 1.4 specification revision errata
1.4A 1394 Errata to Relax requirements on CPU rendez in SEC
1.4A 1351 EndOfDxe and SmmReadyToLock
1.4A 1322 Minor Updates to handle Asynchronous CPU Entry Into SMM
1.4 1210 Adding persistence attribute to GCD
1.4 1235 PI.Next Feature - no execute support
1.4 1236 PI.Next feature - Graphics PPI
1.4 1237 PI.Next feature - add reset2 PPI
1.4 1239 PI.Next feature - Disk Info Guid UFS
1.4 1240 PI.Next feature - Recovery Block IO PPI - UFS
1.4 1259 PI.Next feature - MP PPI
1.4 1273 PI.Next feature - capsule PPI
1.4 1274 Recovery Block I/O PPI Update
1.4 1275 GetMemoryMap Update
1.4 1277 PI1.next feature - multiple CPU health info
1.4 1278 PI1.next - Memory relative reliability definition
1.4 1305 PI1.next - specification number encoding
1.4 1331 Remove left-over Boot Firmware Volume references in the SEC Platform Information PPI
1.4 1366 PI 1.4 draft - M1277 issue BIST / CPU. So health record needs to be indexed / CPU.
1.3A 1041 typo in HOB Overview
1.3A 1067 PI1.3 Errata for SetBootMode
1.3A 1068 Updates to PEI Service table/M1006
1.3A 1069 SIO Errata - pnp end node definition
1.3A 1070 Typo in SIO chapter
1.3A 1072 Errata – SMM register protocol notify clarification/errata
1.3A 1093 Extended File Size Errata
1.3A 1095 typos/errata
1.3A 1097 PI SMM GPI Errata
1.3A 1098 Errata on I2C IO status code
1.3A 1099 I2C Protocol stop behavior errata
CONTENTS -vUEFI Platform Initialization Specification, Release 1.8
1.3A 1104 ACPI System Description Table Protocol Errata
1.3A 1105 ACPI errata - supported table revision
1.3A 1177 PI errata - make CPU IO optional
1.3A 1178 errata - allow PEI to report an additional memory type
1.3A 1283 Errata - clarify sequencing of events
1.3 945 Integrated Circuit (I2C) Bus Protocol
1.3 998 PI Status Code additions
1.3 999 PCI enumeration complete GUID
1.3 1005 NVMe Disk Info guid
1.3 1006 Security Ppi Fixes
1.3 1025 PI table revisions
1.2.1A 922 Add a “Boot with Manufacturing” boot mode setting
1.2.1A 925 Errata on signed FV/Files
1.2.1A 931 DXE Volume 2 - Clarify memory map construction from the GCD
1.2.1A 936 Clarify memory usage in PEI on S3
1.2.1A 937SMM report protocol notify issue errata
1.2.1A 951 Root Handler Processing by SmiManage
1.2.1A 958 Omissions in PI1.2.1 integration for M816 and M894
1.2.1A 969 Vol 1 errata: TE Header parameters
1.2.1 527 PI Volume 2 DXE Security Architecture Protocol (SAP) clarification
1.2.1 562 Add SetMemoryCapabilities to GCD interface
1.2.1 719 End of DXE event
1.2.1 731 Volume 4 SMM - clarify the meaning of NumberOfCpus
1.2.1 737 Remove SMM Communication ACPI Table definition .
1.2.1 753 SIO PEI and UEFI-Driver Model Architecture
1.2.1 769 Signed PI sections
1.2.1 813 Add a new EFI_GET_PCD_INFO_PROTOCOL and EFI_GET_PCD_INFO_PPI instance.
1.2.1 818 New SAP2 return code
1.2.1 822 Method to disable Temporary RAM when Temp RAM Migration is not required
1.2.1 833 Method to Reserve Interrupt and Exception Vectors
1.2.1 839 Add support for weakly aligned FVs
1.2.1 892 EFI_PCI_ENUMERATION_COMPLETE_GUID Protocol
1.2.1 894 SAP2 Update
1.2.1 895 Status Code Data Structures Errata
1.2.1 902 Errata on signed firmware volume/file
1.2.1 903 SmiManage Update
1.2.1 906 Volume 3 errata - Freeform type
1.2.1 916 Service table revisions
1.2C 550 Naming conflicts w/ PI SMM
1.2C 571duplicatedefinitionofEFI_AP_PROCEDUREinDXEMP(volume2)andSMM(volume4)
1.2C 654 UEFI PI specific handle for SMBIOS is now available
1.2C 688 Status Code errata
1.2C 690 Clarify agent in IDE Controller chapter
1.2C 691 SMM a priori file and SOR support
1.2C 692 Clarify the SMM SW Register API
1.2C 694 PEI Temp RAM PPI ambiguity
1.2C 703 End of PEI phase PPI publication for the S3 boot mode case
1.2C 706 GetPeiServicesTablePointer () changes for the ARM architecture
1.2C 714 PI Service Table Versions
1.2C 717 PI Extended File Size Errata
CONTENTS -viUEFI Platform Initialization Specification, Release 1.8
1.2C 718 PI Extended Header cleanup / Errata
1.2C 730 typo in EFI_SMM_CPU_PROTOCOL.ReadSaveState() return code
1.2C 737 Remove SMM Communication ACPI Table definition .
1.2C 738 Errata to Volume 2 of the PI1.2 specification
1.2C 739 Errata for PI SMM Volume 4 Control protocol
1.2C 742 Errata for SMBUS chapter in Volume 5
1.2C 743 Errata - PCD_PPI declaration
1.2C 745 Errata – PI Firmware Section declarations
1.2C 746 Errata - PI status code
1.2C 747 Errata - Text for deprecated HOB
1.2C 752 Binary Prefix change
1.2C 753 SIO PEI and UEFI-Driver Model Architecture
1.2C 764 PI Volume 4 SMM naming errata
1.2C 775 errata/typo in EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT, Volume 3
1.2C 781 S3 Save State Protocol Errata
1.2C 782 Format Insert(), Compare() and Label() as for Write()
1.2C 783 TemporaryRamMigration Errata
1.2C 784 Typos in status code definitions
1.2C 787 S3 Save State Protocol Errata 2
1.2C 810 Set Memory Attributes return code clarification
1.2C 811 SMBIOS API Clarification
1.2C 814 PI SMBIOS Errata
1.2C 821Location conflict for EFI_RESOURCE_ATTRIBUTE_xxx_PROTECTABLE #defines
1.2C 823 Clarify max length of SMBIOS Strings in SMBIOS Protocol
1.2C 824 EFI_SMM_SW_DISPATCH2_PROTOCOL.Register() Errata
1.2C 837 ARM Vector table can not support arbitrary 32-bit address
1.2C 838 Vol 3 EFI_FVB2_ALIGNMNET_512K should be EFI_FVB2_ALIGNMENT_512K
1.2C 840 Vol 3 Table 5 Supported FFS Alignments contains values not supported by FFS
1.2C 844 correct references to Platform Initialization Hand-Off Block Specification
1.2B 628 ACPI SDT protocol errata
1.2B 629 Typos in PCD GetSize()

1.2B 630EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL service clarification
1.2A 363 PI volume 1 errata
1.2A 365 UEFI Capsule HOB
1.2A 381 PI1.1 Errata on EFI_SMM_SAVE_STATE_IO_INFO
1.2A 482 One other naming inconsistency in the PCD PPI declaration
1.2A 483 PCD Protocol / PPI function name synchronization.....
1.2A 496 Boot mode description
1.2A 497 Status Code additions
1.2A 548 Boot firmware volume clarification
1.2A 551 Name conflicts w/ Legacy region
1.2A 552 MP services
1.2A 553 Update text to PEI
1.2A 554 update return code from PEI AllocatePages
1.2A 555 Inconsistency in the S3 protocol
1.2A 561 Minor update to PCD->SetPointer
1.2A 565 CANCEL_CALL_BACK should be CANCEL_CALLBACK
1.2A 569 Recovery: EFI_PEI_GET_NUMBER_BLOCK_DEVICES decl has EFI_STATUS w/o re-
turn code & errror on stage 3 recovery description
1.2A 571duplicatedefinitionofEFI_AP_PROCEDUREinDXEMP(volume2)andSMM(volume4)
CONTENTS -viiUEFI Platform Initialization Specification, Release 1.8
1.2A 581 EFI_HOB_TYPE_LOAD_PEIM ambiguity
1.2A 591 ACPI Protocol Name collision
1.2A 592 More SMM name conflicts
1.2A 593 A couple of ISA I/O clarifications
1.2A 594 ATA/ATAPI clarification
1.2A 595 SMM driver entry point clarification
1.2A 596 Clarify ESAL return codes
1.2A 602 SEC->PEI hand-off update
1.2A 604 EFI_NOT_SUPPORTED versus EFI_UNSUPPORTED
1.2A 345 PI1.0 errata
1.2A 468 Issues on proposed PI1.2 ACPI System Description Table Protocol
1.2A 492 Add Resource HOB Protectability Attributes
1.2A 494 Vol. 2 Appendix A Clean up
1.2A 495 Vol 1: update HOB reference
1.2A 380 PI1.1 errata from SMM development
1.2A 501 Clean Up SetMemoryAttributes() language Per Mantis 489 (from USWG)
1.2A 502 Disk info
1.2A 503 typo
1.2A 504 remove support for fixed address resources
1.2A 509 PCI errata – execution phase
1.2A 510 PCI errata - platform policy
1.2A 511 PIC TE Image clarification/errata
1.2A 520 PI Errata
1.2A 521Add help text for EFI_PCD_PROTOCOL for GetNextTokenSpace
1.2A 525 Itanium ESAL, MCA/INIT/PMI errata
1.2A 526 PI SMM errata
1.2A 529 PCD issues in Volume 3 of the PI1.2 Specification
1.2A 541 Volume 5 Typo
1.2A 543 Clarification around usage of FV Extended header
1.2A 550 Naming conflicts w/ PI SMM
1.2 407 Comment: additional change to LMA Pseudo-Register
1.2 441 Comment: PI Volume 3, Incorrect Struct Declaration (esp PCD_PPI)
1.2 455 Comment: Errata - Clarification of InstallPeiMemory()
1.2 465 Comment: Errata on PMI interface
1.2 466 Comment: Vol 4 EXTENDED_SAL_PROC definition
1.2 467 Comments: PI1.1 errata
1.2 480 Comment: FIX to PCD_PROTOCOL and PCD_PPI
1.2 401 SMM Volume 4 issue
1.2 402 SMM PI spec issue w.r.t. CRC
1.2 407 Add LMA Pseudo-Register to SMM Save State Protocol
1.2 409 PCD_PROTOCOL Errata
1.2 411 Draft Errata, Volume 5, Section 8
1.2 412 Comment: PEI_S3_RESUME_PPI should be EFI_PEI_S3_RESUME_PPI
1.2 414 Draft Chapter 7 Comments
1.2 415 Comment: Report Status Code Routers
1.2 416 EFI_CPU_IO_PROTOCOL2 Name should be EFI_CPU_IO2_PROTOCOL
1.2 417 Volume 5, Chapter 4 & 5 order is reversed
1.2 423 Comment: Section 15.2.1 Formatting Issues vol5
1.2 424 Comments: Volume 5, Appendix A.1 formatting issues
1.2 425 Comment: Formatting in Section 6.1 of Volume 3
CONTENTS -viiiUEFI Platform Initialization Specification, Release 1.8
1.2 426 Comments: Volume 2
1.2 427 Comment: Volume 3, Section 6
1.2 433 Editorial issues in PI 1.2 draft
1.2 271 Support For Large Firmware Files And Firmware File Sections
1.2 284 CPU I/O protocol update
1.2 286 Legacy Region protocol
1.2 289 Recovery API
1.2 292 PCD Specification Update
1.2 354 ACPI Manipulation Protocol
1.2 355 EFI_SIO_PROTOCOL Errata
1.2 365 UEFI Capsule HOB
1.2 382 IDE Controller Specification
1.2 385 Report Status Code Router Specification
1.2 386 Status Code Specification
1.1D 247 Clarification regarding use of dependency expression section types with firmware volume
image files
1.1D 399 SMBIOS Protocol Errata
1.1D 405 PIWG Volume 5 incorrectly refers to EFI_PCI_OVERRIDE_PROTOCOL
1.1D 422 TEMPORARY_RAM_SUPPORT_PPI is misnamed
1.1D 428 Volume 5 PCI issue
1.1D 430 Clarify behavior w/ the FV extended header
1.1C 204 Stack HOB update 1.1errata
1.1C 225 Correct references from EFI_FIRMWARE_VOLUME_PROTOCOL to
EFI_FIRMWARE_VOLUME2_PROTOCOL
1.1C 226 Remove references to Framework
1.1C 227 Correct protocol name GUIDED_SECTION_EXTRACTION_PROTOCOL
1.1C 228 insert”typedef” missing from some typedefs in Volume 3
1.1C 243 Define interface “EFI_PEI_FV_PPI” declaration in PI1.0 FfsFindNextVolume()
1.1C 285 Time quality of service in S3 boot script poll operation
1.1C 287 Correct MP spec, PIVOLUME 2:Chapter 13.3 and 13.4 - return error language
1.1C 290 PI Errata
1.1C 305 Remove Datahub reference
1.1C 336 SMM Control Protocol update
1.1C 345 PI Errata
1.1C 353 PI Errata
1.1C 360 S3RestoreConfig description is missing
1.1C 363 PI Volume 1 Errata
1.1C 367 PCI Hot Plug Init errata
1.1C 369 Volume 4 Errata
1.1C 380 SMM Development errata
1.1C 381 Errata on EFI_SMM_SAVE_STATE_IO_INFO
1.1B Revises typographical errors and minor omissions–see Errata for details
1.1A Restore (missing) MP protocol
1.1 M39 (Updates PCI Hostbridge & PCI Platform)
1.1 M41 (Duplicate 167)
1.1 M42 Add the definition of theDXE CIS Capsule AP & Variable AP
1.1 M43 (SMbios)
1.1 M46 (SMM error codes)
1.1 M163 (Add Volume 4–SMM
1.1 M167 (Vol2: adds the DXE Boot Services Protocols–new Chapter 12)
CONTENTS -ixUEFI Platform Initialization Specification, Release 1.8
1.1 M179 (S3 boot script)
1.1 M180 (PMI ECR)
1.1 M195 (Remove PMI references from SMM CIS)
1.1 M196 (disposable-section type to the FFS)
1.0A M47 dxe_dispatcher_load_image_behavior
1.0A M48 Make spec more consistent GUID & filename.
1.0A M155 FV_FILE and FV_ONLY: Change subtype number back to th:e original one.
1.0A M171Remove 10 us lower bound restriction for the TickPeriod in the Metronome
1.0A M178 Remove references to tail in file header and made file checksum for the data
1.0A M183 Vol 1-Vol 5: Make spec more consistent.
1.0A M192 Change PAD files to have an undefined GUID file name and update all FV
1.0 Initial public release.
CONTENTS -xPart I
Pre-EFI Initialization Core InterfaceUEFI Platform Initialization Specification, Release 1.8
List of Figures - Volume I
•Typical PEIM Layout in a Firmware File
•Mode Information Supported By Graphics PEI Module
•Itanium Processor Boot Path (INIT and MCHK)
•Min-State Buffer Organization
•Boot Path in Itanium Processors
•Health Flag Bit Format
•PEI Initialization Steps in IA-32
•Security (SEC) Phase in the Itanium ProcessorFamily
I-iUEFI Platform Initialization Specification, Release 1.8
•Organization of the PEI CIS
•PEI Foundation Classes of Service
•PEI Services
•Boot Mode Register
•PUSH Instruction Encoding
•PEI PPI Services List Descriptors
•Organization of the Code Definitions Section
•Required HOB Types in the HOB List
•Handoff Processor State to the DXE IPL PPI
•Boot Path Assumptions
•Architectural Boot Mode PPIs
•Device Recovery Module Functions
•Device Recovery Block I/O Functions
•Health Flag Bit Field Description
•Self-Test State Bit Values
•COFF Header Fields Required for TE Images
•Optional Header Fields Required for TE Images
I-iiUEFI Platform Initialization Specification, Release 1.8
ThisspecificationdefinesthecorecodeandservicesthatarerequiredforanimplementationofthePre-EFIInitialization
(PEI) phase of the Platform Initialization (PI) specifications (hereafter referred to as the “PI Architecture”). This PEI
core interface specification (CIS) does the following:
•Describes the basic components of the PEI phase
•Provides code definitions for services and functions that are architecturally required by the UEFI PI working
group (PIWG)
•Describes the machine preparation that is required for subsequent phases of firmware execution
•Discusses state variables that describe the system restart type
See Section I-2 for more information.
I-1CHAPTER
ONE
PRINCIPLE OF INCLUSIVE TERMINOLOGY
The UEFI Forum follows a Principle of Inclusive Terminology in building and maintaining content for specifications.
earlierwork,forexamplereferencestolegacyspecificationsnotcontrolledbytheForum,maynotfollowthisprinciple.
In order to preserve compatibility for code that reads on legacy specifications, particularly where that specification is
nolongerundermaintenanceordevelopment,languageinthisspecificationmayappearoutofsyncwiththePrinciple.
The Forum is resolved to work with other standards development bodies to eliminate such examples over time. In the
meanwhile, by acknowledging and calling attention to this issue the hope is to promote discussion and action towards

ONE
morecompleteuseofInclusiveLanguagereflectiveofthediverseandinnovativepopulationofthetechnicalcommunity
that works on standards.
I-2CHAPTER
TWO
ORGANIZATION OF THE PEI CIS
ThisPEIcoreinterfacespecificationisorganizedasshownin“OrganizationofthePEICIS.”BecausethePEIFounda-
tionisjustonecomponentofaPIArchitecture-basedfirmwaresolution,thereareanumberofadditionalspecifications
that are referred to throughout this document.
Table 2.1: Organization of the PEI CIS
Section Description
Overview Describes the major components of PEI including the PEI Services boot mode PEI
Dispatcher and PEIMs
PEI Services Table Describes the data structure that maintains the PEI Services
Services PEI Services Details each of the functions that comprise the PEI Services
PEI Foundation Describes the PEI Foundation and its methods of operation and the PEI Dispatcher
and its associated dependency expression grammar
PEIMs Describes the format and use of the Pre EFI Initialization Module PEIM
Architectural PPIs Contains PEIM to PEIM Interfaces PPIs that are used by the PEI Foundation
Additional PPIs Contains PPIs that can exist on a platform
SPEI to DXE Handoff DescribesthestateofthemachineandmemorywhenthePEIphaseinvokestheDXE
phase
Boot Paths Boot Describes the restart modalities and behavior supported in the PEI phase
PEI Physical Memory Us-
ageDescribes the memory map and memory usage during the PEI phase
SpecialPathsUniquetothe
Itanium Processor FamilyContains flow during PEI that is unique to the Itanium processor family
Security SEC Phase Infor-
mationContains an overview of the phase of execution that occurs prior to PEI
Dependency Expression
GrammarDescribestheBNFgrammarforatoolthatcanconvertatextfilecontainingadepen-
dency expression into a dependency section of a PEIM stored in a firmware volume
TE Image Describes the format of the TE executable
TE Image Creation Describes how TE executables are created from PE32 executables
TE Image Loading Describes how TE executables are loaded into memory
I-3CHAPTER
THREE
CONVENTIONS USED IN THIS DOCUMENT
This document uses the typographic and illustrative conventions described below.
I-3.1 Data Structure Descriptions
iteminmemoryisatthelowestaddress,whilethehigh-orderbyteisatthehighestaddress. Somesupportedprocessors
may be configured for both “little endian” and “big endian” operation. All implementations designed to conform to
this specification will use “little endian” operation.
In some memory layout descriptions, certain fields are marked reserved. Software must initialize such fields to zero
and ignore them when read. On an update operation, software must preserve any reserved field.
The data structures described in this document generally have the following format:
Structure Name: The formal name of the data structure.
Summary: A brief description of the data structure.
Prototype: A “C-style” type declaration for the data structure.
Parameters: A brief description of each field in the data structure prototype.
Description: A description of the functionality provided by the data structure, including any limitations and caveats
of which the caller should be aware.
Related Definitions: The type declarations and constants that are used only by this data structure.
I-3.2 Procedure Descriptions
The procedures described in this document generally have the following format:
Prototype: A “C-style” procedure header defining the calling sequence.
Parameters: A brief description of each field in the procedure prototype.
Related Definitions: The type declarations and constants that are used only by this procedure.
I-4UEFI Platform Initialization Specification, Release 1.8
StatusCodesReturned: Adescriptionofanycodesreturnedbytheinterface. Theprocedureisrequiredtoimplement
I-3.3 Instruction Descriptions
A dependency expression instruction description generally has the following format:
InstructionName The formal name of the instruction.
Syntax:A brief description of the instruction.
BehaviorsandRestrictions: Anitem-by-itemdescriptionofthebehaviorofeachoperandinvolvedintheinstruction
I-3.4 PPI Descriptions
A PEIM-to-PEIM Interface (PPI) description generally has the following format:
PPI Name: The formal name of the PPI.
Summary: A brief description of the PPI.
GUID:The 128-bit Globally Unique Identifier (GUID) for the PPI.
Protocol Interface Structure: A “C-style” procedure template defining the PPI calling structure.
Parameters: A brief description of each field in the PPI structure.
Related Definitions: The type declarations and constants that are used only by this interface.
Status Codes Returned: A description of any codes returned by the interface. The PPI is required to implement
I-3.5 Pseudo-Code Conventions
In describing variables, a list is an unordered collection of homogeneous objects. A queue is an ordered list of homo-
geneous objects. Unless otherwise noted, the ordering is assumed to be First In First Out (FIFO).
the indentation style, is used for readability and does not necessarily comply with an implementation of the Unified
Extensible Firmware Interface Specification (UEFI 2.0 specification).
I-3.3. Instruction Descriptions I-5CHAPTER
FOUR
REQUIREMENTS
ThisdocumentisanarchitecturalspecificationthatispartofthePlatformInitializationArchitecture(PIArchitecture)
family of specifications defined and published by the Unified EFI Forum. The primary intent of the PI Architecture is
to present an interoperability surface for firmware components that may originate from different providers. As such,
the burden to conform to this specification falls both on the producer and the consumer of facilities described as part
of the specification.
In general, it is incumbent on the producer implementation to ensure that any facility that a conforming consumer
firmware component might attempt to use is present in the implementation. Equally, it is incumbent on a developer
of a firmware component to ensure that its implementation relies only on facilities that are defined as part of the PI
Architecture. Maximum interoperability is assured when collections of conforming components are designed to use
only the required facilities defined in the PI Architecture family of specifications.
Asthisdocumentisanarchitecturalspecification,carehasbeentakentospecifyarchitectureinwaysthatallowmaxi-
mumflexibilityinimplementationforbothproducerandconsumer. However,therearecertainrequirementsonwhich
elementsofthisspecificationmustbeimplementedtoensureaconsistentandpredictableenvironmentfortheoperation
of code designed to work with the architectural interfaces described here.
For the purposes of describing these requirements, the specification includes facilities that are required, such as inter-
faces and data structures, as well as facilities that are marked as optional.
Ingeneral,foranimplementationtobeconformantwiththisspecification,theimplementationmustincludefunctional
elementsthatmatchinallrespectsthecompletedescriptionoftherequiredfacilitydescriptionspresentedaspartofthe
specification. Any part of the specification that is not explicitly marked as “optional” is considered a required facility.
Wherepartsofthespecificationaremarkedas“optional,”animplementationmaychoosetoprovidematchingelements
or leave them out. If an element is provided by an implementation for a facility, then it must match in all respects the

corresponding complete description.
In practical terms, this means that for any facility covered in the specification, any instance of an implementation
may only claim to conform if it follows the normative descriptions completely and exactly. This does not preclude an
implementationthatprovidesadditionalfunctionality,overandabovethatdescribedinthespecification. Furthermore,
it does not preclude an implementation from leaving out facilities that are marked as optional in the specification.
By corollary, modular components of firmware designed to function within an implementation that conforms to the
PI Architecture are conformant only if they depend only on facilities described in this and related PI Architecture
specifications. In other words, any modular component that is free of any external dependency that falls outside of
the scope of the PI Architecture specifications is conformant. A modular component is not conformant if it relies for
correct and complete operation upon a reference to an interface or data structure that is neither part of its own image
nor described in any PI Architecture specifications.
Itispossibletomakeapartialimplementationofthespecificationwheresomeoftherequiredfacilitiesarenotpresent.
Suchanimplementationisnon-conforming,andotherfirmwarecomponentsthatarethemselvesconformingmightnot
function correctly with it. Correct operation of non-conforming implementations is explicitly out of scope for the PI
Architecture and this specification.
I-6CHAPTER
FIVE
I-5.1 Number formats
A binary number is represented in this standard by any sequence of digits consisting of only the Western-Arabic nu-
merals0and1immediatelyfollowedbyalower-caseb(e.g.,0101b). Underscoresorspacesmaybeincludedbetween
charactersinbinarynumberrepresentationstoincreasereadabilityordelineatefieldboundaries(e.g.,001011010bor
0_0101_1010b).
Western-Arabicnumerals0through9and/ortheupper-caseEnglishlettersAthroughF(e.g.,0xFA23). Underscoresor
spacesmaybeincludedbetweencharactersinhexadecimalnumberrepresentationstoincreasereadabilityordelineate
field boundaries (e.g., 0xB FD8C FA23 or 0xB_FD8C_FA23).
•the decimal separator (i.e., separating the integer and fractional portions of the number) is a period;
•the thousands separator (i.e., separating groups of three digits in a portion of the number) is a comma;
•the thousands separator is used in the integer portion and is not used in the fraction portion of a number.
I-5.2 Binary prefixes
This standard uses the prefixes defined in the International System of Units (SI) (see http://www.bipm.org/en/si/si_
brochure/chapter3/prefixes.html ) for values that are powers of ten.
Table 5.1: SI prefixes
Factor Factor NameSymbol
103 1,000 kiloK
106 1,000,000 megaM
109 1,000,000,000 gigaG
ThisstandardusesthebinaryprefixesdefinedinISO/IEC80000-13 Quantitiesandunits–Part13: Informationscience
and technology and IEEE 1514 Standard for Prefixes for Binary Multiples for values that are powers of two.
I-7UEFI Platform Initialization Specification, Release 1.8
Table 5.2: Binary prefixes
210 1,024 kibiKi
220 1,048,576 mebiMi
230 1,073,741,824 gibiGi
I-5.2. Binary prefixes I-8CHAPTER
SIX
OVERVIEW
The Pre-EFI Initialization (PEI) phase of the PI Architecture specifications (hereafter referred to as the “PI Architec-
ture”) is invoked quite early in the boot flow. Specifically, after some preliminary processing in the Security (SEC)
phase, any machine restart event will invoke the PEI phase.
ThePEIphasewillinitiallyoperatewiththeplatforminanascentstate,leveragingonlyon-processorresources,suchas
the processor cache as a call stack, to dispatch Pre-EFI Initialization Modules (PEIMs). These PEIMs are responsible
for the following:
•Initializing some permanent memory complement
•Describing the memory in Hand-Off Blocks (HOBs)
•Describing the firmware volume locations in HOBs
•Passing control into the Driver Execution Environment (DXE) phase
Philosophically,thePEIphaseisintendedtobethethinnestamountofcodetoachievetheendslistedabove. Assuch,
any more sophisticated algorithms or processing should be deferred to the DXE phase of execution.
ThePEIphaseisalsoresponsibleforcrisisrecoveryandresumingfromtheS3sleepstate. Forcrisisrecovery,thePEI
phase should reside in some small, fault-tolerant block of the firmware store. As a result, it is imperative to keep the
footprint of the PEI phase as small as possible. In addition, for a successful S3 resume, the speed of the resume is of
utmost importance, so the code path through the firmware should be minimized. These two boot flows also speak to
the need to keep the processing and code paths in the PEI phase to a minimum.
The implementation of the PEI phase is more dependent on the processor architecture than any other phase. In par-
ticular, the more resources the processor provides at its initial or near initial state, the richer the interface between the
PEI Foundation and PEIMs. As such, there are several parts of the following discussion that note requirements on the
architecture but are otherwise left architecturally dependent.
I-6.1 Design Goals
The PI Architecture requires the PEI phase to configure a system to meet the minimum prerequisites for the Driver
Execution Environment (DXE) phase of the PI Architecture architecture. In general, the PEI phase is required to
initialize a linear array of RAM large enough for the successful execution of the DXE phase elements.
The PEI phase provides a framework to allow vendors to supply separate initialization modules for each functionally
distinct piece of system hardware that must be initialized prior to the DXE phase of execution in the PI Architecture.
ThePEIphaseprovidesacommonframeworkthroughwhichtheseparateinitializationmodulescanbeindependently
designed, developed, and updated. The PEI phase was developed to meet the following goals in the PI architecture:
•Enable maintenance of the “chain of trust.” This includes protection against unauthorized updates to the PEI
phase or its modules, as well as a form of authentication of the PEI
•Foundation and its modules during the PEI phase.
I-9UEFI Platform Initialization Specification, Release 1.8
•ProvideacorePEImodule(thePEIFoundation)thatwillremainmoreorlessconstantforaparticularprocessor
architecturebutthatwillsupportadd-inmodulesfromvariousvendors,particularforprocessors,chipsets,RAM
initialization, and so on.
•Allow independent development of early initialization modules.
I-6.2 Pre-EFI Initialization (PEI) Phase
ThedesignforthePre-EFIInitialization(PEI)phaseofaPIArchitecture-compliantbootisasanessentiallyminiature
versionoftheDXEphaseofthePIArchitectureandaddressesmanyofthesameissues. ThePEIphaseisdesignedto
be developed in several parts. The PEI phase consists of the following:
•Some core code known as the PEI Foundation
•Specialized plug-ins known as Pre-EFI Initialization Modules (PEIMs)
Unlike DXE, the PEI phase cannot assume the availability of reasonable amounts of RAM, so the richness of the
features in DXE does not exist in PEI. The PEI phase limits its support to the following actions:
•Locating, validating, and dispatching PEIMs
•Facilitating communication between PEIMs
•Providing handoff data to subsequent phases
See PEI Operations Diagram. below shows a diagram of the process completed during the PEI phase.
Fig. 6.1: PEI Operations Diagram
I-6.2. Pre-EFI Initialization (PEI) Phase I-10UEFI Platform Initialization Specification, Release 1.8
I-6.3 PEI Services
ThePEIFoundationestablishesasystemtablenamedthePEIServicesTablethatisvisibletoallPre-EFIInitialization
Modules (PEIMs) in the system. A PEI Service is defined as a function, command, or other capability manifested by
the PEI Foundation when that service’s initialization requirements are met. Because the PEI phase has no permanent
memory available until nearly the end of the phase, the range of services created during the PEI phase cannot be as
rich as those created during later phases. Because the location of the PEI Foundation and its temporary RAM is not
knownatbuildtime,apointertothePEIServicesTableispassedintoeachPEIM’sentrypointandalsotopartofeach
PEIM-to-PEIM Interface (PPI).
The PEI Foundation provides the classes of services listed in See PEI Foundation Classes of Service. .
Table 6.1: PEI Foundation Classes of Service
PPI Services Manages PPIs to facilitate intermodule calls between PEIMs Interfaces are installed
and tracked on a database maintained in temporary RAM
Boot Mode Ser-
vicesManages the boot mode S3 S5 normal boot diagnostics etc of the system

HOB Services Creates data structures called Hand Off Blocks HOBs that are used to pass information to the
next phase of the PI Architecture
Firmware Vol-
ume ServicesFinds PEIMs and other firmware files in the firmware volumes
PEI Memory
ServicesProvidesacollectionofmemorymanagementservicesforusebothbeforeandafterpermanent
memory has been discovered
StatusCodeSer-
vicesProvides common progress and error code reporting services for example port 080h or a serial
port for simple text output for debug
Reset Services Provides a common means by which to initiate a warm or cold restart of the system
I-6.4 PEI Foundation
The PEI Foundation is the entity that is responsible for the following:
•Successfully dispatching Pre-EFI Initialization Modules (PEIMs)
•Maintaining the boot mode
•Initializing permanent memory
•Invoking the Driver Execution Environment (DXE) loader
The PEI Foundation is written to be portable across all platforms of a given instruction-set architecture. As such,
a binary for 32-bit Intel ®architecture (IA-32) should work across all Pentium ®processors, from the Pentium II
processor with MMX ™technology through the latest Pentium 4 processors. Similarly, the PEI Foundation binary for
the Itanium ®processor family should work across all Itanium processors.
Regardless of the processor microarchitecture, the set of services exposed by the PEI Foundation should be the same.
ThisuniformsurfaceareaaroundthePEIFoundationallowsPEIMstobewrittenintheCprogramminglanguageand
compiled across any microarchitecture.
I-6.3. PEI Services I-11UEFI Platform Initialization Specification, Release 1.8
I-6.5 PEI Dispatcher
The PEI Dispatcher is essentially a state machine that is implemented in the PEI Foundation. The PEI Dispatcher
evaluates the dependency expressions in Pre-EFI Initialization Modules (PEIMs) that are in the firmware volume(s)
being examined.
ThedependencyexpressionsarelogicalcombinationsofPEIM-to-PEIMInterfaces(PPIs). Theseexpressionsdescribe
the PPIs that must be available before a given PEIM can be invoked. To evaluate the dependency expression for the
PEIM, the PEI Dispatcher references the PPI database in the PEI Foundation to determine which PPIs have been
installed. IfthePPIhasbeeninstalled,thedependencyexpressionwillevaluateto TRUE,whichtellsthePEIDispatcher
itcan runthePEIM. Atthispoint, thePEIFoundation passescontrolto thePEIMwith atruedependency expression.
Once the PEI Dispatcher has evaluated all of the PEIMs in all of the exposed firmware volumes and no more PEIMs
canbedispatched(i.e.,thedependencyexpressionsdonotevaluatefrom FALSEtoTRUE),thePEIDispatcherwillexit.
It is at this point that the PEI Dispatcher cannot invoke any additional PEIMs. The PEI Foundation then reassumes
control from the PEI Dispatcher and invokes the DXE IPL PPI to pass control to the DXE phase of execution.
I-6.6 Pre-EFI Initialization Modules (PEIMs)
Pre-EFI Initialization Modules (PEIMs) are specialized drivers that personalize the PEI Foundation to the platform.
TheyareanalogoustoDXEdriversandgenerallycorrespondtothecomponentsbeinginitialized. Itistheresponsibility
of the PEI Foundation code to dispatch the PEIMs in a sequenced order and provide basic services. The PEIMs are
intended to mirror the components being initialized.
Communication between PEIMs is not easy in a “memory poor” environment. Nonetheless, PEIMs cannot be coded
without some interaction between one another and, even if they could, it would be inefficient to do so. The PEI phase
provides mechanisms for PEIMs to locate and invoke interfaces from other PEIMs.
Because the PEI phase exists in an environment where minimal hardware resources are available and execution is
performedfromtheboot firmwaredevice,itisstronglyrecommended thatPEIMsdotheminimumnecessarywork to
initialize the system to a state that meets the prerequisites of the DXE phase.
It is expected that, in the future, common practice will be that the vendor of a software or hardware component will
provide the PEIM (possibly in source form) so the customer can debug integration problems quickly.
I-6.7 PEIM-to-PEIM Interfaces (PPIs)
PEIMs communicate with each other using a structure called a PEIM-to-PEIM Interface (PPI). PPIs are contained in
aEFI_PEI_PPI_DESCRIPTOR data structure, which is composed of a GUID/pointer pair. The GUID “names” the
interface and the associated pointer provides the associated data structure and/or service set for that PPI. A consumer
of a PPI must use the PEI Service LocatePpi() to discover the PPI of interest. The producer of a PPI publishes the
available PPIs in its PEIM using the PEI Services InstallPpi() orReinstallPpi() .
All PEIMs are registered and located in the same fashion, namely through the PEI Services listed above. Within this
name space of PPIs, there are two classes of PPIs:
•Architectural PPIs
•Additional PPIs
Anarchitectural PPI is a PPI whose GUID is described in the PEI CIS and is a GUID known to the PEI Foundation.
These architectural PPIs typically provide a common interface to the PEI Foundation of a service that has a platform-
specific implementation, such as the PEI Service ReportStatusCode() .
I-6.5. PEI Dispatcher I-12UEFI Platform Initialization Specification, Release 1.8
Additional PPIs are PPIs that are important for interoperability but are not depended upon by the PEI Foundation.
They can be classified as mandatory or optional. Specifically, to have a large class of interoperable PEIMs, it would
be good to signal that the final boot mode was installed in some standard fashion so that PEIMs could use this PPI
in their dependency expressions. The alternative to defining these additional PPIs in the PEI CIS would be to have a
proliferation of similar services under different names.
I-6.8 Firmware Volumes
Pre-EFI Initialization Modules (PEIMs) reside in firmware volumes (FVs). The PEI phase supports the ability for
PEIMs to reside in multiple firmware volumes.. Other PEIMs can expose firmware volumes for use by the PEI Foun-
dation.
I-6.8. Firmware Volumes I-13CHAPTER
SEVEN
PEI SERVICES TABLE
I-7.1 Introduction
Note:In the PEI Foundation use of the EFI_TABLE_HEADER for the PEI Services Table, there is special treatment
of the CRC32 field. This value is ignorable for PEI and should be set to zero.
I-7.2 PEI Services Table
I-7.2.1 EFI_PEI_SERVICES
I-7.2.1.1 Summary
ThePEIServicesTableincludesalistoffunctionpointersinatable. Thetableislocatedinthetemporaryorpermanent
memory, depending upon the capabilities and phase of execution of PEI. The functions in this table are defined in
Services - PEI.
I-7.2.1.2 Related Definitions
//
// PI Specification Revision information
//
#define PI_SPECIFICATION_VERSION ((1<<16) | 80)
//
// PEI Services Table
//
#define PEI_SERVICES_SIGNATURE 0x5652455320494550
#define PEI_SERVICES_REVISION PI_SPECIFICATION_VERSION
typedef EFI_PEI_SERVICES {
I-14UEFI Platform Initialization Specification, Release 1.8
//
// PPI Functions
//
EFI_PEI_INSTALL_PPI InstallPpi;
EFI_PEI_REINSTALL_PPI ReInstallPpi;
EFI_PEI_LOCATE_PPI LocatePpi;
EFI_PEI_NOTIFY_PPI NotifyPpi;
//
// Boot Mode Functions
//
EFI_PEI_GET_BOOT_MODE GetBootMode;
EFI_PEI_SET_BOOT_MODE SetBootMode;
//
// HOB Functions
//
EFI_PEI_GET_HOB_LIST GetHobList;
EFI_PEI_CREATE_HOB CreateHob;
//
// Firmware Volume Functions
//
EFI_PEI_FFS_FIND_NEXT_VOLUME2 FfsFindNextVolume;
EFI_PEI_FFS_FIND_NEXT_FILE2 FfsFindNextFile;
EFI_PEI_FFS_FIND_SECTION_DATA2 FfsFindSectionData;
//
// PEI Memory Functions
//
EFI_PEI_INSTALL_PEI_MEMORY InstallPeiMemory;
EFI_PEI_ALLOCATE_PAGES AllocatePages;
EFI_PEI_ALLOCATE_POOL AllocatePool;
EFI_PEI_COPY_MEM CopyMem;
EFI_PEI_SET_MEM SetMem;
//
// Status Code
EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;
//
// Reset
//
EFI_PEI_RESET_SYSTEM ResetSystem;
//
// (the following interfaces are installed by publishing PEIM)
//
// I/O Abstractions
//
EFI_PEI_CPU_IO_PPI *CpuIo;
EFI_PEI_PCI_CFG2_PPI *PciCfg;
I-7.2. PEI Services Table I-15UEFI Platform Initialization Specification, Release 1.8
//
// Additional File System-Related Services
//
EFI_PEI_FFS_FIND_BY_NAME FfsFindFileByName;
EFI_PEI_FFS_GET_FILE_INFO FfsGetFileInfo;
EFI_PEI_FFS_GET_VOLUME_INFO FfsGetVolumeInfo;

//
//
//
//
//
//
// Reset
//
//
//
//
//
//
EFI_PEI_REGISTER_FOR_SHADOW RegisterForShadow;
EFI_PEI_FFS_FIND_SECTION_DATA3 FindSectionData3;
EFI_PEI_FFS_GET_FILE_INFO2 FfsGetFileInfo2;
EFI_PEI_RESET2_SYSTEM ResetSystem2;
EFI_PEI_FREE_PAGES FreePages;
} EFI_PEI_SERVICES;
I-7.2.1.3 Parameters
Hdr
The table header for the PEI Services Table. This header contains the PEI_SERVICES_SIGNATURE and
PEI_SERVICES_REVISION valuesalongwiththesizeofthe EFI_PEI_SERVICES structureanda32-bitCRCto
verify that the contents of the PEI Foundation Services Table are valid.
InstallPpi
InstallsaninterfaceinthePEIPEIM-to-PEIMInterface(PPI)databasebyGUID.Seethe InstallPpi() func-
tion description in this document.
ReInstallPpi
ReinstallsaninterfaceinthePEIPPIdatabasebyGUID.Seethe ReinstallPpi() functiondescriptioninthis
document.
LocatePpi
LocatesaninterfaceinthePEIPPIdatabasebyGUID.Seethe LocatePpi() functiondescriptioninthisdocu-
ment.
NotifyPpi
Installs the notification service to be called back upon the installation or reinstallation of a given interface. See
theNotifyPpi() function description in this document.
GetBootMode
Returns the present value of the boot mode. See the GetBootMode() function description in this document.
SetBootMode
Sets the value of the boot mode. See the SetBootMode() function description in this document.
GetHobList
ReturnsthepointertothelistofHand-OffBlocks(HOBs)inmemory. Seethe GetHobList() functiondescrip-
tion in this document.
CreateHob
Abstracts the creation of HOB headers. See the CreateHob() function description in this document.
FfsFindNextVolume
Discovers instances of firmware volumes in the system. See the FfsFindNextVolume() function description
in this document.
I-7.2. PEI Services Table I-16UEFI Platform Initialization Specification, Release 1.8
FfsFindNextFile
Discovers instances of firmware files in the system. See the FfsFindNextFile() function description in this
document.
FfsFindSectionData
Searchesforasectioninafirmwarefile. Seethe FfsFindSectionData() functiondescriptioninthisdocument.
InstallPeiMemory
Registers the found memory configuration with the PEI Foundation. See the InstallPeiMemory() function
description in this document.
AllocatePages
Allocates memory ranges that are managed by the PEI Foundation. See the AllocatePages() function de-
scription in this document.
AllocatePool
Frees memory ranges that are managed by the PEI Foundation. See the AllocatePool() function description
CopyMem
Copies the contents of one buffer to another buffer. See the CopyMem() function description in this document.
SetMem
Fills a buffer with a specified value. See the SetMem() function description in this document.
ReportStatusCode
Provides an interface that a PEIM can call to report a status code. See the ReportStatusCode() function
description in this document. This is installed by provider PEIM by copying the interface into the PEI Service
table.
ResetSystem
Resets the entire platform. See the ResetSystem() function description in this document. This is installed by
provider PEIM by copying the interface into the PEI Service table.
ResetSystem2
Resetstheentireplatform. Seethe ResetSystem2() functiondescriptioninthisdocument. Thisisinstalledby
CpuIo
Provides an interface that a PEIM can call to execute an I/O transaction. This interface is installed by provider
PEIM by copying the interface into the PEI Service table.
PciCfg
Provides an interface that a PEIM can call to execute PCI Configuration transactions. This interface is installed
by provider PEIM by copying the interface into the EFI_PEI_SERVICES table.
FfsFindFileByName
Discovers firmware files within a volume by name. See FfsFindFileByName() in this document.
FfsGetFileInfo
Return information about a particular file. See FfsGetFileInfo() in this document.
FfsGetFileInfo2
Return information about a particular file. See FfsGetFileInfo2() in this document.
FfsGetVolumeInfo
Return information about a particular volume. See FfsGetVolumeInfo() in this document.
RegisterForShadow
Register a driver to be re-loaded when memory is available. See RegisterForShadow() in this document.
I-7.2. PEI Services Table I-17UEFI Platform Initialization Specification, Release 1.8
FindSectionData3
Searches for a section in a firmware file. See the FfsFindSectionData3() function description in this docu-
ment.
FreePages
Releases memory previously allocated using AllocatePages() .
I-7.2.1.4 Description
EFI_PEI_SERVICES is a collection of functions whose implementation is provided by the PEI Foundation. These
services fall into various classes, including the following:
•Managing the boot mode
•Allocating both early and permanent memory
•Supporting the Firmware File System (FFS)
•Abstracting the PPI database abstraction
•Creating Hand-Off Blocks (HOBs)
Apointertothe EFI_PEI_SERVICES tableispassedintoeachPEIMwhenthePEIMisinvokedbythePEIFoundation.
As such, every PEIM has access to these services. Unlike the UEFI Boot Services, the PEI Services have no calling
restrictions, such as the UEFI 2.0 Task Priority Level (TPL) limitations. Specifically, a service can be called from a
PEIM or notification service.
Someoftheservicesarealsoaproxytoplatform-providedservices,suchastheResetServices,StatusCodeServices,
and I/O abstractions. This partitioning has been designed to provide a consistent interface to all PEIMs without en-
cumbering a PEI Foundation implementation with platform-specific knowledge. Any callable services beyond the set
in this table should be invoked using a PPI. The latter PEIM-installed services will return EFI_NOT_AVAILABLE_YET
until a PEIM copies an instance of the interface into the EFI_PEI_SERVICES table.
I-7.2. PEI Services Table I-18CHAPTER
EIGHT
SERVICES - PEI
I-8.1 Introduction
A PEI Service is defined as a function, command, or other capability created by the PEI Foundation during a phase
that remains available after the phase is complete. Because the PEI phase has no permanent memory available until
nearly the end of the phase, the range of PEI Foundation Services created during the PEI phase cannot be as rich as
those created during later phases.
PEI Services shows the PEI Services described in this section:
Table 8.1: PEI Services
PPI Services Manages PEIM to PEIM Interface PPIs to facilitate intermodule
calls between PEIMs Interfaces are installed and tracked on a
database maintained in temporary RAM
Boot Mode Services Manages the boot mode S3 S5 normal boot diagnostics etc of the
system
HOB Services Creates data structures called Hand Off Blocks HOBs that are used
to pass information to the next phase of the PI Architecture
Firmware Volume Services Walks the Firmware File Systems FFS in firmware volumes to find
PEIMs and other firmware files in the flash device
PEI Memory Services Provides a collection of memory management services for use both
before and after permanent memory has been discovered
Status Code Services Providescommonprogressanderrorcodereportingservicesforex-
ample port 080h or a serial port for simple text output for debug
Reset Services Providesacommonmeansbywhichtoinitiateawarmorcoldrestart
of the system
The calling convention for PEI Services is similar to PPIs. See PEIM-to-PEIM Communication for more details on
PPIs.
The means by which to bind a service call into a service involves a dispatch table, EFI_PEI_SERVICES . A pointer to
the table is passed into the PEIM entry point.
I-19UEFI Platform Initialization Specification, Release 1.8
I-8.2 PPI Services
The following services provide the interface set for abstracting the PPI database:
•InstallPpi()
•ReinstallPpi()
•LocatePpi()
•NotifyPpi()
I-8.2.1 InstallPpi()
Summary
ThisserviceisthefirstoneprovidedbythePEIFoundation. ThisfunctioninstallsaninterfaceinthePEIPPIdatabase
by GUID. The purpose of the service is to publish an interface that other parties can use to call additional PEIMs.
Prototype
typedef
(EFIAPI *EFI_PEI_INSTALL_PPI) (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
);
PeiServices
An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
PpiList
A pointer to the list of interfaces that the caller shall install. Type EFI_PEI_PPI_DESCRIPTOR is defined in
“PEIM Descriptors”.
This service enables a given PEIM to register an interface with the PEI Foundation. The interface takes a pointer to
a list of records that adhere to the format of a EFI_PEI_PPI_DESCRIPTOR . Since the PEI Foundation maintains a
pointer to the list rather than copying the list, the list must either be in the body of the PEIM or else allocated from
temporary or permanent RAM.
The length of the list of described by the EFI_PEI_PPI_DESCRIPTOR that has the
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST flag set in its Flagsfield. There shall be at least one
EFI_PEI_PPI_DESCRIPTOR in the list.
There are two types of EFI_PEI_PPI_DESCRIPTOR ``s that can be installed, including the

);
PpiList
``EFI_PEI_PPI_DESCRIPTOR_NOTIFY_DISPATCH andEFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK .
EFI_SUCCESS The interface was successfully installed
EFI_INVALID_PARAMETER The PpiList pointer is NULL
EFI_INVALID_PARAMETER Any of the PEI PPI descriptors in the list do not have the
EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field
EFI_OUT_OF_RESOURCES There is no additional space in the PPI database
I-8.2. PPI Services I-20UEFI Platform Initialization Specification, Release 1.8
I-8.2.2 ReinstallPpi()
Summary
This function reinstalls an interface in the PEI PPI database by GUID. The purpose of the service is to publish an
interface that other parties can use to replace an interface of the same name in the protocol database with a different
Prototype
typedef
(EFIAPI *EFI_PEI_REINSTALL_PPI) (
IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi,
IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi
);
OldPpi
ApointertotheformerPPIinthedatabase. Type EFI_PEI_PPI_DESCRIPTOR isdefinedin“PEIMDescriptors”.
NewPpi
A pointer to the new interfaces that the caller shall install.
This service enables PEIMs to replace an entry in the PPI database with an alternate entry.
EFI_INVALID_PARAMETER The OldPpi or NewPpi pointer is NULL
EFI_NOT_FOUND The PPI for which the reinstallation was requested has not been in-
stalled
I-8.2.3 LocatePpi()
Summary
This function locates an interface in the PEI PPI database by GUID.
Prototype
typedef
(EFIAPI *EFI_PEI_LOCATE_PPI) (
IN UINTN Instance,
I-8.2. PPI Services I-21UEFI Platform Initialization Specification, Release 1.8
IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor OPTIONAL,
IN OUT VOID **Ppi
);
An indirect pointer to the EFI_PEI_SERVICES published by the PEI Foundation.
Guid
A pointer to the GUID whose corresponding interface needs to be found.
Instance
The N-th instance of the interface that is required.
PpiDescriptor
A pointer to instance of the EFI_PEI_PPI_DESCRIPTOR .
Ppi
A pointer to the instance of the interface.
This service enables PEIMs to discover a given instance of an interface. This interface differs from the interface
discovery mechanism in the UEFI 2.0 specification, namely HandleProtocol() , in that the PEI PPI database does
not expose the handle’s name space. Instead, PEI manages the interface set by maintaining a partial order on the
interfaces such that the Instance of the interface, among others, can be traversed.
LocatePpi() provides the ability to traverse all of the installed instances of a given GUID-named PPI. For example,
there can be multiple instances of a PPI named Fooin the PPI database. An Instance value of 0 will provide the
first instance of the PPI that is installed. Correspondingly, an Instance value of 2 will provide the second, 3 the
third,andsoon. The Instance valuedesignateswhenaPPIwasinstalled. Foranimplementationthatmustreference
all possible manifestations of a given GUID-named PPI, the code should invoke LocatePpi() with a monotonically
increasing Instance number until EFI_NOT_FOUND is returned.
EFI_SUCCESS The interface was successfully returned.
EFI_NOT_FOUND The PPI descriptor is not found in the database.
I-8.2.4 NotifyPpi()
Summary
This function installs a notification service to be called back when a given interface is installed or reinstalled. The
purpose of the service is to publish an interface that other parties can use to call additional PPIs that may materialize
later.
Prototype
typedef
(EFIAPI *EFI_PEI_NOTIFY_PPI) (
IN CONST EFI_PEI_NOTIFY_DESCRIPTOR *NotifyList
);
I-8.2. PPI Services I-22UEFI Platform Initialization Specification, Release 1.8
NotifyList
A pointer to the list of notification interfaces that the caller shall install. Type EFI_PEI_NOTIFY_DESCRIPTOR
is defined in “PEIM Descriptors”.
This service enables PEIMs to register a given service to be invoked when another service is installed or reinstalled.
This service will fire notifications on PPIs installed prior to this service invocation. This is different behavior than the
RegisterProtocolNotify of UEFI2.0, for example EFI_PEI_NOTIFY_DESCRIPTOR is defined in “PEIM Descriptors”.
Inaddition,thePPIpointerispassedbacktotheagentthatregisteredforthenotificationsothatitcandeferenceprivate
data, if so needed.
EFI_INVALID_PARAMETER The NotifyList pointer is NULL
EFI_INVALID_PARAMETER Any of the PEI notify descriptors in the list do not have
the EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES bit set in the
Flags field
I-8.3 Boot Mode Services
These services provide abstraction for ascertaining and updating the boot mode:
•GetBootMode()
•SetBootMode()
SeeBoot Paths for additional information on the boot mode.
I-8.3.1 GetBootMode()
Summary
This function returns the present value of the boot mode.
Prototype
typedef
(EFIAPI *EFI_PEI_GET_BOOT_MODE) (
OUT EFI_BOOT_MODE *BootMode
);
I-8.3. Boot Mode Services I-23UEFI Platform Initialization Specification, Release 1.8
BootMode
Apointertocontainthevalueofthebootmode. Type EFI_BOOT_MODE isdefinedin“RelatedDefinitions”below.
ThisserviceenablesPEIMstoascertainthepresentvalueofthebootmode. Thelistofpossiblebootmodesisdescribed
in “Related Definitions” below.
// EFI_BOOT_MODE
typedef UINT32 EFI_BOOT_MODE;
#define BOOT_WITH_FULL_CONFIGURATION 0x00
#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01
#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02
#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03
#define BOOT_WITH_DEFAULT_SETTINGS 0x04
#define BOOT_ON_S4_RESUME 0x05
#define BOOT_ON_S5_RESUME 0x06
#define BOOT_WITH_MFG_MODE_SETTINGS 0x07
#define BOOT_ON_S2_RESUME 0x10
#define BOOT_ON_S3_RESUME 0x11
#define BOOT_ON_FLASH_UPDATE 0x12
#define BOOT_IN_RECOVERY_MODE 0x20
0x21 - 0xF..F Reserved Encodings
Boot Mode Register describes the bit values in the Boot Mode Register.
Table 8.2: Boot Mode Register
Register Bits Values Descriptions
MSBit 0 000000b Boot with full configuration
000001b Boot with minimal configuration
000010b Boot assuming no configuration changes from last boot
000011b Boot with full configuration plus diagnostics
000100b Boot with default settings
000101b Boot on S4 resume
000110b Boot in S5 resume
000111b Boot with manufacturing mode settings
000111b 001111b Reserved for boot paths that configure memory
010000b Boot on S2 resume
010001b Boot on S3 resume
010010b Boot on flash update restart
010011c 011111b Reserved for boot paths that preserve memory context
100000b Boot in recovery mode
100001b 111111b Reserved for special boots
I-8.3. Boot Mode Services I-24UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The boot mode was returned successfully.
I-8.3.2 SetBootMode()
Summary
This function sets the value of the boot mode.
Prototype
typedef
(EFIAPI *EFI_PEI_SET_BOOT_MODE) (
IN EFI_BOOT_MODE BootMode
);
BootMode
The value of the boot mode to set. Type EFI_BOOT_MODE is defined in GetBootMode() .
This service enables PEIMs to update the boot mode variable. This would be used by either the boot mode PPIs
described in See Architectural PPIs. or by a PEIM that needs to engender a recovery condition. It is permissible to
change the boot mode at any point during the PEI phase.
EFI_SUCCESS The value was successfully updated.
I-8.4 HOB Services
The following services describe the capabilities in the PEI Foundation for providing Hand-Off Block (HOB) manipu-
lation:
•GetHobList()
•CreateHob()
The purpose of the abstraction is to automate the common case of HOB creation and manipulation. See Volume 3 for
details on HOBs and their type definitions.

);
BootMode
lation:
I-8.4. HOB Services I-25UEFI Platform Initialization Specification, Release 1.8
I-8.4.1 GetHobList()
Summary
This function returns the pointer to the list of Hand-Off Blocks (HOBs) in memory.
Prototype
typedef
(EFIAPI *EFI_PEI_GET_HOB_LIST) (
IN OUT VOID **HobList
);
HobList
A pointer to the list of HOBs that the PEI Foundation will initialize.
ThisserviceenablesaPEIMtoascertaintheaddressofthelistofHOBsinmemory. Thisserviceshouldnotberequired
by many modules in that the creation of HOBs is provided by the PEI Service CreateHob() .
EFI_SUCCESS The list was successfully returned.
EFI_NOT_AVAILABLE_YET The HOB list is not yet published.
I-8.4.2 CreateHob()
Summary
This service published by the PEI Foundation abstracts the creation of a Hand-Off Block’s (HOB’s) headers.
Prototype
typedef
(EFIAPI *EFI_PEI_CREATE_HOB) (
IN UINT16 Length,
IN OUT VOID **Hob
);
Type
The type of HOB to be installed. See the Volume 3 for a definition of this type.
I-8.4. HOB Services I-26UEFI Platform Initialization Specification, Release 1.8
Length
The length of the HOB to be added.
Hob
The address of a pointer that will contain the HOB header.
This service enables PEIMs to create various types of HOBs. This service handles the common work of allocating
memoryontheHOBlist,fillinginthetypeandlengthfields,andbuildingtheendoftheHOBlist. Thefinalaspectof
this service is to return a pointer to the newly allocated HOB. At this point, the caller can fill in the type-specific data.
This service is always available because the HOBs can also be created on temporary memory.
There will be no error checking on the Lengthinput argument. Instead, the PI Architecture implementation of this
service will round up the allocation size that is specified in the Lengthfield to be a multiple of 8 bytes in length.
This rounding is consistent with the requirement that all of the HOBs, including the PHIT HOB, begin on an 8-byte
boundary. See the PHIT HOB definition in the Platform Initialization Specification, Volume 3, for more information.
EFI_SUCCESS The HOB was successfully created.
EFI_OUT_OF_RESOURCES There is no additional space for HOB creation.
I-8.5 Firmware Volume Services
The following services abstract traversing the Firmware File System (FFS):
•FfsFindNextVolume()
•FfsFindNextFile()
•FfsFindSectionData()
•FfsFindFileByName()
•FfsGetFileInfo()
•FfsGetVolumeInfo()
The description of the FFS can be found in the Platform Initialization Specification , Volume 3.
I-8.5.1 FfsFindNextVolume()
Summary
ThepurposeoftheserviceistoabstractthecapabilityofthePEIFoundationtodiscoverinstancesoffirmwarevolumes
Prototype
typedef
(EFIAPI *EFI_PEI_FFS_FIND_NEXT_VOLUME2) (
OUT EFI_PEI_FV_HANDLE *VolumeHandle
);
I-8.5. Firmware Volume Services I-27UEFI Platform Initialization Specification, Release 1.8
Instance
This instance of the firmware volume to find. The value 0 is the Boot Firmware Volume (BFV).
VolumeHandle
On exit, points to the next volume handle or NULLif it does not exist.
This service enables PEIMs to discover additional firmware volumes. The core uses
EFI_PEI_FIRMWARE_VOLUME_INFO_PPI to discover these volumes. The service returns a volume handle of
typeEFI_PEI_FV_HANDLE , which must be unique within the system.
typedef VOID *EFI_PEI_FV_HANDLE;
EFI_SUCCESS The volume was found.
EFI_NOT_FOUND The volume was not found.
EFI_INVALID_PARAMETER VolumeHandle isNULL
I-8.5.2 FfsFindNextFile()
Summary
Searches for the next matching file in the firmware volume.
Prototype
typedef
(EFIAPI *EFI_PEI_FFS_FIND_NEXT_FILE2) (
IN EFI_FV_FILETYPE SearchType,
IN CONST EFI_PEI_FV_HANDLE FvHandle,
IN OUT EFI_PEI_FILE_HANDLE *FileHandle
);
SearchType
A filter to find files only of this type. Type EFI_FV_FILETYPE is defined in the Platform Initialization Specifi-
cation,Volume 3. Type EFI_FV_FILETYPE_ALL causes no filtering to be done.
FvHandle
Handle of firmware volume in which to search. The type EFI_PEI_FV_HANDLE is defined in the PEI Services
FfsFindNextVolume() .
FileHandle
On entry, points to the current handle from which to begin searching or NULL to start at the beginning of the
I-8.5. Firmware Volume Services I-28UEFI Platform Initialization Specification, Release 1.8
firmwarevolume. Onexit,pointsthefilehandleofthenextfileinthevolumeorNULLiftherearenomorefiles.
The typeEFI_PEI_FILE_HANDLE is defined in “Related Defintions” below.
ThisserviceenablesPEIMstodiscoverfirmwarefileswithinaspecifiedvolume. Tofindthefirstinstanceofafirmware
file, pass a FileHandle value ofNULLinto the service.
The service returns a file handle of type EFI_PEI_FILE_HANDLE , which must be unique within the system.
The behavior of files with file types EFI_FV_FILETYPE_FFS_MIN andEFI_FV_FILETYPE_FFS_MAX depends on the
firmwarefilesystem. FormoreinformationonthespecificbehaviorforthestandardPIfirmwarefilesystem,seesection
1.1.4.1.6 of the PI Specification, Volume 3.
typedef VOID *EFI_PEI_FILE_HANDLE;
EFI_SUCCESS The file was found.
EFI_NOT_FOUND The file was not found.
EFI_NOT_FOUND The header checksum was not zero.
I-8.5.3 FfsFindSectionData()
Summary
Searches for the next matching section within the specified file.
Prototype
typedef
(EFIAPI *EFI_PEI_FFS_FIND_SECTION_DATA2) (
IN EFI_SECTION_TYPE SectionType,
IN EFI_PEI_FILE_HANDLE FileHandle,
OUT VOID **SectionData
);
SectionType
Thevalueofthesectiontypetofind. Type EFI_SECTION_TYPE isdefinedinthe PlatformInitializationSpecifi-
cation,Volume 3.
Handle of the firmware file to search. Type EFI_PEI_FILE_HANDLE is defined in FfsFindNextFile() , “Re-
lated Definitions.” A pointer to the file header that contains the set of sections to be searched.
SectionData
A pointer to the discovered section, if successful.
I-8.5. Firmware Volume Services I-29UEFI Platform Initialization Specification, Release 1.8
This service enables PEI modules to discover the first section of a given type within a valid file. This service will
searchwithinencapsulationsections(compressionandGUIDed)aswell. ItwillsearchinsideofaGUIDedsectionor
a compressed section, but may not, for example, search a GUIDed section inside a GUIDes section.
This service will not search within compression sections or GUIDed sections which require extraction if memory is
not present.
EFI_SUCCESS The section was found.
EFI_NOT_FOUND The section was not found.
I-8.5.4 FfsFindSectionData3()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_FFS_FIND_SECTION_DATA3) (
In UINTN SectionInstance
OUT UINT32 *AuthenticationStatus
);
SectionInstance
Section instance to find.
AuthenticationStatus
A pointer to the authentication status for this section.
This service enables PEI modules to discover the section of a given type within a valid file. This service will search
within encapsulation sections (compression and GUIDed) as well. It will search inside of a GUIDed section or a
compressed section, but may not, for example, search a GUIDed section inside a GUIDes section.
I-8.5. Firmware Volume Services I-30UEFI Platform Initialization Specification, Release 1.8

I-8.5.5 FfsFindFileByName()
Summary
Find a file within a volume by its name.
Prototype
typedef
(EFIAPI *EFI_PEI_FFS_FIND_BY_NAME) (
IN CONST EFI_GUID *FileName,
IN EFI_PEI_FV_HANDLE VolumeHandle,
OUT EFI_PEI_FILE_HANDLE *FileHandle
);
FileName
A pointer to the name of the file to find within the firmware volume.
The firmware volume to search
Upon exit, points to the found file’s handle or NULLif it could not be found.
Thisservicesearchesforfileswithaspecificname,withineitherthespecifiedfirmwarevolumeorallfirmwarevolumes.
Table 8.3: Status Codes Returned
EFI_SUCCESS File was found
EFI_NOT_FOUND File was not found
EFI_INVALID_PARAMETER VolumeHandle or FileHandle or FileName was NULL
I-8.5. Firmware Volume Services I-31UEFI Platform Initialization Specification, Release 1.8
I-8.5.6 FfsGetFileInfo()
Summary
Returns information about a specific file.
Prototype
typedef
(EFIAPI \*EFI_PEI_FFS_GET_FILE_INFO) (
OUT EFI_FV_FILE_INFO *FileInfo
);
Handle of the file.
FileInfo
Upon exit, points to the file’s information.
Thisfunctionreturnsinformationaboutaspecificfile,includingitsfilename,type,attributes,startingaddressandsize.
If the firmware volume is not memory mapped then the Buffermember will be NULL.
EFI_GUID FileName;
EFI_FV_FILETYPE FileType;
EFI_FV_FILE_ATTRIBUTES FileAttributes;
UINT32 BufferSize;
} EFI_FV_FILE_INFO;
FileName
Name of the file.
FileType
File type. See EFI_FV_FILETYPE , which is defined in the Platform Initialization Firmware Storage Specifica-
tion.
FileAttributes
Attributesofthefile. Type EFI_FV_FILE_ATTRIBUTES isdefinedinthe PlatformInitializationFirmwareStor-
age Specification .
Buffer
Points to the file’s data (not the header). Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED is zero.
Size of the file’s data.
EFI_SUCCESS File information returned.
EFI_INVALID_PARAMETER IfFileHandle does not represent a valid file.
EFI_INVALID_PARAMETER IfFileInfois NULL
I-8.5. Firmware Volume Services I-32UEFI Platform Initialization Specification, Release 1.8
I-8.5.7 FfsGetFileInfo2()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_FFS_GET_FILE_INFO2) (
OUT EFI_FV_FILE_INFO2 *FileInfo
);
FileInfo
This function returns information about a specific file, including its file name, type, attributes, starting address, size
and authentication status. If the firmware volume is not memory mapped then the Buffermember will be NULL.
UINT32 AuthenticationStatus;
} EFI_FV_FILE_INFO2;
FileName
FileType
Filetype. See EFI_FV_FILETYPE ,whichisdefinedinthe PlatformInitializationFirmwareStorageSpecification
.
Buffer
Authentication status for this file.
I-8.5. Firmware Volume Services I-33UEFI Platform Initialization Specification, Release 1.8
I-8.5.8 FfsGetVolumeInfo()
Summary
Returns information about the specified volume.
Prototype
typedef
(EFIAPI *EFI_PEI_FFS_GET_VOLUME_INFO) (
OUT EFI_FV_INFO *VolumeInfo
);
Handle of the volume.
VolumeInfo
Upon exit, points to the volume’s information.
EFI_FVB_ATTRIBUTES_2 FvAttributes;
EFI_GUID FvFormat;
EFI_GUID FvName;
VOID* FvStart;
UINT64 FvSize;
} EFI_FV_INFO;
FvAttributes
Attributes of the firmware volume. Type EFI_FVB_ATTRIBUTES_2 is defined in the Platform Initialization
Firmware Storage Specficiation .
FvFormat
Format of the firmware volume. For PI Architecture Firmware Volumes, this can be copied from
FileSystemGuid inEFI_FIRMWARE_VOLUME_HEADER .
FvName
Nameofthefirmwarevolume. ForPIArchitectureFirmwareVolumes,thiscanbecopiedfrom VolumeName in
the extended header of EFI_FIRMWARE_VOLUME_HEADER .
FvStart
Points to the first byte of the firmware volume, if bit EFI_FVB_MEMORY_MAPPED is set inFvAttributes .
FvSize
Size of the firmware volume.
I-8.5. Firmware Volume Services I-34UEFI Platform Initialization Specification, Release 1.8
Thisfunctionreturnsinformationaboutaspecificfirmwarevolume,includingitsname,type,attributes,startingaddress
and size.
EFI_SUCCESS Volume information returned
EFI_INVALID_PARAMETER If VolumeHandle does not represent a valid volume
EFI_INVALID_PARAMETER If VolumeInfo is NULL
EFI_SUCCESS Information successfully returned
EFI_INVALID_PARAMETER The volume designated by the VolumeHandle is not available
I-8.5.9 RegisterForShadow()
Summary
Register a PEIM so that it will be shadowed and called again.
Prototype
typedef
(EFIAPI *EFI_PEI_REGISTER_FOR_SHADOW) (
IN EFI_PEI_FILE_HANDLE FileHandle
);
PEIM’s file handle. Must be the currently executing PEIM.
Thisserviceregistersafilehandlesothataftermemoryisavailable,thePEIMwillbere-loadedintopermanentmemory
and re-initialized. The PEIM registered this way will always be initialized twice. The first time, this function call will
returnEFI_SUCCESS . The second time, this function call will return EFI_ALREADY_STARTED .
DependingontheorderinwhichPEIMsaredispatched,thePEIMmakingthiscallmaybeinitializedafterpermanent
memory is installed, even the first time.
EFI_SUCCESS The PEIM was successfully registered for shadowing
EFI_ALREADY_STARTED The PEIM was previously registered for shadowing
EFI_NOT_FOUND The FileHandle does not refer to a valid file handle
I-8.6 PEI Memory Services
The following services are a collection of memory management services for use both before and after permanent
memory has been discovered:
•InstallPeiMemory()
•AllocatePages()
•AllocatePool()
I-8.6. PEI Memory Services I-35UEFI Platform Initialization Specification, Release 1.8
•CopyMem()
•SetMem()
•FreePages()
I-8.6.1 InstallPeiMemory()
Summary
This function registers the found memory configuration with the PEI Foundation.
Prototype
typedef
(EFIAPI *EFI_PEI_INSTALL_PEI_MEMORY) (
IN EFI_PHYSICAL_ADDRESS MemoryBegin,
IN UINT64 MemoryLength
);
MemoryBegin
The value of a region of installed memory.
MemoryLength
The corresponding length of a region of installed memory.
This service enables PEIMs to register the permanent memory configuration that has been initialized with the PEI
Foundation. Theresultofthiscall-setisthecreationoftheappropriateHand-OffBlock(HOB)describingthephysical
memory.
TheusagemodelisthatthePEIMthatdiscoversthepermanentmemoryshallinvokethisservice. Thememoryreported
is a single contiguous run. It should be enough to allocate a PEI stack and some HOB list. The full memory map
will be reported using the appropriate memory HOBs. The PEI Foundation will follow up with an installation of
EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI .
Any invocations of this service after the first invocation which returns EFI_SUCCESS will be ignored.
EFI_SUCCESS The region was successfully installed in a HOB or this service was
successfully invoked earlier and no HOB modification will occur
EFI_INVALID_PARAMETER MemoryBegin andMemoryLength are illegal for this system
EFI_OUT_OF_RESOURCES There is no additional space for HOB creation
I-8.6. PEI Memory Services I-36UEFI Platform Initialization Specification, Release 1.8
I-8.6.2 AllocatePages()
Summary
ThepurposeoftheserviceistopublishaninterfacethatallowsPEIMstoallocatememoryrangesthataremanagedby
the PEI Foundation.
Prototype
typedef
(EFIAPI *EFI_PEI_ALLOCATE_PAGES) (
OUT EFI_PHYSICAL_ADDRESS *Memory,
);

Summary
Prototype
typedef
);
MemoryType
The type of memory to allocate. The only types allowed are EfiLoaderCode ,EfiLoaderData
,EfiRuntimeServicesCode ,EfiRuntimeServicesData ,EfiBootServicesCode ,
EfiBootServicesData ,EfiACPIReclaimMemory, EfiReservedMemoryType , andEfiACPIMemoryNVS
.
Pages
The number of contiguous 4 KiB pages to allocate. Type EFI_PHYSICAL_ADDRESS is defined in
AllocatePages() in the UEFI 2.0 specification.
Memory
Pointer to a physical address. On output, the address is set to the base of the page range that was allocated.
This service allocates the requested number of pages and returns a pointer to the base address of the page range in
the location referenced by Memory. The service scans the available memory to locate free pages. When it finds a
physically contiguous block of pages that is large enough it creates a memory allocation HOB describing the region
with the requested MemoryType.
Allocation made prior to permanent memory will be migrated to permanent memory and the HOB updated.
The expectation is that the implementation of this service will automate the creation of the Memory Allocation HOB
types. As such, this is in the same spirit as the PEI Services to create the FV HOB, for example.
Prior to InstallPeiMemory() being called, PEI will allocate pages from the heap. After InstallPeiMemory() is called,
PEI will allocate pages within the region of memory provided by InstallPeiMemory() service in a best-effort fashion.
Location-specific allocations are not managed by the PEI foundation code.
TheservicealsosupportsthecreationofMemoryAllocationHOBsthatdescribethestack,boot-strapprocessor(BSP)
BSPStore(“BackingStorePointerStore”),andtheDXEFoundationallocation. Thisadditionalinformationisconveyed
through the final two arguments in this API and the description of the appropriate HOB types can be found in the
Platform Initialization Specification , Volume 3.
I-8.6. PEI Memory Services I-37UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The memory range was successfully allocated.
EFI_OUT_OF_RESOURCES The page could not be allocated.
EFI_INVALID_PARAMETER Type is not equal to EfiLoaderCode ,EfiLoaderData ,
EfiRuntimeServicesCode ,EfiRuntimeServicesData ,
EfiBootServices , EfiBootServicesData ,
EfiACPIReclaimMemory ,EfiReservedMemoryType , or
EfiACCPIMemoryNVS .
I-8.6.3 AllocatePool()
Summary
The purpose of this service is to publish an interface that allows PEIMs to allocate memory ranges that are managed
by the PEI Foundation.
Prototype
typedef
(EFIAPI *EFI_PEI_ALLOCATE_POOL) (
);
Size
The number of bytes to allocate from the pool.
Buffer
If the call succeeds, a pointer to a pointer to the allocated buffer; undefined otherwise.
This service allocates memory from the Hand-Off Block (HOB) heap. Because HOBs can be allocated from either
temporary or permanent memory, this service is available throughout the entire PEI phase.
ThisserviceallocatesmemoryinmultiplesofeightbytestomaintaintherequiredHOBalignment. Theearlyallocations
from temporary memory will be migrated to permanent memory when permanent main memory is installed; this
migration shall occur when the HOB list is migrated to permanent memory.
EFI_SUCCESS The allocation was successful
EFI_OUT_OF_RESOURCES There is not enough heap to allocate the requested size
I-8.6. PEI Memory Services I-38UEFI Platform Initialization Specification, Release 1.8
I-8.6.4 CopyMem()
Summary
This service copies the contents of one buffer to another buffer.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_COPY_MEM) (
);
Destination
Pointer to the destination buffer of the memory copy.
Source
Pointer to the source buffer of the memory copy.
Length
Number of bytes to copy from SourcetoDestination .
This function copies Lengthbytes from the buffer Sourceto the buffer Destination .
None.
I-8.6.5 FreePages()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_FREE_PAGES) (
IN EFI_PHYSICAL_ADDRESS Memory
);
Memory
The base physical address of the pages to be freed. Type EFI_PHYSICAL_ADDRESS is defined in the
EFI_BOOT_SERVICES.AllocatePages()function description.
I-8.6. PEI Memory Services I-39UEFI Platform Initialization Specification, Release 1.8
Pages
The number of contiguous 4KiB pages to free.
Descripotion
The FreePages() function returns memory allocated by AllocatePages() to the firmware.
EFI_SUCCESS The requested memory pages were freed
EFI_NOT_FOUND TherequestedmemorypageswerenotallocatedwithAllocatePages
EFI_INVALID_PARAMETER Memory is not a page aligned address or Pages is invalid
I-8.6.6 SetMem()
Summary
The service fills a buffer with a specified value.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_SET_MEM) (
);
Buffer
Pointer to the buffer to fill.
Size
Number of bytes in Bufferto fill.
Value
Value to fill Bufferwith.
This function fills Sizebytes ofBufferwithValue.
None.
I-8.7 Status Code Service
The PEI Foundation publishes the following status code service:
•ReportStatusCode()
This service will report EFI_NOT_AVAILABLE_YET until a PEIM publishes the services for other modules. For the
GUID of the PPI, see EFI_PEI_PROGRESS_CODE_PPI .
I-8.7. Status Code Service I-40UEFI Platform Initialization Specification, Release 1.8
I-8.7.1 ReportStatusCode()
Summary
This service publishes an interface that allows PEIMs to report status codes.
Prototype
typedef
(EFIAPI \*EFI_PEI_REPORT_STATUS_CODE) (
IN EFI_STATUS_CODE_TYPE Type,
IN EFI_STATUS_CODE_VALUE Value,
IN UINT32 Instance,
IN CONST EFI_GUID *CallerId OPTIONAL,
IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL
);
Type
Indicates the type of status code being reported. The type EFI_STATUS_CODE_TYPE is defined in “Related
Definitions” below.
Value
Describes the current status of a hardware or software entity. This includes information about the class and
subclass that is used to classify the entity as well as an operation. For progress codes, the operation is the
current activity. For error codes, it is the exception. For debug codes, it is not defined at this time. Type
EFI_STATUS_CODE_VALUE is defined in “Related Definitions” below.
Instance
The enumeration of a hardware or software entity within the system. A system may contain multiple entities
that match a class/subclass pairing. The instance differentiates between them. An instance of 0 indicates that
instance information is unavailable, not meaningful, or not relevant. Valid instance numbers start with 1.
CallerId
Thisoptionalparametermaybeusedtoidentifythecaller. Thisparameterallowsthestatuscodedrivertoapply
different rules to different callers.
Data
Thisoptionalparameter maybeusedtopass additionaldata. Type EFI_STATUS_CODE_DATA isdefinedin “Re-
lated Definitions“ below. The contents of this data type may have additional GUID-specific data.
ReportStatusCode() is called by PEIMs that wish to report status information on their progress. The principal use
model is for a PEIM to emit one of the standard 32-bit error codes. This will allow a platform owner to ascertain the
state of the system, especially under conditions where the full consoles might not have been installed.
This is the entry point that PEIMs shall use. This service can use all platform PEI Services, and when main memory
is available, it can even construct a GUIDed HOB that conveys the pre-DXE data. This service can also publish an
interface that is usable only from the DXE phase. This entry point should not be the same as that published to the
PEIMs, and the implementation of this code path should notdo the following:
•Use any PEI Services or PPIs from other modules.
•Make any presumptions about global memory allocation.
I-8.7. Status Code Service I-41UEFI Platform Initialization Specification, Release 1.8
It can only operate on its local stack activation frame and must be careful about using I/O and memory-mapped I/O
resources. Theseconcerns,includingthelatterwarning,arisebecausethisservicecouldbeusedduringthe“blackout”
period between the termination of PEI and the beginning of DXE, prior to the loading of the DXE progress code
driver. As such, the ownership of the memory map and platform resource allocation is indeterminate at this point in
the platform evolution.
//
// Status Code Type Definition
//

//
//
typedef UINT32 EFI_STATUS_CODE_TYPE;
//
// A Status Code Type ismade up of the code type andseverity
// All values masked by EFI_STATUS_CODE_RESERVED_MASK are
// reserved foruse by this specification.
//
#define EFI_STATUS_CODE_TYPE_MASK 0x000000FF
#define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000
#define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00
//
// Definition of code types, all other values masked by
// EFI_STATUS_CODE_TYPE_MASK are reserved foruse by
// this specification.
//
#define EFI_PROGRESS_CODE 0x00000001
#define EFI_ERROR_CODE 0x00000002
#define EFI_DEBUG_CODE 0x00000003
//
// Definitions of severities, all other values masked by
// EFI_STATUS_CODE_SEVERITY_MASK are reserved foruse by
// Uncontained errors are major errors that could notcontained
// to the specific component that isreporting the error
// For example, ifa memory error was notdetected early enough,
// the bad data could be consumed by other drivers.
//
#define EFI_ERROR_MINOR 0x40000000
#define EFI_ERROR_MAJOR 0x80000000
#define EFI_ERROR_UNRECOVERED 0x90000000
#define EFI_ERROR_UNCONTAINED 0xa0000000
//
// Status Code Value Definition
//
typedef UINT32 EFI_STATUS_CODE_VALUE;
//
// A Status Code Value ismade up of the class, subclass, and
// an operation.
//
I-8.7. Status Code Service I-42UEFI Platform Initialization Specification, Release 1.8
#define EFI_STATUS_CODE_CLASS_MASK 0xFF000000
#define EFI_STATUS_CODE_SUBCLASS_MASK 0x00FF0000
#define EFI_STATUS_CODE_OPERATION_MASK 0x0000FFFF
//
// Definition of Status Code extended data header.
// The data will follow HeaderSize bytes from the beginning of
// the structure and isSize bytes long.
//
UINT16 HeaderSize;
} EFI_STATUS_CODE_DATA;
HeaderSize
The size of the structure. This is specified to enable future expansion.
Size
The size of the data in bytes. This does not include the size of the header structure.
Type
The GUID defining the type of the data.
EFI_NOT_AVAILABLE_YET No progress code provider has installed an interface in the system
I-8.8 Reset Services
The PEI Foundation publishes the following reset service:
•ResetSystem()
I-8.8.1 ResetSystem()
Summary
Resets the entire platform.
Prototype
typedef
(EFIAPI *EFI_PEI_RESET_SYSTEM) (
IN CONST EFI_PEI_SERVICES **PeiServices
);
I-8.8. Reset Services I-43UEFI Platform Initialization Specification, Release 1.8
This service resets the entire platform, including all processors and devices, and reboots the system. It is important to
have a standard variant of this function for cases such as the following:
•Resetting the processor to change frequency settings
•Restarting hardware to complete chipset initialization
•Responding to exceptions from a catastrophic errorReturned Status Codes
EFI_NOT_AVAILABLE_YET The service has not been installed yet.
I-8.9 I/O and PCI Services
•The PEI Foundation publishes CPU I/O and PCI Configuration services.
I-8.9. I/O and PCI Services I-44CHAPTER
NINE
PEI FOUNDATION
I-9.1 Introduction
The PEI Foundation centers around the PEI Dispatcher. The dispatcher’s job is to hand control to the PEIMs in an
orderly manner. The PEI Foundation also assists in PEIM-to-PEIM communication. The central resource for the
module-to-module communication involves the PPI. The marshalling of references to PPIs can occur using the instal-
lable or notification interface.
The PEI Foundation is constructed as an autonomous binary image that is of file type EFI_FV_FILETYPE_PEI_CORE
and is composed of the following:
•An authentication section
•A code image that is possibly PE32+
See thePlatform Initialization Specification , Volume 3, for information on section and file types. If the code that
comprises the PEI Foundation is not a PE32+ image, then it is a raw binary whose lowest address is the entry point to
the PEI Foundation. The PEI Foundation is discovered and authenticated by the Security (SEC) phase.
I-9.1.1 Prerequisites
The PEI phase is handed control from the Security (SEC) phase of the PI Architecture-compliant boot process. The
PEI phase must satisfy the following minimum prerequisites before it can begin execution:
•Processor execution mode
•Access to the firmware volume that contains the PEI Foundation
It is expected that the SEC infrastructure code and PEI Foundation are not linked together as a single ROMable ex-
ecutable image. The entry point from SEC into PEI is not architecturally fixed but is instead dependent on the PEI
Foundation location within FV0, or the Boot Firmware Volume.
I-9.1.2 Processor Execution Mode
I-9.1.2.1 Processor Execution Mode in IA-32 Intel ®Architecture
InIA-32Intelarchitecture,theSecurity(SEC)phaseofthePIArchitectureisresponsibleforplacingtheprocessorina
nativelinearaddressmodebywhichthefulladdressrangeoftheprocessorisaccessibleforcode,data,andstack. For
example,“flat32”istheIA-32processorgenerationmodeinwhichthePEIphasewillexecute. Theprocessormustbe
in its most privileged “ring 0” mode, or equivalent, and be able to access all memory and I/O space.
This prerequisite is strictly dependent on the processor generation architecture.
I-45UEFI Platform Initialization Specification, Release 1.8
I-9.1.2.2 Processor Execution Mode in Itanium ®Processor Family
ThePEIFoundationwillbeginexecutingaftertheSecurity(SEC)phasehascompleted. TheSECphasesubsumedthe
System Abstraction Layer entry point (SALE_ENTRY) in Itanium ®architecture. In addition, the SEC phase makes
the appropriate Processor Abstraction Layer (PAL) calls or platform services to enable the temporary memory store.
TheSECpassesitshandoffstatetothePEIFoundationinphysicalmodewithsomeconfiguredmemorystack,suchas
the processor cache configured as memory.
I-9.1.2.3 Access to the Boot Firmware Volume (BFV) andother boot-critical FVs
The program that the Security (SEC) phase hands control to is known as the PEI Foundation. PEIMs may reside in
the BFVor other FVs. A “special” PEIM must be resident in the BFV to provide information about the location of the
other FVs.
Eachfilethatisrequiredtoboot,intheBFVandothercriticalFVs(likewherethePEIfoundationislocated),mustbe
able to be discovered and validated by the PEI phase. This allows the PEI phase to determine if those FVs have been
corrupted.
ThePEIFoundationandthePEIMsareexpectedtobestoredinsomereasonablytamper-proof(albeitnotnecessarilyin
thestrictsecurity-baseddefinitionoftheterm)nonvolatilestorage(NVS).Thestorageisexpectedtobefairlyanalogous
toaflatfilesystemwiththeuniqueIDssubstitutingfornames. RulesforusingtheparticularNVSmightaffectcertain
storageconsiderations,butastandarddata-onlymechanismforlocatingPEIMsbyIDisrequired. ThePIArchitecture
architecturedescribesthePIFirmwareVolumeformatandPIFirmwareFileSystemformat,withtheGUIDconvention
ofnamingfiles. ThesestandardsarearchitecturalforPEIinasmuchasthePEIphaseneedstodirectlysupportthisfile
system.
The BFV can only be constructed of type EFI_FIRMWARE_FILE_SYSTEM2_GUID .
ThePEIFoundation,andsomePEIMsrequiredforrecovery,mustbeeitherlockedintoanonupdateableFVormustbe
abletobeupdatedviaa“fault-tolerant”mechanism. Thefault-tolerantmechanismisdesignedsuchthat,ifthesystem
halts at any point, either the old (preupdate) PEIM or the newly updated PEIM is entirely valid and that the PEI phase
can determine which is valid.
I-9.1.2.4 Access to the Boot Firmware Volume in IA-32Intel Architecture
In IA-32 Intel architecture, the Security (SEC) file is at the top of the Boot Firmware Volume (BFV). This SEC file
will have the 16-byte entry point for IA-32 and restarts at address 0xFFFFFFF0.
I-9.1.2.5 Access to the Boot Firmware Volume in ItaniumProcessor Family
IntheItaniumprocessorfamily,themicrocodestartsuptheProcessorAbstractionLayerA(PAL-A)code,whichisthe
firstlayerofPALcodeandisprovidedbytheprocessorvendor,thatresidesintheBootFirmwareVolume(BFV).This
codeminimallyinitializestheprocessorandthenfindsandauthenticatesthesecondlayerofPALcode,calledPAL-B.
The location of both PAL-A and PAL-B can be found by consulting either of the following:
•The architected pointers in the ROM (near the 4 GiB region)
•The Firmware Interface Table (FIT) pointer in the ROM
The PAL layer communicates with the OEM boot firmware using a single entry point called the System Abstrac-
tion Layer entry point (SALE_ENTRY). The PEI Foundation will be located at the SALE_ENTRY point on the boot
firmware device for an Itanium-based system. The Itanium processor family PEIMs, like other PEIMs, may reside in
the BFV or other firmware volumes. A “special” PEIM must be resident in the BFV to provide information about the
location of the other firmware volumes; this will be described in the context of the EFI_PEI_FIND_FV_PPI descrip-
tion. It must also be noted that in an Itanium-based system, all the processors in each node start up and execute the

I-9.1. Introduction I-46UEFI Platform Initialization Specification, Release 1.8
PAL code and subsequently enter the PEI Foundation. The BFV of a particular node must be accessible by all the
processors running in that node. This also means that some of the PEIMs in the Itanium ®architecture boot path will
be multiprocessor (MP) aware.
In an Itanium-based system, it is also imperative that the organization of firmware modules in the BFV must be such
that at least the PAL-A is contained in the fault-tolerant regions. This processor-specific PAL-A code authenticates
the PAL-B code, which is usually contained in the non-fault-tolerant regions of the firmware system. The PAL-A and
PAL-Bbinarycomponentsarealwaysvisibletoalltheprocessorsinanodeatthetimeofpower-on;thesystemfabric
should not need to be initialized.
I-9.2 PEI Foundation Entry Point
I-9.2.1 PEI Foundation Entry Point
The Security (SEC) phase calls the entry point to the PEI Foundation with the following information:
•A set of PPIs
•Size and location of the Boot Firmware Volume (BFV)
•Size and location of other boot-critical FVs, by adding the firmware volume into the PpiList with
EFI_PEI_FIRMWARE_VOLUME_PPI type.
•Size and location of the temporary RAM
•Size and location of the temporary RAM available for use by the PEI Foundation
•Size and location of the stack
The entry point is described in “Code Definitions” below.
Prototype
typedef
VOID
EFIAPI
(*EFI_PEI_CORE_ENTRY_POINT)(
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
);
SecCoreData
Points to a data structure containing information about the PEI core’s operating environment, such as the size
and location of temporary RAM, the stack location and the BFV location. The type EFI_SEC_PEI_HAND_OFF
is defined in “Related Definitions” below.
PpiList
Points to a list of one or more PPI descriptors. These PPI descriptors can be a combina-
tion of descriptors of type EFI_PEI_PPI_DESCRIPTOR for PPIs to be installed initially by the PEI
core and descriptors of type EFI_PEI_NOTIFY_DESCRIPTOR for notifications in which the PEI Core
will notify when the PPI service is installed. An empty PPI list consists of a single descriptor
with the end-tag EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST . TypesEFI_PEI_PPI_DESCRIPTOR and
EFI_PEI_NOTIFY_DESCRIPTOR are defined in “PEIM Descriptors.” As part of its initialization phase, the PEI
FoundationwilladdtheseSEC-hostedPPIstoitsPPIdatabase,suchthatboththePEIFoundationandanymod-
ules can leverage the associated service calls and/or code in these early PPIs. This should contain all the boot
criticalFVsthatwouldbepassedfromSECtoPEIFoundationthoroughthe EFI_PEI_FIRMWARE_VOLUME_PPI .
I-9.2. PEI Foundation Entry Point I-47UEFI Platform Initialization Specification, Release 1.8
ThisfunctionistheentrypointforthePEIFoundation,whichallowstheSECphasetopassinformationaboutthestack,
temporary RAM and the Boot Firmware Volume. In addition, it also allows the SEC phase to pass services and data
forwardforuseduringthePEIphaseintheformofoneormorePPIs. ThesePPI’swillbeinstalledand/orimmediately
signaled if they are notification type.
There is no limit to the number of additional PPIs that can be passed from SEC into the PEI Foundation. As part of
its initialization phase, the PEI Foundation will add these SEC-hosted PPIs to its PPI database such that both the PEI
Foundation and any modules can leverage the associated service calls and/or code in these early PPIs.
Finally,laterphasesofplatformevolutionmightneedmanyofthefeaturesanddatathattheSECphasemightpossibly
have. To support this, the SEC phase can construct a EFI_PEI_PPI_DESCRIPTOR and pass its address into the PEI
Foundation as the final argument.
Among these PPIs, the SEC can pass an optional PPI, EFI_SEC_PLATFORM_INFORMATION_PPI , as part of the PPI
list that is passed to the PEI Foundation entry point. This PPI abstracts platform-specific information that the PEI
FoundationneedstodiscoverwheretobegindispatchingPEIMs. OtherpossiblevaluestopassintothePEIFoundation
would include any security or verification services, such as the Trusted Computing Group (TCG) access services,
because the SEC would constitute the Core Root-of-Trust Module (CRTM) in a TCG-conformant system.
Further,SECcanpassthe EFI_SEC_HOB_DATA_PPI asapartofthePPIlist. ThisPPIcanretrievezeroormoreHOBs
to be added to the HOB list before any PEIMs are dispatched.
typedef struct _EFI_SEC_PEI_HAND_OFF {
UINT16 DataSize;
VOID *BootFirmwareVolumeBase;
UINTN BootFirmwareVolumeSize;
VOID *TemporaryRamBase;
UINTN TemporaryRamSize;
VOID *PeiTemporaryRamBase;
UINTN PeiTemporaryRamSize;
VOID *StackBase;
UINTN StackSize;
} EFI_SEC_PEI_HAND_OFF;
DataSize
Size of the data structure.
BootFirmwareVolumeBase
Points to the first byte of the boot firmware volume, which the PEI Dispatcher should search for PEI modules.
BootFirmwareVolumeSize
Size of the boot firmware volume, in bytes.
TemporaryRamBase
Points to the first byte of the temporary RAM.
TemporaryRamSize
Size of the temporary RAM, in bytes.
PeiTemporaryRamBase
Points to the first byte of the temporary RAM available for use by the PEI Foundation. The area described
byPeiTemporaryRamBase andPeiTemporaryRamSize mustnotextendoutsidebeyondtheareadescribedby
TemporaryRamBase &TemporaryRamSize . Thisareashouldnotoverlapwiththeareareportedby StackBase
andStackSize .
I-9.2. PEI Foundation Entry Point I-48UEFI Platform Initialization Specification, Release 1.8
PeiTemporaryRamSize
Size of the available temporary RAM available for use by the PEI Foundation, in bytes.
StackBase
Points to the first byte of the stack. This are may be part of the memory described by TemporaryRamBase and
TemporaryRamSize or may be an entirely separate area.
StackSize
Size of the stack, in bytes.
The information from SEC is mandatory information that is placed on the stack by the SEC phase to invoke the PEI
Foundation.
TheSECphaseprovidestherequiredprocessorand/orplatforminitializationsuchthatthereisatemporaryRAMregion
available to the PEI phase. This temporary RAM could be a particular configuration of the processor cache, SRAM,
or other source. What is important with respect to this handoff is that the PEI ascertain the available amount of cache
as RAM from this data structure.
Similarly, the PEI Foundation needs to receive a priori information about where to commence the dispatch of PEIMs.
A platform can have various size BFVs. As such, the BootFirmwareVolume value tells the PEI Foundation where it
canexpecttodiscoverafirmwarevolumeheaderdatastructure,anditisthisfirmwarevolumethatcontainsthePEIMs
necessary to perform the basic system initialization.
I-9.3 PEI Calling Convention Processor Binding
Unless otherwise specified, the calling convention used for PEI functions is the same as the one specified in the UEFI
specification. However,forcertainprocessors,analternatecallingconventionisrecommendedfornewPPIdefinitions.
I-9.4 PEI Services Table Retrieval
This section describes processor-specific mechanisms for retrieving a pointer to a pointer to the PEI Services Table (
EFI_PEI_SERVICES** )suchasiscommonlyusedinPEIMs. Themeansofstorageandretrievalareprocessorspecific.
I-9.4.1 X86
ForX86processors,the EFI_PEI_SERVICES** isstoredinthe4bytesimmediatelyprecedingtheInterruptDescriptor
Table. The EFI_PEI_SERVICES** can be retrieved with the following code fragment, which should be placed in a
library routine for portability between architectures:
IDTR32 STRUCT
Limit DW 1 DUP (?)
BaseAddress DD 1 DUP (?)
IDTR32 ENDS
sub esp, SIZEOF IDTR32
sidt FWORD PTR ss:[esp]
mov eax, [esp].IDTR32.BaseAddress
mov eax, DWORD PTR [eax - 4]
add esp, SIZEOF IDTR32
I-9.3. PEI Calling Convention Processor Binding I-49UEFI Platform Initialization Specification, Release 1.8
I-9.4.1.1 Interrupt Descriptor Table Initialization andOwnership Rules.
1. The SEC Core must initialize the IDT using the lidt command and ensure that the four-bytes field immediately
preceding the IDT base address resides within temporary memory.
2. The PEI Foundation initializes or updates the four-byte field immediately preceding the currently loaded IDT
base address.
3. Any PEIM can reinitialize the IDT with the following restrictions:
•The four-bytes field immediately prior to new IDT base address must reside within the temporary or permanent
memory.
•Thefour-bytefieldimmediatelyprecedingtheoldIDTbaseaddressmustbecopiedtothefour-bytefieldimme-
diately preceding the new IDT base address.
I-9.4.2 x64
Forx64processors,the EFI_PEI_SERVICES** isstoredineightbytesimmediatelyprecedingtheInterruptDescriptor
Table
TheEFI_PEI_SERVICES** can be retrieved with the following code fragment, which should be placed in a library
routine for portability between architectures:
IDTR64 STRUCT
BaseAddress DQ 1 DUP (?)
IDTR64 ENDS
sub rsp, SIZEOF IDTR64
sidt [rsp]
mov rax, [rsp].IDTR64.BaseAddress
mov rax, QWORD PTR [rax - 8]
add rsp, SIZEOF IDTR64

memory.
Table
sidt [rsp]
I-9.4.2.1 Interrupt Descriptor Table Initialization andOwnership Rules.
1. TheSECCoremustinitializetheIDTusingthelidtcommandandensurethattheeight-bytesfieldimmediately
2. ThePEIinitializesorupdatestheeight-bytefieldimmediatelyprecedingthecurrentlyloadedIDTbaseaddress.
•Theeight-bytesfieldimmediatelypriortonewIDTbaseaddressmustresidewithinthetemporaryorpermanent
memory
•The eight-byte field immediately preceding the old IDT base address must be copied to the eight-byte field
immediately preceding the new IDT base address.
I-9.4. PEI Services Table Retrieval I-50UEFI Platform Initialization Specification, Release 1.8
I-9.4.3 Itanium Processor Family - Register Mechanism
ForItaniumProcessorFamilyprocessors,the EFI_PEI_SERVICES **isstoredinkernelregister7(ar.kr7). Information
on the kernel registers for IPF can be found at http://www.intel.com/design/itanium/downloads/245358.htm..
TheEFI_PEI_SERVICES **canberetrievedwiththefollowingcodefragment,whichmaybeplacedinalibraryroutine
for portability between architectures:
AsmReadKr7
mov r8, ar.kr7;;
br.ret b0;;
EFI_PEI_SERVICES **
GetPeiServicesTablePointer (
VOID
)
{
return(EFI_PEI_SERVICES **)(UINTN)AsmReadKr7 ();
}
Note:Compilers should not be using KRs, they are reserved for OS use (i.e.,this is the overlap w/ the Software De-
velopment Manual). Also, priv. level 3 code can only read KRs and not write them anyway, only PL0 code can write
these.
I-9.4.4 ARM Processor Family - Register Mechanism
FortheARMProcessorFamilyprocessors,the EFI_PEI_SERVICES **isstoredinatheTPIDRURWread/writeSoft-
ware Thread ID register defined in the ARMv7-A Architectural Reference Manual .
CpuReadTPIDRURW:
MRC p15, 0, r0, c13, c0, 2
bx lr
EFI_PEI_SERVICES \*\*
VOID
)
{
return(EFI_PEI_SERVICES \**)(UINTN)CpuReadTPIDRURW ();
}
I-9.4.4.1 ARM Vector Table
For ARM processors the vector table entries are instructions, and thus are limited to 24-bit relative offset of a branch
instruction. The PI specification requires that the 8 defined vectors contain the following instruction LDR pc, [pc,
#0x20]. This means the 32-bit address of the handler is contained at a 32-byte offset from the address of the vector.
WhenPIcodehooksintothevectortableitmustensurethatthe32-bitabsoluteaddressoffset32-bytesfromthevector
iswhatisupdated. Thefirstcodeintheplatformthatinitializesthevectortablemustfillitwith8LDRpc,[pc,#0x20]
instructions.
I-9.4. PEI Services Table Retrieval I-51UEFI Platform Initialization Specification, Release 1.8
I-9.4.5 AArch64 Processor Family - Register Mechanism
ForAArch64architectureprocessors,the EFI_PEI_SERVICES **isstoredintheTPIDR_EL0register. Informationon
this register can be found in the “ ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile ”.
I-9.4.6 RISC-V Processor Family - Register Mechanism
For the RISC-V processor, the EFI_PEI_SERVICES ** is stored in the RISCV_MACHINE_MODE_CONTEXT struc-
ture and the pointer to this structure is stored in the Machine mode Control and Status register MSCRATCH .
EFI_PEI_SERVICES **isoneofthestructurememberin RISCV_MACHINE_MODE_CONTEXT .Thecontentsinthisstruc-
ture will be kept across all UEFI execution phases during the entire system life. MSCRATCH is a readable and writable
CSR which is initiated to maintain various pointers for each UEFI execution phase. The pointers in this structure
includesEFI_PEI_SERVICES ** and the interrupt handlers of each RISC-V privilege level.
/// Machine mode context used forsaving hart-local context.
typedef struct \_RISCV_MACHINE_MODE_CONTEXT {
EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap
/// handler.
EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap
EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap
EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// User mode trap handler.
TRAP_HANDLER_CONTEXT MModeHandler; /// Handler formachine
/// mode.
} RISCV_MACHINE_MODE_CONTEXT;
EFI_PEI_SERVICES ** can be retrieved through below function
which isprovided by RISC-V library.
CONST EFI_PEI_SERVICES **
EFIAPI
VOID
)
{
RISCV_MACHINE_MODE_CONTEXT *Context;
EFI_PEI_SERVICES **PeiServices;
Context = (RISCV_MACHINE_MODE_CONTEXT *) UINTN)
RiscVGetScratch ();
PeiServices = (EFI_PEI_SERVICES **) Context->PeiService;
return(CONST EFI_PEI_SERVICES **)PeiServices;
}
I-9.4. PEI Services Table Retrieval I-52UEFI Platform Initialization Specification, Release 1.8
I-9.5 PEI Dispatcher Introduction
ThePEIDispatcher’sjobistohandcontroltothePEIMsinanorderlymanner. ThePEIDispatcherconsistsofasingle
phase. ItisduringthisphasethatthePEIFoundationwillexamineeachfileinthefirmwarevolumesthatcontainfiles
of typeEFI_FV_FILETYPE_PEIM orEFI_FV_FILETYPE_COMBINED_PEIM_DRIVER (see thePlatform Initialization
Specification ,Volume3,forfiletypedefinitions). Itwillexaminethedependencyexpression(depex)andtheoptional
a priori file within each firmware file to decide when a PEIM is eligible to be dispatched. The binary encoding of the
depex will be the same as that of a depex associated with a PEIM.
I-9.6 Ordering
I-9.6.1 Requirements
Except for the order imposed by an a priori file, it is not reasonable to expect PEIMs to be executed in any order. A
chipsetinitializationPEIMusuallyrequiresprocessorinitializationandamemoryinitializationPEIMusuallyrequires
chipsetinitialization. Ontheotherhand,thePEIMsthatsatisfytheserequirementsmighthavebeenauthoredbydiffer-
ent organizations and might reside in different FVs. The requirement is thus to, without memory, create a mechanism
to allow for the definition of ordering among the different PEIMs so that, by the time a PEIM executes, all of the
requirements for it to execute have been met.
Although the update and build processes assist in resolving ordering issues, they cannot be relied upon completely.
Considerasystemwitharemovableprocessorcardcontainingaprocessorandfirmwarevolumethatplugsintoamain
systemboard. Iftheprocessorcardisupgraded,itisentirelyreasonablethattheusershouldexpectthesystemtowork
even though no update program was executed.
I-9.6.2 Requirement Representation and Notation
RequirementsarerepresentedbyGUIDs,witheachGUIDrepresentingaparticularrequirement. Therequirementsare
represented by two sets of data structures:
•The dependency expression (depex) of a given PEIM
•The installed set of PPIs maintained by the PEI Foundation in the PPI database
Thismechanismprovidesfora“weakordering”amongPEIMs. IfPEIMsAandBconsumeX(writtenAcXandBcX),
once a PEIM (C) that produces X (CpX) is executed, A and B can be executed. There is no definition about the order
in which A and B are executed.
I-9.6.3 PEI a priori File Overview
The PEI a priori file is a special file that may optionally be present in a firmware volume, and its main purpose is to
provideagreaterdegreeofflexibilityinthefirmwaredesignofaplatform. Specifically,theapriorifilecomplementsthe
dependencyexpressionmechanismofPEIbystipulatingaseriesofmoduleswhichneedbedispatchedinaprescribed
order.
There may be at most one PEI a priori file per firmware volume present in a platform. The a priori file has a known
GUIDfilename PEI_APRIORI_FILE_NAME_GUID ,enablingthePEIFoundationdispatchbehaviortofindtheapriori
file if it is present. The contents of the file shall contain data of the format PEI_APRIORI_FILE_CONTENTS , with
possiblyzeroentries. EverytimethePEIDispatcherdiscoversafirmwarevolume,itfirstlooksfortheapriorifile. The
PEIM’s enumerated in a an a priori file must exist in the same firmware volume as the a priori file iteself; no cross-
volumemappingisallowed. ThePEIFoundationwillinvokethePEIM’slistedinthe PEI_APRIORI_FILE_CONTENTS
in the order found in this file.
I-9.5. PEI Dispatcher Introduction I-53UEFI Platform Initialization Specification, Release 1.8
Without the a priori file, PEIMs executed solely because of their dependency expressions are weakly ordered. This
means that the execution order is not completely deterministic between boots or between platforms. In some cases a
deterministicexecutionorderisrequired. ThePEIapriorifileprovidesadeterministicexecutionorderofPEIMsusing
the following two implementation methods.
The a priori model must be supported by all PEI Foundation implementations, but it does not preclude additional a
priori dispatch methodologies, as long as the latter models use a different mechanism and/or file name GUID for the
alternate a priori module listing. The a priori file format follows below.
I-9.6.3.1 PEI_APRIORI_FILE_NAME_GUID
Summary
The GUID PEI_APRIORI_FILE_NAME_GUID definition is the file name of the PEI a priori file that is stored in a
firmware volume.
GUID

Summary
GUID
#define PEI_APRIORI_FILE_NAME_GUID \
{0x1b45cc0a,0x156a,0x428a,0xaf62,0x49,0x86,\
0x4d,0xa0,0xe6,0xe6}
EFI_GUID FileNamesWithinVolume[NumberOfModulesInVolume];
// Optional list of file-names
} PEI_APRIORI_FILE_CONTENTS;
FileNamesWithinVolume[]
AnarrayofzeroormoreEFI_GUIDtypeentriesthatmatchthefilenamesofPEIMmodulesinthesameFirmware
Volume. The maximum number of entries NumberOfModulesInVolume is determined by the number of mod-
ules in the FV.
Thisfilemustbeoftype EFI_FV_FILETYPE_FREEFORM andmustcontainasinglesectionoftype EFI_SECTION_RAW
. For details on firmware volumes, firmware file types, and firmware file section types, see the Platform Initialization
Specification , Volume 3.
I-9.6.3.2 Dispatch Behavior
TheapriorifilecancontainalistoftheEFI_GUIDs,whicharethenamesofthePEIMfileswithinthesamefirmware
volume. Herein, the PEI Foundation dispatch logic reads the list of names from the a priori file and invokes the
appropriately named module in the order enumerated in the a priori file. This value can be calculated by means of the
size ofPEI_APRIORI_FILE_CONTENTS . This shall be an integral number of GUID sizes.
Ifthereisafilenamewithin PEI_APRIORI_FILE_CONTENTS whichisinthedeletedstateordoesnotexist,thespecific
file name shall be ignored by the PEI Foundation dispatch logic and the successive entry invoked.
During dispatch of PEIM’s in the a priori file, any PEIMs in newly published firmware volumes will be ignored until
completionoftheapriorifiledispatch. Theseinterfaceswouldbeassessedduringsubsequentmoduledispatch,though.
Inadditiontoignoringanyadditionalvolumespublishedduringaprioridispatch,anydependencyexpressionsassoci-
ated with PEIMs listed within PEI_APRIORI_FILE_CONTENTS are ignored.
I-9.6. Ordering I-54UEFI Platform Initialization Specification, Release 1.8
During dispatch of the a priori PEIM list, the PEI Dispatcher shall invoke the EFI_PEI_SECURITY2_PPI
AuthenticationState service, if it exists, to qualify the dispatch of each module. This is the same be-
havior as the normal dependency-based dispatch. For the a priori file in the boot firmware volume, for ex-
ample, the EFI_PEI_SECURITY2_PPI could be passed by the SEC into the PEI Foundation via the optional
EFI_PEI_PPI_DESCRIPTOR list. This latter scenario allows authentication of PEIMs in the a priori file.
AfterexecutingallofthePEIMsspecifiedintheapriorifile,thePEIDispatchersearchesthefirmwarevolumeforany
additional PEIMs and executes them according to their dependency expressions.
I-9.6.4 Firmware Volume Image Files
For PEI, while processing a firmware volume, if a file of type EFI_FV_FIRMWARE_VOLUME_IMAGE is found, the PEI
Dispatcherwillcheckwhetherthisfirmwarevolumeimagefilewasalreadyprocessed. Ifitwas,thenthefileisignored.
Otherwise,thePEIDispatcherwillsearchthefileforasectionwiththetype EFI_SECTION_PEI_DEPEX ,andiffound,
evaluate the expression against the presently installed entries in the PPI database. If the file has a dependency ex-
pression that evaluates to TRUE (or no EFI_SECTION_PEI_DEPEX section), then the PEI Dispatcher will search the
file for a section with the type EFI_SECTION_FIRMWARE_VOLUME_IMAGE , copy its contents into memory, and install
theEFI_PEI_FIRMWARE_VOLUME_INFO_PPI andEFI_PEI_FIRMWARE_VOLUME_INFO2_PPI forthefirmwarevolume
image,andaddHOBsoftype EFI_HOB_FIRMWARE_VOLUME andEFI_HOB_FIRMWARE_VOLUME2 tothehoblistforthe
firmware volume image.
I-9.6.5 PEIM Dependency Expressions
The sequencing of PEIMs is determined by evaluating a dependency expression associated with each PEIM. This
expression describes the requirements necessary for that PEIM to run, which imposes a weak ordering on the PEIMs.
Within this weak ordering, the PEIMs may be initialized in any order.
I-9.6.6 Types of Dependencies
Thebaseunitofthedependencyexpressionisadependency. Arepresentativesyntax(usedinthisdocumentfordescrip-
tive purposes) for each dependency is shown in the following section. The syntax is case-insensitive and mnemonics
are used in place of non-human-readable data such as GUIDs. White space is optional.
The operands are GUIDs of PPIs. The operand becomes “true” when a PPI with the GUID is registered.
I-9.7 Dependency Expressions
I-9.7.1 Introduction
APEIMisstoredinafirmwarevolumeasafilewithoneormoresections. OneofthesectionsmustbeaPE32+image.
If a PEIM has a dependency expression, then it is stored in a dependency section. A PEIM may contain additional
sections for compression and security wrappers. The PEI Dispatcher can identify the PEIMs by their file type. In
addition, the PEI Dispatcher can look up the dependency expression for a PEIM by looking for a dependency section
in a PEIM file. The dependency section contains a section header followed by the actual dependency expression that
is composed of a packed byte stream of opcodes and operands.
Dependency expressions stored in dependency sections are designed to meet the following goals:
•Be small to conserve space.
•Be simple and quick to evaluate to reduce execution overhead.
I-9.7. Dependency Expressions I-55UEFI Platform Initialization Specification, Release 1.8
These two goals are met by designing a small, stack-based instruction set to encode the dependency expressions. The
PEIDispatchermustimplementaninterpreterforthisinstructionsettoevaluatedependencyexpressions. Theinstruc-
tion set is defined in the following topics.
SeeDependency Expression Grammar for an example BNF grammar for a dependency expression compiler. There
aremanypossiblemethodsofspecifyingthedependencyexpressionforaPEIM.Thisexamplegrammardemonstrates
one possible design for a tool that can be used to help build PEIM images.
I-9.7.1.1 Dependency Expression Instruction Set
The following topics describe each of the dependency expression (depex) opcodes in detail. Information includes a
descriptionoftheinstructionfunctionality,binaryencoding,andanylimitationsoruniquebehaviorsoftheinstruction.
SeveraloftheopcodesrequireaGUIDoperand. TheGUIDoperandisa16-bytevaluethatmatchesthetype EFI_GUID
thatisdescribedinChapter2oftheUEFI2.0specification. TheseGUIDsrepresentPPIsthatareproducedbyPEIMs
andthefilenamesofPEIMsstoredinfirmwarevolumes. Adependencyexpressionisapackedbytestreamofopcodes
and operands. As a result, some of the GUID operands will not be aligned on natural boundaries. Care must be taken
on processor architectures that do allow unaligned accesses.
The dependency expression is stored in a packed byte stream using postfix notation. As a dependency expression is
expression. If a push operation causes a stack overflow, then the entire dependency expression evaluates to FALSE.
If a pop operation causes a stack underflow, then the entire dependency expression evaluates to FALSE. Reasonable
addition, PEIMs that contain dependency expressions should make an effort to keep their dependency expressions as
small as possible to help reduce the size of the PEIM.
Allopcodesare8-bitvalues,andifaninvalidopcodeisencountered,thentheentiredependencyexpressionevaluates
toFALSE.
IfanENDopcodeisnotpresentinadependencyexpression,thentheentiredependencyexpressionevaluatesto FALSE.
The final evaluation of the dependency expression results in either a TRUEorFALSEresult.
Note:The PEI Foundation will only support the evaluation of dependency expressions that are less than or equal to
256 terms.
DependencyExpressionOpcodeSummary isasummaryoftheopcodesthatareusedtobuilddependencyexpressions.
The following sections describe each of these instructions in detail.
Table 9.1: Dependency Expression Opcode Summary
0x02 PUSH <PPI GUID>
0x03 AND
0x04 OR
0x05 NOT
0x06 TRUE
0x07 FALSE
0x08 END
I-9.7. Dependency Expressions I-56UEFI Platform Initialization Specification, Release 1.8
I-9.7.1.1.1 PUSH
Syntax
PUSH <PPI GUID>
Pushes a Boolean value onto the stack. If the GUID is present in the handle database, then a TRUEis pushed onto the
stack. IftheGUIDisnotpresentinthehandledatabase,thena FALSEispushedontothestack. ThetestfortheGUID
in the handle database may be performed with the Boot Service LocatePpi() .
Operation
Status = (*PeiServices)->LocatePpi (PeiServices, GUID, 0, NULL, &Interface);
PUSH FALSE;
} Else {
PUSH TRUE;
}
The following table defines the PUSHinstruction encoding.
Table 9.2: PUSH Instruction Encoding
0 0x02
1 16 A16byteGUIDthatrepresentsaprotocolthatisproducedbyadifferentPEIM
The format is the same at type EFI_GUID
None.
I-9.7.1.1.2 AND
Syntax
AND

0x03 AND
0x04 OR
0x05 NOT
0x06 TRUE
0x07 FALSE
0x08 END
Syntax
Operation
} Else {
PUSH TRUE;
}
0 0x02
None.
Syntax
AND
PopstwoBooleanoperandsoffthestack,performsaBoolean ANDoperationbetweenthetwooperands,andpushesthe
Operation
AND Instruction Encoding defines the ANDinstruction encoding.
Table 9.3: AND Instruction Encoding
0 0x03
I-9.7. Dependency Expressions I-57UEFI Platform Initialization Specification, Release 1.8
None.
I-9.7.1.1.3 OR
Syntax
OR
Pops two Boolean operands off the stack, performs a Boolean ORoperation between the two operands, and pushes the
Operation
OR Instruction Encoding defines the ORinstruction encoding.
Table 9.4: OR Instruction Encoding
0 0x04
None.
I-9.7.1.1.4 NOT
Syntax
NOT
Pops a Boolean operands off the stack, performs a Boolean NOToperation on the operand, and pushes the result back
Operation
Result <= NOT Operand
NOT Instruction Encoding defines the NOTinstruction encoding.
Table 9.5: NOT Instruction Encoding
0 0x05
I-9.7. Dependency Expressions I-58UEFI Platform Initialization Specification, Release 1.8
None.
I-9.7.1.1.5 TRUE
Syntax
TRUE
Pushes a Boolean TRUEonto the stack.
Operation
PUSH TRUE
TRUE Instruction Encoding defines the TRUEinstruction encoding.
Table 9.6: TRUE Instruction Encoding
0 0x06
None.
I-9.7.1.1.6 FALSE
Syntax
FALSE
Pushes a Boolean FALSEonto the stack.
Operation
PUSH FALSE
FALSE Instruction Encoding defines the FALSEinstruction encoding.
Table 9.7: FALSE Instruction Encoding
0 0x07
None.
I-9.7. Dependency Expressions I-59UEFI Platform Initialization Specification, Release 1.8
I-9.7.1.1.7 END
Syntax
END
Popsthefinalresultofthedependencyexpressionevaluationoffthestackandexitsthedependencyexpressionevaluator.
Operation
POP ResultRETURN Result
END Instruction Encoding defines the ENDinstruction encoding.
Table 9.8: END Instruction Encoding
0 0x08
I-9.7.2 Dependency Expression with No Dependencies
APEIMthatdoesnothaveanydependencieswillhaveadependencyexpressionthatevaluatesto TRUEwithnodepen-
dencies on any PPI GUIDs.
I-9.7.3 Empty Dependency Expressions
If a PEIM file does not contain a dependency section, then the PEIM has an empty dependency expression.
I-9.7.4 Dependency Expression Reverse Polish Notation(RPN)
The actual equations will be presented by the PEIM in a simple-to-evaluate form, namely postfix. The following
is a BNF encoding of this grammar. See Dependency Expression Instruction Set for definitions of the dependency
<statement> ::= <expression> END
<expression> ::= PUSH <guid> |
TRUE |
FALSE |
<expression> NOT |
<expression> <expression> OR |
<expression> <expression> AND
I-9.7. Dependency Expressions I-60UEFI Platform Initialization Specification, Release 1.8
I-9.8 Dispatch Algorithm
I-9.8.1 Overview
I-9.8.1.1 Ordering Algorithm
The dispatch algorithm repeatedly scans through the PEIMs to find those that have not been dispatched. For each
PEIM that is found, it scans through the PPI database of PPIs that have been published, searching for elements in the
yet-to-be-dispatched PEIM’s depex. If all of the elements in the depex are in the PEI Foundation’s PPI database, the
PEIM is dispatched. The phase terminates when all PEIMs are scanned and none dispatched.
Note:The PEIM may be dispatched without a search if its depex is NULL.
I-9.8.1.2 Multiple Firmware Volume Support
In order to expose a new firmware volume, a PEIM should install an instance of
EFI_PEI_FIRMWARE_VOLUME_INFO_PPI containing the firmware volume format GUID, the starting address
and the size of the firmware volume’s window. PEIMs exposing firmware volumes which have a firmware volume
format other than the PI Architecture Firmware Volume format should include the firmware volume format GUID in
their dependency expression.
PEIMsexposingmemory-mappedfirmwarevolumesshouldcreateamemoryresourcedescriptorHOBforthememory
occupied by the firmware volume if it is outside of the PEI memory.
For each new exposed firmware volume, the PEI Foundation will take the following steps:
1. Create a new firmware volume handle. The firmware volume handle may be created by the PEI Foundation or
by the optional EFI_PEI_FIRMWARE_VOLUME_PPI.
2. Create a new firmware volume HOB.
3. If the firmware volume’s format (identified by its GUID) is not supported directly by the PEI Foundation and it
is not supported by any installed EFI_PEI_FIRMWARE_VOLUME_PPI , the firmware volume is skipped.
4. Otherwise, all PEIMs in the firmware volume are scheduled for dispatching.
5. Find the a priori file, if it exists, and dispatch any PEIMs listed in it.
I-9.8.2 Requirements
I-9.8.2.1 Requirements of a Dispatching Algorithm
The dispatching algorithm must meet the following requirements:
1. Preserve the dispatch weak ordering.
2. Prevent an infinite loop.
3. Control processor resources.
4. Preserve proper dispatch order.
5. Make use of available memory.
6. Invoke each PEIM’s entry point.
7. Know when the PEI Dispatcher tasks are finished.
I-9.8. Dispatch Algorithm I-61UEFI Platform Initialization Specification, Release 1.8
I-9.8.2.2 Preserving Weak Ordering
The algorithm must preserve the weak ordering implied by the depex.
I-9.8.2.3 Preventing Infinite Loops
ItisillegalforAcXpY(AconsumesXandproducesY)andBcYpX.Thisisknownasacycleandisunresolvableeven
ifmemoryisavailable. Ataminimum,thedispatchingalgorithmmustnotendupinaninfiniteloopinsuchascenario.
With the algorithm described above, neither PEIM would be executed.
I-9.8.2.4 Controlling Processor Register Resources
The algorithm must require that a minimum of the processor’s register resources be preserved while PEIMs are dis-
patched.
I-9.8.2.5 Preserving Proper Dispatch Order
The algorithm must preserve proper dispatch order in cases such as the following:
AcQpZ BcLpR CpL DcRpQ
TheissuewiththeabovescenarioisthatAandBarenotobviouslyrelateduntilDisprocessed. IfAandBwereinone
firmwarevolumeandCandDwereinanother,theorderingcouldnotberesolveduntilexecution. Theproperdispatch
order in this case is CBDA. The algorithm must resolve this type of case.
I-9.8.2.6 Using Available Memory
The PEI Foundation begins operation using a temporary memory store that contains the initial call stack from the
Security (SEC) phase. The SEC phase must pass the size and location of the stack and the size and location of the
temporary memory store.
The PEI stack will be available for subsequent PEIM invocations, and the PEI heap will be used for PEIM memory
allocations and Hand-Off Block (HOB) creation.
There can be no memory writes to the address space beyond this initial temporary memory until a PEIM registers a
permanent memory range using the PEI Service InstallPeiMemory() . When permanent memory is installed, the
PEI Foundation will copy the call stack that is located in temporary memory into a segment of permanent memory. If
necessary, the size of the call stack can be expanded to support the subsequent transition into DXE.
In addition to the call stack, the PEI Foundation will copy the following from temporary to permanent memory:
•PEI Foundation private data
•PEI Foundation heap
•HOB list
•Installed Firmware Volumes
Any permanent memory consumed in this fashion by the PEI Foundation will be described in a HOB, which the PEI
Foundation will create.
The PEI Foundation will copy any installed firmware volumes from the temporary memory location to a permanent
memorylocationwiththealignmentspecifiedinthefirmwarevolumeheader. AnyuncompressedPE32orTEsections
within PEIMs in these firmware volumes will be fixed up. This ensures any static EFI_PEI_PPI_DESCRIPTOR s or
PPI interface pointers in these PEIMs point to the permanent memory addresses.
I-9.8. Dispatch Algorithm I-62UEFI Platform Initialization Specification, Release 1.8
In addition, if there were any EFI_PEI_PPI_DESCRIPTOR s created in the temporary memory heap or declared stati-
callyinPEIMs,theirrespectivelocationshavebeentranslatedbyanoffsetequaltothedifferencebetweentheoriginal
locationintemporarymemoryandthedestinationlocationinpermanentmemory. Inadditiontothisheapcopy,thePEI
FoundationwilltraversethePEIPPIdatabase. Anyreferencesto EFI_PEI_PPI_DESCRIPTOR sthatareintemporary
memorywillbefixedupbythePEIFoundationtoreflectthelocationofthe EFI_PEI_PPI_DESCRIPTOR sdestination
in permanent memory.
ThePEIFoundationwillinvoketheDXEIPLPPIafterdispatchingallcandidatePEIMs. TheDXEIPLPPImayhave

to allocate additional regions from permanent memory to be able to load and relocate the DXE Foundation from its
firmware store. The DXE IPL PPI will describe these memory allocations in the appropriate HOB such that when
control is passed to DXE, an accurate record of the memory usage will be known to the DXE Foundation.
I-9.8.2.7 Invoking the PEIM’s Entry Point
The entry point of a PEIM uses the calling conventions specified in the UEFI 2.0 specification, which detail how
parameters are passed to a function. After assessing a PEIM’s dependency expression to see if it can be invoked, the
PEIFoundationwillpasscontroltothePEIM’sentrypoint. ThisentrypointisavaluedescribedinthePEIM’simage
header.
ThePEIFoundationwillpassanindirectpointertothePEIServicesTableandthehandleofthefirmwarefilewhenit
invokes the PEIM.
In the entry point of the PEIM, the PEIM has the opportunity do the following:
•Locate other PPIs
•Install PPIs that reference services within the body of this PEIM
•Register for a notification
•Upon return from the PEIM’s entry point, it returns back to the PEI Foundation.
•See the Microsoft Portable Executable and Common Object File Format Specification for information on
PE/COFF images; see TE Image for information on TE images.
I-9.8.2.8 Knowing When Dispatcher Tasks Are Finished
The PEI Dispatcher is finished with a pass when it has finished dispatching all the PEIMs that it can. During a pass,
some PEIMs might not have been dispatched if they had requirements that no other PEIM has met.
However, with the weak ordering defined in previous requirements, system RAM could possibly be initialized before
all PEIMs are given a chance to run. This situation can occur because the system RAM initialization PEIM is not
required to consume all resources provided by all other PEIMs. The PEI Dispatcher must recognize that its tasks are
not complete until all PEIMs have been given an opportunity to run.
I-9.8.2.9 Reporting PEI Core Location
IftheEFI_PEI_LOADED_IMAGE_PPI issupportedbythePEIDispatcher,thenthePEIFoundationmustfirstreportits
ownlocationbyusingthePEIService InstallPpi() andtheEFI_PEI_LOADED_IMAGE_PPI .IftheFileHandle is
unknown, then NULLcan be used. PEI Foundation must also report the location of the PEIM loaded by creating the
EFI_PEI_LOADED_IMAGE_PPI and call the PEI Service ReinstallPpi() .
I-9.8. Dispatch Algorithm I-63UEFI Platform Initialization Specification, Release 1.8
I-9.8.3 Example Dispatch Algorithm
The following pseudo code is an example of an algorithm that uses few registers and implements the requirements
listed in the previous section. The pseudo code uses simple C-like statements but more assembly-like flow-of-control
primitives.
The dispatch algorithm’s main data structure is the DispatchedBitMap as described in Example Dispatch Map .
Table 9.9: Example Dispatch Map
PEIM# Item PEIM# Item
FV0 4 FV1
PEI Foundation <non PEIM>
0 PEIM <non PEIM>
1 PEIM <non PEIM>
2 PEIM with EFI_PEI_FIRMWARE_VOLUME_PPI <non PEIM>
<non PEIM> 6 <non PEIM>
3 PEIM 7 PEIM
Example Dispatch Map is an example of a dispatch in a given set of firmware volumes (FVs). Following are the steps
in this dispatch:
1. The algorithm scans through the PEIMs that it knows about.
2. When it comes to a PEIM that has not been dispatched, it verifies that all of the required PPIs listed in the
dependency expression (depex) are in the PPI database.
3. If all of the GUIDed interfaces listed in the depex are available, the PEIM is invoked.
4. Create the EFI_PEI_LOADED_IMAGE_PPI and call the PEI Service ReinstallPpi()
5. Iterations continue through all known PEIMs in all known FVs until a pass is made with no PEIMs dispatched,
thus signifying completion.
6. After the dispatch completes, the PEI Foundation locates and invokes the GUID for the DXE IPL PPI, passing
in the HOB address and a valid stack. Failing to discover the GUID for the DXE IPL PPI shall be an error.
I-9.8.4 Dispatching When Memory Exists
ThepurposeofthePEIphaseofexecutionistodiscoverandinitializemainmemory. Thereareseveralcircumstances
inwhichtheshadowingofaPEIMandtherelocationofthisimageintomemoryareofinterest. Thiscanincludebutis
not limited to compressing PEIMs, such as the DXE IPL PPI, those modules that are required for crisis recovery, and
platforms in which code is executed from temporary memory.
The PEI architecture shall not dictate what compression mechanism is to be used, but there will be a Decompress
service that is published by some PEIM that the PEI Foundation will discover and use when it becomes available. In
addition, loading images also requires a full image-relocation service and the ability to flush the cache. The former
will allow the PEIM that was relocated into RAM to have its relocations adjust pursuant to the new load address. The
latterservicewillbeinvokedbythePEIFoundationsothatthisrelocatedcodecanberun,especiallyonItanium-based
platforms that do not have a coherent data and code cache.
A compressed section shall have an implied dependency on permanent memory having been installed. To speed up
boot time, however, there can be an explicit annotation of this dependency.
I-9.8. Dispatch Algorithm I-64UEFI Platform Initialization Specification, Release 1.8
I-9.8.5 PEIM Dispatching
When the PEI Dispatcher has decided to invoke a PEIM, the following steps are taken:
1. If any instances of EFI_PEI_LOAD_FILE_PPI are installed, they are called, one at a time, until one reports
2. Ifnoinstancereports EFI_SUCCESS ortherearenoinstancesinstalled,thenthebuilt-insupportfor(atleast)the
PE32+/TE XIP image formats is used.
3. Ifanyinstancesof EFI_PEI_SECURITY2_PPI areinstalled,theyarecalled,oneatatime,aslongasnonereturns
anEFI_SECURITY_VIOLATION error. If such an error is returned, then the PEIM is marked as dispatched, but
is never invoked.
4. The PEIM’s entry point is invoked with the file’s handle and the PEI Services Table pointer.
5. The PEIM is marked as dispatched.
ThePEICoremaydecide,becauseofmemoryconstraintsorperformancereasons,todispatchXIPinsteadofshadowing
into memory.
I-9.8.6 PEIM Authentication
The PEI specification provides three methods which the PEI Foundation can use to authenticate a PEIM:
1. The authentication information could be encoded as part of a GUIDed section. In this case, the provider of the
EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI (see thePlatform Initialization Specification , Volume 3) can
check the authentication data and return the results in AttestationState .
2. The authentication information can be checked by the provider of the EFI_PEI_LOAD_FILE_PPI (see thePlat-
form Initialization Specification , Volume 3) and the results returned in AttestationState .
3. The PEI Foundation may implement the digital signing as described in the UEFI 2.0 specification.
In all cases, the result of the authentication must be passed to any instances of the EFI_PEI_SECURITY2_PPI .
I-9.8. Dispatch Algorithm I-65CHAPTER
TEN
ARCHITECTURAL PPIS
I-10.1 Introduction
ThePEIFoundationandPEIDispatcherrelyonthefollowingPEIM-to-PEIMInterfaces(PPIs)toperformitswork. The
abstraction provided by these interfaces allows dispatcher algorithms to be improved over time or have some platform
variability without affecting the rest of PEI.
ThekeytothesePPIsisthattheyarearchitecturallydefinedinterfacesconsumedbythePEIFoundation,buttheymay
not be published by the PEI Foundation.
I-10.2 Required Architectural PPIs
I-10.2.1 Master Boot Mode PPI (Required)
I-10.2.1.1 EFI_PEI_MASTER_BOOT_MODE_PPI (Required)
Summary
The Master Boot Mode PPI is installed by a PEIM to signal that a final boot has been determined and set. This signal
is useful in that PEIMs with boot-mode-specific behavior (for example, S3 versus normal) can put this PPI in their
dependency expression.
GUID
#define EFI_PEI_MASTER_BOOT_MODE_PEIM_PPI \
{0x7408d748, 0xfc8c, 0x4ee6, 0x92, 0x88, 0xc4, 0xbe, \
0xc0, 0x92, 0xa4, 0x10}
PPI Interface Structure
None.
TheMasterBootModePPIisaPPIGUIDandmustbeinthedependencyexpressionofeveryPEIMthatmodifiesthe
basic hardware. The dispatch, or entry point, of the module that installs the Master Boot Mode PPI modifies the boot
path value in the following ways:
•Directly, through the PEI Service SetBootMode()
•Indirectly through its optional subordinate boot path modules
I-66UEFI Platform Initialization Specification, Release 1.8
The PEIM that publishes the Master Boot Mode PPI has a non-null dependency expression if there are subsidiary
modulesthatpublishalternatebootpathPPIs. TheprimaryreasonforthisPPIistobetherootofdependenciesforany
child boot mode provider PPIs.
None.
I-10.2.2 DXE IPL PPI (Required)
I-10.2.2.1 EFI_DXE_IPL_PPI (Required)
Summary
Final service to be invoked by the PEI Foundation.
GUID
#define EFI_DXE_IPL_PPI_GUID \
{ 0xae8ce5d, 0xe448, 0x4437, 0xa8, 0xd7, 0xeb, 0xf5, \
0xf1, 0x94, 0xf7, 0x31 }
typedef struct _EFI_DXE_IPL_PPI {
EFI_DXE_IPL_ENTRY Entry;
} EFI_DXE_IPL_PPI;
Entry
The entry point to the DXE IPL PPI. See the Entry() function description.

None.
Summary
GUID
Entry
After completing the dispatch of all available PEIMs, the PEI Foundation will invoke this PPI through its entry point
using the same handoff state used to invoke other PEIMs. This special treatment by the PEI Foundation effectively
makes the DXE IPL PPI the last PPI to execute during PEI. When this PPI is invoked, the system state should be as
follows:
•Single thread of execution
•Interrupts disabled
•Processor mode as defined for PEI
TheDXEIPLPPIisresponsibleforlocatingandloadingtheDXEFoundation. TheDXEIPLPPImayusePEIservices
to locate and load the DXE Foundation. As long as the DXE IPL PPI is using PEI Services, it must obey all PEI
interoperability rules of memory allocation, HOB list usage, and PEIM-to-PEIM communication mechanisms.
ForS3resumebootmodesDXEIPLmustbepreparedtoexecutewithoutpermanentmemoryinstalledandinvokethe
S3 resume modules.
I-10.2. Required Architectural PPIs I-67UEFI Platform Initialization Specification, Release 1.8
I-10.2.2.2 EFI_DXE_IPL_PPI.Entry()
Summary
The architectural PPI that the PEI Foundation invokes when there are no additional PEIMs to invoke.
Prototype
typedef
(EFIAPI *EFI_DXE_IPL_ENTRY) (
IN CONST EFI_DXE_IPL_PPI *This,
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_HOB_POINTERS HobList
);
This
Pointer to the DXE IPL PPI instance.
Pointer to the PEI Services Table.
HobList
Pointer to the list of Hand-Off Block (HOB) entries.
//
// Union of all the possible HOB Types
//
EFI_HOB_GENERIC_HEADER *Header;
EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable;
EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore;
EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack;
EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule;
EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
EFI_HOB_GUID_TYPE *Guid;
EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume;
EFI_HOB_CPU *Cpu;
EFI_HOB_MEMORY_POOL *Pool;
UINT8 *Raw;
} EFI_PEI_HOB_POINTERS;
This function is invoked by the PEI Foundation. The PEI Foundation will invoke this service when there are no ad-
ditional PEIMs to invoke in the system. If this PPI does not exist, it is an error condition and an ill-formed firmware
set. TheDXEIPLPPIshouldneverreturnafterhavingbeeninvokedbythePEIFoundation. TheDXEIPLPPIcando
many things internally, including the following:
•Invoke the DXE entry point from a firmware volume.
•Invoke the recovery processing modules.
•Invoke the S3 resume modules.
I-10.2. Required Architectural PPIs I-68UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS UponthisreturncodethePEIFoundationshouldentersomeexcep-
tionhandlingUndernormalcircumstancestheDXEIPLPPIshould
not return
I-10.2.3 Memory Discovered PPI (Required)
I-10.2.3.1 EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI (Required)
Summary
ThisPPIispublishedbythePEIFoundationwhenthemainmemoryisinstalled. ItisessentiallyaPPIwithnoassociated
interface. Its purpose is to be used as a signal for other PEIMs who can register for a notification on its installation.
GUID
#define EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI_GUID \
{0xf894643d, 0xc449, 0x42d1, 0x8e, 0xa8, 0x85, 0xbd, \s
0xd8, 0xc6, 0x5b, 0xde}
None.
ThisPPIisinstalledbythePEIFoundationatthepointofsystemevolutionwhenthepermanentmemorysizehasbeen
registered and waiting PEIMs can use the main memory store. Using this GUID allows PEIMs to do the following:
•Be notified when this PPI is installed.
•Include this PPI’s GUID in the EFI_DEPEX .
The expectation is that a compressed PEIM would depend on this PPI, for example. The PEI Foundation will relocate
the temporary cache to permanent memory prior to this installation.
None.
I-10.3 Optional Architectural PPIs
I-10.3.1 Boot in Recovery Mode PPI (Optional)
I-10.3.1.1 EFI_PEI_BOOT_IN_RECOVERY_MODE_PPI (Optional)
Summary
This PPI is installed by the platform PEIM to designate that a recovery boot is in progress.
GUID
#define EFI_PEI_BOOT_IN_RECOVERY_MODE_PEIM_PPI \
{0x17ee496a, 0xd8e4, 0x4b9a, 0x94, 0xd1, 0xce, 0x82, \
0x72, 0x30, 0x8, 0x50}
I-10.3. Optional Architectural PPIs I-69UEFI Platform Initialization Specification, Release 1.8
None.
This optional PPI is installed by the platform PEIM to designate that a recovery boot is in progress. Its purpose is to
allow certain PEIMs that wish to be dispatched only during a recovery boot to include this PPI in their dependency
expression (depex). Including this PPI in the depex allows the PEI Dispatcher to skip recovery-specific PEIMs during
normal restarts andthus save on boottime. This PEIM has no associatedPPI and is usedonly to designate the system
state as being “in a crisis recovery dispatch.”
None.
I-10.3.2 End of PEI Phase PPI (Optional)
I-10.3.2.1 EFI_PEI_END_OF_PEI_PHASE_PPI (Optional)
Summary
ThisPPIwillbeinstalledattheendofPEIforallbootpaths,includingnormal, recovery,andS3. ItallowsforPEIMs
to possibly quiesce hardware, build handoff information for the next phase of execution, or provide some terminal
processing behavior.
GUID
#define EFI_PEI_END_OF_PEI_PHASE_PPI_GUID \
{0x605EA650, 0xC65C, 0x42e1, 0xBA, 0x80, 0x91, 0xA5, \
0x2A, 0xB6,0x18, 0xC6}
None.
This PPI is installed by the DXE IPL PPI to indicate the end of the PEI usage of memory and ownership of memory
allocation by the DXE phase.
For the BOOT_ON_S3_RESUME boot mode, this PPI is installed by the EFI_PEI_S3_RESUME_PPI.
S3RestoreConfig() (Section 8.6 of the PI1.2 Specification, Volume 5) just before jump to OS waking vector.
Theintendedusemodelisforanyagentthatneedstodocleanup,suchasmemoryservicestoconvertinternalmetadata
for tracking memory allocation into HOBs, to have some distinguished point in which to do so. The PEI Memory
Services would register for a callback on the installation of this PPI.
None.
I-10.3. Optional Architectural PPIs I-70UEFI Platform Initialization Specification, Release 1.8
I-10.3.3 PEI Reset PPI
I-10.3.3.1 EFI_PEI_RESET_PPI (Optional)
Summary
This PPI is installed by some platform- or chipset-specific PEIM that abstracts the Reset Service to other agents.
GUID
#define EFI_PEI_RESET_PPI_GUID \
{0xef398d58, 0x9dfd, 0x4103, 0xbf, 0x94, 0x78, 0xc6, \
0xf4, 0xfe, 0x71, 0x2f}
typedef struct _EFI_PEI_RESET_PPI {
} EFI_PEI_RESET_PPI;
A service to reset the platform. See the ResetSystem() function description in Reset Services .
These services provide a simple reset service. See the ResetSystem() function description for a description of this
service.
I-10.3.4 PEI Reset2 PPI
I-10.3.4.1 EFI_PEI_RESET2_PPI (Optional)
Summary
This PPI is installed by some platform- or chipset-specific PEIM that abstracts the ability to reset the platform.
GUID
#define EFI_PEI_RESET2_PPI_GUID \
{0x6cc45765, 0xcce4, 0x42fd, \
{0xbc, 0x56, 0x1, 0x1a,0xaa, 0xc6, 0xc9, 0xa8}}
typedef struct _EFI_PEI_RESET2_PPI {
EFI_PEI_RESET2_SYSTEM ResetSystem;
A service to reset the platform.
These services provide a simple reset service. This is equivalent to the ResetSystem() API call in the UEFI2.4
specification.
I-10.3. Optional Architectural PPIs I-71UEFI Platform Initialization Specification, Release 1.8
I-10.3.4.2 ResetSystem()
Summary
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_RESET2_SYSTEM) (
);
ResetType
The type of reset to perform. Type EFI_RESET_TYPE is defined in “Related Definitions” below.
ResetStatus
The status code for the reset. If the system reset is part of a normal operation, the status code would be
EFI_SUCCESS .IfthesystemresetisduetosometypeoffailurethemostappropriateEFIStatuscodewouldbe
used.
DataSize
The size, in bytes, of ResetData .
ResetData
ForaResetType ofEfiResetCold ,EfiResetWarm ,orEfiResetShutdown thedatabufferstartswithaNull-
use to further indicate the reason for the system reset. ResetData is only valid if ResetStatus is something
otherthan EFI_SUCCESS unlessthe ResetType isEfiResetPlatformSpecific whereaminimumamountof
ResetData is always required.
// EFI_RESET_TYPE//
EfiResetShutdown,
TheResetSystem() functionresetstheentireplatform,includingallprocessorsanddevices,andrebootsthesystem.
Callingthisinterfacewith ResetType ofEfiResetCold causesasystem-widereset. Thissetsallcircuitrywithinthe

used.
DataSize
ResetData
boundaries. EfiResetCold is tantamount to a system power cycle.
Calling this interface with ResetType ofEfiResetWarm causes a system-wide initialization. The processors are set
I-10.3. Optional Architectural PPIs I-72UEFI Platform Initialization Specification, Release 1.8
EfiResetCold must be performed.
Calling this interface with ResetType ofEfiResetShutdown causes the system to enter a power state equivalent to
theACPIG2/S5orG3states. Ifthesystemdoesnotsupportthisresettype,thenwhenthesystemisrebooted,itshould
exhibit the EfiResetCold attributes.
Calling this interface with ResetType of EfiResetPlatformSpecific causes a system-wide reset. The exact type of
the reset is defined by the EFI_GUID that follows the Null-terminated Unicode string passed into ResetData . If the
platformdoesnotrecognizethe EFI_GUID inResetData theplatformmustpickasupportedresettypetoperform.The
TheResetSystem() function does not return.
I-10.3.5 Status Code PPI (Optional)
I-10.3.5.1 EFI_PEI_PROGRESS_CODE_PPI (Optional)
Summary
ThisserviceispublishedbyaPEIM.Therecanbeonlyoneinstanceofthisserviceinthesystem. Iftherearemultiple
variableaccessservices,thisPEIMmustmultiplexthesealternateaccessorsandprovidethissingle,read-onlyservice
totheotherPEIMsandthePEIFoundation. ThissingletonnatureisimportantbecausethePEIFoundationwillnotify
when this service is installed.
GUID
#define EFI_PEI_REPORT_PROGRESS_CODE_PPI_GUID \
{0x229832d3, 0x7a30, 0x4b36, 0xb8, 0x27, 0xf4, 0xc, \
0xb7, 0xd4, 0x54, 0x36);
typedef struct \_EFI_PEI_PROGRESS_CODE_PPI {
} EFI_PEI_PROGRESS_CODE_PPI;
I-10.3.5.2 ReportStatusCode
Service that allows PEIMs to report status codes.
See theReportStatusCode function description for a description of this service.
I-10.3. Optional Architectural PPIs I-73UEFI Platform Initialization Specification, Release 1.8
I-10.3.6 Security PPI (Optional)
I-10.3.6.1 EFI_PEI_SECURITY2_PPI (Optional)
Summary
This PPI is installed by some platform PEIM that abstracts the security policy to the PEI Foundation, namely the case
of a PEIM’s authentication state being returned during the PEI section extraction process.
GUID
#define EFI_PEI_SECURITY2_PPI_GUID \
{ 0xdcd0be23, 0x9586, 0x40f4, 0xb6, 0x43, 0x6, 0x52, \
0x2c, 0xed, 0x4e, 0xde }
typedef struct _EFI_PEI_SECURITY2_PPI {
EFI_PEI_SECURITY_AUTHENTICATION_STATE AuthenticationState;
} EFI_PEI_SECURITY2_PPI;
Parameter
AuthenticationState
Allowstheplatformbuildertoimplementasecuritypolicyinresponsetovaryingfileauthenticationstates. See
theAuthenticationState() function description.
This PPI is a means by which the platform builder can indicate a response to a PEIM’s authentication state. This
can be in the form of a requirement for the PEI Foundation to skip a module using the DeferExecution Boolean
output in the AuthenticationState() member function. Alternately, the Security PPI can invoke something like
a cryptographic PPI that hashes the PEIM contents to log attestations, for which the FileHandle parameter in
AuthenticationState() will be useful. If this PPI does not exist, PEIMs will be considered trusted.
I-10.3.6.2 EFI_PEI_SECURITY2_PPI.AuthenticationState()
Summary
Allows the platform builder to implement a security policy in response to varying file authentication states.
Prototype
typedef
(EFIAPI *EFI_PEI_SECURITY_AUTHENTICATION_STATE) (
IN CONST EFI_PEI_SECURITY2_PPI *This,
IN UINT32 AuthenticationStatus,
IN EFI_PEI_FV_HANDLE FvHandle,
IN OUT BOOLEAN *DeferExecution
);
An indirect pointer to the PEI Services Table published by the PEI Foundation.
I-10.3. Optional Architectural PPIs I-74UEFI Platform Initialization Specification, Release 1.8
This
Interface pointer that implements the particular EFI_PEI_SECURITY2_PPI instance.
Authentication status of the file.
FvHandle
Handle of the volume in which the file resides. Type EFI_PEI_FV_HANDLE is defined in FfsFindNextVolume
. This allows different policies depending on different firmware volumes.
Handle of the file under review. Type EFI_PEI FILE HANDLE is defined in FfsFindNextFile .
DeferExecution
Pointer to a variable that alerts the PEI Foundation to defer execution of a PEIM.
This service is published by some platform PEIM. The purpose of this service is to expose a given platform’s policy-
based response to the PEI Foundation. For example, if there is a PEIM in a GUIDed encapsulation section and the
extraction of the PEI file section yields an authentication failure, there is no a prioripolicy in the PEI Foundation.
Specifically,thissituationleadstothequestionwhetherPEIMsthatareeithernotinGUIDedsectionsorareinsections
whose authentication fails should still be executed.
Infact,itistheresponsibilityoftheplatformbuildertomakethisdecision. Thisplatform-scopedpolicyisaresultthat
a desktop system might not be able to skip or not execute PEIMs because the skipped PEIM could be the agent that
initializes main memory. Alternately, a system may require that unsigned PEIMs not be executed under any circum-
stances. In either case, the PEI Foundation simply multiplexes access to the Section Extraction PPI and the Security
PPI. The Section Extraction PPI determines the contents of a section, and the Security PPI tells the PEI Foundation
whether or not to invoke the PEIM.
The PEIM that publishes the AuthenticationState() service uses its parameters in the following ways:
•AuthenticationStatus conveys the source information upon which the PEIM acts.
•TheDeferExecution value tells the PEI Foundation whether or not to dispatch the PEIM.
In addition, between receiving the AuthenticationState() from the PEI Foundation and returning with the
DeferExecution value, the PEIM that publishes AuthenticationState() can do the following:
•Log the file state.
•Lock the firmware hubs in response to an unsigned PEIM being discovered.
These latter behaviors are platform- and market-specific and thus outside the scope of the PEI CIS.
EFI_SUCCESS The service performed its action successfully.
EFI_SECURITY_VIOLATION The object cannot be trusted
I-10.3. Optional Architectural PPIs I-75UEFI Platform Initialization Specification, Release 1.8
I-10.3.7 Temporary RAM Support PPI (Optional)
I-10.3.7.1 EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI (Optional)
Summary
This service allows for migrating from some contents of Temporary RAM store, which is instantiated during the SEC
phase, into permanent RAM. The latter store will persist unmodified into the subsequent phase of execution, such as
DXE. This service may be published by the SEC as part of the SEC-to-PEI handoff or published by any other PEIM.
GUID
#define EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI_GUID
{0xdbe23aa9, 0xa345, 0x4b97,0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89}
Prototype
typedef struct _EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI {
TEMPORARY_RAM_MIGRATION TemporaryRamMigration;
} EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI;
TemporaryRamMigration
Perform the migration of contents of Temporary RAM to Permanent RAM. This service may terminate the
TemporaryRAM,forexample,ifitcannotcoexistwiththePermanentRAM.Seethe TemporaryRamMigration() `
This service abstracts the ability to migrate contents of the platform early memory store. This is an optional PPI
that is only required for platforms that may have side effects when both Temporary RAM and Permanent RAM are
enabled. This PPI provides a service that orchestrates the complete transition from Temporary RAM to Permanent
RAMthatavoidssideeffects. Thisincludesthemigrationofalldata, astackswitchaction,andpossiblythedisabling
of Temporary RAM.
If a platform does not have any side effects when both Temporary RAM and Permanent RAM are enabled, and the
platformisrequiredtodisabletheuseofTemporaryRAM,then EFI_PEI_TEMPORARY_RAM_DONE shouldbeproduced.
platform is not required to disable the use of Temporary RAM, then neither EFI_PEI_TEMPORARY_RAM_DONE nor
EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI should be produced.
I-10.3.7.2 EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI.TemporaryRamMigration()
Summary
This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into permanent
memory.
Prototype
typedef
(EFIAPI * TEMPORARY_RAM_MIGRATION) (
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,

Summary
memory.
Prototype
typedef
I-10.3. Optional Architectural PPIs I-76UEFI Platform Initialization Specification, Release 1.8
IN UINTN CopySize
);
TemporaryMemoryBase
Source Address in temporary memory from which the SEC or PEIM will copy the Temporary RAM contents.
PermanentMemoryBase
DestinationAddressinpermanentmemoryintowhichtheSECorPEIMwillcopytheTemporaryRAMcontents.
CopySize
Amount of memory to migrate from temporary to permanent memory.
This service is published by the SEC module or a PEIM. It migrates the Temporary RAM contents into Permanent
RAMRAM and performs all actions required to switch the active stack from Temporary RAM to Permanent RAM.
Theaddressrangefrom PermanentMemoryBase toPermanentMemoryBase +CopySize shouldfixwithintherange
of memory provided to the PEI Foundation as part of the InstallPeiMemory() core services. Also, since the SEC
may have sequestered some of the Temporary RAM for its own data storage and PPI’s, the SEC handoff now in-
cludesaddressesandsizesofboththe“available”( PeiTemporaryRamBase /PeiTemporaryRamSize )and“total”(
TemporaryRamBase /TemporaryRamSize ) Temporary RAM as separate numbers.
PeiTemporaryRamBase is used by the PEI foundation for its resource management; TemporaryRamBase is used by
the foundation as an input to this TemporaryRamMigration() service call. As such, the PEI foundation is the only
agentwhoknowsthefullextentoftheTemporaryRAMstorethatneedsmigrationtoPermanentRAM.Itwillusethis
full extent as the CopySize argument in this PPI invocation. At minimum, the CopySize must include the portion of
the Temporary RAM used by the SEC.
The PEI Foundation implementation will invoke this PPI service TemporaryRamMigration() , if present, after
InstallPeiMemory() isinvoked. EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI isinstalledafterthePPIservice
TemporaryRamMigration() is invoked, providing a signal to PEIMs that permanent memory is available.
IftheEFI_PEI_TEMPORARY_RAM_SUPPORT_PPI serviceisnotavailable,aPEIfoundationimplementationshallcopy
thecontentsoftheTemporaryRAMtoPermanentRAMdirectlyandperformthestackswitchaction. Thelackofthis
PPI is not an error condition.
Thestackswitchaction,namelythebeginningofusageofthepermanentRAMasstackinlieuofthetemporaryRAM
stack,isanintegralcapabilityofanyPEIfoundationimplementationandneednothaveanAPIinthisPPIoranyother
to externally-installed abstraction.
EFI_SUCCESS The data was successfully returned
EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase
when TemporaryMemoryBase > PermanentMemoryBase
I-10.3. Optional Architectural PPIs I-77UEFI Platform Initialization Specification, Release 1.8
I-10.3.8 Temporary RAM Done PPI (Optional)
I-10.3.8.1 EFI_PEI_TEMPORARY_RAM_DONE_PPI (Optional)
Summary
The PPI that provides a service to disable the use of Temporary RAM.
GUID
#define EFI_PEI_TEMPORARY_RAM_DONE_PPI_GUID \
{ 0xceab683c, 0xec56, 0x4a2d, \
{ 0xa9, 0x6, 0x40, 0x53, 0xfa, 0x4e, 0x9c, 0x16 } }
typedef struct _EFI_PEI_TEMPORARY_RAM_DONE_PPI {
EFI_PEI_TEMPORARY_RAM_DONE TemporaryRamDone;
} EFI_PEI_TEMPORARY_RAM_DONE_PPI;
TemporaryRamDone
Disable the use of Temporary RAM.
This is an optional PPI that may be produced by SEC or a PEIM. If present, it provide a service to disable the use of
Temporary RAM. This service may only be called by the PEI Foundation after the transition from Temporary RAM
to Permanent RAM is complete. This PPI provides an alternative to the Temporary RAM Migration PPI for system
architectures that allow Temporary RAM and Permanent RAM to be enabled and accessed at the same time with no
side effects.
I-10.3.8.2 EFI_PEI_TEMPORARY_RAM_DONE_PPI.TemporaryRamDone ()
Summary
Prototype
typedef
(EFIAPI * EFI_PEI_TEMPORARY_RAM_DONE) (
VOID
);
TemporaryRamDone() disablestheuseofTemporaryRAM.Ifpresent,thisserviceisinvokedbythePEIFoundation
after theEFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.
EFI_SUCCESS Use of Temporary RAM was disabled.
EFI_DEVICE_ERROR Temporary RAM could not be disabled.
I-10.3. Optional Architectural PPIs I-78UEFI Platform Initialization Specification, Release 1.8
I-10.3.9 EFI_PEI_CORE_FV_LOCATION_PPI
Summary
Indicates to the PEI Foundation which Firmware Volume contains the PEI Foundation.
GUID
#define EFI_PEI_CORE_FV_LOCATION_GUID \
{0x52888eae, 0x5b10, 0x47d0, \
{0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4}}
Prototype
VOID *PeiCoreFvLocation;
} EFI_PEI_CORE_FV_LOCATION_PPI;
PeiCoreFVLocation
Points to the first byte of the firmware volume which contains the PEI Foundation.
PISpecification1.6 andearlierversionsrequiredthatthePEIFoundationresideintheBootFirmwareVolume(BFV).
ThisallowedthePEIFoundationtoassumethatitcanlocateitselfwithintheBFV.Thisassumptionisnolongervalid.
AsthePISpecificationnolongerdefinesamechanismforthePEIFoundationtolocateitself,anewmethodisneeded.
Specifically,thePEICorecanusethe EFI_PEI_CORE_FV_LOCATION_PPI toascertainitscontainingfirmwarevolume
location.
Specifically, if the PEI Foundation does not reside in the BFV, then SEC must pass the
EFI_PEI_CORE_FV_LOCATION_PPI as a part of the PPI list provided to the PEI Foundation Entry Point. If
this PPI is not present in the PPI list, the PEI Foundation shall assume that it resides within the BFV.
ThePEIFoundationwillusethe EFI_PEI_CORE_FV_LOCATION_PPI forpurposesofmoduledispatchifitexists. Ifit
does not exist, the BootFirmwareVolume base inEFI_SEC_PEI_HAND_OFF will be used.
I-10.3. Optional Architectural PPIs I-79CHAPTER
ELEVEN
PEIMS
I-11.1 Introduction
A Pre-EFI Initialization Module (PEIM) represents a unit of code and/or data. It abstracts domain-specific logic and
is analogous to a DXE driver. As such, a given group of PEIMs for a platform deployment might include a set of the
•Platform-specific PEIMs
•Processor-specific PEIMs
•Chipset-specific PEIMs
•PEI CIS-prescribed architectural PEIMs
•Miscellaneous PEIMs
ThePEIMencapsulationallowsforaplatformbuildertouseservicesforagivenhardwaretechnologywithouthaving
to build the source of this technology or necessarily understand its implementation. A PEIM-to-PEIM Interface (PPI)
is the means by which to abstract hardware-specific complexities to a platform builder’s PEIM. As such, PEIMs can
work in concert with other PEIMs using PPIs.
In addition, PEIMs can ascertain a fixed set of services that are always available through the PEI Services Table.
Finally, because the PEIM represents the basic unit of execution beyond the Security (SEC) phase and the PEI Foun-
dation, there will always be some non-zero-sized collection of PEIMs in a platform.
I-11.2 PEIM Structure
I-11.2.1 PEIM Structure Overview
Each PEI Module (PEIM) is stored in a file. It consists of the following:
•Standard header
•Execute-in-place code/data section
•Optional relocation information
•Authentication information, if present
ThePEIMbinaryimagecanbeexecutedinplacefromitslocationinthefirmwarevolume(FV)orfromacompressed
componentthatwillbeshadowedafterpermanentmemoryhasbeeninstalled. TheexecutablesectionofthePEIMmay
beeitherposition-dependentorposition-independentcode. IftheexecutablesectionofthePEIMisposition-dependent
code, relocation information must be provided in the PEIM image to allow FV store software to relocate the image to
a different location than it is compiled.
I-80UEFI Platform Initialization Specification, Release 1.8
Typical PEIM Layout in a Firmware File depicts the typical layout of a PEIM.
Fig. 11.1: Typical PEIM Layout in a Firmware File
I-11.2.2 Relocation Information
I-11.2.2.1 Position-Dependent Code
PEIMsthataredevelopedusingposition-dependentcoderequirerelocationinformation. Whenanimageinafirmware
volume (FV) is updated, the update software will use the relocation information to fix the code image according to
the module’s location in the FV. The relocation is done on the authenticated image; therefore, software verifying the
integrity of the image must undo the relocation during the verification process.
There is no explicit pointer to this data. Instead, the update and verification tool will know that the im-
age is actually stored as PE32 if the Pe32Image bit is set in the header EFI_COMMON_SECTION_HEADER or
EFI_COMMON_SECTION_HEADER2 ;typesEFI_COMMON_SECTION_HEADER andEFI_COMMON_SECTION_HEADER2 are
definedinthe PlatformInitializationSpecification,Volume3 . ThePE32specification,inturn,willbeusedtoascertain
the relocation records.
I-11.2.2.2 Position-Independent Code
If the PEIM is written in position-independent code, then its entry point shall be at the lowest address in the section.
This method is useful for creating PEIMs for the Itanium ®processor family.
I-11.2.2.3 Relocation Information Format
TherelocationswillbecontainedinaTEorPE32+image. Seethe MicrosoftPortableExecutableandCommonObject

FileFormatSpecification formoreinformation. ThedeterminationofwhethertheimagesubscribestothePE32image
formatorisposition-independentassemblylanguageisprovidedbythefirmwarevolumesectiontype. ThePEIMthat
is formatted as PE/COFF will always be linked against a base address of zero. This allows for support of signature
checking.
The section may also be compressed if there is a compression encapsulation section.
I-11.2. PEIM Structure I-81UEFI Platform Initialization Specification, Release 1.8
I-11.2.3 Authentication Information
This section describes in more detail, the means by which authentication information could be contained in a section
oftypeEFI_SECTION_GUID_DEFINED (seethePlatformInitializationSpecification ,Volume3,formoreinformation
on section types). The information contained in this section could be one of the following:
•A cryptographic-quality hash computed across the PEIM image
•A simple checksum
•A CRC
TheGUIDdefinesthemeaningoftheassociatedencapsulateddata. Therelocationsectionisneededtoundothefix-ups
doneontheimagesothehashthatwascomputedatbuildtimecanbeconfirmed. Inotherwords,thebuildofaPEIM
imageislinkedagainstzero,buttheupdatetoolwillrelocatethePEIMimageforitsexecute-in-placeaddress(atleast
forimagesthatarenotposition-independentcode). Anysigninginformationiscalculatedontheimageaftertheimage
has been linked against an address of zero. The relocations on the image will have to be “undone” to determine if the
image has been modified.
TheimagemustbelinkedagainstaddresszerobythePEIMprovider. Thebuildorupdatetoolwillapplytheappropriate
relocations. The linkage against address zero is key because it allows a subsequent undoing of the relocations.
I-11.3 PEIM Invocation Entry Point
I-11.3.1 EFI_PEIM_ENTRY_POINT2
Summary
The PEI Dispatcher will invoke each PEIM one time.
Prototype
typedef
(EFIAPI *EFI_PEIM_ENTRY_POINT2) (
);
Handle of the file being invoked. Type EFI_PEI_FILE_HANDLE is defined in FfsFindNextFile() .
Describes the list of possible PEI Services.
ThisfunctionistheentrypointforaPEIM. EFI_IMAGE_ENTRY_POINT2 istheequivalentofthisstateintheUEFI/DXE
environment; see the DXE CIS for its definition.
The motivation behind this definition is that the firmware file system has the provision to mark a file as being both
a PEIM and DXE driver. The result of this name would be that both the PEI Dispatcher and the DXE Dispatcher
would attempt to execute the module. In doing so, it is incumbent upon the code in the entry point of the driver
to decide what services are exposed, namely whether to make boot service and runtime calls into the UEFI System
Table or to make calls into the PEI Services Table. The means by which to make this decision entail examining the
second argument on entry, which is a pointer to the respective foundation’s exported service-call table. Both PEI and
I-11.3. PEIM Invocation Entry Point I-82UEFI Platform Initialization Specification, Release 1.8
UEFI/DXE have a common header, EFI_TABLE_HEADER , for the table. The code in the PEIM or DXE driver will
examine the Arg2->Hdr->Signature . If it isEFI_SYSTEM_TABLE_SIGNATURE , the code will assume DXE driver
behavior; if it is PEI_SERVICES_SIGNATURE , the code will assume PEIM behavior.
EFI_SUCCESS The service completed successfully
< 0 There was an error
I-11.4 PEIM Descriptors
I-11.4.1 PEIM Descriptors Overview
APEIMdescriptoristhedatastructureusedbyPEIMstoexportserviceentrypointsanddata. Thedescriptorcontains
the following:
•Flags
•A pointer to a GUID
•A pointer to data
The latter data can include a list of pointers to functions and/or data. It is the function pointers that are commonly
referred to as PEIM-to-PEIM Interfaces (PPIs), and the PPI is the unit of software across which PEIMs can invoke
services from other PEIMs.
APEIMalsousesaPEIMdescriptortoexportaservicetothePEIFoundationintowhichthePEIFoundationwillpass
control in response to an event, namely “notifying” the callback when a PPI is installed or reinstalled. As such, PEIM
descriptors serve the dual role of exposing the following:
•A callable interface/data for other PEIMs
•A callback interface from the perspective of the PEI Foundation
I-11.4.2 EFI_PEI_DESCRIPTOR
Summary
ThisdatastructureisthemeansbywhichcallableservicesareinstalledandnotificationsareregisteredinthePEIphase.
Prototype
EFI_PEI_NOTIFY_DESCRIPTOR Notify;
EFI_PEI_PPI_DESCRIPTOR Ppi;
} EFI_PEI_DESCRIPTOR;
Notify
The typedef structure of the notification descriptor. See the EFI_PEI_NOTIFY_DESCRIPTOR type definition.
Ppi
The typedef structure of the PPI descriptor. See the EFI_PEI_PPI_DESCRIPTOR type definition.
I-11.4. PEIM Descriptors I-83UEFI Platform Initialization Specification, Release 1.8
EFI_PEI_DESCRIPTOR isadatastructurethatcanbeeitheraPPIdescriptororanotificationdescriptor. APPIdescrip-
tor is used to expose callable services to other PEIMs. A notification descriptor is used to register for a notification or
callback when a given PPI is installed.
I-11.4.3 EFI_PEI_NOTIFY_DESCRIPTOR
Summary
The data structure in a given PEIM that tells the PEI Foundation where to invoke the notification service.
Prototype
typedef struct _EFI_PEI_NOTIFY_DESCRIPTOR {
UINTN Flags;
EFI_GUID *Guid;
EFI_PEIM_NOTIFY_ENTRY_POINT Notify;
} EFI_PEI_NOTIFY_DESCRIPTOR;
Flags
Details if the type of notification is callback or dispatch.
Guid
The address of the EFI_GUID that names the interface.
Notify
AddressofthenotificationcallbackfunctionitselfwithinthePEIM.Type EFI_PEIM_NOTIFY_ENTRY_POINT is
defined in “Related Definitions” below.
EFI_PEI_NOTIFY_DESCRIPTOR is a data structure that is used by a PEIM that needs to be called back when a PPI
is installed or reinstalled. The notification is similar to the RegisterProtocolNotify() function in the UEFI 2.0
Specification. The use model is complementary to the dependency expression (depex) and is as follows:
•A PEIM expresses the PPIs that it must have to execute in its depex list.
•APEIMexpressesanyotherPEIMsthatitneeds,perhapsatsomelatertime,in EFI_PEI_NOTIFY_DESCRIPTOR
.
ThelatterdatastructureincludestheGUIDofthePPIforwhichthePEIMpublishingthenotificationwouldliketobe
reinvoked.
Following is an example of the notification use model for EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI . In this
example, a PEIM called SamplePeim executes early in the PEI phase before main memory is available. However,
SamplePeim also needs to create some large data structure later in the PEI phase. As such, SamplePeim has a NULL
depex, but after its entry point is processed, it needs to call NotifyPpi() with aEFI_PEI_NOTIFY_DESCRIPTOR ,
where the notification descriptor includes the following:
•A reference to EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI
•A reference to a function within this same PEIM called SampleCallback
When the PEI Foundation finally migrates the system from temporary to permanent memory and installs the
EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI , the PEI Foundation assesses if there are any pending notifications
onthisPPI.AfterthePEIFoundationdiscoversthedescriptorfromSamplePeim,thePEIFoundationinvokesSample-
Callback.
I-11.4. PEIM Descriptors I-84UEFI Platform Initialization Specification, Release 1.8
With respect to the Flagsparameter, the difference between callback and dispatch mode is as follows:
•Callbackmode : InvokesalloftheagentsthatareregisteredfornotificationimmediatelyafterthePPIisinstalled.
•Dispatch mode : Calls the agents that are registered for notification only after the PEIM that installs the PPI in
question has returned to the PEI Foundation.
The callback mechanism will give a better quality of service, but it has the downside of possibly deepening the use of
the stack (i.e., the agent that installed the PPI that engenders the notification is a PEIM itself that has used the stack
already). The dispatcher mode, however, is better from a stack-usage perspective in that when the PEI Foundation
invokestheagentsthatwantnotification,thestackhasreturnedtotheminimumstackusageofjustthePEIFoundation.
typedef
(EFIAPI *EFI_PEIM_NOTIFY_ENTRY_POINT) (
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
);
Indirect reference to the PEI Services Table.
NotifyDescriptor
Address of the notification descriptor data structure. Type EFI_PEI_NOTIFY_DESCRIPTOR is defined above.
Ppi
Address of the PPI that was installed. The status code returned from this function is ignored.
I-11.4.4 EFI_PEI_PPI_DESCRIPTOR
Summary
The data structure through which a PEIM describes available services to the PEI Foundation.
Prototype
VOID *Ppi;
} EFI_PEI_PPI_DESCRIPTOR;
Flags
This field is a set of flags describing the characteristics of this imported table entry. See “Related Definitions”
below for possible flag values.
Guid
Ppi

typedef
);
Ppi
Summary
Prototype
VOID *Ppi;
Flags
Guid
Ppi
A pointer to the PPI. It contains the information necessary to install a service.
I-11.4. PEIM Descriptors I-85UEFI Platform Initialization Specification, Release 1.8
EFI_PEI_PPI_DESCRIPTOR isadatastructurethatiswithinthebodyofaPEIMorcreatedbyaPEIM.Itincludesthe
•Information about the nature of the service
•A reference to a GUID naming the service
•An associated pointer to either a function or data related to the service
There can be a catenation of one or more of these EFI_PEI_PPI_DESCRIPTOR s. The final descriptor will have the
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST flagsettoindicatetothePEIFoundationhowmanyofthedescriptors
need to be added to the PPI database within the PEI Foundation. The PEI Services that references this data structure
includeInstallPpi() ,ReinstallPpi() , andLocatePpi() .
//
// PEI PPI Services List Descriptors
//
#define EFI_PEI_PPI_DESCRIPTOR_PIC 0x00000001
#define EFI_PEI_PPI_DESCRIPTOR_PPI 0x00000010
#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK 0x00000020
#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_DISPATCH 0x00000040
#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES 0x00000060
#define EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST 0x80000000
PEI PPI Services List Descriptors provides descriptions of the fields in the above definition:
I-11.4. PEIM Descriptors I-86UEFI Platform Initialization Specification, Release 1.8
Table 11.1: PEI PPI Services List Descriptors
Descriptor Description
EFI_PEI_PPI_DESCRIPTOR_PIC When set to 1 this designates that the PPI described by
the structure is position independent code PIC
EFI_PEI_PPI_DESCRIPTOR_PPI When set to 1 this designates that the PPI described
by this structure is a normal PPI As such it should be
callable by the conventional PEI infrastructure
EFI_PE I_PPI_DESCRIPTOR_NOTIFY_CALLBACK Whensetto1thisflagdesignatesthattheserviceregis-
tered in the descriptor is to be invoked at callback This
means that if the PPI is installed for which the listener
registers a notification then the callback routine will be
immediately invoked The danger herein is that the call-
back will inherit whatever depth had been traversed up
to and including this call
EFI_PE I_PPI_DESCRIPTOR_NOTIFY_DISPATCH Whensetto1thisflagdesignatesthattheserviceregis-
tered in the descriptor is to be invoked at dispatch This
deferred until the PEIM calling context returns to the
PEIFoundationPriortoinvocationofthenextPEIMthe
notifications will be dispatched The advantage herein is
thatthecallbackwillhavethemaximumavailablestack
depth as any other PEIM
EFI _PEI_PPI_DESCRIPTOR_NOTIFY_TYPES When set to 1 this flag designates that this is a notifica-
tion style PPI
EFI_P EI_PPI_DESCRIPTOR_TERMINATE_LIST Thisflagissetto1inthelaststructureentryinthelistof
PEI PPI descriptors This flag is used by the PEI Foun-
dation Services to know that there are no additional in-
terfaces to install
I-11.5 PEIM-to-PEIM Communication
I-11.5.1 Overview
PEIMs may invoke other PEIMs. The interfaces themselves are named using GUIDs. Because the PEIMs may be
authored by different organizations at different times and updated at different times, references to these interfaces
cannot be resolved during their execution by referring to the PEI PPI database. The database is loaded and queried
using PEI Services such as InstallPpi() andLocatePpi() .
I-11.5.2 Dynamic PPI Discovery
I-11.5.2.1 PPI Database
ThePPIdatabaseisadatastructurethatPEIMscanusetodiscoverwhatinterfacesareavailableortomanageaspecific
interface. The actual layout of the PPI database is opaque to a PEIM but its contents can be queried and manipulated
using the following PEI Services:
I-11.5. PEIM-to-PEIM Communication I-87UEFI Platform Initialization Specification, Release 1.8
I-11.5.2.2 Invoking a PPI
When the PEI Foundation examines a PEIM for dispatch eligibility, it examines the dependency expression section
of the firmware file. If there are non-NULL contents, the Reverse Polish Notation (RPN) expression is evaluated.
Any requested PPI GUIDs in this data structure are queried in the PPI database. The existence in the database of the
particular PUSH_GUID depex opcode leads to this expression evaluating to true.
I-11.5.2.3 Address Resolution
When a PEIM needs to leverage a PPI, it uses the PEI Foundation Service LocatePpi() to discover if an instance of
the interface exists. The PEIM could do either of the following:
•InstallthePPIinitsdepextoensurethatitsentrypointwillnotbeinvokeduntiltheneededPPIisalreadyinstalled
•Have a very thin set of code in its entry point that simply registers a notification on the desired PPI.
Inthecaseofeitherthedepexorthenotification,the LocatePpi() callwillthensucceedandthepointerreturnedon
this call references the EFI_PEI_PPI_DESCRIPTOR . It is through this data structure that the actual code entry point
can be discovered. If this PEIM is being loaded before permanent memory is available, it will not have resources to
cache this discovered interface and will have to search for this interface every time it needs to invoke the service.
ItshouldalsobenotedthatyoucannotuninstallaPPI,sotheserviceswillbeleftinthedatabase. IfaPPIneedstobe
shrouded, a version can be “reinstalled” that just returns failure.
Also, there is peril in caching a PPI. For example, if you cache a PPI and the producer of the PPI “reinstalls” it to be
something else (i.e., shadows to memory), then you have the possibility that the agent who cached the data will have
“stale”or“illegal”data. Forexample,imaginetheStallPPI, EFI_PEI_STALL_PPI ,relocatingitselftomemoryusing
the Load File PPI, EFI_PEI_LOAD_FILE_PPI , and reinstalling the interface for performance considerations. A way
to solve the latter issue, as a platform builder, is by having a different stall PPI for the memory-based one versus that
of the Execute In Place (XIP) one.
I-11.5. PEIM-to-PEIM Communication I-88CHAPTER
TWELVE
ADDITIONAL PPIS
I-12.1 Introduction
ArchitecturalPPIsdescribedacollectionofarchitecturallyrequiredPPIs. ThesewereinterfacesconsumedbythePEI
Foundation and are not intended to be consumed by other PEIMs.
InadditiontothesearchitecturalPPIs,however,thereisanothernamespaceofPPIsthatareoptionalormandatoryfor
a given platform. This section describes these additional PPIs:
•Required PPIs:
–CPU I/O PPI
–PCI Configuration PPI
–Stall PPI
–PEI Variable Services
•Optional PPIs:
–Security (SEC) Platform Information PPI
These shall be referred to as first-class PEIMs in some contexts.
I-12.2 Required Additional PPIs
I-12.2.1 PCI Configuration PPI (Required)
The PEI phase provides limited support for initializing and configuring PCI devices through the
EFI_PEI_PCI_CFG2_PPI. The PEI module which supports a PCI root bridge may install this PPI to allow ac-
cess to the PCI configuration space for a particular PCI segment. The PEI module responsible for the PCI root bridge
representing segment 0 should also install a pointer to the PPI in the PEI Services Table.
ThePEImoduleswhichcontroldevicesonsegment0mayusethepointerprovidedinthePEIServicesTable. ThePEI
modules for devices residing on other segments may find the correct PPI by iterating through PPI instances using the
LocatePpi() function. For example:
UINTN Instance = 0;
EFI_PEI_PPI_DESCRIPTOR *PciCfgDescriptor = NULL;
EFI_PEI_PCI_CFG2_PPI *PciCfg = NULL;
I-89UEFI Platform Initialization Specification, Release 1.8
/* Loop through all instances of the PPI */
for(;;) {
Status = PeiServices->LocatePpi(PeiServices,
&gPeiPciCfg2PpiGuid,
Instance,
&PciCfgDescriptor,
(VOID**) &PciCfg
);
if(Status != EFI_SUCCESS \|\|
PciCfg->Segment == MySegment) {
break;
}
Instance++;
}
if(Status == EFI_SUCCESS) {
...PciCfg contains pointer...
}
I-12.2.1.1 EFI_PEI_PCI_CFG2_PPI
Summary
Provides platform or chipset-specific access to the PCI configuration space for a specific PCI segment.
GUID
static const EFI_GUID EFI_PEI_PCI_CFG2_PPI_GUID = \
{ 0x57a449a, 0x1fdc, 0x4c06, \
{ 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 }}
Prototype
typedef struct \_EFI_PEI_PCI_CFG2_PPI {
EFI_PEI_PCI_CFG2_PPI_IO Read;
EFI_PEI_PCI_CFG2_PPI_IO Write;
EFI_PEI_PCI_CFG2_PPI_RW Modify;
UINT16 Segment;
} EFI_PEI_PCI_CFG2_PPI
Read
PCI read services. See the Read()function description.
Write
PCI write services. See the Write() function description.
Modify
PCI read-modify-write services. See the Modify() function description.
Segment
The PCI bus segment which the specified functions will access.
I-12.2. Required Additional PPIs I-90UEFI Platform Initialization Specification, Release 1.8
TheEFI_PEI_PCI_CFG2_PPI interfaces are used to abstract accesses to the configuration space of PCI controllers
behind a PCI root bridge controller. There can be multiple instances of this PPI in the system, one for each segment.

GUID
Prototype
Read
Write
Modify
Segment
The pointer to the instance which describes segment 0 is installed in the PEI Services Table.
The assignment of segment numbers is implementation specific.
TheModify() service allows for space-efficient implementation of the following common operations:
•Reading a register
•Changing some bit fields within the register
•Writing the register value back into the hardware
TheModify() service is a composite of the Read()andWrite() services.
Register
Register number in PCI configuration space.
Function
Function number in the PCI device (0-7).
Device
Device number in the PCI device (0-31).
Bus
PCI bus number (0-255).
ExtendedRegister
RegisternumberinPCIconfigurationspace. Ifthisfieldiszero,thenRegisterisusedfortheregisternumber. If
this field is non-zero, then Register is ignored and this field is used for the register number.
I-12.2.1.2 EFI_PEI_PCI_CFG2_PPI.Read()
Summary
PCI read operation.
Prototype
typedef
(EFIAPI *EFI_PEI_PCI_CFG_PPI_IO) (
IN CONST EFI_PEI_PCI_CFG2_PPI *This,
IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
);
This
Pointer to local data for the interface.
I-12.2. Required Additional PPIs I-91UEFI Platform Initialization Specification, Release 1.8
Width
The width of the access. Enumerated in bytes. Type EFI_PEI_PCI_CFG_PPI_WIDTH is defined in “Related
Address
The physical address of the access. The format of the address is described by
EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS , which is defined in “Related Definitions” below.
Buffer
A pointer to the buffer of data.
TheRead()function reads from a given location in the PCI configuration space.
// EFI_PEI_PCI_CFG_PPI_WIDTH
EfiPeiPciCfgWidthUint8 = 0,
EfiPeiPciCfgWidthUint16 = 1,
EfiPeiPciCfgWidthUint32 = 2,
EfiPeiPciCfgWidthUint64 = 3,
EfiPeiPciCfgWidthMaximum
} EFI_PEI_PCI_CFG_PPI_WIDTH;
// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
UINT8 Register;
UINT8 Function;
UINT8 Device;
UINT8 Bus;
UINT32 ExtendedRegister;
} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
Register
8-bit register offset within the PCI configuration space for a given device’s function space.
Function
Only the 3 least-significant bits are used to encode one of 8 possible functions within a given device.
Device
Only the 5 least-significant bits are used to encode one of 32 possible devices.
Bus
8-bit value to encode between 0 and 255 buses.
#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
(((bus) << 24) | \
((dev) << 16) | \
I-12.2. Required Additional PPIs I-92UEFI Platform Initialization Specification, Release 1.8
((func) << 8) | \
((reg) < 256 ? (reg) : ((UINT64) (reg) << 32)))
EFI_DEVICE_ERROR There was a problem with the transaction
EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this time
I-12.2.1.3 EFI_PEI_PCI_CFG2_PPI.Write()
Summary
PCI write operation.
Prototype
typedef
(EFIAPI \*EFI_PEI_PCI_CFG_PPI_IO) (
);
This
Width
The width of the access. Enumerated in bytes. Type EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
Address
The physical address of the access.
Buffer
TheWrite() function writes to a given location in the PCI configuration space.
I-12.2. Required Additional PPIs I-93UEFI Platform Initialization Specification, Release 1.8
I-12.2.1.4 EFI_PEI_PCI_CFG2_PPI.Modify()
Summary
PCI read-modify-write Operation.
Prototype
typedef
(EFIAPI \*EFI_PEI_PCI_CFG_PPI_RW) (
IN CONST EFI_PEI_PCI_CFG_PPI *This,
IN VOID *SetBits,
IN VOID *ClearBits
);
This
Width
Address
SetBits
Points to value to bitwise-OR with the read configuration value. The size of the value is determined by Width.
ClearBits
Points to the value to negate and bitwise-AND with the read configuration value. The size of the value is deter-
mined by Width.
TheModify() function performs a read-modify-write operation on the contents from a given location in the PCI
configuration space.
I-12.2. Required Additional PPIs I-94UEFI Platform Initialization Specification, Release 1.8
I-12.2.2 Stall PPI (Required)
I-12.2.2.1 EFI_PEI_STALL_PPI (Required)
Summary
ThisPPIisinstalledbysomeplatformorchipset-specificPEIMthatabstractstheblockingstallservicetootheragents.
GUID
#define EFI_PEI_STALL_PPI_GUID \
{ 0x1f4c6f90, 0xb06b, 0x48d8, {0xa2, 0x01, 0xba, 0xe5, \
0xf1, 0xcd, 0x7d, 0x56} }
typedef
struct _EFI_PEI_STALL_PPI {
UINTN Resolution;
EFI_PEI_STALL Stall;
} EFI_PEI_STALL_PPI;
Parameter
Resolution
The resolution in microseconds of the stall services.
Stall
The actual stall procedure call. See the Stall() function description.
This service provides a simple, blocking stall with platform-specific resolution.
I-12.2.2.2 EFI_PEI_STALL_PPI.Stall()
Summary
Blocking stall.
Prototype
typedef
(EFIAPI *EFI_PEI_STALL) (
IN CONST EFI_PEI_STALL_PPI *This,
);
This
Pointer to the local data for the interface.
I-12.2. Required Additional PPIs I-95UEFI Platform Initialization Specification, Release 1.8
Microseconds
Number of microseconds for which to stall.
TheStall() functionprovidesablockingstallforatleastthenumberofmicrosecondsstipulatedinthefinalargument
of the API.
EFI_SUCCESS The service provided at least the required delay.
I-12.2.3 Variable Services PPI (Required)
I-12.2.3.1 EFI_PEI_READ_ONLY_VARIABLE2_PPI
Summary
Permits read-only access to the UEFI variable store during the PEI phase.
GUID
#define EFI_PEI_READ_ONLY_VARIABLE2_PPI_GUID \
{ 0x2ab86ef5, 0xecb5, 0x4134, \
0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4 }
Prototype
typedef struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI {
EFI_PEI_GET_VARIABLE2 GetVariable;
EFI_PEI_GET_NEXT_VARIABLE_NAME2 NextVariableName;
} EFI_PEI_READ_ONLY_VARIABLE2_PPI;
GetVariable
A service to read the value of a particular variable using its name.
NextVariableName
Find the next variable name in the variable store.
These services provide a light-weight, read-only variant of the full UEFI variable services.
I-12.2.3.2 EFI_PEI_READ_ONLY_VARIABLE2_PPI.GetVariable
Summary
This service retrieves a variable’s value using its name and GUID.
Prototype
typedef
(EFIAPI *EFI_PEI_GET_VARIABLE2)(
IN CONST EFI_PEI_READ_ONLY_VARIABLE2_PPI *This,
I-12.2. Required Additional PPIs I-96UEFI Platform Initialization Specification, Release 1.8
IN CONST CHAR16 *VariableName,
IN CONST EFI_GUID *VariableGuid,
OUT UINT32 *Attributes, OPTIONAL
OUT VOID *Data, OPTIONAL
);
This
A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI .
VariableName
A pointer to a null-terminated string that is the variable’s name.
VariableGuid
Apointertoan EFI_GUID thatisthevariable’sGUID.Thecombinationof VariableGuid andVariableName
must be unique.
If non-NULL, on return, points to the variable’s attributes. See “Related Definitons” below for possi-

Summary
Prototype
typedef
);
This
ble attribute values. If not NULL, then Attributes is set on output both when EFI_SUCCESS and when
DataSize
Onentry,pointstothesizeinbytesofthe Databuffer. Onreturn,pointstothesizeofthedatareturnedin Data
.
Data
Pointstothebufferwhichwillholdthereturnedvariablevalue. Maybe NULLwithazero DataSize inorderto
Read the specified variable from the UEFI variable store. If the Databuffer is too small to hold the contents of the
variable,theerror EFI_BUFFER_TOO_SMALL isreturnedand DataSize issettotherequiredbuffersizetoobtainthe
data.
EFI_SUCCESS The variable was read successfully
EFI_NOT_FOUND The variable was not found
EFI_BUFFER_TOO_SMALL TheDataSize istoosmallfortheresult DataSize hasbeenupdated
with the size needed to complete the request If Attributes is not
NULLthen the attributes bitmask for the variable has been stored to
the memory location pointed to by Attributes
EFI_INVALID_PARAMETER VariableName isNULL
EFI_INVALID_PARAMETER DataSize isNULL
EFI_INVALID_PARAMETER TheDataSize is not too small and Data is NULL
EFI_DEVICE_ERROR The variable could not be retrieved because of a device error
EFI_INVALID_PARAMETER VariableGuid isNULL
I-12.2. Required Additional PPIs I-97UEFI Platform Initialization Specification, Release 1.8
I-12.2.3.3 EFI_PEI_READ_ONLY_VARIABLE2_PPI.NextVariableName
Summary
Return the next variable name and GUID.
Prototype
typedef
(EFIAPI EFI_PEI_GET_NEXT_VARIABLE_NAME2) (
IN OUT EFI_GUID *VariableGuid
);
This
VariableNameSize
Onentry,pointstothesizeofthebufferpointedtoby VariableName . Onreturn,thesizeofthevariablename
buffer
Onentry,apointertoanull-terminatedstringthatisthevariable’sname. Onreturn,pointstothenextvariable’s
null-terminated name string.
Onentry,apointertoan EFI_GUID thatisthevariable’sGUID.Onreturn,apointertothenextvariable’sGUID.
Desription
This function is called multiple times to retrieve the VariableName andVariableGuid of all variables currently
available in the system. On each call, the previous results are passed into the interface, and, on return, the interface
returns the data for the next interface. When the entire variable list has been returned, EFI_NOT_FOUND is returned.
Note:If``EFI_BUFFER_TOO_SMALL ``is returned, the ``VariableName ``buffer was too small for the name of the
next variable. When such an error occurs, ``VariableNameSize ``is updated to reflect the size of the buffer needed. In
allcaseswhencalling ``GetNextVariableName() ``the``VariableNameSize ``mustnotexceedtheactualbuffersizethat
was allocated for ``VariableName ``.
To start the search, a null-terminated string is passed in VariableName ; that is,VariableName is a pointer to a null
Unicodecharacter. Thisisalwaysdoneontheinitialcall. When VariableName isapointertoanullUnicodecharacter,
VariableGuid is ignored.
EFI_NOT_FOUND The variable could not be found
EFI_BUFFER_TOO_SMALL TheVariableNameSize is too small for the resulting data
VariableNameSize is updated with the size required for the spec-
ified variable
EFI_INVALID_PARAMETER VariableName VariableGuid or VariableNameSize is NULL
I-12.2. Required Additional PPIs I-98UEFI Platform Initialization Specification, Release 1.8
I-12.3 Optional Additional PPIs
I-12.3.1 SEC Platform Information PPI (Optional)
I-12.3.1.1 EFI_SEC_PLATFORM_INFORMATION_PPI (Optional)
Summary
This service is the platform information for the PEI Foundation.
GUID
#define EFI_SEC_PLATFORM_INFORMATION_GUID \
{0x6f8c2b35, 0xfef4, 0x448d, 0x82, 0x56, 0xe1, \
0x1b, 0x19, 0xd6, 0x10, 0x77}
Prototype
typedef struct \_EFI_SEC_PLATFORM_INFORMATION_PPI {
EFI_SEC_PLATFORM_INFORMATION PlatformInformation;
} EFI_SEC_PLATFORM_INFORMATION_PPI;
PlatformInformation
Conveys state information out of the SEC phase into PEI. See the PlatformInformation() function descrip-
tion.
This service abstracts platform-specific information.
I-12.3.1.2 EFI_SEC_PLATFORM_INFORMATION_PPI.PlatformInformation()
Summary
This service is the single member of the EFI_SEC_PLATFORM_INFORMATION_PPI that conveys state information out
of the Security (SEC) phase into PEI.
Prototype
typedef
(EFIAPI *EFI_SEC_PLATFORM_INFORMATION) (
IN OUT UINT64 *StructureSize,
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
);
StructureSize
Pointer to the variable describing size of the input buffer.
I-12.3. Optional Additional PPIs I-99UEFI Platform Initialization Specification, Release 1.8
PlatformInformationRecord
Pointertothe EFI_SEC_PLATFORM_INFORMATION_RECORD .TypeEFI_SEC_PLATFORM_INFORMATION_RECORD
ThisserviceispublishedbytheSECphase. TheSECphasehandoffhasanoptional EFI_PEI_PPI_DESCRIPTOR listas
itsfinalargumentwhencontrolispassedfromSECintothePEIFoundation. Assuch,iftheplatformsupportsthebuilt-
inselftest(BIST)onIA-32IntelarchitectureorthePAL-AhandoffstateforItanium ®architecture,thisinformationis
encapsulatedintothedatastructureabstractedbythisservice. Thisinformationiscollectedfortheboot-strapprocessor
(BSP) on IA-32, and for Itanium architecture, it is available on all processors that execute the PEI Foundation.
Themotivationforthisserviceisthataspecificprocessorregistercontainsthisinformationforeachmicroarchitecture,
but the PEI CIS avoids using specific processor registers. Instead, the PEI CIS describes callable interfaces across
whichdataisconveyed. Assuch,thisprocessorstateinformationthatiscollectedattheresetofthemachineismapped
intoacommoninterface. Theexpectationisthatamanageabilityagent,suchasaplatformPEIMthatlogsinformation
for the platform, would use this interface to determine the viability of the BSP and possibly select an alternate BSP if
there are significant errors.
// EFI_SEC_PLATFORM_INFORMATION_RECORD
IA32_HANDOFF_STATUS IA32HealthFlags;
X64_HANDOFF_STATUS x64HealthFlags;
ITANIUM_HANDOFF_STATUS ItaniumHealthFlags;
} EFI_SEC_PLATFORM_INFORMATION_RECORD;
HealthFlags
Contains information generated by microcode, or hardware, about the state of the processor upon reset. Type
EFI_HEALTH_FLAGS is defined below.
// EFI_HEALTH_FLAGS
struct {
UINT32 Status : 2;
UINT32 Tested : 1;
UINT32 Reserved1 :13;
UINT32 VirtualMemoryUnavailable : 1;
UINT32 Ia32ExecutionUnavailable : 1;
UINT32 FloatingPointUnavailable : 1;
UINT32 MiscFeaturesUnavailable : 1;
UINT32 Reserved2 :12;
} Bits;
UINT32 Uint32;
} EFI_HEALTH_FLAGS;
..FIX THIS REF!!
IA-32 and X64 have the BIST. See Health Flag Bit Format for more information on EFI_HEALTH_FLAGS .
The following two structures are for IA32 and x64.
I-12.3. Optional Additional PPIs I-100UEFI Platform Initialization Specification, Release 1.8
typedef EFI_HEALTH_FLAGS X64_HANDOFF_STATUS;
typedef EFI_HEALTH_FLAGS IA32_HANDOFF_STATUS;
There is no instance of an EFI_SEC_PLATFORM_INFORMATION_RECORD for the ARM PI binding.
For Itanium, the structure is as follows:
Fordetails,seethe ItaniumSoftwareDevelopersManual ,Volume2,Rev2.2,DocumentNumber: 245318-005(SwDe-
vMan) Section 11.2.2.1 “Definition of SALE_ENTRY State Parameter” as indicated below.
UINT8 BootPhase; // SALE_ENTRY state : 3 = Recovery_Check
//and0 = RESET orNormal_Boot phase.
// See 'function 'inSwDevMan Fig 11-8 and
// Table 11-3.
UINT8 FWStatus; // Firmware status on entry to SALE.
// See 'Status 'inSwDevMan Fig 11-8 and
// Table 11-4.
UINT32 Reserved2;
UINT16 ProcId; // Geographically significant unique
// processor ID assigned by PAL.
// See 'proc_id 'inSwDevMan Fig 11-9
//andTable 11-5.
UINT16 Reserved3;
UINT8 IdMask; // See 'id_mask 'inSwDevMan
// Fig 11-9 andTable 11-5.
UINT8 EidMask; // See 'eid_mask 'inSwDevMan
// Fig 11-9 andTable 11-5
UINT16 Reserved4;
UINT64 PalCallAddress; // Address to make PAL calls.
UINT64 PalSpecialAddress; // If the entry state is
// RECOVERY_CHECK, this
// contains the PAL_RESET
//returnaddress, and ifentry
// state isRESET, this contains
// address forPAL_authentication
// call.
UINT64 SelfTestStatus; // GR35 from PALE_EXIT state,
// See 'Self Test State 'in
// SwDevMan Fig 11-10 and
// Table 11-6.
UINT64 SelfTestControl; // GR37 from PALE_EXIT state:
// See 'Self Test Control 'in
// SwDevMan Fig 11-11.
UINT64 MemoryBufferRequired; // See GR38 Reset Layout
//inSwDevMan Table 11-2.

// call.
} ITANIUM_HANDOFF_STATUS;
Consultthe PALE_RESET ExitStateinSoftwareDevelopmentManualforItaniumregardinganinterpretationofthese
fields.
I-12.3. Optional Additional PPIs I-101UEFI Platform Initialization Specification, Release 1.8
EFI_BUFFER_TOO_SMALL The buffer was too small The current buffer size needed to hold the
record is returned in StructureSize
I-12.3.2 SEC Platform Information 2 PPI (Optional)
I-12.3.2.1 EFI_SEC_PLATFORM_INFORMATION2_PPI (Optional)
Summary
This service is the primary handoff state into the PEI Foundation. The Security (SEC) component creates the early,
transitorymemoryenvironmentandalsoencapsulatesknowledgeofatleastthelocationoftheBootFirmwareVolume
(BFV).
GUID
#define EFI_SEC_PLATFORM_INFORMATION2_GUID \
{0x9e9f374b, 0x8f16, 0x4230,
{ 0x98, 0x24, 0x58, 0x46, 0xee, 0x76, 0x6a, 0x97}};
Prototype
typedef struct _EFI_SEC_PLATFORM_INFORMATION2_PPI {
EFI_SEC_PLATFORM_INFORMATION2 PlatformInformation2;
} EFI_SEC_PLATFORM_INFORMATION2_PPI;
PlatformInformation2
ConveysstateinformationoutoftheSECphaseintoPEIformanyCPU’s. Seethe PlatformInformation2()
This service abstracts platform-specific information for many CPU’s. It is the multi-processor equivalent of
PlatformInformation for implementations that synchronize some, if not all CPU’s in the SEC phase.
I-12.3.2.2 EFI_SEC_PLATFORM_INFORMATION2_PPI.PlatformInformation2()
Summary
Thisserviceisthesinglememberofthe EFI_SEC_PLATFORM_INFORMATION2_PPI thatconveysstateinformationout
Prototype
typedef
(EFIAPI *EFI_SEC_PLATFORM_INFORMATION2) (
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2
);
I-12.3. Optional Additional PPIs I-102UEFI Platform Initialization Specification, Release 1.8
PlatformInformationRecord2
Pointertothe EFI_SEC_PLATFORM_INFORMATION_RECORD2 . TypeEFI_SEC_PLATFORM_INFORMATION_RECORD2
Descriptions
This service is published by the SEC phase.
// EFI_SEC_PLATFORM_INFORMATION_RECORD2
UINT32 CpuLocation;
EFI_SEC_PLATFORM_INFORMATION_RECORD InfoRecord;
} EFI_SEC_PLATFORM_INFORMATION_CPU;
UINT32 NumberOfCpus.
EFI_SEC_PLATFORM_INFORMATION_CPU CpuInstance [1];
} EFI_SEC_PLATFORM_INFORMATION_RECORD2;
The CPU location would be the local API ID.
I-12.3.3 Loaded Image PPI (Optional)
I-12.3.3.1 EFI_PEI_LOADED_IMAGE_PPI
Summary
Notifies other drivers of the PEIM being initialized by the PEI Dispatcher.
GUID
#define EFI_PEI_LOADED_IMAGE_PPI_GUID \
{ 0xc1fcd448, 0x6300, 0x4458, \
0xb8, 0x64, 0x28, 0xdf, 0x1, 0x53, 0x64, 0xbc }
Prototype
I-12.3. Optional Additional PPIs I-103UEFI Platform Initialization Specification, Release 1.8
typedef struct _EFI_PEI_LOADED_IMAGE_PPI {
EFI_PHYSICAL_ADDRESS ImageAddress,
UINT64 ImageSize,
EFI_PEI_FILE_HANDLE FileHandle
} EFI_PEI_LOADED_IMAGE_PPI;
ImageAddress
Address of the image at the address where it will be executed.
ImageSize
Size of the image as it will be executed.
Filehandlefromwhichtheimagewasloaded. CanbeNULL,indicatingtheimagewasnotloadedfromahandle.
ThisinterfaceisinstalledbythePEIDispatcheraftertheimagehasbeenloadedandafterallsecuritycheckshavebeen
performed, to notify other PEIMs of the files which are being loaded.
Note: The same PEIM may be initialized twice.
I-12.3.4 SEC HOB PPI
I-12.3.4.1 EFI_SEC_HOB_DATA_PPI
Summary
This PPI allows the SEC code to install HOBs into the HOB list.
GUID
#define EFI_SEC_HOB_DATA_PPI_GUID \
{0x3ebdaf20, 0x6667, 0x40d8,\
{0xb4, 0xee, 0xf5, 0x99, 0x9a, 0xc1, 0xb7, 0x1f}};
typedef struct _EFI_SEC_HOB_DATA_PPI {
EFI_SEC_HOB_DATA_GET GetHobs;
} EFI_SEC_HOB_DATA_PPI;
GetHobs
Retrieves a list of HOBs to install into the PEI HOB list.
This PPI provides a way for the SEC code to pass zero or more HOBs in a HOB list.
I-12.3. Optional Additional PPIs I-104UEFI Platform Initialization Specification, Release 1.8
I-12.3.4.2 EFI_SEC_HOB_DATA_PPI.GetHobs()
Summary
Return a pointer to a buffer containing zero or more HOBs that will be installed into the PEI HOB List.
Prototype
(EFIAPI *EFI_SEC_HOB_DATA_GET) (
IN CONST EFI_SEC_HOB_DATA_PPI *This,
OUT EFI_HOB_GENERIC_HEADER **HobList
);
This
Pointer to this PPI structure.
HobList
A pointer to a returned pointer to zero or more HOBs. If no HOBs are to be returned, then the returned pointer
is a pointer to a HOB of type EFI_HOB_TYPE_END_OF_HOB_LIST .
This function returns a pointer to a pointer to zero or more HOBs, terminated with a HOB of type
EI_HOB_TYPE_END_OF_HOB_LIST .
Note: The HobList must not contain a EFI_HOB_HANDOFF_INFO_TABLE HOB (PHIT) HOB.
Note: TheHOBspointedtobyHobListmustbeformedasdescribedinsection4.5.2ofVolume3,“HOBConstruction
Rules” including the requirement that the list start on an 8-byte boundary.
Status Codes
EFI_SUCCESS This function completed successfully.
EFI_UNSUPPORTED No HOBS are available
I-12.3.5 Recovery
This section contains the definitions of the PPIs that are required on platforms that support firmware recovery. The
table below explains the organization of this section and lists the PPIs that are defined in this section.
Table 12.1: Organization of the Code Definitions Section
Section Summary PPI Definition
Recovery Module PPI Describes the main Recovery
Module PPIEFI_PEI _RECOVERY_MODULE_PPI
Device Recovery Module PPI Describes the Device Recovery
Module PPIEFI_PEI_DEVICE _RECOV-
ERY_MODULE_PPI
Device Recovery Block I O PPI Describes the Device Recovery
BlockIOPPIThissectionisde-
vice specific and addresses the
most common form of recovery
media block I O devices such as
legacy floppy CD ROM or IDE
devicesEFI_PEI_R ECOVERY_BLOCK_IO_PPI
I-12.3. Optional Additional PPIs I-105UEFI Platform Initialization Specification, Release 1.8
This section also contains the definitions for additional data types and structures that are subordinate to the structures
inwhichtheyarecalled. Thefollowingtypesorstructurescanbefoundin“RelatedDefinitions”oftheparentprotocol
or function definition:
•EFI_PEI_BLOCK_IO_MEDIA
•EFI_PEI_BLOCK_DEVICE_TYPE
•EFI_PEI_LBA
I-12.3.5.1 Recovery Module PPI
I-12.3.5.1.1 EFI_PEI_RECOVERY_MODULE_PPI
Summary
Finds and loads the recovery files.
GUID
#define EFI_PEI_RECOVERY_MODULE_PPI_GUID \
{0xFB6D9542, 0x612D, 0x4f45, 0x87, 0x2F, 0x5C, \
0xFF, 0x52, 0xE9, 0x3D, 0xCF}
typedef struct _EFI_PEI_RECOVERY_MODULE_PPI {
EFI_PEI_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule;
} EFI_PEI_RECOVERY_MODULE_PPI;
LoadRecoveryCapsule
Loads a DXE binary capsule into memory.
This module has many roles and is responsible for the following:
1. Calling the driver recovery PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
GetNumberRecoveryCapsules() to determine if one or more DXE recovery entities exist.
2. If no capsules exist, then performing appropriate error handling.
3. Allocatingabufferof MaxRecoveryCapsuleSize asdeterminedby EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
.GetRecoveryCapsuleInfo() or larger.
4. Determining the policy in which DXE recovery capsules are loaded.
5. Calling the driver recovery PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.LoadRecoveryCapsule() for
capsule number x.
6. If the load failed, performing appropriate error handling.
7. Performing security checks for a loaded DXE recovery capsule.
8. If the security checks failed, then logging the failure in a data HOB.
9. If the security checks failed, then determining the next EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
LoadRecoveryCapsule() capsule number; otherwise, go to step 11.
10. If more DXE recovery capsules exist, then go to step 5; otherwise, perform error handling.
I-12.3. Optional Additional PPIs I-106UEFI Platform Initialization Specification, Release 1.8
11. Decomposing the capsule loaded by EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.LoadRecoveryCapsule()
intoitscomponents. ItisassumedthatthepathparametersareredundantforrecoveryandSetupparametersare
either redundant or canned.
12. Invalidating all HOB entries for updateable firmware volume entries. This invalidation prevents possible errant
drivers from being executed.
13. Updating the HOB table with the recovery DXE firmware volume information generated from the capsule de-
composition.
14. Returning to the PEI Dispatcher.
I-12.3.5.1.2 EFI_PEI_RECOVERY_MODULE_PPI.LoadRecoveryCapsule()
Summary

Summary
Loads a DXE capsule from some media into memory and updates the HOB table with the DXE firmware volume
Prototype
typedef
(EFIAPI \*EFI_PEI_LOAD_RECOVERY_CAPSULE) (
IN EFI_PEI_SERVICES \ **PeiServices,
IN struct \_EFI_PEI_RECOVERY_MODULE_PPI *This
);
General-purpose services that are available to every PEIM. Type EFI_PEI_SERVICES is defined in
EFI_PEI_SERVICES .
This
Indicates the EFI_PEI_RECOVERY_MODULE_PPI instance.
This function, by whatever mechanism, retrieves a DXE capsule from some device and loads it into memory.
Note that the published interface is device neutral.
EFI_SUCCESS The capsule was loaded correctly.
EFI_DEVICE_ERROR A devive error occured
EFI_NOT_FOUND A recovery DXE capsule cannot be found.
I-12.3. Optional Additional PPIs I-107UEFI Platform Initialization Specification, Release 1.8
I-12.3.5.2 Device Recovery Module PPI
I-12.3.5.2.1 EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
Summary
Presents a standard interface to EFI_PEI_RECOVERY_MODULE_PPI , regardless of the underlying device(s).
GUID
#define EFI_PEI_DEVICE_RECOVERY_MODULE_PPI_GUID \
{ 0x0DE2CE25, 0x446A, 0x45a7, 0xBF, 0xC9, 0x37, 0xDA, \
0x26, 0x34, 0x4B, 0x37}
typedef struct \_EFI_PEI_DEVICE_RECOVERY_MODULE_PPI {
EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE GetNumberRecoveryCapsules;
EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO GetRecoveryCapsuleInfo;
EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule;
} EFI_PEI_DEVICE_RECOVERY_MODULE_PPI;
GetNumberRecoveryCapsules
Returns the number of DXE capsules that were found. See the GetNumberRecoveryCapsules() function
GetRecoveryCapsuleInfo
Returns the capsule image type and the size of a given image. See the GetRecoveryCapsuleInfo() function
Loads a DXE capsule into memory. See the LoadRecoveryCapsule() function description.
The role of this module is to present a standard interface to EFI_PEI_RECOVERY_MODULE_PPI , regardless of the
underlying device(s). The interface does the following:
•Reports the number of recovery DXE capsules that exist on the associated device(s)
•Finds the requested firmware binary capsule
•Loads that capsule into memory
Adevicecanbeeitheragroupofdevices,suchasablockdevice,oranindividualdevice. Themoduledeterminesthe
internal search order, with capsule number 1 as the highest load priority and number N as the lowest priority.
I-12.3. Optional Additional PPIs I-108UEFI Platform Initialization Specification, Release 1.8
I-12.3.5.2.2 EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.GetNumberRecoveryCapsules()
Summary
Returns the number of DXE capsules residing on the device.
Prototype
typedef
(EFIAPI *EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE) (
IN struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This,
OUT UINTN *NumberRecoveryCapsules
);
This
Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI instance.
NumberRecoveryCapsules
Pointer to a caller-allocated UINTN. On output, *NumberRecoveryCapsules contains the number of recovery
capsule images available for retrieval from this PEIM instance.
This function,by whatever mechanism,searches for DXEcapsules from theassociated device andreturns the number
and maximum size in bytes of the capsules discovered. Entry 1 is assumed to be the highest load priority and entry N
is assumed to be the lowest priority.
EFI_SUCCESS One or more capsules were discovered.
EFI_DEVICE_ERROR A device error has occurred.
I-12.3.5.2.3 EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.GetRecoveryCapsuleInfo()
Summary
Returns the size and type of the requested recovery capsule.
Prototype
typedef
(EFIAPI *EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO) (
IN UINTN CapsuleInstance,
OUT UINTN *Size,
I-12.3. Optional Additional PPIs I-109UEFI Platform Initialization Specification, Release 1.8
OUT EFI_GUID *CapsuleType
);
This
CapsuleInstance
Specifies for which capsule instance to retrieve the information. This parameter must be between one and the
value returned by GetNumberRecoveryCapsules() inNumberRecoveryCapsules .
Size
A pointer to a caller-allocated UINTNin which the size of the requested recovery module is returned.
CapsuleType
A pointer to a caller-allocated EFI_GUID in which the type of the requested recovery capsule is returned.
The semantic meaning of the value returned is defined by the implementation. Type EFI_GUID is defined in
InstallProtocolInterface() in theEFI 1.10 Specification .
This function returns the size and type of the capsule specified by CapsuleInstance.
EFI_DEVICE_ERROR A device error occurred.
I-12.3.5.2.4 EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.LoadRecoveryCapsule()
Summary
Loads a DXE capsule from some media into memory.
Prototype
typedef
(EFIAPI \*EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE) (
IN struct \_EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This,
);
I-12.3. Optional Additional PPIs I-110UEFI Platform Initialization Specification, Release 1.8
This
Specifies which capsule instance to retrieve.
Buffer
Specifies a caller-allocated buffer in which the requested recovery capsule will be returned.
Thisfunction,bywhatevermechanism,retrievesaDXEcapsulefromsomedeviceandloadsitintomemory. Notethat
the published interface is device neutral.
EFI_NOT_FOUND The requested recovery DXE capsule cannot be found.
I-12.3.5.3 Device Recovery Block I/O PPI
The Recovery Module PPI and the Device Recovery Module PPI subsections earlier in Code Definitions are device
neutral. Thissectionisdevicespecificandaddressesthemostcommonformofrecoverymedia-blockI/Odevicessuch
as legacy floppy, CD-ROM, or IDE devices.
The Recovery Block I/O PPI is used to access block devices. Because the Recovery Block I/O PPIs that are provided
bythePEIATAPIdriverandPEIlegacyfloppydriverarethesame,herewedefineasetofgeneralPPIsforbothdrivers
to use.
I-12.3.5.3.1 EFI_PEI_RECOVERY_BLOCK_IO_PPI
Summary
Provides the services required to access a block I/O device during PEI recovery boot mode.
GUID
#define EFI_PEI_RECOVERY_BLOCK_IO_PPI_GUID \
{ 0x695d8aa1, 0x42ee, 0x4c46, 0x80, 0x5c,0x6e, 0xa6, \
0xbc, 0xe7, 0x99, 0xe3 }
typedef struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI {
EFI_PEI_GET_NUMBER_BLOCK_DEVICES GetNumberOfBlockDevices;
EFI_PEI_GET_DEVICE_MEDIA_INFORMATION GetBlockDeviceMediaInfo;
EFI_PEI_READ_BLOCKS ReadBlocks;
} EFI_PEI_RECOVERY_BLOCK_IO_PPI;
GetNumberOfBlockDevices
Gets the number of block I/O devices that the specific block driver manages. See the
GetNumberOfBlockDevices() function description.
I-12.3. Optional Additional PPIs I-111UEFI Platform Initialization Specification, Release 1.8
GetBlockDeviceMediaInfo
Gets the specified media information. See the GetBlockDeviceMediaInfo() function description.
ReadBlocks
Readstherequestednumberofblocksfromthespecifiedblockdevice. Seethe ReadBlocks() functiondescrip-
tion.
This function provides the services that are required to access a block I/O device during PEI recovery boot mode.
I-12.3.5.3.2 EFI_PEI_RECOVERY_BLOCK_IO_PPI.GetNumberOfBlockDevices()
Summary
Gets the count of block I/O devices that one specific block driver detects.
Prototype
typedef
(EFIAPI *EFI_PEI_GET_NUMBER_BLOCK_DEVICES) (
IN struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
OUT UINTN *NumberBlockDevices
);
This
Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
NumberBlockDevices
The number of block I/O devices discovered.
ThisfunctionisusedforgettingthecountofblockI/Odevicesthatonespecificblockdriverdetects. TothePEIATAPI
driver, it returns the number of all the detected ATAPI devices it detects during the enumeration process. To the PEI

tion.
Summary
Prototype
typedef
);
This
legacyfloppydriver,itreturnsthenumberofallthelegacydevicesitfindsduringitsenumerationprocess. Ifnodevice
is detected, then the function will return zero.
EFI_SUCCESS Operation performed successfully
I-12.3. Optional Additional PPIs I-112UEFI Platform Initialization Specification, Release 1.8
I-12.3.5.3.3 EFI_PEI_RECOVERY_BLOCK_IO_PPI.GetBlockDeviceMediaInfo()
Summary
Gets a block device’s media information.
Prototype
typedef
(EFIAPI *EFI_PEI_GET_DEVICE_MEDIA_INFORMATION) (
IN struct \_EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
IN UINTN DeviceIndex,
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
);
This
DeviceIndex
Specifiestheblockdevicetowhichthefunctionwantstotalk. BecausethedriverthatimplementsBlockI/OPPIs
will manage multiple block devices, the PPIs that want to talk to a single device must specify the device index
that was assigned during the enumeration process. This index is a number from one to NumberBlockDevices .
MediaInfo
The media information of the specified block media. Type EFI_PEI_BLOCK_IO_MEDIA is defined in “Related
Definitions” below. The caller is responsible for the ownership of this data structure.
Note:This structure describes an enumeration of possible block device types. This enumeration exists because no
device paths are actually passed across interfaces that describe the type or class of hardware that is publishing the
block I/O interface. This enumeration will allow for policy decisions in the Recovery PEIM, such as “Try to recover
from legacy floppy first, LS-120 second, CD-ROM third.” If there are multiple partitions abstracted by a given device
type, they should be reported in ascending order; this order also applies to nested partitions, such as legacy MBR,
where the outermost partitions would have precedence in the reporting order. The same logic applies to systems such
asIDEthathaveprecedencerelationshipslike“Master/Slave”or“Primary/Secondary”;themasterdeviceshouldbe
reported first, the slave second.
Thisfunctionwillprovidethecallerwiththespecifiedblockdevice’smediainformation. Ifthemediachanges,calling
this function will update the media information accordingly.
// EFI_PEI_BLOCK_IO_MEDIA
EFI_PEI_BLOCK_DEVICE_TYPE DeviceType;
I-12.3. Optional Additional PPIs I-113UEFI Platform Initialization Specification, Release 1.8
UINTN LastBlock;
UINTN BlockSize;
} PEI_BLOCK_IO_MEDIA;
DevType
The type of media device being referenced by DeviceIndex. Type EFI_PEI_BLOCK_DEVICE_TYPE is defined
below.
MediaPresent
A flag that indicates if media is present. This flag is always set for nonremovable media devices.
LastBlock
The last logical block that the device supports.
BlockSize
The size of a logical block in bytes.
//**********************************************************\*
// EFI_PEI_BLOCK_DEVICE_TYPE
LegacyFloppy = 0,
IdeCDROM = 1,
IdeLS120 = 2,
UsbMassStorage = 3,
SD = 4,
EMMC = 5,
UfsDevice = 6,
MaxDeviceType
} EFI_PEI_BLOCK_DEVICE_TYPE;
EFI_SUCCESS Media information about the specified block device was obtained
successfully
EFI_DEVICE_ERROR Cannot get the media information due to a hardware error
I-12.3.5.3.4 EFI_PEI_RECOVERY_BLOCK_IO_PPI.ReadBlocks()
Summary
Reads the requested number of blocks from the specified block device.
Prototype
typedef
(EFIAPI *EFI_PEI_READ_BLOCKS) (
IN EFI_PEI_LBA StartLBA,
I-12.3. Optional Additional PPIs I-114UEFI Platform Initialization Specification, Release 1.8
);
(EFI_PEI_SERVICES ) .
This
thatwasassignedduringtheenumerationprocess. Thisindexisanumberfromoneto NumberBlockDevices .
StartLBA
Thestartinglogicalblockaddress(LBA)toreadfromonthedevice. Type EFI_PEI_LBA isdefinedin“Related
The size of the Bufferin bytes. This number must be a multiple of the intrinsic block size of the device.
Buffer
A pointer to the destination buffer for the data. The caller is responsible for the ownership of the buffer.
The function reads the requested number of blocks from the device. All the blocks are read, or an error is returned. If
there is no media in the device, the function returns EFI_NO_MEDIA .
//****************************************************\*
// EFI_PEI_LBA
typedef UINT64 EFI_PEI_LBA;
EFI_PEI_LBA is theUINT64LBA number.
EFI_SUCCESS The data was read correctly from the device
EFI_DEVICE_ERROR The device reported an error while attempting to perform the read
operation
EFI_INVALID_PARAMETER ThereadrequestcontainsLBAsthatarenotvalidorthebufferisnot
properly aligned
EFI_NO_MEDIA There is no media in the device
EFI_BAD_BUFFER_SIZE TheBufferSize parameter is not a multiple of the intrinsic block
size of the device
I-12.3. Optional Additional PPIs I-115UEFI Platform Initialization Specification, Release 1.8
I-12.3.6 EFI PEI Recovery Block IO2 PPI
I-12.3.6.1 EFI_PEI_RECOVERY_BLOCK_IO2_PPI
Summary
GUID
#define EFI_PEI_RECOVERY_BLOCK_IO2_PPI_GUID \
{ 0x26cc0fad, 0xbeb3, 0x478a,\
{ 0x91, 0xb2, 0xc, 0x18, 0x8f, 0x72, 0x61, 0x98 } }
typedef struct \_EFI_PEI_RECOVERY_BLOCK_IO2_PPI {
EFI_PEI_GET_NUMBER_BLOCK_DEVICES2 GetNumberOfBlockDevices;
EFI_PEI_GET_DEVICE_MEDIA_INFORMATION2
GetBlockDeviceMediaInfo;
EFI_PEI_READ_BLOCKS2 ReadBlocks:
} EFI_PEI_RECOVERY_BLOCK_IO2_PPI;
Revision
The revision to which the interface adheres. All future revisions must be backwards compatible.
tion.
#define EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION 0x00010000
I-12.3. Optional Additional PPIs I-116UEFI Platform Initialization Specification, Release 1.8
I-12.3.6.2 EFI_PEI_RECOVERY_BLOCK_IO2_PPI.GetNumberOfBlockDevices()
Summary
Prototype
typedef
(EFIAPI \*EFI_PEI_GET_NUMBER_BLOCK_DEVICES2) (
IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
);
General-purpose services that are available to every PEIM. Type EFI_PEI_SERVICES is defined in the Intel* ®
*Platform Innovation Framework for EFI Pre-EFI Initialization Core Interface Specification (PEI CIS).
This
I-12.3.6.3 EFI_PEI_RECOVERY_BLOCK_IO2_PPI.GetBlockDeviceMediaInfo()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_GET_DEVICE_MEDIA_INFORMATION2) (
OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
);
I-12.3. Optional Additional PPIs I-117UEFI Platform Initialization Specification, Release 1.8

Summary
Prototype
typedef
);
This
MediaInfo
The media information of the specified block media. Type EFI_PEI_BLOCK_IO2_MEDIA is defined in “Related
Notethatthisstructuredescribesanenumerationofpossibleblockdevicetypes. Thisenumerationexistsbecause
nodevicepathsareactuallypassedacrossinterfacesthatdescribethetypeorclassofhardwarethatispublishing
the block I/O interface. This enumeration will allow for policy decisions in the Recovery PEIM, such as “Try
to recover from legacy floppy first, USB mass storage device second, CD-ROM third.” If there are multiple
partitionsabstractedbyagivendevicetype,theyshouldbereportedinascendingorder;thisorderalsoappliesto
nested partitions, such as legacy MBR, where the outermost partitions would have precedence in the reporting
order. The same logic applies to systems such as IDE that have precedence relationships like “Master/Slave” or
“Primary/Secondary”; the master device should be reported first, the slave second.
// EFI_PEI_BLOCK_IO2_MEDIA
UINT8 InterfaceType;
BOOLEAN RemovablaMedia;
EFI_PEI_LBA LastBlock;
} PEI_BLOCK_IO2_MEDIA;
InterfaceType
Atypeofinterfacethatthedevicebeingreferencedby DeviceIndex isattachedto. Thisfieldre-usesMessaging
DevicePathNodesub-typevaluesasdefinedbySection“9.3.5MessagingDevicePath”of UEFISpecification .
Whenmorethanonesub-typeisassociatedwiththeinterface,sub-typewiththesmallestnumbermustbeused.
For example, InterfaceType must be set to 5 for USB devices.
RemovablaMedia
A flag that indicates if media is removable.
A flag that indicates if media is present. This flag is always set for non-removable media devices.
ReadOnly
A flag that indicates if media is read-only.
I-12.3. Optional Additional PPIs I-118UEFI Platform Initialization Specification, Release 1.8
LastBlock
BlockSize
The size of a logical block in bytes. Type EFI_PEI_LBA is defined below.
I-12.3.6.4 EFI_PEI_RECOVERY_BLOCK_IO2_PPI.ReadBlocks()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_READ_BLOCKS2) (
);
This
StartLBA
The starting logical block address (LBA) to read from on the device. Type EFI_PEI_LBA is defined in in the
GetBlockDeviceMediaInfo() function description.
I-12.3. Optional Additional PPIs I-119UEFI Platform Initialization Specification, Release 1.8
Buffer
EFI_DEVICE_ERROR Thedevicereportedanerrorwhileattemptingtoperformthereadoperation
EFI_INVALID_PARAMETER ThereadrequestcontainsLBAsthatarenotvalidorthebufferisnotproperly
aligned
device
I-12.3.7 EFI PEI Vector Handoff Info PPI
I-12.3.7.1 EFI_PEI_VECTOR_HANDOFF_INFO_PPI (Optional)
Summary
The PPI that describes an array of interrupt and/or exception vectors that are in use and need to persist.
GUID
#define EFI_PEI_VECTOR_HANDOFF_INFO_PPI_GUID \
{ 0x3cd652b4, 0x6d33, 0x4dce, \
{ 0x89, 0xdb, 0x83, 0xdf, 0x97, 0x66, 0xfc, 0xca } }
typedef struct _EFI_PEI_VECTOR_HANDOFF_INFO_PPI {
EFI_VECTOR_HANDOFF_INFO *Info;
} EFI_PEI_VECTOR_HANDOFF_INFO_PPI;
Info
Pointer to an array of interrupt and /or exception vectors.
This is an optional PPI that may be produced by SEC. If present, it provides a description of the interrupt and/or
exceptionvectorsthatwereestablishedintheSECPhaseandneedtopersistintoPEIandDXE.ThisPPIisanarrayof
entries that is terminated by an entry whose Attribute is set toEFI_VECTOR_HANDOFF_LAST_ENTRY .
IfAttribute is set toEFI_VECTOR_HANDOFF_DO_NOT_HOOK , then the associated handler for VectorNumber must
be preserved in PEI and DXE.
IfAttribute issettoEFI_VECTOR_HANDOFF_HOOK_BEFORE ,thenVectorNumbermaybeusedinPEIandDXE,but
new handlers must be invoked prior to when the existing handler is called.
I-12.3. Optional Additional PPIs I-120UEFI Platform Initialization Specification, Release 1.8
IfAttribute issettoEFI_VECTOR_HANDOFF_HOOK_AFTER ,thentheassociated VectorNumber maybeusedinPEI
and DXE, but new handlers must be called after the existing handler is called.
EFI_PEI_VECTOR_HANDOFF_INFO_PPI_GUID canalsobeusedinthePEIPhasetobuildaGUIDedHOBthatcontains
anarrayof EFI_VECTOR_HANDOFF_INFO entriesthatdescribestheinterruptand/orexceptionvectorsinuseinthePEI
Phase. ThismaybeidenticaltothearraypassedupfromSEC,oritcouldbeanarraythatisaugmentedwithadditional
vectors used in PEI Phase.
//
// System configuration table entry that points to the table
//incase an entity inDXE wishes to update/change the vector
// table contents.
//
// The table shall be stored inmemory of type
// EfiBootServicesData.
//
#define EFI_VECTOR_HANDOFF_TABLE_GUID \
{0x996ec11c, 0x5397, 0x4e73, \
{0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef}}
UINT32 VectorNumber;
UINT32 Attribute;
EFI_GUID Owner;
} EFI_VECTOR_HANDOFF_INFO;
VectorNumber
The interrupt or exception vector that is in use and must be preserved.
Attribute
A bitmask that describes the attributes of the interrupt or exception vector.
Owner
The GUID identifies the party who created the entry. For the EFI_VECTOR_HANDOFF_DO_NOT_HOOK case, this
establishes the single owner.
I-12.3.8 CPU I/O PPI (Optional)
I-12.3.8.1 EFI_PEI_CPU_IO_PPI (Optional)
If the service is not available, the PEI Core service EFI_PEI_CPU_IO_PPI *CpuIo member functions will have a
dummy function that return EFI_NOT_AVAILABLE_YET ;
Summary
This PPI is installed by some platform or chipset-specific PEIM that abstracts the processor-visible I/O operations.
GUID
#define EFI_PEI_CPU_IO_PPI_INSTALLED_GUID \
{0xe6af1f7b, 0xfc3f, 0x46da, 0xa8, 0x28, 0xa3, 0xb4, \
0x57, 0xa4, 0x42, 0x82}
I-12.3. Optional Additional PPIs I-121UEFI Platform Initialization Specification, Release 1.8
This is an indicator GUID without any data. It represents the fact that a PEIM has written the address of the
EFI_PEI_CPU_IO_PPI into theEFI_PEI_SERVICES table.
typedef
struct \_EFI_PEI_CPU_IO_PPI {
EFI_PEI_CPU_IO_PPI_ACCESS Mem;
EFI_PEI_CPU_IO_PPI_ACCESS Io;
EFI_PEI_CPU_IO_PPI_IO_READ8 IoRead8;
EFI_PEI_CPU_IO_PPI_IO_READ16 IoRead16;
EFI_PEI_CPU_IO_PPI_IO_READ32 IoRead32;
EFI_PEI_CPU_IO_PPI_IO_READ64 IoRead64;
EFI_PEI_CPU_IO_PPI_IO_WRITE8 IoWrite8;

Summary
GUID
typedef
EFI_PEI_CPU_IO_PPI_IO_WRITE16 IoWrite16;
EFI_PEI_CPU_IO_PPI_IO_WRITE32 IoWrite32;
EFI_PEI_CPU_IO_PPI_IO_WRITE64 IoWrite64;
EFI_PEI_CPU_IO_PPI_MEM_READ8 MemRead8;
EFI_PEI_CPU_IO_PPI_MEM_READ16 MemRead16;
EFI_PEI_CPU_IO_PPI_MEM_READ32 MemRead32;
EFI_PEI_CPU_IO_PPI_MEM_READ64 MemRead64;
EFI_PEI_CPU_IO_PPI_MEM_WRITE8 MemWrite8;
EFI_PEI_CPU_IO_PPI_MEM_WRITE16 MemWrite16;
EFI_PEI_CPU_IO_PPI_MEM_WRITE32 MemWrite32;
EFI_PEI_CPU_IO_PPI_MEM_WRITE64 MemWrite64;
} EFI_PEI_CPU_IO_PPI;
Mem
Collection of memory-access services. See the Mem() function description. Type
EFI_PEI_CPU_IO_PPI_ACCESS is defined in “Related Definitions” below.
Io
Collection of I/O-access services. See the Io()function description. Type EFI_PEI_CPU_IO_PPI_ACCESS is
IoRead8
8-bit read service. See the IoRead8() function description.
IoRead16
16-bit read service. See the IoRead16() function description.
IoRead32
32-bit read service. See the IoRead32() function description.
IoRead64
64-bit read service. See the IoRead64() function description.
IoWrite8
8-bit write service. See the IoWrite8() function description.
IoWrite16
16-bit write service. See the IoWrite16() function description.
IoWrite32
32-bit write service. See the IoWrite32() function description.
IoWrite64
64-bit write service. See the IoWrite64() function description.
I-12.3. Optional Additional PPIs I-122UEFI Platform Initialization Specification, Release 1.8
MemRead8
8-bit read service. See the MemRead8() function description.
MemRead16
16-bit read service. See the MemRead16() function description.
MemRead32
32-bit read service. See the MemRead32() function description.
MemRead64
64-bit read service. See the MemRead64() function description.
MemWrite8
8-bit write service. See the MemWrite8() function description.
MemWrite16
16-bit write service. See the MemWrite16() function description.
MemWrite32
32-bit write service. See the MemWrite32() function description.
MemWrite64
64-bit write service. See the MemWrite64() function description.
ThisPPIprovidesasetofmemory-andI/O-basedservices. Theperspectiveoftheservicesisthatoftheprocessor,not
the bus or system.
//******************************************************\*
// EFI_PEI_CPU_IO_PPI_ACCESS
typedef
struct {
EFI_PEI_CPU_IO_PPI_IO_MEM Read;
EFI_PEI_CPU_IO_PPI_IO_MEM Write;
} EFI_PEI_CPU_IO_PPI_ACCESS;
Read
This service provides the various modalities of memory and I/O read.
Write
This service provides the various modalities of memory and I/O write.
I-12.3.8.2 EFI_PEI_CPU_IO_PPI.Mem()
Summary
Memory-based access services.
Prototype
typedef
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_MEM) (
I-12.3. Optional Additional PPIs I-123UEFI Platform Initialization Specification, Release 1.8
IN CONST EFI_PEI_CPU_IO_PPI *This,
IN EFI_PEI_CPU_IO_PPI_WIDTH Width,
);
This
Width
The width of the access. Enumerated in bytes. Type EFI_PEI_CPU_IO_PPI_WIDTH is defined in “Related
Address
Count
The number of accesses to perform.
Buffer
TheMem()function provides a list of memory-based accesses.
// EFI_PEI_CPU_IO_PPI_WIDTH
EfiPeiCpuIoWidthUint8,
EfiPeiCpuIoWidthUint16,
EfiPeiCpuIoWidthUint32,
EfiPeiCpuIoWidthUint64,
EfiPeiCpuIoWidthFifoUint8,
EfiPeiCpuIoWidthFifoUint16,
EfiPeiCpuIoWidthFifoUint32,
EfiPeiCpuIoWidthFifoUint64,
EfiPeiCpuIoWidthFillUint8,
EfiPeiCpuIoWidthFillUint16,
EfiPeiCpuIoWidthFillUint32,
EfiPeiCpuIoWidthFillUint64,
EfiPeiCpuIoWidthMaximum
} EFI_PEI_CPU_IO_PPI_WIDTH;
EFI_NOT_YET_AVAILABLE The service has not been installed.
I-12.3. Optional Additional PPIs I-124UEFI Platform Initialization Specification, Release 1.8
I-12.3.8.3 EFI_PEI_CPU_IO_PPI.Io()
Summary
I/O-based access services.
Prototype
typedef
);
This
Width
The width of the access. Enumerated in bytes. Type EFI_PEI_CPU_IO_PPI_WIDTH is defined in Mem().
Address
Count
Buffer
TheIo()function provides a list of I/O-based accesses. Input or output data can be found in the last argument.
I-12.3.8.4 EFI_PEI_CPU_IO_PPI.IoRead8()
Summary
8-bit I/O read operations.
Prototype
typedef
UINT8
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ8) (
I-12.3. Optional Additional PPIs I-125UEFI Platform Initialization Specification, Release 1.8
IN UINT64 Address
);
This
Address
TheIoRead8() function returns an 8-bit value from the I/O space.
I-12.3.8.5 EFI_PEI_CPU_IO_PPI.IoRead16()
Summary
16-bit I/O read operations.
Prototype
typedef
UINT16
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ16) (
);
This
Address
TheIoRead16() function returns a 16-bit value from the I/O space.
I-12.3. Optional Additional PPIs I-126UEFI Platform Initialization Specification, Release 1.8
I-12.3.8.6 EFI_PEI_CPU_IO_PPI.IoRead32()
Summary
32-bit I/O read operations.
Prototype
typedef
UINT32
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ32) (
);
This
Address
TheIoRead32() function returns a 32-bit value from the I/O space.
I-12.3.8.7 EFI_PEI_CPU_IO_PPI.IoRead64()
Summary
64-bit I/O read operations.
Prototype
typedef
UINT64
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ64) (
IN CONST_EFI_PEI_CPU_IO_PPI *This,
);
This
Address
TheIoRead64() function returns a 64-bit value from the I/O space.
I-12.3. Optional Additional PPIs I-127UEFI Platform Initialization Specification, Release 1.8
I-12.3.8.8 EFI_PEI_CPU_IO_PPI.IoWrite8()
Summary
8-bit I/O write operations.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE8) (
IN UINT8 Data
);
This
Address
Data
The data to write.
TheIoWrite8() function writes an 8-bit value to the I/O space.
I-12.3.8.9 EFI_PEI_CPU_IO_PPI.IoWrite16()
Summary
16-bit I/O write operation.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE16) (
IN UINT16 Data
);
This
I-12.3. Optional Additional PPIs I-128UEFI Platform Initialization Specification, Release 1.8
Address
Data
TheIoWrite16() function writes a 16-bit value to the I/O space.
I-12.3.8.10 EFI_PEI_CPU_IO_PPI.IoWrite32()
Summary
32-bit I/O write operation.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE32) (

Address
Data
Summary
Prototype
typedef
VOID
);
This
Address
Data
Summary
Prototype
typedef
VOID
);
This
Address
Data
TheIoWrite32() function writes a 32-bit value to the I/O space.
I-12.3.8.11 EFI_PEI_CPU_IO_PPI.IoWrite64()
Summary
64-bit I/O write operation.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE64) (
I-12.3. Optional Additional PPIs I-129UEFI Platform Initialization Specification, Release 1.8
IN UINT64 Data
);
This
Address
Data
TheIoWrite64() function writes a 64-bit value to the I/O space.
I-12.3.8.12 EFI_PEI_CPU_IO_PPI.MemRead8()
Summary
8-bit memory read operations.
Prototype
typedef
UINT8
(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ8) (
);
This
Address
TheMemRead8() function returns an 8-bit value from the memory space.
I-12.3. Optional Additional PPIs I-130UEFI Platform Initialization Specification, Release 1.8
I-12.3.8.13 EFI_PEI_CPU_IO_PPI.MemRead16()
Summary
16-bit memory read operations.
Prototype
typedef
UINT16
(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ16) (
);
This
Address
TheMemRead16() function returns a 16-bit value from the memory space.
I-12.3.8.14 EFI_PEI_CPU_IO_PPI.MemRead32()
Summary
32-bit memory read operations.
Prototype
typedef
UINT32
(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ32) (
);
This
Address
TheMemRead32() function returns a 32-bit value from the memory space.
I-12.3. Optional Additional PPIs I-131UEFI Platform Initialization Specification, Release 1.8
I-12.3.8.15 EFI_PEI_CPU_IO_PPI.MemRead64()
Summary
64-bit memory read operations.
Prototype
typedef
UINT64
(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ64) (
);
This
Address
TheMemRead64() function returns a 64-bit value from the memory space.
I-12.3.8.16 EFI_PEI_CPU_IO_PPI.MemWrite8()
Summary
8-bit memory write operations.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE8) (
);
This
Address
I-12.3. Optional Additional PPIs I-132UEFI Platform Initialization Specification, Release 1.8
Data
TheMemWrite8() function writes an 8-bit value to the memory space.
I-12.3.8.17 EFI_PEI_CPU_IO_PPI.MemWrite16()
Summary
16-bit memory write operation.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE16) (
);
This
Address
Data
TheMemWrite16() function writes a 16-bit value to the memory space.
I-12.3.8.18 EFI_PEI_CPU_IO_PPI.MemWrite32()
Summary
32-bit memory write operation.
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE32) (
);
I-12.3. Optional Additional PPIs I-133UEFI Platform Initialization Specification, Release 1.8
This
Address
Data
TheMemWrite32() function writes a 32-bit value to the memory space.
I-12.3.8.19 EFI_PEI_CPU_IO_PPI.MemWrite64()
Summary
64-bit memory write operation.
Prototype
typedef
VOID
);
This
Address
Data
TheMemWrite64() function writes a 64-bit value to the memory space.
//
// Vector Handoff Info Attributes
//
#define EFI_VECTOR_HANDOFF_DO_NOT_HOOK 0x00000000
#define EFI_VECTOR_HANDOFF_HOOK_BEFORE 0x00000001
#define EFI_VECTOR_HANDOFF_HOOK_AFTER 0x00000002
#define EFI_VECTOR_HANDOFF_LAST_ENTRY 0x80000000
I-12.3. Optional Additional PPIs I-134UEFI Platform Initialization Specification, Release 1.8
I-12.3.9 EFI Pei Capsule PPI
I-12.3.9.1 EFI_PEI_CAPSULE_PPI (Optional)
Summary
This PPI is installed by some platform or chipset-specific PEIM that abstracts handling of UEFI Capsule processing.
GUID
#define EFI_PEI_CAPSULE_PPI_GUID \
{0x3acf33ee, 0xd892, 0x40f4, \
{0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d } }
typedef
struct \_EFI_PEI_CAPSULE_PPI {
EFI_PEI_CAPSULE_COALESCE Coalesce;
EFI_PEI_CAPSULE_CHECK_CAPSULE_UDPATE CheckCapsuleUpdate;
EFI_PEI_CAPSULE_CREATE_STATE CreateState;
} EFI_PEI_CAPSULE_PPI;
Coalesce
Upon determining that there is a capsule to operate on, this service will use a series of
EFI_CAPSULE_BLOCK_DESCRIPTOR entries to determine the current location of the various capsule frag-
ments and coalesce them into a contiguous region of system memory.
CheckCapsuleUpdate
Determine if a capsule needs to be processed. The means by which the presence of a capsule is determined is
platform specific. For example, an implementation could be driven by the presence of a Capsule EFI Variable
containing a list of EFI_CAPSULE_BLOCK_DESCRIPTOR entries. If present, return EFI_SUCCESS , otherwise
returnEFI_NOT_FOUND .
CreateState
The Capsule PPI service that gets called after memory is available. The capsule coalesce function, which must
be called first, returns a base address and size. Once the memory init PEIM has discovered memory, it should
call this function and pass in the base address and size returned by the Coalesce() function. Then this function
can create a capsule HOB and return.
This PPI provides several services in PEI to work with the underlying capsule capabilities of the platform. These
services include the ability for PEI to coalesce a capsule from a scattered set of memory locations into a contiguous
space in memory, detect if a capsule is present for processing, and once memory is available, create a HOB for the
capsule.
I-12.3. Optional Additional PPIs I-135UEFI Platform Initialization Specification, Release 1.8
I-12.3.9.2 EFI_PEI_CAPSULE_PPI.Coalesce
Summary
Coalesce the capsule
Prototype
typedef
(EFIAPI *EFI_PEI_CAPSULE_COALESCE)(
IN OUT VOID *MemoryBase,
IN OUT UINTN *MemSize
);
MemoryBase
Pointer to the base of a block of memory into which the buffers will be coalesced. On output, this variable will
hold the base address of a coalesced capsule.
MemorySize
EFI_CAPSULE_BLOCK_DESCRIPTOR entries to determine the current location of the various capsule fragments
and coalesce them into a contiguous region of system memory.
EFI_SUCCESS There was no capsule or the capsule was processed successfully

Summary
Prototype
typedef
);
EFI_NOT_FOUND If boot mode could not be determined or the boot mode is not flash
update or the capsule descriptors were not found
EFI_BUFFER_TOO_SMALL The capsule could not be coalesced in the provided memory region
I-12.3.9.3 EFI_PEI_CAPSULE_CHECK_CAPSULE_UDPATE.CheckCapsuleUpdate()
Summary
Check the Capsule Update.
Prototype
typedef
(EFIAPI *EFI_PEI_CAPSULE_CHECK_CAPSULE_UPDATE)(
IN EFI_PEI_SERVICES **PeiServices
);
I-12.3. Optional Additional PPIs I-136UEFI Platform Initialization Specification, Release 1.8
Determineifacapsuleneedstobeprocessed. Themeansbywhichthepresenceofacapsuleisdeterminedisplatform
specific. For example, an implementation could be driven by the presence of a Capsule EFI Variable containing a list
ofEFI_CAPSULE_BLOCK_DESCRIPTOR entries. Ifpresent,return EFI_SUCCESS ,otherwisereturn EFI_NOT_FOUND .
EFI_SUCCESS If a capsule is available.
EFI_NOT_FOUND No capsule detected.
I-12.3.9.4 EFI_PEI_CAPSULE_CHECK_CAPSULE_UDPATE.CapsuleCreateState()
Summary
Create the Capsule state.
Prototype
typedef
(EFIAPI *EFI_PEI_CAPSULE_CREATE_STATE)(
IN VOID *CapsuleBase,
IN UINTN CapsuleSize
);
CapsuleBase
Address returned by the capsule coalesce function.
CapsuleSize
Value returned by the capsule coalesce function.
The Capsule PPI service that gets called after memory is available. The capsule coalesce function, which must be
called first, returns a base address and size. Once the memory init PEIM has discovered memory, it should call this
function and pass in the base address and size returned by the Coalesce() function. Then this function can create a
capsule HOB and return.
EFI_VOLUME_CORRUPTED CapsuleBase does not appear to point to a coalesced capsule
EFI_SUCCESS Capsule HOB was created successfully
I-12.3. Optional Additional PPIs I-137UEFI Platform Initialization Specification, Release 1.8
I-12.3.9.5 EFI_PEI_MP_SERVICES_PPI (Optional)
Summary
This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support.
GUID
#define EFI_PEI_MP_SERVICES_PPI_GUID \
{ 0xee16160a, 0xe8be, 0x47a6, { 0x82, 0xa, 0xc6, 0x90, 0xd, 0xb0, 0x25, 0xa } }
typedef
struct _EFI_PEI_MP_SERVICES_PPI {
EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;
EFI_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;
EFI_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP;
EFI_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;
EFI_PEI_MP_SERVICES_WHOAMI WhoAmI;
} EFI_PEI_MP_SERVICES_PPI;
GetNumberOfProcessors
Discover the number of CPU’s
GetProcessorInfo
Ascertain information on the CPU’s.
StartupAllAPs
Startup all of the application processors.
StartupThisAP
Startup the specific application processor.
SwitchBSP
Switch the boot strap processor.
WhoAmI
Identify the currently executing processor.
When installed, the MP Services PPI produces a collection of services that are needed for MP management.
BeforethePIevent END_OF_PEI issignaled,themodulethatproducesthisprotocolisrequiredtoplaceallAPsintoan
idlestatewhenevertheAPsaredisabledortheAPsarenotexecutingcodeasrequestedthroughthe StartupAllAPs()
orStartupThisAP() services. TheidlestateofanAPbeforethePIevent END_OF_PEI issignaledisimplementation
dependent.
After the PI event END_OF_PEI is signaled, all the APs must be placed in the OS compatible CPU state as defined by
theUEFI Specification . Implementations of this Ppi may use the PI event END_OF_PEI to force APs into the OS
compatible state as defined by the UEFI Specification .
Thesupportfor SwitchBSP() andEnableDisableAP() maynolongerbesupportedafterthePEIevent END_OF_PEI
I-12.3. Optional Additional PPIs I-138UEFI Platform Initialization Specification, Release 1.8
I-12.3.9.6 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors()
Summary
Get the number of CPUs
Prototype
typedef
(EFIAPI *EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(
IN EFI_PEI_MP_SERVICES_PPI *This,
OUT UINTN *NumberOfProcessors,
OUT UINTN *NumberOfEnabledProcessors
);
This
Pointer to this instance of the PPI.
NumberOfProcessors
Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
NumberOfEnabledProcessors
Number of processors in the system that are enabled.
This service retrieves the number of logical processor in the platform and the number of those logical processors that
are enabled on this boot. This service may only be called from the BSP.
This function is used to retrieve the following information:
•The number of logical processors that are present in the system.
•The number of enabled logical processors in the system at the instant this call is made.
BecauseMPServicePPIprovidesservicestoenableanddisableprocessorsdynamically,thenumberofenabledlogical
processors may vary during the course of a boot session.
If this service is called from an AP, then EFI_DEVICE_ERROR is returned.
IfNumberOfProcessors orNumberOfEnabledProcessors isNULL,then EFI_INVALID_PARAMETER isreturned.
Otherwise, the total number of processors is returned in NumberOfProcessors , the number of currently enabled
processor is returned in NumberOfEnabledProcessors , andEFI_SUCCESS is returned.
EFI_SUCCESS Thenumberoflogicalprocessorsandenabledlogicalprocessorswas
retrieved
EFI_DEVICE_ERROR The calling processor is an AP
EFI_INVALID_PARAMETER NumberOfProcessors is NULL
EFI_INVALID_PARAMETER NumberOfEnabledProcessors is NULL
I-12.3. Optional Additional PPIs I-139UEFI Platform Initialization Specification, Release 1.8
I-12.3.9.7 EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo()
Summary
Get information on a specific CPU.
Prototype
typedef
(EFIAPI EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(
IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
);
This
A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
ProcessorNumber
The handle number of the processor.
ProcessorInfoBuffer
A pointer to the buffer where the processor information is stored.
GetsdetailedMP-relatedinformationontherequestedprocessorattheinstantthiscallismade. Thisservicemayonly
be called from the BSP.
This service retrieves detailed MP-related information about any processor on the platform. Note the following:
•The processor information may change during the course of a boot session.
•The information presented here is entirely MP related.
Information regarding the number of caches and their sizes, frequency of operation, slot numbers is all considered
platform-related information and is not provided by this service.
EFI_SUCCESS Processor information was returned
EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL
EFI_NOT_FOUND Theprocessorwiththehandlespecifiedby ProcessorNumber does
not exist in the platform
I-12.3. Optional Additional PPIs I-140UEFI Platform Initialization Specification, Release 1.8
I-12.3.9.8 EFI_PEI_MP_SERVICES_PPI.StartupAllAPs()
Summary
Activate all of the application proessors.
Prototype
typedef
(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_ALL_APS)(
IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread,
IN UINTN TimeoutInMicroSeconds,
IN VOID *ProcedureArgument OPTIONAL
);
This
Procedure
A pointer to the function to be run on enabled APs of the system. See type EFI_AP_PROCEDURE .
SingleThread
IfTRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order
of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure
simultaneously.
TimeoutInMicroseconds
Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero
means infinity. If the timeout expires before all APs return from Procedure , thenProcedure on the failed
APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.
StartupAllAPs() orEFI_PEI_MP_SERVICES_PPI.StartupThisAP() .
If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT .
ProcedureArgument
The parameter passed into Procedure for all APs.

This
Procedure
ThisserviceexecutesacallerprovidedfunctiononallenabledAPs. APscanruneithersimultaneouslyoroneatatime
in sequence. This service supports both blocking requests only. This service may only be called from the BSP.
This function is used to dispatch all the enabled APs to the function specified by Procedure . If any enabled AP is
busy, then EFI_NOT_READY is returned immediately and Procedure is not started on any AP.
IfSingleThread isTRUE, all the enabled APs execute the function specified by Procedure one by one, in ascend-
ing order of processor handle number. Otherwise, all the enabled APs execute the function specified by Procedure
Ifthetimeoutspecifiedby TimeoutInMicroseconds expiresbeforeallAPsreturnfrom Procedure ,thenProcedure
onthefailedAPsisterminated. AllenabledAPsarealwaysavailableforfurthercallsto EFI_PEI_MP_SERVICES_PPI.
I-12.3. Optional Additional PPIs I-141UEFI Platform Initialization Specification, Release 1.8
StartupAllAPs() andEFI_PEI_MP_SERVICES_PPI.StartupThisAP() . IfFailedCpuList isnotNULL,itscon-
tent points to the list of processor handle numbers in which Procedure was terminated.
Note: It is the responsibility of the consumer of the EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() to make sure
thatthenatureofthecodethatisexecutedontheBSPandthedispatchedAPsiswellcontrolled. TheMPServicesPpi
does not guarantee that the Procedure function is MP-safe. Hence, the tasks that can be run in parallel are limited to
certain independent tasks and well-controlled exclusive code. PEI services and Ppis may not be called by APs unless
otherwise specified.
In blocking execution mode, BSP waits until all APs finish or TimeoutInMicroSeconds expires.
EFI_SUCCESS In blocking mode all APs have finished before the timeout expired
EFI_DEVICE_ERROR Caller processor is AP
EFI_NOT_STARTED No enabled APs exist in the system
EFI_NOT_READY Any enabled APs are busy
EFI_TIMEOUT In blocking mode the timeout expired before all enabled APs have
finished
EFI_INVALID_PARAMETER Procedure is NULL
I-12.3.9.9 EFI_PEI_MP_SERVICES_PPI.StartupThisAP ()
Summary
Activate a specific application processor
Prototype
typedef
(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_THIS_AP)(
IN UINTN TimeoutInMicroseconds,
);
This
Procedure
The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total
numberoflogicalprocessorscanberetrievedby EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors() .
TimeoutInMicrosecsond
Indicates the time limit in microseconds for APs to return from Procedure , for blocking mode only. Zero
I-12.3. Optional Additional PPIs I-142UEFI Platform Initialization Specification, Release 1.8
ThisserviceletsthecallergetoneenabledAPtoexecuteacaller-providedfunction. ThecallercanrequesttheBSPto
wait for the completion of the AP. This service may only be called from the BSP.
This function is used to dispatch one enabled AP to the function specified by Procedure passing in the argument
specified by ProcedureArgument .
The execution is in blocking mode. The BSP waits until the AP finishes or TimeoutInMicroSecondss expires.
Ifthetimeoutspecifiedby TimeoutInMicroseconds expiresbeforetheAPreturnsfrom Procedure ,thenexecution
ofProcedure by the AP is terminated. The AP is available for subsequent calls to EFI_PEI_MP_SERVICES_PPI.
StartupAllAPs() andEFI_PEI_MP_SERVICES_PPI.StartupThisAP() .
EFI_SUCCESS In blocking mode specified AP finished before the timeout expires
EFI_TIMEOUT In blocking mode the timeout expired before the specified AP has
finished
not exist
EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or a disabled AP
I-12.3.9.10 EFI_PEI_MP_SERVICES_PPI.SwitchBSP ()
Summary
Switch the boot strap processor
Prototype
typedef
(EFIAPI *EFI_PEI_MP_SERVICES_SWITCH_BSP)(
IN UINTN *ProcessorNumber,
IN BOOLEAN *EnableOldBSP
);
This
The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical
I-12.3. Optional Additional PPIs I-143UEFI Platform Initialization Specification, Release 1.8
processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.
GetNumberOfProcessors() .
EnableOldBSP
IfTRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
This service switches the requested AP to be the BSP from that point onward.
This service changes the BSP for all purposes.This call can only be performed by the current BSP.
This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all
purposes. The new BSP can take over the execution of the old BSP and continue seamlessly from where the old one
left off.
If the BSP cannot be switched prior to the return from this service, then EFI_UNSUPPORTED must be returned.
EFI_SUCCESS BSP successfully switched
EFI_UNSUPPORTED SwitchingtheBSPcannotbecompletedpriortothisservicereturn-
ing
EFI_UNSUPPORTED Switching the BSP is not supported
not exist
EFI_NOT_READY The specified AP is busy
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_MP_SERVICES_ENABLEDISABLEAP)(
IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL
);
This
EnableAP
Specifies the new state for the processor for enabled, FALSE for disabled.
I-12.3. Optional Additional PPIs I-144UEFI Platform Initialization Specification, Release 1.8
HealthFlag
If not NULL, a pointer to a value that specifies the new health status of the AP. This flag cor-
responds to StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo() . Only the
PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
This service lets the caller enable or disable an AP from this point onward.
This service may only be called from the BSP.
This service allows the caller enable or disable an AP from this point onward. The caller can optionally specify the
health status of the AP by Health. If an AP is being disabled, then the state of the disabled AP is implementation
dependent. If an AP is enabled, then the implementation must guarantee that a complete initialization sequence is
performed on the AP, so the AP is in a state that is compatible with an MP operating system.
IftheenableordisableAPoperationcannotbecompletedpriortothereturnfromthisservice,then EFI_UNSUPPORTED
must be returned.
EFI_SUCCESS The specified AP was enabled or disabled successfully
EFI_UNSUPPORTED Enabling or disabling an AP cannot be completed prior to this ser-
vice returning
EFI_UNSUPPORTED Enabling or disabling an AP is not supported
EFI_NOT_FOUND Processorwiththehandlespecifiedby ProcessorNumber doesnot
exist
EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP
I-12.3.9.11 EFI_PEI_MP_SERVICES_PPI.WhoAmI ()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_MP_SERVICES_WHOAMI)(

exist
Summary
Prototype
typedef
OUT UINTN *ProcessorNumber
);
This
I-12.3. Optional Additional PPIs I-145UEFI Platform Initialization Specification, Release 1.8
This services returns the handle number for the calling processor. This service may be called from the BSP and APs.
This service returns the processor handle number for the calling processor.
The returned value is in the range from 0 to the total number of logical processors minus 1. The total number of
logical processors can be retrieved with EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors() . This service
may be called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER is returned.
Otherwise, the current processors handle number is returned in ProcessorNumber , andEFI_SUCCESS is returned.
EFI_SUCCESS The current processor handle number was returned in
EFI_INVALID_PARAMETER ProcessorNumber is NULL
I-12.3.9.12 EDKII_PEI_MP_SERVICES2_PPI (Optional)
Summary
GUID
#define EDKII_PEI_MP_SERVICES2_PPI_GUID \
{ 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0xb9, 0xba, 0xcf, 0xba } }
typedef
struct _EDKII_PEI_MP_SERVICES2_PPI {
EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;
EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;
EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;
EDKII_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP;
EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;
EDKII_PEI_MP_SERVICES_WHOAMI WhoAmI;
EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS StartupAllCPUs;
} EDKII_PEI_MP_SERVICES2_PPI;
SwitchBSP
I-12.3. Optional Additional PPIs I-146UEFI Platform Initialization Specification, Release 1.8
WhoAmI
StartupAllCPUs
I-12.3.9.13 EDKII_PEI_MP_SERVICES2_PPI.GetNumberOfProcessors()
Summary
Prototype
typedef
(EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(
IN EDKII_PEI_MP_SERVICES2_PPI *This,
);
This
I-12.3. Optional Additional PPIs I-147UEFI Platform Initialization Specification, Release 1.8
retrieved
I-12.3.9.14 EDKII_PEI_MP_SERVICES2_PPI.GetProcessorInfo()
Summary
Prototype
typedef
(EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(
);
This
A pointer to the EDKII_PEI_MP_SERVICES2_PPI instance.
I-12.3. Optional Additional PPIs I-148UEFI Platform Initialization Specification, Release 1.8
I-12.3.9.15 EDKII_PEI_MP_SERVICES2_PPI.StartupAllAPs()
Summary
Prototype
typedef
(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS)(
);
This
Procedure
IndicatesthetimelimitinmicrosecondsforAPstoreturnfromProcedure,forblockingmodeonly. Zeromeans
infinity. If the timeout expires before all APs return from Procedure , thenProcedure on the failed APs is
terminated. All enabled APs are available for next function assigned by EDKII_PEI_MP_SERVICES2_PPI.
StartupAllAPs() orEDKII_PEI_MP_SERVICES2_PPI.StartupThisAP() .
I-12.3. Optional Additional PPIs I-149UEFI Platform Initialization Specification, Release 1.8
If the timeout specified by TimeoutInMicroseconds expires before all APs return from Procedure , then
Procedure on the failed APs is terminated. All enabled APs are always available for further calls to
EDKII_PEI_MP_SERVICES2_PPI.StartupAllAPs() andEDKII_PEI_MP_SERVICES2_PPI.StartupThisAP() .

IfFailedCpuList is not NULL, its content points to the list of processor handle numbers in which Procedure
was terminated.
Note: It is the responsibility of the consumer of the EDKII_PEI_MP_SERVICES2_PPI.StartupAllAPs() to make
surethatthenatureofthecodethatisexecutedontheBSPandthedispatchedAPsiswellcontrolled. TheMPServices
Ppidoesnotguaranteethatthe Procedure functionisMP-safe. Hence,thetasksthatcanberuninparallelarelimited
tocertainindependenttasksandwell-controlledexclusivecode. PEIservicesandPpismaynotbecalledbyAPsunless
finished
I-12.3.9.16 EDKII_PEI_MP_SERVICES2_PPI.StartupThisAP ()
Summary
Prototype
typedef
(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP)(
);
This
Procedure
The handle number of the AP. The range is from 0 to the total number of logical processors mi-
I-12.3. Optional Additional PPIs I-150UEFI Platform Initialization Specification, Release 1.8
nus 1. The total number of logical processors can be retrieved by EDKII_PEI_MP_SERVICES2_PPI.
meansinfinity. IfthetimeoutexpiresbeforeallAPsreturnfrom Procedure ,thenProcedure onthefailedAPs
is terminated. All enabled APs are available for next function assigned by EDKII_PEI_MP_SERVICES2_PPI.
ofProcedure bytheAPisterminated. TheAPisavailableforsubsequentcallsto EDKII_PEI_MP_SERVICES2_PPI.
StartupAllAPs() andEDKII_PEI_MP_SERVICES2_PPI.StartupThisAP() .
finished
not exist
I-12.3.9.17 EDKII_PEI_MP_SERVICES2_PPI.SwitchBSP ()
Summary
Prototype
typedef
(EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP)(
IN BOOLEAN EnableOldBSP
);
This
I-12.3. Optional Additional PPIs I-151UEFI Platform Initialization Specification, Release 1.8
ThehandlenumberofAPthatistobecomethenewBSP.Therangeisfrom0tothetotalnumberoflogicalpro-
cessorsminus1. Thetotalnumberoflogicalprocessorscanberetrievedby EDKII_PEI_MP_SERVICES2_PPI.
left off.
ing
not exist
Summary
Prototype
typedef
(EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP)(
);
This
EnableAP
I-12.3. Optional Additional PPIs I-152UEFI Platform Initialization Specification, Release 1.8
If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corre-
sponds to StatusFlag defined in EDKII_PEI_MP_SERVICES2_PPI.GetProcessorInfo() . Only the
exist
I-12.3.9.18 EDKII_PEI_MP_SERVICES2_PPI.WhoAmI ()
Summary
Prototype
typedef
(EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI)(
);
This
I-12.3. Optional Additional PPIs I-153UEFI Platform Initialization Specification, Release 1.8
The returned value is in the range from 0 to the total number of logical processors minus 1. The total number of log-
ical processors can be retrieved with EDKII_PEI_MP_SERVICES2_PPI.GetNumberOfProcessors() . This service
I-12.3.9.19 EDKII_PEI_MP_SERVICES2_PPI.StartupAllCPUs ()
Summary
This service executes a caller provided function on all enabled CPUs.
Prototype
typedef

Summary
Prototype
typedef
);
This
A pointer to the EDKII_PEI_MP_SERVICES2_PPI instance
Procedure
A pointer to the function to be run on enabled APs of the system. See type EFI_AP_PROCEDURE.
infinity.
If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT..
This function is used to dispatch all the enabled CPUs to the function specified by Procedure. If any enabled CPU is
If the timeout specified by TimeoutInMicroseconds expires before all APs return from Procedure, then Pro-
cedure on the failed APs is terminated. All enabled APs are always available for further calls to ED-
KII_PEI_MP_SERVICES2_PPI.StartupAllAPs()andEDKII_PEI_MP_SERVICES2_PPI.StartupThisAP(). IfFailed-
CpuList is not NULL, its content points to the list of processor handle numbers in which Procedure was terminated.
I-12.3. Optional Additional PPIs I-154UEFI Platform Initialization Specification, Release 1.8
Inblockingexecutionmode,BSPwaitsuntilallAPsfinishorTimeoutInMicroSecondsexpires. Innon-blockingmode,
the function has been dispatched to all enabled CPUs.
EFI_SUCCESS Inblockingmode,allCPUshavefinishedbeforethetimeoutexpired.
EFI_SUCCESS In non-blocking mode, function has been dispatched to all enabled
CPUs.
EFI_DEVICE_ERROR Caller processor is AP.
EFI_NOT_STARTED No enabled APs exist in the system.
EFI_NOT_READY Any enabled APs are busy.
EFI_TIMEOUT In blocking mode, the timeout expired before all enabled APs have
finished.
EFI_INVALID_PARAMETER Procedure is NULL.
I-12.4 Graphics PEIM Interfaces
There is one PEI to PEI Interfaces (PPI) that is required to provide graphics functionality in the PEI phase.
ThePeiGraphicsPpi is the PPI produced by the Graphics PEI Module and provides interfaces to the platform code
to complete the basic initialization of the graphics subsystem to enable console output.
I-12.4.1 Pei Graphics PPI
ThePeiGraphicsPpi isthemaininterfaceexposedbytheGraphicsPEIMtobeusedbytheotherfirmwaremodules.
The following sections cover the individual APIs in detail.
GUID
#define EFI_PEI_GRAPHICS_PPI_GUID \
{ 0x6ecd1463, 0x4a4a, 0x461b,
{0xaf, 0x5f, 0x5a, 0x33, 0xe3, 0xb2, 0x16, 0x2b }};
Prototype
struct \_EFI_PEI_GRAPHICS_PPI {
EFI_PEI_GRAPHICS_INIT GraphicsPpiInit;
EFI_PEI_GRAPHICS_GET_MODE GraphicsPpiGetMode;
} EFI_PEI_GRAPHICS_PPI;
I-12.4.2 GraphicsPpiInit
TheGraphicsPpiInit initializes the graphics subsystem in phases.
Calling Condition
There are certain conditions to be met before the GraphicsPpiInit can be called; Memory has been initialized.
Prototype
I-12.4. Graphics PEIM Interfaces I-155UEFI Platform Initialization Specification, Release 1.8
typedef
(EFIAPI *EFI_PEI_GRAPHICS_INIT) (
IN VOID *GraphicsPolicyPtr;
);
GraphicsPolicyPtr
GraphicsPolicyPtr points to a configuration data block of policy settings required by Graphics PEIM.
Return
EFI_SUCCESS The invocation was successful.
EFI_INVALID_PARAMETER The phase parameter is not valid.
EFI_NOT_ABORTED The stages were not called in the proper order
EFI_NOT_FOUND ThePeiGraphicsPlatformPolicyPpi is not located
EFI_DEVICE_ERROR The initialization failed due to device error
EFI_NOT_READY The previous init stage is still in progress and not ready for the cur-
rentinitializationphaseyet. Theplatformcodeshouldcallthisagain
sometime later.
I-12.4.3 GraphicsPpiGetMode
TheGraphicsPpiGetMode returns the mode information supported by the Graphics PEI Module.
The frame buffer abstracts the video display as an array of pixels. Each pixels location on the video display is defined
defined as (0, 0) where the notation (X, Y) represents the X and Y coordinate of the pixel. The lower right corner of
Apixeliscomprisedofa32-bitquantity. ThefirstthreebytesforeachpixelrepresentstheintensityforRed,Blueand
Green colors. The fourth byte is reserved and must be zero. The byte values for the red, green, and blue components
represent the color intensity. This color intensity value range from a minimum intensity of 0 to maximum intensity of
255.
ThemodeinformationreturnedbythisPPIissimilartotheGOP’s EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE
Prototype
typedef
(EFIAPI *EFI_PEI_GRAPHICS_GET_MODE) (
IN OUT EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode
);
Mode
Pointer to EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE data. Type EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE is
defined in the UEFI Specification and in “Related Definitions” below.
I-12.4. Graphics PEIM Interfaces I-156UEFI Platform Initialization Specification, Release 1.8
Fig. 12.1: Mode Information Supported By Graphics PEI Module
Return
EFI_SUCCESS Valid mode information was returned
EFI_INVALID_PARAMETER TheModeparameter is not valid.
EFI_DEVICE_ERROR A hardware error occured trying to retrieve the video mode
EFI_NOT_READY TheGraphicsInitializationisnotcompete,andModeinformationis
not yet available.The platform code should call this again after the
Graphics initialization is done.
I-12.4.3.1 Related Definition - EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE
MaxMode
The number of modes that is supported by this module.
Mode
Current mode of the graphics device. If the MaxMode is 1, then this field will be 0.
Info
Pointer to EFI_GRAPHICS_OUTPUT_MODE_INFORMATION data. See Related Definition below.
SizeOfInfo
Size of the Infostructure in bytes.
I-12.4. Graphics PEIM Interfaces I-157UEFI Platform Initialization Specification, Release 1.8
FrameBufferBase
Base address of graphics linear frame buffer. Infocontains information required to allow software to draw
directly to the frame buffer.
FrameBufferSize
Size of the frame buffer represented by FrameBufferBase in bytes.
I-12.4.3.2 Related Definition - EFI_GRAPHICS_OUTPUT_MODE_INFORMATION
Version
Theversionofthisdatastructure. Avalueofzerorepresentsthestructureasdefinedinthisspecification. Future
versionofthisspecificationmayextendthisdatastructureinabackwardscompatiblewayandincreasethevalue
of Version.
HorizontalResolution
The size of video screen in pixels in the X dimension.
VerticalResolution
The size of video screen in pixels in the Y dimension.
PixelFormat
Enumerationthatdefinesthephysicalformatofthepixel. Avalueof PixelBltOnly impliesthatalinearframe
buffer is not available for this mode.
PixelInformation
This bit-mask is only valid if PixelFormat is set toPixelPixelBitMask . A bit being set defines what bits
are used for what purpose such as Red, Green, Blue, or Reserved.
PixelsPerScanLine
Defines the number of pixel elements per video memory line. For performance reasons, or due to hardware
restrictions, scan lines may be padded to an amount of memory alignment. These padding pixel elements are
outside the area covered by HorizontalResolution and are not visible. For direct frame buffer access, this
numberisusedasaspanbetweenstartsofpixellinesinvideomemory. Basedonthesizeofanindividualpixel
element and PixelsPerScanline , the offset in video memory from pixel element (x, y) to pixel element (x,
y+1) has tobe calculated as “sizeof( PixelElement)* PixelsPerScanLine “, not ”sizeof( PixelElement )*
HorizontalResolution “, though in many cases those values can coincide. This value can depend on video
hardware and mode resolution.
I-12.4. Graphics PEIM Interfaces I-158UEFI Platform Initialization Specification, Release 1.8
I-12.4.3.3 Related Definition - EFI_GRAPHICS_OUTPUT_MODE_INFORMATION
PixelRedGreenBlueReserved8BitPerColor
A pixel is 32-bits and byte zero represents red, byte one represents green, byte two represents blue, and byte
three is reserved. This is the definition for the physical frame buffer. The byte values for the red, green, and
blue components represent the color intensity. This color intensity value range from a minimum intensity of 0

to maximum intensity of 255.
PixelBlueGreenRedReserved8BitPerColor
A pixel is 32-bits and byte zero represents blue, byte one represents green, byte two represents red, and byte
PixelBitMask
The pixel definition of the physical frame buffer is defined by EFI_PIXEL_BITMASK
PixelBltOnly
This mode does not support a physical frame buffer.
I-12.4.3.4 Related Definition - EFI_PIXEL_BITMASK
If a bit is set in RedMask ,GreenMask , orBlueMask then those bits of the pixel represent the corresponding color.
Bits inRedMask ,GreenMask ,BlueMask , andReserveredMask must not overlap bit positions. The values for the
red, green, and blue components in the bit mask represent the color intensity. The color intensities must increase as
thecolorvaluesforeachcolormaskincreasewithaminimumintensityofallbitsinacolormaskcleartoamaximum
intensity of all bits in a color mask set.
I-12.4.4 EFI PEI Graphics INFO HOB
I-12.4.4.1 EFI_PEI_GRAPHICS_INFO_HOB
#define EFI_PEI_GRAPHICS_INFO_HOB_GUID \
{ 0x39f62cce, 0x6825, 0x4669,\
{ 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 }}
I-12.4. Graphics PEIM Interfaces I-159UEFI Platform Initialization Specification, Release 1.8
UINT32 FrameBufferSize;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;
} EFI_PEI_GRAPHICS_INFO_HOB;
I-12.4.4.2 EFI_PEI_GRAPHICS_DEVICE_INFO_HOB
#define EFI_PEI_GRAPHICS_DEVICE_INFO_HOB_GUID \
{ 0xe5cb2ac9, 0xd35d, 0x4430,\
{ 0x93, 0x6e, 0x1d, 0xe3, 0x32, 0x47, 0x8d, 0xe7 }}
UINT16 VendorId
UINT16 DeviceId
UINT16 SubsystemVendorId
UINT16 SubsystemId;
UINT8 RevisionId;
UINT8 BarIndex;
} EFI_PEI_GRAPHICS_DEVICE_INFO_HOB;
When graphics capability is included in PEI, it may optionally provide a splash screen capability as well.
When graphics capability is included in PEI, it produces a EFI_PEI_GRAPHICS_INFO_HOB which
provides information about the graphics mode and the framebuffer, and may optionally produce a
EFI_PEI_GRAPHICS_DEVICE_INFO_HOB which provides information about the graphics device charac-
teristics. The EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure is defined in the UEFI specification. This
informationcanbeusedbytheHOB-consumerphase,suchasDXE,toprovidedisplaysupportofitsown,orelidethe
need to do graphics initialization again in the UEFI GOP driver, for example.
ItistobenotedthatthePEIphasemayprogramatemporaryframebufferaddresstocompleteitsinitializationandthe
framebuffer address at the time of building the EFI_PEI_GRAPHICS_INFO_HOB will reflect the current assignment.
The post-PEI phase consuming this HOB should be aware that a generic PCI enumeration logic could reprogram the
temporary resources assigned by the PEI phase and it is the responsibility of the post-PEI phase to update its internal
data structures with the new framebuffer address after the enumeration is complete.
The EFI_PEI_GRAPHICS_DEVICE_INFO_HOB is optional. When it exists, the DXE module which provides dis-
play support uses the VendorId, DeviceId, RevisionId, SubsystemVendorId, and SubsystemDeviceId in the HOB to
match the graphics device. It’s useful when system has multiple graphics devices and the DXE module cannot know
whichonetomanagewithouttheinformationprovidedbythisHOB.If VendorId,DeviceId,SubsystemVendorId or
SubsystemDeviceId issettoMAX_UINT16,orRevisionIdissettoMAX_UINT8,thatfieldwillbeignored. TheID
values that are assigned to other values will be used to identify the graphics device. The BarIndex tells DXE module
whichPCIMMIOBARisusedtoholdtheframebuffer. BAR0isusedifthe BarIndex issettoMAX_UINT8orthe
HOB doesn’t exist.
I-12.4. Graphics PEIM Interfaces I-160CHAPTER
THIRTEEN
PEI TO DXE HANDOFF
I-13.1 Introduction
The PEI phase of the system firmware boot process performs rudimentary initialization of the system to meet specific
minimum system state requirements of the DXE Foundation. The PEI Foundation must have a mechanism of locating
and passing off control of the system to the DXE Foundation. PEI must also provide a mechanism for components
of DXE and the DXE Foundation to discover the state of the system when the DXE Foundation is invoked. Certain
aspects of the system state at handoff are architectural, while other system state information may vary and hence must
be described to DXE components.
I-13.2 Discovery and Dispatch of the DXE Foundation
The PEI Foundation uses a special PPI named the DXE Initial Program Load (IPL) PPI to discover and dispatch the
DXE Foundation and components that are needed to run the DXE Foundation The final action of the PEI Foundation
is to locate and pass control to the DXE IPL PPI. To accomplish this, the PEI Foundation scans all PPIs by GUID for
the GUID matching the DXE IPL PPI. The GUID for this PPI is defined in EFI_DXE_IPL_PPI .
I-13.3 Passing the Hand-Off Block (HOB) List
The DXE IPL PPI passes the Hand-Off Block (HOB) list from PEI to the DXE Foundation when it invokes the DXE
Foundation. The handoff state is described in the form of HOBs in the HOB list. The HOB list must contain at least
the HOBs listed in Required HOB Types in the HOB List .
I-161UEFI Platform Initialization Specification, Release 1.8
Table 13.1: Required HOB Types in the HOB List
Required HOB Type Usage
Phase Handoff Information Table PHIT HOB This HOB is required
One or more Resource Descriptor HOB s describing
physical system memoryTheDXEFoundationwillusethisphysicalsystemmem-
ory for DXE
Boot strap processor BSP Stack HOB The DXE Foundation needs to know the current stack
location so that it can move it if necessary based upon
its desired memory address map This HOB will be of
type EfiConventionalMemory
BSP BSPStore Backing Store Pointer Store HOB Note
Itanium processor family onlyThe DXE Foundation needs to know the current store
its desired memory address map
firmware devicesThe DXE Foundation will place this into the GCD
One or more Firmware Volume HOB s The DXE Foundation needs this information to begin
loading other drivers in the platform
A Memory Allocation Module HOB This HOB tells the DXE Foundation where it is when
allocating memory into the initial system address map
The above HOB types are defined in volume 3 of this specification.
I-13.4 Handoff Processor State to the DXE IPL PPI
Handoff Processor State to the DXE IPL PPI defines the state that processors must be in at handoff to the DXE IPL
PPI, for the following processors:
•IA-32 processors
•Itanium processor family
•Intel®processors using Intel ®XScale ™technology
Table 13.2: Handoff Processor State to the DXE IPL PPI
Processor State at Handoff
IA 32 In 32 bit flat mode
Itanium In Itanium processor family physical mode
Intel XScale In SuperVisor Mode with a one to one virtual to physical mapping if there
is a memory management unit MMU in the system
I-13.4. Handoff Processor State to the DXE IPL PPI I-162CHAPTER
FOURTEEN
BOOT PATHS
I-14.1 Introduction
The PEI Foundation is unaware of the boot path required by the system. It relies on the PEIMs to determine the boot
mode (e.g. R0, R1, S3, etc.) and take appropriate action depending on the mode.
To implement this, each PEIM has the ability to manipulate the boot mode using the PEI Service SetBootMode()
described in Services - PEI.
The PEIM does not change the order in which PEIMs are dispatched depending on the boot mode.
I-14.2 Code Flow
The normal code flow in PI firmware passes through a succession of phases, in the following order:
1. SEC
2. PEI
3. DXE
4. BDS
5. Runtime
6. Afterlife
This section describes alternatives to this ordering.
I-14.2.1 Reset Boot Paths
The following sections describe the boot paths that are followed when a system encounters several different types of
reset.
I-163UEFI Platform Initialization Specification, Release 1.8
I-14.2.1.1 Intel Itanium Processor Reset
ItaniumarchitecturecontainsenoughhookstoauthenticatePAL-AandPAL-Bcodethatisdistributedbytheprocessor
vendor. The internal microcode on the processor silicon, which starts up on a PowerGood reset, finds the first layer of
processor abstraction code (called PAL-A) that is located in the boot firmware volume (BFV), or the volume that has
SEC and the PEI core, using architecturally defined pointers in the BFV. It is the responsibility of this microcode to
authenticate that the PAL-A code layer from the processor vendor has not been tampered. If the authentication of the
PAL-A layer passes, control then passes to the PAL-A layer, which then authenticates the next layer of processor ab-

reset.
stractioncode(calledPAL-B)beforepassingcontroltoit. Inadditiontothismicroarchitecture-specificauthentication,
the SEC phase of UEFI is still responsible for locating the PEI Foundation and verifying its authenticity.
In an Itanium-based system, it is also imperative that the firmware modules in the BFV be organized such that at least
the PAL-A is contained in the fault-tolerant regions. This processor-specific PAL-A authenticates the PAL-B code,
which usually is contained in the non-fault-tolerant regions of the firmware system. The PAL A and PAL B binary
componentsarealwaysvisibletoalltheprocessorsinanodeatthetimeofpower-on;thesystemfabricshouldnotneed
to be initialized.
I-14.2.1.2 Non-Power-on Resets
Non-power-on resets can occur for many reasons. There are PEI and DXE system services that reset and reboot the
entire platform, including all processors and devices. It is important to have a standard variant of this boot path for
cases such as the following:
•Responding to an exception from a catastrophic error
This reset is also used for Configuration Values Driven through Reset (CVDR) configuration.
I-14.3 Normal Boot Paths
A traditional BIOS executes POST from a cold boot (G3 to S0 state), on resumes, or in special cases like INIT. UEFI
covers all those cases but provides a richer and more standardized operating environment.
The basic code flow of the system needs to be changeable due to different circumstances. The boot path variable
satisfies this need. The initial value of the boot mode is defined by some early PEIMs, but it can be altered by other,
later PEIM(s). All systems must support a basic S0 boot path. Typically a system has a more rich set of boot paths,
including S0 variations, S-state boot paths, and one or more special boot paths.
The architecture for multiple boot paths presented here has several benefits, as follows:
•The PEI Foundation is not required to be aware of system-specific requirements such as MP and various power
states. This lack of awareness allows for scalability and headroom for future expansion.
•Supporting the various paths only minimally impacts the size of the PEI Foundation.
•The PEIMs that are required to support the paths scale with the complexity of the system.
Note that the Boot Mode Register becomes a variable upon transition to the DXE phase. The DXE phase can have
additional modifiers that affect the boot path more than the PEI phase.
Theseadditionalmodifierscanindicateifthesystemisinmanufacturingmode,chassisintrusion,orACpowerlossor
if silent boot is enabled.
I-14.3. Normal Boot Paths I-164UEFI Platform Initialization Specification, Release 1.8
I-14.3.1 Basic G0-to-S0 and S0 Variation Boot Paths
ThebasicS0bootpathis“bootwithfullconfiguration.”ThispathsettinginformsallPEIMstodoafullconfiguration.
The basic S0 boot path must be supported.
The Framework architecture also defines several optional variations to the basic S0 boot path. The variations that are
supported depend on the following:
•Richness of supported features
•If the platform is open or closed
•Platform hardware
For example, a closed system or one that has detected a chassis intrusion could support a boot path that assumes no
configuration changes from last boot option, thus allowing a very rapid boot time.
Unsupported variations default to basic S0 operation. The following are the defined variations to the basic boot path:
•Boot with minimal configuration: This path is for configuring the minimal amount of hardware to boot the
system.
•Boot assuming no configuration changes: This path uses the last configuration data.
•Boot with full configuration plus diagnostics: This path also causes any diagnostics to be executed.
•Boot with default settings: This path uses a known set of safe values for programming hardware.
I-14.3.2 S-State Boot Paths
The following optional boot paths allow for different operation for a resume from S3, S4, and S5:
•S3(SavetoRAMResume): PlatformsthatsupportS3resumemusttakespecialcaretopreserve/restorememory
and critical hardware.
•S4 (Save to Disk): Some platforms may want to perform an abbreviated PEI and DXE phase on a S4 resume.
•S5 (Soft Off): Some platforms may want an S5 system state boot to be differentiated from a normal boot – for
example, if buttons other than the power button can wake the system.
An S3 resume needs to be explained in more detail because it requires cooperation between a G0-to-S0 boot path and
anS3resumebootpath. TheG0-to-S0bootpathneedstosavehardwareprogramminginformationthattheS3resume
path needs to retrieve.
ThisinformationissavedintheHardwareSaveTableusingpredefineddatastructurestoperformI/Oormemorywrites.
The data is stored in an UEFI equivalent of the INT15 E820 type 4 (firmware reserved memory) area or a firmware
device area that is reserved for use by UEFI. The S3 resume boot path code can access this region after memory has
been restored.
I-14.4 Recovery Paths
All of the above boot paths can be modified or aborted if the system detects that recovery is needed. Recovery is the
processofreconstitutingasystem’sfirmwaredeviceswhentheyhavebecomecorrupted. Thecorruptioncanbecaused
by various mechanisms. Most firmware volumes on nonvolatile storage devices (flash, disk) are managed as blocks.
If the system loses power while a block, or semantically bound blocks, are being updated, the storage might become
invalid. Ontheotherhand,thedevicemightbecomecorruptedbyanerrantprogramorbyerranthardware. Thesystem
designersmustdeterminethelevelofsupportforrecoverybasedontheirperceptionsoftheprobabilitiesoftheseevents
occurring and their consequences.
I-14.4. Recovery Paths I-165UEFI Platform Initialization Specification, Release 1.8
The following are some reasons why system designers may choose to not support recovery:
•A system’s firmware volume storage media might not support modification after being manufactured. It might
be the functional equivalent of a ROM.
•Most mechanisms of implementing recovery require additional firmware volume space, which might be too
expensive for a particular application.
•Asystemmayhaveenoughfirmwarevolumespaceandhardwarefeaturesthatthefirmwarevolumecanbemade
sufficiently fault tolerant to make recovery unnecessary.
I-14.4.1 Discovery
Discovering that recovery is done using a PEIM (for example, by checking a “force recovery” jumper).
I-14.4.2 General Recovery Architecture
Theconceptbehindrecoveryistopreserveenoughofthesystemfirmwaresothatthesystemcanboottoapointwhere
it can do the following:
•Read a copy of the data that was lost from chosen peripherals.
•Reprogram the firmware volume with that data.
Preserving the recovery firmware is a function of the way the firmware volume store is managed, which is generally
beyond the scope of this document.
ThePIrecoveryarchitectureallowsforoneormanyPEIMstobebuilttohandletheportionoftherecoverythatwould
initialize the recovery peripherals (and the busesthey reside on) and then to read the new images from the peripherals
and update the firmware volumes.
ItisconsideredfarmorelikelythatthePEIwilltransitiontoDXEbecauseDXEisdesignedtohandleaccesstoperiph-
erals. This transition has the additional benefit that, if DXE then discovers that a device has become corrupted, it may
institute recovery without transferring control back to the PEI.
I-14.5 Defined Boot Modes
The list of possible boot modes is described in the GetBootMode() function description. PI architecture specifically
doesnotdefineanupgradepathifnewbootmodesaredefined. Thisisnecessaryasthenatureofthoseadditionalboot
modes may work in conjunction with or may conflict with the previously defined boot modes.
I-14.6 Priority of Boot Paths
Within a given PEIM, the priority ordering of the sources of boot mode should be as follows (from highest priority to
lowest):
1.BOOT_IN_RECOVERY_MODE
2.BOOT_ON_FLASH_UPDATE
3.BOOT_ON_S3_RESUME
4.BOOT_WITH_MINIMAL_CONFIGURATION
5.BOOT_WITH_FULL_CONFIGURATION
I-14.5. Defined Boot Modes I-166UEFI Platform Initialization Specification, Release 1.8
6.BOOT_ASSUMING_NO_CONFIGURATION_CHANGES
7.BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS
8.BOOT_WITH_DEFAULT_SETTINGS
9.BOOT_ON_S4_RESUME
10.BOOT_ON_S5_RESUME
11.BOOT_ON_S2_RESUME
The boot modes listed above are defined in the PEI Service SetBootMode() .
I-14.7 Assumptions
Boot Path Assumptions lists the assumptions that can be made about the system for each sleep state.
Table 14.1: Boot Path Assumptions
System State Description Assumptions
R0 Cold Boot Cannot assume that the previously stored configuration
data is valid.
R1 Warm Boot May assume that the perviously stored configuration
S3 ACPI Save to RAM Resume The previously stored configuratio data is valid and
RAM is valid. RAM configuration must be restored
from nonvolatile storage (NVS) before RAM may be
used. The firmware may only modify previously re-
served RAM. There are two types of reserved memory.

OneistheequivalentoftheBIOSINT15h,E820type-4
memory and indicates that the RAM is reserved for use
bythefirmware. Thesuggestionistoaddanothertypeof
memory that allows the OS to corrupt the memory dur-
ing runtime but that may be overwritten during resume.
S4, | S5 Save to Disk Resume, | “Soft
Off”S$ and S% are identical from a PEIM’s point of view.
The two are distinguished to support follow-on phases.
The entire system must be reinitialized but the PEIMs
mayassumethatthepreviousconfigurationisstillvalid.
Boot on Flash Up-
dateThisbootmodecanbeeitheranINIT,S3,orothermeans
bywhichtorestartthemachine. IfitisanS3,forexam-
ple,theflashupdatecausewillsupersedetheS3restart.
It is incumbent upon platform code, such as the Mem-
oryInitializationPEIM,todeterminetheexactcauseand
performcorrectbehavior(i.e.,S3staterestorationversus
INIT behavior).
Boot with Manufac-
turingModesettingsPEIM’s and/or DXE drivers may parameterize based
upon actions that should only occur in the factory or a
manufacturer approved setting.
I-14.7. Assumptions I-167UEFI Platform Initialization Specification, Release 1.8
I-14.8 Architectural Boot Mode PPIs
There is a possible hierarchy of boot mode PPIs that abstracts the various producers of this variable. It is a hierarchy
in that there should be an order of precedence in which each mode can be set. The PPIs and their respective GUIDs
aredescribedin RequiredArchitecturalPPIs andOptionalArchitecturalPPIs . ThehierarchyincludesthemasterPPI,
whichpublishesaPPIthatwillbedependeduponbytheappropriatePEIMs,andsomesubsidiaryPPI.ForPEIMsthat
require that the boot mode is finally known, the Master Boot Mode PPI can be used as a dependency. Architectural
Boot Mode PPIs lists the architectural boot mode PPIs.
Table 14.2: Architectural Boot Mode PPIs
PPI Name Required or Optional PPI Definition in Section
Master Boot Mode PPI Required Architectural PPIs: Required Architectural PPIs
Boot in Recovery Mode PPI Optional Architectural PPIs: Optional Architectural PPIs
I-14.9 Recovery
I-14.9.1 Scope
Recoveryistheprocessofreconstitutingasystem’sfirmwaredeviceswhentheyhavebecomecorrupted. Thecorruption
can be caused by various mechanisms. Most firmware volumes (FVs) in nonvolatile storage (NVS) devices (flash or
disk, for example) are managed as blocks. If the system loses power while a block, or semantically bound blocks, are
being updated, the storage might become invalid. On the other hand, an errant program or hardware could corrupt
the device. The system designers must determine the level of support for recovery based on their perceptions of the
probabilities of these events occurring and the consequences.
The designers of a system may choose not to support recovery for the following reasons:
•Asystem’sFVstoragemediamightnotsupportmodificationafterbeingmanufactured. Itmightbethefunctional
equivalent of a ROM.
•Most mechanisms of implementing recovery require additional FV space that might be too expensive for a par-
ticular application.
•A system may have enough FV space and hardware features that the FV can be made sufficiently fault tolerant
to make recovery unnecessary.
I-14.9.2 Discovery
DiscoveringthatrecoveryisrequiredmaybedoneusingaPEIM(forexample,bycheckinga“forcerecovery”jumper)
orthePEIFoundationitself. ThePEIFoundationmightdiscoverthataparticularPEIMhasnotvalidatedcorrectlyor
that an entire firmware has become corrupted.
I-14.8. Architectural Boot Mode PPIs I-168UEFI Platform Initialization Specification, Release 1.8
I-14.9.3 General Recovery Architecture
•Reprogram the firmware volume (FV) with that data.
PreservingtherecoveryfirmwareisafunctionofthewaytheFVstoreismanaged,whichisgenerallybeyondthescope
of this document.
If the PEI Dispatcher encounters PEIMs that have been corrupted (for example, by receiving an incorrect hash value),
it must change the boot mode to “recovery.” Once set to recovery, other PEIMs must not change it to one of the other
states.
APEIMcanalsodetectacatastrophicconditionoraforced-recoveryeventandalertthePEI10.6.4FindingandLoading
the Recovery DXE Image.
I-14.9.4 Finding and Loading the Recovery DXE Image
I-14.9.4.1 Finding the Recovery DXE Image: Overview
The PEI Dispatcher specifically invokes the DXE Initial Program Load (IPL) PEIM, regardless of normal or recovery
mode. The DXE IPL PEIM detects that a recovery is in process and invokes a recovery-specific PPI, the Recovery
Module PPI. The Recovery Module PPI, EFI_PEI_RECOVERY_MODULE_PPI , does the following:
•Loads a binary capsule that includes a recovery DXE image into memory
•Updates the Hand-Off Block (HOB) table with the DXE firmware volume
•Installs or Reinstalls instance of the Firmware Volume Info PPI ( EFI_PEI_FIRMWARE_VOLUME_INFO_PPI ) for
the DXE firmware volume
See Section 8.6.3 for the PPIs that are needed to load the DXE image.
Note:TheRecoveryModulePPIisdeviceandcontentneutral. TheDXEIPLPEIMusestheRecoveryModulePPIto
loadaDXEimageandinvokestheDXEimagenormally. TheDXEIPLPEIMdoesnotknoworcareaboutthecapsule’s
internal structure or from which device the capsule was loaded.
The internals of the recovery PEIM normally fall within four phases:
•Searching the supported devices for recovery capsules
•Deciding which capsule to load
•Loading the capsule into memory
•Loading the resulting DXE firmware volume
TheRecoveryModulePPIencompassesthefirstthreephasesandtheDXEIPLPEIMencompassesthelastphase. See
the next topic, Recovery Sequence: Detailed Steps, for the details of these four phases.
I-14.9. Recovery I-169UEFI Platform Initialization Specification, Release 1.8
I-14.9.4.2 Recovery Sequence
The normal, non-recovery sequence is that after completion of the PEI phase, the PEI Dispatcher specifically invokes
theDXEInitialProgramLoad(IPL)PEIM.Therecoverysequenceisidenticaltothenon-recoverysequenceinthatthe
PEIDispatcheralsospecificallyinvokestheDXEIPLPEIM.AfterinvokingtheDXEIPLPEIM,therecoverysequence
is as follows:
1. TheDXEIPLPEIMdetectsthatarecoveryisinprocess,searchesforthe RecoveryModulePPI,andinvokesthe
recovery function EFI_PEI_RECOVERY_MODULE_PPI.LoadRecoveryCapsule() .
2.EFI_PEI_RECOVERY_MODULE_PPI searches for one or more instances of the Device Recov-
ery Module PPI, EFI_PEI_DEVICE_RECOVERY_MODULE_PPI . For each instance found, the
EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.GetNumberRecoveryCapsules() function is invoked to
determine the following:
•The number of recovery DXE capsules detected by the specified device
•The maximum buffer size required to load a capsule
3.EFI_PEI_RECOVERY_MODULE_PPI then decides the following:
•The device search order, if more than one Device Recovery Module PPI was discovered
•The individual search order, if the device reported more than one recovery DXE capsule was found gener-
ating a search order list
4.EFI_PEI_RECOVERY_MODULE_PPI invokes the device recovery function
EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.LoadRecoveryCapsule() to load a capsule that includes a
recovery DXE image into memory. The capsule that is returned from the device recovery module is a capsule
that contains the recovery DXE image.
5. TheEFI_PEI_RECOVERY_MODULE_PPI security does the following:
•Verifies the capsule
•Generates a data Hand-Off Block (HOB) entry for a security failure
•Tries the next entry in the search order list
6. Once a valid capsule has been loaded, EFI_PEI_RECOVERY_MODULE_PPI does the following:
•DecomposesthecapsuleandupdatestheHOBtablewiththerecoveryDXEfirmwarevolumeinformation.
Thepathparametersareassumedtoberedundantforrecovery. TheSetupparametersareeitherredundant
or fixed.
•Invalidates all HOB entries for updateable firmware volume entries.
The DXE capsule that is loaded by the Device Recovery Module PPI makes no assumptions about contents or format
other than assuming that the recovery DXE image is somewhere in the returned capsule.
The following subsections describe the different recovery PPIs.
I-14.9. Recovery I-170UEFI Platform Initialization Specification, Release 1.8
I-14.9.4.3 Recovery PPIs: Recovery Module PPI
The Recovery Module PPI, EFI_PEI_RECOVERY_MODULE_PPI , invokes the Device Recovery Module PPI
EFI_PEI_DEVICE_RECOVERY_MODULE_PPI to do the following:
•Determine the number of DXE recovery capsules found by each device
•Determine capsule information
•Load a specific DXE recovery capsule from the indicated device
•Determine the device load order
ThecapsuleissecurityverifiedanddecomposedandtheHOBtableisupdatedwiththeDXErecoveryfirmwarevolume.
There are two general categories of recovery PPIs:
•Device recovery PPI
•Device recovery block I/O PPI
The Device Recovery Module PPI is device neutral. The Device Recovery Block I/O PPI is device specific and used
to access the physical media. The following subsections describe the PPI associated with each category. See Code
Definitions for the definitions of these PPIs.

I-14.9.4.3.1 Device Recovery Module PPI
The table below lists the device recovery functions in the Device Recovery Module PPI,
EFI_PEI_DEVICE_RECOVERY_MODULE_PPI .
Table 14.3: Device Recovery Module Functions
Function Description
GetNumberRecoveryCapsules Scans the devices that are supported by the PPI for DXE recovery capsules
andreportsthenumberfoundTheinternalorderingshouldreflecttheprior-
ityintheloadorderwiththehighestprioritycapsulenumbersettooneand
the lowest priority number set to N
GetRecoveryCapsuleInfo Provides the size of the indicated capsule and a CapsuleType Globally
Unique Identifier GUID The recovery module uses this information to al-
low an alternate priority scheme based on the CapsuleType information
LoadRecoveryCapsule Loads the indicated DXE recovery capsule instance and returns a capsule
with the actual number of bytes loaded
I-14.9.4.3.2 Device Recovery Block I/O PPI
TheDeviceRecoveryBlockI/OPPI, EFI_PEI_RECOVERY_BLOCK_IO_PPI ,differsfromtheDeviceRecoveryModule
PPI in that the Device Recovery Block I/O PPI is used for physical media access. The Device Recovery Module PPI
uses this PPI to search for capsules. This PPI is included with the recovery PEIMs because a block I/O is the most
common recovery media.
The table below lists the functions in the Device Recovery Block I/O PPI.
I-14.9. Recovery I-171UEFI Platform Initialization Specification, Release 1.8
Table 14.4: Device Recovery Block I/O Functions
GetNumberOf-
BlockDevicesReturns the number of block I O devices supported There is no ordering priority
GetBlockDevice-
MediaInfoIndicates the type of block I O device found such as a legacy floppy or CD ROM The block
size and last block number are also returned
ReadBlocks Reads the indicated block I O device starting at the given logical block address LBA and for
buffer size block size
I-14.9. Recovery I-172CHAPTER
FIFTEEN
PEI PHYSICAL MEMORY USAGE
I-15.1 Introduction
This section describes how physical system memory is used during PEI. The rules for using physical system memory
are different before and after permanent memory registration within the PEI execution.
I-15.2 Before Permanent Memory Is Installed
I-15.2.1 Discovering Physical Memory
Before permanent memory is installed, the minimum exit condition for the PEI phase is that it has enough physical
system memory to run PEIMs and the DXE IPL PPI that require permanent memory. These memory-aware PEIMs
may discover and initialize additional system memory, but in doing so they must not cause loss of data in the physical
system memory initialized during the earlier phase. The required amount of memory initialized and tested by PEIMs
in these two phases is platform dependent.
Beforepermanentmemoryisinstalled,aPEIMmaynotassumeanyareaofphysicalmemoryispresentandinitialized.
Duringthisearlyphase,aPEIM—usuallyonespecifictothechipsetmemorycontroller—willinitializeandtestphysical
memory. When this PEIM has initialized and tested the physical memory, it will register the memory using the PEI
Memory Service InstallPeiMemory() , which in turn will cause the PEI Foundation to create an initial Hand- Off
Block (HOB) list and describe the memory. The memory that is present, initialized, and tested will reside in resource
descriptorHOBsintheinitialHOBlist(see Volume3 formoreinformation). ThismemoryallocationPEIMmayalso
choose to allocate some of the physical memory by doing the following:
•–CreatingmemoryallocationHOBs,asdescribedin:ref: allocating-memory-using-guid-extension-hobs on
page 227 to allocate the memory outside the region registered with InstallPeiMemory() .
•Usingthememoryallocationservices AllocatePages() andAllocatePool() toallocatethememorywithin
the region registered with InstallPeiMemory() . Once permanent memory has been installed, the resources
described in the HOB list are considered permanent system memory.
Oncepermanentmemoryhasbeeninstalled,theresourcesdescribedintheHOBlistareconsideredpermanentsystem
memory.
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I-15.2.2 Using Physical Memory
A PEIM that requires permanent, fixed memory allocation must schedule itself to run after
EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI is installed. To schedule itself, the PEIM can do one of the
•Put this PPI’s GUID into the depex of the PEIM.
•Register for a notification.
The PEIM can then allocate Hand-Off Blocks (HOBs) and other memory using the same mechanisms described in
Allocating Physical Memory .
TheAllocatePool() service can be invoked at any time during the boot phase to discover temporary memory that
will have its location translated, even before permanent memory is installed.
I-15.3 After Permanent Memory Is Installed
I-15.3.1 Allocating Physical Memory
After permanent memory is installed, PEIMs may allocate memory in two ways:
•Using a GUID Extension HOB
•Within the PEI free memory space
I-15.3.2 Allocating Memory Using GUID Extension HOBs
A PEIM may allocate memory for its private use by constructing a GUID Extension HOB and using the private data
area defined by the GUIDed name of the HOB for private data storage. See Volume 3 for HOB construction rules.
Note:Memory region allocated with GUID Extension HOB must not overlap with the memory region registered
with the PEI Foundation using IntelPeiMemory() service. The boundaries of the latter region are described by the
EfiMemoryBottom and EfiMemoryTop values of the PHIT HOB. Refer to Volume 3 for a full PHIT HOB format
I-15.3.3 Allocating Memory Using PEI Service
A PEIM may allocate memory using the PEI Service AllocatePages() . Use the EFI_MEMORY_TYPE values to
specify the type of memory to allocate; type EFI_MEMORY_TYPE is defined is defined in AllocatePages() in the
UEFI 2.0 specification.
I-15.3. After Permanent Memory Is Installed I-174CHAPTER
SIXTEEN
SPECIAL PATHS UNIQUE TO THE ITANIUM ®PROCESSOR FAMILY
I-16.1 Introduction
TheItaniumprocessorfamilysupportsthefullcomplementofbootmodeslistedinthePEICIS.Inaddition,however,
Itanium ®architecture requires an augmented flow. This flow includes a “recovery check call” in which all processors
execute the PEI Foundation when an Itanium platform restarts. Each processor has its own version of temporary
memory such that there are as many concurrent instances of PEI execution as there are Itanium processors.
Thereisapointinthemultiprocessorflow,however,whenallprocessorshavetocallbackintotheProcessorAbstraction
Layer A (PAL-A) component to assess whether the processor revisions and PAL-B binaries are compatible. This
callback into the PAL-A does not preserve the state of the temporary memory, however. When the PAL-A returns
control back to the various processors, the PEI Foundation and its associated data structures have to be reinstantiated.
Atthispoint,however,theflowofthePEIphaseisthesameasforIA-32Intelarchitectureinthatallprocessorsmake
forward progress up through invoking the DXE IPL PPI.
I-16.2 Unique Boot Paths for Itanium Architecture
Intel®ItaniumprocessorspossesstwouniquebootpathsthatalsoinvokethedispatcherlocatedattheSystemAbstrac-
tion Layer entry point (SALE_ENTRY):
•Processor INIT
•Machine Check (MCHK)
INIT and MCHK are two asynchronous events that start up the Security (SEC) code/dispatcher in an Itanium ®-based
system. ThePIArchitecturesecuritymoduleistransparentduringallthecodepathsexceptfortherecoverycheckcall
that happens during a cold boot. The PEIMs that handle these events are architecture aware and do not return control
to the PEI Dispatcher. They call their respective architectural handlers in the operating system.
Itanium Processor Boot Path (INIT and MCHK) shows the boot path for INIT and MCHK events.
I-175UEFI Platform Initialization Specification, Release 1.8
Fig. 16.1: Itanium Processor Boot Path (INIT and MCHK)
I-16.3 Min-State Save Area
When the Processor Abstraction Layer (PAL) hands control to the dispatcher, it will supply the following:
•Unique handoff state in the registers
•A pointer, called the min-state pointer, to the minimum-state saved buffer area
Thisbufferisauniqueper-processorsaveareathatisregisteredtoeachprocessorduringthenormalOSbootpath. The
PIArchitecturedefinesaunique,PIArchitecture-specificdatapointer, EFI_PEI_MIN_STATE_DATA ,thatisattachedto
this min-state pointer. This data structure is defined in the next topic.
Min-State Buffer Organization shows a typical organization of a min-state buffer. The PEI Data Pointer references
EFI_PEI_MIN_STATE_DATA .
Fig. 16.2: Min-State Buffer Organization
I-16.3. Min-State Save Area I-176UEFI Platform Initialization Specification, Release 1.8
I-16.3.1 EFI_PEI_MIN_STATE_DATA
Note:This data structure is for the Itanium processor family only.
Summary
AstructurethatencapsulatestheProcessorAbstractionLayer(PAL)min-statedatastructureforpurposesoffirmware
state storage and reference.
Prototype
UINT64 OsInitHandlerPointer;
UINT64 OsInitHandlerGP;
UINT64 OsInitHandlerChecksum;
UINT64 OSMchkHandlerPointer;
UINT64 OSMchkHandlerGP;
UINT64 OSMchkHandlerChecksum;

Summary
Prototype
UINT64 PeimInitHandlerPointer;
UINT64 PeimInitHandlerGP;
UINT64 PeimInitHandlerChecksum;
UINT64 PeimMchkHandlerPointer;
UINT64 PeimMchkHandlerGP;
UINT64 PeimMckhHandlerChecksum;
UINT64 TypeOfOSBooted;
UINT8 MinStateReserved[0x400];
UINT8 OEMReserved[0x400];
} EFI_PEI_MIN_STATE_DATA;
OsInitHandlerPointer
Theaddressoftheoperatingsystem’sINIThandler. TheINITisarestarttypefortheItaniumprocessorfamily.
OsInitHandlerGP
The value of the operating system’s INIT handler’s General Purpose (GP) register. Per the calling conventions
for the Itanium processor family, the GP must be set before invoking the function.
OsInitHandlerChecksum
A 64-bit checksum across the contents of the operating system’s INIT handler. This can be used by the PEI
firmware to corroborate the integrity of the INIT handler prior to invocation.
OSMchkHandlerPointer
Theaddressoftheoperatingsystem’sMachineCheck(MCHK)handler. MCHKisarestarttypefortheItanium
processor family.
OSMchkHandlerGP
The value of the operating system’s MCHK handler’s GP register. Per the calling conventions for the Itanium
processor family, the GP must be set before invoking the function.
OSMchkHandlerChecksum
A 64-bit checksum across the contents of the operating system’s MCHK handler. This can be used by the PEI
firmware to corroborate the integrity of the MCHK handler prior to invocation.
PeimInitHandlerPointer
The address of the PEIM’s INIT handler.
PeimInitHandlerGP
ThevalueofthePEIM’sINIThandler’sGPregister. PerthecallingconventionsfortheItaniumprocessorfamily,
the GP must be set before invoking the function.
I-16.3. Min-State Save Area I-177UEFI Platform Initialization Specification, Release 1.8
PeimInitHandlerChecksum
A 64-bit checksum across the contents of the PEIM’s INIT handler. This can be used by the PEI firmware to
corroborate the integrity of the INIT handler prior to invocation.
PeimMchkHandlerPointer
The address of the PEIM’s MCHK handler.
PeimMchkHandlerGP
The value of the PEIM’s MCHK handler’s GP register. Per the calling conventions for the Itanium processor
family, the GP must be set before invoking the function.
PeimMckhHandlerChecksum
A 64-bit checksum across the contents of the PEIM’s MCHK handler. This can be used by the PEI firmware to
corroborate the integrity of the MCHK handler prior to invocation.
TypeOfOSBooted
Detailsthetypeofoperatingsystemthatwasoriginallybooted. Thisallowsfordifferentpreliminaryprocessing
in firmware based upon the target OS.
MinStateReserved
Reserved bytes that must not be interpreted by OEM firmware. Future versions of PEI may choose to expand in
this range.
OEMReserved
Reserved bytes for the OEM. PEI core components should not attempt to interpret the contents of this region.
A 64-bit PEI data pointer is defined at the beginning of the Itanium processor family min-state data structure. This
data pointer references an EFI_PEI_MIN_STATE_DATA structure that is defined above. This latter structure contains
the entry points of INIT and MCHK code blocks. The pointers are defined such that the INIT and MCHK code can
be either written as ROM-based PEIMs or as DXE drivers. The distinction between PEIM and DXE driver are at the
OEM’s discretion.
In Itanium ®architecture, the PEI firmware must register a min-state with the PAL. This min-state is memory when
the PAL code can deposit processor-specific information upon various restart events (INIT, RESET, Machine Check).
Upon receipt of INIT or MCHK, the PEI firmware shall first invoke the PEIM INIT or MCHK handlers, respectively,
andthentheOSINITorMCHKhandler. Themin-statedatastructureisanaturallocationfromwhichtoreferencethe
PEI data structure that contains these latter entry points.
I-16.4 Dispatching Itanium Processor Family PEIMs
The Itanium processor family dispatcher starts dispatching all the PEIMs as it resolves the dependency grammar con-
tained within their headers. Because all Itanium processors enter into SALE_ENTRY for a recovery check, some of
thePEIMswillcontainmultiprocessor(MP)codeandwillworkonallprocessors. ThebehaviorofaparticularPEIM
that is dispatched depends on the following:
•Handoff state given by the Processor Abstraction Layer (PAL)
•The boot mode flag
Once the processor runs some code and one of the recovery check PEIM determines that the firmware needs to be
recovered, it flips the boot flag to recovery and invokes the dispatcher again in recovery mode.
If it is a nonrecovery situation (normal boot), then the recovery check PEIM wakes up all the processors and returns
them to PAL-A for further initialization. Note that when control for a normal boot returns back to the PAL to run
PAL-B code, all of the register contents are lost. When control returns to the dispatcher, the PEIMs gain control in
thedispatchedorderandcandeterminethememorytopology(ifneededinaplatformimplementation)byreadingthe
memory controller registers of the chipset. The PEIMs can then build Hand-Off Blocks (HOBs).
I-16.4. Dispatching Itanium Processor Family PEIMs I-178UEFI Platform Initialization Specification, Release 1.8
When the first phase is done, there will be coherent memory on the system that all the node processors can see. The
system then begins to execute the dispatcher in a second phase, during which it builds HOBs. On a multinode system
with many processors, the configuration of memory may take several steps and therefore quite a bit of code.
When the second phase is done, the last PEIM will build DXE as described in PEI to DXE Handoff and hand control
to the PI Architecture DXE phase for further initialization of the platform.
Boot Path in Itanium Processors depicts the initial flow between PAL-A , PAL-B, and the PEI Foundation located at
SALE_ENTRY point.
Fig. 16.3: Boot Path in Itanium Processors
I-16.4. Dispatching Itanium Processor Family PEIMs I-179CHAPTER
SEVENTEEN
SECURITY (SEC) PHASE INFORMATION
I-17.1 Introduction
The Security (SEC) phase is the first phase in the PI Architecture architecture and is responsible for the following:
•Handling all platform restart events
•Creating a temporary memory store
•Serving as the root of trust in the system
•Passing handoff information to the PEI Foundation
Inadditiontotheminimumarchitecturallyrequiredhandoffinformation,theSECphasecanpassoptionalinformation
to the PEI Foundation, such as the SEC Platform Information PPI or information about the health of the processor.
Thetaskslistedabovearecommontoallprocessormicroarchitectures. However,therearesomeadditionsordifferences
between IA-32 and Itanium processors, which are discussed in Processor-Specific Details .
I-17.2 Responsibilities
I-17.2.1 Handling All Platform Restart Events
The Security (SEC) phase is the unit of processing that handles all platform restart events, including the following:
•Applying power to the system from an unpowered state
•Restarting the system from an active state
•Receiving various exception conditions
The SEC phase is responsible for aggregating any state information so that some PEIM can deduce the health of the
processor upon the respective restart.
I-180UEFI Platform Initialization Specification, Release 1.8
I-17.2.2 Creating a Temporary Memory Store
The Security (SEC) phase is also responsible for creating some temporary memory store. This temporary memory
store can include but is not limited to programming the processor cache to behave as a linear store of memory. This
cache behavior is referred to as “no evictions mode” in that access to the cache should always represent a hit and not
engenderanevictiontothemainmemorybackingstore;this“noeviction”isimportantinthatduringthisearlyphaseof
platform evolution, the main memory has not been configured and such as eviction could engender a platform failure.
I-17.2.3 Serving As the Root of Trust in the System
Finally,theSecurity(SEC)phaserepresentstherootoftrustinthesystem. Anyinductivesecuritydesigninwhichthe
integrityofthesubsequentmoduletogaincontroliscorroboratedbythecallermusthavearoot,or“first,”component.
For any PI Architecture deployment, the SEC phase represents the initial code that takes control of the system. As
such,aplatformortechnologydeploymentmaychoosetoauthenticatethePEIFoundationfromtheSECphasebefore
invoking the PEI Foundation.
I-17.2.4 Passing Handoff Information to the PEI Foundation
Regardlessoftheotherresponsibilitieslistedinthissection,theSecurity(SEC)phase’sfinalresponsibilityistoconvey
the following handoff information to the PEI:
•State of the platform
•Location and size of the Boot Firmware Volume (BFV)
•Location and size of the temporary RAM
•Location and size of the stack
•Optionally, one or more HOBs via the EFI_SEC_HOB_DATA_PPI
This handoff information listed above is passed to the PEI as arguments to the PEI Foundation entry point described
inPEI Foundation Entry Point . The location of the BFV will be superseded by EFI_PEI_CORE_FV_LOCATION_PPI
if that exists.
I-17.3 SEC Platform Information PPI

Handoff information is passed from the Security (SEC) phase to the PEI Foundation using the
EFI_SEC_PEI_HAND_OFF structure and the list of PPI descriptors passed to the PEI entry point. One of these
PPIs,EFI_SEC_PLATFORM_INFORMATION_PPI , can be used to pass handoff information from SEC to the PEI
Foundation. ThisPPIabstractsplatform-specificinformationthatthePEIFoundationneedstodiscoverwheretobegin
dispatching PEIMs.
I-17.3. SEC Platform Information PPI I-181UEFI Platform Initialization Specification, Release 1.8
I-17.4 SEC HOB Data PPI
HOB data can be passed forward from the SEC phase to PEI or DXE consumers using HOBs. If the
EFI_SEC_HOB_DATA_PPI is in the list of PPIs passed to the PEI entry point, the PEI Foundation will call the
GetHobs() member function and installed all HOBs returned into the HOB list. It does this after installing all PPIs
passed from SEC into the PPI database and before dispatching any PEIMs.
I-17.5 Health Flag Bit Format
TheHealthflagcontainsinformationthatisgeneratedbymicrocode,hardware,and/ortheItaniumprocessorProcessor
Abstraction Layer (PAL) code about the state of the processor upon reset. Type EFI_HEALTH_FLAGS is defined in
SEC_PLATFORM_INFORMATION_PPI.PlatformInformation() .
InanItanium ®-basedsystem,theHealthflagispassedfromPAL-Aafterrestarting. ItisthemeansbywhichthePAL
conveys the state of the processor to the firmware, such as PI. The handoff state is separated between the PAL and PI
because the code is provided by different vendors; Intel provides the PAL and various OEMs design the PI firmware.
The Health flag is used by both IA-32 and Itanium architectures, but Tested(Te) is the only common bit. IA-32 has
the built-in self-test (BIST), but none of the other capabilities.
Health Flag Bit Format depicts the bit format in the Health flag.
Fig. 17.1: Health Flag Bit Format
Health Flag Bit Field Description explains the bit fields in the Health flag. IA-32 ignores all bits except Tested(Te).
Table 17.1: Health Flag Bit Field Description
Field Parameter Name in
EFI_HEALTH_FLAGSBit Description
State Status 0 1 A2bitfieldindicatingselfteststateaf-
terresetFormoreinformationsee Self-
Test State Parameter
Te Tested 2 A 1 bit field indicating whether test-
inghasoccurredIfthisfieldiszerothe
processor has not been tested and no
further fields in the self test State pa-
rameter are valid
Vm VirtualMemoryUnavailable 16 A 1 bit field If set to 1 indicates that
virtual memory features are not avail-
able
Ia Ia32ExecutionUnavailable 17 A1bitfieldIfsetto1indicatesthatIA
32 execution is not available
I-17.4. SEC HOB Data PPI I-182UEFI Platform Initialization Specification, Release 1.8
Table 17.1 – continued from previous page
Fp FloatingPointUnavailable 18 A 1 bit field If set to 1 indicates that
the floating point unit is not available
Mf MiscFeaturesUnavailable 19 A1bitfieldIfsetto1indicatesmiscel-
laneous functional failure other than
vm ia or fp The test status field pro-
vides additional information on test
failures when the State field returns
a value of performance restricted or
functionally restricted The value re-
turned is implementation dependent
I-17.5.1 Self-Test State Parameter
Self-teststateparametersaredefinedinthesameformatforIA-32Intel ®processorsandtheIntel ®Itanium ®processor
family. SomeoftheteststatusbitsmaynotberelevanttoIA-32processors. Inthatcase,thesebitswillread NULLon
IA-32 processors.
Self-Test State Bit Values indicates the meanings for various values of the self-test State parameter (bits 0:1) of the
Health flag.
Table 17.2: Self-Test State Bit Values
State Value Description
Catastrophic Failure N/A Processor is not executing.
Healthy 00 No failure in functionality or performance.
Performance Restricted 01 Nofailureinfunctionalitybutperformanceisrestricted.
Functionally Restricted 10 Some code may run but functionality is restricted and
performance may also be affected.
If the state field indicates that the processor is functionally restricted, then the vm, ia, and fp fields in the Health flag
specify additional information about the functional failure. See Health Flag Bit Field Description for a description of
these fields.
To further qualify “Functionally Restricted,” the following requirements will be met:
•TheprocessororPAL(fortheItaniumprocessorfamily)hasdetectedandisolatedthefailingcomponentsothat
it will not be used.
•The processor must have at least one functioning memory unit, arithmetic logic unit (ALU), shifter, and branch
unit.
•The floating-point unit may be disabled.
•FortheItaniumprocessorfamily,theRegisterStackEngine(RSE)isnotrequiredtowork,butregisterrenaming
logic must work properly.
•The paths between the processor-controlled caches and the register files must work during the tests.
•Loads from the firmware address space must work correctly.
I-17.5. Health Flag Bit Format I-183UEFI Platform Initialization Specification, Release 1.8
I-17.6 Processor-Specific Details
I-17.6.1 SEC Phase in IA-32 Intel Architecture
In32-bitIntel ®architecture(IA-32),theSecurity(SEC)phaseofthePIArchitectureisresponsibleforseveralactivities:
•Locating the PEI Foundation
•Passing control directly to PEI using an architecturally defined handoff state
•Initializingprocessor-controlledmemoryresources,suchastheprocessordatacache,thatcanbeusedasalinear
extent of memory for a call stack (if supported)
PEI Initialization Steps in IA-32 below shows the steps completed during PEI initialization for IA-32.
Fig. 17.2: PEI Initialization Steps in IA-32
I-17.6.2 SEC Phase in the Itanium Processor Family
Itanium architecture contains enough hooks to authenticate the PAL-A and PAL-B code distributed by the processor
vendor.
The internal microcode on the processor silicon that starts up on a power-good reset finds the first layer of processor
abstractioncode(calledPAL-A)locatedintheBootFirmwareVolume(BFV)usingarchitecturallydefinedpointersin
theBFV.ItistheresponsibilityofthismicrocodetoauthenticatethatthePAL-Acodelayerfromtheprocessorvendor
has not been tampered.
If the authentication of the PAL-A layer passes, then control passes on to the PAL-A layer. The PAL-A layer then
authenticates the next layer of processor abstraction code (called PAL-B) before passing control to it.
In addition, the SEC phase of the PI Architecture is also responsible for locating the PEI Foundation and verifying its
authenticity.
Security (SEC) Phase in the Itanium ProcessorFamily summarizes the SEC phase in the Itanium ®processor family.
Fig. 17.3: Security (SEC) Phase in the Itanium ProcessorFamily
I-17.6. Processor-Specific Details I-184CHAPTER
EIGHTEEN
DEPENDENCY EXPRESSION GRAMMAR
I-18.1 Dependency Expression Grammar
ThistopiccontainsanexampleBNFgrammarforaPEIMdependencyexpressioncompilerthatconvertsadependency
expression source file into a dependency section of a PEIM stored in a firmware volume.
I-18.1.1 Example Dependency Expression BNF Grammar
<depex> ::= <bool>
<bool> ::= <bool> AND <term>
| <bool> OR <term>
| <term>
<term> ::= NOT <factor>
| <factor>
<factor> ::= <bool>
| TRUE
| FALSE
| GUID
| END
<guid> ::= ‘{‘ <hex32> ‘,’ <hex16> ‘,’ <hex16> ‘,’
<hex8> ‘,’ <hex8> ‘,’ <hex8> ‘,’ <hex8> ‘,’
<hex8> ‘,’ <hex8> ‘,’ <hex8> ‘,’ <hex8> ’}’
<hex32> ::= <hexprefix> <hexvalue>
<hex16> ::= <hexprefix> <hexvalue>
<hex8> ::= <hexprefix> <hexvalue>
<hexprefix> ::= ‘0’ ‘x’
| ‘0’ ‘X’
<hexvalue> ::= <hexdigit> <hexvalue>
| <hexdigit>
<hexdigit> ::= [0-9]
| [a-f]
| [A-F]
I-185UEFI Platform Initialization Specification, Release 1.8
I-18.1.2 Sample Dependency Expressions
ThefollowingcontainsthreeexamplesofsourcestatementsusingtheBNFgrammarfromabovealongwiththeopcodes,
operands, and binary encoding that a dependency expression compiler would generate from these source statements.
//
// Source
//
EFI_PEI_CPU_IO_PPI_GUID AND EFI_PEI_READ_ONLY_VARIABLE_ACCESS_PPI_GUID
END
//
// Opcodes, Operands, andBinary Encoding
//
ADDR BINARY MNEMONIC
==== ======================= =======================
0x00 : 02 PUSH
0x01 : 26 25 73 b0 c8 38 40 4b EFI_PEI_CPU_IO_PPI_GUID
88 77 61 c7 b0 6a ac 45
0x11 : 02 PUSH
0x12 : b1 cc ba 26 42 6f d4 11
EFI_PEI_READ_ONLY_VARIABLE_ACCESS_PPI_GUID
bc e7 00 80 c7 3c 88 81
0x22 : 03 AND
0x23 : 08 END
I-18.1. Dependency Expression Grammar I-186CHAPTER
NINETEEN
TE IMAGE
I-19.1 Introduction
TheTerse Executable (TE) image format was created as a mechanism to reduce the overhead of the PE/COFF head-
ers in PE32/PE32+ images, resulting in a corresponding reduction of image sizes for executables running in the PI
Architecture environment. Reducing image size provides an opportunity for use of a smaller system flash part.
TE images, both drivers and applications, are created as PE32 (or PE32+) executables. PE32 is a generic executable
image format that is intended to support multiple target systems, processors, and operating systems. As a result, the
headers in the image contain information that is not necessarily applicable to all target systems. In an effort to reduce

NINETEEN
TE IMAGE
imagesize,anewexecutableimageheader(TE)wascreatedthatincludesonlythosefieldsfromthePE/COFFheaders
required for execution under the PI Architecture. Since this header contains the information required for execution of
the image, it can replace the PE/COFF headers from the original image. This specification defines the TE header, the
fields in the header, and how they are used in the PI Architecture’s execution environment.
I-19.2 PE32 Headers
A PE file header, as described in the Microsoft Portable Executable and Common Object File Format Specification ,
contains an MS-DOS* stub, a PE signature, a COFF header, an optional header, and section headers. For successful
execution,PEIMsinthePIArchitecturerequireverylittleofthedatafromtheseheaders,andinfacttheMS-DOSstub
and PE signature are not required at all.
SeeCOFFHeaderFieldsRequiredforTEImages andOptionalHeaderFieldsRequiredforTEImages forthenecessary
fields and their descriptions.
Table 19.1: COFF Header Fields Required for TE Images
COFF Header Description
Machine Target machine identifier 2 bytes in both COFF header and TE
header
NumberOfSections Number of sections section headers 2 bytes in COFF header 1 byte
in TE header
I-187UEFI Platform Initialization Specification, Release 1.8
Table 19.2: Optional Header Fields Required for TE Images
OPTIONAL Header Description
AddressOfEntryPoint Addressofentrypointrelativetoimagebase4bytesinbothoptional
header and TE header
BaseOfCode Offsetfromimagebasetothestartofthecodesection4bytesinboth
optional header and TE header
ImageBase Image s linked address 4 bytes in OptionalHeader32 8 bytes in Op-
tionalHeader64 and 8 bytes in TE header
Subsystem Subsystem required to run the image 2 bytes in optional header 1
byte in TE header
I-19.2.1 TE Header
Summary
ToreducetheoverheadofPE/COFFheadersinthePIArchitecture’senvironment,aminimal(TE)headercanbedefined
that includes only those fields required for execution in the PI Architecture. This header can then be used to replace
the original headers at the start of the original image.
Prototype
UINT16 Machine;
UINT8 NumberOfSections;
UINT8 Subsystem;
UINT16 StrippedSize;
UINT32 AddressOfEntryPoint;
UINT32 BaseOfCode;
UINT64 ImageBase;
EFI_IMAGE_DATA_DIRECTORY DataDirectory[2];
} EFI_TE_IMAGE_HEADER;
Signature
TE image signature
Machine
Target machine, as specified in the original image’s file header
NumberOfSections
Number of sections, as specified in the original image’s file header
Subsystem
Target subsystem, as specified in the original optional header
StrippedSize
Number of bytes removed from the base of the original image
AddressOfEntryPoint
Address of the entry point to the driver, as specified in the original image’s optional header
BaseOfCode
Base of the code, as specified in the original image’s optional header
I-19.2. PE32 Headers I-188UEFI Platform Initialization Specification, Release 1.8
ImageBase
Image base, as specified in the original image’s optional header (0-extended to 64-bits for PE32 images)
DataDirectory
Directoryentriesforbaserelocationsandthedebugdirectoryfromtheoriginalimage’scorrespondingdirectory
entries. See “Related Definitions” below.
Field Descrptions
In theEFI_TE_IMAGE HEADER , theMachine, NumberOfSections ,Subsystem ``,``AddressOfEntryPoint ,
BaseOfCode , andImageBase all come directly from the original PE headers to enable partial reconstitution of the
original headers if necessary.
The2-byte Signature shouldbesetto EFI_TE_IMAGE_HEADER_SIGNATURE todesignatetheimageasTE,asopposed
to the “MZ” signature at the start of standard PE/COFF images.
TheStrippedSize should be set to the number of bytes removed from the start of the original image, which will
typically include the MS-DOS, COFF, and optional headers, as well as the section headers. This size can be used
by image loaders and tools to make appropriate adjustments to the other fields in the TE image header. Note that
StrippedSize does not take into account the size of the TE image header that will be added to the image. That is to
say,thedeltainthetotalimagesizewhenconvertedtoTEis StrippedSize -sizeof(EFI_TE_IMAGE_HEADER ).This
will typically need to be taken into account by tools using the fields in the TE header.
TheDataDirectory array contents are copied directly from the base relocations and debug directory entries in the
original optional header data directories. This image format also assumes that file alignment is equal to section align-
ment.
//EFI_IMAGE_DATA_DIRECTORY
UINT32 VirtualAddress;
} EFI_IMAGE_DATA_DIRECTORY;
#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC 0
#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG 1
#define EFI_TE_IMAGE_HEADER_SIGNATURE 0x5A56 // “VZ”
I-19.2. PE32 Headers I-189CHAPTER
TWENTY
TE IMAGE CREATION
I-20.1 Introduction
This section describes the tool requirements to create a TE image.
I-20.2 TE Image Utility Requirements
A utility that creates TE images from standard PE/COFF images must be able to do the following:
•Create an EFI_TE_IMAGE_HEADER in memory
•Parse the PE/COFF headers in an existing image and extract the necessary fields to fill in the
EFI_TE_IMAGE_HEADER
•Fill in the signature and stripped size fields in the EFI_TE_IMAGE_HEADER
•Write out the EFI_TE_IMAGE_HEADER to a new binary file
•Write out the contents of the original image, less the stripped headers, to the output file
Since some fields from the PE/COFF headers have a smaller corresponding field in the TE image header, the utility
mustbeabletorecognizeiftheoriginalvaluefromthePE/COFFheaderdoesnotfitintheTEheader. Inthiscase,the
original image is not a candidate for conversion to TE image format.
I-20.3 TE Image Relocations
Relocation fix ups in TE images are not modified by the TE image creation process. Therefore, if a TE image is to
be relocated, the loader/relocator must take into consideration the stripped size and size of a TE image header when
applying fix ups.
I-190CHAPTER
TWENTYONE
TE IMAGE LOADING
I-21.1 Introduction
This section describes the use of the TE image and how embedded, execute-in-place environments can invoke these
images.
I-21.2 XIP Images
For execute-in-place (XIP) images that do not require relocations, loading a TE image simply requires that the loader
adjusttheimage’sentrypointfromthevaluespecifiedinthe EFI_TE_IMAGE_HEADER .Forexample,iftheimage(and
thustheTEheader)residesatmemorylocation LoadedImageAddress ,thentheactualentryforthedriveriscomputed
EntryPoint = LoadedImageAddress + sizeof (*EFI_TE_IMAGE_HEADER*)
+
((EFI_TE_IMAGE_HEADER *)LoadedImageAddress)->
AddressOfEntryPoint - ((EFI_TE_IMAGE_HEADER *)
LoadedImageAddress)->StrippedSize;
I-191UEFI Platform Initialization Specification, Release 1.8
I-21.3 Relocated Images
To successfully load and relocate a TE image requires the same operations as required for XIP code. However, for
imagesthatcanberelocated,theimageloadermustmakeadjustmentsforalltherelocationfixupsperformed. Details
on this operation are beyond the scope of this document, but suffice it to say that the adjustments will be computed in
a manner similar to the EntryPoint adjustment made in XIP Images.
I-21.4 PIC Images
ATEImageisPositionIndependentCode(PIC)ifitcanbeexecutedinflashandshadowedtomemorywithoutanyfix
ups. In this case, the TE Image Relocation Data Directory Entry Virtual Address is non-zero, but the Relocation Data
Directory Size is zero.
I-21.3. Relocated Images I-192Part II
Driver Execution Environment Core
InterfaceUEFI Platform Initialization Specification, Release 1.8
List of Figures - Volume II
•DXE Architectural Protocols
•DXE Driver States
•Sample Firmware Volume
•HOB List
•UEFI System Table and Related Components
•DXE Foundation Components
•PI Architecture Firmware Phases
•GCD Memory State Transitions
•GCD I/O State Transitions
II-iUEFI Platform Initialization Specification, Release 1.8
•BEFORE Instruction Encoding
•AFTER Instruction Encoding
•DXE Dispatcher Orderings
•Boot Service Dependencies
•Runtime Service Dependencies
•Resource Descriptor HOB to GCD Type Mapping
•Organization of the DXE CIS
•UEFI Boot Services
•UEFI Runtime Services
•DXE Services
•Status Codes Runtime Protocol
•Firmware Volume Media Device Path
•Firmware Volume Device Node Text Representation
•Firmware File Media Device Path
•Firmware Volume File Device Node TextRepresentation
•Status Code Runtime Protocol
•Supported Subsystem Values
•Global Coherency Domain Boot Type Services
•Dispatcher Boot Type Services
II-iiCHAPTER
ONE
II-1.1 Overview
This specification defines the core code and services that are required for an implementation of the driver execution
environment (DXE) phase of the Unified Extensible Firmware Interface (UEFI) Foundation. This DXE core interface

ONE
specification (CIS) does the following:
•Describes the basic components of the DXE phase.
•Provides code definitions for services and functions that are architecturally required by the Unified Extensible
Firmware Interface Specification (UEFI 2.0 specification).
•Presents a set of backward-compatible extensions to the UEFI 2.0 specification.
•Describes the machine preparation that is required for subsequent phases of firmware execution.
SeeOrganization of the DXE CIS for more information.
II-1.2 Organization of the DXE CIS
ThisDXEcoreinterfacespecification(CIS)isorganizedasshownin OrganizationoftheDXECIS .BecausetheDXE
FoundationisjustonecomponentofaPIArchitecture-basedfirmwaresolution,thereareanumberofadditionalspec-
ifications that are referred to throughout this document.
II-1UEFI Platform Initialization Specification, Release 1.8
Table 1.1: Organization of the DXE CIS
Book Description
Overview Describes the major components of DXE, including the boot manager,
firmware core, protocols, and requirements.
Boot Manager Describes the boot manager, which is used to load UEFI drivers, UEFI ap-
plications, and UEFI OS loaders.
UEFI System Table Describes the DXE Service table.
Services - Boot Services Describes specific event types for DXE Foundation.
Runtime Capabilities Contains definitions of a runtime protocol for status code support.
Services - DXE Services ContainsdefinitionsforthefundamentalservicesthatarepresentinaDXE-
Protocols - Device Path Protocol Defines the device path extensions required by the DXE Foundation.
DXE Foundation Describes the DXE Foundation that consumes HOBs, Firmware Volumes,
and DXE Architectural Protocols to produce an UEFI System Table, UEFI
Boot Services, UEFI Runtime Services, and the DXE Services.
DXE Dispatcher DescribestheDXEDispatcherthatisresponsibleforloadingandexecuting
DXE drivers from Firmware Volumes.
DXE Drivers Describes the different classes of DXE drivers that may be stored in
Firmware Volumes.
DXE Architectural Protocols Describes the Architectural Protocols that are produced by DXE drivers.
They are also consumed by the DXE Foundation to produce the UEFI Boot
Services, UEFI Runtime Services, and DXE Services.
DXE Runtime Protocols Lists success, error, and warning codes returned by DXE and UEFI inter-
faces.
Dependency Expression Grammar DescribestheBNFgrammarforatoolthatcanconvertatextfilecontaining
a dependency expression into a dependency section of a DXE driver stored
in a Firmware Volume.
II-1.3 Target Audience
•IHVs and OEMs who will be implementing DXE drivers that are stored in firmware volumes.
•BIOS developers, either those who create general-purpose BIOS and other firmware products or those who
modify these products for use in various vendor architecture-based products.
II-1.3. Target Audience II-2UEFI Platform Initialization Specification, Release 1.8
II-1.4 Conventions Used in this Document
II-1.4.1 Data Structure Descriptions
STRUCTURE NAME
The formal name of the data structure.
Summary
A brief description of the data structure.
Prototype
A “C-style” type declaration for the data structure.
A brief description of each field in the data structure prototype.
Adescriptionofthefunctionalityprovidedbythedatastructure,includinganylimitationsandcaveatsofwhich
the caller should be aware.
The type declarations and constants that are used only by this data structure.
II-1.4.2 Protocol Descriptions
The protocols described in this document generally have the following format:
Protocol Name
The formal name of the protocol interface.
Summary
A brief description of the protocol interface.
GUID
The 128-bit Globally Unique Identifier (GUID) for the protocol interface.
A“C-style”datastructuredefinitioncontainingtheproceduresanddatafieldsproducedbythisprotocolinterface.
A brief description of each field in the protocol interface structure.
A description of the functionality provided by the interface, including any limitations and caveats of which the
caller should be aware.
II-1.4. Conventions Used in this Document II-3UEFI Platform Initialization Specification, Release 1.8
The type declarations and constants that are used in the protocol interface structure or any of its procedures.
II-1.4.3 Procedure Descriptions
ProcedureName()
The formal name of the procedure.
Summary
A brief description of the procedure.
Prototype
A “C-style” procedure header defining the calling sequence.
A brief description of each field in the procedure prototype.
The type declarations and constants that are used only by this procedure.
A description of any codes returned by the interface. The procedure is required to implement any status codes
listed in this table. Additional error codes may be returned, but they will not be tested by standard compli-
ance tests, and any software that uses the procedure cannot depend on any of the extended error codes that an
II-1.4.4 Instruction Descriptions
InstructionName
The formal name of the instruction.
Syntax
A brief description of the instruction.
Adescriptionofthefunctionalityprovidedbytheinstructionaccompaniedbyatablethatdetailstheinstruction
encoding.
Operation
Details the operations performed on operands.
Anitem-by-itemdescriptionofthebehaviorofeachoperandinvolvedintheinstructionandanyrestrictionsthat
apply to the operands or the instruction.
II-1.4. Conventions Used in this Document II-4UEFI Platform Initialization Specification, Release 1.8
II-1.4.5 Pseudo-Code Conventions
In describing variables, a listis an unordered collection of homogeneous objects. A queue is an ordered list of homo-
II-1.4.6 Typographic Conventions
Plain text
The normal text typeface is used for the vast majority of the descriptive text in a specification.
In the online help version of this specification, any plain text that is underlined and in blue indicates an active
link to the cross-reference. Click on the word to follow the hyperlink. Note that these links are not active in the
PDF of the specification.
Bold
In text, a Boldtypeface identifies a processor register name. In other instances, a Boldtypeface can be used as
a running head within a paragraph.
Italic
Intext,an Italictypefacecanbeusedasemphasistointroduceanewtermortoindicateamanualorspecification
name.
Computercode,examplecodesegments,andallprototypecodesegmentsusea BOLD Monospace typefacewith
a dark red color. These code listings normally appear in one or more separate paragraphs, though words or
segments can also be embedded in a normal text paragraph.
BoldMonospace Intheonlinehelpversionofthisspecification,wordsina BoldMonospace typefacethatisunderlined
andinblueindicateanactivehyperlinktothecodedefinitionforthatfunctionortypedefinition. Clickonthewordto
follow the hyperlink. Note that these links are not active in the PDF of the specification. Also, these inactive links in

Bold
Italic
name.
the PDF may instead have a Bold Monospace appearance that is underlined but in dark red. Again, these links are not
active in the PDF of the specification.
Italic Monospace In code or in text, words in Italic Monospace indicate placeholder names for variable information
that must be supplied (i.e., arguments).
Plain Monospace In code, words in a Plain Monospace typeface that is a dark red color but is not bold or italicized
indicate pseudo code or example code. These code segments typically occur in one or more separate paragraphs.
II-1.4. Conventions Used in this Document II-5UEFI Platform Initialization Specification, Release 1.8
II-1.5 Requirements
II-1.5. Requirements II-6UEFI Platform Initialization Specification, Release 1.8
II-1.6 Conventions used in this document
II-1.6.1 Number formats
II-1.6.2 Binary prefixes
brochure/chapter3/prefixes.html) for values that are powers of ten.
Table 1.2: SI prefixes
Table 1.3: Binary prefixes
II-1.6. Conventions used in this document II-7CHAPTER
TWO
OVERVIEW
II-2.1 Driver Execution Environment (DXE) Phase
The Driver Execution Environment (DXE) phase is where most of the system initialization is performed. Pre-EFI
Initialization (PEI), the phase prior to DXE, is responsible for initializing permanent memory in the platform so that
the DXE phase can be loaded and executed. The state of the system at the end of the PEI phase is passed to the DXE
phase through a list of position-independent data structures called Hand-Off Blocks (HOBs). HOBs are described in
detail inVolume 3 .
There are several components in the DXE phase:
•DXE Foundation
•DXE Dispatcher
•A set ofDXE Drivers
The DXE Foundation produces a set of Boot Services, Runtime Services, and DXE Services. The DXE Dispatcher
is responsible for discovering and executing DXE drivers in the correct order. The DXE drivers are responsible for
initializing the processor, chipset, and platform components as well as providing software abstractions for system ser-
vices, console devices, and boot devices. These components work together to initialize the platform and provide the
servicesrequiredtobootanoperatingsystem. TheDXEphaseandBootDeviceSelection(BDS)phasesworktogether
to establish consoles and attempt the booting of operating systems. The DXE phase is terminated when an operating
system is successfully booted. The DXE Foundation is composed of boot services code, so no code from the DXE
Foundation itself is allowed to persist into the OS runtime environment. Only the runtime data structures allocated by
theDXEFoundationandservicesanddatastructuredproducedbyruntimeDXEdriversareallowedtopersistintothe
OS runtime environment.
PI Architecture Firmware Phases shows the phases that a platform with PI Architecture firmware will execute.
In a PI Architecture firmware implementation, the phase executed prior to DXE is PEI. This specification covers the
transition from the PEI to the DXE phase, the DXE phase, and the DXE phase’s interaction with the BDS phase. The
DXE phase does not require a PEI phase to be executed. The only requirement for the DXE phase to execute is the
presence of a valid HOB list. There are many different implementations that can produce a valid HOB list for the
DXE phase to execute. The PEI phase in a PI Architecture firmware implementation is just one of many possible
II-8UEFI Platform Initialization Specification, Release 1.8
Fig. 2.1: PI Architecture Firmware Phases
II-2.2 UEFI System Table
II-2.2.1 Overview

TheUEFISystemTableispassedtoeveryexecutablecomponentintheDXEphase. TheUEFISystemTablecontains
a pointer to the following:
•UEFI Boot Services Table
•UEFI Runtime Services Table
ItalsocontainspointerstotheconsoledevicesandtheirassociatedI/Oprotocols. Inaddition, theUEFISystemTable
contains a pointer to the UEFI Configuration Table, and this table contains a list of GUID/pointer pairs. The UEFI
Configuration Table may include tables such as the DXE Services Dependencies , HOB list, ACPI table, SMBIOS
table, and SAL System table.
TheUEFIBootServicesTablecontainsservicestoaccessthecontentsofthehandledatabase. Thehandledatabaseis
whereprotocolinterfacesproducedbydriversareregistered. OtherdriverscanusetheUEFIBootServicestolookup
these services produced by other drivers.
All of the services available in the DXE phase may be accessed through a pointer to the UEFI System Table.
II-2.2.2 UEFI Boot Services Table
UEFIBootServices providesasummaryoftheservicesthatareavailablethroughtheUEFIBootServicesTable. These
servicesaredescribedindetailintheUEFI2.0specification. ThisDXECISmakesafewminor,backward-compatible
extensions to these services.
II-2.2. UEFI System Table II-9UEFI Platform Initialization Specification, Release 1.8
Table 2.1: UEFI Boot Services
UEFI Boot Services Description
Task Priority ProvidesservicestoincreaseordecreasethecurrenttaskprioritylevelThis
can be used to implement simple locks and to disable the timer interrupt
for short periods of time These services depend on the CPU Architectural
Protocol.
Memory Providesservicestoallocateandfreepagesin4KiBincrementsandallocate
andfreepoolonbyteboundariesItalsoprovidesaservicetoretrieveamap
of all the current physical memory usage in the platform
Event and Timer Provides services to create events signal events check the status of events
wait for events and close events One class of events is timer events and that
classsupportsperiodictimerswithvariablefrequenciesandoneshottimers
with variable durations These services depend on the CPU Architectural
Protocol, theTimer Architectural Protocol , theMetronome Architectural
Protocol, and theWatchdog Timer Architectural Protocol .
Protocol Handler Provides services to add and remove handles from the handle database It
also provides services to add and remove protocols from the handles in the
handledatabaseAdditionalservicesareavailablethatallowanycomponent
tolookuphandlesinthehandledatabaseandopenandcloseprotocolsinthe
handle database
Image Provides services to load start exit and unload images using the PE COFF
image format These services use the services of the Security Architectural
Protocolif it is present
Driver Support Provides services to connect and disconnect drivers to devices in the plat-
formTheseservicesareusedbytheBDSphasetoeitherconnectalldrivers
to all devices or to connect only the minimum number of drivers to devices
requiredtoestablishtheconsolesandbootanoperatingsystemTheminimal
connect strategy is one possible mechanism to reduce boot time
II-2.2.3 UEFI Runtime Services Table
UEFI Runtime Services provides a summary of the services that are available through the UEFI Runtime Services
Table. These services are described in detail in the UEFI 2.0 specification. One additional runtime service, Status
Code Services, is described in this specification.
UEFI Runtime Services Description
Variable Provides services to look up, add, and remove environment variables from
nonvolatile storage. These services depend on the Variable Architectural
Protocol and the Variable Write Architectural Protocol.
Real Time Clock Provides services to get and set the current time and date. It also provides
servicestogetandsetthetimeanddateofanoptionalwake-uptimer. These
services depend on the Real Time Clock Architectural Protocol.
Reset Providesservicestoshutdownorresettheplatform. Theseservicesdepend
on the Reset Architectural Protocol.
Virtual Memory Provides services that allow the runtime DXE components to be converted
from a physical memory map to a virtual memory map. These services can
onlybecalledonceinphysicalmode. Oncethephysicaltovirtualconversion
has been performed, these services cannot be called again. These services
depend on the Runtime Architectural Protocol.
II-2.2. UEFI System Table II-10UEFI Platform Initialization Specification, Release 1.8
II-2.2.4 DXE Services Table
DXE Services provides a summary of the services that are available through the DXE Services Table. These are new
services that are available in boot service time and are required only by the DXE Foundation and DXE drivers.
Table 2.3: DXE Services
DXE Services Description
Global Coherency Domain Provides services to manage I O resources memory mapped I O resources
and system memory resources in the platform These services are used to
dynamically add and remove these resources from the processor s global
coherency domain
Dispatcher Provides services to manage DXE drivers that are being dispatched by the
DXE Dispatcher
II-2.3 DXE Foundation
The DXE Foundation is a boot service image that is responsible for producing the following:
The DXE Foundation consumes a HOB list and the services of the DXE Architectural Protocols to produce the full
complement of UEFI Boot Services, UEFI Runtime Services, and DXE Services. The HOB list is described in detail
in theVolume 3 .
The DXE Foundation is an implementation of UEFI. The DXE Foundation defined in this specification is backward
compatiblewiththeUEFI2.0specification. Asaresult,boththeDXEFoundationandDXEdriverssharemanyofthe
attributes of UEFI images. Because this specification makes extensions to the standard UEFI interfaces, DXE images
will not be functional on UEFI systems that are not compliant with this DXE CIS. However, UEFI images must be
functional on all UEFI-compliant systems including those that are compliant with the DXE CIS.
II-2.4 DXE Dispatcher
The DXE Dispatcher is one component of the DXE Foundation. This component is required to discover DXE drivers
stored in firmware volumes and execute them in the proper order. The proper order is determine by a combination of
anapriorifilethatisoptionallystoredinthefirmwarevolumeandthedependencyexpressionsthatarepartoftheDXE
drivers. The dependency expression tells the DXE Dispatcher the set of services that a particular DXE driver requires
to be present for the DXE driver to execute. The DXE Dispatcher does not allow a DXE driver to execute until all of
the DXE driver’s dependencies have been satisfied. After all of the DXE drivers have been loaded and executed by
the DXE Dispatcher, control is handed to the BDS Architectural Protocol that is responsible for implementing a boot
policy that is compliant with the UEFI Boot Manager described in the UEFI 2.0 specification.
II-2.3. DXE Foundation II-11UEFI Platform Initialization Specification, Release 1.8
II-2.5 DXE Drivers
The DXE drivers are required to initialize the processor, chipset, and platform. They are also required to produce the
DXEArchitecturalProtocolsandanyadditionalprotocolservicesrequiredtoproduceI/Oabstractionsforconsolesand
boot devices.
II-2.6 DXE Architectural Protocols
The following table provides a summary of the Section II-12. The DXE Foundation is abstracted from the platform
throughtheDXEArchitecturalProtocols. TheDXEArchitecturalProtocolsmanifesttheplatform-specificcomponents
of the DXE Foundation. DXE drivers that are loaded and executed by the DXE Dispatcher component of the DXE
Foundation must produce these protocols.
Table 2.4: DXE Architectural Protocols
Protocol Name Description
Security Architectural AllowstheDXEFoundationtoauthenticatefilesstoredinfirmwarevolumes
before they are used
CPU Architectural Providesservicestomanagecachesmanageinterruptsretrievetheprocessor
s frequency and query any processor based timers
Metronome Architectural Provides the services required to perform very short calibrated stalls
Timer Architectural Providestheservicesrequiredtoinstallandenabletheheartbeattimerinter-
rupt required by the timer services in the DXE Foundation
BDS Architectural Provides an entry point that the DXE Foundation calls once after all of the
DXE drivers have been dispatched from all of the firmware volumes This
entrypointisthetransitionfromtheDXEphasetotheBootDeviceSelection
BDS phase and it is responsible for establishing consoles and enabling the
boot devices required to boot an OS
Watchdog Timer Architectural Providestheservicesrequiredtoenableanddisableawatchdogtimerinthe
platform
Runtime Architectural Provides the services required to convert all runtime services and runtime
drivers from physical mappings to virtual mappings
Variable Architectural Provides the services to retrieve environment variables and set volatile en-
vironment variables
Variable Write Architectural Proto-
colProvides the services to set nonvolatile environment variables

platform
Monotonic Counter Architectural Provides the services required by the DXE Foundation to manage a 64 bit
monotonic counter
Reset Architectural Provides the services required to reset or shutdown the platform
Real Time Clock Architectural Providestheservicestoretrieveandsetthecurrenttimeanddateaswellas
the time and date of an optional wake up timer
Capsule Architectural Protocol Providestheservicestoretrieveandsetthecurrenttimeanddateaswellas
II-2.5. DXE Drivers II-12UEFI Platform Initialization Specification, Release 1.8
II-2.7 Runtime Protocol
Status Codes Runtime Protocol provides a summary of the runtime protocol for status codes.
Table 2.5: Status Codes Runtime Protocol
Status Code Runtime
ProtocolProvidestheservicestosendstatuscodesfromtheDXEFoundationorDXEdriversto
a log or device.
II-2.7. Runtime Protocol II-13CHAPTER
THREE
II-3.1 Boot Manager
The Boot Manager in DXE executes after all the DXE drivers whose dependencies have been satisfied have been dis-
patchedbytheDXEDispatcher. Atthattime,controlishandedtotheBootDeviceSelection(BDS)phaseofexecution.
The BDSphase isresponsible forimplementing theplatform bootpolicy. System firmwarethat iscompliantwith this
specification must implement the boot policy specified in the Boot Manager chapter of the UEFI 2.0 specification.
This boot policy provides flexibility that allows system vendors to customize the user experience during this phase of
execution.
The Boot Manager must also support booting from a short-form device path that starts with the first node being a
firmware volume device path. The boot manager must use the GUID in the firmware volume device node to match it
to a firmware volume in the system. The GUID in the firmware volume device path is compared with the firmware
volume name GUID. If a match is made, then the firmware volume device path can be appended to the device path of
the matching firmware volume and normal boot behavior can then be used.
The BDS phase is implemented as part of the BDS Architectural Protocol. The DXE Foundation will hand control to
theBDSArchitecturalProtocolafteralloftheDXEdriverswhosedependencieshavebeensatisfiedhavebeenloaded
and executed by the DXE Dispatcher. The BDS phase is responsible for the following:
•Initializing console devices
•Loading device drivers
•Attempting to load and execute boot selections
IftheBDSphasecannotmakeforwardprogress,itwillreinvoketheDXEDispatchertoseeifthedependenciesofany
additional DXE drivers have been satisfied since the last time the DXE Dispatcher was invoked.
II-14CHAPTER
FOUR
UEFI SYSTEM TABLE
II-4.1 DXE Services Table
II-4.1.1 DXE_SERVICES
Summary
Contains a table header and pointers to all of the DXE-specific services.
//
// DXE Services Table
//
#define DXE_SERVICES_SIGNATURE 0x565245535f455844
#define DXE_SERVICES_REVISION PI_SPECIFICATION_VERSION
//
// Global Coherency Domain Services
//
EFI_ADD_MEMORY_SPACE AddMemorySpace;
EFI_ALLOCATE_MEMORY_SPACE AllocateMemorySpace;
EFI_FREE_MEMORY_SPACE FreeMemorySpace;
EFI_REMOVE_MEMORY_SPACE RemoveMemorySpace;
EFI_GET_MEMORY_SPACE_DESCRIPTOR GetMemorySpaceDescriptor;
EFI_SET_MEMORY_SPACE_ATTRIBUTES SetMemorySpaceAttributes;
EFI_GET_MEMORY_SPACE_MAP GetMemorySpaceMap;
EFI_ADD_IO_SPACE AddIoSpace;
EFI_ALLOCATE_IO_SPACE AllocateIoSpace;
EFI_FREE_IO_SPACE FreeIoSpace;
EFI_REMOVE_IO_SPACE RemoveIoSpace;
EFI_GET_IO_SPACE_DESCRIPTOR GetIoSpaceDescriptor;
EFI_GET_IO_SPACE_MAP GetIoSpaceMap;
//
// Dispatcher Services
//
EFI_DISPATCH Dispatch;
II-15UEFI Platform Initialization Specification, Release 1.8
EFI_SCHEDULE Schedule;
EFI_TRUST Trust;
//
// Service to process a single firmware volume found in
// a capsule
//
EFI_PROCESS_FIRMWARE_VOLUME ProcessFirmwareVolume;
//
// Extensions to Global Coherency Domain Services
//
EFI_SET_MEMORY_SPACE_CAPABILITIES SetMemorySpaceCapabilities;
} DXE_SERVICES;
Hdr
The table header for the DXE Services Table. This header contains the DXE_SERVICES_SIGNATURE and
DXE_SERVICES_REVISION valuesalongwiththesizeofthe DXE_SERVICES_TABLE structureanda32-bitCRC
to verify that the contents of the DXE Services Table are valid.
AddMemorySpace
Adds reserved memory, system memory, or memory-mapped I/O resources to the global coherency domain of
the processor. See the AddMemorySpace() function description in this document.
AllocateMemorySpace
Allocates nonexistent memory, reserved memory, system memory, or memory-mapped I/O resources from the
globalcoherencydomainoftheprocessor. Seethe AllocateMemorySpace() functiondescriptioninthisdoc-
ument.
FreeMemorySpace
Freesnonexistentmemory,reservedmemory,systemmemory,ormemory-mappedI/Oresourcesfromtheglobal
coherency domain of the processor. See the FreeMemorySpace() function description in this document.
RemoveMemorySpace
Removes reserved memory, system memory, or memory-mapped I/O resources from the global coherency do-
main of the processor. See the RemoveMemorySpace() function description in this document.
GetMemorySpaceDescriptor
Retrieves the descriptor for a memory region containing a specified address. See the
GetMemorySpaceDescriptor() function description in this document.
SetMemorySpaceAttributes
Modifies the attributes for a memory region in the global coherency domain of the processor. See the
SetMemorySpaceAttributes() function description in this document.
GetMemorySpaceMap
Returns a map of the memory resources in the global coherency domain of the processor. See the
GetMemorySpaceMap() function description in this document.
AddIoSpace
Adds reserved I/O or I/O resources to the global coherency domain of the processor. See the AddIoSpace()
function description in this document.
AllocateIoSpace
Allocates nonexistent I/O, reserved I/O, or I/O resources from the global coherency domain of the processor.
See theAllocateIoSpace() function description in this document.
II-4.1. DXE Services Table II-16UEFI Platform Initialization Specification, Release 1.8
FreeIoSpace
Frees nonexistent I/O, reserved I/O, or I/O resources from the global coherency domain of the processor. See
theFreeIoSpace() function description in this document.
RemoveIoSpace
Removes reserved I/O or I/O resources from the global coherency domain of the processor. See the
RemoveIoSpace() function description in this document.
GetIoSpaceDescriptor
Retrieves the descriptor for an I/O region containing a specified address. See the GetIoSpaceDescriptor()
GetIoSpaceMap
ReturnsamapoftheI/Oresourcesintheglobalcoherencydomainoftheprocessor. Seethe GetIoSpaceMap()
Dispatch
Loads and executed DXE drivers from firmware volumes. See the Dispatch() function description in this
document.
Schedule
Clears the Schedule on Request (SOR) flag for a component that is stored in a firmware volume. See the
Schedule() function description in this document.
Trust
Promotes a file stored in a firmware volume from the untrusted to the trusted state. See the Trust() function
ProcessFirmwareVolume
Creates a firmware volume handle for a firmware volume that is present in system memory. See the
ProcessFirmwareVolume() function description in this document.
SetMemorySpaceCapabilities
Modifies the capabilities for a memory region in the global coherency domain of the processor. See the
SetMemorySpaceCapabilities() function description in this document.
TheUEFIDXEServicesTablecontainsatableheaderandpointerstoalloftheDXE-specificservices. Exceptforthe
table header, all elements in the DXE Services Tables are prototypes of function pointers to functions as defined in
Services - DXE Services .
II-4.2 UEFI Image Entry Point Examples
II-4.2.1 UEFI Application Example
The following example shows the UEFI image entry point for an UEFI application. This application makes use of the
UEFI System Table, UEFI Boot Services Table, UEFI Runtime Services Table, and DXE Services Table.
EFI_GUID gEfiDxeServicesTableGuid = DXE_SERVICES_TABLE_GUID;
DXE_SERVICES *gDS;
II-4.2. UEFI Image Entry Point Examples II-17UEFI Platform Initialization Specification, Release 1.8
)
{
BOOLEAN Result;
UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemorySpaceDescriptor;
gDS = NULL;
for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
Result = EfiCompareGuid (
&gEfiDxeServicesTableGuid,
&(gST->ConfigurationTable[Index].VendorGuid)
);
if (Result) {
gDS = gST->ConfigurationTable[Index].VendorTable;
}
}
if (gDS == NULL) {
}
//

)
{
gDS = NULL;
);
}
}
}
//
// Use UEFI System Table to print “Hello World” to the active console
// output device.
//
Status = gST->ConOut->OutputString (gST->ConOut, L”Hello
World\n\r”);
}
//
// Use UEFI Boot Services Table to allocate a buffer to store the
// current time and date.
//
(VOID **)&Time
);
}
II-4.2. UEFI Image Entry Point Examples II-18UEFI Platform Initialization Specification, Release 1.8
//
// Use the UEFI Runtime Services Table to get the current
// time and date.
//
Status = gRT->GetTime (&Time, NULL)
}
//
// Use UEFI Boot Services to free the buffer that was used to store
// the current time and date.
//
Status = gBS->FreePool (Time);
}
//
// Use the DXE Services Table to get the current GCD Memory Space Map
//
Status = gDS->GetMemorySpaceMap (
&NumberOfDescriptors,
&MemorySpaceMap
);
}
//
// the GCD Memory Space Map.
//
Status = gBS->FreePool (MemorySpaceMap);
}
}
II-4.2. UEFI Image Entry Point Examples II-19UEFI Platform Initialization Specification, Release 1.8
II-4.2.2 Non-UEFI Driver Model Example (Resident in Memory)
The following example shows the UEFI image entry point for an UEFI driver that does not follow the UEFI Driver
Model. Because this driver returns EFI_SUCCESS , it will stay resident in memory after it exits.
)
{
gDS = NULL;
for(Index = 0; Index < gST->NumberOfTableEntries; Index++) {
);
if(Result) {
}
}
if(gDS == NULL) {
returnEFI_REQUEST_UNLOAD_IMAGE;
}
//
//
}
II-4.2. UEFI Image Entry Point Examples II-20UEFI Platform Initialization Specification, Release 1.8
II-4.2.3 Non-UEFI Driver Model Example (Nonresident inMemory)
ThefollowingexampleshowstheUEFIimageentrypointforanUEFIdriverthatalsodoesnotfollowthe UEFIDriver
Model. Becausethisdriverreturnstheerrorcode EFI_REQUEST_UNLOAD_IMAGE ,itwillnotstayresidentinmemory
after it exits.
)
{
gDS = NULL;
);
}
}
}
//
//
}
II-4.2. UEFI Image Entry Point Examples II-21UEFI Platform Initialization Specification, Release 1.8
II-4.2.4 UEFI Driver Model Example
The following is an UEFI Driver Model example that shows the driver initialization routine for the ABC device con-
troller that is on the XYZ bus. The EFI_DRIVER_BINDING_PROTOCOL is defined in Chapter 9 of the UEFI 2.0 speci-
fication. The function prototypes for the AbcSupported() ,AbcStart() , andAbcStop() functions are defined in
Section9.1oftheUEFI2.0specification. Thisfunctionsavesthedriver’simagehandleandapointertotheUEFIBoot
ServicesTableinglobalvariables,sothattheotherfunctionsinthesamedrivercanhaveaccesstothesevalues. Itthen
creates an instance of the EFI_DRIVER_BINDING_PROTOCOL and installs it onto the driver’s image handle.
AbcStart,
AbcStop,
0x10,
NULL,
NULL
};
)
{
NULL
);
}
II-4.2.5 UEFI Driver Model Example (Unloadable)
The following is the same UEFI Driver Model example as in the UEFI Driver Model Example, except that it also in-
cludesthecoderequiredtoallowthedrivertobeunloadedthroughthebootservice Unload() . Anyprotocolsinstalled
ormemoryallocatedin AbcEntryPoint() mustbeuninstalledorfreedinthe AbcUnload() . TheAbcUnload() func-
tion first checks to see how many controllers this driver is currently managing. If the number of controllers is greater
than zero, then this driver cannot be unloaded at this time, so an error is returned.
II-4.2. UEFI Image Entry Point Examples II-22UEFI Platform Initialization Specification, Release 1.8
AbcStart,
AbcStop,
1,
NULL,
NULL
};
);
)
{
NULL,
);
}
NULL
);
}
II-4.2. UEFI Image Entry Point Examples II-23UEFI Platform Initialization Specification, Release 1.8
)
{
UINTN Count;
Status = LibGetManagedControllerHandles (ImageHandle, &Count, NULL);
}
if(Count > 0) {
returnEFI_ACCESS_DENIED;
}
NULL
);
}
II-4.2.6 UEFI Driver Model Example (Multiple Instances)
The following is the same as the first UEFI Driver Model example, except that it produces three
EFI_DRIVER_BINDING_PROTOCOL instances. The first one is installed onto the driver’s image handle. The other
two are installed onto newly created handles.
AbcStopA,
1,
NULL,
NULL
};
AbcStopB,
1,
NULL,
NULL
};
II-4.2. UEFI Image Entry Point Examples II-24UEFI Platform Initialization Specification, Release 1.8
AbcStopC,
1,
NULL,
NULL
};
)
{
//
//
NULL
);
}
//
//
NULL
);
}
//
//
II-4.2. UEFI Image Entry Point Examples II-25UEFI Platform Initialization Specification, Release 1.8

//
NULL
);
}
//
//
NULL
);
}
//
//
NULL
);
}
II-4.2. UEFI Image Entry Point Examples II-26CHAPTER
FIVE
SERVICES - BOOT SERVICES
II-5.1 Extensions to UEFI Boot Service Event Usage
II-5.1.1 CreateEvent
CreateEventEx() in UEFI 2.0 allows for registration of events named by GUID’s. The DXE foundation defines the
#define EFI_EVENT_LEGACY_BOOT_GUID
{0x2a571201, 0x4966, 0x47f6, 0x8b, 0x86, 0xf3, 0x1e,
0x41, 0xf3, 0x2f, 0x10}
This event is to be used with CreateEventEx() in order to be notified when the UEFI boot manager is about to boot
a legacy boot option. Notification of events of this type is sent just before Int19h is invoked.
II-5.1.2 Pre-Defined Event Groups
This section describes the pre-defined event groups used by this specification.
EFI_EVENT_GROUP_DXE_DISPATCH_GUID
ThiseventgroupisnotifiedbythesystemwhentheDXEdispatcherfinishedoneroundofdriverdispatch. Thisallows
the SMM dispatcher get chance to dispatch SMM driver which will depend on UEFI protocols.
#define EFI_EVENT_GROUP_DXE_DISPATCH_GUID \
{ 0x7081e22f, 0xcac6, 0x4053, { 0x94, 0x68, 0x67, 0x57, \
0x82, 0xcf, 0x88, 0xe5 } \ }
II-5.1.2.1 End of DXE Event
PriortoinvokinganyUEFIdrivers,orapplicationsthatarenotfromtheplatformmanufacturer,orconnectingconsoles,
the platform should signals the event EFI_END_OF_DXE_EVENT_GUID End of DXE Event and immediately after that
the platform installs DXE SMM Ready to Lock Protocol (defined in volume 4).
#define EFI_END_OF_DXE_EVENT_GROUP_GUID \
{ 0x2ce967a, 0xdd7e, 0x4ffc, { 0x9e, 0xe7, 0x81, 0xc, \
0xf0, 0x47, 0x8, 0x80 } }
II-27UEFI Platform Initialization Specification, Release 1.8
From SEC through the signaling of this event, all of the components should be under the authority of the platform
manufacturer and not have to worry about interaction or corruption by 3rd party extensible modules such as UEFI
drivers and UEFI applications.
Platform may choose to lock certain resources or disable certain interfaces prior to executing third party extensible
modules. Transition from the environment where all of the components are under the authority of the platform manu-
facturer to the environment where third party modules are executed is a two-step process:
1. End of DXE Event is signaled. This event presents the last opportunity to use resources or interfaces that are
going to be locked or disabled in anticipation of the invocation of 3rd party extensible modules.
2. DXE SMM Ready to Lock Protocol is installed. PI modules that need to lock or protect their resources in
anticipation of the invocation of 3rd party extensible modules should register for notification on installation of
this protocol and effect the appropriate protections in their notification handlers
II-5.1.3 Additions to LoadImage()
Summary
Loads an UEFI image into memory. This function has been extended from the LoadImage() Boot Service defined
in the UEFI 2.0 specification. The DXE foundation extends this to support an additional image type, allowing UEFI
imagestobeloadedfromfilesstoredinfirmwarevolumes. ItalsovalidatestheimageusingtheservicesoftheSecurity
Architectural Protocol.
Prototype
LoadImage (
IN EFI_DEVICE_PATH *FilePath,
IN VOID *SourceBuffer OPTIONAL ,
);
BootPolicy
IfTRUE,indicatesthattherequestoriginatesfromthebootmanager,andthatthebootmanagerisattemptingto
loadFilePath as a boot selection. Ignored if SourceBuffer is notNULL.
ParentImageHandle
The caller’s image handle. Type EFI_HANDLE is defined in the InstallProtocolInterface() function
description in the UEFI 2.0 specification. This field is used to initialize the ParentHandle field of the
LOADED_IMAGE protocol for the image that is being loaded.
FilePath
The specific file path from which the image is loaded. Type EFI_DEVICE_PATH is defined in the
LocateDevicePath() function description in the UEFI 2.0 specification.
SourceBuffer
If notNULL, a pointer to the memory location containing a copy of the image to be loaded.
SourceSize
The size in bytes of SourceBuffer . Ignored if SourceBuffer isNULL.
II-5.1. Extensions to UEFI Boot Service Event Usage II-28UEFI Platform Initialization Specification, Release 1.8
ImageHandle
Pointertothereturnedimagehandlethatiscreatedwhentheimageissuccessfullyloaded. Type EFI_HANDLE is
defined in the InstallProtocolInterface() function description in the UEFI 2.0 specification.
TheLoadImage() function loads an UEFI image into memory and returns a handle to the image. The supported
subsystem values in the PE image header are listed in “Related Definitions” below. The image is loaded in one of two
ways. IfSourceBuffer isnotNULL,thefunctionisamemory-to-memoryloadinwhich SourceBuffer pointstothe
imagetobeloadedand SourceSize indicatestheimage’ssizeinbytes. FilePath specifieswheretheimagespecified
bySourceBuffer andSourceSize wasloaded. Inthiscase,thecallerhascopiedtheimageinto SourceBuffer and
can free the buffer once loading is complete.
IfSourceBuffer isNULL, the function is a file copy operation that uses the EFI_FIRMWARE_VOLUME2_PROTOCOL ,
followed by the SIMPLE_FILE_SYSTEM_PROTOCOL and then the LOAD_FILE_PROTOCOL to access the file referred to
byFilePath . In this case, the BootPolicy flag is passed to the LOAD_FILE.LoadFile() function and is used to
loadthedefaultimageresponsibleforbootingwhenthe FilePath onlyindicatesthedevice. Formoreinformationsee
the discussion of the Load File Protocol in Chapter 11 of the UEFI 2.0 specification.
Regardless of the type of load (memory-to-memory or file copy), the function relocates the code in the image while
loading it.
The image is also validated using the FileAuthenticationState() service of the Security Architectural Pro-
tocol (SAP). If the SAP returns the status EFI_SUCCESS , then the load operation is completed normally. If
the SAP returns the status EFI_SECURITY_VIOLATION , then the load operation is completed normally, and the
EFI_SECURITY_VIOLATION status is returned. In this case, the caller is not allowed to start the image until some
platformspecificpolicyisexecutedtoprotectthesystemwhileexecutinguntrustedcode. IftheSAPreturnsthestatus
EFI_ACCESS_DENIED ,thentheimageshouldneverbetrusted. Inthiscase,theimageisunloadedfrommemory,and
Once the image is loaded, firmware creates and returns an EFI_HANDLE that identifies the image and supports the
LOADED_IMAGE_PROTOCOL .Thecallermayfillintheimage’s“loadoptions”data,oraddadditionalprotocolsupport
to the handle before passing control to the newly loaded image by calling StartImage() . Also, once the image is
loaded, the caller either starts it by calling StartImage() or unloads it by calling UnloadImage() .
// Supported subsystem values
#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13
Supported Subsystem Values describes the fields in the above definition.
II-5.1. Extensions to UEFI Boot Service Event Usage II-29UEFI Platform Initialization Specification, Release 1.8
Table 5.1: Supported Subsystem Values
Supported Subsystem Values Description
EFI_IMAGE_SUBSYSTEM_EFI _APPLI-
CATIONTheimageisloadedintomemoryoftype EfiLoaderCode ,andthe
memory is freed when the application exits
EFI_IMAGE_SUBSYSTEM_EFI
_BOOT_SERVICE_DRIVERTheimageisloadedintomemoryoftype EfiBootServicesCode .
Iftheimageexitswithanerrorcode,thenthememoryfortheimage
isfree. Iftheimageexitswith EFI_SUCCESS ,thenthememoryfor
the image is not freed.
EFI_IMAGE_SUBSYSTEM_EFI _RUN-
TIME_DRIVERThe image is loaded intoThe image is loaded into memory of
typeEfiRuntimeServicesCode . If the image exits with an
error code, then the memory for the image is free. If the im-
age exits with EFI_SUCCESS , then the memory for the image is
not freed. Images of this type are automatically converted from
physical addresses to virtual address when the Runtime Service
SetVirtualAddressMap() is called.
EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER The image is loaded intoThe image is loaded into memory of type
EfiRuntimeServicesCode . Iftheimageexitswithanerrorcode,
then the memory for the image is free. If the image exits with
EFI_SUCCESS , then the memory for the image is not freed. Im-
agesofthistypearenotconvertedfromphysicaladdressestovirtual
address when the Runtime Service SetVirtualAddressMap() is
called.
Table 5.2: Status Codes Returned
EFI_SUCCESS The image was loaded into memory
EFI_SECURITY_VIOLATION The image was loaded into memory but the current security policy
dictates that the image should not be executed at this time

called.
EFI_ACCESS_DENIED Theimagewasnotloadedintomemorybecausethecurrentsecurity
policy dictates that the image should never be executed
EFI_NOT_FOUND TheFilePath was not found
EFI_INVALID_PARAMETER One of the parameters has an invalid value
EFI_UNSUPPORTED Theimagetypeisnotsupportedorthedevicepathcannotbeparsed
to locate the proper protocol for loading the file
EFI_OUT_OF_RESOURCES Image was not loaded due to insufficient resources
EFI_LOAD_ERROR Image was not loaded because the image format was corrupt or not
understood
EFI_DEVICE_ERROR Image was not loaded because the device returned a read error
II-5.1. Extensions to UEFI Boot Service Event Usage II-30CHAPTER
SIX
RUNTIME CAPABILITIES
II-6.1 Additional Runtime Protocol
II-6.1.1 Status Code Services
Status Code Runtime Protocol lists the runtime protocol that are used to report status codes. This protocol provides a
runtime protocol that can be bound by other runtime drivers for reporting status information.
Table 6.1: Status Code Runtime Protocol
ReportStatusCode Runtime Reports status codes at boot services time and runtime
II-31CHAPTER
SEVEN
SERVICES - DXE SERVICES
II-7.1 Introduction
This chapter describes the services in the DXE Services Table. These services include the following:
•Global Coherency Domain (GCD) Services
•Dispatcher Services
The GCD Services are used to manage the system memory, memory-mapped I/O, and I/O resources present in a plat-
form. The Dispatcher Services are used to invoke the DXE Dispatcher and modify the state of a DXE driver that is
being tracked by the DXE Dispatcher.
II-7.2 Global Coherency Domain Services
II-7.2.1 Global Coherency Domain (GCD) Services Overview
TheGlobalCoherencyDomain(GCD)ServicesareusedtomanagethememoryandI/Oresourcesvisibletotheboot
processor. These resources are managed in two different maps:
•GCD memory space map
•GCD I/O space map
If memory or I/O resources are added, removed, allocated, or freed, then the GCD memory space map and GCD I/O
space map are updated. GCD Services are also provided to retrieve the contents of these two resource maps.
The GCD Services can be broken up into two groups. The first manages the memory resources visible to the boot
processor,andthesecondmanagestheI/Oresourcesvisibletothebootprocessor. NotallprocessortypessupportI/O
resources, so the management of I/O resources may not be required. However, since system memory resources and
memory-mapped I/O resources are required to execute the DXE environment, the management of memory resources
is always required.
II-32UEFI Platform Initialization Specification, Release 1.8
II-7.2.2 GCD Memory Resources
The Global Coherency Domain (GCD) Services used to manage memory resources include the following:
•AddMemorySpace()
•AllocateMemorySpace()
•FreeMemorySpace()
•RemoveMemorySpace()
•SetMemorySpaceAttributes()
•SetMemorySpaceCapabilities()
The GCD Services used to retrieve the GCD memory space map include the following:
•GetMemorySpaceDescriptor()
•GetMemorySpaceMap()
TheGCDmemoryspacemapisinitializedfromtheHOBlistthatispassedtotheentrypointoftheDXEFoundation.
OneHOBtypedescribesthenumberofaddresslinesthatareusedtoaccessmemoryresources. Thisinformationisused
toinitializethestateoftheGCDmemoryspacemap. Anymemoryregionsoutsidethisinitialregionarenotavailable
to any of the GCD Services that are used to manage memory resources. The GCD memory space map is designed to
describe the memory address space with as many as 64 address lines. Each region in the GCD memory space map
can begin and end on a byte boundary. There are additional HOB types that describe the location of system memory,
the location memory mapped I/O, the location of firmware devices, the location of firmware volumes, the location of
reserved regions, and the location of system memory regions that were allocated prior to the execution of the DXE
Foundation. TheDXEFoundationmustparsethecontentsoftheHOBlisttoguaranteethatmemoryregionsreserved
prior to the execution of the DXE Foundation are honored. As a result, the GCD memory space map must reflect
the memory regions described in the HOB list. The GCD memory space map provides the DXE Foundation with the
informationrequiredtoinitializethememoryservicessuchas AllocatePages() ,FreePages() ,AllocatePool()
,FreePool() , andGetMemoryMap() . See the UEFI 2.0 specification for definitions of these services.
A memory region described by the GCD memory space map can be in one of several different states:
•Nonexistent memory
•System memory
•Memory-mapped I/O
•Reserved memory
These memory regions can be allocated and freed by DXE drivers executing in the DXE environment. In addition, a
DXE driver can attempt to adjust the caching attributes of a memory region. GCD Memory State Transitions shows
thepossiblestatetransitionsforeachbyteofmemoryintheGCDmemoryspacemap. Thetransitionsarelabeledwith
the GCD Service that can move the byte from one state to another. The GCD services are required to merge similar
memory regions that are adjacent to each other into a single memory descriptor, which reduces the number of entries
in the GCD memory space map.
II-7.2. Global Coherency Domain Services II-33UEFI Platform Initialization Specification, Release 1.8
Fig. 7.1: GCD Memory State Transitions
II-7.2.3 GCD I/O Resources
The Global Coherency Domain (GCD) Services used to manage I/O resources include the following:
•AddIoSpace()
•AllocateIoSpace()
•FreeIoSpace()
•RemoveIoSpace()
The GCD Services used to retrieve the GCD I/O space map include the following:
•GetIoSpaceDescriptor()
•GetIoSpaceMap()
TheGCDI/OspacemapisinitializedfromtheHOBlistthatispassedtotheentrypointoftheDXEFoundation. One
HOB type describes the number of address lines that are used to access I/O resources. This information is used to
initializethestateoftheGCDI/Ospacemap. AnyI/Oregionsoutsidethisinitialregionarenotavailabletoanyofthe
GCDServicesthatareusedtomanageI/Oresources. TheGCDI/OspacemapisdesignedtodescribetheI/Oaddress
spacewithasmanyas64addresslines. EachregionintheGCDI/Ospacemapcanbeingandendonabyteboundary.
An I/O region described by the GCD I/O space map can be in several different states. These include nonexistent I/O,
I/O,andreservedI/O.TheseI/OregionscanbeallocatedandfreedbyDXEdriversexecutingintheDXEenvironment.
GCD I/O State Transitions shows the possible state transitions for each byte of I/O in the GCD I/O space map. The
transitions are labeled with the GCD Service that can move the byte from one state to another. The GCD Services are
required to merge similar I/O regions that are adjacent to each other into a single I/O descriptor, which reduces the
number of entries in the GCD I/O space map.
II-7.2. Global Coherency Domain Services II-34UEFI Platform Initialization Specification, Release 1.8
Fig. 7.2: GCD I/O State Transitions
II-7.2.4 Global Coherency Domain Services
The functions that make up Global Coherency Domain (GCD) Services are used during preboot to add, remove, al-
locate, free, and provide maps of the system memory, memory-mapped I/O, and I/O resources in a platform. These
services, used in conjunction with the Memory Allocation Services, provide the ability to manage all the memory
and I/O resources in a platform. Global Coherency Domain Boot Type Services lists the Global Coherency Domain
Services.
II-7.2. Global Coherency Domain Services II-35UEFI Platform Initialization Specification, Release 1.8
Table 7.1: Global Coherency Domain Boot Type Services
AddMemorySpace ThisserviceaddsreservedmemorysystemmemoryormemorymappedIO
resources to the global coherency domain of the processor
AllocateMemorySpace This service allocates nonexistent memory reserved memory system mem-
oryormemorymappedIOresourcesfromtheglobalcoherencydomainof
the processor
FreeMemorySpace This service frees nonexistent memory reserved memory system memory
or memory mapped I O resources from the global coherency domain of the
processor
RemoveMemorySpace Thisserviceremovesreservedmemorysystemmemoryormemorymapped
I O resources from the global coherency domain of the processor
GetM emorySpaceDescriptor Thisserviceretrievesthedescriptorforamemoryregioncontainingaspec-
ified address
SetM emorySpaceAttributes This service modifies the attributes for a memory region in the global co-
herency domain of the processor
SetMem orySpaceCapabilities Thisservicemodifiesthecapabilitiesforamemoryregionintheglobalco-
GetMemorySpaceMap Returns a map of the memory resources in the global coherency domain of
AddIoSpace This service adds reserved I O or I O resources to the global coherency do-
main of the processor
AllocateIoSpace ThisserviceallocatesnonexistentIOreservedIOorIOresourcesfromthe
global coherency domain of the processor
FreeIoSpace This service frees nonexistent I O reserved I O or I O resources from the
RemoveIoSpace ThisserviceremovesreservedIOorIOresourcesfromtheglobalcoherency
domain of the processor

GetIoSpaceDescriptor ThisserviceretrievesthedescriptorforanIOregioncontainingaspecified
address
GetIoSpaceMap Returns a map of the I O resources in the global coherency domain of the
processor
II-7.2.4.1 AddMemorySpace()
Summary
Thisserviceaddsreservedmemory,systemmemory,ormemory-mappedI/Oresourcestotheglobalcoherencydomain
of the processor.
Prototype
typedef
(EFIAPI *EFI_ADD_MEMORY_SPACE) (
IN EFI_GCD_MEMORY_TYPE GcdMemoryType,
IN UINT64 Capabilities
);
II-7.2. Global Coherency Domain Services II-36UEFI Platform Initialization Specification, Release 1.8
GcdMemoryType
The type of memory resource being added. Type EFI_GCD_MEMORY_TYPE is defined in “Related Defini-
tions”below. Theonlytypesallowedare EfiGcdMemoryTypeReserved ,EfiGcdMemoryTypeSystemMemory
,EfiGcdMemoryTypePersistent ,EfiGcdMemoryTypeMoreReliable ,EfiGcdMemoryTypeUnaccepted ,
andEfiGcdMemoryTypeMemoryMappedIo .
BaseAddress
The physical address that is the start address of the memory resource being added. Type
EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function description in the UEFI 2.0 specifica-
tion.
Length
The size, in bytes, of the memory resource that is being added.
Capabilities
The bit mask of attributes that the memory resource region supports. The bit mask of available attributes is
defined in the GetMemoryMap() function description in the UEFI 2.0 specification.
TheAddMemorySpace() function converts unallocated non-existent memory ranges to a range of reserved memory,
a range of system memory, or a range of memory mapped I/O. BaseAddress andLengthspecify the memory range,
andGcdMemoryType specifiesthememorytype. Thebitmaskofallsupportedattributesforthememoryrangebeing
added is specified by Capabilities . If the memory range is successfully added, then EFI_SUCCESS is returned.
If the memory range specified by BaseAddress andLengthis of type EfiGcdMemoryTypeSystemMemory or
EfiGcdMemoryTypeMoreReliable , then the memory range may be automatically allocated for use by the UEFI
memory services. If the addition of the memory range specified by BaseAddress andLengthresults in a GCD
memory space map containing one or more 4 KiB regions of unallocated EfiGcdMemoryTypeSystemMemory or
EfiGcdMemoryTypeMoreReliable aligned on 4 KiB boundaries, then those regions will always be converted to
ranges of allocated EfiGcdMemoryTypeSystemMemory orEfiGcdMemoryTypeMoreReliable respectively. This
extra conversion will never be performed for fragments of memory that do not meet the above criteria.
If the GCD memory space map contains adjacent memory regions that only differ in their base address and length
fields, then those adjacent memory regions must be merged into a single memory descriptor.
IfLengthis zero, then EFI_INVALID_PARAMETER is returned.
IfGcdMemoryType is not EfiGcdMemoryTypeReserved ,EfiGcdMemoryTypeSystemMemory ,
EfiGcdMemoryTypeMemoryMappedIo ,EfiGcdMemoryPersistent ,EfiGcdMemoryTypeMoreReliable ,
orEfiGcdMemoryTypeUnaccepted thenEFI_INVALID_PARAMETER is returned.
Iftheprocessordoesnotsupportoneormorebytesofthememoryrangespecifiedby BaseAddress andLength,then
If any portion of the memory range specified by BaseAddress andLength is not of type
EfiGcdMemoryTypeNonExistent , thenEFI_ACCESS_DENIED is returned.
If any portion of the memory range specified by BaseAddress andLengthwas allocated in a prior call to
AllocateMemorySpace() , thenEFI_ACCESS_DENIED is returned.
If there are not enough system resources available to add the memory resource to the global coherency domain of the
processor, then EFI_OUT_OF_RESOURCES is returned.
// EFI_GCD_MEMORY_TYPE
II-7.2. Global Coherency Domain Services II-37UEFI Platform Initialization Specification, Release 1.8
EfiGcdMemoryTypeNonExistent,
EfiGcdMemoryTypeReserved,
EfiGcdMemoryTypeSystemMemory,
EfiGcdMemoryTypeMemoryMappedIo,
EfiGcdMemoryTypePersistent,
EfiGcdMemoryTypeMoreReliable,
EfiGcdMemoryTypeUnaccepted,
EfiGcdMemoryTypeMaximum
} EFI_GCD_MEMORY_TYPE;
EfiGcdMemoryTypeNonExistent
Amemoryregionthatisvisibletothebootprocessor. However,therearenosystemcomponentsthatarecurrently
decoding this memory region.
EfiGcdMemoryTypeReserved
A memory region that is visible to the boot processor. This memory region is being decoded by a system com-
ponent, but the memory region is not considered to be either system memory or memory-mapped I/O.
EfiGcdMemoryTypeSystemMemory
A memory region that is visible to the boot processor. A memory controller is currently decoding this memory
region and the memory controller is producing a tested system memory region that is available to the memory
services.
EfiGcdMemoryTypeMemoryMappedIo
A memory region that is visible to the boot processor. This memory region is currently being decoded by a
component as memory-mapped I/O that can be used to access I/O devices in the platform.
EfiGcdMemoryTypePersistent
A memory region that is visible to the boot processor. This memory supports byte-addressable non-volatility.
EfiGcdMemoryTypeMoreReliable
A memory region that provides higher reliability relative to other memory in the system. If all memory has the
same reliability, then this bit is not used.
EfiGcdMemoryTypeUnaccepted
Amemoryregionthatisunaccepted. Thisregionmustbeacceptedbeforeitcanbeconvertedtosystemmemory.
EFI_SUCCESS Thememoryresourcewasaddedtotheglobalcoherencydomainof
EFI_INVALID_PARAMETER GcdMemoryType is invalid
EFI_INVALID_PARAMETER Lengthis zero
EFI_OUT_OF_RESOURCES Therearenotenoughsystemresourcestoaddthememoryresource
to the global coherency domain of the processor
EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
resource range specified by BaseAddress andLength
EFI_ACCESS_DENIED One or more bytes of the memory resource range specified by
BaseAddress andLengthconflictswithamemoryresourcerange
thatwaspreviouslyaddedtotheglobalcoherencydomainofthepro-
cessor
EFI_ACCESS_DENIED One or more bytes of the memory resource range specified
byBaseAddress andLengthwas allocated in a prior call to
II-7.2. Global Coherency Domain Services II-38UEFI Platform Initialization Specification, Release 1.8
II-7.2.4.2 AllocateMemorySpace()
Summary
Thisserviceallocatesnonexistentmemory,reservedmemory,systemmemory,ormemory-mappedI/Oresourcesfrom
the global coherency domain of the processor.
Prototype
typedef
(EFIAPI \*EFI_ALLOCATE_MEMORY_SPACE) (
IN EFI_GCD_ALLOCATE_TYPE GcdAllocateType,
IN UINTN Alignment,
IN OUT EFI_PHYSICAL_ADDRESS *BaseAddress,
IN EFI_HANDLE DeviceHandle OPTIONAL
);
GcdAllocateType
The type of allocation to perform. Type EFI_GCD_ALLOCATE_TYPE is defined in “Related Definitions” below.
The type of memory resource being allocated. Type EFI_GCD_MEMORY_TYPE is defined
inAddMemorySpace() . The only types allowed are EfiGcdMemoryTypeNonExistent ,
EfiGcdMemoryTypeReserved ,EfiGcdMemoryTypeSystemMemory ,EfiGcdMemoryTypePersistent,
EfiGcdMemoryTypeMoreReliable andEfiGcdMemoryTypeMemoryMappedIo .
Alignment
The log base 2 of the boundary that BaseAddress must be aligned on output. For example, a value of 0 means
thatBaseAddress can be aligned on any byte boundary, and a value of 12 means that BaseAddress must be
aligned on a 4 KiB boundary.
Length
The size in bytes of the memory resource range that is being allocated.
Apointertoaphysicaladdress. Oninput,thewayinwhichtheaddressisuseddependsonthevalueof Type. See
“Description”belowformoreinformation. Onoutputtheaddressissettothebaseofthememoryresourcerange
thatwasallocated. Type EFI_PHYSICAL_ADDRESS isdefinedinthe AllocatePages() functiondescriptionin
the UEFI 2.0 specification.
The image handle of the agent that is allocating the memory resource. Type EFI_HANDLE is defined in
InstallProtocolInterface() in the UEFI 2.0 specification.
DeviceHandle
The device handle for which the memory resource is being allocated. If the memory resource is not being
allocated for a device that has an associated device handle, then this parameter is optional and may be NULL.
TypeEFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 specification.
TheAllocateMemorySpace() function searches for a memory range of type GcdMemoryType and converts the
discovered memory range from the unallocated state to the allocated state. The parameters GcdAllocateType ,
Alignment ,Length, andBaseAddress specify the manner in which the GCD memory space map is searched.
II-7.2. Global Coherency Domain Services II-39UEFI Platform Initialization Specification, Release 1.8

If a memory range is found that meets the search criteria, then the base address of the memory range is returned
inBaseAddress , andEFI_SUCCESS is returned. ImageHandle andDeviceHandle are used to convert the
memory range from the unallocated state to the allocated state. ImageHandle identifies the image that is calling
AllocateMemorySpace() , andDeviceHandle identifies the device that ImageHandle is managing that requires
the memory range. DeviceHandle is optional, because the device that ImageHandle is managing might not have
an associated device handle. If a memory range meeting the search criteria cannot be found, then EFI_NOT_FOUND is
returned.
IfGcdAllocateType isEfiGcdAllocateAnySearchBottomUp ,thentheGCDmemoryspacemapissearchedfrom
the lowest address up to the highest address looking for unallocated memory ranges of Lengthbytes beginning on a
boundary specified by Alignment that matches GcdMemoryType .
IfGcdAllocateType isEfiGcdAllocateAnySearchTopDown , thenthe GCDmemory space mapis searchedfrom
the highest address down to the lowest address looking for unallocated memory ranges of Lengthbytes beginning on
a boundary specified by Alignment that matches GcdMemoryType .
IfGcdAllocateType isEfiGcdAllocateMaxAddressSearchBottomUp , then the GCD memory space map is
searched from the lowest address up to BaseAddress looking for unallocated memory ranges of Lengthbytes be-
ginning on a boundary specified by Alignment that matches GcdMemoryType .
IfGcdAllocateType isEfiGcdAllocateMaxAddressSearchTopDown , then the GCD memory space map is
searched from BaseAddress down to the lowest address looking for unallocated memory ranges of Lengthbytes
beginning on a boundary specified by Alignment that matches GcdMemoryType .
IfGcdAllocateType isEfiGcdAllocateAddress ,thentheGCDmemoryspacemapischeckedtoseeifthememory
rangestartingat BaseAddress forLengthbytesisoftype GcdMemoryType ,unallocated,andbeginsonatheboundary
specified by Alignment .
IfBaseAddress isNULL, thenEFI_INVALID_PARAMETER is returned.
IfImageHandle isNULL, thenEFI_INVALID_PARAMETER is returned.
IfGcdMemoryType is not EfiGcdMemoryTypeNonExistent ,EfiGcdMemoryTypeReserved ,
EfiGcdMemoryTypeSystem Memory ,EfiGcdMemoryTypePersistent ,EfiGcdMemoryTypeMemoryMappedIo ,
EfiGcdMemoryTypeMoreReliable , thenEFI_INVALID_PARAMETER is returned.
IfGcdAlocateType is less than zero, or GcdAllocateType is greater than or equal to EfiGcdMaxAllocateType
thenEFI_INVALID_PARAMETER is returned.
If there are not enough system resources available to allocate the memory range, then EFI_OUT_OF_RESOURCES is
returned.
// EFI_GCD_ALLOCATE_TYPE
EfiGcdAllocateAnySearchBottomUp,
EfiGcdAllocateMaxAddressSearchBottomUp,
EfiGcdAllocateAddress,
EfiGcdAllocateAnySearchTopDown,
EfiGcdAllocateMaxAddressSearchTopDown,
EfiGcdMaxAllocateType
} EFI_GCD_ALLOCATE_TYPE;
II-7.2. Global Coherency Domain Services II-40UEFI Platform Initialization Specification, Release 1.8
Table 7.2: Status Codes Returned
EFI_SUCCESS The memory resource was allocated from the global coherency do-
EFI_INVALID_PARAMETER GcdAllocateType is invalid
EFI_INVALID_PARAMETER BaseAddress isNULL
EFI_INVALID_PARAMETER ImageHandle isNULL
EFI_OUT_OF_RESOURCES There are not enough system resources to allocate the memory re-
source from the global coherency domain of the processor
EFI_NOT_FOUND The memory resource request could not be satisfied
II-7.2.4.3 FreeMemorySpace()
Summary
Thisservicefreesnonexistentmemory,reservedmemory,systemmemory,ormemory-mappedI/Oresourcesfromthe
global coherency domain of the processor.
Prototype
typedef
(EFIAPI *EFI_FREE_MEMORY_SPACE) (
);
Thephysicaladdressthatisthestartaddressofthememoryresourcebeingfreed. Type EFI_PHYSICAL_ADDRESS
is defined in the AllocatePages() function description in the UEFI 2.0 specification.
Length
The size in bytes of the memory resource range that is being freed.
TheFreeMemorySpace() function converts the memory range specified by BaseAddress andLengthfrom the al-
located state to the unallocated state. If this conversion is successful, then EFI_SUCCESS is returned.
Ifoneormorebytesofthememoryrangespecifiedby BaseAddress andLengthwerenotallocatedonpreviouscalls
toAllocateMemorySpace() , thenEFI_NOT_FOUND is returned.
Iftherearenotenoughsystemresourcesavailabletofreethememoryrange,then EFI_OUT_OF_RESOURCES isreturned.
II-7.2. Global Coherency Domain Services II-41UEFI Platform Initialization Specification, Release 1.8
Table 7.3: Status Codes Returned
EFI_SUCCESS The memory resource was freed from the global coherency domain of the processor
EFI_UNSUPPORTED The processor does not support one or more bytes of the memory resource range specified
byBaseAddress andLength
EFI_NOT_FOUND Thememoryresourcerangespecifiedby BaseAddress andLengthwasnotallocatedwith
previous calls to AllocateMemorySpace
EFI_OUT_OF_RESOURCES There are not enough system resources to free the memory resource from the global co-
II-7.2.4.4 RemoveMemorySpace()
Summary
Thisserviceremovesreservedmemory,systemmemory,ormemory-mappedI/Oresourcesfromtheglobalcoherency
domain of the processor.
Prototype
typedef
(EFIAPI *EFI_REMOVE_MEMORY_SPACE) (
);
The physical address that is the start address of the memory resource being removed. Type
EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function description in the UEFI 2.0 specifi-
cation.
Length
The size in bytes of the memory resource that is being removed.
TheRemoveMemorySpace() functionconvertsthememoryrangespecifiedby BaseAddress andLengthtothemem-
ory typeEfiGcdMemoryTypeNonExistent . If this conversion is successful, then EFI_SUCCESS is returned.
Ifoneormorebytesofthememoryrangespecifiedby BaseAddress andLengthwerenotaddedtotheGCDmemory
space map with previous calls to AddMemorySpace() , thenEFI_NOT_FOUND is returned.
If one or more bytes of the memory range specified by BaseAddress andLengthwere allocated from the GCD
memory space map with previous calls to AllocateMemorySpace() , thenEFI_ACCESS_DENIED is returned.
If there are not enough system resources available to remove the memory range, then EFI_OUT_OF_RESOURCES is
returned.
II-7.2. Global Coherency Domain Services II-42UEFI Platform Initialization Specification, Release 1.8
Table 7.4: Status Codes Returned
EFI_SUCCESS The memory resource was removed from the global coherency do-
EFI_NOT_FOUND One or more bytes of the memory resource range specified by
BaseAddress andLengthwas not added with previous calls to
EFI_ACCESS_DENIED One or more bytes of the memory resource range speci-
fied byBaseAddress andLength has been allocated with
EFI_OUT_OF_RESOURCES There are not enough system resources to remove the memory re-
II-7.2.4.5 GetMemorySpaceDescriptor()
Summary
This service retrieves the descriptor for a memory region containing a specified address.
Prototype
typedef
(EFIAPI *EFI_GET_MEMORY_SPACE_DESCRIPTOR) (
OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
);
The physical address that is the start address of a memory region. Type EFI_PHYSICAL_ADDRESS is defined
in theAllocatePages() function description in the UEFI 2.0 specification.
Descriptor

Summary
Prototype
typedef
);
A pointer to a caller allocated descriptor. On return, the descriptor describes the memory region containing
BaseAddress . TypeEFI_GCD_MEMORY_SPACE_DESCRIPTOR is defined in “Related Definitions” below.
TheGetMemorySpaceDescriptor() functionretrievesthedescriptorforthememoryregionthatcontainstheaddress
specifiedby BaseAddress . Ifamemoryregioncontaining BaseAddress isfound,thenthedescriptorforthatmemory
region is returned in the caller allocated structure Descriptor , andEFI_SUCCESS is returned.
IfDescriptor isNULL, thenEFI_INVALID_PARAMETER is returned.
If amemory regioncontaining BaseAddress is notpresent inthe GCD memoryspace map, then EFI_NOT_FOUND is
returned.
// EFI_GCD_MEMORY_SPACE_DESCRIPTOR
II-7.2. Global Coherency Domain Services II-43UEFI Platform Initialization Specification, Release 1.8
EFI_PHYSICAL_ADDRESS BaseAddress;
UINT64 Capabilities;
EFI_GCD_MEMORY_TYPE GcdMemoryType;
} EFI_GCD_MEMORY_SPACE_DESCRIPTOR;
The physical address of the first byte in the memory region. Type EFI_PHYSICAL_ADDRESS is defined in the
AllocatePages() function description in the UEFI 2.0 specification.
Length
The number of bytes in the memory region.
The bit mask of attributes that the memory region is capable of supporting. The bit mask of available attributes
is defined in the GetMemoryMap() function description in the UEFI 2.0 specification.
The bit mask of attributes that the memory region is currently using. The bit mask of available attributes is
defined in GetMemoryMap() .
Type of the memory region. Type EFI_GCD_MEMORY_TYPE is defined in the AddMemorySpace() function de-
The image handle of the agent that allocated the memory resource described by PhysicalStart and
NumberOfBytes . Ifthisfieldis NULL,thenthememoryresourceisnotcurrentlyallocated. Type EFI_HANDLE
is defined in InstallProtocolInterface() in the UEFI 2.0 specification.
Thedevicehandleforwhichthememoryresourcehasbeenallocated. If ImageHandle isNULL,thenthememory
resourceisnotcurrentlyallocated. Ifthisfieldis NULL,thenthememoryresourceisnotassociatedwithadevice
that is described by a device handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the
Table 7.5: Status Codes Returned
EFI_SUCCESS The descriptor for the memory resource region containing
BaseAddress was returned in Descriptor
EFI_INVALID_PARAMETER Descriptor isNULL
EFI_NOT_FOUND A memory resource range containing BaseAddress was not found
EFI_NOT_AVAILABLE_YET The attributes cannot be set because CPU architectural protocol is
not available yet
II-7.2. Global Coherency Domain Services II-44UEFI Platform Initialization Specification, Release 1.8
II-7.2.4.6 SetMemorySpaceAttributes()
Summary
This service modifies the attributes for a memory region in the global coherency domain of the processor.
Prototype
typedef
(EFIAPI *EFI_SET_MEMORY_SPACE_ATTRIBUTES) (
);
The physical address that is the start address of a memory region. Type EFI_PHYSICAL_ADDRESS is defined in
theAllocatePages() function description in the UEFI 2.0 specification.
Length
The size in bytes of the memory region.
The bit mask of attributes to set for the memory region. The bit mask of available attributes is defined in the
GetMemoryMap() function description in the UEFI 2.0 specification.
TheSetMemorySpaceAttributes() function modifies the attributes for the memory region specified by
BaseAddress andLengthfrom their current attributes to the attributes specified by Attributes . If this modifi-
cation of attributes succeeds, then EFI_SUCCESS is returned.
If the attributes specified by Attributes are not supported for the memory region specified by BaseAddress and
Length, thenEFI_UNSUPPORTED is returned. The Attributes bit mask must be a proper subset of the capabilities
bit mask for the specified memory region. The capabilities bit mask is specified when a memory region is added with
AddMemorySpace() and can be retrieved with GetMemorySpaceDescriptor() orGetMemorySpaceMap() .
Iftheattributesforoneormorebytesofthememoryrangespecifiedby BaseAddress andLengthcannotbemodified
because the current system policy does not allow them to be modified, then EFI_ACCESS_DENIED is returned.
If there are not enough system resources available to modify the attributes of the memory range, then
II-7.2. Global Coherency Domain Services II-45UEFI Platform Initialization Specification, Release 1.8
Table 7.6: Status Codes Returned
EFI_SUCCESS The attributes were set for the memory region
EFI_UNSUPPORTED The bit mask of attributes is not support for the memory resource
range specified by BaseAddress andLength
EFI_ACCESS_DENIED The attributes for the memory resource range specified by
BaseAddress andLengthcannot be modified
EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
the memory resource range
II-7.2.4.7 SetMemorySpaceCapabilities()
Summary
This service modifies the capabilities for a memory region in the global coherency domain of the processor.
Prototype
typedef
(EFIAPI *EFI_SET_MEMORY_SPACE_CAPABILITIES) (
IN UINT64 Capabilities*
);
theAllocatePages() function description in the UEFI Specification.
Length
The bit mask of capabilities that the memory region supports. The bit mask of available attributes is defined in
theGetMemoryMap() function description in the UEFI specification.
TheSetMemorySpaceCapabilities() function modifies the capabilities for the memory region specified by
BaseAddress andLengthfrom their current capabilities to the capabilities specified by Capabilities . If this
modification of capabilities succeeds, then EFI_SUCCESS is returned.
If the value for Capabilities does not include the current operating memory region attributes (having previously
been set by calling SetMemorySpaceAttributes ) thenEFI_UNSUPPORTED is returned.
If Length is zero, then EFI_INVALID_PARAMETER is returned.
Ifthecapabilitiesforoneormorebytesofthememoryrangespecifiedby BaseAddress andLengthcannotbemodified
If there are not enough system resources available to modify the capabilities of the memory range, then
II-7.2. Global Coherency Domain Services II-46UEFI Platform Initialization Specification, Release 1.8
Table 7.7: Status Codes Returned
EFI_SUCCESS The capabilities were set for the memory region
EFI_UNSUPPORTED The capabilities specified by Capabilities do not include the
memory region attributes currently in use
EFI_ACCESS_DENIED The capabilities for the memory resource range specified by
EFI_OUT_OF_RESOURCES Therearenotenoughsystemresourcestomodifythecapabilitiesof
II-7.2.4.8 GetMemorySpaceMap()
Summary
Returns a map of the memory resources in the global coherency domain of the processor.
Prototype
typedef
(EFIAPI *EFI_GET_MEMORY_SPACE_MAP) (
OUT UINTN *NumberOfDescriptors,
OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR **MemorySpaceMap
);
NumberOfDescriptors
Apointertonumberofdescriptorsreturnedinthe MemorySpaceMap buffer. Thisparameterisignoredoninput,
and is set to the number of descriptors in the MemorySpaceMap buffer on output.
MemorySpaceMap
A pointer to the array of EFI_GCD_MEMORY_SPACE_DESCRIPTOR s. Type
EFI_GCD_MEMORY_SPACE_DESCRIPTOR is defined in GetMemorySpaceDescriptor() . This buffer is
allocatedwith AllocatePool() ,soitisthecaller’sresponsibilitytofreethisbufferwithacallto FreePool()

Summary
Prototype
typedef
);
. The number of descriptors in MemorySpaceMap is returned in NumberOfDescriptors . See the UEFI 2.0
specification for definitions of AllocatePool() andFreePool() .
TheGetMemorySpaceMap() function retrieves the entire GCD memory space map. If there are no errors re-
trieving the GCD memory space map, then the number of descriptors in the GCD memory space map is re-
turned in NumberOfDescriptors , the array of descriptors from the GCD memory space map is allocated with
AllocatePool() , the descriptors are transferred into MemorySpaceMap , andEFI_SUCCESS is returned.
IfNumberOfDescriptors isNULL, thenEFI_INVALID_PARAMETER is returned.
IfMemorySpaceMap isNULL, thenEFI_INVALID_PARAMETER is returned.
If there are not enough resources to allocate MemorySpaceMap , thenEFI_OUT_OF_RESOURCES is returned.
II-7.2. Global Coherency Domain Services II-47UEFI Platform Initialization Specification, Release 1.8
Table 7.8: Status Codes Returned
EFI_SUCCESS The memory space map was returned in the MemorySpaceMap
buffer and the number of descriptors in MemorySpaceMap was re-
turned inNumberOfDescriptors
EFI_INVALID_PARAMETER NumberOfDescriptors isNULL
EFI_INVALID_PARAMETER MemorySpaceMap isNULL
EFI_OUT_OF_RESOURCES There are not enough resources to allocate MemorySpaceMap
II-7.2.4.9 AddIoSpace()
Summary
This service adds reserved I/O, or I/O resources to the global coherency domain of the processor.
Prototype
typedef
(EFIAPI *EFI_ADD_IO_SPACE) (
IN EFI_GCD_IO_TYPE GcdIoType,
);
GcdIoType
The type of I/O resource being added. Type EFI_GCD_IO_TYPE is defined in “Related Definitions” below. The
only types allowed are EfiGcdIoTypeReserved andEfiGcdIoTypeIo .
ThephysicaladdressthatisthestartaddressoftheI/Oresourcebeingadded. Type EFI_PHYSICAL_ADDRESS is
defined in the AllocatePages() function description in the UEFI 2.0 specification.
Length
The size in bytes of the I/O resource that is being added.
TheAddIoSpace() functionconvertsunallocatednon-existentI/OrangestoarangeofreservedI/O,orarangeofI/O.
BaseAddress andLengthspecifytheI/Orange,and GcdIoType specifiestheI/Otype. IftheI/Orangeissuccessfully
added, then EFI_SUCCESS is returned.
If the GCD I/O space map contains adjacent I/O regions that only differ in their base address and length fields, then
those adjacent I/O regions must be merged into a single I/O descriptor.
IfGcdIoType is notEfiGcdIoTypeReserved orEfiGcdIoTypeIo , thenEFI_INVALID_PARAMETER is returned.
If the processor does not support one or more bytes of the I/O range specified by BaseAddress andLength, then
If any portion of the I/O range specified by BaseAddress andLengthis not of type EfiGcdIoTypeNonExistent ,
thenEFI_ACCESS_DENIED is returned.
If any portion of the I/O range specified by BaseAddress andLength was allocated in a prior call to
AllocateIoSpace() , thenEFI_ACCESS_DENIED is returned.
II-7.2. Global Coherency Domain Services II-48UEFI Platform Initialization Specification, Release 1.8
If there are not enough system resources available to add the I/O resource to the global coherency domain of the
// EFI_GCD_IO_TYPE
EfiGcdIoTypeNonExistent,
EfiGcdIoTypeReserved,
EfiGcdIoTypeIo,
EfiGcdIoTypeMaximum
} EFI_GCD_IO_TYPE;
EfiGcdIoTypeNonExistent
An I/O region that is visible to the boot processor. However, there are no system components that are currently
decoding this I/O region.
EfiGcdIoTypeReserved
An I/O region that is visible to the boot processor. This I/O region is currently being decoded by a system
component, but the I/O region cannot be used to access I/O devices.
EfiGcdIoTypeIo
component that is producing I/O ports that can be used to access I/O devices.
Table 7.9: Status Codes Returned
EFI_SUCCESS The I O resource was added to the global coherency domain of the
processor
EFI_INVALID_PARAMETER GcdIoType is invalid
EFI_OUT_OF_RESOURCES TherearenotenoughsystemresourcestoaddtheIOresourcetothe
EFI_UNSUPPORTED TheprocessordoesnotsupportoneormorebytesoftheIOresource
EFI_ACCESS_DENIED One or more bytes of the I O resource range specified by
BaseAddress andLengthconflictswithanIOresourcerangethat
waspreviouslyaddedtotheglobalcoherencydomainoftheproces-
sor
BaseAddress andLength was allocated in a prior call to
II-7.2. Global Coherency Domain Services II-49UEFI Platform Initialization Specification, Release 1.8
II-7.2.4.10 AllocateIoSpace()
Summary
ThisserviceallocatesnonexistentI/O,reservedI/O,orI/Oresourcesfromtheglobalcoherencydomainoftheprocessor.
Prototype
typedef
(EFIAPI *EFI_ALLOCATE_IO_SPACE) (
IN EFI_GCD_ALLOCATE_TYPE AllocateType,
);
The type of allocation to perform. Type EFI_GCD_ALLOCATE_TYPE is defined in AllocateMemorySpace() .
GcdIoType
The type of I/O resource being allocated. Type EFI_GCD_IO_TYPE is defined in AddIoSpace() . The only
types allowed are EfiGcdIoTypeNonExistent ,EfiGcdIoTypeReserved , andEfiGcdIoTypeIo .
Alignment
Length
The size in bytes of the I/O resource range that is being allocated.
“Description”belowformoreinformation. OnoutputtheaddressissettothebaseoftheI/Oresourcerangethat
was allocated. Type EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0 specification.
The image handle of the agent that is allocating the I/O resource. Type EFI_HANDLE is defined in
InstallProtocolInterface() in the v.
The device handle for which the I/O resource is being allocated. If the I/O resource is not being allocated for a
devicethathasanassociateddevicehandle,thenthisparameterisoptionalandmaybe NULL.TypeEFI_HANDLE
TheAllocateIoSpace() function searches for an I/O range of type GcdIoType and converts the discovered I/O
range from the unallocated state to the allocated state. The parameters GcdAllocateType ,Alignment ,Length,
andBaseAddress specify the manner in which the GCD I/O space map is searched. If an I/O range is found that
meets the search criteria, then the base address of the I/O range is returned in BaseAddress , andEFI_SUCCESS
is returned. ImageHandle andDeviceHandle are used to convert the I/O range from the unallocated state to the
allocatedstate. ImageHandle identifiestheimagethatiscalling AllocateIoSpace() ,andDeviceHandle identifies
thedevice that ImageHandle ismanaging thatrequires theI/O range. DeviceHandle isoptional, becausethe device
II-7.2. Global Coherency Domain Services II-50UEFI Platform Initialization Specification, Release 1.8
thatImageHandle ismanagingmightnothaveanassociateddevicehandle. IfanI/Orangemeetingthesearchcriteria
cannot be found, then EFI_NOT_FOUND is returned.
IfGcdAllocateType isEfiGcdAllocateAnySearchBottomUp , then the GCD I/O space map is searched from the
lowestaddressuptothehighestaddresslookingforunallocatedI/Orangesof Lengthbytesbeginningonaboundary
specified by Alignment that matches GcdIoType .
IfGcdAllocateType isEfiGcdAllocateAnySearchTopDown , then the GCD I/O space map is searched from the
highestaddressdowntothelowestaddresslookingforunallocatedI/Orangesof Lengthbytesbeginningonaboundary
IfGcdAllocateType isEfiGcdAllocateMaxAddressSearchBottomUp , then the GCD I/O space map is searched
fromthelowestaddressupto BaseAddress lookingforunallocatedI/Orangesof Lengthbytesbeginningonabound-
ary specified by Alignment that matches GcdIoType .
IfGcdAllocateType isEfiGcdAllocateMaxAddressSearchTopDown , then the GCD I/O space map is searched
fromBaseAddress down to the lowest address looking for unallocated I/O ranges of Lengthbytes beginning on a
boundary specified by Alignment that matches GcdIoType .
IfGcdAllocateType isEfiGcdAllocateAddress , then the GCD I/O space map is checked to see if the I/O range

startingat BaseAddress forLengthbytesisoftype GcdIoType ,unallocated,andbeginsonatheboundaryspecified
byAlignment .
IfGcdIoType is notEfiGcdIoTypeNonExistent ,EfiGcdIoTypeReserved , orEfiGcdIoTypeIo , then
IftherearenotenoughsystemresourcesavailabletoallocatetheI/Orange,then EFI_OUT_OF_RESOURCES isreturned.
Table 7.10: Status Codes Returned
EFI_SUCCESS The I O resource was allocated from the global coherency domain
of the processor
EFI_OUT_OF_RESOURCES There are not enough system resources to allocate the I/O resource
from the global coherency domain of the processor
EFI_NOT_FOUND The I/O resource request could not be satisfied
II-7.2. Global Coherency Domain Services II-51UEFI Platform Initialization Specification, Release 1.8
II-7.2.4.11 FreeIoSpace()
Summary
This service frees nonexistent I/O, reserved I/O, or I/O resources from the global coherency domain of the processor.
Prototype
typedef
(EFIAPI *EFI_FREE_IO_SPACE) (
);
The physical address that is the start address of the I/O resource being freed. Type EFI_PHYSICAL_ADDRESS is
Length
The size in bytes of the I/O resource range that is being freed.
TheFreeIoSpace() functionconvertstheI/Orangespecifiedby BaseAddress andLengthfromtheallocatedstate
to the unallocated state. If this conversion is successful, then EFI_SUCCESS is returned.
If one or more bytes of the I/O range specified by BaseAddress andLengthwere not allocated on previous calls to
AllocateIoSpace() , thenEFI_NOT_FOUND is returned.
If there are not enough system resources available to free the I/O range, then EFI_OUT_OF_RESOURCES is returned.
Table 7.11: Status Codes Returned
EFI_SUCCESS TheI/Oresourcewasfreedfromtheglobalcoherencydomainofthe
processor
EFI_UNSUPPORTED TheprocessordoesnotsupportoneormorebytesoftheI/Oresource
EFI_NOT_FOUND TheI/Oresourcerangespecifiedby BaseAddress andLengthwas
not allocated with previous calls to AllocateIoSpace
EFI_OUT_OF_RESOURCES TherearenotenoughsystemresourcestofreetheI/Oresourcefrom
the global coherency domain of the processor
II-7.2. Global Coherency Domain Services II-52UEFI Platform Initialization Specification, Release 1.8
II-7.2.4.12 RemoveIoSpace()
Summary
This service removes reserved I/O, or I/O resources from the global coherency domain of the processor.
Prototype
typedef
(EFIAPI *EFI_REMOVE_IO_SPACE) (
);
A pointer to a physical address that is the start address of the I/O resource being removed. Type
EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0 specification.
Length
The size in bytes of the I/O resource that is being removed.
TheRemoveIoSpace() function converts the I/O range specified by BaseAddress andLengthto the I/O type
EfiGcdIoTypeNonExistent . If this conversion is successful, then EFI_SUCCESS is returned.
If one or more bytes of the I/O range specified by BaseAddress andLengthwere not added to the GCD I/O space
map with previous calls to AddIoSpace() , thenEFI_NOT_FOUND is returned.
If one or more bytes of the I/O range specified by BaseAddress andLengthwere allocated from the GCD I/O space
map with previous calls to AllocateIoSpace() , thenEFI_ACCESS_DENIED is returned.
IftherearenotenoughsystemresourcesavailabletoremovetheI/Orange,then EFI_OUT_OF_RESOURCES isreturned.
II-7.2. Global Coherency Domain Services II-53UEFI Platform Initialization Specification, Release 1.8
Table 7.12: Status Codes Returned
EFI_SUCCESS TheI/Oresourcewasremovedfromtheglobalcoherencydomainof
EFI_NOT_FOUND One or more bytes of the I/O resource range specified by
EFI_ACCESS_DENIED One or more bytes of the I/O resource range specified
byBaseAddress andLength has been allocated with
EFI_OUT_OF_RESOURCES There are not enough system resources to remove the I/O resource
II-7.2.4.13 GetIoSpaceDescriptor()
Summary
This service retrieves the descriptor for an I/O region containing a specified address.
Prototype
typedef
(EFIAPI *EFI_GET_IO_SPACE_DESCRIPTOR) (
OUT EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor
);
The physical address that is the start address of an I/O region. Type EFI_PHYSICAL_ADDRESS is defined in
A pointer to a caller allocated descriptor. On return, the descriptor describes the I/O region containing
BaseAddress . TypeEFI_GCD_IO_SPACE_DESCRIPTOR is defined in “Related Definitions” below.
TheGetIoSpaceDescriptor() functionretrievesthedescriptorfortheI/Oregionthatcontainstheaddressspecified
byBaseAddress . IfanI/Oregioncontaining BaseAddress isfound,thenthedescriptorforthatI/Oregionisreturned
in the caller allocated structure Descriptor , andEFI_SUCCESS is returned.
IfanI/Oregioncontaining BaseAddress isnotpresentintheGCDI/Ospacemap,then EFI_NOT_FOUND isreturned.
// EFI_GCD_IO_SPACE_DESCRIPTOR
II-7.2. Global Coherency Domain Services II-54UEFI Platform Initialization Specification, Release 1.8
EFI_GCD_IO_TYPE GcdIoType;
} EFI_GCD_IO_SPACE_DESCRIPTOR;
Physical address of the first byte in the I/O region. Type EFI_PHYSICAL_ADDRESS is defined in the
Length
Number of bytes in the I/O region.
GcdIoType
Type of the I/O region. Type EFI_GCD_IO_TYPE is defined in the AddIoSpace() function description.
TheimagehandleoftheagentthatallocatedtheI/Oresourcedescribedby PhysicalStart andNumberOfBytes
. If this field is NULL, then the I/O resource is not currently allocated. Type EFI_HANDLE is defined in
ThedevicehandleforwhichtheI/Oresourcehasbeenallocated. If ImageHandle isNULL,thentheI/Oresource
is not currently allocated. If this field is NULL, then the I/O resource is not associated with a device that is
described by a device handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI
2.0 specification.
Table 7.13: Status Codes Returned
EFI_SUCCESS ThedescriptorfortheI/Oresourceregioncontaining BaseAddress
was returned in Descriptor
EFI_NOT_FOUND An I/O resource range containing BaseAddress was not found
II-7.2.4.14 GetIoSpaceMap()
Summary
Returns a map of the I/O resources in the global coherency domain of the processor.
Prototype
typedef
(EFIAPI *EFI_GET_IO_SPACE_MAP) (
OUT EFI_GCD_IO_SPACE_DESCRIPTOR **IoSpaceMap
);

Summary
Prototype
typedef
);
II-7.2. Global Coherency Domain Services II-55UEFI Platform Initialization Specification, Release 1.8
A pointer to number of descriptors returned in the IoSpaceMap buffer. This parameter is ignored on input, and
is set to the number of descriptors in the IoSpaceMap buffer on output.
IoSpaceMap
A pointer to the array of EFI_GCD_IO_SPACE_DESCRIPTOR s. TypeEFI_GCD_IO_SPACE_DESCRIPTOR is de-
fined inGetIoSpaceDescriptor() . This buffer is allocated with AllocatePool() , so it is the caller’s re-
sponsibilitytofreethisbufferwithacallto FreePool() . Thenumberofdescriptorsin IoSpaceMap isreturned
inNumberOfDescriptors .
TheGetIoSpaceMap() function retrieves the entire GCD I/O space map. If there are no errors retrieving the GCD
I/Ospacemap,thenthenumberofdescriptorsintheGCDI/Ospacemapisreturnedin NumberOfDescriptors ,the
array of descriptors from the GCD I/O space map is allocated with AllocatePool() , the descriptors are transferred
intoIoSpaceMap , andEFI_SUCCESS is returned.
IfIoSpaceMap isNULL, thenEFI_INVALID_PARAMETER is returned.
If there are not enough resources to allocate IoSpaceMap , thenEFI_OUT_OF_RESOURCES is returned.
Table 7.14: Status Codes Returned
EFI_SUCCESS The I/O space map was returned in the IoSpaceMap buffer
and the number of descriptors in IoSpaceMap was returned in
EFI_INVALID_PARAMETER IoSpaceMap isNULL
EFI_OUT_OF_RESOURCES There are not enough resources to allocate IoSpaceMap
II-7.3 Dispatcher Services
ThefunctionsthatmakeuptheDispatcherServicesareusedduringpreboottoscheduledriversforexecution. Adriver
may optionally have the Schedule On Request (SOR) flag set in the driver’s dependency expression. Drivers with this
bit set will not be loaded and invoked until they are explicitly requested to do so. Files loaded from firmware volumes
may be placed in the untrusted state by the Security Architectural Protocol. The services in this section provide this
abilitytocleartheSORflaginaDXEdriver’sdependencyexpressionandtheabilitytopromoteafilefromafirmware
volume from the untrusted to the trusted state. Dispatcher Boot Type Services lists the Dispatcher Services.
Table 7.15: Dispatcher Boot Type Services
Dispatch Loads and executed DXE drivers from firmware volumes
Schedule Clears the Schedule on Request SOR flag for a component that is stored in a firmware
volume
Trust Changes the state of a file stored in a firmware volume from the untrusted state to the
trusted state
ProcessFirmwareVol-
umeCreatesafirmwarevolumehandleforafirmwarevolumethatispresentinsystemmemory
II-7.3. Dispatcher Services II-56UEFI Platform Initialization Specification, Release 1.8
II-7.3.1 Dispatch()
Summary
Loads and executes DXE drivers from firmware volumes.
Prototype
typedef
(EFIAPI *EFI_DISPATCH) (
VOID
);
TheDispatch() function searches for DXE drivers in firmware volumes that have been installed since the last time
theDispatch() service was called. It then evaluates the dependency expressions of all the DXE drivers and loads
and executes those DXE drivers whose dependency expression evaluate to TRUE. This service must interact with the
Security Architectural Protocol to authenticate DXE drivers before they are executed. This process is continued until
nomoreDXEdriverscanbeexecuted. IfoneormoreDXEdriversareexecuted,then EFI_SUCCESS isreturned. Ifno
DXE drivers are executed, EFI_NOT_FOUND is returned.
If an attempt is made to invoke the DXE Dispatcher recursively, then no action is performed by the Dispatch()
service, and EFI_ALREADY_STARTED is returned. In this case, because the DXE Dispatcher is already running, it is
not necessary to invoke it again. All the DXE drivers that can be dispatched will be dispatched.
Table 7.16: Status Codes Returned
EFI_SUCCESS One or more DXE driver were dispatched
EFI_NOT_FOUND No DXE drivers were dispatched
EFI_ALREADY_STARTED An attempt is being made to start the DXE Dispatcher recursively
Thus no action was taken
II-7.3.2 Schedule()
Summary
Clears the Schedule on Request (SOR) flag for a component that is stored in a firmware volume.
Prototype
typedef
(EFIAPI *EFI_SCHEDULE) (
IN EFI_HANDLE FirmwareVolumeHandle,
IN CONST EFI_GUID *FileName
);
FirmwareVolumeHandle
The handle of the firmware volume that contains the file specified by FileName . TypeEFI_HANDLE is defined
inInstallProtocolInterface() in the UEFI 2.0 specification.
II-7.3. Dispatcher Services II-57UEFI Platform Initialization Specification, Release 1.8
FileName
Apointertothenameofthefileinafirmwarevolume. ThisisthefilethatshouldhaveitsSORbitcleared. Type
EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0 specification.
TheSchedule() function searches the dispatcher queues for the driver specified by FirmwareVolumeHandle and
FileName . If this driver cannot be found, then EFI_NOT_FOUND is returned. If the driver is found, and its Schedule
On Request (SOR) flag is not set in its dependency expression, then EFI_NOT_FOUND is returned. If the driver is
found,anditsSORbitissetinitsdependencyexpression,thentheSORflagiscleared,and EFI_SUCCESS isreturned.
After the SOR flag is cleared, the driver will be dispatched if the remaining portions of its dependency expression are
satisfied. This service does not automatically invoke the DXE Dispatcher. Instead, the Dispatch() service must be
used to invoke the DXE Dispatcher.
Table 7.17: Status Codes Returned
EFI_SUCCESS The DXE driver was found and its SOR bit was cleared
EFI_NOT_FOUND The DXE driver does not exist or the DXE driver exists and its SOR bit is not set
II-7.3.3 Trust()
Summary
Promotes a file stored in a firmware volume from the untrusted to the trusted state. Only the Security Architectural
Protocolcanplaceafileintheuntrustedstate. Aplatformspecificcomponentmaychoosetousethisservicetopromote
a previously untrusted file to the trusted state.
Prototype
typedef
(EFIAPI *EFI_TRUST) (
);
FileName
A pointer to the name of the file in a firmware volume. This is the file that should be promoted from the un-
trustedstatetothetrustedstate. Type EFI_GUID isdefinedin InstallProtocolInterface() intheUEFI2.0
TheTrust() functionpromotesthefilespecifiedby FirmwareVolumeHandle andFileName fromtheuntrustedstate
to the trusted state. If this file is not found in the queue of untrusted files, then EFI_NOT_FOUND is returned. If the
driver is found, and its state is changed to trusted and EFI_SUCCESS is returned. This service does not automatically
invoke the DXE Dispatcher. Instead, the Dispatch() service must be used to invoke the DXE Dispatcher.
II-7.3. Dispatcher Services II-58UEFI Platform Initialization Specification, Release 1.8
Table 7.18: Status Codes Returned
EFI_SUCCESS The file was found in the untrusted state and it was promoted to the trusted state
EFI_NOT_FOUND The file was not found in the untrusted state
ProcessFirmwareVolume()
Summary
Creates a firmware volume handle for a firmware volume that is present in system memory.
Prototype
typedef
(EFIAPI *EFI_PROCESS_FIRMWARE_VOLUME) (
IN CONST VOID *FirmwareVolumeHeader,
OUT EFI_HANDLE *FirmwareVolumeHandle
);
FirmwareVolumeHeader
A pointer to the header of the firmware volume.
Size
The size, in bytes, of the firmware volume.
Onoutput,apointertothecreatedhandle. Thisservicewillinstallthe EFI_FIRMWARE_VOLUME2_PROTOCOL and
EFI_DEVICE_PATH_PROTOCOL for the of the firmware volume that is described by FirmwareVolumeHeader
andSize. TypeEFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 specification.
TheProcessFirmwareVolume() functionexaminesthecontentsofthebufferspecifiedby FirmwareVolumeHeader
andSize. If the buffer contains a valid firmware volume, then a new handle is created, and the
EFI_FIRMWARE_VOLUME2_PROTOCOL and a memory-mapped EFI_DEVICE_PATH_PROTOCOL are installed onto the
new handle. The new handle is returned in FirmwareVolumeHandle .
Table 7.19: Status Codes Returned
EFI_SUCCESS The EFI_FIRMWARE_VOLUME2_PROTOCOL and
EFI_DEVICE_PATH_PROTOCOL were installed onto
FirmwareVolumeHandle for the firmware volume described
byFirmwareVolumeHeader andSize
EFI_VOLUME_CORRUPTED The firmware volume described by FirmwareVolumeHeader and
Sizeis corrupted
EFI_OUT_OF_RESOURCES There are not enough system resources available to
produce the EFI_FIRMWARE_VOLUME2_PROTOCOL and
EFI_DEVICE_PATH_PROTOCOL for the firmware volume de-
scribed by FirmwareVolumeHeader andSize

II-7.3. Dispatcher Services II-59CHAPTER
EIGHT
PROTOCOLS - DEVICE PATH PROTOCOL
II-8.1 Introduction
This section adds two device path node types that describe files stored in firmware volumes:
ThesedevicepathnodesareusedbyaDXE-awareupdatedUEFIBootService LoadImage() toloadUEFIimagesfrom
firmware volumes. This new capability is used by the DXE Dispatcher to load DXE drivers from firmware volumes.
II-8.2 Firmware Volume Media Device Path
This type is used by systems implementing the PI architecture specifications to describe a firmware volume.
Table 8.1: Firmware Volume Media Device Path
Type 0 1 Type 4 – Media Device Path
Sub-Type 1 1 Sub Type 7 – Firmware Volume Media Device Path
Length 2 2 Length of this structure in bytes. Length is 20 bytes
Firmware Volume Name 4 16 Firmware volume name. Type EFI_GUID
Table 8.2: Firmware Volume Device Node Text Representation
Device Node Type/Subtype/Other Description
Type: 4 (Media Device Path)
Sub Type: 7 (Firmware Volume)Fv (fv guid)
Thefv guid is a GUID.
II-60UEFI Platform Initialization Specification, Release 1.8
II-8.3 Firmware File Media Device Path
This type is used by systems implementing the PI architecture specifications to describe a firmware file in a firmware
volume.
Table 8.3: Firmware File Media Device Path
Sub-Type 1 1 Sub Type 6 – Firmware File Media Device Path
Firmware File Name 4 16 Firmware file name. Type EFI_GUID.
Table 8.4: Firmware Volume File Device Node TextRepresentation
Sub Type: 6 (Firmware File)FvFile (fvfile-guid)
Thefvfile guid is a GUID.
II-8.3. Firmware File Media Device Path II-61CHAPTER
NINE
DXE FOUNDATION
II-9.1 Introduction
TheDXEFoundationisdesignedtobecompletelyportablewithnoprocessor,chipset,orplatformdependencies. This
lack of dependencies is accomplished by designing in several features:
•The DXE Foundation depends only upon a HOB list for its initial state.
This means that the DXE Foundation does not depend on any services from a previous phase, so all the prior
phases can be unloaded once the HOB list is passed to the DXE Foundation.
•The DXE Foundation does not contain any hard-coded addresses.
ThismeansthattheDXEFoundationcanbeloadedanywhereinphysicalmemory,anditcanfunctioncorrectly
no matter where physical memory or where Firmware Volumes (FVs) are located in the processor’s physical
•TheDXEFoundationdoesnotcontainanyprocessor-specific,chipset-specific,orplatform-specificinformation.
Instead,theDXEFoundationisabstractedfromthesystemhardwarethroughasetofDXEArchitecturalProtocol
interfaces. These architectural protocol interfaces are produced by a set of DXE drivers that are invoked by the
DXE Dispatcher.
The DXE Foundation must produce the UEFI System Table and its associated set of UEFI Boot Services and UEFI
Runtime Services. The DXE Foundation also contains the DXE Dispatcher whose main purpose is to discover and
executeDXEdriversstoredinFVs. TheexecutionorderofDXEdriversisdeterminedbyacombinationoftheoptional
apriorifileandthesetofdependencyexpressionsthatareassociatedwiththeDXEdrivers. TheFVfileformatallows
dependencyexpressionstobepackagedwiththeexecutableDXEdriverimage. DXEdriversutilizeaPE/COFFimage
format, so the DXE Dispatcher must also contain a PE/COFF loader to load and execute DXE drivers.
TheGetMemoryMap() implementation must include all GCD map entries of types EfiGcdMemoryTypeReserved and
EfiGcdMemoryTypeMemoryMappedIo into the UEFI memory map.
II-9.2 Hand-Off Block (HOB) List
TheHand-OffBlock(HOB)listcontainsalltheinformationthattheDXEFoundationrequirestoproduceitsmemory-
based services. The HOB list contains the following:
•Information on the boot mode and the memory that was allocated in the previous phase.
•Adescriptionofthesystemmemorythatwasinitializedbythepreviousphasealongwithinformationaboutthe
firmware devices that were discovered in the previous phase.
The firmware device information includes the system memory locations of the firmware devices and system memory
locationsofthefirmwarevolumesthatarecontainedwithinthosefirmwaredevices. Thefirmwarevolumesmaycontain
II-62UEFI Platform Initialization Specification, Release 1.8
DXE drivers, and the DXE Dispatcher is responsible for loading and executing the DXE drivers that are discovered in
those firmware volumes.
The I/O resources and memory-mapped I/O resources that were discovered in the previous phase.
The HOB list must be treated as a read-only data structure. It conveys the state of the system at the time the DXE
Foundation is started. The DXE Foundation and DXE drivers should never modify the contents of the HOB list.
HOBList showsanexampleHOBlist. ThefirstHOBlistentryisalwaysthePhaseHandoffInformationTable(PHIT)
HOBthatcontainsthebootmodeandadescriptionofthememoryregionsusedbythepreviousphase. Therestofthe
HOB list entries can appear in any order. This example shows the various HOB types that are supported. The most
importantonestotheDXEFoundationaretheHOBsthatdescribesystemmemoryandthefirmwarevolumes. AHOB
list is terminated by an end of list HOB. There is one additional HOB type that is not shown. This is a GUIDed HOB
thatallowsamodulefromthepreviousphasetopassprivatedatatoaDXEdriver. OnlytheDXEdriverthatrecognizes
the GUID value in the GUIDed HOB will be able to understand the data in the GUIDed HOB. The DXE Foundation
does not consume any GUIDed HOBs. The HOB entries are all designed to be position independent. This allows the
DXEFoundationtorelocatetheHOBlisttoadifferentlocationiftheDXEFoundationdoesnotlikewheretheprevious
phase placed the HOB list in memory.
SeeHOB Translations for more information on HOB types.
Fig. 9.1: HOB List
II-9.3 DXE Foundation Data Structures
TheDXEFoundationproducestheUEFISystemTable,andtheUEFISystemTableisconsumedbyeveryDXEdriver
and executable image invoked by the DXE Dispatcher and BDS. It contains all the information required for these
componentstoutilizetheservicesprovidedbytheDXEFoundationandtheservicesprovidedbyanypreviouslyloaded
DXEdriver. UEFISystemTableandRelatedComponents showsthevariouscomponentsthatareavailablethroughthe
UEFI System Table.
The DXE Foundation produces the UEFI Boot Services, UEFI Runtime Services, and DXE Services with the aide of
the DXE Architectural Protocols. The UEFI System Table also provides access to all the active console devices in the
platformandthesetofUEFIConfigurationTables. TheUEFIConfigurationTablesareanextensiblelistoftablesthat
describetheconfigurationoftheplatform. Today,thisincludespointerstotablessuchasDXEServices,theHOBlist,
ACPItable,SMBIOStable,andtheSALSystemTable. Thislistmaybeexpandedinthefutureasnewtabletypesare
defined. Also,throughtheuseoftheProtocolHandleServicesintheUEFIBootServicesTable,anyexecutableimage
can access the handle database and any of the protocol interfaces that have been registered by DXE drivers.
When the transition to the OS runtime is performed, the handle database, active consoles, UEFI Boot Services, DXE
Services,andservicesprovidedbybootserviceDXEdriversareterminated. ThisfreesupmemoryforusebytheOS.
This only leaves the UEFI System Table, UEFI Runtime Services Table, and the UEFI Configuration Tables available
intheOSruntimeenvironment. ThereisalsotheoptionofconvertingalloftheUEFIRuntimeServicesfromaphysical
address space to an OS-specific virtual address space. This address space conversion may be performed only once.
II-9.3. DXE Foundation Data Structures II-63UEFI Platform Initialization Specification, Release 1.8
Fig. 9.2: UEFI System Table and Related Components
II-9.4 Required DXE Foundation Components
DXE Foundation Components shows the components that a DXE Foundation must contain. A detailed description of
these components follows.
A DXE Foundation must have the following components:
•An implementation of the UEFI Boot Services. UEFI Boot Services Dependencies describes which services
can be made available based on the HOB list alone and which services depend on the presence of architectural
protocols.
•An implementation of the DXE Services. DXE Services Dependencies describes which services can be made
available based on the HOB list alone and which services depend on the presence of architectural protocols.
•AHOBParser thatconsumesthe HOBlistspecifiedby HobStart andinitializesthe UEFImemorymap, GCD
memoryspacemap,andGCDI/Ospacemap. SeesectioniffordetailsonthetranslationfromHOBstothemaps
maintained by the DXE Foundation
•An implementation if a DXE Dispatcher that includes a dependency expression evaluator. See DXE Dispatcher
for a detailed description of this component.
•A Firmware Volume driver that produces the EFI_FIRMWARE_VOLUME2_PROTOCOL for every firmware volume
described in the HOB list. This component is used by the DXE Dispatcher to search for a priori files and DXE

drivers in firmware volumes. See the Platform Initialization Specification , Volume 3, for the defi-
nition of the Firmware Volume Protocol.
•An instance of the EFI_DECOMPRESS_PROTOCOL . See the UEFI 2.0 specification for the detailed requirements
for this component. This component is required by the DXE Dispatcher to read compressed sections from DXE
drivers stored in firmware volumes. It is expected that most DXE drivers will utilize compressed sections to
reduce the size of firmware volumes.
•The DXE Dispatcher uses the Boot Service StartImage() to invoke a DXE driver. The Boot Services
StartImage() andExit()worktogethertohandcontroltoaDXEdriverandreturncontroltotheDXEFoun-
dation. SincetheBootService Exit()canbecalledforanywhereinsideaDXEdriver,theBootService Exit()
isrequiredtorebalancethestack,soitisinthesamestateitwasinwhentheBootService Start() wascalled.
Thisistypicallyimplementedusingtheprocessor-specificfunctionscalled SetJump() andLongJump() . Since
II-9.4. Required DXE Foundation Components II-64UEFI Platform Initialization Specification, Release 1.8
Fig. 9.3: DXE Foundation Components
theDXEFoundationmustusetheBootServices StartImage() andExit()toinvokeDXEdrivers,theroutines
SetJump() andLongJump() are required by the DXE Foundation.
•A PE/COFF loader that supports PE32+ image types. This PE/COFF loader is used to implement the UEFI
Boot Service LoadImage() . The DXE Dispatcher uses the Boot Service LoadImage() to load DXE drivers
into system memory. If the processor that the DXE Foundation is compiled for requires an instruction cache
whenanimageisloadedintosystemmemory,thenaninstructioncacheflushroutineisalsorequiredintheDXE
•ThephasethatexecutedpriortoDXEwillinitializeastackfortheDXEFoundationtouse. Thisstackisdescribed
intheHOBlist. IfthesizeofthisstackdoesnotmeettheDXEFoundation’sminimumstacksizerequirementor
thestackisnotlocatedinmemoryregionthatissuitabletotheDXEFoundation,thentheDXEFoundationwill
have to allocate a new stack that does meet the minimum size and location requirements. As a result, the DXE
Foundation must contain a stack switching routine for the processor type that the DXE Foundation is compiled.
II-9.5 Handing Control to DXE Dispatcher
TheDXEFoundationmustcompletethefollowingtasksbeforehandingcontroltotheDXEDispatcher. Theorderthat
these tasks are performed is implementation dependent.
•Use the HOB list to initialize the GCD memory space map, the GCD I/O space map, and UEFI memory map.
•AllocatetheUEFIBootServicesTablefrom EFI_BOOT_SERVICES_MEMORY andinitializetheservicesthatonly
requiresystemmemorytofunctioncorrectly. TheremainingUEFIBootServicesmustbefilledinwithaservice
that returns EFI_NOT_AVAILABLE_YET .
•AllocatetheDXEServicesTablefrom EFI_BOOT_SERVICES_MEMORY andinitializetheservicesthatonlyrequire
system memory to function correctly. The remaining DXE Services must be filled in with a service that returns
II-9.5. Handing Control to DXE Dispatcher II-65UEFI Platform Initialization Specification, Release 1.8
EFI_NOT_AVAILABLE_YET .
•AllocatetheUEFIRuntimeServicesTablefrom EFI_RUNTIME_SERVICES_MEMORY andinitializealltheservices
to a service that returns EFI_NOT_AVAILABLE_YET .
•Allocate the UEFI System Table from EFI_RUNTIME_SERVICES_MEMORY and initialize all the fields.
•Build an image handle and EFI_LOADED_IMAGE_PROTOCOL instance for the DXE Foundation itself and add it
to the handle database.
•If the HOB list is not in a suitable location in memory, then relocate the HOB list to a more suitable location.
•Add the DXE Services Table to the UEFI Configuration Table.
•Add the HOB list to the UEFI Configuration Table.
•Create a notification event for each of the DXE Architectural Protocols. These events will be signaled when a
DXE driver installs a DXE Architectural Protocol in the handle database. The DXE Foundation must have a
notificationfunctionassociatedwitheachoftheseevents,sothefullcomplementofUEFIBootServices,UEFI
Runtime Services, and DXE Services can be produced. Each of the notification functions should compute the
32-bitCRCoftheUEFIBootServicesTable,UEFIRuntimeServicesTable,andtheDXEServicesTableifthe
CalculateCrc32() Boot Services is available.
•Initialize the Decompress Protocol driver that must be available before the DXE Dispatcher can process com-
pressed sections.
•Produce firmware volume handles for the one or more firmware volumes that are described in the HOB list.
Oncethesetaskshavebeencompleted,theDXEFoundationisreadytoloadandexecuteDXEdriversstoredinfirmware
volumes. This execution is done by handing control to the DXE Dispatcher. Once the DXE Dispatcher has finished
dispatchingalltheDXEdriversthatitcan,controlisthenpassedtotheBDSArchitecturalProtocol. Ifforsomereason,
anyoftheDXEArchitecturalProtocolshavenotbeenproducedbytheDXEdrivers,thenthesystemisinanunusable
state and the DXE Foundation must halt. Otherwise, control is handed to the BDS Architectural Protocol. The BDS
Architectural Protocol is responsible for transferring control to an operating system or system utility.
II-9.6 DXE Foundation Entry Point
II-9.6.1 DXE_ENTRY_POINT
TheonlyparameterpassedtotheDXEFoundationisapointertotheHOBlist. TheDXEFoundationandalltheDXE
drivers must treat the HOB list as read-only data.
The function DXE_ENTRY_POINT is the main entry point to the DXE Foundation.
II-9.6.1.1 DXE_ENTRY_POINT
Summary
This function is the main entry point to the DXE Foundation.
Prototype
typedef
VOID
(EFIAPI *DXE_ENTRY_POINT) (
IN CONST VOID *HobStart
);
II-9.6. DXE Foundation Entry Point II-66UEFI Platform Initialization Specification, Release 1.8
HobStart
A pointer to the HOB list.
ThisfunctionistheentrypointtotheDXEFoundation. ThePEIphase,whichexecutesjustbeforeDXE,isresponsible
for loading and invoking the DXE Foundation in system memory. The only parameter that is passed to the DXE
Foundationis HobStart . ThisparameterisapointertotheHOBlistthatdescribesthesystemstateatthehand-offto
the DXE Foundation. At a minimum, this system state must include the following:
•PHIT HOB
•CPU HOB
•Description of system memory
•Description of one or more firmware volumes
The DXE Foundation is also guaranteed that only one processor is running and that the processor is running with
interrupts disabled. The implementation of the DXE Foundation must not make any assumptions about where the
DXE Foundation will be loaded or where the stack is located. In general, the DXE Foundation should make as few
assumptions about the state of the system as possible. This lack of assumptions will allow the DXE Foundation to be
portable to the widest variety of system architectures.
II-9.7 Dependencies
II-9.7.1 UEFI Boot Services Dependencies
Boot Service Dependencies lists all the UEFI Boot Services and the components upon which each of these services
depend. The topics that follow describe what responsibilities the DXE Foundation has in producing the services that
depend on the presence of DXE Architectural Protocols.
Table 9.1: Boot Service Dependencies
Name Dependency
CreateEvent HOB list
CloseEvent HOB list
SignalEvent HOB list
WaitForEvent HOB list
CheckEvent HOB list
SetTimer Timer Architectural Protocol
RaiseTPL CPU Architectural Protocol
RestoreTPL CPU Architectural Protocol
AllocatePages HOB list
FreePages HOB list
GetMemoryMap HOB list and GetMemorySpaceMap
AllocatePool HOB list
FreePool HOB list
InstallProtocolInterface HOB list
UninstallProtocolInterface HOB list
ReinstallProtocolInterface HOB list
RegisterProtocolNotify HOB list
LocateHandle HOB list
II-9.7. Dependencies II-67UEFI Platform Initialization Specification, Release 1.8
Table 9.1 – continued from previous page
HandleProtocol HOB list
LocateDevicePath HOB list
OpenProtocol HOB list
CloseProtocol HOB list
OpenProtocolInformation HOB list
ConnectController HOB list
DisconnectController HOB list
ProtocolsPerHandle HOB list
LocateHandleBuffer HOB list
LocateProtocol HOB list
InstallMultipleProtocolInterfaces HOB list
Un installMultipleProtocolInterfaces HOB list
LoadImage HOB list
StartImage HOB list
UnloadImage HOB list
EFI_IMAGE_ENTRY_POINT HOB list
Exit HOB list
ExitBootServices HOB list
SetWatchDogTimer Watchdog Architectural Protocol
Stall Metronome Architectural Protocol Timer Architectural Protocol
CopyMem HOB list
SetMem HOB list
GetMemory Map HOB list
GetMemorySpaceMap GCD Service
GetNextMonotonicCount Monotonic Counter Architectural Protocol
InstallConfigurationTable HOB list
CalculateCrc32 Runtime Architectural Protocol
II-9.7.1.1 SetTimer()
WhentheDXEFoundationisnotifiedthatthe EFI_TIMER_ARCH_PROTOCOL hasbeeninstalled,thentheBootService
SetTimer() can be made available. The DXE Foundation can use the services of the EFI_TIMER_ARCH_PROTOCOL
toinitializeandhookaheartbeattimerinterruptfortheDXEFoundation. TheDXEFoundationcanusethisheartbeat
timer interrupt to determine when to signal on-shot and periodic timer events. This service may be called before the
EFI_TIMER_ARCH_PROTOCOL is installed. However, since a heartbeat timer is not running yet, time is essentially

frozenatzero. Thismeansthatnoperiodicorone-shottimereventswillfireuntilthe EFI_TIMER_ARCH_PROTOCOL is
installed.
II-9.7.1.2 RaiseTPL()
TheDXEFoundationmustproducetheBootService RaiseTPL() whenthememory-basedservicesareinitialized. The
DXEFoundationisguaranteedtobehandedcontroloftheplatformwithinterruptsdisabled. UntiltheDXEFoundation
installsaheartbeattimerinterruptandturnsoninterrupts,thisBootServicecanbeaverysimplefunctionthatalways
succeeds. When the DXE Foundation is notified that the EFI_CPU_ARCH_PROTOCOL has been installed, then the full
version of the Boot Service RaiseTPL() can be made available. When an attempt is made to raise the TPL level to
EFI_TPL_HIGH_LEVEL orhigher,thentheDXEFoundationshouldusetheservicesofthe EFI_CPU_ARCH_PROTOCOL
to disable interrupts.
II-9.7. Dependencies II-68UEFI Platform Initialization Specification, Release 1.8
II-9.7.1.3 RestoreTPL()
The DXE Foundation must produce the Boot Service RestoreTPL() when the memory-based services are initial-
ized. The DXE Foundation is guaranteed to be handed control of the platform with interrupts disabled. Until the
DXE Foundation installs a heartbeat timer interrupt and turns on interrupts, this Boot Service can be a very simple
function that always succeeds. When the DXE Foundation is notified that the EFI_CPU_ARCH_PROTOCOL has been
installed,thenthefullversionoftheBootService RestoreTPL() canbemadeavailable. Whenanattemptismadeto
restore the TPL level to level below EFI_TPL_HIGH_LEVEL , then the DXE Foundation should use the services of the
EFI_CPU_ARCH_PROTOCOL to enable interrupts.
II-9.7.1.4 SetWatchdogTimer()
When the DXE Foundation is notified that the EFI_WATCHDOG_ARCH_PROTOCOL has been installed, then the
Boot Service SetWatchdogTimer() can be made available. The DXE Foundation can use the services of the
EFI_WATCHDOG_TIMER_ARCH_PROTOCOL to set the amount of time before the system’s watchdog timer will expire.
II-9.7.1.5 Stall()
When the DXE Foundation is notified that the EFI_METRONOME_ARCH_PROTOCOL has been installed, the DXE Foun-
dationcanproduceaverysimpleversionoftheBootService Stall() . ThegranularityoftheBootService Stall()
will be based on the period of the EFI_METRONOME_ARCH_PROTOCOL . When the DXE Foundation is notified that the
EFI_TIMER_ARCH_PROTOCOL hasbeeninstalled,theDXEFoundationcanpossiblyproduceamoreaccurateversionof
the Boot Service Stall() . This all depends on the periods of the EFI_METRONOME_ARCH_PROTOCOL and the period
oftheEFI_TIMER_ARCH_PROTOCOL .TheDXEFoundationshouldproducetheBootService Stall() usingthemost
accurate time base available.
II-9.7.1.6 GetNextMonotonicCount()
When the DXE Foundation is notified that the EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL has been in-
stalled, then the Boot Service GetNextMonotonicCount() is available. The DXE driver that produces the
EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL isresponsiblefordirectlyupdatingthe GetNextMonotonicCount field
of the UEFI Boot Services Table. The DXE Foundation is only responsible for updating the 32-bit CRC of the UEFI
Boot Services Table.
II-9.7.1.7 CalculateCrc32()
When the DXE Foundation is notified that the EFI_RUNTIME_ARCH_PROTOCOL has been installed, then the Boot Ser-
viceCalculateCrc32() is available. The DXE driver that produces the EFI_RUNTIME_ARCH_PROTOCOL is respon-
sible for directly updating the CalculateCrc32 field of the UEFI Boot Services Table. The DXE Foundation is only
responsible for updating the 32-bit CRC of the UEFI Boot Services Table.
II-9.7. Dependencies II-69UEFI Platform Initialization Specification, Release 1.8
II-9.7.1.8 GetMemoryMap()
TheGetMemoryMap() implementation must include into the UEFI memory map all GCD map entries
of types EfiGcdMemoryTypeReserved andEfiPersistentMemory , and all GCD map entries of type
EfiGcdMemoryTypeMemoryMappedIo that haveEFI_MEMORY_RUNTIME attribute set.
II-9.7.2 UEFI Runtime Services Dependencies
Runtime Service Dependencies lists all the UEFI Runtime Services and the components upon which each of these
servicesdepend. ThetopicsthatfollowdescribewhatresponsibilitiestheDXEFoundationhasinproducingtheservices
that depend on the presence of DXE Architectural Protocols.
Table 9.2: Runtime Service Dependencies
GetVariable Variable Architectural Protocol
GetNextVariableName Variable Architectural Protocol
SetVariable Variable Architectural Protocol Variable Write Architectural Protocol
GetTime Real Time Clock Architectural Protocol
SetTime Real Time Clock Architectural Protocol
GetWakeupTime Real Time Clock Architectural Protocol
SetWakeupTime Real Time Clock Architectural Protocol
SetVirtualAddressMap Runtime Architectural Protocol
ConvertPointer Runtime Architectural Protocol
ResetSystem Reset Architectural Protocol
GetNextHighMonotonicCount Monotonic Counter Architectural Protocol
UpdateCapsule Capsule Header Protocol
QueryCapsuleCapabilities Capsule Header Protocol
II-9.7.2.1 GetVariable()
When the DXE Foundation is notified that the EFI_VARIABLE_ARCH_PROTOCOL has been installed, then the Runtime
ServiceGetVariable() isavailable. The DXEdriver thatproduces the EFI_VARIABLE_ARCH_PROTOCOL is respon-
sible for directly updating the GetVariable field of the UEFI Runtime Services Table. The DXE Foundation is only
responsible for updating the 32-bit CRC of the UEFI Runtime Services Table.
II-9.7.2.2 GetNextVariableName()
ServiceGetNextVariableName() isavailable. TheDXEdriverthatproducesthe EFI_VARIABLE_ARCH_PROTOCOL
is responsible for directly updating the GetNextVariableName field of the UEFI Runtime Services Table. The DXE
Foundation is only responsible for updating the 32-bit CRC of the UEFI Runtime Services Table.
II-9.7. Dependencies II-70UEFI Platform Initialization Specification, Release 1.8
II-9.7.2.3 SetVariable()
ServiceSetVariable() isavailable. The DXEdriver thatproduces the EFI_VARIABLE_ARCH_PROTOCOL is respon-
sible for directly updating the SetVariable field of the UEFI Runtime Services Table. The DXE Foundation is only
responsible for updating the 32-bit CRC of the UEFI Runtime Services Table. The EFI_VARIABLE_ARCH_PROTOCOL
is required to provide read-only access to all environment variables and write access to volatile environment vari-
ables. When the DXE Foundation is notified that the EFI_VARIABLE_WRITE_ARCH_PROTOCOL has been installed,
then write access to nonvolatile environment variables will also be available. If an attempt is made to call this func-
tionforanonvolatileenvironmentvariablepriortotheinstallationof EFI_VARIABLE_WRITE_ARCH_PROTOCOL ,then
EFI_NOT_AVAILABLE_YET must be returned. This allows for flexibility in the design and implementation of the vari-
ablesservicesinaplatformsuchthatreadaccesstoenvironmentvariablescanbeprovidedveryearlyintheDXEphase
and write access to nonvolatile environment variables can be provided later in the DXE phase.
II-9.7.2.4 GetTime()
When the DXE Foundation is notified that the EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL has been
installed, then the Runtime Service GetTime() is available. The DXE driver that produces the
EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL is responsible for directly updating the GetTime field of the UEFI
Runtime Services Table. The DXE Foundation is only responsible for updating the 32-bit CRC of the UEFI Runtime
Services Table.
II-9.7.2.5 SetTime()
installed, then the Runtime Service SetTime() is available. The DXE driver that produces the
EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL is responsible for directly updating the SetTime field of the UEFI
II-9.7.2.6 GetWakeupTime()
When the DXE Foundation is notified that the EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL has been in-
stalled, then the Runtime Service GetWakeupTime() is available. The DXE driver that produces the
EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL is responsible for directly updating the GetWakeupTime field of the
UEFI Runtime Services Table. The DXE Foundation is only responsible for updating the 32-bit CRC of the UEFI
Runtime Services Table.
II-9.7.2.7 SetWakeupTime()
stalled, then the Runtime Service SetWakeupTime() is available. The DXE driver that produces the
EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL is responsible for directly updating the SetWakeupTime field of the
II-9.7. Dependencies II-71UEFI Platform Initialization Specification, Release 1.8
II-9.7.2.8 SetVirtualAddressMap()

When the DXE Foundation is notified that the EFI_RUNTIME_ARCH_PROTOCOL has been installed, then the Runtime
ServiceSetVirtualAddressMap() isavailable. TheDXEdriverthatproducesthe EFI_RUNTIME_ARCH_PROTOCOL
isresponsiblefordirectlyupdatingthe SetVirtualAddressMap fieldoftheUEFIRuntimeServicesTable. TheDXE
II-9.7.2.9 ConvertPointer()
ServiceConvertPointer() is available. The DXE driver that produces the EFI_RUNTIME_ARCH_PROTOCOL is re-
sponsiblefordirectlyupdatingthe ConvertPointer fieldoftheUEFIRuntimeServicesTable. TheDXEFoundation
is only responsible for updating the 32-bit CRC of the UEFI Runtime Services Table.
II-9.7.2.10 ResetSystem()
When the DXE Foundation is notified that the EFI_RESET_ARCH_PROTOCOL has been installed, then the Runtime
ServiceResetSystem() is available. The DXE driver that produces the EFI_RESET_ARCH_PROTOCOL is responsible
for directly updating the Resetfield of the UEFI Runtime Services Table. The DXE Foundation is only responsible
for updating the 32-bit CRC of the UEFI Runtime Services Table.
II-9.7.2.11 GetNextHighMonotonicCount()
When the DXE Foundation is notified that the EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL has been installed,
then the Runtime Service GetNextHighMonotonicCount() is available. The DXE driver that produces the
EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL isresponsiblefordirectlyupdatingthe GetNextHighMonotonicCount
fieldoftheUEFIRuntimeServicesTable. TheDXEFoundationisonlyresponsibleforupdatingthe32-bitCRCofthe
UEFI Runtime Services Table.
II-9.7. Dependencies II-72UEFI Platform Initialization Specification, Release 1.8
II-9.7.3 DXE Services Dependencies
DXE Service Dependencies lists all the DXE Services and the components upon which each of these services depend.
ThetopicsthatfollowdescribewhatresponsibilitiestheDXEFoundationhasinproducingtheservicesthatdependon
the presence of DXE Architectural Protocols.
Table 9.3: DXE Service Dependencies
AddMemorySpace HOB list
AllocateMemorySpace HOB list
FreeMemorySpace HOB list
RemoveMemorySpace HOB list
GetMemorySpaceDescriptor CPU Architectural Protocol
SetMemorySpaceAttributes CPU Architectural Protocol
GetMemorySpaceMap CPU Architectural Protocol
AddIoSpace HOB list
AllocateIoSpace HOB list
FreeIoSpace HOB list
RemoveIoSpace HOB list
GetIoSpaceDescriptor HOB list
GetIoSpaceMap HOB list
Schedule HOB list
II-9.7.3.1 GetMemorySpaceDescriptor()
When the DXE Foundation is notified that the EFI_CPU_ARCH_PROTOCOL has been installed, then the DXE Service
GetMemorySpaceDescriptor() isfullyfunctional. Thisfunctionismadeavailablewhenthememory-basedservices
are initialized. However, the Attributes field of the EFI_GCD_MEMORY_SPACE_DESCRIPTOR is not valid until the
EFI_CPU_ARCH_PROTOCOL is installed.
II-9.7.3.2 SetMemorySpaceAttributes()
When the DXE Foundation is notified that the EFI_CPU_ARCH_PROTOCOL has been installed, then the
DXE Service SetMemorySpaceAttributes() can be made available. The DXE Foundation can then
use theSetMemoryAttributes() service of the EFI_CPU_ARCH_PROTOCOL to implement the DXE Service
SetMemorySpaceAttributes() .
II-9.7.3.3 GetMemorySpaceMap()
GetMemorySpaceMap() is fully functional. This function is made available when the memory-based services are
initialized. However,the Attributes fieldofthearrayof EFI_GCD_MEMORY_SPACE_DESCRIPTOR sisnotvaliduntil
theEFI_CPU_ARCH_PROTOCOL is installed.
II-9.7. Dependencies II-73UEFI Platform Initialization Specification, Release 1.8
II-9.8 HOB Translations
II-9.8.1 HOB Translations Overview
The following topics describe how the DXE Foundation should interpret the contents of the HOB list to initialize the
GCD memory space map, GCD I/O space map, and UEFI memory map. After all of the HOBs have been parsed,
the Boot Service GetMemoryMap() and the DXE Services GetMemorySpaceMap() andGetIoSpaceMap() should
reflect the memory resources, I/O resources, and logical memory allocations described in the HOB list.
SeeVolume 3 for detailed information on HOBs.
II-9.8.2 PHIT HOB
ThePhaseHandoffInformationTable(PHIT)HOBdescribesaregionoftestedsystemmemory. Thisregionofmemory
contains the following:
•HOB list
•Some amount of free memory
•Potentially some logical memory allocations
ThePHITHOBisusedbytheDXEFoundationtodeterminethesizeoftheHOBlistsothattheDXEFoundationcan
relocate the HOB list to a new location in system memory. The base address of the HOB list is passed to the DXE
Foundation in the parameter HobStart , and the PHIT HOB field EfiFreeMemoryBottom specifies the end of the
HOB list.
Since the PHIT HOB may contain some of amount of free memory, the DXE Foundation may use this free memory
region in its early initialization phase until the full complement of UEFI memory services are available.
SeeVolume 3 for the definition of this HOB type.
II-9.8.3 CPU HOB
The CPU HOB contains the field SizeOfMemorySpaceMap . This field is used to initialize the GCD memory
space map. The SizeOfMemorySpaceMap field defines the number of address bits that the processor can use to ad-
dress memory resources. The DXE Foundation must create the primordial GCD memory space map entry of type
EfiGcdMemoryTypeNonExistent for the region from 0 to (1 << SizeOfMemorySpaceMap) . All future GCD
memory space operations must be performed within this memory region.
The CPU HOB also contains the field SizeOfIoSpaceMap . This field is used to initialize the GCD I/O space map.
TheSizeOfIoSpaceMap field defines the number of address bits that the processor can use to address I/O resources.
The DXE Foundation must create the primordial GCD I/O space map entry of type EfiGcdIoTypeNonExistent for
the region from 0 to (1 << SizeOfIoSpaceMap) . All future GCD I/O space operations must be performed within
this I/O region.
II-9.8. HOB Translations II-74UEFI Platform Initialization Specification, Release 1.8
II-9.8.4 Resource Descriptor HOBs
TheDXEFoundationmusttraversetheHOBlistlookingforResourceDescriptorHOBs. TheseHOBsdescribememory
andI/Oresourcesthatarevisibletotheprocessor. AlloftheresourcerangesdescribedintheseHOBsmustfallinthe
memory and I/O ranges initialized in the GCD maps based on the contents of the CPU HOB. The DXE Foundation
willusetheDXEServices AddMemorySpace() andAddIoSpace() toregisterthesememoryandI/Oresourcesinthe
GCD maps.
TheOwnerfield of the Resource Descriptor HOB is ignored by the DXE Foundation. The ResourceType field and
ResourceAttribute fieldsareusedtodeterminetheGCDmemorytypeorGCDI/Otypeoftheresource. Thetable
below shows this mapping. The resource range is specified by the PhysicalStart andResourceLength fields of
the Resource Descriptor HOB.
TheResourceAttribute fieldalsocontainsthecachingcapabilitiesofmemoryregions. Ifamemoryregionisbeing
added to the GCD memory space map, then the ResourceAttribute field will be used to initialize the supported
cachingcapabilities. The ResourceAttribute fieldisalsobeusedtofurtherqualifymemoryregions. Forexample,
a system memory region cannot be added to the UEFI memory map if it is read protected. However, it is legal to add
a firmware device memory region that is write-protected if the firmware device is a ROM.
Table 9.4: Resource Descriptor HOB to GCD Type Mapping
Resource Descriptor HOB GCD Map
Resource Type Attributes Memory Type I/O Type
System Memory Present Reserved
System Memory Present AND Initialized Reserved
System Memory Present AND Initialized AND Tested System Memory
Memory Mapped I/O Memory Mapped I/O
Firmware Device Memory Mapped I/O
Memory Mapped I/O Port Reserved
Memory Reserved Reserved
Unaccepted Memory Unaccepted
I/O I/O
I/O Reserved Reserved
II-9.8.5 Firmware Volume HOBs
TheDXEFoundationmusttraversetheHOBlistforFirmwareVolumeHOBs. Therearetwotypesoffirmwarevolume
HOBs:
•EFI_HOB_FIRMWARE_VOLUME , which describes PI Firmware Volumes.
•EFI_HOB_FIRMWARE_VOLUME2 which describes PI Firmware Volumes which came from a firmware file within
a firmware volume.
When the DXE Foundation discovers a Firmware Volume HOB, the DXE Dispatcher verifies that the firmware
volume has not been previously processed. Then a new handle must be created in the handle database, and the
EFI_FIRMWARE_VOLUME2_PROTOCOL must be installed on that handle. The BaseAddress andLengthfields of
the Firmware Volume HOB specific the memory range that the firmware volume consumes. The DXE Service
AllocateMemorySpace() is used to allocate the memory regions described in the Firmware Volume HOBs to the
DXEFoundation. TheUEFIBootService InstallProtocolInterface() isusedtocreatenewhandlesand install

I/O I/O
HOBs:
SeethePlatformInitializationSpecification ,Volume3,forcodedefinitionsconcerningHand-OffBlocks,theFirmware
Volume Block Protocol and the Firmware Volume Protocol.
II-9.8. HOB Translations II-75UEFI Platform Initialization Specification, Release 1.8
II-9.8.6 Memory Allocation HOBs
MemoryAllocationHOBsdescribelogicalmemoryallocationsthatoccurredpriortotheDXEphase. TheDXEFoun-
dation must parse the HOB list for this HOB type. When a HOB of this type is discovered, the GCD memory space
mapmustbeupdatedwithacalltotheDXEService AllocateMemorySpace() . Inaddition,theUEFImemorymap
must be updated with logical allocation described by the MemoryType ,MemoryBaseAddress , andMemoryLength
fields of the Memory Allocation HOB.
Once the DXE Foundation has parsed all of the Memory Allocation HOBs, all of the unallocated system mem-
ory regions in the GCD memory space map must be allocated to the DXE Foundation with the DXE Service
AllocateMemorySpace() . In addition, those same memory regions must be added to the UEFI memory map so
those memory regions can be allocated and freed using the Boot Services AllocatePages() ,AllocatePool() ,
FreePages() , andFreePool() .
II-9.8.7 GUID Extension HOBs
The DXE Foundation does not require any GUID Extension HOBs. Implementations of the DXE Foundation may
use GUID Extension HOBs but shall not require them in order to function correctly. GUID Extension HOBs contain
privateorimplementation-specificdatathatisbeingpassedfromthepreviousexecutionphasetoaspecificDXEdriver.
DXE drivers may choose to parse the HOB list for GUID Extension HOBs.
II-9.8. HOB Translations II-76CHAPTER
TEN
DXE DISPATCHER
II-10.1 Introduction
AftertheDXEFoundationisinitialized,controlishandedtotheDXEDispatcher. TheDXEDispatcherexaminesevery
firmwarevolumethatispresentinthesystem. FirmwarevolumesareeitherdeclaredbyHOBs,ortheyaredeclaredby
DXE drivers. For the DXE Dispatcher to run, at least one firmware volume must be declared by a HOB.
The DXE Dispatcher is responsible for loading and invoking DXE drivers found in firmware volumes. Some DXE
driversmaydependontheservicesproducedbyotherDXEdrivers,sotheDXEDispatcherisalsorequiredtoexecute
the DXE drivers in the correct order. The DXE drivers may also be produced by a variety of different vendors, so the
DXE drivers must describe the services they depend upon. The DXE dispatcher must evaluate these dependencies to
determineavalidordertoexecutetheDXEdrivers. Somevendorsmaywishtospecifyafixedexecutionorderforsome
or all of the DXE drivers in a firmware volume, so the DXE dispatcher must support this requirement.
The DXE Dispatcher will ignore file types that it does not recognize.
In addition, the DXE Dispatcher must support the ability to load “emergency patch” drivers. These drivers would be
addedtothefirmwarevolumetoaddressanissuethatwasnotknowatthetimetheoriginalfirmwarewasbuilt. These
DXE drivers would be loaded just before or just after an existing DXE driver.
Finally, the DXE Dispatcher must be flexible enough to support a variety of platform specific security policies for
loading and executing DXE drivers from firmware volumes. Some platforms may choose to run DXE drivers with no
security checks, and others may choose to check the validity of a firmware volume before it is used, and other may
choose to check the validity of every DXE driver in a firmware volume before it is executed.
II-10.2 Requirements
The DXE Dispatcher must meet the following requirement:
•SupportfixedexecutionorderofDXEdrivers. Thisfixedexecutionorderisspecifiedinan apriorifileinthe
•DetermineDXEdriverexecutionorderbasedoneachdriver’sdependencies. ADXEdriverthatisstoredin
afirmwarevolumemayoptionallycontainadependencyexpressionsection. Thissectionspecifiestheprotocols
that the DXE driver requires to execute.
•Support “emergency patch” DXE drivers. The dependency expressions are flexible enough to describe the
protocols that a DXE drivers may require. In addition, the dependency expression can declare that the DXE
driver is to be loaded and executed immediately before or immediately after a different DXE driver.
•SupportplatformspecificsecuritypoliciesforDXEdriverexecution. TheDXEDispatcherisrequiredtouse
the services of the Security Architecture Protocol every time a firmware volume is discovered and every time a
DXE driver is loaded.
II-77UEFI Platform Initialization Specification, Release 1.8
When a new firmware volume is discovered, it is first authenticated with the Security Architectural Protocol. The
Security Architectural Protocol provides the platform-specific policy for validating all firmware volumes. Then, a
search is made for the a priorifile. Thea priorifile has a fixed file name, and it contains the list of DXE drivers that
shouldbe loadedandexecuted first. There canbeat mostone apriorifileper firmwarevolume,and itislegal tohave
zeroa priorifiles in a firmware volume. Once the DXE drivers from the a priorifile have been loaded and executed,
the dependency expressions of the remaining DXE drivers in the firmware volumes are evaluated to determine the
order that they will be loaded and executed. The a priorifile provides a strongly ordered list of DXE drivers that are
not required to use dependency expressions. The dependency expressions provide a weakly ordered execution of the
remaining DXE drivers.
The DXE Dispatcher loads the image using LoadImage() with theFilePath parameter pointing ot the firmware
volume from which the image is located.
BeforeeachDXEdriverisexecuted,itmustbeauthenticatedthroughtheSecurityArchitecturalProtocol. TheSecurity
Architectural Protocol provides the platform-specific policy for validating all DXE drivers.
ControlistransferredfromtheDXEDispatchertotheBDSArchitecturalProtocolaftertheDXEdriversinthe apriori
fileandalltheDXEdriverswhosedependencyexpressionsevaluateto TRUEhavebeenloadedandexecuted. TheBDS
ArchitecturalProtocolisresponsibleforestablishingtheconsoledevicesandattemptingthebootofoperatingsystems.
As the console devices are established and access to boot devices is established, additional firmware volumes may be
discovered. IftheBDSArchitecturalProtocolisunabletostartaconsoledeviceorgainaccesstoabootdevice,itwill
reinvoke the DXE Dispatcher. This will allow the DXE Dispatcher to load and execute DXE drivers from firmware
volumesthathavebeendiscoveredsincethelasttimetheDXEDispatcherwasinvoked. OncetheDXEDispatcherhas
loaded and executed all the DXE drivers it can, control is once again returned to the BDS Architectural Protocol to
continue the OS boot process.
II-10.3 The A Priori File
Theapriorifileisaspecialfilethatmaybepresentinafirmwarevolume. The apriorifileformatdescribedhereinmust
be supported if the DXE Foundation implementation also supports 3rd party firmware volumes. The rule is that there
may be at most one a priorifile per firmware volume present in a platform. The a priorifile has a known GUID file
name,sotheDXEDispatchercanalwaysfindthe apriorifileifitispresent. EverytimetheDXEDispatcherdiscovers
afirmwarevolume,itfirstlooksforthe apriorifile. TheapriorifilecontainsthelistofDXEdriversfromthatfirmware
volume that should be loaded and executed before any other DXE drivers are discovered. The DXE drivers listed in
theapriorifileareexecutedintheorderthattheyappear. IfanyofthoseDXEdrivershaveanassociateddependency
expression, then those dependency expressions are ignored. The a priorifile provides a deterministic execution order
of DXE drivers. DXE drivers that are executed solely based on their dependency expression are weakly ordered. This
means that the execution order is not completely deterministic between boots or between platforms. There are cases
whereadeterministicexecutionorderisrequired. OneexamplewouldbetolisttheDXEdriversrequiredtodebugthe
restoftheDXEphaseinthe apriorifile. TheseDXEdriversthatprovidedebugservicesmayhavebeenloadedmuch
later if only their dependency expressions were considered. By loading them earlier, more of the DXE Foundation
and DXE drivers can be debugged. Another example is to use the a priorifile to eliminate the need for dependency
expressions. Some embedded platforms may only require a few DXE drivers with a highly deterministic execution
order. The apriorifilecanprovidethisordering,andnoneoftheDXEdriverswouldrequiredependencyexpressions.
The dependency expressions do have some amount of size overhead, so this method may reduce the size of firmware
images. The main purpose of the a priorifile is to provide a greater degree of flexibility in the firmware design of a
platform.
SeethenexttopicfortheGUIDdefinitionofthe apriorifile,whichisthefilenamethatisstoredinafirmwarevolume.
TheapriorifilecontainsthefilenamesofDXEdriversthatarestoredinthesamefirmwarevolumeasthe apriorifile.
FilenamesinfirmwarevolumesareGUIDs,sothe apriorifileissimplyalistofbyte-packedvaluesoftype EFI_GUID

platform.
. TypeEFI_GUID is defined in the UEFI 2.0 specification. The DXE Dispatcher reads the list of EFI_GUID s from the
apriorifile. Each EFI_GUID isusedto loadandexecutetheDXEdriver withthatGUIDfilename. IftheDXE driver
specifiedbytheGUIDfilenameisnotfoundinthefirmwarevolume,thenthefileisskipped. Ifthe apriorifileisnot
II-10.3. The A Priori File II-78UEFI Platform Initialization Specification, Release 1.8
en even multiple of EFI_GUID s in length, then the DXE driver specified by the last EFI_GUID in thea priorifile is
skipped.
AfteralloftheDXEdriverslistedinthe apriorifilehavebeenloadedandexecuted,theDXEDispatchersearchesthe
firmware volume for any additional DXE drivers and executed them according to their dependency expressions.
II-10.3.1 EFI_APRIORI_GUID
The following GUID definition is the file name of the a priorifile that is stored in a firmware volume. This file must
be of type EFI_FV_FILETYPE_FREEFORM and must contain a single section of type EFI_SECTION_RAW . For details
onfirmwarevolumes,firmwarefiletypes,andfirmwarefilesectiontypes,seethe PlatformInitializationSpecification ,
Volume 3 .
GUID
#define EFI_APRIORI_GUID \
{0xfc510ee7,0xffdc,0x11d4,0xbd,0x41,0x0,0x80,
0xc7,0x3c,0x88,0x81}
II-10.4 Firmware Volume Image Files
For DXE, while processing a firmware volume, if a file of type EFI_FV_FIRMWARE_VOLUME_IMAGE is found, the
DXE Dispatcher will check whether information about this firmware volume image file was already described in an
EFI_FIRMWARE_VOLUME_HOB2 . If it was, then the file is ignored.
Otherwise,theDXEDispatcherwillsearchthefileforasectionwiththetype EFI_SECTION_DXE_DEPEX ,andiffound,
evaluate the expression against the presently installed entries in the protocol database.
Ifthefilehasbothadependencyexpressionthatevaluatesto TRUE(ornodependencyexpressionsection)andthefileis
notalreadydescribedbyan EFI_FIRMWARE_VOLUME_HOB2 ,thentheDXEDispatcherwillsearchthefileforasection
with the type EFI_SECTION_FIRMWARE_VOLUME_IMAGE , copy its contents into memory, create a handle and install
theEFI_FIRMWMARE_VOLUME2_PROTOCOL andEFI_DEVICE_PATH_PROTOCOL on the handle.
II-10.5 Dependency Expressions
II-10.6 Dependency Expressions Overview
ADXEdriverisstoredinafirmwarevolumeasafilewithoneormoresections. OneofthesectionsmustbeaPE32+
image. If a DXE driver has a dependency expression, then it is stored in a dependency section . A DXE driver may
containadditionalsectionsforcompressionandsecuritywrappers. TheDXEDispatchercanidentifytheDXEdrivers
bytheirfiletype. Inaddition,theDXEDispatchercanlookupthedependencyexpressionforaDXEdriverbylooking
foradependencysectioninaDXEdriverfile. Thedependencysectioncontainsasectionheaderfollowedbytheactual
dependency expression that is composed of a packed byte stream of opcodes and operands.
Dependency expressions stored in dependency sections are designed to be small to conserve space. In addition, they
are designed to be simple and quick to evaluate to reduce execution overhead. These two goals are met by designing
a small, stack based, instruction set to encode the dependency expressions. The DXE Dispatcher must implement an
interpreter for this instruction set in order to evaluate dependency expressions. The instruction set is defined in the
following topics.
II-10.4. Firmware Volume Image Files II-79UEFI Platform Initialization Specification, Release 1.8
SeeDependencyExpressionGrammar foranexampleBNFgrammarforadependencyexpressioncompiler. Thereare
manypossiblemethodsofspecifyingthedependencyexpressionforaDXEdriver. DependencyExpressionGrammar
demonstrates one possible design for a tool that can be used to help build DXE driver images.
II-10.7 Dependency Expression Instruction Set
Thefollowingtopicsdescribeeachofthedependencyexpressionopcodesindetail. Informationincludesadescription
of the instruction functionality, binary encoding, and any limitations or unique behaviors of the instruction.
that is described in the UEFI 2.0 specification. These GUIDs represent protocols that are produced by DXE drivers
and the file names of DXE drivers stored in firmware volumes. A dependency expression is a packed byte stream of
opcodes and operands. As a result, some of the GUID operands will not be aligned on natural boundaries. Care must
be taken on processor architectures that do allow unaligned accesses.
addition,DXEdriversthatcontaindependencyexpressionsshouldmakeanefforttokeeptheirdependencyexpressions
as small as possible to help reduce the size of the DXE driver.
toFALSE.
IfanENDopcodeisnotpresentinadependencyexpression,thentheentiredependencyexpressionevaluatesto FALSE
.
If an instruction encoding extends beyond the end of the dependency section, then the entire dependency expression
evaluates to FALSE.
The following topics describe each of these instructions in detail.
Table 10.1: Dependency Expression Opcode Summary
0x00 BEFORE <File Name GUID>
0x01 AFTER <File Name GUID>
0x02 PUSH <Protocol GUID>
0x03 AND
0x04 OR
0x05 NOT
0x06 TRUE
0x07 FALSE
0x08 END
0x09 SOR
II-10.7. Dependency Expression Instruction Set II-80UEFI Platform Initialization Specification, Release 1.8
II-10.7.1 BEFORE
Syntax
BEFORE <File Name GUID>
This opcode tells the DXE Dispatcher that the DXE driver that is associated with this dependency expression must be
dispatchedjustbeforetheDXEdriverwiththefilenamespecifiedby GUID.Thismeansthatassoonasthedependency
expressionfortheDXEdriverspecifiedby GUIDevaluatesto TRUE,thenthisDXEdrivermustbeplacedinthedispatch
queue just before the DXE driver with the file name specified by GUID.
Operation
None.
BEFORE Instruction Encoding defines the BEFOREinstruction encoding.
Table 10.2: BEFORE Instruction Encoding
ByteDescription
00x00
1..16A 16-byte GUID that represents the file name of a different DXE driver. The format is the same as type
EFI_GUID .
Ifthisopcodeispresentinadependencyexpression,itmustbethefirstandonlyopcodeintheexpression. Ifisappears
in any other location in the dependency expression, then the dependency expression is evaluated to FALSE.
II-10.7.2 AFTER
Syntax
AFTER <File Name GUID>
dispatchedjustaftertheDXEdriverwiththefilenamespecifiedby GUID.Thismeansthatassoonasthedependency
queue just after the DXE Driver with the file name specified by GUID.
Operation
None.
AFTER Instruction Encoding defines the AFTERinstruction encoding.
Table 10.3: AFTER Instruction Encoding
00x01
EFI_GUID .
II-10.7. Dependency Expression Instruction Set II-81UEFI Platform Initialization Specification, Release 1.8
II-10.7.3 PUSH
Syntax
PUSH <Protocol GUID>
in the handle database may be performed with the Boot Service LocateProtocol() .
Operation
Status = gBS->LocateProtocol (GUID, NULL, &Interface);
} Else {
PUSH TRUE;
}
PUSH Instruction Encoding defines the PUSHinstruction encoding.
Table 10.4: PUSH Instruction Encoding
00x02
1..16A 16-byte GUID that represents a protocol that is produced by a different DXE driver. The format is the

Syntax
Operation
} Else {
PUSH TRUE;
}
00x02
same at type EFI_GUID .
None.
II-10.7.4 AND
Syntax
AND
Operation
II-10.7. Dependency Expression Instruction Set II-82UEFI Platform Initialization Specification, Release 1.8
Table 10.5: AND Instruction Encoding
00x03.
None.
II-10.7.5 OR
Syntax
OR
PopstwoBooleanoperandsoffthestack,performsaBooleanORoperationbetweenthetwooperands,andpushesthe
OPeration
Table 10.6: OR Instruction Encoding
00x04.
None.
II-10.7.6 NOT
Syntax
NOT
PopsaBooleanoperandsoffthestack,performsaBooleanNOToperationontheoperand,andpushestheresultback
Operation
Result <= NOT Operand1
II-10.7. Dependency Expression Instruction Set II-83UEFI Platform Initialization Specification, Release 1.8
Table 10.7: NOT Instruction Encoding
00x05.
None.
II-10.7.7 TRUE
Syntax
TRUE
Operation
PUSH TRUE
Table 10.8: TRUE Instruction Encoding
00x06.
None.
II-10.7.8 FALSE
Syntax
FALSE
Operation
PUSH FALSE
Table 10.9: FALSE Instruction Encoding
00x07.
II-10.7. Dependency Expression Instruction Set II-84UEFI Platform Initialization Specification, Release 1.8
None.
II-10.7.9 END
Syntax
END
Operation
POP Result
Table 10.10: END Instruction Encoding
00x08.
II-10.7.10 SOR
Syntax
SOR
IndicatesthattheDXEdriveristoremainontheScheduleonRequest(SOR)queueuntiltheDXEService Schedule()
is called for this DXE. The dependency expression evaluator treats this operation like a No Operation ( NOP).
Operation
None.
SOR Instruction Encoding defines the SORinstruction encoding.
Table 10.11: SOR Instruction Encoding
00x09.
•If this instruction is present in a dependency expression, it must be the first instruction in the expression. If
it appears in any other location in the dependency expression, then the dependency expression is evaluated to
FALSE.
II-10.7. Dependency Expression Instruction Set II-85UEFI Platform Initialization Specification, Release 1.8
•This instruction must be followed by a valid dependency expression. If this instruction is the last instruction or
it is followed immediately by an ENDinstruction, then the dependency expression is evaluated to FALSE.
II-10.8 Dependency Expression with No Dependencies
ADXEdriverthatdoesnothaveanydependenciesmusthaveadependencyexpressionthatevaluatesto TRUEwithno
dependenciesonanyprotocolGUIDsorfilenameGUIDs. TheDXEDispatcherwillqueuealltheDXEdriversofthis
typeimmediatelyafterthe apriorifilehasbeenprocessed. Thefollowingcodeexampleshowsthedependencyexpres-
sion for a DXE driver that does not have any dependencies using the BNF grammar listed in Dependency Expression
Grammar. This is followed by the 2-byte dependency expression that is encoded using the instruction set described in
Dependency Expression Instruction Set .
//
// Source
//
TRUE
END
//
//
==== =======================
===============================================
0x00 : 06 TRUE
0x01 : 08 END
II-10.9 Empty Dependency Expressions
IfaDXEdriverfiledoesnotcontainadependencysection,thentheDXEdriverhasanemptydependencyexpression.
The DXE Foundation must support DXE driver and UEFI drivers that conform to the UEFI 2.0 specification. These
UEFI drivers assume that all the UEFI Boot Services and UEFI Runtime Services are available. If an UEFI driver
is added to a firmware volume, then the UEFI driver will have an empty dependency expression, and it should not be
loadedandexecutedbytheDXEDispatcheruntilalltheUEFIBootServicesandUEFIRuntimeServicesareavailable.
TheDXEFoundationcannotguaranteethatthisconditionistrueuntilalloftheDXEArchitecturalProtocolshavebeen
From the DXE Dispatcher’s perspective, DXE drivers without dependency expressions cannot be loaded until all of
theDXEArchitecturalProtocolshavebeeninstalled. Thisisequivalenttoanimplieddependencyexpressionofallthe
GUIDs of the architectural protocols ANDed together. This implied dependency expression is shown below. The use
of empty dependency expressions may also save space, because DXE drivers that require all the UEFI Boot Services
and UEFI Runtime Services to be present can simply remove the dependency section from the DXE driver file.
Thecodeexamplebelowshowsthedependencyexpressionthatisimpliedbyanemptydependencyexpressionusingthe
BNF grammar listed in Dependency Expression Grammar . It also shows the dependency expression after it has been
encodedusingtheinstructionsetdescribedin DependencyExpressionInstructionSet . Thisfairlycomplexdependency
expressionisencodedintoadependencyexpressionthatis216byteslong. Typicaldependencyexpressionswillcontain
2 or 3 terms, so those dependency expressions will
typically be less than 60 bytes long.
//
II-10.8. Dependency Expression with No Dependencies II-86UEFI Platform Initialization Specification, Release 1.8
// Source
//
EFI_BDS_ARCH_PROTOCOL_GUID AND
EFI_CPU_ARCH_PROTOCOL_GUID AND
EFI_METRONOME_ARCH_PROTOCOL_GUID AND
EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL_GUID AND
EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID AND
EFI_RESET_ARCH_PROTOCOL_GUID AND
EFI_RUNTIME_ARCH_PROTOCOL_GUID AND
EFI_SECURITY_ARCH_PROTOCOL_GUID AND
EFI_TIMER_ARCH_PROTOCOL_GUID AND
EFI_VARIABLE_ARCH_PROTOCOL_GUID AND
EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID AND
EFI_WATCHDOG_TIMER_ARCH_PROTOCOL_GUID
END
//
//
0x01 : F6 3F 5E 66 CC 46 d4 11 EFI_BDS_ARCH_PROTOCOL_GUID
9A 38 00 90 27 3F C1 4D
0x12 : B1 CC BA 26 42 6F D4 11 EFI_CPU_ARCH_PROTOCOL_GUID
BC E7 00 80 C7 3C 88 81
0x23 : 02 PUSH
0x24 : B2 CC BA 26 42 6F d4 11 EFI_METRONOME_ARCH_PROTOCOL_GUID
0x34 : 02 PUSH
0x35 : 72 70 A9 1D DC BD 30 4B
EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL_GUID
99 F1 72 A0 B5 6F FF 2A
0x45 : 03 AND
0x46 : 03 AND
0x47 : 02 PUSH
0x48 : 87 AC CF 27 CC 46 d4 11
EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID
0x58 : 02 PUSH
0x59 : 88 AC CF 27 CC 46 d4 11 EFI_RESET_ARCH_PROTOCOL_GUID
0x69 : 03 AND
0x6A : 02 PUSH
0x6B : 53 82 d0 96 83 84 d4 11 EFI_RUNTIME_ARCH_PROTOCOL_GUID
BC F1 00 80 C7 3C 88 81
0x7B : 02 PUSH
0x7C : E3 23 64 A4 17 46 f1 49 EFI_SECURITY_ARCH_PROTOCOL_GUID
B9 FF D1 BF A9 11 58 39
II-10.9. Empty Dependency Expressions II-87UEFI Platform Initialization Specification, Release 1.8
82 CE 5A 89 0C CB 2C 95
0xA0 : 02 PUSH
0xA1 : B3 CC BA 26 42 6F D4 11 EFI_TIMER_ARCH_PROTOCOL_GUID
0xB1 : 03 AND
0xB2 : 02 PUSH
0xB3 : E2 68 56 1E 81 84 D4 11 EFI_VARIABLE_ARCH_PROTOCOL_GUID
0xC3 : 02 PUSH
0xC4 : 18 F8 41 64 62 63 44 4E EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID
B5 70 7D BA 31 DD 24 53
0xD4 : 03 AND
0xD5 : 03 AND
0xD6 : 03 AND
0xD7 : 02 PUSH
0xD8 : F5 3F 5E 66 CC 46 d4 11 EFI_WATCHDOG_TIMER_ARCH_PROTOCOL_GUID
0xE8 : 03 AND
0xE9 : 08 END
II-10.10 Dependency Expression Reverse Polish Notation (RPN)
The actual equations will be presented by the DXE driver in a simple-to-evaluate form, namely postfix.
The following is a BNF encoding of this grammar. See `Dependency Expression Instruction Set <V2-DXE-
Dispatcher.htm#80631> `__ for definitions of the dependency expressions.
<statement> ::= SOR <expression> END |
BEFORE <guid> END |
AFTER <guid> END |
<expression> END
TRUE |
FALSE |
II-10.11 DXE Dispatcher State Machine

TRUE |
FALSE |
TheDXEDispatcherisresponsiblefortrackingthestateofaDXEdriverfromthetimethattheDXEdriverisdiscovered
inafirmwarevolumeuntiltheDXEFoundationisterminatedwithacallto ExitBootServices() . Duringthistime,
eachDXEdrivermaybeinoneofseveraldifferentstates. ThestatemachinethattheDXEDispatchermustusetotrack
a DXE driver is shown in DXE Driver States .
A DXE driver starts in the “Undiscovered” state, which means that the DXE driver is in a firmware volume that the
DXE Dispatcher does not know about yet. When the DXE Dispatcher discovers a new firmware volume, any DXE
drivers from that firmware volume listed in the a priorifile are immediately loaded and executed. DXE drivers listed
intheapriorifileareimmediatelypromotedtothe“Scheduled”state. ThefirmwarevolumeisthensearchedforDXE
II-10.10. Dependency Expression Reverse Polish Notation (RPN) II-88UEFI Platform Initialization Specification, Release 1.8
Fig. 10.1: DXE Driver States
drivers that are not listed in the a priorifile. Any DXE drivers found are promoted from the “Undiscovered” to the
“Discovered” state. The dependency expression for each DXE driver is evaluated. If the SOR opcode is present in a
DXE driver’s dependency expression, then the DXE driver is placed in the “Unrequested” state. If the SOR opcode is
notpresentintheDXEdriver’sdependencyexpression,thentheDXEdriverisplacedinthe“Dependent”state. Once
a DXE driver is in the “Unrequested” state, it may only be promoted to the “Dependent” state with a call to the DXE
ServiceSchedule() .
OnceaDXEDriverisinthe“Dependent”state,theDXEDispatcherwillevaluatetheDXEdriver’sdependencyexpres-
sion. If the DXE driver does not have a dependency expression, then a dependency expression of all the architectural
protocolsANDedtogetherisassumedforthatDXEdriver. Ifthedependencyexpressionevaluatesto FALSE,thenthe
DXE driver stays in the “Dependent” state. If the dependency expression never evaluates to TRUE, then it will never
leave the “Dependent” state. If the dependency expression evaluates to TRUE, then the DXE driver will be promoted
to the “Scheduled” state.
ADXEdriverthatispromptedtothe“Scheduled”stateisaddedtotheendofthequeueofotherDXEdriversthathave
beenpromotedtothe“Scheduled”state. WhentheDXEdriverhasreachedtheheadofthequeue,theDXEDispatcher
must use the services of the Security Authentication Protocol (SAP) to check the authentication status of the DXE
Driver. IftheSecurityAuthenticationProtocoldeemsthattheDXEDriverviolatesthesecuritypolicyoftheplatform,
then the DXE Driver is placed in the “Untrusted” state. The Security Authentication Protocol can also tell the DXE
DispatcherthattheDXEdrivershouldneverbeexecutedandbeplacedinthe“NeverTrusted”state. IfaDXEdriveris
placed in the “Untrusted” state, it can only be promoted back to the “Scheduled” state with a call to the DXE Service
Trust() .
Once a DXE driver has reached the head of the scheduled queue, and the DXE driver has passed the authenti-
cation checks of the Security Authentication Protocol, the DXE driver is loaded into memory with the Boot Ser-
viceLoadImage() . Control is then passed from the DXE Dispatcher to the DXE driver with the Boot Service
StartImage() . WhenStartImage() is called for a DXE driver, that DXE driver is promoted to the “Initializ-
ing” state. The DXE driver returns control to the DXE Dispatcher through the Boot Service Exit(). When a DXE
driver has returned control to the DXE Dispatcher, the DXE driver is in the terminal state called “Initialized.”
The DXE Dispatcher is responsible for draining the queue of DXE drivers in the “Scheduled” state until the queue is
empty. Once the queue is empty, then DXE Dispatcher must evaluate all the DXE drivers in the “Dependent” state to
II-10.11. DXE Dispatcher State Machine II-89UEFI Platform Initialization Specification, Release 1.8
see if any of them need to be promoted to the “Scheduled” state. These evaluations need to be performed every time
oneormoreDXEdrivershavebeenpromotedtothe“Initialized”state,becausethoseDXEdriversmayhaveproduced
protocol interfaces for which the DXE drivers in the “Dependent” state are waiting.
II-10.12 Example Orderings
TheorderthatDXEdriversareloadedandexecutedbytheDXEDispatcherisamixofstrongandweakorderings. The
strongorderingsarespecifiedthrough apriorifiles,andtheweakorderingsarespecifiedbydependencyexpressionsin
DXE drivers. Sample Firmware Volume shows the contents of a sample firmware volume that contains the following:
•DXE Foundation image
•DXE driver images
•Ana priorifile
Theorderthattheseimagesappearinthefirmwarevolumeisarbitrary. TheDXEFoundationandtheDXEDispatcher
must not make any assumptions about the locations of files in firmware volumes. The a priorifile contains the GUID
file names of the DXE drivers that are to be loaded and executed first. The dependency expressions and the protocols
that each DXE driver produces is shown next to each DXE driver image in the firmware volume.
Fig. 10.2: Sample Firmware Volume
Based on the contents of the firmware volume in the figure above, the Security Driver, Runtime Driver, and Variable
Driver will always be executed first. This is an example of a strongly ordered dispatch due to the a priorifile. The
DXE Dispatcher will then evaluate the dependency expressions of the remaining DXE drivers to determine the order
that they will be executed. Based on the dependency expressions and the protocols that each DXE driver produces,
there are 30 valid orderings from which the DXE Dispatcher may choose. The BDS Driver and CPU Driver tie for
the next drivers to be scheduled, because their dependency expressions are simply TRUE. A dependency expression of
TRUE means that the DXE driver does not require any other protocol interfaces to be executed. The DXE Dispatcher
maychooseeitheroneofthesedriverstobescheduledfirst. TheTimerDriver,MetronomeDriver,andResetDriverall
depend on the protocols produced by the CPU Driver. Once the CPU Driver has been loaded and executed, the Timer
Driver, Metronome Driver, and Reset Driver may be scheduled in any order. The table below shows all 30 possible
II-10.12. Example Orderings II-90UEFI Platform Initialization Specification, Release 1.8
orderings from the sample firmware volume in the figure above. Each ordering is listed from left to right across the
table. A reasonable implementation of a DXE Dispatcher would consistently produce the same ordering for a given
system configuration. If the configuration of the system is changed in any way (including a order of files stored in a
firmwarevolume),thenadifferentdispatchorderingmaybegenerated,butthisneworderingshouldbeconsistentuntil
the next system configuration change.
Table 10.12: DXE Dispatcher Orderings
Dispatch Order
1 2 3 45 6 7 8
1 Security Runtime Variable BDSCPU Timer Metronome Reset
2 Security Runtime Variable BDSCPU Timer Reset Metronome
3 Security Runtime Variable BDSCPU Metronome Timer Reset
4 Security Runtime Variable BDSCPU Metronome Reset Timer
5 Security Runtime Variable BDSCPU Reset Timer Metronome
6 Security Runtime Variable BDSCPU Reset Metronome Timer
7 Security Runtime Variable CPUBDS Timer Metronome Reset
8 Security Runtime Variable CPUBDS Timer Reset Metronome
9 Security Runtime Variable CPUBDS Metronome Timer Reset
10 Security Runtime Variable CPUBDS Metronome Reset Timer
11 Security Runtime Variable CPUBDS Reset Timer Metronome
12 Security Runtime Variable CPUBDS Reset Metronome Timer
13 Security Runtime Variable CPUTimer BDS Metronome Reset
14 Security Runtime Variable CPUTimer BDS Reset Metronome
15 Security Runtime Variable CPUTimer Metronome BDS Reset
16 Security Runtime Variable CPUTimer Metronome Reset BDS
17 Security Runtime Variable CPUTimer Reset BDS Metronome
18 Security Runtime Variable CPUTimer Reset Metronome BDS
19 Security Runtime Variable CPUMetronome Timer BDS Reset
20 Security Runtime Variable CPUMetronome Timer Reset BDS
21 Security Runtime Variable CPUMetronome BDS Timer Reset
22 Security Runtime Variable CPUMetronome BDS Reset Timer
23 Security Runtime Variable CPUMetronome Reset Timer BDS
24 Security Runtime Variable CPUMetronome Reset BDS Timer
25 Security Runtime Variable CPUReset Timer Metronome BDS
26 Security Runtime Variable CPUReset Timer BDS Metronome
27 Security Runtime Variable CPUReset Metronome Timer BDS
28 Security Runtime Variable CPUReset Metronome BDS Timer
29 Security Runtime Variable CPUReset BDS Timer Metronome
30 Security Runtime Variable CPUReset BDS Metronome Timer
II-10.13 Security Considerations
TheDXEDispatcherisrequiredtousetheservicesoftheSecurityArchitecturalProtocoleverytimeafirmwarevolume
is discovered and before each DXE driver is executed. Because the Security Architectural Protocol is produced by a
DXEdriver, there willbe atleast onefirmware volumediscovered, andone ormore DXEdrivers loadedand executed
before the Security Architectural Protocol is installed. The DXE Dispatcher should not attempt to use the services

of the Security Architectural Protocol until the Security Architectural Protocol is installed. If a platform requires the
SecurityArchitecturalProtocoltobepresentveryearlyintheDXEphase,thenthe apriorifilemaybeusedtospecify
the name of the DXE driver that produces the Security Architectural Protocol.
The Security Architectural Protocol provides a service to evaluate the authentication status of a file. This service can
II-10.13. Security Considerations II-91UEFI Platform Initialization Specification, Release 1.8
alsobeusedtoevaluatetheauthenticatestatusofafirmwarevolume. Iftheauthenticationstatusisgood,thennoaction
istaken. Ifthereisaproblemwiththefirmwarevolume’sauthenticationstatus,thentheSecurityArchitecturalProtocol
may perform a platform specific action. One option is to force the DXE Dispatcher to ignore the firmware volume so
noDXEdriverswillbeloadedandexecutedfromit. AnotheristologthefactthattheDXEDispatcherisgoingtostart
dispatching DXE driver from a firmware volume with a questionable authentication status.
TheSecurityArchitecturalProtocolcanalsobeusedtoevaluatetheauthenticationstatusofeachDXEdriverdiscovered
in a firmware volume. If the authentication status is good, then no action is taken. If there is a problem with the
DXE driver’s authentication status, then the Security Architectural Protocol may take a platform-specific action. One
possibilityistoforcetheDXEdriverintothe“Untrusted”state,soitwillnotbeconsideredfordispatchuntiltheBoot
ServiceTrust() iscalledforthatDXEdriver. AnotherpossibilityistohavetheDXEDispatcherplacetheDXEdriver
inthe“NeverTrusted”state,soitwillneverbeloadedorexecuted. AnotheroptionistologthefactthataDXEdriver
with a questionable authentication status is about to be loaded and executed.
II-10.13. Security Considerations II-92CHAPTER
ELEVEN
DXE DRIVERS
II-11.1 Introduction
The DXE architecture provides a rich set of extensible services that provides for a wide variety of different system
firmware designs. The DXE Foundation provides the generic services required to locate and execute DXE drivers.
The DXE drivers are the components that actually initialize the platform and provide the services required to boot
an UEFI-compliant operating system or a set of UEFI-compliant system utilities. There are many possible firmware
implementationsforanygivenplatform. BecausetheDXEFoundationhasfixedfunctionality,alltheaddedvalueand
flexibility in a firmware design is embodied in the implementation and organization of DXE drivers.
There are two basic classes of DXE drivers:
•Early DXE Drivers
•DXE Drivers that follow the UEFI Driver Model
Additional classifications of DXE drivers are also possible.
All DXE drivers may consume the UEFI Boot Services, UEFI Runtime Services, and DXE Services to perform their
functions. DXE drivers must use dependency expressions to guarantee that the services and protocol interfaces they
requireareavailablebeforetheyareexecuted. SeethefollowingtopicsfortheDXEArchitecturalProtocolsuponwhich
the services depend:
•UEFI Boot Services Dependencies
•UEFI Runtime Services Dependencies
•DXE Services Dependencies
II-11.2 Classes of DXE Drivers
II-11.2.1 Early DXE Drivers
The first class of DXE drivers are those that execute very early in the DXE phase. The execution order of these DXE
drivers depends on the following:
•The presence and contents of an a priori file
•The evaluation of dependency expressions
TheseearlyDXEdriverswilltypicallycontainbasicservices,processorinitializationcode,chipsetinitializationcode,
andplatforminitializationcode. TheseearlydriverswillalsotypicallyproducetheDXEArchitecturalProtocolsthatare
requiredfortheDXEFoundationtoproducesitsfullcomplementofUEFIBootServicesandUEFIRuntimeServices.
Tosupportthefastestpossibleboottime,asmuchinitializationshouldbedeferredtotheDXEdriversthatfollowUEFI
Driver Model described in the UEFI 2.0 specification.
II-93UEFI Platform Initialization Specification, Release 1.8
The early DXE drivers need to be aware that not all of the UEFI Boot Services, UEFI Runtime Services, and DXE
ServicesmaybeavailablewhentheyexecutebecausenotalloftheDXEArchitecturalProtocolsmaybebeenregistered
yet.
II-11.2.2 DXE Drivers that Follow the UEFI Driver Model
The second class of DXE drivers are those that follow the UEFI Driver Model in the UEFI 2.0 specification. These
drivers do not touch any hardware resources when they initialize. Instead, they register a Driver Binding Protocol
interface in the handle database. The set of Driver Binding Protocols are used by the Boot Device Selection (BDS)
phase to connect the drivers to the devices that are required to establish consoles and provide access to boot devices.
The DXE drivers that follow the UEFI Driver Model ultimately provide software abstractions for console devices and
boot devices, but only when they are explicitly asked to do so.
TheDXEdriversthatfollowtheUEFIDriverModeldonotneedtobeconcernedwithdependencyexpressions. These
drivers simply register the Driver Binding Protocol in the handle database when they are executed, and this operation
canbeperformedwithouttheuseofanyDXEArchitecturalProtocols. DXEdriverswithemptydependencyexpressions
will not be dispatched by the DXE Dispatcher until all of the DXE Architectural Protocols have been installed.
II-11.2.3 Additional Classifications
DXE drivers can also be classified as the following:
•Boot service drivers
•Runtime drivers
Boot service drivers provide services that are available until the ExitBootServices() function is called. When
ExitBootServices() is called, all the memory used by boot service drivers is released for use by an operating
system.
Runtimedriversprovideservicesthatareavailablebeforeandafter ExitBootServices() iscalled,includingthetime
that an operating system is running. All of the services in the UEFI Runtime Services Table are produced by runtime
drivers.
The DXE Foundation is considered a boot service component, so the DXE Foundation is also released when
ExitBootServices() is called. As a result, runtime drivers may not use any of the UEFI Boot Services, DXE
Services, or services produced by boot service drivers after ExitBootServices() is called.
II-11.2. Classes of DXE Drivers II-94CHAPTER
TWELVE
DXE ARCHITECTURAL PROTOCOLS
II-12.1 Introduction
TheDXEFoundationisabstractedfromtheplatformhardwarethroughasetofarchitecturalprotocols. Theseprotocols
functionjustlikeotherprotocolsineveryway. Theonlydifferenceisthatthesearchitecturalprotocolsaretheprotocols
that the DXE Foundation itself consumes to produce the UEFI Boot Services, UEFI Runtime Services, and DXE
Services. DXE drivers that are loaded from firmware volumes produce the DXE Architectural Protocols. This means
that the DXE Foundation must have enough services to load and start DXE drivers before even a single DXE driver is
executed.
The DXE Foundation is passed a HOB list that must contain a description of some amount of system memory and at
leastonefirmwarevolume. ThesystemmemorydescriptorsintheHOBlistareusedtoinitializetheUEFIservicesthat
require only memory to function correctly. The system is also guaranteed to be running on only one processor in flat
physicalmodewithinterruptsdisabled. ThefirmwarevolumeispassedtotheDXEDispatcher,andtheDXEDispatcher
mustcontainaread-onlyfirmwarefilesystemdrivertosearchfortheapriorifileandanyDXEdriversinthefirmware
volumes. When a driver is discovered that needs to be loaded and executed, the DXE Dispatcher will use a PE/COFF
loadertoloadandinvoketheDXEdriver. TheearlyDXEdriverswillproducetheDXEArchitecturalProtocols,sothe
DXE Foundation can produce the full complement of UEFI Boot Services and UEFI Runtime Services.
The following figure shows the HOB list being passed to the DXE Foundation.
The DXE Foundation consumes the services of the DXE Architectural Protocols and produces the following:
•UEFI System Table
•DXE Services Table
TheUEFIBootServicesTableandDXEServicesTableareallocatedfromUEFIbootservicesmemory,whichmeans
thattheUEFIBootServicesTableandDXEServicesTablearefreedwhentheOSruntimephaseisentered. TheUEFI
System Table and UEFI Runtime Services Table are allocated from UEFI runtime services memory, and they persist
into the OS runtime phase.
When executing upon an UEFI-compliant system, UEFI drivers, applications, and UEFI-aware operating systems can
discerniftheplatformisbuiltupontheFoundationbysearchingfortheDXEServicesTableGUIDintheUEFISystem
configuration table. The DXE Architectural Protocols shown on the left of the figure are used to produce the UEFI
Boot Services and DXE Services.
The DXE Foundation and these protocols will be freed when the system transitions to the OS runtime phase. The
DXE Architectural Protocols shown on the right are used to produce the UEFI Runtime Services. These services will
persist in the OS runtime phase. The Runtime Architectural Protocol in the middle is unique. This protocol provides

theservicesthatarerequiredtotransitiontheruntimeservicesfromphysicalmodetovirtualmodeunderthedirection
II-95UEFI Platform Initialization Specification, Release 1.8
Fig. 12.1: DXE Architectural Protocols
of an OS. Once this transition is complete, the services of the Runtime Architectural Protocol can no longer be used.
The following topics describe all of the DXE Architectural Protocols in detail.
II-12.2 Boot Device Selection (BDS) Architectural Protocol
II-12.2.1 EFI_BDS_ARCH_PROTOCOL
Summary
Transfers control from the DXE phase to an operating system or system utility. This protocol must be produced by a
boot service or runtime DXE driver and may only be consumed by the DXE Foundation.
GUID
#define EFI_BDS_ARCH_PROTOCOL_GUID \
{0x665E3FF6,0x46CC,0x11d4,
0x9A,0x38,0x00,0x90,0x27,0x3F,0xC1,0x4D}
EFI_BDS_ENTRY Entry;
} EFI_BDS_ARCH_PROTOCOL;
Entry
The entry point to BDS. See the Entry() function description. This call does not take any parameters, and the
return value can be ignored. If it returns, then the dispatcher must be invoked again, if it never returns, then an
operating system or a system utility have been invoked.
II-12.2. Boot Device Selection (BDS) Architectural Protocol II-96UEFI Platform Initialization Specification, Release 1.8
TheEFI_BDS_ARCH_PROTOCOL transferscontrolfromDXEtoanoperatingsystemorasystemutility. Iftherearenot
enoughdriversinitializedwhenthisprotocolisusedtoaccesstherequiredbootdevice(s),thenthisprotocolshouldadd
drivers to the dispatch queue and return control back to the dispatcher. Once the required boot devices are available,
then the boot device can be used to load and invoke an OS or a system utility.
II-12.2.2 EFI_BDS_ARCH_PROTOCOL.Entry()
Summary
Performs Boot Device Selection (BDS) and transfers control from the DXE Foundation to the selected boot device.
The implementation of the boot policy must follow the rules outlined in the Boot Manager chapter of the UEFI 2.0
specification. Thisbootpolicyallowsforflexibility,sotheplatformvendorwilltypicallycustomizetheimplementation
of this service.
Prototype
typedef
VOID
(EFIAPI *EFI_BDS_ENTRY) (
IN CONST EFI_BDS_ARCH_PROTOCOL *This
);
This
TheEFI_BDS_ARCH_PROTOCOL instance.
Thisfunctionusespolicydatafromtheplatformtodeterminewhatoperatingsystemorsystemutilityshouldbeloaded
andinvoked. Thisfunctioncallalsooptionallyusestheuser’sinputtodeterminetheoperatingsystemorsystemutilityto
beloadedandinvoked. WhentheDXEFoundationhasdispatchedallthedriversonthedispatchqueue,thisfunctionis
called. Thisfunctionwillattempttoconnectthebootdevicesrequiredtoloadandinvoketheselectedoperatingsystem
orsystemutility. Duringthisprocess,additionalfirmwarevolumesmaybediscoveredthatmaycontainadditionDXE
drivers that can be dispatched by the DXE Foundation. If a boot device cannot be fully connected, this function calls
theDXEService Dispatch() toallowtheDXEdriversfromanynewlydiscoveredfirmwarevolumestobedispatched.
Thenthebootdeviceconnectioncanbeattemptedagain. Ifthesamebootdeviceconnectionoperationfailstwiceina
row, then that boot device has failed, and should be skipped. This function should never return.
II-12.3 CPU Architectural Protocol
II-12.3.1 EFI_CPU_ARCH_PROTOCOL
Summary
Abstracts the processor services that are required to implement some of the DXE services. This protocol must be
produced by a boot service or runtime DXE driver and may only be consumed by the DXE Foundation and DXE
drivers that produce architectural protocols.
GUID
II-12.3. CPU Architectural Protocol II-97UEFI Platform Initialization Specification, Release 1.8
#define EFI_CPU_ARCH_PROTOCOL_GUID \
{0x26baccb1,0x6f42,0x11d4,0xbc,\
0xe7,0x0,0x80,0xc7,0x3c,0x88,0x81}
typedef struct _EFI_CPU_ARCH_PROTOCOL {
EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;
EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;
EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;
EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;
EFI_CPU_INIT Init;
EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;
EFI_CPU_GET_TIMER_VALUE GetTimerValue;
EFI_CPU_SET_ATTRIBUTES SetMemoryAttributes;
UINT32 NumberOfTimers;
UINT32 DmaBufferAlignment;
} EFI_CPU_ARCH_PROTOCOL;
FlushDataCache
Flushesarangeoftheprocessor’sdatacache. Seethe FlushDataCache() functiondescription. Iftheprocessor
doesnotcontainadatacache,orthedatacacheisfullycoherent,thenthisfunctioncanjustreturn EFI_SUCCESS .
Iftheprocessordoesnotsupportflushingarangeofaddressesfromthedatacache,thentheentiredatacachemust
be flushed. This function is used by the root bridge I/O abstractions to flush data caches for DMA operations.
EnableInterrupt
Enablesinterruptprocessingbytheprocessor. Seethe EnableInterrupt() functiondescription. Thisfunction
is used by the Boot Service RaiseTPL() andRestoreTPL() .
DisableInterrupt
Disablesinterruptprocessingbytheprocessor. Seethe DisableInterrupt() functiondescription. Thisfunc-
tion is used by the Boot Service RaiseTPL() andRestoreTPL() .
GetInterruptState
Retrieves the processor’s current interrupt state. See the GetInterruptState() function description.
Init
Generates an INIT on the processor. See the Init()function description. This function may be used by the
EFI_RESET Protocoldependinguponaspecifiedbootpath. Ifaprocessorcannotprogrammaticallygeneratean
INIT without help from external hardware, then this function returns EFI_UNSUPPORTED .
RegisterInterruptHandler
Associates an interrupt service routine with one of the processor’s interrupt vectors. See the
RegisterInterruptHandler() function description. This function is typically used by the
EFI_TIMER_ARCH_PROTOCOL to hook the timer interrupt in a system. It can also be used by the debug-
ger to hook exception vectors.
GetTimerValue
Returns the value of one of the processor’s internal timers. See the GetTimerValue() function description.
SetMemoryAttributes
Change a memory region to support specified memory attributes. See the SetMemoryAttributes() function
NumberOfTimers
The number of timers that are available in a processor. The value in this field is a constant that must not be
II-12.3. CPU Architectural Protocol II-98UEFI Platform Initialization Specification, Release 1.8
modified after the CPU Architectural Protocol is installed. All consumers must treat this as a read-only field.
DmaBufferAlignment
The size, in bytes, of the alignment required for DMA buffer allocations. This is typically the size of the largest
data cache line in the platform. This value can be determined by looking at the data cache line sizes of all the
cachespresentintheplatform,andreturningthelargest. ThisisusedbytherootbridgeI/Oabstractionprotocols
toguaranteethatnotwoDMAbufferseversharethesamecacheline. Thevalueinthisfieldisaconstantthatmust
not be modified after the CPU Architectural Protocol is installed. All consumers must treat this as a read-only
field.
TheEFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE Foundation. This in-
cludes flushing caches, enabling and disabling interrupts, hooking interrupt vectors and exception vectors, reading
internal processor timers, resetting the processor, and determining the processor frequency.
The GCD memory space map is initialized by the DXE Foundation based on the contents of the HOB list. The HOB
list contains the capabilities of the different memory regions, but it does not contain their current attributes. The
DXE driver that produces the EFI_CPU_ARCH_PROTOCOL is responsible for maintaining the current attributes of the
memoryregionsvisibletotheprocessor. ThismeansthattheDXEdriverthatproducesthe EFI_CPU_ARCH_PROTOCOL
must seed the GCD memory space map with the initial state of the attributes for all the memory regions visible to the
processor. TheDXEService SetMemorySpaceAttributes() allowstheattributesofamemoryrangetobemodified.
TheSetMemorySpaceAttributes() DXE Service is implemented using the SetMemoryAttributes() service of
theEFI_CPU_ARCH_PROTOCOL .
To initialize the state of the attributes in the GCD memory space map, the DXE driver that produces the
EFI_CPU_ARCH_PROTOCOL must call the DXE Service SetMemorySpaceAttributes() for all the different mem-
ory regions visible to the processor passing in the current attributes. If the CPU does not support certain memory
regionattributesintheUEFISpecification,thentheseshouldalwaysbereportedasdisabledornotpresent. IftheCPU
supportsadditionalmemoryregionattributes,thenthereportedattributesshouldbethosewhichmostcloselymatchbut
not exceed those described in the specification. This, in turn, will call back to the SetMemoryAttributes() service
oftheEFI_CPU_ARCH_PROTOCOL ,andallofthesecallsmustreturn EFI_SUCCESS ,sincetheDXEFoundationisonly
requestingthattheattributesofthememoryregionbesettotheircurrentsettings. Thiswillforcethecurrentattributes
intheGCDmemoryspacemaptobesettothesecurrentsettings. Afterthisinitializationiscomplete,thenextcalltothe

DXEService GetMemorySpaceMap() willcorrectlyshowthecurrentattributesofallthememoryregions. Inaddition,
anyfuturecallstotheDXEService SetMemorySpaceAttributes() willinturncallthe EFI_CPU_ARCH_PROTOCOL
to see if those attributes can be modified, and if they can, the GCD memory space map will be updated accordingly.
II-12.3.2 EFI_CPU_ARCH_PROTOCOL.FlushDataCache()
Summary
Flushes a range of the processor’s data cache. If the processor does not contain a data cache, or the data cache is
fully coherent, then this function can just return EFI_SUCCESS . If the processor does not support flushing a range of
addresses from the data cache, then the entire data cache must be flushed. This function is used by the root bridge I/O
abstractions to flush caches for DMA operations.
Prototype
typedef
(EFIAPI *EFI_CPU_FLUSH_DATA_CACHE) (
IN CONST EFI_CPU_ARCH_PROTOCOL *This,
II-12.3. CPU Architectural Protocol II-99UEFI Platform Initialization Specification, Release 1.8
IN EFI_CPU_FLUSH_TYPE FlushType
);
This
TheEFI_CPU_ARCH_PROTOCOL instance.
Start
The beginning physical address to flush from the processor’s data cache.
Length
The number of bytes to flush from the processor’s data cache. This function may flush more bytes than Length
specifies depending upon the granularity of the flush operation that the processor supports.
FlushType
Specifiesthetypeofflushoperationtoperform. Type EFI_CPU_FLUSH_TYPE isdefinedin“RelatedDefinitions”
below.
Thisfunctionflushestherangeofaddressesfrom StarttoStart+Length fromtheprocessor’sdatacache. If Startis
notalignedtoacachelineboundary,thenthebytesbefore Starttotheprecedingcachelineboundaryarealsoflushed.
IfStart+Length is not aligned to a cache line boundary, then the bytes past Start+Length to the end of the next
cachelineboundaryarealsoflushed. Iftheaddressrangeisflushed,then EFI_SUCCESS isreturned. Iftheaddressrange
cannot be flushed, then EFI_DEVICE_ERROR is returned. If the processor does not support the flush type specified by
FlushType , thenEFI_UNSUPPORTED is returned. The FlushType ofEfiCpuFlushTypeWriteBackInvalidate
must be supported. If the data cache is fully coherent with all DMA operations, then this function can just return
EFI_SUCCESS . If the processor does not support flushing a range of the data cache, then the entire data cache can be
flushed.
EfiCpuFlushTypeWriteBackInvalidate,
EfiCpuFlushTypeWriteBack,
EfiCpuFlushTypeInvalidate,
EfiCpuMaxFlushType
} EFI_CPU_FLUSH_TYPE;
Table 12.1: Status Codes Returned
EFI_SUCCESS Theaddressrangefrom StarttoStart+Length wasflushedfrom
the processor’s data cache.
EFI_UNSUPPORTED The processor does not support the cache flush type specified by
FlushType .
EFI_DEVICE_ERROR The address range from StarttoStart+Length could not be
flushed from the processor s data cache.
II-12.3. CPU Architectural Protocol II-100UEFI Platform Initialization Specification, Release 1.8
II-12.3.3 EFI_CPU_ARCH_PROTOCOL.EnableInterrupt()
Summary
Enablesinterruptprocessingbytheprocessor. ThisfunctionisusedtoimplementtheBootServices RaiseTPL() and
RestoreTPL() .
Prototype
typedef
(EFIAPI *EFI_CPU_ENABLE_INTERRUPT) (
IN CONST EFI_CPU_ARCH_PROTOCOL *This
);
This
This function enables interrupt processing by the processor. If interrupts are enabled, then EFI_SUCCESS is returned.
Otherwise, EFI_DEVICE_ERROR is returned.
Table 12.2: Status Codes Returned
EFI_SUCCESS Interrupts are enabled on the processor.
EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
II-12.3.4 EFI_CPU_ARCH_PROTOCOL.DisableInterrupt()
Summary
Disablesinterruptprocessingbytheprocessor. ThisfunctionisusedtoimplementtheBootServices RaiseTPL() and
Prototype
typedef
(EFIAPI *EFI_CPU_DISABLE_INTERRUPT) (
);
This
Thisfunctiondisablesinterruptprocessingbytheprocessor. Ifinterruptsaredisabled,then EFI_SUCCESS isreturned.
II-12.3. CPU Architectural Protocol II-101UEFI Platform Initialization Specification, Release 1.8
Table 12.3: Status Codes Returned
EFI_SUCCESS Interrupts are disabled on the processor.
EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
II-12.3.5 EFI_CPU_ARCH_PROTOCOL.GetInterruptState()
Summary
Retrieves the processor’s current interrupt state.
Prototype
typedef
(EFIAPI *EFI_CPU_GET_INTERRUPT_STATE) (
OUT BOOLEAN *State
);
This
State
Apointertotheprocessor’scurrentinterruptstate. Setto TRUEifinterruptsareenabledand FALSEifinterrupts
are disabled.
This function retrieves the processor’s current interrupt state a returns it in State. If interrupts are currently en-
abled, then TRUEis returned. If interrupts are currently disabled, then FALSEis returned. If StateisNULL, then
EFI_INVALID_PARAMETER is returned. Otherwise, EFI_SUCCESS is returned.
Table 12.4: Status Codes Returned
EFI_SUCCESS The processor’s current interrupt state was returned in State.
EFI_INVALID_PARAMETER StateisNULL.
II-12.3.6 EFI_CPU_ARCH_PROTOCOL.Init()
Summary
Generates an INIT on the processor.
Prototype
typedef
(EFIAPI *EFI_CPU_INIT) (
IN EFI_CPU_INIT_TYPE InitType
);
II-12.3. CPU Architectural Protocol II-102UEFI Platform Initialization Specification, Release 1.8
This
InitType
The type of processor INIT to perform. Type EFI_CPU_INIT_TYPE is defined in “Related Definitions” below.
This function generates an INIT on the processor. If this function succeeds, then the processor will be reset, and
control will not be returned to the caller. If InitType is not supported by this processor, or the processor cannot
programmatically generate an INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an
error occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
EfiCpuInit,
EfiCpuMaxInitType
} EFI_CPU_INIT_TYPE;
Table 12.5: Status Codes Returned
EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
EFI_UNSUPPORTED TheprocessorINIToperationspecifiedby InitType isnotsupportedbythisprocessor.
EFI_DEVICE_ERROR The processor INIT failed.
II-12.3.7 EFI_CPU_ARCH_PROTOCOL.RegisterInterruptHandler()
Summary
Registers a function to be called from the processor interrupt handler.
Prototype
typedef
(EFIAPI *EFI_CPU_REGISTER_INTERRUPT_HANDLER) (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
This
InterruptType
Defineswhichinterruptorexceptiontohook. Type EFI_EXCEPTION_TYPE andthevalidvaluesforthisparameter
are defined in EFI_DEBUG_SUPPORT_PROTOCOL of the UEFI 2.0 specification.
InterruptHandler
Apointertoafunctionoftype EFI_CPU_INTERRUPT_HANDLER thatiscalledwhenaprocessorinterruptoccurs.
Ifthisparameteris NULL,thenthehandlerwillbeuninstalled. Type EFI_CPU_INTERRUPT_HANDLER isdefined
II-12.3. CPU Architectural Protocol II-103UEFI Platform Initialization Specification, Release 1.8
TheRegisterInterruptHandler() function registers and enables the handler specified by InterruptHandler
for a processor interrupt or exception type specified by InterruptType . IfInterruptHandler isNULL, then the
handlerfortheprocessorinterruptorexceptiontypespecifiedby InterruptType isuninstalled. Theinstalledhandler
is called once for each processor interrupt or exception.
If the interrupt handler is successfully installed or uninstalled, then EFI_SUCCESS is returned.
IfInterruptHandler is notNULL, and a handler for InterruptType has already been installed, then
IfInterruptHandler isNULL, and a handler for InterruptType has not been installed, then
IfInterruptType is not supported, then EFI_UNSUPPORTED is returned.
TheEFI_CPU_ARCH_PROTOCOL implementation of this function must handle saving and restoring system context to
thesystemcontextrecordaroundcallstotheinterrupthandler. Itmustalsoperformthenecessarystepstoreturntothe
context that was interrupted by the interrupt. No chaining of interrupt handlers is allowed.
typedef
VOID
(*EFI_CPU_INTERRUPT_HANDLER) (
IN EFI_SYSTEM_CONTEXT SystemContext
);
Defines the type of interrupt or exception that occurred on the processor. This parameter is processor ar-

typedef
VOID
);
chitecture specific. The type EFI_EXCEPTION_TYPE and the valid values for this parameter are defined in
EFI_DEBUG_SUPPORT_PROTOCOL of the UEFI 2.0 specification.
SystemContext
A pointer to the processor context when the interrupt occurred on the processor. Type EFI_SYSTEM_CONTEXT
is defined in the EFI_DEBUG_SUPPORT_PROTOCOL of the UEFI 2.0 specification.
Table 12.6: Status Codes Returned
EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED InterruptHandler isnotNULLandahandlerfor InterruptType waspreviously
EFI_INVALID_PARAMETER InterruptHandler isNULLandahandlerfor InterruptType wasnotpreviously
EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
II-12.3. CPU Architectural Protocol II-104UEFI Platform Initialization Specification, Release 1.8
II-12.3.8 EFI_CPU_ARCH_PROTOCOL.GetTimerValue()
Summary
Returns a timer value from one of the processor’s internal timers.
Prototype
typedef
(EFIAPI *EFI_CPU_GET_TIMER_VALUE) (
IN UINT32 TimerIndex,
OUT UINT64 *TimerValue,
OUT UINT64 *TimerPeriod OPTIONAL
);
This
TimerIndex
Specifies which processor timer is to be returned in TimerValue . This parameter must be between 0 and
NumberOfTimers-1 .
TimerValue
Pointer to the returned timer value.
TimerPeriod
A pointer to the amount of time that passes in femtoseconds (10^15) for each increment of TimerValue . If
TimerValue does not increment at a predictable rate, then 0 is returned. The amount of time that has passed
between two calls to GetTimerValue() can be calculated with the formula ( TimerValue2 - TimerValue1
)*TimerPeriod . This parameter is optional and may be NULL.
This function reads the processor timer specified by TimerIndex and returns it in TimerValue . IfTimerValue
isNULL, thenEFI_INVALID_PARAMETER is returned. If TimerPeriod is notNULL, then the amount of time that
passesinfemtoseconds(10^15)foreachincrementif TimerValue isreturnedin TimerPeriod . Ifthetimerdoesnot
run at a predictable rate, then a TimerPeriod of 0 is returned. If TimerIndex does not specify a valid timer in this
processor,then EFI_INVALID_PARAMETER isreturned. Thevalidrangefor TimerIndex is0..``NumberOfTimers ``-1.
Iftheprocessordoesnotcontainanyreadabletimers,thenthisfunctionreturns EFI_UNSUPPORTED .Ifanerroroccurs
attempting to read one of the processor’s timers, then EFI_DEVICE_ERROR is returned.
Table 12.7: Status Codes Returned
EFI_SUCCESS Theprocessortimervaluespecifiedby TimerIndex wasreturnedin
TimerValue .
EFI_INVALID_PARAMETER TimerValue isNULL.
EFI_INVALID_PARAMETER TimerIndex is not valid.
EFI_UNSUPPORTED The processor does not have any readable timers.
EFI_DEVICE_ERROR An error occurred attempting to read one of the processor s timers.
II-12.3. CPU Architectural Protocol II-105UEFI Platform Initialization Specification, Release 1.8
II-12.3.9 EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes()
Summary
Change a memory region to support specified memory attributes.
Prototype
typedef
(EFIAPI *EFI_CPU_SET_MEMORY_ATTRIBUTES) (
);
This
Length
Abitmaskthatspecifiesthememoryregionattributes. SeetheUEFIBootService GetMemoryMap() fortheset
of legal attribute bits.
This function changes the attributes for the memory region specified by BaseAddress andLengthto support those
specifiedby Attributes . Ifthememoryregionattributesarechangedsothattheydonotconflictwiththosespecified
byAttributes , thenEFI_SUCCESS is returned.
Thisfunctionmodifiestheattributesforthememoryregionspecifiedby BaseAddress andLengthfromtheircurrent
attributestotheattributesspecifiedby Attributes . Ifthismodificationofattributessucceeds,then EFI_SUCCESS is
returned.
Length, thenEFI_UNSUPPORTED is returned.
IfAttributes specifies a combination of memory attributes that cannot be set together, then
EFI_INVALID_PARAMETER is returned. For example, if both EFI_MEMORY_UC andEFI_MEMORY_WT are set.
II-12.3. CPU Architectural Protocol II-106UEFI Platform Initialization Specification, Release 1.8
Table 12.8: Status Codes Returned
EFI_SUCCESS The attributes were set for the memory region.
EFI_INVALID_PARAMETER Lengthis zero.
EFI_INVALID_PARAMETER Attributes specifiedanillegalcombinationofattributesthatcan-
not be set together.
resource range specified by BaseAddress andLength.
range specified by BaseAddress andLength.
BaseAddress andLengthcannot be modified.
the memory resource range.
II-12.4 Metronome Architectural Protocol
II-12.4.1 EFI_METRONOME_ARCH_PROTOCOL
Summary
Usedtowaitforticksfromaknowntimesourceinaplatform. Thisprotocolmaybeusedtoimplementasimpleversion
oftheStall() BootService. ThisprotocolmustbeproducedbyabootserviceorruntimeDXEdriverandmayonly
be consumed by the DXE Foundation and DXE drivers that produce DXE Architectural Protocols.
GUID
#define EFI_METRONOME_ARCH_PROTOCOL_GUID \
{0x26baccb2,0x6f42,0x11d4,0xbc,\
typedef struct _EFI_METRONOME_ARCH_PROTOCOL {
EFI_METRONOME_WAIT_FOR_TICK WaitForTick;
UINT32 TickPeriod;
} EFI_METRONOME_ARCH_PROTOCOL;
WaitForTick
Waitsforaspecifiednumberofticksfromaknowntimesourceintheplatform. Seethe WaitForTick() function
description. Theactualtimepassedbetweenentryofthisfunctionandthefirsttickisbetween0and TickPeriod
100 ns units. To guarantee that at least TickPeriod time has elapsed, wait for two ticks.
TickPeriod
The period of platform’s known time source in 100 ns units. This value on any platform must not exceed 200
µs. The value in this field is a constant that must not be modified after the Metronome architectural protocol is
installed. All consumers must treat this as a read-only field.
This protocol provides access to a known time source in the platform to the DXE Foundation. The DXE Foundation
uses this known time source to produce DXE Foundation services that require calibrated delays.
II-12.4. Metronome Architectural Protocol II-107UEFI Platform Initialization Specification, Release 1.8
II-12.4.2 EFI_METRONOME_ARCH_PROTOCOL.WaitForTick()
Summary
Waits for a specified number of ticks from a known time source in a platform.
Prototype
typedef
(EFIAPI *EFI_METRONOME_WAIT_FOR_TICK) (
IN CONST EFI_METRONOME_ARCH_PROTOCOL *This,
IN UINT32 TickNumber
);
This
TheEFI_METRONOME_ARCH_PROTOCOL instance.
TickNumber
Number of ticks to wait.
TheWaitForTick() function waits for the number of ticks specified by TickNumber from a known time source in
the platform. If TickNumber of ticks are detected, then EFI_SUCCESS is returned. The actual time passed between
entryofthisfunctionandthefirsttickisbetween0and TickPeriod 100nsunits. Ifyouwanttoguaranteethatatleast
TickPeriod time has elapsed, wait for two ticks. This function waits for a hardware event to determine when a tick
occurs. Itispossibleforinterruptprocessing,orexceptionprocessingtointerrupttheexecutionofthe WaitForTick()
function. Depending on the hardware source for the ticks, it is possible for a tick to be missed. This function cannot
guaranteethattickswillnotbemissed. Ifatimeoutoccurswaitingforthespecifiednumberofticks,then EFI_TIMEOUT
Table 12.9: Status Codes Returned
EFI_SUCCESS The wait for the number of ticks specified by TickNumber suc-
ceeded.
EFI_TIMEOUT A timeout occurred waiting for the specified number of ticks.
II-12.5 Monotonic Counter Architectural Protocol
II-12.5.1 EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL
Summary

ceeded.
Summary
Providestheservicesrequiredtoaccessthesystem’smonotoniccounter. Thisprotocolmustbeproducedbyaruntime
DXE driver and may only be consumed by the DXE Foundation and DXE drivers that produce DXE Architectural
Protocols.
GUID
#define EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL_GUID \
{0x1da97072,0xbddc,0x4b30,0x99,\
0xf1,0x72,0xa0,0xb5,0x6f,0xff,0x2a}
II-12.5. Monotonic Counter Architectural Protocol II-108UEFI Platform Initialization Specification, Release 1.8
The DXE driver that produces this protocol must be a runtime driver. This driver is responsible for initializing the
GetNextHighMonotonicCount() field of the UEFI Runtime Services Table and the GetNextMonotonicCount()
field of the UEFI Boot Services Table. See :ref: Services—Boot-Services for details on these services. After the field
of the UEFI Runtime Services Table and the field of the UEFI Boot Services Table have been initialized, the driver
must install the EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL_GUID on a new handle with a NULLinterface pointer.
The installation of this protocol informs the DXE Foundation that the monotonic counter services are now available
andthattheDXEFoundationmustupdatethe32-bitCRCoftheUEFIRuntimeServicesTableandthe32-bitCRCof
the UEFI Boot Services Table.
II-12.6 Real Time Clock Architectural Protocol
II-12.6.1 EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL
Summary
Provides the services required to access a system’s real time clock hardware. This protocol must be produced by a
runtime DXE driver and may only be consumed by the DXE Foundation.
GUID
#define EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID \
{0x27CFAC87,0x46CC,0x11d4,0x9A,\
0x38,0x00,0x90,0x27,0x3F,0xC1,0x4D}
GetTime() ,SetTime(), GetWakeupTime() , andSetWakeupTime() fields of the UEFI Runtime Services Table.
SeeRuntime Capabilities for details on these services. After the four fields of the UEFI Runtime Services Table have
been initialized, the driver must install the EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID on a new handle with a
NULLinterface pointer. The installation of this protocol informs the DXE Foundation that the real time clock-related
services are now available and that the DXE Foundation must update the 32-bit CRC of the UEFI Runtime Services
Table.
II-12.7 Reset Architectural Protocol
II-12.7.1 EFI_RESET_ARCH_PROTOCOL
Summary
Provides the service required to reset a platform. This protocol must be produced by a runtime DXE driver and may
only be consumed by the DXE Foundation.
GUID
#define EFI_RESET_ARCH_PROTOCOL_GUID \
{0x27CFAC88,0x46CC,0x11d4,0x9A,\
II-12.6. Real Time Clock Architectural Protocol II-109UEFI Platform Initialization Specification, Release 1.8
The DXE driver that produces this protocol must be a runtime driver. This driver is responsible for initializ-
ing theResetSystem() field of the UEFI Runtime Services Table. See Runtime Capabilities for details on this
service. After this field of the UEFI Runtime Services Table has been initialized, the driver must install the
EFI_RESET_ARCH_PROTOCOL_GUID on a new handle with a NULLinterface pointer. The installation of this proto-
col informs the DXE Foundation that the reset system service is now available and that the DXE Foundation must
update the 32-bit CRC of the UEFI Runtime Services Table.
II-12.8 Runtime Architectural Protocol
The following topics provide a detailed description of the EFI_RUNTIME_ARCH_PROTOCOL . The DXE Foundation
contains no runtime code, so all runtime code is contained in DXE Architectural Protocols. This is due to the fact
thatruntimecodemustbecallableinphysicalorvirtualmode. TheRuntimeArchitecturalProtocolcontainstheUEFI
runtime services that are callable only in physical mode. The Runtime Architectural Protocol can be thought of as the
runtime portion of the DXE Foundation.
The Runtime Architectural Protocol contains support for transition of runtime drivers from physical mode calling to
virtual mode calling.
II-12.8.1 EFI_RUNTIME_ARCH_PROTOCOL
Summary
Allows the runtime functionality of the DXE Foundation to be contained in a separate driver. It also provides hooks
for the DXE Foundation to export information that is needed at runtime. As such, this protocol allows services to the
DXEFoundationtomanageruntimedriversandevents. Thisprotocolalsoimpliesthattheruntimeservicesrequiredto
transitiontovirtualmode, SetVirtualAddressMap() andConvertPointer() ,havebeenregisteredintotheUEFI
Runtime Table in the UEFI System Table. This protocol must be produced by a runtime DXE driver and may only be
consumed by the DXE Foundation.
GUID
#define EFI_RUNTIME_ARCH_PROTOCOL_GUID \
{0xb7dfb4e1,0x52f,0x449f,0x87,\
0xbe,0x98,0x18,0xfc,0x91,0xb7,0x33}
typedef struct _EFI_RUNTIME_ARCH_PROTOCOL {
EFI_LIST_ENTRY ImageHead;
EFI_LIST_ENTRY EventHead;
UINTN MemoryDescriptorSize;
UINT32 MemoryDesciptorVersion;
UINTN MemoryMapSize;
EFI_MEMORY_DESCRIPTOR *MemoryMapPhysical;
EFI_MEMORY_DESCRIPTOR *MemoryMapVirtual;
BOOLEAN VirtualMode;
BOOLEAN AtRuntime;
} EFI_RUNTIME_ARCH_PROTOCOL;
ImageHead
Alistoftype EFI_RUNTIME_IMAGE_ENTRY wheretheDXEFoundationinsertsitemsintothelistandtheRuntime
AP consumes the data to implement the SetVirtualAddressMap() call.
II-12.8. Runtime Architectural Protocol II-110UEFI Platform Initialization Specification, Release 1.8
EventHead
Alistoftype EFI_RUNTIME_EVENT_ENTRY wheretheDXEFoundationinsertsitemsintothelistandtheRuntime
MemoryDescriptorSize
Sizeofamemorydescriptorthatisreturnedby GetMemoryMap() . ThisvalueisupdatedbytheDXEFoundation.
MemoryDescriptorVersion
Versionofamemorydescriptorthatisreturnby GetMemoryMap() . ThisvalueisupdatedbytheDXEFounda-
tion.
MemoryMapSize
Size of the memory map in bytes contained in MemoryMapPhysical andMemoryMapVirtual . This value is
updated by the DXE Foundation when memory for MemoryMapPhysical gets allocated.
MemoryMapPhysical
Pointertoaruntimebufferthatcontainsacopyofthememorymapreturnedvia GetMemoryMap() . Thememory
must be allocated by the DXE Foundation so that it is accounted for in the memory map.
MemoryMapVirtual
Pointer to MemoryMapPhysical that is updated to virtual mode after SetVirtualAddressMap() . The DXE
Foundationupdatesthisvaluewhenitupdates MemoryMapPhysical withthesamephysicaladdress. TheRun-
time AP is responsible for converting MemoryMapVirtual to a virtual pointer.
VirtualMode
Booleanthatis TRUEifSetVirtualAddressMap() hasbeencalled. ThisfieldissetbytheRuntimeAP.When
VirtualMode isTRUEMemoryMapVirtual pointer contains the virtual address of the MemoryMapPhysical .
AtRuntime
Boolean that is TRUEifExitBootServices() has been called. This field is set by the Runtime AP.
// EFI_LIST_ENTRY
struct _EFI_LIST_ENTRY {
struct _EFI_LIST_ENTRY *ForwardLink;
struct _EFI_LIST_ENTRY *BackLink;
} EFI_LIST_ENTRY;
ForwardLink
A pointer next node in the doubly linked list.
BackLink
A pointer previous node in the doubly linked list.
// EFI_RUNTIME_IMAGE_ENTRY
VOID *RelocationData;
EFI_LIST_ENTRY Link;
} EFI_RUNTIME_IMAGE_ENTRY;
II-12.8. Runtime Architectural Protocol II-111UEFI Platform Initialization Specification, Release 1.8
ImageBase
Startofimagethathasbeenloadedinmemory. ItisapointertoeithertheDOSheaderorPEheaderoftheimage.
TypeEFI_PHYSICAL_ADDRESS is defined in the AllocatePages() UEFI 2.0 specification.
ImageSize
Size in bytes of the image represented by ImageBase .
RelocationData
Information about the fix-ups that were performed on ImageBase when it was loaded into memory. This in-
formation is needed when the virtual mode fix-ups are reapplied so that data that has been programmatically
updated will not be fixed up. If code updates a global variable the code is responsible for fixing up the variable
for virtual mode.
Handle
TheImageHandle passedinto ImageBase whenitwasloaded. See EFI_IMAGE_ENTRY_POINT forthedefinition
ofImageHandle .
Link
Entry for this node in the EFI_RUNTIME_ARCHITECTURE_PROTOCOL.ImageHead list.
// EFI_RUNTIME_EVENT_ENTRY
EFI_TPL NotifyTpl;
EFI_EVENT_NOTIFY NotifyFunction;
VOID *NotifyContext;
EFI_EVENT *Event;
} EFI_RUNTIME_EVENT_ENTRY;
Note: the (EFI_EVENT*) type of EFI_RUNTIME_EVENT_ENTRY.Event is an historical mistake in the Platform
Initializationspecification. ImplementationsareexpectedtoassignEFI_EVENTvalues(asreturnedbyCreateEvent()),

Handle
Link
cast to (EFI_EVENT*), to the field, and to cast values read from the field to EFI_EVENT.
Type
The same as Typepassed into CreateEvent() .
NotifyTpl
The same as NotifyTpl passed into CreateEvent() . TypeEFI_TPL is defined in RaiseTPL() in the UEFI
NotifyFunction
The same as NotifyFunction passed into CreateEvent() . TypeEFI_EVENT_NOTIFY is defined in the
CreateEvent() function description.
NotifyContext
The same as NotifyContext passed into CreateEvent() .
Event
TheEFI_EVENT returnedby CreateEvent() . Eventmustbeinruntimememory. Type EFI_EVENT isdefined
in theCreateEvent() function description.
Link
Entry for this node in the EFI_RUNTIME_ARCHITECTURE_PROTOCOL.EventHead list.
II-12.8. Runtime Architectural Protocol II-112UEFI Platform Initialization Specification, Release 1.8
ing theSetVirtualAddressMap() andConvertPointer() fields of the UEFI Runtime Services Table and the
CalculateCrc32() field of the UEFI Boot Services Table. See Runtime Capabilities and Services - Boot Services.
for details on these services. After the two fields of the UEFI Runtime Services Table and the one field of the UEFI
BootServicesTablehavebeeninitialized,thedrivermustinstallthe EFI_RUNTIME_ARCH_PROTOCOL_GUID onanew
handle with an EFI_RUNTIME_ARCH_PROTOCOL interface pointer. The installation of this protocol informs the DXE
Foundation that the virtual memory services and the 32-bit CRC services are now available, and the DXE Foundation
mustupdatethe32-bitCRCoftheUEFIRuntimeServicesTableandthe32-bitCRCoftheUEFIBootServicesTable.
AllruntimeDXEFoundationservicesareprovidedbythe EFI_RUNTIME_ARCH_PROTOCOL .Thisincludesthesupport
for registering runtime images that must be fixed up again when a transition is made from physical mode to virtual
mode. This protocol also supports all events that are defined to fire at runtime. This protocol also contains a CRC-32
function that will be used by the DXE Foundation as a boot service. The EFI_RUNTIME_ARCH_PROTOCOL needs the
CRC-32functionwhenatransitionismadefromphysicalmodetovirtualmodeandtheUEFISystemTableandUEFI
Runtime Table are fixed up with virtual pointers.
II-12.9 Security Architectural Protocols
TheEFI_SECURITY_ARCH_PROTOCOL andEFI_SECURITY2_ARCH_PROTOCOL abstractpolicyactionsonimageinvo-
cation and other security controls from the DXE core to a security driver.
II-12.9.1 Security Architectural Protocol
II-12.9.1.1 EFI_SECURITY_ARCH_PROTOCOL
Summary
Abstracts security-specific functions from the DXE Foundation for purposes of handling GUIDed section encapsula-
tions. ThisprotocolmustbeproducedbyabootserviceorruntimeDXEdriverandmayonlybeconsumedbytheDXE
Foundation and any other DXE drivers that need to validate the authentication of files.
See also Security2 Architectural Protocol section below.
GUID
#define EFI_SECURITY_ARCH_PROTOCOL_GUID \
{0xA46423E3,0x4617,0x49f1,0xB9,\
0xFF,0xD1,0xBF,0xA9,0x11,0x58,0x39}
typedef struct _EFI_SECURITY_ARCH_PROTOCOL {
EFI_SECURITY_FILE_AUTHENTICATION_STATE
FileAuthenticationState;
} EFI_SECURITY_ARCH_PROTOCOL;
FileAuthenticationState
This service is called upon fault with respect to the authentication of a section of a file. See the
FileAuthenticationState() function description.
II-12.9. Security Architectural Protocols II-113UEFI Platform Initialization Specification, Release 1.8
TheEFI_SECURITY_ARCH_PROTOCOL is used to abstract platform-specific policy from the DXE Foundation. This
includes locking flash upon failure to authenticate, attestation logging, and other exception operations.
The driver that produces the EFI_SECURITY_ARCH_PROTOCOL may also optionally install the
EFI_SECURITY_POLICY_PROTOCOL_GUID onto a new handle with a NULLinterface. The existence of this
GUID in the protocol database means that the GUIDed Section Extraction Protocol should authenticate the contents
of an Authentication Section. The expectation is that the GUIDed Section Extraction protocol will look for the
existence of the EFI_SECURITY_POLICY_PROTOCOL_GUID in the protocol database. If it exists, then the publication
thereof is taken as an injunction to attempt an authentication of any section wrapped in an Authentication Section.
See thePlatform Initialization Specification, Volume 3, for details on the GUIDed Section Extraction Protocol and
Authentication Sections.
Addition GUID Definitions
#define EFI_SECURITY_POLICY_PROTOCOL_GUID \
{0x78E4D245,0xCD4D,0x4a05,0xA2,0xBA,0x47,0x43,0xE8,0x6C,0xFC,0xAB}
II-12.9.1.2 EFI_SECURITY_ARCH_PROTOCOL.FileAuthenticationState()
Summary
The DXE Foundation uses this service to check the authentication status of a file. This allows the system to execute a
platform-specific policy in response the different authentication status values.
Prototype
typedef
(EFIAPI *EFI_SECURITY_FILE_AUTHENTICATION_STATE) (
IN CONST EFI_SECURITY_ARCH_PROTOCOL *This,
IN CONST EFI_DEVICE_PATH_PROTOCOL *File
);
This
TheEFI_SECURITY_ARCH_PROTOCOL instance.
The authentication type returned from the Section Extraction Protocol. See the Platform Initialization
Specification , Volume 3, for details on this type.
File
A pointer to the device path of the file that is being dispatched. This will optionally be used for logging. Type
EFI_DEVICE_PATH_PROTOCOL is defined Chapter 8 of the UEFI 2.0 specification.
TheEFI_SECURITY_ARCH_PROTOCOL (SAP) is used to abstract platform-specific policy from the DXE Foundation
response to an attempt to use a file that returns a given status for the authentication check from the section extraction
protocol.
ThepossibleresponsesinagivenSAPimplementationmayincludelockingflashuponfailuretoauthenticate,attestation
logging for all signed drivers, and other exception operations. The Fileparameter allows for possible logging within
the SAP of the driver.
IfFileisNULL, thenEFI_INVALID_PARAMETER is returned.
II-12.9. Security Architectural Protocols II-114UEFI Platform Initialization Specification, Release 1.8
If the file specified by Filewith an authentication status specified by AuthenticationStatus is safe for the DXE
Foundation to use, then EFI_SUCCESS is returned.
Ifthefilespecifiedby Filewithanauthenticationstatusspecifiedby AuthenticationStatus isnotsafefortheDXE
Foundation to use under any circumstances, then EFI_ACCESS_DENIED is returned.
Foundation to use right now, but it might be possible to use it at a future time, then EFI_SECURITY_VIOLATION is
returned.
Table 12.10: Status Codes Returned
EFI_SUCCESS The file specified by Filedid authenticate, and the platform policy
dictates that the DXE Foundation may use File.
EFI_INVALID_PARAMETER FileisNULL.
EFI_SECURITY_VIOLATION The file specified by Filedid not authenticate, and the platform
policy dictates that Fileshould be placed in the untrusted state.
A file may be promoted from the untrusted to the trusted state at a
future time with a call to the Trust() DXE Service.
EFI_ACCESS_DENIED The file specified by Filedid not authenticate, and the platform
policy dictates that Fileshould not be used for any purpose.
II-12.9.2 Security2 Architectural Protocol
Summary
Abstractssecurity-specificfunctionsfromtheDXEFoundationofUEFIImageVerification,TrustedComputingGroup
(TCG) measured boot, and User Identity policy for image loading and consoles. This protocol must be produced by a
boot service or runtime DXE driver.
This protocol is optional and must be published prior to the EFI_SECURITY_ARCH_PROTOCOL . As a result, the same
driver must publish both of these interfaces.
When both Security and Security2 Architectural Protocols are published, LoadImage must use them in accordance
with the following rules:
•The Security2 protocol must be used on every image being loaded.
•The Security protocol must be used after the Securiy2 protocol and only on images that have been read using
Firmware Volume protocol.
When only Security architectural protocol is published, LoadImage must use it on every image being loaded.
GUID
#define EFI_SECURITY2_ARCH_PROTOCOL_GUID \
{0x94ab2f58, 0x1438, 0x4ef1, 0x91, \
0x52, 0x18, 0x94, 0x1a, 0x3a, 0xe, 0x68}
typedef struct _EFI_SECURITY2_ARCH_PROTOCOL {
EFI_SECURITY2_FILE_AUTHENTICATION FileAuthentication;
} EFI_SECURITY2_ARCH_PROTOCOL;
II-12.9. Security Architectural Protocols II-115UEFI Platform Initialization Specification, Release 1.8
FileAuthentication
This service is called by DXE Foundation from the LoadImage service to verify and/or measure the image and
from theConnectController service to probe whether a specific device path can be connected.
TheEFI_SECURITY2_ARCH_PROTOCOL is used to abstract platform-specific policy from the DXE Foundation. This

GUID
includes measuring the PE/COFF image prior to invoking, comparing the image against a policy (whether a white-
list/black-list of public image verification keys or registered hashes).
II-12.9.2.1 EFI_SECURITY2_ARCH_PROTOCOL.FileAuthentication()
Summary
The DXE Foundation uses this service to measure and/or verify a UEFI image.
Prototype
typedef EFI_STATUS (EFIAPI
*EFI_SECURITY_FILE_AUTHENTICATION_STATE) (
IN CONST EFI_SECURITY2_ARCH_PROTOCOL *This,
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePat ,
IN VOID *FileBuffer,
IN UINTN FileSize,
IN BOOLEAN BootPolicy
);
This
TheEFI_SECURITY2_ARCH_PROTOCOL instance.
A pointer to the device path of the file that is being dispatched or the location that is being connected. This
will optionally be used for logging. Type EFI_DEVICE_PATH_PROTOCOL is defined Chapter 9 of the UEFI
Specification.
FileBuffer
A pointer to the buffer with the UEFI file image
FileSize
The size of the file.
A boot policy that was used to call LoadImage() UEFI service. If FileAuthentication() is invoked not
from theLoadImage() ,BootPolicy must be set to FALSE.
This service abstracts the invocation of Trusted Computing Group (TCG) measured boot, UEFI Secure boot, and
UEFI User Identity infrastructure. For the former two, the DXE Foundation invokes the FileAuthentication()
with aDevicePath and corresponding image in FileBuffer memory. The TCG measurement code will record the
FileBuffer contentsintotheappropriatePCR.Theimageverificationlogicwillconfirmtheintegrityandprovenance
of the image in FileBuffer of lengthFileSize . The origin of the image will be DevicePath in these cases.
IfDevicePath isNULL,theoriginoftheimageisunknown. Implementationofthisservicemustapplytosuchimage
security policy that is applied to the image with the least trusted origin.
IftheFileBuffer isNULL,theinterfacewilldetermineifthe DevicePath canbeconnectedinordertosupportthe
User Identification policy.
II-12.9. Security Architectural Protocols II-116UEFI Platform Initialization Specification, Release 1.8
Table 12.11: Status Codes Returned
EFI_SUCCESS Thefilespecifiedby DevicePath andnonNULL FileBuffer did
authenticate,andtheplatformpolicydictatesthattheDXEFounda-
tion may use the file.
EFI_SUCCESS The device path specified by NULL device path DevicePath and
non NULL FileBuffer did authenticate, and the platform pol-
icy dictates that the DXE Foundation may execute the image in
FileBuffer .
EFI_SUCCESS FileBuffer isNULLandcurrentuserhaspermissiontostartUEFI
device drivers on the device path specified by DevicePath .
EFI_SECURITY_VIOLATION Thefilespecifiedby DevicePath andFileBuffer didnotauthen-
ticate and the platform policy dictates that the file should be placed
intheuntrustedstate. Theimagehasbeenaddedtothefileexecution
table.
EFI_ACCESS_DENIED Thefilespecifiedby FileandFileBuffer didnotauthenticateand
the platform policy dictates that the DXE Foundation many not use
File.
EFI_SECURITY_VIOLATION FileBuffer isNULLandtheuserhasnopermissiontostartUEFI
EFI_SECURITY_VIOLATION FileBuffer is not NULL and the user has no permission to load
drivers from the device path specified by DevicePath . The image
has been added into the list of the deferred images.
II-12.10 Timer Architectural Protocol
II-12.10.1 EFI_TIMER_ARCH_PROTOCOL
Summary
Usedtosetupaperiodictimerinterruptusingaplatformspecifictimer,andaprocessor-specificinterruptvector. This
protocolenablestheuseofthe SetTimer() BootService. Thisprotocolmustbeproducebyabootserviceorruntime
DXEdriverandmayonlybeconsumedbytheDXEFoundationorDXEdriversthatproduceotherDXEArchitectural
GUID
#define EFI_TIMER_ARCH_PROTOCOL_GUID \
{0x26baccb3,0x6f42,0x11d4,0xbc,\
typedef struct _EFI_TIMER_ARCH_PROTOCOL {
EFI_TIMER_REGISTER_HANDLER RegisterHandler;
EFI_TIMER_SET_TIMER_PERIOD SetTimerPeriod;
EFI_TIMER_GET_TIMER_PERIOD GetTimerPeriod;
EFI_TIMER_GENERATE_SOFT_INTERRUPT GenerateSoftInterrupt;
} EFI_TIMER_ARCH_PROTOCOL;
II-12.10. Timer Architectural Protocol II-117UEFI Platform Initialization Specification, Release 1.8
RegisterHandler
Registersahandlerthatwillbecalledeachtimethetimerinterruptfires. Seethe RegisterHandler() function
description. TimerPeriod defines the minimum time between timer interrupts, so TimerPeriod will also be
the minimum time between calls to the registered handler.
SetTimerPeriod
Sets the period of the timer interrupt in 100 ns units. See the SetTimerPeriod() function description. This
functionisoptionalandmayreturn EFI_UNSUPPORTED .Ifthisfunctionissupported,thenthetimerperiodwill
be rounded up to the nearest supported timer period.
GetTimerPeriod
Retrieves the period of the timer interrupt in 100 ns units. See the GetTimerPeriod() function description.
GenerateSoftInterrupt
Generates a soft timer interrupt that simulates the firing of the timer interrupt. This service can be used
to invoke the registered handler if the timer interrupt has been masked for a period of time. See the
GenerateSoftInterrupt() function description.
This protocol provides the services to initialize a periodic timer interrupt and to register a handler that is called each
time the timer interrupt fires. It may also provide a service to adjust the rate of the periodic timer interrupt. When a
timer interrupt occurs, the handler is passed the amount of time that has passed since the previous timer interrupt.
II-12.10.2 EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
Summary
Registers a handler that is called each timer the timer interrupt fires.
Prototype
typedef
(EFIAPI *EFI_TIMER_REGISTER_HANDLER) (
IN CONST EFI_TIMER_ARCH_PROTOCOL *This,
IN EFI_TIMER_NOTIFY NotifyFunction
);
This
TheEFI_TIMER_ARCH_PROTOCOL instance.
The function to call when a timer interrupt fires. This function executes at EFI_TPL_HIGH_LEVEL . The DXE
Foundation will register a handler for the timer interrupt, so it can know how much time has passed. This
informationisusedtosignaltimerbasedevents. NULLwillunregisterthehandler. Type EFI_TIMER_NOTIFY is
Thisfunctionregistersthehandler NotifyFunction soitiscalledeverytimethetimerinterruptfires. Italsopassesthe
amountoftimesincethelasthandlercalltothe NotifyFunction . IfNotifyFunction isNULL,thenthehandleris
unregistered. Ifthehandlerisregistered,then EFI_SUCCESS isreturned. Iftheprocessordoesnotsupportregisteringa
timerinterrupthandler,then EFI_UNSUPPORTED isreturned. Ifanattemptismadetoregisterahandlerwhenahandler
is already registered, then EFI_ALREADY_STARTED is returned. If an attempt is made to unregister a handler when
a handler is not registered, then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to register the
NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR is returned.
II-12.10. Timer Architectural Protocol II-118UEFI Platform Initialization Specification, Release 1.8
typedef
VOID
(EFIAPI *EFI_TIMER_NOTIFY) (
IN UINT64 Time
);
Time
Timesincethelasttimerinterruptin100nsunits. Thiswilltypicallybe TimerPeriod ,butifatimerinterrupt
ismissed,andthe EFI_TIMER_ARCH_PROTOCOL drivercandetectmissedinterrupts,then Timewillcontainthe
actual amount of time since the last interrupt.
Table 12.12: Status Codes Returned
EFI_SUCCESS The timer handler was registered.
EFI_UNSUPPORTED The platform does not support timer interrupts.
EFI_ALREADY_STARTED NotifyFunction is notNULL, and a handler is already registered.
EFI_INVALID_PARAMETER NotifyFunction isNULL, and a handler was not previously registered.
EFI_DEVICE_ERROR The timer handler could not be registered.
II-12.10.3 EFI_TIMER_ARCH_PROTOCOL.SetTimerPeriod()
Summary
Sets the rate of the periodic timer interrupt.
Prototype
typedef
(EFIAPI *EFI_TIMER_SET_TIMER_PERIOD) (
IN UINT64 TimerPeriod
);
This
The rate to program the timer interrupt in 100 ns units. If the timer hardware is not programmable, then
EFI_UNSUPPORTED is returned. If the timer is programmable, then the timer period will be rounded up to the
nearesttimerperiodthatissupportedbythetimerhardware. If TimerPeriod issetto0,thenthetimerinterrupts
will be disabled.
This function adjusts the period of timer interrupts to the value specified by TimerPeriod . If the timer period is up-
dated,then EFI_SUCCESS isreturned. Ifthetimerhardwareisnotprogrammable,then EFI_UNSUPPORTED isreturned.
Ifanerroroccurswhileattemptingtoupdatethetimerperiod,thenthetimerhardwarewillbeputbackinitsstateprior
tothiscall,and EFI_DEVICE_ERROR isreturned. If TimerPeriod is0,thenthetimerinterruptisdisabled. Thisisnot
II-12.10. Timer Architectural Protocol II-119UEFI Platform Initialization Specification, Release 1.8

);
This
thesameasdisablingtheprocessor’sinterrupts. Instead,itmusteitherturnoffthetimerhardware,oritmustadjustthe
interrupt controller so that a processor interrupt is not generated when the timer interrupt fires.
Table 12.13: Status Codes Returned
EFI_SUCCESS The timer period was changed.
EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
II-12.10.4 EFI_TIMER_ARCH_PROTOCOL.GetTimerPeriod()
Summary
Retrieves the rate of the periodic timer interrupt.
Prototype
typedef
(EFIAPI *EFI_TIMER_GET_TIMER_PERIOD) (
OUT UINT64 *TimerPeriod
);
This
A pointer to the timer period to retrieve in 100 ns units. If 0 is returned, then the timer is currently disabled.
This function retrieves the period of timer interrupts in 100 ns units, returns that value in TimerPeriod , and returns
EFI_SUCCESS . IfTimerPeriod isNULL, thenEFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
returned, then the timer is currently disabled.
Table 12.14: Status Codes Returned
EFI_SUCCESS The timer period was returned in TimerPeriod .
EFI_INVALID_PARAMETER TimerPeriod isNULL.
II-12.10.5 EFI_TIMER_ARCH_PROTOCOL.GenerateSoftInterrupt()
Summary
Generates a soft timer interrupt.
Prototype
II-12.10. Timer Architectural Protocol II-120UEFI Platform Initialization Specification, Release 1.8
typedef
(EFIAPI *EFI_TIMER_GENERATE_SOFT_INTERRUPT) (
IN CONST EFI_TIMER_ARCH_PROTOCOL *This
);
This
This function generates a soft timer interrupt. If the platform does not support soft timer interrupts, then
EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. If a handler has been registered through the
EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() service,thenasofttimerinterruptwillbegenerated. Ifthetimer
interrupt is enabled when this service is called, then the registered handler will be invoked. The registered handler
should not be able to distinguish a hardware-generated timer interrupt from a software-generated timer interrupt.
Table 12.15: Status Codes Returned
EFI_SUCCESS The soft timer interrupt was generated.
EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
II-12.11 Variable Architectural Protocol
II-12.11.1 EFI_VARIABLE_ARCH_PROTOCOL
Summary
Providestheservicesrequiredtogetandsetenvironmentvariables. ThisprotocolmustbeproducedbyaruntimeDXE
driver and may be consumed only by the DXE Foundation.
GUID
#define EFI_VARIABLE_ARCH_PROTOCOL_GUID \
{0x1e5668e2,0x8481,0x11d4,0xbc,\
0xf1,0x0,0x80,0xc7,0x3c,0x88,0x81}
GetVariable() ,GetNextVariableName() ,SetVariable() andQueryVariableInfo() fields of the UEFI
Runtime Services Table. See Runtime Capabilities for details on these services. After the three fields of the UEFI
Runtime Services Table have been initialized, the driver must install the EFI_VARIABLE_ARCH_PROTOCOL_GUID on
a new handle with a NULL interface pointer. The installation of this protocol informs the DXE Foundation that the
read-only and the volatile environment variable related services are now available and that the DXE Foundation must
update the 32-bit CRC of the UEFI Runtime Services Table. The full complement of environment variable services
arenotavailableuntilboththisprotocoland EFI_VARIABLE_WRITE_ARCH_PROTOCOL areinstalled. DXEdriversthat
requireread-onlyaccessorread/writeaccesstovolatileenvironmentvariablesmusthavethisarchitecturalprotocolin
their dependency expressions. DXE drivers that require write access to nonvolatile environment variables must have
theEFI_VARIABLE_WRITE_ARCH_PROTOCOL in their dependency expressions.
II-12.11. Variable Architectural Protocol II-121UEFI Platform Initialization Specification, Release 1.8
II-12.12 Variable Write Architectural Protocol
II-12.12.1 EFI_VARIABLE_WRITE_ARCH_PROTOCOL
Summary
Provides the services required to set nonvolatile environment variables. This protocol must be produced by a runtime
DXE driver and may be consumed only by the DXE Foundation.
GUID
#define EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID \
{0x6441f818,0x6362,0x4e44,0xb5,\
0x70,0x7d,0xba,0x31,0xdd,0x24,0x53}
TheDXEdriverthatproducesthisprotocolmustbearuntimedriver. Thisdrivermayupdatethe SetVariable() field
of the UEFI Runtime Services Table. See Runtime Capabilities for details on this service. After the UEFI Runtime
Services Table has been initialized, the driver must install the EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID on a
newhandlewithaNULLinterfacepointer. TheinstallationofthisprotocolinformstheDXEFoundationthatthewrite
services for nonvolatile environment variables are now available and that the DXE Foundation must update the 32-bit
CRC of the UEFI Runtime Services Table. The full complement of environment variable services are not available
untilboththisprotocoland EFI_VARIABLE_ARCH_PROTOCOL areinstalled. DXEdriversthatrequireread-onlyaccess
orread/writeaccesstovolatileenvironmentvariablesmusthavethe EFI_VARIABLE_WRITE_ARCH_PROTOCOL intheir
dependency expressions. DXE drivers that require write access to nonvolatile environment variables must have this
architectural protocol in their dependency expressions.
II-12.13 EFI Capsule Architectural Protocol
II-12.13.1 EFI_CAPSULE_ARCH_PROTOCOL
Summary
Provides the services for capsule update.
GUID
#define EFI_CAPSULE_ARCH_PROTOCOL_GUID \
{ 0x5053697e, 0x2cbc, 0x4819, 0x90, \
0xd9, 0x5, 0x80, 0xde, 0xee, 0x57, 0x54 }
The DXE Driver that produces this protocol must be a runtime driver. The driver is responsible for ini-
tializing the CapsuleUpdate() andQueryCapsuleCapabilities() fields of the UEFI Runtime Services Ta-
ble. After the two fields of the UEFI Runtime Services Table have been initialized, the driver must install the
EFI_CAPSULE_ARCH_PROTOCOL_GUID on a new handle with a NULLinterface pointer. The installation of this pro-
tocol informs the DXE Foundation that the Capsule related services are now available and that the DXE Foundation
must update the 32-bit CRC of the UEFI Runtime Services Table.
II-12.12. Variable Write Architectural Protocol II-122UEFI Platform Initialization Specification, Release 1.8
II-12.14 Watchdog Timer Architectural Protocol
Thefollowingtopicsprovideadetaileddescriptionofthe EFI_WATCHDOG_TIMER_ARCH_PROTOCOL .Thisprotocolis
used to implement the Boot Service SetWatchdogTimer() . The watchdog timer may be implemented in software
using Boot Services, or it may be implemented with specialized hardware. The protocol provides a service to register
a handler when the watchdog timer fires and a service to set the amount of time to wait before the watchdog timer is
fired.
II-12.14.1 EFI_WATCHDOG_TIMER_ARCH_PROTOCOL
Summary
Used to program the watchdog timer and optionally register a handler when the watchdog timer fires. This protocol
mustbeproducedbyabootserviceorruntimeDXEdriverandmaybeconsumedonlybytheDXEFoundationorDXE
driversthatproduceotherDXEArchitecturalProtocols. Ifaplatformwishestoperformaplatform-specificactionwhen
the watchdog timer expires, then the DXE driver that contains the implementation of the EFI_BDS_ARCH_PROTOCOL
should use this protocol’s RegisterHandler() service.
GUID
#define EFI_WATCHDOG_TIMER_ARCH_PROTOCOL_GUID \
{0x665E3FF5,0x46CC,0x11d4,0x9A,\
typedef struct _EFI_WATCHDOG_TIMER_ARCH_PROTOCOL {
EFI_WATCHDOG_TIMER_REGISTER_HANDLER RegisterHandler;
EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD SetTimerPeriod;
EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD GetTimerPeriod;
} EFI_WATCHDOG_TIMER_ARCH_PROTOCOL;
Registers a handler that is invoked when the watchdog timer fires. See the RegisterHandler() function de-
Sets the amount of time in 100 ns units to wait before the watchdog timer is fired. See the SetTimerPeriod()
function description. If this function is supported, then the watchdog timer period will be rounded up to the
nearest supported watchdog timer period.
Retrievestheamountoftimein100nsunitsthatthesystemwillwaitbeforethewatchdogtimerisfired. Seethe
GetTimerPeriod() function description.
This protocol provides the services required to implement the Boot Service SetWatchdogTimer() . It provides a
service to set the amount of time to wait before firing the watchdog timer, and it also provides a service to register a
handler that is invoked when the watchdog timer fires. This protocol can implement the watchdog timer by using the
eventandtimerBootServices,oritcanmakeuseofcustomhardware. Whenthewatchdogtimerfires,controlwillbe

passedtoahandlerifonehasbeenregistered. Ifnohandlerhasbeenregistered,ortheregisteredhandlerreturns,then
the system will be reset by calling the Runtime Service ResetSystem() .
II-12.14. Watchdog Timer Architectural Protocol II-123UEFI Platform Initialization Specification, Release 1.8
II-12.14.2 EFI_WATCHDOG_TIMER_ARCH_PROTOCOL.RegisterHandler()
Summary
Registers a handler that is to be invoked when the watchdog timer fires.
Prototype
typedef
(EFIAPI *EFI_WATCHDOG_TIMER_REGISTER_HANDLER) (
IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
);
This
TheEFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.
The function to call when the watchdog timer fires. If this is NULL, then the handler will be unregistered. Type
EFI_WATCHDOG_TIMER_NOTIFY is defined in “Related Definitions” below.
This function registers a handler that is to be invoked when the watchdog timer fires. By default,
EFI_WATCHDOG_TIMER_ARCH_PROTOCOL will call the Runtime Service ResetSystem() when the watchdog timer
fires. If a NotifyFunction is registered, then NotifyFunction will be called before the Runtime Service
ResetSystem() is called. If NotifyFunction isNULL, then the watchdog handler is unregistered. If a watch-
dog handler is registered, then EFI_SUCCESS is returned. If an attempt is made to register a handler when a handler
is already registered, then EFI_ALREADY_STARTED is returned. If an attempt is made to uninstall a handler when a
handler is not installed, then return EFI_INVALID_PARAMETER .
typedef
VOID
(EFIAPI *EFI_WATCHDOG_TIMER_NOTIFY) (
);
Time
Thetimein100nsunitsthathaspassedsincethewatchdogtimerwasarmed. Forthenotifyfunctiontobecalled,
this must be greater than TimerPeriod .
Table 12.16: Status Codes Returned
EFI_SUCCESS The watchdog timer handler was registered or unregistered
II-12.14. Watchdog Timer Architectural Protocol II-124UEFI Platform Initialization Specification, Release 1.8
II-12.14.3 EFI_WATCHDOG_TIMER_ARCH_PROTOCOL.SetTimerPeriod()
Summary
Sets the amount of time in the future to fire the watchdog timer.
Prototype
typedef
(EFIAPI *EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) (
);
This
Theamountoftimein100nsunitstowaitbeforethewatchdogtimerisfired. If TimerPeriod iszero,thenthe
watchdog timer is disabled.
This function sets the amount of time to wait before firing the watchdog timer to TimerPeriod 100 ns units. If
TimerPeriod is zero, then the watchdog timer is disabled.
Table 12.17: Status Codes Returned
EFI_SUCCESS The watchdog timer has been programmed to fire in Time100 ns units.
EFI_DEVICE_ERROR A watchdog timer could not be programmed due to a device error.
II-12.14.4 EFI_WATCHDOG_TIMER_ARCH_PROTOCOL.GetTimerPeriod()
Retrieves the amount of time in 100 ns units that the system will wait before firing the watchdog timer.
Prototype
typedef
(EFIAPI *EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) (
);
This
A pointer to the amount of time in 100 ns units that the system will wait before the watchdog timer is fired. If
TimerPeriod of zero is returned, then the watchdog timer is disabled.
II-12.14. Watchdog Timer Architectural Protocol II-125UEFI Platform Initialization Specification, Release 1.8
This function retrieves the amount of time the system will wait before firing the watchdog timer. This period is re-
turned inTimerPeriod , andEFI_SUCCESS is returned. If TimerPeriod isNULL, thenEFI_INVALID_PARAMETER
Table 12.18: Status Codes Returned
EFI_SUCCESS Theamountoftimethatthesystemwillwaitbeforefiringthewatch-
dog timer was returned in TimerPeriod .
II-12.14. Watchdog Timer Architectural Protocol II-126CHAPTER
THIRTEEN
DXE BOOT SERVICES PROTOCOL
II-13.1 Overview
This chapter defines the services required for the Multiprocessor (MP) Services Protocol of Platform Initialization
Specification. This specification does the following:
•Describes the basic components of the MP Services Protocol
•Provides code definitions for the MP Services Protocol and the MP-related type definitions.
II-13.2 Conventions and Abbreviations
The following terms are used throughout this specification.
AP
Application processor. All other processors in a computer system other than the boot-strap processor are called
application processors.
BSP
Boot-strapprocessor. AprocessorinanMPplatformthatischosentoexecutethemodulesthatarenecessaryfor
booting the system. It is not necessary that the same processor that was selected earlier as a BSP shall remain a
BSP throughout an entire boot session.
DXE
DriverExecuteEnvironment. EnvironmenttosupportrunningmodularcodeintheformofEFIdrivers;common
to all platforms; typically in C language.
EFI
ExtensibleFirmwareInterface-thespecificationcontaininginterfacedefinitionsforfirmware. Thisincludesboth
interfacesusedbytheoperatingsystemforbootingaswellasinterfacesthatareusedforinternalconstructionof
firmware.
MP
Multiprocessor.
II-127UEFI Platform Initialization Specification, Release 1.8
II-13.3 MP Services Protocol Overview
The MP Services Protocol provides a generalized way of performing following tasks:
•Retrieving information of multi-processor environment and MP-related status of specific processors.
•Dispatching user-provided function to APs.
•Maintain MP-related processor status.
The MP Services Protocol must be produced on any system with more than one logical processor.
The Protocol is available only during boot time.
MPServicesProtocolishardware-independent. Mostofthelogicofthisprotocolisarchitecturallyneutral. Itabstracts
the multi-processor environment and status of processors, and provides interfaces to retrieve information, maintain,
and dispatch.
MP Services Protocol may be consumed by ACPI module. The ACPI module may use this protocol to retrieve data
that are needed for an MP platform and report them to OS.
MP Services Protocol may also be used to program and configure processors, such as MTRR synchronization for
memory space attributes setting in DXE Services.
MP Services Protocol may be used by non-CPU DXE drivers to speed up platform boot by taking advantage of the
processing capabilities of the APs, for example, using APs to help test system memory in parallel with other device
initialization.
Diagnostics applications may also use this protocol for multi-processor.
II-13.4 MP Services Protocol
This section contains the basic definitions of the MP Services Protocol.
II-13.4.1 EFI_MP_SERVICES_PROTOCOL
Summary
When installed, the MP Services Protocol produces a collection of services that are needed for MP management.
GUID
#define EFI_MP_SERVICES_PROTOCOL_GUID \
{0x3fdda605,0xa76e,0x4f46,{0xad,0x29,0x12,0xf4,\
0x53,0x1b,0x3d,0x08}}
typedef struct _EFI_MP_SERVICES_PROTOCOL {
EFI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
EFI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;
EFI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;
EFI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;
EFI_MP_SERVICES_SWITCH_BSP SwitchBSP;
EFI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;
EFI_MP_SERVICES_WHOAMI WhoAmI;
} EFI_MP_SERVICES_PROTOCOL;
II-13.3. MP Services Protocol Overview II-128UEFI Platform Initialization Specification, Release 1.8
Gets the number of logical processors and the number of enabled logical processors in the system.
Gets detailed information on the requested processor at the instant this call is made.
Starts up all the enabled APs in the system to run the function provided by the caller.
Starts up the requested AP to run the function provided by the caller.
SwitchBSP
SwitchestherequestedAPtobetheBSPfromthatpointonward. ThisservicechangestheBSPforallpurposes.
EnableDisableAP
Enables and disables the given AP from that point onward.
WhoAmI
Gets the handle number of the caller processor.
The MP Services Protocol must be produced on any system with more than one logical processor. Before the
UEFI event EFI_EVENT_LEGACY_BOOT_GUID orEFI_EVENT_GROUP_EXIT_BOOT_SERVICES is signaled, the mod-
ule that produces this protocol is required to place all APs into an idle state whenever the APs are disabled
or the APs are not executing code as requested through the StartupAllAPs() orStartupThisAP() services.

SwitchBSP
WhoAmI
The idle state of an AP is implementation dependent before the UEFI event EFI_EVENT_LEGACY_BOOT_GUID or
EFI_EVENT_GROUP_EXIT_BOOT_SERVICES is signaled.
AftertheUEFIevent EFI_EVENT_LEGACY_BOOT_GUID orEFI_EVENT_GROUP_EXIT_BOOT_SERVICES issignaled,all
theAPsmustbeplacedintheOScompatibleCPUstateasdefinedbytheUEFISpecification. Implementationsofthis
protocol may use the UEFI event EFI_EVENT_LEGACY_BOOT_GUID orEFI_EVENT_GROUP_EXIT_BOOT_SERVICES
to force APs into the OS compatible state as defined by the UEFI Specification. Modules that use this pro-
tocol must guarantee that all non-blocking mode requests on all APs have been completed before the UEFI
eventEFI_EVENT_LEGACY_BOOT_GUID orEFI_EVENT_GROUP_EXIT_BOOT_SERVICES is signaled. Since the or-
der that event notification functions in the same event group are executed is not deterministic, an event of type
EFI_EVENT_LEGACY_BOOT_GUID orEFI_EVENT_GROUP_EXIT_BOOT_SERVICES can not be used to guarantee that
APs have completed their non-blocking mode requests.
II-13.4.2 EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors()
Summary
are currently enabled. This service may only be called from the BSP.
Prototype
typedef
(EFIAPI *EFI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) (
IN EFI_MP_SERVICES_PROTOCOL *This,
);
II-13.4. MP Services Protocol II-129UEFI Platform Initialization Specification, Release 1.8
This
A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
Pointer to the total number of logical processors in the system, including the BSP and all enabled and disabled
APs.
Pointer to the number of logical processors in the platform including the BSP that are currently enabled.
•The number of logical processors that are present in the system
Since MP Service Protocol provides services to enable and disable processors dynamically, the number of enabled
logical processors may vary during the course of a boot session.
If this service is called from an AP, then EFI_DEVICE_ERROR is returned. If NumberOfProcessors or
NumberOfEnabledProcessors isNULL, thenEFI_INVALID_PARAMETER i s returned. Otherwise, the total num-
ber of processors is returned in NumberOfProcessors , the number of currently enabled processor is returned in
NumberOfEnabledProcessors , andEFI_SUCCESS is returned.
Table 13.1: Status Codes Returned
EFI_SUCCESS The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR The calling processor is an AP.
EFI_INVALID_PARAMETER NumberOfProcessors isNULL.
EFI_INVALID_PARAMETER NumberOfEnabledProcessors isNULL.
II-13.4.3 EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo()
Summary
Prototype
typedef
(EFIAPI *EFI_MP_SERVICES_GET_PROCESSOR_INFO) (
);
this-1
II-13.4. MP Services Protocol II-130UEFI Platform Initialization Specification, Release 1.8
processornumber
Thehandlenumberofprocessor. Therangeisfrom0tothetotalnumberoflogicalprocessorsminus1. Thetotal
numberoflogicalprocessorscanberetrievedby EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors() .
processorinfobuffer
Apointertothebufferwhereinformationfortherequestedprocessorisdeposited. Thebufferisallocatedbythe
caller. Type EFI_PROCESSOR_INFORMATION is defined in “Related Definitions” below.
•The data of information presented here is entirely MP related.
// EFI_PROCESSOR_INFORMATION
UINT64 ProcessorId;
UINT32 StatusFlag;
EFI_CPU_PHYSICAL_LOCATION Location;
EXTENDED_PROCESSOR_INFORMATION ExtendedInformation;
} EFI_PROCESSOR_INFORMATION;
ProcessorId
The unique processor ID determined by system hardware. For IPF, the lower 16 bits contains id/eid, and higher
bits are reserved.
StatusFlag
Flags indicating if the processor is BSP or AP, if the processor is enabled or disabled, and if the processor is
healthy. The bit format is defined below.
Location
The physical location of the processor, including the physical package number that identifies the cartridge, the
physical core number within package, and logical thread number within core. Type EFI_PHYSICAL_LOCATION
is defined below.
ExtendedInformation
The extended information of the processor. This field is filled only when CPU_V2_EXTENDED_TOPOLOGY
is set in parameter ProcessorNumber . Value CPU_V2_EXTENDED_TOPOLOGY and type
EXTENDED_PROCESSOR_INFORMATION are defined below.
// StatusFlag Bits Definition
#define PROCESSOR_AS_BSP_BIT 0x00000001
#define PROCESSOR_ENABLED_BIT 0x00000002
#define PROCESSOR_HEALTH_STATUS_BIT 0x00000004
PROCESSOR_AS_BSP_BIT
This bit indicates whether the processor is playing the role of BSP. If the bit is 1, then the processor is BSP.
II-13.4. MP Services Protocol II-131UEFI Platform Initialization Specification, Release 1.8
Otherwise, it is AP.
PROCESSOR_ENABLED_BIT
Thisbitindicateswhethertheprocessorisenabled. Ifthebitis1,thentheprocessorisenabled. Otherwise,itis
disabled.
PROCESSOR_HEALTH_STATUS_BIT
Thisbitindicateswhethertheprocessorishealthy. Ifthebitis1,thentheprocessorishealthy. Otherwise,some
fault has been detected for the processor.
Bits 3..31 are reserved and must be 0. The following table shows all the possible combinations of the StatusFlag
bits:
Table 13.2: StatusFlag bits
BSPENABLED HEALTH Description
00 0 Unhealthy Disabled AP.
00 1 Healthy Disabled AP.
01 0 Unhealthy Enabled AP.
01 1 Healthy Enabled AP.
10 0 Invalid. The BSP can never be in the disabled state.
10 1 Invalid. The BSP can never be in the disabled state.
11 0 Unhealthy Enabled BSP.
11 1 Healthy Enabled BSP.
// EFI_CPU_PHYSICAL_LOCATION
UINT32 Package;
UINT32 Core;
UINT32 Thread;
} EFI_CPU_PHYSICAL_LOCATION;
Package
Zero-based physical package number that identifies the cartridge of the processor.
Core
Zero-based physical core number within package of the processor.
Thread
Zero-based logical thread number within core of the processor.
#define CPU_V2_EXTENDED_TOPOLOGY BIT24
EFI_CPU_PHYSICAL_LOCATION2 Location2;
} EXTENDED_PROCESSOR_INFORMATION;
Location2
The 6-level physical location of the processor, including the physical package number that identifies the car-
tridge,thephysicalmodulenumberwithinpackage,thephysicaltilenumberwithinthemodule,thephysicaldie
number within the tile, the physical core number within package, and logical thread number within core. Type
EFI_CPU_PHYSICAL_LOCATION2 is defined below.
II-13.4. MP Services Protocol II-132UEFI Platform Initialization Specification, Release 1.8
UINT32 Module;
UINT32 Tile;
UINT32 Die;
} EFI_CPU_PHYSICAL_LOCATION2;
Package
Module
Zero-based physical module number within package of the processor.
Tile
Zero-based physical tile number within module of the processor.
Die
Zero-based physical die number within tile of the processor.
Core
Zero-based physical core number within die of the processor.
Thread
Table 13.3: Status Codes Returned
EFI_SUCCESS Processor information was returned.
EFI_INVALID_PARAMETER ProcessorInfoBuffer isNULL.
not exist in the platform.
II-13.4.4 EFI_MP_SERVICES_PROTOCOL.StartupAllAPs()
Summary
This service executes a caller provided function on all enabled APs. APs can run either simultaneously or one at a

Package
Module
Tile
Die
Core
Thread
Summary
time in sequence. This service supports both blocking and non-blocking requests. The non-blocking requests use EFI
events so the BSP can detect when the APs have finished. See “Non-blocking Execution Support” below for details.
Prototype
typedef
(EFIAPI *EFI_MP_SERVICES_STARTUP_ALL_APS) (
IN EFI_EVENT WaitEvent OPTIONAL,
IN VOID *ProcedureArgument OPTIONAL,
II-13.4. MP Services Protocol II-133UEFI Platform Initialization Specification, Release 1.8
OUT UINTN **FailedCpuList OPTIONAL
);
This
Procedure
A pointer to the function to be run on enabled APs of the system. Type EFI_AP_PROCEDURE is defined in the
“Related Definitions” of this function, below.
of processor handle number.
IfFALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
WaitEvent
The event created by the caller with CreateEvent() service.
If it isNULL, then execute in blocking mode. BSP waits until all APs finish or TimeoutInMicroSeconds
expires.
If it’s not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure
to be started on all the enabled APs, and go on executing immediately. If all return from Procedure
orTimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or
WaitForEvent() services to check the state of event.
TypeEFI_EVENT isdefinedin CreateEvent() intheUnifiedExtensibleFirmwareInterfaceSpecification(Ver-
sion 2.0).
IndicatesthetimelimitinmicrosecondsforAPstoreturnfrom Procedure ,eitherforblockingornon-blocking
mode. Zero means infinity.
IfthetimeoutexpiresbeforeallAPsreturnfrom Procedure ,thenProcedure onthefailedAPsisterminated.
AllenabledAPsareavailablefornextfunctionassignedby EFI_MP_SERVICES_PROTOCOL.StartupAllAPs()
orEFI_MP_SERVICES_PROTOCOL.StartupThisAP().
If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent() .
FailedCpuList
IfNULL, this parameter is ignored.
Otherwise, if all APs finish successfully, then its content is set to NULL. If not all APs finish before timeout
expires, then its content is set to address of the buffer holding handle numbers of the failed APs. The buffer is
allocatedbyMPServiceProtocol,andit’sthecaller’sresponsibilitytofreethebufferwith FreePool() service.
In blocking mode, it is ready for consumption when the call returns. In non-blocking mode, it is ready when
WaitEvent is signaled.
The list of failed CPU is terminated by END_OF_CPU_LIST . It is defined in “Related Definitions” below.
This function is used to dispatch all the enabled APs to the function specified by Procedure .
II-13.4. MP Services Protocol II-134UEFI Platform Initialization Specification, Release 1.8
If any enabled AP is busy, then EFI_NOT_READY is returned immediately and Procedure is not started on any AP.
IfWaitEvent isNULL, execution is in blocking mode. The BSP waits until all APs finish or TimeoutInMicroSecs
expires. Otherwise,executionisinnon-blockingmode,andtheBSPreturnsfromthisservicewithoutwaitingforAPs.
If a non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then
EFI_UNSUPPORTED must be returned.
EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() andEFI_MP_SERVICES_PROTOCOL.StartupThisAP() . If
FailedCpuList is notNULL, its content points to the list of processor handle numbers in which Procedure was
terminated.
Note: Itistheresponsibilityoftheconsumerofthe EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() tomakesure
that the nature of the code that is executed on the BSP and the dispatched APs is well controlled. The MP Services
Protocol does not guarantee that the Procedure function is MP-safe. Hence, the tasks that can be run in parallel are
limited to certain independent tasks and well-controlled exclusive code. EFI services and protocols may not be called
by APs unless otherwise specified.
#define END_OF_CPU_LIST 0xffffffff
typedef
VOID
(EFIAPI *EFI_AP_PROCEDURE) (
IN VOID *ProcedureArgument
);
Pointer to the procedure’s argument
Non-Blocking Execution Support
The following usage guidelines must be followed for non-blocking execution support.
In non-blocking execution mode, BSP is freed to return to the caller and then proceed to the next task without having
to wait for APs. The following sequence needs to occur in a non-blocking execution mode:
1. ThecallerthatintendstousethisMPServicesProtocolinnon-blockingmodecreates WaitEvent bycallingthe
EFICreateEvent() service.
The caller invokes EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() . If the parameter WaitEvent is notNULL,
thenStartupAllAPs() executesinnon-blockingmode. Itrequeststhefunctionspecifiedby Procedure tobestarted
on all the enabled APs, and releases the BSP to continue with other tasks.
2. The caller can use the CheckEvent() andWaitForEvent() services to check the state of the WaitEvent
created in step 1.
3. When the APs complete their task or TimeoutInMicroSecondss expires, the MP Service signals WaitEvent
by calling the EFI SignalEvent() function. If FailedCpuList is not NULL, its content is available when
WaitEvent is signaled. If all APs returned from Procedure prior to the timeout, then FailedCpuList is set
toNULL. If not all APs return from Procedure before the timeout, then FailedCpuList is filled in with the
II-13.4. MP Services Protocol II-135UEFI Platform Initialization Specification, Release 1.8
listofthefailedAPs. ThebufferisallocatedbyMPServiceProtocolusing AllocatePool() . Itisthecaller’s
responsibility to free the buffer with FreePool() service.
4. This invocation of SignalEvent() function informs the caller that invoked EFI_MP_SERVICES_PROTOCOL.
StartupAllAPs() that either all the APs completed the specified task or a timeout occurred. The contents
ofFailedCpuList can be examined to determine which APs did not complete the specified task prior to the
timeout.
Table 13.4: Status Codes Returned
EFI_SUCCESS Inblockingmode,allAPshavefinishedbeforethetimeoutexpired.
EFI_SUCCESS In non blocking mode, function has been dispatched to all enabled
APs.
EFI_UNSUPPORTED A non blocking mode request was made after the UEFI event
EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
finished.
EFI_INVALID_PARAMETER Procedure isNULL.
II-13.4.5 EFI_MP_SERVICES_PROTOCOL.StartupThisAP()
Summary
either wait for the completion of the AP or just proceed with the next task by using the EFI event mechanism. See the
“Non-blocking Execution Support” section in EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() for more details.
Prototype
typedef
(EFIAPI *EFI_MP_SERVICES_STARTUP_THIS_AP) (
OUT BOOLEAN *Finished OPTIONAL
);
This
Procedure
A pointer to the function to be run on the designated AP. Type EFI_AP_PROCEDURE is defined in
EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() .
II-13.4. MP Services Protocol II-136UEFI Platform Initialization Specification, Release 1.8
numberoflogicalprocessorscanberetrievedby EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors()
.
WaitEvent

Prototype
typedef
);
This
Procedure
.
WaitEvent
If it isNULL, then execute in blocking mode. BSP waits until this AP finishes or TimeoutInMicroSeconds
expires.
If it’s not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be
started on the AP, and go on executing immediately. If this AP finishes or TimeoutInMicroSeconds expires,
this event is signaled. BSP can use the CheckEvent() andWaitForEvent() services to check the state of
event.
sion 2.0)
Indicates the time limit in microseconds for this AP to finish the function, either for blocking or non-blocking
If the timeout expires before this AP returns from Procedure, then Procedure on the AP is termi-
nated. The AP is available for subsequent calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() and
EFI_MP_SERVICES_PROTOCOL.StartupThisAP() .
The parameter passed into Procedure on the specified AP.
Finished
In blocking mode, this parameter is ignored.
In non-blocking mode, if AP returns from Procedure before the timeout expires, its content is set to TRUE.
Otherwise,thevalueissetto FALSE.ThecallercandetermineiftheAPreturnedfrom Procedure byevaluating
this value.
IfWaitEvent isNULL, execution is in blocking mode. The BSP waits until the AP finishes or
TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode. BSP proceeds to
the next task without waiting for the AP. If a non-blocking mode is requested after the UEFI Event
EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then EFI_UNSUPPORTED must be returned.
ofProcedure by the AP is terminated. The AP is available for subsequent calls to EFI_MP_SERVICES_PROTOCOL.
StartupAllAPs() andEFI_MP_SERVICES_PROTOCOL.StartupThisAP() .
II-13.4. MP Services Protocol II-137UEFI Platform Initialization Specification, Release 1.8
Table 13.5: Status Codes Returned
EFI_SUCCESS Inblockingmode,specifiedAPfinishedbeforethetimeoutexpires.
EFI_SUCCESS Innon-blockingmode,thefunctionhasbeendispatchedtospecified
AP.
EFI_UNSUPPORTED A non-blocking mode request was made after the UEFI event
EFI_TIMEOUT In blocking mode, the timeout expired before the specified AP has
finished.
EFI_NOT_READY The specified AP is busy.
not exist.
EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or disabled AP.
II-13.4.6 EFI_MP_SERVICES_PROTOCOL.SwitchBSP()
Summary
purposes. This service may only be called from the current BSP.
Prototype
typedef
(EFIAPI *EFI_MP_SERVICES_SWITCH_BSP) (
);
ThisA pointer to the EFI_MP_SERVICES_PROTOCOL instance.
processorsminus1. Thetotalnumberoflogicalprocessorscanberetrievedby EFI_MP_SERVICES_PROTOCOL.
left off. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.
This call can only be performed by the current BSP.
II-13.4. MP Services Protocol II-138UEFI Platform Initialization Specification, Release 1.8
Table 13.6: Status Codes Returned
EFI_SUCCESS BSP successfully switched.
EFI_UNSUPPORTED Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED Switching the BSP is not supported.
EFI_NOT_FOUND The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or a disabled AP.
II-13.4.7 EFI_MP_SERVICES_PROTOCOL.EnableDisableAP()
Summary
This service lets the caller enable or disable an AP from this point onward. This service may only be called from the
BSP.
Prototype
typedef
(EFIAPI *EFI_MP_SERVICES_ENABLEDISABLEAP) (
);
This
ThehandlenumberofAP.Therangeisfrom0tothetotalnumberoflogicalprocessorsminus1. Thetotalnumber
of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors() .
EnableAP
Specifiesthenewstatefortheprocessorspecifiedby ProcessorNumber .TRUEforenabled, FALSEfordisabled.
If notNULL, a pointer to a value that specifies the new health status of the AP. This flag cor-
responds to StatusFlag defined in EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() . Only the
PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored.
If it is NULL, this parameter is ignored.
performed on the AP, so the AP is in a state that is compatible with an MP operating system. This service may not be
supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.
II-13.4. MP Services Protocol II-139UEFI Platform Initialization Specification, Release 1.8
Table 13.7: Status Codes Returned
EFI_SUCCESS The specified AP successfully enabled or disabled.
EFI_UNSUPPORTED EnablingordisablinganAPcannotbecompletedpriortothisservicereturning.
EFI_UNSUPPORTED Enabling or disabling an AP is not supported.
EFI_NOT_FOUND Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP.
II-13.4.8 EFI_MP_SERVICES_PROTOCOL.WhoAmI()
Summary
This return the handle number for the calling processor. This service may be called from the BSP and APs.
Prototype
typedef
(EFIAPI *EFI_MP_SERVICES_WHOAMI) (
);
This
Pointer to the handle number of AP. The range is from 0 to the total number of logical processors
minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.
This service returns the processor handle number for the calling processor. The returned value is in the range from
0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved with
EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors() . ThisservicemaybecalledfromtheBSPandAPs. If
ProcessorNumber isNULL, thenEFI_INVALID_PARAMETER is returned. Otherwise, the current processors handle
number is returned in ProcessorNumber , andEFI_SUCCESS is returned.
Table 13.8: Status Codes Returned
EFI_SUCCESS The current processor handle number was returned in ProcessorNumber .
EFI_INVALID_PARAMETER ProcessorNumber isNULL.
II-13.4. MP Services Protocol II-140CHAPTER
FOURTEEN
DXE RUNTIME PROTOCOLS
II-14.1 Introduction
Inadditiontothearchitecturalprotocolslistedearlier,thereisalsoaruntimeprotocol. Specifically,theabilitytoreport
statuscodesisruntime-callableservicethatallowsforemittingstatusandprogressinformation. Itwasformerlypartof
the 0.9 DXE-CIS runtime table, but in consideration of UEFI 2.0 compatibility, this capability has become a separate
runtime protocol.

FOURTEEN
II-14.2 Status Code Runtime Protocol
II-14.2.1 EFI_STATUS_CODE_ PROTOCOL
Summary
Provides the service required to report a status code to the platform firmware. This protocol must be produced by a
runtime DXE driver.
GUID
#define EFI_STATUS_CODE_RUNTIME_PROTOCOL_GUID \
{ 0xd2b2b828, 0x826, 0x48a7, 0xb3, 0xdf, 0x98, 0x3c, \
0x0, 0x60, 0x24, 0xf0}
typedef struct _EFI_STATUS_CODE_PROTOCOL {
EFI_REPORT_STATUS_CODE ReportStatusCode;
} EFI_STATUS_CODE_PROTOCOL;
Emit a status code.
The DXE driver that produces this protocol must be a runtime driver. This driver is responsible for providing the
ReportStatusCode() service with the EFI_STATUS_CODE_PROTOCOL .
EFI_STATUS_CODE_PROTOCOL.ReportStatusCode()
Summary
Provides an interface that a software module can call to report a status code.
II-141UEFI Platform Initialization Specification, Release 1.8
Prototype
(EFIAPI \*EFI_REPORT_STATUS_CODE) (
);
Type
Indicates the type of status code being reported. Type EFI_STATUS_CODE_TYPE is defined in “Related Defini-
Value
Describes the current status of a hardware or software entity. This included information about the class and
Instance
CallerId
different rules to different callers. Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI
Data
Thisoptionalparametermaybeusedtopassadditionaldata. Type EFI_STATUS_CODE_DATA isdefinedinvolume
3 of this specification. The contents of this data type may have additional GUID-specific data.
Various software modules including drivers can call this function to report a status code. No disposition of the status
code is guaranteed. The ReportStatusCode() function may choose to log the status code, but this action is not
required.
It is possible that this function may get called at EFI_TPL_LEVEL_HIGH . Therefore, this function cannot call
any protocol interface functions or services (including memory allocation) that are not guaranteed to work at
EFI_TPL_LEVEL_HIGH . It should be noted that SignalEvent() could be called by this function because it works
atanyTPLincluding EFI_TPL_LEVEL_HIGH .Itispossibleforanimplementationtouseeventstologthestatuscodes
when the TPL level is reduced.
ReportStatusCode() functioncanperformotherimplementationspecificwork,butthatisnotspecifiedinthearchi-
tecture document.
In case of an error, the caller can specify the severity. In most cases, the entity that reports the error may not have a
platform wide view and may not be able to accurately assess the impact of the error condition. The DXE driver that
producestheStatusCodeProtocol, EFI_STATUS_CODE_PROTOCOL ,isresponsibleforassessingthetrueseveritylevel
basedonthereportedseverityandotherinformation. ThisDXEdrivermayperformplatformspecificactionsbasedon
the type and severity of the status code being reported.
IfDatais present, the Status Code Protocol driver treats it as read only data. The Status Code Protocol driver must
copyDatatoalocalbufferinanatomicoperationbeforeperforminganyotheractions. Thisisnecessarytomakethis
II-14.2. Status Code Runtime Protocol II-142UEFI Platform Initialization Specification, Release 1.8
function re-entrant. The size of the local buffer may be limited. As a result, some of the Datacan be lost. The size of
thelocalbuffershouldatleastbe256bytesinsize. Largerbufferswillreducetheprobabilityoflosingpartofthe Data
. Note than multiple status codes may be reported at elevated TPL levels before the TPL level is reduced. Allocating
multiple local buffers may reduce the probability losing status codes at elevated TPL levels. If all of the local buffers
are consumed, then this service may not be able to perform the platform specific action required by the status code
being reported. As a result, if all the local buffers are consumed, the behavior of this service is undefined.
IftheCallerId parameterisnot NULL,thenitisrequiredtopointtoaconstantGUID.Inotherwords,thecallermay
not reuse or release the buffer pointed to by CallerId .
//
//
//
//
//
//
//
//
//
//
II-14.2. Status Code Runtime Protocol II-143UEFI Platform Initialization Specification, Release 1.8
//
//
Size
Type
Table 14.1: Status Codes Returned
EFI_DEVICE_ERROR The function should not be completed due to a device error.
II-14.2. Status Code Runtime Protocol II-144CHAPTER
FIFTEEN
II-15.1 Dependency Expression Grammar
This topic contains an example BNF grammar for a DXE driver dependency expression compiler that converts a de-
pendency expression source file into a dependency section of a DXE driver stored in a firmware volume.
II-15.2 Example Dependency Expression BNF Grammar
<depex> ::= BEFORE <guid>
| AFTER <guid>
| SOR <bool>
| <bool>
| <term>
| <factor>
| TRUE
| FALSE
| GUID
| END
<hex8> ‘,’ <hex8> ‘,’
˓→<hex8> ‘,’ <hex8> ‘,’
˓→<hex8> ‘,’ <hex8> ’}’
| ‘0’ ‘X’
| [a-f]
| [A-F]
II-145UEFI Platform Initialization Specification, Release 1.8
II-15.3 Sample Dependency Expressions
//
// Source
//
EFI_CPU_IO_PROTOCOL_GUID AND EFI_CPU_ARCH_PROTOCOL_GUID END
//
//
ADDR BINARY ␣
˓→ MNEMONIC
==== =========================
0x00 : 02 ␣
˓→ PUSH
0x01 : 26 25 73 b0 c8 38 40 4b EFI_CPU_IO_PROTOCOL_GUID
0x11 : 02 ␣
˓→ PUSH
0x12 : b1 cc ba 26 42 6f d4 11 EFI_CPU_ARCH_PROTOCOL_GUID
0x22 : 03 ␣
˓→ AND
0x23 : 08 ␣
˓→ END
//
// Source
//
AFTER (EFI_CPU_DRIVER_FILE_NAME_GUID) END
//
//
0x00 : 01 ␣
˓→ AFTER
0x01 : 93 e5 7b 98 43 16 0b 45 EFI_CPU_DRIVER_FILE_NAME_GUID
be 4f 8f 07 66 6e 36 56
0x11 : 08 ␣
˓→ END
//
// Source
//

//
// Source
//
//
//
0x00 : 02 ␣
˓→ PUSH
0x11 : 02 ␣
˓→ PUSH
0x22 : 03 ␣
˓→ AND
0x23 : 08 ␣
˓→ END
//
// Source
//
//
//
0x00 : 01 ␣
˓→ AFTER
0x11 : 08 ␣
˓→ END
//
// Source
//
SOR EFI_CPU_IO_PROTOCOL_GUID END
II-15.3. Sample Dependency Expressions II-146UEFI Platform Initialization Specification, Release 1.8
//
// Opcodes, Operands andBinary Encoding
//
0x00 : 09 ␣
˓→ SOR
0x01 : 02 ␣
˓→ PUSH
0x02 : b1 cc ba 26 42 6f d4 11 EFI_CPU_IO_PROTOCOL_GUID
0x12 : 03 ␣
˓→ END
II-15.3. Sample Dependency Expressions II-147CHAPTER
SIXTEEN
APPENDIX: ERROR CODES
#define DXE_ERROR(a) (MAX_BIT|MAX_BIT >> 2 | (a))
EFI_REQUEST_UNLOAD_IMAGE DXE_ERROR (1) If this value is returned by an EFI image,
then the image should be unloaded.
EFI_NOT_AVAILABLE_YET DXE_ERROR (2) IF this value is returned by an API,
it means the capability is not yet in-
stalled/available/ready to use.
II-148CHAPTER
SEVENTEEN
APPENDIX: GUID DEFINITIONS
II-17.1 DXE Services Table GUID
#define DXE_SERVICES_TABLE_GUID \
{0x5ad34ba,0x6f02,0x4214,0x95,0x2e,0x4d,0xa0,0x39,0x8e,0x2b,0xb9}
The DXE Services Table shall be stored in memory of type EfiBootServicesData.
II-17.2 HOB List GUID
#define HOB_LIST_GUID {0x7739f24c,0x93d7,0x11d4,0x9a,0x3a,0x0,0x90,0x27,0x3f,0xc1,0x4d}
The HOB List Table shall be stored in memory of type EfiBootServicesData
II-149Part III
Shared Architectural ElementsUEFI Platform Initialization Specification, Release 1.8
List of Figures - Volume III
•Bit Allocation of FFS Attributes
•EFI_FV_FILE_ATTRIBUTES-fields
•Example File Image (Graphical and TreeRepresentations)
•The Firmware Volume Format
•Typical FFS File Layout
•File Header 2 layout for files larger than 16Mb
•Format of a section (below 16Mb)
•Format of a section using the ExtendedLengthfield
•Creating a File
•Updating a File
•Example HOB Producer Phase Memory Map and Usage
•Status Code Services
•Hierarchy of Status Code Operations
III-iUEFI Platform Initialization Specification, Release 1.8
•Descriptions of EFI_FVB_ATTRIBUTES_2
•Bit Allocation Definitions
•Supported FFS Alignments
•Description of Fields for CompressionType
•Descriptions of Fields for GuidedSectionHeader.Attributes
•AuthenticationStatus Bit Definitions
•Descriptions of Fields for EFI_FV_ATTRIBUTES
•Description of fields for EFI_FV_WRITE_POLICY
•Defined File Types
•Architectural Section Types
•EFI_RESOURCE_ATTRIBUTE_TYPE fields
•HOB Producer Phase Resource Types
•Translation of HOB Specification Terminology
•Organization of This Specification
•Class Definitions
•Progress Code Operations: Computing UnitClass
•Error Code Operations: Computing Unit Class
•Computing Unit Class: Subclasses
•Progress and Error Code Operations: Computing Unit Unspecified Subclass
•Progress and Error Code Operations: HostProcessor Subclass
•Progress and Error Code Operations:Service Processor Subclass
•Progress and Error Code Operations: CacheSubclass
•Progress and Error Code Operations: MemorySubclass
•Progress and Error Code Operations:Chipset Subclass
•Progress Code Operations: User-AccessiblePeripheral Class
•Error Code Operations: User-AccessiblePeripheral Class
•Defined Subclasses: User-Accessible Peripheral Class
•Progress and Error Code Operations: Peripheral Unspecified Subclass
•Progress and Error Code Operations: Keyboard Subclass
•Progress and Error Code Operations: MouseSubclass
•Progress and Error Code Operations: LocalConsole Subclass
•Progress and Error Code Operations: RemoteConsole Subclass
•Progress and Error Code Operations: SerialPort Subclass
•Progress and Error Code Operations:Parallel Port Subclass
•Progress and Error Code Operations: FixedMedia Subclass
III-iiUEFI Platform Initialization Specification, Release 1.8
•Progress and Error Code Operations: Removable Media Subclass
•Progress and Error Code Operations: AudioInput Subclass
•Progress and Error Code Operations: AudioOutput Subclass
•Progress and Error Code Operations: LCD Device Subclass
•Progress and Error Code Operations: Network Device Subclass
•Progress Code Operations: I/O Bus Class
•Error Code Operations: I/O Bus Class
•Defined Subclasses: I/O Bus Class
•Progress and Error Code Operations: I/OBus Unspecified Subclass
•Progress and Error Code Operations: PCISubclass
•Progress and Error Code Operations: USBSubclass
•Progress and Error Code Operations: IBASubclass
•Progress and Error Code Operations: AGPSubclass
•Progress and Error Code Operations: PCCard Subclass
•Progress and Error Code Operations: LPCSubclass
•Progress and Error Code Operations: SCSISubclass
•Progress and Error Code Operations:ATA/ATAPI/SATA Subclass
•Progress and Error Code Operations: FCSubclass
•Progress and Error Code Operations: IPNetwork Subclass
•Progress and Error Code Operations: SMBusSubclass
•Progress and Error Code Operations: I2CSubclass
•Progress Code Operations: Host Software Class
•Error Code Operations: Host Software Class
•Defined Subclasses: Host Software Class
•Progress and Error Code Operations: HostSoftware Unspecified Subclass
•Progress and Error Code Operations: SECSubclass
•Progress and Error Code Operations: PEIFoundation Subclass
•Progress and Error Code Operations: PEIModule Subclass
•Progress and Error Code Operations: DXEFoundation Subclass
•Progress and Error Code Operations: DXEBoot Service Driver Subclass
•Progress and Error Code Operations: DXERuntime Service Driver Subclass
•Progress and Error Code Operations: SMMDriver Subclass
•Progress and Error Code Operations: UEFIApplication Subclass
•Progress and Error Code Operations: OSLoader Subclass
•Progress and Error Code Operations: Runtime Subclass
•Progress and Error Code Operations: PEISubclass
III-iiiUEFI Platform Initialization Specification, Release 1.8
•Progress and Error Code Operations: BootServices Subclass
•Progress and Error Code Operations:Runtime Services Subclass
•Progress and Error Code Operations: DXEServices Subclass
•Progress Code Enumeration Scheme
•Decription of EFI_CPU_STATE_CHANGE_CAUSE fields
•Definitions to describe Group Operations
III-ivCHAPTER
ONE
III-1.1 Overview
This volume describes the basic concepts behind Platform Initialization (PI) firmware storage and Hand-Off Blocks
implementation.
The basic Platform Initialization (PI) firmware storage concepts include:
•Firmware Volumes
•Firmware File Systems
•Firmware Files
•Standard Binary Layout
•Pre-EFI Initialization (PEI) PEIM-to-PEIM Interfaces (PPIs)
•Driver Execution Environment (DXE) Protocols
The core code that is required for an implementation of Hand-Off Blocks (HOBs) in the Platform Initialization (PI)
Architecture specifications are also shown. A HOB is a binary data structure that passes system state information
from the HOB producer phase to the HOB consumer phase in the PI Architecture. This HOB specification does the
•Describes the basic components of HOBs and the rules for constructing them
•ProvidescodedefinitionsfortheHOBdatatypesandstructuresthatarearchitecturallyrequiredbythePIArchi-
tecture specifications
III-1.2 Target Audience
•Independenthardwarevendors(IHVs)andoriginalequipmentmanufacturers(OEMs)whowillbeimplementing
firmware components that are stored in firmware volumes
•Firmware developers who create firmware products or those who modify these products for use in platforms
III-1UEFI Platform Initialization Specification, Release 1.8
III-1.3 Conventions Used in this Document
III-1.3.1 Data Structure Descriptions
Summary
Prototype
III-1.3.2 Pseudo-Code Conventions

Summary
Prototype
III-1.3. Conventions Used in this Document III-2UEFI Platform Initialization Specification, Release 1.8
III-1.3.3 Typographic Conventions
Plain text
Bold
Italic
name.
III-1.3. Conventions Used in this Document III-3UEFI Platform Initialization Specification, Release 1.8
III-1.4 Conventions used in this document
III-1.4.1 Number formats
III-1.4. Conventions used in this document III-4UEFI Platform Initialization Specification, Release 1.8
III-1.4.2 Binary prefixes
Table 1.1: SI prefixes
Table 1.2: Binary prefixes
III-1.4. Conventions used in this document III-5CHAPTER
TWO
FIRMWARE STORAGE DESIGN DISCUSSION
III-2.1 Firmware Storage Introduction
Thisspecificationdescribeshowfilesshouldbestoredandaccessedwithinnon-volatilestorage. Firmwareimplemen-
tations must support the standard PI Firmware Volume and Firmware File System format (described below), but may
support additional storage formats.
III-2.1.1 Firmware Devices
Afirmwaredevice isapersistentphysicalrepositorythatcontainsfirmwarecodeand/ordata. Itistypicallyaflashcom-

TWO
ponentbutmaybesomeothertypeofpersistentstorage. Asinglephysicalfirmwaredevicemaybedividedintosmaller
piecestoformmultiplelogicalfirmwaredevices. Similarly,multiplephysicalfirmwaredevicesmaybeaggregatedinto
one larger logical firmware device.
This section describes the characteristics of typical physical firmware devices.
III-2.1.1.1 Flash
Flashdevicesarethemostcommonnon-volatilerepositoryforfirmwarevolumes. Flashdevicesareoftendividedinto
sectors (or blocks) of possibly differing sizes, each with different run-time characteristics. Flash devices have several
unique qualities that are reflected in the design of the firmware file system:
•Flash devices can be erased on a sector-by-sector basis. After an erasure, all bits within a sector return to their
erase value , either all 0 or all 1.
•Flashdevicescanbewrittenonabit-by-bitbasisifthechangeisfromitserasevaluetothenon-erasevalue. For
example, if the erase value is 1, then a bit with the value 1 can be changed to 0.
•Flash devices can only change from a non-erase value to an erase value by performing an erase operation on an
entire flash sector.
•Someflashdevicescanenableordisablereadsandwritestotheentireflashdeviceortoindividualflashsectors.
•Some flash devices can lock the current enable or disable state of reads and writes until the next reset.
•Flash writes and erases are often longer operations than reads.
•Flashdevicesoftenplacerestrictionsontheoperationsthatcanbeperformedwhileawriteoreraseisoccurring.
III-6UEFI Platform Initialization Specification, Release 1.8
III-2.1.2 Firmware Volumes
AFirmwareVolume(FV)isalogicalfirmwaredevice. Inthisspecification,thebasicstoragerepositoryfordataand/or
codeisthefirmwarevolume. Eachfirmwarevolumeisorganizedintoafilesystem. Assuch,thefileisthebaseunitof
storage for firmware.
Each firmware volume has the following attributes:
•Name. Each volume has a name consisting of an UEFI Globally Unique Identifier (GUID).
•Size. Each volume has a size, which describes the total size of all volume data, including any header, files, and
free space.
•Format. Each volume has a format, which describes the Firmware File System used in the body of the volume.
•Memory Mapped? Some volumes may be memory-mapped, which indicates that the entire contents of the
volume appear at once in the memory address space of the processor.
•StickyWrite? Somevolumesmayrequirespecialerasecyclesinordertochangebitsfromanon-erasevalueto
an erase value.
•Erase Polarity . If a volume supports “Sticky Write,” then all bits within the volume will return to this value (0
or 1) after an erase cycle.
•Alignment . Thefirstbyteofavolumeisrequiredtobealignedonsomepower-of-twoboundary. Ataminimum,
this must be greater than or equal to the highest file alignment value. If EFI_FVB2_WEAK_ALIGNMENT is set in
the volume header then the first byte of the volume can be aligned on any power-of-two boundary. A weakly
aligned volume can not be moved from its initial linked location and maintain its alignment.
•Read Enable/Disable Capable/Status . Volumes may have the ability to change from readable to hidden.
•Write Enable/Disable Capable/Status . Volumes may have the ability to change from writable to write pro-
tected.
•Lock Capable/Status. Volumes may be able to have their capabilities locked.
•Read-Lock Capable/Status . Volumes may have the ability to lock their read status.
•Write-Lock Capable/Status . Volumes may have the ability to lock their write status.
Firmware volumes may also contain additional information describing the mapping between OEM file types and a
GUID.
III-2.1.3 Firmware File System
Afirmwarefilesystem(FFS)describestheorganizationoffilesand(optionally)freespacewithinthefirmwarevolume.
EachfirmwarefilesystemhasauniqueGUID,whichisusedbythefirmwaretoassociateadriverwithanewlyexposed
The PI Firmware File System is described in Firmware File System Format .
III-2.1. Firmware Storage Introduction III-7UEFI Platform Initialization Specification, Release 1.8
III-2.1.4 Firmware Files
Firmware files are code and/or data stored in firmware volumes. Each of the files has the following attributes:
•Name. EachfilehasanameconsistingofanUEFIGUID.Filenamesmustbeuniquewithinafirmwarevolume.
Some file names have special significance.
•Type. Eachfilehasatype. Therearefourrangesoffiletypes: Normal(0x00-0xBF),OEM(0xC0-0xDF),Debug
(0xE0-0xEF) and Firmware Volume Specific (0xF0-0xFF). For more information on types, see Firmware File
Types.
•Alignment . Each file’s data can be aligned on some power-of-two boundary. The specific boundaries that are
supported depend on the alignment and format of the firmware volume. If EFI_FVB2_WEAK_ALIGNMENT is set
in the volume header then file alignment does not depend on volume alignment.
•Size. Each file’s data is zero or more bytes.
Specific firmware volume formats may support additional attributes, such as integrity verification and staged file cre-
ation. The file data of certain file types is sub-divided in a standardized fashion into Firmware File Sections .
Non-standard file types are supported through the use of the OEM file types. See Firmware File Types for more
In the PEI phase, file-related services are provided through the PEI Services Table, using FfsFindNextFile ,
FfsFindFileByName andFfsGetFileInfo . In the DXE phase, file-related services are provided through the
EFI_FIRMWARE_VOLUME2_PROTOCOL servicesattachedtoavolume’shandle( ReadFile ,ReadSection ,WriteFile
andGetNextFile ).
III-2.1.4.1 Firmware File Types
ConsideranapplicationfilenamedFOO.EXE.TheformatofthecontentsofFOO.EXEisimpliedbythe“.EXE”inthe
file name. Depending on the operating environment, this extension typically indicates that the contents of FOO.EXE
are a PE/COFF image and follow the PE/COFF image format.
Similarly, the PI Firmware File System defines the contents of a file that is returned by the firmware volume interface.
ThePIFirmwareFileSystemdefinesanenumerationoffiletypes. Forexample,thetype EFI_FV_FILETYPE_DRIVER
indicates that the file is a DXE driver and is interesting to the DXE Dispatcher. In the same way, files with the type
EFI_FV_FILETYPE_PEIM are interesting to the PEI Dispatcher.
III-2.1. Firmware Storage Introduction III-8UEFI Platform Initialization Specification, Release 1.8
Table 2.1: Defined File Types
EFI_FV_FILETYPE_RAW 0x01 Binary data
EFI_FV_FILETYPE_FREEFORM 0x02 Sectioned data
EFI_FV_FI LETYPE_SECURITY_CORE 0x03 Platform core code used during
the SEC phase
EFI_FV_FILETYPE_PEI_CORE 0x04 PEI Foundation
EFI_FV_FILETYPE_DXE_CORE 0x05 DXE Foundation
EFI_FV_FILETYPE_PEIM 0x06 PEI module PEIM
EFI_FV_FILETYPE_DRIVER 0x07 DXE driver
EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08 Combined PEIM DXE driver
EFI_FV_FILETYPE_APPLICATION 0x09 Application
EFI_FV_FILETYPE_MM 0x0A ContainsaPE32imagethatwill
beloadedintoMMRAMinMM
Traditional Mode
EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B Firmware volume image
EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C Contains PE32 image that will
be dispatched by the DXE Dis-
patcher and will also be loaded
into MMRAM in MM Tradition
Mode
EF I_FV_FILETYPE_MM_CORE 0x0D MM Foundation that support
MM Traditional Mode
EFI_FV_FILETYPE_MM_STANDALONE 0x0E ContainsaPE32imagethatwill
Standalone Mode
EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F MM Foundation that support
MM Tradition Mode and MM
EFI_FV _FILETYPE_OEM_MIN
EFI_FV_FILETYPE_OEM_MAX0xC0 0xDF OEM File Types
EFI_FV_FILETYPE_DEBUG_MIN
EFI_FV_FILETYPE_DEBUG_MAX0xE0 0xEF Debug Test File Types
EFI_FV_FILETYPE_FFS_MIN
EFI_FV_FILETYPE_FFS_MAX0xF0 0xFF Firmware File System Specific
File Types
EFI_FV_FILETYPE_FFS_PAD 0xF0 Pad File For FFS
III-2.1.4.1.1 EFI_FV_FILETYPE_APPLICATION
Thefiletype EFI_FV_FILETYPE_APPLICATION denotesafilethatcontainsaPE32imagethatcanbeloadedusingthe
UEFI Boot Service LoadImage() . Files of type EFI_FV_FILETYPE_APPLICATION are not dispatched by the DXE
Dispatcher.
This file type is a sectioned file that must be constructed in accordance with the following rule:
•Thefilemustcontainatleastone EFI_SECTION_PE32 section. Therearenorestrictionsonencapsulationofthis
section.
There are no restrictions on the encapsulation of the leaf section.
Intheeventthatmorethanone EFI_SECTION_PE32 sectionispresentinthefile,theselectionalgorithmforchoosing
which one represents the PE32 for the application in question is defined by the LoadImage() boot service. See the
Platform Initialization Driver Execution Environment Core Interface Specification for details.
III-2.1. Firmware Storage Introduction III-9UEFI Platform Initialization Specification, Release 1.8
The file may contain other leaf and encapsulation sections as required or enabled by the platform design.
III-2.1.4.1.2 EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER
The file type EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER denotes a file that contains code suitable for dispatch by
the PEI Dispatcher, as well as a PE32 image that can be dispatched by the DXE Dispatcher. It has two uses:

section.
•Enables sharing code between PEI and DXE to reduce firmware storage requirements.
•Enables bundling coupled PEIM/driver pairs in the same file.
Thisfiletypeisasectionedfileandmustfollowtheintersectionofallrulesdefinedforboth EFI_FV_FILETYPE_PEIM
andEFI_FV_FILETYPE_DRIVER files. This intersection is listed below:
•Thefilemustcontainoneandonlyone EFI_SECTION_PE32 section. Therearenorestrictionsonencapsulation
of this section; however, care must be taken to ensure any execute-in-place requirements are satisfied.
•The file must not contain more than one EFI_SECTION_DXE_DEPEX section.
•The file must not contain more than one EFI_SECTION_PEI_DEPEX section.
•The file must contain no more than one EFI_SECTION_VERSION section.
III-2.1.4.1.3 EFI_FV_FILETYPE_COMBINED_SMM_DXE
Thefiletype EFI_FV_FILETYPE_COMBINED_MM_DXE denotesafilethatcontainsaPE32+imagethatwillbedispatched
by the DXE Dispatcher and will also be loaded into MMRAM in MM Traditional Mode.
This file type is a sectioned file that must be constructed in accordance with the following rules:
section.
•The file must contain no more than one EFI_SECTION_DXE_DEPEX section. This section is ignored when the
file is loaded into SMRAM.
•Thefilemustcontainnomorethanone EFI_SECTION_MM_DEPEX section. Thissectionisignoredwhenthefile
is dispatched by the DXE Dispatcher.
Therearenorestrictionsontheencapsulationoftheleafsections. Intheeventthatmorethanone EFI_SECTION_PE32
section is present in the file, the selection algorithm for choosing which one represents the DXE driver that will be
dispatched is defined by the LoadImage() boot service, which is used by the DXE Dispatcher. See the Platform
InitializationSpecification,Volume2 fordetails. Thefilemaycontainotherleafandencapsulationsectionsasrequired
or enabled by the platform design.
III-2.1. Firmware Storage Introduction III-10UEFI Platform Initialization Specification, Release 1.8
III-2.1.4.1.4 EFI_FV_FILETYPE_DRIVER
Thefiletype EFI_FV_FILETYPE_DRIVER denotesafilethatcontainsaPE32imagethatcanbedispatchedbytheDXE
section.
•The file must contain no more than one EFI_SECTION_DXE_DEPEX section.
There are no restrictions on the encapsulation of the leaf sections.
whichonerepresentstheDXEdriverthatwillbedispatchedisdefinedbythe LoadImage() bootservice,whichisused
bytheDXEDispatcher. SeethePlatformInitialization DriverExecutionEnvironmentCoreInterfaceSpecification for
details.
III-2.1.4.1.5 EFI_FV_FILETYPE_DXE_CORE
The file type EFI_FV_FILETYPE_DXE_CORE denotes the DXE Foundation file. This image is the one entered upon
completion of the PEI phase of a UEFI boot cycle.
•The file must contain at least one and only one executable section, which must have a type of
EFI_SECTION_PE32 .
The sections that are described in the rules above may be optionally encapsulated in compression and/or additional
GUIDed sections as required by the platform design.
Aslongastheaboverulesarefollowed,thefilemaycontainotherleafandencapsulationsectionsasrequiredorenabled
by the platform design.
III-2.1.4.1.6 EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE
Thefiletype EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE denotesafilethatcontainsoneormorefirmwarevolume
images.
•The file must contain at least one section of type EFI_SECTION_FIRMWARE_VOLUME_IMAGE . There are no re-
strictions on encapsulation of this section.
III-2.1. Firmware Storage Introduction III-11UEFI Platform Initialization Specification, Release 1.8
III-2.1.4.1.7 EFI_FV_FILETYPE_FREEFORM
Thefiletype EFI_FV_FILETYPE_FREEFORM denotesasectionedfilethatmaycontainanycombinationofencapsulation
andleafsections. Whilethesectionlayoutcanbeparsed,theconsumerofthistypeoffilemusthaveaprioriknowledge
of how it is to be used.
Standardfirmwarefilesystemserviceswillnotreturnthehandleofanypadfiles,norwilltheypermitexplicitcreation
of such files. The Namefield of the EFI_FFS_FILE_HEADER andEFI_FFS_FILE_HEADER2 structures is considered
invalid for pad files and will not be used in any operation that requires name comparisons.
A single EFI_SECTION_FREEFORM_SUBTYPE_GUID section may be included in a file of type
EFI_FV_FILETYPE_FREEFORM to provide additional file type differentiation. While it is permissible to omit
theEFI_SECTION_FREEFORM_SUBTYPE_GUID section entirely, there must never be more than one instance of it.
III-2.1.4.1.8 EFI_FV_FILETYPE_FFS_PAD
A pad file is an FFS-defined file type that is used to pad the location of the file that follows it in the storage file. The
normalstateofanyvalid(notdeletedorinvalidated)fileisthatbothitsheaderanddataarevalid. Thisstatusisindicated
usingtheStatebitswithState= 00000111b . Padfilesdifferfromallothertypesoffilesinthatanypadfileinthis
state must not have any data written into the data space. It is essentially a file filled with free space.
of such files. The Namefield of the EFI_FFS_FILE_HEADER structure is considered invalid for pad files and will not
be used in any operation that requires name comparisons.
III-2.1.4.1.9 EFI_FV_FILETYPE_PEIM
Thefiletype EFI_FV_FILETYPE_PEIM denotesafilethatisaPEImodule(PEIM).APEImoduleisdispatchedbythe
PEI Foundation based on its dependencies during execution of the PEI phase. See the Platform Initialization Pre-EFI
Initialization Core Interface Specification for details on PEI operation.
•The file must contain one and only one executable section. This section must have one of the following types:
•EFI_SECTION_PE32
•EFI_SECTION_PIC
•EFI_SECTION_TE
•The file must contain no more than one EFI_SECTION_PEI_DEPEX section.
by the platform design. Care must be taken to ensure that additional encapsulations do not render the file inaccessible
due to execute-in-place requirements.
III-2.1. Firmware Storage Introduction III-12UEFI Platform Initialization Specification, Release 1.8
III-2.1.4.1.10 EFI_FV_FILETYPE_PEI_CORE
The file type EFI_FV_FILETYPE_PEI_CORE denotes the PEI Foundation file. This image is entered upon completion
of the SEC phase of a PI Architecture-compliant boot cycle.
As long as the above rules are followed, the file may contain other leaf and encapsulations as required/enabled by the
platform design.
III-2.1.4.1.11 EFI_FV_FILETYPE_RAW
Thefiletype EFI_FV_FILETYPE_RAW denotesafilethatdoesnotcontainsectionsandistreatedasarawdatafile. The
consumer of this type of file must have a priori knowledge of its format and content. Because there are no sections,
there are no construction rules.
III-2.1.4.1.12 EFI_FV_FILETYPE_SECURITY_CODE
Thefiletype EFI_FV_FILETYPE_SECURITY_CORE denotescodeanddatathatcomprisethefirstpartofPIArchitecture
firmwaretoexecute. ItsformatisundefinedwithrespecttothePIArchitecture,asdifferingplatformarchitecturesmay
have varied requirements.
III-2.1.4.1.13 EFI_FV_FILETYPE_MM
The file type EFI_FV_FILETYPE_MM denotes a file that contains a PE32+ image that will be loaded into MMRAM in
MM Tradition Mode.
section.
•The file must contain no more than one EFI_SECTION_MM_DEPEX section.

section.
InitializationSpecification,Volume2fordetails. Thefilemaycontainotherleafandencapsulationsectionsasrequired
III-2.1. Firmware Storage Introduction III-13UEFI Platform Initialization Specification, Release 1.8
III-2.1.4.1.14 EFI_FV_FILETYPE_MM_CORE
Thefiletype EFI_FV_FILETYPE_MM_CORE denotestheMMFoundationfilethatonlysupportsMMTraditionalMode.
This image will be loaded by MM IPL into MMRAM.
•Thefilemustcontainatleastoneandonlyoneexecutablesection,whichmusthaveatypeof EFI_SECTION_PE32
.
III-2.1.4.1.15 EFI_FV_FILETYPE_MM_STANDALONE
Thefiletype EFI_FV_FILETYPE_MM_STANDALONE denotesafilethatcontainsaPE32+imagethatwillbeloadedinto
SMRAM in SMM Standalone Mode.
section.
section is present in the file, the selection algorithm for choosing which one represents the MM driver that will be
dispatchedisdefinedbyMMFoundationDispatcher. Seethe PlatformInitializationSpecification,Volume4 fordetails.
III-2.1.4.1.16 EFI_FV_FILETYPE_MM_CORE_STANDALONE
The file type EFI_FV_FILETYPE_SMM_CORE_STANDALONE denotes the MM Foundation file that support MM Tradi-
tional Mode and MM Standalone Mode. This image will be loaded by standalone MM IPL into MMRAM.
III-2.1.5 Firmware File Sections
Firmwarefilesectionsareseparatediscrete“parts”withincertainfiletypes. Eachsectionhasthefollowingattributes:
•Type. Each section has a type. For more information on section types, see Firmware File Section Types .
•Size. Each section has a size.
While there are many types of sections, they fall into the following two broad categories:
•Encapsulation sections
•Leaf sections
III-2.1. Firmware Storage Introduction III-14UEFI Platform Initialization Specification, Release 1.8
Encapsulationsectionsareessentiallycontainersthatholdothersections. Thesectionscontainedwithinanencapsula-
tion section are known as childsections, and the encapsulation section is known as the parentsection. Encapsulation
sections may have many children. An encapsulation section’s children may be leaves and/or more encapsulation sec-
tions and are called peersrelative to each other. An encapsulation section does not contain data directly; instead it is
just a vessel that ultimately terminates in leaf sections.
Files that are built with sections can be thought of as a tree, with encapsulation sections as nodes and leaf sections as
theleaves. Thefileimageitselfcanbethoughtofastherootandmaycontainanarbitrarynumberofsections. Sections
that exist in the root have no parent section but are still considered peers.
Unlike encapsulation sections, leaf sections directly contain data and do not contain other sections. The format of the
data contained within a leaf section is defined by the type of the section.
Fig. 2.1: Example File Image (Graphical and TreeRepresentations)
In the example shown in Example File Image (Graphical and TreeRepresentations) , the file image root contains two
encapsulation sections (E0 and E1) and one leaf section (L3). The first encapsulation section (E0) contains chil-
dren, all of which are leaves (L0, L1, and L2). The second encapsulation section (E1) contains two children, one
that is an encapsulation (E2) and the other that is a leaf (L6). The last encapsulation section (E2) has two chil-
dren that are both leaves (L4 and L5) In the PEI phase, section-related services are provided through the PEI Ser-
vice Table, using FfsFindSectionData . In the DXE phase, section-related services are provided through the
EFI_FIRMWARE_VOLUME2_PROTOCOL services attached to a volume’s handle ( ReadSection ).
III-2.1. Firmware Storage Introduction III-15UEFI Platform Initialization Specification, Release 1.8
III-2.1.5.1 Firmware File Section Types
Architectural Section Types lists the defined architectural section types.
Table 2.2: Architectural Section Types
EFI_SECTION_COMPRESSION 0x01 Encapsulation section where
other sections are compressed
EFI_SECTION_GUID_DEFINED 0x02 Encapsulation section where
other sections have format
defined by a GUID
EFI_SECTION_DISPOSABLE 0x03 Encapsulation section used dur-
ing the build process but not re-
quired for execution
EFI_SECTION_PE32 0x10 PE32 Executable image
EFI_SECTION_PIC 0x11 Position Independent Code
EFI_SECTION_TE 0x12 Terse Executable image
EFI_SECTION_DXE_DEPEX 0x13 DXE Dependency Expression
EFI_SECTION_VERSION 0x14 Version Text and Numeric
EFI_SECTION_USER_INTERFACE 0x15 UserFriendlynameofthedriver
EFI_SECTION_COMPATIBILITY16 0x16 DOS style 16 bit EXE
EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 PI Firmware Volume image
EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 Raw data with GUID in header
to define format
EFI_SECTION_RAW 0x19 Raw data
EFI_SECTION_PEI_DEPEX 0x1b PEI Dependency Expression
EFI_SECTION_MM_DEPEX 0x1c Leaf section type for determin-
ingthedispatchorderforanMM
Traditional driver in MM Tradi-
tional Mode or MM Standaline
driver in MM Standalone Mode
III-2.2 PI Architecture Firmware File System Format
ThissectiondescribesthestandardbinaryencodingforPIFirmwareFiles,PIFirmwareVolumes,andthePIFirmware
File System. Implementations that allow the non-vendor firmware files or firmware volumes to be introduced into the
systemmustsupportthestandardformats. Thissectionalsodescribeshowfeaturesofthestandardformatmapintothe
standard PEI and DXE interfaces.
The standard firmware file and volume format also introduces additional attributes and capabilities that are used to
guarantee the integrity of the firmware volume. The standard format is broken into three levels: the firmware volume
format, the firmware file system format, and the firmware file format.
The standard firmware volume format ( The Firmware Volume Format ) consists of two parts: the firmware volume
headerandthefirmwarevolumedata. Thefirmwarevolumeheaderdescribesalloftheattributesspecifiedin Firmware
Volumes. TheheaderalsocontainsaGUIDwhichdescribestheformatofthefirmwarefilesystemusedtoorganizethe
firmwarevolumedata. ThefirmwarevolumeheadercansupportotherfirmwarefilesystemsotherthanthePIFirmware
File System.
The PI Firmware File System format describes how firmware files and free space are organized within the firmware
volume.
III-2.2. PI Architecture Firmware File System Format III-16UEFI Platform Initialization Specification, Release 1.8
Fig. 2.2: The Firmware Volume Format
The PI Firmware File format describes how files are organized. The firmware file format consists of two parts: the
firmware file header and the firmware file data.
III-2.2.1 Firmware Volume Format
The PI Architecture Firmware Volume format describes the binary layout of a firmware volume. The firmware vol-
ume format consists of a header followed by the firmware volume data. The firmware volume header is described by
EFI_FIRMWARE_VOLUME_HEADER .
The format of the firmware volume data is described by a GUID. Valid files system GUID values are
EFI_FIRMWARE_FILE_SYSTEM2_GUID andEFI_FIRMWARE_FILE_SYSTEM3_GUID .
III-2.2.2 Firmware File System Format
The PI Architecture Firmware File System is a binary layout of file storage within firmware volumes. It is a flat file
system in that there is no provision for any directory hierarchy; all files reside in the root directly. Files are stored end
to end without any directory entry to describe which files are present. Parsing the contents of a firmware volume to
obtain a listing of files present requires walking the firmware volume from beginning to end.
All files stored with the FFS must follow the PI Architecture Firmware File System Format . The standard file header
provides for several levels of integrity checking to help detect file corruption, should it occur for some reason. This
section describes:
•PI Architecture’s Firmware File System GUID (s)
•Volume Top File (VTF)

III-2.2.2.1 Firmware File System GUID
The PI Architecture firmware volume header contains a data field for the file system GUID. See `
EFI_FIRMWARE_VOLUME_HEADER <V3-Code-Definitions.htm#92285> `__ for more information on the firmware vol-
ume header. There are two valid FFS file system, the GUID is defined as `EFI_FIRMWARE_FILE_SYSTEM2_GUID
<V3-Code-Definitions.htm#29788> `__ andEFI_FIRMWARE_FILE_SYSTEM3_GUID .
If the FFS file system is backward compatible with EFI_FIRMWARE_FILE_SYSTEM2_GUID and supports files larger
than 16 MB then EFI_FIRMWARE_FILE_SYSTEM3_GUID is used.
III-2.2. PI Architecture Firmware File System Format III-17UEFI Platform Initialization Specification, Release 1.8
III-2.2.2.2 Volume Top File
A Volume Top File (VTF) is a file that must be located such that the last byte of the file is also the last
byte of the firmware volume. Regardless of the file type, a VTF must have the file name GUID of See
``EFI_FFS_VOLUME_TOP_FILE_GUID `<V3-Code-Definitions.htm#92833> `__.
Firmware file system driver code must be aware of this GUID and insert a pad file as necessary to guarantee the VTF
is located correctly at the top of the firmware volume on write and update operations. File length and alignment
requirements must be consistent with the top of volume. Otherwise, a write error occurs and the firmware volume is
not modified.
III-2.2.3 Firmware File Format
All FFS files begin with a header that is aligned on an 8-byteboundry with respect to the beginning of the firmware
volume. FFS files can contain the following parts:
•Header
•Data
It is possible to create a file that has only a header and no data, which consumes 24 bytes of space. This type of file is
known as a zero-length file.
If the file contains data, the data immediately follows the header. The format of the data within a file is defined by the
Typefield in the header, either EFI_FFS_FILE_HEADER orEFI_FFS_FILE_HEADER2 inFirmware File .
Typical FFS File Layout illustrates the layout of a (typical) PI Architecture Firmware File smallerthan 16 Mb:
Fig. 2.3: Typical FFS File Layout
Figure 4 illustrates the layout of a PI Architecture Firmware File largerthan 16 Mb:
III-2.2. PI Architecture Firmware File System Format III-18UEFI Platform Initialization Specification, Release 1.8
Fig. 2.4: File Header 2 layout for files larger than 16Mb
III-2.2.4 Firmware File Section Format
This section describes the standard firmware file section layout.
Each section begins with a section header, followed by data defined by the section type.
Thesectionheadersalignedon4byteboundariesrelativetothestartofthefile’simage. Ifpaddingisrequiredbetween
the end of one section and the beginning of the next to achieve the 4-byte alignment requirement, all padding bytes
must be initialized to zero.
Manysectiontypesarevariableinlengthandaremoreaccuratelydescribedasdatastreamsratherthandatastructures.
Regardless of section type, all section headers begin with a 24-bit integer indicating the section size, followed by an
8-bit section type. The format of the remainder of the section header and the section data is defined by the section
type. If the section size is 0xFFFFFF then the size is defined by a 32-bit integer that follows the 32-bit section header.
Figures 5 and 6 shows the general format of a section.
Fig. 2.5: Format of a section (below 16Mb)
III-2.2. PI Architecture Firmware File System Format III-19UEFI Platform Initialization Specification, Release 1.8
Fig. 2.6: Format of a section using the ExtendedLengthfield
III-2.2.5 File System Initialization
ThealgorithmbelowdescribesamethodofFFSinitializationthatensuresFFSfilecorruptioncanbedetectedregardless
of the cause.
TheStatebyteofeachfilemustbecorrectlymanagedtoensuretheintegrityofthefilesystemisnotcompromisedin
theeventofapowerfailureduringanyFFSoperation. ItisexpectedthatanFFSdriverwillproduceaninstanceofthe
Firmware Volume Protocol and that all normal file operations will take place in that context. All file operations must
follow all the creation, update, and deletion rules described in this specification to avoid file system corruption.
The following FvCheck() pseudo code must be executed during FFS initialization to avoid file system corruption. If
at any point a failure condition is reached, then the firmware volume is corrupted and a crisis recovery is initiated.All
FFS files, including files of type EFI_FV_FILETYPE_FFS_PAD must be evaluated during file system initialization. It
islegalformultiplepadfileswiththisfiletypetohavethesameNamefieldinthefileheader. Nochecksforduplicate
files should be performed on pad files.
// Firmware volume initialization entry point - returns TRUE
// if FFS driver can use this firmware volume.
BOOLEAN FvCheck(Fv)
{
// first check out firmware volume header
if (FvHeaderCheck(Fv) == FALSE) {
FAILURE();// corrupted firmware volume header
}
if (!((Fv->FvFileSystemId == EFI_FIRMWARE_FILE_SYSTEM2_GUID) || \
(Fv->FvFileSystemId == EFI_FIRMWARE_FILE_SYSTEM3_GUID))){
return (FALSE); // This firmware volume is not
// formatted with FFS
}
// next walk files and verify the FFS is in good shape
for (FilePtr = FirstFile; Exists(Fv, FilePtr);
FilePtr = NextFile(Fv, FilePtr)) {
if (FileCheck (Fv, FilePtr) != 0) {
FAILURE(); // inconsistent file system
}
}
if (CheckFreeSpace (Fv, FilePtr) != 0) {
FAILURE();
}
return (TRUE); // this firmware volume can be used by the FFS
III-2.2. PI Architecture Firmware File System Format III-20UEFI Platform Initialization Specification, Release 1.8
// driver and the file system is OK
}
// FvHeaderCheck - returns TRUE if FvHeader checksum is OK.
BOOLEAN FvHeaderCheck (Fv)
{
return (Checksum (Fv.FvHeader) == 0);
}
// Exists - returns TRUE if any bits are set in the file header
BOOLEAN Exists(Fv, FilePtr)
{
return (BufferErased (Fv.ErasePolarity,
FilePtr, sizeof (EFI_FIRMWARE_VOLUME_HEADER) == FALSE);
}
// BufferErased - returns TRUE if no bits are set in buffer
BOOLEAN BufferErased (ErasePolarity, BufferPtr, BufferSize)
{
if (Fv.ErasePolarity == 1) {
ErasedByte = 0xff;
} else {
ErasedByte = 0;
}
for (Count = 0; Count < BufferSize; Count++) {
if (BufferPtr[Count] != ErasedByte) {
return FALSE;
}
}
return TRUE;
}
// GetFileState - returns high bit set of state field.
UINT8 GetFileState (Fv, FilePtr) {
UINT8 FileState;
UINT8 HighBit;
FileState = FilePtr->State;
if (Fv.ErasePolarity != 0) {
FileState = ~FileState;
}
HighBit = 0x80;
while (HighBit != 0 && (HighBit & FileState) == 0) {
HighBit = HighBit >> 1;
}
return HighBit;
}
// FileCheck - returns TRUE if the file is OK
BOOLEAN FileCheck (Fv, FilePtr) {
switch (GetFileState (Fv, FilePtr)) {
case EFI_FILE_HEADER_CONSTRUCTION:
SetHeaderBit (Fv, FilePtr, EFI_FILE_HEADER_INVALID);
break;
case EFI_FILE_HEADER_VALID:
if (VerifyHeaderChecksum (FilePtr) != TRUE) {
return (FALSE);
III-2.2. PI Architecture Firmware File System Format III-21UEFI Platform Initialization Specification, Release 1.8
}
SetHeaderBit (Fv, FilePtr, EFI_FILE_DELETED);
Break;
case EFI_FILE_DATA_VALID:
}
if (VerifyFileChecksum (FilePtr) != TRUE) {
}
if (DuplicateFileExists (Fv, FilePtr,
EFI_FILE_DATA_VALID) != NULL) {
}
break;
case EFI_FILE_MARKED_FOR_UPDATE:
}
}
if (FilePtr->State & EFI_FILE_DATA_VALID) == 0) {
}
if (FilePtr->Type == EFI_FV_FILETYPE_FFS_PAD) {
}
else {
if (DuplicateFileExists (Fv, FilePtr, EFI_FILE_DATA_VALID)) {
}
else {
if (Fv->Attributes & EFI_FVB_STICKY_WRITE) {
CopyFile (Fv, FilePtr);
}
else {
ClearHeaderBit (Fv, FilePtr, EFI_FILE_MARKED_FOR_UPDATE);
}
}
}
break;
case EFI_FILE_DELETED:
}
}
break;
case EFI_FILE_HEADER_INVALID:
III-2.2. PI Architecture Firmware File System Format III-22UEFI Platform Initialization Specification, Release 1.8
break;
}
return (TRUE);
}
// FFS_FILE_PTR * DuplicateFileExists (Fv, FilePtr, StateBit)
// This function searches the firmware volume for another occurrence
// of the file described by FilePtr, in which the duplicate files
// high state bit that is set is defined by the parameter StateBit.
// It returns a pointer to a duplicate file if it exists and NULL
// if it does not. If the file type is EFI_FV_FILETYPE_FFS_PAD
// then NULL must be returned.
// CopyFile (Fv, FilePtr)
// The purpose of this function is to clear the
// EFI_FILE_MARKED_FOR_UPDATE bit from FilePtr->State
// in firmware volumes that have EFI_FVB_STICKY_WRITE == TRUE.

}
}
break;
break;
}
}
// The file is copied exactly header and all, except that the
// EFI_FILE_MARKED_FOR_UPDATE bit in the file header of the
// new file is clear.
// VerifyHeaderChecksum (FilePtr)
// The purpose of this function is to verify the file header
// sums to zero. See IntegrityCheck.Checksum.Header definition
// for details.
// VerifyFileChecksum (FilePtr)
// The purpose of this function is to verify the file integrity
// check. See IntegrityCheck.Checksum.File definition for details.
III-2.2.6 Traversal and Access to Files
TheSecurity(SEC),PEI,andearlyDXEcodemustbeabletotraversetheFFSandreadandexecutefilesbeforeawrite-
enabled DXE FFS driver is initialized. Because the FFS may have inconsistencies due to a previous power failure or
other system failure, it is necessary to follow a set of rules to verify the validity of files prior to using them. It is not
incumbent on SEC, PEI, or the early read-only DXE FFS services to make any attempt to recover or modify the file
system. If any situation exists where execution cannot continue due to file system inconsistencies, a recovery boot is
initiated.
There is one inconsistency that the SEC, PEI, and early DXE code can deal with without initiating a recovery boot.
Thisconditioniscreatedbyapowerfailureorothersystemfailurethatoccursduringafileupdateonapreviousboot.
SuchafailurewillcausetwofileswiththesamefilenameGUIDtoexistwithinthefirmwarevolume. Oneofthemwill
have theEFI_FILE_MARKED_FOR_UPDATE bit set in its Statefield but will be otherwise a completely valid file. The
other one may be in any state of construction up to and including EFI_FILE_DATA_VALID . All files used prior to the
initialization of the write-enabled DXE FFS driver must be screened with this test prior to their use. If this condition
is discovered, it is permissible to initiate a recovery boot and allow the recovery DXE to complete the update.
Thefollowingpseudocodedescribesthemethodfordeterminingwhichofthesetwofilestouse. Theinconsistencyis
corrected during the write-enabled initialization of the DXE FFS driver.
// Screen files to ensure we get the right one incase
// of an inconsistency.
FFS_FILE_PTR EarlyFfsUpdateCheck(FFS_FILE_PTR * FilePtr) {
FFS_FILE_PTR * FilePtr2;
if(VerifyHeaderChecksum (FilePtr) != TRUE) {
III-2.2. PI Architecture Firmware File System Format III-23UEFI Platform Initialization Specification, Release 1.8
return(FALSE);
}
if(VerifyFileChecksum (FilePtr) != TRUE) {
}
caseEFI_FILE_DATA_VALID:
return(FilePtr);
break;
caseEFI_FILE_MARKED_FOR_UPDATE:
FilePtr2 = DuplicateFileExists (Fv, FilePtr,
EFI_FILE_DATA_VALID);
if(FilePtr2 != NULL) {
}
}
return(FilePtr2);
}else{
}
break;
}
}
Note: There is no check for duplicate files once a file in the EFI_FILE_DATA_VALID state is located. The condition
wheretwofilesinasinglefirmwarevolumehavethesamefilenameGUIDandarebothinthe EFI_FILE_DATA_VALID
state cannot occur if the creation and update rules that are defined in this specification are followed.
III-2.2.7 File Integrity and State
File corruption, regardless of the cause, must be detectable so that appropriate file system repair steps may be taken.
File corruption can come from several sources but generally falls into three categories:
•General failure
•Erase failure
•Write failure
Ageneral failure is defined to be apparently random corruption of the storage media. This corruption can be caused
by storage media design problems or storage media degradation, for example. This type of failure can be as subtle as
changingasinglebitwithinthecontentsofafile. Withgoodsystemdesignandreliablestoragemedia,generalfailures
should not happen. Even so, the FFS enables detection of this type of failure.
Anerasefailure occurswhenablockeraseoffirmwarevolumemediaisnotcompletedduetoapowerfailureorother
systemfailure. Whiletheeraseoperationisnotdefined,itisexpectedthatmostimplementationsofFFSthatallowfile
write and delete operations will also implement a mechanism to reclaim deleted files and coalesce free space. If this
operation is not completed correctly, the file system can be left in an inconsistent state.
Similarly, a write failure occurs when a file system write is in progress and is not completed due to a power failure or
other system failure. This type of failure can leave the file system in an inconsistent state.
III-2.2. PI Architecture Firmware File System Format III-24UEFI Platform Initialization Specification, Release 1.8
AllofthesefailuresaredetectableduringFFSinitialization,and,dependingonthenatureofthefailure,manyrecovery
strategies are possible. Careful sequencing of the Statebits during normal file transitions is sufficient to enable
subsequent detection of write failures. However, the Statebits alone are not sufficient to detect all occurrences of
general and/or erase failures. These types of failures require additional support, which is enabled with the file header
IntegrityCheck field.
ForsamplecodethatprovidesamethodofFFSinitializationthatcandetectFFSfilecorruption,regardlessofthecause,
seeFile System Initialization .
III-2.2.8 File State Transitions
III-2.2.8.1 Overview
There are three basic operations that may be done with the FFS:
•Creating a file
•Deleting a file
•Updating a file
Allstatetransitionsmustbedonecarefullyatalltimestoensurethatapowerfailureneverresultsinacorruptedfirmware
volume. This transition is managed using the Statefield in the file header.
For the purposes of the examples below, positive decode logic is assumed ( EFI_FVB_ERASE_POLARITY = 0 ). In
actual use, the EFI_FVB_ERASE_POLARITY in the firmware volume header is referenced to determine the truth value
of all FFS Statebits. AllStatebit transitions must be atomic operations. Further, except when specifically noted,
onlythemostsignificant Statebitthatis TRUEhasmeaning. Lower-order Statebitsaresupersededbyhigher-order
Statebits.
TypeEFI_FVB_ERASE_POLARITY is defined in `EFI_FIRMWARE_VOLUME_HEADER . <V3-Code-
Definitions.htm#92285> `__.
III-2.2.8.2 Initial State
Theinitialconditionisthatof“freespace.”Allfreespaceinafirmwarevolumemustbeinitializedsuchthatallbitsin
thefreespacecontainthevalueof EFI_FVB_ERASE_POLARITY .Assuch,ifthefreespaceisinterpretedasanFFSfile
header,all StatebitsareFALSE.TypeEFI_FVB_ERASE_POLARITY isdefinedin `EFI_FIRMWARE_VOLUME_HEADER .
<V3-Code-Definitions.htm#92285> `__
III-2.2.8.3 Creating a File
A new file is created by allocating space from the firmware volume immediately beyond the end of the preceding file
(or the firmware volume header if the file is the first one in the firmware volume). Creating a File illustrates the steps
to create a new file, which are detailed below the figure.
As shown in Creating a File , the following steps are required to create a new file:
1. Allocate space in the firmware volume for a new file header, either EFI_FFS_FILE_HEADER , or
EFI_FFS_FILE_HEADER2 if the file is 16MB or more in size, and complete all fields of the header (except
for theStatefield, which is updated independently from the rest of the header). This allocation is done by
interpreting the free space as a file header and changing the EFI_FILE_HEADER_CONSTRUCTION bit toTRUE.
Thetransitionofthisbittothe TRUEstatemustbeatomicandfullycompletebeforeanyadditionalwritestothe
firmwarevolumearemade. Thistransitionyields State= 00000001b ,whichindicatestheheaderconstruction
has begun but has not yet been completed. This value has the effect of “claiming” the FFS header space from
the firmware volume free space.
III-2.2. PI Architecture Firmware File System Format III-25UEFI Platform Initialization Specification, Release 1.8
Fig. 2.7: Creating a File
While in this state, the following fields of the FFS header are initialized and written to the firmware volume:
•Name
•IntegrityCheck.Header
•Type
•Attributes
•Size
IfFFS_ATTRIB_LARGE_FILE is set in Attributes theSizefield of the FFS header must be zero and
ExtendedSize must contian the size of the FFS file.The value of IntegrityCheck.Header is calculated as
described in EFI_FFS_FILE_HEADER .
2. Mark the new header as complete and write the file data. To mark the header as complete, the
EFI_FILE_HEADER_VALID bit is changed to TRUE. The transition of this bit to the TRUEstate must be atomic
and fully complete before any additional writes to the firmware volume are made. This transition yields State
= 00000011b , which indicates the header construction is complete, but the file data has not yet been written.
Thisvaluehastheeffectof“claiming”thefulllengthofthefilefromthefirmwarevolumefreespace. Oncethe
EFI_FILE_HEADER_VALID bit is set, no further changes to the following fields may be made:
•Name
•Type
•Size

•Name
•Type
•Size
•Name
•Type
•Size
III-2.2. PI Architecture Firmware File System Format III-26UEFI Platform Initialization Specification, Release 1.8
While in this state, the file data and IntegrityCheck.File are written to the firmware vol-
ume. The order in which these are written does not matter. The calculation of the value for
IntegrityCheck.File is described in `EFI_FFS_FILE_HEADER Firmware Storage Code
Definitions .
3. Mark the data as valid. To mark the data as valid, the EFI_FILE_DATA_VALID bit is changed to TRUE. The
transition of this bit to the TRUEstate must be atomic and fully complete before any additional writes to the
firmware volume are made. This transition yields State = 00000111b , which indicates the file data is fully
written and is valid.
III-2.2.8.4 Deleting a File
Anyfilewith EFI_FILE_HEADER_VALID settoTRUEandEFI_FILE_HEADER_INVALID andEFI_FILE_DELETED set
toFALSEis a candidate for deletion.
Todeleteafile,the EFI_FILE_DELETED bitissettothe TRUEstate. Thetransitionofthisbittothe TRUEstatemustbe
atomicandfullycompletebeforeanyadditionalwritestothefirmwarevolumearemade. Thistransitionyields State
= 0001xx11b , which indicates the file is marked deleted. Its header is still valid, however, in as much as its length
field is used in locating the next file in the firmware volume.
Note: TheEFI_FILE_HEADER_INVALID bit must be left in the FALSEstate.
III-2.2.8.5 Updating a File
A file update is a special case of file creation where the file being added already exists in the firmware volume. At
all times during a file update, only one of the files, either the new one or the old one, is valid at any given time. This
validation is possible by using the EFI_FILE_MARKED_FOR_UPDATE bit in the old file.
Updating a File illustrates the steps to update a file, which are detailed below the figure.
Fig. 2.8: Updating a File
As shown in Updating a File , the following steps are required to update a file:
1. Set the EFI_FILE_MARKED_FOR_UPDATE bit toTRUEin the old file. The transition of this bit to the TRUEstate
mustbeatomicandfullycompletebeforeanyadditionalwritestothefirmwarevolumearemade. Thistransition
yieldsState = 00001111b , which indicates the file is marked for update. A file in this state remains valid as
long as no other file in the firmware volume has the same name and a Stateof000001xxb .
III-2.2. PI Architecture Firmware File System Format III-27UEFI Platform Initialization Specification, Release 1.8
2. CreatethenewfilefollowingthestepsdescribedinCreatingaFile. Whenthenewfilebecomesvalid,theoldfile
thatwasmarkedforupdatebecomesinvalid. Thatistosay,afilemarkedforupdateisvalidonlyaslongasthere
is no file with the same name in the firmware volume that has a Stateof000001xxb . In this way, only one of
thefiles,eitherthenewortheold,isvalidatanygiventime. Theactofwritingthe EFI_FILE_DATA_VALID bit
in the new file’s Statefield has the additional effect of invalidating the old file.
3. Delete the old file following the steps described in Deleting a File..
III-2.2. PI Architecture Firmware File System Format III-28CHAPTER
THREE
FIRMWARE STORAGE CODE DEFINITIONS
III-3.1 Firmware Storage Code Definitions Introduction
This section provides the code definitions for:
•The PI Architecture Firmware Storage binary formats for volumes, file system, files, and file sections.
•The PEI interfaces that support firmware volumes, firmware file systems, firmware files, and firmware file sec-
tions.
•The DXE protocols that support firmware volumes, firmware file systems, firmware files, and firmware file sec-
tions.
III-3.2 Firmware Storage Formats
III-3.2.1 Firmware Volume
III-3.2.1.1 EFI_FIRMWARE_VOLUME_HEADER
Summary
Describes the features and layout of the firmware volume.
Prototype
UINT8 ZeroVector[16];
EFI_GUID FileSystemGuid;
UINT64 FvLength;
UINT32 Signature;
EFI_FVB_ATTRIBUTES_2 Attributes;
UINT16 HeaderLength;
UINT16 ExtHeaderOffset;
UINT8 Reserved[1];
UINT8 Revision;
EFI_FV_BLOCK_MAP BlockMap[];
} EFI_FIRMWARE_VOLUME_HEADER;
III-29UEFI Platform Initialization Specification, Release 1.8
ZeroVector
The first 16 bytes are reserved to allow for the reset vector of processors whose reset vector is at address 0.
FileSystemGuid
Declares the file system with which the firmware volume is formatted. Type EFI_GUID is defined in
InstallProtocolInterface() intheUnifiedExtensibleFirmwareInterfaceSpecification ,version2.0(UEFI
2.0 specification).
FvLength
Length in bytes of the complete firmware volume, including the header.
Signature
Set to{'_','F','V','H'}.
Declares capabilities and power-on defaults for the firmware volume. Current state is determined using the
GetAttributes() function and is not maintained in the Attributes field of the firmware volume header.
TypeEFI_FVB_ATTRIBUTES_2 is defined in “Related Definitions” below.
HeaderLength
Length in bytes of the complete firmware volume header.
Checksum
A 16-bit checksum of the firmware volume header. A valid header sums to zero.
ExtHeaderOffset
Offset, relative to the start of the header, of the extended header ( EFI_FIRMWARE_VOLUME_EXT_HEADER ) or
zero if there is no extended header. The extended header is followed by zero or more variable length extension
entries. Each extension entry is prefixed with the EFI_FIRMWARE_VOLUME_EXT_ENTRY structure (see “Related
Definitions”below),whichdefinesthetypeandsizeoftheextensionentry. Theextendedheaderisalways32-bit
aligned relative to the start of the FIRMWARE VOLUME.
If there is an instance of the EFI_FIRMWARE_VOLUME_EXT_HEADER , then the firmware shall build an instance
of the Firmware Volume Media Device Path (ref Vol2, Section 8.2).
Reserved
In this version of the specification, this field must always be set to zero.
Revision
Set to 2. Future versions of this specification may define new header fields and will increment the Revision
field accordingly.
FvBlockMap[]
Anarrayofrun-lengthencoded FvBlockMapEntry structures. Thearrayisterminatedwithanentryof {0,0}.
FvBlockMapEntry.NumBlocks
The number of blocks in the run.
FvBlockMapEntry.BlockLength
The length of each block in the run.
Afirmwarevolumebasedonablockdevicebeginswithaheaderthatdescribesthefeaturesandlayoutofthefirmware
volume. This header includes a description of the capabilities, state, and block map of the device.
Theblockmapisarun-length-encodedarrayoflogicalblockdefinitions. Thisdesignallowsareasonablemechanism
of describing the block layout of typical firmware devices. Each block can be referenced by its logical block address
(LBA). The LBA is a zero-based enumeration of all of the blocks–i.e., LBA 0 is the first block, LBA 1 is the second
block, and LBA n is the (n-1) device.
The header is always located at the beginning of LBA 0.
III-3.2. Firmware Storage Formats III-30UEFI Platform Initialization Specification, Release 1.8
// EFI_FVB_ATTRIBUTES_2
typedef UINT32 EFI_FVB_ATTRIBUTES_2
// Attributes bit definitions
#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
#define EFI_FVB2_READ_STATUS 0x00000004
#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
#define EFI_FVB2_WRITE_STATUS 0x00000020
#define EFI_FVB2_LOCK_CAP 0x00000040
#define EFI_FVB2_LOCK_STATUS 0x00000080
#define EFI_FVB2_STICKY_WRITE 0x00000200
#define EFI_FVB2_MEMORY_MAPPED 0x00000400
#define EFI_FVB2_ERASE_POLARITY 0x00000800
#define EFI_FVB2_READ_LOCK_CAP 0x00001000
#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
#define EFI_FVB2_ALIGNMENT 0x001F0000
#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000
#define EFI_FVB2_ALIGNMENT_1 0x00000000
#define EFI_FVB2_ALIGNMENT_2 0x00010000
#define EFI_FVB2_ALIGNMENT_4 0x00020000
#define EFI_FVB2_ALIGNMENT_8 0x00030000
#define EFI_FVB2_ALIGNMENT_16 0x00040000
#define EFI_FVB2_ALIGNMENT_32 0x00050000
#define EFI_FVB2_ALIGNMENT_64 0x00060000
#define EFI_FVB2_ALIGNMENT_128 0x00070000
#define EFI_FVB2_ALIGNMENT_256 0x00080000
#define EFI_FVB2_ALIGNMENT_512 0x00090000
#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
#define EFI_FVB2_ALIGNMENT_64K 0x00100000
#define EFI_FVB2_ALIGNMENT_128K 0x00110000
#define EFI_FVB2_ALIGNMENT_256K 0x00120000
#define EFI_FVB2_ALIGNMENT_512K 0x00130000
#define EFI_FVB2_ALIGNMENT_1M 0x00140000
#define EFI_FVB2_ALIGNMENT_2M 0x00150000
III-3.2. Firmware Storage Formats III-31UEFI Platform Initialization Specification, Release 1.8
#define EFI_FVB2_ALIGNMENT_4M 0x00160000
#define EFI_FVB2_ALIGNMENT_8M 0x00170000
#define EFI_FVB2_ALIGNMENT_16M 0x00180000
#define EFI_FVB2_ALIGNMENT_32M 0x00190000
#define EFI_FVB2_ALIGNMENT_64M 0x001A0000

#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
Descriptions of EFI_FVB_ATTRIBUTES_2 describes the fields in the above definition:
Table 3.1: Descriptions of EFI_FVB_ATTRIBUTES_2
Attribute Description
EFI_FVB2_READ_DISABLED_CAP TRUEif reads from the firmware volume may be disabled.
EFI_FVB2_READ_ENABLED_CAP TRUEif reads from the firmware volume may be enabled.
EFI_FVB2_READ_STATUS TRUEif reads from the firmware volume are currently enabled.
EFI_FVB2_WRITE_DISABLED_CAP TRUEif writes to the firmware volume may be disabled.
EFI_FVB2_WRITE_ENABLED_CAP TRUEif writes to the firmware volume may be enabled.
EFI_FVB2_WRITE_STATUS TRUEif writes to the firmware volume are currently enabled.
EFI_FVB2_LOCK_CAP TRUEif firmware volume attributes may be locked down.
EFI_FVB2_LOCK_STATUS TRUEif firmware volume attributes are currently locked down.
EFI_FVB2_STICKY_WRITE TRUEif a block erase is required to transition bits from NOT
EFI_FVB2_ERASE_POLARITY toEFI_FVB2_ERASE_POLARITY .
That is, after erasure, a write may negate a bit in the
EFI_FVB2_ERASE_POLARITY state, but a write cannot flip
it back again. A block erase cycle is required to transi-
tion bits from the (NOT) EFI_FVB2_ERASE_POLARITY state
back to the EFI_FVB2_ERASE_POLARITY state. See the
EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL .
EFI_FVB2_MEMORY_MAPPED TRUEif firmware volume is memory mapped.
EFI_FVB2_ERASE_POLARITY Value of all bits after erasure. See the
EFI_FVB2_READ_LOCK_CAP TRUEif the firmware volume’s read-status can be locked.
EFI_FVB2_READ_LOCK_STATUS TRUEIf the firmware volume’s read-status is locked.
EFI_FVB2_WRITE_LOCK_CAP TRUEif the firmware volume’s write-status can be locked.
EFI_FVB2_WRITE_LOCK_STATUS TRUEif the firmware volume’s write-status is locked.
EFI_FVB2_ALIGNMENT The first byte of the firmware volume must be placed at an address
which is an even multiple of 2^( this field). For example, a value of
5 in this field would mean a required alignment of 32 bytes.
EFI_FVB2_WEAK_ALIGNMENT TRUEif the firmware volume can be less than the the highest file
alignment value.
All otherEFI_FVB_ATTRIBUTES_2 bits are reserved and must be zero.
UINT32 NumBlocks;
} EFI_FV_BLOCK_MAP;
NumBlocks
III-3.2. Firmware Storage Formats III-32UEFI Platform Initialization Specification, Release 1.8
The number of sequential blocks which are of the same size.
Length
The size of the blocks.
UINT32 ExtHeaderSize;
} EFI_FIRMWARE_VOLUME_EXT_HEADER;
FvName
Firmware volume name.
ExtHeaderSize
Size of the rest of the extension header, including this structure.
After the extension header, there is an array of variable-length extension header entries, each prefixed with the
EFI_FIRMWARE_VOLUME_EXT_ENTRY structure.
UINT16 ExtEntrySize;
UINT16 ExtEntryType;
} EFI_FIRMWARE_VOLUME_EXT_ENTRY;
ExtEntrySize
Size of this header extension.
ExtEntryType
Type of the header. See EFI_FV_EXT_TYPE_x .
#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
UINT32 TypeMask;
//EFI_GUID Types[];
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;
Hdr
Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE .
TypeMask
Abitmask,onebitforeachfiletypebetween0xC0(bit0)and0xDF(bit31). Ifabitis‘1’,thentheGUIDentry
existsinTypes. Ifabitis‘0’thennoGUIDentryexistsin Types. Forexample,thevalue0x01010301would
indicate that there would be five total entries in Typesfor file types 0xC0 (bit 0), 0xC8 (bit 4), 0xC9 (bit 5),
0xD0 (bit 16), and 0xD8 (bit 24).
Types
An array of GUIDs, each GUID representing an OEM file type.
This extension header provides a mapping between a GUID and an OEM file type.
#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
EFI_GUID FormatType;
//UINT8 Data[];
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
III-3.2. Firmware Storage Formats III-33UEFI Platform Initialization Specification, Release 1.8
Hdr
FormatType
Vendor-specific GUID
Length
Length of the data following this field
Data
An array of bytes of length Length.
This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor-specific GUID
FormatType type which includes a length and a successive series of data bytes. Values 0x00, 0x03..0xffff are
reserved by the specification.
#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03
UINT32 UsedSize;
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE;
Hdr
Standard extension entry, with the type EFI_FV_EXT_TYPE_USED_SIZE_TYPE .
UsedSize
The number of bytes of the FV that are in uses. The remaining EFI_FIRMWARE_VOLUME_HEADER FvLength
minus UsedSize bytes in the FV must contain the value implied by EFI_FVB2_ERASE_POLARITY .
TheEFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE can be used to find out how many
EFI_FVB2_ERASE_POLARITY bytes are at the end of the FV.
III-3.2.1.2 EFI Signed Firmware Volumes
There may be one or more headers with a FormatType of valueEFI_FIRMWARE_CONTENTS_SIGNED_GUID .
Asigned firmware volume is a cryptographic signature across the entire volume. To process the contents
and verify the integrity of the volume, the EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE Data[] shall con-
tain an instance of WIN_CERTIFICATE_UEFI_GUID where the CertType = EFI_CERT_TYPE_PKCS7_GUID or
EFI_CERT_TYPE_RSA2048_SHA256_GUID .
III-3.2.2 Firmware File System
III-3.2.2.1 EFI_FIRMWARE_FILE_SYSTEM2_GUID
Summary
The firmware volume header contains a data field for the file system GUID. See the
EFI_FIRMWARE_VOLUME_HEADER for more information on the firmware volume header.
GUID
// {8C8CE578-8A3D-4f1c-9935-896185C32DD3}
#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \
{ 0x8c8ce578, 0x8a3d, 0x4f1c, \
0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 }
III-3.2. Firmware Storage Formats III-34UEFI Platform Initialization Specification, Release 1.8
III-3.2.2.2 EFI_FIRMWARE_FILE_SYSTEM3_GUID
Summary
EFI_FIRMWARE_FILE_SYSTEM3_GUID indicates support for FFS_ATTRIB_LARGE_SIZE and thus support for files
16MBorlarger. EFI_FIRMWARE_FILE_SYSTEM2_GUID volumedoesnotcontainlargefiles. Files16MBorlargeruse
aEFI_FFS_FILE_HEADER2 and smaller files use EFI_FFS_FILE_HEADER. EFI_FIRMWARE_FILE_SYSTEM2_GUID
allows backward compatibility with previous versions of this specification
GUID
// {5473C07A-3DCB-4dca-BD6F-1E9689E7349A}
#define EFI_FIRMWARE_FILE_SYSTEM3_GUID \
{ 0x5473c07a, 0x3dcb, 0x4dca, \
{ 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a } }
III-3.2.2.3 EFI_FFS_VOLUME_TOP_FILE_GUID
Summary
AVolumeTopFile(VTF)isafilethatmustbelocatedsuchthatthelastbyteofthefileisalsothelastbyteofthefirmware
volume. Regardless of the file type, a VTF must have the file name GUID of EFI_FFS_VOLUME_TOP_FILE_GUID as
defined below.
GUID
// {1BA0062E-C779-4582-8566-336AE8F78F09}
#define EFI_FFS_VOLUME_TOP_FILE_GUID \
{ 0x1BA0062E, 0xC779, 0x4582, 0x85, 0x66, 0x33, 0x6A, \
0xE8, 0xF7, 0x8F, 0x9 }
III-3.2.3 Firmware File
III-3.2.3.1 EFI_FFS_FILE_HEADER
Summary
Eachfilebeginswithaheaderthatdescribesthestateandcontentsofthefile. Theheaderis8-bytealignedwithrespect
to the beginning of the firmware volume.
Prototype
EFI_GUID Name;
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
EFI_FV_FILETYPE Type;
EFI_FFS_FILE_ATTRIBUTES Attributes;
UINT8 Size[3];
EFI_FFS_FILE_STATE State;
} EFI_FFS_FILE_HEADER;
III-3.2. Firmware Storage Formats III-35UEFI Platform Initialization Specification, Release 1.8
UINT64 ExtendedSize;
} EFI_FFS_FILE_HEADER2;
Name
ThisGUIDisthefilename. Itisusedtouniquelyidentifythefile. Theremaybeonlyoneinstanceofafilewith
thefilenameGUIDof Nameinanygivenfirmwarevolume,exceptifthefiletypeis EFI_FV_FILETYPE_FFS_PAD
.
IntegrityCheck
Used to verify the integrity of the file. Type EFI_FFS_INTEGRITY_CHECK is defined in “Related Definitions”
below.
Type
Identifies the type of file. Type EFI_FV_FILETYPE is defined in “Related Definitions,” below. FFS-specific file
types are defined in EFI_FV_FILETYPE_FFS_PAD .
Declaresvariousfileattributebits. Type EFI_FFS_FILE_ATTRIBUTES isdefinedin“RelatedDefinitions”below.
Size
The length of the file in bytes, including the FFS header. The length of the file data is either ( Size -
sizeof(EFI_FFS_FILE_HEADER)) .Thiscalculationmeansazero-lengthfilehasa Sizeof24bytes,whichis
sizeof(EFI_FFS_FILE_HEADER) .

Name
.
below.
Type
Size
Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is located at the next 8-byte
aligned firmware volume offset following the last byte of the file F.
State
Used to track the state of the file throughout the life of the file from creation to deletion. Type
EFI_FFS_FILE_STATE isdefinedin“RelatedDefinitions”below. See FileIntegrityandState foranexplanation
of how these bits are used.
ExtendedSize
IfFFS_ATTRIB_LARGE_FILE is set inAttributes thenExtendedSize exists and Sizemust be set to zero.
IfFFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.
The file header may use one of two structures to define the file. If the size of the file is larger than 0xFFFFFF the
EFI_FFS_FILE_HEADER2 structuremustbeused,otherwisethe EFI_FFS_FILE_HEADER structuremustbeused. The
structure used is determined by the FFS_ATTRIB_LARGE_FILE attribute in the Attributes member. Note that all of
the structure elements other than ExtendedSize are the same in the two structures. The ExtendedSize member is
usedinsteadoftheSizememberwhenthe EFI_FFS_FILE_HEADER2 structureisused( FFS_ATTRIB_LARGE_FILE is
set).
III-3.2. Firmware Storage Formats III-36UEFI Platform Initialization Specification, Release 1.8
// EFI_FFS_INTEGRITY_CHECK
struct {
UINT8 Header;
UINT8 File;
} Checksum;
UINT16 Checksum16;
} EFI_FFS_INTEGRITY_CHECK;
Header
TheIntegrityCheck.Checksum.Header field is an 8-bit checksum of the file header. The Stateand
IntegrityCheck.Checksum.File fields are assumed to be zero and the checksum is calculated such
that the entire header sums to zero. The IntegrityCheck.Checksum.Header field is valid anytime
theEFI_FILE_HEADER_VALID bit is set in the Statefield. See File Integrity and State for more de-
tails. If the FFS_ATTRIB_LARGE_FILE bit of the Attributes field is set the header size is sizeof (
EFI_FFS_FILE_HEADER2 ), if it is clear the header size is sizeof ( EFI_FFS_FILE_HEADER ).
File
If theFFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes field is set to one, the
IntegrityCheck.Checksum.File fieldisan8-bitchecksumofthefiledata. Ifthe FFS_ATTRIB_CHECKSUM bit
oftheAttributes fieldisclearedtozero,the IntegrityCheck.Checksum.File fieldmustbeinitializedwith
a value of 0xAA. The IntegrityCheck.Checksum.File field is valid any time the EFI_FILE_DATA_VALID
bit is set in the Statefield. See File Integrity and State for more details.
Checksum
IntegrityCheck.Checksum16 is the full 16 bits of the IntegrityCheck field.
// EFI_FV_FILETYPE
typedef UINT8 EFI_FV_FILETYPE;
// EFI_FFS_FILE_ATTRIBUTES
typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
// FFS File Attributes
#define FFS_ATTRIB_LARGE_FILE 0x01
#define FFS_ATTRIB_FIXED 0x04
#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
#define FFS_ATTRIB_CHECKSUM 0x40
Bit Allocation of FFS Attributes depicts the bit allocation of the Attributes field in an FFS file’s header.
Bit Allocation Definitions provides descriptions of the fields in the above definition.
III-3.2. Firmware Storage Formats III-37UEFI Platform Initialization Specification, Release 1.8
Fig. 3.1: Bit Allocation of FFS Attributes
Table 3.2: Bit Allocation Definitions
Value Definition
FFS_ATTRIB_FIXED Indicates that the file may not be moved from its present location.
FFS_ATTRIB_LARGE_FILE Indicates that large files are supported and the
EFI_FFS_FILE_HEADER2 is in use.
FFS_ATTRIB_DATA_ALIGNMENT and
FFS_ATTRIB_DATA_ALIGNMENT2Indicatesthatthebeginningofthefiledata(notthefileheader)must
be aligned on a particular boundary relative to the firmware vol-
ume base. The three bits in this field are an enumeration of align-
mentpossibilities. Thefirmwarevolumeinterfaceallowsalignments
based on powers of two from byte alignment to 16MiB alignment.
FFS does not support this full range. The table below maps all
FFS supported alignments to FFS_ATTRIB_DATA_ALIGNMENT and
FFS_ATTRIB_DATA_ALIGNMENT2 values and firmware volume in-
terfacealignmentvalues. NootheralignmentsaresupportedbyFFS.
Whenafilewithanalignmentrequirementiscreated,apadfilemay
need to be created before it to ensure proper data alignment. See
EFI_FV_FILETYPE_FFS_PAD formoreinformationregardingpad
files
FFS_ATTRIB_CHECKSUM Determines the interpretation of IntegrityCheck.Checksum.
File. SeetheIntegrityCheck definitionaboveforspecificusage.
Supported FFS Alignments maps all FFS-supported alignments to FFS_ATTRIB_DATA_ALIGNMENT and
FFS_ATTRIB_DATA_ALIGNMENT2 values and firmware volume interface alignment values.
III-3.2. Firmware Storage Formats III-38UEFI Platform Initialization Specification, Release 1.8
Table 3.3: Supported FFS Alignments
Required
Alignment
(bytes)AlignmentValue in
FFS Attributes
FieldFFS_ATTRIB_DATA _ALIGN-
MENT2 in FFS Attributes FieldAlignment Value in
Firmware Volume Inter-
faces
1 0 0 0
16 1 0 4
128 2 0 7
512 3 0 9
1KiB 4 0 10
4KiB 5 0 12
32KiB 6 0 15
64KiB 7 0 16
128KiB 0 1 17
256KiB 1 1 18
512KiB 2 1 19
1MiB 3 1 20
2MiB 4 1 21
4MiB 5 1 22
8MiB 6 1 23
16MiB 7 1 24
// EFI_FFS_FILE_STATE
typedef UINT8 EFI_FFS_FILE_STATE;
// FFS File State Bits
#define EFI_FILE_HEADER_CONSTRUCTION 0x01
#define EFI_FILE_HEADER_VALID 0x02
#define EFI_FILE_DATA_VALID 0x04
#define EFI_FILE_MARKED_FOR_UPDATE 0x08
#define EFI_FILE_DELETED 0x10
#define EFI_FILE_HEADER_INVALID 0x20
All other Statebits are reserved and must be set to EFI_FVB_ERASE_POLARITY . SeeFile Integrity
and State for an explanation of how these bits are used. Type EFI_FVB_ERASE_POLARITY is defined in
EFI_FIRMWARE_VOLUME_HEADER.
III-3.2.4 Firmware File Section
III-3.2.4.1 EFI_COMMON_SECTION_HEADER
Summary
Defines the common header for all the section types.
Prototype
EFI_SECTION_TYPE Type;
III-3.2. Firmware Storage Formats III-39UEFI Platform Initialization Specification, Release 1.8
} EFI_COMMON_SECTION_HEADER;
UINT32 ExtendedSize;
} EFI_COMMON_SECTION_HEADER2;
Size
A 24-bit unsigned integer that contains the total size of the section in bytes, including the
EFI_COMMON_SECTION_HEADER . For example, a zero-length section has a Sizeof 4 bytes.
Type
Declares the section type. Type EFI_SECTION_TYPE is defined in “Related Definitions” below.
IfSizeis 0xFFFFFF then ExtendedSize contains the size of the section. If Sizeis not equal to 0xFFFFFF
then this field does not exist.
The typeEFI_COMMON_SECTION_HEADER defines the common header for all the section types.
IfSizeis0xFFFFFFthesizeofthesectionheaderissizeof( EFI_COMMON_SECTION_HEADER2 ). IfSizeisnotequal
to 0xFFFFFF then the size of the section header is sizeof ( EFI_COMMON_SECTION_HEADER ).
TheEFI_COMMON_SECTION_HEADER2 structure is only used if the section is too large to be described using
EFI_COMMON_SECTION_HEADER .Largesectionsusing EFI_COMMON_SECTION_HEADER2 canonlyexistinafileusing
EFI_FFS_FILE_HEADER2 , theFFS_ATTRIB_LARGE_FILE attribute in the file header is set.
// EFI_SECTION_TYPE
typedef UINT8 EFI_SECTION_TYPE;
// The section type EFI_SECTION_ALL isa pseudo type. It is
// used asa wild card when retrieving sections. The section
// type EFI_SECTION_ALL matches all section types.
#define EFI_SECTION_ALL 0x00
// Encapsulation section Type values
#define EFI_SECTION_COMPRESSION 0x01
#define EFI_SECTION_GUID_DEFINED 0x02
#define EFI_SECTION_DISPOSABLE 0x03
// Leaf section Type values
III-3.2. Firmware Storage Formats III-40UEFI Platform Initialization Specification, Release 1.8
#define EFI_SECTION_PE32 0x10
#define EFI_SECTION_PIC 0x11
#define EFI_SECTION_TE 0x12
#define EFI_SECTION_DXE_DEPEX 0x13
#define EFI_SECTION_VERSION 0x14
#define EFI_SECTION_USER_INTERFACE 0x15
#define EFI_SECTION_COMPATIBILITY16 0x16
#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
#define EFI_SECTION_RAW 0x19
#define EFI_SECTION_PEI_DEPEX 0x1B

#define EFI_SECTION_MM_DEPEX 0x1C
All other values are reserved for future use.
III-3.2.5 Firmware File Section Types
III-3.2.5.1 EFI_SECTION_COMPATIBILITY16
Summary
A leaf section type that contains an IA-32 16-bit executable image.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2;
ACompatibility16 image section is a leaf section that contains an IA-32 16-bit executable image. IA-32
16-bit legacy code that may be included in PI Architecture firmware is stored in a 16-bit executable image.
EFI_COMPATIBILITY16_SECTION2 is used if the section is 16MB or larger.
III-3.2.5.2 EFI_SECTION_COMPRESSION
Summary
An encapsulation section type in which the section data is compressed.
Prototype
EFI_COMMON_SECTION_HEADER CommonHeader;
UINT32 UncompressedLength;
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION;
EFI_COMMON_SECTION_HEADER2 CommonHeader;
} EFI_COMPRESSION_SECTION2;
III-3.2. Firmware Storage Formats III-41UEFI Platform Initialization Specification, Release 1.8
CommonHeader
Usual common section header. CommonHeader.Type =EFI_SECTION_COMPRESSION .
UncompressedLength
UINT32that indicates the size of the section data after decompression.
CompressionType
Indicates which compression algorithm is used.
Acompression section is an encapsulation section in which the section data is compressed. To process the con-
tents and extract the enclosed section stream, the section data must be decompressed using the decompressor in-
dicated by the CompressionType parameter. The decompressed image is then interpreted as a section stream.
EFI_COMPRESSION_SECTION2 is used if the section is 16MB or larger.
// CompressionType values
#define EFI_NOT_COMPRESSED 0x00
#define EFI_STANDARD_COMPRESSION 0x01
Description of Fields for CompressionType describes the fields in the above definition.
Table 3.4: Description of Fields for CompressionType
EFI_NOT_COMPRESSED Indicates that the encapsulated section stream is not compressed.
Thistypeisusefultogroupingsectionstogetherwithoutrequiringa
decompressor.
EFI_STANDARD_COMPRESSION Indicates that the encapsulated section stream is compressed using
the compression standard defined by the UEFI 2.0 specification.
III-3.2.5.3 EFI_SECTION_DISPOSABLE
Summary
An encapsulation section type in which the section data is disposable.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
None
A disposable section is an encapsulation section in which the section data may be disposed of during the process of
creating or updating a firmware image without significant impact on the usefulness of the file. The Typefield in the
section header is set to EFI_SECTION_DISPOSABLE . This allows optional or descriptive data to be included with the
firmwarefilewhichcanberemovedinordertoconservespace. Thecontentsofthissectionareimplementationspecific,
III-3.2. Firmware Storage Formats III-42UEFI Platform Initialization Specification, Release 1.8
but might contain debug data or detailed integration instructions. EFI_DISPOSABLE_SECTION2 is used if the section
is 16MB or larger.
III-3.2.5.4 EFI_SECTION_DXE_DEPEX
Summary
A leaf section type that is used to determine the dispatch order for a DXE driver.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
TheDXEdependencyexpressionsection isaleafsectionthatcontainsadependencyexpressionthatisusedtodetermine
the dispatch order for a DXE driver. See the Platform Initialization Driver Execution Environment Core Interface
Specification for details regarding the format of the dependency expression. EFI_DXE_DEPEX_SECTION2 must be
used if the section is 16MB or larger.
III-3.2.5.5 EFI_SECTION_FIRMWARE_VOLUME_IMAGE
Summary
A leaf section type that contains a PI Firmware Volume.
Prototype
typedef EFI_COMMON_SECTION_HEADER
EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2
EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
Afirmware volume image section is a leaf section that contains a PI Firmware Volume Image.
EFI_FIRMWARE_VOLUME_IMAGE_SECTION2 must be used if the section is 16MB or larger.
III-3.2.5.6 EFI_SECTION_FREEFORM_SUBTYPE_GUID
Summary
A leaf section type that contains a single EFI_GUID in the header to describe the raw data.
Prototype
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION;
III-3.2. Firmware Storage Formats III-43UEFI Platform Initialization Specification, Release 1.8
} EFI_FREEFORM_SUBTYPE_GUID_SECTION2;
Common section header. CommonHeader.Type =EFI_SECTION_FREEFORM_SUBTYPE_GUID .
SubtypeGuid
This GUID is defined by the creator of the file. It is a vendor-defined file type. Type EFI_GUID is defined in
Afree-form subtype GUID section is a leaf section that contains a single EFI_GUID in the header to describe the raw
data. It is typically used in files of type EFI_FV_FILETYPE_FREEFORM to provide an extensibility mechanism for file
types. The section can also be used in other file types as an alternative to raw section(EFI_SECTION_RAW) as it
providestheabilitytotagsectionwithauniqueGUID.SeeEFI_FV_FILETYPE_FREEFORMformoredetailsabout
EFI_FV_FILETYPE_FREEFORM files.
III-3.2.5.7 EFI_SECTION_GUID_DEFINED
Summary
An encapsulation section type in which the method of encapsulation is defined by an identifying GUID.
Prototype
EFI_GUID SectionDefinitionGuid;
UINT16 DataOffset;
UINT16 Attributes;
// GuidSpecificHeaderFields;
} EFI_GUID_DEFINED_SECTION;
} EFI_GUID_DEFINED_SECTION2;
Common section header. CommonHeader.Type =EFI_SECTION_GUID_DEFINED.
SectionDefinitionGuid
GUID that defines the format of the data that follows. It is a vendor-defined section type. Type EFI_GUID is
defined in InstallProtocolInterface() in the UEFI 2.0 specification.
DataOffset
Contains the offset in bytes from the beginning of the common header to the first byte of the data.
III-3.2. Firmware Storage Formats III-44UEFI Platform Initialization Specification, Release 1.8
Bit field that declares some specific characteristics of the section contents. The bits are defined in “Related
GuidSpecificHeaderFields
Zero or more bytes of data that are defined by the section’s GUID. An example of this data would be a digital
signature and manifest.
Data
Zero or more bytes of arbitrary data. The format of the data is defined by SectionDefinitionGuid .
AGUID-defined section contains a section-type-specific header that contains an identifying GUID, followed
by an arbitrary amount of data. It is an encapsulation section in which the method of encapsulation
is defined by the GUID. A matching instance of EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL (DXE) or
EFI_GUIDED_SECTION_EXTRACTION_PPI (PEI) is required to extract the contents of this encapsulation section.
The GUID-defined section enables custom encapsulation section types for any purpose. One commonly ex-
pected use is creating an encapsulation section to enable a cryptographic authentication of the section contents.
EFI_GUID_DEFINED_SECTION2 must be used if the section is 16MB or larger.
// Bit values forGuidedSectionHeader.Attributes
#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01
#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02
Descriptions of Fields for GuidedSectionHeader.Attributes describes the fields in the above definition.
Table 3.5: Descriptions of Fields for GuidedSectionHeader.
EFI_GUIDED_SECTION _PROCESS-
ING_REQUIREDSet to 1 if the section requires processing to obtain meaning-
ful data from the section contents. Processing would be re-
quired, for example, if the section contents were encrypted or com-
pressed. If the EFI_GUIDED_SECTION_PROCESSING_REQUIRED
bit is cleared to zero, it is possible to retrieve the section’s con-
tents without processing in the absence of an associated instance
of theEFI_GUIDED_SECTION_EXTRACTION_PROTOCOL (DXE) or
EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI (PEI).Inthiscase,

thebeginningoftheencapsulatedsectionstreamisindicatedbythe
value ofDataOffset .
EFI_GUIDED_SECTION_AUTH _ STA-
TUS_VALIDSet to 1 if the section contains authentication data that is re-
ported through the AuthenticationStatus parameter returned
from the GUIDed Section Extraction Protocol . If the
EFI_GUIDED_SECTION_AUTH_STATUS_VALID bit is clear, the
AuthenticationStatus parameter is not used.
All other bits are reserved and must be set to zero. Together, the EFI_GUIDED_SECTION_PROCESSING_REQUIRED
andEFI_GUIDED_SECTION_AUTH_STATUS_VALID bits provide the necessary data to set the proper bits of the
AuthenticationStatus output parameter in the event that no EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL is
available and the data is still returned.
EFI Signed Sections
III-3.2. Firmware Storage Formats III-45UEFI Platform Initialization Specification, Release 1.8
ForEFI_GUID_DEFINED_SECTION andEFI_GUID_DEFINED_SECTION2 there is a SectionDefinitionGuid
of typeEFI_FIRMWARE_CONTENTS_SIGNED_GUID . TheGuidSpecificHeaderFields shall include an entry
SignatureInfo of typeWIN_CERTIFICATE_UEFI_GUID .
#define EFI_FIRMWARE_CONTENTS_SIGNED_GUID \
| { 0xf9d89e8, 0x9259, 0x4f76, \
| { 0xa5, 0xaf, 0xc, 0x89, 0xe3, 0x40, 0x23, 0xdf } }
Thesigned section is an encapsulation section in which the section data is cryptographically signed. To
process the contents and extract the enclosed section stream, the section data integrity must be accessed by
evaluating the enclosed data via the cryptographic information in the SignatureInfo . TheCertType =
EFI_CERT_TYPE_PKCS7_GUID orEFI_CERT_TYPE_RSA2048_SHA256_GUID . The signed image is then interpreted
as a section stream. EFI_GUID_DEFINED_SECTION2 is used if the section is 16MB or larger.
III-3.2.5.8 EFI_SECTION_PE32
Summary
A leaf section type that contains a complete PE32+ image.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
ThePE32+imagesection isaleafsectionthatcontainsacompletePE32+image. NormalUEFIexecutablesarestored
within PE32+ images. EFI_PE32_SECTION2 must be used if the section is 16MB or larger.
III-3.2.5.9 EFI_SECTION_PEI_DEPEX
Summary
A leaf section type that is used to determine dispatch order for a PEIM.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
ThePEIdependencyexpressionsection isaleafsectionthatcontainsadependencyexpressionthatisusedtodetermine
dispatchorderforaPEIM.SeethePlatformInitialization Pre-EFIInitializationCoreInterfaceSpecification fordetails
regarding theformat ofthe dependencyexpression. EFI_PEI_DEPEX_SECTION2 must beused ifthe sectionis 16MB
or larger.
III-3.2. Firmware Storage Formats III-46UEFI Platform Initialization Specification, Release 1.8
III-3.2.5.10 EFI_SECTION_PIC
Summary
A leaf section type that contains a position-independent-code (PIC) image.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
APIC image section is a leaf section that contains a position-independent-code (PIC) image.
InadditiontonormalPE32+imagesthatcontainrelocationinformation,PEIMexecutablesmaybePICandarereferred
to as PIC images. A PIC image is the same as a PE32+ image except that all relocation information has been stripped
from the image and the image can be moved and will execute correctly without performing any relocation or other
fix-ups.EFI_PIC_SECTION2 must be used if the section is 16MB or larger.
III-3.2.5.11 EFI_SECTION_RAW
Summary
A leaf section type that contains an array of zero or more bytes.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
Araw section is a leaf section that contains an array of zero or more bytes. No particular formatting of these bytes is
implied by this section type. EFI_RAW_SECTION2 must be used if the section is 16MB or larger.
III-3.2.5.12 EFI_SECTION_MM_DEPEX
Summary
A leaf section type that is used to determine the dispatch order for an MM driver.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_MM_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_MM_DEPEX_SECTION2;
TheMMdependencyexpressionsection isaleafsectionthatcontainsadependencyexpressionthatisusedtodetermine
the dispatch order for MM drivers. Before the MMRAM invocation of the MM driver’s entry point, this dependency
expression must evaluate to TRUE. See the Platform Initialization Specification, Volume 2 for details regarding the
format of the dependency expression.
The dependency expression may refer to protocols installed in either the UEFI or the MM protocol database.
EFI_MM_DEPEX_SECTION2 must be used if the section is 16MB or larger.
III-3.2. Firmware Storage Formats III-47UEFI Platform Initialization Specification, Release 1.8
III-3.2.5.13 EFI_SECTION_TE
Summary
A leaf section that contains a Terse Executable (TE) image.
Prototype
typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
Theterseexecutablesection isaleafsectionthatcontainsaTerseExecutable(TE)image. ATEimageisanexecutable
image format specific to the PI Architecture that is used for storing executable images in a smaller amount of space
than would be required by a full PE32+ image. Only PEI Foundation and PEIM files may contain a TE section.
EFI_TE_SECTION2 must be used if the section is 16MB or larger.
III-3.2.5.14 EFI_SECTION_USER_INTERFACE
Summary
A leaf section type that contains a Unicode string that contains a human-readable file name.
Prototype
CHAR16 FileNameString[];
} EFI_USER_INTERFACE_SECTION;
} EFI_USER_INTERFACE_SECTION2;
Theuserinterfacefilenamesection isaleafsectionthatcontainsaUnicodestringthatcontainsahuman-readablefile
name.
This section is optional and is not required for any file types. There must never be more than one user interface file
namesectioncontainedwithinafile. EFI_USER_INTERFACE_SECTION2 mustbeusedifthesectionis16MBorlarger.
III-3.2.5.15 EFI_SECTION_VERSION
Summary
AleafsectiontypethatcontainsanumericbuildnumberandanoptionalUnicodestringthatrepresentsthefilerevision.
Prototype
UINT16 BuildNumber;
CHAR16 VersionString[];
} EFI_VERSION_SECTION;
III-3.2. Firmware Storage Formats III-48UEFI Platform Initialization Specification, Release 1.8
} EFI_VERSION_SECTION2;
Common section header. CommonHeader.Type =EFI_SECTION_VERSION .
BuildNumber
AUINT16that represents a particular build. Subsequent builds have monotonically increasing build numbers
relative to earlier builds.
VersionString
Anull-terminatedUnicodestringthatcontainsatextrepresentationoftheversion. Ifthereisnotextrepresenta-
tion of the version, then an empty string must be provided.
Aversionsection isaleafsectionthatcontainsanumericbuildnumberandanoptionalUnicodestringthatrepresents
the file revision.
TofacilitateversioningofPEIMs,DXEdrivers,andotherfiles,aversionsectionmaybeincludedinafile. Theremust
never be more than one version section contained within a file. EFI_VERSION_SECTION2 must be used if the section
III-3.3 PEI
III-3.3.1 EFI_PEI_FIRMWARE_VOLUME_INFO_PPI
Summary
Provides location and format of a firmware volume.
GUID
#define EFI_PEI_FIRMWARE_VOLUME_INFO_PPI_GUID \
{ 0x49edb1c1, 0xbf21, 0x4761, \
0xbb, 0x12, 0xeb, 0x0, 0x31, 0xaa, 0xbb, 0x39 }
Prototype
typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI {
VOID *FvInfo;
UINT32 FvInfoSize;
EFI_GUID *ParentFvName;
EFI_GUID *ParentFileName;
} EFI_PEI_FIRMWARE_VOLUME_INFO_PPI ;
III-3.3. PEI III-49UEFI Platform Initialization Specification, Release 1.8
FvFormat
Unique identifier of the format of the memory-mapped firmware volume.
FvInfo
Pointstoabufferwhichallowsthe EFI_PEI_FIRMWARE_VOLUME_PPI toprocessthevolume. Theformatofthis
bufferisspecifictothe FvFormat . Formemory-mappedfirmwarevolumes,thistypicallypointstothefirstbyte
of the firmware volume.
FvInfoSize
Size of the data provided by FvInfo. For memory-mapped firmware volumes, this is typically the size of the
ParentFvName ,ParentFileName
Ifthefirmwarevolumeoriginallycamefromafirmwarefile,thenthesepointtotheparentfirmwarevolumename
and firmware volume file. If it did not originally come from a firmware file, these should be NULL.
This PPI describes the location and format of a firmware volume. The FvFormat can
beEFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for a user-defined format. The
EFI_FIRMWARE_FILE_SYSTEM2_GUID is the PI Firmware Volume format.

FvFormat
FvInfo
III-3.3.2 EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI
Summary
GUID
#define EFI_PEI_FIRMWARE_VOLUME_INFO_PPI2_GUID \
{ 0xea7ca24b, 0xded5, 0x4dad, \
0xa3, 0x89, 0xbf, 0x82, 0x7e, 0x8f, 0x9b, 0x38 }
Prototype
typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI {
} EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI ;
FvFormat
FvInfo
III-3.3. PEI III-50UEFI Platform Initialization Specification, Release 1.8
Authentication status.
This PPI describes the location, format and authentication status of a firmware volume. The
FvFormat can beEFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for a user-defined format. The
III-3.3.3 PEI Firmware Volume PPI
III-3.3.3.1 EFI_PEI_FIRMWARE_VOLUME_PPI
Summary
Provides functions for accessing a memory-mapped firmware volume of a specific format.
GUID
The GUID for this PPI is the same as the firmware volume format GUID.
Prototype
typedef struct _EFI_PEI_FIRMWARE_VOLUME_PPI {
EFI_PEI_FV_PROCESS_FV ProcessVolume;
EFI_PEI_FV_FIND_FILE_TYPE FindFileByType;
EFI_PEI_FV_FIND_FILE_NAME FindFileByName;
EFI_PEI_FV_GET_FILE_INFO GetFileInfo;
EFI_PEI_FV_GET_INFO GetVolumeInfo;
EFI_PEI_FV_FIND_SECTION FindSectionByType;
EFI_PEI_FV_GET_FILE_INFO2 GetFileInfo2;
EFI_PEI_FV_FIND_SECTION2 FindSectionByType2;
} EFI_PEI_FIRMWARE_VOLUME_PPI;
ProcessVolume
Process a firmware volume and create a volume handle.
FindFileByType
Find all files of a specific type.
FindFileByName
Find the file with a specific name.
GetFileInfo
Return the information about a specific file
GetVolumeInfo
Return the firmware volume attributes.
FindSectionByType
Find the first section of a specific type.
III-3.3. PEI III-51UEFI Platform Initialization Specification, Release 1.8
GetFileInfo2
Return the information with authentication status about a specific file.
FindSectionByType2
Find the section with authentication status of a specific type.
Signature
Signature is used to keep backward-compatibility, set to {‘P’,’F’,’V’,’P’}.
Revision
Revision for further extension.
# define EFI_PEI_FIRMWARE_VOLUME_PPI_REVISION 0x00010030
III-3.3.3.2 EFI_PEI_FIRMWARE_VOLUME_PPI.ProcessVolume()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_FV_PROCESS_FV) (
IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
OUT EFI_PEI_FV_HANDLE *FvHandle
);
This
Points to this instance of the EFI_PEI_FIRMWARE_VOLUME_PPI .
Buffer
Points to the start of the buffer.
Size of the buffer.
FvHandle
Points tothe returned firmware volumehandle. The firmware volumehandle must beunique within the system.
The typeEFI_PEI_FV_HANDLE is defined in the PEI Services FfsFindNextVolume() .
Create a volume handle from the information in the buffer. For memory-mapped firmware volumes, Bufferand
BufferSize refertothestartofthefirmwarevolumeandthefirmwarevolumesize. Fornonmemory-mappedfirmware
volumes, this points to a buffer which contains the necessary information for creating the firmware volume handle.
Normally, these values are derived from the EFI_PEI_FIRMWARE_VOLUME_INFO_PPI .
Table 3.6: Status Codes Returned
EFI_SUCCESS Firmware volume handle created.
EFI_VOLUME_CORRUPTED Volume was corrupt.
III-3.3. PEI III-52UEFI Platform Initialization Specification, Release 1.8
III-3.3.3.3 EFI_PEI_FIRMWARE_VOLUME_PPI.FindFileByType()
Summary
Finds the next file of the specified type.
Prototype
typedef
(EFIAPI *EFI_PEI_FV_FIND_FILE_TYPE) (
);
This
A filter to find only files of this type. Type EFI_FV_FILETYPE_ALL causes no filtering to be done.
FvHandle
Handle of firmware volume in which to search.
Points to the current handle from which to begin searching or NULL to start at the beginning of the firmware
volume. Updated upon return to reflect the file found.
This service enables PEI modules to discover additional firmware files. The FileHandle must be unique within the
system.
Table 3.7: Status Codes Returned
EFI_NOT_FOUND The file was not found. FileHandle contains NULL.
III-3.3.3.4 EFI_PEI_FIRMWARE_VOLUME_PPI.FindFileByName()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_FV_FIND_FILE_NAME) (
IN EFI_PEI_FV_HANDLE *FvHandle,
III-3.3. PEI III-53UEFI Platform Initialization Specification, Release 1.8
);
This
FileName
FvHandle
Upon entry, the pointer to the firmware volume to search or NULLif all firmware volumes should be searched.
Upon exit, the actual firmware volume in which the file was found.
Table 3.8: Status Codes Returned
EFI_SUCCESS File was found.
EFI_NOT_FOUND File was not found.
EFI_INVALID_PARAMETER FileHandle orFileName was NULL.
III-3.3.3.5 EFI_PEI_FIRMWARE_VOLUME_PPI.GetFileInfo()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_FV_GET_FILE_INFO) (
);
This
III-3.3. PEI III-54UEFI Platform Initialization Specification, Release 1.8
FileInfo
Table 3.9: Status Codes Returned
EFI_INVALID_PARAMETER IfFileInfo is NULL
III-3.3.3.6 EFI_PEI_FIRMWARE_VOLUME_PPI.GetFileInfo2()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_FV_GET_FILE_INFO2) (
);
This
FileInfo
Table 3.10: Status Codes Returned
III-3.3. PEI III-55UEFI Platform Initialization Specification, Release 1.8
III-3.3.3.7 EFI_PEI_FIRMWARE_VOLUME_PPI.GetVolumeInfo()
Summary
Return information about the firmware volume.
Prototype
typedef
(EFIAPI *EFI_PEI_FV_GET_INFO)(
);
This
FvHandle
Handle to the firmware handle.
Points to the returned firmware volume information.
This function returns information about the firmware volume.
Table 3.11: Status Codes Returned

Summary
Prototype
typedef
);
This
FvHandle
EFI_INVALID_PARAMETER FvHandle does not indicate a valid firmware volume or VolumeInfo isNULL.
III-3.3.3.8 EFI_PEI_FIRMWARE_VOLUME_PPI.FindSectionByType()
Summary
Find the next matching section in the firmware file.
Prototype
typedef
(EFIAPI *EFI_PEI_FV_FIND_SECTION) (
IN EFI_SECTION_TYPE SearchType,
);
This
III-3.3. PEI III-56UEFI Platform Initialization Specification, Release 1.8
A filter to find only sections of this type.
Handle of firmware file in which to search.
Updated upon return to point to the section found.
This service enables PEI modules to discover sections of a given type within a valid file.
EFI_SUCCESS Section was found.
EFI_NOT_FOUND Section of the specified type was not found. SectionData containsNULL.
III-3.3.3.9 EFI_PEI_FIRMWARE_VOLUME_PPI.FindSectionByType2()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_FV_FIND_SECTION2) (
IN UINTN SearchInstance,
);
This
SearchInstance
A filter to find the specific instance of sections.
Updated upon return to point to the authentication status for this section.
This service enables PEI modules to discover sections of a given instance and type within a valid file.
III-3.3. PEI III-57UEFI Platform Initialization Specification, Release 1.8
III-3.3.4 PEI Load File PPI
III-3.3.4.1 EFI_PEI_LOAD_FILE_PPI
Summary
Installed by a PEIM that supports the Load File PPI.
GUID
#define EFI_PEI_LOAD_FILE_PPI_GUID \
{ 0xb9e0abfe, 0x5979, 0x4914, \
0x97, 0x7f, 0x6d, 0xee, 0x78, 0xc2, 0x78, 0xa6 }
Prototype
typedef struct _EFI_PEI_LOAD_FILE_PPI {
EFI_PEI_LOAD_FILE LoadFile;
} EFI_PEI_LOAD_FILE_PPI;
LoadFile
Loads a PEIM into memory for subsequent execution. See the LoadFile() function description.
ThisPPIisapointertotheLoadFileservice. ThisservicewillbepublishedbyaPEIM.ThePEIFoundationwilluse
this service to launch the known PEI module images.
III-3.3.4.2 EFI_PEI_LOAD_FILE_PPI.LoadFile()
Summary
Loads a PEIM into memory for subsequent execution.
Prototype
typedef
(EFIAPI *EFI_PEI_LOAD_FILE) (
IN CONST EFI_PEI_LOAD_FILE_PPI *This,
OUT EFI_PHYSICAL_ADDRESS *ImageAddress,
OUT UINT64 *ImageSize,
OUT EFI_PHYSICAL_ADDRESS *EntryPoint,
OUT UINT32 *AuthenticationState
);
III-3.3. PEI III-58UEFI Platform Initialization Specification, Release 1.8
This
Interface pointer that implements the Load File PPI instance.
File handle of the file to load. Type EFI_PEI_FILE_HANDLE is defined in FfsFindNextFile() .
Pointer to the address of the loaded image.
ImageSize
Pointer to the size of the loaded image.
EntryPoint
Pointer to the entry point of the image.
On exit, points to the attestation authentication state of the image or 0 if no at-
testation was performed. The format of AuthenticationState is defined in
EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI.ExtractSection().
This service is the single member function of EFI_LOAD_FILE_PPI . This service separates image loading and re-
locating from the PEI Foundation. For example, if there are compressed images or images that need to be relo-
cated into memory for performance reasons, this service performs that transformation. This service is very similar
totheEFI_LOAD_FILE_PROTOCOL intheUEFI2.0specification. Theabstractionallowsforanimplementationofthe
LoadFile() servicetosupportdifferentimagetypesinthefuture. TheremaybemorethanoneinstanceofthisPPIin
thesystem. Forexample,thePEIFoundationmightsupportonlyXIPimagesnatively,butanotherPEIMmightcontain
support for relocatable images. There must be an LoadFile() instance that at least supports the PE/COFF and Terse
Executable (TE) image format.
For sectioned files, this function should use FfsFindSectionData in order to find the executable image section.
This service must support loading of XIP images with or without copying them to a permanent memory. If the image
withinthespecifiedfilecannotbeloadedbecauseitmustbecopiedintomemory(eitherbecausetheFVisnotmemory
mappedorbecausetheimagecontainsrelocations),andthepermanentmemoryisnotavailable,thefunctionwillreturn
EFI_NOT_SUPPORTED . If permanent memory is available, then the PEIM should be loaded into permanent memory
unless the image is not relocatable. If the image cannot be loaded into permanent memory due to insufficient amount
of the available permanent memory, the function will return EFI_WARN_BUFFER_TOO_SMALL in case of XIP image,
andEFI_OUT_OF_RESOURCES in case of non-XIP image. When EFI_WARN_BUFFER_TOO_SMALL is returned, all the
output parameters are valid and the image can be invoked.
Any behavior PEIM which requires to be executed from code permanent memory should include wait for
EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI andEFI_PEI_LOAD_FILE_PPI to be installed.
Table 3.12: Status Codes Returned
EFI_SUCCESS The image was loaded successfully.
EFI_OUT_OF_RESOURCES There was not enough memory.
EFI_LOAD_ERROR There was no supported image in the file.
EFI_INVALID_PARAMETER FileHandle was not a valid firmware file handle.
EFI_INVALID_PARAMETER EntryPoint was NULL.
EFI_UNSUPPORTED An image requires relocations or is not memory mapped.
EFI_WARN_BUFFER_TOO_SMALL There is not enough heap to allocate the requested size. This will
not prevent the XIP image from being invoked.
III-3.3. PEI III-59UEFI Platform Initialization Specification, Release 1.8
III-3.3.5 PEI Guided Section Extraction PPI
III-3.3.5.1 EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
Summary
If a GUID-defined section is encountered when doing section extraction, the PEI Foundation or the
EFI_PEI_FILE_LOADER_PPI instancecallstheappropriateinstanceoftheGUIDedSectionExtractionPPItoextract
the section stream contained therein.
GUID
Typically,protocolinterfacestructuresareidentifiedbyassociatingthemwithaGUID.Eachinstanceofaprotocolwith
agivenGUIDmusthavethesameinterfacestructure. WhileallinstancesoftheGUIDedSectionExtractionPPImust
have the same interface structure, they do not all have the same GUID. The GUID that is associated with an instance
of the GUIDed Section Extraction Protocol is used to correlate it with the GUIDed section type that it is intended to
process.
PPI Structure
typedef struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI {
EFI_PEI_EXTRACT_GUIDED_SECTION ExtractSection;
} EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI;
ExtractSection
TakestheGUIDedsectionasinputandproducesthesectionstreamdata. Seethe ExtractSection() function
III-3.3.5.2 EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI.ExtractSection()
Summary
Processes the input section and returns the data contained therein along with the authentication status.
Prototype
typedef
(EFIAPI *EFI_PEI_EXTRACT_GUIDED_SECTION)(
IN CONST EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI *This,
IN CONST VOID *InputSection,
OUT VOID **OutputBuffer,
OUT UINTN *OutputSize,
);
This
Indicates the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI instance.
InputSection
Buffer containing the input GUIDed section to be processed.
OutputBuffer
*OutputBuffer is allocated from PEI permanent memory and contains the new section stream.
III-3.3. PEI III-60UEFI Platform Initialization Specification, Release 1.8
OutputSize
A pointer to a caller-allocated UINTNin which the size of *OutputBuffer allocation is stored. If the function
returns anything other than EFI_SUCCESS , the value of *OutputSize is undefined.
Apointertoacaller-allocated UINT32thatindicatestheauthenticationstatusoftheoutputbuffer. Iftheinputsec-
tion’sGuidedSectionHeader.Attributes fieldhasthe EFI_GUIDED_SECTION_AUTH_STATUS_VALID bitas
clear,*AuthenticationStatus must return zero. These bits reflect the status of the extraction operation. If
the function returns anything other than EFI_SUCCESS , the value of *AuthenticationStatus is undefined.
TheExtractSection() function processes the input section and returns a pointer to the section contents. If the
section being extracted does not require processing (if the section’s GuidedSectionHeader.Attributes has the

EFI_GUIDED_SECTION_PROCESSING_REQUIRED field cleared), then OutputBuffer is just updated to point to the
start of the section’s contents. Otherwise, *Buffer must be allocated from PEI permanent memory.
Ifthesectionbeingextractedcontainsauthenticationinformation(thesection’s GuidedSectionHeader.Attributes
field has the EFI_GUIDED_SECTION_AUTH_STATUS_VALID bit set), the values returned in AuthenticationStatus
must reflect the results of the authentication operation.
If the section contains other encapsulation sections, their contents do not need to be extracted or decompressed.
// Bit values forAuthenticationStatus
#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01
#define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02
#define EFI_AUTH_STATUS_NOT_TESTED 0x04
#define EFI_AUTH_STATUS_TEST_FAILED 0x08
// all other bits are reserved andmust be 0
Thebitdefinitionsaboveleadtotheevaluationsof AuthenticationStatus : inAuthenticationStatusBitDefinitions .
Table 3.13: AuthenticationStatus Bit Definitions
BitDefinition
xx00Image was not signed.
xxx1Platformsecuritypolicyoverride. Assumessamemeaningas0010(theimagewassigned,thesignaturewas
tested, and the signature passed authentication test).
0010Image was signed, the signature was tested, and the signature passed authentication test.
0110Imagewassignedandthesignaturewasnottested. ThiscanoccurifthereisnoGUIDedSectionExtraction
Protocol available to process a GUID-defined section, but it was still possible to retrieve the data from the
GUID-defined section directly.
1010Image was signed, the signature was tested, and the signature failed the authentication test.
1110To generate this code, there must be at least two layers of GUIDed encapsulations. In one layer, the
AuthenticationStatus was returned as 0110; in another layer, it was returned as 1010. When these
two results are OR ed together, the aggregate result is 1110.
III-3.3. PEI III-61UEFI Platform Initialization Specification, Release 1.8
Table 3.14: Status Codes Returned
EFI_SUCCESS TheInputSection wassuccessfullyprocessedandthesectioncon-
tents were returned.
EFI_OUT_OF_RESOURCES The system has insufficient resources to process the request.
EFI_INVALID_PARAMETER The GUID in InputSection does not match this instance of the
GUIDed Section Extraction PPI.
III-3.3.6 PEI Decompress PPI
III-3.3.6.1 EFI_PEI_DECOMPRESS_PPI
Summary
Provides decompression services to the PEI Foundatoin.
GUID
#define EFI_PEI_DECOMPRESS_PPI_GUID \
{ 0x1a36e4e7, 0xfab6, 0x476a, \
{ 0x8e, 0x75, 0x69, 0x5a, 0x5, 0x76, 0xfd, 0xd7 } }
typedef struct _EFI_PEI_DECOMPRESS_PPI {
EFI_PEI_DECOMPRESS_DECOMPRESS Decompress;
} EFI_PEI_DECOMPRESS_PPI;
Members
Decompress
Decompress a single compression section in a firmware file. See Decompress() for more information.
ThisPPI’ssinglememberfunctiondecompressesacompressionencapsulatedsection. ItisusedbythePEIFoundation
to process sectioned files. Prior to the installation of this PPI, compression sections will be ignored.
III-3.3.6.2 EFI_PEI_DECOMPRESS_PPI.Decompress()
Summary
Decompress a single section.
Prototype
typedef
(EFIAPI *EFI_PEI_DECOMPRESS_DECOMPRESS)(
IN CONST EFI_PEI_DECOMPRESS_PPI *This,
IN CONST EFI_COMPRESSION_SECTION *InputSection,
OUT UINTN *OutputSize
);
III-3.3. PEI III-62UEFI Platform Initialization Specification, Release 1.8
This
Points to this instance of the EFI_PEI_DECOMPRESS_PEI PPI .
Points to the compressed section.
Holds the returned pointer to the decompressed sections.
Holds the returned size of the decompress section streams.
Decompresses the data in a compressed section and returns it as a series of standard PI Firmware File Sections. The
required memory is allocated from permanent memory.
Table 3.15: Status Codes Returned
EFI_SUCCESS The section was decompressed successfully. OutputBuffer con-
tainstheresultingdataand OutputSize containstheresultingsize.
EFI_OUT_OF_RESOURCES Unabletoallocatesufficientmemorytoholdthedecompresseddata.
EFI_UNSUPPORTED Thecompressiontypespecifiedinthecompressionheaderisunsup-
ported.
III-3.4 DXE
III-3.4.1 Firmware Volume2 Protocol
III-3.4.1.1 EFI_FIRMWARE_VOLUME2_PROTOCOL
Summary
The Firmware Volume Protocol provides file-level access to the firmware volume. Each firmware volume driver must
produce an instance of the Firmware Volume Protocol if the firmware volume is to be visible to the system during the
DXEphase. TheFirmwareVolumeProtocolalsoprovidesmechanismsfordeterminingandmodifyingsomeattributes
GUID
#define EFI_FIRMWARE_VOLUME2_PROTOCOL_GUID \
{ 0x220e73b6, 0x6bdb, 0x4413, 0x84, 0x5, 0xb9, 0x74, \
0xb1, 0x8, 0x61, 0x9a }
typedef struct_EFI_FIRMWARE_VOLUME_PROTOCOL {
EFI_FV_GET_ATTRIBUTES GetVolumeAttributes;
EFI_FV_SET_ATTRIBUTES SetVolumeAttributes;
EFI_FV_READ_FILE ReadFile;
EFI_FV_READ_SECTION ReadSection;
EFI_FV_WRITE_FILE WriteFile;
EFI_FV_GET_NEXT_FILE GetNextFile;
III-3.4. DXE III-63UEFI Platform Initialization Specification, Release 1.8
EFI_FV_GET_INFO GetInfo;
EFI_FV_SET_INFO SetInfo;
} EFI_FIRMWARE_VOLUME2_PROTOCOL;
GetVolumeAttributes
Retrieves volume capabilities and current settings. See the GetVolumeAttributes() function description.
SetVolumeAttributes
Modifies the current settings of the firmware volume. See the SetVolumeAttributes() function description.
ReadFile
Reads an entire file from the firmware volume. See the ReadFile() function description.
ReadSection
Reads a single section from a file into a buffer. See the ReadSection() function description.
WriteFile
Writes an entire file into the firmware volume. See the WriteFile() function description.
GetNextFile
Provides service to allow searching the firmware volume. See the GetNextFile() function description.
KeySize
Data field that indicates the size in bytes of the Keyinput buffer for the GetNextFile() API.
ParentHandle
Handleoftheparentfirmwarevolume. Type EFI_HANDLE isdefinedin InstallProtocolInterface() inthe
GetInfo
Gets the requested file or volume information. See the GetInfo() function description.
SetInfo
Sets the requested file information. See the SetInfo() function description.
The Firmware Volume Protocol contains the file-level abstraction to the firmware volume as well as some firmware
volumeattributereportingandconfigurationservices. TheFirmwareVolumeProtocolistheinterfaceusedbyallparts
of DXE that are not directly involved with managing the firmware volume itself. This abstraction allows many varied
types of firmware volume implementations. A firmware volume may be a flash device or it may be a file in the UEFI
system partition, for example. This level of firmware volume implementation detail is not visible to the consumers of
the Firmware Volume Protocol.
III-3.4.1.2 EFI_FIRMWARE_VOLUME2_PROTOCOL.GetVolumeAttributes()
Summary
Returns the attributes and current settings of the firmware volume.
Prototype
typedef
(EFIAPI * EFI_FV_GET_ATTRIBUTES) (
III-3.4. DXE III-64UEFI Platform Initialization Specification, Release 1.8
IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
OUT EFI_FV_ATTRIBUTES *FvAttributes
);
This
Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
Pointer to an EFI_FV_ATTRIBUTES in which the attributes and current settings are returned. Type
EFI_FV_ATTRIBUTES is defined in “Related Definitions” below.
Becauseofconstraintsimposedbytheunderlyingfirmwarestorage,aninstanceoftheFirmwareVolumeProtocolmay
not be to able to support all possible variations of this architecture. These constraints and the current state of the
firmware volume are exposed to the caller using the GetVolumeAttributes() function.
GetVolumeAttributes() is callable only from EFI_TPL_NOTIFY and below. Behavior of
GetVolumeAttributes() at anyEFI_TPL aboveEFI_TPL_NOTIFY is undefined. Type EFI_TPL is defined in
RaiseTPL() in the UEFI 2.0 specification.
// EFI_FV_ATTRIBUTES
typedef UINT64 EFI_FV_ATTRIBUTES;
// EFI_FV_ATTRIBUTES bit definitions
// EFI_FV_ATTRIBUTES bit semantics
#define EFI_FV2_READ_DISABLE_CAP 0x0000000000000001
#define EFI_FV2_READ_ENABLE_CAP 0x0000000000000002
#define EFI_FV2_READ_STATUS 0x0000000000000004
#define EFI_FV2_WRITE_DISABLE_CAP 0x0000000000000008
#define EFI_FV2_WRITE_ENABLE_CAP 0x0000000000000010
#define EFI_FV2_WRITE_STATUS 0x0000000000000020

#define EFI_FV2_LOCK_CAP 0x0000000000000040
#define EFI_FV2_LOCK_STATUS 0x0000000000000080
#define EFI_FV2_WRITE_POLICY_RELIABLE 0x0000000000000100
#define EFI_FV2_READ_LOCK_CAP 0x0000000000001000
#define EFI_FV2_READ_LOCK_STATUS 0x0000000000002000
#define EFI_FV2_WRITE_LOCK_CAP 0x0000000000004000
#define EFI_FV2_WRITE_LOCK_STATUS 0x0000000000008000
#define EFI_FV2_ALIGNMENT 0x00000000001F0000
#define EFI_FV2_ALIGNMENT_1 0x0000000000000000
#define EFI_FV2_ALIGNMENT_2 0x0000000000010000
III-3.4. DXE III-65UEFI Platform Initialization Specification, Release 1.8
#define EFI_FV2_ALIGNMENT_4 0x0000000000020000
#define EFI_FV2_ALIGNMENT_8 0x0000000000030000
#define EFI_FV2_ALIGNMENT_16 0x0000000000040000
#define EFI_FV2_ALIGNMENT_32 0x0000000000050000
#define EFI_FV2_ALIGNMENT_64 0x0000000000060000
#define EFI_FV2_ALIGNMENT_128 0x0000000000070000
#define EFI_FV2_ALIGNMENT_256 0x0000000000080000
#define EFI_FV2_ALIGNMENT_512 0x0000000000090000
#define EFI_FV2_ALIGNMENT_1K 0x00000000000A0000
#define EFI_FV2_ALIGNMENT_2K 0x00000000000B0000
#define EFI_FV2_ALIGNMENT_4K 0x00000000000C0000
#define EFI_FV2_ALIGNMENT_8K 0x00000000000D0000
#define EFI_FV2_ALIGNMENT_16K 0x00000000000E0000
#define EFI_FV2_ALIGNMENT_32K 0x00000000000F0000
#define EFI_FV2_ALIGNMENT_64K 0x0000000000100000
#define EFI_FV2_ALIGNMENT_128K 0x0000000000110000
#define EFI_FV2_ALIGNMENT_256K 0x0000000000120000
#define EFI_FV2_ALIGNMENT_512K 0x0000000000130000
#define EFI_FV2_ALIGNMENT_1M 0x0000000000140000
#define EFI_FV2_ALIGNMENT_2M 0x0000000000150000
#define EFI_FV2_ALIGNMENT_4M 0x0000000000160000
#define EFI_FV2_ALIGNMENT_8M 0x0000000000170000
#define EFI_FV2_ALIGNMENT_16M 0x0000000000180000
#define EFI_FV2_ALIGNMENT_32M 0x0000000000190000
#define EFI_FV2_ALIGNMENT_64M 0x00000000001A0000
#define EFI_FV2_ALIGNMENT_128M 0x00000000001B0000
#define EFI_FV2_ALIGNMENT_256M 0x00000000001C0000
#define EFI_FV2_ALIGNMENT_512M 0x00000000001D0000
#define EFI_FV2_ALIGNMENT_1G 0x00000000001E0000
#define EFI_FV2_ALIGNMENT_2G 0x00000000001F0000
Descriptions of Fields for EFI_FV_ATTRIBUTES describes the fields in the above definition.
III-3.4. DXE III-66UEFI Platform Initialization Specification, Release 1.8
Table 3.16: Descriptions of Fields for EFI_FV_ATTRIBUTES
EFI_FV_READ_DISABLED_CAP Set to 1 if it is possible to disable reads from the firmware volume.
EFI_FV_READ_ENABLED_CAP Set to 1 if it is possible to enable reads from the firmware volume.
EFI_FV_READ_STATUS Indicates the current read state of the firmware volume. Set to 1 if
reads from the firmware volume are enabled.
EFI_FV_WRITE_DISABLED_CAP Set to 1 if it is possible to disable writes to the firmware volume.
EFI_FV_WRITE_ENABLED_CAP Set to 1 if it is possible to enable writes to the firmware volume.
EFI_FV_WRITE_STATUS Indicatesthecurrentstateofthefirmwarevolume. Setto1ifwrites
to the firmware volume are enabled.
EFI_FV_LOCK_CAP Setto1ifitispossibletolockfirmwarevolumereadwriteattributes.
EFI_FV_LOCK_STATUS Set to 1 if firmware volume attributes are locked down.
EFI_FV_WRITE_POLICY_RELIABLE Set to 1 if the firmware volume supports “reliable” writes.
EFI_FV_READ_LOCK_CAP Set to 1 if it is possible to lock the read status for the firmware vol-
ume.
EFI_FV_READ_LOCK_STATUS Indicates the current read lock state of the firmware volume. Set to
1 if the read lock is currently enabled.
EFI_FV_WRITE_LOCK_CAP Setto1ifitispossibletolockthewritestatusforthefirmwarevol-
ume.
EFI_FV_WRITE_LOCK_STATUS Indicatesthecurrentwritelockstateofthefirmwarevolume. Setto
1 if the write lock is currently enabled.
EFI_FV_ALIGNMENT Thefirstbyteofthefirmwarevolumemustbeatanaddresswhichis
an even multiple of the alignment specified.
All other bits are reserved and are cleared to zero.
Table 3.17: Status Codes Returned
EFI_SUCCESS The firmware volume attributes were returned.
III-3.4.1.3 EFI_FIRMWARE_VOLUME2_PROTOCOL.SetVolumeAttributes()
Summary
Modifies the current settings of the firmware volume according to the input parameter.
Prototype
typedef
(EFIAPI * EFI_FV_SET_ATTRIBUTES) (
IN OUT EFI_FV_ATTRIBUTES *FvAttributes
);
This
On input, FvAttributes is a pointer to an EFI_FV_ATTRIBUTES containing the desired firmware volume
settings. On successful return, it contains the new settings of the firmware volume. On unsuccessful return,
III-3.4. DXE III-67UEFI Platform Initialization Specification, Release 1.8
FvAttributes is not modified and the firmware volume settings are not changed. Type EFI_FV_ATTRIBUTES
is defined in GetVolumeAttributes() .
TheSetVolumeAttributes() function is used to set configurable firmware volume attributes. Only
EFI_FV_READ_STATUS ,EFI_FV_WRITE_STATUS , andEFI_FV_LOCK_STATUS may be modified, and then only in
accordance with the declared capabilities. All other bits of *FvAttributes are ignored on input. On successful
return, all bits of *FvAttributes are valid and it contains the completed EFI_FV_ATTRIBUTES for the volume.
To modify an attribute, the corresponding status bit in the EFI_FV_ATTRIBUTES is set to the desired value on input.
TheEFI_FV_LOCK_STATUS bit does not affect the ability to read or write the firmware volume. Rather, once the
EFI_FV_LOCK_STATUS bit is set, it prevents further modification to all the attribute bits.
SetVolumeAttributes() is callable only from EFI_TPL_NOTIFY and below. Behavior of
SetVolumeAttributes() at anyEFI_TPL aboveEFI_TPL_NOTIFY is undefined. Type EFI_TPL is defined in
Table 3.18: Status Codes Returned
EFI_SUCCESS The requested firmware volume attributes were set and the resulting
EFI_FV_ATTRIBUTES is returned in FvAttributes .
EFI_INVALID_PARAMETER FvAttributes:EFI_FV_READ_STATUS is set to 1 on in-
put, but the device does not support enabling reads
(FvAttributes:EFI_FV_READ_ENABLE_CAP is clear on return from
GetVolumeAttributes() ). Actual volume attributes are unchanged.
EFI_INVALID_PARAMETER FvAttributes:EFI_FV_READ_STATUS is cleared to 0 on
input, but the device does not support disabling reads
(FvAttributes:EFI_FV_READ_DISABLE_CAP is clear on return from
EFI_INVALID_PARAMETER FvAttributes:EFI_FV_WRITE_STATUS is set to 1 on in-
put, but the device does not support enabling writes
(FvAttributes:EFI_FV_WRITE_ENABLE_CAP is clear on return from
EFI_INVALID_PARAMETER FvAttributes:EFI_FV_WRITE_STATUS is cleared to 0 on
input, but the device does not support disabling writes
(FvAttributes:EFI_FV_WRITE_DISABLE_CAP is clear on return
fromGetVolumeAttributes() ). Actualvolumeattributesareunchanged.
EFI_INVALID_PARAMETER FvAttributes:EFI_FV_LOCK_STATUS issetoninput,butthedevicedoes
notsupportlocking( FvAttributes:EFI_FV_LOCK_CAP isclearonreturn
EFI_ACCESS_DENIED Device is locked and does not allow attribute modification
(FvAttributes:EFI_FV_LOCK_STATUS is set on return from
III-3.4. DXE III-68UEFI Platform Initialization Specification, Release 1.8
III-3.4.1.4 EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadFile()
Summary
Retrieves a file and/or file information from the firmware volume.
Prototype
typedef
(EFIAPI * EFI_FV_READ_FILE) (
IN CONST EFI_GUID *NameGuid,
IN OUT VOID **Buffer,
OUT EFI_FV_FILETYPE *FoundType,
OUT EFI_FV_FILE_ATTRIBUTES *FileAttributes,
);
This
NameGuid
Pointer to an EFI_GUID , which is the file name. All firmware file names are EFI_GUID s. A single firmware
volume must not have two valid files with the same file name EFI_GUID . TypeEFI_GUID is defined in
Buffer
Pointer to a pointer to a buffer in which the file contents are returned, not including the file header. See “De-
scription” below for more details on the use of the Bufferparameter.
Pointertoacaller-allocated UINTN.Itindicatesthesizeofthememoryrepresentedby *Buffer . See“Descrip-
tion” below for more details on the use of the BufferSize parameter.
FoundType
Pointer to a caller-allocated EFI_FV_FILETYPE . See Firmware File Types for EFI_FV_FILETYPE related defi-
nitions.
Pointertoacaller-allocated EFI_FV_FILE_ATTRIBUTES .TypeEFI_FV_FILE_ATTRIBUTES isdefinedin“Re-
lated Definitions” below.
Pointer to a caller-allocated UINT32in which the authentication status is returned. See “Related Definitions” in
EFI_SECTION_EXTRACTION_PROCOCOL.ExtractSection() for more information.

Buffer
FoundType
nitions.
ReadFile() isusedtoretrieveanyfilefromafirmwarevolumeduringtheDXEphase. Theactualbinaryencodingof
the file in the firmware volume media may be in any arbitrary format as long as it does the following:
•It is accessed using the Firmware Volume Protocol.
•The image that is returned follows the image format defined in Code Definitions: PI Firmware File Format.
If the input value of Buffer==NULL , it indicates the caller is requesting only that the type, attributes, and size of the
file be returned and that there is no output buffer. In this case, the following occurs:
III-3.4. DXE III-69UEFI Platform Initialization Specification, Release 1.8
•*BufferSize is returned with the size that is required to successfully complete the read.
•The output parameters *FoundType and*FileAttributes are returned with valid values.
•The returned value of *AuthenticationStatus is undefined.
If the input value of Buffer!=NULL , the output buffer is specified by a double indirection of the Bufferparameter.
The input value of *Buffer is used to determine if the output buffer is caller allocated or is dynamically allocated by
ReadFile() .
If the input value of *Buffer!=NULL , it indicates the output buffer is caller allocated. In this case, the input
value of*BufferSize indicates the size of the caller-allocated output buffer. If the output buffer is not large
enough to contain the entire requested output, it is filled up to the point that the output buffer is exhausted and
EFI_WARN_BUFFER_TOO_SMALL isreturned,andthen *BufferSize isreturnedwiththesizerequiredtosuccessfully
complete the read. All other output parameters are returned with valid values.
If the input value of *Buffer==NULL , it indicates the output buffer is to be allocated by ReadFile() . In this case,
ReadFile() will allocate an appropriately sized buffer from boot services pool memory, which will be returned in
*Buffer . The size of the new buffer is returned in *BufferSize and all other output parameters are returned with
valid values.
ReadFile() is callable only from EFI_TPL_NOTIFY and below. Behavior of ReadFile() at anyEFI_TPL above
EFI_TPL_NOTIFY is undefined. Type EFI_TPL is defined in RaiseTPL() in the UEFI 2.0 specification.
// EFI_FV_FILE_ATTRIBUTES
typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
Fig. 3.2: EFI_FV_FILE_ATTRIBUTES-fields
This value is returned by EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadFile() and the PEI Service
FfsGetFileInfo() . It is not the same as EFI_FFS_FILE_ATTRIBUTES .
TheReserved field must be set to zero.
TheEFI_FV_FILE_ATTRIB_ALIGNMENT fieldindicatesthatthebeginningofthefiledata(notthefileheader)mustbe
alignedonaparticularboundaryrelativetothebeginningofthefirmwarevolume. Thisalignmentonlymakessensefor
block-oriented firmware volumes. This field is an enumeration of alignment possibilities. The allowable alignments
are powers of two from byte alignment to 2GB alignment. The supported alignments are described in Supported
Alignments for EFI_FV_FILE_ATTRIB_ALIGNMENT. All other values are reserved.
III-3.4. DXE III-70UEFI Platform Initialization Specification, Release 1.8
Table 3.19: Supported Alignments for
EFI_FV_FILE_ATTRIB_ALIGNMENT
Required Alignment (bytes) Alignment Value in Attributes Field
1 0
2 1
4 2
8 3
16 4
32 5
64 6
128 7
256 8
512 9
1KiB 10
2KiB 11
4KiB 12
8KiB 13
16KiB 14
32KiB 15
64KiB 16
128 KiB 17
256 KiB 18
512 KiB 19
1 MiB 20
2 MiB 21
4 MiB 22
8 MiB 23
16 MiB 24
32 MiB 25
64 MiB 26
128 MiB 27
256 MiB 28
512 MiB 29
1 GiB 30
2 GiB 31
TheEFI_FV_FILE_ATTRIB_FIXED attributeindicatesthatthefilehasafixedlocationandshouldnotbemoved(1)or
may be moved to any address consistent with the alignment specified in EFI_FV_FILE_ATTRIB_ALIGNMENT .
TheEFI_FV_FILE_ATTRIB_MEMORY_MAPPED attribute indicates that the file is memory mapped in the firmware vol-
ume and thus its contents may be accessed directly. If this is clear, then Bufferis invalid. This value can be derived
from theEFI_FV_ATTRIBUTES value returned by EFI_FIRMWARE_VOLUME2_PROTOCOL.GetVolumeAttributes()
or the PEI Service FfsGetVolumeInfo() .
III-3.4. DXE III-71UEFI Platform Initialization Specification, Release 1.8
Table 3.20: Status Codes Returned
EFI_SUCCESS The call completed successfully.
EFI_WARN_BUFFER_TOO_SMALL The buffer is too small to contain the requested output. The buffer
is filled and the output is truncated.
EFI_OUT_OF_RESOURCES An allocation failure occurred.
EFI_NOT_FOUND Namewas not found in the firmware volume.
EFI_DEVICE_ERROR A hardware error occurred when attempting to access the firmware
volume.
EFI_ACCESS_DENIED The firmware volume is configured to disallow reads.
III-3.4.1.5 EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection()
Summary
Locates the requested section within a file and returns it in a buffer.
Prototype
typedef
(EFIAPI * EFI_FV_READ_SECTION) (
IN UINTN SectionInstance,
);
This
NameGuid
Pointer to an EFI_GUID , which indicates the file name from which the requested section will be read. Type
EFI_GUID isdefinedin InstallProtocolInterface() intheRelatedDefinitionsfor FirmwareFileSection .
Indicates the section type to return. SectionType in conjunction with SectionInstance indicates which
section to return. Type EFI_SECTION_TYPE is defined in EFI_COMMON_SECTION_HEADER .
Indicates which instance of sections with a type of SectionType to return. SectionType in conjunction with
SectionInstance indicates which section to return. SectionInstance is zero based.
Buffer
Pointer to a pointer to a buffer in which the section contents are returned, not including the section header. See
“Description” below for more details on the usage of the Bufferparameter.
tion” below for more details on the usage of the BufferSize parameter.
III-3.4. DXE III-72UEFI Platform Initialization Specification, Release 1.8
Pointer to a caller-allocated UINT32 in which the authentication status is returned. See
EFI_SECTION_EXTRACTION_PROCOCOL.GetSection() for more information.
ReadSection() is used to retrieve a specific section from a file within a firmware volume. The section returned
is determined using a depth-first, left-to-right search algorithm through all sections found in the specified file. See
Firmware File Sections for more details about sections.
Theoutputbufferisspecifiedbyadoubleindirectionofthe Bufferparameter. Theinputvalueof *Buffer isusedto
determine if the output buffer is caller allocated or is dynamically allocated by ReadSection() .
If the input value of *Buffer!=NULL , it indicates that the output buffer is caller allocated. In this case, the in-
put value of *BufferSize indicates the size of the caller-allocated output buffer. If the output buffer is not large
EFI_WARN_BUFFER_TOO_SMALL is returned, and then *BufferSize is returned with the size that is required to suc-
cessfully complete the read. All other output parameters are returned with valid values.
Iftheinputvalueof *Buffer==NULL ,itindicatestheoutputbufferistobeallocatedby ReadSection() . Inthiscase,
ReadSection() will allocate an appropriately sized buffer from boot services pool memory, which will be returned
in*Buffer . Thesizeofthenewbufferisreturnedin *BufferSize andallotheroutputparametersarereturnedwith
ReadSection() is callable only from EFI_TPL_NOTIFY and below. Behavior of ReadSection() at anyEFI_TPL
aboveEFI_TPL_NOTIFY is undefined. Type EFI_TPL is defined in RaiseTPL() in the UEFI 2.0 specification.
Table 3.21: Status Codes Returned
EFI_WARN_BUFFER _
TOO_SMALLThecallerallocatedbufferistoosmalltocontaintherequestedoutput. The
buffer is filled and the output is truncated.
EFI_NOT_FOUND The requested file was not found in the firmware volume.
EFI_NOT_FOUND The requested section was not found in the specified file.
EFI_DEVICE_ERROR Ahardwareerroroccurredwhenattemptingtoaccessthefirmwarevolume.

EFI_PROTOCOL_ERROR The requested section was not found, but the file could not be fully parsed
because a required EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL
was not found. It is possible the requested section exists within
the file and could be successfully extracted once the required
EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL is published.
III-3.4.1.6 EFI_FIRMWARE_VOLUME2_PROTOCOL.WriteFile()
Summary
Writes one or more files to the firmware volume.
Prototype
typedef
(EFIAPI * EFI_FV_WRITE_FILE) (
III-3.4. DXE III-73UEFI Platform Initialization Specification, Release 1.8
IN UINT32 NumberOfFiles,
IN EFI_FV_WRITE_POLICY WritePolicy,
IN EFI_FV_WRITE_FILE_DATA *FileData
);
This
NumberOfFiles
Indicates the number of elements in the array pointed to by FileData .
WritePolicy
Indicates the level of reliability for the write in the event of a power failure or other system failure during the
write operation. Type EFI_FV_WRITE_POLICY is defined in “Related Definitions” below.
FileData
Pointertoanarrayof EFI_FV_WRITE_FILE_DATA .Eachelementof FileData[] representsafiletobewritten.
TypeEFI_FV_WRITE_FILE_DATA is defined in “Related Definitions” below.
WriteFile() is used to write one or more files to a firmware volume. Each file to be written is described by an
EFI_FV_WRITE_FILE_DATA structure.
The caller must ensure that any required alignment for all files listed in the FileData array is compatible with the
firmware volume. Firmware volume capabilities can be determined using the GetVolumeAttributes() call.
Similarly, if the WritePolicy is set toEFI_FV_RELIABLE_WRITE , the caller must check the firmware volume ca-
pabilities to ensure EFI_FV_RELIABLE_WRITE is supported by the firmware volume. EFI_FV_UNRELIABLE_WRITE
must always be supported.
Writing a file with a size of zero ( FileData[n].BufferSize == 0 ) deletes the file from the firmware volume if
it exists. Deleting a file must be done one at a time. Deleting a file as part of a multiple file write is not allowed.
WriteFile() is callable only from EFI_TPL_NOTIFY and below. Behavior of WriteFile() at anyEFI_TPL above
// EFI_FV_WRITE_POLICY
typedef UINT32 EFI_FV_WRITE_POLICY
#define EFI_FV_UNRELIABLE_WRITE 0x00000000
#define EFI_FV_RELIABLE_WRITE 0x00000001
All other values of EFI_FV_WRITE_POLICY are reserved. Description of fields for EFI_FV_WRITE_POLICY de-
scribes the fields in the above definition.
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Table 3.22: Description of fields for EFI_FV_WRITE_POLICY
EFI_FV_UNRELIABLE_WRITE This value in the WritePolicy parameter indicates that there is no re-
quired reliability if a power failure or other system failure occurs during
a write operation. Updates may leave a combination of old and new files.
Data loss, including complete loss of all files involved, is also permis-
sible. In essence, no guarantees are made regarding what files will be
present following a system failure during a write with a WritePolicy of
EFI_FV_UNRELIABLE_WRITE . The advantage of this mode is that it can be
implementedtousemuchlessspaceinthestoragemedia. Space-constrained
firmwarevolumesmaybeabletosupportwriteswhereitwouldbeotherwise
impossible.
EFI_FV_RELIABLE_WRITE This value in the WritePolicy parameter indicates that, on the next ini-
tializationofthefirmwarevolumefollowingapowerfailureorothersystem
failure during a write, all files listed in the FileData array are completely
writtenandarevalid,ornoneiswrittenandthestateofthefirmwarevolume
is the same as it was before the write operation was attempted.
// EFI_FV_WRITE_FILE_DATA
EFI_GUID *NameGuid,
EFI_FV_FILETYPE Type,
EFI_FV_FILE_ATTRIBUTES FileAttributes
VOID *Buffer,
UINT32 BufferSize
} EFI_FV_WRITE_FILE_DATA;
NameGuid
Pointer to a GUID, which is the file name to be written. Type EFI_GUID is defined in
Type
Indicates the type of file to be written. Type EFI_FV_FILETYPE is defined in “Related Definitions” of
EFI_FFS_FILE_HEADER..
Indicates the attributes for the file to be written. Type EFI_FV_FILE_ATTRIBUTES is defined in ReadFile() .
Buffer
Pointer to a buffer containing the file to be written.
Indicates the size of the file image contained in Buffer.
III-3.4. DXE III-75UEFI Platform Initialization Specification, Release 1.8
Table 3.23: Status Codes Returned
EFI_SUCCESS The write completed successfully.
EFI_OUT_OF_RESOURCES The firmware volume does not have enough free space to storefile(s).
EFI_WRITE_PROTECTED The firmware volume is configured to disallow writes.
EFI_NOT_FOUND A delete was requested but the requested file was not found in the firmware
volume.
EFI_INVALID_PARAMETER A delete was requested with a multiple file write.
EFI_INVALID_PARAMETER An unsupported WritePolicy was requested.
EFI_INVALID_PARAMETER Anunknownfiletypewasspecifiedspecifiedorthespecifiedfiletypeisnot
supported by the firmware file system.
EFI_INVALID_PARAMETER A file system specific error has occurred.
Other than EFI_DEVICE_ERROR , all error codes imply the firmware volume has not been modified. In the case of
EFI_DEVICE_ERROR , the firmware volume may have been corrupted and appropriate repair steps must be taken.
III-3.4.1.7 EFI_FIRMWARE_VOLUME2_PROTOCOL.GetNextFile()
Summary
Retrieves information about the next file in the firmware volume store that matches the search criteria.
Prototype
typedef
(EFIAPI * EFI_FV_GET_NEXT_FILE) (
IN OUT VOID *Key,
IN OUT EFI_FV_FILETYPE *FileType,
OUT EFI_GUID *NameGuid,
OUT EFI_FV_FILE_ATTRIBUTES *Attributes,
OUT UINTN *Size
);
This
Key
Pointertoacaller-allocatedbufferthatcontainsimplementation-specificdatathatisusedtotrackwheretobegin
the search for the next file. The size of the buffer must be at least This->KeySize bytes long. To re-initialize
thesearchandbeginfromthebeginningofthefirmwarevolume,theentirebuffermustbeclearedtozero. Other
than clearing the buffer to initiate a new search, the caller must not modify the data in the buffer between calls
toGetNextFile() .
FileType
Pointer to a caller-allocated EFI_FV_FILETYPE . TheGetNextFile() API can filter its search for files based
onthevalueofthe *FileType input. A*FileType inputofEFI_FV_FILETYPE_ALL causesGetNextFile()
to search for files of all types. If a file is found, the file’s type is returned in *FileType .*FileType is not
modified if no file is found. See“Related Definitions” of EFI_FFS_FILE_HEADER..
NameGuid
Pointer to a caller-allocated EFI_GUID . If a matching file is found, the file’s name is returned in
III-3.4. DXE III-76UEFI Platform Initialization Specification, Release 1.8
*NameGuid . If no matching file is found, *NameGuid is not modified. Type EFI_GUID is defined in
Pointer to a caller-allocated EFI_FV_FILE_ATTRIBUTES . If a matching file is found, the file’s attributes
are returned in *Attributes . If no matching file is found, *Attributes is not modified. Type
EFI_FV_FILE_ATTRIBUTES is defined in ReadFile() .
Size
Pointertoacaller-allocated UINTN.Ifamatchingfileisfound,thefile’ssizeisreturnedin *Size. Ifnomatching
file is found, *Sizeis not modified.
GetNextFile() is the interface that is used to search a firmware volume for a particular file. It is called successively
until the desired file is located or the function returns EFI_NOT_FOUND .
To filter uninteresting files from the output, the type of file to search for may be specified in *FileType . For
example, if *FileType isEFI_FV_FILETYPE_DRIVER , only files of this type will be returned in the output. If
*FileType isEFI_FV_FILETYPE_ALL , no filtering of file types is done.The behavior of files with file types
EFI_FV_FILETYPE_FFS_MIN andEFI_FV_FILETYPE_FFS_MAX dependsonthefirmwarefilesystem. Formoreinfor-
mation on the specific behavior for the standard PI firmware file system, see section 1.1.4.1.6 of the PI Specification,
Volume 3.
TheKeyparameter is used to indicate a starting point of the search. If the buffer *Keyis completely initialized to
zero,thesearchre-initializedandstartsatthebeginning. Subsequentcallsto GetNextFile() mustmaintainthevalue
of*Keyreturned by the immediately previous call. The actual contents of *Keyare implementation specific and no

Volume 3.
semantic content is implied.
GetNextFile() is callable only from EFI_TPL_NOTIFY and below. Behavior of GetNextFile() at anyEFI_TPL
Table 3.24: Status Codes Returned
EFI_SUCCESS The output parameters are filled with data obtained from the first matching file
that was found.
EFI_NOT_FOUND No files of type FileType were found.
EFI_DEVICE_ERROR A hardware error occurred when attempting to access the firmware volume.
III-3.4.1.8 EFI_FIRMWARE_VOLUME2_PROTOCOL.GetInfo()
Summary
Return information about a firmware volume.
Prototype
typedef
(EFIAPI *EFI_FV_GET_INFO) (
IN CONST EFI_GUID *InformationType,
);
III-3.4. DXE III-77UEFI Platform Initialization Specification, Release 1.8
This
A pointer to the EFI_FIRMWARE_VOLUME2_PROTOCOL instance that is the file handle the requested information
is for.
Thetypeidentifierfortheinformationbeingrequested. Type EFI_GUID isdefinedintheUEFI2.0specification.
On input, the size of Buffer. On output, the amount of data returned in Buffer. In both cases, the size is
Buffer
A pointer to the data buffer to return. The buffer’s type is indicated by InformationType.
TheGetInfo() function returns information of type InformationType for the requested firmware volume. If the
volumedoesnotsupporttherequestedinformationtype,then EFI_UNSUPPORTED isreturned. Ifthebufferisnotlarge
enoughtoholdtherequestedstructure, EFI_BUFFER_TOO_SMALL isreturnedandthe BufferSize issettothesizeof
bufferthatisrequiredtomaketherequest. Theinformationtypesdefinedbythisspecificationarerequiredinformation
types that all file systems must support.
Table 3.25: Status Codes Returned
EFI_SUCCESS The information was retrieved.
EFI_VOLUME_CORRUPTED The file system structures are corrupted.
EFI_BUFFER_TOO_SMALL TheBufferSize is too small to read the current directory entry. BufferSize
III-3.4.1.9 EFI_FIRMWARE_VOLUME2_PROTOCOL.SetInfo()
Summary
Sets information about a firmware volume.
Prototype
typedef
(EFIAPI *EFI_FV_SET_INFO) (
IN CONST VOID *Buffer
);
This
A pointer to the EFI_FIRMWARE_VOLUME2_PROTOCOL instance that is the file handle the information is for.
III-3.4. DXE III-78UEFI Platform Initialization Specification, Release 1.8
The type identifier for the information being set. Type EFI_GUID is defined in the UEFI 2.0 specification.
The size, in bytes, of Buffer.
Buffer
A pointer to the data buffer to write. The buffer’s type is indicated by InformationType .
TheSetInfo() function sets information of type InformationType on the requested firmware volume.
Table 3.26: Status Codes Returned
EFI_WRITE_PROTECTED The media is read only.
EFI_BAD_BUFFER_SIZE BufferSize issmallerthanthesizeofthetypeindicatedby InformationType .
III-3.4.2 Firmware Volume Block2 Protocol
III-3.4.2.1 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
Summary
This optional protocol provides control over block-oriented firmware devices.
GUID
//{8F644FA9-E850-4db1-9CE2-0B44698E8DA4}
#define EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL_GUID \
{0x8f644fa9, 0xe850, 0x4db1, 0x9c, 0xe2, 0xb, 0x44, \
0x69, 0x8e, 0x8d, 0xa4}
typedef struct _EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL {
EFI_FVB_GET_ATTRIBUTES GetAttributes;
EFI_FVB_SET_ATTRIBUTES SetAttributes;
EFI_FVB_GET_PHYSICAL_ADDRESS GetPhysicalAddress;
EFI_FVB_GET_BLOCK_SIZE GetBlockSize;
EFI_FVB_READ Read;
EFI_FVB_WRITE Write;
EFI_FVB_ERASE_BLOCKS EraseBlocks;
} EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL;
III-3.4. DXE III-79UEFI Platform Initialization Specification, Release 1.8
GetAttributes
Retrieves the current volume attributes. See the GetAttributes() function description.
SetAttributes
Sets the current volume attributes. See the SetAttributes() function description.
GetPhysicalAddress
Retrieves the memory-mapped address of the firmware volume. See the GetPhysicalAddress() function
GetBlockSize
Retrieves the size for a specific block. Also returns the number of consecutive similarly sized blocks. See the
GetBlockSize() function description.
Read
Reads n bytes into a buffer from the firmware volume hardware. See the Read()function description.
Write
Writesnbytes from a buffer into the firmware volume hardware. See the Write() function description.
EraseBlocks
Erases specified block(s) and sets all values as indicated by the EFI_FVB_ERASE_POLARITY bit.
See the EraseBlocks() function description. Type EFI_FVB_ERASE_POLARITY is defined in
The Firmware Volume Block Protocol is the low-level interface to a firmware volume. File-level access to a firmware
volumeshouldnotbedoneusingtheFirmwareVolumeBlockProtocol. Normalaccesstoafirmwarevolumemustuse
theFirmwareVolumeProtocol. Typically,onlythefilesystemdriverthatproducestheFirmwareVolumeProtocolwill
bind to the Firmware Volume Block Protocol.
The Firmware Volume Block Protocol provides the following:
•Byte-level read/write functionality.
•Block-level erase functionality.
•It further exposes device-hardening features, such as may be required to protect the firmware from unwanted
overwriting and/or erasure.
•It is useful to layer a file system driver on top of the Firmware Volume Block Protocol. This file system driver
produces the Firmware Volume Protocol, which provides file-level access to a firmware volume. The Firmware
Volume Protocol abstracts the file system that is used to format the firmware volume and the hardware device-
hardening features that may be present.
III-3.4.2.2 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.GetAttributes()
Summary
Prototype
typedef
(EFIAPI * EFI_FVB_GET_ATTRIBUTES) (
III-3.4. DXE III-80UEFI Platform Initialization Specification, Release 1.8
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
OUT EFI_FVB_ATTRIBUTES_2 *Attributes
);
This
Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and current settings are returned. Type
EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER .
TheGetAttributes() function retrieves the attributes and current settings of the block.
Table 3.27: Status Codes Returned
III-3.4.2.3 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.SetAttributes()
Summary
Prototype
typedef
(EFIAPI * EFI_FVB_SET_ATTRIBUTES) (
IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
);
This
On input, Attributes is a pointer to EFI_FVB_ATTRIBUTES_2 that contains the desired firmware volume set-
tings. Onsuccessfulreturn,itcontainsthenewsettingsofthefirmwarevolume. Type EFI_FVB_ATTRIBUTES_2
is defined in EFI_FIRMWARE_VOLUME_HEADER .
TheSetAttributes() function sets configurable firmware volume attributes and returns the new settings of the
III-3.4. DXE III-81UEFI Platform Initialization Specification, Release 1.8
Table 3.28: Status Codes Returned
EFI_INVALID_PARAMETER The attributes requested are in conflict with the capabilities as declared in the
firmware volume header.
III-3.4.2.4 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.GetPhysicalAddress()
Summary
Retrieves the physical address of a memory-mapped firmware volume.
Prototype
typedef
(EFIAPI * EFI_FVB_GET_PHYSICAL_ADDRESS) (
OUT EFI_PHYSICAL_ADDRESS *Address
);
This
Address

Summary
Prototype
typedef
);
This
Address
Pointertoacaller-allocated EFI_PHYSICAL_ADDRESS that,onsuccessfulreturnfrom GetPhysicalAddress()
, contains the base address of the firmware volume. Type EFI_PHYSICAL_ADDRESS is defined in
TheGetPhysicalAddress() function retrieves the base address of a memory-mapped firmware volume. This func-
tion should be called only for memory-mapped firmware volumes.
Table 3.29: Status Codes Returned
EFI_SUCCESS The firmware volume base address is returned.
EFI_UNSUPPORTED The firmware volume is not memory mapped.
III-3.4.2.5 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.GetBlockSize()
Summary
Retrieves the size in bytes of a specific block within a firmware volume.
Prototype
typedef
(EFIAPI * EFI_FVB_GET_BLOCK_SIZE) (
IN EFI_LBA Lba,
OUT UINTN *BlockSize,
III-3.4. DXE III-82UEFI Platform Initialization Specification, Release 1.8
OUT UINTN *NumberOfBlocks
);
This
Lba
Indicates the block for which to return the size. Type EFI_LBA is defined in the BLOCK_IO Protocol (section
11.6) in the UEFI 2.0 specification.
BlockSize
Pointer to a caller-allocated UINTNin which the size of the block is returned.
NumberOfBlocks
Pointer to a caller-allocated UINTNin which the number of consecutive blocks, starting with Lba, is returned.
All blocks in this range have a size of BlockSize .
TheGetBlockSize() function retrieves the size of the requested block. It also returns the number of addi-
tional blocks with the identical size. The GetBlockSize() function is used to retrieve the block map (see
EFI_FIRMWARE_VOLUME_HEADER ).
Table 3.30: Status Codes Returned
EFI_INVALID_PARAMETER The requested LBA is out of range.
III-3.4.2.6 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.Read()
Summary
Reads the specified number of bytes into a buffer from the specified block.
Prototype
typedef
(EFIAPI *EFI_FVB_READ) (
IN OUT UINTN *NumBytes,
);
This
Lba
Thestartinglogicalblockindexfromwhichtoread. Type EFI_LBA isdefinedinthe BLOCK_IO Protocol(section
III-3.4. DXE III-83UEFI Platform Initialization Specification, Release 1.8
Offset
Offset into the block at which to begin reading.
NumBytes
Pointer to a UINTN. At entry, *NumBytes contains the total size of the buffer. At exit, *NumBytes contains the
total number of bytes read.
Buffer
Pointer to a caller-allocated buffer that will be used to hold the data that is read.
TheRead()function reads the requested number of bytes from the requested block and stores them in the provided
buffer.
Implementationsshouldbemindfulthatthefirmwarevolumemightbeinthe ReadDisabled state. Ifitisinthisstate,
theRead()function must return the status code EFI_ACCESS_DENIED without modifying the contents of the buffer.
TheRead()function must also prevent spanning block boundaries. If a read is requested that would span a block
boundary, the read must read up to the boundary but not beyond. The output parameter NumBytes must be set to
correctly indicate the number of bytes actually read. The caller must be aware that a read may be partially completed.
Table 3.31: Status Codes Returned
EFI_SUCCESS The firmware volume was read successfully and contents are in Buffer.
EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. On output, NumBytes contains the
total number of bytes returned in Buffer.
EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
EFI_DEVICE_ERROR The block device is not functioning correctly and could not be read.
III-3.4.2.7 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.Write()
Summary
Writes the specified number of bytes from the input buffer to the block.
Prototype
typedef
(EFIAPI * EFI_FVB_WRITE) (
IN UINT8 *Buffer
);
This
Lba
The starting logical block index to write to. Type EFI_LBA is defined in the BLOCK_IO Protocol (section 11.6)
in the UEFI 2.0 specification.
III-3.4. DXE III-84UEFI Platform Initialization Specification, Release 1.8
Offset
Offset into the block at which to begin writing.
NumBytes
total number of bytes actually written.
Buffer
Pointer to a caller-allocated buffer that contains the source for the write.
TheWrite() functionwritesthespecifiednumberofbytesfromtheprovidedbuffertothespecifiedblockandoffset.
If the firmware volume is sticky write, the caller must ensure that all the bits of the specified range to write are
in theEFI_FVB_ERASE_POLARITY state before calling the Write() function, or else the result will be unpre-
dictable. This unpredictability arises because, for a sticky-write firmware volume, a write may negate a bit in the
EFI_FVB_ERASE_POLARITY state but it cannot flip it back again. In general, before calling the Write() function,
the caller should call the EraseBlocks() function first to erase the specified block to write. A block erase cycle will
transition bits from the (NOT)EFI_FVB_ERASE_POLARITY state back to the EFI_FVB_ERASE_POLARITY state.
Implementations should be mindful that the firmware volume might be in the WriteDisabled state. If it is in this
state, theWrite() function must return the status code EFI_ACCESS_DENIED without modifying the contents of the
TheWrite() functionmustalsopreventspanningblockboundaries. Ifawriteisrequestedthatspansablockboundary,
thewritemuststoreuptotheboundarybutnotbeyond. Theoutputparameter NumBytes mustbesettocorrectlyindicate
the number of bytes actually written. The caller must be aware that a write may be partially completed.
All writes, partial or otherwise, must be fully flushed to the hardware before the Write() service returns.
Table 3.32: Status Codes Returned
EFI_SUCCESS The firmware volume was written successfully.
EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary. On output, NumBytes con-
tains the total number of bytes actually written.
EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
EFI_DEVICE_ERROR The block device is malfunctioning and could not be written.
III-3.4.2.8 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.EraseBlocks()
Summary
Erases and initializes a firmware volume block.
Prototype
typedef
(EFIAPI * EFI_FVB_ERASE_BLOCKS) (
...
);
This
III-3.4. DXE III-85UEFI Platform Initialization Specification, Release 1.8
...
The variable argument list is a list of tuples. Each tuple describes a range of LBAs to erase and consists of the
•AnEFI_LBA that indicates the starting LBA
•AUINTNthat indicates the number of blocks to erase
The list is terminated with an EFI_LBA_LIST_TERMINATOR . TypeEFI_LBA_LIST_TERMINATOR is defined in
“Related Definitions” below.
For example, the following indicates that two ranges of blocks (5-7 and 10-11) are to be erased:
EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
TheEraseBlocks() functionerasesoneormoreblocksasdenotedbythevariableargumentlist. Theentireparameter
listofblocksmustbeverifiedbeforeerasinganyblocks. Ifablockisrequestedthatdoesnotexistwithintheassociated
firmwarevolume(ithasalargerindexthanthelastblockofthefirmwarevolume),the EraseBlocks() functionmust
return the status code EFI_INVALID_PARAMETER without modifying the contents of the firmware volume.
state,theEraseBlocks() functionmustreturnthestatuscode EFI_ACCESS_DENIED withoutmodifyingthecontents
All calls to EraseBlocks() must be fully flushed to the hardware before the EraseBlocks() service returns.
// EFI_LBA_LIST_TERMINATOR
#define EFI_LBA_LIST_TERMINATOR 0xFFFFFFFFFFFFFFFF
Table 3.33: Status Codes Returned
EFI_SUCCESS The erase request was successfully completed.
EFI_DEVICE_ERROR The block device is not functioning correctly and could not be written. The
firmware device may have been partially erased.

EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable argument list do not exist in the
III-3.4.3 Guided Section Extraction Protocol
III-3.4.3.1 EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL
Summary
If a GUID-defined section is encountered when doing section extraction, the section extraction driver calls the appro-
priate instance of the GUIDed Section Extraction Protocol to extract the section stream contained therein.
GUID
Typically, protocol interface structures are identified by associating them with a GUID. Each instance of a protocol
with a given GUID must have the same interface structure. While all instances of the GUIDed Section Extraction
Protocolmusthavethesameinterfacestructure,theydonotallhavethesameGUID.TheGUIDthatisassociatedwith
III-3.4. DXE III-86UEFI Platform Initialization Specification, Release 1.8
an instance of the GUIDed Section Extraction Protocol is used to correlate it with the GUIDed section type that it is
intended to process.
typedef struct \_EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL {
EFI_EXTRACT_GUIDED_SECTION ExtractSection;
} EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL;
III-3.4.3.2 EFI_GUIDED_SECTION_EXTRACTION_PROCOCOL.ExtractSection()
Summary
Prototype
typedef
(EFIAPI *EFI_EXTRACT_GUIDED_SECTION)(
IN CONST EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL *This,
);
This
Indicates the EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL instance.
*OutputBuffer is allocated from boot services pool memory and contains the new section stream. The caller
is responsible for freeing this buffer.
A pointer to a caller-allocated UINT32that indicates the authentication status of the output buffer. If the input
section’sGuidedSectionHeader.Attributes field has the EFI_GUIDED_SECTION_AUTH_STATUS_VALID
bit as clear, *AuthenticationStatus must return zero. Both local bits (19:16) and aggregate bits (3:0) in
AuthenticationStatus are returned by ExtractSection() . These bits reflect the status of the extraction
operation. The bit pattern in both regions must be the same, as the local and aggregate authentication statuses
have equivalent meaning at this level. If the function returns anything other than EFI_SUCCESS , the value of
*AuthenticationStatus is undefined.
III-3.4. DXE III-87UEFI Platform Initialization Specification, Release 1.8
TheExtractSection() function processes the input section and allocates a buffer from the pool in which it returns
the section contents.
Dependingonthealgorithmandsizeoftheencapsulateddata,thetimethatisrequiredtodoafullauthenticationmaybe
prohibitivelylongforsomeclassesofsystems. Toindicatethis,use EFI_SECURITY_POLICY_PROTOCOL_GUID ,which
maybepublishedbythesecuritypolicydriver(seethe PlatformInitializationDriverExecutionEnvironmentCoreIn-
terfaceSpecification formoredetailsandtheGUIDdefinition). Ifthe EFI_SECURITY_POLICY_PROTOCOL_GUID exists
inthehandledatabase,then,ifpossible,fullauthenticationshouldbeskippedandthesectioncontentssimplyreturned
intheOutputBuffer . Inthiscase,the EFI_AUTH_STATUS_PLATFORM_OVERRIDE bitAuthenticationStatus must
be set on return. See “Related Definitions” in EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI.ExtractSection()
for the definition of type EFI_AUTH_STATUS_PLATFORM_OVERRIDE .
ExtractSection() is callable only from EFI_TPL_NOTIFY and below. Behavior of ExtractSection() at any
EFI_TPL aboveEFI_TPL_NOTIFY isundefined. Type EFI_TPL isdefinedin RaiseTPL() intheUEFI2.0specification.
Table 3.34: Status Codes Returned
EFI_SUCCESS TheInputSection was successfully processed and the section contents were
returned.
EFI_INVALID_PARAMETER TheGUIDin InputSection doesnotmatchthisinstanceoftheGUIDedSec-
tion Extraction Protocol.
III-3.5 SMM
III-3.5.1 SMM Firmware Volume Protocol
III-3.5.1.1 EFI_SMM_FIRMWARE_VOLUME_PROTOCOL
Summary
The Firmware Volume Protocol provides file-level access to the firmware volume in SMM.
GUID
#define EFI_SMM_FIRMWARE_VOLUME_PROTOCOL_GUID { \
0x19e9da84, 0x72b, 0x4274, 0xb3, 0x2e, 0xc, 0x8, 0x2, 0xe7,
0x17, 0xa5 \
}
Prototype
Same asEFI_FIRMWARE_VOLUME2_PROTOCOL ;
The function API is same as DXE version EFI_FIRMWARE_VOLUME2_PROTOCOL .
III-3.5. SMM III-88UEFI Platform Initialization Specification, Release 1.8
III-3.5.2 SMM Firmware Volume Block Protocol
III-3.5.2.1 EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL
Summary
This optional protocol provides control over block-oriented firmware devices in SMM.
GUID
#define EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID { \
0xd326d041, 0xbd31, 0x4c01, 0xb5, 0xa8, 0x62, 0x8b, 0xe8, 0x7f,
0x06, 0x53 \
}
Prototype
Same asEFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL ;
The function API is same as DXE version EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL .
III-3.5. SMM III-89CHAPTER
FOUR
HOB DESIGN DISCUSSION
III-4.1 Explanation of HOB Terms
Because HOBs are the key architectural mechanism that is used to hand off system information in the early preboot
stages and because not all implementations of the PI Architecture will use the Pre-EFI Initialization (PEI) and Driver
Execution Environment (DXE) phases, this specification refrains from using the PEI and DXE nomenclature used in
other PI specifications.
Instead, this specification uses the following terms to refer to the phases that deal with HOBs:
•HOB producer phase
•HOB consumer phase
TheHOBproducerphase istheprebootphaseinwhichHOBsandtheHOBlistarecreated. The HOBconsumerphase
is the preboot phase to which the HOB list is passed and then consumed.
If the PI Architecture implementation incorporates the PEI and DXE, the HOB producer phase is the PEI phase and
the HOB consumer phase is the DXE phase. The producer and consumer can change, however, depending on the
The following table translates the terminology used in this specification with that used in other PI specifications.
Table 4.1: Translation of HOB Specification Terminology
Term Used in the HOB Specification Term Used in Other PI Specifications
HOB producer phase PEI phase
HOB consumer phase DXE phase
executablecontentintheHOBproducer
phasePre EFI Initialization Module (PEIM)
hand-off into the HOB consumer phase DXE InitialProgram Load(IPL) PEIMor DXE IPLPEIM toPEIM In-
terface (PPI)
platform boot policy phase Boot Device Selection (BDS) phase
III-90UEFI Platform Initialization Specification, Release 1.8
III-4.2 HOB Overview
The HOB producer phase provides a simple mechanism to allocate memory for data storage during the phase’s exe-
cution. The data store is architecturally defined and described by HOBs. This data store is also passed to the HOB
producer phase when it is invoked from the HOB producer phase.
The basic container of data storage is named a Hand-Off Block, or HOB. HOBs are allocated sequentially in memory
that is available to executable content in the HOB producer phase. There are a series of services that facilitate HOB
manipulation. The sequential list of HOBs in memory will be referred to as the HOB list.
FordefinitionsofthevariousHOBtypes,see HOBCodeDefinitions below. Theconstructionsemanticsaredescribed
inConstructing the HOB List below.
III-4.3 Example HOB Producer Phase Memory Map and Usage
ExampleHOBProducerPhaseMemoryMapandUsage showsanexampleoftheHOBproducerphasememorymap
and its usage. This map is a possible means by which to subdivide the region.
Fig. 4.1: Example HOB Producer Phase Memory Map and Usage
III-4.4 HOB List
The first HOB in the HOB list must be the Phase Handoff Information Table (PHIT) HOB. The last HOB in the HOB
list must be the End of HOB List HOB.
OnlyHOBproducerphasecomponentsareallowedtomakeadditionsorchangestoHOBs. OncetheHOBlistispassed
into the HOB consumer phase, it is effectively read only. The ramification of a read-only HOB list is that handoff

information,suchasbootmode,mustbehandledinadistinguishedfashion. Forexample,iftheHOBconsumerphase
weretoengenderarecoverycondition,itwouldnotupdatethebootmodebutinsteadwouldimplementtheactionusing
a special type of reset call. The HOB list contains system state data at the time of HOB producer-to-HOB producer
handoff and does not represent the current system state during the HOB consumer phase.
III-4.2. HOB Overview III-91UEFI Platform Initialization Specification, Release 1.8
III-4.5 Constructing the HOB List
III-4.5.1 Constructing the Initial HOB List
TheHOBlistisinitiallybuiltbytheHOBproducerphase. TheHOBlistiscreatedinmemorythatispresent,initialized,
and tested. Once the initial HOB list has been created, the physical memory cannot be remapped, interleaved, or
otherwise moved by a subsequent software agent.
TheHOBproducerphase mustbuildthefollowingthreeHOBsintheinitialHOBlistbeforeexposingthelisttoother
modules:
•The PHIT HOB
•A memory allocation HOB describing where the boot-strap processor (BSP) stack for permanent memory is
located
or
AmemoryallocationHOBdescribingwheretheBSPstoreforpermanentmemoryislocated(Itanium ®proces-
sor family only)
•A resource descriptor HOB that describes a physical memory range encompassing the HOB producer phase
memory range with its attributes set as present, initialized, and tested
TheHOBlistcreatormaybuildmoreHOBsintotheinitialHOBlist,suchasadditionalHOBstodescribeotherphysical
memory ranges. There can also be additional modules, which might include a HOB producer phase-specific HOB to
record memory errors discovered during initialization.
When the HOB producer phase completes its list creation, it exposes a pointer to the PHIT HOB to other modules.
III-4.5.2 HOB Construction Rules
HOB construction must obey the following rules:
1. All HOBs must start with a HOB generic header. This requirement allows users to locate the HOBs in which
they are interested while skipping the rest. See the EFI_HOB_GENERIC_HEADER definition.
2. HOBsmaycontainbootservicesdatathatisavailableduringtheHOBproducerandconsumerphasesonlyuntil
the HOB consumer phase is terminated.
3. HOBs may be relocated in system memory by the HOB consumer phase. HOBs must not contain pointers to
other data in the HOB list, including that in other HOBs. The table must be able to be copied without requiring
internal pointer adjustment.
4. AllHOBsmustbemultiplesof8bytesinlength. ThisrequirementmeetsthealignmentrestrictionsoftheItanium
®processor family.
5. The PHIT HOB must always begin on an 8-byte boundary. Due to this requirement and requirement #4 in this
list, all HOBs will begin on an 8-byte boundry
6. HOBsareaddedtotheendoftheHOBlist. HOBscanonlybeaddedtotheHOBlistduringtheHOBproducer
phase, not the HOB consumer phase.
7. HOBscannotbedeleted. ThegenericHOBheaderofeachHOBmustdescribethelengthoftheHOBsothatthe
nextHOBcanbefound. AprivateGUIDedHOBmayprovideamechanismtomarksomeoritsentirecontents
invalid; however, this mechanism is beyond the scope of this document.
Note: The HOB list must be valid (i.e., no HOBs “under construction”) when any HOB producer phase service is
invoked. AnotherHOBproducerphasecomponent’sfunctionmightwalktheHOBlist,andifaHOBheadercontains
invalid data, it might cause unreliable operation.
III-4.5. Constructing the HOB List III-92UEFI Platform Initialization Specification, Release 1.8
III-4.5.3 Adding to the HOB List
To add a HOB to the HOB list, HOB consumer phase software must obtain a pointer to the PHIT HOB (start of the
HOB list) and follow these steps:
1. Determine NewHobSize , whereNewHobSize is the size in bytes of the HOB to be created.
2. CheckfreememorytoensurethatthereisenoughfreememorytoallocatethenewHOB.Thistestisperformed
by checking that NewHobSize <= PHIT-> EfiFreeMemoryTop - PHIT->EfiFreeMemoryBottom ).
3. Construct the HOB at PHIT-> EfiFreeMemoryBottom .
4. Set PHIT-> EfiFreeMemoryBottom = PHIT-> EfiFreeMemoryBottom +NewHobSize .
III-4.5. Constructing the HOB List III-93CHAPTER
FIVE
HOB CODE DEFINITIONS
III-5.1 HOB Introduction
This section contains the basic definitions of various HOBs. All HOBs consist of a generic header,
EFI_HOB_GENERIC_HEADER ,thatspecifiesthetypeandlengthoftheHOB.EachHOBhasadditionaldatabeyondthe
generic header, according to the HOB type. The following data types and structures are defined in this section:
•EFI_HOB_GENERIC_HEADER
•EFI_HOB_HANDOFF_INFO_TABLE
•EFI_HOB_MEMORY_ALLOCATION
•EFI_HOB_MEMORY_ALLOCATION_STACK
•EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
•EFI_HOB_MEMORY_ALLOCATION_MODULE
•EFI_HOB_RESOURCE_DESCRIPTOR
•EFI_HOB_GUID_TYPE
•EFI_HOB_FIRMWARE_VOLUME
•EFI_HOB_FIRMWARE_VOLUME2
•EFI_HOB_FIRMWARE_VOLUME3
•EFI_HOB_CPU
•EFI_HOB_MEMORY_POOL
•EFI_HOB_UEFI_CAPSULE
•EFI_HOB_TYPE_UNUSED
•EFI_HOB_TYPE_END_OF_HOB_LIST
in which they are called. The following types or structures can be found in “Related Definitions” of the parent data
structure definition:
•EFI_HOB_MEMORY_ALLOCATION_HEADER
•EFI_RESOURCE_TYPE
•EFI_RESOURCE_ATTRIBUTE_TYPE
III-94UEFI Platform Initialization Specification, Release 1.8
III-5.2 HOB Generic Header
III-5.2.1 EFI_HOB_GENERIC_HEADER
Summary
Describes the format and size of the data inside the HOB. All HOBs must contain this generic HOB header.
Prototype
typedef struct _EFI_HOB_GENERIC_HEADER{
UINT16 HobType;
UINT16 HobLength;
} EFI_HOB_GENERIC_HEADER;
HobType
Identifies the HOB data structure type. See “Related Definitions” below for the HOB types that are defined in
this specification.
HobLength
The length in bytes of the HOB.
Reserved
For this version of the specification, this field must always be set to zero.
All HOBs have a common header that is used for the following:
•Traversing to the next HOB
•Describing the format and size of the data inside the HOB
The following values for HobType are defined by this specification.
// HobType values
#define EFI_HOB_TYPE_HANDOFF 0x0001
#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
#define EFI_HOB_TYPE_FV 0x0005
#define EFI_HOB_TYPE_CPU 0x0006
#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
#define EFI_HOB_TYPE_FV2 0x0009
#define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A
#define EFI_HOB_TYPE_UEFI_CAPSULE 0x000B
#define EFI_HOB_TYPE_FV3 0x000C
#define EFI_HOB_TYPE_UNUSED 0xFFFE
#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
Other values for HobType are reserved for future use by this specification.
III-5.2. HOB Generic Header III-95UEFI Platform Initialization Specification, Release 1.8
III-5.3 PHIT HOB
III-5.3.1 EFI_HOB_HANDOFF_INFO_TABLE (PHIT HOB)
Summary
Contains general state information used by the HOB producer phase. This HOB must be the first one in the HOB list.
Prototype
typedef struct _EFI_HOB_HANDOFF_INFO_TABLE {
EFI_HOB_GENERIC_HEADER Header;
EFI_BOOT_MODE BootMode;
EFI_PHYSICAL_ADDRESS EfiMemoryTop;
EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
EFI_PHYSICAL_ADDRESS EfiEndOfHobList;
} EFI_HOB_HANDOFF_INFO_TABLE;
Header
The HOB generic header. Header.HobType =EFI_HOB_TYPE_HANDOFF .
Version
The version number pertaining to the PHIT HOB definition. See “Related Definitions” below for the version
numbers defined by this specification. This value is 4 bytes in length to provide an 8-byte aligned entry when it
is combined with the 4-byte BootMode .
BootMode
ThesystembootmodeasdeterminedduringtheHOBproducerphase. Type EFI_BOOT_MODE isaUINT32;ifthe
PI Architecture-compliant implementation incorporates the PEI phase, the possible bit values are defined in the
Platform Initialization Pre-EFI Initialization Core Interface Specification (PEI CIS).
EfiMemoryTop
The highest address location of memory that is allocated for use by the HOB producer phase. This ad-
dress must be 4-KiB aligned to meet page restrictions of UEFI. Type EFI_PHYSICAL_ADDRESS is defined in
EfiMemoryBottom
The lowest address location of memory that is allocated for use by the HOB producer phase.
EfiFreeMemoryTop
ThehighestaddresslocationoffreememorythatiscurrentlyavailableforusebytheHOBproducerphase. This
address must be 4-KiB aligned to meet page restrictions of UEFI.
EfiFreeMemoryBottom
The lowest address location of free memory that is available for use by the HOB producer phase.
EfiEndOfHobList
The end of the HOB list.
The Phase Handoff Information Table (PHIT) HOB must be the first one in the HOB list. A pointer to this HOB is
availabletoaHOBproducerphasecomponentthroughsomeservice. ThisspecificationcommonlyreferstothisHOB
as the PHIT HOB, or sometimes the handoff HOB.

III-5.3. PHIT HOB III-96UEFI Platform Initialization Specification, Release 1.8
The HOB consumer phase reads the PHIT HOB during its initialization.
// Version values
#define EFI_HOB_HANDOFF_TABLE_VERSION 0x000a
III-5.4 Memory Allocation HOB
III-5.4.1 Memory Allocation HOB
III-5.4.1.1 EFI_HOB_MEMORY_ALLOCATION
Summary
Describes all memory ranges used during the HOB producer phase that exist outside the HOB list. This HOB type
describes how memory is used, not the physical attributes of memory.
Prototype
typedef struct _EFI_HOB_MEMORY_ALLOCATION {
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
//
// Additional data pertaining to the “Name” Guid memory
// may go here.
//
} EFI_HOB_MEMORY_ALLOCATION;
Header
The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION .
AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi-
cal memory allocation. The type field will be used for subsequent inclusion in the UEFI memory map. Type
EFI_HOB_MEMORY_ALLOCATION_HEADER is defined in “Related Definitions” below.
ThememoryallocationHOBisusedtodescribememoryusageoutsidetheHOBlist. TheHOBconsumerphasedoes
not make assumptions about the contents of the memory that is allocated by the memory allocation HOB, and it will
not move the data unless it has explicit knowledge of the memory allocation HOB’s Name(EFI_GUID ). Memory may
be allocated in either the HOB producer phase memory area or other areas of present and initialized system memory.
The HOB consumer phase reads all memory allocation HOBs and allocates memory into the system memory map
based on the following fields of EFI_HOB_MEMORY_ALLOCATION_HEADER of each memory allocation HOB:
•MemoryBaseAddress
•MemoryLength
•MemoryType
III-5.4. Memory Allocation HOB III-97UEFI Platform Initialization Specification, Release 1.8
TheHOBconsumerphasedoesnotparsetheGUID-specificdataidentifiedbythe Namefieldofeachmemoryallocation
HOB,exceptforaspecificsetofmemoryallocationHOBsthatdefinedbythisspecification. AHOBconsumerphase
driver that corresponds to the specific NameGUIDed memory allocation HOB can parse the HOB list to find the
specificallynamedmemoryallocationHOBandthenmanipulatethememoryspaceasdefinedbytheusagemodelfor
that GUID.
Note: SpecialdesigncareshouldbetakentoensurethattwoHOBconsumerphasecomponentsdonotmodifymemory
space that is described by a memory allocation HOB, because unpredictable behavior might result.
This specification defines a set of memory allocation HOBs that are architecturally used to allocate memory used by
theHOBproducerandconsumerphases. Additionally,thefollowingmemoryallocationHOBsaredefinedspecifically
for use by the final stage of the HOB producer phase to describe the processor state prior to handoff into the HOB
consumer phase:
•BSP stack memory allocation HOB
•BSP store memory allocation HOB
•Memory allocation module HOB
// EFI_HOB_MEMORY_ALLOCATION_HEADER
typedef struct _EFI_HOB_MEMORY_ALLOCATION_HEADER {
EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
UINT64 MemoryLength;
EFI_MEMORY_TYPE MemoryType; // UINT32
UINT8 Reserved[4]; // Padding for Itanium ®
// processor family
} EFI_HOB_MEMORY_ALLOCATION_HEADER;
Name
A GUID that defines the memory allocation region’s type and purpose, as well as other fields within the mem-
ory allocation HOB. This GUID is used to define the additional data within the HOB that may be present for
the memory allocation HOB. Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
MemoryBaseAddress
The base address of memory allocated by this HOB. Type EFI_PHYSICAL_ADDRESS is defined in
The length in bytes of memory allocated by this HOB.
DefinesthetypeofmemoryallocatedbythisHOB.Thememorytypedefinitionfollowsthe EFI_MEMORY_TYPE
definition. Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0 specification.
Reserved For this version of the specification, this field will always be set to zero.
Note:MemoryBaseAddress andMemoryLength musteachhave4-KiBgranularitytomeetthepagesizerequirements
of UEFI.
III-5.4. Memory Allocation HOB III-98UEFI Platform Initialization Specification, Release 1.8
III-5.4.2 Boot-Strap Processor (BSP) Stack MemoryAllocation HOB
III-5.4.2.1 EFI_HOB_MEMORY_ALLOCATION_STACK
Summary
Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed
executable content in the HOB producer phase is executing.
GUID
#define EFI_HOB_MEMORY_ALLOC_STACK_GUID \
{0x4ed4bf27, 0x4092, 0x42e9, 0x80, 0x7d, 0x52, 0x7b, \
0x1d, 0x0, 0xc9, 0xbd}
Prototype
typedef struct _EFI_HOB_MEMORY_ALLOCATION_STACK {
} EFI_HOB_MEMORY_ALLOCATION_STACK;
Header
The HOB generic header. Header.HobType =EFI_HOB_TYPE_MEMORY_ALLOCATION .
EFI_HOB_MEMORY_ALLOCATION_HEADER is defined in EFI_HOB_MEMORY_ALLOCATION .
ThisHOBdescribesthememorystackthatisproducedbytheHOBproducerphaseanduponwhichallpost-memory-
installed executable content in the HOB producer phase is executing. It is necessary for the hand-off into the HOB
consumerphasetoknowthisinformationsothatitcanappropriatelymapthisstackintoitsownexecutionenvironment
and describe it in any subsequent memory maps.
The HOB consumer phase reads this HOB during its initialization. The HOB consumer phase may elect to move
or relocate the BSP’s stack to meet size and location requirements that are defined by the HOB consumer phase’s
implementation. Therefore, other HOB consumer phase components cannot rely on the BSP stack memory allocation
HOB to describe where the BSP stack is located during execution of the HOB consumer phase.
Note: BSP stack memory allocation HOB must be valid at the time of hand off to the HOB consumer phase. If BSP
stack is reallocated during HOB producer phase, the component that reallocates the stack must also update BSP stack
memory allocation HOB.
The BSP stack memory allocation HOB without any additional qualification describes either of the following:
•The stack that is currently consumed by the BSP.
•The processor that is currently executing the HOB producer phase and its executable content.
•ThemodelforthePIarchitectureandtheHOBproducerphaseisthatofasingle-threadedexecutionenvironment,
so it is this single, distinguished thread of control whose environment is described by this HOB. The Itanium
®processor family has the additional requirement of having to describe the value of the BSPSTORE (AR18)
(“Backing Store Pointer Store”) register, which holds the successive location in memory where the Itanium
processor family Register Stack Engine (RSE) will spill its values.
III-5.4. Memory Allocation HOB III-99UEFI Platform Initialization Specification, Release 1.8
•In addition, Itanium ®-based systems feature a system architecture where all processors come out of reset and
executetheresetpathconcurrently. Assuch,thestackresourcesthatareconsumedbythesealternateagentsneed
to be described even though they are not responsible for executing the main thread of control through the HOB
producer and consumer phases.
III-5.4.3 Boot-Strap Processor (BSP) BSPSTORE MemoryAllocation HOB
III-5.4.3.1 EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Note: This HOB is valid for the Itanium ®processor family only.
Summary
Defines the location of the boot-strap processor (BSP) BSPStore (“Backing Store Pointer Store”) register overflow
store.
GUID
#define EFI_HOB_MEMORY_ALLOC_BSP_STORE_GUID \
{0x564b33cd, 0xc92a, 0x4593, 0x90, 0xbf, 0x24, 0x73, \
0xe4, 0x3c, 0x63, 0x22}
Prototype
typedef struct _EFI_HOB_MEMORY_ALLOCATION_BSP_STORE {
} EFI_HOB_MEMORY_ALLOCATION_BSP_STORE;
Header
EFI_HOB_MEMORY_ALLOCATION_HEADERisdefinedintheHOBtype EFI_HOB_MEMORY_ALLOCATION
.
The HOB consumer phase reads this HOB during its initialization. The HOB consumer phase may elect to move or
relocatetheBSP’sregisterstoretomeetsizeandlocationrequirementsthataredefinedbytheHOBconsumerphase’s

store.
GUID
Prototype
Header
.
implementation. Therefore, other HOB consumer phase components cannot rely on the BSP store memory allocation
HOB to describe where the BSP store is located during execution of the HOB consumer phase.
Note: BSPBSPSTOREmemoryallocationHOBmustbevalidatthetimeofhandofftotheHOBconsumerphase. If
BSPBSPSTOREisreallocatedduringHOBproducerphase,thecomponentthatreallocatesthestackmustalsoupdate
BSP BSPSTORE memory allocation HOB.
This HOB is valid for the Itanium processor family only.
III-5.4. Memory Allocation HOB III-100UEFI Platform Initialization Specification, Release 1.8
III-5.4.4 Memory Allocation Module HOB
III-5.4.4.1 EFI_HOB_MEMORY_ALLOCATION_MODULE
Summary
Defines the location and entry point of the HOB consumer phase.
GUID
#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \
{0xf8e21975, 0x899, 0x4f58, 0xa4, 0xbe, 0x55, 0x25, \
0xa9, 0xc6, 0xd7, 0x7a}
Prototype
EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader;
EFI_GUID ModuleName;
EFI_PHYSICAL_ADDRESS EntryPoint;
} EFI_HOB_MEMORY_ALLOCATION_MODULE;
Header
MemoryAllocationHeader
EFI_HOB_MEMORY_ALLOCATION_HEADER is defined in the HOB type EFI_HOB_MEMORY_ALLOCATION .
ModuleName
The GUID specifying the values of the firmware file system name that contains the HOB consumer phase com-
ponent. Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0 specification.
Theaddressofthememory-mappedfirmwarevolumethatcontainstheHOBconsumerphasefirmwarefile. Type
The HOB consumer phase reads the memory allocation module HOB during its initialization. This HOB describes
thememorylocationoftheHOBconsumerphase. TheHOBconsumerphaseshouldusetheinformationtocreatethe
image handle for the HOB consumer phase.
III-5.5 Resource Descriptor HOB
III-5.5.1 EFI_HOB_RESOURCE_DESCRIPTOR
Summary
Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during
the HOB producer phase.
Prototype
III-5.5. Resource Descriptor HOB III-101UEFI Platform Initialization Specification, Release 1.8
typedef struct _EFI_HOB_RESOURCE_DESCRIPTOR {
EFI_RESOURCE_TYPE ResourceType;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
UINT64 ResourceLength;
} EFI_HOB_RESOURCE_DESCRIPTOR;
Header
The HOB generic header. Header.HobType =EFI_HOB_TYPE_RESOURCE_DESCRIPTOR .
Owner
A GUID representing the owner of the resource. This GUID is used by HOB consumer phase components to
correlate device ownership of a resource.
ResourceType
Resourcetype enumerationas definedby EFI_RESOURCE_TYPE .TypeEFI_RESOURCE_TYPE isdefined in“Re-
ResourceAttribute
Resourceattributesasdefinedby EFI_RESOURCE_ATTRIBUTE_TYPE .TypeEFI_RESOURCE_ATTRIBUTE_TYPE
PhysicalStart
Physical start address of the resource region. Type EFI_PHYSICAL_ADDRESS is defined in AllocatePages()
ResourceLength
Number of bytes of the resource region.
The resource descriptor HOB describes the resource properties of all fixed, nonrelocatable resource ranges found on
the processor host bus during the HOB producer phase. This HOB type does not describe how memory is used but
instead describes the attributes of the physical memory present.
TheHOBconsumerphasereadsallresourcedescriptorHOBswhenitestablishedtheinitialGlobalCoherencyDomain
(GCD) map. The minimum requirement for the HOB producer phase is that executable content in the HOB producer
phase report one of the following:
•The resources that are necessary to start the HOB consumer phase
•The fixed resources that are not captured by HOB consumer phase driver components that were started prior to
the dynamic system configuration performed by the platform boot-policy phase
Forexample,executablecontentintheHOBproducerphaseshouldreportanyphysicalmemoryfoundduringtheHOB
producer phase. Another example is reporting the Boot Firmware Volume (BFV) that contains firmware volume(s).
ExecutablecontentintheHOBproducerphasedoesnotneedtoreportfixedsystemresourcessuchasI/Oport70h/71h
(real-time clock) because these fixed resources can be allocated from the GCD by a platform-specific chipset driver
loading in the HOB consumer phase prior to the platform boot-policy phase, for example.
Current thinking is that the GCD does not track the HOB’s OwnerGUID, so a HOB consumer phase component that
assumesownershipofadevice’sresourcemustdeallocatetheresourceinitializedbytheHOBproducerphasefromthe
GCD before attempting to assign the devices resource to itself in the HOB consumer phase.
There can only be a single ResourceType field, characterized as follows.
III-5.5. Resource Descriptor HOB III-102UEFI Platform Initialization Specification, Release 1.8
// EFI_RESOURCE_TYPE
typedef UINT32 EFI_RESOURCE_TYPE;
#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
#define EFI_RESOURCE_IO 0x00000002
#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
#define EFI_RESOURCE_IO_RESERVED 0x00000006
#define EFI_RESOURCE_MEMORY_UNACCEPTED 0x00000007
#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000008
The following table describes the fields listed in the above definition.
EFI_RESOURCE_SYSTEM_MEMORY Memory that persists out of the HOB producer phase.
EFI_RESOURCE_MEMORY_MAPPED_IO Memory-mapped I/O that is programmed in the HOB
producer phase.
EFI_RESOURCE_IO Processor I/O space.
EFI_RESOURCE_FIRMWARE_DEVICE Memory-mapped firmware devices.
EFI_RESOURCE_MEMORY_MAPPED_IO_PORT Memory that is decoded to produce I/O cycles.
EFI_RESOURCE_MEMORY_RESERVED Reserved memory address space.
EFI_RESOURCE_IO_RESERVED Reserved I/O address space.
EFI_RESOURCE_MEMORY_UNACCEPTED Memory that is unaccepted.
EFI_RESOURCE_MAX_MEMORY_TYPE Any reported HOB value of this type or greater should
be deemed illegal. This value could increase with suc-
cessiverevisionsofthisspecification,sothe“illegality”
will also be based upon the revision field of the PHIT
HOB
TheResourceAttribute field is characterized as follows:
// EFI_RESOURCE_ATTRIBUTE_TYPE
typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
// These types can be ORed together asneeded.
//
// The following attributes are used to describe settings
//
#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
III-5.5. Resource Descriptor HOB III-103UEFI Platform Initialization Specification, Release 1.8
#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED
0x00000200
#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000
#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000
// The rest of the attributes are used to describe capabilities
//
#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000
#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE 0x00100000
#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000
#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000
#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000
#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000
#define EFI_RESOURCE_ATTRIBUTE_ENCRYPTED 0x04000000
#define EFI_RESOURCE_ATTRIBUTE_SPECIAL_PURPOSE 0x08000000
III-5.5. Resource Descriptor HOB III-104UEFI Platform Initialization Specification, Release 1.8
Table 5.1: EFI_RESOURCE_ATTRIBUTE_TYPE fields

EFI_RESOURCE_ATTRIBUTE_PRESENT Physical memory attribute: The memory region exists.
EFI_RESOURCE_ATTRIBUTE_INITIALIZED Physical memory attribute: The memory region has
been initialized.
EFI_RESOURCE_ATTRIBUTE_TESTED Physical memory attribute: The memory region has
been tested.
EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC Physical memory attribute: The memory region sup-
ports single-bit ECC.
EFI_RESOURCE_ATTRIBUTE _MULTI-
PLE_BIT_ECCPhysical memory attribute: The memory region sup-
ports multibit ECC.
EFI_RESOURCE_ATTRIBUTE_ECC _RE-
SERVED_1Physical memory attribute: The memory region sup-
ports reserved ECC.
SERVED_2Physical memory attribute: The memory region sup-
EFI_RESOURCE_ATTRIBUTE_READ _PRO-
TECTEDPhysical memory protection attribute: The memory re-
gion is read protected.
EFI_RESOURCE_ATTRIBUTE_WRITE _PRO-
TECTEDPhysical memory protection attribute: The memory
region is write protected. This is typically used as
memory cacheability attribute today. NOTE: Since PI
spec 1.4, please use EFI_RESOURCE_ATTRIBUTE
_READ_ONLY_PROTECTED as Physical write pro-
tected attribute, and EFI_RESOURCE_ATTRIBUTE
_WRITE_PROTECTED means Memory cacheability
attribute: Thememorysupportsbeingprogrammedwith
a write-protected cacheable attribute.
EFI_RESOURCE_ATTRIBUTE _EXECU-
TION_PROTECTEDPhysical memory protection attribute: The memory re-
gion is execution protected.
EFI_RESOURCE_ATTRIBUTE
_READ_ONLY_PROTECTEDPhysical memory protection attribute: The memory re-
gion is write protected.
EFI_RESOURCE_ATTRIBUTE_PERSISTENT Physical memory persistence attribute: This memory is
configured for byte-addressable non-volatility.
EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE Physical memory relative reliability attribute: This
memory provides higher reliability relative to other
memory in the system. If all memory has the same reli-
ability, then this bit is not used.
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE Memory cacheability attribute: The memory does not
support caching.
TECTABLEMemory capability attribute: The memory supports be-
ing protected from processor reads.
TECTABLEMemory capability attribute: The memory sup-
ports being protected from processor writes.
This is typically used as memory cacheabil-
ity attribute today. NOTE: Since PI spec 1.4,
please use EFI_RESOURCE_ATTRIBUTE
_READ_ONLY_PROTECTABLE as Memory capabil-
ityattribute: Thememorysupportsbeingprotectedfrom
processor writes, and EFI_RESOURCE_ATTRIBUTE
_WRITE_PROTECTABLE means Memory cacheabil-
ity attribute: The memory supports being programmed
with a write-protected cacheable attribute.
EFI_RESOURCE_ATTRIBUTE_EXECUTION
_PROTECTABLEMemory capability attribute: The memory supports be-
ing protected from processor execution.
EFI_RESOURCE_ATTRIBUTE_READ_ONLY
ing protected from processor writes.
EFI_RESOURCE_ATTRIBUTE_PERSISTABLE Memory capability attribute: This memory supports
byte-addressable non-volatility.
EFI_RESOURCE_ATTRIBUTE_WRITE
_THROUGH_CACHEABLEMemory cacheability attribute: The memory supports
being programmed with a write-through cacheable at-
tribute.
EFI_RESOURCE_ATTRIBUTE_WRITE _COM-
BINEABLEMemorycacheabilityattribute: Thememorysupportsa
write-combining attribute.
_BACK_CACHEABLEMemorycacheabilityattribute: Thememoryregionsup-
ports being configured as cacheable with a write-back
policy. Reads and writes that hit in the cache do not
propagate to main memory. Dirty data is written back
to main memory when a new cache line is allocated.
EFI_RESOURCE_ATTRIBUTE _16_BIT_IO Memory physical attribute: The memory supports 16-
bit I/O.
EFI_RESOURCE_ATTRIBUTE _32_BIT_IO Memory physical attribute: The memory supports 32-
bit I/O.
EFI_RESOURCE_ATTRIBUTE _64_BIT_IO Memory physical attribute: The memory supports 64-
bit I/O.
EFI_RESOURCE_ATTRIBUTE _UN-
CACHED_EXPORTEDMemory cacheability attribute: The memory region is
uncacheableandexportedandsupportsthefetchandadd
semaphore mechanism.
EFI_RESOURCE_ATTRIBUTE_ENCRYPTED Ifthisflagisset,thememoryregioniscapableofbeing
protected with the CPU’s memory cryptographic capa-
bilities. Ifthisflagisclear,thememoryregionisnotca-
pable of being protected with the CPU’s memory cryp-
tographiccapabilitiesortheCPUdoesnotsupportCPU
memory cryptographic capabilities.
EFI_RESOURCE_ATTRIBUTE_SPECIAL_PURPOSE Ifthisflagisset,thememoryregioniscapableofbeing
aSpecific-purposememory(SPM).Thememoryisear-
marked for specific purposes such as for specific device
drivers or applications. The SPM attribute serves as a
hint to the OS to avoid allocating this memory for core
OSdataorcodethatcannotberelocated. Prolongeduse
ofthismemoryforpurposesotherthantheintendedpur-
pose may result in suboptimal platform performance.III-5.5. Resource Descriptor HOB III-105UEFI Platform Initialization Specification, Release 1.8
HOB Producer Phase Resource Types specifies the resource attributes applicable to each resource type.
Table 5.2: HOB Producer Phase Resource Types
EFI_RESOURCE_ATTRIBUTE_TYPE HOB Producer-
Phase System-
MemoryHOB
ProducerPhaseMemory-
MappedI/OHOB Producer-
Phase I/O
Present X
Initialized X
Tested X
SingleBitEcc X
MultipleBitEcc X
EccReserved1 X
EccReserved2 X
ReadProtected X X
WriteProtected X X
ExecutionProtected X
ReadOnlyProtected X X
Uncacheable X X
ReadProtectable X X
WriteProtectable X X
ExecutionProtectable X
ReadOnlyProtectable X X
WriteThroughCacheable X X
WriteCombineable X X
WriteBackCacheable X X
16bitIO X
32bitIO X
64bitIO X
UncachedExported X X
III-5.6 GUID Extension HOB
III-5.6.1 EFI_HOB_GUID_TYPE
Summary
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs whose types are not
included in this specification. Specifically, writers of executable content in the HOB producer phase can generate a
GUID and name their own HOB entries using this module-specific value.
Prototype
typedef struct _EFI_HOB_GUID_TYPE {
//
// Guid specific data goes here
//
} EFI_HOB_GUID_TYPE;
III-5.6. GUID Extension HOB III-106UEFI Platform Initialization Specification, Release 1.8
Header
The HOB generic header. Header.HobType =EFI_HOB_TYPE_GUID_EXTENSION .
Name
A GUID that defines the contents of this HOB. Type EFI_GUID is defined in InstallProtocolInterface()
The GUID extension HOB allows writers of executable content in the HOB producer phase to create their own HOB
definitionsusingaGUID.ThisHOBtypeshouldbeusedbyallexecutablecontentintheHOBproducerphasetodefine
implementation-specific data areas that are not architectural. This HOB type may also pass implementation-specific
data from executable content in the HOB producer phase to drivers in the HOB consumer phase.
AHOBconsumerphasecomponentsuchasaHOBconsumerphasedriverwillreadtheGUIDextensionHOBduring
the HOB consumer phase. The HOB consumer phase component must inherently know the GUID for the GUID
extension HOB for which it is scanning the HOB list. This knowledge establishes a contract on the HOB’s definition
and usage between the executable content in the HOB producer phase and the HOB consumer phase driver.
III-5.7 Firmware Volume HOB
III-5.7.1 EFI_HOB_FIRMWARE_VOLUME
Summary
Details the location of firmware volumes that contain firmware files.
Prototype
} EFI_HOB_FIRMWARE_VOLUME;
Header
The HOB generic header. Header.HobType =EFI_HOB_TYPE_FV .
The physical memory-mapped base address of the firmware volume. Type EFI_PHYSICAL_ADDRESS is defined
inAllocatePages() in the UEFI 2.0 specification.
Length
The length in bytes of the firmware volume.
The firmware volume HOB details the location of firmware volumes that contain firmware files. It includes a base
address and length. In particular, the HOB consumer phase will use these HOBs to discover drivers to execute and
the hand-off into the HOB consumer phase will use this HOB to discover the location of the HOB consumer phase
firmware file.
The firmware volume HOB is produced in the following ways:
•BytheexecutablecontentintheHOBproducerphaseintheBootFirmwareVolume(BFV)thatunderstandsthe
size and layout of the firmware volume(s) that are present in the platform.
III-5.7. Firmware Volume HOB III-107UEFI Platform Initialization Specification, Release 1.8
•By a module that has loaded a firmware volume from some media into memory. The firmware volume HOB
details this memory location.
Firmware volumes described by the firmware volume HOB must have a firmware volume header as described in this
The HOB consumer phase consumes all firmware volume HOBs that are presented by the HOB producer phase for
use by its read-only support for the PI Firmware Image Format. The HOB producer phase is required to describe any

firmware volumes that may contain the HOB consumer phase or platform drivers that are required to discover other
firmware volumes.
III-5.7.2 EFI_HOB_FIRMWARE_VOLUME2
Summary
Details the location of a firmware volume which was extracted from a file within another firmware volume.
Prototype
} EFI_HOB_FIRMWARE_VOLUME2;
Header
The HOB generic header. Header.HobType =EFI_HOB_TYPE_FV2 .
inAllocatePages() in theUnified Extensible Firmware Interface Specification , version 2.0.
Length
FvName
The name of the firmware volume.
FileName
The name of the firmware file which contained this firmware volume.
The firmware volume HOB details the location of a firmware volume that was extracted prior to the HOB consumer
phase from a file within a firmware volume. By recording the volume and file name, the HOB consumer phase can
avoid processing the same file again.
ThisHOBiscreatedbyamodulethathasloadedafirmwarevolumefromanotherfileintomemory. ThisHOBdetails
the base address, the length, the file name and volume name.
TheHOBconsumerphaseconsumesallfirmwarevolumeHOBsthatarepresentedbytheHOBproducerphaseforuse
by its read-only support for the PI Firmware Image format.
III-5.7. Firmware Volume HOB III-108UEFI Platform Initialization Specification, Release 1.8
III-5.7.3 EFI_HOB_FIRMWARE_VOLUME3
Summary
Details the location of a firmware volume including authentication information, for both standalone and extracted
Prototype
BOOLEAN ExtractedFv;
} EFI_HOB_FIRMWARE_VOLUME3;
Header
The HOB generic header. Header.HobType= EFI_HOB_TYPE_FV3 .
inAllocatePages() in the Unified Extensible Firmware Interface Specification.
Length
The authentication status. See Related Definitions of EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI.
ExtractSection() for more information.
ExtractedFv
TRUEif the FV was extracted as a file within another firmware volume. FALSEotherwise.
FvName
The name GUID of the firmware volume. Valid only if IsExtractedFv isTRUE.
FileName
The name GUID of the firmware file which contained this firmware volume. Valid only if IsExtractedFv is
TRUE.
•By a module that has extracted the firmware volume from a file within a firmware file system. By recording the
volume and file name, the HOB consumer phase can avoid processing the same file again.
III-5.7. Firmware Volume HOB III-109UEFI Platform Initialization Specification, Release 1.8
use by its read-only support for the PI Firmware Image Format. The HOB consumer phase must provide appropriate
authentication data reflecting AuthenticationStatus for clients accessing the corresponding firmware volumes.
The HOB producer phase is required to describe any firmware volumes that may contain the HOB consumer phase or
platform drivers that are required to discover other firmware volumes.
III-5.8 CPU HOB
III-5.8.1 EFI_HOB_CPU
Summary
Describes processor information, such as address space and I/O space capabilities.
Prototype
typedef struct _EFI_HOB_CPU {
UINT8 SizeOfMemorySpace;
UINT8 SizeOfIoSpace;
UINT8 Reserved[6];
} EFI_HOB_CPU;
Header
The HOB generic header. Header.HobType =EFI_HOB_TYPE_CPU .
SizeOfMemorySpace
Identifies the maximum physical memory addressability of the processor.
SizeOfIoSpace
Identifies the maximum physical I/O addressability of the processor.
Reserved
For this version of the specification, this field will always be set to zero.
The CPU HOB is produced by the processor executable content in the HOB producer phase. It describes processor
information, such as address space and I/O space capabilities. The HOB consumer phase consumes this information
to describe the extent of the GCD capabilities.
III-5.9 Memory Pool HOB
III-5.9.1 EFI_HOB_MEMORY_POOL
Summary
Describes pool memory allocations.
Prototype
III-5.8. CPU HOB III-110UEFI Platform Initialization Specification, Release 1.8
typedef struct _EFI_HOB_MEMORY_POOL {
} EFI_HOB_MEMORY_POOL;
Header
The HOB generic header. Header.HobType =EFI_HOB_TYPE_MEMORY_POOL .
The memory pool HOB is produced by the HOB producer phase and describes pool memory allocations. The HOB
consumerphaseshouldbeabletoignoretheseHOBs. ThepurposeofthisHOBistoallowfortheHOBproducerphase
to have a simple memory allocation mechanism within the HOB list. The size of the memory allocation is stipulated
by theHobLength field inEFI_HOB_GENERIC_HEADER .
III-5.10 UEFI Capsule HOB
III-5.10.1 EFI_HOB_UEFI_CAPSULE
Summary
Details the location of coalesced each UEFI capsule memory pages.
Prototype
} EFI_HOB_UEFI_CAPSULE;
Header
The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
The physical memory-mapped base address of an UEFI capsule. This value is set to point to the base of the
contiguous memory of the UEFI capsule. The length of the contiguous memory in bytes
Each UEFI capsule HOB details the location of a UEFI capsule. It includes a base address and length which is based
upon memory blocks with a EFI_CAPSULE_HEADER and the associated CapsuleImageSize -based payloads. These
HOB’s shall be created by the PEI PI firmware sometime after the UEFI UpdateCapsule service invocation with the
CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE flag set in the EFI_CAPSULE_HEADER .
III-5.10. UEFI Capsule HOB III-111UEFI Platform Initialization Specification, Release 1.8
III-5.11 Unused HOB
III-5.11.1 EFI_HOB_TYPE_UNUSED
Summary
Indicates that the contents of the HOB can be ignored.
Prototype
This HOB type means that the contents of the HOB can be ignored. This type is necessary to support the simple,
allocate-only architecture of HOBs that have no delete service. The consumer of the HOB list should ignore HOB
entries with this type field.
An agent that wishes to make a HOB entry ignorable should set its type to the prototype defined above.
III-5.12 End of HOB List HOB
III-5.12.1 EFI_HOB_TYPE_END_OF_HOB_LIST
Summary
Indicates the end of the HOB list. This HOB must be the last one in the HOB list.
Prototype
This HOB type indicates the end of the HOB list. This HOB type must be the last HOB type in the HOB list
and terminates the HOB list. A HOB list should be considered ill formed if it does not have a final HOB of type
EFI_HOB_TYPE_END_OF_HOB_LIST .
III-5.13 SMRAM Memory Hob
III-5.13.1 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
Summary
This is a special GUID extension Hob to describe SMRAM memory regions.
GUID
#define EFI_SMM_SMRAM_MEMORY_GUID { \
0x6dadf1d1, 0xd4cc, 0x4910, 0xbb, 0x6e, 0x82, 0xb1, 0xfd,
0x80, 0xff, 0x3d \
}
Prototype
III-5.11. Unused HOB III-112UEFI Platform Initialization Specification, Release 1.8
UINT32 NumberOfSmmReservedRegions;
EFI_SMRAM_DESCRIPTOR Descriptor[1];
} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;
NumberOfSmmReservedRegions
Designates the number of possible regions in the system that can be usable for SMRAM.
Used to describe the candidate regions for SMRAM that are supported by this platform.
The GUID extension hob is to describe SMRAM memory regions supported by the platform.
III-5.13. SMRAM Memory Hob III-113CHAPTER
SIX
III-6.1 Status Codes Overview
ThisspecificationdefinesthestatuscodearchitecturethatisrequiredforanimplementationofthePlatformInitialization

Summary
GUID
}
Prototype
SIX
(PI) specifications (hereafter referred to as the “PI Architecture”). Status codes enable system components to report
information about their current state. This specification does the following:
•Describes the basic components of status codes
•Defines the status code classes; their subclasses; and the progress, error, and debug code operations for each
•Provides code definitions for the data structures that are common to all status codes
•Provides code definitions for the status code classes; subclasses; progress, error, and debug code enumerations;
and extended error data that are architecturally required by the PI Architecture.
The basic definition of a status code can be found in the Termssection.
III-6.1.1 Organization of the Status Codes Specification
Thisspecificationisorganizedaslistedbelow. BecausestatuscodesarejustonecomponentofaPIArchitecture-based
firmware solution, there are a number of references to the PI Specifications throughout this document.
Table 6.1: Organization of This Specification
OverviewProvides a high level explanation of status codes and the status code classes and subclasses
that are defined in this specification
Status Code Classes Provides detailed explanations of the defined status code classes
Code Definitions Providesthecodedefinitionsforallstatuscodeclassessubclassesextendederrordatastruc-
turesandprogresserroranddebugcodeenumerationsthatareincludedinthisspecification
III-6.2 Terms
The following terms are used throughout this document:
debug code
Dataproducedbyvarioussoftwareentitiesthatcontainsinformationspecificallyintendedtoassistindebugging.
The format of the debug code data is governed by this specification.
III-114UEFI Platform Initialization Specification, Release 1.8
error code
Data produced by various software entities that indicates an abnormal condition. The format of the error code
data is governed by this specification.
progress code
Dataproducedbyvarioussoftwareentitiesthatindicatesforwardprogress. Theformatoftheprogresscodedata
is governed by this specification.
status code
One of the three types of codes: progress code, error code, or debug code.
status code driver
The driver that produces the Status Code Runtime Protocol ( EFI_STATUS_CODE_PROTOCOL ). The status code
driverreceivesstatuscodesandnotifiesregisteredlistenersuponreceipt. Statuscodeshandledbythisdriverare
different from the EFI_STATUS returned by various functions. The term EFI_STATUS is defined in the UEFI
Specification .
III-6.3 Types of Status Codes
For each entity classification (class/subclass pair) there are three sets of operations:
•Progress codes
•Error codes
•Debug codes
For progress codes, operations correspond to activities related to the component classification. For error codes, oper-
ations correspond to exception conditions (errors). For debug codes, operations correspond to the basic nature of the
debug information.
The values 0x00-0x0FFF are common operations that are shared by all subclasses in a class. There are also subclass-
specific operations/error codes. Out of the subclass-specific operations, the values 0x1000-0x7FFF are reserved by
this specification. The remaining values (0x8000-0xFFFF) are not defined by this specification and OEMs can assign
meaningtovaluesinthisrange. Thecombinationofclassandsubclassoperationsprovidesthecompletesetofopera-
tionsthatmaybereportedbyanentity. Thefigurebelowdemonstratesthehierarchyofclassandsubclassandprogress,
error, and debug operations.
The organization of status codes, progress versus error, class, subclass, and operation facilitate a flexible reporting of
status codes. In the simplest case, reporting the status code might only convey that an event occurred. In a slightly
more complex system, it might be possible to report the class and if it is a progress, error, or debug Code. In such
a case, it is at least possible to understand that the system is executing a software activity or that an error occurred
with a computing unit. If more reporting capability is present, the error could be isolated to include the subclass–for
example, an error occurred related to memory, or the system is currently executing the PEI Foundation software. If
yet more capability is present, information about the type of error or activity is available–for example, single-bit ECC
errororPEIMdispatchinprogress. Ifthereportingcapabilityiscomplete,itcanprovidethedetailederrorinformation
aboutthesingle-bitECCerror,includingthelocationandastringdescribingthefailure. Alargespectrumofconsumer
capability can be supported with a single interface for the producers of progress and error information.
III-6.3. Types of Status Codes III-115UEFI Platform Initialization Specification, Release 1.8
Fig. 6.1: Hierarchy of Status Code Operations
III-6.3. Types of Status Codes III-116UEFI Platform Initialization Specification, Release 1.8
III-6.3.1 Status Code Classes
The PI architecture defines four classes of status codes–three classes for hardware and one class for software. These
classes are listed in the table below and described in detail in the rest of this section. Each class is made up of several
subclasses, which are also defined later in this section.
See Code Definitions for all the definitions of all data types and enumerations listed in this section.
Table 6.2: Class Definitions
Type of Class Class Name Date Type Name
Hardware Computing Unit EFI_COMPUTING_UNIT
User-Accessible Peripheral EFI_PERIPHERAL
I/O Bus EFI_IO_BUS
Software Host Software EFI_SOFTWARE
Class/subclass pairing should be able to classify any system entity, whether software or hardware. For example, the
boot-strap processor (BSP) in a system would be a member of the computing unit class and host processor subclass,
while a graphics processor would also be a member of the computing unit class, but a member of the I/O processor
subclass.
III-6.3.2 Instance Number
Becauseasystemmaycontainmultipleentitiesmatchingaclass/subclasspairing,thereisan instancenumber . Instance
numbershavedifferentmeaningsfordifferentclasses. However,aninstancenumberof0xFFFFFFFFalwaysindicates
that instance information is unavailable, not applicable, or not provided.
Valid instance numbers start from 0. So a 4-processor server would logically have four instances of the class/subclass
pairing, computing unit/host processor, instance numbers 0 to 3.
Duetothecomplexityofsystemdesign,itisoutsideofthescopeofthisspecificationhowtopairinstancenumberswith
the actual component–for instance, determining which processor is number 3. However, this specification mandates
that the numbering be consistent with the other agents in the system. For example, the processor numbering scheme
that is followed by status codes must be consistent with the one followed by the ACPI tables.
III-6.4 Hardware Classes
III-6.4.1 Computing Unit Class
TheComputingUnitclasscoverscomponentsdirectlyrelatedtosystemcomputationalcapabilities. Subclassescorre-
spond to types of computational devices and resources. See the following for the computing unit class:
•Instance Number
•Progress Code Operations
•Error Code Operations
•Defined Subclasses
III-6.4. Hardware Classes III-117UEFI Platform Initialization Specification, Release 1.8
III-6.4.1.1 Instance Number
The instance number refers to the computing unit’s geographic location in some manner. An instance number of
0xFFFFFFFF means that the instance number information is not available or the provider of the information is not
interested in providing the instance number.
III-6.4.1.2 Progress Code Operations
All computing unit subclasses share the operation codes listed in the table below. See Progress Code Definitions in
Code Definitions: Computing Unit Class for the definitions of these progress codes.
Table 6.3: Progress Code Operations: Computing UnitClass
Operation Description Extended Data
EFI_CU_PC_INIT_BEGIN Generalcomputingunitinitializationbegins. Nodetails
regarding operation are made available.See subclass.
EFI_CU_PC_INIT_END General computing unit initialization ends. No details
0x0002 0x0FFF ReservedforfutureusebythisspecificationforComput-
ing Class progress codes.NA
0x1000 0x7FFF Reserved for subclass use. See the subclass definitions
within this specification for value definitions.NA
0x8000 0xFFFF Reserved for OEM use. OEM defined.
III-6.4.1.3 Error Code Operations
Allcomputingunitsubclassessharetheerrorcodeslistedinthetablebelow. SeeErrorCodeDefinitionsin Computing
Unit Class for the definitions of these error codes.
Table 6.4: Error Code Operations: Computing Unit Class
EFI_CU_EC_NON_SPECIFIC No error details available. See subclass.
EFI_CU_EC_DISABLED Instance is disabled. See subclass.
EFI_CU_EC_NOT_SUPPORTED Instance is not supported. See subclass.
EFI_CU_EC_NOT_DETECTED Instancenotdetectedwhenitwasexpectedtobepresent. See subclass.
E
FI_CU_EC_NOT_CONFIGUREDInstance could not be properly or completely initialized

E
or configured.See subclass.
0x0005 0x0FFF ReservedforfutureusebythisspecificationforComput-
ing Class error codes.NA
0x1000 0x7FFF Subclass defined: See the subclass definitions within
this specification.NA
III-6.4. Hardware Classes III-118UEFI Platform Initialization Specification, Release 1.8
III-6.4.1.4 Subclasses
III-6.4.1.4.1 Defined Subclasses
ThetablebelowliststhesubclassesintheComputingUnitclass. Thefollowingtopicsdescribeeachsubclassinmore
detail. See Subclass Definitions in Code Definitions: Computing Unit Class for the definitions of these subclasses.
Table 6.5: Computing Unit Class: Subclasses
Subclass Code Name Description
Unspecified EFI_COMPUTING_UNIT_UNSPECIFIED The computing unit type is un-
known, undefined, or unspeci-
fied.
Host processor EFI_COMPUTING_UNIT _HOST_PROCESSOR The computing unit is a full-
service central processing unit.
Firmware processor EFI_COMPUTING_UNIT
_FIRMWARE_PROCESSORThe computing unit is a limited
service processor, typically de-
signedtohandletasksoflimited
scope.
I O processor EFI_COMPUTING_UNIT _IO_PROCESSOR The computing unit is a proces-
sordesignedspecificallytohan-
dle I/O transactions.
Cache EFI _COMPUTING_UNIT_CACHE The computing unit is a cache.
All types of cache qualify.
Memory EFI_COMPUTING_UNIT_MEMORY The computing unit is memory.
Many types of memory qualify.
Chipset EFI_COMPUTING_UNIT_CHIPSET The computing unit is a chipset
component.
0x07 0x7F Reserved for future use by this specification.
0x80 0xFF Reserved for OEM use.
III-6.4.1.4.2 Unspecified Subclass
Thissubclasscanbeusedforanycomputingunittypeofcomponentthatdoesnotbelonginoneoftheothersubclasses.
SeeSubclass Definitions for the definition of this subclass.
Progress and Error Code Operations
InadditiontothestandardprogressanderrorcodesthataredefinedfortheComputingUnitclass,thetablebelowlists
the additional codes for this subclass.
Table 6.6: Progress and Error Code Operations: Computing Unit Un-
specified Subclass
Type of Code Operation Description Extended Data
Progress 0x1000 0x7FFF Reserved for future use by this specification. NA
Error 0x1000 0x7FFF Reserved for future use by this specification. NA
None.
III-6.4. Hardware Classes III-119UEFI Platform Initialization Specification, Release 1.8
III-6.4.1.4.3 Host Processor Subclass
This subclass is used for computing units that provide the system’s main processing power and their associated hard-
ware. Thesearegeneral-purposeprocessorscapableofawiderangeoffunctionality. Theinstancenumbermatchesthe
processor handle number that is assigned to the processor by the Multiprocessor (MP) Services Protocol. They often
contain multiple levels of embedded cache.
Progress and Error Code operations
See “Related Definitions” below for links to the definitions of code listed in this table.
III-6.4. Hardware Classes III-120UEFI Platform Initialization Specification, Release 1.8
Table6.7: ProgressandErrorCodeOperations: HostProcessorSubclass
Type of
CodeOperation Description Extended Data
Progress EFI_CU_HP_PC_POWER_ON_INIT Power-on initializa-
tionNone
EFI_CU_HP_PC_CACHE_INIT Embedded cache
initialization includ-
ing cache controller
hardware and cache
memory.EFI_CACHE_INIT_DATA
Progress
(cont.)EFI_CU_HP_PC_RAM_INIT Embedded RAM
initializationNone
EFI_CU_HP_PC_MEMORY _CON-
TROLLER_INITEmbedded memory
controller initializa-
tionNone
EFI_CU_HP_PC_IO_INIT EmbeddedI/Ocom-
plex initializationNone
EFI_CU_HP_PC_BSP_SELECT BSP selection None
EFI_CU_HP_PC_BSP_RESELECT BSP reselection None
EFI_CU_HP_PC_AP_INIT AP initialization
(this operation is
performed by the
current BSP)None
EFI_CU_HP_PC_SMM_INIT SMM initialization None
0x000B-0x7FFF Reserved for future
usebythisspecifica-
tionNA
Error EFI _CU_EC_DISABLED Instance is disabled.
This is a standard
error code for this
class.EFI_COMPUTING_UNIT
_CPU_DISABLED _ER-
ROR_DATA
EFI_CU_HP_EC _INVALID_TYPE Instance is not a
valid type.None
EFI_CU_HP_EC _INVALID_SPEED Instance is not a
valid speed.None
EFI_CU_HP_EC_MISMATCH Mismatch detected
between two in-
stances.EFI_HOST_PROCESSOR
_MISMATCH_ERROR_DATA
EFI_CU_HP_EC _TIMER_EXPIRED A watchdog timer
expired.None
EFI_CU_HP_EC_SELF_TEST Instance detected an
error during BIST.None
EFI_CU_HP_EC_INTERNAL Instance detected an
IERR.None
EFI_CU_HP_EC_THERMAL Anovertemperature
condition was de-
tected with this in-
stance.EFI_COMPUTING_UNIT
_THERMAL_ERROR_DATA
Error
(cont.)EFI_CU_HP_EC _LOW_VOLTAGE Voltage for this in-
stance dropped be-
low the low voltage
threshold.EFI_COMPUTING_UNIT
_VOLTAGE_ERROR_DATA
EFI_CU_HP_EC_HIGH_VOLTAGE Voltage for this in-
stance surpassed the
high voltage thresh-
old.EFI_COMPUTING_UNIT
EFI _CU_HP_EC_CACHE The instance suf-
feredacachefailure.None
EFI_CU_HP_EC _MI-
CROCODE_UPDATEInstance microcode
update failed.EFI_COMPUTING_UNIT
_MI-
CROCODE_UPDATE_ERROR_DATA
EFI_CU_HP_EC_CORRECTABLE Correctable error
detected.None
EFI_CU_HP_EC _UNCORRECTABLE Uncorrectable ECC
error detected.None
EFI_CU_HP_EC_NO._MICROCODE_UPDATE No matching mi-
crocode update is
found.None
0x100D 0x7FFF Reserved for future
tionNAIII-6.4. Hardware Classes III-121UEFI Platform Initialization Specification, Release 1.8
See the following topics in Subclass Definitions for definitions of the subclass-specific operations:
•Progress Code Definitions
•Error Code Definitions
See Extended Error Data in Computing Unit Class for definitions of the extended error data.
III-6.4.1.4.4 Firmware Processor Subclass
This subclass applies to processors other than the Host Processors that provides services to the system.
Table 6.8: Progress and Error Code Operations:Service Processor Sub-
class
Type of
CodeOperation Description Ex-
tended
Data
Progress 0x1000 0x7FFF Reservedforfutureusebythisspecification. NA
Error EFI_CU_FP_EC_HARD_FAIL Firmware processor detected a hardware er-
ror during initialization.None
EFI_CU_FP_EC_SOFT_FAIL Firmware processor detected an error dur-
ing initialization. E.g. Firmware processor
NVRAM contents are invalid.None
EFI_CU_FP_EC_COMM_ERROR The host processor encountered an error
whilecommunicatingwiththefirmwarepro-
cessor.None
0x1004 0x7FFF Reservedforfutureusebythisspecification. NA
See the following topics in Computing Unit Class for definitions of the subclass-specific operations listed above:
III-6.4.1.4.5 I/O Processor Subclass
ThissubclassappliestosystemI/Oprocessorsandtheirassociatedhardware. Theseprocessorsaretypicallydesigned
tooffloadI/Otasksfromthecentralprocessorsinthesystem. ExampleswouldincludegraphicsorI20processors. The
subclass is identical to the host processor subclass. See Host Processor Subclass for more information.
SeeHost Processor Subclass for the definition of this subclass.
III-6.4. Hardware Classes III-122UEFI Platform Initialization Specification, Release 1.8
III-6.4.1.4.6 Cache Subclass
The cache subclass applies to any external/system level caches. Any cache embedded in a computing unit would not
be counted in this subclass, but would be considered a member of that computing unit subclass.
Table 6.9: Progress and Error Code Operations: CacheSubclass
Type of
tended
Data
Progress EFI_CU_CACHE_PC_PRESENCE_DETECT Detecting cache presence. None
EFI_CU_CACHE_PC_CONFIGURATION Configuring cache. None
0x1002 0x7FFF Reservedforfutureusebythisspec-
ification.NA
Error EFI_CU_CACHE_EC_INVALID_TYPE Instance is not a valid type. None
EFI_CU_CACHE_EC_INVALID_SPEED Instance is not a valid speed. None
EFI_CU_CACHE_EC_INVALID_SIZE Instance size is invalid. None
EFI_CU_CACHE_EC_MISMATCH Instance does not match other
caches.None
0x1004-0x7FFF Reservedforfutureusebythisspec-
III-6.4.1.4.7 Memory Subclass
The memory subclass applies to any external/system level memory and associated hardware. Any memory embedded

Type of
tended
Data
in a computing unit would not be counted in this subclass, but would be considered a member of that computing unit
subclass.
For all operations and errors, the instance number specifies the DIMM number unless stated otherwise. Some of
the operations may affect multiple memory devices and multiple memory controllers. The specification provides
mechanisms ( EFI_MULTIPLE_MEMORY_DEVICE_OPERATION and others) to describe such group operations. See
EFI_STATUS_CODE_DIMM_NUMBER inComputing Unit Class for details.
III-6.4. Hardware Classes III-123UEFI Platform Initialization Specification, Release 1.8
Table 6.10: Progress and Error Code Operations: MemorySubclass
Type
of
tended
Data
Progress EFI_CU_MEMORY_PC_SPD_READ Reading configuration data (e.g. SPD)
from memory devices.None
EFI_CU_MEMORY_PC_PRESENCE_DETECT Detecting presence of memory devices
(e.g. DIMMs).None
EFI_CU_MEMORY_PC_TIMING Determining optimum configuration
e.g. timing for memory devices.None
EFI_CU_MEMORY_PC_CONFIGURING Initial configuration of memory device
and memory controllers.None
EFI_CU_MEMORY_PC_OPTIMIZING Programming the memory controller
and memory devices with optimized
settings.None
Progress
(cont.)EFI_CU_MEMORY_PC_INIT Memory initialization such as ECC ini-
tialization.EFI_MEMORY
_RANGE
_EX-
TENDED_DATA
EFI_CU_MEMORY_PC_TEST Performing memory test. EFI_MEMORY
_RANGE
_EX-
0x1007-0x7FFF Reserved for future use by this specifi-
cationNA
Error EFI_CU_MEMORY _EC_INVALID_TYPE Instance is not a valid type. None
EFI_CU_MEMORY _EC_INVALID_SPEED Instance is not a valid speed. None
EFI_CU_MEMORY _EC_CORRECTABLE Correctable error detected. EFI_MEMORY
_EX-
TENDED
_ER-
ROR_DATA
EFI_CU_MEMORY _EC_UNCORRECTABLE Uncorrectable error detected. This in-
cluded memory miscomparisions dur-
ing the memory test.EFI_MEMORY
_EX-
TENDED
_ER-
ROR_DATA
EFI_CU_MEMORY _EC_SPD_FAIL Instance SPD failure detected. None
EFI_CU_MEMORY _EC_INVALID_SIZE Instance size is invalid. None
EFI_CU_MEMORY _EC_MISMATCH Mismatch detected between two in-
stances.EFI_MEMORY
_MOD-
ULE
_MIS-
MATCH
_ER-
ROR_DATA
E FI_CU_MEMORY_EC _S3_RESUME_FAIL Resume from S3 failed. None
EFI_CU_MEMORY _EC_UPDATE_FAIL Flash Memory Update failed. None
EFI_CU_MEMORY _EC_NONE_DETECTED Memorywasnotdetectedinthesystem.
Instance field is ignored.None
Error
contEFI_CU_MEMORY _EC_NONE_USEFUL No useful memory was detected in the
system. E.g., Memory was detected but
cannot be used due to errors. Instance
field is ignored.None
0x1009-0x7FFF Reserved for future use by this specifi-
cation.NAIII-6.4. Hardware Classes III-124UEFI Platform Initialization Specification, Release 1.8
SeeExtended Data Formats for definitions of the extended error data listed above.
III-6.4.1.4.8 Chipset Subclass
This subclass can be used for any chipset components and their related hardware.
Table 6.11: Progress and Error Code Operations:Chipset Subclass
Type of
tended
Data
Progress EFI_CHIPSET_PC_PEI_CAR_SB_INIT South Bridge initialization prior to memory
detectionNone
EFI_CHIPSET_PC_PEI_CAR_NB_INIT North Bridge initialization prior to memory
EFI_CHIPSET_PC_PEI_MEM_SB_INIT SouthBridgeinitializationaftermemoryde-
tectionNone
EFI_CHIPSET_PC_PEI_MEM_NB_INIT NorthBridgeinitializationaftermemoryde-
EFI_CHIPSET_PC_DXE_HB_INIT PCI Host Bridge DXE initialization None
EFI_CHIPSET_PC_DXE_NB_INIT North Bridge DXE initialization None
EFI_CHIPSET_PC_DXE_NB_SMM_INIT North Bridge specific SMM initialization in
DXENone
EFI_CHIPSET_PC_DXE_SB_RT_INIT Initialization of the South Bridge specific
UEFI Runtime ServicesNone
EFI_CHIPSET_PC_DXE_SB_INIT South Bridge DXE initialization None
EFI_CHIPSET_PC_DXE_SB_SMM_INIT South Bridge specific SMM initialization in
DXENone
EFI_CHIPSET_PC_DXE
_SB_DEVICES_INITInitialization of the South Bridge devices None
Progress 0x100B-0x7FFF Reserved for future use by this specification NA
Error EFI_CHIPSET_EC_BAD_BATTERY Bad battery status has been detected None
EFI_CHIPSET_EC_DXE_NB_ERROR North Bridge initialization error in DXE None
EFI_CHIPSET_EC_DXE_NB_ERROR South Bridge initialization error in DXE None
EFI_CHIPSET_EC_INTRUDER_DETECT Physicalaccesstoinnersystemcomponents
thatarenotaccessibleduringnormalsystem
operation is detectedNone
Error 0x1004-0x7FFF Reserved for future use by this specification
None.
III-6.4. Hardware Classes III-125UEFI Platform Initialization Specification, Release 1.8
III-6.4.2 User-Accessible Peripheral Class
The User-Accessible Peripheral class refers to any peripheral with which the user interacts. Subclass elements corre-
spond to general classes of peripherals. See the following for the User-Accessible Peripheral class:
•instance number
•progress code operations
•error code operations
•defined subclasses
III-6.4.2.1 Instance Number
The instance number refers to the peripheral’s geographic location in some manner. Instance number of 0 means that
instancenumberinformationisnotavailableortheprovideroftheinformationisnotinterestedinprovidingtheinstance
number.
III-6.4.2.2 Progress Code Operations
All peripheral subclasses share the operation codes listed in the table below. See Progress Code Definitions for the
definitions of these progress codes.
Table 6.12: Progress Code Operations: User-AccessiblePeripheral Class
EFI_P_PC_INIT General Initialization. No details regarding
operation are made available.See subclass
EFI_P_PC_RESET Resetting the peripheral. See subclass
EFI_P_PC_DISABLE Disabling the peripheral. See subclass
EFI_P_PC _PRESENCE_DETECT Detecting the presence. See subclass
EFI_P_PC_ENABLE Enabling the peripheral. See subclass
EFI_P_PC_RECONFIG Reconfiguration. See subclass
EFI_P_PC_DETECTED Peripheral was detected. See subclass
EFI_P_PC_REMOVED Peripheralwasunplugged,ejected,orother-
wise removed from the system.See subclass
0x0007 0x0FFF Reserved for future use by this specification
for Peripheral Class progress codes.NA
0x1000-0x7FFF Reserved for subclass use. See the subclass
definitionswithinthisspecificationforvalue
definitions.See subclass
0x8000-0xFFFF Reserved for OEM use. NA
III-6.4.2.3 Error Code Operations
Allperipheralsubclassessharetheerrorcodeslistedinthetablebelow. See User-AccessiblePeripheralsClass forthe
definitions of these error codes.
III-6.4. Hardware Classes III-126UEFI Platform Initialization Specification, Release 1.8
Table 6.13: Error Code Operations: User-AccessiblePeripheral Class
EFI_P_EC_NON_SPECIFIC No error details available See subclass
EFI_P_EC_DISABLED Instance is disabled See subclass
EFI_P_EC _NOT_SUPPORTED Instance is not supported See subclass
EFI_P_EC _NOT_DETECTED Instance not detected when it was expected
to be presentSee subclass
EFI_P_EC _NOT_CONFIGURED Instancecouldnotbeproperlyorcompletely
initialized or configuredSee subclass
EFI_P_EC_INTERFACE_ERROR An error occurred with the peripheral inter-
faceSee subclass
EFI_P_EC_CONTROLLER_ERROR An error occurred with the peripheral con-
trollerSee subclass
EFI_P_EC_INPUT_ERROR Anerroroccurredgettinginputfromthepe-
ripheralSee subclass
E FI_P_EC_OUTPUT_ERROR An error occurred putting output to the pe-
EFI_P_EC_RESOURCE_CONFLICT A resource conflict exists with this instance
s resource requirementsSee
EFI_RESOURCE_ALLO
C_FAILURE_ERROR_DATA
for all subclasses
0x0006-0x0FFF Reserved for future use by this specifica-
tion for User-Accessible Peripheral class er-
ror codesNA
0x1000-0x7FFF Seethesubclassdefinitionswithinthisspec-
ificationSee subclass
0x8000-0xFFFF Reserved for OEM use NA
III-6.4.2.4 Subclasses
III-6.4.2.4.1 Defined Subclasses
ThetablebelowliststhesubclassesintheUser-AccessiblePeripheralclass. Thefollowingtopicsdescribeeachsubclass
in more detail. See Subclass Definitions . for the definitions of these subclasses.
III-6.4. Hardware Classes III-127UEFI Platform Initialization Specification, Release 1.8
Table 6.14: Defined Subclasses: User-Accessible Peripheral Class
Unspecified EFI_PERIPHERAL_UNSPECIFIED Theperipheraltypeisunknown,
undefined, or unspecified.
Keyboard E FI_PERIPHERAL_KEYBOARD The peripheral referred to is a
keyboard.
Mouse EFI_PERIPHERAL_MOUSE The peripheral referred to is a

keyboard.
mouse.
Local console EFI_PERIPHERAL_LOCAL_CONSOLE The peripheral referred to is a
console directly attached to the
system.
Remote con-
soleEFI_PERIPHERAL_REMOTE_CONSOLE The peripheral referred to is a
consolethatcanberemotelyac-
cessed.
Serial port EFI_PERIPHERAL_SERIAL_PORT Theperipheralreferredtoisase-
rial port.
Parallel port EFI_PERIPHERAL_PARALLEL_PORT The peripheral referred to is a
parallel port.
Fixed media EFI_PERIPHERAL_FIXED_MEDIA The peripheral referred to is a
fixed media device–e.g., an IDE
hard disk drive.
Removable
mediaEFI_PERIPHERAL_REMOVABLE_MEDIA The peripheral referred to is a
removable media device–e.g., a
DVD ROM drive.
Audio input EFI_PERIPHERAL_AUDIO_INPUT The peripheral referred to is an
audioinputdevice–e.g.,amicro-
phone.
Audio output EFI_PERIPHERAL_AUDIO_OUTPUT The peripheral referred to is an
audiooutputdevice–e.g.,speak-
ers or headphones.
LCD device EFI _PERIPHERAL_LCD_DEVICE The peripheral referred to is an
LCD device.
Network de-
viceEFI_PERIPHERAL_NETWORK The peripheral referred to is a
network device–e.g., a network
card.
Docking Sta-
tionEFI_PERIPHERAL_DOCKING The peripheral referred to is a
docking station.
Trusted Plat-
form ModuleEFI_PERIPHERAL_TPM The peripheral referred to is a
Trusted Platform Module
0x0F-0x7F Reserved for future use by this specification.
0x80-0xFF Reserved for OEM use.
III-6.4. Hardware Classes III-128UEFI Platform Initialization Specification, Release 1.8
III-6.4.2.4.2 Unspecified Subclass
This subclass applies to any user-accessible peripheral not belonging to any of the other subclasses.
InadditiontothestandardprogressanderrorcodesthataredefinedfortheUser-AccessiblePeripheralclass,thetable
below lists the additional codes for this subclass.
Table6.15: ProgressandErrorCodeOperations: PeripheralUnspecified
Subclass
Progress 0x1000-0x7FFF Reserved for future use by this specification. NA
Error 0x1000-0x7FFF Reserved for future use by this specification. NA
None.
III-6.4.2.4.3 Keyboard Subclass
This subclass applies to any keyboard style interfaces. ExtendedData contains the device path to the keyboard device
as defined in EFI_DEVICE_PATH_EXTENDED_DATA and the instance is ignored.
III-6.4. Hardware Classes III-129UEFI Platform Initialization Specification, Release 1.8
Table 6.16: Progress and Error Code Operations: Keyboard Subclass
Progress EFI_P_KEYBOARD
_PC_CLEAR_BUFFERClearing the
input keys from
keyboard.The device path to the keyboard de-
viceSeeEFI_DEVICE_PATH_EX-
EFI_P_KEYBOARD
_PC_SELF_TESTKeyboard self
test.The device path to the keyboard de-
0x1002-0x7FFF Reserved for fu-
ture use by this
specification.NA
Error EFI_P_KEYBOARD
_EC_LOCKEDThe keyboard
input is locked.The device path to the keyboard de-
_EC_STUCK_KEYA stuck key was
detected.The device path to the keyboard de-
_EC_BUFFER_FULLKeyboard buffer
is full.The device path to the keyboard de-
0x1003-0x7FFF Reserved for fu-
See the following topics in User-Accessible Peripherals Class for definitions of the subclass-specific operations listed
above:
See Extended Error Data in User-Accessible Peripherals Class for definitions of the extended error data listed above.
III-6.4.2.4.4 Mouse Subclass
Thissubclassappliestoanymouseorpointerperipherals. ExtendedData containsthedevicepathtothemousedevice
III-6.4. Hardware Classes III-130UEFI Platform Initialization Specification, Release 1.8
Table 6.17: Progress and Error Code Operations: MouseSubclass
Progress EFI_P_MOUSE_PC _SELF_TEST Mouse self test The device path to the mouse de-
0x1001-0x7FFF Reserved for fu-
specificationNA
Error EFI_P_MOUSE _EC_LOCKED Themouseinput
is lockedThe device path to the mouse de-
above:
III-6.4.2.4.5 Local Console Subclass
This subclass applies to all console devices directly connected to the system. This would include VGA/UGA devices.
ExtendedData containsthedevicepathtotheconsoledeviceasdefinedin EFI_DEVICE_PATH_EXTENDED_DATA and
the instance is ignored. LCD devices have their own subclass.
Table6.18: ProgressandErrorCodeOperations: LocalConsoleSubclass
Progress 0x1000-0x7FFF Reserved for future use by this specification NA
Error 0x1000-0x7FFF Reserved for future use by this specification NA
None.
III-6.4. Hardware Classes III-131UEFI Platform Initialization Specification, Release 1.8
III-6.4.2.4.6 Remote Console Subclass
This subclass applies to any console not directly connected to the system. This would include consoles displayed
via serial or LAN Hconnections. ExtendedData contains the device path to the console device as defined in
EFI_DEVICE_PATH_EXTENDED_DATA and the instance is ignored.
Table 6.19: Progress and Error Code Operations: RemoteConsole Sub-
class
None.
III-6.4.2.4.7 Serial Port Subclass
Thissubclassappliestodevicesattachedtoasystemserialport,suchasamodem. ExtendedData containsthedevice
path to the device as defined in EFI_DEVICE_PATH_EXTENDED_DATA and the instance is ignored.
Table 6.20: Progress and Error Code Operations: SerialPort Subclass
Type of
Progress EFI_P_SERIAL_PORT
_PC_CLEAR_BUFFERClearingtheserialportin-
put bufferThe device handle See
EFI_DEVICE_PATH _EX-
0x1001-0x7FFF Reservedforfutureuseby
this specificationNA
Error 0x1000-0x7FFF Reservedforfutureuseby
above:
III-6.4. Hardware Classes III-132UEFI Platform Initialization Specification, Release 1.8
III-6.4.2.4.8 Parallel Port Subclass
Thissubclassappliestodevicesattachedtoasystemparallelport,suchasaprinter. ExtendedData containsthedevice

above:
Table 6.21: Progress and Error Code Operations:Parallel Port Subclass
None.
III-6.4.2.4.9 Fixed Media Subclass
This subclass applies to fixed media peripherals such as hard drives. These peripherals are capable of pro-
ducing the EFI_BLOCK_IO Protocol. ExtendedData contains the device path to the device as defined in
Table 6.22: Progress and Error Code Operations: FixedMedia Subclass
None.
III-6.4. Hardware Classes III-133UEFI Platform Initialization Specification, Release 1.8
III-6.4.2.4.10 Removable Media Subclass
ThissubclassappliestoremovablemediaperipheralssuchasfloppydiskdrivesorLS-120drives. Theseperipheralsare
capable of producing the EFI_BLOCK_IO Protocol. ExtendedData contains the device path to the device as defined
inEFI_DEVICE_PATH_EXTENDED_DATA and the instance is ignored.
Table6.23: ProgressandErrorCodeOperations: RemovableMediaSub-
class
None.
III-6.4.2.4.11 Audio Input Subclass
This subclass applies to audio input devices such as microphones.
Table 6.24: Progress and Error Code Operations: AudioInput Subclass
None.
III-6.4.2.4.12 Audio Output Subclass
This subclass applies to audio output devices like speakers or headphones.
III-6.4. Hardware Classes III-134UEFI Platform Initialization Specification, Release 1.8
Table6.25: ProgressandErrorCodeOperations: AudioOutputSubclass
None.
III-6.4.2.4.13 LCD Device Subclass
This subclass applies to LCD display devices attached to the system.
Progress and Errror Code Operations
Table 6.26: Progress and Error Code Operations: LCD Device Subclass
None.
III-6.4.2.4.14 Network Device Subclass
This subclass applies to network adapters attached to the system. These devices are capable of producing standard
UEFI networking protocols such as the EFI_SIMPLE_NETWORK Protocol.
Table 6.27: Progress and Error Code Operations: Network Device Sub-
class
None.
III-6.4. Hardware Classes III-135UEFI Platform Initialization Specification, Release 1.8
III-6.4.3 I/O Bus Class
TheI/Obusclasscovershardwarebusesirrespectiveofanysoftwareprotocolsthatareused. Atabroadlevel,everything
that connects the computing unit to the user peripheral can be covered by this class. Subclass elements correspond to
industry-standard hardware buses. See the following for the I/O Bus class:
III-6.4.3.1 Instance Number
The instance number is ignored and the ExtendedData describes the device path to the controller or the device as
defined in EFI_DEVICE_PATH_EXTENDED_DATA .
III-6.4.3.2 Progress Code Operations
All I/O bus subclasses share the operation codes listed in the table below. See Progress Code Definitions for the
III-6.4. Hardware Classes III-136UEFI Platform Initialization Specification, Release 1.8
Table 6.28: Progress Code Operations: I/O Bus Class
EFI_IOB_PC_INIT Generalinitialization. Nodetailsre-
garding operation are made avail-
able.The device path correspond-
ing to the host bus controller
(the controller that produces
this bus). For the PCI bus, it is
the PCI root bridge. The for-
mat of the device path extended
data is defined in EFI_DEVICE
_PATH_EXTENDED_DATA
EFI_IOB_PC_RESET Resetting the bus. Generally, this
operation resets all the devices on
the bus as well.The device path corresponding to
the host controller (the controller
that produces this bus) The for-
mat is defined in EFI_DEVICE
EFI_IOB_PC_DISABLE Disabling all the devices on the bus
prior to enumeration.The device path corresponding to
that produces this bus). The for-
EFI_IOB_PC_DETECT Detecting devices on the bus. The device path corresponding to
EFI_IOB_PC_ENABLE Configuring the bus and enabling
device on the bus.The device path corresponding to
EFI_IOB_PC_RECONFIG Bus reconfiguration including re-
source re-enumeration.The device path corresponding to
the host controller the controller
that produces this bus The for-
EFI_IOB_PC_HOTPLUG Ahot-plugeventwasdetectedonthe
bus and the hot-plugged device was
initialized.The device path corresponding to
0x0007 0x0FFF Reservedforfutureusebythisspec-
ification for I/O Bus class progress
codes.NA
0x1000 0x7FFF Reserved for subclass use. See the
subclassdefinitionswithinthisspec-
ification for value definitions.NA
III-6.4. Hardware Classes III-137UEFI Platform Initialization Specification, Release 1.8
III-6.4.3.3 Error Code Operations
All I/O bus subclasses share the error codes listed in the table below. See Error Code Definitions in Error Code
Operations: I/O Bus Class for the definitions of these error codes.
Table 6.29: Error Code Operations: I/O Bus Class
EFI_IOB_EC_NON_SPECIFIC No error details available. None.
EFI_IOB_EC_DISABLED A device is disabled due to bus-
level errors.The device path correspond-
ing to the device. See
EFI_DEVICE_PATH_EXTENDED_DATA.
EFI_IOB_EC_NOT_SUPPORTED A device is nots upported on
thisbus.The device path correspond-
EFI_IOB_EC_NOT_DETECTED Instance not detected when it
was expected to be present.The device path correspond-
EFI_IOB_EC_NOT_CONFIGURED Instance could not be prop-
erly or completely initial-
ized/configured.The device path correspond-

EFI_IOB_EC_INTERFACE_ERROR An error occurred with the bus
interface.The device path correspond-
ing to the failing device. See
EFI_IOB_EC_CONTROLLER_ERROR An error occurred with the host
bus controller (the controller
that produces this bus).The device path correspond-
ing to the bus controller. See
EFI_IOB_EC_READ_ERROR A bus specific error occurred
getting input from a device on
the bus.The device path correspond-
ing to the failing device or
the closest device path. See
EFI_DEVICE_PATH_
EFI_IOB_EC_WRITE_ERROR Anerroroccurredputtingoutput
to the bus.The device path correspond-
EFI_IOB_EC_RESOURCE_CONFLICT A resource conflict exists with
this instance’s resource require-
ments.See
EFI_RESOURCE_ALLOC_FAILURE
ERROR_DATA.
0x000A-0x0FFF Reserved for future use by this
specification for I/O Bus class
errorcodes.NA
0x1000-0x7FFF See the subclass definitions
within this specification.NA
III-6.4. Hardware Classes III-138UEFI Platform Initialization Specification, Release 1.8
III-6.4.3.4 Subclasses
III-6.4.3.4.1 Defined Subclasses
The table below lists the subclasses in the . The following topics describe each subclass in more detail. See Subclass
Definitions for the definitions of these subclasses.
Table 6.30: Defined Subclasses: I/O Bus Class
Unspecified EF I_IO_BUS_UNSPECIFIED Thebustypeisunknownundefinedorunspec-
ified
PCI EFI_IO_BUS_PCI The bus is a PCI bus
USB EFI_IO_BUS_USB The bus is a USB bus
InfiniBand architec-
tureEFI_IO_BUS_IBA The bus is an IBA bus
AGP EFI_IO_BUS_AGP The bus is an AGP bus
PC card EFI_IO_BUS_PC_CARD The bus is a PC Card bus
Low pin count LPC EFI_IO_BUS_LPC The bus is a LPC bus
SCSI EFI_IO_BUS_SCSI The bus is a SCSI bus
ATA ATAPI SATA EFI_IO_BUS_ATA_ATAPI The bus is a ATA ATAPI bus
Fibre Channel EFI_IO_BUS_FC The bus is an EC bus
IP network E FI_IO_BUS_IP_NETWORK The bus is an IP network bus
SMBus EFI_IO_BUS_SMBUS The bus is a SMBUS bus
I2C EFI_IO_BUS_I2C The bus is an I2C bus
0x0D 0x7F Reservedforfutureusebythisspecifica-
tion
0x80 0xFF Reserved for OEM use
III-6.4.3.4.2 Unspecified Subclass
This subclass applies to any I/O bus not belonging to any of the other I/O bus subclasses.
In addition to the standard progress and error codes that are defined for the I/O Bus class, the table below lists the
additional codes for this subclass.
Table 6.31: Progress and Error Code Operations: I/OBus Unspecified
Subclass
None.
III-6.4. Hardware Classes III-139UEFI Platform Initialization Specification, Release 1.8
III-6.4.3.4.3 PCI Subclass
This subclass applies to PCI buses and devices. It also includes different variations of PCI bus including PCI-X and
PCI Express.
Table 6.32: Progress and Error Code Operations: PCISubclass
Type of
Progress EFI_IOB_PCI _BUS_ENUM Enumerating
buses under a
root bridge.The device path corresponding to the
PCI root bridge See EFI_DEVICE_PATH
_EXTENDED_DATA
EFI_IOB_PCI _RES_ALLOC Allocating
resources to
devices under a
host bridge.The host bridge handle as defined
in EFI_DEVICE_HANDLE _EX-
EFI_IOB_PCI _HPC_INIT Initializing a
PCI hot-plug
controller.The device path to the controller as
defined in EFI_DEVICE_PATH _EX-
Error EFI_IOB_PCI _EC_PERR Parity error; see
PCI Specifica-
tion.The device path to the controller that
generated the PERR The data format
is defined in EFI_DEVICE_PATH _EX-
EFI_IOB_PCI _EC_SERR System error;
see PCI Specifi-
cation.The device path to the controller that
generated the SERR The data format
above:
See Extended Error Data in I/O Bus Class for definitions of the extended error data listed above.
III-6.4. Hardware Classes III-140UEFI Platform Initialization Specification, Release 1.8
III-6.4.3.5 USB Subclass
This subclass applies to USB buses and devices.
Table 6.33: Progress and Error Code Operations: USBSubclass
None.
III-6.4.3.5.1 InfiniBand* Architecture Subclass
This subclass applies to InfiniBand* (IBA) buses and devices.
Table 6.34: Progress and Error Code Operations: IBASubclass
None.
III-6.4.3.5.2 AGP Subclass
This subclass applies to AGP buses and devices.
Table 6.35: Progress and Error Code Operations: AGPSubclass
III-6.4. Hardware Classes III-141UEFI Platform Initialization Specification, Release 1.8
None.
III-6.4.3.5.3 PC Card Subclass
This subclass applies to PC Card buses and devices.
Table 6.36: Progress and Error Code Operations: PCCard Subclass
None.
III-6.4.3.5.4 LPC Subclass
This subclass applies to LPC buses and devices.
Table 6.37: Progress and Error Code Operations: LPCSubclass
None.
III-6.4.3.5.5 SCSI Subclass
This subclass applies to SCSI buses and devices.
III-6.4. Hardware Classes III-142UEFI Platform Initialization Specification, Release 1.8
Table 6.38: Progress and Error Code Operations: SCSISubclass
None.
III-6.4.3.5.6 ATA/ATAPI/SATA Subclass
This subclass applies to ATA and ATAPI buses and devices. It also includes Serial ATA (SATA) buses.

None.
None.
Table 6.39: Progress and Error Code Operations:ATA/ATAPI/SATA
Subclass
Type of code Operation Description Ex-
tended
data
Progress EFI_IOB_ATA_BUS_SMART_ENABLE SMART is enabled on the stor-
age deviceNA
EFI_IOB_ATA_BUS_SMART_DISABLE SMART is disabled on the stor-
EFI_IOB_ATA_BUS_SMART _OVER-
THRESHOLDSMARTrecordsareoverthresh-
old on the storage deviceNA
EFI_IOB_ATA_BUS_SMART _UNDER-
THRESHOLDSMART records are under
threshold on the storage deviceNA
0x1004-0x7FFF Reserved for future use by this
Error EFI_IOB_ATA_BUS_SMART _NOTSUP-
PORTEDSMART is not supported on the
storage deviceNA
EFI_IOB_ATA_BUS_SMART _DISABLED SMART is disabled on the stor-
0x1002-0x7FFF Reserved for future use by this
None.
III-6.4. Hardware Classes III-143UEFI Platform Initialization Specification, Release 1.8
III-6.4.3.5.7 Fibre Channel (FC) Subclass
This subclass applies to Fibre Channel buses and devices.
Table 6.40: Progress and Error Code Operations: FCSubclass
None.
III-6.4.3.5.8 IP Network Subclass
This subclass applies to IP network buses and devices.
Table 6.41: Progress and Error Code Operations: IPNetwork Subclass
None.
III-6.4.3.5.9 3SMBus Subclass
This subclass applies to SMBus buses and devices.
Table 6.42: Progress and Error Code Operations: SMBusSubclass
III-6.4. Hardware Classes III-144UEFI Platform Initialization Specification, Release 1.8
None.
III-6.4.3.5.10 I2C Subclass
This subclass applies to I2C buses and devices.
Table 6.43: Progress and Error Code Operations: I2CSubclass
None.
III-6.5 Software Classes
III-6.5.1 Host Software Class
The Host Software class covers any software-generated codes. Subclass elements correspond to common software
types in a PI Architecture system. See the following for the Host Software class:
III-6.5.2 Instance Number
The instance number is not used for software subclasses unless otherwise stated.
III-6.5.3 Progress Code Operations
All host software subclasses share the operation codes listed in the table below. See Progress Code Definitions in
Software Classes for the definitions of these progress codes.
III-6.5. Software Classes III-145UEFI Platform Initialization Specification, Release 1.8
Table 6.44: Progress Code Operations: Host Software Class
EFI_SW_PC_INIT Generalinitialization. Nodetailsre-
able.None
EFI_SW_PC_LOAD Loading a software module in the
prebootphasebyusingLoadImage()
or an equivalent PEI service. May
includeaPEIM,DXEdrivers,UEFI
application, etc.Handle identifying the mod-
ule. There will be an instance of
EFI_LOADED_IMAGE_PROTOCOL
on this handle. See
EFI_DEVICE_HANDLE _EX-
EFI_SW_PC _INIT_BEGIN Initializing software module by us-
ing StartImage() or an equivalent
PEI service.Handle identifying the mod-
EFI_SW_PC _INIT_END Software module returned control
back after initialization.Handle identifying the mod-
EFI_SW_PC _AUTHENTI-
CATE_BEGINPerforming authentication (pass-
words, biometrics, etc.)None
CATE_ENDAuthentication completed None
EFI_SW_PC _INPUT_WAIT Waiting for user input None
EFI_SW_PC _USER_SETUP Executing user setup None
0x0008-0x0FFF Reservedforfutureusebythisspec-
ification for Host Software class
progress codes.NA
0x1000-0x7FFF Reserved for subclass use. See the
III-6.5.4 Error Code Operations
All host software subclasses share the error codes listed in the table below. See Error Code Definitions in Software
Classesfor the definitions of these progress codes.
Table 6.45: Error Code Operations: Host Software Class
EFI_SW_EC_NON_SPECIFIC No error details are avail-
able.None
III-6.5. Software Classes III-146UEFI Platform Initialization Specification, Release 1.8
Table 6.45 – continued from previous page
EFI_SW_EC_LOAD_ERROR The software module load
failed.Handle identifying
the module. There
will be an instance of
EFI_DEVICE_HANDLE_EXTENDED_DATA.
EFI_SW_EC_INVALID_PARAMETER An invalid parameter was
passed to the instance.None.
EFI_SW_EC_UNSUPPORTED An unsupported operation
was requested.None.
EFI_SW_EC_INVALID_BUFFER The instance encoun-
tered an invalid buffer
(too large, small, or
nonexistent).None.
EFI_SW_EC_OUT_OF_RESOURCES Insufficient resources ex-
ist.None.
EFI_SW_EC_ABORTED The instance was aborted. None.
EFI_SW_EC_ILLEGAL_SOFTWARE_STATE The instance detected an
illegal software state.See
EFI_DEBUG_ASSERT_DATA
EFI_SW_EC_ILLEGAL_HARDWARE_STATE The instance detected an
illegal hardware state.None.
EFI_SW_EC_START_ERROR The software module
returned an error when
startedviaStartImage()or
equivalent.Handle identifying
EFI_SW_EC_BAD_DATE_TIME Thesystemdate/timeisin-
validNone.
EFI_SW_EC_CFG_INVALID Invalid configuration set-
tings were detected.None.
EFI_SW_EC_CFG_CLR_REQUEST User requested that con-
figuration defaults be
loaded (via a physical
jumper, for example).None.
EFI_SW_EC_CFG_DEFAULT Configuration defaults
were loaded.None.
EFI_SW_EC_PWD_INVALID Invalid password settings
were detected.None.
EFI_SW_EC_PWD_CLR_REQUEST User requested that the
passwords be cleared (via
a physical jumper, for ex-
ample).None.
EFI_SW_EC_PWD_CLEARED Passwords were cleared. None.
EFI_SW_EC_EVENT_LOG_FULL System event log is full. None.
EFI_SW_EC_WRITE_PROTECTED Thedevicecannotbewrit-
ten to.EFI_DEVICE_PATH_EXTENDED_DATA
if device path to the write
protected device is avail-
able; otherwise, none.
III-6.5. Software Classes III-147UEFI Platform Initialization Specification, Release 1.8
EFI_SW_EC_FV_CORRUPTED Corrupted Firmware Vol-
ume is detected.EFI_DEVICE_PATH_EXTENDED_DATA
if device path to the cor-
rupted firmware volume
is available; otherwise,
none.
EFI_SW_EC_INCONSISTENT_MEMORY_MAP System will reboot due
to inconsistent memory
mapsNone
0x0015-0x00FF Reserved for future use
by this specification for
Host Software class error
codes.None.
0x0100-0x01FF Unexpected EBC excep-
tions.See
EFI_STATUS_CODE_EXCEP_EXTENDED_DATA.
0x0200-0x02FF UnexpectedIA-32proces-
sor exceptions.See
0x0300-0x03FF Unexpected Itanium(r)
processor family excep-
tions.See
0x0400-0x7FFF See the subclass defini-
tionswithinthisspecifica-
tion.

none.
mapsNone
tions.See
tions.See
tion.
0x8000-0xFFFF Reserved for OEM use.
III-6.5.5 Subclasses
III-6.5.5.1 Defined Subclasses
The table below lists the subclasses in the Host Software class. The following topics describe each subclass in more
detail.
SeeSubclass Definitions for the definitions of these subclasses.
III-6.5. Software Classes III-148UEFI Platform Initialization Specification, Release 1.8
Table 6.46: Defined Subclasses: Host Software Class
Unspecified EFI_SOFTWARE_UNSPECIFIED Thesoftwaretypeisunknown,undefined,or
unspecified.
Security SEC EFI_SOFTWARE_SEC The software is a part of the SEC phase.
PEI Foundation E FI_SOFTWARE_PEI_CORE ThesoftwareisthePEIFoundationmodule.
PEI module EFI _SOFTWARE_PEI_MODULE The software is a PEIM.
DXE Foundation E FI_SOFTWARE_DXE_CORE The software is the DXE Foundation mod-
ule.
DXE Boot Service
driverEFI_SOFTWARE_DXE _BS_DRIVER The software is a DXE Boot Service driver.
Boot service drivers are not available once
ExitBootServices() is called.
DXE Runtime Ser-
vice driverEFI_SOFTWARE_DXE_RT_DRIVER The software is a DXE Runtime Service
driver. Thesedriversexecuteduringruntime
phase.
SMM driver EFI _SOFTWARE _SMM_DRIVER The software is a SMM driver.
EFI application EFI_SOFTWARE_EFI _APPLICATION The software is a UEFI application.
OS loader EFI_SOFTWARE_EFI _OS_LOADER The software is an OS loader.
Runtime (RT) EFI_SOFTWARE_EFI_RT The software is a part of the RT phase.
EBC exception EFI_SOFTWARE_EBC _EXCEPTION ThestatuscodeisdirectlyrelatedtoanEBC
IA-32 exception EFI_SOFTWARE_IA32 _EXCEPTION The status code is directly related to an IA-
32 exception.
Itanium processor
family exceptionEFI_SOFTWARE_IPF _EXCEPTION The status code is directly related to an Ita-
nium processor family exception.
x64 software excep-
tionEFI_SOFTWARE_X64 _EXCEPTION The status code is directly related to anx64
ARM software ex-
ceptionEFI_SOFTWARE_ARM _EXCEPTION ThestatuscodeisdirectlyrelatedtoanARM
exceptionwhilstexecutinginAArch32state.
ARM AArch64 ex-
ceptionEFI_SOFTWARE_AARCH64 _EXCEP-
TIONThestatuscodeisdirectlyrelatedtoanARM
exceptionwhilstexecutinginAArch64state.
RISC-V software
exceptionEFI_SOFTWARE_RISCV _EXCEPTION ThestatuscodeisdirectlyrelatedtoRISC-V
PEI Services EFI_SOFTWARE_PEI _SERVICE The status code is directly related to a PEI
Services function.
EFI Boot Services EFI_SOFTWARE_EFI_BOOT _SERVICE ThestatuscodeisdirectlyrelatedtoaUEFI
Boot Services function.
EFI Runtime Ser-
vicesEFI_SOFTWARE_EFI _RUN-
TIME_SERVICEThestatuscodeisdirectlyrelatedtoaUEFI
Runtime Services function.
DXE Services EFI_SOFTWARE_EFI_DXE_SERVICE The status code is directly related to a DXE
0x13-0x7F Reservedforfutureusebythisspecification. NA
0x80-0xFF Reserved for OEM use. NA
III-6.5. Software Classes III-149UEFI Platform Initialization Specification, Release 1.8
III-6.5.5.2 Unspecified Subclass
Thissubclassappliestoanysoftwareentitynotbelongingtoanyoftheothersoftwaresubclasses. Itmayalsobeused
if the caller is unable to determine the exact subclass.
In addition to the standard progress and error codes that are defined for the Host Software class, the table below lists
Table6.47: ProgressandErrorCodeOperations: HostSoftwareUnspec-
ified Subclass
None.
III-6.5.5.3 SEC Subclass
This subclass applies to the Security (SEC) phase in software.
InadditiontothestandardprogressanderrorcodesthataredefinedfortheHostSoftwareclass,thetablebelowliststhe
additional codes for this subclass. In most platforms, status code services may be unavailable during the SEC phase.
Table 6.48: Progress and Error Code Operations: SECSubclass
Type of
Progress EFI_SW_SEC_PC_ENTRY_POINT Entry point of the phase. None
EFI_SW_SEC_PC _HAND-
OFF_TO_NEXTHanding off to the next phase None
specificationReserved for future
tion
Error 0x1000 0x7FFF Reserved for future use by this
See the following topic in Software Classes for definitions of the subclass-specific operations listed above:
III-6.5. Software Classes III-150UEFI Platform Initialization Specification, Release 1.8
III-6.5.5.4 PEI Foundation Subclass
This subclass applies to the PEI Foundation. The PEI Foundation is responsible for starting and ending the PEI phase
as well as dispatching Pre-EFI Initialization Modules (PEIMs).
Table 6.49: Progress and Error Code Operations: PEIFoundation Sub-
class
Type of
tended
Data
Progress EFI_SW_PEI_CORE_PC_ENTRY_POINT Entry point of the phase None
EFI_SW_PEI_CORE_PC_HANDOFF _TO_NEXT Handing off to the next phase
(DXE)None
EFI_SW_PEI_CORE_PC_RETURN _TO_LAST Returning to the last phase None
0x1003-0x7FFF Reserved for future use by this
Error EFI_SW_PEI_CORE_EC_DXE _CORRUPT Unable to hand off to DXE
because the DXE Foundation
could not be foundNone
EFI_SW_PEI_CORE_EC_DXEIPL _NOT_FOUND DXEIPLPPIcouldnotbefound None
EFI_SW_PEI_CORE_EC_MEMORY
_NOT_INSTALLEDPEIM dispatching is over and
InstallPeiMemory()PEIService
has not been calledNone
III-6.5.5.5 PEI Module Subclass
This subclass applies to Pre-EFI Initialization Modules (PEIMs).
III-6.5. Software Classes III-151UEFI Platform Initialization Specification, Release 1.8
Table 6.50: Progress and Error Code Operations: PEIModule Subclass
Type of
tended
Data
Progress EFI_SW_PEI_PC_RECOVERY_BEGIN Crisis recovery has been initi-
ated.NULL
EFI_SW_PEI_PC_CAPSULE_LOAD Found a recovery capsule.
About to load the recovery
capsule.NULL
EFI_SW_PEI_PC_CAPSULE_START Loaded the recovery capsule.
About to hand off control to the
EFI_SW_PEI_PC_RECOVERY_USER Recoverywasforcedbytheuser
via a jumper, for example. Re-
ported by the PEIM that detects
thejumpersandupdatestheboot
mode.NULL
EFI_SW_PEI_PC_RECOVERY_AUTO Recoverywasforcedbythesoft-
ware based on some policy. Re-
portedbythePEIMthatupdates
thebootmodetoforcerecovery.NULL
EFI_SW_PEI_PC_S3_BOOT_SCRIPT S3 boot script execution. NULL
EFI_SW_PEI_PC_OS_WAKE Calling OS S3 wake up vector. NULL
EFI_SW_PEI_PC_S3_STARTED Signifies beginning of the
EFI_PEI_S3 _RESUME_PPI
S3 RestoreConfig() execution.NULL
0x1008-0x7FFF Reserved for future use by this
specification.NULL
Error EFI _SW_PEI_EC_NO _RECOVERY_CAPSULE Unable to continue with the cri-
sisrecoverybecausenorecovery
capsule was found.NULL
EFI_SW_PEI_EC_INVALID _CAP-
SULE_DESCRIPTORAninvalidorcorruptcapsulede-
scriptor was detected.NULL
EFI_SW_PEI_EC_S3_RESUME _PPI_NOT_FOUND S3 Resume PPI is not found. NULL
EFI_SW_PEI_EC_S3_BOOT _SCRIPT_ERROR Error during boot script execu-
tion.NULL
EFI_SW_PEI_EC_S3_OS _WAKE_ERROR Error related to the OS wake up
vector (no valid vector found or
vector returned control back to
the firmware)NULL
EFI_SW_PEI_EC_S3 _RESUME_FAILED Unspecified S3 resume failure. NULL
EFI_SW_PEI_EC_RECOVERY _PPI_NOT_FOUND Recovery failed because Recov-
ery Module PPI is not found.NULL
EFI_SW_PEI_EC _RECOVERY_FAILED Unspecified Recovery failure. NULL
EFI_SW_PEI_EC_S3_RESUME _ERROR ErrorduringS3resumeprocess. NULL
EFI_SW_PEI_EC_INVALID _CAPSULE Invalid capsule is detected. NULL
0x100A-0x7FFF Reserved for future use by this
III-6.5. Software Classes III-152UEFI Platform Initialization Specification, Release 1.8
III-6.5.5.6 DXE Foundation Subclass
This subclass applies to DXE Foundation software. The DXE Foundation is responsible for providing core services,
dispatching DXE drivers, and calling the Boot Device Selection (BDS) phase.

Table 6.51: Progress and Error Code Operations: DXEFoundation Sub-
class
Type of
Progress EFI_SW_DXE_CORE_PC_ENTRY _POINT Entry point of the
phase.None
EFI_SW_DXE_CORE_PC_HANDOFF _TO_NEXT Handing off to the
next phase (Run-
time).None
EFI_SW_DXE_CORE_PC_RETURN _TO_LAST Returning to the last
EFI_SW_DXE_CORE_PC_START _DRIVER Calling the Start()
function of the EFI
_DRIVER_BINDING
Protocol.See EFI_STATUS
_CODE_START
_EX-
EFI_SW_DXE_CORE_PC_ARCH _READY All architectural
protocols are avail-
able.None
0x1005-0x7FFF Reserved for future
tion.NA
Error EFI_SW_DXE_CORE_EC_NO_ARCH Driver dispatching
is over and some
of the architectural
protocols are not
available.None
0x1001-0x7FFF Reserved for future
tion.NA
See Extended Error Data in Software Classes for definitions of the extended error data listed above.
III-6.5. Software Classes III-153UEFI Platform Initialization Specification, Release 1.8
III-6.5.5.7 DXE Boot Service Driver Subclass
This subclass applies to DXE boot service drivers. If a driver provides both boot services and runtime services, it is
considered a runtime service driver.
III-6.5. Software Classes III-154UEFI Platform Initialization Specification, Release 1.8
Table 6.52: Progress and Error Code Operations: DXEBoot Service
Driver Subclass
Type of
Progress EFI_SW_DXE_BS_PC_LEGACY
_OPROM_INITInitializing a legacy Option
ROM (OpROM).See
EFI_LEGACY_OPROM
_EX-
EFI_SW_DXE_BS_PC_READY
_TO_BOOT_EVENTThe EFI_EVENT_GROUP
_READY_TO_BOOT event
was signaled. See the UEFI
Specification .None
EFI_SW_DXE_BS_PC
_LEGACY_BOOT_EVENTThe event with GUID
EFI_EVENT_LEGACY
_BOOT_GUID was signaled.
See the DXE CIS.None
EFI_SW_DXE_BS_PC_EXIT
_BOOT_SERVICES_EVENTThe EVT_SIGNAL_EXIT
_BOOT_SERVICES event
SpecificationNone
EFI_SW_DXE_BS_PC_VIRTUAL _AD-
DRESS_CHANGE_EVENTThe EVT_SIGNAL_VIRTUAL
_ADDRESS_CHANGE event
EFI_SW_DXE_BS_PC _VARI-
ABLE_SERVICES_INITVariable Services initialization None
EFI _SW_DXE_BS_PC _VARI-
ABLE_RECLAIMVariableServicesdriverisabout
to start variable store reclaim
process (a process of storage
optimization by removing stale
data).None
EFI_SW_DXE_BS_PC _CONFIG_RESET Configuration is about to be re-
setNone
EFI_SW_DXE_BS_PC _CSM_INIT Compatibility (legacy BIOS)
Support Module initialization.None
Error EFI_SW_DXE_BS_EC
_LEGACY_OPROM_NO_SPACENotenoughmemoryavailableto
shadow a legacy option ROM.See
_ EX-
TENDED_DATA.
RomImageBase
corresponds to the
ROM image in the
regular memory as
opposed to shadow
RAM.
EFI_SW_DXE_BS_EC _IN-
VALID_PASSWORDInvalid password has been pro-
vided.None
EFI_SW_DXE_BS_EC
_BOOT_OPTION_LOAD_ERRORErrorduringbootoptionloading
(LoadImage returned error).E
FI_RETURN_STATU
S_EXTENDED_DATA
_BOOT_OPTION_FAILEDError during boot option launch
(StartImage returned error).EFI_RETURN_STATUS
_EX-
EFI_SW_DXE_BS_EC_INVALID
_IDE_PASSWORDInvalidharddriverpasswordhas
been provided.None
Progress EFI_SW_DXE_BS_PC_ATTEMPT
_BOOT_ORDER_EVENTAttempting boot from options
defined in the BootOrder list.None
0x1005-0x7FFF Reserved for future use by this
specification.NAIII-6.5. Software Classes III-155UEFI Platform Initialization Specification, Release 1.8
III-6.5.5.8 DXE Runtime Service Driver Subclass
This subclass applies to DXE runtime service drivers.
Table 6.53: Progress and Error Code Operations: DXERuntime Service
None.
III-6.5.5.9 SMM Driver Subclass
This subclass applies to SMM code.
Table 6.54: Progress and Error Code Operations: SMMDriver Subclass
None.
III-6.5. Software Classes III-156UEFI Platform Initialization Specification, Release 1.8
III-6.5.5.10 EFI Application Subclass
This subclass applies to UEFI applications.
Table6.55: ProgressandErrorCodeOperations: UEFIApplicationSub-
class
None.
III-6.5.5.11 OS Loader Subclass
This subclass applies to any OS loader application. Although OS loaders are UEFI applications, they are very special
cases and merit a separate subclass.
Table 6.56: Progress and Error Code Operations: OSLoader Subclass
None.
III-6.5.6 Runtime (RT) Subclass
This subclass applies to runtime software. Runtime software is made up of the UEFI-aware operating system and the
non-UEFI software running under the operating system environment. Other firmware components, such as SAL code
orASLcode,arealsoexecutingduringthisphasebutcannotcallaUEFIruntimeservice. Hencenocodesarereserved
for them.
•InadditiontothestandardprogressanderrorcodesthataredefinedfortheHostSoftwareclass,thetablebelow
lists the additional codes for this subclass.
III-6.5. Software Classes III-157UEFI Platform Initialization Specification, Release 1.8
Table 6.57: Progress and Error Code Operations: Runtime Subclass
Type of
tended
Data
Progress EFI_SW_RT_PC_ENTRY_POINT Entry point of the phase. None
EFI_SW_RT_PC_RETURN_TO_LAST Returning to the last phase. None
EFI_SW_RT_PC_HANDOFF_TO_NEXT
0x1003-0x7FFF Reservedforfutureusebythisspecification. NA
Error 0x1000-0x7FFF Reservedforfutureusebythisspecification. NA
III-6.5.6.1 PEI Services Subclass
This subclass applies to any PEI Service present in the PEI Services Table.
Progress and Error Codes
the additional codes for this subclass. These progress codes are reported by the code that provides the specified boot
service and not by the module that invokes the given boot service.
Manyofthedescriptionsbelowrefertothe PlatformInitializationPre-EFIInitializationCoreInterfaceSpecification ,
or PEI CIS. Also, see “Related Definitions” below for links to the definitions of code listed in this table.
III-6.5. Software Classes III-158UEFI Platform Initialization Specification, Release 1.8
Table 6.58: Progress and Error Code Operations: PEISubclass
Type
of

Type
of
tended
Data
Progress EFI_SW_PS_PC_INSTALL_PPI Install a PPI. See the PEI CIS. None
EFI_SW_PS_PC_REINSTALL_PPI Reinstall a PPI. See the PEI CIS. None
EFI_SW_PS_PC_LOCATE_PPI Locateanexisting. PPISeethePEICIS. None
EFI_SW_PS_PC_NOTIFY_PPI Install a notification callback. See the
PEI CIS.None
EFI_SW_PS_PC_GET_BOOT_MODE Get the current boot mode. See the PEI
CIS.None
EFI_SW_PS_PC_SET_BOOT_MODE Set the current boot mode. See the PEI
CIS.None
EFI_SW_PS_PC_GET_HOB_LIST Get the HOB list. See the PEI CIS. None
EFI_SW_PS_PC_CREATE_HOB Create a HOB. See the PEI CIS. None
Progress
contEFI_SW_PS_PC_FFS_FIND_NEXT_VOLUME Find the next FFS formatted firmware
volume. See the PEI CIS.None
EFI_SW_PS_PC_FFS_FIND_NEXT_FILE FindthenextFFSfile. SeethePEICIS. None
EFI_SW_PS_PC_FFS_FIND_SECTION_DATA Find a section in an FFS file. See the
EFI_SW_PS_PC_INSTALL_PEI_MEMORY Install the PEI memory. See the PEI
CIS.None
EFI_SW_PS_PC_ALLOCATE_PAGES Allocate pages from the memory heap.
See the PEI CIS.None
EFI_SW_PS_PC_ALLOCATE_POOL Allocate from the memory heap. See
the PEI CIS.None
EFI_SW_PS_PC_COPY_MEM Copy memory. See the PEI CIS. None
EFI_SW_PS_PC_SET_MEM Set a memory range to a specific value.
EFI_SW_PS_PC_RESET_SYSTEM System reset. See the PEI CIS. None
EFI_SW_PS_PC_FFS_FIND_FILE_BY_NAME Find a file in a firmware volume by
name. See the PEI CIS.None
EFI_SW_PS_PC_FFS_GET_FILE_INFO Get information about a file in a
firmware volume. See the PEI CIS.None
EFI_SW_PS_PC_FFS_GET_VOLUME_INFO Get information about a firmware vol-
ume. See the PEI CIS.None
EFI_SW_PS_PC_FFS_REGISTER
_FOR_SHADOWRegister a module to be shadowed after
permanent memory is discovered. See
0x1017-0x7fff Reserved for future use by this specifi-
cation.NA
Error EFI_SW_PS_EC_RESET_NOT_AVAILABLE ResetSystem() PEI Service is failed be-
cause Reset PPI is not available.None
EFI_SW_PS_EC_MEMORY_INSTALLED
_TWICEInstallPeiMemory() PEI Service is
called more than once.None
0x1002 0x7FFF Reserved for future use by this specifi-
cation.NA
III-6.5. Software Classes III-159UEFI Platform Initialization Specification, Release 1.8
III-6.5.6.2 Boot Services Subclass
This subclass applies to any boot service present in the UEFI Boot Services Table.
Table6.59: ProgressandErrorCodeOperations: BootServicesSubclass
Progress EFI_SW_BS_PC_RAISE_TPL Raise the task priority level service; see UEFI Specification. This code is an invalid operation because the status code driver uses this boot service. The status code driver cannot report its own status codes. None
EFI_SW_BS_PC_RESTORE_TPL Restore the task priority level service; see UEFI Specification. This code is an invalid operation because the status code driver uses this boot service. The status code driver cannot report its own status codes. None
EFI_SW_BS_PC_ALLOCATE_PAGE Allocate page service; see UEFI Specification. None
EFI_SW_BS_PC_FREE_PAGES Free page service; see UEFI Specification. None
EFI_SW_BS_PC_GET_MEMORY_MAP Get memory map service; see UEFI Specification. None
EFI_SW_BS_PC_ALLOCATE_POOL Allocate pool service; see UEFI Specification. None
EFI_SW_BS_PC_FREE_POOL Free pool service see; UEFI Specification. None
EFI_SW_BS_PC_CREATE_EVENT CreateEvent service see; UEFI Specification. None
EFI_SW_BS_PC_SET_TIMER Set timer service see; UEFI Specification. None
EFI_SW_BS_PC_WAIT_FOR_EVENT Wait for event service see; UEFI Specification. None
Progress cont EFI_SW_BS_PC_SIGNAL_EVENT Signal event service; see UEFI Specification. This code is an invalid operation because the status code driver uses this boot service. The status code driver cannot report its own status codes. None
EFI_SW_BS_PC_CLOSE_EVENT Close event service; see UEFI Specification None
EFI_SW_BS_PC_CHECK_EVENT Check event service; see UEFI Specification None
EFI_SW_BS_PC_INSTALL _PROTOCOL_INTERFACE Install protocol interface service; see UEFI Specification None
EFI_SW_BS_PC_REINSTALL _PROTOCOL_INTERFACE Reinstall protocol interface service; see UEFI Specification None
EFI_SW_BS_PC_UNINSTALL _PROTOCOL_INTERFACE Uninstall protocol interface service; see UEFI Specification None
EFI_SW_BS_PC_HANDLE _PROTOCOL Handle protocol service; see UEFI Specification None
EFI_SW_BS_PC_PC _HANDLE_PROTOCOL PC handle protocol service; see UEFI Specification None
EFI_SW_BS_PC_REGISTER _PROTOCOL_NOTIFY Register protocol notify service; see UEFI Specification None
EFI_SW_BS_PC_LOCATE _HANDLE Locate handle service; see UEFI Specification None
EFI_SW_BS_PC_INSTALL _CONFIGURATION_TABLE Install configuration table service; see UEFI Specification None
EFI_SW_BS_PC_LOAD_IMAGE Load image service; see UEFI Specification None
EFI_SW_BS_PC_START_IMAGE Start image service; see UEFI Specification None
EF I_SW_BS_PC_EXIT Exit service; see UEFI Specification None
EFI_SW_BS_PC_UNLOAD _IMAGE Unload image service; see UEFI Specification None
EFI_SW_BS_PC_EXIT_BOOT _SERVICES Exit boot services service; see UEFI Specification None
EFI_SW_BS_PC_GET_NEXT _MONOTONIC_COUNT Get next monotonic count service; see UEFI Specification None
EFI _SW_BS_PC_STALL Stall service; see UEFI Specification None
EFI_SW_BS_PC_SET_WATCHDOG _TIMER Set watchdog timer service; see UEFI Specification None
EFI_SW_BS_PC_CONNECT _CONTROLLER Connect controller service; see UEFI Specification None
Progress cont EFI_SW_BS_PC_DISCONNECT _CONTROLLER Disconnect controller service; see UEFI Specification None
EFI_SW_BS_PC_OPEN_PROTOCOL Open protocol service; see UEFI Specification None
EFI_SW_BS_PC_CLOSE_PROTOCOL Close protocol service; see UEFI Specification None
EFI_SW_BS_PC_OPEN_PROTOCOL _INFORMATION Open protocol Information service; see UEFI Specification None
EFI_SW_BS_PC_PROTOCOLS _PER_HANDLE Protocols per handle service; see UEFI Specification None
EFI_SW_BS_PC_LOCATE _HANDLE_BUFFER Locate handle buffer service; see UEFI Specification None
EFI_SW_BS_PC_LOCATE_PROTOCOL Locate protocol service; see UEFI Specification None
E FI_SW_BS_PC_INSTALL_MULTIPLE _PROTOCOL_INTERFACES Install multiple protocol interfaces service; see UEFI Specification None
EFI_SW_BS_PC_UNINSTALL_MULTIPLE _PROTOCOL_INTERFACES Uninstall multiple protocol interfaces service; see UEFI Specification None
III-6.5. Software Classes III-160UEFI Platform Initialization Specification, Release 1.8
Table 6.59 – continued from previous page
EFI_SW_BS_PC_CALCULATE _CRC_32 Calculate CRC32 service; see UEFI Specification None
EFI_SW_BS_PC_COPY_MEM Copy memory; see UEFI Specification None
EFI_SW_BS_PC_SET_MEM Set memory to a specific value; see UEFI Specification None
EFI_SW_BS_PC_CREATE_EVENT_EX Create an event and optionally associate it with an event group. See the UEFI Specification None
0x102b-0x7fff Reserved for future use by this specification NA
III-6.5.6.3 Runtime Services Subclass
This subclass applies to any runtime service present in the UEFI Runtime Services Table.
the additional codes for this subclass. For obvious reasons, the runtime service ReportStatusCode() cannot report
status codes related to the progress of the ReportStatusCode() function.
III-6.5. Software Classes III-161UEFI Platform Initialization Specification, Release 1.8
Table 6.60: Progress and Error Code Operations:Runtime Services Sub-
class
Type of
tended
Data
Progress EFI_SW_RS_PC_GET_TIME Get time service; see UEFI
Specification.None
EFI_SW_RS_PC_SET_TIME Settimeservice;seeUEFISpec-
ification.None
EFI_SW_RS_PC_GET _WAKEUP_TIME Get wakeup time service; see
UEFI Specification.None
EFI_SW_RS_PC_SET _WAKEUP_TIME Set wakeup time service; see
EFI_SW_RS_PC_SET _VIRTUAL_ADDRESS_MAP Set virtual address map service;
see UEFI Specification.None
EFI_SW_RS_PC_CONVERT _POINTER Convert pointer service; see

class
Type of
tended
Data
EFI_SW_RS_PC_GET _VARIABLE Get variable service; see UEFI
EFI_SW_RS_PC_GET_NEXT _VARIABLE_NAME Get next variable name service;
EFI_SW_RS_PC_SET _VARIABLE Set variable service; see UEFI
EFI_SW_RS_PC_GET_NEXT
_HIGH_MONOTONIC_COUNTGet next high monotonic count
service;seeUEFISpecification.None
EFI_SW_RS_PC_RESET _SYSTEM Reset system service; see UEFI
EFI_SW_RS_PC_UPDATE _CAPSULE Update a capsule. See the UEFI
EFI_SW_RS_PC_QUERY_CAPSULE _CAPABILI-
TIESQueryfirmwaresupportforcap-
sulate capabilities.See the UEFI
specification.None
EFI_SW_RS_PC_QUERY_VARIABLE _INFO Query firmware support for EFI
variables. See the UEFI specifi-
cation.None
0x100E Reserved for future use by this
Error 0x1000-0x7FFF Reserved for future use by this
III-6.5. Software Classes III-162UEFI Platform Initialization Specification, Release 1.8
III-6.5.6.4 DXE Services Subclass
This subclass applies to any DXE Service that present in the UEFI DXE Services Table.
Table6.61: ProgressandErrorCodeOperations: DXEServicesSubclass
Type of
tended
Data
Progress EFI_SW_DS_PC_ADD _MEM-
ORY_SPACEAdd memory to GCD. See DXE CIS. None
EFI_SW_DS_PC_ALLOCATE _MEM-
ORY_SPACEAllocatememoryfromGCD.SeeDXECIS. None
EFI_SW_DS_PC_FREE _MEM-
ORY_SPACEFree memory from GCD. See DXE CIS. None
EFI_SW_DS_PC_REMOVE _MEM-
ORY_SPACERemovememoryfromGCD.SeeDXECIS. None
EFI_SW_DS_PC_GET _MEM-
ORY_SPACE_DESCRIPTORGet memory descriptor from GCD. See
DXE CIS.None
EFI_SW_DS_PC_SET _MEM-
ORY_SPACE_ATTRIBUTESSet attributes of memory in GCD. See DXE
CIS.None
EFI_SW_DS_PC_GET_MEMORY
_SPACE_MAPGet map of memory space from GCD. See
EFI_SW_DS_PC_ADD _IO_SPACE Add I/O to GCD. See DXE CIS. None
EFI_SW_DS_PC_ALLOCATE
_IO_SPACEAllocate I/O from GCD. See DXE CIS. None
EFI_SW_DS_PC_FREE _IO_SPACE Free I/O from GCD. See DXE CIS. None
EFI_SW_DS_PC_REMOVE_IO _SPACE RemoveI/OspacefromGCD.SeeDXECIS. None
EFI_SW_DS_PC_GET_IO_SPACE _DE-
SCRIPTORGet I/O space descriptor from GCD. See
EFI_SW_DS_PC_GET_IO _SPACE_MAP Get map of I/O space from the GCD. See
EFI_SW_DS_PC_DISPATCH Dispatch DXE drivers from a firmware vol-
ume. See DXE CIS.None
EFI_SW_DS_PC_SCHEDULE Clear the schedule on request flag for a
driver. See DXE CIS.None
EFI_SW_DS_PC_TRUST Promoteafiletotrustedstate. SeeDXECIS. None
EFI_SW_DS_PC_PROCESS
_FIRMWARE_VOLUMEDispatch all drivers in a firmware volume.
See DXE CIS.None
0x1011-0x7FFF Reservedforfutureusebythisspecification. NA
Progress Code Definitions
III-6.5. Software Classes III-163UEFI Platform Initialization Specification, Release 1.8
III-6.6 Code Definitions
This section provides the code definitions for the following data types and structures for status codes:
•Data structures and types that are common to all status codes
•Progress, error, and debug codes that are common to all classes
•Class definitions
•Subclass definitions for each status code class
•Extended error data
Thissectiondefinesthedatastructuresthatarecommontoallstatuscodes. Forclass-andsubclass-specificinformation,
seeClass Definitions .
III-6.6.1 Data Structures
See theReportStatusCode() declaration in Volume 2 of this specification for definitions and details on the following
basic data structures:
•EFI_STATUS_CODE_TYPE and defined severities
•EFI_PROGRESS_CODE
•EFI_ERROR_CODE
•EFI_DEBUG_CODE
•EFI_STATUS_CODE_VALUE
III-6.6.2 Extended Data Header
III-6.6.2.1 EFI_STATUS_CODE_DATA
Summary
The definition of the status code extended data header. The data will follow HeaderSize bytes from the beginning of
the structure and is Sizebytes long.
Size
Type
TheGUIDdefiningthetypeofthedata. ThestandardGUIDsandtheirassociateddatastructuresaredefinedin
III-6.6. Code Definitions III-164UEFI Platform Initialization Specification, Release 1.8
The status code information may be accompanied by optional extended data. The extended data begins with a header.
Theheadercontainsa Typefieldthatrepresentstheformatoftheextendeddatafollowingtheheader. Thisspecification
defines two GUIDs and their meaning. If these GUIDs are used, the extended data contents must follow this specifi-
cation. Extended data formats that are not compliant with this specification are permitted, but they must use different
GUIDs. Theformatoftheextendeddataheaderisdefinedin PlatformInitializationDXECIS ,butitisduplicatedhere
for convenience.
III-6.6.2.2 EFI_STATUS_CODE_DATA_TYPE_STRING_GUID
Summary
Defines a string type of extended data.
GUID
#define EFI_STATUS_CODE_DATA_TYPE_STRING_GUID \
{ 0x92D11080, 0x496F, 0x4D95, 0xBE, 0x7E, 0x03, 0x74, \
0x88, 0x38, 0x2B, 0x0A }
Prototype
EFI_STATUS_CODE_DATA DataHeader;
EFI_STRING_TYPE StringType;
EFI_STATUS_CODE_STRING String;
} EFI_STATUS_CODE_STRING_DATA;
DataHeader
The data header identifying the data. D ataHeader.HeaderSize should be sizeof
(EFI_STATUS_CODE_DATA) ,DataHeader.Size shouldbe sizeof (EFI_STATUS_CODE_STRING_DATA) -
HeaderSize andDataHeader.Type should be EFI_STATUS_CODE_DATA_TYPE_STRING_GUID .
StringType
Specifiestheformatofthedatain String. TypeEFI_STRING_TYPE isdefinedin“RelatedDefinitions”below.
String
Apointertotheextendeddata. Thedatafollowstheformatspecifiedby StringType . TypeEFI_STRING_TYPE
This data type defines a string type of extended data. A string can accompany any status code. The string can provide
additional information about the status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure
(HII) token/GUID pair.
// EFI_STRING_TYPE
EfiStringAscii,
EfiStringUnicode,
III-6.6. Code Definitions III-165UEFI Platform Initialization Specification, Release 1.8
EfiStringToken
} EFI_STRING_TYPE;
EfiStringAscii
ANULL-terminated ASCII string.
EfiStringUnicode
A double NULL-terminated Unicode string.
AnEFI_STATUS_CODE_STRING_TOKEN representing the string. The actual string can be obtained by querying
the HII database.
// EFI_STATUS_CODE_STRING_TOKEN
//
// HII string token
//
EFI_HII_HANDLE Handle;
EFI_STRING_ID Token;
} EFI_STATUS_CODE_STRING_TOKEN;
Handle
TheHIIpackagelistwhichcontainsthestring. Handleisadynamicvaluethatmaynotbethesamefordifferent
boots. Type EFI_HII_HANDLE isdefinedin EFI_HII_DATABASE_PROTOCOL.NewPackageList() intheUEFI
Token
When combined with Handle, the string token can be used to retrieve the string. Type EFI_STRING_ID is
defined in EFI_IFR_OP_HEADER in theUEFI Specification.
// EFI_STATUS_CODE_STRING
//
// String structure
//
CHAR8 *Ascii;
CHAR16 *Unicode;
EFI_STATUS_CODE_STRING_TOKEN Hii;
} EFI_STATUS_CODE_STRING;
Ascii
ASCII formatted string.
Unicode
Unicode formatted string.
Hii
HII handle/token pair. Type EFI_STATUS_CODE_STRING_TOKEN is defined above.
III-6.6. Code Definitions III-166UEFI Platform Initialization Specification, Release 1.8
III-6.6.2.3 EFI_STATUS_CODE_SPECIFIC_DATA_GUID
Summary
Indicates that the format of the accompanying data depends upon the status code value but follows this specification.
GUID
#define EFI_STATUS_CODE_SPECIFIC_DATA_GUID \
{0x335984bd,0xe805,0x409a,0xb8,0xf8,0xd2,0x7e, \
0xce,0x5f,0xf7,0xa6}
This GUID indicates that the format of the accompanying data depends upon the status code value but follows this
specification. This specification defines the format of the extended data for several status code values. For example,
EFI_DEBUG_ASSERT_DATA definestheextendederrordatafortheerrorcode EFI_SW_EC_ILLEGAL_SOFTWARE_STATE

//
//
Ascii
Unicode
Hii
Summary
GUID
. The agent reporting this error condition can use this GUID if the extended data follows the format defined in
EFI_DEBUG_ASSERT_DATA .
If the consumer of the status code detects this GUID, it must look up the status code value to correctly interpret the
contents of the extended data.
This specification declares certain ranges of status code values as OEM specific. Because this specification does not
definethemeaningofstatuscodesintheseranges,theextendeddataforthesecannotusethisGUID.TheOEMdefining
the meaning of the status codes is responsible for defining the GUID that is to be used for associated extended data.
III-6.6.3 Enumeration Schemes
III-6.6.3.1 Operation Code Enumeration Scheme
Summary
All operation codes (regardless of class and subclass) use the progress code partitioning scheme listed in the table
below.
Table 6.62: Progress Code Enumeration Scheme
Operation Description
0x0000-0x0FFF These operation codes are common to all the subclasses in a given class.
These values are used to represent operations that are common to all sub-
classes in a given class. For example, all the I/O buses in the I/O Bus sub-
classesshareanoperationcodethatrepresentstheresetoperation,whichisa
commonoperationformostbuses. Itispossiblethatcertainoperationcodes
in this range will not be applicable to certain subclasses. It is also possible
that the format of the extended data will vary from one subclass to another.
Ifthesubclassdoesnotdefinetheformatoftheextendeddataextendeddata
is not required. These codes are reserved by this specification.
0x1000-0x7FFF These operation codes are specific to the subclass and represent operations
that are specific to the subclass. These codes are reserved by this specifica-
tion.
Prototype
III-6.6. Code Definitions III-167UEFI Platform Initialization Specification, Release 1.8
//
// General partitioning scheme for Progress and Error Codes
// 0x0000-0x0FFF - Shared by all subclasses in a given class
// 0x1000-0x7FFF - Subclass Specific
// 0x8000-0xFFFF - OEM specific
//
#define EFI_SUBCLASS_SPECIFIC 0x1000
#define EFI_OEM_SPECIFIC 0x8000
III-6.6.3.2 Debug Code Enumeration Scheme
Summary
All classes share these debug operation codes. It is not currently expected that operation codes have a lot of meaning
fordebuginformation. Onlyonedebugcodeiscurrentlydefinedbythisspecificationanditissharedbyallclassesand
subclasses.
Table 6.63: Debug Code Enumeration Scheme
Debug Code Description
0x0000-0x7FFF Reserved for future use by this specification.
Prototype
//
// Debug Code definitions forall classes andsubclass
// Only one debug code isdefined at this point andshould
// be used foranything that gets sent to debug stream.
//
#define EFI_DC_UNSPECIFIED 0x0
III-6.6.4 Common Extended Data Formats
This section specifies formats for the extended data included in a variety of status codes.
III-6.6.4.1 EFI_DEVICE_PATH_EXTENDED_DATA
Summary
Extended data about the device path, which is used for many errors and progress codes to point to the device.
Prototype
EFI_STATUS_CODE_DATA ``DataHeader ``;
// EFI_DEVICE_PATH_PROTOCOL ``DevicePath ``;
} EFI_DEVICE_PATH_EXTENDED_DATA;
III-6.6. Code Definitions III-168UEFI Platform Initialization Specification, Release 1.8
The data header identifying the data. DataHeader.HeaderSize should be sizeof
(EFI_STATUS_CODE_DATA) .DataHeader.Size should be the size of variable-length DevicePath , and
DataHeader.Size is zero for a virtual device that does not have a device path. DataHeader.Type should be
EFI_STATUS_CODE_SPECIFIC_DATA_GUID .
The device path to the controller or the hardware device. Note that this parameter is a variable-length device
pathstructureandnotapointertosuchastructure. Thisstructureispopulatedonlyifitisaphysicaldevice. For
virtual devices, the Size field in DataHeader is set to zero and this field is not populated.
The device path is used to point to the physical device in case there is more than one device belonging to the same
subclass. Forexample,thesystemmaycontaintwoUSBkeyboardsandonePS/2*keyboard. Thedriverthatparsesthe
statuscodecanusethedevicepathextendeddatatodifferentiatebetweenthethree. Theindexfieldisnotusefulinthis
casebecausethereisnostandardnumberingconvention. Devicepathsarepreferredoverusingdevicehandlesbecause
devicehandlesforagivendevicecanchangefromoneboottoanotheranddonotmeananythingbeyondBootServices
time. In certain cases, the bus driver may not create a device handle for a given device if it detects a critical error. In
these cases, the device path extended data can be used to refer to the device, but there may not be any device handles
with an instance of EFI_DEVICE_PATH_PROTOCOL that matches DevicePath . The variable device path structure is
included in this structure to make it self sufficient.
III-6.6.4.2 EFI_DEVICE_HANDLE_EXTENDED_DATA
Summary
Extended data about the device handle, which is used for many errors and progress codes to point to the device.
Prototype
} EFI_DEVICE_HANDLE_EXTENDED_DATA;
The data header identifying the data. DataHeader.HeaderSize should be
sizeof (EFI_STATUS_CODE_DATA) ,DataHeader.Size should be sizeof
(EFI_DEVICE_HANDLE_EXTENDED_DATA) -HeaderSize , and DataHeader.Type should be
Handle
The device handle.
The handle of the device with which the progress or error code is associated. The handle is guaranteed to be accurate
onlyatthetimethestatuscodeisreported. Handlesaredynamicentitiesbetweenboots,sohandlescannotbeconsidered
to be valid if the system has reset subsequent to the status code being reported. Handles may be used to determine a
wide variety of useful information about the source of the status code.
III-6.6. Code Definitions III-169UEFI Platform Initialization Specification, Release 1.8
III-6.6.4.3 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA
Summary
This structure defines extended data describing a PCI resource allocation error.
Prototype
Note:
The following structure contains variable-length fields and cannot be defined as a C-style structure.
UINT32 Bar;
UINT16 DevicePathSize;
UINT16 ReqResSize;
UINT16 AllocResSize;
// UINT8 ReqRes[...];
// UINT8 AllocRes[...];
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA;
Thedataheaderidentifyingthedata. DataHeader.HeaderSize shouldbesizeof (EFI_STATUS_CODE_DATA)
, DataHeader.Size should be ( DevicePathSize + DevicePathSize + DevicePathSize
+sizeof(UINT32) + 3 \* sizeof (UINT16) ), andDataHeader.Type should be
EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
Bar
The PCI BAR. Applicable only for PCI devices. Ignored for all other devices.
DevicePathSize
DevicePathSize should be zero if it is a virtual device that is not associated with a device path. Otherwise,
this parameter is the length of the variable-length DevicePath .
ReqResSize
Represents the size the ReqResparameter. ReqResSize should be zero if the requested resources are not pro-
vided as a part of extended data.
AllocResSize
Represents the size the AllocRes parameter. AllocResSize should be zero if the allocated resources are not
provided as a part of extended data.
The device path to the controller or the hardware device that did not get the requested resources. Note that this
parameter is the variable-length device path structure and not a pointer to this structure.
ReqRes
The requested resources in the format of an ACPI 2.0 resource descriptor. This parameter is not a pointer; it is
the complete resource descriptor.
AllocRes
The allocated resources in the format of an ACPI 2.0 resource descriptor. This parameter is not a pointer; it is
III-6.6. Code Definitions III-170UEFI Platform Initialization Specification, Release 1.8
This extended data conveys details for a PCI resource allocation failure error. See the PCI specification and the ACPI
specification for details on PCI resource allocations and the format for resource descriptors. This error does not detail
why the resource allocation failed. It may be due to a bad resource request or a lack of available resources to satisfy
a valid request. The variable device path structure and the resource structures are included in this structure to make it
self sufficient.
III-6.7 Class Definitions
Summary
Classescorrespondtobroadtypesofsystempieces. Thesetypesarechosentoprovideareasonableinitialclassification
ofthesystementitywhosestatusisrepresented. Therearethreeclassesofhardwareandoneclassforsoftware. These
classes are listed in the table below. Each class is made up of several subclasses. See “Types of Status Codes” for
descriptions of each of these classes.
Table 6.64: Class Definitions
Type of Class Class Name Data Type Name

Summary
User-Accessible Peripherals EFI_PERIPHERAL
Prototype
//
// Class definitions
// Values of 4-127 are reserved forfuture use by this
// specification.
// Values inthe range 128-255 are reserved forOEM use.
//
#define EFI_COMPUTING_UNIT 0x00000000
#define EFI_PERIPHERAL 0x01000000
#define EFI_IO_BUS 0x02000000
#define EFI_SOFTWARE 0x03000000
III-6.7.1 Computing Unit Class
The table below lists the subclasses defined in the Computing Unit class. See the following section for their code
definitions.
Table 6.65: Defined Subclasses: Computing Unit Class
Subclass Code Name
Unspecified EFI_COMPUTING_UNIT_UNSPECIFIED
Host processor EFI_COMPUTING_UNIT_HOST_PROCESSOR
Firmware processor EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR
Service processor EFI_COMPUTING_UNIT_SERVICE_PROCESSOR
I/O processor EFI_COMPUTING_UNIT_IO_PROCESSOR
Cache EFI_COMPUTING_UNIT_CACHE
Memory EFI_COMPUTING_UNIT_MEMORY
Chipset EFI_COMPUTING_UNIT_CHIPSET
III-6.7. Class Definitions III-171UEFI Platform Initialization Specification, Release 1.8
III-6.7.1.1 Subclass Definitions
Summary
Definitions for the Computing Unit subclasses. See Subclasses in Computing Unit Class for descriptions of these
Prototype
//
// Computing Unit Subclass definitions.
// Values of 8-127 are reserved forfuture use by this
// Values of 128-255 are reserved forOEM use.
//
#define EFI_COMPUTING_UNIT_UNSPECIFIED \
(EFI_COMPUTING_UNIT | 0x00000000)
#define EFI_COMPUTING_UNIT_HOST_PROCESSOR \
(EFI_COMPUTING_UNIT | 0x00010000)
#define EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR \
(EFI_COMPUTING_UNIT | 0x00020000)
#define EFI_COMPUTING_UNIT_IO_PROCESSOR \
(EFI_COMPUTING_UNIT | 0x00030000)
#define EFI_COMPUTING_UNIT_CACHE \
(EFI_COMPUTING_UNIT | 0x00040000)
#define EFI_COMPUTING_UNIT_MEMORY \
(EFI_COMPUTING_UNIT | 0x00050000)
#define EFI_COMPUTING_UNIT_CHIPSET \
(EFI_COMPUTING_UNIT | 0x00060000)
III-6.7.1.2 Progress Code Definitions
Summary
ProgresscodedefinitionsfortheComputingUnitclassandallsubclasses. SeeProgressCodeOperationsin“Computing
Unit Class” for descriptions of these progress codes. The following subclasses define additional subclass-specific
progress code operations, which are included below:
•Host processor
•Cache
•Memory
Prototype
//
// Computing Unit Class Progress Code definitions.
// These are shared by all subclasses.
//
#define EFI_CU_PC_INIT_BEGIN 0x00000000
#define EFI_CU_PC_INIT_END 0x00000001
//
// Computing Unit Unspecified Subclass Progress Code
III-6.7. Class Definitions III-172UEFI Platform Initialization Specification, Release 1.8
// definitions.
//
//
// Computing Unit Host Processor Subclass Progress Code
//
#define EFI_CU_HP_PC_POWER_ON_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x00000000)
#define EFI_CU_HP_PC_CACHE_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x00000001)
#define EFI_CU_HP_PC_RAM_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x00000002)
#define EFI_CU_HP_PC_MEMORY_CONTROLLER_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x00000003)
#define EFI_CU_HP_PC_IO_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x00000004)
#define EFI_CU_HP_PC_BSP_SELECT \
(EFI_SUBCLASS_SPECIFIC | 0x00000005)
#define EFI_CU_HP_PC_BSP_RESELECT \
(EFI_SUBCLASS_SPECIFIC | 0x00000006)
#define EFI_CU_HP_PC_AP_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x00000007)
#define EFI_CU_HP_PC_SMM_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x00000008)
//
// Computing Unit Firmware Processor Subclass Progress Code
//
//
// Computing Unit IO Processor Subclass Progress Code
//
//
// Computing Unit Cache Subclass Progress Code definitions.
//
#define EFI_CU_CACHE_PC_PRESENCE_DETECT \
#define EFI_CU_CACHE_PC_CONFIGURATION \
//
// Computing Unit Memory Subclass Progress Code definitions.
//
III-6.7. Class Definitions III-173UEFI Platform Initialization Specification, Release 1.8
#define EFI_CU_MEMORY_PC_SPD_READ \
#define EFI_CU_MEMORY_PC_PRESENCE_DETECT \
#define EFI_CU_MEMORY_PC_TIMING \
#define EFI_CU_MEMORY_PC_CONFIGURING \
#define EFI_CU_MEMORY_PC_OPTIMIZING \
#define EFI_CU_MEMORY_PC_INIT \
#define EFI_CU_MEMORY_PC_TEST \
//
// Computing Unit Chipset Subclass Progress Code definitions.
//
#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT \
#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT \
#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT \
#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT \
#define EFI_CHIPSET_PC_DXE_HB_INIT \
#define EFI_CHIPSET_PC_DXE_NB_INIT \
#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT \
#define EFI_CHIPSET_PC_DXE_SB_RT_INIT \
#define EFI_CHIPSET_PC_DXE_SB_INIT \
#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x00000009)
#define EFI_CHIPSET_PC_DXE_SB_DEVICES_INIT \
(EFI_SUBCLASS_SPECIFIC | 0x0000000A)
III-6.7. Class Definitions III-174UEFI Platform Initialization Specification, Release 1.8
III-6.7.1.3 Error Code Definitions
Summary
ErrorcodedefinitionsfortheComputingUnitclassandallsubclasses. SeeErrorCodeOperationsinComputingUnit
Class for descriptions of these error codes.
The following subclasses define additional subclass-specific error code operations, which are included below:
•Firmware processor
•Cache
•Memory
Prototype
//
// Computing Unit Class Error Code definitions.
//
#define EFI_CU_EC_NON_SPECIFIC 0x00000000
#define EFI_CU_EC_DISABLED 0x00000001
#define EFI_CU_EC_NOT_SUPPORTED 0x00000002
#define EFI_CU_EC_NOT_DETECTED 0x00000003
#define EFI_CU_EC_NOT_CONFIGURED 0x00000004
//
// Computing Unit Unspecified Subclass Error Code definitions.
//
//
// Computing Unit Host Processor Subclass Error Code definitions.
//
#define EFI_CU_HP_EC_INVALID_TYPE \
#define EFI_CU_HP_EC_INVALID_SPEED \
#define EFI_CU_HP_EC_MISMATCH \
#define EFI_CU_HP_EC_TIMER_EXPIRED \
#define EFI_CU_HP_EC_SELF_TEST \
#define EFI_CU_HP_EC_INTERNAL \
#define EFI_CU_HP_EC_THERMAL \
#define EFI_CU_HP_EC_LOW_VOLTAGE \
#define EFI_CU_HP_EC_HIGH_VOLTAGE \
#define EFI_CU_HP_EC_CACHE \
III-6.7. Class Definitions III-175UEFI Platform Initialization Specification, Release 1.8
#define EFI_CU_HP_EC_MICROCODE_UPDATE \
#define EFI_CU_HP_EC_CORRECTABLE \
(EFI_SUBCLASS_SPECIFIC | 0x0000000B)
#define EFI_CU_HP_EC_UNCORRECTABLE \
(EFI_SUBCLASS_SPECIFIC | 0x0000000C)
#define EFI_CU_HP_EC_NO_MICROCODE_UPDATE \
(EFI_SUBCLASS_SPECIFIC | 0x0000000D)
//
// Computing Unit Firmware Processor Subclass Error Code
//
#define EFI_CU_FP_EC_HARD_FAIL \
#define EFI_CU_FP_EC_SOFT_FAIL \
#define EFI_CU_FP_EC_COMM_ERROR \
//
// Computing Unit IO Processor Subclass Error Code definitions.
//
//
// Computing Unit Cache Subclass Error Code definitions.
//
#define EFI_CU_CACHE_EC_INVALID_TYPE \
#define EFI_CU_CACHE_EC_INVALID_SPEED \
#define EFI_CU_CACHE_EC_INVALID_SIZE \
#define EFI_CU_CACHE_EC_MISMATCH \
//
// Computing Unit Memory Subclass Error Code definitions.
//
#define EFI_CU_MEMORY_EC_INVALID_TYPE \
#define EFI_CU_MEMORY_EC_INVALID_SPEED \
#define EFI_CU_MEMORY_EC_CORRECTABLE \
#define EFI_CU_MEMORY_EC_UNCORRECTABLE \
III-6.7. Class Definitions III-176UEFI Platform Initialization Specification, Release 1.8
#define EFI_CU_MEMORY_EC_SPD_FAIL \
#define EFI_CU_MEMORY_EC_INVALID_SIZE \
#define EFI_CU_MEMORY_EC_MISMATCH \
#define EFI_CU_MEMORY_EC_S3_RESUME_FAIL\

//
//
#define EFI_CU_MEMORY_EC_UPDATE_FAIL \
#define EFI_CU_MEMORY_EC_NONE_DETECTED \
#define EFI_CU_MEMORY_EC_NONE_USEFUL \
//
// Computing Unit Chipset Subclass Error Code definitions.
//
#define EFI_CHIPSET_EC_BAD_BATTERY \
#define EFI_CHIPSET_EC_DXE_NB_ERROR \
#define EFI_CHIPSET_EC_DXE_SB_ERROR \
#define EFI_CHIPSET_EC_INTRUDER_DETECT \
III-6.7.1.4 Extended Data Formats
III-6.7.1.4.1 Host Processor Subclass
III-6.7.1.5 EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA
Summary
This structure provides details about the computing unit voltage error.
Prototype
EFI_EXP_BASE10_DATA Voltage;
EFI_EXP_BASE10_DATA Threshold;
} EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA;
The data header identifying the data. DataHeader.HeaderSize should
besizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be sizeof
(EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA) - HeaderSize , andDataHeader.Type should be
III-6.7. Class Definitions III-177UEFI Platform Initialization Specification, Release 1.8
Voltage
The voltage value at the time of the error.
Threshold
The voltage threshold.
This structure provides the voltage at the time of error. It also provides the threshold value indicating the minimum
or maximum voltage that is considered an error. If the voltage is less than the threshold, the error indicates that the
voltage fell below the minimum acceptable value. If the voltage is greater than the threshold, the error indicates that
the voltage rose above the maximum acceptable value.
III-6.7.1.6 EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA
Summary
This structure provides details about the microcode update error.
Prototype
} EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA;
(EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA) - HeaderSize , andDataHeader.Type
should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID .
Version
The version of the microcode update from the header.
III-6.7.1.7 EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA
Summary
This structure provides details about the computing unit timer expiration error.
Prototype
EFI_EXP_BASE10_DATA TimerLimit;
} EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA;
(EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA) - HeaderSize , andDataHeader.Type should
beEFI_STATUS_CODE_SPECIFIC_DATA_GUID .
III-6.7. Class Definitions III-178UEFI Platform Initialization Specification, Release 1.8
TimerLimit
The number of seconds that the computing unit timer was configured to expire.
The timer limit provides the timeout value of the timer prior to expiration.
III-6.7.1.8 EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA
Summary
This structure defines extended data for processor mismatch errors.
Prototype
UINT32 Instance;
} EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA;
sizeof (EFI_STATUS_CODE_DATA) ,DataHeader.Size should be sizeof (EFI\_
HOST_PROCESSOR_MISMATCH_ERROR_DATA) - HeaderSize , and DataHeader.Type should be
Instance
The unit number of the computing unit that does not match.
The attributes describing the failure. See “Related Definitions” below for the type declarations.
This provides information to indicate which processors mismatch, and how they mismatch. The status code contains
theinstancenumberoftheprocessorthatisinerror. Thisstructure’s Instance indicatesthesecondprocessorthatdoes
notmatch. Thisdifferentiationallowstheconsumertodeterminewhichtwoprocessorsdonotmatch. The Attributes
indicatewhatmismatchisbeingreported. Because Attributes isabitfield,morethanonemismatchcanbereported
with one error code.
// EFI_COMPUTING_UNIT_MISMATCH_ATTRIBUTES
//
// All other attributes are reserved forfuture use and
// must be initialized to 0.
//
#define EFI_COMPUTING_UNIT_MISMATCH_SPEED 0x0001
#define EFI_COMPUTING_UNIT_MISMATCH_FSB_SPEED 0x0002
#define EFI_COMPUTING_UNIT_MISMATCH_FAMILY 0x0004
#define EFI_COMPUTING_UNIT_MISMATCH_MODEL 0x0008
#define EFI_COMPUTING_UNIT_MISMATCH_STEPPING 0x0010
#define EFI_COMPUTING_UNIT_MISMATCH_CACHE_SIZE 0x0020
III-6.7. Class Definitions III-179UEFI Platform Initialization Specification, Release 1.8
#define EFI_COMPUTING_UNIT_MISMATCH_OEM1 0x1000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM2 0x2000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM3 0x4000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM4 0x8000
III-6.7.1.9 EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA
Summary
This structure provides details about the computing unit thermal failure.
Prototype
EFI_EXP_BASE10_DATA Temperature;
} EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA;
(EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA) - HeaderSize , andDataHeader.Type should be
Temperature
The thermal value at the time of the error.
Threshold
The thermal threshold.
Thisstructureprovidesthetemperatureatthetimeoferror. Italsoprovidesthethresholdvalueindicatingtheminimum
temperature that is considered an error.
III-6.7.1.10 EFI_CACHE_INIT_DATA
Summary
This structure provides cache initialization data.
Prototype
UINT32 Level;
EFI_INIT_CACHE_TYPE Type;
} EFI_CACHE_INIT_DATA;
Thedataheaderidentifyingthedata. DataHeader.HeaderSize shouldbe sizeof(EFI_STATUS_CODE_DATA
III-6.7. Class Definitions III-180UEFI Platform Initialization Specification, Release 1.8
),DataHeader.Size should be sizeof (EFI_CACHE_INIT_DATA) -HeaderSize , andDataHeader.Type
Level
The cache level. Starts with 1 for level 1 cache.
Type
The type of cache. Type EFI_INIT_CACHE_TYPE is defined in “Related Definitions” below.
This structure contains the cache level and type information.
// EFI_INIT_CACHE_TYPE
// Valid cache types
EfiInitCacheDataOnly,
EfiInitCacheInstrOnly,
EfiInitCacheBoth,
EfiInitCacheUnspecified
} EFI_INIT_CACHE_TYPE;
III-6.7.1.11 EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA
Summary
This structure provides information about the disabled computing unit.
Prototype
UINT32 Cause;
BOOLEAN SoftwareDisabled*;
} EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA;
(EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA) - HeaderSize , andDataHeader.Type should be
Cause
The reason for disabling the processor. See “Related Definitions” below for defined values.
SoftwareDisabled
TRUEif the processor is disabled via software means such as not listing it in the ACPI tables. Such a processor
willrespondtoInterprocessorInterrupts(IPIs). FALSEiftheprocessorishardwaredisabled,whichmeansitis
invisible to software and will not respond to IPIs.
III-6.7. Class Definitions III-181UEFI Platform Initialization Specification, Release 1.8
This structure provides details as to why and how the computing unit was disabled. The causes should cover the
typicalreasonsaprocessorwouldbedisabled. Howtheprocessorwasdisabledisimportantbecausetherearedistinct
differences between hardware and software disabling.
// EFI_CPU_STATE_CHANGE_CAUSE
typedef UINT32 EFI_CPU_STATE_CHANGE_CAUSE;
//
// The reason a processor was disabled
//
#define EFI_CPU_CAUSE_INTERNAL_ERROR 0x0001
#define EFI_CPU_CAUSE_THERMAL_ERROR 0x0002
#define EFI_CPU_CAUSE_SELFTEST_FAILURE 0x0004

//
//
#define EFI_CPU_CAUSE_PREBOOT_TIMEOUT 0x0008
#define EFI_CPU_CAUSE_FAILED_TO_START 0x0010
#define EFI_CPU_CAUSE_CONFIG_ERROR 0x0020
#define EFI_CPU_CAUSE_USER_SELECTION 0x0080
#define EFI_CPU_CAUSE_BY_ASSOCIATION 0x0100
#define EFI_CPU_CAUSE_UNSPECIFIED 0x8000
Table 6.66: Decription of EFI_CPU_STATE_CHANGE_CAUSE fields
EFI_CPU_CAUSE_INTERNAL_ERROR Theprocessorwasdisabledbecauseitsignaledaninter-
nal error (IERR).
EFI_CPU_CAUSE_THERMAL_ERROR The processor was disabled because of a thermal error.
EFI_CPU_CAUSE_SELFTEST_FAILURE The processor was disabled because it failed BIST.
EFI_CPU_CAUSE_PREBOOT_TIMEOUT The processor started execution, but it timed out during
a particular task and was therefore disabled.
EFI_CPU_CAUSE_FAILED_TO_START The processor was disabled because it failed to start ex-
ecution (FRB-3 timeout).
EFI_CPU_CAUSE_CONFIG_ERROR Theprocessorwasdisabledduetoaconfigurationerror.
EFI_CPU_CAUSE_USER_SELECTION The processor state was changed due to user selection.
Applicable to enabling and disabling of processors.
EFI_CPU_CAUSE_BY_ASSOCIATION The processor state was changed due because it shared
thestatewithanotherprocessorandthestateoftheother
processor was changed.
EFI_CPU_CAUSE_UNSPECIFIED The CPU state was changed due to unspecified reason.
Summary
III-6.7. Class Definitions III-182UEFI Platform Initialization Specification, Release 1.8
III-6.7.1.12 EFI_MEMORY_EXTENDED_ERROR_DATA
Summary
This structure defines extended data describing a memory error.
Prototype
EFI_MEMORY_ERROR_GRANULARITY Granularity;
EFI_MEMORY_ERROR_OPERATION Operation;
UINT32 Syndrome;
} EFI_MEMORY_EXTENDED_ERROR_DATA;
(EFI_MEMORY_EXTENDED_ERROR_DATA) - HeaderSize , and DataHeader.Type should be
Granularity
Theerrorgranularitytype. Type EFI_MEMORY_ERROR_GRANULARITY isdefinedin“RelatedDefinitions”below.
Operation
The operation that resulted in the error being detected. Type EFI_MEMORY_ERROR_OPERATION is defined in
Syndrome
Theerrorsyndrome,vendor-specificECCsyndrome,orCRCdataassociatedwiththeerror. Ifunknown,should
be initialized to 0.
Address
Thephysicaladdressoftheerror. Type EFI_PHYSICAL_ADDRESS isdefinedin AllocatePages() intheUEFI
The range, in bytes, within which the error address can be determined.
This structure provides specific details about the memory error that was detected. It provides enough information so
thatconsumerscanidentifytheexactfailureandprovidesenoughinformationtoenablecorrectiveactionifnecessary.
// EFI_MEMORY_ERROR_GRANULARITY
typedef UINT8 EFI_MEMORY_ERROR_GRANULARITY;
//
// Memory Error Granularities
//
#define EFI_MEMORY_ERROR_OTHER 0x01
III-6.7. Class Definitions III-183UEFI Platform Initialization Specification, Release 1.8
#define EFI_MEMORY_ERROR_UNKNOWN 0x02
#define EFI_MEMORY_ERROR_DEVICE 0x03
#define EFI_MEMORY_ERROR_PARTITION 0x04
// EFI_MEMORY_ERROR_OPERATION
typedef UINT8 EFI_MEMORY_ERROR_OPERATION;
//
// Memory Error Operations
//
#define EFI_MEMORY_OPERATION_OTHER 0x01
#define EFI_MEMORY_OPERATION_UNKNOWN 0x02
#define EFI_MEMORY_OPERATION_READ 0x03
#define EFI_MEMORY_OPERATION_WRITE 0x04
#define EFI_MEMORY_OPERATION_PARTIAL_WRITE 0x05
III-6.7.1.13 EFI_STATUS_CODE_DIMM_NUMBER
Summary
This structure defines extended data describing a DIMM.
Prototype
UINT16 Array;
UINT16 Device;
} EFI_STATUS_CODE_DIMM_NUMBER;
(EFI_STATUS_CODE_DATA ),DataHeader.Size should be sizeof (EFI_STATUS_CODE_DIMM_NUMBER) -
HeaderSize , andDataHeader . Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID .
Array
The memory array number.
Device
The device number within that Array.
ThisextendeddataprovidessomecontextthatconsumerscanusetolocateaDIMMwithintheoverallmemoryscheme.
TheArrayandDevicenumbers may indicate a specific DIMM, or they may be populated with the group definitions
III-6.7. Class Definitions III-184UEFI Platform Initialization Specification, Release 1.8
//
// Definitions to describe Group Operations
// Many memory init operations are essentially group
// operations.
//
#define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe
#define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff
#define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe
#define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff
Table 6.67: Definitions to describe Group Operations
EFI_MULTIPLE_MEMORY_DEVICE_OPERATION Adefinitiontodescribethattheoperationis
performedonmultipledeviceswithinthear-
ray.
EFI_ALL_MEMORY_DEVICE_OPERATION Adefinitiontodescribethattheoperationis
performed on all devices within the array.
EFI _MULTIPLE_MEMORY_ARRAY_OPERATION Adefinitiontodescribethattheoperationis
performed on multiple arrays.
EFI_ALL_MEMORY_ARRAY_OPERATION Adefinitiontodescribethattheoperationis
performed on all the arrays.
III-6.7.1.14 EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA
Summary
This structure defines extended data describing memory modules that do not match.
Prototype
EFI_STATUS_CODE_DIMM_NUMBER Instance;
} EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA;
besizeof (EFI_STATUS_CODE_DATA) ,DataHeader.Size should be sizeof
(EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA) - HeaderSize , andDataHeader.Type
Instance
The instance number of the memory module that does not match. See the definition for type
EFI_STATUS_CODE_DIMM_NUMBER .
This extended data may be used to convey the specifics of memory modules that do not match.
III-6.7. Class Definitions III-185UEFI Platform Initialization Specification, Release 1.8
III-6.7.1.15 EFI_MEMORY_RANGE_EXTENDED_DATA
Summary
This structure defines extended data describing a memory range.
Prototype
EFI_PHYSICAL_ADDRESS Start;
EFI_PHYSICAL_ADDRESS Length;
} EFI_MEMORY_RANGE_EXTENDED_DATA;
(EFI_MEMORY_RANGE_EXTENDED_DATA) - HeaderSize , and DataHeader.Type should be
Start
The starting address of the memory range. Type EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in
theUEFI Specification .
Length
The length in bytes of the memory range.
This extended data may be used to convey the specifics of a memory range. Ranges are specified with a start address
and a length.
III-6.7.2 User-Accessible Peripherals Class
The table below lists the subclasses defined in the User-Accessible Peripheral class. See the following subsection for
their code definitions.
Table 6.68: Defined Subclasses: User-Accessible Peripheral Class
Unspecified EFI_PERIPHERAL_UNSPECIFIED
Keyboard EFI_PERIPHERAL_KEYBOARD
Mouse EFI_PERIPHERAL_MOUSE
Local console EFI_PERIPHERAL_LOCAL_CONSOLE
Remote console EFI_PERIPHERAL_REMOTE_CONSOLE
Serial port EFI_PERIPHERAL_SERIAL_PORT
Parallel port EFI_PERIPHERAL_PARALLEL_PORT
Fixed media EFI_PERIPHERAL_FIXED_MEDIA
Removable media EFI_PERIPHERAL_REMOVABLE_MEDIA
Audio input EFI_PERIPHERAL_AUDIO_INPUT
Audio output EFI_PERIPHERAL_AUDIO_OUTPUT
LCD device EFI_PERIPHERAL_LCD_DEVICE
Network device EFI_PERIPHERAL_NETWORK
Docking Station EFI_PERIPHERAL_DOCKING
III-6.7. Class Definitions III-186UEFI Platform Initialization Specification, Release 1.8
Table 6.68 – continued from previous page
Trusted Platform Module EFI_PERIPHERAL_TPM
III-6.7.2.1 Subclass Definitions
Summary
Definitions for the User-Accessible Peripheral subclasses. See Subclasses in User-Accessible Peripherals Class for
descriptions of these subclasses.
Prototype
//
// Peripheral Subclass definitions.
// Values of 12-127 are reserved forfuture use by this
//
#define EFI_PERIPHERAL_UNSPECIFIED \
(EFI_PERIPHERAL | 0x00000000)
#define EFI_PERIPHERAL_KEYBOARD \
(EFI_PERIPHERAL | 0x00010000)
#define EFI_PERIPHERAL_MOUSE \
(EFI_PERIPHERAL | 0x00020000)
#define EFI_PERIPHERAL_LOCAL_CONSOLE \
(EFI_PERIPHERAL | 0x00030000)

Summary
Prototype
//
//
#define EFI_PERIPHERAL_REMOTE_CONSOLE \
(EFI_PERIPHERAL | 0x00040000)
#define EFI_PERIPHERAL_SERIAL_PORT \
(EFI_PERIPHERAL | 0x00050000)
#define EFI_PERIPHERAL_PARALLEL_PORT \
(EFI_PERIPHERAL | 0x00060000)
#define EFI_PERIPHERAL_FIXED_MEDIA \
(EFI_PERIPHERAL | 0x00070000)
#define EFI_PERIPHERAL_REMOVABLE_MEDIA \
(EFI_PERIPHERAL | 0x00080000)
#define EFI_PERIPHERAL_AUDIO_INPUT \
(EFI_PERIPHERAL | 0x00090000)
#define EFI_PERIPHERAL_AUDIO_OUTPUT \
(EFI_PERIPHERAL | 0x000A0000)
#define EFI_PERIPHERAL_LCD_DEVICE \
(EFI_PERIPHERAL | 0x000B0000)
#define EFI_PERIPHERAL_NETWORK \
(EFI_PERIPHERAL | 0x000C0000)
#define EFI_PERIPHERAL_DOCKING \
(EFI_PERIPHERAL | 0x000D0000)
#define EFI_PERIPHERAL_TPM \
(EFI_PERIPHERAL | 0x000E0000)
III-6.7. Class Definitions III-187UEFI Platform Initialization Specification, Release 1.8
III-6.7.2.2 Progress Code Definitions
Summary
ProgresscodedefinitionsfortheUser-AccessiblePeripheralclassandallsubclasses. SeeProgressCodeOperationsin
User-Accessible Peripherals Class for descriptions of these progress codes.
The following subclasses define additional subclass-specific progress code operations, which are included below:
•Keyboard
•Mouse
•Serial port
Prototype
//
// Peripheral Class Progress Code definitions.
//
#define EFI_P_PC_INIT 0x00000000
#define EFI_P_PC_RESET 0x00000001
#define EFI_P_PC_DISABLE 0x00000002
#define EFI_P_PC_PRESENCE_DETECT 0x00000003
#define EFI_P_PC_ENABLE 0x00000004
#define EFI_P_PC_RECONFIG 0x00000005
#define EFI_P_PC_DETECTED 0x00000006
#define EFI_P_PC_REMOVED 0x00000007
//
// Peripheral Class Unspecified Subclass Progress Code
//
//
// Peripheral Class Keyboard Subclass Progress Code definitions.
//
#define EFI_P_KEYBOARD_PC_CLEAR_BUFFER \
#define EFI_P_KEYBOARD_PC_SELF_TEST \
//
// Peripheral Class Mouse Subclass Progress Code definitions.
//
#define EFI_P_MOUSE_PC_SELF_TEST \
//
// Peripheral Class Local Console Subclass Progress Code
III-6.7. Class Definitions III-188UEFI Platform Initialization Specification, Release 1.8
//
//
// Peripheral Class Remote Console Subclass Progress Code
//
//
// Peripheral Class Serial Port Subclass Progress Code
//
#define EFI_P_SERIAL_PORT_PC_CLEAR_BUFFER \
//
// Peripheral Class Parallel Port Subclass Progress Code
//
//
// Peripheral Class Fixed Media Subclass Progress Code
//
//
// Peripheral Class Removable Media Subclass Progress Code
//
//
// Peripheral Class Audio Input Subclass Progress Code
//
//
// Peripheral Class Audio Output Subclass Progress Code
//
//
// Peripheral Class LCD Device Subclass Progress Code
//
III-6.7. Class Definitions III-189UEFI Platform Initialization Specification, Release 1.8
//
// Peripheral Class Network Subclass Progress Code definitions.
//
III-6.7.2.3 Error Code Definitions
Summary
ErrorcodedefinitionsfortheUser-AccessiblePeripheralclassandallsubclasses. SeeErrorCodeOperationsin User-
Accessible Peripherals Class for descriptions of these error codes.
•Keyboard
•Mouse
Prototype
//
// Peripheral Class Error Code definitions.
//
#define EFI_P_EC_NON_SPECIFIC 0x00000000
#define EFI_P_EC_DISABLED 0x00000001
#define EFI_P_EC_NOT_SUPPORTED 0x00000002
#define EFI_P_EC_NOT_DETECTED 0x00000003
#define EFI_P_EC_NOT_CONFIGURED 0x00000004
#define EFI_P_EC_INTERFACE_ERROR 0x00000005
#define EFI_P_EC_CONTROLLER_ERROR 0x00000006
#define EFI_P_EC_INPUT_ERROR 0x00000007
#define EFI_P_EC_OUTPUT_ERROR 0x00000008
#define EFI_P_EC_RESOURCE_CONFLICT \
0x00000009
//
// Peripheral Class Unspecified Subclass Error Code definitions.
//
//
// Peripheral Class Keyboard Subclass Error Code definitions.
//
#define EFI_P_KEYBOARD_EC_LOCKED \
#define EFI_P_KEYBOARD_EC_STUCK_KEY \
#define EFI_P_KEYBOARD_EC_BUFFER_FULL \
III-6.7. Class Definitions III-190UEFI Platform Initialization Specification, Release 1.8
//
// Peripheral Class Mouse Subclass Error Code definitions.
//
#define EFI_P_MOUSE_EC_LOCKED \
//
// Peripheral Class Local Console Subclass Error Code
//
//
// Peripheral Class Remote Console Subclass Error Code
//
//
// Peripheral Class Serial Port Subclass Error Code definitions.
//
//
// Peripheral Class Parallel Port Subclass Error Code
//
//
// Peripheral Class Fixed Media Subclass Error Code definitions.
//
//
// Peripheral Class Removable Media Subclass Error Code
//
//
// Peripheral Class Audio Input Subclass Error Code definitions.
//
//
// Peripheral Class Audio Output Subclass Error Code
//
III-6.7. Class Definitions III-191UEFI Platform Initialization Specification, Release 1.8
//
// Peripheral Class LCD Device Subclass Error Code definitions.
//
//
// Peripheral Class Network Subclass Error Code definitions.
//
III-6.7.2.4 Extended Data Formats
The User-Accessible Peripheral class uses the following extended error data definitions:
•EFI_DEVICE_PATH_EXTENDED_DATA
•EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA
SeeCommon Extended Data Formats for definitions.
III-6.7.3 I/O Bus Class
The table below lists the subclasses defined in the I/O Bus class. See Subclass Definitions for their code definitions.
Table 6.69: Defined Subclasses: I/O Bus Class
Unspecified EFI_IO_BUS_UNSPECIFIED
PCI EFI_IO_BUS_PCI
USB EFI_IO_BUS_USB
InfiniBand* architecture EFI_IO_BUS_IBA
AGP EFI_IO_BUS_AGP
PC card EFI_IO_BUS_PC_CARD
Low pin count (LPC) EFI_IO_BUS_LPC
SCSI EFI_IO_BUS_SCSI
ATA/ATAPI/SATA EFI_IO_BUS_ATA_ATAPI
Fibre Channel EFI_IO_BUS_FC
IP network EFI_IO_BUS_IP_NETWORK
SMBus EFI_IO_BUS_SMBUS
I2C EFI_IO_BUS_I2C
0x0D-0x7F Reserved for future use by this specification.
III-6.7. Class Definitions III-192UEFI Platform Initialization Specification, Release 1.8
III-6.7.3.1 Subclass Definitions
Summary
Definitions for the I/O Bus subclasses. See Subclasses in I/O Bus Class for descriptions of these subclasses.
Prototype
//
// IO Bus Subclass definitions.
// Values of 14-127 are reserved forfuture use by this
//
#define EFI_IO_BUS_UNSPECIFIED \
(EFI_IO_BUS | 0x00000000)
#define EFI_IO_BUS_PCI \
(EFI_IO_BUS | 0x00010000)
#define EFI_IO_BUS_USB \
(EFI_IO_BUS | 0x00020000)
#define EFI_IO_BUS_IBA \
(EFI_IO_BUS | 0x00030000)
#define EFI_IO_BUS_AGP \
(EFI_IO_BUS | 0x00040000)
#define EFI_IO_BUS_PC_CARD \
(EFI_IO_BUS | 0x00050000)
#define EFI_IO_BUS_LPC \
(EFI_IO_BUS | 0x00060000)
#define EFI_IO_BUS_SCSI \
(EFI_IO_BUS | 0x00070000)
#define EFI_IO_BUS_ATA_ATAPI \
(EFI_IO_BUS | 0x00080000)
#define EFI_IO_BUS_FC \
(EFI_IO_BUS | 0x00090000)
#define EFI_IO_BUS_IP_NETWORK \
(EFI_IO_BUS | 0x000A0000)
#define EFI_IO_BUS_SMBUS \
(EFI_IO_BUS | 0x000B0000)
#define EFI_IO_BUS_I2C \
(EFI_IO_BUS | 0x000C0000)
III-6.7.3.2 Progress Code Definitions
Summary
Progress code definitions for the I/O Bus class and all subclasses. See Progress Code Operations in User-Accessible
Peripherals Class for descriptions of these progress codes.
•PCI
Prototype
III-6.7. Class Definitions III-193UEFI Platform Initialization Specification, Release 1.8
//
// IO Bus Class Progress Code definitions.
//
typedef struct _EFI_SIO_PROTOCOL EFI_SIO_PROTOCOL;
#define EFI_IOB_PC_INIT 0x00000000
#define EFI_IOB_PC_RESET 0x00000001
#define EFI_IOB_PC_DISABLE 0x00000002
#define EFI_IOB_PC_DETECT 0x00000003
#define EFI_IOB_PC_ENABLE 0x00000004
#define EFI_IOB_PC_RECONFIG 0x00000005
#define EFI_IOB_PC_HOTPLUG 0x00000006
//
// IO Bus Class Unspecified Subclass Progress Code definitions.
//
//
// IO Bus Class PCI Subclass Progress Code definitions.
//
#define EFI_IOB_PCI_BUS_ENUM \
#define EFI_IOB_PCI_RES_ALLOC \
#defineEFI_IOB_PCI_HPC_INIT \
//
// IO Bus Class USB Subclass Progress Code definitions.
//
//
// IO Bus Class IBA Subclass Progress Code definitions.
//
//
// IO Bus Class AGP Subclass Progress Code definitions.
//
//
// IO Bus Class PC Card Subclass Progress Code definitions.
//
//

//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// IO Bus Class LPC Subclass Progress Code definitions.
//
III-6.7. Class Definitions III-194UEFI Platform Initialization Specification, Release 1.8
//
// IO Bus Class SCSI Subclass Progress Code definitions.
//
//
// IO Bus Class ATA/ATAPI Subclass Progress Code definitions.
//
#define EFI_IOB_ATA_BUS_SMART_ENABLE \
#define EFI_IOB_ATA_BUS_SMART_DISABLE \
#define EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD \
#define EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD \
//
// IO Bus Class FC Subclass Progress Code definitions.
//
//
// IO Bus Class IP Network Subclass Progress Code definitions.
//
//
// IO Bus Class SMBUS Subclass Progress Code definitions.
//
//
// IO Bus Class I2C Subclass Progress Code definitions.
//
III-6.7.3.3 Error Code Definitions
Summary
Error code definitions for the I/O Bus class and all subclasses. See Error Code Operations in User-Accessible Periph-
erals Class for descriptions of these error codes.
•PCI
Prototype
// IO Bus Class Error Code definitions.
//
#define EFI_IOB_EC_NON_SPECIFIC 0x00000000
III-6.7. Class Definitions III-195UEFI Platform Initialization Specification, Release 1.8
#define EFI_IOB_EC_DISABLED 0x00000001
#define EFI_IOB_EC_NOT_SUPPORTED 0x00000002
#define EFI_IOB_EC_NOT_DETECTED 0x00000003
#define EFI_IOB_EC_NOT_CONFIGURED 0x00000004
#define EFI_IOB_EC_INTERFACE_ERROR 0x00000005
#define EFI_IOB_EC_CONTROLLER_ERROR 0x00000006
#define EFI_IOB_EC_READ_ERROR 0x00000007
#define EFI_IOB_EC_WRITE_ERROR 0x00000008
#define EFI_IOB_EC_RESOURCE_CONFLICT 0x00000009
//
// IO Bus Class Unspecified Subclass Error Code definitions.
//
//
// IO Bus Class PCI Subclass Error Code definitions.
//
#define EFI_IOB_PCI_EC_PERR \
#define EFI_IOB_PCI_EC_SERR \
//
// IO Bus Class USB Subclass Error Code definitions.
//
//
// IO Bus Class IBA Subclass Error Code definitions.
//
//
// IO Bus Class AGP Subclass Error Code definitions.
//
//
// IO Bus Class PC Card Subclass Error Code definitions.
//
//
// IO Bus Class LPC Subclass Error Code definitions.
//
//
// IO Bus Class SCSI Subclass Error Code definitions.
III-6.7. Class Definitions III-196UEFI Platform Initialization Specification, Release 1.8
//
//
// IO Bus Class ATA/ATAPI Subclass Error Code definitions.
//
#define EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED \
#define EFI_IOB_ATA_BUS_SMART_DISABLED \
//
// IO Bus Class FC Subclass Error Code definitions.
//
//
// IO Bus Class IP Network Subclass Error Code definitions.
//
//
// IO Bus Class SMBUS Subclass Error Code definitions.
//
//
// IO Bus Class I2C Subclass Error Code definitions.
//
III-6.7.3.4 Extended Data Formats
The I/O Bus class uses the following extended data definitions:
•EFI_DEVICE_HANDLE_EXTENDED_DATA
III-6.7.4 Software Classes
The table below lists the subclasses defined in the Host Software class. See Subclass Definitions for their code defini-
tions.
III-6.7. Class Definitions III-197UEFI Platform Initialization Specification, Release 1.8
Table 6.70: Defined Subclasses: Host Software Class
Unspecified EFI_SOFTWARE_UNSPECIFIED
Security (SEC) EFI_SOFTWARE_SEC
PEI Foundation EFI_SOFTWARE_PEI_CORE
PEI module EFI_SOFTWARE_PEI_MODULE
DXE Foundation EFI_SOFTWARE_DXE_CORE
DXE Boot Service driver EFI_SOFTWARE_DXE_BS_DRIVER
DXE Runtime Service driver EFI_SOFTWARE_DXE_RT_DRIVER
SMM driver EFI_SOFTWARE_SMM_DRIVER
EFI application EFI_SOFTWARE_EFI_APPLICATION
OS loader EFI_SOFTWARE_EFI_OS_LOADER
Runtime (RT) EFI_SOFTWARE_EFI_RT
EBC exception EFI_SOFTWARE_EBC_EXCEPTION
IA 32 exception EFI_SOFTWARE_IA32_EXCEPTION
Itanium processor family exception EFI_SOFTWARE_IPF_EXCEPTION
PEI Services EFI_SOFTWARE_PEI_SERVICE
EFI Boot Service EFI_SOFTWARE_EFI_BOOT_SERVICE
EFI Runtime Service EFI_SOFTWARE_EFI_RUNTIME_SERVICE
DXE Service EFI_SOFTWARE_EFI_DXE_SERVICE
0x13 0x7F Reserved for future use by this specification.
x64 software exception EFI_SOFTWARE_X64_EXCEPTION
ARM AArch32 software exception EFI_SOFTWARE_ARM_EXCEPTION
ARM AArch64 software exception EFI_SOFTWARE_AARCH64_EXCEPTION
RISC V software exception EFI_SOFTWARE_RISCV_EXCEPTION
III-6.7.4.1 Subclass Definitions
Summary
DefinitionsfortheHostSoftwaresubclasses. SeeSubclassesin HostSoftwareClass fordescriptionsofthesesubclasses.
Prototype
//
// Software Subclass definitions.
//
#define EFI_SOFTWARE_UNSPECIFIED \
(EFI_SOFTWARE | 0x00000000)
#define EFI_SOFTWARE_SEC \
(EFI_SOFTWARE | 0x00010000)
#define EFI_SOFTWARE_PEI_CORE \
(EFI_SOFTWARE | 0x00020000)
#define EFI_SOFTWARE_PEI_MODULE \
(EFI_SOFTWARE | 0x00030000)
#define EFI_SOFTWARE_DXE_CORE \
(EFI_SOFTWARE | 0x00040000)
#define EFI_SOFTWARE_DXE_BS_DRIVER \
III-6.7. Class Definitions III-198UEFI Platform Initialization Specification, Release 1.8
(EFI_SOFTWARE | 0x00050000)
#define EFI_SOFTWARE_DXE_RT_DRIVER \
(EFI_SOFTWARE | 0x00060000)
#define EFI_SOFTWARE_SMM_DRIVER \
(EFI_SOFTWARE | 0x00070000)
#define EFI_SOFTWARE_EFI_APPLICATION \
(EFI_SOFTWARE | 0x00080000)
#define EFI_SOFTWARE_EFI_OS_LOADER\
(EFI_SOFTWARE | 0x00090000)
#define EFI_SOFTWARE_RT \
(EFI_SOFTWARE | 0x000A0000)
#define EFI_SOFTWARE_AL \
(EFI_SOFTWARE | 0x000B0000)
#define EFI_SOFTWARE_EBC_EXCEPTION \
(EFI_SOFTWARE | 0x000C0000)
#define EFI_SOFTWARE_IA32_EXCEPTION \
(EFI_SOFTWARE | 0x000D0000)
#define EFI_SOFTWARE_IPF_EXCEPTION \
(EFI_SOFTWARE | 0x000E0000)
#define EFI_SOFTWARE_PEI_SERVICE \
(EFI_SOFTWARE | 0x000F0000
#define EFI_SOFTWARE_EFI_BOOT_SERVICE \
(EFI_SOFTWARE | 0x00100000)
#define EFI_SOFTWARE_EFI_RUNTIME_SERVICE \
(EFI_SOFTWARE | 0x00110000)
#define EFI_SOFTWARE_EFI_DXE_SERVICE \
(EFI_SOFTWARE | 0x00120000)
#define EFI_SOFTWARE_X64_EXCEPTION \
(EFI_SOFTWARE | 0x00130000)
#define EFI_SOFTWARE_ARM_EXCEPTION \
(EFI_SOFTWARE | 0x00140000)
#define EFI_SOFTWARE_AARCH64_EXCEPTION \
(EFI_SOFTWARE | 0x00150000)
III-6.7.4.2 Progress Code Definitions
Summary
Progress code definitions for the Host Software class and all subclasses. See Table 6.44 for descriptions of these
progress codes.
•SEC
•PEI Foundation
•PEI Module
•DXE Boot Service Driver
•Runtime (RT)
III-6.7. Class Definitions III-199UEFI Platform Initialization Specification, Release 1.8
•Boot Services
•Runtime Services
Prototype
//
// Software Class Progress Code definitions.
//
#define EFI_SW_PC_INIT \
0x00000000
#define EFI_SW_PC_LOAD \
0x00000001
#define EFI_SW_PC_INIT_BEGIN \
0x00000002
#define EFI_SW_PC_INIT_END \
0x00000003
#define EFI_SW_PC_AUTHENTICATE_BEGIN \
0x00000004
#define EFI_SW_PC_AUTHENTICATE_END \
0x00000005
#define EFI_SW_PC_INPUT_WAIT \
0x00000006
#define EFI_SW_PC_USER_SETUP \
0x00000007
//
// Software Class Unspecified Subclass Progress Code
//
//
// Software Class SEC Subclass Progress Code definitions.
//
#define EFI_SW_SEC_PC_ENTRY_POINT \
#define EFI_SW_SEC_PC_HANDOFF_TO_NEXT \
//
// Software Class PEI Foundation Subclass Progress Code
//
#define EFI_SW_PEI_CORE_PC_ENTRY_POINT \
#define EFI_SW_PEI_CORE_PC_HANDOFF_TO_NEXT \
#define EFI_SW_PEI_CORE_PC_RETURN_TO_LAST \
III-6.7. Class Definitions III-200UEFI Platform Initialization Specification, Release 1.8
//
// Software Class PEI Module Subclass Progress Code definitions.
//
#define EFI_SW_PEI_PC_RECOVERY_BEGIN \
#define EFI_SW_PEI_PC_CAPSULE_LOAD \
#define EFI_SW_PEI_PC_CAPSULE_START \
#define EFI_SW_PEI_PC_RECOVERY_USER \
#define EFI_SW_PEI_PC_RECOVERY_AUTO \
#define EFI_SW_PEI_PC_S3_BOOT_SCRIPT \
#define EFI_SW_PEI_PC_OS_WAKE \
(EFI_SUBCLASS_SPECIFIC | 0x00000006
#define EFI_SW_PEI_PC_S3_STARTED \

//
//
//
// Software Class DXE Foundation Subclass Progress Code
//
#define EFI_SW_DXE_CORE_PC_ENTRY_POINT \
#define EFI_SW_DXE_CORE_PC_HANDOFF_TO_NEXT \
#define EFI_SW_DXE_CORE_PC_RETURN_TO_LAST \
#define EFI_SW_DXE_CORE_PC_START_DRIVER \
#define EFI_SW_DXE_CORE_PC_ARCH_READY \
//
// Software Class DXE BS Driver Subclass Progress Code
//
#define EFI_SW_DXE_BS_PC_LEGACY_OPROM_INIT \
#define EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT \
#define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT \
#define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT \
#define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT \
III-6.7. Class Definitions III-201UEFI Platform Initialization Specification, Release 1.8
#define EFI_SW_DXE_BS_PC_VARIABLE_SERVICES_INIT \
#define EFI_SW_DXE_BS_PC_VARIABLE_RECLAIM \
III-6.7.4.3 Error Code Definitions
Summary
Error code definitions for the Host Software class and all subclasses. See Error Code Operations in Host Software
Classfor descriptions of these error codes.
•PEIM
•DxeBootServiceDriver
•EFI Byte Code (EBC) exception
•IA-32 exception
•Itanium(r) processor family exception
•ARM AArch32 and AArch64 exceptions
Prototype
//
// Software Class Error Code definitions.
//
#define EFI_SW_EC_NON_SPECIFIC 0x00000000
#define EFI_SW_EC_LOAD_ERROR 0x00000001
#define EFI_SW_EC_INVALID_PARAMETER 0x00000002
#define EFI_SW_EC_UNSUPPORTED 0x00000003
#define EFI_SW_EC_INVALID_BUFFER 0x00000004
#define EFI_SW_EC_OUT_OF_RESOURCES 0x00000005
#define EFI_SW_EC_ABORTED 0x00000006
#define EFI_SW_EC_ILLEGAL_SOFTWARE_STATE 0x00000007
#define EFI_SW_EC_ILLEGAL_HARDWARE_STATE 0x00000008
#define EFI_SW_EC_START_ERROR 0x00000009
#define EFI_SW_EC_BAD_DATE_TIME 0x0000000A
#define EFI_SW_EC_CFG_INVALID 0x0000000B
#define EFI_SW_EC_CFG_CLR_REQUEST 0x0000000C
#define EFI_SW_EC_CFG_DEFAULT 0x0000000D
#define EFI_SW_EC_PWD_INVALID 0x0000000E
#define EFI_SW_EC_PWD_CLR_REQUEST 0x0000000F
#define EFI_SW_EC_PWD_CLEARED 0x00000010
#define EFI_SW_EC_EVENT_LOG_FULL 0x00000011
#define EFI_SW_EC_WRITE_PROTECTED 0x00000012
#define EFI_SW_EC_FV_CORRUPTED 0x00000013
#define EFI_SW_EC_INCONSISTENT_MEMORY_MAP 0x00000014
III-6.7. Class Definitions III-202UEFI Platform Initialization Specification, Release 1.8
//
// Software Class Unspecified Subclass Error Code definitions.
//
//
// Software Class SEC Subclass Error Code definitions.
//
//
// Software Class PEI Foundation Subclass Error Code
//
#define EFI_SW_PEI_CORE_EC_DXE_CORRUPT \
#define EFI_SW_PEI_CORE_EC_DXEIPL_NOT_FOUND \
#define EFI_SW_PEI_CORE_EC_MEMORY_NOT_INSTALLED \
//
// Software Class PEI Module Subclass Error Code definitions.
//
#define EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE \
#define EFI_SW_PEI_EC_INVALID_CAPSULE_DESCRIPTOR \
#define EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND \
#define EFI_SW_PEI_EC_S3_BOOT_SCRIPT_ERROR \
#define EFI_SW_PEI_EC_S3_OS_WAKE_ERROR \
#define EFI_SW_PEI_EC_S3_RESUME_FAILED \
#define EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND \
#define EFI_SW_PEI_EC_RECOVERY_FAILED \
#define EFI_SW_PEI_EC_S3_RESUME_ERROR \
#define EFI_SW_PEI_EC_INVALID_CAPSULE \
//
// Software Class DXE Foundation Subclass Error Code
//
#define EFI_SW_DXE_CORE_EC_NO_ARCH \
III-6.7. Class Definitions III-203UEFI Platform Initialization Specification, Release 1.8
//
// Software Class DXE Boot Service Driver Subclass Error Code
//
#define EFI_SW_DXE_BS_EC_LEGACY_OPROM_NO_SPACE\
#define EFI_SW_DXE_BS_EC_INVALID_PASSWORD \
#define EFI_SW_DXE_BS_EC_BOOT_OPTION_LOAD_ERROR \
#define EFI_SW_DXE_BS_EC_BOOT_OPTION_FAILED \
#define EFI_SW_DXE_BS_EC_INVALID_IDE_PASSWORD \
//
// Software Class DXE Runtime Service Driver Subclass Error Code
//
//
// Software Class SMM Driver Subclass Error Code definitions.
//
//
// Software Class EFI Application Subclass Error Code
//
//
// Software Class EFI OS Loader Subclass Error Code definitions.
//
//
// Software Class EFI RT Subclass Error Code definitions.
//
//
// Software Class EBC Exception Subclass Error Code definitions.
// These exceptions are derived from the debug protocol
// definitions inthe EFI specification.
//
#define EFI_SW_EC_EBC_UNDEFINED \
#define EFI_SW_EC_EBC_DIVIDE_ERROR \
EXCEPT_EBC_DIVIDE_ERROR
#define EFI_SW_EC_EBC_DEBUG \
III-6.7. Class Definitions III-204UEFI Platform Initialization Specification, Release 1.8
EXCEPT_EBC_DEBUG
#define EFI_SW_EC_EBC_BREAKPOINT \
EXCEPT_EBC_BREAKPOINT
#define EFI_SW_EC_EBC_OVERFLOW \
EXCEPT_EBC_OVERFLOW
#define EFI_SW_EC_EBC_INVALID_OPCODE \
EXCEPT_EBC_INVALID_OPCODE
#define EFI_SW_EC_EBC_STACK_FAULT \
EXCEPT_EBC_STACK_FAULT
#define EFI_SW_EC_EBC_ALIGNMENT_CHECK \
EXCEPT_EBC_ALIGNMENT_CHECK
#define EFI_SW_EC_EBC_INSTRUCTION_ENCODING \
EXCEPT_EBC_INSTRUCTION_ENCODING
#define EFI_SW_EC_EBC_BAD_BREAK \
EXCEPT_EBC_BAD_BREAK
#define EFI_SW_EC_EBC_STEP EXCEPT_EBC_STEP
//
// Software Class IA32 Exception Subclass Error Code
//
#define EFI_SW_EC_IA32_DIVIDE_ERROR \
EXCEPT_IA32_DIVIDE_ERROR
#define EFI_SW_EC_IA32_DEBUG \
EXCEPT_IA32_DEBUG
#define EFI_SW_EC_IA32_NMI \
EXCEPT_IA32_NMI
#define EFI_SW_EC_IA32_BREAKPOINT \
EXCEPT_IA32_BREAKPOINT
#define EFI_SW_EC_IA32_OVERFLOW \
EXCEPT_IA32_OVERFLOW
#define EFI_SW_EC_IA32_BOUND \
EXCEPT_IA32_BOUND
#define EFI_SW_EC_IA32_INVALID_OPCODE \
EXCEPT_IA32_INVALID_OPCODE
#define EFI_SW_EC_IA32_DOUBLE_FAULT \
EXCEPT_IA32_DOUBLE_FAULT
#define EFI_SW_EC_IA32_INVALID_TSS \
EXCEPT_IA32_INVALID_TSS
#define EFI_SW_EC_IA32_SEG_NOT_PRESENT \
EXCEPT_IA32_SEG_NOT_PRESENT
#define EFI_SW_EC_IA32_STACK_FAULT \
EXCEPT_IA32_STACK_FAULT
#define EFI_SW_EC_IA32_GP_FAULT \
EXCEPT_IA32_GP_FAULT
#define EFI_SW_EC_IA32_PAGE_FAULT \
EXCEPT_IA32_PAGE_FAULT
III-6.7. Class Definitions III-205UEFI Platform Initialization Specification, Release 1.8
#define EFI_SW_EC_IA32_FP_ERROR \
EXCEPT_IA32_FP_ERROR
#define EFI_SW_EC_IA32_ALIGNMENT_CHECK \
EXCEPT_IA32_ALIGNMENT_CHECK
#define EFI_SW_EC_IA32_MACHINE_CHECK \
EXCEPT_IA32_MACHINE_CHECK
#define EFI_SW_EC_IA32_SIMD EXCEPT_IA32_SIMD
//
// Software Class IPF Exception Subclass Error Code definitions.
//
#define EFI_SW_EC_IPF_ALT_DTLB \
EXCEPT_IPF_ALT_DTLB
#define EFI_SW_EC_IPF_DNESTED_TLB \
EXCEPT_IPF_DNESTED_TLB
#define EFI_SW_EC_IPF_BREAKPOINT \
EXCEPT_IPF_BREAKPOINT
#define EFI_SW_EC_IPF_EXTERNAL_INTERRUPT \
EXCEPT_IPF_EXTERNAL_INTERRUPT
#define EFI_SW_EC_IPF_GEN_EXCEPT \
EXCEPT_IPF_GEN_EXCEPT
#define EFI_SW_EC_IPF_NAT_CONSUMPTION \
EXCEPT_IPF_NAT_CONSUMPTION
#define EFI_SW_EC_IPF_DEBUG_EXCEPT \
EXCEPT_IPF_DEBUG_EXCEPT
#define EFI_SW_EC_IPF_UNALIGNED_ACCESS \
EXCEPT_IPF_UNALIGNED_ACCESS
#define EFI_SW_EC_IPF_FP_FAULT \
EXCEPT_IPF_FP_FAULT
#define EFI_SW_EC_IPF_FP_TRAP \
EXCEPT_IPF_FP_TRAP
#define EFI_SW_EC_IPF_TAKEN_BRANCH \
EXCEPT_IPF_TAKEN_BRANCH
#define EFI_SW_EC_IPF_SINGLE_STEP \
EXCEPT_IPF_SINGLE_STEP
//
// Software Class PEI Service Subclass Error Code definitions.
//
#define EFI_SW_PS_EC_RESET_NOT_AVAILABLE \
#define EFI_SW_PS_EC_MEMORY_INSTALLED_TWICE \
//
// Software Class EFI Boot Service Subclass Error Code
//

//
//
//
//
III-6.7. Class Definitions III-206UEFI Platform Initialization Specification, Release 1.8
//
// Software Class EFI Runtime Service Subclass Error Code \
//
//
// Software Class EFI DXE Service Subclass Error Code \
//
#define EFI_SW_DXE_BS_PC_BEGIN_CONNECTING_DRIVERS \
#define EFI_SW_DXE_BS_PC_VERIFYING_PASSWORD \
//
// Software Class DXE RT Driver Subclass Progress Code
//
#define EFI_SW_DXE_RT_PC_S0 (EFI_SUBCLASS_SPECIFIC | 0x00000000)
#define EFI_SW_DXE_RT_PC_S1 (EFI_SUBCLASS_SPECIFIC | 0x00000001)
#define EFI_SW_DXE_RT_PC_S2 (EFI_SUBCLASS_SPECIFIC |
0x00000002)
#define EFI_SW_DXE_RT_PC_S3 (EFI_SUBCLASS_SPECIFIC | 0x00000003)
#define EFI_SW_DXE_RT_PC_S4 (EFI_SUBCLASS_SPECIFIC | 0x00000004)
#define EFI_SW_DXE_RT_PC_S5 (EFI_SUBCLASS_SPECIFIC | 0x00000005)
//
// Software Class X64 Exception Subclass Error Code definitions.
// definitions inthe EFI
//
#define EFI_SW_EC_X64_DIVIDE_ERROR EXCEPT_X64_DIVIDE_ERROR
#define EFI_SW_EC_X64_DEBUG EXCEPT_X64_DEBUG
#define EFI_SW_EC_X64_NMI EXCEPT_X64_NMI
#define EFI_SW_EC_X64_BREAKPOINT EXCEPT_X64_BREAKPOINT
#define EFI_SW_EC_X64_OVERFLOW EXCEPT_X64_OVERFLOW
#define EFI_SW_EC_X64_BOUND EXCEPT_X64_BOUND
#define EFI_SW_EC_X64_INVALID_OPCODE \
EXCEPT_X64_INVALID_OPCODE
#define EFI_SW_EC_X64_DOUBLE_FAULT EXCEPT_X64_DOUBLE_FAULT
#define EFI_SW_EC_X64_INVALID_TSS EXCEPT_X64_INVALID_TSS
#define EFI_SW_EC_X64_SEG_NOT_PRESENT \
EXCEPT_X64_SEG_NOT_PRESENT
#define EFI_SW_EC_X64_STACK_FAULT EXCEPT_X64_STACK_FAULT
#define EFI_SW_EC_X64_GP_FAULT EXCEPT_X64_GP_FAULT
III-6.7. Class Definitions III-207UEFI Platform Initialization Specification, Release 1.8
#define EFI_SW_EC_X64_PAGE_FAULT EXCEPT_X64_PAGE_FAULT
#define EFI_SW_EC_X64_FP_ERROR EXCEPT_X64_FP_ERROR
#define EFI_SW_EC_X64_ALIGNMENT_CHECK \
EXCEPT_X64_ALIGNMENT_CHECK
#define EFI_SW_EC_X64_MACHINE_CHECK EXCEPT_X64_MACHINE_CHECK
#define EFI_SW_EC_X64_SIMD EXCEPT_X64_SIMD
//
// Software Class ARM Exception Subclass Error Code definitions.
//
#define EFI_SW_EC_ARM_RESET EXCEPT_ARM_RESET
#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION \
EXCEPT_ARM_UNDEFINED_INSTRUCTION
#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT \
EXCEPT_ARM_SOFTWARE_INTERRUPT
#define EFI_SW_EC_ARM_PREFETCH_ABORT \
EXCEPT_ARM_PREFETCH_ABORT
#define EFI_SW_EC_ARM_DATA_ABORT EXCEPT_ARM_DATA_ABORT
#define EFI_SW_EC_ARM_RESERVED EXCEPT_ARM_RESERVED
#define EFI_SW_EC_ARM_IRQ EXCEPT_ARM_IRQ
#define EFI_SW_EC_ARM_FIQ EXCEPT_ARM_FIQ
#define EFI_SW_EC_AARCH64_SYNCHRONOUS_EXCEPTIONS \
EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
#define EFI_SW_EC_AARCH64_IRQ EXCEPT_AARCH64_IRQ
#define EFI_SW_EC_AARCH64_FIQ EXCEPT_AARCH64_FIQ
#define EFI_SW_EC_AARCH64_SERROR EXCEPT_AARCH64_SERROR
//
// Software Class RISC-V Exception Subclass Error Code
//
#define EFI_SW_EC_RISCV_INST_MISALIGNED
EXCEPT_RISCV_INST_MISALIGNED
#define EFI_SW_EC_RISCV_INST_ACCESS_FAULT
EXCEPT_RISCV_INST_ACCESS_FAULT
#define EFI_SW_EC_RISCV_ILLEGAL_INST
EXCEPT_RISCV_ILLEGAL_INST
#define EFI_SW_EC_RISCV_BREAKPOINT EXCEPT_RISCV_BREAKPOINT
#define EFI_SW_EC_RISCV_LOAD_ADDRESS_MISALIGNED \
EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED
#define EFI_SW_EC_RISCV_LOAD_ACCESS_FAULT
EXCEPT_RISCV_LOAD_ACCESS_FAULT
#define EFI_SW_EC_RISCV_STORE_AMO_ADDRESS_MISALIGNED \
EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED
#define EFI_SW_EC_RISCV_STORE_AMO_ACCESS_FAULT \
III-6.7. Class Definitions III-208UEFI Platform Initialization Specification, Release 1.8
EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT
#define EFI_SW_EC_RISCV_ENV_CALL_FROM_UMODE
EXCEPT_RISCV_ENV_CALL_FROM_UMODE
#define EFI_SW_EC_RISCV_ENV_CALL_FROM_SMODE
EXCEPT_RISCV_ENV_CALL_FROM_SMODE
#define EFI_SW_EC_RISCV_ENV_CALL_FROM_HMOD
EXCEPT_RISCV_ENV_CALL_FROM_HMODE
#define EFI_SW_EC_RISCV_ENV_CALL_FROM_MMODE
EXCEPT_RISCV_ENV_CALL_FROM_MMODE
III-6.7.4.4 Extended Data Formats
In addition to the other class-specific error definitions in this subsection, the Host Software class uses the following
extended error data definition:
SeeCommon Extended Data Formats for its definition.
III-6.7.4.5 EFI_DEBUG_ASSERT_DATA
Summary
This structure provides the assert information that is typically associated with a debug assertion failing.
Prototype
EFI_STATUS_CODE_DATA *DataHeader;
UINT32 LineNumber;
UINT32 FileNameSize;
EFI_STATUS_CODE_STRING_DATA *FileName;
} EFI_DEBUG_ASSERT_DATA;
(EFI_STATUS_CODE_DATA) ,DataHeader.Size should be sizeof (EFI_DEBUG_ASSERT_DATA) -
HeaderSize , andDataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID .
LineNumber
The line number of the source file where the fault was generated.
FileNameSize
The size in bytes of FileName .
FileName
A pointer to a NULL-terminated ASCII or Unicode string that represents the file name of the source file where
the fault was generated. Type EFI_STATUS_CODE_STRING_DATA is defined in Extended Data Header .
The data indicates the location of the assertion that failed in the source code. This information includes the file name
and line number that are necessary to find the failing assertion in source code.
III-6.7. Class Definitions III-209UEFI Platform Initialization Specification, Release 1.8
III-6.7.4.6 EFI_STATUS_CODE_EXCEP_EXTENDED_DATA
Summary
This structure defines extended data describing a processor exception error.
Prototype
EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT Context;
} EFI_STATUS_CODE_EXCEP_EXTENDED_DATA;
(EFI_STATUS_CODE_EXCEP_EXTENDED_DATA) - HeaderSize , andDataHeader.Type should be
Context
The system context. Type EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT is defined in “Related Definitions”
below.
This extended data allows the processor context that is present at the time of the exception to be reported with the
exception. The format and contents of the context data varies depending on the processor architecture.
// EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT
EFI_SYSTEM_CONTEXT_EBC SystemContextEbc;
EFI_SYSTEM_CONTEXT_IA32 SystemContextIa32;
EFI_SYSTEM_CONTEXT_IPF SystemContextIpf;
EFI_SYSTEM_CONTEXT_X64 SystemContextX64;
EFI_SYSTEM_CONTEXT_ARM SystemContextArm;
EFI_SYSTEM_CONTEXT_RISCV32 SystemContextRiscV32;
EFI_SYSTEM_CONTEXT_RISCV64 SystemContextRiscV64;
EFI_SYSTEM_CONTEXT_RISCV128 SystemContextRiscv128;
} EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT;
SystemContextEbc
The context of the EBC virtual machine when the exception was generated. Type EFI_SYSTEM_CONTEXT_EBC
is defined in EFI_DEBUG_SUPPORT_PROTOCOL in theUEFI Specification .
SystemContextIa32
The context of the IA-32 processor when the exception was generated. Type EFI_SYSTEM_CONTEXT_IA32 is
defined in the EFI_DEBUG_SUPPORT_PROTOCOL in theUEFI Specification .
SystemContextIpf
The context of the Itanium(r) processor when the exception was generated. Type EFI_SYSTEM_CONTEXT_IPF
is defined in the EFI_DEBUG_SUPPORT_PROTOCOL in theUEFI Specification .
III-6.7. Class Definitions III-210UEFI Platform Initialization Specification, Release 1.8
SystemContextX64
The context of the X64 processor when the exception was generated. Type EFI_SYSTEM_CONTEXT_X64 is de-
fined in the EFI_DEBUG_SUPPORT_PROTOCOL in theUEFI Specification .
SystemContextArm
The context of the ARM processor when the exception was generated. Type EFI_SYSTEM_CONTEXT_ARM is
SystemContextRiscV32
The context of the RISC-V RV32 processor when the exception was generated. Type
EFI_SYSTEM_CONTEXT_RISCV32 is defined in the EFI_DEBUG_SUPPORT_PROTOCOL in theUEFI Speci-
fication.
SystemContextRiscV64
The context of the RISC-V RV64 processor when the exception was generated. Type
EFI_SYSTEM_CONTEXT_RISCV64 is defined in the EFI_DEBUG_SUPPORT_PROTOCOL in theUEFI Speci-
fication.
SystemContextRiscV128
The context of the RISC-V RV128 processor when the exception was generated. Type
EFI_SYSTEM_CONTEXT_RISCV128 is defined in the EFI_DEBUG_SUPPORT_PROTOCOL in theUEFI Spec-
ification.
III-6.7.4.7 EFI_STATUS_CODE_START_EXTENDED_DATA
Summary
This structure defines extended data describing a call to a driver binding protocol start function.
Prototype

fication.
fication.
Summary
Prototype
// EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath;
} EFI_STATUS_CODE_START_EXTENDED_DATA;
(EFI_STATUS_CODE_START_EXTENDED_DATA) - HeaderSize , andDataHeader.Type should be
The controller handle.
DriverBindingHandle
The driver binding handle.
The size of the RemainingDevicePath . It is zero if the Start() function is called with
RemainingDevicePath= NULL .TheUEFISpecification allowsthatthe Start() functionofbusdriverscan
be called in this way.
III-6.7. Class Definitions III-211UEFI Platform Initialization Specification, Release 1.8
Matchesthe RemainingDevicePath parameterbeingpassedtothe Start() function. Notethatthisparameter
is the variable-length device path and not a pointer to the device path.
This extended data records information about a Start() function call. Start() is a member of the UEFI Driver
Binding Protocol.
III-6.7.4.8 EFI_LEGACY_OPROM_EXTENDED_DATA
Summary
This structure defines extended data describing a legacy option ROM (OpROM).
Prototype
EFI_PHYSICAL_ADDRESS RomImageBase;
} EFI_LEGACY_OPROM_EXTENDED_DATA;
The data header identifying the data:
DataHeader.HeaderSize should be sizeof(EFI_STATUS_CODE_DATA) ,DataHeader.Size should
besizeof(EFI_LEGACY_OPROM_EXTENDED_DATA) - HeaderSize , andDataHeader.Type should be
The handle corresponding to the device that this legacy option ROM is being invoked.
The base address of the shadowed legacy ROM image. May or may not point to the shadow RAM area. Type
EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in theUEFI Specification .
ThedevicehandleandROMimagebasecanbeusedbyconsumerstodeterminewhichoptionROMfailed. Duetothe
black-box nature of legacy option ROMs, the amount of information that can be obtained may be limited.
III-6.7.4.9 EFI_RETURN_STATUS_EXTENDED_DATA
Summary
Thisstructuredefinesextendeddatadescribingan EFI_STATUS returnvaluethatstandsforafailedfunctioncall(such
as a UEFI boot service).
Prototype
EFI_STATUS ReturnStatus;
} EFI_RETURN_STATUS_EXTENDED_DATA;
III-6.7. Class Definitions III-212UEFI Platform Initialization Specification, Release 1.8
besizeof(EFI_RETURN_STATUS_EXTENDED_DATA) - HeaderSize , andDataHeader.Type should be
ReturnStatus
TheEFI_STATUS returnvalueoftheserviceorfunctionwhosefailuretriggeredthereportingofthestatuscode
(generally an error code or a debug code).
The extended data records the return value of a service or function call whose failure justifies reporting a status code
(generally an error code or debug code).
III-6.7. Class Definitions III-213CHAPTER
SEVEN
REPORT STATUS CODE ROUTERS
III-7.1 Overview
This section provides the code definitions for the PPI and Protocols used in a Report Status Code Router. These
interfaces allow multiple platform dependent drivers for displaying status code information to coexist without prior
knowledge of one another.
Fig. 7.1:Status Code Services
There is a generic status code driver in each phase. In each case the driver consumes the Report Status Code Protocol
andproducestheReportStatusCodeHandlerPPIorProtocol. EachconsumeroftheReportStatusCodeHandlerPPI
or Protocol will register a callback to receive notification of new Status Codes from the Generic Status Code Driver.
III-7.2 Code Definitions
III-7.2.1 Report Status Code Handler Protocol
III-7.2.1.1 EFI_RSC_HANDLER_PROTOCOL
Summary
Provide registering and unregistering services to status code consumers while in DXE.
GUID
#define EFI_RSC_HANDLER_PROTOCOL_GUID \
{ \
0x86212936, 0xe76, 0x41c8, \
III-214UEFI Platform Initialization Specification, Release 1.8
0xa0, 0x3a, 0x2a, 0xf2, 0xfc, 0x1c, 0x39, 0xe2 \
}
EFI_RSC_HANDLER_REGISTER Register;
EFI_RSC_HANDLER_UNREGISTER Unregister;
} EFI_RSC_HANDLER_PROTOCOL;
Members
Register
Register the callback for notification of status code messages.
Unregister
Unregister the callback.
Onceregistered,statuscodemessageswillbeforwardedtothecallback. Thecallbackmustbeunregisteredbeforeitis
deallocated.
typedef
(EFIAPI *EFI_RSC_HANDLER_CALLBACK) (
IN EFI_STATUS_CODE_TYPE CodeType,
IN EFI_GUID *CallerId,
IN EFI_STATUS_CODE_DATA *Data
);
For parameter descriptions, function descriptions and status code values, see ReportStatusCode() in thePI Speci-
fication,Volume 2, section 14.2 .
III-7.2.1.2 EFI_RSC_HANDLER_PROTOCOL.Register()
Summary
Register the callback function for ReportStatusCode() notification.
Prototype
typedef
(EFIAPI *EFI_RSC_HANDLER_REGISTER) (
IN EFI_RSC_HANDLER_CALLBACK Callback,
IN EFI_TPL Tpl
);
III-7.2. Code Definitions III-215UEFI Platform Initialization Specification, Release 1.8
Callback
A pointer to a function of type EFI_RSC_HANDLER_CALLBACK that is called when a call to
ReportStatusCode() occurs.
Tpl
TPL at which callback can be safely invoked.
When this function is called the function pointer is added to an internal list and any future calls to
ReportStatusCode() will be forwarded to the Callback function. During the boot-services, this is the callback
forwhichthisservicecanbeinvoked. Thereportstatuscoderouterwillcreateaneventsuchthatthecallbackfunction
isonlyinvokedattheTPLforwhichitwasregistered. Theentitythatregistersforthecallbackshouldalsoregisterfor
an event upon generation of exit boot services and invoke the unregister service.
IfthehandlerdoesnothaveaTPLdependency,itshouldregisterforacallbackatTPLhigh. Therouterinfrastructure
will support making callbacks at runtime, but the caller for runtime invocation must meet the following criteria:
1. must be a runtime driver type so that itsmemory is not reclaimed
2. not unregister at exit boot services so that the router will still have its callback address
3. thecallermustbeself-contained(eg. Notcalloutintoanyboot-serviceinterfaces)andberuntimesafe,ingeneral.
Table 7.1: Status Codes Returned
EFI_SUCCESS Function was successfully registered.
EFI_INVALID_PARAMETER The callback function was NULL.
EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No more functions can be registered.
EFI_ALREADY_STARTED The function was already registered. It can’t be registered again.
III-7.2.1.3 EFI_RSC_HANDLER_PROTOCOL.Unregister()
Summary
Remove a previously registered callback function from the notification list.
Prototype
typedef
(EFIAPI *EFI_RSC_HANDLER_UNREGISTER) (
IN EFI_RSC_HANDLER_CALLBACK Callback
);
Callback
A pointer to a function of type EFI_RSC_HANDLER_CALLBACK that is to be unregistered.
A callback function must be unregistered before it is deallocated. It is important that any registered callbacks that are
not runtime complaint be unregistered when ExitBootServices() is called.
III-7.2. Code Definitions III-216UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The function was successfully unregistered.
EFI_INVALID_PARAMETER The callback function was NULL
EFI_NOT_FOUND The callback function was not found to be unregistered.
III-7.2.2 Report Status Code Handler PPI
III-7.2.2.1 EFI_PEI_RSC_HANDLER_PPI
Summary
Provide registering and unregistering services to status code consumers.
GUID
#define EFI_PEI_RSC_HANDLER_PPI_GUID \
{ \
0x65d394, 0x9951, 0x4144, \
0x82, 0xa3, 0xa, 0xfc, 0x85, 0x79, 0xc2, 0x51 \
}
typedef struct _EFI_PEI_RSC_HANDLER_PPI {
EFI_PEI_RSC_HANDLER_REGISTER Register;
EFI_PEI_RSC_HANDLER_UNREGISTER Unregister;
} EFI_PEI_RSC_HANDLER_PPI;
Members
Register
Once registered, status code messages will be forwarded to the callback.
typedef
(EFIAPI *EFI_PEI_RSC_HANDLER_CALLBACK) (
IN CONST EFI_GUID *CallerId,
IN CONST EFI_STATUS_CODE_DATA *Data
);
Forparameterdescriptions,functiondescriptionsandstatuscodevalues,see ReportStatusCode() inthePIspecifi-
cation Volume 1, section 4.5 .

Summary
GUID
{ \
}
Members
Register
typedef
);
III-7.2. Code Definitions III-217UEFI Platform Initialization Specification, Release 1.8
III-7.2.2.2 EFI_PEI_RSC_HANDLER_PPI.Register()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_RSC_HANDLER_REGISTER) (
IN EFI_PEI_RSC_HANDLER_CALLBACK Callback
);
Callback
A pointer to a function of type EFI_PEI_RSC_HANDLER_CALLBACK that is called when a call to
ReportStatusCode() will be forwarded to the Callback function.
EFI_ALREADY_STARTED The function was already registered. It can t be registered again.
III-7.2.2.3 EFI_PEI_RSC_HANDLER_PPI.Unregister()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_RSC_HANDLER_UNREGISTER) (
IN EFI_PEI_RSC_HANDLER_CALLBACK ``Callback ``
);
Callback
A pointer to a function of type EFI_PEI_RSC_HANDLER_CALLBACK that is to be unregistered.
ReportStatusCode() messages will no longer be forwarded to the Callback function.
III-7.2. Code Definitions III-218UEFI Platform Initialization Specification, Release 1.8
III-7.2.3 SMM Report Status Code Handler Protocol
III-7.2.3.1 EFI_SMM_RSC_HANDLER_PROTOCOL
Summary
Provide registering and unregistering services to status code consumers while in DXE SMM.
GUID
#define EFI_SMM_RSC_HANDLER_PROTOCOL_GUID \
{ \
0x2ff29fa7, 0x5e80, 0x4ed9, 0xb3, 0x80, 0x1, 0x7d, 0x3c,
0x55, 0x4f, 0xf4
}
typedef struct _EFI_SMM_RSC_HANDLER_PROTOCOL {
EFI_SMM_RSC_HANDLER_REGISTER Register;
SMM_RSC_HANDLER_UNREGISTER Unregister;
} EFI_SMM_RSC_HANDLER_PROTOCOL;
Members
Register
typedef
(EFIAPI *EFI_SMM_RSC_HANDLER_CALLBACK) (
);
Forparameterdescriptions,functiondescriptionsandstatuscodevalues,see ReportStatusCode() inthePIspecification
Volume 2, section 14.2.
III-7.2. Code Definitions III-219UEFI Platform Initialization Specification, Release 1.8
III-7.2.3.2 EFI_SMM_RSC_HANDLER_PROTOCOL.Register()
Summary
Prototype
typedef
(EFIAPI *EFI_SMM_RSC_HANDLER_REGISTER) (
IN EFI_SMM_RSC_HANDLER_CALLBACK Callback
);
Callback
EFI_OUT_OF_RESOURCES The internal buffer ran out of space No more functions can be registered.
EFI_ALREADY_STARTED The function was already registered It can t be registered again.
III-7.2.3.3 EFI_SMM_RSC_HANDLER_PROTOCOL.Unregister()
Summary
Prototype
typedef
(EFIAPI *EFI_SMM_RSC_HANDLER_UNREGISTER) (
);
Callback
A pointer to a function of type EFI_SMM_RSC_HANDLER_CALLBACK that is to be unregistered.
III-7.2. Code Definitions III-220UEFI Platform Initialization Specification, Release 1.8
III-7.2. Code Definitions III-221CHAPTER
EIGHT
PCD
III-8.1 PCD Protocol Definitions
III-8.1.1 PCD Protocol
III-8.1.1.1 EFI_PCD_PROTOCOL
Summary
Aplatformdatabasethatcontainsavarietyofcurrentplatformsettingsordirectivesthatcanbeaccessedbyadriveror
GUID
#define EFI_PCD_PROTOCOL_GUID \
{ 0x13a3f0f6, 0x264a, 0x3ef0, \
{ 0xf2, 0xe0, 0xde, 0xc5, 0x12, 0x34, 0x2f, 0x34 } }
typedef struct _EFI_PCD_PROTOCOL {
EFI_PCD_PROTOCOL_SET_SKU SetSk ;
EFI_PCD_PROTOCOL_GET_8 Get8;
EFI_PCD_PROTOCOL_GET_16 Get16;
EFI_PCD_PROTOCOL_GET_32 Get32;
EFI_PCD_PROTOCOL_GET_64 Get64;
EFI_PCD_PROTOCOL_GET_POINTER GetPtr;
EFI_PCD_PROTOCOL_GET_BOOLEAN GetBool;
EFI_PCD_PROTOCOL_GET_SIZE GetSize;
EFI_PCD_PROTOCOL_SET_8 Set8;
EFI_PCD_PROTOCOL_SET_16 Set16;
EFI_PCD_PROTOCOL_SET_32 Set32;
EFI_PCD_PROTOCOL_SET_64 Set64;
EFI_PCD_PROTOCOL_SET_POINTER SetPtr;
EFI_PCD_PROTOCOL_SET_BOOLEAN SetBool;
EFI_PCD_PROTOCOL_CALLBACK_ON_SET CallbackOnSet;
EFI_PCD_PROTOCOL_CANCEL_CALLBACK CancelCallback;
EFI_PCD_PROTOCOL_GET_NEXT_TOKEN GetNextToken;
III-222UEFI Platform Initialization Specification, Release 1.8
EFI_PCD_PROTOCOL_GET_NEXT_TOKEN_SPACE GetNextTokenSpace;
} EFI_PCD_PROTOCOL;
SetSku
Establish a current SKU value for the PCD service to use for subsequent data Get/Set requests.
Get8
Retrieve an 8-bit value from the PCD service using a GUIDed token namespace.
Get16
Retrieve a 16-bit value from the PCD service using a GUIDed token namespace.
Get32
Retrieve a 32-bit value from the PCD service using a GUIDed token namespace.
Get64
Retrieve a 64-bit value from the PCD service using a GUIDed token namespace.
GetPtr
Retrieve a pointer to a value from the PCD service using a GUIDed token namespace. Can be used to retrieve
an array of bytes that may represent a data structure, ASCII string, or Unicode string
GetBool
Retrieve a Boolean value from the PCD service using a GUIDed token namespace.
GetSize
Retrieve the size of a particular PCD Token value using a GUIDed token namespace.
Set8
Set an 8-bit value in the PCD service using a GUIDed token namespace
Set16
Set a 16-bit value in the PCD service using a GUIDed token namespace.
Set32
Set a 32-bit value in the PCD service using a GUIDed token namespace.
Set64
Set a 64-bit value in the PCD service using a GUIDed token namespace.
SetPtr
Set a pointer to a value in the PCD service using a GUIDed token namespace. Can be used to set an array of
bytes that may represent a data structure, ASCII string, or Unicode string
SetBool
Set a Boolean value in the PCD service using a GUIDed token namespace.
CallBackOnSet
Establish a notification to alert when a particular PCD Token value is set.
CancelCallBackOnSet
Cancel a previously set notification for a particular PCD Token value.
GetNextToken
Retrieve the next token number that is contained in the PCD name-space.
GetNextTokenSpace
Retrieve the next valid PCD token namespace for a given name-space.
III-8.1. PCD Protocol Definitions III-223UEFI Platform Initialization Specification, Release 1.8
Callers to this protocol must be at a TPL_APPLICATION task priority level.
This is the base PCD service API that provides an abstraction for accessing configuration content in the platform. It
a seamless mechanism for extracting information regardless of where the information is stored (such as in Read-only
data, or an EFI Variable).
This protocol allows access to data through size-granular APIs and provides a mechanism for a firmware component
to monitor specific settings and be alerted when a setting is changed.
III-8.1.1.2 EFI_PCD_PROTOCOL.SetSku ()
Summary
Sets the SKU value for subsequent calls to set or get PCD token values.
Prototype
typedef
VOID
(EFIAPI *EFI_PCD_PROTOCOL_SET_SKU) (
IN UINTN SkuId
);
Parameter
SkuId
The SKU value to set.
SetSku() setstheSKUIdtobeusedforsubsequentcallstosetorgetPCDvalues. SetSku() isnormallycalledonly
once by the system.
For each item (token), the database can hold a single value that applies to all SKUs, or multiple values, where each
value is associated with a specific SKU Id. Items with multiple, SKU-specific values are called SKU enabled .

Summary
Prototype
typedef
VOID
);
Parameter
SkuId
The SKU Id of zero is reserved as a default. For tokens that are not SKU enabled, the system ignores any set SKU Id
andworkswiththesinglevalueforthattoken. ForSKU-enabledtokens,thesystemwillusetheSKUIdsetbythelast
call to SetSku(). If no SKU Id is set or the currently set SKU Id isn’t valid for the specified token, the system uses the
default SKU Id. If the system attempts to use the default SKU Id and no value has been set for that Id, the results are
unpredictable.
III-8.1.1.3 EFI_PCD_PROTOCOL.Get8 ()
Summary
Retrieves an 8-bit value for a given PCD token.
Prototype
typedef
UINT8
(EFIAPI *EFI_PCD_PROTOCOL_GET_8) (
IN UINTN TokenNumber
);
III-8.1. PCD Protocol Definitions III-224UEFI Platform Initialization Specification, Release 1.8
Guid
The 128-bit unique value that designates the namespace from which to extract the value.
TokenNumber
The PCD token number.
Retrieves the current byte-sized value for a PCD token number. If the TokenNumber is invalid, the results are unpre-
dictable.
III-8.1.1.4 EFI_PCD_PROTOCOL.Get16 ()
Summary
Retrieves a 16-bit value for a given PCD token.
Prototype
typedef
UINT16
(EFIAPI *EFI_PCD_PROTOCOL_GET_16) (
IN UINTN TokenNumbe*
);
Guid
Retrieves the current word-sized value for a PCD token number. If the TokenNumber is invalid, the results are unpre-
dictable.
III-8.1.1.5 EFI_PCD_PROTOCOL.Get32 ()
Summary
Retrieves a 32-bit value for a given PCD token.
Prototype
typedef
UINT32
(EFIAPI *EFI_PCD_PROTOCOL_GET_32) (
);
Guid
III-8.1. PCD Protocol Definitions III-225UEFI Platform Initialization Specification, Release 1.8
Retrievesthecurrent32-bitsizedvalueforaPCDtokennumber. Ifthe TokenNumber isinvalid,theresultsareunpre-
dictable.
III-8.1.1.6 EFI_PCD_PROTOCOL.Get64 ()
Summary
Retrieves a 64 -bit value for a given PCD token.
Prototype
typedef
UINT64
(EFIAPI *EFI_PCD_PROTOCOL_GET_64) (
);
Parameter
Guid
Retrievesthe64-bitsizedvalueforaPCDtokennumber. IftheTokenNumberisinvalid,theresultsareunpredictable.
III-8.1.1.7 EFI_PCD_PROTOCOL.GetPtr ()
Summary
Retrieves a pointer to a value for a given PCD token.
Prototype
typedef
VOID *
(EFIAPI *EFI_PCD_PROTOCOL_GET_POINTER) (
);
Guid
III-8.1. PCD Protocol Definitions III-226UEFI Platform Initialization Specification, Release 1.8
RetrievesthecurrentpointertothevalueforaPCDtokennumber. Donotmakeanyassumptionsaboutthealignment
of the pointer that is returned by this function call. If the TokenNumber is invalid, the results are unpredictable.
III-8.1.1.8 EFI_PCD_PROTOCOL.GetBool ()
Summary
Retrieves a Boolean value for a given PCD token.
Prototype
typedef
BOOLEAN
(EFIAPI *EFI_PCD_PROTOCOL_GET_BOOLEAN) (
);
Guid
Retrieves the current BOOLEAN-sized value for a PCD token number. If the TokenNumber is invalid, the results are
III-8.1.1.9 EFI_PCD_PROTOCOL.GetSize ()
Summary
Retrieves the size of the value for a given PCD token.
Prototype
typedef
UINTN
(EFIAPI *EFI_PCD_PROTOCOL_GET_SIZE) (
);
Guid
Retrieves the current size of a particular PCD token. If the TokenNumber is invalid, the results are unpredictable.
III-8.1. PCD Protocol Definitions III-227UEFI Platform Initialization Specification, Release 1.8
III-8.1.1.10 EFI_PCD_PROTOCOL.Set8 ()
Summary
Sets an 8-bit value for a given PCD token.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_SET_8) (
IN UINTN TokenNumber,
IN UINT 8 Value
);
Guid
Value
The value to set for the PCD token.
When the PCD service sets a value, it will check to ensure that the size of the value being set is compatible with the
Token’s existing definition. If it is not, an error will be returned.
Table 8.1: Status Codes Returned
EFI_SUCCESS The PCD service has set the value requested.
EFI_INVALID_PARAMETER ThePCDservicedeterminedthatthesizeofthedatabeingsetwasincompatible
withacalltothisfunction. Use GetBool() toretrievethesizeofthetargetdata.
EFI_NOT_FOUND The PCD service could not find the requested token number.
III-8.1.1.11 EFI_PCD_PROTOCOL.Set16 ()
Summary
Sets a 16-bit value for a given PCD token.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_SET_16) (
IN UINT16 Value
);
III-8.1. PCD Protocol Definitions III-228UEFI Platform Initialization Specification, Release 1.8
Guid
Value
ThevaluetosetforthePCDtoken.The128-bituniquevaluethatdesignatesthenamespacefromwhichtoextract
the value.
Table 8.2: Status Codes Returned
III-8.1.1.12 EFI_PCD_PROTOCOL.Set32 ()
Summary
Sets a 32-bit value for a given PCD token.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_SET_32) (
IN UINT32 Value
);
Guid
Value
III-8.1. PCD Protocol Definitions III-229UEFI Platform Initialization Specification, Release 1.8
III-8.1.1.13 EFI_PCD_PROTOCOL.Set64 ()
Summary
Sets a 64-bit value for a given PCD token.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_SET_64) (
IN UINT64 Value
);
Guid
Value
Table 8.4: Status Codes Returned
III-8.1. PCD Protocol Definitions III-230UEFI Platform Initialization Specification, Release 1.8
III-8.1.1.14 EFI_PCD_PROTOCOL.SetPtr ()
Summary
Sets a value of a specified size for a given PCD token.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_SET_POINTER) (
IN OUT UINTN *SizeOfValue,
);
Guid
SizeOfValue
The length of the value being set for the PCD token. If too large of a length is specified, upon return from this
function the value of SizeOfValue will reflect the maximum size for the PCD token.
Buffer

Summary
Prototype
typedef
);
Guid
Buffer
A pointer to the buffer containing the value to set for the PCD token.
Table 8.5: Status Codes Returned
withacalltothisfunction. The SizeofValue parameterreflectsthemaximum
size of the PCD token referenced. Use GetSize() to retrieve the current size
of the target data.
III-8.1.1.15 EFI_PCD_PROTOCOL.SetBool ()
Summary
Sets a Boolean value for a given PCD token.
Prototype
typedef
III-8.1. PCD Protocol Definitions III-231UEFI Platform Initialization Specification, Release 1.8
(EFIAPI *EFI_PCD_PROTOCOL_SET_BOOLEAN) (
IN BOOLEAN Value
);
Guid
Token
NumberThe PCD token number.
Value
Table 8.6: Status Codes Returned
EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was
incompatiable with a call to this function. Use GetBool() to re-
trieve the size of the target data.
III-8.1.1.16 EFI_PCD_PROTOCOL.CallbackOnSet ()
Summary
Specifies a function to be called anytime the value of a designated token is changed.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_CALLBACK_ON_SET) (
IN CONST EFI_GUID *Guid, OPTIONAL
IN UINTN CallBackToken,
IN EFI_PCD_PROTOCOL_CALLBACK CallBackFunction
);
Guid
The 128-bit unique value that designates which namespace to monitor. If NULL, use the standard platform
namespace.
CallBackToken
The PCD token number to monitor.
III-8.1. PCD Protocol Definitions III-232UEFI Platform Initialization Specification, Release 1.8
CallBackFunction
The function prototype called when the value associated with the CallBackToken is set.
typedef
VOID
(EFIAPI *EFI_PCD_PROTOCOL_CALLBACK) {
IN EFI_GUID *Guid, OPTIONAL
IN OUT VOID *TokenData,
IN UINTN TokenDataSize
};
Table 8.7: Status Codes Returned
EFI_SUCCESS The PCD service has successfully established a call event for the
CallBackToken requested.
EFI_NOT_FOUND The PCD service could not find the referenced token number.
III-8.1.1.17 EFI_PCD_PROTOCOL.CancelCallback ()
Summary
Cancels a previously set callback function for a particular PCD token number.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_CANCEL_CALLBACK) (
);
Guid
The PCD token number for which to cancel monitoring.
The function prototype that was originally passed to the CallBackOnSet function.
Cancels a callback function that was set through a previous call to the CallBackOnSet function.
III-8.1. PCD Protocol Definitions III-233UEFI Platform Initialization Specification, Release 1.8
Table 8.8: Status Codes Returned
EFI_SUCCESS The PCD service has cancelled the call event associated with the
CallBackToken .
EFI_INVALID_PARAMETER ThePCDservicedidnotmatchthe CallBackFunction toonethat
is currently being monitored.
EFI_NOT_FOUND The PCD service could not find data the requested token number.
III-8.1.1.18 EFI_PCD_PROTOCOL.GetNextToken ()
Summary
Retrieves the next valid PCD token for a given namespace.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_GET_NEXT_TOKEN) (
IN UINTN *TokenNumber
);
Guid
The 128-bit unique value that designates the namespace from which to retrieve the next token.
A pointer to the PCD token number to use to find the subsequent token number. To retrieve the “first” token,
have the pointer reference a TokenNumber value of 0.
Gets the next valid token number in a given namespace. This is useful since the PCD infrastructure contains a sparse
list of token numbers, and one cannot a priori know what token numbers are valid in the database.
Table 8.9: Status Codes Returned
EFI_SUCCESS The PCD service has retrieved the value requested.
EFI_NOT_FOUND The PCD service could not find data from the requested token number.
III-8.1.1.19 EFI_PCD_PROTOCOL.GetNextTokenSpace ()
Summary
Retrieves the next valid PCD token namespace for a given namespace.
Prototype
typedef
(EFIAPI *EFI_PCD_PROTOCOL_GET_NEXT_TOKEN_SPACE) (
IN OUT CONST EFI_GUID **Guid
);
III-8.1. PCD Protocol Definitions III-234UEFI Platform Initialization Specification, Release 1.8
Guid
An indirect pointer to EFI_GUID . On input it designates a known token namespace from which the search will
start. On output, it designates the next valid token namespace on the platform. If *GuidisNULL, then the
GUIDofthefirsttokenspaceofthecurrentplatformisreturned. Ifthesearchcannotlocatethenextvalidtoken
namespace, an error is returned and the value of *Guidis undefined.
Getsthenextvalidtokennamespaceforagivennamespace. Thisisusefultotraversethevalidtokennamespacesona
platform.
Table 8.10: Status Codes Returned
EFI_SUCCESS The PCD service retrieved the value requested.
EFI_NOT_FOUND The PCD service could not find the next valid token namespace.
III-8.1.2 Get PCD Information Protocol
III-8.1.2.1 EFI_GET_PCD_INFO_PROTOCOL
Summary
The protocol that provides additional information about items that reside in the PCD database.
GUID
#define EFI_GET_PCD_INFO_PROTOCOL_GUID \
{ 0xfd0f4478, 0xefd, 0x461d, \
{ 0xba, 0x2d, 0xe5, 0x8c, 0x45, 0xfd, 0x5f, 0x5e } }
typedef struct _EFI_GET_PCD_INFO_PROTOCOL {
EFI_GET_PCD_INFO_PROTOCOL_GET_INFO GetInfo;
EFI_GET_PCD_INFO_PROTOCOL_GET_SKU GetSku;
} EFI_GET_PCD_INFO_PROTOCOL;
GetInfo
Retrieve additional information associated with a PCD.
GetSku
Retrieve the currently set SKU Id.
This is the PCD service to use when querying for some additional data that can be contained in the PCD database.
III-8.1. PCD Protocol Definitions III-235UEFI Platform Initialization Specification, Release 1.8
III-8.1.2.2 EFI_GET_PCD_INFO_PROTOCOL.GetInfo ()
Summary
Retrieve additional information associated with a PCD token.
Prototype
typedef
(EFIAPI *EFI_GET_PCD_INFO_PROTOCOL_GET_INFO) (
OUT EFI_PCD_INFO *PcdInfo
);
Guid
PcdInfo
The returned information associated with the requested TokenNumber. See related definitions below.
GetInfo() retrieves additional information associated with a PCD token. This includes information such as the type
ofvaluethe TokenNumber isassociatedwithaswellaspossiblehumanreadablenamethatisassociatedwiththetoken.
EFI_PCD_TYPE PcdType;
UINTN PcdSize;
CHAR8 *PcdName;
} EFI_PCD_INFO;
PcdType
The returned information associated with the requested TokenNumber . IfTokenNumber is 0, thenPcdType is
set toEFI_PCD_TYPE_8 .
PcdSize
The size of the data in bytes associated with the TokenNumber specified. If TokenNumber is 0, then PcdSize
is set 0.
PcdName
The null-terminated ASCII string associated with a given token. If the TokenNumber specified was 0, then this
field corresponds to the null-terminated ASCII string associated with the token’s namespace Guid. If NULL,
there is no name associated with this request.
EFI_PCD_TYPE_8,
EFI_PCD_TYPE_16,
EFI_PCD_TYPE_32,
EFI_PCD_TYPE_64,
EFI_PCD_TYPE_BOOL,
III-8.1. PCD Protocol Definitions III-236UEFI Platform Initialization Specification, Release 1.8
EFI_PCD_TYPE_PTR
} EFI_PCD_TYPE;
Table 8.11: Status Codes Returned
EFI_SUCCESS The PCD information was returned successfully
III-8.1.2.3 EFI_GET_PCD_INFO_PROTOCOL.GetSku ()
Summary

PcdSize
is set 0.
PcdName
Summary
Prototype
typedef
UINTN
(EFIAPI *EFI_GET_PCD_INFO_PROTOCOL_GET_SKU) (
VOID
);
GetSku() returns the currently set SKU Id. If the platform has not set at a SKU Id, then the default SKU Id value of
0 is returned. If the platform has set a SKU Id, then the currently set SKU Id is returned.
III-8.2 PCD PPI Definitions
III-8.2.1 PCD PPI
III-8.2.1.1 EFI_PEI_PCD_PPI
Summary
GUID
#define EFI_PEI_PCD_PPI_GUID \
{ 0x1f34d25, 0x4de2, 0x23ad, \
{ 0x3f, 0xf3, 0x36, 0x35, 0x3f, 0xf3, 0x23, 0xf1 } }
EFI_PEI_PCD_PPI_SET_SKU SetSku;
EFI_PEI_PCD_PPI_GET_8 Get8;
III-8.2. PCD PPI Definitions III-237UEFI Platform Initialization Specification, Release 1.8
EFI_PEI_PCD_PPI_GET_16 Get16;
EFI_PEI_PCD_PPI_GET_32 Get32;
EFI_PEI_PCD_PPI_GET_64 Get64;
EFI_PEI_PCD_PPI_GET_POINTER GetPtr;
EFI_PEI_PCD_PPI_GET_BOOLEAN GetBool;
EFI_PEI_PCD_PPI_GET_SIZE GetSize;
EFI_PEI_PCD_PPI_SET_8 Set8;
EFI_PEI_PCD_PPI_SET_16 Set16;
EFI_PEI_PCD_PPI_SET_32 Set32;
EFI_PEI_PCD_PPI_SET_64 Set64;
EFI_PEI_PCD_PPI_SET_POINTER SetPtr;
EFI_PEI_PCD_PPI_SET_BOOLEAN SetBool;
EFI_PEI_PCD_PPI_CALLBACK_ON_SET CallbackOnSet;
EFI_PEI_PCD_PPI_CANCEL_CALLBACK CancelCallback;
EFI_PEI_PCD_PPI_GET_NEXT_TOKEN GetNextToken;
EFI_PEI_PCD_PPI_GET_NEXT_TOKEN_SPACE GetNextTokenSpace;
} EFI_PEI_PCD_PPI;
SetSku
Get8
Get16
Get32
Get64
GetPtr
an array of bytes that represents a data structure, ASCII string, or Unicode string
GetBool
GetBool
Set8
Set an 8-bit value in the PCD service using a GUIDed token namespace.
Set16
Set32
Set64
III-8.2. PCD PPI Definitions III-238UEFI Platform Initialization Specification, Release 1.8
SetPtr
bytes that represents a data structure, ASCII string, or Unicode string
SetBool
Establish a notification when a particular PCD Token value is set.
Retrieve the next token number that is contained in the PCD namespace.
ThisisthebasePCDserviceAPIthatprovidesanabstractionforaccessingconfigurationcontentintheplatform. Itis
data in an EFI Variable).
This ppi provides access to data through size-granular APIs and provides a mechanism for a firmware component to
monitor specific settings and be alerted when a setting is changed.
III-8.2.1.2 EFI_PEI_PCD_PPI.SetSku ()
Summary
Prototype
typedef
VOID
(EFIAPI *EFI_PEI_PCD_PPI_SET_SKU) (
);
SkuId
value is associated with a specific SKU Id. Items with multiple, SKU-specific values are called SKU enabled. The
SKU Id of zero is reserved as a default. For tokens that are not SKU enabled, the system ignores any set SKU Id and
workswiththesinglevalueforthattoken. ForSKU-enabledtokens,thesystemwillusetheSKUIdsetbythelastcall
toSetSku() . If no SKU Id is set or the currently set SKU Id isn’t valid for the specified token, the system uses the
III-8.2. PCD PPI Definitions III-239UEFI Platform Initialization Specification, Release 1.8
III-8.2.1.3 EFI_PEI_PCD_PPI.Get8 ()
Summary
Prototype
typedef
UINT8
(EFIAPI *EFI_PEI_PCD_PPI_GET_8) (
);
Guid
The 128-bit unique value that designates which namespace to extract the value from.
dictable.
III-8.2.1.4 EFI_PEI_PCD_PPI.Get16 ()
Summary
Retrieves a value for a given PCD token.
Prototype
typedef
UINT16
(EFIAPI *EFI_PEI_PCD_PPI_GET_16) (
);
Guid
dictable.
III-8.2. PCD PPI Definitions III-240UEFI Platform Initialization Specification, Release 1.8
III-8.2.1.5 EFI_PEI_PCD_PPI.Get32 ()
Summary
Prototype
typedef
UINT32
(EFIAPI *EFI_PEI_PCD_PPI_GET_32) (
);
Guid
Retrievesthecurrent32-bitvalueforaPCDtokennumber. Ifthe TokenNumber isinvalid,theresultsareunpredictable.
III-8.2.1.6 EFI_PEI_PCD_PPI.Get64 ()
Summary
Retrieves a 64-bit value for a given PCD token.
Prototype
typedef
UINT64
(EFIAPI *EFI_PEI_PCD_PPI_GET_64) (
);
Guid
Retrieves the 64-bit value for a PCD token number. If the TokenNumber is invalid, the results are unpredictable.
III-8.2. PCD PPI Definitions III-241UEFI Platform Initialization Specification, Release 1.8
III-8.2.1.7 EFI_PEI_PCD_PPI.GetPtr ()
Summary
Retrieves a pointer to the value for a given PCD token.
Prototype
typedef
VOID *
(EFIAPI *EFI_PEI_PCD_PPI_GET_POINTER) (
);
Guid
Retrieves the current pointer to the value for a PCD token number. There should not be any alignment assumptions
about the pointer that is returned by this function call. If the TokenNumber is invalid, the results are unpredictable.
EFI_PEI_PCD_PPI.GetBool ()
Summary
Prototype
typedef
BOOLEAN
(EFIAPI *EFI_PEI_PCD_PPI_GET_BOOLEAN) (
);
Guid
Retrieves the current Boolean-sized value for a PCD token number. If the TokenNumber is invalid, the results are
III-8.2. PCD PPI Definitions III-242UEFI Platform Initialization Specification, Release 1.8
III-8.2.1.8 EFI_PEI_PCD_PPI.GetSize ()
Summary
Prototype
typedef
UINTN
(EFIAPI *EFI_PEI_PCD_PPI_GET_SIZE) (
);
Guid
III-8.2.1.9 EFI_PEI_PCD_PPI.Set8 ()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PPI_SET_8) (
);
Guid
Value

Summary
Prototype
typedef
UINTN
);
Guid
Summary
Prototype
typedef
);
Guid
Value
III-8.2. PCD PPI Definitions III-243UEFI Platform Initialization Specification, Release 1.8
Table 8.12: Status Codes Returned
incompatiblewithacalltothisfunction. Use GetBool() toretrieve
the size of the target data.
III-8.2.1.10 EFI_PEI_PCD_PPI.Set16 ()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PPI_SET_16) (
);
Guid
Value
Table 8.13: Status Codes Returned
III-8.2. PCD PPI Definitions III-244UEFI Platform Initialization Specification, Release 1.8
III-8.2.1.11 EFI_PEI_PCD_PPI.Set32 ()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PPI_SET_32) (
);
Guid
Value
Table 8.14: Status Codes Returned
III-8.2.1.12 EFI_PEI_PCD_PPI.Set64 ()
Summary
Prototype
(EFIAPI *EFI_PEI_PCD_PPI_SET_64) (
);
III-8.2. PCD PPI Definitions III-245UEFI Platform Initialization Specification, Release 1.8
Guid
Value
Table 8.15: Status Codes Returned
III-8.2.1.13 EFI_PEI_PCD_PPI.SetPtr ()
Summary
Sets a value of the specified size for a given PCD token.
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PPI_SET_POINTER) (
);
Guid
Buffer
III-8.2. PCD PPI Definitions III-246UEFI Platform Initialization Specification, Release 1.8
Table 8.16: Status Codes Returned
incompatible with a call to this function. Use GetBool to retrieve
incompatible with a call to this function. The SizeofValue() pa-
rameterreflectsthemaximumsizeofthePCDtokenreferenced. Use
GetSize() to retrieve the current size of the target data
III-8.2.1.14 EFI_PEI_PCD_PPI.SetBool()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PPI_SET_BOOLEAN) (
IN CONST EFI_GUID Guid,
);
Prototype
Guid
Value
Table 8.17: Status Codes Returned
III-8.2. PCD PPI Definitions III-247UEFI Platform Initialization Specification, Release 1.8
III-8.2.1.15 EFI_PEI_PCD_PPI.CallbackOnSet ()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PPI_CALLBACK_ON_SET) (
IN EFI_PEI_PCD_PPI_CALLBACK CallBackFunction
);
Guid
The function prototype that will be called when the value associated with the CallBackToken is set.
typedef
VOID
(EFIAPI * EFI_PEI_PCD_PPI_CALLBACK ) {
IN EFI_GUID *Guid, OPTIONAL,
IN UINTN TokenDatSize
};
Table 8.18: Status Codes Returned
EFI_SUCCESS ThePCDservicehassuccessfullyestablishedacalleventforthe CallBackToken requested.
III-8.2. PCD PPI Definitions III-248UEFI Platform Initialization Specification, Release 1.8
III-8.2.1.16 EFI_PEI_PCD_PPI.CancelCallback ()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PPI_CANCEL_CALLBACK) (
);
Guid
The PCD token number to cancel monitoring.
Table 8.19: Status Codes Returned
III-8.2.1.17 EFI_PEI_PCD_PPI.GetNextToken ()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PPI_GET_NEXT_TOKEN) (
);
III-8.2. PCD PPI Definitions III-249UEFI Platform Initialization Specification, Release 1.8
Guid

Summary
Prototype
typedef
);
Guid
Thisprovidesameansbywhichtogetthenextvalidtokennumberinagivennamespace. ThisisusefulsincethePCD
infrastructure has a sparse list of token numbers in it, and one cannot a priori know what token numbers are valid in
the database.
Table 8.20: Status Codes Returned
EFI_SUCCESS The PCD service has retrieved the value requested
EFI_NOT_FOUND The PCD service could not find data from the requested token number
III-8.2.1.18 EFI_PEI_PCD_PPI.GetNextTokenSpace ()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_PCD_PROTOCOL_GET_NEXT_TOKEN_SPACE) (
);
Guid
start. On output, it designates the next valid token namespace on the platform. If * GuidisNULL, then the
namespace, an error is returned and the value of * Guidis undefined.
platform.
Table 8.21: Status Codes Returned
EFI_SUCCESS The PCD service retrieved the value requested
EFI_NOT_FOUND The PCD service could not find the next valid token namespace
III-8.2. PCD PPI Definitions III-250UEFI Platform Initialization Specification, Release 1.8
III-8.2.2 Get PCD Information PPI
III-8.2.2.1 EFI_GET_PCD_INFO_PPI
Summary
The PPI that provides additional information about items that reside in the PCD database.
GUID
#define EFI_GET_PCD_INFO_PPI_GUID \
{ 0xa60c6b59, 0xe459, 0x425d, \
{ 0x9c, 0x69, 0xb, 0xcc, 0x9c, 0xb2, 0x7d, 0x81 } }
typedef struct _EFI_GET_PCD_INFO_PPI {
EFI_GET_PCD_INFO_PPI_GET_INFO GetInfo;
EFI_GET_PCD_INFO_PPI_GET_SKU GetSku;
} EFI_GET_PCD_INFO_PPI;
GetInfo
GetSku
III-8.2.2.2 EFI_GET_PCD_INFO_PPI.GetInfo ()
Summary
Prototype
typedef
(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_INFO) (
);
Guid
PcdInfo
The returned information associated with the requested TokenNumber .
III-8.2. PCD PPI Definitions III-251UEFI Platform Initialization Specification, Release 1.8
Table 8.22: Status Codes Returned
III-8.2.2.3 EFI_GET_PCD_INFO_PPI.GetSku ()
Summary
Prototype
typedef
UINTN
(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_SKU) (
VOID
);
III-8.2. PCD PPI Definitions III-252Part IV
Management Mode Core InterfaceUEFI Platform Initialization Specification, Release 1.8
List of Figures - Volume IV
•MM Architecture
•Example MM Initialization Components
•MMI Handler Relationships
•Published Protocols for IA-32 Systems
•SAL Calling Diagram
•Early Reset, MCA and INIT flow
•Basic MCA processing flow
•PI MCA processing flow
•PI architectural data in the min
•PI INIT processing flow
•PMI handling flow
IV-iUEFI Platform Initialization Specification, Release 1.8
•Extended SAL Service Classes - EFI Runtime Services
•Extended SAL Service Classes - SAL Procedures
•Extended SAL Service Classes - HardwareAbstractions
•Extended SAL Service Classes - Other
•Extended SAL Base I/O Services Class
•Extended SAL Stall Services Class
•Extended SAL Real Time Clock ServicesClass
•Extended SAL Reset Services Class
•Extended SAL PCI Services Class
•Extended SAL Cache Services Class
•Extended SAL PAL Services Class
•Extended SAL Status Code Services Class
•Extended SAL Monotonic Counter ServicesClass
•Extended SAL Variable Services Class
•Extended SAL MP Services Class
•Extended SAL MCA Services Class
IV-iiCHAPTER
ONE
OVERVIEW
IV-1.1 Definition of Terms
The following terms are used in the MM Core Interface Specification (CIS). See Glossary in the master help system
for additional definitions.
IP
Instruction pointer.
IPI
Interprocessor Interrupt. This interrupt is the means by which multiple processors in a system or a single pro-
cessor can issue APIC-directed messages for communicating with self or other processors.
MM
ManagementMode. Generictermforasecure,isolatedexecutionenvironmententeredwhenaCPUcoredetects
anMMIandjumpstotheMMEntryPointwithinMMRAM.ThiscanbeimplementedbySystemManagement
Mode on x86 processors and TrustZone on ARM processors.
MM Driver
A driver launched directly into MMRAM, with access to the MM interfaces.
MM Driver Initialization
The phase of MM Driver initialization which starts with the call to the driver’s entry point and ends with the
return from the driver’s entry point.
MM Driver Runtime
The phase of MM Driver initialization which starts after the return from the driver’s entry point.
MM Entry Point
When the CPU core(s) enter MM, they begin execution at a pre-defined addresses in a pre-defined operating
mode. At some point later, they jump into the MM Foundation entry point.
MM handler
ADXEdriverthatisloadedintoandexecutedfromMMRAM.MMHandlersaredispatchedduringbootservices
time and invoked synchronously or asynchronously thereafter. MM handlers remain present during runtime.
MMI
ManagementModeInvocation.TheCPUinstructionorhigh-priorityinterruptwhichtransitionsCPUcore(s)into
MM via the MM Entry Point.
MMI Source.
The instruction, interrupt or exception which caused the CPU core(s) to enter MM. An MMI source can be
detected, quiesced and disabled.
MMST
Management Mode System Table. Hand-off to handler.
IV-1UEFI Platform Initialization Specification, Release 1.8
MTRR
Memory Type Range Register.
RSM
Resume. The process by which a CPU exits MM.
IV-1.2 Management Mode (MM)
ManagementMode(MM)isagenerictermusedtodescribeasecureexecutionenvironmentprovidedbytheCPUand
related silicon that is entered when the CPU detects a MMI. For x86 systems, this can be implemented with System
Management Mode (SMM). For ARM systems, this can be implemented with TrustZone (TZ). A MMI can be a CPU
instructionorinterrupt. UpondetectionofaMMI,aCPUwilljumptotheMMEntryPointandsavesomeportionofits
state (the “save state”) such that execution can be resumed. The MMI can be generated synchronously by software or
asynchronously by a hardware event. Each MMI source can be detected, cleared and disabled. Some systems provide
for special memory (Management Mode RAM or MMRAM) which is set aside for software running in MM. Usually
the MMRAM is hidden during normal CPU execution, but this is not required. Usually, after MMRAM is hidden it
cannot be exposed until the next system reset.
IV-1.3 MM Driver Execution Environment
TheMMCoreInterfaceSpecificationdescribestheoptionalMMenvironment,whichexistsinparallelwiththeotherPI
Architecture phases into runtime. The MM Core Interface Specification describes three pieces of the PI Management
Mode architecture:
MM Dispatch
DuringDXE,theDXEFoundationworkswiththeMMFoundationtoscheduleMMdriversforexecutioninthe
discovered firmware volumes.
MM Initialization
MMrelatedcodeopensMMRAM,createstheMMRAMmemorymap,andlaunchestheMMFoundation,which
providesthenecessaryservicestolaunchMM-relateddrivers. Then,sometimebeforeboot,MMRAMisclosed
and locked. This piece may be completed during the SEC, PEI or DXE phases.
MMI Management
When an MMI generated, the MM environment is created and then the MMI sources are detected and MMI
handlers called.
The figure below shows the MM architecture.
Note:The MM architecture does not guarantee support for the execution of handlers written to the EFI Byte Code
(EBC) specification.
IV-1.2. Management Mode (MM) IV-2UEFI Platform Initialization Specification, Release 1.8
Fig. 1.1:MM Architecture
IV-1.4 Initializing Management Mode in MM Traditional Mode

ManagementModeinitializationpreparesthehardwareforMMIgenerationandcreatesthenecessarydatastructuresfor
managingtheMMresourcessuchasMMRAM.ThisspecificationsupportsthreeMMinitializationmodels: SEC,PEI
and DXE. This specification does not describe MM Dispatch or MMI handling during SEC or PEI. Previous versions
of this specification only supported DXE Initialization.
IV-1.4.1 SEC Initialization
In this model, the MM Entry Points are initialized and the MM Foundation is loaded into MMRAM during the SEC
phase. Optionally,MMRAMishiddenandlocked. Then,duringtheDXEphase,MMorMM/DXEdriversareloaded
normally. This is detailed in the following steps:
1. TheSECcodeinitializestheMMenvironment,includinginitializingtheMMEntryPoints,settingupMMRAM,
initializing the MM Foundation in MMRAM.
2. Optionally, the SEC code hides and locks the MMRAM.
3. The SEC code produces the EFI_SEC_HOB_DATA_PPI , which produces a HOB with the GUID
EFI_PEI_MM_CORE_GUID , and the EFI_PEI_MM_CORE_LOADED flag set which indicates that the MM
Foundationisalreadyinstalled. Afterthis,thestepsfollowthoseinDXEinitialization. Thereisnotarchitectural
provision for loading MM-related drivers during the SEC phase.
IV-1.4. Initializing Management Mode in MM Traditional Mode IV-3UEFI Platform Initialization Specification, Release 1.8
IV-1.4.2 PEI Initialization
In this model, the MM Entry Points are initialized and the MM Foundation is loaded into MMRAM during the PEI
1. ThePEIcodeinitializestheMMenvironment,includinginitializingtheMMEntryPoints,settingupMMRAM
and initializing the MM Foundation in MMRAM.
2. Optionally, the PEI code hides and locks the MMRAM.
3. The PEI code produces the HOB with the GUID EFI_PEI_MM_CORE_GUID , and the
EFI_PEI_MM_CORE_LOADED flag set, which indicates that the MM Foundation has already been in-
stalled. After this, the steps follow those in DXE initialization. There is not architectural provision for loading
MM-related drivers during the PEI phase.
IV-1.4.3 DXE Initialization
It is initialized with the cooperation of several DXE drivers:
1. A DXE driver produces the EFI_MM_ACCESS_PROTOCOL , which describes the different MMRAM regions
available in the system.
2. A DXE driver produces the EFI_MM_CONTROL_PROTOCOL , which allows synchronous MMIs to be gener-
ated.
3. A DXE driver (dependent on the EFI_MM_ACCESS_PROTOCOL and, perhaps, the
EFI_MM_CONTROL_PROTOCOL ), does the following:
•IftheMM_CORE_LOADED flagisnotsetinthe EFI_PEI_MM_CORE_GUID HOBwasnotset,initializes
theMMentryvectorwiththecodenecessarytomeettheentrypointrequirementsdescribedinSeeEntering
& Exiting MM..
•If theMM_CORE_LOADED flag is not set in the EFI_PEI_MM_CORE_GUID HOB or that HOB does
not exist, then produces the EFI_MM_CONFIGURATION _PROTOCOL , which describes those areas of
MMRAM which should be excluded from the memory map.
•NOTE:ThisimpliesthatthisDXEdriveriscompletelyoptionalifthe MM_CORE_LOADED flagissetin
theEFI_PEI_MM_CORE_GUID HOB.
4. The MM IPL DXE driver (dependent on the EFI_MM_CONTROL_PROTOCOL ) does the following:
•IfMM_CORE_LOADED flags is set in the EFI_PEI_MM_CORE_GUID HOB, regis-
ter for notification of the installation of the EFI_MM_ACCESS_PROTOCOL and the
EFI_MM_CONFIGURATION_PROTOCOL . Once both are available, opens MMRAM and:
•CreatestheMMRAMheap,excludinganyareaslistedin EFI_MM_CONFIGURATION_PROTOCOLMm-
ramReservedRegions field.
•Loads the MM Foundation into MMRAM. The MM Foundation produces the MMST.
•Invokesthe EFI_MM_CONFIGURATION_PROTOCOL.RegisterMmEntry() functionwiththe MMFoun-
dation entry point.
•Publishes the EFI_MM_BASE_PROTOCOL in the UEFI Protocol Database
•At this point MM is initially configured and MMIs can be generated.
•Call theCommunicate() member of the EFI_MM_COMMUNICATION_PROTOCOL with a buffer con-
tainingthe EFI_MM_INITIALIAZATION_HEADER andthepointertotheUEFISystemTableinthecom-
munication buffer. This gives the MM Core access to the UEFI Boot Services. Before this point, the MM
IV-1.4. Initializing Management Mode in MM Traditional Mode IV-4UEFI Platform Initialization Specification, Release 1.8
CoremustnotuseanyUEFIservicesorprotocols. NOTE:ItalsoimpliesthattheMMCorecannotfindor
dispatch any MM drivers from firmware volumes, since access to UEFI Boot Services is required to find
instances for the Firmware Volume protocols.
•Register for notification upon installation of the EFI_DXE_MM_READY_TO_LOCK_PROTOCOL in the
UEFI protocol database.
5. During the remainder of the DXE phase, additional drivers may load and be initialized in MMRAM.
6. At some point prior to the processing of boot options, a DXE driver will install the
EFI_DXE_MM_READY_TO_LOCK_PROTOCOL protocol in the UEFI protocol database. (outside of
MM).
7. Asaresult,someDXEdriverwillcausethe EFI_MM_READY_TO_LOCK_PROTOCOL protocoltobeinstalled
in the SM protocol database.
•Optionally, close the MMRAM so that it is no longer visible using the EFI_MM_ACCESS_PROTOCOL .
Closing MMRAM may not be supported on all platforms.
•Optionally, lock the MMRAM so that its configuration can no longer be altered using the
EFI_MM_ACCESS_PROTCOL . Locking MMRAM may not be supported on all platforms.
Fig. 1.2:Example MM Initialization Components
IV-1.4. Initializing Management Mode in MM Traditional Mode IV-5UEFI Platform Initialization Specification, Release 1.8
IV-1.5 Initializing Management Mode in MM StandaloneMode
IV-1.5.1 Initializing MM Standalone Mode in PEI phase
Management Mode initialization prepares the hardware for MMI generation and creates the necessary data structures
for managing the MM resources such as MMRAM. It is initialized with the cooperation of several DXE driver or
PEIMs. Details below:
1. A PEIM produces the EFI_PEI_MM_ACCESS_PPI , which describes the different MMRAM regions available
2. A PEIM produces the EFI_PEI_MM_CONTROL_PPI , which allows synchronous MMIs to be generated.
3. A PEIM (dependent on the EFI_PEI_MM_ACCESS_PPI and, perhaps, the EFI_PEI_MM_CONTROL_PPI ),
does the following:
•Initializes the MM entry vector with the code necessary to meet the entry point requirements described in
Entering & Exiting MM .
•Producesthe EFI_MM_CONFIGURATION_PPI ,whichdescribesthoseareasofMMRAMwhichshould
be excluded from the memory map.
•TheMMIPLPEIM(dependentonthe EFI_PEI_MM_ACCESS_PPI ,EFI_PEI_MM_CONTROL_PPI and
EFI_PEI_MM_CONFIGURATION_PPI ) does the following:
•Opens MMRAM.
•Creates the MMRAM heap, excluding any areas listed in EFI_PEI_MM_CONFIGURATION_PPI Mm-
•Invokes the EFI_PEI_MM_CONFIGURATION_PPI .RegisterMmEntry() function with the MM Founda-
tion entry point.
•Publishes the EFI_PEI_MM_COMMUNICATION_PPI
4. During the remainder of the PEI phase, additional MM standalone drivers may load and be initialized in MM-
RAM.
5. During the remainder of the DXE phase, additional MM standalone drivers may load and be initialized in MM-
RAM.
6. A special MM IPL DXE driver does the following:
•Communicate with MM Foundation and tell EFI_SYSTEM_TABLE pointer.
•Publishes the EFI_MM_COMMUNICATION_PROTOCOL in the UEFI Protocol Database
7. DuringtheremainderoftheDXEphase,additionalMMTraditionaldriversmayloadandbeinitializedinMM-
RAM.
8. At some point prior to the processing of boot options, a DXE driver will install the
MM).
9. Asaresult,someDXEdriverwillcausethe EFI_MM_READY_TO_LOCK_PROTOCOL protocoltobeinstalled
in the MM protocol database.
IV-1.5. Initializing Management Mode in MM StandaloneMode IV-6UEFI Platform Initialization Specification, Release 1.8
Note:InordertosupportbothMMstandalonedriverandMMtraditionaldriver,theMMFoundationmusthavesame
calling convention as DXE phase, instead of PEI phase. It means, if PEI phase is 32bit, DXE phase is 64bit, then the
MM Foundation must be 64bit. The 32bit MM IPL PEIM must have ability to launch 64bit MM Foundation.
IV-1.5.2 Initializing MM Standalone Mode in SEC phase
StandaloneModecanalsobeinitializedinSECphase. WetakeSECphaseinitializationasexampleforMMStandalone
Mode, as described below:
1. SEC does the following:
•Creates the MMRAM heap.
•Invokes the RegisterMmEntry() function with the MM Foundation entry point.

•Optionally, closes MMRAM so that it is no longer visible.
•Optionally, locks MMRAM so that its configuration can no longer be altered.
2. Then SEC Core can load PEI core as normal process.
3. A special MM IPL PEIM does the following:
RAM.
RAM.
7. During the remainder of the DXE phase, additional MM traditional drivers may load and be initialized in MM-
RAM.
MM).
IV-1.5. Initializing Management Mode in MM StandaloneMode IV-7UEFI Platform Initialization Specification, Release 1.8
callingconventionasDXEphase,insteadofSECphase. ThismeansthatiftheSECphaseis32bit,DXEphaseis64bit,
then the MM Foundation must be 64bit. The 32bit SEC must have ability to launch 64bit MM Foundation.
IV-1.6 Entering & Exiting MM
The code at the entry vector must:
•Save any CPU state necessary for supporting the EFI_MM_CPU_PROTOCOL
•Save any CPU state so that the normal operation can be resumed.
•Select a single CPU to enter the MM Foundation.
•Ifanentrypointhasbeenregisteredvia RegisterMmEntry() ,switchtothesameCPUmodeastheMMFounda-
tion and call the MM Foundation entry point.
The MM Foundation entry point must:
•Update the MMST with the CPU information passed to the entry point.
•Call all root MMI controller handlers using MmiManage (NULL)
•Return to the entry vector code.
After returning from the MM Foundation entry point, the code at the entry vector must:
•Restore any CPU state information necessary for normal operation.
•Resume normal operation
IV-1.7 MM Traditional Drivers
There are two types of SM-related drivers: MM Drivers and Combination SM/DXE Drivers. Both types of drivers
are initialized by calling their main entry point. The entry point of the driver is the same as a UEFI Specification
EFI_IMAGE_ENTRY_POINT .
IV-1.7.1 MM Drivers
MM Drivers must have the file type EFI_FV_FILETYPE_MM . MM Drivers are launched once, directly into MM-
RAM in MM Traditional Mode. MM Drivers cannot be launched until the dependency expression in the file section
EFI_SECTION_MM_DEPEX evaluatestotrue. ThisdependencyexpressioncanrefertobothUEFIandSMprotocols.
The entry point of the driver is the same as a UEFI Specification EFI_IMAGE_ENTRY_POINT .
IV-1.6. Entering & Exiting MM IV-8UEFI Platform Initialization Specification, Release 1.8
IV-1.7.2 Combination MM/DXE Drivers
Combination MM/DXE Drivers must have the file type EFI_FV_FILETYPE_COMBINED_MM_DXE . Combination
Drivers are launched twice.
TheyarelaunchedbytheDXEDispatcherasanormalDXEdriveroutsideofMMRAMinMMTradtionalModeafter
the dependency expression in the file section EFI_SECTION_DXE_DEPEX evaluates to true. As DXE Drivers, they
have access to the normal UEFI interfaces.
CombinationDriversarealsolaunchedasMMDriversinsideofMMRAMafterthedependencyexpressioninthefile
sectionEFI_SECTION_MM_DEPEX evaluates to true.
CombinationDrivershaveaccesstoDXE,UEFIandSMservicesduringMMInitialization. CombinationDrivershave
access to MM services during MM Runtime.
Combination Drivers can determine whether or not they are executing during MM Initialization or MM Runtime by
locating the EFI_MM_READY_TO_LOCK_MM_PROTOCOL .
On the first load, the entry point of the driver is the same as a UEFI specification EFI_IMAGE_ENTRY_POINT since
the driver is loaded by the DXE core.
On the second load, the entry point of the driver is the same as a UEFI Specification EFI_IMAGE_ENTRY_POINT .
IV-1.7.3 MM Standalone Drivers
MM Standalone Drivers must have the file type EFI_FV_FILETYPE_MM_STANDALONE . MM Standalone Drivers
arelaunchedonce,directlyintoMMRAM.MMStandaloneDriverscannotbelauncheduntilthedependencyexpression
in the file section EFI_SECTION_MM_DEPEX evaluates to true. This dependency expression must refer to MM
The entry point of the driver is defined below as MM_IMAGE_ENTRY_POINT .
IV-1.7.4 MM_IMAGE_ENTRY_POINT
This function is the main entry point to an MM Standalone Driver.
Prototype
typedef
VOID
(EFIAPI \*MM_IMAGE_ENTRY_POINT) (
IN EFI_HANDLE *ImageHandle* ,
IN EFI_MM_SYSTEM_TABLE *MmSystemTable*
);
The handle allocated for the MMStandalone Driver.
MmSystemTable
A pointer to the MM System Table.
This function is the entry point to an MM Standalone Driver. An MM Standalone Driver is loaded and relocated into
MMRAMby*MMFoundation . Thefirstargumentistheimage’simagehandle. Thesecondargumentisapointerto
the MM system table.
IV-1.7. MM Traditional Drivers IV-9UEFI Platform Initialization Specification, Release 1.8
IV-1.7.5 SOR and Dependency Expressions for SM
TheApriorifilecanalsocontainDXEandSMFFSfiles. Theimplementationdoesn’tsupportSORfortheMMdrivers,
though.
IV-1.8 MM Traditional Driver Initialization
AnMMDriver’s initializationphasebeginswhenthe driverhasbeenloaded intoMMRAMinMMTraditional Mode
and its entry point is called. An MM Driver’s initialization phase ends when the entry point returns.
During MM Driver initialization, MM Drivers have access to two sets of protocols: UEFI and SM. UEFI protocols
are those which are installed and discovered using the UEFI Boot Services. UEFI protocols can be located and used
by MM drivers only during MM Initialization. SM protocols are those which are installed and discovered using the
ManagementModeServicesTable(MMST).SMprotocolscanbediscoveredbyMMdriversduringinitializationtime
and accessed while inside of SM.
MM Drivers shall not use the following UEFI Boot Services during MM Driver Initialization:
Exit()
ExitBootServices()
IV-1.9 MM Standalone Driver Initialization
An MM Standalone Driver’s initialization phase begins when the driver has been loaded into MMRAM in MM Stan-
dalone Mode and its entry point is called. An MM Standalone Driver’s initialization phase ends when the entry point
returns.
During MM Standalone Driver initialization, MM Standalone Drivers can only access MM protocols. MM protocols
arethosewhichareinstalledanddiscoveredusingtheManagementModeServicesTable(MMST).MMprotocolscan
be discovered by MM Drivers during initialization time and accessed while inside of MM.
IV-1.10 MM Traditional Driver Runtime
During MM Driver runtime, MM Drivers only have access to MM protocols. In addition, depending on the platform
architecture,memoryareasoutsideofMMRAMmaynotbeaccessibletoMMDrivers. Likewise,memoryareasinside
of MMRAM may not be accessible to UEFI drivers.
These MM Driver Runtime characteristics lead to several restrictions regarding the usage of UEFI services:
•UEFIinterfacesandserviceswhicharelocatedduringMMDriverInitializationshouldnotbecalledorreferenced
duringMMDriverRuntime. ThisincludestheEFISystemTable,theUEFIBootServicesandtheUEFIRuntime
Services.
•InstalledUEFIprotocolsshouldbeuninstalledbeforeexitingthedriverentrypoint,ortheUEFIprotocolshould
refer to addresses which are not within MMRAM.
•Events created during MM Driver Initialization should be closed before exiting the drier entry point.
IV-1.8. MM Traditional Driver Initialization IV-10UEFI Platform Initialization Specification, Release 1.8
IV-1.11 MM Standalone Driver Runtime
DuringMMStandaloneDriverruntime,MMdriversonlyhaveaccesstoMMprotocols. Inaddition,dependingonthe
platform architecture, memory areas outside of MMRAM may not be accessible to MM Drivers.
IV-1.12 Dispatching MMI Handlers
MMI handlers are registered using the MMST’s MmiHandlerRegister() function. MMI handlers fall into three cate-
gories:
RootMMI Controller Handlers
These are handlers for devices which directly control MMI generation for the CPU(s). The handlers have the
abilitytodetect,clearanddisableoneormoreMMIsources. Theyareregisteredbycalling MmiHandlerRegis-
ter()withHandlerType set to NULL. After an MMI source has been detected, the Root MMI handler calls the
Child MMI Controllers or MMI Handlers whose handler functions were registered using either an MM Child
Dispatchprotocolsorusing MmiHandlerRegister() . Tocallthelatter,itcalls Manage() withaGUIDidentifying
theMMIsourcesothatanyregisteredChildMMIHandlersorLeafMMIHandlerswillbecalled. Ifthehandler
returnsEFI_INTERRUPT_PENDING , it indicates that the interrupt source could not be quiesced. If possible,

gories:
theRootMMIhandlershoulddisableandcleartheMMIsource. Ifthehandlerdoesnotreturnanerror,theRoot
MMI Handler should clear the MMI source.
Child MMI Controller Handlers
These are MMI handlers which handle a single interrupt source from a Root or Child MMI handler and, in
turn,controloneormorechildMMIsourceswhichcanbedetected,clearedanddisabled. Theyareregisteredby
callingthe MmiHandlerRegister() functionwith HandlerType settotheGUIDoftheParentMMIControllerMMI
source. Handlers for this MMI handler’s MMI sources are called in the same manner as Root MMI Handlers.
MMI Handlers
These MMI handlers perform basic software or hardware services based on the MMI source received. If the
MMI handler manages a device outside the control of the Parent MMI Controller, it must make sure that the
device is quiesced, especially if the device drives a level-active input.
IV-1.13 MM Services
IV-1.13.1 MM Driver Model
The MM Driver model has similar constraints to those of UEFI runtime drivers. Specifically, during MM Driver
Runtime, the drivers must not use core protocol services. There will be MMST-based services, which the drivers can
access, but the UEFI System Table and other protocols installed during boot services are not available.
Instead,thefullcollectionofUEFIBootServicesandUEFIRuntimeServicesareavailableonlyduringtheMMDriver
Initialization phase. This visibility is useful so that the MM Driver can leverage the rich set of UEFI services. This
designmakestheUEFIprotocoldatabaseusefultothesedriverswhileoutsideofSMandduringtheirinitialloadwithin
SM.
The MMST-based services that are available include the following:
•A minimal, blocking variant of the device I/O protocol
•A memory allocator from MM memory
•A minimal protocol database for protocols for use inside of SM.
These services are exposed by entries in the Management Mode System Table (MMST) .
IV-1.11. MM Standalone Driver Runtime IV-11UEFI Platform Initialization Specification, Release 1.8
Fig. 1.3:MMI Handler Relationships
IV-1.13.2 MM Protocols
Additional standard protocols are exposed as SM protocols and accessed using the protocol services provided by the
MMST. They may be located during MM Driver Initialization or MM Driver Runtime. MM Driver. For example, the
status code equivalent in MM is simply a UEFI protocol whose interface references an MM-based driver’s service.
Other MM Drivers locate this MM-based status code protocol and can use it during runtime to emit error or progress
IV-1.14 MM UEFI Protocols
This section describes those protocols related to MM that are available through the UEFI boot services (called “UEFI
Protocols”) or through the MMST (called “MM Protocols”).
IV-1.14.1 UEFI Protocols
The system architecture of the MM driver is broken into the following pieces:
•MM Base Protocol
•MM Access Protocol
•MM Control Protocol
TheMMBaseProtocol willbepublishedbytheMMIPLdriverwhichactivatestheMMFoundationforusageduring
the DXE phase.The MM Access Protocol understands the particular enable and locking mechanisms that memory
controller might support while executing in MM.
IV-1.14. MM UEFI Protocols IV-12UEFI Platform Initialization Specification, Release 1.8
TheMM Control Protocol understands how to trigger synchronous MMIs either once or periodically.
IV-1.14.2 MM Protocols
The following figure shows the MM protocols that are published for an IA-32 system.
Fig. 1.4:Published Protocols for IA-32 Systems
IV-1.14. MM UEFI Protocols IV-13CHAPTER
TWO
MM FOUNDATION ENTRY POINT
IV-2.1 EFI_MM_ENTRY_POINT
Summary
This function is the main entry point to the MM Foundation.
Prototype
typedef
VOID
(EFIAPI \*EFI_MM_ENTRY_POINT) (
IN CONST EFI_MM_ENTRY_CONTEXT *\*MmEntryContext*
);
MmEntryContext
Processor information and functionality needed by MM Foundation.
This function is the entry point to the MM Foundation. The processor MM entry code will call this function with the
processor information and functionality necessary for MM.
typedef struct \_EFI_MM_ENTRY_CONTEXT {
EFI_MM_STARTUP_THIS_AP *MmStartupThisAp;*
UINTN *CurrentlyExecutingCpu* ;
UINTN *NumberOfCpus* ;
UINTN *\*CpuSaveStateSize* ;
VOID *\**CpuSaveState;*
} EFI_MM_ENTRY_CONTEXT;
MmStartupThisAp
Initiate a procedure on an application processor while in SM. See the MmStartupThisAp() function description.
CurrentlyExecutingCpu
A number between zero and the NumberOfCpus field. This field designates which processor is executing the
MM Foundation.
NumberOfCpus
The number of current operational processors in the platform. This is a 1 based counter. This does not indicate
the number of processors that entered MM.
IV-14UEFI Platform Initialization Specification, Release 1.8
CpuSaveStateSize
Points to an array, where each element describes the number of bytes in the corresponding save state specified
byCpuSaveState . There are always NumberOfCpus entries in the array.
CpuSaveState
Pointstoanarray,whereeachelementisapointertoaCPUsavestate. Thecorrespondingelementin CpuSaveS-
tateSizespecifies the number of bytes in the save state area. There are always NumberOfCpus entries in the
array.
IV-2.2 MM_FOUNDATION_ENTRY_POINT
Summary
This function is the image entry point of a standalone MM Foundation.
Prototype
typedef
VOID
(EFIAPI \*MM_FOUNDATION_ENTRY_POINT) (
IN CONST VOID \* *HobStart*
);
HobStart
This function is the image entry point of a standalone MM Foundation. Standalone MM IPL passes* HobStart to
standalone MM Foundation. HOB list that describes the system state at the hand-off to the MM Foundation. At a
minimum, this system state must include the following:
•PHIT HOB
•CPU HOB
•Description of MMRAM
MM Foundation can use MMRAM hob to build heap base upon MMRAM hob information. MM Foundation can use
FV hob to dispatch standalone MM driver.
IV-2.2. MM_FOUNDATION_ENTRY_POINT IV-15CHAPTER
THREE
MANAGEMENT MODE SYSTEM TABLE (MMST)
IV-3.1 MMST Introduction
ThissectiondescribestheManagementModeSystemTable(MMST).TheMMSTisasetofcapabilitiesexportedfor
use by all drivers that are loaded into Management Mode RAM (MMRAM).
TheMMSTissimilartotheUEFISystemTable. Itisafixedsetofservicesanddatathataredesignedtoprovidebasic
services for MM Drivers. The MMST is provided by the MM IPL driver, which also manages the following:
•Dispatch of drivers in MM
•Allocations of MMRAM
•Installation/discovery of MM protocols
IV-3.2 EFI_MM_SYSTEM_TABLE
Summary
The Management Mode System Table (MMST) is a table that contains a collection of common services for managing
MMRAMallocationandprovidingbasicI/Oservices. Theseservicesareintendedforbothprebootandruntimeusage.
///
/// Management Mode System Table (MMST)
///
#define MM_MMST_SIGNATURE SIGNATURE_32 ( 'S', 'M', 'S', 'T')
#define EFI_MM_SYSTEM_TABLE_REVISION PI_SPECIFICATION_VERSION
typedef struct _EFI_MM_SYSTEM_TABLE {
CHAR16 *MmFirmwareVendor;
UINT32 MmFirmwareRevision;
EFI_MM_INSTALL_CONFIGURATION_TABLE MmInstallConfigurationTable;
EFI_MM_CPU_IO_PROTOCOL MmIo;
//
// Runtime memory service
IV-16UEFI Platform Initialization Specification, Release 1.8
//
EFI_ALLOCATE_POOL MmAllocatePool;
EFI_FREE_POOL MmFreePool;
EFI_ALLOCATE_PAGES MmAllocatePages;
EFI_FREE_PAGES MmFreePages;
//
// MP service
//
EFI_MM_STARTUP_THIS_AP MmStartupThisAp;
//
// CPU information records
//
UINTN CurrentlyExecutingCpu;
UINTN *CpuSaveStateSize;
VOID **CpuSaveState;
//
// Extensibility table
//
EFI_CONFIGURATION_TABLE *MmConfigurationTable;
//
// Protocol services
//
EFI_INSTALL_PROTOCOL_INTERFACE MmInstallProtocolInterface;
EFI_UNINSTALL_PROTOCOL_INTERFACE MmUninstallProtocolInterface;
EFI_HANDLE_PROTOCOL MmHandleProtocol;
EFI_MM_REGISTER_PROTOCOL_NOTIFY MmRegisterProtocolNotify;
EFI_LOCATE_HANDLE MmLocateHandle;
EFI_LOCATE_PROTOCOL MmLocateProtocol;
//
// MMI management functions
//
EFI_MM_INTERRUPT_MANAGE *MmiManage;*
EFI_MM_INTERRUPT_REGISTER *MmiHandlerRegister;*
EFI_MM_INTERRUPT_UNREGISTER *MmiHandlerUnRegister;*
} EFI_MM_SYSTEM_TABLE;
Hdr
The table header for the Management Mode System Table (MMST). This header contains the
MM_SMST_SIGNATURE, MM_MMST_SIGNATURE andEFI_MM_SYSTEM_TABLE_REVISION values
along with the size of the EFI_MM_SYSTEM_TABLE structure.
Note: In the MM Foundation use of the EFI_TABLE_HEADER for the Management Mode Services Table
(MMST), there is special treatment of the CRC32 field. This value is reserved for MM and should be set to
zero
IV-3.2. EFI_MM_SYSTEM_TABLE IV-17UEFI Platform Initialization Specification, Release 1.8
MmFirmwareVendor
Apointertoa NULL-terminatedUnicodestringcontainingthevendorname. Itispermissibleforthispointerto
beNULL.
MmFirmwareRevision
The particular revision of the firmware.
MmInstallConfigurationTable

//
//
Hdr
zero
beNULL.
Adds, updates, or removes a configuration table entry from the MMST. See the MmInstallConfigurationTable()
MmIo
ProvidesthebasicmemoryandI/Ointerfacesthatareusedtoabstractaccessestodevices. TheI/Oservicesare
provided by the driver which produces the MM CPU I/O Protocol. If that driver has not been loaded yet, this
function pointer will return EFI_UNSUPPORTED .
MmAllocatePool
Allocates MMRAM.
MmFreePool
MmAllocatePages
Allocates pages from MMRAM.
MmFreePages
Returns pages of memory to the system.
InitiateaprocedureonanapplicationprocessorwhileinMM.Seethe MmStartupThisAp() functiondescription.
MmStartupThisAp maynotbeusedduringMMDriverInitialization,andMMandMMDrivermustbeconsidered
“undefined”. This service only defined while an MMI is being processed.
A number between zero and the value in the field NumberOfCpus . This field designates which processor is
executingtheMMinfrastructure. CurrentlyExecutingCpu maynotbeusedduringMMDriverInitialization,and
MM and MM Driver and must be considered “undefined”. This field is only defined while an MMI is being
The number of possible processors in the platform. This is a 1-based counter. NumberOfCpus may not be used
in the entry point of an MM MM Driver and must be considered “undefined”. This field is only defined while
an MMI is being processed.
Pointstoanarray,whereeachelementdescribesthenumberofbytesinthecorrespondingsavestatespecifiedby
CpuSaveState . Therearealways NumberOfCpus entriesinthearray. CpuSaveStateSize maynotbeusedduring
MM Driver Initialization Driver and must be considered “undefined”. This field is only defined while an MMI
is being processed.
tateSizespecifiesthenumberofbytesinthesavestatearea. Therearealways NumberOfCpus entriesinthearray.
CpuSaveState maynotbeusedduringMMDriverInitializationMMDriverandmustbeconsidered“undefined”.
This field is only defined while an MMI is being processed.
NumberOfTableEntries
The number of UEFI Configuration Tables in the buffer MmConfigurationTable .
MmConfigurationTable
Apointertothe UEFIConfigurationTables . Thenumberofentriesinthetableis NumberOfTableEntries . Type
IV-3.2. EFI_MM_SYSTEM_TABLE IV-18UEFI Platform Initialization Specification, Release 1.8
EFI_CONFIGURATION_TABLE is defined in the UEFI Specification .
MmInstallProtocolInterface
InstallsanMMprotocolinterfaceonadevicehandle. Type EFI_INSTALL_PROTOCOL_INTERFACE isdefined
in theUEFI Specification .
MmUninstallProtocolInterface
Removes an MM protocol interface from a device handle. Type EFI_UNINSTALL_PROTOCOL_INTERFACE
is defined in the UEFI Specification .
MmHandleProtocol
Queries a handle to determine if it supports a specified MM protocol. Type EFI_HANDLE_PROTOCOL is
defined in the UEFI Specification .
MmRegisterProtocolNotify
Registers a callback routine that will be called whenever an interface is installed for a specified MM protocol.
MmLocateHandle
Returns an array of handles that support a specified MM protocol. Type EFI_LOCATE_HANDLE is defined in
MmLocateProtocol
Returns the first installed interface for a specific MM protocol. Type EFI_LOCATE_PROTOCOL is defined in
MmiManage
Manage MMI sources of a particular type.
MmiHandlerRegister
Registers an MMI handler for an MMI source.
MmiHandlerUnRegister
Unregisters an MMI handler for an MMI source.
TheCurrentlyExecutingCpu parameter is a value that is less than the NumberOfCpus field. The CpuSaveState is a
pointer toan arrayof CPUsave statesin MMRAM.The CurrentlyExecutingCpu can beused asan indexto locatethe
respective save-state for which the given processor is executing, if so desired.
TheEFI_MM_SYSTEM_TABLE provides support for MMRAM allocation. The functions have the same function
prototypesasthosefoundintheUEFIBootServices,butareonlyeffectiveinallocatingandfreeingMMRAM.Drivers
cannot allocate or free UEFI memory using these services. Drivers cannot allocate or free MMRAM using the UEFI
Boot Services. The functions are:
•MmAllocatePages()
•MmFreePages()
•MmAllocatePool()
•MmFreePool()
TheEFI_MM_SYSTEM_TABLE providessupportforMMprotocols,whichareruntimeprotocolsdesignedtoexecute
exclusivelyinsideofMM.DriverscannotaccessprotocolsinstalledusingtheUEFIBootServicesthroughthisinterface.
Drivers cannot access protocols installed using these interfaces through the UEFI Boot Services interfaces.
Fiveofthestandardprotocol-relatedfunctionsfromtheUEFIbootservicestableareprovidedintheMMSTandperform
inasimilarfashion. Thesefunctionsarerequiredtobeavailableuntilthe EFI_MM_READY_TO_LOCK_PROTOCOL
notification has been installed. The functions are:
•MmInstallProtocolInterface()
•MmUninstallProtocolInterface()
IV-3.2. EFI_MM_SYSTEM_TABLE IV-19UEFI Platform Initialization Specification, Release 1.8
•MmLocateHandle()
•MmHandleProtocol()
•MmLocateProtocol()
NoticeablyabsentareserviceswhichsupporttheUEFIdrivermodel. Thefunction MmRegisterProtocolNotify() ,works
in a similar fashion to the UEFI function except that it does not use an event.
IV-3.2.1 MmInstallConfigurationTable()
Summary
Adds, updates, or removes a configuration table entry from the Management Mode System Table (MMST) .
Prototype
typedef
(EFIAPI \*EFI_MM_INSTALL_CONFIGURATION_TABLE) (
IN CONST *EFI_MM_SYSTEM_TABLE* \* *SystemTable,*
IN CONST EFI_GUID *\*Guid,*
IN VOID *\*Table,*
IN UINTN *TableSize*
)
SystemTable
A pointer to the Management Mode System Table (MMST) .
Guid
A pointer to the GUID for the entry to add, update, or remove.
Table
A pointer to the buffer of the table to add.
TableSize
The size of the table to install.
TheMmInstallConfigurationTable() function is used to maintain the list of configuration tables that are stored in the
MMST. The list is stored as an array of (GUID, Pointer) pairs. The list must be allocated from pool memory with
PoolType set toEfiRuntimeServicesData .
IfGuidis not a valid GUID, EFI_INVALID_PARAMETER is returned. If Guidis valid, there are four possibilities:
•IfGuidisnotpresentintheMMSTand TableisnotNULL,thenthe( Guid,Table)pairisaddedtotheMMST.
SeeNotebelow.
•IfGuidis not present in the MMST and TableisNULL, thenEFI_NOT_FOUND is returned.
•IfGuidis present in the MMST and Tableis notNULL, then the ( Guid,Table) pair is updated with the new
Table value.
•IfGuidis present in the MMST and TableisNULL, then the entry associated with Guidis removed from the
MMST.
IV-3.2. EFI_MM_SYSTEM_TABLE IV-20UEFI Platform Initialization Specification, Release 1.8
Note:If there is not enough memory to perform an add operation, then EFI_OUT_OF_RESOURCES is returned.
Table 3.1: Status Codes Returned
EFI_SUCCESS The Guid Table pair was added updated or removed
EFI_INVALID_PARAMETER Guid is not valid
EFI_NOT_FOUND An attempt was made to delete a nonexistent entry
EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation
IV-3.2.2 MmAllocatePool()
Summary
Allocates pool memory from MMRAM.
Prototype
TypeEFI_ALLOCATE_POOL isdefinedinthe UEFISpecification . Thefunctionisalsodescribedinthatspecification.
TheMmAllocatePool() function allocates a memory region of Sizebytes from memory of type PoolType and returns
the address of the allocated memory in the location referenced by Buffer. This function allocates pages from EfiCon-
ventionalMemory as needed to grow the requested pool type. All allocations are eight-byte aligned.
The allocated pool memory is returned to the available pool with the MmFreePool() function.
All allocations of MMRAM should use EfiRuntimeServicesCode orEfiRuntimeServicesData .
Table 3.2: Status Codes Returned
EFI_INVALID_PARAMETER PoolType was invalid.
IV-3.2.3 MmFreePool()
Summary
Prototype
TypeEFI_FREE_POOL isdefinedinthe UEFISpecification . Thefunctiondescriptionisalsofoundinthatspecifica-
tion.
TheMmFreePool() function returns the memory specified by Bufferto the MMRAM heap. The Bufferthat is freed
must have been allocated by MmAllocatePool().
IV-3.2. EFI_MM_SYSTEM_TABLE IV-21UEFI Platform Initialization Specification, Release 1.8
Table 3.3: Status Codes Returned
EFI_INVALID_PARAMETER Bufferwas invalid.
IV-3.2.4 MmAllocatePages()
Summary
Allocates page memory from MMRAM.
Prototype
TypeEFI_ALLOCATE_PAGES is defined in the UEFI Specification . The function description is also found in that
TheMmAllocatePages() functionallocatestherequestednumberofpagesfromtheMMRAMheapandreturnsapointer

Summary
Prototype
tion.
Summary
Prototype
tothebaseaddressofthepagerangeinthelocationreferencedbyMemory. ThefunctionscanstheMMmemorymap
to locate free pages. When it finds a physically contiguous block of pages that is large enough and also satisfies the
allocation requirements of Type, it changes the memory map to indicate that the pages are now of type MemoryType.
Allocation requests of Type:
•AllocateAnyPages allocate any available range of pages that satisfies the request. On input, the address pointed
to by Memory is ignored.
•AllocateMaxAddress allocate any available range of pages whose uppermost address is less than or equal to the
address pointed to by Memory on input.
•AllocateAddress allocate pages at the address pointed to by Memory on input.
Table 3.4: Status Codes Returned
EFI_SUCCESS The requested pages were allocated
EFI_OUT_OF_RESOURCES The pages could not be allocated
EFI_INVALID_PARAMETER Type is not AllocateAnyPages or AllocateMaxAddress or AllocateAddress
EFI_INVALID_PARAMETER MemoryType is in the range EfiMaxMemoryType 0x7FFFFFFF
EFI_NOT_FOUND The requested pages could not be found
IV-3.2.5 MmFreePages()
Summary
Protocol
TypeEFI_FREE_PAGES isdefinedinthe UEFISpecification . Thefunctiondescriptionisalsofoundinthisspecifica-
tion.
TheMmFreePages() function returns memory allocated by MmAllocatePages () to the MMRAM heap.
IV-3.2. EFI_MM_SYSTEM_TABLE IV-22UEFI Platform Initialization Specification, Release 1.8
Table 3.5: Status Codes Returned
EFI_NOT_FOUND The requested memory pages were not allocated with MmAllocatePages
EFI_NOT_FOUND EFI_INVALID_PARAMETER Memory is not a page aligned address or Pages is invalid
IV-3.2.6 MmStartupThisAp()
Summary
This service lets the caller get one distinct application processor (AP) to execute a caller-provided code stream while
in MM.
Prototype
typedef
(EFIAPI \*EFI_MM_STARTUP_THIS_AP) (
IN *EFI_AP_PROCEDURE* *Procedure*
IN UINTN *CpuNumber,*
IN OUT VOID *\*ProcArguments* OPTIONAL
);
Procedure
A pointer to the code stream to be run on the designated AP of the system. Type EFI_AP_PROCEDURE is
CpuNumber
The zero-based index of the processor number of the AP on which the code stream is supposed to run. If the
processor number points to the current processor, then it will not run the supplied code.
ProcArguments
AllowsthecallertopassalistofparameterstothecodethatisrunbytheAP.Itisanoptionalcommonmailbox
between APs and the caller to share information.
See PI Spec Volume 2, EFI_MP_SERVICES_PROTOCOL.StartupAllAPs , Related Definitions.
Thisfunctionisusedtodispatchonespecific,healthy,enabled,andnon-busyAPoutoftheprocessorpooltothecode
streamthatisprovidedbythecallerwhileinMM.TherecoveryofafailedAPisoptionalandtherecoverymechanism
is implementation dependent.
EFI_SUCCESS The call was successful and the return parameters are valid
EFI_INVALID_PARAMETER The input arguments are out of range
EFI_INVALID_PARAMETER The CPU requested is not available on this MMI invocation
EFI_INVALID_PARAMETER The CPU cannot support an additional service invocation
IV-3.2. EFI_MM_SYSTEM_TABLE IV-23UEFI Platform Initialization Specification, Release 1.8
IV-3.2.7 MmInstallProtocolInterface()
Summary
Installs a MM protocol interface on a device handle. If the handle does not exist, it is created and added to the list of
handles in the system.
Prototype
TypeEFI_INSTALL_PROTOCOL_INTERFACE isdefinedinthe UEFISpecification . Thefunctiondescriptionisalso
found in this specification.
TheMmInstallProtocolInterface() function installs a protocol interface (a GUID/Protocol Interface structure pair) on
an MM device handle. The same GUID cannot be installed more than once onto the same handle. If installation of a
duplicate GUID on a handle is attempted, an EFI_INVALID_PARAMETER will result. Installing a protocol interface
allows other MM MM Drivers to locate the Handle, and the interfaces installed on it.
When a protocol interface is installed, the firmware calls all notification functions that have registered to wait for the
installation of Protocol. For more information, see the MmRegisterProtocolNotify() function description.
EFI_SUCCESS The protocol interface was installed
EFI_OUT_OF_RESOURCES Space for a new handle could not be allocated
EFI_INVALID_PARAMETER Handle is NULL
EFI_INVALID_PARAMETER Protocol is NULL
EFI_INVALID_PARAMETER InterfaceType is not EFI_NATIVE_INTERFACE
EFI_INVALID_PARAMETER Protocol is already installed on the handle specified by Handle
IV-3.2.8 MmUninstallProtocolInterface()
Summary
Removes a MM protocol interface from a device handle.
Prototype
TypeEFI_UNINSTALL_PROTOCOL_INTERFACE is defined in the UEFI Specification . The function description is
also found in that specification.
TheMmUninstallProtocolInterface() functionremovesaprotocolinterfacefromthehandleonwhichitwaspreviously
installed. The Protocol andInterface values define the protocol interface to remove from the handle. The caller is
responsible for ensuring that there are no references to a protocol interface that has been removed. If the last protocol
interface is removed from a handle, the handle is freed and is no longer valid.
EFI_SUCCESS The interface was removed
EFI_NOT_FOUND The interface was not found
EFI_ACCESS_DENIED Theinterfacewasnotremovedbecausetheinterfaceisstillbeingusedbyadriver
EFI_INVALID_PARAMETER Handle i s not a valid EFI_HANDLE
IV-3.2. EFI_MM_SYSTEM_TABLE IV-24UEFI Platform Initialization Specification, Release 1.8
IV-3.2.9 MmHandleProtocol()
Summary
Queries a handle to determine if it supports a specified MM protocol.
Prototype
TypeEFI_HANDLE_PROTOCOL is defined in the UEFI Specification . The function description is also found in that
TheMmHandleProtocol() function queries Handleto determine if it supports Protocol . If it does, then, on return,
Interface points to a pointer to the corresponding Protocol Interface.
Interface can then be passed to any protocol service to identify the context of the request.
EFI_SUCCESS The interface information for the specified protocol was returned
EFI_UNSUPPORTED The device does not support the specified protocol
EFI_INVALID_PARAMETER Handle is not a valid EFI_HANDLE
EFI_INVALID_PARAMETER Interface is NULL
IV-3.2.10 MmRegisterProtocolNotify()
Summary
Register a callback function be called when a particular protocol interface is installed.
Prototype
typedef
(EFIAPI \*EFI_MM_REGISTER_PROTOCOL_NOTIFY)(
IN CONST EFI_GUID \*Protocol,
IN EFI_MM_NOTIFY_FN Function,
IN OUT VOID \**Registration
);
Protocol
The unique ID of the protocol for which the event is to be registered. Type EFI_GUID is defined in the Install-
ProtocolInterface() function description.
Function
Points to the notification function, which is described below.
Registration
A pointer to a memory location to receive the registration value. This value must be saved and used by the
notification function to retrieve the list of handles that have added a protocol interface of type Protocol.
IV-3.2. EFI_MM_SYSTEM_TABLE IV-25UEFI Platform Initialization Specification, Release 1.8
TheMmRegisterProtocolNotify() functioncreatesaregistration Function thatistobecalledwheneveraprotocolinter-
faceisinstalledfor ProtocolbyMmInstallProtocolInterface() . WhenFunctionhasbeencalled,the MmLocateHandle()
functioncanbecalledtoidentifythenewlyinstalledhandlesthatsupport Protocol. TheRegistration parameterin Mm-
RegisterProtocolNotify() corresponds to the SearchKey parameter in MmLocateHandle() . Note that the same handle
maybereturnedmultipletimesifthehandlereinstallsthetargetprotocolIDmultipletimes. If Function ==NULLand
Registration isanexistingregistration,thenthecallbackisunhooked. *Protocol mustbevalidateditwith *Registration
. IfRegistration is not found then EFI_NOT_FOUND is returned.
typedef
(EFIAPI \*EFI_MM_NOTIFY_FN)(
IN CONST EFI_GUID *\*Protocol* ,
IN VOID *\*Interface,*
IN EFI_HANDLE *Handle*
);
Protocol
Points to the protocol’s unique identifier.
Interface
Points to the interface instance.
Handle
The handle on which the interface was installed.
EFI_SUCCESS Successfully returned the registration record that has been added or unhooked
EFI_INVALID_PARAMETER Protocol is NULL or Registration is NULL
EFI_OUT_OF_RESOURCES Not enough memory resource to finish the request
EFI_NOT_FOUND If the registration is not found when Function NULL

typedef
);
Protocol
Interface
Handle
IV-3.2.11 MmLocateHandle()
Summary
Returns an array of handles that support a specified protocol.
Prototype
TypeEFI_LOCATE_HANDLE is defined in the UEFI Specification . The function description is also found in this
TheMmLocateHandle() function returns an array of handles that match the SearchType request. If the input value
ofBufferSize is too small, the function returns EFI_BUFFER_TOO_SMALL and updates BufferSize to the size of the
IV-3.2. EFI_MM_SYSTEM_TABLE IV-26UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The array of handles was returned
EFI_NOT_FOUND No handles match the search
EFI_BUFFER_TOO_SMALL The BufferSize is too small for the result BufferSize has been updated with the size
needed to complete the request
EFI_INVALID_PARAMETER SearchType is not a member of EFI_LOCATE_SEARCH_TYPE
EFI_INVALID_PARAMETER SearchType is ByRegisterNotify and SearchKey is NULL
EFI_INVALID_PARAMETER SearchType is ByProtocol and Protoco l is NULL
EFI_INVALID_PARAMETER One or more matches are found and BufferSiz e is NULL
EFI_INVALID_PARAMETER BufferSize is large enough for the result and Buffer is NULL
IV-3.2.12 MmLocateProtocol()
Summary
Returns the first MM protocol instance that matches the given protocol.
Prototype
TypeEFI_LOCATE_PROTOCOL isdefinedinthe UEFISpecification . Thefunctiondescriptionisfoundinthatspec-
TheMmLocateProtocol() function finds the first device handle that support Protocol, and returns a pointer to the pro-
tocol interface from that handle in Interface. If no protocol instances are found, then Interface is set toNULL.
IfInterface isNULL, thenEFI_INVALID_PARAMETER is returned.
IfRegistration isNULL,andtherearenohandlesinthehandledatabasethatsupport Protocol,thenEFI_NOT_FOUND
IfRegistration is notNULL, and there are no new handles for Registration, then EFI_NOT_FOUND is returned.
EFI_SUCCESS A protocol instance matching Protocol was found and returned in Interface
EFI_NOT_FOUND No protocol instances were found that match Protocol and Registration
IV-3.2.13 MmiManage()
Summary
Manage MMI of a particular type.
Prototype
typedef
(EFIAPI \*EFI_MM_INTERRUPT_MANAGE)(
IN CONST EFI_GUID \* *HandlerType* ,
IN CONST VOID \* *Context* OPTIONAL,
IN OUT VOID \* *CommBuffer* OPTIONAL,
IV-3.2. EFI_MM_SYSTEM_TABLE IV-27UEFI Platform Initialization Specification, Release 1.8
IN OUT UINTN \* *CommBufferSize* OPTIONAL
);
HandlerType
Points to the handler type or NULL for root MMI handlers.
Context
Points to an optional context buffer. The format of the contents of the context buffer depends on HandlerType .
CommBuffer
Points to the optional communication buffer. The format of the contents of the communication buffer depends
onHandlerType . The contents of the buffer (and its size) may be altered if EFI_SUCCESS is returned.
CommBufferSize
Points to the sizeof the optional communication buffer. The size ofthe buffer may be altered if EFI_SUCCESS
This function will call the registered handler functions which match the specified invocation type.
If NULL is passed in HandlerType , then only those registered handler functions which passed NULL as their Han-
dlerTypewillbecalled. IfNULLispassedin HandlerType ,thenContextshouldbeNULL, CommBuffer shouldpoint
to an instance of EFI_MM_ENTRY_CONTEXT andCommBufferSize should point to the size of that structure. Type
EFI_MM_ENTRY_CONTEXT is defined in “Related Definitions” below.
If at least one of the handlers returns EFI_WARN_INTERRUPT_SOURCE_QUIESCED orEFI_SUCCESS then the
functionwillreturn EFI_SUCCESS .Ifahandlerreturns EFI_SUCCESS andHandlerType isnotNULLthennoaddi-
tional handlers will be processed.
If a handler returns EFI_INTERRUPT_PENDING andHandlerType is not NULL then no additional han-
dlers will be processed and EFI_INTERRUPT_PENDING will be returned. If all the handlers returned
EFI_WARN_INTERRUPT_SOURCE_PENDING thenEFI_WARN_INTERRUPT_SOURCE_PENDING will be re-
turned.
If no handlers of HandlerType are found then EFI_NOT_FOUND will be returned.
Table 3.13: Status Codes Returned
EFI_WARN_INTERRUPT_SOURCE_PENDING TheMMIwasprocessedsuccessfullybuttheMMIsourcenotqui-
esced
EFI_INTERRUPT_PENDING One or more MMI sources could not be quiesced
EFI_NOT_FOUND TheMMIwasnothandledandtheMMIsourcewasnotquiesced
EFI_SUCCESS The MMI was handled and the MMI source was quiesced
IV-3.2. EFI_MM_SYSTEM_TABLE IV-28UEFI Platform Initialization Specification, Release 1.8
IV-3.2.14 MmiHandlerRegister()
Summary
Registers a handler to execute within MM.
Prototype
typedef
(EFIAPI \*EFI_MM_INTERRUPT_REGISTER) (
IN EFI_MM_HANDLER_ENTRY_POINT *Handler* ,
IN CONST EFI_GUID *\*HandlerType* OPTIONAL,
OUT EFI_HANDLE \* *DispatchHandle*
);
Handler
Handler service function pointer. Type EFI_MM_HANDLER_ENTRY_POINT is defined in “Related Defini-
Pointstoan EFI_GUID whichdescribesthetypeofinvocationthatthishandlerisforor NULLtoindicatearoot
MMI handler.
DispatchHandle
On return, contains a unique handle which can be used to later unregister the handler function. It is also passed
to the handler function itself.
This service allows the registration of a MMI handling function from within MM. The handler should have the
EFI_MM_HANDLER_ENTRY_POINT interface defined in “Related Definitions” below.
//**********************************************\*
// EFI_MM_HANDLER_ENTRY_POINT
typedef
(EFIAPI \*EFI_MM_HANDLER_ENTRY_POINT) (
IN EFI_HANDLE *DispatchHandle* ,
);
Theuniquehandleassignedtothishandlerby MmiHandlerRegister() .TypeEFI_HANDLE isdefinedin Install-
ProtocolInterface() in the UEFI Specification.
Context
Points to the optional handler context which was specified when the handler was registered.
IV-3.2. EFI_MM_SYSTEM_TABLE IV-29UEFI Platform Initialization Specification, Release 1.8
A pointer to a collection of data in memory that will be conveyed from a non-MM environment into an MM
environment. The buffer must be contiguous, physically mapped, and be a physical address.
The size of the CommBuffer .MmiHandlerRegister() returns one of two status codes:
Status Codes Returned (MmiHandlerRegister)
EFI_SUCCESS MMI handler added successfully.
EFI_INVALID_PARAMETER Handler is NULLorDispatchHandle isNULL
EFI_MM_HANDLER_ENTRY_POINT returns one of four status codes:
Status Codes Returned (EFI_MM_HANDLER_ENTRY_POINT)
EFI_SUCCESS The MMI was handled and the MMI source the MMI source was quiesced.
No other handlers should still be called.
EFI_WARN_INTERRUPT_SOURCE_QUIESCED The MMI source has been quiesced but other handlers should still be called.
EFI_WARN_INTERRUPT_SOURCE_PENDING The MMI source is still pending and other handlers should still be called.
EFI_INTERRUPT_PENDING The MMI source could not be quiesced.
IV-3.2.15 MmiHandlerUnRegister()
Summary
Unregister a handler in MM.
Prototype
typedef
(EFIAPI \*EFI_MM_INTERRUPT_UNREGISTER)(
);
The handle that was specified when the handler was registered.
This function unregisters the specified handler function.
EFI_SUCCESS Handler function was successfully unregistered
EFI_INVALID_PARAMETER DispatchHandle does not refer to a valid handle
IV-3.2. EFI_MM_SYSTEM_TABLE IV-30CHAPTER
FOUR
MM PROTOCOLS
IV-4.1 Introduction
There is a share-nothing model that is employed between the management-mode application and the boot ser-
vice/runtime UEFI environment. As such, a minimum set of services needs to be available to the boot service agent.
The services described in this section coexist with a foreground pre-boot or runtime environment. The latter can in-
cludebothUEFIandnon-UEFIawareoperatingsystems. Assuch,theimplementationoftheseservicesmustsaveand
restoreany“shared”resourceswiththeforegroundenvironmentoronlyuseresourcesthatareprivatetotheMMcode.
IV-4.2 Status Codes Services
IV-4.2.1 EFI_MM_STATUS_CODE_PROTOCOL
Summary
Provides status code services from MM.
GUID
#define EFI_MM_STATUS_CODE_PROTOCOL_GUID \
{ 0x6afd2b77, 0x98c1, 0x4acd, 0xa6, 0xf9, 0x8a, 0x94, \
0x39, 0xde, 0xf, 0xb1 }
typedef struct \_EFI_MM_STATUS_CODE_PROTOCOL {
EFI_MM_REPORT_STATUS_CODE ReportStatusCode;
} EFI_MM_STATUS_CODE_PROTOCOL;
Allows for the MM agent to produce a status code output. See the ReportStatusCode() function description.

Summary
GUID
TheEFI_MM_STATUS_CODE_PROTOCOL provides the basic status code services while in MMRAM.
IV-31UEFI Platform Initialization Specification, Release 1.8
IV-4.2.2 EFI_MM_STATUS_CODE_PROTOCOL.ReportStatusCode()
Summary
Service to emit the status code in MM.
Prototype
typedef
(EFIAPI \*EFI_MM_REPORT_STATUS_CODE) (
IN CONST EFI_MM_STATUS_CODE_PROTOCOL *This,
IN EFI_STATUS_CODE_DATA *Data OPTIONAL
);
This
Points to this instance of the EFI_MM_STATUS_CODE_PROTOCOL .
CodeType
Indicates the type of status code being reported. Type EFI_STATUS_CODE_TYPE is defined in “Related Defi-
Value
Describes the current status of a hardware or software entity. This status includes information about the class
and subclass that is used to classify the entity, as well as an operation. For progress codes, the operation is
the current activity. For error codes, it is the exception. For debug codes, it is not defined at this time. Type
Instance
CallerId
Data
This optional parameter may be used to pass additional data. Type EFI_STATUS_CODE_DATA is defined in
“Related Definitions” below. The contents of this data type may have additional GUID-specific data.
TheEFI_MM_STATUS_CODE_PROTOCOL.ReportStatusCode()functionenablesadrivertoemitastatuscodewhile
inMM.ThereasonthatthereisaseparateprotocoldefinitionfromtheDXEvariantofthisserviceisthatthepublisher
of this protocol will provide a service that is capability of coexisting with a foreground operational environment, such
as an operating system after the termination of boot services.
platform-wide view and may not be able to accurately assess the impact of the error condition. The MM MM Driver
that produces the Status Code MM Protocol is responsible for assessing the true severity level based on the reported
severity and other information. This MM MM Driver may perform platform specific actions based on the type and
severity of the status code being reported.
IV-4.2. Status Codes Services IV-32UEFI Platform Initialization Specification, Release 1.8
IfDatais present, the driver treats it as read only data. The driver must copy Datato a local buffer in an atomic
operationbeforeperforminganyotheractions. Thisisnecessarytomakethisfunctionre-entrant. Thesizeofthelocal
buffermaybelimited. Asaresult,someofthe Datacanbelost. Thesizeofthelocalbuffershouldatleastbe256bytes
in size. Larger buffers will reduce the probability of losing part of the Data. If all of the local buffers are consumed,
thenthisservicemaynotbeabletoperformtheplatformspecificactionrequiredbythestatuscodebeingreported. As
a result, if all the local buffers are consumed, the behavior of this service is undefined.
If theCallerIdparameter is not NULL, then it is required to point to a constant GUID. In other words, the caller may
not reuse or release the buffer pointed to by CallerId.
EFI_DEVICE_ERROR The function should not be completed due to a device error
IV-4.3 CPU Save State Access Services
IV-4.3.1 EFI_MM_CPU_PROTOCOL
Summary
Provides access to CPU-related information while in MM.
GUID
#define EFI_MM_CPU_PROTOCOL_GUID \
{ 0xeb346b97, 0x975f, 0x4a9f, \
0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 }
Prototype
typedef struct \_EFI_MM_CPU_PROTOCOL {
EFI_MM_READ_SAVE_STATE ReadSaveState;
EFI_MM_WRITE_SAVE_STATE WriteSaveState;
} EFI_MM_CPU_PROTOCOL;
Members
ReadSaveState
Read information from the CPU save state. See ReadSaveState() for more information.
WriteSaveState
Write information to the CPU save state. See WriteSaveState() for more information.
This protocol allows MM Drivers to access architecture-standard registers from any of the CPU save state areas. In
some cases, difference processors provide the same information in the save state, but not in the same format. These
so-called pseudo-registers provide this information in a standard format.
IV-4.3. CPU Save State Access Services IV-33UEFI Platform Initialization Specification, Release 1.8
IV-4.3.2 EFI_MM_CPU_PROTOCOL.ReadSaveState()
Summary
Read data from the CPU save state.
Prototype
typedef
(EFIAPI *EFI_MM_READ_SAVE_STATE (
IN CONST EFI_MM_CPU_PROTOCOL *This,
IN UINTN CpuIndex,
);
Width
The number of bytes to read from the CPU save state. If the register specified by Registerdoes not support the
size specified by Width, thenEFI_INVALID_PARAMETER is returned.
Register
Specifies the CPU register to read formthe save state. The type EFI_MM_SAVE_STATE_REGISTER is defined
in “Related Definitions” below. If the specified register is not implemented in the CPU save state map then
EFI_NOT_FOUND error will be returned.
CpuIndex
Specifies the zero-based index of the CPU save state
*Buffer
Upon return, this holds the CPU register value read from the save state.
This function is used to read the specified number of bytes of the specified register from the CPU save state of the
specified CPU and place the value into the buffer. If the CPU does not support the specified register Register,
thenEFI_NOT_FOUND should be returned. If the CPU does not support the specified register width Width, then
//
// x86/X64 standard registers
//
EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4,
EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5,
EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6,
EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7,
EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8,
EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9,
EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10,
EFI_MM_SAVE_STATE_REGISTER_ES = 20,
EFI_MM_SAVE_STATE_REGISTER_CS = 21,
EFI_MM_SAVE_STATE_REGISTER_SS = 22,
EFI_MM_SAVE_STATE_REGISTER_DS = 23,
IV-4.3. CPU Save State Access Services IV-34UEFI Platform Initialization Specification, Release 1.8
EFI_MM_SAVE_STATE_REGISTER_FS = 24,
EFI_MM_SAVE_STATE_REGISTER_GS = 25,
EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26,
EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27,
EFI_MM_SAVE_STATE_REGISTER_DR7 = 28,
EFI_MM_SAVE_STATE_REGISTER_DR6 = 29,
EFI_MM_SAVE_STATE_REGISTER_R8 = 30,
EFI_MM_SAVE_STATE_REGISTER_R9 = 31,
EFI_MM_SAVE_STATE_REGISTER_R10 = 32,
EFI_MM_SAVE_STATE_REGISTER_R11 = 33,
EFI_MM_SAVE_STATE_REGISTER_R12 = 34,
EFI_MM_SAVE_STATE_REGISTER_R13 = 35,
EFI_MM_SAVE_STATE_REGISTER_R14 = 36,
EFI_MM_SAVE_STATE_REGISTER_R15 = 37,
EFI_MM_SAVE_STATE_REGISTER_RAX = 38,
EFI_MM_SAVE_STATE_REGISTER_RBX = 39,
EFI_MM_SAVE_STATE_REGISTER_RCX = 40,
EFI_MM_SAVE_STATE_REGISTER_RDX = 41,
EFI_MM_SAVE_STATE_REGISTER_RSP = 42,
EFI_MM_SAVE_STATE_REGISTER_RBP = 43,
EFI_MM_SAVE_STATE_REGISTER_RSI = 44,
EFI_MM_SAVE_STATE_REGISTER_RDI = 45,
EFI_MM_SAVE_STATE_REGISTER_RIP = 46,
EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51,
EFI_MM_SAVE_STATE_REGISTER_CR0 = 52,
EFI_MM_SAVE_STATE_REGISTER_CR3 = 53,
EFI_MM_SAVE_STATE_REGISTER_CR4 = 54,
EFI_MM_SAVE_STATE_REGISTER_FCW = 256,
EFI_MM_SAVE_STATE_REGISTER_FSW = 257,
EFI_MM_SAVE_STATE_REGISTER_FTW = 258,
EFI_MM_SAVE_STATE_REGISTER_OPCODE = 259,
EFI_MM_SAVE_STATE_REGISTER_FP_EIP = 260,
EFI_MM_SAVE_STATE_REGISTER_FP_CS = 261,
EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET = 262,
EFI_MM_SAVE_STATE_REGISTER_FP_DS = 263,
EFI_MM_SAVE_STATE_REGISTER_MM0 = 264,
EFI_MM_SAVE_STATE_REGISTER_MM1 = 265,
EFI_MM_SAVE_STATE_REGISTER_MM2 = 266,
EFI_MM_SAVE_STATE_REGISTER_MM3 = 267,
EFI_MM_SAVE_STATE_REGISTER_MM4 = 268,
EFI_MM_SAVE_STATE_REGISTER_MM5 = 269,
EFI_MM_SAVE_STATE_REGISTER_MM6 = 270,
EFI_MM_SAVE_STATE_REGISTER_MM7 = 271,
EFI_MM_SAVE_STATE_REGISTER_XMM0 = 272,
EFI_MM_SAVE_STATE_REGISTER_XMM1 = 273,
EFI_MM_SAVE_STATE_REGISTER_XMM2 = 274,
EFI_MM_SAVE_STATE_REGISTER_XMM3 = 275,
EFI_MM_SAVE_STATE_REGISTER_XMM4 = 276,
EFI_MM_SAVE_STATE_REGISTER_XMM5 = 277,
EFI_MM_SAVE_STATE_REGISTER_XMM6 = 278,
EFI_MM_SAVE_STATE_REGISTER_XMM7 = 279,
EFI_MM_SAVE_STATE_REGISTER_XMM8 = 280,
IV-4.3. CPU Save State Access Services IV-35UEFI Platform Initialization Specification, Release 1.8
EFI_MM_SAVE_STATE_REGISTER_XMM9 = 281,
EFI_MM_SAVE_STATE_REGISTER_XMM10 = 282,
EFI_MM_SAVE_STATE_REGISTER_XMM11 = 283,
EFI_MM_SAVE_STATE_REGISTER_XMM12 = 284,
EFI_MM_SAVE_STATE_REGISTER_XMM13 = 285,

EFI_MM_SAVE_STATE_REGISTER_XMM14 = 286,
EFI_MM_SAVE_STATE_REGISTER_XMM15 = 287,
//
// Pseudo-Registers
//
EFI_MM_SAVE_STATE_REGISTER_IO = 512,
EFI_MM_SAVE_STATE_REGISTER_LMA = 513,
EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID = 514,
//
// ARM Registers. X0 corresponds to R0
//
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X0 = 1024,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X1 = 1025,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X2 = 1026,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X3 = 1027,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X4 = 1028,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X5 = 1029,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X6 = 1030,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X7 = 1031,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X8 = 1032,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X9 = 1033,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X10 = 1034,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X11 = 1035,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X12 = 1036,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X13 = 1037,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X14 = 1038,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X15 = 1039,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X16 = 1040,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X17 = 1041,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X18 = 1042,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X19 = 1043,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X20 = 1044,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X21 = 1045,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X22 = 1046,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X23 = 1047,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X24 = 1048,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X25 = 1049,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X26 = 1050,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X27 = 1051,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X28 = 1052,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X29 = 1053,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X30 = 1054,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_X31 = 1055,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_FP = 1053, // x29 -
IV-4.3. CPU Save State Access Services IV-36UEFI Platform Initialization Specification, Release 1.8
Frame Pointer
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_LR = 1054, // x30 - Link
Register
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SP = 1055, // x31 -
Stack Pointer
// AArch64 EL1 Context System Registers
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_ELR_EL1 = 1300,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_ESR_EL1 = 1301,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_FAR_EL1 = 1302,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_ISR_EL1 = 1303,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_MAIR_EL1 = 1304,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_MIDR_EL1 = 1305,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_MPIDR_EL1 = 1306,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SCTLR_EL1 = 1307,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SP_EL0 = 1308,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SP_EL1 = 1309,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SPSR_EL1 = 1310,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TCR_EL1 = 1311,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TPIDR_EL0 = 1312,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TPIDR_EL1 = 1313,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TPIDRRO_EL0 = 1314,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TTBR0_EL1 = 1315,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TTBR1_EL1 = 1316,
// AArch64 EL2 Context System Registers
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_ELR_EL2 = 1320,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_ESR_EL2 = 1321,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_FAR_EL2 = 1322,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_HACR_EL2 = 1333,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_HCR_EL2 = 1334,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_HPFAR_EL2 = 1335,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_MAIR_EL2 = 1336,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SCTLR_EL2 = 1337,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SP_EL2 = 1338,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SPSR_EL2 = 1339,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TCR_EL2 = 1340,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TPIDR_EL2 = 1341,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TTBR0_EL2 = 1342,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_VTCR_EL2 = 1343,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_VTTBR_EL2 = 1344,
// AArch64 EL3 Context System Registers
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_ELR_EL3 = 1350,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_ESR_EL3 = 1351,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_FAR_EL3 = 1352,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_MAIR_EL3 = 1353,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SCTLR_EL3 = 1354,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SP_EL3 = 1355,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_SPSR_EL3 = 1356,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TCR_EL3 = 1357,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TPIDR_EL3 = 1358,
IV-4.3. CPU Save State Access Services IV-37UEFI Platform Initialization Specification, Release 1.8
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_TTBR0_EL3 = 1359,
// 32-bit aliases forRx->Xx
EFI_SMM_SAVE_STATE_REGISTER_ARM_R0 = 1024,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R1 = 1025,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R2 = 1026,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R3 = 1027,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R4 = 1028,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R5 = 1029,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R6 = 1030,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R7 = 1031,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R8 = 1032,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R9 = 1033,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R10 = 1034,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R11 = 1035,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R12 = 1036,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R13 = 1037,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R14 = 1038,
EFI_SMM_SAVE_STATE_REGISTER_ARM_R15 = 1039,
// Unique AArch32 Registers
EFI_SMM_SAVE_STATE_REGISTER_ARM_SP = 1037, // alias forR13
EFI_SMM_SAVE_STATE_REGISTER_ARM_LR = 1038, // alias forR14
EFI_SMM_SAVE_STATE_REGISTER_ARM_PC = 1040, // alias forR15
// AArch32 EL1 Context System Registers
EFI_SMM_SAVE_STATE_REGISTER_ARM_DFAR = 1222,
EFI_SMM_SAVE_STATE_REGISTER_ARM_DFSR = 1223,
EFI_SMM_SAVE_STATE_REGISTER_ARM_IFAR = 1224,
EFI_SMM_SAVE_STATE_REGISTER_ARM_ISR = 1225,
EFI_SMM_SAVE_STATE_REGISTER_ARM_MAIR0 = 1226,
EFI_SMM_SAVE_STATE_REGISTER_ARM_MAIR1 = 1227,
EFI_SMM_SAVE_STATE_REGISTER_ARM_MIDR = 1228,
EFI_SMM_SAVE_STATE_REGISTER_ARM_MPIDR = 1229,
EFI_SMM_SAVE_STATE_REGISTER_ARM_NMRR = 1230,
EFI_SMM_SAVE_STATE_REGISTER_ARM_PRRR = 1231,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SCTLR_NS = 1231,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SPSR = 1232,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SPSR_abt = 1233,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SPSR_fiq = 1234,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SPSR_irq = 1235,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SPSR_svc = 1236,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SPSR_und = 1237,
EFI_SMM_SAVE_STATE_REGISTER_ARM_TPIDRPRW = 1238,
EFI_SMM_SAVE_STATE_REGISTER_ARM_TPIDRURO = 1239,
EFI_SMM_SAVE_STATE_REGISTER_ARM_TPIDRURW = 1240,
EFI_SMM_SAVE_STATE_REGISTER_ARM_TTBCR = 1241,
EFI_SMM_SAVE_STATE_REGISTER_ARM_TTBR0 = 1242,
EFI_SMM_SAVE_STATE_REGISTER_ARM_TTBR1 = 1243,
EFI_SMM_SAVE_STATE_REGISTER_ARM_DACR = 1244,
IV-4.3. CPU Save State Access Services IV-38UEFI Platform Initialization Specification, Release 1.8
EFI_SMM_SAVE_STATE_REGISTER_ARM_ELR_hyp = 1245,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HAMAIR0 = 1246,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HAMAIR1 = 1247,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HCR = 1248,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HCR2 = 1249,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HDFAR = 1250,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HIFAR = 1251,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HPFAR = 1252,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HSR = 1253,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HTCR = 1254,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HTPIDR = 1255,
EFI_SMM_SAVE_STATE_REGISTER_ARM_HTTBR = 1256,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SPSR_hyp = 1257,
EFI_SMM_SAVE_STATE_REGISTER_ARM_VTCR = 1258,
EFI_SMM_SAVE_STATE_REGISTER_ARM_VTTBR = 1259,
EFI_SMM_SAVE_STATE_REGISTER_ARM_DACR32_EL2 = 1260,
// AArch32 EL2 Secure Context System Registers
EFI_SMM_SAVE_STATE_REGISTER_ARM_SCTLR_S = 1261,
EFI_SMM_SAVE_STATE_REGISTER_ARM_SPSR_mon = 1262,
// Context System Registers: 32768 - 65535
EFI_SMM_SAVE_STATE_REGISTER_ARM_CSR = 32768,
EFI_SMM_SAVE_STATE_REGISTER_AARCH64_CSR = 32768
} EFI_SMM_SAVE_STATE_REGISTER;
} EFI_MM_SAVE_STATE_REGISTER;
IV-4.3.3 AARCH32/AARCH64 REGISTER AVAILABILITY
Dependingontheplatformpolicy,notallregistersmaybeavailableintheMMSaveState. Theseregisterswillreturn
thestatuscode EFI_NOT_FOUND whencalling ReadSaveState() orWriteSaveState() . Insomecasesthismaybedone
to protect sensitive information in the non-secure execution environment.
IV-4.3.4 EFI_MM_SAVE_STATE_ARM_CSR,EFI_MM_SAVE_STATE_AARCH64_CSR
The Read/Write interface can be used to retrieve AARCH32/AARCH64 Context System Registers that were saved
upon entry to MM. These registers have the CPU Register Index starting with EFI_MM_SAVE_STATE_ARM_CSR .
TheactualCPUregisterindexforaspecificCSRregisteriscalculatedbyaddingtheencodingoftheMRSinstruction,
bits 5:19, to EFI_MM_SAVE_STATE_REGISTER_ARM_CSR .
That is: (MRSIntruction[5:19] << 5 + EFI_MM_SAVE_STATE_ARM_CSR ). See the UEFI Specification , Table 275
in Appendix N for more information.
IV-4.3. CPU Save State Access Services IV-39UEFI Platform Initialization Specification, Release 1.8

IV-4.3.5 EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID
The Read/Write interface for the pseudo-register EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID follows the
following rules.
ForReadSaveState() :
•The pseudo-register only supports the 64-bit size specified by Width.
•If the processor is in SM at the time the MMI occurred, the pseudo register value
EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer. The value should match
theProcessorId value, as described in the EFI_PROCESSOR_INFORMATION record defined in Volume 2 of
thePlatform Initialization Specification .
ForWriteSaveState() :
•Write operations to this pseudo-register are ignored.
IV-4.3.6 EFI_MM_SAVE_STATE_REGISTER_LMA
The Read/Write interface for the pseudo-register EFI_MM_SAVE_STATE_REGISTER_LMA follows the following
rules.
•The pseudo-register only supports the single Byte size specified by Width. If the processor acts in 32-bit mode
at the time the MMI occurred, the pseudo register value EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT is
returned in Buffer. Otherwise, EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.
#define EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT = 32
#define EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT = 64
EFI_SUCCESS The register was read or written from Save State
EFI_NOT_FOUND The register is not defined for the Save State of Processor
EFI_NOT_FOUND The processor is not in SM
EFI_INVALID_PARAMETER InputparametersarenotvalidForexProcessorNoorregisterwidthisnotcorrectThis
or Buffer is NULL
IV-4.3.7 EFI_MM_CPU_PROTOCOL.WriteSaveState()
Summary
Write data to the CPU save state.
Prototype
typedef
(EFIAPI \*EFI_MM_WRITE_SAVE_STATE (
IV-4.3. CPU Save State Access Services IV-40UEFI Platform Initialization Specification, Release 1.8
IN EFI_MM_SAVE_STATE_REGISTER Register,
);
Width
ThenumberofbytestowritetotheCPUsavestate. Iftheregisterspecifiedby Registerdoesnotsupportthesize
specified by Width, thenEFI_INVALID_PARAMETER s returned.
Register
Specifies the CPU register to write to the save state. The type EFI_MM_SAVE_STATE_REGISTER is de-
fined inReadSaveState() above. If the specified register is not implemented in the CPU save state map then
CpuIndex
Specifies the zero-based index of the CPU save state.
Buffer
Upon entry, this holds the new CPU register value.
This function is used to write the specified number of bytes of the specified register to the CPU save state of the
EFI_NOT_FOUND The register Register is not defined for the Save State of Processor
EFI_INVALID_PARAMETER InputparametersarenotvalidForexampleProcessorIndexorWidthisnotcorrectThis
IV-4.4 MM Save State IO Info
IV-4.4.1 EFI_MM_SAVE_STATE_IO_INFO
Summary
Describes the I/O operation which was in process when the MMI was generated.
Prototype
typedef struct _EFI_MM_SAVE_STATE_IO_INFO {
UINT64 IoData;
UINT16 IoPort;
EFI_MM_SAVE_STATE_IO_WIDTH IoWidth;
EFI_MM_SAVE_STATE_IO_TYPE IoType;
} EFI_MM_SAVE_STATE_IO_INFO
IV-4.4. MM Save State IO Info IV-41UEFI Platform Initialization Specification, Release 1.8
IoData
Forinputinstruction(IN,INS),thisisdatareadbeforetheMMIoccurred. Foroutputinstructions(OUT,OUTS)
this is data that was written before the MMI occurred. The width of the data is specified by IoWidth. The data
buffer is allocated by the Called MMfunction, and it is the Caller’s responsibility to free this buffer.
IoPort
The I/O port that was being accessed when the MMI was triggered.
IoWidth
Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData. See Related Definitions.
IoType
Defines type of I/O instruction. See Related Definitions.
This is the structure of the data which is returned when ReadSaveState() is called with
EFI_MM_SAVE_STATE_REGISTER_IO . If there was no I/O then ReadSaveState() will return EFI_NOT_FOUND .
EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 = 0,
EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 = 1,
EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 = 2,
EFI_MM_SAVE_STATE_IO_WIDTH_UINT64 = 3
} EFI_MM_SAVE_STATE_IO_WIDTH
EFI_MM_SAVE_STATE_IO_TYPE_INPUT = 1,
EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT = 2,
EFI_MM_SAVE_STATE_IO_TYPE_STRING = 4,
EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8
} EFI_MM_SAVE_STATE_IO_TYPE
IV-4.5 MM CPU I/O Protocol
IV-4.5.1 EFI_MM_CPU_IO_PROTOCOL
Summary
Provides CPU I/O and memory access within SM
GUID
#define EFI_MM_CPU_IO_PROTOCOL_GUID \
{ 0x3242a9d8, 0xce70, 0x4aa0, \
0x95, 0x5d, 0x5e, 0x7b, 0x14, 0xd, 0xe4, 0xd2 }
typedef struct \_EFI_MM_CPU_IO_PROTOCOL {
EFI_MM_IO_ACCESS Mem;
EFI_MM_IO_ACCESS Io;
} EFI_MM_CPU_IO_PROTOCOL;
IV-4.5. MM CPU I/O Protocol IV-42UEFI Platform Initialization Specification, Release 1.8
Mem
Allows reads and writes to memory-mapped I/O space. See the Mem()function description. Type
EFI_MM_IO_ACCESS is defined in “Related Definitions” below.
Io
Allows reads and writes to I/O space. See the Io()function description. Type EFI_MM_IO_ACCESS is defined
TheEFI_MM_CPU_IO_PROTOCOL service provides the basic memory, I/O, and PCI interfaces that are used to
abstract accesses to devices.
The interfaces provided in EFI_MM_CPU_IO_PROTOCOL are for performing basic operations to memory and I/O.
TheEFI_MM_CPU_IO_PROTOCOL canbethoughtofasthebusdriverforthesystem. Thesystemprovidesabstracted
accesstobasicsystemresourcestoallowadrivertohaveaprogrammaticmethodtoaccessthesebasicsystemresources.
// EFI_MM_IO_ACCESS
EFI_MM_CPU_IO Read;
EFI_MM_CPU_IO Write;
} EFI_MM_IO_ACCESS;
Read
Write
IV-4.5.2 EFI_MM_CPU_IO_PROTOCOL.Mem()
Summary
Enables a driver to access device registers in the memory space.
Prototype
typedef
(EFIAPI * EFI_MM_CPU_IO (
IN CONST *EFI_MM_CPU_IO_PROTOCOL *This,
IN *EFI_MM_IO_WIDTH* Width,
);
This
TheEFI_MM_CPU_IO_PROTOCOL instance.
IV-4.5. MM CPU I/O Protocol IV-43UEFI Platform Initialization Specification, Release 1.8
Width
SignifiesthewidthoftheI/Ooperations. Type EFI_MM_IO_WIDTH isdefinedin“RelatedDefinitions”below.
Address
The base address of the I/O operations. The caller is responsible for aligning the Addressif required.
Count
The number of I/O operations to perform. Bytes moved is Widthsize *Count, starting at Address.
Buffer
Forreadoperations,thedestinationbuffertostoretheresults. Forwriteoperations,thesourcebufferfromwhich
to write data.
TheEFI_MM_CPU_IO.Mem() function enables a driver to access device registers in the memory.
issues that the bus, device, platform, or type of I/O might require. For example, on IA-32 platforms, width requests of
MM_IO_UINT64 do not work.
TheAddressfield is the bus relative address as seen by the device on the bus.
// EFI_MM_IO_WIDTH
MM_IO_UINT8 = 0,
MM_IO_UINT16 = 1,
MM_IO_UINT32 = 2,
MM_IO_UINT64 = 3
} EFI_MM_IO_WIDTH;
EFI_SUCCESS The data was read from or written to the device
EFI_UNSUPPORTED The Address is not valid for this system
EFI_INVALID_PARAMETER Width or Count or both were invalid
IV-4.5.3 EFI_MM_CPU_IO_PROTOCOL.Io()
Summary
Enables a driver to access device registers in the I/O space.
Prototype
typedef
(EFIAPI \* EFI_MM_CPU_IO) (
IV-4.5. MM CPU I/O Protocol IV-44UEFI Platform Initialization Specification, Release 1.8
);
This
Width
Signifies the width of the I/O operations. Type EFI_MM_IO_WIDTH is defined in Mem().
Address

Summary
Prototype
typedef
);
This
Width
Address
Count
Buffer
TheEFI_MM_CPU_IO.Io() function enables a driver to access device registers in the I/O space. The I/O operations
are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues which the bus,
device, platform, or type of I/O might require. For example, on IA-32 platforms, width requests of MM_IO_UINT64
do not work. The caller must align the starting address to be on a proper width boundary.
IV-4.6 MM PCI I/O Protocol
IV-4.6.1 EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL
Summary
Provides access to PCI I/O, memory and configuration space inside of SM.
GUID
#define EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \
{0x8bc1714d, 0xffcb, 0x41c3, \
0x89, 0xdc, 0x6c, 0x74, 0xd0, 0x6d, 0x98, 0xea}
Prototype
typedef EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL;
IV-4.6. MM PCI I/O Protocol IV-45UEFI Platform Initialization Specification, Release 1.8
This protocol provides the same functionality as the PCI Root Bridge I/O Protocol defined in the UEFI Specifcation ,
except that the functions for Map(),Unmap() ,Flush(),AllocateBuffer() ,FreeBuffer() ,SetAttributes() , andConfig-
uration() may return EFI_UNSUPPORTED .
IV-4.7 MM Ready to Lock Protocol
IV-4.7.1 EFI_MM_READY_TO_LOCK_PROTOCOL
Summary
Indicates that MM resources and services that should not be used by the third party code are about to be locked.
GUID
#define EFI_MM_READY_TO_LOCK_PROTOCOL_GUID \
{ 0x47b7fa8c, 0xf4bd, 0x4af6, {0x82, 0x0, 0x33, 0x30, 0x86, 0xf0, 0xd2, 0xc8 } }
Prototype
NULL
This protocol is a mandatory protocol published by the MM Foundation code when the system is preparing to lock
certain resources and interfaces in anticipation of the invocation of 3rd party extensible modules. This protocol is an
SM counterpart of the DXE MM Ready to Lock Protocol . This protocol prorogates resource locking notification into
SM environment. This protocol is installed after installation of the SM End of DXE Protocol .
IV-4.8 MM MP protocol
IV-4.8.1 EFI_MM_MP_PROTOCOL
Summary
TheMMMPprotocolprovidesasetoffunctionstoallowexecutionofproceduresonprocessorsthathaveenteredMM.
This protocol has the following properties:
•The caller can only invoke execution of a procedure on a processor, other than the caller, that has also entered
MM.
•It is possible to invoke a procedure on multiple processors.
•Supports blocking and non-blocking modes of operation.
GUID
// {5D5450D7-990C-4180-A803-8E63F0608307}
#define EFI_MM_MP_PROTOCOL_GUID \
{ 0x5d5450d7, 0x990c, 0x4180,
{ 0xa8, 0x3, 0x8e, 0x63, 0xf0, 0x60, 0x83, 0x7 } };
Protocol
IV-4.7. MM Ready to Lock Protocol IV-46UEFI Platform Initialization Specification, Release 1.8
typedef struct \_EFI_MM_MP_PROTOCOL {
UINT32 Revision,
UINT32 Attributes ,
EFI_MM\_ GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors,
EFI_MM_DISPATCH_PROCEDURE DispatchProcedure,
EFI_MM_BROADCAST_PROCEDURE BroadcastProcedure,
EFI_MM_SET_STARTUP_PROCEDURE SetStartupProcedure,
EFI_CHECK_FOR_PROCEDURE CheckOnProcedure,
EFI_WAIT_FOR_PROCEDURE WaitForProcedure,
}EFI_MM_MP_PROTOCOL;
Members
Revision
Revision information for the interface
Provides information about the capabilities of the implementation.
Return the number of processors in the system.
DispatchProcedure
Run a procedure on one AP.
BroadcastProcedure
Run a procedure on all processors except the caller.
SetStartupProcedure
ProvideaproceduretobeexecutedwhenanAPstartsupfrompowerstatewherecorecontextandconfiguration
is lost.
CheckOnProcedure
Check whether a procedure on one or all APs has completed.
WaitForProcedure
Wait until a procedure on one or all APs has completed execution.
IV-4.8.2 EFI_MM_MP_PROTOCOL.Revision
Summary
For implementations compliant with this revision of the specification this value must be 0.
IV-4.8.3 EFI_MM_MP_PROTOCOL.Attributes
Summary
This parameter takes the following format:
IV-4.8. MM MP protocol IV-47UEFI Platform Initialization Specification, Release 1.8
Field Number of bits Bit offset Description
Timeout support flag 1 0
Thisbitdescribeswhether
timeouts are supported in
DispatchProcedure and
This bit is set to one if
BroadcastProcedure .
This bit is set to zero if
timeouts are not
supported in
In implementations where
supported, timeout values
are always treated as
infinite.
See
EFI_MM_MP_TIMEOUT_SUPPORTED
in Related Definitions
below.
Reserved 31 1 Reserved must be zero
IV-4.8.4 EFI_MM_MP_PROTOCOL.GetNumberOfProcessors()
Summary
This service retrieves the number of logical processor in the platform.
Prototype
typedef
FI_STATUS
(EFIAPI *EFI_MM_GET_NUMBER_OF_PROCESSORS) (
IN CONST EFI_MM_MP_PROTOCOL *This,
OUT UINTN *NumberOfProcessors
);
This
The EFI_MM_MP_PROTOCOL instance.
Pointer to the total number of logical processors in the system, including the BSP and all APs.
IV-4.8. MM MP protocol IV-48UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The number of processors was retrieved successfully
IV-4.8.5 EFI_MM_MP_PROTOCOL.DispatchProcedure()
Summary
This service allows the caller to invoke a procedure one of the application processors (AP). This function uses an op-
tional token parameter to support blocking and non-blocking modes. If the token is passed into the call, the function
will operate in a non-blocking fashion and the caller can check for completion with CheckOnProcedure orWaitFor-
Procedure .
Prototype
typedef
(EFIAPI *EFI_MM_DISPATCH_PROCEDURE) (
IN EFI_AP_PROCEDURE2 Procedure,
IN UINTN CpuNumber,
IN OUT VOID *ProcedureArguments OPTIONAL,
IN OUT MM_COMPLETION *Token,
IN OUT EFI_STATUS *CPUStatus,
);
This
TheEFI_MM_MP_PROTOCOL instance.
Procedure
A pointer to the procedure to be run on the designated target AP of the system. Type EFI_AP_PROCEDURE2
is defined below in related definitions.
CpuNumber
The zero-based index of the processor number of the target AP, on which the code stream is supposed to run. If
the number points to the calling processor then it will not run the supplied code.
Indicates the time limit in microseconds for this AP to finish execution of Procedure , either for blocking or
non-blocking mode. Zero means infinity. If the timeout expires before this AP returns from Procedure , then
Procedure on the AP is terminated. If the timeout expires in blocking mode, the call returns EFI_TIMEOUT.
If the timeout expires in non-blocking mode, the timeout determined can be through CheckOnProcedure or
WaitForProcedure .
Note that timeout support is optional. Whether an implementation supports this feature, can be determined via
theAttributes data member.
ProcedureArguments
Token
Thisisanoptionalparameterthatallowsthecallertoexecutetheprocedureinablockingornon-blockingfashion.
If it isNULLthe call is blocking, and the call will not return until the AP has completed the procedure. If the
IV-4.8. MM MP protocol IV-49UEFI Platform Initialization Specification, Release 1.8
tokenisnot NULL,thecallwillreturnimmediately. Thecallercancheckwhethertheprocedurehascompleted
withCheckOnProcedure orWaitForProcedure .
CpuStatus
This optional pointer may be used to get the status code returned by Procedure when it completes execution
on the target AP, or with EFI_TIMEOUT if theProcedure fails to complete within the optional timeout. The
implementation will update this variable with EFI_NOT_READY prior to starting Procedure on the target AP.
EFI_SUCCESS IntheblockingcasethisindicatesthatProcedurehascompletedexecutiononthetargetAPInthe
non blocking case this indicates that the procedure has been successfully scheduled for execution
on the target AP
EFI_INVALID_PARAMETER The input arguments are out of range Either the target AP is the caller of the function or the
Procedure or Token is NULL
EFI_NOT_READY If the target AP is busy executing another procedure
EFI_ALREADY_STARTED Before the AP procedure associated with the Token is finished the same Token cannot be used to

CpuStatus
dispatch or broadcast another procedure
EFI_TIMEOUT In blocking mode the timeout expired before the specified AP has finished
IV-4.8.6 EFI_MM_MP_PROTOCOL.BroadcastProcedure()
Summary
This service allows the caller to invoke a procedure on all running application processors (AP) except the caller. This
functionusesanoptionaltokenparametertosupportblockingandnon-blockingmodes. Ifthetokenispassedintothe
call,thefunctionwilloperateinanon-blockingfashionandthecallercancheckforcompletionwith CheckOnProcedure
orWaitForProcedure .
Itisnotnecessaryfortheimplementationtoruntheprocedureoneveryprocessorontheplatform. Processorsthatare
powered down in such a way that they cannot respond to interrupts, may be excluded from the broadcast.
Prototype
typedef
(EFIAPI *EFI_MM_BROADCAST_PROCEDURE) (
);
This
Procedure
A pointer to the code stream to be run on the APs that have entered MM. Type EFI_AP_PROCEDURE2 is
defined below in related definitions.
IndicatesthetimelimitinmicrosecondsfortheAPstofinishexecutionofProcedure,eitherforblockingornon-
blockingmode. Zeromeansinfinity. IfthetimeoutexpiresbeforeallAPsreturnfrom Procedure ,thenProcedure
IV-4.8. MM MP protocol IV-50UEFI Platform Initialization Specification, Release 1.8
on the failed APs is terminated. If the timeout expires in blocking mode, the call returns EFI_TIMEOUT .
Note that timeout support is optional. Whether an implementation supports this feature can be determined via
Token
token is not NULL, the call will return immediately. The caller can check whether the procedure has completed
CPUStatus
This optional pointer may be used to get the individual status returned by every AP that participated in the
broadcast. This parameter if used provides the base address of an array to hold the EFI_STATUS value of each
AP in the system. The size of the array can be ascertained by the GetNumberOfProcessors function.
Asmentionedabove,thebroadcastmaynotincludeeveryprocessorinthesystem. Someimplementationsmayexclude
processors that have been powered down in such a way that they are not responsive to interrupts. Additionally the
broadcast excludes the processor which is making the BroadcastProcedure call. For every excluded processor, the
array entry must contain a value of EFI_NOT_STARTED .
EFI_SUCCESS IntheblockingcasethisindicatesthatProcedurehascompletedexecutionontheAPsInthenon
blocking case this indicates that the procedure has been successfully scheduled for execution on
the APs
EFI_INVALID_PARAMETER Procedure or Token is NULL
EFI_NOT_READY If a target AP is busy executing another procedure
EFI_TIMEOUT In blocking mode the timeout expired before all enabled APs have finished
EFI_ALREADY_STARTED BeforetheAPprocedureassociatedwiththeTokenisfinishedthesameTokencannotbeusedto
IV-4.8.7 EFI_MM_MP_PROTOCOL.SetStartupProcedure()
Summary
ThisserviceallowsthecallertosetastartupprocedurethatwillbeexecutedwhenanAPpowersupfromastatewhere
core configuration and context is lost. The procedure is execution has the following properties:
•The procedure executes before the processor is handed over to the operating system.
•All processors execute the same startup procedure.
•The procedure may run in parallel with other procedures invoked through the functions in this protocol, or with
processors that are executing an MM handler or running in the operating system.
Prototype
typedef
(EFIAPI *EFI_SET_STARTUP\_ PROCEDURE) (
IV-4.8. MM MP protocol IV-51UEFI Platform Initialization Specification, Release 1.8
IN EFI_AP_PROCEDURE * Procedure,
);
This
Procedure
A pointer to the code stream to be run on the designated target AP of the system. Type EFI_AP_PROCEDURE
is defined below in Volume 2 with the related definitions of EFI_MP_SERVICES_PROTOCOL.StartupAllAPs .
If caller may pass a value of NULLto deregister any existing startup procedure.
EFI_SUCCESS TheProcedure has been set successfully.
IV-4.8.8 EFI_MM_MP_PROTOCOL.CheckOnProcedure()
Summary
When non-blocking execution of a procedure on an AP is invoked with DispatchProcedure , via the use of a token,
this function can be used to check for completion of the procedure on the AP. The function takes the token that was
passed into the DispatchProcedure call. If the procedure is complete, and therefore it is now possible to run another
procedure on the same AP, this function returns EFI_SUCESS . In this case the status returned by the procedure that
executed on the AP is returned in the token’s Statusfield. If the procedure has not yet completed, then this function
returnsEFI_NOT_READY .
When a non-blocking execution of a procedure is invoked with BroadcastProcedure , via the use of a token, this
function can be used to check for completion of the procedure on all the broadcast APs. The function takes the token
thatwaspassedintothe BroadcastProcedure call. IftheprocedureiscompleteonallbroadcastAPsthisfunctionreturns
EFI_SUCESS .IftheprocedurehasnotyetcompletedonthebroadcastAPs,thefunctionreturns EFI_NOT_READY .
Prototype
typedef
(EFIAPI \*EFI_CHECK_ON_PROCEDURE)
IN OUT MM_COMPLETION Token
);
This
Token
This parameter describes the token that was passed into DispatchProcedure orBroadcastProcedure . Type
MM_COMPLETION is defined below in related definitions.
IV-4.8. MM MP protocol IV-52UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS Procedure has completed
EFI_NOT_READY The Procedure has not completed
EFI_INVALID_PARAMETER Token is NULL
EFI_NOT_FOUND Token is not currently in use for a non blocking call
IV-4.8.9 EFI_MM_MP_PROTOCOL.WaitForProcedure()
Summary
When a non-blocking execution of a procedure on an AP is invoked via DispatchProcedure , this function will block
the caller until the remote procedure has completed on the designated AP. The non-blocking procedure invocation is
identified by the Tokenparameter, which must match the token that used when DispatchProcedure was called.
When a non-blocking execution of a procedure on an AP is invoked via BroadcastProcedure this function will block
the caller until the remote procedure has completed on all of the APs that entered MM. The non-blocking procedure
invocation is identified by the Tokenparameter, which must match the token that used when BroadcastProcedure was
called.
Prototype
typedef
(EFIAPI \*EFI_WAIT_FOR_PROCEDURE)
IN OUT MM_COMPLETION Token,
);
This
Token
This parameter describes token that was passed into DispatchProcedure or BroadcastProcedure.
EFI_SUCCESS The procedure has completed
EFI_AP_PROCEDURE is defined in Volume 2 of this specification, with
EFI_MP_SERVICES_PROTOCOL.StartupAllAPs
// Attribute flags
#define EFI_MM_MP_TIMEOUT_SUPPORTED 0x1
// Procedure callback
typedef
(EFIAPI *EFI_AP_PROCEDURE2)(
IV-4.8. MM MP protocol IV-53UEFI Platform Initialization Specification, Release 1.8
);
// completion token
typedef VOID *MM_COMPLETION;
IV-4.9 MM Configuration Protocol
IV-4.9.1 EFI_MM_CONFIGURATION_PROTOCOL
Summary
Register MM Foundation entry point.*
GUID
#define EFI_MM_CONFIGURATION_PROTOCOL_GUID { \
0x26eeb3de, 0xb689, 0x492e, \
0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7
}
Prototype
typedef struct \_EFI_MM_CONFIGURATION_PROTOCOL {
EFI_MM_REGISTER_MM_FOUNDATION_ENTRY RegisterMmFoundationEntry;
} EFI_MM_CONFIGURATION_PROTOCOL;
Members
RegisterMmFoundationEntry
A function to register the MM Foundation entry point.

typedef
);
Summary
GUID
}
Prototype
Members
This Protocol is an MM Protocol published by a standalone MM CPU driver to allow MM Foundation register MM
Foundation entry point. If a platform chooses to let MM Foundation load standalone MM CPU driver for MM relo-
cation, this protocol must be produced this standalone MM CPU driver. The RegisterMmFoundationEntry() function
allows the MM Foundation to register the MM Foundation entry point with the MM entry vector code.
IV-4.9.2 EFI_MM_CONFIGURATION_PROTOCOL.RegisterMmFoundationEntry()
Summary
Register the MM Foundation entry point in MM standalone mode.
Prototype
typedef
(EFIAPI \*EFI_MM_REGISTER_MM_FOUNDATION_ENTRY) (
IN CONST EFI_MM_CONFIGURATION_PROTOCOL \* *This* ,
IN EFI_MM_ENTRY_POINT *MmEntryPoint*
)
IV-4.9. MM Configuration Protocol IV-54UEFI Platform Initialization Specification, Release 1.8
This
TheEFI_MM_CONFIGURATION_PROTOCOL instance.
MmEntryPoint
MM Foundation entry point.
This function registers the MM Foundation entry point with the processor code. This entry point will be invoked by
the MM Processor entry code as defined in section 2.5.
Table 4.1: Status Codes Returned
EFI_SUCCESS The entry-point was successfully registered.
IV-4.10 MM End Of PEI Protocol
IV-4.10.1 EFI_MM_END_OF_PEI_PROTOCOL
Summary
Indicate that the UEFI/PI firmware is about to exit PEI phase.
GUID
#define EFI_MM_END_OF_PEI_PROTOCOL_GUID { \\
0xf33e1bf3, 0x980b, 0x4bfb, 0xa2, 0x9a, 0xb2, 0x9c, 0x86,
0x45, 0x37, 0x32 \\
}
Prototype
NULL
This protocol is a MM Protocol published by a standalone MM Foundation code if MM Foundation is loaded in PEI
phase. This protocol should be installed immediately after DXE IPL installs EFI_PEI_END_OF_PEI_PHASE_PPI .
IV-4.11 MM UEFI Ready Protocol
IV-4.11.1 EFI_MM_UEFI_READY_PROTOCOL
Summary
Indicate that the UEFI/PI firmware is in UEFI phase and EFI_SYSTEM_TABLE is ready to use.
GUID
#define EFI_MM_UEFI_READY_PROTOCOL_GUID { \
0xc63a953b, 0x73b0, 0x482f, 0x8d, 0xa6, 0x76, 0x65, 0x66, 0xf6, 0x5a, 0x82 \
}
IV-4.10. MM End Of PEI Protocol IV-55UEFI Platform Initialization Specification, Release 1.8
Prototype
NULL
ThisprotocolisaMMProtocolpublishedbyastandaloneMMFoundationcodeafterDXEMMIPLcommunicateswith
MMFoundationtotellMMFoundationUEFIsystemtablelocation. AfterthattraditionMMdrivercanbedispatched.
IV-4.12 MM Ready To Boot Protocol
IV-4.12.1 EFI_MM_READY_TO_BOOT_PROTOCOL
Summary
Indicate that the UEFI/PI firmware is about to load and execute a boot option.
GUID
#define EFI_MM_READY_TO_BOOT_PROTOCOL_GUID { \\
0x6e057ecf, 0xfa99, 0x4f39, 0x95, 0xbc, 0x59, 0xf9, 0x92,
0x1d, 0x17, 0xe4 \\
}
Prototype
NULL
This protocol is a MM Protocol published by a standalone MM Foundation code, when UEFI/PI firmware is about
to load and execute a boot option. There is an associated event GUID that is signaled for the DXE drivers called
EFI_EVENT_GROUP_READY_TO_BOOT .
IV-4.13 MM Exit Boot Services Protocol
IV-4.13.1 EFI_MM_EXIT_BOOT_SERVICES_PROTOCOL
Summary
Indicate that the UEFI/PI firmware is about to enter UEFI runtime phase.
GUID
#define EFI_MM_EXIT_BOOT_SERVICES_PROTOCOL_GUID { \\
0x296eb418, 0xc4c8, 0x4e05, 0xab, 0x59, 0x39, 0xe8, 0xaf,
0x56, 0xf0, 0xa \\
}
Prototype
NULL
IV-4.12. MM Ready To Boot Protocol IV-56UEFI Platform Initialization Specification, Release 1.8
to enter UEFI runtime phase. There is an associated event GUID that is signaled for the DXE drivers called
EFI_EVENT_GROUP_EXIT_BOOT_SERVICES .
IV-4.14 MM Security Architecture Protocol
EFI_MM_SECURITY_ARCHITECTURE_PROTOCOL
Summary
Abstractssecurity-specificfunctionsfromtheMMFoundationforpurposesofhandlingGUIDedsectionencapsulations
instandalonemode. ThisprotocolmustbeproducedbyaMMdriverandmayonlybeconsumedbytheMMFoundation
and any other MM drivers that need to validate the authentication of files.
GUID
#define EFI_MM_SECURITY_ARCH_PROTOCOL_GUID { \\
0xb48e70a3, 0x476f, 0x486d, 0xb9, 0xc0, 0xc2, 0xd0, 0xf8,
0xb9, 0x44, 0xd9 \\
}
Prototype
Same as*EFI_SECURITY_ARCH_PROTOCOL*.
TheEFI_MM_SECURITY_ARCH_PROTOCOL isusedtoabstractplatform-specificpolicy fromtheMMFoundation
in standalone mode. This includes locking flash upon failure to authenticate, attestation logging, and other exception
operations. The usage is same as DXE EFI_SECURITY_ARCH_PROTOCOL .
IV-4.15 MM End of DXE Protocol
IV-4.15.1 EFI_MM_END_OF_DXE_PROTOCOL
Summary
Indicatesendoftheexecutionphasewhenallofthecomponentsareundertheauthorityoftheplatformmanufacturer.
GUID
#define EFI_MM_END_OF_DXE_PROTOCOL_GUID \\
{ 0x24e70042, 0xd5c5, 0x4260, \\
{ 0x8c, 0x39, 0xa, 0xd3, 0xaa, 0x32, 0xe9, 0x3d } }
Prototype
NULL
IV-4.14. MM Security Architecture Protocol IV-57UEFI Platform Initialization Specification, Release 1.8
This protocol is a mandatory protocol published by MM Foundation code. This protocol is an MM counterpart of the
EndofDXEEvent. ThisprotocolprorogatesEndofDXEnotificationintoMMenvironment. Thisprotocolisinstalled
prior to installation of the MM Ready to Lock Protocol.
IV-4.16 MM Handler State Notification Protocol
IV-4.16.1 EFI_MM_HANDLER_STATE_NOTIFICATION_PROTOCOL
Summary
Register or unregister a MM Handler State notification function.
GUID
// {30C8340F-4C30-41D9-BFAE-444ACB2C1F76}
#define EFI_MM_HANDLER_STATE_NOTIFICATION_PROTOCOL_GUID \
{0x30c8340f, 0x4c30, 0x41d9, {0xbf, 0xae, 0x44, 0x4a, 0xcb, 0x2c, 0x1f, 0x76}}
Prototype
typedef
struct \_EFI_MM_HANDLER_STATE_NOTIFICATION_PROTOCOL {
EFI_MM_HANDLER_STATE_NOTIFIER_REGISTER
HandlerStateNotifierRegister;
EFI_MM_HANDLER_STATE_NOTIFIER_UNREGISTER
HandlerStateNotifierUnregister;
} EFI_MM_HANDLER_STATE_NOTIFICATION_PROTOCOL;
Members
HandlerStateNotifierRegister
Register notification function
HandlerStateNotifierUnRegister
Un-register previously registered notification function.
This protocol is an MM Protocol published by Standalone MM Foundation code if MM Foundation is loaded in SEC
Phase. This protocol must be installed before any MM Standalone or Traditional drivers are initialized in MMRAM.
The MM Handler State notification protocol provides a set of functions to allow registration and un-registration of a
notification procedure that is invoked whenever a MM Handler is registered or un-registered through an invocation of
MmiHandlerRegister() orMmiHandlerUnRegister() services in the MMST.
IV-4.16.2 EFI_MM_HANDLER_STATE_NOTIFICATION_PROTOCOL.HandlerStateNotifierRegister
Summary
Prototype
IV-4.16. MM Handler State Notification Protocol IV-58UEFI Platform Initialization Specification, Release 1.8
typedef
(EFIAPI *EFI_MM_HANDLER_STATE_NOTIFIER_REGISTER)(
IN EFI_MM_HANDLER_STATE_NOTIFY_FN Notifier,
);
Notifier
Pointer to function to invoke whenever MmiHandlerRegister() orMmiHandlerUnRegister() in the MMST are
called. Type EFI_MM_HANDLER_STATE_NOTIFY_FN is defined in “Related Definitions” below
Returns the registration record that has been successfully added
Thisserviceregistersafunction( Notifier)whichwillbecalledwheneveraMMHandlerisregisteredorun-registered
throughinvocationsof MmiHandlerRegister() orMmiHandlerUnRegister() intheMMST.Onasuccessfulreturn, Reg-
istrationcontains a record that can be later used to unregister the Notifierfunction.
// EFI_MM_HANDLER_STATE_NOTIFY_FN
typedef
(EFIAPI \*EFI_MM_HANDLER_STATE_NOTIFY_FN)(
IN EFI_MM_HANDLER_ENTRY_POINT Handler,
IN CONST EFI_GUID \*HandlerType OPTIONAL,
IN EFI_MM_HANDLER_STATE HandlerState
);
Handler
MM Handler function pointer. The Handlerparameter is the same as the one passed to MmiHandlerRegister()
.TypeEFI_MM_HANDLER_ENTRY_POINT isdefinedinVolume4ofthePlatformInitializationSpecification.
MMI handler. The HandlerType parameter is the same as the one passed to MmiHandlerRegister() .
HandlerState
Handler state i.e. registered or unregistered. Type EFI_MM_HANDLER_STATE is defined below. This param-
eter indicates whether EFI_MM_HANDLER_STATE_NOTIFY_FN has been invoked in response to MmiHan-
dlerRegister() orMmiHandlerUnRegister() .
// EFI_MM_HANDLER_STATE
HandlerRegistered,
HandlerUnregistered,
} EFI_MM_HANDLER_STATE;
Status Codes Returned (EFI_MM_HANDLER_STATE_NOTIFY_FN)
IV-4.16. MM Handler State Notification Protocol IV-59UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS Notification function was successfully invoked
EFI_INVALID_PARAMETER HandlerisNULLorHandlerType is unrecognized
Status Codes Returned (HandlerStateNotifierRegister)
EFI_SUCCESS Notification function registered successfully

EFI_INVALID_PARAMETER Registration is NULL
IV-4.16.3 EFI_MM_HANDLER_STATE_NOTIFICATION_PROTOCOL.HandlerStateNotifierUnregister
Summary
Un-register notification function.
Prototype
typedef
(EFIAPI \*EFI_MM_HANDLER_STATE_NOTIFIER_UNREGISTER)(
IN VOID \*Registration
);
Registration record returned upon successfully registering the callback function
This service un-registers a previously registered Notifierfunction. The function is identified by the Registration pa-
rameter. Subsequent invocations of MmiHandlerRegister() orMmiHandlerUnRegister() will not invoke the Notifier
function.
Status Codes Returned (HandlerStateNotifierUnRegister)
EFI_SUCCESS Notification function un-registered successfully
EFI_NOT_FOUND Registration record not found
IV-4.16. MM Handler State Notification Protocol IV-60CHAPTER
FIVE
UEFI PROTOCOLS
IV-5.1 Introduction
The services described in this Mode chapter describe a series of protocols that locate the MMST, manipulate the
Management RAM (MMRAM) apertures, and generate MMIs. Some of these protocols provide only boot services
while others have both boot services and runtime services.
The following protocols are defined in this chapter:
•EFI_MM_BASE_PROTOCOL
•EFI_MM_ACCESS_PROTOCOL
•EFI_MM_CONTROL_PROTOCOL
•EFI_MM_CONFIGURATION_PROTOCOL
•EFI_MM_COMMUNICATION_PROTOCOL
IV-5.2 EFI MM Base Protocol
IV-5.2.1 EFI_MM_BASE_PROTOCOL
Dummary
This protocol is used to locate the MMST during MM Driver Initialization.
GUID
#define EFI_MM_BASE_PROTOCOL_GUID \
{ 0xf4ccbfb7, 0xf6e0, 0x47fd, 0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 }
typedef struct \_EFI_MM_BASE_PROTOCOL {
EFI_MM_INSIDE_OUT InMm;
EFI_MM_GET_MMST_LOCATION GetMmstLocation;
} EFI_MM_BASE_PROTOCOL;
InMm
Detects whether the caller is inside or outside of MMRAM. See the InMm()function description.
IV-61UEFI Platform Initialization Specification, Release 1.8
GetMmstLocation
Retrieves the location of the Management Mode System Table (MMST) . See the GetMmstLocation() function
TheEFI_MM_BASE_PROTOCOL is provided by the MM IPL driver. It is a required protocol. It will be utilized by
all MM Drivers to locate the MM infrastructure services and determine whether the driver is being invoked as a DXE
or MM Driver.
IV-5.2.2 EFI_MM_BASE_PROTOCOL.InMm()
Summary
Service to indicate whether the driver is currently executing in the MM Driver Initialization phase.
Prototype
typedef
(EFIAPI *EFI_MM_INSIDE_OUT) (
IN CONST EFI_MM_BASE_PROTOCOL *This,
OUT BOOLEAN *InMmram*
)
This
TheEFI_MM_BASE_PROTOCOL instance.
InMmram
PointertoaBooleanwhich,onreturn,indicatesthatthedriveriscurrentlyexecutinginsideofMMRAM(TRUE)
or outside of MMRAM (FALSE).
This service returns whether the caller is being executed in the MM Driver Initialization phase. For MM Drivers, this
willreturn TRUEinInMmram whileinsidethedriver’sentrypointandotherwise FALSE.ForcombinationMM/DXE
drivers, this will return FALSEin the DXE launch. For the MM launch, it behaves as an MM Driver.
EFI_SUCCESS The call returned successfully.
EFI_INVALID_PARAMETER InMmram wasNULL.
IV-5.2.3 EFI_MM_BASE_PROTOCOL.GetMmstLocation()
Summary
Returns the location of the Management Mode Service Table (MMST) .
Prototype
typedef
(EFIAPI \*EFI_MM_GET_MMST_LOCATION) (
IN CONST *EFI_MM_BASE_PROTOCOL* *\*This* ,
IV-5.2. EFI MM Base Protocol IV-62UEFI Platform Initialization Specification, Release 1.8
IN OUT *EFI_MM_SYSTEM_TABLE* *\**Mmst*
)
This
Mmst
On return, points to a pointer to the Management Mode Service Table (MMST).
This function returns the location of the Management Mode Service Table (MMST) . The use of the API is such that a
drivercandiscoverthelocationoftheMMSTinitsentrypointandthencacheitinsomedriverglobalvariablesothat
the MMST can be invoked in subsequent handlers.
EFI_INVALID_PARAMETER Mmstwas invalid.
EFI_UNSUPPORTED Not in MM.
IV-5.3 MM Access Protocol
IV-5.3.1 EFI_MM_ACCESS_PROTOCOL
Summary
This protocol is used to control the visibility of the MMRAM on the platform.
GUID
#define EFI_MM_ACCESS_PROTOCOL_GUID \
{ 0xc2702b74, 0x800c, 0x4131, 0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac }
typedef struct _EFI_MM_ACCESS_PROTOCOL {
EFI_MM_OPEN Open;
EFI_MM_CLOSE Close;
EFI_MM_LOCK Lock;
EFI_MM_CAPABILITIES GetCapabilities;
BOOLEAN LockState ;
BOOLEAN OpenState ;
} EFI_MM_ACCESS_PROTOCOL;
Open
Opens the MMRAM. See the Open()function description.
Close
Closes the MMRAM. See the Close()function description.
IV-5.3. MM Access Protocol IV-63UEFI Platform Initialization Specification, Release 1.8
Lock
Locks the MMRAM. See the Lock()function description.
GetCapabilities
Gets information about all MMRAM regions. See the GetCapabilities() function description.
LockState
Indicates the current state of the MMRAM. Set to TRUEif MMRAM is locked.
OpenState
Indicates the current state of the MMRAM. Set to TRUEif MMRAM is open.
TheEFI_MM_ACCESS_PROTOCOL abstracts the location and characteristics of MMRAM. The platform should re-
port all MMRAM via EFI_MM_ACCESS_PROTOCOL . The principal functionality found in the memory controller
includes the following:
•Exposing the MMRAM to all non-MM agents, or the “open” state
•Hiding the MMRAM to all but the MM agents, or the “closed” state
•Securing or “locking” the MMRAM, such that the settings cannot be changed by either boot service or runtime
agents
IV-5.3.2 EFI_MM_ACCESS_PROTOCOL.Open()
Summary
Opens the MMRAM area to be accessible by a boot-service driver.
Prototype
typedef
(EFIAPI \*EFI_MM_OPEN) (
IN *EFI_MM_ACCESS_PROTOCOL *This
);
This
TheEFI_MM_ACCESS_PROTOCOL instance.
This function “opens” MMRAM so that it is visible while not inside of MM. The function should re-
turnEFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function should return
EFI_DEVICE_ERROR if the MMRAM configuration is locked.
EFI_SUCCESS The operation was successful
EFI_UNSUPPORTED The system does not support opening and closing of MMRAM
EFI_DEVICE_ERROR MMRAM cannot be opened perhaps because it is locked
IV-5.3. MM Access Protocol IV-64UEFI Platform Initialization Specification, Release 1.8
IV-5.3.3 EFI_MM_ACCESS_PROTOCOL.Close()
Summary
Inhibits access to the MMRAM.
Prototype
typedef
(EFIAPI *EFI_MM_CLOSE) (
IN EFI_MM_ACCESS_PROTOCOL *This
);
This
This function “closes” MMRAM so that it is not visible while outside of MM. The function should return
EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.
EFI_DEVICE_ERROR MMRAM cannot be closed
IV-5.3.4 EFI_MM_ACCESS_PROTOCOL.Lock()
Summary
Prototype
typedef
(EFIAPI *EFI_MM_LOCK) (
);
This
ThisfunctionprohibitsaccesstotheMMRAMregion. Thisfunctionisusuallyimplementedsuchthatitisawrite-once
EFI_SUCCESS The device was successfully locked.
EFI_UNSUPPORTED The system does not support locking of MMRAM.
IV-5.3. MM Access Protocol IV-65UEFI Platform Initialization Specification, Release 1.8
IV-5.3.5 EFI_MM_ACCESS_PROTOCOL.GetCapabilities()
Summary
Queries the memory controller for the regions that will support MMRAM.
Prototype
typedef
(EFIAPI *EFI_MM_CAPABILITIES) (
IN CONST EFI_MM_ACCESS_PROTOCOL *This,
IN OUT UINTN *MmramMapSize,
IN OUT EFI_MMRAM_DESCRIPTOR *MmramMap
);
This
MmramMapSize
A pointer to the size, in bytes, of the MmramMemoryMap buffer. On input, this value is the size of the buffer
thatisallocatedbythecaller. Onoutput,itisthesizeofthebufferthatwasreturnedbythefirmwareifthebuffer
was large enough, or, if the buffer was too small, the size of the buffer that is needed to contain the map.
MmramMap
A pointer to the buffer in which firmware places the current memory map. The map is an array of
EFI_MMRAM_DESCRIPTOR s. TypeEFI_MMRAM_DESCRIPTOR isdefinedin“RelatedDefinitions”below.
This function describes the MMRAM regions. This data structure forms the contract between the MM Access and
MMIPLdrivers. ThereisanambiguitywhenanyMMRAMregionisremapped. Forexample,onsomechipsets,some
MMRAMregionscanbeinitializedatonephysicaladdressbutislateraccessedatanotherprocessoraddress. Thereis
currentlynowayfortheMMIPLdrivertoknowthatitmustusetwodifferentaddressesdependingonwhatitistrying

);
This
MmramMap
todo. Asaresult,initialconfigurationandloadingcanusethephysicaladdress PhysicalStart whileMMRAMisopen.
However, once the region has been closed and needs to be accessed by agents in MM, the CpuStart address must be
used.
This protocol publishes the available memory that the chipset can shroud for the use of installing code. These regions
serve the dual purpose of describing which regions have been open, closed, or locked. In addition, these regions may
includeoverlappingmemoryranges,dependingonthechipsetimplementation. Thelattermightincludeachipsetthat
supportsT-SEG,wherememorynearthetopofthephysicalDRAMcanbeallocatedforMMRAMtoo. Thekeything
to note is that the regions that are described by the protocol are a subset of the capabilities of the hardware.
//EFI_MMRAM_STATE
//
// Hardware state
//
#define EFI_MMRAM_OPEN 0x00000001
#define EFI_MMRAM_CLOSED 0x00000002
#define EFI_MMRAM_LOCKED 0x00000004
//
IV-5.3. MM Access Protocol IV-66UEFI Platform Initialization Specification, Release 1.8
// Capability
//
#define EFI_CACHEABLE 0x00000008
//
// Logical usage
//
#define EFI_ALLOCATED 0x00000010
//
// Directive prior to usage
//
#define EFI_NEEDS_TESTING 0x00000020
#define EFI_NEEDS_ECC_INITIALIZATION 0x00000040
// EFI_MMRAM_DESCRIPTOR
typedef struct \_EFI_MMRAM_DESCRIPTOR {
EFI_PHYSICAL_ADDRESS CpuStart;
UINT64 RegionState;
} EFI_MMRAM_DESCRIPTOR;
Designates the physical address of the MMRAM in memory. This view of memory is the same as seen by I/O-
basedagents,forexample,butitmaynotbetheaddressseenbytheprocessors. Type EFI_PHYSICAL_ADDRESS
is defined in AllocatePages() in the UEFI Specification.
CpuStart
Designates the address of the MMRAM, as seen by software executing on the processors. This address may or
may not match PhysicalStart .
PhysicalSize
Describes the number of bytes in the MMRAM region.
RegionState
Describes the accessibility attributes of the MMRAM. These attributes include the hardware state (e.g.,
Open/Closed/Locked), capability (e.g., cacheable), logical allocation (e.g., allocated), and pre-use initialization
(e.g., needs testing/ECC initialization).
EFI_SUCCESS The chipset supported the given resource
EFI_BUFFER_TOO_SMALL TheMmramMapparameterwastoosmallThecurrentbuffersizeneededtoholdthemem-
ory map is returned in MmramMapSize
IV-5.3. MM Access Protocol IV-67UEFI Platform Initialization Specification, Release 1.8
IV-5.4 MM Control Protocol
IV-5.4.1 EFI_MM_CONTROL_PROTOCOL
Summary
This protocol is used initiate synchronous MMIs.
GUID
#define EFI_MM_CONTROL_PROTOCOL_GUID \
{ 0x843dc720, 0xab1e, 0x42cb, 0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b }
typedef struct _EFI_MM_CONTROL_PROTOCOL {
EFI_MM_ACTIVATE Trigger;
EFI_MM_DEACTIVATE Clear;
EFI_MM_PERIOD MinimumTriggerPeriod;
} EFI_MM_CONTROL_PROTOCOL;
Trigger
Initiates the MMI. See the Trigger() function description.
Clear
Quiesces the MMI source. See the Clear()function description.
MinimumTriggerPeriod
Minimumintervalatwhichtheplatformcansettheperiod. Amaximumisnotspecified. Thatis,theMMinfras-
tructure code can emulate a maximum interval that is greater than the hardware capabilities by using software
emulation in the MM infrastructure code. Type EFI_MM_PERIOD is defined in “Related Definitions” below.
TheEFI_MM_CONTROL_PROTOCOL is produced by a runtime driver. It provides an abstraction of the platform
hardware that generates an MMI. There are often I/O ports that, when accessed, will generate the MMI. Also, the
hardware optionally supports the periodic generation of these signals.
//***********************************************\*
// EFI_MM_PERIOD
typedef UINTN EFI_MM_PERIOD;
Note:The-period-is-in-increments-of-10-ns.
IV-5.4. MM Control Protocol IV-68UEFI Platform Initialization Specification, Release 1.8
IV-5.4.2 EFI_MM_CONTROL_PROTOCOL.Trigger()
Summary
Invokes MMI activation from either the preboot or runtime environment.
Prototype
typedef
(EFIAPI \*EFI_MM_ACTIVATE) (
IN CONST *EFI_MM_CONTROL_PROTOCOL* *\*This* ,
IN OUT UINT8 *\*CommandPort* OPTIONAL,
IN OUT UINT8 *\*DataPort* OPTIONAL,
IN BOOLEAN *Periodic* OPTIONAL,
IN UINTN *ActivationInterval* OPTIONAL
);
This
TheEFI_MM_CONTROL_PROTOCOL instance.
CommandPort
The value written to the command port; this value corresponds to the SwMmiInputValue in theRegisterContext
parameter for the Register() function in the EFI_MM_SW_DISPATCH_PROTOCOL and in the Contextparam-
eter in the call to the DispatchFunction , seeMM Software Dispatch Protocol .
DataPort
Thevaluewrittentothedataport;thisvaluecorrespondstothe DataPort memberinthe CommBuffer parameter
in the call to the DispatchFunction , seeMM Software Dispatch Protocol .
Periodic
Optional mechanism to engender a periodic stream.
ActivationInterval
Optional parameter to repeat at this period one time or, if the PeriodicBoolean is set, periodically.
This function generates an MMI.
EFI_SUCCESS The MMI has been engendered.
EFI_DEVICE_ERROR The timing is unsupported.
EFI_INVALID_PARAMETER The activation period is unsupported.
EFI_INVALID_PARAMETER The last periodic activation has not been cleared.
EFI_NOT_STARTED The MM base service has not been initialized.
IV-5.4. MM Control Protocol IV-69UEFI Platform Initialization Specification, Release 1.8
IV-5.4.3 EFI_MM_CONTROL_PROTOCOL.Clear()
Summary
Clears any system state that was created in response to the Trigger() call.
Prototype
typedef
(EFIAPI *EFI_MM_DEACTIVATE) (
IN CONST *EFI_MM_CONTROL_PROTOCOL *This,
IN BOOLEAN Periodic OPTIONAL
);
This
Periodic
ThisfunctionacknowledgesandcausesthedeassertionoftheMMIactivationsource.thatwasinitiatedbyapreceding
Triggerinvocation.
The results of this function update the software state of the communication infrastructure in the runtime code, but
it is ignorable from the perspective of the hardware state, though. This distinction stems from the fact that many
implementations clear the hardware acknowledge in the MM-resident infrastructure itself and may also have other
actionsusingthatsameactivationhardwaregeneratedbyMMDrivers. Thisclear-inMMdistinctionalsoavoidshaving
the possible pathology of an asynchronous MMI being received in the time window between the RSM instruction (or
other means of exiting MM) that followed the flows engendered by the Triggerand the subsequent non-MM resident
runtime driver code invocation of the Clear.
EFI_SUCCESS The MMI has been engendered
EFI_DEVICE_ERROR The source could not be cleared
EFI_INVALID_PARAMETER The service did not support the Periodic input argument
IV-5.5 MM Configuration Protocol
IV-5.5.1 EFI_MM_CONFIGURATION_PROTOCOL
Summary
Reports the portions of MMRAM regions which cannot be used for the MMRAM heap.
GUID
#define EFI_MM_CONFIGURATION_PROTOCOL_GUID \
{ 0x26eeb3de, 0xb689, 0x492e, 0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 }
Prototype
IV-5.5. MM Configuration Protocol IV-70UEFI Platform Initialization Specification, Release 1.8
typedef struct _EFI_MM_CONFIGURATION_PROTOCOL {
EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions;
EFI_MM_REGISTER_MM_ENTRY RegisterMmEntry;
Members
MmramReservedRegions
A pointer to an array MMRAM ranges used by the initial MM Entry Point code.
RegisterMmEntry
This protocol is a mandatory protocol published by a DXE CPU driver to indicate which areas within MMRAM are
reserved for use by the CPU for any purpose, such as stack, save state or MM Entry Point.
TheMmramReservedRegions pointstoanarrayofoneormore EFI_MM_RESERVED_MMRAM_REGION structures,
with the last structure having the MmramReservedSize set to 0. An empty array would contain only the last structure.
TheRegisterMmEntry() function allows the MM IPL DXE driver to register the MM Foundation entry point with the
MM entry vector code.
typedef struct \_EFI_MM_RESERVED_MMRAM_REGION {
EFI_PHYSICAL_ADDRESS MmramReservedStart;
UINT64 MmramReservedSize;
} EFI_MM_RESERVED_MMRAM_REGION;
MmramReservedStart
Starting address of the reserved MMRAM area, as it appears while MMRAM is open. Ignored if MmramRe-
servedSize is 0.
MmramReservedSize
Number of bytes occupied by the reserved MMRAM area. A size of zero indicates the last MMRAM area.

IV-5.5.2 EFI_MM_CONFIGURATION_PROTOCOL.RegisterMmEntry()
Summary
Register the MM Foundation entry point.
Prototype
typedef
(EFIAPI \*EFI_MM_REGISTER_MM_ENTRY) (
IN CONST EFI_MM_CONFIGURATION_PROTOCOL *This,
IN EFI_MM_ENTRY_POINT MmEntryPoint
)
This
IV-5.5. MM Configuration Protocol IV-71UEFI Platform Initialization Specification, Release 1.8
IV-5.6 DXE MM Ready to Lock Protocol
EFI_DXE_MM_READY_TO_LOCK_PROTOCOL
Summary
Indicates that MM is about to be locked.
GUID
#define EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID \
{ 0x60ff8964, 0xe906, 0x41d0, 0xaf, 0xed, 0xf2, 0x41, 0xe9, 0x74, 0xe0, 0x8e}
Prototype
NULL
This protocol is a mandatory protocol published by PI platform code.
Thisprotocolintandemwiththe EndofDXEEven tfacilitatestransitionoftheplatformfromtheenvironmentwhereall
ofthecomponentsareundertheauthorityoftheplatformmanufacturertotheenvironmentwherethirdpartyextensible
modules such as UEFI drivers and UEFI applications are executed.
The protocol is published immediately after signaling of the End of DXE Event .
PI modules that need to lock or protect their resources in anticipation of the invocation of 3rd party extensible mod-
ules should register for notification on installation of this protocol and effect the appropriate protections in their no-
tification handlers. For example, PI platform code may choose to use notification handler to lock MM by invoking
EFI_MM_ACCESS_PROTOCOL.Lock() function.
IV-5.7 MM Communication Protocol
IV-5.7.1 EFI_MM_COMMUNICATION_PROTOCOL
Summary
This protocol provides a means of communicating between drivers outside of MM and MMI handlers inside of MM.
GUID
#define EFI_MM_COMMUNICATION_PROTOCOL_GUID \
{ 0xc68e d8e2, 0x9dc6, 0x4cbd, 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 }
IV-5.6. DXE MM Ready to Lock Protocol IV-72UEFI Platform Initialization Specification, Release 1.8
Prototype
typedef struct \_EFI_MM_COMMUNICATION_PROTOCOL {
EFI_MM_COMMUNICATE *Communicate;*
} EFI_MM_COMMUNICATION_PROTOCOL;
Members
Communicate
Sends/receives a message for a registered handler. See the Communicate() function description.
This protocol provides runtime services for communicating between DXE drivers and a registered MMI handler.
IV-5.7.2 EFI_MM_COMMUNICATION_PROTOCOL.Communicate()
Summary
Communicates with a registered handler.
Prototype
typedef
(EFIAPI *EFI_MM_COMMUNICATE) (
IN CONST *EFI_MM_COMMUNICATION_PROTOCOL *This,
IN OUT VOID *CommBuffer,
IN OUT UINTN *CommSize OPTIONAL
);
This
TheEFI_MM_COMMUNICATION_PROTOCOL instance.
Pointer to the buffer to convey into MMRAM.
CommSize
Thesizeofthedatabufferbeingpassedin. Onexit,thesizeofdatabeingreturned. Zeroifthehandlerdoesnot
wish to reply with any data. This parameter is optional and may be NULL.
This function provides a service to send and receive messages from a registered UEFI service. The
EFI_MM_COMMUNICATION_PROTOCOL driver is responsible for doing any of the copies such that the data lives
in boot-service-accessible RAM.
A given implementation of the EFI_MM_COMMUNICATION_PROTOCOL may choose to use the
EFI_MM_CONTROL_PROTOCOL for effecting the mode transition, or it may use some other method. The
agent invoking the communication interface at runtime may be virtually mapped. The MM infrastructure code and
handlers,ontheotherhand,executeinphysicalmode. Asaresult,thenon-MMagent,whichmaybeexecutinginthe
virtual-mode OS context as a result of an OS invocation of the UEFI SetVirtualAddressMap() service, should use a
contiguous memory buffer with a physical address before invoking this service. If the virtual address of the buffer is
used, the MM Driver may not know how to do the appropriate virtual-to-physical conversion.
To avoid confusion in interpreting frames, the CommunicateBuffer parameter should always begin with
EFI_MM_COMMUNICATE_HEADER , which is defined in “Related Definitions” below. The header data is manda-
tory for messages sent into the MM agent.
IV-5.7. MM Communication Protocol IV-73UEFI Platform Initialization Specification, Release 1.8
IftheCommSize parameterisomittedthe MessageLength fieldinthe EFI_MM_COMMUNICATE_HEADER ,incon-
junction with the size of the header itself, can be used to ascertain the total size of the communication payload. If the
MessageLength is zero, or too large for the MM implementation to manage, the MM implementation must update the
MessageLength to reflect the size of the Databuffer that it can tolerate.
IftheCommSize parameterispassedintothecall,buttheintegeritpointsto,hasavalueof0,thenthismustbeupdated
to reflect the maximum size of the CommBuffer that the implementation can tolerate.
Once inside of MM, the MM infrastructure will call all registered handlers with the same HandlerType as the GUID
specified by HeaderGuid and theCommBuffer pointing to Data.
This function is not reentrant.
Thestandardheaderisusedatthebeginningofthe EFI_MM_INITIALIATION_HEADER structureduringMMinitial-
ization. See “Related Definitions” below for more information.
} EFI_MM_COMMUNICATE_HEADER;
HeaderGuid
Allows for disambiguation of the message format. Type EFI_GUID is defined in InstallProtocolInterface() in
the UEFI Specification.
MessageLength
Describes the size of Data(in bytes) and does not include the size of the header..
Data
Designates an array of bytes that is MessageLength in size.
EFI_MM_COMMUNICATE_HEADER Header;
EFI_SYSTEM_TABLE *SystemTable;
} EFI_MM_INITIALIZATION_HEADER;
#define EFI_MM_INITIALIZATION_GUID \
0x99be0d8f, 0x3548, 0x48aa, {0xb5, 0x77, 0xfc, 0xfb, 0xa5, 0x6a, 0x67, 0xf7}}
Header
AstandardMMcommunicationbufferheader,where HeaderGuid issettoEFI_MM_INITIALIZATION_GUID
.
A pointer to the UEFI System Table. As with DXE driver initialization, there is no guarantee that the entries in
this structure which rely on architectural protocols are implemented at the time when this event is generated.
EFI_SUCCESS The message was successfully posted
EFI_INVALID_PARAMETER The buffer was NULL
EFI_BAD_BUFFER_SIZE The buffer is too large for the MM implementation If this error is returned the MessageLength field
in the CommBuffer header or the integer pointed by CommSize are updated to reflect the maximum
payloadsizetheimplementationcanaccommodateSeethefunctiondescriptionaboveformoredetails
EFI_ACCESS_DENIED The CommunicateBuffer parameter or CommSize parameter if not omitted are in address range that
cannot be accessed by the MM environment
IV-5.7. MM Communication Protocol IV-74UEFI Platform Initialization Specification, Release 1.8
IV-5.7.3 EFI_MM_COMMUNICATION2_PROTOCOL
Summary
This protocol provides a means of communicating between drivers outside of MM and MMI handlers inside of MM,
in a way that hides the implementation details regarding whether traditional or standalone MM is being used.
GUID
#define EFI_MM_COMMUNICATION2_PROTOCOL_GUID \
{ 0x378daedc, 0xf06b, 0x4446, 0x83, 0x14, 0x40, 0xab, 0x93, 0x3c, 0x87, 0xa3 }
Prototype
typedef struct _EFI_MM_COMMUNICATION2_PROTOCOL {
EFI_MM_COMMUNICATE2 Communicate;
} EFI_MM_COMMUNICATION2_PROTOCOL;
Members
IV-5.7.4 EFI_MM_COMMUNICATION2_PROTOCOL.Communicate()
Summary
Prototype
typedef
(EFIAPI *EFI_MM_COMMUNICATE2) (
IN CONST EFI_MM_COMMNICATION2_PROTOCOL *This,
IN OUT VOID *CommBufferPhysical,
IN OUT VOID *CommBufferVirtual,
);
This
The EFI_MM_COMMUNICATION2_PROTOCOL instance.
Commbufferphysical
Physical address of the buffer to convey into MMRAM.
Commbuffervirtual
Virtual address of the buffer to convey into MMRAM.
Commsize
IV-5.7. MM Communication Protocol IV-75UEFI Platform Initialization Specification, Release 1.8
Usage is identical to EFI_MM_COMMUNICATION_PROTOCOL.Communicate() except for the notes below:
•Insteadofpassingjustthephysicaladdressviathe CommBuffer parameter,thecallermustpassboththephysical
and the virtual addresses of the communication buffer.
•Ifnovirtualremappinghastakenplace,thephysicaladdresswillbeequaltothevirtualaddress,andsothecaller
is required to pass the same value for both parameters.

);
This
Commsize
EFI_INVALID_PARAMETER The CommBuffer parameters do not refer to the same location in memory
IV-5.7. MM Communication Protocol IV-76CHAPTER
SIX
PI PEI PPIS
IV-6.1 MM Access PPI
IV-6.1.1 EFI_PEI_MM_ACCESS_PPI
Summary
This PPI is used to control the visibility of the MMRAM on the platform.
GUID
#define EFI_PEI_MM_ACCESS_PROTOCOL_GUID { \\
0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 } \
}
typedef struct _EFI_PEI_MM_ACCESS_PPI {
EFI_PEI_MM_OPEN Open;
EFI_PEI_MM_CLOSE Close;
EFI_PEI_MM_LOCK Lock;
EFI_PEI_MM_CAPABILITIES GetCapabilities;
BOOLEAN LockState;
BOOLEAN OpenState;
} EFI_PEI_MM_ACCESS_PPI;
Open
Close
Closes th MMRAM. See the Close()function description.
Lock
LockState
OpenState
IV-77UEFI Platform Initialization Specification, Release 1.8
TheEFI_PEI_MM_ACCESS_PPI abstracts the location and characteristics of MMRAM. The principal functionality
found in the memory controller includes the following:
•Shrouding the MMRAM to all but the MM agents, or the “closed” state
•Preserving the system integrity, or “locking” the MMRAM, such that the settings cannot be perturbed by either
boot service or runtime agents
IV-6.1.2 EFI_PEI_MM_ACCESS_PPI.Open()
Summary
Opens the* MMRAM area to be accessible by a PEIM.
Prototype
typedef
(EFIAPI *EFI_PEI_MM_OPEN) (
IN PEI_MM_ACCESS_PPI *This,
IN UINTN DescriptorIndex
);
This
TheEFI_PEI_MM_ACCESS_PPI instance.
DescriptorIndex
The region of MMRAM to Open.
IV-6.1. MM Access PPI IV-78UEFI Platform Initialization Specification, Release 1.8
IV-6.1.3 EFI_PEI_MM_ACCESS_PPI.Close()
Summary
Prototype
typedef
(EFIAPI EFI_PEI_MM_CLOSE)(
IN EFI_PEI_MM_ACCESS_PPI *This
);
This
IV-6.1.4 EFI_PEI_MM_ACCESS_PPI.Lock()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_MM_LOCK) (
);
IV-6.1. MM Access PPI IV-79UEFI Platform Initialization Specification, Release 1.8
This
The region of MMRAM to Lock.
IV-6.1.5 EFI_PEI_MM_ACCESS_PPI.GetCapabilities()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_MM_CAPABILITIES) (
IN CONST EFI_PEI_MM_ACCESS_PPI *This,
);
This
MmramMap
EFI_MMRAM_DESCRIPTORs
This function describes the MMRAM regions.
This data structure forms the contract between the MM_ACCESS andMM_IPL drivers. There is an ambiguity when
any MMRAM region is remapped. For example, on some chipsets, some MMRAM regions can be initialized at one
physical address but is later accessed at another processor address. There is currently no way for the MM IPL driver
to know that it must use two different addresses depending on what it is trying to do. As a result, initial configuration
IV-6.1. MM Access PPI IV-80UEFI Platform Initialization Specification, Release 1.8
and loading can use the physical address PhysicalStart while MMRAM is open. However, once the region has been
closed and needs to be accessed by agents in MM, the CpuStart address must be used.
This PPI publishes the available memory that the chipset can shroud for the use of installing code.
Theseregionsservethedualpurposeofdescribingwhichregionshavebeenopen,closed,orlocked. Inaddition,these
regions may include overlapping memory ranges, depending on the chipset implementation. The latter might include
a chipset that supports T-SEG, where memory near the top of the physical DRAM can be allocated for MMRAM too.
The key thing to note is that the regions that are described by the PPI are a subset of the capabilities of the hardware.
EFI_BUFFER_TOO_SMALL The MmramMap parameter was too small The current buffer size
needed to hold the memory map is returned in MmramMapSize
IV-6.2 MM Control PPI
IV-6.2.1 EFI_PEI_MM_CONTROL_PPI
Summary
This PPI is used initiate synchronous MMI activations. This PPI could be published by a processor driver to abstract
the MMI IPI or a driver which abstracts the ASIC that is supporting the APM port.
BecauseofthepossibilityofperformingMMIIPItransactions,theabilitytogeneratethiseventfromaplatformchipset
agent is an optional capability for both IA-32 and x64-based systems.
GUID
#define EFI_PEI_MM_CONTROL_PPI_GUID { \\
0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 } \
}
typedef struct _EFI_PEI_MM_CONTROL_PPI {
EFI_PEI_MM_ACTIVATE Trigger;
EFI_PEI_MM_DEACTIVATE Clear;
} EFI_PEI_MM_CONTROL_PPI;
Trigger
Initiates the MMI activation. See the Trigger() function description.
Clear
Quiesces the MMI activation. See the Clear()function description.
TheEFI_PEI_MM_CONTROL_PPI is produced by a PEIM. It provides an abstraction of the platform hardware that
generatesanMMI.ThereareoftenI/Oportsthat,whenaccessed,willgeneratetheMMI.Also,thehardwareoptionally
supports the periodic generation of these signals.
IV-6.2. MM Control PPI IV-81UEFI Platform Initialization Specification, Release 1.8
IV-6.2.2 EFI_PEI_MM_CONTROL_PPI.Trigger()
Summary
Invokes PPI activation from the PI PEI environment.
Prototype
typedef
(EFIAPI *EFI_PEI_MM_ACTIVATE) (
IN CONST EFI_PEI_MM_CONTROL_PPI *This,
IN OUT INT8 *ArgumentBuffer OPTIONAL,
IN OUT UINTN *ArgumentBufferSize OPTIONAL,
IN BOOLEAN Periodic OPTIONAL,
IN UINTN ActivationInterval OPTIONAL
);
This
TheEFI_PEI_MM_CONTROL_PPI instance.
ArgumentBuffer
The value passed to the MMI handler. This value corresponds to the SwMmiInputValue in theRegisterContext

Summary
Prototype
typedef
);
This
parameter for the Register() function in the EFI_MM_SW_DISPATCH_PROTOCOL and in the Context param-
eter in the call to the DispatchFunction , see section 6.2.
ArgumentBufferSize
The size of the data passed in ArgumentBuffer orNULLifArgumentBuffer isNULL.
Periodic
IV-6.2. MM Control PPI IV-82UEFI Platform Initialization Specification, Release 1.8
IV-6.2.3 EFI_PEI_MM_CONTROL_PPI.Clear()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_MM_DEACTIVATE) (
);
This
Periodic
ThisfunctionacknowledgesandcausesthedeassertionoftheMMIactivationsource. thatwasinitiatedbyapreceding
Triggerinvocation. The results of this function update the software state of the communication infrastructure in the
PEIM code, but it is ignorable from the perspective of the hardware state, though. This distinction stems from the
factthatmanyimplementationsclearthehardwareacknowledgeintheMM-residentinfrastructureitselfandmayalso
have other actions using that same activation hardware generated by MM drivers. This clear-in-MM distinction also
avoids having the possible pathology of an asynchronous MMI being received in the time window between the RSM
instruction(orothermeansofexitingMM)followedtheflowsengenderedbytheTriggerandthesubsequentnon-MM
resident PEIM code invocation of the Clear.
IV-6.3 EFI DELAYED DISPATCH PPI (Required)
IV-6.3.1 EFI_DELAYED_DISPATCH_PPI (Required)
Summary
Provide timed event service in PEI
GUID
#define EFI_DELAYED_DISPATCH_PPI_GUID \\
{ \
0x869c711d, 0x649c, 0x44fe, { 0x8b, 0x9e, 0x2c, 0xbb, 0x29,
0x11, 0xc3, 0xe6} } \
}
IV-6.3. EFI DELAYED DISPATCH PPI (Required) IV-83UEFI Platform Initialization Specification, Release 1.8
struct _EFI_DELAYED_DISPATCH_PPI {
EFI_DELAYED_DISPATCH_REGISTER Register;
EFI_DELAYED_DISPATCH WAIT_ON_EVENT WaitOnEvent;
};
Register
Register a callback to be called after a minimum delay has occurred.
WaitOnEvent
Pausecurrentprocessandallowothercomponentstocontinuetodispatchuntilallentrieswithspecified“Unique
ID” have completed.
Define a time based event mechanism for PEI (Pei Delayed Dispatch):
Eliminate spin loops for timing. Instead of blocking for 50 or 100 ms, the driver would request callbacks after 50ms
(or100ms)andallowotherPEIM’stodispatch. EachloopthroughthePEIdispatcherwillattempttodispatcheachof
the queued delayed dispatch requests.
Method to schedule a callback after a minimum delay, not a real time callback. Maintains a 64 bit “State” for use by
the callback.
PPI has only one function - Register, to register a function to be called after the required delay with the current value
of “State”.
IV-6.3.2 EFI_DELAYED_DISPATCH_PPI.Register()
Summary
Prototype
typedef
(EFIAPI *EFI_DELAYED_DISPATCH_REGISTER)(
IN EFI_DELAYED_DISPATCH_PPI *This,
IN EFI_DELAYED_DISPATCH_FUNCTION Function,
IN UINT64 Context,
IN EFI_GUID *UniqueId OPTIONAL,
IN UINT32 Delay
);
This
Pointer to the EFI_DELAYED_DISPATCH_PPI instance.
Function
Function to call back. The function prototype is defined in the “Related Definitions” below.
Context
Context data.
IV-6.3. EFI DELAYED DISPATCH PPI (Required) IV-84UEFI Platform Initialization Specification, Release 1.8
UniqueId
GUID for identifying the delayed dispatch request.
Delay
Delay interval. This parameter describes a multiple of microseconds.
This function is invoked by a PEIM to have a handler returned. The handler will be invoked after at the minimum of
specified Delay. Note that if the Register service is called with a Delayof zero, then the handler will be dispatched
immediately. If the UniqueId is specified, this request will be marked with GUID for WaitOnEvent usage.
// EFI_DELAYED_DISPATCH_FUNCTION
typedef
VOID
(EFIAPI *EFI_DELAYED_DISPATCH_FUNCTION)(
IN OUT UINT64 *Context,
OUT UINT32 *NewDelay
);
Context
Pointer to Context Data. Can be updated by routine.
NewDelay
The new delay in us. Leave at 0 to unregister this callback. Upon return, if NewDelay is 0, the function is
unregistered. If NewDelay is not zero, this routine will be called again after the new delay period.
Status Codes Returned (EFI_DELAYED_DISPATCH_PPI.Register)
EFI_SUCCESS Function successfully invoked
EFI_INVALID_PARAMETER One of the arguments is not supported
EFI_OUT_OF_RESOURCES No more entries
IV-6.3.3 EFI_DELAYED_DISPATCH_PPI.WaitOnEvent()
Summary
Pause current process and allow other components to continue to dispatch until all entries with specified “Unique ID”
have completed.
Prototype
typedef
(EFIAPI *EFI_DELAYED_DISPATCH_WAIT ON EVENT)(
IN EFI_GUID UniqueId
);
IV-6.3. EFI DELAYED DISPATCH PPI (Required) IV-85UEFI Platform Initialization Specification, Release 1.8
This
UniqueId
Delayed dispatch request ID the caller will wait on.
This function is invoked by a PEIM to wait until all specified UniqueId events have been dispatched. The other events
will continue to dispatch while this process is being paused.
IV-6.4 MM Configuration PPI
IV-6.4.1 EFI_PEI_MM_CONFIGURATION_PPI
Summary
GUID
#define EFI_PEI_MM_CONFIGURATION_PPI_GUID { \
0xc109319, 0xc149, 0x450e, 0xa3, 0xe3, 0xb9, 0xba, 0xdd,
0x9d, 0xc3, 0xa4 \
}
typedef struct _EFI_PEI_MM_CONFIGURATION_PPI {
EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions* ;
EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry;
} EFI_PEI_MM_CONFIGURATION_PPI;
Members
A pointer to an array MMRAM ranges used by the initial MM entry code.
ThisPPIisaPPIpublishedbyaCPUPEIMtoindicatewhichareaswithinMMRAMarereservedforusebytheCPU
for any purpose, such as stack, save state or MM entry point. If a platform chooses to let a CPU PEIM do MMRAM
relocation, this PPI must be produced by this CPU PEIM.
TheRegisterMmEntry() function allows the MM IPL PEIM to register the MM Foundation entry point with the MM
entry vector code.
IV-6.4. MM Configuration PPI IV-86UEFI Platform Initialization Specification, Release 1.8
IV-6.4.2 EFI_PEI_MM_CONFIGURATION_PPI.RegisterMmEntry()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY) (
IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This,
)
This
TheEFI_PEI_MM_CONFIGURATION_PPI instance.
IV-6.5 MM Communication PPI
IV-6.5.1 EFI_PEI_MM_COMMUNICATION_PPI
Summary
ThisPPIprovidesameansofcommunicatingbetweendriversoutsideofMMandMMIhandlersinsideofMMinPEI
phase.
GUID
#define EFI_PEI_MM_COMMUNICATION_PPI_GUID { \
0xae933e1c, 0xcc47, 0x4e38, \
{ 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } \
}
typedef struct _EFI_PEI_MM_COMMUNICATION_PPI {
EFI_PEI_MM_COMMUNICATE Communicate;
} EFI_PEI_MM_COMMUNICATION_PPI;
Members
IV-6.5. MM Communication PPI IV-87UEFI Platform Initialization Specification, Release 1.8

This
Summary
phase.
GUID
}
Members
This PPI provides services for communicating between PEIM and a registered MMI handler.
IV-6.5.2 EFI_PEI_MM_COMMUNICATION_PPI.Communicate()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_MM_COMMUNICATE) (
IN CONST EFI_PEI_MM_COMMUNICATION_PPI *This,
IN OUT UINTN *CommSize
);
This
TheEFI_PEI_MM_COMMUNICATION_PPI instance.
CommSize
wish to reply with any data.
This function provides a service to send and receive messages from a registered PEI service. The
EFI_PEI_MM_COMMUNICATION_PPI driver is responsible for doing any of the copies such that the data lives
in PEI-service-accessible RAM.
A given implementation of the EFI_PEI_MM_COMMUNICATION_PPI may choose to use the
EFI_MM_CONTROL_PPI for effecting the mode transition, or it may use some other method.
The agent invoking the communication interface must be physical/virtually 1:1 mapped.
To avoid confusion in interpreting frames, the CommBuffer parameter should always begin with
EFI_MM_COMMUNICATE_HEADER . The header data is mandatory for messages sent into the MM agent.
specified by HeaderGuid and theCommBuffer pointing to Data. This function is not reentrant.
IV-6.5. MM Communication PPI IV-88CHAPTER
SEVEN
MM CHILD DISPATCH PROTOCOLS
IV-7.1 Introduction
The services described in this chapter describe a series of protocols that abstract installation of handlers for a chipset-
specific MM design. These services are all scoped to be usable only from within MMRAM.
•EFI_MM_SW_DISPATCH_PROTOCOL
•EFI_MM_SX_DISPATCH_PROTOCOL
•EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL
•EFI_MM_USB_DISPATCH_PROTOCOL
•EFI_MM_GPI_DISPATCH_PROTOCOL
•EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL
•EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL
•EFI_MM_IO_TRAP_DISPATCH_PROTOCOL
MM Drivers which create instances of these protocols should install an instance of the
EFI_DEVICE_PATH_PROTOCOL on the same handle. This allows other MM Drivers to distinguish between
multiple instances of the same child dispatch protocol
IV-7.2 MM Software Dispatch Protocol
IV-7.2.1 EFI_MM_SW_DISPATCH_PROTOCOL
Summary
Provides the parent dispatch service for a given MMI source generator.
GUID
#define EFI_MM_SW_DISPATCH_PROTOCOL_GUID \
{ 0x18a3c6dc, 0x5eea, 0x48c8, \
0xa1, 0xc1, 0xb5, 0x33, 0x89, 0xf9, 0x89, 0x99}
IV-89UEFI Platform Initialization Specification, Release 1.8
typedef struct _EFI_MM_SW_DISPATCH_PROTOCOL {
EFI_MM_SW_REGISTER Register;
EFI_MM_SW_UNREGISTER UnRegister;
UINTN MaximumSwiValue;
} EFI_MM_SW_DISPATCH_PROTOCOL;
Register
Installs a child service to be dispatched by this protocol. See the Register() function description.
UnRegister
Removes a child service dispatched by this protocol. See the UnRegister() function description.
MaximumSwiValue
A read-only field that describes the maximum value that can be used in the
EFI_MM_SW_DISPATCH_PROTOCOL.Register() service.
TheEFI_MM_SW_DISPATCH_PROTOCOL provides the ability to install child handlers for the given software.
These handlers will respond to software-generated MMI,s, and the maximum software-generated MMI value in the
EFI_MM_SW_REGISTER_CONTEXT is denoted by MaximumSwiValue .
IV-7.2.2 EFI_MM_SW_DISPATCH_PROTOCOL.Register()
Summary
Prototype
typedef
(EFIAPI *EFI_MM_SW_REGISTER) (
IN CONST EFI_MM_SW_DISPATCH_PROTOCOL *This,
IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction,
IN EFI_MM_SW_REGISTER_CONTEXT *RegisterContext,
OUT EFI_HANDLE *DispatchHandle
);
This
Pointer to the EFI_MM_SW_DISPATCH_PROTOCOL instance.
DispatchFunction
Function to register for handler when the specified software MMI is generated. Type
EFI_MM_HANDLER_ENTRY_POINT is defined in “Related Definitions” in MmiHandlerRegister() .
RegisterContext
Pointer to the dispatch function’s context. The caller fills in this context before calling the Register() function
to indicate to the Register() function the software MMI input value for which the dispatch function should be
invoked. Type EFI_MM_SW_REGISTER_CONTEXT is defined in “Related Definitions” below.
Handle generated by the dispatcher to track the function instance. Type EFI_HANDLE is defined in InstallPro-
tocolInterface() in the UEFI Specification.
IV-7.2. MM Software Dispatch Protocol IV-90UEFI Platform Initialization Specification, Release 1.8
This service registers a function ( DispatchFunction ) which will be called when the software MMI source specified
byRegisterContext->SwMmiCpuIndex is detected. On return, DispatchHandle contains a unique handle which may
be used later to unregister the function using UnRegister().
IfSwMmiInputValue is set to(UINTN) -1 then a unique value will be assigned and returned in the structure. If no
unique value can be assigned then EFI_OUT_OF_RESOURCES will be returned.
TheDispatchFunction will be called with Contextset to the same value as was passed into this function in Register-
ContextandwithCommBuffer (andCommBufferSize )pointingtoaninstanceof EFI_MM_SW_CONTEXT indicating
the index of the CPU which generated the software MMI.
// EFI_MM_SW_CONTEXT
UINTN SwMmiCpuIndex;
UINT8 CommandPort;
UINT8 DataPort;
} EFI_MM_SW_CONTEXT;
SwMmiCpuIndex
The 0-based index of the CPU which generated the software MMI.
This value corresponds directly to the CommandPort parameter used in the call to Trigger() , seeMM Control
Protocol.
DataPort
Thisvaluecorrespondsdirectlytothe DataPort parameterusedinthecallto Trigger() ,seeMMControlProtocol .
// EFI_MM_SW_REGISTER_CONTEXT
UINTN SwMmiInputValue;
} EFI_MM_SW_REGISTER_CONTEXT;
SwMmiInputValue
A number that is used during the registration process to tell the dispatcher which software input value to use to
invoke the given handler.
EFI_SUCCESS ThedispatchfunctionhasbeensuccessfullyregisteredandtheMMI
source has been enabled
EFI_DEVICE_ERROR The driver was unable to enable the MMI source
EFI_INVALID_PARAMETER RegisterContext is invalid The SW MMI input value is not within a
valid range or is already in use
EFI_OUT_OF_RESOURCES There is not enough memory system or SM to manage this child
EFI_OUT_OF_RESOURCES AuniquesoftwareMMIvaluecouldnotbeassignedforthisdispatch
IV-7.2. MM Software Dispatch Protocol IV-91UEFI Platform Initialization Specification, Release 1.8
IV-7.2.3 EFI_MM_SW_DISPATCH_PROTOCOL.UnRegister()
Summary
Unregisters a software service.
Prototype
typedef
(EFIAPI *EFI_MM_SW_UNREGISTER) (
IN EFI_HANDLE DispatchHandle
);
This
Handleoftheservicetoremove. Type EFI_HANDLE isdefinedin InstallProtocolInterface() intheUEFISpec-
This service removes the handler associated with DispatchHandle so that it will no longer be called in response to a
software MMI.
EFI_SUCCESS The service has been successfully removed.
EFI_INVALID_PARAMETER TheDispatchHandle was not valid.
IV-7.3 MM Sx Dispatch Protocol
IV-7.3.1 EFI_MM_SX_DISPATCH_PROTOCOL
Summary
Provides the parent dispatch service for a given Sx-state source generator.
GUID
#define EFI_MM_SX_DISPATCH_PROTOCOL_GUID \
{ 0x456d2859, 0xa84b, 0x4e47, \
0xa2, 0xee, 0x32, 0x76, 0xd8, 0x86, 0x99, 0x7d }
typedef struct _EFI_MM_SX_DISPATCH_PROTOCOL {
EFI_MM_SX_REGISTER Register;
EFI_MM_SX_UNREGISTER UnRegister;
} EFI_MM_SX_DISPATCH_PROTOCOL;
IV-7.3. MM Sx Dispatch Protocol IV-92UEFI Platform Initialization Specification, Release 1.8
Register
TheEFI_MM_SX_DISPATCH_PROTOCOL provides the ability to install child handlers to respond to sleep state re-
lated events.
IV-7.3.2 EFI_MM_SX_DISPATCH_PROTOCOL.Register()
Summary
Provides the parent dispatch service for a given Sx source generator.
Prototype
typedef
(EFIAPI *EFI_MM_SX_REGISTER) (
IN CONST EFI_MM_SX_DISPATCH_PROTOCOL *This,

Register
Summary
Prototype
typedef
IN CONST EFI_MM_SX_REGISTER_CONTEXT* *RegisterContext,
);
This
Pointer to the EFI_MM_SX_DISPATCH_PROTOCOL instance.
Function to register for handler when the specified sleep state event occurs. Type
EFI_MM_HANDLER_ENTRY_POINT is defined in “Related Definitions” in MmiHandlerRegister() in
the MMST.
Pointertothedispatchfunction’scontext. Thecallerinfillsthiscontextbeforecallingthe Register() functionto
indicate to the Register() function on which Sx state type and phase the caller wishes to be called back.
Handle of the dispatch function, for when interfacing with the parent Sx state MM Driver. Type EFI_HANDLE
is defined in InstallProtocolInterface() in the UEFI Specification.
This service registers a function ( DispatchFunction ) which will be called when the sleep state event specified by
RegisterContext isdetected. Onreturn, DispatchHandle containsauniquehandlewhichmaybeusedlatertounregister
the function using UnRegister() .
Contextand withCommBuffer andCommBufferSize set to NULL and 0 respectively
Contextand withCommBuffer andCommBufferSize set to NULL and 0 respectively.
IV-7.3. MM Sx Dispatch Protocol IV-93UEFI Platform Initialization Specification, Release 1.8
// EFI_MM_SX_REGISTER_CONTEXT
EFI_SLEEP_TYPE Type;
EFI_SLEEP_PHASE Phase;
} EFI_MM_SX_REGISTER_CONTEXT;
// EFI_SLEEP_TYPE
SxS0,
SxS1,
SxS2,
SxS3,
SxS4,
SxS5,
EfiMaximumSleepType
} EFI_SLEEP_TYPE;
// EFI_SLEEP_PHASE
SxEntry,
SxExit,
EfiMaximumPhase
} EFI_SLEEP_PHASE;
EFI_UNSUPPORTED The Sx driver or hardware does not support that Sx Type Phase
EFI_DEVICE_ERROR The Sx driver was unable to enable the MMI source
EFI_INVALID_PARAMETER RegisterContextisinvalidTheICHNinputvalueisnotwithinavalid
range
IV-7.3.3 EFI_MM_SX_DISPATCH_PROTOCOL.UnRegister()
Summary
Unregisters an Sx-state service.
Prototype
typedef
(EFIAPI *EFI_MM_SX_UNREGISTER) (
IV-7.3. MM Sx Dispatch Protocol IV-94UEFI Platform Initialization Specification, Release 1.8
);
This
Thisserviceremovesthehandlerassociatedwith DispatchHandle sothatitwillnolongerbecalledinresponsetosleep
event.
IV-7.4 MM Periodic Timer Dispatch Protocol
IV-7.4.1 EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL
Summary
Provides the parent dispatch service for the periodical timer MMI source generator.
GUID
#define EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID \
{ 0x4cec368e, 0x8e8e, 0x4d71, \
0x8b, 0xe1, 0x95, 0x8c, 0x45, 0xfc, 0x8a, 0x53}
typedef struct _EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL {
EFI_MM_PERIODIC_TIMER_REGISTER Register;
EFI_MM_PERIODIC_TIMER_UNREGISTER UnRegister;
EFI_MM_PERIODIC_TIMER_INTERVAL GetNextShorterInterval;
} EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL;
Register
GetNextShorterInterval
Returns the next MMI tick period that is supported by the chipset. See the GetNextShorterInterval() function
IV-7.4. MM Periodic Timer Dispatch Protocol IV-95UEFI Platform Initialization Specification, Release 1.8
TheEFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL providestheabilitytoinstallchildhandlersforthegiven
event types.
IV-7.4.2 EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL.Register()
Summary
Prototype
typedef
(EFIAPI *EFI_MM_PERIODIC_TIMER_REGISTER) (
IN CONST EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This,
IN CONST EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT *RegisterContext,
);
This
Pointer to the EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL instance.
Function to register for handler when at least the specified amount of time has elapsed. Type
theMMST.
Pointer to the dispatch function’s context. The caller fills this context in before calling the Register() func-
tion to indicate to the Register() function the period at which the dispatch function should be invoked. Type
EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT is defined in “Related Definitions” below.
This service registers a function ( DispatchFunction ) which will be called when at least the amount of time specified
byRegisterContext has elapsed. On return, DispatchHandle contains a unique handle which may be used later to
unregister the function using UnRegister() .
TheDispatchFunction willbecalledwith Contextsettothesamevalueaswaspassedintothisfunctionin RegisterCon-
textandwithCommBuffer pointingtoaninstanceof EFI_MM_PERIODIC_TIMER_CONTEXT andCommBufferSize
pointing to its size.
// EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT
IV-7.4. MM Periodic Timer Dispatch Protocol IV-96UEFI Platform Initialization Specification, Release 1.8
UINT64 Period;
UINT64 MmiTickInterval;
} EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT;
Period
The minimum period of time in 100 nanosecond units that the child gets called. The child will be called back
after a time greater than the time Period.
MmiTickInterval
The period of time interval between MMIs. Children of this interface should use this field when registering for
periodic timer intervals when a finer granularity periodic MMI is desired.
Example: AchipsetsupportsperiodicMMIsonevery64msor2seconds. AchildwishestoscheduleaperiodicMMI
to fire on a period of 3 seconds. There are several ways to approach the problem:
The child may accept a 4 second periodic rate, in which case it registers with the following:
Period = 40000
MmiTickInterval = 20000
The resulting MMI will occur every 2 seconds with the child called back on every second MMI.
Note:The same result would occur if the child set MmiTickInterval = 0 .
The child may choose the finer granularity MMI (64 ms):
Period = 30000
MmiTickInterval = 640
The resulting MMI will occur every 64 ms with the child called back on every 47th MMI.
Note:The child driver should be aware that this will result in more MMIs occurring during system runtime, which
can negatively impact system performance.
typedef struct _EFI_MM_PERIODIC_TIMER_CONTEXT {
UINT64 ElapsedTime;
} EFI_MM_PERIODIC_TIMER_CONTEXT;
ElapsedTime
Theactualtimein100nanosecondunitselapsedsincelastcalled. Avalueof0indicatesanunknownamountof
time.
range
IV-7.4. MM Periodic Timer Dispatch Protocol IV-97UEFI Platform Initialization Specification, Release 1.8
IV-7.4.3 EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL.UnRegister()
Summary
Unregisters a periodic timer service.
Prototype
typedef
(EFIAPI *EFI_MM_PERIODIC_TIMER_UNREGISTER) (
);
This

time.
range
Summary
Prototype
typedef
);
This
Thisserviceremovesthehandlerassociatedwith DispatchHandle sothatitwillnolongerbecalledwhenthetimehas
elapsed.
IV-7.4.4 EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL.GetNextShorterInterval()
Summary
Returns the next MMI tick period that is supported by the chipset.
Prototype
typedef
(EFIAPI *EFI_MM_PERIODIC_TIMER_INTERVAL) (
IN OUT UINT64 **MmiTickInterval
);
This
Pointer to pointer of the next shorter MMI interval period that is supported by the child. This parameter works
as a get-first, get-next field. The first time that this function is called, *MmiTickInterval should be set to NULL
IV-7.4. MM Periodic Timer Dispatch Protocol IV-98UEFI Platform Initialization Specification, Release 1.8
to get the longest MMI interval. The returned *MmiTickInterval should be passed in on subsequent calls to get
the next shorter interval period until *MmiTickInterval = NULL .
This service returns the next MMI tick period that is supported by the device. The order returned is from longest to
shortest interval period.
EFI_SUCCESS The service returned successfully.
IV-7.5 MM USB Dispatch Protocol
IV-7.5.1 EFI_MM_USB_DISPATCH_PROTOCOL
Summary
Provides the parent dispatch service for the USB MMI source generator.
GUID
#define EFI_MM_USB_DISPATCH_PROTOCOL_GUID \
{ 0xee9b8d90, 0xc5a6, 0x40a2, \
0xbd, 0xe2, 0x52, 0x55, 0x8d, 0x33, 0xcc, 0xa1 }
typedef struct _EFI_MM_USB_DISPATCH_PROTOCOL {
EFI_MM_USB_REGISTER Register;
EFI_MM_USB_UNREGISTER UnRegister;
} EFI_MM_USB_DISPATCH_PROTOCOL;
Register
TheEFI_MM_USB_DISPATCH_PROTOCOL provides the ability to install child handlers for the given event types.
IV-7.5.2 EFI_MM_USB_DISPATCH_PROTOCOL.Register()
Summary
Prototype
typedef
(EFIAPI *EFI_MM_USB_REGISTER) (
IV-7.5. MM USB Dispatch Protocol IV-99UEFI Platform Initialization Specification, Release 1.8
IN CONST EFI_MM_USB_DISPATCH_PROTOCOL *This,
IN CONST EFI_MM_USB_REGISTER_CONTEXT *RegisterContext,
);
This
Pointer to the EFI_MM_USB_DISPATCH_PROTOCOL instance.
Function to register for handler when a USB-related MMI occurs. Type EFI_MM_HANDLER_ENTRY_POINT
is defined in “Related Definitions” in MmiHandlerRegister() in the MMST.
Pointertothedispatchfunction’scontext. Thecallerfillsthiscontextinbeforecallingthe Register() functionto
indicatetothe Register() functiontheUSBMMIsourceforwhichthedispatchfunctionshouldbeinvoked. Type
EFI_MM_USB_REGISTER_CONTEXT is defined in “Related Definitions” below.
tocolInterface() in the UEFISpecification.
This service registers a function ( DispatchFunction ) which will be called when the USB-related MMI specified by
RegisterContext hasoccurred. Onreturn, DispatchHandle containsauniquehandlewhichmaybeusedlatertounreg-
ister the function using UnRegister() .
Contextand withCommBuffer containing NULL and CommBufferSize containing zero.
// EFI_MM_USB_REGISTER_CONTEXT
EFI_USB_MMI_TYPE Type;
EFI_DEVICE_PATH_PROTOCOL *Device;
} EFI_MM_USB_REGISTER_CONTEXT;
Type
DescribeswhetherthischildhandlerwillbeinvokedinresponsetoaUSBlegacyemulationevent,suchasport-
trap on the PS/2* keyboard control registers, or to a USB wake event, such as resumption from a sleep state.
TypeEFI_USB_MMI_TYPE is defined below.
Device
ThedevicepathispartofthecontextstructureanddescribesthelocationoftheparticularUSBhostcontrollerin
thesystemforwhichthisregistereventwilloccur. Thislocationisimportantbecauseofthepossibleintegration
of several USB host controllers in a system. Type EFI_DEVICE_PATH is defined in the UEFI Specification.
// EFI_USB_MMI_TYPE
IV-7.5. MM USB Dispatch Protocol IV-100UEFI Platform Initialization Specification, Release 1.8
UsbLegacy,
UsbWake
} EFI_USB_MMI_TYPE;
EFI_INVALID_PARAMETER RegisterContextisinvalidTheICHNinputvalueisnotwithinvalid
range
EFI_OUT_OF_RESOURCES There is not enough memory system or MM to manage this child
IV-7.5.3 EFI_MM_USB_DISPATCH_PROTOCOL.UnRegister()
Summary
Unregisters a USB service.
Prototype
typedef
(EFIAPI *EFI_MM_USB_UNREGISTER) (
);
This
This service removes the handler associated with DispatchHandle so that it will no longer be called when the USB
event occurs.
EFI_SUCCESS The dispatch function has been successfully unregistered and the
MMI source has been disabled if there are no other registered child
dispatch functions for this MMI source
EFI_INVALID_PARAMETER The DispatchHandle was not valid
IV-7.5. MM USB Dispatch Protocol IV-101UEFI Platform Initialization Specification, Release 1.8
IV-7.6 MM General Purpose Input (GPI) Dispatch Protocol
IV-7.6.1 EFI_MM_GPI_DISPATCH_PROTOCOL
Summary
Provides the parent dispatch service for the General Purpose Input (GPI) MMI source generator.
GUID
#define EFI_MM_GPI_DISPATCH_PROTOCOL_GUID \
{ 0x25566b03, 0xb577, 0x4cbf, \
0x95, 0x8c, 0xed, 0x66, 0x3e, 0xa2, 0x43, 0x80 }
typedef struct _EFI_MM_GPI_DISPATCH_PROTOCOL {
EFI_MM_GPI_REGISTER Register;
EFI_MM_GPI_UNREGISTER UnRegister;
UINTN NumSupportedGpis;
} EFI_MM_GPI_DISPATCH_PROTOCOL;
Register
NumSupportedGpis
Denotes the maximum value of inputs that can have handlers attached.
TheEFI_MM_GPI_DISPATCH_PROTOCOL provides the ability to install child handlers for the given event types.
Several inputs can be enabled. This purpose of this interface is to generate an MMI in response to any of these inputs
having a true value provided.
IV-7.6.2 EFI_MM_GPI_DISPATCH_PROTOCOL.Register()
Summary
Registers a child MMI source dispatch function with a parent MM driver.
Prototype
typedef
(EFIAPI *EFI_MM_GPI_REGISTER) (
IN CONST EFI_MM_GPI_DISPATCH_PROTOCOL *This,
IN CONST EFI_MM_GPI_REGISTER_CONTEXT *RegisterContext,
);
IV-7.6. MM General Purpose Input (GPI) Dispatch Protocol IV-102UEFI Platform Initialization Specification, Release 1.8
This
Pointer to the EFI_MM_GPI_DISPATCH_PROTOCOL instance.
Function to register for handler when the specified GPI causes an MMI. Type
the MMST.
Pointertothedispatchfunction’scontext. Thecallerfillsinthiscontextbeforecallingthe Register() functionto
indicatetothe Register() functiontheGPIMMIsourceforwhichthedispatchfunctionshouldbeinvoked. Type
EFI_MM_GPI_REGISTER_CONTEXT is defined in “Related Definitions” below.
This service registers a function ( DispatchFunction ) which will be called when an MMI is generated because of one
ormoreoftheGPIsspecifiedby RegisterContext . Onreturn, DispatchHandle containsauniquehandlewhichmaybe

This
the MMST.
used later to unregister the function using UnRegister() .
Contextand with CommBuffer pointing to another instance of EFI_MM_GPI_REGISTER_CONTEXT describing the
GPIs which actually caused the MMI and CommBufferSize pointing to the size of the structure.
// EFI_MM_GPI_REGISTER_CONTEXT
UINT64 GpiNum;
} EFI_MM_GPI_REGISTER_CONTEXT;
GpiNum
A number from one of 2^64 possible GPIs that can generate an MMI. A 0 corresponds to logical GPI[0]; 1
corresponds to logical GPI[1]; and GpiNumof N corresponds to GPI[N], where N can span from 0 to 2^64-1.
EFI_INVALID_PARAMETER RegisterContext is invalid The GPI input value is not within valid
range
IV-7.6. MM General Purpose Input (GPI) Dispatch Protocol IV-103UEFI Platform Initialization Specification, Release 1.8
IV-7.6.3 EFI_MM_GPI_DISPATCH_PROTOCOL.UnRegister()
Summary
Unregisters a General Purpose Input (GPI) service.
Prototype
typedef
(EFIAPI *EFI_MM_GPI_UNREGISTER) (
);
This
This service removes the handler associated with DispatchHandle so that it will no longer be called when the GPI
triggers an MMI.
IV-7.7 MM Standby Button Dispatch Protocol
IV-7.7.1 EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL
Summary
Provides the parent dispatch service for the standby button MMI source generator.
GUID
#define EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL_GUID \
{ 0x7300c4a1, 0x43f2, 0x4017, \
0xa5, 0x1b, 0xc8, 0x1a, 0x7f, 0x40, 0x58, 0x5b }
typedef struct _EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL {
EFI_MM_STANDBY_BUTTON_REGISTER Register;
EFI_MM_STANDBY_BUTTON_UNREGISTER UnRegister;
} EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL;
IV-7.7. MM Standby Button Dispatch Protocol IV-104UEFI Platform Initialization Specification, Release 1.8
Register
TheEFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL provides the ability to install child handlers for the
given event types.
IV-7.7.2 EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL.Register()
Summary
Prototype
typedef
(EFIAPI *EFI_MM_STANDBY_BUTTON_REGISTER) (
IN CONST EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL *This,
IN EFI_MM_HANDLER_ENTRY_POINT* DispatchFunction,
IN EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT *RegisterContext,
);
This
Pointer to the EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL instance.
Function to register for handler when the standby button is pressed or released. Type
the MMST.
Pointer to the dispatch function’s context. The caller fills in this context before calling the register function to
indicatetotheregisterfunctionthestandbybuttonMMIsourceforwhichthedispatchfunctionshouldbeinvoked.
TypeEFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT is defined in “Related Definitions” below.
tocolInterface() in the UEFI 2.1 Specification.
This service registers a function ( DispatchFunction ) which will be called when an MMI is generated because the
standbybuttonwaspressedorreleased,asspecifiedby RegisterContext . Onreturn, DispatchHandle containsaunique
handle which may be used later to unregister the function using UnRegister() .
Contextand withCommBuffer andCommBufferSize set toNULL.
IV-7.7. MM Standby Button Dispatch Protocol IV-105UEFI Platform Initialization Specification, Release 1.8
// EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT
EFI_STANDBY_BUTTON_PHASE Phase;
} EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT;
Phase
Describeswhetherthechildhandlershouldbeinvokedupontheentrytothebuttonactivationoruponexit(i.e.,
upon receipt of the button press event or upon release of the event). This differentiation allows for workarounds
or maintenance in each of these execution regimes. Type EFI_STANDBY_BUTTON_PHASE is defined below.
// EFI_STANDBY_BUTTON_PHASE;
EfiStandbyButtonEntry,
EfiStandbyButtonExit,
EfiStandbyButtonMax
} EFI_STANDBY_BUTTON_PHASE;
EFI_INVALID_PARAMETER RegisterContext is invalid The standby button input value is not
within valid range
IV-7.7.3 EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL.UnRegister()
Summary
Unregisters a child MMI source dispatch function with a parent MM Driver.
Prototype
typedef
(EFIAPI *EFI_MM_STANDBY_BUTTON_UNREGISTER) (
IN EFI_HANDLE *DispatchHandle
);
This
IV-7.7. MM Standby Button Dispatch Protocol IV-106UEFI Platform Initialization Specification, Release 1.8
This service removes the handler associated with DispatchHandle so that it will no longer be called when the standby
button is pressed or released.
IV-7.8 MM Power Button Dispatch Protocol
IV-7.8.1 EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL
Summary
Provides the parent dispatch service for the power button MMI source generator.
GUID
#define EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID \
{ 0x1b1183fa, 0x1823, 0x46a7, \
0x88, 0x72, 0x9c, 0x57, 0x87, 0x55, 0x40, 0x9d }
typedef struct _EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL {
EFI_MM_POWER_BUTTON_REGISTER Register;
EFI_MM_POWER_BUTTON_UNREGISTER UnRegister;
} EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL;
Register
Removes a child service that was dispatched by this protocol. See the UnRegister() function description.
TheEFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL providestheabilitytoinstallchildhandlersforthegiven
IV-7.8.2 EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL. Register()
Summary
Prototype
typedef
(EFIAPI *EFI_MM_POWER_BUTTON_REGISTER) (
IV-7.8. MM Power Button Dispatch Protocol IV-107UEFI Platform Initialization Specification, Release 1.8
IN CONST EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL *This,
IN EFI_MM_POWER_BUTTON_REGISTER_CONTEXT *RegisterContext,
);
This
Pointer to the EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL instance.
Function to register for handler when power button is pressed or released. Type
theMMST.
to indicate to the Register() function the power button MMI phase for which the dispatch function should be
invoked. Type EFI_MM_POWER_BUTTON_REGISTER_CONTEXT isdefinedin“RelatedDefinitions”below.

);
This
theMMST.
power button was pressed or released, as specified by RegisterContext . On return, DispatchHandle contains a unique
// EFI_MM_POWER_BUTTON_REGISTER_CONTEXT
EFI_POWER_BUTTON_PHASE Phase;
} EFI_MM_POWER_BUTTON_REGISTER_CONTEXT;
Phase
Designateswhetherthishandlershouldbeinvokeduponentryorexit. Type EFI_POWER_BUTTON_PHASE is
// EFI_POWER_BUTTON_PHASE
EfiPowerButtonEntry,
EfiPowerButtonExit,
EfiPowerButtonMax
} EFI_POWER_BUTTON_PHASE;
IV-7.8. MM Power Button Dispatch Protocol IV-108UEFI Platform Initialization Specification, Release 1.8
EFI_INVALID_PARAMETER RegisterContextisinvalidThepowerbuttoninputvalueisnotwithin
valid range
IV-7.8.3 EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL.UnRegister()
Summary
Unregisters a power-button service.
Prototype
typedef
(EFIAPI *EFI_MM_POWER_BUTTON_UNREGISTER) (
IN CONST *EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL *This,
);
This
IV-7.9 MM IO Trap Dispatch Protocol
IV-7.9.1 EFI_MM_IO_TRAP_DISPATCH_PROTOCOL
Summary
This protocol provides a parent dispatch service for IO trap MMI sources.
GUID
#define EFI_MM_IO_TRAP_DISPATCH_PROTOCOL_GUID \
{ 0x58dc368d, 0x7bfa, 0x4e77, \
0xab, 0xbc, 0xe, 0x29, 0x41, 0x8d, 0xf9, 0x30 }
IV-7.9. MM IO Trap Dispatch Protocol IV-109UEFI Platform Initialization Specification, Release 1.8
struct _EFI_MM_IO_TRAP_DISPATCH_PROTOCOL {
EFI_MM_IO_TRAP_DISPATCH_REGISTER Register;
EFI_MM_IO_TRAP_DISPATCH_UNREGISTER UnRegister;
} EFI_MM_IO_TRAP_DISPATCH_PROTOCOL;
Register
Installs a child service to be dispatched when the requested IO trap MMI occurs. See the Register() function
Removes a previously registered child service. See the Register() and UnRegister() function descriptions.
ThisprotocolprovidestheabilitytoinstallchildhandlersforIOtrapMMI.Thesehandlerswillbeinvokedtorespond
to specific IO trap MMI. IO trap MMI would typically be generated on reads or writes to specific processor IO space
addresses or ranges. This protocol will typically abstract a limited hardware resource, so callers should handle errors
gracefully.
IV-7.9.2 EFI_MM_IO_TRAP_DISPATCH_PROTOCOL.Register ()
Summary
Register an IO trap MMI child handler for a specified MMI.
Prototype
(EFIAPI *EFI_MM_IO_TRAP_DISPATCH_REGISTER) (
IN CONST EFI_MM_IO_TRAP_DISPATCH_PROTOCOL *This,
IN OUT EFI_MM_IO_TRAP_REGISTER_CONTEXT *RegisterContext,
);
This
Pointer to the EFI_MM_IO_TRAP_DISPATCH_PROTOCOL instance.
FunctiontoregisterforhandlerwhenI/Otraplocationisaccessed. Type EFI_MM_HANDLER_ENTRY_POINT
Pointer to the dispatch function’s context. The caller fills this context in before calling the register function to
indicate to the register function the IO trap MMI source for which the dispatch function should be sinvoked.
Handleofthedispatchfunction,forwheninterfacingwiththeparentMMDriver. Type EFI_HANDLE isdefined
inInstallProtocolInterface() in the UEFI Specification.
This service registers a function ( DispatchFunction ) which will be called when an MMI is generated because of an
access to an I/O port specified by RegisterContext . On return, DispatchHandle contains a unique handle which may
IV-7.9. MM IO Trap Dispatch Protocol IV-110UEFI Platform Initialization Specification, Release 1.8
be used later to unregister the function using UnRegister() . If the base of the I/O range specified is zero, then an I/O
range with the specified length and characteristics will be allocated and the Address field in RegisterContext updated.
If no range could be allocated, then EFI_OUT_OF_RESOURCES will be returned.
TheservicewillnotperformGCDallocationifthebaseaddressisnon-zeroor EFI_MM_READY_TO_LOCK hasbeen
installed. In this case, the caller is responsible for the existence and allocation of the specific IO range.
An error may be returned if some or all of the requested resources conflict with an existing IO trap child handler.
ItisnotrequiredthatimplementationswillallowmultiplechildrenforasingleIOtrapMMIsource. Someimplemen-
tations may support multiple children.
TheDispatchFunction willbecalledwith ContextupdatedtocontaininformationconcerningtheI/Oactionthatactually
happenedandispassedin RegisterContext, withCommBuffer pointingtothedataactuallywrittenand CommBufferSize
pointing to the size of the data in CommBuffer .
//
// IO Trap valid types
//
WriteTrap,
ReadTrap,
ReadWriteTrap,
IoTrapTypeMaximum
} EFI_MM_IO_TRAP_DISPATCH_TYPE;
//
// IO Trap context structure containing information about the
// IO trap event that should invoke the handler
//
UINT16 Address;
EFI_MM_IO_TRAP_DISPATCH_TYPE Type;
} EFI_MM_IO_TRAP_REGISTER_CONTEXT;
//
// IO Trap context structure containing information about the IO trap that occurred
//
UINT32 WriteData;
} EFI_MM_IO_TRAP_CONTEXT;
EFI_SUCCESS The dispatch function has been successfully registered
EFI_DEVICE_ERROR The driver was unable to complete due to hardware error
EFI_OUT_OF_RESOURCES InsufficientresourcesareavailabletofulfilltheIOtraprangerequest
EFI_INVALID_PARAMETER RegisterContextisinvalidTheinputvalueisnotwithinavalidrange
IV-7.9. MM IO Trap Dispatch Protocol IV-111UEFI Platform Initialization Specification, Release 1.8
IV-7.9.3 EFI_MM_IO_TRAP_DISPATCH_PROTOCOL.UnRegister ()
Summary
Unregister a child MMI source dispatch function with a parent MM Driver.
Prototype
(EFIAPI *EFI_MM_IO_TRAP_DISPATCH_UNREGISTER) (
);
This
Handle of the child service to remove. Type EFI_HANDLE is defined in InstallProtocolInterface() in the EFI
1.10 Specification.
This service removes a previously installed child dispatch handler. This does not guarantee that the system resources
will be freed from the GCD.
None
EFI_SUCCESS The dispatch function has been successfully unregistered
IV-7.10 HOBs
IV-7.10.1 EFI_PEI_MM_CORE_GUID
Summary
A GUIDed HOB that indicates whether the MM Core has been loaded.
GUID
#define EFI_PEI_MM_CORE_GUID \
{0x8d1b3618, 0x111b, 0x4cba, \
{0xb7, 0x9a, 0x55, 0xb3, 0x2f, 0x60, 0xf0, 0x29} }
HOB Structure
typedef struct _EFI_PEI_MM_CORE_HOB {
IV-7.10. HOBs IV-112UEFI Platform Initialization Specification, Release 1.8
} EFI_PEI_MM_CORE_HOB;
Members
Header
The HOB generic header with Header.HobType set toEFI_HOB_TYPE_GUID_EXTENSION .
Name
The GUID that specifies this particular HOB structure. Set to EFI_PEI_MM_CORE_GUID .
flags
Bitmask that specifies which MM features have been initialized in SEC. All other bits must be set to 0.
# define EFI_PEI_MM_CORE_LOADED 0x00000001
# MM Core Loaded
ThisHOBisconsumedbytheMMIPLdrivertounderstandwhichportionsofMMinitializationhavebeencompleted.
ForexampletheDXEMMIPLdrivercandeterminewhetherMMRAMhasbeeninitializedandtheMMCoreloaded.
IV-7.10. HOBs IV-113CHAPTER
EIGHT
INTERACTIONS WITH PEI, DXE, AND BDS
IV-8.1 Introduction

Members
Header
Name
flags
EIGHT
This chapter describes issues related to image verification and interactions between SM and other PI Architecture
phases.
IV-8.2 MM and DXE
IV-8.2.1 Software MMI Communication Interface (Method #1)
During the boot service phase of DXE/UEFI, there will be a messaging mechanism between MM and DXE drivers.
This mechanism will allow a gradual state evolution of the SM handlers during the boot phase.
ThepurposeoftheDXE/UEFIcommunicationistoallowinterfacesfromeitherruntimeorbootservicestobeproxied
into SM. For example, a vendor may choose to implement their UEFI Variable Services in SM. The motivation to
do so would include a design in which the SM code performed error logging by writing data to an UEFI variable in
flash. The error generation would be asynchronous with respect to the foreground operating system (OS). A problem
is that the OS could be writing an UEFI variable when the error condition, such as a Single-Bit Error (SBE) that was
generated from main memory, occurred. To avoid two agents–SM and UEFI Runtime–both trying to write to flash
at the same time, the runtime implementation of the SetVariable() UEFI call would simply be an invocation of the
EFI_MM_COMMUNICATION_PROTOCOL.Communicate() interface. Then, the SM code would internally serialize
the error logging flash write request and the OS SetVariable() request.
See theEFI_MM_COMMUNICATION_PROTOCOL.Communicate() service for more information on this interface.
IV-8.2.2 Software MMI Communication Interface (Method #2)
This section describes an alternative mechanism that can be used to initiate inter-mode communication. This mecha-
nism can be used in the OS present environment by non-firmware agents. Inter-mode communication can be initiated
using special software MMI.
Details regarding the MMI are described in the SM Communication ACPI Table. This table is described in Appendix
O of theUEFI Specification .
Firmware processes this software MMI in the same manner it processes direct invocation of the Communicate() func-
tion.
IV-114UEFI Platform Initialization Specification, Release 1.8
IV-8.3 MM and PEI
IV-8.3.1 Software MMI Communication Interface (Method #1)
During the PI PEI, there will be a messaging mechanism between MM and PEI drivers. This mechanism will allow a
gradual state evolution of the MM Handlers during the PI PEI phase.
The purpose of the PEI communication is to allow interfaces from PEI services to be proxied into MM. For example,
a vendor may choose to implement the LockBox Services in MM. The motivation to do so would include a design in
which the MM code performed secure storage to save data for S3 resume. PEI phase LockBox service would simply
be an invocation of the EFI_PEI_MM_COMMUNICATION_PPI.Communicate() interface. Then, the MM code would
perform LockBox request.
See theEFI_PEI_MM_COMMUNICATION_PPI.Communicate() service for more information on this interface.
IV-8.3. MM and PEI IV-115CHAPTER
NINE
OTHER RELATED NOTES FOR SUPPORT OF MM DRIVERS
IV-9.1 File Types
The following new file types are added:
#define EFI_FV_FILETYPE_MM 0x0A
#define EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C
#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E
IV-9.1.1 File Type EFI_FV_FILETYPE_MM
The file type EFI_FV_FILETYPE_MM denotes a file that contains a PE32+ image that will be loaded into MMRAM
in MM Tradition Mode.
•The file must contain at least one EFI_SECTION_PE32 section. There are no restrictions on encapsulation of
this section.
dispatchedisdefinedbythe LoadImage() bootservice,whichisusedbytheDXEDispatcher. SeethePlatformInitial-
ization Specification, Volume 2 for details. The file may contain other leaf and encapsulation sections as required or
enabled by the platform design.
IV-9.1.2 File Type EFI_FV_FILETYPE_COMBINED_MM_DXE
The file type EFI_FV_FILETYPE_COMBINED_MM_DXE denotes a file that contains a PE32+ image that will be
dispatched by the DXE Dispatcher and will also be loaded into MMRAM in MM Tradition Mode.
•Thefilemustcontainnomorethanone EFI_SECTION_DXE_DEPEX section. Thissectionisignoredwhenthe
file is loaded into MMRAM.
IV-116UEFI Platform Initialization Specification, Release 1.8
•Thefilemustcontainnomorethanone EFI_SECTION_MM_DEPEX section. Thissectionisignoredwhenthe
file is dispatched by the DXE Dispatcher.
IV-9.2 File Type EFI_FV_FILETYPE_MM_STANDALONE
Thefiletype EFI_FV_FILETYPE_MM_STANDALONE denotesafilethatcontainsaPE32+imagethatwillbeloaded
into MMRAM in MM Standalone Mode.
section.
dispatchedisdefinedbyMMFoundationDispatcher. SeethePlatformInitializationSpecification,Volume4fordetails.
IV-9.3 File Section Types
The following new section type must be added:
#define EFI_SECTION_MM_DEPEX 0x1c
IV-9.3.1 File Section Type EFI_SECTION_MM_DEPEX
Summary
A leaf section type that is used to determine the dispatch order for an MM Driver.
Prototype
TheMMdependencyexpressionsectionisaleafsectionthatcontainsadependencyexpressionthatisusedtodetermine
the dispatch order for MM Drivers. Before the MMRAM invocation of the MM Driver’s entry point, this dependency
IV-9.2. File Type EFI_FV_FILETYPE_MM_STANDALONE IV-117CHAPTER
TEN
MCA/INIT/PMI PROTOCOL
This document defines the basic plumbing required to run the MCA, PMI & INIT in a generic framework. They have
been group together since MCA and INIT follows a very similar flow and all three have access to the min-state as
defined by PAL.
It makes an attempt to bind the platform knowledge by the way of generic abstraction to the SAL MCA, PMI & INIT
code. We have tried to create a private & public data structures for each CPU. For example, any CPU knowledge that
shouldremainwithinthecontextofthatCPUshouldbeprivate. AnyCPUknowledgethatmaybeaccessedbyanother
CPUshouldbeaGlobalStructurethatcanbeaccessedbyanyCPUforthatdomain. Therearesomeflagsthatmaybe
required globally (Sal Proc, Runtime Services, PMI, INIT, MCA) are made accessible through a protocol pointer that
is described in section 5.
IV-10.1 Machine Check and INIT
This section describes how Machine Check Abort Interrupt and INIT are handled in a UEFI 2.0 compliant system.
As shown in Early Reset, MCA and INIT flow resets, MCA and INIT follow a near identical early flow. For all three
events, PAL first processes the event, save some states if needed in the min-state before jumping to SAL through the
common SALE_ENTRY entry point. SAL performs some early processor initialization, save some extra states to set
upanenvironmentinwhichtheeventcanbehandledandthenbranchtotheappropriateeventdispatcher(normalreset
flow, MCA, INIT).
MCA/INIThandlingpersayconsistsofagenericdispatcherandoneormoreplatformspecifichandlers. Thedispatcher
isresponsibleforhandlingtasksspecifiedinSALspecification,suchasperformingrendezvous,beforecallingtheevent

handlersinafixedorder. Thehandlersareresponsibleforerrorlogging,errorcorrectionandanyotherplatformspecific
task required to properly handle a MCA or INIT event.
IV-10.2 MCA Handling
The machine check (MCA) code path in a typical machine based on IPF architecture is shown in the diagram below
(seeBasic MCA processing flow ).
MCA processing starts in PAL, running in physical mode. Control is then pass to SAL through the SALE_ENTRY
entry point which in turn, after processing the MCA, pass control to the OS MCA handler.
In the PI architecture, OEMs have the choice to process MCA events in either entirely in ROM code, entirely in the
RAMcodeorpartlyinROMandpartlyinRAM.TheearlypartoftheMCAflowfollowtheSEC->PEIbootflow,with
SALE_ENTRYresidinginSECwhiletheMCAdispatcherisaPEIMdispatcher(see PIMCAprocessingflow ). From
that point on the rest of the code can reside in ROM or RAM.
When PAL hands off control to SALE_ENTRY, it will supply unique hand off state in the processor registers as well
as the minimum state saved buffer area pointer called “min-state pointer”. The min-state pointer is the only context
IV-118UEFI Platform Initialization Specification, Release 1.8
Fig. 10.1: Early Reset, MCA and INIT flow
Fig. 10.2: Basic MCA processing flow
Fig. 10.3: PI MCA processing flow
IV-10.2. MCA Handling IV-119UEFI Platform Initialization Specification, Release 1.8
availabletoSALE_ENTRY.Thisbufferisauniqueperprocessorsavearearegisteredtoeachprocessorduringnormal
OS boot path.
AsampleimplementationisdescribedbelowtoclarifysomeofthefinerpointsofMCA/INIT/PMI.Actualimplemen-
tations may vary.
Usually, we can anchor some extra data (the MCA_INIT_PMI_PER_PROCESSOR_DATA data structure) required by
the PEIM dispatcher and the MCA and INIT dispatchers to the min-state (see PI architectural data in the min ).
Fig. 10.4: PI architectural data in the min
The software component (a PEIM or a DXE module) that includes the MCA and INIT dispatchers is responsible for
registeringthemin-stateonallprocessorsandinitializing MCA_INIT_PMI_PER_PROCESSOR_DATA datastructures.
Only then can MCA be properly handled by the platform. To guarantee proper MCA and INIT handling, at least one
handler is required to be registered with the MCA dispatcher. OEM might decide to use a monolithic handler or use
multiple handlers.
The register state at the MCA dispatcher entry point is the same as the PALE_CHECK exit state with the following
exceptions
•GR1 contains GP for the McaDispatcherProc .
•PAL saves b0 in the min-state and can be used as scratch. b0 contains the address of the McaDispatcherProc .
•PAL saves static registers to the min-state. All static registers in both banks except GR16-GR20 in bank 0 can
be used as scratch registers. SALE_ENTRY may freely modify these registers.
The MCA dispatcher is responsible for setting up a stack and backing store based on the values in the
MCA_INIT_PMI_PER_PROCESSOR_DATA data structure. The OS stack and backing store cannot be used since
theymightpointtovirtualaddresses. TheMCAdispatcherisalsoresponsibleforsavinganyregistersnotsavedinthe
min-state that may be used by the MCA handling code in the PI per processor data. Since we want to use high-level
language such as C, floating point registers f2 to f31 as well as branch registers b6 and b7 must be saved. Code used
during MCA handling must be compiled with /f32 option to prevent the use of registers f33-f127. Otherwise, such
codeisresponsibleforsavingandrestoringfloatingpointregistersf33-f127aswellasanyotherregistersnotsavedin
the min-state or the PI per processor data.
Note thatnested MCA recoveryis not supportedby the Itaniumarchitecture as PALuses the samemin-state for every
MCA and INIT event. As a result, the same context within the min-state is used by PI every time the MCA dispatcher
is entered.
All the MCA handles are presented in a form of an Ordered List. The head of the Ordered List is a member of the
Private Data Structure. In order to reach the MCA handle Ordered List the following steps are used:
1. PerCpuInfoPointer = MinStatePointer ( FromSALE_CHECK ) + 4K
2. ThisCpuMcaPrivateData = PerCpuInfoPointer->Private
3. McaHandleListHead = ThisCpuMcaPrivateData->McaList
Or((EFI_MCA_SAVE_DATA*) (((UINT8*) MinStatePointer) + 4*1024))->Private-> McaList
On reaching the Ordered List from the private data we can obtain Plabel & MCA Handle Context. Using that we can
execute each handle as they appear in the ordered list.
IV-10.2. MCA Handling IV-120UEFI Platform Initialization Specification, Release 1.8
Once the last handler has completed execution, the MCA dispatcher is responsible for deciding whether to resume
execution, halt the platform or reset the platform. This is based on the OS request and platform policies. Resuming to
the interrupted context is accomplished by calling PAL_MC_RESUME .
As shown in Basic MCA processing flow , the MCA handling flow requires access to certain shared hardware and
software resources to support things such as error logging, error handling/correction and processor rendezvous. In
addition, since MCAs are asynchronous, they might happen while other parts of the system are using those shared
resourcesorwhileaccessingthoseresources(forexampleduringtheexecutionofaSAL_PROClikePCIconfigwrite).
We thus need a mechanism to allow shared access to two isolated model which are not aware of each others.
This is handled through the use of common code (libraries) and semaphores. The SAL PROCs and the MCAA/INIT
code use the same libraries to implement any functionality shared between them such as platform reset, stall, PCI
read/write. Semaphores are used to gate access to critical portion of the code and prevent multiple accesses to the
same HW resource at the same time. To prevent deadlocks and guarantee proper OS handling of an MCA it might be
necessary for the MCA/INIT handler to break semaphore or gets priority access to protected resources.
InadditiontothepreviouslymentionedsemaphoresusedforgatingaccesstoHWresource,themultithreaded/MPMCA
modelmayrequireanMCAspecificsemaphoretosupportthingslikemonarchprocessorselectionandlogaccess. This
semaphoreshouldbevisiblefromallprocessors. InadditionsomeglobalarerequiredforMCAprocessingtoindicate
a processor status (entering MCA, in MCA rendezvous, ready to enter OS MCA) with regards to the current MCA.
ThisflagsneedtohaveaglobalscopesincetheMCAmonarchmayneedtoaccessthemtomakesureallprocessorare
where they are supposed to be.
IV-10.3 INIT Handling
MostofwhathavebeendefinedfortheMCAhandlinganddispatcherappliestotheINITcodepath. Theearlypartof
theINITcodepath,uptotheINITdispatcherisidenticaltotheMCAcodepathwhilesomeoftheINIThandlercode,
like logging, can be shared with the MCA handler.
The INIT code path in a typical machine based on IPF architecture is shown in the diagram below.
Fig. 10.5: PI INIT processing flow
LikeMCA,INITprocessingstartsinthePALcodeinphysicalmodeandthenflowsintoPIcode(OEMfirmwarecode)
throughSALE_ENTRY.TheINITdispatcherisresponsibleforsettingupastackandbackingstore,savingthefloating
point registers before calling any code that may be written in higher level languages. At that point the dispatcher is
ready to call the INIT handlers. As with MCA only one handler is required to exist but OEMs are free to implement
a monolithic handler or use multiple handlers. Once the last handler has been executed, the dispatcher will resume to
the interrupted context or reset the platform based on the OS request.
The MCA handler limitations regarding access to shared HW and SW resources applies to the INIT handler, as such
library code and common semaphores should be used.
INIT events are always local to each processor. As a result we do not need INIT specific flags or semaphore in the
MCA_INIT_PMI_PER_PROCESSOR_DATA data structures.
IV-10.3. INIT Handling IV-121UEFI Platform Initialization Specification, Release 1.8
IV-10.4 PMI
This section describes how PMI, platform management interrupts, are handled in EFI 2.0 compliant system. PMIs
provide an operating system-independent interrupt mechanism to support OEM and vendor specific hardware event.
Fig. 10.6: PMI handling flow
As shown in PMI handling flow , PMI handling is pretty similar to MCA and INIT handling in such that it consists
of a generic dispatcher and one of more platform specific handlers. The dispatchers is the SAL PMI entry point
(SALE_PMI) and is responsible for saving state and setting up the environment for the handler to execute. Contrary
to MCA and INIT, PAL does not save any context in the min-state and it is the responsibility of the PMI dispatcher
to save state. Since the min-state is available during PMI handling (PAL provides its address to the SAL PMI han-
dler) the MCA_INIT_PMI_PER_PROCESSOR_DATA data structure present in the min-state can be used. However
an MCA/INIT event occurring while PMI is being would preclude the system from resuming from the PMI event. To
alleviatethis,aplatformmaydecidetoimplementaseparatecopyofthe MCA_INIT_PMI_PER_PROCESSOR_DATA

data structure out side of the min-state, to be used for PMI state saving.
Oncethestateissaved,theplatformspecificPMIhandlersarefoundusingtheorderhandlerlistprovidedintheprivate
data structure. The mechanism used is the same one used in MCA and INIT handling.
IV-10.5 Event Handlers
The events handlers are called by the various dispatchers.
IV-10.5.1 MCA Handlers
MCA Handler
typedef
SAL_RUNTIMESERVICE
(EFIAPI *EFI_SAL_MCA_HANDLER) (
IN VOID *ModuleGlobal,
IN UINT64 ProcessorStateParameters ,
IN EFI_PHYSICAL_ADDRESS MinstateBase,
IN UINT64 RendezvouseStateInformation,
IN UINT64 CpuIndex,
IN SAL_MCA_COUNT_STRUCTURE *McaCountStructure,
IN OUT BOOLEAN *CorrectedMachineCheck
);
ModuleGlobal
The context of MCA Handler.
IV-10.4. PMI IV-122UEFI Platform Initialization Specification, Release 1.8
ProcessorStateParameters
The processor state parameters (PSP),
MinstateBase
Base address of the min-state.
RendezvousStateInformation
RendezvousstateinformationtobepassedtotheOSonOSMCAentry. Refertothe SalSpecification3.0,section
4.8for moreinformation.
CpuIndex
Index of the logical processor
McaCountStructure
Pointer to the MCA records structure
CorrectedMachineCheck
This flag is set to TRUEis the MCA hasbeen corrected by the handler or by a previoushandler.
//
// MCA Records Structure
//
UINT64 First : 1;
UINT64 Last : 1;
UINT64 EntryCount : 16;
UINT64 DispatchedCount : 16;
UINT64 Reserved : 30;
} SAL_MCA_COUNT_STRUCTURE;
IV-10.5.2 INIT Handlers
INIT Handler
typedef
(EFIAPI *EFI_SAL_INIT_HANDLER) (
IN UINT64 ProcessorStateParameters,
IN BOOLEAN McaInProgress,
OUT BOOLEAN *DumpSwitchPressed
);
IV-10.5. Event Handlers IV-123UEFI Platform Initialization Specification, Release 1.8
McaInProgress
This flag indicates if an MCA is inprogress.
CpuIndex
DumpSwitchPressed
This flag indicates the crash dump switchhas been pressed.
IV-10.5.3 PMI Handlers
PMI Handler
typedef
(EFIAPI *SAL_PMI_HANDLER) (
IN UINT64 PmiVector
);
CpuIndex
PmiVector
The PMI vector number as received from thePALE_PMI exit state (GR24).
IV-10.6 MCA PMI INIT Protocol
Summary
This protocol is used to register MCA, INIT and PMI handlers with their respective dispatcher.
GUID
#define EFI_SAL_MCA_INIT_PMI_PROTOCOL_GUID \
{
0xb60dc6e8,0x3b6f,0x11d5,0xaf,0x9,0x0,0xa0,0xc9,0x44,0xa0,0x5b }
EFI_SAL_REGISTER_MCA_HANDLER RegisterMcaHandler;
EFI_SAL_REGISTER_INIT_HANDLER RegisterInitHandler;
EFI_SAL_REGISTER_PMI_HANDLER RegisterPmiHandler;
IV-10.6. MCA PMI INIT Protocol IV-124UEFI Platform Initialization Specification, Release 1.8
BOOLEAN McaInProgress;
BOOLEAN InitInProgress;
BOOLEAN PmiInProgress;
} EFI_SAL_MCA_INIT_PMI_PROTOCOL;
RegisterMcaHandler
Function to register a MCA handler.
RegisterInitHandler
Function to register an INIT handler.
RegisterPmiHandler
Function to register a PMI hander.
Whether MCA handler is in progress
InitInProgress
Whether Init handler is in progress
PmiInProgress
Whether Pmi handler is in progress
IV-10.6.1 EFI_SAL_MCA_INIT_PMI_PROTOCOL. RegisterMcaHandler()
Summary
Register a MCA handler with the MCA dispatcher.
Prototype
typedef
(EFIAPI \*EFI_SAL_REGISTER_MCA_HANDLER) (
IN struct \_EFI_SAL_MCA_INIT_PMI_PROTOCOL *This,
IN EFI_SAL_MCA_HANDLER McaHandler,
IN VOID ModuleGlobal
IN BOOLEAN MakeFirst,
IN BOOLEAN MakeLast
);
This
TheEFI_SAL_MCA_INIT_PMI_PROTOCOL instance.
McaHandler
The MCA handler to register as defined in:ref: MCAHandlers .
The context of the MCA Handler.
MakeFirst
This flag specifies the handler should bemade first in the list.
MakeLast
This flag specifies the handler should bemade last in the list.
IV-10.6. MCA PMI INIT Protocol IV-125UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS MCA Handle was registered
EFI_OUT_OF_RESOURCES No more resources to register an MCA handler
EFI_INVALID_PARAMETER Invalid parameters were passed.
IV-10.6.2 EFI_SAL_MCA_INIT_PMI_PROTOCOL. RegisterInitHandler()
Summary
Register an INIT handler with the INIT dispatcher.
Prototype
typedef
(EFIAPI \*EFI_SAL_REGISTER_INIT_HANDLER) (
IN EFI_SAL_INIT_HANDLER InitHandler,
);
This
InitHandler
The INIT handler to register as defined in:ref: INITHandlers
The context of the INIT Handler.
MakeFirst
MakeLast
EFI_SUCCESS INIT Handle was registered
EFI_OUT_OF_RESOURCES No more resources to register an INIT handler
IV-10.6. MCA PMI INIT Protocol IV-126UEFI Platform Initialization Specification, Release 1.8
IV-10.6.3 EFI_SAL_MCA_INIT_PMI_PROTOCOL. RegisterPmiHandler()
Summary
Register a PMI handler with the PMI dispatcher.
Prototype
typedef
(EFIAPI *EFI_SAL_REGISTER_PMI_HANDLER) (
IN EFI_SAL_PMI_HANDLER PmiHandler,
);
This
PmiHandler
The PMI handler to register as defined in:ref: PMIHandlers .
The context of the PMI Handler.
MakeFirst
MakeLast
EFI_OUT_OF_RESOURCES No more resources to register a PMI handler
IV-10.6. MCA PMI INIT Protocol IV-127CHAPTER
ELEVEN
EXTENDED SAL SERVICES
ThisdocumentdescribestheExtendedSALsupportfortheEDKII.TheExtendedSALusesacallingconventionthat
is very similar to the SAL calling convention. This includes the ability to call Extended SAL Procedures in physical
mode prior to SetVirtualAddressMap() , and the ability to call Extended SAL Procedures in physical mode or virtual
mode after SetVirtualAddressMap() .
IV-11.1 SAL Overview
The Extended SAL can be used to implement the following services:
•SAL Procedures required by the Intel Itanium Processor Family System Abstraction Layer Specification.
•EFI Runtime Services required by the UEFI 2.0 Specification , that may also be required by SAL Procedures,
other Extended SAL Procedures, or MCA, INIT, and PMI flows.
•Services required to abstract hardware accesses from SAL Procedures and Extended SAL Procedures. This
includes I/O port accesses, MMIO accesses, PCI Configuration Cycles, and access to non-volatile storage for
logging purposes.
•Services required during the MCA, INIT, and PMI flows.
Note:ArgumentstoSALproceduresareformattedthesameasargumentsandparamentersinthisdocument. Example
“addressparameter to ...”
TheExtendedSALsupportincludesaDXEProtocolthatsupportsthepublishingoftheSALSystemTablealongwith
services to register and call Extended SAL Procedures. It also includes a number of standard Extended SAL Service
Classes that are required to implement EFI Runtime Services, the minimum set of required SAL Procedures, services
to abstract hardware accesses, and services to support the MSA, INIT, and PMI flows. Platform developer may define
addition Extended SAL Service Classes to provide platform specific functionality that requires the Extended SAL
calling conventions.The SAL calling convention requires operation in both physical and virtual mode. Standard EFI
runtime services work in either physical mode or virtual mode at a time. Therefore, the EFI code can call the SAL
code, but not vice versa. To reduce code duplication resulting out of multiple operating modes, additional procedures
called Extended SAL Procedures are implemented. Architected SAL procedures are a subset of the Extended SAL
procedures. The individual Extended SAL procedures can be called through the entry point ExtendedSalProc() in the
EXTENDED_SAL_BOOT_SERVICE_PROTOCOL .Thecostofwritingdualmodecodeisthatonemuststrictlyfollow
the SAL runtime coding rules. Experience on prior IPF platform shows us that the benefits outweigh the cost.
Note:Inthefigureabove,arrowsindicatethedirectionofcalling. Forexample,OScodemaycallEFIruntimeservices

orSAL_PROCs . Extended SAL functions are divided in several classes based on their functionality, with no defined
hierarchy. It is legal for an EFI Boot Service Code to call ExtendedSalProc() . It is also legal for an Extended SAL
IV-128UEFI Platform Initialization Specification, Release 1.8
Fig. 11.1: SAL Calling Diagram
procedure to call another Extended SAL Procedure via ExtendedSalProc() . These details are not shown in the figure
in order to maintain clarity.
A driver with a module type of DXE_SAL_DRIVER is required to produce the EX-
TENDED_SAL_BOOT_SERVICE_PROTOCOL .ThisdrivercontainstheentrypointoftheExtendedSALProcedures
and dispatches previously registered procedures. It also provides services to register Extended SAL Procedures and
functions to help construct the SAL System Table.
Driverswithamoduletypeof DXE_SAL_DRIVER arerequiredtoproducethevariousExtendedSALServiceClasses.
It is expected that a single driver will supply all the Extended SAL Procedures that belong to a single Extended SAL
ServiceClass. AseachExtendedSALServiceClassisregistered,theGUIDassociatedwiththatclassisalsoinstalled
intotheEFIHandleDatabase. ThisallowsotherDXEdriverstousetheExtendedSALServiceClassGUIDsintheirde-
pendencyexpressions,sotheyonlyexecuteoncetheirdependentExtendedSALServiceClassesareavailable. Drivers
registerthesetofExtendedSALProcedurestheyproducewiththe EXTENDED_SAL_BOOT_SERVICE_PROTOCOL
. Once this registration step is complete, the Extended SAL Procedure are available for use by other drivers.
IV-11.2 Extended SAL Boot Service Protocol
ThisprotocolsupportsthecreationoftheSALSystemTable,andprovidesservicestoregisterandcallExtendedSAL
Procedures. The driver that produces this protocol is required to allocate and initialize the SAL System Table. The
SAL System Table must also be registered in the list of EFI System Configuration tables. The driver that produces
this protocol must be of type DXE_SAL_DRIVER . This is required because the entry point to the ExtendedSalProc()
function is always available, even after the OS assumes control of the platform at ExitBootServices() .
IV-11.2. Extended SAL Boot Service Protocol IV-129UEFI Platform Initialization Specification, Release 1.8
IV-11.2.1 EXTENDED_SAL_BOOT_SERVICE_PROTOCOL
Summary
This section provides a detailed description of the EXTENDED_SAL_BOOT_SERVICE_PROTOCOL .
GUID
#define EXTENDED_SAL_BOOT_SERVICE_PROTOCOL_GUID \
{0xde0ee9a4,0x3c7a,0x44f2, \
{0xb7,0x8b,0xe3,0xcc,0xd6,0x9c,0x3a,0xf7}}
typedef struct _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL {
EXTENDED_SAL_ADD_SST_INFO AddSalSystemTableInfo;
EXTENDED_SAL_ADD_SST_ENTRY AddSalSystemTableEntry;
EXTENDED_SAL_REGISTER_INTERNAL_PROC RegisterExtendedSalProc;
EXTENDED_SAL_PROC ExtendedSalProc;
} EXTENDED_SAL_BOOT_SERVICE_PROTOCOL;
AddSalSystemTableInfo
Adds platform specific information to the to the header of the SAL System Table. Only available prior to Exit-
BootServices() .
AddSalSystemTableEntry
Add an entry into the SAL System Table. Only available prior to ExitBootServices() .
RegisterExtendedSalProc
Registers an Extended SAL Procedure. Extended SAL Procedures are named by a (GUID, FunctionID) pair.
Extended SAL Procedures are divided into classes based on the functionality they provide. Extended SAL Pro-
ceduresarecallableonlyinphysicalmodepriorto SetVirtualAddressMap() ,andarecallableinbothvirtualand
physical mode after SetVirtualAddressMap() . Only available prior to ExitBootServices() .
ExtendedSalProc
Entry point for all extended SAL procedures. This entry point is always available.
TheEXTENDED_SAL_BOOT_SERVICE_PROTOCOL providesamechanismsforplatformspecificdriverstoupdate
the SAL System Table and register Extended SAL Procedures that are callable in physical or virtual mode using the
SALcallingconvention. TheservicesexportedbytheSALSystemTablearetypicallyimplementedasExtendedSAL
Procedures. Services required by MCA, INIT, and PMI flows that are also required in the implementation of EFI
RuntimeServicesarealsotypicallyimplementedasExtendedSALProcedures. ExtendedSALProceduresarenamed
by a (GUID, FunctionID) pair. A standard set of these (GUID, FunctionID) pairs are defined in this specification.
Platforms that require additional functionality from their Extended SAL Procedures may define additional (GUID,
FunctionID) pairs.
IV-11.2. Extended SAL Boot Service Protocol IV-130UEFI Platform Initialization Specification, Release 1.8
IV-11.2.2 EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.AddSalSystemTableInfo()
Summary
Adds platform specific information to the to the header of the SAL System Table.
Prototype
typedef
(EFIAPI *EXTENDED_SAL_ADD_SST_INFO) (
IN EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *This,
IN UINT16 SalAVersion,
IN UINT16 SalBVersion,
IN CHAR8 *OemId,
IN CHAR8 *ProductId
);
This
A pointer to the EXTENDED_SAL_BOOT_SERVICE_PROTOCOL instance.
SalAVersion
Version of recovery SAL PEIM(s) in BCD format. Higher byte contains the major revision and the lower byte
contains the minor revision.
SalBVersion
VersionofDXESALDriverinBCDformat. Higherbytecontainsthemajorrevisionandthelowerbytecontains
the minor revision.
OemId
A pointer to a Null-terminated ASCII string that contains OEM unique string. The string cannot be longer than
32 bytes in total length.
ProductId
ApointertoaNull-terminatedASCIIstringthatuniquelyidentifiesafamilyofcompatibleproducts. Thestring
cannot be longer than 32 bytes in total length.
This functionupdates theplatform specificinformation inthe SALSystem Tableheader. The SAL_A_VERSION field
oftheSALSystemTableissettothevaluespecifiedby SalAVersion . TheSAL_B_VERSION fieldoftheSALSystem
Table is set to the value specified by SalBVersion . TheOEM_ID field of the SAL System Table is filled in with the
contentsoftheNull-terminatedASCIIstringspecifiedby OemId. IfOemIdisNULLorthelengthof OemIdisgreater
than32characters,then EFI_INVALID_PARAMETER isreturned. The PRODUCT_ID fieldoftheSALSystemTable
is filled in with the contents of the Null-terminated ASCII string specified by ProductId . IfProductId isNULLor
the length of ProductId is greater than 32 characters, then EFI_INVALID_PARAMETER is returned. This function
is also responsible for re-computing the CHECKSUM field of the SAL System Table after the SAL_A_REVISION ,
SAL_B_REVISION ,OEM_ID , andPRODUCT_ID fields have been filled in. Once the CHEKSUM field has been
updated,EFI_SUCCESS is returned.
EFI_SUCCESS The SAL System Table header was updated successfully
EFI_INVALID_PARAMETER OemId is NULL
EFI_INVALID_PARAMETER ProductId is NULL
EFI_INVALID_PARAMETER The length of OemId is greater than 32 characters
EFI_INVALID_PARAMETER The length of ProductId is greater than 32 characters
IV-11.2. Extended SAL Boot Service Protocol IV-131UEFI Platform Initialization Specification, Release 1.8
IV-11.2.3 EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.AddSalSystemTableEntry()
Summary
Adds an entry to the SAL System Table.
Prototype
typedef
(EFIAPI *EXTENDED_SAL_ADD_SST_ENTRY) (
IN UINT8 *TableEntry,
IN UINTN EntrySize
);
This
TableEntry
Pointer to a buffer containing a SAL System Table entry that is EntrySize bytes in length. The first byte of
theTableEntry describes the type of entry. See the Intel Itanium Processor Family System Abstraction Layer
Specification* for more details.
EntrySize
The size, in bytes, of TableEntry .
This function adds the SAL System Table Entry specified by TableEntry andEntrySize to the SAL System Table. If
TableEntry isNULL,thenEFI_INVALID_PARAMETER isreturned. Iftheentrytypespecifiedin TableEntry isinvalid,
thenEFI_INVALID_PARAMETER is returned. If the length of the TableEntry is not valid for the entry type specified
inTableEntry , thenEFI_INVALID_PARAMETER is returned. Otherwise, TableEntry is added to the SAL System
Table. This function is also responsible for re-computing the CHECKSUM field of the SAL System Table. Once the
CHEKSUM field has been updated, EFI_SUCCESS is returned.
EFI_SUCCESS The SAL System Table was updated successfully
EFI_INVALID_PARAMETER TableEntry is NULL.
EFI_INVALID_PARAMETER TableEntry specifies an invalid entry type.
EFI_INVALID_PARAMETER EntrySize is not valid for this type of entry.
IV-11.2.4 EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.AddExtendedSalProc()
Summary
Registers an Extended SAL Procedure.
Prototype
typedef
(EFIAPI *EXTENDED_SAL_REGISTER_INTERNAL_PROC) (
IV-11.2. Extended SAL Boot Service Protocol IV-132UEFI Platform Initialization Specification, Release 1.8
IN UINT64 ClassGuidLo,
IN UINT64 ClassGuidHi,
IN UINT64 FunctionId,
IN SAL_INTERNAL_EXTENDED_SAL_PROC InternalSalProc,
IN VOID \
*PhysicalModuleGlobal OPTIONAL
);
This

Summary
Prototype
typedef
IN VOID \
);
This
ClassGuidLo
The lower 64-bits of the class GUID for the Extended SAL Procedure being added. Each class GUID contains
one or more functions specified by a Function ID.
ClassGuidHi
The upper 64-bits of the class GUID for the Extended SAL Procedure being added. Each class GUID contains
FunctionId
The Function ID for the Extended SAL Procedure that is being added. This Function ID is a member of the
Extended SAL Procedure class specified by ClassGuidLo and ClassGuidHi .
InternalSalProc
A pointer to the Extended SAL Procedure being added. The Extended SAL Procedure is named by the GUID
and Function ID specified by ClassGuidLo ,ClassGuidHi , andFunctionId .
PhysicalModuleGlobal
Pointer to a module global structure. This is a physical mode pointer. This pointer is passed to the Extended
SALProcedurespecifiedby ClassGuidLo ,ClassGuidHi ,FunctionId ,andInternalSalProc . Ifthesystemisin
physicalmode,thenthispointerispassedunmodifiedto InternalSalProc . Ifthesystemisinvirtualmode,then
thevirtualaddressassociatedwiththispointerispassedto InternalSalProc . Thisparameterisoptionalandmay
beNULL. If it isNULL, thenNULLis always passed to InternalSalProc .
typedef
SAL_RETURN_REGS
(EFIAPI *SAL_INTERNAL_EXTENDED_SAL_PROC) (
IN UINT64 Arg2,
IN UINT64 Arg3,
IN UINT64 Arg4,
IN UINT64 Arg5,
IN UINT64 Arg6,
IN UINT64 Arg7,
IN UINT64 Arg8,
IN BOOLEAN VirtualMode,
IN VOID *ModuleGlobal OPTIONAL
);
The Function ID associated with this Extended SAL Procedure.
IV-11.2. Extended SAL Boot Service Protocol IV-133UEFI Platform Initialization Specification, Release 1.8
Arg2
Second argument to the Extended SAL procedure.
Arg3
Third argument to the Extended SAL procedure.
Arg4
Fourth argument to the Extended SAL procedure.
Arg5
Fifth argument to the Extended SAL procedure.
Arg6
Sixth argument to the Extended SAL procedure.
Arg7
Seventh argument to the Extended SAL procedure.
Arg8
Eighth argument to the Extended SAL procedure.
TRUEiftheExtendedSALProcedureisbeinginvokedinvirtualmode. FALSEiftheExtendedSALProcedure
is being invoked in physical mode.
A pointer to the global context associated with this Extended SAL Procedure.
TheExtendedSALProcedure specifiedbyInternalSalProcandnamedbyClassGuidLo ,ClassGuidHi ,andFunctionId
isaddedtothesetofavailableExtendedSALProcedures. EachExtendedSALProcedureisallowedonemoduleglobal
to record any state information required during the execution of the Extended SAL Procedure. This module global is
specified by PhysicalModuleGlobal .
If there are not enough resource available to add the Extended SAL Procedure, then EFI_OUT_OF_RESOURCES is
returned.
If the Extended SAL Procedure specified by InternalSalProc and named by ClassGuidLo ,ClassGuidHi , andFunc-
tionIdwas not previously registered, then the Extended SAL Procedure along with its module global specified by
PhysicalModuleGlobal is added to the set of Extended SAL Procedures, and EFI_SUCCESS is returned.
tionIdwaspreviouslyregistered,thenthemoduleglobalisreplacedwith PhysicalModuleGlobal ,andEFI_SUCCESS
EFI_SUCCESS The Extended SAL Procedure was added
EFI_OUT_OF_RESOURCES There are not enough resources available to add the Extended SAL
Procedure
IV-11.2. Extended SAL Boot Service Protocol IV-134UEFI Platform Initialization Specification, Release 1.8
IV-11.2.5 EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.ExtendedSalProc()
Summary
Calls a previously registered Extended SAL Procedure.
Prototype
typedef
(EFIAPI *EXTENDED_SAL_PROC) (
IN UINT64 Arg8
);
The lower 64-bits of the class GUID for the Extended SAL Procedure that is being called.
The upper 64-bits of the class GUID for the Extended SAL Procedure that is being called.
Function ID for the Extended SAL Procedure being called.
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function calls the Extended SAL Procedure specified by ClassGuidLo ,ClassGuidHi , andFunctionId . The set
ofpreviouslyregisteredExtendedSALProceduresissearchedforamatching ClassGuidLo ,ClassGuidHi ,andFunc-
tionId. Ifamatchisnotfound,then EFI_SAL_NOT_IMPLEMENTED isreturned. Themoduleglobalassociatedwith
ClassGuidLo ,ClassGuidHi ,andFunctionId isretrieved. Ifthatmoduleglobalisnot NULLandthesystemisinvirtual
IV-11.2. Extended SAL Boot Service Protocol IV-135UEFI Platform Initialization Specification, Release 1.8
mode, and the virtual address of the module global is not available, then EFI_SAL_VIRTUAL_ADDRESS_ERROR is
returned. Otherwise, the Extended SAL Procedure associated with ClassGuidLo ,ClassGuidHi , andFunctionId is
called. Theargumentsspecifiedby FunctionId ,Arg2,Arg3,Arg4,Arg5,Arg6,Arg7,andArg8arepassedintothe
Extended SAL Procedure along with the VirtrualMode flag andModuleGlobal pointer.
If the system is in physical mode, then the ModuleGlobal that was originally registered with AddExtendedSalProc()
is passed into the Extended SAL Procedure. If the system is in virtual mode, then the virtual address associated with
ModuleGlobal ispassedtotheExtendedSALProcedure. TheEFIRuntimeService ConvertPointer() isusedtoconvert
the physical address of ModuleGlobal to a virtual address. If ModuleGlobal was registered as NULL, thenNULLis
always passed into the Extended SAL Procedure.
The return status from this Extended SAL Procedure is returned.
EFI_SAL_NOT_IMPLEMENTED The Extended SAL Procedure specified by ClassGuidLo Class-
GuidHi and FunctionId has not been registered
EFI_SAL_VIRTUAL_ADDRESS_ERROR Thisfunctionwascalledinvirtualmodebeforevirtualmappingsfor
the specified Extended SAL Procedure are available
Other The result returned from the specified Extended SAL Procedure
IV-11.3 Extended SAL Service Classes
This chapter contains the standard set of Extended SAL service classes. These include EFI Runtime Services in the
UEFI 2.0 Specification , SAL Procedures required by the Intel Itanium Processor Family System Abstraction Layer
Specification ,servicesrequiredtoabstractaccesstohardwaredevices,andservicesrequiredinthehandlingofMCA,
INIT, and PMI flows. Extended SAL Service Classes behave like PPIs and Protocols. They are named by GUID and
containasetofservicesforeachGUID.ThisalsoallowsplatformdeveloperstoaddnewExtendedSALserviceclasses
over time to implement platform specific features that require the Extended SAL capabilities.
ThefollowingtableslisttheExtendedSALServiceClassesdefinedbythisspecification. Thefollowingsectionscontain
detailed descriptions of the functions in each of the classes.
Table 11.1: Extended SAL Service Classes - EFI Runtime Services
Real Time Clock Services Class TheExtendedSALRealTimeClockServicesClasspro-
vides functions to access the real time clock
Reset Services Class The Extended SAL Reset Services Class provides plat-
form reset services
Status Code Services Class TheExtendedSALStatusCodeServicesClassprovides
services to report status code information
Monotonic Counter Services Class The Extended SAL Monotonic Counter Services Class
provides functions to access the monotonic counter
Variable Services Class The Extended SAL Variable Services Class provides
functions to access EFI variables
IV-11.3. Extended SAL Service Classes IV-136UEFI Platform Initialization Specification, Release 1.8
Table 11.2: Extended SAL Service Classes - SAL Procedures
Base Services Class The Extended SAL Base Services Classprovides base
services that do not haveany hardware dependencies in-
cludinganumberofSALProceduresrequiredbythe In-
tel Itanium Processor Family SystemAbstraction Layer
Cache Services Class The Extended SAL Cache Services Classprovides ser-
vices to initialize and flushthe caches.
PAL Services Class TheExtendedSALPALServicesClassprovidesservices
to make PAL calls.
PCI Services Class TheExtendedSALPCIServicesClassprovidesservices
to perform PCIconfiguration cycles.
MCA Log Services Class The Extended SAL MCA Log Services Classprovides
logging services for MCA events.
Table 11.3: Extended SAL Service Classes - HardwareAbstractions
Base I O Services Class TheExtendedSALBaseIOServicesClassprovidesthe
basic abstractions for accessing I O ports and MMIO

Stall Services Class The Extended SAL Stall Services Class provides func-
tions to perform calibrated delays
Firmware Volume Block Services Class The Extended SAL Firmware Volume Block Services
Class provides services that are equivalent to the
Firmware Volume Block Protocol in the Platform Ini-
tialization Specification
Table 11.4: Extended SAL Service Classes - Other
MP Services Class TheExtendedSALMPServicesClassprovidesservices
for managing multiple CPUs.
MCA Services Class TBD
IV-11.3.1 Extended SAL Base I/O Services Class
Summary
The Extended SAL Base I/O Services Class provides the basic abstractions for accessing I/O ports and MMIO.
GUID
#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO \
0x451531e15aea42b5
#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI \
0xa6657525d5b831bc
#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID \
{0x5aea42b5,0x31e1,0x4515,
{0xbc,0x31,0xb8,0xd5,0x25,0x75,0x65,0xa6}}
IV-11.3. Extended SAL Service Classes IV-137UEFI Platform Initialization Specification, Release 1.8
IoReadFunctionId,
IoWriteFunctionId,
MemReadFunctionId,
MemWriteFunctionId,
} EFI_EXTENDED_SAL_BASE_IO_SERVICES_FUNC_ID;
Table 11.5: Extended SAL Base I/O Services Class
ExtendedSalIoRead ThisfunctionisequivalentinfunctionalitytotheIoReadfunctionof
the CPU I O PPI See Volume1 Platform Initialization Specification
Section72ThefunctionprototypefortheIoReadserviceisshown
ExtendedSalIoWrite ThisfunctionisequivalentinfunctionalitytotheIoWritefunctionof
Section72ThefunctionprototypefortheIoWriteserviceisshown
ExtendedSalMemRead This function is equivalent in functionality to the Mem Read func-
tionoftheCPUIOPPISeeVolume1PlatformInitializationSpecifi-
cationSection72ThefunctionprototypefortheMemReadservice
is shown in Related Definitions
ExtendedSalMemWrite This function is equivalent in functionality to the Mem Write func-
cationSection72ThefunctionprototypefortheMemWriteservice
IV-11.3.2 ExtendedSalIoRead
Summary
This function is equivalent in functionality to the Io.Read() function of the CPU I/O PPI. See Volume1:Platform Ini-
tializationSpecificationSection7.2. ThefunctionprototypefortheIo.Read()serviceisshowninRelatedDefinitions.
Prototype
EFIAPI
ExtendedSalIoRead (
);
IV-11.3. Extended SAL Service Classes IV-138UEFI Platform Initialization Specification, Release 1.8
Must beEsalIoReadFunctionId .
Arg2
Signifies the width of the I/O read operation. This argument is interpreted as type
EFI_PEI_CPU_IO_PPI_WIDTH . See the Width parameter in Related Definitions.
Arg3
ThebaseaddressoftheI/Oreadoperation. ThisargumentisinterpretedasaUINT64. SeetheAddressparameter
in Related Definitions.
Arg4
ThenumberofI/Oreadoperationstoperform. Thisargumentisinterpretedasa UINTN.SeetheCountparameter
Arg5
The destination buffer to store the results. This argument is interpreted as a VOID *. See the Buffer parameter
Arg6
Reserved. Must be zero.
Arg7
Arg8
A pointer to the global context associated with this Extended SAL Procedure. Implementation dependent.
typedef
IN EFI_PEI_CPU_IO_PPI *This,
);
This function performs the equivalent operation as the Io.Read() function in the CPU I/O PPI. If this func-
tion is called in virtual mode before any required mapping have been converted to virtual addresses, then
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the status from performing the Io.Read() function of
the CPU I/O PPI is returned.
IV-11.3. Extended SAL Service Classes IV-139UEFI Platform Initialization Specification, Release 1.8
Other See the return status codes for the Io Read function in the CPU I O
PPI
IV-11.3.3 ExtendedSalIoWrite
Summary
This function is equivalent in functionality to the Io.Write() function of the CPU I/O PPI. See Volume1:Platform Ini-
tializationSpecificationSection7.2. ThefunctionprototypefortheIo.Write()serviceisshowninRelatedDefinitions.
Prototype
EFIAPI
ExtendedSalIoWrite (
);
Must beEsalIoWriteFunctionId .
Arg2
Signifies the width of the I/O write operation. This argument is interpreted as type
EFI_PEI_CPU_IO_PPI_WIDTH . See theWidthparameter in Related Definitions.
Arg3
The base address of the I/O write operation. This argument is interpreted as a UINT64. See the Address
parameter in Related Definitions.
Arg4
The number of I/O write operations to perform. This argument is interpreted as a UINTN. See the Count
Arg5
The source buffer of the value to write. This argument is interpreted as a VOID *. See the Bufferparameter in
Related Definitions.
Arg6
Arg7
IV-11.3. Extended SAL Service Classes IV-140UEFI Platform Initialization Specification, Release 1.8
Arg8
typedef
);
This function performs the equivalent operation as the Io.Write() function in the CPU I/O PPI. If this func-
EFI_SAL_VIRTUAL_ADDRESS_ERROR isreturned. Otherwise,thestatusfromperformingthe Io.Write() functionof
Other See the return status codes for the Io Write function in the CPU I O
PPI
IV-11.3.4 ExtendedSalMemRead
Summary
This function is equivalent in functionality to the Mem.Read() function of the CPU I/O PPI. See Volume 1:Platform
Initialization Specification Section 7.2. The function prototype for the Mem.Read() service is shown in Related Defi-
nitions.
Prototype
EFIAPI
ExtendedSalMemRead (
IV-11.3. Extended SAL Service Classes IV-141UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalMemReadFunctionId .
Arg2
Signifies the width of the MMIO read operation. This argument is interpreted as type
Arg3
The base address of the MMIO read operation. This argument is interpreted as a UINT64. See the Address
Arg4
The number of MMIO read operations to perform. This argument is interpreted as a UINTN. See the Count
Arg5
The destination buffer to store the results. This argument is interpreted as a VOID *. See the Bufferparameter
Arg6
Arg7
Arg8
typedef
);

Arg4
Arg5
Arg6
Arg7
Arg8
typedef
);
IV-11.3. Extended SAL Service Classes IV-142UEFI Platform Initialization Specification, Release 1.8
This function performs the equivalent operation as the Mem.Read() function in the CPU I/O PPI. If this func-
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the status from performing the Mem.Read() func-
tion of the CPU I/O PPI is returned.
Other SeethereturnstatuscodesfortheMemReadfunctionintheCPUI
O PPI
IV-11.3.5 ExtendedSalMemWrite
Summary
This function is equivalent in functionality to the Mem.Write() function of the CPU I/O PPI. See Volume 1:Platform
Initialization Specification Section 7.2. The function prototype for the Mem.Write() service is shown in Related Defi-
nitions.
Prototype
EFIAPI
ExtendedSalMemWrite (
);
Must beEsalMemWriteFunctionId .
Arg2
Signifies the width of the MMIO write operation. This argument is interpreted as type
Arg3
The base address of the MMIO write operation. This argument is interpreted as a UINT64. See the Address
Arg4
The number of MMIO write operations to perform. This argument is interpreted as a UINTN. See the Count
Arg5
IV-11.3. Extended SAL Service Classes IV-143UEFI Platform Initialization Specification, Release 1.8
Arg6
Arg7
Arg8
typedef
);
This function performs the equivalent operation as the Mem.Write() function in the CPU I/O PPI. If this func-
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the status from performing the Mem.Write() func-
Other SeethereturnstatuscodesfortheMemWritefunctionintheCPUI
O PPI
IV-11.4 Extended SAL Stall Services Class
Summary
The Extended SAL Stall Services Class provides functions to perform calibrated delays.
GUID
#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO \
0x4d8cac2753a58d06
#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI \
0x704165808af0e9b5
#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID \
IV-11.4. Extended SAL Stall Services Class IV-144UEFI Platform Initialization Specification, Release 1.8
{0x53a58d06,0xac27,0x4d8c,\
{0xb5,0xe9,0xf0,0x8a,0x80,0x65,0x41,0x70}}
StallFunctionId,
} EFI_EXTENDED_SAL_STALL_FUNC_ID;
Table 11.6: Extended SAL Stall Services Class
ExtendedSalStall This function is equivalent in functionality to the EFI Boot Service
StallSeeUEFI20SpecificationSection65Thefunctionprototype
for the Stall service is shown in Related Definitions
IV-11.4.1 ExtendedSalStall
Summary
This function is equivalent in functionality to the EFI Boot Service Stall(). See UEFI 2.0 Specification Section 6.5.
The function prototype for the Stall()service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalStall (
);
Must beEsalStallFunctionId .
Arg2
Specifiesthedelayinmicroseconds. Thisargumentisinterpretedastype UINTN.SeeMicroseconds inRelated
Definitions.
Arg3
Arg4
IV-11.4. Extended SAL Stall Services Class IV-145UEFI Platform Initialization Specification, Release 1.8
Arg5
Arg6
Arg7
Arg8
typedef
);
This function performs the equivalent operation as the Stall()function in the EFI Boot Services Table. If this
function is called in virtual mode before any required mapping have been converted to virtual addresses, then
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the Stall()
function of the EFI Boot Services Table is returned.
Other See the return status codes for the Stall function in the EFI Boot
Services Table
IV-11.4.2 Extended SAL Real Time Clock Services Class
Summary
The Extended SAL Real Time Clock Services Class provides functions to access the real time clock.
GUID
#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID_LO \
0x4d02efdb7e97a470
#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID_HI \
0x96a27bd29061ce8f
#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID \
{0x7e97a470,0xefdb,0x4d02, \
{0x8f,0xce,0x61,0x90,0xd2,0x7b,0xa2,0x96}
IV-11.4. Extended SAL Stall Services Class IV-146UEFI Platform Initialization Specification, Release 1.8
GetTimeFunctionId,
SetTimeFunctionId,
GetWakeupTimeFunctionId,
SetWakeupTimeFunctionId,
GetRtcClassMaxFunctionId
InitializeThresholdFunctionId,
BumpThresholdCountFunctionId,
GetThresholdCountFunctionId
} EFI_EXTENDED_SAL_RTC_SERVICES_FUNC_ID;
Table 11.7: Extended SAL Real Time Clock ServicesClass
ExtendedSalGetTime This function is equivalent in functionality to the EFI Boot Service
GetTime See UEFI 2 0 Specification Section 7 2 The function pro-
totype for the GetTime service is shown in Related Definitions
ExtendedSalSetTime This function is equivalent in functionality to the EFI Runtime Ser-
vice SetTime See UEFI 2 0 Specification Section 7 2 The function
prototype for the SetTime service is shown in Related Definitions
ExtendedSalGetWakeupTime This function is equivalent in functionality to the EFI Runtime Ser-
vice GetWakeupTime See UEFI 2 0 Specification Section 7 2 The
function prototype for the GetWakeupTime service is shown in Re-
lated Definitions
ExtendedSalSetWakeupTime This function is equivalent in functionality to the EFI Runtime Ser-
vice SetWakeupTime See UEFI 2 0 Specification Section 7 2 The
function prototype for the SetWakeupTime service is shown in Re-
IV-11.4.3 ExtendedSalGetTime
Summary
ThisfunctionisequivalentinfunctionalitytotheEFIRuntimeService GetTime() . SeeUEFI2.0Specification Section
7.2. The function prototype for the GetTime() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalGetTime (
IV-11.4. Extended SAL Stall Services Class IV-147UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalGetTimeFunctionId .
Arg2
This argument is interpreted as a pointer to an EFI_TIME structure. See Timein Related Definitions.
Arg3
Thisargumentisinterpretedasapointertoan EFI_TIME_CAPABILITIES structure. See Capabilities inRelated
Arg4
Arg5
Arg6
Arg7
Arg8

);
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_GET_TIME) (
);
This function performs the equivalent operation as the GetTime() function in the EFI Runtime Services Table. If
this function is called in virtual mode before any required mapping have been converted to virtual addresses, then
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the GetTime()
function of the EFI Runtime Services Table is returned.
Other SeethereturnstatuscodesfortheGetTimefunctionintheEFIRun-
time Services Table
IV-11.4. Extended SAL Stall Services Class IV-148UEFI Platform Initialization Specification, Release 1.8
IV-11.4.4 ExtendedSalSetTime
Summary
ThisfunctionisequivalentinfunctionalitytotheEFIRuntimeService SetTime() . SeeUEFI2.0Specification Section
7.2. The function prototype for the SetTime() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalSetTime (
);
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
TRUEif the Extended SAL Procedure is being invoked in virtual mode. FALSEif the Extended SAL Procedure
IV-11.4. Extended SAL Stall Services Class IV-149UEFI Platform Initialization Specification, Release 1.8
typedef
(EFIAPI *EFI_SET_TIME) (
);
This function performs the equivalent operation as the SetTime() function in the EFI Runtime Services Table. If
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the SetTime()
Other SeethereturnstatuscodesfortheSetTimefunctionintheEFIRun-
IV-11.4.5 ExtendedSalGetWakeupTime
Summary
ThisfunctionisequivalentinfunctionalitytotheEFIRuntimeService GetWakeupTime() . SeeUEFI2.0Specification
Section 7.2. The function prototype for the GetWakeupTime() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalGetWakeupTime (
);
Must be EsalGetWakeupTimeFunctionId.
Arg2
This argument is interpreted as a pointer to a BOOLEAN value. See Enabledin Related Definitions.
Arg3
This argument is interpreted as a pointer to a BOOLEAN value. See Pendingin Related Definitions.
IV-11.4. Extended SAL Stall Services Class IV-150UEFI Platform Initialization Specification, Release 1.8
Arg4
Arg5
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_GET_WAKEUP_TIME) (
);
Thisfunctionperformstheequivalentoperationasthe GetWakeupTime() functionintheEFIRuntimeServicesTable.
If this function is called in virtual mode before any required mapping have been converted to virtual addresses, then
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the GetWake-
upTime() function of the EFI Runtime Services Table is returned.
Other See the return status codes for the GetWakeupTime function in the
EFI Runtime Services Table
IV-11.4.6 ExtendedSalSetWakeupTime
Summary
ThisfunctionisequivalentinfunctionalitytotheEFIRuntimeService SetWakeupTime() . SeeUEFI2.0Specification
Section 7.2. The function prototype for the SetWakeupTime() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalSetWakeupTime (
IV-11.4. Extended SAL Stall Services Class IV-151UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalSetWakeupTimeFunctionId .
Arg2
This argument is interpreted as a BOOLEAN value. See Enablein Related Definitions.
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_SET_WAKEUP_TIME) (
);
.._description-16
IV-11.4. Extended SAL Stall Services Class IV-152UEFI Platform Initialization Specification, Release 1.8
This function performs the equivalent operation as the SetWakeupTime() function in the EFI Runtime Services Table.
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the SetWake-
Other See the return status codes for the SetWakeupTime function in the
IV-11.4.7 Extended SAL Reset Services Class
Summary
The Extended SAL Reset Services Class provides platform reset services.
GUID
#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID_LO \
0x46f58ce17d019990
#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID_HI \
0xa06a6798513c76a7
#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID \
{0x7d019990,0x8ce1,0x46f5,
{0xa7,0x76,0x3c,0x51,0x98,0x67,0x6a,0xa0}}
ResetSystemFunctionId,
} EFI_EXTENDED_SAL_RESET_FUNC_ID;
Table 11.8: Extended SAL Reset Services Class
ExtendedSalResetSystem This function is equivalent in functionality to the EFI Runtime Ser-
viceResetSystemSeeUEFI20SpecificationSection741Thefunc-
tionprototypefortheResetSystemserviceisshowninRelatedDef-
initions
IV-11.4.8 ExtendedSalResetSystem
Summary
This function is equivalent in functionality to the EFI Runtime Service ResetSystem() . SeeUEFI 2.0 Specification
Section 7.4.1. The function prototype for the ResetSystem() service is shown in Related Definitions.
Prototype
IV-11.4. Extended SAL Stall Services Class IV-153UEFI Platform Initialization Specification, Release 1.8
EFIAPI
ExtendedSalResetSystem (
);
Must beEsalResetSystemFunctionId .
Arg2
This argument is interpreted as a EFI_RESET_TYPE value. See ResetType in Related Definitions.
Arg3
This argument is interpreted as EFI_STATUS value. See ResetStatus in Related Definitions.
Arg4
This argument is interpreted as UINTNvalue. See DataSize in Related Definitions.
Arg5

initions
Summary
Prototype
EFIAPI
);
Arg2
Arg3
Arg4
Arg5
This argument is interpreted a pointer to a Unicode string. See ResetData in Related Definitions.
Arg6
Arg7
Arg8
typedef
VOID
(EFIAPI *EFI_RESET_SYSTEM) (
IN CHAR16 *ResetData OPTIONAL
);
IV-11.4. Extended SAL Stall Services Class IV-154UEFI Platform Initialization Specification, Release 1.8
This function performs the equivalent operation as the ResetSystem() function in the EFI Runtime Services Table.
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the Reset-
System() function of the EFI Runtime Services Table is returned.
Other See the return status codes for the ResetSystem function in the EFI
Runtime Services Table
IV-11.4.9 Extended SAL PCI Services Class
Summary
The Extended SAL PCI Services Class provides services to perform PCI configuration cycles.
GUID
#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO \
0x4905ad66a46b1a31
#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI \
0x6330dc59462bf692
#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID \
{0xa46b1a31,0xad66,0x4905,
{0x92,0xf6,0x2b,0x46,0x59,0xdc,0x30,0x63}}
SalPciConfigReadFunctionId,
SalPciConfigWriteFunctionId,
} EFI_EXTENDED_SAL_PCI_SERVICES_FUNC_ID;
Table 11.9: Extended SAL PCI Services Class
ExtendedSalPciRead This function is equivalent in functionality to the SAL Procedure
SAL_PCI_CONFIG_READSeetheIntelItaniumProcessorFamily
System Abstraction Layer Specification Chapter 9
ExtendedSalPciWrite This function is equivalent in functionality to the SAL Procedure
SAL_PCI_CONFIG_WRITE See the Intel Itanium Processor Fam-
ily System Abstraction Layer Specification Chapter 9
IV-11.4. Extended SAL Stall Services Class IV-155UEFI Platform Initialization Specification, Release 1.8
IV-11.4.10 ExtendedSalPciRead
Summary
This function is equivalent in functionality to the SAL Procedure SAL_PCI_CONFIG_READ . See the Intel Itanium
Processor Family System Abstraction Layer Specification Chapter 9.
Prototype
EFIAPI
ExtendedSalPciRead (
);
Must beEsalPciReadFunctionId .
Arg2
addressparameter to SAL_PCI_CONFIG_WRITE .
Arg3
sizeparameter to SAL_PCI_CONFIG_WRITE .
Arg4
address_type parameter to SAL_PCI_CONFIG_WRITE .
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-156UEFI Platform Initialization Specification, Release 1.8
IV-11.4.11 ExtendedSalPciWrite
Summary
This function is equivalent in functionality to the SAL Procedure SAL_PCI_CONFIG_WRITE . See theIntel Itanium
Prototype
EFIAPI
ExtendedSalPciWrite (
);
Must beEsalPciWriteFunctionId .
Arg2
Arg3
Arg4
valueparameter to SAL_PCI_CONFIG_WRITE .
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-157UEFI Platform Initialization Specification, Release 1.8
IV-11.4.12 Extended SAL Cache Services Class
Summary
The Extended SAL Cache Services Class provides services to initialize and flush the caches.
GUID
#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO \
0x4ba52743edc9494
#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI \
0x88f11352ef0a1888
#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID \
{0xedc9494,0x2743,0x4ba5,\
{0x88,0x18,0x0a,0xef,0x52,0x13,0xf1,0x88}}
SalCacheInitFunctionId,
SalCacheFlushFunctionId,
SalCacheClassMaxFunctionId
} EFI_EXTENDED_SAL_CACHE_SERVICES_FUNC_ID;
Table 11.10: Extended SAL Cache Services Class
ExtendedSalCacheInit This function is equivalent in functionality to the SAL Procedure
SAL_CACHE_INITSeetheIntelItaniumProcessorFamilySystem
Abstraction Layer Specification Chapter 9
ExtendedSalCacheFlush This function is equivalent in functionality to the SAL Procedure
SAL_CACHE_FLUSHSeetheIntelItaniumProcessorFamilySys-
tem Abstraction Layer Specification Chapter 9
IV-11.4.13 ExtendedSalCacheInit
Summary
ThisfunctionisequivalentinfunctionalitytotheSALProcedure SAL_CACHE_INIT .SeetheIntelItaniumProcessor
Family System Abstraction Layer Specification Chapter 9.
Prototype
EFIAPI
ExtendedSalCacheInit (
IV-11.4. Extended SAL Stall Services Class IV-158UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalCacheInitFunctionId .
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4.14 ExtendedSalCacheFlush
Summary
This function is equivalent in functionality to the SAL Procedure SAL_CACHE_FLUSH . See the Intel Itanium Pro-
cessor Family System Abstraction Layer Specification Chapter 9.
Prototype
EFIAPI
ExtendedSalCacheFlush (
IV-11.4. Extended SAL Stall Services Class IV-159UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalCacheFlushFunctionId .
Arg2
i_or_dparameter in SAL_CACHE_FLUSH .
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4.15 Extended SAL PAL Services Class
Summary
The Extended SAL PAL Services Class provides services to make PAL calls.
GUID
#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO \
0x438d0fc2e1cd9d21
#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI \
0x571e966de6040397
#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID \
{0xe1cd9d21,0x0fc2,0x438d, \
{0x97,0x03,0x04,0xe6,0x6d,0x96,0x1e,0x57}}
IV-11.4. Extended SAL Stall Services Class IV-160UEFI Platform Initialization Specification, Release 1.8
PalProcFunctionId,
SetNewPalEntryFunctionId,
GetNewPalEntryFunctionId,
EsalUpdatePalFunctionId,
} EFI_EXTENDED_SAL_PAL_SERVICES_FUNC_ID;
Table 11.11: Extended SAL PAL Services Class
ExtendedSalPalProc ThisfunctionprovidesaCwrapperformakingPALProcedurecalls
SeetheIntelItaniumArchitectureSoftwareDevelopersManualVol-
ume2SystemArchitectureSection1110fordetailsonthePALcall-

Summary
GUID
ing conventions and the set of PAL Procedures
ExtendedSalSetNewPalEntry This function records the physical or virtual PAL entry point
ExtendedSalSetNewPalEntry This function retrieves the physical or virtual PAL entry point
IV-11.4.16 ExtendedSalPalProc
Summary
This function provides a C wrapper for making PAL Procedure calls. See the Intel Itanium Architecture Software
DevelopersManualVolume2: SystemArchitecture Section11.10fordetailsonthePALcallingconventionsandtheset
of PAL Procedures.
Prototype
PAL_PROC_RETURN
EFIAPI
ExtendedSalPalProc (
);
Must beEsalPalProcFunctionId .
Arg2
PAL_PROC Function ID.
Arg3
Arg2of the PAL_PROC .
IV-11.4. Extended SAL Stall Services Class IV-161UEFI Platform Initialization Specification, Release 1.8
Arg4
Arg3 of the PAL_PROC .
Arg5
Arg4 of the PAL_PROC .
Arg6
Arg7
Arg8
This function provide a C wrapper for making PAL Procedure calls. The PAL_PROC Function ID in Arg2 is used to
determine if the PAL_PROC is stacked or static. If the PAL has been shadowed, then the memory copy of the PAL is
called. Otherwise, the ROM version of the PAL is called. The caller does not need to worry whether or not the PAL
has been shadowed or not (except for the fact that some of the PAL calls don’t work until PAL has been shadowed).
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the return status from the PAL_PROC is returned.
IV-11.4.17 ExtendedSalSetNewPalEntry
Summary
This function records the physical or virtual PAL entry point.
Prototype
EFIAPI
ExtendedSalSetNewPalEntry (
);
Must beEsalSetNewPalEntryFunctionId .
IV-11.4. Extended SAL Stall Services Class IV-162UEFI Platform Initialization Specification, Release 1.8
Arg2
Thisparameterisinterpretedasa BOOLEAN .IfitisTRUE,thenPALEntryPointspecifiedby Arg3isaphysical
address. If it is FALSE, then the Pal Entry Point specified by Arg3is a virtual address.
Arg3
The PAL Entry Point that is being set.
Arg4
Arg5
Arg6
Arg7
Arg8
This function records the PAL Entry Point specified by Arg3, soPAL_PROC calls can be made with the EsalPal-
ProcFunctionId Function ID. If Arg2isTRUE, thenArg3is the physical address of the PAL Entry Point. If Arg2is
FALSE, thenArg3is the virtual address of the PAL Entry Point. If this function is called in virtual mode before any
requiredmappinghavebeenconvertedtovirtualaddresses,then EFI_SAL_VIRTUAL_ADDRESS_ERROR isreturned.
Otherwise, the EFI_SAL_SUCCESS is returned.
EFI_SAL_SUCCESS The PAL Entry Point was set
IV-11.4.18 ExtendedSalGetNewPalEntry
Summary
This function retrieves the physical or virtual PAL entry point.
Prototype
EFIAPI
ExtendedSalGetNewPalEntry (
IV-11.4. Extended SAL Stall Services Class IV-163UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalGetNewPalEntryFunctionId .
Arg2
This parameter is interpreted as a BOOLEAN. If it isTRUE, then physical address of the PAL Entry Point is
retrieved. If it is FALSE, then the virtual address of the Pal Entry Point is retrieved.
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function retrieves the PAL Entry Point that as previously set with EsalSetNewPalEntryFunctionId . If
Arg2isTRUE, then the physical address of the PAL Entry Point is returned in SAL_RETURN_REGS .r9and
EFI_SAL_SUCCESS is returned. If Arg2isFALSEand a virtual mapping for the PAL Entry Point is not available,
thenEFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. If Arg2 is FALSE and a virtual mapping for the PAL En-
try Point is available, then the virtual address of the PAL Entry Point is returned in SAL_RETURN_REGS .r9 and
EFI_SAL_SUCCESS is returned.
EFI_SAL_SUCCESS The PAL Entry Point was retrieved and returned in
SAL_RETURN_REGS r9
EFI_SAL_VIRTUAL_ADDRESS_ERROR A request for the virtual mapping of the PAL Entry Point was re-
quested and a virtual mapping is not currently available
IV-11.4. Extended SAL Stall Services Class IV-164UEFI Platform Initialization Specification, Release 1.8
IV-11.4.19 ExtendedSalUpdatePal
Summary
ThisfunctionisequivalentinfunctionalitytotheSALProcedure SAL_UPDATE_PAL .SeetheIntelItaniumProcessor
Prototype
EFIAPI
ExtendedSalUpdatePal (
);
Must beEsalUpdatePal .
Arg2
param_buf parameter to SAL_UPDATE_PAL .
Arg3
scratch_buf parameter to SAL_UPDATE_PAL .
Arg4
scratch_buf_size parameter to SAL_UPDATE_PAL .
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-165UEFI Platform Initialization Specification, Release 1.8
IV-11.4.20 Extended SAL Status Code Services Class
Summary
The Extended SAL Status Code Services Class provides services to report status code information.
GUID
#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID_LO \
0x420f55e9dbd91d
#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID_HI \
0x4fb437849f5e3996
#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID \
{0xdbd91d,0x55e9,0x420f,
{0x96,0x39,0x5e,0x9f,0x84,0x37,0xb4,0x4f}}
ReportStatusCodeServiceFunctionId,
} EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_FUNC_ID;
Table 11.12: Extended SAL Status Code Services Class
ExtendedSalReportStatusCode ThisfunctionisequivalentinfunctionalitytotheReportStatusCode
service of the Status Code Runtime Protocol See Section 12 2 of
theVolume2PlatformInitializationSpecificationDriverExecution
Environment Core Interface The function prototype for the Report-
StatusCode service is shown in Related Definitions
IV-11.4.21 ExtendedSalReportStatusCode
Summary
This function is equivalent in functionality to the ReportStatusCode() service of the Status Code Runtime Protocol.
SeeSection12.2ofthe Volume2:PlatformInitializationSpecification,DriverExecutionEnvironment,CoreInterface
. The function prototype for the ReportStatusCode() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalReportStatusCode (
IV-11.4. Extended SAL Stall Services Class IV-166UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalReportStatusCodeFunctionId .
Arg2

Summary
Prototype
EFIAPI
);
Arg2
Thisargumentisinterpretedastype EFI_STATUS_CODE_TYPE .SeetheTypeparameterinRelatedDefinitions.
Arg3
Thisargumentisinterpretedastype EFI_STATUS_CODE_VALUE .SeetheValueparameterinRelatedDefini-
tions.
Arg4
This argument is interpreted as type UINT32. See theInstanceparameter in Related Definitions.
Arg5
This argument is interpreted as a pointer to type CONST EFI_GUID . See the CallerId parameter in Related
Arg6
This argument is interpreted as pointer to type CONST EFI_STATUS_CODE_DATA . See the Dataparameter
Arg7
Arg8
typedef
);
Thisfunctionperformstheequivalentoperationasthe ReportStatusCode functionoftheStatusCodeRuntimeProtocol.
EFI_SAL_VIRTUAL_ADDRESS_ERROR isreturned. Otherwise,theoneofthestatuscodesdefinedinthe ReportSta-
tusCode() function of the Status Code Runtime Protocol is returned.
IV-11.4. Extended SAL Stall Services Class IV-167UEFI Platform Initialization Specification, Release 1.8
Other SeethereturnstatuscodesfortheReportStatusCodefunctioninthe
Status Code Runtime Protocol
IV-11.4.22 Extended SAL Monotonic Counter Services Class
Summary
The Extended SAL Monotonic Counter Services Class provides functions to access the monotonic counter.
GUID
#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID_LO \
0x408b75e8899afd18
#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID_HI \
0x54f4cd7e2e6e1aa4
#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID \
{0x899afd18,0x75e8,0x408b,\\
{0xa4,0x1a,0x6e,0x2e,0x7e,0xcd,0xf4,0x54}}
GetNextHighMotonicCountFunctionId,
} EFI_EXTENDED_SAL_MTC_SERVICES_FUNC_ID;
Table 11.13: Extended SAL Monotonic Counter ServicesClass
ExtendedSalGetNextHighMtc This function is equivalent in functionality to the EFI Runtime Ser-
viceGetNextHighMonotonicCountSeeUEFI20SpecificationSec-
tion 7 4 2 The function prototype for the GetNextHighMonotonic-
Count service is shown in Related Definitions
IV-11.4.23 ExtendedSalGetNextHighMtc
Summary
ThisfunctionisequivalentinfunctionalitytotheEFIRuntimeService GetNextHighMonotonicCount() . SeeUEFI2.0
Specification Section7.4.2. Thefunctionprototypeforthe GetNextHighMonotonicCount() serviceisshowninRelated
Prototype
EFIAPI
ExtendedSalGetNextHighMtc (
IV-11.4. Extended SAL Stall Services Class IV-168UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalGetNextHighMtcFunctionId .
Arg2
This argument is interpreted as a pointer to a UINT32. See theHighCount parameter in Related Definitions.
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_GET_NEXT_HIGH_MONO_COUNT) (
);
This function performs the equivalent operation as the GetNextHighMonotoicCount() function in the EFI Runtime
Services Table. If this function is called in virtual mode before any required mapping have been converted to virtual
addresses, then EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined
in theGetNextHighMonotonicCount() function of the EFI Runtime Services Table is returned.
IV-11.4. Extended SAL Stall Services Class IV-169UEFI Platform Initialization Specification, Release 1.8
Other See the return status codes for the GetNextHighMonotonicCount
function in the EFI Runtime Services Table
IV-11.4.24 Extended SAL Variable Services Class
Summary
The Extended SAL Variable Services Class provides functions to access EFI variables.
GUID
#define
EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID_LO \
0x4370c6414ecb6c53
#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID_HI \
0x78836e490e3bb28c
#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID \
{0x4ecb6c53,0xc641,0x4370, \
{0x8c,0xb2,0x3b,0x0e,0x49,0x6e,0x83,0x78}}
EsalGetVariableFunctionId,
EsalGetNextVariableNameFunctionId,
EsalSetVariableFunctionId,
EsalQueryVariableInfoFunctionId,
} EFI_EXTENDED_SAL_VARIABLE_SERVICES_FUNC_ID;
Table 11.14: Extended SAL Variable Services Class
ExtendedSalGetVariable This function is equivalent in functionality to the EFI Runtime Ser-
vice GetVariable See UEFI 2 0 Specification Section 7 1 The func-
tionprototypefortheGetVariableserviceisshowninRelatedDefi-
nitions
ExtendedSalGetNextVariableName This function is equivalent in functionality to the EFI Runtime Ser-
vice GetNextVariableName See UEFI 2 0 Specification Section 7
1 The function prototype for the GetNextVariableName service is
shown in Related Definitions
ExtendedSalSetVariable This function is equivalent in functionality to the EFI Runtime Ser-
vice SetVariable See UEFI 2 0 Specification Section 7 1 The func-
tion prototype for the SetVariable service is shown in Related Defi-
nitions
ExtendedSalQueryVariableInfo This function is equivalent in functionality to the EFI Runtime Ser-
viceQueryVariableInfoSeeUEFI20SpecificationSection71The
functionprototypefortheQueryVariableInfoserviceisshowninRe-
IV-11.4. Extended SAL Stall Services Class IV-170UEFI Platform Initialization Specification, Release 1.8
IV-11.4.25 ExtendedSalGetVariable
Summary
This function is equivalent in functionality to the EFI Runtime Service GetVariable() . SeeUEFI 2.0 Specification
Section 7.1. The function prototype for the GetVariable() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalGetVariable (
);
Must beEsalGetVariableFunctionId .
Arg2
This argument is interpreted as a pointer to a Unicode string. See the VariableName parameter in Related Defi-
nitions.
Arg3
Thisargumentisinterpretedasapointertoan EFI_GUID .SeetheVendorGuid parameterinRelatedDefinitions.
Arg4
This argument is interpreted as a pointer to a value of type UINT32. See the Attributes parameter in Related
Arg5
This argument is interpreted as a pointer to a value of type UINTN. See the DataSize parameter in Related
Arg6
This argument is interpreted as a pointer to a buffer with type VOID *. See the Dataparameter in Related
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-171UEFI Platform Initialization Specification, Release 1.8
typedef
(EFIAPI *EFI_GET_VARIABLE) (
);
This function performs the equivalent operation as the GetVariable() function in the EFI Runtime Services Table. If
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the GetVari-
able()function of the EFI Runtime Services Table is returned.

typedef
);
EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before virtual map-
pings for the specified Extended SAL Procedure are available
Other See the return status codes for the GetVariable function in the EFI
IV-11.4.26 ExtendedSalGetNextVariableName
Summary
ThisfunctionisequivalentinfunctionalitytotheEFIRuntimeService GetNextVariableName() . SeeUEFI2.0Speci-
ficationSection 7.1. The function prototype for the GetNextVariableName() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalGetNextVariableName (
);
Must beEsalGetNextVariableNameFunctionId .
IV-11.4. Extended SAL Stall Services Class IV-172UEFI Platform Initialization Specification, Release 1.8
Arg2
Thisargumentisinterpretedasapointertovalueoftype UINTN.SeetheVariableNameSize parameterinRelated
Arg3
ThisargumentisinterpretedasapointertoaUnicodestring. Seethe VendorName parameterinRelatedDefini-
tions.
Arg4
Thisargumentisinterpretedasapointertoavalueoftype EFI_GUID .SeetheVendorGuid parameterinRelated
Arg5
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_GET_NEXT_VARIABLE_NAME) (
);
This function performs the equivalent operation as the GetNextVariableName() function in the EFI Runtime Services
Table. Ifthisfunctioniscalledinvirtualmodebeforeanyrequiredmappinghavebeenconvertedtovirtualaddresses,
thenEFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the Get-
NextVariableName() function of the EFI Runtime Services Table is returned.
Other See the return status codes for the GetNextVariableName function
in the EFI Runtime Services Table
IV-11.4. Extended SAL Stall Services Class IV-173UEFI Platform Initialization Specification, Release 1.8
IV-11.4.27 ExtendedSalSetVariable
Summary
This function is equivalent in functionality to the EFI Runtime Service SetVariable() . SeeUEFI 2.0 Specification
Section 7.1. The function prototype for the SetVariable() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalSetVariable (
);
Must beEsalSetVariableFunctionId .
Arg2
nitions.
Arg3
Arg4
This argument is interpreted as a value of type UINT32. See theAttributes parameter in Related Definitions.
Arg5
This argument is interpreted as a value of type UINTN. See theDataSize parameter in Related Definitions.
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-174UEFI Platform Initialization Specification, Release 1.8
typedef
(EFIAPI \*EFI_SET_VARIABLE) (
);
This function performs the equivalent operation as the SetVariable() function in the EFI Runtime Services Table. If
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the SetVari-
Other See the return status codes for the SetVariable function in the EFI
IV-11.4.28 ExtendedSalQueryVariableInfo
Summary
ThisfunctionisequivalentinfunctionalitytotheEFIRuntimeService QueryVariableInfo() . SeeUEFI2.0Specifica-
tionSection 7.1. The function prototype for the QueryVariableInfo() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalQueryVariableInfo (
);
Must beEsalQueryVariableInfoFunctionId .
Arg2
IV-11.4. Extended SAL Stall Services Class IV-175UEFI Platform Initialization Specification, Release 1.8
Arg3
This argument is interpreted as a pointer to a value of type UINT64. See the MaximumVariableStorageSize
Arg4
This argument is interpreted as a pointer to a value of type UINT64. See the RemainingVariableStorageSize
Arg5
This argument is interpreted as a pointer to a value of type UINT64. See the MaximumVariableSize parameter
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_QUERY_VARIABLE_INFO) (
);
This function performs the equivalent operation as the QueryVariableInfo() function in the EFI Runtime Services Ta-
ble. If this function is called in virtual mode before any required mapping have been converted to virtual addresses,
thenEFI_SAL_VIRTUAL_ADDRESS_ERROR isreturned. Otherwise,theoneofthestatuscodesdefinedinthe Query-
VariableInfo() function of the EFI Runtime Services Table is returned.
Other SeethereturnstatuscodesfortheQueryVariableInfofunctioninthe
IV-11.4. Extended SAL Stall Services Class IV-176UEFI Platform Initialization Specification, Release 1.8
IV-11.4.29 Extended SAL Firmware Volume Block ServicesClass
Summary
The Extended SAL Firmware Volume Block Services Class provides services that are equivalent to the Firmware
Volume Block Protocol in the Platform Initialization Specification.
GUID
#define EFI_EXTENDED_SAL_FVB_SERVICES_PROTOCOL_GUID_LO \
0x4f1dbcbba2271df1
#define EFI_EXTENDED_SAL_FVB_SERVICES_PROTOCOL_GUID_HI \
0x1a072f17bc06a998
#define EFI_EXTENDED_SAL_FVB_SERVICES_PROTOCOL_GUID \
{0xa2271df1,0xbcbb,0x4f1d,\
{0x98,0xa9,0x06,0xbc,0x17,0x2f,0x07,0x1a}}
ReadFunctionId,
WriteFunctionId,
EraseBlockFunctionId,
GetVolumeAttributesFunctionId,
SetVolumeAttributesFunctionId,
GetPhysicalAddressFunctionId,
GetBlockSizeFunctionId,
} EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_FUNC_ID;
Table 11.15: Extended SAL Variable Services Class
ExtendedSalRead This function is equivalent in functionality to the Read service of
the EFI Firmware Volume Block Protocol See Section 2 4 of the
Volume3PlatformInitializationSpecificationSharedArchitectural
Elements The function prototype for the Read service is shown in
ExtendedSalWrite This function is equivalent in functionality to the Write service of
Elements The function prototype for the Write service is shown in

ExtendedSalEraseBlock This function is equivalent in functionality to the EraseBlocks ser-
vice of the EFI Firmware Volume Block Protocol except this func-
tioncanonlyeraseoneblockperrequestSeeSection24oftheVol-
ume3PlatformInitializationSpecificationSharedArchitecturalEl-
ements The function prototype for the EraseBlock service is shown
ExtendedSalGetAttributes ThisfunctionisequivalentinfunctionalitytotheGetAttributesser-
viceoftheEFIFirmwareVolumeBlockProtocolSeeSection24of
theVolume3PlatformInitializationSpecificationSharedArchitec-
tural Elements The function prototype for the GetAttributes service
IV-11.4. Extended SAL Stall Services Class IV-177UEFI Platform Initialization Specification, Release 1.8
Table 11.15 – continued from previous page
ExtendedSalSetAttributes This function is equivalent in functionality to the SetAttributes ser-
tural Elements The function prototype for the SetAttributes service
ExtendedSalGetPhysicalAddress This function is equivalent in functionality to the GetPhysicalAd-
dress service of the EFI Firmware Volume Block Protocol See Sec-
tion24oftheVolume3PlatformInitializationSpecificationShared
Architectural Elements The function prototype for the GetPhysical-
Address service is shown in Related Definitions
ExtendedSalGetBlockSize ThisfunctionisequivalentinfunctionalitytotheGetBlockSizeser-
turalElementsThefunctionprototypefortheGetBlockSizeservice
ExtendedSalEraseCustomBlockRange ThisfunctionissimilarinfunctionalitytotheEraseBlocksserviceof
the EFI Firmware Volume Block Protocol except this function can
specify a range of blocks with offsets into the starting and ending
blockSeeSection24oftheVolume3PlatformInitializationSpec-
ification Shared Architectural Elements The function prototype for
the EraseBlock service is shown in Related Definitions
IV-11.4.30 ExtendedSalRead
Summary
Thisfunctionisequivalentinfunctionalitytothe Read()serviceoftheEFIFirmwareVolumeBlockProtocol. SeeSec-
tion2.4ofthe Volume3:PlatformInitializationSpecification,SharedArchitecturalElements . Thefunctionprototype
for theRead()service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalRead (
);
Must beEsalFvbReadFunctionId .
IV-11.4. Extended SAL Stall Services Class IV-178UEFI Platform Initialization Specification, Release 1.8
Arg2
Thisargumentisinterpretedastype UINTNthatrepresentstheFirmwareVolumeBlockinstance. Thisinstance
valueisusedtolookupa EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL .SeetheThisparameterinRelated
Arg3
This argument is interpreted as type EFI_LBA . See theLbaparameter in Related Definitions.
Arg4
This argument is interpreted as type UINTN. See theOffsetparameter in Related Definitions.
Arg5
This argument is interpreted as a pointer to type UINTN. See theNumBytes parameter in Related Definitions.
Arg6
This argument is interpreted as pointer to a buffer of type VOID *. See the Bufferparameter in Related Defini-
tions.
Arg7
Arg8
typedef
IN EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
OUT UINT8 *Buffer
);
This function performs the equivalent operation as the Read()function of the EFI Firmware Volume Block Protocol.
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the Read()
function of the EFI Firmware Volume Block Protocol is returned.
Other SeethereturnstatuscodesfortheReadfunctionintheEFIFirmware
Volume Block Protocol
IV-11.4. Extended SAL Stall Services Class IV-179UEFI Platform Initialization Specification, Release 1.8
IV-11.4.31 ExtendedSalWrite
Summary
Thisfunctionisequivalentinfunctionalitytothe Write()serviceoftheEFIFirmwareVolumeBlockProtocol. SeeSec-
for theWrite()service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalWrite (
);
Must beEsalFvbWriteFunctionId .
Arg2
Arg3
Arg4
Arg5
Arg6
tions.
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-180UEFI Platform Initialization Specification, Release 1.8
typedef
(EFIAPI *EFI_FVB_WRITE) (
);
This function performs the equivalent operation as the Write()function of the EFI Firmware Volume Block Protocol.
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the Write()
Other SeethereturnstatuscodesfortheWritefunctionintheEFIFirmware
IV-11.4.32 ExtendedSalEraseBlock
Summary
This function is equivalent in functionality to the EraseBlocks() service of the EFI Firmware Volume Block Protocol
except this function can only erase one block per request. See Section 2.4 of the Volume 3:Platform Initialization
Specification,SharedArchitecturalElements . Thefunctionprototypeforthe EraseBlock() serviceisshowninRelated
Prototype
EFIAPI
ExtendedSalEraseBlock (
);
Must beEsalFvbEraseBlockFunctionId .
IV-11.4. Extended SAL Stall Services Class IV-181UEFI Platform Initialization Specification, Release 1.8
Arg2
Arg3
Thisargumentisinterpretedastype EFI_LBA .Thisisthelogicalblockaddressinthefirmwarevolumetoerase.
Only a single block can be specified with this Extended SAL Procedure. The EraseBlocks() function in the EFI
FirmwareVolumeBlockProtocolsupportsavariablenumberofargumentsthatallowoneormoreblockranges
to be specified.
Arg4
Arg5
Arg6
Arg7
Arg8

Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_FVB_ERASE_BLOCKS) (
...
);
Thisfunctionperformstheequivalentoperationasthe EraseBlock() functionoftheEFIFirmwareVolumeBlockPro-
tocol. If this function is called in virtual mode before any required mapping have been converted to virtual addresses,
thenEFI_SAL_VIRTUAL_ADDRESS_ERROR isreturned. Otherwise,theoneofthestatuscodesdefinedinthe Erase-
Block()function of the EFI Firmware Volume Block Protocol is returned.
Other See the return status codes for the EraseBlock function in the EFI
Firmware Volume Block Protocol
IV-11.4. Extended SAL Stall Services Class IV-182UEFI Platform Initialization Specification, Release 1.8
IV-11.4.33 ExtendedSalGetAttributes
Summary
Thisfunctionisequivalentinfunctionalitytothe GetAttributes() serviceoftheEFIFirmwareVolumeBlockProtocol.
See Section 2.4 of the Volume 3:Platform Initialization Specification, Shared Architectural Elements . The function
prototype for the GetAttributes() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalGetAttributes (
);
Must beEsalFvbGetAttributesFunctionId .
Arg2
Arg3
Thisargumentisinterpretedaspointertoavalueoftype EFI_FVB_ATTRIBUTES .SeetheAttributes parameter
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-183UEFI Platform Initialization Specification, Release 1.8
(EFIAPI *EFI_FVB_GET_ATTRIBUTES) (
OUT EFI_FVB_ATTRIBUTES *Attributes
);
This function performs the equivalent operation as the GetAttributes() function of the EFI Firmware Volume Block
Protocol. If this function is called in virtual mode before any required mapping have been converted to virtual ad-
dresses, then EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in
theGetAttributes() function of the EFI Firmware Volume Block Protocol is returned.
Other SeethereturnstatuscodesfortheGetAttributesfunctionintheEFI
IV-11.4.34 ExtendedSalSetAttributes
Summary
Thisfunction isequivalentin functionalitytothe SetAttributes() serviceof theEFIFirmware VolumeBlockProtocol.
prototype for the SetAttributes() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalSetAttributes (
);
Must beEsalFvbSetAttributesFunctionId .
Arg2
IV-11.4. Extended SAL Stall Services Class IV-184UEFI Platform Initialization Specification, Release 1.8
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_FVB_SET_ATTRIBUTES) (
IN OUT EFI_FVB_ATTRIBUTES *Attributes
);
This function performs the equivalent operation as the SetAttributes() function of the EFI Firmware Volume Block
theSetAttributes() function of the EFI Firmware Volume Block Protocol is returned.
Other See the return status codes for the SetAttributes function in the EFI
IV-11.4. Extended SAL Stall Services Class IV-185UEFI Platform Initialization Specification, Release 1.8
IV-11.4.35 ExtendedSalGetPhysicalAddress
Summary
This function is equivalent in functionality to the GetPhysicalAddress() service of the EFI Firmware Volume Block
Protocol. See Section 2.4 of the Volume 3:Platform Initialization Specification, Shared Architectural Elements . The
function prototype for the GetPhysicalAddress() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalGetPhysicalAddress (
);
Must beEsalFvbGetPhysicalAddressFunctionId .
Arg2
Arg3
Thisargumentisinterpretedaspointertoavalueoftype EFI_PHYSICAL_ADDRESS .SeetheAddressparameter
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-186UEFI Platform Initialization Specification, Release 1.8
typedef
(EFIAPI *EFI_FVB_GET_PHYSICAL_ADDRESS) (
);
This function performs the equivalent operation as the GetPhysicalAddress() function of the EFI Firmware Volume
Block Protocol. If this function is called in virtual mode before any required mapping have been converted to virtual
addresses,thenEFI_SAL_VIRTUAL_ADDRESS_ERRORisreturned. Otherwise,theoneofthestatuscodesdefined
in the GetPhysicalAddress() function of the EFI Firmware Volume Block Protocol is returned.
Other See the return status codes for the GetPhysicalAddress function in
the EFI Firmware Volume Block Protocol
IV-11.4.36 ExtendedSalGetBlockSize
Summary
Thisfunctionisequivalentinfunctionalitytothe GetBlockSize() serviceoftheEFIFirmwareVolumeBlockProtocol.
prototype for the GetBlockSize() service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalGetBlockSize (
);
Must beEsalFvbGetBlockSizeFunctionId .
Arg2
value is used to lookup a EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL .
IV-11.4. Extended SAL Stall Services Class IV-187UEFI Platform Initialization Specification, Release 1.8
Arg3
This argument is interpreted as type EFI_LBA . SeeLbaparameter in Related Definitions.
Arg4

Summary
Prototype
EFIAPI
);
Arg2
Arg3
Arg4
Thisargumentisinterpretedasapointertoavalueoftype UINTN.SeeBlockSize parameterinRelatedDefini-
tions.
Arg5
This argument is interpreted as a pointer to a value of type UINTN. SeeNumberOfBlocks parameter in Related
Arg6
Arg7
Arg8
typedef
(EFIAPI *EFI_FVB_GET_BLOCK_SIZE) (
);
This function performs the equivalent operation as the GetBlockSize() function of the EFI Firmware Volume Block
theGetBlockSize() function of the EFI Firmware Volume Block Protocol is returned.
Other SeethereturnstatuscodesfortheGetBlockSizefunctionintheEFI
IV-11.4. Extended SAL Stall Services Class IV-188UEFI Platform Initialization Specification, Release 1.8
IV-11.4.37 ExtendedSalEraseCustomBlockRange
Summary
Thisfunctionissimilarinfunctionalitytothe EraseBlocks() serviceoftheEFIFirmwareVolumeBlockProtocolexcept
thisfunctioncanspecifyarangeofblockswithoffsetsintothestartingandendingblock. SeeSection2.4ofthe Volume
3:Platform Initialization Specification, Shared Architectural Elements . The function prototype for the EraseBlock()
service is shown in Related Definitions.
Prototype
EFIAPI
ExtendedSalEraseCustomBlockRange (
);
Must beEsalFvbEraseCustomBlockRangeFunctionId .
Arg2
Arg3
Thisargumentisinterpretedastype EFI_LBA .Thisisthestartinglogicalblockaddressinthefirmwarevolume
to erase.
Arg4
This argument is interpreted as type UINTN. This is the offset into the starting logical block to erase.
Arg5
Thisargumentisinterpretedastype EFI_LBA .Thisistheendinglogicalblockaddressinthefirmwarevolume
to erase.
Arg6
This argument is interpreted as type UINTN. This is the offset into the ending logical block to erase.
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-189UEFI Platform Initialization Specification, Release 1.8
typedef
...
);
This function performs a similar operation as the EraseBlock() function of the EFI Firmware Volume Block Protocol.
The main difference is that this function can perform a partial erase of the starting and ending blocks. The start of
the erase operation is specified by Arg3andArg4. The end of the erase operation is specified by Arg5andArg6.
EFI_SAL_VIRTUAL_ADDRESS_ERROR is returned. Otherwise, the one of the status codes defined in the Erase-
IV-11.4.38 Extended SAL MCA Log Services Class
Summary
The Extended SAL MCA Log Services Class provides logging services for MCA events.
GUID
#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO \
0x4c0338a3cb3fd86e
#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI \
0x7aaba2a3cf905c9a
#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID \
{0xcb3fd86e,0x38a3,0x4c03,\
{0x9a,0x5c,0x90,0xcf,0xa3,0xa2,0xab,0x7a}}
SalGetStateInfoFunctionId,
SalGetStateInfoSizeFunctionId,
SalClearStateInfoFunctionId,
SalGetStateBufferFunctionId,
SalSaveStateBufferFunctionId,
} EFI_EXTENDED_SAL_MCA_LOG_SERVICES_FUNC_ID;
IV-11.4. Extended SAL Stall Services Class IV-190UEFI Platform Initialization Specification, Release 1.8
IV-11.4.39 ExtendedSalGetStateInfo
Summary
This function is equivalent in functionality to the SAL Procedure SAL_GET_STATE_INFO . See the Intel Itanium
Prototype
EFIAPI
ExtendedSalGetStateInfo (
);
Must beEsalGetStateInfoFunctionId .
Arg2
typeparameter to SAL_GET_STATE_INFO .
Arg3
Arg4
memaddr parameter to SAL_GET_STATE_INFO .
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-191UEFI Platform Initialization Specification, Release 1.8
IV-11.4.40 ExtendedSalGetStateInfoSize
Summary
ThisfunctionisequivalentinfunctionalitytotheSALProcedure SAL_GET_STATE_INFO_SIZE .SeetheIntelItanium
Prototype
EFIAPI
ExtendedSalGetStateInfoSize (
);
Must beEsalGetStateInfoSizeFunctionId .
Arg2
typeparameter to SAL_GET_STATE_INFO_SIZE .
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-192UEFI Platform Initialization Specification, Release 1.8
IV-11.4.41 ExtendedSalClearStateInfo
Summary
This function is equivalent in functionality to the SAL Procedure SAL_CLEAR_STATE_INFO . See theIntel Itanium
Prototype
EFIAPI
ExtendedSalClearStateInfo (
);
Arg2
typeparameter to SAL_CLEAR_STATE_INFO .
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-193UEFI Platform Initialization Specification, Release 1.8
IV-11.4.42 ExtendedSalGetStateBuffer
Summary
Returns a memory buffer to store error records.
Prototype
EFIAPI
ExtendedSalGetStateBuffer (
);
Must beEsalGetStateBufferFunctionId .
Arg2
Same astypeparameter to SAL_GET_STATE_INFO .
Arg3
Arg4
Arg5

Arg5
Arg6
Arg7
Arg8
Summary
Prototype
EFIAPI
);
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function returns a memory buffer to store error records. The base address of the buffer is returned in
SAL_RETURN_REGS .r9 ,andthesizeofthebuffer,inbytes,isreturnedin SAL_RETURN_REGS .r10 . Ifabufferis
not available, then EFI_OUT_OF_RESOURCES is returned. Otherwise, EFI_SUCCESS is returned.
IV-11.4. Extended SAL Stall Services Class IV-194UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS Thememorybuffertostoreerrorrecordswasreturnedinr9andr10
EFI_OUT_OF_RESOURCES A memory buffer for string error records in not available
IV-11.4.43 ExtendedSalSaveStateBuffer
Summary
Saves a memory buffer containing an error records to nonvolatile storage.
Prototype
EFIAPI
ExtendedSalSaveStateBuffer (
);
Must beEsalSaveStateBufferFunctionId .
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-195UEFI Platform Initialization Specification, Release 1.8
This function saved a memory buffer containing an error record to nonvolatile storage.
EFI_SUCCESS The memory buffer containing the error record was written to non-
volatile storage
TBD
IV-11.4.44 Extended SAL Base Services Class
Summary
TheExtendedSALBaseServicesClassprovidesbaseservicesthatdonothaveanyhardwaredependenciesincluding
a number of SAL Procedures required by the Intel Itanium Processor Family System Abstraction Layer Specification .
GUID
#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO \
0x41c30fe0d9e9fa06
#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI \
0xf894335a4283fb96
#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID \
{0xd9e9fa06,0x0fe0,0x41c3,\
{0x96,0xfb,0x83,0x42,0x5a,0x33,0x94,0xf8}}
SalSetVectorsFunctionId,
SalMcRendezFunctionId,
SalMcSetParamsFunctionId,
EsalGetVectorsFunctionId,
EsalMcGetParamsFunctionId,
EsalMcGetMcParamsFunctionId,
EsalGetMcCheckinFlagsFunctionId,
EsalGetPlatformBaseFreqFunctionId,
EsalRegisterPhysicalAddrFunctionId,
EsalBaseClassMaxFunctionId
} EFI_EXTENDED_SAL_BASE_SERVICES_FUNC_ID;
IV-11.4. Extended SAL Stall Services Class IV-196UEFI Platform Initialization Specification, Release 1.8
Table 11.16: Extended SAL MP Services Class
Extended-
SalSetVectorsThis function is equivalent in functionality to the SAL Procedure SAL_SET_VECTORS See
the Intel Itanium Processor Family System Abstraction Layer Specification Chapter 9
ExtendedSalM-
cRendezThis function is equivalent in functionality to the SAL Procedure SAL_MC_RENDEZ See the
Intel Itanium Processor Family System Abstraction Layer Specification Chapter 9
cSetParamsThis function is equivalent in functionality to the SAL Procedure SAL_MC_SET_PARAMS
See the Intel Itanium Processor Family System Abstraction Layer Specification Chapter 9
ExtendedSal-
GetVectorsRetrieves information that was previously registered with the SAL Procedure
SAL_SET_VECTORS
cGetParamsRetrieves information that was previously registered with the SAL Procedure
SAL_MC_SET_PARAMS
cGetMcParamsRetrieves information that was previously registered with the SAL Procedure
GetMcCheckin-
FlagsUsed to determine if a specific CPU has called the SAL Procedure SAL_MC_RENDEZ
GetPlatform-
BaseFreqThis function is equivalent in functionality to the SAL Procedure SAL_FREQ_BASE with a
clock_typeof0SeetheIntelItaniumProcessorFamilySystemAbstractionLayerSpecification
Chapter 9
RegisterPhysi-
calAddrThis function is equivalent in functionality to the SAL Procedure
SAL_REGISTER_PHYSICAL_ADDR See the Intel Itanium Processor Family System
IV-11.4.45 ExtendedSalSetVectors
Summary
ThisfunctionisequivalentinfunctionalitytotheSALProcedure SAL_SET_VECTORS .SeetheIntelItaniumProcessor
Prototype
EFIAPI
ExtendedSalSetVectors (
);
Must beEsalSetVectorsFunctionId .
IV-11.4. Extended SAL Stall Services Class IV-197UEFI Platform Initialization Specification, Release 1.8
Arg2
vector_type parameter to SAL_SET_VECTORS .
Arg3
phys_addr_1 parameter to SAL_SET_VECTORS .
Arg4
gp_1parameter to SAL_SET_VECTORS .
Arg5
length_cs_1 parameter to SAL_SET_VECTORS .
Arg6
phys_addr_2 parameter to SAL_SET_VECTORS .
Arg7
gp_2parameter to SAL_SET_VECTORS .
Arg8
length_cs_2 parameter to SAL_SET_VECTORS .
IV-11.4.46 ExtendedSalMcRendez
Summary
ThisfunctionisequivalentinfunctionalitytotheSALProcedure SAL_MC_RENDEZ .SeetheIntelItaniumProcessor
Prototype
EFIAPI
ExtendedSalMcRendez (
);
Must beEsalMcRendezFunctionId .
Arg2
IV-11.4. Extended SAL Stall Services Class IV-198UEFI Platform Initialization Specification, Release 1.8
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4.47 ExtendedSalMcSetParams
Summary
This function is equivalent in functionality to the SAL Procedure SAL_MC_SET_PARAMS. See the Intel Itanium
Prototype
EFIAPI
ExtendedSalMcSetParams (
);
Must beEsalMcSetParamsFunctionId .
Arg2
param_type parameter to SAL_MC_SET_PARAMS .
Arg3
i_or_mparameter to SAL_MC_SET_PARAMS .
IV-11.4. Extended SAL Stall Services Class IV-199UEFI Platform Initialization Specification, Release 1.8
Arg4
i_or_m_val parameter to SAL_MC_SET_PARAMS .
Arg5
time_out parameter to SAL_MC_SET_PARAMS .
Arg6
mca_optparameter to SAL_MC_SET_PARAMS .
Arg7
Arg8
IV-11.4.48 ExtendedSalGetVectors
Retrieves information that was previously registered with the SAL Procedure SAL_SET_VECTORS .
Prototype
EFIAPI
ExtendedSalGetVectors (
IN BOOLEAN VirtualMode ,
);
Must beEsalGetVectorsFunctionId .
Arg2
The vector type to retrieve. 0 - MCA, 1-BSP INIT, 2 - BOOT_RENDEZ, 3 - AP INIT.
Arg3
Arg4
IV-11.4. Extended SAL Stall Services Class IV-200UEFI Platform Initialization Specification, Release 1.8
Arg5
Arg6
Arg7
Arg8

Prototype
EFIAPI
);
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function returns the vector information for the vector specified by Arg2. If the specified vector was not previ-
ously registered with the SAL Procedure SAL_SET_VECTORS , thenSAL_NO_INFORMATION_AVAILABLE is re-
turned. Otherwise, the physical address of the requested vector is returned in SAL_RETURN_REGS .r9, the global
pointer(GP) value is returned in SAL_RETURN_REGS .r10, the length and checksum information is returned in
SAL_RETURN_REGS .r10, andEFI_SUCCESS is returned.
EFI_SUCCESS The information for the requested vector was returned
SAL_NO_INFORMATION_AVAILABLE TherequestedvectorhasnotbeenregisteredwiththeSALProcedure
IV-11.4.49 ExtendedSalMcGetParams
Summary
Retrieves information that was previously registered with the SAL Procedure SAL_MC_SET_PARAMS .
Prototype
EFIAPI
ExtendedSalMcGetParams (
);
IV-11.4. Extended SAL Stall Services Class IV-201UEFI Platform Initialization Specification, Release 1.8
Must beEsalMcGetParamsFunctionId .
Arg2
The parameter type to retrieve. 1 - rendezvous interrupt, 2 - wake up, 3 - Corrected Platform Error Vector.
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
Thisfunctionreturnsinformationfortheparametertypespecifiedby Arg2thatwaspreviouslyregisteredwiththeSAL
Procedure SAL_MC_SET_PARAMS . If the parameter type specified by Arg2was not previously registered with the
SAL Procedure SAL_MC_SET_PARAMS , thenSAL_NO_INFORMATION_AVAILABLE is returned. Otherwise, the
i_or_mvalue is returned in SAL_RETURN_REGS .r9, thei_or_m_val value is returned in SAL_RETURN_REGS.
r10, andEFI_SUCCESS is returned.
IV-11.4.50 ExtendedSalMcGetMcParams
Summary
Prototype
EFIAPI
ExtendedSalMcGetMcParams (
IV-11.4. Extended SAL Stall Services Class IV-202UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalMcGetMcParamsFunctionId .
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function returns information that was previously registered with the SAL Procedure SAL_MC_SET_PARAMS
. If the information was not previously registered with the SAL Procedure SAL_MC_SET_PARAMS ,
thenSAL_NO_INFORMATION_AVAILABLE is returned. Otherwise, the rz_always value is returned in
SAL_RETURN_REGS .r9,time_out valueisreturnedin SAL_RETURN_REGS .r10,binit_escalate valueisreturned
inSAL_RETURN_REGS. r11 .
IV-11.4. Extended SAL Stall Services Class IV-203UEFI Platform Initialization Specification, Release 1.8
IV-11.4.51 ExtendedSalGetMcCheckinFlags
Summary
Used to determine if a specific CPU has called the SAL Procedure SAL_MC_RENDEZ .
Prototype
EFIAPI
ExtendedSalMcGetMcCheckinFlags (
);
Must beEsalMcGetMcChckinFlagsFunctionId .
Arg2
The index of the CPU in the set of enabled CPUs to check.
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function check to see if the CPU index specified by Arg2 has called the SAL Procedure SAL_MC_RENDEZ
. The CPU index values are assigned by the Extended SAL MP Services Class. If the CPU specified by Arg2
IV-11.4. Extended SAL Stall Services Class IV-204UEFI Platform Initialization Specification, Release 1.8
has called the SAL Procedure SAL_MC_RENDEZ , then 1 is returned in SAL_RETURN_REGS .r9. Otherwise,
SAL_RETURN_REGS .r9is set to 0. EFI_SAL_SUCCESS is always returned.
EFI_SAL_SUCCESS The checkin status of the requested CPU was returned.
IV-11.4.52 ExtendedSalGetPlatformBaseFreq
Summary
This function is equivalent in functionality to the SAL Procedure SAL_FREQ_BASE with a clock_type of 0. See the
Intel Itanium Processor Family System Abstraction Layer Specification Chapter 9.
Prototype
EFIAPI
ExtendedSalMcGetPlatformBaseFreq (
);
Must beEsalMcGetPlatformBaseFreqFunctionId .
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-205UEFI Platform Initialization Specification, Release 1.8
IV-11.4.53 ExtendedSalRegisterPhysicalAddr
Summary
This function is equivalent in functionality to the SAL Procedure SAL_REGISTER_PHYSICAL_ADDR . See theIntel
Itanium Processor Family System Abstraction Layer Specification Chapter 9.
Prototype
EFIAPI
ExtendedSalRegisterPhysicalAddr (
IN VOID *ModuleGlobalOPTIONAL
);
Must beEsalRegisterPhysicalAddrFunctionId .
Arg2
phys_entity parameter to SAL_REGISTER_PHYSICAL_ADDRESS .
Arg3
paddrparameter to SAL_REGISTER_PHYSICAL_ADDRESS .
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-206UEFI Platform Initialization Specification, Release 1.8
IV-11.4.54 Extended SAL MP Services Class
Summary
The Extended SAL MP Services Class provides services for managing multiple CPUs.
GUID
#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO \
0x4dc0cf18697d81a2
#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI \
0x3f8a613b11060d9e
#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID \
{0x697d81a2,0xcf18,0x4dc0,\
{0x9e,0x0d,0x06,0x11,0x3b,0x61,0x8a,0x3f}}
AddCpuDataFunctionId,
RemoveCpuDataFunctionId,
ModifyCpuDataFunctionId,
GetCpuDataByIdFunctionId,
GetCpuDataByIndexFunctionId,
SendIpiFunctionId,
CurrentProcInfoFunctionId,
NumProcessorsFunctionId,
SetMinStateFunctionId,
GetMinStateFunctionId,
EsalPhysicalIdInfo,
} EFI_EXTENDED_SAL_MP_SERVICES_FUNC_ID;

Summary
GUID
IV-11.4. Extended SAL Stall Services Class IV-207UEFI Platform Initialization Specification, Release 1.8
Table 11.17: Extended SAL MP Services Class
ExtendedSalAddCpuData Add a CPU to the database of CPUs
ExtendedSalRemoveCpuData Add a CPU to the database of CPUs
ExtendedSalModifyCpuData Updates the data for a CPU that is already in the database of CPUs
ExtendedSalGetCpuDataById Returns the information on a CPU specified by a Global ID
ExtendedSalGetCpuDataByIndex Returns information on a CPU specified by an index
ExtendedSalWhoAmI Returns the Global ID for the calling CPU
ExtendedSalNumProcessors Returns the number of currently enabled CPUs the total number of
CPUsandthemaximumnumberofCPUsthattheplatformsupports
ExtendedSalSetMinState Sets the MINSTATE pointer for the CPU specified by a Global ID
ExtendedSalGetMinState RetrievestheMINSTATEpointerfortheCPUspecifiedbyaGlobal
ID
ExtendedSalPhysicalIdInfo Retrieves the Physical ID of a CPU in the platform
IV-11.4.55 ExtendedSalAddCpuData
Summary
Add a CPU to the database of CPUs.
Prototype
EFIAPI
ExtendedSalAddCpuData (
);
Must beEsalAddCpuDataFunctionId .
Arg2
The 64-bit Global ID of the CPU being added.
Arg3
The enable flag for the CPU being added. This value is interpreted as type BOOLEAN .TRUEmeans the CPU
is enabled. FALSEmeans the CPU is disabled.
Arg4
The PAL Compatibility value for the CPU being added.
Arg5
The 16-bit Platform ID of the CPU being added.
IV-11.4. Extended SAL Stall Services Class IV-208UEFI Platform Initialization Specification, Release 1.8
Arg6
Arg7
Arg8
This function adds the CPU with a Global ID specified by Arg2, the enable flag specified by Arg3, and the PAL
Compatibility value specified by Arg4to the database of CPUs in the platform. If there are not enough resource
availabletoaddtheCPU,then EFI_SAL_NOT_ENOUGH_SCRATCH isreturned. Otherwise,theCPUtoaddedtothe
database, and EFI_SAL_SUCCESS is returned.
EFI_SAL_SUCCESS The CPU was added to the database
EFI_SAL_NOT_ENOUGH_SCRATCH There are not enough resource available to add the CPU
IV-11.4.56 ExtendedSalRemoveCpuData
Summary
Prototype
EFIAPI
ExtendedSalRemoveCpuData (
);
Must beEsalRemoveCpuDataFunctionId .
Arg2
IV-11.4. Extended SAL Stall Services Class IV-209UEFI Platform Initialization Specification, Release 1.8
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function removes the CPU with a Global ID specified by Arg2from the database of CPUs in the platform. If the
CPUspecifiedby Arg2isnotpresentinthedatabase,then EFI_SAL_NO_INFORMATION isreturned. Otherwise,the
CPU specified by Arg2 is removed from the database of CPUs, and EFI_SAL_SUCCESS is returned.
EFI_SAL_SUCCESS The CPU was removed from the database.
EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
IV-11.4.57 ExtendedSalModifyCpuData
Summary
Updates the data for a CPU that is already in the database of CPUs.
Prototype
EFIAPI
ExtendedSalModifyCpuData (
);
IV-11.4. Extended SAL Stall Services Class IV-210UEFI Platform Initialization Specification, Release 1.8
Must beEsalModifyCpuDataFunctionId .
Arg2
The 64-bit Global ID of the CPU being updated.
Arg3
TheenableflagfortheCPUbeingupdated. Thisvalueisinterpretedastype BOOLEAN .TRUEmeanstheCPU
Arg4
The PAL Compatibility value for the CPU being updated.
Arg5
The 16-bit Platform ID of the CPU being updated.
Arg6
Arg7
Arg8
ThisfunctionupdatestheCPUwithaGlobalIDspecifiedby Arg2,theenableflagspecifiedby Arg3,andthePALCom-
patibilityvaluespecifiedby Arg4inthedatabaseofCPUsintheplatform. IftheCPUspecifiedby Arg2isnotpresent
in the database, then EFI_SAL_NO_INFORMATION is returned. Otherwise, the CPU specified by Arg2is updates
with the enable flag specified by Arg3and the PAL Compatibility value specified by Arg4, andEFI_SAL_SUCCESS
EFI_SAL_SUCCESS The CPU database was updated.
IV-11.4.58 ExtendedSalGetCpuDataById
Summary
Returns the information on a CPU specified by a Global ID.
Prototype
EFIAPI
ExtendedSalGetCpuDataById (
IV-11.4. Extended SAL Stall Services Class IV-211UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalGetCpuDataByIdFunctionId .
Arg2
The 64-bit Global ID of the CPU to lookup.
Arg3
This parameter is interpreted as a BOOLEAN value. IfTRUE, then the index in the set of enabled CPUs in the
database is returned. If FALSE, then the index in the set of all CPUs in the database is returned.
Arg4
Arg5
Arg6
Arg7
Arg8
This function looks up the CPU specified by Arg2in the CPU database and returns the enable status and PAL Com-
patibility value. If the CPU specified by Arg2is not present in the database, then EFI_SAL_NO_INFORMATION is
returned. Otherwise, the enable status is returned in SAL_RETURN_REGS .r9 , the PAL Compatibility value is re-
turned in SAL_RETURN_REGS .r10, andEFI_SAL_SUCCESS is returned. If Arg3isTRUE, then the index of the
CPU specified by Arg2in the set of enabled CPUs is returned in SAL_RETURN_REGS .r11.IfArg3isFALSE, then
the index of the CPU specified by Arg2in the set of all CPUs is returned in SAL_RETURN_REGS .r11.
EFI_SAL_SUCCESS The information on the specified CPU was returned
EFI_SAL_NO_INFORMATION The specified CPU is not in the database
IV-11.4. Extended SAL Stall Services Class IV-212UEFI Platform Initialization Specification, Release 1.8
IV-11.4.59 ExtendedSalGetCpuDataByIndex
Summary
Returns information on a CPU specified by an index.
Prototype
EFIAPI
ExtendedSalGetCpuDataByIndex (
);
Must beEsalGetCpuDataByIndexFunctionId .
Arg2
The index of the CPU to lookup.
Arg3
This parameter is interpreted as a BOOLEAN value. IfTRUE, then the index in Arg2is the index in the set of
enabled CPUs. If FALSE, then the index in Arg2is the index in the set of all CPUs.
Arg4
Arg5
Arg6
Arg7
Arg8

Summary
Prototype
EFIAPI
);
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
IV-11.4. Extended SAL Stall Services Class IV-213UEFI Platform Initialization Specification, Release 1.8
returned. Otherwise,theenablestatusisreturnedin SAL_RETURN_REGS .r9,thePALCompatibilityvalueisreturned
inSAL_RETURN_REGS .r10,theGlobalIDisreturnedin SAL_RETURN_REGS .r11,andEFI_SAL_SUCCESS is
returned. If Arg3isTRUE, thenArg2is the index in the set of enabled CPUs. If Arg3isFALSE, thenArg2is the
index in the set of all CPUs.
IV-11.4.60 ExtendedSalWhoiAmI
Summary
Returns the Global ID for the calling CPU.
Prototype
EFIAPI
ExtendedSalWhoAmI (
);
Must beEsalWhoAmIFunctionId .
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
IV-11.4. Extended SAL Stall Services Class IV-214UEFI Platform Initialization Specification, Release 1.8
Arg8
This function looks up the Global ID of the calling CPU. If the calling CPU is not present in the database, then
EFI_SAL_NO_INFORMATION is returned. Otherwise, the Global ID is returned in SAL_RETURN_REGS .r9, the
PAL Compatibility value is returned in SAL_RETURN_REGS .r10, andEFI_SAL_SUCCESS is returned. If Arg2is
TRUE, then the index of the calling CPU in the set of enabled CPUs is returned in SAL_RETURN_REGS .r11. If
Arg3isFALSE, then the index of the calling CPU in the set of all CPUs is returned in SAL_RETURN_REGS .r11.
EFI_SAL_SUCCESS The Global ID for the calling CPU was returned.
EFI_SAL_NO_INFORMATION The calling CPU is not in the database.
IV-11.4.61 ExtendedSalNumProcessors
Summary
ReturnsthenumberofcurrentlyenabledCPUs,thetotalnumberofCPUs,andthemaximumnumberofCPUsthatthe
platform supports.
Prototype
EFIAPI
ExtendedSalNumProcessors (
);
Must beEsalNumProcessorsFunctionId .
Arg2
Arg3
IV-11.4. Extended SAL Stall Services Class IV-215UEFI Platform Initialization Specification, Release 1.8
Arg4
Arg5
Arg6
Arg7
Arg8
ThisfunctionreturnsthemaximumnumberofCPUsthattheplatformsupportsin SAL_RETURN_REGS .r9,thetotal
number of CPUs in SAL_RETURN_REGS .r10, and the number of enabled CPUs in SAL_RETURN_REGS .r11.
EFI_SAL_SUCCESS is always returned.
EFI_SAL_SUCCESS TheinformationonthenumberofCPUsintheplatformwasreturned
IV-11.4.62 ExtendedSalSetMinState
Summary
Sets the MINSTATE pointer for the CPU specified by a Global ID.
Prototype
EFIAPI
ExtendedSalSetMinState (
);
Must beEsalSetMinStateFunctionId .
IV-11.4. Extended SAL Stall Services Class IV-216UEFI Platform Initialization Specification, Release 1.8
Arg2
The 64-bit Global ID of the CPU to set the MINSTATE pointer.
Arg3
This parameter is interpreted as a pointer to the MINSTATE area for the CPU specified by Arg2.
Arg4
Arg5
Arg6
Arg7
Arg8
This function sets the MINSTATE pointer for the CPU specified by Arg2to the buffer specified by Arg3. If the
CPU specified by Arg2is not present in the database, then EFI_SAL_NO_INFORMATION is returned. Otherwise,
EFI_SAL_SUCCESS The MINSTATE pointer was set for the specified CPU
IV-11.4.63 ExtendedSalGetMinState
Summary
Retrieves the MINSTATE pointer for the CPU specified by a Global ID.
Prototype
EFIAPI
IV-11.4. Extended SAL Stall Services Class IV-217UEFI Platform Initialization Specification, Release 1.8
);
Arg2
The 64-bit Global ID of the CPU to get the MINSTATE pointer.
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function retrieves the MINSTATE pointer for the CPU specified by Arg2. If the CPU specified by Arg2is not
present in the database, then EFI_SAL_NO_INFORMATION is returned. Otherwise, the MINSTATE pointer for the
specified CPU is returned in SAL_RETURN_REGS .r9, andEFI_SAL_SUCCESS is returned.
EFI_SAL_SUCCESS The MINSTATE pointer for the specified CPU was retrieved
IV-11.4.64 ExtendedSalPhysicalIdInfo
Summary
Returns the Physical ID for the calling CPU.
Prototype
EFIAPI
ExtendedSalPhysicalIdInfo (
IV-11.4. Extended SAL Stall Services Class IV-218UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalPhysicalIdInfo .
Arg2
Arg3
Arg4
Arg5
Arg6
Arg7
Arg8
This function looks up the Physical ID of the calling CPU. If the calling CPU is not present in the database, then
EFI_SAL_NO_INFORMATION isreturned. Otherwise,thePhysicalIDisreturnedin SAL_RETURN_REGS .r9,and
EFI_SAL_SUCCESS The Physical ID for the calling CPU was returned.
IV-11.4. Extended SAL Stall Services Class IV-219UEFI Platform Initialization Specification, Release 1.8
IV-11.4.65 Extended SAL MCA Services Class
Summary
The Extended SAL MCA Services Class provides services to
GUID
#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO \
0x42b16cc72a591128
#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI \
0xbb2d683b9358f08a
#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID \
{0x2a591128,0x6cc7,0x42b1,\
{0x8a,0xf0,0x58,0x93,0x3b,0x68,0x2d,0xbb}}

Summary
GUID
McaGetStateInfoFunctionId,
McaRegisterCpuFunctionId,
} EFI_EXTENDED_SAL_MCA_SERVICES_FUNC_ID;
Table 11.18: Extended SAL MCA Services Class
ExtendedSalMcaGetStateInfo Obtain the buffer corresponding to the Machine Check Abort state
information
ExtendedSalMcaRegisterCpu Register the CPU instance for the Machine Check Abort handling
IV-11.4.66 ExtendedSalMcaGetStateInfo
Summary
Obtain the buffer corresponding to the Machine Check Abort state information.
Prototype
EFIAPI
ExtendedSalMcaGetStateInfo (
);
IV-11.4. Extended SAL Stall Services Class IV-220UEFI Platform Initialization Specification, Release 1.8
Must be EsalMcaGetStateInfoFunctionId.
Arg2
Arg3
Pointer to the state buffer for output.
Arg4
Pointer to the required buffer size for output
Arg5
Arg6
Arg7
Arg8
This function retrieves the MINSTATE pointer specified by Arg3for the CpuId specified by Arg2, and cal-
culates required size specified by Arg4. If the CPU specified by Arg2was not registered in system, then
EFI_SAL_NO_INFORMATION is returned. Otherwise, the CPU state buffer related information will be returned,
andEFI_SAL_SUCCESS is returned.
EFI_SAL_SUCCESS MINSTATE successfully got and size calculated.
EFI_SAL_NO_INFORMATION The CPU was not registered in system.
IV-11.4.67 ExtendedSalMcaRegisterCpu
Summary
Register the CPU instance for the Machine Check Abort handling.
Prototype
EFIAPI
ExtendedSalMcaRegisterCpu (
IV-11.4. Extended SAL Stall Services Class IV-221UEFI Platform Initialization Specification, Release 1.8
);
Must beEsalMcaRegisterCpuFunctionId .
Arg2
The 64-bit Global ID of the CPU to register its MCA state buffer.
Arg3
The pointer of the CPU’s state buffer.
Arg4
Reserved. Must be zero
Arg5
Arg6
Arg7
Arg8
This function registers MCA state buffer specified by Agr3for CPU specified by Arg2. If the CPU specified by Arg2
was not registered in system, then EFI_SAL_NO_INFORMATION is returned. Otherwise, the CPU state buffer is
registered for MCA handing, and EFI_SAL_SUCCESS is returned.
EFI_SAL_SUCCESS The CPU state buffer is registered for MCA handing successfully
EFI_SAL_NO_INFORMATION The CPU was not registered in system
IV-11.4. Extended SAL Stall Services Class IV-222CHAPTER
TWELVE
SMM SPI PROTOCOL STACK
IV-12.1 Design
ThedesignoftheSPIprotocolstackisalmostidenticalbetweenSMMandDXE.SeethesectiononSPIProtocolStack
in Volume 5 for more details. The differences are described in this section.
SMM SPI support is primarily used to support SPI flash devices. Since SMM does not support device paths, there is
no mechanism to identify a SPI controller and properly connect it to the corresponding bus in the board database. As
such,onlyasingleSPIhostcontrollerisallowedinSMM.TheSMMversionoftheSPIbusdriverconnectstothefirst
and only SPI host controller identified by gEfiSpiSmmHcProtocolGuid.
AseparateSMMspecificSPIconfigurationdatabaseisprovidedbytheboardlayer. TheSMMSPIbusdriverconnects
totheSMMversionoftheSPIconfigurationdatabaseidentifiedbygEfiSpiSmmConfigurationProtocolGuid. TheSMM
version of the SPI bus driver verifies that there is a single bus in the SMM version of the board database and connects
this to the SPI controller.
TheSPIprotocoldeclarationsareidenticalbetweenSMMandDXEbutSMMusesdifferentGUIDstoidentifytheSPI
protocols for SMM.
IV-12.2 SMM SPI Protocols
IV-12.2.1 EFI_LEGACY _SPI_SMM_FLASH_PROTOCOL GUID
// {Se3848d4-0db5-4fc0-9729-3f353d4f879f}
#define EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL \
{ 0x5e3848d4, 0x0db5, 0x4fc0, { 0x97, 0x29, 0x3f, 0x35, \
0x3d, 0x4f, 0x87, 0x9f }}
IV-12.2.2 EFI_SPI_SMM_NOR_FLASH_PROTOCOL GUID
// {aab18f19-fe14-4666-8604-87ff6d662c9a}
#define EFI_SPI_SMM_NOR_FLASH_PROTOCOL \
{ 0xaab18f19, 0xfe14, 0x4666, { 0x86, 0x04, 0x87, 0xff, \ 0x6d, 0x66, 0x2c, 0x9a }}
SSN Flash Driver GUID
UseapointertogEfiSpiSmmNorFlashDriverGuidintheEFI_SPI_PERIPHERALstructuretoconnectaSPINORflash
part to the SMM SPI flash driver.
IV-223UEFI Platform Initialization Specification, Release 1.8
IV-12.2.3 EFI- SPI- SMM- CONFIGURATION PROTOCOL GUID
// {995c6eca-171b-45fd-a3aa-fd4c9c9def59}
#define EFI_SPI_SMM_CONFIGURATION_PROTOCOL \
{ 0x995c6eca, 0x171b, 0x45fd, { 0xa3, 0xaa, 0xfd, 0x4c, \
0x9c, 0x9d, 0xef, 0x59 }}
IV-12.2.4 EFI- SPI- SMM HC- PROTOCOL GUID
// {e9f02217-2093-4470-8a54-5c2cffe73ecb}
#define EFI_SPI_SMM_HC_PROTOCOL \
{ 0xe9f02217, 0x2093, 0x4470, { 0x8a, 0x54, 0x5c, 0x2c, \ 0xff, 0xe7, 0x3e, 0xcb }}
IV-12.2.5 EFI LEGACY- SPI- SMM- CONTROLLER- PROTOCOL GUID
// {62331b78-d8d0-4c8c-8ccb-d27dfe32db9b}
#define EFI_LEGACY_SPI_SMM_CONTROLLER_GUID \
{ 0x62331b78, 0xd8d0, 0x4c8c, { 0x8c, 0xcb, 0xd2, 0x7d, \ 0xfe, 0x32, 0xdb, 0x9b }}
IV-12.2. SMM SPI Protocols IV-224CHAPTER
THIRTEEN
APPENDIX: 
MANAGEMENT  MODE BACKWARD COMP ATIBILITY  TYPES
In versions of the PI specification up to and including version 1.4, this volume described System Management Mode
(SMM), and many of the types were named with this acronym as a part of their name. With later versions of the PI
specification,thesetypesandconstantswererenamedtofollowtheManagementMode(MM)nomenclature,toabstract
theconcepts from thex86architecture System Management Mode.
In order to maintain continuity, this appendix details typedefs and #define statements that allow code developed with
theseearlier versionsof thespecification tocompileunchanged.
typedef EFI_MM_ENTRY_POINT EFI_SMM_ENTRY_POINT;
typedef EFI_MM_ENTRY_CONTEXT EFI_SMM_ENTRY_CONTEXT;
typedef EFI_MM_STARTUP_THIS_AP EFI_SMM_STARTUP_THIS_AP;
#define EFI_SMM_SYSTEM_TABLE2_REVISION EFI_MM_SYSTEM_TABLE_REVISION
#define SMM_SMST_SIGNATURE MM_MMST_SIGNATURE
#define SMM_SPECIFICATION_MAJOR_REVISION
MM_SPECIFICATION_MAJOR_REVISION
#define SMM_SPECIFICATION_MINOR_REVISION
MM_SPECIFICATION_MINOR_REVISION
typedef EFI_MM_INSTALL_CONFIGURATION_TABLE
EFI_SMM_INSTALL_CONFIGURATION_TABLE2;
typedef EFI_MM_CPU_IO_PROTOCOL EFI_SMM_CPU_IO2_PROTOCOL;
typedef EFI_MM_REGISTER_PROTOCOL_NOTIFY
EFI_SMM_REGISTER_PROTOCOL_NOTIFY;
typedef EFI_MM_INTERRUPT_MANAGE EFI_SMM_INTERRUPT_MANAGE;
typedef EFI_MM_INTERRUPT_REGISTER EFI_SMM_INTERRUPT_REGISTER;
typedef EFI_MM_INTERRUPT_UNREGISTER EFI_SMM_INTERRUPT_UNREGISTER;
typedef EFI_MM_NOTIFY_FN EFI_SMM_NOTIFY_FN;
typedef EFI_MM_HANDLER_ENTRY_POINT EFI_SMM_HANDLER_ENTRY_POINT2;
typedef EFI_MM_STATUS_CODE_PROTOCOL EFI_SMM_STATUS_CODE_PROTOCOL;
#define EFI_SMM_STATUS_CODE_PROTOCOL_GUID
EFI_MM_STATUS_CODE_PROTOCOL_GUID
typedef EFI_MM_REPORT_STATUS_CODE EFI_SMM_REPORT_STATUS_CODE;
typedef EFI_MM_CPU_PROTOCOL EFI_SMM_CPU_PROTOCOL;
#define EFI_SMM_CPU_PROTOCOL_GUID EFI_MM_CPU_PROTOCOL_GUID
typedef EFI_MM_READ_SAVE_STATE EFI_SMM_READ_SAVE_STATE;
#define EFI_SMM_SAVE_STATE_REGISTER_GDTBASE
EFI_MM_SAVE_STATE_REGISTER_GDTBASE
#define EFI_SMM_SAVE_STATE_REGISTER_IDTBASE
EFI_MM_SAVE_STATE_REGISTER_IDTBASE
#define EFI_SMM_SAVE_STATE_REGISTER_LDTBASE
EFI_MM_SAVE_STATE_REGISTER_LDTBASE
#define EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT
(continues on nextpage)
IV-225UEFI Platform Initialization Specification, Release 1.8
EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT
#define EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT
EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT
#define EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT
EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT
#define EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
EFI_MM_SAVE_STATE_REGISTER_LDTINFO
#define EFI_SMM_SAVE_STATE_REGISTER_ES EFI_MM_SAVE_STATE_REGISTER_ES
#define EFI_SMM_SAVE_STATE_REGISTER_CS EFI_MM_SAVE_STATE_REGISTER_CS
#define EFI_SMM_SAVE_STATE_REGISTER_SS EFI_MM_SAVE_STATE_REGISTER_SS
#define EFI_SMM_SAVE_STATE_REGISTER_DS EFI_MM_SAVE_STATE_REGISTER_DS
#define EFI_SMM_SAVE_STATE_REGISTER_FS EFI_MM_SAVE_STATE_REGISTER_FS
#define EFI_SMM_SAVE_STATE_REGISTER_GS EFI_MM_SAVE_STATE_REGISTER_GS
#define EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL

EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL
#define EFI_SMM_SAVE_STATE_REGISTER_TR_SEL
EFI_MM_SAVE_STATE_REGISTER_TR_SEL
#define EFI_SMM_SAVE_STATE_REGISTER_DR7 EFI_MM_SAVE_STATE_REGISTER_DR7
#define EFI_SMM_SAVE_STATE_REGISTER_DR6 EFI_MM_SAVE_STATE_REGISTER_DR6
#define EFI_SMM_SAVE_STATE_REGISTER_R8 EFI_MM_SAVE_STATE_REGISTER_R8
#define EFI_SMM_SAVE_STATE_REGISTER_R9 EFI_MM_SAVE_STATE_REGISTER_R9
#define EFI_SMM_SAVE_STATE_REGISTER_R10 EFI_MM_SAVE_STATE_REGISTER_R10
#define EFI_SMM_SAVE_STATE_REGISTER_R11 EFI_MM_SAVE_STATE_REGISTER_R11
#define EFI_SMM_SAVE_STATE_REGISTER_R12 EFI_MM_SAVE_STATE_REGISTER_R12
#define EFI_SMM_SAVE_STATE_REGISTER_R13 EFI_MM_SAVE_STATE_REGISTER_R13
#define EFI_SMM_SAVE_STATE_REGISTER_R14 EFI_MM_SAVE_STATE_REGISTER_R14
#define EFI_SMM_SAVE_STATE_REGISTER_R15 EFI_MM_SAVE_STATE_REGISTER_R15
#define EFI_SMM_SAVE_STATE_REGISTER_RAX EFI_MM_SAVE_STATE_REGISTER_RAX
#define EFI_SMM_SAVE_STATE_REGISTER_RBX EFI_MM_SAVE_STATE_REGISTER_RBX
#define EFI_SMM_SAVE_STATE_REGISTER_RCX EFI_MM_SAVE_STATE_REGISTER_RCX
#define EFI_SMM_SAVE_STATE_REGISTER_RDX EFI_MM_SAVE_STATE_REGISTER_RDX
#define EFI_SMM_SAVE_STATE_REGISTER_RSP EFI_MM_SAVE_STATE_REGISTER_RSP
#define EFI_SMM_SAVE_STATE_REGISTER_RBP EFI_MM_SAVE_STATE_REGISTER_RBP
#define EFI_SMM_SAVE_STATE_REGISTER_RSI EFI_MM_SAVE_STATE_REGISTER_RSI
#define EFI_SMM_SAVE_STATE_REGISTER_RDI EFI_MM_SAVE_STATE_REGISTER_RDI
#define EFI_SMM_SAVE_STATE_REGISTER_RIP EFI_MM_SAVE_STATE_REGISTER_RIP
#define EFI_SMM_SAVE_STATE_REGISTER_RFLAGS
EFI_MM_SAVE_STATE_REGISTER_RFLAGS
#define EFI_SMM_SAVE_STATE_REGISTER_CR0 EFI_MM_SAVE_STATE_REGISTER_CR0
#define EFI_SMM_SAVE_STATE_REGISTER_CR3 EFI_MM_SAVE_STATE_REGISTER_CR3
#define EFI_SMM_SAVE_STATE_REGISTER_CR4 EFI_MM_SAVE_STATE_REGISTER_CR4
#define EFI_SMM_SAVE_STATE_REGISTER_FCW EFI_MM_SAVE_STATE_REGISTER_FCW
#define EFI_SMM_SAVE_STATE_REGISTER_FSW EFI_MM_SAVE_STATE_REGISTER_FSW
#define EFI_SMM_SAVE_STATE_REGISTER_FTW EFI_MM_SAVE_STATE_REGISTER_FTW
#define EFI_SMM_SAVE_STATE_REGISTER_OPCODE
EFI_MM_SAVE_STATE_REGISTER_OPCODE
#define EFI_SMM_SAVE_STATE_REGISTER_FP_EIP
EFI_MM_SAVE_STATE_REGISTER_FP_EIP
#define EFI_SMM_SAVE_STATE_REGISTER_FP_CS
EFI_MM_SAVE_STATE_REGISTER_FP_CS
#define EFI_SMM_SAVE_STATE_REGISTER_DATAOFFSET
EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET
IV-226UEFI Platform Initialization Specification, Release 1.8
#define EFI_SMM_SAVE_STATE_REGISTER_FP_DS
EFI_MM_SAVE_STATE_REGISTER_FP_DS
#define EFI_SMM_SAVE_STATE_REGISTER_MM0 EFI_MM_SAVE_STATE_REGISTER_MM0
#define EFI_SMM_SAVE_STATE_REGISTER_MM1 EFI_MM_SAVE_STATE_REGISTER_MM1
#define EFI_SMM_SAVE_STATE_REGISTER_MM2 EFI_MM_SAVE_STATE_REGISTER_MM2
#define EFI_SMM_SAVE_STATE_REGISTER_MM3 EFI_MM_SAVE_STATE_REGISTER_MM3
#define EFI_SMM_SAVE_STATE_REGISTER_MM4 EFI_MM_SAVE_STATE_REGISTER_MM4
#define EFI_SMM_SAVE_STATE_REGISTER_MM5 EFI_MM_SAVE_STATE_REGISTER_MM5
#define EFI_SMM_SAVE_STATE_REGISTER_MM6 EFI_MM_SAVE_STATE_REGISTER_MM6
#define EFI_SMM_SAVE_STATE_REGISTER_MM7 EFI_MM_SAVE_STATE_REGISTER_MM7
#define EFI_SMM_SAVE_STATE_REGISTER_XMM0
EFI_MM_SAVE_STATE_REGISTER_XMM0
#define EFI_SMM_SAVE_STATE_REGISTER_XMM1
EFI_MM_SAVE_STATE_REGISTER_XMM1
#define EFI_SMM_SAVE_STATE_REGISTER_XMM2
EFI_MM_SAVE_STATE_REGISTER_XMM2
#define EFI_SMM_SAVE_STATE_REGISTER_XMM3
EFI_MM_SAVE_STATE_REGISTER_XMM3
#define EFI_SMM_SAVE_STATE_REGISTER_XMM4
EFI_MM_SAVE_STATE_REGISTER_XMM4
#define EFI_SMM_SAVE_STATE_REGISTER_XMM5
EFI_MM_SAVE_STATE_REGISTER_XMM5
#define EFI_SMM_SAVE_STATE_REGISTER_XMM6
EFI_MM_SAVE_STATE_REGISTER_XMM6
#define EFI_SMM_SAVE_STATE_REGISTER_XMM7
EFI_MM_SAVE_STATE_REGISTER_XMM7
#define EFI_SMM_SAVE_STATE_REGISTER_XMM8
EFI_MM_SAVE_STATE_REGISTER_XMM8
#define EFI_SMM_SAVE_STATE_REGISTER_XMM9
EFI_MM_SAVE_STATE_REGISTER_XMM9
#define EFI_SMM_SAVE_STATE_REGISTER_XMM10
EFI_MM_SAVE_STATE_REGISTER_XMM10
#define EFI_SMM_SAVE_STATE_REGISTER_XMM11
EFI_MM_SAVE_STATE_REGISTER_XMM11
#define EFI_SMM_SAVE_STATE_REGISTER_XMM12
EFI_MM_SAVE_STATE_REGISTER_XMM12
#define EFI_SMM_SAVE_STATE_REGISTER_XMM13
EFI_MM_SAVE_STATE_REGISTER_XMM13
#define EFI_SMM_SAVE_STATE_REGISTER_XMM14
EFI_MM_SAVE_STATE_REGISTER_XMM14
#define EFI_SMM_SAVE_STATE_REGISTER_XMM15
EFI_MM_SAVE_STATE_REGISTER_XMM15
#define EFI_SMM_SAVE_STATE_REGISTER_IO EFI_MM_SAVE_STATE_REGISTER_IO
#define EFI_SMM_SAVE_STATE_REGISTER_LMA EFI_MM_SAVE_STATE_REGISTER_LMA
#define EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID
#define EFI_SMM_SAVE_STATE_REGISTER EFI_MM_SAVE_STATE_REGISTER
#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT
#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT
#define EFI_SMM_WRITE_SAVE_STATE EFI_MM_WRITE_SAVE_STATE
IV-227UEFI Platform Initialization Specification, Release 1.8
#define EFI_SMM_SAVE_STATE_IO_INFO EFI_MM_SAVE_STATE_IO_INFO
#define EFI_SMM_CPU_IO2_PROTOCOL_GUID EFI_MM_CPU_IO_PROTOCOL_GUID
typedef EFI_MM_IO_ACCESS EFI_SMM_IO_ACCESS2;
typedef EFI_MM_CPU_IO EFI_SMM_CPU_IO2;
typedef EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL
EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL;
#define EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID
EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID
typedef EFI_MM_READY_TO_LOCK_SMM_PROTOCOL
EFI_SMM_READY_TO_LOCK_SMM_PROTOCOL;
#define EFI_SMM_READY_TO_LOCK_PROTOCOL_GUID
EFI_MM_READY_TO_LOCK_PROTOCOL_GUID
typedef EFI_MM_END_OF_DXE_PROTOCOL EFI_SMM_END_OF_DXE_PROTOCOL;
#define EFI_SMM_END_OF_DXE_PROTOCOL_GUID
EFI_MM_END_OF_DXE_PROTOCOL_GUID
#define EFI_SMM_BASE2_PROTOCOL_GUID EFI_MM_BASE_PROTOCOL_GUID
typedef EFI_MM_GET_MMST_LOCATION EFI_SMM_GET_SMST_LOCATION2;
typedef EFI_MM_ACCESS_PROTOCOL EFI_SMM_ACCESS2_PROTOCOL;
#define EFI_SMM_ACCESS2_PROTOCOL_GUID EFI_MM_ACCESS_PROTOCOL_GUID
typedef EFI_MM_OPEN EFI_SMM_OPEN2;
typedef EFI_MM_CLOSE EFI_SMM_CLOSE2;
typedef EFI_MM_LOCK EFI_SMM_LOCK2;
typedef EFI_MM_CONTROL_PROTOCOL EFI_SMM_CONTROL2_PROTOCOL;
#define EFI_SMM_CONTROL2_PROTOCOL_GUID EFI_MM_CONTROL_PROTOCOL_GUID
typedef EFI_MM_PERIOD EFI_SMM_PERIOD;
typedef EFI_MM_ACTIVATE EFI_SMM_ACTIVATE2;
typedef EFI_MM_DEACTIVATE EFI_SMM_DEACTIVATE2;
#define EFI_SMM_CONFIGURATION_PROTOCOL_GUID
EFI_MM_CONFIGURATION_PROTOCOL_GUID
typedef EFI_MM_REGISTER_SMM_ENTRY EFI_SMM_REGISTER_SMM_ENTRY;
typedef EFI_MM_COMMUNICATION_PROTOCOL EFI_SMM_COMMUNICATION_PROTOCOL;
#define EFI_SMM_COMMUNICATION_PROTOCOL_GUID
EFI_MM_COMMUNICATION_PROTOCOL_GUID
typedef EFI_MM_COMMUNICATE EFI_SMM_COMMUNICATE2;
typedef EFI_MM_COMMUNICATE_HEADER EFI_SMM_COMMUNICATE_HEADER;
typedef EFI_MM_SW_DISPATCH_PROTOCOL EFI_SMM_SW_DISPATCH2_PROTOCOL;
#define EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID
EFI_MM_SW_DISPATCH_PROTOCOL_GUID
typedef EFI_MM_SW_REGISTER EFI_SMM_SW_REGISTER2;
typedef EFI_MM_SW_UNREGISTER EFI_SMM_SW_UNREGISTER2;
typedef EFI_MM_SX_DISPATCH_PROTOCOL EFI_SMM_SX_DISPATCH2_PROTOCOL;
typedef EFI_MM_SX_DISPATCH_PROTOCOL_GUID
EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID;
typedef EFI_MM_SX_REGISTER EFI_SMM_SX_REGISTER2;
typedef EFI_MM_SX_REGISTER_CONTEXT EFI_SMM_SX_REGISTER_CONTEXT;
typedef EFI_MM_SX_UNREGISTER EFI_SMM_SX_UNREGISTER2;
typedef EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL
EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL;
#define EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL_GUID
EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID
typedef EFI_MM_PERIODIC_TIMER_REGISTER
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EFI_SMM_PERIODIC_TIMER_REGISTER2;
typedef EFI_MM_PERIODIC_TIMER_CONTEXT EFI_SMM_PERIODIC_TIMER_CONTEXT;
typedef EFI_MM_PERIODIC_TIMER_UNREGISTER
EFI_SMM_PERIODIC_TIMER_UNREGISTER2;
typedef EFI_MM_PERIODIC_TIMER_INTERVAL
EFI_SMM_PERIODIC_TIMER_INTERVAL2;
typedef EFI_MM_USB_DISPATCH_PROTOCOL EFI_SMM_USB_DISPATCH2_PROTOCOL;
#define EFI_SMM_USB_DISPATCH2_PROTOCOL_GUID
EFI_MM_USB_DISPATCH_PROTOCOL_GUID
typedef EFI_MM_USB_REGISTER EFI_SMM_USB_REGISTER2;
typedef EFI_MM_USB_REGISTER_CONTEXT EFI_SMM_USB_REGISTER_CONTEXT;
typedef EFI_USB_MMI_TYPE EFI_USB_SMI_TYPE;
typedef EFI_MM_GPI_DISPATCH_PROTOCOL EFI_SMM_GPI_DISPATCH2_PROTOCOL;
#define EFI_SMM_GPI_DISPATCH2_PROTOCOL_GUID
EFI_MM_GPI_DISPATCH_PROTOCOL_GUID
typedef EFI_MM_GPI_REGISTER EFI_SMM_GPI_REGISTER2;
typedef EFI_MM_GPI_REGISTER_CONTEXT EFI_SMM_GPI_REGISTER_CONTEXT;
typedef EFI_MM_GPI_UNREGISTER EFI_SMM_GPI_UNREGISTER2;
typedef EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL
EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL;
#define EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL_GUID
EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL_GUID
typedef EFI_MM_STANDBY_BUTTON_REGISTER
EFI_SMM_STANDBY_BUTTON_REGISTER2;
typedef EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT
EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT;
typedef EFI_MM_STANDBY_BUTTON_UNREGISTER
EFI_SMM_STANDBY_BUTTON_UNREGISTER2;
typedef EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL
EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL;
#define EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL_GUID
EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID

typedef EFI_MM_POWER_BUTTON_REGISTER EFI_SMM_POWER_BUTTON_REGISTER2;
typedef EFI_MM_POWER_BUTTON_REGISTER_CONTEXT
EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT;
typedef EFI_MM_POWER_BUTTON_UNREGISTER
EFI_SMM_POWER_BUTTON_UNREGISTER2;
typedef EFI_MM_IO_TRAP_DISPATCH_PROTOCOL
EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL;
#define EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL_GUID
EFI_MM_IO_TRAP_DISPATCH_PROTOCOL_GUID
typedef EFI_MM_IO_TRAP_DISPATCH_REGISTER
EFI_SMM_IO_TRAP_DISPATCH2_REGISTER;
typedef EFI_MM_IO_TRAP_DISPATCH_TYPE EFI_SMM_IO_TRAP_DISPATCH_TYPE;
typedef EFI_MM_IO_TRAP_REGISTER_CONTEXT
EFI_SMM_IO_TRAP_REGISTER_CONTEXT;
typedef EFI_SMM_IO_TRAP_CONTEXT EFI_MM_IO_TRAP_CONTEXT;
typedef EFI_MM_IO_TRAP_DISPATCH_UNREGISTER
EFI_SMM_IO_TRAP_DISPATCH2_UNREGISTER;
#define EFI_FV_FILETYPE_SMM EFI_FV_FILETYPE_MM
IV-229UEFI Platform Initialization Specification, Release 1.8
#define EFI_FV_FILETYPE_COMBINED_SMM_DXE EFI_FV_FILETYPE_MM_DXE
#define EFI_FV_FILETYPE_SMM_CORE EFI_FV_FILETYPE_MM_CORE
#define EFI_SECTION_SMM_DEPEX EFI_SECTION_MM_DEPEX
typedef EFI_MM_DEPEX_SECTION EFI_SMM_DEPEX_SECTION2;
typedef EFI_MM_DEPEX_SECTION EFI_SMM_DEPEX_SECTION;
IV-13.1 EFI_SMM_BASE2_PROTOCOL
This structure is deprecated. It is identical in content to EFI_MM_BASE_PROTOCOL .
typedef struct _EFI_SMM_BASE2_PROTOCOL {
EFI_SMM_INSIDE_OUT2 InSmm ;
EFI_SMM_GET_SMST_LOCATION2 GetSmstLocation ;
} EFI_SMM_BASE2_PROTOCOL;
EFI_SMM_RESERVED_SMRAM_REGION
This structure is deprecated. It is identical in content to EFI_MM_RESERVED_MMRAM_REGION .
typedef struct _EFI_SMM_RESERVED_SMRAM_REGION {
EFI_PHYSICAL_ADDRESS SmramReservedStart ;
UINT64 SmramReservedSize ;
} EFI_SMM_RESERVED_SMRAM_REGION;
IV-13.1.1 EFI_SMM_CONFIGURATION_PROTOCOL
This structure is deprecated. It is identical in content to EFI_MM_CONFIGURATION_PROTOCOL .
typedef struct _EFI_SMM_CONFIGURATION_PROTOCOL {
EFI_SMM_RESERVED_SMRAM_REGION *SmramReservedRegions ;
EFI_SMM_REGISTER_SMM_ENTRY RegisterSmmEntry;
} EFI_SMM_CONFIGURATION_PROTOCOL;
IV-13.1.2 EFI_SMM_CAPABILITIES2
This type is deprecated. It is identical in content to EFI_MM_CAPABILITIES .
typedef
(EFIAPI *EFI_SMM_CAPABILITIES2) (
IN CONST EFI_SMM_ACCESS2_PROTOCOL *This ,
IN OUT UINTN *SmramMapSize ,
IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
);
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IV-13.1.3 EFI_SMM_INSIDE_OUT2
This type is deprecated. It is identical in content to EFI_MM_INSIDE_OUT .
typedef
(EFIAPI *EFI_SMM_INSIDE_OUT2) (
IN CONST EFI_SMM_BASE2_PROTOCOL *This ,
OUT BOOLEAN *InSmram
);
IV-13.1.4 EFI_SMM_SW_CONTEXT
This structure is deprecated. It is identical in content to EFI_MM_SW_CONTEXT ;
UINTN SwSmiCpuIndex ;
UINT8 CommandPort ;
UINT8 DataPort ;
} EFI_SMM_SW_CONTEXT;
IV-13.1.5 EFI_SMM_SW_REGISTER_CONTEXT
This structure is deprecated. It is identical in content to EFI_MM_SW_REGISTER_CONTEXT .
UINTN SwSmiInputValue ;
} EFI_SMM_SW_REGISTER_CONTEXT;
IV-13.1.6 EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT
This structure is deprecated. It is identical in content to EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT .
UINT64 Period ;
UINT64 SmiTickInterval ;
} EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT;
IV-13.1.7 EFI_SMM_SAVE_STATE_IO_WIDTH
This type is deprecated. It is identical in content to EFI_MM_SAVE_STATE_IO_WIDTH .
EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 = 0,
EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 = 1,
EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 = 2,
EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64 = 3
} EFI_SMM_SAVE_STATE_IO_WIDTH
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IV-13.1.8 EFI_SMM_SAVE_STATE_IO_TYPE
This type is deprecated. It is identical in content to EFI_MM_SAVE_STATE_IO_TYPE .
EFI_SMM_SAVE_STATE_IO_TYPE_INPUT = 1,
EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT = 2,
EFI_SMM_SAVE_STATE_IO_TYPE_STRING = 4,
EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8
} EFI_SMM_SAVE_STATE_IO_TYPE
IV-13.1.9 EFI_SMM_IO_WIDTH
This type is deprecated. It is identical in content to EFI_MM_IO_WIDTH .
SMM_IO_UINT8 = 0,
SMM_IO_UINT16 = 1,
SMM_IO_UINT32 = 2,
SMM_IO_UINT64 = 3
} EFI_SMM_IO_WIDTH;
EFI_SMM_SYSTEM_TABLE2
ThisstructuremustmatchthemembersofEFI_MM_SYSTEM_TABLEuptoandincluding MmiHandlerUnregister .
typedef struct _EFI_SMM_SYSTEM_TABLE2 { EFI_TABLE_HEADER Hdr;
CHAR16 *SmmFirmwareVendor;
UINT32 SmmFirmwareRevision;
EFI_SMM_INSTALL_CONFIGURATION_TABLE2 SmmInstallConfigurationTable;
EFI_SMM_CPU_IO_PROTOCOL SmmIo;
//
//
EFI_ALLOCATE_POOL SmmAllocatePool;
EFI_FREE_POOL SmmFreePool;
EFI_ALLOCATE_PAGES SmmAllocatePages;
EFI_FREE_PAGES SmmFreePages;
//
//
EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp;
//
//
UINTN NumberOfCpus;
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//
//
EFI_CONFIGURATION_TABLE *SmmConfigurationTable;
//
//
EFI_INSTALL_PROTOCOL_INTERFACE SmmInstallProtocolInterface;
EFI_UNINSTALL_PROTOCOL_INTERFACE SmmUninstallProtocolInterface;
EFI_HANDLE_PROTOCOL SmmHandleProtocol;
EFI_SMM_REGISTER_PROTOCOL_NOTIFY SmmRegisterProtocolNotify;
EFI_LOCATE_HANDLE SmmLocateHandle;
EFI_LOCATE_PROTOCOL SmmLocateProtocol;
//
//
EFI_SMM_INTERRUPT_MANAGE SmiManage;
EFI_SMM_INTERRUPT_REGISTER SmiHandlerRegister;
EFI_SMM_INTERRUPT_UNREGISTER SmiHandlerUnRegister;
} EFI_SMM_SYSTEM_TABLE2;
IV-13.1. EFI_SMM_BASE2_PROTOCOL IV-233Part V
StandardsUEFI Platform Initialization Specification, Release 1.8
List of Figures - Volume V
•EFI CPU I/O2 Protocol
•Simple 12C Bus
•Multiple I2C Bus Frequencies
•Limited Address Space
•Controller Handle After I2C Stack Initialization
•I2C Protocol Stack after EFI_I2C_ENUMERATE_PROTOCOL
•State of the Required I2C Controller Handle
•v5 i2c protocol stack
•PI Architecture S3 Resume
•PEI Phase in S3 Resume Boot Path
•Configuration Save for PEI Phase
•SPI Bus
•SPI Layers
•Host Bus Controllers
•Super I/O and ISA Host Controller Interactions
V-iUEFI Platform Initialization Specification, Release 1.8
•Drivers Involved in Configuring IDE Devices
•Field descriptiond forEFI_IDE_CONTROLLER_ENUM_PHASE
•EFI_ATAPI_IDENTIFY_DATA Definition .
•Functions in Legacy Region Protocol
•Standard PCI Devices - Header Type 0
•PCI-to-PCI Bridge - Header Type 1
•ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage
•ACPI 2.0 & 3.0 End Tag Usage
•I/O Resource Flag (Resource Type = 1) Usage
•Memory Resource Flag (Resource Type = 0) Usage
•Enumeration Descriptions
•EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTESfield descriptions
•ACPI 2.0 & 3.0 Resource Descriptor FieldValues for StartBusEnumeration()
•ACPI 2.0 & 3.0 Resource Descriptor FieldValues for SetBusNumbers()
•ACPI 2.0& 3.0 Resource Descriptor FieldValues for SubmitResources()
•ACPI 2.0 & 3.0 GetProposedResources()Resource Descriptor Field Values
•EFI_RESOURCE_ALLOCATION_STATUS fielddescriptions
•EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASEfield descriptions
•Description of possible states for EFI_HPC_STATE
•EFI_HPC_PADDING_ATTRIBUTES field descriptions
•Producing the PCI Host Bridge Resource Allocation Protocol
•Desktop System with 1 PCI Root Bridge
•Server System with 4 PCI Root Bridges
•Server System with 2 PCI Segments
•Server System with 2 PCI Host Buses
V-iiCHAPTER
ONE
V-1.1 Overview
ThischapterdefinesthecorecodeandservicesthatarerequiredforanimplementationoftheSystemManagementBus
(SMBus)HostControllerProtocolandSystemManagementBus(SMBus)PEIM-to-PEIMInterface(PPI).TheSMBus
HostControllerProtocolisusedbycode,typicallyearlychipsetdrivers,andSMBusbusdriversthatarerunninginthe
UEFIBootServicesenvironmenttoperformdatatransactionsovertheSMBus. Thisspecificationdoesthefollowing:
•Describes the basic components of the SMBus Host Controller Protocol
•Provides code definitions for the SMBus Host Controller
Protocol and the SMBus-related type definitions that are architecturally required. The SMBus PPI is used by other
Pre-EFI Initialization Modules (PEIMs) to control an SMBus host controller. This specification does the following:
•Describes the basic components of the PEI SMBus PPI
•Provides code definitions for the PEI SMBus PPI and
SMBus-related type definitions that are architecturally required.
V-1.2 Terms Used in this Document
16-bit PC Card
Legacy cards that follow the PC Card Standard and operate in 16-bit mode.
CardBay PC Card
32-bit PC Cards that follow the high-performance serial PC Card Standard. After initialization, these devices
appear as standard PCI devices.
CardBus bridge

A hardware controller that produces a CardBus bus. A CardBus bus can accept a CardBus PC Card as well as
legacy 16-bit PC Cards. CardBus PC Cards appear just like PCI devices to the configuration software.
CardBus PC Card
32-bit PC Cards that follow the PC Card Standard.
HB
Host bridge. See PCI host bridge.
HPB
Hot Plug Bus.
HPC
Hot Plug Controller. A generic term that refers to both a PHPC and a CardBus bridge.
V-1UEFI Platform Initialization Specification, Release 1.8
HPRT
Hot Plug Resource Table.
Incompatible PCI device
A PCI device that does not fully comply with the PCI Specification. Typically, this kind of device has a special
requirement for Base Address Register (BAR) allocation. Some devices may want a special resource length or
alignment, while others may want fixed I/O or memory locations.
JEITA
Japan Electronics and Information Technology Association.
legacy PHPC
PCI devices that can be identified by their class code but were defined prior to the PCI Standard Hot-Plug
Controller and Subsystem Specification , revision 1.0. These devices have a base class of 0x6, subclass of 0x4,
and programming interface of 0.
MWI
Memory Write and Invalidate. See the PCI Local Bus Specification, revision 2.3, for more information.
PC Card
Integrated circuit cards that follow the PC Card Standard. “PC Card” is a generic term that is used to refer to
16-bit PC Cards, 32-bit CardBus PC Cards, and high-performance CardBay PC Cards.
PC Card Standard
ReferstothesetofspecificationsthatareproducedjointlybythePCMCIAandJEITA.Thisstandardwasdefined
to promote interchangeability among mobile computers.
PCI bus
A generic term used to describe any PCI-like buses, including conventional PCI, PCI-X*, and PCI Express*.
Fromasoftwarestandpoint,aPCIbusiscollectionofupto32physicalPCIdevicesthatsharethesamephysical
PCI bus.
PCI bus driver
Software that creates a handle for every PCI controller in the system and installs both the PCI I/O Protocol and
the Device Path Protocol onto that handle. It may optionally perform PCI enumeration if resources have not
already been allocated to all the PCI controllers. It also loads and starts any EFI drivers that are found in any
PCI option ROMs that were discovered during PCI enumeration.
PCI configuration space
TheconfigurationchannelthatisdefinedbyPCItoconfigurePCIdevicesintotheresourcedomainofthesystem.
Each PCI device must produce a standard set of registers in the form of a PCI configuration header and can
optionallyproducedevice-specificregisters. TheregistersareaddressedviaType0orType1PCIconfiguration
cycles as described by the PCI Specification. The PCI configuration space can be shared across multiple PCI
buses. On Intel ®architecture-based systems, the PCI configuration space is accessed via I/O ports 0xCF8 and
0xCFC. The PCI Express configuration space is accessed via a memory-mapped aperture.
PCI controller
A hardware components that is discovered by a PCI bus driver and is managed by a PCI device driver. This
document uses the terms “PCI function” and “PCI controller” equivalently.
PCI device
A collection of up to 8 PCI functions that share the same PCI configuration space. A PCI device is physically
connected to a PCI bus.
PCI enumeration
The process of assigning resources to all the PCI controllers on a given PCI host bridge. This process includes
•Assigning PCI bus numbers and PCI interrupts
•Allocating PCI I/O resources, PCI memory resources, and PCI
V-1.2. Terms Used in this Document V-2UEFI Platform Initialization Specification, Release 1.8
prefetchable memory resources
•Setting miscellaneous PCI DMA values
Typically, PCI enumeration is to be performed only once during the boot process.
PCI function
A controller that provides some type of I/O services. It consumes some combination of PCI I/O, PCI memory,
and PCI prefetchable memory regions and the PCI configuration space. The PCI function is the basic unit of
configuration for PCI.
PCI host bridge
The software abstraction that produces one or more PCI root bridges. All the PCI buses that are produced by a
hostbuscontrollerarepartofthesamecoherencydomain. APCIhostbridgeisanabstractionandmaybemade
up of multiple hardware devices. Most systems can be modeled as having one PCI host bridge. This software
abstraction is necessary while dealing with PCI resource allocation because resources that are assigned to one
PCI root bridge depend on another and all the “related” PCI root bridges must be considered together during
resource allocation.
PCI root bridge
A PCI root bridge that produces a root PCI bus. It bridges a root PCI bus and a bus that is not a PCI bus
(e.g., processor local bus, InfiniBand* fabric). A PCI host bridge may have one or more root PCI bridges.
Configurations of a root PCI bridge within a host bridge can have dependencies upon other root PCI bridges
within the same host bridge.
PCI segment
A collection of up to 256 PCI buses that share the same PCI configuration space. A PCI segment is defined
in section 6.5.6 of the ACPI 2.0 Specification (also ACPI 3.0) as the _SEG object. If a system supports only a
single PCI segment, the PCI segment number is defined to be zero.The existence of PCI segments enables the
PEC
Packet Error Code. It is similar to a checksum data of the data coming across the SMBus wire.
PCI-to-CardBus bridges
A PCI device that produces a CardBus bus. The PCI-to-CardBus bridge has a PEI Pre-EFI Initialization.
PEIM
Pre-EFI Initialization Module. greater than 256 PCI buses.
PERR
Parity Error. type 2 PCI configuration header and has a class code of 0x070600.
PHPC
PCIHotPlug*Controller. AhardwarecomponentthatcontrolsthepowertooneormoreconventionalPCIslots
or PCI Express slots.
PPI
PEIM-to-PEIM Interface.
RB
Root bridge. See PCI root bridge.
resource padding
Also known as resource overallocation. System resources are said to be overallocated if more resources are
allocated to a PCI bus than are required. Resource padding allows a limited number of add-in cards to be hot
added to a PCI bus without disturbing allocation to the rest of the buses.
root HPC
Root Hot Plug Controller. An HPC that gets reset only when the entire system is reset. Such HPCs can depend
uponthesystemfirmwaretoinitializethembecausesystemfirmwareisguaranteedtorunafterasystemreset. An
V-1.2. Terms Used in this Document V-3UEFI Platform Initialization Specification, Release 1.8
HPC that is embedded in the PCI root bridge is considered a root HPC bridge. Some platform chipsets include
special-purposePCI-to-PCIbridges. TheyappearlikeaPCI-to-PCIbridgetotheconfigurationsoftware,buttheir
primarybusinterfaceisnotaPCIbus. SuchacomponentcanbeconsideredarootHPCifitisnotsubordinateto
an HPC. Legacy HPCs may be implemented as chipset devices that appear to be behind a special-purpose PCI-
to-PCI bridge, but these HPCs are not reset when the secondary bus reset bit in the parent PCI-to-PCI bridge is
set. Such HPCs are considered as root HPCs as well.
AnHPCthatisachildofaPCI-to-PCIbridgeisnotarootHPC.SuchanHPCcanberesetifthesecondarybus
reset bit in the PCI-to-PCI bridge is set by an operating system. Because the initialization code in the system
firmware may not be executed during this case, such an HPC must initialize itself using hardware mechanisms,
withoutanyfirmwareintervention. AnHPCthatisachildofanotherHPCisnotarootHPC.Seesection3.5.1.3
in the PCI Standard Hot-Plug Controller and Subsystem Specification, revision 1.0, for details regarding this
term.
root PCI bus
A PCI bus that is not a child of another PCI bus. For every root PCI bus, there is an object in the ACPI name
space with a Plug and Play (PNP) ID of “PNP0A03.” Typical desktop systems include only one root PCI bus.
SERR
System error.
SHPC
Standard (PCI) Hot Plug Controller. A PCI Hot Plug controller that conforms to the PCI Standard Hot-Plug
ControllerandSubsystemSpecification,revision1.0. ThisspecificationispublishedbythePCISpecialInterest
Group (PCI-SIG). An SHPC can either be embedded in a PCI root bridge or a PCI-to-PCI bridge.coherency
domain
The address resources of a system as seen by a processor. It consists of both system memory and I/O space.
SMBus
System Management Bus.
SMBus host controller
Provides a mechanism for the processor to initiate communications with SMBus slave devices. This controller
can be connected to a main I/O bus such as PCI.
SMBus master device
Any device that initiates SMBus transactions and drives the clock.
SMBus PPI
AsoftwareinterfacethatprovidesamethodtocontrolanSMBushostcontrollerandaccessthedataoftheSMBus
slave devices that are attached to it.
SMBus slave device
The target of an SMBus transaction, which is driven by some master.
UDID
Unique Device Identifier. A 128-bit value that a device uses during the Address Resolution Protocol (ARP)
process to uniquely identify itself.
V-1.2. Terms Used in this Document V-4UEFI Platform Initialization Specification, Release 1.8
V-1.3 Conventions Used in this Document

domain
SMBus
SMBus PPI
UDID
V-1.3.1 Data Structure Descriptions
V-1.3.2 Protocol Descriptions
GUID:The 128-bit Globally Unique Identifier (GUID) for the protocol interface.
ProtocolInterfaceStructure: A“C-style”datastructuredefinitioncontainingtheproceduresanddatafieldsproduced
by this protocol interface.
Parameters: A brief description of each field in the protocol interface structure.
Related Definitions: The type declarations and constants that are used in the protocol interface structure or any of its
V-1.3. Conventions Used in this Document V-5UEFI Platform Initialization Specification, Release 1.8
V-1.3.3 Procedure Descriptions
V-1.3.4 Pseudo-Code Conventions
V-1.3.5 Typographic Conventions
Plain text The normal text typeface is used for the vast majority of the descriptive text in a specification.
Plain text (blue) In the online help version of this specification, any plain text that is underlined and in blue indicates
an active link to the cross-reference. Click on the word to follow the hyperlink. Note that these links are not active in
the PDF of the specification.
BoldIntext,aBoldtypefaceidentifiesaprocessorregistername. Inotherinstances,a Boldtypefacecanbeusedasa
running head within a paragraph.
ItalicIntext,anItalictypefacecanbeusedasemphasistointroduceanewtermortoindicateamanualorspecification
name.
BOLD Monospace Computercode,examplecodesegments,andallprototypecodesegmentsusea BOLDMonospace
typefacewithadarkredcolor. Thesecodelistingsnormallyappearinoneormoreseparateparagraphs,thoughwords
or segments can also be embedded in a normal text paragraph.
Bold Monospace Intheonlinehelpversionofthisspecification,wordsina BoldMonospace typefacethatisunderlined
thePDFmayinsteadhavea Bold Monospace appearancethatisunderlinedbutindarkred. Again,theselinksarenot
V-1.3. Conventions Used in this Document V-6UEFI Platform Initialization Specification, Release 1.8
that must be supplied (i.e. arguments). Plain Monospace In code, words in a Plain Monospace typeface that is a dark
red color but is not bold or italicized indicate pseudo code or example code. These code segments typically occur in
one or more separate paragraphs.
V-1.4 Requirements

V-1.4. Requirements V-7CHAPTER
TWO
SMBUS HOST CONTROLLER DESIGN DISCUSSION
V-2.1 SMBus Host Controller Overview
These section describe the System Management Bus (SMBus) Host Controller Protocol. This protocol provides an
I/OabstractionforanSMBushostcontroller. AnSMBushostcontrollerisahardwarecomponentthatinterfacestoan
SMBus. ItmovesdatabetweensystemmemoryanddevicesontheSMBusbyprocessingdatastructuresandgenerating
transactions on the SMBus. The following use this protocol:
•An SMBus bus driver to perform all data transactions over the SMBus
•Early chipset drivers that need to manage devices that are required early in the Driver Execution Environment
(DXE) phase, before the Boot Device Selection (BDS) phase
This protocol should be used only by drivers that require direct access to the SMBus.
Considerable discussion has been done to understand the usage model of the UEFI Driver Model in the SMBus. Al-
though, the UEFI Driver Model concepts can be applied to SMBus, only the SMBus Host Controller Protocol was
created for now for the following reasons:
•TheUEFIDriverModelisdesignedprimarilyforbootdevices. Bootdevicesareunlikelytobeconnectedtothe
SMBus because of SMBus-intrinsic capability. They are slow and not enumerable.
•ThecurrentusagemodelofSMBusistoenableandconfiguredevicesearlyduringthebootphase,beforeBDS.
A DXE driver that publishes this protocol will either support Execute, ArpDevice, GetArpMap, and Notify; alterna-
tively, a driver will support only Execute and return “not supported” for the latter 3 services.
Ifsomeoftheseassumptionsbecomeobsoleteandrequirebeingrevisitedinthefuture,thisspecificationisextensible
to convert to the UEFI Driver Model.
V-2.2 Related Information
The following publications and sources of information may be useful to you or are referred to by this specification.
Industry Specifications
•System Management Bus (SMBus) Specification, version 2.0, SBS Implementers Forum, August 3, 2000: http:
//www.smbus.org
•PCI Local Bus Specification, revision 3.0, PCI Special Interest Group.
V-8UEFI Platform Initialization Specification, Release 1.8
V-2.3 SMBus Host Controller Protocol Terms
ThefollowingtermsareusedthroughoutthisdocumenttodescribethemodelforconstructingSMBusHostController
Protocol instances in the DXE environment.
PEC
SMBus
UDID
V-2.4 SMBus Host Controller Protocol Overview
The interfaces that are provided in the EFI_SMBUS_HC_PROTOCOL are used to manage data transactions on the
SMBus. The EFI_SMBUS_HC_PROTOCOL is designed to support SMBus 1.0- and 2.0-compliant host controllers.
Each instance of the EFI_SMBUS_HC_PROTOCOL corresponds to an SMBus host controller in a platform. To pro-
vide support for early drivers that need to communicate on the SMBus, this protocol is available before the Boot
Device Selection (BDS) phase. During BDS, this protocol can be attached to the device handle of an SMBus host
controller that is created by a device driver for the SMBus host controller’s parent bus type. For example, an SM-
Bus controller that is implemented as a PCI device would require a PCI device driver to produce an instance of the
EFI_SMBUS_HC_PROTOCOL .
SeeSMBus Host Controller Protocol for the definition of this protocol.
V-2.3. SMBus Host Controller Protocol Terms V-9CHAPTER
THREE
SMBUS HOST CONTROLLER CODE DEFINITIONS
V-3.1 Introduction
This section contains the basic definitions of the SMBus Host Controller Protocol. The following protocol is defined
in this section:
•EFI_SMBUS_HC_PROTOCOL
inwhichtheyarecalled. Thefollowingtypesorstructurescanbefoundin“RelatedDefinitions”oftheparentfunction
definition:
•EFI_SMBUS_NOTIFY_FUNCTION
V-3.2 SMBus Host Controller Protocol
EFI_SMBUS_HC_PROTOCOL
Summary
Provides basic SMBus host controller management and basic data transactions over the SMBus.
GUID
#define EFI_SMBUS_HC_PROTOCOL_GUID \\
{0xe49d33ed, 0x513d, 0x4634, 0xb6, 0x98, 0x6f, 0x55, \\
0xaa, 0x75, 0x1c, 0x1b}
typedef struct \_EFI_SMBUS_HC_PROTOCOL {
EFI_SMBUS_HC_EXECUTE_OPERATION Execute;
EFI_SMBUS_HC_PROTOCOL_ARP_DEVICE ArpDevice;
EFI_SMBUS_HC_PROTOCOL_GET_ARP_MAP GetArpMap;
EFI_SMBUS_HC_PROTOCOL_NOTIFY Notify;
} EFI_SMBUS_HC_PROTOCOL;
Execute
Executes the SMBus operation to an SMBus slave device. See the Execute() function description.
V-10UEFI Platform Initialization Specification, Release 1.8
ArpDevice
AllowsanSMBus2.0device(s)tobeAddressResolutionProtocol(ARP).Seethe ArpDevice() functiondescrip-
tion.
GetArpMap
AllowsadrivertoretrievetheaddressthatwasallocatedbytheSMBushostcontrollerduringenumeration/ARP.
See theGetArpMap() function description.
Notify
Allows a driver to register for a callback to the SMBus host controller driver when the bus issues a notification
to the bus controller driver. See the Notify()function description.
TheEFI_SMBUS_HC_PROTOCOL provides SMBus host controller management and basic data transactions over
SMBus. There is one EFI_SMBUS_HC_PROTOCOL instance for each SMBus host controller.
Early chipset drivers can communicate with specific SMBus slave devices by calling this protocol directly. Also, for
driversthatarecalledduringtheBootDeviceSelection(BDS)phase,thedevicedriverthatwishestomanageanSMBus
bus in a system retrieves the EFI_SMBUS_HC_PROTOCOL instance that is associated with the SMBus bus to be
managed. AdevicehandleforanSMBushostcontrollerwillminimallycontainan EFI_DEVICE_PATH_PROTOCOL
instance and an EFI_SMBUS_HC_PROTOCOL instance.
V-3.2.1 EFI_SMBUS_HC_PROTOCOL.Execute()
Summary
Executes an SMBus operation to an SMBus controller. Returns when either the command has been executed or an
error is encountered in doing the operation.
Prototype
typedef
(EFIAPI \*EFI_SMBUS_HC_EXECUTE_OPERATION) (
IN CONST EFI_SMBUS_HC_PROTOCOL \*This,
IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
IN EFI_SMBUS_DEVICE_COMMAND Command,
IN EFI_SMBUS_OPERATION Operation,
IN BOOLEAN PecCheck,
IN OUT UINTN \*Length,
IN OUT VOID \*Buffer
);
V-3.2. SMBus Host Controller Protocol V-11UEFI Platform Initialization Specification, Release 1.8
This
A pointer to the EFI_SMBUS_HC_PROTOCOL instance.
SlaveAddress
The SMBus slave address of the device with which to communicate. Type EFI_SMBUS_DEVICE_ADDRESS
is defined in EFI_PEI_SMBUS_PPI.Execute() in thePlatform Initialization SMBus PPI Specification.
Command
This command is transmitted by the SMBus host controller to the SMBus slave device and the interpretation is
SMBus slave device specific. It can mean the offset to a list of functions inside an SMBus slave device. Not
all operations or slave devices support this command’s registers. Type EFI_SMBUS_DEVICE_COMMAND is
defined in EFI_PEI_SMBUS_PPI.Execute() in thePlatform Initialization SMBus PPI Specification .
Operation
SignifieswhichparticularSMBushardwareprotocolinstancethatitwillusetoexecutetheSMBustransactions.
This SMBus hardware protocol is defined by the SMBus Specification and is not related to PI Architecture.
TypeEFI_SMBUS_OPERATION isdefinedin EFI_PEI_SMBUS_PPI.Execute*()inthe*PlatformInitialization
SMBus PPI Specification .
PecCheck
Defines if Packet Error Code (PEC) checking is required for this operation.
Length
Signifiesthenumberofbytesthatthisoperationwilldo. Themaximumnumberofbytescanberevisionspecific
andoperationspecific. Thisfieldwillcontaintheactualnumberofbytesthatareexecutedforthisoperation. Not
all operations require this argument.
Buffer
Contains the value of data to execute to the SMBus slave device. Not all operations require this argument. The
length of this buffer is identified by Length.
TheExecute() function provides a standard way to execute an operation as defined in the System Management Bus

Operation
PecCheck
Length
Buffer
(SMBus)Specification . TheresultingtransactionwillbeeitherthattheSMBusslavedevicesacceptthistransactionor
that this function returns with error.
EFI_SUCCESS The last data that was returned from the access matched the
poll exit criteria
EFI_CRC_ERROR Checksum is not correct PEC is incorrect
EFI_TIMEOUT TimeoutexpiredbeforetheoperationwascompletedTimeoutisde-
termined by the SMBus host controller device
EFI_DEVICE_ERROR Therequestwasnotcompletedbecauseafailurethatwasreflectedin
theHostStatusRegisterbitDeviceerrorsarearesultofatransaction
collisionillegalcommandfieldunclaimedcyclehostinitiatedorbus
errors collisions
EFI_INVALID_PARAMETER Operation is not defined in EFI_SMBUS_OPERATION
EFI_INVALID_PARAMETER Length Buffer is NULL for operations except for EfiSmbusQuick-
Read and EfiSmbusQuickWrite Length is outside the range of valid
values
EFI_UNSUPPORTED The SMBus operation or PEC is not supported
EFI_BUFFER_TOO_SMALL Buffer is not sufficient for this operation
V-3.2. SMBus Host Controller Protocol V-12UEFI Platform Initialization Specification, Release 1.8
V-3.2.2 EFI_SMBUS_HC_PROTOCOL.ArpDevice()
Summary
Sets the SMBus slave device addresses for the device with a given unique ID or enumerates the entire bus.
Prototype
typedef
(EFIAPI \*EFI_SMBUS_HC_PROTOCOL_ARP_DEVICE) (
IN BOOLEAN ArpAll,
IN EFI_SMBUS_UDID \*SmbusUdid, OPTIONAL
IN OUT EFI_SMBUS_DEVICE_ADDRESS \*SlaveAddress OPTIONAL
);
This
ArpAll
A Boolean expression that indicates if the host drivers need to enumerate all the devices or enumerate only the
devicethatisidentifiedby SmbusUdid . IfArpAllisTRUE,SmbusUdid andSlaveAddress areoptional. If ArpAll
isFALSE,ArpDevice will enumerate SmbusUdid and the address will be at SlaveAddress .
SmbusUdid
TheUniqueDeviceIdentifier(UDID)thatisassociatedwiththisdevice. Type EFI_SMBUS_UDID isdefinedin
EFI_PEI_SMBUS_PPI.ArpDevice*() in the *Platform Initialization SMBus PPI Specification .
The SMBus slave address that is associated with an SMBus UDID. Type EFI_SMBUS_DEVICE_ADDRESS is
defined in EFI_PEI_SMBUS_PPI.Execute() in the Platform Initialization SMBus PPI Specification.
TheArpDevice() functionprovidesastandardwayforadevicedrivertoenumeratetheentireSMBusorspecificdevices
on the bus.
EFI_DEVICE_ERROR Therequestwasnotcompletedbecauseafailurewasreflectedinthe
Host Status Register bit Device Errors are a result of a transaction
EFI_UNSUPPORTED ArpDevice GetArpMap and Notify are not implemented by this
driver
V-3.2. SMBus Host Controller Protocol V-13UEFI Platform Initialization Specification, Release 1.8
V-3.2.3 EFI_SMBUS_HC_PROTOCOL.GetArpMap()
Summary
ReturnsapointertotheAddressResolutionProtocol(ARP)mapthatcontainstheID/addresspairoftheslavedevices
that were enumerated by the SMBus host controller driver.
Prototype
typedef
(EFIAPI \*EFI_SMBUS_HC_PROTOCOL_GET_ARP_MAP) (
IN OUT EFI_SMBUS_DEVICE_MAP \**SmbusDeviceMap
);
This
Length
Size of the buffer that contains the SMBus device map.
SmbusDeviceMap
ThepointertothedevicemapasenumeratedbytheSMBuscontrollerdriver. Type EFI_SMBUS_DEVICE_MAP
is defined in EFI_PEI_SMBUS_PPI.GetArpMap*() in the *Platform Initialization SMBus PPI Specification .
TheGetArpMap() function returns the mapping of all the SMBus devices that were enumerated by the SMBus host
driver.
EFI_SUCCESS The SMBus returned the current device map
driver
V-3.2.4 EFI_SMBUS_HC_PROTOCOL.Notify()
Summary
Allows a device driver to register for a callback when the bus driver detects a state that it needs to propagate to other
drivers that are registered for a callback.
Prototype
typedef
(EFIAPI \*EFI_SMBUS_HC_PROTOCOL_NOTIFY) (
IN UINTN Data,
IN EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction
);
V-3.2. SMBus Host Controller Protocol V-14UEFI Platform Initialization Specification, Release 1.8
This
Address that the host controller detects as sending a message and calls all the registered function. Type
EFI_SMBUS_DEVICE_ADDRESS is defined in EFI_PEI_SMBUS_PPI.Execute*() in the *Platform Initializa-
tion SMBus PPI Specification .
Data
Data that the host controller detects as sending a message and calls all the registered function.
The function to call when the bus driver detects the SlaveAddress andDatapair. Type
EFI_SMBUS_NOTIFY_FUNCTION is defined in “Related Definitions” below.
TheNotify()functionregistersallthecallbackfunctionstoallowthebusdrivertocallthesefunctionswhenthe SlaveAd-
dress/Datapair happens.
// EFI_SMBUS_NOTIFY_FUNCTION
typedef
(EFIAPI \*EFI_SMBUS_NOTIFY_FUNCTION) (
IN UINTN Data
);
The SMBUS hardware address to which the SMBUS device is preassigned or allocated. Type
Data
Data of the SMBus host notify command that the caller wants to be called.
EFI_SUCCESS NotifyFunction was registered
driver
V-3.2. SMBus Host Controller Protocol V-15CHAPTER
FOUR
SMBUS DESIGN DISCUSSION
V-4.1 Introduction
These sections describe the System Management Bus (SMBus) PEIM-to-PEIM Interfaces (PPIs). This document
providesenoughmaterialtoimplementanSMBusPre-EFIInitializationModule(PEIM)thatcancontroltransactions
between an SMBus host controller and its slave devices.
ThematerialthatiscontainedinthisdocumentisdesignedtosupportcommunicationviatheSMBus. Theseextensions
are provided in the form of SMBus-specific protocols. This document provides the information that is required to
implement an SMBus PEIM in the Pre-EFI Initialization (PEI) portion of system firmware.
A full understanding of the Unified Extensible Firmware Interface Specification (UEFI specification) and the System
ManagementBus(SMBus)Specificationisassumedthroughoutthisdocument. See RelatedInformation belowforthe
URL for the System Management Bus (SMBus) Specification.
V-4.2 Target Audience
•Originalequipmentmanufacturers(OEMs)whowillbecreatingplatformsthatareintendedtobootshrink-wrap
operating systems.
•BIOS developers, either those who create general-purpose BIOS and other firmware products, or those who
modify these productss.
•Operatingsystemdeveloperswhowillbecreatingand/oradaptingtheirshrink-wrapoperatingsystemproducts.
V-4.3 Related Information
•SystemManagementBus(SMBus)Specification,version2.0,SBSImplementer’sForum,August3,2000: http:
V-16UEFI Platform Initialization Specification, Release 1.8
V-4.4 PEI SMBus PPI Overview
The PEI SMBus PPI is used by code, typically other PEIMs, that is running in the PEI environment to access data on
an SMBus slave device via the SMBus host controller. In particular, functions for managing devices on SMBus buses
are defined in this specification.
Theinterfacesthatareprovidedinthe EFI_PEI_SMBUS2_PPI areforperformingbasicoperationstoanSMBusslave
device. The system provides abstracted access to basic system resources to allow a PEIM to have a programmatic
methodtoaccessthesebasicsystemresources. ThemaingoalofthisPPIistoprovideanabstractionthatsimplifiesthe
writingofPEIMsforSMBusslavedevices. ThisgoalisaccomplishedbyprovidingastandardinterfacetotheSMBus
slave devices that does not require detailed knowledge about the particular hardware implementation or protocols of
the SMBus.
Certain implentations of the module may omit Arp capabilities. Specifically, a module will either support Execute,
ArpDevice,GetArpMap,andNotify;alternatively,amodulewillsupportonlyExecuteandreturn“notsupported”for

the SMBus.
the latter 3 services.
SeeEFI_PEI_SMBUS2_PPI forthedefinitionof EFI_PEI_SMBUS2_PPI .ThisPPIisproducedbyeachoftheSMBus
host controllers in the system.
V-4.4. PEI SMBus PPI Overview V-17CHAPTER
FIVE
SMBUS PPI CODE DEFINITIONS
V-5.1 Introduction
This section contains the basic definitions for PEIMs and SMBus devices to use during the PEI phase. The following
PPI is defined in this section:
•EFI_PEI_SMBUS2_PPI
This section also contains the definitions for additional SMBus-related data types and structures that are
subordinate to the structures in which they are called. All of the data structures below except for
EFI_PEI_SMBUS_NOTIFY_FUNCTION can be used in the DXE phase as well. The following types or structures
can be found in “Related Definitions” of the parent function definition:
•EFI_SMBUS_DEVICE_ADDRESS
•EFI_SMBUS_DEVICE_COMMAND
•EFI_SMBUS_OPERATION
•EFI_SMBUS_UDID
•EFI_SMBUS_DEVICE_MAP
•EFI_PEI_SMBUS_NOTIFY_FUNCTION
V-5.2 PEI SMBus PPI
V-5.2.1 EFI_PEI_SMBUS2_PPI
Summary
Provides the basic I/O interfaces that a PEIM uses to access its SMBus controller and the slave devices attached to it.
GUID
#define EFI_PEI_SMBUS2_PPI_GUID \\
{ 0x9ca93627, 0xb65b, 0x4324, \\
0xa2, 0x2, 0xc0, 0xb4, 0x61, 0x76, 0x45, 0x43 }
typedef struct \_EFI_PEI_SMBUS2_PPI {
EFI_PEI_SMBUS2_PPI_EXECUTE_OPERATION Execute;
EFI_PEI_SMBUS2_PPI_ARP_DEVICE ArpDevice;
V-18UEFI Platform Initialization Specification, Release 1.8
EFI_PEI_SMBUS2_PPI_GET_ARP_MAP GetArpMap;
EFI_PEI_SMBUS2_PPI_NOTIFY Notify;
EFI_GUID Identifier
} EFI_PEI_SMBUS2_PPI;
Execute
ArpDevice
tion.
GetArpMap
AllowsaPEIMtoretrievetheaddressthatwasallocatedbytheSMBushostcontrollerduringenumeration/ARP.
Notify
Allows a PEIM to register for a callback to the SMBus host controller PEIM when the bus issues a notification
to the bus controller PEIM. See the Notify()function description.
Identifier
Identifier which uniquely identifies this SMBus controller in a system.
TheEFI_PEI_SMBUS2_PPI provides the basic I/O interfaces that are used to abstract accesses to SMBus host con-
trollers. There is one EFI_PEI_SMBUS2_PPI instance for each SMBus host controller in a system. A PEIM that
wishestomanageanSMBusslavedeviceinasystemwillhavetoretrievethe EFI_PEI_SMBUS2_PPI instancethatis
associated with its SMBus host controller.
V-5.2.2 EFI_PEI_SMBUS2_PPI.Execute()
Summary
Prototype
typedef
(EFIAPI \*EFI_PEI_SMBUS2_PPI_EXECUTE_OPERATION) (
IN CONST EFI_PEI_SMBUS2_PPI \*This,
);
This
A pointer to the EFI_PEI_SMBUS2_PPI instance.
V-5.2. PEI SMBus PPI V-19UEFI Platform Initialization Specification, Release 1.8
EFI_SMBUS_DEVICE_ADDRESS is defined in “Related Definitions” below.
Command
Operation
This SMBus hardware protocol is defined by the System Management Bus (SMBus) Specification and is not
related to UEFI. Type EFI_SMBUS_OPERATION is defined in “Related Definitions” below.
PecCheck
Length
andoperationspecific. Thisparameterwillcontaintheactualnumberofbytesthatareexecutedforthisoperation.
Not all operations require this argument.
Buffer
// EFI_SMBUS_DEVICE_ADDRESS
typedef struct \_EFI_SMBUS_DEVICE_ADDRESS {
UINTN SmbusDeviceAddress:7;
} EFI_SMBUS_DEVICE_ADDRESS;
SmbusDeviceAddress
The SMBUS hardware address to which the SMBUS device is preassigned or allocated.
// EFI_SMBUS_DEVICE_COMMAND
typedef UINTN EFI_SMBUS_DEVICE_COMMAND;
// EFI_SMBUS_OPERATION
typedef enum \_EFI_SMBUS_OPERATION {
EfiSmbusQuickRead,
EfiSmbusQuickWrite,
EfiSmbusReceiveByte,
V-5.2. PEI SMBus PPI V-20UEFI Platform Initialization Specification, Release 1.8
EfiSmbusSendByte,
EfiSmbusReadByte,
EfiSmbusWriteByte,
EfiSmbusReadWord,
EfiSmbusWriteWord,
EfiSmbusReadBlock,
EfiSmbusWriteBlock,
EfiSmbusProcessCall,
EfiSmbusBWBRProcessCall
} EFI_SMBUS_OPERATION;
See theSystem Management Bus (SMBus) Specification for descriptions of the fields in the above definition.
EFI_SUCCESS Thelastdatathatwasreturnedfromtheaccessmatchedthepollexit
criteria
EFI_CRC_ERROR The checksum is not correct PEC is incorrect
EFI_DEVICE_ERROR TherequestwasnotcompletedbecauseafailurereflectedintheHost
StatusRegisterbitDeviceerrorsarearesultofatransactioncollision
illegal command field unclaimed cycle host initiated or bus errors
collisions
values
V-5.2.3 EFI_PEI_SMBUS2_PPI.ArpDevice()
Summary
Prototype
typedef
(EFIAPI \*EFI_PEI_SMBUS2_PPI_ARP_DEVICE) (
);
Paramaters
This
V-5.2. PEI SMBus PPI V-21UEFI Platform Initialization Specification, Release 1.8
ArpAll
A Boolean expression that indicates if the host PEIMs need to enumerate all the devices or enumerate only the
SmbusUdid
The targeted SMBus Unique Device Identifier (UDID). The UDID may not exist for SMBus devices with fixed
addresses. Type EFI_SMBUS_UDID is defined in “Related Definitions” below.
The new SMBus address for the slave device for which the operation is targeted. Type
EFI_SMBUS_DEVICE_ADDRESS is defined in EFI_PEI_SMBUS2_PPI.Execute() .
TheArpDevice() function enumerates the entire bus or enumerates a specific device that is identified by SmbusUdid .
// EFI_SMBUS_UDID
typedef struct \_EFI_SMBUS_UDID {
UINT32 VendorSpecificId;
UINT16 SubsystemDeviceId;
UINT16 SubsystemVendorId;
UINT16 Interface;
UINT16 DeviceId;
UINT8 VendorRevision;
UINT8 DeviceCapabilities;
} EFI_SMBUS_UDID;
VendorSpecificId
A unique number per device.
SubsystemDeviceId
Identifies a specific interface, implementation, or device. The subsystem ID is defined by the party that is iden-
tified by the SubsystemVendorId field.
SubsystemVendorId
This field may hold a value that is derived from any of several sources:
•The device manufacturer’s ID as assigned by the SBS Implementer’s Forum or the PCI SIG.

•The device OEM’s ID as assigned by the SBS Implementer’s Forum or the PCI SIG.
•A value that, in combination with the SubsystemDeviceId , can be used to identify an organization or
industry group that has defined a particular common device interface specification.
Interface
IdentifiestheprotocollayerinterfacesthataresupportedovertheSMBusconnectionbythedevice. Forexample,
Alert Standard Format (ASF) and IPMI.
DeviceId
The device ID as assigned by the device manufacturer (identified by the VendorId field).
VendorId
The device manufacturer’s ID as assigned by the SBS Implementer’s Forum or the PCI SIG.
V-5.2. PEI SMBus PPI V-22UEFI Platform Initialization Specification, Release 1.8
VendorRevision
UDID version number and a silicon revision identification.
DeviceCapabilities
Describes the device’s capabilities.
EFI_SUCCESS The SMBus slave device address was set
EFI_INVALID_PARAMETER SlaveAddress is NULL
EFI_TIMEOUT The SMBus slave device did not respond
EFI_DEVICE_ERROR TherequestwasnotcompletedbecausethetransactionfailedDevice
errorsarearesultofatransactioncollisionillegalcommandfieldor
unclaimed cycle host initiated
PEIM
V-5.2.4 EFI_PEI_SMBUS2_PPI.GetArpMap()
Summary
that were enumerated by the SMBus host controller PEIM.
Prototype
typedef
(EFIAPI \*EFI_PEI_SMBUS2_PPI_GET_ARP_MAP) (
IN CONST EFI_PEI_SMBUS_PPI \*This,
);
This
Length
ThepointertothedevicemapasenumeratedbytheSMBuscontrollerPEIM.Type EFI_SMBUS_DEVICE_MAP
TheGetArpMap() function returns the mapping of all the SMBus devices that are enumerated by the SMBus host
PEIM.
// EFI_SMBUS_DEVICE_MAP
V-5.2. PEI SMBus PPI V-23UEFI Platform Initialization Specification, Release 1.8
typedef struct \_EFI_SMBUS_DEVICE_MAP {
EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress;
EFI_SMBUS_UDID SmbusDeviceUdid;
} EFI_SMBUS_DEVICE_MAP;
SmbusDeviceUdid
TheSMBUSUniqueDeviceIdentifier(UDID)asdefinedin EFI_SMBUS_UDID .TypeEFI_SMBUS_UDID is
defined in EFI_PEI_SMBUS2_PPI.ArpDevice().
EFI_SUCCESS The device map was returned correctly in the buffer
PEIM
V-5.2.5 EFI_PEI_SMBUS2_PPI.Notify()
Summary
Allows a PEIM to register for a callback when the PEIM detects a state that it needs to propagate to other PEIMs that
are registered for a callback.
Prototype
typedef
(EFIAPI \*EFI_PEI_SMBUS2_PPI_NOTIFY) (
IN EFI_PEI_SMBUS_NOTIFY2_FUNCTION NotifyFunction
);
This
Address that the host controller detects as sending a message and calls all the registered functions. Type
Data
Data that the host controller detects as sending a message and calls all the registered functions.
The function to call when the PEIM detects the SlaveAddress andDatapair. Type
EFI_PEI_SMBUS_NOTIFY2_FUNCTION is defined in “Related Definitions” below.
V-5.2. PEI SMBus PPI V-24UEFI Platform Initialization Specification, Release 1.8
TheNotify()functionregistersallthecallbackfunctionstoallowthePEIMtocallthesefunctionswhenthe SlaveAddress
/Datapair happens.
// EFI_PEI_SMBUS_NOTIFY2_FUNCTION
typedef
(EFIAPI \*EFI_PEI_SMBUS_NOTIFY2_FUNCTION) (
IN CONST EFI_PEI_SMBUS_PPI \*SmbusPpi,
);
SmbusPpi
Data
EFI_SUCCESS NotifyFunction has been registered
PEIM
V-5.2. PEI SMBus PPI V-25CHAPTER
SIX
SMBIOS PROTOCOL
V-6.1 EFI_SMBIOS_PROTOCOL
Summary
AllowsconsumerstologSMBIOSdatarecords,andenablestheproducertocreatetheSMBIOStablesforaplatform.
GUID
#define EFI_SMBIOS_PROTOCOL_GUID \\
{ 0x3583ff6, 0xcb36, 0x4940, { 0x94, 0x7e, 0xb9, 0xb3, 0x9f,\\
0x4a, 0xfa, 0xf7 } }
typedef struct \_EFI_SMBIOS_PROTOCOL {
EFI_SMBIOS_ADD *Add* ;
EFI_SMBIOS_UPDATE_STRING *UpdateString* ;
EFI_SMBIOS_REMOVE *Remove* ;
EFI_SMBIOS_GET_NEXT *GetNext* ;
UINT8 *MajorVersion* ;
UINT8 *MinorVersion* ;
} EFI_SMBIOS_PROTOCOL;
Member Description
Add
Add an SMBIOS record including the formatted area and the optional strings that follow the formatted area.
UpdateString
Update a string in the SMBIOS record.
Remove
Remove an SMBIOS record.
GetNext
Discover all SMBIOS records.
MajorVersion
The major revision of the SMBIOS specification supported.
MinorVersion
The minor revision of the SMBIOS specification supported.
Desscription
V-26UEFI Platform Initialization Specification, Release 1.8
This protocol provides an interface to add, remove or discover SMBIOS records. The driver which produces this
protocol is responsible for creating the SMBIOS data tables and installing the pointer to the tables in the EFI System
Configuration Table.
ThecallerisresponsibleforonlyaddingSMBIOSrecordsthatarevalidfortheSMBIOS MajorVersion andMinorVer-
sion. When an enumerated SMBIOS field’s values are controlled by the DMTF, new values can be used as soon as
they are defined by the DMTF without requiring an update to MajorVersion andMinorVersion .
The SMBIOS protocol can only be called a TPL < TPL_NOTIFY .
V-6.2 EFI_SMBIOS_PROTOCOL.Add()
Summary
Add an SMBIOS record.
Prototype
typedef
(EFIAPI \*EFI_SMBIOS_ADD) (
IN CONST EFI_SMBIOS_PROTOCOL *\*This* ,
IN EFI_HANDLE *ProducerHandle* , OPTIONAL
IN OUT EFI_SMBIOS_HANDLE *\*SmbiosHandle* ,
IN EFI_SMBIOS_TABLE_HEADER *\*Record*
);
This
TheEFI_SMBIOS_PROTOCOL instance.
ProducerHandle
The handle of the controller or driver associated with the SMBIOS information. NULLmeans no handle.
SmbiosHandle
On entry, the handle of the SMBIOS record to add. If FFFEh, then a unique handle will be assigned to the SM-
BIOSrecord. IftheSMBIOShandleisalreadyinuse, EFI_ALREADY_STARTED isreturnedandtheSMBIOS
record is not updated.
Record
The data for the fixed portion of the SMBIOS record. The format of the record is deter-
mined by EFI_SMBIOS_TABLE_HEADER .*Type* . The size of the formatted area is defined by
EFI_SMBIOS_TABLE_HEADER .*Length*andeitherfollowedbyadouble-null(0x0000)orasetofnulltermi-
nated strings and a null.
This function allows any agent to add SMBIOS records. The caller is responsible for ensuring Recordis formatted in
awaythatmatchestheversionoftheSMBIOSspecificationasdefinedinthe MajorRevision andMinorRevision fields
of theEFI_SMBIOS_PROTOCOL .
RecordmustfollowtheSMBIOSstructureevolutionandusageguidelinesintheSMBIOSspecification. Recordstarts
withtheformattedareaoftheSMBIOSstructureandthelengthisdefinedby EFI_SMBIOS_TABLE_HEADER.Length
. Each SMBIOS structure is terminated by a double-null (0x0000), either directly following the formatted area (if no
stringsarepresent)ordirectlyfollowingthelaststring. Thenumberofoptionalstringsisnotdefinedbytheformatted
area, but is fixed by the call to Add(). A string can be a place holder, but it must not be a NULLstring as two NULL
strings look like the double-null that terminates the structure.
V-6.2. EFI_SMBIOS_PROTOCOL.Add() V-27UEFI Platform Initialization Specification, Release 1.8
*typedef UINT8 EFI_SMBIOS_TYPE;*
*typedef UINT16 EFI_SMBIOS_HANDLE;*
EFI_SMBIOS_TYPE *Type* ;
UINT8 *Length* ;
EFI_SMBIOS_HANDLE *Handle* ;
} EFI_SMBIOS_TABLE_HEADER;
#define EFI_SMBIOS_TYPE_BIOS_INFORMATION 0
#define EFI_SMBIOS_TYPE_SYSTEM_INFORMATION 1
#define EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION 2
#define EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE 3
#define EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION 4
#define EFI_SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION 5

#define EFI_SMBIOS_TYPE_MEMORY_MODULE_INFORMATON 6
#define EFI_SMBIOS_TYPE_CACHE_INFORMATION 7
#define EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION 8
#define EFI_SMBIOS_TYPE_SYSTEM_SLOTS 9
#define EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION 10
#define EFI_SMBIOS_TYPE_OEM_STRINGS 11
#define EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS 12
#define EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION 13
#define EFI_SMBIOS_TYPE_GROUP_ASSOCIATIONS 14
#define EFI_SMBIOS_TYPE_SYSTEM_EVENT_LOG 15
#define EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY 16
#define EFI_SMBIOS_TYPE_MEMORY_DEVICE 17
#define EFI_SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION 18
#define EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS 19
#define EFI_SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS 20
#define EFI_SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE 21
#define EFI_SMBIOS_TYPE_PORTABLE_BATTERY 22
#define EFI_SMBIOS_TYPE_SYSTEM_RESET 23
#define EFI_SMBIOS_TYPE_HARDWARE_SECURITY 24
#define EFI_SMBIOS_TYPE_SYSTEM_POWER_CONTROLS 25
#define EFI_SMBIOS_TYPE_VOLTAGE_PROBE 26
#define EFI_SMBIOS_TYPE_COOLING_DEVICE 27
#define EFI_SMBIOS_TYPE_TEMPERATURE_PROBE 28
#define EFI_SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE 29
#define EFI_SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS 30
#define EFI_SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE 31
#define EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION 32
#define EFI_SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION 33
#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE 34
#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT 35
#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA 36
#define EFI_SMBIOS_TYPE_MEMORY_CHANNEL 37
#define EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION 38
#define EFI_SMBIOS_TYPE_SYSTEM_POWER_SUPPLY 39
#define EFI_SMBIOS_TYPE_ADDITIONAL_INFORMATION 40
V-6.2. EFI_SMBIOS_PROTOCOL.Add() V-28UEFI Platform Initialization Specification, Release 1.8
#define EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
#define EFI_SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
#define EFI_SMBIOS_TYPE_INACTIVE 126
#define EFI_SMBIOS_TYPE_END_OF_TABLE 127
#define EFI_SMBIOS_OEM_BEGIN 128
#define EFI_SMBIOS_OEM_END 255
typedef UINT8 EFI_SMBIOS_STRING;
Note:These types are consistent with the DMTF SMBIOS 2.7 specification
EFI_SUCCESS Recordwas added.
EFI_OUT_OF_RESOURCES Recordwas not added.
EFI_ALREADY_STARTED TheSmbiosHandle passed in was already in use.
V-6.3 EFI_SMBIOS_PROTOCOL.UpdateString()
Summary
Update the string associated with an existing SMBIOS record.
Prototype
typedef
(EFIAPI \*EFI_SMBIOS_UPDATE_STRING) (
IN EFI_SMBIOS_HANDLE *\*SmbiosHandle* ,
IN UINTN *\*StringNumber* ,
IN CHAR8 *\*String*
);
This
SMBIOS Handle of structure that will have its string updated.
StringNumber
The non-zero string number of the string to update
String
Update the StringNumber string with String.
This function allows the update of specific SMBIOS strings. The number of valid strings for any SMBIOS record is
defined by how many strings were present when Add()was called.
V-6.3. EFI_SMBIOS_PROTOCOL.UpdateString() V-29UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS SmbiosHandle had itsStringNumber String updated
EFI_INVALID_PARAMETER SmbiosHandle does not exist
EFI_UNSUPPORTED String was not added because it is longer than the SMBIOS Table
supports
EFI_NOT_FOUND TheStringNumber is not valid for this SMBIOS record
V-6.4 EFI_SMBIOS_PROTOCOL.Remove()
Summary
Prototype
typedef
(EFIAPI \*EFI_SMBIOS_REMOVE) (
IN EFI_SMBIOS_HANDLE *SmbiosHandle*
);
This
The handle of the SMBIOS record to remove.
This function removes an SMBIOS record using the handle specified by SmbiosHandle.
EFI_SUCCESS SMBIOS record was removed
EFI_INVALID_PARAMETER SmbiosHandle does not specify a valid SMBIOS record
V-6.5 EFI_SMBIOS_PROTOCOL.GetNext()
Summary
Allow the caller to discover all or some of the SMBIOS records.
Prototype
typedef
(EFIAPI \*EFI_SMBIOS_GET_NEXT) (
IN EFI_SMBIOS_TYPE *\*Type* , OPTIONAL
OUT EFI_SMBIOS_TABLE_HEADER *\**Record,*
V-6.4. EFI_SMBIOS_PROTOCOL.Remove() V-30UEFI Platform Initialization Specification, Release 1.8
OUT EFI_HANDLE *\*ProducerHandle* OPTIONAL
);
This
On entry, points to the previous handle of the SMBIOS record. On exit, points to the next SMBIOS record
handle. If it is FFFEh on entry, then the first SMBIOS record handle will be returned. If it returns FFFEh on
exit, then there are no more SMBIOS records.
Type
Onentry,itpointstothetypeofthenextSMBIOSrecordtoreturn. IfNULL,itindicatesthatthenextrecordof
any type will be returned. Typeis not modified by the this function.
Record
On exit, points to a pointer to the the SMBIOS Record consisting of the formatted area followed by the unfor-
matted area. The unformatted area optionally contains text strings.
Onexit,pointstothe ProducerHandle registeredby Add(). IfnoProducerHandle waspassedinto Add()NULL
is returned. If a NULLpointer is passed in no data will be returned
This function allows all of the SMBIOS records to be discovered. It’s possible to find only the SMBIOS records that
match the optional Typeargument.
EFI_SUCCESS SMBIOS record information was successfully returned in Record.
SmbiosHandle is the handle of the current SMBIOS record
EFI_INVALID_PARAMETER The SMBIOS record with SmbiosHandle was the last available
record.
V-6.5. EFI_SMBIOS_PROTOCOL.GetNext() V-31CHAPTER
SEVEN
IDE CONTROLLER
V-7.1 IDE Controller Overview
This specification defines the core code and services that are required for an implementation of the IDE Controller
InitializationProtocoloftheUEFIPlatformInitializationSpecification. Thisprotocolisadriverentitysuchasadriver
entitytoprogramanIDEcontrollerandtoobtainIDEdevicetiminginformation. Thisprotocolabstractsthenonstan-
dard parts of an IDE controller. This protocol is not tied to any specific bus.
This specification does the following:
•Describes the basic components of the IDE Controller Initialization Protocol
•Provides code definitions for the IDE Controller Initialization Protocol and other IDE-controller-related type
definitions that are architecturally required
V-7.2 Design Discussion
V-7.2.1 IDE Controller Initialization Protocol Overview
This section discusses the IDE Controller Initialization Protocol. This protocol is used by a driver entity to program
an IDE controller and to obtain IDE device timing information. This protocol abstracts the nonstandard parts of IDE
controller. This protocol is mandatory on platforms with IDE controllers that are managed by a driver entity.
See IDE Controller Initialization Protocol in Code Definitions for the definition of
EFI_IDE_CONTROLLER_INIT_PROTOCOL .
V-7.2.1.1 IDE Controller Terms
The following terms are used throughout this document.
AHCI
Advanced Host Controller Interface.
ATAPI
AT Attachment Packet Interface
enumeration group
The set of IDE devices that must be enumerated as a group. In other words, if device A and device B belong to
an enumeration group and device A needs to be configured, device B must be configured at the same time and
vice versa. There are two possible enumeration groupings for an IDE controller:
V-32UEFI Platform Initialization Specification, Release 1.8
•“All the devices on a channel. In this case, the number of enumeration groups is equal to the number of
channels.
•“AllthedevicesonallthechannelsbehindanIDEcontroller. Thisenumerationgroupingmayarisebecause
multiplechannelssharesomehardwareregistersorhavesomeotherdependencies. Inthiscase,thenumber
of enumeration groups is 1.
The IDE controller indicates the type of enumeration group that is applicable. In case 2, the driver entity must
enumerateallthedevicesonallthechannelsifthereisarequesttoconfigureasingledevice. Incase1,thedriver
entitymustenumerateallthedevicesonthesamechannelifthereisarequesttoconfigureasingledevice. Case
1 will lead to faster boot.
IDE controller
The hardware device that produces one or more IDE buses (channels). Each channel can host one or more IDE
devices.
PATA
Parallel ATA.
PATA controller
An IDE controller that supports PATA devices. Traditionally, a PATA controller supports up to two channels:
primary and secondary. Each channel traditionally supports up to two devices: master and slave.
SATA
Serial ATA.
SATA controller
An IDE controller that supports the SATA driver. SATA controllers can emulate PATA behavior. The behavior
of command and control block registers, PIO and DMA data transfers, resets, and interrupts are all emulated.

devices.
PATA
SATA
In addition, SATA controllers can implement a more modern register interface, namely AHCI. AHCI allows
the host software to overcome the limitations that are imposed by PATA emulation and to use advanced SATA
features.
SomechipsetscontainbothPATAandSATAcontrollersandsupportacombinedmode. Incombinedmode,the
twocontrollersarelogicallymergedintoonecontroller. ThePATAdrivescanappearbehindtheSATAcontroller
to the host software. In such a mode, all the PATA rules in terms of IDE timing configuration apply to SATA
V-7.2.2 IDE Controller Initialization Protocol References
The following sources of information are referenced in this specification or may be useful to you.
•”ATA Host Adapter Standards , Working Draft Version of: http://www.t13.org/*
•”Information Technology - AT Attachment with Packet Interface - 6 (ATA/ATAPI-6): http://www.t13.org/*
•Serial ATA Advanced Host Controller Interface (AHCI) Specification , version 1.0: http://developer.intel.com/
technology/serialata/ahci.htm
•Serial ATA: High Speed Serialized AT Attachment , revision 1.0a (may also be referred to as Serial ATA Speci-
fication 1.0a): http://www.serialata.org/*
•”Serial ATA II: Port Multiplier Specification , revision 1.1: http://www.serialata.org/*
V-7.2. Design Discussion V-33UEFI Platform Initialization Specification, Release 1.8
V-7.2.3 Background
V-7.2.3.1 IDE Requirements
The IDE Controller Initialization Protocol is designed to work for both Parallel ATA (PATA) and Serial ATA (SATA)
IDE controllers.
This protocol is designed with the following requirements in mind:
1. ThetimingregistersinaPATAIDEcontrollerarevendorspecific. (See ATAHostAdapterStandards ,Working
Draft Version 0f, for more information.) The programming of these registers needs to be abstracted from the
driver entity.
2. TheIDEControllerInitializationProtocolshouldalsosupportacasewhereaspecificchannelisdisabledand/or
it should not be scanned. This protocol also needs a mechanism to address individual devices in various SATA
and PATA configurations. This protocol needs to support the following:
3. “A variable number of channels per controller
4. “A variable number of devices per channel
V-7.2.3.1.1 PATA Controllers
PATA controllers support up to two channels and each channel can have a maximum of two devices.
V-7.2.3.1.2 SATA Contollers
SATA controllers can support standard ATA emulation. As described in the Serial ATA Specification 1.0a , ATA
emulation can either be master-only emulation or master-slave emulation. In either case, the SATA controller appears
tohaveoneortwochannels. Inmaster-onlyemulation,amaximumofonedriveappearsonachannel. Inmaster-slave
emulation, one or two drives can show up behind a channel.
When an SATA controller is operating in Advanced Host Controller Interface (AHCI) mode, it can support up to 32
ports. The SATA port that is generated by an SATA controller can host an SATA port multiplier. There can be up to
16 SATA devices on the other side of the SATA port multiplier.
Inthisgeometry,eachSATAportthatisgeneratedbytheSATAcontrolleristreatedasachannel,andthischannelcan
have up to 16 devices. This is done so that PATA drives as well as SATA drives can be represented using a ( Channel
,Device) address pair. Note that the SATA channels work very differently from PATA channels in the sense that the
SATA channels do not have the concept of master/slave or daisy chaining.
See Figure 2 1 and Figure 2 2 below for explanations how the devices are addressed.
V-7.2.3.1.3 Bus Neutral
It should be possible to use the same abstractions to support an IDE controller on the PCI bus or some other bus. The
IDE controller driver will know which controller devices it can support. Because the majority of IDE controllers that
existtodayarelocatedonthePCIbus,alltheexampleswillrefertoPCIIDEcontrollers,buttheprotocolisnottiedto
the PCI bus.
V-7.2. Design Discussion V-34UEFI Platform Initialization Specification, Release 1.8
V-7.2.3.2 PCI IDE controller
PCIIDEcontrollerscanoperateinnativePCImodeorcompatibilitymode. TheIDEControllerInitializationProtocol
should permit both modes.
The design should use the EFI Driver Model to support the quick boot feature. The smallest unit of initialization is
one channel. By default, the driver entity initializes only the channel on which the user-requested drive resides. The
IDE Controller Initialization Protocol should support the case where various channels share the same hardware bits
andcannotbeindependentlyenumerated. Thecontrollerdrivercanspecifythatallthechannelsshouldbeenumerated
as one unit.
TheIDEControllerInitializationProtocolmustsupportSATAcontrollersthatmayormaynotimplementAHCIregister
V-7.2.4 Simplifying the Design of IDE Drivers
The IDE bus is not a general-purpose bus. The standard ATA and ATAPI command sets support only a storage class
of devices. The following design decisions can be made to simplify the IDE Controller Initialization Protocol and the
design of IDE drivers:
•“The driver entity is the only driver that will send commands to the ATA devices. No device-specific drivers
are needed for IDE devices because all the devices belong to the same class (i.e., storage) and the driver en-
tity can have inherent knowledge of these commands. IDE bus equivalents of EFI_PCI_IO_PROTOCOL and
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL foraccessingIDEdevicesarenotrequired. Itispossibletofurther
simplify the design of the driver entity if it does not have to deal with the ATAPI devices. It can enumerate the
ATA and ATAPI devices and install the EFI_SCSI_PASSTHRU_PROTOCOL on ATAPI device handles. Either
way, IDE-bus-specific I/O protocols are not needed. See the UEFI Specification for the definitions of the EFI
PCI I/O Protocol, PCI Root Bridge I/O Protocol, and the SCSI Pass Thru Protocol.
•“IDE devices are accessed and configured through a set of standard registers in the IDE controller. The ATA
committee is standardizing the layout of these registers. (See ATA Host Adapter Standards , Working Draft
Version0f,formoreinformation.) ForSerialATA(SATA)controllers,the SerialATAAdvancedHostController
Interface(AHCI)Specification definesastandardregisterinterface. Althoughthelayoutisdependentonthebus
on which the controller is located, the layout for a particular bus is fixed. As a result, the driver entity can be
required to know about the register layout for buses that it chooses to support. For example, for a PCI IDE
controller, the IDE driver can access the base of the command block register for channel 0 using the following
steps:
1. Check bit 0 of register 0x9 (Programming Interface Code) in the PCI configuration space of the controller to
determine whether it is operating in compatibility mode or native PCI mode. For this example, we will assume
that the controller is operating in native mode.
2. Read register 0x10 (Base Address Register [BAR] 0) of the controller. Clear bit 0 of the value that was read to
get the command block base
V-7.2.5 Configuring Devices on the IDE Bus
The table below lists the various drivers that may participate in configuring the devices on the IDE bus.
V-7.2. Design Discussion V-35UEFI Platform Initialization Specification, Release 1.8
Table 7.1: Drivers Involved in Configuring IDE Devices
Driver Follows the EFI
Driver ModelDescription
driverYes Produces the EFI_IDE_CONTR OLLER_INIT_PROTOCOL
Consumes the bus specific I O protocol EFI_IDE_CONT
ROLLER_INIT_PROTOCOL abstracts the chipset specific
IDE controller registers and is responsible for early initial-
ization of the IDE controller Note that EFI_IDE_CONT
ROLLER_INIT_PROTOCOL is not tied to a specific bus al-
though most IDE controllers today are on the PCI or ISA bus
Driver entity Yes Consumes the EFI_IDE_CONT ROLLER_INIT_PROTOCOL and
the bus specific I O protocol It enumerates the IDE buses
This driver will check for the presence of the EFI_IDE_CONT
ROLLER_INIT_PROTOCOL on the controller handle before enu-
merating the child devices This driver uses the presence of
the EFI_IDE_CONT ROLLER_INIT_PROTOCOL to determine
whether a controller is an IDE controller or not This driver will use
bus specific methods to access the standard ATA registers such as
thecontrolblockcommandblockandbusmasterDMAregistersfor
a particular device The driver not only knows the address of a spe-
cificregisterblockbutitalsoknowsthelayoutofthatregisterblock
ThisdrivermayproducetheEFI_SCSI_PASSTHRU_PROTOCOL
for ATAPI devices or it may directly manage the ATAPI devices by
producingtheEFI_BLOCK_IO_PROTOCOLThisdriverproduces
the E FI_BLOCK_IO_PROTOCOL for ATA devices
Generic SCSI or
ATAPI storage
driverYes This optional driver manages the ATAPI device using the
EFI_SC SI_PASSTHRU_PROTOCOL and produces the E
FI_BLOCK_IO_PROTOCOL if requested
Driver entity and
driver combined as
one driverYes It is also possible to combine the driver entity and the IDE
controller driver into one driver In this case EFI_IDE_CONTR
OLLER_INIT_PROTOCOL is not installed on the IDE controller

handle The monolithic driver is responsible for initializing the
IDE controller as well as the IDE devices behind that controller
EFI_IDE_CONTROLLER_INIT_PROTOCOLismandatoryifthe
IDE devices behind the controller are to be enumerated by the
generic driver entity
See the UEFI Specification for the definitions of the Block I/O Protocol and the SCSI Pass Thru Protocol. The IDE
Controller Initialization Protocol is defined in Code Definitions of this specification.
V-7.2.6 Sample Implementation for a Simple PCI IDEController
This topic provides a sample implementation only. The sequencing of various notifications cannot be changed. The
steps below apply if EFI_IDE_CONTROLLER_INIT_PROTOCOL.EnumAll =FALSE.
SeetheUEFISpecification fordefinitionsoftheDriverBindingProtocol,EFIPCII/OProtocol,DevicePathProtocol,
andBlockI/OProtocol. SeeCodeDefinitionsinthisspecificationforthedefinitionoftheIDEControllerInitialization
Protocol.
1. The IDE controller driver as well as the driver entity follow the EFI Driver Model. They are loaded and both
install(atleast)oneinstanceofthe EFI_DRIVER_BINDING_PROTOCOL ontheirimagehandle. AnATAhard
drive behind a PCI IDE controller is one of the boot devices.
V-7.2. Design Discussion V-36UEFI Platform Initialization Specification, Release 1.8
2. The PCI bus driver enumerates the PCI bus, finds the PCI IDE controller, creates a handle for it, and installs an
instance of EFI_PCI_IO_PROTOCOL andEFI_DEVICE_PATH_PROTOCOL on that handle.
3. TheBootDeviceSelection(BDS)phasesearchesforanappropriatedrivertoowntheIDEcontrollerdeviceand
findstheIDEcontrollerdriver. ItthenconnectstheIDEcontrollerdeviceandtheIDEcontrollerdriver. TheIDE
controller driver opens the EFI_PCI_IO_PROTOCOL BY_DRIVER . It may perform some other preprogram-
ming at this point.
4. BDS searches for a driver to own the IDE device and finds the driver entity. The driver entity’s Supported()
functionchecksforthepresenceof EFI_IDE_CONTROLLER_INIT_PROTOCOL ontheparentoftheIDEdevice
(i.e., the IDE controller).
5. The EFI Boot Services function ConnectController() calls theStart()function of the driver entity, which starts
the IDE bus enumeration. The following steps are performed by the Start()function.
•The driver entity locates the EFI_IDE_CONTROLLER_INIT_PROTOCOL . It opens the
EFI_IDE_CONTROLLER_INIT_PROTOCOLBY_DRIVER .Ifitneedstoopen EFI_PCI_IO_PROTOCOL
, it may open it by GET_PROTOCOL . The driver entity reads the EnumAll andChannelCount fields in
EFI_IDE_CONTROLLER_INIT_PROTOCOL . In this case, EnumAll isFALSE. The driver entity also
obtains the channel number from Start().RemainingDevicePath .
•The driver entity calls EFI_IDE_CONTROLLER_INIT_PROTOCOL.NotifyPhase (This,EfiIdeBe-
foreChannelEnumeration ,Channel).
•The driver entity calls EFI_IDE_CONTROLLER_INIT_PROTOCOL.GetChannelInfo (This,Channel ,
*Enabled ,*MaxDevices )tofindoutthenumberofdevicesonthischannel. If *Enabled =FALSE, itexits
with an error code. If the device number of the device to be connected is too large, it exits with an error
code.
•The driver entity calls*EFI_IDE_CONTROLLER_INIT_PROTOCOL.NotifyPhase* ( This,*EfiIdeBe-
foreChannelReset* , Channel).
•The driver entity resets the channel.
•Thedriverentitycalls EFI_IDE_CONTROLLER_INIT_PROTOCOL.NotifyPhase (This,EfiIdeAfterChan-
nelReset,Channel).
•Thedriverentitycalls EFI_IDE_CONTROLLER_INIT_PROTOCOL.NotifyPhase (This,EfiIdeBeforeDe-
vicePresenceDetection ,Channel). The IDE controller driver may insert a predelay here or may ensure
that various IDE bus signals are at desired levels.
•Thedriverentityattemptstodetectdevicesonthechannel. NotethantherecanbenomorethanMaxDevices
on the channel.
•Thedriverentitycalls EFI_IDE_CONTROLLER_INIT_PROTOCOL.NotifyPhase (This,EfiIdeAfterDevi-
cePresenceDetection ,Channel).
•Thedriverentitycalls EFI_IDE_CONTROLLER_INIT_PROTOCOL.NotifyPhase (This,EfiIdeResetMode
,Channel). The IDE controller sets up the controller with the default timings.
6. For all the devices on this channel:
•The driver entity gathers EFI_IDENTIFY_DATA for the device and submits it to the IDE controller driver
usingEFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() . SubmitNULLdatafordevicesthatdo
not exist.
•The driver entity may call EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() to disqualify
modes that it does not support.
7. For all the detected devices on this channel:
V-7.2. Design Discussion V-37UEFI Platform Initialization Specification, Release 1.8
•CallEFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() to get the optimum mode settings.
The IDE controller driver uses controller-specific algorithms and platform information to calculate the
best modes.
•The driver entity enables the appropriate modes by sending an ATA SET_FEATURES command to the
device. Itthedevicereturnsanerror,itdisqualifiesthatmodeforthatdeviceandgoesbacktostep7. This
time step 7 (first bullet) will not consider the failed mode. The implementation then returns here to step 7
(second bullet) with new (less optimum) modes.
8. For all the detected devices on this channel, call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SetTiming() to
program the timings. Note that we reset the mode settings in step 5(last bullet), so the settings for nonexistent
devices will remain at their default levels.
9. The driver entity calls EFI_IDE_CONTROLLER_INIT_PROTOCOL.NotifyPhase (This,EfiIdeAfterChanne-
lEnumeration ,Channel).
10. Install EFI_BLOCK_IO_PROTOCOL on that device handle.
V-7.3 Code Definitions
ThissectioncontainsthebasicdefinitionsoftheIDEControllerInitializationProtocol. TheIDEControllerInitializa-
tion Protocol
following protocol is defined in this section:
V-7.3.1 EFI_IDE_CONTROLLER_INIT_PROTOCOL
EFI_IDE_CONTROLLER_ENUM_PHASE
EFI_IDENTIFY_DATA
EFI_ATA_IDENTIFY_DATA
EFI_ATAPI_IDENTIFY_DATA
EFI_ATA_COLLECTIVE_MODE
EFI_ATA_MODE
EFI_ATA_EXTENDED_MODE
EFI_ATA_EXT_TRANSFER_PROTOCOL
V-7.3.2 EFI_IDE_CONTROLLER_INIT_PROTOCOL
Summary
Provides the basic interfaces to abstract an IDE controller.
GUID
#define EFI_IDE_CONTROLLER_INIT_PROTOCOL_GUID \\
{ 0xa1e37052, 0x80d9, 0x4e65, 0xa3, 0x17, 0x3e, 0x9a, \\
0x55, 0xc4, 0x3e, 0xc9 }
V-7.3. Code Definitions V-38UEFI Platform Initialization Specification, Release 1.8
typedef struct \_EFI_IDE_CONTROLLER_INIT_PROTOCOL {
EFI_IDE_CONTROLLER_GET_CHANNEL_INFO *GetChannelInfo* ;
EFI_IDE_CONTROLLER_NOTIFY_PHASE *NotifyPhase* ;
EFI_IDE_CONTROLLER_SUBMIT_DATA *SubmitData* ;
EFI_IDE_CONTROLLER_DISQUALIFY_MODE *DisqualifyMode* ;
EFI_IDE_CONTROLLER_CALCULATE_MODE *CalculateMode* ;
EFI_IDE_CONTROLLER_SET_TIMING *SetTiming* ;
BOOLEAN *EnumAll* ;
UINT8 *ChannelCount* ;
} EFI_IDE_CONTROLLER_INIT_PROTOCOL;
GetChannelInfo
Returns the information about a specific channel. See the GetChannelInfo() function description.
NotifyPhase
The notification that the driver entity is about to enter the specified phase during the enumeration process. See
theNotifyPhase() function description.
SubmitData
Submits the Drive Identify data that was returned by the device. See the SubmitData() function description.
DisqualifyMode
Submits information about modes that should be disqualified. The specified IDE device does not support these
modes and these modes should not be returned by CalculateMode . See the DisqualifyMode() function descrip-
tion.
CalculateMode
Calculates and returns the optimum mode for a particular IDE device. See the CalculateMode() function de-
SetTiming
Programs the IDE controller hardware to the default timing or per the modes that were returned by the last call
toCalculateMode( ). See the SetTiming() function description.
EnumAll
Set toTRUEif the enumeration group includes all the channels that are produced by this controller. FALSEif
an enumeration group consists of only one channel.
ChannelCount
The number of channels that are produced by this controller. Parallel ATA (PATA) controllers can support up
to two channels. Advanced Host Controller Interface (AHCI) Serial ATA (SATA) controllers can support up to
32channels,eachofwhichcanhaveuptoonedevice. Inthepresenceofamultiplier,eachchannelcanhave15
devices.
TheEFI_IDE_CONTROLLER_INIT_PROTOCOL provides the chipset-specific information to the driver entity. This
protocol is mandatory for IDE controllers if the IDE devices behind the controller are to be enumerated by a driver
entity.
There can only be one instance of EFI_IDE_CONTROLLER_INIT_PROTOCOL for each IDE controller in a system.
It is installed on the handle that corresponds to the IDE controller. A driver entity that wishes to manage an IDE bus
and possibly IDE devices in a system will have to retrieve the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance
that is associated with the controller to be managed.
A device handle for an IDE controller must contain an EFI_DEVICE_PATH_PROTOCOL .

devices.
entity.
V-7.3. Code Definitions V-39UEFI Platform Initialization Specification, Release 1.8
V-7.3.3 EFI_IDE_CONTROLLER_INIT_PROTOCOL.GetChannelInfo()
Summary
Returns the information about the specified IDE channel.
Prototype
typedef
(EFIAPI \*EFI_IDE_CONTROLLER_GET_CHANNEL_INFO) (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL \* *This* ,
IN UINT8 *Channel* ,
OUT BOOLEAN \* *Enabled* ,
OUT UINT8 \* *MaxDevices*
);
This
Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
Channel
Zero-based channel number.
Enabled
TRUEif this channel is enabled. Disabled channels are not scanned to see if any devices are present.
MaxDevices
The maximum number of IDE devices that the bus driver can expect on this channel. For the ATA/ATAPI
specification, version 6, this number will either be 1 or 2. For Serial ATA (SATA) configurations with a port
multiplier, this number can be as large as 15.
ThisfunctioncanbeusedtoobtaininformationaboutaparticularIDEchannel. Thedriverentityusesthisinformation
during the enumeration process.
IfEnabledissettoFALSE,thedriverentitywillnotscanthechannel. Notethatitwillnotpreventanoperatingsystem
driver from scanning the channel.
For most of today’s controllers, MaxDevices will either be 1 or 2. For SATA controllers, this value will always be
1. SATA configurations can contain SATA port multipliers. SATA port multipliers behave like SATA bridges and
can support up to 16 devices on the other side. If an SATA port out of the IDE controller is connected to a port
multiplier, MaxDevices will be set to the number of SATA devices that the port multiplier supports. Because today’s
portmultiplierssupportupto15SATAdevices,thisnumbercanbeaslargeas15. Thedriverentityisrequiredtoscan
for the presence of port multipliers behind an SATA controller and enumerate up to MaxDevices number of devices
behind the port multiplier.
In this context, the devices behind a port multiplier constitute a channel.
EFI_SUCCESS Information was returned without any errors
EFI_INVALID_PARAMETER Channel is invalid Channel ChannelCount
V-7.3. Code Definitions V-40UEFI Platform Initialization Specification, Release 1.8
V-7.3.4 EFI_IDE_CONTROLLER_INIT_PROTOCOL.NotifyPhase()
Summary
ThenotificationsfromthedriverentitythatitisabouttoenteracertainphaseoftheIDEchannelenumerationprocess.
Prototype
typedef
(EFIAPI \*EFI_IDE_CONTROLLER_NOTIFY_PHASE) (
IN EFI_IDE_CONTROLLER_ENUM_PHASE *Phase* ,
IN UINT8 *Channel*
);
This
Phase
The phase during enumeration. Type EFI_IDE_CONTROLLER_ENUM_PHASE is defined in “Related Defini-
Channel
ThisfunctioncanbeusedtonotifytheIDEcontrollerdrivertoperformspecificactions,includinganychipset-specific
initialization,sothatthechipsetisreadytoenterthenextphase. Sevennotificationpointsaredefinedatthistime. See
“Related Definitions” below for the definition of various notification points and Sample Implementation for a Simple
PCI IDE Controller in the Design Discussion chapter for usage.
More synchronization points may be added as required in the future.
// EFI_IDE_CONTROLLER_ENUM_PHASE
EfiIdeBeforeChannelEnumeration,
EfiIdeAfterChannelEnumeration,
EfiIdeBeforeChannelReset,
EfiIdeAfterChannelReset,
EfiIdeBusBeforeDevicePresenceDetection,
EfiIdeBusAfterDevicePresenceDetection,
EfiIdeResetMode,
EfiIdeBusPhaseMaximum
} EFI_IDE_CONTROLLER_ENUM_PHASE;
V-7.3. Code Definitions V-41UEFI Platform Initialization Specification, Release 1.8
Table7.2: FielddescriptiondforEFI_IDE_CONTROLLER_ENUM_PHASE
EfiIdeBeforeChannelEnumeration The driver entity is about to begin enumerating the devices
behind the specified channel This notification can be used to
perform any chipset specific programming
EfiIdeAfterChannelEnumeration The driver entity has completed enumerating the devices behind
the specified channel This notification can be used to perform any
chipset specific programming
EfiIdeBeforeChannelReset The driver entity is about to reset the devices behind the specified
channelThisnotificationcanbeusedtoperformanychipsetspecific
programming
EfiIdeAfterChannelReset The driver entity has completed resetting the devices behind the
specified channel This notification can be used to perform any
EfiIde BusBeforeDevicePresenceDetection The driver entity is about to detect the presence of devices behind
the specified channel This notification can be used to set up the bus
signals to default levels or for implementing predelays
EfiId eBusAfterDevicePresenceDetection The driver entity is done with detecting the presence of devices be-
hind the specified channel This notification can be used to perform
any chipset specific programming
EfiIdeResetMode TheIDEbusisrequestingtheIDEcontrollerdrivertoreprogramthe
IDE controller hardware and thereby reset all the mode and timing
settings to default settings
EFI_SUCCESS The notification was accepted without anyerrors.
EFI_UNSUPPORTED Phase is not supported.
EFI_INVALID_PARAMETER Channel is invalid (Channel >=ChannelCount).
EFI_NOT_READY Thisphasecannotbeenteredatthistime;forexample,anattemptwas
made to enter aPhase without having entered one or moreprevious
Phase.
V-7.3.5 EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
Summary
Submits the device information to the IDE controller driver.
Prototype
typedef
(EFIAPI \*EFI_IDE_CONTROLLER_SUBMIT_DATA) (
IN UINT8 *Device* ,
IN EFI_IDENTIFY_DATA \* *IdentifyData*
);
This
V-7.3. Code Definitions V-42UEFI Platform Initialization Specification, Release 1.8
Channel
Device
Zero-based device number on the Channel.
IdentifyData
The device’s response to the ATA IDENTIFY_DEVICE command. Type EFI_IDENTIFY_DATA is defined in
// EFI_IDENTIFY_DATA
EFI_ATA_IDENTIFY_DATA *AtaData* ;
EFI_ATAPI_IDENTIFY_DATA *AtapiData* ;
} EFI_IDENTIFY_DATA;
#define EFI_ATAPI_DEVICE_IDENTIFY_DATA 0x8000
AtaData
The data that is returned by an ATA device upon successful completion of the ATA IDENTIFY_DEVICE
command. The IDENTIFY_DEVICE command is defined in the ATA/ATAPI specification. Type
EFI_ATA_IDENTIFY_DATA is defined below.
AtapiData
The data that is returned by an ATAPI device upon successful completion of the ATA IDEN-
TIFY_PACKET_DEVICE command. The IDENTIFY_PACKET_DEVICE command is defined in the
ATA/ATAPI specification. Type EFI_ATAPI_IDENTIFY_DATA is defined below.
Table 7.3: EFI_ATAPI_IDENTIFY_DATA Definition .
EFI_ATAPI_DEVICE_IDENTIFY_DATA This flag indicates whether the IDENTIFY data is a response
from an ATA device EFI_ATA_IDENTIFY_DATA or response
from an ATAPI device EFI_ATAPI_IDENTIFY_DATA Accord-
ing to the ATA ATAPI specification EFI_IDENTIFY_DATA is for
an ATA device if bit 15 of the Config field is zero The Con-
fig field is common to both EFI_ATA_IDENTIFY_DATA and
// EFI_ATA_IDENTIFY_DATA
//
// This structure definition is notpart of the protocol
// definition because the ATA/ATAPI Specification controls
// the definition of all the fields. The ATA/ATAPI
// Specification can obsolete old fields orredefine existing
// fields. This definition isprovided here forreference only.
//
///
V-7.3. Code Definitions V-43UEFI Platform Initialization Specification, Release 1.8
/// EFI_ATA_IDENTIFY_DATA isstrictly complied withATA/ATAPI-8 Spec
///
UINT16 config; ///< General Configuration
UINT16 obsolete_1;
UINT16 specific_config; ///< Specific Configuration
UINT16 obsolete_3;
UINT16 retired_4_5[2];
UINT16 obsolete_6;
UINT16 cfa_reserved_7_8[2];
UINT16 retired_9;
CHAR8 SerialNo[20]; ///< word 10~19
UINT16 retired_20_21[2];
UINT16 obsolete_22;
CHAR8 FirmwareVer[8]; ///< word 23~26
CHAR8 ModelName[40]; ///< word 27~46
UINT16 multi_sector_cmd_max_sct_cnt;
UINT16 trusted_computing_support;
UINT16 capabilities_49;
UINT16 capabilities_50;
UINT16 obsolete_51_52[2];
UINT16 field_validity;
UINT16 obsolete_54_58[5];
UINT16 multi_sector_setting;
UINT16 user_addressable_sectors_lo;
UINT16 user_addressable_sectors_hi;
UINT16 obsolete_62;
UINT16 multi_word_dma_mode;
UINT16 advanced_pio_modes;
UINT16 min_multi_word_dma_cycle_time;
UINT16 rec_multi_word_dma_cycle_time;
UINT16 min_pio_cycle_time_without_flow_control;
UINT16 min_pio_cycle_time_with_flow_control;
UINT16 reserved_69_74[6];
UINT16 queue_depth;

///
UINT16 reserved_76_79[4]; ///< reserved forSerial ATA
UINT16 major_version_no;
UINT16 minor_version_no;
UINT16 command_set_supported_82; ///< word 82
UINT16 command_set_supported_83; ///< word 83
UINT16 command_set_feature_extn; ///< word 84
UINT16 command_set_feature_enb_85; ///< word 85
UINT16 command_set_feature_enb_86; ///< word 86
UINT16 command_set_feature_default; ///< word 87
UINT16 ultra_dma_mode; ///< word 88
UINT16 time_for_security_erase_unit;
UINT16 time_for_enhanced_security_erase_unit;
UINT16 advanced_power_management_level;
UINT16 master_password_identifier;
UINT16 hardware_configuration_test_result;
UINT16 acoustic_management_value;
UINT16 stream_minimum_request_size;
V-7.3. Code Definitions V-44UEFI Platform Initialization Specification, Release 1.8
UINT16 streaming_transfer_time_for_dma;
UINT16 streaming_access_latency_for_dma_and_pio;
UINT16 streaming_performance_granularity[2];///< word 98~99
UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103
UINT16 streaming_transfer_time_for_pio;
UINT16 reserved_105;
UINT16 phy_logic_sector_support; ///< word 106
UINT16 interseek_delay_for_iso7779;
UINT16 world_wide_name[4]; ///< word 108~111
UINT16 reserved_for_128bit_wwn_112_115[4];
UINT16 reserved_for_technical_report;
UINT16 logic_sector_size_lo; ///< word 117
UINT16 logic_sector_size_hi; ///< word 118
UINT16 features_and_command_sets_supported_ext; ///< word 119
UINT16 features_and_command_sets_enabled_ext; ///< word 120
UINT16 reserved_121_126[8];
UINT16 obsolete_127;
UINT16 security_status; ///< word 128
UINT16 vendor_specific_129_159[31];
UINT16 cfa_power_mode; ///< word 160
UINT16 reserved_for_compactflash_161_175[15];
CHAR8 media_serial_number[60]; ///< word 176~205
UINT16 sct_command_transport; ///< word 206
UINT16 reserved_207_208[2];
UINT16 alignment_logic_in_phy_blocks; ///< word 209
UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211
UINT16 verify_sector_count_mode2[2];
UINT16 nv_cache_capabilities;
UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215
UINT16 nv_cache_size_in_logical_block_msw; ///< word 216
UINT16 nv_cache_read_speed;
UINT16 nv_cache_write_speed;
UINT16 nv_cache_options; ///< word 219
UINT16 write_read_verify_mode; ///< word 220
UINT16 reserved_221;
UINT16 transport_major_revision_number;
UINT16 transport_minor_revision_number;
UINT16 reserved_224_233[10];
UINT16 min_number_per_download_microcode_mode3; ///< word 234
UINT16 max_number_per_download_microcode_mode3; ///< word 235
UINT16 reserved_236_254[19];
UINT16 integrity_word;
} EFI_ATA_IDENTIFY_DATA;
// EFI_ATAPI_IDENTIFY_DATA
///
/// EFI_ATAPI_IDENTIFY_DATA isstrictly complied with
ATA/ATAPI-8 Spec
V-7.3. Code Definitions V-45UEFI Platform Initialization Specification, Release 1.8
///
UINT16 reserved_1;
UINT16 reserved_3_9[7];
UINT16 reserved_20_22[3];
UINT16 reserved_47_48[2];
UINT16 obsolete_51;
UINT16 reserved_52;
UINT16 field_validity; ///< word 53
UINT16 reserved_54_61[8];
UINT16 dma_dir;
UINT16 multi_word_dma_mode; ///< word 63
UINT16 advanced_pio_modes; ///< word 64
UINT16 reserved_69_70[2];
UINT16 obsolete_71_72[2];
UINT16 reserved_73_74[2];
UINT16 reserved_76_79[4];
UINT16 major_version_no; ///< word 80
UINT16 minor_version_no; ///< word 81
UINT16 cmd_set_support_82;
UINT16 cmd_set_support_83;
UINT16 cmd_feature_support;
UINT16 cmd_feature_enable_85;
UINT16 cmd_feature_enable_86;
UINT16 cmd_feature_default;
UINT16 ultra_dma_select;
UINT16 time_required_for_sec_erase; ///< word 89
UINT16 time_required_for_enhanced_sec_erase; ///< word 90
UINT16 reserved_91;
UINT16 master_pwd_revison_code;
UINT16 hardware_reset_result; ///< word 93
UINT16 current_auto_acoustic_mgmt_value;
UINT16 reserved_95_107[13];
UINT16 reserved_116_124[9];
UINT16 atapi_byte_count_0_behavior; ///< word 125
UINT16 obsolete_126;
UINT16 removable_media_status_notification_support;
UINT16 security_status;
V-7.3. Code Definitions V-46UEFI Platform Initialization Specification, Release 1.8
UINT16 reserved_129_160[32];
UINT16 cfa_reserved_161_175[15];
UINT16 reserved_176_254[79];
} EFI_ATAPI_IDENTIFY_DATA;
This function is used by the driver entity to pass detailed information about a particular device to the IDE controller
driver. The driver entity obtains this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. Iden-
tifyDatais the pointer to the response data buffer. The IdentifyData buffer is owned by the driver entity, and the
IDE controller driver must make a local copy of the entire buffer or parts of the buffer as needed. The original
IdentifyData buffer pointer may not be valid when EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or
EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point.
TheIDE controllerdrivermayconsult variousfieldsof EFI_IDENTIFY_DATA tocompute theoptimummodefor the
device. These fields are not limited to the timing information. For example, an implementation of the IDE controller
driver may examine the vendor and type/mode field to match known bad drives.
The driver entity may submit drive information in any order, as long as it submits information for all the devices
belonging to the enumeration group before CalculateMode() is called for any device in that enumeration group. If a
device is absent, SubmitData() should be called with IdentifyData set toNULL. The IDE controller driver may not
have any other mechanism to know whether a device is present or not. Therefore, setting IdentifyData toNULLdoes
not constitute an error condition. SubmitData() can be called only once for a given ( Channel,Device) pair.
EFI_SUCCESS The information was accepted without any errors
EFI_INVALID_PARAMETER Channelis invalid ( Channel >= ChannelCount )
EFI_INAVLID_PARAMETER Deviceis invalid.
V-7.3.6 EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode()
Summary
Disqualifies specific modes for an IDE device.
Prototype
typedef
(EFIAPI \*EFI_IDE_CONTROLLER_DISQUALIFY_MODE) (
IN EFI_ATA_COLLECTIVE_MODE \* *BadModes*
);
This
V-7.3. Code Definitions V-47UEFI Platform Initialization Specification, Release 1.8
Channel
Device
BadModes
The modes that the device does not support and that should be disqualified. Type
EFI_ATA_COLLECTIVE_MODE is defined in “Related Definitions” below.
Definitions
This function allows the driver entity or other drivers (such as platform drivers) to reject certain timing modes and
request the IDE controller driver to recalculate modes. This function allows the driver entity and the IDE controller
driver to negotiate the timings on a per-device basis. This function is useful in the case of drives that lie about their
capabilities. An example is when the IDE device fails to accept the timing modes that are calculated by the IDE
controller driver based on the response to the Identify Drive command.
IfthedriverentitydoesnotwanttolimittheATAtimingmodesandleavethatdecisiontotheIDEcontrollerdriver,it
can either not call this function for the given device or call this function and set the Validflag toFALSEfor all modes
that are listed in EFI_ATA_COLLECTIVE_MODE .
The driver entity may disqualify modes for a device in any order and any number of times.
This function can be called multiple times to invalidate multiple modes of the same type (e.g., Programmed In-
put/Output [PIO] modes 3 and 4). See the ATA/ATAPI specification for more information on PIO modes.
For Serial ATA (SATA) controllers, this member function can be used to disqualify a higher transfer rate mode on
a given channel. For example, a platform driver may inform the IDE controller driver to not use second-generation
(Gen2) speeds for a certain SATA drive.
//*****************************************************\*
// EFI_ATA_COLLECTIVE_MODE
EFI_ATA_MODE *PioMode* ;
EFI_ATA_MODE *SingleWordDmaMode* ;

EFI_ATA_MODE *MultiWordDmaMode* ;
EFI_ATA_MODE *UdmaMode* ;
UINT32 *ExtModeCount* ;
EFI_ATA_EXTENDED_MODE *ExtMode* [1];
} EFI_ATA_COLLECTIVE_MODE;
PioMode
This field specifies the PIO mode. PIO modes are defined in the ATA/ATAPI specification. The ATA/ATAPI
specification defines the enumeration. In other words, a value of 1 in this field means PIO mode 1. The actual
meaningofPIOmode1isgovernedbytheATA/ATAPIspecification. TypeEFI_ATA_MODEisdefinedbelow.
SingleWordDmaMode
ThisfieldspecifiesthesinglewordDMAmode. SinglewordDMAmodesaredefinedintheATA/ATAPIspec-
ification, versions 1 and 2. Single word DMA support was obsoleted in the ATA/ATAPI specification, version
3; therefore, most devices and controllers will not support this transfer mode. The ATA/ATAPI specification
defines the enumeration. In other words, a value of 1 in this field means single word DMA mode 1. The actual
meaning of single word DMA mode 1 is governed by the ATA/ATAPI specification.
MultiWordDmaMode
This field specifies the multiword DMA mode. Various multiword DMA modes are defined in the ATA/ATAPI
V-7.3. Code Definitions V-48UEFI Platform Initialization Specification, Release 1.8
specification. Avalueof1inthisfieldmeansmultiwordDMAmode1. TheactualmeaningofmultiwordDMA
mode 1 is governed by the ATA/ATAPI specification.
UdmaMode
ThisfieldspecifiestheultraDMA(UDMA)mode. UDMAmodesaredefinedintheATA/ATAPIspecification.
A value of 1 in this field means UDMA mode 1. The actual meaning of UDMA mode 1 is governed by the
ATA/ATAPI specification.
ExtModeCount
The number of extended-mode bitmap entries. Extended modes describe transfer protocols beyond PIO, single
word DMA, multiword DMA, and UDMA. This field can be zero and provides extensibility.
ExtMode
ExtModeCount number of entries. Each entry represents a transfer protocol other than the ones defined above
(i.e.,PIO,singlewordDMA,multiwordDMA,andUDMA).Thisfieldisdefinedforextensibility. Atthistime,
onlyoneextendedtransferprotocolisdefinedtocoverSATAtransfers. Type EFI_ATA_EXTENDED_MODE is
// EFI_ATA_MODE
BOOLEAN *Valid* ;
UINT32 *Mode* ;
} EFI_ATA_MODE;
Valid
TRUEifModeis valid.
Mode
The actual ATA mode. This field is not a bit map.
// EFI_ATA_EXTENDED_MODE
EFI_ATA_EXT_TRANSFER_PROTOCOL *TransferProtocol* ;
} EFI_ATA_EXTENDED_MODE;
TransferProtocol
An enumeration defining various transfer protocols other than the protocols that exist at the time this specifi-
cation was developed (i.e., PIO, single word DMA, multiword DMA, and UDMA). Each transfer protocol is
associated with a mode. The various transfer protocols are defined by the ATA/ATAPI specification. This enu-
meration makes the interface extensible because we can support new transport protocols beyond UDMA. Type
EFI_ATA_EXT_TRANSFER_PROTOCOL is defined below.
Mode
The mode for operating the transfer protocol that is identified by TransferProtocol .
// EFI_ATA_EXT_TRANSFER_PROTOCOL
//
// This extended mode describes the SATA physical protocol.
// SATA physical layers can operate at different speeds.
V-7.3. Code Definitions V-49UEFI Platform Initialization Specification, Release 1.8
// These speeds are defined below. Various PATA protocols
//andassociated modes are notapplicable to SATA devices.
//
EfiAtaSataTransferProtocol
} EFI_ATA_EXT_TRANSFER_PROTOCOL;
#define EFI_SATA_AUTO_SPEED 0
#define EFI_SATA_GEN1_SPEED 1
#define EFI_SATA_GEN2_SPEED 2
Table7.4: EFI_ATA_EXT_TRANSFER_PROTOCOLfielddescriptions
EFI_SATA_AUTO_SPEED Automatically detects the optimum SATA speed.
EFI_SATA_GEN1_SPEED Indicates a first-generation (Gen1) SATA speed.
EFI_SATA_GEN2_SPEED Indicates a second-generation (Gen2) SATA speed.
EFI_SUCCESS The modes were accepted without any errors.
EFI_INVALID_PARAMETER Channelis invalid ( Channel >= ChannelCount ).
EFI_INVALID_PARAMETER Deviceis invalid.
EFI_INVALID_PARAMETER IdentifyData isNULL.
V-7.3.7 EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode()
Summary
Returns the information about the optimum modes for the specified IDE device.
Prototype
typedef
(EFIAPI \*EFI_IDE_CONTROLLER_CALCULATE_MODES) (
OUT EFI_ATA_COLLECTIVE_MODE \*\* *SupportedModes*
);
This
Channel
Device
V-7.3. Code Definitions V-50UEFI Platform Initialization Specification, Release 1.8
SupportedModes
The optimum modes for the device. Type EFI_ATA_COLLECTIVE_MODE is defined in
EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() .
This function is used by the driver entity to obtain the optimum ATA modes for a specific device. The IDE controller
driver takes into account the following while calculating the mode:
•“TheIdentifyData inputs toEFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
•“TheBadModes inputs toEFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode()
Thedriverentityisrequiredtocall SubmitData() forallthedevicesthatbelongtoanenumerationgroupbeforecalling
CalculateMode() for any device in the same group.
TheIDEcontrollerdriverwillusecontroller-andpossiblyplatform-specificalgorithmstoarriveat SupportedModes .
The IDE controller may base its decision on user preferences and other considerations as well. This function may be
calledmultipletimesbecausethedriverentitymayrenegotiatethemodewiththeIDEcontrollerdriverusing Disqual-
ifyMode() .
The driver entity may collect timing information for various devices in any order. The driver entity is responsible for
making sure that all the dependencies are satisfied; for example, the SupportedModes information for device A that
was previously returned may become stale after a call to DisqualifyMode() for device B.
Thebuffer SupportedModes isallocatedbythecalleebecausethecallerdoesnotnecessarilyknowthesizeofthebuffer.
ThetypeEFI_ATA_COLLECTIVE_MODE isdefinedinawaythatallowsforfutureextensibilityandcanbeofvariable
length. This memory pool should be deallocated by the caller when it is no longer necessary.
The IDE controller driver for a Serial ATA (SATA) controller can use this member function to force a lower speed
(first-generation [Gen1] speeds on a second-generation [Gen2]-capable hardware). The IDE controller driver can also
allow the driver entity to stay with the speed that has been negotiated by the physical layer.
EFI_SUCCESS SupportedModes was returned
EFI_INVALID_PARAMETER Channelis invalid ( Channel ChannelCount )
EFI_INVALID_PARAMETER Deviceis invalid
EFI_INVALID_PARAMETER SupportedModes isNULL
EFI_NOT_READY Modes cannot be calculated due to a lack of data This error may
happen if SubmitData() andDisqualifyData() were not called for at
least one drive in the same enumeration group
V-7.3.8 EFI_IDE_CONTROLLER_INIT_PROTOCOL.SetTiming()
Summary
Commands the IDE controller driver to program the IDE controller hardware so that the specified device can operate
at the specified mode.
Prototype
typedef
(EFIAPI \*EFI_IDE_CONTROLLER_SET_TIMING) (
V-7.3. Code Definitions V-51UEFI Platform Initialization Specification, Release 1.8
IN EFI_ATA_COLLECTIVE_MODE \* *Modes*
);
This
Channel
Device
Modes
The modes to set. Type EFI_ATA_COLLECTIVE_MODE is defined in
ThisfunctionisusedbythedriverentitytoinstructtheIDEcontrollerdrivertoprogramtheIDEcontrollerhardwareto
thespecifiedmodes. Thisfunctioncanbecalledonlyonceforaparticulardevice. ForaSerialATA(SATA)Advanced
Host Controller Interface (AHCI) controller, no controller-specific programming may be required.
EFI_SUCCESS The command was accepted without any errors
EFI_NOT_READY Modescannot be set at this time due to lack of data
EFI_DEVICE_ERROR ModescannotbesetduetohardwarefailureThedriverentityshould
not use this device
V-7.3.9 IDE Disk Information Protocol
This section contains the basic definitions of the IDE Disk Information Protocol.
V-7.3.10 EFI_DISK_INFO_PROTOCOL
Summary
Provides the basic interfaces to abstract platform information regarding an IDE controller.
GUID

Summary
GUID
#define EFI_DISK_INFO_PROTOCOL_GUID \\
{ 0xd432a67f, 0x14dc, 0x484b, 0xb3, 0xbb, 0x3f, 0x02, 0x91,\\
0x84, 0x93, 0x27 }
typedef struct \_EFI_DISK_INFO_PROTOCOL {
EFI_GUID *Interface* ;
EFI_DISK_INFO_INQUIRY *Inquiry* ;
V-7.3. Code Definitions V-52UEFI Platform Initialization Specification, Release 1.8
EFI_DISK_INFO_IDENTIFY *Identify* ;
EFI_DISK_INFO_SENSE_DATA *SenseData* ;
EFI_DISK_INFO_WHICH_IDE *WhichIde* ;
} EFI_DISK_INFO_PROTOCOL;
Interface
A GUID that defines the format of buffers for the other member functions of this protocol.
Inquiry
Return the results of the Inquiry command to a drive in InquiryData . Data format of Inquirydata is defined by
the Interface GUID.
Identify
Returntheresultsofthe Identifycommandtoadrivein IdentifyData . Dataformatof Identifydataisdefinedby
SenseData
ReturntheresultsoftheRequestSensecommandtoadrivein SenseData . DataformatofSensedataisdefined
by the Interface GUID.
WhichIde
Specific controller.
TheEFI_DISK_INFO_PROTOCOL provides controller specific information.
There can only various instances of EFI_DISK_INFO_PROTOCOL for different interface types.
V-7.3.11 EFI_DISK_INFO_PROTOCOL.Interface
Summary
GUID of the type of interfaces
#define EFI_DISK_INFO_IDE_INTERFACE_GUID \\
{ \\
0x5e948fe3, 0x26d3, 0x42b5, 0xaf, 0x17, 0x61, 0x2, \\
0x87, 0x18, 0x8d, 0xec \\
}
#define EFI_DISK_INFO_SCSI_INTERFACE_GUID \\
{ \\
0x8f74baa, 0xea36, 0x41d9, 0x95, 0x21, 0x21, 0xa7, \\
0xf, 0x87, 0x80, 0xbc \\
}
#define EFI_DISK_INFO_USB_INTERFACE_GUID \\
{ \\
0xcb871572, 0xc11a, 0x47b5, 0xb4, 0x92, 0x67, 0x5e, \\
0xaf, 0xa7, 0x77, 0x27 \\
}
V-7.3. Code Definitions V-53UEFI Platform Initialization Specification, Release 1.8
#define EFI_DISK_INFO_AHCI_INTERFACE_GUID \\
{ \\
0x9e498932, 0x4abc, 0x45af, 0xa3, 0x4d, 0x2, 0x47, \\
0x78, 0x7b, 0xe7, 0xc6 \\
}
#define EFI_DISK_INFO_NVME_INTERFACE_GUID \\
{ \\
0x3ab14680, 0x5d3f, 0x4a4d, 0xbc, 0xdc, 0xcc, 0x38, \\
0x0, 0x18, 0xc7, 0xf7 \\
}
#define EFI_DISK_INFO_UFS_INTERFACE_GUID \\
{ \\
0x4b3029cc, 0x6b98, 0x47fb, 0xbc, 0x96, 0x76, 0xdc, \\
0xb8, 0x4, 0x41, 0xf0 \\
}
#define EFI_DISK_INFO_SD_MMC_INTERFACE_GUID \\
{ \\
{0x8deec992, 0xd39c, 0x4a5c, { 0xab, 0x6b, 0x98, 0x6e, \\
0x14, 0x24, 0x2b, 0x9d } \\
}
The data format of InquiryData ofEFI_DISK_INFO_PROTOCOL.Inquiry() is the card CID register content defined
at SD physical layer specification or MMC/eMMC electrical standard.
The type of interface being described.
V-7.3.12 EFI_DISK_INFO_PROTOCOL.Inquiry()
Summary
Provides inquiry information for the controller type.
Prototype
typedef
(EFIAPI \*EFI_DISK_INFO_INQUIRY) (
IN EFI_DISK_INFO_PROTOCOL \* *This* ,
IN OUT VOID \* *InquiryData* ,
IN OUT UINT32 \* *InquiryDataSize*
);
This
Pointer to the EFI_DISK_INFO_PROTOCOL instance.
InquiryData
Pointer to a buffer for the inquiry data.
V-7.3. Code Definitions V-54UEFI Platform Initialization Specification, Release 1.8
InquiryDataSize
Pointer to the value for the inquiry data size.
This function is used by the driver entity to get inquiry data. Data format of Identifydata is defined by the Interface
GUID.
EFI_SUCCESS The command was accepted without any errors.
EFI_NOT_FOUND Device does not support this data class
EFI_DEVICE_ERROR Error reading InquiryData from device
EFI_BUFFER_TOO_SMALL InquiryDataSize not big enough
V-7.3.13 EFI_DISK_INFO_PROTOCOL.Identify()
Summary
Provides identify information for the controller type.
Prototype
typedef
(EFIAPI \*EFI_DISK_INFO_IDENTIFY) (
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *IdentifyData,
IN OUT UINT32 *IdentifyDataSize
);
This
Pointer to a buffer for the identify data.
IdentifyDataSize
Pointer to the value for the identify data size.
Descripton
This function is used by the driver entity to get identify data. Data format of Identify data is defined by the Interface
GUID.
EFI_DEVICE_ERROR Error reading IdentifyData from device
EFI_BUFFER_TOO_SMALL IdentifyDataSize not big enough
V-7.3. Code Definitions V-55UEFI Platform Initialization Specification, Release 1.8
V-7.3.14 EFI_DISK_INFO_PROTOCOL.SenseData()
Summary
Provides sense data information for the controller type.
Prototype
typedef
(EFIAPI \*EFI_DISK_INFO_SENSE_DATA) (
IN OUT VOID \* *SenseData* ,
IN OUT UINT32 \* *SenseDataSize*
OUT UINT8 \* *SenseDataNumber*
);
This
SenseData
Pointer to the SenseData .
SenseDataSize
Size ofSenseData in bytes.
SenseDataNumber
Pointer to the value for the sense data size.
This function is used by the driver entity to get sense data. Data format of Identifydata is defined by the Interface
GUID.
EFI_DEVICE_ERROR Error reading SenseData from device
EFI_BUFFER_TOO_SMALL SenseDataSize not big enough
V-7.3.15 EFI_DISK_INFO_PROTOCOL.WhichIde()
Summary
Provides IDE channel and device information for the interface
Prototype
typedef
(EFIAPI \*EFI_DISK_INFO_WHICH_IDE) (
OUT UINT32 \* *IdeChannel* ,
OUT UINT32 \* *IdeDevice*
);
V-7.3. Code Definitions V-56UEFI Platform Initialization Specification, Release 1.8
This
IdeChannel
Pointer to the Ide Channel number. Primary or secondary.This should also return the port.
IdeDevice
PointertotheIdeDevicenumber. Masterorslave.Thisshouldalsoreturntheport-multiplierportforAHCI.The
format will be the same as for port above.
This function is used by the driver entity to get controller information.
EFI_SUCCESS IdeChannel and IdeDevice are valid
EFI_UNSUPPORTED This is not an IDE Device
V-7.3. Code Definitions V-57CHAPTER
EIGHT
S3 RESUME
V-8.1 S3 Overview
ThisspecificationdefinesthecorecodeandservicesthatarerequiredforanimplementationoftheS3resumebootpath
in the PI. The S3 resume boot path is a special boot path that causes the system to take actions different from those in
the normal boot path. In this special path, the system derives pre-saved data about the platform’s configuration from
persistent storage and configures the platform before jumping to the operating system’s waking vector.
•“Describes the basic components of the S3 resume boot path, how it relates to a normal boot path, and how it
interacts with other PI phases and code
•“ProvidescodedefinitionsfortheS3-relatedprotocolsandPPIsthatarearchitecturallyrequiredbythe PISpec-
V-8.2 Goals
This PI S3 resume boot path design has the following goals:
Extensibility:
The PI S3 resume boot path should easily adapt to different platforms, such as Itanium ®-based platforms those
basedon32-bitIntel ®architecture(IA-32),andx64platformsbyreplacingonlyafewplatform-specificmodules.
High performance:
The performance of the PI S3 resume boot path is highly visible to end users and must be optimized.
V-8.3 Requirements
All aspects of this PI S3 resume boot path design must comply with the Advanced Configuration and Power Interface
Specification (hereafter referred to as the “ACPI specification”).
The design should emphasize size efficiency, code reuse and maintainability.
V-58UEFI Platform Initialization Specification, Release 1.8
V-8.4 Assumptions
V-8.4.1 Multiple Phases of Platform Initialization
The PI Architecture consists of multiple phases. For example:
•Pre-EFI Initialization (PEI)
•Driver Execution Environment (DXE)
•SMM (System Management Mode)
The PEI phase is responsible for initializing enough of the platform’s resources to enable the execution of the DXE
phase, which is where the majority of platform configuration is performed by different DXE drivers.
Initialization that is done in PEI is not necessarily preserved in DXE. In other words, a DXE driver can override the
configuration settings that were derived from PEI. In light of this fact, the preboot platform state that the S3 resume
bootpathneedstorestoreistheDXEsnapshotoftheplatformstate,ratherthanthePEIsnapshotoftheplatformstate.
V-8.4.2 Process of Platform Initialization
Platform initialization can be viewed as a flow of the following:
•I/O operations
•Memory operations
•Accessing the PCI configuration space
•Acollectionofplatform-specificactionsthatcanbeabstractedbyPre-EFIInitializationModule(PEIM)PEIM-
to-PEIM Interfaces (PPIs)
Theprocessofrestoringhardwaresettingsindifferentplatformsinvolvesdifferentactionsorevendifferentinstruction

sets. These differences, however, can be abstracted behind PEIM PPIs.
V-8.5 Restoring the Platform
The goal of the S3 resume process is to restore the platform to its preboot configuration. However, it is impossible to
restoretheplatforminonlyonestep,withoutgoingthroughallthePIinitializationphases,becausethePIArchitechture
cannot have a priori knowledge of the following:
•Preboot configuration that is introduced by various PEIMs
•Drivers provided by different vendors
Asaresult,thePIArchitechturestillneedstorestoretheplatforminaphasedfashionasitdoesinanormalbootpath.
ThefigurebelowshowsthephasesinanS3resumebootpath. Seethefollowingsubsectionsfordetailsofeachphase.
V-8.4. Assumptions V-59UEFI Platform Initialization Specification, Release 1.8
Fig. 8.1: PI Architecture S3 Resume
V-8.5.1 Phases in the S3 Resume Boot Path
V-8.5.1.1 SEC and the S3 Resume Boot Path
The Security (SEC) phase is the first architectural phase in the PI Architecture. It builds the root of trust for the entire
system. As such, the SEC phase remains intact in the S3 resume boot path.
V-8.5.1.2 PEI
V-8.5.1.2.1 PEI and the S3 Resume Boot Path
The PEI phase initializes the platform with the minimum configuration needed to enable the execution of the DXE
phase. During the S3 resume boot path, the PI Architechture still needs to restore the PEI portion of configuration.
Each PEIM is “boot path aware” in that the PEIM can call the appropriate PEI service to find out what the current
boot path is. This awareness enables the platform to restore more efficiently because the same PEIM can save the
configuration during a normal boot path and take advantage of that configuration in the S3 resume boot path. The
figure below shows how the PEI phase works in a normal boot path and in an S3 resume boot path.
Fig. 8.2: PEI Phase in S3 Resume Boot Path
V-8.5. Restoring the Platform V-60UEFI Platform Initialization Specification, Release 1.8
V-8.5.1.2.2 Saving Configuration Data in PEI
There are different ways to save configuration data, such as the firmware volume variable, for the PEI phase in non-
volatile storage (NVS). One way is to save the data directly in the PEI phase. However, if the PEI phase does not
implementthecapabilitytowritetoafirmwarevolume,aPEIMcanchoosetopasstheconfigurationdatatotheDXE
phaseusingaHand-OffBlock(HOB).ThePEIM’sDXEcounterpartoranotherappropriateDXEcomponentcanthen
save the configuration data. The figure below illustrates this mechanism to save the configuration data. See the PI
Specification for more details on HOBs.
Toachievehigherperformance,itisrecommendedtoimplementthelattermechanismbecausecoderunninginthePEI
phase is more time consuming than code running in the DXE phase. Note that the way to save the configuration data
during the PEI phase is outside the scope of this document.
Fig. 8.3: Configuration Save for PEI Phase
V-8.5.1.3 DXE
V-8.5.1.3.1 DXE and the S3 Resume Boot Path
In the DXE phase during a normal boot path, various DXE drivers collectively bring the platform to the preboot state.
However, bringing DXE into the S3 resume boot path and making a DXE driver boot-path aware is very risky for the
following reasons:
•The DXE phase hosts numerous services, which makes it rather large.
•Loading DXE from flash is very time consuming.
EvenifDXEcouldberelocatedintoNVSduringanormalboot,thelargeamountofmemorythatDXEconsumesand
the complexity of executing the DXE phase do not justify doing so.
V-8.5. Restoring the Platform V-61UEFI Platform Initialization Specification, Release 1.8
Instead, the PI Architechture provides a boot script that lets the S3 resume boot path avoid the DXE phase altogether,
which helps to maximize optimum performance. During a normal boot, DXE drivers record the platform’s configura-
tioninthebootscript,whichissavedinNVS.DuringtheS3resumebootpath,abootscriptengineexecutesthescript,
thereby restoring the configuration.
TheACPIspecificationonlyrequirestheBIOStorestorechipsetandprocessorconfiguration. Thechipsetconfiguration
can be viewed as a series of memory, I/O, and PCI configuration operations, which DXE drivers record in the PI
Architechture boot script. During an S3 resume, a boot script engine executes the boot script to restore the chipset
settings. Processor configuration involves the following:
•“Basic setup for System Management Mode (SMM)
•“Microcode updates
•“Processor-specific initialization
•“Processor cache setting
DXEdriversregisterapointertoafunctioninthebootscripttorestoreprocessorconfiguration. DuringtheS3resume
bootpath,thebootscriptenginecanjumptoexecutetheregisteredcodetorestoreallprocessor-relatedconfigurations.
V-8.5.1.3.2 S3 Resume PPI and DXE IPL PPI
TheDXEInitialProgramLoad(IPL)PPIisarchitecturallythelastPPIthatisexecutedinthePEIphase. Itisalsomade
aware of the exact boot path that the PI Architechture is currently using. It discovers the boot mode and initiates the
process of restoring the pre-boot platform state and jumping to the operating system (OS) waking vector. The DXE
phase is not entered, as it would be during a normal boot.
When resuming from S3, the DXE IPL PEIM will transfer control to the S3 Resume PPI, which is responsible for
restoring the platform configuration and jumping to the waking vector.
V-8.5.1.4 SMM
TheEFI_S3_SMM_SAVE_STATE_PROTOCOL publishes the PI SMM boot script abstractions
In the S3 boot mode the data stored via this protocol is replayed in the order it was stored.
The order of replay is the order either of the S3 Save State Protocol or S3 SMM Save State Protocol Write()functions
were called during the boot process. Insert(),Label(), andCompare() operations are ordered relative other S3 SMM
Save State Protocol Write()operations and the order relative to S3 State Save Write()operations is not defined. Due
to these ordering restrictions it is recommended that the S3 State Save Protocol be used during the DXE phase when
every possible.
TheEFI_S3_SMM_SAVE_STATE_PROTOCOL can be called at runtime and EFI_OUT_OF_RESOURCES may be
returned from a runtime call. It is the responsibility of the platform to ensure enough memory resource exists to save
the system state. It is recommended that runtime calls be minimized by the caller.3
V-8.5. Restoring the Platform V-62UEFI Platform Initialization Specification, Release 1.8
V-8.6 PEI Boot Script Executer PPI
V-8.6.1 EFI_PEI_S3_RESUME2_PPI
Summary
This PPI produces functions to interpret and execute the PI boot script table.
GUID
#define EFI_PEI_S3_RESUME2_PPI_GUID \
{0x6d582dbc, 0xdb85, 0x4514, \
0x8f, 0xcc, 0x5a, 0xdf, 0x62, 0x27, 0xb1,0x47}
typedef struct \_EFI_PEI_S3_RESUME2_PPI {
EFI_PEI_S3_RESUME_PPI_RESTORE_CONFIG2 *S3RestoreConfig2* ;
} EFI_PEI_S3_RESUME2_PPI;
S3RestoreConfig2
Perform S3 resume operation.
This PPI is published by a PEIM and provides for the restoration of the platform’s configuration when resuming from
the ACPI S3 power state. The ability to execute the boot script may depend on the availability of other PPIs. For
example, if the boot script includes an SMBus command, this PEIM looks for the relevant PPI that is able to execute
that command.
V-8.6.2 EFI_PEI_S3_RESUME_PPI.S3RestoreConfig()
Summary
Restores the platform to its pre-boot configuration for an S3 resume and jumps to the OS waking vector.
Prototype
typedef
(EFIAPI \*EFI_PEI_S3_RESUME_PPI_RESTORE_CONFIG) (
IN EFI_PEI_S3_RESUME_PPI *This
);
This
A pointer to this instance of the PEI_S3_RESUME_PPI.
This function will restore the platform to its pre-boot configuration that was pre-stored in the boot script table and
transfer control to OS waking vector.
Upon invocation, this function is responsible for locating the following information before jumping to OS waking
vector:
V-8.6. PEI Boot Script Executer PPI V-63UEFI Platform Initialization Specification, Release 1.8
•ACPI tables
•boot script table
•any other information that it needs
TheS3RestoreConfig() function then executes the pre-stored boot script table and transitions the platform to the pre-
boot state. The boot script is recorded during regular boot using the EFI_S3_SAVE_STATE_PROTOCOL.Write() and
EFI_S3_SMM_SAVE_STATE_PROTOCOL.Write() functions. Finally,thisfunctiontransferscontroltotheOSwaking
vector. IftheOSsupportsonlyareal-modewakingvector,thisfunctionwillswitchfromflatmodetorealmodebefore
jumping to the waking vector.
Ifallplatformpre-bootconfigurationsaresuccessfullyrestoredandallothernecessaryinformationisready,thisfunc-
tion will never return and instead will directly jump to the OS waking vector. If this function returns, it indicates that
the attempt to resume from the ACPI S3 sleep state failed.
EFI_ABORTED Execution of the S3 resume boot script table failed
EFI_NOT_FOUND SomenecessaryinformationthatisusedfortheS3resumebootpath
could not be located
V-8.7 S3 Save State Protocol

ThissectiondefineshowaDXEPImodulecanrecordIOoperationstobeperformedaspartoftheS3resume. Thisis
doneviathe EFI_S3_SAVE_STATE_PROTOCOL andthisallowstheimplementationoftheS3resumebootpathtobe
abstracted from DXE drivers.
V-8.7.1 EFI_S3_SAVE_STATE_PROTOCOL
Summary
Used to store or record various IO operations to be replayed during an S3 resume.
GUID
#define EFI_S3_SAVE_STATE_PROTOCOL_GUID \
{ 0xe857caf6, 0xc046, 0x45dc, { 0xbe, 0x3f, 0xee, 0x7, \
0x65, 0xfb, 0xa8, 0x87 } }
typedef struct _EFI_S3_SAVE_STATE_PROTOCOL {
EFI_S3_SAVE_STATE_WRITE Write;
EFI_S3_SAVE_STATE_INSERT Insert;
EFI_S3_SAVE_STATE_LABEL Label;
EFI_S3_SAVE_STATE_COMPARE Compare;
} EFI_S3_SAVE_STATE_PROTOCOL;
Write
Write an opcode at the end of the boot script table. See the Write()function description.
V-8.7. S3 Save State Protocol V-64UEFI Platform Initialization Specification, Release 1.8
Insert
Write an opcode at the specified position in the boot script table. See the Insert()function description.
Label
Find an existing label in the boot script table or, if not present, create it. See the Label()function description.
Compare
Compare two positions in the boot script table to determine their relative location. See the Compare() function
TheEFI_S3_SAVE_STATE_PROTOCOL publishesthePIbootscriptabstractions. Thisprotocolisnotrequiredforall
platforms.
On an S3 resume boot path the data stored via this protocol is replayed in the order it appears in the boot script table.
V-8.7.2 Save State Write
V-8.7.3 EFI_S3_SAVE_STATE_PROTOCOL.Write()
Summary
Record operations that need to be replayed during an S3 resume.
Prototype
typedef
(EFIAPI \*EFI_S3_SAVE_STATE_WRITE) (
IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,
IN UINTN OpCode,
. . .
);
This
A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance.
OpCode
The operation code (opcode) number. See “Related Definitions” below for the defined opcode types.
...
Argument list that is specific to each opcode. See the following subsections for the definition of each opcode.
ThisfunctionisusedtostoreanOpCodetobereplayedaspartoftheS3resumebootpath. Itisassumedthisprotocol
has platform specific mechanism to store the OpCode set and replay them during the S3 resume.
Note:The opcode is inserted at the end of the boot script table
Thisfunctionhasavariableparameterlist. Theexactparameterlistdependsonthe OpCodethatispassedintothefunc-
tion. IfanunsupportedOpCodeorillegalparameterlistispassedin,thisfunctionreturns EFI_INVALID_PARAMETER
.
Iftherearenotenoughresourcesavailableforstoringmorescripts,thisfunctionreturns EFI_OUT_OF_RESOURCES
.
V-8.7. S3 Save State Protocol V-65UEFI Platform Initialization Specification, Release 1.8
OpCodevalues of 0x80 - 0xFE are reserved for implementation-specific functions.
//******************************************\*
// EFI Boot Script Opcode definitions
#define EFI_BOOT_SCRIPT_IO_WRITE_OPCODE 0x00
#define EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE 0x01
#define EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE 0x02
#define EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE 0x03
#define EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE 0x04
#define EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE 0x05
#define EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE 0x06
#define EFI_BOOT_SCRIPT_STALL_OPCODE 0x07
#define EFI_BOOT_SCRIPT_DISPATCH_OPCODE 0x08
#define EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE 0x09
#define EFI_BOOT_SCRIPT_INFORMATION_OPCODE 0x0A
#define EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE 0x0B
#define EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE 0x0C
#define EFI_BOOT_SCRIPT_IO_POLL_OPCODE 0x0D
#define EFI_BOOT_SCRIPT_MEM_POLL_OPCODE 0x0E
#define EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE 0x0F
#define EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE 0x10
// EFI_BOOT_SCRIPT_WIDTH
EfiBootScriptWidthUint8,
EfiBootScriptWidthUint16,
EfiBootScriptWidthUint32,
EfiBootScriptWidthUint64,
EfiBootScriptWidthFifoUint8,
EfiBootScriptWidthFifoUint16,
EfiBootScriptWidthFifoUint32,
EfiBootScriptWidthFifoUint64,
EfiBootScriptWidthFillUint8,
EfiBootScriptWidthFillUint16,
EfiBootScriptWidthFillUint32,
EfiBootScriptWidthFillUint64,
EfiBootScriptWidthMaximum
} EFI_BOOT_SCRIPT_WIDTH;
EFI_SUCCESS TheoperationsucceededArecordwasaddedintothespecifiedscript
table
EFI_INVALID_PARAMETER The parameter is illegal or the given boot script is not supported
EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script
V-8.7. S3 Save State Protocol V-66UEFI Platform Initialization Specification, Release 1.8
V-8.7.3.1 Opcodes for Write()
This section contains the prototypes for variations of the Write()function, based on the Opcodeparameter.
V-8.7.4 EFI_BOOT_SCRIPT_IO_WRITE_OPCODE
Summary
Adds a record for an I/O write operation into a specified bootscript table.
Prototype
typedef
(EFIAPI \*EFI_BOOT_SCRIPT_WRITE) (
IN UINT16 OpCode,
IN EFI_BOOT_SCRIPT_WIDTH Width,
);
This
OpCode
Mustbesetto EFI_BOOT_SCRIPT_IO_WRITE_OPCODE .ValueEFI_BOOT_SCRIPT_IO_WRITE_OPCODE
is defined in “Related Definitions” in EFI_S3_SAVE_STATE_PROTOCOL.Write() .
Width
The width of the I/O operations. Enumerated in EFI_BOOT_SCRIPT_WIDTH
. Type EFI_BOOT_SCRIPT_WIDTH is defined in “Related Definitions” in
EFI_S3_SAVE_STATE_PROTOCOL.Write() .
Address
The base address of the I/O operations.
Count
ThenumberofI/Ooperationstoperform. Thenumberofbytesmovedis Widthsize*Count,startingat Address
.
Buffer
The source buffer from which to write data. The buffer size is Widthsize* Count.
This function adds an I/O write record into a specified boot script table. On script execution, this operation writes the
presaved value into the specified I/O ports.
The caller is responsible for complying with any I/O alignment and width requirements presented by the bus, device,
or platform. For example, on some platforms, width requests of EfiBootScriptWidthUint64 might not work.
If Width is EfiBootScriptWidthUint8, EfiBootScriptWidthUint16, EfiBootScriptWidthUint32, or Efi-
BootScriptWidthUint64, then:
•BufferisincrementedforeachoftheCountoperationswhenaddingtherecordtothespecifiedbootscripttable,
V-8.7. S3 Save State Protocol V-67UEFI Platform Initialization Specification, Release 1.8
•Address is incremented for each of the Count operations when the array of presaved values is written on script
If Width is EfiBootScriptWidthFifoUint8, EfiBootScriptWidthFifoUint16, EfiBootScriptWidthFifoUint32, or Efi-
BootScriptWidthFifoUint64, then
•Address is reused unchanged for each of the Count operations when the array of presaved values is written on
script execution.
If Width is EfiBootScriptWidthFillUint8, EfiBootScriptWidthFillUint16, EfiBootScriptWidthFillUint32, or Efi-
BootScriptWidthFillUint64, then
•Buffer is reused unchanged for each of the Count operations when adding the record to the specified boot script
table,
•AddressisincrementedforeachoftheCountoperationswhenthepresavedvalueiswrittenonscriptexecution.
See “Status Codes Returned” in Write().
V-8.7.5 EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE
Summary
Adds a record for an I/O modify operation into a specified boot script table.
Prototype
typedef
IN VOID *DataMask
);
This
OpCode
Must be set to EFI_BOOT_SCRIPT_IO_POLL_OPCODE . ValueEFI_BOOT_SCRIPT_IO_POLL_OPCODE
is defined in “Related Definitions” in EFI_S3_SAVE_STATE_PROTOCOL.Write()
Width
EFI_S3_SAVE_STATE_PROTOCOL.Write() .EfiBootScriptWidthFifoUint8, EfiBootScriptWidthFifoUint16,
EfiBootScriptWidthFifoUint32, and EfiBootScriptWidthFifoUint64 are**interpreted identically to Efi-
BootScriptWidthUint8, EfiBootScriptWidthUint16, EfiBootScriptWidthUint32, and EfiBootScriptWidthUint64,
V-8.7. S3 Save State Protocol V-68UEFI Platform Initialization Specification, Release 1.8
EfiBootScriptWidthFillUint8, EfiBootScriptWidthFillUint16, EfiBootScriptWidthFillUint32, and Efi-
BootScriptWidthFillUint64 are interpreted identically to EfiBootScriptWidthUint8, EfiBootScriptWidthUint16,
EfiBootScriptWidthUint32, and EfiBootScriptWidthUint64, respectively.
Address
Data
A pointer to the data to be OR-ed.
DataMask

Width
Address
Data
DataMask
A pointer to the data mask to be AND-ed with the data read from the register.
This function adds an I/O read and write record into the specified boot script table. When the script is executed, the
register at Address is read, AND-ed with DataMask, and OR-ed with Data, and finally the result is written back.
V-8.7.6 EFI_BOOT_SCRIPT_IO_POLL_OPCODE
Summary
AddsarecordforI/OreadstheI/Olocationandcontinueswhentheexitcriteriaissatisfiedorafteradefinedduration.
Prototype
typedef
IN VOID *DataMask,
IN UINT64 Delay
);
This
OpCode
Must be set to EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE . Value
EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE is defined in “Related Definitions” in
Width
V-8.7. S3 Save State Protocol V-69UEFI Platform Initialization Specification, Release 1.8
EfiBootScriptWidthFifoUint32, and EfiBootScriptWidthFifoUint64 are interpreted identically to Efi-
Address
Data
The comparison value used for the polling exit criteria.
DataMask
Mask used for the polling criteria. The bits in the bytes below Widthwhich are zero in Dataare ignored when
polling the memory address.
Delay
The number of 100ns units to poll. Note that timer available may be of poorer granularity so the delay may be
longer.
Thisfunctionaddsadelaytothebootscripttable. TheI/Oreadoperationisrepeateduntileithera Delayofatleast100
nsunitshasexpired,or( Data&DataMask )isequalto Data. AtleastoneI/Oaccessisalwaysperformedregardless
of the value of Delay.
V-8.7.7 EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE
Summary
Adds a record for a memory write operation into a specified boot script table.
Prototype
typedef
IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This ,
);
This
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OpCode
Mustbesetto EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE. ValueEFI_BOOT_SCRIPT_MEM_WRITE_OPCODE
Width
The width of the memory operations. Enumerated in EFI_BOOT_SCRIPT_WIDTH
Address
The base address of the memory operations. Address needs alignment if required.
Count
The number of memory operations to perform. The number of bytes moved is Width size * Count, starting at
Address.
Buffer
The source buffer from which to write the data. The buffer size is Widthsize *Count.
Thisfunctionaddsamemorywriterecordintoaspecifiedbootscripttable. Whenthescriptisexecuted,thisoperation
writes the presaved value into the specified memory location.
The caller is responsible for complying with any memory and MMIO alignment and width requirements presented by
the bus, device, or platform. For example, on some platforms, width requests of EfiBootScriptWidthUint64 might not
work.
BootScriptWidthFifoUint64, then:
BootScriptWidthFillUint64, then:
table,
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V-8.7.8 EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE
Summary
Adds a record for a memory modify operation into a specified boot script table.
Prototype
typedef
);
This
OpCode
Must be set to EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE . Value
EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE is defined in “Related Definitions” in
Width
The width of the memory operations. Enumerated in EFI_BOOT_SCRIPT_WIDTH.
Type EFI_BOOT_SCRIPT_WIDTH is defined in “Related Definitions” in
EFI_S3_SAVE_STATE_PROTOCOL.Write() .EfiBootScriptWidthFifoUint8 ,EfiBootScriptWidthFifoUint16
,EfiBootScriptWidthFifoUint32 , andEfiBootScriptWidthFifoUint64 are interpreted identically to Efi-
BootScriptWidthUint8 ,EfiBootScriptWidthUint16 ,EfiBootScriptWidthUint32 , andEfiBootScriptWidthUint64
, respectively. *
EfiBootScriptWidthFillUint8* , EfiBootScriptWidthFillUint16 ,EfiBootScriptWidthFillUint32 , andEfi-
BootScriptWidthFillUint64 areinterpreted identically to EfiBootScriptWidthUint8 ,EfiBootScriptWidthUint16 ,
EfiBootScriptWidthUint32 , andEfiBootScriptWidthUint64 , respectively.
Address
The base address of the memory operations. Addressneeds alignment if required.
Data
DataMask
This function adds a memory read and write record into a specified boot script table. When the script is executed, the
memory at Addressis read,AND-ed withDataMask , andOR-ed withData, and finally the result is written back.
work.
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V-8.7.9 EFI_BOOT_SCRIPT_MEM_POLL_OPCODE
Summary
Adds a record for memory reads of the memory location and continues when the exit criteria is satisfied or after a
defined duration.
Prototype
typedef
);
This
OpCode
Mustbesetto EFI_BOOT_SCRIPT_MEM_POLL_OPCODE .ValueEFI_BOOT_SCRIPT_MEM_POLL_OPCODE
Width
EfiBootScriptWidthFifoUint8 ,EfiBootScriptWidthFifoUint16 ,EfiBootScriptWidthFifoUint32 , andEfi-
BootScriptWidthFifoUint64 areinterpretedidenticallyto EfiBootScriptWidthUint8 ,EfiBootScriptWidthUint16 ,

Summary
Prototype
typedef
);
This
OpCode
Width
EfiBootScriptWidthFillUint8 ,EfiBootScriptWidthFillUint16 ,EfiBootScriptWidthFillUint32 , andEfi-
Address
Data
DataMask
Mask used for the polling criteria. The bits in the bytes below Width which are zero in Data are ignored when
Delay
longer.
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This function adds a delay to the boot script table. The memory read operation is repeated until either a timeout of
Delay100nsunitshasexpired,or( Data&DataMask )isequalto Data. AtleastoneI/Oaccessisalwaysperformed
regardless of the value of Delay.
work.
V-8.7.10 EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE
Summary
Adds a record for a PCI configuration space write operation into a specified boot script table.
Prototype
typedef
)
This
OpCode
Must be set to EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE . Value
EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE is defined in “Related Definitions” in
Width
The width of the PCI operations. Enumerated in EFI_BOOT_SCRIPT_WIDTH
Address
The address within the PCI configuration space. For address format details, see the “PCI Configuration
Address” table in the UEFI Specification, under EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() and
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write(). <http://uefi.org/specifications> `__
Count
ThenumberofPCIoperationstoperform. Thenumberofbytesmovedis Widthsize*Count,startingat Address.
Buffer
The source buffer from which to write the data. The buffer size is Widthsize* Count.
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ThisfunctionaddsaPCIconfigurationspacewriterecordintoaspecifiedbootscripttable. Whenthescriptisexecuted,
this operation writes the presaved value into the specified location in PCI configuration space.
ThecallerisresponsibleforcomplyingwithanyPCIconfigurationspacealignmentandwidthrequirementspresented
by the bus, device, or platform. For example, on some platforms, width requests of EfiBootScriptWidthUint64 might
not work.
table,
Incrementing Address (that is, when Width is EfiBootScriptWidthUint8, EfiBootScriptWidthUint16, Efi-
BootScriptWidthUint32, EfiBootScriptWidthUint64, EfiBootScriptWidthFillUint8, EfiBootScriptWidthFillUint16,
EfiBootScriptWidthFillUint32, or EfiBootScriptWidthFillUint64) provides a way to write several registers in the con-
figuration space of the same PCI or PCI Express Bus/Device/Function that is encoded by the initial value of Address,
using a single record in the specified boot script table.
If,onscriptexecution,aregisterwriteisattemptedthatisoutsideoftheconfigurationspaceofthePCIorPCIExpress
Bus/Device/Function that was encoded by the initial value of Address, the behavior is undefined.
For PCI Express devices, it is valid to encode an 8-bit starting configuration space offset in byte
0 of Address, and to continue into extended configuration space during the execution of the same
EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE.
In addition to the common status codes specified in Write(), Write() may optionally return the following status code
when OpCode is EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE:
EFI_INVALID_PARAMETERPerformingCountconfigurationspacewritesstartingatAddress,asdictatedbyWidth,
would cross the configuration space boundary for the PCI or PCI Express Bus/Device/Function that was encoded in
the original value of Address. It is unspecified whether an implementation of Write() recognizes this error.
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V-8.7.11 EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE
Summary
Adds a record for a PCI configuration space modify operation into a specified boot script table.
Prototype
typedef
);
This
OpCode
Must be set to EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE . Value
EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE is defined in “Related Definitions” in
Width
BootScriptWidthFillUint64 are interpreted identically to EfiBootScriptWidthUint8 ,EfiBootScriptWidthUint16
,EfiBootScriptWidthUint32 , andEfiBootScriptWidthUint64 , respectively.
Address
The address within the PCI configuration space. For address format details, see the “PCI Configura-
tion Address” in the UEFI Specification, under EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() and
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() .
Data
A pointer to the data to be OR-ed. The size depends on Width.
DataMask
A pointer to the data mask to be AND-ed.
This function adds a PCI configuration read and write record into a specified boot script table. When the script is
executed, the PCI configuration space location at Addressis read,AND-ed withDataMask , andOR-ed with, and
finally the result is written back.
V-8.7. S3 Save State Protocol V-76UEFI Platform Initialization Specification, Release 1.8
not work.
V-8.7.12 EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE
Summary
Adds a record for PCI configuration space reads and continues when the exit criteria is satisfied or after a defined
duration.
Prototype
typedef
);
This
OpCode
Must be set to EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE . Value
EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE is defined in “Related Definitions” in
Width

not work.
Summary
duration.
Prototype
typedef
);
This
OpCode
Width
Address
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write().
Data
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DataMask
Delay
longer.
This function adds a delay to the boot script table. The PCI configuration read operation is repeated until either a
timeout of Delay100 ns units has expired, or ( Data&DataMask ) is equal to Data. At least one PCI configuration
access is always performed regardless of the value of Delay.
not work.
V-8.7.13 EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE
Summary
Prototype
typedef
IN UINT16 Segment,
);
This
OpCode
Must be set to EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE . Value
Width
Segment
The PCI segment number for Address.
V-8.7. S3 Save State Protocol V-78UEFI Platform Initialization Specification, Release 1.8
Address
Count
ThenumberofPCIoperationstoperform. Thenumberofbytesmovedis Widthsize*Count,startingat Address
.
Buffer
not work.
table,
figuration space of the same PCI or PCI Express
Segment/Bus/Device/FunctionthatisencodedbytheSegmentparameterandtheinitialvalueofAddress,usingasingle
record in the specified boot script table.
If, on script execution, a register write is attempted that is outside of the configuration space of the PCI or PCI Ex-
press Segment/Bus/Device/Function that was encoded by the Segment parameter and the initial value of Address, the
behavior is undefined.
EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE.
V-8.7. S3 Save State Protocol V-79UEFI Platform Initialization Specification, Release 1.8
when OpCode is EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE:
would cross the configuration space boundary for the PCI or PCI Express Segment/Bus/Device/Function that was
encoded in the Segment parameter and the original value of Address. It is unspecified whether an implementation of
Write() recognizes this error.
V-8.7.14 EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE
Summary
Prototype
typedef
)
This
OpCode
Must be set to EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE . Value
Width
EfiBootScriptWidthUint16 ,EfiBootScriptWidthUint32 , andEfiBootScriptWidthUint64 , respectively.
Segment
Address
Data
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DataMask
not work.
V-8.7.15 EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE
Summary
duration.
Prototype
typedef

DataMask
not work.
Summary
duration.
Prototype
typedef
);
This
OpCode
Must be set to EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE . Value
EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE is defined in “Related Definitions” in
Width
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Segment
Address
Data
DataMask
Mask used for the polling criteria. The bits in the bytes below Width which are zero in Dataare ignored when
Delay
longer.
timeout of Delay100 ns units has expired, or ( Data&DataMask) is equal to Data. At least one PCI configuration
not work.
V-8.7.16 EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE
Summary
Adds a record for an SMBus command execution into a specified boot script table.
Prototype
typedef
IN CONST \_EFI_S3_SAVE_STATE_PROTOCOL *This,
IN UINTN *Length,
);
V-8.7. S3 Save State Protocol V-82UEFI Platform Initialization Specification, Release 1.8
This
OpCode
Must be set to EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE . Value
EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE is defined in “Related Definitions” in
TheSMBusaddressfortheslavedevicethattheoperationistargeting. Type EFI_SMBUS_DEVICE_ADDRESS
is defined in EFI_PEI_SMBUS_PPI.Execute() in thePI Specification .
Command
The command that is transmitted by the SMBus host controller to the SMBus slave device. The interpretation
is SMBus slave device specific. It can mean the offset to a list of functions inside an SMBus slave device. Type
EFI_SMBUS_DEVICE_COMMAND is defined in EFI_PEI_SMBUS_PPI.Execute() in thePI Specification .
Operation
Indicates which particular SMBus protocol it will use to execute the SMBus transactions. Type
EFI_SMBUS_OPERATION is defined in EFI_PEI_SMBUS_PPI.Execute() in thePI Specification .
PecCheck
Length
A pointer to signify the number of bytes that this operation will do.
Buffer
Contains the value of data to execute to the SMBUS slave device.
ThisfunctionaddsanSMBuscommandexecutionrecordintoaspecifiedbootscripttable. Whenthescriptisexecuted,
this operation executes a specified SMBus command.
V-8.7.17 EFI_BOOT_SCRIPT_STALL_OPCODE
Summary
Adds a record for an execution stall on the processor into a specified boot script table.
Prototype
typedef
IN UINTN Duration
);
This
V-8.7. S3 Save State Protocol V-83UEFI Platform Initialization Specification, Release 1.8
OpCode
Must be set to EFI_BOOT_SCRIPT_STALL_OPCODE . ValueEFI_BOOT_SCRIPT_STALL_OPCODE is de-
fined in “Related Definitions” in EFI_S3_SAVE_STATE_PROTOCOL.Write() .
Duration
Duration in microseconds of the stall.
Thisfunctionaddsastallrecordintoaspecifiedbootscripttable. Whenthescriptisexecuted,thisoperationwillstall
the system for Duration number of microseconds.
V-8.7.18 EFI_BOOT_SCRIPT_DISPATCH_OPCODE
Summary
Adds a record for dispatching specified arbitrary code into a specified boot script table.
Prototype
typedef
IN EFI_PHYSICAL_ADDRESS EntryPoint
);
This
OpCode
Mustbesetto EFI_BOOT_SCRIPT_DISPATCH_OPCODE .ValueEFI_BOOT_SCRIPT_DISPATCH_OPCODE
Entry point of the code to be dispatched. Type EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the
UEFI 2.0 Specification.
This function adds a dispatch record into a specified boot script table, with which it can run the arbitrary code that is
specified. This script can be used to initialize the processor. When the script is executed, the script incurs jumping to
the entry point to execute the arbitrary code. After the execution is returned, it goes on executing the next opcode in
the table.
TheEntryPoint mustpointtomemoryoftypeof EfiRuntimeServicesCode ,EfiRuntimeServicesData ,orEfiACPIMem-
oryNVS. The EntryPoint must have the same calling convention as the PI DXE Phase.
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V-8.7.19 EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE
Summary
Prototype
typedef
IN EFI_PHYSICAL_ADDRESS EntryPoint,
IN EFI_PHYSICAL_ADDRESS Context
);
This
OpCode
Mustbesetto EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE .ValueEFI_BOOT_SCRIPT_DISPATCH_2_OPCODE
UEFI Specification .
Context
Argument to be passed into the EntryPoint of the code to be dispatched. Type EFI_PHYSICAL_ADDRESS is
defined in AllocatePages() in theUEFI Specification .
the table.
TheEntryPoint andContextmust point to memory of type of EfiRuntimeServicesCode ,EfiRuntimeServicesData , or
EfiACPIMemoryNVS . TheEntryPoint must have the same calling convention as the PI DXE Phase.
V-8.7.20 EFI_BOOT_SCRIPT_INFORMATION_OPCODE
Summary
Store the pointer to the arbitrary information in the boot script table. This opcode is a no-op on dispatch and is only
used for debugging script issues.
Prototype
V-8.7. S3 Save State Protocol V-85UEFI Platform Initialization Specification, Release 1.8
typedef
IN UINT32 InformationLength,
IN EFI_PHYSICAL_ADDRESS Information
);
This
OpCode
Must be set to EFI_BOOT_SCRIPT_INFORMATION_OPCODE . Value
EFI_BOOT_SCRIPT_INFORMATION_OPCODE is defined in “Related Definitions” in
InformationLength
Length of the data in bytes.
Information
Pointer to the information to be logged in the boot script.

Summary
Prototype
typedef
);
This
OpCode
ThisfunctionaddsarecordthathasnoimpactontheS3replay. Thisfunctionisusedtostoredebuginformationinthe
S3 data stream.
TheInformation mustpointtomemoryoftypeof EfiRuntimeServicesCode ,EfiRuntimeServicesData ,orEfiACPIMem-
oryNVS.
V-8.7.21 Save State Insert
V-8.7.22 EFI_S3_SAVE_STATE_PROTOCOL.Insert()
Summary
Prototype
typedef
(EFIAPI \*EFI_S3_SAVE_STATE_INSERT) (
IN BOOLEAN BeforeOrAfter,
IN OUT EFI_S3_BOOT_SCRIPT_POSITION *Position OPTIONAL,
...
);
V-8.7. S3 Save State Protocol V-86UEFI Platform Initialization Specification, Release 1.8
This
A pointer to the EFI_S3_SAVE_STATE_PROTOCO L instance.
BeforeOrAfter
Specifies whether the opcode is stored before ( TRUE)or after ( FALSE) the position in the boot script table
specified by Position. IfPositionisNULLor points to NULLthen the new opcode is inserted at the beginning
of the table (if TRUE)or end of the table (if FALSE).
Position
On entry, specifies the position in the boot script table where the opcode will be inserted, either before or after,
depending on BeforeOrAfter . On exit, if not NULL, specifies the position of the inserted opcode in the boot
script table.
OpCode
The operation code (opcode) number. See “Related Definitions” in Write()for the defined opcode types.
...
Thisfunctionisusedtostorean OpCodetobereplayedaspartoftheS3resumebootpath. Itisassumedthisprotocol
has platform specific mechanism to store the OpCodeset and replay them during the S3 resume.
The opcode is stored before ( TRUE) or after ( FALSE) the position in the boot script table specified by Position. If
PositionisNULLorpointsto NULLthenthenewopcodeisinsertedatthebeginningofthetable(if TRUE)orendof
the table (if FALSE).
The position which is pointed to by Positionupon return can be used for subsequent insertions.
tion. Ifanunsupported OpCodeorillegalparameterlistispassedin,thisfunctionreturns EFI_INVALID_PARAMETER
.
.
OpCodevalues of 0x80 - 0xFE are reserved for implementation specific functions.
typedef VOID \*EFI_S3_BOOT_SCRIPT_POSITION;
EFI_SUCCESS TheoperationsucceededAnopcodewasaddedintothescripttable
EFI_INVALID_PARAMETER The Opcode is an invalid opcode value
EFI_INVALID_PARAMETER The Position is not a valid position in the boot script table
V-8.7. S3 Save State Protocol V-87UEFI Platform Initialization Specification, Release 1.8
V-8.7.23 Save State Label
V-8.7.24 EFI_S3_SAVE_STATE_PROTOCOL.Label()
Summary
Find a label within the boot script table and, if not present,optionally create it.
Prototype
typedef
(EFIAPI \*EFI_S3_SAVE_STATE_LABEL) (
IN BOOLEAN CreateIfNotFound,
IN CONST CHAR8 *Label
);
This
Specifies whether the label is stored before ( TRUE) or after ( FALSE) the position in the boot script table
specified by Position. IfPositionisNULLor points to NULLthen the new label is inserted at the beginning of
the table (if TRUE) or end of the table (if FALSE).
CreateIfNotFound
Specifies whether the label will be created if the label does not exists ( TRUE) or not ( FALSE).
Position
On entry, specifies the position in the boot script table where the label will be inserted, either before or after,
dependingon BeforeOrAfter . Onexit,ifnotNULL,specifiesthepositionoftheinsertedlabelinthebootscript
table.
Label
Points to the NULL terminated label which will be inserted in the boot script table.
Ifthelabel Labelalreadyexistsinthebootscripttable,thennonewlabeliscreated,thepositionofthe Labelisreturned
in* Position (ifPositionis not NULL) and EFI_SUCCESS is returned. If the label already exists, the input value of
thePositionis ignored.
If the label Labeldoes not already exist and CreateIfNotFound isTRUE, then it will be created before or after the
specified position and EFI_SUCCESS is returned.
If the label Labeldoes not already exist and CreateIfNotFound isFALSE, thenEFI_NOT_FOUND is returned.
EFI_SUCCESS The label already exists or was inserted
EFI_NOT_FOUND The label did not already exist and CreateifNotFound wasFALSE
EFI_INVALID_PARAMETER TheLabelisNULLor points to an empty string
EFI_INVALID_PARAMETER ThePositionis not a valid position in the boot script table
V-8.7. S3 Save State Protocol V-88UEFI Platform Initialization Specification, Release 1.8
V-8.7.25 Save State Compare
V-8.7.26 EFI_S3_SAVE_STATE_PROTOCOL.Compare()
Summary
Compare two positions in the boot script table and return their relative position.
Prototype
typedef
(EFIAPI \*EFI_S3_SAVE_STATE_COMPARE) (
IN EFI_S3_BOOT_SCRIPT_POSITION Position1,
IN EFI_S3_BOOT_SCRIPT_POSITION Position2,
OUT UINTN *RelativePosition
);
This
Position1, Position2
The positions in the boot script table to compare.
RelativePosition
On return, points to the result of the comparison.
Thisfunctioncomparestwopositionsinthebootscripttableandreturnstheirrelativepositions. If Position1 isbefore
Position2 , then -1 is returned. If Position1 is equal to Position2 , then 0 is returned. If Position1 is afterPosition2 ,
then 1 is returned.
EFI_SUCCESS The operation succeeded
EFI_INVALID_PARAMETER ThePosition1 orPosition2 is not a valid position in the boot script
table
EFI_INVALID_PARAMETER TheRelativePosition isNULL
V-8.8 S3 SMM Save State Protocol
This section defines how a SMM PI module can record IO operations to be performed as part of the S3 resume. This
is done via the EFI_S3_SMM_SAVE_STATE_PROTOCOL and this allows the implementation of the S3 resume boot
path to be abstracted from SMM drivers.
The S3 SMM Save State Protocol shares the interface definition with the S3 Save State Protocol but it has a different
GUID. It is an SMM protocol. Having separate protocols for SMM and DXE makes it easier to accommodate the
differences in the operating environment between SMM and DXE.
V-8.8. S3 SMM Save State Protocol V-89UEFI Platform Initialization Specification, Release 1.8
V-8.8.1 EFI_S3_SMM_SAVE_STATE_PROTOCOL
Summary
GUID
#define EFI_S3_SMM_SAVE_STATE_PROTOCOL_GUID \\
{ 0x320afe62, 0xe593, 0x49cb, { 0xa9, 0xf1, 0xd4, 0xc2, \\
0xf4, 0xaf, 0x1, 0x4c } }
typedef struct \_EFI_S3_SMM_SAVE_STATE_PROTOCOL {
} EFI_S3_SMM_SAVE_STATE_PROTOCOL;
Write
Write an opcode at the end of the boot script table. See the Write()function description under the
EFI_S3_SAVE_STATE_PROTOCOL definition.
Insert
Writeanopcodeatthespecifiedpositioninthebootscripttable. Seethe Insert()functiondescriptionunderthe
Label
Find an existing label in the boot script table or, if not present, create it. See the Label()function description
under the EFI_S3_SAVE_STATE_PROTOCOL definition.
Compare
description under the EFI_S3_SAVE_STATE_PROTOCOL definition.
TheEFI_S3_SMM_SAVE_STATE_PROTOCOL provides the PI SMMboot script abstraction.
On an S3 resume boot path the data stored via this protocol is replayed in the order it was stored.
were called during the boot process.
the system state. It is recommended that runtime calls be minimized by the caller.
V-8.8. S3 SMM Save State Protocol V-90CHAPTER
NINE
ACPI SYSTEM DESCRIPTION TABLE PROTOCOL
V-9.1 EFI_ACPI_SDT_PROTOCOL
Summary
Provides services for creating ACPI system description tables.
GUID
#define EFI_ACPI_SDT_PROTOCOL_GUID \\
{ 0xeb97088e, 0xcfdf, 0x49c6, \\
{ 0xbe, 0x4b, 0xd9, 0x6, 0xa5, 0xb2, 0xe, 0x86 } }

NINE
Summary
GUID
typedef struct \_EFI_ACPI_SDT_PROTOCOL {
EFI_ACPI_TABLE_VERSION AcpiVersion;
EFI_ACPI_GET_TABLE2 GetAcpiTable;
EFI_ACPI_REGISTER_NOTIFY RegisterNotify;
EFI_ACPI_OPEN Open;
EFI_ACPI_OPEN_SDT OpenSdt;
EFI_ACPI_CLOSE Close;
EFI_ACPI_GET_CHILD GetChild;
EFI_ACPI_GET_OPTION GetOption;
EFI_ACPI_SET_OPTION SetOption;
EFI_ACPI_FIND_PATH FindPath;
} EFI_ACPI_SDT_PROTOCOL;
#define UINT32 EFI_ACPI_TABLE_VERSION;
#define EFI_ACPI_TABLE_VERSION_NONE (1 << 0)
#define EFI_ACPI_TABLE_VERSION_1_0B (1 << 1)
#define EFI_ACPI_TABLE_VERSION_2_0 (1 << 2)
#define EFI_ACPI_TABLE_VERSION_3_0 (1 << 3)
#define EFI_ACPI_TABLE_VERSION_4_0 (1 << 4)
#define EFI_ACPI_TABLE_VERSION_5_0 (1 << 5)
Members
AcpiVersion
A bit map containing all the ACPI versions supported by this protocol.
V-91UEFI Platform Initialization Specification, Release 1.8
GetTable
Enumerate the ACPI tables.
RegisterNotify
Register a notification when a table is installed.
Open
Create a handle from an ACPI opcode.
OpenSdt
Create a handle from an ACPI table.
Close
Close an ACPI handle.
GetChild
Cycle through the child objects of an ACPI handle.
GetOption
Return one of the optional pieces of the opcode.
SetOption
Change one of the optional pieces of the opcode.
FindPath
Given an ACPI path, return an ACPI handle.
V-9.1.1 EFI_ACPI_SDT_PROTOCOL.GetAcpiTable()
Summary
Returns a requested ACPI table.
Prototype
typedef
(EFIAPI \*EFI_ACPI_GET_ACPI_TABLE) (
IN UINTN Index,
OUT EFI_ACPI_SDT_HEADER **Table,
OUT EFI_ACPI_TABLE_VERSION *Version,
OUT UINTN *TableKey
);
Index
The zero-based index of the table to retrieve.
Table
Pointerforreturningthetablebuffer. Type EFI_ACPI_SDT_HEADER isdefinedin“RelatedDefinitions”below.
Version
On return, updated with the ACPI versions to which this table belongs. Type EFI_ACPI_TABLE_VERSION is
defined in “Related Definitions” in the EFI_ACPI_SDT_PROTOCOL .
TableKey
On return, points to the table key for the specified ACPI system definition table. This is identi-
cal to the table key used in the EFI_ACPI_TABLE_PROTOCOL . TheTableKey can be passed to
EFI_ACPI_TABLE_PROTOCOL.UninstallAcpiTable() to uninstall the table.
V-9.1. EFI_ACPI_SDT_PROTOCOL V-92UEFI Platform Initialization Specification, Release 1.8
TheGetAcpiTable( )functionreturnsapointertoabuffercontainingtheACPItableassociatedwiththeIndexthatwas
input. The following structures are not considered elements in the list of ACPI tables:
•Root System Description Pointer (RSD_PTR)
•Root System Description Table (RSDT)
•Extended System Description Table (XSDT)
Version is updated with a bit map containing all the versions of ACPI of which the table is a member.
Fortablesinstalledviathe EFI_ACPI_TABLE_PROTOCOL.InstallAcpiTable() interface,thefunctionreturnsthevalue
ofEFI_ACPI_STD_PROTOCOL.AcpiVersion .
Related Definitions .. code-block:
UINT8 Checksum;
CHAR8 OemId[6];
CHAR8 OemTableId[8];
UINT32 OemRevision;
UINT32 CreatorId;
UINT32 CreatorRevision;
} EFI_ACPI_SDT_HEADER;
Thisstructureisbasedonthe DESCRIPTION_HEADER structure,definedinsection5.2.6ofthe ACPI3.0specification
.
EFI_NOT_FOUND The requested index is too large and a table was not found
V-9.1.2 EFI_ACPI_SDT_PROTOCOL.RegisterNotify()
Summary
Register or unregister a callback when an ACPI table is installed.
Prototype
typedef
(EFIAPI \*EFI_ACPI_REGISTER_NOTIFY) (
IN BOOLEAN Register,
IN EFI_ACPI_NOTIFICATION_FN Notification
);
Register
IfTRUE, then the specified function will be registered. If FALSE, then the specified function will be unregis-
tered.
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Notification
Pointstothecallbackfunctiontoberegisteredorunregistered. Type EFI_ACPI_NOTIFICATION_FN isdefined
This function registers or unregisters a function which will be called whenever a new ACPI table is installed.
EFI_SUCCESS Callback successfully registered or unregistered
EFI_INVALID_PARAMETER Notification is NULL
EFI_INVALID_PARAMETER Register is FALSE and Notification does not match a known regis-
tration function
typedef
(EFIAPI \*EFI_ACPI_NOTIFICATION_FN)(
IN EFI_ACPI_SDT_HEADER *Table,
IN EFI_ACPI_TABLE_VERSION Version,
IN UINTN TableKey
);
Table
A pointer to the ACPI table header.
Version
The ACPI table’s version. Type EFI_ACPI_TABLE_VERSION is defined in “Related Definitions” in the
EFI_ACPI_SDT_PROTOCOL .
TableKey
The table key for this ACPI table. This is identical to the table key used in the
EFI_ACPI_TABLE_PROTOCOL . This function is called each time a new ACPI table is added using
EFI_ACPI_TABLE_PROTOCOl.InstallAcpiTable() .
V-9.1.3 EFI_ACPI_SDT_PROTOCOL.Open()
Summary
Create a handle from an ACPI opcode
Prototype
typedef
(EFIAPI \*EFI_ACPI_OPEN) (
OUT EFI_ACPI_HANDLE *Handle
);
Buffer
Points to the ACPI opcode.
V-9.1. EFI_ACPI_SDT_PROTOCOL V-94UEFI Platform Initialization Specification, Release 1.8
Handle
Upon return, holds the handle.
typedef VOID *EFI_ACPI_HANDLE;
Creates a handle from a single ACPI opcode.
Status Code Values
EFI_SUCCESS Success
EFI_INVALID_PARAMETER Bufferis NULL or Handleis NULL or Bufferpoints to an invalid
opcode.
V-9.1.4 EFI_ACPI_SDT_PROTOCOL.OpenSdt()
Summary
Create a handle for the first ACPI opcode in an ACPI system description table.
Prototype
typedef
(EFIAPI \*EFI_ACPI_OPEN_SDT) (
);
TableKey
The table key for the ACPI table, as returned by GetTable() .
Handle
On return, points to the newly created ACPI handle. Type EFI_ACPI_HANDLE is defined in “Related Defini-
Creates an ACPI handle for the top-level opcodes in the ACPI system description table specified by TableKey .
EFI_SUCCESS Handlecreated successfully.
EFI_NOT_FOUND TableKey does not refer to a valid ACPI table.
V-9.1. EFI_ACPI_SDT_PROTOCOL V-95UEFI Platform Initialization Specification, Release 1.8
V-9.1.5 EFI_ACPI_SDT_PROTOCOL.Close()
Summary
Prototype
typedef
(EFIAPI \*EFI_ACPI_CLOSE) (
IN EFI_ACPI_HANDLE Handle
);
Handle
Returns the handle. Type EFI_ACPI_HANDLE is defined in Open().
Closes the ACPI handle and, if any changes were made, updates the table checksum.
EFI_INVALID_PARAMETER Handleis NULL or does not refer to a valid ACPI object.
V-9.1.6 EFI_ACPI_SDT_PROTOCOL.GetChild()
Summary
Return the child ACPI objects.
Prototype
typedef
(EFIAPI \*EFI_ACPI_ENUM) (
IN EFI_ACPI_HANDLE ParentHandle,
IN OUT EFI_ACPI_HANDLE *Handle
);
Parent handle.
Handle
Onentry,pointstothepreviouslyreturnedhandleorNULLtostartwiththefirsthandle. Onreturn,pointstothe
next returned ACPI handle or NULL if there are no child objects.
Iterates through all children ACPI objects of the ACPI object specified by the handle ParentHandle .
V-9.1. EFI_ACPI_SDT_PROTOCOL V-96UEFI Platform Initialization Specification, Release 1.8
EFI_INVALID_PARAMETER ParentHandle is NULL or does not refer to a valid ACPI object.
V-9.1.7 EFI_ACPI_SDT_PROTOCOL.GetOption()
Summary
Retrieve information about an ACPI object.
Prototype
typedef
(EFIAPI \*EFI_ACPI_GET_OPTION) (
IN EFI_ACPI_HANDLE Handle,
OUT EFI_ACPI_DATA_TYPE *DataType,
OUT CONST VOID **Data,
OUT UINTN *DataSize
);
Handle
ACPI object handle.
Index
Index of the data to retrieve from the object. In general, indexes read from left-to-right in the ACPI encoding,
with index 0 always being the ACPI opcode.
DataType
Pointstothereturneddatatypeor EFI_ACPI_DATA_TYPE_NONE ifnodataexistsforthespecifiedindex. See
EFI_ACPI_DATA_TYPE in Related Definitions.
Data
Upon return, points to the pointer to the data.
DataSize
Upon return, points to the size of Data.
typedef UINT32 EFI_ACPI_DATA_TYPE;
#define EFI_ACPI_DATA_TYPE_NONE 0
#define EFI_ACPI_DATA_TYPE_OPCODE 1
#define EFI_ACPI_DATA_TYPE_NAME_STRING 2
#define EFI_ACPI_DATA_TYPE_OP 3
#define EFI_ACPI_DATA_TYPE_UINT 4
#define EFI_ACPI_DATA_TYPE_STRING 5
#define EFI_ACPI_DATA_TYPE_CHILD 6
Retrieves various fields encoded within the ACPI object. All ACPI objects support at least index 0.
V-9.1. EFI_ACPI_SDT_PROTOCOL V-97UEFI Platform Initialization Specification, Release 1.8
TheEFI_ACPI_DATA_TYPE_NONE indicates that the specified ACPI object does not support the spec-
ified option. The EFI_ACPI_DATA_TYPE_OPCODE indicates that the option is an ACPI opcode.
TheEFI_ACPI_DATA_TYPE_NAME_STRING indicates that the option is an ACPI name string. The

Data
DataSize
EFI_ACPI_DATA_TYPE_OP indicates that the option is an ACPI opcode. The Open()function can be used to
manipulate the contents of this ACPI opcode. The EFI_ACPI_DATA_TYPE_UINT indicates that the option is an
unsigned integer. The size of the integer is indicated by DataSize . TheEFI_ACPI_DATA_TYPE_STRING indicates
thattheoptionisastringwhoselengthisindicatedby DataSize . TheEFI_ACPI_DATA_TYPE_CHILD indicatesthat
the opcode has child data, pointed to by Data, with the size DataSize.
Table 9.1: AML terms and supported options
Term 0 123456
ACPI_OP_ZERO 0000
ACPI_OP_ONE 0001
ACPI_OP_ALIAS 0006 NN
ACPI_OP_NAME 0008 NO
ACPI_OP_BYTE 000A U8
ACPI_OP_WORD 000B U16
ACPI_OP_DWORD 000C U32
ACPI_OP_STRING 000D S
ACPI_OP_QWORD 000E U64
ACPI_OP_SCOPE 0010 N
ACPI_OP_BUFFER 0011 O
ACPI_OP_PACKAGE 0012 U8
ACPI_OP_PACKAGE1 0013 O
ACPI_OP_METHOD 0014 NU8
ACPI_OP_LOCAL0 0060
ACPI_OP_LOCAL1 0061
ACPI_OP_LOCAL2 0062
ACPI_OP_LOCAL3 0063
ACPI_OP_LOCAL4 0064
ACPI_OP_LOCAL5 0065
ACPI_OP_LOCAL6 0066
ACPI_OP_LOCAL7 0067
ACPI_OP_ARG0 0068
ACPI_OP_ARG1 0069
ACPI_OP_ARG2 006A
ACPI_OP_ARG3 006B
ACPI_OP_ARG4 006C
ACPI_OP_ARG5 006D
ACPI_OP_ARG6 006E
ACPI_OP_STORE 0070 OO
ACPI_OP_REFOF 0071 O
ACPI_OP_ADD 0072 OOO
ACPI_OP_CONTACT 0073 OOO
ACPI_OP_SUBTRACT 0074 OOO
ACPI_OP_INCREMENT 0075 O
ACPI_OP_DECREMENT 0076 O
ACPI_OP_MULTIPLY 0077 OOO
ACPI_OP_DIVIDE 0078 OOOO
ACPI_OP_SHIFTLEFT 0079 OOO
ACPI_OP_SHIFTRIGHT 007A OOO
V-9.1. EFI_ACPI_SDT_PROTOCOL V-98UEFI Platform Initialization Specification, Release 1.8
ACPI_OP_AND 007B OOO
ACPI_OP_NAND 007C OOO
ACPI_OP_OR 007D OOO
ACPI_OP_NOR 007E OOO
ACPI_OP_XOR 007F OOO
ACPI_OP_NOT 0080 OO
ACPI_OP_FINDSETLEFTBIT 0081 OO
ACPI_OP_FINDSETRIGHTBIT 0082 OO
ACPI_OP_DEREFOF 0083 O
ACPI_OP_CONCATENATE 0084 OOO
ACPI_OP_MODULO 0085 OOO
ACPI_OP_NOTIFY 0086 OO
ACPI_OP_SIDEOF 0087 O
ACPI_OP_INDEX 0088 OOO
ACPI_OP_MATCH 0089 OU8OU8OO
ACPI_OP_OBJECTTYPE 008E O
ACPI_OP_LAND 0090 OO
ACPI_OP_LOR 0091 OO
ACPI_OP_LNOT 0092 O
ACPI_OP_LEQUAL 0093 OO
ACPI_OP_LGREATER 0094 OO
ACPI_OP_LLESS 0095 OO
ACPI_OP_TOBUFFER 0096 OO
ACPI_OP_TODECIMALSTRING 0097 OO
ACPI_OP_TOHEXSTRING 0098 OO
ACPI_OP_TOINTEGER 0099 OO
ACPI_OP_TOSTRING 009C OOO
ACPI_OP_COPYOBJECT 009D OO
ACPI_OP_MID 009E OOO
ACPI_OP_CONTINUE 009F
ACPI_OP_IF 00A0 O
ACPI_OP_ELSE 00A1
ACPI_OP_WHILE 00A2 O
ACPI_OP_NOP 00A3
ACPI_OP_RETURN 00A4 O
ACPI_OP_BREAK 00A5
ACPI_OP_BREAKPOINT 00CC
ACPI_OP_ONES 00FF
ACPI_OP_MUTEX 5B01 NU8
ACPI_OP_EVENT 5B02 N
ACPI_OP_CONDREFOF 5B12 OO
ACPI_OP_CREATEFIELD 5B13 OOON
ACPI_OP_LOADTABLE 5B1F OOOOOO
ACPI_OP_LOAD 5B20 NO
ACPI_OP_STALL 5B21 O
ACPI_OP_SLEEP 5B22 O
ACPI_OP_ACQUIRE 5B23 OU16
ACPI_OP_SIGNAL 5B24 O
ACPI_OP_WAIT 5B25 OO
V-9.1. EFI_ACPI_SDT_PROTOCOL V-99UEFI Platform Initialization Specification, Release 1.8
ACPI_OP_RESET 5B26 O
ACPI_OP_RELEASE 5B27 O
ACPI_OP_FROMBCD 5B28 OO
ACPI_OP_TOBCD 5B29 OO
ACPI_OP_UNLOAD 5B2A O
ACPI_OP_REVISION 5B30
ACPI_OP_DEBUG 5B31
ACPI_OP_FATAL 5B32 U8U32O
ACPI_OP_TIMER 5B33
ACPI_OP_OPERATIONREGION 5B80 NU8U32O
ACPI_OP_FIELD 5B81 NU8
ACPI_OP_DEVICE 5B82 N
ACPI_OP_PROCESSOR 5B83 NU8U32U8
ACPI_OP_POWERRESOURCE 5B84 NU8U16
ACPI_OP_THERMALZONE 5B85 N
ACPI_OP_INDEXFIELD 5B86 NNU8
ACPI_OP_BANKFIELD 5B87 NNOU8
ACPI_OP_DATAREGION 5B88 NOOO
ACPI_OP_CREATEDWORDFIELD 5B8A OON
ACPI_OP_CREATEWORDFIELD 5B8B OON
ACPI_OP_CREATEBYTEFIELD 5B8C OON
ACPI_OP_CREATEBITFIELD 5B8D OON
ACPI_OP_CREATEQWORDFIELD 5B8F OON
Status Code Returns
V-9.1.8 EFI_ACPI_SDT_PROTOCOL.SetOption()
Summary
Change information about an ACPI object.
Prototype
typedef
(EFIAPI \*EFI_ACPI_SET_OPTION) (
IN CONST VOID *Data,
);
Handle
V-9.1. EFI_ACPI_SDT_PROTOCOL V-100UEFI Platform Initialization Specification, Release 1.8
Index
Data
Points to the data.
DataSize
The size of the Data.
Changes fields within the ACPI object. If the new size will not fit in the space occupied by the previous option, then
his function will return EFI_BAD_BUFFER_SIZE . The list of opcodes and their related options can be found in
GetOption() .
EFI_BAD_BUFFER_SIZE Data cannot be accommodated in the space occupied by the option.
V-9.1.9 EFI_ACPI_SDT_PROTOCOL.FindPath()
Summary
Returns the handle of the ACPI object representing the specified ACPI path.
Prototype
typedef
(EFIAPI \*EFI_ACPI_FIND_PATH) (
IN EFI_ACPI_HANDLE HandleIn,
IN VOID *AcpiPath,
OUT EFI_ACPI_HANDLE *HandleOut
);
HandleIn
Points to the handle of the object representing the starting point for the path search.
AcpiPath
Points to the ACPI path, which conforms to the ACPI encoded path format.
HandleOut
On return, points to the ACPI object which represents AcpiPath , relative to HandleIn .
Starting with the ACPI object represented by HandleIn , walk the specified ACPI path AcpiPath and return the handle
of the ACPI object it refers to. This function supports absolute paths, relative paths and the special rules applied to
single name segments.
EFI_INVALID_PARAMETER HandleIn is NULL or does not refer to a valid ACPI object.
V-9.1. EFI_ACPI_SDT_PROTOCOL V-101CHAPTER
TEN
PCI HOST BRIDGE
V-10.1 PCI Host Bridge Overview
This specification defines the core code and services that are required for an implementation of the PCI Host Bridge
ResourceAllocationProtocol. ThisprotocolisusedbyaPCIbusdrivertoprogramthePCIhostbridgeandconfigure
therootPCIbuses. TheregistersinsidethePCIhostbridgethatcontrolrootPCIbusconfigurationarenotgovernedby
thePCIspecificationandvaryfromchipsettochipset. ThePCIHostBridgeResourceAllocationProtocolistherefore
specific to a particular chipset.
•Describes the basic components of the PCI Host Bridge Resource Allocation Protocol
•Describes several sample PCI architectures and a sample implementation of the PCI Host Bridge Resource Al-
location Protocol
•ProvidescodedefinitionsforthePCIHostBridgeResourceAllocationProtocolandthePCI-host-bridge-related
type definitions that are architecturally required by this specification.
TheEFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL does not describe platform policies. The
platform policies are described by the EFI_PCI_PLATFORM_PROTOCOL , which is desribed in PCI Platform Pro-
tocol. Silicon-related policies are described by the EFI_PCI_OVERRIDE_PROTOCOL , which is described in PCI
Override Protocol .
V-10.2 PCI Host Bridge Design Discussion
This section provides background and design information for the PCI Host Bridge Resource Allocation Protocol. A
PCIbusdriver,runningintheEFIBootServicesenvironment,usesthisprotocoltoprogramPCIhostbridgehardware.
This protocol abstracts a PCI host bridge. In particular, functions for programming a PCI host bridge are defined here
although other bus types may be supported in a similar fashion as extensions to this specification.
This chapter discusses the following:
•PCI terms that are used in this document
•An overview of the PCI Host Bridge Resource Allocation Protocol
•Sample PCI architectures
•ISA aliasing considerations
•Programming of standard PCI configuration registers
•Sample implementation
V-102UEFI Platform Initialization Specification, Release 1.8
V-10.3 PCI Host Bridge Resource Allocation Protocol
V-10.3.1 PCI Host Bridge Resource Allocation ProtocolOverview
The PCI Host Bridge Resource Allocation Protocol is used by a PCI bus driver to program a PCI host bridge. The
registersinsideaPCIhostbridgethatcontrolconfigurationofPCIrootbusesarenotgovernedbythePCIspecification
and vary from chipset to chipset. The PCI Host Bridge Resource Allocation Protocol implementation is therefore
Each PCI host bridge is comprised of one or more PCI root bridges, and there are hardware registers associated with
eachPCIrootbridge. Theseregisterscontrolthebus,I/O,andmemoryresourcesthataredecodedbythePCIrootbus
that the PCI root bridge produces and all the PCI buses that are children of that PCI root bus.
TheEFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL allows for future innovation of the
chipsets. ItabstractsthePCIbusdriverfromthechipsetdetails. Thisdesignallowssystemdesignerstomakechanges
to the host bridge hardware without impacting a platform-independent PCI bus driver.
See PCI Host Bridge Resource Allocation Protocol in Code Definitions for the definition of
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL .
V-10.3.2 Host Bus Controllers
A platform can be viewed as the following:
•A set of processors

•A set of core chipset components that may produce one or more host buses
Thefigurebelowshowsaplatformwithnprocessors(CPUs)andasetofcorechipsetcomponentsthatproducemhost
bridges (HBs).
Most systems with one PCI host bus controller will contain a single instance of the
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL . More complex systems may contain
multiple instances of this protocol.
Note: There is no relationship between the number of chipset components in a platform and the number of
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instances. Thisprotocolisanabstractionfrom
a software point of view. This protocol is attached to the device handle of a PCI host bus controller, which itself is
composed of one or more PCI root bridges. A PCI root bridge is a chipset component(s) that produces a physical PCI
bus whose parent is not another physical PCI bus.
V-10.3.3 Producing the PCI Host Bridge ResourceAllocation Protocol
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instances are produced by DXE drivers–most
often by early DXE drivers.
The figure below shows how the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
is used to identify the associated PCI root bridges. After the steps in the figure are completed, the
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL can then be queried to identify the de-
vicehandlesoftheassociated PCIrootbridges. See theUEFI2.1SpecificationfordetailsofthePCIRootBridge I/O
Protocol.
V-10.3. PCI Host Bridge Resource Allocation Protocol V-103UEFI Platform Initialization Specification, Release 1.8
Fig. 10.1: Host Bus Controllers
V-10.3. PCI Host Bridge Resource Allocation Protocol V-104UEFI Platform Initialization Specification, Release 1.8
Fig. 10.2: Producing the PCI Host Bridge Resource Allocation Protocol
V-10.3. PCI Host Bridge Resource Allocation Protocol V-105UEFI Platform Initialization Specification, Release 1.8
V-10.3.4 Required PCI Protocols
The following protocols are mandatory if the system supports PCI devices or slots:
•EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
•EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
See the UEFI 2.1 Specification for more information on the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
V-10.3.5 Relationship withEFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
It is expected, although not necessary, that a chipset-aware driver will produce the following protocol instances:
Care has been taken to avoid overlap between the member functions of the two protocols. For exam-
ple, EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL does not describe the SegmentNum-
ber or the final resource assignment for a root bridge, because these attributes are available using the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. Both protocols contain links to the associated instances of the other
protocols, as follows:
•EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL:IncludesthehandleofthePCIhostbridgethatisassociatedwith
the root bridge.
•EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL: Provides a member function to re-
trieve the handles of the associated root bridges.
Thedefinitionof EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL attemptstomaintaincompat-
ibility with the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL definition.
V-10.4 Sample PCI Architectures
V-10.4.1 Sample PCI Architectures Overview
The PCI Host Bridge Resource Allocation Protocol is a protocol that is designed to provide a software abstraction for
a wide variety of PCI architectures. This section provides examples of the following PCI architectures:
•Desktop system with 1 PCI root bridge
•Server system with 4 PCI root bridges
•Server system with 2 PCI segments
•Server system with 2 PCI host buses
ThissectionisnotintendedtobeanexhaustivelistofthePCIarchitecturesthatthePCIHostBridgeResourceAllocation
Protocolcansupport. Instead,itisintendedtoshowtheflexibilityofthisprotocoltoadapttocurrentandfutureplatform
designs.
V-10.4. Sample PCI Architectures V-106UEFI Platform Initialization Specification, Release 1.8
V-10.4.2 Desktop System with 1 PCI Root Bridge
The figure below shows an example of a PCI host bus with one PCI root bridge. This PCI root bridge produces one
PCI local bus that can contain PCI devices on the motherboard and/or PCI slots. This setup would be typical of a
desktop system. In this system, the PCI root bridge needs minimal setup. Typically, the PCI root bridge will decode
•The entire bus range on Segment 0
•The entire I/O space of the processor
•All the memory above the top of system memory
The firmware for this platform would produce the following:
•One instance of the PCI Host Bridge Resource Allocation Protocol
•One instance of PCI Root Bridge I/O Protocol
See the UEFI 2.1 Specification, Chapter 13, for details of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
Fig. 10.3: Desktop System with 1 PCI Root Bridge
V-10.4. Sample PCI Architectures V-107UEFI Platform Initialization Specification, Release 1.8
V-10.4.3 Server System with 4 PCI Root Bridges
ThefigurebelowshowsanexampleofalargerserverwithonePCIhostBuswithfourPCIrootbridges(RBs). ThePCI
devices that are attached to the PCI root bridges are all part of the same coherency domain, which means they share
•A common PCI I/O space
•A common PCI memory space
•A common PCI prefetchable memory space
As a result, each PCI root bridge must get resources out of a common pool. Each PCI root bridge produces one PCI
localbusthatcancontainPCIdevicesonthemotherboardorPCIslots. Thefirmwareforthisplatformwouldproduce
•Four instances of the PCI Root Bridge I/O Protocol
Fig. 10.4: Server System with 4 PCI Root Bridges
V-10.4. Sample PCI Architectures V-108UEFI Platform Initialization Specification, Release 1.8
V-10.4.4 Server System with 2 PCI Segments
The figure below shows an example of a server with one PCI host bus and two PCI root bridges (RBs). Each of these
PCI root bridges is on a different PCI segment, which allows the system to have up to 512 PCI buses. A single PCI
segment is limited to 256 PCI buses. These two segments do not share the same PCI configuration space, but they do
share the following, which is why they can be described with a single PCI host bus:
•Two instances of the PCI Root Bridge I/O Protocol
V-10.4.5 Server System with 2 PCI Host Buses
The figure below shows a server system with two PCI host buses and one PCI root bridge (RB) per PCI host bus. As
inServer System with 2 PCI Segments , this system supports up to 512 PCI buses, but the following resources are not
shared between the two PCI root bridges:
•PCI I/O space
•PCI memory space
•PCI prefetchable memory space
•Two instances of the PCI Host Bridge Resource Allocation Protocol
V-10.5 ISA Aliasing Considerations
ThePCIhostbridgedriverwillhandletheISAaliasaddressesbasedontheplatformpolicy. Theplatformcommunicates
the policy to the PCI host bridge driver using the EFI_PCI_PLATFORM_PROTOCOL . If the PCI host bridge driver
cannotlocateaninstanceofEFI_PCI_PLATFORM_PROTOCOL,itwillnotreservetheISAaliasaddresses. ThePCI
busdriverisnotawareofthispolicyandprobesdevicestogatherresourcerequirementsregardlessofthispolicy. The
EFI_PCI_PLATFORM_PROTOCOL is defined in PCI Platform Protocol .
Note: When it is started, a PCI device may request that the ISA alias ranges be forwarded to it
through the EFI_PCI_IO_PROTOCOL.Attributes() member function by setting the input parameter Attributes to
EFI_PCI_IO_ATTRIBUTE_ISA_IO. If the ISA alias I/O addresses are not reserved during enumeration, such a re-
quest may fail because one or more PCI devices may be occupying aliased addresses.
If the ISA alias I/O addresses are to be reserved during enumeration, the PCI host bridge driver is responsible for
allocating four times the amount of the requested I/O. The PCI bus driver obtains the resources by calling one of the
following member functions:
V-10.5. ISA Aliasing Considerations V-109UEFI Platform Initialization Specification, Release 1.8
Fig. 10.5: Server System with 2 PCI Segments
V-10.5. ISA Aliasing Considerations V-110UEFI Platform Initialization Specification, Release 1.8
Fig. 10.6: Server System with 2 PCI Host Buses
V-10.5. ISA Aliasing Considerations V-111UEFI Platform Initialization Specification, Release 1.8

•EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL .*GetProposedResources()*
•EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL .*Configuration()*
The PCI host bridge driver sets the _RNG bit to communicate the availability of the ISA alias range to the
PCI bus driver. If the _RNG flag is set, the PCI bus enumerator is not allowed to allocate the ISA alias
addresses to any PCI device. See Standard PCI Devices - Header Type 0 in the “Description” section of
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL for the definition of the _RNG flag. In this
case,aPCIdevice’srequesttoturnonaliasingwillsucceedbecauseoneormorePCIdevicesmaybeoccupyingaliased
addresses. The _RNG flag is the only aspect of the protocol interface structure that is affected by ISA aliasing.
V-10.6 Programming of Standard PCI Configuration Registers
ThistopicdefinesdesignguidelinesforprogrammingPCIconfigurationregistersinthestandardPCIheader. Itdefines
roles and responsibilities of various drivers.
Table 10.1: Standard PCI Devices - Header Type 0
PCI Configuration Register Bits Programmed By
PCIcommandregisterIOMemoryandBus
Master enablePCI bus driver This driver sets these values as requested by the de-
vice driver through the EFI_PCI_IO_PROTOCOL member func-
tions
PCI command register SERR PERR MWI
SpecialCycleEnableFastBacktoBackEn-
ableChipset platform specific code
PCI command register VGA palette snoop PCI device driver
Cache line size Chipset platform code to match the processor s cache line size or
some other value
Latency timer PCI bus driver This driver programs this register to default values
beforeitsendstheEfiPciBeforeResourceCollectionnotificationFor
PCIdevicesthisvalueis0x20PCIXdevicescomeoutofresetwith
thisregistersetto0x40ThePCIbusdriverdoesnotchangetheset-
ting The PCI bus driver will also make sure that the default value
for PCI devices is consistent with the MIN_LAT and MAX_LAT
registervaluesinthedevicesPCIconfigurationspaceChipsetplat-
form code can overwrite this register during the EfiPciBeforeRe-
sourceCollection notification call The new value may come from
theenduserusingconfigurationoptionsThedevicedrivermayover-
write this value during its own Start function
BIST PCI bus driver
Base address registers PCI bus driver
Interrupt line Not touched
Subsystem vendor ID and Device ID ChipsetplatformcodePerthePCISpecificationtheseregistersmust
get programmed before system software accesses the device Some
noncompliant or chipset devices may require that these registers be
programmed during the preboot phase
V-10.6. Programming of Standard PCI Configuration Registers V-112UEFI Platform Initialization Specification, Release 1.8
Table 10.2: PCI-to-PCI Bridge - Header Type 1
PCI command register - I/O,Memory, Bus
Master enable, VGApalette snoopPCI bus driver. This driver setsthese values as requested by
thedevice driver through theEFI_PCI_IO_PROTOCOL member-
PCI command register - SERR,PERR,
MWI, Fast Back to BackEnable, Special
Cycle EnableChipset/platform-specific code.
Cache line size Chipset/platform code to matchthe processor’s cache line sizeor
some other value.
Latency timer PCI bus driver. This driverprograms to default values beforeit
sends the*EfiPciBeforeResourceCollection*notification. For PCI
devices,this value is 0x20. PCI-X devicescome out of reset with
thisregister set to 0x40.The PCI busdriver does not change theset-
ting. ThePCIbusdriverwillalsomakesurethatthedefaultvaluefor
PCI devices isconsistent with the MIN_LAT andMAX_LAT regis-
ter values in thedevice’s PCI configuration space.Chipset/platform
codecanoverwritethisregisterduringtheEfiPciBeforeResourceCol-
lectionnotification call. The new valuemay come from the end user
usingconfiguration options.
Baseaddressesregisters,bus,I/O,andmem-
ory apertureregistersPCI bus driver.
Interrupt line Not touched.
Bridge control register - ISAEnable, VGA
EnablePCI bus driver. This driver setsthese values as requested by
Bridge control register - PERREnable,
SERR Enable, Fast Back toBack, Discard
TimersChipset/platform-specific code.
Bridge control register -Secondary Bus Re-
setPCIbusdriverispermittedtoresetthesecondarybusduringenumer-
ation. The chipset/platformcode may also reset the secondarybus
during the*EfiPciBeforeChildBusEnumeration*notification.
V-10.7 Sample Implementation
Typically, the PCI bus driver will enumerate and allocate resources to all devices for a PCI host bridge.
A sample algorithm for PCI enumeration is described below to clarify some of the finer points of the
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL . Actual implementations may vary. Calls to
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL .PreprocessController() are not included for
the sake of clarity.
Unless noted otherwise, all functions that are listed below are member functions of the
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
1. If the hardware supports dynamically changing the number of PCI root buses or changing the segment number
that is associated with a PCI root bus, such changes must be completed before the next steps.
2. The chipset/platform driver(s) creates a device handle for the PCI host bridges in the system(s) and installs an
instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL on that handle.
3. Thechipset/platformdriver(s)createsadevicehandleforeveryPCIrootbridgeandinstallsthefollowingonthat
handle:
•An instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
V-10.7. Sample Implementation V-113UEFI Platform Initialization Specification, Release 1.8
•An instance of EFI_DEVICE_PATH_PROTOCOL
It is expected that a single driver will handle a PCI host bridge, as well as all the asso-
ciated PCI root bridges. The ParentHandle field of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
must be initialized with the handle for the PCI host bridge that contains an instance of the
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL...Other initialization activities
take place.
4. The EFI_DRIVER_BINDING_PROTOCOL.Start() function of the PCI bus driver
is called and is passed the device handle of a PCI root bridge. The
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance that is associated with the
PCI root bridge can be found by using the ParentHandle field of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL must be present in PI Architecture
systems.
5. Begin the PCI enumeration process. The order in which the various member functions are called cannot be
changed. Between any two steps, there can be any amount of implementation-specific code as long as it does
notcallanymemberfunctionsofEFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.This
requirement is necessary to keep the state machines in the PCI host bridge allocation driver and the PCI bus
enumerator in sync.
6. NotifythehostbridgedriverthatPCIenumerationisabouttobeginbycalling NotifyPhase (EfiPciHostBridge-
BeginEnumeration ). Thismemberfunctionmustbethefirstonethatgetscalled. PCIenumerationhastwosteps:
bus enumeration and resource enumeration.
7. Notify the host bridge driver that bus enumeration is about to begin by calling NotifyPhase ( EfiPciHostBridge-
BeginBusAllocation ).
8. Do the following for every PCI root bridge handle:
•CallStartBusEnumeration (This,RootBridgeHandle ).
•Make sure each PCI root bridge handle supports the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
•Allocate memory to hold resource requirements. These resources can be two resource trees: one to hold bus
requirements and another to hold the I/O and memory requirements.
•CallGetAllocAttributes() to get the attributes of this PCI root bridge. This information is used to combine
different types of memory resources in the next step.
•Scan all the devices in the specified bus range and on the specified segment. If it is a PCI-to-PCI bridge,
update the bus numbers and program the bus number registers in the PCI-to-PCI bridge hardware. If it is
an ordinary device, collect the resource request and add up all of these requests in multiple pools (e.g., I/O,
32-bit prefetchable memory). Combine different types of memory requests at an appropriate level based
on the PCI root bridge attributes. Update the resource requirement information accordingly. On every
PCI root bridge, reserve space to cover the largest expansion ROMs on that bus, which will allow the PCI
bus driver to retrieve expansion ROMs from the PCI card or device without having to reprogram the PCI
host bridge. Because the memory and I/O resource collection step does not call any member function of
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL, it can be performed at a later time.
•OncethenumberofPCIbusesunderthisPCIrootbridgeisknown,call SetBusNumbers() withthisinformation.
9. NotifythehostbridgedriverthatthebusallocationphaseisoverbycallingNotifyPhase( EfiPciHostBridgeEnd-
BusAllocation ).
10. Notifythehostbridgedriverthatresourceallocationisabouttobeginbycalling NotifyPhase (EfiPciHostBridge-
BeginResourceAllocation ).

11. For every PCI root bridge handle, call SubmitResources() . The Configuration information is derived from the
resource requirements that were computed in step 8 above.
V-10.7. Sample Implementation V-114UEFI Platform Initialization Specification, Release 1.8
12. CallNotifyPhase (EfiPciHostBridgeAllocateResources ) to allocate the necessary resources. This call should
notbemadeunlessresourcerequirementsforallthePCIrootbridgeshavebeensubmitted. Ifthecallsucceeds,
go to next step. Otherwise, there are two options:
•Make do with the smaller ranges.
•CallGetProposedResources() to retrieve the proposed settings and examine the differences. Prioritize various
requests and drop lower-priority requests. Call NotifyPhase( EfiPciHostBridgeFreeResources ) to undo the pre-
viousallocation. Gobacktostep11withreducedrequirements,whichincludesresubmittingrequestsforallthe
root bridges.
13. CallNotifyPhase (EfiPciHostBridgeSetResources )toprogramthehardware. Atthispoint,thedecodelogicin
this host bridge is fully set up.
14. Do the following for every root bridge handle:
•Obtain the resource range that is assigned to a PCI root bridge by calling the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Configuration() member function on that handle.
•From the resource range that is assigned to the PCI root bridge, assign resources to all the devices. Program
the Base Address Registers (BARs) in all the PCI functions and decode registers in PCI-to-PCI bridges. If a
PCI device has a PCI option ROM, copy the contents to a buffer in memory. It is possible to defer the BAR
programming for a PCI controller until a connect request for the device is received.
•Create a device handle for each PCI device as required.
•Install an instance of EFI_PCI_IO_PROTOCOL and EFI_DEVICE_PATH_PROTOCOL on each of these han-
dles.
15. Notify the host bridge driver that resource allocation is complete by calling NotifyPhase( EfiPciHostBridgeEn-
dResourceAllocation ).
16. Deallocate any temporary buffers.
Looping on PCI root bridges is accomplished with the following algorithm:
RootBridgeHandle = NULL;
while(GetNextRootBridge(RootBridgeHandle) == EFI_SUCCESS) {
. . .
V-10.7.1 PCI enumeration process
2. The PCI host bridge driver (s) creates a device handle for the PCI host bridges in the system(s) and installs an
3. ThePCIrootbridgedriver(s)createsadevicehandleforeveryPCIrootbridgeandinstallsthefollowingonthat
handle:
It is expected that a single driver will handle a PCI host bridge, as well as all the associated PCI root bridges. The
ParentHandle field ofEFI_PCI_ROOT_BRIDGE_IO_PROTOCOL must be initialized with the handle for the PCI
host bridge that contains an instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL .
V-10.7. Sample Implementation V-115UEFI Platform Initialization Specification, Release 1.8
V-10.7.1.1 Other initialization activities take place.
PCI root bridge can be found by using the ParentHandle field of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL .
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL must be present.
not call any member functions of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL . This
6. Notify drivers that PCI enumeration is about to begin using EfiPciHostBridgeBeginenumeration .
V-10.7.1.2 PCI enumeration has two steps: bus enumerationand resource enumeration.
7. Notify drivers that PCI bus enumeration is about to begin using EfiPciHostBridgeBeginBusAllocation.
•Make sure each PCI root bridge handle supports the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL .
•Allocate memory to hold resource requirements.
•Scan all the devices in the specified bus range and on the specified segment.
If it is a PCI-to-PCI bridge, update the bus numbers and program the bus number registers in the PCI-to-PCI bridge
hardware. Call the drivers for preprocess notifications using EfiPciBeforeChildBusEnumeration.
If it is an ordinary device, collect the resource request and add up all of these requests in multiple pools (e.g., I/O,
32-bit prefetchable memory). Combine different types of memory requests at an appropriate level based on the PCI
root bridge attributes. Update the resource requirement information accordingly.
On every PCI root bridge, reserve space to cover the largest expansion ROMs on that bus, which will allow
the PCI bus driver to retrieve expansion ROMs from the PCI card or device without having to reprogram the
PCI host bridge. Because the memory and I/O resource collection step does not call any member function of
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL , it can be performed at a later time.
9. Notify drivers that the bus allocation phase is over using EfiPciHostBridgeEndBusAllocation .
10. Notify drivers that resource allocation is about to begin using EfiPciHostBridgeBeginResourceAllocation .
11. For every PCI root bridge handle, call SubmitResources() . TheConfiguration information is derived from the
12. Notifythedriverstoallocatethenecessaryresourcesusing EfiPciHostBridgeAllocateResources . Thiscallshould
requests and drop lower-priority requests. Notify the drivers using EfiPciHostBridgeFreeResources to undo the
V-10.7. Sample Implementation V-116UEFI Platform Initialization Specification, Release 1.8
previousallocation. Gobacktostep11withreducedrequirements,whichincludesresubmittingrequestsforall
the root bridges.
13. Notifythedriversusing EfiPciHostBridgeSetResources toprogramthehardware. Atthispoint,thedecodelogic
in this host bridge is fully set up.
•Install an instance of EFI_PCI_IO_PROTOCOL andEFI_DEVICE_PATH_PROTOCOL on each of these han-
dles.
15. Notify the drivers that resource allocation is complete by using EfiPciHostBridgeEndResourceAllocation .
16. Notify the drivers that bus enumeration is complete by calling EfiPciHostBridgeEndEnumeration .
17. Deallocate any temporary buffers.
18. Install the EFI_PCI_ENUMERATION_COMPLETE_GUID protocol.
V-10.7.1.3 Sample PCI Device Set Up Implementation
This section describes further the outlines of the process in step 14, second bullet (above).
1. Call the PCI enumeration preprocess functions using EfiPciBeforeResourceCollection .
2. Gather PCI device resource requirements.
3. Ifpresent,call EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL toseeifthereisanalternateset
of resources for this device.
4. Callthe EFI_PCI_PLATFORM_PROTOCOL functionGetPciRom() . IfitreturnsEFI_SUCCESS,gotostep7.
5. Call the EFI_PCI_OVERRIDE_PROTOCOL functionGetPciRom() . If it returns EFI_SUCCESS, go to step 7.
6. Find the PCI device’s option ROM and copy its contents into memory. If there is no option ROM, go to step 8.
7. Find and decompress the UEFI image within the option ROM image.
8. Exit
V-10.7.2 Sample Enumeration Implementation

8. Exit
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL . Actual implementations may vary.
V-10.7. Sample Implementation V-117UEFI Platform Initialization Specification, Release 1.8
V-10.7.2.1 PCI Enumeration Phases
There are several phases of the PCI enumeration process. For each phase, the PCI platform drivers and the PCI host
bridge drivers are notified as follows:
1. ThePlatformNotify() functionofthe EFI_PCI_PLATFORM_PROTOCOL iscalledwiththeenumerationphase
and the execution phase BeforePciHostBridge.
2. ThePlatformNotify() function of the EFI_PCI_OVERRIDE_PROTOCOL is called with the enumeration phase
3. TheNotifyPhasefunctionofeachinstanceofthe EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
is called with the enumeration phase.
4. ThePlatformNotify() functionofthe EFI_PCI_PLATFORM_PROTOCOL iscalledwiththeenumerationphase
and the execution phase AfterPciHostBridge.
5. ThePlatformNotify () function of the EFI_PCI_OVERRIDE_PROTOCOL is called with the execution phase
AfterPciHostBridge.
V-10.7.2.2 Additional locations to preprocess PCI devices
There are a few additional places during the PCI enumeration process where the platform or PCI host bridge drivers
are given the opportunity to preprocess individual PCI devices.
1. ThePlatformPrepController function of the EFI_PCI_PLATFORM_PROTOCOL is called with the preprocess
phase and the execution phase of BeforePciHostBridge.
2. ThePlatformPrepController functionofeachinstanceofthe EFI_PCI_OVERRIDE_PROTOCOL iscalledwith
the preprocess phase and the execution phase of BeforePciHostBridge.
3. ThePreprocessController functionofeachinstanceofthe EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
is called with the preprocess phase.
4. ThePlatformPrepController functionofeachinstanceofthe EFI_PCI_PLATFORM_PROTOCOL iscalledwith
the preprocess phase and the execution phase of AfterPciHostBridge.
5. ThePlatformPrepController function of the EFI_PCI_OVERRIDE_PROTOCOL is called with the preprocess
phase and the execution phase of AfterPciHostBridge .
V-10.8 PCI HostBridge Code Definitions
V-10.8.1 Introduction
This section contains the basic definitions of the PCI Host Bridge Resource Allocation Protocol. This section defines
the protocol EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
•EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE
•EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES
•EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE
V-10.8. PCI HostBridge Code Definitions V-118UEFI Platform Initialization Specification, Release 1.8
V-10.8.2 PCI Host Bridge Resource Allocation Protocol
V-10.8.3 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
Summary
Provides the basic interfaces to abstract a PCI host bridge resource allocation.
Note:This protocol is mandatory if the system includes PCI devices.
GUID
#define EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GUID \
{
0xCF8034BE,0x6768,0x4d8b,0xB7,0x39,0x7C,0xCE,0x68,0x3A,0x9F,0xBE
}
typedef struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL {
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE
NotifyPhase;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE
GetNextRootBridge;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES
GetAllocAttributes;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION
StartBusEnumeration;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS
SetBusNumbers;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES
SubmitResources;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES
GetProposedResources;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER
PreprocessController;
} EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL;
The notification from the PCI bus enumerator that it is about to enter a certain phase during the enumeration
process. See the NotifyPhase() function description.
GetNextRootBridge
RetrievesthedevicehandleforthenextPCIrootbridgethatisproducedbythehostbridgetowhichthisinstance
of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached. See the GetNext-
RootBridge() function description. See Terms Used in this Document for a definition of a PCI root bridge.
GetAllocAttributes
Retrievestheallocation-relatedattributesofaPCIrootbridge. Seethe GetAllocAttributes() functiondescription.
StartBusEnumeration
Sets up a PCI root bridge for bus enumeration. See the StartBusEnumeration() function description.
V-10.8. PCI HostBridge Code Definitions V-119UEFI Platform Initialization Specification, Release 1.8
SetBusNumbers
SetsupthePCIrootbridgesothatitdecodesaspecificrangeofbusnumbers. Seethe SetBusNumbers() function
SubmitResources
Submits the resource requirements for the specified PCI root bridge. See the SubmitResources() function de-
GetProposedResources
Returns the proposed resource assignment for the specified PCI root bridges. See the GetProposedResources()
PreprocessController
ProvideshooksfromthePCIbusdrivertoeveryPCIcontroller(device/function)atvariousstagesofthePCIenu-
merationprocessthatallowthehostbridgedrivertopreinitializeindividualPCIcontrollersbeforeenumeration.
See thePreprocessController() function description.
The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL provides the basic resource allocation
services to the PCI bus driver. There is one EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
instance for each PCI host bridge in a system. The following will typically have only one PCI host bridge:
•Embedded systems
•Desktops
•Workstations
•Most servers
High-end servers may have multiple PCI host bridges. A PCI bus driver that wishes to manage a PCI bus in
a system will have to retrieve the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance
that is associated with the PCI bus to be managed. A device handle for a PCI host bridge will not contain an
EFI_DEVICE_PATH_PROTOCOL instance because the PCI host bridge is a software abstraction and has no equiva-
lent in the ACPI name space.
All applicable member functions use ACPI 2.0 or ACPI 3.0 resource descriptors to describe resources. Using ACPI
resource descriptors does the following:
•Allows other types of resources to be described in the future because they are very generic in nature.
•Avoids multiple structure definitions for describing resources.
•Maintains compatibility with the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL definition.
Only the following two resource descriptor types from the ACPI Specification may be used to describe the current
resources that are allocated to a PCI root bridge:
•QWORD Address Space Descriptor ( ACPI 3.0 )
•End Tag ( ACPI 3.0)
The QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic or fixed re-
sources. The configuration of a PCI root bridge is described with one or more QWORD Address Space Descriptors,
followedbyanEndTag. ACPI2.0&3.0QWORDAddressSpaceDescriptorUsage andACPI2.0&3.0EndTagUsage
below contain these two descriptor types. I/O Resource Flag (Resource Type = 1) Usage andMemory Resource Flag
(Resource Type = 0) Usage define how resource-specific flags are used. See the ACPI Specification for details on the
field values.
V-10.8. PCI HostBridge Code Definitions V-120UEFI Platform Initialization Specification, Release 1.8
Table 10.3: ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage
0x01 0x02 0x2B Length of this descriptor in bytes not including the first two fields
0x03 0x01 Resource type 0 Memory range 1 I O range 2 Bus number range
0x04 0x01 General flags Flags that are common to all resource types Bits 7 4
Reservedmustbe0Bit3_MAFAlwaysreturnedas1whilereturn-
ing allocated requests to indicate that the specified max address is
fixedBit2_MIFAlwaysreturnedas1whilereturningallocatedre-
queststoindicatethatthespecifiedminaddressisfixedBit1_DEC
Ignored Bit 0 Ignored
0x05 0x01 Type specific flags Ignored
0x06 0x08 Address Space Granularity Used to differentiate between a 32 bit
memory request and a 64 bit memory request For a 32 bit memory
requestthisfieldshouldbesetto32Fora64bitmemoryrequestthis
field should be set to 64 Ignored for I O and bus resource requests
Ignored during GetPropo sedResources
0x0E 0x08 Address Range Minimum Set to the base of the allocated address
range bus I O memory during GetPropo sedResources Ignored dur-
ing Sub mitResources
0x16 0x08 AddressRangeMaximumUsedtoindicatetheBARIndexfrom0to

6 where 6 is the Option Rom BAR Specially UINT64 1 in this field
meansallthePCIBARsonthedeviceexcepttheOptionRomBAR
0x1E 0x08 Address Translation Offset Used to indicate alignment require-
ment during Su bmitResources and ignored during GetPropo se-
dResources This value must be 2n 1 The address base must be a
multiple of the granularity field That is if this field is 4KiB 1 the
allocated address must be a multiple of 4 KiB Note The interpreta-
tionofthisfieldforPlatformInitializationisdifferentfromtheACPI
Specification and PCI Root Bridge I O Protocol
0x26 0x08 Address Range Length This field specifies the amount of resources
that are requested or allocated in number of bytes
Table 10.4: ACPI 2.0 & 3.0 End Tag Usage
Byte Offset Byte Length DataDescription
0x00 0x01 0x79End Tag.
0x01 0x01 0x00Checksum. Set to 0 toindicate thatchecksum is tobe ignored.
Table 10.5: I/O Resource Flag (Resource Type = 1) Usage
Bits Meaning
Bits[7:1] Ignored.
Bit[0] _RNG. Ignored during anallocation request. Setting thisbit while returning allocate-
dresources means that the I/Oallocation must be limited to theISA I/O ranges. In that case,
thePCI bus driver must allocate I/Oaddresses out of the ISA I/Oranges. The following are
theSAI/Oranges:n100-n3FFn500-n7FFn900-nBFFnD00-nFFFSeeISAAliasingConsider-
ationsfor more details.
V-10.8. PCI HostBridge Code Definitions V-121UEFI Platform Initialization Specification, Release 1.8
Table 10.6: Memory Resource Flag (Resource Type = 0) Usage
Bits[7:3] Ignored.
Bit[2:1]
_MEM. Memory attributes.| Value and Meaning:| 0 The memory is nonprefetchable.| 1
Invalid.| 2 Invalid.| 3 The memory is prefetchable.Note: The interpretation of thesebits is
somewhat different fromthe ACPI Specification. Accordingto the ACPI Specification,
avalue of 0 implies noncacheablememory and the value of 3indicates prefetchable
andcacheable memory.
Bit[0] Ignored.
V-10.8.4 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.NotifyPhase()
Summary
These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI enumeration
process.
Prototype
typedef
(EFIAPI
*EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE)
(
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
);
This
Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
Phase
The phase during enumeration. Type EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE is de-
fined in “Related Definitions” below.
This member function can be used to notify the host bridge driver to perform specific actions, including any chipset-
specific initialization, so that the chipset is ready to enter the next phase. Nine notification points are defined at this
time. See “Related Definitions” below for definitions of various notification points and Sample Implementation for
usage.
// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE
EfiPciHostBridgeBeginEnumeration,
EfiPciHostBridgeBeginBusAllocation,
V-10.8. PCI HostBridge Code Definitions V-122UEFI Platform Initialization Specification, Release 1.8
EfiPciHostBridgeEndBusAllocation,
EfiPciHostBridgeBeginResourceAllocation,
EfiPciHostBridgeAllocateResources,
EfiPciHostBridgeSetResources,
EfiPciHostBridgeFreeResources,
EfiPciHostBridgeEndResourceAllocation,
EfiPciHostBridgeEndEnumeration,
EfiMaxPciHostBridgeEnumeratonPhase
} EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE;
Enumeration Descriptions provides a description of the fields in the above enumeration:
Table 10.7: Enumeration Descriptions
Enumeration Description
EfiPciHostBridgeBeginEnumeration ResetsthehostbridgePCIaperturesandinternaldatastructuresThe
PCIenumeratorshouldissuethisnotificationbeforestartingafresh
enumeration process Enumeration cannot be restarted after sending
any other notification such as Ef iPciHostBridgeBeginBusAlloca-
tion
Ef iPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin No specific action is re-
quiredhereThisnotificationcanbeusedtoperformanychipsetspe-
cific programming
EfiPciHostBridgeEndBusAllocation ThebusallocationandbusprogrammingphaseiscompleteNospe-
cificactionisrequiredhereThisnotificationcanbeusedtoperform
EfiPciHostBridgeBeginResourceAllocation TheresourceallocationphaseisabouttobeginNospecificactionis
required here This notification can be used to perform any chipset
specific programming
V-10.8. PCI HostBridge Code Definitions V-123UEFI Platform Initialization Specification, Release 1.8
Table 10.7 – continued from previous page
E fiPciHostBridgeAllocateResources AllocatesresourcesperpreviouslysubmittedrequestsforallthePCI
root bridges These resource settings are returned on the next call
to GetProposedResources Before calling NotifyPhase with a Phase
ofEfiPciHostBridgeAllocateResourcethePCIbusenumeratorisre-
sponsibleforgatheringIOandmemoryrequestsforallthePCIroot
bridges and submitting these requests using SubmitResources This
function pads the resource amount to suit the root bridge hardware
takescareofdependenciesbetweenthePCIrootbridgesandcallsthe
Global Coherency Domain GCD with the allocation request In the
case of padding the allocated range could be bigger than what was
requested Note that the size of the allocated range could be smaller
thanwhatwasrequestedThisscenariocouldhappenduetoanallo-
cation failure a host bridge hardware limitation or any other reason
InthatcasethecallwillreturnanEFI_OUT_OF_RESOURCESer-
ror If the allocated windows are smaller than what was requested
the PCI bus enumerator may not be able to fit all the devices within
the range The PCI bus driver can call GetProposedResouces to find
outwhichoftheresourcetypeswerepartiallyallocatedandthedif-
ferencebetweentheamountthatwasrequestedandtheamountthat
wasallocatedThePCIbusenumeratorshouldreadjusttherequested
sizesbydroppingcertainPCIdevicesorPCIbusestoobtainabestfit
The PCI bus driver can call NotifyPhase EfiPciHostBridgeFreeRe-
sourcestofreeuptheoriginalassignmentsandresubmittheadjusted
resource requests with SubmitResources
EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
resources proposed resources for all the PCI root bridges After the
hardwareisprogrammedreassigningresourceswillnotbesupported
The bus settings are not affected
EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
root bridges and resets the I O and memory apertures to their ini-
tial state The bus settings are not affected If the request to allocate
resources fails the PCI enumerator can use this notification to deal-
locate previous resources adjust the requests and retry allocation
EfiPc iHostBridgeEndResourceAllocation TheresourceallocationphaseiscompletedNospecificactionisre-
E fiPciHostBridgeEndBusEnumeration The bus enumeration phase is completed No specific action is re-
EFI_INVALID_PARAMETER ThePhaseis invalid.
EFI_NOT_READY This phase cannot be entered at this time.For example, this er-
ror is valid for a*Phase* ofEfiPciHostBridgeAllocateResources
if*SubmitResources()*hasnotbeencalledforoneormorePCIroot
bridges before thiscall.
EFI_DEVICE_ERROR Programmingfailedduetoahardwareerror.Thiserrorisvalidfora
PhaseofEfiPciHostBridgeSetResources.
V-10.8. PCI HostBridge Code Definitions V-124UEFI Platform Initialization Specification, Release 1.8
Table 10.8 – continued from previous page
EFI_OUT_OF_RESOURCES The request could not be completed due to alack of resources. This
error is valid fora Phase ofEfiPciHostBridgeAllocateResources if
thepreviouslysubmittedresourcerequestscannotbefulfilledorwere
only partiallyfulfilled.
V-10.8.5 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.GetNextRootBridge()
Summary
Returns the device handle of the next PCI root bridge that is associated with this host bridge.
Prototype
typedef
(EFIAPI
*EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE) (
IN OUT EFI_HANDLE *RootBridgeHandle
);
This
RootBridgeHandle
ReturnsthedevicehandleofthenextPCIrootbridge. Oninput,itholdstheRootBridgeHandlethatwasreturned
by the most recent call to GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle for the

Summary
Prototype
typedef
(EFIAPI
);
This
first PCI root bridge is returned. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.1
This function is called multiple times to retrieve the device handles of all the PCI root bridges that are associ-
ated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI root bridges. On each
call, the handle that was returned by the previous call is passed into the interface, and on output the interface re-
turns the device handle of the next PCI root bridge. The caller can use the handle to obtain the instance of the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no more PCI root bridges to re-
port, the interface returns EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order
that they are returned by this function.
The search is initiated by passing in a NULL device handle as input. Some of the member functions of the
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL operate on a PCI root bridge and expect the
RootBridgeHandle as an input.
There is no requirement that this function return the root bridges in any specific relation with the EFI device paths of
This function can also be used to determine the number of PCI root bridges that were produced by this PCI host
bridge. The host bridge hardware may provide mechanisms to change the number of root bridges that it produces, but
such changes must be completed before the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
is installed.
V-10.8. PCI HostBridge Code Definitions V-125UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The requested attribute information was returned
EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was returned on a
previous call to GetNextRootBridge
EFI_NOT_FOUND There are no more PCI root bridge device handles
V-10.8.6 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.GetAllocAttributes()
Summary
Returns the allocation attributes of a PCI root bridge.
Prototype
typedef
(EFIAPI \*
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_GET_ATTRIBUTES) (
IN EFI_HANDLE RootBridgeHandle,
);
This
The device handle of the PCI root bridge in which the caller is interested. Type EFI_HANDLE is defined in
InstallProtocolInterface() in the UEFI 2.1 Specification.
The pointer to attributes of the PCI root bridge. The permitted attribute values are defined in “Related Defini-
The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary from one PCI
root bridge to another. These attributes are different from the decode-related attributes that are returned by the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The RootBridgeHandle parameter is
used to specify the instance of the PCI root bridge. The device handles of all the root bridges that are associated with
thishostbridgemustbeobtainedbycalling GetNextRootBridge() . Theattributesarestaticinthesensethattheydonot
changeduringoraftertheenumerationprocess. Thehardwaremayprovidemechanismstochangetheattributesonthe
fly,butsuchchangesmustbecompletedbefore EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
is installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are de-
finedin“RelatedDefinitions”below. Thecallerusestheseattributestocombinemultipleresourcerequests. Forexam-
ple, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to include
requests for the prefetchable memory in the nonprefetchable memory pool and not request any prefetchable memory.
// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES
V-10.8. PCI HostBridge Code Definitions V-126UEFI Platform Initialization Specification, Release 1.8
#define EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM 1
#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2
Following is a description of the fields in the above definition:
Table10.9: EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTESfield
descriptions
EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set then the PCI root bridge does not sup-
portseparatewindowsfornonprefetchableandprefetch-
ablememoryAPCIbusdriverneedstoincluderequests
forprefetchablememoryinthenonprefetchablememory
pool
EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set then the PCI root bridge supports 64 bit
memorywindowsIfthisbitisnotsetthePCIbusdriver
needstoincluderequestsfora64bitmemoryaddressin
the corresponding 32 bit memory pool
EFI_SUCCESS The requested attribute information was returned.
EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
EFI_INVALID_PARAMETER Attributes is NULL.
V-10.8.7 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.StartBusEnumeration()
Summary
Sets up the specified PCI root bridge for the bus enumeration process.
Prototype
typedef
(EFIAPI
*EFI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION) (
OUT VOID **Configuration
);
This
The PCI root bridge to be set up. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.1
Configuration
Pointer to the pointer to the PCI bus resource descriptor.
V-10.8. PCI HostBridge Code Definitions V-127UEFI Platform Initialization Specification, Release 1.8
ThismemberfunctionsetsuptherootbridgeforbusenumerationandreturnsthePCIbusrangeoverwhichthesearch
should be performed in ACPI (2.0 & 3.0) resource descriptor format. The following table lists the fields in the ACPI
(2.0 & 3.0) resource descriptor that are set for StartBusEnumeration().
Table 10.10: ACPI 2.0 & 3.0 Resource Descriptor FieldValues for
StartBusEnumeration()
Field Setting
Address Range Minimum Set to the lowest bus number to be scanned
Address Range Length Set to the number of PCI buses that may be scanned The highest bus number is
computed by adding the length to the lowest bus number and subtracting 1
Address Range Maximum Ignored
All other fields Ignored
Note:Seethe“Description”sectionofthePCIHostBridgeResourceAllocationProtocoldefinitionforadescription
of these ACPI resource descriptor fields.
This function cannot return resource descriptors for anything other than bus resources. This function can be used
to prevent a PCI bus driver from scanning certain PCI buses to work around a chipset limitation. Because the size
of ACPI resource descriptors is not fixed, StartBusEnumeration() is responsible for allocating memory for the buffer
Configuration.
The PCI segment is implicit and is identified by the SegmentNumber field in the instance of the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL that is installed on the PCI root bridge handle RootBridgeHandle.
EFI_SUCCESS The PCI root bridge was set up and the bus range was returned in
EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle
EFI_DEVICE_ERROR Programming failed due to a hardware error
V-10.8.8 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SetBusNumbers()
Summary
Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
Prototype
typedef
(EFIAPI
*EFI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS) (
IN VOID *Configuration
);
This
V-10.8. PCI HostBridge Code Definitions V-128UEFI Platform Initialization Specification, Release 1.8
ThePCIrootbridgewhosebusrangeistobeprogrammed. TypeEFI_HANDLEisdefinedinInstallProtocolIn-
terface() in the UEFI 2.1 Specification.
The pointer to the PCI bus resource descriptor.
This member function programs the specified PCI root bridge to decode the bus range that is specified by the input
parameter Configuration.
ThebusrangeinformationisspecifiedintermsoftheACPI(2.0&3.0)resourcedescriptorformat. Thefollowingtable
lists the fields in the ACPI (2.0 & 3.0) resource descriptor that are set for SetBusNumbers().
Table 10.11: ACPI 2.0 & 3.0 Resource Descriptor FieldValues for
SetBusNumbers()
Address Range Minimum Set to the lowest bus number to be decoded
Address Range Length SettothenumberofPCIbusesthatshouldbedecodedThehighestbusnumber

);
This
is computed by adding the length to the lowest bus number and subtracting 1
This call will return EFI_INVALID_PARAMETER without programming the hardware if either of the following are
specified:
•Any descriptors other than bus type descriptors
•Any invalid descriptors
Thebusrangeistypicallyasubsetofwhatwasreturnedduring StartBusEnumeration() . IfSetBusNumbers()iscalled
with incorrect (but valid) parameters, it may cause system failure.
This call cannot alter the following:
•The SegmentNumber field in the corresponding instances of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
•The segment number settings in the hardware
The caller is responsible for allocating and deallocating a buffer to hold Configuration. If the call returns
EFI_DEVICE_ERROR, the PCI bus enumerator can optionally attempt another bus setting.
V-10.8. PCI HostBridge Code Definitions V-129UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The bus range for the PCI root bridge was programmed
EFI_INVALID_PARAMETER Configuration is NULL
EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2 0 3 0 resource de-
scriptor
EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2 0 bus resource de-
scriptor
EFI_INVALID_PARAMETER ConfigurationincludesvalidACPI2030resourcedescriptorsother
than bus descriptors
EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descrip-
tors
EFI_INVALID_PARAMETER Address Range Minimum is invalid for this root bridge
EFI_INVALID_PARAMETER Address Range Length is invalid for this root bridge
V-10.8.9 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SubmitResources()
Summary
Submits the I/O and memory resource requirements for the specified PCI root bridge.
Prototype
typedef
(EFIAPI *
EFI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES) (
);
This
ThePCIrootbridgewhoseI/Oandmemoryresourcerequirementsarebeingsubmitted. TypeEFI_HANDLEis
defined in InstallProtocolInterface() in the UEFI 2.1 Specification.
The pointer to the PCI I/O and PCI memory resource descriptor.
This function is used to submit all the I/O and memory resources that are required by the specified PCI root bridge.
The input parameter Configuration is used to specify the following:
•The various types of resources that are required
•The associated lengths in terms of ACPI (2.0 & 3.0) resource descriptor format
The following table lists the fields in the ACPI (2.0 & 3.0) resource descriptor that are set for SubmitResources().
V-10.8. PCI HostBridge Code Definitions V-130UEFI Platform Initialization Specification, Release 1.8
Table 10.12: ACPI 2.0& 3.0 Resource Descriptor FieldValues for
SubmitResources()
Address Range Length Set to the size of the aperture that is requested
Address Space Granularity Used to differentiate between a 32 bit memory request and a 64 bit memory re-
quest For a 32 bit memory request this field should be set to 32 For a 64 bit
memoryrequestthisfieldshouldbesetto64Allothervaluesresultinthisfunc-
tion returning the error code of EFI_INVALID_PARAMETER
Address Range Maximum Used to specify the alignment requirement If Address Range Maxi-
mum is of the form 2n 1 this member function returns the error code
EFI_INVALID_PARAMETERTheaddressbasemustbeamultipleofthegran-
ularityfieldThatisifthisfieldis4KiB1theallocatedaddressmustbeamultiple
of 4 KiB
Address Range Minimum Ignored
Address Translation Offset Ignored
Thecallermustaskforappropriatealignmentusingthe“AddressRangeMaximum”field. Thecallerisresponsiblefor
allocating and deallocating a buffer to hold Configuration.
ItisconsideredanerrorifnoresourcerequestsaresubmittedforaPCIrootbridge. IfaPCIrootbridgedoesnotrequire
any resources, a zero-length resource request must explicitly be submitted.
IftheConfigurationincludesoneormoreinvalidresourcedescriptors,alltheresourcedescriptorsareignoredandthe
function returns EFI_INVALID_PARAMETER.
EFI_SUCCESS The I O and memory resource requests for a PCI root bridge were
accepted
scriptor
EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that
arenotsupportedbythisPCIrootbridgeThiserrorwillhappenifthe
caller did not combine resources according to Attributes that were
returned by GetAllocAttributes
EFI_INVALID_PARAMETER Address Range Maximum is invalid
EFI_INVALID_PARAMETER Address Range Length is invalid for this PCI root bridge
EFI_INVALID_PARAMETER Address Space Granularity is invalid for this PCI root bridge
V-10.8. PCI HostBridge Code Definitions V-131UEFI Platform Initialization Specification, Release 1.8
V-10.8.10 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.GetProposedResources()
Summary
Returns the proposed resource settings for the specified PCI root bridge.
Prototype
typedef
(EFIAPI *
EFI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES) (
);
This
ThePCIrootbridgehandle. TypeEFI_HANDLEisdefinedinInstallProtocolInterface()inthe UEFI2.1Spec-
The pointer to the pointer to the PCI I/O and memory resource descriptor.
ThismemberfunctionreturnstheproposedresourcesettingsforthespecifiedPCIrootbridge. Theproposedresource
settings are prepared when NotifyPhase() is called with a PhaseofEfiPciHostBridgeAllocateResources. The output
parameter Configuration specifies the following:
•The various types of resources, excluding bus resources, that are allocated
ThefollowingtableliststhefieldsintheACPI(2.0&3.0)resourcedescriptorthataresetfor GetProposedResources()
.
Table10.14: ACPI2.0&3.0GetProposedResources()ResourceDescrip-
tor Field Values
Address Space Granularity Ignored
Address Range Minimum Indicates the starting address of the allocated ranges
Address Translation Offset IndicatestheallocationstatusAllocationstatusisdefinedinRelated
Definitions below
V-10.8. PCI HostBridge Code Definitions V-132UEFI Platform Initialization Specification, Release 1.8
The callee is responsible for allocating a buffer to hold Configuration because the caller does not know the number of
descriptors that are required. The caller is also responsible for deallocating the buffer.
If NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResources and returns
EFI_OUT_OF_RESOURCES, the PCI bus enumerator may use GetProposedResources() to retrieve the pro-
posed settings. The EFI_OUT_OF_RESOURCES error status indicates that one or more requests could not be
fulfilledorwerepartiallyfulfilled. Additionaldetailsoftheallocationstatusforeachtypeofresourcecanberetrieved
from the “Address Translation Offset” field in the resource descriptor that was returned by this function; also see
“Related Definitions” below for defined allocation status values. This error could happen for the following reasons:
•Allocation failure
•A limitation in the host bridge hardware
•Any other reason
If the allocated windows are smaller than what was requested, the PCI bus enumerator may not be able to fit all the
deviceswithintherange. Inthatcase,thePCIbusenumeratormaychoosetoreadjusttherequestedsizes(bydropping
certain devices or PCI buses) to obtain a best fit. The PCI bus driver calls NotifyPhase() with a Phase of EfiPciHost-
BridgeFreeResources to free the original assignments.

Ifthismemberfunctionisabletoonlypartiallyfulfilltherequestsforoneormoreresourcetypes,therootbridgesthat
are first in the list will get resources first. The ordering of the root bridges is determined by the output of GetNext-
RootBridge() . The handle to the first root bridge is obtained by calling GetNextRootBridge() with an input handle of
NULL.
In the case of I/O resources, the PCI bus enumerator must check the _RNG flag. If this flag is set, the I/O ranges that
are allocated to the devices must come from the non-ISA I/O subset.
Forexample,ifthisflagisset,the“AddressRangeMinimum”is0x1000,andthe“AddressRangeLength”is0x1000,
then the following I/O ranges can be allocated to PCI devices:
•0x1000-0x10FF
•0x1400-0x14FF
•0x1800-0x18FF
•0x1C00-0x1CFF
This call is made before NotifyPhase() is called with a PhaseofEfiPciHostBridgeSetResources . After that time, the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Configuration() memberfunctionshouldbeusedtoobtaintheresources
that were consumed by a particular PCI root bridge.
//**************************************************************\*
// EFI_RESOURCE_ALLOCATION_STATUS
typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS;
#define EFI_RESOURCE_SATISFIED 0
#define EFI_RESOURCE_NOT_SATISFIED (UINT64) -1
Following is a description of the fields in the above definition. All other values indicate that the request of this re-
source type could be partially fulfilled. The exact value indicates how much more space is still required to fulfill the
requirement.
V-10.8. PCI HostBridge Code Definitions V-133UEFI Platform Initialization Specification, Release 1.8
Table 10.15: EFI_RESOURCE_ALLOCATION_STATUS fielddescrip-
tions
EFI_RESOURCE_SATISFIED The request of this resource type could be fulfilled
EFI_RESOURCE_NOT_SATISFIED Therequestofthisresourcetypecouldnotbefulfilledforitsabsence
in the host bridge resource pool
EFI_SUCCESS The requested parameters were returned
V-10.8.11 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.PreprocessController()
Summary
Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various stages of the PCI
enumeration process that allow the host bridge driver to preinitialize individual PCI controllers before enumeration.
Prototype
typedef
(EFIAPI *
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER) (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
);
This
The associated PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UE
FI 2.1 Specification.
PciAddress
The address of the PCI device on the PCI bus. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
structure is defined in the “Related Definitions” section below.
Phase
ThephaseofthePCIdeviceenumeration. Type EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE
ThisfunctioniscalledduringthePCIenumerationprocess. Nospecificactionisexpectedfromthismemberfunction.
It allows the host bridge driver to preinitialize individual PCI controllers before enumeration.
Theparameter RootBridgeHandle canbeusedtolocatetheinstanceofthe EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
thatisinstalledontherootbridgethatistheparentofthespecificPCIfunction. Theparameter PciAddress canbepassed
V-10.8. PCI HostBridge Code Definitions V-134UEFI Platform Initialization Specification, Release 1.8
to thePci.Read() andPci.Write() functions of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance to access the
PCI configuration space of the specific PCI function.
This member function is invoked during PCI enumeration and before the PCI enumerator has created a handle for the
PCI function. As a result, the EFI_PCI_IO_PROTOCOL cannot be used at this point.
Twonotificationpointsaredefinedatthistime. Seetype EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE
in “Related Definitions” below for definitions of these notification points and ISA Aliasing Considerations for usage.
// EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE
EfiPciBeforeChildBusEnumeration,
EfiPciBeforeResourceCollection
} EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE;
Following is a description of the fields in the above enumeration:
Table10.16: EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASEfield
EfiPciBeforeChildBusEnumeration This notification is applicable only to PCI to PCI bridges and in-
dicates that the PCI enumerator is about to begin enumerating the
bus behind the PCI to PCI bridge This notification is sent after the
primarybusnumberthesecondarybusnumberandthesubordinate
bus number registers in the PCI to PCI bridge are programmed to
valid but not necessary final values Programming of the bus num-
ber register allows the chipset code to scan devices on the bus that
are immediately behind the PCI to PCI bridge This notification can
be used to reset the secondary PCI bus Some PCI to PCI bridges
can drive their secondary bus at various clock speeds 33 MHz or
66 MHz for example and support PCI X or conventional PCI mode
Thesebridgesmustbesetuptooperateatthecorrectspeedandcor-
rectmodebeforethedownstreamdevicesandbusesareenumerated
ThisnotificationcanbeusedtoperformthatactivityThehostbridge
codecannotreprogramthebusnumbersinthePCItoPCIbridgeor
reprogramanyupstreamdevicesduringthisnotificationItcantouch
the downstream devices because the PCI enumerator has not found
these devices If there are multiple PCI to PCI bridges on the same
PCI bus the order in which the notification is sent to these bridges
is implementation specific On the other hand it is guaranteed that a
PCI to PCI bridge will see this notification before the downstream
bridgereceivesthisnotificationoritschilddevicesreceivetheEfiP-
ciBeforeResourceCollection notification
V-10.8. PCI HostBridge Code Definitions V-135UEFI Platform Initialization Specification, Release 1.8
Table 10.16 – continued from previous page
EfiPciBeforeResourceCollection This notification is sent before the PCI enumerator probes the Base
Address Register BAR registers for every valid PCI function This
notification can be used to program the backside registers that de-
termine the BAR size or any other programming such as the master
latencytimercachelinesizeandPERRandSERRcontrolThisnoti-
fication is sent regardless of whether the function implements BAR
or not In the case of a multifunction device this notification is sent
for every function of the device The order within the functions is
not specified The order in which this notification is sent to various
devices functions on the same bus is implementation specific
UINT8 Bus;
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS;
EFI_SUCCESS The requested parameters were returned.
EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE
EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator
should not enumerate this device, including its child devices if it is
a PCI-to-PCI bridge
V-10.9 End of PCI Enumeration Overview
This specification defines the indicia to inform the platform when the PCI enumeration process has completed. This
allows for some post enumeration finalization actions to occur, if necessary.
V-10.9.1 End of PCI Enumeration Protocol
The indicia for this finalization action is a protocol. The obligation of the platform that supports this capability is as
follows. Once PCI enumeration is complete, the EFI_PCI_ENUMERATION_PROTOCOL shall be installed on the
same handle as the host bridge protocol.
This protocol is always installed with a NULL pointer.
GUID
#define EFI_PCI_ENUMERATION_COMPLETE_GUID \
{ \
0x30cfe3e7, 0x3de1, 0x4586,
{ 0xbe, 0x20, 0xde, 0xab, 0xa1, 0xb3, 0xb7, 0x93 } \
}
V-10.9. End of PCI Enumeration Overview V-136UEFI Platform Initialization Specification, Release 1.8
The protocol can be used as an indicia by other DXE agents that the process of PCI device enumeration has been
completed.
V-10.9. End of PCI Enumeration Overview V-137CHAPTER
ELEVEN
PCI PLATFORM
V-11.1 Introduction
ThissectioncontainsthebasicdefinitionsofprotocolsthatprovidePCIplatformsupport. Thefollowingprotocolsare

GUID
{ \
}
ELEVEN
defined in this section:
EFI_PCI_PLATFORM_PROTOCOL
EFI_PCI_OVERRIDE_PROTOCOL
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
EFI_PCI EXECUTION_PHASE
EFI_PCI_PLATFORM_POLICY
V-11.2 PCI Platform Overview
This section defines the core code and services that are required for an implementation of the following protocols in
this specification:
•PCI Platform Protocol
•PCI Override Protocol
•Incompatible PCI Device Support Protocol
The PCI Platform Protocol allows a PCI bus driver to obtain the platform policy and call a platform driver at various
points in the enumeration phase. The Incompatible PCI Device Support Protocol allows a PCI bus driver to handle
resource allocation for some PCI devices that do not comply with the PCI Specification.
•Describes the basic components of the PCI Platform Protocol
•DescribesthebasiccomponentsoftheIncompatiblePCIDeviceSupportProtocolandhowfirmwareconfigures
incompatible PCI devices
V-138UEFI Platform Initialization Specification, Release 1.8
•Provides code definitions for the PCI Platform Protocol, the Incompatible PCI Device Support Protocol, and
their related type definitions that are architecturally required by this specification.
modify these products for use in IntelÆ architecture-based products.
•Operating system developers who will be adapting their shrink-wrapped operating system products to run on
Intel architecture-based platforms.
Readers of this specification are assumed to have solid knowledge of the UEFI 2.1 Specification.
V-11.3 PCI Platform Support Related Information
V-11.3.1 Industry Specifications
•Advanced Configuration and Power Interface Specification (hereafter referred to as the ACPI Specification),
version 3.0.
V-11.3.2 PCI Specifications
•Conventional PCI Specification, version 3.0: http://www.pcisig.com*
•PCI-to-PCI Bridge Architecture Specification, revision 1.2: http://www.pcisig.com*
•PCI-to-PCI Bridges and CardBus Controllers on Windows 2000, Windows XP, and Windows Server 2003:
http://www.microsoft.com/whdc/system/bus/PCI/pcibridge-cardbus.mspx*
V-11.4 PCI Platform Protocol
V-11.4.1 PCI Platform Protocol Overview
“PCIHostBridgeResourceAllocationProtocol”,SectionV-10.3definesanddescribesthePCIHostBridgeResource
AllocationProtocol. ThePCIHostBridgeResourceAllocationProtocoldriverprovideschipset-specificfunctionality
thatworksacrossprocessorarchitecturesanduniqueplatformfeatures. Itdoesnotaddressissueswhereanimplemen-
tation varies across platforms.
Incontrast,thePCIOverrideProtocolandPCIPlatformProtocolprovideinterfacesallowaplatformdriverorcodebase
driver to perform platform-specific actions. For example:
•AllowaPCIbusdrivertoobtainplatformpolicy. TheplatformcanusethisprotocoltocontrolwhetherthePCI
bus driver reserves I/O ranges for ISA aliases and VGA aliases. The default policy for the PCI bus driver is to
reserveI/OrangesforbothISAaliasesandVGAaliases,whichmayresultinalargeamountofI/Ospacebeing
unavailable for PCI devices. This protocol allows the platform driver to change this policy.
•Call a platform driver at various points in the enumeration phase. The platform driver can use these hooks
to perform various platform-specific activities. Examples of such activities include but are not limited to the
•PlatformPrepController() canbeusedtoprogramthePCIsubsystemvendorIDanddeviceIDintoonboardand
chipset devices.
V-11.3. PCI Platform Support Related Information V-139UEFI Platform Initialization Specification, Release 1.8
•PlatformPrepController() and PlatformNotify() can be used for implementing hardware workarounds.
•PlatformPrepController() can be used for preprogramming any backside registers that control the Base Address
Register (BAR) window sizes.
•PlatformPrepController()canbeusedtosetPCIorPCI-X*busspeedsforPCIbridgesthatsupportmultiplebus
speeds.
•AllowPCIoptionROMstobestoredinlocalstorage. TheplatformcanstorePCIoptionROMsinlocalstorage
(e.g.,afirmwarevolume)andreporttheirexistencetothePCIbusdriverusingthe GetPciRom() memberfunction.
Option ROMs for embedded PCI controllers are often stored in a platform-specific location. The same member
functioncanbeusedtooverridethedefaultPCIROMonanadd-incardwithonefromplatform-specificstorage.
A platform should implement this protocol if any of the functionality that is listed above is required.
SeeCodeDefinitionsforthedefinitionof EFI_PCI_PLATFORM_PROTOCOL andthememberfunctionslistedabove.
SeePCI Host Bridge Resource Allocation Protocol for additional PCI-related design discussion.
V-11.5 Incompatible PCI Device Support Protocol
V-11.5.1 Incompatible PCI Device Support Protocol Overview
Some PCI devices do not fully comply with the PCI Specification. For example, a PCI device may request that its
I/O Base Address Register (BAR) be placed on a 0x200 boundary even though it is requesting an I/O with a length of
0x100. TheIncompatiblePCIDeviceSupportProtocolallowsaPCIbusdrivertohandleresourceallocationforsome
PCI devices that do not comply with the PCI Specification.
In the PI Architecture, the platform-specific PCI host bridge driver works with the generic, standard PCI bus driver to
configure the entire PCI subsystem. Even though the exact configuration is up to individual incompatible devices, it
is a platform choice to support those incompatible PCI devices. For example, one platform may not want to support
those incompatible devices while another platform appears more tolerant of those devices.
See Code Definitions for the definition of the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL .
V-11.5.2 Usage Model for the Incompatible PCI Device SupportProtocol
The following describes the usage model for the Incompatible PCI Device Support Protocol:
1. The PCI bus driver locates EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL . If the PCI bus
driver cannot find this protocol, simply follow the regular PCI enumeration path. Otherwise, go to step 2.
2. ForeachPCIdevicethatwasdetected,thePCIbusdriverbeginscollectingtherequiredPCIresourcesbyprobing
the Base Address Register (BAR) for each device.
3. For each device, call EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() to check
whether this PCI device is an incompatible device. If this device in not an incompatible device, go to step 5.
4. UsetheConfigurationthatisreturnedbyCheckDevice()tooverrideormodifytheoriginalPCIresourcerequire-
ments.
5. Follow the normal PCI enumeration process.
V-11.5. Incompatible PCI Device Support Protocol V-140UEFI Platform Initialization Specification, Release 1.8
V-11.6 PCI Code Definitions
•EFI_PCI_PLATFORM_PROTOCOL
•EFI_PCI_OVERRIDE_PROTOCOL
•EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
•EFI_PCI_CHIPSET_EXECUTION_PHASE
•EFI_PCI_PLATFORM_POLICY
V-11.6.1 PCI Platform Protocol
V-11.6.2 EFI_PCI_PLATFORM_PROTOCOL
Summary
This protocol provides the interface between the PCI bus driver/PCI Host Bridge Resource Allocation driver and a
platform-specific driver to describe the unique features of a platform. This protocol is optional.
GUID
#define EFI_PCI_PLATFORM_PROTOCOL_GUID \
{ 0x7d75280, 0x27d4, 0x4d69, 0x90, 0xd0, 0x56, 0x43, 0xe2, \
0x38, 0xb3, 0x41)
typedef struct \_EFI_PCI_PLATFORM_PROTOCOL {
EFI_PCI_PLATFORM_PHASE_NOTIFY PlatformNotify;
EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;
EFI_PCI_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy;
EFI_PCI_PLATFORM_GET_PCI_ROM GetPciRom;
} EFI_PCI_PLATFORM_PROTOCOL;
PlatformNotify
The notification from the PCI bus enumerator to the platform that it is about to enter a certain phase during the
enumeration process. See the PlatformNotify() function description.
PlatformPrepController
ThenotificationfromthePCIbusenumeratortotheplatformforeachPCIcontrolleratseveralpredefinedpoints
during PCI controller initialization. See the PlatformPrepController() function description.
GetPlatformPolicy
Retrieves the platform policy regarding enumeration. See the GetPlatformPolicy() function description.
GetPciRom
GetsthePCIdevice’soptionROMfromaplatform-specificlocation. Seethe GetPciRom() functiondescription.

GetPciRom
V-11.6. PCI Code Definitions V-141UEFI Platform Initialization Specification, Release 1.8
TheEFI_PCI_PLATFORM_PROTOCOL is published by a platform-aware driver. This protocol is optional; see PCI
Platform Protocol Overview in Design Discussion for scenarios in which this protocol is required. There cannot be
more than one instance of this protocol in the system.
If the PCI bus driver detects the presence of this protocol before enumeration, it will use the PCI Platform Protocol to
obtain information about the platform policy. The PCI bus driver will use this protocol to get the PCI device’s option
ROM from a platform-specific location in storage. It will also call the various member functions of this protocol at
predefinedpointsduringPCIbusenumeration. Thememberfunctionscanbeusedforperforminganyplatform-specific
initialization that is appropriate during the particular phase.
V-11.6.3 EFI_PCI_PLATFORM_PROTOCOL.PlatformNotify()
Prototype
typedef
(EFIAPI \* EFI_PCI_PLATFORM_PHASE_NOTIFY) (
IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
IN EFI_HANDLE HostBridge,
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
IN EFI_PCI_EXECUTION_PHASE ExecPhase
);
This
Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
HostBridge
Thehandleofthehostbridgecontroller. Type EFI_HANDLE isdefinedin InstallProtocolInterface() intheUEFI
2.1 Specification .
Phase
The phase of the PCI bus enumeration. Type EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE
is defined in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.NotifyPhase() .
ExecPhase
Defines the execution phase of the PCI chipset driver. Type EFI_PCI_ EXECUTION_PHASE is defined in
ThePlatformNotify() functioncanbeusedtonotifytheplatformdriversothatitcanperformplatform-specificactions.
No specific actions are required.
Several notification points are defined at this time. More notification points may be added as required in the future.
The function should return EFI_UNSUPPORTED for any value of Phase that that the function does not support.
The PCI bus driver calls this function twice for every Phase-once before the PCI Host Bridge Resource Allocation
Protocol driver is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has been notified.
This member function may not perform any error checking on the input parameters. If this member function detects
anyerrorcondition,itneedstohandlethoseerrorsonitsownbecausethereisnowaytosurfaceanyerrorstothecaller.
V-11.6. PCI Code Definitions V-142UEFI Platform Initialization Specification, Release 1.8
//***********************************************************\*
// EFI_PCI_EXECUTION_PHASE
BeforePciHostBridge = 0,
ChipsetEntry = 0,
AfterPciHostBridge = 1,
ChipsetExit = 1,
MaximumExecutionPhase
} EFI_PCI_EXECUTION_PHASE;
typedef EFI_PCI_EXECUTION_PHASE EFI_PCI_CHIPSET_EXECUTION_PHASE;
Note:EFI_PCI_EXECUTION_PHASE is used to call a platform protocol and execute platform-specific code. Fol-
lowing is a description of the fields in the above enumeration.
BeforePciHostBridge
ThephasethatindicatestheentrypointtothePCIBusNotifyphase. ThisplatformhookiscalledbeforethePCI
bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.
AfterPciHostBridge
The phase that indicates the exit point to the PCI Bus Notify phase before returning to the
PCI Bus Driver Notify phase. This platform hook is called after the PCI bus driver calls the
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.
EFI_UNSUPPORTED The function does not support the phase specified by Phase
V-11.6.4 EFI_PCI_PLATFORM_PROTOCOL.PlatformPrepController()
Summary
TheplatformdriverreceivesnotificationsfromthePCIbusenumeratoratvariousphasesduringPCIcontrollerinitial-
ization, just like the PCI host bridge driver.
Prototype
typedef
(EFIAPI \* EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER) (
IN EFI_HANDLE RootBridge,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
);
V-11.6. PCI Code Definitions V-143UEFI Platform Initialization Specification, Release 1.8
This
TheassociatedPCIhostbridgehandle. TypeEFI_HANDLEisdefinedinInstallProtocolInterface()intheUEFI
2.1 Specification.
RootBridge
The associated PCI root bridge handle.
structureisdefinedinthe EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.PreprocessController()
section above.
Phase
ThephaseofthePCIcontrollerenumeration. Type EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE
is defined in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.PreprocessController() .
ExecPhase
Defines the execution phase of the PCI chipset driver. Type EFI_PCI_CHIPSET_EXECUTION_PHASE is de-
fined inEFI_PCI_PLATFORM_PROTOCOL.PlatformNotify() .
ThePlatformPrepController()functioncanbeusedtonotifytheplatformdriversothatitcanperformplatform-specific
actions. No specific actions are required.
Severalnotificationpointsaredefinedatthistime. Moresynchronizationpointsmaybeaddedasrequiredinthefuture.
ThePCIbusdrivercallstheplatformdrivertwiceforeveryPCIcontroller–oncebeforethePCIHostBridgeResource
AllocationProtocoldriverisnotified,andonceafterthePCIHostBridgeResourceAllocationProtocoldriverhasbeen
notified.
This member function may not perform any error checking on the input parameters. It also does not return any error
codes. If this member function detects any error condition, it needs to handle those errors on its own because there is
no way to surface any errors to the caller.
V-11.6.5 EFI_PCI_PLATFORM_PROTOCOL.GetPlatformPolicy()
Summary
The PCI bus driver and the PCI Host Bridge Resource Allocation Protocol driver can call this member function to
retrieve platform policies regarding PCI enumeration.
Prototype
typedef
(EFIAPI \* EFI_PCI_PLATFORM_GET_PLATFORM_POLICY) (
OUT EFI_PCI_PLATFORM_POLICY *PciPolicy,
);
V-11.6. PCI Code Definitions V-144UEFI Platform Initialization Specification, Release 1.8
This
PciPolicy
TheplatformpolicywithrespecttoVGAandISAaliasing. Type EFI_PCI_PLATFORM_POLICY isdefinedin
TheGetPlatformPolicy() function retrieves the platform policy regarding PCI enumeration. The PCI bus driver and
the PCI Host Bridge Resource Allocation Protocol driver can call this member function to retrieve the policy.
TheEFI_PCI_IO_PROTOCOL.Attributes() function allows a PCI device driver to ask for various legacy ranges. Be-
cause PCI device drivers run after PCI enumeration, a request for legacy allocation comes in after PCI enumeration.
TheonlypracticalwaytoguaranteethatsucharequestfromaPCIdevicedriverwillbefulfilledistopreallocatethese
ranges during enumeration. The PCI bus enumerator does not know which legacy ranges may be requested and there-
fore must rely on GetPlatformPolicy() . The data that is returned by GetPlatformPolicy() determines the supported
attributes that are returned by the EFI_PCI_IO_PROTOCOL.Attributes() function.
See “Related Definitions” below for a description of the output parameter PciPolicy . For example, the plat-
form can decide if it wishes to support devices that require ISA aliases using this parameter. Note that the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() function returns the attributes that the root bridge hard-
ware supports and does not depend upon preallocations.
typedef UINT32 EFI_PCI_PLATFORM_POLICY;
EFI_PCI_PLATYFORM_POLICY is a bitmask with the following legal combinations.
#define EFI_RESERVE_NONE_IO_ALIAS 0x0000
#define EFI_RESERVE_ISA_IO_ALIAS 0x0001
#define EFI_RESERVE_ISA_IO_NO_ALIAS 0x0002
#define EFI_RESERVE_VGA_IO_ALIAS 0x0004
#define EFI_RESERVE_VGA_IO_NO_ALIAS 0x0008
EFI_UNSUPPORTED The function is not supported.
EFI_INVALID_PARAMETER PciPolicy is NULL.
V-11.6.6 EFI_PCI_PLATFORM_PROTOCOL.GetPciRom()
Summary
Gets the PCI device’s option ROM from a platform-specific location.
Prototype
typedef
(EFIAPI \* EFI_PCI_PLATFORM_GET_PCI_ROM) (
IN EFI_HANDLE PciHandle,
V-11.6. PCI Code Definitions V-145UEFI Platform Initialization Specification, Release 1.8
OUT VOID **RomImage,
OUT UINTN *RomSize

Summary
Prototype
typedef
);
This
PciHandle
The handle of the PCI device. Type EFI_HANDLE is defined in InstallProtocolInterface() in theUEFI 2.1
RomImage
If the call succeeds, the pointer to the pointer to the option ROM image. Otherwise, this field is undefined.
The memory for RomImage is allocated by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using the UEFI
Boot Service AllocatePool() . It is the caller’s responsibility to free the memory using the UEFI Boot Service
FreePool() , when the caller is done with the option ROM.
RomSize
If the call succeeds, a pointer to the size of the option ROM size. Otherwise, this field is undefined.
TheGetPciRom() functiongetsthePCIdevice’soptionROMfromaplatform-specificlocation. TheoptionROMwill
be loaded into memory. This member function is used to return an image that is packaged as a PCI 2.2 option ROM.
TheimagemaycontainbothlegacyandUEFIoptionROMs. Seethe UEFI2.1Specification fordetails. Thismember
functioncanbeusedtoreturnoptionROMimagesforembeddedcontrollers. OptionROMsforembeddedcontrollers
are typically stored in platform-specific storage, and this member function can retrieve it from that storage and return
ittothePCIbusdriver. ThePCIbusdriverwillcallthismemberfunctionbeforescanningtheROMthatisattachedto
any controller, which allows a platform to specify a ROM image that is different from the ROM image on a PCI card.
EFI_SUCCESS TheoptionROMwasavailableforthisdeviceandloadedintomem-
ory
EFI_NOT_FOUND No option ROM was available for this device
EFI_OUT_OF_RESOURCES No memory was available to load the option ROM
EFI_DEVICE_ERROR An error occurred in getting the option ROM
V-11.6.7 PCI Override Protocol
V-11.6.8 EFI_PCI_OVERRIDE_PROTOCOL
Summary
This protocol provides the interface between the PCI bus driver/PCI Host Bridge Resource Allocation driver and an
implementation’s driver to describe the unique features of a platform. This protocol is optional.
GUID
#define EFI_PCI_OVERRIDE_GUID \
{ 0xb5b35764, 0x460c, 0x4a06, { 0x99, 0xfc, 0x77, 0xa1, \
0x7c, 0x1b, 0x5c, 0xeb } }
V-11.6. PCI Code Definitions V-146UEFI Platform Initialization Specification, Release 1.8
typedef EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_OVERRIDE_PROTOCOL;
The PCI Override Protocol is published by an implementation aware driver. This protocol is optional. But it must be
called, if present, during PCI enumeration. There cannot be more than one instance of this protocol in the system.
IfthePCIbusdriverdetectsthepresenceofthisprotocolbeforebusenumeration,itwillusethePCIOverrideProtocol
to obtain information about the platform policy. If the PCI Platform Protocol does not exist or returns an error, then
this protocol is called.
ThePCIbusdriverwillusethisprotocoltogetthePCIdevice’soptionROMfromanimplementation-specificlocation
in storage. If the PCI Platform Protocol does not exist or returns an error, then this function is called.
It will also call the various member functions of this protocol at predefined points during PCI bus enumeration. The
memberfunctionscanbeusedforperforminganyimplementation-specificinitializationthatisappropriateduringthe
particular phase.
V-11.6.9 Incompatible PCI Device Support Protocol
V-11.6.10 EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
Summary
AllowsthePCIbusdrivertosupportresourceallocationforsomePCIdevicesthatdonotcomplywiththePCISpeci-
fication.
Note:Thisprotocolisoptional. Onlythoseplatformsthatimplementthisprotocolwillhavethecapabilitytosupport
incompatible PCI devices. The absence of this protocol can cause the PCI bus driver to configure these incompatible
PCI devices incorrectly. As a result, these devices may not work properly.
GUID
#define EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL_GUID \
{0xeb23f55a, 0x7863, 0x4ac2, 0x8d, 0x3d, 0x95, 0x65, 0x35, \
0xde, 0x3, 0x75}
typedef struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL {
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE CheckDevice;
} EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL;
CheckDevice
Returns a list of ACPI resource descriptors that detail any special resource configuration requirements if the
specified device is a recognized incompatible PCI device. See the CheckDevice() function description.
The EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL is used by the PCI bus driver to support re-
source allocation for some PCI devices that do not comply with the PCI Specification. This protocol can
find some incompatible PCI devices and report their special resource requirements to the PCI bus driver. The
generic PCI bus driver does not have prior knowledge of any incompatible PCI devices. It interfaces with the
V-11.6. PCI Code Definitions V-147UEFI Platform Initialization Specification, Release 1.8
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL to find out if a device is incompatible and to obtain
the special configuration requirements for a specific incompatible PCI device.
This protocol is optional, and only one instance of this protocol can be present in the system. If a platform supports
this protocol, this protocol is produced by a Driver Execution Environment (DXE) driver and must be made available
beforetheBootDeviceSelection(BDS)phase. ThePCIbusdriverwilllookforthepresenceofthisprotocolbeforeit
begins PCI enumeration.
If this protocol exists in a platform, it indicates that the platform has the capability to support those incompatible PCI
devices. However,finalsupportforincompatiblePCIdevicesstilldependsontheimplementationofthePCIbusdriver.
The PCI bus driver may fully, partially, or not even support these incompatible devices.
During PCI bus enumeration, the PCI bus driver will probe the PCI Base Address Registers (BARs) for each PCI
device–regardless of whether the PCI device is incompatible or not–to determine the resource requirements so that
the PCI bus driver can invoke the proper PCI resources for them. Generally, this resource information includes the
•Resource type
•Resource length
•Alignment
However, some incompatible PCI devices may have special requirements. As a result, the length or the alignment
that is derived through BAR probing may not be exactly the same as the actual resource requirement of the device.
For example, there are some devices that request I/O resources at a length of 0x100 from their I/O BAR, but these
incompatibledeviceswillneverworkcorrectlyifanoddI/Obaseaddress,suchas0x100,0x300,or0x500,isassigned
totheBAR.Instead,thesedevicesrequestanevenbaseaddress,suchas0x200or0x400. TheIncompatiblePCIDevice
SupportProtocolcanthenbeusedtoobtainthesespecialresourcerequirementsfortheseincompatiblePCIdevices. In
this way, the PCI bus driver will take special consideration for these devices during PCI resource allocation to ensure
that they can work correctly.
This protocol may support the following incompatible PCI BAR types:
•I/O or memory length that is different from what the BAR reports
•I/O or memory alignment that is different from what the BAR reports
•Fixed I/O or memory base address
See theConventional PCI Specification 3.0 for the details of how a PCI BAR reports the resource length and the
alignment that it requires.
V-11.6.11 EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice()
Summary
ReturnsalistofACPIresourcedescriptorsthatdetailthespecialresourceconfigurationrequirementsforanincompat-
ible PCI device.
Prototype
typedef
(EFIAPI \*EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE) (
IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,
IN UINTN VendorId,
IN UINTN DeviceId,
IN UINTN RevisionId,
V-11.6. PCI Code Definitions V-148UEFI Platform Initialization Specification, Release 1.8
IN UINTN SubsystemVendorId,
IN UINTN SubsystemDeviceId,
);
This
Pointer to the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL instance.
VendorID
A unique ID to identify the manufacturer of the PCI device. See the Conventional PCI Specification 3.0 for
details.
DeviceID
A unique ID to identify the particular PCI device. See the Conventional PCI Specification 3.0 for details.
RevisionID
A PCI device-specific revision identifier. See the Conventional PCI Specification 3.0 for details.
Specifies the subsystem vendor ID. See the Conventional PCI Specification 3.0 for details.
Specifies the subsystem device ID. See the Conventional PCI Specification 3.0 for details.
A list of ACPI resource descriptors that detail the configuration requirement. See ACPI 2.0 & 3.0 QWORD
Address Space Descriptor Usage in the “Description” subsection below for the definition.
The CheckDevice() function returns a list of ACPI resource descriptors that detail the special resource configuration
requirements for an incompatible PCI device.
Prior to bus enumeration, the PCI bus driver will look for the presence of the

details.
DeviceID
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL . Only one instance of this protocol can be present
in the system. For each PCI device that the PCI bus driver discovers, the PCI bus driver calls this function with the
device’svendorID,deviceID,revisionID,subsystemvendorID,andsubsystemdeviceID.IftheVendorId,DeviceId,
RevisionId, SubsystemVendorId, or SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The ID
values that are not (UINTN)-1 will be used to identify the current device.
This function will only return EFI_SUCCESS. However, if the device is an incompatible PCI device, a list of ACPI
resourcedescriptorswillbereturnedinConfiguration. Otherwise,NULLwillbereturnedinConfigurationinstead. The
PCIbusdriverdoesnotneedtoallocatememoryforConfiguration. However,itisthePCIbusdriver’sresponsibilityto
freeit. ThePCIbusdriverthencanconfigurethisdevicewiththeinformationthatisderivedfromthislistofresource
nodes, rather than the result of BAR probing.
Onlythefollowingtworesourcedescriptortypesfromthe ACPISpecification maybeusedtodescribetheincompatible
PCI device resource requirements:
•QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)
•End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)
below contain these two descriptor types. See the ACPI Specification for details on the field values.
V-11.6. PCI Code Definitions V-149UEFI Platform Initialization Specification, Release 1.8
Table 11.1: ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage
Byte
0x03 0x01 Resource type 0 Memory range 1 I O range Other values will be ignored
0x04 0x01 General flags Ignored
0x05 0x01 Type specific flags Only used when Address Translation Offset 6 Value 0 Skip
deviceoptionROMdonotprobeoptionromBAROthervalueswillbeignored
0x06 0x08 AddressSpaceGranularityIgnoredifthevalueis0IgnoredifthePCIBARisI
OIgnoredifthePCIBARis32btmemoryIfPCIBARis64bitmemoryandthis
fieldis32thenthePCIBARresourceisallocatedbelow4GBIfthePCIBARis
64bitmemoryandthisfieldis64thenthePCIBARresourceisallocatedabove
4GB
0x16 0x08 Address Range Maximum Used to indicate the BAR Index from 0 to 6 where
6 is the Option Rom BAR Specially UINT64 1 in this field means all the PCI
BARs on the device except the Option Rom BAR
0x1E 0x08 Address Translation Offset Used to indicate the BAR Index from 0 to 6 where
6 is the Option ROM BAR Specially UINT64 1 in this field means all the PCI
BARs are on the device except the Option ROM BAR
0x26 0x08 Address Range Length Length of the requested resource If the device has no
speciallengthrequestitmustbe0ThenthelengththatwasobtainedfromBAR
probing will be applied
Table 11.2: ACPI 2.0 & 3.0 End Tag Usage
Byte
0x00 0x01 0x79 End Tag.
0x01 0x01 0x00 Checksum. Set to 0 to indicate that checksum is to beignored.
EFI_SUCCESS The function always returns EFI_SUCCESS
V-11.6. PCI Code Definitions V-150CHAPTER
TWELVE
HOT PLUG PCI
V-12.1 HOT PLUG PCI Overview
This specification defines the core code and services that are required for an implementation of the Hot-Plug PCI
InitializationProtocol. APCIbusdriver,runningintheEFIBootServicesenvironment,usesthisprotocoltoinitialize
the hot-plug subsystem. The same protocol may be used by other buses such as CardBus that support hot plugging.
•Describes the basic components of the hot-plug PCI subsystem and the Hot-Plug PCI Initialization Protocol
•Provides code definitions for the Hot-Plug PCI Initialization Protocol and the hot-plug-PCI-related type defini-
tions that are architecturally required.
V-12.2 Hot Plug PCI Initialization Protocol Introduction
This chapter describes the Hot-Plug PCI Initialization Protocol. A PCI bus driver, running in the EFI Boot Services
environment,usesthisprotocoltoinitializethehot-plugsubsystem. ThisprotocolisgenericenoughtoincludePCI-to-
CardBusbridgesandPCIExpress*systems. Thisprotocolabstractsthehot-plugcontrollerinitializationandresource
padding. This protocol is required on platforms that support PCI Hot Plug* or PCI Express slots. For the purposes of
initialization, a CardBus PC Card bus is treated in the same way. This protocol is not required on all other platforms.
ThisprotocolisnotintendedtosupporthotpluggingofPCIcardsduringtheprebootstage. Separatecomponentscan
bedevelopedifsuchsupportisdesired. SeeHot-PlugPCIInitializationProtocolinCodeDefinitionsforthedefinition
ofEFI_PCI_HOT_PLUG_INIT_PROTOCOL .
V-12.3 Hot Plug PCI Initialization Protocol RelatedInformation
The following resources are referenced throughout this specification or may be useful to you:
•Conventional PCI Specification, revision 3.0: http://www.pcisig.com/*
•PC Card Standard, volumes 1, 7, and 8: http://www.pcmcia.org/*
•PCI Express Base Specification, revision 1.0a: http://www.pcisig.com/*
•PCI Hot-Plug Specification, revision 1.1: http://www.pcisig.com/*
•PCI Standard Hot-Plug Controller and Subsystem Specification, revision 1.0: http://www.pcisig.com/*
V-151UEFI Platform Initialization Specification, Release 1.8
V-12.4 Requirements
PIArchitecturefirmwaremustsupportplatformswithPCIHotPlug*slotsandPCIExpress*HotPlugslots,aswellas
CardBus PC Card sockets. In both cases, the user is allowed to plug in new devices or remove existing devices during
runtime. PCI Hot Plug slots are controlled by a PCI Hot Plug controller whereas CardBus sockets are controlled by a
PCI-to-CardBusbridge. PCIExpressHotPlugslotsarecontrolledbyaPCIExpressrootportoradownstreamportin
a switch. The term “Hot Plug Controller” (HPC) in this document refers to all of these types of controllers. From the
standpoint of initialization, all three are identical and have the same general requirements, as follows:
•The root HPCs may come up uninitialized after system reset. These HPCs must be initialized by the system
firmware.
•Every HPC may require resource padding. The padding must be taken into account during PCI enumeration.
ThisscenarioistrueforconventionalPCI,PCIExpress,andCardBusPCCardsbecausetheyallconsumeshared
system resources (I/O, memory, and bus). These resources are produced by the root PCI bridge.
These general requirements place the following specific requirements on an implementation of the PI Architechture
PCI hot plug support:
•PI Architecture firmware must handle root HPCs differently than other regular PCI devices. When a root HPC
is initialized, the hot-plug slots or CardBus sockets are enabled and this process may uncover more PCI buses
anddevices. Inthatrespect,rootHPCsaresomewhatlikePCIbridges. TherootHPCinitializationprocessmay
involvedetectingbustypeandoptimumbusspeed. Theinitializationprocessmayalsodetectfaultsandvoltage
mismatches. Theinitializationprocessmaybespecifictothecontrollerandtheplatform. Atthetimeoftheroot
HPC initialization, the PCI bus may not be fully initialized and the standard PCI bus-specific protocols are not
available. PI Architecture firmware must provide an alternate infrastructure for the initialization code. In other
words, the HPC initialization code should not be required to understand the bus numbering scheme and other
chipset details.
•PI Architecture firmware must support an unlimited number of HPCs in the system. PI Architecture firmware
must support various types of HPCs as long as they follow industry standards or conventions. A mix of various
types of HPCs is allowed.
•PI Architecture firmware must support legacy PCI Hot Plug Controllers (PHPCs; class code 0x6, subclass code
0x4) as well as Standard (PCI) Hot Plug Controllers (SHPCs). Other conventional PCI Hot Plug controllers are
not supported.
•PIArchitecturefirmwaremustbecapableofsupportingaPHPCthatisachildofanotherPHPC.Inthatcase,the
PCIStandardHot-PlugControllerandSubsystemSpecification requiresthatthechildPHPCmustbeinitialized
without firmware assistance because it is not a root PHPC.
•PI Architecture firmware must be capable of supporting SHPCs on an add-in card. In that case, the PCI Stan-
dard Hot-Plug Controller and Subsystem Specification requires that such an SHPC must be initialized without
firmware assistance because it is not a root PHPC. PI Architecture firmware must also support plug-in CardBus
bridges that follow the CardBus Specification, which is part of the PC Card Standard .
•As stated above, root HPCs may require firmware initialization. PI Architecture firmware must be capable of
supporting root HPCs that are initialized by hardware and do not require any firmware initialization.
•APIArchitecturePCIbusenumeratormustoverallocateresourcesforPCIHotPlugbusesandCardBussockets.

The amount of overallocation may be platform specific.
•TherootHPCinitializationprocessmaybetimeconsuming. AnSHPCcantakeaslongas15secondstoenable
power to a hot-plug bus without violating the PCI Special Interest Group (PCI-SIG*) requirements. PI Archi-
tecturefirmwareshouldbeabletoinitializemultipleHPCsinparalleltoreduceboottime. Incontrast,CardBus
initialization is quick.
•PI Architecture firmware should be able to handle when an HPC fails. PI Architecture firmware should be able
to handle an HPC that has been disabled.
V-12.4. Requirements V-152UEFI Platform Initialization Specification, Release 1.8
•The PCI bus driver in PI Architecture firmware is not required to assume anything that is not in one of the
PCI-SIG specifications.
•It must be possible to produce legacy Hot Plug Resource Tables (HPRTs) if necessary. HPRTs are described in
the PCI Standard Hot-Plug Controller and Subsystem Specification.
V-12.5 Sample Implementation for a Platform Containing PCIHot
Plug* Slots
A sample algorithm for PCI bus enumeration is described below to clarify some of the finer points of the
EFI_PCI_HOT_PLUG_INIT_PROTOCOL .Actualimplementationsmayvaryalthoughtherelativeorderingofevents
iscritical. TheactivitiesrelatedtoPCIHotPlug*areunderlined. Pleasenotethatmultiplepassesofbusenumeration
are required in a system containing PCI Hot Plug slots.
SeePCI Host Bridge Resource Allocation Protocol for definitions of the
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL and its member functions.
If the platform supports PCI Hot Plug, an instance of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL is installed.
The PCI enumeration process begins.
Look for instances of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL . If it is not found, all the hot-plug subsys-
tem initialization steps can be skipped. If one exists, create a list of root Hot Plug Controllers (HPCs) by calling
EFI_PCI_HOT_PLUG_INIT_PROTOCOL.GetRootHpcList() .
Notify the host bridge driver that bus enumeration is about to begin by calling
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.NotifyPhase (EfiPciHostBridgeBeginBusAl-
location).
For every PCI root bridge handle, do the following:
1. Call EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.StartBusEnumeration
(This,RootBridgeHandle).
2. Make sure each PCI root bridge handle supports the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL . See theUE
FI 2.1 Specification for the definition of the PCI Root Bridge I/O Protocol.
3. Allocatememorytoholdresourcerequirements. Thesecanbetworesourcedescriptors,onetoholdbusrequire-
ments and another to hold the I/O and memory requirements.
4. CallEFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.GetAllocAttributes() to get the at-
tributesofthisPCIrootbridge. Thisinformationisusedtocombinedifferenttypesofmemoryresourcesinthe
next step.
Scanallthedevicesinthespecifiedbusrangeandthespecifiedsegment,onebusatatime. IfthedeviceisaPCI-to-PCI
bridge,updatethebusnumbersandprogramthebusnumberregistersinthePCI-to-PCIbridgehardware. Ifthedevice
path of a device matches that of a root HPC and it is not a PCI-to-CardBus bridge, it must be initialized by calling
EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc() beforethebusitcontrolscanbefullyenumerated. The
PCI bus enumerator determines the PCI address of the PCI Hot Plug Controller (PHPC) and passes it as an input to
InitializeRootHpc() .
5. Continue to scan devices on that root bridge and start the initialization of all root HPCs.
6. CallEFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SetBusNumbers() so that the HPCs
under initialization are still accessible. SetBusNumbers() cannot affect the PCI addresses of the HPCs.
Wait until all the HPCs that were found on various root bridges in step 5 to complete initialization.
V-12.5. Sample Implementation for a Platform Containing PCIHot Plug* Slots V-153UEFI Platform Initialization Specification, Release 1.8
Go back to step 5 for another pass and rescan the PCI buses. For all the root HPCs and the non-
root HPCs, call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.GetResourcePadding() to obtain the amount of over-
allocation and add that amount to the requests from the physical devices. Reprogram the bus num-
bers by taking into account the bus resource padding information. This action will require calling
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SetBusNumbers() . The rescan is not required
if there is only one root bridge in the system.
Once the memory resources are allocated and a PCI-to-CardBus bridge is part of the HpcList, it will be initialized.
V-12.6 PCI Hot Plug PCI Initialization Protocol
V-12.6.1 EFI_PCI_HOT_PLUG_INIT_PROTOCOL
Summary
ThisprotocolprovidesthenecessaryfunctionalitytoinitializetheHotPlugControllers(HPCs)andthebusesthatthey
control. This protocol also provides information regarding resource padding.
Note:This protocol is required only on platforms that support one or more PCI Hot Plug* slots or CardBus sockets.
GUID
#define EFI_PCI_HOT_PLUG_INIT_PROTOCOL_GUID \\
{ 0xaa0e8bc1, 0xdabc, 0x46b0, 0xa8, 0x44, 0x37, 0xb8, 0x16,\\
0x9b, 0x2b, 0xea }
typedef struct \_EFI_PCI_HOT_PLUG_INIT_PROTOCOL {
EFI_GET_ROOT_HPC_LIST GetRootHpcList;
EFI_INITIALIZE_ROOT_HPC InitializeRootHpc;
EFI_GET_HOT_PLUG_PADDING GetResourcePadding;
} EFI_PCI_HOT_PLUG_INIT_PROTOCOL;
GetRootHpcList
Returns a list of root HPCs and the buses that they control. See the GetRootHpcList() function description.
InitializeRootHpc
Initializes the specified root HPC. See the InitializeRootHpc() function description.
GetResourcePadding
Returns the resource padding that is required by the HPC. See the GetResourcePadding() function description.
TheEFI_PCI_HOT_PLUG_INIT_PROTOCOL providesamechanismforthePCIbusenumeratortoproperlyinitialize
theHPCsandCardBussocketsthatrequireinitialization. TheHPCinitializationtakesplacebeforethePCIenumeration
processiscomplete. Therecannotbemorethanoneinstanceofthisprotocolinasystem. Thisprotocolisinstalledon
its own separate handle.
BecausethesystemmayincludemultipleHPCs,oneinstanceofthisprotocolshouldrepresentallofthem. Theprotocol
functions use the device path of the HPC to identify the HPC. When the PCI bus enumerator finds a root HPC, it will
callEFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc() . If InitializeRootHpc() is unable to initialize a
V-12.6. PCI Hot Plug PCI Initialization Protocol V-154UEFI Platform Initialization Specification, Release 1.8
root HPC, the PCI enumerator will ignore that root HPC and continue the enumeration process. If the HPC is not
initialized, the devices that it controls may not be initialized, and no resource padding will be provided.
From the standpoint of the PCI bus enumerator, HPCs are divided into the following two classes:
Root HPC
These HPCs must be initialized by calling InitializeRootHpc() during the enumeration process. These HPCs
will also require resource padding. The platform code must have a priori knowledge of these devices and must
know how to initialize them. There may not be any way to access their PCI configuration space before the PCI
enumeratorprogramsalltheupstreambridgesandthusenablesthepathtothesedevices. ThePCIbusenumerator
is responsible for determining the PCI bus address of the HPC before it calls InitializeRootHpc().
Nonroot HPC
These HPCs will not need explicit initialization during enumeration process. These HPCs will require resource
padding. The platform code does not have to have a priori knowledge of these devices.
V-12.6.2 EFI_PCI_HOT_PLUG_INIT_PROTOCOL.GetRootHpcList()
Summary
Returns a list of root Hot Plug Controllers (HPCs) that require initialization during the boot process.
Prototype
typedef
(EFIAPI *EFI_GET_ROOT_HPC_LIST) (
IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
OUT UINTN *HpcCount,
OUT EFI_HPC_LOCATION **HpcList
);
This
Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.
HpcCount
The number of root HPCs that were returned.
HpcList
The list of root HPCs. HpcCount defines the number of elements in this list. Type EFI_HPC_LOCATION is
ThisprocedurereturnsalistofrootHPCs. ThePCIbusdrivermustinitializethesecontrollersduringthebootprocess.
ThePCIbusdrivermayormaynotbeabletodetecttheseHPCs. IftheplatformincludesaPCI-to-CardBusbridge,it
canbeincludedinthislistifitrequiresinitialization. TheHpcListmustbeselfconsistent. AnHPCcannotcontrolany
ofitsparentbuses. OnlyoneHPCcancontrolaPCIbus. BecausethislistincludesonlyrootHPCs,noHPCinthelist
can be a child of another HPC. This policy must be enforced by the EFI_PCI_HOT_PLUG_INIT_PROTOCOL . The
PCI bus driver may not check for such invalid conditions.
The callee allocates the buffer HpcList.
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// EFI_HPC_LOCATION

HpcList
EFI_DEVICE_PATH_PROTOCOL \* *HpcDevicePath* ;
EFI_DEVICE_PATH_PROTOCOL \* *HpbDevicePath* ;
} EFI_HPC_LOCATION;
HpcDevicePath
The device path to the root HPC. An HPC cannot control its parent buses. The PCI bus driver requires this
informationsothatitcanpassthecorrectHpcPciAddresstothe InitializeRootHpc() andGetResourcePadding()
functions. Type EFI_DEVICE_PATH_PROTOCOL isdefinedin LocateDevicePath() inPCIPlatformOverview
of the UEFI 2.1 Specification.
HpbDevicePath
The device path to the Hot Plug Bus (HPB) that is controlled by the root HPC. The PCI bus driver uses this
information to check if a particular PCI bus has hot-plug slots. The device path of a PCI bus is the same as the
device path of its parent. For Standard (PCI) Hot Plug Controllers (SHPCs) and PCI Express*, HpbDevicePath
is the same as HpcDevicePath.
EFI_SUCCESS HpcList was returned
EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient resources
EFI_INVALID_PARAMETER HpcCount is NULL
EFI_INVALID_PARAMETER HpcList is NULL
V-12.6.3 EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc()
Summary
Initializes one root Hot Plug Controller (HPC). This process may causes initialization of its subordinate buses.
Prototype
typedef
(EFIAPI *EFI_INITIALIZE_ROOT_HPC) (
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
IN UINT64 HpcPciAddress,
IN EFI_EVENT Event, OPTIONAL
OUT EFI_HPC_STATE *HpcState
);
This
The device path to the HPC that is being initialized. Type EFI_DEVICE_PATH_PROTOCOL is defined in
LocateDevicePath() inPCI Platform Overview of the UEFI 2.1 Specification.
HpcPciAddress
The address of the HPC function on the PCI bus.
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Event
TheeventthatshouldbesignaledwhentheHPCinitializationiscomplete. Setto NULLifthecallerwantstowait
until the entire initialization process is complete. The event must be of type EFI_EVENT_NOTIFY_SIGNAL .
TypeEFI_EVENT is defined in CreateEvent() in theUEFI Specification .
HpcState
The state of the HPC hardware. The type EFI_HPC_STATE is defined in “Related Definitions” below.
ThisfunctioninitializesthespecifiedHPC.Attheendofinitialization,thehot-plugslotsorsockets(controlledbythis
HPC)arepoweredandareconnectedtothebus. AllthenecessaryregistersintheHPCaresetup. ForaStandard(PCI)
Hot Plug Controller (SHPC), the registers that must be set up are defined in the PCI Standard Hot Plug Controller
andSubsystemSpecification . ForothersHPCs,theyarespecifictotheHPChardware. Theinitializationprocessmay
choosenottoenablecertainPCIHotPlug*slotsorsocketsforanyreason. ThePCIHotPlugslotsorCardBussockets
thatareleftdisabledatthisstagearenotavailabletothesystem. APCIslotmaybedisabledduetoapowerfault,PCI
bustypemismatch,orpowerbudgetconstraints. TheHPCinitializationprocesscanbetimeconsuming. Poweringup
the slots that are controlled by SHPCs can take up to 15 seconds. In a system with multiple HPCs, it is desirable to
perform these activities in parallel. Therefore, this procedure supports nonblocking execution mode.
IfInitializeRootHpc() iscalledwithanon-NULLevent,HPCinitializationisconsideredcompleteaftertheeventissig-
naled. IfInitializeRootHpc() iscalledwithanon-NULLevent,areturnfrom InitializeRootHpc() withEFI_SUCCESS
marks the completion of the HPC initialization.
The PCI bus enumerator will call this function for every root HPC that is returned by GetRootHpcList() .
The PCI bus enumerator must make sure that the registers that are required during HPC initialization are accessible
beforecalling InitializeRootHpc() . Thedeterminationofwhethertheregistersareaccessibleisbasedonthefollowing
rules:
•For HPCs (legacy HPCs, SHPCs inside a PCI-to-PCI bridge, and PCI Express* HPCs), the PCI configuration
spaceoftheHPCdevicemustbeaccessible. Inotherwords,alltheupstreambridgesincludingrootbridgesand
special-purpose PCI-to-PCI bridges are programmed to forward PCI configuration cycles to the HPC.
•SHPCs inside a root bridge are accessible without any initialization of the PCI bus.
•PCI-to-CardBusbridgeshavetheirregistersmappedintothememoryspaceusingamemoryBaseAddressReg-
ister (BAR).
ThisfunctiontakesthedevicepathoftheHPCasaninput. AtthetimeofHPCinitialization,thePCIbusenumeration
is not complete. The PCI bus enumerator may not have created a handle for the HPC and the hot-plug initialization
code cannot use the EFI_PCI_IO_PROTOCOL orEFI_DEVICE_PATH_PROTOCOL like other PCI device drivers.
The device path uniquely identifies the HPC and also the PCI bus that it controls.
If the HPCis a PCI device,the hot-plug initialization codemay need its addresson the PCI busto access its registers.
The PCI address of a regular PCI device is dynamic but is known to the PCI bus driver. Therefore, the PCI bus driver
provides it through the input parameter HpcPciAddress to this function. Passing this address eliminates the need for
InitializeRootHpc() toconvertthedevicepathintothePCIaddress. IftheHPCisafunctioninamultifunctiondevice,
this address is the PCI address of that function. The HPC’s configuration space must be accessible at the specified
HpcPciAddressuntiltheHPCinitializationiscomplete. Inotherwords,thePCIbusdrivercannotrenumberPCIbuses
that are upstream to the HPC while it is being initialized.
This member function can use the LocateDevicePath() function to locate the appropriate instance of the
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL .
If theEventis not NULL, this function will return control to the caller without completing the entire initialization.
This function must perform some basic checks to make sure that it knows how to initialize the specified HPC before
returningcontrol. The Eventissignaledwhentheinitializationprocesscompletes,regardlessofwhetheritresultsina
failure. The caller must check HpcState to get the initialization status after the event is signaled.
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IfEventis not NULL, it is possible that the Eventmay be signaled before this function returns. There are at least two
cases where that may happen:
•A simple implementation of EFI_PCI_HOT_PLUG_INIT_PROTOCOL may force the caller to wait until the
initialization is complete. In that case, the InitializeRootHpc() function may signal the event before it returns
control back to the caller.
•The HPC may already have been initialized by the time InitializeRootHpc() is called. In that case, Initialize-
RootHpc() will signal Eventand return control back to the caller.
HpcStatereturnsthestateoftheHPCatthetimewhencontrolreturns. IfEventisNULL,HpcStatemustindicatethat
the HPC has completed initialization. If Event is not NULL, HpcState can indicate that the HPC has not completed
initialization when this function returns, but HpcState must be updated before Event is signaled.
ThefirmwaremaynotwaituntilInitializeRootHpc()tostartHPCinitialization. Thefirmwaremaystarttheinitialization
earlier in the boot process and the initialization may be completely done by the time the PCI bus enumerator calls
InitializeRootHpc(). An HPC can be initialized by hardware alone, and no firmware initialization may be needed. For
suchHPCs,thismemberfunctiondoesnothavetodoanyrealwork. Insuchcases,InitializeRootHpc()merelyactsas
a synchronization point.
// EFI_HPC_STATE
// Describes current state of an HPC
typedef UINT16 EFI_HPC_STATE;
#define EFI_HPC_STATE_INITIALIZED 0x01
#define EFI_HPC_STATE_ENABLED 0x02
Following is a description of the possible states for EFI_HPC_STATE .
Table 12.1: Description of possible states for EFI_HPC_STATE
0 Not initialized
EFI_HPC_STATE_INITIALIZED The HPC initialization function was called and the HPC completed
initialization but it was not enabled for some reason The HPC may
bedisabledinhardwareoritmaybedisabledduetouserpreferences
hardware failure or other reasons No resource padding is required
EFI_HPC_STATE_INITIALIZED
EFI_HPC_ENABLEDThe HPC initialization function was called the HPC completed ini-
tialization and it was enabled Resource padding is required
EFI_SUCCESS IfEventis NULL, the specific HPC wassuccessfully initialized. If
Event isnot NULL, Event will be signaled at a latertime when ini-
tialization is complete.
EFI_UNSUPPORTED This instance of*EFI_PCI_HOT_PLUG_INIT_PROTOCOL* does
notsupport the specified HPC. If Eventisnot NULL, it will not be
signaled.
EFI_OUT_OF_RESOURCES Initialization failed due to insufficientresources. If Eventis not
NULL, it willnot be signaled.
EFI_INVALID_PARAMETER HpcState is NULL.
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signaled.
V-12.6.4 EFI_PCI_HOT_PLUG_INIT_PROTOCOL.GetResourcePadding()
Summary
Returns the resource padding that is required by the PCI bus that is controlled by the specified Hot Plug Controller
(HPC).
Prototype
typedef
(EFIAPI *EFI_GET_HOT_PLUG_PADDING) (
OUT EFI_HPC_STATE *HpcState,
OUT VOID **Padding,
OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
);
This
The device path to the HPC. Type EFI_DEVICE_PATH_PROTOCOL is defined in LocateDevicePath() inPCI
Platform Overview of the UEFI 2.1 Specification.
HpcState
The state of the HPC hardware. Type EFI_HPC_STATE is defined in
EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc() .
Padding
TheamountofresourcepaddingthatisrequiredbythePCIbusunderthecontrolofthespecifiedHPC.Because
the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller.
Describes how padding is accounted for. The padding is returned in the form of ACPI (2.0 & 3.0) resource
descriptors. The exact definition of each of the fields is the same as in PCI Host Bridge Resource Allocation
Protocol in Section V-10.8.2 .TypeEFI_HPC_PADDING_ATTRIBUTES is defined in “Related Definitions”
below.
ThisfunctionreturnstheresourcepaddingthatisrequiredbythePCIbusthatiscontrolledbythespecifiedHPC.This
member function is called for all the root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. This
functionwillbecalledbeforePCIresourceallocationiscompleted. ThisfunctionmustbecalledafteralltherootHPCs,
with the possible exception of a PCI-to-CardBus bridge, have completed initialization. Waiting until initialization
is completed allows the HPC driver to optimize the padding requirement. The calculation may take into account
the number of empty and/or populated PCI Hot Plug* slots, the number of PCI-to-PCI bridges among the populated
slots, and other factors. This information is available only after initialization is complete. PCI-to-CardBus bridges
require memory resources before the initialization is started and therefore are considered an exception. The padding
requirements are relatively constant for PCI-to-CardBus bridges and an estimated value must be returned.
V-12.6. PCI Hot Plug PCI Initialization Protocol V-159UEFI Platform Initialization Specification, Release 1.8
marks the completion of HPC initialization.
The input parameters HpcDevicePath ,HpcPciAddress , and HpcState are described in
EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc() . The value of HpcPciAddress for the same root
HPC may be different from what was passed to I nitializeRootHpc() . The HPC’s configuration space must be
accessible at the specified HpcPciAddress until this function returns control.
The padding is returned in the form of ACPI (2.0 & 3.0) resource descriptors. The exact definition of each of the
fields is the same as in the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SubmitResources()
function. See the PCI HostBridge Code Definitions for the definition of this function.
The PCI bus driver is responsible for adding this resource request to the resource requests by the physical PCI
devices. If Attributes is EfiPaddingPciBus, the padding takes effect at the PCI bus level. If Attributes is Efi-
PaddingPciRootBridge, the required padding takes effect at the root bridge level. For details, see the definition of
EFI_HPC_PADDING_ATTRIBUTES in “Related Definitions” below.
Note that the padding request cannot ask for specific legacy resources such as COM port addresses. Legacy PC Card
devices may require such resources. Supporting these resource requirements is outside the scope of this specification.
// EFI_HPC_PADDING_ATTRIBUTES
// Describes how resource padding should be applied
EfiPaddingPciBus,
EfiPaddingPciRootBridge
} EFI_HPC_PADDING_ATTRIBUTES;
Following is a description of the fields in the above definition.
Table 12.2: EFI_HPC_PADDING_ATTRIBUTES field descriptions
EfiPaddingPciBus Apply the padding at a PCI bus level In other words the resources
that are allocated to the bus containing hot plug slots are padded by
thespecifiedamountIfthehotplugbusisbehindaPCItoPCIbridge
the PCI to PCI bridge apertures will indicate the padding
EfiPaddingPciRootBridge Apply the padding at a PCI root bridge level If a PCI root bridge
includes more than one hot plug bus the resource padding requests
forthesebusesareaddedtogetherandtheresourcesthatareallocated
to the root bridge are padded by the specified amount This strategy
mayreducethetotalamountofpaddingbutrequiresreprogramming
ofPCItoPCIbridgesinahotaddeventIfthehotplugbusisbehind
aPCI toPCIbridge thePCIto PCIbridgeapertures donotindicate
the padding for that bus
V-12.6. PCI Hot Plug PCI Initialization Protocol V-160UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The resource padding was successfullyreturned.
EFI_UNSUPPORTED This instance of the*EFI_PCI_HOT_PLUG_INIT_PROTOCOL*
does not support the specified HPC.
EFI_NOT_READY This function was called before HPCinitialization is complete.
EFI_INVALID_PARAMETER Padding is NULL.
EFI_OUT_OF_RESOURCES ACPI (2.0 & 3.0) resource descriptors for Padding cannot be allo-
cated due to insufficient resources.
V-12.7 PCI Hot Plug Request Protocol
A hot-plug capable PCI bus driver should produce the EFI PCI Hot Plug Request protocol. When a PCI device or a
PCI-like device (for example, 32-bit PC Card) is installed after PCI bus does the enumeration, the PCI bus driver can
benotifiedthroughthisprotocol. Forexample,whena32-bitPCCardisinsertedintothePCCardsocket,thePCCard
busdrivercancallinterfaceofthisprotocoltonotifyPCIbusdrivertoallocateresourceandcreatehandlesforthisPC
Card.
Summary
Provides services to notify PCI bus driver that some events have happened in a hot-plug controller (for example, PC
Card socket, or PHPC), and ask PCI bus driver to create or destroy handles for the PCI-like devices.
GUID
#define EFI_PCI_HOTPLUG_REQUEST_PROTOCOL_GUID \
{0x19cb87ab,0x2cb9,0x4665,0x83,0x60,0xdd,0xcf,0x60,0x54,\
0xf7,0x9d}
typedef struct \_EFI_PCI_HOTPLUG_REQUEST_PROTOCOL {
EFI_PCI_HOTPLUG_REQUEST_NOTIFY Notify;
} EFI_PCI_HOTPLUG_REQUEST_PROTOCOL;
Notify
NotifythePCIbusdriverthatsomeeventshavehappenedinahot-plugcontroller(forexample,PCCardsocket,
or PHPC), and ask PCI bus driver to create or destroy handles for the PCI-like devices. See Section 0 for a
detailed description.
TheEFI_PCI_HOTPLUG_REQUEST_PROTOCOLisinstalledbythePCIbusdriveronaseparatehandlewhenPCI
bus driver starts up. There is only one instance in the system. Any driver that wants to use this protocol must locate it
globally.
The EFI_PCI_HOTPLUG_REQUEST_PROTOCOL allows the driver of hot-plug controller, for example, PC Card
Bus driver, to notify PCI bus driver that an event has happened in the hot-plug controller, and the PCI bus driver is
requested to create (add) or destroy (remove) handles for the specified PCI-like devices. For example, when a 32-bit
PCCardisinserted,thisprotocolinterfacewillbecalledwithanaddoperation,andthePCIbusdriverwillenumerate
and start the devices inserted; when a 32-bit PC Card is removed, this protocol interface will be called with a remove
operation, and the PCI bus driver will stop the devices and destroy their handles.
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TheexistenceofthisprotocolrepresentsthecapabilityofthePCIbusdriver. Ifthisprotocolexistsinsystem,itmeans
PCI bus driver is hot-plug capable, thus together with the effort of PC Card bus driver, hot-plug of PC Card can be
supported. Otherwise, the hot-plug capability is not provided.
V-12.7.1 EFI_PCI_HOTPLUG_REQUEST_PROTOCOL.Notify()
Summary
ThisfunctionisusedtonotifyPCIbusdriverthatsomeeventshappenedinahot-plugcontroller,andthePCIbusdriver
is requested to start or stop specified PCI-like devices.
Prototype
typedef
(EFIAPI *EFI_PCI_HOTPLUG_REQUEST_NOTIFY) (
IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL *This,
IN EFI_PCI_HOTPLUG_OPERATION Operation,
IN EFI_HANDLE Controller,
IN OUT UINT8 NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
);
This
A pointer to the EFI_PCI_HOTPLUG_REQUEST_PROTOCOL instance. Type
EFI_PCI_HOTPLUG_REQUEST_PROTOCOL is defined in Section 0.

Summary
Prototype
typedef
);
This
Operation
The operation the PCI bus driver is requested to make. See “Related Definitions” for the list of legal values.
The handle of the hot-plug controller.
The remaining device path for the PCI-like hot-plug device. It only contains device path nodes behind the hot-
plug controller. It is an optional parameter and only valid when the Operation is a add operation. If it is NULL,
all devices behind the PC Card socket are started.
NumberOfChildren
Thenumberofchildhandles. Foraaddoperation,itisanoutputparameter. Foraremoveoperation,it’saninput
parameter. When it contains a non-zero value, children handles specified in ChildHandleBuffer are destroyed.
Otherwise, PCI bus driver is notified to stop managing the controller handle.
ChildHandleBuffer
Thebufferwhichcontainsthechildhandles. Foraaddoperation,itisanoutputparameterandcontainsallnewly
createdchildhandles. Foraremoveoperation,itcontainschildhandlestobedestroyedwhen NumberOfChildren
containsanon-zerovalue. ItcanbeNULLwhen NumberOfChildren is0. It’sthecaller’sresponsibilitytoallocate
and free memory for this buffer.
This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has happened on the
hot-plug controller. Currently, the operations include add operation and remove operation.
Ifitisaaddoperation,thePCIbusdriverwillenumerate,allocateresourcesfordevicesbehindthehot-plugcontroller,
and create handle for the device specified by RemainingDevicePath. The RemainingDevicePath is an optional param-
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eter. If it is not NULL, only the specified device is started; if it is NULL, all devices behind the hot-plug controller
arestarted. ThenewlycreatedhandlesofPCCardfunctionsarereturnedinthe ChildHandleBuffer ,togetherwiththe
number of child handle in NumberOfChildren .
If it is a remove operation, when NumberOfChildren contains a non-zero value, child handles specified in ChildHan-
dleBuffer are stopped and destroyed; otherwise, PCI bus driver is notified to stop managing the controller handle.
// EFI PCI HOTPLUG NOTIFY OPERATION
EfiPciHotPlugRequestAdd,
EfiPciHotplugRequestRemove
} EFI_PCI_HOTPLUG_OPERATION;
EfiPciHotplugRequestAdd
ThePCIbusdriverisrequestedtocreatehandlesforthespecifieddevices. Anarrayof EFI_HANDLE isreturned,
a NULL element marks the end of the array.
The PCI bus driver is requested to destroy handles for the specified devices.
EFI_SUCCESS The handles for the specified device have been created or destroyed
as requested and for an add operation the new handles are returned
in ChildHandleBuffer
EFI_INVALID_PARAMETER Operation is not a legal value
EFI_INVALID_PARAMETER Controller is NULL or not a valid handle
EFI_INVALID_PARAMETER NumberOfChildren is NULL
EFI_INVALID_PARAMETER ChildHandleBufferisNULLwhileOperationisìremoveîandNum-
berOfChildren contains a non zero value
EFI_INVALID_PARAMETER ChildHandleBuffer is NULL while Operation is ìaddî
EFI_OUT_OF_RESOURCES There are no enough resources to start the devices
V-12.8 Sample Implementation for a Platform Containing PCIHot
is critical. The activities related to PCI Hot Plug* are underlined. Please note that hot plug PCI devices may require
that multiple passes of bus enumeration are required.
There are several phases during the PCI bus enumeration process when PCI hot plug slots are present. At each phase,
thePlatformNotifyfunctionofthe EFI_PCI_PLATFORM_PROTOCOL andEFI_PCI_OVERRIDE_PROTOCOL will
be called with the execution phase BeforePciHostBridge. Then the PCI host bridge driver function NotifyPhase is
called. Finally, the PlatformNotify functions are called again, but with the execution phase AfterPciHostBridge .
1. IftheplatformsupportsPCIHotPlug,aninstanceofthe EFI_PCI_HOT_PLUG_INIT_PROTOCOL isinstalled.
2. The PCI enumeration process begins.
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3. Lookforinstancesofthe EFI_PCI_HOT_PLUG_INIT_PROTOCOL .Ifitisnotfound,allthehot-plugsubsystem
initialization steps can be skipped. If one exists, create a list of root Hot Plug Controllers (HPCs) by calling
4. Notify the drivers using EfiPciHostBridgeBeginBusAllocation .
5. For every PCI root bridge handle, do the following:
•CallEFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.StartBusEnumeration (This, Root-
BridgeHandle ).
•MakesureeachPCIrootbridgehandlesupportsthe EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL .SeetheUEFI
2.1`Specification for the definition of the PCI Root Bridge I/O Protocol.
•CallEFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.GetAllocAttributes() to get the at-
next step.
Scan all the devices in the specified bus range and the specified segment, one bus at a time. If the device is a PCI-to-
PCI bridge, update the bus numbers and program the bus number registers in the PCI-to-PCI bridge hardware. If the
devicepathofadevicematchesthatofarootHPCanditisnotaPCI-to-CardBusbridge,itmustbeinitializedbycalling
•Continue to scan devices on that root bridge and start the initialization of all root HPCs.
•CallEFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SetBusNumbers() so that the HPCs
6. Wait until all the HPCs that were found on various root bridges in step 5 to complete initialization.
7. Go back to step 5 for another pass and rescan the PCI buses. For all the root HPCs and the non-
root HPCs, call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.GetResourcePadding() to obtain the amount of
overallocation and add that amount to the requests from the physical devices. Reprogram the bus
numbers by taking into account the bus resource padding information. This action requires calling
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SetBusNumbers() . Therescanisnotre-
quired if there is only one root bridge in the system.
V-12.8. Sample Implementation for a Platform Containing PCIHot Plug* Slots V-164CHAPTER
THIRTEEN
SUPER I/O PROTOCOL
V-13.1 Super I/O Protocol
V-13.1.1 EFI_SIO_PROTOCOL
Summary
The Super I/O driver installs an instance of this protocol on the handle of every device within the Super I/O chip.
GUID
#define EFI_SIO_PROTOCOL_GUID \
{ 0x215fdd18, 0xbd50, 0x4feb, { 0x89, 0xb, 0x58, 0xca, \
0xb, 0x47, 0x39, 0xe9 } }
typedef struct \_EFI_SIO_PROTOCOL {
EFI_SIO_REGISTER_ACCESS RegisterAccess;
EFI_SIO_GET_RESOURCES GetResources;
EFI_SIO_SET_RESOURCES SetResources;
EFI_SIO_POSSIBLE_RESOURCES PossibleResources;
EFI_SIO_MODIFY Modify;
} EFI_SIO_PROTOCOL;
Parameter
RegisterAccess
Provides a low level access to the registers for the Super I/O.
GetResources
Provides a list of current resources consumed by the device in ACPI Resource Descriptor Format.
SetResources
Sets resources for a device.
PossibleResources
Provides a collection of possible resource descriptors for the device. Each resource descriptor in the collection
defines a combination of resources that can potentially be used by the device.
Modify
Provides an interface for table based programming of the Super I/O registers.
V-165UEFI Platform Initialization Specification, Release 1.8
The Super I/O Protocol is installed by the Super I/O driver. The Super I/O driver is a UEFI driver model compliant
driver. In the Start()routine of the Super I/O driver, a handle with an instance of EFI_SIO_PROTOCOL is created
for each device within the Super I/O. The device within the Super I/O is powered up, enabled, and assigned with the
default set of resources. In the Stop()routine of the Super I/O driver, the device is disabled and Super I/O protocol is
uninstalled.
V-13.1.2 EFI_SIO_PROTOCOL.RegisterAccess()
Summary
Prototype
typedef
(EFIAPI \*EFI_SIO_REGISTER_ACCESS) (
IN CONST EFI_SIO_PROTOCOL *This,

Modify
Summary
Prototype
typedef
IN BOOLEAN Write,
IN BOOLEAN ExitCfgMode,
IN UINT8 Register,
IN OUT UINT8 *Value
);
This
Indicates a pointer to the calling context.
Write
Specifiesthetypeoftheregisteroperation. Ifthisparameteris TRUE,Valueisinterpretedasaninputparameter
andtheoperationisaregisterwrite. Ifthisparameteris FALSE,Valueisinterpretedasanoutputparameterand
the operation is a register read.
ExitCfgMode
ExitConfigurationModeIndicator. Ifthisparameterissetto TRUE,theSuperI/Odriverwillturnoffconfigu-
ration mode of the Super I/O prior to returning from this function. If this parameter is set to FALSE, the Super
I/O driver will leave Super I/O in the configuration mode.
The Super I/O driver must track the current state of the Super I/O and enable the configuration mode of Super
I/O if necessary prior to register access.
Register
Register number.
Value IfWriteisTRUE,Valueis a pointer to the buffer containing the byte of data to be written to the Super I/O
register. If WriteisFALSE,Valueis a pointer to the destination buffer for the byte of data to be read from the Super
I/O register.
TheRegisterAccess() function provides low level interface to the registers in the Super I/O.
Note:This function only provides access to the internal registers of the Super I/O chip. For example, on a typical
desktop system, these are the registers accessed via the 0x2E/0x2F indexed port I/O. This function cannot be used to
access I/O or memory locations assigned to individual logical devices.
V-13.1. Super I/O Protocol V-166UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The operation completed successfully
EFI_INVALID_PARAMETER TheValueis NULL
EFI_INVALID_PARAMETER InvalidRegisternumber
V-13.1.3 EFI_SIO_PROTOCOL.GetResources()
Summary
Provides an interface to get a list of the current resources consumed by the device in the ACPI Resource Descriptor
format.
Prototype
typedef
(EFIAPI \*EFI_SIO_GET_RESOURCES)(
OUT ACPI_RESOURCE_HEADER_PTR *ResourceList
);
This
ResourceList
A pointer to an ACPI resource descriptor list that defines the current resources used by the device. Type
ACPI_RESOURCE_HEADER_PTR is defined in the “Related Definitions” below.
GetResources() returnsalistofresourcescurrentlyconsumedbythedevice. The ResourceList isapointertothebuffer
containing resource descriptors for the device. The descriptors are in the format of Small or Large ACPI resource
descriptorasdefinedbyACPIspecification(2.0&3.0). Thebufferofresourcedescriptorsisterminatedwiththe‘End
tag’ resource descriptor.
UINT8 Byte;
struct{
UINT8 Length : 3;
UINT8 Name : 4;
UINT8 Type : 1;
}Bits;
} ACPI_SMALL_RESOURCE_HEADER;
union {
struct{
UINT8 Name : 7;
}Bits;
V-13.1. Super I/O Protocol V-167UEFI Platform Initialization Specification, Release 1.8
} Header;
} ACPI_LARGE_RESOURCE_HEADER;
ACPI_SMALL_RESOURCE_HEADER *SmallHeader;
ACPI_LARGE_RESOURCE_HEADER *LargeHeader;
} ACPI_RESOURCE_HEADER_PTR;
Length
Length of the resource descriptor in bytes.
Name
Resource descriptor name. Possible values for this field are defined in the ACPI specification.
Type
Descriptor type. 0 - ACPI Small Resource Descriptor 1 - ACPI Large Resource Descriptor
EFI_SUCCESS The iperation completed successfully
EFI_INVALID_PARAMETER ResourceList is NULL
V-13.1.4 EFI_SIO_PROTOCOL.SetResources()
Summary
Sets the resources for the device.
Prototype
typedef
(EFIAPI *EFI_SIO_SET_RESOURCES)(
IN ACPI_RESOURCE_HEADER_PTR ResourceList
);
This
PointertotheACPIresourcedescriptorlist. Type ACPI_RESOURCE_HEADER_PTR isdefinedinthe“Related
Definitions” section of EFI_SIO_PROTOCOL.GetResources() .
SetResources() setstheresourcesforthedevice. ResourceList isapointertotheACPIresourcedescriptorlistcontaining
requested resources for the device.
V-13.1. Super I/O Protocol V-168UEFI Platform Initialization Specification, Release 1.8
EFI_INVALID_PARAMETER ResourceList is invalid
EFI_ACCESS_DENIED Some of the resources in ResourceList are in use
V-13.1.5 EFI_SIO_PROTOCOL.PossibleResources()
Summary
Provides a collection of resource descriptor lists. Each resource descriptor list in the collection defines a combination
of resources that can potentially be used by the device.
Prototype
typedef
(EFIAPI \*EFI_SIO_POSSIBLE_RESOURCES)(
OUT ACPI_RESOURCE_HEADER_PTR *ResourceCollection
);
This
ResourceCollection
Collection of the resource descriptor lists. Type ACPI_RESOURCE_HEADER_PTR is defined in the “Related
PossibleResources() returns a collection of resource descriptor lists. Each resource descriptor list in the collection
definesacombinationofresourcesthatcanpotentiallybeusedbythedevice. ThedescriptorsareintheformatofSmall
orLargeACPIResourceDescriptorasdefinedbythe ACPISpecification (2.0&3.0). Thecollectionisterminatedwith
the ‘End tag’ resource descriptor.
EFI_INVALID_PARAMETER ResourceCollection is NULL
V-13.1.6 EFI_SIO_PROTOCOL.Modify()
Summary
Provides an interface for a table based programming of the Super I/O registers.
Prototype
typedef
(EFIAPI \*EFI_SIO_MODIFY)(
IN CONST EFI_SIO_REGISTER_MODIFY *Command,
V-13.1. Super I/O Protocol V-169UEFI Platform Initialization Specification, Release 1.8
IN UINTN NumberOfCommands
);
This
Command
Apointertoanarrayof NumberOfCommandsEFI_SIO_REGISTER_MODIFY structures. Eachstructurespeci-
fiesasingleSuperI/Oregistermodifyoperation. Type EFI_SIO_REGISTER_MODIFY isdefinedinthe“Related
NumberOfCommands
Number of elements in the Command array.
TheModify()functionprovidesaninterfacefortablebasedprogrammingoftheSuperI/Oregisters. Thisfunctioncan
be used to perform programming of multiple Super I/O registers with a single function call. For each table entry, the
Registeris read, its content is bitwise ANDed with AndMask, and then ORed with OrMaskbefore being written back
to theRegister. The Super I/O driver must track the current state of the Super I/O and enable the configuration mode
ofSuperI/Oifnecessarypriortotableprocessing. Oncethetableisprocessed,theSuperI/Odevicehastobereturned
to the original state.
UINT8 AndMask;
UINT8 OrMask;
} EFI_SIO_REGISTER_MODIFY;
Register
AndMask
Bitwise AND mask.
OrMask
Bitwise OR mask.
EFI_INVALID_PARAMETER Command is NULL
V-13.1. Super I/O Protocol V-170CHAPTER
FOURTEEN
SUPER I/O AND ISA HOST CONTROLLER INTERACTIONS
V-14.1 Design Descriptions
ThePIarchitectureprovidesameanstointeractinastandardfashionwithSuperI/Odevices. Forthepurposesofthis
specification, the Super I/O is a device residing on an ISA or LPC or similar bus that consumes I/O and/or memory
resources and provides multiple standard logical devices, such as PC/AT compatible floppy, serial port, parallel port,
keyboard or mouse. There may be more than one of these devices behind each of the ISA/LPC buses.
Fig. 14.1: Super I/O and ISA Host Controller Interactions
V-171UEFI Platform Initialization Specification, Release 1.8
Mouse, Floppy, Serial and keyboard Drivers
The Mouse, Floppy, Serial and Keyboard drivers are UEFI driver-model drivers that support devices produced by the
SuperI/Ocomponent. Whenstarted,theyusetheoptionalSIOControlprotocoltoenablethelogicaldevice,toproduce
the standard UEFI protocols used for console or booting, such as Serial I/O or Block I/O. They typically examine the
device paths on the child handles created by the Super I/O drivers for the ACPI device path nodes that refer to their
devices (e.g. PNP0501, PNP0303, etc.).
Super I/O Driver
The Super I/O driver consists of a UEFI driver-model driver (in DXE) and PEIM (in PEI) that supports a Super I/O
component. TheSuperI/Ocomponentssupportmultiplelogicaldevices,suchasthePS/2keyboardcontroller,afloppy
controller or serial/IrDa controller. When started, the Super I/O driver verifies it is present on the board and produces

childhandlesforeachofthelogicaldevicesthatareenabled. OneachchildhandleitinstallsaninstanceoftheDevice
Path protocol, the SIO protocol and the SIO Control protocol.
ISA Bus Driver
TheISABusdriverconsistsofaUEFIdriver-modeldriver(DXEonly)thatproducestheISAHostControllerService
Binding protocol, which manages the many-to-one relationship between Super I/O drivers in the system and an ISA
Host Controller.
ISA Host Controller Driver
The ISA Host Controller driver is a DXE driver that supports a PCI-ISA or PCI-LPC bridge component. It creates a
child handle that represents the ISA Bus and installs the ISA Host Controller protocol and the Device Path protocol
with an ACPI device path node (PNP0A05/PNP0A06).
PCD
The Platform Configuration Database (PCD) provides configuration information about the device configuration. In-
formation concerning configured I/O addresses can be placed into the PCD by platform drivers and then used by the
various silicon drivers, including SIO to find base addresses and logical device configuration.
V-14.1.1 Super I/O
TheSuperI/ODXEdriverandPEIMencapsulatethefunctionalityoftheSuperI/Ocomponent. Theyarebothrespon-
sible to:
•Detectthepresenceofthecomponent,usinginformationfromthePCDandtheaperturesopenedbytheISAhost
•Configure the component and its logical devices using information from the PCD.
•Publish information about the component and the logical devices it supports using the SIO protocol/PPI.
V-14.1.1.1 DXE
The Super I/O DXE Driver is responsible for: - Producing the Driver Binding protocol’s Supported() ,Start()and
Stop()member functions on the driver image handle. - Installing the same GUID as used for the SioGuid member of
the Super I/O PPI on the image handle. This allows other drivers to detect which Super I/O is present in the system.
- Checking Super I/O controller presence. The Supported() function must check whether the Super I/O controller
is present in the system and whether the handle has an instance of the ISA Host Controller Service Binding protocol
installedonit. Formoreinformation,see“WorkingWithTheISABus”,below. -Creatingchildhandlesforeachlogical
device. The Start()functioncreatesachildhandleforeachlogicaldeviceusingtheISAHostControllerServiceBinding
protocolandinstallstheSIOandSIOControlprotocolsoneachone. Formoreinformation,see“WorkingWithLogical
Devices”, below.
V-14.1. Design Descriptions V-172UEFI Platform Initialization Specification, Release 1.8
V-14.1.1.1.1 Working with the ISA Bus
The system may contain an ISA bus bridge and zero or more Extended I/O bus bridges. The Super I/O driver checks
each of these to see whether it is present.
Supported()
The Super I/O DXE driver’s Driver Binding protocol Supported() function typically performs the following steps:
1. VerifiesthatthecontrollerhandlehasaninstalledinstanceoftheISAHostControllerServiceBindingprotocol.
2. Opens the apertures necessary to access the component’s configuration I/O address (i.e. 0x2e/0x2f) using the
ISA Host Controller protocol.
3. Verifiesthedevice’ssignaturetodeterminewhetherthecomponentisactuallypresentusingtheseconfiguration
I/O addresses. For example, it might read a device-specific register and check for a signature.
4. Closes the aperture and any opened protocols.
Start()
The Super I/O DXE driver’s Driver Binding protocol Start()function typically performs the following steps:
1. DetectswhetherSuperI/ODXEdriverisalreadymanagingthedeviceindicatedbytheconfigurationI/Oaddress.
One method of doing this is to create a Device Path with the configuration I/O address embedded in one device
node, then use LocateDevicePath to determine whether a child handle with the ISA Host Controller protocol
installed, exists.
2. Creates a child handle for the SIO using the ISA Host Controller Service Binding protocol.
•Opens the I/O apertures used for the configuration I/O address.
•Installs an instance of the Device Path and (optionally) the SIO and SIO Control protocol
3. Creates child handles for each logical device. Install an instance of the Device Path and SIO protocol and (op-
tionally) the SIO Control protocol on each child handle.
4. Installs an instance of the Device Path, SIO and SIO Control protocols on each of the child handles.
Stop()
The Super I/O DXE driver’s Driver Binding protocol Stop()function typically performs the following steps:
1. Uninstalls the instances of the Device Path, SIO and SIO control protocols from each of the child handles.
2. Destroys the Super I/O’s own child handle using the ISA Host Controller Service Binding protocol.
SetResources()
The Super I/O DXE driver’s SIO protocol SetResources() function typically calls the OpenIoAperture() andClo-
seIoAperture() member functions of the ISA Host Controller protocol for the I/O addresses related to the individual
logical devices.
V-14.1. Design Descriptions V-173UEFI Platform Initialization Specification, Release 1.8
V-14.1.1.1.2 Working with Logical Devices
TheSuperI/Ocontrollersupportsmanydifferentlogicaldevices. Someofthesedevices,suchasthefloppycontroller,
keyboard controller, MIDI controller and serial port are standard PC/AT devices. These drivers produce interfaces
based on these industry-standard interfaces. Also, the Super I/O component itself may act as a logical device.
For each logical device, the following steps are taken during Start():
1. Create a child handle.
2. Install the EFI_SIO_PROTOCOL (with correct current resource settings) on the child handle.
3. Installthe EFI_SIO_CONTROL_PROTOCOL onthesamechildhandle. Thisprotocolallowsastandarddrivers
tocorrectlyenableanddisabletheirresourceswhenthe Start()andStop()membersoftheDriverBindingprotocol
that they produce is called.
4. If the device implements one of the standard PC/AT devices, install the EFI_DEVICE_PATH_PROTOCOL by
appending a device node containing the ACPI HID of the PC/AT device to the device path of the ISA bus on
which it is installed.
For more information, see “Logical Devices”
V-14.1.1.2 PEI
The Super I/O PEIM is responsible to:
•Read its configuration information from the PCD.
•DetectiftheSuperI/Odeviceispresentinthesystem. Ifnecessary,itshouldopentheaperturerequiredtoaccess
the configuration registers using the ISA Host Controller PPI. If the Super I/O device is not detected, the driver
should close the aperture and exit immediately.
•Install the EFI_SIO_PPI for the Super I/O. The Identifier field allows consumers of the PPI to know which de-
vice’sregistersetcanbeaccessedbyusingthePPI’sfunctions,incaseswheremultipleSuperI/Osaresupported
on a platform.
•AllocateI/Oandmemoryresources. AllI/Oandmemoryresourcesareallocatedusingthe EFI_ISA_HC_PPI ,
which handles opening and closing bridge apertures.
The Super I/O PEIM should have the EFI_ISA_HC_PPI in its dependency expression.
V-14.1.2 ISA Bus
The ISA Bus is the logical device that manages the child devices attached to the ISA Host Controller.
ItconsumestheISAHostControllerprotocolproducedbytheISAHostControllerandinstallstheISAHostController
Service Binding protocol on the ISA Host Controller’s handle.
V-14.1. Design Descriptions V-174UEFI Platform Initialization Specification, Release 1.8
V-14.1.3 ISA Host Controller
The Host Controller is the device that translates the memory and I/O cycles from a parent device (such as a PCI bus)
into memory and I/O cycles for the target devices.
V-14.1.3.1 DXE
The ISA Host Controller driver creates a child handle for the ISA Host Controller and installs an instance of the ISA
Host Controller protocol and Device Path protocol on it. The Device Path instance for the child handle will have an
extraACPIdevicepathnodeforeitherPNP0A05(standardsubtractive-decodeISAbus)orPNP0A06(positive-decode
extended I/O bus). If a bridge device can support more than one of these simultaneously, the _UID field of the device
path node must contain a different value.
For PCI-ISA/LPC bridges, there are two classes of the ISA Host Controller Driver: generic and chipset-specific. The
genericISABusdriverconnectstoanystandardsubtractive-decodePCI-ISAbridgedevice(classcode:6,sub-class: 1,
programming I/F 0).
Chipset-specific ISA Bus Drivers are used for PCI-ISA (or PCI-LPC) bridges that support positive decode. These
bridges have device-specific mechanisms for opening and closing the I/O and memory apertures. These apertures
determine which address ranges will be passed through to devices attached to the ISA/LPC side of the bridge. In this
case,theregistrationprocessincludesopeningofaperturesandguaranteeingthatI/Oaccessfallswithintheaddresses
that go the specified bus.
The ISA Host Controller is responsible for reporting the actual address and size of the apertures using the DXE GCD
services.
V-14.1.3.2 PEI
The ISA Bus PEIM comes in two versions: generic and chipset-specific.
The generic version is used for subtractive-decode ISA (or LPC) buses. It implements the EFI_ISA_HC_PPI with a
device identifier of all zeroes. All of the aperture functions report EFI_UNSUPPORTED .

services.
The chipset-specific version implements the EFI_ISA_HC_PPI , which opens and close apertures for ISA/LPC buses
that are positive decode. The device identifier is filled in with the PCI PFA of the PCI-ISA bridge device.
V-14.1.4 Logical Devices
Logical Device drivers are UEFI driver model drivers that support many of the standard PC/AT peripherals. They are
designed to connect to the device paths produced by the Super I/O DXE driver. Each of these drivers produces the
DriverBindingandrelatedprotocolsusedinimplementingUEFIdrivermodeldrivers. Eachofthesedriverssupports
more than one instance of a specific device can be in a system. Calls to Stop()andStart()will disable or enable the
deviceandstopconsumptionofallsystemresources. ThisallowsSuperI/Odriverstobeloadedandunloaded. These
drivers can use the SIO Control protocol to enable consumption of system I/O and memory resources when they are
started or stopped.
V-14.1. Design Descriptions V-175UEFI Platform Initialization Specification, Release 1.8
V-14.2 Code Definitions
V-14.2.1 EFI_SIO_PPI
Summary
Super I/O register access.
GUID
#define EFI_SIO_PPI_GUID \
{0x23a464ad, 0xcb83, 0x48b8, \
{0x94, 0xab, 0x1a, 0x6f, 0xef, 0xcf, 0xe5, 0x22}}
typedef struct _EFI_SIO_PPI {
EFI_PEI_SIO_REGISTER_READ Read;
EFI_PEI_SIO_REGISTER_WRITE Write;
EFI_PEI_SIO_REGISTER_MODIFY Modify;
EFI_GUID SioGuid;
PEFI_SIO_INFO Info;
} EFI_SIO_PPI, *PEFI_SIO_PPI;
Members
Read
This function reads a register’s value from the Super I/O controller.
Write
This function writes a value to a register in the Super I/O controller.
Modify
This function modifies zero or more registers in the Super I/O controller using a table.
SioGuid
This GUID uniquely identifies the Super I/O controller.
Info
This pointer is to an array which maps EISA identifiers to logical devices numbers.
ThisPPIprovideslow-levelaccesstoSuperI/Oregistersusing Read()andWrite(). ItalsouniquelyidentifiesthisSuper
I/O controller using a GUID and provides mappings between ACPI-style PNP IDs and the logical device numbers.
There is one instance of this PPI per Super I/O device.
This PPI is produced by the Super I/O PEIM after the driver has determined that it is present in the system.
typedef struct _EFI_SIO_INFO {
EFI_ACPI_HID Hid;
EFI_ACPI_UID Uid;
UINT8 Ldn;
} EFI_SIO_INFO, *PEFI_SIO_INFO;
Hid
V-14.2. Code Definitions V-176UEFI Platform Initialization Specification, Release 1.8
This is the EISA-style Plug-and-Play identifier for one of the devices on the super I/O controller. The standard values
are:
EFI_ACPI_PNP_HID_KBC - 101/102-key Keyboard
EFI_ACPI_PNP_HID_LPT - Standard parallel port
EFI_ACPI_PNP_HID_COM - Standard serial port
EFI_ACPI_PNP_HID_FDC - Standard floppy controller
EFI_ACPI_PNP_HID_MIDI - Standard MIDI controller
EFI_ACPI_PNP_HID_GAME - Standard joystick controller
EFI_ACPI_PNP_HID_END - Specifies the end of the information list.
Uid
Thisistheuniquezero-basedinstancenumberforadeviceonthesuperI/O.Forexample,iftherearetwoserial
ports, one of them would have a Uid of 0 and the other would have a Uid of 1.
Ldn
ThisistheLogicalDeviceNumberforthislogicaldeviceintheSuperI/O.Thisvaluecanbeusedinthe Read()
andWrite()functions. The logical device number of EFI_SIO_LDN_GLOBAL indicates that global registers
typedef UINT32 EFI_ACPI_HID;
typedef UINT32 EFI_ACPI_UID;
#define EFI_ACPI_PNP_HID_KBC EFI_PNP_ID(0x0303)
#define EFI_ACPI_PNP_HID_LPT EFI_PNP_ID(0x0400)
#define EFI_ACPI_PNP_HID_COM EFI_PNP_ID(0x0500)
#define EFI_ACPI_PNP_HID_FDC EFI_PNP_ID(0x0700)
#define EFI_ACPI_PNP_HID_MIDI EFI_PNP_ID(0xB006)
#define EFI_ACPI_PNP_HID_END EFI_PNP_ID(0x0000)
#define EFI_ACPI_PNP_HID_GAME EFI_PNP_ID(0xB02F)
UINT8 Ldn;
V-14.2.1.1 EFI_SIO_PPI.Read()
Prototype
typedef
(EFIAPI \*EFI_PEI_SIO_REGISTER_READ) (
IN CONST EFI_SIO_PPI *This,
IN EFI_SIO_REGISTER Register,
V-14.2. Code Definitions V-177UEFI Platform Initialization Specification, Release 1.8
OUT UINT8 *IoData
);
A pointer to a pointer to the PEI Services.
This
A pointer to this instance of the EFI_SIO_PPI .
A boolean specifying whether the driver should turn on configuration mode (FALSE) or turn off configuration
mode (TRUE) after completing the read operation. The driver must track the current state of the configuration
mode (if any) and turn on configuration mode (if necessary) prior to register access.
Register
A value specifying the logical device number (bits 15:8) and the register to read (bits 7:0). The logical device
number of EFI_SIO_LDN_GLOBAL indicates that global registers will be used.
IoData
A pointer to the returned register value.
This function provides low-level read access to a device register. The register is specified as an 8-bit logical device
number and an 8-bit register value. The logical device numbers for specific SIO devices can be determined using the
Info member of the PPI structure.
If this function completes successfully, it will return EFI_SUCCESS andIoDatawill point to the returned Su-
per I/O register value. If the register value was invalid for this device or IoDatawas NULL, then it will return
EFI_INVALID_PARAMETERS . If the register could not be read within the correct amount of time, it will return
EFI_TIMEOUT .Ifthedevicehadsomesortoffaultorthedevicewasnotpresent,itwillreturn EFI_DEVICE_ERROR
.
Return Values
This function returns standard EFI status codes.
Status Code Value Description
EFI_SUCCESS Success.
EFI_TIMEOUT The register could not be read in a reasonable amount of time. The
exact time is device-specific.
EFI_INVALID_PARAMETERS Register was out of range for this device. IoDatawas NULL
EFI_DEVICE_ERROR There was a device fault or the device was not present.
EFI_TIMEOUT The register could not be read in the a reasonable amount of time. The exact time is
device-specific.
EFI_INVALID_PARAMETERS Register was out of range for this device.
IoDatawas NULL
V-14.2. Code Definitions V-178UEFI Platform Initialization Specification, Release 1.8
typedef UINT16 EFI_SIO_REGISTER;
#define EFI_SIO_REG(ldn,reg) (EFI_SIO_REGISTER)(((ldn)<<8)|reg)
#define EFI_SIO_LDN_GLOBAL 0xFF
V-14.2.1.2 EFI_SIO_PPI.Write()
Write a Super I/O register.
Prototype
typedef
(EFIAPI *EFI_PEI_SIO_REGISTER_WRITE) (
IN UINT8 IoData
);
This
A boolean specifying whether the device should turn on configuration mode (FALSE) or turn off configuration
mode (TRUE) after completing the write operation. The driver must track the current state of the configuration
Register
A value specifying the logical device number and the register to read. The logical device number can be deter-
minedbyusingtheSuperI/OchipspecificationorbylookingupthevalueintheInfofieldofthe EFI_SIO_PPI
. The logical device number of EFI_SIO_LDN_GLOBAL indicates that global registers will be used.
IoData
An 8-bit register value.
Status Code Return
EFI_INVALID_PARAMETERS Register was out of range for this deive. IoDatawas NULL
EFI_DEVICE_ERROR There was a device fault or ther device was not present.
This function provides low-level write access to a Super I/O register.
V-14.2. Code Definitions V-179UEFI Platform Initialization Specification, Release 1.8
The register is specified as an 8-bit logical device number and an 8-bit register value. The logical device numbers for
specific SIO devices can be determined using the Info member of the PPI structure.
.
V-14.2.1.3 EFI_SIO_PPI.Modify()
Summary
Prototype
typedef
(EFIAPI *EFI_SIO_MODIFY)(
);

.
Summary
Prototype
typedef
);
This
Command
A pointer to an array of NumberOfCommands EFI_SIO_REGISTER_MODIFY structures. Each structure
specifies a single Super I/O register modify operation. Type EFI_SIO_REGISTER_MODIFY is defined in
EFI_SIO_PROTOCOL.Modify() .
The number of elements in the Command array.
Registerisread,itscontentisbitwiseANDedwith AndMask ,andthenORedwith OrMaskbeforebeingwrittenback
ofSuperI/Oifnecessarypriortotableprocessing. Oncethetableisprocessed,theSuperI/Odevicemustbereturned
EFI_INVALID_PARAMETERS Command is NULL
V-14.2. Code Definitions V-180UEFI Platform Initialization Specification, Release 1.8
V-14.2.2 EFI_ISA_HC_PPI
GUID
#define EFI_ISA_HC_PPI_GUID \
{0x8d48bd70, 0xc8a3, 0x4c06, \
{0x90, 0x1b, 0x74, 0x79, 0x46, 0xaa, 0xc3, 0x58}}
typedef struct _EFI_ISA_HC_PPI {
UINT32 Address;
EFI_PEI_ISA_HC_OPEN_IO OpenIoAperture;
EFI_PEI_ISA_HC_CLOSE_IO CloseIoAperture;
} EFI_ISA_HC_PPI, \*PEFI_ISA_HC_PPI;
Members
Version
An unsigned integer that specifies the version of the PPI structure. Initialized to zero.
The address of the ISA/LPC Bridge device. For PCI, this is the segment, bus, device and function of the a
ISA/LPC Bridge device.
If bits 24-31 are 0, then the definition is:
Bits 0:2 - Function
Bits 3-7 - Device
Bits 8:15 - Bus
Bits 16-23 - Segment
Bits 24-31 - Bus Type
If bits 24-31 are 0xff, then the definition is platform-specific.
OpenIoAperture
Opens an aperture on a positive-decode ISA Host Controller.
CloseIoAperture
Closes an aperture on a positive-decode ISA Host Controller.
V-14.2.2.1 EFI_ISA_HC_PPI.OpenIoAperture()
Open I/O aperture.
Prototype
typedef
(EFIAPI \*EFI_PEI_ISA_HC_OPEN_IO) (
IN CONST EFI_ISA_HC_PPI *This,
V-14.2. Code Definitions V-181UEFI Platform Initialization Specification, Release 1.8
IN UINT16 IoAddress,
IN UINT16 IoLength,
OUT UINT64 *IoApertureHandle
);
A pointer to a pointer to the PEI Services Table.
This
A pointer to this instance of the EFI_ISA_HC_PPI .
IoAddress
An unsigned integer that specifies the first byte of the I/O space required.
IoLength
An unsigned integer that specifies the number of bytes of the I/O space required.
IoApertureHandle
ApointertothereturnedI/Oaperturehandle. Thisvaluecanbeusedonsubsequentcallsto CloseIoAperture() .
ThisfunctionopensanI/OapertureinaISAHostControllerfortheI/Oaddressesspecifiedby IoAddress toIoAddress
+IoLength - 1. It is possible that more than one caller may be assigned to the same aperture.
It may be possible that a single hardware aperture may be used for more than one device. This function tracks the
number of times that each aperture is referenced, and doesa not close the hardware aperture (via CloseIoAperture() )
until there are no more references to it.
If this function completes successfully, then it returns EFI_SUCCESS . If there is no available I/O aperture, then this
function returns EFI_OUT_OF_RESOURCES .
V-14.2.2.2 EFI_ISA_HC_PPI.CloseIoAperture()
Close I/O aperture.
Prototype
typedef
(EFIAPI \*EFI_PEI_ISA_HC_CLOSE_IO) (
IN UINT64 IoApertureHandle
);
This
The I/O aperture handle previously returned from a call to OpenIoAperture() .
V-14.2. Code Definitions V-182UEFI Platform Initialization Specification, Release 1.8
This function closes a previously opened I/O aperture handle. If there are no more I/O aperture handles that refer to
the hardware I/O aperture resource, then the hardware I/O aperture is closed.
number of times that each aperture is referenced, and does not close the hardware aperture (via CloseIoAperture() )
V-14.2.3 EFI_ISA_HC_PROTOCOL
Summary
Provides registration and enumeration of ISA devices.
GUID
#define EFI_ISA_HC_PROTOCOL_GUID \
{0xbcdaf080, 0x1bde, 0x4e22, \
{0xae, 0x6a, 0x43, 0x54, 0x1e, 0x12, 0x8e, 0xc4}}
typedef struct _EFI_ISA_HC_PROTOCOL {
EFI_ISA_HC_OPEN_IO OpenIoAperture;
EFI_ISA_HC_CLOSE_IO CloseIoAperture;
} EFI_ISA_HC_PROTOCOL, *PEFI_ISA_HC_PROTOCOL;
Members
Version
Theversionofthisprotocol. Higherversionnumbersarebackwardcompatiblewithlowerversionnumbers. The
current version is 0.
Open an I/O aperture.
Close an I/O aperture.
This protocol provides registration for ISA devices on a positive- or subtractive-decode ISA bus. It allows devices to
be registered and also handles opening and closing the apertures which are positively-decoded.
V-14.2.3.1 EFI_ISA_HC_PROTOCOL.OpenIoAperture()
Prototype
typedef
(EFIAPI \*EFI_ISA_HC_OPEN_IO) (
IN CONST EFI_ISA_HC_PROTOCOL *This,
V-14.2. Code Definitions V-183UEFI Platform Initialization Specification, Release 1.8
);
This
A pointer to this instance of the EFI_ISA_HC_PROTOCOL .
IoAddress
IoLength
+IoLength - 1.
V-14.2.3.2 EFI_ISA_HC_PROTOCOL.CloseIoAperture()
Prototype
typedef
(EFIAPI *EFI_ISA_HC_CLOSE_IO) (
);
This
V-14.2. Code Definitions V-184UEFI Platform Initialization Specification, Release 1.8
V-14.2.4 EFI_ISA_HC_SERVICE_BINDING_PROTOCOL
Summary
Manages child devices for an ISA Host Controller.
GUID
#define EFI_ISA_HC_SERVICE_BINDING_PROTOCOL_GUID \
{0xfad7933a, 0x6c21, 0x4234, \
{0xa4, 0x34, 0x0a, 0x8a, 0x0d, 0x2b, 0x07, 0x81}}
The protocol interface structure is the same for all service binding protocols and can be found in Section 10.6 (“EFI
Service Binding Protocol”).
The ISA Host Controller Service Binding protocol permits multiple Super I/O devices to use the services provide by
an ISA Host Controller. The function CreateChild() installs an instance of the ISA Host Controller protocol on each
child handle created.
V-14.2.5 EFI_SIO_CONTROL_PROTOCOL
Summary
Provide low-level services for SIO devices that enable them to be used in the UEFI driver model.
GUID
#define EFI_SIO_CONTROL_PROTOCOL_GUID \
{0xb91978df, 0x9fc1, 0x427d, \
{0xbb, 0x5, 0x4c, 0x82, 0x84, 0x55, 0xca, 0x27}}
typedef struct _EFI_SIO_CONTROL_PROTOCOL {
EFI_SIO_CONTROL_ENABLE EnableDevice;
EFI_SIO_CONTROL_DISABLE DisableDevice;
} EFI_SIO_CONTROL_PROTOCOL, PEFI_SIO_CONTROL_PROTOCOL;
Members
Version
EnableDevice
Enable a device.

Summary
GUID
Members
Version
V-14.2. Code Definitions V-185UEFI Platform Initialization Specification, Release 1.8
DisableDevice
Disable a device.
TheEFI_SIO_CONTROL_PROTOCOL provides control over the decoding of Super I/O and memory resources by
a logical device within a Super I/O. While the logical devices often implement industry standard interfaces (such as
PS/2 keyboard or serial port), these standard interfaces do not describe how to enable or disable the memory and I/O
resources for those devices. Instead, this control is usually implemented within the Super I/O device itself through
proprietary means. The industry standard drivers may utilize these functions in their implementations of the Driver
Binding protocol’s Start()andStop()functions.
The Super I/O driver installs this protocol on the same child handle as the EFI_SIO_PROTOCOL .
V-14.2.5.1 EFI_SIO_CONTROL_PROTOCOL.Enable()
Summary
Enable an ISA-style device.
Prototype
typedef
(EFIAPI \*EFI_SIO_CONTROL_ENABLE)(
IN CONST EFI_SIO_CONTROL_PROTOCOL *This
);
This
A pointer to this instance of the EFI_SIO_CONTROL_PROTOCOL .
This function enables a logical ISA device and, if necessary, configures it to default settings, including memory, I/O,
DMA and IRQ resources.
If the function completed successfully, then this function returns EFI_SUCCESS .
Ifthedevicecouldnotbeenabledbecausetherewereinsufficientresourceseitherforthedeviceitselforfortherecords
needed to track the device, then this function returns EFI_OUT_OF_RESOURCES .
Ifthisdeviceisalreadyenabled,thenthisfunctionreturns EFI_ALREADY_STARTED .Ifthisdevicecannotbeenabled,
then this function returns EFI_UNSUPPORTED .
V-14.2.5.2 EFI_SIO_CONTROL_PROTOCOL.Disable()
Summary
Disable a logical ISA device.
Prototype
typedef
(EFIAPI *EFI_SIO_CONTROL_DISABLE)(
);
V-14.2. Code Definitions V-186UEFI Platform Initialization Specification, Release 1.8
This
ThisfunctiondisablesalogicalISAdevicesothatitnolongerconsumessystemresources,suchasmemory,I/O,DMA
andIRQresources. Enoughinformationmustbeavailablesothatsubsequent Enable()callswouldproperlyreconfigure
the device.
If this function completed successfully, then it returns EFI_SUCCESS .
Ifthedevicecouldnotbedisabledbecausetherewereinsufficientresourceseitherforthedeviceitselforfortherecords
If this device is already disabled, then this function returns EFI_ALREADY_STARTED . If this device cannot be dis-
abled, then this function returns EFI_UNSUPPORTED .
V-14.2. Code Definitions V-187CHAPTER
FIFTEEN
CPU I/O PROTOCOL
ThisdocumentdescribestheCPUI/OProtocol. ThisprotocolprovidesanI/Oabstractionforasystemprocessor. This
protocol is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions. The I/O or
memory primitives can be used by the consumer of the protocol to materialize bus-specific configuration cycles, such
as the transitional configuration address and data ports for PCI. Only drivers that require direct access to the entire
system should use this protocol. This is a boot-services only protocol.
V-15.1 CPU I/O Protocol Terms
The following are the terms that are used throughout this document to describe the CPU I/O Protocol.
CPU I/O Protocol
A software abstraction that provides access to the I/O and memory regions in a single coherency domain.
SMP
Symmetric multiprocessing. A collection of processors that share a common view of I/O and memory-mapped
I/O.
V-15.2 CPU I/O Protocol2 Description
This section describes the CPU I/O Protocol. This protocol is used by code–typically PCI root bridge I/O drivers and
drivers that need I/O prior to the loading of the PCI root bridge I/O driver–that is running in the EFI Boot Services
environment to access memory and I/O.This protocol can be also used by non-PC-AT* systems to abstract the I/O
mechanism published by the processor and/or integrated CPU-I/O complex.
See Code Definitions for the definition of EFI_CPU_IO_PROTOCOL2 .
V-15.2.1 EFI CPU I/O Overview
The interfaces that are provided in the EFI_CPU_IO2_PROTOCOL are for performing basic operations to memory
and I/O. The system provides abstracted access to basic system resources to allow a driver to have a programmatic
method to access these basic system resources.
TheEFI_CPU_IO2_PROTOCOL allows for future innovation of the platform. It abstracts processor-device-specific
code from the system memory map. This abstraction allows system designers to make changes to the system memory
map without impacting platform-independent code that is consuming basic system resources.
V-188UEFI Platform Initialization Specification, Release 1.8
Systemswithonetomanyprocessorsinasymmetricmultiprocessing(SMP)configurationwillcontainasingleinstance
of theE FI_CPU_IO2_PROTOCOL . This protocol is an abstraction from a software point of view. This protocol is
attachedtothedevicehandleofaprocessordriver. TheCPUI/OProtocolistheparenttoasetofPCIRootBridgeI/O
Protocol instances that may contain many PCI segments. A CPU I/O Protocol instance might also be the parent of a
series of protocols that abstract host-bus attached devices.
CPU I/O Protocol instances are either produced by the system firmware or an EFI driver. When a CPU I/O Protocol
is produced, it is placed on a device handle without an EFI Device Path Protocol instance. The figure below shows a
device handle that has the EFI_CPU_IO2_PROTOCOL installed on it.
Fig. 15.1: EFI CPU I/O2 Protocol
EFI CPU I/O2 Protocol Other characteristics of the CPU I/O Protocol include the following:
•Theprotocolusesre-entrancytoenablepossibleusebyadebuggeragentthatisoutsideofthegenericEFITask
Priority Level (TPL) priority mechanism.
See Code Definitions for the definition of EFI_CPU_IO2_PROTOCOL.
V-15.3 Code Definitions
This section contains the basic definitions of the CPU I/O Protocol ( EFI_CPU_IO2_PROTOCOL ).
•EFI_CPU_IO_PROTOCOL_ACCESS
•EFI_CPU_IO_PROTOCOL_WIDTH
V-15.3. Code Definitions V-189UEFI Platform Initialization Specification, Release 1.8
V-15.3.1 CPU I/O Protocol
V-15.3.2 EFI_CPU_IO2_PROTOCOL
Summary
Provides the basic memory and I/O interfaces that are used to abstract accesses to devices in a system.
GUID
#define EFI_CPU_IO2_PROTOCOL_GUID \
{0xad61f191, 0xae5f, 0x4c0e, 0xb9, 0xfa, 0xe8, 0x69, 0xd2, \\
0x88, 0xc6, 0x4f}
typedef struct \_EFI_CPU_IO2_PROTOCOL {
EFI_CPU_IO_PROTOCOL_ACCESS Mem;
EFI_CPU_IO_PROTOCOL_ACCESS Io;
} EFI_CPU_IO2_PROTOCOL;
Mem.Read
Allows reads from memory-mapped I/O space. See the Mem.Read() function description. Type
EFI_CPU_IO_PROTOCOL_ACCESS is defined in “Related Definitions” below.
Mem.Write
Allows writes to memory-mapped I/O space. See the Mem.Write() function description.
Io.Read
Allows reads from I/O space. See the Io.Read() function description. Type
Io.Write
Allows writes to I/O space. See the Io.Write( ) function description.
TheEFI_CPU_IO2_PROTOCOL provides the basic memory and I/O interfaces that are used to abstract ac-
cesses to platform hardware. This hardware can include PCI- or host-bus-attached peripherals and buses. There
is oneEFI_CPU_IO2_PROTOCOL instance for each PI System. Embedded systems, desktops, and worksta-
tions will typically have only one PI System. Non-symmetric multiprocessing (non-SMP), high-end servers may
have multiple PI Systems. A device driver that wishes to make I/O transactions in a system will have to re-
trieve the EFI_CPU_IO2_PROTOCOL instance. A device handle for an PI System will minimally contain an
EFI_CPU_IO2_PROTOCOL instance.
// EFI_CPU_IO2_PROTOCOL_ACCESS
EFI_CPU_IO_PROTOCOL_IO_MEM Read;
EFI_CPU_IO_PROTOCOL_IO_MEM Write;
} EFI_CPU_IO_PROTOCOL_ACCESS;
Read
V-15.3. Code Definitions V-190UEFI Platform Initialization Specification, Release 1.8
Write
V-15.3.3 EFI_CPU_IO2_PROTOCOL.Mem.Read() and Mem.Write()
Summary
Enables a driver to access memory-mapped registers in the PI System memory space.
Prototype
typedef
(EFIAPI \*EFI_CPU_IO_PROTOCOL_IO_MEM) (
IN EFI_CPU_IO2_PROTOCOL *This,
IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
);
This

Read
Write
Summary
Prototype
typedef
);
This
A pointer to the EFI_CPU_IO2_PROTOCOL instance.
Width
Signifies the width of the memory operation. Type EFI_CPU_IO_PROTOCOL_WIDTH is defined in “Related
Address
The base address of the memory operation.
Count
The number of memory operations to perform. The number of bytes moved is Widthsize* Count, starting at
Address.
Buffer
TheMem.Read() andMem.Write() functions enable a driver to access memory-mapped registers in the PI System
The memory operations are carried out exactly as requested. The caller is responsible for satisfying any alignment
and memory width restrictions that a PI System on a platform might require. For example, on some platforms, width
requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.
IfWidthisEfiCpuIoWidthUint8 ,EfiCpuIoWidthUint16 ,EfiCpuIoWidthUint32 , orEfiCpuIoWidthUint64 , then both
AddressandBufferare incremented for each of the Countoperations that is performed. If WidthisEfiCpuIoWidth-
FifoUint8 ,EfiCpuIoWidthFifoUint16 ,EfiCpuIoWidthFifoUint32 , orEfiCpuIoWidthFifoUint64 , then only Bufferis
incrementedforeachofthe Countoperationsthatisperformed. Thereadorwriteoperationisperformed Counttimes
on the same Address.
V-15.3. Code Definitions V-191UEFI Platform Initialization Specification, Release 1.8
IfWidthisEfiCpuIoWidthFillUint8 ,EfiCpuIoWidthFillUint16,EfiCpuIoWidthFillUint32,orEfiCpuIoWidthFillUint64
, then only Addressis incremented for each of the Countoperations that is performed. The read or write operation is
performed Counttimes from the first element of Buffer.
// EFI_CPU_IO_PROTOCOL_WIDTH
EfiCpuIoWidthUint8,
EfiCpuIoWidthUint16,
EfiCpuIoWidthUint32,
EfiCpuIoWidthUint64,
EfiCpuIoWidthFifoUint8,
EfiCpuIoWidthFifoUint16,
EfiCpuIoWidthFifoUint32,
EfiCpuIoWidthFifoUint64,
EfiCpuIoWidthFillUint8,
EfiCpuIoWidthFillUint16,
EfiCpuIoWidthFillUint32,
EfiCpuIoWidthFillUint64,
EfiCpuIoWidthMaximum
} EFI_CPU_IO_PROTOCOL_WIDTH;
EFI_SUCCESS The data was read from or written to the PI System
EFI_INVALID_PARAMETER Width is invalid for this PI System
EFI_INVALID_PARAMETER Buffer is NULL
EFI_UNSUPPORTED The Buffer is not aligned for the given Width
EFI_UNSUPPORTED TheaddressrangespecifiedbyAddressWidthandCountisnotvalid
for this PI System
V-15.3.4 EFI_CPU_IO2_PROTOCOL.Io.Read() and Io.Write()
Summary
Enables a driver to access registers in the PI CPU I/O space.
Prototype
typedef
);
V-15.3. Code Definitions V-192UEFI Platform Initialization Specification, Release 1.8
This
Width
Signifies the width of the I/O operation. Type EFI_CPU_IO_PROTOCOL_WIDTH is defined in
EFI_CPU_IO2_PROTOCOL.Mem().
Address
The base address of the I/O operation. The caller is responsible for aligning the Addressif required.
Count
.
Buffer
TheIo.Read() and Io.Write() functions enable a driver to access PCI controller registers in the PI CPU I/O space.
width restrictions that a PI System on a platform might require. For example on some platforms, width requests of
EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.
AddressandBufferare incremented for each of the Countoperations that is performed.
IfWidthisEfiCpuIoWidthFifoUint8 ,EfiCpuIoWidthFifoUint16 ,EfiCpuIoWidthFifoUint32 , orEfiCpuIoWidthFi-
foUint64 , then only Bufferis incremented for each of the Countoperations that is performed. The read or write
operation is performed Counttimes on the same Address.
IfWidthisEfiCpuIoWidthFillUint8 ,EfiCpuIoWidthFillUint16 ,EfiCpuIoWidthFillUint32 , orEfiCpuIoWidthFil-
lUint64, then only Addressis incremented for each of the Countoperations that is performed. The read or write
operation is performed Counttimes from the first element of Buffer.
V-15.3. Code Definitions V-193CHAPTER
SIXTEEN
LEGACY REGION PROTOCOL
This section describes the legacy region protocol that abstracts the platform capability for the BIOS memory region
from 0xC0000 to 0xFFFFF. The Legacy Region Protocol is used to abstract the hardware control of the Option ROM
and Compatibility 16-bit code region shadowing.
V-16.1 Legacy Region Protocol
The Legacy Region Protocol controls the read, write and boot-lock attributes for the region 0xC0000 to
0xFFFFF. The table below lists the functions that are included in the Legacy Region Protocol. See
EFI_LEGACY_REGION2_PROTOCOL in Code Definitions for the definitions of these functions.
Table 16.1: Functions in Legacy Region Protocol
Decode Programs the chipset to decode or not decode regions in the 0xC0000 to
0xFFFFF range Governs the read attribute
Lock Programs the chipset to lock write protect regions in the 0xC0000 to 0xFFFFF
range Disables the write attribute
BootLock Programs the chipset to boot lock regions in the 0xC0000 to 0xFFFFF range
Enables the boot lock attribute
Unlock Programs the chipset to unlock regions in the 0xC0000 to 0xFFFFF range En-
ables the write attribute
GetInfo Get information about the granularity of the regions for each attribute
V-16.2 Code Definitions
V-16.2.1 Legacy Region Protocol
V-16.2.2 EFI_LEGACY_REGION2_PROTOCOL
Summary
Abstracts the hardware control of the physical address region 0xC0000-0xFFFFF.
GUID
#define EFI_LEGACY_REGION2_PROTOCOL_GUID \
{ 0x70101eaf, 0x85, 0x440c, 0xb3, 0x56, 0x8e, 0xe3, 0x6f,\
0xef, 0x24, 0xf0 }
V-194UEFI Platform Initialization Specification, Release 1.8
typedef struct \_EFI_LEGACY_REGION2_PROTOCOL {
EFI_LEGACY_REGION2_DECODE Decode;
EFI_LEGACY_REGION2_LOCK Lock;
EFI_LEGACY_REGION2_BOOT_LOCK BootLock;
EFI_LEGACY_REGION2_UNLOCK UnLock;
EFI_LEGACY_REGION_GET_INFO GetInfo;
} EFI_LEGACY_REGION2_PROTOCOL;
Decode
Modify the read attribute of a memory region. See the Decode() function description.
Lock
Modify the write attribute of a memory region to prevent writes. See the Lock()function description.
BootLock
Modify the boot-lock attribute of a memory region to prevent future changes to the memory attributes for this
region. See the BootLock() function description.
Unlock
Modify the write attribute of a memory region to allow writes. See the Unlock()function description.
GetInfo
Modify the write attribute of a memory region to allow writes. See the GetInfo() function description.
TheEFI_LEGACY_REGION2_PROTOCOL is used to abstract the hardware control of the memory attributes of the
Option ROM shadowing region, 0xC0000 to 0xFFFFF.
Therearethreememoryattributesthatcanbemodifiedthroughthisprotocol: read,writeandboot-lock. Theseproto-
cols may be set in any combination.
V-16.2.3 EFI_LEGACY_REGION2_PROTOCOL.Decode()
Summary
Modify the hardware to allow (decode) or disallow (not decode) memory reads in a region.
Prototype
typedef
(EFIAPI \*EFI_LEGACY_REGION2_DECODE) (
IN EFI_LEGACY_REGION2_PROTOCOL *This,
IN UINT32 Start,
IN UINT32 Length,
OUT UINT32 *Granularity,
IN BOOLEAN *On
);
This
Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
V-16.2. Code Definitions V-195UEFI Platform Initialization Specification, Release 1.8
Start
The beginning of the physical address of the region whose attributes should be modified.
Length
Thenumberofbytesofmemorywhoseattributesshouldbemodified. Theactualnumberofbytesmodifiedmay
be greater than the number specified.
The number of bytes in the last region affected. This may be less than the total number of bytes affected if the
starting address was not aligned to a region’s starting address or if the length was greater than the number of
bytes in the first region.
On
Decode / Non-Decode flag.
If the On parameter evaluates to TRUE, this function enables memory reads in the address range Start to (Start +
Length - 1).

Prototype
typedef
);
This
Start
Length
On
If theOnparameter evaluates to FALSE, this function disables memory reads in the address range Start to (Start +
EFI_SUCCESS The region s attributes were successfully modified
EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region
V-16.2.4 EFI_LEGACY_REGION2_PROTOCOL.Lock()
Summary
Modify the hardware to disallow memory writes in a region.
Prototype
typedef
(EFIAPI *EFI_LEGACY_REGION2_LOCK) (
OUT UINT32 *Granularity
);
This
Start
Length
V-16.2. Code Definitions V-196UEFI Platform Initialization Specification, Release 1.8
This function changes the attributes of a memory range to not allow writes.
V-16.2.5 EFI_LEGACY_REGION2_PROTOCOL.BootLock()
Summary
Modify the hardware to disallow memory attribute changes in a region.
Prototype
typedef
(EFIAPI *EFI_LEGACY_REGION2_BOOT_LOCK) (
);
This
Start
Length
This function makes the attributes of a region read only. Once a region is boot-locked with this function, the read and
writeattributesofthatregioncannotbechangeduntilapowercyclehasresettheboot-lockattribute. Callsto Decode()
,Lock()andUnlock()will have no effect.
EFI_SUCCESS The region s attributes were successfully locked
EFI_UNSUPPORTED Thechipsetdoesnotsupportlockingtheconfigurationregistersina
waythatwillnotaffectmemoryregionsoutsidethelegacymemory
region
V-16.2. Code Definitions V-197UEFI Platform Initialization Specification, Release 1.8
V-16.2.6 EFI_LEGACY_REGION2_PROTOCOL.UnLock()
Summary
Modify the hardware to allow memory writes in a region.
Prototype
typedef
(EFIAPI \*EFI_LEGACY_REGION2_UNLOCK) (
);
This
Start
Length
This function changes the attributes of a memory range to allow writes.
V-16.2.7 EFI_LEGACY_REGION2_PROTOCOL.GetInfo()
Summary
Get region information for the attributes of the Legacy Region.
Prototype
typedef
(EFIAPI \*EFI_LEGACY_REGION_GET_INFO) (
OUT UINT32 *DescriptorCount,
OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor
);
V-16.2. Code Definitions V-198UEFI Platform Initialization Specification, Release 1.8
This
DescriptorCount
The number of region descriptor entries returned in the Descriptor buffer. Type
EFI_LEGACY_REGION_DESCRIPTOR is defined in the “Related Definitions” section.
A pointer to a pointer used to return a buffer where the legacy region information is deposited. This buffer will
contain a list of DescriptorCount number of region descriptors. This function will provide the memory for the
buffer.
This function is used to discover the granularity of the attributes for the memory in the legacy region. Each attribute
may have a different granularity and the granularity may not be the same for all memory ranges in the legacy region.
EFI_SUCCESS The information structure was returned.
EFI_UNSUPPORTED This funtion is not supported.
LegacyRegionDecoded,
LegacyRegionNotDecoded,
LegacyRegionWriteEnabled,
LegacyRegionWriteDisabled,
LegacyRegionBootLocked,
LegacyRegionNotLocked
} EFI_LEGACY_REGION_ATTRIBUTE;
LegacyRegionDecoded
This region is currently set to allow reads.
LegacyRegionNotDecoded
This region is currently set to not allow reads.
LegacyRegionWriteEnabled
This region is currently set to allow writes.
LegacyRegionWriteDisabled
This region is currently set to write protected.
LegacyRegionBootLocked
This region’s attributes are locked, cannot be modified until after a power cycle.
This region’s attributes are not locked.
UINT32 Start;
EFI_LEGACY_REGION_ATTRIBUTE Attribute;
UINT32 Granularity;
} EFI_LEGACY_REGION_DESCRIPTOR;
V-16.2. Code Definitions V-199UEFI Platform Initialization Specification, Release 1.8
Start
The beginning of the physical address of this region.
Length
The number of bytes in this region.
Attribute
Attribute of the Legacy Region Descriptor that describes the capabilities for that memory region.
Describes the byte length programmability associated with the Startaddress and the specified Attribute setting.
V-16.2. Code Definitions V-200CHAPTER
SEVENTEEN
I2C PROTOCOL STACK
V-17.1 Design Discussion
The Inter-Integrated Circuit (I2C) protocol stack enables third party silicon vendors to write UEFI drivers for their
products by decoupling the I2C chip details from the I2C controller and I2C bus configuration details.
V-17.1.1 I2C Bus Overview
`<http://www.acpi.info/spec.htm> `__The Inter-Integrated Circuit (|I2C|) bus enables simple low speed communica-
tions between chips. The following sections describe the attributes of the |I2C| bus configurations supported by the
|I2C| protocol stack and the |I2C|-bus specification and user manual .
V-17.1.1.1 SingleMaster
Fig. 17.1: Simple 12C Bus
Simple12CBus showsasimpleI2CbusconfigurationconsistingofonehostcontrollerandtwoI2Cdeviceswhichuse
thesameI2Cclockfrequency. InthisconfigurationtheI2Chostcontrollergetsinitializedwithasingleclockfrequency
and performs transactions to the I2C devices using their slave addresses.
V-17.1.1.2 Multiple I2C Bus Frequencies
Fig. 17.2: Multiple I2C Bus Frequencies
V-201UEFI Platform Initialization Specification, Release 1.8
TwoI2Cbusconfigurationsareshownin MultipleI2CBusFrequencies ,separatedbyaswitch. ThisallowstheI2Cbus
to operate at two different frequencies depending on the state of the switch. Device requiring higher bus frequencies
are placed closer to the I2C host controller and are accessed when the switch is turned off. Devices using lower bus
frequenciesareplacedaftertheswitchandmayonlybeaccessedwhentheswitchison. NotethattheI2Cbusfrequency
needs to be set to a frequency supported by all devices currently accessible by the I2C host controller.
V-17.1.1.3 Limited Address Space
Fig. 17.3: Limited Address Space
|I2C|deviceshavealimitednumberofaddresssettings,sometimesonlyone. Whenthehardwaredesignrequiresmore
|I2C| devices than the address space supports a multiplexer may be introduced to create additional bus configurations
(address spaces). Note that the host must first select the appropriate bus configuration before communicating with the
|I2C| device.
V-17.1.1.4 I2C Bus Configurations
A bus configuration is a concept introduced by the I2C protocol stack to configure the state of the switches and multi-
plexersintheI2Cbus. TheI2Cprotocolstackcallsintotheplatformcodewithavaluefromzero(0)toN-1torequest

the platform code enable a specific configuration of the switches and multiplexers. The platform code then sets the
requestedstatefortheswitchesandmultiplexersandsetstheI2CclockfrequencyforthisI2Cbusconfiguration. Upon
return the I2C protocol stack is able to access the I2C devices in this configuration.
V-17.1.2 2C Protocol Stack Overview
The following is a representation of the I2C protocol stack and an I2C bus layout.
I2C Protocol Stack The platform hardware designer chooses the bus layout based upon the platform, I2C chip and
software requirements. The design uses switches to truncate the bus to enable higher bus frequencies for a subset of
deviceswhichare placedclosertothecontroller. Whentheswitch ison,theextendedbus mustoperateatalower bus
frequency. The design uses multiplexer to create separate address spaces enabling the use of multiple devices which
would otherwise have conflicting addresses. See the |I2C|-bus specification and user manual for more details.
N.B. Some operating systems may prohibit the changing of switches and multiplexers in the I2C bus. In this case the
platformhardwareandsoftwaredesignersmustselectasingleI2Cbusconfigurationconsistingofconstantinputvalues
fortheswitchesandmultiplexers. TheI2CsubsystemmustbeplacedintheOScompatibleI2Cbusconfigurationupon
successful completion of ExitBootServices() .
The platform hardware designer needs to provide the platform software designer the following data for each I2C bus:
1. Which controller controls this bus
2. A list of logic blocks contained in one or more I2C devices:
•I2C device which contains this logic block
V-17.1. Design Discussion V-202UEFI Platform Initialization Specification, Release 1.8
Fig. 17.4: I2C Protocol StackV-17.1. Design Discussion V-203UEFI Platform Initialization Specification, Release 1.8
•Logic block I2C slave address
•Logic block description
3. For each configuration of the switches and multiplexers in the I2C bus
•What is the maximum frequency of operation for the I2C bus
•What I2C slave addresses are accessible
4. The settings for the switches and multiplexers when control is given to the operating system.
V-17.1.2.1 Handles
The I2C protocol stack uses two groups of handles:
•I2C controller handles
•I2C device handles
Somebusdriver(PCI,USB,etc.) ortheplatformspecificcodemayexposeahandleforeachoftheI2Ccontrollers. The
platformspecificcodeinstallstheI2CbusconfigurationmanagementandI2Cenumerationprotocolsonthecontroller
handle. AstheI2Cstackisinitialized,additionalprotocolsareplacedontheI2Ccontrollerhandle. WhentheI2Cstack
initialization is complete, the controller handle contains:
Fig. 17.5: Controller Handle After I2C Stack Initialization
The I2C Bus Driver uses the EFI_I2C_ENUMERATE_PROTOCOL to enumerate the set of I2C devices connected to
an I2C controller, and creates an I2C device handle for each I2C device installing the following protocols on each:
Fig. 17.6: I2C Protocol Stack after EFI_I2C_ENUMERATE_PROTOCOL
ItispossiblefortheSMBusHostControllerProtocoltobeimplementedusingtheservicesonanI2CControllerHandle.
The SMBus Host Controller Protocol does not support the concept of multiple bus configurations, so the state of the
I2C controller handle required for the SMBus Host Controller Protocol to be produced on an I2C Controller Handle is
V-17.1. Design Discussion V-204UEFI Platform Initialization Specification, Release 1.8
Fig. 17.7: State of the Required I2C Controller Handle
V-17.1.2.2 Driver Loading Order
A race condition potentially exists between the platform specific code and a layered SMBus driver when
a driver for a PCI or USB I2C controller installs the EFI_I2C_MASTER_PROTOCOL on its handle.
The layered SMBus driver may start on this controller as soon as the EFI_I2C_MASTER_PROTOCOL
is installed as long as the EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL is not in-
stalled on the controller handle. However if the platform specific code wants to use this controller with
theEFI_I2C_HOST_PROTOCOL then the platform specific code needs to prevent the SMBus driver
from starting by installing the EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL . Note
that the I2C host protocol opens the EFI_I2C_MASTER_PROTOCOL only if the handle contains the
EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL .
Chapter10oftheUniversalExtensibleFirmwareInterfaceSpecificationdescribesseveralwaysfortheplatformspecific
code to adjust the driver load order. One possible way to eliminate this race condition is to use the version number
for the driver binding protocol. The platform specific code implements the driver binding protocol’s Supported() and
Start()routines and sets the version field to a value in the range of 0xfffffff0 - 0xffffffff . The SMBus driver should
set the version field of the driver binding protocol to a value in the range of 0x00000010 - 0xffffffef . This selection
delays the SMBus driver to execute its Supported() andStart()routines after the platform specific code, enabling
the platform specific code to install the EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL and the
EFI_I2C_ENUMERATE_PROTOCOL on the controller’s handle.
V-17.1.2.3 Third Party I2C Drivers
Third party I2C drivers are I2C chip specific but platform and host controller independent.
Third party I2C driver writers, typically silicon vendors, need to provide:
•The vendor specific GUID that is used to select their driver.
•I2C slave address array guidance (described below) when the I2C device uses more than one I2C slave address
consisting of the order for the blocks of logic that get referenced by the entries in the slave address array.
The hardware version of the I2C device, this value is passed to the third party I2C driver to enable it to perform
workarounds for the specific hardware version. It is recommended that value match the value in the ACPI _HRV
tag. Seethe AdvancedConfigurationandPowerInterfaceSpecification,Revision5.0 forthefieldformatandthe Plug
and play support for |I2C| web-page for restriction on values.
The third party I2C driver uses relative addressing to abstract the platform specific details of the I2C device. Using an
example I2C device containing an accelerometer and a magnetometer which consumes two I2C slave addresses, one
for each logic block. The third party I2C driver writer may choose to write two drivers, one for each block of logic, in
which case each driver refers to the single I2C slave address using the relative value of zero (0). However if the third
party I2C driver writer chooses to write a single driver which consumes multiple I2C slave addresses then the third
party I2C driver writer needs to convey the order of the I2C slave address entries in the I2C slave address array to the
platform software designer. For the example:
V-17.1. Design Discussion V-205UEFI Platform Initialization Specification, Release 1.8
0: Accelerometer
1: Magnetometer
The platform hardware designer picks the actual slave addresses from the I2C device’s data sheet and provides this
informationtotheplatformsoftwaredesigner. TheplatformsoftwaredesignerthenplacestheI2Cslaveaddressesinto
the I2C slave address array in the EFI_I2C_ENUMERATE_PROTOCL in the order specified by the third party I2C
driver writer. The third party I2C driver writer uses the index into the I2C slave address array as the relative I2C slave
address. TheI2CIOprotocolusestheI2CslaveaddressarraytotranslatetherelativeI2Cslaveaddressintotheplatform
specific I2C slave address. The relative value always starts at zero (0) and its maximum value is the number of entries
in I2C slave address array minus one.
EachI2Cslaveaddressentryisspecifiedasa32-bitintegertoallowroomforfutureI2Cslaveaddressexpansion. Only
theI2CmasterprotocolknowsthemaximumI2Cslaveaddressvalue. Allotherdriversandapplicationsmustlookfor
theEFI_NOT_FOUND status for the indication that a reserve bit was set in the I2C slave address.
Fig. 17.8: v5 i2c protocol stack
Fig. 17.9: v5 i2c protocol stack
V-17.1.2.3.1 Driver Binding Protocol Supported() API
The driver binding protocol’s Supported() routine looks for controllers which declare the EFI_I2C_IO_PROTOCOL
and match the device path supplied by the silicon vendor or third party I2C driver writer to the platform integrator.
The third party I2C device driver creates a GUID for a Vendor-Defined Hardware Device Path Node when describing
theI2Cdevice. ThethirdpartyI2CdevicedriverwriterprovidesthisGUIDtothepersonwritingtheplatformspecific
code to identify the type of I2C device.
ThethirdpartyI2Cdriverwhichconsumesthe EFI_I2C_IO_PROTOCOL comparestheknownGUIDwiththeGUID
pointed to by the DeviceGuid field.
An example algorithm for the driver binding protocol Supported() routine:
1. Open the EFI_I2C_IO_PROTOCOL usingEFI_OPEN_PROTOCOL_BY_DRIVER
2. If OpenProtocol() fails return the error status
3. Get the vendor GUID from the EFI_I2C_IO_PROTOCOL
4. Close the EFI_I2C_IO_PROTOCOL
5. Compare the expected vendor GUID to the GUID from the EFI_I2C_IO_PROTOCOL structure.

6. If the GUIDS don’t match then return EFI_NOT_SUPPORTED
7. Return EFI_SUCCESS
V-17.1. Design Discussion V-206UEFI Platform Initialization Specification, Release 1.8
V-17.1.2.3.2 Supporting Multiple Hardware Versions
Note that package markings are important to allow the platform integrator to verify the hardware revision
after the part is integrated! The platform integrator includes the hardware revision information into the
EFI_I2C_ENUMERATE_PROTOCOL .TheI2CbusdrivergetsthisdataduringtheI2Cdeviceenumerationandmakes
itavailabletothethirdpartyI2Cdevicedriverviathe EFI_I2C_IO_PROTOCOL .Thereareacoupleofwaysinwhich
the silicon vendor or third party I2C driver writer may support multiple hardware versions of the I2C device:
•Provide a different GUID value to the platform integrator for each hardware revision
•Provide a different hardware version value to the platform integrator with the devices
EachoftheabovemethodsdescribesaninterfacetotheI2Cdevice. Theinterfacespecifiesthenumberofslaveaddresses
as well as the features and software workarounds for the I2C device.
V-17.1.2.4 I2C IO Protocol
The I2C IO protocol is platform, host controller, and I2C chip independent.
The I2C bus driver creates a handle for each of the I2C devices returned by the I2C enumerate protocol. The I2C
controller’sdevicepathisextendedwiththevendorGUIDanduniqueIDvaluereturnedbytheI2Cenumerateprotocol
andattachedtothehandle. ThevendorGUIDisusedtoextendthedevicepathwithaVendor-defineHardwareDevice
PathNodeandtheuniqueIDisusedtofurtherextendthedevicepathwithaControllerDevicePathNode. Iftheunique
ID is 0, then the Controller Device Path Node is optional. The third party I2C device driver uses the device GUID to
determine if it may connect.
When a third party I2C device driver or application calls QueueRequest() , the I2C IO protocol validates the SlaveAd-
dressIndex (relative I2C address) for the I2C device and then converts the SlaveAddressIndex to a I2C slave address.
The request is then passed to the I2C host protocol along with the tuple BusConfiguration:I2C slave address.
V-17.1.2.5 I2C Host Protocol
The I2C host protocol is platform, host controller, and I2C chip independent.
Note:For proper operation of the I2C bus, only the I2C IO protocol and I2C test applications connect to the
EFI_I2C_HOST_PROTOCOL .
The I2C host protocol may access any device on the I2C bus. The I2C host protocol has the following responsibilities:
•Limits the number of requests to the I2C master protocol to one. The I2C host protocol holds on to additional
requests until the I2C master protocol is available to process the request. The I2C requests are issued in FIFO
order to the I2C master protocol.
•Enable the proper I2C bus configuration before starting the I2C request using the I2C master protocol
I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress. I2C bus configuration zero (0) is the portion
of the I2C bus that connects to the host controller. The bus configuration specifies the control values for the switches
and multiplexers in the I2C bus. After the switches and multiplexers are properly configured, the I2C controller uses
the slave address to access the requested I2C device.
SincetheI2CprotocolstacksupportsasynchronoustransactionstheI2ChostprotocolmaintainsaqueueofI2Crequests
untiltheI2Ccontrollerisavailablethem. Whenarequestreachestheheadofthequeuethenecessarybusconfiguration
is enabled and then the request is sent to the I2C master protocol.
V-17.1. Design Discussion V-207UEFI Platform Initialization Specification, Release 1.8
V-17.1.2.6 I2C Master Protocol
The I2C master protocol is I2C controller specific but platform independent.
Thisprotocolisdesignedtoallowtheimplementationtobebuiltasadriverwhichmaybedeliveredinbinaryformas
an EFI image.
The master protocol manipulates the I2C controller to perform a transaction on the I2C bus. The I2C master protocol
does not configure the I2C bus so it is up to the caller to ensure that the I2C bus is in the proper configuration before
issuing the I2C request.
The I2C master protocol typically needs the following information:
•Host controller address
•Controller’s input clock frequency
DependingupontheI2Ccontroller,moredatamaybenecessary. Thisprotocolmayuseanymethodtogetthesevalues:
hard coded values, PCD values, or may choose to communicate with the platform specific code using an undefined
mechanism to get these values.
If the I2C master protocol requires data from the platform specific code then the I2C master protocol writer needs to
provide the platform interface details to the platform software designer.
V-17.1.2.7 Platform Specific Code
The platform specific code installs the EFI_I2C_ENUMERATE_PROTOCOL to provide the I2C device descriptions
tothe I2Cbus driverusing the EFI_I2C_DEVICE structure. Thesedescriptions includethe busconfiguration number
required for the I2C device, the slave address array, the vendor GUID and a unique ID value.
TheEFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL enables the I2C host protocol to call into the
platformspecificcodetoenableaspecificI2CbusconfigurationandsettheI2Cbusfrequency. Thisprotocolisrequired
to get the I2C host protocol to start for the I2C controller’s handle.
The platform software designer collects the data requirements from third party I2C driver writers, the ven-
dor specific I2C master protocol writer, the EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL and
EFI_I2C_ENUMERATE_PROTOCOL .Theplatformsoftwaredesignergetsthenecessarydatafromtheplatformhard-
ware designer. The platform software designer then builds the data structures and implements the necessary routines
to construct the platform specific code for I2C.
V-17.1.2.8 Switches and Multiplexers
There are some I2C switches and I2C multiplexers where the control is done via I2C commands. When the con-
trol inputs come via the same I2C bus that is being configured then the platform specific code must use the
EFI_I2C_MASTER_PROTOCOL . While the I2C host protocol makes the call to EnableI2cBusConfiguration to con-
figure the I2C bus, the I2C host protocol keeps the I2C master protocol idle, enabling the platform specific code to
perform the necessary I2C configuration transactions.
If however the configuration control is done via an I2C device connected to a different I2C bus (host controller), then
the platform software designer may choose between the following:
•Call into a third party I2C driver to manipulate the I2C bus control device.
•Call into the EFI_I2C_IO_PROTOCOL if no third party I2C driver exists for the I2C bus control device
•Call into the EFI_I2C_HOST_PROTOCOL if the platform does not expose the I2C bus control device.
V-17.1. Design Discussion V-208UEFI Platform Initialization Specification, Release 1.8
V-17.1.3 PCI Comparison
PCI provides several features to describe the device to the operating system as well decoupling the driver from the
specific platform.
V-17.1.3.1 Device Description
PCIusesthe VendorID andDeviceID fieldsinconfigurationspacetoidentifythepieceofhardware. WheretheVendor
ID is assigned by the PCI committee and the Device ID is assigned by the hardware manufacture.
PCIalsousesthe BaseClass ,SubClass andProgrammingInterface fieldstohelpidentifytheoperatingsystemdriver.
The I2C protocol stack uses the vendor GUID associated with the I2C device to identify the UEFI driver. This GUID
issuppliedbythesiliconvendororthirdpartyI2CdriverwritertotheplatformintegratorandgetsincludedintheI2C
platform driver. The EFI_I2C_ENUMERATE_PROTOCOL provides this GUID to the I2C bus driver during the I2C
bus enumeration.
Thedriverbindingprotocol’s Supported() routineofthethirdpartyI2Cdevicedriverlooksforcontrollerswhichhave
theEFI_I2C_IO_PROTOCOL and have a match for the vendor GUID.
V-17.1.3.2 Hardware Features and Workarounds
PCI provides a Revision ID field to allow the driver to determine which version of hardware is present and which
features and software workarounds are necessary to support this device.
The I2C protocol stack uses the HardwareRevision field in the EFI_I2C_IO_PROTOCOL for this same purpose. It is
recommendedthatthisvaluematchthe_HRVvalueintheDSDTforthisI2Cdevice. Seethe AdvancedConfiguration
and Power Interface Specification, Revision 5.0 for the field format and the Plug and play support for |I2C| web-page
for restriction on values.
V-17.1.3.3 Device Relative Addressing
PCIprovides BaseAddressRegisters (BARs)todecouplethedevicedriversoftwarefromthedetailsoftheplatform’s
PCI bus configuration. Typically, all device register references are fixed offsets from one of the BAR addresses.
TheI2Cprotocolstackprovidesasimilarmechanismusinganindexintoanarrayofslaveaddresses. Thesiliconvendor
orthirdpartydriverwriterprovidesthestructureofthearraylistingthemajorfunctionstotheplatformintegrator. An
example is:
1: Compass
The platform integrator works with the platform’s hardware designer to get the I2C slave addresses of the I2C device

1: Compass
andbuildsthearraywhichisincludedintheplatformspecificcode. DuringI2Cdeviceenumeration,thisarrayispassed
to the I2C bus driver for use by the I2C IO protocol.
ThethirdpartyI2CdriverreferencesthemajorcomponentswithintheI2Cdeviceusingtheindexvalues,thusremaining
platformindependent. TheI2CIOprotocolperformsthearraylookup,translatingtheindexintoanactualslaveaddress
on the I2C bus.
MostI2CdevicesonlyhaveasingleI2CslaveaddressandthusthethirdpartyI2Cdevicedriverwillonlyuseindexzero
(0). Also depending upon the I2C device architecture, the silicon vendor or third party I2C device writer may choose
to write multiple drivers, each supporting a single I2C slave address.
V-17.1. Design Discussion V-209UEFI Platform Initialization Specification, Release 1.8
V-17.1.4 Hot Plug Support
I2C protocol stack enables the platform specific code to support hot-plug with the following algorithm:
1. Describe all possible devices on all possiblebusses, including the hot-plug devices.
2. The platform specific code detects hot-plug events: Add and Remove
3. For a removal event:
•The platform specific code opens the EFI_I2C_IO_PROTOCOL on the hot-plug device’s handle exclu-
sively. Thisoperationtearsdownanyupperlayerprotocolsonthishandle. Notethattheopenrequestmay
fail if I/O is pending in the lower protocols.
•When the step above fails, delay below TPL_NOTIFY to allow the current I
•2C transaction complete and then retry until the open is successful
•After the open is successful, the platform specific code may use the I
•2C IO protocol to perform I2C transactions for device probing.
4. For an add event:
•TheplatformspecificcodewaitsforcompletionanyoutstandingI/Othattheplatformspecificcodeinitiated
on the hot-plug I2C device.
•The platform specific code closes the EFI_I2C_IO_PROTOCOL
•The platform specific code issues a ConnectController() on the hot-plug device’s handle. This causes the
protocol stack which uses the hot-plug device to be reloaded.
V-17.2 DXE Code definitions
The I2C protocol stack consists of the following protocols:
•EFI_I2C_IO_PROTOCOL -ThirdpartysiliconvendorsusethisprotocoltoaccesstheirI2Cdevice. Thisprotocol
enables a driver or application to perform I/O transactions to a single I2C device independent of the I2C bus
configuration.
•EFI_I2C_HOST_PROTOCOL -TheI2Cbusdriverusesthisprotocoltoproducethe EFI_I2C_IO_PROTOCOL
that provides access a device on the I2C bus.
•EFI_I2C_MASTER_PROTOCOL -TheI2ChostprotocolusesthisprotocoltomanipulatetheI2Chostcontroller
and perform transactions as a master on the I2C bus.
•EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL -TheI2Chostprotocolusesthisprotocolto
request the proper state for the switches and multiplexers in the I2C bus and set the I2C clock frequency.
•EFI_I2C_ENUMERATE_PROTOCOL - The I2C bus driver uses this protocol to enumerate the devices on the
I2C bus, getting the bus configuration and an array of slave addresses for each of the I2C devices.
The following sections describe these protocols in detail.
V-17.2. DXE Code definitions V-210UEFI Platform Initialization Specification, Release 1.8
V-17.2.1 I2C Master Protocol
V-17.2.2 EFI_I2C_MASTER_PROTOCOL
Summary
This protocol manipulates the I2C host controller to perform transactions as a master on the I2C bus using the current
state of any switches or multiplexers in the I2C bus.
GUID
#define EFI_I2C_MASTER_PROTOCOL_GUID \
{ 0xcd72881f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, \
0xa8, 0x11, 0x74, 0x62 }}
typedef struct \_EFI_I2C_MASTER_PROTOCOL {
EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY SetBusFrequency;
EFI_I2C_MASTER_PROTOCOL_RESET Reset;
EFI_I2C_MASTER_PROTOCOL_START_REQUEST StartRequest;
CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;
} EFI_I2C_MASTER_PROTOCOL;
SetBusFrequency
Set the clock frequency for the I2C bus.
Reset
Reset the I2C host controller.
StartRequest
Start an I2C transaction in master mode on the host controller.
I2cControllerCapabilities
Pointertoan EFI_I2C_CONTROLLER_CAPABILITIES datastructurecontainingthecapabilitiesoftheI2Chost
TheEFI_I2C_MASTER_PROTOCOL istypicallyusedbytheI2ChostprotocoltoperformtransactionsontheI2Cbus.
ThisprotocolmayalsobeusedtoconfiguretheI2CclockfrequencyanduseI2Ctransactionstosetthestateofswitches
and multiplexers in the I2C bus.
A10-bitslaveaddressisor’edwiththefollowingvalueenablingtheI2Cprotocolstacktoaddresstheduplicatedaddress
space between 0 and 127 in 10-bit mode.
V-17.2. DXE Code definitions V-211UEFI Platform Initialization Specification, Release 1.8
#define I2C_ADDRESSING_10_BIT 0x80000000
The I2C protocol stack uses the EFI_I2C_REQUEST_PACKET structure to describe I2C transactions on the I2C bus.
TheEFI_I2C_OPERATION describes a portion of the I2C transaction. The transaction starts with a start bit followed
by the first operation in the operation array. Subsequent operations are separated with repeated start bits and the last
operation is followed by a stop bit which concludes the transaction.
UINTN OperationCount;
EFI_I2C_OPERATION Operation[];
} EFI_I2C_REQUEST_PACKET;
OperationCount
Number of elements in the operation array.
Operation
Description of the I2C operation
TheEFI_I2C_REQUEST_PACKET describes a single I2C transaction. The transaction starts with a start bit followed
operationisfollowedbyastopbitwhichconcludesthetransaction. Eachoperationisdescribedbyoneoftheelements
in theOperation array.
UINT32 LengthInBytes;
} EFI_I2C_OPERATION;
Flags
Flag bits qualify the I2C operation.
Flag Bits:
///
/// Define the I2C flags
///
/// I2C read operation when set
#define I2C_FLAG_READ 0x00000001
///
/// Define the flags forSMBus operation
///
/// The following flags are also present inonly the first I2C operation
/// andare ignored when present inother operations. These flags
/// describe a particular SMB transaction asshown inthe following table.
///
/// SMBus operation
#define I2C_FLAG_SMBUS_OPERATION 0x00010000
V-17.2. DXE Code definitions V-212UEFI Platform Initialization Specification, Release 1.8
/// SMBus block operation
/// The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update
/// the LengthInBytes field of the operation inthe request packet with
/// the actual number of bytes read orwritten. These values are only
/// valid when the entire I2C transaction issuccessful.
/// This flag also changes the LengthInBytes meaning to be: A maximum
/// of LengthInBytes isto be read from the device. The first byte
/// read contains the number of bytes remaining to be read, plus an
/// optional PEC value.
#define I2C_FLAG_SMBUS_BLOCK 0x00020000
/// SMBus process call operation
#define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000
/// SMBus use packet error code (PEC)
/// Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit
/// to indicate that the PEC value was checked by the hardware and is
/// notappended to the returned read data.
///
#define I2C_FLAG_SMBUS_PEC 0x00080000
//----------------------------------------------------------------------
///
/// QuickRead: OperationCount=1,
/// LengthInBytes=0, Flags=I2C_FLAG_READ
/// QuickWrite: OperationCount=1,
/// LengthInBytes=0, Flags=0
///
///
/// ReceiveByte: OperationCount=1,
/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
/// | I2C_FLAG_READ
/// ReceiveByte+PEC: OperationCount=1,
/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
/// | I2C_FLAG_SMBUS_PEC
///
///
/// SendByte: OperationCount=1,
/// SendByte+PEC: OperationCount=1,
///
///
/// ReadDataByte: OperationCount=2,
/// LengthInBytes=1, Flags=I2C_FLAG_READ
/// ReadDataByte+PEC: OperationCount=2,
V-17.2. DXE Code definitions V-213UEFI Platform Initialization Specification, Release 1.8
/// LengthInBytes=2, Flags=I2C_FLAG_READ
///
///
/// WriteDataByte: OperationCount=1,
/// WriteDataByte+PEC: OperationCount=1,
/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
///
///
/// ReadDataWord: OperationCount=2,
/// ReadDataWord+PEC: OperationCount=2,
/// LengthInBytes=3, Flags=I2C_FLAG_READ
///
///
/// WriteDataWord: OperationCount=1,
/// WriteDataWord+PEC: OperationCount=1,

///
///
///
///
///
///
/// LengthInBytes=4, Flags=I2C_FLAG_SMBUS_OPERATION
///
///
/// ReadBlock: OperationCount=2,
/// | I2C_FLAG_SMBUS_BLOCK
/// LengthInBytes=33, Flags=I2C_FLAG_READ
/// ReadBlock+PEC: OperationCount=2,
/// LengthInBytes=34, Flags=I2C_FLAG_READ
///
///
/// WriteBlock: OperationCount=1,
/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
/// WriteBlock+PEC: OperationCount=1,
/// LengthInBytes=N+3, Flags=I2C_FLAG_SMBUS_OPERATION
///
///
/// ProcessCall: OperationCount=2,
/// | I2C_FLAG_SMBUS_PROCESS_CALL
/// ProcessCall+PEC: OperationCount=2,
V-17.2. DXE Code definitions V-214UEFI Platform Initialization Specification, Release 1.8
///
///
/// BlkProcessCall: OperationCount=2,
/// BlkProcessCall+PEC: OperationCount=2,
///
LengthInBytes
Number of bytes to send to or receive from the I2C device. A ping (address only byte/bytes) is indicated by
setting the LengthInBytes to zero.
Buffer
Pointer to a buffer containing the data to send or to receive from the I2C device. The Buffermust be at least
LengthInBytes in size.
TheEFI_I2C_OPERATION describes a subset of an I2C transaction in which the I2C controller is either sending or
receiving bytes from the bus. Some transactions will consist of a single operation while others will be two or more.
Note: Some I2C controllers do not support read or write ping (address only) operation and will return
EFI_UNSUPPORTED status when these operations are requested.
Note:I2C controllers which do not support complex transactions requiring multiple repeated start bits return
EFI_UNSUPPORTED without processing any of the transaction.
UINT32 StructureSizeInBytes;
UINT32 MaximumReceiveBytes;
UINT32 MaximumTransmitBytes;
UINT32 MaximumTotalBytes;
} EFI_I2C_CONTROLLER_CAPABILITIES;
StructureSizeInBytes
Length of this data structure in bytes
MaximumReceiveBytes;
The maximum number of bytes the I2C host controller is able to receive from the I2C bus.
V-17.2. DXE Code definitions V-215UEFI Platform Initialization Specification, Release 1.8
MaximumTransmitBytes
The maximum number of bytes the I2C host controller is able to send on the I2C bus.
MaximumTotalBytes
The maximum number of bytes in the I2C bus transaction.
TheEFI_I2C_CONTROLLER_CAPABILITIES specifies the capabilities of the I2C host controller. The Structure-
SizeInBytes enables variations of this structure to be identified if there is need to extend this structure in the future.
V-17.2.3 EFI_I2C_MASTER_PROTOCOL.SetBusFrequency()
Summary
Set the frequency for the I2C clock line.
Prototype
typedef
(EFIAPI *EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY) (
IN CONST EFI_I2C_MASTER_PROTOCOL *This,
IN OUT UINTN *BusClockHertz
);
This
Pointer to an EFI_I2C_MASTER_PROTOCOL structure.
BusClockHertz
Pointer to the requested I2C bus clock frequency in Hertz. Upon return this value contains the actual frequency
in use by the I2C controller.
This routine must be called at or below TPL_NOTIFY .
The software and controller do a best case effort of using the specified frequency for the I2C bus. If the frequency
does not match exactly then the I2C master protocol selects the next lower frequency to avoid exceeding the operating
conditions for any of the I2C devices on the bus. For example if 400 KHz was specified and the controller’s divide
network only supports 402 KHz or 398 KHz then the I2C master protocol selects 398 KHz. If there are not lower
frequencies available, then return EFI_UNSUPPORTED .
EFI_SUCCESS The bus frequency was set successfully.
EFI_ALREADY_STARTED The controller is busy with another transaction.
EFI_UNSUPPORTED The controller does not support this frequency.
V-17.2. DXE Code definitions V-216UEFI Platform Initialization Specification, Release 1.8
V-17.2.4 EFI_I2C_MASTER_PROTOCOL.Reset()
Summary
Reset the I2C controller and configure it for use.
Prototype
typedef
(EFIAPI *EFI_I2C_MASTER_PROTOCOL_RESET) (
IN CONST EFI_I2C_MASTER_PROTOCOL *This
);
This
The I2C controller is reset. The caller must call SetBusFrequency() after calling Reset().
EFI_SUCCESS The rest completed successfully.
EFI_DEVICE_ERROR The reset operation failed.
V-17.2.5 EFI_I2C_MASTER_PROTOCOL.StartRequest()
Summary
Start an I2C transaction on the host controller.
Prototype
typedef
(EFIAPI *EFI_I2C_MASTER_PROTOCOL_START_REQUEST) (
IN UINTN SlaveAddress,
IN EFI_I2C_REQUEST_PACKET *RequestPacket,
IN EFI_EVENT Event OPTIONAL,
OUT EFI_STATUS *I2cStatus OPTIONAL
);
This
Address of the device on the I2C BUS. Set the I2C_ADDRESSING_10_BIT when using 10-bit addresses, clear
this bit for 7-bit addressing. Bits 0-6 are used for 7-bit I2C slave addresses and bits 0-9 are used for 10-bit I2C
slave addresses.
V-17.2. DXE Code definitions V-217UEFI Platform Initialization Specification, Release 1.8
RequestPacket
Pointer to an EFI_I2C_REQUEST_PACKET structure describing the I2C transaction.
Event
Event to signal for asynchronous transactions, NULL for synchronous transactions
I2cStatus
Optional buffer to receive the I2C transaction completion status
Thisroutinemustbecalledatorbelow TPL_NOTIFY .Forsynchronousrequeststhisroutinemustbecalledatorbelow
This function initiates an I2C transaction on the controller. To enable proper error handling by the I2C protocol stack,
the I2C master protocol does not support queuing but instead only manages one I2C transaction at a time. This API
requires that the I2C bus is in the correct configuration for the I2C transaction.
The transaction is performed by sending a start-bit and selecting the I2C device with the specified I2C slave address
and then performing the specified I2C operations. When multiple operations are requested they are separated with a
repeated start bit and the slave address. The transaction is terminated with a stop bit.
When Event is NULL, StartRequest operates synchronously and returns the I2C completion status as its return value.
WhenEventisnotNULL, StartRequest synchronouslyreturns EFI_SUCCESS indicatingthattheI2Ctransactionwas
startedasynchronously. Thetransactionstatusvalueisreturnedinthebufferpointedtoby I2cStatus uponthecomple-
tion of the I2C transaction when I2cStatus is not NULL. After the transaction status is returned the Event is signaled.
Note:The typical consumer of this API is the I2C host protocol. Extreme care must be taken by other consumers of
this API to prevent confusing the third party I2C drivers due to a state change at the I2C device which the third party
I2C drivers did not initiate. I2C platform specific code may use this API within these guidelines.
EFI_SUCCESS The asynchronous transaction was successfully started when Event
is not NULL
EFI_SUCCESS The transaction completed successfully when Event is NULL
EFI_ALREADY_STARTED The controller is busy with another transaction
EFI_BAD_BUFFER_SIZE The RequestPacket LengthInBytes value is too large
EFI_DEVICE_ERROR There was an I2C error NACK during the transaction
EFI_INVALID_PARAMETER RequestPacket is NULL
EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter
EFI_NO_RESPONSE The I2C device is not responding to the slave address
EFI_DEVICE_ERROR will be returned if the controller can-
not distinguish when the NACK occurred
EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction
EFI_UNSUPPORTED The controller does not support the requested transaction
V-17.2. DXE Code definitions V-218UEFI Platform Initialization Specification, Release 1.8
V-17.2.6 I2C Host Protocol
V-17.2.7 EFI_I2C_HOST_PROTOCOL
Summary
This protocol provides callers with the ability to do I/O transactions to all of the devices on the I2C bus.
GUID

is not NULL
Summary
GUID
#define EFI_I2C_HOST_PROTOCOL_GUID \
{ 0xa5aab9e3, 0xc727, 0x48cd, { 0x8b, 0xbf, 0x42, 0x72, \
0x33, 0x85, 0x49, 0x48 }}
typedef struct _EFI_I2C_HOST_PROTOCOL {
EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST QueueRequest;
} EFI_I2C_HOST_PROTOCOL;
QueueRequest
Queue an transaction for execution on the I2C bus
The I2C bus driver uses the services of the EFI_I2C_HOST_PROTOCOL to produce an instance of the
EFI_I2C_IO_PROTOCOL for each I2C device on an I2C bus.
TheEFI_I2C_HOST_PROTOCOL exposes an asynchronous interface to callers to perform transactions to any de-
vice on the I2C bus. Internally, the I2C host protocol manages the flow of the I2C transactions to the host controller,
keeping them in FIFO order. Prior to each transaction, the I2C host protocol ensures that the switches and multi-
plexers are properly configured. The I2C host protocol then starts the transaction on the host controller using the
EFI_I2C_MASTER_PROTOCOL .
V-17.2.8 EFI_I2C_HOST_PROTOCOL.QueueRequest()
Summary
Queue an I2C transaction for execution on the I2C controller.
Prototype
typedef
(EFIAPI \*EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST) (
IN CONST EFI_I2C_HOST_PROTOCOL *This,
IN UINTN I2cBusConfiguration,
V-17.2. DXE Code definitions V-219UEFI Platform Initialization Specification, Release 1.8
);
This
Pointer to an EFI_I2C_HOST_PROTOCOL structure.
I2cBusConfiguration
I2C bus configuration to access the I2C device
Address of the device on the I2C bus. Set the I2C_ADDRESSING_10_BIT when using 10-bit addresses, clear
Event
Pointer to an EFI_I2C_REQUEST_PACKET structure describing the I2C transaction
I2cStatus
TPL_CALLBACK .TheI2ChostprotocolusestheconceptofI2CbusconfigurationstodescribetheI2Cbus. AnI2Cbus
configurationisdefinedasauniquesettingofthemultiplexersandswitchesintheI2Cbuswhichenableaccesstoone
ormoreI2Cdevices. Whenusingaswitchtodivideabus,duetobusfrequencydifferences,theI2Cbusconfiguration
management protocol defines an I2C bus configuration for the I2C devices on each side of the switch. When using
a multiplexer, the I2C bus configuration management defines an I2C bus configuration for each of the selector values
requiredtocontrolthemultiplexer. SeeFigure1inthe |I2C|-busspecificationandusermanual foracomplexI2Cbus
TheI2ChostprotocolprocessesalltransactionsinFIFOorder. Priortoperformingthetransaction,theI2Chostprotocol
callsEnableI2cBusConfiguration to reconfigure the switches and multiplexers in the I2C bus enabling access to the
specified I2C device. The EnableI2cBusConfiguration also selects the I2C bus frequency for the I2C device. After the
I2C bus is configured, the I2C host protocol calls the I2C master protocol to start the I2C transaction. When Event is
NULL,QueueRequest() operates synchronously and returns the I2C completion status as its return value.
When Event is not NULL, QueueRequest() synchronously returns EFI_SUCCESS indicating that the asynchronously
I2C transaction was queued. The values above are returned in the buffer pointed to by I2cStatus upon the completion
of the I2C transaction when I2cStatus is not NULL.
EFI_SUCCESS The asynchronous transaction was successfully queued when Event
is not NULL
V-17.2. DXE Code definitions V-220UEFI Platform Initialization Specification, Release 1.8
Table 17.2 – continued from previous page
EFI_NO_MAPPING Invalid I2cBusConfiguration value
V-17.2.9 I2C I/O Protocol
V-17.2.10 EFI_I2C_IO_PROTOCOL
Summary
TheEFII2CI/OprotocolenablestheusertomanipulateasingleI2CdeviceindependentofthehostcontrollerandI2C
design.
GUID
#define EFI_I2C_IO_PROTOCOL_GUID \
{ 0xb60a3e6b, 0x18c4, 0x46e5, { 0xa2, 0x9a, 0xc9, 0xa1, \
0x06, 0x65, 0xa2, 0x8e }}
typedef struct \_EFI_I2C_IO_PROTOCOL {
EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST QueueRequest;
CONST EFI_GUID *DeviceGuid;
UINT32 DeviceIndex;
UINT32 HardwareRevision;
} EFI_I2C_IO_PROTOCOL;
Queue an I2C transaction for execution on the I2C device.
DeviceGuid
UniquevalueassignedbythesiliconmanufactureorthethirdpartyI2CdriverwriterfortheI2Cpart. Thisvalue
logicallycombinesboththemanufacturenameandtheI2CpartnumberintoasinglevaluespecifiedasaGUID.
Unique ID of the I2C part within the system
HardwareRevision
Hardware revision - ACPI _HRV value. See the Advanced Configuration and Power Interface Specification,
Revision 5.0 for the field format and the Plug and play support for |I2C| web-page for restriction on values.
•The I2C IO protocol enables access to a specific device on the I2C bus.
V-17.2. DXE Code definitions V-221UEFI Platform Initialization Specification, Release 1.8
•Each I2C device is identified uniquely in the system by the tuple DeviceGuid :DeviceIndex . TheDeviceGuid
represents the manufacture and part number and is provided by the silicon vendor or the third party I2C device
driver writer. The DeviceIndex identifies the part within the system by using a unique number and is created
by the board designer or the writer of the EFI_I2C_ENUMERATE_PROTOCOL . I2C slave addressing is ab-
stracted to validate addresses and limit operation to the specified I2C device. The third party providing the
I2C device support provides an ordered list of slave addresses for the I2C device required to implement the
EFI_I2C_ENUMERATE_PROTOCOL . The order of the list must be preserved.
V-17.2.11 EFI_I2C_IO_PROTOCOL.QueueRequest()
Summary
Prototype
typedef
(EFIAPI *EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST) (
IN CONST EFI_I2C_IO_PROTOCOL *This,
IN UINTN SlaveAddressIndex,
);
This
Pointer to an EFI_I2C_IO_PROTOCOL structure.
SlaveAddressIndex
IndexvalueintoanarrayofslaveaddressesfortheI2Cdevice. Thevaluesinthearrayarespecifiedbytheboard
designer, with the third party I2C device driver writer providing the slave address order.
For devices that have a single slave address, this value must be zero. If the I2C device uses more than one slave
addressthenthethirdparty(upperlevel)I2Cdriverwriterneedstospecifytheorderofentriesintheslaveaddress
array.
Event
I2cStatus
This routine queues an I2C transaction to the I2C controller for execution on the I2C bus. When Eventis NULL,
QueueRequest() operates synchronously and returns the I2C completion status as its return value.
WhenEventisnotNULL, QueueRequest() synchronouslyreturns EFI_SUCCESS indicatingthattheasynchronousI2C
transactionwasqueued. ThevaluesabovearereturnedinthebufferpointedtobyI2cStatusuponthecompletionofthe
I2C transaction when I2cStatus is not NULL.
V-17.2. DXE Code definitions V-222UEFI Platform Initialization Specification, Release 1.8
is not NULL

I2cStatus
is not NULL
EFI_NO_MAPPING TheEFI_I2C_HOST_PROTOCOLcouldnotsetthebusconfigura-
tion required to access this I2C device
EFI_NO_RESPONSE The I2C device is not responding to the slave address selected by
SlaveAddressIndex EFI_DEVICE_ERROR will be returned if the
controller cannot distinguish when the NACK occurred
V-17.2.12 I2C Bus Configuration Management Protocol
V-17.2.13 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
Summary
TheEFII2CbusconfigurationmanagementprotocolprovidesplatformspecificservicesthatallowtheI2Chostprotocol
toreconfiguretheswitchesandmultiplexersandsettheclockfrequencyfortheI2Cbus. Thisprotocolalsoenablesthe
I2C host protocol to reset an I2C device which may be locking up the I2C bus by holding the clock or data line low.
GUID
#define EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_GUID \
{ 0x55b71fb5, 0x17c6, 0x410e, { 0xb5, 0xbd, 0x5f, 0xa2, \
0xe3, 0xd4, 0x46, 0x6b }}
typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL {
EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION ␣
˓→EnableI2cBusConfiguration;
} EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL;
EnableI2cBusConfiguration
Enable an I2C bus configuration for use.
TheI2CprotocolstackusestheconceptofanI2Cbusconfigurationasawaytodescribeaparticularstateoftheswitches
A simple I2C bus does not have any multiplexers or switches is described to the I2C protocol stack with a single I2C
bus configuration which specifies the I2C bus frequency. An I2C bus with switches and multiplexers use an I2C bus
configuration to describe each of the unique settings for the switches and multiplexers and the I2C bus frequency.
However the I2C bus configuration management protocol only needs to define the I2C bus configurations that the
software uses, which may be a subset of the total.
V-17.2. DXE Code definitions V-223UEFI Platform Initialization Specification, Release 1.8
The I2C bus configuration description includes a list of I2C devices which may be accessed when this I2C bus config-
urationisenabled. I2CdevicesbeforeaswitchormultiplexermustbeincludedinoneI2CbusconfigurationwhileI2C
devices after a switch or multiplexer are on another I2C bus configuration.
TheI2Cbusconfigurationmanagementprotocolisanoptionalprotocol. WhentheI2Cbusconfigurationprotocolisnot
definedtheI2ChostprotocoldoesnotstartandtheI2CmasterprotocolmaybeusedforotherpurposessuchasSMBus
traffic. When the I2C bus configuration protocol is available, the I2C host protocol uses the I2C bus configuration
protocol to call into the platform specific code to set the switches and multiplexers and set the maximum I2C bus
frequency.
The platform designers determine the maximum I2C bus frequency by selecting a frequency which supports all of the
I2C devices on the I2C bus for the setting of switches and multiplexers. The platform designers must validate this
against the I2C device data sheets and any limits of the I2C controller or bus length.
DuringI2Cdeviceenumeration,theI2CbusdriverretrievestheI2CbusconfigurationthatmustbeusedtoperformI2C
transactions to each I2C device. This I2C bus configuration value is passed into the I2C host protocol to identify the
I2C bus configuration required to access a specific I2C device. The I2C host protocol calls EnableBusConfiguration()
to set the switches and multiplexers in the I2C bus and the I2C clock frequency. The I2C host protocol may optimize
callstoEnableBusConfiguration() byonlymakingthecallwhentheI2CbusconfigurationvaluechangesbetweenI2C
requests.
WhenI2CtransactionsarerequiredonthesameI2Cbustochangethestateofmultiplexersorswitches,theI2Cmaster
protocol must be used to perform the necessary I2C transactions.
It is up to the platform specific code to choose the proper I2C bus configuration when ExitBootServices() is called.
SomeoperatingsystemsarenotabletomanagetheI2CbusconfigurationsandmustusetheI2Cbusconfigurationthat
is established by the platform firmware before ExitBootServices() returns.
V-17.2.14 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL.EnableI2cBusConfiguration()
Summary
Enable access to an I2C bus configuration.
Prototype
typedef
(EFIAPI
*EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION) (
IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This,
IN EFI_STATUS *I2cStatus OPTIONAL
);
This
Pointer to an EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL structure.
Index of an I2C bus configuration. All values in the range of zero to N-1 are valid where N is the total number
of I2C bus configurations for an I2C bus.
Event
Event to signal when the transaction is complete
V-17.2. DXE Code definitions V-224UEFI Platform Initialization Specification, Release 1.8
I2cStatus
Buffer to receive the transaction status.
ReconfiguretheswitchesandmultiplexersintheI2CbustoenableaccesstoaspecificI2Cbusconfiguration. Alsoselect
themaximumclockfrequencyforthisI2Cbusconfiguration. ThisroutineusestheI2CMasterprotocoltoperformI2C
transactionsonthelocalbus. ThiseliminatesanyrecursionintheI2Cstackforconfigurationtransactionsonthesame
I2C bus. This works because the local I2C bus is idle while the I2C bus configuration is being enabled.
If I2C transactions must be performed on other I2C busses, then the EFI_I2C_HOST_PROTOCOL , the
EFI_I2C_IO_PROTCOL , or a third party I2C driver interface for a specific device must be used. This requirement is
becausetheI2ChostprotocolcontrolstheflowofrequeststotheI2Ccontroller. Usethe EFI_I2C_HOST_PROTOCOL
when the I2C device is not enumerated by the EFI_I2C_ENUMERATE_PROTOCOL . Use a protocol produced by a
thirdpartydriverwhenitisavailableorthe EFI_I2C_IO_PROTOCOL whenthethirdpartydriverisnotavailablebut
the device is enumerated with the EFI_I2C_ENUMERATE_PROTOCOL .
When Event is NULL, EnableI2cBusConfiguration operates synchronously and returns the I2C completion status as
its return value. The values returned from EnableI2cBusConfiguration are:
EFI_SUCCESS Theasynchronousbusconfigurationrequestwassuccessfullystarted
when Event is not NULL
EFI_SUCCESS ThebusconfigurationrequestcompletedsuccessfullywhenEventis
NULL
EFI_DEVICE_ERROR The bus configuration failed
V-17.2.15 I2C Enumerate Protocol
V-17.2.16 EFI_I2C_ENUMERATE_PROTOCOL
Summary
Support the enumeration of the I2C devices.
GUID
#define EFI_I2C_ENUMERATE_PROTOCOL_GUID \
{ 0xda8cd7c4, 0x1c00, 0x49e2, { 0x80, 0x3e, 0x52, 0x14, \
0xe7, 0x01, 0x89, 0x4c }}
typedef struct \_EFI_I2C_ENUMERATE_PROTOCOL {
EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE Enumerate;
EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY GetBusFrequency;
} EFI_I2C_ENUMERATE_PROTOCOL;
Enumerate
Traverse the set of I2C devices on an I2C bus. This routine returns the next I2C device on an I2C bus.
V-17.2. DXE Code definitions V-225UEFI Platform Initialization Specification, Release 1.8
GetBusFrequency
Get the requested I2C bus frequency for a specified bus configuration.
The I2C bus driver uses this protocol to enumerate the devices on the I2C bus.
UINT32 I2cBusConfiguration;
UINT32 SlaveAddressCount;
CONST UINT32 *SlaveAddressArray;
} EFI_I2C_DEVICE;
I2C bus configuration for the I2C device
SlaveAddressCount
Number of slave addresses for the I2C device.
SlaveAddressArray
Pointer to the array of slave addresses for the I2C device.
TheEFI_I2C_ENUMERATE_PROTOCOL usestheEFI_I2C_DEVICE todescribetheplatformspecificdetailsassoci-
atedwithanI2Cdevice. ThisdescriptionispassedtotheI2Cbusdriverduringenumerationwhereitismadeavailable
to the third party I2C device driver via the EFI_I2C_IO_PROTOCOL .
V-17.2.17 EFI_I2C_ENUMERATE_PROTOCOL.Enumerate()
Summary
Enumerate the I2C devices
Prototype
typedef

Summary
Prototype
typedef
(EFIAPI \*EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE) (
IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This,
IN OUT CONST EFI_I2C_DEVICE **Device
);
V-17.2. DXE Code definitions V-226UEFI Platform Initialization Specification, Release 1.8
This
Pointer to an EFI_I2C_ENUMERATE_PROTOCOL structure.
Device
Pointer to a buffer containing an EFI_I2C_DEVICE structure. Enumeration is started by setting the initial
EFI_I2C_DEVICE structure pointer to NULL. The buffer receives an EFI_I2C_DEVICE structure pointer to
the next I2C device.
This function enables the caller to traverse the set of I2C devices on an I2C bus.
EFI_SUCCESS The platform data for the next device on the I2C bus was returned
EFI_INVALID_PARAMETER Device is NULL
EFI_NO_MAPPING Device does not point to a valid EFI_I2C_DEVICE structure re-
turned in a previous call Enumerate
V-17.2.18 EFI_I2C_ENUMERATE_PROTOCOL.GetBusFrequency()
Summary
Prototype
typedef
(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY) (
OUT UINTN *BusClockHertz
);
This
Pointer to a buffer to receive the I2C bus clock frequency in Hertz
ThisfunctionreturnstherequestedI2Cbusclockfrequencyforthe I2cBusConfiguration . Thisroutineisprovidedfor
diagnostic purposes and is meant to be called after calling Enumerate to get the I2cBusConfiguration value.
EFI_SUCCESS The I2C bus frequency was returned successfully.
EFI_INVALID_PARAMETER BusClockHertz wasNULL
EFI_NO_MAPPING InvalidI2cBusConfiguration value
V-17.2. DXE Code definitions V-227UEFI Platform Initialization Specification, Release 1.8
V-17.3 PEI Code definitions
For the Pre-EFI Initialization environment a subset of the I2C stack is defined to support basic hardware initialization
in the PEI phase. The EFI_PEI_I2C_MASTER PPI is defined to standardize access to the I2C controller.
V-17.3.1 I2C Master PPI
V-17.3.2 EFI_PEI_I2C_MASTER
Summary
ThisPPImanipulatestheI2ChostcontrollertoperformtransactionsasamasterontheI2Cbususingthecurrentstate
of any switches or multiplexers in the I2C bus.
GUID
#define EFI_PEI_I2C_MASTER_PPI_GUID \
{ 0xb3bfab9b, 0x9f9c, 0x4e8b, { 0xad, 0x37, 0x7f, 0x8c, \
0x51, 0xfc, 0x62, 0x80 }}
PEIM-to-PEIM Interface Structure
typedef struct _EFI_PEI_I2C_MASTER_PPI {
EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY SetBusFrequency;
EFI_PEI_I2C_MASTER_PPI_RESET Reset;
EFI_PEI_I2C_MASTER_PPI_START_REQUEST StartRequest;
CONST EFI_PEI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;
} EFI_PEI_I2C_MASTER_PPI;
Set the clock frequency in Hertz for the I2C bus.
Reset
Identifier which uniquely identifies thisI2C controller in the system.
TheEFI_PEI_I2C_MASTER PPI enables the platform code to perform transactions on the I2C bus.
V-17.3. PEI Code definitions V-228UEFI Platform Initialization Specification, Release 1.8
V-17.3.3 EFI_PEI_I2C_MASTER_PPI.SetBusFrequency()
Summary
Prototype
typedef
(EFIAPI \*EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY) (
IN EFI_PEI_I2C_MASTER *This,
IN UINTN *BusClockHertz
);
This
Pointer to an EFI_PEI_I2C_MASTER_PPI structure.
network only supports 402 KHz or 398 KHz then the controller would be set to 398 KHz. If there are no lower
EFI_INVALID_PARAMETER BusClockHertz is NULL
V-17.3.4 EFI_PEI_I2C_MASTER_PPI.Reset()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_I2C_MASTER_PPI_RESET) (
IN CONST EFI_PEI_I2C_MASTER *This
);
This
V-17.3. PEI Code definitions V-229UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The reset completed successfully.
V-17.3.5 EFI_PEI_I2C_MASTER_PPI.StartRequest()
Summary
Prototype
typedef
(EFIAPI \*EFI_PEI_I2C_MASTER_PPI_START_REQUEST) (
IN CONST EFI_PEI_I2C_MASTER *This,
IN EFI_I2C_REQUEST_PACKET *RequestPacket
);
This
This function initiates an I2C transaction on the controller.
repeatedstartbitandtheslaveaddress. Thetransactionisterminatedwithastopbit. Whenthetransactioncompletes,
the status value is returned.
V-17.3. PEI Code definitions V-230UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The transaction completed successfully
V-17.3.6 I2C Host PPI
V-17.3.7 EFI_PEI_I2C_HOST
Summary
This PPI provides callers with the ability to do I/O transactions to all of the devices on the I2C bus.
GUID
#define EFI_PEI_I2C_HOST_GUID \
{ 0x3a12e52d, 0x3bd2, 0x482c, 0xa6, 0x80, 0x0f, 0xeb, \
0x61, 0x9a, 0xeb, 0xef }
typedef struct \_EFI_I2C_HOST_PPI {
EFI_I2C_HOST_START_REQUEST StartRequest;
UINTN ControllerNumber;
};
Queue a transaction for execution on the I2C bus
Theaddressofan EFI_I2C_CONTROLLER_CAPABILITIES datastructurecontainingthecapabilitiesoftheI2C
host controller.
ControllerNumber
Unique number identifying the I2C controller in the system
Please use EFI_PEI_I2C_IO asEFI_PEI_I2C_HOST is only intended to be used by the I2C bus driver. The
EFI_PEI_I2C_HOST requiresthetuple ControllerNumber:BusConfiguration:SlaveAddress whichisplatformspecific
datatoidentifytheI2Cdevice. EFI_PEI_I2C_IO eliminatestheplatformspecificdetails. Theupperlayerdriverlocates
the correct EFI_PEI_I2C_HOST interface (I2cHost) by comparing the following field:
•I2cHost->ControllerNumber with the system unique value for the I2C Controller Number
Priortoeachtransaction,theI2Chostdriverensuresthattheswitchesandmultiplexersareproperlyconfigured. TheI2C
hostdriverthenstartsthetransactionontheI2CcontrollercallingtheI2Cportdriverinterface( EFI_PEI_I2C_MASTER
).
V-17.3. PEI Code definitions V-231UEFI Platform Initialization Specification, Release 1.8
The I2C platform driver installs the following GUID after installing EFI_PEI_I2C_ENUMERATE
and*EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT* PPIs for the necessary I2C controllers. The
followingGUIDresolvesthedependencyexpressionsfortheI2Cportandhostdriversenablingthemtoloadandstart
their configuration.
Lack ofEFI_PEI_I2C_BUS_CONFIGURATION prevents the I2C host driver from loading, reserving the I2C port

).
driver for SMBus transactions.
GUID
#define EFI_PEI_I2C_BUS_CONFIGURED_GUID \
{ 0x9eade134, 0x6bb1, 0x421d, 0xac, 0xaf, 0x59, 0x0a, \
0x5d, 0x2e, 0xa6, 0x3a }
V-17.3.8 EFI_PEI_I2C_HOST.StartRequest()
Summary
Start a transaction on the I2C controller.
Prototype
typedef
(EFIAPI \*EFI_PEI_I2C_HOST_START_REQUEST) (
IN EFI_PEI_I2C_HOST *This,
);
This
Address of an EFI_PEI_I2C_HOST structure.
Addressofthedeviceonthe|I2C|bus. Orinthevalue I2C_ADDRESSING_10_BIT whenusing10-bitaddresses.
Address of an EFI_I2C_REQUEST_PACKET structure describing the I2C transaction
Start an I2C transaction on the I2C controller.
N.B. The typical consumers of this API are the I2C bus driver and on rare occasions I2C test applications. Extreme
caremustbetakenbyotherconsumersofthisAPItopreventconfusingthethirdpartyI2Cdriversduetoastatechange
at the I2C device which the third party I2C drivers did not initiate. I2C platform drivers may use this API within these
guidelines.
ThislayerusestheconceptofI2CbusconfigurationstodescribetheI2Cbus. AnI2Cbusconfigurationisdefinedasa
unique setting of the multiplexers and switches in the I2C bus which enable access to one or more I2C devices. When
using a switch to divide a bus, due to speed differences, the I2C platform layer would define an I2C bus configuration
V-17.3. PEI Code definitions V-232UEFI Platform Initialization Specification, Release 1.8
fortheI2Cdevicesoneachsideoftheswitch. Whenusingamultiplexer,theI2CplatformlayerdefinesanI2Cbuscon-
figurationforeachoftheselectorvaluesrequiredtocontrolthemultiplexer. SeeFigure1inthe |I2C|-busspecification
and user manual for a complex I2C bus configuration.
The I2C host driver calls the I2C platform driver to reconfigure the switches and multiplexers in the I2C bus enabling
access to the specified I2C device. The I2C platform driver also selects the maximum bus speed for the device. After
the I2C bus is configured, the I2C host driver calls the I2C port driver to initialize the I2C controller and start the I2C
transaction.
In event of timeout, the I2C host driver calls the I2C platform driver in an attempt to reset the host controller and the
I2C device.
The values returned from StartRequest are:
EFI_BAD_BUFFER_SIZE The LengthInBytes value is too large
EFI_DEVICE_ERROR There was an I2C error NACK during the transaction One possible
cause is that the slave device is not present
EFI_NOT_FOUND I2C slave address exceeds maximum address
EFI_NO_MEDIA State was lost because more than one device was reset
EFI_DEVICE_ERROR may also be returned if the controller
cannot distinguish when the NACK occurred
EFI_TIMEOUT Thetransactiondidnotcompletewithinthespecifiedtimeoutperiod
V-17.3.9 I2C I/O PPI
V-17.3.10 EFI_PEI_I2C_IO
Summary
TheEFII2CI/OPPIenablestheusertomanipulateasingleI2CdeviceindependentofthehostcontrollerandI2Cbus
design.
GUID
#define EFI_PEI_I2C_IO_GUID \
{ 0x42179ed0, 0x2fa2, 0x47c0, 0x85, 0x7e, 0x8b, 0xc0, \
0x18, 0x81, 0xea, 0x97 }
EFI_PEI_I2C_IO_GET_DEVICE_INFO GetDeviceInfo;
EFI_PEI_I2C_IO_GET_DEVICE_INFO_ID_LIST GetDeviceInfoIdList;
EFI_PEI_I2C_IO_START_REQUEST StartRequest;
EFI_I2C_DEVICE *I2cDevice;
} EFI_PEI_I2C_IO;
V-17.3. PEI Code definitions V-233UEFI Platform Initialization Specification, Release 1.8
GetDeviceInfo
Get a blob of data identified by a GUID.
GetDeviceInfoIdList
Get a list of the GUIDs associated with this I2C device.
Start a transaction on the I2C device.
I2cDevice
A pointer to the EFI_I2C_DEVICE structure contained within the I2C platform driver.
The I2C I/O PPI enables access to a specific device on the I2C bus.
EachI2Cdeviceisidentifieduniquelyinthesystembythetuple DeviceGuid:DeviceIndex . TheDeviceGuid combines
themanufactureandpartnumberandisprovidedbythesiliconvendororthethirdpartyI2Cdevicedriverwriter. The
DeviceIndex identifiesthepartwithinthesystembyusingauniquenumberandiscreatedbytheboarddesignerorthe
I2C platform driver writer. The upper layer I2C driver writer provides the following to the platform vendor:
•Vendor specific GUID for the I2C part that is used to connect the upper layer driver to the device.
•Slave address array guidance when the I2C device uses more than one slave address. This is used to access the
blocks of hardware within the I2C device.
The upper layer driver locates the correct EFI_PEI_I2C_IO interface (I2cIo) by comparing the following fields:
•I2cIo->Device.DeviceGuid with the vendor supplied GUID
•I2cIo->DeviceIndex with the system wide unique number assigned to the specific I2C part.
I2CslaveaddressingisabstractedtovalidateaddressesandlimitoperationtothespecifiedI2Cdevice. Thethirdparty
providingtheI2CdevicesupportprovidesanorderedlistofslaveaddressesfortheI2Cdevicetotheteambuildingthe
platform layer. The platform team must preserve the order of the supplied list. SlaveAddressCount is the number of
entriesinthislistorarraywithintheplatformlayer. Thethirdpartydevicesupportreferencesaslaveaddressusingan
index into the list or array in the range of zero to SlaveAddressCount - 1.
V-17.3.11 EFI_I2C_IO_PROTOCOL.GetDeviceInfo()
Summary
Get a data blob associated with the I2C device.
Prototype
typedef
(EFIAPI \*EFI_I2C_IO_GET_DEVICE_INFO) (
IN EFI_PEI_I2C_IO *This,
IN EFI_GUID *DataGuid,
IN OUT UINT32 *LengthInBytes,
);
V-17.3. PEI Code definitions V-234UEFI Platform Initialization Specification, Release 1.8
This
Address of an EFI_PEI_I2C_IO structure.
DataGuid
Address of the GUID associated with the data
Address of a value containing the length of the buffer in bytes on input and receiving the length of the data on
output. If the input length was too small, the output length specifies the data length.
Buffer
Buffer address to receive the data
This routine locates the specified data blob associated with the I2C device.
The values returned from GetDeviceInfo are:
EFI_SUCCESS The data was returned successfully
EFI_BUFFER_TOO_SMALL The specified buffer length is too small
EFI_INVALID_PARAMETER BufferisNULL
EFI_INVALID_PARAMETER DataGuid isNULL
EFI_INVALID_PARAMETER LengthInBytes isNULL
EFI_NOT_FOUND Data blob was not found
V-17.3.12 EFI_I2C_IO_PROTOCOL.GetDeviceInfoIdList()
Summary
Get the list of data associated with the I2C device.
Prototype
typedef
(EFIAPI \*EFI_I2C_IO_GET_DEVICE_INFO_ID_LIST) (
IN CONST EFI_GUID ***GuidArray,
IN UINTN *GuidEntries
);
This
GuidArray
Address to receive the list of GUIDs
GuidEntries
Address to receive the number of entries in the GUID array
V-17.3. PEI Code definitions V-235UEFI Platform Initialization Specification, Release 1.8
This routine returns an array of GUIDs identifying data associated with the I2C device. When the caller is done with
the GUID array, the caller must call FreePool to return the GUID array to the heap.
The values returned from GetDeviceInfoIdList are:
EFI_SUCCESS The GUID array was returned successfully
EFI_INVALID_PARAMETER GuidArray isNULL
EFI_INVALID_PARAMETER GuidEntries isNULL
EFI_OUT_OF_RESOURCES Memory allocation failure
V-17.3.13 EFI_PEI_I2C_IO.StartRequest()
Summary
Start an I2C transaction on the I2C device.
Prototype
typedef
(EFIAPI \*EFI_PEI_I2C_BUS_START_REQUEST) (
);
This
designer, with the I2C device driver writer providing the slave address order.
array.
N.B.ThetypicalconsumersofthisAPIarethethirdpartyI2Cdrivers. Extremecaremustbetakenbyotherconsumers
ofthisAPItopreventconfusingthethirdpartyI2CdriversduetoastatechangeattheI2Cdevicewhichthethirdparty

Summary
Prototype
typedef
);
This
array.
I2C drivers did not initiate. I2C platform drivers may use this API within these guidelines.
This routine starts a transaction on the I2C device.
V-17.3. PEI Code definitions V-236UEFI Platform Initialization Specification, Release 1.8
EFI_NO_MAPPING Invalid I2cBusConfiguration value due to invalid platform data
V-17.3.14 I2C Bus Configuration Management PPI
V-17.3.15 EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT
Summary
TheEFII2CbusconfigurationmanagementPPIenablesthehostdrivertointeractwiththeplatformlayertoreconfigure
theswitchesandmultiplexersandsettheclockspeedfortheI2Cbus. ThisPPIalsoenablestheI2Chostdrivertoreset
an I2C device which may be locking up the I2C bus by holding the clock or data line low.
GUID
#define EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT_GUID \
{ 0xe721de6f, 0x145b, 0x4532, 0xbd, 0x78, 0x9b, 0x40, \
0x95, 0xc7, 0x46, 0x97 }
EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION␣
EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT_I2C_DEVICE_RESET I2cDeviceReset;
} EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT;
I2cDeviceReset
Perform a platform specific reset for the specified I2C part and the I2C controller.
Unique number identifying the I2C controller in the system.
TheI2CdriverstackusestheconceptofanI2Cbusconfigurationasawaytodescribeaparticularstateoftheswitches
V-17.3. PEI Code definitions V-237UEFI Platform Initialization Specification, Release 1.8
A simple I2C bus does not have any multiplexers or switches is described to the I2C driver stack with a single I2C bus
AnI2CbuswithswitchesandmultiplexersuseanI2Cbusconfigurationtodescribeeachoftheuniquesettingsforthe
switches and multiplexers. However the I2C platform driver only needs to define the I2C bus configurations that the
software uses, which is a subset of the total.
The upper layer driver locates the correct EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT interface
(I2cBusConfig) by comparing the following field:
•I2cBusConfigControllerNumber with the system unique value for the I2C ControllerNumber
TheI2CbusconfigurationmanagementPPIisanoptionalPPIprovidedbytheI2Cplatformdriver. TheI2Chostdriver
onlystartsforthisI2CcontrolleriftheI2CbusconfigurationmanagementPPIispresent. TheI2Chostdriverusesthe
I2CbusconfigurationmanagementPPItocallintotheI2Cplatformdrivertosettheswitchesandmultiplexersandset
the maximum I2C bus frequency.
V-17.3.16 EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT.EnableI2cBusConfiguration()
Summary
Prototype
typedef
(EFIAPI
*EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION) (
IN EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT *This,
IN UINTN I2cBusConfiguration
);
This
Address of an EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT structure.
Index into a list or array of I2C bus configurations
Reconfigure the switches and multiplexers in the I2C bus to enable access to a specific I2C bus configuration. Also
select the maximum clock frequency for this I2C bus configuration.
This routine uses the I2C Master PPI when the platform routine needs to perform I2C transactions on the local bus.
This eliminates any recursion in the I2C stack for configuration transactions on the local bus.
The platform layer must perform I2C transactions on other I2C busses by using the EFI_PEI_I2C_HOST PPI or third
party driver interface for the specific device. Use the EFI_PEI_I2C_HOST PPI when the device is not defined by the
V-17.3. PEI Code definitions V-238UEFI Platform Initialization Specification, Release 1.8
I2C platform driver. Use the third party driver when it is available or EFI_PEI_I2C_IO when the third party driver is
not available but the device is defined in the I2C platform driver.
The values returned from EnableI2cBusConfiguration are:
V-17.3.17 EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT.I2cDeviceReset()
Summary
Prototype
typedef
(EFIAPI
*EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT_I2C_DEVICE_RESET) (
IN CONST EFI_PEI_I2C_BUS_CONFIGURATION_MANAGEMENT *This,
IN UINTN SlaveAddress
);
This
Address of the device on the I2C bus.
ThiserrorhandlingroutineiscalledbytheI2Chostdriverwhen EFI_TIMEOUT statusisreturnedbytheI2Cportdriver
for anEFI_I2C_REQUEST_PACKET . This routine attempts to reset the failing I2C device and the I2C controller.
The values returned from I2cDeviceReset are:
V-17.3. PEI Code definitions V-239UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The transaction completed successfully Only the requested I2C de-
vice and the I2C controller were reset
EFI_NO_MEDIA State was lost because more than one device was reset The
host driver needs to return errors for the queue of pending
EFI_I2C_REQUEST_PACKETs
V-17.3.18 I2C Enumerate PPI
V-17.3.19 EFI_PEI_I2C_ENUMERATE
Summary
Support the enumeration of the I2C devices listed in the I2C platform driver.
GUID
#define EFI_PEI_I2C_ENUMERATE_GUID \
{ 0xbe83f6f4, 0xe286, 0x4e70, 0xb4, 0x51, 0x1a, 0x2e, \
0x42, 0xdf, 0x31, 0x03 }
EFI_PEI_I2C_ENUMERATE_ENUMERATE Enumerate;
EFI_PEI_I2C_ENUMERATE_GET_BUS_FREQUENCY GetBusFrequency;
} EFI_PEI_I2C_ENUMERATE;
Enumerate
Walk the platform’s list of I2C devices on the bus. This routine returns the next I2C device in the platform’s list
for this I2C bus.
Get the I2C bus frequency for the bus configuration.
The I2C bus driver uses this PPI to enumerate the devices on the I2C bus listed in the platform layer.
The upper layer driver locates the correct EFI_PEI_I2C_ENUMERATE interface (I2cEnumerate) by comparing the
following field:
•I2cEnumerateControllerNumber with the system unique value for the I2CControllerNumber .
V-17.3. PEI Code definitions V-240UEFI Platform Initialization Specification, Release 1.8
V-17.3.20 EFI_PEI_I2C_ENUMERATE_PROTOCOL.Enumerate()
Summary
Prototype
typedef
(EFIAPI \*EFI_PEI_I2C_ENUMERATE_ENUMERATE) (
IN EFI_PEI_I2C_ENUMERATE *This,
);
This

Enumerate
Summary
Prototype
typedef
);
This
Address of an EFI_PEI_I2C_ENUMERATE structure.
Device
Address of a buffer containing an EFI_I2C_DEVICE structure. Enumeration is started by setting the initial
EFI_I2C_DEVICE structure address to NULL. The buffer receives an EFI_I2C_DEVICE structure address for
This function walks the platform specific data to enumerate the I2C devices on an I2C bus.
The values returned from Enumerate are:
EFI_INVALID_PARAMETER Device was NULL
EFI_NO_MAPPING Device does not point to a valid EFI_I2C_DEVICE structure
V-17.3.21 EFI_PEI_I2C_ENUMERATE_PROTOCOL.GetBusFrequency()
Summary
Prototype
typedef
(EFIAPI *EFI_PEI_I2C_ENUMERATE_GET_BUS_FREQUENCY) (
IN UNITN I2cBusConfiguration,
);
This
V-17.3. PEI Code definitions V-241UEFI Platform Initialization Specification, Release 1.8
Address to receive the I2C bus clock frequency in Hertz
This function returns the I2C bus clock frequency for the specified I2C bus configuration.
The values returned from GetBusFrequency are:
Table 17.6: Status Codes Returned
EFI_SUCCESS The I2C bus frequency was returned
V-17.3. PEI Code definitions V-242CHAPTER
EIGHTEEN
SPI PROTOCOL STACK
V-18.1 Design Discussion
The SPI protocol stack enables third party silicon vendors to write UEFI drivers for their products by decoupling the
SPI chip details from the SPI controller and SPI bus configuration details.
V-18.1.1 SPI Bus Overview
Each peripheral on the SPI bus share the clock, data out and data in lines. The peripheral is addressed by using a
uniquechipselectline. Communicationswiththeperipheralmustbedoneatorbelowthemaximumclockratewhich
the peripheral supports and must use the proper clock polarity and phase.
Fig. 18.1: SPI Bus
TheSPIcontrollermustcontainthedatashiftregisterandclockgatinglogicwhichhonorsclockphase,clockpolarity
andonlypresentsclockpulseswhenvaliddataisontheSPIbus. TheSPIcontrollermustpausetheclockwhilewaiting
for more data.
IndependentlogicblocksmayprovidetheclockfrequencyusedbytheSPIcontrolleraswellastheGPIOsusedforthe
SPI chip selects.
V-243UEFI Platform Initialization Specification, Release 1.8
V-18.1.2 SPI Protocol Stack Overview
TheSPIdriverstackisbeingsplitonfunctionallines. MostofthecomplexityendsupintheSPIbuslayer,simplifying
the SPI peripheral, SPI controller and board layers.
Fig. 18.2: SPI Layers
The SPI protocol layers are:
•Application Layer - Applications using the SPI chips
•SPI Peripheral Layer - Converts an SPI chip request into one or more transactions on the SPI bus
•SPI Bus Layer - Handles:
–SPI Peripheral Device Enumeration
–SPI Transaction Management
–SPI Controller Management
•SPI Host Controller Layer - Handles details of the SPI controller
•SPI Board Layer - Contains:
–SPI bus descriptions
–SPI part descriptions
–Alternative SPI bus clock support
–Alternative SPI chip select support
The SPI bus layer provides a data connection point with an EFI_SPI_IO_PROTOCOL data structure for each SPI
peripheral. This data connection point exports the SpiPeripheralDriverGuid from theEFI_SPI_PART data structure.
The SPI peripheral drivers connect to the connection points with the corresponding GUID.
An example:
V-18.1. Design Discussion V-244UEFI Platform Initialization Specification, Release 1.8
AgenericSPIflashdriveriswrittenandprovidestheGUID{5993c862-5c3f-4ae8-804d-8c89ad962c31}forusebySPI
flash peripherals that meet the criteria specified by the developer of the SPI flash driver. The board developer chooses
anSPIflashpart,let’ssayaWinBondW25Q64FV.IdeallytheSPIchipvendorwouldprovideaheaderfilecontaining
theEFI_SPI_PART definition. When that is not available, the board developer could create an EFI_SPI_PART data
structure and fill it with data from the datasheet as follows:
CONST EFI_SPI_PART Winbond_W25Q64FV = {
L"Winbond",
L"W25Q64FV",
0,
MHz(104), // Page 75, 3.0V - 3.6V
FALSE // Page 6, Section 3.1
};
WhentheSPIbuslayercreatesthe EFI_SPI_IO_PROTOCOL datastructureforthisdevice,thegenericSPIflashdriver
is able to find and connect to it by calling OpenProtocol with the GUID specified above.
Some SPI chip examples:
•Maxim MAX3111E - UART and RS232 transceiver
•Maxim MAX6950 - Seven segment numeric LED controller
•Serial SPI NOR flash, one of:
–Atmel AT25DF321 - 4 MiB SPI NOR flash
–Winbond W2SQ80DV - 1 MiB SPI NOR flash
–Winbond W25Q16DV - 2 MiB SPI NOR flash
–Winbond W25Q32FV - 4 MiB SPI NOR flash
–Winbond W25Q64FV - 8 MiB SPI NOR flash
–Spansion S25FL164K - 16 MiB SPI NOR flash
–Micron N2SQ128A - 32 MiB SPI NOR flash
–Winbond W2SQ128FV - 32 MiB SPI NOR flash
The board vendor may provide example code which describes the SPI buses and SPI peripherals to simplify the con-
figuration process. The example code may be modified by the board consumer to adjust for added SPI devices or SPI
buses.
V-18.1.3 Application Layer
Theapplicationlayerinteractswithvariouschipspecificdriversusingvendorspecificprotocols. Exampleapplications
are:
•A background application which reads gets the system time once per second and uses the MAX6950 driver to
display the time on a four seven-segment displays.
•A background application which uses the Texas Instruments ADC108S102 driver to read a 10-bit voltage value
fromtheanalog-to-digitalconverteranddisplaystheresultonseven-segmentdisplaysdrivenbytheMAX6950.
V-18.1. Design Discussion V-245UEFI Platform Initialization Specification, Release 1.8
V-18.1.4 SPI Peripheral Layer
This layer provides vendor specific interfaces to the SPI chips. The upper interface to the SPI peripheral layer is chip
specificanddeterminedbytheUEFIorPlspecificationswherethereisastandardorbythechipvendorwhenastandard
does not exist.
The lower interface of the SPI peripheral layer connects to one or more of the SPI peripherals exposed by the SPI bus
layer as an EFI_SPI_IO_PROTOCOL instance. The SPI peripheral driver interacts with the SPI chip by issuing data
transactions to the SPI bus layer. These transactions make their way to the SPI controller layer where they are placed
onto the SPI bus and data is exchanged with the SPI chip.
V-18.1.5 SPI I/O Interface
The SPI bus layer creates an EFI_SPI_IO_PROTOCOL instance for each SPI chip listed in the board layer. However
unlike other protocols, the EFI_SPI_IO_PROTOCOL instance is identified by a GUID that is unique to the SPI chip
driver to which it should connect. This differs from other bus protocols which produce a bus-specific GUID.
The rational behind this is decision is based upon:
1. No common device support
2. Performance and code size
3. SPI device enumeration performed infrequently
V-18.1.5.1 No Common Device Support
With other protocols such as PCI and USB, even though the devices differ, there is a common hardware support layer
for peripheral identity, resource allocation and attaching the device to the bus. SPI chips differ in this respect because
there are no hardware standards! Bus attachment is done by the board developer at a hardware level. From a software
viewpointassoonaschipselectisasserted,theSPIchipisonthebus. AlsowithSPItherearenocommoncommands
thatmaybeissuedtoidentifyorenablethechip. Assuchthereisnoadvantageexposingthe EFI_SPI_IO_PROTOCOL
with a generic GUID.
V-18.1.5.2 Performance and Code Size
Times have changed since UEFI was originally architected and implemented. In todays world, the firmware engineers
arebeingaskedforsub-one-secondboottimesandasmallerfirmwarefootprintwithmorefunctionality. Usingageneric
GUIDforthe EFI_SPI_IO_PROTOCOL requiresthateachSPIperipheraldriverimplementmorecodetoverifysome
otheridentifiertodetermineifthedrivershouldusethisdevice. Thisadditionalcheckaddscostandcomplexitytothe
SPI peripheral driver. The costs are the development time to implement and debug the code as well as the CPU time
to execute the code. This code also has a multiplicative effect on the firmware footprint.
V-18.1.5.3 SPI Device Enumeration Performed Infrequently
The claim is that SPI device enumeration will be performed infrequently.
•How often is SPI device enumeration a necessary operation?
•Is it a requirement that this operation be done using a generic GUID for EFI_SPI_IO_PROTOCOL ?
•What are the use cases for this operation?
V-18.1. Design Discussion V-246UEFI Platform Initialization Specification, Release 1.8
EliminatingthegenericGUIDfor EFI_SPI_IO_PROTOCOL removesonewayofdoingSPIdeviceenumeration. How-
ever SPI device enumeration is still possible.
SPI device enumeration is easiest done using the EFI_SPI_CONFIGURATION_PROTOCOL . From this protocol is

possibletodeterminetheSPIbusesinthesystemandthedeviceswhichareattachedtothesebuses. Withalittleextra
work, calling LocateHandleBuffer it is possible to identify the handles which use the SPI driver GUID and match the
EFI_SPI_IO_PROTOCOL interface.
DevicepathsmayalsobeusedtofindhandleswhichareattachedtoaspecificSPIhostcontroller. EachSPIperipheral
attaches a HW_CONTROLLER node to the device path.
V-18.1.5.4 Synchronous Operation
All SPI I/O layer transactions are synchronous. No support is provided for asynchronous transactions.
V-18.1.5.5 SPI Transaction Management
TheSPII/Olayerallocatesa EFI_SPI_BUS_TRANSACTION datastructurewhichcontainstheparametersthatwillbe
passed to the SPI host controller as part of this SPI transaction. The SPI bus layer uses this structure to control and
complete the SPI transaction.
Synchronizing with the SPI bus layer schedules the SPI transaction on a free SPI host controller.
V-18.1.6 SPI Bus Layer
The SPI bus layer manages the SPI transactions for each of the host’s SPI controllers. SPI peripheral drivers submit
SPI transactions to the SPI bus layer which in turn submits them to the host’s SPI controller.
The SPI transaction consists of:
1. Adjusting the clock speed, polarity and phase for an SPI peripheral
2. Use the chip select to enable the SPI peripheral, signaling the transaction start to the chip
3. Transfer the data in one or both directions simultaneously
4. Remove the chip select from the SPI peripheral signaling the transaction end to the chip
5. Optionally, shutdown the SPI controller’s internal clock to reduce power
The SPI bus layer is responsible setting up the SPI clock and chip select. This ensures that the chip set up is done
properly across all SPI controller drivers. The SPI bus layer uses the SPI chip data from the board layer to determine
the clock phase and polarity. The clock frequency is the lowest frequency specified by:
•Maximum SPI controller clock frequency
•Supported SPI controller clock frequency < = SPI chip maximum clock frequency
•Supported SPI controller clock frequency < = non-zero ClockHz
After setting up the clock, the SPI bus layer asserts the appropriate chip select and then passes the SPI transaction to
theSPIcontrollertostartthedataflowinbothdirections. Uponcompletion,theSPIbuslayerdeassertsthechipselect
and completes the SPI transaction to the SPI peripheral layer.
V-18.1. Design Discussion V-247UEFI Platform Initialization Specification, Release 1.8
V-18.1.6.1 Half Duplex SPI controllers
VariousSPIcontrollerssupportahalf-duplexoperationinadditiontothefull-duplexoperation. Thebenefitsofthehalf-
duplexoperationonthesystemarethatlessphysicalmemorytiedupduringtheoperationandthememorybandwidth
is cut in half for the operation.
It is beneficial to the system for the SPI architecture to support the half duplex operations of the SPI controller. Ad-
ditionally it reduces code size and memory footprint by eliminating unnecessary buffers in the SPI peripheral drivers
when half-duplex operations are performed on the SPI chip.
Write Then Read Operations
SPI flash chips and some SPI UARTs support write then read operations using SPI. The NXP SC16IS750/760 is an
exampleofaUARTdesignedforI2CandSPIwhichperformshalf-duplexoperationswhichareamixoftransmitand
receive.
SPINORflashchipssuchastheWinbondW25Q64FValsoperformhalf-duplexoperationswhichareamixoftransmit
andreceive. Theseoperationconsistofwritingacommandbyteandpossiblyanaddressandthenimmediatelyreading
data either from the status register or memory.
SPI Controller Support
SinceSPIisinherentlyfull-duplex,theSPIhostcontrollershouldsupportfull-duplexoperation. NotallSPIcontrollers
however are able to support half-duplex or write-then-read operation. In this case, the SPI bus layer converts the SPI
transaction into a full-duplex transaction by allocating the necessary buffers and if necessary coping any write data
into the new buffer. The SPI bus layer then hands the full-duplex transaction to the SPI host controller for processing.
Upon completion, the SPI bus driver copies any necessary data from the full-duplex buffers into the SPI peripheral
layer’sreceivebufferandthenfreestheallocatedfull-duplexbuffers. ThisconversionallowstheSPIperipheraldrivers
to choose transaction types which optimize system resources and performance in the general case.
SPI Controller To SPI Bus Connection
For DXE, the SPI host controller is identified by the device path. The SPI board layer includes copy of this device
path in the ControllerPath field of the EFI_SPI_BUS structure. When the DXE version of the SPI bus layer locates
an SPI host controller, the SPI bus layer matches the device path for the SPI host controller to the device field in the
ControllerPath of theEFI_SPI_BUS structure in the board layer. Once this connection is made, the SPI bus layer can
create the necessary SPI I/O interfaces.
V-18.1.7 SPI Host Controller Layer
The SPI host controller layer provides a simple interface to the SPI controller. This layer only handles SPI controller
details for a single transaction.
The support at this layer is broken into three primary routines:
•Clock set up
•Chip selection
•Data movement
The SPI bus layer calls these routines to initiate and complete the SPI transaction.
V-18.1. Design Discussion V-248UEFI Platform Initialization Specification, Release 1.8
V-18.1.7.1 Legacy SPI Flash Controller
The legacy SPI flash controller is designed to handle SPI NOR flash devices. This controller has several limitations
and several security enhancements that impact the design of the SPI bus I/O layers and the SPI NOR flash peripheral
driver. The security enhancements include:
•BIOS base address
•Protect range registers
•Controller configuration lock
•Prefix type table
•Opcode menu table
•Opcode type table
The security enhancements are handled by the EFI_LEGACY_SPI_CONTROLLER_PROTOCOL . This protocol pro-
vides the functions support the security features of the legacy SPI flash controller as well as functions to work around
the flash targeted design of the controller.
The limitations of the legacy SPI flash controller include:
•8-bit frames only
•Fixed clock rate
•No full-duplex transaction support
•No read-only transaction support
•Reads: 64-byte maximum transfer length
•Writes: 67-byte maximum transfer length
•Prefix opcode table
These limitations are handled by:
•Setting frame size support to 8-bit only
•Using the legacy SPI flash controller’s clock routine to validate the requested clock frequency
•Letting the legacy SPI flash controller’s transaction routine fail the full-duplex and read-only transactions
•Setting the maximum transfer size to 64 bytes
•Adding a couple of flags to indicate that the opcode and 3 address bytes are included in the maximum transfer
size
•Using the EFI_LEGACY_SPI_CONTROLLER_PROTOCOL to set the erase block opcode
•Using the EFI_LEGACY_SPI_CONTROLLER_PROTOCOL to set the write status prefix opcode
V-18.1. Design Discussion V-249UEFI Platform Initialization Specification, Release 1.8
V-18.2 DXE Code Definitions
The SPI protocol stack consists of the following protocols:
•EFI_LEGACY_SPI_FLASH_PROTOCOL -TheupperlayersusethisprotocoltoaccesstheBIOSspaceaddress
and protection registers of the legacy SPI flash controller.
•EFI_SPI_NOR_FLASH_PROTOCOL -TheupperlayersusethisprotocoltointeractwithSPINORflashdevices.
•EFI_SPI_IO_PROTOCOL - The SPI peripheral drivers use this to interact with chips on the SPI bus.
•EFI_SPI_HC_PROTOCOL - The SPI bus layer uses this to interact with the host’s SPI controller.
•EFI_LEGACY_SPI_CONTROLLER_PROTOCOL - The flash layer uses this protocol to invoke the additional
functions provided by the legacy SPI controller.
•EFI_SPI_CONFIGURATION_PROTOCOL -TheSPIbuslayerusesthistointeractwiththeboardlayerdatabase
and additional logic blocks for clock and GPIO controllers.
V-18.2.1 EFI_SPI_CONFIGURATION_PROTOCOL
Summary
Describe the details of the board’s SPI buses to the SPI driver stack.
GUID
// {85a6d3e6-b65b-4afc-b38f-c6d54af6ddc8}
#define EFI_SPI_CONFIGURATION_GUID \
{ 0x85a6d3e6, 0xb65b, 0x4afc, { 0xb3, 0x8f, 0xc6, 0xd5, \
0x4a, 0xf6, 0xdd, 0xc8 }}
typedef struct _EFI_SPI_CONFIGURATION_PROTOCOL {
UINT32 BusCount;
CONST EFI_SPI_BUS *CONST *CONST Buslist;
} EFI_SPI_CONFIGURATION_PROTOCOL;
BusCount
The number of SPI buses on the board.
Buslist
The address of an array of EFI_SPI_BUS data structure addresses.
The board layer uses the EFI_SPI_CONFIGURATION_PROTOCOL to expose the data tables which describe the
board’s SPI buses. The SPI bus layer uses these tables to configure the clock and chip select, and manage the SPI
transactions on the SPI controllers.
The configuration tables describe:
•The number of SPI buses on the board
•Which SPI chips are connected to each SPI bus
For each SPI chip the configuration describes:
V-18.2. DXE Code Definitions V-250UEFI Platform Initialization Specification, Release 1.8

GUID
BusCount
Buslist
•The maximum clock frequency for the SPI part
•The clock polarity needed for the SPI part
•Whether the SPI controller uses a separate clock generator that needs to be set up
•The chip select polarity
•Whether the SPI controller or a GPIO pin is used for the chip select
•The data sampling edge for the SPI part.
TheEFI_SPI_PERIPHERAL andEFI_SPI_BUS data structures are defined later in this section.
V-18.2.2 EFI_SPI_CHIP_SELECT
Summary
Manipulate the chip select for an SPI device.
Prototype
typedef
(EFIAPI *EFI_SPI_CHIP_SELECT) (
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,
IN BOOLEAN PinValue
);
SpiPeripheral
Theaddressofan EFI_SPI_PERIPHERAL datastructuredescribingtheSPIperipheralwhosechipselectpinis
to be manipulated. The routine may access the ChipSelectParameter field to gain sufficient context to complete
PinValue
The value to be applied to the chip select line of the SPI peripheral.
This routine must be called at or below TPL_NOTIFY . Update the value of the chip select line for an SPI peripheral.
TheSPIbuslayercallsthisroutineeitherintheboardlayerorintheSPIcontrollertomanipulatethechipselectpinat
the start and end of an SPI transaction.
EFI_SUCCESS The chip select was set successfully
EFI_NOT_READY Support for the chip select is not properly initialized
EFI_INVALID_PARAMETER The SpiPeripheral ChipSelectParameter value is invalid
V-18.2. DXE Code Definitions V-251UEFI Platform Initialization Specification, Release 1.8
V-18.2.3 EFI_SPI_PART
Summary
Describe the properties of an SPI chip.
Prototype
typedef struct _EFI_SPI_PART
{
CONST CHAR16 *Vendor;
CONST CHAR16 *PartNumber;
UINT32 MinClockHz;
UINT32 MaxClockHz;
BOOLEAN ChipSelectPolarity;
} EFI_SPI_PART;
Vendor
A Unicode string specifying the SPI chip vendor.
PartNumber
A Unicode string specifying the SPI chip part number.
MinClockHz
The minimum SPI bus clock frequency used to access this chip. This value may be specified in the chip’s
datasheet. If not, use the value of zero.
MaxClockHz
The maximum SPI bus clock frequency used to access this chip. This value is found in the chip’s datasheet.
ChipSelectPolarity
Specify the polarity of the chip select pin. This value can be found in the SPI chip’s datasheet. Specify TRUE
when a one asserts the chip select and FALSEwhen a zero asserts the chip select.
TheEFI_SPI_PART datastructureprovidesadescriptionofanSPIpartwhichisindependentoftheuseontheboard.
This data is available directly from the part’s datasheet and may be provided by the vendor.
V-18.2.4 EFI_SPI_PERIPHERAL
Summary
Describe the board specific properties associated with a specific SPI chip.
Prototype
typedef struct _EFI_SPI_PERIPHERAL
{
CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral;
CONST CHAR16 *FriendlyName;
CONST GUID *SpiPeripheralDriverGuid;
CONST EFI_SPI_PART *SpiPart;
BOOLEAN ClockPolarity;
BOOLEAN ClockPhase;
V-18.2. DXE Code Definitions V-252UEFI Platform Initialization Specification, Release 1.8
CONST VOID *ConfigurationData;
CONST EFI_SPI_BUS *SpiBus;
EFI_SPI_CHIP_SELECT ChipSelect;
VOID *ChipSelectParameter;
} EFI_SPI_PERIPHERAL;
NextSpiPeripheral
Address of the next EFI_SPI_PERIPHERAL data structure. Specify NULL if the current data structure is the
last one on the SPI bus.
FriendlyName
A unicode string describing the function of the SPI part.
SpiPeripheralDriverGuid
Address of a GUID provided by the vendor of the SPI peripheral driver. Instead of using a ”
EFI_SPI_IO_PROTOCOL ”GUID,theSPIbusdriverusesthisGUIDtoidentifyan EFI_SPI_IO_PROTOCOL
data structure and to provide the connection points for the SPI peripheral drivers. This reduces the comparison
logic in the SPI peripheral EFI_DRIVER_BINDING_PROTOCOL.Supported() routine.
SpiPart
The address of an EFI_SPI_PART data structure which describes this chip.
The maximum clock frequency is specified in the EFI_SPI_PART . When this value is non-zero and less than
the value in the EFI_SPI_PART then this value is used for the maximum clock frequency for the SPI part.
ClockPolarity
Specify the idle value of the clock as found in the datasheet. Use zero (0) if the clock’s idle value is low or one
(1) if the clock’s idle value is high.
ClockPhase
Specify the clock delay after chip select. Specify zero (0) to delay an entire clock cycle or one (1) to delay only
half a clock cycle.
SPI peripheral attributes, select zero or more of:
•SPI_PART_SUPPORTS_2_BIT_DATA_BUS_WIDTH -TheSPIperipheraliswiredtosupportatwo-bitdatabus
•SPI_PART_SUPPORTS_4_BIT_DATA_BUS_WIDTH - The SPI peripheral is wired to support a four-bit data
bus
ConfigurationData
Address of a vendor specific data structure containing additional board configuration details related to the SPI
chip. The SPI peripheral layer uses this data structure when configuring the chip.
SpiBus
The address of an EFI_SPI_BUS data structure which describes the SPI bus to which this chip is connected.
ChipSelect
Address of the routine which controls the chip select pin for this SPI peripheral. Call the SPI host controller’s
chip select routine when this value is set to NULL.
ChipSelectParameter
Address of a data structure containing the additional values which describe the necessary control for the chip
select. When ChipSelect isNULL, the declaration for this data structure is provided by the vendor of the host’s
V-18.2. DXE Code Definitions V-253UEFI Platform Initialization Specification, Release 1.8
SPI controller driver. The vendor’s documentation specifies the necessary values to use for the chip select pin
selection and control.
WhenChipselect is notNULL, the declaration for this data structure is provided by the board layer.
TheEFI_SPI_PERIPHERAL data structure describes how a specific block of logic which is connected to the SPI
bus. This data structure also selects which upper level driver is used to manipulate this SPI device. The SpiPeripher-
aLDriverGuid is available from the vendor of the SPI peripheral driver.
V-18.2.5 EFI_SPI_CLOCK
Summary
Set up the clock generator to produce the correct clock frequency, phase, and polarity for an SPI chip.
Prototype
typedef
(EFIAPI *EFI_SPI_CLOCK) (
IN UINT32 *ClockHz
);
Pointer to a EFI_SPI_PERIPHERAL data structure from which the routine can access the ClockParameter ,
ClockPhase, andClockPolarity fields. The routine also has access to the names for the SPI bus and chip which
can be used during debugging.
ClockHz
Pointer to the requested clock frequency. The clock generator will choose a supported clock frequency which is
lessthenorequaltothisvalue. Specifyzerototurntheclockgeneratoroff. Theactualclockfrequencysupported
by the clock generator will be returned.
This routine updates the clock generator to generate the correct frequency and polarity for the SPI clock.
EFI_SUCCESS The clock was set up successfully
EFI_UNSUPPORTED The SPI controller was not able to support the frequency requested
by ClockHz
V-18.2. DXE Code Definitions V-254UEFI Platform Initialization Specification, Release 1.8
V-18.2.6 EFI_SPI_BUS
Summary
Describe the board specific details associated with an SPI bus.
Prototype
typedef struct _EFI_SPI_BUS {
CONST EFI_SPI_PERIPHERAL *Peripherallist;
CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath;
EFI_SPI_CLOCK Clock;
VOID *ClockParameter;
} EFI_SPI_BUS;
A Unicode string describing the SPI bus
Peripheral List
Address of the first EFI_SPI_PERIPHERAL data structure connected to this bus. Specify NULLif there are no
SPI peripherals connected to this bus.
ControllerPath
Address of an EFI_DEVICE_PATH_PROTOCOL data structure which uniquely describes the SPI controller.
Clock
Address of the routine which controls the clock used by the SPI bus for this SPI peripheral. The SPI host con-
troller’s clock routine is called when this value is set to NULL.
ClockParameter
Address of a data structure containing the additional values which describe the necessary control for the clock.
WhenClockisNULL,thedeclarationforthisdatastructureisprovidedbythevendorofthehost’sSPIcontroller
driver. When Clockis notNULL, the declaration for this data structure is provided by the board layer.
TheEFI_SPI_BUS data structure provides the connection details between the physical SPI bus and the
EFI_SPI_HC_PROTOCOL instance which controls that SPI bus. This data structure also describes the details of
how the clock is generated for that SPI bus. Finally this data structure provides the list of physical SPI devices which
are attached to the SPI bus.
Summary
Macros to easily specify frequencies in hertz, kilohertz and megahertz.
Prototype
#define Hz(Frequency) (Frequency)

Summary
Prototype
#define KHz(Frequency) (1000 * Hz(Frequency))
#define MHz(Frequency) (1000 * KHz(Frequency))
V-18.2. DXE Code Definitions V-255UEFI Platform Initialization Specification, Release 1.8
V-18.2.7 EFI_SPI_NOR_FLASH_PROTOCOL
Summary
TheEFI_SPI_NOR_FLASH_PROTOCOL exists in the SPI peripheral layer. This protocol manipulates the SPI NOR
flash parts using a common set of commands. The board layer provides the interconnection and configuration details
fortheSPINORflashpart. TheSPINORflashdriverusesthisconfigurationdatatoexposeagenericinterfacewhich
provides the following APls:
•Read manufacture and device ID
•Read data
•Read data using low frequency
•Read status
•Write data
•Erase 4 KiB blocks
•Erase 32 or 64 KiB blocks
•Write status
TheEFI_SPI_NOR_FLASH_PROTOCOL also exposes some APls to set the security features on the legacy SPI flash
GUID
// {b57ec3fe-f833-4ba6-8578-2a7d6a87444b}
#define EFI_SPI_NOR_FLASH_PROTOCOL_GUID \
{ 0xb57ec3fe, 0xf833, 0x4ba6, { 0x85, 0x78, 0x2a, 0x7d, \
0x6a, 0x87, 0x44, 0x4b }}
struct _EFI_SPI_NOR_FLASH_PROTOCOL {
CONST EFI_SPI_PERIPHERAL \*SpiPeripheral;
UINT32 FlashSize;
UINT8 DeviceId [3];
UINT32 EraseBlockBytes;
EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID GetFlashId;
EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA ReadData;
EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA LfReadData;
EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS ReadStatus;
EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS WriteStatus;
EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA WriteData;
EFI_SPI_NOR_FLASH_PROTOCOL_ERASE Erase;
};
Pointer to an EFI_SPI_PERIPHERAL data structure
FlashSize
Flash size in bytes
DeviceId
Manufacturer and Device ID
V-18.2. DXE Code Definitions V-256UEFI Platform Initialization Specification, Release 1.8
EraseBlockBytes
Erase block size in bytes
V-18.2.8 SPI Flash Driver GUID
Use a pointer to gEfiSpiNorFlashDriverGuid in theEFI_SPI_PERIPHERAL structure to connect an SPI NOR flash
part to the SPI flash driver.
V-18.2.9 EFI_SPI_NOR_FLASH_PROTOCOL.GetFlashld()
Summary
Read the 3 byte manufacture and device ID from the SPI flash.
Prototype
typedef
(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID) (
IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,
);
This
Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure.
Buffer
Pointer to a 3 byte buffer to receive the manufacturer and device ID.
This routine reads the 3 byte manufacture and device ID from the flash part filling the buffer provided.
EFI_SUCCESS The manufacture and device ID was read successfully
EFI_DEVICE_ERROR Invalid data received from SPI flash part
V-18.2.10 EFI_SPI_NOR_FLASH_PROTOCOL.ReadData()
Summary
Read data from the SPI flash.
Prototype
typedef
(EFIAPI \*EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA) (
V-18.2. DXE Code Definitions V-257UEFI Platform Initialization Specification, Release 1.8
IN UINT32 FlashAddress,
IN UINT32 LengthInBytes, OUT UINT8 *Buffer
);
This
FlashAddress
Address in the flash to start reading
Read length in bytes
Buffer
Address of a buffer to receive the data
This routine reads data from the SPI part in the buffer provided.
EFI_SUCCESS The data was read successfully.
EFI_INVALID_PARAMETER FlashAddress >= This->FlashSize
EFI_INVALID_PARAMETER LengthInBytes > This->FlashSize - FlashAddress
V-18.2.11 EFI_SPI_NOR_FLASH_PROTOCOL.LfReadData()
Summary
Low frequency read data from the SPI flash.
Prototype
typedef
(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA) (
IN UINT32 LengthInBytes,
OUT UINTS *Buffer
);
This
V-18.2. DXE Code Definitions V-258UEFI Platform Initialization Specification, Release 1.8
Buffer
V-18.2.12 EFIEFI_SPI_NOR_FLASH_PROTOCOL.ReadStatus()
Summary
Read the flash status register.
Prototype
typedef
EFI STATUS
(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS) (
OUT UINT8 *FlashStatus
);
This
Number of status bytes to read.
FlashStatus
Pointer to a buffer to receive the flash status.
This routine must be called at or below TPL_NOTIFY . This routine reads the flash part status register.
EFI_SUCCESS The status register was read successfully.
V-18.2. DXE Code Definitions V-259UEFI Platform Initialization Specification, Release 1.8
V-18.2.13 EFI_SPI_NOR_FLASH_PROTOCOL.WriteStatus()
Summary
Write the flash status register.
Prototype
typedef
(EFIAPI \*EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS) (
IN UINT8 *FlashStatus
);
This
Number of status bytes to write.
Pointer to a buffer containing the new status.
This routine must be called at or below TPL_NOTIFY . This routine writes the flash part status register.
EFI_SUCCESS The status write was successful.
EFI_OUT_OF_RESOURCES Failed to allocate the write buffer.
V-18.2.14 EFI_SPI_NOR_FLASH_PROTOCOL.WriteData()
Summary
Write data to the SPI flash.
Prototype
typedef
(EFIAPI \*EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA) (
);
This
V-18.2. DXE Code Definitions V-260UEFI Platform Initialization Specification, Release 1.8
Address in the flash to start writing
Write length in bytes
Buffer
Address of a buffer containing the data
This routine breaks up the write operation as necessary to write the data to the SPI part.
EFI_SUCCESS The data was written successfully.
EFI_OUT_OF_RESOURCES Insufficient memory to copy buffer.
V-18.2.15 EFI_SPI_NOR_FLASH_PROTOCOL.Erase()
Summary
Efficiently erases one or more 4KiB regions in the SPI flash.
Prototype
typedef
(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_ERASE) (
IN UINT32 BlockCount
);
This
Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure
Address within a 4 KiB block to start erasing
BlockCount
Number of 4 KiB blocks to erase
This routine uses a combination of 4 KiB and larger blocks to erase the specified area.
V-18.2. DXE Code Definitions V-261UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The erase was completed successfully
EFI_INVALID_PARAMETER FlashAddress This FlashSize
EFI_INVALID_PARAMETER BlockCount 4 KiB This FlashSize FlashAddress
V-18.2.16 EFI_LEGACY_SPI_FLASH_PROTOCOL
Summary
The EFI_LEGACY _SPI_FLASH_PROTOCOL extends the EFI_SPI_NOR_FLASH_PROTOCOL with APls to sup-
port the legacy SPI flash controller.
GUID
// {f01bed57-04bc-4f3f-9660-d6f2ea228259}
#define EFI_LEGACY_SPI_FLASH_PROTOCOL_GUID \
{ 0xf01bed57, 0x04bc, 0x4f3f, { 0x96, 0x60, 0xd6, 0xf2, \
0xea, 0x22, 0x82, 0x59 }}
struct _EFI_LEGACY_SPI_FLASH_PROTOCOL {
EFI_SPI_NOR_FLASH_PROTOCOL FlashProtocol;
///
/// Legacy flash (SP! host) controller support
///
EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;
EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;
EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;
EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;
EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER LockController;
};
V-18.2.17 EFI_LEGACY _SPI_FLASH_PROTOCOL.BiosBaseAddress()
Summary
Set the BIOS base address.
Prototype
typedef

Summary
GUID
///
///
};
Summary
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS) (
IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,
IN UINT32 BiosBaseAddress
);
This
Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure.
BiosBaseAddress
The BIOS base address.
V-18.2. DXE Code Definitions V-262UEFI Platform Initialization Specification, Release 1.8
TheBIOSbaseaddressworkswiththeprotectrangeregisterstoprotectportionsoftheSPINORflashfromeraseand
write operations . The BIOS calls this API prior to passing control to the OS loader.
EFI_SUCCESS The BIOS base address was properly set
EFI_ACCESS_ERROR The SPI controller is locked
EFI_INVALID_PARAMETER The BIOS base address was already set
EFI_UNSUPPORTED The BIOS base address was already set
EFI_UNSUPPORTED Not a legacy SPI host controller
V-18.2.18 EFI_LEGACY _SPI_FLASH_PROTOCOL.ClearSpiProtect()
Summary
Clear the SPI protect range registers.
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT) (
IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This
);
This
The BIOS uses this routine to set an initial condition on the SPI protect range registers.
EFI_SUCCESS The registers were successfully cleared
V-18.2.19 EFI_LEGACY _SPI_FLASH_PROTOCOL.lsRangeProtected()
Summary
Determine if the SPI range is protected.
Prototype
V-18.2. DXE Code Definitions V-263UEFI Platform Initialization Specification, Release 1.8
typedef
BOOLEAN
(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED) (
IN UINT32 BiosAddress,
IN UINT32 BlocksToProtect
);
This
BiosAddress
Address within a 4 KiB block to start protecting.
BlocksToProtect
The number of 4 KiB blocks to protect.
The BIOS uses this routine to verify a range in the SPI is protected.
TRUE The range is protected
FALSE The range is not protected
V-18.2.20 EFI_LEGACY_SPI_FLASH_PROTOCOL.ProtectNextRange()
Summary
Set the next protect range register.
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE) (
);
This
V-18.2. DXE Code Definitions V-264UEFI Platform Initialization Specification, Release 1.8
TheBIOSsetstheprotectrangeregistertopreventwriteanderaseoperationstoaportionoftheSPINORflashdevice.
EFI_SUCCESS The register was successfullyupdated
EFI_INVALID_PARAMETER BiosAddress <This->BiosBaseAddress
EFI_INVALID_PARAMETER BlocksToProtect * 4 KiB >This->MaximumRangeBytes
EFI_INVALID_PARAMETER BiosAddress-This->BiosBaseAddress+(BlocksToProtect*4KiB)>
This->MaximumRangeBytes
EFI_OUT_OF_RESOURCES No protect range registeravailable
EFI_UNSUPPORTED CallThis->SetBaseAddress because the BIOS base address is not
set
V-18.2.21 EFI_LEGACY _SPI_FLASH_PROTOCOL.LockController()
Summary
Lock the SPI controller configuration.
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER) (
IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL \*This
);
This
This routine locks the SPI controller’s configuration so that the software is no longer able to update:
•Prefix table
•Opcode menu
EFI_SUCCESS The SPI controller was successfully locked
EFI_ALREADY_STARTED The SPI controller was already locked
V-18.2. DXE Code Definitions V-265UEFI Platform Initialization Specification, Release 1.8
V-18.2.22 EFI_SPI_IO_PROTOCOL
Summary
Support managed SPI data transactions between the SPI controller and an SPI chip.
GUID
The SPI peripheral layer provides the GUID for this interface!
typedef struct _EFI_SPI_IO_PROTOCOL {
CONST EFI_SPI_PERIPHERAL *SpiPeripheral;
CONST EFI_SPI_PERIPHERAL *OriginalSpiPeripheral;
UINT32 FrameSizeSupportMask;
UINT32 MaximumTransferBytes;
CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *LegacySpiProtocol;
EFI_SPI_IO_PROTOCOL_TRANSACTION Transaction;
EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral;
} EFI_SPI_IO_PROTOCOL;
Address of an EFI_SPI_PERIPHERAL data structure associated with this protocol instance.
OriginalSpiPeripheral
Address of the original EFI_SPI_PERIPHERAL data structure associated with this protocol instance.
FrameSizeSupportMask
Mask of frame sizes which the SPI I/O layer supports. Frame size of N-bits is supported when bit N-1 is set.
The host controller must support a frame size of 8-bits. Frame sizes of 16, 24 and 32-bits are converted to 8-bit
frame sizes by the SPI bus layer if the frame size is not supported by the SPI host controller.
MaximumTransferBytes
Maximum transfer size in bytes: 1 - 0xffffffff
Transaction attributes: One or more from:
•SPl_IO_SUPPORTS_2_B1T_DATA_BUS_W1DTH - The SPI host and peripheral supports a two-bit data bus
•SPI_IO_SUPPORTS_4_BIT_DATA_BUS_W1DTH - The SPI host and peripheral supports a four-bit data bus
•SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE - Transfer size includes the opcode byte
•SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS - Transfer size includes the 3 address bytes
LegacySpiProtocol;
Pointer to legacy SPI controller protocol
V-18.2. DXE Code Definitions V-266UEFI Platform Initialization Specification, Release 1.8
V-18.2.23 EFI_SPI_BUS_ TRANSACTION
TheEFI_SPI_BUS_TRANSACTION data structure contains the description of the SPI transaction to perform on the
Prototype
typedef struct _EFI_SPI_BUS_TRANSACTION
{
EFI_SPI_TRANSACTION_TYPE TransactionType;
BOOLEAN DebugTransaction;
UINT32 BusWidth; UINT32 FrameSize;
UINT32 WriteBytes; UINT8 *WriteBuffer;
UINT32 ReadBytes; UINT8 *ReadBuffer;
} EFI_SPI_BUS_TRANSACTION;
Pointer to the SPI peripheral being manipulated.
TransactionType
Type of transaction specified by one of the EFI_SPI_TRANSACTION_TYPE values.
DebugTransaction
TRUEifthetransactionisbeingdebugged. DebuggingmaybeturnedonforasingleSPItransaction. Onlythis
transactionwilldisplaydebuggingmessages. Allothertransactionswiththisvaluesetto FALSEwillnotdisplay
any debugging messages.
BusWidth
SPI bus width in bits: 1, 2, 4
FrameSize
Frame size in bits, range: 1 - 32
WriteBytes
Length of the write buffer in bytes
WriteBuffer
Buffer containing data to send to the SPI peripheral Frame sizes 1-8 bits: UINT8 (one byte) per frame Frame
sizes 7-16 bits: UINT16 (two bytes) per frame
Frame sizes
17-32 bits: UINT32 (four bytes) per frame
Read Bytes
Length of the read buffer in bytes
Read Buffer
Buffer to receive the data from the SPI peripheral
•Frame sizes 1-8 bits: UINT8 (one byte) per frame
•Frame sizes 7-16 bits: UINT16 (two bytes) per frame
•Frame sizes 17-32 bits: UINT32 (four bytes) per frame
V-18.2. DXE Code Definitions V-267UEFI Platform Initialization Specification, Release 1.8
V-18.2.24 EFI_SPI_IO_PROTOCOL.Transaction()
Summary
Initiate an SPI transaction between the host and an SPI peripheral.
Prototype
typedef
(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION) (
IN CONST EFI_SPI_IO_PROTOCOL *This,
IN EFI_SPI_TRANSACTION_TYPE TransactionType,
IN BOOLEAN DebugTransaction,
IN UINT32 ClockHz OPTIONAL,
IN UINT32 BusWidth,
IN UINT32 FrameSize,
IN UINT32 WriteBytes,
IN UINT8 *WriteBuffer,*
IN UINT32 ReadBytes,*
OUT UINT8 *ReadBuffer
);
This
Pointer to an EFI_SPI_IO_PROTOCOL structure.
typedef enum \_EFI_SPI_TRANSACTION_TYPE {
SPI_TRANSACTION_FULL_DUPLEX = 0,
SPI_TRANSACTION_WRITE_ONLY,
SPI_TRANSACTION_READ_ONLY,
SPI_TRANSACTION_WRITE_THEN_READ
} EFI_SPI_TRANSACTION_TYPE;
Type of SPI transaction specified by one of the EFI_SPI_TRANSACTION_ TYPE values:
•SPI_TRANSACTION_FULL_DUPLEX - Data flowing in both direction between the host and SPI peripheral.
ReadBytes must equal WriteBytes and bothReadBuffer andWriteBuffer must be provided.
•SPI_TRANSACTION_WRITE_ONLY - Data flowing from the host to the SPI peripheral. ReadBytes must be
zero.WriteBytes must be non-zero and WriteBuffer must be provided.

);
This
•SPI_TRANSACTION_READ_ONLY -DataflowingfromtheSPIperipheraltothehost. WriteBytes mustbezero.
ReadBytes must be non-zero and ReadBuffer must be provided.
•SPI_TRANSACTION_WRITE_THEN_READ - Data first flowing from the host to the SPI peripheral and then
data flows from the SPI peripheral to the host. These types of operations get used for SPI flash devices when
control data (opcode, address) must be passed to the SPI peripheral to specify the data to be read.
SetTRUEonlywhendebuggingisdesired. DebuggingmaybeturnedonforasingleSPItransaction. Onlythis
ClockHz
Specifythe ClockHzvalueaszero(0)tousethemaximumclockfrequencysupportedbytheSPIcontrollerand
V-18.2. DXE Code Definitions V-268UEFI Platform Initialization Specification, Release 1.8
part. Specify a non-zero value only when a specific SPI transaction requires a reduced clock rate.
BusWidth
Width of the SPI bus in bits: 1, 2, 4
FrameSize
The length of the WriteBuffer in bytes. Specify zero for read-only operations.
The buffer containing data to be sent from the host to the SPI chip. Specify NULLfor read only operations.
The transmit frame is in the least significant N bits.
ReadBytes
The length of the ReadBuffer in bytes. Specify zero for write-only operations.
ReadBuffer
The buffer to receive data from the SPI chip during the transaction. Specify NULLfor write only operations.
The received frame is in the least significant N bits.
ThisroutineworkswiththeSPIbuslayertopasstheSPItransactiontotheSPIcontrollerforexecutionontheSPIbus.
There are four types of supported transactions supported by this routine:
•Full Duplex: WriteBuffer andReadBuffer are the same size.
•Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0
•Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0
•Write Then Read: WriteBuffer contains control data to write to SPI peripheral before data is placed into the
ReadBuffer . BothWriteBytes andReadBytes must be non-zero.
EFI_SUCCESS The SPI transaction completed successfully
EFI_BAD_BUFFER_SIZE The WriteBytes value was invalid
EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid
EFI_INVALID_PARAMETER TransactionType is not valid
EFI_INVALID_PARAMETER BusWidth not supported by SPI peripheral or SPI host controller
EFI_INVALID_PARAMETER WriteBytes is non zero and WriteBuffer is NULL
EFI_INVALID_PARAMETER ReadBytes non zero and ReadBuffer is NULL
EFI_INVALID_PARAMETER ReadBuffer WriteBuffer for full duplex type
EFI_INVALID_PARAMETER WriteBuffer was NULL
V-18.2. DXE Code Definitions V-269UEFI Platform Initialization Specification, Release 1.8
Table 18.1 – continued from previous page
EFI_INVALID_PARAMETER TPL is too high
EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction
EFI_UNSUPPORTED TheFrameSizeisnotsupportedbytheSPIbuslayerortheSPIhost
controller
by ClockHz
V-18.2.25 EFI_SPI_IO_PROTOCOL.UpdateSpiPeripheral()
Summary
Update the SPI peripheral associated with this SPI I/O instance.
Prototype
typedef
(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL) (
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral
);
This
Pointer to an EFI_SPI_PERIPHERAL structure.
Support socketed SPI parts by allowing the SPI peripheral driver to replace the SPI peripheral after the connection is
made. AnexampleuseissocketedSPINORflashparts,wherethesizeandparameterschangedependingupondevice
is in the socket.
EFI_SUCCESS The SPI peripheral was updated successfully
EFI_INVALID_PARAMETER TheSpiPeripheral value isNULL
EFI_INVALID_PARAMETER TheSpiPeripheral->SpiBus isNULL
EFI_INVALID_PARAMETER TheSpiPeripheral->SpiBus pointing at wrong bus
EFI_INVALID_PARAMETER TheSpiPeripheral->SpiPart isNULL
V-18.2.26 EFI_SPI_HC_PROTOCOL
Summary
Support an SPI data transaction between the SPI controller and an SPI chip.
GUID
// {c74e5db2-fa96-4ae2-b399-15977fe3002d}
#define EFI_SPI_HOST_GUID \
V-18.2. DXE Code Definitions V-270UEFI Platform Initialization Specification, Release 1.8
{ 0xc74e5db2, 0xfa96, 0x4ae2, { 0xb3, 0x99, 0x15, 0x97, \
0x7f, 0xe3, 0x0, 0x2d }}
typedef struct _EFI_SPI_HC_PROTOCOL {
EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;
EFI_SPI_HC_PROTOCOL_CLOCK Clock;
EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;
} EFI_SPI_HC_PROTOCOL;
Host control attributes, may have zero or more of the following set:
•HC_SUPPORTS_WRITE_ONLY_OPERATIONS
•HC_SUPPORTS_READ_ONLY_OPERATIONS
•HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS
•HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS - The SPI host controller requires the transmit
frame to be in most significant bits instead of least significant bits. The host driver will adjust the
frames if necessary.
•HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS - The SPI host controller places the receive
frames to be in the least significant bits if necessary.
•HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH - The SPI controller supports a two-bit data bus
•HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH - The SPI controller supports a four-bit data bus
•HC_TRANSFER_SIZE_INCLUDES_OPCODE - Transfer size includes the opcode byte
•HC_TRANSFER_SIZE_INCLUDES_ADDRESS - Transfer size includes the 3 address bytes
TheSPIhostcontrollermustsupportfull-duplex(receivewhilesending)operation. TheSPIhostcontroller
must support a one-bit bus width.
Mask of frame sizes which the SPI host controller supports. Frame size of N-bits is supported when bit N-1 is
set. The host controller must support a frame size of 8-bits.
V-18.2. DXE Code Definitions V-271UEFI Platform Initialization Specification, Release 1.8
V-18.2.27 EFI_SPI_HC_PROTOCOL.ChipSelect()
Summary
Assert or deassert the SPI chip select.
Prototype
typedef
(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (
IN CONST EFI_SPI_HC_PROTOCOL *This,
);
This
Pointer to an EFI_SPI_HC_PROTOCOL structure.
PinValue
This routine is called at TPL_NOTIFY .
Update the value of the chip select line for an SPI peripheral. The SPI bus layer calls this routine either in the board
layer or in the SPI controller to manipulate the chip select pin at the start and end of an SPI transaction.
EFI_SUCCESS The chip select was set as requested
EFI_INVALID_PARAMETER The ChipSelect value or its contents are invalid
V-18.2.28 EFI_SPI_HC_PROTOCOL.Clock()
Summary
Set up the clock generator to produce the correct clock frequency, phase and polarity for an SPI chip.
Prototype
typedef
(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (
);
V-18.2. DXE Code Definitions V-272UEFI Platform Initialization Specification, Release 1.8
This
Pointer to a EFI_SPI_PERIPHERAL data structure from which the routine can access the CLockParameter,
CLockPhaseandCLockPolarityfields. TheroutinealsohasaccesstothenamesfortheSPIbusandchipwhich
ClockHz
Pointertotherequestedclockfrequency. TheSPIhostcontrollerwillchooseasupportedclockfrequencywhich
is less then or equal to this value. Specify zero to turn the clock generator off. The actual clock frequency
supported by the SPI host controller will be returned.

);
This
ClockHz
by ClockHz
V-18.2.29 EFI_SPI_HC_PROTOCOL.Transaction()
Summary
Perform the SPI transaction on the SPI peripheral using the SPI host controller.
Prototype
typedef
EFI_STATUS*
(EFIAPI \*EFI_SPI_HC_PROTOCOL_TRANSACTION) (
IN EFI_SPI_BUS_TRANSACTION *BusTransaction
);
This
BusTransaction
Pointer to a EFI_SPI_BUS_TRANSACTION containing the description of the SPI transaction to perform.
This routine synchronously returns EFI_SUCCESS indicating that the asynchronous SPI transaction was started. The
routine then waits for completion of the SPI transaction prior to returning the final transaction status.
V-18.2. DXE Code Definitions V-273UEFI Platform Initialization Specification, Release 1.8
EFI_BAD_BUFFER_SIZE TheBusTransaction->WriteBytes value is invalid
EFI_BAD_BUFFER_SIZE TheBusTransaction->ReadinBytes value is invalid
EFI_UNSUPPORTED TheBusTransaction->TransactionType is unsupported
V-18.2.30 EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
Summary
Support the extra features of the legacy SPI flash controller.
GUID
// {39136fc7-lall-49de-bf35-0e78ddb524fc}
#define EFI_LEGACY_SPI_CONTROLLER_GUID \
{ 0x39136fc7, 0xlall, 0x49de, { 0xbf, 0x35, 0x0e, 0x78, \
0xdd, 0xb5, 0x24, 0xfc }}
typedef struct \_EFI_LEGACY_SPI_CONTROLLER_PROTOCOL {
UINT32 MaximumOffset; UINT32 MaximumRangeBytes;
UINT32 RangeRegisterCount;
EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE EraseBlockOpcode;
EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix;
EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;
EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;
EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;
EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;
EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER LockController;
} EFI_LEGACY_SPI_CONTROLLER_PROTOCOL;
MaximumOffset
Maximum offset from the BIOS base address that is able to be protected.
MaximumRangeBytes
Maximum number of bytes that can be protected by one range register.
RangeRegisterCount
The number of registers available for protecting the BIOS.
V-18.2.31 EFI_LEGACY_SPI_CONTROLLER_PROTOCOL.EraseBlockOpcode()
Summary
Set the erase block opcode.
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE) (
V-18.2. DXE Code Definitions V-274UEFI Platform Initialization Specification, Release 1.8
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
IN UINT8 EraseBlockOpcode
);
This
Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
EraseBlockOpcode
Erase block opcode to be placed into the opcode menu table.
ThemenutablecontainsSPItransactionopcodeswhichareaccessibleafterthelegacySPIflashcontroller’sconfigura-
tionislocked. TheboardlayerspecifiestheeraseblocksizefortheSPINORflashpart. TheSPINORflashperipheral
driverselects theeraseblock opcodewhich matchestheerase blocksizeand usesthisAPI toload theopcodeinto the
opcode menu table.
EFI_SUCCESS The opcode menu was updated
V-18.2.32 EFI_LEGACY_SPI_CONTROLLER_PROTOCOL.WriteStatusPrefix()
Summary
Set the write status prefix opcode.
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX) (
IN UINT8 WriteStatusPrefix
);
This
WriteStatusPrefix
Prefix opcode for the write status command.
TheprefixtablecontainsSPItransactionwriteprefixopcodeswhichareaccessibleafterthelegacySPIflashcontroller’s
configuration is locked. The board layer specifies the write status prefix opcode for the SPI NOR flash part. The SPI
NOR flash peripheral driver uses this API to load the opcode into the prefix table.
V-18.2. DXE Code Definitions V-275UEFI Platform Initialization Specification, Release 1.8
EFI_SUCCESS The prefix table was updated
V-18.2.33 EFI_LEGACY_SPI_CONTROLLER_PROTOCOL.BiosBaseAddress()
Summary
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS) (
);
This
write operations. The BIOS calls this API prior to passing control to the OS loader.
EFI_INVALID_PARAMETER The BIOS base address is greater than This MaximumOffset
V-18.2.34 EFI_LEGACY_SPI_CONTROLLER_PROTOCOL.ClearSpiProtect()
Summary
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT) (
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This
);
V-18.2. DXE Code Definitions V-276UEFI Platform Initialization Specification, Release 1.8
This
This routine must be called at or below TPL_NOTIFY.
V-18.2.35 EFI_LEGACY_SPI_CONTROLLER_PROTOCOL.lsRangeProtected()
Summary
Prototype
typedef
BOOLEAN
(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED) (
);
This
BytesToProtect
This routine must be called at or below TPL_NOTIFY. The BIOS uses this routine to verify a range in the SPI is
protected.
V-18.2. DXE Code Definitions V-277UEFI Platform Initialization Specification, Release 1.8
V-18.2.36 EFI_LEGACY_SPI_CONTROLLER_PROTOCOL.ProtectNextRange()
Summary
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE) (
);
This
This>MaximumRangeBytes
EFI_OUT_OF_RESOURCES No protect range register available
EFI_UNSUPPORTED CallThis->SetBaseAddress becausetheBIOSbaseaddressisnotset
V-18.2.37 EFI_LEGACY_SPI_CONTROLLER_PROTOCOL.LockController()
Summary
Prototype
typedef
(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER) (
);
V-18.2. DXE Code Definitions V-278UEFI Platform Initialization Specification, Release 1.8
This
V-18.2. DXE Code Definitions V-279CHAPTER
NINETEEN
V-19.1 Error Code Definitions
For 32-bit architecture:

Summary
Prototype
typedef
);
This
NINETEEN
#define EFI_INTERRUPT_PENDING 0xa0000000
#define EFI_WARN_INTERRUPT_SOURCE_PENDING 0x20000000
#define EFI_WARN_INTERRUPT_SOURCE_QUIESCED 0x20000001
For 64-bit architecture:
#define EFI_INTERRUPT_PENDING 0xa000000000000000
#define EFI_WARN_INTERRUPT_SOURCE_PENDING 0x2000000000000000
#define EFI_WARN_INTERRUPT_SOURCE_QUIESCED 0x2000000000000001
V-280INDEX
Symbols
16-bit PC Card ,V-1
A
AP,II-127
B
BSP,II-127
C
CardBay PC Card ,V-1
CardBus bridge ,V-1
CardBus PC Card ,V-1
D
debug code ,III-114
DXE,II-127
E
EFI,II-127
error code ,III-115
H
HB,V-1
HPB,V-1
HPC,V-1
HPRT,V-2
I
Incompatible PCI device ,V-2
IP,IV-1
IPI,IV-1
J
JEITA,V-2
L
legacy PHPC ,V-2
M
MM,IV-1MM Driver ,IV-1
MM Driver Initialization ,IV-1
MM Driver Runtime ,IV-1
MM Entry Point ,IV-1
MM handler ,IV-1
MMI,IV-1
MMI Source. ,IV-1
MMST,IV-1
MP,II-127
MTRR,IV-2
MWI,V-2
P
PC Card,V-2
PC Card Standard ,V-2
PCI bus,V-2
PCI bus driver ,V-2
PCI configuration space ,V-2
PCI controller ,V-2
PCI device ,V-2
PCI enumeration ,V-2
PCI function ,V-3
PCI host bridge ,V-3
PCI root bridge ,V-3
PCI segment ,V-3
PCI-to-CardBus bridges ,V-3
PEC,V-3
PEIM,V-3
PERR,V-3
PHPC,V-3
PPI,V-3
progress code ,III-115
R
RB,V-3
resource padding ,V-3
root HPC ,V-3
root PCI bus ,V-4
RSM,IV-2
S
SERR,V-4
V-281UEFI Platform Initialization Specification, Release 1.8
SHPC,V-4
SMBus,V-4
SMBus host controller ,V-4
SMBus master device ,V-4
SMBus PPI ,V-4
SMBus slave device ,V-4
status code ,III-115
status code driver ,III-115
U
UDID,V-4
Index V-282 
AMD Secure Encrypted Virtual-
ization (AMD-SEV) Guide
AMD's Secure Encrypted Virtualization (SEV) allows the memory of virtu-
al machines to be encrypted. This is a new feature for Linux's built-in Ker-
nel-based Virtual Machine (KVM) hypervisor. The intention is to increase
system security, especially when using persistent memory.
This document aims to provide a basic understanding of how SEV works,
how to enable and configure it, and some of the limitations and restrictions
that its use causes as compared to non-encrypted virtualization.
Publication Date: January 25, 2024
Contents
1 Introducing SEV 2
2 VM Host Requirements 2
3 VM Requirements 3
4 VM Conﬁguration 3
5 Current Limitations 7
6 For More Information 7
7 GNU Free Documentation License 7
1 AMD Secure Encrypted Virtualization (AMD-SEV) Guide1Introducing SEV
Encryption of computer data stored on disk is a widely-deployed feature. However, data in RAM
is stored in the clear. This can leave that data vulnerable to software or hardware probing by
intruders into the host system. New persistent-memory technology makes this problem more
acute, since an NVDIMM (non-volatile memory module) could be physically removed from a
system and the data on it will remain intact, like to that on a hard drive or SSD. Without en-
cryption, any stored information - such as sensitive data, passwords, or secret keys - could easily
be compromised.
AMD's SEV (Secure Encrypted Virtualization) is a technology to protect Linux KVM virtual ma-
chines by transparently encrypting the memory of each VM with a unique key. SEV can also
calculate a signature of the memory contents, which can be sent to the VM's owner as an attes-
tation that the memory was encrypted correctly by the rmware. SEV is especially relevant to
cloud computing environments, where VMs are hosted on remote servers which are not under
the control of the VMs' owners, since it can reduce the amount of trust VMs need to place in the
hypervisor and administrator of their host system.
In SUSE Linux Enterprise 12 SP4 and above, and a forthcoming maintenance release of SUSE
Linux Enterprise 15, the kernel, QEMU, and libvirt  support the creation and management
of VMs using SEV.
2VM Host Requirements
The VM host hardware must support AMD's SEV technology. To detect if the host hardware
supports SEV, check that the sev attribute is present in the capabilities of libvirt  and that
its value is set appropriately:
<domainCapabilities>
   ...
   <features>
   ...
   <sev supported='yes'/>
   ...
   </sev>
   </features>
</domainCapabilities>
Additionally, ensure that the kvm_amd  kernel module has the sev parameter enabled:
/sys/module/kvm_amd/parameters/sev = 1
2 AMD Secure Encrypted Virtualization (AMD-SEV) Guide3VM Requirements
The VM must be the modern Q35 machine type and must use UEFI rmware.
Note
The Q35 machine type does not have an IDE controller and does not support IDE disks.
All virtio  devices need to be configured with the iommu='on'  attribute in their <driver>
configuration. In addition, all memory regions used by the VM must be locked for Direct Memory
Access (DMA) and to prevent swapping.
4VM Conﬁguration
EXAMPLE 1:  SAMPLE CONFIGURATION FILE
As an example, an SEV-encrypted VM configured with 4 GB of memory would contain the
following XML configuration:
<domain type='kvm'>
    <memory unit='KiB'>4194304</memory>
    <currentMemory unit='KiB'>4194304</currentMemory>
    <os>
    <type arch='x86_64' machine='pc-q35-2.11'>hvm</type>
    <loader readonly='yes' type='pflash'>/usr/share/qemu/ovmf-x86_64-ms-4m-
code.bin</loader>
    <nvram>/var/lib/libvirt/qemu/nvram/sles15-sev-guest_VARS.fd</nvram>
    <boot dev='hd'/>
    </os>
    <launchSecurity 1 type='sev'>
    <cbitpos>47</cbitpos> 2
    <reducedPhysBits>1</reducedPhysBits> 3
    <policy>0x0033</policy> 4
    </launchSecurity>
    <memtune>
    <hard_limit unit='KiB'>4718592</hard_limit> 
    ...
    </memtune>
    <devices>
    <disk type='file' device='disk'>
    <driver iommu='on' name='qemu' type='raw'/>
3 AMD Secure Encrypted Virtualization (AMD-SEV) Guide    <target dev='vda' bus='virtio'/>
    <source file='/vmimages/sev-guest-disk.raw'/>
    </disk>
    <rng model='virtio'>
    <driver iommu='on'/>
    ...
    </rng>
    <memballoon model='virtio'>
    <driver iommu='on' /> 5
    ...
    </memballoon>
    <video>
    <model type='qxl' ram='65536' vram='65536' vgamem='16384' heads='1'
 primary='yes'/>
    </video>
    ...
    </devices>
    ...
    </domain>
1The launchSecurity type='sev'  element and its contents enable encryption of
the VM's memory contents.
2When memory encryption is enabled, one of the physical address bits (also known
as the "C-bit") is used to mark if a memory page is protected. The required cbitpos
element provides the location of the C-bit in a guest page table entry. For example, the
value 47 indicates that bit position 47 in a page table entry will determine whether
that page is encrypted or not. The C-bit number is read from the host's CPUID and is
thus hardware-dependent. The value of cbitpos  is hypervisor-dependent, and can
be obtained through the sev element in the capabilities of the domain.
3When memory encryption is enabled, we lose certain bits of the physical address
space. The required reducedPhysBits  element provides this physical address bit
reduction. Similarly to cbitpos , the value of reducedPhysBits  is processor-fami-
ly-dependent and can be obtained through the sev element in the domain capabil-
ities.
4The required policy  element provides the guest policy which must be maintained
by the SEV rmware. This policy is enforced by the rmware, and restricts what con-
figuration and operational commands can be performed on the VM by the hypervisor.
The guest policy provided when starting the VM is bound to that VM and cannot be
changed throughout its lifetime.
4 AMD Secure Encrypted Virtualization (AMD-SEV) Guide5In addition to the launchSecurity  settings, SEV-encrypted VMs must have the iom-
mu='on'  attribute set in each virtio  device. This attribute is required in order to
enable DMA APIs for the device within QEMU.
The guest policy is four unsigned bytes with the following definition:
TABLE 1:  GUEST POLICY DEFINITIONS
Bit(s) Definition
0 If set, debugging of the guest is disallowed
1 If set, sharing keys with other guests is disallowed
2 If set, SEV-ES is required
3 If set, sending the guest to another platform is disallowed
4 If set, the guest must not be transmitted to another platform that is not in
the domain
5 If set, the guest must not be transmitted to another platform that is not
SEV-capable
6-15 Reserved
16-32 The guest must not be transmitted to another platform with a lower
rmware version
The optional dhCert  element provides the guest owner's base64-encoded Die-Hellman (DH)
key. The key is used to negotiate a master secret key between the SEV rmware and guest owner.
This master secret key is then used to establish a trusted channel between the SEV rmware
and guest owner.
The optional session  element provides the guest owner's base64-encoded session blob, as de-
fined in the SEV API specification. See the LAUNCH_START section of the SEV specification for
the session-blob format.
SEV-encrypted VMs must also have all of their memory regions locked to allow DMA and prevent
swapping. This includes not only the VM's RAM, but also ROM(s), pash, and video memory.
Using the example configuration, the memory regions needing to be locked total to 4352592

the domain
5 AMD Secure Encrypted Virtualization (AMD-SEV) GuidekB, which exceeds the default memlock  limit. The memlock  limit for a virtual machine process
can be increased using the hard_limit  subelement of memtune . The value 4352592 kB was
determined using the following formula:
hard_limit = VM RAM + VM video memory + ROMs/ACPI tables
where:
    4096 kB (UEFI ROM)
   +  4096 kB (UEFI variable store)
   +   128 kB (PC ROM)
   +   128 kB (ISA BIOS) 
   +  2384 kB (ACPI tables)
   = 10832 kB (total of all ROMs/ACPI tables)
Although 10832 kB for ROMs and ACPI tables should be sufficient in most cases, we recommend
adding a few hundred kilobytes of padding. ROM sizes have been known to change and adding
some padding here will accommodate that. Using the virtual machine RAM and video memory
values from the example configuration:
  4194304 kB (virtual machine RAM) 
   +   65536 kB (qlx RAM) 
   +   65536 kB (qlx video RAM) 
   +   16384 kB (qlx VGA memory)
   +   10832 kB (ROMs/ACPI tables)
   = 4352592 kB hard_limit
Calculating the memlock  limit and setting it via hard_limit  can be avoided by configuring
the virtual machine to use hugepages . For more information on using hugepages with VMs,
refer to the Virtualization Best Practices Guide , Chapter "Configuring the VM Host Server and the
VM Guest to use Huge Pages": https://documentation.suse.com/sles/html/SLES-all/article-vt-best-
practices.html#sec-vt-best-mem-huge-pages .
Whilst the overhead incurred is no different to that required for non-SEV VMs, it is much more
important to get the hard limit right when pinning memory. If the limit is too low, the VM will
get killed.
6 AMD Secure Encrypted Virtualization (AMD-SEV) Guide5Current Limitations
The guest operating system running inside an SEV-encrypted VM must contain SEV sup-
port. Currently, SUSE Linux Enterprise Server 12 SP4 and SUSE Linux Enterprise Server
15 provide this.
Any operations that involve saving and restoring the memory and state of an instance
are currently not supported. This means that SEV-encrypted VMs cannot be resumed from
snapshots, and live migration is not possible. Encrypted VMs can be shutdown and restarted
on another host as normal.
SEV-encrypted VMs cannot contain directly-accessible host devices (that is, PCI
passthrough).
These limitations will be removed in the future as the hardware, rmware, and various layers
of software receive new features.
6For More Information
https://developer.amd.com/sev  — AMD-SEV landing page
https://developer.amd.com/wp-content/resources/55766.PDF  — AMD SEV-KM API Spec-
ification (PDF)
https://github.com/AMDESE/AMDSEV/  — AMD SEV GitHub repository containing exam-
ples and tools
https://libvirt.org/formatdomain.html#sev  — libvirt SEV configuration settings
http://events17.linuxfoundation.org/sites/events/ﬁles/slides/AMD%20SEV-ES.pdf  — Slides
from the 2017 Linux Security Summit describing SEV and preliminary performance results
(PDF)
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9 AMD Secure Encrypted Virtualization (AMD-SEV) Guide9. TERMINATION
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ADDENDUM: How to use this License for your documents
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or any later version published by the Free Software Foundation;
with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts.
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10 AMD Secure Encrypted Virtualization (AMD-SEV) GuideGeneral overview of AMD SEV-SNP and Intel TDX
Kevin Kollenda
ABSTRACT
Trusted execution environments (TEEs) have become increasingly
common for the execution of security critical code. AMD SEV-SNP
and Intel TDX are new hardware extensions developed to provide
trusted execution for virtual machines. By providing additional
integrity guarantees and building upon previous secure extensions,
they enable confidential computing in cloud environments with-
out risking sensitive user data. This work presents the additional
components and processes which are used to accomplish these
substantial security gains.
KEYWORDS
trusted computing, amd sev-snp, intel tdx, secure nested paging
1 INTRODUCTION
Today, software companies are increasingly moving their applica-
tions to cloud environments instead of hosting them on-premises.
This may pose a risk to confidential user data, as cloud service
providers (CSP) have direct access to the hardware running poten-
tially security critical applications. TEEs provide a way to safely
execute code without the risk of sensitive data being disclosed to
nefarious actors and were previously created using Intel SGX. How-
ever, SGX works by partitioning an application into a trusted part
secured by an enclave and an untrusted part being run normally.
This degrades the development experience, as developers need to be
aware of the security model and split their applications accordingly,
whereas securing a VM requires no adjustments to application code.
To prevent information leakages and protect confidential data,
the need for virtual machines (VM) with locked down access from
hypervisors emerged. AMD and Intel now iterate on their previous
trusted computing CPU extensions, AMD SEV-ES [ 4] and Intel SGX
[17], to improve virtual machine integrity guarantees and minimize
the trusted computing base (TCB). Cloud service users (CSU) are
able to safely rely on applications running in cloud environments,
leveraging the capabilities introduced by these new extensions.
AMD SEV-SNP (Secure Nested Paging) [2] and Intel Trust Domain
Extensions (TDX) [17] are two hardware based CPU extensions that
aim to increase the confidentiality and integrity of in-memory vir-
tual machine data. They build upon earlier extensions (e.g. Intel
SGX, AMD SEV-SEM), which could not provide sufficient integrity
guarantees. These guarantees are implemented by allowing VMs
to restrict write access to their memory pages and cryptograph-
ically verifying the output of security critical CPU instructions
likeCPUID . Additionally, virtual machines can now trust that the
firmware versions reported by security critical components match
the actually running version, which is essential to prevent rollback
attacks making use of fixed issues.
Similar to their predecessor extensions AMD SEV-ES and Intel
SGX, AMD SEV-SNP and Intel TDX provide remote attestation
capabilities [ 24]. Generated attestation reports include the VM’s
state and custom data provided by the VM (e.g. a public key used
for verification) [ 2] [17], allowing CSUs to confirm that their VM
launched and executed correctly.While AMD SEV-SNP is already available for every AMD EPYC
7003 series processor released since March 2021 [ 22], Intel TDX is
not available for any current generation processors. Linux kernel
support for both AMD SEV-SNP and Intel TDX was introduced
with version 5.19 of July 2022 [ 13] and share some of the newly
added code due to the architectural similarity.
2 BACKGROUND
In this section, previous VM extensions and their functionalities
are explained. Additionally, the process of how memory is accessed
on a modern system is outlined, due to its importance for memory
integrity.
2.1 History of virtual machine CPU extensions
Previously multiple CPU extensions were developed by AMD and
Intel to support more reliable and better performing virtual ma-
chines. This includes AMD-V Nested Paging (NP) [1] and Intel Ex-
tended Page Table (EPT) [15], which replaced slow software-based

page virtualization with hardware accelerated nested paging.
Increased confidentiality guarantees were made possible by AMD
Secure Memory Encryption (SME) [11] to provide memory encryp-
tion for general purpose computing and AMD Secure Encrypted
Virtualization (SEV) [11] which brought SME to virtual machines
accelerated by AMD-V Nested Paging. The required memory en-
cryption keys are handled by an integrated low power AMD Secure
(Co-)Processor (AMD SP) [ 11], as to further decrease the amount of
trusted components. There is currently no hardware assisted VM
memory encryption available for Intel processors, but it is covered
in the upcoming Intel TDX extensions. While SGX could be used
in virtual machines to secure virtualized applications (vSGX), it is
not ideal as several VM features are unavailable once you enable it
for a guest (e.g. VM suspend/resume, snapshots, ...)[ 27] [9]. AMD
also iterated on their AMD SEV extensions by introducing AMD
SEV-ES (Encrypted State), which encrypts the virtual machine’s
register state when the VM terminates [ 4]. As AMD SEV-ES already
provides integrity guarantees for the VM’s register contents no
additional hardware support was required regarding the VM’s state
in AMD SEV-SNP.
Current generation processors will provide a (malicious) virtual
machine manager (VMM) with the encrypted contents of guest’s
memory (by relying on SEV), but they do not prevent write ac-
cesses on VM pages. This enables the aforementioned malicious
hypervisor to corrupt the VM’s state and poses the risk for various
replay attacks. Replay attacks are a type of attack vector, where the
malicious actor retrieves ciphertext at a given moment and replaces
the unprotected memory with this data at a later point in time.
2.2 CPU capability self-reports and security
sensitive registers
Modern processors provide various ways for a running system to
gather information about the current CPU. This is mainly done
by calling the CPUID instructions, which reports the hardware ex-
tensions available to the CPU, register sizes, and several otherKevin Kollenda
configuration details. While emulating and adjusting the output
of this instruction is often performed by a VMM to ease VM mi-
grations and to limit a VM’s features, this can also be abused by a
malicious hypervisor. Although such interferences will only lead
to a denial-of-service for the guest in most cases, it may also re-
sult in a buffer overflow when wrong values are reported for the
extended save area included in x86. [ 2]. Model-specific-registers
(MSR) are various control registers used by a processor to provide
hardware debugging capabilities, performance monitoring/tracing
data and additional information about available CPU features [ 21].
Unrestricted access to these registers is possible by the hypervisor,
enabling potentially unwanted interventions in the VM’s execution,
such as forcing a debug breakpoint to interrupt the guest’s control
flow. Similarly, the CPU microcode patch level and firmware ver-
sions of CPU components used by hardware extensions can also
be queried from software. If a trust domain (TD) cannot rely that
security critical hardware components are running a certain prede-
termined version, there is no guarantee that previously resolved
issues and bugs found in those aforementioned components aren’t
exploited.
2.3 Threat model
The threat model that earlier CPU extensions (e.g. AMD SEV and
AMD SEV-ES) relied on includes more components that need to be
trusted. This is caused by the lack of memory integrity guarantees,
which enable a malicious entity to tamper with the VM’s mem-
ory. As SEV-SNP and TDX prevent this, every component which
would previously considered to be trusted due to its ability to write
into VM memory (e.g. Hypervisor, Direct Memory Access (DMA)
capable PCI devices) can now safely be assumed to be untrusted.
2.4 Paging
In typical x86_64 systems memory is accessed using pages. Paging
is used to emulate a full virtual address space for each process, with-
out requiring that much memory to be available on the computer
[25]. It is also typically used for page-level memory protection,
providing each process with its own set of pages. Thus user space
processes cannot read and write to pages belonging to a different
process or the system kernel. Paging capabilities are handled by
the Memory Management Unit (MMU), which translates the virtual
addresses used by applications to their underlying real physical
addresses available to the hardware. Addresses are mapped to pages
by splitting them up in different parts. Typically the most signif-
icant bits correspond to the page directory entry, the following
bits indicate the page table entry and the remaining bits contain
the offset within the page and various flags set by the operating
system (e.g. read/write/execute enable). AMD SEV provides guest
virtual machines to selectively protect and encrypt memory pages
using a VM specific encryption key [ 11], restricting read access
from outside sources (like the VMM). Similar memory encryption
is guaranteed on a per application basis by Intel SGX [10].
3 ARCHITECTURE
Several hardware technologies are leveraged by SEV-SNP and TDX
to provide a more secure TEE for VMs. How this is achieved and
which components are involved in this process are described below.3.1 Security critical components
The architectural improvements enabled by SEV-SNP and TDX are
achieved by the introduction of newly created CPU integrated com-
ponents and modules. While AMD’s implementation of SEV-SNP
relies on a CPU inbuilt secure processor to provide a safe environ-
ment for VMs [ 2], Intel TDX uses a multi-component architecture
[17] consisting of the following items:
•Intel TDX Module offering a safe way to manage TDs while
enforcing various security policies
•Intel Authenticated Code Module required for loading and
verifying the TDX module in protected memory
•TD Quoting enclave (TDQE) created using Intel SGX for
remote attestation
Those components offer the management interface needed by
the hypervisor to create and configure VMs and are in charge of
intercepting any attacks targeted at VMs protected by either SEV-
SNP or TDX. Communication with AMD’s SP is facilitated using
a novel VM management API interface [ 6], while Intel relies on
additional CPU instructions [ 18]. Data structures used by these
components are inaccessible by external actors, e.g. software run-
ning on the system or DMA enabled devices, due to their security
critical purpose. These data structures contain management infor-
mation as required by the CPU’s integrated secure modules. Such
data structures include the encrypted virtual machine save area
(VMSA) as provided by SEV-SNP or the virtual machine control
structure (VMCS) issued for each TD by the VMMs using TDX.
3.2 Memory integrity protection
Memory integrity projection marks one of the major improvements
introduced in AMD SEV-SNP and Intel TDX. Both SEV-SNP and
TDX establish a split between shared (unencrypted) and private
(encrypted) memory pages. Whether a page is considered shared
or private is indicated by the most significant bit of the virtual
address and verified in the page table walk. Shared pages may
still be encrypted with a key belonging to the hypervisor [ 17], but
should be considered untrusted from the VM’s point of view. Private
(guest) pages are always encrypted using a VM specific key, making
the memory contents unreadable for outside observers [2] [17].
3.2.1 AMD SEV-SNP
The key principle of AMD SEV-SNP’s integrity improvements is
guaranteeing a VM, which has allocated private memory pages,
that it will always read back the last memory value that it wrote
into such pages. SEV-SNP not only guarantees this behaviour for
regular memory reads and writes, but also when memory pages
are swapped to persistent storage or the whole virtual machine
is migrated to another host [ 2]. Thus replay attacks relying on
replacing VM memory with previously read ciphertexts and denial
of service attacks that corrupt VM memory by writing unrelated
data to its pages, are no longer possible.
This is realized by adding a reverse map table (RMP) data struc-
ture shared across the system, which keeps track of the owner for
each page that can be assigned to a VM. In the case of a RMP entry
belonging to a page owned by a SNP enabled VM, it also saves the
guest’s physical address (gPA) that the page should be mapped to.
Additionally, each RMP entry contains a validation bit, which isGeneral overview of AMD SEV-SNP and Intel TDX
Figure 1: Nested VM PTW on AMD SEV-SNP enabled systems.
cleared before a page is created for a VM [ 2]. Whenever a memory
write access to a SNP-VM’s page is performed, either by the VMM
or a VM itself, a RMP check is performed to ensure that only the
entity who owns that page can modify it. Memory read accesses
from external actors, e.g. the virtual machine manager or other
guests, do not need to be validated using the RMP, as the memory

of private pages is always encrypted using the VM’s specific private
key.
The hypervisor’s table walk is unaffected by the RMP, as long
as the accessed page does not belong to a SEV-SNP enabled guest.
If a malicious hypervisor tries to overwrite the memory contents
of such a page, the table walk will result in a page fault ( #PF) and
the addressed page is unaffected. RMP checks are performed at
the end of the regular page table walk (PTW), and its entries are
indexed using the system’s physical address. The changed table
walk is the same as in Figure 1, however the first page translation
is not necessary as there is no guest involved.
For SEV-SNP enabled virtual machines the page table walk is
more complex. Using the accelerated nested page table walk pro-
vided by AMD-V, the initial address translation from a guest virtual
address (gVA) to the guest’s physical address and finally to the host
systems physical address (sPA) is performed [ 1]. Afterwards the
RMP check is invoked, which verifies that the page:
•belongs to a VM and not the hypervisor.
•is owned by the specific guest that initiated the table walk.
•mapped at the correct gPA.
This modified version of the PTW with the additional nested page
table walk is visualized in Figure 1. Further information on page
table states can be found in the appendix section A.
Page re-mapping attacks are prevented by these memory in-
tegrity guarantees, if a guest properly validates its private pages. To
ensure that these integrity violations are not possible and caught by
RMP checks, the guest must ensure that any gPA is only validated
once. Achieving this can be done by performing all page valida-
tion on VM launch or by the guest keeping track of all previously
verified gPAs. If this injective property between gPAs and sPAs
holds true, any malicious nested page table change initiated by
a compromised hypervisor will lead to the guest receiving a VM
communication ( #VC) exception when trying to access a remapped
gPA (as RMPUPDATE clears the validation). Guests should treat #VC
Figure 2: Page table walk on Intel TDX enabled systems.
exceptions with great care, since it is a sign of an attack taking
place. Typically the guest then tries to performs any necessary
steps required to protect itself from a malicious VMM or terminates
completely. [2]
3.2.2 Intel TDX
Intel TDX enables similar memory related integrity capabilities
as AMD SEV-SNP. The CPU’s inbuilt TDX Module provides an
interface for the hypervisor to manage VMs indirectly and offers
new instructions, VMLAUNCH-VMX andVMRESUME , for starting and
resuming a VM. Instead of keeping track of the owner for each
memory page on a system wide basis, TDX relies on keeping one
shared extended page table for the hypervisor and multiple private
extended page tables for each virtual machine (called TD by Intel)
[18]. Due to these inherent architectural differences, the PTW initi-
ated from inside a TD works quite differently to the one used by
SEV-SNP. As can be observed in Figure 2, systems incorporating
TDX resolve gVAs by choosing the appropriate EPT for a given
address.
Initialization of the private EPT is handled by the Intel TDX mod-
ule, which transforms VMM provided memory pages into private
pages required by the TD. Integrity protection for pages is offered
analogous to SEV-SNP. However, instead of relying on the guest to
validate its private pages itself, Intel TDX tracks that the mapping
of pages to their associated gPAs is unique inside a TD and addition-
ally across TD boundaries, to avoid any memory aliasing related
vulnerabilities [ 18]. Differentiating between shared and private
memory is realized by including a 1-bit TD identifier for each cache
line and optionally a 28-bit message authentication code (MAC)
that includes the 1-bit identifier to ensure that any unauthorized
changes to the memory are detected. If an attacker were to write
to pages protected by the TDX module, a MAC-verification-failure
would occur the next time the TD tries to read from the affected
memory. If logical-integrity-mode without a crpytographic MAC
is used, such read accesses will instead result in a TD-ownership
check failure. Contrary to AMD’s implementation, the guest has no
impact on the way these failures would be handled and they will
be terminated by the TDX module. The VMM or other VMs are not
affected by the forceful termination of a guest due to one of these
integrity violations.Kevin Kollenda
3.3 Privilege levels and access control
AMD SEV-SNP and Intel TDX rely on different kinds of privilege
levels for their integrity guarantees.
3.3.1 AMD SEV-SNP’s privilege concept
As hypervisor operations modifying the state or memory of SEV-
SNP enabled VM’s are no longer permitted by default, the SP needs
to assess these requests. Such operations may include standard VM
managing commands, e.g. launching and resuming or suspending
and terminating a VM, which were previously handled completely
by the hypervisor [ 6]. Remote attestation and quoting is also per-
formed by the SP, using the appropriate keys for the VM that the
attestation process has been initiated for.
Apart from moving security sensitive operations to the secure
processor, SEV-SNP also supports four additional optional virtual
machine privilege levels (VMPLs). They are numbered from VMPL0
to VMPL3, with VMPL0 indicating the highest and VMPL3 the
least access rights. These can be used to further divide the newly
gained access controls provided by the RMP, for example to enable
hardware assisted address space isolation inside a SEV-SNP enabled
guest. Each virtual CPU (vCPU) assigned to a guest runs within one
VMPL, where each VMPL can only grant permissions equivalent
to the ones it currently possesses. This is done by invoking the
RMPADJUST instruction, which updates the necessary RMP entries
accordingly. Initial page validation using PVALIDATE only grants
full read, write and execute rights to VMPL0. The restrictive nature
of page table permission checks performed during the nested table
walk imply that multiple page permissions need to be equivalent
for a page to be accessible by a guest. Page permission validation
is therefore handled in both the guest-managed page table and
the hypervisor-managed nested page table provided by AMD-V,
also additionally through the RMP table managed by the higher
privileged VMPL. [2] [5]
Utilizing this finer-grained access control made available by these
different VMPLs allows SEV-SNP guests to create a more restrictive
emulation environment. APIC virtualization, which was previously
handled by the hypervisor, could be performed by software run-
ning in VMPL0 and passing through the results to lower privileged
VMPLs running inside the guest. Further tasks can be delegated
to an intermediate layer executing with the highest privilege level,
such as handling #VC exceptions which occurred in other vCPUs,
thus providing additional abilities to support SEV-SNP unaware
software inside a guest. Combining all those features made avail-
able by VMPLs, it is possible to nest legacy (non SEV-SNP) VMs
inside a SEV-SNP guest containing intermediate code in VMPL0.
Although there is a slight performance decrease due to the addi-
tional emulation performed by this translation, it can enable legacy
workloads to run securely. [ 2] An architectural overview of this is
outlined in Figure 3.
3.3.2 Intel TDX components required for access control
Due to the multi-component architecture used by Intel TDX, there
are more steps involved for VM management and communication.
The Intel TDX module is hosted in an environment protected by
the CPU’s Secure-Arbitration Mode (SEAM), allocating as much
reserved memory as is configured in the SEAM-range-register
(SEAMRR). Confidentiality and integrity guarantees for SEAM
Figure 3: Nested virtualization as enabled by optional VMPLs.
memory are enforced similar to Intel TDX secured VMs. Mem-
ory accesses from any external actor, e.g. all software (regardless
of whether it is run inside a VM or the VMM) or DMA capable
devices, are prohibited [ 17]. The CPU in SEAM mode is not fully
privileged though, as it is not permitted to access other secured
memory regions, such as those used by Intel SGX enclaves or the
CPU’s system-management mode.
Installation and loading of this TDX module is performed by
the newly introduced SEAM Loader (SEAMLDR), an additional
authenticated code module (ACM) integrated into Intel’s Trusted
Execution Technology (TXT) stack. It is responsible for verifying
and subsequently loading the Intel TDX module into the aforemen-
tioned SEAM memory range (SEAMMR), after being invoked by the
VMM [ 18]. Additionally, the SEAMLDR passes the security-version
number (SVN) through hardware-measurement registers inside
the SEAMMR and places the TDX module into SEAM-VMX root
mode. Following this initialization process, the VMM can commu-
nicate and give control over to the TDX module by executing the

SEAMCALL instruction. The SEAMRET instruction is used by the TDX
module to return execution to the hypervisor, ensuing the requested
operation (e.g. creation, deletion or launching of a TD). Starting or
resuming a virtual machine is accomplished using VMLAUNCH and
VMRESUME instructions, which move the TDX module into SEAM-
VMX non-root operation before passing control over to the TD
[18].
In contrast to AMD’s singular module architecture, remote at-
testation is handled by a separate SGX TDQE [18].
3.4 Secure capability reports
As mentioned in subsection 2.2, there are several issues with a VMM
being able to control the information provided by CPUID or read
from MSRs using RDMSR [21]. SEV-SNP and TDX seek to prevent
a hypervisor from supplying VMs with incorrect CPU capability
information as retrieved using one of the instructions mentioned
above.
SEV-SNP enabled guests may instruct the AMD SP to verify that
theCPUID data passed through by the hypervisor does not contain
capabilities unavailable on the host and that safety critical size
information is correct. This filtering may either be performed on-
the-fly whenever CPUID is called or during the initial VM launch.
When this should be handled on launch, two special pages are
inserted into the guest’s memory by the SP. One page contains theGeneral overview of AMD SEV-SNP and Intel TDX
encryption keys used for the communication between guest and SP,
while the other holds the verified CPUID values. The former page
is securely encrypted by the guest’s private memory encryption
key to prevent any unwanted accesses by the VMM [ 6]. As the
verification process is only done once on VM launch and not every
time CPUID is invoked, it is the better performing solution [2].
On guests using Intel TDX CPUID validation is done by default
and does not need to be explicitly configured. Analogous to SEV-
SNP the TDX module prevents the VMM from reporting greater
capabilities than the host system actually supports. However, TDX
guests can enable a virtualization exception unconditionally being
thrown whenever CPUID is executed, allowing the VM’s operating
system (OS) to fully control how software inside the VM receives
the requested CPUID information [18].
SEV-SNP and TDX both prevent interference with guest’s MSRs,
e.g. hardware debugging registers, by prohibiting the VMM’s ability
to write into these security sensitive registers [ 18]. This is handled
automatically, without requiring any modifications to the guest’s
OS.
3.5 TCB rollback prevention
Rollback attacks rely on downgrading the version of components
included in the trusted computing base (TCB) or maliciously report-
ing an older version of the component and subsequently exploiting
bugs, which were already fixed in recent versions.
On SEV-SNP systems the SP ensures that its firmware may not be
downgraded below the currently running version [ 6]. Additionally,
the firmware version of each TCB component, such as the SP, is
cryptographically merged with the Chip Endorsment Key (CEK)
fused into the processor [ 2]. Due to these improvements, guest
owners can now reliably trust that their VMs will not launch with
a misreported firmware version lower than the minimum version
threshold they have set beforehand.
A TCB managed by a TDX module is only considered to be
up-to-date if each component included in the TCB reports a SVN
higher than a threshold set by the component’s author [ 17]. These
SVNs are loaded from hardware registers into memory managed
by the SEAM Loader, which is inaccessible for anyone but the TDX
module, keeping it safe from manipulations of external actors. Thus
any downgrade of such a module below this previously set version
can result in the TCB losing it’s up-to-date status. If a VM’s launch
policy does require a modern TCB version without it being present,
the VM will not launch. [19]
3.6 Interrupt and exception injection
Injecting interrupts and exceptions is traditionally possible at all
times by the hypervisor. Generally, this does not lead to problems for
VMs, as all major VM operating systems support proper interrupt
and exception handling. Some of these VM OSs contain in-built
presumptions about how and when interrupts and exceptions can
occur, caused by the fact that VMs typically try to emulate bare-
metal hardware as close as possible. A guest OS may assume that
no unknown opcode exceptions ( #UD) are thrown after executing
a valid instruction, as is the case for real hardware. However, they
could be injected by the VMM at any time. [2]Preventing yet to be discovered issues in the handling of such
uncommon events in operating systems, AMD SEV-SNP provides
two optionally configurable modes, which guests can enable to re-
strict the commonly unprotected interrupt and exception interface
[4]. Alternate injection provides the default virtualized interrupt
injection and queuing interfaces as they are typically used by the
hypervisor, but only allow them to be called from within the VM it-
self. This prevents a malicious hypervisor from interfering with the
guest’s OS altogether, because the fields used to save the interrupt
information are only accessible by other entities that can already
work with the guest’s data. Similar to how nested virtualization
is realized using VMPL0 as an intermediate layer, as described in
subsection 3.3.1, interrupt and exception handling can be facilitated
by software running with VMPL0 privileges. However, guests may
not want to fully block the hypervisor from injecting interrupts
and exceptions, therefore SEV-SNP provides an additional inter-
face called restricted injection. Guests that have enabled this mode
prevent virtual interrupt queuing from the VMM altogether and
heavily limit which interrupts can be injected. Instead of neces-
sary interrupts being passed through to the VM directly, a newly
introduced exception called hypervisor injected exception ( #HV )
[5] notifies the guest of the VMM’s interrupt. Communicating ex-
tended information required by the VM to handle this event can be
passed between the hypervisor and the guest using shared memory
pages [2].
Intel TDX similarly keeps track of virtual interrupt information
and APIC data inside the virtual machines control structures, pro-
tected from the hypervisor. Pages used for saving this information
are provided on TD launch using the VM’s associated private key.
Intel VM-X was adjusted to prevent the delivery of exceptions into
trust domains as virtual interrupts and injected interrupts are man-
aged by CPU hardware [ 18]. Ensuring assumptions made by the
VM’s OS about interrupt prioritization and masks is also handled
by TD’s virtual interrupt virtualization. All of these guarantees
are provided without requiring any modifications to the guest’s
operating system [17].
3.7 Remote attestation
Remote attestation is an essential feature required by CSUs as they
want to verify that their deployed VMs are running as the CSU
intended them to and were not tampered with [ 24]. Attestation
reports are generated by the CPU in-built components, e.g. the SP
on AMD systems or the TDQE on Intel hosts, containing various
information (collected after launch and during runtime) about the
VM itself. Previous extensions only allowed for the attestation to
be performed after a trusted execution environment was launched,
but SEV-SNP and TDX also enable runtime attestation.
The attestation process is always initiated by the guest. SEV-
SNP VMs ask the SP to generate the report for them by using the
SNP_GUEST_REQUEST firmware API call [ 6], while TDX guests in-
voke the TDCALL instruction of the TDX module. SEV-SNP guests
only need to communicate with the SP and no other entities to
process the attestation. This differs on TDX TDs, which would
start by asking the TDX module for a general attestation report
and subsequently requesting the VMM to quote it using the TDQE.
The quoting enclave cannot be used by the TDX module directly,Kevin Kollenda
Figure 4: Remote attestation process for SEV-SNP guests
adapted from AMD SEV-SNP whitepaper [2].
because it is running inside a SGX enclave, inaccessible to SEAM.
Typically the information includes metadata collected during the
VM’s launch, general system information, versions of security sen-
sitive components (such as the TDX module or the SP’s firmware)
and arbitrary data provided by the TD [ 6] [2] [17]. On SEV-SNP
enabled systems, the guest’s owner can additionally issue a signed
identity block (IDB) after launch to differentiate between guests
and validate the boot using a provided checksum. TDX attestation
reports also include fields identifying the TD’s owner inside the
TDINFO_STRUCT created during the attestation process [ 18]. The ar-
bitrary data filled by the VM is often used to provide the other party
with the VM’s public key to communicate in a secure manner. CSUs
can trust that the attestation report was generated properly, as the
version for each component involved in the attestation and the

status of security sensitive CPU features (e.g. simultaneous multi-
threading, SEM) is included [ 6]. The report is signed using either
the versioned chip endorsement key (VCEK) that is unique for each
AMD chip performing the SEV-SNP attestation or by relying on
the signing key provided by the provisioning certification enclave
(PCE) for Intel TDX guests [ 18]. Afterwards such reports can be
verified by the party that requested the attestation by validating the
report using company provided signatures. The process required
to generate and transfer an attestation report is outlined in Figure
4 for SEV-SNP guests.
Due to the TDX’s multi component architecture described above,
there are more steps required for successful transfer of the attes-
tation report as detailed in Figure 5. Initially, the TDX VM tasks
the TDX module with generating the attestation report (Figure 5.1),
analagous to how a SEV-SNP guest requests the report from the
SP. Using this newly created report (Figure 5.2) the TD passes it
upwards to the hypervisor for the signing process (Figure 5.3). The
VMM relays the attestation data to the TDQE (Figure 5.4), respon-
sible for the cryptographic verification of the report. Subsequently
the signed information is passed back down to the hypervisor (Fig-
ure 5.5) and to the trust domain (Figure 5.6), which finally delivers
the report back to the remote party [17] [18].
3.8 VM Migration and sealing
As trust domains may want to save data across VM executions,
means to securely write data to persistent storage are part of SEV-
SNP and TDX. SEV-SNP guests can simply ask the SP to generate
Figure 5: Remote attestation process for TDX guests adapted
from Intel TDX whitepaper [ 17] and Intel TDX architecture
specification [18].
local sealing keys, which the VM can trust to not have been tam-
pered with by a malicious actor [ 2] and use to encrypt data that is
not protected by SEV-SNP’s memory guarantees.
SEV-SNP introduces a new CPU component called the migration
agent (MA) to perform guest migrations. This agent runs inside
a SEV-SNP VM on the same host and is responsible for verifying
that a migration can be performed securely. As the agent is active
on a per-system basis, it needs to run on both the source physical
machine that the guest should be transferred away from and on the
destination machine that it should be migrated to. TDX does also
confidential VM migration using a specific service trust domain
called the migration TD (MigTD), which handles the process in
a secure fashion similar to AMD’s MA [ 20]. Nearly all modern
CSPs support the migration of (running) VM’s, to ease maintenance
efforts and to allow for dynamic load balancing. Live migration is
managed by the agents running on both systems, which handle
the re-encryption of data moved from source to destination [ 6].
Guests need to ensure that their resting data, e.g. data not being in
memory, is encrypted by other means like full disk encryption, as
neither TDX nor SEV-SNP handles the protection of such data.
4 RELATED WORK
While the introduced integrity guarantees provided by SEV-SNP
solve multiple issues discovered in the predecessor SEV-ES exten-
sions, new attack vectors have emerged targeting SEV-SNP systems.
Fault injection vulnerabilities attacking the SP can be exploited to
extract SEV-SNP secrets and decrypt memory assumed to be pri-
vate. As this severely impacts the remote attestation process, it
cannot be relied on for secure report creation on current generation
AMD processors [ 8]. Additional side channel attacks are possible,
because SEV-SNP does not prevent read access to (encrypted) VM
private pages, which can be used to leak guest register values or
recover secret keys [ 23]. There are currently no known vulnera-
bilities targeting Intel TDX, as no implementing hardware exists
yet.
High demand for running applications in a TEE without the need
to modify them also lead to the creation of Gramine and SecureGeneral overview of AMD SEV-SNP and Intel TDX
CONtainer Environment (SCONE). Both provide a secure environ-
ment by relying on SGX enclaves, making use of the confidentiality
guarantees. Gramine is a library OS which can encapsulate an appli-
cation, while keeping a low memory footprint [ 26] and handling all
OS functionality that the application might require. SCONE allows
for applications to be run inside a secure Docker container and
keeps the TCB small by providing a C library [7].
IBM is working on providing comparable integrity guarantees,
as ensured by SEV-SNP and TDX, for Power ISA based comput-
ers using a VM-based TEE called protected execution facility. It
is supported in IBM POWER9 chips available since 2017 and in-
creases access control restrictions and relies on several existing
technologies, as it leverages secure boot and a trusted platform
module [14].
5 CONCLUSION
SEV-SNP and TDX build on the memory confidentiality guarantees
offered by SEV-SEM and SGX by enforcing additional integrity
assurances. The switch to running applications in VM based TEEs
is driven by the reduced development efforts, as no adjustments
to application code are required. These new technologies allow
secure processing of sensitive user data on systems administrated
by external actors and mark an important milestone in the ongoing
push towards trusted execution environments in the cloud.
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com/v1/dl/getContent/733579
[17] Intel. 2021. White Paper: Intel Trust Domain Extensions. https://cdrdv2.intel.
com/v1/dl/getContent/690419
[18] Intel. 2022. Architecture Specification: Intel ®Trust Domain Extensions (Intel ®
TDX) Module. https://cdrdv2.intel.com/v1/dl/getContent/733568

[19] Intel. 2022. Device Attestation Model in Confidental Computing Environment.
https://cdrdv2.intel.com/v1/dl/getContent/742533
[20] Intel. 2022. Guest Hypervisor Communication Interface (GHCI) for Intel Trust
Domain Extensions (Intel TDX) 1.5. https://cdrdv2.intel.com/v1/dl/getContent/
726792
[21] Intel. 2022. Intel ®64 and IA-32 Architecture Software Developer’s Manual
Volume 4: Model-Specific Registers. https://www.intel.com/content/www/us/
en/develop/download/intel-64-and-ia-32-architectures-software-developers-
manual-volume-4-model-specific-registers.html
[22] David Kaplan. 2017. Protecting VM register state with SEV-ES. https://www.
amd.com/system/files/documents/amd-epyc-7003-series-datasheet.pdf
[23] Mengyuan Li, Luca Wilke, Jan Wichelmann, Thomas Eisenbarth, Radu Teodor-
escu, and Yinqian Zhang. 2022. A Systematic Look at Ciphertext Side Channels
on AMD SEV-SNP. In 2022 IEEE Symposium on Security and Privacy (SP) . 337–351.
https://doi.org/10.1109/SP46214.2022.9833768
[24] Jämes Mé nétrey, Christian Göttel, Anum Khurshid, Marcelo Pasin, Pascal Felber,
Valerio Schiavoni, and Shahid Raza. 2022. Attestation Mechanisms for Trusted
Execution Environments Demystified. In Distributed Applications and Interoper-
able Systems . Springer International Publishing. https://doi.org/10.1007/978-3-
031-16092-9_7
[25] Timothy Merrifield and H Reza Taheri. 2016. Performance implications of
extended page tables on virtualized x86 processors. In Proceedings of the12th ACM
SIGPLAN/SIGOPS International Conference on Virtual Execution Environments .
https://dl.acm.org/doi/abs/10.1145/2892242.2892258
[26] Chia-Che Tsai, Kumar Saurabh Arora, Nehal Bandi, Bhushan Jain, William
Jannen, Jitin John, Harry A. Kalodner, Vrushali Kulkarni, Daniela Oliveira, and
Donald E. Porter. 2014. Cooperation and Security Isolation of Library OSes for
Multi-Process Applications (EuroSys ’14) . Association for Computing Machinery,
New York, NY, USA, Article 9, 14 pages. https://doi.org/10.1145/2592798.2592812
[27] VMware. 2021. vSGX Overview . Retrieved 16 December, 2022
from https://docs.vmware.com/en/VMware-vSphere/7.0/com.vmware.vsphere.
security.doc/GUID-EF552A5E-744B-4FD4-85AB-07B3CB22EF3E.html
A PAGE TABLE STATES
All pages tracked in the RMP are categorized using a page state
attribute. Pages can only be in one of the following states shown in
Table 1.
Pages in the Hypervisor state correspond to the aforementioned
shared (unencrypted) pages, which can be freely accessed by the
VMM or by SEV-SNP VMs. Guest-Valid pages are assigned to a
SEV-SNP VM and were successfully validated by the guest and are
thus marked as private pages. Transitioning between the different
states is possible by calling new CPU instructions, e.g. PVALIDATE
orRMPUPDATE , or by using the VM management API included in the
AMD secure processor [ 2].PVALIDATE is used within guests to move
pages from the Guest-Invalid to the Guest-Valid state, verifying them
in the process. This is typically done by the guest after receiving
pages assigned using the RMPUPDATE instruction, as it clears the
validated bit, marking the page as untrusted. Assigning pages from
the hypervisor to a SEV-SNP enabled guest or from a guest back to
the VMM can be done using the previously mentioned RMPUPDATE
instruction. Modifying the RMP directly from software is forbidden
by design and is only possible by the AMD Secure Processor, as it
is essential for memory access control [6].Kevin Kollenda
State Description
Hypervisor Default state for unassigned memory
Guest-Invalid Unvalidated page assigned to guest
Guest-Valid Page validated by guest
Pre-Guest Page owned by AMD-SP before guest assignment
Pre-Swap Used to prepare page swap
Firmware Used for pages not yet configured by AMD-SP
Metadata Metadata necessary for page swap
Context Used by AMD-SP to hold VM metadata
Table 1: Table adapted from AMD SEV-SNP whitepaper [2]
Moving a page into the Metadata ,Firmware orContext state
requires calling into the AMD SP’s management API, which makes
the page immutable and configures it to the requested state.
B DEVELOPMENT EXPERIENCE
To develop software making use of these newly introduced capabil-
ities, as provided by SEV-SNP and TDX, requires a stable functionand instruction specification and hardware supporting these exten-
sions. While AMD already offers processors with enabled SEV-SNP
support, Intel still lacks any hardware support in their current gen-
eration chips. However, they have already issued an application
binary interface (ABI) for TDX [ 16], enabling developers to start
the software development process. AMD exposes API access to the
SP using a rust library, which supports SEV-SNP since October 2022
[12]. Making use of these libraries and tools allows the creation of
VM’s and communication with the necessary secure components.
Certificates for validating attestation reports are issued by the chip
maker and are publicly available for each chip generation.
Performance may decrease due to the new components used
during the page table walk, as they perform additional access veri-
fication for memory writes to guest private pages. The real world
impact has not yet been measured, as the very recent and ongo-
ing development efforts by AMD and Intel are still affecting the
implementation details. Previously discussed CPU measurement in-
structions, such as CPUID , are also getting slower due to additional
validation efforts provided by the SP and TDX module.
Received 9 January 2023  
 
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Secure Encrypted Virtualization API  
Version 0.24  55766  Rev. 3.24 April 2020   
 
4 Contents   
 
Contents  
Chapter 1  Overview  ................................ ................................ ................................ ................  19 
1.1 Operational Model ................................ ................................ ................................ ...........  19 
1.2 Platform Management  ................................ ................................ ................................ ..... 19 
1.2.1  Platform Lifecycle  ................................ ................................ ................................ ... 19 
1.2.2  Identity  ................................ ................................ ................................ ....................  20 
1.2.3  Device Authenticity  ................................ ................................ ................................ . 20 
1.2.4  Ownership  ................................ ................................ ................................ ...............  20 
1.2.5  Encrypted St ate ................................ ................................ ................................ ....... 21 
1.3 Guest Lifecycle  ................................ ................................ ................................ ...............  21 
1.3.1  Launch  ................................ ................................ ................................ .....................  21 
1.3.2  Activate and Deactivate  ................................ ................................ ..........................  22 
1.3.3  Snapshot and Migrate  ................................ ................................ ..............................  23 
1.3.4  Decommission  ................................ ................................ ................................ .........  23 
1.3.5  Debugging  ................................ ................................ ................................ ...............  24 
Chapter 2  Key Management  ................................ ................................ ................................ ... 25 
2.1 Keys  ................................ ................................ ................................ ................................ . 25 
2.1.1  Platform Diffie -Hellman Key  ................................ ................................ ..................  25 
2.1.2  Platform Endorsement Key  ................................ ................................ .....................  26 
2.1.3  Chip Endorsement Key  ................................ ................................ ...........................  26 
2.1.4  AMD Signing Key  ................................ ................................ ................................ .. 26 
2.1.5  Owner Certificate Authority Signing Key  ................................ ..............................  26 
2.1.6  AMD Root Key  ................................ ................................ ................................ ....... 27

2.1.6  AMD Root Key  ................................ ................................ ................................ ....... 27 
2.1.7  Transport Integrity Key  ................................ ................................ ...........................  27 
2.1.8  Transport Encryption Key  ................................ ................................ .......................  27 
2.1.9  Key Encryption Key  ................................ ................................ ................................  27 
2.1.10  Key Integrity Key  ................................ ................................ ................................ .... 28 
2.1.11  VM Encryption Key  ................................ ................................ ................................  28 
2.2 Usage  ................................ ................................ ................................ ...............................  28 
2.2.1  Key Derivation Fun ction  ................................ ................................ .........................  28   
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2.2.2  Master Secret Derivation  ................................ ................................ .........................  28 
2.2.3  Transport Key Establishment  ................................ ................................ ...................  29 
2.2.4  Data Protection ................................ ................................ ................................ .........  29 
Chapter 3  Guest Policy  ................................ ................................ ................................ ............  31 
Chapter 4  Mailbox Register Protocol  ................................ ................................ .....................  32 
4.1 Mailbox Mode  ................................ ................................ ................................ ..................  32 
4.1.1  Mailboxes  ................................ ................................ ................................ .................  32 
4.2 Ring Buffer Mo de ................................ ................................ ................................ ............  33 
4.3 Command Buffer  ................................ ................................ ................................ .............  37 
4.4 Command Identifiers  ................................ ................................ ................................ ....... 37 
4.5 Status Codes  ................................ ................................ ................................ .....................  39 
4.6 Endianness  ................................ ................................ ................................ .......................  40 
4.7 Synchrony  ................................ ................................ ................................ ........................  40 
4.8 Address Validation  ................................ ................................ ................................ ..........  40 
Chapter 5  Platform Management API  ................................ ................................ ...................  42 
5.1 Overview  ................................ ................................ ................................ ..........................  42 
5.1.1  Platform Conte xt ................................ ................................ ................................ ...... 42 
5.1.2  Platform State Machine ................................ ................................ ............................  43 
5.1.3  Authenticity ................................ ................................ ................................ ..............  43 
5.1.4  Ownershi p ................................ ................................ ................................ ................  43 
5.1.5  Non-volatile Storage  ................................ ................................ ................................  44 
5.1.6  Power State Transitions  ................................ ................................ ...........................  44 
5.1.7  SEV -ES Trusted Memory Region  ................................ ................................ ...........  44 
5.2 INIT  ................................ ................................ ................................ ................................ . 45 
5.2.1  Actions  ................................ ................................ ................................ .....................  45 
5.2.2  Parameters  ................................ ................................ ................................ ................  45 
5.2.3  Status Codes  ................................ ................................ ................................ .............  46 
5.3 INIT_EX  ................................ ................................ ................................ ..........................  46 
5.3.1  Actions  ................................ ................................ ................................ .....................  46 
5.3.2  Parameters  ................................ ................................ ................................ ................  47 
5.3.3  Status Codes  ................................ ................................ ................................ .............  48   
 
6 Contents   
 
5.4 SHUTDOWN  ................................ ................................ ................................ ..................  48 
5.4.1  Actions  ................................ ................................ ................................ ....................  48 
5.4.2  Parameters  ................................ ................................ ................................ ...............  49 
5.4.3  Status Codes  ................................ ................................ ................................ ............  49 
5.5 PLATFORM_RESET  ................................ ................................ ................................ ..... 49 
5.5.1  Actions  ................................ ................................ ................................ ....................  49 
5.5.2  Parameters  ................................ ................................ ................................ ...............  49 
5.5.3  Status Codes  ................................ ................................ ................................ ............  49 
5.6 PLATFORM_STATUS  ................................ ................................ ................................ .. 50 
5.6.1  Actions  ................................ ................................ ................................ ....................  50 
5.6.2  Parameters  ................................ ................................ ................................ ...............  50 
5.6.3  Status Codes  ................................ ................................ ................................ ............  51 
5.7 PEK_GEN  ................................ ................................ ................................ .......................  51 
5.7.1  Actions  ................................ ................................ ................................ ....................  51 
5.7.2  Parameters  ................................ ................................ ................................ ...............  52 
5.7.3  Status Codes  ................................ ................................ ................................ ............  52 
5.8 PEK_CSR  ................................ ................................ ................................ ........................  52 
5.8.1  Actions  ................................ ................................ ................................ ....................  53 
5.8.2  Parameters  ................................ ................................ ................................ ...............  53 
5.8.3  Status Codes  ................................ ................................ ................................ ............  53 
5.9 PEK_CERT_IMPORT  ................................ ................................ ................................ .... 54 
5.9.1  Actions  ................................ ................................ ................................ ....................  54 
5.9.2  Parameters  ................................ ................................ ................................ ...............  54 
5.9.3  Status Codes  ................................ ................................ ................................ ............  55 
5.10  PDH_GEN  ................................ ................................ ................................ .......................  55 
5.10.1  Actions  ................................ ................................ ................................ ....................  55

5.10.1  Actions  ................................ ................................ ................................ ....................  55 
5.10.2  Parameters  ................................ ................................ ................................ ...............  56 
5.10.3  Status Codes  ................................ ................................ ................................ ............  56 
5.11  PDH_CERT_EXPORT  ................................ ................................ ................................ ... 56 
5.11.1  Actio ns ................................ ................................ ................................ ....................  56 
5.11.2  Parameters  ................................ ................................ ................................ ...............  57   
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5.11.3  Status Codes  ................................ ................................ ................................ .............  57 
5.12  DOWNLOAD_FIRMWARE  ................................ ................................ ..........................  58 
5.12.1  Actions  ................................ ................................ ................................ .....................  58 
5.12.2  Parameters  ................................ ................................ ................................ ................  58 
5.12.3  Status Codes  ................................ ................................ ................................ .............  59 
5.13  GET_ID  ................................ ................................ ................................ ...........................  59 
5.13.1  Actions  ................................ ................................ ................................ .....................  59 
5.13.2  Parameters  ................................ ................................ ................................ ................  59 
5.13.3  Status Codes  ................................ ................................ ................................ .............  60 
5.14  NOP  ................................ ................................ ................................ ................................ . 60 
5.14.1  Actions  ................................ ................................ ................................ .....................  60 
5.14.2  Parameters  ................................ ................................ ................................ ................  60 
5.14.3  Status Codes  ................................ ................................ ................................ .............  60 
5.15  RING_BUFFER  ................................ ................................ ................................ ...............  61 
5.15.1  Actions  ................................ ................................ ................................ .....................  61 
5.15.2  Parameters  ................................ ................................ ................................ ................  61 
5.15.3  Status Codes  ................................ ................................ ................................ .............  62 
Chapter 6  Guest Management API  ................................ ................................ ........................  63 
6.1 Overview  ................................ ................................ ................................ ..........................  63 
6.1.1  Guest Context ................................ ................................ ................................ ...........  63 
6.1.2  Activation and Deactivation  ................................ ................................ ....................  64 
6.2 LAUNCH_START  ................................ ................................ ................................ ..........  64 
6.2.1  Actions  ................................ ................................ ................................ .....................  65 
6.2.2  Parameters  ................................ ................................ ................................ ................  66 
6.2.3  Status Codes  ................................ ................................ ................................ .............  66 
6.3 LAUNCH_UPD ATE_DATA  ................................ ................................ ..........................  67 
6.3.1  Actions  ................................ ................................ ................................ .....................  67 
6.3.2  Parameters  ................................ ................................ ................................ ................  67 
6.3.3  Status Codes  ................................ ................................ ................................ .............  68 
6.4 LAUNCH_UPDATE_VMSA  ................................ ................................ .........................  68 
6.4.1  Actions  ................................ ................................ ................................ .....................  68   
 
8 Contents   
 
6.4.2  Parameters  ................................ ................................ ................................ ...............  69 
6.4.3  Status Codes  ................................ ................................ ................................ ............  69 
6.5 LAUNCH_MEA SURE  ................................ ................................ ................................ ... 70 
6.5.1  Actions  ................................ ................................ ................................ ....................  70 
6.5.2  Parameters  ................................ ................................ ................................ ...............  70 
6.5.3  Status Codes  ................................ ................................ ................................ ............  71 
6.6 LAUNCH_SECRET  ................................ ................................ ................................ ....... 71 
6.6.1  Actions  ................................ ................................ ................................ ....................  71 
6.6.2  Parameters  ................................ ................................ ................................ ...............  72 
6.6.3  Status Codes  ................................ ................................ ................................ ............  73 
6.7 LAUNCH_FIN ISH ................................ ................................ ................................ .........  73 
6.7.1  Actions  ................................ ................................ ................................ ....................  73 
6.7.2  Parameters  ................................ ................................ ................................ ...............  74 
6.7.3  Status Codes  ................................ ................................ ................................ ............  74 
6.8 ATTESTATON  ................................ ................................ ................................ ...............  74 
6.8.1  Actions  ................................ ................................ ................................ ....................  74 
6.8.2  Parameters  ................................ ................................ ................................ ...............  75 
6.8.3  Status Codes  ................................ ................................ ................................ ............  75 
6.9 SEND_START  ................................ ................................ ................................ ................  76 
6.9.1  Actions  ................................ ................................ ................................ ....................  76 
6.9.2  Parameters  ................................ ................................ ................................ ...............  77 
6.9.3  Status Codes  ................................ ................................ ................................ ............  79 
6.10  SEND_UPDATE_DATA ................................ ................................ ................................  79 
6.10.1  Actions  ................................ ................................ ................................ ....................  79 
6.10.2  Parameters  ................................ ................................ ................................ ...............  80 
6.10.3  Status Codes  ................................ ................................ ................................ ............  81 
6.11  SEND_UPDA TE_VMSA  ................................ ................................ ...............................  82

6.11  SEND_UPDA TE_VMSA  ................................ ................................ ...............................  82 
6.11.1  Actions  ................................ ................................ ................................ ....................  82 
6.11.2  Parameters  ................................ ................................ ................................ ...............  83 
6.11.3  Status Codes  ................................ ................................ ................................ ............  84 
6.12  SEND_FINISH ................................ ................................ ................................ ................  84   
 
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6.12.1  Actions  ................................ ................................ ................................ .....................  84 
6.12.2  Parameters  ................................ ................................ ................................ ................  85 
6.12.3  Status Codes  ................................ ................................ ................................ .............  85 
6.13  SEND_CANC EL ................................ ................................ ................................ .............  85 
6.13.1  Actions  ................................ ................................ ................................ .....................  85 
6.13.2  Parameters  ................................ ................................ ................................ ................  86 
6.13.3  Status Codes  ................................ ................................ ................................ .............  86 
6.14  RECEIVE_START  ................................ ................................ ................................ ..........  86 
6.14.1  Actions  ................................ ................................ ................................ .....................  86 
6.14.2  Parameters  ................................ ................................ ................................ ................  87 
6.14.3  Status Codes  ................................ ................................ ................................ .............  88 
6.15  RECEIVE_U PDATE_DATA  ................................ ................................ ..........................  89 
6.15.1  Actions  ................................ ................................ ................................ .....................  89 
6.15.2  Parameters  ................................ ................................ ................................ ................  90 
6.15.3  Status Codes  ................................ ................................ ................................ .............  90 
6.16  RECEIVE_UPDATE_VMSA  ................................ ................................ .........................  91 
6.16.1  Actions  ................................ ................................ ................................ .....................  91 
6.16.2  Parameters  ................................ ................................ ................................ ................  92 
6.16.3  Status Codes  ................................ ................................ ................................ .............  92 
6.17  RECEIVE_F INISH  ................................ ................................ ................................ ..........  93 
6.17.1  Actions  ................................ ................................ ................................ .....................  93 
6.17.2  Parameters  ................................ ................................ ................................ ................  94 
6.17.3  Status Codes  ................................ ................................ ................................ .............  94 
6.18  GUEST_STATUS  ................................ ................................ ................................ ...........  94 
6.18.1  Actions  ................................ ................................ ................................ .....................  94 
6.18.2  Parameters  ................................ ................................ ................................ ................  95 
6.18.3  Status Codes  ................................ ................................ ................................ .............  95 
6.19  ACTIVATE  ................................ ................................ ................................ .....................  95 
6.19.1  Actions  ................................ ................................ ................................ .....................  95 
6.19.2  Parameters  ................................ ................................ ................................ ................  96 
6.19.3  Status Codes  ................................ ................................ ................................ .............  96   
 
10 Contents   
 
6.20  ACTIVATE_EX ................................ ................................ ................................ ..............  97 
6.20.1  Actions  ................................ ................................ ................................ ....................  97 
6.20.2  Parameters  ................................ ................................ ................................ ...............  98 
6.20.3  Status Codes  ................................ ................................ ................................ ............  98 
6.21  DEACTIVATE ................................ ................................ ................................ ................  99 
6.21.1  Actions  ................................ ................................ ................................ ....................  99 
6.21.2  Parameters  ................................ ................................ ................................ ...............  99 
6.21.3  Status Codes  ................................ ................................ ................................ ............  99 
6.22  DF_FLUSH  ................................ ................................ ................................ ...................  100 
6.22.1  Actions  ................................ ................................ ................................ ..................  100 
6.22.2  Parameters  ................................ ................................ ................................ .............  100 
6.22.3  Status Codes  ................................ ................................ ................................ ..........  100 
6.23  DECOMMISSION  ................................ ................................ ................................ ........  101 
6.23.1  Actions  ................................ ................................ ................................ ..................  101 
6.23.2  Parameters  ................................ ................................ ................................ .............  101 
6.23.3  Status Codes  ................................ ................................ ................................ ..........  101 
6.24  COPY  ................................ ................................ ................................ ............................  102 
6.24.1  Actions  ................................ ................................ ................................ ..................  102 
6.24.2  Parameters  ................................ ................................ ................................ .............  102 
6.24.3  Status Codes  ................................ ................................ ................................ ..........  102 
6.25  SWAP_OUT ................................ ................................ ................................ ..................  103 
6.25.1  Actions  ................................ ................................ ................................ ..................  103 
6.25.2  Parameters  ................................ ................................ ................................ .............  104 
6.25.3  Status Codes  ................................ ................................ ................................ ..........  105 
6.26  SWAP_IN ................................ ................................ ................................ ......................  105 
6.26.1  Actions  ................................ ................................ ................................ ..................  106 
6.26.2  Parameters  ................................ ................................ ................................ .............  107 
6.26.3  Status Codes  ................................ ................................ ................................ ..........  107

6.26.3  Status Codes  ................................ ................................ ................................ ..........  107 
Chapter 7  Debugging API  ................................ ................................ ................................ ..... 109 
7.1 DBG_DECRYPT  ................................ ................................ ................................ ..........  109 
7.1.1  Actions  ................................ ................................ ................................ ..................  109   
 
 Contents  11 
 
7.1.2  Parameters  ................................ ................................ ................................ ..............  109 
7.1.3  Status Codes  ................................ ................................ ................................ ...........  110 
7.2 DBG_ENCRYPT  ................................ ................................ ................................ ...........  110 
7.2.1  Actions  ................................ ................................ ................................ ...................  110 
7.2.2  Parameters  ................................ ................................ ................................ ..............  111 
7.2.3  Status Codes  ................................ ................................ ................................ ...........  111 
Appendix A  Usage Flows  ................................ ................................ ................................ ..........  112 
Appendix B  AMD Certificate Authority Certificates  ................................ ............................  116 
B.1 Certificate Format  ................................ ................................ ................................ ..........  116 
B.2 Certificate Signature  ................................ ................................ ................................ ...... 117 
B.3 Certificate Validation  ................................ ................................ ................................ ..... 117 
Appendix C  SEV Certificates  ................................ ................................ ................................ ... 118 
C.1 Certificate Format  ................................ ................................ ................................ ..........  118 
C.2 Elliptic Curve Enumeration  ................................ ................................ ...........................  119 
C.3 Public Key Formats  ................................ ................................ ................................ ....... 120 
C.3.1  RSA Public Key  ................................ ................................ ................................ ..... 120 
C.3.2  ECDSA Public Key ................................ ................................ ................................  120 
C.3.3  ECDH Public Key  ................................ ................................ ................................ .. 120 
C.4 Signature Formats  ................................ ................................ ................................ ..........  121 
C.4.1  RSA Signature  ................................ ................................ ................................ ....... 121 
C.4.2  ECDSA Signature  ................................ ................................ ................................ .. 121 
C.5 Certificate Validation  ................................ ................................ ................................ ..... 121 
   
Versio n 0.24  55766  Rev. 3.24 April 2020   
 
12 List of Tables   
 
List of Tables  
Table 1. Summary of Keys  ................................ ................................ ................................ ..............  25 
Table 2. Guest Policy Structure  ................................ ................................ ................................ ....... 31 
Table 3. CmdResp Register Layout  ................................ ................................ ................................  32 
Table 4. CmdBufAddr_Hi Register Layout  ................................ ................................ ....................  32 
Table 5. CmdBufAddr_Lo Register Layout  ................................ ................................ ....................  32 
Table 6. CmdPtr Entry Layout  ................................ ................................ ................................ ........  34 
Table 7. Command Flags Values  ................................ ................................ ................................ .... 34 
Table 8. StatVal Entry Layout  ................................ ................................ ................................ .........  34 
Table 9. RBCtl Register Layout  ................................ ................................ ................................ ...... 35 
Table 10. RBTail Register Layout  ................................ ................................ ................................ .. 35 
Table 11. RBHead Register Layout  ................................ ................................ ................................  35 
Table 12. Ring Buffer Mode Error Recovery Handshake Sequence  ................................ ..............  37 
Table 13. Command Identifiers  ................................ ................................ ................................ ....... 37 
Table 14. Status Codes  ................................ ................................ ................................ ....................  39 
Table 15. Platform Context (PCTX) Fields  ................................ ................................ ....................  42 
Table 16. PSTATE Finite State Machine  ................................ ................................ ........................  43 
Table 17. Power Management Transitions  ................................ ................................ ......................  44 
Table 18. INIT Command Buffer  ................................ ................................ ................................ .... 45 
Table 19. INIT Command Status Codes  ................................ ................................ .........................  46 
Table 20. INIT_EX Command Buffer  ................................ ................................ ............................  47 
Table 21. INIT_EX Command Status Codes.  ................................ ................................ .................  48 
Table 22. SHUTDOWN Command Status Codes  ................................ ................................ ..........  49 
Table 23. PLATFORM_RESET Command Status Codes  ................................ ..............................  50 
Table 24. PLATFORM_STATUS Command Buffer  ................................ ................................ ..... 50 
Table 25. PLATFORM_STATUS Command Status Codes  ................................ ...........................  51 
Table 26. PEK_GEN Command Status Codes  ................................ ................................ ................  52 
Table 27. PEK_CSR Command Buffer  ................................ ................................ ...........................  53 
Table 28. PEK_CSR Command Status Codes  ................................ ................................ ................  53 
Table 29. PEK_CERT_IMPORT Command Buffer  ................................ ................................ ....... 54   
 
 List of Tables  13 
 
Table 30. PEK_CERT_IMPORT Command Status Codes  ................................ .............................  55 
Table 31. PDH_GEN Command Status Codes  ................................ ................................ ................  56 
Table 32. PDH_CERT_EXPORT Command Buffer  ................................ ................................ ....... 57 
Table 33. PDH_CERT_EXPORT Certificates Buffer  ................................ ................................ ..... 57 
Table 34. PDH_CERT_EXPORT Command Status Codes  ................................ ............................  57 
Table 35. DOWNLOAD_FIRMWARE Command Buffer  ................................ .............................  58 
Table 36. DOWNLOAD_FIRMWARE Command Status Codes  ................................ ...................  59 
Table 37. GET_ID Command Buffer  ................................ ................................ ..............................  59 
Table 38. GET_ID Command Status Codes  ................................ ................................ ....................  60 
Table 39: NOP Status Codes ................................ ................................ ................................ ............  60 
Table 40. RING_BUFFER Command Buffer  ................................ ................................ .................  61

Table 40. RING_BUFFER Command Buffer  ................................ ................................ .................  61 
Table 41. RING_BUFFER Status Codes  ................................ ................................ .........................  62 
Table 42. Guest Context (GCTX) Fields  ................................ ................................ .........................  63 
Table 43. GSTATE Finite State Machine  ................................ ................................ ........................  63 
Table 44. LAUNCH_START Command Buffer  ................................ ................................ .............  66 
Table 45. LAUNCH_START Session Data Buffer  ................................ ................................ .........  66 
Table 46. LAUNCH_START Status Codes  ................................ ................................ ....................  66 
Table 47. LAUNCH_UPDATE_DATA Command Buffer  ................................ .............................  67 
Table 48. LAUNCH_UPDATE_DATA Status Codes  ................................ ................................ .... 68 
Table 49. LAUNCH_UPDATE_VMSA Command Buffer  ................................ ............................  69 
Table 50. LAUNCH_UPDATE_VMSA Status Codes  ................................ ................................ .... 69 
Table 51. LAUNCH_MEASURE Command Buffer  ................................ ................................ ....... 70 
Table 52. LAUNCH_MEASURE Measurement Buffer  ................................ ................................ . 71 
Table 53. LAUNCH_MEASURE Status Codes  ................................ ................................ ..............  71 
Table 54. LAUNCH_SECRET Command Buffer  ................................ ................................ ...........  72 
Table 55. LAUNCH_SECRET Packet Header Buffer  ................................ ................................ .... 72 
Table 56. LAUNCH_SECRET Status Codes  ................................ ................................ ..................  73 
Table 57. LAUNCH_FINISH Command Buffer  ................................ ................................ .............  74 
Table 58. LAUNCH_FINISH Status Codes  ................................ ................................ ....................  74 
Table 59. ATTESTATION Command Buffer  ................................ ................................ .................  75 
Table 60. Attestation Report Buffer ................................ ................................ ................................ . 75   
 
14 List of Tables   
 
Table 61. ATTESATION Status Codes  ................................ ................................ ..........................  76 
Table 62. SEND_START Command Buffer  ................................ ................................ ...................  77 
Table 63. SEND_START Platform Certificates Buffer  ................................ ................................ .. 78 
Table 64. SEND_START AMD Certificates Buffer  ................................ ................................ ...... 78 
Table 65. SEND_START Session Data Buffer  ................................ ................................ ..............  79 
Table 66. SEND_START Status Codes  ................................ ................................ ..........................  79 
Table 67. SEND_UPDATE_DATA Command Buffer  ................................ ................................ .. 80 
Table 68. SEND_UPDATE_DATA Packet Header Buffer  ................................ ............................  81 
Table 69. SEND_UPDATE_DATA Status Codes  ................................ ................................ ..........  81 
Table 70. SEND_UPDATE_VMSA Command Buffer  ................................ ................................ .. 83 
Table 71. SEND_UPDATE_VMSA Packet Header Buffer  ................................ ...........................  83 
Table 72. SEND_UPDATE_VMSA Status Codes  ................................ ................................ .........  84 
Table 73. SEND_FINISH Command Buffer  ................................ ................................ ..................  85 
Table 74. SEND_FINISH Status Codes  ................................ ................................ ..........................  85 
Table 75. SEND_CANCEL Command Buffer  ................................ ................................ ...............  86 
Table 76. SEND_CANCEL Status Codes  ................................ ................................ .......................  86 
Table 77. RECEIVE_START Command Buffer  ................................ ................................ ............  87 
Table 78. RECEIVE_START Session Data Buffer  ................................ ................................ ........  88 
Table 79. RECEIVE_START Status Codes  ................................ ................................ ...................  88 
Table 80. RECEIVE_UPDATE_DATA Command Buffer  ................................ ............................  90 
Table 81. RECEIVE_UPDATE_DATA Packet Header Buffer  ................................ .....................  90 
Table 82. RECEIVE_UPDATE_DATA Status Codes  ................................ ................................ ... 91 
Table 83. RECEIVE_UPDATE_VMSA Command Buffer  ................................ ...........................  92 
Table 84. RECEIVE_UPDATE_VMSA Packet Header Buffer  ................................ .....................  92 
Table 85. RECEIVE_UPDATE_VMSA Status Codes  ................................ ................................ ... 93 
Table 86. RECEIVE_FINISH Command Buffer  ................................ ................................ ............  94 
Table 87. RECEIVE_FINISH Status Codes  ................................ ................................ ...................  94 
Table 88. GUEST_STATUS Command Buffer  ................................ ................................ ..............  95 
Table 89. GUEST_STATUS Status Codes  ................................ ................................ .....................  95 
Table 90. ACTIVATE Command Buffer  ................................ ................................ ........................  96 
Table 91. ACTIVATE Status Codes  ................................ ................................ ...............................  96   
 
 List of Tables  15 
 
Table 92. ACTIVATE_EX  Command Buffer  ................................ ................................ .................  98 
Table 93. ACTIVATE_EX  Status Codes  ................................ ................................ ........................  98 
Table 94. DEACTIVATE Command Buffer  ................................ ................................ ...................  99 
Table 95. DEACTIVATE Status Codes  ................................ ................................ ..........................  99 
Table 96. DF_FLUSH Command Status Codes  ................................ ................................ ............  100 
Table 97. DECOMMISSION Command Buffer  ................................ ................................ ...........  101 
Table 98. DECOMMISSION Status Codes  ................................ ................................ ...................  101 
Table 99. COPY Command Buffer  ................................ ................................ ................................  102 
Table 100. COPY Status Codes  ................................ ................................ ................................ ..... 103 
Table 101. SWAP_OUT Command Buffer  ................................ ................................ ...................  104 
Table 102. SWAP_OUT & SWAP_IN Metadata Entry  ................................ ................................  105 
Table 103. SWAP_OUT Status Codes  ................................ ................................ ..........................  105 
Table 104. SWAP_IN Command Buffer  ................................ ................................ .......................  107 
Table 105. SWAP_IN Status Codes  ................................ ................................ ..............................  107 
Table 106. DBG_DECRYPT Command Buffer  ................................ ................................ ............  109 
Table 107. DBG_DECRYPT Status Codes  ................................ ................................ ...................  110 
Table 108. DBG_ENCRYPT Command Buffer  ................................ ................................ ............  111 
Table 109. DBG_ENCRYPT Status Codes  ................................ ................................ ...................  111

Table 109. DBG_ENCRYPT Status Codes  ................................ ................................ ...................  111 
Table 110. AMD Signing Key Certificate Format ................................ ................................ .........  116 
Table 111. Key Usage Encoding  ................................ ................................ ................................ ... 116 
Table 112. SEV Certificate Format  ................................ ................................ ...............................  118 
Table 113. USAGE Enumeration (All other encodings are reserved)  ................................ ...........  118 
Table 114. ALGO Enumeration (All o ther encodings are reserved)  ................................ .............  119 
Table 115. CURVE Enumeration (All other encodings are reserved) ................................ ...........  119 
Table 116. RSA Public Key  ................................ ................................ ................................ ...........  120 
Table 117. ECDSA Public Key  ................................ ................................ ................................ ..... 120 
Table 118. ECDH Public Key  ................................ ................................ ................................ ........  120 
Table 119. RSA Signature  ................................ ................................ ................................ .............  121 
Table 120. ECDSA Signature  ................................ ................................ ................................ ........  121 
   
16 Revision History   
 
Revision History  
Date  Revision  Description  
April 2020  3.24 • Change API version to 0.24  
• Add RING_BUFFER command  
April  2020  3.23 • Change API version to 0.2 3 
• Add SWAP_OUT/SWAP_IN commands  
• Add SEND_ CANCEL  command  
• Add NOP  command  
• Add ATTESTATION command  
• DF_FLUSH is valid in any state  
July 2019  3.22 • Change API version to 0.2 2 
• Describe differences between versions of the API  
• Add ACTIVATE_EX command  
• Add INIT_EX command  
• Add Sent Guest state  
October  2018  3.07 • Change API version to 0.17  
• Add COPY  command  
• Improve LAUNCH_MEASURE, LAUNCH_SECRET  
February  2018 3.06 • Change API version to 0.16  
• Added DOWNLOAD_FIRMWARE command.  
• Added GET_ID command.  
• API version doesn’t matter in certificate validation.  
• MNONCE generation and usage in LAUNCH_MEASURE and 
LAUNCH_SECRET.  
• WBINVD required after SEV -ES SHUTDOWN command.  
• Document mailbox register numbers.  
October 2017  3.04 • RECEIVE_START works in PSTATE.INIT as well as 
PSTATE.WORKING.  
• Updated flowchart to emphasize dependency on 
PDH_CERT_EXPORT before LAUNCH_START.  
• Clarification on snapshot constraint.  
• Other minor edits    
 
 Revision History  17 
 
August  2017  3.03 • Move Policy to command buffer in all commands  
• SEND_UPDATE_DATA TRANS_LENGTH parameter is In and 
Out. 
• Document MNONCE generation  
• Insert documentation for RECEIVE_UPDATE_DATA  
• Removed “Key Management” from title  
• Many other m inor edits  
January 2017  3.02 • Split all the *_UPDATE commands into *_UPDATE_DATA 
and *_UPDATE_VMSA  
• Added LAUNCH_SECRET command to allow for secret data to 
be injected into a launched guest. Updated state machine to 
reflect new command.  
• Replaced X.509 certificate usage with API -specific formatted 
certificates.  
• Added clarity around cryptographic algorith ms; Switched from 
ECC curve P -256 to ECC P -384. 
• Addressed industry partner inputs to command buffer structures.  
• General clarifications.  
August 2016  3.01 Bug fixes and minor edits.  
May 2016  3.00 Initial Release  
   
18 References   
 
References  
FIPS 186 -4 Digital Signature Standard (DSS). Federal Information Processing Standards 
Publication 186 -4.  
http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.186 -4.pdf  
FIPS 198 -1 The Keyed -Hash Message Authentication Code (HMAC). Federal Information 
Processing Standards  Publication 198 -1. 
http://csrc.nist.gov/publications/fips/fips198 -1/FIPS -198-1_final.pdf  
SP 800 -38F Recommendation for Block Cipher Modes of Operation: Methods for Key 
Wrapping. NIST Special Publication 800 -38F 
http://nvlpubs.nist.gov/nistpubs/SpecialPub lications/NIST.SP.800 -38F.pdf  
SP 800 -56A Recommendation for Pair -Wise Key Establishment Schemes Using Discrete 
Logarithm Cryptography. NIST Special Publication 800 -56A Revision 2.  
http://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800 -56Ar2.pdf  
SP 800 -108 Recommendation for Key Derivation Using Pseudorandom Functions. NIST 
Special Publication 800 -108. 
http://csrc.nist.gov/publications/nistpubs/800 -108/sp800 -108.pdf  
RFC 3279  Algorithms and Identifiers for the Internet X.509 Public Key Infrastructure 
Certificate and Certificate Revocation List (CRL) Profile. IETF RFC 3279.  
https://www.ietf.org/rfc/rfc3279.txt  
RFC 5480  Elliptic Curve Cryptography Subject Public Key Information. IETF RFC 5480.  
https://www.ietf.org/rfc/rfc5480.txt  
RFC 57 58 Internet X.509 Public Key Infrastructure: Additional Algorithms and Identifiers 
for DSA and ECDSA. IETF RFC 5758.  
https://www.ietf.org/rfc/rfc5758.txt  
 
 Chapter 1  Overview  19 
 
Chapter 1  Overview  
The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual 
machine (VM) to be transparently encrypted with a key unique to the guest virtual mach ine (VM). 
The memory controller contains a high-performance  encryption engine which can be programmed 
with multiple keys for use by different VMs in the system.   The programming and management of 
these keys  and secure data transfer between host hypervisor  and guest VM memory  is handled by 
the SEV firmware running AMD Secure Processor.  The API  available to the host  hypervisor  for 
these operations  is the focus of this document.  
1.1 Operational Model  
The capabilities of the SEV feature can support many operation al environments. It is capable of 
supporting both lightweight virtualized containers as well as conventional virtual machines within 
an enterprise cloud environment. In either case, there are two parties concerned in the deployment 
of SEV guests: the guest  owner and the platform owner.  For example, in a cloud environment, the 
platform owner would be the cloud vendor and the guest owner would be the user that wishes to 
run their workload in the cloud.  
Guest owners wish to protect the confidentiality of the data running within their guests. While 
they trust the platform owner to provide the infrastructure to run their guest, they benefit from 
reducing their risk exposure to vulnerabilities within that infrastructure. The SEV feature encrypts 
the contents of t he memory of the guest and provides assurances that it was encrypted properly. 
The encryption of memory places an additional burden on attackers within the operational 
environment who may have already obtained some illicit access to the guest’s memory thro ugh a 
vulnerability in the hypervisor or other supporting enterprise software.  
Platform owners wish to provide such protection to guest owners, but also must manage the 
computing resources efficiently and effectively. Resource allocation needs to be fluid and their 
customers data must be safely backed up in case of failure. The SEV feature has been developed to 
be sensitive to this requirement; it integrates into the conventional guest lifecycle surrounding 
launching, migration, and snapshotting of guests.  
1.2 Platform Management  
This section describes the management of the platform by the platform owner.  
1.2.1 Platform Lifecycle  
The firmware maintains context  for the platform. To initialize the platform, the INIT command is 
executed to initialize and configure the platform context . The INIT command accepts 
configuration parameters that affect the behavior of the platform until the system is reset or the   
Secure Encryp ted Virtualization API  
 
20 Overview   Chapter 1  
 
SHUTDO WN command is invoked. The SHUTDOWN command clears all platform and guest 
state that exists in non -persistent storage.  
The status of the platform can be queried using the PLATFORM_STATUS command. This 
command provides information about the state of the pl atform.  
If the platform needs to be reset to factory settings, the PLATFORM _RESET command can be 
issued by the hypervisor. This command clears all persistently stored platform state including the 
platform certificates and signing keys (see below).  
1.2.2 Identity  
The firmware identifies itself by an asymmetric signing key generated during the one -time 
configuration steps taken before the platform may be put into production. This key is called the

configuration steps taken before the platform may be put into production. This key is called the 
Platform Endorsement Key (PEK) and is used to sign the Platf orm Diffie -Hellman key (PDH). By 
signing this key, the firmware authenticates the cryptographic contexts built with the PDH.  
The firmware provides interfaces to manage the PDH: PDH_GEN and PDH_CERT_EXPORT. 
The PDH_GEN command generates a new PDH, which is then signed by the PEK. This command 
is not necessary for normal operation; it is provided to support the ability to generate a fresh PDH 
in case the platform owner’s security policies require it.  
The PDH_CERT_EXPORT command exports the PDH and its PEK si gnature. The PEK is signed 
by two keys to connect it to two different roots of trust. These roots of trust provide authenticity 
and ownership proof to third parties, described in the following sections. These signatures are also 
exported via the PDH_CERT_E XPORT command.  
1.2.3 Device Authenticity  
The firmware provides a mechanism to verify that it is executing on AMD hardware that is 
capable of supporting SEV. Each platform contains a chip -unique signing key called the Chip 
Endorsement Key (CEK) .  The CEK is signe d by the AMD SEV Signing Key (ASK), which is 
signed by the AMD root signing key (ARK).   A guest owner or remote platform interacting with 
the firmware can obtain the public component of the AMD signing key s to prove the hardware 
authenticity. The mechanism  to obtain the public key is outside the scope of this document.  
The CEK  signs the PEK. This signature connects the PEK to the A RK, which is a root of trust.  
1.2.4 Ownership  
The firmware also provides interfaces to verify the identity of the owner of the platfo rm on which 
it is executing: PEK_CSR and PEK_CERT_IMPORT.  
PEK_CSR generates a certificate signing request (CSR) for the PEK. This signing request 
contains the PEK public key and other identifying information about the platform. When the 
platform owner’s ce rtificate authority is provided this CSR, it generates a certificate using the   
 
 Chapter 1  Overview  21 
 
public key of the PEK and signs it with its root signing key. This signed certificate connects the 
PEK to the platform owner’s root of trust. It can be used by external parties to verify ownership of 
the platform.  
The platform itself keeps a copy of the PEK certificate in persistent storage. In order to install the 
certificate in the platform, the PEK_CERT_IMPORT command is issued. Once the certificate is 
imported, the platform o wner has taken ownership of the platform.  
1.2.5 Encrypted State  
When a #VMEXIT occurs, the register state of the guest is saved to memory in the VMCB save 
area. Access to this save area exposes the guest register state to manipulation and observation by 
attacke rs. To mitigate this, some SEV capable platforms support the AMD SEV Encrypted State 
(SEV -ES) feature. When enabled, SEV -ES encrypts and integrity protects the VMCB save area 
with the memory encryption key.  
1.3 Guest Lifecycle  
The SEV feature supports the comm on guest lifecycle events so that SEV can integrate well 
within already existing cloud infrastructures. These events include launching, running, 
snapshotting, migrating, and decommissioning guests.  
The status of a guest is available via the GUEST_STATUS co mmand. This command reports the 
current SEV state the guest is in and other information.  
1.3.1 Launch  
When a guest is launched, its memory must first be encrypted before SEV can be enabled in 
hardware for this guest.  The firmware provides interfaces to bootstra p the memory encryption for 
this purpose: the LAUNCH commands . These six commands together generate a fresh memory 
encryption key for the guest, encrypt guest memory, and provide an attestation of the successful 
launch.  
LAUNCH_START is called first to crea te a guest context within the firmware. The hypervisor 
provides the firmware with the guest’s security policy and the public key of the guest owner. The 
guest policy constrains the use and features activated for the lifetime of the launched guest, such 
as disallowing debugging, enabling key sharing, or turning on other SEV -related features. The 
provided public key allows the firmware to establish a cryptographic session with the guest owner 
to negotiate keys used for attestation (see Chapter 2 ). 
The hypervisor loads the guest into memory and begins calling subsequent 
LAUNCH_UPDATE _DATA  commands.  
LAUNCH_UPDATE _DATA  encrypts the memory provided to it by the hypervisor.  It also 
calculates a measurement of the memory. This measurement is a signature of the memory contents   
 
22 Overview   Chapter 1  
 
that can be sent to the guest owner as an attestation that the memory was encrypted correctly by 
the firmware.  
The hypervisor also initializes the VM sa ve area within the VMCB by issuing 
LAUNCH_UPDATE_VMSA. This command encrypts the VM save area. The 
LAUNCH_UPDATE_VMSA command is only used when the SEV -ES feature is enabled.  
Once the guest data and VM save areas are encrypted, the hypervisor issues the 
LAUNCH_MEASURE command to produce a measurement of the data encrypted by the launch 
flow. The guest owner may wait to provide the guest with confidential information until it can 
verify the attestation measurement. Since the guest owner knows the initial con tents of the guest at 
boot, the attestation measurement can be verified by comparing it to what the guest owner expects.  
To provide the guest with secret data after the measurement is validated, the guest owner wraps a 
secret and sends it to the guest through the LAUNCH_SECRET command.  
After completion of the launch workflow, the hypervisor issues LAUNCH_FINISH to ready the 
guest for execution.  
1.3.2 Activate and Deactivate  
AMD -V requires the guest to be associated with an ASID within its VMCB  prior to execut ing a 
VMRUN instruction to run the guest . Additionally, LAUNCH_UPDATE_DATA and 
LAUNCH_UPDATE_VMSA require an active ASID.  An ASID is an identifier associated with all 
memory accesses of the guest. SEV uses ASIDs to associate memory encryption keys with the  
guest. The number of guests  that the firmware supports is conceptually  unlimited  (though resource 
constraints impose a more practical limit .) However, there are only a limited number of ASIDs 
that can be simultaneously associated with keys.  The firmware provides to the hypervisor 
interfaces to overcommit ASIDs to guests using the  ACTIVATE, DEACTIVATE, and 
DF_FLUSH  commands , and the WBINVD instruction.  
The ACTIVATE command allows the hypervisor to inform the firmware that a given guest is 
associated with a n ASID. When this command is issued, the firmware programs the memory 
controller with the guest’s memory encryption key. This key is then associated with the guest’s 
ASID.  
The hypervisor uses the DEACTIVATE command to de -allocate an ASID from a guest. This  
removes the association in the memory controller between the guest and the ASID. A hypervisor 
may wish to re -allocate this ASID due to operating system specific ASID scheduling protocols. It 
may also need to re -allocate ASIDs if there are no SEV -capable A SIDs currently available.  
Before re -activating an ASID, the firmware requires the hypervisor to flush the cache back to 
memory with a WBINVD instruction  on each core . Once WBINVD  completes, the hypervisor 
must call DF_FLUSH to ensure that the data fabric i s completely flushed. The DF_FLUSH  
command checks that a WBINVD has been executed since the last DEACTIVATE. The firmware 
enforces the WBINVD and DF_FLUSH flow to ensure any unencrypted data in the cache and data   
 
 Chapter 1  Overview  23 
 
fabric write buffers associated with the previous key value is written back to memory before the 
key can be changed.   On success, the DF_FLUSH command marks the previously deactivated 
ASIDs as usable. The DF_FLUSH command provides the hypervisor flexibility to batch multiple 
DEACTIVATE calls toge ther and flushing the cache and data fabric only once afterwards.  
1.3.3 Snapshot and Migrate  
Snapshotting and migration both require the memory image of a guest to be removed from the 
system to be reconstituted at another platform later in time. (Note that in th is version of the API, 
the platform reconstituting the image must be known at the time the snapshot is taken.) To protect 
the confidentiality of an SEV protected guest while in transit and storage, its memory image must 
be encrypted with a key that can be recovered by the next platform to execute it. The firmware 
provides the same set of interfaces to support this protection: SEND_START, 
SEND_UPDATE _DATA , SEND_UPDATE_VMSA,  and SEND_FINISH for the sending or 
snapshotting platform and RECEIVE_START, RECEIVE_U PDATE _DATA ,

snapshotting platform and RECEIVE_START, RECEIVE_U PDATE _DATA , 
RECEIVE_UPDATE_VMSA,  and RECEIVE_FINISH for the receiving or reconstituting 
platform.  
The SEND_START, SEND_UPDATE _DATA, SEND_UPDATE_VMSA , and SEND_FINISH 
commands are used to transform the guest’s memory image for transmission.  SEND_START 
establishes  a cryptographic context with the remote platform. Subsequent invocations of 
SEND_UPDATE _DATA  may be used to encrypt additional memory regions.  Each UPD ATE 
operation is independently integrity protected.  
The SEND_START command enforces the guest’s p olicy restriction on which platforms it may be 
transferred to. The policy can require the destination to be an SEV -capable platform or require the 
receiving platform to have the same owner as the sending one —or both. This check is performed 
by verifying th e receiving platform’s platform certificates and certificate chains.  
The receiving platform uses the related RECEIVE_START, RECEIVE_UPDATE _DATA, 
RECEIVE_UPDATE_VMSA , and RECEIVE_FINISH in the same manner as the sending 
platform. The RECEIVE_START derives t he cryptographic context necessary to re -encrypt the 
guest. The RECEIVE_UPDATE _DATA  and RECEIVE_UPDATE_VMSA  command s re-
encrypts memory regions provided by the hypervisor. The RECEIVE_FINISH command finalizes  
the operation. However, the RECEIVE_START comma nd does not verify the identity of the 
sending platform.  
The RECEIVE_START command is the only command other than the LAUNCH_START 
command that generates a new guest context and guest handle.  
1.3.4 Decommission  
When the hypervisor needs to shut down  a guest, it issues the DECOMMISSION command to the 
firmware. The firmware then deletes the memory encryption key and all other internal state the 
firmware has kept for the guest.    
 
24 Overview   Chapter 1  
 
1.3.5 Debugging  
The firmware provides two interfaces to assist in the debugging of an SEV enabl ed guest: 
DBG_ENCRYPT and DBG_DECRYPT. These commands request the firmware to encrypt or 
decrypt the data at the given memory regions provided by the hypervisor. Since decrypting 
protected memory allows the hypervisor to gain access to guest memory, the gu est policy must 
explicitly allow debugging to enable these two commands.     
 
 Chapter 2  Key Management  25 
 
Chapter 2  Key Management  
The primary purpose of the firmware is to manage the memory encryption keys and the keys to 
support the guest lifecycle within an enterprise environment. This section describes each of these 
keys. Table 1 summarizes all the keys, their abbreviations, their algorithm, and their usage.  
Table 1. Summary of Keys  
Key Abbr.  Algorithm  Usage  
Platform Diffie -Hellman Key  PDH  ECDH curve P -384 Key agreement  
Platform Endorsement Key  PEK  ECDSA curve P -384 Signing the PDH  
Chip Endorsement Key  CEK  ECDSA curve P -384 Signing the PEK  
AMD  SEV  Signing Key  ASK  RSA 2048  Signing the CEK  
AMD Root Key  ARK  RSA 2048  Signing the ASK; AMD root of 
trust 
Owner Certificate Authority  OCA ECDSA curve P -384 Signing the PEK; platform 
owner root of trust  
Transport Integrity Key  TIK HMAC SHA -256 Trusted channel Integrity  
Transport Encryption Key  TEK  AES 128  Trusted channel confidentiality  
Key Encryption Key  KEK  AES 128  Key wrapping  
Key Integrity Key  KIK HMAC SHA -256 Key wrapping  
VM Encryption Key  VEK  AES 128  Guest memory encryption  
 
2.1 Keys  
2.1.1 Platform Diffie -Hellman Key  
The Platform Diffie -Hellman key (PDH) is an Elliptic Curve Diffie Hellman (ECDH)   key using 
curve P -384 as defined in section D.1.2.3 of [ FIPS 186 -4]. The PDH is used to negotiate a master 
secret between the SEV firmware and external entities. This master secret is then used with a key 
derivation function (KDF)  to establish a tru sted channel.  
The SEV firmware generates the PDH using output from a secure entropy source. The lifetime of 
this key is the lifetime of the platform’s membership in its cloud or domain. When the Platform 
Encryption Key (PEK)  changes, the PDH is regenerated .   
Secure Encr ypted Virtualization API  
 
26 Key Management   Chapter 2  
 
2.1.2 Platform Endorsement Key  
The Platform Endorsement Key (PEK) is an ECDSA signing key using curve P -384 as defined in 
section D.1.2.3 of [FIPS 186 -4] It signs th e PDH to anchor the PDH to the AMD root of trust and 
the platform owner’s root of trust.   
The SEV firmware generates the PEK using a secure entropy source. The lifetime of this key is the 
lifetime of the platform's membership in its cloud or domain.  
2.1.3 Chip E ndorsement Key  
The Chip Endorsement Key (CEK) is an ECDSA signing key using curve P -384 as defined in 
section D.1.2. 3 of [ FIPS 186 -4]. It signs the PEK to anchor  the PEK to the AMD  root of trust. 
Each chip has a unique CEK which is derived from secrets stored in chip -unique OTP fuses. The 
lifetime of this key is the lifetime of the individual chip.  
2.1.4 AMD Signing Key  
The AMD SEV Signing Key (ASK) is an RSA 2048 -bit key pair.  It is an intermedia te signing key, 
signed by the AR K. The ASK private key signs the CEK public key to demonstrate that the CEK 
is an authentic AMD key.  
The AMD Key Distribution Server ( KDS ) managed by AMD contains the ASK private key. The 
lifetime of this key is the lifetime of the product line.  
2.1.5 Owner Certificate Authority Signing Key  
The platform owner’s Certificate Authority key ( OCA) is an ECDSA signing key using curve P -
384 as defined in  section D.1.2.3 of [FIPS 186 -4]. It is the root of trust of the platform owner and 
its signatures signify platform ownership. The OCA private key signs the PEK public key to 
demonstrate that the PEK is owned by the platform owner.  
When the platform is sel f-owned, the firmware stores both the OCA private key and public key. In 
this case, no entity outside of the SEV firmware has access to the OCA private key; the SEV 
firmware generates the OCA key pair using a secure entropy source.   
When the platform is ow ned by an external entity, the firmware stores only the OCA public key. 
In this case, only the platform owner has access to the private key; the platform owner must 
generate the OCA key pair according to its own security policies.  
When the SEV firmware sto res anything , including the OCA certificate,  in non -volatile storage, it 
is encrypted and integrity protected.    
 
 Chapter 2  Key Managem ent 27 
 
2.1.6 AMD Root Key  
The AMD Root key (ARK) is an RSA 2048 key pair. It is the root of trust of AMD and its 
signatures signify AMD authenticity. The ARK private key signs the ASK public key to 
demonstrate that the ASK is an authentic AMD key.  
The AMD KDS that is managed by AMD contains the ARK private key. The lifetime of this key 
is the lifetime of the product line.  
2.1.7 Transport Integrity Key  
The Transport I ntegrity Key (TIK) is a n HMAC SHA -256 integrity key. The SEV  firmware uses 
the TIK to integrity protect all trusted information transferred between the firmware and external 
entities such as the guest owner or another SEV firmware instance.  
The SEV firmwar e generates the TIK during the sending operational flows. In this case, the 
firmware generates the TIK from a secure entropy source.  
The SEV firmware imports a wrapped TIK during the launching and receiving operational flows.  
The lifetime of this key is th e lifetime of a single send, receive, or launch session. Once 
SEND_FINISH, RECEIVE_FINISH, or LAUNCH_FINISH are invoked respectively, the TIK is 
destroyed.  
2.1.8 Transport Encryption Key  
The Transport Encryption Key (TEK) is an AES -128 encryption key. The SEV fi rmware uses the 
TEK to encrypt all confidential information transferred between the firmware and external entities 
such as the guest owner or another SEV firmware instance.  
The SEV firmware generates the TEK during the sending operational flows. In this ca se, the 
firmware generates the TEK from a secure entropy source.  
The SEV firmware imports a wrapped TEK during the launching and receiving operational flows.  
The lifetime of this key is the lifetime of a single send, receive, or launch session. Once 
SEND_F INISH, RECEIVE_FINISH, or LAUNCH_FINISH are invoked respectively, the TEK is 
2.1.9 Key Encryption Key  
The Key Encryption Key (KEK) is an AES -128 encryption key. It is used to wrap the TEK and 
TIK during session establishment.  
The SEV firmware derives the KEK from the master secret negotiated during the key agreement 
protocol. The lifetime of this key is the lifetime of a single send, receive, or launch session. Once   
 
28 Key Management   Chapter 2

28 Key Management   Chapter 2  
 
SEND_FINISH, RECEIVE_FINISH, or LAUNCH_FINISH are invoked respectively, the KEK is 
2.1.10  Key Integrity Key  
The Key Integrity Key (KIK) is an HMAC -SHA -256 key. It is used to wrap the TEK and TIK 
during session establishment.  
The SEV firmware derives the KIK from the master secret negotiated during the key agreement 
protocol. The lifetime of this key is the lifetime of a single send, receive, or launch session. Once 
SEND_FINISH, RECEIVE_FINISH, or LAUNCH_FINISH are invoked respectively, the KIK is 
2.1.11  VM Encryption Key  
The VM Encryption Key (VEK) is a n AES -128 encryption key . The UMC uses the memory 
encryption key to encrypt guest data while the guest is operating.  
The SEV firmware generates the memory encryption key from a secure entropy source. The 
lifetime of this key is the lifetime of the guest while it executes on this platform. The guest will 
use a different VEK when migrated to a remote platform. The remote platform is responsible for 
generation of the new VEK.  
2.2 Usage  
The SEV firmware must be capable of communicating securely with other parties. This section 
describes h ow the firmware establishes a trusted channel between itself and the remote party.  
Each trusted channel has a client and server. In the SEV API, the guest owner and the SEV 
firmware instance issuing send commands are designated the client parties. The SEV firmware 
issuing launch and receive commands are designated the servers. These designations do not imply 
any further semantics beyond this trusted channel protocol.  
2.2.1 Key Derivation Function   
The SEV firmware uses a key derivation function (KDF) to securely derive new secrets from old 
secrets. Specifically, it uses the KDF to derive the CEK from fused secrets , and to derive transport 
keys from a negotiated master secret. The KDF used is the counter mode KDF specified in NIST 
[SP 800 -108], Section 5.1. It uses the HMAC -SHA -256 as the underlying pseudorandom function 
(PRF). The parameter r is set to 32 and the length in bits of [L]¬2 is 32.  
2.2.2 Master Secret Derivation   
Key agreement is  accomplished using the Elliptic Curve Diffie -Hellman (ECDH) protocol. The 
protocol follows the Static Unified Model described in Section 6.3.2 of NIST [SP 800 -56A].   
 
 Chapter 2  Key Management  29 
 
In summar y, the following occurs:  
• The client retrieves the server’s ECDH public key, Q¬¬S  
• The client transmits its ECDH public key, QC, to the server  
• The client transmits a fresh nonce, N, to the server  
• The client calculates a shared secret, Z, from Q¬¬S and its pr ivate key, dC.  
• The server calculates a shared secret, Z, from Q¬¬C and its private key, dS.  
• The client and server calculate the master secret, M, from Z and N using the KDF.  
The derivation of M uses the KDF. The parameters to the KDF are:  
• Secret input: Z  
• Label: “sev -master -secret”, ASCII encoded (17 bytes).  
• Context: N  
The intermediate secret Z must be securely deleted after the master secret is derived.  
2.2.3 Transport Key Establishment  
The client generates the transport encryption key (TEK) and the transport integrity key (TIK). The 
TEK and TIK are then transmitted to the server using key wrapping keys derived from the master 
secret, M.  
The Key Encryption Key (KEK) is derived using the KDF with the following parameters:  
• Secret input: M  
• Label: “sev -kek”, ASCII encoded (7 bytes).  
• Context: None  
The Key Integrity Key (KIK) is derived using the KDF with the following parameters:  
• Label: “sev -kik”, ASCII encoded (7 bytes).  
The TEK and TIK are concatenated together in that order,  encrypted, and integrity protected using 
the scheme specified in Section 2.2 on page 28, using the KEK as the encryption key, the KIK as 
the integrity key, and a freshly generated IV.  
When transmitt ing guest data from client to server, the TEK and TIK are used with the data 
protection scheme specified in Section 2.2 on page 28, according to the command specification.  
2.2.4 Data Protection  
The SEV API uses a common data protection scheme for multiple uses. The data protection 
scheme requires the following input parameters:    
 
30 Key Management   Chapter 2  
 
• A 128 -bit initialization vector, IV  
• A 128 -bit encryption key, K  
• A 128 -bit integrity protection key, I  
• A message to protect, M  
Two different messages should never be protected with the same IV and K. The IV may be 
repeated only when used with a different K.  
The d ata protection scheme used by this API utilizes AES -128 CTR mode for confidentiality 
protection and HMAC -SHA -256 for integrity protection. The output of this data protection is:  
• C = AES -128-CTR(M; K, IV)  
• MAC = HMAC -SHA -256(IV || C; I) 
The client must send C, MAC, and IV to the server to allow the server to recover the plaintext.  
   
 Chapter 3  Guest Policy  31 
 
Chapter 3  Guest Policy  
The firmware maintains a guest policy provided by the guest owner. This policy is enforced by the 
firmware and restricts what configuration and operational commands can be performed on this 
guest by the hypervisor. The policy also requires a minimum firmware level.  
The guest policy is provided to firmware during guest launch. The policy is then bound to the 
guest and cannot be changed throughout the lifetime of the guest. Th e policy is also transmitted 
during snapshot and migration flows and enforced on the destination platform.  
The guest policy is a 4 -byte structure with the fields shown in Table 2: 
Table 2. Guest Policy Structure  
Offset  Bit(s)  Name  Description  
000h  0 NODBG  Debugging of the guest is disallowed when set  
1 NOKS  Sharing keys with other guests is disallowed when 
set 
2 ES SEV -ES is required when set  
3 NOSEND  Sending the guest to another platform is disallowed 
when set  
4 DOMAIN  The guest must not be transmitted to another 
platform that is not in the domain when set.  
5 SEV  The guest must not be transmitted to another 
platform that is not SEV capable when set.  
15:6 Reserved. Should be zero.  
002h  7:0 API_MAJOR  The guest must not be transmitted to another 
platform with a lower firmware version.  003h  7:0 API_MINOR  
 
The policy bits for a given guest are referenced with the format POLICY.<FLAG_NAME>. For 
instance, the key sharing flag is referred to as POLICY. NOKS.   
 
32 Mailbox Register Protocol   Chapter 4  
 
Chapter 4  Mailbox Register Protocol  
Software on the x86 CPUs communicate with the AMD Secure Processor through a set of MMIO 
registers, referred to as ma ilbox registers.  This section describes the protocol used by the x86 
SEV driver for communicating through these mailbox registers to invoke the SEV key 
management functions described in this API.  
There are two modes these mailboxes can be used in : 
• Mailbox  mode  — the original mode the SEV FW supports  
• Ring Buffer mode  — a new mode with SEV FW 0.2 4 
Entry to Ring Buffer mode requires a RING_BUFFER command, sen t in Mailbox mode. After 
that, commands are submitted and status returned via queues in the ring buffe rs. 
4.1 Mailbox Mode  
In a nutshell, the driver writes the command  ID and 64 -bit physical address of a command buffer 
(if parameters are required) into the mailbox registers. The SEV firmware takes action and returns 
a 16-bit return code and potentially writes output to the same physical address parameter region.  
4.1.1 Mailboxes  
The SEV API exposes an external interface to the x86 system software through three memory 
mapped registers: CmdResp, CmdBufAddr_Hi, and CmdBufAddr_Lo. Their formats are 
described in Table 3, Table 4, and Table 5, respectively.  
Table 3. CmdResp Register Layout  
Bit(s) Description/Purpose  
31 0: Command; 1: Response  
[30:2 6] Reserved . Must be zero.  
[25:16] Command ID  
[15:0]  When bit 31 is 1: Status  code  from SEV Firmware  
When bit 31 is 0: Bit 0 : x86 requests SEV FW to interrupt on completion . Other 
bits are reserved, must be zero.  
Table 4. CmdBufAddr_Hi Register Layout  
31:0 Most significant 32 bits of the physical address of the command buffer  
Table 5. CmdBufAddr_Lo Register Layout  
31:0 Least significant 32 bits of the physical address of the command buffer    
 
 Chapter 4  Mailbox Register Protocol  33 
 
The x86 system software issues commands to the firmware by writing to these 32-bit registers. 
These registers appear in the memory -mapped I/O space of the PSP device in PCI space. The

These registers appear in the memory -mapped I/O space of the PSP device in PCI space. The 
precise physical address of these registers is normally determined by BIOS when it performs PCI 
device enumeration. Relative to the base address assigned by BIOS to the PSP device’s memory -
mapped I/O space, CmdResp  is register 32 (offset 128), CmdBufAddr_Lo is register 56 (offset 
224), and CmdBufAddr_Hi is register 57 (offset 228).  
The x86 system software first constructs a command buffer (formatted specifically for the given 
command) within system DRAM. The x86 sys tem software then writes the most significant 32 
bits of the command buffer's physical address into the CmdBufAddr_Hi register and the least 
significant 32 bits into the CmdBufAddr_Lo address.  
The x86 software then writes to the CmdResp register to issue the command with bit 31 set to 0 to 
indicate that this is an issued command and bits [25:16] containing the command identifier. The 
values written into bits [15:1] are reserved and must be writt en as 0 by the x86 software . The x86 
software may set bit 0 to inform the SEV firmware to interrupt the x86 core upon command 
completion.  
Upon command completion, the PSP firmware writes to the CmdResp register. The PSP firmware 
sets bit 31 to 1 to indicate that this is a command response and bits [15:0] to the 16 -bit status code.  
If the command is not recognized, an INVALID_COMMAND status code is returned.  
4.2 Ring Buffer Mode  
Upon successful completion of the RING_BUFFER command from Mailbox mode, 
comm unications between the x86 SEV driver and the PSP firmware changes the semantics of the 
three  registers.  
• The CmdResp register becomes the RBCtl register . It is only ever written by the x86.  
• The CmdBufAddr_Hi register becomes the RBTail register . It is onl y ever written by 
the x86.  
• The CmdBufAddr_Lo register becomes the RBHead register . It should n ever be 
written by the x86; the PSP will update it.  
There are up to two queues created by the RING_BUFFER command, each with parallel arrays . 
The parallel arrays for CmdPtr entries (written only by the x86) and StatVal  entries (written only 
by the PSP FW) . The two queues are a low priority queue  (required)  and a high priority queue  
(optional) . Each time the PSP is ready to process a new command, the high pr iority queue is 
checked for work before the low priority queue.  As long as the high priority queue has work,  the 
low pr iority queue will not be serviced.  
Work to be entered on a queue is written by the x86 in an entry at the tail of the queue in a 16-byte 
entry called a CmdPtr. The CmdPtr replicates and extends the information that Mailbox mode 
passes in the three  registers. The CmdPtr entry is structured  as shown i n Table 6.   
 
34 Mailbox Register Protocol   Chapter 4  
 
Table 6. CmdPtr Entry Lay out 
Byte Offset  Bits Description  
00h 15:0 Command Identifier (from Table 13)  
02h 15:0 Command Flags  
04h 31:0 Software Data  
08h 63:0 Command Buffer Pointer  
 
Software Data is an arbitrary 32 -bit value that the x86 software can use for anything. The 
Command Identifier contains  the Command ID value from Table 13. Command Flags  contains the 
flags defined in  Table 7. The Command Buffer Pointer points at the command buffer for the 
Command Identifier, if any . 
Table 7. Command Flags Values  
Bit(s) Name  Description  
[15:2] - Reserved. Must be 0.  
1 ContinueOnError  1 – Continue even if command returns an error . 
0 – Pause the queue if command returns an error.  
0 InterruptOnCompletion  1 – Interrupt when command complete s. 
0 – No interrupt  when command completes.  
 
There are two bits defined for the Command Flags in a CmdPtr entry. Bit 0, as in Mailbox mode, 
is the request for the completion of this command to interrupt  the x86. Bit 1 is the ContineOnError 
flag. If it is 0,  commands that return errors will block the queue, preventing any additional 
commands from being processed from th e queue until the queue error recovery sequence is 
completed for the queue.  
After the PSP processes a command from the CmdP trs array, it writes the result in to the StatVal 
array, which parallels (by index) the CmdP trs array.  That is, after processing a command from the 
CmdPtrs array at index N, the result of that command will be wr itten to the StatVal array at index 
N. The layout of a StatVal entry is shown in Table 8. 
Table 8. StatVal Entry Layout  
00h 15:0 Status . 
02h 15:0 Reserved . 
04h 31:0 Reserved.  
08h 63:0 Reserved.  
   
 Chapter 4  Mailbox Register Protocol  35 
 
As mentioned earlier,  in Ring Buffer mode, the three  mailbox registers have different semantics.  
The RBCtl register is written only by the x86 and has the following layout.  
Table 9. RBCtl Register  Layout  
Bit(s) Name  Description/Purpose  
31 X86Writes  Must be 1. 0 will exit Ring Buffer mode (indicates x86 controls the 
register) . 
30 RBModeAct  Must be 1. 0 will exit Ring Buffer mode (indicates Ring Buffer 
mode active.)  
29 ClrIntStat  Clear Interrupt Status bits in RBHead  register.  
[28:10]  - Reserved. Must be 0.  
9 QHiResume  Resume Hi priority queue. (Part of queue error recovery.)  
8 QLoResume  Resume Lo priority queue. (Part of queue error recovery.)  
[7:2]  - Reserved. Must be 0.  
1 QHiFreeIntEn  Enable Hi priority queue near empty interrupt.  
0 QLoFreeIntEn  Enable Lo priority queue near empty interrupt.  
 
In Ring Buffer mode, the RBTail register is written only by the x86 and has the following layout:  
Table 10. RBTail Register Layout  
[31:24] - Reserved. Must be 0.  
[23:16] QHiTail  Hi priority Queue CmdPtr Tail index . 
[15:8]  - Reserved. Must be 0.  
[7:0]  QLoTail  Lo priority Queue CmdPtr Tail index . 
 
In Ring Buffer mode, the RBHead register is written only by the PSP and has the following 
layout:  
Table 11. RBHead Register L ayout  
31 QFreeIntStat  A queue is near empty.  
30 QPausedIntStat  A command without ContinueOnError s et did not return 
SUCCESS.  
29 CmdDoneIntStat  A command with InterruptOnCompletion set completed.  
28 AllQEmpty IntStat  All queues are empty.  
27 QHiRunning  Hi priority Queue is running.    
 
36 Mailbox Regis ter Protocol   Chapter 4  
 
[26:24]  - Reserved.  
[23:16] QHiHead  Hi priority Queue CmdPtr Head index.  
[15:12]  - Reserved.  
11 QLoRunning  Lo priority Queue is running.  
[10:8] - Reserved.  
[7:0]  QLoHead  Lo priority Queue CmdPtr Head  index . 
 
The x86 submits a command to a queue in ring buffer mode by creating any necessary buffers,  
writing the entry in the CmdPtr array  at the desire Q*Tail in dex, incrementing the Q*Tail index 
(modulo the queue size provided in the RING_BUFFER command)  in the RBTail register and 
finally  writing an appropr iate value to RBCtl.  Multiple commands may be submitted at one time. 
Additional commands can be submitted any time the queue has room . The depth of the queue is 
(Q*Tail – Q*Head) modulo QSize.  
The PSP,  at the beginning of each command, clears the four IntStat bits in the RBHead register if 
ClrIntStat in the RBCtl register is set . Note that ClrIntStat is sampled only at the beginning of each 
command execution.  
If an error occurs executing the command and the command didn’t have ContinueOnError set , the 
PSP pauses the queue from which the command was fetched and clears that queue’s Running bit.  
At the end of each command, each IntStat bit may be set (and will stay set until ClrIntStat clears 
them) if the corresponding condition is met. If one or more  of the conditions is met, one interrupt 
will be sent to the x86.  
If the command caused the queue to be paused , the QPausedIntStat bit will be set. If the command 
had its InterruptOnCompletion flag set, CmdDoneIntStat bit will be set. If the RBCtl register  has a 
Q*FreeIntEn bit set and the corresponding queue is below the threshold established with the 
RING_BUFFER command, the QFreeIntStat bit will be set. If both queues are empty and the 
RING_BUFFER command had the InterruptOnEmpty flag set, the AllQEmptyI ntStat bit will be 
set. Once set, each IntStat bit will remain set until ClrIntStat is set when processing a later 
command.  
If a queue is paused, it will stay p aused until the x86 cleans up the queue. The x86 is free to  
manipulate any command in the queue and the queue tail index. The x86  may not adjust the queue 
head index . Setting the queue tail index equal to the queue head index will empty the queue.  When 
the x86 is done cleaning up the queue, it shall set the queue’s Resume bit in the RBCtl register. 
This bit must remain set until the PSP acknowledges seeing the Resume bit by setting the queue’s

command.  
This bit must remain set until the PSP acknowledges seeing the Resume bit by setting the queue’s 
Running bit in the RBHead register.  When the x86 clears  the Resume bit, the PSP will again start 
processing commands from the queue.    
 
 Chapter 4  Mailbox Register Protocol  37 
 
Table 12. Ring Buffer Mode Error Recovery  Handshake Sequen ce 
QRunning  bit 
PSP Controlled  QResume Bit 
x86 Controlle d Description  
1 0 Normal operation. Commands are accepted from the queue.  
0 0 A command without ContinueOnError set has fai led. The queue is 
paused.  
0 1 The x86 has cleaned up the queue.  
1 1 The PSP acknowledges clean up complete . 
1 0 Normal operation resumes.  
 
Ring Buffer mode exit s if a SHUTDOWN command is executed or an invalid value is read from 
the RBCtl register ( that is , one with either the x86Writes or RBModeAct bits clear, or one of the 
“must be zero” bits set). Mailbox mode is active after Ring Buffer mode i s exited. If Ring Buffer 
mode exits because of an invalid value written to RBCtl, then the value in that register is ignored. 
If bit 31 of the mailbox mode CmdResp register is 0, indicating a command has been issued, the 
response shall be the status value RB_MODE_EXITED  and the command will be ignored.  
4.3 Command Buffer  
In both Mailbox mode and Ring Buffer mode, the x86 system software is responsible for 
allocating the command buffer. The size of the command buffer is fixed for a given command. 
Some commands require the command buffer to be populated with pointers to secondary buffers. 
The x86 system software is also responsible for allocating these secondary buffers.  
The command buffer and all secondary buffers must reside within memory accessible to  the x86 
system software. The SEV API enforces this by checking the validity of all pointers provided by 
the x86 system software before use.  
All pointers provided by the x86 software are 64 -bit system physical addresses.  
4.4 Command Identifiers  
Table 13 summarizes the platform management, guest management, and debugging commands. 
See the command definitions for further details.  The API column indicates which version of the 
API the command first appeared in. The first public SEV API version was 0.16.   
Table 13. Command Identifiers  
Command  ID API Description  
INIT  001h  16 Initialize the platform  
INIT_EX  00Dh  18 Initialize the platform with extended parameters  
SHUTDOWN  002h  16 Shut down the platform  
PLATFORM_RESET  003h  16 Delete the persistent platform state    
 
38 Mailbox Register Protocol   Chapter 4  
 
PLATFORM_STATUS  004h  16 Return status of the platform  
PEK_GEN  005h  16 Generate a new PEK  
PEK_CSR  006h  16 Generate a PEK certificate signing request  
PEK_CERT_IMPORT  007h  16 Import the signed PEK certificate  
PDH_GEN  009h  16 Generate a new PDH and PEK signature  
PDH_CERT_EXPORT  008h  16 Export the PDH and its certificate chains   
DOWNLOAD_FIRMWARE  00Bh  16 Download new SEV firmware  
GET_ID  00Ch  16 Get System Unique ID  
NOP  00Eh  23 Nop command  
RING_BUFFER  00Fh  24 Enter Ring Buffer  command mode  
LAUNCH_START  030h  16 Begin to launch a new SEV enabled guest  
LAUNCH_UPDATE_DATA  031h  16 Encrypt guest data for launch  
LAUNCH_UPDATE_VMSA  032h  16 Encrypt guest VMCB save area for launch  
LAUNCH_MEASURE  033h  16 Output the launch measurement  
LAUNCH_UPDATE_SECRET  034h  16 Import a guest secret sent from the guest owner  
LAUNCH_FINISH  035h  16 Complete launch of guest  
ATTESTATION  036h  23 Provide signed measurement to hypervisor  
SEND_START  040h  16 Begin to send guest to new remote platform  
SEND_UPDATE_DATA  041h  16 Re-encrypt guest data for transmission  
SEND_UPDATE_VMSA  042h  16 Re-encrypt guest VMCB save area for transmission  
SEND_FINISH  043h  16 Complete sending guest to remote platform  
SEND_CANCEL  044h  23 Cancel a send operation in progress  
RECEIVE_START  050h  16 Begin to receive guest from remote platform  
RECEIVE_UPDATE_DATA  051h  16 Re-encrypt guest data from transmission  
RECEIVE_UPDATE_VMSA  052h  16 Re-encrypt guest VMCB save area from 
transmission  
RECEIVE_FINISH  053h  16 Complete receiving guest from remote platform  
GUEST_STATUS  023h  16 Query the status and metadata of a guest  
ACTIVATE  021h  16 Load a guest’s key into the memory controller  
DEACTIVATE  022h  16 Unload a guest’s key into the memory controller  
ACTIVATE_EX  025h 18 Load a guest’s key into the memory controller  
DF_FLUSH  00Ah  16 Flush the data fabric  
DECOMMISSION  020h  16 Delete the guest’s SEV context in firmware  
COPY  024h  17 Copy encrypted guest memory to a new guest 
location    
 
 Chapter 4  Mailbox Register Protocol  39 
 
SWAP_OUT  070h  23 Decrypt guest memory page and re-encrypt for 
temporary storage  
SWAP_IN  071h  23 Decrypt temporarily -stored page and re -encrypt for 
guest use  
DBG_DECRYPT  060h  16 Decrypt guest memory region for debugging  
DBG_ENCRYPT  061h  16 Encrypt guest memory region for debugging  
 
4.5 Status Codes  
Table 14 summarizes the status codes that can be returned by the firmware commands. See the 
command definitions for further details.  
Table 14. Status Codes  
Status  Code  Description  
SUCCESS  0x0000  Successful completion  
INVALID_PLATFORM_STATE  0x0001  The platform state is invalid for this command  
INVALID_GUEST_STATE  0x0002  The guest state is invalid for this command  
INVALID_CONFIG  0x0003  The platform configuration is invalid  
INVALID_LENGTH  0x0004  A memory  buffer is too small.  
ALREADY_OWNED  0x0005  The platform is already owned  
INVALID_CERTIFICATE  0x0006  The certificate is invalid  
POLICY_FAILURE   0x0007  Request is not allowed by guest policy  
INACTIVE  0x0008  The guest is inactive  
INVALID_ADDRESS  0x0009  The address provided is invalid  
BAD_SIGNATURE  0x000A  The provided signature is invalid  
BAD_MEASUREMENT  0x000B  The provided measurement is invalid  
ASID_OWNED  0x000C  The ASID is already owned  
INVALID_ASID  0x000D  The ASID is invalid  
WBINVD_REQUIRED  0x000E  WBINVD instruction required  
DF_FLUSH_REQUIRED  0x000F  DF_FLUSH invocation required  
INVALID_GUEST  0x0010  The guest handle is invalid  
INVALID_COMMAND  0x0011  The command issued is invalid.  
ACTIVE  0x0012  The guest is active.    
Vers ion 0.24  55766  Rev. 3.24 April 2020   
 
40 Mailbox Register Protocol   Chapter 4  
 
HWERROR_PLATFORM  0x0013  A hardware condition has occurred affecting the 
platform. It is safe to re -allocate parameter 
buffers.  
HWERROR_UNSAFE  0x0014  A hardware condition has occurred affecting the 
platform. Re-allocat ing parameter buffers  is not 
safe. 
UNSUPPORTED  0x0015  Feature is unsupported.  
INVALID_PARAM  0x0016  A parameter is invalid.  
RESOURCE_LIMIT  0x0017  The SEV FW has run out of a resource 
necessary to complete the command.  
SECURE_DATA_INVALID  0x0018  The part -specific SEV data failed integrity 
checks.  
RB_MODE_EXITED  0x001 F A Mailbo x mode command was sent while the 
SEV FW was in Ring Buffer mode. Ring Buffer 
mode has b een exited ; the Mailbox mode 
command has been ignored. Retry is 
recommended.  
 
4.6 Endianness  
All integral values passed between the firmware and the CPU driver are little -endian formatted 
unless otherwise specified. That is, the first byte of the integer representation is the least 
significant byte. Note that this applies to all bit integer  values  in public keys and signatures unless 
explicitly stated otherwise.  
4.7 Synchrony  
The SEV API processes commands serially. The x86 system software receives a response when 
the SEV firmware has completed processing the command. The x86 system software must not 
send subsequent commands before receiving a response from the SEV firmware for the first sent 
command.  
Any subsequent commands sent by the x86 system software before receiving a response must be 
ignored by the SEV firmware and must not result in any change to the platform or any guest 
context.  
4.8 Address Validation  
All addresses provided by x86 system software are checked by SEV firmware to ensure that the 
regions do not overlap invalid memory regions. Each address is checked that it does not have any 
of the fo llowing properties:    
 
 Chapter 4  Mailbox Register P rotocol  41 
 
• Bits 46:43 != 0  
• Overlaps TSseg  
• Overlaps ASeg  
• Is above the max physical address (7FD_0000_0000)  
• Lies within any Trusted Memory Region ( TMR ) that disallows x86 software access  
This check is performed before any action is taken on the cont ents of addresses provided by the

command.  
context.  
 
This check is performed before any action is taken on the cont ents of addresses provided by the 
x86 system software as parameters. If the check fails, an INVALID_ADDRESS status code is 
returned.    
 
42 Platform Management API   Chapter 5  
 
Chapter 5  Platform Management API  
This chapter  describes the platform management commands. Platform management commands are 
used by t he platform owner to provision the platform and query platform -wide data.  
5.1 Overview  
This section overviews the platform management and provides the background to understand the 
semantics of each command.  
5.1.1 Platform Context  
The SEV firmware maintains a platform context throughout the lifetime of the platform. This 
context contains data and metadata necessary to implement the SEV API.  
Table 15. Platform Context (PCTX) F ields  
Field  Field Description  
STATE  The current state of the platform in the PSTATE finite state machine . 
CONFIG  The configuration of the platform.  
PDH  Platform Diffie Hellman key . 
PEK  Platform Endorsement Key . 
CEK  Chip Endorsement Key . 
OCA  Owner Certificate Authority key . 
GUEST_COUNT  Number of guest contexts currently managed by the firmware . 
GUESTS  The guest contexts currently managed by the firmware . 
 
The platform context is denoted PCTX. The PCTX fields are referenced as PCTX.<FIELD>. For 
instance, the number of guests currently managed by the platform would be denoted 
PCTX.GUEST_COUNT. When unambiguous, the PCTX portion may be omitted.    
 
 Chapter 5  Platform Management API  43 
 
5.1.2 Platform State Machine  
The SEV firmware traverses a platform finite state machine during operation. The firmware may 
only execute  certain commands in each platform state.  Guest commands are only valid in INIT 
and WORKING platform states.  
Table 16. PSTATE Finite State Machine  
State  Value  Description  Allowed Platform Commands  
UNINIT  0h The platform is uninitialized.  INIT, PLATFORM_RESET, 
PLATFORM_STATUS , 
DOWNLOAD_FIRMWARE , GET_ID , 
DF_FLUSH, NOP  
INIT  1h The platform is initialized but not 
currently managing any guests.  SHUTDOWN, PLATFORM_STATUS, 
PEK_GEN, PEK_CSR, 
PEK_CERT_IMPORT, PDH_GEN, 
PDH_CERT_EXPOR T, DF_FLUSH , 
GET_ID , NOP , RING_BUFFER  
WORKING  2h The platform is initialized and current 
managing guests.  SHUTDOWN, PLATFORM_STATUS, 
PDH_GEN, PDH_CERT_EXPORT, 
DF_FLUSH , GET_ID , NOP , 
RING_BUFFER  
 
The platform finite state machine is denoted PSTATE. The PSTATE states are referenced as 
PSTATE.<STATE>. For instance, the uninitialized state is denoted PSTATE.UNINIT.  
5.1.3 Authenticity  
An authentic platform is a platform that is executing AMD developed firmware on AMD 
hardware. Authenticity allows the guest owner t o trust that the platform it communicates with will 
implement SEV correctly and securely.  
The authenticity of the platform is defined by a certificate chain rooted in the ARK, the AMD root 
of trust. The ARK signs the ASK, which in turn signs the CEK. The C EK signs the PEK which 
roots the PEK in the AMD root of trust, asserting that this platform is an authentic AMD platform.  
5.1.4 Ownership  
A platform may be owned by an external entity or it may be self -owned. Platforms can disallow 
migration of guests to platfor ms that do not share the same owner. This allows platform owners to 
contain guests within a known set of servers.  
The platform ownership is defined by a certificate chain rooted in the OCA, the owner’s root of 
trust. The OCA signs the PEK. When the platfor m is not owned by an external entity, the platform 
generates its own OCA key pair.    
Secure Enc rypted Virtualization API  
 
44 Platform Management API   Chapter 5  
 
5.1.5 Non-volatile Storage  
The platform stores identity information in non -volatile storage available to the firmware. The 
identity information includes the following:  
• PDH key pa ir 
• PDH certificate  
• PEK key pair  
• PEK certificate  
• OCA public key  
• OCA private key (only if self -owned)  
• OCA certificate  
The firmware writes each of these keys immediately after generation, derivation, or import. The 
persistent data is stored encrypted and inte grity protected.  
If a power failure occurs during a write operation to non -volatile storage, the persistent data may 
become corrupted. Upon executing the INIT command immediately after the power failure, the 
command will return an integrity check failure s tatus code. In such a case, the platform must be 
reset with the PLATFORM_RESET command.  
5.1.6 Power State Transitions  
Table 17 summarizes the effects of power state transitions on the firmware.  
Table 17. Power Management Transitions  
Power State  Effect  
S0, S1, S2, S3  The firmware volatile state is not affected and resumes execution after 
transitioning out of the low power states.  
Hybrid Sleep  This is equivalent to preparing to transition to S4, but transitioning to S3. If a 
power failure occurs, the system resumes as if it transit ioned to S4. If not, it 
the system resumes as if it transitioned to S3.  
S4, S5, Mechanical 
Off The firmware starts from the reset state and must be re -initialized. No non -
persistent state is recovered from the point before the power state transition.  
 
5.1.7 SEV-ES Trusted Memory Region  
The SEV -ES product feature requires that the x86 system software donate a 1 MB region aligned 
on a 1 MB boundary to the firmware for exclusive use by the firmware during the lifetime of the 
platform (until a SHUTDOWN command invo cation). The firmware uses the memory region to 
store integrity data necessary to support the SEV -ES functionality.  Attempts by the x86 to access 
this memory while donated will result in exceptions that frequently cause system instability.    
 
 Chapter 5  Platform Management API  45 
 
5.2 INIT  
This command is used by the platform  owner  to the initialize the platform . This command loads 
the SEV related persistent data from non -volatile storage and initializes the platform context. In 
typical workflows, this command should be the first command iss ued, aside from the possible 
invocation of PLATFORM_STATUS to determine the supported API version.  
5.2.1 Actions  
The platform must be in the PSTATE.UNINIT state.  
The firmware first loads the persistent state into its private memory, and  validates it. If valida tion 
fails, an error is returned and the persistent state is erased. If validation succeeds,  then the 
following actions  are performed : 
• The CEK is derived from the chip unique values.  
• If no OCA certificate exists, a n OCA signing key is generated and a self -signed OCA 
certificate is created. The signing key and certificate are written to persistent storage . 
• If no PEK exists or the OCA was just regenerated, a PEK signing key is generated and 
a PEK certificate is created and signed by the OCA and CEK . The PEK and its 
certificate are written to persistent storage . 
• If no PDH exists or the PEK was just regenerated, a PDH key is generated.  A 
certificate is created for the PDH and is signed by the PEK.  
• All SEV -related ASIDs on all cores are marked invalid. Each core requires a WBINVD 
before activating any guest. See ACTIVATE and DEACTIVATE for further details.  
Upon successful completion, the  platform transitions to the PSTATE.INIT state.  
5.2.2 Parameters  
Table 18 specifies the parameters for the INIT  command.  
Table 18. INIT Command Buf fer 
Byte Offset  Bits In / Out  Name  Description  
00h 0 In – SEV -ES is initialized for the platform when set. It 
is disabled for all guests when not set.  
31:1 – – Reserved. Must be zero.  
04h 31:0 – – Reserved. Must be zero.  
08h 63:0 In TMR_PADDR   If CONFIG.ES=1, system physical address to 
memory region donated by hypervisor for SEV -
ES operations. Must be 1MB aligned.  
 
Ignored if CONFIG.ES=0    
 
46 Platform Management API   Chapter 5  
 
10h 31:0 In TMR_LENGTH  If CONFIG.ES=1, length of the memory region 
donated by hypervisor for SEV -ES operation. 
Must equal 1MB.  
 
Ignored if CONFIG.ES=0  
5.2.3 Status Codes   
Table 19 enumerates the possible status codes returned by this command.  
Table 19. INIT Command Status Codes   
Return Value  Reason  
SUCCESS  Successful completion  
INVALID_PARAM  A parameter is invalid  
INVALID_PLATFORM_STATE  The platform is not in the PSTATE.UNINIT state 
INVALID _LENGTH  A buffer length is not correct  
INVALID_CONFIG  The configuration flags are invalid or unsupported  
INVALID_ADDRESS  A memory region provided contains invalid physical addresses.  
INVALID_SECURE_DATA  Data in non -empty SPI failed integrity checks.

INVALID_SECURE_DATA  Data in non -empty SPI failed integrity checks.  
HWERROR_PLATFORM  A hardware condition has occurred affecting the platform. It is safe 
to re-allocate parameter buffers.  
HWERROR_UNSAFE  A hardware con dition has occurred affecting the platform. It is 
unsafe to re -allocate parameter buffers.  
 
5.3 INIT_EX  
The INIT_EX command is used by the platform owner to the initialize the platform with extended 
parameters. This command loads the SEV related persistent data from user -supplied data and 
initializes the platform context. In typical workflows, this command should be the first command 
issued, aside from the possible invocation of PLATFORM_STATUS to determine the supported 
API version.  
5.3.1 Actions  
The p latform must be in the PSTATE.UNINIT state.  
The firmware first loads the persistent state into its private memory, and  validates it. If validation 
following a ctions  are performed :   
 
 Chapter 5  Platform Management API  47 
 
certificate is created. The signing key and certificate are written to persistent storage.  
• If no PEK e xists or the OCA was just regenerated, a PEK signing key is generated and 
a PEK certificate is created and signed by the OCA and CEK. The PEK and its 
certificate are written to persistent storage.  
• If no PDH exists or the PEK was just regenerated, a PDH key  is generated. A 
Upon successful c ompletion, the platform transitions to the PSTATE.INIT state.  
The area of memory pointed to by NV_PADDR must be reserved for SEV FW use from the time 
of the INIT_EX call until SHUTDOWN. The uninitialized empty state of this memory is all bytes 
FFh.  The ca ller is expected to preserve the 32KB area so that it may be passed in to a future 
INIT_EX call. The contents of the area are tied to the specific CPU in use and cannot be used with 
any other CPU, even of the same model. The area will only change for some platform commands 
(Chapter 5.) No other commands alter the area. If NV_PADDR is 0, the SPI will be used instead.  
5.3.2 Parameters  
Table 20 specifies the parameters for the INIT_EX  command.  
Table 20. INIT_EX Command Buffer  
00h 31:0 In EX_LEN  Length of the command buffer. 24h for 0.22 of 
the API.  
04h 0 In FLAGS  SEV -ES is initialized for the platform when set. It 
31:1 In – Reserved. Must be zero.  
 
14h 31:0 In - Reserved. Must be zero.    
 
48 Platform Management API   Chapter 5  
 
18h 63:0 In NV_PADDR  System Physical Address of an area of memory 
the SEV FW will use in lieu of SPI. Must be 4KB 
aligned.  
20h 31:0 In NV_LENGTH  Length of area in bytes to be used in lieu of SPI. 
Must be 32KB.  
5.3.3 Status Codes  
Table 21 enumerates the possible status codes returned by this command.  
Table 21. INIT_EX Command Status Codes  
INVALID_PLATFORM_STATE  The platform is not in the PSTATE.UNINIT state  
INVALID_ADDRESS  A memory region p rovided contains invalid physical addresses.  
INVALID_SECURE_DATA  Data in non -empty NV memory area or SPI failed integrity checks.  
HWERROR_UNSAFE  A hardware condition has occurred affecting the platform. It is 
 
5.4 SHUTDOWN  
The SHUTDOWN command is used by the platform owner to transition the platform to the 
uninitialized state.  
5.4.1 Actions  
The platform may be in any state.  
All platform and guest state maintained by the firmware is securely deleted from volatile storage.  
If SEV -ES is enabled during platform initialization, the firmware returns control of the SEV -ES 
TMR back to the x86. After  this command completes, the TMR will be accessible by x86 
software.    
 
 Chapter 5  Platform Management API  49 
 
Upon successful completion, the platform transitions to the PSTATE.UNINIT state.  The 
mailboxes revert to Mailbox mode.  
If the SHUTDOWN is for an INIT for SEV -ES, then a WBINVD on all threads is required 
immediately following the completion of the SHUTDOWN command.  
5.4.2 Parameters  
None.   CmdBuf_Lo and CmdBuf_Hi registers are ignored.  
5.4.3 Status Codes   
Table 22 enumerates the possible status codes returned by this command.  
Table 22. SHUTDOWN Command Status Codes  
HWERROR_PLAT FORM  A hardware condition has occurred affecting the platform. It is safe to 
re-allocate parameter buffers.  
HWERROR_UNSAFE  A hardware condition has occurred affecting the platform. It is unsafe to 
 
5.5 PLATFORM _RESET  
The PLATFORM_RESET  command is used by the platform owner to reset the non -volatile SEV 
related data. Invoking this command is useful when the owner wishes to transfer the platform to a 
new owner or securely dispose of the system.  
5.5.1 Actions  
The platform must be i n the PSTATE.UNINIT state. Otherwise, an error is returned.  
The persistent state is securely deleted from non -volatile storage.  
The platform remains in the PSTATE.UNINIT state after completion.  
5.5.2 Parameters  
None.   CmdBuf_Lo and CmdBuf_Hi registers are ignore d. 
5.5.3 Status Codes  
Table 23 enumerates the possible status codes returned by the PLATFORM_RESET command.    
 
50 Platform Manageme nt API   Chapter 5  
 
Table 23. PLATFORM _RESET  Command Status Codes  
SUCCESS  Successful completion . 
INVALID_PLATFORM_STATE  The platform is not in the PSTATE.UNINIT state. 
 
5.6 PLATFORM_STATUS  
The PLATFORM_STATUS  command is used by the platform owner to collect the current statu s 
of the platform.  
5.6.1 Actions  
If the platform is in the PSTATE.UNINIT state, then the following fields are set to zero:  
• OWNER  
• CONFIG.ES  
• GUEST_COUNT  
The OWNER bit is set to 1 if the platform is owned by an external owner. The OWNER bit is set 
to 0 if the platform is self -owned.  
The CONFIG flags are equal to the values passed to the INIT command.  
The platform remains in the same state after completion.  
5.6.2 Parameters  
Table 24 specifies the parameters for the PLATFORM_STATUS  command.  
Table 24. PLATFORM_STATUS Command Buffer  
00h 7:0 Out API_MAJOR  Major API version  
01h 7:0 Out API_MINOR  Minor API version  
02h 7:0 Out STATE  Current platform state. See Table 3.   
 
 Chapter 5  Platform Management API  51 
 
03h 0 Out OWNER  OWNER=0: Self -owned  
OWNER=1: Externally owned . 
7:1 – – Reserved. Set to zero.  
04h 0 Out CONFIG.ES  SEV -ES is initialized for the platform when set. 
It is disabled for all guests when not set.  
23:1 – – Reserved. Set to zero.  
31:24  Out BUILD  Firmware Build ID for this API version.  
08h 31:0 Out GUEST_COUNT  Number of valid guests maintained by the 
firmware  
 
5.6.3 Status Codes  
Table 25 enumerates the possible status codes returned by the PLATFORM_STATUS command.  
Table 25. PLATFORM_STATUS Command Status Codes  
INVALID_ADDRESS  A memory region provided contains invalid physical addresses  
5.7 PEK_GEN

firmware  
 
5.7 PEK_GEN  
This command is used to generate a new PEK. This may be used to regenerate the identity of the 
platform if required by the user’s policy. This comm and is not necessary for normal workflows as 
the INIT command regenerates this after being invoked for the first time after a platform reset.   
5.7.1 Actions  
The platform must be in the PSTATE.INIT state. Otherwise, an error is returned.  
The following objects are  securely deleted from volatile and non -volatile storage:  
• PDH key pair  
• OCA key pair (if the platform is self -owned)  
• OCA certificate    
 
52 Platform Management API   Chapter 5  
 
A new OCA signing key pair and self -signed certificate are generated and stored in non -volatile 
storage. The previous OCA certificate (and signing key if self -owned) is securely deleted.  
A new PEK signing key pair and certificate signed by the new OCA are generated and stored in 
non-volatile storage. The previous PEK signing ke y and certificate are securely deleted.  
A new PDH key pair is generated and signed by the PEK. Regeneration of the PDH is equivalent 
to the invocation of the PDH_GEN command.  
Note that in this version of the API, this command is an alias for an invocation of SHUTDOWN, 
PLATFORM_RESET, and INIT, in that order.  
5.7.2 Parameters  
None.  The CmdBuf_Lo and CmdBuf_Hi mailbox registers are ignored.  
5.7.3 Status Codes  
Table 26 enumerates the possible status codes returned by the PEK_GEN command.  
Table 26. PEK_GEN Command Status Codes  
INVALID_PLATFORM_STATE  The platform is not in the PSTATE.INIT state 
to re-allocate parameter buffers  
HWERROR_UNSAFE  A hardware condition has occurred affect ing the platform. It is 
 
5.8 PEK_CSR  
During the provisioning process, the owner of the platform can take ownership using this 
command in conjunction with the PEK_CERT_IMPORT command. The CSR contains identifying 
inform ation of this platform and also contains the PEK public key. A certificate authority 
processes the CSR by generating a certificate with the information from the CSR and signing it 
with its key.  
The caller can issue this command with the PEK_CSR_LEN field s et to zero to query the correct 
amount of memory to allocate for the CSR.    
55766 Rev. 3.24 April 2020    Secure Encrypted Virtualization API  
 
 Chapter 5  Platform Management API  53 
 
5.8.1 Actions  
The platform must be in the PSTATE.INIT or PSTATE.WORKING states. Otherwise, an error is 
returned.  
A CSR is generated which contains the PEK public key to be signed. The CSR format is identical 
to the SEV certificate with zero signatures. See Appendix C  on page 118 for the certificate format.  
If the PEK_CSR_LEN is too small, the required length is w ritten out to that field and an error is 
returned. Otherwise, the number of bytes written to the buffer are written into PEK_CSR_LEN.  
5.8.2 Parameters  
Table 27 specifies the parameters for the PEK_CSR command.  
Table 27. PEK_CSR Command Buffer  
00h 63:0 In PEK_CSR_PADDR  System physical address of the region to 
output the PEK certificate signing request. 
See Appendix C  for layout.  
08h 31:0 In, Out  PEK_CSR_LEN  Length of the region to output the PEK 
certificate signing request in bytes.  
 
5.8.3 Status Codes  
Table 28 enumerates the possible status codes returned by the PEK_CSR  command.   
Table 28. PEK_CSR Command Status Codes  
INVA LID_LENGTH  A length field is invalid.  
INVALID_PLATFORM_STATE  The platform is not in the PSTATE.INIT or PSTATE.WORKING 
states . 
   
54 Platform Management API   Chapter 5  
 
5.9 PEK_CERT_IMPORT  
During the provisioning process, the pl atform can be joined to a domain using this command in 
conjunction with the PEK_CSR command. The CSR contains the identifying information of this 
platform and the PEK public key. A certificate authority processes the CSR by generating a 
certificate with th e information from the CSR and signing it with its key. This command imports 
the certificate of the PEK and OCA  into the platform.  
Note that this provisioning process should be performed by the platform owner in a trusted 
environment. In an untrusted envir onment —particularly where the x86 software is untrusted —this 
request could be intercepted and replaced with a certificate chain crafted by the attacker.  
5.9.1 Actions  
The platform mu st be self -owned. This requirement ensures that the caller has regenerated the 
PEK via PEK_GEN and therefore PEKs will never be shared by owners.  
The OCA and PEK certificates are validated. Validation involves the following steps:  
• The algorithms of the PEK and OCA must be supported  
• The version of the PEK and OCA certificates must be supported  
• The PEK certificate must match the current PEK  
• The OCA signature on the PEK certificate must be valid  
The OCA certificate and PEK signature are then written into th e platform context as well as to 
non-volatile storage.  
The PDH is regenerated and signed with the new PEK. This action is equivalent to the PDH_GEN 
command.  
5.9.2 Parameters  
Table 29 specifies the parameters for the PEK_CERT_IMPORT  command.  
Table 29. PEK_CERT_IMPORT Command Buffer  
00h 63:0 In PEK_CERT_PADDR  System physical address of the region 
containing the PEK certificate. See 
Appendix C  for layout.  
08h 31:0 In PEK_CERT_LEN  Length of the region containing the PEK 
certificate, in bytes.    
 
 Chapter 5  Platform Management API  55 
 
0Ch 31:0 — — Reserved. Must be zero.  
10h 63:0 In OCA_CERT_PADDR  System physical address of the region 
containing the OCA certificate. See 
Appendix C . 
18h 31:0 In OCA_CERT_LEN  First certificate in the chain. Signed by 
CERT2.  Length of the region containing the 
OCA certificate, in bytes.  
5.9.3 Status Codes  
Table 30 enumerates the possible status codes returned by the PEK_CERT_IMPORT  command.   
Tabl e 30. PEK_CERT_IMPORT Command Status Codes  
INVALID_PLATFORM _STATE  The platform is not in the PSTATE.INIT states.  
INVALID_LENGTH  A buffer length is not correct . 
ALREADY_OWNED  The platform is already owned.  
INVALID_CERTIFICATE  A provided certificate is invalid or the PEK does not match the 
current PEK.  
 
5.10 PDH_GEN  
This command may be used  to re-generate the PDH as often as desired. Note that if other entities 
are using the current PDH to establish keys to encrypt data or provide integrity checking, 
regenerating the PDH will invalidate any ongoing key establishment work.  In this case, the other 
entities must retrieve the new PDH in order to perform key establishment.  
5.10.1  Actions  
returned.  
The PDH key pair is regenerated. The PDH certificate is created and s igned by the PEK. The 
current PDH key pair and certificate are replaced with the new PDH key pair and certificate.    
 
56 Platform Management API   Chapter 5  
 
5.10.2  Parameters  
None.   The CmdBuf_Lo and CmdBuf_Hi mailbox registers are ignored.  
5.10.3  Status Codes 
Table 31 enumerates the possible status codes returned by the PHD_GEN  command.  
Table 31. PDH_GEN Command Status Codes  
Return Value  Reason

returned.  
 
INVAL ID_PLATFORM_STATE  The platform must be in the PSTATE.INIT or 
PSTATE.WORKING states. 
HWERROR_UNSAFE  A hardware condition has occurred a ffecting the platform. It is 
 
5.11 PDH_CERT_EXPORT  
This command is used to to retrieve the PDH and identity of the platform. This information may 
then be exported to remote entities which wish to establish a secure transport context with the 
platform in order to transmit data securely.  
5.11.1  Actions  
returned.  
Exports the following data that can be used by an external party to au thenticate the identity of the 
platform and establish keys:  
• The PDH certificate  
• The CEK certificate  
• The PEK certificate  
• The OCA certificate  
• If the PDH_CERT_LEN or CERT_LEN fields are too small, the required length is 
written out to those fields and an err or is returned. Otherwise, the number of bytes 
written to the buffers are written into PDH_CERT_LEN and CERT_LEN, respectively . 
The platform remains be in the same  state after completion .   
 
 Chapter 5  Platform Management API  57 
 
5.11.2  Parameters  
Table 32 and Table 33 specify the parameters for the PDH_CERT_EXPORT command . 
Table 32. PDH_CERT_EXPORT Command Buffer  
00h 63:0 In PDH_CERT_PADDR  System physical address of the region 
containing the PDH certificate. See 
08h 31:0 In, Out PDH_CERT_LEN  Length of the region containing the 
PDH certificate, in bytes.  
10h 63:0 In CERT S_PADDR  System physical address of the region 
containing the PDH certificate chain. 
See Table 33 for the layout.  
18h 31:0 In, Out CERTS _LEN  Length of the reg ion containing the 
PDH certificate chain, in bytes.  
 
Table 33. PDH_CERT_EXPORT Certificate s Buffer  
Byte Offset   Bits In / Out  Name  Description  
0000h – 0823h   — Out PEK_CERT  The PEK certificate. See Appendix C  for 
layout.  
0824h – 1047h   — Out OCA_CERT  The OCA certificate. See Appendix C  for 
layout.  
1048h – 186Bh   — Out CEK_CERT  The CEK certificate. See Appendix C  for 
layout.  
 
5.11.3  Status Cod es 
Table 34 enumerates the possible status codes returned by the PDH_CERT_EXPORT command.  
Table 34. PDH_CERT_EXPORT Command Status Codes  
states . 
HWERROR_PLATFORM  A hardware condition has occurred affecting the platform. It is 
safe to re -allocate parameter buffers.    
 
58 Platform Management API   Chapter 5  
 
unsafe to re -allocate parameter buf fers. 
 
5.12 DOWNLOAD_FIRMWARE  
The DOWNLOAD_FIRMWARE command is provided to allow operating systems to install SEV 
firmware newer than the currently active SEV firmware.  This command was added in SEV API 
v0.15.  
5.12.1  Actions  
The platform must be in the PSTATE.UNINIT. Otherwise, an error is returned.  
The OS provided firmware image will be validated by the current firmware . If validation fails, an 
error is returned and the current firmware remains active. If validation succeeds, the current 
firmware is rep laced with the OS provided firmware.  The provided  firmware image must be the 
same build or  newer than the current firmware.  The new firmware image will remain active only 
until a system reset.  
5.12.2  Parame ters 
Table 35 specifies the parameters for the DOWNLOAD_FIRMWARE  command.  
Table 35. DOWNLOAD_FIRMWARE  Command Buffer  
00h 63:0 In FW_PADDR  System physical address of the region t hat 
contains a proposed SEV FW image.  This 
region must be 32 -byte aligned.  
08h 31:0 In FW_LEN  Length of the proposed SEV FW image  in 
bytes.  
   
 Chapter 5  Platform Managemen t API  59 
 
5.12.3  Status Codes  
Table 36 enumerates the possible status codes returned by the DOWNLOAD _FIRMWARE  
command.   
Table 36. DOWNLOAD_FIRMWARE  Command Status Codes  
SUCCESS  Successful completion.  
INVALID_LENGTH  The length field is invalid.  
INVALID_PLATFORM_STATE  The platform is not in the PSTATE. UNINIT  state. 
INVALID_ADDRESS  The memory region provided contains invalid physical addresses.  
BAD_SIGNATURE  The proposed FW image has a bad signature.  
INVALID_PARAM  The proposed FW image is not acceptable to the current FW.  
5.13 GET_ID  
The GET_ID command provides a unique ID for the CPU tha t can be used to obtain a certificate 
for the CEK public key that is signed by the ASK. This command was added in SEV API v0.16.  
5.13.1  Actions  
If the value of the ID_LEN field is too small, an INVALID_LENGTH error is returned and the 
minimum required length is written to the field. Otherwise, the ID of the master CPU (Processor 
0) is returned in the area pointed to by ID_PADDR and the length of t he ID value written is 
written to the ID_LEN field. If ID_LEN is precisely two times the minimum length required, and 
the system has 2 CPUs, the ID value for both CPUs is returned in the area pointed to by 
ID_PADDR and the ID_LEN field is updated to reflec t the number of bytes written at 
ID_PADDR.  
5.13.2  Parameters  
Table 37 specifies the parameters for the GET_ID  command.  
Table 37. GET_ID  Command Buffer  
00h 63:0 In ID_PADDR  System physical address of the region t hat 
will be filled with the CPU ID.  
08h 31:0 In, Out  ID_LEN  Length of the region .   
 
60 Platform Management API   Chapter 5  
 
5.13.3  Status Codes  
Table 38 enumerates the possible status codes returned by the GET_ID  command.   
Table 38. GET_ID  Command Status Codes  
 
5.14 NOP  
The NOP  command does nothing . This command was added in SEV API v0. 23 to support 
generation of interrupts from command completion in Ring Buffer mode without advance 
knowledge of the ‘last’ command in a batch.  
5.14.1  Actions  
There are no parameters. The c ommand can return only SUCCESS.  
The platf orm remains in the same state after completion.  
5.14.2  Parameters  
There are no parameters to the NOP command.  
5.14.3  Status Codes  
Table 39 enumerates the possible status codes returned by the NOP  command.   
Table 39: NOP Status Codes  
   
 Chapter 5  Platform Management API  61 
 
5.15 RING_BUFFER  
The RING_BUFFER comman d causes commands to be fetched from a pair of queues , each  
implemented by a pair  of ring buffers to allow parallelization of command creation on the x86 side 
with command execution  by the SEV FW . This command was added in  SEV API v0.2 4. 
5.15.1  Actions  
The platform may be in any state  except UNINIT . The command is valid only as a Mailbox  mode 
command. (That is, a RING_BUFFER command cannot be submitted from a ring buffer. ) The 
RING_BUFFER command will have its status reported via Mailbox m ode. Ring Buffer mode will 
be active only after the x86 writes the RBCtl register with a value meeting the requirements 
describ ed in 4.2. 
Details of the usage of ring buffers are detailed in  Section  4.2, Ring Buffer Mo de. 
5.15.2  Parameters  
Table 40 specifies the parameters for the RING_BUFFER  command.  
Table 40. RING_BUFFER  Command Buffer  
Byte Offset  Bit(s) In / Out  Name  Description  
00h 63:0 In QLoCmdPtr  System physical address of the 4K a ligned 
region to be used for the low priority queue’s 
CmdPtr ring buffer.  
08h 63:0 In QLoStatVal  System physical address of the 4K aligned 
StatVal ring buffer.  
10h 63:0 In QHiCmdPtr  System physical address of the 4K aligned

10h 63:0 In QHiCmdPtr  System physical address of the 4K aligned 
region to be used for the high priority queue’s 
18h 63:0 In QHiStatVal  System physical address of the 4K aligned 
20h 7:0 In QLoSize  Size of the low priority queue in 4K pages. 
Must be 1.  
21h 7:0 In QHiSize  Size of the high priority queue in 4K pages. 
Must be  0 or 1. If 0, all other QHi values are 
ignored.  
22h 15:0 In QLoThreshold  Queue size , in entries,  below which an 
interrupt may optionally be generated.    
 
62 Platform Management API   Chapter 5  
 
24h 15:0 In QHiThreshold  Queue size, in entries, below which an 
interrupt may optionally be generated.  
26h 0 In IntOnEmpty  Unconditionally interrupt when both queues 
are found empty.  
15:1 In - Reserved . Must be 0.  
 
5.15.3  Status Codes  
Table 41 enumerates the possible status codes returned by the RING_BUFFER  command.   
Table 41. RING_BUFFER Status Codes  
INVALID_PLATFORM_STATE  The platform state is UNINIT.  
INVALID_PARAM  A parameter is invalid.  
INVALID_COMMAND  RING_BUFFER is only valid in Mailbox mode.  
   
55766  Rev. 3.24 April 2020    Secure Enc rypted Virtualization API  
 
 Chapter 6  Guest Management API  63 
 
Chapter 6  Guest Management API  
This chapter describes the management of guest contexts throughout the guest lifecycle.  
6.1 Overview  
This chapter  describes the SEV context of an SEV -enabled guest.  
6.1.1 Guest Context  
The SEV firmware maintains guest contexts throughout the lifetime of the platform. The guest 
context contains data and metadata necessary to implement the SEV API specific to a guest.  
Table 42. Guest Context (GCTX) F ields  
STATE  The current state of this guest in the GSTATE finite state machine  
HANDLE  The handle of this guest  
ASID  The ASID currently associate with this guest.  
ACTIVE  Flag describing whether this guest is currently active  
POLICY  This guest’s policy  
VEK  The memory encryption key of the guest  
NONCE  The trusted channel nonce currently associated with this guest  
MS The master secret current associated with this guest  
TEK  The transport encryption key currently associated with this guest  
TIK The transport integrity key currently associated with this guest  
LD The launch digest context for this guest  
A guest context is denoted GCTX. The GCTX fields are referenced as GCTX.<FIELD>. The 
GCTX prefix is omitted if it’s unnecessary in context.  
Table 43. GSTATE Finite State Machine  
State  Value  Description  Allowed Guest Commands  
UNINIT  0h The guest is uninitialized.  LAUNCH_START, 
RECEIVE_START  
LUPDATE  1h The guest is currently being 
launched and plaintext data and 
VMCB save areas are being 
imported.  LAUNCH_UPDATE_DATA, 
LAUNCH_UPDATE_VMSA, 
LAUNCH_MEASURE, ACTIVATE, 
DEACTIVATE, DECOMMISSION, 
GUEST_STATUS  
   
64 Guest Management API   Chapte r 6 
 
Table 43. GSTATE Finite State Machine  (Continued)  
LSECRET  2h The guest is currently being launched 
and ciphertext data are being 
imported.  LAUNCH_SECRET,  
LAUNCH_FINISH, ACTIVATE, 
GUEST_STATUS , ATTESTATION  
RUNNING  3h The guest is fully launched or 
migrated in, and not being migrated 
out to another machine.  ACTIVATE, DEACTIVATE, 
DECOMMISSION, SEND_START, 
SUPDATE  4h The guest is currently being migrated 
out to another machine.  SEND_UPDATE_DATA, 
SEND_UPDATE_VMSA, 
SEND_FINISH, ACTIVATE, 
GUEST_STATUS , 
ATTESTATION, SEND_CANCEL  
RUPDATE  5h The guest is currently being migrated 
from anoth er machine.  RECEIVE_UPDATE_DATA, 
RECEIVE_UPDATE_VMSA, 
RECEIVE_FINISH, ACTIVATE, 
SENT  6h The guest has been sent to another 
machine.  DEACTIVATE, DECOMMISSION  
Each SEV guest managed by the SEV firmware traverses a finite state machine during operation. 
The firmware will only execute certain commands in each guest state.  
The guest finite state machine is denoted GSTATE. The GSTATE states are referenced as 
GSTATE.<STATE>. For instance, the uninitialized st ate is denoted GSTATE.UNINIT.  
6.1.2 Activation and Deactivation  
The number of ASIDs that can be associated with a VEK and used with SEV are limited. The limit 
is implementation specific and can be retrieved via CPUID Fn8000_001F[ECX]. To allow for the 
execution of a larger number of guests, the SEV firmware provides the ability to activate and 
deactivate guests.  
6.2 LAUNCH_START  
This command is used to bootstrap a guest by encrypting its memory with a new VEK. This 
command creates a guest context managed by the SEV f irmware which can then be referred to by 
the handle passed out to the caller.    
 
 Chapter 6  Guest Management API  65 
 
6.2.1 Actions  
A new guest context is created and assigned to an available guest handle.  
If the HANDLE field is zero, a new VEK is generated for this guest. If the HANDLE field is non -
zero, the following checks are performed:  
• HANDLE is a valid guest  
• GUESTS[HANDLE].POLICY is equal to the POLICY field  
• POLICY.NOKS is zero  
If the above checks pass, then the VEK from the guest referred to by HANDLE is copied into the 
new guest context.  
The handle of the new guest is written to the HANDLE field.  
The launch digest stored in GCTX.LD field is initialized.  
If POLICY.ES is set and the platform is configured with SEV -ES, then SEV -ES is enabled. If 
POLICY.ES is set and the platform is n ot configured with SEV -ES, an error is returned. 
Otherwise, SEV -ES is disabled.  
A version check is performed to ensure that the API version implemented on the platform provides 
the proper functionality requested by the initiator of the guest VM.  The major  API version of this 
platform must be greater than the guest’s POLICY.API_MAJOR field value, or the major API 
version is equal to POLICY.API_MAJOR, and the minor API version of this platform is greater 
than or equal to POLICY.API_MINOR. If all of these con ditions are not met then an error is 
returned.  
If DH_CERT_PADDR is equal to 0h, then the DH_CERT_LEN, SESSION_PADDR, and 
SESSION_LEN fields are ignored. The subsequent launch commands will use 0h for both the 
TEK and TIK.  
After successful completion of this command, the guest is transitioned to the GSTATE.LUPDATE 
state.  
The platform transitions to the PSTATE.WORKING state.    
 
66 Guest Management API   Chapter 6  
 
6.2.2 Parameters  
Table 44 and Table 45 specify the parameters for the LAUNCH_START  command.  
Table 44. LAUNCH_START Command Buffer  
Byte Off set Bits In / Out  Name  Description  
00h 31:0 In, Out  HANDLE  Guest handle.  
04h 31:0 In POLICY  Guest policy.  
08h 63:0 In DH_CERT_PADDR  System physical address of the region 
containing the guest owner DH certificate. 
See Appendix C  for the layout.  
10h 31:0 In DH_CERT_LEN  Length of the region containing the guest 
owner DH certificate, in bytes.  
14h 31:0 – – Reserved. Must be zero.  
18h 63:0 In SESSION_PADDR  System physical address of the region 
containing the session parameters.  
20h 31:0 In SESSION_LEN  Length of the region containing the session 
parameters, in bytes.  
Table 45. LAUNCH_START Session Data Buffer  
Byte Offset  Bits In / Out Name  Description  
00h 127:0  In NONCE  Session nonce.  
10h 255:0  In WRAP_TK  The TEK and TIK  concatenated and 
encrypted with the KEK . 
30h 127:0  In WRAP_IV  IV for WRAP _TK encryption . 
40h 255:0  In WRAP_MAC  HMAC for  WRAP_TK  using K IK. 
60h 255:0  In POLICY_MAC  HMAC for POLICY using TIK . 
6.2.3 Status Cod es 
Table 46 enumerates the possible status codes returned by the LAUNCH_START command . 
Table 46. LAUNCH_START Status Codes  
INVALID_PLATFORM_STATE  The platform is not in PSTATE.INIT or WORKING state.  
   
 Chapter 6  Guest Management API  67 
 
Table 46. LAUNCH_START Status Codes  (Continued)  
INVALID_GUEST  The guest handle is invalid.  
POLICY_FAILURE  The guest policy was violated.  
BAD_MEASUREMENT  Failed to verify the integrity of a field covered by a MAC . 
INVALID_ADDRESS  A memory region provided contains invalid physical addresses.

UNSUPPORTED  SEV -ES has not been configured.  
HWERROR_PLATFORM  A hardware condition has occurred affecting the platform. It is safe to 
 
6.3 LAUNCH_UPDATE _DATA  
This command is used to encrypt guest data with its VEK.  
6.3.1 Actions  
The platform must be in the PSTATE.WORKING state.  
The guest must be in the GSTATE.LUPDATE state. The guest must be activated with an ASID 
using the ACTIVATE command.  
The GCTX.LD is updated with the plaintext contents of the memory region point ed to by 
PADDR. The plaintext context is then encrypted with the guest’s VEK in place.  
The guest remains in the same state after completion.  
6.3.2 Parameters  
Table 47 specifies  the parameters for the LAUNCH_UPDATE_DATA command . 
Table 47. LAUNCH_UPDATE_DATA Command Buffer  
Byte 
Offset  Bits In / Out  Name  Description  
00h 31:0 In HANDLE  Guest handle  
04h 31:0 - - Reserved. Must be zero.  
08h 63:0 In PADDR  System physical address of the data to be encrypted. 
Must be 16 B aligned.    
 
68 Guest Management API   Chapte r 6 
 
Byte 
10h 31:0 In LENGTH  Length of the data to be encrypted. Must be a multiple 
of 16 B.  
 
6.3.3 Status Cod es 
Table 48 enumerates the possible status codes returned by the LAUNCH_UPDATE_DATA 
command . 
Table 48. LAUNCH_UPDATE_DATA Status Codes  
Return Val ue Reason  
INVALID_PLATFORM_STATE  The platform is not in the PSTATE.WORKING state.  
INVALID_GUEST_STATE  The guest state is not in the GSTATE.LUPDATE state.  
INACTIVE  The guest is inactive.  
 
6.4 LAUNCH_UPDATE_VMSA  
This command is used to encrypt the guest VMCB save area with its VEK. This command  is only 
allowed when SEV -ES is enabled for this guest and when SEV -ES is configured for the platform.  
6.4.1 Actions  
using t he ACTIVATE command.  
The GCTX.LD is updated with the plaintext contents of the VMCB save area pointed to by 
PADDR. The VMCB save area is prepared for SEV -ES usage and is then encrypted with the 
guest’s VEK in place.    
 
 Chapter 6  Guest Management API  69 
 
The platform remains in the same state a fter completion.  
6.4.2 Parameters  
Table 49 specifies  the parameters for the LAUNCH_UPDATE_VMSA command.  
Table 49. LAUNCH_UPDATE_VMSA Command Buffer  
00h 31:0 In HANDLE  Guest handle.  
Must be 16 B aligned.  
10h 31:0 In LENGTH  Length of the data to be encrypted. Must be 4096 B.  
6.4.3 Status Codes  
Table 50 enumerates the possible status codes returned by the LAUNCH_UPDATE_VMSA 
command  
Table 50. LAUNCH_UPDATE_VMSA Status Codes  
Return Valu e Reason  
INVALID_LENGTH  A buffer length is not correct  
   
70 Guest Management API   Chapter 6  
 
6.5 LAUNCH_MEASURE  
This command returns the measurement of the launched guest’s memory pages and VMCB save 
areas (if ES is enabled). The measurement is keyed with the TIK so the guest owner can use the 
measurement to verify that the guest was properly launched without tampering.  
6.5.1 Actions  
The platform must be in the  PSTATE.WORKING state.  
The guest must be in the GSTATE.LUPDATE state.  
If the MEASURE_LEN is too small, the required length is written out to that field and an error is 
returned. Otherwise, the number of bytes written to the buffer are written into MEASURE_LEN.  
GCTX.LD is finalized, producing the hash digest of all plaintext  data imported into the guest.  
The launch measurement is calculated as:  
 HMAC( 0x04 || API_MAJOR || API_MINOR || BUILD || GCTX.POLICY || GCTX.LD  || 
MNONCE ; GCTX.TIK)  
where “||” represents concatenation. The launch measurement is written into the MEASURE fie ld. 
The firmware generates a random MNONCE.  
The guest transitions to the GSTATE.LSECRET state.  
6.5.2 Parameters  
Table 51 and Table 52 specify the parameters for the LAUNCH_MEASURE command.  
Table 51. LAUNCH_MEASURE Command Buffer  
08h 63:0 In MEASURE_PAD
DR System physical address of the region 
containing the launch measurement. See  Table 
52 for layout.  
10h 31:0 In, Out  MEASURE_LEN  Length of the region containing the launch 
measurement, in bytes.    
 
 Chapter 6  Guest Management API  71 
 
Table 52. LAUNCH_MEASURE Measurement Buffer  
00h 255:0  Out MEASURE  Measurement of the launched guest  
20h 127:0  Out MNONCE  Firmware -generated random nonce  
 
6.5.3 Status Codes  
Table 53 enumerates the possible status codes returned by the LAUNCH_MEASURE command . 
Table 53. LAUNCH_MEASURE Status Codes  
INVALID_PLATFORM_STATE  The platform is not in the PSTATE.WORKING state  
INVALID_GUEST_STATE  The guest state is not in the GSTATE.LUPDATE state  
INVALID_GUEST  The guest handle is invalid  
HWERROR_UNSAFE  A hardware condition has occurred affectin g the platform. It is 
 
6.6 LAUNCH_SECRET  
This command is used by the guest owner to inject a secret into the guest. This can be done after 
the launch measurement is retrieved and verified by the guest owner.  
6.6.1 Actions  
The guest must be in the GSTAT E.LSECRET state.  
Before all other processing, the MAC field is verified. The MAC is calculated as follows:  
 HMAC(0x01 || FLAGS || IV || GUEST_LENGTH || TRANS_LENGTH || DATA  || 
MEASURE ; GCTX.TIK)    
 
72 Guest Management API   Chapte r 6 
 
Where “||” represents concatenation, FLAGS is the full 32 -bit FLAGS field, DATA is ciphertext 
pointed to by TRANS_PADDR , and MEASURE is the value returned by the firmware in the 
LAUNCH_MEASURE command . 
The data pointed to by TRANS_PADDR is decrypted with GCTX.TEK. If 
FLAGS.COMPRESSED is set to 1, then the resulting plaintext is then decompressed. The result is 
then written to GUEST_PADDR, encrypted with the guest’s VEK.  
The platform remains in the same state after completion.  The guest remains in the same state after 
6.6.2 Parameters  
Table  54 and Table 55 specify the parameters for the  LAUNCH_SECRET  command.  
Table 54. LAUNCH_SECRET Command Buffer  
Byte 
08h 63:0 In HDR_PADDR  System physical address of the region 
containing the packet header. See Table 55 for 
the layout.  
10h 31:0 In HDR_LEN  Length of the region containing the packet 
heade r in bytes.  
14h 31:0 - - Reserved. Must be zero.

Byte 
14h 31:0 - - Reserved. Must be zero.  
18h 63:0 In GUEST_PADDR  System physical of the guest memory region. 
20h 31:0 In GUEST_LENGTH  Length of guest memory region. Must be a 
multiple of 16 B and no more than 16 kB.  
24h 31:0 - -  
28h 63:0 In TRANS_PADDR  System physical address of the transport 
memory buffer.  
30h 31:0 In TRANS_LENGTH  Length of the transport memory buffer.  
Table 55. LAUNCH_SECRET Packet Header Buffer  
00h 0 In FLAGS.COMPRESSED  If set, data is compressed.  
31:1 - - Reserved. Must be zero.  
04h 127:0  In IV Initialization vector.  
14h 255:0  In MAC  Integrity protection MAC.    
 
 Chapter 6  Guest Management API  73 
 
6.6.3 Status Codes  
Table 56 enumerates the possible status codes returned by the LAUNCH_SECRET command  
Table 56. LAUNCH_SECRET Status Codes  
INVALID_GUEST_STATE  The guest state is not in the GSTATE.LSECRET state.  
INVALID_GU EST The guest handle is invalid.  
BAD_MEASUREMENT  The measurement of the secret is invalid.  
 
6.7 LAUNCH_FINISH  
After the launch flow is completed, this command is used to transition the guest into a state ready 
to be run.  
6.7.1 Actions  
The guest must be in the GSTATE.LSECRET state.  
The following fields of the guest context are zeroed:  
• GCTX.TEK  
• GCTX.TIK  
• GCTX.MS  
• GCTX.NONCE  
• GCTX.LD  
The platform remains in the same state after completion.    
 
74 Guest Management API   Chapter 6  
 
The guest transitions to the GSTATE.RUNNING state.  
6.7.2 Parameters  
Table 57 specifies  the parameters for the LAUNCH_FINISH command.  
Table 57. LAUNCH_FINISH Command Buffer  
 
6.7.3 Status Codes  
Table 58 enumerates the possible status codes returned by the LAUNCH_FINISH command . 
Table 58. LAUNCH_FINISH Status Codes  
INVALID_ADDRESS  A memory region provided contains inv alid physical addresses.  
unsafe to re-allocate parameter buffers.  
 
6.8 ATTESTATON  
This command is used to generate an attestation r eport containing  the SHA -256 digest of the guest 
memory and VMSA passed through the LAUNCH_UPDATE_* commands  and signed with the 
PEK . This digest should match the digest used by  the guest owner with LAUNCH_MEASURE.  A 
random MNONCE is provided as input and placed in the report to provide protection.  
6.8.1 Actions  
The guest must be in the GSTATE.LSECRET, GSTATE.RUNNING, GSTATE.SUPDATE, or 
GSTATE.SENT state.    
 
 Chapter 6  Guest Management API  75 
 
The LENGTH must be large enough to hold the report or INVAL ID_LENGTH will b e returned 
and the required length will be placed in the LENGTH  field of the Command Buffer.  
The firmware will sign the report buffer starting at offset 0h and up to but not including the 
SIG_USAGE parameter. The value of SIG_USAGE will be PEK, which is de fined in  Table 113. 
The value of SIG_ALGO will be ECDSA with SHA -256, which is defined  in Table 114. The 
length of the report will be written to the LENGTH field of the Command Buffer.  
6.8.2 Parameters  
Table 59 specifies the parameters for the  ATTESTATION command.  
Table 59. ATTESTATION Command Buffer  
08h 63:0 In PADDR  System physical address of the attestation report . 
10h 127:0 In MNONCE  Report nonce.  
20h 31:0 In/Out  LENGTH  Input : length of area provided for the attestation 
report.  
Output: length of area used by the attestation report.  
 
Table 60. Attestation Report Buffer  
Byte Offset  Bits Name  Description  
00h 127:0 MNONCE  Nonce  from Command Buffer.  
10h 255:0  LAUNCH_DIGEST  SHA -256 digest of launched guest.  
30h 31:0 POLICY  Policy the guest was launched with  
34h 31:0 SIG_USAGE  Key usage of SIG1 signing key.  
38h 31:0 SIG_ALGO  Signature algorithm.  
3Ch 31:0 - Reserved.  
40h-CFh  SIG1  Signature.  
 
6.8.3 Status Codes  
Table 61 enumerates the possible status codes returned by the  ATTESTATION command.    
 
76 Guest Management API   Chapter 6  
 
Table 61. ATTESATION Status Codes  
INVALID_GUEST_STATE  The guest state is not in the GSTATE.LSECRET , RUNNING, or 
SUPDATE  state.  
INVALID_LENGTH  The length of the buffer for the Attestation report is too small.  
 
6.9 SEND_START  
This command is used to export a guest from one platform to another. It can be used for saving a 
guest to disk to be resumed later, or it can be used to migrate a guest across the network to a 
receiving platform.  
6.9.1 Actions  
The guest must be in the GSTATE.RUNNING state.  
GCTX .POLICY.NOSEND must be zero. Otherwise, an error is  returned.  
If GCTX.POLICY.SEV is 1, the PDH, PEK, CEK, ASK, and ARK certificates are validated.  
A version check is performed to ensure that the API version implemented on the receiving 
platform provides the proper functionality requested by the initiator of the guest. The receiving 
platform API version is read from the PEK certificate. The major API version of the receiving 
version is equal to POLICY.API_MAJO R, and the minor API version of the receiving platform is 
greater than or equal to POLICY.API_MINOR. If all of these conditions are not met then an error 
is returned.  
If GCTX.POLICY.SEV is 0, this certificate chain is ignored and no version check is perfor med.    
Version 0 .24 
 
 Chapter 6  Guest Management API  77 
 
If GCTX.POLICY.DOMAIN is 1, the PDH -PEK -OCA are validated. If 
GCTX.POLICY.DOMAIN is 0, this certificate chain is ignored.  
When required by the guest policy, the PDH, PEK, OCA, and CEK certificates are validated 
according to Appendix C  on page 118. The ASK and ARK certificates are validated according to 
Appendix B  on page 116.  
A fresh nonce is generated an d written into the NONCE field. The master secret is calculated with 
NONCE and PDH_CERT fields and the PCTX.PDH private key according to the key 
establishment protocol specified in Chapter 2  on page 25. Fresh TEK and TIK transport keys are 
generated. The transport keys are then wrapped according to Chapter 2  on page 25, and the output 
is placed in the WRAP_TK, WRAP_IV, and WRAP_MAC fields.  
GCTX.POLICY is written to the POLICY field and a MAC of GCTX.POLICY is calculated, 
keyed with TIK. The MAC is written to the POLICY_MAC field.  
The guest transit ions to the GSTATE.SUPDATE state.  
6.9.2 Parameters  
Table 62, Table 63, Table 64 and Table 65 specify the parameters for the SEND_START 
command.  
Table 62. SEND_START Command Buffer  
00h 31:0 In HANDLE  Guest handle .

command.  
00h 31:0 In HANDLE  Guest handle . 
04h 31:0 Out POLICY  Guest policy  
08h 63:0 In PDH_CERT_PADDR  System physical address of the region 
Appendix C  for the layout.  
   
78 Guest Management API   Chapter 6  
 
Table 62. SEND_START Command Buffer  (Continued)  
10h 31:0 In PDH_CERT_LEN  Length of the region containing the PDH 
certificate in bytes.  
14h - - - Reserved. Must be zero.  
18h 63:0 In PLAT_CERTS_PADDR  System physical address of the region 
containing the platform certificates.  See 
Table 63 for the layout.  
20h 31:0 In PLAT_CERTS_LEN  Length of the region containing the 
platform certificate in bytes.  
24h - - - Reserved. Must be zero . 
28h 63:0 In AMD_CERTS_PADDR  System physical address of the region 
containing the AMD certificates.  See 
Table 64 for the layout.  
30h 31:0 In AMD_CERTS_LEN  Length of the region containing the AMD 
certificates in bytes.  
34h - - - Reserved. Must be zero.  
38h 63:0 In SESSION_PADDR  System physical address of the region 
containing the session data. Table 65 for 
40h 31:0 In, Out  SESSION_LEN  Length of the region containing the 
session data in bytes.  
 
Table 63. SEND_START Platform Certificates Buffer  
0000h – 0823h  - In PEK_CERT  The PEK certificate. See Appendix C  for the 
layout.  
0824h – 1047h  - In OCA_CERT  The OCA certificate. See Appendix C  for the 
layout.  
1048h – 186Bh  - In CEK_CERT  The CEK certificate. See Appendix C  for the 
layout.  
 
Table 64. SEND_START AMD Certificates Buffer  
Variable  - In ASK_CERT  The ASK certificate. See Appendix B  for the layout.  
Variable  - In ARK_CERT  The ARK certificate. See Appendix B  for the  layout.  
   
 Chapter 6  Guest Management API  79 
 
Table 65. SEND_START Session Data Buffer  
Byte Offset  Bits In / 
Out Name  Description  
00h 127:0  Out NONCE  Session nonce.  
10h 255:0  Out WRAP_TK  The TEK and TIK  concatenated and encrypted 
with the KEK.  
30h 127:0  Out WRAP_IV  IV for WRAP_TK encryption . 
40h 255:0  Out WRAP_MAC  HMAC for  WRAP_TK using KIK.  
60h 255:0  Out POLICY_MAC  HMAC for POLICY using TIK . 
 
6.9.3 Status Cod es 
Table 66 enumerates the possible status codes returned by the SEND _START command . 
Table 66. SEND_START Status Codes  
INVALID_GUEST_STATE  The guest state is not in the GSTATE.RUNNING state  
INVALID_CERTIFICATE  A certificate chain is not valid  
BAD_SIGNATURE  A signature on the certificates is incorrect  
 
6.10 SEND_UPDATE _DATA  
This command is used to export guest memory reg ions to another platform.  
6.10.1  Actions  
The guest must be in the GSTATE.SUPDATE state.    
 
80 Guest Management API   Chapter 6  
 
If the HDR_LEN is too small, the required length is written out to that field and an error is 
returned. Otherwise, the number of bytes written to the buffer are written into HDR_LEN.  
If FLAGS.COMPRESSED is 1, the data pointed to by GUEST_PADDR will first be compressed 
before encryption and integrity protection. If FLAGS.COMPRESSED is 0, no compression is 
performed.  
A fresh IV is generated and written to the IV field. The data pointed to by GUEST_PADDR is 
encrypted with the GCTX.TEK. The result is then writ ten to the TRANS_PADDR field. If the 
input TRANS_LENGTH field is greater than output length of the compressed and encrypted 
plaintext, the new length is written into the TRANS_LENGTH field. If TRANS_LENGTH is less 
than the output length of the compressed a nd encrypted plaintext, an error is returned.  
A MAC is computed to integrity protect the data. The MAC is calculated as follows:  
 HMAC(0x02 || FLAGS || IV || GUEST_LENGTH || TRANS_LENGTH || DATA; 
GCTX.TIK)  
Where “||” represents concatenation, FLAGS is the full 32 -bit FLAGS field, and DATA is 
ciphertext pointed to by TRANS_PADDR. TRANS_LENGTH is the new length written out to the 
TRANS_LENGTH field. The MAC is written out to the MAC field.  
The guest rem ains in the same state after completion.  
6.10.2  Parameters  
Table 67  specifies  the parameters for the SEND_UPDATE_DATA command.  
Table 67. SEND_UPDATE_DATA Command Buffer  
containing the packet header.  
10h 31:0 In, Out  HDR_LEN  Length of the region containing the packet 
header in bytes.  
14h 31:0 - - Reserved. Must be zero  
Must be 16 B aligned  with the C -bit set.  
   
 Chapter 6  Guest Management API  81 
 
Table 67. SEND_UPDATE_DATA Command Buffer  (Continued)  
24h 31:0 - -  
30h 31:0 In, Out  TRANS_LENGTH  Length of the transport memory buffer.  
 
Table 68. SEND_UPDATE_DATA  Packet Header Buffer  
00h 0 Out FLAGS.COMPRESSED  If set, data is compressed.  
04h 127:0  Out IV Initialization vector.  
14h 255:0  Out MAC  Integrity protection MAC.  
 
6.10.3  Status Cod es 
Table 69 enumerates the possible status codes returned by the SEND_UPDATE_DATA 
command . 
Table 69. SEND_UPDATE_DATA Status Codes  
INVALID_GUEST_STATE  The guest state is not in the GSTATE.SUPDATE state.  
unsafe to re -allocate parameter buffers.    
 
82 Guest Management API   Chapter 6  
 
6.11 SEND_UPDATE_VMSA  
This command is used to export guest VMCB save areas to another platform.  
6.11.1  Actions  
The guest must be in the GSTATE.SUPDATE state.  
returned. Otherwise, the number of bytes written to the b uffer are written into HDR_LEN.  
A fresh IV is generated and written to  the IV field. The data pointed to by GUEST_PADDR is 
encrypted with the GCTX.TEK. The result is then written to the TRANS_PADDR field. If the 
plaintext, the new length i s written into the TRANS_LENGTH field. If TRANS_LENGTH is less 
than the output length of the compressed and encrypted plaintext, an error is returned.  
 HMAC(0x03 || FLAGS ||  IV || GUEST_LENGTH || TRANS_LENGTH || DATA; 
GCTX.TIK)  
TRANS_LENGTH field. The MA C is written out to the MAC field.  
The guest remains in the same state after completion.

GCTX.TIK)  
The vCPU represented by this VMSA should no longer be run by the hypervisor. Future versions 
of firmware may e nforce this constraint.    
 
 Chapter 6  Guest Management API  83 
 
6.11.2  Parameters  
Table 70 and Table 71 specifies the parameters for the SEND_UPDATE_VMSA command.  
Table 70. SEND_UPDATE_VMSA Command Buffer  
Byte 
24h 31:0 - -  
 
Table 71. SEND_UPDATE_VMSA Packet Header Buffer  
14h 255:0  Out MAC  Integrity protection MAC.    
 
84 Guest Management API   Chapter 6  
 
6.11.3  Status Codes  
Table 72 enumerates the possible status codes returned by the SEND_UPDATE_VMSA 
command.  
Table 72. SEND_UPDATE_VMSA Status Codes  
UNSUPPORTED  SEV -ES is not configured.  
 
6.12 SEND_FINISH  
This command finalizes the send operational  flow.  
6.12.1  Actions  
• GCTX.TEK  
• GCTX.TIK  
• GCTX.MS  
The guest transitions to the GSTATE. SENT  state.    
 
 Chapter 6  Guest Management API  85 
 
6.12.2  Parameters  
Table 73 specif ies the parameters for the SEND_FINISH command.  
Table 73. SEND_FINISH Command Buffer  
6.12.3  Status Codes  
Table 74 enumerates the possible status codes returned by the SEND_FINISH command.  
Table 74. SEND_FINISH Status Codes  
INVALI D_PLATFORM_STATE  The platform is not in the PSTATE.WORKING state  
INVALID_GUEST_STATE  The guest state is not in the GSTATE.SUPDATE state  
6.13 SEND_CANCEL  
This command cancels  the send operational flow.  
6.13.1  Actions  
• GCTX.TEK  
• GCTX.TIK  
• GCTX.MS  
 
86 Guest Management API   Chapter 6  
 
The guest transitions to the GSTATE. RUNNING  state.  
6.13.2  Parameters  
Table 75 specif ies the parameters for the SEND_ CANCEL  command.  
Table 75. SEND_ CANCEL  Command Buffer  
6.13.3  Status Codes  
Table 76 enumerates the possible status codes returned by the SEND_ CANCEL  command.  
Table 76. SEND_ CANCEL  Status Codes  
INVALID_PLATFORM_STATE  The platform is not in the PSTATE.WORKING state . 
INVALID_GUEST_STATE  The guest state is not in the GSTATE.SUPDATE state . 
INVALID_GUEST  The guest handle is invalid . 
INVALID_ADDRESS  A memory region provided contains invalid physical addresses . 
HWERROR_UNSAFE  A hardware condition has occurr ed affecting the platform. It is 
 
6.14 RECEIVE_START  
This command is used to import a guest from one platform to another. It can be used for restoring 
a guest from disk, or it can be used to migrate a guest across the network from a sending platform.  
6.14.1  Actions  
The platform must not be in the PSTATE. UNINIT  state.  
The MAC of GCTX.POLICY is calculated, keyed with TIK. The MAC is compared to the 
POL ICY_MAC field to verify the integrity of the guest policy.    
 
 Chapter 6  Guest Management API  87 
 
• GUESTS[HANDLE].POLICY is equal to th e POLICY field  
• The MAC of the POLICY is valid  
The master secre t is calculated with NONCE and PDH_CERT fields and the PCTX.PDH private 
key according to the key establishment protocol specified in Chapter 2  on page 25. The transport 
keys in the WRAPPED_TK field are then unwrapped according to Chapter 2  on page 25 using the 
WRAP_IV and WRAP_MAC fields as the IV and MAC parameters, respectively.  
A version check is performed to ensure that the API version implemented on the plat form provides 
the proper functionality requested by the initiator of the guest.  The major API version of this 
platform must be greater than the guest's POLICY.API_MAJOR field value, or the major API 
than or equal to POLICY.API_MINOR. If all of these conditions are not met then an error is 
returned.  
POLICY.ES is set and the pla tform is not configured with SEV -ES, an error is returned. 
The guest transitions to the GSTATE.RUPDATE state.  
6.14.2  Parameters  
Table 77 and Table 78 specify the parameters for the RECEIVE_START command.  
Table 77. RECEIVE _START Command Buffer  
00h 31:0 In, Out  HANDLE  Guest handle  
04h 31:0 In POLICY  Guest policy  
containing the PDH certificate.  
14h 31:0 - - Reserved. Must be zero    
 
88 Guest Management API   Chapter 6  
 
containing the session data.  
data in bytes.  
 
Table 78. RECEIVE_START Session Data Buffer  
10h 255:0  In WRAP_TK  The TEK and TIK  concatenated and encrypted 
30h 127:0  In WRAP_IV  IV for WRAP_TK encryption . 
40h 255:0  In WRAP_MAC  HMAC for  WRAP_TK using KIK.  
 
6.14.3  Status Cod es

6.14.3  Status Cod es 
Table 79 enumerates the possible status codes returned by the RECEIVE_START command.  
Table 79. RECEIVE_START Status Codes  
POLICY_FAILURE  A guest policy requirement cannot be honored.  
BAD_MEASUREMENT  The measurement of the wrapped key or policy is invalid  
UNSUPPORTED  SEV -ES has not been configured  
   
 Chapter 6  Guest Management API  89 
 
6.15 RECEIVE_UPDATE_DATA  
This command is used to import guest memory from a sending  platform.   
6.15.1  Actions  
The guest must be in the GSTATE.RUPDATE state.  
A MAC is computed to verify the integrity of the data area.  The MAC is calculated as follows:  
 HMAC(0x02  || FLAGS || IV || GUEST_LENGTH || TRANS_LENGTH || DATA; 
GCTX.TIK)  
Where “||” represents concatenation, FLAGS is the full 32 -bit FLAGS field, and DATA i s 
ciphertext pointed to by TRANS_PADDR. The MAC is compared against the MAC field which 
must be equal.  
The ciphertext data pointed to by TRANS_PADDR is decrypted with the GCTX.TEK and the IV 
field. If FLAGS.COMPRESSED is 1, the resulting plaintext data wil l be decompressed. If 
FLAGS.COMPRESSED is 0, no compression is performed. The result is then encrypted with 
GCTX.VEK and written to the memory pointed to by GUEST_PADDR field.  
The guest remains in t he same state after completion.    
 
90 Guest Management API   Chapter 6  
 
6.15.2  Parameters  
Table 80 and Table 81 specify the parameters for the RECEIVE_UPDATE_ DATA  command.  
Table 80. RECEIVE_UPDATE_ DATA  Command Buffer  
18h 63:0 In GUEST_PADDR  System physical address of the guest  memory 
region . Must be 16 B aligned.  
24h 31:0 - - Reserved. Must be zero.  
 
Table 81. RECEIVE_UPDATE_ DATA  Packet Header Buffer  
00h 0 In FLAGS.COMPRESSED  If set, data is compressed . 
04h 127:0  In IV Initialization vector . 
14h 255:0  In MAC  Integrity protection MAC . 
 
6.15.3  Status Codes  
Table 82 enumerates the possible status codes returned by the RECEIVE_UPDATE _DATA  
command.    
 
 Chapter 6  Guest Management API  91 
 
Table 82. RECEIVE_UPDATE_DATA  Status Codes  
INVALID_GUEST_STATE  The guest state is not in the GSTATE. RUPDATE  state.  
INACTIV E The guest is inactive.  
HWERROR_PLATFORM  A hardware con dition has occurred affecting the platform. It is safe 
 
6.16 RECEIVE_UPDATE_V MSA 
This command is used to import a VMCB save area from another platform.   
6.16.1  Actions  
A MAC is computed to verify the integrity of the VMCB save area.  The MAC is calculated as 
follows:  
 HMAC(0x03  || FLAGS || IV || GUEST_LENGTH || TRANS_LENGTH || DATA; 
GCTX.TIK)  
must be  equal.  
field. If FLAGS.COMPRESSED is 1, the resulting plaintext data will be decompressed. If 
FLAGS.COMPRESSED is 0, no compression is performed. The result is then en crypted with 
GCTX.VEK and written to the memory pointed to by GUEST_PADDR field.    
 
92 Guest Management API   Chapter 6  
 
6.16.2  Parameters  
Table 83 and Table 84 specify the parameters for the RECEIVE_UPDATE_ VMSA  command.  
Table 83. RECEIVE_UPDATE_ VMSA  Command Buffer  
18h 63:0 In GUEST_PADDR  System physical of the VMCB save area . 
 
Table 84. RECEIVE_UPDATE_ VMSA  Packet Header Buffer  
 
6.16.3  Status Cod es 
Table 85 enumerates the possible status codes returned by the RECEIVE_UPDATE _VMSA  
command.    
55766  Rev. 3.24 April 2020    Secure Encrypted Virtualization API 
 
 Chapter 6  Guest Management API  93 
 
Table 85. RECEIVE_UPDATE_ VMSA  Status Codes  
UNSUPPORTED  SEV -ES is not configured  
 
6.17 REC EIVE_FINISH  
This command is used to complete the receive work flow and bring the guest to a state that can be 
executed.  
6.17.1  Actions  
• GCTX.TEK  
• GCTX.TIK  
• GCTX.MS  
The guest transitions to the GSTATE.RUNNING state.    
 
94 Guest Management API   Chapter 6  
 
6.17.2  Parameters  
Table 86 specif ies the parameters for the RECEIVE_FINISH command.  
Table 86. RECEIVE_FINISH Command Buffer  
 
6.17.3  Status Cod es 
Table 87 enumerates the possible status codes returned by the RECEIVE _FINISH command.  
Table 87. RECEIVE _FINISH Status Codes  

executed.  
• GCTX.TEK  
• GCTX.TIK  
• GCTX.MS  
 
INVALID_LENGTH  A buffer length is not correct.  
INVALID_GUEST_STATE  The guest state is not in the GSTATE. RUPDATE state.  
 
6.18 GUEST_STATUS  
This command is used to retrieve status information about an SEV -enabled guest . 
6.18.1  Actions  
The platform must be in the PSTAT E.INIT or PSTATE.WORKING states.  
The guest may be in any state.  
If the HANDLE field is invalid, the STATE field is set to 0h and all other parameters are 
untouched.  
 
 Chapter 6  Guest Management API  95 
 
The guest remains in the same stat e after completion.  
6.18.2  Parameters  
Table 88 specify the parameters for the GUEST_STATUS command.  
Table 88. GUEST_STATUS Command Buffer  
04h 31:0 Out POLICY  Guest policy.  
08h 31:0 Out ASID  Current ASID. If not active, set to 0h.  
0Ch 7:0 Out STATE  Current guest state.  See Table 43. 
6.18.3  Status Cod es 
Table 89 enumerates the possible status codes returned by the GUEST_STATUS  command.  
Table 89. GUEST_STATUS Status Codes  
 
6.19 ACTIVATE  
This command is used to inform the firmware that the guest is bound to a particular ASID. The  
firmware then loads the guest’s VEK into the memory controller at the key slot for that ASID.  
When the guest is RUNNING, all Cache Core Complexes (CCXs) will be allowed to execute the 
guest.  
6.19.1  Actions  
The gu est may be in any state.    
 
96 Guest Management API   Chapter 6  
 
The guest must be inactive. The ASID parameter must not be zero and must be a valid SEV ASID. 
The ASID must not be currently used by another guest.  
If the guest is SEV -ES enabled, then the ASID must be at least 1h and at most (MIN_ SEV_ASID -
1). If the guest is not SEV -ES enabled, then the ASID must be at least MIN_SEV_ASID and at 
most the maximum SEV ASID available. The MIN_SEV_ASID value is discovered by CPUID 
Fn8000_001F[EDX]. The maximum SEV ASID available is discovered by CPUID 
Fn8000_001F[ECX].  
A successful DF_FLUSH must be executed since the last DEACTIVATE command was issued  
for the ASID . 
The VEK of the guest identified by HANDLE is loaded into the memory controller in the slot 
identified by ASID. The ASID will be marked valid on all cores  when the guest transitions to 
RUNNING state , or immediately if already in RUNNING state . 
The guest remains in the same state after completion . 
6.19.2  Parameters  
Table 90 specifies  the parameters for the ACTIVATE command . 
Table 90. ACTIVATE Command Buffer  
04h 31:0 In ASID  ASID to activate the guest with.  
 
6.19.3  Status Cod es 
Table 91 enumerates the possible status codes returned by the ACTIVATE command.  
Table 91. ACTIVATE Status Codes  
INVALID_PLATFORM_STATE  The platform is not in the working state.  
ACTIVE  The guest is currently active.  
ASID _OWNED  The ASID  is already in use by another guest.  
INVALID_ASID  The ASID is invalid.    
 
 Chapter 6  Guest Management API  97 
 
DF_FLUSH_REQUIRED  A DF_FLUSH has not be en invoked since the last DEACTIVATE 
invocation.  
 
6.20 ACTIVATE_EX  
This command is used to inform the firmware that the guest is bound to a particular ASID and 
designate which specific threads (identified by APIC ID)  will be allowed to run the guest. The 
firmware then loads the guest’s VEK into the memory controller at th e key slot for that ASID. 
When the guest is RUNNING, all threads in the CCX(s) selected by the provided APIC ID(s) will 
be allowed to execute the guest.  That is, designation of a single APIC ID on a CCX will allow all 
threads in that CCX to execute the gue st, and all such threads – whether the guest was run on them 
or not – must have a WBINVD instruction performed between DEACTIVATE and DF_FLUSH. 
The benefit of ACTIVATE_EX over ACTIVATE is that by excluding ALL APIC  IDs residing on 
a CCX, that CCX’s threads  do not need a WBINVD between DEACTIVATE and DF_FLUSH.  
6.20.1  Actions  
The guest may be active or inactive. The ASID parameter must not be zero and must be a valid 
SEV ASID. The ASID must not be currently used by a different  guest. If the guest is already 
active, the ASID must be the ASID the guest is using.  
If the guest was launched with  SEV -ES enabled, then the ASID must be at least 1h and at most 
(MIN_SEV_ASID -1). If the guest was not SEV -ES enabled, then the ASID must be at least 
MIN_SEV_ASID and at most the maximum SEV ASID available. The MIN_SEV_ASID value is 
discovered by CPUID Fn8000_001F[EDX]. The maximum SEV ASID available is discovered by 
CPUID Fn8000_001F[ECX].  
If the guest is inactive, DF_FLUSH (and its pre -requisite WBINVDs) must be executed since  
INIT, or  the last DEACTIVATE command was issued for the ASID , whichever is later.  
identi fied by ASID. The ASID will be marked valid on the selected  CCXs when the guest 
transitions to RUNNING state, or immediately if currently in RUNNING state.    
 
98 Guest Management API   Chapter 6  
 
CCXs are identified by the SEV firmware by APIC ID, which is a thread -level identifier. The 
hypervis or must be aware that ALL threads available on a CCX with one or more activated APIC 
IDs, are subject to the WBINVD/DF_FLUSH requirements.  
6.20.2  Parame ters 
Table 92 specifie s the parameters for the ACTIVATE command. If the EX_LEN field is not 
recognized, the command is invalid.  
Table 92. ACTIVATE_EX  Command Buffer  
Byte 
Offset  Bits In / 
00h 31:0 In EX_LEN  Length of the command buffer. 18h for 0. 22 of the 
API 
04h 31:0 In HANDLE  Guest handle.  
08h 31:0 In ASID  ASID to activate the guest with.  
0Ch 31:0 In NUMID S Number of APIC ID S in ID S_PADDR list  
10h 63:0 In IDS_PADDR  System physical address of the list of APIC IDs  
  
6.20.3  Status Codes  
Table 93 enumerates the possible status codes returned by the ACTIVATE _EX command.  
Table 93. ACTIVATE_EX  Status Codes  
ASID_OWNED  The ASID is already in use by another guest.  
INVALID_ASID  The ASID is invalid.  
DF_FLUSH_REQUIRED  A DF_FLUSH has not been invoked since the last DEACTIVATE 
invocation for the ASID.  
safe to re -allocate parame ter buffers.    
 
 Chapter 6  Guest Management API  99 
 
HWERROR_UNSAFE  A hardware condition has occurred affecting the platform. It is

6.21 DEACTIVATE  
This command is used to dissociate the guest from its current ASID. The firmware will uninstall 
the guest’s key from the memory controller  and disallow use of the ASID by all CCXs .  
6.21.1  Actions  
The firmware uninstalls the guest’s key from the memory controller and records that a  
DF_FLUSH is required for this ASID. The ASID is marked invalid on all cores.  
6.21.2  Parameters  
Table 94 specifies the parameters for the DEACTIVATE command.  
Table 94. DEACTIVATE Command Buffer  
 
6.21.3  Status Cod es 
Table 95 enumerates the possible status codes returned by the DEACTIVATE command.  
Table 95. DEACTIVATE Status Codes  
INVALID_GUEST  The guest handle is invalid.    
 
100 Guest Management API   Chapter 6  
 
6.22 DF_FLUSH  
The x86 system software invokes this command after deactivating one or more guests. The x86 
system software must execute a WBINVD on the hardware threads that the previous guest was 
active on before invoking the DF_FLUSH command.  
6.22.1  Actions  
Each core must have executed a WBINVD instruction since the last DEACTIVATE command 
was invoked.  
The data fabric write buffers are flushed for each core. The firmware also records that a flush has 
been performed for all deactivated ASIDs.  
The platform rem ains in the same state after completion.  
6.22.2  Parameters  
6.22.3  Status Cod es 
Table 96 enumerates the possible status codes returned by the DF_FLUSH command.  
Table 96. DF_FLUSH Command Status Codes  
INVALID_PLATFORM_STATE  The platform is not in the PSTAET.INIT or PSTATE.WORKING 
states  
WBINVD_REQUIRED  WBINVD has not been executed  
 
 Chapter 6  Guest Management API  101 
 
6.23 DECOMMISSION  
The hypervisor no longer intends to run the guest. Invoking this command deletes all guest context 
for this guest. Upon su ccessful completion of this command, HANDLE is no longer a valid guest 
handle. Guests that shared their VEK with this guest are not affected.  
6.23.1  Actions  
The guest handle must be valid. The guest may be in an y state.  
The guest must not be active. The hypervisor must invoke DEACTIVATE for the guest before 
invoking DECOMMISSION.  
All guest context is securely deleted from firmware memory.  After completion, the guest handle 
will not be valid.  
The platform transitions to the PSTATE.INIT state if PCTX.GUEST_COUNT is zero. Otherwise, 
the platform remains in the PSTATE.WORKING state.  
6.23.2  Parameters  
Table 97 specifies  the parameters for the DECOMMISSION command.  
Table 97. DECOMMISSION Command Buffer  
Byte 
 
6.23.3  Status Cod es 
Table 98 enumerates the possible status codes returned by the DECOMMISSION command.  
Table 98. DECOMMISSION Status Codes  
 
102 Guest Management API   Chapter 6  
 
HWERROR_PLATFORM   A hardware condition has occurred affecting the platform. It is safe 
 
6.24 COPY  
The hypervisor wishes to move encrypted guest page(s) from one place in system physical 
memory to another place in system physical memory.  
6.24.1  Actions  
The guest handle must be valid. The guest may be in any state. The guest must be active.  
LENGTH must be a multiple of 4096. SRC_ PADDR must be aligned to a 4096 -byte boundary. 
DST_ PADDR must be aligned to a 4096 -byte boundary.  
LENGTH encrypted bytes are copied from S RC_PADDR to DST_PADDR.  
The platform and guest remain in the same state.  
6.24.2  Parameters  
Table 99 specifies  the parameters for the COPY  command.  
Table 99. COPY  Command Buffer  
Byte 
04h 31:0 In LENGTH  Number of bytes to be copied.  Multiple of 4096.  
08h 63:0 In SRC_PADDR  Physical address of the bytes to be copied.  
10h 63:0 In DST_PADDR  Physical address for the destination of the copy.  
 
6.24.3  Status Codes  
Table 100 enumerates the possible status codes returned by the COPY  command.    
 
 Chapter 6  Guest Management API  103 
 
Table 100. COPY  Status Codes  
INACTIVE  The guest is not active.  
INVALID_ LENGTH  The LENGTH parameter is not a multiple of 4096, or too large.  
 
6.25 SWAP_OUT  
The hypervisor wishes to move an encrypted guest page from system physical memory to some 
off-line storage medium (e.g., a di sk swap ar ea for the guest.) Note that the page can only be 
restored as long as the guest is active. This facility cannot be used to save and restore a guest  to 
any other machine or after the guest has been decommissione d. 
6.25.1  Actions  
The platform must be in the PSTATE.WORKING state. INVALID_PLATFORM_STATE is 
returned if the platform is in any other state.  
SRC_PADDR and DST_PADDR must be aligned to a 4096 -byte boundary if PAGE_SIZE 
indicates  a 4 KB page or aligned to a 2097152 -byte boun dary if PAGE_SIZE indicates  a 2 MB 
page. MDATA_PADDR must be 64 -byte aligned. INVALID_ADDRESS is returned if any of 
these requirements are not met.  
If PAGE_TYPE indicates a VMSA page, PAGE_SIZE must be 4  KB or INVALID_PARAM is 
returned.  
SRC_PADDR, DST_PADD R, and MDATA_PADDR must be valid addresses, otherwise 
INVALID_ADDRESS is returned.  
MDATA_PADDR must not overlap SRC_PADDR or DST_PADDR, otherwise 
INVALID_PARAM is returned.    
 
104 Guest Management API   Chapter 6  
 
The guest handle must be valid. INVALID_GUEST is returned if the guest is not valid. The guest 
may be in any state  except UNINIT . The guest must be active.  INACTIVE is returned if the guest 
is not active.  
If SRC_PADDR points to a VMSA page and PAGE_TYPE does not equal VMSA or if 
SRC_PADD R does not point to a VMSA page and PAGE_TYPE equals VMSA, 
INVALID_PARAM is returned.  
The page at SRC_PADDR will be decrypted with the guest’s VEK. A new, random 64 -bit IV is 
generated and stored in the Metadata Entry. The SOFTWARE_DATA, PAGE_SIZE and 
PAGE_TYPE fields are also stored in the Metadata entry. If the source page was a VMSA page, 
the VMSA_FLAG is set in the Metadata entry. AES -256 GCM is used to encrypt the decrypted 
guest memory using the IV with the Metadata entry (with AUTH_TAG zeroed) as  additional 
authenticated data. The generated Auth Tag is stored in the Metadata entry.

authenticated data. The generated Auth Tag is stored in the Metadata entry.  
6.25.2  Parameters  
Table 101 specifies  the parameters for the SWAP_OUT  command.  
Table 101. SWAP_OUT  Command Buffer  
Byte 
04h 0 In PAGE_SIZE  Indicates page size. 0 indicates a 4 KB page. 
1 indicates a 2 MB page.  
 2:1 In PAGE_TYPE  Indicates the page type of the source page. 0h 
indicates a normal data page. 2h indicates a VMSA 
page. Other encodings are reserved.  
 31:3 - - Reserved. Must be zero.  
08h 63:0 In SRC_PADDR  Physical address of the page  to be swapped out . Must 
be 4 KB or 2 MB aligned , per PAGE_SIZE.  
10h 63:0 In DST_PADDR  Physical address for the destination of the copy.  Must 
18h 63:0 In MDATA_PADDR  Physical address used to store the page’s 
METADATA_ENTRY. Must be 64 -byte aligned.  See 
Table 102 for format.  
20h 63:0 In SOFTWARE_DATA  64 bits of arbitrary data that will be preserved and 
authenticated (but not encrypted) by the 
METADATA_ENTRY . 
   
 Chapter 6  Guest Management API  105 
 
Table 102. SWAP_OUT & SWAP_IN Metadata Entry  
Byte 
Offset  Bits Name  Description  
00h 63:0 SOFTWARE_DATA  SOFTWARE_DATA from SWAP_OUT command . 
08h 63:0 AES_GCM_IV  IV for AES_GCM encryption randomly generated by 
SWAP_OUT command.  
10h 127:0 AUTH_TAG  AES -GCM Authentication Tag generated by 
20h-3Bh 7:0 - All bytes in this range must be zero.  
3Ch 0 PAGE_SIZE  Indicates page size. 0 indicates a 4 KB page. 1 
indicates a 2 MB page.  
2:1 PAGE_TYPE  Indicates the page type of the source page. 0h 
31:3 - Reserved. Must be zero.  
 
6.25.3  Status Codes  
Table 103 enumerates the possible status codes returned by the SWAP_OUT  command.  
Table 103. SWAP_OUT  Status Codes  
INVALID_ADDRESS  A memory region provided contains invalid physical addresses  or 
address that are not aligned.  
unsafe to re -allocat e parameter buffers.  
 
6.26 SWAP_IN  
The hypervisor wishes to restore an encrypted guest page to system physical memory from some 
off-line storage medium (e.g., a disk swap area for the guest.) Note that the page can only be   
 
106 Guest Management  API  Chapter 6  
 
restored to the same guest that used SWAP_OUT . This facility cannot be used to save and restore 
a guest.  
6.26.1  Actions  
SRC_PADDR and DST_PADDR must be aligned to a 4096 -byte boundary if SIZE_FLAG equals 
a 4 KB page or aligned to a 2097152 -byte boundary if SIZE_FLAG equals a 2  M page. 
MDATA_PADDR must be 64 -byte aligned. INVALID_ADDRESS is returned if any of these 
requirements are not met.  
SRC_PADDR, DST_PADDR, and MDATA_PADDR must be valid addresse s, otherwise 
PAGE_SIZE and PAGE_SOURCE must match the corresponding values in the metadata entry or 
else INVALID_PARAM is returned.  SWAP_ IN_PLACE must be 0 if PAGE_TYPE equals 
VMSA, otherwise INVALID_PARAM is returned.  If SWAP_IN_PLACE is 1, then SRC_PADDR 
must match DST_PADDR.  
may be in any state  except UNINIT. The guest must be active. INACTIVE is returned if the guest 
The page at SRC _PADDR will be decrypted with the guest’s OEK and the IV from the Metadata 
entry . The AUTH_TAG field i s saved and zeroed and AES -256 GCM is used to decrypt the 
encrypted memory  to PSP private memory  using the Metadata entry  as additional authenticated 
data. If authentication against the original AUTH_TAG value is successful, the decrypted data will 
be stored at DST_PADDR with the guest’s VEK.  
The platform and guest remain in the same state.    
 
 Chapter 6  Guest Management API  107 
 
6.26.2  Parameters  
Table 104 specifies  the parameters for the SWAP_ IN command.  
Table 104. SWAP_ IN Command Buffer  
Byte 
04h 0 In PAGE_SIZE  Indicates page size. 0 indicates a 4 KB page. 1 
2:1 In PAGE_TYPE  Indicates the page type of the source page. 0h 
3 In SWAP_IN_PLACE  If set, then SRC_PADDR and DST_PADDR are 
equal and the page will be swapped in place.  
31:4 - - Reserved. Must be zero.  
08h 63:0 In SRC_PADDR  Physical address of the encrypted data to be swapped 
in. Must be 4  KB aligned . 
10h 63:0 In DST_PADDR  Physical address for the destination of the copy. Must 
be 4 KB aligned . 
METADATA_ENTRY. Must be 64 -byte aligned. See 
 
6.26.3  Status Codes  
Table 105 enumerates the possible status codes returned by the SWAP_IN  command.  
Table 105. SWAP _IN Status Codes  
 
108 Guest Management API   Chapter 6  
 
 Chapter 7  Debugging API  109 
 
Chapter 7  Debugging API  
The debugging API provides a simple interface to decrypt and encrypt memory with a guest’s 
VEK. This allows developers of guest kernels and hypervisor to troubleshoot bugs.  The 
commands in this chapter can be (and , in production environments, should be) disabled via the 
Guest Policy bit NODBG (see Table 2. Guest Policy Structure ) establ ished in LAUNCH_START . 
7.1 DBG_DECRYPT  
This command enables developers of hypervisors and guest kernels to access encrypted memory.  
7.1.1 Actions  
The guest policy must allow deb ugging.  
The contents of the source region starting at SRC_PADDR and extending LENGTH bytes are 
decrypted using GCTX.VEK and saved into the destination memory region starting at 
DST_PADDR and extending LENGTH bytes.  
The guest and platform states are unaffec ted. 
7.1.2 Parameters  
Table 106 specifies the parameters for the DBG_DECRYPT command.  
Table 106. DBG_DECRYPT Command Buffer  
08h 63:0 In SRC_PADDR  System physical address of data to decrypt. Must 
be 16 B aligned.  
10h 63:0 In DST_PADDR  System physical address of destination. Must be 
16 B aligned.  
18h 31:0 In LENGTH  Length of regions. Must be 16 B aligned.  
   
110 Debugging API   Chapter 7  
 
7.1.3 Status Cod es 
Table 107 enumerates the possible status codes returned by the DBG_DECRYPT command.  
Table 107. DBG_DECRYPT Status Codes  
INVA LID_PLATFORM_STATE  The platform is not in the PSTATE.WORKING state.  
POLICY_FAILURE  The policy disallows debugging.  
 
7.2  DBG_ENCRYPT

7.2  DBG_ENCRYPT  
This command allows a developer to encrypt memory for debugging purposes.  
7.2.1 Actions  
The guest policy must allow debugging.  
The contents of the source region , starting at SR C_PADDR and extending LENGTH bytes , are 
encrypted using GCTX. VEK and saved into the destination memory region , starting at 
The guest and platform states are unaffected.    
 
 Chapter 7  Debugging API  111 
 
7.2.2 Parameters  
Table 108 specifies the parameters for the DBG_ENCRYPT command.  
Table 108. DBG_ENCRYPT Command Buffer  
Byte Offset  Bits In / Out  Name  Descriptio n 
08h 63:0 In SRC_PADDR  System physical address of data to encrypt. Must be 
10h 63:0 In DST_PADDR  System physical address of destination. Must be 16 
B aligned.  
 
7.2.3 Status Cod es 
Table 109 enumerates the possible status codes returned by the DBG_ENCRYPT command.  
Table 109. DBG_ENCRYPT Status Codes  
 
Secur e Encrypted Virtualization API  
 
112 Usage Flows   Appendix A  
 
Appendix A  Usage Flows  
The following flow charts are provided to illustrate the how the usage of the SEV API might be 
implemented. Note that these are only examp les and there may be other implementation strategies.  
Platform Provisioning
AMD Secure 
Processor
Cloud Provider
SEV Platform from 
factory
Boots platform and 
initializes SEVINIT
Retrieves PEK 
certificate signing 
request
Generates PEK 
certificate and signs 
with CA signing key
Imports PEK 
certificate into 
platformPEK_CSRFACTORY _RESET
SEV Platform re -
allocated
Resets platform to 
factory state
PEK_CERT _IMPORTAll interactions between 
provider and AMD Secure 
Processor are facilitated by 
hypervisor
   
 Appendix A  Usage Fl ows 113 
 
Launching a Guest
 Guest Owner
AMD Secure 
Processor
Guest Startup
 Provisioning
Agreement on boot image and computation of hash
Generate and 
provide session info 
for LAUNCH _START
Asks hypervisor to 
boot guest
Retrieves guest from 
library and  loads it 
into memory
Provides the 
customer DH key 
and session infoLAUNCH _START
Continues to ask 
firmware to encrypt 
guest memoryLAUNCH _UPDATE _DATA
LAUNCH _UPDATE _VMSA
Initialize SEV 
firmwwareINIT
 Boots SEV platform
Allocates an ASID 
and activates guestACTIVATE
Update commands are called 
as many times as needed .
Query for PDH 
certificate chain
Query / store PDH 
certificate chainPDH _CERT _EXPORT   
 
114 Usage Flows   Appendix A  
 
Launching a Guest (continued )
AMD Secure 
Processor
Completes 
encrypting guest 
image
Sends measurement 
to guest ownerMeasurementLAUNCH _MEASURE
LAUNCH _SECRET
Inject guest with 
secret (disk 
encryption key )
Customer (or 
delegate ) 
authenticates 
platform and verifies 
measurementVia provider
Encrypts disk 
encryption key and 
sends to guest
Finalize launch 
processLAUNCH _FINISH
Sets SEV -enable bit 
in VMCB
VMRUN
Guest is runningVia provider   
 
 Appendix A  Usage Flows  115 
 
Live Migration
Destination 
Source AMD Secure 
Processor
Destination AMD Secure 
Processor
Source Hypervisor / 
Guest is running
Requests PDH of 
destination platform
Retrieves PDH and 
certificate chain 
from destination 
firmwarePDH _CERT _EXPORT
Begins re -encryption 
process by providing 
PDH and certificate 
chain to source 
firmware
Sends PDH and 
certificate chain to 
sourceSEND _START
Retrieves encrypted 
guest pages and 
sends to destinationSEND _UPDATE _DATA
SEND _UPDATE _VMSA
Finalizes re -
encryption process . 
Informs destination 
of completionSEND _FINISHSEND _START authenticates 
the PDH and certificate 
chain .
Sends PDH 
certificate and 
session info to 
firmware
Sends PDH 
firmwareRECEIVE _START
RECEIVE _UPDATE _DATA
RECEIVE _UPDATE _VMSA
Loads encrypted 
guest pages into 
destination guest
Finalizes receive 
processRECEIVE _FINISH
Migration 
CompletedUpdate commands are called 
and activates guestACTIVATE 
   
116 AMD Certificate Authority Certificates   Appendix B  
 
Appendix B  AMD Certificate Authority 
Certificates  
AMD maintains a certificate authority to authenticate AMD hardware and software for a number 
of applications. The root of trust of the certificate authority is the AMD Root Signing Key (ARK). 
This key then signs the AMD SEV Signing Key (ASK), which is an intermediate certificate 
authority specifically used for SEV related authentication.  
B.1 Certificate Format  
Table 110 specifies the format of the certificates for the ASK and ARK.  This version of the API 
supports version 01h of the certificate format. Table 111 enumerates the valid key usage values for 
the KEY_USAGE field.  
Table 110. AMD Signing Key Certificate Format  
00h 31:0 VERSION  Certificate format version.  The API expects a 1.  
04h 127:0  KEY_ID  The unique ID for this key.  
14h 127:0  CERTIFYING_ID  The unique ID for the key that signed this certificate. 
If this certificate is self -signed, then this field equals 
the KEY_ID field.  
24h 31:0 KEY_USAGE  Usage of the key. See Table 111. 
28h 127:0  - Reserved. Set to zero.  
38h 31:0 PUBEXP_SIZE  Size of the public exponen t in bits. Must be 2048 or 
4096.  
3Ch 31:0 MODULUS_SIZE  Size of the public modulus in bits. Must be 2048 or 
4096.  
40h 2047:0 or 
4095:0  PUBEXP  Public exponent of this key. The size of this field in 
bits is equal to PUBEXP_SIZE.  
- 2047:0 or 
4095:0  MODULUS  Public modulus of this key. The size of this field in 
bits is equal to MODULUS_SIZE.  
- 2047:0 or 
4095:0  SIGNATURE  Signature of this key. The size of this field in bits is 
equal to MODULUS_SIZE in.  
 
Table 111. Key Usage Enc oding  
Key Usage  Description  
00h AMD Root Signing Key.  
13h AMD SEV Signing Key.  
   
 Appendix B  AMD Certificate Authority Certificates  117 
 
B.2 Certificate Signature  
The ARK and ASK certificates both carry RSASSA -PSS signatures . EPYC 7001 generation of 
microprocessors  uses SHA -256 as the digest algorithm  with 2048 -bit keys . EPYC 7002 generation 
of microprocessors  uses SHA -384 as the digest algorithm  with 4096 -bit keys.  
B.3 Certificate Validation  
The following procedure validates an AMD SEV Signing Key certificate:  
1. Verify that the ASK VERSION field is a version supported by this API version  (1). 
2. Verify that the ASK KEY_USAGE field is equal to the ASK key usage encoding.  
3. Verify that the ASK PUBEXP_SIZE field is equal to 4096 or 2048.  
4. Verify that the ASK MOD_SIZE field is equ al to 4096 or 2048.  
5. Verify that the ARK VERSION field is a version supported by this API version  (1). 
6. Verify that the ARK KEY_USAGE field is equal to the ARK key usage encoding.  
7. Verify that the ARK PUBEXP_SIZE field is equal to 4096 or 2048.  
8. Verify that th e ARK MOD_SIZE field is equal to 4096 or 2048.  
9. Verify that the ARK KEY_ID field is equal to the ASK CERTIFYING_ID field.  
10. Verify that the ASK SIGNATURE field is a valid signature by the ARK.  
11. Verify that the ARK SIGNATURE field is a valid signature by the AR K. 
If any of the above fail, the certificate is invalid.  
   
118 SEV Certificates   Appendix C  
 
Appendix C  SEV Certificates  
The PEK, CEK, OCA, and PDH key pairs all have certificates used to authenticate the platform. 
The certificates for the PEK, CEK, OCA, and PDH are distinct from the certific ate used within the 
AMD certificate authority described in Appendix B . 
C.1 Certificate Format

C.1 Certificate Format  
An SEV certificate consists of a certificate version, public key, and zer o, one, or two signatures. 
Table 112 specifies the layout of a SEV certificate.  
Table 112. SEV Certificate Format  
000h  31:0 VERSION  Certificate version, set to 01h.  
004h  7:0 API_MAJOR  If PEK, set to API minor version  
Otherwise, zero.  
005h  7:0 API_MINOR  If PEK, set to API minor version  
006h  7:0 - Reserved. Set to zero.  
007h  7:0 - Reserved. Set to zero.  
008h  31:0 PUBKEY_USAGE  Public key usage  
00Ch  31:0 PUBKEY_ALGO  Public key algorithm  
010h – 413h  - PUBKEY  Public key  
414h  31:0 SIG1_USAGE  Key usage of SIG1 signing key  
418h  31:0 SIG1_ALGO  First signature algorithm  
41Ch – 61Bh  - SIG1  First signature  
61Ch  31:0 SIG2_USAGE  Key usage of SIG2 signing key  
620h  31:0 SIG2_ALGO  Second signature algorithm  
624h – 823h  - SIG2  Second signature  
 
Table 113. USAGE Enumeration (All other encodings are reserved ) 
Value  Enumeration  
0000h  ARK  
0013h  ASK  
1000h  Invalid  
1001h  OCA  
1002h  PEK  
1003h  PDH  
1004h  CEK  
   
 Appendix C  SEV Certificates  119 
 
Table 114. ALGO Enumeration (All other encodings are reserved ) 
0h Invalid  
1h RSA  with SHA -256 
2h ECDSA  with SHA -256 
3h ECDH  with SHA -256 
101h  RSA with SHA -384 
102h  ECDSA with SHA -384 
103h  ECDH with SHA -384 
 
The PUBKEY field contains the public key represented by this certificate. The format of the 
PUBKEY field is determined by the PUBKEY_ALGO field. Th e PUBKEY_ALGO field must be 
one of the valid algorithms enumerated in Table 114 on page 119. See Section  C.3 for the format 
of the public key for each algorithm.  
The PUBKEY_USAGE field specifies the SEV specific usage for the public key represented by 
this certificate. Table 113 on page 118 enumerates the possible usage identifiers.  
The certificate may have zero, one, or two signatures. SIG1_USAGE and SIG2_USAGE describe 
the key usage for the certifying key that signed the certificate.  If SIG1_USAGE is 1000h, SIG1 is 
not present and the SIG1_ALGO and SIG1 fields are ignored.  If SIG2_USAGE is 1000h, SIG2 is 
not present and the SIG2_ALGO and SIG2 fields are ignored.  
The SIG1 and SIG2 fields are formatted according to the SIG1_ALGO and SI G2_ALGO fields, 
respectively. SIG1_ALGO and SIG2_ALGO must each specify a signing key algorithm from 
Table 114. See  Section C.4, on page 121, for the format of each signature algorithm.  
C.2 Elliptic Curve Enumeration  
Table 115. CURVE Enumeration (All other encodings are reserved ) 
0h Invalid  
1h P256  
2h P384  
 
The above table describes elliptic curves used by the SEV firmware. Note that the NIST P -256 
curve is not currently supported but reserved for future usage.    
 
120 SEV Certificates   Appendix C  
 
C.3 Public Key Formats  
The following subsections describe the public key formats for the SEV certificates.  
C.3.1  RSA Public Key  
The ALGO.RSA public key format is specified in Table 116 . This format supports RSA keys up 
to 4096 bits in size.  
Table 116. RSA Public Key  
000h  31:0 MODULUS_SIZE  Size of modulus in bits. 
004h  4095:0  PUBEXP  Public exponent.  
204h  4095:0  MODULUS  Modulus.  
C.3.2  ECDSA Public Key  
The ALGO.ECDSA public key format is specified in Table 117 . The CURVE field specifies 
which elliptic curve that the public key is defined on. The supported curves are defined in 
Section  C.2 on page 119. 
Table 117. ECDSA Public Key  
000h  31:0 CUR VE Curve ID.  
004h  575:0  QX x component of the public point Q.  
04Ch  575:0  QY y component of the public point Q.  
094h – 403h  - - Reserved. Must be zero.  
C.3.3  ECDH Public Key  
The ALGO.ECDH public key format is specified in Table 118. The CURVE field specifies which 
elliptic curve that the public key is defined on. The supported curves are defined in Section C.2 on 
page 119. 
Table 118. ECDH Public Key  
000h  31:0 CURVE  Curve ID.  
094h – 403h  - - Reserved. Must be zero.    
 
 Appendix C  SEV Certificates  121 
 
C.4 Signature Formats  
The following subsections describe the signature formats for the SEV certificates.  
C.4.1  RSA Signature  
The ALGO.RSA signature format is specified in Table 119. This format supports signatures by 
RSA keys up to 4096 bits in size.  
Table 119. RSA Signature  
000h – 1FFh  4095:0  S Signature.  
 
C.4.2  ECDSA Signature  
The ALGO.ECDSA signature format is specified in Table 120. 
Table 120. ECDSA Signature  
000h – 047h  575:0  R R component of the signature.  
048h – 08Fh  575:0  S S component of the signature.  
090h – 1FFh  - - Reserved. Must be zero.  
 
C.5 Certificate Validation  
The following procedure validates an SEV certificate chain:  
1. PDH certificate  
a. Verify that the VERSION field is supported by this API version  
b. Verify that the PUBKEY_USAGE field is equal to the PDH key usage encoding  
c. Verify that SIG1_USAGE field is equal to the PEK key usage encoding  
d. Verify that SIG1_ALGO field is equal to the PUBKEY_ALGO field of the PEK ce rtificate  
e. Verify that the SIG1 field is a valid signature by the PEK certificate’s public key  
2. PEK certificate  
b. Verify that the PUBKEY_USAGE field is equal to the PEK key usage encoding  
c. Verify that SIG1_USAGE field is equal to the CEK key usage encoding    
Version 0.2 4 55766  Rev. 3.24 April 2020   
 
122 SEV Certificates   Appendix C  
 
d. Verify that SIG1_ALGO field is equal to the PUBKEY_ALGO field of the CEK certificate  
e. Verify that the SIG1 field is a valid signature by the CEK certificate’s public key  
f. Verify that SIG2_US AGE field is equal to the OCA key usage encoding  
g. Verify that SIG2_ALGO field is equal to the PUBKEY_ALGO field of the OCA 
certificate  
h. Verify that the SIG2 field is a valid signature by the OCA certificate’s public key  
i. Note: SIG1 and SIG2 can be swapped. Th at is, SIG1 could be the OCA certificate and 
SIG2 could be the CEK certificate.  
3. OCA certificate  
b. Verify that the PUBKEY_USAGE field is equal to the OCA key usage encoding  
d. Verify that SIG1_ALGO field is equal to the PUBKEY_ALGO field  
e. Verify that the SIG1 field is a valid self signature  
4. CEK certificate  
b. Verify that the P UBKEY_USAGE field is equal to the CEK key usage encoding  
c. Verify that SIG1_USAGE field is equal to the ASK key usage encoding  
d. Verify that SIG1_ALGO field is equal to the PUBKEY_ALGO field of the ASK certificate  
e. Verify that the SIG1 field is a valid signatu re by the ASK certificate’s public key  
5. ASK certificate – see Section B  
6. ARK certificate – see Section B  
If any of the above fail, the certificate is invalid   
 
Intel® TDX Connect  
TEE-IO Device Guide  
 
February 2023  
 
 Disclai mers    
 
2        Document Number:  354272 -001    
Disclaimers    
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subject to change without notice.  Intel does not guarantee the availability of these interfaces in any 
future product. Contact your Intel representative to obtain the latest Intel product specifications and 
roadmaps.  
The products described might contain design defects or errors known as errata, which might cause the 
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Intel technologies might require e nabled hardware, software, or service activation.  Some results have 
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information provided here is subject to change without notice.

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information provided here is subject to change without notice.  
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© Intel Corporation , 2023 .  Intel, the Intel logo, and other Intel marks are trademarks of Intel 
Corporation or its subsidiaries.  O ther names and brands might be claimed as the property of others.  
 
  Table  of Contents    
 
3        Document Number:  354272 -001    
Table of Contents  
Disclaimers  ................................ ................................ ................................ ................................ ................................ ........ 2 
Table of Contents  ................................ ................................ ................................ ................................ ...........................  3 
Introduction and Scope  ................................ ................................ ................................ ................................ ...............  6 
Glossary  ................................ ................................ ................................ ................................ ................................ .........  8 
1 TEE-IO Device Architecture Overview  ................................ ................................ ................................ ....... 10 
TEE-IO Security Model  ................................ ................................ ................................ ................................ .........  10 
Security Model for the Device  ................................ ................................ ................................ ...........................  11 
Implementing TEE -IO Device Stack  ................................ ................................ ................................ ................  11 
Secure Device Interface Lifecycle Example  ................................ ................................ ................................ . 12 
2     TEE -IO Software Stack ................................ ................................ ................................ ................................ ...... 15 
Software Stack Overview ................................ ................................ ................................ ................................ ..... 15 
Devi ce Communication (DOE)  ................................ ................................ ................................ ...........................  16 
Device Attestation (SPDM)  ................................ ................................ ................................ ................................ .. 16 
Software Secure Communication (SPDM)  ................................ ................................ ................................ .... 17 
Link Encryption Key Management (IDE_KM)  ................................ ................................ ...............................  18 
Device Interface Management (TDISP)  ................................ ................................ ................................ ..........  19 
Implementation Reference  ................................ ................................ ................................ ................................ . 21 
SPDM software stack  ................................ ................................ ................................ ................................ ........ 21 
IDE_KM software stack  ................................ ................................ ................................ ................................ .... 22 
TDISP software stack  ................................ ................................ ................................ ................................ ........ 22 
3     TE E-IO Hardware Stack  ................................ ................................ ................................ ................................ .... 24 
IDE Stream  ................................ ................................ ................................ ................................ ................................ . 24 
IDE Stream Precedence  ................................ ................................ ................................ ................................ ... 27 
TEE Limited Stream  ................................ ................................ ................................ ................................ ...........  27 
Partial He ader Encryption  ................................ ................................ ................................ ..............................  27 
TDI TLP Rule  ................................ ................................ ................................ ................................ .............................  28 
TDI as Completer ................................ ................................ ................................ ................................ ................  30 
TDI as Requester  ................................ ................................ ................................ ................................ ................  32 
ATS Rule  ................................ ................................ ................................ ................................ ................................ . 34 
Peer to Peer (P2P)  ................................ ................................ ................................ ................................ ..............  36 Table  of Contents    
 
4        Document Number:  354272 -001    
TDISP Interoperability with PCIe Capabilities ................................ ................................ .............................  37 
MSI-X ................................ ................................ ................................ ................................ ................................ ....... 37 
ATS  ................................ ................................ ................................ ................................ ................................ ...........  37 
Direct P2P  ................................ ................................ ................................ ................................ ..............................  37 
PASID  ................................ ................................ ................................ ................................ ................................ ...... 37 
LNR  ................................ ................................ ................................ ................................ ................................ ...........  37 
TPH  ................................ ................................ ................................ ................................ ................................ ...........  38 
4     Device Security Architecture  ................................ ................................ ................................ ..........................  39 
Resource Isolation and Protection  ................................ ................................ ................................ ..................  39 
Address Translation  ................................ ................................ ................................ ................................ ..............  39 
Device Resource  ................................ ................................ ................................ ................................ ......................  39 
Device Identity and Measurement Reporting  ................................ ................................ .............................  39 
Device Firmware Resilience  ................................ ................................ ................................ ...........................  40 
Runtime Firmware Update  ................................ ................................ ................................ .............................  40 
Secure Interconnects  ................................ ................................ ................................ ................................ ............  42 
Device Attached Memory  ................................ ................................ ................................ ................................ .... 42 
TDI Security  ................................ ................................ ................................ ................................ ...............................  42 
Data Integrity Errors  ................................ ................................ ................................ ................................ ..............  42 
Debug Modes  ................................ ................................ ................................ ................................ ...........................  43 
Device Debug Interface  ................................ ................................ ................................ ................................ ... 43

Device Debug Interface  ................................ ................................ ................................ ................................ ... 43 
Device Reset ................................ ................................ ................................ ................................ ..............................  43 
Conventional Reset  ................................ ................................ ................................ ................................ ...........  43 
Function Level Reset (FLR)  ................................ ................................ ................................ .............................  44 
Timing  ................................ ................................ ................................ ................................ ................................ ..........  44 
Error Handling  ................................ ................................ ................................ ................................ ..........................  45 
Error Trigger  ................................ ................................ ................................ ................................ .........................  45 
Error Notifica tion ................................ ................................ ................................ ................................ ................  48 
Error Recovery  ................................ ................................ ................................ ................................ .....................  50 
5     Summary  ................................ ................................ ................................ ................................ ................................  52 
Appendix A: Intel® TDX Connect Interoperability  ................................ ................................ ..........................  53 
TDX Connect Software Interoperability  ................................ ................................ ................................ ........ 53 Table  of Contents    
 
5        Document Number:  354272 -001    
DOE  ................................ ................................ ................................ ................................ ................................ ..........  53 
SPDM  ................................ ................................ ................................ ................................ ................................ ....... 54 
IDE_KM  ................................ ................................ ................................ ................................ ................................ ... 55 
TDISP  ................................ ................................ ................................ ................................ ................................ ....... 56 
TDX Connect Hardware Interoperability  ................................ ................................ ................................ ...... 57 
IDE Stream  ................................ ................................ ................................ ................................ ............................  57 
TDISP  ................................ ................................ ................................ ................................ ................................ ....... 59 
Appendix B: Secure Device Interface Lifecycle Example  ................................ ................................ ............  66 
SPDM Management  ................................ ................................ ................................ ................................ ...............  66 
SPDM Session Setup  ................................ ................................ ................................ ................................ ........ 66 
SPDM Session Termination  ................................ ................................ ................................ ...........................  66 
SPDM Session Heartbeat  ................................ ................................ ................................ ................................  67 
SPDM S ession Key Update  ................................ ................................ ................................ .............................  67 
Device Information Recollection  ................................ ................................ ................................ .................  67 
IDE Stream Management  ................................ ................................ ................................ ................................ ..... 68 
IDE Stream Setup  ................................ ................................ ................................ ................................ ...............  68 
IDE Stream Stop  ................................ ................................ ................................ ................................ .................  69 
IDE Stream Key Refresh  ................................ ................................ ................................ ................................ ... 70 
TDI Lifecycle Management  ................................ ................................ ................................ ................................ . 71 
TDI Assignment  ................................ ................................ ................................ ................................ ...................  71 
TDI Teardown  ................................ ................................ ................................ ................................ ......................  73 
References ................................ ................................ ................................ ................................ ................................ ...... 74 
Standards  ................................ ................................ ................................ ................................ ................................ ... 74 
Web Resources  ................................ ................................ ................................ ................................ ........................  76 
 
  Introduction  and Scope    
 
6        Document Number:  354272 -001    
Introduction and Scope  
In the  computer  industry, hardware -based trusted execution environments (TEEs) are used to 
provide the confidential computing environment. In this document, such TEEs are referred to 
as Trusted Execution Environment VMs (TVMs) to distinguish them from traditional virtual  
machines (VMs). Today, multiple CPU vendor s such as Intel, AMD, ARM, and  RISC -V already 
published the solution to address the need based upon the new capability in the host CPU.  
In order to achieve high performance in the data center, the host CPU may off load some 
workload to the device, such as Hardware Security Module  (HSM) for crypto accelerating, 
Graphic Processing Unit  (GPU) for AI processing, and Smart Network Interface Card  (NIC) for 
network processing. In this case, the confidential computing environment is extended from 
the T VM to a portion of a device (TEE Device Interface, also known as TDI).  
The TDI could be a Physical function (PF), a Virtual function (VF), or an Assi gnable Device 
Interface (ADI). To support such functions, the industry standard groups, such as PCI -SIG and 
Compute Express Link (CXL) Consortium , defined the new standard to support the use case, 
including Integrity and Data Encryption (IDE) and TEE Devic e Interface Security Protocol 
(TDISP).  
In a host environment, we use TEE security manager (TSM) to indicate the logic Trust 
Computing Base (TCB) component to enforce the security policy. The TSM could be inside of a 
TVM, or the TSM could be a component out side of the TVM and trusted by the TVM.  
Inside the device, we use Device Security Manager (DSM) to indicate the logic al TCB 
component t hat enforce s the security policy. The TSM should set up a secure management 
channel with the DSM to get the device inform ation and manage the device interface.  The TSM 
and DSM may also negotiate the encryption key for secure  communication.  Introduction  and Scope    
 
7        Document Number:  354272 -001    
 
Figure 0 -1: TEE-IO Component Conceptual View (Source: [PCIe TDISP 1.0])  
Figure 0 -1 shows a conceptual view of TEE -IO component  as an ex ample.  
This whitepaper's  goal is to provide the guidance on  how to build a device to meet the 
confidential computing requirement, as such the T VM can offload the workload to the device.   
The organization of the white paper  is as follows:  
• Chapter 1 provide s an overview on how the host software establishes the trust 
relationship with the device.  
• Chapter 2 describe s the software protocols and requirement s for secure management 
of SPDM and IDE session management between TSM and DSM and for secure 
manage ment of TDI assignment to a TVM . 
• Chapter 3 describe s the device and the host hardware shared responsibilities for 
ensuring access controls of data path MMIO and DMA access controls between a TDI 
and its corresponding TVM . 
Introduction  and Scope    
 
8        Document Number:  354272 -001

8        Document Number:  354272 -001    
• Chapter 4 describe s intra -device security requirements including isolation, integrity,  
and confidentiality protection  of TDI and TVM private data , device identity , and 
measurement reporting  and device firmware update.  
• Appendix A specifies  the specific requirement s for TEE-IO device  interoperability with 
the TDX Connect architecture . 
Glossary  
 
Table 0 -1: Glossary  
ACS  Access Control Service  
ATS  Address Translation Service  
CA Completer Abort  
CMA  Component Measurement and Authentication  
CPL  Completion  
DOE  Data Object Exchange  
DSM  Device Security Manager  
EP Endpoint  
FLR Function Level Reset  
IDE Integrity and Data Encryption  
IDE_KM  IDE Key Management  
LN Lightweight Notification  
LNR  LN Request  
MSI Message Signal Interrupt  
NPR  Non -Posted Request  
P2P  Peer to Peer  
PASID  Process Address Space ID  
PR Posted Request  
PRS  Page Request Service  Introduction  and Scope    
 
9        Document Number:  354272 -001    
RP Root Port  
SPDM  Security Protocol and Data Model  
TDI TEE Device Interface  
TDISP  TEE Device Interface Security Protocol  
TEE  Trusted Execution Environment  
TLP  Transaction Layer Packet  
TPH  TLP Processing Hint  
TSM  TEE Security Manager  
TVM  TEE Virtual Machine  
UC Unexpected Completion  
UR Unsupported Request  
 
  TEE-IO Device Architecture Overview    
 
10        Document Number:  354272 -001    
1 TEE -IO Device  Architecture Overview  
This chapter provides an overview of the TEE-IO device architecture . 
TEE-IO Security Model  
According to [PCIe TDISP 1.0] , the TEE -I/O security model is primarily intended to apply to 
systems using device resources directly assigned to VMs . The device resource  can be assigned 
as a TEE-IO Device Interface (TDI). The Before the TVM accept s a TDI , only the TSM and the 
host CPU are in the TEE TCB of the TVM.  Once the TVM accepts a TDI, the  TVM extends its TEE 
TCB to the entire TEE -IO device DSM, even if only one TDI  from the device is accepted by the 
TVM.  
The table 1-1 provides a summary of the shared security responsibility model of TDISP:  
Table 1 -1: Component in TEE -IO Security Model  
Component  Role  Responsibilities  
TSM  TEE TCB for TVM , a 
logic entity in a host.  Enforce security policies on the host . 
DSM  TEE TCB for TVM , a 
logic entity in a device  Enforce security policies on the device.  
TVM  TEE virtual machine  on 
host  Admit the DSM  into the TEE TCB.  Accept the TDI.  
TDI Portion of the device 
assigned to a TVM  Provide device function s to a TVM.  
VMM  Resource Manager  Attach and detach  TDIs to a TVM . 
 
Figure 1 -1: Component in TEE -IO 
TEE-IO Device Architecture Overview    
 
11        Document Number:  354272 -001    
 
Security Mode l for the Device  
According to  [PCIe TDISP 1.0]  (11.1 Overview of the TEE -I/O Security Model as it Relates to 
Devices, page 11 ), the security object ive for a TEE -IO device is to protect the TVM data, code, 
and execution state  with respect to : 
• Confidentiality : protection from disclosure to entities such as firmware, software, or 
hardware not in the TEE TCB of the TVM ( e.g., other TVMs, VMM, etc.).  
• Integrity : protection from modification by entities such as firmware, software, or 
hardware not in the TEE TCB of the TVM  (e.g., other TVMs, VMM, etc.).  Replay -
protection of the TVM data  is also in scope . 
There is no requirement for the  protection of TVMs against denial -of-service attacks.  
To achieve these  security objective s, the device shall support:  
1. Device Identity Authentication and Measurement Reportin g. In order to  protect a 
TVM from TEE -IO device  identity spoofing , the device shall implement  a root -of-trust  
(ROT)  for measurement (RTM), storage (RTS) and reporting (RTR) to support identity 
authentication and measurement reporting.  The device debug inte rface shall not 
impact the device security properties. See Chapter 4 for detail . 
2. Authenticated Secure Communication . The device shall use a secure communication 
channel to transfer the trusted data between the host and the device. The secure 
channel  shall provide confidentiality, integrity , replay protection  and message  ordering 
protection . See Chapter 2 Secure Protocol and Data Model ( SPDM ) for management 
communication  channel  and Chapt er 3 Integrity and Data Encryption ( IDE) stream  for 
data communication  channel . 
3. TEE Device Interface (TDI) Management . The device shall support locking down 
configurations of the TDI, reporting the configuration in a trusted manner, securely 
placing TDIs t o operational state, and tearing them down securely when the TDI is 
detected . See Chapter 2 TEE Device Interface Security Protocol (TDISP) and Chapter 3 
PCI Express Transaction Layer Packet ( TLP) Rule for TDI . 
4. Device Security Architecture . The device shall provide isolation and access control for 
the TVM data in the device for protection against the entities not in the trust boundary  
of TVM  (such as the VMM, other TVM s, untrusted device component, other TDI s). The 
device should implement A dvanced Error Reporting (AER) to report  error s according to 
[PCIe TDISP 1.0]  page 13 . See Chapter 4 for detail.  
Implementing TEE -IO Device Stack  
According to [PCIe TDISP 1.0]  page 13 , the device memory could be system level memory 
(defined as non -TEE memory), or TDI specific memory (defined as TEE memory). The TEE TEE-IO Device Architecture Overview    
 
12        Document Number:  354272 -001    
memory shall  have mechanisms to ensure the confidentiality and optional integrity  of TVM 
data.  
The device implementation to support TEE -IO can be separated as software stack and 
hardware stack. Usually, the TEE-IO software stack  is to transfer the management 
information, such as device identity, device measurement, data encryption key, TDI lock, TDI 
report, TDI attachment, TDI detachment,  etc. 
The TEE-IO hardware stack  provides link encryption to ensure the link’s confidentiality and 
integrity, downstream access control logic to prevent non -trusted MMIO access to TEE 
memory, and upstream logic to ensure device DMA TEE data sent with encryp ted IDE TLP.  
Secure Device Interface Lifecycle  Example  
 
The following figures show the high -level software flow for TEE -IO architecture as a typical 
example.  
Step 1 (SPDM setup). See Figure 1 -2. The VMM calls the TSM to establish the SPDM session 
with the device. Then the TSM will own the SPDM session. The TSM will also collect the device 
certificate and measurement and return to VMM for device attestation later. This step is per 
device.  
Step 2 (IDE Stream setup). See Figure 1 -3. The VMM calls the TSM to us e IDE_KM to set up  the 
default IDE selective steam  with the device. The IDE_KM is an SPDM  vendor defined protocol  
sent in the SPDM session. The TSM will also configure the SOC IDE key programming register 
to ensure the IDE selective stream between SOC and device is established. After this step, the 
device and host SOC have two secure communication sessions. The SPDM session is a 
software sessi on, which is used for software configuration such as IDE_KM and TDISP. The IDE 
steam is hardware session, which is used to secure the PCI Express  TLP. This step is also per 
device.  
Step 3 (TDI assignment ). See Figure 1 -4. The VMM locks the TDI and launches  a TVM, then 
assigns the TDI to the T VM. 
• The T VM will get the device certificate and measurement from the TSM, then the T VM will 
verify the device based on a T VM specific policy. For example, the device certificate must 
have a trusted root Certificate Authority ( CA) and the device measurement must match the 
latest reference manifest published by the device vendor. If the verification passes, the T VM 
can accept the  TDI and use TDISP protocol to manage the TDI. If the verification fails, the 
TVM will reject the device.  
• After the device is approved by the T VM, the VMM sets up the DMA and MMIO for the TD I 
and lets the TVM accept the configuration.  
• Now T VM can start the  TDI and use trusted DMA and MMIO to communicate with the TDI. 
This step is per device interface.  TEE-IO Device Architecture Overview    
 
13        Document Number:  354272 -001    
The VMM can repeat the same  above process to assign another TDI to another T VM. See 
Figure 1 -5. Note: One T VM may accept multiple TDIs. But one TDI must not b e assigned to 
more than one T VM. 
If a TDI is no longer needed, then the T VM or VMM can stop the TDI. If all TDIs in a device are 
removed, the VMM can remove the IDE stream and terminate the SPDM session for the device.  
Appendix B provides more detail on SP DM management, IDE Stream management, and TDI 
lifecycle management.  
 
Figure 1 -2:  Device SPDM Session Setup for Secure Communication  
 
Figure 1-3: Device  IDE Setup for Link Encryption  
 
TEE-IO Device Architecture Overview

14        Document Number:  354272 -001    
 
Figure 1-4: TVM Launch and TDI Start  
 
Figure 1-5: Another T VM Launch and TDI Start  
 
2     TEE-IO Software Stack    
 
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2     TEE -IO Software Stack  
This chapter describes the TEE-IO software stack  requirement for the  device.  The device TEE-
IO software stack implements the responder role of the secure device management protocols 
(i.e., SPDM, IDE_KM and TDISP).  
Software Stack Overview  
Figure 2 -1 shows one example of implementing the TEE-IO software stack in the device.  
The purpose of the TEE Device Interface Security Protocol ( TDISP ) protocol is to manage the 
TDI. The purpose of the Integrity a nd Data Encryption Key Management ( IDE_KM ) protocol is 
to configure the IDE keys  for the PCIe Root Port . Both  IDE_KM and TDISP are application -level 
protocols  that are transported within a Secure Protocol and Data Model ( SPDM ) secure 
session  for transport level protection . The SPDM messages are sent and received via PCI Data 
Object Exchange ( DOE) interface.  
 
Figure 2 -1: Device DSM Software Stack  
On the host side, the VMM manages the DOE mailbox to send or receive SPDM messages. The 
TSM acts as the security policy enforce to encrypt and decrypt SPDM secure messages, 
including IDE_KM message and TDISP message. At runtime, the VMM or TVM request s the  
TSM to generate a protocol message request . Then the VMM send s the request to the device 
 
16        Document Number:  354272 -001    
DOE mai lbox . Later, the VMM receives the response from the DOE mailbox and sends back to 
TSM to process it.  
On the device side, there should be a listener to wait for SPDM messages. Then the SPDM 
stack in DSM will decrypt the SPDM secure messages and dispatch to TDISP or IDE_KM 
callback to process the TDISP or IDE_KM request message. Later, DSM will encrypt the TDISP 
or IDE_KM response message and sends to DOE mailbox on the device.  
Device Communication (DOE)  
PCI Express Data Object Exchange (DOE)  ECN defines a mailbox mechanism for the host 
software to perform data object exchange with the device, such as a SPDM message or a 
secure SPDM message. The host  uses the DOE to exchange messages  with the device.  One  
device may support multiple DOE mailboxes.  
Requirement:  
1. The d evice shall support SPDM over PCI DOE . 
2. The device shall expose DOE Extended Capability registers for capability detection and 
control . [PCIe DOE 1.0]  7.9.xx Data Object Exchange (DOE) Exte nded  
Capability . 
3. The device shall support the DOE 1.0 protocol including DOE Discovery (Data Object 0), 
CMA/SPDM (Data Object 1), Secure CMA/SPDM (Data Object 2) . [PCIe DOE 1.0]  6.xx Data 
Object Exchange (DOE)  and [PCIe IDE 1.0]  6.xx Data Object Exchang e (DOE) . 
4. The device shall provide  the DOE Extended Capability within function 0 to support the 
establish ment of  the SPDM session and transport secured  messages . [PCIe TDISP 1.0]  11.2.2 
TDISP message transport . 
 
For TDX Connect compatibility, please refer to Appendix A “ DOE ” section.  
Device Attestation (SPDM)  
The TVM  need s to offload the confidential workload to the device TDI. As such, the T VM 
need s to verify the device.  
PCI Express Component Measurement and Authentication (CMA)  ECN defines the 
mechanism based upon Secure Protocol and Data Model (SPDM). The DSM provides the 
device certificate, authentication, and  measurement reporting via SPDM.  
1. The device shall support SPDM version 1.2 . 2     TEE-IO Software Stack    
 
17        Document Number:  354272 -001    
2. The device shall support SPDM capability: CERT_CAP and MEAS_CAP , and support 
GET_DIGEST, GET_CERTIFICATE, and GET_MEASUREMENTS.  
3. The device shall support at least one of BaseAsymAlgo listed in CMA ECN: 
TPM_ALG_RSASSA_3072 , TPM_ALG_ECDSA_ECC_NIST_P256,  
TPM_ALG_ECDSA_ECC_NIST_P384 . 
4. The device shall support at least one of BaseHashAlgo listed in CMA ECN: 
TPM_ALG_SHA_256, TPM_ALG_SHA_384 . 
5. The d evice shall support at least one of MeasurementHashAlgo listed in CMA ECN: 
6. The d evice shall support MeasurementSpecification: DMTF (bit 0) . 
7. The d evice certificate shall follow DSP0274 requirement. The X.509 certificate shall follow 
SPDM 1.2.1 Table 33 – Required fields . The X.509 certificate OID shall follow SPDM 1.2.1, 
10.8.2, SPDM certificate requirements and recommendations, including 10.8.2.1 Extended Key 
Usage authentication OIDs, 10.8.2.2 SPDM Non -Critical Certificate Extension OID.  
8. The device shall only return the DMTFSpecMeasurementValueType defined in SPDM 1.2.1 . 
Table 45 – DMTF measurement specification format.  
9. The DICE device shall support ALIAS_CERT_CAP  and return DICE alias certificate.  
10. The DICE alias certificate shall include DiceTcbInfo OID. The DiceTcbInfo  shall include the 
firmware information such as digest and/or secure version number (SVN).  
 
For TDX Connect compatibility, please refer to Appendix A “SPDM” section.  
Software Secure Communication (SPDM)  
The TSM need s to establish an authenticated secure se ssion with the device for integrity and 
confidentiality. This software secure session is used to exchange the hardware encryption key 
such as IDE_KM protocol, or TDI management such as TDISP protocol.  
DMTF Secure Protocol and Data Model (SPDM)  provides an authenticated secure session 
between the host TSM and the device  DSM . PCI Express Integrity and Data Encryption (IDE) 
ECN and TEE Device Interface Security Protocol (TDISP) ECN rely on SPDM for the secure 
management data communication.  
1. The device shall support SPDM capability: ENCRYPT_CAP, MAC_CAP, and KEY_EX_CAP , and 
support KEY_EXCHANGE, FINISH, and END_SESSION.  2     TEE-IO Software Stack    
 
18        Document Number:  354272 -001    
2. The d evice shall support at least one of DHE Group: secp256r1 , secp384r1 . 
3. The device shall support at least one of AEAD Cip her Suite: AES -256-GCM . 
4. The device shall support Key Schedule Algorithm: DMTF . 
5. The device shall support DSP0274 OtherParamsSupport.OpaqueDataFmt1.  
6. The device shall use DSP0277 version  1.1 as Secured Message  transport binding version in 
the Secure Message opaque data . 
7. The device should support KEY_UPD_CAP. If the device supports KEY_UPD_CAP, the device  
shall support update keys for both directions  with UpdateAllKeys.  
8. The device may support HBEAT_CAP.  If it is supported, the device session shal l be 
terminated after twice HeartbeatPeriod.  
9. The DSM shall teardown the session i f a firmware update is triggered, if the SPDM 1.2  
SessionPolicy.TerminationPolicy = 0. 
10. The DSM shall keep the confidentiality of the SPDM session key.  
11. The DSM may perform  mutual authentication  based upon the TSM capability  during SPDM 
session establishment, or DSM may perform TVM authentication in an established SPDM 
session.  This is use case specific.  
NOTE: The TSM may be implemented in software, making it  hard to provision a public 
certificate and a private key to sign the SPDM message at session creation. The TSM may use a 
non-standardized TEE -Quote based certificate as described in Remote -Attestation TLS (RA -
TLS) to support quote -based mutual atte station.  Or the TSM/DSM may use two -phase 
authentications: In phase 1 TSM attests the device as described in SPDM specification; in 
phase 2 DSM authenticates the host environment including host TEE TCB  (CPU and  TSM ), host 
TVM, and so on  with an implementa tion specific mechanism.  
 
Link Encryption Key Management (IDE_KM)  
The TSM need s to setup link encryption with the device to mitigate possible attack s in the 
path between the host  and device.  
PCI Express Integrity and Data Encryption (IDE)  ECN provides  confidentiality, integrity, and  
replay protection for Transaction Layer Packet ( TLP) transmitted and received between two 
PCI Express  ports.  The TSM uses  IDE key management (IDE_KM) protocol to manage the IDE 
keys with the DSM, such as programming the IDE key, starting or stopping the IDE stream. The 2     TEE-IO Software Stack    
 
19        Document Number:  354272 -001    
DSM c onfigur es the IDE encryption keys in the device.  Please refer to  Chapter 3, IDE Stream 
section , for an  example on how to setup IDE stream, stop IDE stream, etc.  
1. The DSM shall support  IDE_KM payload in SPDM vendor defined message . [PCIe IDE 1.0]  
6.99.3 IDE Key Management (IDE_KM) , page 19.  
2. The d evice shall expose DOE for IDE  in Function 0 . [PCIe IDE 1.0]  6.99.3 IDE Key 
Management (IDE_KM) , page 20.  
3. The DSM shall support IDE_KM messages  QUERY . [PCIe IDE 1.0]  6.99.3 IDE Key 
Management (IDE_KM) , page 21.  
4. The DSM shall support IDE_KM messages KEY_PROG . [PCIe IDE 1.0]  6.99.3  IDE Key 
Management (IDE_KM) , page 22.

Management (IDE_KM) , page 22.  
5. The DSM shall support IDE_KM messages SET_K_GO . [PCIe IDE 1.0]  6.99.3 IDE Key 
Management (IDE_KM) , page 23.  
6. The DSM shall support IDE_KM messages SET_K_STOP . [PCIe IDE 1.0]  6.99.3 IDE Key 
Management (IDE_KM) , page 24.  
7. The DSM shall handle  IDE enable/disable i n IDE Stream Enable bit , according to [PCIe IDE 
1.0] 6.99.3 IDE Key Management (IDE_KM) , page 24.  
8. The DSM shall manage the Secure/Insecure State correctly  in SPDM secure session , 
according to [PCIe IDE 1.0]  6.99.3 IDE Key Management (IDE_KM) , page 24.  
9. The DSM shall handle key correctly , according to [PCIe IDE 1.0]  6.99.3 IDE Key Management 
(IDE_KM) , page 26.  The k ey set bit shall be used for the key update . 
 
For TDX Connect co mpatibility, please refer to Appendix A “ IDE_KM ” section.  
Device Interface Management (TDISP)  
One device may be used by multiple T VMs. The VMM need s to assign the TDI in the device to 
the T VM. Also , the T VM needs to decide to start  or stop the TDI. 
PCI Exp ress TEE Device Interface Security Protocol (TDISP)  ECN  defines such mechanism . 
The T VM and VMM may use TDISP protocol to manage  the device TDI. The DSM provides the 
interface management, such as TDI configuration lock with policy (such as NO_FW_UPDATE) 
and reporting, and TDI attach and detach.  
Requirement:  2     TEE-IO Software Stack    
 
20        Document Number:  354272 -001    
1. The DSM shall ensure the IDE _KM (for IDE keys establishment) and TDISP  (for TDI 
management)  using same SPDM session . [PCIe TDISP 1.0]  11.1 Overview of the TEE -I/O 
Security Model as it Relates to Devices, page 15.  
2. If implemented , the DSM shall follow the peer -to-peer  (P2P)  communication rule  to set up  
P2P stream , according to [PCIe TDISP 1.0]  11.2 TDISP Rules, page 1 9. 
3. The DSM shal l support TDISP payload in SPDM vendor defined message, according to [PCIe 
TDISP 1.0]  11.2.2  TDISP Message Transport, page 21.  
4. The DSM shall follow Requirements for Responders (DSM), according to [PCIe TDISP 1.0]  
11.2.4  Requirements for Responders (DSM), page 2 2. 
5. The DSM shall follow DSM Tracking and Handling of Locked TDI Configurations , according 
to [PCIe TDISP 1.0]  11.2. 6 DSM Tracking and Handling of Locked TDI Configurations , page 2 3. 
6. The DSM shall support TDISP required message s: TDISP_VERSION, TDISP_CAPABILITIES, 
LOCK_INTERFACE_RESPONSE, DEVICE_INTERFACE_REPORT, DEVICE_INTERFACE_STATE, 
START_INTERFACE_RESPONSE, STOP_INTERFACE_RESPONSE . 
7. The DSM shall follow TDISP Message Format and Protocol Versioning, according to [PCIe 
TDIS P 1.0]  11.3.3  TDISP Message Format and Protocol Versioning , page 28.  
8. The DSM shall support  GET_TDISP_VERSION  according to [PCIe TDISP 1.0]  11.3.4  
GET_ TDISP _VERSION, page 30 and 11.3.5 TDISP_VERSION, page 30.  
9. The DSM shall support GET_TDISP_CAPABILITI ES according to [PCIe TDISP 1.0]  11.3.6  
GET_ TDISP _CAPABILITIES, page 30 and 11.3. 7 TDISP_ CAPABILITIES , page 3 1. 
The DSM shall support  a DEV_ADDR_WIDTH  that is equal to or larger than host address width, 
to prevent address alias attack.  
10. The DSM shall support LOCK_INTERFACE_REQUEST according to [PCIe TDISP 1.0]  11.3.8  
LOCK_INTERFACE_REQUEST, page 3 1 and 11.3. 9 LOCK_ INTERFACE_RESPONSE , page 3 4. 
11. The DSM shall support GET_DEVICE_INTERFACE_REPORT according to [PCIe TDISP 1.0]  
11.3.10  GET_DEVICE_INTERFACE_REPORT, page 35 and 11.3.11 
DEVICE_INTERFACE_REPORT, page 3 6. The DSM shall generate the TDI report according to 
[PCIe TDISP 1.0]  Table 15 TDI Report  Structure , page 37. 
12. The DSM shall support GET_DEVICE_INTERFACE_ STATE  according to [PCIe TDISP 1.0]  
11.3.1 2 GET_DEVICE_INTERFACE_ STATE , page 40 and 11.3.1 3 DEVICE_INTERFACE_ STATE , 
page 40. 
13. The DSM shall support START_INTERFACE_REQUEST according to [PCIe TDISP 1.0]  
11.3. 14 LOCK_INTERFACE_REQUEST, page 40 and 11.3. 15 START_INTERFACE_RESPONSE, 
page 4 1. 2     TEE-IO Software Stack    
 
21        Document Number:  354272 -001    
14. The DSM shall support STOP_INTERFACE_REQUEST according to [PCIe TDISP 1.0]  11.3.16  
LOCK _INTERFACE_REQUEST, page 41 and 11.3.17 STOP_INTERFACE_RESPONSE, page 4 2. 
15. If implemented, t he DSM shall support BIND_P2P_STREAM_REQUEST according to [PCIe 
TDISP 1.0]  11.3.1 8 BIND_P2P_STREAM_REQUEST, page 4 2 and 11.3.1 9 
BIND_P2P_STREAM_RESPONSE, page 4 3. 
16. If implemented, the DSM shall support UNBIND_P2P_STREAM_REQUEST according to 
[PCIe TDISP 1.0]  11.3.20  UNBIND_P2P_STREAM_REQUEST, page 43 and 11.3.21 
UNBIND_P2P_STREAM_RESPONSE, page 4 4. 
17. If implemented, the DSM shall support SET_MMIO_ATTRIBUTE_REQ UEST  according to 
[PCIe TDISP 1.0]  11.3.2 2 SET_MMIO_ATTRIBUTE_REQUEST , page 4 4 and 11.3.2 3 
SET_MMIO_ATTRIBUTE _RESPONSE, page 4 5. 
18. The DSM shall support TDISP_ERROR according to [PCIe TDISP 1.0]  11.3.24  
TDISP_ERROR, page 4 6. 
19. If implemented, the DSM shall support VDM_REQUEST  according to [PCIe TDISP 1.0]  
11.3.2 5 VDM_REQUEST , page 4 8 and 11.3.26  VDM_RESPONSE, page 48.  
 
For TDX Connect compatibility, please refer to Appendix A “TDISP” section.  
Implementation Reference  
SPDM  softwa re stack  
The DMTF open sourced SPDM sample implementation at https://github.com/DMTF/libspdm . 
Table 2 -1: SPDM software Stack Reference  
Component  Purpose  URL  
spdm _resp
onder_lib  Responder library. It can be used 
on the device side.  https://github.com/DMTF/libspdm/tree/
main/library/spdm_responder_lib   
spdm_requ
ester_lib  Requester library. It can be used to 
test the device . https://github.com/DMTF/libspdm/tree/
main/library/spdm_requester_lib   
spdm_devic
e_secret_lib
_sample  sample device li brary to support 
measurement reporting and digital 
signature generation on the device 
side  https://github.com/DMTF/libspdm/tree/
main/os_stub/spdm_device_secret_ lib_
sample   2     TEE-IO Software Stack    
 
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spdm -emu  An SPDM  requester emulator, 
which may be used to test the 
device SPDM stack.  https://github.com/DMTF/spdm -emu  
spdm -
dump  A tool to dump SPDM messages  
with PCAP format.  https://github.com/DMTF/spdm -dump  
SPDM -
Responder -
Validator  A test suite for  the SPDM device  https://github.com/DMTF/SPDM -
Responder -Validator  
 
IDE_KM software stack  
The DMTF open sourced SPDM sample implementation includes an IDE_KM software 
example . 
Table 2 -2: IDE_KM software Stack Reference  
pci_ide_km
_responder
_lib Responder library. It can be used 
on the device side.  https://github.com/DMTF/spdm -
emu/tree/main/library/pci_ide_km_resp
onder_lib   
_requester_
lib Requester library. It can be used to 
test the device . https://github.com/DMTF/spdm -
emu/tree/main/library/pci_ide_km_requ
ester_lib   
_device_lib
_sample  sample device library to support 
IDE_KM messages.  https://github.com/DMTF/spdm -
emu/tree/main/library/pci_ide_km_devi
ce_lib_sample   
 
TDISP software stack  
The DM TF open sourced SPDM sample implementation includes a TDISP software example . 
Table 2 -3: TDISP software Stack Reference  
pci_ tdisp _re
sponder_lib  Responder library. It can be used 
emu/tree/main/library/pci_tdisp_reques
ter_lib   
quester_lib  Requester library. It can be used to 
test the device.  https://github.com/DMTF/spdm -
emu/tree/main/library/pci_tdisp_respo
nder_lib   2     TEE-IO Software Stack    
 
23        Document Number:  354272 -001    
pci_ tdisp _d
evice_lib_sa
mple  sample device library to support 
emu/tree/main/library/pci_tdisp_device
_lib_sample   
 
  3     TEE-IO Hardware Stack    
 
24        Document Number:  354272 -001    
3     TEE -IO Hardware Stack  
This chapter describes the TEE-IO hardware stack  requirement on the device side.  The TEE-IO 
hardware stack  is the data encryption engineer  to support trusted MMIO and trusted DMA,  
and hardware registers such as data encryption key, TDI state, etc.  
IDE Stream  
IDE secures the TLP traffic from one port to ano ther port. IDE TLP Prefix includes a “ T bit ”, 
which indicates the TLP originated from within a trusted execution environment. The “T bit ” 
provides a mechanism to distinguish TLPs that are associated with a T VM. IDE mechanisms 
ensure that the T bit (like other TLP content) is secured during transit . 
IDE Stream State Machine includes Insecure or Secure state. See figure 3 -1. 
Secure State : The  device IDE Stream  shall enter Secure State only after all necessary steps are 
done, including the keys are programmed, and the IDE stream is enabled.  
Insecure State : The device IDE Stream  shall enter  an Insecure state if any necessary steps are 
not met. For example, the IDE stream is disabled,  or IDE Check Failed  error happens . 
Ready sub -state : This is a sub -state of Insecure state. The device has all keys programmed .

IDE Stream  
Ready sub -state : This is a sub -state of Insecure state. The device has all keys programmed . 
The only rest step is to trigger  IDE stream . The trigger  action requires both K_SET_GO 
message s and IDE Stream E nable bit set in the IDE Extended Capability Register . 3     TEE-IO Hardware Stack    
 
25        Document Number:  354272 -001    
 
Figure 3 -1: IDE Stream State Machine  (Source: [PCIe IDE 1.0])  
 
1. The device shall maintain the IDE Stream Secure State and Insecure State , according to 
[PCIe IDE 1.0]  6.99. 1 IDE Stream and TEE State Machines , page 16.  
2. The device shall implement IDE Extended Capability in function 0.  [PCIe IDE 1.0]  6.99. 2 IDE 
Stream Establishment, page 18.  
3. The devi ce shall follow IDE TLP rule , according to [PCIe IDE 1.0]  6.99. 4 IDE TLPs, page 29. 
The device shall use IDE TLP Prefix for all IDE TLPs.  
4. The device shall follow a selective IDE stream rule , according to [PCIe IDE 1.0]  6.99. 4 IDE 
TLPs, page 33. The device shall follow “ Table XX – TLP Types for Selective IDE Streams”  to 
only permit MRd, MRdLk, MWr, CfgRd1, CfgWr1, DMWr, Msg*, MsgD*, Cpl, CplD, CplLk, CplDLk, 
FetchAdd, Swap, and CAS. The IORd, IOWr, CfgRd0, and CfgWr0 are not encrypted . 
3     TEE-IO Hardware Stack    
 
26        Document Number:  354272 -001    
5. The device s hall follow IDE TLP sub -stream rule , according to [PCIe IDE 1.0]  6.99. 5 IDE TLP 
Sub-streams, page 3 8. 
6. The device shall follow IDE TLP Aggregation, if it is supported , according to [PCIe IDE 1.0]  
6.99. 6 IDE TLP Aggregation, page 40.   
7. The device shall follow other IDE Rules for Non -Posted IDE Requests , according to [PCIe IDE 
1.0] 6.99. 8 Other IDE Rules, page 44.  
8. The device shall follow other IDE Rules for resets , according to [PCIe IDE 1.0]  6.99. 8 Other 
IDE Rules, page 44. Conventional Reset or Funct ion Level Reset (FLR) to a function with IDE 
shall change to Insecure state. FLR to a function without IDE shall not affect IDE operation.  
9. The device shall follow other IDE Rules for Access Control Services (ACS) , according to [PCIe 
IDE 1.0]  6.99. 8 Other IDE Rules, page 44.  
10. The device shall follow other IDE Rules for error handling , according to [PCIe IDE 1.0]  
6.99. 8 Other IDE Rules, page 45. Detecting IDE Check Failed error, MAC check failure, 
underflow or overflow of TLP counter shall change to  Insecure State.  
11. The device shall follow other IDE Rules for power management, according to [PCIe IDE 1.0]  
6.99. 8 Other IDE Rules, page 46. No_Soft_Reset bit shall be Set. All state related to keys and 
counters shall  be maintained in D0, D1, D2, and  D3hot. They may be maintained in D3cold.  
12. The device shall follow other IDE Rules for secure local environment , according to [PCIe 
IDE 1.0]  6.99. 8 Other IDE Rules, page 46. Attempts to modify IDE registers, BARs, and other 
structures that could affect the  security or an IDE Stream shall  be detected  and enter Insecure 
state . 
13. The device shall implement IDE Extended Capability , according to [PCIe IDE 1.0]  7.9.99 IDE 
Extended Capability, page 48.  
14. The d evice shall expose “TEE -IO Supported” in Device Cap ability Register. [PCIe TDISP 1.0]  
6.33.4 IDE TLPs, page 5 . 
15. The device  shall  implement bit 7 of Sub -Stream field as Reserved . [PCIe TDISP 1.0]  6.33.4 
IDE TLPs, page 5 . 
16. The device shall  follow rule when TEE -IO Supported is set, according to [PCIe TDISP 1.0]  
6.33.4 IDE TLPs, page 6.  
17. The device shall  follow rule for Non -Posted IDE Requests based upon  TEE-IO Supported 
bit, according to [PCIe TDISP 1.0]  6.33. 8 Other IDE Rules , page 7. 
 3     TEE-IO Hardware Stack    
 
27        Document Number:  354272 -001    
IDE Stream Precedence  
 
The device shall follow IDE stream precedence rule, according to [PCIe IDE 1.0] 6.99. 4 IDE 
TLPs, page 37. The rule is summarized as follows:  
a. For transmitter:  
if (IAAR and IRAR rule hit ) { 
    Stream ID := corresponding Stream ID  
} else if (default Selective IDE Stream is configured) {  
    Stream ID := default Selective IDE Stream ID  
} else if (Link IDE Stream is enabled) {  
    Stream ID := Link IDE Stream ID  
} else {  
    Stream ID := invalid // Not use IDE -TLP 
} 
Where IAAR == IDE Address Association Register , IRAR = IDE RID Association Register . 
b. For receiver : 
Stream ID := Stream ID in the received IDE TLP Prefix  
 
TEE Limited Stream  
TEE limited stream is optional. It indicates that only those TLPs that have the T bit Set are 
perm itted to be associated with  this Stream . This is for optimization purpose, because not all 
data in TVM requires the protection.  
Note:  This IDE features requires same capability to be supported and configured on the host 
Root Port to function correctly . For more details, p lease refer to [PCIe IDE 1.0] . 
Requirement  if implemented : 
1. If implemented, the device shall follow the description for TEE Limited Stream, according to 
[PCIe TDISP 1.0]  7.9.26.5.2: Selective IDE Stream Control Register, page 8 . 
Partial Header Encryption  
Partial header encryption is added in [PCIe 6.0]  as an opt ional feature. It provides the ability to 
reduce potential exposure to side -channel attacks by encryption some portions of the Header 3     TEE-IO Hardware Stack    
 
28        Document Number:  354272 -001    
of an IDE Memory Request while maintaining information that is required for TLP routing and 
low-level TLP processing in th e clear.  
Root Port  to function correctly . For more details, please refer to [PCIe IDE 1.0] . 
1. If implemented, the device shall follow the description for partial header encryption, 
according to [PCIe 6.0] 7.9.26.2 IDE Capability Register, 7.9.26.4.1 Link IDE Stream Control 
Register, 7.9.26.5.2 Selective IDE Stream Control Register.  
 
For TDX Connect  compatibility, please refer to Appendix A “IDE Stream” section.  
 
TDI TLP Rule  
The device function unit may have : 
• TDI: A Trusted Device Interface. It may be an entire device, a physical function (PF) or 
virtual function (VF). It may be in CONFIG_UNLOCK, CO NFIG_LOCK, RUN, or  ERROR 
state. A TDI shall be isolated from non -TDI and other TDIs by the DSM.  
• Non -TDI: A legacy device function unit, which cannot be assigned as a TDI by 
definition. It may be a physical function (PF) or virtual function (VF).  
• DSM : A device security manager, which is  the TEE TCB for all TDIs.  
A TDI state machine includes 4 states (see Figure 3 -2): 
CONFIG_UNLOCKED : This is the initial, default state of a TDI. There is no security property 
(confidentiality and optional integrity) that a TDI need s to provide to the TVM data.  The DSM 
shall not allow interface start.  
CONFIG_LOCKED : This is the intermediate transition s tate from default to RUN. To enter this 
state, the VMM should finish configuration, and TSM should explicitly send LOCK_INTERFACE. 
The DSM or TDI is expected to clean up and prepare to provide the security property. For 
example, all previous MMIO request s or DMA request s should be dropped.  
RUN : This is the actual functional state. TVM can send START_INTERFACE to explicitly request 
the TDI to enter this state. The TDI can perform trusted MMIO or DMA transaction to 
communicate with TVM.  
ERROR : This is the error state. When the DSM or TDI detects any change impacting device 
configuration or security in CONFIG_LOCKED or RUN state, the TDI sh all be changed to  ERROR 
state. TDI shall not expose any confidential TVM data. TDI may start cleaning up the TVM data.  3     TEE-IO Hardware Stack    
 
29        Document Number:  354272 -001    
 
Figure 3 -2: TDI State Machine  (Source: [PCIe TDISP 1.0])  
 
The host function unit may have  
• TEE VM (TVM) : A VM requiring the TEE capability. A TVM shall be isolated from  VMM, 
legacy VM, and other TVM by the TSM . 
• Legacy VM : A VM not requiring the TEE capability.  
• VMM : A system resource manager for TVM and Legacy VM.  
• TSM : A TEE security manager, which is TCB for all TVMs.  
The connection between the device and the host:  
• TVM < -> TDI : Follow TLP rules for MMIO, DMA, ATS, etc.  
• Legac y VM < -> TDI : Not the focus of the TDISP specification.  * 
• Legacy VM/VMM < -> Non -TDI: Legacy behavior. Out of scope.  
• TSM < -> DSM : Follow SPDM, IDE_KM, TDISP protocol.  
* NOTE: For Legacy VM < -> TDI, it is permitted for IDE streams established by the TSM to b e used 
to carry TLPs associated with legacy VMs. [PCIe TDISP 1.0]  11.1 page 14. For a TDI that supports 
assignment to Legacy VMs, if a TDI is assigned to a Legacy VM, the VMM assigns the TDI in 
CONFIG_UNLOCKED, and the TSM must ensure that the TDI remains in that state unless and 
until the TDI is removed from the Legacy VM and prepared for re -assignment to a TDI. [PCIe 
TDISP 1.0]  11.1 page 18.  
 
30        Document Number:  354272 -001

30        Document Number:  354272 -001    
According to [PCIe TDISP 1.0] , a device implementation may support legacy VM <> TDI. If a TDI 
is assigned to a lega cy VM, the TDI is allowed to transmit or receive messages (such as MMIO 
or DMA) in Non -IDE Stream in CONFIG_UNLOCK state. Once the TDI is asked to transit to 
CONFIG_LOCK state, the TDI should drain all pending requests and received data in 
CONFIG_UNLOCK st ate.  
 
In order to facilitate the TLP rule discussion, we define the following  term s: 
• Bound IDE stream : The IDE stream bound to a TDI. In normal case, i t is the default 
stream  in LOCK_INTERFACE_REQUEST  [PCIe TDISP 1.0] 11.3.8.  The IDE specification 
defined “default stream” in [PCIe IDE 1.0] 7.9.99.5.2  Selective IDE Stream Control 
Register.  If a device includes multiple TDIs, those TDIs may share the same default 
stream.  In direct peer to peer (P2P) case, the Bound IDE stream is t he P2P stream  in 
BIND_P2P_STREAM_REQUEST  [PCIe TDISP 1.0] 11.3. 18. 
• Non -Bound IDE Stream : The IDE stream not bound to this TDI.  
• Non -IDE Stream : The plaintext TLP (not encrypted) . 
• TEE-TLP: TLP Bound IDE stream  with  T=1.  
• Non -TEE-TLP: All the other not TEE -TLP, such as TLP Bound IDE stream  with  T=0, 
Non -Bound IDE Stream  with T=0 or T=1 , or Non -IDE Stream.  
NOTE: The “T bit” indicates that the TLP originated  from  within a trusted execution 
environment  (TEE). However, there is no bit to in dicate if the target  is within TEE or non -TEE. 
This is a known limitation so far. As such, the device should not use a common shared cache 
to store the data, unless the device cache ha s an attribute to identify if the cache -entry is 
private (TEE) or shared  (non -TEE).  
NOTE: the following  rules are only for TDI, but not for non -TDI. 
TDI as Completer  
Resource  definition : 
• TEE MMIO  (T-MMIO) : The TEE memory in the device , read/write from the host , which 
must have mechanisms to ensure the confidentiality of TVM data, and optionally 
integrity. [PCIe TDISP 1.0] 11.1. page 13. It is NON_TEE_MEM=0 in the TDI report  
structure . TEE MMIO is only present when TDI is in CONFIG_LOCK, RUN, or  ERROR state.  
TEE MMIO do es not exist when TDI is in CONFIG_UNLOCK state.  
• Non -TEE MMIO  (NT-MMIO) : The Non -TEE memory in the device, read/write from the 
host, which does not have above protection mechanism. It is NON_TEE_MEM=1 in the 
TDI report  structure . 
• CFG : The device configurat ion space read/write from the host.  It is not required that 
Configuration Requests to a TDI be secured . [PCIe TDISP 1.0] 11.2. page 20.  
Rule  definition : 
• Success (V): The device shall process and return success completion (SC) TLP for NPR.  3     TEE-IO Hardware Stack    
 
31        Document Number:  354272 -001    
• Reject (X): The device shall return an Unsupported Request (UR) TLP o r drop  the 
received TLP.  
NOTE:  
1. "If the result is a determination that the TLP must be rejected , the associated TDI must 
transition to ERROR where indicated , but no further error reporting or logging is required  to 
be performed on that TLP ,” [PCIe TDISP 1.0]  11.2. TDISP Rules  Page 18 . Here the “rejected” 
means the “IDE Check Failed” instead of access control rule. “no further error reporting  is 
required ” because there is no trusted  way to guarantee that the device error message is 
delivered to the TVM. The man -in-the-middle adversary can block or delay the error reporting 
regardless of whether  it is a hardware mechanism or a software mechanism. Please refer to 
Chapter 4, Error Handl ing Section.  
2. “If the result is a determination that the TLP must be rejected, … it is optionally permitted on 
a case -by-case  basis to handle a  Request as an Unsupported Request , and/or handle a 
Completion as an Unexpected Completion , or that the TLP be drop ped.” [PCIe TDISP 1.0]  11.2. 
TDISP Rules  Page 18 . In the case of rejection, the TLP can be responded with UR/UC or dropped.  
 
Table 3 -4, Table 3 -5 and Table 3 -6 are the rule summary of TDI acting as a Completer, 
according to [PCIe TDISP 1.0]  11.2 .1 TLP Rules, page 21. 
Table 3 -4: TEE-MMIO Rule Summary for TDI as Completer  
Access Control  CONFIG _UNLOCK  CONFIG _LOCK  RUN ERROR  
TEE-TLP N/A * T-MMIO ( X) T-MMIO (V)  T-MMIO ( X) 
Non -TEE-TLP N/A ** T-MMIO ( X) T-MMIO  (X) T-MMIO ( X) 
* By definition, the Bound IDE stream is only known after LOCK_INTERFACE_REQUEST is sent. 
As such, there is no TEE -TLP in CONFIG_UNLOCK . All TLP s in CONFIG_UNLOCK are non-TEE-
TLP.  
** By definition, the TDI does not provide confidentiality or optional integ rity of the TVM data  
in CONFIG_UNLOCK , if the TDI is assigned to a legacy VM . As such, the TDI does not have any 
TEE-MMIO , because a TDI is not required to protect confidential data placed into it in this 
state.  
Table 3 -5: NON -TEE-MMIO Rule Summary for TDI  as Completer  
TEE-TLP N/A NT-MMIO (V)  NT-MMIO (V)  NT-MMIO (V)  
Non -TEE-TLP NT-MMIO (V)  NT-MMIO (V)  NT-MMIO (V)  NT-MMIO (V)  
 
32        Document Number:  354272 -001    
Table 3 -6: CFG Rule Summary for TDI as Completer  
TEE-TLP N/A CFG  (V) CFG  (V) CFG  (V) 
Non -TEE-TLP CFG  (V) CFG  (V) CFG  (V) CFG  (V) 
 
NOTE:  
1. TEE MMIO : TEE MMIO is only allowed with bound IDE stream, T=1, and TDI in RUN.  
if ((TDI.STATE  != RUN) || 
    (TLP.T == 0) || 
    (STREAM_TYPE != IDE_TLP) || 
    (IDE_STREAM_ID != TDISP_BOUND_STREAM_ID ) || 
    (TLP.ADDRESS NOT IN STREAM-ASSOCIATION -RANGES[N] )) { 
    Access = Deny; 
} else { 
    Access = Allow;  
} 
2. Non -TEE MMIO : [PCIe TDISP 1.0]  mentioned the rule for TDI acting as a Completer: 
“Requests targeting device memory received with the T bit Set while in any state other than 
RUN must be rejected .”. That rule is superseded by “ The TDI’s handling is not modified by 
TDISP state for Receive d Memory Requests targeting MMIO with IS_NON_TEE_MEM Set .” 
3. CPL rule: The value of the T bit in the Completion(s) returned by the TDI must match  the 
value of the T bit in the corresponding Request.  [PCIe TDISP 1.0] . 
4. CFG  rule: It is not required that C onfiguration Requests to a TDI be secured.  [PCIe TDISP 
1.0] 11.2. page 20 . [PCIe IDE 1.0]  Table XX–TLP Types for Selective IDE Streams  mention s 
Type0 is not permitted for selective IDE stream s, because we do not expect that will happen. A 
proper  requester shall always use Type1 . An improper  requester may use Type0. The device 
may choose to accept or reject, but it does not impact security.  
 
TDI as Requester  
• DMA : The host me mory -read/write from the device. The device does not know if the 
host memory is TEE memory or non -TEE memory,  according to [PCIe TDISP 1.0] . 3     TEE-IO Hardware Stack    
 
33        Document Number:  354272 -001    
• MSI: The message signaled interrupt from the device to the host.  
• Trusted -MSI (T-MSI) : The LOCK_MSIX flag in LOCK_INTERFACE_REQUEST  is 1 and 
MSIX table is part of locked MMIO_RANGE . 
• Allowed  (V): The device can send the TLP.  
• Not allowed  (X): The device shall not send the TLP.  It is DSM/TDI’s responsibility.  
 
Table 3 -7, Table 3 -8, and Table 3 -9 are rule summary of TDI acting as a Requester , according 
to [PCIe TDISP 1.0]  11.2 .1 TLP Rules, page 20. 
Table 3 -7: DMA Rule Summary for TDI as Requester  
Operation  CONFIG _UNLOCK  CONFIG _LOCK  RUN ERROR  
TEE-TLP N/A DMA (X)  DMA (V)  DMA (X)  
Non -TEE-TLP DMA ( V) ** DMA (X)  DMA (X)  DMA (X)  
** DMA is allowed in CONFIG_UNLOCK,  if the TDI is designed to a Legacy VM.  
Table 3 -8: MSI Rule Summary for TDI as Requester  
TEE-TLP N/A MSI (X)  MSI (X)  MSI (X) 
Non -TEE-TLP MSI (V)  MSI (V)  MSI (V)  MSI (V)  
Table 3 -9: Trusted -MSI Rule Summary for TDI as Requester  
TEE-TLP N/A T-MSI (X)  T-MSI (V)  T-MSI (X)  
Non -TEE-TLP N/A ** T-MSI (X)  T-MSI (X)  T-MSI (X)  
** Trusted -MSI is not applicable , only non -trusted  MSI is allowed.  
NOTE:  
1. DMA  rule: DMA is only allowed with bound IDE stream, T=1, and when TDI in RUN.  
if (TDI.STATE  != RUN) { 
    Operation  = Deny; 
} else { 
    Operation  = Allow; 
    TLP.T = 1; 3     TEE-IO Hardware Stack    
 
34        Document Number:  354272 -001    
    STREAM_TYPE = IDE_TLP; 
    IDE_STREAM_ID = TDISP_BOUND_STREAM_ID ; 
} 
2. CPL rule: For Memory Reads issued by the TDI while in RUN, the corresponding 
Completion(s) must be handled normally  if and only if the TDI is still in RUN  and must 
otherwise be rejected . [PCIe TDISP 1.0] . “Still in RUN” means that the TDI shall  not change to 
ERROR state then back to RUN state again.  
 A TDI in RUN must ignore  the value of the T bit in Received Completions.  [PCIe TDISP 1.0] .

NOTE:  
} else { 
 
} 
 A TDI in RUN must ignore  the value of the T bit in Received Completions.  [PCIe TDISP 1.0] . 
The reason is that the host SOC implementation may set T=0 for non -TEE owned shared 
memory.  
Receipt of a Completion with UR/CA or Completion timeout  (following recovery retries)  for 
request initiated by a TDI in CONFIG_LOCK, RUN (with T=1) indicates occurrence of an 
uncorrectabl e error , TDI must  transition to ERROR. [PCIe TDISP 1.0]  11.4.3. Securing 
Interconnects.  
3. MSI rules:  The T -bit must  be set according to LOCK_MSIX flag in 
LOCK_INTERFACE_REQUEST  and MSIX table is part of locked MMIO_RANGE, if TDI is in RUN 
state . 
if ((TDI.STATE  == RUN) && 
(LOCK_MSIX flag  == 1) && 
(MSIX table is part of locked MMIO _RANGE)) { 
    TLP.T = 1; 
} else { 
    TLP.T = 0; 
} 
An MSI  with T -bit clear is always allowed in CONFIG_UNLOCK or ERROR state, although it is 
not explicit stated in TDISP specification, because there is no security property  required.  
ATS Rule  
The presence of DMA address translation in the host system has certain performance 
implications for DMA accesses.  To mitigate these impacts, a device may include an address 
translation cache  (ATC) , which is also known as device translation look -aside buffer ( Device 
TLB). Address translation service ( ATS ) uses a reques t-completion protocol between a Device 
and a Root Complex (RC) to provide translation services.  In addition, a new Address Type ( AT) 
field is defined within the Memory Read and Memory Write TLP. The new AT field could be 
Untranslated, Translation Request, Translated.  3     TEE-IO Hardware Stack    
 
35        Document Number:  354272 -001    
ATS improves the behavior of DMA based data movement. An associated Page Request 
service (PRS)  provides additional advantages by allowing DMA operations to be initiated 
without requiring that all the data to be moved into or out of system memor y be pinned.  
Allowing a device to operate more independently (to page fault when it requires memory 
resources that are not present) provides a superior level of coupling between device and host.  
ATS TLP Type  definition : 
• Translated read/write :  Follow the same rule  as Memory read/write  for DMA/MMIO . 
• Translation Request  (TRANS ): The t ranslation request from the device Address 
Translation Cache ( ATC ) to the host Translation Agent ( TA). 
• Translation Completion  (TRANS -CPL): The translation completion from the host TA to 
the device ATC.  
• Invalidate  Request (INVAL ): The invalidate request from the host TA to the device ATC.  
• Invalidate Completion (I NVAL-CPL) : The invalidate completion from the device ATC to 
the host TA.  
• Page Request ( PAGE ): The page request from the device  ATC to the host TA.  
• PRG Response (PGR -RSP) : The PRG response from the host TA to the device ATC.  
Table 3 -10, Table 3 -11, and Table 3 -12 are rule summary of ATS TLP , according to [PCIe 
TDISP 1.0]  11.4.10 , page 53. 
Table 3 -10: ATS  Invalidate Request  Rule Summary for TDI as Completer  
TEE-TLP N/A INVAL (V) INVAL  (V) INVAL  (V) 
Non -TEE-TLP INVAL  (V) INVAL  (V) INVAL  (V) INVAL  (V) 
 
1. INVAL  rule: Invalidation Request is allow ed in TEE -TLP or Non -TEE-TLP.  
2. INVAL-CPL rule: Invalidation Completion must  use the same IDE Stream as the Invalidation 
Request, and must match  the T bit value from the  Invalidation Request . 
Table 3 -11: ATS Translation Request Rule Summary for TDI as Requester  
TEE-TLP N/A TRANS  (X) TRANS  (V) TRANS  (X) 
Non -TEE-TLP TRANS  (V) ** TRANS  (X) TRANS  (X) TRANS  (X) 
** TRANS is allowed in CONFIG_UNLOCK, if the TDI is designed to a Legacy VM.  
Table 3 -12: ATS Page Request Rule Summary for TDI as Requester  
TEE-TLP N/A PAGE (X)  PAGE (V)  PAGE (X)  3     TEE-IO Hardware Stack    
 
36        Document Number:  354272 -001    
Non -TEE-TLP PAGE (V)  ** PAGE (X)  PAGE (X)  PAGE (X)  
** PAGE is allowed in CONFIG_UNLOCK, if the TDI is designed to a Legacy VM.  
 
1. TRANS  rule: Translation Request is only allowed with T -bit set and in RUN state . Although it 
is not explicit stated in TDISP specification, Translation Request is not allowed in other state 
(CONFIG_UNLOCK or ERROR ) or without T -bit set . 
2. TRANS -CPL rule:  Translation Completion(s) received with the T bit Clear  must transition the 
TDI to ERROR . 
3. PAGE  rule: Page Request is only allowed with T -bit set and in RUN state.  
4. PGR -RSP  rule:  A PRG Response  must use the same IDE Stream as the corresponding Page 
Request and must have the T bit Set.  A violation of this rule must result in the TD I transitioning 
to ERROR . 
Peer to Peer  (P2P)  
PCIe peer to peer (P2P) enables  two PCIe device  endpoints (EPs)  to transfer data between 
each other without using host memory as a temporary storage.  There are two types of P2P . 
See figure 3 -3. 
• Direct P2P : Two endpoints set up a dedicated P2P IDE stream with TDISP 
BIND_P2P_STREAM message.  This feature requires the ATS  is support and enabled for 
the device.  
• P2P via  Root Complex : Two endpoints set up two different IDE stream s with Root 
Complex.  If EP1 needs to send TLP to EP2, Root Complex will decrypt TLP in IDE 
stream 1 and encrypt it in IDE stream 2 . 
 
Figure 3 -3: P2P  types  
 
The TLP rule for “ P2P via  Root Complex”  is same as the TLP rule for TEE -MMIO  (Table 3 -4), 
Non -TEE-MMIO  (Table 3 -5), DMA  (Table 3 -7). 
 
37        Document Number:  354272 -001    
 
For TDX Connect compatibility, please refer to Appendix A “Access Control in TDX Connect” 
section.  
 
TDISP Interoperability  with PCIe Capabilities  
MSI-X 
TDISP provides an optional support for TDIs to lock  the MSI -X table the Pending Bit Array 
(PBA) in order enable trusted interrupts to TVM sending MSI -X requests using IDE-TLPs . 
1. The device shall expose the MSI -X Capability register to the host.  
2. The DSM shall lock the MSI -X table and PBA if indicated by the 
LOCK_INTERFACE_REQUEST  FLAG S (Bit 2 – LOCK_MSIX ). 
3. The DSM shall report the MSI-X capability message control register state  in TDI Report 
MSI_X_MESSAGE_CONTROL, according to [PCIe TDISP 1.0]  Table 15 TDI Report Structure , 
page 37.  
ATS 
ATS is an optional feature , this document does not cover TDISP with ATS enabled devices. For 
more details, please refer to [PCIe T DISP 1.0] . 
Direct P2P 
TDISP provides an optional mechanism to configure direct TDI P2P instead of using “P2P via 
Root Complex” . This document does not cover TDISP with direct P2P enabled devices. For 
more details, please refer to [PCIe TDISP 1.0] . 
PASID  
PASID is an optional feature that enables sharing of a single Endpoint device across multiple  
processes while providing each process a complete virtual address space . This document 
does not cover TDISP with ATS enabled devices. For more details, please refer to [PCIe TDISP 
1.0]. 
LNR 
LNR is deprecated in PCRE 6.0 , this document does not cover TDISP with LNR  enabled 
devices. For m ore details, please refer to [PCIe TDISP 1.0] . 3     TEE-IO Hardware Stack    
 
38        Document Number:  354272 -001    
TPH 
TLP Processing Hints  (TPH)  is an optional feature that provides hints in Request TLP headers 
to facilitate optimized processing of Requests that target Memory Space.  This document does 
not cover TDISP with  TPH enabled devices. For more details, please refer to [PCIe TDISP 1.0] . 
 
For TDX Connect compatibility, please refer to Appendix A “TDISP” section.   4     Device Security Architecture    
 
39        Document Number:  354272 -001    
4     Device Security Architecture  
This chapter describes the device security architecture  requirement.  
Resource Isolation and Protection  
DSM shall implement access control and isolation mechanisms:  
1. The device  shall isolate t he data for TDI from non -TDI. 
2. The device shall isolate the data for one TDI from other TDI s. 
3. The device shall scrub the confidential information in case of TDISP  STOP_INTERFACE, data 
integrity error, conventional reset, function level reset , according to [PCIe TDISP 1.0]  11.3.16.  
STOP_INTERFACE_REQUEST , 11.5.6.  Data Integrity Errors , 11.4.8.  Conventional Reset, 11.4.9.  
Function Level Reset . 
4. The device should follow good practice including : securing secrets through the use of local 
encryption, access control, and/or other mechanisms ; ensuring that secure data cannot “leak” 
due to errors, power management, or other operations ; ensuring that secret keys are never 
exposed or stored in non -secure buffers ; ensuring that the establishment & management of 
TEEs is itself secure , according to [PCIe IDE 1.0]  6.99 Implementation Note.  
Address Transla tion  
Device may implement ATS.  
1. TEE-I/O capable devices must enforce integrity of the Address Translation Cache (ATC) such

1. TEE-I/O capable devices must enforce integrity of the Address Translation Cache (ATC) such 
that the  translations provided by the Root Complex cannot be modified through untrusted 
accesses.  [PCIe TDISP 1.0]  11.4.10, page 54.  
Device Resource  
1. The DSM shall not support I/O resource for T VM, according to [PCIe TDISP 1.0]  11.2 TDISP 
Rules, page 20. 
 
Device Identity and Measurement Reporting  
DSM shall implement root of trust (ROT) for device attestation.  
Requirement:  4     Device Secur ity Architecture    
 
40        Document Number:  354272 -001    
1. The device shall support device identity and authentication, according to [PCIe TDISP 1.0]  
11.4.1 Device Identity and Authentication , page 49. 
2. The device shall support firmware and configuration measurements, according to [PCIe 
TDISP 1.0]  11.4.2 Firmware and Configuration Measurement , page 49. 
3. The DSM  shall provide ROT for storage (RTS) to provide the  confidentiality for the  device 
private key. 
4. The DSM  shall provide ROT for measurement (RTM) to record the measurement data at 
runtime.  
5. The DSM  shall provide ROT for reporting (RTR) to report the measurement data.  
6. The d evice should provision the device  certificate at manufacture  time.  A DICE device shall 
generate alias certificate at boot time.  
7. The Device vendor should publish the reference integrity manifest (RIM)  for attestation.  The 
RIM may  follow IETF CoRIM specification.  
Device Firmware Resilience  
Usually, the device supports fi rmware update. The DSM shall implement ROT for resilience.  
1. The DSM  shall provide ROT for update (RTU) for secure firmware update, including update 
image integrity protection and rollback protection , according to [NIST SP 800 -193].  
2. The DSM  shall provide ROT for detection (RTD) for secure boot, including boot image 
integrity verification and secure version number (SVN) verification , according to [NIST SP 800 -
193].  
3. The DSM  should provide ROT for recovery (RTRec) to recover the de vice firmware in case of 
verification failure , according to [NIST SP 800 -193].  
Runtime Firmware Update  
Optionally, the device may support runtime update without reset.  The capability is controlled 
by following field s: 
• SPDM 1.2 SessionPolicy.TerminationPoli cy: Determine if runtime update will keep 
session alive.  
• TDISP LOCK_INTERFACE_REQUEST.NO_FW_UPDATE : Determine if update is allowed 
in TDISP CONFIG_LOCKED state.  
See table 4 -1. 4     Device Security Architecture    
 
41        Document Number:  354272 -001    
Table 4 -1: Runtime Firmware Update Summary  
SPDM:  
TerminationPolicy  TDISP:  
NO_FW_UPDATE  Result  
0 (No Runtime 
Update)  0 (Allow firmware 
update  if TDISP is in 
CONFIG_LOCKED 
state ) No Runtime Update.  
 
The update will cause SPDM session 
termination.  After update, the device will 
expect next SPDM message to be 
GET_VERSION, and will return 
ERROR( RequestResynch ) for all other.  
Update)  1 (No t allow  
firmware update  if 
TDISP is in 
 
Any update is not allowed  if TDISP is in 
CONFIG_LOCKED state.  The update is 
allowed if TDISP is not in CONFIG_LOCKED  
state  and the update will cause SPDM session 
termination.  
1 (May support 
Runtime Update ) 0 (Allow firmware 
state ) The de vice may choose to a llow Runtime 
Update  regardless of the TDISP state . 
 
The update may keep session alive or 
terminate . It is the device’s choice based on 
the impact of the update.  
Runtime Update ) 1 (No allow 
firmware u pdate  if 
TDISP is in 
state ) The device may choose to allow Runtime 
Update if TDISP is not in CONFIG_LOCKED 
state . 
 
CONFIG_LOCKED state.  
 
1. The device shall support SPDM 1.2  SessionPolicy.TerminationPolicy = 1 , to keep the SPDM 
session alive during runtime update.  
2. The device shall keep IDE stream alive during the runtime update.  
3. The device shall support TDISP LOCK_INTERFACE_REQUEST.NO_FW_UPDATE = 0 , to keep 
TDISP alive d uring the runtime update.  
4. The device shall support SPDM_DIGESTS and SPDM_CERTIFICATE command in Session . 
5. The device sh ould  support SPDM 1.2 MEAS_FRESH_CAP to report the fresh measurement 
after the runtime update.  4     Device Security Architecture    
 
42        Document Number:  354272 -001    
6. The device should support SPDM 1.2 , MEASUREMENTS.Param2.content_change detection  
to report the atomicity of the measurement reporting.  
7. The device should support SPDM 1.2, DMTFSpecMeasurementValueType  Mutable Firmware 
Security Version Number (SVN).  
8. The DICE device shall report the cer tificate including the new firmware information in 
DiceTcbInfo, such as firmware digest and/or SVN.  
Secure Interconnects  
The device shall support IDE based secure communication with the TSM.  
1. The d evices must support selective IDE . [PCIe TDISP 1.0]  11.4.3 Secure Interconnects , page 
50. 
2. The device must implement adequate security measures to prevent leakage of the 
encryption key at rest and in use , according to [PCIe TDISP 1.0]  11.4.3 Secure Interconnects , 
page 50. 
Device Attached Memory  
A device may implement device attached memory, which is used to host the TVM data.  
1. If device attached memory is supported, the device shall ensure the confidentiality  and 
optionally integrity of the TVM data stored in the device atta ched memory , according to [PCIe 
TDISP 1.0]  11.4.4 Device Attached Memory , page 50. 
TDI Security  
The device shall support TDISP protocol to manage TDI state.  
1. The device shall follow TDI Security requirement, according to [PCIe TDISP 1.0]  11.4.5 TDI 
Security , page 51. The device shall support TDI state (CONFIG_UNLOCK, CONFIG_LOCK, RUN, 
ERROR) and IDE Stream state (Insecure, Secure)  transition. Any configuration change that 
impacts the TDI security properties shall result in the TDI ERROR state  and IDE Stream 
Insecure state.  
Data Integrity Errors  
A device may receive a poisoned TLP on an interface in RUN.  4     Device Security Architecture    
 
43        Document Number:  354272 -001    
1. The device shall handle data integrity error according to [PCIe TDISP 1.0]  11.4.6 Data 
Integrity Error , page 52. The device shall change the interface from RUN to ERROR  if a 
poisoned TLP is received,  to prevent bad data consumption and propagation. The d evice shall  
scrub and clear information in such logs and reporting registers (e.g., syndrome) that may 
reveal c onfidential data.  
Debug Modes  
A device may support multiple debug modes or debug capabilities.  
1. The device shall handle the debug mode , according to [PCIe TDISP 1.0]  11.4.7 Debug  
Modes , page 52. Debug capabilities must not affect the security of the device, and must not 
lead to a compromise of the confidentiality or integrity of the TVM data provided to the 
device.  
Device Debug Interface  
A device may provide debug interface to access low level dat a. 
1. The device shall implement the debug interface without impacting the security properties.  
2. The device should report the debug state to the host if the debug mode is enabled or a 
debugger is attached. The mechanism may be in SPDM measur ement DeviceModeCapabilties 
or DiceTcbInfo flags.  
 
Device Reset  
Conventional Reset  
A conventional reset (cold, warm, or hot) leads to the device changing all its port registers and 
state machines to their initialization values, and the TDISP state of all TDIs transitions to 
CONFIG_UNLOCKED.   
1. The device shall handle the conventional reset , according to [PCIe TDISP 1.0]  11.4.8 
Conventional Reset , page 53. The device shall ensure that all TVM data, IDE keys, other 
encryption keys (e.g., P2P links, intra -device interconnects, etc.) and SPDM session keys are 4     Device Security Architecture    
 
44        Document Number:  354272 -001    
cleared  and not exposed in conventional reset. The device shall reset t he device measurement 
registers  to their default values  in conventional reset.  
2. The device shall handle the conventional reset, according to [PCIe IDE 1.0] 6.99.8 Other IDE 
Rules . Any Conventional Reset to an Upstream Port or to the Bridge Function of a Downstream 
Port  must result in all IDE  Streams associated with that Function transitioning to the Insecure 
state, and all keys must be  invalidated and rendered unreadable.  
Function Level Reset (FLR)  
A device may support function level reset.  
1. The device shall handle the Function Level Reset (FLR), according to [PCIe TDISP 1.0]  11.4.9 
Function Level Reset , page 53. The device shall ensure that all affected TDI  from 
CONFIG_LOCKED, RUN state to ERROR state  in function level reset. As such, the host need s to 
issue STOP_INTERFACE_REQUEST request to clean up the TDI state and scrub TVM 
data/secrets.

data/secrets.  
2. The device shall handle the Function Level Reset (FLR), according to [PCIe IDE 1.0] 6.99.8 
Other IDE Rules . Any FLR to a Function containing an IDE Extended Capability  must result in all 
IDE Streams associated with that Function transitioning to the Insecure state, and all keys 
must be  invalidated and rendered unreadable. An FLR to a Function that does not contain an 
IDE Extended Capability must not a ffect IDE operation . 
Table 4 -2 shows examples of the impact of different reset, assuming that  Physical Function 
FLR (PF -FLR) happens on a function that contains an IDE Extended Capability and Virtual 
Function FLR (VF -FLR) happens on a function that does not contains an IDE Extended 
Capability.  
Table 4 -2: Examples of the Impact of Reset  
Reset Type  VF specific 
TDI Other subordinate  
VF TDIs  IDE Stream  SPDM Session  
Conventional Reset  ERROR  ERROR  Insecure  Termination  
PF-FLR (with IDE ECAP)  ERROR  ERROR  Insecure  No impact  
VF-FLR (no IDE ECAP)  ERROR  No impact  No impact  No impact  
 
Timing  
A device shall  follow t he timing requirement defined in the standards.  See table 4 -3. 
Table 4 -3: Timing requirement summary  
Protocol  Description  4     Device Security Architecture    
 
45        Document Number:  354272 -001    
PCI DOE  The device shall return DOE response within 1 second , according to [PCIe 
DOE 1.0]  6.xx.1 Operation.  
SPDM  The device shall follow “Timing specification table ” and the CTExponent 
shall be return via SPDM CAPABILIT IES. 
IDE 1. The device port shall be able to process IDE TLP within 10ms  after 
receiving the IDE_KM K_SET_GO  (enable or refr esh) , according to [PCIe IDE 
1.0].  
2. The device port shall invalidate and render unreadable the key set within 
10ms  after receiving the IDE_KM K_SET_STOP, according to [PCIe IDE 1.0] .  
3. When aggregating TLPs, the Transmitter must treat a TLP as the las t TLP of 
an aggregated unit unless the Transmitter can guarantee that it will transmit 
another TLP within the aggregated unit  within 1µs. 
TDISP  The device shall inherit timing requirements from the SPDM.  
TLP The device shall follow [PCIe 6.0]  2.8 Completion Timeout Mechanism  
 
Error Handling  
A device shall follow the error handling requirement defined in the standards.  
Error Trigger  
Table 4 -4 shows the possible source that triggers the error.  
Table 4 -4: Error Trigger  
Source  IDE Insecure  TDISP ERROR  
DOE Mailbox  If DOE mailbox error causes 
unrecoverable error and SPDM 
session termination , then IDE state 
shall be changed to insecure.   If DOE mailbox error causes 
session termination , then TDI state 
shall be changed to  ERROR.  
SPDM Session  SPDM session termination  shall 
cause the IDE state to insecure. 
[PCIe TDISP 1.0]  11.4.5.  TDI 
Security . 
 
If the secure SPDM session that was  
used for initial key programming is 
closed, any  subsequent QUERY 
and/or  KEY_PROG requests 
received through a different 
secure  SPDM session  must  first 
cause the responder to invalidate 
and render unreadable all keys  
must for the IDE Stream, then 
transition that IDE Stream to the SPDM session termination  shall 
cause the TDI state to ERROR. [PCIe 
TDISP 1.0]  11.4.5.  TDI Security . 4     Device Security Architecture    
 
46        Document Number:  354272 -001    
Insecure state.  [PCIe IDE 1.0] 6.99.3. 
IDE KM . Page 24.  
TLP / 
Configuration  1. Any conventional reset  or any 
FLR to a function containing an 
IDE extended capability  must 
result in IDE stream to insecure 
state. [PCIe IDE 1.0]  6.99.8 Other 
IDE Rules.  
NOTE: An FLR to a Function that 
does not contain an IDE Extended 
Capability  must not affect IDE 
operation.  
 
2. Use of Selective IDE under any 
use case where ACS services  (or any 
other mechanism) blocks  or 
otherwise terminates IDE TLPs  will 
result in the associated Selective 
IDE Stream going to  Insecure.  [PCIe 
IDE 1.0]  6.99.8 Other IDE Rules.  
 
3. Using the following  practices . 
[PCIe IDE 1.0]  6.99 Integrity & Data 
Encryption (IDE)  implementation 
note.  
3.1. Detecting inappropriate 
attempts to reconfigure IDE , 
and/or other internal conditions 
that could compromise secure data 
forcing the Port into Insecure . 
3.2. A ny change in debug 
configuration  that could expose 
data intended to be secured result 
in a transition to Insecure . 1. Following conditions must be 
treated as errors , according to  [PCIe 
TDISP 1.0]  11.2 TDISP Rules page 
19. 
1.1. Changes to TDI configuration 
that affect the configuration or the 
security  of the TDI.  [PCIe TDISP 
1.0] 11.2.6.  DSM Tracking and 
Handling of Locked TDI , 11.4.5.  
TDI Security . Refer to Table 2: 
Example DSM Tracking and 
Handling for Architected Registers.  
1.2. Changes to the Requester ID  
1.3. Resetting the TDI using a 
1.4. Any IDE stream bound to the 
TDI transitions to the Insecure 
state . [PCIe TDISP 1.0]  11.4.5.  TDI 
Security . 
1.5. Receipt of a poisoned TLP  
([PCIE Base] 6.2.3.3 Error 
Forwarding ) or detecting data 
integrity errors in the device for 
data associated with that TDI, 
where the error is not recoverable.  
1.6. Other device specific 
conditions or changes in 
configuration that affect trust  
properties.  
 
2. Receipt of a Completion with 
UR/CA  or Completion timeout  
(following recovery retries) for 
request initiated by a TDI in 
CONFIG_LOCK, RUN  (with T=1) 
indicates occurrence of an 
uncorrectable  error . [PCIe TDISP 
1.0] 11.4.3. Securing Interconnects.  
 
3. ATS Error [PCIe TDISP 1.0]  
11.4.10  4     Device Security Architecture    
 
47        Document Number:  354272 -001    
3.1. Translation Completion (s) 
received with the T bit Clear , if the 
request with T bit set.  
3.2. PRG Response  received with 
the T bit clear , if the request with T 
bit set.  
 
Table 4 -5 shows the IDE TLP Error . “IDE Check Failed ” is a fatal error and will cause  the IDE 
state to be Insecure. “Misrouted IDE TL P” and “PCRC Check Failed ” are non -fatal error and will 
not cause  an IDE state change.  
Table 4 -5: IDE TLP Error  
IDE Error  Error Condition  
IDE Check 
Failed  1. Selective IDE Stream rules which cause an IDE Check Failed error . [PCIe 
IDE 1.0]  6.99.4 IDE TLPs  
1.1. Receipt of an IDE TLP associated with a Selective IDE Stream that is 
not a permitted TLP Type . 
2. Aggregation TLP  rules that  cause an IDE Check Failed err or. [PCIe IDE 
1.0] 6.99. 6 IDE TLP  Aggregation  
2.1. If the K bit is to be toggled, it must only be toggled for the first TLP of 
an aggregated unit . 
2.2. If an IDE TLP with the M bit Clear  is received at a Receiver  where 
Aggregation is not supported , or if n ine or more  successive TLPs are 
received in the Sub -Stream with the M bit Clear . 
3. Other rules that  cause an IDE Check Failed. [PCIe IDE 1.0]  6.99.8 Other 
IDE Rules.  
3.1.  Received Completion shall use same Stream ID and Same T bit  with 
NPR.  
3.2. Use of m echanisms that result in the blocking or termination of TLPs 
must be carefully coordinated with the use of Selective IDE Streams. 
Dropping of Selective IDE TLPs . 
3.3. Detection following condition:  
3.3.1 MAC check failure  
3.3.2 underflow  of PR -received -counter-NPR/C PL 
3.3.3 overflow  of PR -received-counter-NPR/CP L 
3.3.4.  unsupported field  in sub -stream identifier . [PCIE Base] 6.33.8 Other 
IDE Rules . 
Misrouted IDE 
TLP 1. Flow -Through selective ID stream rules which cause Misrouted IDE TLP. 
[PCIe TDISP 1.0]  6.99.7 Flow -Through Selective IDE Streams  
1.1 If an IDE TLP is routed to an Egress Port with the Flow -Through IDE 
Stream Enabled bit Clear . 
2. Other IDE rules that  cause Misrouted IDE TLP. [PCIe TDISP 1.0]  6.99.8 
Other IDE Rules  4     Device Security Architecture    
 
48        Document Number:  354272 -001    
2.1. Receipt of a Link IDE TLP or Selective IDE TLP for which there is not an 
associated IDE Stream  
2.2. Receipt of a Link IDE TLP by a Switch that targets an Egress Port for 
which there is not  a Link IDE Stream associated with the same TC and in 
the Secure state  
PCRC Check 
Failed  1. IDE TLP  rules that  cause PCRC Check Failed. [PCIe TDISP 1.0]  6.99.4 IDE 
TLPs  
1.1. When PCRC is enabled for an IDE Stream, the PCRC is not present.  
1.2. The PCRC mu st only be checked by the ultimate Receiver of the IDE 
TLP including PCRC.  A failure of the PCRC check indicates that one or more 
bits of the data payload have been corrupted.  
 
Error  Notification  
Table 4 -5 shows the  error notification  via software protocol.  
Table 4 -6: Error Notification via Protocol  
Source  Protocol  Error  
DOE Message  N/A 
SPDM  SPDM response may return error via SPDM_ERROR . 
IDE_KM  IDE_KM re sponse  may return error via Status Field  in IDE_KM KP_ACK, 
according to [PCIe IDE 1.0]  6.99.3  IDE Key Management (IDE_KM) . 
Attempting to configure IDE keys into a sub -stream using different SPDM

PCRC Check 
TLPs  
 
Attempting to configure IDE keys into a sub -stream using different SPDM 
sessions is an error and must be rejected . [PCIe TDISP 1.0]  11.4.5.  TDI 
Security . 
TDISP  TDISP  response may return error via TDISP_ERROR , according to [PCIe 
TDISP 1.0]  11.3.8. LOCK_INTERFACE_REQUEST, 11.3.10. 
GET_DEVICE_INTERFACE_REPORT , 11.3.12. 
GET_DEVICE_INTERFACE_STATE , 11.3.14. START_INTERFACE_REQUEST, 
11.3.16. STOP_INTERFACE_REQUEST, 11.3.18. 
BIND_P2P_STREAM_REQUEST , 11.3.20. UNBIND_P2P_STREAM_REQUEST, 
11.3.22. SET_MMIO_ATTRIBUTE_REQUEST . 
TLP TLP may return Unsupported Request (UR) or Unexpected Completion (UC), 
according to [PCIE Base] 6.33.8 Other IDE Rules . 
The Translation Complete Status field  is defined in [PCIE Base] Table 10 -2 
Translation Completion with No Data Status Codes . 
The transaction layer Error is listed at [PCIE Base] Table 6 -5 Transaction 
Layer Error List . 
Table 4 -7 shows the error notification via error regi ster. 
Table 4 -7: Error Notification via Register  
Source  Register  
DOE Error  DOE Error  (bit 2)  is in [PCIe DOE 1.0]  7.9.24.4 DOE Status Register . 4     Device Security Architecture    
 
49        Document Number:  354272 -001    
IDE Error  Link IDE Integrity Check Fail  (bit 31) is in [PCIe IDE 1.0]  7.9.99.4.2 Link IDE 
Stream Status Register . 
Selective IDE Integrity Check Fail  (bit 31)  is in [PCIe IDE 1.0]  7.9.99. 5.3 
Selective IDE Stream Status Register . 
The Integrity Check Fail  is equal to IDE Check Failed . Misrouted IDE TLP  or 
PCRC Check Failed  error shall not cause Integrity Check Fail error bit set . 
Advanced 
Error  
(optional)  Unrecoverable Error Status Register is defined in [PCIe IDE 1.0]  7.8.4 
Advanced Error Reporting Extended Capability , including IDE Check Failed  (bit 
28), Misrouted IDE TLP  (bit 29), PCRC Check Failed  (bit 30).  
 
NOTE : There is no proactive TDISP error  notification  via either a hardware or software 
mechanism. The reason is that there is no way to guarantee that such proactive notification  
will be delivered to a TVM  when the error happens , such as an MS I-X interrupt or TDISP error 
event message . Even if a device chooses to implement such  a notification mechanism, it is not 
secured  because the man -in-the-middle adversary may block or delay the error  notification . 
Before the TVM receives such notification, it may already consume the invalid  data . As such, 
when error happens, the only requirement from the device side is to stop workin g 
immediately.  
When TVM  performs MMIO_READ action , it will usually get All-1 (such as 0xFF  for 8bit reg, 
0xFFFF for 16bit reg, or 0xFFFFFFFF for 32-bit reg) if the device is in ERROR state. The best 
practice is for the device to design the MMIO register in  a way that All-1 can be  considered an 
error.  As such, when TVM gets  All-1, it knows that device is in the ERROR state . Also, the TVM 
may use GET_DEVICE_INTERFACE_STATE to poll the TDI state to confirm whenever it 
suspects TDI being in ERROR  state . 4     Device Security Architecture    
 
50        Document Number:  354272 -001    
Error Recovery  
Table 4 -8 shows the possible error recovery mechanism.  
Table 4 -8: Error Recovery  
Source  Recovery  
DOE  If DOE Error  (bit 2) in DOE Status Register  is set, the device shall wait for 
host software to  set DOE Abort (bit 0) in DOE Control Register  to clear the 
Error.  
SPDM  If there is SPDM session error or heartbeat timeout, the device shall 
terminate the session and wait for new KEY_EXCHANGE  message  to set up  
a new SPDM session, or terminate the SPDM connection and wait for 
GET_VERSION  message  to set up  a new SPDM connection . 
IDE 1. Once IDE Check Failed  error  is detected, t he TLP that triggered the error 
and all subsequent IDE TLPs received associated  with the same IDE Stream 
must be discarded , according to [PCIe IDE 1.0]  6.99.8  Other IDE Rules, page 
45. 
1.1. For Link IDE  (TC0 /VC0) , it will be impossible  to communicate with the 
device until the device is reset , e.g.  using a Secondary Bus Reset (a PCIe Hot 
Reset) , because the device must reject all subsequent coming TLP s. 
1.2. For Selective IDE , if Configuration Requests are not being associated 
with the Stream, then i t is possible to recover the device by tearing dow n 
the affected TDIs, disabling and then re -enabling the Selective IDE 
Stream, and then restarting the TDIs . 
2. Misrouted IDE TLP  is not a fatal error. The device shall permit continued 
operation.  [PCIe IDE 1.0]  Table 605.  
3. PCRC Check Failed  is not a fata l error. The device shall permit continued 
TDISP  1. For TDI ERROR, the host can send STOP_INTERFACE_REQUEST  to 
change the TDI to CONFIG_UNLOCKED.  
2. A TDI is permitted to transport TLP message s in ERROR  state  if and only 
if T bit is set , e.g. ATS invalidate.  [PCIe TDISP 1.0]  11.2.1 TLP Rules,  page 
21. 
3. A TDI is permitted so that clearing this data  be deferred  until the 
receipt of a STOP_INTERFACE_REQUEST to transition  the TDI to 
CONFIG_UNLOCKED . [PCIe TDISP 1.0] 11.2.1 TLP Rules,  page 19.  
4. It is permitted that the TDI transition automatically from ERROR to 
CONFIG_UNLOCKED , if and only if the TDI first clears all TVM confidential 
data.  [PCIe TDISP 1.0]  11.2.1 TLP Rules,  page 19.  
 
NOTE: Once TDI is in ERROR state, the TDI shall clear all security related context. Care must be 
taken that the Tag in NPR without CPL shall not in the context. The TDI shall keep tracking the 
CPL Tag and ensure the same Tag is never reused when the TDI is out of ERROR state to avoid 
Tag reuse attack. Alternatively, the TDI may disallow change from ERROR to other state before 4     Device Security Architecture    
 
51        Document Number:  354272 -001    
the TDI receives a corresponding CPL TLP or CPL timeout. Or the TDI can d o reset such as 
Function Level Reset (FLR) or convention reset.  5     Summary    
 
52        Document Number:  354272 -001    
5     Summary  
This white paper  describes how to build a  device to support confidential computing . First, we 
provide summary of the secure device interface lifecycle. Then we provide detailed 
information on  the software communication (DOE, SPDM, IDE_KM, TDISP) and the hardware 
communication (link encryption ), as well as the device security implementation.  
  Appendix  A: Intel® TDX Connect Interoperability  
  
53        Document Number:  354272 -001    
Appendix A: Intel ® TDX  Connect  Interoperability  
This section describes the feature s suppo rted in Intel ® TDX  Connect  host architecture and 
restrictions that are introduced to the generic device architecture described in the main 
portion of this document.  
Table A -1 shows the generic terminology mapping for Intel ® TDX  Connect . 
Table A -1: Terminology Mapping for Intel TDX  
Term  Intel ® TDX Connect  
TEE Security Manager (TSM)  Intel ® TDX Module  
Intel ® TDX Connect TEE-IO provisioning agent ( TPA ) 
TEE Virtual Machine (TVM)  Tenant Trust Domain (TD)  
 
In following sections,  we will use term “Intel TSM”  to indicate the T SM in Intel TDX Connect , 
including Intel ® TDX Module and Intel ® TDX Connect TEE -IO provisioning agent  (TPA ). 
TDX Connect  Software Interoperability  
This section describes the software stack requirements for device interoperability with the 
TDX Connect host.  
DOE  
The DOE functionality required to be supported by the TDX  Connect  device is:  
• DOE Discovery  
• CMA/SPDM  
• Secure CMA/SPDM  
The following DOE functionality is not supported by the TDX host , and the device shall not use 
them for any TDX  Connect  usages.  
• CMA/SPDM with Connection ID  
• Secure CMA/SPDM with Connection ID  
• Async Message  
Configurations  
Depending on the device’s architecture and functionality , a device shall implement one or 
more DOE mailboxes . The mailboxes may be  in the following configurations : 
• 1 device -> N function s -> 1 DOE (in function 0 only)  
• 1 device -> N function s -> N DOE s  
• 1 device -> N function s -> N*M DOE s (each function has M DOE s) Appendix  A: Intel® TDX Connect Interoperability  
  
54        Document Number:  354272 -001    
The TDX host does not place any restrictions on the number of DOE mailboxes and how they 
are associated with the functions  other tha n overall platform capacity.  
SPDM  
TDX  Conn ect host supports SPDM version 1.2.  
The device shall support SPDM version 1.2 or h igher.  If the device supports a higher version 
than 1.2,  it shall be able to fall back to using version 1.2 for TDX  Connect  usages through  the 
SPDM Get Capabilities mechanics.  
The device shall  support the SPDM request and response messages in table A -2. “Optional ” 
means the TDX Connect host may send the message if the device supports the capability.  “In 
session ” means the TDX Connect host needs to send the message in SPDM session.  “In/out of 
session ” means the TDX Connect host needs to send the message in SPDM session and out of 
SPDM session.  
Table A -2: Supported SPDM  Messages  
Request Messages  Response Messages

SPDM  
Request Messages  Response Messages  
GET_VERSION  VERSION  
GET_CAPABILITIES  CAPABILITIES  
NEGOTIATE_ALGORITHMS  ALGORITHMES  
GET_DIGESTS  (in/out of session)  DIGESTS  (in/out of session)  
GET_CERTIFICATE  (in/out of session)  CERTIFICATE  (in/out of session)  
GET_MEASUREMENTS  (in session)  MEASUREMENTS  (in session)  
KEY_EXCHANGE  KEY_EXCHANGE_RSP  
FINISH  FINISH_RSP  
HEARTBEAT  (optional)  HEARTBEAT_ACK (optional)  
KEY_UPDATE  (optional)  KEY_UPDATE_ACK (optional)  
END_SESSION  END_SESSION_ACK  
- ERROR  
 
DOE mappings  
SPDM may be mapped to the device/function and DOEs in the following ways.  
• 1 device -> N function s -> 1 DOE (in function 0 only) -> 1 SPDM.  
• 1 device -> N function s -> N DOE s -> N SPDM s 
• 1 device -> N function s -> N DOE s -> 1 SPDM (other N -1 DOE is used for other 
purpose)  
• 1 device -> N function s -> N*M DOE s (each function has M DOE) -> N SPDM s 
VMM will discover and select  the proper DOE mailbox  one that  supports IDE_KM and TDISP . 
Then the VMM will ask TPA to  setup the SPDM session . Appendix  A: Intel® TDX Connect Interoperability  
  
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Cryptographic algorithms  
The TDX  Connect  host supports the SPDM cryptographic algorithms defined in CMA ECN . 
The device may implement any subset of the algorithms governed by those specifications.  
Mutual Authentication  
The TDX  Connect  host does not support mutual authentication.  The host will not set 
MUT_AUTH_CAP. The DSM shall not request mutual authentication.  
The device may optionally implement a non -standardized mutual auth entication -attestation 
method  as mentioned in chapter 2 , such as RATLS.  
Certificate  
Intel TSM is the host component that will receive the certificate chain from the device, verify 
the signature by using the public key associated with the leaf certificate o f the Responder, and 
all intermediate public keys within the certificate chain using the root certificate as the trusted 
anchor. It will use the public key associated with the leaf certificate to setup the SPDM session.  
Intel TSM provides a secure mechanis m to  pass the entire certificate chain in all slots to the 
TVM , so that the T VM can verify its contents and make decision to accept the device using the 
TVM’s own policy.  
Measurement  
Intel TSM will receive the device measurement s from the device in the SPDM session.  
Intel TSM provides a secure mechanism to pass all measurement s received from the device  to 
the TVM,  so that the TVM can verify the device measurements  based TVM’ s policy.  
SPDM Connection  and Session  
The d evice may suppo rt multiple SPDM connection s and multiple SPDM sessions in one 
SPDM connection.  
• 1 DOE mailbox -> 1 Connection -> 1 Session  
• 1 DOE  mailbox  -> X Connection s -> X Session s 
• 1 DOE  mailbox  -> X Connection s -> X*Y Session s 
Intel TSM  will only choose 1 SPDM Connection and setup 1 SPDM session.  
IDE_KM  
The TDX Connect device shall support  the IDE_KM defined  in [PCIe IDE 1.0]. 
The device shall  support the IDE_KM request and response messages in table A -3. 
Table A -3: Supported IDE_KM  Messages  
QUERY  QUERY_RESP  Appendix  A: Intel® TDX Connect Interoperability  
  
56        Document Number:  354272 -001    
KEY_PROG  KP_ACK  
K_SET_GO  K_GOSTOP_ACK  
K_SET_STOP  K_GOSTOP_ACK  
 
Selective IDE Stream Sequence  
The TDX Connect host supports the following IDE  key management sequence.  
• Initial IDE Stream setup. The TDX Connect host SOC only supports the  sequence to set 
IDE Stream Enable bit for SOC after  the IDE key and the IDE key set are programmed 
into S OC Root Port  and the device . 
• IDE Stream Stop.  The TDX Connect host SOC only support the sequence to disable IDE 
stream Enable bit for device and then for SOC , before send IDE_KM message to the 
device.  
• IDE Stream Key refresh.  
Please refer to Appendix B , IDE  Stream section, for an example on how to program keys into 
device and start IDE stream.  
 
TDISP  
The TDX Connect device shall support [PCIe TDISP 1.0] .  That is the only TDISP version 
supported by the TDX Connect host.  
 
The device shall  support the TDISP re quest and response messages  in table A -4. 
Table A -4: Supported TDISP Messages  
GET_TDISP_VERSION  TDISP_VERSION  
GET_TDISP_CAPABILITIES  TDISP_CAPABILITIES  
LOCK_INTERFACE_REQUEST  LOCK_INTERFACE_RESPONSE  
GET_DEVICE_INTERFACE_REPORT  INTERFACE_REPORT  
GET_DEVICE_INTERFACE_STATE  GET_DEVICE_INTERFACE_STATE  
START_INTERFACE_REQUEST  START_INTERFACE_RESPONSE  
STOP_INTERFACE_REQUEST  STOP_INTERFACE_RESPONSE  
- TDISP_ERROR  
 
Intel TSM only support above TDISP mandatory messages  in Table A -4. 
Device Address Width  
The TDX  Connect  compliant device ’s address width must be at least 52 bits.  Appendix  A: Intel® TDX Connect Interoperability  
  
57        Document Number:  354272 -001    
The device reports the address width thru the TDISP GET_TDISP_CAPABILITIES exchange.  
Intel  TSM will  reject devices that do not support at least 52 bits . 
TDI Report Structure  
Once the device returns TDI Report structure to the host.  The host software should check the 
TDI report to decide if the device configuration is acceptable.  
Intel TSM will perform  basic TSM capability check  for the TD Report Structure.  See Table A -5. 
Table A -5: Intel TSM Capability Check  for TDI Report  
TDI Repor t Structure Field  Intel TSM Capability  
INTERFACE_INFO:BIT0  
(Firmware update no t allowed in CONFIG_LOCK ED or RUN ) Ignored  
INTERFACE_INFO:BIT1  
(TDI generates DMA requests without PASID ) Must be 1 
INTERFACE_INFO:BIT 2 
(TDI generates DMA requests with PASID ) Must be 0 
INTERFACE_INFO:BIT3  
(ATS supported and enabled for the TDI ) Must be 0 
INTERFACE_INFO:BIT4  
(PRS supported and enabled for the TDI ) Must be 0 
MSI_X_MESSAGE_ CONTROL  Must be 0 
LNR_CONTROL  Must be 0 
TPH_CONTROL  Must be 0 
MMIO_RANGE_COUNT  Ignored  
MMIO_RANGE  Ignored  
DEVICE_SPECIFIC_INFO_LEN  Ignored  
DEVICE_SPECIFIC_INFO  Ignored  
 
The TVM should perform policy check . For example, if firmware update is allowed in 
CONFIG_LOCKED or RUN state.  
The TDX Connect compliant device shall follow the TSM capability to return  the TDI report 
TDX Connect  Hard ware Interoperability  
This section describes the hardware  stack requirements for device interoperability with the 
IDE Stream  
TDX  Connect  compliant host SOC only supports PCI Express IDE and not CXL IDE.  Appendix  A: Intel® TDX Connect Interoperability  
  
58        Document Number:  354272 -001    
The TDX  Connect  compliant device shall follow the PCI Express  device requirements for IDE.  
Selective IDE Stream Support  
The TDX  Connect  host SOC only supports selective IDE streams. The SOC  does not support 
Selective IDE for Configuration Requests Enable.  
The TDX  Connect device shall only use selective IDE streams to communicate with TDX  
Connect  host  with out Configuration Requests Enable .  
Number of Selective IDE Streams  Supported  
The TDX  Connect  host supports a  total of u p to 4 IDE stream s per Root -Complex . The 
actual  number  of IDE stream register blocks per R oot Port (RP) depends on per RP 
bifurcation  as defined  in the following table . 
The device can support 1~4 Selective IDE streams depending on the interface as defined 
in the table  A-6. 
Table A -6: number of IDE stream register blocks per R oot Port 
Bifurcation  Selective  IDE Register Blocks  Link  IDE Register Blocks  
1x16  4 1 
2x8 3 1 
4x4 1 1 
8x2 N/A N/A 
16x1  N/A N/A 
The TDX Connect host only support s 1 IDE Address Association Register  block and 1 IDE RID 
Association Register  block per each selective IDE stream . 
TLP MAC  Aggregation  
The TDX  Connect  host SOC does not support TLP MAC aggregation. Intel TSM will always 
select the No Aggregation mode.  
The TDX  Connect  device shall not indicate IDE TLP aggregation capability in the IDE Extended 
capability register.  
IDE Support  for TEE -IO 
The TDX Connect host SOC  Root Port  IDE is TEE -IO capable . However, it  does not expose  the 
TEE-IO Supported Bit in IDE Device Capability register  in [PCIe TDISP  1.0]. 
Intel TSM requires the software to enumerate TEE -IO support and enable it using Intel TSM 
host VMM interface . 
The TDX  Connect  host SOC does not support TEE  Limited Stream.  Appendix  A: Intel® TDX Connect Interoperability  
  
59        Document Number:  354272 -001    
The TDX  Connect  device shall not indicate support for TEE Limited Stream capability in the 
IDE Extended capability register. Both TLPs with the T bit set and TLPs w ith the T bit not set 
are allowed to be associated with the selective ID stream.  
The TDX Connect host SOC does not support Partial Header Encryption.  
The TDX Connect device shall not enable Partial Header Encryption.  
 
TDISP

TDISP  
The TD X Connect device shall support [PCIe TDISP 1.0] .  That is the only TDISP version 
Access Control  in TDX Connect  
The Intel TSM does not have knowledge on the device ’s TDI state, because Intel TSM cannot 
guarantee how the DSM does the transition. A TDI may transit ion to the ERROR state directly if 
the DSM detects a security violation or function level reset (FLR). A TDI may transit to 
CONFIG_UNLOCKED in case of conventional reset. A TDI may automatically transit from 
ERROR to  CONFIG_UNLOCKED if the TDI clears all TVM confidential data, according to [PCIe 
TDISP 1.0]  page 19.  
MMIO Access Control  
Intel TSM does not have knowledge on which device MMIO region is TEE -MMIO or Non -TEE-
MMIO. The device will return TEE -MMIO information via INTERFACE_REPORT. Intel TSM does 
not parse the information but passes it to the TVM directly.  As such, we need define the MMIO 
resource in a different way  in TDX Connect host . 
MMIO Resource definition:  
• Private MMIO : The MMIO range whose GPA.S = 0  and HPA TDX HKID is the TD private 
HKID . In Intel TDX Connect  architecture , the private MMIO can only be high MMIO  
whose address is above 4GB  (MMIO -H) and no t PCI Express  configuration space  (CFG) . 
The low MMIO range whose address is below 4GB (MMIO -L) or CFG  cannot be private 
MMIO.  Private MMIO access is only allowed in TEE -TLP.  
• Shared  MMIO : All other MMIO which is not private MMIO , including PCI  Express  
configuration space.  Shared MMIO access is only a llowed in Non -TEE-TLP.  
Role and Responsibility:  
• VMM is the resource manager.  VMM should allocate MMIO region and assign them to 
the devices.  
• TVM is the policy maker.  TVM should parse the TEE -MMIO range from 
INTERFACE_REPORT and fully understand which MMIO is TEE -MMIO and which is Appendix  A: Intel® TDX Connect Interopera bility  
  
60        Document Number:  354272 -001    
Non -TEE-MMIO. The TVM shall accept the private GPA mapping from VMM according 
to the reported TEE -MMIO range.  
• Intel TSM is the policy enforcer.  Intel TSM provides API (TDG.MMIO.ACCEPT) for the 
TVM to let TVM accept the TEE -MMIO map ped by VMM as private GPA. Intel TSM will 
ensure that the Private GPA access uses TEE -TLP and shared GPA access uses Non -
TEE-TLP.  Intel TSM ensures the TEE -MMIO is mapped as private GPA before allowing 
the DSM to transit to RUN state.  Since only MMIO -H can be private memory, Intel TSM 
will reject the private MMIO map request for MMIO -L or CFG.  
 
The f ollowing table A-7 shows the MMIO Access Rules for TDX Connect host as Requester . 
For TEE -TLP, Intel TSM will ensure  that only TVM (as TDI owner) can gener ate such access.  
Table A -7: MMIO Rule for TDX Connect host  as Requester  
Operation  TEE-TLP (Private GPA access)  Non -TEE-TLP (Shared GPA access)  
TEE-MMIO  TEE-MMIO ( V) TEE-MMIO ( X) * 
Non -TEE-MMIO  Non -TEE-MMIO ( V) ** Non -TEE-MMIO ( V) 
* This is rejected  by DSM.  See Table 3 -4. 
** A TVM may choose to use TEE -TLP for Non -TEE-MMIO access. In this case, the TVM owner 
should be aware  that the private GPA usage with TEE-TLP cannot guarantee the data 
security  because DSM has no responsibility to protect  the data in Non -TEE-MMIO . The TVM 
owner shall still treat the  Non -TEE-MMIO  data from the device as untrusted  data  and shall not  
store  any confidential data to Non -TEE-MMIO  region , even if the Non -TEE-MMIO is map ped to 
private GPA.  
 
NOTE:  
1. The device shall  expose all TEE MMIO resources using 64-bit BARs . 
2. The device shall enforce that IDE Selective Stream bound to TDI and TDI TEE MMIO ranges 
are configured to MMIO -H. Note that this restriction does not apply to Non-TEE-MMIO.  
3. The device shall  treat any TEE-MMIO BAR re -programming as an error when the TDI is in 
CONFIG_LOCKED  state.  
 
Figure A-1 shows the trusted MMIO flow initiated from host TEE to the device.  Please  refer to 
[Intel TDX Connect] for more detail.  Appendix  A: Intel® TDX Connect Interoperability  
  
61        Document Number:  354272 -001    
 
Figure A-1: Trusted MMIO Flow  
 
DMA Access Control  
The memory resource in TDX Connect host  is defined as following:  
• Private Memory : The physical memory  range whose GPA.S = 0  with private HKID . It is 
TEE memory in TDX Connect host.  
• Shared Memory : All other memory  which is not private memory . It is Non -TEE memory 
in TDX Connect host.  
Note: The device does not know if the host memory is private memory or shared memory , 
according to [PCIe TDISP 1.0] . 
Appendix  A: Intel® TDX Connect Interoperability  
  
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• TVM is the policy maker.  TVM may choose to change the shared memory region. TVM 
shall clear the secret in the private memory before transiting it to shared memory. TVM 
shall accept the memory configur ation and IOMMU configuration from VMM.  
• Intel TSM is the policy enforcer.  Intel TSM provides API (TDG.DMAR.ACCEPT)  for the 
TVM to let TVM accept the Intel IOMMU (VT-d) configuration.  While a TDI is in RUN 
state, the TSM must pin the DMA page and ensure the DMA cannot be blocked by 
the VMM . Otherwise, the VMM may block the DMA  page  from being accessed by the 
TDI. The DSM or TDI cannot know that a DMA Write TPL is dropped , because DMA  
Write TPL is PR without CPL.  
 
The following table A-8 shows the DMA Rules for TDX Connect host as Completer . 
Table A -8: DMA Rule for TDX Connect host as Completer  
Access Control  TEE-TLP Non -TEE-TLP 
Private Memory  Private Memory ( V) Private Memory ( X) * 
Shared Memory  Shared Memory ( V) Shared Memory ( V) 
* It is rejected by the TDX Connect host SOC . TVM defines private memory range. Intel TSM 
enforces the configuration in TDX Connect host SOC  with Intel IOMMU.  
 
Note: Intel TDX Connect SOC supports “P2P via  Root Complex ”. In this case, Private Memory 
means  the TEE-MMIO on the target device.  Shared Memory means the Non -TEE-MMIO on the 
target device.  
 Appendix  A: Int el® TDX Connect Interoperability  
  
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Figure A-2 shows the trusted DMA flow initiated from the device to the host.  Please refer to 
[Intel TDX Connect] for more detail.  
 
Figure A-2: Trusted DMA Flow  
 
MSI-X 
The TDX  Connect  host does not support Trusted MSI.  
The device must not use MSI/X requests for TEE -IO transactions.  
The device must not set the MSI/X locking flag as part as device interface TDISP lock request.  
The device shall clear MSI_X_MESSAGE_CONTROL in TDI Report Structure.  
  
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ATS  
The TDX Connect host does not support ATS . 
The d evice must not use ATS requests for TEE -IO transactions. The device shall not gen erate 
Translation Request, Translated Request, or Page Requests on TDIs.  During TDI configuration  
the device could either disable ATS  for the specific TDI or it can be turned off globally for the 
entire device.  
The device shall indicate ATS is not suppor ted and enabled in the TDI Report Structure.  
PRS 
The TDX Connect host does not support PRS.  
The device must not use PRS requests for TEE -IO transactions. During TDI configuration it is 
recommended to disable PRS.  
The device shall indicate PRS is not supp orted and enabled in the TDI Report Structure.  
Peer to Peer (P2P)  
Direct P2P  
TDX  Connect  host SOC does not support Direct P2P, because ATS is not supported, and host 
SOC does not support setting P2P IDE Selective Streams required for Direct P2P.  
The TDX  Connect  device shall not generate any direct P2P messages.  
P2P via  Root Complex  
TDX  Connect  host SOC supports P2P via  Root Complex.  
The device may send and handle trusted TLPs only via the Root -Complex IOMMU in TDX  
Connect CPU host.  
PASID  
The TDX Connect host does not support PASID. The device must not be configured to enable 
PASID  on TDIs . 
The device and  its hosted TDIs must not gener ate or expect TLP with PASID for IDE TLP with T 
bit Set.  
The device shall indicate that PASID is  not supported and enabled in the TDI Report Structure.  
Shared Virtual Memory (SVM)  
The TDX Connect host does not support Shared Virtual Memory  (SVM) , also known as  Shared 
Virtual Addressing .  SVM requires PRS and PASID support. PRS and PASID are not useable 
with the TDX Connect host.  
The TDX Connect host’s Trusted IOMMU engine, Intel VT -d, does not support first stage 
translation  which is required for SVM.  Appendix  A: Intel® TDX Connect Interoperability  
  
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SVM should not be enabled for TDX Connect usages.  
LNR  
The TDX Connect host SOC does not support Lightweight Notification (LN) Protocol. LN has 
been deprecated from [PCIe 6.0]  
The device should not implement the deprecated Lightweight Notification (LN) prot ocol, I.e.,

bit Set.  
  
LNR  
The device should not implement the deprecated Lightweight Notification (LN) prot ocol, I.e., 
issue LN Reads, LN Completions, and LN Writes or generate LN metadata.  
The device shall clear LNR_CONTROL in the TDI Report Structure to indicate it is not 
supported.  
TPH  
The TDX Connect host SOC does not support TPH. The TDX host does not support MSI -X 
table locking which is a requir ement for TPH support  in [PCIe TDISP 1.0] . 
The device shall set the “TPH Completer Supported” field in the “Device Capabilities 2 
register” to “ TPH and Extended TPH Completer not supported” .  The device shall clear 
TPH_CONTROL in the TDI Report Structure.  
  Appendix  B: Secure Device Interface Lifecycle Example  
  
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Appendix B: Secure Device Interface Lif ecycle 
Example  
This section provides more detail SPDM management, IDE stream management and TDI 
lifecycle management flow as example . 
SPDM Management  
SPDM Session Setup  
In order to use the device, VMM need invoke TSM to establish SPDM session with the devi ce. 
Table B-1: SPDM Session Setup Example  
Step  Action  Description  
1 VMM checks device 
capability.  VMM reads device PCI DOE capability and IDE capability.  
VMM uses DOE message  DISCOVERY  to get the DOE 
capability.  
2 VMM invokes TSM 
to establish SPDM 
connection .  TSM sends SPDM messages  including GET_VERSION, 
GET_CAPABILITIES, NEGOTIATE_ALGORITHMS , and  
processes the responses.  
3 VMM invokes TSM 
session .  TSM sends SPDM messages  including 
GET_CERTIFICATE (slot=0) , KEY_EXCHANGE, FINISH , and  
4 VMM invokes TSM 
to collect device 
certificates and 
measurements from 
device.  TSM sends SPDM messages  including 
GET_CERTIFICATE (slot=1~7) , GET_MEASURMEMENT  in 
SPDM session  and processes the responses.  
 
SPDM Session Termination  
If all TDIs in a device are stopped, the VMM can terminate the SPDM session with the device.  
Table B-2: SPDM Session Termination Example  
1 VMM may ask TSM 
to terminate the 
SPDM session.  VMM invokes TSM to send SPDM message  - END_SESSION  
and processes the responses.  
 Appendix  B: Secure Device Interface Lifecycle Example  
  
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SPDM Session Heartbeat  
The VMM should calculate the time for the SPDM session and invoke the TSM to send 
heartbeat before the session timeout.  
Table B-3: SPDM Session Heartbeat Example  
to maintain the 
SPDM session at 
runtime, with 
heartbeat.  TSM sends SPDM messages  such as HEARTBEAT to keep 
SPDM session alive.  
 
SPDM Session Key Update  
The VMM should invoke TSM to perform Key Update before the session sequence number 
overflows. The TSM shall detect the sequence number overflow and stop the session 
immediately if that happens in either direction.  
Table B-4: SPDM Session Key Update Example  
runtime, with key 
update.  TSM sends SPDM messages  such as KEY_UPDATE  to keep 
 
Device Information Recollection  
If the device supports runtime update, the TVM may want to recollect the device certificates 
and measurements information to know if the device is kept up to date.  
Table B-5: SPDM Device Information Recollection Example  
1 TVM may ask TSM 
to recollect the 
device certificates 
and measurements  TSM sends SPDM message  – GET_CERTIFICATE  and 
GET_MESUREMENT  again  in the SPDM session  and returns 
information to T VM. 
TVM can verify the certificates and measurements again 
according to the device attestation policy.  
  Appendix  B: Secure Device I nterface Lifecycle Example  
  
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IDE Stream Management  
IDE Stream Setup  
The host software may use following sequence in Table 1 -7 to start IDE stream with the 
device. For host SOC, we use Intel Root Complex as example [Intel RC IDE].  
If a step includes the actions for both the host SOC and the device, then the actions for the 
host SOC and the device can be in any order.  
Note: This is not the only sequence to start IDE stream. This is one po ssible sequence to 
support both link IDE stream and selective IDE stream.  
Table B-6: IDE Stream Setup Example  
Step  To host SOC  To device  Comment  
1 Detect the IDE capability.  Detect the IDE capability.  Stop if no capability.  
2 Ensure IDE is disabled.  Ensu re IDE is disabled.  This is to avoid confusion 
with IDE Stream Key 
Refresh.  
3  Enable device’s interrupt, 
if needed.  It is for DOE message.  
4  Establish SPDM session  It is for IDE_KM messages 
and TDISP messages later.  
5 Program IDE key to SOC 
key programming 
registers.  Send IDE_KM message  – 
KEY_PROG  and process 
the KP_ACK response . The KEY_PROG is for each 
IDE sub -stream in (PR, NPR, 
CPL) and direction in (Rx, 
Tx). 
Now the IDE stream is in ready sub -state.  
6 Program IDE key set for 
SOC in Rx and Tx.  Send IDE_KM message  – 
K_SET_GO and process 
the K_GOSTOP_ACK 
response  in Rx and Tx.  The K_SET_GO is for each 
Tx). 
7  Do necessary action to 
ensure the device will not 
initiate IDE TLPs before 
the host SOC is ready. *  For example:  Disable 
device’s capability to 
generate asynchronous TLP. 
E.g. BusMasterEnable  (BME) , 
InterruptEnable.  
8  Set IDE Stream E nable bit 
for the device  and check 
Status bit.  The port must return the 
configuration completion as 
a Non -IDE TLP, then trigger 
the start of IDE. [PCIe IDE 
1.0] 6.99.3 IDE Key 
Management (IDE_ KM) Pa ge 
24. Appendix  B: Secure Device Interface Lifecycle Example  
  
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Now the device port is ready to receive IDE TLP. The device port shall continue to accept 
Non -IDE TLPs until it receives an IDE TLP. [PCIe IDE 1.0] 6.99.4 IDE TLPs  Page 36. 
9 Set IDE Stream Enable 
bit for SOC    
Now both sides can use IDE -TLP to transmit and receive. The IDE stream is in Secure state.  
10  Re-enable device 
capability to initiate IDE 
TLPs, if it is disabled.  For example, BME, 
 
NOTE:  
1. In link IDE stream use case, step 8 must be prior to step 9. If we put step 9 before step 8, the 
host SOC would send an IDE -TLP for PCI CFG c ycle to the device to set IDE Stream Enable bit 
before the device is ready to receive an IDE -TLP. The consequence is that the device will reject 
this IDE -TLP, and there is no way to enable the link IDE stream. This is not applicable to 
selective IDE if the  Selective IDE for Configuration Requests Enable bit is cleared.  
2. Step 7 is introduced according to [PCIe IDE 1.0] 6.99.3 IDE Key Management (IDE_KM) Page 
24. “ System software must ensure that the Partner Ports initiate IDE TLPs sequenced 
appropriately s o that a Port will not receive an IDE TLP before the Enable bit has been set. ” 
Otherwise, the device might send an IDE -TLP for the interrupt to the host SOC before the host 
SOC is ready to receive an IDE -TLP. The consequence is that the host SOC will rejec t this IDE -
TLP and lose the interrupt.  
Software shall not enable device Tx direction (in step 6) after step 9, because the device shall 
return the IDE -TLP Completion for the IDE -TLP Non -Posted Request from the host. Otherwise, 
it will cause IDE Check Failed error. [PCIe IDE 1.0] 6.99.8 Other IDE Rules Page 46.  
3. After step 8, the device may still receive Non -IDE TLP until the first IDE TLP. However, if the 
IDE TLP is Non -Posted Request, then the Completion shall use the same Stream ID and same 
T bit v alue. [PCIe IDE 1.0] 6.99.8 Other IDE Rules Page 46. If the device returns Completion 
with IDE -TLP, the host is not ready yet and will reject such TLP.  
IDE Stream Stop  
The host software may use following sequence in Table 1 -8 to stop IDE stream with the 
device.  
Table B-7: IDE Stream Stop Example  
1  Clear IDE Stream Enable 
bit for the device  and 
check Status bit.  The port must return the 
an IDE TLP, then stop IDE. 
[PCIe IDE 1.0] 6.99.3 IDE Appendix  B: Secure Device Interface Lifecycle Example  
  
70        Document Number:  354272 -001    
Key Management (IDE_ KM) 
Page 24. 
Now the device shall only use Non -IDE-TLP to transmit or receive TLPs. The IDE stream is in 
Insecure state. The host SOC still has IDE enabled. If the host uses IDE -TLP to communicate 
with the device, the device will reject.  
2 Clear IDE Stream Enable 
bit for SOC.    
Now both sides shall use Non -IDE-TLP to transmit or receive.  
3  (Optionally ) Send IDE_KM 
message  – K_SET_STOP  
and process the 
K_GOSTOP_ACK 
response . The K_SET_STOP is for each 
Tx). 
 
NOTE:  
1. In link IDE stream use case, step 1 must be prior to step 2. If we put step 2 before step 1, the

Page 24. 
Tx). 
 
NOTE:  
1. In link IDE stream use case, step 1 must be prior to step 2. If we put step 2 before step 1, the 
host SOC would send a Non -IDE-TLP for PCI CFG cycle to the device to clear IDE Stream 
Enable bit, but the devic e can only accept an IDE -TLP. The consequence is that the device will 
reject this Non -IDE-TLP, and there is no way to disable the link IDE stream gracefully.  
2. Once the IDE stream is disabled in step 1, the device can only send Non -IDE-TLP. If the 
device  needs to generate an interrupt before step 2, the interrupt will be lost in link IDE 
stream use case.  
IDE Stream Key Refresh  
The host software may use following sequence  in Table 1 -9 to refresh IDE keys with the 
device.  
Table B-8: IDE Stream Key Refresh Example  
1 Ensure IDE is enabled.  Ensure IDE is enabled.  This is to avoid confusion 
with IDE Stream Start.  
2 Program new IDE key to 
SOC key programming 
registers with new key 
set. Send IDE_KM message  – 
the KP_ACK response  with 
new key set.  The KEY_PROG is for each 
Tx). 
3 Trigger new IDE key set 
for SOC in Rx direction.  Send IDE_KM message  – 
response  with new key set 
in Rx direction.  The K_SET_GO is for each 
CPL) and direction in (Rx).  Appendix  B: Secure Device Interface Lifecycle Example  
  
71        Document Number:  354272 -001    
Now SOC and device still use old keys for transmit and receive, because the port shall 
continue to accept IDE TLPs usi ng the established key set until it receives an IDE TLP using 
the new key set. [PCIe IDE 1.0] 6.99.3 IDE Key Management (IDE_ KM) Pa ge 23. 
4 Trigger new IDE key set 
for SOC in Tx direction.  Send IDE_KM message  – 
respon se with new key set 
in Tx direction.  The K_SET_GO is for each 
CPL) and direction in (Tx).  
Now SOC and device will use new keys for transmit and receive.  
The port shall be ready to use the new key set no more than 10ms after the  receipt of the 
K_SET_GO. The old keys shall be invalidated and never be used, if the port receives IDE TLP 
with new key. [PCIe IDE 1.0] 6.99.3 IDE Key Management (IDE_ KM) Pa ge 23. 
 
NOTE:  
According to [PCIe IDE 1.0] 6.99.3 IDE Key Management (IDE_ KM) Pa ge 23, “The agent 
implementing the Requester role for IDE_KM must send K_SET_GO commands to enable the 
Receivers at both IDE Partner Ports, and then send K_SET_GO commands to enable the 
Transmitters at both IDE Partner Ports. ” 
 
TDI Life cycle Management  
TDI Assignment  
The VMM follows the above software flow to initialize the device resource and assign to 
TEE. There are two resource configuration models:  
• Static Configuration Model : VMM allocates resource when the TDI is initialized and 
hopes the TEE can accept the resource later.  
• Lazy Configuration Model : VMM does not allocate resource for the TDI until the TEE 
starts to accept the configuration.  
Table B-9: TDI Assignment Example  
1 VMM invokes TSM 
to negotiate wi th 
DSM . TSM sends TDISP messages  including 
TDISP_GET_VERSION, TDISP_GET_CAPABILITIES, and  
2 VMM creates device 
interface context VMM creates the device interface context for the TDI in 
TDISP CONFIG_UNLOCKED state.  Appendix  B: Secure Device Interface Lifecycle Example  
  
72        Document Number:  354272 -001    
and configures the 
TDI. VMM allocates MMIO resources for the device.  
In static configuration model , VMM builds the trusted 
DMA table between the TDI and the TVM private memory.  
to move it to TDISP 
CONFIG_LOCKED  
state.  TSM sends TDISP message  – LOCK_INTERFACE_REQUEST  
and processes the response.  
4 VMM assigns TDI to 
TVM. VMM exposes the device interface to a T VM, for example, 
PCI Express  enumeration.  
TVM gets the TDI associated device interface handle from 
the VMM.  
5 TVM gets the device 
measurements, then 
TVM verifies the 
information.  TVM gets device SPDM certificates and SPDM 
measurements.  
TVM device verifier should verify the certificates and the 
measurements according to the device attestation policy 
(policy definition is out of scope of this document).  
Finally, T VM calls TSM to accept the device.  
4 TVM gets device 
interface report and 
verif ies it.  TVM invokes TSM to send TDISP message  – 
GET_DEVICE_INTERFACE_REPORT , then get the response.  
TVM verifies the fields in the device interface report, such 
as if firmware update is permitted, if TDI generates DMA 
request with or without PASID, etc.  
5 TVM accepts the 
MMIO and DMA 
mappings in the 
report.  TVM accepts all device MMIO pages described in al l 
MMIO_RANGEs in the report. T VM accepts the DMAR 
information.  
In lazy configuration model , VMM will get an exception 
when T VM performs the accept, then the VMM can add 
those resources  and they can be accepted by T VM. 
6 TVM calls TSM and 
VMM to move the 
TDI into TDISP RUN  
state.  TVM invokes TSM to send and receive TDISP message  – 
START_INTERFACE_REQUEST , then get the response.  
7 TVM pins/unpins 
private GPA pages 
as part as DMA 
allocate/free.  TVM may invoke VMM to ask DMA paging, if the paging is 
not requested before.  
Then T VM can accept the DMA paging. After this step, the 
TVM can perform trusted DMA and MMIO access directly 
to the TDI.  
  
73        Document Number:  354272 -001    
TDI Teardown  
If a TDI or a device is no longer needed, the VMM may need to stop the TDI or stop the device. 
There are two possible teardown models:  
• TVM  initiated teardown model : A T VM can actively teardown a TDI. For example, after 
a TVM performs device information rec ollection, the T VM does not want to trust the 
TDI anymore because its version is lower than expected. Or a T VM wants to let the 
orchestrator initiate a device runtime update. In this mode, the T VM needs to notify 
VMM to stop the TDI.  
• VMM initiated teardown  mode : If T VM does not teardown the TDI, the VMM needs to 
ensure that the TDI is  stopped gracefully after the T VM itself goes through  teardown  
mode . 
Table B-10: TDI Teardown Example  
1 TVM asks VMM to 
stop the TDI. 
(Optional, only in 
TVM initiated 
teardown model ) The T VM may notify VMM to stop the TDI.  
After the VMM returns the VMCALL, the T VM may check 
TDI state to see if it is changed to TDISP 
CONFIG_UNLOCKED.  
Following steps are common f or both T VM initiated and 
VMM initiated TDI stop.  
2 VMM moves the TDI 
to 
CONFIG_UNLOCKED  
state.  VMM invokes TSM to generate TDISP message  – 
STOP_INTERFACE_REQUEST  and process the response.  
3 VMM removes DMA 
pages and MMIO 
pages.  VMM removes entries in IOMMU’s DMA remapping 
VMM blocks MMIO pages, invalidates the IOTLB and 
unmaps MMIO pages from a T VM. 
 
 References    
 
74        Document Number:  354272 -001    
Reference s 
Standards  
[SPDM 1.2] DMTF, DSP0274 - Secure Protocol and Data Model, Version 1.2.1, June 2022, 
https://www.dmtf.org/dsp/DSP0274    
[Secured SPDM 1.1] DMTF, DSP0277 - Secured Messages Using SPDM, Version 1.1, May 2022, 
https://www.dmtf.org/dsp/DSP0277   
[SPDM WP 1.1] DMTF, DSP2058 - Security Protocol and Data Model (SPDM) Architecture 
White Paper, Version 1.1, Feb 2022, https://www.dmtf.org/dsp/DSP2058   
[SPDM Val] DMTF, IS0023 - SPDM Conformance Test Suite Guidance , 
https://www.dmtf.org/dsp/DSP -IS0023    
[PCIe 6.0] PCI -SIG, PCI Express Base Specification 6.0 .1, Version 1.0, August  2022, 
https://members.pcisig.com/wg/PCI -SIG/document/18363      
[PCIe DOE 1.0] PCI -SIG, Data Object Exchange (DOE) 1.0 ECN, March 2020, 
https://members.pc isig.com/wg/PCI -SIG/document/14143  or [PCIe 6.0] Section 6.30 – Data 
Object Exchange (DOE)  
[PCIe DOE 1.1] PCI -SIG, Data Object Exchange (DOE) 1.1 ECN , September 2022, 
https://members.pcisig.com/wg/PCI -SIG/document/18483   
[PCIe CMA 1.0] PCI -SIG, Component Measurement and Authentication (CMA) 1.0 ECN, April 
2020, https://members.pcisig.com/wg/PCI -SIG/document/14236  or [PCIe 6.0] Section 6.31 – 
Component Measurement and Authentication (CMA)  
[PCIe IDE 1.0] PCI -SIG, Integrity, and  Data Encryption (IDE) 1.0.A ECN, October 2021, 
https://members.pcisig.com/wg/PCI -SIG/document/16599  or [PCIe 6.0] Section 6.33 – 
Integrity and Data Encryption (IDE)  
[PCIe TDISP 1.0] PCI -SIG, TEE Device Interface Security Protocol (TDISP) 1.0 ECN, Ju ly 2022, 
https://members.pcisig.com/wg/PCI -SIG/document/18255   
[CXL 3.0] CXL Consortium, Compute Express Link (CXL) Specification 3.0, Version 1.0, August 
2022, https://www.computeexpresslink.org/download -the-specification      
[DICE HW] TCG, Hardware Requirements for a Device Identifier Composition Engine, March, 
2018, https://trustedcomputinggroup.org/resource/hardware -requirements -for-a-device -
identifier -composition -engine/

identifier -composition -engine/   
[DICE Attestation] TCG, DICE Attestation Architecture, March 2021 , 
https://trustedcomputinggroup.org/resource/dice -attestation -architecture/   References    
 
75        Document Number:  354272 -001    
[DICE Layering] TCG, DICE Layering Architecture, July 2020, 
https://trustedcomputinggroup.org/resource/dice -layering -architecture/   
[DICE Endorsement] TCG, DICE Endorsement Architecture for Device, May 2022, 
https://trustedcomputinggroup.org/resource/dice -endorsement -archite cture -for-devices -v1-
0-r0-38/   
[CyRes ] Cyber Resilient Module and Building Block Requirements , June 2022,  
https://trustedcomputinggroup.org /resource/cyber -resilient -module -and-building -block -
requirements/   
[SP 800 -193] NIST, Platform Firmware Resiliency Guidelines, May 2018, 
https://csrc.nist.gov/publications/detail/sp /800 -193/final   
[IETF -RATS] IETF, RFC 9334 : Remote Attestation Procedures Architecture, 
https://datatracker.ietf.org/doc/rfc9334/    
[IETF -ATTS] IETF  draft , Reference Interaction Models for Remote At testation  
Procedures, https://datatracker.ietf.org/doc/draft -ietf-rats-reference -interaction -models/   
[IETF -COSWID -EXT] IETF  draft , Reference Integrity Measurement Extension for Concise 
Software Identities,  https://datatracker.ietf.org/doc/draft -birkholz -rats-coswid -rim/   
[IETF -CORIM] IETF  draft , Concise Reference Integrity M anifest (CoRIM), 
https://datatracker.ietf.org/doc/draft -ietf-rats-corim/   
[IETF -COS WID] IETF  draft , Concise Software Identification Tags (CoSWID), 
https://datatracker.ietf.org/doc/draft -ietf-sacm -coswid/   
[S-IOV] OCP,  Scalable I/O Virtualization Revision 1.0, Version 1.2, Feb . 2022, 
https://www.opencompute.org/documents/ocp -scalable -io-virtualization -technical -
specification -revision -1-v1-2-pdf  
[Intel S -IOV] Intel Scalable I/O Virtualization Revision 1.1, September 2022, 
https://www.intel.com/content/www/us/en/develop/download/i ntel-scalable -io-
virtualization -technical -specification.html   
[Intel VT -d] Intel Virtualization Technology for Directed I/O Architecture Specification , 
Revision 4.0, June  2022, https://www.intel.com/content/www/us/en/develop/download/intel -
virtualization -technology -for-directed -io-architecture -specification.html      
[Intel RC IDE] Intel Root Complex IDE Key Configuration Unit - Software Programming Guide , 
June 2022, https://www.intel.com/content/www/us/en/io/pci -express/pci -express -
architecture -devnet -resources.html   References    
 
76        Document Number:  354272 -001    
[Intel TDX Connect] Intel TDX Connect Architecture Specification, January 2023, 
https://software.intel.com/content/www/us/en/develop/articles/i ntel-trust -domain -
extensions.html    
[AMD -SEV] AMD, AMD Secure Encrypted Virtualization (SEV), https://developer.amd.com/sev/   
[ARM -RME ] ARM, ARM Realm Management Extension (RME), 
https://developer.arm.com/documentation/den0129   
[RISCV -APTEE ] RISCV, RISCV AP TEE, https://github.com/riscv -non-isa/riscv -ap-tee   
Web Resources  
[RATLS] Integrating Remote Attestation with Transport Layer Security ( RA-TLS), 
https://github.com/cloud -security -research/sgx -ra-tls 
[OPENENCLAVE] open enclave, https://github.com/openenclave/openenclave   
[OPENENCLAVE -RATLS] attested TLS, 
https://github.co m/openenclave/openenclave/blob/master/samples/attested_tls/AttestedTLS
README.md   
[DEV -ATT -TEE] White  paper - Device Attestation Model in Confidential Computing 
Environment , https://software.intel.com/content/www/us/en/develop/articles/intel -trust -
domain -extensions.html  
 Document Number:  344991 -004US 
  
Intel® TDX Virtual Firmware 
Design Guide  
 
December  2023 
 
Document Number:  344991 -004US 
 
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning  
Intel products described herein. You agree to grant Intel a non -exclusive, royalty -free license to any patent claim thereafter 
drafted which includes subject matter disclosed herein.  
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.  
Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or servic e 
activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with 
your sy stem manufacturer or retailer or learn more at intel.com.  
Intel technologies may require enabled hardware, specific software, or services activation. Check with your system manufactur er 
or retailer.  
The products described may contain design defects or errors known as errata, which  may cause the product to deviate from 
published specifications. Current characterized errata are available on request.  
Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness 
for a particular purpose, and non -infringement, as well as any warranty arising from course of performance, course of deali ng, or 
usage in trade.  
All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Int el 
product specifications and roadmaps  
Copies of documents that  have an order number and are referenced in this document may be obtained by calling 1 -800-548-
4725 or visit www.intel.com/design/literature.htm.  
Intel, the Intel logo, are trademarks of Intel Corporation in the USA and/or other countries.  
© 2020 Intel Corporation. All rights reserved.  Introduction   
 
Contents  
1 Introduction  ................................ ................................ ................................ ...... 7 
1.1 Background  ................................ ................................ ............................  7 
1.2 Overview  ................................ ................................ ...............................  7 
1.3 Terminology  ................................ ................................ ...........................  8 
2 Architectural Overview  ................................ ................................ .....................  11 
2.1 TDVF Features  ................................ ................................ ......................  11 
2.2 TD Hardware  ................................ ................................ ........................  11 
2.3 Boot Flow ................................ ................................ .............................  12 
2.3.1  VMM Setup Phase  ................................ ................................ .... 12 
2.3.2  TDVF Launch Phase  ................................ ................................ . 12 
2.3.3  TDVF OS Boot Phase  ................................ ................................  13 
2.4 TDVF Requirements ................................ ................................ ...............  13 
2.5 Reproducibility  ................................ ................................ ......................  14 
2.5.1  Challenge  ................................ ................................ ...............  14 
2.5.2  Solution ................................ ................................ ..................  14 
2.6 Security Considerations  ................................ ................................ .........  15 
2.6.1  General Security Practice  ................................ ..........................  15 
2.6.2  Side Channel Security Practice  ................................ ..................  16 
2.6.3  Confidential Computing Virtual Firmware Security Practice  ............  16 
2.6.4  TDX Specific Security Practice  ................................ ...................  17 
3 TDVF Binary Image  ................................ ................................ ..........................  19 
3.1 Boot Firmware Volume (BFV)  ................................ ................................ . 19 
3.2 Configuration Firmware Volume (CFV)  ................................ .....................  19 
4 TD Launch  ................................ ................................ ................................ ...... 21 
4.1 TDVF initialization  ................................ ................................ .................  21 
4.1.1  VCPU Init State  ................................ ................................ ....... 21 
4.1.2  System Information  ................................ ................................ . 21 
4.1.3  Long Mode Transition  ................................ ...............................  21 
4.1.4  Setup stack to call C function  ................................ ....................  22

4.1.4  Setup stack to call C function  ................................ ....................  22 
4.1.5  Switch to UEFI environment  ................................ ......................  22 
4.2 TD Hand -Off Block (HOB)  ................................ ................................ ....... 23 
4.2.1  PHIT HOB  ................................ ................................ ...............  23 
4.2.2  Resource Description HOB  ................................ ........................  23 
4.2.3  CPU HOB  ................................ ................................ ................  24 
4.2.4  GUID Extension HOB  ................................ ................................  24 
4.3 TDVF AP handling  ................................ ................................ .................  24 
4.3.1  AP Init State  ................................ ................................ ...........  24 
4.3.2  AP Information Reporting from VMM to TDVF  ..............................  24 
4.3.3  AP initialization in TDVF  ................................ ............................  25 
4.3.4  AP information reporting from TDVF to OS  ................................ .. 26 
4.3.5  AP initialization in OS  ................................ ...............................  26 
5 TDVF UEFI Secure Boot Support  ................................ ................................ ........  29 
5.1 Provisioning UEFI Secure Boot  ................................ ................................  29 
5.2 Variable Driver  ................................ ................................ .....................  29 
6 TDVF ACPI Support  ................................ ................................ ..........................  30  
 
6.1 Source of ACPI Tables  ................................ ................................ ...........  30 
6.2 ACPI Support  ................................ ................................ .......................  30 
6.3 FADT  ................................ ................................ ................................ ... 30 
6.4 DSDT  ................................ ................................ ................................ .. 30 
6.5 FACS  ................................ ................................ ................................ ... 30 
6.6 MADT  ................................ ................................ ................................ .. 30 
7 TD Memory Management  ................................ ................................ ..................  32 
7.1 Memory Type  ................................ ................................ .......................  32 
7.1.1  Private Memory Indicator in Guest Page Table.  ............................  32 
7.2 Initial State from VMM  ................................ ................................ ...........  32 
7.2.1  Memory Type in TD Resource HOB  ................................ .............  33 
7.3 Memory Information for DXE Core  ................................ ..........................  35 
7.3.1  Memory Type in DXE Resource HOB  ................................ ...........  37 
7.4 Memory Map to TD -OS ................................ ................................ ..........  38 
7.5 Convert Shared to Private  ................................ ................................ ...... 38 
7.6 Convert Private to Shared  ................................ ................................ ...... 39 
7.7 Memory State Transition  ................................ ................................ ........  39 
7.8 Optimization Consideration  ................................ ................................ .... 40 
7.8.1  Partial Memory Initialization in Pre -UEFI ................................ ..... 40 
7.8.2  Partial Memory Initialization in UEFI  ................................ ...........  40 
7.8.3  Parallelized Memory Initialization  ................................ ...............  41 
7.8.4  Pre-allocating Virtual Device IO Buffer  ................................ ........  41 
8 TD Measurement  ................................ ................................ .............................  42 
8.1 Measurement Register Usage in TD  ................................ .........................  42 
8.2 Fundamental Support  ................................ ................................ ............  43 
8.3 Virtual Firmware Configuration  ................................ ...............................  45 
8.3.1  Build-Time Configuration  ................................ ..........................  45 
8.3.2  Launch -Time Configuration  ................................ .......................  45 
8.3.3  Runtime Configuration ................................ ..............................  45 
8.3.4  Hypervisor Specific Configuration Interface  ................................ . 45 
8.4 Attestation and Quote Support  ................................ ...............................  46 
9 TDVF Device Support  ................................ ................................ .......................  48 
9.1 Minimal Requirement  ................................ ................................ .............  48 
9.2 VirtIo Requirement ................................ ................................ ................  48 
9.3 Security Device  ................................ ................................ ....................  48 
9.4 HotPlug Device  ................................ ................................ .....................  49 
9.5 PCI Device Option ROM  ................................ ................................ .........  49 
10 Exception Handling  ................................ ................................ ..........................  50 
10.1  Virtualization Exception (#VE)  ................................ ................................  50 
10.2  Instruction Conversion ................................ ................................ ...........  50 
11 TDVF Metadata  ................................ ................................ ................................  51 
11.1  TDVF Metadata Location  ................................ ................................ ........  51 
11.2  TDVF descriptor  ................................ ................................ ....................  51 
12 OS Direct Boot  ................................ ................................ ................................  56 
12.1  Measurement  ................................ ................................ .......................  56 
13 Minimal TDVF (TD -Shim) Requirements  ................................ ..............................  58 Introduction   
 
13.1  Hardware Virtualization -based Containers  ................................ ................  58 
13.1.1  TD Container Requirements  ................................ ......................  58 
13.2  TD-Shim Launch  ................................ ................................ ...................  58 
13.2.1  TD-Shim AP Handling  ................................ ...............................  59 
13.3  TD-Shim Secure Boot Support  ................................ ................................  59 
13.4  TD-Shim ACPI Support  ................................ ................................ ..........  59 
13.5  TD-Shim Memory Management  ................................ ...............................  59 
13.5.1  Memory Type in Initialization  ................................ ....................  59 
13.5.2  Memory Map for OS  ................................ ................................ . 60 
13.6  TD-Shim Measurement  ................................ ................................ ..........  60 
13.6.1  TD Measurement  ................................ ................................ ..... 60 
13.6.2  TD Event Log  ................................ ................................ ..........  61 
13.7  TD-Shim Device Support  ................................ ................................ ........  61 
13.8  TD-Shim Exception Handling  ................................ ................................ .. 61 
14 Disk Encryption  ................................ ................................ ...............................  63 
14.1  Overview  ................................ ................................ .............................  63 
14.2  Attestation Agent  ................................ ................................ ..................  65 
14.2.1  Network Communication  ................................ ...........................  65 
14.2.2  Authenticated Secure Session  ................................ ...................  65 
14.2.3  Key Server Information  ................................ ............................  65 
14.2.4  Key transport from Server  ................................ ........................  66 
14.3  Decryption Agent  ................................ ................................ ..................  66

14.3  Decryption Agent  ................................ ................................ ..................  66 
14.3.1  Key Passing – SVKL table  ................................ .........................  66 
14.3.2  Storage Volume Key Usage in TDVF  ................................ ...........  66 
14.4  High-level Flow Examples  ................................ ................................ ...... 66 
14.4.1  Example on Full Disk Encryption  ................................ ................  66 
14.4.2  Example on Data Partition Encryption  ................................ .........  67 
Appendix A  - References  ................................ ................................ ................................ ... 68 
 
Figures  
Figure 1 -1:  Intel TDX Architecture  ................................ ................................ ..........................  8 
Figure 3 -1:  TDVF Configuration Firmware Volume  ................................ ................................ ... 20 
Figure 4 -1:  TDVF General Flow  ................................ ................................ .............................  23 
Figure 7 -1:  TD Hob and Initial Memory Layout  ................................ ................................ ....... 33 
Figure 7 -2:  DXE HOB and Runtime Memory Layout  ................................ ................................ . 37 
Figure 7 -3:  TDVF Memory State Transition  ................................ ................................ .............  39 
Figure 8 -1:  TDVF Measurement  ................................ ................................ ............................  44 
Figure 8 -2:  TDVF Measurement Interface ................................ ................................ ...............  45 
Figure 8 -3:  Attestation and Quote  ................................ ................................ .........................  46 
Figure 11 -1:  TDVF Metadata Layout  ................................ ................................ ......................  51 
Figure 14 -1:  Preboot Disk Decryption Flow ................................ ................................ .............  64 
Figure 14 -2: Early -boot Disk Decryption Flow  ................................ ................................ ..........  64 
 
Tables   
 
Table 1 -1:  Differences between VMX and TDX  ................................ ................................ ..........  8 
Table 1 -2:  Terminology  ................................ ................................ ................................ .........  8 
Table 7 -1:  Memory Type in TD Resource HOB  ................................ ................................ ........  33 
Table 7 -2:  TDVF memory state from VMM  ................................ ................................ ..............  34 
Table 7 -3:  Memory Type in DXE resource HOB  ................................ ................................ ....... 37 
Table 8 -1:  TD Measurement -related Register  ................................ ................................ .........  42 
Table 11 -1:  TDVF_DESCRIPTOR definition  ................................ ................................ .............  52 
Table 11 -2:  TDVF_SECTION definition  ................................ ................................ ...................  52 
Table 11 -3:  TDVF_DESCTION.Type definition  ................................ ................................ .........  53 
Table 11 -4:  TDVF_DESCTION.Attributes definition  ................................ ................................ .. 53 
Table 11 -5:  TD_INFO definition  ................................ ................................ ............................  54 
Table 12 -1:  OS loader measurement  ................................ ................................ .....................  56 
Table 13 -1:  TD -Shim memory state from VMM  ................................ ................................ ....... 59 
Table 13 -2:  TD Measurement -Related Registers for TD -Shim ................................ ...................  60 
Table 14 -1:  Disk Encryption Use Cases  ................................ ................................ ..................  63 
Table 14 -2: Security Property Example ................................ ................................ ...................  64 
 
Intel Total Memory Encryption (TME) engine encrypts the platform’s entire memory 
with a single key and provides the ability to specify use of a specific key for a page of 
memory . The Multi-Key mode of TME (MK -TME) extends TME to support multiple 
encryption keys.  In a virtualization scenario, a Virtual Machine Manager (VMM) or 
hypervisor will manage keys to transparently support legacy operating systems 
without any changes (thus, MKTME can also be viewed as TME virtualization in these 
scenarios). An operatin g system (OS) may take advantage of MKTME capabilities in a 
native or virtualized environment. When properly enabled, MKTME is available to each 
guest OS in a virtualized environment, so both native and guest OS can take 
advantage of MKTME.  In these usages, the VMM is in the Trust Computing Base ( TCB). 
Intel Trust Domain Extensions ( Intel TDX) refers to an Intel technology that extends 
Virtual Machines Extensions (VMX)  and Multi -Key Total Memory Encryption (MKTME)  
with a new kind of virtual machine guest called  a Trust Domain (TD) .  A TD runs in a 
CPU mode that protects the confidentiality of its memory contents and its CPU state 
from any other software, including the hosting Virtual Machine Monitor (VMM), unless 
explicitly shared by the TD itself.  
The TDX solution is built using a combination of Intel® Virtual Machine Extensions 
(VMX) and Multi -Key Total Memory Encryption (MK -TME), as extended by the Intel®  
Trust Domain Instruction Set Architecture Extensions (TDX ISA) .  An attested software 
module called The Intel TDX module  implements the TDX architecture.  
The platform is managed by a  TDX-aware host VMM .  A host VMM can launch and 
manage both guest TDs and legacy guest  VMs.  The host  VMM maintains all legacy 
functionality  from the legacy VMs perspective ; it’s restricted only wit h regard to the 
TDs it manages . 
In Summary, Intel TDX : 
1) Remove s the cloud host software and devices from the Trust Computing Base 
(TCB) of cloud ( TD) tenants . 
2) Provide s memory encryption and integrity multi-tenancy for hardware  attack 
protection . 
3) Support s TD measurement for attestation  to a relying party . 
Intel® Trust Domain Extensions (Intel® TDX) provides the capabilities required to 
enable an TDX -aware VMM to manage the lifecycle of a TD.   
 
Figure 1-1:  Intel TDX Architecture  
Fundamental differences between Virtual Machine Extension  (VMX) and Intel TDX are 
outlined in the following table.  
Table 1-1:  Differences between VMX and TDX  
 Access to Guest 
State  Transitions for State 
Save & Restore  Controls  
VMX VMM has full access  VMM SW augments VMX 
transitions (e.g. general -
purpose  registers)  VMM has a rich set of 
controls to interact with 
the VM in order to de -
privilege the VM  
TDX VMM has no direct 
access;  
TD may volunteer info  State transitions 
completed are managed 
by Intel TDX Module  in 
Secure -Arbitration Mode 
(SEAM)   VMM has a limited set of 
controls for resource 
management  
Trust Domain Virtual Firmware (TDVF) is required to provide TD services to the TD 
Guest OS. This document describes the TDVF architecture.  
TDVF reference code is integrated to TianoCore open source repository:  
https://github.com/tianocore/edk2/tree/master/OvmfPkg . A minimal TDVF (td -shim) 
reference code is at confidential container repository:  https://github.com/confidential -
containers/td -shim. 
 
Table 1-2:  Terminology   
ACPI Advanced Configuration and Power Interface  
Introduction   
 
AP Application Processor  
APIC Advanced Programmable Interrupt Controller  
BFV Boot Firmware Volume  
BSP Bootstrap Processor  
CFV Configuration Firmware Volume  
CSM Compatibility Support Module  
DXE Driver Execution Environment  
EPT Extended Page Table  
GPA Guest Physical Address  
GPAW  Guest Physical Address Width  
HOB Hand Off Block  
HPA Host Physical Address  
MADT  Multiple APIC Description Table  
MKTME  Multi-Key Total Memory Encryption  
MPWK  Multiple Processor Wakeup  
MRCONFIGID  Measure ment Register of configuration data  
MRTD  TD Measure ment Register  
OVMF  Open Virtual Machine Firmware  
PEI Pre-EFI Initialization  
RA-TLS Remote Attestation -TLS 
RTMR  Runtime Extendable Measurement Register  
SEAM  Secure -Arbitration Mode  
SEC Security Phase  
SMM System Management Mode  
SMX Safer Mode Extensions  
TCB Trust Computing Base  
TCG Trusted Computing Group  
TDVF Trust D omain Virtual Firmware

TDVF Trust D omain Virtual Firmware  
TDX (Intel) Trust Domain Extensions  
TME Total Memory Encryption  
UEFI Unified Extensible Firmware Interface  
VCPU  Virtual CPU  
VE Virtualization Exception  
VM Virtual Machine   
 
VMCS  Virtual Machine Control State  
VMM Virtual Machine Monitor  
VMX Virtual Machine Extension  
 
§ Architectural Overview   
 
2 Architectural  Overview  
2.1 TDVF Features  
TDVF has the following features:  
1) Use Unified Extensible Firmware Interface  (UEFI) Secure Boot as base with 
extensions for TD launch . 
2) Use Trusted Computing Group (TCG) Trusted Boot to perform a measured and 
verified launch of a guest  OS loader  or kernel . 
3) Simplify firmware by removing features found in traditional UEFI implementations:  
a) SEC, PEI, SMM (DXE Only)  
b) CSM (UEFI Class 3 OS only)  
c) Setup  UI 
d) Recovery  
e) Capsule -based Firmware Update  
f) ACPI S3 (not supported by TDX guest s) 
2.2 TD Hardware  
A TD is based on the following hardware:  
1) CPU: x2APIC  
2) CPU: xFLUSH, STI, CLI, LIDT, LGDT  instruction are allowed.  
3) VMM-specific Virtual Device (block device, console, network ). This is highly 
dependent on the hypervisor configuration (e.g. VirtIo device for KVM/XEN, 
Vmbus device for Microsoft Hyper -V). 
4) Hot Plug  – CPU and memory hotplug are not supported now. Device hotplug is out 
of scope of this document.  
5) TD may or may not support below feature. If it is supported, the device must be 
access via TD CALL [TDG.VP.VMCALL]  interface instead of direct hardware access. 
For example, the IO access needs to be replaced by TDCALL [TDG.VP.VMCALL] 
<INSTRUCTION .IO>.  
a) Persistent NV storage.  
b) The emulated physical device. (Graphic, Keyboard, Storage, etc.)   
 Architectural Overview  
 
c) I/O Subsystems (PCI, USB, ISA, DMA, IOMMU, PIC, PIT, etc.). For example, 
the PCI might only be used to emulate the VirtIo device.  
d) MMIO (APIC, HPET)  
e) vTPM  
2.3 Boot Flow  
A TD launch takes below steps:  
1) VMM sets up TDVF, calls Intel TDX module  to create the initial measurement, then 
calls Intel TDX module to launch TDVF.  
2) TDVF boots and enables UEFI Secure Boot.  
3) TDVF prepares CC event log and launches the OS loader.  
2.3.1  VMM Setup Phase  
The TDVF image includes firmware code, which is measured into TD Measure ment 
Register  (MRTD ). The TDVF image may als o include static configuration data, including 
UEFI Secure Boot certificates (PK/KEK/db/dbx). The VMM provides dynamic 
configuration data, including the hand-off block  (HOB) list as a parameter for the 
entrypoint.  
The VMM  calls Intel TDX module to initialize TD memory . This includes firmware code  
and UEFI Secure Boot configuration read -only data captured by the tenant:  
• Intel TDX module associates memory via Extended Page Table ( EPT) with the 
TD gue st. 
• Intel TDX module associates logical processors with TD guest via TD -Virtual 
Machine Control State ( VMCS ). 
• Intel TDX module performs TDENTER instruction on all processors , including 
Bootstrap Processor ( BSP) and Application Processors ( APs). 
2.3.2  TDVF Launch Phase  
TDVF is launched on all processors:  
• All processors start in 32 -bit protected mode with flat descriptors  (paging  
disabled) . 
• The CPU with VCPU_INDEX 0 is elected as BSP, the other CPUs are APs.  
• Startup code switches to 4 -level paging enabled (0 -4GB). Option for startup 
code to switch to 5 -level paging enabled (0 -4GB). 
• BSP performs Virtua l Firmware initialization and determines how many APs to 
wake via TD CALL [TDG.VP. INFO]. Architectural Overview   
 
• APs perform TDCALL [TDG.VP. INFO] and wait for virtual -wake triggered in -
memory by BSP. 
2.3.3  TDVF OS Boot Phase  
The TDVF prepared information and boots to OS loader finally.  
• Memory map is prepared, and private memory is used.  
• ACPI Tables report platform information.  
• UEFI Secure Boot is enabled.  
• CC event log is prepared.  
• APs are in wait for wake -up. 
2.4 TDVF Requirements  
TDVF should  meet the following requirements:  
1) TDVF is launched by a hypervisor  and Intel TDX module (see ' TD Launch ' for 
details).  
a) The entry point of TDVF is 32-bit protected mode, launched by Intel TDX 
module . 
b) TDVF enables long mode and continues to run in long mode.  
c) TDVF parses system information passed from the hypervisor.  
d) TDVF halts the AP till AP wakeup.  
2) TDVF launches guest TD.  
a) TDVF starts the guest TD OS loader.  
b) TDVF provides memory map to guest TD  (see ' TD Memory Management ' for 
details).  
c) TDVF provides ACPI table to guest TD  (see ' TDVF ACPI Support ' for details).  
d) TDVF supports multi -processors and allows guest TD to wake up APs. (see 
'TD Launch ' for details).  
3) Security  
a) TDVF enables UEFI Secure Boot  (see ' TDVF UEFI Secure Boot Support ' for 
details)  
b) TDVF creates the CC event log and pass it to guest TD  (see ' TD 
Measurement ' for details).  
c) TDVF  sets up private memory (see ' TD Memory Management ' for details).   
 
2.5 Reproducibility  
If a virtual firmware  (TDVF or Td-shim) is used in a service  TD, the binary should be 
reproducible, meaning you can recreate the same release binary  with the same source 
code version and same compiler version. This condition should be true under any 
circumstances, anytime, on any machine, and any source path location.  
2.5.1  Challenge  
There are reproducibility  challenges today. For example, some C code may use 
__FILE__, __LINE__, __DATE__, __TIME__ as the build -in information. The __FILE__ 
may change  based on the file location. __DATA__ and __TIME__ may change based 
on the build time.  
The compiler may generate a debug entry, including  a source file path . 
For a PE/COFF image, the compiler may generate a time stamp for when the binary is 
created. In addition, the compiler may include  the unique GUID to provide detailed 
debugging information.  Refer to the Microsoft PE/COFF specification  for more details . 
For a Rust project, t he Rust compiler may add additional tool file paths, such as 
CARGO_HOME and RUSTUP_HOME.  Rust compiler may generate different image with 
different username . 
2.5.2  Solution  
To resolve the reproducibility  challenge, we have the following recommendation : 
2.5.2.1  Code  
The C code should use __FILE__, __LINE__, __DATE__, __TIME__ only for debug 
purposes.  
If present, the info should be included in the DEBUG macro and removed in release 
build.  
2.5.2.2  Compiler Option  
Don’t generate any debug info in the release build. Strip all symbols.  
2.5.2.3  Additional tools  
The additional tools should be created to zero the debug data fields in the PE image, 
and zero the time stamp and unique GUID.  
For example,  the EDKII project  (using C)  includes a `GenFW` tool that has -z, --zero 
option to zero such information. The Td-shim project (using Rust ) includes a ` td-shim-
strip-info` tool that can zero such information for a PE image and zero the Rust tool 
path. Architectural Overview   
 
2.5.2.4  Docker Image  
Docker image may be used for Rust based Td-shim project . It is to ensure that the 
same username is used when building the final image.  
2.6 Security Considerations  
This section introduces security practice s for the TD virtual firmware . The Linux kernel 
version is at https://intel.github.io/ccc -linux-guest -hardening -docs/security -spec.html . 
2.6.1  General Security Practice  
2.6.1.1  Minimize the Attack Surface  
The virtual firmware should include a driver only when it is necessary. For example, 
the TCP/IP network  is a big attack surface , and it should be excluded in the TDVF.   
2.6.1.2  Input Validatio n 
Any input data from VMM should be treated as untrusted. The data must be verified 
before use. If the data is in shared memory, TDVF should copy the data to private 
memory, then validate and use.  
2.6.1.3  Enable Defensive Technologies  
TDVF should consider enabl ing the following technologies:  
1) Data Execution Protection (DEP)  
The virtual firmware  may set up  DEP to mark data regions  (including stack and heap) 
to be non -executable, an d mark  code regions  to be read-only to prevent code 
injection attacks . 
2) Address Space Layout Rando mization  (ASLR)  
The virtual firmware  may use ASLR for the heap /stack allocation. The effectiveness of 
ASLR is based upon random bit entropy. If the T DVF only has limited memory 
resource s, then the entropy bit cannot be too large. But shifting even a few bits offers 
some benefit . 
3) Control Flow Enforcement Technology (CET)  
The virtual firmware  may set up  CET Shadow Stack (SS) protection to prevent Return 
Oriented Programming (ROP) attacks .

Oriented Programming (ROP) attacks . 
The virtual firmware  may set up CET Indirect Branch Tracking (IBT) to prevent Jump 
Oriented Programming (JOP) attacks . This mainly depends upon the compiler’s 
capability.   
 
2.6.2  Side Channel  Security Practice  
The T DVF should consider side channel attacks  that may steal secret s, including but 
not limited to the disk encryption key, TLS session key, SPDM session key, ephemeral 
private key, etc. The host firmware version is at 
https://www.intel.com/content/www/us/en/developer/articles/technical/software -
security -guidance/technical -documentation/host -firmware -speculative -side-channel -
mitigation.html . 
2.6.2.1  Bound Check Bypass  (Spectre Variant 1)  
The T DVF should use LFENCE before parsing any VMM input data  if the data includes 
length or offset  field, such as CFV and TD_HOB.  
Care must be taken that the data from the device might also be from VMM , including 
MMIO , IO, or PCI Configuration. The device driver should also  follow the same rule  to 
consume the length or offset field s. 
2.6.2.2  Branch Target Injection  (Spectre Variant 2)  
N/A. Branch predictions cached by the CPU before entering a guest TD should not 
impact the behavior of that TD. The Intel TDX module helps ensure that by applying 
CPU mechanisms to isolate the branch predictions of each guest TD from branch 
predication s done elsewhere . 
2.6.2.3  Rogue Data Cache  Load (Meltdown Variant 3)  
N/A. The TDVF is a bare metal execution environment. All code runs in supervisor 
mode.  
2.6.2.4  Rogue System Register Load (Meltdown Variant 3a)  
N/A. 
2.6.2.5  Speculative Store Bypass  (Spectre Variant 4)  
N/A. 
2.6.3  Confidential Computing  Virtual Firmware  Security Practice  
2.6.3.1  Measured Boot  
TDVF should follow the measured boot principle  to construct the chain of trust.  
Any configuration data from VMM should be measured to a measurement register 
(MR) before being used, including but not limited to the data in CFV, TD_HOB (ACPI), 
or VMM specific configuration, such as QEMU FW_CONFIG_IO.  
The dynamic data from VMM, such as device state  or device base address register , 
should not be measured.  These data should be treated as untrusted input and should 
be verified before use.  Architectural Overview   
 
Please refer to chapter 8 TD Measurement for more detail.  
2.6.3.2  Random Number  
If a random number is required, TDVF should only use RDSEED/RDRAND CPU 
instruction . 
Other software random number, such as virtio-rng is not trusted.  
2.6.3.3  Timer  
TDX architecture does not provide a trusted timer . The legacy source, such as 
Runtime -Clock ( RTC) via port 0x70/0x71  is not trusted.  
If a trusted timer is required, the TDVF should connect to a n authenticated time 
server.  
2.6.3.4  CPU Information  
The TDVF may require accessing CPU information  such as CPUID  or MSR. Most of 
those resources are emulated by VMM , and they cannot be trusted.  
Only a small portion of CPUID and MSR are provided  to the TDX -module, and they can 
be trusted. Please refer to  the TDX Module architecture specification, chapter 18 ABI 
reference: CPU Virtualization Tables.  
2.6.3.5  Device Information  
The TDVF may require accessing  resource s such as MMIO, IO, PCI Configuration 
Space, etc.  Those resources are em ulated by VMM , and they cannot be trusted.  TDVF 
should verify the data before use.  
2.6.4  TDX Specific Security Practice  
2.6.4.1  Private Memory Acceptance  
The TDVF needs to use TDCALL[ TDG.MEM.PAGE.ACCEPT ] to accept PENDING pages 
added by VMM via SEAMCALL[TDH.MEM.PAGE.AUG]  
The TDVF should track the accepted pages and not accept the previously  accepted 
memory.  Otherwise, the VMM could zero -out a page by removing it  and add a new 
one at the same address.  
2.6.4.2  MMIO Access in #VE handler  
To support an unmodified driver using MMIO, a  TDVF may implement a Virtualization 
Exception (#VE)  handler  for an extended page table ( EPT) violation . The #VE handler 
will use the guest physical address (GPA) as the MMIO address in 
TDCALL[ TDG.VP.VMCALL ]<#VE.RequestMMIO>.   
 
In #VE handler, t he TDVF should check if the SHARED bit is set in the GPA , and 
should reject this request if the SHARED bit is clear.  Otherwise, the VMM could remove 
an accepted page and TDH.MEM.PAGE.AUG the same page to put the page in 
PENDING state. Then the VMM could use 
TDCALL[ TDG.VP.VMCALL ]<#VE.RequestMMIO> to inject the malicious data  to the 
private page .  
2.6.4.3  TD ATTRIBUTES .SEPT_VE_DISABLE  
Ideally, the VMM should set SEPT_VE_DISABLE in the TD ATTRIBUTES to prevent an 
EPT violation to #VE caused by guest TD access of PENDING pages.  
The TDVF early boot code should read the TD ATTRIBUTES  via TDCALL[ TDG.VP.INFO ] 
to ensure the VMM set s the SEPT_VE_DISABLE  bit. Otherwise, there is risk in the #VE 
handler for this EPT violation . 
2.6.4.4  TDCS.NOTIFY_ENABLES  
TDX module may raise a #VE as a notification mechanism when it detects excessive 
Secure EPT violations raised by the same TD instruction (zero -step attack is suspected  
by TDX module). This is only done if bit 0 of TDCS.NOTIFY_ENABLES field is set.  
TDCS.NOTIFY_ENABLES  is 0 by default. The TDVF should not set the 
TDCS.NOTIFY_ENABLES  via TDCALL[ TDG.VM. WR]. Otherwise, there is risk in the #VE 
handler  for this EPT violation . 
 
 TDVF Binary Image   
 
3 TDVF Binary Image  
This chapter describes the TDVF binary image format.  
3.1 Boot Firmware Volume (BFV)  
The TDVF includes one Firmware Volume (FV) known as the Boot Firmware Volume. 
The FV format is defined in the UEFI Platform Initialization (PI) specification.  
The Boot Firmware Volume includes all TDVF components required during boot.  
1) TdResetVector  – this component provides the entrypoint for TDVF, switch to long 
mode, and jumps to the DxeIpl. The FFS GUID must be 
EFI_FFS_VOLUME_TOP_FILE_GUID, which is defined in PI specification.  
2) TdDxeIpl  – This component prepares the required parameter for DxeCore and 
jumps to DxeCore.  
3) DxeCore  – This is standard DxeCore, used in standard UEFI firmware. It 
dispatches all DXE modules.  
4) DXE Modules – These are TDVF-specific  modules, to initialize the TDVF 
environment and launch the OS loader.  
The BFV may include an initial static page table to assist the ResetVector switch from 
32-bit mode to 64-bit mode.  
3.2 Configuration Firmware Volume (CFV)  
TDVF may also include a configuration firmware volume  (CFV)  that is separated from 
the boot firmware volume . The reason to do this is because the CFV is measured in 
RTMR, while the boot FV is measured in MRTD .  
Configuration Firmware Volume includes all the provisioned data. This region is read 
only. One possible usage is to provide UEFI Secure Boot Variable content in this 
region, such as PK, KEK, db, dbx.  
This region may include additional configuration variables.  
The file system GUID must be EFI_SYSTEM_NV_DATA_FV_GUID , which is defined i n 
NvDataGuid.h .  
 TDVF Binary Image  
 
The variable storage header must be VARIABLE_STORE_HEADER, and the variable 
header must be VARIABLE_HEADER. Both are  defined in 
https://github.com/tianocore/edk2/blob/master/MdeModulePkg/Include/Guid/Variable
Format.h . 
 
Figure 3-1:  TDVF Configuration Firmware Volume  
TD Launch   
 
4 TD Launch  
This chapter describes how a VMM passes control to TDVF.  
4.1 TDVF initialization  
Because TDVF relies on Intel TDX module , initialization flow is different from the 
typical firmware used for VM support (e.g. Open Virtual Machine Firmware  (OVMF)).  
4.1.1  VCPU Init State  
When Intel TDX module launches TDVF, the virtual CPU (VCPU) executes in 32-bit 
protected mode with flat descriptor paging disabled. See [TDX -CPU]  for details on 
the VCPU init state.  
4.1.2  System Information  
When the VMM calls Intel TDX module to launch TDVF, the VMM must build system 
information and pass it to TDVF as part of a TD HOB in RCX and R8 (the system 
memory location)  if the TD_HOB section is present in the TDVF metadata area. If the 
TD_HOB section in the TDVF metadata area is absent, then the PermMem (permanent 
memory) section must be present and VMM must follow the memory requirement in 
the permanent memory section . 
Please refer to ' TD Memory Management ' for details on memory information reporting.  
4.1.3  Long Mode Transition  
The 32-bit TDVF init code will set up  paging and switch to long mode. Because TDCALL 
is only valid in long mode, the 32-bit TDVF init code cannot invoke TDCALL to convert

is only valid in long mode, the 32-bit TDVF init code cannot invoke TDCALL to convert 
private memory regions, and 32-bit TDVF init code cannot access any permanent 
memory.  
The 32-bit TDVF init code may refer to an initial temporary page table inside of the 
TDVF flash image (ROM page table), which is created at build time. Because the page 
table is not updatable, the page table Access Bit and Dirty Bit must be set to 1. The 
ROM page ta ble must be in the Boot Firmware Volume if it is implemented.  
Once TDVF switches to long mode it will obtain permanent memory information from 
the resource description HOB, allocate private memory, and create the final page table 
in private memory.  
The TDVF should refer to  GPAW (RBX[0:6] ) to decide how much memory can be 
covered by the page table. If the GPAW is 48bit, then TDVF should set up  4 level 
paging. If the GPAW is 52bit, the TDVF should set up  5 level paging.  
  
 TD Launch  
 
4.1.4  Setup stack to call C function  
The 32-bit TDVF init code runs on the flash. Because it cannot access any permanent 
memory, the code cannot use stack, which is required by C language.  
After TDVF switches to the long mode and issues TDCALL to convert the shared 
memory to private memory, the TDVF can set up  stack in the private memory and call 
C function.  
4.1.5  Switch to UEFI environment  
The purpose of PEI is to detect and initialize memory. Since TDVF already knows the 
memory information via the HOB, the TDVF may skip PEI phase for information 
collection, and jump directly to DXE. If more HOB entry is required, the TDVF may 
allocate a new HOB from permanent memory and pass it to DXE.  
The whole boot flow is shown below:  
Stage 1: TD Init Code - 32-bit protected mode (stackless)  
1) Use the TDVF flash image for ROM page table.  
2) Switch to long mode  
 
Stage 2: TD Init Code - 64-bit long mode (stackless)  
1) Parse the TD Hob to get the memory location.  
2) Set up  initial private page, now we can use memory . 
3) Set up  temp stack from private page  
4) Jump to C -code.  
 
Stage 3: TD Init Code - 64-bit long mode (C -code)  
1) Setup TD Initial Heap from private page.  
2) Create the DXE Hob in the heap, based upon TD Hob.  
3) Setup final page table in the heap.  
4) Set up  final stack in the heap.  
5) Relocate DXE core in the heap.  
6) Jump to DXE  
 
Stage 4: UEFI environment  
1) Dispatch drivers.  
2) Wake up APs  
3) Setup ACPI table  
4) Prepare TD measurement  
5) Prepare memory map  
6) Start Console and storage Device  
7) Invoke OS loader  
 
Stage 5: OS environment  
1) Init OS  
2) Wake up APs.  
The following figure shows the general TDVF  flow. TD Launch   
 
Figure 4-1:  TDVF General  Flow  
 
4.2 TD Hand -Off Block (HOB)  
The TD HOB list is used to pass the information from VMM to TDVF. The HOB format is 
The TD HOB must include  PHIT HOB, Resource Descriptor HOB . Other HOBs are 
optional.  
The TDVF must create its own DXE HOB based upon TD HOB and pass the DXE HOB to 
DXE Core. The DXE HOB requirements are  described in the UEFI PI specification.  
4.2.1  PHIT HOB  
The TD HOB must include PHIT HOB as the first HOB. EfiMemoryTop , 
EfiMemoryBottom , EfiFreeMemoryTop , and EfiFreeMemoryBottom  shall be zero.  
4.2.2  Resource Description HOB  
The TD HOB must include at least one Resource Description HOB to declare the 
physical memory resource.  
Any DRAM reported here should be accepted  by TDVF , except the Temporary 
memory and TD HOB region s, which are declared in the TD metadata  (see section 11). 
The resource HOB may optionally report the MMIO  and IO region s based on the guest 
hardware provided by the VMM.  
 
 TD Launch  
 
4.2.3  CPU HOB  
The CPU HOB is optional ; if it is included the TDVF must ignore it and create its own 
CPU HOB for DXE . This CPU HOB should have SizeOfMemorySpace  equal to  or smaller 
than GPAW (48 or 52) and  SizeOfIoSpace  (0 or 16) based on the IO reported by the 
Resource HOB . According to PI specification, SizeOfMemorySpace  is to “identify the 
maximum physical memory addressability of the processor”. In EDK II, t he 
SizeOfMemorySpace  value is  consumed by DXE IPL to create page table  for DXE Core . 
As such, if the memory hot plug is not supported, the value  may be set to the 
maximum supported address according to the VMM reported memory range . 
4.2.4  GUID Extension HOB  
The TD HOB may include the GUID extension HOB to describe the TD Feature, which is 
VMM or TDVF specific. Any GUID extension HOB in TD HOB must be passed to DXE 
HOB. 
4.3 TDVF  AP handling  
4.3.1  AP Init State  
The AP init state is exactly same as the BSP init state.  
The VCPU_INDEX  is reported by INIT_STATE.RSI  or TD_INFO.R9[0:31] . It is the 
starting from 0 and allocated sequentially on each successful TDINITVP . 
The NUM_VCPUS  is reported by TD_INFO.R8[0:31] . It is the Number of Virtual CPUs 
that are usable, i.e. either active or ready. The TDVF need use this number to 
determine how many CPUs will join.  
The MAX_VCPUS  is reported by TD_INFO.R8[32:63] . It is TD's maximum number of 
Virtual CPUs . This value should be ignored by the TDVF in this version. It may be used 
for other purpose in future version such as later -add. 
Intel TDX module will start t he VCPU with VCPU_INDEX  from 0 to (NUM_VCPUS – 1). 
As such, the TDVF can treat the BSP as the CPU with VCPU_INDEX 0 . However, the 
TDVF cannot assume that the CPU with VCPU_INDEX 0  is the first one to launch. The 
TDVF need s to rendezvous in early initialization code , let the BSP execute the main 
boot flow and let APs execute in the wait loop.  
4.3.2  AP Information Reporting from VMM to TDVF  
In TDX, there is no INIT/SIPI protocol. The expectation is that VMM need launch all 
VCPU to the TDVF entrypoint. After reset, all CPUs run the same initialization code. 
TDVF will do the BSP selection.  
There might be several ways for BSP selection. Here the TDVF may rely on the 
information from Intel TDX module , but the TDVF must not rely on the information 
from VMM.  TD Launch   
 
1) All CPUs try to set a global flag. The first CPU set the flag is elected as the BSP 
and does the rest of BSP work. The rest CPUs just wait for the release signal 
from the BSP, then does the rest of AP work.  (Do not rely on the information 
provided by Intel TDX module ) 
2) CPU with VCPU_INDEX  0 is BSP. CPUs with non -0 VCPU_INDEX are APs. (Rely 
on the information provided by Intel TDX module ) 
The pseudo code in TDVF is below:  
==================  
VOID 
BspSelection (  
  VOID 
  ) 
{ 
  if ( VCPU_INDEX  == 0) { 
    BspInit()  
  } else {  
    ApInit()  
  } 
} 
 
VOID 
BspInit (  
  VOID 
  ) 
{ 
  // Set up page table  
  // Jump to 64-bit mode. 
  // Set up AP MPWK mailbox. 
  // Wakeup AP for init rendezvous  
  // Do rest of initialization  
  // Wakeup AP to perform required function  
  // Jump to OS  
} 
 
VOID 
ApInit (  
  VOID 
  ) 
{ 
  // Wait for BSP init notification  
  // Jump to the 64-bit mode setup by BSP (page table, etc.) 
@Wait: 
  // Wait in MPWK mailbox 
  // Do the task assigned in MPWK mailbox 
  // jump @Wait:  
} 
4.3.3  AP initialization in TDVF  
In TDVF, there is no need to do normal CPU initialization such as configure MTRR, or 
patch Microcode. The AP is just in a wait -for-procedure state.   
 TD Launch  
 
4.3.4  AP information reporting from TDVF to OS  
In TDVF, the CPU information is reported via ACPI MADT table. The MADT need report 
the existing APIC ID and processor UID in ASL and enabled flags.  
The existing APIC ID may be got from the TD_VCPU_INFO_HOB  or MAX_VCPUS . 
The ACPI driver need assign processor UID and match them in ASL code and MADT.  
The enabled flag may be reported by TD_VCPU_INFO_HOB  with 
PROCESSOR_ENABLED_BIT , or NUM_VCPUS  or confirmed by the AP itself.  
4.3.5  AP initialization in OS  
For the system that does not support INIT -SIPI-SIPI, the platform firmware publishes 
an ACPI MADT MPWK STRUCT  in the MADT  ACPI table. Please refer to the TDX Guest 
Hypervisor Communication Interface document for the detailed data structure.  
The firmware pseudo code is shown below:  
VOID 
BspInitMailBox (  
  VOID 
  ) 
{ 
  MailBox->ApicId = ACPI_MPWK_APICID_INVALID;  
  MailBox->WakeupVector = 0;  
  MailBox->Command = AcpiMpwkCommandNoop;  
} 
 
VOID 
ApWaitForWakeup (  
  VOID 
  ) 
{ 
  while (TRUE) {  
    if (MonitorSupported()) {  
      Monitor (MailBox);  
      Mwait (Extension, Hint);  
    } 
    else if (UMonitorSupported()) {  
      UMonitor (MailBox);  
      UMwait (Extension, Hint);  
    } 
    else { 
      Pause ();  
    } 
    // 
    // Wait for wakeup  
    // 
    if (MailBox ->Command == AcpiMpwkCommandNoop) {  
      continue;  
    } 
 TD Launch   
 
    // 
    // Check if for me  
    //

VOID 
  VOID 
  ) 
{ 
} 
 
VOID 
  VOID 
  ) 
{ 
    } 
    } 
    else { 
      Pause ();  
    } 
    // 
    // 
      continue;  
    } 
 TD Launch   
 
    // 
    // 
    if (!ApIsMyMessage (MailBox ->ApicId) {  
      continue;  
    } 
 
    // 
    // Dispatch command  
    // 
    switch (MailBox ->Command) {  
    case AcpiMpwkCommandWakeup:  
      // 
      // 64-bit vector 
      // 
      UINT64 WakeupVector = MailBox ->WakeupVector;  
      // 
      // Ack MailBox  
      // 
      ReadWriteBarrier();  
      MailBox->Command = AcpiMpwkCommandNoop;  
 
      Jump64 (WakeupVector)  
      // 
      // Never returns  
      // 
      CpuDeadLoop();  
      break; 
    default:  
      break; 
    } 
  } 
} 
 
BOOLEAN 
ApIsMyMessage (  
  UINT32 ApicId  
  ) 
{ 
  if (ApicId == MyApicId()) {  
    return TRUE;  
  } 
  return FALSE;  
} 
 
The OS pseudo code is shown below:  
 
VOID 
BspWakeupThis (  
  ) 
{  
 TD Launch  
 
  ReadWriteBarrier();  
  // 
  // Fill the mailbox  
  // 
  MailBox->ApicId = ApicId;  
  MailBox->WakeupVector = ApWakeupAddress();  
 
  MailBox->Command = AcpiMpwkCommandWakeup;  
  // 
  // Wait to join  
  // 
  Command = AcpiMpwkCommandWakeup;  
  while ((Command != AcpiMpwkCommandNoop) && (!IsTimeout())) {  
    ReadWriteBarrier();  
    Command = MailBox ->Command;  
    CpuPause();  
  } 
 
  if (GetJoinedCpuApicId() != ApicId) {  
    // Something Wrong  
  } else {  
    // Good, new AP is here  
  } 
} 
 
§ TDVF UEFI Secure Boot Support   
 
5 TDVF UEFI Secure Boot Support  
This chapter describes TDVF support for UEFI Secure Boot.  
5.1 Provisioning UEFI Secure Boot  
The TDVF creator should be responsible for provisioning the UEFI Secure Boot variable 
as the CFV.  
The initialization code may build a variable hob and pass the information to variable 
driver. The GUID hob gEfiAuthenticatedVariableGuid  is defined in 
Format.h . 
5.2 Variable Driver  
The TDVF variable driver uses the emulation variable driver in EDKII. This emulation 
driver does not support non -volatile storage and uses variable storage in RAM.  
During variable initialization, the variable driver consults the variable GUID HOB data 
and initialize s the variable storage region in RAM.  
 
§  
 TDVF ACPI Support  
 
6 TDVF ACPI Support  
This section describes TDVF ACPI Support.  
Please refer to the ACPI specification for detailed information on what ACPI tables 
should be reported to OS.  
6.1 Source of ACPI Tables  
There are different ways to create ACPI table. For example:  
1) The ACPI table may be created at build time, as the part of Boot Firmware 
Volume. It is measured automatically.  
2) The ACPI table may be input at launch time, as the part of TD Hob or 
Configuration Firmware Volume. It is measured automatically.  
3) The ACPI table may be input via  a hypervisor -specific  configuration interface. 
If this method is chosen, the consumer  in TDVF  must explicit ly measure the 
raw ACPI table data to RTMR register. (See chapter 8, TD measurement).  
6.2 ACPI Support  
• ACPI S5  should be supported.  
6.3 FADT  
FADT should be configured for 'no ACPI  Hardware ' mode . 
Due to the lack of SMM support, any SMI command field in FADT must be 0.  
6.4 DSDT  
The DSDT may report PCI or IO device based upon the device emulated by the VMM.  
6.5 FACS  
No ACPI S3 support is required.  
6.6 MADT  
Please refer to ' TDVF AP handling ' (Section 4.3) for information on AP handling.  
 
 TDVF ACPI Support   
 
§ 
 
 TD Memory Management  
 
7 TD Memory Management  
This chapter describes  the memory management.  
7.1 Memory Type  
There are four defined types of TD memory:  
1) Private Memory  - SEAMCALL [ TDH.MEM.PAGE.ADD] by VMM or TDCALL  
[TDG.MEM.PAGE. ACCEPT]  by TDVF with S -bit clear in page table  
2) Shared Memory  - SEAMCALL [ TDH.MEM.PAGE.ADD] by VMM or TDCALL  
[TDG.MEM.PAGE. ACCEPT]  by TDVF with S -bit set in page table  
3) Unaccepted  Memory  - SEAMCALL [ TDH.MEM.PAGE.AUG] by VMM and not 
accepted by TDVF yet  
4) Memory -Mapped I/O  (MMIO)  – Shared memory accessed by TDVF via 
TDCALL [TDG.VP.VMCALL] <#VE.RequestMMIO > 
The private memory type should be used by default.  
Unaccepted memory is a special type of private memory. The TDVF must invoke 
TDCALL  [TDG.MEM.PAGE. ACCEPT]  the unaccepted memory before use it.  
The shared memory can be converted from private memory. It is used for information 
pass from VMM or for IO buffer including Direct Memory Access (DMA). It must not be 
used for page table or executable. The private page is the default memory type in a 
TD fo r confidentiality and integrity. It must NOT be used for IO buffer.  
The MMIO is a special shared memory. It can only be accessed via TDCALL 
[TDG.VP.VMCALL] <#VE.RequestMMIO >. It cannot be accessed via direct memory 
read or write.  
7.1.1  Private Memory Indicator in Guest Page Table.  
The guest indicate s if a page is shared using the Guest Physical Address (GPA) Shared 
(S) bit. If the GPA Width (GPAW) is 48, the S -bit is bit -47. If the GPAW is 52, the S -bit 
is bit-51. 
7.2 Initial State from VMM  
The memory map information is passed from VMM to TDVF, via resource description 
Hob. The following figure shows a sample memory layout.  TD Memory Management   
 
Figure 7-1:  TD Hob and Initial Memory Layout  
The VMM shall copy the BFV and CFV from the TDVF binary image, then fill TD_HOB to 
describe the memory layout  if the TD_HOB is present in the TD metadata . If the 
TD_HOB is input from the VMM, t he TD_HOB  shall be measured by TDVF as the 
evidence of the initial TD memory configuration  at the TD launch time.  
7.2.1  Memory Type in TD Resource HOB  
There are different types of memory in TD Hob, described in Table 7-1. 
Table 7-1:  Memory Type in TD Resource HOB  
 
Memory 
Type  Report from VMM  VMM Action  TDVF Action  
Private 
Memory  Optional, because TDVF can get the information 
from TD metadata directly.  
 
If it is reported, below format should be used  
TD Hob - Resource Hob  
Type: EFI_RESOURCE_SYSTEM_MEMORY  
Attributes: EFI_RESOURCE_ATTRIBUTE_PRESENT | 
EFI_RESOURCE_ATTRIBUTE_INITIALIZED  | 
EFI_RESOURCE_ATTRIBUTE_ TESTED | 
EFI_RESOURCE_ATTRIBUTE_ENCRYPTED  SEAMCALL 
[TDH.MEM.PAG
E.ADD]  N/A 
Use directly  
 
Unaccepted 
Memory  TD Hob - Resource Hob  
Type: EFI_RESOURCE_MEMORY _UNACCEPTED  
Attributes: EFI_RESOURCE_ATTRIBUTE_PRESENT |  
EFI_RESOURCE_ATTRIBUTE_ TESTED  SEAMCALL 
E.AUG]  TDCALL  
[TDG.MEM.PAGE. ACCE
PT] 
Memory -
Mapped I/O  
(MMIO)  TD Hob - Resource Hob  
Type: EFI_RESOURCE_MEMORY_MAPPED_IO  
Attribute: EFI_RESOURCE_ATTRIBUTE_PRESENT |  
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE  N/A Use directly via 
TDCALL 
[TDG.VP.VMCALL] 
<#VE.RequestMMIO > 
 
The TDVF may indicate a small chunk of temporary initialized memory (added by 
SEAMCALL [ TDH.MEM.PAGE.ADD] ) for temporary usage before the TDVF accepts the 
unaccepted memory (added by SEAMCALL [ TDH.MEM.PAGE.AUG] ). The temporary 
initialize memory size can be small to support initial TDVF code finishing the memory 
initialization.  
Any physical memory  reported in TD Hob should be ACCEPTED by TDVF , except the 
Temporary memory and TD HOB region s, which are declared in the TD metadata.  
TDVF must consult the TD metadata to not accept any ADDED memory region, such 
as BFV, CFV, TD Hob,  and Temporary memory.  TDVF must only accept the unaccepted 
memory reported by VMM.  The summary of the TDVF memory state from VMM is 
shown in Table 7 -2. 
Table 7-2:  TDVF memory state from VMM   
 
Component  Provider  Data  Report  VMM Action  TDVF Action  Measurement  
Static 
Firmware 
Code  (BFV, 
Page table)  TDVF 
(Tenant)  Initialized  From TD 
Metadata  SEAMCALL 
[TDH.MEM.PAGE.
ADD]  
 
SEAM CALL 
[TDH.MR. EXTEN
D] 
 
SEAMCALL 
[TDH.MR. FINALI
ZE] (called after 
all SEAMCALL 
ADD] ) N/A MRTD  
Static 
Firmware 
Configuration 
(CFV, UEFI 
variable)  TDVF 
ADD]  TDCALL 
[TDG.MR.RTMR.
EXTEND ] RTMR[0]  
Dynamic 
Runtime 
(TD Hob)  VMM 
(CSP)  Initialized  From TD 
EXTEND ] RTMR[0]  TD Memory Management   
 
Temporary 
Initialized TD 
Memory  VMM 
(CSP)  0 From TD 
ADD]  N/A N/A 
TD Memory  VMM 
(CSP)  0 TD Hob - 
Resource 
Hob SEAMCALL 
AUG] TDCALL  
[TDG.MEM.PAG

Static 
Firmware 
Code  (BFV, 
ADD]  
 
SEAM CALL 
D] 
 
SEAMCALL 
Static 
Firmware 
(CFV, UEFI 
Dynamic 
Runtime 
 
Temporary 
Memory  VMM 
Resource 
E.ACCEPT]  N/A 
MMIO  VMM 
(CSP)  Initialized  TD Hob - 
Resource 
Hob N/A N/A N/A 
Disk TD Guest 
(Tenant)  Not loaded  N/A Virtual Disk 
Access  TDCALL 
EXTEND ] for the 
content in the 
disk, but not 
the full disk.  RTMR[1] for 
OS loader , 
kernel , initrd, 
boot 
parameter.  
 
NOTE:  
RTMR[2] is 
reserved for 
OS application 
by OS kernel.  
 
RTMR[3] is 
reserved only 
for special 
usage.  
7.3 Memory Information for DXE Core  
The initial TDVF code need s to build a DXE HOB based on the TD HOB to pass the 
memory information to DXE Core. Figure 7-2 shows the DXE HOB and Runtime 
Memory Layout . 
The flow of DXE HOB creation is below:  
1) TDVF only uses the temporary initialized memory for temporary stack and 
temporary heap.  
2) TDVF scans the TD HOB to get the memory layout information.  
3) TDVF initializes permanent memory (by calling TDCALL  
[TDG.MEM.PAGE. ACCEPT] ) from the top of the usable memory below 4GiB. 
The size of initial permanent memory can be small to support initial DXE core 
finishing the initialization and running memory test for the rest of permanent 
memory.  
4) TDVF sets up heap from the top of the usable memory below 4GiB. The page 
table, stack, or DXE Core memory can be allocated there.   
 
5) TDVF constructs the DXE_HOB in the permanent memory.  
a. The PHIT points to the location in the permanent memory.  
b. The FV Hob is created based upon TD Metadata. (See chapter 11)  
c. The CPU Hob is created based upon memory GPAW bit (48 or 52  
SizeOfMemorySpace ) and IO resource reporting (0 or 16 
SizeOfIoSpace ) 
d. The Resource Hob is created based upon the memory initialization 
state. The TDVF may optionally allocate shared memory. If this is the 
case, the shared memory should be reported as a stand -alone  HOB 
entry without EFI_RESOURCE_ATTRIBUTE_ENCRYPTED . (See below section)  
e. The Memory Allocation Hob is created to describe the allocated 
memory in heap, such as permanent page table, stack, or DxeCore 
module.  
6) The TDVF reclaims the temporary memory.  
7) The TDVF handles the MMIO reported by TD HOB.  
a. If the MMIO region is for fixed resource such as APIC and HPET, the 
MMIO region should be reported in the DXE HOB.  
b. If the MMIO region is for dynamic resource allocation and will be 
managed by a dedicated DXE driver, then the MMIO region might not 
be reported in the DXE HOB. (Such as for an MMIO space for PCI 
MMIO BAR allocation by the PCI host bridge driver.) If the MMIO 
region is reported, then the HOB resource attribute 
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE  must be used, because PCI host 
bridge driver will try to add this region with GCD attribute 
EFI_MEMORY_UC .  
8) The TDVF handles the Port IO reported by TD HOB.  
a. If the port IO region is for fixed resource such as 8254 and 8259, the 
port IO region should be reported in the DXE HOB.  
b. If the port IO region is for dynamic resource allocation and will be 
managed by a dedicated DXE driver, then IO region might not be 
reported in the DXE HOB. (For example, for an IO space for PCI IO 
BAR allocation by the PCI host bridge driver.)  
 TD Memory Management   
 
Figure 7-2:  DXE HOB and Runtime Memory Layout  
7.3.1  Memory Type in DXE Resource HOB  
There are different types of memory in DXE Hob. See table 7 -3. 
Table 7-3:  Memory Type in DXE resource HOB  
Memory 
Type  Report from TDVF initial code  VMM/TDVF initial 
code Action  TDVF Action  
Private 
Memory  DXE Hob - Resource Hob  
ADD] / TDCALL  
[TDG.MEM.PAGE.
ACCEPT]  Use directly  
Shared 
Memory 
(optional)  DXE Hob - Resource Hob  
EFI_RESOURCE_ATTRIBUTE_ TESTED SEAMCALL 
 
EFI_RESOURCE_ATTRIBUTE_ TEST SEAMCALL 
AUG]  TDCALL  
PT] 
Memory -
Mapped I/O  
(MMIO)  DXE Hob - Resource Hob  
TDCALL 
 
7.4 Memory Map to TD -OS 
If a memory region is private memory, the final UEFI memory map shall report the 
region with normal UEFI memory type.  
If a memory region is shared memory, the final UEFI memory map shall report the 
region with normal UEFI memory type.  It is converted by the IOMMU driver to private 
memory automatically at ExitBootServices  event.  
If a memory region is unaccepted memory and requires TDCALL  
[TDG.MEM.PAGE. ACCEPT] in the TD guest OS, then the final UEFI memory map shall 
report this region in EfiUnaccepted MemoryType . The OS need TDCALL  
[TDG.MEM.PAGE. ACCEPT]  before use it.  
If a memory region is MMIO, it can only be accessed via TDCALL [TDG.VP.VMCALL] 
<#VE.RequestMMIO >. It cannot be accessed via direct memory read or write. There is 
no need to report this region in UEFI memory map because no RUNTIME attribute is 
required. The full MMIO regions should be reported in ACPI ASL code via memory 
resource descriptors.  
For non-UEFI system, the memory map is reported via E820 table . The private 
memory is reported as normal E820 memory type. The unaccepted memory is 
reported as AddressRangeUnaccepted  type. 
The TDVF need report the memory map information to OS. Please refer to the TDX 
Guest Hypervisor Communication Interface document for the detailed information.  
7.5 Convert Shared to Private  
The TDVF need convert shared memory to private memory in late memory 
initialization or to reclaim virtual device IO buffer or hypervisor communication buffer.  
The TDVF must take the following steps  to convert shared memory to private 
memory:  
• Guest removes  GPA from shared space. Clear S -bit in page table.  
• TDCALL [TDG.VP.VMCALL] <MAPGPA>  
• TDCALL  [TDG.MEM.PAGE. ACCEPT]  TD Memory Management   
 
This step can be done by an IOMMU protocol FreePages()/Unmap()  if this is for the 
virtual device IO buffer.  
The IOMMU protocol definition can be found at 
https://github.com/tianocore/edk2/blob/master/MdeModulePkg/Include/Protocol/IoM
mu.h 
7.6 Convert Private to Shared  
The TDVF needs to convert private memory to shared memory for hypervisor 
communication such as TDCALL [TDG.VP.VMCALL] or virtual device IO buffer.  
The TDVF should  take the following steps  to convert shared memory to private 
memory:  
• Guest adds GPA to the shared space. Set S -bit in page table.  
This step can be done by an IOMMU protocol AllocatePages()/Map()  if this is for the 
7.7 Memory State Transition  
Please see the figure below for the TDVF memory statue transition.  
 
Figure 7-3:  TDVF Memory State Transition  
 
7.8 Optimization Consideration  
The TDVF implementation may add all physical pages to private memory before 
transfer control to OS. This may increase the boot time, because the TDCALL  
[TDG.MEM.PAGE. ACCEPT ] is time -consuming. As such, the TDVF may choose to add 
part of memory to be private memory and boot to OS. Then the TD -OS can convert 
the rest page to be private. The TDVF may do below optimization.  
7.8.1  Partial Memory Initialization in Pre -UEFI  
 
When the TDVF MemoryInit module initializes the memory - convert all memory to be 
accepted private memory, the MemoryInit module need mark the resource description 
HOB to be  EFI_RESOURCE_SYSTEM_MEMORY with 
(EFI_RESOURCE_ATTRIBUTE_ PRESENT | 
EFI_RESOURCE_ATTRIBUTE_INITIALIZED  |  
EFI_RESOURCE_ATTRIBUTE_ TESTED). 
 
There is no need to initialize all system memory in the early phase, where it is the 
single thread environment. The MemoryInit module just need initialize enough 
memory to launch the DXE Core. The MemoryInit module need split the resource 
description HOB i nto 2 parts: the initialized private or shared memory 
EFI_RESOURCE_SYSTEM_MEMORY with (EFI_RESOURCE_ATTRIBUTE_ PRESENT | 
EFI_RESOURCE_ATTRIBUTE_ TESTED) and the unaccepted memory 
EFI_RESOURCE_MEMORY_UNACCEPTED  with (EFI_RESOURCE_ATTRIBUTE_ PRESENT | 
EFI_RESOURCE_ATTRIBUTE_ TESTED).

For example, the MemoryInit may just need to initialize 256M memory for DXE core , 
even if there are 4G memory available.  
7.8.2  Partial Memory Initialization in UEFI  
Once the DXE Core is launched, it checks the resource description HOB and only uses 
the memory EFI_RESOURCE_SYSTEM_MEMORY  with 
EFI_RESOURCE_ATTRIBUTE_ TESTED). A MemoryTest module must go through 
the resource description HOB and do the late -initialization in DXE phase for the 
unaccepted memory EFI_RESOURCE_MEMORY_UNACCEPTED  with 
After the late initialization, the GCD type of the memory is converted from 
EfiGcdMemoryTypeUnaccepted  to EfiGcdMemoryTypeSystemMemory  
The MemoryTest module just needs to initialize enough accepted private memory for 
the UEFI environment , and launch the OS loader. The accepted private memory is TD Memory Management   
 
reported as normal memory type. The unaccepted memory is reported as 
EfiUnaccepted MemoryType . This allows OS to do late initialization.  
 
For example, the UEFI environment may only need to initialize 4G memory for the OS 
loader if there is 256G memory available.  
7.8.3  Parallelized Memory Initialization  
The MemoryTest module is executed in the multi -processor environment.  
The MemoryTest module may consider using multi -processor to parallelize the 
memory initialization process. The BSP may split the task and wake up all APs and let 
multiple APs do the memory initialization.  
For example, if a system has 16 CPUs and 8G memory to be initialized, the BSP may 
wake up 15 APs to let each CPU initialize 512M memory.  
7.8.4  Pre-allocating Virtual Device IO Buffer  
The TDVF may use virtual device IO buffer in the deriver driver to support system 
boot, such as virt -io, file system driver. Because the virtual device IO buffer is shared 
memory, there is risk of thrashing which means the excessive swapping between 
shared  memory and private memory.  
To avoid such thrashing, the IOMMU driver may pre -allocate a big chunk of shared 
memory as the virtual device IO buffer in the driver entrypoint, and only convert it 
back to private in the ExitBootServices  event. The other virtual device IO buffer 
allocation should be inside of the pre -allocated IO buffer. As such, the overhead of the 
virtual device IO buffer converting can be reduced.  
 
§  
 TD Measurement  
 
8 TD Measurement  
This chapter describes  the measurement/attestation/quote.  
 
8.1 Measurement Register Usage in TD  
• TD measurement register ( MRTD ): Static measurement of the TD build 
process and the initial contents of the TD.  
• Runtime Extendable measurement register ( RTMR ): An array of general -
purpose measurement registers, available to the TD software for measuring 
additional logic and data loaded into the TD at runtime.  
 
A system has 1 MRTD  and 4 RTMR. The typical usage is shown below:  
• MRTD  is for the TDVF code (match PCR[0]).  
• RTMR[0] is for the TDVF configuration (match PCR[1,7]).  The usage should follow 
TCG P latform Firmware Profile (P FP) specification.  
• RTMR[1] is for the TD VF loaded component, such as  OS loader (match PCR[4,5]).  
The usage should follow TCG Platform Firmware Profile (PFP) specification.  
• RTMR[2] is for the OS component, such as OS kernel, initrd, and application 
(match PCR[8~15]).  The usage is OS dependent.  
• RTMR[3] is reserved for special usage only.  
 
Table 8 -1 shows how to match the PCR used in the regular platform to the TD 
Measurement Register used in TDVF.  
Table 8-1:  TD Measurement -related  Register  
 
PCR 
Index  Typical  Usage  TD 
Register  TD 
Reg 
Index  Event 
Log Exte nded by  Checked  
by Content  
0 Firmware 
Code  (BFV, 
including init 
page table)  MRTD  0 NO VMM: TDCALL 
[TDH.MR. EXTEND ] Remote  VF cod e (BFV)  
1 Firmware 
Data  
(CFV, TD Hob, 
ACPI Table)  RTMR 
[0] 1 YES TDVF : TDCALL  
[TDG.MR.RTMR. E
XTEND ] Remote  Static Configuration 
(CFV),  
Dynamic Configuration 
(TD HOB, ACPI)  TD Measurement   
 
2 Option ROM 
code  RTMR  
[1] 2 YES TDVF : TDCALL  
XTEND ] Remote  PCI Option ROM, such as 
NIC. 
3 Option ROM  
data  RTMR  
XTEND ] Remote   
4 OS loader 
code  RTMR  
XTEND ] Remote  OS lo ader  
5 Configuration 
(GPT, Boot 
Variable)  RTMR  
XTEND ] Remote  GPT, Boot Variable, Boot 
Parameter.  
6 N/A N/A  N/A N/A N/A  
7 Secure Boot 
Configuration  RTMR 
XTEND ] Remote  Secure BootConfig (in 
CFV)  
8~15  TD OS 
measurement  RTMR 
[2] 3 - TD OS Loader  or 
TD OS : TDCALL  
XTEND ] - OS kernel, initrd, boot 
parameter  -  done by TD 
OS loader . 
OS Application – done 
by TD OS. 
 
8.2 Fundamental Support  
Intel TDX module  shall measure TD BFV and extend to MRTD . MRTD  can be used for 
attestation purpose. (Similar to the trust boot flow)  
During runtime, TDVF shall measure TD CFV and TD Hob to RTMR[0] and the OS 
code/data and extend to RTMR[1] . This action is done via TDCALL  
[TDG.MR.RTMR. EXTEND ] that allows dynamic measurement extensions (Dynamic 
data).  RTMR can be used for attestation purpose. (Similar to the trust boot flow)  
  
Figure 8-1:  TDVF Measurement  
 
Please  see the Intel® TDX Guest -Hypervisor Communication Interface  document for 
the detailed data structure.  
The TDVF should expose EFI_CC_MEASURMENT_PROTOCOL and CCEL ACPI table.  The 
original EFI_TCG2_PROTOCOL and TPM2 ACPI table should be used for virtual TPM  
only. See figure 8 -2. 
 
TD Measurement   
 
Figure 8-2:  TDVF Measurement  Interface  
 
8.3 Virtual Firmware Configuration  
The TDVF may support to consume different configuration data as the policy to control 
the code flow. Care must be taken that this is an attack surface, because the VMM is 
not trusted. Please use the following guidance:  
• The TDVF should reduce configuration  options to reduce the attack surface.  
• Configuration data must be copied to private memory, measured , and verified 
before it is used.  
8.3.1  Build -Time Configuration  
The Build -Time configuration is the configuration firmware volume (CFV). It may 
include UEFI Secure Boot variables (PK, KEK, db, dbx).  
The data will be exposed as UEFI variable.  
 
8.3.2  Launch -Time Configuration  
The Launch -Time configuration is the TD HOB passed from VMM. This hob may include 
the system configuration, such as the memory range, MMIO range, IO range, CPU 
number, etc.  
The hypervisor vendor may add GUIDed Hob as the extension to provide hypervisor -
specific information to the hypervisor -specific TDVF, such as ACPI tables and SMBIOS 
tables.  
The data included in TD HOB must be accessible during the whole firmware boot time.  
8.3.3  Runtime Configuration  
Runtime configuration uses non -volatile UEFI variable data.  
In order to simplify the design, TDVF does not support non -volatile variables.  
If TDVF requires support for non -volatile variables in the future, the variable area 
must be measured into RTMR [0]. 
8.3.4  Hypervisor Specific Configuration Interface  
 
Currently, some virtual firmware may use hypervisor -specific  configuration interface to 
get the configuration information.  
  
For example, OVMF uses FW_CFG_IO_SELECTOR (0x510)  and FW_CFG_IO_DATA  
(0x511) to get configuration information from QEMU. Example information:  
• “etc/system -states ” 
• "etc/table -loader"  
• "etc/extra -pci-roots"  
• "bootorder"  
• "etc/boot -menu -wait" 
• "etc/tpm/config"  
• "etc/edk2/https/cacerts"  
• "etc/msr_feature_control"  
• "etc/e820"  
• "opt/ovmf/X -PciMmio64Mb"  
• "etc/reserved -memory -end" 
• "etc/ramfb"  
• "etc/smbios/smbios -tables"  
• "etc/smi/supported -features"  
• "etc/smi/requested -features"  
• "etc/smi/features -ok" 
 
If TDVF uses this method, configuration data must be measured into RTMR[0].  
8.4 Attestation and Quote Support  
 
Figure 8-3:  Attestation and Quote  
1. Guest TD invokes TDCALL  [TDG.MR. REPORT ] API function . 
 
2. Intel TDX module  uses the SEAMOPS [ SEAMREPORT ] instruction to create a MAC 
TDREPORT _STRUCT  with the Intel TDX module  measurements from CPU and TD 
measurements from TDCS . 
3. Guest TD uses TDCALL [TDG.VP.VMCALL] <GetQuote > to request 
TDREPORT _STRUCT  be converted into Quote.  
4. The TD Quoting enclave uses ENCLU[EVERIFYREPORT 2] to verify the 
TDREPORT _STRUCT .  This allows the Quoting Enclave to verify the report without

TDREPORT _STRUCT .  This allows the Quoting Enclave to verify the report without 
requiring direct access to the CPU’s HMAC key.  Once the integrity of the 
TDREPORT _STRUCT  has been verified, the TD Quoting Enclave signs the 
TDREPORT _STRCUT  body with an ECDSA 384 signing key.  
5. The Quote can then be used by TD software to perform a remote -attestation 
protocol with a verifying -remote party.  
 
§  
 TDVF Device Support  
 
9 TDVF Device Support  
TDVF device driver support must align with the TD -VMM capability. Microsoft Windows 
Hyper -V may require Vmbus. Linux KVM may require VirtIo.  
9.1 Minimal Requirement  
The following devices are enabled for a typical guest OS:  
1) Debug Device (Serial Port)  
2) Storage Device (Block device or SCSI)  
3) Output Device (Graphic)  
4) Input Device (Keyboard)  
5) Network Device (LAN)  
For a container use case, a simplified TDVF may jump directly to the OS kernel 
without enabling any devices.  
9.2 VirtIo Requirement  
VirtIo requires the following:  
• virtio-pci (Enumeration over PCI)  
• virtio-serial (serial output / debug)  
• virtio-blk and/or virtio -scsi (Storage)  
• virtio-gpu (Graphics)  
• virtio-input (Keyboard)  
• virtio-net and/or virtio -socket (Network)  
9.3 Security Device  
Support for virtio-rng is not required because the VMM is not trusted . TD must use the 
RDSEED or RDRAND instruction to obtain a random number . 
 TDVF Device Support   
 
9.4 HotPlug Device  
The current TD X does not support CPU Hot Plug  feature. As such, the TDVF does not 
support CPU Hot Plug . Memory Hot Plug can be supported by TDX architecture . The 
TDVF does not support the memory hot plug and only reports the memory map from 
VMM at TD launch time , including accepted memory and unaccepted memory . The TD 
OS may support memory hot plug  at runtime as an optional feature . 
1) CPU Hot Add – This is blocked by Intel TDX module . Intel TDX module  injects 
all VCPU into the guest TD  at one time . The MADT ACPI table holds and only 
holds the active CPUs reported by the Intel TDX module . 
2) CPU Hot Remove – It can be use d as a denial -of-service attack from the VMM. 
This feature is out of scope for TDX.  
3) Memory Hot Add – VMM must use the standard defined process (such as ACPI) 
to notify the hot add event to TD OS. Otherwise, TD OS should ignore memory 
configuration changes.  
4) Memory Hot Remove – VMM must use the standard defined process (such as 
ACPI) to notify the hot remove event to TD OS. Surprise removing  can be 
used as a denial -of-service attack from the VMM. This feature is out of scope 
for TDX.  
Although TDVF does not support Hot Plug , a VMM may report an ACPI table with Hot 
Plug support to access the guest OS. In order to mitigate this, any input from the VMM 
must be measured by OVMF into RMTD for attestation. Note that TDVF cannot verify 
ACPI table content. The guest OS should treat ACPI input as untrusted data and parse 
it care fully. 
9.5 PCI Device Option ROM  
UEFI x64 PCI Option ROMs (OROM) are supported. Before execution, the OROM must 
be measured into RTMR . Because UEFI Secure Boot is enabled, the PCI OROM must be 
signed with valid certificate against info enrolled into UEFI Secure Boot variables.  
Legacy 16bit OROM and 32-bit UEFI OROM must be rejected and ignored.  
§  
 Exception Handling  
 
10 Exception Handling  
This chapter describes exceptions that may be injected by Intel TDX module . 
10.1  Virtualization Exception (#VE)  
The TDVF provides the default #VE exception handler . The handler is implementation -
specific , like all other exception handlers.  
The default handler may:  
• Dump the exception reason via TDCALL  [TDG.VP.VEINFO .GET] and the 
architecture state, including general -purpose  registers, in debug mode for 
root-cause analysis  
• Dead loop  
Care must be taken that the debug output must NOT violate TDX restrictions. For 
example, IO port access is illegal in TD , so the Serial IO  debug output must be 
modified with TDCALL [TDG.VP.VMCALL] <INSTRUCTION .IO>.  
10.2  Instruction Conversion  
The VE exception handler may also convert some of the forbidden instruction to the 
TDCALL [TDG.VP.VMCALL] <INSTRUCTION >. For example:  
CPUID => TDCALL [TDG.VP.VMCALL] <Instruction .CPUID>  
IO => TDCALL [TDG.VP.VMCALL] <Instruction .IO> 
MMIO => TDCALL [TDG.VP.VMCALL] < #VE.RequestMMIO >RDMSR => TDCALL 
[TDG.VP.VMCALL] <Instruction .RDM SR> 
WRMSR => TDCALL [TDG.VP.VMCALL] <Instruction .WRMSR> 
Care must be taken that when the #VE handler should not use 
TDCALL[ TDG.VP.VMCALL ]<#VE.RequestMMIO>  to access any private memory  caused 
by the EPT violation . Please refer to Chapter 2 Security Consideration.  
 
§ TDVF Metadata   
 
11 TDVF Metadata  
This section describes TDVF Metadata. This metadata provides information to the VMM 
that is used to build a TD.  
11.1  TDVF Metadata Location  
The metadata is located at (TDVF end – 0x20) byte. It is a 4 -bytes offset of the 
TDVF_DESCRIPTOR to the beginning of the TDVF image.  
 
Figure 11-1:  TDVF Metadata Layout  
 
11.2  TDVF descriptor  
The VMM refers to TDVF_DESCRIPTOR to set up  memory for TDVF.  
 
 TDVF Metadata  
 
Table 11-1:  TDVF_DESCRIPTOR definition  
 
(Byte)  Type  Size 
(Byte)  Description  
Signature  0 CHAR8[4]  4 “TDVF”  
Length  4 UINT32  4 Size of the structure  (d) 
Version  8 UINT32  4 Version of the structure. 
It must be 1.  
NumberOfSection
Entry  12 UINT32  4 Number of the section 
entry (n)  
SectionEntries  16 TDVF_SECTION[n]  32*n  See table 13 -2. 
Table 11-2:  TDVF_SECTION definition  
 
DataOffset  0 UINT32  4 The offset to the raw section in the 
binary image.  
RawDataSize  4 UINT32  4 The size of the raw section in the 
image.  
 
If it is zero, the VMM shall allocate 
zero memory from MemoryAddress 
to (MemoryAddress + 
MemoryDataSize).  
 
If it is zero, then the DataOffset shall 
also be zero.  
MemoryAddress  8 UINT64  8 The guest physical address of the 
section loaded.  
It must be 4K aligned.  
 
Zero  means  no action  for the VMM . 
MemoryDataSize  16 UINT64  8 The size of the section loaded.  
It must be not less  than RawDataSize , 
if it is non -zero . 
 
If MemoryDataSize is greater than 
RawDataSize, the VMM shall fill zero 
up to the MemoryDataSize.  
 
Zero  means  no action  for the VMM . TDVF Metadata   
 
Type  24 UINT32  4 The type of the TDVF_SECTION.  See 
table 13 -3. 
Attributes  28 UINT32  4 The attribute of the section. See table 
13-4. 
 
Table 11-3:  TDVF_DESCTION. Type definition  
Value  Name  Memory 
Type  VMM Action  Td-Shim Action  Measurement  
0 BFV/TdShim  Private 
Memory  PAGE.ADD +  
MR.EXTEND  N/A MRTD  
1 CFV Private 
Memory  PAGE.ADD  RTMR.EXTEND  RTMR[0]  
2 TD_HOB  Private 
3 TempMem  Private 
Memory  PAGE.ADD  N/A N/A 
4 PermMem  Unaccepted 
Memory  PAGE.AUG  PAGE.ACCEPT  N/A 
5 Payload  Private 
MR.EXTEND*  RTMR.EXTEND*  MRTD (or)  
RTMR[1]  
6 Payload Param  Private 
Memory  PAGE.ADD  RTMR.EXTEND  RTMR[1]  
7 TD_INFO  Private 
Memory  N/A N/A N/A 
8 ~ 
0xFFFFFFFF  Reserved  N/A N/A N/A N/A 
 
Table  11-4:  TDVF_DESCTION.Attributes definition   
Bits Name  Description  
0 MR.EXTEND  If the VMM need use TDCALL [ TDH.MR. EXTEND ] for this section.  
0: Do not n eed TDCALL [ TDH.MR. EXTEND ] 
1: Need TDCALL [ TDH.MR. EXTEND ] 
 
For example, TDVF BFV sets to 1 . TDVF CFV/TD_HOB/TempMem  
/PermMem  set to 0.  The Payload  sets 1 or 0. The Payload Param 
sets to 0.  
1 PAGE.AUG  If the VMM need use TDCALL [TDH.MEM.PAGE.AUG] for this 
section.  
0: Use TDCALL [TDH.MEM.PAGE.ADD]  
1: Use TDCALL [TDH.MEM.PAGE.AUG]  
  
For example, PermMem sets be 1. Others set to 0.  
31:2 Reserved  Must be 0.  
Rules for the TDVF_SECTION:  
• A TDVF shall include at least one BFV section and the reset vector shall be 
inside of BFV. The RawDataSize of BFV must be non -zero. 
• A TDVF may have zero, one or multiple CFV  section s. The RawDataSize of CFV 
must be non-zero. 
• A TDVF may have zero or  one TD_HOB section.  The RawDataSize of TD_HOB 
must be zero.  If TDVF reports zero TD_HOB section, then TD VF shall report all 
required memory in PermMem section.  
• A TDVF may have zero , one or multiple  TempMem  section s. The RawDataSize 
of TempMem must be zero.  
• A TD-Shim may have zero, one or multiple PermMem section s. The 
RawDataSize of PermMem must be zero. If a TD provides PermMem section, 
that means the TD will own the memory allocation. VMM shall allocate the 
permanent memory for this TD. TD will NOT use the system memory 
information in the TD HOB. Even if VMM adds system memory information in 
the TD HOB, it will be ignored.

the TD HOB, it will be ignored.  
• A TD-Shim may have zero or one Payload . The RawDataSize of Payload must 
be non -zero, if the whole image includes the Payload . Otherwise the 
RawDataSize must be zero.  
• A TD-Shim may have zero or one Payload Param . Payload Param is present only 
if the Payload is present.  
• A TDVF may have zero or one TD_INFO  section. If present, it shall be included 
in BFV section.  MemoryAddress and MemoryDataSize shall be zero.  
The metadata above may support below use cases as example : 
• Normal TDVF: The metadata includes one BFV, one CFV, one TD_HOB and 
multiple TempMem.  
• TD-Shim with container OS: The metadata includes one BFV, one TD_HOB, 
multiple TempMem and one OS kernel as Payload. The OS kernel is added so 
that the TD -Shim does not need load it from other storage.  
• TD-Shim with Service TD core: The metadata includes one BFV, zero or one 
CFV, multiple TempMem, one PermMem, and one Service TD Core as Payload. 
The TD_HOB is removed and the PermMem is added, so that the configuration 
is static, and all measurement regist ers are predictable at build time.  
Table 11-5:  TD_ INFO  definition  
(Byte)  Type  Size (Byte)  Description  
GUID  0 GUID  16 The GUID for the TDVF.  TDVF Metadata   
 
Length  16 UINT32  4 Length of the full structure, including 
the GUID.  
Version  20 UINT32  4 The version of the TDVF . 0 means 
unsupported.  
SVN 24 UINT 32 4 The Security Version Number of TDVF . 
It must be Monotonically increasing . 0 
means unsupported.  
Data  28   GUID specific data.  
 
§ 
  
 OS Direct Boot  
 
12 OS Direct Boot  
This section describes OS Direct Boot that may be implemented in TDVF.  
The default TDVF implementation boots to an OS loader, which in turn loads the OS 
kernel. As implementation option, TDVF may implement an OS loader that directly 
boots the OS kernel.  
For specialized workloads like functions or containers, the underlying guest OS is both 
simplified and customized. In these cases , a bootloader or general -purpose  firmware 
is needed, so the VMM can directly boot to the guest kernel entry point. With TDX, the 
VMM does not choose the guest entry point and must offload the guest direct kernel 
boot to a TD firmware shim.  
For more information on Linux Direct Boot using efi -stub, please refer to the following 
documentation: https://github.com/torvalds/linux/blob/master/Documentation/admin -
guide/efi -stub.rst  
12.1  Measurement  
In OS direct boot use case, the OS kern el and kernel required data (such as initrd and 
boot parameter) must be loaded into private memory and measured into runtime 
measurement register.  
For example, if the TDVF loads the UEFI Linux kernel (bzImage) and initrd (initrd.img) 
with kernel boot parameter console=ttyS0 root=/dev/sda4 , then TDVF needs to 
measure the following in RTMR[1]:  
• UEFI Linux kernel  
Then efi-stub in the Linux kernel needs to measure the following into RTMR[2]:  
• initrd 
• console=ttyS0 root=/dev/sda4  
Table 12-1:  OS loader measurement  
 
Data  Register  Event 
Log Exte nded by Checked  by 
OS kernel  RTMR  [1] YES TDVF : TDCALL  
[TDG.MR.RTMR. EXTEND ] Remote  
initrd  RTMR  [2] YES efi-stub : TDCALL  
Boot Parameter  RTMR  [2] YES efi-stub : TDCALL  
OS application  RTMR [2]  - TDOS: TDCALL  
[TDG.MR.RTMR. EXTEND ] Remote  OS Direct Boot   
 
12.2  UEFI Kern el Image Hash Ca lculation  
When a UEFI kernel image is used, the QEMU will parse the kernel image and patch 
the kernel setup area . See 
https://github.com/qemu/qemu/blob/master/hw/i386/x86.c#L791 , x86_load_linux() 
function.  
• Offset 0x210 ( uint8_t ): change to 0xB0 ( setup.loadflags  is changed to qemu 
bootloader id ) 
• Offset 0x211 ( uint8_t ): change to 0x81 ( setup.loadflags is changed from 0x01 
to 0x81 ) 
• Offset 0x224 ( uint16_t ): change to 0x fe00 (setup.heap_end_ptr is changed  
from 0x4f40 to 0xfe00 ) 
• Offset 0x2 28 (uint32_t ): change to 0x 20000  (setup.cmd_line_ptr is changed 
to 0x200000 ) 
A verifier should perform  the same patch for the kernel image , before calculating the 
kernel image hash based on PE Auth enticode in Microsoft PE/COFF specification . 
 
§  
 Minimal TDVF (TD -Shim) Requirements  
 
13 Minimal TDVF (TD -Shim) 
Requirements  
This section describes requirements for a minimal TDVF implementation (TD -Shim).  
In a TD container solution, the VMM loads almost everything into memory before TD 
launch. This means TDVF can perform minimal initialization and jump directly to the 
Linux Kernel without a full UEFI implementation.  
For more information on Linux Boot Protocol and Linux Boot Parameter, please refer to 
the following documentation:  
• https://www.kernel.org/doc/Documentation/x86/boot.txt  
• https://www.kernel.org/doc/Documentation/x86/zero -page.txt  
13.1  Hardware Virtualization -based Containers  
Hardware virtualization -based containers are designed to launch and run containerized 
applications in hardware virtualized environments. While containers usually run 
directly as bare -metal applications, using TD or VT as an isolation layer from the host 
OS is used as a secure and efficient way of building multi -tenant Cloud -native 
infrastructures (e.g. Kubernetes).  
In order to match the short start -up time and resource consumption overhead of bare -
metal containers, runtime architectures for TD - and VT-based  containers put a strong 
focus on minimizing boot time . They must also launch the container payload as quickly 
as possible. Hardware virtualization -based containers typically run on top of simplified 
and customized Linux kernels to minimize the overall guest boot time.  
Simplified kernels typically have no UEFI dependencies and, no ACPI  ASL support. This 
allows guests to boot without firmware dependencies. Current VT -based container 
runtimes rely on VMMs that are capable of directly booting into the guest kernel 
without loading firmware.  
13.1.1  TD Container Requirements  
While it is possible to let a VMM drive a VT guest via direct kernel boot, this is not part 
of the TD threat model (which leaves VMM outside of the TCB). The TD initial state is 
not modifiable by the VMM so TD containers, as opposed to VT containers, rely on a 
minimal TD virtual firmware solution (TD -Shim) to launch a TD guest OS.  
13.2  TD-Shim Launch  
The VMM launches TD -Shim in 32 -bit protected mode. The TD -Shim needs to set the 
page tables up and then switch to 64 -bit long mode.  Minimal TDVF (TD -Shim) Requirements   
 
TD-Shim assumes the VMM loads the Linux kernel (bzImage  or vmLinux ) and optional 
initrd (initrd.img) with boot parameter into memory. The VMM passes information to 
the TD -Shim via the TD HOB and/or Linux boot protocol and Linux boot parameter.  
13.2.1  TD-Shim  AP Handling  
The Intel TDX module  initializes all CPUs and allows them to jump to the reset vector 
at the same time. In a full TDVF implementation, the BSP does the TD initialization 
and let s APs do wait -loop. TDVF creates an ACPI table to share mailbox information 
with the OS , and send the OS commands via ACPI mailbox to wakeup APs.  
A TD container cannot assume the guest environment supports ACPI.  This enables 
boot to a guest environment without ACPI ASL support.  
When TD containers support ACPI  static table , then the TD -Shim can generate  MADT 
table and inserts the mailbox information into it.  
13.3  TD-Shim Secure Boot Support  
UEFI Secure Boot is not required for TD -Shim.  
13.4  TD-Shim ACPI Support  
ACPI is optional for TD containers, but a typical VMM will build guest ACPI tables. 
When TD containers support ACPI, those tables may be passed by the initial HOB.  
When TD containers do not support ACPI  ASL, device information may be passed via 
other mechanisms (e.g. kernel command line parameter ). 
13.5  TD-Shim Memory Management  
13.5.1  Memory Type in Initialization  
 
Table 13-1:  TD-Shim memory state from VMM  
 
Memory 
Type  Provider  Data  Report  VMM Action  TDVF Action  Measurement  
Static 
Firmware 
Code  (Shim, 
E.ADD]  
SEAM CALL 
[TDH.MR. EXTE
ND] 
 N/A MRTD   
 
SEAMCALL 
[TDH.MR. FINA
LIZE] (called 
after all 
SEAMCALL 
E.ADD] ) 
Dynamic 
Runtime 
E.ADD]  TDCALL 
XTEND ] RTMR[0]  
 
Temporary 
Memory  VMM 
E.ADD]  N/A N/A 
Resource Hob  SEAMCALL 
ACCEPT]  N/A 
Kernel  TD Guest

Memory 
Static 
Firmware 
E.ADD]  
SEAM CALL 
ND] 
 N/A MRTD   
 
SEAMCALL 
after all 
SEAMCALL 
E.ADD] ) 
Dynamic 
Runtime 
 
Temporary 
Memory  VMM 
Kernel  TD Guest 
(Tenant)  Initialized  TD Hob - 
Resource Hob, 
GUID hob  SEAMCALL 
XTEND ] RTMR[ 1] 
Initrd  TD Guest 
Boot 
Parameter  TD Guest 
13.5.2  Memory Map for OS  
VMM shall pass the initial memory map information via TD HOB. TD -Shim may 
generate E820 table  for the container.  
13.6  TD-Shim Measurement  
13.6.1  TD Measurement  
TD-Shim must extend RTMR before transferring control to the Linux kernel.  
Table 13-2:  TD Measurement -Related  Registers for TD -Shim  
 
PCR Typical  Usage  Register  Event 
by Content  
0 Firmware 
Code  MRTD  NO VMM: SEAM CALL  
[TDH.MR. EXTEND ] Remote  TD-Shim + Initial Page 
Table  Minimal TDVF (TD -Shim) Requirements   
 
1 Firmware 
Data  RTMR 
[0] YES TDVF : TDCALL  
XTEND ] Remote  Static Configuration (CFV), 
(TD HOB)  
code  N/A N/A N/A N/A N/A 
data  N/A N/A N/A N/A N/A 
4 OS loader 
code  RTMR  
[1] YES TDVF : TDCALL  
XTEND ] Remote  OS kernel, initrd.  
5 Boot 
Configuration  RTMR  
[1] YES TDVF : TDCALL 
XTEND ] Remote  Boot Parameter  
6 N/A N/A N/A N/A N/A N/A 
Configuration  N/A N/A N/A N/A N/A 
8~15  TD OS APP 
[2] - TDOS: TDCALL 
XTEND ] - TD OS App. Done by OS.  
13.6.2  CC Event Log  
When TD containers support ACPI  static table , TD-Shim passes the CC event log via 
13.7  TD-Shim Device Support  
No Device Support is required in TD -Shim. TD -Shim will jump to the Linux kernel 
without initializing any device.  
13.8  TD-Shim Exception Handling  
This model assumes TD -Shim does not generate exceptions. Exception handling is not 
required.  
§  
 
 Disk Encryption   
 
14 Disk Encryption  
Today a VM disk image may be encrypted. Before boot, the VMM gets a storage 
volume key to decrypt the VM disk image and pass the decrypted disk content to the 
VM. However, in the TDX the VMM is not trusted. The TD need s to have a way to get 
the storage volume key to decrypt the VM disk image.   
The VM disk image may be decrypted in OS  or may be decrypted in the virtual 
firmware  based upon the use case.  
This section describes the possible  solution s in the virtual firmware.  
14.1  Overview  
There are two agents involved in the disk encryption solution:  
1) Attestation Agent : It will perform attestation , retrieve the storage volume key 
from a remote key server , and pass it to a decryption agent . 
• Preboot a ttestation: The attestation agent is in TDVF  or OS loader . See Figure  
14-1. 
• Early OS boot attestation: The attestation agent is in initrd. See Figure 14 -2. 
• OS runti me attestation: The attestation agent is an OS application.  
2) Decryption Agent : This will get the storage volume key from the attestation 
agent and decrypt the disk.  
The scope of the encrypted disk is use case specific. A common storage volume key 
may be used to decrypt:  
• Full Disk Encryption  (System Partition + Data Partition) : The decryption agent 
may be  in TDVF  or integrated OS loader (grub) . 
• Data Partition Encryption : The decryption agent may be  in TDVF , OS loader 
(grub)  or initrd.  
• Container Image Encryption : The  decryption  agent may be an OS application . 
Table 14 -1 shows these  use cases.  
Table 14-1:  Disk Encryption Use Cases  
Use Case  Preboot 
Attestation  Early OS Boot 
Attestation  OS Runtime 
Attestation  
Full Disk Encryption  Yes No No 
Data Partition Encryption  Yes Yes No 
Container Image Encryption  Yes Yes Yes 
 
 Disk Encryption  
 
Figure 14-1:  Preboot Disk Decryption Flow  
 
Figure 14-2: Early -boot Disk Decryption Flow  
Since TDVF is involved in preboot disk decryption , we list security propert ies for 
preboot attestation  as an example  in table 14 -2. 
Table 14-2: Security Property Example  
Property  Comment  
Confidentiality  Required. VMM should not be able to read the content.  
Integrity  Required. VMM should not be able to write the content.  
Availability  N/A. VMM may disconnect the network for TD. 
Authentication  Mutual authentication  is required . 
1) TD needs to ensure the data is from a real key s erver.  
2) Key server need s to en sure the request is from a known  TD. 
Authorization  Simple  model is used.  
Disk Encryption   
 
Any access (read/write/execute) is allowed once the key is 
acquired . 
Key management (provision/revocation) is out of scope.  
Non-Repudiation  N/A 
One possible way to support the above security propert ies is that the TDVF attestation 
agent  create s an authenticated  secure session with the key server. Then the TD VF 
gets the storage volume key from the key server  in the secure session . 
14.2  Attestation Agent  
14.2.1  Network Communication  
In order to communicate with the remote key server, the TDVF need s network 
capability. Because the TD VF is in TCB, it is not recommended to include a full TCP/IP 
network stack in a TD VF. Instead, the TD VF should use the network stack in the 
untrusted VMM host environment.  
The TDVF may use a special TDG.VP.VMCALL  to send and receive the network packet 
on top of transport layer, such as network T LS packet s, or TDVF may use the VMM 
specific communication, such as virt -io or vmbus.  
14.2.2  Authenticated Secure Session  
The network TLS protocol is a standard to allow two entities  to create a n 
authenticated  secure session. TDVF can provision the public certificate of the key 
server and verify the server certificate at runtime . 
14.2.2.1  Mutual Authentication  
In order to let the key server verify the TD VF, a typical mutual authentication in TLS 
requires X.509 certificate provision. However, it is hard to provision a private key to 
TDVF. A way to resolve this problem is to use remote attestation TLS (RA -TLS).  
RA-TLS does not require private key provision. The TD VF can generate a n ephemeral  
keypair at runtime and include the public key in the TD report data and TD quote 
data. Then the TD VF generates an X.509 certificate at runtime, includes the TD Quote 
in the X.509 certificate, and send s this TD certificate to the key server  as the TLS 
certificate. When the key server  receives the certificate, it gets the TD Quote, verifies 
the Quote, then it can trust the public key. Finally, the key server  can use the public 
key to verify additional  TLS messages.  
14.2.3  Key Server Information  
The remote key server information (such as server certificate ) should be provisioned 
to TDVF configuration FV  as a UEFI variable . It will be used in TLS authentication.  
This information shall be extended to RTMR  for remote attestation.   
 
14.2.4  Key transport  from Server  
Once TD VF and remote key server establish  an authenticated secure session, the 
TDVF can request the key from the server.  This can be done via high level network 
protocol on top of TLS.  
One possible way is to use RESTful API . For exampl e, the TDVF  sends  a “Transfer 
Storage Volume Key ” request message, then the key server returns a “Storage 
Volume Key Data ” response message.  
14.3  Decryption Agent  
14.3.1  Key Passing  – SVKL table  
Once the attestation agent gets the key, the attestation agent  should  allocate a 
reserved data memory and put the key into this memory , then  create a Storage 
Volume Key Location (SVKL) ACPI table to contain the address and size of the key.  
The decryption agent should locate the key from  the SVKL table, read the key, then 
erase the key in the reserved data memory.  
14.3.2  Storage Volume Key Usage  in TD VF 
In Full Disk Encryption, the decryption agent  should decrypt the disk image . Then the 
TDVF can load the OS from the decrypted partition and launch it.  
In Data Partition  Encryption  or container image encryption, the decryption happens 
outside of TDVF  boot phase . 
14.4  High-level Flow  Example s 
14.4.1  Example on Full Disk Encryption  
1. VMM gets the encrypted disk image from the customer.  
2. VMM launches TDVF with encrypted disk.  
3. TDVF launches the attestation agent to communicate with remot e key server.  
4. The  attestation  agent sets up an authenticate secure session with remote key 
server via RA -TLS. 
5. The attestation agent gets the disk encryption key from the remote key server , 
then passes the key to the decryption agent.  
6. The decryption agent decrypts the disk.  
7. TDVF locates the OS loader and boot s to OS.  
 Disk Encryption

14.4.2  Example on Data Partition Encryption  
1. VMM launches TDVF with a normal  OS image  and encrypted use data partition.  
2. TDVF launches the  attestation  agent to communicate with remote key server.  
3. The attestation  agent sets up an authenticate secure session with remote key 
4. The attestation agent gets the storage volume key from the remote key server.  
5. The attestation agent stores the storage volume key in the SVKL ACPI table.  
6. TDVF boots  to OS.  
7. The OS decryption agent  locates the SVKL ACPI table and decrypts the user data 
partition.  
  §   
 
Appendix A  - Reference s 
 
[TDX]  Intel Trust Domain Extensions, 
https://www.intel.com/content/www/us/en/developer/tools/trust -domain -
extensions/documentation.html   
[TDX -CPU]  Intel CPU Architecture Extensions Specification, 
[TDX -SEAM]  Intel TDX Module EAS, 
[TDX -SEAMLoader]  Intel TDX Loader Interface Specification, 
extensions/documentation.html  
[TDX -VMM]  Intel TDX Guest -Hypervisor Communication Interface, 
[TDX Linux Security]  Intel® Trust Domain Extension Linux* Guest Kernel Security 
Specification , https://intel.github.io/ccc -linux-guest -hardening -docs/security -
spec.html  
[Firmware Side Channel]  Host Firmware Speculative Execution Side Channel 
Mitigation , 
mitigation.html  
[ACPI ] ACPI Specification, https://uefi.org/specifications    
[UEFI ] UEFI Specification, https://uefi.org/specifications    
[UEFI PI ] UEFI Platform Initialization Specification, https://uefi.org/specifications    
[Virtio]  Virtual I/O Device (VIRTIO) Version 1. 1, http://docs.oasis -
open.org/virtio/virtio/v1.1/virtio -v1.1.html  
[Hyper -V*] Hyper -V Top-Level Functional Specification (TLFS) , 
https://docs.microsoft.com/en -us/virtualization/hyper -v-on-windows/reference/tlfs   
[TCG2 Protocol ] TCG EFI Protocol specification, 
https://trustedcomputinggroup.org/resource/tcg -efi-protocol -specification/  
[TCG ACPI ] TCG ACPI specification, https://trustedcomputinggroup.org/resource/tcg -
acpi-specification/  Disk Encryption   
 
[TCG PFP ] PC Client -Specific  Platform Firmware Profile Specification , 
https://trustedcomputinggroup.org/resource/pc -client -specific -platform -firmware -
profile -specification/  
[PE COFF]  Microsoft PE COFF specification, 
http://download.microsoft.com/download/9/c/5/9c5b2167 -8017-4bae-9fde-
d599bac8184a/pecoff_v83.docx , https://learn.microsoft.com/en -
us/windows/win32/debug/pe -format  
[Linux Direct Boot]  
https://github.com/torvalds/linux/blob/master/Documentation/admin -guide/efi -
stub.rst  
[Linux Boot Protocol]  https://www.kernel.org/doc/Documentation/x86/boot.txt  
[Linux Boot Parameter]  https://www.kernel.org/doc/Documentation/x86/zero -
page.txt  
[Intel RA -TLS] Intel Remote Attestation TLS, https://github.com/cloud -security -
research/sgx -ra-tls 
[Open Enclave RA -TLS] open enclave Remote Attestation TLS, 
https://github.com/openenclave/openenclave/tree/master/samples/attested_tls , 
https://github.com/openenclave/openenclave/blob/master/include/openenclave/attest
ation/attester.h , 
ation/verifier.h  
  
    Software Enabling for  Intel® TDX in Support of TEE-I/O  Revision 1.00 September 2022                
2        Document Number:  352723-001    Disclaimers  Intel Corporation (“Intel”) provides these materials as-is, with no express or implied warranties. All products, dates, and figures specified are preliminary, based on current expectations, and are subject to change without notice.  Intel does not guarantee the availability of these interfaces in any future product. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described might contain design defects or errors known as errata, which might cause the product to deviate from published specifications.  Current, characterized errata are available on request. Intel technologies might require enabled hardware, software, or service activation.  Some results have been estimated or simulated.  Your costs and results might vary. No product or component can be absolutely secure. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein.  You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted that includes the subject matter disclosed herein. No license (express, implied, by estoppel, or otherwise) to any intellectual-property rights is granted by this document. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice.  Copies of documents that have an order number and are referenced in this document or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting http://www.intel.com/design/literature.htm. © Intel Corporation.  Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.  Other names and brands might be claimed as the property of others.

3        Document Number:  352723-001    Table of Contents Disclaimers ........................................................................................................................................................................ 2 Table of Contents ........................................................................................................................................................... 3 Overview ............................................................................................................................................................................. 4 1 I/O Virtualization ................................................................................................................................................... 6 I/O virtualization for Existing VMs ...................................................................................................................... 6 Direct access to Hardware I/O Devices ............................................................................................................. 6 2 TVMs and I/O Virtualization ............................................................................................................................. 8 Existing TVMs and I/O Virtualization ................................................................................................................. 8 MKTME and DMA Remapping .............................................................................................................................. 9 3 TDISP and Intel TDX ......................................................................................................................................... 11 TEE Device Interface Security Protocol (TDISP) ........................................................................................ 11 Intel TDX in Support of TEE I/O ........................................................................................................................ 13 TDISP-Compliant Devices ................................................................................................................................... 14 IDE on PCIe/CXL Links .......................................................................................................................................... 15 Trusted MMIO and DMA Access Controls .................................................................................................... 16 Secure IOTLB Invalidation .................................................................................................................................. 16 4 Software Enabling for Intel TDX .................................................................................................................. 17 High-Level Software Flows ................................................................................................................................. 17 Conceptual Structure of a VMM with Intel TDX in Support of TEE-I/O ........................................... 21 Host/VMM Changes ............................................................................................................................................... 22 TVM (TD) Changes .................................................................................................................................................. 24 Attestation ................................................................................................................................................................. 25 References ...................................................................................................................................................................... 26   
4        Document Number:  352723-001    Overview The purpose of this white paper is to discuss the software touch points, or new functionalities required in software to enable the Intel TDX technology in support of TEE-I/O, introducing the key features that software developers need to know. The first generation of virtualization-based Trusted Execution Environment (TEE) VMs (Virtual Machines), such as Intel® Trusted Domain Extensions (TDX) guests do not include devices and accelerators into the trust boundary of TVMs (TEE VMs). Devices are not allowed to read/write TVM confidential memory. Because of the limitations, the current techniques used for TVMs incur significant performance overhead especially for high performance I/O.  The TEE Device Interface Security Protocol (TDISP) defines an architecture for trusted I/O virtualization so that the implementations can address the limitations [PCI-TDISP]. TDISP builds upon the foundation provided by the standard messaging protocols and methodologies, such as CMA (The Component Measurement and Authentication)/SPDM (Security Protocol and Data Model) and IDE (Integrity & Data Encryption); SPDM and IDE are general features for operating systems, and they may already be available there. To support TEE-I/O, Intel TDX is designed to implement the TDISP architecture with extensions to the current Intel TDX or TDX 1.0 [INTEL-TDX]. In this document, we use Intel TDX to mean Intel TDX that includes such extensions. Software enabling for Intel TDX should take advantage of such a general architecture, defining the common layer and interfaces in support of TDISP support.  We describe a conceptual structure of a VMM (Virtual Machine Monitor) with Intel TDX support as an example, to help clarify the common elements or subsystems required to enable the TDISP architecture and the ones specific to Intel TDX.    
5        Document Number:  352723-001    The organization of this white paper is as follows:  • Chapter 1 will revisit the existing I/O virtualization technologies and implementations for VMs.  • Chapter 2 will explain the limitations of the current I/O virtualization when used for TVMs. • Chapter 3 will summarize the TDISP architecture and requirements.  And it will introduce the Intel TDX architecture in support of TEE-I/O as Intel’s implementation that helps allow direct assignment and establishment of trust between a TD(s) and a TDI(s) hosted by a TDISP-compatible device. • Chapter 4 will describe high-level software flows for basic operation. And it will show the software touch points, or the new functionality to enable Intel TDX in support of TEE-I/O, describing a conceptual structure of a VMM with Intel TDX support.   
6        Document Number:  352723-001    1 I/O Virtualization  To implement the capabilities for the direct assignment of devices to VMs, the VMM needs to implement certain functions using hardware features, and we revisit how those are implemented to discuss the requirements for TVMs, which may not include the VMM into in the trust boundary. I/O virtualization refers to the virtualization and sharing of I/O devices across multiple VMs or container instances. There are multiple existing approaches for I/O virtualization that may be broadly classified as either software-based or hardware-assisted. I/O virtualization for Existing VMs With software based I/O virtualization, the VMM exposes a virtual device, such as a Network Interface Controller (NIC), to a VM. A software device model in the VMM or the host OS emulates the behavior of the virtual device. The device model translates from virtual device commands to physical device commands before forwarding to the physical device.  Modern processors provide features to reduce virtualization overhead that may be utilized by VMMs to allow VMs direct access to hardware I/O devices.  Direct access to Hardware I/O Devices Those features include capabilities for direct memory access (DMA) and interrupt remapping and isolation that can be utilized to minimize the overheads of IO virtualization [INTEL-DIRECTIO].  Specifically, Intel supports the following hardware-assisted I/O virtualization schemes for direct data movement without needing software assistance: 1. Direct Device Assignment – Assignment of entire device to a VM 2. Single Root I/O virtualization (SR-IOV) – Assignment of a device virtualized function. 3. Scalable I/O virtualization (S-IOV) – Assignment of low-level device interfaces composed by the VMM virtualize a device. Those schemes determine the device interfaces, the unit of assignment for an I/O virtualization-capable device. Device Access via MMIO When device interfaces are assigned to a VM, the MMIO ranges of the device interface are mapped by the processor-level (memory) virtualization, such as the Extended Page Table (EPT) in Intel® Virtualization Technology (VT). When EPT is in use, such MMIO ranges are

7        Document Number:  352723-001    treated as guest-physical address (GPA), and not used to access the ranges directly. Instead, GPAs are translated by traversing a set of EPT paging structures to produce host-physical addresses (HPAs) that are used to access device interfaces. And the EPT paging structures are built by the VMM today for VMs. Since the VMM itself may not be trusted by TVMs, we also need a trusted entity that utilizes the memory virtualization for direct access to MMIO by TVMs. For example, the VMM would need to use the Intel TDX module API to map such trusted MMIO space to a TVM as private memory in the TVM’s Secure-EPT [INTEL-TDX].  DMA Remapping for VMs To allow a VM to use direct assignment of IO devices, the VMM must also enforce isolation of DMA requests by the VM, and the DMA remapping hardware can be used to restrict DMA from a device interface to the physical memory presently owned by its VM. The address-translation hardware transforms the address in a DMA request issued by a device interface to its corresponding HPA. This functionality is also known as IOMMU (IO Memory Management Unit). As Chapter 3 in [INTEL-DIRECTIO] describes, the remapping hardware uses the upper portion of the input address (the address in a DMA request issued by a device interface in a VM, for example) to identify a series of paging-structure entries. The last of these entries identifies the physical address of the region to which the input address translates (called the page frame). The format of the paging structures (VT-d paging structures, hereafter) is different from the EPT paging structures (above) used by the CPU side, but the format of VT-d paging structures is designed to share the same paging structures with EPT. That allows the VMM to build a single set of paging structures used for consistent address translations between the CPU(s) and I/O device(s) in a VM, and this technique is used by some of the existing VMMs today.  Since the VMM itself may not be trusted by TVMs, we also need a trusted entity that utilizes the DMA remapping hardware. It also needs to isolate and protect the setting of the DMA remapping hardware (IOMMU) when the VMM uses the rest of the DMA remapping hardware for VMs.        
8        Document Number:  352723-001    2 TVMs and I/O Virtualization Existing TVMs and I/O Virtualization This chapter shows the current I/O virtualization for TVMs, and it explains the limitations and the causes of performance overhead. The first generation of TVMs, such as Intel® TDX guests, do not include (physical) devices and accelerators into the trust computing base of TVMs. Devices are not allowed to read/write TVM confidential memory.  Because of the limitation, today the VMM exposes synthetic device interfaces to TVMs for I/O virtualization. The synthetic device interface is defined to be virtualization-friendly to enable efficient virtualization compared to the overhead associated with I/O emulation. This, however, requires the TVMs to stage the data that needs to be sent (or “copy-out”) or received (“copy-in”) from devices in shared memory, which is designed to hold contents accessible to the TVM and the VMM. Further to protect the confidentiality and integrity of such data, the TVM is expected to use cryptographic protections on the I/O data (See Figure  2-1 below). For some synthetic I/O devices like network and storage, TVM may employ software based cryptographic techniques for data protection. For example, for networking the TVM may use TLS (Transport Layer Security) or such mechanisms to protect the data sent to the NIC (Network Interface Card), and for storage the TVM may employ file system encryption schemes.  However, such techniques incur significant performance overhead especially for high performance devices.     
9        Document Number:  352723-001     Figure  2-1:  Current I/O Handling in TVM    Even if there is a particular device such as a GPU or an FPGA accelerator that the TVM includes into its TCB using its own security policy, the cryptographic data protection does not allow the TVM to offload computation directly to such GPUs or FPGA accelerators.  MKTME and DMA Remapping For legacy Intel VMX-based VMs where the VMM needs to be included in their TCB, the multi-key, total-memory-encryption (MKTME) technology can be used to enable memory encryption and enhance it by adding support for cryptographic-integrity protection. For directed I/O use cases mentioned in Chapter 1, the VMM needs to set a KeyID1 as part of the physical addresses in the VT-d paging structures corresponding to the KeyID as part of the physical addresses in EPT employed for the CPU side. This will allow DMAs to be able to access memory without requiring changes to I/O devices and/or I/O drivers in the legacy VM. For TVMs that may not include the VMM into TCB, the above implementation is not available because the KeyIDs are visible to the VMM, and because they need to be programmed by the VMM.  For Intel TDX the set of KeyID(s) supported by MKTME can be partitioned into two groups of KeyID(s) – a set of private KeyID(s) and a set of shared KeyID(s). Intel TDX uses a set of private  1 A KeyID identifies a key used by MKTME. TVM
VMM
IO DataIO Data
DeviceEncrypt & Copy-outDecrypt & Copy-inTrust Compute BoundaryShared Memory
DMA 
10        Document Number:  352723-001    KeyIDs, and private KeyIDs can only be programmed with keys when called from Intel TDX module. This implies that Intel TDX module needs to be extended to help provide secure DMA remapping or IOMMU management functions to the VMM to add or remove mappings from the VT-d paging structures. In addition, if the Data Links between the TVM and the Trusted Device (Figure  2-2 below) are not in TCB of the TVM because of the intermediate switches that are out of the trust compute boundary, for example, the TVM still needs to use the shared memory combined with cryptographic data protection. Also, such GPUs or FPGA accelerators need to make DMA operations with encryption/decryption sharing the key with the CPU side.   
 Figure  2-2: GPU or FPGA accelerator with TVM  As we discussed above, we need to extend various areas, including hardware, to enable trusted I/O virtualization. The TEE Device Interface Security Protocol (TDISP) defines an architecture for trusted I/O virtualization, and we will look at an overview of TDISP in the next chapter, introducing the Intel’s implementation of the functionality defined by TDSIP. See [TDISP] for details of TDISP. TVM
VMM
IO DataIO DataEncrypt & Copy-outDecrypt & Copy-inTrust Compute Boundary
Trusted DeviceData LinkDMA(w/ encryption/decryption)Shared Memory 
11        Document Number:  352723-001    3 TDISP and Intel TDX TEE Device Interface Security Protocol (TDISP) TDISP defines an architecture for trusted I/O virtualization [PCI-TDISP] which includes: A. Establishing a trust relationship between a TVM and a TDISP-compliant or TEE-I/O device. A TEE-I/O device interface (TDI) is the unit of assignment for an IO-virtualization capable device. For example, a TDI may be an entire (physical) device, a non-IOV Function, or a virtual function (VF). B. Securing the data-path PCIe interconnect between the host and device. Physical access may be used to tamper with the data transferred between the host and the device. Transfers must be cryptographically protected to provide confidentiality, integrity, and replay protection to TVM data. Such schemes must also guard against violations of producer-consumer ordering.  C. Support TDISP assignment and removal life cycle in a trusted manner.  TDISP builds upon the foundation provided by: • CMA/SPDM. The SPDM (Security Protocol and Data Model) specification [DMTF-0274] defines standard messages, data objects, and sequences for performing message exchanges between devices. The message exchanges include authentication and provisioning of hardware identities, measurement for firmware identities, session key exchange protocols to enable confidentiality with integrity protected data communication and other related capabilities. The Component Measurement and Authentication (CMA) [CMA] defines optional security features based on the adaptation of the data objects and underlying protocol defined in SPDM. <Examples will be shown later> • IDE (Integrity & Data Encryption). IDE provides confidentiality, integrity, and replay protection for Transaction Layer Packets (TLPs) [PCIe 6.0]. This provides the implementation for B above.  Figure 3-1shows the TDISP Host/Device Reference Architecture. The TEE security manager (TSM) is a logical entity in a host that is in the TCB for a TVM and enforces security policies on the host.  In other words, the TSM needs to be implemented by a particular technology. When implementing the TSM in the Intel TDX architecture, the Intel TDX module is extended to function as the TSM.    
12        Document Number:  352723-001     Figure 3-1: TDISP Host/Device Reference Architecture (from [PCI-TDISP])  As we show below, we also use TPA (TDX Provision Agent) to implement part of the TSM. TPA is an architectural TD that extends the Intel TDX module. The TSM tracks the TDISP state of the TDIs in the figure above, and Figure 3-2 shows the state machine.  Some of the transitions are triggered by the TVM that the TDI is assigned to. For example, the TVM requests the TSM to move the TDI to the RUN state by sending a TDISP START_INTERFACE_REQUEST indirectly; as we explain in Chapter 4, the VMM communicates with the device (DSM) and sends/receives actual TDISP messages, regardless of the originator of the message, getting the secured payload from the Intel TDX module.

12        Document Number:  352723-001     Figure 3-1: TDISP Host/Device Reference Architecture (from [PCI-TDISP])  As we show below, we also use TPA (TDX Provision Agent) to implement part of the TSM. TPA is an architectural TD that extends the Intel TDX module. The TSM tracks the TDISP state of the TDIs in the figure above, and Figure 3-2 shows the state machine.  Some of the transitions are triggered by the TVM that the TDI is assigned to. For example, the TVM requests the TSM to move the TDI to the RUN state by sending a TDISP START_INTERFACE_REQUEST indirectly; as we explain in Chapter 4, the VMM communicates with the device (DSM) and sends/receives actual TDISP messages, regardless of the originator of the message, getting the secured payload from the Intel TDX module. 
 
13        Document Number:  352723-001     Figure 3-2: TDISP State Machine from [PCI-TDISP]  Since a TVM is implemented as TD (Trusted Domain) virtual machine on Intel TDX, we use “TD” below to indicate as such.   Intel TDX in Support of TEE I/O Intel TDX is designed to implement the functionality defined by TDISP with extensions to the first generation of Intel TDX or Intel TDX 1.0 [INTEL-TDX], addressing the restrictions discussed in Chapter 2 to include devices and accelerators into TDs. Such devices admitted into the trust boundary of a TD can thus access TD confidential memory and can compute on the data provided by the TDs.  Specifically, the framework of Intel TDX defines the following elements, and the circled numbers in Figure 3-3 correspond to the ones below: 1. TDISP-compliant (TEE-I/O) device. As an example, the figure shows that a (physical) TEE-I/O device has two TDIs (TDI1 and TDI2) and Device Security Manager (DSM), which is explained below. It also has a legacy VF (Virtual Function) and physical function device. TDI1 is assigned to TVM1, and TDI2 to TVM2. Multiple TEE-I/O devices may exist in the system, and their configuration can be different.  
 
14        Document Number:  352723-001    2. Integrity and Data Encryption (IDE) on PCIe/CXL Links. IDE is defined by [PCI-IDE], and is designed to provide confidentiality, integrity, and replay protection for Transaction Layer Packets (TLPs). 3. Trusted MMIO and DMA access controls.  4. Intel TDX module (and TPA) extensions. The extensions provide the functionality of TEE Security Manager (TSM) defined by TDISP, which is a logical entity in a host that is in the TCB for a TVM and enforces security policies on the host [TDISP]. TPA (TDX Provision Agent) is an architectural TD that extends the Intel TDX module which is responsible for the SPDM session establishment between the Intel TDX module and the device.  Note that the TEE-IO Device is moved to the right-hand side from the bottom in Figure 3-3 compared with Figure 3-1, but the Intel TDX architecture is consistent with the TDISP reference architecture.   
 Figure 3-3: Intel TDX (w/ TEE-I/O)   TDISP-Compliant Devices The Device Security Manager (DSM) is a logical entity, and it provides the following functions: • Authentication of device identities and measurement reporting. • Configuring the IDE encryption keys in the device. The Intel TDX module provides the keys for the initial configuration and subsequent key refreshes to the DSM using the IDE key management protocol. TVM1(TD)HostVMMTDI2INTEL®  TDX MODULETPA(TD)TDI1LegacyVFPhysicalFunctionDSMPCIe-IDEPortINTEL®  TDX SOC
Trusted MMIO, DMAPCIe-IDE Root PortTrusted MMIO, DMATrusted MMIO, DMASPDM Cert + Key ExchangeTDISP, IDE_KMIDE Selective  StreamSPDM BindLegacy VM1
Intel TDX (w/ TEE-I/O) Host SOCTEE-I/O DeviceBridges/Swiches234TDXHost APIsTVM2(TD)TDXGuest APIsIOMMU and IDE Programing Interface 
15        Document Number:  352723-001    • Locking the TDI configuration, reporting TDI configurations, attaching, and detaching TDIs to TDs.  • Implementing access control and security mechanisms to isolate TD data from entities not in the TCB of the TD. A TDISP-compliant device must satisfy the TDISP specification for TEE-I/O device security requirements and have a DSM implementation with the following capabilities: 1. Device function 0 must implement a DOE (Data Object Exchange) [PCI-OED] mailbox and support the CMA/SPDM 1.2 protocols for device authentication. 2. At least one Selective IDE Stream and implement IDE key management (IDE_KM) protocol as a Responder. 3. Per TDI implementation of the TDISP state machine management with support for locking the TDI configuration, reporting the TDI configurations and moving the TDI in and out of RUN state. 4. Implementing access control and security mechanisms to isolate TVM provided data from entities not in the TCB of the TD. The host CPU and the device must use the established Secure SPDM session of 1. As secure transport for passing host requests and device response messages for the protocols implemented for 2 and 3. IDE on PCIe/CXL Links As defined by TDISP, Intel TDX requires establishment of a secure connection with a device such that: • Data that flows between the TD and a trusted device must remain confidentiality, integrity, and replay protected, using the keys derived in above step. • Metadata associated with transfers (e.g. logical addresses of DMA transfers in the TD’s address space) must be integrity and replay protected. A port-to-port connection established using the mechanisms defined by IDE to secure TLP traffic between the two ports. The connection may be in the form of a selective IDE stream, in which case it is possible for IDE TLPs to flow through switches without affecting their security, or in the form of a link IDE stream, in which case the two ports must be connected without intervening switches. When there are no switches between the ports, then it is possible to secure all, or only selected, TLP traffic on the Link.   The Intel TDX security architecture excludes switches from the TCB of TD and devices participating in the Intel TDX framework. To that effect, the Intel TDX architecture exclusively uses the selective IDE streams to protect the TLPs flowing between the SOC root complex and the Intel TDX capable endpoint devices.  
16        Document Number:  352723-001    Trusted MMIO and DMA Access Controls Trusted MMIO access controls As we discussed in Chapter 2, the VMM needs to use Intel-TDX module APIs to map a TDI trusted MMIO space to a TD as private memory in the TD’s Secure-EPT. When the TD accesses the MMIO page using private guest-physical address (GPA), the translated host-physical address (HPA) gets the TD private (Host KeyID) HKID. The base Intel TDX already enforces that no other context (e.g., VMM or other TD) may use the TD HKID. MMIO pages can only be mapped to TDs if the TD accepted GPA as MMIO page and it is matching the device owner and offset from MMIO base address as indicated by the TD. According to TDISP spec, TDI enforces that: 1. When a TDI is not in RUN state, trusted MMIO accesses (IDE with TLP T bit set) must be rejected 2. When TDI is in CONFIG_LOCKED, the TDI must capture the IDE stream ID from the INTERFACE_LOCK_REQUEST message and use it later to ensure trusted IO transactions only use this IDE stream. 3. When DI is in RUN state, non-trusted MMIO accesses (IDE with TLP T bit clear) or with the wrong IDE stream ID, must be rejected and when TDI is in TDISP RUN state. Trusted DMA access controls Intel TDX enforces Secure DMA access controls to help ensure that a TDI may only access TD private memory after: 1. The TD has accepted the device into its TCB 2. The TDI is in TDISP CONFIG_LOCKED or RUN state (TDI is responsible not to access or accept TD memory accesses when it’s not in TDISP RUN state) 3. The TD has verified the TDI report and explicitly accepted the TDI MMIO pages and trusted DMA mappings between the TDI and the TD private memory. Secure IOTLB Invalidation IOMMU has caches that are used to save DMA remapping table translation overhead for recurrent DMA accesses. On legacy VT-d, for example, the VMM is responsible for the blocking and the invalidation of the relevant IOTLB (I/O Translation Lookaside Buffer) caches before changing or removing the mapping structures that may have been cached. The Intel TDX module is responsible for invalidating the IOTLB caches to help ensure that stale entries cannot be used to perform DMA attacks and access trusted TD memory assets once a TDI binding has been removed from the TD. This is enforced by extending the current Intel TDX TLB tracking with IOTLB tracking, which is done by the Intel TDX module following the TLB tracking sequence: BLOCK, TRACK, INVALIATE, and REMOVE [INTEL-TDX].

17        Document Number:  352723-001    4 Software Enabling for Intel TDX In this chapter, we assume that 1) the VMM already supports the Intel TDX 1.0 specified by [INTEL TDX], and 2) the guest OS also has changes for Intel TDX 1.0 (also known as “TDX enlightenments”) to run as a TD. First, we describe the high-level software flows for the basic operations to identify the components and to show the interactions among them based on the TDISP architecture with the Intel TDX functionalities. Second, we discuss the software touch points to implement Intel TDX support in the VMM and TDs, taking advantage of the software subsystems required to implement the TDISP framework. High-Level Software Flows The following (the step A – D) shows high-level software flows for the basic operations with Intel TDX when a TDI is assigned to a TD.  The TDI is owned by a TEE-I/O device below. The steps correspond to the circled A-C in Figure 4-1 and the D in Figure 4-2.  A. Initialize the host machine for Intel TDX.  1. The Intel TDX module extensions for TEE-I/O require a reliable mechanism to enumerate the underlying Intel TDX hardware. The emulation is given to the Intel TDX module as a global “IO System Information Table” which describes the (MCHECK verified) IO configuration information (per socket and IOMMU). See [INTEL-TDX] for MCHECK. 2. The VMM loads the Intel TDX module (if not already done) and completes initialization of the Intel TDX module, checking for the presence of the TEE-I/O support capability (A1).  3. It configures the Trusted IOMMU and the PCI express root ports (A2).  4. It launches the TPA TD (A3).  This step is global for the system. B. Start the SPDM session with the device for secure communication.  1. The VMM checks the device capability by reading the device PCI DOE capability and IDE capability (B1). As described in Chapter 3, as one of the requirements for a TDISP-compliant device, the device function 0 must implement a DOE mailbox. 2. It creates SPDM metadata for the Intel TDX module (B2). 3. It invokes TPA to start the SPDM session with a physical device, injecting an interrupt event (B3).  4. TPA uses SPDM to collect the device certificate and measurement and return to the VMM for device attestation later (B4).   
18        Document Number:  352723-001    5. TPA passes the SPDM session keys to the Intel TDX module.  The parameter also includes a hash of the device information, which is used later to ensure that the TD get the unmodified device information from the VMM. The Intel TDX module provides functions that can be invoked only by a TPA TD to bind keys, capability, and device identity into the SPDM session metadata (B5).  6. TPA returns device certificates and measurements to the VMM.  This step is done per device.  C. Set up the IDE stream for link encryption.  1. The VMM creates IDE stream by calling the Intel TDX module. 2. It queries and configure the device IDE extended capabilities. 3. It programs keys for all IDE sub streams with both receive and transmit direction. The Intel TDX module provides functions for the VMM to generate IDE_KM messages (KEY_PROG) and to process the response.  Upon a KEY_PROG request, the Intel TDX module generates an ephemeral key and program it to the root-port key programming register. 4. It starts all IDE sub streams with both receive and transmit direction. The Intel TDX module provides functions for the VMM to generate IDE messages (K_SET_GO) and to process the response. If the Intel TDX module receives K_GOSTOP_ACK response for the K_SET_GO request, the Intel TDX-module will trigger IDE stream for the Root Port. After this step, the device and host SOC have two communication secure sessions. The SPDM session is a software session, which is used for software configuration such as IDE_KM and TDISP. The IDE session is a hardware session, which is used to secure the PCI express TLP.  This step is also per device.   As Figure 3-2 shows the TDISP state machine [PCI-TDISP], and each TDI is associated with that. The goal of Step D is to move the TDI into the TDISP RUN state. In general, the VMM initiates the steps with the TD, and the TD is responsible for checking the information provided or the operations made by the VMM by using the trusted information from the Intel TDX module (including TPA) and the DSM. The TD is also responsible for accepting the configuration upon successful verification to move on to the next step.  
19        Document Number:  352723-001     Figure 4-1: Step A-C  TDISP messages are integrity-protected, and the VMM communicates with the device (DSM) and sends/receives actual TDISP messages, regardless of the originator of the message (the VMM or TD). But the VMM needs to call the Intel TDX module to prepare (encrypt and protect) a required TDISP message, and the Intel TDX module returns the secured payload that the VMM can send to the device. If the TD initiates the steps, the interaction with the VMM needs to use a structure like the following: 1. The TD informs the Intel TDX module of the intent to send a TDISP message in advance. This step is required so that the Intel TDX module can later check that the VMM didn’t tamper with the request (step 3 below). 2. The TD requests the VMM to send the TDISP message to, a device (DSM), for example, using a hypercall (TDG.VP.VMCALL). 3. As described above, the VMM needs to call the Intel TDX module because the TDISP message needs a secured payload, which be prepared only by the Intel TDX module. The Intel TDX module checks that the message is what the device intended to send (step 1 above) and returns the secure payload to the VMM. 4. The VMM sends the TDISP message to the device. For example, the above applies to the Step D-6 below.  D. Start the TDI. 1. The VMM creates a data structure for the device interface and configures the TDI (D1). The state of the TDI is TDISP CONFIG_UNLOCKED state. It also prepares the MMIO metadata structure and associates the TDI MMIO pages with the data structure. HostVMMTDI2INTEL®  TDX MODULETPA(TD)TDI1LegacyVFPhysicalFunctionDSMPCIe-IDEPortINTEL®  TDX SOC
Trusted MMIO, DMAPCIe-IDE Root PortSPDM Cert + Key ExchangeIDE_KMIDE Selective  StreamSPDM BindLegacy VM
Intel TDX (w/ TEE-I/O) Host SOCTEE-I/O DeviceBridges/SwichesTDXHost APIsConfig IOMMURoot PortA3Launch TPAA2B5C4A1C3B1B3Start SPDM SessionB2B4B5
C1C2 
20        Document Number:  352723-001    2. The VMM calls the Intel TDX module to move it to TDISP CONFIG_LOCKED state (D2), by generating a TDISP message – LOCK_INTERFACE_REQUEST. 3. The VMM creates a TD and assigns the TDI to the TD, by advertising the TDI in PCIe enumeration. 4. The TD gets the device certificate and measurement from the VMM, then the TD verifies the device based on a TD specific policy. For example, the device certificate must have a trusted root CA (Certification Authorities) and the device measurement must match the latest reference manifest published by the device vendor. 5. If the verification passes, the TD can accept the TDI to the Intel TDX module. 6. The TD uses the TDISP protocol to send TDISP message – GET_DEVICE_INTERFACE_REPORT from the DSM. Note that the Intel-TDX IO provides functions that the TD can use to send TDISP messages (D6).  7. The TD accepts the MMIO and DMA mappings in the report by the functions provided by the Intel TDX module. 8. The TD requests the Intel TDX module and VMM to move the TDI into the TDISP RUN state (D8).  It receives a TDISP message – START_INTERFACE_REQUEST from the VMM. 9. The TD pins/unpins private GPA pages as part as DMA allocate/free. Now TD can start the TDI and use trusted DMA to communicate directly with the TDI (D9).  This step is per device interface. 
 Figure 4-2: Step D  The VMM can repeat same above process to assign another TDI to another TD. Note that one TD may accept multiple TDIs but one TDI must not be assigned to more than one TD. HostVMMTDI2INTEL®  TDX MODULETPA(TD)TDI1LegacyVFPhysicalFunctionDSMPCIe-IDEPortINTEL®  TDX SOC
Trusted MMIO, DMAPCIe-IDE Root PortSPDM Cert + Key ExchangeIDE_KM, TDISPIDE Selective  StreamSPDM BindLegacy VM
Intel TDX (w/ TEE-I/O) Host SOCTEE-I/O DeviceBridges/SwichesTDXHost APIsConfig IOMMU Root PortSPDM MgmtTVM1(TD)Trusted MMIO, DMA
D1TDXGuest APIsD9D2CONFIG_LOCKEDD8CONFIG_RUND6GET_DEVICE_INTERFACE_REPORT

Figure 4-2: Step D  The VMM can repeat same above process to assign another TDI to another TD. Note that one TD may accept multiple TDIs but one TDI must not be assigned to more than one TD. HostVMMTDI2INTEL®  TDX MODULETPA(TD)TDI1LegacyVFPhysicalFunctionDSMPCIe-IDEPortINTEL®  TDX SOC
D1TDXGuest APIsD9D2CONFIG_LOCKEDD8CONFIG_RUND6GET_DEVICE_INTERFACE_REPORT  
21        Document Number:  352723-001    If a TDI is no longer needed, then the TD or VMM can stop the TDI. If all TDIs in a device are removed, the VMM can remove the IDE stream and terminate the SPDM session for the device. If all devices managed by an IOMMU are disconnected, the VMM can reinitialize the IOMMU. Conceptual Structure of a VMM with Intel TDX in Support of TEE-I/O In the following sections, we discuss the software touch points or new functionality to enable Intel TDX in support of TEE-I/O.  As we showed above, software enabling for Intel TDX can take advantage of the standard and general security operating-system (OS) features, which are not necessarily related with virtualization: • General OS features – PCI-SIG DOE, SPDM, IDE subsystem • Virtualization features – PCI I/O virtualization subsystem and IOMMU.  • TEE-I/O support – TDISP support (the host and guest side)  • Hardware-based TEE support, such as Intel TDX support Some of the above may already be present or under development because of the generic features.  The following Figure 4-3 conceptually shows the touch points in the VMM subsystems with a TD, or the code required to be modified/added, and we categorize them into the following: • Required for TDISP support – general OS functionality. The code may already be present or under development.  • TDISP support – general functionality to support TDISP TEE-I/O. Since Intel TDX is an implementation of the TDISP functionalities, it would depend on the common code. • Intel TDX support – functionalities that specifically utilize the Intel TDX. They are typically placed under the common or abstracted layer. • I/O virtualization support – general functionality required for direct assignment of I/O devices to (legacy) VMs. This includes CPU, memory, interrupts virtualization (including Intel TDX support), and the PCI virtual I/O subsystem. Only the related areas are shown in the figure.  
22        Document Number:  352723-001     Figure 4-3: Software Touch Points for Enabling Intel TDX Next, we describe more details of the subsystems and the touch points with the circled numbers in the figure. The changes to TDs (○4) will be described later in details. Host/VMM Changes As we showed, the VMM is not required to be TCB of TDs, but it still performs resource allocations as it does for the current Intel TDX support. In this paper, we focus on PCIe devices, and TEE-I/O devices are enumerated as PCIe devices. PCI Virtual I/O Subsystem Since TEE-I/O devices will have “TEE-I/O Supported” in the Device Capabilities Register, the PCI subsystem should be able to identify the TEE-I/O devices. For such TEE-I/O devices, additional initialization is required by the VMM so that they can be assigned to a TD(s). If a device(s) identified as “TEE-I/O capable”, then the TDSP subsystem should manage the device (○1).   Host/VMMINTEL®  TDX MODULETPA(TD)
TDIsLegacy VMTDTDXGuest APIs
PCI DOEIDEPCI Virtual I/O subsystem
TDISPSPDMCPU, memory, interrupts virtualization(Including TDX support)IOMMUTDX SupportTDISPTDX Support
TDXHost APIsTDXHost APIs3
21TDX SupportTDISP4
TEE-I/O DeviceDSMPCIe-IDEPort
Attestation
TDISP supportIntel TDX (w/ TEE-I/O) supportRequired for TDISP supportI/O virtualization support 
23        Document Number:  352723-001    TDISP Subsystem The TDISP subsystem supports TEE-I/O use cases, and implements the following functionalities: • Initialize the device(s) based on the TDISP requirements, managing the TDISP state machine of TDIs: CONFIG_UNLOCKED, CONFIG_LOCKED, CONFIG_RUN, and CONFIG_ERROR. • Request SPDM session. As we see in the TDISP architecture, the SPDM session is required for the secure communication between the TSM (TEE Security Manager, Intel TDX module and TPA in Intel TDX) and DSM (Device Security Manager). • Request IDE selective streams. • Bind a TDI(s) to the target TVM. As described, the requests from the VMM or from the TD(s) are sent to the Intel TDX module first (○2) to prepare the secured payload, and then they are handled by SPDM. Such requests include: • Lock (TDISP CONFIG_LOCKED) or stop (TDISP CONFIG_UNLOCKED) TDIs • Get Device Interface Report (TDISP GET_DEVICE_INTERFACE_REPORT)  IDE Subsystem As we showed at the Step C above, the IDE subsystem implements the following functionalities: • Set up IDE selective streams between two ports.  • Configure the IDE extended capability for the target device by the PCIe driver. The following are related with Intel TDX support (○2): • Configure the IDE extended capability for Root Port by requesting the Intel TDX module. IDE needs to use the functions provided by the Intel TDX module. • As we showed above, IDE Key Programming for the Root Port is done by the TDX module (Step C-3), and IDE needs to use the functions provided by the Intel TDX module. • IDE Key Programming for the target device by Intel TDX module (IDE_KM_KEY_PROG). It requests the Intel TDX module to generate IDE_KM requests and sends them via SPDM session/DOE mailbox. IOMMU Subsystem This subsystem needs to exist for the existing I/O virtualization, especially to support direct assignment of I/O devices, as we discussed in Chapter 1. Thus, we focus on the additional functionality required for Intel TDX (○3).  The IOMMU subsystem implements the following functions:  
24        Document Number:  352723-001    • Configure Trusted IOMMU to Intel TDX mode during initialization (Step A). • Use the functions provided by the Intel TDX module to access a trusted IOMMU register.  As we discussed in Chapter 1, the format of VT-d (IOMMU) paging structures is designed to share the same paging structures with EPT. This also applies to Intel TDX, that is, the IOMMU paging structures can be shared with Secure-EPT (S-EPT), and this is the implementation used by the Intel TDX module for Intel TDX to add trusted IOMMU functionality effectively and efficiently.  Since the CPU-side already manages S-EPT, one of the options would be: • The IOMMU subsystem requests the S-EPT management component to build the S-EPT in advance. This is because most I/O devices cannot tolerate a page fault, unlike the CPU-side where the faulted instruction is restarted after handling of S-EPT violation. MMIO Subsystem As discussed in Chapter 1, the VMM uses the EPT to map the MMIO ranges for the device interfaces assigned to VMs. Unlike for the mapping for the usual memory, however, the EPT memory type is typically set to UC (uncacheable) for the device interfaces. This also applies to Intel TDX, and the current Intel TDX module doesn’t allow the VMM to set UC for the S-EPT memory type. For Intel TDX, the Intel TDX module provides functions for the VMM to map the TDI MMIO pages, and the VMM needs to use the functions (○3). Interrupts Handling Non-NMI interrupt injection into TDs by the VMM or the IOMMU can be done through the posted-interrupt mechanism [INTEL-TDX]. TVM (TD) Changes In general, the TVM (TD) is responsible for checking the devices, the SPDM sessions, IDE keys, and TDIs using the trusted information before accepting or using the TDIs.  Enumeration of TDISP Devices First-level enumeration of TDSP devices can be done by checking “TEE-I/O Supported” in the Device Capabilities Register as the host does. And the PCI subsystem should be able to identify the TEE-I/O devices.  Checking prior to accepting an TDI A TD must ask the following questions before it accepts an TDI into its TCB: 1. Is the identity of the device and the measurements reported by the device hosting the TDI acceptable?

25        Document Number:  352723-001    2. Is there a SPDM secure session established between TSM and the DSM and is the identity authenticated by the Intel TDX-module to set up the SPDM secure session match the identity reported to the TD? 3. Were all IDE keys for the IDE stream used by the TDI established by the Intel TDX-module? 4. Has the VMM configured the TDI and mapped the TDI into the TD address space as expected? The TD gets the device certificate and measurements from the VMM to determine the answer to question 1. The information should have been reported by the TPA to the VMM (Step B-4). The TD calculates a hash of the data structure, and it requests the Intel TDX-module to verify that the hash matches the one calculated by the TPA (Step B-5). The TD queries the Intel TDX-module to determine the answers to question 2 and 3. The TD uses the report of the TDI configuration (TDISP specified – GET_DEVICE_INTERFACE_REPORT) from the DSM. The TD may then use the report and communicate with the Intel TDX-module to determine the answer to the question 4 (○4). If the answer to each of these questions is a yes, then the TD may accept the TDI into its TCB. DMA Subsystem Today, DMA buffers are allocated from shared memory in TDs because of the limitation described in Chapter 2, and DMA buffers for TDIs need to be allocated from private memory. Also, the TD needs to explicitly accept or remove the mapping done by the VMM using the function provided by the Intel TDX module. TDI assignment to TDs requires the VMM to set up the trusted translations in the IOMMU for DMA remapping. And the mapping becomes valid once the TD accepts the mapping. MMIO Subsystem Likewise, the TD needs to accept all the device MMIO pages described in all the MMIO_RANGEs in the report from the TDISP message – GET_DEVICE_INTERFACE_REPORT.  Attestation Attestation implementations are out of scope of this white paper. For device attestation, the white paper “Device Attestation in Confidential Computing Environment” convers the details required for TEE-I/O devices [DEV-ATTEST].  For a TVM (TD), it is also required to verify the device driver for the TDI before using the device interface unless the device driver is already covered by the attestation for the OS (kernel, etc.). The actual change would depend on the current attestation implementation of the TVM.   
26        Document Number:  352723-001    References [DMTF-2058] DMTF, DSP2058: Security Protocol and Data Model (SPDM) Architecture White Paper, https://www.dmtf.org/dsp/DSP2058 [DMTF-0274] DMTF, DSP0274: Security Protocol and Data Model (SPDM) Specification, https://www.dmtf.org/dsp/DSP0274 [PCI-PCIE] PCI, PCI Express Base 6.0 Specification, https://members.pcisig.com/wg/PCI-SIG/document/16609  [PCI-IDE] PCI, Integrity & Data Encryption (IDE) – Revision A,  https://members.pcisig.com/wg/PCI-SIG/document/16599 [PCI-TDISP] PCI, Trusted Device Interface Security Protocol (TDISP) ECN, https://members.pcisig.com/wg/PCI-SIG/document/16849  [CXL-CXL] CXL, CXL 2.0 Specification, https://www.computeexpresslink.org/  [OCP-SIOV] OCP, Scalable I/O virtualization, https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf   [AMD-SEV] AMD, AMD Secure Encrypted Virtualization (SEV), https://developer.amd.com/sev/  [ARM-RME] ARM, ARM Realm Management Extension (RME), https://developer.arm.com/documentation/den0129  [INTEL-TDX] Intel, Intel Trust Domain Extensions (TDX), https://software.intel.com/content/www/us/en/develop/articles/intel-trust-domain-extensions.html  [RISCV-APTEE] RISCV, RISCV AP TEE, https://github.com/riscv-non-isa/riscv-ap-tee/blob/main/specification/attestation.adoc  [INTEL-DIRECTIO] Intel, Intel Virtualization Technology for Directed I/O Architecture Specification, https://www.intel.com/content/www/us/en/developer/tools/overview.htm [INTEL-MKTME] Intel, Intel® Architecture Memory Encryption Technologies Specification, https://software.intel.com/sites/default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption-Spec.pdf [DEV-ATTEST] Device Attestation Model in Confidential Computing Environment, https://software.intel.com/content/www/us/en/develop/articles/intel-trust-domain-extensions.html  Advanced Conﬁguration and Power
Interface (ACPI) Speciﬁcation
Release 6.5
1.1 Principal Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Principle of Inclusive Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Power Management Rationale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Legacy Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 OEM Implementation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Power and Sleep Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 ACPI Speciﬁcation and the Structure of ACPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.7 OS and Platform Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.7.1 Platform Implementations of ACPI-deﬁned Interfaces . . . . . . . . . . . . . . . . . . . . . 6
1.7.1.1 Recommended Features and Interface Descriptions for Design Guides . . . . . . . 6
1.7.1.2 Terminology Examples for Design Guides . . . . . . . . . . . . . . . . . . . . . . 8
1.7.2 OSPM Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7.3 OS Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.8 Target Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.9 Document Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9.1 ACPI Introduction and Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9.2 Programming Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9.3 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.9.4 Technical Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.9.5 Revsion Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.10 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Deﬁnition of Terms 15
2.1 General ACPI Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Global System State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.1 Device Performance States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Sleeping and Soft-off State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 Processor Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6 Device and Processor Performance State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 ACPI Concepts 26
3.1 System Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Power Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.2 Platform Power Management Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.2.1 Mobile PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.2.2 Desktop PCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.2.3 Multiprocessor and Server PCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
i3.3 Device Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.1 Device Power Management Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.2 Power Management Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.3 Device Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.4 Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 Controlling Device Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.1 Getting Device Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.2 Setting Device Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.3 Getting Device Power Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.4 Waking the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.5 Example: Modem Device Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.5.1 Obtaining the Modem Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.5.2 Setting the Modem Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.5.3 Obtaining the Modem Power Status . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.5.4 Waking the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5 Processor Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.6 Device and Processor Performance States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.7 Conﬁguration and “Plug and Play” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7.1 Device Conﬁguration Example: Conﬁguring the Modem . . . . . . . . . . . . . . . . . . . 37
3.7.2 NUMA Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8 System Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9 Battery Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.9.1 Battery Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.9.2 Battery Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9.3 Battery Gas Gauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9.4 Low Battery Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.9.4.1 Emergency Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.9.5 Battery Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.9.6 Battery Charge Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.10 Thermal Management Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.10.1 Active and Passive Cooling Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.10.2 Performance vs. Energy Conservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.10.3 Acoustics (Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.10.4 Multiple Thermal Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.11 Flexible Platform Architecture Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.11.1 Hardware-reduced ACPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11.1.1 Interrupt-based Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11.2 Low-Power Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11.2.1 Low Power S0 Idle Capable Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11.3 Connection Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.11.3.1 Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 ACPI Hardware Speciﬁcation 48
4.1 Hardware-Reduced ACPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1.1 Hardware-Reduced Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1.1.1 GPIO-Signaled Events or Interrupt Signaled Events . . . . . . . . . . . . . . . . . 49
4.1.1.2 Interrupt-based Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Fixed Hardware Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3 Generic Hardware Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4 Diagram Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.5 Register Bit Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6 The ACPI Hardware Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6.1 Hardware Reserved Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.6.2 Hardware Ignored Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ii4.6.3 Hardware Write-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.6.4 Cross Device Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.6.4.1 Example 1: Related Device Interference . . . . . . . . . . . . . . . . . . . . . . . 57
4.6.4.2 Example 2: Unrelated Device Interference . . . . . . . . . . . . . . . . . . . . . . 57
4.7 ACPI Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.8 ACPI Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.8.1 ACPI Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.8.1.1 PM1 Event Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.8.1.2 PM1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.8.1.3 PM2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.8.1.4 PM Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.8.1.5 Processor Control Block (P_BLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.8.1.6 General-Purpose Event Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.8.2 Fixed Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.8.2.1 Power Management Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.8.2.2 Console Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.8.2.3 Sleeping/Wake Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.8.2.4 Real Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.8.2.5 Legacy/ACPI Select and the SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . 72
4.8.2.6 Processor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.8.3 Fixed Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.8.3.1 PM1 Event Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.8.3.2 PM1 Control Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.8.3.3 Power Management Timer (PM_TMR) . . . . . . . . . . . . . . . . . . . . . . . . 79
4.8.3.4 PM2 Control (PM2_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.8.3.5 Processor Register Block (P_BLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.8.3.6 Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.8.3.7 Sleep Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.8.4 Generic Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.8.4.1 General-Purpose Event Register Blocks . . . . . . . . . . . . . . . . . . . . . . . . 85
4.8.4.2 Example Generic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5 ACPI Software Programming Model 90
5.1 Overview of the System Description Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . 90
5.1.1 Address Space Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.2 ACPI System Description Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.2.1 Reserved Bits and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.2.1.1 Reserved Bits and Software Components . . . . . . . . . . . . . . . . . . . . . . . 94
5.2.1.2 Reserved Values and Software Components . . . . . . . . . . . . . . . . . . . . . 94
5.2.1.3 Reserved Hardware Bits and Software Components . . . . . . . . . . . . . . . . . 94
5.2.1.4 Ignored Hardware Bits and Software Components . . . . . . . . . . . . . . . . . . 95
5.2.2 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.2.3 Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.2.3.1 Functional Fixed Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.2.3.2 Generic Address Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.2.4 Universally Unique Identiﬁers (UUIDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.5 Root System Description Pointer (RSDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.5.1 Finding the RSDP on IA-PC Systems . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.5.2 Finding the RSDP on UEFI Enabled Systems . . . . . . . . . . . . . . . . . . . . 98
5.2.5.3 Root System Description Pointer (RSDP) Structure . . . . . . . . . . . . . . . . . 99
5.2.6 System Description Table Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.2.7 Root System Description Table (RSDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.8 Extended System Description Table (XSDT) . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.9 Fixed ACPI Description Table (FADT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
iii5.2.9.1 Preferred PM Proﬁle System Types . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.2.9.2 System Type Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.2.9.3 IA-PC Boot Architecture Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.2.9.4 ARM Architecture Boot Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2.10 Firmware ACPI Control Structure (FACS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2.10.1 Global Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.2.11 Deﬁnition Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.2.11.1 Differentiated System Description Table (DSDT) . . . . . . . . . . . . . . . . . . 126
5.2.11.2 Secondary System Description Table (SSDT) . . . . . . . . . . . . . . . . . . . . . 126
5.2.11.3 Persistent System Description Table (PSDT) . . . . . . . . . . . . . . . . . . . . . 127
5.2.12 Multiple APIC Description Table (MADT) . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.2.12.1 MADT Processor Local APIC / SAPIC Structure Entry Order . . . . . . . . . . . . 130
5.2.12.2 Processor Local APIC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.2.12.3 I/O APIC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.2.12.4 Platforms with APIC and Dual 8259 Support . . . . . . . . . . . . . . . . . . . . . 131
5.2.12.5 Interrupt Source Override Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.2.12.6 Non-Maskable Interrupt (NMI) Source Structure . . . . . . . . . . . . . . . . . . . 133
5.2.12.7 Local APIC NMI Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.2.12.8 Local APIC Address Override Structure . . . . . . . . . . . . . . . . . . . . . . . 134
5.2.12.9 I/O SAPIC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.2.12.10 Local SAPIC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2.12.11 Platform Interrupt Source Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2.12.12 Processor Local x2APIC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.2.12.13 Local x2APIC NMI Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.2.12.14 GIC CPU Interface (GICC) Structure . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.2.12.15 GIC Distributor (GICD) Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.2.12.16 GIC MSI Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.2.12.17 GIC Redistributor (GICR) Structure . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2.12.18 GIC Interrupt Translation Service (ITS) Structure . . . . . . . . . . . . . . . . . . 142
5.2.12.19 Multiprocessor Wakeup Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2.12.20 Core Programmable Interrupt Controller (CORE PIC) Structure . . . . . . . . . . . 144
5.2.12.21 Legacy I/O Programmable Interrupt Controller(LIO PIC) Structure . . . . . . . . . 145
5.2.12.22 HyperTransport Programmable Interrupt Controller (HT PIC) Structure . . . . . . . 145
5.2.12.23 Extend I/O Programmable Interrupt Controller (EIO PIC) Structure . . . . . . . . . 146
5.2.12.24 MSI Programmable Interrupt Controller (MSI PIC) Structure . . . . . . . . . . . . 146
5.2.12.25 Bridge I/O Programmable Interrupt Controller (BIO PIC) Structure . . . . . . . . . 147
5.2.12.26 LPC Programmable Interrupt Controller (LPC PIC) Structure . . . . . . . . . . . . 147
5.2.13 Global System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.2.14 Smart Battery Table (SBST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.2.15 Embedded Controller Boot Resources Table (ECDT) . . . . . . . . . . . . . . . . . . . . . 151
5.2.16 System Resource Afﬁnity Table (SRAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.2.16.1 Processor Local APIC/SAPIC Afﬁnity Structure . . . . . . . . . . . . . . . . . . . 154
5.2.16.2 Memory Afﬁnity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.2.16.3 Processor Local x2APIC Afﬁnity Structure . . . . . . . . . . . . . . . . . . . . . . 155
5.2.16.4 GICC Afﬁnity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.2.16.5 GIC Interrupt Translation Service (ITS) Afﬁnity Structure . . . . . . . . . . . . . . 156
5.2.16.6 Generic Initiator Afﬁnity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.16.7 Generic Port Afﬁnity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.2.17 System Locality Information Table (SLIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.2.18 Corrected Platform Error Polling Table (CPEP) . . . . . . . . . . . . . . . . . . . . . . . . 160
5.2.18.1 Corrected Platform Error Polling Processor Structure . . . . . . . . . . . . . . . . 161
5.2.19 Maximum System Characteristics Table (MSCT) . . . . . . . . . . . . . . . . . . . . . . . 162
5.2.19.1 Maximum Proximity Domain Information Structure . . . . . . . . . . . . . . . . . 163
5.2.20 ACPI RAS Feature Table (RASF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
iv5.2.20.1 RASF PCC Sub Channel Identiﬁer . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2.20.2 Using PCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2.20.3 RASF Communication Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2.20.4 Platform RAS Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.2.20.5 Parameter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.2.21 ACPI RAS2 Feature Table (RAS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.2.21.1 Common Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.2.21.2 Memory RAS Features – Feature Type 0 . . . . . . . . . . . . . . . . . . . . . . . 171
5.2.22 Memory Power State Table (MPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.2.22.1 MPST PCC Sub Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.2.22.2 Memory Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
5.2.22.3 Action Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.2.22.4 Memory Power Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.2.22.5 Memory Power State Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.2.22.6 Memory Power State Characteristics structure . . . . . . . . . . . . . . . . . . . . 184
5.2.22.7 Autonomous Memory Power Management . . . . . . . . . . . . . . . . . . . . . . 185
5.2.22.8 Handling BIOS Reserved Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 186
5.2.22.9 Interaction with NUMA processor and memory afﬁnity tables . . . . . . . . . . . . 186
5.2.22.10 Interaction with Memory Hot Plug . . . . . . . . . . . . . . . . . . . . . . . . . . 186
5.2.22.11 OS Memory Allocation Considerations . . . . . . . . . . . . . . . . . . . . . . . . 187
5.2.22.12 Platform Memory Topology Table (PMTT) . . . . . . . . . . . . . . . . . . . . . . 187
5.2.23 Boot Graphics Resource Table (BGRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
5.2.23.1 Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.2.23.2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.2.23.3 Image Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.2.23.4 Image Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.2.23.5 Image Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.2.24 Firmware Performance Data Table (FPDT) . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.2.24.1 Performance Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
5.2.24.2 FPDT Performance Record Types . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.2.24.3 Runtime Performance Record Types . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.2.24.4 Firmware Basic Boot Performance Table Pointer Record . . . . . . . . . . . . . . . 195
5.2.24.5 S3 Performance Table Pointer Record . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.2.24.6 Firmware Basic Boot Performance Table . . . . . . . . . . . . . . . . . . . . . . . 196
5.2.24.7 Firmware Basic Boot Performance Data Record . . . . . . . . . . . . . . . . . . . 197
5.2.24.8 S3 Performance Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.2.25 Generic Timer Description Table (GTDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

5.2.25.1 GT Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.2.25.2 Arm Generic Watchdog Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.2.26 NVDIMM Firmware Interface Table (NFIT) . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.2.26.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.2.26.2 System Physical Address (SPA) Range Structure . . . . . . . . . . . . . . . . . . . 206
5.2.26.3 NVDIMM Region Mapping Structure . . . . . . . . . . . . . . . . . . . . . . . . 208
5.2.26.4 Interleave Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.2.26.5 SMBIOS Management Information Structure . . . . . . . . . . . . . . . . . . . . . 212
5.2.26.6 NVDIMM Control Region Structure . . . . . . . . . . . . . . . . . . . . . . . . . 212
5.2.26.7 NVDIMM Block Data Window Region Structure . . . . . . . . . . . . . . . . . . 215
5.2.26.8 Flush Hint Address Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.2.26.9 Platform Capabilities Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
5.2.26.10 NVDIMM Representation Format . . . . . . . . . . . . . . . . . . . . . . . . . . 217
5.2.27 Secure Devices (SDEV) ACPI Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.2.27.1 Secure Device Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.2.28 Heterogeneous Memory Attribute Table (HMAT) . . . . . . . . . . . . . . . . . . . . . . . 223
5.2.28.1 HMAT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
v5.2.28.2 Memory Side Cache Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.2.28.3 Memory Proximity Domain Attributes Structure . . . . . . . . . . . . . . . . . . . 224
5.2.28.4 System Locality Latency and Bandwidth Information Structure . . . . . . . . . . . 225
5.2.28.5 Memory Side Cache Information Structure . . . . . . . . . . . . . . . . . . . . . . 229
5.2.29 Platform Debug Trigger Table (PDTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
5.2.29.1 PDTT PCC Sub Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
5.2.29.2 PDTT PCC Trigger Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.2.29.3 Example: OS Invoking Multiple Debug Triggers . . . . . . . . . . . . . . . . . . . 234
5.2.30 Processor Properties Topology Table (PPTT) . . . . . . . . . . . . . . . . . . . . . . . . . 236
5.2.30.1 Processor hierarchy node structure (Type 0) . . . . . . . . . . . . . . . . . . . . . 237
5.2.30.2 Cache Type Structure - Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
5.2.31 Platform Health Assessment Table (PHAT) . . . . . . . . . . . . . . . . . . . . . . . . . . 243
5.2.31.1 Platform Health Assessment Record Format . . . . . . . . . . . . . . . . . . . . . 243
5.2.31.2 Platform Health Assessment Record Type Format . . . . . . . . . . . . . . . . . . 244
5.2.31.3 Firmware Version Data Record Structure . . . . . . . . . . . . . . . . . . . . . . . 244
5.2.31.4 Firmware Health Data Record Structure . . . . . . . . . . . . . . . . . . . . . . . 245
5.2.31.5 Reset Reason Health Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
5.2.32 Virtual I/O Translation (VIOT) Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.2.32.1 Virtual I/O Translation (VIOT) Table Header . . . . . . . . . . . . . . . . . . . . . 251
5.2.32.2 VIOT Node Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.2.32.3 PCI Range Node Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
5.2.32.4 Single MMIO Endpoint Node Structure . . . . . . . . . . . . . . . . . . . . . . . . 252
5.2.32.5 virtio-iommu based on virtio-pci Node Structure . . . . . . . . . . . . . . . . . . . 253
5.2.32.6 virtio-iommu based on virtio-mmioNode Structure . . . . . . . . . . . . . . . . . . 253
5.2.33 Miscellaneous GUIDed Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
5.2.34 CC Event Log ACPI Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
5.2.35 Storage V olume Key Location Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
5.3 ACPI Namespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
5.3.1 Predeﬁned Root Namespaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
5.3.2 Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
5.4 Deﬁnition Block Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
5.4.1 AML Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
5.4.2 Deﬁnition Block Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
5.5 Control Methods and the ACPI Source Language (ASL) . . . . . . . . . . . . . . . . . . . . . . . . 261
5.5.1 ASL Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.5.2 Control Method Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.5.2.1 Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.5.2.2 Method Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.5.2.3 Local Variables and Locally Created Data Objects . . . . . . . . . . . . . . . . . . 263
5.5.2.4 Access to Operation Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
5.6 ACPI Event Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
5.6.1 ACPI Event Programming Model Components . . . . . . . . . . . . . . . . . . . . . . . . 290
5.6.2 Types of ACPI Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
5.6.3 Fixed Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
5.6.4 General-Purpose Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
5.6.4.1 _Exx, _Lxx, and _Qxx Methods for GPE Processing . . . . . . . . . . . . . . . . . 293
5.6.4.2 GPE Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
5.6.5 GPIO-signaled ACPI Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
5.6.5.1 Declaring GPIO Controller Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 296
5.6.5.2 _AEI Object for GPIO-signaled Events . . . . . . . . . . . . . . . . . . . . . . . . 296
5.6.5.3 The Event (_EVT) Method for Handling GPIO-signaled Events . . . . . . . . . . . 297
5.6.6 Device Object Notiﬁcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
5.6.7 Device Class-Speciﬁc Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
5.6.8 Predeﬁned ACPI Names for Objects, Methods, and Resources . . . . . . . . . . . . . . . . 305
vi5.6.9 Interrupt-signaled ACPI events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
5.6.9.1 Declaring Generic Event Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
5.6.9.2 _CRS Object for Interrupt-signaled Events . . . . . . . . . . . . . . . . . . . . . . 312
5.6.9.3 The Event (_EVT) Method for Handling Interrupt-signaled Events . . . . . . . . . 313
5.6.9.4 GED Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
5.6.10 Managing a Wake Event Using Device _PRW Objects . . . . . . . . . . . . . . . . . . . . 315
5.7 Predeﬁned Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
5.7.1 \_GL (Global Lock Mutex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
5.7.2 \_OSI (Operating System Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
5.7.2.1 _OSI Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
5.7.3 \_OS (OS Name Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
5.7.4 \_REV (Revision Data Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
5.7.5 \_DLM (DeviceLock Mutex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
5.8 System Conﬁguration Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
5.8.1 \_PIC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
6 Device Conﬁguration 322
6.1 Device Identiﬁcation Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
6.1.1 _ADR (Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

6.1.2 _CID (Compatible ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
6.1.3 _CLS (Class Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
6.1.4 _DDN (DOS Device Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
6.1.5 _HID (Hardware ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
6.1.6 _HRV (Hardware Revision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
6.1.7 _MLS (Multiple Language String) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
6.1.8 _PLD (Physical Location of Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
6.1.9 _SUB (Subsystem ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
6.1.10 _STR (String) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.1.11 _SUN (Slot User Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.1.12 _UID (Unique ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.2 Device Conﬁguration Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.2.1 _CDM (Clock Domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
6.2.2 _CRS (Current Resource Settings) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
6.2.3 _DIS (Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
6.2.4 _DMA (Direct Memory Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
6.2.5 _DSD (Device Speciﬁc Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
6.2.6 _FIX (Fixed Register Resource Provider) . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
6.2.7 _GSB (Global System Interrupt Base) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
6.2.8 _HPP (Hot Plug Parameters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
6.2.9 _HPX (Hot Plug Parameter Extensions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
6.2.9.1 PCI Setting Record (Type 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
6.2.9.2 PCI-X Setting Record (Type 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
6.2.9.3 PCI Express Setting Record (Type 2) . . . . . . . . . . . . . . . . . . . . . . . . . 350
6.2.9.4 PCI Express Descriptor Setting Record (Type 3) . . . . . . . . . . . . . . . . . . . 352
6.2.9.5 _HPX Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
6.2.10 _MAT (Multiple APIC Table Entry) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
6.2.11 _OSC (Operating System Capabilities) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
6.2.11.1 Rules for Evaluating _OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
6.2.11.2 Platform-Wide OSPM Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 364
6.2.11.3 Operating System Capabilities (_OSC) for USB . . . . . . . . . . . . . . . . . . . 366
6.2.12 _PRS (Possible Resource Settings) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
6.2.13 _PRT (PCI Routing Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
6.2.13.1 Example: Using _PRT to Describe PCI IRQ Routing . . . . . . . . . . . . . . . . . 368
6.2.14 _PXM (Proximity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
vii6.2.15 _SLI (System Locality Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
6.2.16 _SRS (Set Resource Settings) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
6.2.17 _CCA (Cache Coherency Attribute) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
6.2.17.1 _CCA Example ASL: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
6.2.18 _HMA(Heterogeneous Memory Attributes) . . . . . . . . . . . . . . . . . . . . . . . . . . 375
6.3 Device Insertion, Removal, and Status Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
6.3.1 _EDL (Eject Device List) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
6.3.2 _EJD (Ejection Dependent Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
6.3.3 _EJx (Eject) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
6.3.4 _LCK (Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
6.3.5 _OST (OSPM Status Indication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
6.3.5.1 Processing Sequence for Graceful Shutdown Request: . . . . . . . . . . . . . . . . 381
6.3.5.2 Processing Sequence for Error Disconnect Recover . . . . . . . . . . . . . . . . . 385
6.3.6 _RMV (Remove) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
6.3.7 _STA (Device Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
6.4 Resource Data Types for ACPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
6.4.1 ASL Macros for Resource Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
6.4.2 Small Resource Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
6.4.2.1 IRQ Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
6.4.2.2 DMA Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
6.4.2.3 Start Dependent Functions Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 389
6.4.2.4 End Dependent Functions Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 390
6.4.2.5 I/O Port Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
6.4.2.6 Fixed Location I/O Port Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . 391
6.4.2.7 Fixed DMA Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
6.4.2.8 Vendor-Deﬁned Descriptor, Type 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 392
6.4.2.9 End Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
6.4.3 Large Resource Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
6.4.3.1 24-Bit Memory Range Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
6.4.3.2 Vendor-Deﬁned Descriptor, Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 395
6.4.3.3 32-Bit Memory Range Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
6.4.3.4 32-Bit Fixed Memory Range Descriptor . . . . . . . . . . . . . . . . . . . . . . . 397
6.4.3.5 Address Space Resource Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . 398
6.4.3.6 Extended Interrupt Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
6.4.3.7 Generic Register Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
6.4.3.8 Connection Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
6.4.3.9 Pin Function Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
6.4.3.10 Pin Conﬁguration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
6.4.3.11 Pin Group Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
6.4.3.12 Pin Group Function Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
6.4.3.13 Pin Group Conﬁguration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 430
6.4.3.14 Clock Input Resource Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
6.5 Other Objects and Control Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
6.5.1 _INI (Init) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
6.5.2 _DCK (Dock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
6.5.3 _BDN (BIOS Dock Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
6.5.4 _REG (Region) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
6.5.5 _BBN (Base Bus Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
6.5.6 _SEG (Segment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
6.5.7 _GLK (Global Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
6.5.8 _DEP (Operation Region Dependencies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
6.5.9 _FIT (Firmware Interface Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
6.5.10 NVDIMM Label Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

6.5.10.1 _LSI (Label Storage Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
viii6.5.10.2 _LSR (Label Storage Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
6.5.10.3 _LSW (Label Storage Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
6.5.11 _CBR (CXL Host Bridge Register Info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
7 Power and Performance Management 445
7.1 Power Resource Objects and the Power Management Models . . . . . . . . . . . . . . . . . . . . . 445
7.2 Declaring a Power Resource Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
7.2.1 Deﬁned Methods for a Power Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
7.2.2 _OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
7.2.3 _ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
7.2.4 _STA (Power Resource Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
7.2.5 Passive Power Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
7.3 Device Power Management Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
7.3.1 _DSW (Device Sleep Wake) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
7.3.2 _PS0 (Power State 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
7.3.3 _PS1 (Power State 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
7.3.4 _PS2 (Power State 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
7.3.5 _PS3 (Power State 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
7.3.6 _PSC (Power State Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
7.3.7 _PSE (Power State for Enumeration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
7.3.8 _PR0 (Power Resources for D0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
7.3.9 _PR1 (Power Resources for D1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
7.3.10 _PR2 (Power Resources for D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
7.3.11 _PR3 (Power Resources for D3hot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
7.3.12 _PRE (Power Resources for Enumeration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
7.3.13 _PRW (Power Resources for Wake) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
7.3.14 _PSW (Power State Wake) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
7.3.15 _IRC (In Rush Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
7.3.16 _S1D (S1 Device State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
7.3.17 _S2D (S2 Device State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
7.3.18 _S3D (S3 Device State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
7.3.19 _S4D (S4 Device State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
7.3.20 _S0W (S0 Device Wake State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
7.3.21 _S1W (S1 Device Wake State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
7.3.22 _S2W (S2 Device Wake State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
7.3.23 _S3W (S3 Device Wake State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
7.3.24 _S4W (S4 Device Wake State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
7.3.25 _RST (Device Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
7.3.26 _PRR (Power Resource for Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
7.3.27 _DSC (Deepest State for Conﬁguration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
7.4 OEM-Supplied System-Level Control Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
7.4.1 \_PTS (Prepare To Sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
7.4.2 \_Sx (System States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
7.4.2.1 System \_S0 State (Working) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
7.4.2.2 System \_S1 State (Sleeping with Processor Context Maintained) . . . . . . . . . . 467
7.4.2.3 System \_S2 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
7.4.2.4 System \_S3 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
7.4.2.5 System \_S4 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
7.4.2.6 System \_S5 State (Soft Off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
7.4.3 \_SWS (System Wake Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
7.4.4 \_TTS (Transition To State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
7.4.5 \_WAK (System Wake) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
7.5 OSPM usage of _PTS, _TTS, and _WAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
ix8 Processor Conﬁguration and Control 473
8.1 Processor Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
8.1.1 Processor Power State C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
8.1.2 Processor Power State C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
8.1.3 Processor Power State C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
8.1.4 Processor Power State C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
8.1.5 Additional Processor Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
8.2 Flushing Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
8.3 Power, Performance, and Throttling State Dependencies . . . . . . . . . . . . . . . . . . . . . . . . 479
8.4 Declaring Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
8.4.1 Processor Power State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
8.4.1.1 _CST (C States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
8.4.1.2 _CSD (C-State Dependency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
8.4.2 Processor Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
8.4.2.1 Processor Container Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
8.4.3 Lower Power Idle States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
8.4.3.1 Hierarchical Idle States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
8.4.3.2 Idle State Coordination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
8.4.3.3 _LPI (Low Power Idle States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
8.4.3.4 _RDI (Resource Dependencies for Idle) . . . . . . . . . . . . . . . . . . . . . . . 506
8.4.3.5 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
8.4.4 Processor Throttling Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
8.4.4.1 _PTC (Processor Throttling Control) . . . . . . . . . . . . . . . . . . . . . . . . . 510
8.4.4.2 _TSS (Throttling Supported States) . . . . . . . . . . . . . . . . . . . . . . . . . . 511
8.4.4.3 _TPC (Throttling Present Capabilities) . . . . . . . . . . . . . . . . . . . . . . . . 512
8.4.4.4 _TSD (T-State Dependency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
8.4.4.5 _TDL (T-state Depth Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
8.4.5 Processor Performance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
8.4.5.1 _PCT (Performance Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
8.4.5.2 _PSS (Performance Supported States) . . . . . . . . . . . . . . . . . . . . . . . . 518
8.4.5.3 _PPC (Performance Present Capabilities) . . . . . . . . . . . . . . . . . . . . . . . 519
8.4.5.4 Processor Performance Control Example . . . . . . . . . . . . . . . . . . . . . . . 519
8.4.5.5 _PSD (P-State Dependency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
8.4.5.6 _PDL (P-state Depth Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
8.4.6 Collaborative Processor Performance Control . . . . . . . . . . . . . . . . . . . . . . . . . 523

8.4.6.1 _CPC (Continuous Performance Control) . . . . . . . . . . . . . . . . . . . . . . . 524
8.4.7 _PPE (Polling for Platform Errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
8.5 Processor Aggregator Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
8.5.1 Logical Processor Idling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
8.5.1.1 _PUR (Processor Utilization Request) . . . . . . . . . . . . . . . . . . . . . . . . 540
8.5.2 OSPM _OST Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
9 ACPI-Deﬁned Devices and Device-Speciﬁc Objects 542
9.1 Device Object Name Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
9.1.1 _DSM (Device Speciﬁc Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
9.2 \_SI System Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
9.2.1 _SST (System Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
9.2.2 _MSG (Message) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
9.2.3 _BLT (Battery Level Threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
9.3 Ambient Light Sensor Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
9.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
9.3.2 _ALI (Ambient Light Illuminance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
9.3.3 _ALT (Ambient Light Temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
9.3.4 _ALC (Ambient Light Color Chromaticity) . . . . . . . . . . . . . . . . . . . . . . . . . . 548
x9.3.5 _ALR (Ambient Light Response) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
9.3.6 _ALP (Ambient Light Polling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
9.3.7 Ambient Light Sensor Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
9.3.8 Relationship to Backlight Control Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 553
9.4 Control Method Lid Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
9.4.1 _LID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
9.5 Control Method Power and Sleep Button Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
9.6 Generic Container Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
9.7 ATA Controller Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
9.7.1 Objects for Both ATA and SATA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . 555
9.7.1.1 _GTF (Get Task File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
9.7.2 IDE Controller Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
9.7.2.1 IDE Controller-speciﬁc Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
9.7.3 Serial ATA (SATA) Controller Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
9.7.3.1 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
9.7.3.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
9.7.3.3 SATA controller-speciﬁc control methods . . . . . . . . . . . . . . . . . . . . . . . 559
9.8 Floppy Controller Device Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
9.8.1 _FDE (Floppy Disk Enumerate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
9.8.2 _FDI (Floppy Disk Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
9.8.3 _FDM (Floppy Disk Drive Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
9.9 GPE Block Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
9.9.1 Matching Control Methods for Events in a GPE Block Device . . . . . . . . . . . . . . . . 563
9.10 Module Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
9.11 Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
9.11.1 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
9.11.2 Memory Bandwidth Monitoring and Reporting . . . . . . . . . . . . . . . . . . . . . . . . 566
9.11.2.1 _MBM (Memory Bandwidth Monitoring Data) . . . . . . . . . . . . . . . . . . . . 567
9.11.2.2 _MSM (Memory Set Monitoring) . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
9.11.3 _OSC Deﬁnition for Memory Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
9.11.4 Example: Memory Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
9.12 _UPC (USB Port Capabilities) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
9.12.1 USB 2.0 Host Controllers and _UPC and _PLD . . . . . . . . . . . . . . . . . . . . . . . . 574
9.12.2 SuperSpeed USB Port and Connector Mapping . . . . . . . . . . . . . . . . . . . . . . . . 576
9.12.3 USB4 Port and USB-C Connector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 576
9.13 _PDO (USB Power Data Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
9.14 PC/AT RTC/CMOS Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
9.14.1 PC/AT-compatible RTC/CMOS Devices (PNP0B00) . . . . . . . . . . . . . . . . . . . . . 581
9.14.2 Intel PIIX4-compatible RTC/CMOS Devices (PNP0B01) . . . . . . . . . . . . . . . . . . . 582
9.14.3 Dallas Semiconductor-compatible RTC/CMOS Devices (PNP0B02) . . . . . . . . . . . . . 583
9.15 User Presence Detection Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
9.15.1 _UPD (User Presence Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
9.15.2 _UPP (User Presence Polling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
9.15.3 User Presence Sensor Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
9.16 I/O APIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
9.17 Time and Alarm Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
9.17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
9.17.2 _GCP (Get Capability) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
9.17.3 _GRT (Get Real Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
9.17.4 _SRT (Set Real Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
9.17.5 _GWS (Get Wake alarm status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
9.17.6 _CWS (Clear Wake alarm status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
9.17.7 _STP (Set Expired Timer Wake Policy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
9.17.8 _STV (Set Timer Value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
xi9.17.9 _TIP (Expired Timer Wake Policy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
9.17.10 _TIV (Timer Values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
9.17.11 ACPI Wakeup Alarm Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
9.17.12 Relationship to Real Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
9.17.13 Time and Alarm device as a replacement to the RTC . . . . . . . . . . . . . . . . . . . . . 593
9.17.14 Relationship to UEFI time source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
9.17.15 Example ASL code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
9.18 Generic Buttons Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
9.18.1 Button Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
9.18.2 Button Usages and Collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
9.18.3 Generic Buttons Device Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
9.19 NVDIMM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
9.19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

9.19.2 NVDIMM Root Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
9.19.3 NVDIMM Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
9.19.4 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
9.19.5 Loading NVDIMM drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
9.19.6 Hot Plug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
9.19.7 NVDIMM Root Device _DSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
9.19.7.1 Input Parameters: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
9.19.7.2 Address Range Scrubbing (ARS) Overview . . . . . . . . . . . . . . . . . . . . . 604
9.19.7.3 Address Range Scrub (ARS) Error Injection Overview . . . . . . . . . . . . . . . . 605
9.19.7.4 Function Index 1 - Query ARS Capabilities . . . . . . . . . . . . . . . . . . . . . . 606
9.19.7.5 Function Index 2 - Start ARS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
9.19.7.6 Function Index 3 - Query ARS Status . . . . . . . . . . . . . . . . . . . . . . . . . 609
9.19.7.7 Function Index 4 - Clear Uncorrectable Error . . . . . . . . . . . . . . . . . . . . . 611
9.19.7.8 Function Index 5 - Translate SPA . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
9.19.7.9 Function Index 7 - ARS Error Inject . . . . . . . . . . . . . . . . . . . . . . . . . 614
9.19.7.10 Function Index 8 - ARS Error Inject Clear . . . . . . . . . . . . . . . . . . . . . . 616
9.19.7.11 Function Index 9 - ARS Error Inject Status Query . . . . . . . . . . . . . . . . . . 616
9.19.7.12 Function Index 0xA - Query ARS Error Inject Capabilities . . . . . . . . . . . . . 617
9.19.8 NVDIMM Device Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
9.19.8.1 _NCH (Get NVDIMM Current Health Information) . . . . . . . . . . . . . . . . . 619
9.19.8.2 _NBS (Get NVDIMM Boot Status) . . . . . . . . . . . . . . . . . . . . . . . . . . 621
9.19.8.3 _NIC (Get NVDIMM Health Error Injection Capabilities) . . . . . . . . . . . . . . 621
9.19.8.4 _NIH (NVDIMM Inject/Clear Health Errors) . . . . . . . . . . . . . . . . . . . . . 622
9.19.8.5 _NIG (Get NVDIMM Inject Health Error Status) . . . . . . . . . . . . . . . . . . 624
10 Power Source and Power Meter Devices 626
10.1 Smart Battery Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
10.1.1 ACPI Smart Battery Status Change Notiﬁcation Requirements . . . . . . . . . . . . . . . . 628
10.1.1.1 Smart Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
10.1.1.2 Smart Battery Charger with optional System Manager or Selector . . . . . . . . . . 629
10.1.1.3 Smart Battery System Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
10.1.1.4 Smart Battery Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
10.1.2 Smart Battery Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
10.1.3 _SBS (Smart Battery Subsystem) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
10.1.3.1 Example: Single Smart Battery Subsystem . . . . . . . . . . . . . . . . . . . . . . 630
10.1.3.2 Multiple Smart Battery Subsystem: Example . . . . . . . . . . . . . . . . . . . . . 631
10.2 Control Method Batteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
10.2.1 Battery Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
10.2.2 Battery Control Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
10.2.2.1 _BCT (Battery Charge Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
10.2.2.2 _BIF (Battery Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
xii10.2.2.3 _BIX (Battery Information Extended) . . . . . . . . . . . . . . . . . . . . . . . . . 637
10.2.2.4 _BMA (Battery Measurement Averaging Interval) . . . . . . . . . . . . . . . . . . 640
10.2.2.5 _BMC (Battery Maintenance Control) . . . . . . . . . . . . . . . . . . . . . . . . 641
10.2.2.6 _BMD (Battery Maintenance Data) . . . . . . . . . . . . . . . . . . . . . . . . . . 642
10.2.2.7 _BMS (Battery Measurement Sampling Time) . . . . . . . . . . . . . . . . . . . . 645
10.2.2.8 _BPC (Battery Power Characteristics) . . . . . . . . . . . . . . . . . . . . . . . . 645
10.2.2.9 _BPS (Battery Power State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
10.2.2.10 _BPT (Battery Power Threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
10.2.2.11 _BST (Battery Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
10.2.2.12 _BTH (Battery Throttle Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
10.2.2.13 _BTM (Battery Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
10.2.2.14 _BTP (Battery Trip Point) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
10.2.2.15 _OSC Deﬁnition for Control Method Battery . . . . . . . . . . . . . . . . . . . . . 652
10.3 AC Adapters and Power Source Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
10.3.1 _PSR (Power Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
10.3.2 _PCL (Power Consumer List) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
10.3.3 _PIF (Power Source Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
10.3.4 _PRL (Power Source Redundancy List) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
10.4 Power Meters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
10.4.1 _PMC (Power Meter Capabilities) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
10.4.2 _PTP (Power Trip Points) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
10.4.3 _PMM (Power Meter Measurement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
10.4.4 _PAI (Power Averaging Interval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
10.4.5 _GAI (Get Averaging Interval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
10.4.6 _SHL (Set Hardware Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
10.4.7 _GHL (Get Hardware Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
10.4.8 _PMD (Power Metered Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
10.5 Wireless Power Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
10.5.1 Wireless Power Calibration Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
10.5.2 Wireless Power Calibration (_WPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
10.5.3 Wireless Power Polling (_WPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
10.6 Wireless Power Calibration Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
10.7 Example: Power Source and Power Meter Namespace . . . . . . . . . . . . . . . . . . . . . . . . . 662
11 Thermal Management 663
11.1 Thermal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
11.1.1 Active, Passive, and Critical Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
11.1.2 Dynamically Changing Cooling Temperature Trip Points . . . . . . . . . . . . . . . . . . . 665
11.1.2.1 OSPM Change of Cooling Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
11.1.2.2 Resetting Cooling Temperatures to Adjust to Bay Device Insertion or Removal . . . 666
11.1.2.3 Resetting Cooling Temperatures to Implement Hysteresis . . . . . . . . . . . . . . 666
11.1.3 Detecting Temperature Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
11.1.3.1 Temperature Change Notiﬁcations . . . . . . . . . . . . . . . . . . . . . . . . . . 667
11.1.3.2 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
11.1.4 Active Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
11.1.5 Passive Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
11.1.5.1 Processor Clock Throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
11.1.6 Critical Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
11.2 Cooling Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
11.2.1 Evaluating Thermal Device Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

11.2.2 Evaluating Device Thermal Relationship Information . . . . . . . . . . . . . . . . . . . . . 672
11.2.3 Fan Device Notiﬁcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
11.3 Fan Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
11.3.1 Fan Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
xiii11.3.1.1 _FIF (Fan Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
11.3.1.2 _FPS (Fan Performance States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
11.3.1.3 _FSL (Fan Set Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
11.3.1.4 _FST (Fan Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
11.4 Thermal Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
11.4.1 _ACx (Active Cooling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
11.4.2 _ALx (Active List) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
11.4.3 _ART (Active Cooling Relationship Table) . . . . . . . . . . . . . . . . . . . . . . . . . . 678
11.4.4 _CRT (Critical Temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
11.4.5 _CR3 (Warm/Standby Temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
11.4.6 _DTI (Device Temperature Indication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
11.4.7 _HOT (Hot Temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
11.4.8 _MTL (Minimum Throttle Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
11.4.9 _NTT (Notiﬁcation Temperature Threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . 682
11.4.10 _PSL (Passive List) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
11.4.11 _PSV (Passive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
11.4.12 _RTV (Relative Temperature Values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
11.4.13 _SCP (Set Cooling Policy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
11.4.14 _STR (String) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
11.4.15 _TC1 (Thermal Constant 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
11.4.16 _TC2 (Thermal Constant 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
11.4.17 _TFP (Thermal fast Sampling Period) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
11.4.18 _TMP (Temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
11.4.19 _TPT (Trip Point Temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
11.4.20 _TRT (Thermal Relationship Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
11.4.21 _TSN (Thermal Sensor Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
11.4.22 _TSP (Thermal Sampling Period) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
11.4.23 _TST (Temperature Sensor Threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
11.4.24 _TZD (Thermal Zone Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
11.4.25 _TZM (Thermal Zone Member) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
11.4.26 _TZP (Thermal Zone Polling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
11.5 Native OS Device Driver Thermal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
11.6 Thermal Zone Interface Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
11.7 Thermal Zone Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
11.7.1 Example: The Basic Thermal Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
11.7.2 Example: Multiple-Speed Fans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
11.7.3 Example: Thermal Zone with Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . 696
12 ACPI Embedded Controller Interface Speciﬁcation 701
12.1 Embedded Controller Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
12.2 Embedded Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
12.2.1 Embedded Controller Status, EC_SC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
12.2.2 Embedded Controller Command, EC_SC (W) . . . . . . . . . . . . . . . . . . . . . . . . . 706
12.2.3 Embedded Controller Data, EC_DATA (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . 706
12.3 Embedded Controller Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
12.3.1 Read Embedded Controller, RD_EC (0x80) . . . . . . . . . . . . . . . . . . . . . . . . . . 706
12.3.2 Write Embedded Controller, WR_EC (0x81) . . . . . . . . . . . . . . . . . . . . . . . . . 706
12.3.3 Burst Enable Embedded Controller, BE_EC (0x82) . . . . . . . . . . . . . . . . . . . . . . 707
12.3.4 Burst Disable Embedded Controller, BD_EC (0x83) . . . . . . . . . . . . . . . . . . . . . 707
12.3.5 Query Embedded Controller, QR_EC (0x84) . . . . . . . . . . . . . . . . . . . . . . . . . 707
12.4 SMBus Host Controller Notiﬁcation Header (Optional), OS_SMB_EVT . . . . . . . . . . . . . . . 708
12.5 Embedded Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
12.6 Interrupt Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
12.6.1 Event Interrupt Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
xiv12.6.2 Command Interrupt Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
12.7 Embedded Controller Interfacing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
12.8 Embedded Controller Description Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
12.9 SMBus Host Controller Interface via Embedded Controller . . . . . . . . . . . . . . . . . . . . . . 711
12.9.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
12.9.1.1 Status Register, SMB_STS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
12.9.1.2 Protocol Register, SMB_PRTCL . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
12.9.1.3 Address Register, SMB_ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
12.9.1.4 Command Register, SMB_CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
12.9.1.5 Data Register Array, SMB_DATA[i], i=0-31 . . . . . . . . . . . . . . . . . . . . . 714
12.9.1.6 Block Count Register, SMB_BCNT . . . . . . . . . . . . . . . . . . . . . . . . . . 714
12.9.1.7 Alarm Address Register, SMB_ALRM_ADDR . . . . . . . . . . . . . . . . . . . 714
12.9.1.8 Alarm Data Registers, SMB_ALRM_DATA[0], SMB_ALRM_DATA[1] . . . . . . 715
12.9.2 Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
12.9.2.1 Write Quick . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
12.9.2.2 Read Quick . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
12.9.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
12.9.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
12.9.2.5 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
12.9.2.6 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
12.9.2.7 Write Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
12.9.2.8 Read Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
12.9.2.9 Write Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
12.9.2.10 Read Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
12.9.2.11 Process Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
12.9.2.12 Block Write-Block Read Process Call . . . . . . . . . . . . . . . . . . . . . . . . 719
12.9.2.13 SMBus Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
12.10 SMBus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
12.10.1 SMBus Device Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

12.10.2 SMBus Device Command Access Restriction . . . . . . . . . . . . . . . . . . . . . . . . . 721
12.11 Deﬁning an Embedded Controller Device in ACPI Namespace . . . . . . . . . . . . . . . . . . . . . 721
12.11.1 Example: EC Deﬁnition ASL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
12.12 Deﬁning an EC SMBus Host Controller in ACPI Namespace . . . . . . . . . . . . . . . . . . . . . . 723
12.12.1 Example: EC SMBus Host Controller ASL-Code . . . . . . . . . . . . . . . . . . . . . . . 724
13 ACPI System Management Bus Interface Speciﬁcation 725
13.1 SMBus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
13.1.1 SMBus Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
13.1.2 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
13.1.3 SMBus Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
13.1.4 SMBus Command Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
13.2 Accessing the SMBus from ASL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
13.2.1 Declaring SMBus Host Controller Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
13.2.2 Declaring SMBus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
13.2.3 Declaring SMBus Operation Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
13.2.4 Declaring SMBus Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
13.2.5 Declaring and Using an SMBus Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 731
13.3 Using the SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
13.3.1 Read/Write Quick (SMBQuick) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
13.3.2 Send/Receive Byte (SMBSendReceive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
13.3.3 Read/Write Byte (SMBByte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
13.3.4 Read/Write Word (SMBWord) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
13.3.5 Read/Write Block (SMBBlock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
13.3.6 Word Process Call (SMBProcessCall) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
xv13.3.7 Block Process Call (SMBBlockProcessCall) . . . . . . . . . . . . . . . . . . . . . . . . . . 737
14 Platform Communications Channel (PCC) 738
14.1 Platform Communications Channel Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
14.1.1 Platform Communications Channel Global Flags . . . . . . . . . . . . . . . . . . . . . . . 739
14.1.2 Platform Communications Channel Subspace Structures . . . . . . . . . . . . . . . . . . . 739
14.1.3 Generic Communications Subspace Structure (type 0) . . . . . . . . . . . . . . . . . . . . . 740
14.1.4 HW-Reduced Communications Subspace Structure (type 1) . . . . . . . . . . . . . . . . . . 740
14.1.5 HW-Reduced Communications Subspace Structure (type 2) . . . . . . . . . . . . . . . . . . 742
14.1.6 Extended PCC subspaces (types 3 and 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
14.1.7 HW Registers based Communications Subspace Structure (Type 5) . . . . . . . . . . . . . . 745
14.2 Generic Communications Channel Shared Memory Region . . . . . . . . . . . . . . . . . . . . . . 747
14.2.1 Generic Communications Channel Command Field . . . . . . . . . . . . . . . . . . . . . . 747
14.2.2 Generic Communications Channel Status Field . . . . . . . . . . . . . . . . . . . . . . . . 747
14.3 Extended PCC Subspace Shared Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
14.4 Reduced PCC Subspace Shared Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
14.5 Doorbell Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
14.6 Platform Notiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
14.6.1 Platform Notiﬁcation for Subspace Types 0, 1 and 2 . . . . . . . . . . . . . . . . . . . . . . 751
14.6.2 Platform Notiﬁcation for Responder PCC subspaces (type 4) . . . . . . . . . . . . . . . . . 752
14.7 Referencing the PCC address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
15 System Address Map Interfaces 754
15.1 INT 15H, E820H - Query System Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
15.2 E820 Assumptions and Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
15.3 UEFI GetMemoryMap() Boot Services Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
15.4 UEFI Assumptions and Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
15.5 Example Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
15.6 Example: Operating System Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
16 Waking and Sleeping 762
16.1 Sleeping States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
16.1.1 S1 Sleeping State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
16.1.1.1 Example 1: S1 Sleeping State Implementation . . . . . . . . . . . . . . . . . . . . 765
16.1.1.2 Example 2: S1 Sleeping State Implementation . . . . . . . . . . . . . . . . . . . . 766
16.1.2 S2 Sleeping State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
16.1.2.1 Example: S2 Sleeping State Implementation . . . . . . . . . . . . . . . . . . . . . 766
16.1.3 S3 Sleeping State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
16.1.3.1 Example: S3 Sleeping State Implementation . . . . . . . . . . . . . . . . . . . . . 767
16.1.4 S4 Sleeping State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
16.1.4.1 Operating System-Initiated S4 Transition . . . . . . . . . . . . . . . . . . . . . . . 768
16.1.4.2 The S4BIOS Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
16.1.5 S5 Soft Off State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
16.1.6 Transitioning from the Working to the Sleeping State . . . . . . . . . . . . . . . . . . . . . 769
16.1.7 Transitioning from the Working to the Soft Off State . . . . . . . . . . . . . . . . . . . . . 770
16.2 Flushing Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
16.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
16.3.1 Placing the System in ACPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
16.3.2 Platform Boot Firmware Initialization of Memory . . . . . . . . . . . . . . . . . . . . . . . 773
16.3.3 OS Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
16.3.4 Exiting ACPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
17 Non-Uniform Memory Access (NUMA) Architecture Platforms 778
17.1 NUMA Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
17.2 System Locality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
xvi17.2.1 System Resource Afﬁnity Table Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
17.2.2 System Resource Afﬁnity Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
17.3 System Locality Distance Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
17.3.1 Online Hot Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
17.3.2 Impact to Existing Localities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
17.4 Heterogeneous Memory Attributes Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
17.4.1 Online Hot Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
17.4.2 Impact to Existing Localities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
18 ACPI Platform Error Interfaces (APEI) 782
18.1 Hardware Errors and Error Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
18.2 Relationship between OSPM and System Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
18.3 Error Source Discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
18.3.1 Boot Error Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

18.3.2 ACPI Error Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
18.3.2.1 IA-32 Architecture Machine Check Exception . . . . . . . . . . . . . . . . . . . . 785
18.3.2.2 IA-32 Architecture Corrected Machine Check . . . . . . . . . . . . . . . . . . . . 787
18.3.2.3 IA-32 Architecture Non-Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . 788
18.3.2.4 PCI Express Root Port AER Structure . . . . . . . . . . . . . . . . . . . . . . . . 788
18.3.2.5 PCI Express Device AER Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 790
18.3.2.6 PCI Express/PCI-X Bridge AER Structure . . . . . . . . . . . . . . . . . . . . . . 791
18.3.2.7 Generic Hardware Error Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
18.3.2.8 Generic Hardware Error Source version 2 (GHESv2 - Type 10) . . . . . . . . . . . 797
18.3.2.9 Hardware Error Notiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
18.3.2.10 IA-32 Architecture Deferred Machine Check . . . . . . . . . . . . . . . . . . . . . 800
18.3.2.11 Error Source Structure Header (Type 12 Onward) . . . . . . . . . . . . . . . . . . 801
18.4 Firmware First Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
18.4.1 Example: Firmware First Handling Using NMI Notiﬁcation . . . . . . . . . . . . . . . . . 802
18.5 Error Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
18.5.1 Serialization Action Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
18.5.1.1 Serialization Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
18.5.1.2 Serialization Instruction Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
18.5.1.3 Error Record Serialization Information . . . . . . . . . . . . . . . . . . . . . . . . 808
18.5.2 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
18.5.2.1 Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
18.5.2.2 Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
18.5.2.3 Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
18.5.2.4 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
18.6 Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
18.6.1 Error Injection Table (EINJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
18.6.2 Injection Instruction Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
18.6.3 Injection Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
18.6.4 Error Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
18.6.4.1 EINJv2 Error Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
18.6.5 Trigger Action Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
18.6.6 Error Injection Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
18.6.7 Error Injection Version 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
18.7 GHES_ASSIST Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
18.7.1 GHES_ASSIST on Machine Check Architecture . . . . . . . . . . . . . . . . . . . . . . . 825
19 ACPI Source Language (ASL) Reference 826
19.1 ASL 2.0 Symbolic Operators and Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
19.2 ASL Language Grammar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
19.2.1 ASL Grammar Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
xvii19.2.2 ASL Name and Pathname Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
19.2.3 ASL Root and Secondary Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
19.2.4 ASL Data and Constant Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
19.2.5 ASL Opcode Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
19.2.6 ASL Primary (Terminal) Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
19.2.7 ASL Parameter Keyword Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
19.2.8 ASL Resource Template Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
19.3 ASL Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
19.3.1 ASL Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
19.3.1.1 _T_x Reserved Object Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
19.3.2 ASL Literal Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
19.3.2.1 Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
19.3.2.2 Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
19.3.3 ASL Resource Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
19.3.4 ASL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
19.3.5 ASL Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
19.3.5.1 Data Type Conversion Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
19.3.5.2 Explicit Data Type Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
19.3.5.3 Implicit Data Type Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
19.3.5.4 Implicit Source Operand Conversion . . . . . . . . . . . . . . . . . . . . . . . . . 869
19.3.5.5 Implicit Result Object Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . 870
19.3.5.6 Data Types and Type Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
19.3.5.7 Data Type Conversion Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
19.3.5.8 Rules for Storing and Copying Objects . . . . . . . . . . . . . . . . . . . . . . . . 874
19.4 ASL Operators Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
19.5 ASL Operator Summary by Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
19.6 ASL Operator Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
19.6.1 AccessAs (Change Field Unit Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
19.6.2 Acquire (Acquire a Mutex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
19.6.3 Add (Integer Add) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
19.6.4 Alias (Declare Name Alias) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
19.6.5 And (Integer Bitwise And) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
19.6.6 Argx (Method Argument Data Objects) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
19.6.7 BankField (Declare Bank/Data Field) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
19.6.8 Break (Break from While) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
19.6.9 BreakPoint (Execution Break Point) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
19.6.10 Buffer (Declare Buffer Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
19.6.11 Case (Expression for Conditional Execution) . . . . . . . . . . . . . . . . . . . . . . . . . 890
19.6.12 Concatenate (Concatenate Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
19.6.13 ConcatenateResTemplate (Concatenate Resource Templates) . . . . . . . . . . . . . . . . . 891
19.6.14 CondRefOf (Create Object Reference Conditionally) . . . . . . . . . . . . . . . . . . . . . 892
19.6.15 Connection (Declare Field Connection Attributes) . . . . . . . . . . . . . . . . . . . . . . . 892
19.6.16 Continue (Continue Innermost Enclosing While) . . . . . . . . . . . . . . . . . . . . . . . 893
19.6.17 CopyObject (Copy and Store Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
19.6.18 CreateBitField (Create 1-Bit Buffer Field) . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
19.6.19 CreateByteField (Create 8-Bit Buffer Field) . . . . . . . . . . . . . . . . . . . . . . . . . . 894
19.6.20 CreateDWordField (Create 32-Bit Buffer Field) . . . . . . . . . . . . . . . . . . . . . . . . 894
19.6.21 CreateField (Create Arbitrary Length Buffer Field) . . . . . . . . . . . . . . . . . . . . . . 894

19.6.22 CreateQWordField (Create 64-Bit Buffer Field) . . . . . . . . . . . . . . . . . . . . . . . . 895
19.6.23 CreateWordField (Create 16-Bit Buffer Field) . . . . . . . . . . . . . . . . . . . . . . . . . 895
19.6.24 CSI2Bus (CSI-2 Serial Bus Connection Resource Descriptor Macro) . . . . . . . . . . . . . 895
19.6.25 DataTableRegion (Create Data Table Operation Region) . . . . . . . . . . . . . . . . . . . 896
19.6.26 Debug (Debugger Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
19.6.27 Decrement (Integer Decrement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
xviii19.6.28 Default (Default Execution Path in Switch) . . . . . . . . . . . . . . . . . . . . . . . . . . 897
19.6.29 DeﬁnitionBlock (Declare Deﬁnition Block) . . . . . . . . . . . . . . . . . . . . . . . . . . 897
19.6.30 DerefOf (Dereference an Object Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . 898
19.6.31 Device (Declare Device Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
19.6.32 Divide (Integer Divide) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
19.6.33 DMA (DMA Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
19.6.34 DWordIO (DWord IO Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . 900
19.6.35 DWordMemory (DWord Memory Resource Descriptor Macro) . . . . . . . . . . . . . . . . 902
19.6.36 DWordSpace (DWord Space Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . 903
19.6.37 EISAID (EISA ID String To Integer Conversion Macro) . . . . . . . . . . . . . . . . . . . 905
19.6.38 Else (Alternate Execution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
19.6.39 ElseIf (Alternate/Conditional Execution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
19.6.40 EndDependentFn (End Dependent Function Resource Descriptor Macro) . . . . . . . . . . 907
19.6.41 Event (Declare Event Synchronization Object) . . . . . . . . . . . . . . . . . . . . . . . . . 907
19.6.42 ExtendedIO (Extended IO Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . 907
19.6.43 ExtendedMemory (Extended Memory Resource Descriptor Macro) . . . . . . . . . . . . . 908
19.6.44 ExtendedSpace (Extended Address Space Resource Descriptor Macro) . . . . . . . . . . . . 910
19.6.45 External (Declare External Objects) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
19.6.46 Fatal (Fatal Error Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
19.6.47 Field (Declare Field Objects) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
19.6.48 FindSetLeftBit (Find First Set Left Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
19.6.49 FindSetRightBit (Find First Set Right Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
19.6.50 FixedDMA (DMA Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . 915
19.6.51 FixedIO (Fixed IO Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . 915
19.6.52 For (Conditional Loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
19.6.53 Fprintf (Create and Store formatted string) . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
19.6.54 FromBCD (Convert BCD To Integer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
19.6.55 Function (Declare Control Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
19.6.56 GpioInt (GPIO Interrupt Connection Resource Descriptor Macro) . . . . . . . . . . . . . . 918
19.6.57 GpioIo (GPIO Connection IO Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . 919
19.6.58 I2CSerialBusV2 (I2C Serial Bus Connection Resource Descriptor (Version 2) Macro) . . . . 920
19.6.59 If (Conditional Execution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
19.6.60 Include (Include Additional ASL File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
19.6.61 Increment (Integer Increment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
19.6.62 Index (Indexed Reference To Member Object) . . . . . . . . . . . . . . . . . . . . . . . . . 922
19.6.62.1 Index with Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
19.6.62.2 Index with Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
19.6.62.3 Index with Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
19.6.63 IndexField (Declare Index/Data Fields) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
19.6.64 Interrupt (Interrupt Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . 925
19.6.65 IO (IO Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
19.6.66 IRQ (Interrupt Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . . . 928
19.6.67 IRQNoFlags (Interrupt Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . 928
19.6.68 LAnd (Logical And) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
19.6.69 LEqual (Logical Equal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
19.6.70 LGreater (Logical Greater) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
19.6.71 LGreaterEqual (Logical Greater Than Or Equal) . . . . . . . . . . . . . . . . . . . . . . . . 930
19.6.72 LLess (Logical Less) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
19.6.73 LLessEqual (Logical Less Than Or Equal) . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
19.6.74 LNot (Logical Not) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
19.6.75 LNotEqual (Logical Not Equal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
19.6.76 Load (Load Deﬁnition Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
19.6.77 LoadTable (Load Deﬁnition Block From XSDT) . . . . . . . . . . . . . . . . . . . . . . . 932
19.6.78 Localx (Method Local Data Objects) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
xix19.6.79 LOr (Logical Or) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
19.6.80 Match (Find Object Match) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
19.6.81 Memory24 (Memory Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . 934
19.6.82 Memory32 (Memory Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . 935
19.6.83 Memory32Fixed (Memory Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . 936
19.6.84 Method (Declare Control Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
19.6.85 Mid (Extract Portion of Buffer or String) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
19.6.86 Mod (Integer Modulo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
19.6.87 Multiply (Integer Multiply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
19.6.88 Mutex (Declare Synchronization/Mutex Object) . . . . . . . . . . . . . . . . . . . . . . . . 939
19.6.89 Name (Declare Named Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
19.6.90 NAnd (Integer Bitwise Nand) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
19.6.91 NoOp Code (No Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
19.6.92 NOr (Integer Bitwise Nor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
19.6.93 Not (Integer Bitwise Not) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
19.6.94 Notify (Notify Object of Event) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
19.6.95 Offset (Change Current Field Unit Offset) . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
19.6.96 ObjectType (Get Object Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
19.6.97 One (Constant One Integer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
19.6.98 Ones (Constant Ones Integer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
19.6.99 OperationRegion (Declare Operation Region) . . . . . . . . . . . . . . . . . . . . . . . . . 943
19.6.100Or (Integer Bitwise Or) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
19.6.101Package (Declare Package Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
19.6.102PinConﬁg (Pin Conﬁguration Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . 946
19.6.103PinFunction (Pin Function Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . . 949

19.6.104PinGroup (Pin Group Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
19.6.105PinGroupConﬁg (Pin Group Conﬁguration Descriptor Macro) . . . . . . . . . . . . . . . . 952
19.6.106PinGroupFunction (Pin Group Function Conﬁguration Descriptor Macro) . . . . . . . . . . 956
19.6.107PowerResource (Declare Power Resource) . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
19.6.108Printf (Create and Store formatted string) . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
19.6.109QWordIO (QWord IO Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . 958
19.6.110QWordMemory (QWord Memory Resource Descriptor Macro) . . . . . . . . . . . . . . . . 959
19.6.111QWordSpace (QWord Space Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . 961
19.6.112RawDataBuffer (Raw Data Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
19.6.113RefOf (Create Object Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
19.6.114Register (Generic Register Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . 963
19.6.115Release (Release a Mutex Synchronization Object) . . . . . . . . . . . . . . . . . . . . . . 964
19.6.116Reset (Reset an Event Synchronization Object) . . . . . . . . . . . . . . . . . . . . . . . . 964
19.6.117ResourceTemplate (Resource To Buffer Conversion Macro) . . . . . . . . . . . . . . . . . . 964
19.6.118Return (Return from Method Execution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
19.6.119Revision (Constant Revision Integer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
19.6.120Scope (Open Named Scope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
19.6.121ShiftLeft (Integer Shift Left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
19.6.122ShiftRight (Integer Shift Right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
19.6.123Signal (Signal a Synchronization Event) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
19.6.124SizeOf (Get Data Object Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
19.6.125Sleep (Milliseconds Sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
19.6.126SPISerialBusV2 (SPI Serial Bus Connection Resource Descriptor (Version 2) Macro) . . . . 968
19.6.127Stall (Stall for a Short Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
19.6.128StartDependentFn (Start Dependent Function Resource Descriptor Macro) . . . . . . . . . . 969
19.6.129StartDependentFnNoPri (Start Dependent Function Resource Descriptor Macro) . . . . . . 970
19.6.130Store (Store an Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
19.6.131Subtract (Integer Subtract) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
19.6.132Switch (Select Code To Execute Based On Expression) . . . . . . . . . . . . . . . . . . . . 971
xx19.6.133ThermalZone (Declare Thermal Zone) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
19.6.134Timer (Get 64-Bit Timer Value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
19.6.135ToBCD (Convert Integer to BCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
19.6.136ToBuffer (Convert Data to Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
19.6.137ToDecimalString (Convert Data to Decimal String) . . . . . . . . . . . . . . . . . . . . . . 974
19.6.138ToHexString (Convert Data to Hexadecimal String) . . . . . . . . . . . . . . . . . . . . . . 975
19.6.139ToInteger (Convert Data to Integer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
19.6.140ToPLD (Creates a _PLD Buffer Object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
19.6.141ToString (Convert Buffer To String) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
19.6.142ToUUID (Convert String to UUID Macro) . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
19.6.143UARTSerialBusV2 (UART Serial Bus Connection Resource Descriptor Version 2 Macro) . . 978
19.6.144Unicode (String To Unicode Conversion Macro) . . . . . . . . . . . . . . . . . . . . . . . . 980
19.6.145VendorLong (Long Vendor Resource Descriptor) . . . . . . . . . . . . . . . . . . . . . . . 980
19.6.146VendorShort (Short Vendor Resource Descriptor) . . . . . . . . . . . . . . . . . . . . . . . 980
19.6.147Wait (Wait for a Synchronization Event) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
19.6.148While (Conditional Loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
19.6.149WordBusNumber (Word Bus Number Resource Descriptor Macro) . . . . . . . . . . . . . . 981
19.6.150WordIO (Word IO Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . . . . 982
19.6.151WordSpace (Word Space Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . 984
19.6.152XOr (Integer Bitwise Xor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
19.6.153Zero (Constant Zero Integer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
19.6.154ClockInput (Clock Input Resource Descriptor Macro) . . . . . . . . . . . . . . . . . . . . . 986
20 ACPI Machine Language (AML) Speciﬁcation 987
20.1 Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
20.2 AML Grammar Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
20.2.1 Table and Table Header Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
20.2.2 Name Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
20.2.3 Data Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
20.2.4 Package Length Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
20.2.5 Term Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
20.2.5.1 Namespace Modiﬁer Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . 991
20.2.5.2 Named Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
20.2.5.3 Statement Opcodes Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
20.2.5.4 Expression Opcodes Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
20.2.6 Miscellaneous Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
20.2.6.1 Arg Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
20.2.6.2 Local Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
20.2.6.3 Debug Objects Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
20.3 AML Byte Stream Byte Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
20.4 AML Encoding of Names in the Namespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
21 ACPI Data Tables and Table Deﬁnition Language 1006
21.1 Types of ACPI Data Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
21.2 ACPI Table Deﬁnition Language Speciﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
21.2.1 Overview of the Table Deﬁnition Language (TDL) . . . . . . . . . . . . . . . . . . . . . . 1007
21.2.2 TDL Grammar Speciﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
21.2.3 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
21.2.3.1 Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
21.2.3.2 Integer Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
21.2.3.3 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
21.2.3.4 Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
21.2.3.5 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
21.2.4 Fields Set Automatically by the Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
xxi21.2.5 Special Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
21.2.6 TDL Generic Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
21.2.7 Deﬁning a Known ACPI Table in TDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
21.2.8 Deﬁning an Unknown or New ACPI table in TDL . . . . . . . . . . . . . . . . . . . . . . . 1013
21.2.9 Table Deﬁnition Language Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013

21.2.9.1 ECDT Disassembler Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
21.2.9.2 ECDT Deﬁnition with Field Comments . . . . . . . . . . . . . . . . . . . . . . . . 1014
21.2.10 Minimal ECDT Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
21.2.10.1 Generic ACPI Table Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
A Appendix A: Device Class Speciﬁcations 1016
A.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
A.2 Device Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
A.2.1 Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
A.2.2 Display Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
A.2.3 PCMCIA/PCCARD/CardBus Power Management . . . . . . . . . . . . . . . . . . . . . . . 1017
A.2.4 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
A.2.5 USB Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
A.2.6 Device Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
A.3 Default Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
A.3.1 Default Power Management Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
A.3.2 Default Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
A.3.3 Default Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
A.4 Audio Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
A.4.1 Audio Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
A.4.2 Audio Device Power Management Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
A.4.3 Audio Device Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
A.4.4 Audio Device Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
A.5 COM Port Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
A.5.1 COM Port Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
A.5.2 COM Power Power Management Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
A.5.3 COM Port Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
A.5.4 COM Port Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
A.6 Display Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
A.6.1 Display Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
A.6.1.1 Display Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
A.6.2 Display Device Power Management Policy . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
A.6.3 Display Device Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
A.6.4 Display Device Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 1027
A.6.5 Display Device Performance States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
A.6.5.1 Common Requirements for Display Class Performance States . . . . . . . . . . . . 1027
A.6.5.2 Performance states for Full Screen Displays . . . . . . . . . . . . . . . . . . . . . 1027
A.6.5.3 Performance States for Video Controllers/Display Adapters . . . . . . . . . . . . . 1028
A.7 Input Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
A.7.1 Input Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
A.7.2 Input Device Power Management Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
A.7.3 Input Device Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
A.7.4 Input Device Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
A.8 Modem Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
A.8.1 Technology Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
A.8.1.1 Traditional Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
A.8.1.2 Power-Managed Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
A.8.1.3 Motherboard Modems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
A.8.2 Modem Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
xxiiA.8.3 Modem Device Power Management Policy . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
A.8.4 Modem Device Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
A.8.5 Modem Device Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 1032
A.9 Network Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
A.9.1 Network Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
A.9.2 Network Device Power Management Policy . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
A.9.3 Network Device Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
A.9.3.1 Link Status Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
A.9.3.2 Wake Frame Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
A.9.4 Network Device Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 1034
A.10 PC Card Controller Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
A.10.1 PC Card Controller Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . 1034
A.10.2 PC Card Controller Device Power Management Policy . . . . . . . . . . . . . . . . . . . . 1035
A.10.3 PC Card Controller Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
A.10.4 PC Card Controller Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . 1036
A.11 Storage Device Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
A.11.1 Storage Device Power State Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
A.11.2 Storage Device Power Management Policy . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
A.11.3 Storage Device Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038
A.11.4 Storage Device Minimum Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 1038
B Appendix B: Video Extensions 1039
B.1 ACPI Extensions for Display Adapters: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
B.2 Video Extension Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
B.3 ACPI Namespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
B.4 Display-speciﬁc Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
B.4.1 _DOS (Enable/Disable Output Switching) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
B.4.2 _DOD (Enumerate All Devices Attached to the Display Adapter) . . . . . . . . . . . . . . . 1042
B.4.3 _ROM (Get ROM Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
B.4.4 _GPD (Get POST Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
B.4.5 _SPD (Set POST Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
B.4.6 _VPO (Video POST Options) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
B.5 Notiﬁcations for Display Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
B.6 Output Device-speciﬁc Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
B.6.1 _ADR (Return the Unique ID for this Device) . . . . . . . . . . . . . . . . . . . . . . . . . 1048
B.6.2 _BCL (Query List of Brightness Control Levels Supported) . . . . . . . . . . . . . . . . . . 1048
B.6.3 _BCM (Set the Brightness Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
B.6.4 _BQC (Brightness Query Current level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
B.6.5 _DDC (Return the EDID for this Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
B.6.6 _DCS (Return the Status of Output Device) . . . . . . . . . . . . . . . . . . . . . . . . . . 1050

B.6.7 _DGS (Query Graphics State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
B.6.8 _DSS (Device Set State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
B.7 Notiﬁcations Speciﬁc to Output Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
B.8 Notes on State Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
C Appendix C: Deprecated Content 1054
Index 1056
xxiiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
DAMAGES.
CONTENTS xxivAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 1.1 Hardware Type vs. OS Type Interaction
• Table 2.1 Summary of Global Power States
• Table 2.2 Summary of Device Power States
• Table 3.1 Low Battery Levels
• Table 3.3 Implementable Platform Types
• Table 4.1 Feature-Programming Model Summary
• Table 4.2 PM1 Event Registers
• Table 4.3 PM1 Control Registers
• Table 4.4 PM2 Control Register
• Table 4.5 PM Timer Register
• Table 4.6 Processor Control Registers
• Table 4.7 General-Purpose Event Registers
• Table 4.8 Power Button Support
• Table 4.9 Sleep Button Support
• Table 4.10 Alarm Field Decodings within the FADT
• Table 4.11 PM1 Status Registers Fixed Hardware Feature Status Bits
• Table 4.12 PM1 Enable Registers Fixed Hardware Feature Enable Bits
• Table 4.13 PM1 Control Registers Fixed Hardware Feature Control Bits
• Table 4.14 PM Timer Bits
• Table 4.15 PM2 Control Register Bits
• Table 4.16 Processor Control Register Bits
• Table 4.17 Processor LVL2 Register Bits
• Table 4.18 Processor LVL3 Register Bits
• Table 4.19 Sleep Control Register
• Table 4.20 Sleep Status Register
• Table 5.1 Generic Address Structure (GAS)
• Table 5.2 Address Space Format
• Table 5.3 RSDP Structure
• Table 5.4 DESCRIPTION_HEADER Fields
• Table 5.5 DESCRIPTION_HEADER Signatures for tables deﬁned by ACPI
• Table 5.6 DESCRIPTION_HEADER Signatures for tables reserved by ACPI
• Table 5.7 Root System Description Table Fields (RSDT)
• Table 5.8 Extended System Description Table Fields (XSDT)
• Table 5.9 FADT Format
• Table 5.10 Fixed ACPI Description Table Fixed Feature Flags
CONTENTS xxvAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 5.11 Fixed ACPI Description Table Boot IA-PC Boot
• Table 5.12 Fixed ACPI Description Table ARM Boot Architecture Flags
• Table 5.13 Firmware ACPI Control Structure (FACS)
• Table 5.14 Firmware Control Structure Feature Flags
• Table 5.15 OSPM Enabled Firmware Control Structure Feature Flags
• Table 5.16 Global Lock Structure within the FACS
• Table 5.17 Differentiated System Description Table Fields (DSDT)
• Table 5.18 Secondary System Description Table Fields (SSDT)
• Table 5.19 Multiple APIC Description Table (MADT) Format
• Table 5.20 Multiple APIC Flags
• Table 5.21 Interrupt Controller Structure Types
• Table 5.22 Processor Local APIC Structure
• Table 5.23 Local APIC Flags
• Table 5.24 I/O APIC Structure
• Table 5.25 Interrupt Source Override Structure
• Table 5.26 MPS INTI Flags
• Table 5.27 NMI Source Structure
• Table 5.28 Local APIC NMI Structure
• Table 5.29 Local APIC Address Override Structure
• Table 5.30 I/O SAPIC Structure
• Table 5.31 Processor Local SAPIC Structure
• Table 5.32 Platform Interrupt Source Structure
• Table 5.33 Platform Interrupt Source Flags
• Table 5.34 Processor Local x2APIC Structure
• Table 5.35 Local x2APIC NMI Structure
• Table 5.36 GICC Structure
• Table 5.37 GICC CPU Interface Flags
• Table 5.38 GICD Structure
• Table 5.39 GIC MSI Frame Structure
• Table 5.40 GIC MSI Frame Flags
• Table 5.41 GICR Structure
• Table 5.42 GIC ITS Structure
• Table 5.43 Multiprocessor Wakeup Structure
• Table 5.44 Multiprocessor Wakeup Mailbox Structure
• Table 5.53 Smart Battery Description Table (SBST) Format
• Table 5.54 Embedded Controller Boot Resources Table Format
CONTENTS xxviAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 5.55 Static Resource Afﬁnity Table Format
• Table 5.56 Processor Local APIC/SAPIC Afﬁnity Structure
• Table 5.57 Flags - Processor Local APIC/SAPIC Afﬁnity Structure
• Table 5.58 Memory Afﬁnity Structure
• Table 5.59 Flags - Memory Afﬁnity Structure
• Table 5.60 Processor Local x2APIC Afﬁnity Structure
• Table 5.61 GICC Afﬁnity Structure
• Table 5.62 Flags - GICC Afﬁnity Structure
• Table 5.63 Architecture Speciﬁc Afﬁnity Structure
• Table 5.64 Generic Initiator Afﬁnity Structure
• Table 5.65 Device Handle - ACPI
• Table 5.66 Device Handle - PCI
• Table 5.68 Flags - Generic Initiator/Port Afﬁnity Structure
• Table 5.69 SLIT Format
• Table 5.70 Corrected Platform Error Polling Table Format
• Table 5.71 Corrected Platform Error Polling Processor Structure
• Table 5.72 Maximum System Characteristics Table (MSCT) Format
• Table 5.73 Maximum Proximity Domain Information Structure
• Table 5.74 RASF Table format
• Table 5.75 RASF Platform Communication Channel Shared Memory Region
• Table 5.76 PCC Command Codes used by RASF Platform Communication Channel
• Table 5.77 Platform RAS Capabilities Bitmap
• Table 5.78 Parameter Block Structure for PATROL_SCRUB
• Table 5.89 MPST Table Structure
• Table 5.90 PCC Command Codes used by MPST Platform Communication Channel
• Table 5.91 MPST Platform Communication Channel Shared Memory Region
• Table 5.92 Power State Values
• Table 5.93 Command Status
• Table 5.94 Memory Power Node Structure deﬁnition
• Table 5.95 Flag format
• Table 5.96 Memory Power State Structure deﬁnition
• Table 5.97 Memory Power State Characteristics Structure
• Table 5.98 Flag format of Memory Power State Characteristics Structure
• Table 5.99 Platform Memory Topology Table
• Table 5.100 Common Memory Device
• Table 5.101 Socket Type Data
CONTENTS xxviiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 5.102 Memory Controller Type Data
• Table 5.103 DIMM Type Speciﬁc Data
• Table 5.104 Vendor Speciﬁc Type Data
• Table 5.105 Boot Graphics Resource Table Fields
• Table 5.106 Firmware Performance Data Table (FPDT) Format
• Table 5.107 Performance Record Structure
• Table 5.108 FPDT Performance Record Types
• Table 5.109 Runtime Performance Record Types
• Table 5.110 Firmware Basic Boot Performance Table Pointer Record
• Table 5.111 S3 Performance Table Pointer Record
• Table 5.112 Firmware Basic Boot Performance Table Header

• Table 5.113 Firmware Basic Boot Performance Data Record
• Table 5.114 S3 Performance Table Header
• Table 5.115 Basic S3 Resume Performance Record
• Table 5.116 Basic S3 Suspend Performance Record
• Table 5.117 GTDT Table Structure
• Table 5.118 Flag Deﬁnitions: Secure EL1 Timer, Non-Secure EL1 Timer, EL2 Timer, Virtual EL1 Timer and
Virtual EL2 Timer
• Table 5.119 Platform Timer Type Structures
• Table 5.120 GT Block Structure Format
• Table 5.121 GT Block Timer Structure Format
• Table 5.122 Flag Deﬁnitions: GT Block Physical Timers and Virtual Timers
• Table 5.123 Flag Deﬁnitions - Common Flags
• Table 5.124 Arm Generic Watchdog Structure Format
• Table 5.125 Flag Deﬁnitions - Arm Generic Watchdog Timer
• Table 5.126 NVDIMM Firmware Interface Table (NFIT)
• Table 5.127 NFIT Structure Types
• Table 5.128 SPA Range Structure
• Table 5.129 NVDIMM Region Mapping Structure
• Table 5.130 Interleave Structure Index and Interleave Ways deﬁnition
• Table 5.131 Interleave Structure
• Table 5.132 SMBIOS Management Information Structure
• Table 5.133 NVDIMM Control Region Structure Mark
• Table 5.134 NVDIMM Block Data Windows Region Structure
• Table 5.135 Flush Hint Address Structure
• Table 5.136 Platform Capabilities Structure
CONTENTS xxviiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 5.137 SDEV ACPI Table
• Table 5.138 Secure Device Structures
• Table 5.139 ACPI_NAMESPACE_DEVICE based Secure Device Structure
• Table 5.140 Secure Access Component Types
• Table 5.141 Identiﬁcation Based Secure Access Component
• Table 5.142 Memory-based Secure Access Component
• Table 5.143 PCIe Endpoint Device-based Device Structure
• Table 5.144 PCIe Endpoint Device-based Device Structure Example
• Table 5.145 Heterogeneous Memory Attribute Table Header
• Table 5.146 HMAT Structure Types
• Table 5.147 Memory Proximity Domain Attributes Structure
• Table 5.148 System Locality Latency and Bandwidth Information Structure
• Table 5.149 Memory Side Cache Information Structure
• Table 5.150 PDTT Structure
• Table 5.151 PDTT Platform Communication Channel Identiﬁer Structure
• Table 5.152, Type 5 Platform Communication Channel Shared Memory
• Table 5.153 PCC Commands Codes used by Platform Debug Trigger Table
• Table 5.154 PDTT Platform Communication Channel
• Table 5.155 Example: Platform with 4 debug triggers
• Table 5.156 Processor Properties Topology Table
• Table 5.157 Processor Hierarchy Node Structure
• Table 5.158 Processor Structure Flags
• Table 5.159 Cache Type Structure
• Table 5.160 Cache Structure Flags
• Table 5.161 Platform Health Assessment Table (PHAT) Format
• Table 5.162 Platform Health Assessment Record Format
• Table 5.163 Platform Health Assessment Record Type Format
• Table 5.164 PHAT Version Element
• Table 5.165 Firmware Version Data Record
• Table 5.166 Firmware Health Data Record Structure
• Table 5.181 Namespaces Deﬁned Under the Namespace Root
• Table 5.182 Operation Region Address Space Identiﬁers
• Table 5.183 IPMI Status Codes
• Table 5.184 Accsessor Type Values
• Table 5.185 ACPI Event Programming Model Components
• Table 5.186 Fixed ACPI Events
CONTENTS xxixAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 5.187 Device Object Notiﬁcation Values
• Table 5.188 System Bus Notiﬁcation Values
• Table 5.189 Control Method Battery Device Notiﬁcation Values
• Table 5.190 Power Source Object Notiﬁcation Values
• Table 5.191 Thermal Zone Object Notiﬁcation Values
• Table 5.192 Control Method Power Button Notiﬁcation Values
• Table 5.193 Control Method Sleep Button Notiﬁcation Values
• Table 5.194 Control Method Lid Notiﬁcation Values
• Table 5.195 NVDIMM Root Device Notiﬁcation Values
• Table 5.196 NVDIMM Device Notiﬁcation Values
• Table 5.197 Processor Device Notiﬁcation Values
• Table 5.198 User Presence Device Notiﬁcation Values
• Table 5.199 Ambient Light Sensor Device Notiﬁcation Values
• Table 5.200 Power Meter Object Notiﬁcation Values
• Table 5.201 Processor Aggregator Device Notiﬁcation Values
• Table 5.202 Error Device Notiﬁcation Values
• Table 5.203 Fan Device Notiﬁcation Values
• Table 5.204 Memory Device Notiﬁcation Values
• Table 5.205 ACPI Device IDs
• Table 5.206 Predeﬁned ACPI Names
• Table 5.207 Predeﬁned Object Names
• Table 5.208 Predeﬁned Operating System Vendor String Preﬁxes
• Table 5.209 Standard ACPI-Deﬁned Feature Group Strings
• Table 5.210 DeviceLockInfo Package Values
• Table 6.1 Device Identiﬁcation Objects
• Table 6.2 ADR Object Address Encodings
• Table 6.3 Additional Language ID Alias Strings
• Table 6.4 _PLD Buffer 0 Return Value
• Table 6.5 PLD Back Panel Example Settings
• Table 6.6 Device Conﬁguration Objects
• Table 6.7 HPP Package Contents
• Table 6.8 PCI Setting Record Content
• Table 6.9 PCI-X Setting Record Content
• Table 6.10 PCI Express Setting Record Content
• Table 6.11 PCI Express Descriptor Setting Record Content
• Table 6.12 PCI Express Register Descriptor
CONTENTS xxxAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 6.13 Platform-Wide _OSC Capabilities DWORD 2
• Table 6.14 OSPM USB Support Field
• Table 6.15 OSPM USB Control Field
• Table 6.16 Mapping Fields
• Table 6.17 Example Relative Distances Between Proximity Domains
• Table 6.18 Example System Locality Information Table
• Table 6.19 Example Relative Distances Between Proximity Domains - 5 Node
• Table 6.20 Device Insertion, Removal, and Status Objects
• Table 6.21 OST Source Event Codes
• Table 6.22 General Processing Status Codes
• Table 6.23 Operating System Shutdown Processing (Source Events : 0x100) Status Codes
• Table 6.24 Ejection Request / Ejection Processing (Source Events: 0x03 and 0x103) Status Codes
• Table 6.25 Insertion Processing (Source Event: 0x200) Status Codes
• Table 6.26 Small Resource Data Type Tag Bit Deﬁnitions
• Table 6.27 Small Resource Items
• Table 6.28 IRQ Descriptor Deﬁnition
• Table 6.29 DMA Descriptor Deﬁnition
• Table 6.30 Start Dependent Functions Descriptor Deﬁnition
• Table 6.31 Start Dependent Function Priority Byte Deﬁnition
• Table 6.32 End Dependent Functions Descriptor Deﬁnition
• Table 6.33 I/O Port Descriptor Deﬁnition
• Table 6.34 Fixed-Location I/O Port Descriptor Deﬁnition
• Table 6.35 Fixed DMA Resource Descriptor
• Table 6.36 Vendor-Deﬁned Resource Descriptor Deﬁnition
• Table 6.37 End Tag Deﬁnition
• Table 6.38 Large Resource Data Type Tag Bit Deﬁnitions
• Table 6.39 Large Resource Items
• Table 6.40 24-bit Memory Range Descriptor Deﬁnition
• Table 6.41 Large Vendor-Deﬁned Resource Descriptor Deﬁnition
• Table 6.42 32-Bit Memory Range Descriptor Deﬁnition
• Table 6.43 32-bit Fixed-Location Memory Range Descriptor Deﬁnition
• Table 6.44 Valid Combination of Address Space Descriptor Fields
• Table 6.45 WORD Address Space Descriptor Deﬁnition
• Table 6.46 DWORD Address Space Descriptor Deﬁnition
• Table 6.47 WORD Address Space Descriptor Deﬁnition
• Table 6.48 Extended Address Space Descriptor Deﬁnition
CONTENTS xxxiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 6.49 Memory Resource Flag (Resource Type = 0) Deﬁnitions
• Table 6.50 I/O Resource Flag (Resource Type = 1) Deﬁnitions
• Table 6.51 Bus Number Range Resource Flag (Resource Type = 2) Deﬁnitions
• Table 6.52 Extended Interrupt Descriptor Deﬁnition
• Table 6.53 Generic Register Descriptor Deﬁnition
• Table 6.54 GPIO Connection Descriptor Deﬁnition
• Table 6.55 GenericSerialBus Connection Descriptors
• Table 6.56 I2C Serial Bus Connection Descriptor
• Table 6.57 SPI Serial Bus Connection Descriptor
• Table 6.58 UART Serial Bus Connection Descriptor
• Table 6.59 CSI-2 Connection Resource Descriptor
• Table 6.60 Pin Function Description Deﬁnition
• Table 6.61 Pin Conﬁguration Descriptor Deﬁnition
• Table 6.62 Pin Group Descriptor Deﬁnition
• Table 6.63 Pin Group Function Descriptor Deﬁnition
• Table 6.64 Pin Group Conﬁguration Descriptor Description
• Table 6.66 Other Objects and Methods
• Table 6.67 OSPM _INI Object Actions
• Table 6.68 NVDIMM Label Methods
• Table 6.69 _LSI Return Package Values
• Table 6.70 _LSR Return Package Values
• Table 6.71, _CBR Return Package Values
• Table 7.1 Power Resource Object Provisions for Information and Control
• Table 7.2 Power Resource Methods
• Table 7.3 Device Power Management Child Objects
• Table 7.4 PSC Device State Codes
• Table 7.5 Power Resource Requirements Package
• Table 7.6 S1 Action / Result Table
• Table 7.7 S2 Action / Result Table
• Table 7.8 S3 Action / Result Table
• Table 7.9 S4 Action / Result Table
• Table 7.10 BIOS-Supplied Control Methods for System-Level Functions
• Table 7.11 System State Package
• Table 8.1 C-state/T-state/P-state Coordination Types
• Table 8.2 Cstate Package Values
• Table 8.3 C-State Dependency Package Values
CONTENTS xxxiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 8.4 Processor Container Device Objects

• Table 8.5 Valid Local State Combinations in preceding example system
• Table 8.6 OS Initiated Flow
• Table 8.7 Example of incorrect platform state in OS Initiated Request without Dependency Check
• Table 8.8 OS Initiated Request Semantics with Dependency Check
• Table 8.9 Example of incorrect platform state in OS Initiated Request without Hierarchy Parameter
• Table 8.10 OS Initiated Request Semantics with Hierarchy Parameter
• Table 8.11 Local Power States for the Parent Processor or Processor Container
• Table 8.12 Extended LPI Fields
• Table 8.13 Flags for LPI states
• Table 8.14 Enabled Parent State values for example system
• Table 8.15 Entry method example
• Table 8.16 _RDI package return values
• Table 8.17 _PTC Package Values
• Table 8.18 TState Package Values
• Table 8.19 T-State Dependency Package Values
• Table 8.20 _PCT Package Values
• Table 8.21 PState Package Values
• Table 8.22 P-State Dependency Package Values
• Table 8.23 Continuous Performance Control Package Values
• Table 8.24 Performance Limited Register Status Bits
• Table 8.25 PCC Command Codes Used by Collaborative Processor Performance Control
• Table 8.26 Processor Aggregator Device Objects
• Table 9.1 System Indicator Control Methods
• Table 9.2 Control Method Ambient Light Sensor Device
• Table 9.3 Control Method Lid Device
• Table 9.4 ATA Speciﬁc Objects
• Table 9.5 GTM Method Result Codes
• Table 9.6 Tape Presence
• Table 9.7 ACPI Floppy Drive Information
• Table 9.8 MBM Package Details
• Table 9.9 MSM Result Encoding
• Table 9.10 Memory Device _OSC Capabilities DWORD number 2
• Table 9.11 UPC Return Package Values
• Table 9.12 User Presence Detection Device
• Table 9.13 Time and Alarm Device
CONTENTS xxxiiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 9.14 Generic Buttons Device Child Objects
• Table 9.15 Usage Types and Interrupt Polarity
• Table 9.16 Common HID Button Usages
• Table 9.17 NVDIMM Root Device Function Index
• Table 9.18 Status and Extended Status Field Generic Interpretations
• Table 9.19 Query ARS Capabilities - Input Buffer
• Table 9.20 Query ARS Capabilities - Output Buffer
• Table 9.21 Start ARS - Input Buffer
• Table 9.22 Start ARS - Output Buffer
• Table 9.23 Query ARS Status - Output Buffer
• Table 9.24 ARS Data
• Table 9.25 ARS Error Record Format
• Table 9.26 Clear Uncorrectable Error - Input Buffer
• Table 9.27 Clear Uncorrectable Error - Output Buffer
• Table 9.28 Translate SPA - Input Payload Format
• Table 9.29 Translate SPA - Output Payload Format
• Table 9.30 Translate SPA - Translated NVDIMM Device List Output Payload Format
• Table 9.31 ARS Error Inject - Input Format
• Table 9.32 ARS Error Inject - Output Format
• Table 9.33 ARS Error Inject Clear - Input Format
• Table 9.34 ARS Error Inject Clear - Output Format
• Table 9.35 ARS Error Inject Status Query - Output Format
• Table 9.36 ARS Error Inject Status Query - Error Record Format
• Table 9.37 ARS Error Inject Options Support
• Table 9.38 NVDIMM Device Method Return Status Code
• Table 9.39 NCH Return Value
• Table 9.40 _NBS Return Value
• Table 9.41 _NIC Output Buffer
• Table 9.42 _NIH Input Buffer
• Table 9.43 _NIH Output Buffer
• Table 9.44 _NIG Output Buffer
• Table 10.1 Example SMBus Device Slave Addresses
• Table 10.2 Smart Battery Objects
• Table 10.3 Battery Control Methods
• Table 10.4 BIF Return Package Values
• Table 10.5 BIX Return Package Values
CONTENTS xxxivAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 10.6 BMD Return Package Values
• Table 10.7 _BPC Return Package Values
• Table 10.8 Battery Power Threshold Support Capability
• Table 10.9 _BPS Return Package Values
• Table 10.10 BST Return Package Values
• Table 10.11 Control Method Battery _OSC Capabilities DWORD2 Bit Deﬁnitions
• Table 10.12 Power Source Objects
• Table 10.13 PIF Method Result Codes
• Table 10.14 Power Meter Objects
• Table 10.15 PMC Method Result Codes
• Table 10.16 Wireless Power Calibration
• Table 10.17 Wireless Power Control Notiﬁcation Values
• Table 11.1 Fan Speciﬁc Objects
• Table 11.2 FIF Package Details
• Table 11.3 FPS FanPstate Package Details
• Table 11.4 FST Package Details
• Table 11.5 Thermal Objects
• Table 11.6 Thermal Relationship Package Values 1
• Table 11.7 Thermal Relationship Package Values 2
• Table 12.1 Read Only Register Table
• Table 12.3 Embedded Controller Commands
• Table 12.4 Events for Which Embedded Controller Must Generate SCIs
• Table 12.5 Read Command (3 Bytes)
• Table 12.6 Write Command (3 Bytes)
• Table 12.7 Query Command (2 Bytes)
• Table 12.8 Burst Enable Command (2 Bytes)
• Table 12.9 Burst Disable Command (1 Byte)
• Table 12.10 Status Register, SMB_STS
• Table 12.11 SMBus Status Codes
• Table 12.12 Protocol Register, SMB_PRTCL
• Table 12.13 Address Register, SMB_ADDR
• Table 12.14 Command Register, SMB_CMD
• Table 12.15 Data Register Array, SMB_DATA[i], i=0-31
• Table 12.16 Block Count Register, SMB_BCNT
• Table 12.17 Alarm Address Register, SMB_ALRM_ADDR
• Table 12.18 Alarm Data Registers, SMB_ALRM_DATA[0], SMB_ALRM_DATA[1]
CONTENTS xxxvAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 12.19 SMB EC Interface
• Table 12.20 Embedded Controller Device Object Control Methods
• Table 12.21 EC SMBus HC Device Objects
• Table 13.1 SMBus Protocol Types
• Table 14.1 Platform Communications Channel Table (PCCT)
• Table 14.2 Platform Communications Channel Global Flags
• Table 14.3 Generic PCC Subspace Structure
• Table 14.4 PCC Subspace Structure type 0 (Generic Communications Subspace)
• Table 14.5 PCC Subspace Structure type 1 (HW-Reduced Communications Subspace)
• Table 14.6 PCC Subspace Structure type 2 (HW-Reduced Communications Subspace)
• Table 14.7 PCC Subspace Structure type 3 and type 4
• Table 14.8 HW Registers based Communications Subspace Structure (Type 5)
• Table 14.9 Generic Communications Channel Shared Memory Region
• Table 14.10 Generic Communications Channel Command Field
• Table 14.11 Generic Communications Channel Status Field
• Table 14.12 Initiator Responder Communications Channel Shared Memory Region
• Table 14.13 Initiator Responder Communications Channel Flags
• Table 14.14 Reduced PCC Subspace Shared Memory Region
• Table 15.1 Address Range Types
• Table 15.2 Input to the INT 15h E820h Call
• Table 15.3 Output from the INT 15h E820h Call
• Table 15.4 Address Range Descriptor Structure
• Table 15.5 Extended Attributes for Address Range Descriptor Structure
• Table 15.6 UEFI Memory Types and mapping to ACPI address range types
• Table 15.7 Sample Memory Map
• Table 18.1 Boot Error Record Table (BERT)
• Table 18.2 Hardware Error Source Table (HEST)
• Table 18.3 IA-32 Architecture Machine Check Exception Structure
• Table 18.4 IA-32 Architecture Machine Check Error Bank Structure
• Table 18.5 IA-32 Architecture Corrected Machine Check Structure
• Table 18.6 IA-32 Architecture NMI Error Structure
• Table 18.7 PCI Express Root Port AER Structure
• Table 18.8 PCI Express Device AER Structure
• Table 18.9 PCI Express/PCI-X Bridge AER Structure
• Table 18.10 Generic Hardware Error Source Structure
• Table 18.11 Generic Error Status Block
CONTENTS xxxviAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 18.12 Generic Error Data Entry
• Table 18.13 Generic Hardware Error Source version 2 (GHESv2) Structure
• Table 18.14 Hardware Error Notiﬁcation Structure
• Table 18.15 IA-32 Architecture Deferred Machine Check Structure
• Table 18.17 Error Record Serialization Table (ERST)
• Table 18.18 Error Record Serialization Actions
• Table 18.19 Command Status Deﬁnition
• Table 18.20 Serialization Instruction Entry
• Table 18.21 Serialization Instructions
• Table 18.22 Instruction Flags
• Table 18.23 Error Record Serialization Info
• Table 18.24 Error Injection Table (EINJ)
• Table 18.25 Error Injection Actions
• Table 18.26 Injection Instruction Entry
• Table 18.27 Instruction Flags
• Table 18.28 Injection Instructions
• Table 18.29 Command Status Deﬁnition
• Table 18.30 Error Type Deﬁnition
• Table 18.31 SET_ERROR_TYPE_WITH_ADDRESS Data Structure
• Table 18.32 Vendor Error Type Extension Structure
• Table 18.36 Trigger Error Action
• Table 19.1 ASL Grammar Notation
• Table 19.2 Named Object Reference Encodings
• Table 19.3 Deﬁnition Block Name Modiﬁer Encodings
• Table 19.4 ASL Escape Sequences
• Table 19.5 Summary of ASL Data Types
• Table 19.6 Data Types and Type Conversions
• Table 19.7 Object Conversion Rules
• Table 19.8 Object Storing and Copying Rules
• Table 19.9 Reading from ArgX Objects
• Table 19.10 Writing to ArgX Objects
• Table 19.11 Reading from LocalX Objects
• Table 19.12 Writing to LocalX Objects
• Table 19.13 Reading from Named Objects
• Table 19.14 Writing to Named Objects
• Table 19.15 ASL Operators Summary List
CONTENTS xxxviiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Table 19.16 ASL compiler controls
• Table 19.17 ACPI table management

• Table 19.18 Miscellaneous named object creation
• Table 19.19 Operation Regions and Fields
• Table 19.20 Buffer Fields
• Table 19.21 Synchronization
• Table 19.22 Object references
• Table 19.23 Integer arithmetic
• Table 19.24 Logical operators
• Table 19.25 Method execution control
• Table 19.26 Data type conversion and manipulation
• Table 19.27 Resource Descriptor macros
• Table 19.28 Constants
• Table 19.29 Control method objects
• Table 19.30 Concatenate Data Types
• Table 19.31 Concatenate Object Types
• Table 19.32 Debug Object Display Formats
• Table 19.33 Field Unit List Entries
• Table 19.34 OperationRegion Address Spaces and Access Types
• Table 19.35 Match Term Operator Meanings
• Table 19.36 Values Returned By the ObjectType Operator
• Table 19.37 Pin Conﬁguration Types and Values
• Table 19.38 Pin Group Conﬁguration Types and Values
• Table 19.39 PLD Keywords and Assignment Types
• Table 19.40 PLD Keywords and assignable String Values
• Table 19.41 UUID Buffer Format
• Table 19.42 UART Serial Bus Connection Resource Descriptor - Version 2 Macro
• Table 20.1 AML Grammar Notation Conventions
• Table 20.2 AML Byte Stream Byte Values
•Table A-1: Default Power State Deﬁnitions
•Table A-2: Default Power Management Policy
•Table A-3: Audio Device Power State Deﬁnitions
•Table A-4: Audio Device Power Management Policy
•Table A-5: COM Port Device Power State Deﬁnitions
•Table A-6: COM Port Device Power Management Policy
•Table A-7: CRT Monitors Power State Deﬁnitions
CONTENTS xxxviiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
•Table A-8: Internal Flat Panel Displays Power State Deﬁnitions
•Table A-9: External Digital Displays Power State Deﬁnitions
•Table A-10: Standard TV Devices and Analog HDTVs Power State Deﬁnitions
•Table A-11: Other (new) Full Screen Display Devices Power State Deﬁnitions
•Table A-12: Video Controllers (Graphics Adapters) Power State Deﬁnitions
•Table A-13: Display Device Power Management Policy
•Table A-14: Input Device Power State Deﬁnitions
•Table A-15: Input Device Power Management Policy
•Table A-16: Modem Device Power State Deﬁnitions
•Table A-17: Modem Device Power Management Policy
•Table A-18: Network Device Power State Deﬁnitions
•Table A-19: Network Device Power Management Policy
•Table A-20: PC Card Controller Power State Deﬁnitions
•Table A-21: PC Card Controller Power Management Policy
•Table A-22: Hard Disk, CD-ROM and IDE/ATAPI Removable Storage Devices Power State Deﬁnitions
•Table A-23: Floppy Disk Devices Power State Deﬁnitions
•Table A-24: IDE Channel Devices Power State Deﬁnitions
•Table A-25: Hard Disk, Floppy Disk, CD-ROM and IDE/ATAPI Removable Storage Devices Power Management
Policy
•Table A-26: IDE Channel Devices Power Management Policy
•Table B-1: Video Extension Object Requirements
•Table B-2: Video Output Device Attributes
•Table B-3: Example Device IDs
•Table B-4: Notiﬁcations for Display Devices
•Table B-5: Output Device Status
•Table B-6: Device State for _DGS
•Table B-7: Device State for _DSS
•Table B-8: Notiﬁcation Values for Output Devices
CONTENTS xxxixAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
•Fig. i-1 - ACPI overview
•Fig. i-2 - ACPI Structure
•Fig. i-3 - ASL and AML
•Fig. i-4 ACPI Initialization
•Fig. i-5 Runtime Thermal Event
• Fig. 1.1 OSPM/ACPI Global System
• Fig. 3.1 Global System Power States and Transitions
• Fig. 3.2 Example Modem and COM Port Hardware
• Fig. 3.3 Reporting Battery Capacity
• Fig. 3.4 Formula for Remaining Battery Percentage
• Fig. 3.5 Formula for the Present Drain Rate
• Fig. 3.6 Low Battery and Warning
• Fig. 4.1 Generic Hardware Feature Model
• Fig. 4.2 Global States and Their Transitions
• Fig. 4.3 Example Event Structure for a Legacy/ACPI Compatible Event Model
• Fig. 4.4 Block Diagram of a Status/Enable Cell
• Fig. 4.5 Example Fixed Hardware Feature Register Grouping
• Fig. 4.6 Register Blocks versus Register Groupings
• Fig. 4.7 Power Management Timer
• Fig. 4.8 Fixed Power Button Logic
• Fig. 4.9 Fixed Hardware Sleep Button Logic
• Fig. 4.10 Sleeping/Wake Logic
• Fig. 4.11 RTC Alarm
• Fig. 4.12 Power Management Events to SMI/SCI Control Logic
• Fig. 4.13 Example of General-Purpose vs. Generic Hardware Events
• Fig. 4.14 Example Generic Address Space Lid Switch Logic
• Fig. 5.1 Root System Description Pointer and Table
• Fig. 5.2 Description Table Structures
• Fig. 5.3 APIC-Global System Interrupts
• Fig. 5.4 8259 - Global System Interrupts
• Fig. 5.5 MPST ACPI Table Overview
• Fig. 5.6 Memory Power State Transitions
• Fig. 5.7 Image Offset
• Fig. 5.8 FPDT Hierarchy Structure
• Fig. 5.9 NVDIMM Firmware Interface Table (NFIT) Overview
CONTENTS xlAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Fig. 5.10 HMAT Representation
• Fig. 5.11 Memory Side Cache Example
• Fig. 5.12, Mapping a PDTT Debug Trigger Table Entry to a PCCT PCC Subspace
• Fig. 5.13 Example: Platform with four debug triggers
• Fig. 5.14 L1 Cache Structure
• Fig. 5.15 Cache Type Structure - Type 1 Example
• Fig. 5.16 Example ACPI NameSpace
• Fig. 5.17 AML Encoding
• Fig. 6.1 System Panel and Panel Origin Positions
• Fig. 6.2 Laptop Panel and Panel Origin Positions
• Fig. 6.3 Default Shape Deﬁnitions
• Fig. 6.4 PLD Back Panel Rendering
• Fig. 6.5 System Locality information Table
• Fig. 6.6 Device Ejection Flow Example Using _OST
• Fig. 7.1 Working / Sleeping State object evaluation ﬂow
• Fig. 8.1 Processor Power States
• Fig. 8.2 Throttling Example
• Fig. 8.3 Equation 1 Duty Cycle Equation
• Fig. 8.4 Example Control for the STPCLK
• Fig. 8.5 ACPI Clock Logic (One per Processor)
• Fig. 8.6 Processor Hierarchy
• Fig. 8.7 Power states for processor hierarchy
• Fig. 8.8 Worst case wake latency
• Fig. 8.9 Energy of states A,B and C versus sleep duration
• Fig. 8.10 Platform performance thresholds
• Fig. 8.11 OSPM performance controls
• Fig. 9.1 A ﬁve-point ALS Response Curve
• Fig. 9.2 A two-point ALS Response Curve
• Fig. 9.3 Example Response Curve for a Transﬂective Display
• Fig. 9.4 USB ports
• Fig. 9.5 Persistence of expired timer events
• Fig. 9.6 System transitions with WakeAlarm — Timer
• Fig. 9.7 System transitions with WakeAlarm — Policy
• Fig. 9.8 Vendor/Device Speciﬁc Driver Loading
• Fig. 10.1 Typical Smart Battery Subsystem (SBS)
• Fig. 10.2 Single Smart Battery Subsystem
CONTENTS xliAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Fig. 10.3 Smart Battery Subsystem
• Fig. 10.4 Remaining Battery Percent Formula
• Fig. 10.5 Remaining Battery Life Formula
• Fig. 10.6 Power Meter and Power Source/Docking Namespace Example
• Fig. 11.1 ACPI Thermal Zone
• Fig. 11.2 Thermal Events
• Fig. 11.3 Temperature and CPU Performance Versus Time
• Fig. 11.4 Active and Passive Threshold Values
• Fig. 11.5 Cooling Preferences
• Fig. 12.1 Shared Interface
• Fig. 12.2 Private Interface
• Fig. 12.3 Interrupt Model
• Fig. 13.1 Bit Encoding Example
• Fig. 13.2 Smart Battery Subsystem Devices
• Fig. 13.3 Smart Battery Device Virtual Registers
• Fig. 14.1 Communication ﬂow of the doorbell protocol
• Fig. 14.2 Communication ﬂow for notiﬁcations on Responder subspaces
• Fig. 16.1 Example Sleeping States
• Fig. 16.2 Platform Firmware Initialization
• Fig. 16.3 Example Physical Memory Map
• Fig. 16.4 Memory as Conﬁgured after Boot
• Fig. 16.5 OS Initialization
• Fig. 18.1 APEI error ﬂow example with external RAS controller
•Fig. B-1 Example Display Architecture
CONTENTS xliiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• ACPI Speciﬁcation Working Group (ASWG)
• Others as noted in the Revision History below
Table 1: Changes in this release
ACPI Rev # Issue / Description / Submitter Affected Content
6.5 2122 DTPR signature reservation Table 5.5
6.5 2151 Reserve an _SB._OSC bit and an OperationRegion
Subtype for Platform Runtime Mechanism (PRM)Table 5.182, Table 6.13
6.5 2152 Code ﬁrst: Add the Virtual I/O Translation (VIOT)
Table (Al Stone and others)Section 5.2.32
6.5 2162 Reserve ACPI table signature for SVKL Table 5.6
6.5 2177 Reserve ACPI table signature for CCEL Table 5.6
6.5 2188 Code First: Add ‘CXL Root Object’ _HID (Vishal
Verma)Section 5.2.6, Table 5.205
6.5 2195 Remove section 9.7 Embedded Controller Device Appendix C: Deprecated Con-
tent
6.5 2196 Introduce unaccepted memory type - Address-
RangeUnacceptedTable 15.1
6.5 2198 Clariﬁcation to Address Space ID Table 5.1
6.5 2203 Code First: Add APIC Structures for Loongarch
in MADT (LV Jianmin)Section 5.2.12, Section
5.2.12.20 & sections following.
6.5 2206 Add new PERSISTENT_CPU_CACHES bits to
FADT Fixed Feature Flags tableTable 5.10
6.5 2210 Update reference link for the PnP BIOS Spec Section 6.2.2
6.5 2215 Update to S4 language Table 5.13, Section 16.1.4.1
6.5 2224 Code First - _DSC Deepest State for Conﬁguration

tent
(Rafael Wysocki)Table 7.3, Section 7.3.27
6.5 2228 Code First - RASF Gen2 (Samer El-Haj-
Mahmoud)Section 5.2, Table 5.5, Section
5.2.21
6.5 2233 Connection Sharing update for Serial Bus Connec-
tion DescriptorSection 6.4.3.8.2.1, Table 6.55,
Section 19.6.58
6.5 2236 Code First: Generic Port, performance data for
hotplug memory (Dan Williams)Section 5.2.16, Section 5.2.16.6,
Table 5.68, Section 5.2.16.7
6.5 2239 Code First - RAS2 Error Record Local Address
to System Physical Address Conversion (Samer El-Haj-
Mahmoud)Table 5.86, Section 5.2.21.2.2
6.5 2241 Reserve ACPI Device ID for Audio Composition
DeviceTable 5.205
6.5 2245 Code First - DSD property for ueﬁ-clock-
frequency (Samer El-Haj-Mahmoud)Table 6.39, Section 6.4.3.14,
Section 19.6.154
6.5 2248 Adding WDDT name reservation into spec Table 5.6
6.5 2250 Reserve APMT table name Table 5.6
6.5 2253 Clariﬁcation - Time and Alarm Device methods
requirements (Samer El-Haj-Mahmoud)Section 9.17.2, Section 9.17.5,
Section 9.17.6, Section 9.17.7,
Section 9.17.8, Section 9.17.9,
Section 9.17.10
CONTENTS xliiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 1 – continued from previous page
6.5 2258 Deprecate CDIT/CRAT Appendix C: Deprecated Con-
tent
6.5 2261 Reserve KEYP table name Table 5.5
6.5 2267 Code ﬁrst - EINJ updates for CXL (Thanunathan
Rangarajan)Table 18.30
6.5 2268 Updated ECR for adding APIC structures for
Loongarch in MADTSection 5.2.12, Section
6.5 2272 Code First - Allow FFH OpRegion (Samer El-Haj-
Mahmoud)Table 5.182, Section 5.5.2.4.2,
Table 6.13
6.5 2275 MHSP table signature reservation Table 5.5
6.5 2281 Reserve “AGDI” table signature Table 5.5
6.5 2285 Code First - MADT GICC new ﬂags (Samer El-
Haj-Mahmoud)Table 5.37
6.5 2287 Code First - EINJv2 (Harb Abdulhamid and oth-
ers)Table 18.25, Section 18.6.2,
Section 18.6.7
6.5 2293 _ADR and _UPC changes, _PDO addition for
USB4 and USB-CSection 1.10, Table 6.14, Ta-
ble 9.11, Section 9.12.1, Section
9.12.2
6.5 2294 Reset Reason Health Record Section 5.2.31.5
6.5 2296 Reserve “NBFT” table signature Table 5.5
6.5 2297 Miscellaneous GUIDed Table Entries deﬁnition Section 5.2.4, Table 5.5, Section
5.2.33
6.5 2298 Reserve “SWFT” table signature Table 5.5
6.5 2303 Code First - Armv9 TRBE Support (Thanunathan
Rangarajan)Table 5.36
6.5 2309 Update of FADT Minor Version Table 5.9
6.5 2312 Update to the HEST table and adding new error
source descriptorTable 18.2
6.5 2314 Code First - Add conﬁdential computing extension
for ACPI (Jiewen Yao)Section 5.2.34, Section 5.2.35
6.5 2316 Add an “attribution” link to the ACPI spec See top of this Revision History
list.
6.5 2322 File name references consistency (upper/lower
case)throughout the spec
6.5 2328 Add ACPI Burst Mode Opt-Out Table 12.20
6.5 2331 IAPC_BOOT_ARCH’s description in FADT table
points to an incorrect tableTable 5.9
6.5 2332 EISAID macro corrections Section 6.5.11, Section 19.6.64
6.5 2333 USB power data object (_PDO) Section 9.13
6.5 2334 Power Button Override clariﬁcation Table 4.1
6.5 2335 Comments on review draft Section 5.2.31.5, Table 5.168
6.5 2338 Table name reservation (IERS) Table 5.6
6.5 2345 draft spec feedback Section 5.2.16.6, Table 5.68,
and miscellaneous corrections
6.5 2346 Inclusive language update for ACPI spec Section 1.1.1
Table 2: Changes in previous releases
ACPI Rev # Issue # / Description Affected Content
6.4 A 2179 _BPT control method: arg2’s description is in-
complete in ACPI 6.4 draftSection 10.2.2.10
CONTENTS xlivAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 2 – continued from previous page
6.4 A 2181 Missing new ACPI 6.4 predeﬁned names in Table
5.173: Predeﬁned ACPI NamesTable 5.206
6.4 A 2187 Some parts of FPDT and SDEV sections should
be re-orderedSection 5.2.27.1
6.4 A 2193 Remove section 9.4 Appendix C: Deprecated Content
6.4 A 2194 Remove deprecated content in section 8.4 Appendix C: Deprecated Content
6.4 A 2195 Remove section 9.7 Appendix C: Deprecated Content
6.4 A 2198 Clariﬁcation to Address Space ID Table 5.1
6.4 A 2211 Two corrections to the Buffer 0 Return Value table Table 6.4
6.4 A 2216 Incorrect DBPG2 reference Table 5.6
6.4 A 2219 PPTT is missing in DESCRIPTION_HEADER
Signatures for tables deﬁned by ACPITable 5.5
6.4 A 2220 Document meaning behind _MEM attributes Section 6.4.3.5.4.1
6.4 A 2221 Document architecture mapping for extended at-
tributes in Type Speciﬁc AttributesSection 6.4.3.5.4.1
6.4 A 2223 Code First - correct _DMA resource type example Section 6.2.4
6.4 A 2242 Note misplaced in the Memory Resource Flag
Deﬁnitions table (resource type=0)Table 6.49, plus other sections of
chapter 6.
6.4 A 2244 shareable (10 used) or sharable (3 used) in ACPI
spec 6.4Table 5.9, Table 5.206, Section 9.12
6.4 A 2254 Incorrect link in 6.4.3.7 Generic Register Descrip-
torSection 6.4.3.7
6.4 A 2257 What is meant by handling an error. Table 18.3
6.4 A 2273 _STA and _DIS Clariﬁcations Section 6.2.3, Section 6.3.7
6.4 A 2274 Code First - Update HW Error Notiﬁcation Struc-
ture to reference SDEITable 18.14
6.4 A 2276 Pin Group Conﬁguration Descriptor: Resource
Identiﬁer binary encoding incorrectTable 6.64
6.4 A 2282 Code ﬁrst - Fix incorrect reference to “Memory
Aggregator Device”Table 6.64
6.4 A 2283 Code ﬁrst - BGRT table “valid” ﬁeld typo Table 5.105
6.4 A 2284 Inclusive language rename for PCCT sub-space
types 3 & 4Table 14.7, Table 14.12, Table 14.13,
Section 14.5, Section 14.6.1, Section
14.6.2
6.4 A 2299 Correction for Device Power Management Objects Section 7.3
6.4 A 2301 Invalid section reference in CopyObject ASL op-
erator deﬁnitionSection 19.6.17
6.4 A 2304 _PLD content missing in table 6.4, spec rev 6.4 Table 6.4
6.4 A 2305 Remove orphaned reference to deprecated PPTT
Type 0Section 5.2.30.1
6.4 A 2307 Missing note numbers in Appendix B table B3 Appendix B: Video Extensions
6.4 A 2308 Update/Clariﬁcation to _STA Section 6.3.7
6.4 A 2310 FADT Format clariﬁcations Table 5.9
6.4 A 2323 Update of FADT Minor Version for ACPI 6.4 Er-
rata ATable 5.9
6.4 1933 Remove obsolete DDBHandle data type Section 19, Section 20
6.4 1975 NFIT PMTT Memory Topology Section 5.2.22.12, Section 9.19.3
6.4 1988 VDIMM SPA Location Cookie Table 5.128
6.4 1991 Generic Initiator clariﬁcations Table 5.68, Section 5.2.28.1, and Sec-
tion 5.2.28.4
CONTENTS xlvAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4 1997 Add Fuel Gauge Support to Control Method Bat-
tery deviceSection 10.2, Section 10.2.1, Table
10.3, Table 10.11
6.4 2006 Add \_SB._OSC bit for native USB 4 sup-
port/controlSection 6.2.11.1.3, Table 6.13, Sec-
tion 6.2.11.3
6.4 2010 Deﬁne new PCC Structure (Type 5) Section 14.1.7, Section 14.4, Section
5.2.29.1
6.4 2044 Query ARS Capabilities Clariﬁcation Table 9.20
6.4 2045 CXL ACPI enumeration Table 5.205, Section 6.5.11
6.4 2056 Signature Reservation for Regulatory Graphics
Resource Table (RGRT)Table 5.6
6.4 2070 Deﬁne Address encoding for PCI BAR Target
GAS structureTable 5.2, Table 6.13
6.4 2075 Add reference to CDAT Structure from ACPI table Section 17, https://ueﬁ.org/acpi
6.4 2076 Reserve CEDT signature Table 5.6, https://ueﬁ.org/acpi
6.4 2077 Clarify CXL _CBR enumeration method Table 6.71
6.4 2081 Add Connection Descriptor deﬁnition and macro
for MIPI CSI-2Table 6.55, Section 6.4.3.8.2.4, Sec-
tion 19.6.24
6.4 2087 Add MultiProcessor Wakeup structure Table 5.21, Section 5.2.12.19
6.4 2090 ECR for Battery Charge Limiting (BCL) mode
supportSection 3.9.6, Table 6.13, Table 10.10,
Table 10.6, Section 10.2.2.5
6.4 2094 New platform telemetry data table - PTDT, reser-
vation and deﬁnitionTable 5.5, Section 5.2.31
6.4 2104 Reserve ACPI table signature for the PRMT Table 5.6
6.4 2105 Increase FADT Major & Minor number to match
next ACPI release.Table 5.9
6.4 2108 Add new ACPI device ID for USB4 host routers Table 5.205
6.4 2111 Add Access Components for Secure ACPI Enu-
merated Devices in the SDEV tableSection 5.2.27.1.1
6.4 2118 AEST table signature reservation Table 5.6
6.4 2120 MPAM Table Name Reservation Table 5.6
6.4 2121 HMAT updates to support systems with heteroge-
neous memorySection 5.2.28.1, Section 5.2.28.4
6.4 2126 Rename SBSA Generic Watchdog and move the
spec link to the UEFI websiteSection 5.2.25, Table 5.119, and Sec-
tion 5.2.25.2
6.4 2127 BDAT name reservation Table 5.6
6.4 2133 Remove reference to DMA Protection Policy Ta-
ble (DPPT)Table 5.5
6.4 2137 Extend _DDC to support greater than 256 byte
buffer return_DDC (Return the EDID for this De-
vice)
6.4 2138 ACPI-based Identiﬁers for Caches Table 5.156, Section 5.2.30.1, Table
5.159, Table 5.160
6.4 2144 Clarify SSDT load order Section 5.2.11
6.4 2146 Error in the HMAT System Locality Latency and
Bandwidth Information StructureTable 5.148
6.4 2150 Clarify description of CoordType in _PSD object Table 8.1, Table 8.3, Table 8.19, Table
8.22

vice)
8.22
6.4 2156 Corrections to the FPDT Fig. 5.8, Table 5.106, Section
5.2.24.1, Section 5.2.24.2, Section
5.2.24.3, Section 5.2.24.4, Section
5.2.24.5, Section 5.2.24.6, Section
5.2.24.7, Section 5.2.24.8
CONTENTS xlviAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4 2157 Processor object cleanup missed ProcessorObj in
ObjectTypeKeyword listObjectTypeKeyword , Table 19.36
6.4 2159 6.3A contains incorrect heading levels for some
sectionsvarious sections
6.4 2162 Reserve ACPI table signature for the SVKL Table 5.6
6.4 2169 IRQ macro description incorrectly refers to the IO
macroSection 19.6.66
6.4 2170 Feedback on the 6.4 draft multiple sections; see Mantis for de-
tails
6.4 2171 Heading changes for consistency in section 19.6 Section 19.6.102, Section 19.6.103,
Section 19.6.104, Section 19.6.105,
and Section 19.6.106
6.4 2176 EINJ: Correction for
GET_COMMAND_STATUS Action.Table 18.18
6.4 2179 _BPT control method: arg2 description is incom-
plete in ACPI 6.4 draftSection 10.2.2.10
6.4 2180 New section from ECR M2010 misplaced in ACPI
6.4 draftSection 14.1.7
6.4 2181 Missing new items in ACPI Predeﬁned Names ta-
bleTable 5.206
6.4 2182 Multiprocessor Wakeup Structure misplaced in
specTable 5.21, Section 5.2.12.19
6.4 2183 Incorrect PHAT reference in Table 5-5 Table 5.5
6.4 2186 Error in sample code Section 5.6.9.2, Section 5.6.9.3
6.4 2187 Some parts of SDEV sections should be re-ordered Section 5.2.27.1
6.4 2191 Feedback on ACPI 6.4 draft various sections
6.4 2197 Typos in the t-state dependency and p-state depen-
dency tablesTable 8.19, Table 8.22
6.3 A 1952 Serious issues with Generic Serial Bus chapters Section 5.5
6.3 A 1972 Add links to grammar deﬁnitions Section 19.2, Section 20.2, Section
21.2.2
6.3 A 1973 Change name of TypeXOpcodes for clarity Section 19.2, Section 20.2
6.3 A 1977 Errata for GHES_ASSIST (APEI) feature Table 18.3, Table 18.5, Table 18.10,
Table 18.15, and Section 18.7
6.3 A 1981 Minor issues with BGRT description and ﬁeld
names.Table 5.105
6.3 A 1985 ASL macro deﬁnitions reversed between “For”
and “Fprintf”Section 19.3.4
6.3 A 1990 _PR0 ﬁxes Section 7.3.8
6.3 A 1995 Clarifcation to the Guaranteed Performance Reg-
ister implementationSection 8.4.6.1.1.6
6.3 A 2001 Clariﬁcations for PCI Express AER ownership Section 18.3.2.4, Section 18.3.2.5,
Section 18.3.2.6
6.3 A 2004 Appendices numbering Appendix A: Device Class Speciﬁca-
tions ,Appendix B: Video Extensions ,
Appendix C: Deprecated Content
6.3 A 2011 _DSD link in Generic Buttons Device Child Ob-
jects tableSection 9.18
6.3 A 2012 Clarify allowed values for ACPI0007 _UIDs Section 5.2.12, Section 6.1.12
6.3 A 2021 Typo in PM_TMR_BLK ﬁeld Table 5.9
CONTENTS xlviiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.3 A 2022 Errors in description of “X_GPE0_BLK” Table 5.9
6.3 A 2037 Incorrect reference in Real Time Clock Alarm Section 4.8.2.4
6.3 A 2047 Clariﬁcations and Fixes to the Error Injection
(EINJ) sectionSection 18.6
6.3 A 2052 Clarify behavior of PerformanceLimitedRegister
in _CPCSection 8.4.6.1.3.2
6.3 A 2057 Clarify wording of delivered performance con-
straints in CPPCSection 8.4.6.1.3.1
6.3 A 2059 EISAID Macro - missing algorithm Section 19.3.4
6.3 A 2064 Make “DPA” deﬁnition more generic Device Physical Address (DPA) , Sec-
tion 9.19.7.8, Section 9.19.7.8.3
6.3 A 2067 Clarify _HID and _ADR usage Section 6, Section 6.1, Section 6.1.1,
Section 6.1.2, Section 6.1.5
6.3 A 2069 Update ﬁgure OSPM/ACPI Global System Fig. 1.1
6.3 A 2072 Deprecate “PPTT Type 2 - Processor ID” section Was section 5.2.29.3 in ACPI Spec 6.3
6.3 A 2098 Clariﬁcation of supported ACPI platform imple-
mentationsTable 3.3
6.3 A 2100 Correction/Clariﬁcation of _CBA description Table 5.206
6.3 A 2109 Incorrect SLIT reference in “DESCRIP-
TION_HEADER Signatures for tables deﬁned by
ACPI”Table 5.5
6.3 A 2112 _TZP questions and issues Section 11.4.26
6.3 A 2113 Label tables in the OS Initiated section of Idle
State CoordinationSection 8.4.3.2.2, Section 8.4.3.2.2.1
6.3 A 2115 Duplicate deﬁnition of RawDataBufferTerm Section 19.2.6
6.3 A 2123 Interrupt Polarity _LL values do not agree between
chaptersSection 19.6.64 and Section 19.6.66
6.3 A 2128 Some changes from ECR 1588 are missing in
ACPI 6.3Section 19.6.64
6.3 A 2140 Incorrect offsets in PCC Subspace Structures type
3 and 4Table 14.7
6.3 A 2141 Typos in Chapters 5 and 17 Revision History, Table 5.23, Section
17.3.1, and Section 17.4.1
6.3 A 2145 Error in the PCC Type 3 and 4 subspace descrip-
tionTable 14.7
6.3 1851 Extend GTDT to describe ARMv8.1 architected
CNTHV timerSection 5.2.24
6.3 1855 ARS Error Inject Table 9-299, Section 9.20.7.7, Section
9.20.7.9.1, Section 9.20.7.12
6.3 1867 Add Trigger order to PCC Identiﬁer structure
within PDTTSection 5.2.28
6.3 1873 Peripheral-attached Memory Table 5-132
6.3 1883 Reserve the table names “CRAT” and “CDIT” http://ueﬁ.org/acpi
6.3 1893 New NVDIMM Device methods _NCH and _NBS Section 9.20.8.1, Section 9.20.8.2
6.3 1898 PCC Operation Region Section 5.5.2.4, Section 6.5.4, Section
19.2.7, Section 19.6, Section 20.2.5.2
6.3 1900 I3C host controller support Table 6-190, Table 6-241
6.3 1904 Generic Initiator Afﬁnity Structure Section 5.2.16
6.3 1910 NVDIMM Address Range Scrubbing (ARS) inter-
face updateSection 5.6.6, Section 9.20.7
6.3 1911 _PRD object in Table 6-186 has no deﬁnition Appendix C
CONTENTS xlviiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.3 1913 New NVDIMM Device methods for Health Error
InjectionSection 5.6.6, Section 9.20.8
6.3 1914 HMAT Enhancements Section 5.2.27
6.3 1922 _HPX Enhancements Section 6.2.9
6.3 1930 ASL: Make some arguments to ASL operators op-
tionalSection 19.6.7, Section 19.6.46, Sec-
tion 19.6.63, Section 19.6.88
6.3 1931 ASL: extend Load() operator to allow table load
from an ASL bufferSection 19.6.76
6.3 1932 ASL: deprecate Unload operator Section 19.6.146 and related refer-
ences
6.3 1934 SPE support for ARM Section 5.2.12.14, Table 5-155
6.3 1939 Error Disconnect Recover Notiﬁcation Table 5-165, Section 6.3.5
6.3 1944 Outdated copied text from PCI Firmware Spec Section 6.2.11.3, Section 6.2.11.4
6.3 1946 Generic Initiator _OSC Bit Section 5.2.16.6, Table 6-200
6.3 1948 Adds an “Online Capable” ﬂag to the Local APIC,
Local SPAPIC, and x2APIC structures in MADTTables 5-46, 5-47, 5-55, and 5-58
6.3 1958 PCC Operation Region Updates Section 5.5.2.4, Section 19.2.7, Table
19-420, Section 20.2.5.2
6.3 1959 Update to ECR 1914 Table 5-146
6.3 1978 GT Block Timers table - update the Timer Inter-
rupt Mode descriptionTable 5-126
6.3 1979 ACPI version change from 6.2 to 6.3 Table 5-33
6.3 1980 Fix link to local APIC ﬂags in the Processor Local
APIC Structure tableTable 5-46
6.2 B 1819 Errata: remove support for multiple GICD struc-
turesTable 5-43
6.2 B 1852 Fix Inconsistent TranslateType Language Section 19.6.33, Section 19.6.34, Sec-
tion 19.6.41, Section 19.6.42, Section
19.6.109, Section 19.6.110, Section
19.6.151
6.2 B 1870 PPTT Clariﬁcations Section 5.2.29.1
6.2 B 1881 Incorrect reference “Memory Devices” in
“5.2.21.10 Interaction with Memory Hot Plug”Section 5.2.21.10
6.2 B 1882 Incorrect EINJ table references/link Table 18-404
6.2 B 1894 SRAT GICC Flags Field Deﬁnition Errata Table 5-76
6.2 B 1905 Missing description in 6.1.9 title in ACPI 6.2a Section 6.1.9
6.2 B 1909 Update NFIT SPA Range Structure Table 5-132
6.2 B 1929 Miscellaneous Errata Section 19.6.38, Section 19.6.53, Sec-
tion 19.6.54, Removed redundant In-
terrupt section (now Section 19.6.63)
6.2 B 1945 NFIT_SPA_ECR Section 5.2.25.2
6.2 B 1951 _PXM Clariﬁcations Section 5.2.16, Section 5.2.16.6, Sec-
tion 6.2.14, Section 6.2.15, Section
17.2, Section 17.2.1, Section 17.3,
Section 17.3.1, Section 17.4, Section
17.4.1
6.2 B 1960 PWR_BUTTON desription should say “power
button”, not “sleep button”Table 5-34
6.2 B 1962 Clariﬁcations for the use of _REG methods Section 6.5.4
6.2 B 1965 Clean up Address Space ID Table 5-25, Table 6-238, Section
19.6.114, Section 19.2.7
CONTENTS xlixAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.2 B 1968 Clariﬁcations for ACPI Namepaths Section 5.2
6.2 A 1839 Missing space in title of ACPI RAS Feature Table
(RASF)Section 5.2, Section 5.2.20, Table 5-
29
6.2 A 1837 Typos in Extended PCC subspaces (types 3 and 4) Section 14.1.6
6.2 A 1831 Add a new NFIT Platform Capabilities Structure Section 5.2.25.1, Figure 5-22, Table
5-131, Section 5.2.25.9
6.2 A 1827 PPTT ID Type Structure offsets Section 5.2.29.3
6.2 A 1825 Remove bits 2-4 in the Platform RAS Capabilities
Bitmap tableSection 5.2.20.4
6.2 A 1820 Region Format Interface Code description Section 5.2.25.6
6.2 A 1819 Remove support for multiple GICD structures Section 5.2.12, Section 5.2.12.1

29
6.2 A 1814 PDTT typos and PPTT reference Revision History, Section 5.2, Section
5.2.28
6.2 A 1812 Minor correction to Trigger Action Table Section 18.6.4
6.2 A 1811 General Purpose Event Handling ﬂow Section 5.6.4
6.2 1795 ACPI Table Signature Reservation Table 5-30
6.2 1781 Clarify ResourceUsage Descriptor Argument Table 6-193
6.2 1780 Add DescriptorName to PinFunction and PinCon-
ﬁg MacrosSection 19.6.102 and Section
19.6.103
6.2 1770 Update Revision History Revision History
6.2 1769 FADT Format: ACPI Version update to reﬂect 6.2
versus 6.1Table 5-33
6.2 1755 Deprecate PCC Platform Async Notiﬁcations Section 14.4, and Section 14.5.1
6.2 1743 PinGroupFunctionConﬁg resource descriptors up-
dateSection 6.4.3.11, Section 6.4.3.12,
Section 6.4.3.13
6.2 1738 PCIEXP_WAKE Bits description updates Table 4-15, Table 4-16, and Table 5-
34
6.2 1731 Software Delegated Exception HW error notitica-
tionSection 18-394
6.2 1725 NVST Updates - NFIT ARS Error Injection Section 9.20.7.9, Section 9.20.7.10,
and Section 9.20.7.11
6.2 1724 NVST Updates - Platform RAS Capabilities Up-
datesSection 5.2.20.4
6.2 1723 NVST Updates - Translate SPA DSM Interface Section 2.1, Section 9.20.7.8
6.2 1722 NVST Updates - ARS Updates Section 2.1, Section 9.20.7.2, Section
9.20.7.4, Section 9.20.7.5, and Sec-
tion 9.20.7.6
6.2 1721 NVST Updates - Labels Section 2.1, Section 5-184, and Sec-
tion 6.5.10
6.2 1717 ASL Grammar Update for Reference Operators Section 19.2
6.2 1714 Reserve the table name “SDEI” Table 5-30
6.2 1705 Add Heterogeneous Memory Attributes Tables
(HMAT)Section 5.2, Section 5.6.6, Section
5.6.8, Section 6.2, Section 6.2.18, and
Section 17.4
6.2 1703 Time & Alarm Device _GCP new bits Section 9.18.2
6.2 1680 Pin Group, Pin Group Function and Pin Group
Conﬁguration Descriptors and MacrosTable 6-224 and Section 6.4.3.10
6.2 1679 Pin Conﬁguration Descriptor and Macro Table 6-224 and Section 6.4.3.10
6.2 1677 CPPC Registers in System Memory Section 6.2.11.2 and Section 8.4.7.1
6.2 1674 GHES_ASSIST Proposal Section 18.3.2
CONTENTS lAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.2 1669 FADT HEADLESS ﬂag should be valid for
HW_REDUCED_ACPI platformsSection 5.2.9
6.2 1667 Processor Properties Topology Table (PPTT) Section 5.2.29
6.2 1659 Master Slave PCC channels Chapter 14, Platform Communica-
tions Channel (PCC)
6.2 1656 SRAT Support for ITS Section 5.2.16
6.2 1650 CPPC Support for Multiple PCC Channels Table 6-200 and Section 8.4.7.1.9
6.2 1649 ECR: Minor updates to IA-32 Architecture De-
ferred Machine CheckSection 18.3.2.10
6.2 1645 Add _STR Support for Thermal Zones Section 6.1, Section 6.1.10, Section
11.4, Section 11.4.14, and Section
11.7.1
6.2 1632 Secure Devices Table (SDEV) Table 5-30
6.2 1611 Add a _PPL object to processor devices Section 8.4.7
6.2 1597 ASL For() Conditional Loop Macro Section 19.6.51, Section 19.2.5, Sec-
tion 19.2.6, and Section 19.3.4
6.2 1588 Clariﬁcation on Interrupt Descriptor Usage for
“Interrupt Combining”Section 6.2.11.2, Section 6.4.3.6, Sec-
tion 19.6.62
6.2 1585 Reserve table signature “WSMT, ” with reference
to ACPI links page for more detailsTable 5-30
6.2 1583 Diverse Highest Processor Performance Table 5-158 and Table 6-200
6.2 1578 Function Conﬁg Descriptor and Macro Table 6-213 and Section 6.4.3.9
6.2 1576 Platform Debug Trigger Table (PDTT) Section 5.2.28
6.2 1573 Extensions to the ASL Concatenate operator Section 19.2.6 and Section 19.6.12
6.2 1569 Add new introduction (background) section Background chapter
6.1 Errata A 1796 Clarify that Type 1 can never support Level trig-
gered platform interruptSection 14.1.4
6.1 Errata A 1785 Lack of clarity on use of System Vector Base on
GICD structuresSection 5.2.12.15
6.1 Errata A 1783 Clariﬁcation on Interrupt Descriptor Usage for Bit
[0] Consumer/ProducerTable 6-237
6.1 Errata A 1760 Typo - incorrect bit offsets in the PM1 Enable Reg-
isters Fixed Hardware Feature Enable Bits table.Table 4-16
6.1 Errata A 1758 Minor Errata in ERST tables, Serialization In-
struction Entry and Injection Instruction Entry.Table 18-399 and Table 18-405
6.1 Errata A 1756 Errata: Ensure non-secure timers are accesible to
non-secure in the Flag Deﬁnitions: Common Flags ta-
ble.Table 5-126
6.1 Errata A 1740 Errata in section 9.13: wrong reference Section 9.13
6.1 Errata A 1715 0 is a valid GSIV for the secure EL1 physical timer
in GTDTTable 5-120
6.1 Errata A 1687 Typo in the Reserved ﬁeld of the GIC ITS Struc-
ture table.Table 5-66
6.1 Errata A 1686 Clariﬁcation of the FADT HW_REDUCED_ACPI
ﬂag description in the FADT Format table.Table 5-33
6.1 Errata A 1676 Clariﬁcations for the ASL Buffer (Declare Buffer
Object)Section 19.6.10
6.1 Errata A 1671 Typo in Memory Afﬁnity Structure table Section 5-72
6.1 Errata A 1670 Update for _OSI return value Section 5.7.2
6.1 Errata A 1664 Clariﬁcation of the RSDP Structure table, Revi-
sion description.Table 5-66
CONTENTS liAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.1 Errata A 1662 Clariﬁcation of the Generic Communications
Channel Command Field table.Table 14-370
6.1 Errata A 1661 typos in the Generic Communications Channel
Status Field table and the Platform Notiﬁcation section.Table 14-371 and Section 14.5
6.1 Errata A 1660 type in the Generic Communications Channel
Shared Memory Region tableTable 14-369
6.1 Errata A 1651 LPI Clariﬁcations Section 8.4.4.3
6.1 Errata A 1644 Mismatch of mantis number 1449 vs. change de-
scriptionRevision History
6.1 Errata A 1643 Incorrect row order in
GET_EXECUTE_OPERATION_TIMINGS tableTable 18-397
6.1 Errata A 1642 Clariﬁcations and ﬁxes to _PSD and _TSD Table 5-184
6.1 Errata A 1639 _WPC and _WPP are missing in the Predeﬁned
ACPI Names table.Table 5-164
6.1 Errata A 1616 Clarify which processor ID to use in the EINJ for
ARMTable 18-403
6.1 Errata A 1606 Errata: typos in the Interrupt Resource Descriptor
Macro deﬁnitionSection 19.6.62
6.1 Errata A 1602 Updates to the PMC Method Result Codes table Table 10-338
6.1 Errata A 1601 Typos in the _CPC Implementation Example Section 8.4.7.1.11
6.1 Errata A 1600 Typos in PCC Subspace Structure Type 1 and Type
2.Table 14-366 and Table 14-367
6.1 Errata A 1599 Add clariﬁcation to existing text (_OSC Control
Field via arg3)Table 6-202
6.1 Errata A 1591 ASL grammar clariﬁcation for “executable” AML
opcodesSection 5.4
6.1 Errata A 1589 Wireless Power Calibration Device ACPI ID not
deﬁnedSection 10.5 (Table 10-292 removed)
and Table 5-163
6.1 Errata A 1582 Clariﬁcation for Time and Alarm wake description Section 9.18.1
6.1 Errata A 1581 Processing Sequence for Graceful Shutdown Re-
quest - need to update section 6.3.5.1 to reﬂect changeTable 5-166 and Section 6.3.5.1
6.1 Errata A 1579 typos Table 5-130 and Table 5-131
6.1 Errata A 1577 BGRT Image Orientation Offset Table 5-107
6.1 Errata A 1572 Update ASL grammar to support multiple Deﬁni-
tion BlocksSection 19.2.3
6.1 Errata A 1571 Update AML Filename description for ASL Deﬁ-
nitionBlock operatorSection 19.6.28
6.1 Errata A 1552 GIC Redistributor base address language in GICC
leaves room for ambiguityTable 5-60
6.1 Errata A 1549 Errata: wrong offset in Generic Communications
Channel Shared Memory Region table.Table 14-369
6.1 1527 Qualcomm feedback on ACPI 6.1 draft 2 Throughout
6.1 1524 Strange hotlink Section 5.7.5
6.1 1514 Comments against 6.1 Draft from HPE Minor corrections and ﬁxed typos
throughout document, especially Sec-
tion 9.20.7.2
6.1 1512 Microsoft feedbacks on ACPI 6.1 draft 2 Section 5.2.25, Section 9.20.7, Sec-
tion 18.3.2
6.1 1503 Editorial comments against 6.1 Draft 1 Throughout–draft corrections & typos
6.1 1500 ACPI 6.1 - Graceful Shutdown (Device Object
Notiﬁcation)Table 5-166
CONTENTS liiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.1 1499 _FIT and _MAT ASL nits in 6.0 and 6.1 Draft Section 6.2.10, Section 6.5.9
6.1 1490 ACPI Version update to reﬂect 6.1 versus 6.0 Table 5-33
6.1 1483 NFIT SPD extensions and clariﬁcations Section 5.2.25x, Section 6.5.9, Sec-
tion 9.20x
6.1 1478 Wireless Power Calibration ACPI Device Section 10.5 & Section 10.6
6.1 1427 Addition to Memory Device State Flags in NFIT Table 5-133
6.1 1395 _DSM interfaces associated with NVDIMM-N
objectsSection 9.20.2x through Section
9.20.7
6.1 1384 ERST/EINJ max wait time Table 18-397, Table 18-404
6.1 1367 Interrupt-signaled Events Section 4.1.1.1 Section 5.6, , Section
5.6.10, Section 5.6.4, Section 5.6.5
Section 5.6.5.2, Section 6.2.11.2, Sec-
tion 7.3.13, Section 18.3.2.7.2, Sec-
tion 18.4, and added
6.1 1356 ARM APEI extensions Section 18.3.2.7, Section 18.3.2.8,
Section 18.3.2.9
6.1 1326 Section 2.2, Table 5-37, Section
7.4.2.5, Section 15, Table 15-374,
Section 16.1.4
6.0 Errata 1488 Typo on description of PkgLength encoding
(ACPI v6.0, section 5.4)Section 5.4

tion 9.20x
9.20.7
6.0 Errata 1487 The Length of GIC ITS Structure is wrong Table 5-66
6.0 Errata 1470 Region Format Interface Code clariﬁcation Table 5-137
6.0 Errata 1462 5.2.21 Errata Section 5.2.21
6.0 Errata 1461 5.2.21.10 Clariﬁcation Section 5.2.21.10
6.0 Errata 1449 Graceful Shutdown Request (Device Object Noti-
ﬁcation Values)Section 2.1, Table 5-44, Section
5.2.12.6, Table 5-51, Section 5.2.12.9,
Section 5.2.12.14 through Section
5.2.12.18, Section 5.2.25, Section 5.6,
Table 6-193, Table 6.2.10, Table 6-
249, Table 6.5.9
6.0 Errata 1445 Section 19.6.99 “Package” of the speciﬁcation
needs updatingSection 19.6.100
6.0 Errata 1444 GTDT CntReadBase Physical address should be
optionalSection 5.2.24
6.0 Errata 1433 Time and Alarm _GCP changes in support of
wakes from S4/S5Section 9.18.2
6.0 Errata 1432 Errata - Explicit Data Type Conversions Section 19.3.4, Section 19.3.5.2, Sec-
tion 19.3.5.3
6.0 Errata 1406 NFIT RAMDisk Update Section 5.2.25.2
6.0 Errata 1403 Two distinct deﬁnitions of the MADT have the
same revision numberTable 5-43
6.0 Errata 1393 In FADT: if X_DSDT ﬁeld is non-zero, DSDT
ﬁeld should be ignored or deprecatedTable 5-33
6.0 Errata 1392 Incorrect length in the GIC ITS Structure Table 5-66
6.0 Errata 1386 Clarify APEI vs UEFI runtime variable support Table 18-397
6.0 Errata 1385 ACPI 6.0 typo and table misnumbering Section 18.5.2.1
6.0 Errata 1380 Unnecessary restrictions to FW vendors in order-
ing of GIC structures in MADTSection 5.2.12.14
6.0 Errata 1378 Duplication of table 5-155/156, section mismatch
in GIC redistributorTable 5-175 & Table 5-180 duplicates
removed, Section 5.2.12.17
CONTENTS liiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.0 Errata 1374 section mismatch: _CCA method belongs to sec-
tion 6.2 Device Conﬁguration Objects?Table 6-189/Table 6-193
6.0 Errata 1372 Fix inconsistency for _PXM method in section 17 Section 17.2.1, Section 17.3.2
6.0 Errata 1368 Various errata ﬁxes and clariﬁcations in chapter 18
APEISection 18.3.1, Section 18.3.2.7.1,
Section 18.5.1, Section 18.6.1, Sec-
tion 18.6.2, Section 18.6.4
6.0 Errata 1361 Clarify _PIC Method on ARM Section 5.8.1
6.0 Errata 1289 replace use of the term “BIOS” with more accurate
descriptionsThroughout spec
6.0 Errata 1154 Ensure that ACPI and UEFI specs agree on the
treatment of “holes” in the memory mapSection 15.4
6.0 1344 Sharing of Connection Resources, NOTE: The
changes were included in ACPI 6.0, but was missed in
the ACPI 6.0 Revision HistorySection 5.5.2.4.6 through Section
5.5.2.4.6.3.9 Section 19.6.15
6.0 1370 Changes needed for ACPI 6.0: persistent memory
S4 behaviorSection 16.3.4
6.0 1359 Vendor Range for E820 Address Types and UEFI
memory TypesTable 15-374
6.0 1354 Disambiguation of _REV Section 5.7.4
6.0 1343 Comments against v6.0 Final Draft Section 18.6.2, Section 18.6.4
6.0 1340 comment against the Final Draft: Minor errata in
register ﬁelds of LPI exampleSection 8.4.4.3.4
6.0 1332 Fixes for ACPI 6.0 Draft March 2 Table 5-37, Section 5.2.25.2, Table 5-
132
6.0 1328 ACPI 6.0 Draft feedback - Mantis 1228 Table 5-62
6.0 1337 Missing reference in Extended Address Space De-
scriptor Deﬁnition, Section 6.4.3.5.4Section 6.4.3.5.4
6.0 1333 ACPI 6.0 March2 Draft Feedback - Bits and NFIT
relatedNFIT throughout
6.0 1329 ACPI 6.0 Feb 18 Draft - Follow consistent notation
for Bits and Bytes rangesthroughout
6.0 1327 ACPI 6.0 Feb 18 draft feedback - NFIT related NFIT throughout
6.0 1324 ACPI 6.0 Feb 5 Draft1 Feeback2 - Mantis 1250 Section 5.2, Section 5.2.25, Section
6.1.1, Section 5.6.6
6.0 1320 ACPI 6.0 Feb 5 Draft1 Feedback - Mantis 1250 Section 5.2, Section 5.2.25, Section
6.0 1319 Comment against ACPI 6.0 Draft 1 concerning
Mantis 1279Section 19.1, Section 19.6.3, Sec-
tion 19.6.5, Section 19.6.26, Sec-
tion 19.6.31, Section 19.6.60, Sec-
tion 19.6.61Section 19.6.68 - Sec-
tion 19.6.74, Section 19.6.78Section
19.6.85, Section 19.6.86, Section
19.6.92
6.0 1312 Add USB-C Connection support to _UPC Table 9-293, Section 9.14
6.0 1306 New ACPI Version Placeholder Table 5-33
6.0 1302 Errata on reference in section 6.2.11.2 Platform-
Wide OSPM CapabilitiesSection 6.2.11.2
6.0 1294 Typo in section 5.7.2: “Section” used when “Ta-
ble” was meantSection 5.7.2
6.0 1293 Reserve “STAO” and “XENV” table signatures Table 5-30
6.0 1292 A Missing space in ﬁrst paragraph of Section 2.4 Section 2.4
CONTENTS livAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.0 1284 Battery ACPI ECR Section 5-184, Section 10.2.2.7, Table
10-329, Section 10.2.2, Table 10-331
6.0 1282 AML: Improve Disassembly of Control Method
InvocationsSection 19.6.44, Section 20.2.5.2,
Section 20-440
6.0 1281 ASL Printf and Fprintf Debug MacrosTable 10-
331Table 10-331Section 19.2.5, Section 19.2.6, Sec-
tion 19.3.4, Section 19.3.5.2, Section
19.3, Section 19.4, Section 19.6.52,
Section 19.6.107
6.0 1280 ASL Helper Macro for _PLD (Physical Location
of Device) - ToPLD()Section 19.2.6, Section 19.3.4, Sec-
tion 19.3.5.2, Section 19.4, Section
19.5, Section 19.6.140
6.0 1279 ASL Extensions for Symbolic Operators and Ex-
pressions (ASL 2.0)Section 19.1, Section 19.6.3, Sec-
tion 19.6.61, Section 19.6.68 - Sec-
tion 19.6.74, Section 19.6.78, Sec-
tion 19.6.85, Section 19.6.86, Section
19.6.92
6.0 1265 Missing word in ﬁgure 1-1 Figure 1-1
6.0 1264 Device Power Management Clariﬁcations Section 2.3, Section 2.3.1, Section
3.3.1, Section 3.3, Section 3.4, Sec-
tion 3.4.2, Section 3.4.3, Section
3.4.3, Section 3.4.4x), Section 7, Sec-
tion 7.1, Section 7.2x, Section 7.3
6.0 1262 New Thermal Zone Objects Table 5-184, Section 11.1.5.1, Section
11.4.8, Section 11.4.21
6.0 1261 _OSC, add OS–>Platform information to commu-
nicate >16 p-states are supportedTable 6-200
6.0 1258 Standby Thermal Trip Section 11.4.5
6.0 1253 Clariﬁcation of S5 (Soft-Off) and S1~S4 Sleeping
StatesSection 2.4, Section 3.9.4, Section
4.7, Section 4.8.2.3, Section 4.8.3.2.1,
Section 7.3.1
6.0 1252 Incorrect Indentation in ﬁrst page of Section 3 Section 3
6.0 1250 Support for Non-V olatile Memory Firmware Inter-
facesSection 5.2, Section 5.2.25, Section
6.0 1241 PCC and level interrupts for HW reduced plat-
formsSection 14.1.2, Section 14.1.5
6.0 1232 Deprecate Processor Keyword Table 5-46, Table 5-52, Section
5.2.12.10, Section 5.2.12.12, Section
8.4, Section 11.7.1, Section 11.7.2,
Section 19.6.30, Section 19.6.108
6.0 1231 Adjust max p-states Section 2.6
6.0 1230 Adding Support for Faster Thermal Sampling Table 6-200, Table 5-184, Section
11.4.17, Section 11.4.22, Section 11.6
6.0 1229 Reserve IORT and support for ARM GICv3/4 ITS
in MADTTable 5-29, Table 5-45, Section
5.2.12.18
6.0 1206 Clarify _HID/_CID/_CLS usage model Section 6.1, Section 6.1.5, Section
6.2x
6.0 1203 CPPC heterogeneous performance capabilities Section 8.4.7, Section 8.4.7.1.10
6.0 1197: MADT Efﬁciency Classes and wording change
for MP Parking updateTable 5-60
CONTENTS lvAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.0 1176 FADT Hypervisor Vendor Identiﬁcation Support Table 5-33
6.0 1171 Extend Address Ranger Types and UEFI Memory
Type to comprehend persistent memory.Table 5-37, Section 6.4.3.5.4.1, Sec-
tion 15, Table 15-379, Section 15.4,
Table 15-380
6.0 1152 Support for Platform-speciﬁc device reset Section 7.3.25 and Section 7.3.26 t,
Table 7-255 Table 7-256
6.0 1132 Generic Button(s) Abstraction Table 5-183, Add new Section 9.19
and following
6.0 1125 ACPI Low Power Idle Table (LPIT) and _LPD
proposalSection 5.6.7, Section 5.6.8, Table
6-200, Section 7.1, Section 7.2.5,
Section 7.4.2.1, Section 8.4, Section
8.4.1, Section 8.4.2, Section 8.4.2.1,
Section 8.4.3.1
5.1 Errata 1265 Missing word in ﬁgure 1-1 Figure 1-1
5.1 Errata 1252 Incorrect Indentation in ﬁrst page of Section 3 Section 3
5.1 Errata 1243 Clarify whether or not the FACS is optional or not Section 5.2.9, Table 5-33
5.1 Errata 1233 Fix broken Link and Example for _CLS Section 6.1.3
5.1 Errata 1228 Present GIC version in MADT table Table 5-62
5.1 Errata 1196 Table reference in Section 9.8.3.2 is Incorrect Section 9.9.3.2
5.1 Errata 1193 Parking protocol ﬁeld link is incorrect Section 5.2.12.14, Table 5-60
5.1 Errata 1190 Table references in Section 18 - ACPI Platform
Error Interfaces (APEI) are incorrectTable 18-383, Table 18-385
5.1 Errata 1189 _CCA attribute default value description does not
work for ARM systemsSection 6.2.17
5.1 1181 MADT GICC table deﬁnition is wrong Table 5-61, 5.2.12.14
5.1 1180 FADT minor version byte length is wrong May-34
5.1 1179 Errors in GTDT Section of 5.1 draft 5.2.24, 5.2.24.1, Tables 5-115, 5-118,
5-121, 5-122
5.1 1175 Bad section reference in ACPI 5.1 19.2.3
5.1 1164 Modiﬁcations to UEFI Forum ownership of PNP
ID and ACPI ID Registry6.1.5

5.1 1161 Misc typos in draft documents 5.2.1.6, 5.2.16.4, 5.2.24, 5.2.12.14,
5.2.24.1.1, Table 5-74, Table 5-115-
116, Table 5-118-119, Table 5-121,
Table 5-61, 5-61 8.4.5.1, 8.4.5.1.2.3
Table 6-162, Table 8-229, RM dupli-
cates from 1123/1130:8.4.5.1.31.1
5.1 1160 ACPI 5.1 draft corrections related to _DSD (SEE
#1126)6.2.5, Table 5-148 & 6-157
5.1 1157 Reserve ACPI Low Power Idle Table Signature
“LPIT”Table 5-31
5.1 1155 Updates to M1133 MADT Table 5-63, 5-64
5.1 1151 Bug in ASL example code PRT3 code example following Figure
9-49
5.1 1149 GTDT changes for new GT Conﬁgurations 5.2.24, 5.24.1x
5.1 1136 Add a Notiﬁcation Type for System Resource
Afﬁnity Change EventTable 5-119 Device Object Notiﬁca-
tions, new 17.2.2
5.1 1134 FADT changes for PSCI Support on ARM plat-
formsTable 5-34, 5-36, New table 5-37
5.1 1135 PCC Doorbell Protocol for HW-Reduced Plat-
forms14.1.1, 14.1.2-4, 14.2.1-2, 14.3-4
CONTENTS lviAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.1 1133 MADT Updates for new GICs 5.2.12.15-17, Table 5-43, 5.2.12 table
5-45, 5-60, 5-61, 5-63, 5-66
5.1 1131 Per-device Cache-coherency Attribute 6.2, 6.2.16, Was Table 6-142–>Table
6-153
5.1 1126 Add _DSD Predeﬁned Object– “DeviceSpeciﬁc
Data” propertiesWas Table 5-133 & 6-142 now–>5-
148 & 6-157
5.1 1123 CPPC Performance Feedback Counter Change,
1130 CPPC2, [overlapping/duplicate tickets]Tables 5-126, 8.4.5, 8.4.5.1x , 8.4.5.1,
8.4.5.1.3.1-4
5.1 1116 Add x2APIC and GIC structure for _MAT method 6.2.10
5.0 B 1145 Support GICs in proximity domain 5.2.16 5.2. new section 16.4 new ta-
bles, 6.2.13 Table 5-65
5.0 B 1144 Fix the gap for Notify value description 5.6.6, new tables: Table 5-132, 5-133
5.0 B 1142 Error Source Notiﬁcations 18.3.2.6.2, 18.4, Table 18-290
5.0 B 1117 Move http://acpi.info/links.htm content to UEFI
Forum Website1.10, 5.2.4, 5.2.22.3, 5.2.24, 5.6.7,
9.8.3.2, 13, 13.2.2 A.2.4, A.2.5, Ta-
bles 5-31, 5-60, 5-133
5.0 B 1113 Typos in ACPI 5.0a Table 6-184
5.0 B 1148 Inconsistent BIX object description/example Was Table 10-234–>10-250
5.0 B 1143 Typos in ACPI 5.0a 6.1.8, 8.4.1
5.0 B 1102 Clarify Use of GPE Block Devices in Hardware-
Reduced ACPI3.11.1, 4.1, 9.10
5.0 B Mantis 1114 Lack of description on Bit 4 of _STA 6.3.7
5.0 A Jira 51 incorrect type information Table 19-322
5.0 A Jira 50 Misspelling of “management” 3.1
5.0 A Jira 49 Updated description of DerefOf to specify be-
havior when attempt is made to de-reference a reference
(via Index) to a NULL (empty) package element.19.5.29
5.0 A Jira 48 Text changes to change PM Timer from required
to optional4.8.1.4, 4.8.2.1, 4.8.3.3, 5.2.9
5.0 A Jira 46 Figure 5-29 is a printer killer Fig 5-29
5.0 A Jira 45 Typos in Figure 5-30 Fig 5-30
5.0 A Jira 44 Link issues in table 5-133 Table 5-133
5.0 A Jira 43 Invalid AddressSpaced keywords in example
ASL code, orphan _REG6.5.4
5.0 A Jira 42 Serious bug in ASL example code for _OSC 6.2.10.4
5.0 A Jira 41 Fix problems with PCC address space descrip-
tion14.5
5.0 A Jira 40 Issues with _GRT and _SRT Buffer description 9.18.3, 9.18.4
5.0 A Jira 39 Clariﬁcation needed for _CST Table 8-206
5.0 A Jira 38 Incorrect ﬁeld name in “Generic Register De-
scriptor”.6.4.3.7
5.0 A Jira 37 Clariﬁcations for _CPC method 8.4.5.1.2.1-2
5.0 A Jira 36 Restore legality of module-level executable
AML code.19.1.3
5.0 A Jira 35 ASL grammar: “UserTerm” is confusing 19.1
5.0 A Jira 34 Description of _GTM has a bad line with very
large font9.8.2.1.1
5.0 A Jira 33 Missing information in _CPC description 8.4.5.1
5.0 A Jira3 2 Error in description of _REG method 6.5.4
5.0 A Jira 31 Clarify length ﬁeld for Serial resource descriptor 6.4.3.8.2, Table 6-190
CONTENTS lviiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.0 A Jira 30 Argument descriptions in incorrect order for re-
source descriptors19.5.41, 19.5.101
5.0 A Jira 29 Issues with memory descriptors (grammar and
macros)19.1, 19.5
5.0 A Jira 28 Problems with ASL grammar entry for DWord-
Memory19.1.8
5.0 A Jira 27 Problems with Unicode description for _MLS
method6.1.7
5.0 A Jira 26 Incorrect grammar for “32-bits” and “64-bits” Throughout spec
5.0 A Jira 25 Incorrect table reference in 19.2.5.4 19.2.5.4
5.0 A Jira 24 Resource Descriptor tables – formatting issues 6.4
5.0 A Jira 23 Interrupt Descriptors: Wake bit should be split
from Share bit6.4
5.0 A Jira 22 ASL grammar for ObjectType operator is incor-
rect19.1.6
5.0 A Jira 21 ASL grammar is missing description of type 6
opcodes19.1.5
5.0 A Jira 20 Problems with table 5-31 (reserved ACPI table
signatures)Table 5-31
5.0 A Jira 19 Clarify description of _BQC method B.5.4
5.0 A Jira 18 Fix for EC OpRegion availability example 5.2.15
5.0 A Jira 17 Clarify meaning of BGRT status ﬁeld Table 5-97
5.0 A Jira 16 Correction to _DSM example 9.14.1
5.0 A Jira 15 Clarify _DSM backward compatibility require-
ment and example9.15.1
5.0 A Jira 14 Description of _CPC is missing deﬁnition of un-
supported optional registers8.4.5.1
5.0 A Jira 13 Incorrect _PLD name expansion Table 5-133, 6.1.8
5.0 A Jira 12 PLD description needs clariﬁcation 6.1.8
5.0 A Jira 11 Errata forwarded from HP 5.2.24, 5.6.5.3
5.0 A Jira 10 More issues with ACPI table 5-133 Table 5-133
5.0 A Jira 7 Error in QWordIO, ExtendedIO descriptions 19.5.41, 19.5.101
5.0 A Jira 6 Appendix A is now misnamed in ACPI 5.0 Appendix A
5.0 A Jira 5 PARTIAL–Need group agreement–Method _GTS
and _BFS are unused, should be removed from ACPI
spec.7.3, 7.3.3, 16.1, 16.1.6-7, ﬁg. 7-204
5.0 A Jira 4 Table 5-133 - issues with _Sx methods Table 5-133
5.0 A Jira 3 Issues with predeﬁned names table (table 5-133) Table 5-133
5.0 A Jira 2 Description of new sleep control register incorrect Table 4-24
5.0 A Jira 1 SystemCMOS keyword inconsistencies Table 5-114, 5.5.2.4.1, 6.5.4 19, 5.96,
9.15.1-2, 19.5.96, 20.2.5.2
5.0 Ptec-002 5.2.6
5.0 MSFT-020 Enumeration Power Controls 7.2.7, 7.2.12
5.0 MSFT-019 GTDT table 5.2.24
5.0 MSFT_0018 Locking Targets from AML 5.7.5
5.0 MSFT-0017 PLD clariﬁcation for handhelf form factors 5.1.8
5.0 MSFT-0016 Extended GPIO-signaled Event Numbers 5.6.5.3
5.0 MSFT-0015 (0.1) D3 Cold Errata 7.2.1, 7.2.18 through 7.2.22
5.0 MSFT-0014 5.2.23
5.0 MSFT-0013_ADR for SIO 6.2
5.0 MSFT-0012 ROM (Get ROM Data) 5.6.6, 9.16
CONTENTS lviiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.0 MSFT-010 Reserved Table Signatures 5.2.6
5.0 MSFT-0009 (0.4)TimeAndAlarmDevice Modiﬁcation 9.18
5.0 MSFT-0008 Collaborative Processor Performance Con-
trol8.4.5
5.0 MSFT-0007 Platform Communications Channel added
(new ch. 14)Ch 14 (new)
5.0 MSFT-0007-0008 Platform Communication Channel
and CPPC changesCh 14 (new)
5.0 MSFT-0006 SPB Abstraction 3.11.3, 5.5.2.4.5.x, 6.4.3.8.2, 6.5.8,
18.1.3, 18.1.6, 18.1.7, 18.5.44, 18.5x,
19.2.5.2
5.0 MSFT-0005 GPIO Abstraction 5.5.2.4.x, 5.6, 5.6.5.x, 6.4.3, 6.3.8.x,
18.5.51, 18.5.52, 18.5.89
5.0 MSFT-0004 (0.2) Fixed DMA Descriptor 6.4.2.9, 18.5.50
5.0 MSFT-0003 Device identiﬁcation 6.1, 6.1.3, 6.1.5, 6.1.6, 6.1.9
5.0 MSFT-0002 Interrupt Descriptors for Generic Interrupt
Controller5.2.11, 5.2.14-15
5.0 MSFT-0001 HW-reduced ACPI 3.11.x, 4, 4.1.x, 4.3.7, 5.2.9, 5.2.9.1,
6.4.2.1, 6.4.3.6, 7.2.11, 7.3.4, 9.6, 12,
12.1, 12.6, 12.11, 12.11.1, 15, 15.1.x,
15.3, 15.3.1.x, 18.5.55, 18.5.57
5.0 INTC-0014 Remove a line (reference) not needed A.2.3
5.0 INTC-0013 n/a
5.0 INTC-0012 ﬁx AML opcode table 19.3
5.0 INTC-0011 ﬁx table offsets 18.6.x (tables)
5.0 INTC-0010 Update Constant Descriptions 18.5.88, 18.5.89, 18.5.104, 18.5.136
5.0 INTC0009 RASF 5.2.20.x
5.0 INTC-008 5.2.6
5.0 INTC-006 Fixed Example 6.2.10.4
5.0 INTC-005 Update Package Description 18.5.92
5.0 INTC-004 Table Deﬁnition Language 20, 21.x
5.0 INTC-003 MPST 6.1, 6.1.3, 6.1.5, 6.1.6, 6.1.9
5.0 INTC-002 EINJ 17.6.1, 17.6.3, 17.6.5
5.0 INTC-001 (0.8) Firmware Performance Data Table
(FPDT)5.2.20.4, 5.2.20.6
5.0 INTC-001 Firmware Performance Data Table (FPDT)
(0.4)5.2.19- 5.2.20.6
5.0 HP-0002 Additional Hardware Error Notiﬁcation Types 18.3.2.7
5.0 HP-0001 (0.2) BMC Requested Graceful Shutdown 5.6.5, 6.3.5
5.0 ACPI4.0 _DSM function 0 clariﬁcation 9.14.1
5.0 AMD-002 0.3 ROM (Get ROM Data) B.3.3
4.0a Errata corrected and clariﬁcations added. 2.2, 5.2.6, 5.2.12.4, 5.2.18,
5.5.2.4.3.1, 5.6.5, 5.6.6, 5.6.7, 6.4.2.8,
6.4.3.5.1-3, 6.5.7, 8.4.3.4, 8.4.4.5,
8.4.5, 9.2.5, 9.8.2.1.1, 9.10, 9.13,
10.4.1, 10.1.3.1, 10.2.2, 10.2.1.1-2,
10.2.2.8, 10.2.2.9, , 10.3, 10.3.3,
10.4, 10.3.4, 10.4.1, 10.5, 15.1,
17.1, 17.3.1, 17.3.2.6.1, 17.3.2.6.2,
17.4, 17.5.1.1, 17.6.1, 17.6.3, 18.1.8,
18.5.44, 18.5.89, 18.5.101
CONTENTS lixAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
4.0 Major speciﬁcation revision. Clock Domains, x2APIC
Support, Logical Processor Idling, Corrected Platform

Error Polling Table, Maximum System Characteristics
Table, Power Metering and Budgeting, IPMI Operation
Region, USB3 Support in _PLD, Re-evaluation of _PPC
acknowledgement via _OST, Thermal Model Enhance-
ments, _OSC at _SB, Wake Alarm Device, Battery Re-
lated Extensions, Memory Bandwidth Monitoring and
Reporting, ACPI Hardware Error Interfaces, D3hot.n/a
3.0b Errata corrected and clariﬁcations added. n/a
3.0a Errata corrected and clariﬁcations added. n/a
3.0 Major speciﬁcation revision. General conﬁguration en-
hancements. Inter-Processor power, performance, and
throttling state dependency support added. Support for
> 256 processors added. NUMA Distancing support
added. PCI Express support added. SATA support
added. Ambient Light Sensor and User Presence de-
vice support added. Thermal model extended beyond
processor-centric support.n/a
2.0c Errata corrected and clariﬁcations added. n/a
2.0b Errata corrected and clariﬁcations added. n/a
2.0a Errata corrected and clariﬁcations added. ACPI 2.0 Er-
rata Document Revision 1.0 through 1.5 integrated.n/a
2.0 Errata
Rev. 1.5Errata corrected and clariﬁcations added. n/a
2.0 Errata
Rev. 1.4Errata corrected and clariﬁcations added. n/a
2.0 Errata
Rev. 1.3Errata corrected and clariﬁcations added. n/a
2.0 Errata
Rev. 1.2Errata corrected and clariﬁcations added. n/a
2.0 Errata
Rev. 1.1Errata corrected and clariﬁcations added. n/a
2.0 Errata
Rev. 1.0Errata corrected and clariﬁcations added. n/a
2.0 Major speciﬁcation revision. 64-bit addressing support
added. Processor and device performance state sup-
port added. Numerous multiprocessor workstation and
server-related enhancements. Consistency and readabil-
ity enhancements throughout.n/a
1.0b Errata corrected and clariﬁcations added. New inter-
faces added.n/a
1.0a Errata corrected and clariﬁcations added. New inter-
1.0 Original Release. n/a
CONTENTS lxAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Overview
The following provides a high-level overview of the Advanced Conﬁguration and Power Interface (ACPI). To make
it easier to understand ACPI, this section focuses on broad and general statements about ACPI and does not discuss
every possible exception or detail about ACPI. The rest of the ACPI speciﬁcation provides much greater detail about
the inner workings of ACPI than is discussed here, and is recommended reading for developers using ACPI.
History of ACPI
ACPI was developed through collaboration between Intel, Microsoft*, Toshiba*, HP*, and Phoenix* in the mid-1990s.
Before the development of ACPI, operating systems (OS) primarily used BIOS (Basic Input/Output System) interfaces
for power management and device discovery and conﬁguration. This power management approach used the OS’s
ability to call the system BIOS natively for power management. The BIOS was also used to discover system devices
and load drivers based on probing input/output (I/O) and attempting to match the correct driver to the correct device
(plug and play). The location of devices could also be hard coded within the BIOS because the platform itself was
non-enumerable. These solutions were problematic in three key ways. First, the behavior of OS applications could
be negatively affected by the BIOS-conﬁgured power management settings, causing systems to go to sleep during
presentations or other inconvenient times. Second, the power management interface was proprietary on each system.
This required developers to learn how to conﬁgure power management for each individual system. Finally, the default
settings for various devices could also conﬂict with each other, causing devices to crash, behave erratically, or become
undiscoverable.
ACPI was developed to solve these problems and others.
What is ACPI?
ACPI can ﬁrst be understood as an architecture-independent power management and conﬁguration framework that
forms a subsystem within the host OS. This framework establishes a hardware register set to deﬁne power states
(sleep, hibernate, wake, etc). The hardware register set can accommodate operations on dedicated hardware and
general purpose hardware.
The primary intention of the standard ACPI framework and the hardware register set is to enable power management
and system conﬁguration without directly calling ﬁrmware natively from the OS. ACPI serves as an interface layer
between the operating system and system ﬁrmware, as shown in ﬁgure i-1.
Fig. 1: Fig. i-1 - ACPI overview
ACPI deﬁnes two types of data structures that are shared between system ﬁrmware and the OS via the ACPI subsystem:
data tables and deﬁnition blocks (see ﬁgure i-2). These data structures are the primary communication mechanism
between the ﬁrmware and the OS. Data tables store raw data and are consumed by device drivers. Deﬁnition blocks
consist of byte code that is executable by an interpreter.
Upon initialization, the AML interpreter extracts byte code in the deﬁnition blocks as enumerable objects. This
collection of enumerable objects forms an OS construct called the ACPI namespace. Objects in the ACPI namespace
CONTENTS lxiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 2: Fig. i-2 - ACPI Structure
can either have a directly deﬁned value, or be evaluated by the AML interpreter. The AML interpreter, directed by the
OS, evaluates objects and then interfaces with system hardware to perform necessary operations.
The deﬁnition block byte code is compiled from the ACPI Source Language (ASL) code. ASL is the language used
to deﬁne ACPI objects and to write control methods. An ASL compiler translates ASL into ACPI Machine Language
(AML) byte code. AML is the language processed by the AML interpreter, as shown in ﬁgure i-3.
ACPI Source Language (ASL) code is used to deﬁne objects and control methods. Then the ASL compiler translates
ASL into ACPI Machine Language (AML) byte code contained within ACPI deﬁnition Blocks. Deﬁnition blocks
consist of an identifying table header and byte code that is executable by an AML interpreter.
The AML interpreter executes byte code and evaluates objects in the deﬁnition blocks to allow the byte code to perform
loop constructs, conditional evaluations, access deﬁned address spaces, and perform other operations that applications
require. The AML interpreter has read/write access to deﬁned address spaces, including system memory, I/O, PCI
conﬁguration, and more. It accesses these address spaces by deﬁning entry points called objects. Objects can either
have a directly deﬁned value or else must be evaluated and interpreted by the AML interpreter.
This collection of enumerable objects is an OS construct called the ACPI namespace. The namespace is a hierarchical
representation of the ACPI devices on a system. The system bus is the root of enumeration for these ACPI devices.
Devices that are enumerable on other buses, like PCI or USB devices, are usually not enumerated in the namespace.
Instead, their own buses enumerate the devices and load their drivers. However, all enumerable buses have an encoding
technique that allows ACPI to encode the bus-speciﬁc addresses of the devices so they can be found in ACPI, even
though ACPI usually does not load drivers for these devices.
Generally, devices that have a _HID object (hardware identiﬁcation object) are enumerated and have their drivers
loaded by ACPI. Devices that have an _ADR object (physical address object) are usually not enumerated by ACPI and
generally do not have their drivers loaded by ACPI. _ADR devices usually can perform all necessary functions without
involving ACPI, but in cases where the device driver cannot perform a function, or if the driver needs to communicate
to system ﬁrmware, ACPI can evaluate objects to perform the needed function.
As an example of this, PCI does not support native hotplug. However, PCI can use ACPI to evaluate objects and deﬁne
CONTENTS lxiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 3: Fig. i-3 - ASL and AML
CONTENTS lxiiiAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
methods that allow ACPI to ﬁll in the functions necessary to perform hotplug on PCI.
An additional aspect of ACPI is a runtime model that handles any ACPI interrupt events that occur during system
operation. ACPI continues to evaluate objects as necessary to handle these events. This interrupt-based runtime model
is discussed in greater detail in the Runtime model section below.
ACPI Initialization
The best way to understand how ACPI works is chronologically. The moment the user powers up the system, the
system ﬁrmware completes its setup, initialization, and self tests.
The system ﬁrmware then uses information obtained during ﬁrmware initialization to update the ACPI tables as nec-
essary with various platform conﬁgurations and power interface data, before passing control to the bootstrap loader.

The extended root system description table (XSDT) is the ﬁrst table used by the ACPI subsystem and contains the ad-
dresses of most of the other ACPI tables on the system. The XSDT points to the ﬁxed ACPI description table (FADT)
as well as other major tables that the OS processes during initialization. After the OS initializes, the FADT directs
the ACPI subsystem to the differentiated system description table (DSDT), which is the beginning of the namespace
because it is the ﬁrst table that contains a deﬁnition block.
The ACPI subsystem then processes the DSDT and begins building the namespace from the ACPI deﬁnition blocks.
The XSDT also points to the secondary system description tables (SSDTs) and adds them to the namespace. The ACPI
data tables give the OS raw data about the system hardware.
After the OS has built the namespace from the ACPI tables, it begins traversing the namespace and loading device
drivers for all the _HID devices it encounters in the namespace. See ﬁgure i-4.
In the ACPI Intialization diagram above, system ﬁrmware updates the ACPI tables as necessary with information only
available at runtime, before handing off control to the bootstrap loader. The XSDT is the ﬁrst table used by the OS’s
ACPI subsystem, and contains addresses of most other ACPI tables on the system. The XSDT points to the FADT, the
SSDTs, and other major ACPI tables. The FADT directs the ACPI subsystem to the DSDT, which is the beginning of
the namespace because DSDT is the ﬁrst table that contains a deﬁnition block. The ACPI subsystem then consumes
the DSDT and begins building the ACPI namespace from the deﬁnition blocks. The XSDT also points to the SSDTs
and adds them to the namespace.
Runtime Model
After the system is up and running, ACPI works with the OS to handle any ACPI events that occur via an interrupt.
This interrupt invokes ACPI events in one of two general ways: ﬁxed events and general purpose events (GPEs).
Fixed events are ACPI events that have a predeﬁned meaning in the ACPI speciﬁcation. These ﬁxed events include
actions like pressing the power button or ACPI timer overﬂows. These events are handled directly by the OS handlers.
GPEs are ACPI events that are not predeﬁned by the ACPI speciﬁcation. These events are usually handled by evaluat-
ing control methods, which are objects in the namespace and can access system hardware. When the ACPI subsystem
evaluates the control method with the AML interpreter, the GPE object handles the events according to the OS’s im-
plementation. Typically this might involve issuing a notiﬁcation to a device to invoke the device driver to perform a
function.
We discuss a generic example of this runtime model in the next section.
Thermal Event Example
ACPI includes a thermal model to allow systems to control the system temperature either actively (by performing
actions like turning a fan on) or passively by reducing the amount of power the system uses (by performing actions
like throttling the processor). We can use an example of a generic thermal event shown in Figure i-5 to demonstrate
how the ACPI runtime model works.
The ACPI thermal zone includes control methods to read the current system temperature and trip points.
When the OS initially ﬁnds a thermal zone in the namespace, it loads the thermal zone driver, which evaluates the
thermal zone to obtain the current temperature and trip points.
CONTENTS lxivAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 4: Fig. i-4 ACPI Initialization
CONTENTS lxvAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 5: Fig. i-5 Runtime Thermal Event
CONTENTS lxviAdvanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
When a system component heats up enough to trigger a trip point, a thermal zone GPE occurs.
The GPE causes an interrupt to occur. When the ACPI subsystem receives the interrupt, it ﬁrst checks whether any
ﬁxed events have occurred. In this example, the thermal zone event is a GPE, so no ﬁxed event has occurred.
The ACPI subsystem then searches the namespace for the control method that matches the GPE number of the inter-
rupt. Upon ﬁnding it, the ACPI subsystem evaluates the control method, which might then access hardware and/or
notify the thermal zone handler.
The operating system’s thermal zone handler then takes whatever actions are necessary to handle the event, including
possibly accessing hardware.
ACPI is a very robust interface implementation. The thermal zone trip point could notify the system to turn on a fan,
reduce a device’s performance, read the temperature, shut down the system, or any combination of these and other
actions depending on the need.
This runtime model is used throughout the system to manage all of the ACPI events that occur during system operation.
Summary
ACPI can best be described as a framework of concepts and interfaces that are implemented to form a subsystem
within the host OS. The ACPI tables, handlers, interpreter, namespace, events, and interrupt model together form this
implementation of ACPI, creating the ACPI subsystem within the host OS. In this sense, ACPI is the interface between
the system hardware/ﬁrmware and the OS and OS applications for conﬁguration and power management. This gives
various OS a standardized way to support power management and conﬁguration via the ACPI namespace.
The ACPI namespace is the enumerable, hierarchical representation of all ACPI devices on the system and is used to
both ﬁnd and load drivers for ACPI devices on the system. The namespace can be dynamic by evaluating objects and
sending interrupts in real time, all without the need for the OS to call native system ﬁrmware code. This enables device
manufacturers to code their own instructions and events into devices. It also reduces incompatibility and instability by
implementing a standardized power management interface.
CONTENTS lxviiCHAPTER
ONE
The Advanced Conﬁguration and Power Interface (ACPI) speciﬁcation was developed to establish industry common
interfaces enabling robust operating system (OS)-directed motherboard device conﬁguration and power management
of both devices and entire systems. ACPI is the key element in Operating System-directed conﬁguration and Power
Management (OSPM).
ACPI evolved the existing pre-ACPI collection of power management BIOS code, Advanced Power Management
(APM) application programming interfaces (APIs, PNPBIOS APIs, Multiprocessor Speciﬁcation (MPS) tables and
so on into a well-deﬁned power management and conﬁguration interface speciﬁcation. ACPI provides the means
for an orderly transition from existing (legacy) hardware to ACPI hardware, and it allows for both ACPI and legacy
mechanisms to exist in a single machine and to be used as needed.
Further, system architectures being built at the time of the original ACPI speciﬁcation’s inception, stretched the lim-
its of historical “Plug and Play” interfaces. ACPI evolved existing motherboard conﬁguration interfaces to support
advanced architectures in a more robust, and potentially more efﬁcient manner.
The interfaces and OSPM concepts deﬁned within this speciﬁcation are suitable to all classes of computers including
(but not limited to) desktop, mobile, workstation, and server machines. From a power management perspective,
OSPM/ACPI promotes the concept that systems should conserve energy by transitioning unused devices into lower
power states including placing the entire system in a low-power state (sleeping state) when possible.
This document describes ACPI hardware interfaces, ACPI software interfaces and ACPI data structures that, when
implemented, enable support for robust OS-directed conﬁguration and power management (OSPM).
1.1 Principal Goals
ACPI is the key element in implementing OSPM. ACPI-deﬁned interfaces are intended for wide adoption to encourage
hardware and software vendors to build ACPI-compatible (and, thus, OSPM-compatible) implementations.
The principal goals of ACPI and OSPM are to:
• Enable all computer systems to implement motherboard conﬁguration and power management functions, using
appropriate cost/function tradeoffs:
–Computer systems include (but are not limited to) desktop, mobile, workstation, and server machines.
–Machine implementers have the freedom to implement a wide range of solutions, from the very simple to
the very aggressive, while still maintaining full OS support.
–Wide implementation of power management will make it practical and compelling for applications to
support and exploit it. It will make new uses of PCs practical and existing uses of PCs more economical.
• Enhance power management functionality and robustness:
1Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
–Power management policies too complicated to implement in platform ﬁrmware can be implemented and
supported in the OS, allowing inexpensive power managed hardware to support very elaborate power
management policies.

–Gathering power management information from users, applications, and the hardware together into the OS
will enable better power management decisions and execution.
–Uniﬁcation of power management algorithms in the OS will reduce conﬂicts between the ﬁrmware and OS
and will enhance reliability.
• Facilitate and accelerate industry-wide implementation of power management:
–OSPM and ACPI reduces the amount of redundant investment in power management throughout the in-
dustry, as this investment and function will be gathered into the OS. This will allow industry participants
to focus their efforts and investments on innovation rather than simple parity.
–The OS can evolve independently of the hardware, allowing all ACPI-compatible machines to gain the
beneﬁts of OS improvements and innovations.
• Create a robust interface for conﬁguring motherboard devices:
–Enable new advanced designs not possible with existing interfaces.
1.1.1 Principle of Inclusive Terminology
This means efforts are made to ensure that all wording is perceived or likely to be perceived as welcoming by everyone
regardless of personal characteristics. In some cases, the Forum acknowledges that wording derived from earlier
work, for example references to legacy speciﬁcations not controlled by the Forum, may not follow this principle. In
order to preserve compatibility for code that reads on legacy speciﬁcations, particularly where that speciﬁcation is no
longer under maintenance or development, language in this speciﬁcation may appear out of sync with this principle.
1.2 Power Management Rationale
It is necessary to move power management into the OS and to use an abstract interface (ACPI) between the OS and
the hardware to achieve the principal goals set forth above. Because ACPI is abstract, the OS can evolve separately
from the hardware and, likewise, the hardware from the OS.
ACPI is by nature more portable across operating systems and processors. ACPI control methods allow for very
ﬂexible implementations of particular features.
Issues with older power management approaches include the following:
• Minimal support for power management inhibits application vendors from supporting or exploiting it.
–Moving power management functionality into the OS makes it available on every machine on which the
OS is installed. The level of functionality (power savings, and so on) varies from machine to machine, but
users and applications will see the same power interfaces and semantics on all OSPM machines.
–This will enable application vendors to invest in adding power management functionality to their products.
• Legacy power management algorithms were restricted by the information available to the platform ﬁrmware that
implemented them. This limited the functionality that could be implemented.
1.2. Power Management Rationale 2Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
–Centralizing power management information and directives from the user, applications, and hardware in
the OS allows the implementation of more powerful functionality. For example, an OS can have a policy
of dividing I/O operations into normal and lazy. Lazy I/O operations (such as a word processor saving
ﬁles in the background) would be gathered up into clumps and done only when the required I/O device is
powered up for some other reason. A non-lazy I/O request made when the required device was powered
down would cause the device to be powered up immediately, the non-lazy I/O request to be carried out,
and any pending lazy I/O operations to be done. Such a policy requires knowing when I/O devices are
powered up, knowing which application I/O requests are lazy, and being able to assure that such lazy I/O
operations do not starve.
• Appliance functions, such as answering machines, require globally coherent power decisions. For example, a
telephone-answering application could call the OS and assert, “I am waiting for incoming phone calls; any sleep
state the system enters must allow me to wake and answer the telephone in 1 second.” Then, when the user
presses the “off” button, the system would pick the deepest sleep state consistent with the needs of the phone
answering service.
–Platform ﬁrmware has become very complex to deal with power management. It is difﬁcult to make work
with an OS and is limited to static conﬁgurations of the hardware.
–There is much less state information for the platform ﬁrmware to retain and manage (because the OS
manages it).
–Power management algorithms are uniﬁed in the OS, yielding much better integration between the OS and
the hardware.
–Because additional ACPI tables (Deﬁnition Blocks) can be loaded, for example, when a mobile system
docks, the OS can deal with dynamic machine conﬁgurations.
–Because the platform ﬁrmware has fewer functions and they are simpler, it is much easier (and therefore
cheaper) to implement and support.
1.3 Legacy Support
ACPI provides support for an orderly transition from legacy hardware to ACPI hardware, and allows for both mecha-
nisms to exist in a single machine and be used as needed.
Table 1.1: Hardware Type vs. OS Type Interaction
Hardware/OS Legacy OS ACPI OS with OSPM
Legacy hardware A legacy OS on legacy
hardware does what it al-
ways did.If the OS lacks legacy support, legacy support is com-
pletely contained within the hardware functions.
Legacy and ACPI hard-
ware support in machineIt works just like a legacy
OS on legacy hardware.During boot, the OS tells the hardware to switch from
legacy to OSPM/ACPI mode and from then on, the sys-
tem has full OSPM/ACPI support.
ACPI-only hardware There is no power man-
agement.There is full OSPM/ACPI support.
1.3. Legacy Support 3Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
1.4 OEM Implementation Strategy
Any OEM is, as always, free to build hardware as they see ﬁt. Given the existence of the ACPI speciﬁcation, two
general implementation strategies are possible:
• An original equipment manufacturer (OEM) can adopt the OS vendor-provided ACPI OSPM software and
implement the hardware part of the ACPI speciﬁcation (for a given platform) in one of many possible ways.
• An OEM can develop a driver and hardware that are not ACPI-compatible. This strategy opens up even more
hardware implementation possibilities. However, OEMs who implement hardware that is OSPM-compatible but
not ACPI-compatible will bear the cost of developing, testing, and distributing drivers for their implementation.
1.5 Power and Sleep Buttons
OSPM provides a new appliance interface to consumers. In particular, it provides for a sleep button that is a “soft”
button that does not turn the machine physically off but signals the OS to put the machine in a soft off or sleeping state.
ACPI deﬁnes two types of these “soft” buttons: one for putting the machine to sleep and one for putting the machine
in soft off.
This gives the OEM two different ways to implement machines: A one-button model or a two-button model. The one-
button model has a single button that can be used as a power button or a sleep button as determined by user settings.
The two-button model has an easily accessible sleep button and a separate power button. In either model, an override
feature that forces the machine to the soft-off state without OSPM interaction is also needed to deal with various rare,
but problematic, situations.
1.6 ACPI Speciﬁcation and the Structure of ACPI
This speciﬁcation deﬁnes ACPI hardware interfaces, ACPI software interfaces and ACPI data structures. This speciﬁ-
cation also deﬁnes the semantics of these interfaces.
Fig. 1.1 below lays out the software and hardware components for OSPM/ACPI, and how they relate to each other.
This speciﬁcation describes the interfaces between components, the contents of the ACPI System Description Tables,
and the related semantics of the other ACPI components. Notice that the ACPI System Description Tables, which
describe a particular platform’s hardware, are at heart of the ACPI implementation and the role of the ACPI System
Firmware is primarily to supply the ACPI Tables (rather than a native instruction API).
ACPI is not a software speciﬁcation; it is not a hardware speciﬁcation, although it addresses both software and hard-
ware and how they must behave. ACPI is, instead, an interface speciﬁcation comprised of both software and hardware
elements.
There are three run-time components to ACPI:
ACPI System Description Tables

elements.
Describes the interfaces to the hardware. Some descriptions limit what can be built (for example, some controls are
embedded in ﬁxed blocks of registers and the table speciﬁes the address of the register block). Most descriptions
allow the hardware to be built in arbitrary ways and can describe arbitrary operation sequences needed to make the
hardware function. ACPI Tables containing “Deﬁnition Blocks” can make use of a pseudo-code type of language,
the interpretation of which is performed by the OS. That is, OSPM contains and uses an interpreter that executes
procedures encoded in the pseudo-code language and stored in the ACPI tables containing “Deﬁnition Blocks.” The
pseudo-code language, known as ACPI Machine Language (AML), is a compact, tokenized, abstract type of machine
language.
ACPI Registers
1.4. OEM Implementation Strategy 4Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 1.1: OSPM/ACPI Global System
1.6. ACPI Speciﬁcation and the Structure of ACPI 5Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The constrained part of the hardware interface, described (at least in location) by the ACPI System Description Tables.
ACPI Platform Firmware
Refers to the portion of the ﬁrmware that is compatible with the ACPI speciﬁcations. Typically, this is the code that
boots the machine (as legacy BIOSs have done) and implements interfaces for sleep, wake, and some restart operations.
It is called rarely, compared to a legacy BIOS. The ACPI Description Tables are also provided by the ACPI Platform
Firmware.
1.7 OS and Platform Compliance
The ACPI speciﬁcation contains only interface speciﬁcations. ACPI does not contain any platform compliance re-
quirements. The following sections provide guidelines for class speciﬁc platform implementations that reference
ACPI-deﬁned interfaces and guidelines for enhancements that operating systems may require to completely support
OSPM/ACPI. The minimum feature implementation requirements of an ACPI-compatible OS are also provided.
1.7.1 Platform Implementations of ACPI-deﬁned Interfaces
System platforms implement ACPI-deﬁned hardware interfaces via the platform hardware and ACPI-deﬁned software
interfaces and system description tables via the ACPI system ﬁrmware. Speciﬁc ACPI-deﬁned interfaces and OSPM
concepts while appropriate for one class of machine (for example, a mobile system), may not be appropriate for
another class of machine (for example, a multi-domain enterprise server). It is beyond the capability and scope of this
speciﬁcation to specify all platform classes and the appropriate ACPI-deﬁned interfaces that should be required for the
platform class.
Platform design guide authors are encouraged to require the appropriate ACPI-deﬁned interfaces and hardware require-
ments suitable to the particular system platform class addressed in a particular design guide. Platform design guides
should not deﬁne alternative interfaces that provide similar functionality to those deﬁned in the ACPI speciﬁcation.
1.7.1.1 Recommended Features and Interface Descriptions for Design Guides
Common description text and category names should be used in design guides to describe all features, concepts, and
interfaces deﬁned by the ACPI speciﬁcation as requirements for a platform class. Listed below is the recommended
set of high-level text and category names to be used to describe the features, concepts, and interfaces deﬁned by ACPI.
Note: The deﬁnitions and relational requirements of the interfaces speciﬁed below are generally spread throughout
the ACPI speciﬁcation:
•System Address Map Interfaces
•ACPI System Description Tables
•Root System Description Pointer (RSDP)
•System Description Table Header
•Fixed ACPI Description Table (FADT)
•Firmware ACPI Control Structure (FACS)
•Differentiated System Description Table (DSDT)
•Secondary System Description Table (SSDT)
1.7. OS and Platform Compliance 6Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
•Multiple APIC Description Table (MADT)
•Smart Battery Table (SBST)
•Embedded Controller Boot Resources Table (ECDT)
•System Resource Afﬁnity Table (SRAT)
•System Locality information Table
•Corrected Platform Error Polling Table (CPEP)
•Maximum System Characteristics Table (MSCT)
•ACPI RAS Feature Table (RASF)
•ACPI RAS2 Feature Table (RAS2)
•Memory Power State Table (MPST)
•Platform Memory Topology Table
•Boot Graphics Resource Table (BGRT)
•Firmware Performance Data Table (FPDT)
•Generic Timer Description Table (GTDT)
•Power management timer control/status
• Power or sleep button with S5 override (also possible in generic space)
• Real time clock wakeup alarm control/status
• SCI /SMI routing control/status for Power Management and General-purpose events
• System power state controls (sleeping/wake control)
• Processor power state control (c states)
• Processor throttling control/status
• Processor performance state control/status
• General-purpose event control/status
• Global Lock control/status
• System Reset control
• Embedded Controller control/status
• SMBus Host Controller (HC) control/status
• Smart Battery Subsystem
• ACPI-deﬁned Generic Register Interfaces and object deﬁnitions in the ACPI Namespace.
• General-purpose event processing
• Motherboard device identiﬁcation, conﬁguration, and insertion/removal
• Thermal zones
• Power resource control
• Device power state control
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• System power state control
• System indicators
• Devices and device controls:
–Processor
–Control Method Battery
–Smart Battery Subsystem
–Mobile Lid
–Power or sleep button with S5 override (also possible in ﬁxed space)
–Embedded controller
–Fan
–Generic Bus Bridge
–ATA Controller
–Floppy Controller
–GPE Block
–Module
–Memory
• Global Lock related interfaces
• ACPI Event programming model
• ACPI-deﬁned Platform Firmware Responsibilities
• ACPI-deﬁned State Deﬁnitions:
–Global system power states (G-states, S0, S5)
–System sleeping states (S-states S1-S4)
–Device power states (D-states)
–Processor power states (C-states)
–Device and processor performance states (P-states)
1.7.1.2 Terminology Examples for Design Guides
The following example shows how a client platform design guide could use the recommended terminology to deﬁne
ACPI requirements, with a goal of requiring robust conﬁguration and power management for the system class.
Note: This example is provided as a guideline for how ACPI terminology can be used. It should not be interpreted as
a statement of ACPI requirements.
Platforms compliant with this platform design guide must implement the following ACPI deﬁned system features,
concepts, and interfaces, along with their associated event models:
• System Address Map Interfaces
• ACPI System Description Tables provided in the system ﬁrmware
• ACPI-deﬁned Fixed Registers Interfaces:
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• Power management timer control/status
• Power or sleep button with S5 override (may also be implemented in generic register space)
• SCI /SMI routing control/status for Power Management and General-purpose events (control required only if
system supports legacy mode)
• Processor power state control (for C1)
• Global Lock control/status (if Global Lock interfaces are required by the system)
• ACPI-deﬁned Generic Register Interfaces and object deﬁnitions in the ACPI Namespace:
–General-purpose event processing
–Motherboard device identiﬁcation, conﬁguration, and insertion/removal
–System power state control ( Section 7.3)
–Devices and device controls:
*Processor
*Control Method Battery (or Smart Battery Subsystem on a mobile system)
*Smart Battery Subsystem (or Control Method Battery on a mobile system)
*Power or sleep button with S5 override (may also be implemented in ﬁxed register space)
–Global Lock related interfaces when a logical register in the hardware is shared between OS and ﬁrmware
environments
–System sleeping states (At least one system sleeping state, S1-S4, must be implemented)
–Device power states (D-states must be implemented in accordance with device class speciﬁcations)
–Processor power states (All processors must support the C1 Power State)
The following example shows how a design guide could use the recommended terminology to deﬁne ACPI related
requirements for systems that execute multiple OS instances, with a goal of requiring robust conﬁguration and contin-
uous availability for the system class.

Platforms compliant with this platform design guide must implement the following ACPI deﬁned system features and
interfaces, along with their associated event models:
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• (control required only if system supports legacy mode)
–Motherboard device identiﬁcation, conﬁguration, and insertion/removal (Section 6)
–System power state control (Section 7.3)
–System indicators
• Global Lock related interfaces when a logical register in the hardware is shared between OS and ﬁrmware
• ACPI Event programming model (Section 5.6)
• ACPI-deﬁned Platform Firmware Responsibilities (Section 15)
Processor power states (All processors must support the C1 Power State)
1.7.2 OSPM Implementations
OS enhancements are needed to support ACPI-deﬁned features, concepts, and interfaces, along with their associated
event models appropriate to the system platform class upon which the OS executes. This is the implementation of
OSPM. The following outlines the OS enhancements and elements necessary to support all ACPI-deﬁned interfaces.
To support ACPI through the implementation of OSPM, the OS needs to be modiﬁed to:
• Use System Address Map Interfaces .
• Find and consume the ACPI System Description Tables.
• Interpret ACPI machine language (AML).
• Enumerate and conﬁgure motherboard devices described in the ACPI Namespace.
• Interface with the power management timer.
• Interface with the real-time clock wake alarm.
• Enter ACPI mode (on legacy hardware systems).
• Implement device power management policy.
• Implement power resource management.
• Implement processor power states in the scheduler idle handlers.
• Control processor and device performance states.
• Implement the ACPI thermal model.
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• Support the ACPI Event programming model including handling SCI interrupts, managing ﬁxed events, general-
purpose events, embedded controller interrupts, and dynamic device support.
• Support acquisition and release of the Global Lock.
• Use the reset register to reset the system.
• Provide APIs to inﬂuence power management policy.
• Implement driver support for ACPI-deﬁned devices.
• Implement APIs supporting the system indicators.
• Support all system states S1-S5.
1.7.3 OS Requirements
The following list describes the minimum requirements for an OSPM/ACPI-compatible OS:
• Use Section 15 to get the system address map on Intel Architecture (IA) platforms:
• INT 15H, E820H - Query System Address Map interface (see Section 15)
• EFI GetMemoryMap() Boot Services Function (see Section 15)
• Find and consume the ACPI System Description Tables (see Section 5).
• Implementation of an AML interpreter supporting all deﬁned AML grammar elements (see Section 20).
• Support for the ACPI Event programming model including handling SCI interrupts, managing ﬁxed events,
general-purpose events, embedded controller interrupts, and dynamic device support.
• Implement support for the following ACPI devices deﬁned within this speciﬁcation:
• Embedded Controller Device (see Section 12)
• GPE Block Device (see Section 9.9)
• Implementation of the ACPI thermal model (see Section 3.10).
• OS-directed power management support (device drivers are responsible for maintaining device context as de-
scribed by the Device Power Management Class Speciﬁcations described in Appendix A: Device Class Speciﬁ-
cations ).
1.8 Target Audience
This speciﬁcation is intended for the following users:
• OEMs building hardware containing ACPI-compatible interfaces
• Operating system and device driver developers
• All platform system ﬁrmware developers
• CPU and chip set vendors
• Peripheral vendors
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1.9 Document Organization
The ACPI speciﬁcation document is organized into the following four parts:
• The ﬁrst part of the speciﬁcation (chapters 1 through 3) introduces ACPI and provides an executive overview.
• The second part (chapters 4 and 5) deﬁnes the ACPI hardware and software programming models.
• The third part (chapters 6 through 17) speciﬁes the ACPI implementation details; this part of the speciﬁcation is
primarily for developers.
• The fourth part (chapters 18 and 19) is technical reference material: chapter 18 is the ACPI Source Language
(ASL) reference, which is referenced by many other sections in this speciﬁcation.
• Appendices contain device class speciﬁcations, describing power management characteristics of speciﬁc classes
of devices, and device class-speciﬁc ACPI interfaces.
1.9.1 ACPI Introduction and Overview
The ﬁrst three sections of the speciﬁcation provide an executive overview of ACPI.
Chapter 1: Introduction Discusses the purpose and goals of the speciﬁcation, presents an overview of the ACPI-
compatible system architecture, speciﬁes the minimum requirements for an ACPI-compatible system, and pro-
vides references to related speciﬁcations.
Chapter 2: Deﬁnition of Terms Deﬁnes the key terminology used in this speciﬁcation. In particular, the global sys-
tem states (Mechanical Off, Soft Off, Sleeping, Working, and Non-V olatile Sleep) are deﬁned in this Chapter,
along with the device power state deﬁnitions: Off (D3), D3hot, D2, D1, and Fully-On (D0). Device and proces-
sor performance states (P0, P1, . . . Pn) are also discussed.
Chapter 3: ACPI Overview Gives an overview of the ACPI speciﬁcation in terms of the functional areas covered by
the speciﬁcation: system power management, device power management, processor power management, Plug
and Play, handling of system events, battery management, and thermal management.
1.9.2 Programming Models
Chapters 4 and 5 deﬁne the ACPI hardware and software programming models. This part of the speciﬁcation is
primarily for system designers, developers, and project managers.
All of the implementation-oriented, reference, and platform example Chapters of the speciﬁcation that follow (all the
rest of the Chapters of the speciﬁcation) are based on the models deﬁned in Chapters 4 and 5. These Chapters are the
heart of the ACPI speciﬁcation. There are extensive cross-references between the two Chapters.
Chapter 4: ACPI Hardware Speciﬁcation Deﬁnes a set of hardware interfaces that meet the goals of this speciﬁca-
tion.
Chapter 5: ACPI Software Programming Model Deﬁnes a set of software interfaces that meet the goals of this
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1.9.3 Implementation Details
The third part of the speciﬁcation deﬁnes the implementation details necessary to actually build components that work
on an ACPI-compatible platform. This part of the speciﬁcation is primarily for developers.
Chapter 6: Conﬁguration Deﬁnes the reserved Plug and Play objects used to conﬁgure and assign resources to
devices, and share resources and the reserved objects used to track device insertion and removal. Also deﬁnes
the format of ACPI-compatible resource descriptors.
Chapter 7: Power and Performance Management Deﬁnes the reserved device power-management objects and the
reserved-system power-management objects.
Chapter 8: Processor Conﬁguration and Control Deﬁnes how the OS manages the processors’ power consumption
and other controls while the system is in the working state.
Chapter 9: ACPI-Speciﬁc Device Objects Lists the integrated devices that need support for some device-speciﬁc
ACPI controls, along with the device-speciﬁc ACPI controls that can be provided. Most device objects are
controlled through generic objects and control methods and have generic device IDs; this Chapter discusses the
exceptions.
Chapter 10: Power Source Devices Deﬁnes the reserved battery device and AC adapter objects.
Chapter 11: Thermal Management Deﬁnes the reserved thermal management objects.

Chapter 12: ACPI Embedded Controller Interface Speciﬁcation Deﬁnes the interfaces between an ACPI-
compatible OS and an embedded controller.
Chapter 13: ACPI System Management Bus Interface Speciﬁcation Deﬁnes the interfaces between an ACPI-
compatible OS and a System Management Bus (SMBus) host controller.
Chapter 14: Platform Communications Channel Explains the generic mechanism for OSPM to communicate with
an entity in the platform deﬁnes a new address space type.
Chapter 15: System Address Map Interfaces Explains the special INT 15 call for use in ISA/EISA/PCI bus-based
systems. This call supplies the OS with a clean memory map indicating address ranges that are reserved and
ranges that are available on the motherboard. UEFI-based memory address map reporting interfaces are also
described.
Chapter 16: Waking and Sleeping Deﬁnes in detail the transitions between system working and sleeping states and
their relationship to wake events. Refers to the reserved objects deﬁned in Chapters 6, 7, and 8.
Chapter 17: Non-Uniform Memory Access (NUMA) Architecture Platforms Discusses in detail how ACPI de-
ﬁne interfaces can be used to describe a NUMA architecture platform. Refers to the reserved objects deﬁned in
Chapters 5, 6, 8, and 9.
Chapter 18: ACPI Platform Error Interfaces Deﬁnes interfaces that enable OSPM to processes different types of
hardware error events that are detected by platform-based error detection hardware.
1.9.4 Technical Reference
The fourth part of the speciﬁcation contains reference material for developers.
Chapter 19: ACPI Source Language Reference Deﬁnes the syntax of all the ASL statements that can be used to
write ACPI control methods, along with example syntax usage.
Chapter 20: ACPI Machine Language Speciﬁcation Deﬁnes the grammar of the language of the ACPI virtual ma-
chine language. An ASL translator (compiler) outputs AML.
Chapter 21: ACPI Data Tables and Table Language Deﬁnition Describes a simple language (the Table Deﬁnition
Language or TDL) that can be used to generate any ACPI data table.
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Appendix A: Device class speciﬁcations Describes device-speciﬁc power management behavior on a per device-
class basis.
Appendix B: Video Extensions Contains video device class-speciﬁc ACPI interfaces
1.9.5 Revsion Numbers
Updates to the ACPI speciﬁcation are considered either new revisions or errata as described below:
New revisions are designated by a Major.Minor version number (e.g. 6.3). In cases where the changes are
exceptionally minor, we may have a Major.Minor.Minor naming convention (e.g. 6.3.1).
• An errata is produced when proposed changes or ﬁxes of the speciﬁcation do not include any signiﬁcant new
version number, such as 6.2A.
1.10 Related Documents
Power management and Plug and Play speciﬁcations for legacy hardware platforms are available from Links to ACPI-
Related Documents:
• Advanced Power Management (APM) BIOS Speciﬁcation
• Plug and Play BIOS Speciﬁcation
Intel Architecture speciﬁcations are available at http://developer.intel.com and https://software.intel.com/en-us/
articles/intel-sdm.
Other UEFI Speciﬁcations are available at https://ueﬁ.org/speciﬁcations:
• Uniﬁed Extensible Firmware Interface (UEFI) Speciﬁcation
• Platform Integration (PI) Speciﬁcation
Documentation and speciﬁcations for the Smart Battery System components and the SMBus are availabe at the fol-
lowing links:
• Smart Battery System speciﬁcations
• SMBus speciﬁcations
USB Power Delivery Speciﬁcation (Revision 3.1, Version 1.3): see “Links to ACPI-Related Documents” (http://ueﬁ.
org/acpi) under the heading “Universal Serial Bus Power Management”
1.10. Related Documents 14CHAPTER
TWO
DEFINITION OF TERMS
This speciﬁcation uses a particular set of terminology, deﬁned in this section. This section has three parts:
General ACPI terms are deﬁned and presented alphabetically.
The ACPI global system states (working, sleeping, soft off, and mechanical off) are deﬁned. Global system states
apply to the entire system, and are visible to the user.
The ACPI device power states are deﬁned. Device power states are states of particular devices; as such, they are
generally not visible to the user. For example, some devices may be in the off state even though the system as a whole
is in the working state. Device states apply to any device on any bus.
2.1 General ACPI Terminology
Advanced Conﬁguration and Power Interface (ACPI) As deﬁned in this document, ACPI is a method for describ-
ing hardware interfaces in terms abstract enough to allow ﬂexible and innovative hardware implementations and
concrete enough to allow shrink-wrap OS code to use such hardware interfaces.
ACPI Hardware Computer hardware with the features necessary to support OSPM and with the interfaces to those
features described using the Description Tables as speciﬁed by this document.
ACPI Namespace A hierarchical tree structure in OS-controlled memory that contains named objects. These objects
may be data objects, control method objects, bus/device package objects, and so on. The OS dynamically
changes the contents of the namespace at run-time by loading deﬁnition blocks from the ACPI Tables that reside
in the ACPI system ﬁrmware. All the information in the ACPI Namespace comes from the Differentiated System
Description Table (DSDT), which contains the Differentiated Deﬁnition Block, and one or more other deﬁnition
blocks.
ACPI Machine Language (AML) Pseudo-code for a virtual machine supported by an ACPI-compatible OS and in
which ACPI control methods and objects are written. The AML encoding deﬁnition is provided in section 19,
“ACPI Machine Language (AML) Speciﬁcation.”
Add-in Card A generic term used to refer to any device which can be inserted or removed from a platform through a
connection bus, such as PCI. Add-in cards are typically inserted within a platform’s physical enclosure, rather
than residing physically external to a platform. An add-in card will have its own devices and associated ﬁrmware,
and may have its own Expansion ROM Firmware.
Advanced Programmable Interrupt Controller (APIC) An interrupt controller architecture commonly found on
Intel Architecture-based 32-bit PC systems. The APIC architecture supports multiprocessor interrupt manage-
ment (with symmetric interrupt distribution across all processors), multiple I/O subsystem support, 8259A com-
patibility, and inter-processor interrupt support. The architecture consists of local APICs commonly attached
directly to processors and I/O APICs commonly in chip sets.
ACPI Source Language (ASL) The programming language equivalent for AML. ASL is compiled into AML im-
ages. The ASL statements are deﬁned in section 18, “ACPI Source Language (ASL) Reference.”
15Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Address Range Scrub (ARS) Process by which regions of memory can be scrubbed to look for memory locations
that contain correctable or uncorrectable errors.
BIOS BIOS (Basic Input/Output System) is ﬁrmware that provides basic boot capabilities for a platform; it is used
here to refer speciﬁcally to traditional x86 BIOS, and not as a general term for all ﬁrmware, or a replacement
term for UEFI Core System BIOS. The ambiguity of this the term is what we are trying to remove. See also:
Legacy BIOS ,System BIOS .
Boot Firmware Generic term to describe any ﬁrmware on a platform used during the boot process. Use a more
speciﬁc term, if possible.
Component Synonym for device. Please use the term “device” if possible.
Control Method A control method is a deﬁnition of how the OS can perform a simple hardware task. For example,
the OS invokes control methods to read the temperature of a thermal zone. Control methods are written in an
encoded language called AML that can be interpreted and executed by the ACPI-compatible OS. An ACPI-
compatible system must provide a minimal set of control methods in the ACPI tables. The OS provides a
set of well-deﬁned control methods that ACPI table developers can reference in their control methods. OEMs
can support different revisions of chip sets with one version of platform ﬁrmware by either including control
methods in the platform ﬁrmware that test conﬁgurations and respond as needed or including a different set of
control methods for each chip set revision.
Central Processing Unit (CPU) or Processor The part of a platform that executes the instructions that do the work.
An ACPI-compatible OS can balance processor performance against power consumption and thermal states by
manipulating the processor performance controls. The ACPI speciﬁcation deﬁnes a working state, labeled G0

(S0), in which the processor executes instructions. Processor sleeping states, labeled C1 through C3, are also
deﬁned. In the sleeping states, the processor executes no instructions, thus reducing power consumption and,
potentially, operating temperatures. The ACPI speciﬁcation also deﬁnes processor performance states, where
the processor (while in C0) executes instructions, but with lower performance and (potentially) lower power
consumption and operating temperature. For more information, see Section 8.
A deﬁnition block contains information about hardware implementation and conﬁguration details in the form of
data and control methods, encoded in AML. An OEM can provide one or more deﬁnition blocks in the ACPI
Tables. One deﬁnition block must be provided: the Differentiated Deﬁnition Block, which describes the base
system. Upon loading the Differentiated Deﬁnition Block, the OS inserts the contents of the Differentiated
Deﬁnition Block into the ACPI Namespace. Other deﬁnition blocks, which the OS can dynamically insert and
remove from the active ACPI Namespace, can contain references to the Differentiated Deﬁnition Block. For
more information, see Deﬁnition Blocks .
Device A generic term used to refer to any computing, input/output or storage element, or any collection of computing,
input/output or storage elements, on a platform. An example of a device is a CPU, APU, embedded controller
(EC), BMC, Trusted Platform Module (TPM), graphics processing unit (GPU), network interface controller
(NIC), hard disk drive (HDD), solid state drive (SSD), Read Only Memory (ROM), ﬂash ROM, or any of the
large number of other possible devices. If at all possible, use a more speciﬁc term.
Device Context The variable data held by the device; it is usually volatile. The device might forget this information
when entering or leaving certain states (for more information, see Device Power State Deﬁnitions ), in which
case the OS software is responsible for saving and restoring the information. Device Context refers to small
amounts of information held in device peripherals. See System Context .
Device Firmware Firmware that is only used by a speciﬁc device and cannot be used with any other device. This
ﬁrmware is typically provided by the device manufacturer.
Differentiated System Description Table (DSDT) An OEM must supply a DSDT to an ACPI-compatible OS. The
DSDT contains the Differentiated Deﬁnition Block, which supplies the implementation and conﬁguration in-
formation about the base system. The OS always inserts the DSDT information into the ACPI Namespace at
system boot time and never removes it.
Device Physical Address (DPA) A Device relative memory address.
2.1. General ACPI Terminology 16Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Embedded Controller The general class of micro-controllers used to support OEM-speciﬁc supports embedded con-
trollers in any platform design, as long as the micro-controller conforms to one of the models described in this
section. The embedded controller performs complex low-level functions through a simple interface to the host
microprocessor(s).
ACPI deﬁnes a standard hardware and software communications interface between an OS bus enumerator and
an embedded controller. This allows any OS to provide a standard bus enumerator that can directly communicate
with an embedded controller in the system, thus allowing other drivers within the system to communicate with
and use the resources of system embedded controllers. This in turn enables the OEM to provide platform features
that the OS and applications can use.
Embedded Controller Interface A standard hardware and software communications interface between an OS driver
and an embedded controller. This allows any OS to provide a standard driver that can directly communicate
and use the resources of system embedded controllers (for example, Smart Battery and AML code). This in turn
enables the OEM to provide platform features that the OS and applications can use.
Expansion ROM Firmware Peripheral Component Interconnect (PCI) term for ﬁrmware executed on a host proces-
sor which is used by an add-in device during the boot process. This includes Option ROM Firmware and UEFI
drivers. Expansion ROM Firmware may be embedded as part of the Host Processor Boot Firmware, or may be
separate (e.g., from an add-in card). See also: Option ROM Firmware .
Firmware Generic term to describe any BIOS or ﬁrmware on a platform; it refers to the general class of things, not a
speciﬁc type. Use a more speciﬁc term, if possible.
Firmware ACPI Control Structure (FACS) A structure in read/write memory that the platform runtime ﬁrmware
uses for handshaking between the ﬁrmware and the OS. The FACS is passed to an ACPI-compatible OS via the
Fixed ACPI Description Table (FADT). The FACS contains the system’s hardware signature at last boot, the
ﬁrmware waking vector, and the Global Lock.
Firmware Storage Device A memory device used to store ﬁrmware. This could include Read Only Memory (ROM),
ﬂash memory, eMMC, UFS drives, etc.
Fixed ACPI Description Table (FADT) A table that contains the ACPI Hardware Register Block implementation
and conﬁguration details that the OS needs to directly manage the ACPI Hardware Register Blocks, as well
as the physical address of the DSDT, which contains other platform implementation and conﬁguration details.
An OEM must provide an FADT to an ACPI-compatible OS in the RSDT/XSDT. The OS always inserts the
namespace information deﬁned in the Differentiated Deﬁnition Block in the DSDT into the ACPI Namespace
at system boot time, and the OS never removes it.
Fixed Features A set of features offered by an ACPI interface. The ACPI speciﬁcation places restrictions on where
and how the hardware programming model is generated. All ﬁxed features, if used, are implemented as described
in this speciﬁcation so that OSPM can directly access the ﬁxed feature registers.
Fixed Feature Events A set of events that occur at the ACPI interface when a paired set of status and event bits in
the ﬁxed feature registers are set at the same time. When a ﬁxed feature event occurs, a system control interrupt
(SCI is raised. For ACPI ﬁxed feature events, OSPM (or an ACPI-aware driver) acts as the event handler.
Fixed Feature Registers A set of hardware registers in ﬁxed feature register space at speciﬁc address locations in
system I/O address space. ACPI deﬁnes register blocks for ﬁxed features (each register block gets a separate
pointer from the FADT). For more information, see ACPI Hardware Features .
General-Purpose Event Registers The general-purpose event registers contain the event programming model for
generic features. All general-purpose events generate SCIs.
Generic Feature A generic feature of a platform is value-added hardware implemented through control methods and
general-purpose events.
Generic Interrupt Controller (GIC) An interrupt controller architecture for ARM processor-based systems.
2.1. General ACPI Terminology 17Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Global System Status Global system states apply to the entire system, and are visible to the user. The various global
system states are labeled G0 through G3 in the ACPI speciﬁcation. For more information, see Global System
State Deﬁnitions .
Host Processor A host processor is the primary processing unit in a platform, traditionally called a Central Processing
Unit (CPU), now also sometimes referred to as an Application Processing Unit (APU), or a System on Chip
(SoC). This is the processing unit on which the primary operating system (and/or hypervisor), as well as user
applications run. This is the processor that is responsible for loading and executing the Host Processor Boot
Firmware. This term and “Boot Processor” should be considered synonyms for this particular text clean-up
effort (i.e., making them consistent should probably be part of a different ECR, if needed).
Host Processor Boot Firmware Generic term used to describe ﬁrmware loaded and executed by the Host Processor
which provides basic boot capabilities for a platform. This class of ﬁrmware is a reference to Legacy BIOS
and UEFI, which were sometimes referred to as System BIOS. Where the distinction between Legacy BIOS
and UEFI is not important, the term Host Processor Boot Firmware will be used. Where the distinction is
important, it will be referenced appropriately. Expansion ROM ﬁrmware may also be considered as part of the
Host Processor Boot Firmware. Expansion ROM Firmware may be embedded as part of the Host Processor
Boot Firmware, or may be separate from the Host Processor Boot Firmware (e.g., loaded from an add-in card).
Host Processor Runtime Firmware Host processor runtime ﬁrmware is any runtime ﬁrmware which executes on
the host processor.
Ignored Bits Some unused bits in ACPI hardware registers are designated as “ignored” in the ACPI speciﬁcation.

Ignored bits are undeﬁned and can return zero or one (in contrast to reserved bits, which always return zero).
Software ignores ignored bits in ACPI hardware registers on reads and preserves ignored bits on writes.
Intel Architecture-Personal Computer (IA-PC) A general descriptive term for computers built with processors
conforming to the architecture deﬁned by the Intel processor family based on the Intel Architecture instruc-
tion set and having an industry-standard PC architecture.
I/O APIC An Input/Output Advanced Programmable Interrupt Controller routes interrupts from devices to the pro-
cessor’s local APIC.
I/O SAPIC An Input/Output Streamlined Advanced Programmable Interrupt Controller routes interrupts from de-
vices to the processor’s local APIC.
Label Storage Area A persistent storage area reserved for Label storage.
Legacy A computer state where power management policy decisions are made by the platform hardware/ﬁrmware
shipped with the system. The legacy power management features found in today’s systems are used to support
power management in a system that uses a legacy OS that does not support the OS-directed power management
architecture.
Legacy BIOS One form of Host Processor Boot Firmware used on x86 platforms which uses a legacy x86 BIOS
structure. This form of host processor boot ﬁrmware has been or is being replaced by UEFI. This term will
likely be most useful in distinguishing and comparing older forms of ﬁrmware to newer forms (e.g., “it was
done this way in legacy BIOS, but is now done another way in UEFI). See also: BIOS ,System BIOS .
Legacy Hardware A computer system that has no ACPI or OSPM power management support.
Legacy OS An OS that is not aware of and does not direct the power management functions of the system. Included
in this category are operating systems with APM 1.x support.
Local APIC A local Advanced Programmable Interrupt Controller receives interrupts from the I/O APIC.
Local SAPIC A local Streamlined Advanced Programmable Interrupt Controller receives interrupts from the I/O
SAPIC.
Management Firmware Firmware used only by a Baseboard Management Controller (BMC) or other Out-of-Band
(OOB) management controller.
2.1. General ACPI Terminology 18Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Multiple APIC Description Table (MADT) The Multiple APIC Description Table (MADT) is used on systems
supporting the APIC and SAPIC to describe the APIC implementation. Following the MADT is a list of
APIC/SAPIC structures that declare the APIC/SAPIC features of the machine.
Namespace A namespace deﬁnes a contiguously-addressed range of Non-V olatile Memory, conceptually similar to
a SCSI Logical Unit (LUN) or an NVM Express namespace. A namespace can be described by one or more
Labels.
Non-Host Processor A non-host processor is a generic term used to describe any processing unit on a platform which
is not a host processor (e.g. a microcontroller, co-processor, etc). For the purposes of this particular ECR, this
should also be considered a synonym for “secondary processor”, those CPUs that might be on an SoC, for
example, that are not the host (or “boot”) processor.
NVDIMM Non V olatile Dual In-line Memory Module.
Object The nodes of the ACPI Namespace are objects inserted in the tree by the OS using the information in the
system deﬁnition tables. These objects can be data objects, package objects, control method objects, and so on.
Package objects refer to other objects. Objects also have type, size, and relative name.
Object name Part of the ACPI Namespace. There is a set of rules for naming objects.
Operating System-directed Power Management (OSPM) A model of power (and system) management in which
the OS plays a central role and uses global information to optimize system behavior for the task at hand.
Option ROM Firmware Legacy term for boot ﬁrmware typically executed on a host processor which is used by a
device during the boot process. Option ROM ﬁrmware may be included with the host processor boot ﬁrmware
or may be carried separately by a device (such as an add-in card). See also: Expansion ROM Firmware
Package An array of objects.
Peripheral A peripheral (also known as an external device) is a device which resides physically external to a platform
and is connected to a platform, either wired or wirelessly. A peripheral is comprised of its own devices which
may have their own ﬁrmware.
Persistent Memory (pmem) Byte-addressable memory that retains its contents across power loss.
Platform A platform consists of multiple devices assembled and working together to deliver a speciﬁc computing
function, but does not include any other software other than the ﬁrmware as part of the devices in the platform.
Examples of platforms include a notebook, a desktop, a server, a network switch, a blade, etc. - all without and
independent of any operating system, user applications, or user data.
Platform Boot Firmware The collection of all boot ﬁrmware on a platform. This ﬁrmware is initially loaded by a
platform (such as an SoC, a motherboard, or a complete system) at power-on to do basic initialization of the
platform hardware and then hand control to a boot loader or OS. In some cases this will be x86 BIOS, or it may
be UEFI Core System BIOS, or it could be something else entirely. Once control has been handed over to a boot
loader or an OS, this ﬁrmware has no further role.
Platform Runtime Firmware The collection of all run-time ﬁrmware on a platform. This is ﬁrmware that can pro-
vide functions that can be invoked by an OS, but those functions are still concerned only with the platform
hardware (e.g., PSCI on ARM). The assumption is that platform boot ﬁrmware has since been superceded by
the OS since the OS is now up and running, but that there is still a need for an OS to access speciﬁc features of
hardware that may only be possible via ﬁrmware.
Platform Firmware The collection of platform boot ﬁrmware and platform runtime ﬁrmware.
Power Button A user push button or other switch contact device that switches the system from the sleeping/soft off
state to the working state, and signals the OS to transition to a sleeping/soft off state from the working state.
Power Management Mechanisms in software and hardware to minimize system power consumption, manage system
thermal limits, and maximize system battery life. Power management involves trade-offs among system speed,
noise, battery life, processing speed, and alternating current (AC) power consumption. Power management
2.1. General ACPI Terminology 19Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
is required for some system functions, such as appliance (for example, answering machine, furnace control)
Power Resources Resources (for example, power planes and clock sources) that a device requires to operate in a
given power state.
Power Sources The battery (including a UPS battery) and AC line powered adapters or power supplies that supply
power to a platform.
Register Grouping Consists of two register blocks (it has two pointers to two different blocks of registers). The
ﬁxed-position bits within a register grouping can be split between the two register blocks. This allows the bits
within a register grouping to be split between two chips.
Reserved Bits Some unused bits in ACPI hardware registers are designated as “Reserved” in the ACPI speciﬁcation.
For future extensibility, hardware-register reserved bits always return zero, and data writes to them have no side
effects. OSPM implementations must write zeros to all reserved bits in enable and status registers and preserve
bits in control registers.
Root System Description Pointer (RSDP) An ACPI-compatible system must provide an RSDP in the system’s low
address space. This structure’s only purpose is to provide the physical address of the RSDT and XSDT.
Root System Description Table (RSDT) A table with the signature ‘RSDT,’ followed by an array of physical point-
ers to other system description tables. The OS locates that RSDT by following the pointer in the RSDP structure.
Runtime Firmware Generic term to describe any ﬁrmware on a platform used during runtime (i.e., after the boot
process has completed). Use a more speciﬁc term, if possible.
Secondary System Description Table (SSDT) SSDTs are a continuation of the DSDT. Multiple SSDTs can be used
as part of a platform description. After the DSDT is loaded into the ACPI Namespace, each secondary descrip-
tion table listed in the RSDT/XSDT with a unique OEM Table ID is loaded. This allows the OEM to provide
the base support in one table, while adding smaller system options in other tables.
System Physical Address (SPA) The platform physical address assigned and programmed by the platform and uti-
lized by the OS.
Sleep Button A user push button that switches the system from the sleeping/soft off state to the working state, and
signals the OS to transition to a sleeping state from the working state.

Smart Battery Subsystem A battery subsystem that conforms to the following speciﬁcations: Smart Battery and
either Smart Battery System Manager or Smart Battery Charger and Selector–and the additional ACPI require-
ments.
Smart Battery Table An ACPI table used on platforms that have a Smart Battery subsystem. This table indicates
the energy-level trip points that the platform requires for placing the system into different sleeping states and
suggested energy levels for warning the user to transition the platform into a sleeping state.
SMBus Interface A standard hardware and software communications interface between an OS bus driver and an
SMBus controller.
Software Software is comprised of elements required to load the operating system and all user applications and user
data subsequently handled by the operating system.
Streamlined Advanced Programmable Interrupt Controller (SAPIC) An advanced APIC commonly found on
Intel ItaniumTMProcessor Family-based 64-bit systems.
System A system is the entirety of a computing entity, including all elements in a platform (hardware, ﬁrmware) and
software (operating system, user applications, user data). A system can be thought of both as a logical construct
(e.g. a software stack) or physical construct (e.g. a notebook, a desktop, a server, a network switch, etc).
System BIOS A term sometimes used in industry to refer to either Legacy BIOS, or to UEFI Core System BIOS, or
both. Please use this term only when referring to Legacy BIOS. See also: BIOS, Legacy BIOS.
System Context The volatile data in the system that is not saved by a device driver.
2.1. General ACPI Terminology 20Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
System Control Interrupt (SCI) A system interrupt used by hardware to notify the OS of ACPI events. The SCI is
an active, low, shareable, level interrupt.
System Management Bus (SMBus) A two-wire interface based upon the I2C protocol. The SMBus is a low-speed
bus that provides positive addressing for devices, as well as bus arbitration.
System Management Interrupt (SMI) An OS-transparent interrupt generated by interrupt events on legacy systems.
By contrast, on ACPI systems, interrupt events generate an OS-visible interrupt that is shareable (edge-style
interrupts will not work). Hardware platforms that want to support both legacy operating systems and ACPI
systems must support a way of re-mapping the interrupt events between SMIs and SCIs when switching between
ACPI and legacy models.
Thermal States Thermal states represent different operating environment temperatures within thermal zones of a
system. A system can have one or more thermal zones; each thermal zone is the volume of space around a
particular temperature-sensing device. The transitions from one thermal state to another are marked by trip
points, which are implemented to generate an SCI when the temperature in a thermal zone moves above or
below the trip point temperature.
UEFI One form of Host Processor Boot Firmware which uses a Uniﬁed Extensible Firmware Interface (UEFI) struc-
ture (as deﬁned by the UEFI Forum). This is the current host processor boot ﬁrmware structure being adopted
as a standard in the industry. This term should be used when referring speciﬁcally to UEFI code on a platform.
UEFI Drivers Standalone binary executables in PECOFF format which are loaded by UEFI during the boot process
to handle speciﬁc pieces of hardware.
eXtended Root System Description Table (XSDT) The XSDT provides identical functionality to the RSDT but ac-
commodates physical addresses of DESCRIPTION HEADERs that are larger than 32 bits. Notice that both the
XSDT and the RSDT can be pointed to by the RSDP structure.
2.2 Global System State Deﬁnitions
Global system states (Gx states) apply to the entire system and are visible to the user.
Global system states are deﬁned by six principal criteria:
1. Does application software run?
2. What is the latency from external events to application response?
3. What is the power consumption?
4. Is an OS reboot required to return to a working state?
5. Is it safe to disassemble the computer?
6. Can the state be entered and exited electronically?
Following is a list of the system states:
G3 Mechanical Off A computer state that is entered and left by a mechanical means (for example, turning off the
system’s power through the movement of a large red switch). It is implied by the entry of this off state through a
mechanical means that no electrical current is running through the circuitry and that it can be worked on without
damaging the hardware or endangering service personnel. The OS must be restarted to return to the Working
state. No hardware context is retained. Except for the real-time clock, power consumption is zero.
G2/S5 Soft Off A computer state where the computer consumes a minimal amount of power. No user mode or system
mode code is run. This state requires a large latency in order to return to the Working state. The system’s context
will not be preserved by the hardware. The system must be restarted to return to the Working state. It is not safe
to disassemble the machine in this state.
2.2. Global System State Deﬁnitions 21Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
G1 Sleeping A computer state where the computer consumes a small amount of power, user mode threads are not
being executed, and the system “appears” to be off (from an end user’s perspective, the display is off, and so
on). Latency for returning to the Working state varies on the wake environment selected prior to entry of this
state (for example, whether the system should answer phone calls). Work can be resumed without rebooting the
OS because large elements of system context are saved by the hardware and the rest by system software. It is
not safe to disassemble the machine in this state.
G0 Working A computer state where the system dispatches user mode (application) threads and they execute. In this
state, peripheral devices (peripherals) are having their power state changed dynamically. The user can select,
through some UI, various performance/power characteristics of the system to have the software optimize for
performance or battery life. The system responds to external events in real time. It is not safe to disassemble the
machine in this state.
S4 Non-Volatile Sleep A special global system state that allows system context to be saved and restored (relatively
slowly) when power is lost to the motherboard. If the system has been commanded to enter S4, the OS will
write all system context to a ﬁle on non-volatile storage media and leave appropriate context markers. The
machine will then enter the S4 state. When the system leaves the Soft Off or Mechanical Off state, transitioning
to Working (G0) and restarting the OS, a restore from a NVS ﬁle can occur. This will only happen if a valid
non-volatile sleep data set is found, certain aspects of the conﬁguration of the machine have not changed, and
the user has not manually aborted the restore. If all these conditions are met, as part of the OS restarting, it will
reload the system context and activate it. The net effect for the user is what looks like a resume from a Sleeping
(G1) state (albeit slower). The aspects of the machine conﬁguration that must not change include, but are not
limited to, disk layout and memory size. It might be possible for the user to swap a PC Card or a Device Bay
device, however.
Notice that for the machine to transition directly from the Soft Off or Sleeping states to S4, the system context must
be written to non-volatile storage by the hardware; entering the Working state ﬁrst so that the OS or platform runtime
ﬁrmware can save the system context takes too long from the user’s point of view. The transition from Mechanical Off
to S4 is likely to be done when the user is not there to see it.
Because the S4 state relies only on non-volatile storage, a machine can save its system context for an arbitrary period
of time (on the order of many years).
Table 2.1: Summary of Global Power States
Global system
stateSoftware
runsLatency Power con-
sumptionOS restart
requiredSafe to dis-
assemble
computerExit state
electroni-
cally
G0 Working Yes 0 Large No No Yes
G1 Sleeping No >0, varies
with sleep
stateSmaller No No Yes
G2/S5 Soft Off No Long Very near 0 Yes No Yes
G3 Mechanical Off No Long RTC battery Yes Yes No
Notice that the entries for G2/S5 and G3 in the Latency column of the above table are “Long.” This implies that a
platform designed to give the user the appearance of “instant-on,” similar to a home appliance device, will use the G0
and G1 states almost exclusively (the G3 state may be used for moving the machine or repairing it).
2.2. Global System State Deﬁnitions 22Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
2.3 Device Power State Deﬁnitions
Device power states are states of particular devices; as such, they are generally not visible to the user. For example,

assemble
cally
with sleep
some devices may be in the Off state even though the system as a whole is in the Working state.
Device states apply to any device on any bus. They are generally deﬁned in terms of four principal criteria:
• Power consumption-How much power the device uses.
• Device context–How much of the context of the device is retained by the hardware. The OS is responsible for
restoring any lost device context (this may be done by resetting the device).
• Device driver–What the device driver must do to restore the device to full on.
• Restore time–How long it takes to restore the device to full on.
The device power states are deﬁned below, although very generically. Many devices do not have all four power states
deﬁned. Devices may be capable of several different low-power modes, but if there is no user-perceptible difference
between the modes, only the lowest power mode will be used. The Device Class Power Management Speciﬁcations,
included in Appendix A of this speciﬁcation, describe which of these power states are deﬁned for a given type (class)
of device and deﬁne the speciﬁc details of each power state for that device class. For a list of the available Device
Class Power Management Speciﬁcations, see Appendix A: Device Class Speciﬁcations .
D3 (Off) Power has been fully removed from the device. Also referred to as D3cold in this and other specs. All
device context is lost when this state is entered, so the OS software will reinitialize the device when powering it
back on. Since all device context and power are lost, devices in this state do not decode their address lines, and
cannot be enumerated by software. Devices in this state have the longest restore times.
D3hot The meaning of the D3hot State is deﬁned by each device class. In general, D3hot is expected to save as
much power as possible without affecting PNP Enumeration. Devices in D3hot must have enough power to
remain enumerable by software. For example, PCI Conﬁguration space access and contents must operate as in
shallower power states. Similarly, ACPI identiﬁcation and conﬁguration objects must operate as in shallower
power states. Otherwise, no device functionality is supported, and Driver software is required to restore any lost
context, or reinitialize the device, during its transition back to D0.
Devices in this state can have long restore times. All classes of devices deﬁne this state.
Note: For devices that support both D3hot and D3 exposed to OSPM via _PR3, device software/drivers must al-
ways assume OSPM will target D3and must assume all device context will be lost and the device will no longer be
enumerable.
D2The meaning of the D2 Device State is deﬁned by each device class. Many device classes may not deﬁne D2. In
general, D2 is expected to save more power and preserve less device context than D1 or D0. Buses in D2 may
cause the device to lose some context (for example, by reducing power on the bus, thus forcing the device to
turn off some of its functions).
D1The meaning of the D1 Device State is deﬁned by each device class. Many device classes may not deﬁne D1. In
general, D1 is expected to save less power and preserve more device context than D2.
D0 (Fully-On) This state is assumed to be the highest level of power consumption. The device is completely active
and responsive, and is expected to remember all relevant context continuously.
Transitions amongst these power states are restricted for simplicity. Power-down transitions (from higher-power, or
shallower, to lower-power, or deeper) are allowed between any two states. However, power-up transitions (from deeper
to shallower) are required to go through D0; i.e. Dy to Dx<y is illegal for all x !=0.
2.3. Device Power State Deﬁnitions 23Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 2.2: Summary of Device Power States
Device State Power Consumption Device Context Retained Driver Restoration
D0 - Fully-On As needed for operation All None
D1 D0>D1>D2> D3hot>D3 >D2 <D2
D2 D0>D1>D2> D3hot>D3 <D1 >D1
D3hot D0>D1>D2>D3hot>D3 Optional None <->Full initializa-
tion and load
D3 - Off 0 None Full initialization and load
Note: Devices often have different power modes within a given state. Devices can use these modes as long as they can
automatically transparently switch between these modes from the software, without violating the rules for the current
Dx state the device is in. Low-power modes that adversely affect performance (in other words, low speed modes) or
that are not transparent to software cannot be done automatically in hardware; the device driver must issue commands
to use these modes.
2.3.1 Device Performance States
Device performance states (Px states) are power consumption and capability states within the active (D0) device power
state. Performance states allow OSPM to make tradeoffs between performance and energy conservation. Device
performance states have the greatest impact when the implementation is such that the states invoke different device
efﬁciency levels as opposed to a linear scaling of performance and energy consumption. Since performance state
transitions occur in the active device states, care must be taken to ensure that performance state transitions do not
adversely impact the system.
Device performance states, when necessary, are deﬁned on a per device class basis (See Appendix A: Device Class
Speciﬁcations for more information).
2.4 Sleeping and Soft-off State Deﬁnitions
S1-S4 are types of sleeping states within the global system state, G1, while S5 is a soft-off state associated with the
G2 system state. The Sx states are brieﬂy deﬁned below.
For a detailed deﬁnition of the system behavior within each Sx state, see \_Sx (System States) . For a detailed deﬁnition
of the transitions between each of the Sx states, see Sleeping States .
S1 Sleeping State The S1 sleeping state is a low wake latency sleeping state. In this state, no system context is lost
(CPU or chip set) and hardware maintains all system context.
S2 Sleeping State The S2 sleeping state is a low wake latency sleeping state. This state is similar to the S1 sleeping
state except that the CPU and system cache context is lost (the OS is responsible for maintaining the caches and
CPU context). Control starts from the processor’s reset vector after the wake event.
S3 Sleeping State The S3 sleeping state is a low wake latency sleeping state where all system context is lost except
system memory. CPU, cache, and chip set context are lost in this state. Hardware maintains memory context
and restores some CPU and L2 conﬁguration context. Control starts from the processor’s reset vector after the
wake event.
S4 Sleeping State The S4 sleeping state is the lowest power, longest wake latency sleeping state supported by ACPI.
In order to reduce power to a minimum, it is assumed that the hardware platform has powered off all devices.
Platform context is maintained.
2.4. Sleeping and Soft-off State Deﬁnitions 24Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
S5 Soft Off State The S5 state is similar to the S4 state except that the OS does not save any context. The system
is in the “soft” off state and requires a complete boot when it wakes. Software uses a different state value to
distinguish between the S5 state and the S4 state to allow for initial boot operations within the platform boot
ﬁrmware to distinguish whether the boot is going to wake from a saved memory image.
2.5 Processor Power State Deﬁnitions
Processor power states (Cx states) are processor power consumption and thermal management states within the global
working state, G0. The Cx states possess speciﬁc entry and exit semantics and are brieﬂy deﬁned below. For a more
detailed deﬁnition of each Cx state, see Processor Power States .
C0 Processor Power State While the processor is in this state, it executes instructions.
C1 Processor Power State This processor power state has the lowest latency. The hardware latency in this state
must be low enough that the operating software does not consider the latency aspect of the state when deciding
whether to use it. Aside from putting the processor in a non-executing power state, this state has no other
software-visible effects.
C2 Processor Power State The C2 state offers improved power savings over the C1 state. The worst-case hardware
latency for this state is provided via the ACPI system ﬁrmware and the operating software can use this informa-
tion to determine when the C1 state should be used instead of the C2 state. Aside from putting the processor in
a non-executing power state, this state has no other software-visible effects.
C3 Processor Power State The C3 state offers improved power savings over the C1 and C2 states. The worst-case
hardware latency for this state is provided via the ACPI system ﬁrmware and the operating software can use this
information to determine when the C2 state should be used instead of the C3 state. While in the C3 state, the

processor’s caches maintain state but ignore any snoops. The operating software is responsible for ensuring that
the caches maintain coherency.
2.6 Device and Processor Performance State Deﬁnitions
Device and Processor performance states (Px states) are power consumption and capability states within the ac-
tive/executing states, C0 for processors and D0 for devices. The Px states are brieﬂy deﬁned below. For a more
detailed deﬁnition of each Px state from a processor perspective, see Processor Performance Control . For a more
detailed deﬁnition of each Px state from a device perspective see Device and Processor Performance States , and
Appendix A: Device Class Speciﬁcations .
P0 Performance State While a device or processor is in this state, it uses its maximum performance capability and
may consume maximum power.
P1 Performance State In this performance power state, the performance capability of a device or processor is limited
below its maximum and consumes less than maximum power.
Pn Performance State In this performance state, the performance capability of a device or processor is at its min-
imum level and consumes minimal power while remaining in an active state. State n is a maximum number
and is processor or device dependent. Processors and devices may deﬁne support for an arbitrary number of
performance states not to exceed 255.
2.5. Processor Power State Deﬁnitions 25CHAPTER
THREE
ACPI CONCEPTS
Platforms compliant with the ACPI speciﬁcation provide OSPM with direct and exclusive control over the power
management and motherboard device conﬁguration functions of a computer. During OS initialization, OSPM takes
over these functions from legacy implementations such as the APM BIOS, SMM-based ﬁrmware, legacy applications,
and the PNPBIOS. Having done this, OSPM is responsible for handling motherboard device conﬁguration events as
well as for controlling the power, performance, and thermal status of the system based on user preference, application
requests and OS imposed Quality of Service (QOS) / usability goals. ACPI provides low-level interfaces that allow
OSPM to perform these functions. The functional areas covered by the ACPI speciﬁcation are:
System power management ACPI deﬁnes mechanisms for putting the computer as a whole in and out of system
sleeping states. It also provides a general mechanism for any device to wake the computer.
Device power management ACPI tables describe motherboard devices, their power states, the power planes the de-
vices are connected to, and controls for putting devices into different power states. This enables the OS to put
devices into low-power states based on application usage.
Processor power management While the OS is idle but not sleeping, it will use commands described by ACPI to
put processors in low-power states.
Device and processor performance management While the system is active, OSPM will transition devices and pro-
cessors into different performance states, deﬁned by ACPI, to achieve a desirable balance between performance
and energy conservation goals as well as other environmental requirements (for example, visibility and acous-
tics).
Conﬁguration / Plug and Play ACPI speciﬁes information used to enumerate and conﬁgure motherboard devices.
This information is arranged hierarchically so when events such as docking and undocking take place, the OS
has precise, a priori knowledge of which devices are affected by the event.
System Events ACPI provides a general event mechanism that can be used for system events such as thermal events,
power management events, docking, device insertion and removal, and so on. This mechanism is very ﬂexible
in that it does not deﬁne speciﬁcally how events are routed to the core logic chip set.
Battery management Battery management policy moves from the APM BIOS to the ACPI OS. An ACPI-compatible
battery device needs either a Smart Battery subsystem interface, which is controlled by the OS directly through
the embedded controller interface, or a Control Method Battery interface. A Control Method Battery interface
is completely deﬁned by AML control methods, allowing an OEM to choose any type of the battery and any
kind of communication interface supported by ACPI. The battery must comply with the requirements of its
interface, as described either herein or in other applicable standards. The OS may choose to alter the behavior
of the battery, for example, by adjusting the Low Battery or Battery Warning trip point. When there are multiple
batteries present, the battery subsystem is not required to perform any synthesis of a “composite battery” from
the data of the separate batteries. In cases where the battery subsystem does not synthesize a “composite battery”
from the separate battery’s data, the OS must provide that synthesis.
Thermal management Since the OS controls the power and performance states of devices and processors, ACPI also
addresses system thermal management. It provides a simple, scalable model that allows OEMs to deﬁne thermal
zones, thermal indicators, and methods for cooling thermal zones.
26Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
SMBus Controller ACPI deﬁnes a standard hardware and software communications interface between an OS bus
driver and an SMBus Controller. This allows any OS to provide a standard bus driver that can directly commu-
nicate with SMBus devices in the system. This in turn enables the OEM to provide platform features that the
OS and applications can use.
OSPM’s mission is to optimally conﬁgure the platform and to optimally manage the system’s power, performance,
and thermal status given the user’s preferences and while supporting OS imposed Quality of Service (QOS) / usability
goals. To achieve these goals, ACPI requires that once an ACPI compliant platform is in ACPI mode, the platform’s
hardware, ﬁrmware, or other non-OS software must not manipulate the platform’s conﬁguration, power, performance,
and thermal control interfaces independently of OSPM. OSPM alone is responsible for coordinating the conﬁguration,
power management, performance management, and thermal control policy of the system. Manipulation of these
interfaces independently of OSPM undermines the purpose of OSPM/ACPI and may adversely impact the system’s
conﬁguration, power, performance, and thermal policy goals. There are two exceptions to this requirement. The ﬁrst
is in the case of the possibility of damage to a system from an excessive thermal conditions where an ACPI compatible
OS is present and OSPM latency is insufﬁcient to remedy an adverse thermal condition. In this case, the platform may
exercise a failsafe thermal control mechanism that reduces the performance of a system component to avoid damage.
If this occurs, the platform must notify OSPM of the performance reduction if the reduction is of signiﬁcant duration
(in other words, if the duration of reduced performance could adversely impact OSPM’s power or performance control
policy - operating system vendors can provide guidance in this area). The second exception is the case where the
platform contains Active cooling devices but does not contain Passive cooling temperature trip points or controls,. In
this case, a hardware based Active cooling mechanism may be implemented without impacting OSPM’s goals. Any
platform that requires both active and passive cooling must allow OSPM to manage the platform thermals via ACPI
deﬁned active and passive cooling interfaces.
3.1 System Power Management
Under OSPM, the OS directs all system and device power state transitions. Employing user preferences and knowledge
of how devices are being used by applications, the OS puts devices in and out of low-power states. Devices that are
not being used can be turned off. Similarly, the OS uses information from applications and user settings to put the
system as a whole into a low- power state. The OS uses ACPI to control power state transitions in hardware.
3.2 Power States
From a user-visible level, the system can be thought of as being in one of the states in the following diagram:
See Section 2.2 for detailed deﬁnitions of these states.
In general use, computers alternate between the Working and Sleeping states. In the Working state, the computer is
used to do work. User-mode application threads are dispatched and running. Individual devices can be in low-power
(Dx) states and processors can be in low-power (Cx) states if they are not being used. Any device the system turns off
because it is not actively in use can be turned on with short latency. (What “short” means depends on the device. An
LCD display needs to come on in sub-second times, while it is generally acceptable to wait a few seconds for a printer
to wake.)
The net effect of this is that the entire machine is functional in the Working state. Various Working sub-states differ
in speed of computation, power used, heat produced, and noise produced. Tuning within the Working state is largely

to wake.)
about trade-offs among speed, power, heat, and noise.
When the computer is idle or the user has pressed the power button, the OS will put the computer into one of the
sleeping (Sx) states. No user-visible computation occurs in a sleeping state. The sleeping sub-states differ in what
events can arouse the system to a Working state, and how long this takes. When the machine must awaken to all
possible events or do so very quickly, it can enter only the sub-states that achieve a partial reduction of system power
consumption. However, if the only event of interest is a user pushing on a switch and a latency of minutes is allowed,
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Fig. 3.1: Global System Power States and Transitions
the OS could save all system context into an NVS ﬁle and transition the hardware into the S4 sleeping state. In this
state, the machine draws almost zero power and retains system context for an arbitrary period of time (years or decades
if needed).
The other states are used less often. Computers that support legacy BIOS power management interfaces boot in the
Legacy state and transition to the Working state when an ACPI OS loads. A system without legacy support (for
example, a RISC system) transitions directly from the Mechanical Off state to the Working state. Users typically put
computers into the Mechanical Off state by ﬂipping the computer’s mechanical switch or by unplugging the computer.
3.2.1 Power Button
In legacy systems, the power button typically either forces the machine into Soft Off or Mechanical Off or, on a laptop,
forces it to some sleeping state. No allowance is made for user policy (such as the user wants the machine to “come
on” in less than 1 second with all context as it was when the user turned the machine “off”), system alert functions
(such as the system being used as an answering machine or fax machine), or application function (such as saving a
user ﬁle).
In an OSPM system, there are two switches. One is to transition the system to the Mechanical Off state. A mechanism
to stop current ﬂow is required for legal reasons in some jurisdictions (for example, in some European countries). The
other is the “main” power button. This is in some obvious place (for example, beside the keyboard on a laptop). Unlike
legacy on/off buttons, all it does is send a request to the system. What the system does with this request depends on
policy issues derived from user preferences, user function requests, and application data.
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3.2.2 Platform Power Management Characteristics
3.2.2.1 Mobile PC
Mobile PCs will continue to have aggressive power management functionality. Going to OSPM/ACPI will allow
enhanced power savings techniques and more reﬁned user policies.
Aspects of mobile PC power management in the ACPI speciﬁcation are thermal management (see Section 3.10).
3.2.2.2 Desktop PCs
Power-managed desktops will be of two types, though the ﬁrst type will migrate to the second over time.
Ordinary “Green PC” Here, new appliance functions are not the issue. The machine is really only used for pro-
ductivity computations. At least initially, such machines can get by with very minimal function. In particular,
they need the normal ACPI timers and controls, but don’t need to support elaborate sleeping states, and so on.
They, however, do need to allow the OS to put as many of their devices/resources as possible into device standby
and device off states, as independently as possible (to allow for maximum compute speed with minimum power
wasted on unused devices). Such PCs will also need to support wake from the sleeping state by means of a
timer, because this allows administrators to force them to turn on just before people are to show up for work.
Home PC Computers are moving into home environments where they are used in entertainment centers and to per-
form tasks like answering the phone. A home PC needs all of the functionality of the ordinary green PC. In fact,
it has all of the ACPI power functionality of a laptop except for docking and lid events (and need not have any
legacy power management). Note that there is also a thermal management aspect to a home PC, as a home PC
user wants the system to run as quietly as possible, often in a thermally constrained environment.
3.2.2.3 Multiprocessor and Server PCs
Perhaps surprisingly, server machines often get the largest absolute power savings. Why? Because they have the
largest hardware conﬁgurations and because it’s not practical for somebody to hit the off switch when they leave at
night.
Day Mode In day mode, servers are power-managed much like a corporate ordinary green PC, staying in the Working
state all the time, but putting unused devices into low-power states whenever possible. Because servers can be
very large and have, for example, many disk spindles, power management can result in large savings. OSPM
allows careful tuning of when to do this, thus making it workable.
Night Mode In night mode, servers look like home PCs. They sleep as deeply as they can and are still able to wake
and answer service requests coming in over the network, phone links, and so on, within speciﬁed latencies. So,
for example, a print server might go into deep sleep until it receives a print job at 3 A.M., at which point it
wakes in perhaps less than 30 seconds, prints the job, and then goes back to sleep. If the print request comes
over the LAN, then this scenario depends on an intelligent LAN adapter that can wake the system in response
to an interesting received packet.
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3.3 Device Power Management
This section describes ACPI-compatible device power management. The ACPI device power states are introduced, the
controls and information an ACPI-compatible OS needs to perform device power management are discussed, the wake
operation devices use to wake the computer from a sleeping state is described, and an example of ACPI-compatible
device management using a modem is given
3.3.1 Device Power Management Model
ACPI Device Power Management is based on an integrated model consisting of:
Distributed device power state policy For each hardware device on the system, there is a Power Policy Owner in
the Operating System that is responsible for continuously determining the best power state for the device. The
best device power state is the one that, at any point in time, minimizes the consumption of power by the device
consistent with the usage requirements of the device by the system and its user. Policy is typically deﬁned for
a class of devices, and incorporates application activity, user scenarios and other operating state as necessary. It
is applied to all devices of a given class.
Layered device power state control Once power state decisions are made for a device, they must be carried-out by
device drivers. The model partitions the control functionality between the device, bus and platform layers.
Device drivers at each layer perform control using mechanisms available at that level, coordinated by OSPM. In
general, the ordering proceeds from Device/Class level, to Bus level, to Platform level when a device is powering
down, and the inverse when powering-up.
For instance, a device-level driver has access, via the device programming interface, to settings and control
registers that invoke speciﬁc, sometimes proprietary, power control features in the device. The device driver
uses these controls as appropriate for the target ACPI-deﬁned power state determined by the policy owner.
Similarly, classes of devices may have standardized power features, invoked in standardized ways that Class
Drivers might use when entering a target power state.
At the bus level, power management standards come into play to provide bus-speciﬁc controls that work for
every device connected to the bus, regardless of device class. PCI, for instance, deﬁnes ﬁelds in the device
Conﬁguration Space for setting the device’s power state (D0-D3). Bus-level drivers utilize these standards to
perform control in addition to that applied by the device-speciﬁc or device class driver. Bus-speciﬁc mechanisms
also enable additional power savings in the system by enabling the bus infrastructure hardware itself to enter
lower power states, as deﬁned in the bus standard.
Finally, for platform-level power state control, ACPI deﬁnes mechanisms (_PRx, _PSx, _ON, _OFF) for putting
a device into a given power state. The Operating System’s Power Management software (OSPM) utilizes these
mechanisms to execute the lowest-level, platform-speciﬁc control for a given device (such as turning power rails
and clocks off and on, resetting hardware, etc.).
Operating System coordination Finally, ACPI deﬁnes information and behavior requirements that enable OSPM to

inform the Power Policy Owner about supported state and wake-up capabilities, and to coordinate the actions
of the various levels of device drivers in controlling power. OSPM, in this role, is responsible for ensuring that
device power management is coordinated with System Power Management such as entering sleep states (S1-
S4) or Low-power Idle states (LPI). Integrated with device power state policy and control, wake-up policy and
control are also coordinated by OSPM. Power Policy Owners, which decide when the device might be needed
to wake the system, ensure that only device power states that the device can wake from are selected when the
platform enters a Sleep or LPI state. Enabling of wake-up hardware is also performed at the device, bus and
platform levels and coordinated by OSPM. OSPM ensures further that the Sleep or LPI state selected for the
system is compatible with the device state and wake-up capabilities of all the devices currently enabled for wake.
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3.3.2 Power Management Standards
To manage power of all the devices in the system, the OS needs standard methods for sending commands to a device.
These standards deﬁne the operations used to manage power of devices on a particular I/O interconnect and the power
states that devices can be put into. Deﬁning these standards for each I/O interconnect creates a baseline level of power
management support the OS can utilize. Independent Hardware Vendors (IHVs) do not have to spend extra time
writing software to manage power of their hardware, because simply adhering to the standard gains them direct OS
support. For OS vendors, the I/O interconnect standards allow the power management code to be centralized in the
driver for each I/O interconnect. Finally, I/O interconnect-driven power management allows the OS to track the states
of all devices on a given I/O interconnect. When all the devices are in a given state (or example, D3 - off), the OS can
put the entire I/O interconnect into the power supply mode appropriate for that state (for example, D3 - off).
I/O interconnect-level power management speciﬁcations are written for a number of buses including:
• PCI
• PCI Express
• CardBus
• USB
• IEEE 1394
3.3.3 Device Power States
To unify nomenclature and provide consistent behavior across devices, standard deﬁnitions are used for the power
states of devices. Generally, these states are deﬁned in terms of the following criteria:
• Power consumption–How much power the device uses.
• Device context–How much of the context of the device is retained by the hardware.
• Device driver–What the device driver must do to restore the device to fully on.
• Restore latency–How long it takes to restore the device to fully on.
More speciﬁcally, power management speciﬁcations for each class of device (for example, modem, network adapter,
hard disk, and so on) more precisely deﬁne the power states and power policy for the class. See Device Power States
for a detailed description of the general device power states (D0-D3).
3.3.4 Device Power State Deﬁnitions
The device power state deﬁnitions are device-independent, but classes of devices on a bus must support some consistent
set of power-related characteristics. For example, when the bus-speciﬁc mechanism to set the device power state to
a given level is invoked, the actions a device might take and the speciﬁc sorts of behaviors the OS can assume while
the device is in that state will vary from device type to device type. For a fully integrated device power management
system, these class-speciﬁc power characteristics must also be standardized:
Device Power State Characteristics Each class of device has a standard deﬁnition of target power consumption lev-
els, state-change latencies, and context loss.
Minimum Device Power Capabilities Each class of device has a minimum standard set of power capabilities.
Device Functional Characteristics Each class of device has a standard deﬁnition of what subset of device function-
ality or features is available in each power state (for example, the net card can receive, but cannot transmit; the
sound card is fully functional except that the power amps are off, and so on).
Device Wakeup Characteristics Each class of device has a standard deﬁnition of its wake policy.
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The Device Class power management speciﬁcations deﬁne these power state characteristics for each class of device.
SeeAppendix A: Device Class Speciﬁcations .
3.4 Controlling Device Power
ACPI interfaces provide the control methods and information needed to manage device power. OSPM leverages these
interfaces to perform tasks like determining the capabilities of a device, executing methods to set a device’s power
state or get its status, and enabling a device to wake the machine.
• Other buses enumerate some devices on the main board. For example, PCI devices are reported through the
standard PCI enumeration mechanisms. Power management of these devices is handled through their own bus
speciﬁcation (in this case, PCI). All other devices on the main board are handled through ACPI. Speciﬁcally,
the ACPI table lists legacy devices that cannot be reported through their own bus speciﬁcation, the root of each
bus in the system, and devices that have additional power management or conﬁguration options not covered by
their own bus speciﬁcation.
For more detailed information see Section 7
3.4.1 Getting Device Power Capabilities
As the OS enumerates devices in the system, it gets information about the power management features that the device
supports. The Differentiated Deﬁnition Block given to the OS by the platform boot ﬁrmware describes every device
handled by ACPI. This description contains the following information:
• A description of what power resources (power planes and clock sources) the device needs in each power state
that the device supports. For example, a device might need a high power bus and a clock in the D0 state but only
a low-power bus and no clock in the D2 state.
• A description of what power resources a device needs in order to wake the machine (or none to indicate that the
device does not support wake). The OS can use this information to infer what device and system power states
from which the device can support wake.
• The optional control method the OS can use to set the power state of the device and to get and set resources.
In addition to describing the devices handled by ACPI, the table lists the power planes and clock sources themselves
and the control methods for turning them on and off. For detailed information, see Section 7.
3.4.2 Setting Device Power States
OSPM uses the Set Power State operation to put a device into one of the four power states.
When a device is put in a lower power state, it conﬁgures itself to draw as little power from the bus as possible. The
OS tracks the state of all devices on the bus, and will put the bus in the best power state based on the current device
requirements on that bus. For example, if all devices on a bus are in the D3 state, the OS will send a command to the
bus control chip set to remove power from the bus (thus putting the bus in the D3 state). If a particular bus supports a
low-power supply state, the OS puts the bus in that state if all devices are in the D1 or D2 state. Whatever power state
a device is in, the OS must be able to issue a Set Power State command to resume the device.
• The device does not need to have power to do this. The OS must turn on power to the device before it can send
commands to the device.
OSPM also uses the Set Power State operation to enable power management features such as wake (described in Power
and Performance Management ).
For power-down operations (transitions from Dx to some deeper Dy), OSPM ﬁrst evaluates the appropriate control
method for the target state (_PSx), then turns-off any unused power resources. Notice that this might not mean that
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power is actually removed from the device. If other active devices are sharing a power resource, the power resource
will remain on. In the power-up case (transitions from some Dx back to the shallower D0), the power resources
required for D0 are ﬁrst turned on, and then the control method (_PS0) is evaluated.
3.4.3 Getting Device Power Status
OSPM uses the Get Power Status operation to determine the current power conﬁguration (states and features), as well
as the status of any batteries supported by the device. The device can signal an SCI to inform the OS of changes in
power status. For example, a device can trigger an interrupt to inform the OS that the battery has reached low power
level.
Devices use the ACPI event model to signal power status changes (for example, battery status changes) to OSPM. The

level.
platform signals events to the OS via an interrupt, either SCI, or GPIO. An interrupt status bit is set to indicate the
event to the OS. The OS runs the control method associated with the event. This control method signals to the OS
which device has changed.
ACPI supports two types of batteries: batteries that report only basic battery status information and batteries that
support the Smart Battery System Implementers Forum “Smart Battery Speciﬁcation”. For batteries that report only
basic battery status information (such as total capacity and remaining capacity), the OS uses control methods from the
battery’s description table to read this information. To read status information for Smart Batteries, the OS can use a
standard Smart Battery driver that directly interfaces to Smart Batteries through the appropriate bus enumerator.
3.4.4 Waking the System
The wake operation enables devices to wake the system from a sleeping or low-power idle state. This operation must
not depend on the CPU because the CPU will not be executing instructions.
The OS ensures any bridges between the device and the core logic are in the lowest power state in which they can still
forward the wake signal. When a device with wake enabled decides to wake the system, it sends the deﬁned signal on
its bus. Bus bridges must forward this signal to upstream bridges using the appropriate signal for that bus. Thus, the
signal eventually reaches the core chip set (for example, an ACPI chip set), which in turn wakes the system.
Before putting the system in a sleeping power state, the OS determines which devices are needed to wake the system
based on application requests, and then enables wake on those devices in a device and bus speciﬁc manner.
The OS enables the wake feature on devices by setting that device’s SCI Enable bit or unmasking its wake interrupt.
The location of this control is listed in the device’s entry in the description table. Only devices that have their wake
feature enabled can wake the system. The OS keeps track of the power states that the wake devices support, and
keeps the system in a power state in which the wake can still wake the system (based on capabilities reported in the
description table).
When the system is in a Sleeping or low-power idle state and a wake device decides to wake the system, it signals
to the core logic. The status bit corresponding to the device waking the system is set, and the core logic resumes the
system. After the OS is running again, it determines the device responsible for the wake event by either running a
control method (for wake events) or processing the device’s ISR (for wake interrupts).
• Besides using ACPI mechanism to enable a particular device to wake the system, an ACPI platform must also
be able to record and report the wake source to OSPM. When a system is woken from certain states (such as the
S4 state), it may start out in non-ACPI mode. In this case, the SCI status bit may be cleared when ACPI mode is
re-entered. However the platform must still attempt to record the wake source for retrieval by OSPM at a later
point.
• Although the above description explains how a device can wake the system, note that a device can also be put
into a low power state during the S0 system state, and that this device may generate a wake signal in the S0 state
as the following example illustrates.
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3.4.5 Example: Modem Device Power Management
To illustrate how these power management methods function in ACPI, consider an integrated modem. (This example
is greatly simpliﬁed for the purposes of this discussion.) The power states of a modem are deﬁned as follows (from
the Modem Device Class Power Management Speciﬁcation):
D0Modem controller on Phone interface on Speaker on Can be on hook or off hook Can be waiting for answer
D1Modem controller in low-power mode (context retained by device) Phone interface powered by phone line or in
low-power mode Speaker off Must be on hook
D2Same as D3
D3Modem controller off (context lost) Phone interface powered by phone line or off Speaker off On hook
The power policy for the modem is deﬁned as follows:
D3 D0 COM port opened
D0, D1 D3 COM port closed
D0 D1 Modem put in answer mode
D1 D0 Application requests dial or the phone rings while the modem is in answer mode
The wake policy for the modem is very simple: When the phone rings and wake is enabled, wake the system.
Based on that policy, the modem and the COM port to which it is attached can be implemented in hardware as shown
in Figure 3-2. This is just an example for illustrating features of ACPI. This example is not intended to describe how
OEMs should build hardware.
Fig. 3.2: Example Modem and COM Port Hardware
Note: Although not shown above, each discrete part has some isolation logic so that the part is isolated when power is
removed from it. Isolation logic controls are implemented as power resources in the ACPI Differentiated Description
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Block so that devices are isolated as power planes are sequenced off.
3.4.5.1 Obtaining the Modem Capabilities
The OS determines the capabilities of this modem when it enumerates the modem by reading the modem’s entry in
the Differentiated Deﬁnition Block. In this case, the entry for the modem would report:
The device supports D0, D1, and D3:
• D0 requires PWR1 and PWR2 as power resources D1 requires PWR1 as a power resource (D3 implicitly requires
no power resources)
• To wake the system, the modem needs no power resources (implying it can wake the system from D0, D1, and
D3)
Control methods for setting power state and resources
3.4.5.2 Setting the Modem Power State
While the OS is running (G0 state), it switches the modem to different power states according to the power policy
deﬁned for modems.
When an application opens the COM port, the OS turns on the modem by putting it in the D0 state. Then if the
application puts the modem in answer mode, the OS puts the modem in the D1 state to wait for the call. To make this
power-down transition, OSPM ﬁrst runs a control method (_PS1) provided in the modem’s entry to put the device in
the D1 state. In this example, this control method asserts the MDM_D1 signal that tells the modem controller to go
into a low-power mode. OSPM then checks to see what power resources are no longer needed by the modem device.
In this case, PWR2 is no longer needed. Then it checks to make sure no other device in the system requires the use of
the PWR2 power resource. If the resource is no longer needed, the OSPM uses the _OFF control method associated
with that power resource in the Differentiated Deﬁnition Block to turn off the PWR2 power plane. This control method
sends the appropriate commands to the core chip set to stop asserting the PWR2_EN line.
OSPM does not always turn off power resources when a given device is put in a lower power state. For example,
assume that the PWR1 power plane also powers an active line printer (LPT) port. Suppose the user terminates the
modem application, causing the COM port to be closed, and therefore causing the modem to be shut off (state D3).
As always, OSPM begins the state transition process by running the modem’s control method to switch the device to
the D3 power state. The control method causes the MDM_D3 line to be asserted. Notice that these registers might not
be in the device itself. For example, the control method could read the register that controls MDM_D3.The modem
controller now turns off all its major functions so that it draws little power, if any, from the PWR1 line. OSPM
continues by checking to see which power resources are no longer needed. Because the LPT port is still active, PWR1
is in use. OSPM does not turn off the PWR1 resource. Because the COM port is closed, the same sequence of events
take place to put it in the D3 state, but the power resource is not turned off due to the LPT dependency.
3.4.5.3 Obtaining the Modem Power Status
Integrated modems have no batteries; the only power status information for the device is the power state of the modem.
To determine the modem’s current power state (D0-D3), OSPM runs a control method (_PSC) supplied in the modem’s
entry in the Differentiated Deﬁnition Block. This control method reads from the necessary registers to determine the
modem’s power state.
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3.4.5.4 Waking the System
As indicated in the modem capabilities, this modem can wake the machine from any device power state. Before putting
the system in a Sleep or LPI state, the OS enables wake on any devices that applications have requested to be able to
wake the system. Then, it chooses the deepest sleeping or LPI state that can still provide the power resources necessary

to allow all enabled wake devices to wake the system. Next, the OS puts each of those devices in the appropriate power
state. In this case, the OS puts the modem in the D3 state because it supports wake from that state. Finally, the OS
puts the system into a sleep or LPI state.
Waking the system via modem starts with the modem’s phone interface asserting its ring indicate (RI) line when it
detects a ring on the phone line. This line is routed to the core logic to generate a wake event. The chipset then wakes
the system and the hardware will eventually pass control back to the OS (the wake mechanism differs depending on
the sleeping state, or LPI). After the OS is running, it puts the device in the D0 state and begins handling interrupts
from the modem to process the event.
3.5 Processor Power Management
To further save power in the Working state, the OS puts the CPU into low-power states (C1, C2, and C3) when the OS
is idle. In these low-power states, the CPU does not run any instructions, and wakes when an interrupt, such as the OS
scheduler’s timer interrupt, occurs.
The OS determines how much time is being spent in its idle loop by reading the ACPI Power Management Timer.
This timer runs at a known, ﬁxed frequency and allows the OS to precisely determine idle time. Depending on this
idle time estimate, the OS will put the CPU into different quality low-power states (which vary in power and latency)
when it enters its idle loop.
The CPU states are deﬁned in detail in Processor Conﬁguration and Control
3.6 Device and Processor Performance States
This section describes the concept of device and processor performance states. Device and processor performance
states (Px states) are power consumption and capability states within the active/executing states, C0 for processors and
D0 for devices. Performance states allow OSPM to make tradeoffs between performance and energy conservation.
Device and processor performance states have the greatest impact when the states invoke different device and processor
transitions occur in the active/executing device states, care must be taken to ensure that performance state transitions
do not adversely impact the system.
Examples of device performance states include:
• A hard drive that provides levels of maximum throughput that correspond to levels of power consumption.
• An LCD panel that supports multiple brightness levels that correspond to levels of power consumption.
• A graphics component that scales performance between 2D and 3D drawing modes that corresponds to levels
of power consumption.
• An audio subsystem that provides multiple levels of maximum volume that correspond to levels of maximum
power consumption.
• A Direct-RDRAMTM controller that provides multiple levels of memory throughput performance, correspond-
ing to multiple levels of power consumption, by adjusting the maximum bandwidth throttles.
Processor performance states are described in Processor Conﬁguration and Control
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3.7 Conﬁguration and “Plug and Play”
In addition to power management, ACPI interfaces provide controls and information that enable OSPM to conﬁgure the
required resources of motherboard devices along with their dynamic insertion and removal. ACPI Deﬁnition Blocks,
including the Differentiated System Description Table (DSDT) and Secondary System Description Tables (SSDTs),
describe motherboard devices in a hierarchical format called the ACPI namespace. The OS enumerates motherboard
devices simply by reading through the ACPI Namespace looking for devices with hardware IDs.
Each device enumerated by ACPI includes ACPI-deﬁned objects in the ACPI Namespace that report the hardware
resources that the device could occupy, an object that reports the resources that are currently used by the device, and
objects for conﬁguring those resources. The information is used by the Plug and Play OS (OSPM) to conﬁgure the
devices.
Note: When preparing to boot a system, the platform boot ﬁrmware only needs to conﬁgure boot devices. This
includes boot devices described in the ACPI system description tables as well as devices that are controlled through
other standards.
3.7.1 Device Conﬁguration Example: Conﬁguring the Modem
Returning to the modem device example above, the OS will ﬁnd the modem and load a driver for it when the OS ﬁnds
it in the DSDT. This table will have control methods that give the OS the following information:
• The device can use IRQ 3, I/O 3F8-3FF or IRQ 4, I/O 2E8-2EF
• The device is currently using IRQ 3, I/O 3F8-3FF
The OS conﬁgures the modem’s hardware resources using Plug and Play algorithms. It chooses one of the supported
conﬁgurations that does not conﬂict with any other devices. Then, OSPM conﬁgures the device for those resources by
running a control method supplied in the modem’s section of the Differentiated Deﬁnition Block. This control method
will write to any I/O ports or memory addresses necessary to conﬁgure the device to the given resources.
3.7.2 NUMA Nodes
Systems employing a Non Uniform Memory Access (NUMA) architecture contain collections of hardware resources
including processors, memory, and I/O buses, that comprise what is commonly known as a “NUMA node”. Processor
accesses to memory or I/O resources within the local NUMA node is generally faster than processor accesses to
memory or I/O resources outside of the local NUMA node. ACPI deﬁnes interfaces that allow the platform to convey
NUMA node topology information to OSPM both statically at boot time and dynamically at run time as resources are
added or removed from the system.
3.8 System Events
ACPI includes a general event model used for Plug and Play, Thermal, and Power Management events. There are two
registers that make up the event model: an event status register and an event enable register.
When an event occurs, the core logic sets a bit in the status register to indicate the event. If the corresponding bit in
the enable register is set, the core logic will assert the SCI to signal the OS. When the OS receives this interrupt, it
will run the control methods corresponding to any bits set in the event status register. These control methods use AML
commands to tell the OS what event occurred.
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For example, assume a machine has all of its Plug and Play, Thermal, and Power Management events connected to
the same pin in the core logic. The event status and event enable registers would only have one bit each: the bit
corresponding to the event pin.
When the system is docked, the core logic sets the status bit and signals the SCI. The OS, seeing the status bit set,
runs the control method for that bit. The control method checks the hardware and determines the event was a docking
event (for example). It then signals to the OS that a docking event has occurred, and can tell the OS speciﬁcally where
in the device hierarchy the new devices will appear.
Since the event model registers are generalized, they can describe many different platform implementations. The single
pin model above is just one example. Another design might have Plug and Play, Thermal, and Power Management
events wired to three different pins so there would be three status bits (and three enable bits). Yet another design might
have every individual event wired to its own pin and status bit. This design, at the opposite extreme from the single pin
design, allows very complex hardware, yet very simple control methods. Countless variations in wiring up events are
possible. However, note that care must be taken to ensure that if events share a signal that the event that generated the
signal can be determined in the corresponding event handling control method allowing the proper device notiﬁcation
to be sent.
3.9 Battery Management
Battery management policy moves from the APM BIOS to the ACPI-compatible OS. Batteries must comply with
the requirements of their associated interfaces, as described either herein or in other applicable standards. The OS
may choose to alter the behavior of the battery, for example, by adjusting the Low Battery or Battery Warning trip
point. When there are multiple batteries present, the battery subsystem is not required to perform any synthesis of a
“composite battery” from the data of the separate batteries. In cases where the battery subsystem does not synthesize
a “composite battery” from the separate battery’s data, the OS must provide that synthesis.
An ACPI-compatible battery device needs either a Smart Battery subsystem interface or a Control Method Battery
• Smart Battery is controlled by the OS directly through the embedded controller (EC). See Section 10.1 and
Section 12.9 for more information.
• Control Method Battery is completely accessed by AML code control methods, allowing the OEM to choose

any type of battery and any kind of communication interface supported by ACPI. See Section 10.2 for more
This section describes concepts common to all battery types.
3.9.1 Battery Communications
Both the Smart Battery and Control Method Battery interfaces provide a mechanism for the OS to query information
from the platform’s battery system. This information may include full charged capacity, present battery capacity, rate
of discharge, and other measures of the battery’s condition. All battery system types must provide notiﬁcation to the
OS when there is a change such as inserting or removing a battery, or when a battery starts or stops discharging. Smart
Batteries and some Control Method Batteries are also able to give notiﬁcations based on changes in capacity. Smart
batteries provide extra information such as estimated run-time, information about how much power the battery is able
to provide, and what the run-time would be at a predetermined rate of consumption.
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3.9.2 Battery Capacity
Each battery must report its designed capacity, latest full-charged capacity, and present remaining capacity. Remaining
capacity decreases during usage, and it also changes depending on the environment. Therefore, the OS must use latest
full-charged capacity to calculate the battery percentage. In addition the battery system must report warning and low
battery levels at which the user must be notiﬁed and the system transitioned to a sleeping state. See Fig. 3.3 for the
relation of these ﬁve values.
A system may use either rate and capacity [mA/mAh] or power and energy [mW/mWh] for the unit of battery infor-
mation calculation and reporting. Mixing [mA] and [mW] is not allowed on a system.
Fig. 3.3: Reporting Battery Capacity
3.9.3 Battery Gas Gauge
At the most basic level, the OS calculates Remaining Battery Percentage [%] using the following formula:
Fig. 3.4: Formula for Remaining Battery Percentage
Control Method Battery also reports the Present Drain Rate [mA or mW] for calculating the remaining battery life. At
the most basic level, Remaining Battery life is calculated by following formula:
Fig. 3.5: Formula for the Present Drain Rate
Smart Batteries also report the present rate of drain, but since they can directly report the estimated run-time, this
function should be used instead as it can more accurately account for variations speciﬁc to the battery.
3.9. Battery Management 39Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
3.9.4 Low Battery Levels
A system has an OEM-designed initial capacity for warning, initial capacity for low, and a critical battery level or ﬂag.
The values for warning and low represent the amount of energy or battery capacity needed by the system to take certain
actions. The critical battery level or ﬂag is used to indicate when the batteries in the system are completely drained.
OSPM can determine independent warning and low battery capacity values based on the OEM-designed levels, but
cannot set these values lower than the OEM-designed values, as shown in the ﬁgure below.
Fig. 3.6: Low Battery and Warning
Each Control Method Battery in a system reports the OEM-designed initial warning capacity and OEM-designed
initial low capacity as well as a ﬂag to report when that battery has reached or is below its critical energy level. Unlike
Control Method Batteries, Smart Batteries are not necessarily speciﬁc to one particular machine type, so the OEM-
designed warning, low, and critical levels are reported separately in a Smart Battery Table described in Smart Battery
Table (SBST) .
The table below describes how these values should be set by the OEM and interpreted by the OS.
Table 3.1: Low Battery Levels
Level Description
Warning When the total available energy (mWh) or capacity (mAh) in the batteries falls below this
level, the OS will notify the user through the UI. This value should allow for a few minutes
of run-time before the “Low” level is encountered so the user has time to wrap up any
important work, change the battery, or ﬁnd a power outlet to plug the system in.
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Table 3.1 – continued from previous page
Low This value is an estimation of the amount of energy or battery capacity required by the
system to transition to any supported sleeping state. When the OS detects that the total
available battery capacity is less than this value, it will transition the system to a user deﬁned
system state (S1-S4). In most situations this should be S4 so that system state is not lost
if the battery eventually becomes completely empty. The design of the OS should consider
that users of a multiple battery system may remove one or more of the batteries in an attempt
replace or charge it. This might result in the remaining capacity falling below the “Low”
level not leaving sufﬁcient battery capacity for the OS to safely transition the system into the
sleeping state. Therefore, if the batteries are discharging simultaneously, the action might
need to be initiated at the point when both batteries reach this level.
Critical The Critical battery state indicates that all available batteries are discharged and do not
appear to be able to supply power to run the system any longer. When this occurs, the OS
must attempt to perform an emergency shutdown as described below.
For a smart battery system, this would typically occur when all batteries reach a capacity of
0, but an OEM may choose to put a larger value in the Smart Battery Table to provide an
extra margin of safely.
For a Control Method Battery system with multiple batteries, the ﬂag is reported per battery.
If any battery in the system is in a critically low state and is still providing power to the
system (in other words, the battery is discharging), the system is considered to be in a
critical energy state. The _BST control method is required to return the Critical ﬂag on a
discharging battery only when all batteries have reached a critical state; the ACPI system
ﬁrmware is otherwise required to switch to a non-critical battery.
3.9.4.1 Emergency Shutdown
Running until all batteries in a system are critical is not a situation that should be encountered normally, since the
system should be put into a sleeping state when the battery becomes low. In the case that this does occur, the OS
should take steps to minimize any damage to system integrity. The emergency shutdown procedure should be designed
to minimize bad effects based on the assumption that power may be lost at any time. For example, if a hard disk is
spun down, the OS should not try to spin it up to write any data, since spinning up the disk and attempting to write data
could potentially corrupt ﬁles if the write were not completed. Even if a disk is spun up, the decision to attempt to save
even system settings data before shutting down would have to be evaluated since reverting to previous settings might
be less harmful than having the potential to corrupt the settings if power was lost halfway through the write operation.
3.9.5 Battery Calibration
The reported capacity of many batteries generally degrade over time, providing less run time for the user. However, it
is possible with many battery systems to provide more usable runtime on an old battery if a calibration or conditioning
cycle is run occasionally. The user has typically been able to perform a calibration cycle either by going into the
platform boot ﬁrmware setup menu, or by running a custom driver and calibration application provided by the OEM.
The calibration process typically takes several hours, and the laptop must be plugged in during this time. Ideally the
application that controls this should make this as good of a user experience as possible, for example allowing the user
to schedule the system to wake up and perform the calibration at some time when the system will not be in use. Since
the calibration user experience does not need to be different from system to system it makes sense for this service to
be provided by the OSPM. In this way OSPM can provide a common experience for end users and eliminate the need
for OEMs to develop custom battery calibration software.
In order for OSPM to perform generic battery calibration, generic interfaces to control the two basic calibration
functions are required. These functions are deﬁned in Power Source and Power Meter Devices and_BST (Battery
Status) . First, there is a means to detect when it would be beneﬁcial to calibrate the battery. Second there is a means to
perform that calibration cycle. Both of those functions may be implemented by dedicated hardware such as a battery
controller chip, by ﬁrmware in the embedded controller, by the platform ﬁrmware, or by OSPM. From here on any
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function implemented through AML, whether or not the AML code relies on hardware, will be referred to as “AML
controlled” since the interface is the same whether the AML passes control to the hardware or not.
Detection of when calibration is necessary can be implemented by hardware or AML code and be reported through
the _BMD method. Alternately, the _BMD method may simply report the number of cycles before calibration should
be performed and let the OS attempt to count the cycles. A counter implemented by the hardware or the platform
ﬁrmware will generally be more accurate since the batteries can be used without the OS running, but in some cases, a
system designer may opt to simplify the hardware or ﬁrmware implementation.
When calibration is desirable and the user has scheduled the calibration to occur, the calibration cycle can be AML
controlled or OSPM controlled. OSPM can only implement a very simple algorithm since it doesn’t have knowledge
of the speciﬁcs of the battery system. It will simply discharge the battery until it quits discharging, then charge it until
it quits charging. In the case where the AC adapter cannot be controlled through the _BMC, it will prompt the user
to unplug the AC adapter and reattach it after the system powers off. If the calibration cycle is controlled by AML,
the OS will initiate the calibration cycle by calling _BMC. That method will either give control to the hardware, or
will control the calibration cycle itself. If the control of the calibration cycle is implemented entirely in AML code,
the platform runtime ﬁrmware may avoid continuously running AML code by having the initial call to _BMC start the
cycle, set some state ﬂags, and then exit. Control of later parts of the cycle can be accomplished by putting code that
checks these state ﬂags in the battery event handler (_Qxx, _Lxx, or _Exx).
Details of the control methods for this interface are deﬁned in Control Method Batteries .
3.9.6 Battery Charge Limiting
If the Platform is said to support Battery Charge Limiting feature, it must:
1. Advertise true charge level to the OSPM, at all times for all installed batteries
2. Limit the battery from reaching its Full Charge Capacity when Battery Charge Limiting is active
3. Set _BST.Battery State.Bit[3] when Battery Charge Limiting is active
4. Ensure that _BST.Battery State (Bit 0 and Bit 1) reﬂect true charging/discharging state of the battery
OSPM must recognize the following settings:
Table 3.2: Battery Charge Limiting States
_BST.Battery
State.Bit[3]_BST.Battery
State.Bit[0]_BST.Battery
State.Bit[1]Interpretation
Cleared N/A N/A Battery Charge Limiting is disengaged
Set Cleared Cleared Battery Charge Limiting is engaged, and the battery has
reached the steady state, it will not be charged or discharged
Set Cleared Set Battery Charge Limiting is engaged, and the battery has not
reached the steady state
Set Set Cleared Battery Charge Limiting is engaged, and the battery has not
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3.10 Thermal Management Concepts
ACPI allows the OS to play a role in the thermal management of the system while maintaining the platform’s ability
to mandate cooling actions as necessary. In the passive cooling mode, OSPM can make cooling decisions based on
application load on the CPU as well as the thermal heuristics of the system. OSPM can also gracefully shutdown the
computer in case of high temperature emergencies.
The ACPI thermal design is based around regions called thermal zones. Generally, the entire PC is one large thermal
zone, but an OEM can partition the system into several logical thermal zones if necessary. Thermal Zone is an example
mobile PC diagram that depicts a single thermal zone with a central processor as the thermal-coupled device. In this
example, the whole notebook is covered as one large thermal zone. This notebook uses one fan for active cooling and
the CPU for passive cooling.
Fig. 3.7: Thermal Zone
The following sections are an overview of the thermal control and cooling characteristics of a computer. For some
thermal implementation examples on an ACPI platform, see Section 11.6
3.10.1 Active and Passive Cooling Modes
ACPI deﬁnes two cooling modes, Active and Passive:
Passive cooling OS reduces the power consumption of devices at the cost of system performance to reduce the tem-
perature of the system.
Active cooling OS increases the power consumption of the system (for example, by turning on a fan) to reduce the
temperature of the system.
These two cooling modes are inversely related to each other. Active cooling requires increased power to reduce the
heat within the system while Passive cooling requires reduced power to decrease the temperature. The effect of this
relationship is that Active cooling allows maximum system performance, but it may create undesirable fan noise, while
Passive cooling reduces system performance, but is inherently quiet.
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3.10.2 Performance vs. Energy Conservation
A robust OSPM implementation provides the means for the end user to convey to OSPM a preference (or a level of
preference) for either performance or energy conservation. Allowing the end user to choose this preference is most
critical to mobile system users where maximizing system run-time on a battery charge often has higher priority over
realizing maximum system performance.
A user’s preference for performance corresponds to the Active cooling mode while a user’s preference for energy
conservation corresponds to the Passive cooling mode. ACPI deﬁnes an interface to convey the cooling mode to
the platform. Active cooling can be performed with minimal OSPM thermal policy intervention. For example, the
platform indicates through thermal zone parameters that crossing a thermal trip point requires a fan to be turned on.
Passive cooling requires OSPM thermal policy to manipulate device interfaces that reduce performance to reduce
thermal zone temperature.
3.10.3 Acoustics (Noise)
Active cooling mode generally implies that fans will be used to cool the system and fans vary in their audible output.
Fan noise can be quite undesirable given the loudness of the fan and the ambient noise environment. In this case,
the end user’s physical requirement for fan silence may override the preference for either performance or energy
conservation.
A user’s desire for fan silence corresponds to the Passive cooling mode. Accordingly, a user’s desire for fan silence
also means a preference for energy conservation.
For more information on thermal management and examples of platform settings for active and passive cooling, see
Section 3.10
3.10.4 Multiple Thermal Zones
The basic thermal management model deﬁnes one thermal zone, but in order to provide extended thermal control in
a complex system, ACPI speciﬁes a multiple thermal zone implementation. Under a multiple thermal zone model,
OSPM will independently manage several thermal-coupled devices and a designated thermal zone for each thermal-
coupled device, using Active and/or Passive cooling methods available to each thermal zone. Each thermal zone can
have more than one Passive and Active cooling device. Furthermore, each zone might have unique or shared cooling
resources. In a multiple thermal zone conﬁguration, if one zone reaches a critical state then OSPM must shut down
the entire system.
3.11 Flexible Platform Architecture Support
ACPI deﬁnes mechanisms and models to accommodate platform architectures that deviate from the traditional PC.
ACPI provides support for platform technologies that enable lower-power, lower cost, more design ﬂexibility and
more device diversity. This support is described in the following sections, and detailed in later chapters.
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3.11.1 Hardware-reduced ACPI
ACPI offers an alternative platform interface model that removes ACPI hardware requirements for platforms that do
not implement the PC Architecture. In the Hardware-reduced ACPI model, the Fixed hardware interface requirements
of Chapter 4 are removed, and Generic hardware interfaces are used instead. This provides the level of ﬂexibility
needed to innovate and differentiate in low-power hardware designs while enabling support by multiple Operating
Systems.
Hardware-reduced ACPI has the following requirements:
• UEFI ﬁrmware interface for boot (Legacy BIOS is not supported).
• Boot in ACPI mode only (ACPI Enable, ACPI Disable, SMI_CMD and Legacy mode are not supported)
• No hardware resource sharing between OSPM and other asynchronous operating environments, such as UEFI
Runtime Services or System Management Mode. (The Global Lock is not supported)
• No dependence on OS-support for maintaining cache coherency across processor sleep states (Bus Master

Systems.
Reload and Arbiter Disable are not supported)
• GPE block devices are not supported
Systems that do not meet the above requirements must implement the ACPI Fixed Hardware interface.
3.11.1.1 Interrupt-based Wake Events
On HW-reduced ACPI platforms, wakeup is an attribute of connected interrupts. Interrupts that are designed to wake
the processor or the entire platform are deﬁned as wake-capable. Wake-capable interrupts, when enabled by OSPM,
wake the system when they assert.
3.11.2 Low-Power Idle
Platform architectures may support hardware power management models other than the traditional ACPI
Sleep/Resume model. These are typically implemented in proprietary hardware and are capable of delivering low-
latency, connected idle while saving as much energy as ACPI Sleep states. To support the diversity of hardware
implementations, ACPI provides a mechanism for the platform to indicate to OSPM that such capability is available.
3.11.2.1 Low Power S0 Idle Capable Flag
This ﬂag in the FADT informs OSPM whether a platform has advanced idle power capabilities such that S0 idle
achieves savings similar to or better than those typically achieved in S3. With this ﬂag, OSPM can keep the system
in S0 idle for its low-latency response and its connectedness rather than transitioning to a system sleep state which
has neither. The ﬂag enables support for a diversity of platform implementations: traditional Sleep/Resume systems,
systems with advanced idle power, systems that support neither, and systems that can support both, depending on the
capabilities of the installed OS.
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3.11.3 Connection Resources
General-purpose I/O (GPIO) and Simple Peripheral Bus (SPB) controllers are hardware resources provided in silicon
solutions to enable ﬂexible conﬁguration of a broad range of system designs. These controllers can provide input,
output, interrupt and serial communication connections to arbitrary devices in a system. The function to which one
of these connections is put depends on the speciﬁc device involved and the needs of the platform design. In order to
support these platform technologies, ACPI deﬁnes a general abstraction for ﬂexible connections.
In order to maintain compatibility with existing software models, ACPI abstracts these connections as hardware re-
sources.
The Connection Resource abstraction mirrors the hardware functionality of GPIO and SPB controllers. Like other
resources, these connections are allocated and conﬁgured before use. With the resources described by the platform,
OSPM abstracts the underlying conﬁguration from device drivers. Drivers, then, can be written for the device’s
function only, and reused with that functional hardware regardless of how it is integrated into a given system.
The key aspects of the Connection Resource abstraction are:
• GPIO and SPB controllers are enumerated as devices in the ACPI Namespace.
• GPIO Connection and SPB Connection resource types are deﬁned.
• Namespace devices that are connected to GPIO or SPB controllers use Resource Template Macros to add Con-
nection Resources to their resource methods (_CRS, _SRS, etc.).
• GPIO Connection Resources can be designated by the platform for use as GPIO-signaled ACPI Events .
• Connection Resources can be used by AML methods to access pins and peripherals through GPIO and SPB
operation regions.
3.11.3.1 Supported Platforms
The HW-reduced ACPI and Low power S0 Idle Capable ﬂags combine to represent 4 platform types that can be
implemented. The following table enumerates these, as well as the intended OSPM behavior and speciﬁc platform
requirements.
Table 3.3: Implementable Platform Types
Low Power
S0 Idle
CapableHardware-
reduced
ACPIOSPM Behavior Platform Implementation
0 0 Fixed hardware interface accessed for
features, events and system power
management. Optionally accesses
GPIO-signaled ACPI events if im-
plemented in ACPI FW. Traditional
Sleep/Resume power management.Implement Fixed-feature hardware
interface. Optionally implements
GPIO-signaled ACPI events.
0 1 Fixed-feature hardware interface not
accessed. Sleep/Resume Power Man-
agement using FADT SLEEP_*_REG
ﬁelds and Interrupt-based wake sig-
naling.Implement GPIO-signaled ACPI
Events; Implement software alter-
natives to any ACPI ﬁxed features,
including the Sleep registers. Im-
plement wake-capable interrupts for
wake events.
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1 0 Fixed hardware interface accessed
for features and events. Platform-
speciﬁc Low-power Idle power man-
agement. Optionally accesses GPIO-
signaled ACPI events if implemented
in ACPI FW.Implement Fixed-feature hardware
GPIO-signaled ACPI events. Imple-
ment low-power hardware such that
the platform achieves power savings
in S0 similar to or better than those
typically achieved in S3.
1 1 Fixed-feature hardware interface not
accessed. Platform-speciﬁc Low-
power Idle power management.Implement GPIO-signaled ACPI
Events ; Implement software alter-
natives to any ACPI ﬁxed features
desired; Implement wake-capable
interrupts for any wake events. Imple-
3.11. Flexible Platform Architecture Support 47CHAPTER
FOUR
ACPI HARDWARE SPECIFICATION
ACPI deﬁnes standard interface mechanisms that allow an ACPI-compatible OS to control and communicate with
an ACPI-compatible hardware platform. These interface mechanisms are optional (See “Hardware-Reduced ACPI”,
below).However, if the ACPI Hardware Speciﬁcation is implemented, platforms must comply with the requirements
in this section.
This section describes the hardware aspects of ACPI.
ACPI deﬁnes “hardware” as a programming model and its behavior. ACPI strives to keep much of the existing
legacy programming model the same; however, to meet certain feature goals, designated features conform to a speciﬁc
addressing and programming scheme. Hardware that falls within this category is referred to as “ﬁxed.”
Although ACPI strives to minimize these changes, hardware engineers should read this section carefully to understand
the changes needed to convert a legacy-only hardware model to an ACPI/Legacy hardware model or an ACPI-only
hardware model.
ACPI classiﬁes hardware into two categories: Fixed or Generic. Hardware that falls within the ﬁxed category meets
the programming and behavior speciﬁcations of ACPI. Hardware that falls within the generic category has a wide
degree of ﬂexibility in its implementation.
4.1 Hardware-Reduced ACPI
For certain classes of systems the ACPI Hardware Speciﬁcation may not be adequate. Examples include legacy-
free, UEFI-based platforms with recent processors, and those implementing mobile platform architectures. For such
platforms, a Hardware-reduced ACPI mode is deﬁned. Under this deﬁnition, the ACPI Fixed Hardware interface is
not implemented, and software alternatives for many of the features it supports are used instead. Note, though, that
Hardware-reduced ACPI is not intended to support every possible ACPI system that can be built today. Rather, it is
intended to introduce new systems that are designed to be HW-reduced from the start. The ACPI HW Speciﬁcation
should be used if the platform cannot be designed to work without it. Speciﬁcally, the following features are not
supported under the HW-reduced deﬁnition:
• The Global Lock, SMI_CMD, ACPI Enable and ACPI Disable. Hardware-reduced ACPI systems always boot
in ACPI mode, and do not support hardware resource sharing between OSPM and other asynchronous operating
environments, such as UEFI Runtime Services or System Management Mode.
• Bus Master Reload and Arbiter Disable. Systems that depend on OS use of these bits to maintain cache co-
herency across processor sleep states are not supported.
• GPE block devices are not supported.
Platforms that require the above features must implement the ACPI Hardware Speciﬁcation.
Platforms that are designed for the Hardware-reduced ACPI deﬁnition must implement Revision 5 or greater of the
Fixed ACPI Descriptor Table, and must set the HW_REDUCED_ACPI ﬂag in the Flags ﬁeld.
48Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Note: FFH is permitted and applicable to both full and HW-reduced ACPI implementations.
4.1.1 Hardware-Reduced Events
HW-reduced ACPI platforms require alternatives to some of the features supported in the ACPI HW Speciﬁcation,
where none already exists. There are two areas that require such alternatives: The ACPI Platform Event Model, and
System and Device Wakeup.
4.1.1.1 GPIO-Signaled Events or Interrupt Signaled Events

General Purpose Input/Output (GPIO) hardware can be used for signaling platform events. GPIO HW is a general-
ization of the GPE model, and is a shared hardware resource used for many applications. ACPI support for GPIO is
described in section Connection Resources . ACPI 6.1 introduces the capability to signal events via interrupts. See
Interrupt-signaled ACPI events for further details.
GPIO based event signaling is provided through GPIO interrupt connections, which describe the connection to a GPIO
controller and pin, and which are mapped to the ACPI Event Handling mechanism via the ACPI Event Information
namespace object (_AEI). OSPM treats GPIO Interrupt Connections listed in _AEI exactly as it does SCI interrupts:
it executes the Event Method associated with the speciﬁc event. The name of the method to run is determined by the
pin information contained in the GPIO Interrupt Connection resource. See GPIO-signaled ACPI Events for further
details.
GPIO-signaled events can also be wake events, just as GPE events can on traditional ACPI platforms. Designating
which events are wake events is done through attributes of the GPIO Interrupt Connection resource used.Devices may
use _PRW to manage wake events as described in _PRW (Power Resources for Wake) .
Interrupt based event signaling follows a similar methodology, a generic event device (GED) is declared which in turn
describes all interrupts associated with event generation. The interrupts are listed in a _CRS object. When an interrupt
is asserted the OSPM will execute the event method (_EVT) declared in the GED object specifying the interrupt
identiﬁer as a parameter. In this way the interrupt can be associated with speciﬁc platform events.
4.1.1.2 Interrupt-based Wake Events
Wake events on HW-reduced ACPI platforms are always caused by an interrupt reaching the processor. Therefore,
there are two requirements for waking the system from a sleep or low-power idle state, or a device from a low-power
state. First, the interrupt line must be Wake-Capable. Wake-capable interrupts are designed to be able to be delivered
to the processor from low-power states. This implies that it must also cause the processor and any required platform
hardware to power-up so that an Interrupt Service Routine can run. Secondly, an OS driver must enable the interrupt
before entering a low-power state, or before OSPM puts the system into a sleep or low-power idle state.
Wake-capable interrupts are designated as such in their Extended Interrupt or GPIO Interrupt Connection resource
descriptor.
4.2 Fixed Hardware Programming Model
Because of the changes needed for migrating legacy hardware to the ﬁxed category, ACPI limits the features speciﬁed
by ﬁxed hardware. Fixed hardware features are deﬁned by the following criteria:
• Performance sensitive features
• Features that drivers require during wake
• Features that enable catastrophic OS software failure recovery
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ACPI deﬁnes register-based interfaces to ﬁxed hardware. CPU clock control and the power management timer are
deﬁned as ﬁxed hardware to reduce the performance impact of accessing this hardware, which will result in more
quickly reducing a thermal condition or extending battery life. If this logic were allowed to reside in PCI conﬁguration
space, for example, several layers of drivers would be called to access this address space. This takes a long time and
will either adversely affect the power of the system (when trying to enter a low-power state) or the accuracy of the
event (when trying to get a time stamp value).
Access to ﬁxed hardware by OSPM allows OSPM to control the wake process without having to load the entire OS.
For example, if PCI conﬁguration space access is needed, the bus enumerator is loaded with all drivers used by the
enumerator. Deﬁning these interfaces in ﬁxed hardware at addresses with which OSPM can communicate without any
other driver’s assistance, allows OSPM to gather information prior to making a decision as to whether it continues
loading the entire OS or puts it back to sleep.
If elements of the OS fail, it may be possible for OSPM to access address spaces that need no driver support. In such
a situation, OSPM will attempt to honor ﬁxed power button requests to transition the system to the G2 state. In the
case where OSPM event handler is no longer able to respond to power button events, the power button override feature
provides a back-up mechanism to unconditionally transition the system to the soft-off state.
4.3 Generic Hardware Programming Model
Although the ﬁxed hardware programming model requires hardware registers to be deﬁned at speciﬁc address lo-
cations, the generic hardware programming model allows hardware registers to reside in most address spaces and
provides system OEMs with a wide degree of ﬂexibility in the implementation of speciﬁc functions in hardware.
OSPM directly accesses the ﬁxed hardware registers, but relies on OEM-provided ACPI Machine Language (AML)
code to access generic hardware registers.
AML code allows the OEM to provide the means for OSPM to control a generic hardware feature’s control and event
logic.
The section entitled “ACPI Source Language Reference” describes the ACPI Source Language (ASL)–a programming
language that OEMs use to create AML. The ASL language provides many of the operators found in common object-
oriented programming languages, but it has been optimized to enable the description of platform power management
and conﬁguration hardware. An ASL compiler converts ASL source code to AML, which is a very compact machine
language that the ACPI AML code interpreter executes.
AML does two things:
• Abstracts the hardware from OSPM
• Buffers OEM code from the different OS implementations
One goal of ACPI is to allow the OEM “value added” hardware to remain basically unchanged in an ACPI conﬁgu-
ration. One attribute of value-added hardware is that it is all implemented differently. To enable OSPM to execute
properly on different types of value added hardware, ACPI deﬁnes higher level “control methods” that it calls to per-
form an action. The OEM provides AML code, which is associated with control methods, to be executed by OSPM.
By providing AML code, generic hardware can take on almost any form.
Another important goal of ACPI is to provide OS independence. To do this, the OEM AML code has to execute the
same under any ACPI-compatible OS. ACPI allows for this by making the AML code interpreter part of OSPM. This
allows OSPM to take care of synchronizing and blocking issues speciﬁc to each particular OS.
The generic feature model is represented in the following block diagram. In this model the generic feature is described
to OSPM through AML code. This description takes the form of an object that sits in the ACPI Namespace associated
with the hardware to which it is adding value.
As an example of a generic hardware control feature, a platform might be designed such that the IDE HDD’s D3 state
has value-added hardware to remove power from the drive. The IDE drive would then have a reference to the AML
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Fig. 4.1: Generic Hardware Feature Model
PowerResource object (which controls the value added power plane) in its namespace, and associated with that object
would be control methods that OSPM invokes to control the D3 state of the drive:
• _PS0: A control method to sequence the IDE drive to the D0 state.
• _PS3: A control method to sequence the IDE drive to the D3 state.
• _PSC: A control method that returns the status of the IDE drive (on or off).
The control methods under this object provide an abstraction layer between OSPM and the hardware. OSPM under-
stands how to control power planes (turn them on or off or to get their status) through its deﬁned PowerResource
object, while the hardware has platform-speciﬁc AML code (contained in the appropriate control methods) to perform
the desired function. In this example, the platform would describe its hardware to the ACPI OS by writing and placing
the AML code to turn the hardware off within the _PS3 control method. This enables the following sequence:
When OSPM decides to place the IDE drive in the D3 state, it calls the IDE driver and tells it to place the drive into
the D3 state (at which point the driver saves the device’s context).
When the IDE driver returns control, OSPM places the drive in the D3 state.
OSPM ﬁnds the object associated with the HDD and then ﬁnds within that object any AML code associated with the
D3 state.
OSPM executes the appropriate _PS3 control method to control the value-added “generic” hardware to place the HDD
into an even lower power state.
As an example of a generic event feature, a platform might have a docking capability. In this case, it will want

D3 state.
to generate an event. Notice that all ACPI events generate an SCI, which can be mapped to any shareable system
interrupt. In the case of docking, the event is generated when a docking has been detected or when the user requests
to undock the system. This enables the following sequence:
OSPM responds to the SCI and calls the AML code event handler associated with that generic event. The ACPI table
associates the hardware event with the AML code event handler.
The AML-code event handler collects the appropriate information and then executes an AML Notify command to
indicate to OSPM that a particular bus needs re-enumeration.
The following sections describe the ﬁxed and generic hardware feature set of ACPI. These sections enable a reader to
understand the following:
• Which hardware registers are required or optional when an ACPI feature, concept or interface is required by a
design guide for a platform class
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• How to design ﬁxed hardware features
• How to design generic hardware features
• The ACPI Event Model
4.4 Diagram Legend
The hardware section uses simpliﬁed logic diagrams to represent how certain aspects of the hardware are implemented.
The following symbols are used in the logic diagrams to represent programming bits:
Write-only control bit
Enable, control, or status bit
Sticky status bit
Query value
The half round symbol with an inverted “V” represents a write-only control bit. This bit has the behavior that it
generates its control function when it is set. Reads to write-only bits are treated as ignore by software (the bit position
is masked off and ignored).
The round symbol with an “X” represents a programming bit. As an enable or control bit, software setting or clearing
this bit will result in the bit being read as set or clear (unless otherwise noted). As a status bit it directly represents the
value of the signal.
The square symbol represents a sticky status bit. A sticky status bit is set by the level (not edge) of a hardware signal
(active high or active low). The bit is only cleared by software writing a “1” to its bit position.
The rectangular symbol represents a query value from the embedded controller. This is the value the embedded
controller returns to the system software upon a query command in response to an SCI event. The query value is
associated with the event control method that is scheduled to execute upon an embedded controller event.
4.5 Register Bit Notation
Throughout this section there are logic diagrams that reference bits within registers. These diagrams use a notation
that easily references the register name and bit position. The notation is as follows:
Registername.Bit
Registername contains the name of the register as it appears in this speciﬁcation
Bitcontains a zero-based decimal value of the bit position
For example, the SLP_EN bit resides in the PM1x_CNT register bit 13 and would be represented in diagram notation
as:
SLP_EN
PM1x_CNT.13
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4.6 The ACPI Hardware Model
The ACPI hardware model is deﬁned to allow OSPM to sequence the platform between the various global system
states (G0-G3) as illustrated in the following ﬁgure by manipulating the deﬁned interfaces. When ﬁrst powered on,
the platform ﬁnds itself in the global system state G3 or “Mechanical Off.” This state is deﬁned as one where power
consumption is very close to zero–the power plug has been removed; however, the real-time clock device still runs off
a battery. The G3 state is entered by any power failure, deﬁned as accidental or user-initiated power loss.
The G3 state transitions into either the G0 working state or the Legacy state depending on what the platform supports.
If the platform is an ACPI-only platform, then it allows a direct boot into the G0 working state by always returning
the status bit SCI_EN set (1) (for more information, see Legacy/ACPI Select and the SCI Interrupt ). If the platform
supports both legacy and ACPI operations (which is necessary for supporting a non-ACPI OS), then it would always
boot into the Legacy state (illustrated by returning the SCI_EN clear (0)). In either case, a transition out of the G3
state requires a total boot of OSPM.
The Legacy system state is the global state where a non-ACPI OS executes. This state can be entered from either the G3
“Mechanical Off,” the G2 “Soft Off,” or the G0 “Working” states only if the hardware supports both Legacy and ACPI
modes. In the Legacy state, the ACPI event model is disabled (no SCIs are generated) and the hardware uses legacy
power management and conﬁguration mechanisms. While in the Legacy state, an ACPI-compliant OS can request a
transition into the G0 working state by performing an ACPI mode request. OSPM performs this transition by writing
the ACPI_ENABLE value to the SMI_CMD, which generates an event to the hardware to transition the platform into
ACPI mode. When hardware has ﬁnished the transition, it sets the SCI_EN bit and returns control back to OSPM.
While in the G0 “working state,” OSPM can request a transition to Legacy mode by writing the ACPI_DISABLE
value to the SMI_CMD register, which results in the hardware going into legacy mode and resetting the SCI_EN bit
LOW (for more information, see Legacy/ACPI Select and the SCI Interrupt ).
The G0 “Working” state is the normal operating environment of an ACPI system. In this state different devices
are dynamically transitioning between their respective power states (D0, D1, D2, D3hot, or D3) and processors are
dynamically transitioning between their respective power states (C0, C1, C2 or C3). In this state, OSPM can make a
policy decision to place the platform into the system G1 “sleeping” state. The platform can only enter a single sleeping
state at a time (referred to as the global G1 state); however, the hardware can provide up to four system sleeping states
that have different power and exit latencies represented by the S1, S2, S3, or S4 states. When OSPM decides to enter a
sleeping state it picks the most appropriate sleeping state supported by the hardware (OS policy examines what devices
have enabled wake events and what sleeping states these support). OSPM initiates the sleeping transition by enabling
the appropriate wake events and then programming the SLP_TYPx ﬁeld with the desired sleeping state and then setting
the SLP_ENx bit. The system will then enter a sleeping state; when one of the enabled wake events occurs, it will
transition the system back to the working state (for more information, see Waking and Sleeping ).
Another global state transition option while in the G0 “working” state is to enter the G2 “soft off” or the G3 “me-
chanical off” state. These transitions represent a controlled transition that allows OSPM to bring the system down
in an orderly fashion (unloading applications, closing ﬁles, and so on). The policy for these types of transitions can
be associated with the ACPI power button, which when pressed generates an event to the power button driver. When
OSPM is ﬁnished preparing the operating environment for a power loss, it will either generate a pop-up message to
indicate to the user to remove power, in order to enter the G3 “Mechanical Off” state, or it will initiate a G2 “soft-off”
transition by writing the value of the S5 “soft off” system state to the SLP_TYPx register and setting the SLP_EN bit.
The G1 sleeping state is represented by four possible sleeping states that the hardware can support. Each sleeping state
has different power and wake latency characteristics. The sleeping state differs from the working state in that the user’s
operating environment is frozen in a low-power state until awakened by an enabled wake event. No work is performed
in this state, that is, the processors are not executing instructions. Each system sleeping state has requirements about
who is responsible for system context and wake sequences (for more information, see Waking and Sleeping ).
The G2 “soft off” state is an OS initiated system shutdown. This state is initiated similar to the sleeping state transition
(SLP_TYPx is set to the S5 value and setting the SLP_EN bit initiates the sequence). Exiting the G2 soft-off state
requires rebooting the system. In this case, an ACPI-only system will re-enter the G0 state directly (hardware returns
the SCI_EN bit set), while an ACPI/Legacy system transitions to the Legacy state (SCI_EN bit is clear).
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Fig. 4.2: Global States and Their Transitions
The ACPI architecture deﬁnes mechanisms for hardware to generate events and control logic to implement this behav-
ior model. Events are used to notify OSPM that some action is needed, and control logic is used by OSPM to cause

some state transition. ACPI-deﬁned events are “hardware” or “interrupt” events. A hardware event is one that causes
the hardware to unconditionally perform some operation. For example, any wake event will sequence the system from
a sleeping state (S1, S2, S3, and S4 in the global G1 state) to the G0 working state (see Example Sleeping States ).
An interrupt event causes the execution of an event handler (AML code or an ACPI-aware driver), which allows the
software to make a policy decision based on the event. For ACPI ﬁxed-feature events, OSPM or an ACPI-aware driver
acts as the event handler. For generic logic events OSPM will schedule the execution of an OEM-supplied AML
control method associated with the event.
For legacy systems, an event normally generates an OS-transparent interrupt, such as a System Management Interrupt,
or SMI. For ACPI systems the interrupt events need to generate an OS-visible interrupt that is shareable; edge-style
interrupts will not work. Hardware platforms that want to support both legacy operating systems and ACPI systems
support a way of re-mapping the interrupt events between SMIs and SCIs when switching between ACPI and legacy
models. This is illustrated in the following block diagram.
This example logic illustrates the event model for a sample platform that supports both legacy and ACPI event models.
This example platform supports a number of external events that are power-related (power button, LID open/close,
thermal, ring indicate) or Plug and Play-related (dock, status change). The logic represents the three different types of
events:
OS Transparent Events
These events represent OEM-speciﬁc functions that have no OS support and use software that can be
operated in an OS-transparent fashion (that is, SMIs).
Interrupt Events
These events represent features supported by ACPI-compatible operating systems, but are not supported
by legacy operating systems. When a legacy OS is loaded, these events are mapped to the transparent
interrupt (SMI# in this example), and when in ACPI mode they are mapped to an OS-visible shareable
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Fig. 4.3: Example Event Structure for a Legacy/ACPI Compatible Event Model
interrupt (SCI#). This logic is represented by routing the event logic through the decoder that routes the
events to the SMI# arbiter when the SCI_EN bit is cleared, or to the SCI# arbiter when the SCI_EN bit is
set.
Hardware events
These events are used to trigger the hardware to initiate some hardware sequence such as waking, resetting,
or putting the system to sleep unconditionally.
In this example, the legacy power management event logic is used to determine device/system activity or idleness
based on device idle timers, device traps, and the global standby timer. Legacy power management models use the idle
timers to determine when a device should be placed in a low-power state because it is idle–that is, the device has not
been accessed for the programmed amount of time. The device traps are used to indicate when a device in a low-power
state is being accessed by OSPM. The global standby timer is used to determine when the system should be allowed
to go into a sleeping state because it is idle–that is, the user interface has not been used for the programmed amount of
time.
These legacy idle timers, trap monitors, and global standby timer are not used by OSPM in the ACPI mode. This work
is handled by different software structures in an ACPI-compatible OS. For example, the driver model of an ACPI-
compatible OS is responsible for placing its device into a low-power state (D1, D2, D3hot, or D3) and transitioning it
back to the On state (D0) when needed. And OSPM is responsible for determining when the system is idle by proﬁling
the system (using the PM Timer) and other knowledge it gains through its operating structure environment (which will
vary from OS to OS). When the system is placed into the ACPI mode, these events no longer generate SMIs, as OSPM
handles this function. These events are disabled through some OEM-proprietary method.
On the other hand, many of the hardware events are shared between the ACPI and legacy models (docking, the power
button, and so on) and this type of interrupt event changes to an SCI event when enabled for ACPI. The ACPI OS will
generate a request to the platform runtime ﬁrmware to enter into the ACPI mode. The ﬁrmware sets the SCI_EN bit
to indicate that the system has successfully entered into the ACPI mode, so this is a convenient mechanism to map the
desired interrupt (SMI or SCI) for these events (as shown in Figure 4-3).
The ACPI architecture speciﬁes some dedicated hardware not found in the legacy hardware model: the power manage-
ment timer (PM Timer). This is a free running timer that the ACPI OS uses to proﬁle system activity. The frequency
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of this timer is explicitly deﬁned in this speciﬁcation and must be implemented as described.
Although the ACPI architecture reuses most legacy hardware as is, it does place restrictions on where and how the
programming model is generated. If used, all ﬁxed hardware features are implemented as described in this speciﬁcation
so that OSPM can directly access the ﬁxed hardware feature registers.
Generic hardware features are manipulated by ACPI control methods residing in the ACPI Namespace. These inter-
faces can be very ﬂexible; however, their use is limited by the deﬁned ACPI control methods (for more information,
seeACPI-Deﬁned Devices and Device-Speciﬁc Objects ). Generic hardware usually controls power planes, buffer
isolation, and device reset resources. Additionally, “child” interrupt status bits can be accessed via generic hardware
interfaces; however, they have a “parent” interrupt status bit in the GP_STS register. ACPI deﬁnes eight address spaces
that may be accessed by generic hardware implementations. These include:
• System I/O space
• System memory space
• PCI conﬁguration space
• Embedded controller space
• System Management Bus (SMBus) space
• CMOS
• PCI BAR Target
• IPMI space
• Platform Communication Channel
Generic hardware power management features can be implemented accessing spare I/O ports residing in any of these
address spaces. The ACPI speciﬁcation deﬁnes an optional embedded controller and SMBus interfaces needed to
communicate with these associated address spaces.
4.6.1 Hardware Reserved Bits
ACPI hardware registers are designed such that reserved bits always return zero, and data writes to them have no side
affects. OSPM implementations must write zeros to reserved bits in enable and status registers and preserve bits in
control registers, and they will treat these bits as ignored.
4.6.2 Hardware Ignored Bits
ACPI hardware registers are designed such that ignored bits are undeﬁned and are ignored by software. Hardware-
ignored bits can return zero or one. When software reads a register with ignored bits, it masks off ignored bits prior to
operating on the result. When software writes to a register with ignored bit ﬁelds, it preserves the ignored bit ﬁelds.
4.6.3 Hardware Write-Only Bits
ACPI hardware deﬁnes a number of write-only control bits. These bits are activated by software writing a 1 to their
bit position. Reads to write-only bit positions generate undeﬁned results. Upon reads to registers with write-only bits,
software masks out all write-only bits.
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4.6.4 Cross Device Dependencies
Cross Device Dependency is a condition in which an operation to a device interferes with the operation of other
unrelated devices, or allows other unrelated devices to interfere with its behavior. This condition is not supportable
and can cause platform failures. ACPI provides no support for cross device dependencies and suggests that devices be
designed to not exhibit this behavior. The following two examples describe cross device dependencies:
4.6.4.1 Example 1: Related Device Interference
This example illustrates a cross device dependency where a device interferes with the proper operation of other unre-
lated devices. Device A has a dependency that when it is being conﬁgured it blocks all accesses that would normally
be targeted for Device B. Thus, the device driver for Device B cannot access Device B while Device A is being con-
ﬁgured; therefore, it would need to synchronize access with the driver for Device A. High performance, multithreaded
operating systems cannot perform this kind of synchronization without seriously impacting performance.
To further illustrate the point, assume that Device A is a serial port and Device B is a hard drive controller. If these
devices demonstrate this behavior, then when a software driver conﬁgures the serial port, accesses to the hard drive

need to block. This can only be done if the hard disk driver synchronizes access to the disk controller with the serial
driver. Without this synchronization, hard drive data will be lost when the serial port is being conﬁgured.
4.6.4.2 Example 2: Unrelated Device Interference
This example illustrates a cross-device dependency where a device demonstrates a behavior that allows other unrelated
devices to interfere with its proper operation. Device A exhibits a programming behavior that requires atomic back-
to-back write accesses to successfully write to its registers; if any other platform access is able to break between the
back-to-back accesses, then the write to Device A is unsuccessful. If the Device A driver is unable to generate atomic
back-to-back accesses to its device, then it relies on software to synchronize accesses to its device with every other
driver in the system; then a device cross dependency is created and the platform is prone to Device A failure.
4.7 ACPI Hardware Features
This section describes the different hardware features deﬁned by the ACPI interface. These features are categorized as
• Fixed Hardware Features
• Generic Hardware Features
Fixed hardware features reside in a number of the ACPI-deﬁned address spaces at the locations described by the ACPI
programming model. Generic hardware features reside in one of four address spaces (system I/O, system memory,
PCI conﬁguration, embedded controller, or serial device I/O space) and are described by the ACPI Namespace through
the declaration of AML control methods.
Fixed hardware features have exact deﬁnitions for their implementation. Although many ﬁxed hardware features
are optional, if implemented they must be implemented as described since OSPM manipulates the registers of ﬁxed
hardware devices and expects the deﬁned behavior. Functional ﬁxed hardware provides functional equivalents of the
ﬁxed hardware feature interfaces as described in Generic Hardware Programming Model
Generic hardware feature implementation is ﬂexible. This logic is controlled by OEM-supplied AML code (for more
information, see ACPI Software Programming Model ), which can be written to support a wide variety of hardware.
Also, ACPI provides specialized control methods that provide capabilities for specialized devices. For example, the
Notify command can be used to notify OSPM from a generic hardware event handler (control method) that a docking
or thermal event has taken place. A good understanding of this section and ACPI Software Programming Model of
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this speciﬁcation will give designers a good understanding of how to design hardware to take full advantage of an
ACPI-compatible OS.
Notice that the generic features are listed for illustration only, the ACPI speciﬁcation can support many types of
hardware not listed.
Table 4.1: Feature-Programming Model Summary
Feature Name Description Programming Model
Power Management
Timer24-bit or 32-bit free running timer. Fixed Hardware Feature Control Logic
Power Button User pushes button to switch the system
between the working and sleeping/soft-off
states.Fixed Hardware Event and Control Logic or
Generic Hardware Event and Logic
Sleep Button User pushes button to switch the system
Power Button Over-
rideUser sequence (press the power button for at
least 4 seconds) to turn off a hung system.
Real Time Clock
AlarmProgrammed time to wake the system. Optional Fixed Hardware*
Sleep/Wake Control
LogicLogic used to transition the system between
the sleeping and working states.Fixed Hardware Control and Event Logic
Embedded Con-
troller InterfaceACPI Embedded Controller protocol and in-
terface, as described in the ACPI Embedded
Controller Interface Speciﬁcation .Generic Hardware Event Logic, must reside
in the general-purpose register block
Legacy/ACPI Select Status bit that indicates the system is us-
ing the legacy or ACPI power management
model (SCI_EN).Fixed Hardware Control Logic
Lid switch Button used to indicate whether the system’s
lid is open or closed (mobile systems only)Generic Hardware Event Feature
C1 Power State Processor instruction to place the processor
into a low-power state.Processor ISA
C2 Power Control Logic to place the processor into a C2 power
state.Fixed Hardware Control Logic
C3 Power Control Logic to place the processor into a C3 power
Thermal Control Logic to generate thermal events at speciﬁed
trip points.Generic Hardware Event and Control Logic
(See description of thermal logic in Thermal
Management Concepts )
Device Power Man-
agementControl logic for switching between differ-
ent device power states.Generic Hardware control logic
AC Adapter Logic to detect the insertion and removal of
the AC adapter.Generic Hardware event logic
Docking/device in-
sertion and removalLogic to detect device insertion and removal
events.Generic Hardware event logic
* RTC wakeup alarm is required; the ﬁxed hardware feature status bit is optional.
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4.8 ACPI Register Model
ACPI hardware resides in one of six address spaces:
• System I/O
• System memory
• PCI conﬁguration
• SMBus
• Embedded controller
• Functional Fixed Hardware
Different implementations will result in different address spaces being used for different functions. The ACPI speci-
ﬁcation consists of ﬁxed hardware registers and generic hardware registers. Fixed hardware registers are required to
implement ACPI-deﬁned interfaces. The generic hardware registers are needed for any events generated by value-
added hardware.
ACPI deﬁnes register blocks. An ACPI-compatible system provides an ACPI table (the FADT, built in memory at
boot-up) that contains a list of pointers to the different ﬁxed hardware register blocks used by OSPM. The bits within
these registers have attributes deﬁned for the given register block. The types of registers that ACPI deﬁnes are:
• Status/Enable Registers (for events)
• Control Registers
If a register block is of the status/enable type, then it will contain a register with status bits, and a corresponding
register with enable bits. The status and enable bits have an exact implementation deﬁnition that needs to be followed
(unless otherwise noted), which is illustrated by the following diagram:
Fig. 4.4: Block Diagram of a Status/Enable Cell
Notice that the status bit, which hardware sets by the Event Input being set in this example, can only be cleared by
software writing a 1 to its bit position. Also, the enable bit has no effect on the setting or resetting of the status bit; it
only determines if the SET status bit will generate an “Event Output,” which generates an SCI when set if its enable
bit is set.
ACPI also deﬁnes register groupings. A register grouping consists of two register blocks, with two pointers to two
different blocks of registers, where each bit location within a register grouping is ﬁxed and cannot be changed. The
bits within a register grouping, which have ﬁxed bit positions, can be split between the two register blocks. This allows
the bits within a register grouping to reside in either or both register blocks, facilitating the ability to map bits within
several different chips to the same register thus providing the programming model with a single register grouping bit
OSPM treats a register grouping as a single register; but located in multiple places. To read a register grouping, OSPM
will read the “A” register block, followed by the “B” register block, and then will logically “OR” the two results
together (the SLP_TYP ﬁeld is an exception to this rule). Reserved bits, or unused bits within a register block always
return zero for reads and have no side effects for writes (which is a requirement).
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The SLP_TYPx ﬁeld can be different for each register grouping. The respective sleeping object \_Sx contains a
SLP_TYPa and a SLP_TYPb ﬁeld. That is, the object returns a package with two integer values of 0-7 in it. OSPM
will always write the SLP_TYPa value to the “A” register block followed by the SLP_TYPb value within the ﬁeld
to the “B” register block. All other bit locations will be written with the same value. Also, OSPM does not read the
SLP_TYPx value but throws it away.
Fig. 4.5: Example Fixed Hardware Feature Register Grouping
As an example, the above diagram represents a register grouping consisting of register block A and register block b.
Bits “a” and “d” are implemented in register block B and register block A returns a zero for these bit positions. Bits
“b”, “c” and “e” are implemented in register block A and register block B returns a zero for these bit positions. All

reserved or ignored bits return their deﬁned ACPI values.
When accessing this register grouping, OSPM must read register block a, followed by reading register block b. OSPM
then does a logical OR of the two registers and then operates on the results.
When writing to this register grouping, OSPM will write the desired value to register group A followed by writing the
same value to register group B.
ACPI deﬁnes the following ﬁxed hardware register blocks. Each register block gets a separate pointer from the FADT.
These addresses are set by the OEM as static resources, so they are never changed–OSPM cannot re-map ACPI
resources. The following register blocks are deﬁned:
Fig. 4.6: Register Blocks versus Register Groupings
The PM1 EVT grouping consists of the PM1a_EVT and PM1b_EVT register blocks, which contain the ﬁxed hardware
feature event bits. Each event register block (if implemented) contains two registers: a status register and an enable
4.8. ACPI Register Model 60Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
register. Each register grouping has a deﬁned bit position that cannot be changed; however, the bit can be implemented
in either register block (A or B). The A and B register blocks for the events allow chipsets to vary the partitioning of
events into two or more chips. For read operations, OSPM will generate a read to the associated A and B registers,
OR the two values together, and then operate on this result. For write operations, OSPM will write the value to the
associated register in both register blocks. Therefore, there are two rules to follow when implementing event registers:
• Reserved or unimplemented bits always return zero (control or enable).
• Writes to reserved or unimplemented bits have no affect.
The PM1 CNT grouping contains the ﬁxed hardware feature control bits and consists of the PM1a_CNT_BLK and
PM1b_CNT_BLK register blocks. Each register block is associated with a single control register. Each register
grouping has a deﬁned bit position that cannot be changed; however, the bit can be implemented in either register
block (A or B). There are two rules to follow when implementing CNT registers:
The PM2_CNT_BLK register block currently contains a single bit for the arbiter disable function. The general-
purpose event register contains the event programming model for generic features. All generic events, just as ﬁxed
events, generate SCIs. Generic event status bits can reside anywhere; however, the top-level generic event resides in
one of the general-purpose register blocks. Any generic feature event status not in the general-purpose register space
is considered a child or sibling status bit, whose parent status bit is in the general-purpose event register space. Notice
that it is possible to have N levels of general-purpose events prior to hitting the GPE event status.
General-purpose event registers are described by two register blocks: The GPE0_BLK or the GPE1_BLK. Each
register block is pointed to separately from within the FADT. Each register block is further broken into two registers:
GPEx_STS and GPEx_EN. The status and enable registers in the general-purpose event registers follow the event
model for the ﬁxed hardware event registers.
4.8.1 ACPI Register Summary
The following tables summarize the ACPI registers:
Table 4.2: PM1 Event Registers
Register Size (Bytes) Address (relative to register block)
PM1a_STS PM1_EVT_LEN/2 <PM1a_EVT_BLK>
PM1a_EN PM1_EVT_LEN/2 <PM1a_EVT_BLK>+PM1_EVT_LEN/2
PM1b_STS PM1_EVT_LEN/2 <PM1b_EVT_BLK>
PM1b_EN PM1_EVT_LEN/2 <PM1b_EVT_BLK>+PM1_EVT_LEN/2
Table 4.3: PM1 Control Registers
PM1_CNTa PM1_CNT_LEN <PM1a_CNT_BLK>
PM1_CNTb PM1_CNT_LEN <<PM1b_CNT_BLK>
Table 4.4: PM2 Control Register
PM2_CNT PM2_CNT_LEN <PM2_CNT_BLK>
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Table 4.5: PM Timer Register
PM_TMR PM_TMR_LEN <PM_TMR_BLK>
Table 4.6: Processor Control Registers
P_CNT 4 Either <P_BLK> or speciﬁed by the PTC object - see Processor Throttling
Controls
P_LVL2 1 <P_BLK>+4h
P_LVL3 1 <P_BLK>+5h
Table 4.7: General-Purpose Event Registers
GPE0_STS GPE0_LEN/2 <GPE0_BLK>
GPE0_EN GPE0_LEN/2 <GPE0_BLK>+GPE0_LEN/2
GPE1_STS GPE1_LEN/2 <GPE1_BLK>
GPE1_EN GPE1_LEN/2 <GPE1_BLK>+GPE1_LEN/2
4.8.1.1 PM1 Event Registers
The PM1 event register grouping contains two register blocks: the PM1a_EVT_BLK is a required register block when
the following ACPI interface categories are required by a class speciﬁc platform design guide:
• Processor power state control/status
• Power or Sleep button (ﬁxed register interfaces)
The PM1b_EVT_BLK is an optional register block. Each register block has a unique 32-bit pointer in the Fixed
ACPI Table (FADT) to allow the PM1 event bits to be partitioned between two chips. If the PM1b_EVT_BLK is not
supported, its pointer contains a value of zero in the FADT.
Each register block in the PM1 event grouping contains two registers that are required to be the same size: the
PM1x_STS and PM1x_EN (where x can be “a” or “b”). The length of the registers is variable and is described by the
PM1_EVT_LEN ﬁeld in the FADT, which indicates the total length of the register block in bytes. Hence if a length
of “4” is given, this indicates that each register contains two bytes of I/O space. The PM1 event register block has a
minimum size of 4 bytes.
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4.8.1.2 PM1 Control Registers
The PM1 control register grouping contains two register blocks: the PM1a_CNT_BLK is a required register block
when the following ACPI interface categories are required by a class speciﬁc platform design guide:
• SCI/SMI routing control/status for power management and general-purpose events
The PM1b_CNT_BLK is an optional register block. Each register block has a unique 32-bit pointer in the Fixed
ACPI Table (FADT) to allow the PM1 event bits to be partitioned between two chips. If the PM1b_CNT_BLK is not
Each register block in the PM1 control grouping contains a single register: the PM1x_CNT. The length of the register
is variable and is described by the PM1_CNT_LEN ﬁeld in the FADT, which indicates the total length of the register
block in bytes. The PM1 control register block must have a minimum size of 2 bytes.
4.8.1.3 PM2 Control Register
The PM2 control register is contained in the PM2_CNT_BLK register block. The FADT contains a length variable
for this register block (PM2_CNT_LEN) that is equal to the size in bytes of the PM2_CNT register (the only register
in this register block). This register block is optional, if not supported its block pointer and length contain a value of
zero.
4.8.1.4 PM Timer Register
The PM timer register is contained in the PM_TMR_BLK register block. It is an optional register block that must be
implemented when the power management timer control/status ACPI interface category is required by a class speciﬁc
platform design guide.
If deﬁned, this register block contains the register that returns the running value of the power management timer. The
FADT also contains a length variable for this register block (PM_TMR_LEN) that is equal to the size in bytes of the
PM_TMR register (the only register in this register block).
4.8.1.5 Processor Control Block (P_BLK)
There is an optional processor control register block for each processor in the system. As this is a homogeneous feature,
all processors must have the same level of support. The ACPI OS will revert to the lowest common denominator of
processor control block support. The processor control block contains the processor control register (P_CNT-a 32-bit
performance control conﬁguration register), and the P_LVL2 and P_LVL3 CPU sleep state control registers. The 32-
bit P_CNT register controls the behavior of the processor clock logic for that processor, the P_LVL2 register is used
to place the CPU into the C2 state, and the P_LVL3 register is used to place the processor into the C3 state.
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4.8.1.6 General-Purpose Event Registers

The general-purpose event registers contain the root level events for all generic features. To facilitate the ﬂexibil-
ity of partitioning the root events, ACPI provides for two different general-purpose event blocks: GPE0_BLK and
GPE1_BLK. These are separate register blocks and are not a register grouping, because there is no need to main-
tain an orthogonal bit arrangement. Also, each register block contains its own length variable in the FADT, where
GPE0_LEN and GPE1_LEN represent the length in bytes of each register block.
Each register block contains two registers of equal length: GPEx_STS and GPEx_EN (where x is 0 or 1). The length of
the GPE0_STS and GPE0_EN registers is equal to half the GPE0_LEN. The length of the GPE1_STS and GPE1_EN
registers is equal to half the GPE1_LEN. If a generic register block is not supported then its respective block pointer
and block length values in the FADT table contain zeros. The GPE0_LEN and GPE1_LEN do not need to be the same
size.
4.8.2 Fixed Hardware Features
This section describes the ﬁxed hardware features deﬁned by ACPI.
4.8.2.1 Power Management Timer
The ACPI speciﬁcation deﬁnes an optional power management timer that provides an accurate time value that can
be used by system software to measure and proﬁle system idleness (along with other tasks). The power management
timer provides an accurate time function while the system is in the working (G0) state. To allow software to extend the
number of bits in the timer, the power management timer generates an interrupt when the last bit of the timer changes
(from 0 to 1 or 1 to 0). ACPI supports either a 24-bit or 32-bit power management timer. The PM Timer is accessed
directly by OSPM, and its programming model is contained in ﬁxed register space. The programming model can be
partitioned in up to three different register blocks. The event bits are contained in the PM1_EVT register grouping,
which has two register blocks, and the timer value can be accessed through the PM_TMR_BLK register block. A
block diagram of the power management timer is illustrated in the following ﬁgure.
Fig. 4.7: Power Management Timer
The power management timer is a 24-bit or 32-bit ﬁxed rate free running count-up timer that runs off a 3.579545
MHz clock. The ACPI OS checks the FADT to determine whether the PM Timer is a 32-bit or 24-bit timer. The
programming model for the PM Timer consists of event logic, and a read port to the counter value. The event logic
consists of an event status and enable bit. The status bit is set any time the last bit of the timer (bit 23 or bit 31) goes
from set to clear or clear to set. If the TMR_EN bit is set, then the setting of the TMR_STS will generate an ACPI
event in the PM1_EVT register grouping (referred to as PMTMR_PME in the diagram). The event logic is only used
to emulate a larger timer.
OSPM uses the read-only TMR_V AL ﬁeld (in the PM TMR register grouping) to read the current value of the timer.
OSPM never assumes an initial value of the TMR_V AL ﬁeld; instead, it reads an initial TMR_V AL upon loading
OSPM and assumes that the timer is counting. It is allowable to stop the Timer when the system transitions out of the
working (G0/S0) state. The only timer reset requirement is that the timer functions while in the working state.
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The PM Timer’s programming model is implemented as a ﬁxed hardware feature to increase the accuracy of reading
the timer.
4.8.2.2 Console Buttons
ACPI deﬁnes user-initiated events to request OSPM to transition the platform between the G0 working state and the G1
sleeping, G2 soft off and G3 mechanical off states. ACPI also deﬁnes a recommended mechanism to unconditionally
transition the platform from a hung G0 working state to the G2 soft-off state.
ACPI operating systems use power button events to determine when the user is present. As such, these ACPI events
are associated with buttons in the ACPI speciﬁcation.
The ACPI speciﬁcation supports two button models:
• A single-button model that generates an event for both sleeping and entering the soft-off state. The function of
the button can be conﬁgured using OSPM UI.
• A dual-button model where the power button generates a soft-off transition request and a sleep button generates
a sleep transition request. The type of button implies the function of the button.
Control of these button events is either through the ﬁxed hardware programming model or the generic hardware
programming model (control method based). The ﬁxed hardware programming model has the advantage that OSPM
can access the button at any time, including when the system is crashed. In a crashed system with a ﬁxed hardware
power button, OSPM can make a “best” effort to determine whether the power button has been pressed to transition to
the system to the soft-off state, because it doesn’t require the AML interpreter to access the event bits.
4.8.2.2.1 Power Button
The power button logic can be used in one of two models: single button or dual button. In the single-button model, the
user button acts as both a power button for transitioning the system between the G0 and G2 states and a sleep button
for transitioning the system between the G0 and G1 states. The action of the user pressing the button is determined by
software policy or user settings. In the dual-button model, there are separate buttons for sleeping and power control.
Although the buttons still generate events that cause software to take an action, the function of the button is now
dedicated: the sleep button generates a sleep request to OSPM and the power button generates a wake request.
Support for a power button is indicated by a combination of the PWR_BUTTON ﬂag and the power button device
object, as shown in the following:
Table 4.8: Power Button Support
Indicated Support PWR_BUTTON Flag Power Button Device Object
Fixed hardware power button Clear Absent
Control method power button Set Present
The power button can also have an additional capability to unconditionally transition the system from a hung working
state to the G2 soft-off state. In the case where OSPM event handler is no longer able to respond to power button
events, the power button override feature provides a back-up mechanism to unconditionally transition the system to
the soft-off state. This feature can be used when the platform doesn’t have a mechanical off button, which can also
provide this function. ACPI deﬁnes that holding the power button active for four seconds or longer will generate a
power button override event.
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4.8.2.2.1.1 Fixed Power Button
Fig. 4.8: Fixed Power Button Logic
The ﬁxed hardware power button has its event programming model in the PM1x_EVT_BLK. This logic consists
of a single enable bit and sticky status bit. When the user presses the power button, the power button status bit
(PWRBTN_STS) is unconditionally set. If the power button enable bit (PWRBTN_EN) is set and the power button
status bit is set (PWRBTN_STS) due to a button press while the system is in the G0 state, then an SCI is generated.
OSPM responds to the event by clearing the PWRBTN_STS bit. The power button logic provides debounce logic that
sets the PWRBTN_STS bit on the button press “edge.”
While the system is in the G1 or G2 global states (S1, S2, S3, S4 or S5 states), any further power button press after
the button press that transitioned the system into the sleeping state unconditionally sets the power button status bit and
wakes the system, regardless of the value of the power button enable bit. OSPM responds by clearing the power button
status bit and waking the system.
4.8.2.2.1.2 Control Method Power Button
The power button programming model can also use the generic hardware programming model. This allows the power
button to reside in any of the generic hardware address spaces (for example, the embedded controller) instead of ﬁxed
space. If the power button is implemented using generic hardware, then the OEM needs to deﬁne the power button as
a device with an _HID object value of “PNP0C0C,” which then identiﬁes this device as the power button to OSPM.
The AML event handler then generates a Notify command to notify OSPM that a power button event was generated.
While the system is in the working state, a power button press is a user request to transition the system into either the
sleeping (G1) or soft-off state (G2). In these cases, the power button event handler issues the Notify command with
the device speciﬁc code of 0x80. This indicates to OSPM to pass control to the power button driver (PNP0C0C) with
the knowledge that a transition out of the G0 state is being requested. Upon waking from a G1 sleeping state, the AML
event handler generates a notify command with the code of 0x2 to indicate it was responsible for waking the system.

The power button device needs to be declared as a device within the ACPI Namespace for the platform and only
requires an _HID. An example deﬁnition follows.
This example ASL code performs the following:
• Creates a device named “PWRB” and associates the Plug and Play identiﬁer (through the _HID object) of
“PNP0C0C.”
• The Plug and Play identiﬁer associates this device object with the power button driver.
• Creates an operational region for the control method power button’s programming model: System I/O space at
0x200.
• Fields that are not accessed are written as zeros. These status bits clear upon writing a 1 to their bit position,
therefore preserved would fail in this case.
• Creates a ﬁeld within the operational region for the power button status bit (called PBP). In this case the power
button status bit is a child of the general-purpose event status bit 0. When this bit is set, it is the responsibility of
the ASL-code to clear it (OSPM clears the general-purpose status bits). The address of the status bit is 0x200.0
(bit 0 at address 0x200).
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• Creates an additional status bit called PBW for the power button wake event. This is the next bit and its physical
address would be 0x200.1 (bit 1 at address 0x200).
• Generates an event handler for the power button that is connected to bit 0 of the general-purpose event status
register 0. The event handler does the following:
• Clears the power button status bit in hardware (writes a one to it).
• Notiﬁes OSPM of the event by calling the Notify command passing the power button object and the device
speciﬁc event indicator 0x80.
// Define a control method power button
Device(\_SB.PWRB)
{
Name(_HID, EISAID("PNP0C0C"))
Name(_PRW, Package(){0, 0x4})
OperationRegion(\PHO, SystemIO, 0x200, 0x1)
Field(\PHO, ByteAcc, NoLock, WriteAsZeros)
{
PBP, 1, // sleep/off request
PBW, 1 // wakeup request
}
}
Scope(\_GPE) // Root level event handlers
{
Method(_L00)
{
// uses bit 0 of GP0_STS register
If (PBP)
{
PBP = One // clear power button status
Notify(\_SB.PWRB, 0x80) // Notify OS of event
}
If (\PBW)
{
PBW = One
Notify(\_SB.PWRB, 0x2)
}
}
}
4.8.2.2.1.3 Power Button Override
The ACPI speciﬁcation also allows that if the user presses the power button for more than four seconds while the
system is in the working state, a hardware event is generated and the system will transition to the soft-off state. This
hardware event is called a power button override. In reaction to the power button override event, the hardware clears
the power button status bit (PWRBTN_STS).
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4.8.2.2.2 Sleep Button
When using the two button model, ACPI supports a second button that when pressed will request OSPM to transition
the platform between the G0 working and G1 sleeping states. Support for a sleep button is indicated by a combination
of the SLEEP_BUTTON ﬂag and the sleep button device object:
Table 4.9: Sleep Button Support
Indicated Support SLEEP_BUTTON Flag Sleep Button Device Object
No sleep button Set Absent
Fixed hardware slee button Clear Absent
Control method sleep button Set Present
4.8.2.2.2.1 Fixed Hardware Sleep Button
Fig. 4.9: Fixed Hardware Sleep Button Logic
The ﬁxed hardware sleep button has its event programming model in the PM1x_EVT_BLK. This logic consists of a sin-
gle enable bit and sticky status bit. When the user presses the sleep button, the sleep button status bit (SLPBTN_STS)
is unconditionally set. Additionally, if the sleep button enable bit (SLPBTN_EN) is set, and the sleep button status
bit is set (SLPBTN_STS, due to a button press) while the system is in the G0 state, then an SCI is generated. OSPM
responds to the event by clearing the SLPBTN_STS bit. The sleep button logic provides debounce logic that sets the
SLPBTN_STS bit on the button press “edge.”
While the system is sleeping (in either the S0, S1, S2, S3 or S4 states), any further sleep button press (after the button
press that caused the system transition into the sleeping state) sets the sleep button status bit (SLPBTN_STS) and
wakes the system if the SLP_EN bit is set. OSPM responds by clearing the sleep button status bit and waking the
system.
4.8.2.2.2.2 Control Method Sleep Button
The sleep button programming model can also use the generic hardware programming model. This allows the sleep
space. If the sleep button is implemented via generic hardware, then the OEM needs to deﬁne the sleep button as a
device with an _HID object value of “PNP0C0E”, which then identiﬁes this device as the sleep button to OSPM. The
AML event handler then generates a Notify command to notify OSPM that a sleep button event was generated. While
in the working state, a sleep button press is a user request to transition the system into the sleeping (G1) state. In
these cases the sleep button event handler issues the Notify command with the device speciﬁc code of 0x80. This will
indicate to OSPM to pass control to the sleep button driver (PNP0C0E) with the knowledge that the user is requesting
a transition out of the G0 state. Upon waking-up from a G1 sleeping state, the AML event handler generates a Notify
command with the code of 0x2 to indicate it was responsible for waking the system.
The sleep button device needs to be declared as a device within the ACPI Namespace for the platform and only requires
an _HID. An example deﬁnition is shown below.
The AML code below does the following:
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• Creates a device named “SLPB” and associates the Plug and Play identiﬁer (through the _HID object) of
“PNP0C0E.”
• The Plug and Play identiﬁer associates this device object with the sleep button driver.
• Creates an operational region for the control method sleep button’s programming model: System I/O space at
0x201.
• Fields that are not accessed are written as “1s” (these status bits clear upon writing a “1” to their bit position,
hence preserved would fail in this case).
• Creates a ﬁeld within the operational region for the sleep button status bit (called PBP). In this case the sleep
button status bit is a child of the general-purpose status bit 0. When this bit is set it is the responsibility of the
AML code to clear it (OSPM clears the general-purpose status bits). The address of the status bit is 0x201.0 (bit
0 at address 0x201).
• Creates an additional status bit called PBW for the sleep button wake event. This is the next bit and its physical
address would be 0x201.1 (bit 1 at address 0x201).
• Generates an event handler for the sleep button that is connected to bit 0 of the general-purpose status register
0. The event handler does the following:
• Clears the sleep button status bit in hardware (writes a “1” to it).
• Notiﬁes OSPM of the event by calling the Notify command passing the sleep button object and the device
// Define a control method sleep button
Device(\_SB.SLPB)
{
Name (_HID, EISAID("PNP0C0E"))
Name (_PRW, Package(){0x01, 0x04})
OperationRegion (\Boo, SystemIO, 0x201, 0x1)
Field (\Boo, ByteAcc, NoLock, WriteAsZeros)
{
SBP, 1, // sleep request
SBW, 1 // wakeup request
}
}
Scope (\_GPE) // Root level event handlers
{
Method (_L01) // uses bit 1 of GP0_STS register
{
If (\SBP)
{
\SBP = One // clear sleep button status
Notify(\_SB.SLPB, 0x80) // Notify OS of event
}
If (\SBW)
{
\SBW = One
Notify(\_SB.SLPB, 0x2)
}
}
}
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4.8.2.3 Sleeping/Wake Control
The sleeping/wake logic consists of logic that will sequence the system into the deﬁned low-power hardware sleeping
state (S1-S4) or soft-off state (S5) and will wake the system back to the working state upon a wake event. Notice that
the S4BIOS state is entered in a different manner (for more information, see The S4BIOS Transition ).
Fig. 4.10: Sleeping/Wake Logic
The logic is controlled via two bit ﬁelds: Sleep Enable (SLP_EN) and Sleep Type (SLP_TYPx). The type of sleep
or soft-off state desired is programmed into the SLP_TYPx ﬁeld and upon assertion of the SLP_EN the hardware
will sequence the system into the deﬁned sleeping state. OSPM gets values for the SLP_TYPx ﬁeld from the \_Sx
objects deﬁned in the static deﬁnition block. If the object is missing OSPM assumes the hardware does not support
that sleeping state. Prior to entering the desired sleeping state, OSPM will read the designated \_Sx object and place
this value in the SLP_TYP ﬁeld.
Additionally ACPI deﬁnes a fail-safe Off protocol called the “power button override,” which allows the user to initiate
an Off sequence in the case where the system software is no longer able to recover the system (the system has hung).

ACPI deﬁnes that this sequence be initiated by the user pressing the power button for over 4 seconds, at which point
the hardware unconditionally sequences the system to the Off state. This logic is represented by the PWRBTN_OR
signal coming into the sleep logic.
While in any of the sleeping states (G1), an enabled “Wake” event will cause the hardware to sequence the system
back to the working state (G0). The “Wake Status” bit (WAK_STS) is provided for OSPM to “spin-on” after setting
the SLP_EN/SLP_TYP bit ﬁelds. When waking from the S1 sleeping state, execution control is passed backed to
OSPM immediately, whereas when waking from the S2-S4 states execution control is passed to the platform boot
ﬁrmware (execution begins at the CPU’s reset vector). The WAK_STS bit provides a mechanism to separate OSPM’s
sleeping and waking code during an S1 sequence. When the hardware has sequenced the system into the sleeping state
(deﬁned here as the processor is no longer able to execute instructions), any enabled wake event is allowed to set the
WAK_STS bit and sequence the system back on (to the G0 state). If the system does not support the S1 sleeping state,
the WAK_STS bit can always return zero.
If more than a single sleeping state is supported, then the sleeping/wake logic is required to be able to dynamically
sequence between the different sleeping states. This is accomplished by waking the system; OSPM programs the new
sleep state into the SLP_TYP ﬁeld, and then sets the SLP_EN bit-placing the system again in the sleeping state.
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4.8.2.4 Real Time Clock Alarm
If implemented, the Real Time Clock (RTC) alarm must generate a hardware wake event when in the sleeping state.
The RTC can be programmed to generate an alarm. An enabled RTC alarm can be used to generate a wake event when
the system is in a sleeping state. ACPI provides for additional hardware to support OSPM in determining that the RTC
was the source of the wake event: the RTC_STS and RTC_EN bits. Although these bits are optional, if supported they
must be implemented as described here.
If the RTC_STS and RTC_EN bits are not supported, OSPM will attempt to identify the RTC as a possible wake
source; however, it might miss certain wake events. If implemented, the RTC wake feature is required to work in the
following sleeping states: S1-S3. S4 wake is optional and supported through the RTC_S4 ﬂag within the FADT (if
set, then the platform supports RTC wake in the S4 state) *.
Note: * The G2/S5 “soft off” and the G3 “mechanical off” states are not sleeping states. The OS will disable the
RTC_EN bit prior to entering the G2/S5 or G3 states regardless.
When the RTC generates a wake event the RTC_STS bit will be set. If the RTC_EN bit is set, an RTC hardware
power management event will be generated (which will wake the system from a sleeping state, provided the battery
low signal is not asserted).
Fig. 4.11: RTC Alarm
The RTC wake event status and enable bits are an optional ﬁxed hardware feature and a ﬂag within the FADT
(FIX_RTC) indicates if the register bits are to be used by OSPM. If the RTC wake event status and enable bits are
implemented in ﬁxed hardware, OSPM can determine if the RTC was the source of the wake event without loading the
entire OS. This also gives the platform the capability of indicating an RTC wake source without consuming a GPE bit,
as would be required if RTC wake was not implemented using the ﬁxed hardware RTC feature. If the ﬁxed hardware
feature event bits are not supported, then OSPM will attempt to determine this by reading the RTC’s status ﬁeld. If the
platform implements the RTC ﬁxed hardware feature, and this hardware consumes resources, the _FIX method can be
used to correlate these resources with the ﬁxed hardware. See _FIX (Fixed Register Resource Provider) , for details.
OSPM supports enhancements over the existing RTC device (which only supports a 99 year date and 24-hour alarm).
Optional extensions are provided for the following features:
Day Alarm The DAY_ALRM ﬁeld points to an optional CMOS RAM location that selects the day within the month
to generate an RTC alarm.
Month Alarm The MON_ALRM ﬁeld points to an optional CMOS RAM location that selects the month within the
year to generate an RTC alarm.
Centenary Value The CENT ﬁeld points to an optional CMOS RAM location that represents the centenary value of
the date (thousands and hundreds of years).
The RTC_STS bit may be set through the RTC interrupt (IRQ8 in IA-PC architecture systems). OSPM will insure
that the periodic and update interrupt sources are disabled prior to sleeping. This allows the RTC’s interrupt pin to
serve as the source for the RTC_STS bit generation. Note however that if the RTC interrupt pin is used for RTC_STS
generation, the RTC_STS bit value may not be accurate when waking from S4. If this value is accurate when waking
from S4, the platform should set the S4_RTC_STS_V ALID ﬂag, so that OSPM can utilize the RTC_STS information.
4.8. ACPI Register Model 71Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 4.10: Alarm Field Decodings within the FADT
Field Value Address (Location) in RTC CMOS
RAM (Must be Bank 0)
DAY_ALRM
Eight bit value that can represent 0x01-0x31
days in BCD or 0x01-0x1F days in binary. Bits 6
and 7 of this ﬁeld are treated as Ignored by
software. The RTC is initialized such that this
ﬁeld contains a “don’t care” value when the
platform ﬁrmware switches from legacy to
ACPI mode. A don’t care value can be any
unused value (not 0x1-0x31 BCD or 0x01-0x1F
hex) that the RTC reverts back to a 24 hour
alarm.The DAY_ALRM ﬁeld in the FADT will
contain a non-zero value that represents
an offset into the RTC’s CMOS RAM area
that contains the day alarm value. A value
of zero in the DAY_ALRM ﬁeld indicates
that the day alarm feature is not
MON_ALRM
Eight bit value that can represent 01-12
months in BCD or 0x01-0xC months in binary.
The RTC is initialized such that this ﬁeld
contains a don’t care value when the platform
ﬁrmware switches from legacy to ACPI mode.
A “don’t care” value can be any unused value
(not 1-12 BCD or x01-xC hex) that the RTC
reverts back to a 24 hour alarm and/or 31 day
alarm).The MON_ALRM ﬁeld in the FADT will
that contains the month alarm value. A
value of zero in the MON_ALRM ﬁeld
indicates that the month alarm feature is
not supported. If the month alarm is
supported, the day alarm function must
also be supported.
CENTURY
8-bit BCD or binary value. This value indicates
the thousand year and hundred year
(Centenary) variables of the date in BCD (19
for this century, 20 for the next) or binary
(x13 for this century, x14 for the next).The CENTURY ﬁeld in the FADT will
that contains the Centenary value for the
date. A value of zero in the CENTURY
ﬁeld
indicates that the Centenary value is not
supported by this RTC.
4.8.2.5 Legacy/ACPI Select and the SCI Interrupt
As mentioned previously, power management events are generated to initiate an interrupt or hardware sequence. ACPI
operating systems use the SCI interrupt handler to respond to events, while legacy systems use some type of transparent
interrupt handler to respond to these events (that is, an SMI interrupt handler). ACPI-compatible hardware can choose
to support both legacy and ACPI modes or just an ACPI mode. Legacy hardware is needed to support these features
for non-ACPI-compatible operating systems. When the ACPI OS loads, it scans the platform ﬁrmware tables to
determine that the hardware supports ACPI, and then if the it ﬁnds the SCI_EN bit reset (indicating that ACPI is
not enabled), issues an ACPI activate command to the SMI handler through the SMI command port. The platform
ﬁrmware acknowledges the switching to the ACPI model of power management by setting the SCI_EN bit (this bit
can also be used to switch over the event mechanism as illustrated below):
4.8. ACPI Register Model 72Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 4.12: Power Management Events to SMI/SCI Control Logic
The interrupt events (those that generate SMIs in legacy mode and SCIs in ACPI mode) are sent through a decoder
controlled by the SCI_EN bit. For legacy mode this bit is reset, which routes the interrupt events to the SMI interrupt
logic. For ACPI mode this bit is set, which routes interrupt events to the SCI interrupt logic. This bit always returns
set for ACPI-compatible hardware that does not support a legacy power management mode (in other words, the bit is
wired to read as “1” and ignore writes).
The SCI interrupt is deﬁned to be a shareable interrupt and is connected to an OS visible interrupt that uses a shareable

protocol. The FADT has an entry that indicates what interrupt the SCI interrupt is mapped to (see System Description
Table Header ).
If the ACPI platform supports both legacy and ACPI modes, it has a register that generates a hardware event (for
example, SMI for IA-PC processors). OSPM uses this register to make the hardware switch in and out of ACPI mode.
Within the FADT are three values that signify the address (SMI_CMD) of this port and the data value written to enable
the ACPI state (ACPI_ENABLE), and to disable the ACPI state (ACPI_DISABLE).
To transition an ACPI/Legacy platform from the Legacy mode to the ACPI mode the following would occur:
• ACPI driver checks that the SCI_EN bit is zero, and that it is in the Legacy mode.
• OSPM does an OUT to the SMI_CMD port with the data in the ACPI_ENABLE ﬁeld of the FADT.
• OSPM polls the SCI_EN bit until it is sampled as SET.
To transition an ACPI/Legacy platform from the ACPI mode to the Legacy mode the following would occur:
• ACPI driver checks that the SCI_EN bit is one, and that it is in the ACPI mode.
• OSPM does an OUT to the SMI_CMD port with the data in the ACPI_DISABLE ﬁeld of the FADT.
• OSPM polls the SCI_EN bit until it is sampled as RESET.
Platforms that only support ACPI always return a 1 for the SCI_EN bit. In this case OSPM skips the Legacy to ACPI
transition stated above.
4.8.2.6 Processor Control
The ACPI speciﬁcation deﬁnes several processor controls including power state control, throttling control, and perfor-
mance state control. See Processor Conﬁguration and Control for a complete description of the processor controls.
4.8. ACPI Register Model 73Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
4.8.3 Fixed Hardware Registers
The ﬁxed hardware registers are manipulated directly by OSPM. The following sections describe ﬁxed hardware
features under the programming model. OSPM owns all the ﬁxed hardware resource registers; these registers cannot
be manipulated by AML code. Registers are accessed with any width up to its register width (byte granular).
4.8.3.1 PM1 Event Grouping
The PM1 Event Grouping has a set of bits that can be distributed between two different register blocks. This allows
these registers to be partitioned between two chips, or all placed in a single chip. Although the bits can be split between
the two register blocks (each register block has a unique pointer within the FADT), the bit positions are maintained.
The register block with unimplemented bits (that is, those implemented in the other register block) always returns
zeros, and writes have no side effects.
4.8.3.1.1 PM1 Status Registers
Register Location: <PM1a_EVT_BLK / PM1b_EVT_BLK> System I/O or Memory Space
Default Value: 00h
Attribute: Read/Write
Size: PM1_EVT_LEN / 2
The PM1 status registers contain the ﬁxed hardware feature status bits. The bits can be split between two registers:
PM1a_STS or PM1b_STS. Each register grouping can be at a different 32-bit aligned address and is pointed to by the
PM1a_EVT_BLK or PM1b_EVT_BLK. The values for these pointers to the register space are found in the FADT.
Accesses to the PM1 status registers are done through byte or word accesses.
For ACPI/legacy systems, when transitioning from the legacy to the G0 working state this register is cleared by
platform ﬁrmware prior to setting the SCI_EN bit (and thus passing control to OSPM). For ACPI only platforms
(where SCI_EN is always set), when transitioning from either the mechanical off (G3) or soft-off state to the G0
working state this register is cleared prior to entering the G0 working state.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates that the feature is
not supported as a ﬁxed hardware feature, then software treats these bits as ignored.
Table 4.11: PM1 Status Registers Fixed Hardware Feature Status
Bits
Bit Name Description
0 TMR_STS This is the timer carry status bit. This bit gets set any time the most
signiﬁcant bit of a 24/32-bit counter changes from clear to set or set to
clear. While TMR_EN and TMR_STS are set, an interrupt event is raised.
1-3 Reserved Reserved
4 BM_STS This is the bus master status bit. This bit is set any time a system bus
master requests the system bus, and can only be cleared by writing a “1” to
this bit position. Notice that this bit reﬂects bus master activity, not CPU
activity (this bit monitors any bus master that can cause an incoherent
cache for a processor in the C3 state when the bus master performs a
memory transaction).
4.8. ACPI Register Model 74Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 4.11 – continued from previous page
5 GBL_STS This bit is set when an SCI is generated due to the platform runtime
ﬁrmware wanting the attention of the SCI handler. Platform runtime
ﬁrmware will have a control bit (somewhere within its address space) that
will raise an SCI and set this bit. This bit is set in response to the platform
runtime ﬁrmware releasing control of the Global Lock and having seen
the pending bit set.
6-7 Reserved Reserved. These bits always return a value of zero.
8 PWRBTN_STS This optional bit is set when the Power Button is pressed. In the system
working state, while PWRBTN_EN and PWRBTN_STS are both set, an
interrupt event is raised. In the sleep or soft-off state, a wake event is gen-
erated when the power button is pressed (regardless of the PWRBTN_EN
bit setting). This bit is only set by hardware and can only be reset by soft-
ware writing a “1” to this bit position. ACPI deﬁnes an optional mech-
anism for unconditional transitioning a system that has stopped working
from the G0 working state into the G2 soft-off state called the power but-
ton override. If the Power Button is held active for more than four sec-
onds, this bit is cleared by hardware and the system transitions into the
G2/S5 Soft Off state (unconditionally). Support for the power button is
indicated by the PWR_BUTTON ﬂag in the FADT being reset (zero). If
the PWR_BUTTON ﬂag is set or a power button device object is present
in the ACPI Namespace, then this bit ﬁeld is ignored by OSPM. If the
power button was the cause of the wake (from an S1-S4 state), then this
bit is set prior to returning control to OSPM.
9 SLPBTN_STS This optional bit is set when the sleep button is pressed. In the system
working state, while SLPBTN_EN and SLPBTN_STS are both set, an
interrupt event is raised. In the sleep or soft-off states a wake event is
generated when the sleeping button is pressed and the SLPBTN_EN bit
is set. This bit is only set by hardware and can only be reset by software
writing a “1” to this bit position. Support for the sleep button is indi-
cated by the SLP_BUTTON ﬂag in the FADT being reset (zero). If the
SLP_BUTTON ﬂag is set or a sleep button device object is present in the
ACPI Namespace, then this bit ﬁeld is ignored by OSPM. If the sleep but-
ton was the cause of the wake (from an S1-S4 state), then this bit is set
prior to returning control to OSPM.
10 RTC_STS This optional bit is set when the RTC generates an alarm (asserts the RTC
IRQ signal). Additionally, if the RTC_EN bit is set then the setting of the
RTC_STS bit will generate a power management event (an SCI, SMI, or
resume event). This bit is only set by hardware and can only be reset by
software writing a ‘1’ to this bit position. If the RTC was the cause of the
wake (from an S1-S3 state), then this bit is set prior to returning control to
OSPM. If the RTC_S4 ﬂag within the FADT is set, and the RTC was the
cause of the wake from the S4 state), then this bit is set prior to returning
control to OSPM.
11 Ignore This bit ﬁeld is ignored by software.
12-14 Reserved Reserved. These bits always return a value of zero.
4.8. ACPI Register Model 75Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
14 PCIEXP_WAKE_STS This bit is optional for chipsets that implement PCI Express. This bit is
set by hardware to indicate that the system woke due to a PCI Expressv
wakeup event. A PCI Express wakeup event is deﬁned as the PCI Express
WAKE# pin being active , one or more of the PCI Express ports being in
the beacon state, or receipt of a PCI Express PME message at a root port.
This bit should only be set when one of these events causes the system
to transition from a non-S0 system power state to the S0 system power
state. This bit is set independent of the state of the PCIEXP_WAKE_DIS
bit. Software writes a 1 to clear this bit. If the WAKE# pin is still active
during the write, one or more PCI Express ports is in the beacon state
or the PME message received indication has not been cleared in the root
port, then the bit will remain active (i.e. all inputs to this bit are level-
sensitive). Note: This bit does not itself cause a wake event or prevent

entry to a sleeping state. Thus if the bit is 1 and the system is put into a
sleeping state, the system will not automatically wake.
15 WAK_STS This bit is set when the system is in the sleeping state and an enabled wake
event occurs. Upon setting this bit system will transition to the working
state. This bit is set by hardware and can only be cleared by software
writing a “1” to this bit position.
4.8.3.1.2 PM1Enable Registers
Register Location: <<PM1a_EVT_BLK / PM1b_EVT_BLK> + PM1_EVT_LEN / 2 System I/O or Memory Space
The PM1 enable registers contain the ﬁxed hardware feature enable bits. The bits can be split between two registers:
PM1a_EN or PM1b_EN. Each register grouping can be at a different 32-bit aligned address and is pointed to by the
Accesses to the PM1 Enable registers are done through byte or word accesses.
For ACPI/legacy systems, when transitioning from the legacy to the G0 working state the enables are cleared by
platform ﬁrmware prior to setting the SCI_EN bit (and thus passing control to OSPM). For ACPI-only platforms
not supported as a ﬁxed hardware feature, then software treats the enable bits as write as zero.
Table 4.12: PM1 Enable Registers Fixed Hardware Feature Enable
Bits
0 TMR_EN This is the timer carry interrupt enable bit. When this bit is set then an SCI
event is generated anytime the TMR_STS bit is set. When this bit is reset
then no interrupt is generated when the TMR_STS bit is set.
1-4 Reserved Reserved. These bits always return a value of zero.
5 GBL_EN The global enable bit. When both the GBL_EN bit and the GBL_STS bit
are set, an SCI is raised.
4.8. ACPI Register Model 76Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 4.12 – continued from previous page
6-7 Reserved Reserved
8 PWRBTN_EN This optional bit is used to enable the setting of the PWRBTN_STS bit to
generate a power management event (SCI or wake). The PWRBTN_STS
bit is set anytime the power button is asserted. The enable bit does not have
to be set to enable the setting of the PWRBTN_STS bit by the assertion of
the power button (see description of the power button hardware). Support
for the power button is indicated by the PWR_BUTTON ﬂag in the FADT
being reset (zero). If the PWR_BUTTON ﬂag is set or a power button de-
vice object is present in the ACPI Namespace, then this bit ﬁeld is ignored
by OSPM.
9 SLPBTN_EN This optional bit is used to enable the setting of the SLPBTN_STS bit to
generate a power management event (SCI or wake). The SLPBTN_STS bit
is set anytime the sleep button is asserted. The enable bit does not have to
be set to enable the setting of the SLPBTN_STS bit by the active assertion
of the sleep button (see description of the sleep button hardware). Support
for the sleep button is indicated by the SLP_BUTTON ﬂag in the FADT
being reset (zero). If the SLP_BUTTON ﬂag is set or a sleep button device
object is present in the ACPI Namespace, then this bit ﬁeld is ignored by
OSPM.
10 RTC_EN This optional bit is used to enable the setting of the RTC_STS bit to gener-
ate a wake event. The RTC_STS bit is set any time the RTC generates an
alarm.
11-13 Reserved Reserved. These bits always return a value of zero.
14 PCIEXP_WAKE_DIS This bit is optional for chipsets that implement PCI Express. This bit dis-
ables the inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register
from waking the system. Modiﬁcation of this bit has no impact on the
value of the PCIEXP_WAKE_STS bit. PCIEXP_WAKE_DIS bit. Soft-
ware writes a 1 to clear this bit. If the WAKE# pin is still active during
the write, one or more PCI Express ports is in the beacon state or the PME
message received indication has not been cleared in the root port, then the
bit will remain active (i.e. all inputs to this bit are level-sensitive). Note:
This bit does not itself cause a wake event or prevent entry to a sleeping
state. Thus if the bit is 1 and the system is put into a sleeping state, the
system will not automatically wake.
15 Reserved Reserved. These bits always return a value of zero.
4.8.3.2 PM1 Control Grouping
The PM1 Control Grouping has a set of bits that can be distributed between two different registers. This allows these
registers to be partitioned between two chips, or all placed in a single chip. Although the bits can be split between
the two register blocks (each register block has a unique pointer within the FADT), the bit positions speciﬁed here are
maintained. The register block with unimplemented bits (that is, those implemented in the other register block) returns
4.8. ACPI Register Model 77Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
4.8.3.2.1 PM1 Control Registers
Register Location: <PM1a_CNT_BLK / PM1b_CNT_BLK> System I/O or Memory Space
Size: PM1_CNT_LEN
The PM1 control registers contain the ﬁxed hardware feature control bits. These bits can be split between two registers:
PM1a_CNT or PM1b_CNT. Each register grouping can be at a different 32-bit aligned address and is pointed to by
the PM1a_CNT_BLK or PM1b_CNT_BLK. The values for these pointers to the register space are found in the FADT.
Accesses to PM1 control registers are accessed through byte and word accesses.
Table 4.13: PM1 Control Registers Fixed Hardware Feature Control
Bits
0 SCI_EN Selects the power management event to be either an SCI or SMI
interrupt for the following events. When this bit is set, then power
management events will generate an SCI interrupt. When this bit is
reset power management events will generate an SMI interrupt. It
is the responsibility of the hardware to set or reset this bit. OSPM
always preserves this bit position.
1 BM_RLD When set, this bit allows the generation of a bus master request to
cause any processor in the C3 state to transition to the C0 state.
When this bit is reset, the generation of a bus master request does
not affect any processor in the C3 state.
2 GBL_RLS This write-only bit is used by the ACPI software to raise an event
to the platform runtime ﬁrmware, that is, generates an SMI to pass
execution control to the platform runtime ﬁrmware for IA-PC plat-
forms. Platform runtime ﬁrmware software has a corresponding en-
able and status bit to control its ability to receive ACPI events (for
example, BIOS_EN and BIOS_STS). The GBL_RLS bit is set by
OSPM to indicate a release of the Global Lock and the setting of the
pending bit in the FACS memory structure.
8:3 Reserved Reserved. These bits are reserved by OSPM.
9 Ignore Software ignores this bit ﬁeld.
12:10 SLP_TYPx Deﬁnes the type of sleeping or soft-off state the system enters when
the SLP_EN bit is set to one. This 3-bit ﬁeld deﬁnes the type of
hardware sleep state the system enters when the SLP_EN bit is set.
The _Sx object contains 3-bit binary values associated with the re-
spective sleeping state (as described by the object). OSPM takes the
two values from the _Sx object and programs each value into the
respective SLP_TYPx ﬁeld.
13 SLP_EN This is a write-only bit and reads to it always return a zero. Setting
this bit causes the system to sequence into the sleeping state asso-
ciated with the SLP_TYPx ﬁelds programmed with the values from
the _Sx object.
15:14 Reserved Reserved. This ﬁeld always returns zero.
4.8. ACPI Register Model 78Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
4.8.3.3 Power Management Timer (PM_TMR)
Register Location: <PM_TMR_BLK> System I/O or Memory Space
Attribute: Read-Only
Size: 32 bits
This optional read-only register returns the current value of the power management timer (PM timer) if it is imple-
mented on the platform. The FADT has a ﬂag called TMR_V AL_EXT that an OEM sets to indicate a 32-bit PM timer
or reset to indicate a 24-bit PM timer. When the last bit of the timer toggles the TMR_STS bit is set. This register is
accessed as 32 bits.
Table 4.14: PM Timer Bits

TMR_V AL 23:0 This read-only ﬁeld returns the running count of the power manage-
ment timer. This is a 24-bit counter that runs off a 3.579545-MHz
clock and counts while in the S0 working system state. The starting
value of the timer is undeﬁned, thus allowing the timer to be reset
(or not) by any transition to the S0 state from any other state. The
timer is reset (to any initial value), and then continues counting until
the system’s 14.31818 MHz clock is stopped upon entering its Sx
state. If the clock is restarted without a reset, then the counter will
continue counting from where it stopped.
E_TMR_V AL 31:24 This read-only ﬁeld returns the upper eight bits of a 32-bit power
management timer. If the hardware supports a 32-bit timer, then
this ﬁeld will return the upper eight bits; if the hardware supports a
24-bit timer then this ﬁeld returns all zeros.
4.8.3.4 PM2 Control (PM2_CNT)
Register Location: <PM2_CNT_BLK> System I/O, System Memory, or Functional
Fixed Hardware Space
Size: PM2_CNT_LEN
This register block is naturally aligned and accessed based on its length. For ACPI 1.0 this register is byte aligned and
accessed as a byte.
4.8. ACPI Register Model 79Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 4.15: PM2 Control Register Bits
0 ARB_DIS This bit is used to enable and disable the system arbiter. When this
bit is CLEAR the system arbiter is enabled and the arbiter can grant
the bus to other bus masters. When this bit is SET the system arbiter
is disabled and the default CPU has ownership of the system. OSPM
clears this bit when using the C0, C1 and C2 power states.
>0 Reserved Reserved
4.8.3.5 Processor Register Block (P_BLK)
This optional register block is used to control each processor in the system. There is one unique processor register
block per processor in the system. For more information about controlling processors and control methods that can be
used to control processors, see Processor Conﬁguration and Control This register block is DWORD aligned and the
context of this register block is not maintained across S3 or S4 sleeping states, or the S5 soft-off state.
4.8.3.5.1 Processor Control (P_CNT): 32
Register Location: Either <P_BLK>: System I/O Space
or speciﬁed by _PTC Object: System I/O, System Memory, or
Functional Fixed Hardware Space
This register is accessed as a DWORD. The CLK_V AL ﬁeld is where the duty setting of the throttling hardware is
programmed as described by the DUTY_WIDTH and DUTY_OFFSET values in the FADT. Software treats all other
CLK_V AL bits as ignored (those not used by the duty setting value).
Table 4.16: Processor Control Register Bits
3:0 CLK_V AL Possible locations for the clock throttling value.
4 THT_EN This bit enables clock throttling of the clock as set in the CLK_V AL
ﬁeld. THT_EN bit must be reset LOW when changing the
CLK_V AL ﬁeld (changing the duty setting).
31:5 CLK_V AL Possible locations for the clock throttling value.
4.8.3.5.2 Processor LVL2 Register (P_LVL2): 8
Register Location: Either <P_BLK> + 4: System I/O Space
or speciﬁed by _CST Object: System I/O, System Memory, or
Size: 8 bits
4.8. ACPI Register Model 80Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
This register is accessed as a byte.
Table 4.17: Processor LVL2 Register Bits
7:0 P_LVL2 Reads to this register return all zeros; writes to this register have
no effect. Reads to this register also generate an “enter a C2 power
state” to the clock control logic.
4.8.3.5.3 Processor LVL3 Register (P_LVL3): 8
Register Location: Either <P_BLK> + 5: System I/O Space
Table 4.18: Processor LVL3 Register Bits
7:0 P_LVL3 Reads to this register return all zeros; writes to this register have
no effect. Readsto this register also generate an “enter a C3 power
4.8.3.6 Reset Register
The optional ACPI reset mechanism speciﬁes a standard mechanism that provides a complete system reset. When
implemented, this mechanism must reset the entire system. This includes processors, core logic, all buses, and all
peripherals. From an OSPM perspective, asserting the reset mechanism is the logical equivalent to power cycling the
system. Upon gaining control after a reset, OSPM will perform actions in like manner to a cold boot.
The reset mechanism is implemented via an 8-bit register described by RESET_REG in the FADT (always accessed via
the natural alignment and size described in RESET_REG). To reset the system, software will write a value (indicated
in RESET_V ALUE in FADT) to the reset register. The RESET_REG ﬁeld in the FADT indicates the location of the
reset register.
The reset register may exist only in I/O space, Memory space, or in PCI Conﬁguration space on a function in bus 0.
Therefore, the Address_Space_ID value in RESET_REG must be set to System I/O space, System Memory space, or
PCI Conﬁguration space (with a bus number of 0). As the register is only 8 bits, Register_Bit_Width must be 8 and
Register_Bit_Offset must be 0.
The system must reset immediately following the write to this register. OSPM assumes that the processor will not
execute beyond the write instruction. OSPM should execute spin loops on the CPUs in the system following a write
to this register.
4.8. ACPI Register Model 81Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
4.8.3.7 Sleep Control and Status Registers
The optional ACPI sleep registers (SLEEP_CONTROL_REG and SLEEP_STATUS_REG) specify a standard mech-
anism for system sleep state entry on HW-Reduced ACPI systems. When implemented, the Sleep registers
are a replacement for the SLP_TYP, SLP_EN and WAK_STS registers in the PM1_BLK. Use of these regis-
ters is at the discretion of OSPM. OSPM can decide whether to enter sleep states on the platform based on the
LOW_POWER_S0_IDLE_CAPABLE ﬂag. Even when implemented, OSPM may use other provided options for
hibernate and shutdown (e.g. UEFI ResetSystem()).
The HW-reduced Sleep mechanism is implemented via two 8-bit registers described by SLEEP_CONTROL_REG
and SLEEP_STATUS_REG in the FADT (always accessed via the natural alignment and size described in
SLEEP_*_REG). To put the system into a sleep state, software will write the HW-reduced Sleep Type value (ob-
tained from the \_Sx object in the DSDT) and the SLP_EN bit to the sleep control register. The OSPM then polls
the WAK_STS bit of the SLEEP_STATUS_REG waiting for it to be one (1), indicating that the system has been
transitioned back to the Working state.
The Sleep registers may exist only in I/O space, Memory space, or in PCI Conﬁguration space on a function in bus 0.
Therefore, the Address_Space_ID value must be set to System I/O space, SystemMemory space, or PCI Conﬁguration
space (with a bus number of 0). As the registers are only 8 bits, Register_Bit_Width must be 8 and Register_Bit_Offset
must be 0.
Table 4.19: Sleep Control Register
Field
NameBit
LengthBit
Reserved 1 0 Reserved. This bit is reserved by OSPM.
Ignore 1 1 Software ignores this bit ﬁeld.
SLP_TYPx 3 2 Deﬁnes the type of sleeping state the system enters when the SLP_EN bit
is set to one. This 3-bit ﬁeld deﬁnes the type of hardware sleep state the
system enters when the SLP_EN bit is set. The _Sx object contains 3-bit
binary values associated with the respective sleeping state (as described by
the object). OSPM takes the HW-reduced Sleep Type value from the _SX
object and programs it into the SLP_TYPx ﬁeld.
SLP_EN 1 5 This is a write-only bit and reads to it always return a zero. Setting this
bit causes the system to sequence into the sleeping state associated with the
SLP_TYPx ﬁelds programmed with the values from the _Sx object.
Reserved 2 6 Reserved. This ﬁeld always returns zero.
Table 4.20: Sleep Status Register
Field Name Bit Length Bit Offset Description
Ignore 4 0 Software ignores this bit ﬁeld.
Reserved 2 4 Reserved. These bits always return a value of zero.
Ignore 1 6 Software ignores this bit ﬁeld.
WAK_STS 1 7 This bit is set when the system is in the sleeping state
and an enabled wake event occurs. Upon setting this
bit system will transition to the working state. This bit
is set by hardware and can only be cleared by software
4.8. ACPI Register Model 82Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
4.8.4 Generic Hardware Registers

ACPI provides a mechanism that allows a unique piece of “value added” hardware to be described to OSPM in the
ACPI Namespace. There are a number of rules to be followed when designing ACPI-compatible hardware.
Programming bits can reside in any of the deﬁned generic hardware address spaces (system I/O, system memory,
PCI conﬁguration, embedded controller, or SMBus), but the top-level event bits are contained in the general-purpose
event registers. The general-purpose event registers are pointed to by the GPE0_BLK and GPE1_BLK register blocks,
and the generic hardware registers can be in any of the deﬁned ACPI address spaces. A device’s generic hardware
programming model is described through an associated object in the ACPI Namespace, which speciﬁes the bit’s
function, location, address space, and address location.
The programming model for devices is normally broken into status and control functions. Status bits are used to
generate an event that allows OSPM to call a control method associated with the pending status bit. The called control
method can then control the hardware by manipulating the hardware control bits or by investigating child status bits
and calling their respective control methods. ACPI requires that the top level “parent” event status and enable bits
reside in either the GPE0_STS or GPE1_STS registers, and “child” event status bits can reside in generic address
space.
The example below illustrates some of these concepts. The top diagram shows how the logic is partitioned into two
chips: a chipset and an embedded controller.
• The chipset contains the interrupt logic, performs the power button (which is part of the ﬁxed register space, and
is not discussed here), the lid switch (used in portables to indicate when the clam shell lid is open or closed),
and the RI# function (which can be used to wake a sleeping system).
• The embedded controller chip is used to perform the AC power detect and dock/undock event logic. Addition-
ally, the embedded controller supports some system management functions using an OS-transparent interrupt in
the embedded controller (represented by the EXTSMI# signal).
At the top level, the generic events in the GPEx_STS register are the:
• Embedded controller interrupt, which contains two query events: one for AC detection and one for docking (the
docking query event has a child interrupt status bit in the docking chip).
• Ring indicate status (used for waking the system).
• Lid status.
The embedded controller event status bit (EC_STS) is used to indicate that one of two query events is active.
• A query event is generated when the AC# signal is asserted. The embedded controller returns a query value of
34 (any byte number can be used) upon a query command in response to this event; OSPM will then schedule
for execution the control method associated with query value 34.
Another query event is for the docking chip that generates a docking event. In this case, the embedded controller will
return a query value of 35 upon a query command from system software responding to an SCI from the embedded
controller. OSPM will then schedule the control method associated with the query value of 35 to be executed, which
services the docking event.
For each of the status bits in the GPEx_STS register, there is a corresponding enable bit in the GPEx_EN register.
Notice that the child status bits do not necessarily need enable bits (see the DOCK_STS bit).
The lid logic contains a control bit to determine if its status bit is set when the LID is open (LID_POL is set and LID
is set) or closed (LID_POL is clear and LID is clear). This control bit resides in generic I/O space (in this case, bit 2
of system I/O space 33h) and would be manipulated with a control method associated with the lid object.
As with ﬁxed hardware events, OSPM will clear the status bits in the GPEx register blocks. However, AML code
clears all sibling status bits in the generic hardware.
Generic hardware features are controlled by OEM supplied control methods, encoded in AML. ACPI provides both
an event and control model for development of these features. The ACPI speciﬁcation also provides speciﬁc control
4.8. ACPI Register Model 83Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 4.13: Example of General-Purpose vs. Generic Hardware Events
4.8. ACPI Register Model 84Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
methods for notifying OSPM of certain power management and Plug and Play events. ACPI Software Programming
Model provides information on the types of hardware functionality that support the different types of subsystems. The
following is a list of features supported by ACPI. The list is not intended to be complete or comprehensive.
• Device insertion/ejection (for example, docking, device bay, A/C adapter)
• Batteries *
• Platform thermal subsystem
• Turning on/off power resources
• Mobile lid Interface
• OEM-speciﬁc wake events
• Plug and Play conﬁguration
Note: * ACPI operating systems assume the use of the Smart Battery System Implementers Forum deﬁned standard
for batteries, called the “Smart Battery Speciﬁcation” (SBS). ACPI provides a set of control methods for use by OEMs
that use a proprietary “control method” battery interface.
4.8.4.1 General-Purpose Event Register Blocks
ACPI supports up to two general-purpose register blocks as described in the FADT (see ACPI Software Programming
Model ), and an arbitrary number of additional GPE blocks described as devices within the ACPI namespace. Each
register block contains two registers: an enable and a status register. Each register block is 32-bit aligned. Each register
in the block is accessed as a byte. It is up to the speciﬁc design to determine if these bits retain their context across
sleeping or soft-off states. If they lose their context across a sleeping or soft-off state, then platform boot ﬁrmware
resets the respective enable bit prior to passing control to the OS upon waking.
4.8.4.1.1 General-Purpose Event 0 Register Block
This register block consists of two registers: The GPE0_STS and the GPE0_EN registers. Each register’s length
is deﬁned to be half the length of the GPE0 register block, and is described in the ACPI FADT’s GPE0_BLK and
GPE0_BLK_LEN operators. OSPM owns the general-purpose event resources and these bits are only manipulated by
OSPM; AML code cannot access the general-purpose event registers.
It is envisioned that chipsets will contain GPE event registers that provide GPE input pins for various events.
The platform designer would then wire the GPEs to the various value-added event hardware and the AML code would
describe to OSPM how to utilize these events. As such, there will be the case where a platform has GPE events that
are not wired to anything (they are present in the chip set), but are not utilized by the platform and have no associated
AML code. In such, cases these event pins are to be tied inactive such that the corresponding SCI status bit in the GPE
register is not set by a ﬂoating input pin.
4.8. ACPI Register Model 85Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
4.8.4.1.1.1 General-Purpose Event 0 Status Register
Register Location: <GPE0_STS> System I/O or System Memory Space
Size: GPE0_BLK_LEN/2
The general-purpose event 0 status register contains the general-purpose event status bits in bank zero of the general-
purpose registers. Each available status bit in this register corresponds to the bit with the same bit position in the
GPE0_EN register. Each available status bit in this register is set when the event is active, and can only be cleared by
software writing a “1” to its respective bit position. For the general-purpose event registers, unimplemented bits are
ignored by OSPM.
Each status bit can optionally wake the system if asserted when the system is in a sleeping state with its respective
enable bit set. OSPM accesses GPE registers through byte accesses (regardless of their length).
4.8.4.1.1.2 General-Purpose Event 0 Enable Register
Register Location: <GPE0_EN> System I/O or System Memory Space
The general-purpose event 0 enable register contains the general-purpose event enable bits. Each available enable bit in
this register corresponds to the bit with the same bit position in the GPE0_STS register. The enable bits work similarly
to how the enable bits in the ﬁxed-event registers are deﬁned: When the enable bit is set, then a set status bit in the
corresponding status bit will generate an SCI bit. OSPM accesses GPE registers through byte accesses (regardless of
their length).
4.8.4.1.2 General-Purpose Event 1 Register Block
This register block consists of two registers: The GPE1_STS and the GPE1_EN registers. Each register’s length

is deﬁned to be half the length of the GPE1 register block, and is described in the ACPI FADT’s GPE1_BLK and
GPE1_BLK_LEN operators.
4.8.4.1.2.1 General-Purpose Event 1 Status Register
Register Location: <GPE1_STS> System I/O or System Memory Space
Size: GPE1_BLK_LEN/2
The general -purpose event 1 status register contains the general-purpose event status bits. Each available status bit in
this register corresponds to the bit with the same bit position in the GPE1_EN register. Each available status bit in this
register is set when the event is active, and can only be cleared by software writing a “1” to its respective bit position.
For the general-purpose event registers, unimplemented bits are ignored by the operating system.
enable bit set.
4.8. ACPI Register Model 86Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
OSPM accesses GPE registers through byte accesses (regardless of their length).
4.8.4.1.2.2 General-Purpose Event 1 Enable Register
Register Location: <GPE1_EN> System I/O or System Memory Space
The general-purpose event 1 enable register contains the general-purpose event enable. Each available enable bit
in this register corresponds to the bit with the same bit position in the GPE1_STS register. The enable bits work
similarly to how the enable bits in the ﬁxed-event registers are deﬁned: When the enable bit is set, a set status bit in
the corresponding status bit will generate an SCI bit.
4.8.4.2 Example Generic Devices
This section points out generic devices with speciﬁc ACPI driver support.
4.8.4.2.1 Lid Switch
The Lid switch is an optional feature present in most “clam shell” style mobile computers. It can be used by the OS
as policy input for sleeping the system, or for waking the system from a sleeping state. If used, then the OEM needs
to deﬁne the lid switch as a device with an _HID object value of “PNP0C0D”, which identiﬁes this device as the lid
switch to OSPM. The Lid device needs to contain a control method that returns its status. The Lid event handler AML
code reconﬁgures the lid hardware (if it needs to) to generate an event in the other direction, clear the status, and then
notify OSPM of the event.
Example hardware and ASL code is shown below for such a design.
Fig. 4.14: Example Generic Address Space Lid Switch Logic
This logic will set the Lid status bit when the button is pressed or released (depending on the LID_POL bit).
The ASL code below deﬁnes the following:
• An operational region where the lid polarity resides in address space System address space in registers 0x201.
• A ﬁeld operator to allow AML code to access this bit: Polarity control bit (LID_POL) is called LPOL and is
accessed at 0x201.0.
• A device named \_SB.LID with the following:
4.8. ACPI Register Model 87Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• A Plug and Play identiﬁer “PNP0C0D” that associates OSPM with this object.
• Deﬁnes an object that speciﬁes a change in the lid’s status bit can wake the system from the S4 sleep state and
from all higher sleep states (S1, S2, or S3).
• The lid switch event handler that does the following:
• Deﬁnes the lid status bit (LID_STS) as a child of the general-purpose event 0 register bit 1.
• Deﬁnes the event handler for the lid (only event handler on this status bit) that does the following:
• Flips the polarity of the LPOL bit (to cause the event to be generated on the opposite condition).
• Generates a notify to the OS that does the following:
• Passes the \_SB.LID object.
• Indicates a device speciﬁc event (notify value 0x80).
// Define a Lid switch
OperationRegion (\PHO, SystemIO, 0x201, 0x1)
Field (\PHO, ByteAcc, NoLock, Preserve)
{
LPOL, 1 // Lid polarity control bit
}
Device (\_SB.LID)
{
Name (_HID, EISAID ("PNP0C0D"))
Method (_LID)
{
Return(LPOL)
}
Name (_PRW, Package (2){
1, // bit 1 of GPE to enable Lid wakeup
0x04}) // can wakeup from S4 state
}
Scope(\_GPE)
{
Method(_L01) // uses bit 1 of GP0_STS register
{
LPOL ~= LPOL // Flip the lid polarity bit
Notify (\_SB.LID, 0x80) // Notify OS of event
}
}
4.8.4.2.2 Embedded Controller
ACPI provides a standard interface that enables AML code to deﬁne and access generic logic in “embedded controller
space.” This supports current computer models where much of the value added hardware is contained within the
embedded controller while allowing the AML code to access this hardware in an abstracted fashion.
• The embedded controller is deﬁned as a device and must contain a set number of control methods:
• _HID with a value of PNP0C09 to associate this device with the ACPI’s embedded controller’s driver.
• _CRS to return the resources being consumed by the embedded controller.
• _GPE that returns the general-purpose event bit that this embedded controller is wired to.
4.8. ACPI Register Model 88Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Additionally the embedded controller can support up to 255 generic events per embedded controller, referred to as
query events. These query event handles are deﬁned within the embedded controller’s device as control methods. An
example of deﬁning an embedded controller device is shown below:
Device(EC0) {
// PnP ID
Name(_HID, EISAID("PNP0C09"))
// Returns the "Current Resources" of EC
Name (_CRS, ResourceTemplate()
{
IO(Decode16, 0x62, 0x62, 0, 1)
IO(Decode16, 0x66, 0x66, 0, 1)
})
// Indicate that the EC SCI is bit 0 of the GP_STS register
Name (_GPE, 0) // embedded controller is wired to bit 0 of GPE
OperationRegion (\EC0, EmbeddedControl, 0, 0xFF)
Field (EC0, ByteAcc, Lock, Preserve)
{
// Field units of EC0
}
// Query methods
Method(_Q00)
{ ... }
Method(_QFF)
{ ... }
}
For more information on the embedded controller, see ACPI Embedded Controller Interface Speciﬁcation
4.8.4.2.3 Fan
ACPI has a device driver to control fans (active cooling devices) in platforms. A fan is deﬁned as a device with the
Plug and Play ID of “PNP0C0B.” It should then contain a list power resources used to control the fan.
For more information, see ACPI-Deﬁned Devices and Device-Speciﬁc Objects .
LA2PA_TRANSLATION .. highlight:: none
4.8. ACPI Register Model 89CHAPTER
FIVE
ACPI SOFTWARE PROGRAMMING MODEL
ACPI deﬁnes a hardware register interface that an ACPI-compatible OS uses to control core power management
features of a machine, as described in ACPI Hardware Speciﬁcation ACPI also provides an abstract interface for
controlling the power management and conﬁguration of an ACPI system. Finally, ACPI deﬁnes an interface between
an ACPI-compatible OS and the platform runtime ﬁrmware.
To give hardware vendors ﬂexibility in choosing their implementation, ACPI uses tables to describe system informa-
tion, features, and methods for controlling those features. These tables list devices on the system board or devices that
cannot be detected or power managed using some other hardware standard, plus their capabilities as described in ACPI
Concepts They also list system capabilities such as the sleeping power states supported, a description of the power
planes and clock sources available in the system, batteries, system indicator lights, and so on. This enables OSPM to
control system devices without needing to know how the system controls are implemented.
Topics covered in this section are:
• The ACPI system description table architecture is deﬁned, and the role of OEM-provided deﬁnition blocks in
that architecture is discussed.
• The concept of the ACPI Namespace is discussed.
5.1 Overview of the System Description Table Architecture
TheRoot System Description Pointer (RSDP) structure is located in the system’s memory address space and is setup by
the platform ﬁrmware. This structure contains the address of the Extended System Description Table (XSDT) , which
references other description tables that provide data to OSPM, supplying it with knowledge of the base system’s
implementation and conﬁguration (see Root System Description Pointer and Table ).
All system description tables start with identical headers. The primary purpose of the system description tables is to
deﬁne for OSPM various industry-standard implementation details. Such deﬁnitions enable various portions of these
implementations to be ﬂexible in hardware requirements and design, yet still provide OSPM with the knowledge it
needs to control hardware directly.
TheExtended System Description Table (XSDT) points to other tables in memory. Always the ﬁrst table, it points to
theFixed ACPI Description Table (FADT) . The data within this table includes various ﬁxed-length entries that describe
the ﬁxed ACPI features of the hardware. The FADT table always refers to the Differentiated System Description Table

(DSDT) , which contains information and descriptions for various system features. The relationship between these
tables is shown in Description Table Structures .
OSPM ﬁnds the RSDP structure as described in Finding the RSDP on IA-PC Systems (“Finding the RSDP on IA-PC
Systems”) or Finding the RSDP on UEFI Enabled Systems (“Finding the RSDP on UEFI Enabled Systems”).
When OSPM locates the structure, it looks at the physical address for the Root System Description Table or the Ex-
tended System Description Table. The Root System Description Table starts with the signature “RSDT”, while the
Extended System Description Table starts with the signature “XSDT”. These tables contain one or more physical
90Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 5.1: Root System Description Pointer and Table
Fig. 5.2: Description Table Structures
5.1. Overview of the System Description Table Architecture 91Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
pointers to other system description tables that provide various information about the system. As shown in Descrip-
tion Table Structures , there is always a physical address in the Root System Description Table for the Fixed ACPI
Description Table (FADT) .
When OSPM follows a physical pointer to another table, it examines each table for a known signature. Based on the
signature, OSPM can then interpret the implementation-speciﬁc data within the description table.
The purpose of the FADT is to deﬁne various static system information related to conﬁguration and power manage-
ment. The Fixed ACPI Description Table starts with the “FACP” signature. The FADT describes the implementation
and conﬁguration details of the ACPI hardware registers on the platform.
For a speciﬁcation of the ACPI Hardware Register Blocks (PM1a_EVT_BLK, PM1b_EVT_BLK, PM1a_CNT_BLK,
PM1b_CNT_BLK, PM2_CNT_BLK, PM_TMR_BLK, GP0_BLK, GP1_BLK, and one or more P_BLKs), see ACPI
Register Model The PM1a_EVT_BLK, PM1b_EVT_BLK, PM1a_CNT_BLK, PM1b_CNT_BLK, PM2_CNT_BLK,
and PM_TMR_BLK blocks are for controlling low-level ACPI system functions.
The GPE0_BLK and GPE1_BLK blocks provide the foundation for an interrupt-processing model for Control Meth-
ods. The P_BLK blocks are for controlling processor features.
Besides ACPI Hardware Register implementation information, the FADT also contains a physical pointer to a data
structure known as the Differentiated System Description Table (DSDT) , which is encoded in Deﬁnition Block format
(See Deﬁnition Blocks ).
A Deﬁnition Block contains information about the platform’s hardware implementation details in the form of data
objects arranged in a hierarchical (tree-structured) entity known as the “ACPI namespace”, which represents the plat-
form’s hardware conﬁguration. All deﬁnition blocks loaded by OSPM combine to form one namespace that represents
the platform. Data objects are encoded in a format known as ACPI Machine Language or AML for short. Data objects
encoded in AML are “evaluated” by an OSPM entity known as the AML interpreter. Their values may be static or
dynamic. The AML interpreter’s dynamic data object evaluation capability includes support for programmatic evalua-
tion, including accessing address spaces (for example, I/O or memory accesses), calculation, and logical evaluation, to
determine the result. Dynamic namespace objects are known as “control methods”. OSPM “loads” an entire deﬁnition
block as a logical unit - adding to or removing the associated objects from the namespace. The DSDT contains a Def-
inition Block named the Differentiated Deﬁnition Block that contains implementation and conﬁguration information
OSPM can use to perform power management, thermal management, or Plug and Play functionality that goes beyond
the information described by the ACPI hardware registers.
Deﬁnition Blocks can either deﬁne new system attributes or, in some cases, build on prior deﬁnitions. A Deﬁnition
Block can be loaded from system memory address space. One use of a Deﬁnition Block is to describe and distribute
platform version changes.
Deﬁnition blocks enable wide variations of hardware platform implementations to be described to the ACPI-
compatible OS while conﬁning the variations to reasonable boundaries. Deﬁnition blocks enable simple platform
implementations to be expressed by using a few well-deﬁned object names. In theory, it might be possible to deﬁne
a PCI conﬁguration space-like access method within a Deﬁnition Block, by building it from I/O space, but that is not
the goal of the Deﬁnition Block speciﬁcation. Such a space is usually deﬁned as a “built in” operator.
Some operators perform simple functions and others encompass complex functions. The power of the Deﬁnition Block
comes from its ability to allow these operations to be glued together in numerous ways, to provide functionality to
OSPM. The operators present are intended to allow many useful hardware designs to be ACPI-expressed, not to allow
all hardware designs to be expressed.
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5.1.1 Address Space Translation
Some platforms may contain bridges that perform translations as I/O and/or Memory cycles pass through the bridges.
This translation can take the form of the addition or subtraction of an offset. Or it can take the form of a conversion
from I/O cycles into Memory cycles and back again. When translation takes place, the addresses placed on the
processor bus by the processor during a read or write cycle are not the same addresses that are placed on the I/O bus by
the I/O bus bridge. The address the processor places on the processor bus will be known here as the processor-relative
address. And the address that the bridge places on the I/O bus will be known as the bus-relative address. Unless
otherwise noted, all addresses used within this section are processor-relative addresses.
For example, consider a platform with two root PCI buses. The platform designer has several choices. One solution
would be to split the 16-bit I/O space into two parts, assigning one part to the ﬁrst root PCI bus and one part to the
second root PCI bus. Another solution would be to make both root PCI buses decode the entire 16-bit I/O space,
mapping the second root PCI bus’s I/O space into memory space. In this second scenario, when the processor needs
to read from an I/O register of a device underneath the second root PCI bus, it would need to perform a memory read
within the range that the root PCI bus bridge is using to map the I/O space.
• Industry standard PCs do not provide address space translations because of historical compatibility issues.
5.2 ACPI System Description Tables
This section speciﬁes the structure of the system description tables:
•Generic Address Structure (GAS)
•GIC CPU Interface (GICC) Structure
•System Locality Information Table (SLIT)
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•Platform Memory Topology Table (PMTT)
•NVDIMM Firmware Interface Table (NFIT)
•Heterogeneous Memory Attribute Table (HMAT)
•Platform Debug Trigger Table (PDTT)
•Processor Properties Topology Table (PPTT)
All numeric values in ACPI-deﬁned tables, blocks, and structures are always encoded in little endian format. Signature
values are stored as ﬁxed-length strings.
5.2.1 Reserved Bits and Fields
For future expansion, all data items marked as reserved in this speciﬁcation have strict meanings. This section lists
software requirements for reserved ﬁelds. Notice that the list contains terms such as ACPI tables and AML code
deﬁned later in this section of the speciﬁcation.
5.2.1.1 Reserved Bits and Software Components
• OEM implementations of software and AML code return the bit value of 0 for all reserved bits in ACPI tables
or in other software values, such as resource descriptors.
• For all reserved bits in ACPI tables and registers, OSPM implementations must:
• Ignore all reserved bits that are read.
• Preserve reserved bit values of read/write data items (for example, OSPM writes back reserved bit values it
reads).

reads).
• Write zeros to reserved bits in write-only data items.
5.2.1.2 Reserved Values and Software Components
• OEM implementations of software and AML code return only deﬁned values and do not return reserved values.
• OSPM implementations write only deﬁned values and do not write reserved values.
5.2.1.3 Reserved Hardware Bits and Software Components
• Software ignores all reserved bits read from hardware enable or status registers.
• Software writes zero to all reserved bits in hardware enable registers.
• Software ignores all reserved bits read from hardware control and status registers.
• Software preserves the value of all reserved bits in hardware control registers by writing back read values.
5.2. ACPI System Description Tables 94Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.1.4 Ignored Hardware Bits and Software Components
• Software handles ignored bits in ACPI hardware registers the same way it handles reserved bits in these same
types of registers.
5.2.2 Compatibility
All versions of the ACPI tables must maintain backward compatibility. To accomplish this, modiﬁcations of the tables
consist of redeﬁnition of previously reserved ﬁelds and values plus appending data to the 1.0 tables. Modiﬁcations of
the ACPI tables require that the version numbers of the modiﬁed tables be incremented. The length ﬁeld in the tables
includes all additions and the checksum is maintained for the entire length of the table.
5.2.3 Address Format
Addresses used in the ACPI 1.0 system description tables were expressed as either system memory or I/O space. This
was targeted at the IA-32 environment. Newer architectures require addressing mechanisms beyond that deﬁned in
ACPI 1.0. To support these architectures ACPI must support 64-bit addressing and it must allow the placement of
control registers in address spaces other than System I/O.
5.2.3.1 Functional Fixed Hardware
ACPI deﬁnes the ﬁxed hardware low-level interfaces as a means to convey to the system OEM the minimum interfaces
necessary to achieve a level of capability and quality for motherboard conﬁguration and system power management.
Additionally, the deﬁnition of these interfaces, as well as others deﬁned in this speciﬁcation, conveys to OS Ven-
dors (OSVs) developing ACPI-compatible operating systems, the necessary interfaces that operating systems must
manipulate to provide robust support for system conﬁguration and power management.
While the deﬁnition of low-level hardware interfaces deﬁned by ACPI 1.0 afforded OSPM implementations a certain
level of stability, controls for existing and emerging diverse CPU architectures cannot be accommodated by this model
as they can require a sequence of hardware manipulations intermixed with native CPU instructions to provide the
ACPI-deﬁned interface function. In this case, an ACPI-deﬁned ﬁxed hardware interface can be functionally imple-
mented by the CPU manufacturer through an equivalent combination of both hardware and software and is deﬁned by
ACPI as Functional Fixed Hardware.
In IA-32-based systems, functional ﬁxed hardware can be accommodated in an OS independent manner by using
System Management Mode (SMM) based system ﬁrmware. Unfortunately, the nature of SMM-based code makes this
type of OS independent implementation difﬁcult if not impossible to debug. As such, this implementation approach is
not recommended. In some cases, Functional Fixed Hardware implementations may require coordination with other
OS components. As such, an OS independent implementation may not be viable.
OS-speciﬁc implementations of functional ﬁxed hardware can be implemented using technical information supplied
by the CPU manufacturer. The downside of this approach is that functional ﬁxed hardware support must be developed
for each OS. In some cases, the CPU manufacturer may provide a software component providing this support. In other
cases support for the functional ﬁxed hardware may be developed directly by the OS vendor.
The hardware register deﬁnition was expanded, in ACPI 2.0, to allow registers to exist in address spaces other than
the System I/O address space. This is accomplished through the speciﬁcation of an address space ID in the register
deﬁnition (see Generic Address Structure for more information). When speciﬁcally directed by the CPU manufacturer,
the system ﬁrmware may deﬁne an interface as functional ﬁxed hardware by indicating 0x7F (Functional Fixed Hard-
ware), in the address space ID ﬁeld for register deﬁnitions. It is emphasized that functional ﬁxed hardware deﬁnitions
may be declared in the ACPI system ﬁrmware only as indicated by the CPU Manufacturer for speciﬁc interfaces as
the use of functional ﬁxed hardware requires speciﬁc coordination with the OS vendor.
5.2. ACPI System Description Tables 95Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Only certain ACPI-deﬁned interfaces may be implemented using functional ﬁxed hardware and only when the in-
terfaces are common across machine designs for example, systems sharing a common CPU architecture that does
not support ﬁxed hardware implementation of an ACPI-deﬁned interface. OEMs are cautioned not to anticipate that
functional ﬁxed hardware support will be provided by OSPM differently on a system-by-system basis. The use of
functional ﬁxed hardware carries with it a reliance on OS speciﬁc software that must be considered. OEMs should
consult OS vendors to ensure that speciﬁc functional ﬁxed hardware interfaces are supported by speciﬁc operating
systems.
• FFH is permitted and applicable to both full and HW-reduced ACPI implementations.
5.2.3.2 Generic Address Structure
The Generic Address Structure (GAS) provides the platform with a robust means to describe register locations. This
structure, described below ( Generic Address Structure (GAS) ), is used to express register addresses within tables
deﬁned by ACPI .
Table 5.1: Generic Address Structure (GAS)
Field Byte
Address
Space ID1 0
The address space where the data structure or register exists. Deﬁned
values are:
0x00 System Memory space
0x01 System I/O space
0x02 PCI Conﬁguration space
0x03 Embedded Controller
0x04 SMBus
0x05 SystemCMOS
0x06 PciBarTarget
0x07 IPMI
0x08 General PurposeIO
0x09 GenericSerialBus
0x0A Platform Communications Channel (PCC)
0x0B Platform Runtime Mechanism (PRM)
0x0C to 0x7E Reserved
0x7F Functional Fixed Hardware
0x80 to 0xFF OEM Deﬁned
Register Bit
Width1 1 The size in bits of the given register. When addressing a data structure,
this ﬁeld must be zero.
Offset1 2 The bit offset of the given register at the given address. When addressing
a data structure, this ﬁeld must be zero.
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Field Byte
Access Size 1 3
Speciﬁes access size. Unless otherwise deﬁned by the Address Space ID:
0 Undeﬁned (legacy reasons)
1 Byte access
2 Word access
3 Dword access
4 QWord access
Address 8 4 The 64-bit address of the data structure or register in the given address
space (relative to the processor). (See below for speciﬁc formats.)
Table 5.2: Address Space Format
Address Space Format
0-System Memory The 64-bit physical memory address (relative to the processor) of the register. 32-bit plat-
forms must have the high DWORD set to 0.
1-System I/O The 64-bit I/O address (relative to the processor) of the register. 32-bit platforms must have
the high DWORD set to 0.
2-PCI Conﬁguration
Space PCI Conﬁguration space addresses must be conﬁned to devices on PCI Segment Group 0,
bus 0. This restriction exists to accommodate access to ﬁxed hardware prior to PCI bus
enumeration. The format of addresses are deﬁned as follows:
Word Location Description
Highest Word Reserved (must be 0)
— PCI Device number on bus 0
— PCI Function number
Longest Word Offset in the conﬁguration space header
For example: Offset 23h of Function 2 on device 7 on bus 0 segment 0 would be
represented as: 0x0000000700020023.
6-PCI BAR Target
PciBarTarget is used to locate a MMIO register on a PCI device BAR space. PCI
Conﬁguration space addresses must be conﬁned to devices on a host bus, i.e any bus
returned by a _BBN object. This restriction exists to accommodate access to ﬁxed
hardware prior to PCI bus enumeration. The format of the Address ﬁeld for this type of
address is:
Bits [63:56] – PCI Segment
Bits [55:48] – PCI Bus
Bits [47:43] – PCI Device
Bits [42:40] – PCI Function
Bits [39:37] – BAR index#
Bits [36:0] – Offset from BAR in DWORDs
0x0A-PCC {Deﬁnition needed}
5.2. ACPI System Description Tables 97Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.2 – continued from previous page
0x7F-Functional
Fixed HardwareUse of GAS ﬁelds other than Address_Space_ID is speciﬁed by the CPU manufacturer. The

use of functional ﬁxed hardware carries with it a reliance on OS speciﬁc software that must
be considered. OEMs should consult OS vendors to ensure that speciﬁc functional ﬁxed
hardware interfaces are supported by speciﬁc operating systems.
5.2.4 Universally Unique Identiﬁers (UUIDs)
UUIDs (Universally Unique IDentiﬁers), also known as GUIDs (Globally Unique IDentiﬁers) are 128 bit long values
that extremely likely to be different from all other UUIDs generated until 3400 A.D. UUIDs are used to distinguish
between callers of ASL methods, such as _DSM and _OSC. UUIDs are also used to distinguish individual entries in
the MISC table.
The format of both the binary and string representations of UUIDs, along with an algorithm to generate them, is
speciﬁed in ISO/IEC 11578:1996 Information technology - Open Systems Interconnection - Remote Procedure Call
(RPC). This can also be found as part of the DCE 1.1: Remote Procedure Call technical standard, and in the Wikipedia
entry for UUIDs.
5.2.5 Root System Description Pointer (RSDP)
During OS initialization, OSPM must obtain the Root System Description Pointer (RSDP) structure from the plat-
form. When OSPM locates the Root System Description Pointer (RSDP) structure, it then locates the Root System
Description Table (RSDT) or the Extended Root System Description Table (XSDT) using the physical system address
supplied in the RSDP.
5.2.5.1 Finding the RSDP on IA-PC Systems
OSPM ﬁnds the Root System Description Pointer (RSDP) structure by searching physical memory ranges on 16-byte
boundaries for a valid Root System Description Pointer structure signature and checksum match as follows:
• The ﬁrst 1 KB of the Extended BIOS Data Area (EBDA). For EISA or MCA systems, the EBDA can be found
in the two-byte location 40:0Eh on the BIOS data area.
• The BIOS read-only memory space between 0E0000h and 0FFFFFh.
5.2.5.2 Finding the RSDP on UEFI Enabled Systems
In Uniﬁed Extensible Firmware Interface (UEFI) enabled systems, a pointer to the RSDP structure exists within the
EFI System Table. The OS loader is provided a pointer to the EFI System Table at invocation. The OS loader must
retrieve the pointer to the RSDP structure from the EFI System Table and convey the pointer to OSPM, using an OS
dependent data structure, as part of the hand off of control from the OS loader to the OS.
The OS loader locates the pointer to the RSDP structure by examining the EFI Conﬁguration Table within the EFI
System Table. EFI Conﬁguration Table entries consist of Globally Unique Identiﬁer (GUID)/table pointer pairs. The
UEFI speciﬁcation deﬁnes two GUIDs for ACPI; one for ACPI 1.0 and the other for ACPI 2.0 or later speciﬁcation
revisions.
The EFI GUID for a pointer to the ACPI 1.0 speciﬁcation RSDP structure is:
• eb9d2d30-2d88-11d3-9a16-0090273fc14d.
The EFI GUID for a pointer to the ACPI 2.0 or later speciﬁcation RSDP structure is:
• 8868e871-e4f1-11d3-bc22-0080c73c8881.
5.2. ACPI System Description Tables 98Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The OS loader for an ACPI-compatible OS will search for an RSDP structure pointer ( RSDP Structure ) using the
current revision GUID ﬁrst and if it ﬁnds one, will use the corresponding RSDP structure pointer. If the GUID is not
found then the OS loader will search for the RSDP structure pointer using the ACPI 1.0 version GUID.
The OS loader must retrieve the pointer to the RSDP structure from the EFI System Table before assuming platform
control via the EFI ExitBootServices interface. See the UEFI Speciﬁcation for more information.
5.2.5.3 Root System Description Pointer (RSDP) Structure
The revision number contained within the structure indicates the size of the table structure.
Table 5.3: RSDP Structure
Field Byte
Signature 8 0 “RSD PTR ” (Notice that this signature must contain a trailing
blank character.)
Checksum 1 8 This is the checksum of the ﬁelds deﬁned in the ACPI 1.0 spec-
iﬁcation. This includes only the ﬁrst 20 bytes of this table, bytes
0 to 19, including the checksum ﬁeld. These bytes must sum to
zero.
OEMID 6 9 An OEM-supplied string that identiﬁes the OEM.
Revision 1 15 The revision of this structure. Larger revision numbers are back-
ward compatible to lower revision numbers. The ACPI version
1.0 revision number of this table is zero. The ACPI version 1.0
RSDP Structure only includes the ﬁrst 20 bytes of this table, bytes
0 to 19. It does not include the Length ﬁeld and beyond. The cur-
rent value for this ﬁeld is 2.
RsdtAddress 4 16 32 bit physical address of the RSDT.
Length* 4 20 The length of the table, in bytes, including the header, starting
from offset 0. This ﬁeld is used to record the size of the entire
table. This ﬁeld is not available in the ACPI version 1.0 RSDP
Structure.
XsdtAddress* 8 24 64 bit physical address of the XSDT.
Extended
Checksum*1 32 This is a checksum of the entire table, including both checksum
ﬁelds.
Reserved* 3 33 Reserved ﬁeld
* These ﬁelds are only valid when the Revision value is 2 or above.
5.2.6 System Description Table Header
All system description tables begin with the structure shown in the DESCRIPTION_HEADER Fields . The Signature
ﬁeld in this table determines the content of the system description table. Also see Table 5.5.
5.2. ACPI System Description Tables 99Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.4: DESCRIPTION_HEADER Fields
Field Byte
Signature 4 0 The ASCII string representation of the table identiﬁer.
Note that if OSPM ﬁnds a signature in a table that is
not listed in Table 5.5, then OSPM ignores the entire
table (it is not loaded into ACPI namespace); OSPM
ignores the table even though the values in the Length
and Checksum ﬁelds are correct.
Length 4 4 The length of the table, in bytes, including the header,
starting from offset 0. This ﬁeld is used to record the
size of the entire table.
Revision 1 8 The revision of the structure corresponding to the sig-
nature ﬁeld for this table. Larger revision numbers are
backward compatible to lower revision numbers with
the same signature.
Checksum 1 9 The entire table, including the checksum ﬁeld, must
add to zero to be considered valid.
OEMID 6 10 An OEM-supplied string that identiﬁes the OEM.
OEM Table ID 8 16 An OEM-supplied string that the OEM uses to identify
the particular data table. This ﬁeld is particularly useful
when deﬁning a deﬁnition block to distinguish deﬁni-
tion block functions. The OEM assigns each dissimilar
table a new OEM Table ID.
OEM Revision 4 24 An OEM-supplied revision number. Larger numbers
are assumed to be newer revisions.
Creator ID 4 28 Vendor ID of utility that created the table. For tables
containing Deﬁnition Blocks, this is the ID for the ASL
Compiler.
Creator Revision 4 32 Revision of utility that created the table. For tables
containing Deﬁnition Blocks, this is the revision for
the ASL Compiler.
For OEMs, good design practices will ensure consistency when assigning OEMID and OEM Table ID ﬁelds in any
table. The intent of these ﬁelds is to allow for a binary control system that support services can use. Because many
support functions can be automated, it is useful when a tool can programmatically determine which table release is a
compatible and more recent revision of a prior table on the same OEMID and OEM Table ID.
Table 5.5 and Table 5.6 contain the system description table signatures deﬁned by this speciﬁcation. These system
description tables may be deﬁned by ACPI and documented within this speciﬁcation, or they may simply be reserved
by ACPI and deﬁned by other industry speciﬁcations. This allows OS and platform speciﬁc tables to be deﬁned and
pointed to by the RSDT/XSDT as needed. For tables deﬁned by other industry speciﬁcations, the ACPI speciﬁcation
acts as gatekeeper to avoid collisions in table signatures.
Table signatures will be reserved by the ACPI promoters and posted independently of this speciﬁcation in ACPI errata
and clariﬁcation documents on the ACPI web site. Requests to reserve a 4-byte alphanumeric table signature should be
sent to the email address info@acpi.info and should include the purpose of the table and reference URL to a document
that describes the table format. Tables deﬁned outside of the ACPI speciﬁcation may deﬁne data value encodings in
either little endian or big endian format. For the purpose of clarity, external table deﬁnition documents should include
the endian-ness of their data value encodings.
Since reference URLs can change over time and may not always be up-to-date in this speciﬁcation, a separate document
containing the latest known reference URLs can be found at “Links to ACPI-Related Documents” ( http://ueﬁ.org/acpi
5.2. ACPI System Description Tables 100Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
), which should conspicuously be placed in the same location as this speciﬁcation.

Table 5.5: DESCRIPTION_HEADER Signatures for tables deﬁned
by ACPI
Signature Description Reference
“APIC” Multiple APIC Description Table Section 5.2.12
“BERT” Boot Error Record Table Section 18.3.1
“BGRT” Boot Graphics Resource Table Section 5.2.23
“CCEL” Virtual Firmware Conﬁdential Com-
puting Event Log Table . See Links
to ACPI-Related Documents under the
heading “Virtual Firmware Conﬁdential
Computing Event Log Table”.
“CPEP” Corrected Platform Error Polling Table Section 5.2.18
“DSDT” Differentiated System Description Table Section 5.2.11.1
“ECDT” Embedded Controller Boot Resources
TableSection 5.2.15
“EINJ” Error Injection Table Section 18.6.1
“ERST” Error Record Serialization Table Section 18.5
“FACP” Fixed ACPI Description Table (FADT) Section 5.2.9
“FACS” Firmware ACPI Control Structure Section 5.2.10
“FPDT” Firmware Performance Data Table Section 5.2.24
“GTDT” Generic Timer Description Table Section 5.2.25
“HEST” Hardware Error Source Table Section 18.3.2
“MISC” Miscellaneous GUIDed Table Entries Section 5.2.33
“MSCT” Maximum System Characteristics Table Section 5.2.19
“MPST” Memory Power StateTable Section 5.2.22
“NFIT” NVDIMM Firmware Interface Table Section 5.2.26
“OEMx” OEM Speciﬁc Information Tables OEM Speciﬁc tables. All table signa-
tures starting with “OEM” are reserved
for OEM use.
“PCCT” Platform Communications Channel Ta-
bleSection 14.1
“PHAT” Platform Health Assessment Table Section 5.2.31
“PMTT” Platform Memory Topology Table Section 5.2.22.12
“PPTT” Processor Properties Topology Table Section 5.2.30
“PSDT” Persistent System Description Table Section 5.2.11.3
“RASF” ACPI RAS Feature Table Section 5.2.20
“RAS2” ACPI RAS2 Feature Table Section 5.2.21
“RSDT” Root System Description Table Section 5.2.7
“SBST” Smart Battery Speciﬁcation Table Section 5.2.14
“SDEV” Secure DEVices Table Section 5.2.27
“SLIT” System Locality Distance Information
TableSection 5.2.17
“SRAT” System Resource Afﬁnity Table Section 5.2.16
“SSDT” Secondary System Description Table Section 5.2.11.2
“SVKL” Storage Volume Key Data table in the
Intel Trusted Domain Extensions. See
Links to ACPI-Related Documents under
the heading “Storage V olume Key Data”.
“XSDT” Extended System Description Table Section 5.2.8
5.2. ACPI System Description Tables 101Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.6: DESCRIPTION_HEADER Signatures for tables reserved
by ACPI
Signature Description and External Reference
“AEST” Arm Error Source Table . See Links to ACPI-Related Documents under the heading
“Arm Error Source Table”.
“AGDI” Arm Generic Diagnostic Dump and Reset Interface . See Links to ACPI-Related
Documents under the heading “Arm Generic Diagnostic Dump and Reset Interface”.
“APMT” Arm Performance Monitoring Unit table . See Links to ACPI-Related Documents
under the heading “Arm Performance Monitoring Unit table”.
“BDAT” BIOS Data ACPI Table – exposing platform margining data . See Links to ACPI-
Related Documents under the heading “BIOS Data ACPI Table”.
“BOOT” Reserved Signature
“CEDT” CXL Early Discovery Table . See “Links to ACPI-Related Documents” (http://ueﬁ.
org/acpi) under the heading “CXL Early Discovery Table”.
“CSRT” Core System Resource Table . See Links to ACPI-Related Documents under the head-
ing “Core System Resource Table”.
“DBGP” Debug Port Table . See Links to ACPI-Related Documents under the heading “Debug
Port Table”.
“DBG2” Debug Port Table 2 . See Links to ACPI-Related Documents under the heading “De-
bug Port Table 2”.
“DMAR” DMA Remapping Table . See Links to ACPI-Related Documents under the heading
“DMA Remapping Table”.
“DRTM” Dynamic Root of Trust for Measurement Table . See Links to ACPI-Related Docu-
ments under the heading “TCG D-RTM Architecture Speciﬁcation”.
“DTPR” DMA TXT Protected Range . See Links to ACPI-Related Documents under the head-
ing “DMA TXT Protected Range”.
“ETDT” Event Timer Description Table (Obsolete) . IA-PC Multimedia Timers Speciﬁcation.
This signature has been superseded by “HPET” (below) and is now obsolete.
“HPET” IA-PC High Precision Event Timer Table . See Links to ACPI-Related Documents
under the heading “IA-PC High Precision Event Timer Table”.
“IBFT” iSCSI Boot Firmware Table . See Links to ACPI-Related Documents under the head-
ing “iSCSI Boot Firmware Table”.
“IERS” Inline Encryption Reporting Structure. See Links to ACPI-Related Documents under
the heading “Inline Encryption Reporting Structure”
“IORT” I/O Remapping Table . See Links to ACPI-Related Documents under the heading
“I/O Remapping Table”.
“IVRS” I/O Virtualization Reporting Structure . See Links to ACPI-Related Documents un-
der the heading “I/O Virtualization Reporting Structure”.
“KEYP” Key Programming Interface for Root Complex Integrity and Data Encryption
(IDE) . See Links to ACPI-Related Documents under the heading “Key Programming
Interface for Root Complex Integrity and Data Encryption (IDE)”.
“LPIT” Low Power Idle Table . See Links to ACPI-Related Documents under the heading
“Low Power Idle Table”.
“MCFG” PCI Express Memory-mapped Conﬁguration Space base address description table.
PCI Firmware Speciﬁcation, Revision 3.0. See Links to ACPI-Related Documents
under the heading “PCI Sig”.
“MCHI” Management Controller Host Interface table . DSP0256 Management Component
Transport Protocol (MCTP) Host Interface Speciﬁcation. See Links to ACPI-Related
Documents under the heading “Management Controller Host Interface Table”.
“MHSP” Microsoft Pluton Security Processor Table . See Links to ACPI-Related Documents
under the heading “Microsoft Pluton Security Processor Table”.
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Table 5.6 – continued from previous page
“MPAM” Arm Memory Partitioning And Monitoring . See Links to ACPI-Related Documents
under the heading “Arm Memory Partitioning And Monitoring”.
“MSDM” Microsoft Data Management Table . See Links to ACPI-Related Documents under
the heading “Microsoft Software Licensing Tables”.
“NBFT” NVMe-over-Fabric (NVMe-oF) Boot Firmware Table . See Links to ACPI-Related
Documents under the heading “NVMe-over-Fabric (NVMe-oF) Boot Firmware Ta-
ble”.
“PRMT” Platform Runtime Mechanism Table . See Links to ACPI-Related Documents under
the heading “Platform Runtime Mechanism Table”.
“RGRT” Regulatory Graphics Resource Table . See Links to ACPI-Related Documents under
the heading “Regulatory Graphics Resource Table”.
“SDEI” Software Delegated Exceptions Interface . See Links to ACPI-Related Documents
under the heading “Software Delegated Exceptions Interface.”
“SLIC” Microsoft Software Licensing table. See Links to ACPI-Related Documents under
the heading “Microsoft Software Licensing Table Speciﬁcation”.
“SPCR” Microsoft Serial Port Console Redirection table. See Links to ACPI-Related Docu-
ments under the heading “Serial Port Console Redirection Table”.
“SPMI” Server Platform Management Interface table. See Links to ACPI-Related Docu-
ments under the heading “Server Platform Management Interface Table”.
“STAO” _STA Override table. See Links to ACPI-Related Documents under the heading
“_STA Override Table”.
“SWFT” Sound Wire File Table table. See Links to ACPI-Related Documents under the head-
ing “Sound Wire File Table”.
“TCPA” Trusted Computing Platform Alliance Capabilities Table. TCPA PC Speciﬁc Im-
plementation Speciﬁcation. See Links to ACPI-Related Documents under the heading
“Trusted Computing Platform Alliance Capabilities Table”.
“TPM2” Trusted Platform Module 2 Table. See Links to ACPI-Related Documents under the
heading “Trusted Platform Module 2 Table”.
“UEFI” Uniﬁed Extensible Firmware Interface Speciﬁcation. See the UEFI Speciﬁcations
web page.
“WAET” Windows ACPI Emulated Devices Table**. See Links to ACPI-Related Documents
under the heading “Windows ACPI Emulated Devices Table”.
“WDAT” Watch Dog Action Table . Requirements for Hardware Watchdog Timers Supported
by Windows - Design Speciﬁcation. See Links to ACPI-Related Documents under the
heading “Watchdog Action Table (WDAT)”.
“WDDT” Watchdog Descriptor Table . The table passes Watchdog-related information to the
OS. See Links to ACPI-Related Documents under the the heading “Watchdog Descrip-
tor Table (WDDT)”.
“WDRT” Watchdog Resource Table . Watchdog Timer Hardware Requirements for Windows
Server 2003. See Links to ACPI-Related Documents under the heading “Watchdog
Timer Resource Table (WDRT)”.
“WPBT” Windows Platform Binary Table . See Links to ACPI-Related Documents under the
heading “Windows Platform Binary Table”.
“WSMT” Windows Security Mitigations Table . See Links to ACPI-Related Documents under
the heading “Windows SMM Security Mitigations Table (WSMT).”
“XENV” Xen Project . See Links to ACPI-Related Documents under the heading Xen Project
Table.
5.2. ACPI System Description Tables 103Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5

Table.
5.2.7 Root System Description Table (RSDT)
OSPM locates that Root System Description Table by following the pointer in the RSDP structure. The RSDT, shown
inRoot System Description Table Fields (RSDT) , starts with the signature ‘RSDT’ followed by an array of physical
pointers to other system description tables that provide various information on other standards deﬁned on the current
system. OSPM examines each table for a known signature. Based on the signature, OSPM can then interpret the
implementation-speciﬁc data within the table.
Platforms provide the RSDT to enable compatibility with ACPI 1.0 operating systems. The XSDT, described in the
next section, supersedes RSDT functionality.
Table 5.7: Root System Description Table Fields (RSDT)
Field Byte
Signature 4 0 ‘RSDT’ Signature for the Root System Description Ta-
ble.
Length 4 4 Length, in bytes, of the entire RSDT. The length im-
plies the number of Entry ﬁelds (n) at the end of the
table.
OEMID 6 10 OEM ID
OEM Table ID 8 16 For the RSDT, the table ID is the manufacture model
ID. This ﬁeld must match the OEM Table ID in the
FADT.
OEM Revision 4 24 OEM revision of RSDT table for supplied OEM Table
ID.
Compiler.
Entry 4*n 36 An array of 32-bit physical addresses that point to
other DESCRIPTION_HEADERs. OSPM assumes
at least the DESCRIPTION_HEADER is addressable,
and then can further address the table based upon its
Length ﬁeld.
5.2.8 Extended System Description Table (XSDT)
The XSDT provides identical functionality to the RSDT but accommodates physical addresses of DESCRIPTION
HEADERs that are larger than 32 bits. Notice that both the XSDT and the RSDT can be pointed to by the RSDP
structure. An ACPI-compatible OS must use the XSDT if present.
5.2. ACPI System Description Tables 104Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.8: Extended System Description Table Fields (XSDT)
Field Byte
Signature 4 0 ‘XSDT’. Signature for the Extended System Descrip-
tion Table.
Length 4 4 Length, in bytes, of the entire table. The length implies
the number of Entry ﬁelds (n) at the end of the table.
OEM Table ID 8 16 For the XSDT, the table ID is the manufacture model
FADT.
OEM Revision 4 24 OEM revision of XSDT table for supplied OEM Table
ID.
Compiler.
Entry 8*n 36 An array of 64-bit physical addresses that point to
5.2.9 Fixed ACPI Description Table (FADT)
The Fixed ACPI Description Table (FADT) deﬁnes various ﬁxed hardware ACPI information vital to an ACPI-
compatible OS, such as the base address for the following hardware registers blocks: PM1a_EVT_BLK,
PM1b_EVT_BLK, PM1a_CNT_BLK, PM1b_CNT_BLK, PM2_CNT_BLK, PM_TMR_BLK, GPE0_BLK, and
GPE1_BLK.
The FADT also has a pointer to the DSDT that contains the Differentiated Deﬁnition Block, which in turn provides
variable information to an ACPI-compatible OS concerning the base system design.
All ﬁelds in the FADT that provide hardware addresses provide processor-relative physical addresses.
Note: If the HW_REDUCED_ACPI ﬂag in the table is set, OSPM will ignore ﬁelds related to the ACPI HW register
interface: Fields at offsets 46 through 108 and 148 through 232, as well as FADT Flag bits 1, 2, 3,7,8,13, 14, 16, and
17).
Note: In all cases where the FADT contains a 32-bit ﬁeld and a corresponding 64-bit ﬁeld the 64-bit ﬁeld should
always be preferred by the OSPM if the 64-bit ﬁeld contains a non-zero value which can be used by the OSPM. In this
case, the 32-bit ﬁeld must be ignored regardless of whether or not it is zero, and whether or not it is the same value as
the 64-bit ﬁeld. The 32-bit ﬁeld should only be used if the corresponding 64-bit ﬁeld contains a zero value, or if the
64-bit value can not be used by the OSPM subject to e.g. CPU addressing limitations.
5.2. ACPI System Description Tables 105Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.9: FADT Format
Field Byte
Header
• Signature4 0 ‘FACP’. Signature for the Fixed ACPI Description Ta-
ble. (This signature predates ACPI 1.0, explaining the
mismatch with this table’s name.)
• Length4 4 Length, in bytes, of the entire FADT.
FADT Major Version 1 8
6
Major Version of this FADT structure, in
“Major.Minor” form, where ‘Minor’ is the value in the
Minor Version Field (Byte offset 131 in this table)
It is the intention that everything contained in the ACPI
table would comply with what is contained in the ACPI
speciﬁcation itself. The FADT Major and Minor
version follow in lock-step with the version of the
ACPI Speciﬁcation. Conforming to a given ACPI
speciﬁcation means that each and every ACPI-related
table conforms to the version number for that table that
is listed in that version of the speciﬁcation.
OEM Table ID 8 16 For the FADT, the table ID is the manufacture model ID.
This ﬁeld must match the OEM Table ID in the RSDT.
OEM Revision 4 24 OEM revision of FADT for supplied OEM Table ID.
Compiler.
Creator Revision 4 32 Revision of utility that created the table. For tables con-
taining Deﬁnition Blocks, this is the revision for the
ASL Compiler.
FIRMWARE_CTRL 4 36 Physical memory address of the FACS, where OSPM
and Firmware exchange control information. See Sec-
tion 5.2.10 for more information about the FACS. If
the X_FIRMWARE_CTRL ﬁeld contains a non zero
value which can be used by the OSPM, then this
ﬁeld must be ignored by the OSPM. If the HARD-
WARE_REDUCED_ACPI ﬂag is set, and both this ﬁeld
and the X_FIRMWARE_CTRL ﬁeld are zero, there is
no FACS available.
DSDT 4 40 Physical memory address of the DSDT. If the X_DSDT
ﬁeld contains a non-zero value which can be used by the
OSPM, then this ﬁeld must be ignored by the OSPM.
5.2. ACPI System Description Tables 106Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.9 – continued from previous page
Reserved 1 44 ACPI 1.0 deﬁned this offset as a ﬁeld named
INT_MODEL, which was eliminated in ACPI 2.0. Plat-
forms should set this ﬁeld to zero but ﬁeld values of one
are also allowed to maintain compatibility with ACPI
1.0.
Preferred_PM_Proﬁle 1 45
This ﬁeld is set by the OEM to convey the preferred
power management proﬁle to OSPM. OSPM can use
this ﬁeld to set default power management policy
parameters during OS installation. Field Values:
0 Unspeciﬁed
1 Desktop
2 Mobile
3 Workstation
4 Enterprise Server
5 SOHO Server
6 Appliance PC
7 Performance Server
8) Tablet
>8 Reserved
SCI_INT 2 46 System vector the SCI interrupt is wired to in 8259
mode. On systems that do not contain the 8259, this
ﬁeld contains the Global System interrupt number of the
SCI interrupt. OSPM is required to treat the ACPI SCI
interrupt as a shareable, level, active low interrupt.
SMI_CMD 4 48 System port address of the SMI Command Port. Dur-
ing ACPI OS initialization, OSPM can determine that
the ACPI hardware registers are owned by SMI (by way
of the SCI_EN bit), in which case the ACPI OS issues
the ACPI_ENABLE command to the SMI_CMD port.
The SCI_EN bit effectively tracks the ownership of the
ACPI hardware registers. OSPM issues commands to
the SMI_CMD port synchronously from the boot pro-
cessor. This ﬁeld is reserved and must be zero on system
that does not support System Management mode.
ACPI_ENABLE 1 52 The value to write to SMI_CMD to disable SMI own-
ership of the ACPI hardware registers. The last action
SMI does to relinquish ownership is to set the SCI_EN
bit. During the OS initialization process, OSPM will
synchronously wait for the ntransfer of SMI ownership
to complete, so the ACPI system releases SMI owner-
ship as quickly as possible. This ﬁeld is reserved and
must be zero on systems that do not support Legacy
Mode.
5.2. ACPI System Description Tables 107Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5

Mode.
ACPI_DISABLE 1 53 The value to write to SMI_CMD to re-enable SMI own-
ership of the ACPI hardware registers. This can only
be done when ownership was originally acquired from
SMI by OSPM using ACPI_ENABLE. An OS can hand
ownership back to SMI by relinquishing use to the ACPI
hardware registers, masking off all SCI interrupts, clear-
ing the SCI_EN bit and then writing ACPI_DISABLE
to the SMI_CMD port from the boot processor. This
ﬁeld is reserved and must be zero on systems that do
not support Legacy Mode.
S4BIOS_REQ 1 54 The value to write to SMI_CMD to enter the S4BIOS
state. The S4BIOS state provides an alternate way to
enter the S4 state where the ﬁrmware saves and restores
the memory context. A value of zero in S4BIOS_F in-
dicates S4BIOS_REQ is not supported. (See Section
5.2.10)
PSTATE_CNT 1 55 If non-zero, this ﬁeld contains the value OSPM writes
to the SMI_CMD register to assume processor perfor-
mance state control responsibility.
PM1a_EVT_BLK 4 56 System port address of the PM1a Event Register Block.
See Section 4.8.3.1 for a hardware description layout
of this register block. This is a required ﬁeld. If the
X_PM1a_CNT_BLK ﬁeld contains a non zero value
which can be used by the OSPM, then this ﬁeld must
be ignored by the OSPM.
PM1b_EVT_BLK 4 60 System port address of the PM1b Event Register Block.
See Section 4.8.3.1 for a hardware description layout of
this register block. This ﬁeld is optional; if this reg-
ister block is not supported, this ﬁeld contains zero. If
the X_PM1b_EVT_BLK ﬁeld contains a non zero value
which can be used by the OSPM, then this ﬁeld must be
ignored by the OSPM.
PM1a_CNT_BLK 4 64 System port address of the PM1a Control Register
Block. See Section 4.8.3.1 for a hardware description
layout of this register block. This is a required ﬁeld. If
the X_PM1a_CNT_BLK ﬁeld contains a non zero value
PM1b_CNT_BLK 4 68 System port address of the PM1b Control Register
layout of this register block. This ﬁeld is optional; if
this register block is not supported, this ﬁeld contains
zero. If the X_PM1b_CNT_BLK ﬁeld contains a non
zero value which can be used by the OSPM, then this
ﬁeld must be ignored by the OSPM.
PM2_CNT_BLK 4 72 System port address of the PM2 Control Register Block.
See Table 4.4 for a hardware description layout of this
register block. This ﬁeld is optional; if this regis-
ter block is not supported, this ﬁeld contains zero. If
the X_PM2_CNT_BLK ﬁeld contains a non zero value
5.2. ACPI System Description Tables 108Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PM_TMR_BLK 4 76 System port address of the Power Management Timer
Control Register Block. See the Section 4.8.3.3
for a hardware description layout of this register
block. This is an optional ﬁeld; if this register
block is not supported, this ﬁeld contains zero. If
the X_PM_TMR_BLK ﬁeld contains a non-zero value
GPE0_BLK 4 80 System port address of General-Purpose Event 0 Regis-
ter Block. See Section 4.8.4.1 for more information. If
zero. If the X_GPE0_BLK ﬁeld contains a nonzero
value which can be used by the OSPM, then this ﬁeld
must be ignored by the OSPM.
GPE1_BLK 4 84 System port address of General-Purpose Event 1 Reg-
ister Block. See Section 4.8.4.1 for more information.
This is an optional ﬁeld; if this register block is not sup-
ported, this ﬁeld contains zero. If the X_GPE1_BLK
ﬁeld contains a nonzero value which can be used by the
PM1_EVT_LEN 1 88 Number of bytes decoded by PM1a_EVT_BLK and, if
supported, PM1b_ EVT_BLK. This value is >= 4.
PM1_CNT_LEN 1 89 Number of bytes decoded by PM1a_CNT_BLK and, if
supported, PM1b_CNT_BLK. This value is >= 2.
PM2_CNT_LEN 1 90 Number of bytes decoded by PM2_CNT_BLK. Support
for the PM2 register block is optional. If supported, this
value is >= 1. If not supported, this ﬁeld contains zero.
PM_TMR_LEN 1 91 Number of bytes decoded by PM_TMR_BLK. If the
PM Timer is supported, this ﬁeld’s value must be 4. If
not supported, this ﬁeld contains zero.
GPE0_BLK_LEN 1 92 The length of the register whose address is given by
X_GPE0_BLK (if nonzero) or by GPE0_BLK (other-
wise) in bytes. The value is a non-negative multiple of
2.
GPE1_BLK_LEN 1 93 The length of the register whose address is given by
X_GPE1_BLK (if nonzero) or by GPE1_BLK (other-
2.
GPE1_BASE 1 94 Offset within the ACPI general-purpose event model
where GPE1 based events start.
CST_CNT 1 95 If non-zero, this ﬁeld contains the value OSPM writes
to the SMI_CMD register to indicate OS support for the
_CST object and C States Changed notiﬁcation.
P_LVL2_LAT 2 96 The worst-case hardware latency, in microseconds, to
enter and exit a C2 state. A value > 100 indicates the
system does not support a C2 state.
P_LVL3_LAT 2 98 The worst-case hardware latency, in microseconds, to
enter and exit a C3 state. A value > 1000 indicates the
system does not support a C3 state.
5.2. ACPI System Description Tables 109Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
FLUSH_SIZE 2 100 If WBINVD=0, the value of this ﬁeld is the number
of ﬂush strides that need to be read (using cacheable
addresses) to completely ﬂush dirty lines from any
processor’s memory caches. Notice that the value in
FLUSH_STRIDE is typically the smallest cache line
width on any of the processor’s caches (for more infor-
mation, see the FLUSH_STRIDE ﬁeld deﬁnition). If
the system does not support a method for ﬂushing the
processor’s caches, then FLUSH_SIZE and WBINVD
are set to zero. Notice that this method of ﬂushing the
processor caches has limitations, and WBINVD=1 is
the preferred way to ﬂush the processors caches. This
value is typically at least 2 times the cache size. The
maximum allowed value for FLUSH_SIZE multiplied
by FLUSH_STRIDE is 2 MB for a typical maximum
supported cache size of 1 MB. Larger cache sizes are
supported using WBINVD=1. This value is ignored if
WBINVD=1. This ﬁeld is maintained for ACPI 1.0 pro-
cessor compatibility on existing systems. Processors in
new ACPI-compatible systems are required to support
the WBINVD function and indicate this to OSPM by
setting the WBINVD ﬁeld = 1.
FLUSH_STRIDE 2 102 If WBINVD=0, the value of this ﬁeld is the cache line
width, in bytes, of the processor’s memory caches. This
value is typically the smallest cache line width on any
of the processor’s caches. For more information, see the
description of the FLUSH_SIZE ﬁeld. This value is ig-
nored if WBINVD=1. This ﬁeld is maintained for ACPI
1.0 processor compatibility on existing systems. Pro-
cessors in new ACPI-compatible systems are required
to support the WBINVD function and indicate this to
OSPM by setting the WBINVD ﬁeld = 1.
DUTY_OFFSET 1 104 The zero-based index of where the processor’s duty cy-
cle setting is within the processor’s P_CNT register.
DUTY_WIDTH 1 105 The bit width of the processor’s duty cycle setting value
in the P_CNT register. Each processor’s duty cycle
setting allows the software to select a nominal pro-
cessor frequency below its absolute frequency as de-
ﬁned by: THTL_EN = 1 BF * DC/(2DUTY_WIDTH)
Where: BF-Base frequency DC-Duty cycle setting
When THTL_EN is 0, the processor runs at its absolute
BF. A DUTY_WIDTH value of 0 indicates that proces-
sor duty cycle is not supported and the processor con-
tinuously runs at its base frequency.
DAY_ALRM 1 106 The RTC CMOS RAM index to the day-of-month alarm
value. If this ﬁeld contains a zero, then the RTC day of
the month alarm feature is not supported. If this ﬁeld
has a non-zero value, then this ﬁeld contains an index
into RTC RAM space that OSPM can use to program
the day of the month alarm. See Section 4.8.2.4 for a
description of how this hardware works.
5.2. ACPI System Description Tables 110Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
MON_ALRM 1 107 The RTC CMOS RAM index to the month of year alarm
value. If this ﬁeld contains a zero, then the RTC month
of the year alarm feature is not supported. If this ﬁeld
the month of the year alarm. If this feature is supported,
then the DAY_ALRM feature must be supported also.
CENTURY 1 108 The RTC CMOS RAM index to the century of data
value (hundred and thousand year decimals). If this ﬁeld
contains a zero, then the RTC centenary feature is not

supported. If this ﬁeld has a non-zero value, then this
ﬁeld contains an index into RTC RAM space that OSPM
can use to program the centenary ﬁeld.
IAPC_BOOT_ARCH 2 109 IA-PC Boot Architecture Flags. See Section 5.2.9.3 for
a description of this ﬁeld.
Reserved 1 111 Must be 0.
Flags 4 112 Fixed feature ﬂags. See Table 5.10 for a description of
this ﬁeld.
RESET_REG 12 116 The address of the reset register represented in Generic
Address Structure format (See Section 4.8.3.6 for a de-
scription of the reset mechanism.) Note: Only Sys-
tem I/O space, System Memory space and PCI Con-
ﬁguration space (bus #0) are valid for values for Ad-
dress_Space_ID. Also, Register_Bit_Width must be 8
and Register_Bit_Offset must be 0.
RESET_V ALUE 1 128 Indicates the value to write to the RESET_REG port to
reset the system. (See Section 4.8.3.6 for a description
of the reset mechanism.)
ARM_BOOT_ARCH 2 129 ARM Boot Architecture Flags. See Table 5.12 for a de-
scription of this ﬁeld.
FADT Minor Version 1 131
5.0 (errata bits 4-7 = 0)
Minor Version of this FADT structure, in
“Major.Minor” form, where ‘Major’ is the value in the
Major Version Field (Byte offset 8 in this table).
Bits 0-3 - The low order bits correspond to the minor
version of the speciﬁcation version. For instance, ACPI
6.3 has a major version of 6, and a minor version of 3.
Bits 4-7 - The high order bits correspond to the version
of the ACPI Speciﬁcation errata this table complies
with. A value of 0 means that it complies with the base
version of the current speciﬁcation. A value of 1 means
this is compatible with Errata A, 2 would be
compatible with Errata B, and so on.
X_FIRMWARE_CTRL 8 132 Extended physical address of the FACS. If this ﬁeld con-
tains a nonzero value which can be used by the OSPM,
then the FIRMWARE_CTRL ﬁeld must be ignored by
the OSPM. If the HARDWARE_REDUCED_ACPI ﬂag
is set, and both this ﬁeld and the FIRMWARE_CTRL
ﬁeld are zero, there is no FACS available.
5.2. ACPI System Description Tables 111Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
X_DSDT 8 140 Extended physical address of the DSDT. If this ﬁeld
contains a nonzero value which can be used by the
OSPM, then the DSDT ﬁeld must be ignored by the
OSPM.
X_PM1a_EVT_BLK 12 148 Extended address of the PM1a Event Register Block,
represented in Generic Address Structure format. See
Section 4.8.3.1 for a hardware description layout of this
register block. This is a required ﬁeld. If this ﬁeld con-
then the PM1a_EVT_BLK ﬁeld must be ignored by the
OSPM.
X_PM1b_EVT_BLK 12 160 Extended address of the PM1b Event Register Block,
register block. This ﬁeld is optional; if this register
block is not supported, this ﬁeld contains zero. If this
ﬁeld contains a nonzero value which can be used by
the OSPM, then the PM1b_EVT_BLK ﬁeld must be ig-
nored by the OSPM.
X_PM1a_CNT_BLK 12 172 Extended address of the PM1a Control Register Block,
Section 4.8.3.2 for a hardware description layout of this
then the PM1a_CNT_BLK ﬁeld must be ignored by the
OSPM.
X_PM1b_CNT_BLK 12 184 Extended address of the PM1b Control Register Block,
the OSPM, then the PM1b_CNT_BLK ﬁeld must be ig-
X_PM2_CNT_BLK 12 196 Extended address of the PM2 Control Register Block,
PM2 Control (PM2_CNT) for a hardware description
zero. If this ﬁeld contains a nonzero value which can
be used by the OSPM, then the PM2_CNT_BLK ﬁeld
X_PM_TMR_BLK 12 208 Extended address of the Power Management Timer
Control Register Block, represented in Generic Ad-
dress Structure format. See Section 4.8.3.3 for a hard-
ware description layout of this register block. This
ﬁeld is optional; if this register block is not sup-
ported, this ﬁeld contains zero. If this ﬁeld contains a
nonzero value which can be used by the OSPM, then the
PM_TMR_BLK ﬁeld must be ignored by the OSPM.
5.2. ACPI System Description Tables 112Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
X_GPE0_BLK 12 220 Extended address of the General-Purpose Event 0 Reg-
ister Block, represented in Generic Address Structure
format. See Section 4.8.4.1 for more information. This
is an optional ﬁeld; if this register block is not sup-
GPE0_BLK ﬁeld must be ignored by the OSPM. Note:
Only System I/O space and System Memory space are
valid for Address_Space_ID values, and the OSPM ig-
nores Register_Bit_Width, Register_Bit_Offset and Ac-
cess_Size.
X_GPE1_BLK 12 232 Extended address of the General-Purpose Event 1 Reg-
GPE1_BLK ﬁeld must be ignored by the OSPM. Note:
SLEEP_CONTROL_REG 12 244 The address of the Sleep register, represented in Generic
Address Structure format (see Section 4.8.3.7 for a de-
scription of the sleep mechanism). Note: Only Sys-
SLEEP_STATUS_REG 12 256 The address of the Sleep status register, represented in
Generic Address Structure format (see Section 4.8.3.7
for a description of the sleep mechanism). Note: Only
System I/O space, System Memory space and PCI Con-
Hypervisor Vendor Identity 8 268 64-bit identiﬁer of hypervisor vendor. All bytes in this
ﬁeld are considered part of the vendor identity. These
identiﬁers are deﬁned independently by the vendors
themselves, usually following the name of the hyper-
visor product. Version information should NOT be in-
cluded in this ﬁeld - this shall simply denote the ven-
dor’s name or identiﬁer. Version information can be
communicated through a supplemental vendor-speciﬁc
hypervisor API. Firmware implementers would place
zero bytes into this ﬁeld, denoting that no hypervisor
is present in the actual ﬁrmware.
Note: [Hypervisor Vendor Identity ] A ﬁrmware implementer would place zero bytes into this ﬁeld, denoting that no
hypervisor is present in the actual ﬁrmware.
5.2. ACPI System Description Tables 113Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Note: [Hypervisor Vendor Identity ] A hypervisor vendor that presents ACPI tables of its own construction to a guest
(for ‘virtual’ ﬁrmware or its ‘virtual’ platform), would provide its identity in this ﬁeld.
Note: [Hypervisor Vendor Identity ] If a guest operating system is aware of this ﬁeld it can consult it and act on the
result, based on whether it recognized the vendor and knows how to use the API that is deﬁned by the vendor.
Table 5.10: Fixed ACPI Description Table Fixed Feature Flags
FACP - Flag Bit
LengthBit
Off-
setDescription
WBINVD 1 0 Processor properly implements a functional
equivalent to the WBINVD IA-32 instruction. If
set, signiﬁes that the WBINVD instruction cor-
rectly ﬂushes the processor caches, maintains
memory coherency, and upon completion of the
instruction, all caches for the current processor
contain no cached data other than what OSPM
references and allows to be cached. If this ﬂag is
not set, the ACPI OS is responsible for disabling
all ACPI features that need this function. This
ﬁeld is maintained for ACPI 1.0 processor com-
patibility on existing systems. Processors in new
ACPI-compatible systems are required to sup-
port this function and indicate this to OSPM by
setting this ﬁeld.
WBINVD_FLUSH 1 1 If set, indicates that the hardware ﬂushes all
caches on the WBINVD instruction and main-

LengthBit
Off-
tains memory coherency, but does not guaran-
tee the caches are invalidated. This provides the
complete semantics of the WBINVD instruction,
and provides enough to support the system sleep-
ing states. If neither of the WBINVD ﬂags is
set, the system will require FLUSH_SIZE and
FLUSH_STRIDE to support sleeping states. If
the FLUSH parameters are also not supported,
the machine cannot support sleeping states S1,
S2, or S3.
PROC_C1 1 2 A one indicates that the C1 power state is sup-
ported on all processors.
P_LVL2_UP 1 3 A zero indicates that the C2 power state is con-
ﬁgured to only work on a uniprocessor (UP) sys-
tem. A one indicates that the C2 power state is
conﬁgured to work on a UP or multiprocessor
(MP) system.
5.2. ACPI System Description Tables 114Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.10 – continued from previous page
PWR_BUTTON 1 4 A zero indicates the power button is handled as
a ﬁxed feature programming model; a one indi-
cates the power button is handled as a control
method device. If the system does not have a
power button, this value would be “1” and no
power button device would be present. Indepen-
dent of the value of this ﬁeld, the presence of a
power button device in the namespace indicates
to OSPM that the power button is handled as a
control method device.
SLP_BUTTON 1 5 A zero indicates the sleep button is handled as
a ﬁxed feature programming model; a one in-
dicates the sleep button is handled as a control
sleep button, this value would be “1” and no
sleep button device would be present. Indepen-
sleep button device in the namespace indicates to
OSPM that the sleep button is handled as a con-
trol method device.
FIX_RTC 1 6 A zero indicates the RTC wake status is sup-
ported in ﬁxed register space; a one indicates the
RTC wake status is not supported in ﬁxed regis-
ter space.
RTC_S4 1 7 Indicates whether the RTC alarm function can
wake the system from the S4 state. The RTC
must be able to wake the system from an S1, S2,
or S3 sleep state. The RTC alarm can optionally
support waking the system from the S4 state, as
indicated by this value.
TMR_V AL_EXT 1 8 A zero indicates TMR_V AL is implemented as
a 24-bit value. A one indicates TMR_V AL is
implemented as a 32-bit value. The TMR_STS
bit is set when the most signiﬁcant bit of the
TMR_V AL toggles.
DCK_CAP 1 9 A zero indicates that the system cannot support
docking. A one indicates that the system can
support docking. Notice that this ﬂag does not
indicate whether or not a docking station is cur-
rently present; it only indicates that the system is
capable of docking.
RESET_REG_SUP 1 10 If set, indicates the system supports system re-
set via the FADT RESET_REG as described in
Section 4.8.3.6.
SEALED_CASE 1 11 System Type Attribute. If set indicates that the
system has no internal expansion capabilities and
the case is sealed.
HEADLESS 1 12 System Type Attribute. If set indicates the sys-
tem cannot detect the monitor or keyboard /
mouse devices.
5.2. ACPI System Description Tables 115Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
CPU_SW_SLP 1 13 If set, indicates to OSPM that a processor na-
tive instruction must be executed after writing
the SLP_TYPx register.
PCI_EXP_WAK 1 14 If set, indicates the platform supports the PCI-
EXP_WAKE_STS bit in the PM1 Status register
and the PCIEXP_WAKE_EN bit in the PM1 En-
able register. This bit must be set on platforms
containing chipsets that implement PCI Express
and supports PM1 PCIEXP_WAK bits.
USE_PLATFORM_CLOCK 1 15 A value of one indicates that OSPM should use a
platform provided timer to drive any monoton-
ically non-decreasing counters, such as OSPM
performance counter services. Which particu-
lar platform timer will be used is OSPM speciﬁc,
however, it is recommended that the timer used is
based on the following algorithm: If the HPET is
exposed to OSPM, OSPM should use the HPET.
Otherwise, OSPM will use the ACPI power man-
agement timer. A value of one indicates that
the platform is known to have a correctly imple-
mented ACPI power management timer. A plat-
form may choose to set this ﬂag if a internal pro-
cessor clock (or clocks in a multi-processor con-
ﬁguration) cannot provide consistent monotoni-
cally non-decreasing counters. Note: If a value
of zero is present, OSPM may arbitrarily choose
to use an internal processor clock or a platform
timer clock for these operations. That is, a zero
does not imply that OSPM will necessarily use
the internal processor clock to generate a mono-
tonically non-decreasing counter to the system.
S4_RTC_STS_V ALID 1 16 A one indicates that the contents of the
RTC_STS ﬂag is valid when waking the system
from S4. See Table 4.11 for more information.
Some existing systems do not reliably set this in-
put today, and this bit allows OSPM to differen-
tiate correctly functioning platforms from plat-
forms with this errata.
REMOTE_POWER_ON_CAPABLE 1 17 A one indicates that the platform is compatible
with remote power- on. That is, the platform
supports OSPM leaving GPE wake events armed
prior to an S5 transition. Some existing plat-
forms do not reliably transition to S5 with wake
events enabled (for example, the platform may
immediately generate a spurious wake event af-
ter completing the S5 transition). This ﬂag al-
lows OSPM to differentiate correctly functioning
platforms from platforms with this type of errata.
5.2. ACPI System Description Tables 116Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
FORCE_APIC_CLUSTER_MODEL 1 18 A one indicates that all local APICs must be con-
ﬁgured for the cluster destination model when
delivering interrupts in logical mode. If this bit
is set, then logical mode interrupt delivery opera-
tion may be undeﬁned until OSPM has moved all
local APICs to the cluster model. Note that the
cluster destination model doesn’t apply to Ita-
nium™ Processor Family (IPF) local SAPICs.
This bit is intended for xAPIC based machines
that require the cluster destination model even
when 8 or fewer local APICs are present in the
machine.
FORCE_APIC_PHYSICAL_-
DESTINATION_MODE1 19 A one indicates that all local xAPICs must be
conﬁgured for physical destination mode. If this
bit is set, interrupt delivery operation in logical
destination mode is undeﬁned. On machines that
contain fewer than 8 local xAPICs or that do not
use the xAPIC architecture, this bit is ignored.
HW_REDUCED_ACPI * 1 20 A one indicates that the Hardware-Reduced
ACPI (section 4.1) is implemented, therefore
software-only alternatives are used for supported
ﬁxed-features deﬁned in chapter 4.
LOW_POWER_S0_IDLE_CAPABLE 1 21 A one informs OSPM that the platform is able to
achieve power savings in S0 similar to or better
than those typically achieved in S3. In effect,
when this bit is set it indicates that the system
will achieve no power beneﬁt by making a sleep
transition to S3.
5.2. ACPI System Description Tables 117Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PERSISTENT_CPU_CACHES 2 22
The following values describe whether cpu
caches and any other caches that are coherent
with them, are considered by the platform to be
persistent. The platform evaluates the
conﬁguration present at system startup to
determine this value. System conﬁguration
changes after system startup may invalidate this.
00b - Not reported by the platform. Software
should reference the NFIT Platform Capabilities
01b - Cpu caches and any other caches that are
coherent with them, are not persistent. Software
is responsible for ﬂushing data from cpu caches
to make stores persistent. Supersedes NFIT
Platform Capabilities.
10b - Cpu caches and any other caches that are
coherent with them, are persistent. Supersedes
NFIT Platform Capabilities. When reporting
this state, the platform shall provide enough
stored energy for ALL of the following:
- Time to ﬂush cpu caches and any other
caches that are coherent with them
- Time of all targets of those ﬂushes to
complete ﬂushing stored data
- If supporting hot plug, the worst case
CXL device topology that can be hot
plugged
11b - Reserved
Reserved 8 24
* The description of HW_REDUCED_ACPI provided here applies to ACPI speciﬁcations 5.0 and later.
5.2.9.1 Preferred PM Proﬁle System Types
The following descriptions of preferred power management proﬁle system types are to be used as a guide for setting the
Preferred_PM_Proﬁle ﬁeld in the FADT. OSPM can use this ﬁeld to set default power management policy parameters
during OS installation.
Desktop A single user, full featured, stationary computing device that resides on or near an individual’s work area.

plugged
Most often contains one processor. Must be connected to AC power to function. This device is used to per-
form work that is considered mainstream corporate or home computing (for example, word processing, Internet
browsing, spreadsheets, and so on).
Mobile A single-user, full-featured, portable computing device that is capable of running on batteries or other power
storage devices to perform its normal functions. Most often contains one processor. This device performs the
same task set as a desktop. However it may have limitations dues to its size, thermal requirements, and/or power
source life.
Workstation A single-user, full-featured, stationary computing device that resides on or near an individual’s work
area. Often contains more than one processor. Must be connected to AC power to function. This device is used
to perform large quantities of computations in support of such work as CAD/CAM and other graphics-intensive
applications.
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Enterprise Server A multi-user, stationary computing device that frequently resides in a separate, often specially de-
signed, room. Will almost always contain more than one processor. Must be connected to AC power to function.
This device is used to support large-scale networking, database, communications, or ﬁnancial operations within
a corporation or government.
SOHO Server A multi-user, stationary computing device that frequently resides in a separate area or room in a small
or home ofﬁce. May contain more than one processor. Must be connected to AC power to function. This device
is generally used to support all of the networking, database, communications, and ﬁnancial operations of a small
ofﬁce or home ofﬁce.
Appliance PC A device speciﬁcally designed to operate in a low-noise, high-availability environment such as a con-
sumer’s living rooms or family room. Most often contains one processor. This category also includes home
Internet gateways, Web pads, set top boxes and other devices that support ACPI. Must be connected to AC
power to function. Normally they are sealed case style and may only perform a subset of the tasks normally
associated with today’s personal computers.
Performance Server A multi-user stationary computing device that frequently resides in a separate, often specially
designed room. Will often contain more than one processor. Must be connected to AC power to function. This
device is used in an environment where power savings features are willing to be sacriﬁced for better performance
and quicker responsiveness.
Tablet A full-featured, highly mobile computing device which resembles writing tablets and which users interact with
primarily through a touch interface. The touch digitizer is the primary user input device, although a keyboard
and/or mouse may be present. Tablet devices typically run on battery power and are generally only plugged
into AC power in order to charge. This device performs many of the same tasks as Mobile; however battery life
expectations of Tablet devices generally require more aggressive power savings especially for managing display
and touch components.
5.2.9.2 System Type Attributes
This set of ﬂags is used by the OS to assist in determining assumptions about power and device management. These
ﬂags are read at boot time and are used to make decisions about power management and device settings. For example,
a system that has the SEALED_CASE bit set may take a very aggressive low noise policy toward thermal management.
In another example an OS might not load video, keyboard or mouse drivers on a HEADLESS system.
5.2.9.3 IA-PC Boot Architecture Flags
This set of ﬂags is used by an OS to guide the assumptions it can make in initializing hardware on IA-PC platforms.
These ﬂags are used by an OS at boot time (before the OS is capable of providing an operating environment suitable
for parsing the ACPI namespace) to determine the code paths to take during boot. In IA-PC platforms with reduced
legacy hardware, the OS can skip code paths for legacy devices if none are present. For example, if there are no
ISA devices, an OS could skip code that assumes the presence of these devices and their associated resources. These
ﬂags are used independently of the ACPI namespace. The presence of other devices must be described in the ACPI
namespace as speciﬁed in Section 6 These ﬂags pertain only to IA-PC platforms. On other system architectures, the
entire ﬁeld should be set to 0.
5.2. ACPI System Description Tables 119Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.11: Fixed ACPI Description Table Boot IA-PC Boot
IAPC_BOOT_ARCH Bit
lengthBit
offsetDescription
LEGACY_DEVICES 1 0 If set, indicates that the motherboard supports user-visible de-
vices on the LPC or ISA bus. User-visible devices are devices
that have end-user accessible connectors (for example, LPT
port), or devices for which the OS must load a device driver so
that an end-user application can use a device. If clear, the OS
may assume there are no such devices and that all devices in
the system can be detected exclusively via industry standard
device enumeration mechanisms (including the ACPI names-
pace).
8042 1 1 If set, indicates that the motherboard contains support for
a port 60 and 64 based keyboard controller, usually imple-
mented as an 8042 or equivalent micro-controller.
VGA Not Present 1 2 If set, indicates to OSPM that it must not blindly probe the
VGA hardware (that responds to MMIO addresses A0000h-
BFFFFh and IO ports 3B0h-3BBh and 3C0h-3DFh) that may
cause machine check on this system. If clear, indicates to
OSPM that it is safe to probe the VGA hardware.
MSI Not Supported 1 3 If set, indicates to OSPM that it must not enable Message
Signaled Interrupts (MSI) on this platform.
PCIe ASPM Controls 1 4 If set, indicates to OSPM that it must not enable OSPM
ASPM control on this platform.
CMOS RTC Not Present 1 5 If set, indicates that the CMOS RTC is either not imple-
mented, or does not exist at the legacy addresses. OSPM uses
the Control Method Time and Alarm Namespace device in-
stead.
Reserved 10 6 Must be 0.
5.2.9.4 ARM Architecture Boot Flags
for parsing the ACPI namespace) to determine the code paths to take during boot. For the PSCI ﬂags, speciﬁcally, the
ﬂags describe if the platform is compliant with the PSCI speciﬁcation. A link to the PSCI speciﬁcation can be found
at “Links to ACPI-Related Documents” at http://ueﬁ.org/acpi.
The ARM Architecture boot ﬂags are described in the following table.
Table 5.12: Fixed ACPI Description Table ARM Boot Architecture
Flags
ARM_BOOT_ARCH Bit
LengthBit Off-
PSCI_COMPLIANT 1 0 1 if PSCI is implemented.
PSCI_USE_HVC 1 1 1 if HVC must be used as the PSCI conduit.instead of SMC.
Reserved 14 2 This value is zero.
5.2. ACPI System Description Tables 120Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.10 Firmware ACPI Control Structure (FACS)
The Firmware ACPI Control Structure (FACS) is a structure in read/write memory that the platform boot ﬁrmware
reserves for ACPI usage. This structure is optional if and only if the HARDWARE_REDUCED_ACPI ﬂag in the
FADT is set. The FACS is passed to an ACPI-compatible OS using the FADT. For more information about the FADT
FIRMWARE_CTRL ﬁeld, see Section 5.2.9
The platform boot ﬁrmware aligns the FACS on a 64-byte boundary anywhere within the system’s memory address
space. The memory where the FACS structure resides must not be reported as system AddressRangeMemory in the
system address map. For example, the E820 address map reporting interface would report the region as AddressRan-
geReserved. For more information, see Section 15.
Table 5.13: Firmware ACPI Control Structure (FACS)
Field Byte
Signature 4 0 ‘FACS’
Length 4 4 Length, in bytes, of the entire Firmware ACPI Control
Structure. This value is 64 bytes or larger.
Hardware Signature 4 8 The value of the system’s “hardware signature at cur-
rent boot.” The only thing that determines the hardware
signature is the ACPI tables. If any content or struc-
ture of the ACPI tables has changed, including adding
or removing of tables, then the hardware signature must
change.
Firmware Waking Vector 4 12 This ﬁeld is superseded by the
X_Firmware_Waking_Vector ﬁeld. The 32-bit ad-
dress ﬁeld where OSPM puts its waking vector. Before
transitioning the system into a global sleeping state,
OSPM ﬁlls in this ﬁeld with the physical memory
address of an OS-speciﬁc wake function. During
POST, the platform ﬁrmware ﬁrst checks if the value
of the X_Firmware_Waking_Vector ﬁeld is non-zero
and if so transfers control to OSPM as outlined in the
X_Firmware_Waking_vector ﬁeld description below. If
the X_Firmware_Waking_Vector ﬁeld is zero then the

change.
platform ﬁrmware checks the value of this ﬁeld and if
it is non-zero, transfers control to the speciﬁed address.
On PCs, the wake function address is in memory below
1 MB and the control is transferred while in real mode.
OSPM’s wake function restores the processors’ context.
For IA-PC platforms, the following example shows
the relationship between the physical address in the
Firmware Waking Vector and the real mode address the
BIOS jumps to. If, for example, the physical address
is 0x12345, then the BIOS must jump to real mode
address 0x1234:0x0005. In general this relationship is
Real-mode address = Physical address>>4 : Physical
address and 0x000F Notice that on IA-PC platforms,
A20 must be enabled when the BIOS jumps to the real
mode address derived from the physical address stored
in the Firmware Waking Vector.
5.2. ACPI System Description Tables 121Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.13 – continued from previous page
Field Byte
Global Lock 4 16 This ﬁeld contains the Global Lock used to synchronize
access to shared hardware resources between the OSPM
environment and an external controller environment (for
example, the SMI environment). This lock is owned ex-
clusively by either OSPM or the ﬁrmware at any one
time. When ownership of the lock is attempted, it might
be busy, in which case the requesting environment exits
and waits for the signal that the lock has been released.
For example, the Global Lock can be used to protect
an embedded controller interface such that only OSPM
or the ﬁrmware will access the embedded controller in-
terface at any one time. See Section 5.2.10.1 for more
information on acquiring and releasing the Global Lock.
Flags 4 20 Table 5.14
X Firmware Waking Vector 8 24 64-bit physical address of OSPM’s Waking Vector. Be-
fore transitioning the system into a global sleeping state,
OSPM ﬁlls in this ﬁeld and the OSPM Flags ﬁeld to
describe the waking vector. OSPM populates this ﬁeld
with the physical memory address of an OS-speciﬁc
wake function. During POST, the platform ﬁrmware
checks if the value of this ﬁeld is non-zero and if so
transfers control to OSPM by jumping to this address
after creating the appropriate execution environment,
which must be conﬁgured as follows: For 64-bit Ita-
nium™ Processor Family (IPF) -based platforms: Inter-
rupts must be disabled The processor must have psr.i set
to 0. See the Intel® ItaniumTM Architecture Software
Developer’s Manual for more information. Memory ad-
dress translation must be disabled The processor must
have psr.it, psr.dt, and psr.rt set to 0. See the Intel®
ItaniumTM Architecture Software Developer’s Manual
for more information. For IA 32 and x64 platforms,
platform ﬁrmware is required to support a 32 bit exe-
cution environment. Platform ﬁrmware can addition-
ally support a 64 bit execution environment. If plat-
form ﬁrmware supports a 64 bit execution environment,
ﬁrmware inspects the OSPM Flags during POST. If the
64BIT_WAKE_F ﬂag is set, the platform ﬁrmware cre-
ates a 64 bit execution environment. Otherwise, the plat-
form ﬁrmware creates a 32 bit execution environment.
For 64 bit execution environment: Interrupts must be
disabled EFLAGS.IF set to 0 Long mode enabled Pag-
ing mode is enabled and physical memory for waking
vector is identity mapped (virtual address equals phys-
ical address) Waking vector must be contained within
one physical page Selectors are set to be ﬂat and are
otherwise not used For 32 bit execution environment:
Interrupts must be disabled EFLAGS.IF set to 0 Mem-
ory address translation / paging must be disabled 4 GB
ﬂat address space for all segment registers
5.2. ACPI System Description Tables 122Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Field Byte
Version 1 32 3-Version of this table
Reserved 3 33 This value is zero.
OSPM Flags 4 36 OSPM enabled ﬁrmware control structure ﬂags. Plat-
form ﬁrmware must initialize this ﬁeld to zero. See Ta-
ble 5.15 for more details.
Reserved 24 40 This value is zero.
Table 5.14: Firmware Control Structure Feature Flags
FACS - Flag Bit
S4BIOS_F 1 0 Indicates whether the platform supports
S4BIOS_REQ. If S4BIOS_REQ is not sup-
ported, OSPM must be able to save and restore
the memory state in order to use the S4 state.
64BIT_WAKE_SUPPORTED_F 1 1 Indicates that the platform ﬁrmware supports a
64 bit execution environment for the waking vec-
tor. When set and the OSPM additionally set
64BIT_WAKE_F, the platform ﬁrmware will cre-
ate a 64 bit execution environment before transfer-
ring control to the X_Firmware_Waking_Vector.
Reserved 30 2 The value is zero.
Table 5.15: OSPM Enabled Firmware Control Structure Feature
Flags
64BIT_WAKE_F 1 0 OSPM sets this bit to indicate to platform ﬁrmware that the
X_Firmware_Waking_Vector requires a 64 bit execution envi-
ronment. This ﬂag can only be set if platform ﬁrmware sets
64BIT_WAKE_SUPPORTED_F in the FACS ﬂags ﬁeld. This bit
ﬁeld has no affect on ItaniumTM Processor Family (IPF) -based
platforms, which require a 64 bit execution environment.
Reserved 31 1 The value is zero.
5.2.10.1 Global Lock
The purpose of the ACPI Global Lock is to provide mutual exclusion between the host OS and the platform runtime
ﬁrmware. The Global Lock is a 32-bit (DWORD) value in read/write memory located within the FACS and is accessed
and updated by both the OS environment and the SMI environment in a deﬁned manner to provide an exclusive lock.
Note: this is not a pointer to the Global Lock, it is the actual memory location of the lock. The FACS and Global Lock
may be located anywhere in physical memory.
By convention, this lock is used to ensure that while one environment is accessing some hardware, the other environ-
ment is not. By this convention, when ownership of the lock fails because the other environment owns it, the requesting
environment sets a “pending” state within the lock, exits its attempt to acquire the lock, and waits for the owning en-
vironment to signal that the lock has been released before attempting to acquire the lock again. When releasing the
lock, if the pending bit in the lock is set after the lock is released, a signal is sent via an interrupt mechanism to the
5.2. ACPI System Description Tables 123Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
other environment to inform it that the lock has been released. During interrupt handling for the “lock released” event
within the corresponding environment, if the lock ownership were still desired an attempt to acquire the lock would be
made. If ownership is not acquired, then the environment must again set “pending” and wait for another “lock release”
signal.
The table below shows the encoding of the Global Lock DWORD in memory.
Table 5.16: Global Lock Structure within the FACS
Field Bit
Pending 1 0 Non-zero indicates that a request for ownership of the Global Lock is
pending.
Owned 1 1 Non-zero indicates that the Global Lock is Owned.
Reserved 30 2 Reserved for future use.
The following code sequence is used by both OSPM and the ﬁrmware to acquire ownership of the Global Lock. If
non-zero is returned by the function, the caller has been granted ownership of the Global Lock and can proceed. If
zero is returned by the function, the caller has not been granted ownership of the Global Lock, the “pending” bit has
been set, and the caller must wait until it is signaled by an interrupt event that the lock is available before attempting
to acquire access again.
Note: In the examples that follow, the “GlobalLock” variable is a pointer that has been previously initialized to point
to the 32-bit Global Lock location within the FACS.
AcquireGlobalLock:
mov ecx, GlobalLock ; ecx = Address of Global Lock in FACS
acq10: mov eax, [ecx] ; Get current value of Global Lock
mov edx, eax
and edx, not 1 ; Clear pending bit
bts edx, 1 ; Check and set owner bit
adc edx, 0 ; If owned, set pending bit
lock cmpxchg dword ptr[ecx], edx ; Attempt to set new value
jnz short acq10 ; If not set, try again
cmp dl, 3 ; Was it acquired or marked pending?
sbb eax, eax ; acquired = -1, pending = 0
ret
The following code sequence is used by OSPM and the ﬁrmware to release ownership of the Global Lock. If non-zero
is returned, the caller must raise the appropriate event to the other environment to signal that the Global Lock is now
free. Depending on the environment, this signaling is done by setting the either the GBL_RLS or BIOS_RLS within
their respective hardware register spaces. This signal only occurs when the other environment attempted to acquire
ownership while the lock was owned.
ReleaseGlobalLock:

ret
rel10: mov eax, [ecx] ; Get current value of Global Lock
and edx, not 03h ; Clear owner and pending field
5.2. ACPI System Description Tables 124Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
lock cmpxchg dword ptr[ecx], edx ; Attempt to set it
jnz short rel10 ; If not set, try again
and eax, 1 ; Was pending set?
; if one is returned (we were pending) the caller must signal that the
; lock has been released using either GBL_RLS or BIOS_RLS as appropriate
ret
Although using the Global Lock allows various hardware resources to be shared, it is important to notice that its
usage when there is ownership contention could entail a signiﬁcant amount of system overhead as well as waits of an
indeterminate amount of time to acquire ownership of the Global Lock. For this reason, implementations should try
to design the hardware to keep the required usage of the Global Lock to a minimum.
The Global Lock is required whenever a logical register in the hardware is shared. For example, if bit 0 is used by
ACPI (OSPM) and bit 1 of the same register is used by SMI, then access to that register needs to be protected under
the Global Lock, ensuring that the register’s contents do not change from underneath one environment while the other
is making changes to it. Similarly if the entire register is shared, as the case might be for the embedded controller
interface, access to the register needs to be protected under the Global Lock.
5.2.11 Deﬁnition Blocks
A Deﬁnition Block consists of data in AML format (see Section 5.4 “Deﬁnition Block Encoding”) and contains
information about hardware implementation details in the form of AML objects that contain data, AML code, or other
AML objects. The top-level organization of this information after a deﬁnition block is loaded is name-tagged in a
hierarchical namespace.
OSPM “loads” or “unloads” an entire deﬁnition block as a logical unit. OSPM will load a deﬁnition block either
as a result of executing the AML Load() or LoadTable() operator or encountering a table deﬁnition during initial-
ization. During initialization, OSPM loads the Differentiated System Description Table (DSDT), which contains the
Differentiated Deﬁnition Block, using the DSDT pointer retrieved from the FADT. OSPM will load other deﬁnition
blocks during initialization as a result of encountering Secondary System Description Table (SSDT) deﬁnitions in
the RSDT/XSDT. Each SSDT must be loaded in the order presented in the RSDT/XSDT. The DSDT and SSDT are
described in the following sections.
As mentioned, the AML Load() and LoadTable() operators make it possible for a Deﬁnition Block to load other
Deﬁnition Blocks, either statically or dynamically, where they in turn can either deﬁne new system attributes or, in
some cases, build on prior deﬁnitions. Although this gives the hardware the ability to vary widely in implementation,
it also conﬁnes it to reasonable boundaries. In some cases, the Deﬁnition Block format can describe only speciﬁc and
well-understood variances. In other cases, it permits implementations to be expressible only by means of a speciﬁed
set of “built in” operators. For example, the Deﬁnition Block has built in operators for I/O space.
In theory, it might be possible to deﬁne something like PCI conﬁguration space in a Deﬁnition Block by building it
from I/O space, but that is not the goal of the deﬁnition block. Such a space is usually deﬁned as a “built in” operator.
Some AML operators perform simple functions, and others encompass complex functions. The power of the Deﬁnition
block comes from its ability to allow these operations to be glued together in numerous ways, to provide functionality
to OSPM.
The AML operators deﬁned in this speciﬁcation are intended to allow many useful hardware designs to be easily
expressed, not to allow all hardware designs to be expressed.
Note: To accommodate addressing beyond 32 bits, the integer type was expanded to 64 bits in ACPI 2.0, see Section
19.3.5 . Existing ACPI deﬁnition block implementations may contain an inherent assumption of a 32-bit integer
width. Therefore, to maintain backwards compatibility, OSPM uses the Revision ﬁeld, in the header portion of system
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description tables containing Deﬁnition Blocks, to determine whether integers declared within the Deﬁnition Block
are to be evaluated as 32-bit or 64-bit values. A Revision ﬁeld value greater than or equal to 2 signiﬁes that integers
declared within the Deﬁnition Block are to be evaluated as 64-bit values. The ASL writer speciﬁes the value for the
Deﬁnition Block table header’s Revision ﬁeld via the ASL Deﬁnition Block’s ComplianceRevision ﬁeld. See Section
19.6.29 , for more information. It is the responsibility of the ASL writer to ensure the Deﬁnition Block’s compatibility
with the corresponding integer width when setting the ComplianceRevision ﬁeld.
5.2.11.1 Differentiated System Description Table (DSDT)
The Differentiated System Description Table (DSDT) is part of the system ﬁxed description. The DSDT is comprised
of a system description table header followed by data in Deﬁnition Block format. See Section 5.2.11 for a description
of Deﬁnition Blocks. During initialization, OSPM ﬁnds the pointer to the DSDT in the Fixed ACPI Description Table
(using the FADT’s DSDT or X_DSDT ﬁelds) and then loads the DSDT to create the ACPI Namespace.
Table 5.17: Differentiated System Description Table Fields (DSDT)
Field Byte
Signature 4 0 ‘DSDT’ Signature for the Differentiated System Description
Table.
Length 4 4 Length, in bytes, of the entire DSDT (including the header).
Revision 1 8
2. This ﬁeld also sets the global integer width for the AML
interpreter. Values less than two will cause the inter-
preter to use 32-bit integers and math. Values of two
and greater will cause the interpreter to use full 64-bit
integers and math.
OEM Table ID 8 16 The manufacture model ID.
OEM Revision 4 24 OEM revision of DSDT for supplied OEM Table ID.
Creator ID 4 28 Vendor ID for the ASL Compiler.
Creator Revision 4 32 Revision number of the ASL Compiler.
Deﬁnition Block n 36 n bytes of AML code (see Section 5.4).
5.2.11.2 Secondary System Description Table (SSDT)
Secondary System Description Tables (SSDT) are a continuation of the DSDT. The SSDT is comprised of a system de-
scription table header followed by data in Deﬁnition Block format. There can be multiple SSDTs present. After OSPM
loads the DSDT to create the ACPI Namespace, each secondary system description table listed in the RSDT/XSDT
with a unique OEM Table ID is loaded in the order presented in the RSDT/XSDT.
• Additional tables can only add data; they cannot overwrite data from previous tables.
This allows the OEM to provide the base support in one table and add smaller system options in other tables. For
example, the OEM might put dynamic object deﬁnitions into a secondary table such that the ﬁrmware can construct
the dynamic information at boot without needing to edit the static DSDT. A SSDT can only rely on the DSDT being
loaded prior to it.
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Table 5.18: Secondary System Description Table Fields (SSDT)
Field Byte
Header
Signature 4 0 ‘SSDT’ Signature for the Secondary System Description Ta-
ble.
Length 4 4 Length, in bytes, of the entire SSDT (including the header).
5.2.11.3 Persistent System Description Table (PSDT)
The table signature, “PSDT” refers to the Persistent System Description Table (PSDT) deﬁned in the ACPI 1.0 speci-
ﬁcation. The PSDT was judged to provide no speciﬁc beneﬁt and as such has been deleted from follow-on versions of
the ACPI speciﬁcation. OSPM will evaluate a table with the “PSDT” signature in like manner to the evaluation of an
SSDT as described in Section 5.2.11.2
5.2.12 Multiple APIC Description Table (MADT)
The ACPI interrupt model describes all interrupts for the entire system in a uniform interrupt model implementation.
Supported interrupt models include:
• the PC-AT-compatible dual 8259 interrupt controller,
• for Intel processor-based systems: the Intel Advanced Programmable Interrupt Controller (APIC) and Intel
Streamlined Advanced Programmable Interrupt,
• for ARM processor-based systems: the Generic Interrupt Controller (GIC),

• for LoongArch processor-based systems: the LoongArch Programmable Interrupt Controller (LPIC).
The choice of interrupt model(s) to support is up to the platform designer. The interrupt model cannot be dynamically
changed by system ﬁrmware; OSPM will choose which model to use and install support for that model at the time of
installation. If a platform supports multiple models, an OS will install support for only one of the models and will not
mix models. Multi-boot capability is a feature in many modern operating systems. This means that a system may have
multiple operating systems or multiple instances of an OS installed at any one time. Platform designers must allow for
this.
This section describes the format of the Multiple APIC Description Table (MADT), which provides OSPM with
information necessary for operation on systems with APIC, SAPIC, GIC, or LPIC implementations.
ACPI represents all interrupts as “ﬂat” values known as global system interrupts. Therefore to support APICs, SAPICs,
GICs, or LPICs on an ACPI-enabled system, each used interrupt input must be mapped to the global system interrupt
value used by ACPI. See Global System Interrupts for more details.
Additional support is required to handle various multi-processor functions that implementations might support (for
example, identifying each processor’s local interrupt controller ID).
All addresses in the MADT are processor-relative physical addresses.
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Starting with ACPI Speciﬁcation 6.3, the use of the Processor() object was deprecated. Only legacy systems should
continue with this usage. On the Itanium architecture only, a _UID is provided for the Processor() that is a string
object. This usage of _UID is also deprecated since it can preclude an OSPM from being able to match a processor
to a non-enumerable device, such as those deﬁned in the MADT. From ACPI Speciﬁcation 6.3 onward, all processor
objects for all architectures except Itanium must now use Device() objects with an _HID of ACPI0007, and use only
integer _UID values.
Table 5.19: Multiple APIC Description Table (MADT) Format
Field Byte
Header
Signature 4 0 ‘APIC’ Signature for the Multiple APIC Description Table.
Length 4 4 Length, in bytes, of the entire MADT.
Revision 1 8 6
OEM Table ID 8 16 For the MADT, the table ID is the manufacturer model ID.
OEM Revision 4 24 OEM revision of MADT for supplied OEM Table ID.
Creator ID 4 28 Vendor ID of utility that created the table. For tables contain-
ing Deﬁnition Blocks, this is the ID for the ASL Compiler.
Creator Revision 4 32 Revision of utility that created the table. For tables containing
Deﬁnition Blocks, this is the revision for the ASL Compiler.
Local Interrupt Controller
Address4 36 The 32-bit physical address at which each processor can ac-
cess its local interrupt controller.
Flags 4 40 Multiple APIC ﬂags. See Multiple APIC Flags for a descrip-
tion of this ﬁeld.
Interrupt Controller Struc-
ture[n]– 44 A list of interrupt controller structures for this implementa-
tion. This list will contain all of the structures from Interrupt
Controller Structure Types needed to support this platform.
These structures are described in the following sections.
Table 5.20: Multiple APIC Flags
Multiple APIC Flags Bit
PCAT_COMPAT 1 0 A one indicates that the system also has a PC-AT-compatible
dual-8259 setup. The 8259 vectors must be disabled (that is,
masked) when enabling the ACPI APIC operation.
Reserved 31 1 This value is zero.
Immediately after the Flags value in the MADT is a list of interrupt controller structures that declare the interrupt
features of the machine. The ﬁrst byte of each structure declares the type of that structure and the second byte declares
the length of that structure.
Table 5.21: Interrupt Controller Structure Types
Value Description _MAT for
Processor
object (a)_MAT for an
I/O APIC ob-
ject (b)Reference
0 Processor Local APIC yes no Section 5.2.12.2
1 I/O APIC no yes Section 5.2.12.3
2 Interrupt Source Override no yes Section 5.2.12.5
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Table 5.21 – continued from previous page
3 Non-maskable Interrupt (NMI)
Sourceno yes Section 5.2.12.6
4 Local APIC NMI yes no Section 5.2.12.7
5 Local APIC Address Override no no Section 5.2.12.8
6 I/O SAPIC no yes Section 5.2.12.9
7 Local SAPIC yes no Section 5.2.12.10
8 Platform Interrupt Sources no yes Section 5.2.12.11
9 Processor Local x2APIC yes no Section 5.2.12.12
0xA Local x2APIC NMI yes no Section 5.2.12.13
0xB GIC CPU Interface (GICC) yes no Section 5.2.12.14
0xC GIC Distributor (GICD) no no Section 5.2.12.15
0xD GIC MSI Frame no no Section 5.2.12.16
0xE GIC Redistributor (GICR) no no Section 5.2.12.17
0xF GIC Interrupt Translation Service
(ITS)no no Section 5.2.12.18
0x10 Multiprocessor Wakeup no no Section 5.2.12.19
0x11 Core Programmable Interrupt Con-
troller (CORE PIC)no no Section 5.2.12.20
0x12 Legacy I/O Programmable Interrupt
Controller (LIO PIC)no no Section 5.2.12.21
0x13 HyperTransport Programmable Inter-
rupt Controller (HT PIC)no no Section 5.2.12.22
0x14 Extend I/O Programmable Interrupt
Controller (EIO PIC)no no Section 5.2.12.23
0x15 MSI Programmable Interrupt Con-
troller (MSI PIC)no no Section 5.2.12.24
0x16 Bridge I/O Programmable Interrupt
Controller (BIO PIC)no no Section 5.2.12.25
0x17 Low Pin Count Programmable Inter-
rupt Controller (LPC PIC)no no Section 5.2.12.26
0x18-0x7F Reserved. OSPM skips structures of
the reserved type.no no
0x80-0xFF Reserved for OEM use no no
Notes
(a) When _MAT (see Section 6.2.10 ) appears under a Processor Device object (see Section 8.4 ), OSPM
processes the Interrupt Controller Structures returned by _MAT with the types labeled “yes” and ignores
other types.
(b) When _MAT appears under an I/O APIC Device, OSPM processes the Interrupt Controller Structures
returned by _MAT with the types labeled “yes” and ignores other types.
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5.2.12.1 MADT Processor Local APIC / SAPIC Structure Entry Order
OSPM implementations may limit the number of supported processors on multi-processor platforms. OSPM executes
on the boot processor to initialize the platform including other processors. To ensure that the boot processor is sup-
ported post initialization, two guidelines should be followed. The ﬁrst is that OSPM should initialize processors in the
order that they appear in the MADT. The second is that platform ﬁrmware should list the boot processor as the ﬁrst
processor entry in the MADT.
The advent of multi-threaded processors yielded multiple logical processors executing on common processor hard-
ware. ACPI deﬁnes logical processors in an identical manner as physical processors. To ensure that non multi-
threading aware OSPM implementations realize optimal performance on platforms containing multi-threaded proces-
sors, two guidelines should be followed. The ﬁrst is the same as above, that is, OSPM should initialize processors in
the order that they appear in the MADT. The second is that platform ﬁrmware should list the ﬁrst logical processor
of each of the individual multi-threaded processors in the MADT before listing any of the second logical processors.
This approach should be used for all successive logical processors.
Failure of OSPM implementations and platform ﬁrmware to abide by these guidelines can result in both unpredictable
and non optimal platform operation.
5.2.12.2 Processor Local APIC Structure
When using the APIC interrupt model, each processor in the system is required to have a Processor Local APIC record
in the MADT, and a processor device object in the DSDT. OSPM does not expect the information provided in this
table to be updated if the processor information changes during the lifespan of an OS boot. While in the sleeping state,
processors are not allowed to be added, removed, nor can their APIC ID or Flags change. When a processor is not
present, the Processor Local APIC information is either not reported or ﬂagged as disabled.
Table 5.22: Processor Local APIC Structure
Field Byte
Type 1 0 0 Processor Local APIC structure
Length 1 1 8
ACPI Processor UID 1 2 The OS associates this Local APIC Structure with a proces-
sor object in the namespace when the _UID child object of
the processor’s device object (or the ProcessorId listed in the
Processor declaration operator) evaluates to a numeric value
that matches the numeric value in this ﬁeld. Note that the use
of the Processor declaration operator is deprecated. See the
description at the beginning of this section for more informa-
tion.
APIC ID 1 3 The processor’s local APIC ID.

Field Byte
Length 1 1 8
tion.
Flags 4 4 Local APIC ﬂags. See the following table (Table 5.23) for a
description of this ﬁeld.
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Table 5.23: Local APIC Flags
Local APIC Flags Bit
Enabled 1 0 If this bit is set the processor is ready for use. If this bit is
clear and the Online Capable bit is set, system hardware sup-
ports enabling this processor during OS runtime. If this bit
is clear and the Online Capable bit is also clear, this proces-
sor is unusable, and OSPM shall ignore the contents of the
Processor Local APIC Structure.
Online Capable 1 1 The information conveyed by this bit depends on the value of
the Enabled bit. If the Enabled bit is set, this bit is reserved
and must be zero. Otherwise, if this this bit is set, system
hardware supports enabling this processor during OS runtime.
Reserved 30 2 Must be zero.
5.2.12.3 I/O APIC Structure
In an APIC implementation, there are one or more I/O APICs. Each I/O APIC has a series of interrupt inputs, referred
to as INTIn, where the value of n is from 0 to the number of the last interrupt input on the I/O APIC. The I/O APIC
structure declares which global system interrupts are uniquely associated with the I/O APIC interrupt inputs. There is
one I/O APIC structure for each I/O APIC in the system. For more information on global system interrupts see Global
System Interrupts .
Table 5.24: I/O APIC Structure
Field Byte
Type 1 0 1 I/O APIC structure
Length 1 1 12
I/O APIC ID 1 2 The I/O APIC’s ID.
Reserved 1 3 0
I/O APIC Address 4 4 The 32-bit physical address to access this I/O APIC. Each I/O
APIC resides at a unique address.
Global System Interrupt
Base4 8 The global system interrupt number where this I/O APIC’s
interrupt inputs start. The number of interrupt inputs is deter-
mined by the I/O APIC’s Max Redir Entry register.
5.2.12.4 Platforms with APIC and Dual 8259 Support
Systems that support both APIC and dual 8259 interrupt models must map global system interrupts 0-15 to the 8259
IRQs 0-15, except where Interrupt Source Overrides are provided (see Section 5.2.12.5 below). This means that I/O
APIC interrupt inputs 0-15 must be mapped to global system interrupts 0-15 and have identical sources as the 8259
IRQs 0-15 unless overrides are used. This allows a platform to support OSPM implementations that use the APIC
model as well as OSPM implementations that use the 8259 model (OSPM will only use one model; it will not mix
models).
When OSPM supports the 8259 model, it will assume that all interrupt descriptors reporting global system interrupts
0-15 correspond to 8259 IRQs. In the 8259 model all global system interrupts greater than 15 are ignored. If OSPM
implements APIC support, it will enable the APIC as described by the APIC speciﬁcation and will use all reported
global system interrupts that fall within the limits of the interrupt inputs deﬁned by the I/O APIC structures. For more
information on hardware resource conﬁguration see Section 6
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5.2.12.5 Interrupt Source Override Structure
Interrupt Source Overrides are necessary to describe variances between the IA-PC standard dual 8259 interrupt deﬁ-
nition and the platform’s implementation.
It is assumed that the ISA interrupts will be identity-mapped into the ﬁrst I/O APIC sources. Most existing APIC
designs, however, will contain at least one exception to this assumption. The Interrupt Source Override Structure is
provided in order to describe these exceptions. It is not necessary to provide an Interrupt Source Override for every
ISA interrupt. Only those that are not identity-mapped onto the APIC interrupt inputs need be described.
• This speciﬁcation only supports overriding ISA interrupt sources.
For example, if your machine has the ISA Programmable Interrupt Timer (PIT) connected to ISA IRQ 0, but in APIC
mode, it is connected to I/O APIC interrupt input 2, then you would need an Interrupt Source Override where the
source entry is ‘0’ and the Global System Interrupt is ‘2.’
Table 5.25: Interrupt Source Override Structure
Field Byte
Type 1 0 2 Interrupt Source Override
Length 1 1 10
Bus 1 2 0 Constant, meaning ISA
Source 1 3 Bus-relative interrupt source (IRQ)
Global System Interrupt 4 4 The Global System Interrupt that this bus-relative interrupt
source will signal.
Flags 2 8 MPS INTI ﬂags. See the corresponding tabel below for a de-
The MPS INTI ﬂags listed in Table 5.26 are identical to the ﬂags used in the MPS version 1.4 speciﬁcation, Table
4-10. The Polarity ﬂags are the PO bits and the Trigger Mode ﬂags are the EL bits.
Table 5.26: MPS INTI Flags
Local APIC - Flags Bit
Polarity 2 0
Polarity of the APIC I/O input signals:
00 Conforms to the speciﬁcations of the bus (for example,
EISA is active-low for level-triggered interrupts).
01 Active high
10Reserved
11 Active low
Trigger Mode 2 2
Trigger mode of the APIC I/O Input signals:
00 Conforms to speciﬁcations of the bus (For example, ISA
is edge-triggered)
01 Edge-triggered
11 Level-triggered
Reserved 12 4 Must be zero.
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Interrupt Source Overrides are also necessary when an identity mapped interrupt input has a non-standard polarity.
• You must have an interrupt source override entry for the IRQ mapped to the SCI interrupt if this IRQ is not
identity mapped. This entry will override the value in SCI_INT in FADT. For example, if SCI is connected to
IRQ 9 in PIC mode and IRQ 9 is connected to INTIN11 in APIC mode, you should have 9 in SCI_INT in the
FADT and an interrupt source override entry mapping IRQ 9 to INTIN11.
5.2.12.6 Non-Maskable Interrupt (NMI) Source Structure
This structure allows a platform designer to specify which I/O (S)APIC interrupt inputs should be enabled as non-
maskable. Any source that is non-maskable will not be available for use by devices.
Table 5.27: NMI Source Structure
Field Byte
Type 1 0 3 NMI Source
Length 1 1 8
Flags 2 2 Same as MPS INTI ﬂags
Global System Interrupt 4 4 The Global System Interrupt that this NMI will signal.
5.2.12.7 Local APIC NMI Structure
This structure describes the Local APIC interrupt input (LINTn) that NMI is connected to for each of the processors
in the system where such a connection exists. This information is needed by OSPM to enable the appropriate local
APIC entry.
Each Local APIC NMI connection requires a separate Local APIC NMI structure. For example, if the platform has 4
processors with ID 0-3 and NMI is connected LINT1 for processor 3 and 2, two Local APIC NMI entries would be
needed in the MADT.
Table 5.28: Local APIC NMI Structure
Field Byte
Type 1 0 4 Local APIC NMI Structure
Length 1 1 6
ACPI Processor UID 1 2 Value corresponding to the _UID listed in the processor’s de-
vice object, or the Processor ID corresponding to the ID listed
in the processor object. A value of 0xFF signiﬁes that this
applies to all processors in the machine. Note that the use of
the Processor declaration operator is deprecated. See the com-
patibility note in Processor Local x2APIC Structure, and see
Processor (Declare Processor).
Flags 2 3 MPS INTI ﬂags. See Table 5.26 for a description of this ﬁeld.
Local APIC LINT# 1 5 Local APIC interrupt input LINTn to which NMI is con-
nected.
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5.2.12.8 Local APIC Address Override Structure
This optional structure supports 64-bit systems by providing an override of the physical address of the local APIC in
the MADT’s table header, which is deﬁned as a 32-bit ﬁeld.
If deﬁned, OSPM must use the address speciﬁed in this structure for all local APICs (and local SAPICs), rather than
the address contained in the MADT’s table header. Only one Local APIC Address Override Structure may be deﬁned.
Table 5.29: Local APIC Address Override Structure
Field Byte
Type 1 0 5 Local APIC Address Override Structure
Reserved 2 2 Reserved (must be set to zero)
Local APIC Address 8 4 Physical address of Local APIC. For Itanium™ Processor
Family (IPF)-based platforms, this ﬁeld contains the starting
address of the Processor Interrupt Block. See the Intel® Ita-
niumTM Architecture Software Developer’s Manual for more
5.2.12.9 I/O SAPIC Structure
The I/O SAPIC structure is very similar to the I/O APIC structure. If both I/O APIC and I/O SAPIC structures exist
for a speciﬁc APIC ID, the information in the I/O SAPIC structure must be used.
The I/O SAPIC structure uses the I/O APIC ID ﬁeld as deﬁned in the I/O APIC table. The Global System Interrupt

Field Byte
Base ﬁeld remains unchanged but has been moved. The I/O APIC Address ﬁeld has been deleted. A new address and
reserved ﬁeld have been added.
Table 5.30: I/O SAPIC Structure
Field Byte
Type 1 0 6 I/O SAPIC Structure
Length 1 1 16
I/O APIC ID 1 2 I/O SAPIC ID
Reserved 1 3 Reserved (must be zero)
Base4 4 The global system interrupt number where this I/O SAPIC’s
mined by the I/O SAPIC’s Max Redir Entry register.
I/O SAPIC Address 8 8 The 64-bit physical address to access this I/O SAPIC. Each
I/O SAPIC resides at a unique address.
If deﬁned, OSPM must use the information contained in the I/O SAPIC structure instead of the information from the
I/O APIC structure.
If both I/O APIC and an I/O SAPIC structures exist in an MADT, the OEM/platform ﬁrmware writer must prevent
“mixing” I/O APIC and I/O SAPIC addresses. This is done by ensuring that there are at least as many I/O SAPIC
structures as I/O APIC structures and that every I/O APIC structure has a corresponding I/O SAPIC structure (same
APIC ID).
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5.2.12.10 Local SAPIC Structure
The Processor local SAPIC structure is very similar to the processor local APIC structure. When using the SAPIC
interrupt model, each processor in the system is required to have a Processor Local SAPIC record in the MADT, and
a processor device object in the DSDT. OSPM does not expect the information provided in this table to be updated if
the processor information changes during the lifespan of an OS boot. While in the sleeping state, processors are not
allowed to be added, removed, nor can their SAPIC ID or Flags change. When a processor is not present, the Processor
Local SAPIC information is either not reported or ﬂagged as disabled.
Table 5.31: Processor Local SAPIC Structure
Field Byte
Type 1 0 7 Processor Local SAPIC structure
Length 1 1 Length of the Local SAPIC Structure in bytes.
ACPI Processor ID 1 2 OSPM associates the Local SAPIC Structure with a processor
object declared in the namespace using the Processor state-
ment by matching the processor object’s ProcessorID value
with this ﬁeld. The use of the Processor statement is depre-
cated. See the compatibility note in Processor Local x2APIC
Structure, and Processor (Declare Processor).
Local SAPIC ID 1 3 The processor’s local SAPIC ID
Local SAPIC EID 1 4 The processor’s local SAPIC EID
Reserved 3 5 Reserved (must be set to zero)
Flags 4 8 Local SAPIC ﬂags. See Local APIC Flags for a description
of this ﬁeld.
ACPI Processor UID
Value4 12 OSPM associates the Local SAPIC Structure with a processor
object declared in the namespace using the Device statement,
when the _UID child object of the processor device evaluates
to a numeric value, by matching the numeric value with this
ﬁeld.
String>=1 16 OSPM associates the Local SAPIC Structure with a processor
to a string, by matching the string with this ﬁeld. This value
is stored as a null-terminated ASCII string.
5.2.12.11 Platform Interrupt Source Structure
The Platform Interrupt Source structure is used to communicate which I/O SAPIC interrupt inputs are connected to
the platform interrupt sources.
Platform Management Interrupts (PMIs) are used to invoke platform ﬁrmware to handle various events (similar to SMI
in IA-32). The Intel® ItaniumTM architecture permits the I/O SAPIC to send a vector value in the interrupt message
of the PMI type. This value is speciﬁed in the I/O SAPIC Vector ﬁeld of the Platform Interrupt Sources Structure.
INIT messages cause processors to soft reset.
If a platform can generate an interrupt after correcting platform errors (e.g., single bit error correction), the interrupt
input line used to signal such corrected errors is speciﬁed by the Global System Interrupt ﬁeld in the following table.
Some systems may restrict the retrieval of corrected platform error information to a speciﬁc processor. In such cases,
the ﬁrmware indicates the processor that can retrieve the corrected platform error information through the Processor
ID and EID ﬁelds in the structure below. OSPM is required to program the I/O SAPIC redirection table entries with
the Processor ID, EID values speciﬁed by the ACPI system ﬁrmware. On platforms where the retrieval of corrected
5.2. ACPI System Description Tables 135Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
platform error information can be performed on any processor, the ﬁrmware indicates this capability by setting the
CPEI Processor Override ﬂag in the Platform Interrupt Source Flags ﬁeld of the structure below. If the CPEI Processor
Override Flag is set, OSPM uses the processor speciﬁed by Processor ID, and EID ﬁelds of the structure below only
as a target processor hint and the error retrieval can be performed on any processor in the system. However, ﬁrmware
is required to specify valid values in Processor ID, EID ﬁelds to ensure backward compatibility.
If the CPEI Processor Override ﬂag is clear, OSPM may reject a ejection request for the processor that is targeted for
the corrected platform error interrupt. If the CPEI Processor Override ﬂag is set, OSPM can retarget the corrected
platform error interrupt to a different processor when the target processor is ejected.
Note that the _MAT object can return a buffer containing Platform Interrupt Source Structure entries. It is allowed for
such an entry to refer to a Global System Interrupt that is already speciﬁed by a Platform Interrupt Source Structure
provided through the static MADT table, provided the value of platform interrupt source ﬂags are identical.
Refer to the ItaniumTM Processor Family System Abstraction Layer (SAL) Speciﬁcation for details on handling the
Corrected Platform Error Interrupt.
Table 5.32: Platform Interrupt Source Structure
Field Byte
Type 1 0 8 Platform Interrupt Source structure
Flags 2 2 MPS INTI ﬂags. See Table 5.26 for a description of this ﬁeld.
Interrupt Type 1 4 1 PMI | 2 INIT | 3 Corrected Platform Error Interrupt. All
other values are reserved.
Processor ID 1 5 Processor ID of destination.
Processor EID 1 6 Processor EID of destination.
I/O SAPIC Vector 1 7 Value that OSPM must use to program the vector ﬁeld of the
I/O SAPIC redirection table entry for entries with the PMI
interrupt type.
Global System Interrupt 4 8 The Global System Interrupt that this platform interrupt will
signal.
Platform Interrupt Source
Flags4 12 Platform Interrupt Source Flags. See Platform Interrupt
Source Flags for a description of this ﬁeld
Table 5.33: Platform Interrupt Source Flags
Platform Interrupt
Source FlagsBit
CPEI Processor Override 1 0 When set, indicates that retrieval of error information is al-
lowed from any processor and OSPM is to use the informa-
tion provided by the processor ID, EID ﬁelds of the Platform
Interrupt Source Structure as a target processor hint.
Reserved 31 1 Must be zero.
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5.2.12.12 Processor Local x2APIC Structure
The Processor X2APIC structure is very similar to the processor local APIC structure. When using the X2APIC
interrupt model, logical processors are required to have a processor device object in the DSDT and must convey the
processor’s APIC information to OSPM using the Processor Local X2APIC structure.
• [Compatibility note] On some legacy OSes, Logical processors with APIC ID values less than 255 (whether in
XAPIC or X2APIC mode) must use the Processor Local APIC structure to convey their APIC information to
OSPM, and those processors must be declared in the DSDT using the Processor() keyword. Logical processors
with APIC ID values 255 and greater must use the Processor Local x2APIC structure and be declared using the
Device() keyword.
OSPM does not expect the information provided in this table to be updated if the processor information changes
during the lifespan of an OS boot. While in the sleeping state, logical processors must not be added or removed, nor
can their X2APIC ID or x2APIC Flags change. When a logical processor is not present, the processor local X2APIC
information is either not reported or ﬂagged as disabled.
The format of x2APIC structure is listed in Section 5.2.12.12 .
Table 5.34: Processor Local x2APIC Structure
Field Byte
Type 1 0 9 Processor Local x2APIC structure
Reserved 2 2 Reserved - Must be zero
X2APIC ID 4 4 The processor’s local x2APIC ID.
Flags 4 8 Same as Local APIC ﬂags. See Local APIC Flags for a de-
ACPI Processor UID 4 12 OSPM associates the X2APIC Structure with a processor ob-

Field Byte
ject declared in the namespace using the Device statement,
ﬁeld.
5.2.12.13 Local x2APIC NMI Structure
The Local APIC NMI and Local x2APIC NMI structures describe the interrupt input (LINTn) that NMI is connected
to for each of the logical processors in the system where such a connection exists. Each NMI connection to a processor
requires a separate NMI structure. This information is needed by OSPM to enable the appropriate APIC entry.
NMI connection to a logical processor with local x2APIC ID 255 and greater requires an X2APIC NMI structure.
NMI connection to a logical processor with an x2APIC ID less than 255 requires a Local APIC NMI structure. For
example, if the platform contains 8 logical processors with x2APIC IDs 0-3 and 256-259 and NMI is connected LINT1
for processor 3, 2, 256 and 257 then two Local APIC NMI entries and two X2APIC NMI entries must be provided in
the MADT.
The Local APIC NMI structure is used to specify global LINTx for all processors if all logical processors have x2APIC
ID less than 255. If the platform contains any logical processors with an x2APIC ID of 255 or greater then the Local
X2APIC NMI structure must be used to specify global LINTx for ALL logical processors. The format of x2APIC
NMI structure is listed in Section 5.2.12.13 .
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Table 5.35: Local x2APIC NMI Structure
Field Byte
Type 1 0 0AH Local x2APIC NMI Structure
Flags 2 2 Same as MPS INTI ﬂags. See MPS INTI Flags For a descrip-
ACPI Processor UID 4 4 UID corresponding to the ID listed in the processor Device
object. A value of 0xFFFFFFFF signiﬁes that this applies to
all processors in the machine.
Local x2APIC LINT# 1 8 Local x2APIC interrupt input LINTn to which NMI is con-
nected.
Reserved 3 9 Reserved - Must be zero.
5.2.12.14 GIC CPU Interface (GICC) Structure
In the GIC interrupt model, logical processors are required to have a Processor Device object in the DSDT, and must
convey each processor’s GIC information to the OS using the GICC structure.
The format of the GICC structure is shown in the following table.
Table 5.36: GICC Structure
Field Byte
Type 1 0 0xB GICC structure
Length 1 1 82
CPU Interface Number 4 4 GIC’s CPU Interface Number. In GICv1/v2 implementations,
this value matches the bit index of the associated processor
in the GIC distributor’s GICD_ITARGETSR register. For
GICv3/4 implementations this ﬁeld must be provided by the
platform, if compatibility mode is supported. If it is not sup-
ported by the implementation, then this ﬁeld must be zero.
ACPI Processor UID 4 8 The OS associates this GICC Structure with a processor de-
vice object in the namespace when the _UID child object of
the processor device evaluates to a numeric value that matches
the numeric value in this ﬁeld.
Flags 4 12 See GICC CPU Interface Flags.
Parking Protocol Version 4 16 Version of the ARM-Processor Parking Protocol imple-
mented. See http://ueﬁ.org/acpi. The document link is listed
under “Multiprocessor Startup for ARM Platforms” For sys-
tems that support PSCI exclusively and do not support the
parking protocol, this ﬁeld must be set to 0.
Performance Interrupt
GSIV4 20 The GSIV used for Performance Monitoring Interrupts
Parked Address 8 24 The 64-bit physical address of the processor’s Parking Proto-
col mailbox
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Table 5.36 – continued from previous page
Physical Base Address 8 32 On GICv1/v2 systems and GICv3/4 systems in GICv2 com-
patibility mode, this ﬁeld holds the 64-bit physical address at
which the processor can access this GIC CPU Interface. If
provided here, the “Local Interrupt Controller Address” ﬁeld
in the MADT must be ignored by the OSPM.
GICV 8 40 Address of the GIC virtual CPU interface registers. If the plat-
form is not presenting a GICv2 with virtualization extensions
this ﬁeld can be 0.
GICH 8 48 Address of the GIC virtual interface control block registers.
If the platform is not presenting a GICv2 with virtualization
extensions this ﬁeld can be 0.
VGIC Maintenance inter-
rupt4 56 GSIV for Virtual GIC maintenance interrupt
GICR Base Address 8 60 On systems supporting GICv3 and above, this ﬁeld holds the
64-bit physical address of the associated Redistributor. If all
of the GIC Redistributors are in the always-on power domain,
GICR structures should be used to describe the Redistributors
instead, and this ﬁeld must be set to 0. If a GICR structure is
present in the MADT then this ﬁeld must be ignored by the
OSPM.
MPIDR 8 68
This ﬁelds follows the MPIDR formatting of ARM
architecture. If ARMv7 architecture is used then the format
must be as follows:
Bits [63:24] Must be zero
Bits [23:16] Aff2 : Match Aff2 of target processor MPIDR
Bits [15:8] Aff1 : Match Aff1 of target processor MPIDR
Bits [7:0] Aff0 : Match Aff0 of target processor MPIDR
For platforms implementing ARMv8 the format must be:
Bits [63:40] Must be zero
Bits [39:32] Aff3 : Match Aff3 of target processor MPIDR
Bits [31:24] Must be zero
Processor Power Efﬁ-
ciency Class1 76 Describes the relative power efﬁciency of the associated pro-
cessor. Lower efﬁciency class numbers are more efﬁcient than
higher ones (e.g. efﬁciency class 0 should be treated as more
efﬁcient than efﬁciency class 1). However, absolute values
of this number have no meaning: 2 isn’t necessarily half as
efﬁcient as 1.
Reserved 1 77 Must be zero.
SPE overﬂow Interrupt 2 78 Statistical Proﬁling Extension buffer overﬂow GSIV . This in-
terrupt is a level triggered PPI. Zero if SPE is not supported
by this processor.
TRBE Interrupt 2 80 Trace Buffer Extension interrupt GSIV . This interrupt is a
level triggered PPI. Zero if TRBE feature is not supported
by this processor. NOTE: This ﬁeld was introduced in ACPI
Speciﬁcation version 6.5.
5.2. ACPI System Description Tables 139Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.37: GICC CPU Interface Flags
GIC Flags Bit
Enabled 1 0 If this bit is set, the processor is ready for use. If this bit is
clear and the Online Capable bit is set, the system supports
enabling this processor during OS runtime. If this bit is clear
and the Online Capable bit is also clear, this processor is un-
usable, and the operating system support will not attempt to
use it.
Mode1 1 0 - Level-triggered | 1 - Edge-Triggered
VGIC Maintenance Inter-
rupt Mode Flags1 2 0 - Level-triggered | 1 - Edge-Triggered
Online Capable 1 3 The information conveyed by this bit depends on the value of
and must be zero. Otherwise, if this bit is set, the system
supports enabling this processor later during OS runtime.
Reserved 28 4 Must be zero.
Note: All processors are assumed to be always physically present
5.2.12.15 GIC Distributor (GICD) Structure
ACPI represents all wired interrupts as “ﬂat” values known as global system interrupts (GSIVs) as described in Section
5.2.13 . On ARM-based systems the Generic Interrupt Controller (GIC) manages interrupts on the system. Each
interrupt is identiﬁed in the GIC by an interrupt identiﬁer (INTID). ACPI GSIVs map one to one to GIC INTIDs for
peripheral interrupts, whether shared (SPI) or private (PPI). The GIC distributor structure describes the GIC distributor
to the OS. One, and only one, GIC distributor structure must be present in the MADT for an ARM based system.
The format of the GICD structure is listed in Table 5.38 .
Table 5.38: GICD Structure
Field Byte
Type 1 0 0xC GICD structure
Length 1 1 24
GIC ID 4 4 This GIC Distributor’s hardware ID
Physical Base Address 8 8 The 64-bit physical address for this Distributor
System Vector Base 4 16 Reserved - Must be zero
5.2. ACPI System Description Tables 140Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.38 – continued from previous page
Field Byte
GIC version 1 20
0x00: No GIC version is speciﬁed, fall back to hardware
discovery for GIC version
0x01: GICv1
0x02: GICv2
0x03: GICv3
0x04: GICv4
0x05-0xFF, Reserved for future use.
Reserved 3 21 Must be zero
5.2.12.16 GIC MSI Frame Structure
Each GICv2m MSI frame consists of a 4k page which includes registers to generate message signaled interrupts to

Field Byte
Field Byte
an associated GIC distributor. The frame also includes registers to discover the set of distributor lines which may be
signaled by MSIs from that frame. A system may have multiple MSI frames, and separate frames may be deﬁned for
secure and non-secure access. This structure must only be used to describe non-secure MSI frames.
The format of the GIC MSI Frame Structure is listed in Section 5.2.12.16 .
Table 5.39: GIC MSI Frame Structure
Field Byte
Type 1 0 0xD GIC MSI Frame structure
GIC MSI Frame ID 4 4 GIC MSI Frame ID. In a system with multiple GIC MSI
frames, this value must be unique to each one.
Physical Base Address 8 8 The 64-bit physical address for this MSI Frame
Flags 4 16 GIC MSI Frame Flags. See Section 5.2.12.16
SPI Count 2 20 SPI Count used by this frame. Unless the SPI Count Select
ﬂag is set to 1 this value should match the lower 16 bits of the
MSI_TYPER register in the frame.
SPI Base 2 22 SPI Base used by this frame. Unless the SPI Base Select ﬂag
is set to 1 this value should match the upper 16 bits of the
Table 5.40: GIC MSI Frame Flags
GIC MSI Frame Flags Bit
SPI Count/Base Select 1 0 0: The SPI Count and Base ﬁelds should be ignored, and the
actual values should be queried from the MSI_TYPER regis-
ter in the associated GIC MSI frame. | 1: The SPI Count and
Base values override the values speciﬁed in the MSI_TYPER
register in the associated GIC MSI frame.
5.2. ACPI System Description Tables 141Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.12.17 GIC Redistributor (GICR) Structure
The GICR Structure is described in Table 5.41. This structure enables the discovery of GIC Redistributor base ad-
dresses by providing the Physical Base Address of a page range containing the GIC Redistributors. More than one
GICR Structure may be presented in the MADT. GICR structures should only be used when describing GIC imple-
mentations which conform to version 3 or higher of the GIC architecture and which place all Redistributors in the
always-on power domain.When a GICR structure is presented, the OSPM must ignore the GICR Base Address ﬁeld
of the GICC structures (see the following table).
Table 5.41: GICR Structure
Field Byte
Type 1 0 0xE GICR structure
Discovery Range Base
Address8 4 The 64-bit physical address of a page range containing all GIC
Redistributors
Discovery Range Length 4 12 Length of the GIC Redistributor Discovery page range.
5.2.12.18 GIC Interrupt Translation Service (ITS) Structure
The GIC ITS is optionally supported in GICv3/v4 implementations. The format of the GIC ITS Structure is listed in
Table 5.42 :
Table 5.42: GIC ITS Structure
Field Byte
Type 1 0 0xF GIC ITS structure
Length 1 1 20
GIC ITS ID 4 4 GIC ITS ID. In a system with multiple GIC ITS units, this
value must be unique to each one.
Physical Base Address 8 8 The 64-bit physical address for the Interrupt Translation Ser-
vice
Reserved 4 16 Reserved - Must be zero
5.2.12.19 Multiprocessor Wakeup Structure
The platform ﬁrmware publishes a multiprocessor wakeup structure to let the bootstrap processor wake up application
processors with a mailbox. The mailbox is memory that the ﬁrmware reserves so that each processor can have the OS
send a message to them.
During system boot, the ﬁrmware puts the application processors in a state to check the mailbox. The shared mailbox is
a 4K-aligned 4K-size memory block allocated by the ﬁrmware in the ACPINvs memory. The ﬁrmware is not allowed
to modify the mailbox location when the ﬁrmware transfer the control to an OS loader. The mailbox is broken down
into two 2KB sections: an OS section and a ﬁrmware section.
The OS section can only be written by OS and read by the ﬁrmware, except the command ﬁeld. The application
processor need clear the command to Noop(0) as the acknowledgement that the command is received. The ﬁrmware
must cache the content in the mailbox which might be used later before clear the command such as WakeupVector.
Only after the command is changed to Noop(0), the OS can send the next command. The ﬁrmware section must be
5.2. ACPI System Description Tables 142Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
considered read-only to the OS and is only to be written to by the ﬁrmware. All data communication between the OS
and FW must be in little endian format.
The OS section contains command, ﬂags, APIC ID, and a wakeup address. After the OS detects the processor number
from the MADT table, the OS may prepare the wakeup routine, ﬁll the wakeup address ﬁeld in the mailbox, indicate
which processor need to be wakeup in the APID ID ﬁeld, and send wakeup command. Once an application processor
detects the wakeup command and its own APIC ID, the application processor will jump to the OS-provided wakeup
address. The application processor will ignore the command if the APIC ID does not match its own.
For each application processor, the mailbox can be used only once for the wakeup command. After the application pro-
cess takes the action according to the command, this mailbox will no longer be checked by this application processor.
Other processors can continue using the mailbox for the next command.
Table 5.43: Multiprocessor Wakeup Structure
Field Byte
Type 1 0 0x10 Multiprocessor Wakeup structure
MailBoxVersion 2 2 Version of the mailbox. 0 for this version of the spec.
Reserved 4 4 Must be 0.
MailBoxAddress 8 8 Physical address of the mailbox. It must be in ACPINvs. It must
also be 4K bytes aligned. See Table 5.44 for the Mailbox deﬁnition.
Table 5.44: Multiprocessor Wakeup Mailbox Structure
Field Byte
Command 2 0
0: Noop - no operation.
1: Wakeup – jump to the wakeup vector.
2-0xFFFF: Reserved
Reserved 2 2 Must be 0.
ApicId 4 4 The processor’s local APIC ID. The application processor
shall check if the ApicId ﬁeld matches its own APIC ID. The
application processor shall ignore the command in case of
APIC ID mismatch.
WakeupVector 8 8
The wakeup address for application processor(s).
For Intel processors, the execution environment is:
Interrupts must be disabled.
RFLAGES.IF set to 0.
Long mode enabled.
Paging mode is enabled and physical memory for
waking vector is identity mapped (virtual address
equals physical address)
Waking vector must be contained within one physical
page.
Selectors are set to ﬂat and otherwise not used.
ReservedForOs 2032 16 Reserved for OS use.
ReservedForFirmware 2048 2048 Reserved for ﬁrmware use.
5.2. ACPI System Description Tables 143Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.12.20 Core Programmable Interrupt Controller (CORE PIC) Structure
Each processor in Loongarch system has a Core Programmable Interrupt Controller record in the MADT, and a pro-
cessor device object in the DSDT. The format of the CORE PIC structure is shown in the following table.
Table 5.45: CORE PIC Structure format
Field Byte
Type 1 0 0x11 Core Programmable Interrupt Controller Structure
Length 1 1 Length of the Core Programmable Interrupt Controller Structure in
bytes.
Version 1 2
0: Invalid
1: CORE PIC v1
ACPI Processor ID 4 3 The OS associates this CORE PIC Structure with a processor device
object in the namespace when the _UID child object of the processor
device evaluates to a numeric value that matches the numeric value
Physical Processor
ID4 7 The processor core physical id. 0xFFFFFFFF is invalid value. If
invalid, this processor is unusable, and OSPM shall ignore Core
Interrupt Controller Structure.
Flags 4 11 CORE PIC ﬂags. See CORE PIC Flags for a description of this
ﬁeld.
Table 5.46: CORE PIC Flags
Field Byte
Enabled 1 0
If Physical Processor ID is invalid, OSPM shall ignore this ﬁeld,
and OSPM shall ignore Core Programmable Interrupt Controller
If Physical Processor ID is valid and if this Enabled bit is clear, this
processor will be unusable on booting, and can be online during
OS runtime.
If Physical Processor ID is valid and if this Enabled bit is set, this
processor is ready for using.
5.2. ACPI System Description Tables 144Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.12.21 Legacy I/O Programmable Interrupt Controller(LIO PIC) Structure
In early Loongson CPUs, Legacy I/O Programmable Interrupt Controller (LIO PIC) routes interrupts from HT PIC to
CORE PIC. The format of the LIO PIC structure is shown in the following table.
Table 5.47: LIO PIC Structure format
Field Byte
Type 1 0 0x12 Legacy I/O Programmable Interrupt Controller Structure

Field Byte
Enabled 1 0
Field Byte
Length 1 1 Length of the Legacy I/O Programmable Interrupt Controller Struc-
ture in bytes.
Version 1 2
0: Invalid
1: LIO PIC v1
Base Address 8 3 The base address of LIO PIC registers.
Size 2 11 The register space size of LIO PIC.
Cascade vector 2 13 This ﬁeld described routed vectors on CORE PIC from LIO PIC
vectors.
Cascade vector
mapping8 15 This ﬁeld described the vectors of LIO PIC routed to the related
vector of parent speciﬁed by Cascade vector ﬁeld.
5.2.12.22 HyperTransport Programmable Interrupt Controller (HT PIC) Structure
In early Loongson CPUs, HT Programmable Interrupt Controller (HT PIC) routes interrupts from BIO PIC and MSI
PIC to LIO PIC. The format of the HT PIC structure is shown in the following table.
Table 5.48: HT PIC Structure format
Field Byte
Type 1 0 0x13 HT Programmable Interrupt Controller Structure
Length 1 1 Length of the HT Programmable Interrupt Controller Structure in
bytes.
Version 1 2
0: Invalid
1: HT PIC v1
Base Address 8 3 The base address of HT PIC registers.
Size 2 11 The register space size of HT PIC.
Cascade vector 8 13 This ﬁeld described routed vector on LIO PIC from HT PIC vectors.
5.2. ACPI System Description Tables 145Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.12.23 Extend I/O Programmable Interrupt Controller (EIO PIC) Structure
In newer generation Loongson CPUs, Extend I/O Programmable Interrupt Controller (EIO PIC) replaces the combi-
nation of HT PIC and part of LIO PIC, and routes interrupts from BIO PIC and MSI PIC to CORE PIC directly. The
format of the EIO PIC structure is shown in the following table.
Table 5.49: EIO PIC Structure format
Field Byte
Type 1 0 0x14 Extend I/O Programmable Interrupt Controller Structure
Length 1 1 Length of the Extend I/O Programmable Interrupt Controller Struc-
Version 1 2
0: Invalid
1: EIO PIC v1
Cascade vector 1 3 This ﬁeld describes routed vector on CORE PIC from EIO PIC vec-
tors.
Node 1 4 The node ID of the node connected to bridge.
Node Map 8 5 Each bit indicates one node that can receive interrupt routing from
the EIO PIC.
5.2.12.24 MSI Programmable Interrupt Controller (MSI PIC) Structure
MSI Programmable Interrupt Controller Structure is deﬁned to support MSI of PCI/PCIE devices in system. The
format of the MSI PIC structure is shown in the following table.
Table 5.50: MSI PIC Structure format
Field Byte
Type 1 0 0x15 Message Programmable Interrupt Controller Structure
Length 1 1 Length of the Message Programmable Interrupt Controller Structure
in bytes.
Version 1 2
0: Invalid
1: MSI PIC v1
Message Address 8 3 The physical address for MSI.
Start 4 11 The start vector allocated for MSI from global vectors of HT PIC or
EIO PIC.
Count 4 15 The count of allocated vectors for MSI.
5.2. ACPI System Description Tables 146Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.12.25 Bridge I/O Programmable Interrupt Controller (BIO PIC) Structure
BIO PIC (Bridge I/O Programmable Interrupt Controller) manages legacy IRQs of chipset devices, and routed them
to HT PIC or EIO PIC. The format of the BIO PIC structure is shown in the following table.
Table 5.51: BIO PIC Structure format
Field Byte
Type 1 0 0x16 Bridge I/O Programmable Interrupt Controller Structure
Length 1 1 Length of the Bridge I/O Programmable Interrupt Controller Struc-
Version 1 2
0: Invalid
1: BIO PIC v1
Base Address 8 3 The base address of BIO PIC registers.
Size 2 11 The register space size of BIO PIC.
Hardware ID 2 13 The hardware ID of BIO PIC.
GSI base 2 15 The global system interrupt number from which this BIO PIC’s in-
terrupt inputs start. For GSI of each interrupt input, GSI = GSI base
+ interrupt input vector of BIO PIC.
5.2.12.26 LPC Programmable Interrupt Controller (LPC PIC) Structure
LPC PIC (Low Pin Count Programmable Interrupt Controller) is responsible for handling ISA IRQs of old legacy
devices such as PS/2 mouse, keyboard and UARTs for Loongarch machines. The format of the LPC PIC structure is
shown in the following table.
Table 5.52: LPC PIC Structure format
Field Byte
Type 1 0 0x17 LPC Programmable Interrupt Controller Structure
Length 1 1 Length of the LPC Programmable Interrupt Controller Structure in
bytes.
Version 1 2
0: Invalid
1: LPC PIC v1
Base Address 8 3 The base address of LPC PIC registers.
Size 2 11 The register space size of LPC PIC.
Cascade vector 2 13 This ﬁeld described routed vector on BIO PIC from LPC PIC vec-
tors.
5.2. ACPI System Description Tables 147Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.13 Global System Interrupts
Global System Interrupts can be thought of as ACPI Plug and Play IRQ numbers. They are used to virtualize interrupts
in tables and in ASL methods that perform resource allocation of interrupts. Do not confuse global system interrupts
with ISA IRQs although in the case of the IA-PC 8259 interrupts they correspond in a one-to-one fashion.
There are two interrupt models used in ACPI-enabled systems. The ﬁrst model is the APIC model. In the APIC model,
the number of interrupt inputs supported by each I/O APIC can vary. OSPM determines the mapping of the Global
System Interrupts by determining how many interrupt inputs each I/O APIC supports and by determining the global
system interrupt base for each I/O APIC as speciﬁed by the I/O APIC Structure. OSPM determines the number of
interrupt inputs by reading the Max Redirection register from the I/O APIC. The global system interrupts mapped to
that I/O APIC begin at the global system interrupt base and extending through the number of interrupts speciﬁed in
the Max Redirection register. There is exactly one I/O APIC structure per I/O APIC in the system. This mapping is
depicted in the following ﬁgure.
5.2. ACPI System Description Tables 148Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 5.3: APIC-Global System Interrupts
5.2. ACPI System Description Tables 149Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The other interrupt model is the standard AT style mentioned above which uses ISA IRQs attached to a master/slave
pair of 8259 PICs. The system vectors correspond to the ISA IRQs. The ISA IRQs and their mappings to the 8259
pair are part of the AT standard and are well deﬁned. This mapping is depicted in the following ﬁgure.
Fig. 5.4: 8259 - Global System Interrupts
5.2.14 Smart Battery Table (SBST)
If the platform supports batteries as deﬁned by the Smart Battery Speciﬁcation 1.0 or 1.1, then an Smart Battery Table
(SBST) is present. This table indicates the energy level trip points that the platform requires for placing the system
into the speciﬁed sleeping state and the suggested energy levels for warning the user to transition the platform into
a sleeping state. Notice that while Smart Batteries can report either in current (mA/mAh) or in energy (mW/mWh),
OSPM must set them to operate in energy (mW/mWh) mode so that the energy levels speciﬁed in the SBST can be
used. OSPM uses these tables with the capabilities of the batteries to determine the different trip points. For more
precise deﬁnitions of these levels, see Section 3.9.3
Table 5.53: Smart Battery Description Table (SBST) Format
Field Byte
Header
Signature 4 0 ‘SBST’ Signature for the Smart Battery Description Table.
Length 4 4 Length, in bytes, of the entire SBST
OEM Table ID 8 16 For the SBST, the table ID is the manufacturer model ID.
OEM Revision 4 24 OEM revision of SBST for supplied OEM Table ID.
Warning Energy Level 4 36 OEM suggested energy level in milliWatt-hours (mWh) at
which OSPM warns the user.
Low Energy Level 4 40 OEM suggested platform energy level in mWh at which
OSPM will transition the system to a sleeping state.
5.2. ACPI System Description Tables 150Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.53 – continued from previous page
Field Byte
Critical Energy Level 4 44 OEM suggested platform energy level in mWh at which
OSPM performs an emergency shutdown.
5.2.15 Embedded Controller Boot Resources Table (ECDT)
This optional table provides the processor-relative, translated resources of an Embedded Controller. The presence of

Field Byte
this table allows OSPM to provide Embedded Controller operation region space access before the namespace has been
evaluated. If this table is not provided, the Embedded Controller region space will not be available until the Embedded
Controller device in the AML namespace has been discovered and enumerated. The availability of the region space
can be detected by providing a _REG method object underneath the Embedded Controller device.
Table 5.54: Embedded Controller Boot Resources Table Format
Field Byte
Header
Signature 4 0 ‘ECDT’ Signature for the Embedded Controller Table.
Length 4 4 Length, in bytes, of the entire Embedded Controller Table
OEM Table ID 8 16 For the Embedded Controller Table, the table ID is the manu-
facturer model ID.
OEM Revision 4 24 OEM revision of Embedded Controller Table for supplied
OEM Table ID.
EC_CONTROL 12 36 Contains the processor relative address, represented in
Generic Address Structure format, of the Embedded Con-
troller Command/Status register. | Note: Only System I/O
space and System Memory space are valid for values for Ad-
dress_Space_ID.
EC_DATA 12 48 Contains the processor-relative address, represented in
troller Data register. | Note: Only System I/O space
and System Memory space are valid for values for Ad-
UID 4 60 Unique ID-Same as the value returned by the _UID under the
device in the namespace that represents this embedded con-
troller.
GPE_BIT 1 64 The bit assignment of the SCI interrupt within the GPEx_STS
register of a GPE block described in the FADT that the em-
bedded controller triggers.
EC_ID Variable 65 ASCII, null terminated, string that contains a fully qualiﬁed
reference to the namespace object that is this embedded con-
troller device (for example, “\_SB.PCI0.ISA.EC”). Quotes
are omitted in the data ﬁeld.
5.2. ACPI System Description Tables 151Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ACPI OSPM implementations supporting Embedded Controller devices must also support the ECDT. ACPI 1.0 OSPM
implementation will not recognize or make use of the ECDT. The following example code shows how to detect whether
the Embedded Controller operation regions are available in a manner that is backward compatible with prior versions
of ACPI/OSPM.
Device(EC0)
{
Name(REGC,Ones)
Method(_REG,2)
{
If(Arg0 == 3)
{
REGC = Arg1
}
}
}
Method(ECAV,0)
{
If (REGC == Ones)
{
If (_REV >=2)
{
Return(One)
}
Else
{
Return(Zero)
}
}
Else
{
Return(REGC)
}
}
To detect the availability of the region, call the ECA V method. For example:
If (\_SB.PCI0.EC0.ECAV())
{
//...regions are available...
}
else
{
//...regions are notavailable...
}
5.2. ACPI System Description Tables 152Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.16 System Resource Afﬁnity Table (SRAT)
This optional table provides information that allows OSPM to associate the following types of devices with system
locality / proximity domains and clock domains:
• processors,
• memory ranges (including those provided by hot-added memory devices),
• generic initiators (e.g. heterogeneous processors and accelerators, GPUs, and I/O devices with integrated com-
pute or DMA engines), and
• generic ports (e.g. host bridges that can dynamically discover new initiators and instantiate new memory range
targets).
On NUMA platforms, SRAT information enables OSPM to optimally conﬁgure the operating system during a point
in OS initialization when evaluation of objects in the ACPI Namespace is not yet possible.
OSPM evaluates the SRAT only during OS initialization. The Local APIC ID / Local SAPIC ID / Local x2APIC ID
or the GICC ACPI Processor UID of all processors started at boot time must be present in the SRAT. If the Local
APIC ID / Local SAPIC ID / Local x2APIC ID or the GICC ACPI Processor UID of a dynamically added processor
is not present in the SRAT, a _PXM object must exist for the processor’s device or one of its ancestors in the ACPI
Namespace.
Note : SRAT is the place where proximity domains are deﬁned, and _PXM provides a mechanism to associate a device
object (and its children) to an SRAT-deﬁned proximity domain.
See Section 6.2.14 (_PXM Proximity) for more information.
Table 5.55: Static Resource Afﬁnity Table Format
Field Byte
Header
Signature 4 0 ‘SRAT’. Signature for the System Resource Afﬁnity Table.
Length 4 4 Length, in bytes, of the entire SRAT. The length implies the
number of Entry ﬁelds at the end of the table
Revision 1 8 3
OEM Table ID 8 16 For the System Resource Afﬁnity Table, the table ID is the
manufacturer model ID.
OEM Revision 4 24 OEM revision of System Resource Afﬁnity Table for supplied
Reserved 4 36 Reserved to be 1 for backward compatibility
Reserved 8 40 Reserved
Static Resource Alloca-
tion Structure[n]— 48 A list of static resource allocation structures for the plat-
form. See Processor Local APIC/SAPIC Afﬁnity Structure,
Memory Afﬁnity Structure, Processor Local x2APIC Afﬁnity
Structure, and GICC Afﬁnity Structure.
5.2. ACPI System Description Tables 153Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.16.1 Processor Local APIC/SAPIC Afﬁnity Structure
The Processor Local APIC/SAPIC Afﬁnity structure provides the association between the APIC ID or SAPIC ID/EID
of a processor and the proximity domain to which the processor belongs. See the Processor Local APIC/SAPIC
Afﬁnity structure.
Table 5.56: Processor Local APIC/SAPIC Afﬁnity Structure
Field Byte
Type 1 0 0 Processor Local APIC/SAPIC Afﬁnity Structure
Proximity Domain [7:0] 1 2 Bit [7:0] of the proximity domain to which the processor be-
longs.
APIC ID 1 3 The processor local APIC ID.
Flags 4 4 Flags - Processor Local APIC/SAPIC Afﬁnity Structure. See
Processor Local APIC/SAPIC Afﬁnity Structure for a descrip-
Local SAPIC EID 1 8 The processor local SAPIC EID.
Proximity Domain [31:8] 3 9 Bit [31:8] of the proximity domain to which the processor be-
longs.
Clock Domain 4 12 The clock domain to which the processor belongs. See _CDM
(Clock Domain).
Table 5.57: Flags - Processor Local APIC/SAPIC Afﬁnity Structure
Field Bit
Enabled 1 0 If clear, the OSPM ignores the contents of the Processor Local
APIC/SAPIC Afﬁnity Structure. This allows system ﬁrmware
to populate the SRAT with a static number of structures but
only enable them as necessary.
5.2.16.2 Memory Afﬁnity Structure
The Memory Afﬁnity structure provides the following topology information statically to the operating system:
• The association between a memory range and the proximity domain to which it belongs
• Information about whether the memory range can be hot-plugged.
See the table below for more details.
Table 5.58: Memory Afﬁnity Structure
Field Byte
Type 1 0 1 Memory Afﬁnity Structure
Length 1 1 40
Proximity Domain 4 2 Integer that represents the proximity domain to which the
memory range belongs.
Reserved 2 6 Reserved
Base Address Low 4 8 Low 32 Bits of the Base Address of the memory range
5.2. ACPI System Description Tables 154Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.58 – continued from previous page
Field Byte
Base Address High 4 12 High 32 Bits of the Base Address of the memory range
Length Low 4 16 Low 32 Bits of the length of the memory range.
Length High 4 20 High 32 Bits of the length of the memory range.
Reserved 4 24 Reserved
Flags 4 28 Flags - Memory Afﬁnity Structure. Indicates whether the re-
gion of memory is enabled and can be hot plugged. See the
corresponding table below for more details.
Reserved 8 32 Reserved
Table 5.59: Flags - Memory Afﬁnity Structure
Field Bit
Enabled 1 0 If clear, the OSPM ignores the contents of the Memory Afﬁn-
ity Structure. This allows system ﬁrmware to populate the
SRAT with a static number of structures but only enable then
as necessary.
Hot Pluggable 1 1 The information conveyed by this bit depends on the value of
the Enabled bit. If the Enabled bit is set and the Hot Pluggable
bit is also set. The system hardware supports hot-add and hot-
remove of this memory region If the Enabled bit is set and
the Hot Pluggable bit is clear, the system hardware does not

Field Bit
support hot-add or hot-remove of this memory region. If the
Enabled bit is clear, the OSPM will ignore the contents of the
Memory Afﬁnity Structure
NonV olatile 1 2 If set, the memory region represents Non-V olatile memory
Reserved 29 3 Must be zero.
5.2.16.3 Processor Local x2APIC Afﬁnity Structure
The Processor Local x2APIC Afﬁnity structure provides the association between the local x2APIC ID of a processor
and the proximity domain to which the processor belongs. Section 5.2.16.3 provides the details of the Processor Local
x2APIC Afﬁnity structure.
Table 5.60: Processor Local x2APIC Afﬁnity Structure
Field Byte
Type 1 0 2 Processor Local x2APIC Afﬁnity Structure
Proximity Domain 4 4 The proximity domain to which the logical processor belongs.
X2APIC ID 4 8 The processor local x2APIC ID.
Flags 4 12 Same as Processor Local APIC/SAPIC Afﬁnity Structure
ﬂags. See the corresponding table below for a description of
this ﬁeld.
Clock Domain 4 16 The clock domain to which the logical processor belongs. See
_CDM (Clock Domain).
Reserved 4 20 Reserved.
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On x86-based platforms, the OSPM uses the Hot Pluggable bit to determine whether it should shift into PAE mode to
allow for insertion of hot-plug memory with physical addresses over 4 GB.
5.2.16.4 GICC Afﬁnity Structure
The GICC Afﬁnity Structure provides the association between the ACPI Processor UID of a processor and the prox-
imity domain to which the processor belongs. Section 5.2.16.4 provides the details of the GICC Afﬁnity structure.
Table 5.61: GICC Afﬁnity Structure
Field Byte
Type 1 0 3 GICC Afﬁnity Structure.
Length 1 1 18
Proximity Domain 4 2 The proximity domain to which the logical processor belongs.
ACPI Processor UID 4 6 The ACPI Processor UID of the associated GICC.
Flags 4 10 Flags - GICC Afﬁnity Structure. See the corresponding table
below for a description of this ﬁeld.
Clock Domain 4 14 The clock domain to which the logical processor belongs. See
Table 5.62: Flags - GICC Afﬁnity Structure
Field Bit
Enabled 1 0 If clear, the OSPM ignores the contents of the GICC Afﬁnity
Structure. This allows system ﬁrmware to populate the SRAT
with a static number of structures but only enable them as
5.2.16.5 GIC Interrupt Translation Service (ITS) Afﬁnity Structure
The GIC ITS Afﬁnity Structure provides the association between a GIC ITS and a proximity domain. This enables
the OSPM to discover the memory that is closest to the ITS, and use that in allocating its management tables and
command queue. The ITS is identiﬁed using an ID matching a declaration of a GIC ITS in the MADT, see Section
5.2.12.18 for details. The following table provides the details of the GIC ITS Afﬁnity structure.
Table 5.63: Architecture Speciﬁc Afﬁnity Structure
Field Byte
Type 1 0 4 GIC ITS Afﬁnity Structure
Proximity domain 4 2 Integer that represents the proximity domain to which the GIC ITS be-
longs to.
Reserved 2 6 Reserved must be zero
ITS ID 4 8 ITS ID matching a GIC ITS entry in the MADT
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5.2.16.6 Generic Initiator Afﬁnity Structure
The Generic Initiator Afﬁnity Structure provides the association between a generic initiator and the proximity domain
to which the initiator belongs.
Support of Generic Initiator Afﬁnity Structures by OSPM is optional, and the platform may query whether the OS
supports it via the _OSC method. See Section 6.2.11.2 for more details.
Table 5.64: Generic Initiator Afﬁnity Structure
Field Byte
Type 1 0 5 Generic Initiator Structure.
Length 1 1 32
Reserved 1 2 Reserved and must be zero.
Device Handle Type 1 3
Device Handle Type:
0 - ACPI Device Handle
1 - PCI Device Handle
2-255 - Reserved
Proximity Domain 4 4 The proximity domain to which the generic initiator belongs.
Device Handle 16 8 Device Handle of the Generic Initiator. See Device Handle -
ACPI for a description of the ACPI Device Handle, and De-
vice Handle - PCI for a description of the PCI Device Handle.
Flags 4 24 Flags - Generic Initiator/Port Afﬁnity Structure. See Section
5.2.16.7 for a description of this ﬁeld.
Reserved 4 28 Reserved and must be zero.
Table 5.65: Device Handle - ACPI
Field Byte
ACPI _HID 8 0 The _HID value
ACPI _UID 4 8 The _UID value
Reserved 4 12 Must be zero.
Table 5.66: Device Handle - PCI
Field Byte
PCI Segment 2 0 PCI segment number. For systems with fewer than 255 PCI buses,
this number must be 0.
PCI BDF Number 2 2
PCI Bus Number (Bits 7:0 of Byte 2)
PCI Device Number (Bits 7:3 of Byte 3)
PCI Function Number (Bits 2:0 of Byte 3)
Reserved 12 4 Must be zero
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5.2.16.7 Generic Port Afﬁnity Structure
The Generic Port Afﬁnity Structure provides an association between a proximity domain number and a device handle
representing a Generic Port (e.g. CXL Host Bridge, or similar device that hosts a dynamic topology of memory ranges
and/or initiators).
Support of Generic Port Afﬁnity Structures by an OSPM is optional.
Table 5.67: Generic Port Afﬁnity Structure Table
Field Byte
Type 1 0 6 Generic Port Structure
Device Handle Type 1 3 Device Handle Type: See Section 5.2.16.6 for the possible device
handle types and their format.
Proximity Domain 4 4 The proximity domain to identify the performance of this port in the
HMAT.
Device Handle 16 8 Device Handle of the Generic Port: see Table 5.65 and Table 5.66
for a description of this ﬁeld.
Flags 4 24 See Table 5.68 for a description of this ﬁeld.
Table 5.68: Flags - Generic Initiator/Port Afﬁnity Structure
Field Bit
Enabled 1 0 If clear, the OSPM ignores the contents of the Generic Ini-
tiator/Port Afﬁnity Structure. This allows system ﬁrmware to
populate the SRAT with a static number of structures, but only
enable them as necessary.
Architectural transactions 1 1 If set, indicates that the Generic Initiator/Port can initiate all
transactions at the same architectural level as the host (e.g.
full atomicOps, cache coherency, virtual memory, etc.) See
implementation note following.
Note: If a generic device with coherent memory is attached to the system, it is recommended to deﬁne afﬁnity
structures for both the device and memory associated with the device. They both may have the same proximity
domain.
If a generic device is marked with “architectural transactions,” the Generic Initiator supports all applicable architectural
mechanisms for cache synchronization, atomicOps and virtual memory, etc. - fully equivalent to the memory model
of the host processor (with potentially different but equivalent instruction mechanisms in its ISA).
Supporting a subset of architectural transactions would be only permissible if the lack of the feature does not have
material consequences to the memory model. One example is lack of cache coherency support on the GI, if the GI
does not have any local caches to global memory that require invalidation through the data fabric.
OS is assured that the GI adheres to the memory model as the host processor architecture related to observable trans-
actions to memory for memory fences and other synchronization operations issued on either initiator or host.
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5.2.17 System Locality Information Table (SLIT)
This optional table provides a matrix that describes the relative distance (memory latency) between all System Local-
ities, which are also referred to as Proximity Domains. Systems employing a Non Uniform Memory Access (NUMA)
architecture contain collections of hardware resources including for example, processors, memory, and I/O buses, that
comprise what is known as a “NUMA node”. Processor accesses to memory or I/O resources within the local NUMA
node is generally faster than processor accesses to memory or I/O resources outside of the local NUMA node.
The value of each Entry[i,j] in the SLIT table, where i represents a row of a matrix and j represents a column of a
matrix, indicates the relative distances from System Locality / Proximity Domain i to every other System Locality j in
the system (including itself).
The i,j row and column values correlate to Proximity Domain values in the System Resource Afﬁnity Table (SRAT),

and to values returned by _PXM objects in the ACPI namespace. See Section 5.2.16 for more information.
The entry value is a one-byte unsigned integer. The relative distance from System Locality i to System Locality j is
the i*N + j entry in the matrix, where N is the number of System Localities. Except for the relative distance from a
System Locality to itself, each relative distance is stored twice in the matrix. This provides the capability to describe
the scenario where the relative distances for the two directions between System Localities is different.
The diagonal elements of the matrix, the relative distances from a System Locality to itself are normalized to a value
of 10. The relative distances for the non-diagonal elements are scaled to be relative to 10. For example, if the relative
distance from System Locality i to System Locality j is 2.4, a value of 24 is stored in table entry i*N+ j and in j*N+ i,
where N is the number of System Localities.
If one locality is unreachable from another, a value of 255 (0xFF) is stored in that table entry. Distance values of 0-9
are reserved and have no meaning.
Table 5.69: SLIT Format
Field Byte
Header
- Signature 4 0 ‘SLIT’. Signature for the System Locality Distance Informa-
- Length 4 4 Length, in bytes, of the entire System Locality Distance In-
formation Table.
- Revision 1 8 1
- Checksum 1 9 Entire table must sum to zero.
- OEMID 6 10 OEM ID.
- OEM Table ID 8 16 For the System Locality Information Table, the table ID is the
- OEM Revision 4 24 OEM revision of System Locality Information Table for sup-
plied OEM Table ID.
- Creator ID 4 28 Vendor ID of utility that created the table. For the DSDT,
RSDT, SSDT, and PSDT tables, this is the ID for the ASL
Compiler.
- Creator Revision 4 32 Revision of utility that created the table. For the DSDT,
RSDT, SSDT, and PSDT tables, this is the revision for the
Number of System Local-
ities8 36 Indicates the number of System Localities in the system.
Entry[0][0] 1 44 Matrix entry (0,0), contains a value of 10.
. . . . . .
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Table 5.69 – continued from previous page
Field Byte
Entry[0][Number of Sys-
tem Localities-1]1 Matrix entry (0, Number of System Localities-1)
Entry[1][0] 1 Matrix entry (1,0)
. . . . . .
Entry [Number of System
Localities-1] [Number of
System Localities-1]1 Matrix entry (Number of System Localities-1, Number of
System Localities-1), contains a value of 10
5.2.18 Corrected Platform Error Polling Table (CPEP)
Platforms may contain the ability to detect and correct certain operational errors while maintaining platform func-
tion. These errors may be logged by the platform for the purpose of retrieval. Depending on the underlying hard-
ware support, the means for retrieving corrected platform error information varies. If the platform hardware supports
interrupt-based signaling of corrected platform errors, the MADT Platform Interrupt Source Structure describes the
Corrected Platform Error Interrupt (CPEI). See Section 5.2.12.11. Alternatively, OSPM may poll processors for cor-
rected platform error information. Error log information retrieved from a processor may contain information for all
processors within an error reporting group. As such, it may not be necessary for OSPM to poll all processors in the
system to retrieve complete error information. This optional table provides information that allows OSPM to poll only
the processors necessary for a complete report of the platform’s corrected platform error information.
Table 5.70: Corrected Platform Error Polling Table Format
Field Byte
Header
- Signature 4 0 ‘CPEP’. Signature for the Corrected Platform Error
Polling Table.
- Length 4 4 Length, in bytes, of the entire CPET. The length implies
the number of Entry ﬁelds at the end of the table
- OEM Table ID 8 16 For the Corrected Platform Error Polling Table, the table
ID is the manufacturer model ID.
- OEM Revision 4 24 OEM revision of Corrected Platform Error Polling Table
for supplied OEM Table ID.
- Creator ID 4 28 Vendor ID of utility that created the table.
- Creator Revision 4 32 Revision of utility that created the table.
Reserved 8 36 Reserved, must be 0.
CPEP Processor Structure[n] — 44 A list of Corrected Platform Error Polling Processor
structures for the platform. See corresponding table be-
low.
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5.2.18.1 Corrected Platform Error Polling Processor Structure
The Corrected Platform Error Polling Processor structure provides information on the speciﬁc processors OSPM polls
for error information. See corresponding table below for details of the Corrected Platform Error Polling Processor
5.2. ACPI System Description Tables 161Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.71: Corrected Platform Error Polling Processor Structure
Field Byte
Type 1 0 0 Corrected Platform Error Polling Processor structure for
APIC/SAPIC based processors
Length 1 1 8
Processor ID 1 2 Processor ID of destination.
Processor EID 1 3 Processor EID of destination.
Polling Interval 4 4 Platform-suggested polling interval (in milliseconds)
5.2.19 Maximum System Characteristics Table (MSCT)
This section describes the format of the Maximum System Characteristic Table (MSCT), which provides OSPM with
information characteristics of a system’s maximum topology capabilities. If the system maximum topology is not
known up front at boot time, then this table is not present. OSPM will use information provided by the MSCT only
when the System Resource Afﬁnity Table (SRAT) exists. The MSCT must contain all proximity and clock domains
deﬁned in the SRAT.
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Table 5.72: Maximum System Characteristics Table (MSCT) Format
Field Byte
LengthByte Off-
Header
- Signature 4 0 ‘MSCT’ Signature for the Maximum Sys-
tem Characteristics Table.
Length 4 4 Length, in bytes, of the entire MSCT.
OEM Table ID 8 16 For the MSCT, the table ID is the manufac-
turer model ID.
OEM Revision 4 24 OEM revision of MSCT for supplied OEM
Table ID.
For tables containing Deﬁnition Blocks, this
is the ID for the ASL Compiler.
Creator Revision 4 32 Revision of utility that created the table. For
tables containing Deﬁnition Blocks, this is
the revision for the ASL Compiler.
Offset to Proximity Domain Informa-
tion Structure [OffsetProxDomInfo]4 36 Offset in bytes to the Proximity Domain In-
formation Structure table entry.
Maximum Number of Proximity Do-
mains4 40 Indicates the maximum number of Proxim-
ity Domains ever possible in the system.
The number reported in this ﬁeld is (max-
imum domains - 1). For example if there
are 0x10000 possible domains in the sys-
tem, this ﬁeld would report 0xFFFF.
Maximum Number of Clock Domains 4 44 Indicates the maximum number of Clock
Domains ever possible in the system. The
number reported in this ﬁeld is (maximum
domains - 1). See Section 6.2.1.
Maximum Physical Address 8 48 Indicates the maximum Physical Address
ever possible in the system. Note: this is
the top of the reachable physical address.
Proximity Domain Information Struc-
ture[Maximum Number of Proximity
Domains]– [OffsetProx-
DomInfo]A list of Proximity Domain Information for
this implementation. The structure format is
deﬁned in the Maximum Proximity Domain
Information Structure section.
5.2.19.1 Maximum Proximity Domain Information Structure
The Maximum Proximity Domain Information Structure is used to report system maximum characteristics. It is likely
that these characteristics may be the same for many proximity domains, but they can vary from one proximity domain
to another. This structure optimizes to cover the former case, while allowing the ﬂexibility for the latter as well. These
structures must be organized in ascending order of the proximity domain enumerations. All proximity domains within
the Maximum Number of Proximity Domains reported in the MSCT must be covered by one of these structures.
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Table 5.73: Maximum Proximity Domain Information Structure
Field Byte
Revision 1 0 1
Length 1 1 22
Proximity Domain Range (low) 4 2 The starting proximity domain for the proximity domain
range that this structure is providing information.

Field Byte
Proximity Domain Range (high) 4 6 The ending proximity domain for the proximity domain
Maximum Processor Capacity 4 10 The Maximum Processor Capacity of each of the Prox-
imity Domains speciﬁed in the range. A value of 0
means that the proximity domains do not contain pro-
cessors. This ﬁeld must be >= the number of processor
entries for the domain in the SRAT.
Maximum Memory Capacity 8 14 The Maximum Memory Capacity (size in bytes) of the
Proximity Domains speciﬁed in the range. A value of 0
means that the proximity domains do not contain mem-
ory.
5.2.20 ACPI RAS Feature Table (RASF)
The following table describes the structure of ACPI RAS Feature Table.
Table 5.74: RASF Table format
Field Byte
Header
- Signature 4 0 ‘RASF’ is Signature for RAS Feature Table
- Length 4 4 Length in bytes for entire RASF. The length implies the
- Checksum 1 9 Entire table must sum to zero
- OEMID 6 10 OEM ID
- OEM Table ID 8 16 The table ID is the manufacturer model ID
- OEM Revision 4 24 OEM revision of table for supplied OEM Table ID
- Creator ID 4 28 Vendor ID of utility that created the table
- Creator Revision 4 32 Revision of utility that created the table
RASF Speciﬁc Entries
- RASF Platform Communica-
tion Channel Identiﬁer12 36 Identiﬁer of the RASF Platform Communication Chan-
nel. OSPM should use this value to identify the PCC
Sub channel structure in the RASF table
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5.2.20.1 RASF PCC Sub Channel Identiﬁer
RASF PCC Sub Channel Identiﬁer is used by the OSPM to identify the PCC Sub channel structure. RASF table
references its PCC Subspace by this identiﬁer as shown in Table 5.74 .
5.2.20.2 Using PCC registers
OSPM will write PCC registers by ﬁlling in the register value in PCC sub channel space and issuing a PCC Execute
command. See Table 5.76.
To minimize the cost of PCC transactions, OSPM should read or write all registers in the same PCC subspace via a
single read or write command.
5.2.20.3 RASF Communication Channel
RASF Action Entries are deﬁned in the PCC sub channel as below.
Table 5.75: RASF Platform Communication Channel Shared Mem-
ory Region
Field Byte
Signature 4 0 The PCC Signature of 0x52415346 (corresponds to
ASCII signature of RASF)
Command 2 4 PCC command ﬁeld; see PCC Command Codes used by
RASF Platform Communication Channel, and the Plat-
form Communications Channel (PCC).
Status 2 6 PCC status ﬁeld. See Platform Communications Chan-
nel (PCC).
Communication Space:
Version 2 8 Byte 0 - Minor Version | Byte 1 - Major Version
RAS Capabilities 16 10 Bit Map describing the platform RAS capabilities as
shown in Platform RAS Capabilities. The Platform pop-
ulates this ﬁeld. The OSPM uses this ﬁeld to determine
the RAS capabilities of the platform.
Set RAS Capabilities 16 26 Bit Map of the RAS features for which the OSPM is
invoking the command. The Bit Map is described in
Section 5.2.20.4. OSPM sets the bit corresponding to a
RAS capability to invoke a command on that capability.
The bitmap implementation allows OSPM to invoke a
command on each RAS feature supported by the plat-
form at the same time.
Number of RASF Parameter
blocks2 42 The Number of parameter blocks will depend on how
many RAS Capabilities the Platform Supports. Typ-
ically, there will be one Parameter Block per RAS
Feature, using which that feature can be managed by
OSPM.
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Table 5.75 – continued from previous page
Field Byte
Set RAS Capabilities Status 4 44 Status:
0000b = Success
0001b = Not Valid
0010b = Not Supported
0011b = Busy
0100b = FailedF
0101b = Aborted
0110b = Invalid Data
Parameter Blocks Varies
(N
Bytes)48 Start of the parameter blocks, the structure of which
is shown in the Parameter Block Structure for PA-
TROL_SCRUB. These parameter blocks are used as
communication mailbox between the OSPM and the
platform, and there is 1 parameter block for each RAS
feature. NOTE: There can be only on parameter block
per type.
Table 5.76: PCC Command Codes used by RASF Platform Commu-
nication Channel
Command Description
0x00 Reserved
0x01 Execute RASF Command.
0x02-0xFF All other values are reserved.
5.2.20.4 Platform RAS Capabilities
The following table deﬁnes the Platform RAS capabilities:
Table 5.77: Platform RAS Capabilities Bitmap
Bit RAS Feature Description
0 Hardware based patrol scrub supported Indicates that the platform supports hardware
based patrol scrub of DRAM memory
1 Hardware based patrol scrub supported and ex-
posed to softwareIndicates that the platform supports hardware
based patrol scrub of DRAM memory and plat-
form exposes this capability to software using
this RASF mechanism
2-127 Reserved Reserved for future use
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5.2.20.5 Parameter Block
The following table describes the Parameter Blocks. The structure is used to pass parameters for controlling the
corresponding RAS Feature.
Each RAS Feature is assigned a TYPE number, which is the bit index into the RAS capabilities bitmap described in
Table 5.77 .
Table 5.78: Parameter Block Structure for PATROL_SCRUB
Field Byte
Type 2 0 0x0000 - Patrol scrub
Version 2 2 Byte 0 - Minor Version | Byte 1 - Major Version
Length 2 4 Length, in bytes of the entire parameter block structure
Patrol Scrub Command (IN-
PUT)2 6
0x01 - GET_PATROL_PARAMETERS
0x02 - START_PATROL_SCRUBBER
0x03 - STOP_PATROL_SCRUBBER
Requested Address
Range(INPUT)16 8 OSPM Speciﬁes the BASE (Bytes 7-0) and SIZE
(Bytes 15-8) of the address range to be patrol
scrubbed. OSPM sets this parameter for the follow-
ing commands: GET_PATROL_PARAMETERS and
START_PATROL_SCRUBBER
Actual Address Range (OUT-
PUT)16 24 The platform returns this value in response to
GET_PATROL_PARAMETERS. The platform calcu-
lates the nearest patrol scrub boundary address from
where it can start. This range should be a superset of
the Requested Address Range. BASE (Bytes 7-0) and
SIZE (Bytes 15-8) of the address
Flags (OUTPUT) 2 40
The platform returns this value in response to
GET_PATROL_PARAMETERS:
Bit [0]: Will be set if patrol scrubber is already running
for address range speciﬁed in “Actual Address Range”
Bits [3:1]: Current Patrol Speeds, if Bit [0] is set:
000b - Slow
100b - Medium
111b - Fast
All other combinations are reserved.
Bits [15:4]: RESERVED
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Table 5.78 – continued from previous page
Requested Speed (INPUT) 1 42
The OSPM Sets this ﬁeld as follows, for the
START_PATROL_SCRUBBER command:
Bits [2:0]: Requested Patrol Speeds
000b - Slow
111b - Fast
Bits [7:3]: RESERVED
5.2.20.5.1 Sequence of Operations:
The following sequence documents the steps for OSPM to identify whether the platform supports hardware based
patrol scrub and invoke commands to request hardware to patrol scrub the speciﬁed address range.
1. Identify whether the platform supports hardware based patrol scrub and exposes the support to software by
reading the RAS capabilities bitmap in the RASF table.
2. Call GET_PATROL_PARAMETERS, by setting the Requested Address Range.
3. Platform Returns Actual Address Range and Flags.
4. Based on the above two data, if the OPSM decides to start the patrol scrubber or change the speed of the patrol
scrubber, then the OSPM calls START_PATROL_SCRUBBER, by setting the Requested Address Range and
Requested Speed.
5.2.21 ACPI RAS2 Feature Table (RAS2)
The RAS2 table provides interfaces for platform RAS features. RAS2 offers the same services as RASF, but is more
scalable than the latter. In particular, RAS2 supports independent RAS controls and capabilities for a given RAS
feature for multiple instances of the same component in a given system.
The platform can support either RAS2 or RASF but not both.
Table 5.79: RAS2 Table format
Field Byte Length Byte Offset Description
Header
- Signature 4 0 Signature is set to ‘RAS2’ for RAS Feature
2 Table.
- Length 4 4 Length in bytes for entire RAS2. The
length implies the number of PCC descrip-
tors ﬁelds at the end of the table
- OEM Revision 4 24 OEM revision of table for supplied OEM
Table ID
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Header
2 Table.
Table ID
Table 5.79 – continued from previous page
RAS2 Speciﬁc Entries
-Reserved 2 36 Reserved, should be zero.
- Number of PCC descriptors 2 38 Number of PCC descriptors.
- RAS2 Platform Communica-
tion Channel (PCC) Descriptor
ListN*8 40 List of PCC descriptors.
5.2.21.1 Common Deﬁnitions
5.2.21.1.1 RAS2 Platform Communication Channel Descriptor
RAS2 supports multiple PCC channels, where a channel is dedicated to a given component instance. The RAS2 PCC
descriptor speciﬁes the PCC sub-space associated with a speciﬁc RAS feature. The RAS feature type speciﬁes the
RAS feature.
Table 5.80: RAS2 Platform Communication Channel Descriptor for-
mat
PCC Identiﬁer 1 0 Identiﬁer of the RAS2 Platform Communication Channel.
OSPM should use this value as an index into the subspace
array within the PCCT table.
Reserved 2 1 Reserved, must be zero.
Feature Type 1 3 RAS feature type. RAS feature types are deﬁned in Table
5.81.
Instance 4 4 Identiﬁer for the system component instance that this RAS
feature is associated with.
Table 5.81: RAS Feature Types
RAS Feature Type Description
0x00 RAS features related to memory.
0x01-0x7F Reserved for future standard RAS feature types deﬁned by this speciﬁcation.
0x80-0xFF Vendor-deﬁned RAS feature types.
5.2.21.1.2 Using PCC Registers
command (see Table 5.82). To minimize the cost of PCC transactions, OSPM should read or write all registers in the
same PCC subspace via a single read or write command.
Table 5.82: PCC Command Codes used by RAS2 Platform Commu-
0x01 Execute RAS2 Command.
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5.2.21.1.3 RAS2 Platform Communication Channel
The RAS2 platform communication channel format is deﬁned below (Table 5.83).
Table 5.83: RAS2 Platform Communication Channel Shared Mem-
ory Region
Signature 4 0 The PCC signature. The signature of a subspace is com-
puted by a bitwise-or of the value 0x50434300 with the
subspace ID. For example, subspace 3 has the signature
0x50434303.
RAS2. See Table 5.82 and Section 14.
Status 2 6 PCC status ﬁeld. See Section 14.
Communication
Space
- Version 2 8
Byte 0 - Minor Version
Byte 1 - Major Version
For this revision, this ﬁeld must be set to 0x0000
- RAS Features 16 10 Bitmap describing the platform RAS features as shown
in Table 5.84. The deﬁnition of the bits is system com-
ponent speciﬁc. For example, Table 5.86 shows the
bitmap deﬁnitions for Memory RAS features. The Plat-
form populates this ﬁeld to indicate which RAS features
for the given feature type are supported for this system
component instance. The OSPM uses this ﬁeld for RAS
feature discovery.
- Set RAS Capabili-
ties16 26 Bit Map of the RAS features for which the OSPM is
Section 5.2.21.1.4. OSPM sets the bit corresponding to
a RAS capability to invoke a command on that capabil-
ity. The bitmap implementation allows OSPM to invoke
a command on each RAS feature supported by the plat-
form at the same time. {need links}
- Number of RAS2
Parameter Blocks2 42 The Number of parameter blocks will depend on how
OSPM.
5.2. ACPI System Description Tables 170Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.83 – continued from previous page
ties Status4 44
Status:
- Parameter Blocks Varies (N
bytes)48 Start of the parameter blocks, the structure of which
feature. NOTE: There can be only one parameter block
per type.
5.2.21.1.4 RAS2 Platform RAS Feature Bitmap (generic)
The following table (Table 5.84) shows a generic deﬁnition of the Platform RAS features supported for a given system
component type. The exact deﬁnitions are speciﬁc for each system component type. For example, Table 5.86 shows
the bitmap deﬁnitions for Memory RAS features.
Table 5.84: Platform RAS Feature Bitmap
Bit RAS feature Description
0 Feature 1 RAS Feature 1
1 Feature 2 RAS Feature 2
. . . . . . . . .
127 Feature 128 RAS Feature 128
5.2.21.2 Memory RAS Features – Feature Type 0
Memory RAS features apply to RAS capabilities, controls and operations that are speciﬁc to memory. These features
might be provided through one or more PCC sub-spaces. RAS2 sub-spaces for memory-speciﬁc RAS features have a
Feature Type of 0x00 (Memory).
Table 5.85: RAS2 Platform Communication Channel Descriptor for
Memory RAS Features
Reserved 2 1 0
Feature Type 1 3 0x00: Memory. See Table 5.81
5.2. ACPI System Description Tables 171Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.85 – continued from previous page
Instance 4 4 Proximity domain that this RAS feature is associated with.
This ﬁeld must match the ACPI SRAT table deﬁnitions. See
Section 5.2.16.
Table 5.86: Platform RAS Feature Bitmap for Memory RAS
Bit RAS Feature Feature Name Description
0 Hardware-based memory scrub
featurePATROL_SCRUB Indicates that the platform supports
hardware-based memory scrubbing.
OSPM must set this bit in the Set RAS
Capabilities ﬁeld to request memory
scrubbing service.
1 Logical to Physical Address
translation featureLA2PA_TRANSLATION Indicates that the platform supports
logical address to physical address
translation service. OSPM must set this
bit in the Set RAS Capabilities ﬁeld to
request address translation for a logical
address.
5.2.21.2.1 Hardware-based Memory Scrubbing
The platform can use this feature to expose controls and capabilities associated with hardware-based memory scrub
engines. Modern scalable platforms have complex memory systems with a multitude of memory controllers that
are in turn associated with NUMA domains. It is also common for RAS errors related to memory to be associated
with NUMA domains, where the NUMA domain functions as a FRU identiﬁer. This feature thus provides memory
scrubbing at a NUMA domain granularity.
The following are supported:
• Independent memory scrubbing controls for each NUMA domain, identiﬁed using its proximity domain.
• Provision for background (patrol) scrubbing of the entire memory system, as well as on-demand scrubbing for
a speciﬁc region of memory.
Table 5.87: Parameter Block Structure for PATROL_SCRUB
Field Byte
Type 2 0 0x0000 – Hardware-based memory scrub RAS feature.
Version 2 2
For this format of the parameter block, this ﬁeld should
be set to 0x0001.
PUT)2 6
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Table 5.87 – continued from previous page
Range(INPUT)16 8
OSPM Speciﬁes the BASE (Bytes 7-0) and SIZE
(Bytes 15-8) of the address range to be patrol scrubbed.
If OSPM requests default scrubbing through Bit 0 of
the Conﬁgure patrol scrubbing ﬁeld, then this ﬁeld
must be ignored by the platform.
OSPM sets this parameter for the following commands:
GET_PATROL_PARAMETERS,
START_PATROL_SCRUBBER.
PUT)16 24
GET_PATROL_PARAMETERS. The platform
calculates the nearest patrol scrub boundary address
from where it can start. This range should be a superset
of the Requested Address Range.
This ﬁeld must be ignored by the OSPM if it is being
returned in response to a request to enable default
scrubbing through Bit 0 of the Conﬁgure patrol
scrubbing ﬁeld.
BASE (Bytes 7-0) and SIZE (Bytes 15-8) of the
address.
Flags (OUTPUT) 4 40
Bit [0]: Will be set if memory scrubber is already

PUT)16 24
address.
running for address range speciﬁed in “Actual Address
Range”.
Bits [31:1]: Reserved, must be zero.
Scrub Parameters (OUTPUT) 4 44
Bits [7:0]: Current scrub rate that is in effect on the
memory region speciﬁed in “Actual Address Range”. If
OSPM requested background scrubbing, then this ﬁeld
will reﬂect the current background patrol scrubbing
rate.
Bits [15:8]: Minimum scrub rate supported.
Bits [23:16]: Maximum scrub rate supported
Bits [31:24]: Reserved, must be zero.
5.2. ACPI System Description Tables 173Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Conﬁgure Scrub Parameters
(INPUT)4 48
Bit[0]: Request background patrol scrubbing.
Bits [7:1]: Reserved, must be zero.
Bits [15:8]: Requested scrub rate, must be in the range
(minimum scrub rate, maximum scrub rate).
Bits [31:16]: Reserved, must be zero.
5.2.21.2.2 Logical to Physical Address Translation Service
The platform can use this feature to provide support for translation of logical addresses to physical addresses. In
some platform implementations, individual components in the platform may be restricted to a local view of memory.
When these components detect and log an error, they may be limited to only recording the logical address of the error.
However, the OSPM requires addresses in the global, physical address space so that it can perform error recovery and
isolation. This service provides the address translation required for this purpose.
Table 5.88: Parameter Block Structure for LA2PA_TRANSLATION
Field Byte
Type 2 0
0x0001 – LA to PA address translation service
Version 2 2
For this format of the parameter block, this ﬁeld should be set to
0x0001.
Length 2 4
Length, in bytes of the entire parameter block structure
Address Translation
Command (INPUT)2 6
0x01 - GET_LA2PA_TRANSLATION
Sub-instance Identi-
ﬁer8 8
If there are multiple constituent components that fall within the
proximity domain, this ﬁeld can be used to point to the speciﬁc
component to which the LA applies.
Logical Address
(INPUT)8 16
OSPM speciﬁes the logical address in this ﬁeld the
GET_LA2PA_TRANSLATION command.
Physical Address
(OUTPUT)8 24
The platform returns the physical address in this ﬁeld in response
to GET_LA2PA_TRANSLATION.
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Table 5.88 – continued from previous page
Status (OUTPUT) 4 32
GET_LA2PA_TRANSLATION:
0x0000_0000: Indicates that the translation succeeded.
0x0000_0001: Indicates that the translation failed, and the Physical
Address returned by the platform may not be valid.
Other values are reserved for future use by this speciﬁcation.
5.2.22 Memory Power State Table (MPST)
The following table describes the structure of new ACPI memory power state table (MPST). This table deﬁnes the
memory power node topology of the conﬁguration, as described earlier in Section 1 . The conﬁguration includes
specifying memory power nodes and their associated information. Each memory power node is speciﬁed using address
ranges, supported memory power states. The memory power states will include both hardware controlled and software
controlled memory power states. There can be multiple entries for a given memory power node to support non
contiguous address ranges. MPST table also deﬁnes the communication mechanism between OSPM and platform
runtime ﬁrmware for triggering software controlled memory powerstate transitions implemented in platform runtime
ﬁrmware.
The following ﬁgure provides a structured organization overview of MPST table.
5.2. ACPI System Description Tables 175Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 5.5: MPST ACPI Table Overview
5.2. ACPI System Description Tables 176Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.89: MPST Table Structure
Field Byte
Header
- Signature 4 0 ‘MPST’. Signature for Memory Power State Table
- Length 4 4 Length in bytes for entire MPST. The length im-
plies the number of Entry ﬁelds at the end of the
table
- OEM Table ID 8 16 For the memory power state table, the table ID is
the manufacturer model ID
- OEM Revision 4 24 OEM revision of memory power state Table for
supplied OEM Table ID
Memory PCC
- MPST Platform Communication
Channel Identiﬁer1 36 Identiﬁer of the MPST Platform Communication
Channel.
-Reserved 3 37 Reserved
Memory Power Node
- Memory Power Node Count 2 40 Number of Memory power Node structure entries
-Reserved 2 42 Reserved
- Memory Power Node Structure
[Memory Power Node Count]— — This ﬁeld provides information on the memory
power nodes present in the system. The informa-
tion includes memory node id, power states sup-
ported & associated latencies. Further details of
this ﬁeld are speciﬁed in Memory Power Node.
Memory Power State Characteris-
tics
- Memory Power State Characteristics
Count2 — Number of Memory power State Characteristics
Structure entries
-Reserved 2 Reserved
Structure [m]— — This ﬁeld provides information of memory power
states supported in the system. The informa-
tion includes power consumed, transition laten-
cies, relevant ﬂags.
5.2.22.1 MPST PCC Sub Channel
The MPST PCC Sub Channel Identiﬁer value provided by the platform in this ﬁeld should be programmed to the Type
ﬁeld of PCC Communications Subspace Structure. The MPST table references its PCC Subspace in a given platform
by this identiﬁer, as shown in Table 5.89.
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5.2.22.1.1 Using PCC registers
command. See the table below. All other command values are reserved.
Table 5.90: PCC Command Codes used by MPST Platform Commu-
0x00-0x02 All other values are reserved.
0x03 Execute MPST Command.
0x04-0xFF All other values are reserved.
Table 5.91: MPST Platform Communication Channel Shared Mem-
ory Region
Field Byte
Signature 4 0 The PCC signature. The signature of a sub-
space is computed by a bitwise-or of the value
0x50434300 with the subspace ID. For example,
subspace 3 has signature 0x50434303.
Command 2 4 PCC command ﬁeld: see Section 14
Status 2 6 PCC status ﬁeld: see Section 14
Communication Space
MEMORY_POWER_-
COMMAND_REGISTER4 8 Memory region for OSPM to write the requested
memory power state.
Write:
1 to this field to GET the memory
˓→power state
2 to this field to set the memory
3 - GET AVERAGE POWER CONSUMED
4 - GET MEMORY ENERGY CONSUMED
5.2. ACPI System Description Tables 178Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.91 – continued from previous page
Field Byte
STATUS_REGISTER4 12 Bits [3:0]: Status (speciﬁc to MEM-
ORY_POWER_COMMAND_REGISTER):
- 0000b = Success
- 0001b = Not Valid
- 0010b = Not Supported
- 0011b = Busy
- 0100b = Failed
- 0101b = Aborted
- 0110b = Invalid Data
- Other values reserved
Bit [4]: Background Activity spe-
ciﬁc to the following MEM-
ORY_POWER_COMMAND_REGISTER
value:
0b = inactive
1b = background memory activity is
˓→inprogress
Bits [31:5]: Reserved
POWER_STATE_ID 4 16 On completion of a GET operation, OSPM reads
the current platform state ID from this ﬁeld. Prior
to a SET operation, OSPM populates this ﬁeld
with the power state value which needs to be trig-
gered. Power State values will be based on the
platform capability.
MEMORY_POWER_NODE_ID 4 20 This ﬁeld identiﬁes Memory power node number
for the command.
MEMORY_ENERGY_CONSUMED 8 24 This ﬁeld returns the energy consumed by
the memory that constitutes the MEM-
ORY_POWER_NODE_ID speciﬁed in the
previous ﬁeld. A value of all 1s in this ﬁeld
indicates that platform does not implement this
ﬁeld.
EXPECTED_A VERAGE_-
POWER_CONSUMED8 32 This ﬁeld returns the expected average power con-
sumption for the memory constituted by MEM-
ORY_POWER_NODE_ID. A value of all 1s in
this ﬁeld indicates that platform does not imple-
ment this ﬁeld.
Note: OSPM should use the ratio of computed memory power consumed to expected average power consumed in
determining the memory power management action.

ﬁeld.
5.2. ACPI System Description Tables 179Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.22.2 Memory Power State
Memory Power State represents the state of a memory power node (which maps to a memory address range) while the
platform is in the G0 working state. Memory power node could be in active state named MPS0 or in one of the power
manage states MPS1-MPSn.
It should be noted that active memory power state (MPS0) does not preclude memory power management in that state.
It only indicates that any active state memory power management in MPS0 is transparent to the OSPM and more
importantly does not require assist from OSPM in terms of restricting memory occupancy and activity.
MPS1-MPSn states are characterized by non-zero exit latency for exit from the state to MPS0. These states could
require explicit OSPM-initiated entry and exit, explicit OSPM-initiated entry but autonomous exit or autonomous
entry and exit. In all three cases, these states require explicit OSPM action to isolate and free the memory address
range for the corresponding memory power node.
Transitions to more aggressive memory power states (for example, from MPS1 to MPS2) can be entered on progressive
idling but require transition through MPS0 (i.e. 𝑀𝑃𝑆 1→𝑀𝑃𝑆 0→𝑀𝑃𝑆 2). Power state transition diagram is
shown in Fig. 5.6 .
It is possible that after OSPM request a memory power state, a brief period of activity returns the memory power node
to MPS0 state . If platform is capable of returning to a memory power state on subsequent period of idle, the platform
must treat the previously requested memory power state as a persistent hint.
Fig. 5.6: Memory Power State Transitions
The following table enumerates the power state values that a node can transition to.
5.2. ACPI System Description Tables 180Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.92: Power State Values
Value State Name Description
0 MPS0 This state value maps to active state of memory node (Normal operation).
OSPM can access memory during this state.
1 MPS1 This state value can be mapped to any memory power state depending on
the platform capability. The platform will inform the features of MPS1
state using the Memory Power State Structure. By convention, it is re-
quired that low value power state will have lower power savings and lower
latencies than the higher valued power states.
2,3. . . n MPS2, MPS3, . . . MPSn Same description as MPS1.
The following table provides the list of command status options:
Table 5.93: Command Status
Field Bit
Command Complete 1 0 If set, the platform has completed processing the last com-
mand.
SCI Doorbell 1 1 If set, then this PCC Sub-Channel has signaled the SCI door
bell. In Response to this SCI, OSPM should probe the Com-
mand Complete and the Platform Notiﬁcation ﬁelds to deter-
mine the cause of SCI.
Error 1 2 If set, an error occurred executing the last command.
Platform Notiﬁcation 1 3 Indicates that the SCI doorbell was invoked by the platform.
Reserved 12 4 Reserved.
5.2.22.3 Action Sequence
SetMemoryPowerState : The following sequence needs to be done to set a memory power state.
1. Write target POWER NODE ID value to MEMORY_POWER_NODE_ID register of PCC sub channel.
StepNumList-1 Write target POWER NODE ID value to MEMORY_POWER_NODE_ID register of PCC sub
channel.
2. Write desired POWER STATE ID value to POWER STATE ID register of PCC sub channel.
3. Write SET (See Table 5.91 ) to MEMORY_POWER_STATE register of PCC sub channel.
4. Write PCC EXECUTE (See PCC Command Codes used by MPST Platform Communication Channel)
5. OSPM rings the door bell by writing to Doorbell register.
6. Platform completes the request and will generate SCI to indicate that the command is complete.
7. OSPM reads the Status register for the PCC sub channel and conﬁrms that the command was successfully
GetMemoryPowerState : The following sequence needs to be done to get the current memory power state.
channel.
2. Write GET (See Table 5.91 ) to MEMORY_POWER_STATE register of PCC sub channel.
3. Write PCC EXECUTE (See PCC Command Codes used by MPST Platform Communication Channel)
5.2. ACPI System Description Tables 181Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
4. OSPM rings the door bell by writing to Doorbell register.
5. Platform completes the request and will generate SCI to indicate that command is complete.
6. OSPM reads Status register for the PCC sub channel and conﬁrms that the command was successfully com-
pleted.
7. OSPM reads POWER STATE from POWER_STATE_ID register of PCC sub channel.
5.2.22.4 Memory Power Node
Memory Power Node is a representation of a logical memory region that needs to be transitioned in and out of a
memory power state as a unit. This logical memory region is made up of one more system memory address range(s).
A Memory Power Node is uniquely identiﬁed by Memory Power Node ID.
Note that memory power node structure deﬁned in Table 5.94 can only represent a single address range. This address
range should be 4K aligned. If a Memory Power Node contains more than one memory address range (i.e. non-
contiguous range), ﬁrmware must construct a Memory power Node structure for each of the memory address ranges
but specify the same Memory Power Node ID in all the structures.
Memory Power Nodes are not hierarchical. However, a given memory address range covered by a Memory power
node could be fully covered by another memory power node if that nodes memory address range is inclusive of the
other node’s range. For example, memory power node MPN0 may cover memory address range 1G-2G and memory
power node MPN1 covers 1-4G. Here MPN1 memory address range also comprehends the range covered by MPN0.
OSPM is expected to identify the memory power node(s) that corresponds to the maximum memory address range
that OSPM is able to power manage at a given time. For example, if MPN0 covers 1G-2G and MPN1 covers 1-4G and
OSPM is able to power manage 1-4G, it should select MPN1. If MPN0 is in a non-active memory power state, OSPM
must move MPN0 to MPS0 (Active state) before placing MPN1 in desired Memory Power State. Further, MPN1 can
support more power states than MPN0. If MPN1 is in such a state , say MPS3 , that MPN0 does not support, software
must not query MPN0. If queried, MPN0 will return “not Valid” until MPN1 returns to MPS0.
• [Implementation Note] In general, memory nodes corresponding to larger address space ranges correspond to
higher memory aggregation (e.g. memory covered by a DIMM vs. memory covered by a memory channel) and
hence typically present higher power saving opportunities.
5.2.22.4.1 Memory Power Node Structure
The following structure speciﬁes the ﬁelds used for communicating memory power node information. Each entry in
the MPST table will be having corresponding memory power node structure deﬁned.
This structure communicates address range, number of power states implemented, information about individual power
states, number of distinct physical components that comprise this memory power node.
The physical component identiﬁers can be cross-referenced against the memory topology table entries.
Table 5.94: Memory Power Node Structure deﬁnition
Field Byte
Flag 1 0 The ﬂag describes type of memory node. See the Table 5.95
table below for details.
Reserved 1 1 For future use
5.2. ACPI System Description Tables 182Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.94 – continued from previous page
Field Byte
Memory Power Node Id 2 2 This ﬁeld provides memory power node number. This is a
unique identiﬁcation for Memory Power State Command and
creation of freelists/cache lists in OSPM memory manager to
bias allocation of non power managed nodes vs. power man-
aged nodes.
Length 4 4 Length in bytes for Memory Power Node Structure. The
length implies the number of Entry ﬁelds at the end of the
table.
Base Address Low 4 8 Low 32 bits of Base Address of the memory range.
Base Address High 4 12 High 32 bits of Base Address of the memory range.
Length Low 4 16 Low 32 bits of Length of the memory range. This ﬁeld along
with “Length High” ﬁeld is used to derive the end physical
address of this address range.
Length High 4 20 High 32 bits of Length of the memory range.
Number of Power States
(n)4 24 This ﬁeld indicates number of power states supported for this
memory power node and in turn determines the number of
entries in memory power state structure.
Number of Physical Com-
ponents4 28 This ﬁeld indicates the number of distinct Physical Compo-
nents that constitute this memory power node. This ﬁeld is

table.
also used to identify the number of entries of Physical Com-
ponent Identiﬁer entries present at end of this table.
Memory Power State
Structure [n]— 32 This ﬁeld provides information of various power states sup-
ported in the system for a given memory power node
Physical Component
Identiﬁer12 — 2 byte identiﬁer of distinct physical component that makes up
this memory power node
. . . . . . . . .
Identiﬁer m2 — 2 byte identiﬁer of distinct physical component that makes up
Table 5.95: Flag format
0 Enabled If clear, the OSPM ignores this Memory Power Node Structure. This
allows system ﬁrmware to populate the MPST with a static number of
structures but enable them as necessary.
1 Power Managed Flag
1 - Memory node is power managed
0 - Memory node is not power managed. For non power managed node,
OSPM shall not attempt to transition node into low power state. System
behavior is undeﬁned if OSPM attempts this. NOTE: If the memory
range corresponding to the memory node includes platform ﬁrmware
reserved memory that cannot be power managed, the platform should
indicate such memory as “not power managed” to OSPM. This allows
OSPM to ignore such ranges from its power optimization.
2 Hot Pluggable This ﬂag indicates that the memory node supports the hot plug feature.
SeeInteraction with Memory Hot Plug for details.
3-7 Reserved Reserved for future use
5.2. ACPI System Description Tables 183Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.22.5 Memory Power State Structure
Table 5.96: Memory Power State Structure deﬁnition
Field Byte
Power State Value 1 0 This ﬁeld provides value of power state. The speciﬁc value to be
used is system dependent. However convention needs to be main-
tained where higher numbers indicates deeper power states with
higher power savings and higher latencies. For example, a power
state value of 2 will have higher power savings and higher latencies
than a power state value of 1.
Power State Infor-
mation Index1 1 This ﬁeld provides unique index into the memory power state char-
acteristics entries which will provide details about the power con-
sumed, power state characteristics and transition latencies. The in-
dexing mechanism is to avoid duplication (and hence reduce po-
tential for mismatch errors) of memory power state characteristics
entries across multiple memory nodes.
5.2.22.6 Memory Power State Characteristics structure
The table below describes the power consumed, exit latency and the characteristics of the memory power state. This
table is referenced by a memory power node.
Table 5.97: Memory Power State Characteristics Structure
Field Byte
LengthByte Offset
Power State Structure ID 1 0 Bit [5:0] = This ﬁeld describes the format of table Structure
Power State Structure ID Value = 1
Bit [7:6] = Structure Revision | Current revision is 1
Flag 1 1 The ﬂag describes the caveats associated with entering the
speciﬁed power state. Refer to Table 5.98 for details.
Reserved 2 2 Reserved
Average Power Consumed
in MPS0 state (in milli
watts)4 4 This ﬁeld provides average power consumed for this memory
power node in MPS0 state. This power is measured in milli-
Watts and signiﬁes the total power consumed by this mem-
ory the given power state as measured in DC watts. Note
that this value should be used as guideline only for esti-
mating power savings and not as actual power consumed.
Also memory power node can map to single or collection of
RANKs/DIMMs. The actual power consumed is dependent
on DIMM type, conﬁguration and memory load.
Relative Power Saving to
MPS0 state4 8 This is a percentage of power saved in MPSx state relative
to MPS0 state and should be calculated as %%MPS0 power -
MPSx power)/MPS0 Power)*100. When this entry is describ-
ing MPS0 state itself, OSPM should ignore this ﬁeld.
Exit Latency (in ns)
(MPSx –> MPS0)8 12 This ﬁeld provides latency of exiting out of a power state
(MPSx) to active state (MPS0). The unit of this ﬁeld is
nanoseconds.
When this entry is describing MPS0 state itself, OSPM should
ignore this ﬁeld.
5.2. ACPI System Description Tables 184Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.97 – continued from previous page
Field Byte
Reserved 8 20 Reserved for future use.
Table 5.98: Flag format of Memory Power State Characteristics
Structure
0 Memory Content
PreservedIf Bit [0] is set, it indicates memory contents will be preserved in the speciﬁed
power state If Bit [0] is clear, it indicates memory contents will be lost in the
speciﬁed power state (e.g. for states such as ofﬂine)
1 Autonomous Mem-
ory Power State En-
tryIf Bit [1] is set, this ﬁeld indicates that given memory power state entry tran-
sition needs to be triggered explicitly by OSPM by calling the Set Power State
command. If Bit [1] is clear, this ﬁeld indicates that given memory power state
entry transition is automatically implemented in hardware and does not require
a OSPM trigger. The role of OSPM in this case is to ensure that the correspond-
ing memory region is idled from a software standpoint to facilitate entry to the
state. Not meaningful for MPS0 - write it for this table
2 Autonomous Mem-
ory Power State ExitIf Bit [1] is set, this ﬁeld indicates that given memory power state exit needs to
be explicitly triggered by the OSPM before the memory can be accessed. Sys-
tem behavior is undeﬁned if OSPM or other software agents attempt to access
memory that is currently in a low power state. If Bit [1] is clear, this ﬁeld in-
dicates that given memory power state is exited automatically on access to the
memory address range corresponding to the memory power node.
5.2.22.6.1 Power Consumed
Average Power Consumed in MPS0 state indicates the power in milli Watts for the MPS0 state. Relative power savings
to MPS0 indicates the savings in the MPSx state as a percentage of savings relative to MPS0 state.
5.2.22.6.2 Exit Latency
Exit Latency provided in the Memory Power Characteristics structure for a speciﬁc power state is inclusive of the entry
latency for that state.
Exit latency must always be provided for a memory power state regardless of whether the memory power state entry
and/or exit are autonomous or requires explicit trigger from OSPM.
5.2.22.7 Autonomous Memory Power Management
Not all memory power management states require OSPM to actively transition a memory power node in and out of
the memory power state. Platforms may implement memory power states that are fully handled in hardware in terms
of entry and exit transition. In such fully autonomous states, the decision to enter the state is made by hardware based
on the utilization of the corresponding memory region and the decision to exit the memory power state is initiated in
response to a memory access targeted to the corresponding memory region.
The role of OSPM software in handling such autonomous memory power states is to vacate the use of such memory
regions when possible in order to allow hardware to effectively save power. No other OSPM initiated action is required
for supporting these autonomously power managed regions. However, it is not an error for OSPM explicitly initiates
5.2. ACPI System Description Tables 185Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
a state transition to an autonomous entry memory power state through the MPST command interface. The platform
may accept the command and enter the state immediately in which case it must return command completion with
SUCCESS (00000b) status. If platform does not support explicit entry, it must return command completion with NOT
SUPPORTED (00010b) status.
5.2.22.8 Handling BIOS Reserved Memory
Platform ﬁrmware may have regions of memory reserved for its own use that are unavailable to OSPM for allocation.
Memory nodes where all (or a portion) of the memory is reserved by platform ﬁrmware may pose a problem for OSPM
because it does not know whether the platform ﬁrmware reserved memory is in use.
If the platform ﬁrmware reserved memory impacts the ability of the memory power node to enter memory power
state(s), the platform must indicate to OSPM (by clearing the Power Managed Flag - see Table 5.95 for details) that
this memory power node cannot be power managed. This allows OSPM to ignore such ranges from its memory power
optimization.
5.2.22.9 Interaction with NUMA processor and memory afﬁnity tables
The memory power state table describes address range for each of the memory power nodes speciﬁed. OSPM can
use the address ranges information provided in MPST table and derive processor afﬁnity of a given memory power
node based on the SRAT entries created by the platform boot ﬁrmware. The association of memory power node to
proximity domain can be used by OSPM to implement memory coalescing taking into account NUMA node topology

for memory allocation/release and manipulation of different page lists in memory management code (implementation
speciﬁc).
An example of policy which can be implemented in OSPM for memory coalescing is: OSPM can prefer allocating
memory from local memory power nodes before going to remote memory power nodes. The later sections provide
sample NUMA conﬁgurations and explain the policy for various memory power nodes.
5.2.22.10 Interaction with Memory Hot Plug
The hot pluggable memory regions are described using memory device objects (see Section 9.11 ). The memory
address ranges of these memory device objects are deﬁned using the _CRS method.
Scope (\_SB) {
Device (MEM0) {
Name (_HID, EISAID ("PNP0C80"))
Name (_CRS, ResourceTemplate () {
QwordMemory (
ResourceConsumer,
,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0xFFFFFFF,
0x10000000,
0x30000000,
0, , ,
)
})
}
}
5.2. ACPI System Description Tables 186Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The memory power state table (MPST) is a static structure created for all memory objects independent of hot plug
status (online or ofﬂine) during initialization. The OSPM will populate the MPST table during the boot. If hot-
pluggable ﬂag is set for a given memory power node in MPST table, OSPM will not use this node till physical
presence of memory is communicated through ACPI notiﬁcation mechanism.
The association between memory device object (e.g. MEM0) to the appropriate memory power node id in the MPST
table is determined by comparing the address range speciﬁed using _CRS method and address ranges conﬁgured
in the MPST table entries. This association needs to be identiﬁed by OSPM as part of ACPI memory hot plug
implementation. When memory device is hot added, as part of existing acpi driver for memory hot plug, OSPM will
scan device object for _CRS method and get the relevant address ranges for the given memory object, OSPM will
determine the appropriate memory power node ids based on the address ranges from _CRS and enable it for power
management and memory coalescing.
Similarly when memory is hot removed, the corresponding memory power nodes will be disabled.
5.2.22.11 OS Memory Allocation Considerations
OSes (non-virtualized OS or a hypervisor/VMM) may need to allocate non-migratable memory. It is recommended
that the OSes (if possible) allocate this memory from memory ranges corresponding to memory power nodes that
indicate they are not power manageable. This allows OS to optimize the power manageable memory power nodes for
optimal power savings.
OSes can assume that memory ranges that belong to memory power nodes that are power manageable (as indicated by
the ﬂag) are interleaved in a manner that does no impact the ability of that range to enter power managed states. For
example, such memory is not cacheline interleaved.
Reference to memory in this document always refers to host physical memory. For virtualized environments, this
requires hypervisors to be responsible for memory power management. Hypervisors also have the ability to create
opportunities for memory power management by vacating appropriate host physical memory through remapping guest
physical memory.
OSes can assume that the memory ranges included in MPST always refer to memory store - either volatile or non-
volatile and never to MMIO or MMCFG ranges.
5.2.22.12 Platform Memory Topology Table (PMTT)
This table describes the memory topology of the system to OSPM, where the memory topology can be logical or
physical. The topology is provided as a hierarchy of memory devices where the top level memory devices (e.g.
sockets) are associated with the platform, down to the last level physical components (e.g. DIMMs) associated with a
parent memory device.
Table 5.99: Platform Memory Topology Table
Field Byte
Header
- Signature 4 0 ‘PMTT’. Signature for Platform Memory Topology Ta-
ble.
- Length 4 4 Length in bytes of the entire PMTT.
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Table 5.99 – continued from previous page
Field Byte
- Revision 1 8
Revision number of the Platform Memory Topology
Table ,Common Memory Device , and memory device
structures (Table 5.101, Table 5.102, Table 5.103, and
Table 5.104) deﬁned in this speciﬁcation.
Current value: 2
Compatibility Note: Revision 1 is deprecated in ACPI
Speciﬁcation 6.4.
- OEM Table ID 8 16 For the PMTT, the table ID is the manufacturer model
ID
- OEM Revision 4 24 OEM revision of the PMTT for supplied OEM Table ID.
Number of Memory Devices 4 36 The number of top level Memory Device structures that
immediately follow. A zero in this ﬁeld indicates no
Memory Device structures follow.
Memory Device Structure [n] — 40 A list of memory device structures for the platform. See
Table 5.100 below.
Table 5.100: Common Memory Device
Field Byte
Header
- Type 1 0
This ﬁeld describes the type of Memory Device:
0 - Socket
1 - Memory Controller
2 - DIMM
3 - 0xFE - Reserved , 0xFF - Vendor Speciﬁc Type
-Reserved 1 1 Reserved, must be zero.
- Length 2 2 Length in bytes for this structure. The length includes the Type
Speciﬁc Data, but not memory devices associated with this device.
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Table 5.100 – continued from previous page
Field Byte
- Flags 2 4
Bit [0]:
0 - Indicates that this is not a top level device.
1 - Indicates that this is a top level aggregator device. This
device must be counted in the number of top level aggregator
devices in PMTT table and must be surfaces via PMTT.
Bit [1]:
0 indicates a logical element of topology.
1 indicates a physical element of the topology.
Bits [2] and [3]:
01 - Indicates that components aggregated by this device
implement both volatile and non-volatile memory
10 - Indicates that all components aggregated by this device
implement non-volatile memory
11 - Reserved
Bits [15:4] Reserved, must be zero
Reserved 2 6 Reserved, must be zero.
Number of Memory
Devices4 8 The number of Memory Devices associated with this device. A zero
in this ﬁeld indicates that no Memory Device structures follow the
Type Speciﬁc Data.
Type Speciﬁc Data — 12 Type speciﬁc data. Interpretation of this data is speciﬁc to the type
of the memory device. See Table 5.101, Table 5.102, Table 5.103,
and Table 5.104.
Memory Device
Structure [n]— — An optional list of Memory Device structures associated with this
device.
Table 5.101: Socket Type Data
Field Byte
Common Memory
Device Header12 0 See Table 5.100. Type = 0 - Socket. Length =16.
Socket Identiﬁer 2 12 Uniquely identiﬁes the socket in the system.
Reserved 2 14 Reserved, must be zero.
Structure [n]— 16 An optional list of Memory Device structures associated with this
socket.
Table 5.102: Memory Controller Type Data
Field Byte
Common Memory Device
Header12 0 See Table 5.100. Type = 1 - Memory Controller. Length =16.
Memory Controller Iden-
tiﬁer2 12 Uniquely identiﬁes the memory controller within its parent
memory device type.
5.2. ACPI System Description Tables 189Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.102 – continued from previous page
Field Byte
Memory Device Structure
[n]— 16 An optional list of Memory Device structures associated with
this memory controller.
Table 5.103: DIMM Type Speciﬁc Data
Field Byte
Header12 0 See Table 5.100. Type = 2 - DIMM. Length =16.
SMBIOS Handle 4 12 Refers to Type 17 table handle of corresponding SMBIOS
record. The platform indicates that this ﬁeld is not valid by
setting a value of 0xFFFFFFFF. If the platform provides a
valid handle, the upper 2 bytes must be 0 (since SMBIOS
handles are 2 bytes only). NOTE: The use of this handle is for
management software to be able to cross-reference the phys-
ical DIMM described in SMBIOS against the topology de-
scribed in this table. It is not expected that OSPM will utilize
this ﬁeld.
Table 5.104: Vendor Speciﬁc Type Data
Field Byte
Device Header12 0 See Table 5.100. Type = 0xFF - Vendor Speciﬁc.
Type UUID 16 12 Vendor speciﬁc type unique identiﬁer.
Vendor Speciﬁc
Data— 28 Vendor speciﬁc type data.
device.
5.2.23 Boot Graphics Resource Table (BGRT)
The Boot Graphics Resource Table (BGRT) is an optional table that provides a mechanism to indicate that an image

this ﬁeld.
Field Byte
device.
was drawn on the screen during boot, and some information about the image.
The table is written when the image is drawn on the screen. This should be done after it is expected that any ﬁrmware
components that may write to the screen are done doing so and it is known that the image is the only thing on the
screen. If the boot path is interrupted (e.g., by a key press), the Displayed bit within the status ﬁeld should be changed
to 0 to indicate to the OS that the current image is invalidated.
This table is only supported on UEFI systems.
Table 5.105: Boot Graphics Resource Table Fields
Field Byte
Header
- Signature 4 0 “BGRT” Signature for the table.
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Table 5.105 – continued from previous page
- Length 4 4 Length, in bytes, of the entire table
- OEM Table ID 8 16 The table ID is the manufacturer model ID.
- OEM Revision 4 24 OEM revision for supplied OEM Table ID.
Version 2 36 2-bytes (16 bit) version ID. This value must be 1.
Status [n] 1 38
1-byte status ﬁeld indicating current status of the image:
Bits [7:3] = Reserved (must be zero)
Bits [2:1] = Orientation Offset. These bits describe the clockwise
degree offset from the image’s default orientation.
[00] = 0, no offset
[01] = 90
[10] = 180
[11] = 270
Bit [0] = Displayed. A one indicates the boot image graphic is
Image Type 1 39
1-byte enumerated type ﬁeld indicating format of the image:
0 = Bitmap
1 - 255 Reserved (for future use)
Image Address 8 40 8-byte (64 bit) physical address pointing to the ﬁrmware’s in-
memory copy of the image bitmap.
Image Offset X 4 48 A 4-byte (32-bit) unsigned long describing the display X-offset of
the boot image. (X, Y) display offset of the top left corner of the
boot image. The top left corner of the display is at offset (0, 0).
Image Offset Y 4 52 A 4-byte (32-bit) unsigned long describing the display Y-offset of
The BGRT is a dynamic ACPI table that enables boot ﬁrmware to provide OPSM with a pointer to the location in
memory where the boot graphics image is stored.
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5.2.23.1 Version
The version ﬁeld identiﬁes which revision of the BGRT table is implemented. The version ﬁeld should be set to 1.
5.2.23.2 Status
The status ﬁeld contains information about the current status of the BGRT image (see Table 5.105 above).
5.2.23.3 Image Type
The Image type ﬁeld contains information about the format of the image being returned. If the value is 0, the Image
Type is Bitmap. The format for a Bitmap is deﬁned atthe reference located in “Links to ACPI-Related Documents”
(http://ueﬁ.org/acpi) under the heading “Types of Bitmaps”.
All other values not deﬁned in the table are reserved for future use.
5.2.23.4 Image Address
The Image Address contains the location in memory where an in-memory copy of the boot image can be found. The
image should be stored in EﬁBootServicesData, allowing the system to reclaim the memory when the image is no
longer needed.
Implementations must present the image in a 24 bit bitmap with pixel format 0xRRGGBB, or a32-bit bitmap with the
pixel format 0xrrRRGGBB, where ‘rr’ is reserved.
5.2.23.5 Image Offset
The Image Offset contains 2 consecutive 4 byte unsigned longs describing the (X, Y) display offset of the top left
corner of the boot image. The top left corner of the display is at offset (0, 0).
Fig. 5.7: Image Offset
5.2. ACPI System Description Tables 192Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.24 Firmware Performance Data Table (FPDT)
This section describes the format of the Firmware Performance Data Table (FPDT), which provides sufﬁcient infor-
mation to describe the platform initialization performance records. This information represents the boot performance
data relating to speciﬁc tasks within the ﬁrmware boot process. The FPDT includes only those mileposts that are part
of every platform boot process:
• End of reset sequence (Timer value noted at beginning of platform boot ﬁrmware initialization - typically at
reset vector)
• Handoff to OS Loader
This information represents the ﬁrmware boot performance data set that would be used to track performance of each
UEFI phase, and would be useful for tracking impacts resulting from changes due to hardware/software conﬁguration.
All timer values are express in 1 nanosecond increments. For example, if a record indicates an event occurred at a
timer value of 25678, this means that 25.678 microseconds have elapsed from the last reset of the timer measurement.
All timer values will be required to have an accuracy of +/- 10%.
Fig. 5.8: FPDT Hierarchy Structure
Table 5.106: Firmware Performance Data Table (FPDT) Format
Field Byte
Header
- Signature 4 0 ‘FPDT’ Signature for the Firmware Performance Data Table.
- Length 4 4 The length of the table, in bytes, of the entire FPDT.
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Table 5.106 – continued from previous page
Field Byte
- Revision 1 8 The revision of the structure corresponding to the signature
ﬁeld for this table. For the Firmware Performance Data Table
conforming to this revision of the speciﬁcation, the revision is
1.
- Checksum 1 9 The entire table, including the checksum ﬁeld, must add to
zero to be considered valid.
- OEMID 6 10 An OEM-supplied string that identiﬁes the OEM.
- OEM Table ID 8 16 An OEM-supplied string that the OEM uses to identify this
particular data table.
- OEM Revision 4 24 An OEM-supplied revision number.
- Creator ID 4 28 The Vendor ID of the utility that created this table.
- Creator Revision 4 32 The revision of the utility that created this table.
Performance Records – 36 A set of FPDT Performance Records, as deﬁned in Table 5-
112. Section 5.2.26.4
5.2.24.1 Performance Record Format
A performance record is comprised of a sub-header including a record type and length, and a set of data. The format
of the data is speciﬁc to the record type. In this manner, records are only as large as needed to contain the speciﬁc type
of data to be conveyed.
Note that unless otherwise speciﬁed, multiple records are permitted for a given type, because some events may occur
multiple times during the boot process.
Table 5.107: Performance Record Structure
Field Byte
Performance
Record Type2 0 This value depicts the format and contents of the performance
record.
Record Length 1 2 This value depicts the length of the performance record, in bytes.
Revision 1 3 This value is updated if the format of the record type is extended.
Any changes to a performance record layout must be backwards-
compatible in that all previously deﬁned ﬁelds must be maintained
if still applicable, but newly deﬁned ﬁelds allow the length of the
performance record to be increased. Previously deﬁned record ﬁelds
must not be redeﬁned, but are permitted to be deprecated.
Data – 4 The content of this ﬁeld is deﬁned by the Performance Record Type
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5.2.24.2 FPDT Performance Record Types
The table below describes the various records contained within the FPDT, and their corresponding Record Types.
Table 5.108: FPDT Performance Record Types
Record Type
ValueType Description
0x0000 Firmware Basic
Boot Performance
Pointer RecordRecord containing a pointer to the Firmware Basic Boot Perfor-
mance Table.
0x0001 S3 Performance Ta-
ble Pointer RecordRecord containing a pointer to the S3 Performance Table.
0x0002 - 0x0FFF Reserved Reserved for ACPI speciﬁcation usage.
0x1000 - 0x1FFF Reserved Reserved for Platform Vendor usage.
0x2000 - 0x2FFF Reserved Reserved for Hardware Vendor usage.
0x3000 - 0x3FFF Reserved Reserved for platform ﬁrmware Vendor usage.
0x4000 - 0xFFFF Reserved Reserved for future use
5.2.24.3 Runtime Performance Record Types
The table below describes the various Runtime Performance records and their corresponding Record Types. These
records are not contained within the FPDT; they are referenced by their respective pointer records in the FPDT.
Table 5.109: Runtime Performance Record Types
Record Type Value Type Description
0x0000 Basic S3 Resume Perfor-
mance RecordPerformance record describing minimal ﬁrmware per-
formance metrics for S3 resume operations.
0x0001 Basic S3 Suspend Perfor-

formance metrics for S3 suspend operations.
0x0002 Firmware Basic Boot Per-
formance Data RecordPerformance record showing basic performance metrics
for critical phases of the ﬁrmware boot process.
0x0003 - 0x0FFF Reserved Reserved for ACPI speciﬁcation usage.
5.2.24.4 Firmware Basic Boot Performance Table Pointer Record
The Firmware Basic Boot Performance Table Pointer Record contains a pointer to the Firmware Basic Boot Per-
formance Table. The Firmware Basic Boot Performance Table itself exists in a range of memory described as ACPI
AddressRangeReserved in the system memory map. The record pointer is a required entry in the FPDT for any system,
and the pointer must point to a valid static physical address. Only one of these records will be produced.
Table 5.110: Firmware Basic Boot Performance Table Pointer
Record
Field Byte
Performance Record Type 2 0 0 - Firmware Basic Boot Performance Table Pointer Record
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Table 5.110 – continued from previous page
Field Byte
Record Length 1 2 16 - This value depicts the length of the performance record,
in bytes.
Revision 1 3 1 - Revision of this Performance Record
FBPT Pointer 8 8 64-bit processor-relative physical address of the Firmware Ba-
sic Boot Performance Table
5.2.24.5 S3 Performance Table Pointer Record
The S3 Performance Table Pointer Record contains a pointer to the S3 Performance Table. The S3 Performance Table
itself exists in a range of memory described as ACPI AddressRangeReserved in the system memory map. The record
pointer is a required entry in the FPDT for any system supporting the S3 state, and the pointer must point to a valid
static physical address. Only one of these records will be produced.
Table 5.111: S3 Performance Table Pointer Record
Field Byte
Performance Record Type 2 0 1 - S3 Performance Table Pointer Record
in bytes.
S3PT Pointer 8 8 64-bit processor-relative physical address of the S3 Perfor-
mance Table
5.2.24.6 Firmware Basic Boot Performance Table
The Firmware Basic Boot Performance Table resides outside of the FPDT. It includes a header, deﬁned in Table 5.112,
and one or more Performance Records.
All event entries will be overwritten during the platform runtime ﬁrmware S4 resume sequence. The Firmware Basic
Boot Performance Table must include the Firmware Basic Boot Performance Data Record. Other entries are optional.
Table 5.112: Firmware Basic Boot Performance Table Header
Field Byte
Signature 4 0 ‘FBPT’ is the signature to use.
Length 4 4 Length of the Firmware Basic Boot Performance Table. This
includes the header and allocated size of the subsequent
records. This size would at minimum include the size of
the header and the Firmware Basic Boot Performance Data
Record.
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5.2.24.7 Firmware Basic Boot Performance Data Record
The Firmware Basic Boot Performance Data Record contains timer information associated with ﬁnal OS loader activ-
ity, as well as data associated with boot time starting and ending information.
Table 5.113: Firmware Basic Boot Performance Data Record
Field Byte
Performance Record Type 2 0 2 - Firmware Basic Boot Performance Data Record. Only one
of these records will be produced.
Record Length 1 2 48 - This value depicts the length of the performance record,
in bytes.
Revision 1 3 2 - Revision of this Performance Record
Reset End 8 8 Timer value logged at the beginning of ﬁrmware image exe-
cution. This may not always be zero or near zero.
OS Loader LoadImage
Start8 16 Timer value logged just prior to loading the OS boot loader
into memory. For non-UEFI compatible boots, this ﬁeld must
be zero.
OS Loader StartImage
Start8 24 Timer value logged just prior to launching the currently
loaded OS boot loader image. For non-UEFI compatible
boots, the timer value logged will be just prior to the INT 19h
handler invocation.
ExitBootServices Entry 8 32 Timer value logged at the point when the OS loader calls
the ExitBootServices function for UEFI compatible ﬁrmware.
For non-UEFI compatible boots, this ﬁeld must be zero.
ExitBootServices Exit 8 40 Timer value logged at the point just prior to the OS loader
gaining control back from the ExitBootServices function for
UEFI compatible ﬁrmware. For non-UEFI compatible boots,
5.2.24.8 S3 Performance Table
The S3 Performance Table resides outside of the FPDT. It includes a header, deﬁned in Table 5.115 , and one or more
Performance Records.
All event entries must be initialized to zero during the initial boot sequence, and overwritten during the platform
runtime ﬁrmware S3 resume sequence. The S3 Performance Table must include the Basic S3 Resume Performance
Record. Other entries are optional.
Table 5.114: S3 Performance Table Header
Field Byte
Offsetescription
Signature 4 0 ‘S3PT’ is the signature to use.
Length 4 4 Length of the S3 Performance Table. This includes the header
and allocated size of the subsequent records. This size would
at minimum include the size of the header and the Basic S3
Resume Performance Record.
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Table 5.115: Basic S3 Resume Performance Record
Field Byte
Runtime Performance
Record Type2 0 0 - The Basic S3 Resume Performance Record Type. Only
one of these records will be produced.
Record Length 1 2 24 - The value depicts the length of this performance record,
in bytes.
Resume Count 4 4 A count of the number of S3 resume cycles since the last full
boot sequence.
FullResume 8 8 Timer recorded at the end of platform runtime ﬁrmware S3
resume, just prior to handoff to the OS waking vector. Only
the most recent resume cycle’s time is retained.
AverageResume 8 16 Average timer value of all resume cycles logged since the last
full boot sequence, including the most recent resume. Note
that the entire log of timer values does not need to be retained
in order to calculate this average. AverageResumenew = (Av-
erageResumeold * (ResumeCount -1) + FullResume) / Re-
sumeCount
Table 5.116: Basic S3 Suspend Performance Record
Field Byte
Record Type2 0 1 - Basic S3 Suspend Performance Record. Zero to one of
these records will be produced.
Record Length 1 2 20 - The value depicts the length of this performance record,
in bytes.
SuspendStart 8 4 Timer value recorded at the OS write to SLP_TYP upon entry
to S3. Only the most recent suspend cycle’s timer value is
retained.
SuspendEnd 8 12 Timer value recorded at the ﬁnal ﬁrmware write to SLP_TYP
(or other mechanism) used to trigger hardware entry to S3.
Only the most recent suspend cycle’s timer value is retained.
5.2.25 Generic Timer Description Table (GTDT)
This section describes the format of the Generic Timer Description Table (GTDT), which provides OSPM with in-
formation about a system’s Generic Timers conﬁguration. The Generic Timer (GT) is a standard timer interface im-
plemented on ARM processor-based systems. The GT hardware speciﬁcation can be found at Links to ACPI-Related
Documents (http://ueﬁ.org/acpi ) under the heading ARM Architecture . The GTDT provides OSPM with information
about a system’s GT interrupt conﬁgurations, for both per-processor timers, and platform (memory-mapped) timers.
The GT speciﬁcation deﬁnes the following per-processor timers:
• Secure EL1 timer
• Non-Secure EL1 timer
• EL2 timer
• Virtual EL1 timer
• Virtual EL2 timer
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and deﬁnes the following memory-mapped Platform timers:
• GT Block
• Arm Generic Watchdog
Table 5.117: GTDT Table Structure
Field Byte
Header
- Signature 4 0 ‘GTDT’. Signature for the Generic Timer Description
Table.
- Length 4 4 Length, in bytes, of the entire Generic Timer Descrip-
- Revision 1 8 3
- OEM Table ID 8 16 The manufacturer model ID.

• EL2 timer
• GT Block
Field Byte
Header
Table.
CntControlBase Physical Ad-
dress8 36 The 64-bit physical address at which the Counter Con-
trol block is located.This value is optional if the system
implements EL3 (Security Extensions). If not provided,
this ﬁeld must be 0xFFFFFFFFFFFFFFFF.
Reserved 4 44 Must be zero
Secure EL1 Timer GSIV 4 48 GSIV for the secure EL1 timer. This value is op-
tional, as an operating system executing in the non-
secure world (EL2 or EL1), will ignore the content of
these ﬁelds.
Secure EL1 Timer Flags 4 52 Flags for the secure EL1 timer (deﬁned below). This
value is optional, as an operating system executing in
the non-secure world (EL2 or EL1) will ignore the con-
tent of this ﬁeld.
Non-Secure EL1 Timer GSIV 4 56 GSIV for the non-secure EL1 timer.
Non-Secure EL1 Timer Flags 4 60 Flags for the non-secure EL1 timer (deﬁned below).
Virtual EL1 Timer GSIV 4 64 GSIV for the virtual EL1 timer.
Virtual EL1 Timer Flags 4 68 Flags for the virtual EL1 timer (deﬁned below)
EL2 Timer GSIV 4 72 GSIV for the EL2 timer.
EL2 Timer Flags 4 76 Flags for the EL2 timer(deﬁned below).
CntReadBase Physical Address 8 80 The 64-bit physical address at which the Counter Read
block is located. This value is optional if the system
Platform Timer Count 4 88 Number of entries in the Platform Timer Structure[] ar-
ray
Platform Timer Offset 4 92 Offset to the Platform Timer Structure[] array from the
start of this table
Virtual EL2 Timer GSIV 4 96 GSIV for the virtual EL2 timer. This ﬁeld is mandatory
for systems implementing ARMv8.1 VHE. For systems
not implementing ARMv8.1 VHE, this ﬁeld is 0.
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Table 5.117 – continued from previous page
Field Byte
Virtual EL2 Timer Flags 4 100 Flags for the virtual EL2 timer (deﬁned below). This
ﬁeld is mandatory for systems implementing ARMv8.1
VHE. For systems not implementing ARMv8.1 VHE,
this ﬁeld is 0.
Platform Timer Structure[] — Platform
Timer
OffsetArray of Platform Timer Type structures describing
memory-mapped Timers available on this platform.
These structures are described in the sections below.
The following ﬂags each have the same deﬁnition, as shown in the table below: Secure EL1 Timer Flags, Non-Secure
EL1 Timer Flags, EL2 Timer Flags, Virtual EL1 Timer Flags, and Virtual EL2 Timer Flags.
Table 5.118: Flag Deﬁnitions: Secure EL1 Timer, Non-Secure EL1
Timer, EL2 Timer, Virtual EL1 Timer and Virtual EL2 Timer
Bit Field Bit Off-
setNumber
of bitsDescription
Timer interrupt Mode 0 1
This bit indicates the mode of the timer interrupt:
1: Interrupt is Edge triggered
0: Interrupt is Level triggered
Timer Interrupt polarity 1 1
This bit indicates the polarity of the timer interrupt:
1: Interrupt is Active low
0: Interrupt is Active high
Always-on Capability 2 1
This bit indicates the always-on capability of the timer
implementation:
1: This timer is guaranteed to assert its interrupt and wake a
processor, regardless of the processor’s power state. All of
the methods by which an ARM Generic Timer may generate
an interrupt must be supported, and must be capable of
waking the processor.
0: This timer may lose context or may not be guaranteed to
assert interrupts when its associated processor enters a
low-power state.
Reserved 3 29 Reserved, must be zero.
The GTDT Platform Timer Structure [] ﬁeld is an array of Platform Timer Type structures, each of which describes
the conﬁguration of an available platform timer. These timers are in addition to the per-processor timers described
above them in the GTDT.
Table 5.119: Platform Timer Type Structures
0 GT Block
1 Arm Generic Watchdog
5.2. ACPI System Description Tables 200Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.119 – continued from previous page
0x02-0xFF Reserved for future use
The ﬁrst byte of each structure declares the type of that structure and the second and third bytes declare the length of
that structure.
5.2.25.1 GT Block Structure
The GT Block is a standard timer block that is mapped into the system address space. Each GT Block implements up
to 8 GTs (GT0 - GT7).
The format of the GT Block structure is shown in the following table.
Table 5.120: GT Block Structure Format
Field Byte
Type 1 0 0x0 GT Block
Length 2 1 20+n*40, where n is the number of timers implemented
in the GT Block
Reserved 1 3 Must be zero
GT Block Physical address
(CntCtlBase)8 4 The 64-bit physical address at which the GT CntCTL-
Base Block is located
GT Block Timer Count 4 12 Number of Timers implemented in this GT Block (‘n’).
. Must be less than or equal to 8.
GT Block Timer Offset 4 16 Offset to the Platform Timer Structure array from the
start of this structure
GT Block Timer Structure[] n*40 GT
Block
Timer
OffsetArray of GT Block Timer Structures. See the GT Block
Timer Structure Format table.
Table 5.121: GT Block Timer Structure Format
Field Byte
GT Frame Number 1 0 The frame number (0-7) for this timer (‘x’)
Reserved 3 1 Must be zero
GTx Physical Address (CntBa-
seX)8 4 Physical Address at which the CntBase block for GTx
is located
GTx Physical Address (Cn-
tEL0BaseX)8 12 Physical Address at which the CntEL0Base block for
GTx is located. If this block is not implemented for
GTx, must be 0xFFFFFFFFFFFFFFFF.
GTx Physical Timer GSIV 4 20 GSIV for the GTx physical timer
GTx Physical Timer Flags 4 24 Flags for the GTx physical timer. See Flag Deﬁnitions:
GT Block Physical Timers and Virtual Timers.
GTx Virtual Timer GSIV 4 28 GSIV for the GTx virtual timer If the Virtual Timer is
not implemented for GTx, this ﬁeld must be 0.
GTx Virtual Timer Flags 4 32 Flags for the GTx virtual timer, if implemented. See
Flag Deﬁnitions: GT Block Physical Timers and Virtual
Timers.
5.2. ACPI System Description Tables 201Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.121 – continued from previous page
Field Byte
GTx Common Flags 4 36 See Common Flags.
Table 5.122: Flag Deﬁnitions: GT Block Physical Timers and Virtual
Timers
setNumber
1: Interrupt is Edge triggered.
0: Interrupt is Level triggered.
Reserved 2 30 Reserved, must be zero.
Flag Deﬁnitions: Common Flags
Table 5.123: Flag Deﬁnitions - Common Flags
setNumber
Secure Timer 0 1
This bit indicates whether the timer is secure or
non-secure:
1: Timer is Secure
0: Timer is Non-secure
Always-on Capability 1 1
This bit indicates the always-on capability of the
Physical and Virtual Timers implementation:
1: This timer is guaranteed to assert its interrupt
and wake a processor, regardless of the
processor’s power state. All of the methods by
which an ARM Generic Timer may generate an
interrupt must be supported, and must be capable
of waking the processor.
0: This timer may lose context or may not be
guaranteed to assert interrupts when its
associated processor enters a low-power state.
5.2. ACPI System Description Tables 202Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.25.2 Arm Generic Watchdog Structure
The Arm Generic Watchdog is a Platform GT with built-in support for use as the Watchdog timer on platforms com-
pliant with the Server Base System Architecture (SBSA) or Base System Architecture (BSA). For more information,
see Links to ACPI-Related Documents under the heading Arm Base System Architecture (BSA).
The format of the Arm Generic Watchdog structure is shown in the following table.
Table 5.124: Arm Generic Watchdog Structure Format
Field Byte
Type 1 0 0x1 Watchdog GT
Length 2 1 28
RefreshFrame Physical Address 8 4 Physical Address at which the RefreshFrame block is
located
WatchdogControlFrame Physi-
cal Address8 12 Physical Address at which the Watchdog Control Frame
block is located
Watchdog Timer GSIV 4 20 GSIV for the Arm Generic Watchdog timer
Watchdog Timer Flags 4 24 Flags for the Arm Generic Watchdog timer. See Flag
Deﬁnitions: Arm Generic Watchdog Timer.
Table 5.125: Flag Deﬁnitions - Arm Generic Watchdog Timer
setNumber

Field Byte
located
setNumber
Secure Timer 2 1
5.2. ACPI System Description Tables 203Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.26 NVDIMM Firmware Interface Table (NFIT)
5.2.26.1 Overview
This optional table provides information that allows OSPM to enumerate NVDIMMs present in the platform and
associate system physical address ranges created by the NVDIMMs. NVDIMMs are represented by zero or more
NVDIMM devices under a single NVDIMM root device in ACPI namespace.
OSPM evaluates NFIT only during system initialization. Any changes to the NVDIMM state at runtime or information
regarding hot added NVDIMMs are communicated using the _FIT method (See Section 6.5.9 ) of the NVDIMM root
device.
The NFIT consists of the following structures:
1. System Physical Address (SPA) Range Structure(s) (see Section 5.2.26.2) – Describes the SPA ranges occupied
by NVDIMMs and the types of the SPA ranges.
2. NVDIMM Region Mapping Structure(s) (see Section 5.2.26.3) – Describes mappings of NVDIMM regions to
SPA ranges and NVDIMM region properties.
3. Interleave Structure(s) (see Section 5.2.26.4) – Describes the various interleave options used by NVDIMM
regions.
4. SMBIOS Management Information Structure(s) (see Section 5.2.26.5) – Describes SMBIOS Table entries for
hot added NVDIMMs.
5. NVDIMM Control Region Structure(s) (see Section 5.2.26.6) – Describes NVDIMM function interfaces, and if
applicable, their Block Control Windows.
6. NVDIMM Block Data Window Region Structure(s) (see Section 5.2.26.7) – Describes Block Data Windows for
a NVDIMM function interfaces that have Block Control Windows.
7. Flush Hint Address Structure(s) (see Section 5.2.26.8) – Describes special system physical addresses that when
written help achieve durability for writes to NVDIMM regions.
8. Platform Capabilities Structure (see Section 5.2.26.9) – Describes the Platform Capabilities to inform OSPM of
platform-wide NVDIMM capabilities.
5.2. ACPI System Description Tables 204Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The following ﬁgure illustrates the above structures and how they are associated with each other.
Fig. 5.9: NVDIMM Firmware Interface Table (NFIT) Overview
The following table deﬁnes the NFIT.
Table 5.126: NVDIMM Firmware Interface Table (NFIT)
Field Byte
LengthByte Offset Description
Header
- Signature 4 0 ‘NFIT’ is Signature for this table
- Length 4 4 Length in bytes for entire table.
Table ID
Reserved 4 36 NFIT Structure[n]
— 40 A list of NFIT structures
for this implementation.Each NFIT Structure must start with a 2 byte
Type ﬁeld followed by a 2 byte length ﬁeld.
This allows OSPM to ignore unrecognized
types. Supported NFIT Structure types are
listed in Table 5.127.
5.2. ACPI System Description Tables 205Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.127: NFIT Structure Types
0 System Physical Address (SPA) Range Structure
1 NVDIMM Region Mapping Structure
2 Interleave Structure
3 SMBIOS Management Information Structure
4 NVDIMM Control Region Structure
5 NVDIMM Block Data Window Region Structure
6 Flush Hint Address Structure
7 Platform Capabilities Structure
8-0xFFFF Reserved
5.2.26.2 System Physical Address (SPA) Range Structure
This structure describes the system physical address ranges occupied by NVDIMMs, and their corresponding Region
Types.
System physical address ranges described as Virtual CD or Virtual Disk shall be described as AddressRangeReserved
in E820, and EFI Reserved Memory Type in the UEFI GetMemoryMap.
Platform is allowed to implement this structure just to describe system physical address ranges that describe Virtual
CD and Virtual Disk. For Virtual CD Region and Virtual Disk Region (both volatile and persistent), the following
ﬁelds - Proximity Domain, SPA Range Structure Index, Flags, and Address Range Memory Mapping Attribute, are
not relevant and shall be set to 0.
The default mapping of the NVDIMM Control Region shall be UC memory attributes with AddressRangeReserved
type in E820 and EﬁMemoryMappedIO type in UEFI GetMemoryMap. The default mapping of the NVDIMM
Block Data Window Region shall be WB memory attributes with AddressRangeReserved type in E820 and EﬁMem-
oryMappedIO type in UEFI GetMemoryMap.
Table 5.128: SPA Range Structure
Field Byte
Type 2 0 0 - SPA Range Structure
Length 2 2 Length in bytes for entire structure.
SPA Range Structure Index 2 4 Used by NVDIMM Region Mapping Structure to
uniquely refer to this structure. Value of 0 is Reserved
and shall not be used as an index.
Flags 2 6
Bit [0] set to 1 indicates that Control region is strictly
for management during hot add/online operation.
Bit [1] set to 1 to indicate that data in the Proximity
Domain ﬁeld is valid.
Bit [2] set to 1 to indicate that data in the
SPALocationCookie ﬁeld is valid.
Bits [15:3]: Reserved
Reserved 4 8 Reserved
Proximity Domain 4 12 Integer that represents the proximity domain to which
the memory belongs. This number must match with cor-
responding entry in the SRAT table.
5.2. ACPI System Description Tables 206Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.128 – continued from previous page
Field Byte
Address Range Type GUID 16 16 GUID that deﬁnes the type of the Address Range Type.
The GUID can be any of the values deﬁned in this sec-
tion, or a vendor deﬁned GUID.
System Physical Address Range
Base8 32 Start Address of the System Physical Address Range
Length8 40 Range Length of the region in bytes
Address Range Memory Map-
ping Attribute8 48
Memory mapping attributes for this address range:
EFI_MEMORY_UC = 0x00000001
EFI_MEMORY_WC = 0x00000002
EFI_MEMORY_WT = 0x00000004
EFI_MEMORY_WB = 0x00000008
EFI_MEMORY_UCE = 0x00000010
EFI_MEMORY_WP = 0x00001000
EFI_MEMORY_RP = 0x00002000
EFI_MEMORY_XP = 0x00004000
EFI_MEMORY_NV = 0x00008000
EFI_MEMORY_MORE_RELIABLE = 0x00010000
EFI_MEMORY_RO = 0x00020000
EFI_MEMORY_SP = 0x00040000
SpaLocationCookie 8 56 Opaque cookie value set by platform ﬁrmware for
OSPM use, to detect changes that may impact the read-
ability of the data.
The following GUIDs are used to describe the NVDIMM Region Types. Additional GUIDs can be generated to
describe additional Address Range Types.
Persistent Memory (PM) Region:
{ 0x66F0D379, 0xB4F3, 0x4074, 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }
NVDIMM Control Region:
{ 0x92F701F6, 0x13B4, 0x405D, 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }
NVDIMM Block Data Window Region:
{ 0x91AF0530, 0x5D86, 0x470E, 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }
RAM Disk supporting a Virtual Disk Region - V olatile (a volatile memory region that contains a raw disk format):
{ 0x77AB535A,0x45FC,0x624B,0x55,0x60,0xF7,0xB2,0x81,0xD1,0xF9,0x6E }
RAM Disk supporting a Virtual CD Region - V olatile (a volatile memory region that contains an ISO image):
{ 0x3D5ABD30,0x4175,0x87CE,0x6D,0x64,0xD2,0xAD,0xE5,0x23,0xC4,0xBB }
RAM Disk supporting a Virtual Disk Region - Persistent (a persistent memory region that contains a raw disk format):
{ 0x5CEA02C9,0x4D07,0x69D3,0x26,0x9F,0x44,0x96,0xFB,0xE0,0x96,0xF9 }
RAM Disk supporting a Virtual CD Region - Persistent (a persistent memory region that contains an ISO image):
{ 0x08018188,0x42CD,0xBB48,0x10,0x0F,0x53,0x87,0xD5,0x3D,0xED,0x3D }
5.2. ACPI System Description Tables 207Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Note: The Address Range Type GUID values used in the ACPI NFIT must match the corresponding values in the Disk
Type GUID of the RAM Disk device path that describe the same RAM Disk Type. Refer to the UEFI speciﬁcation for
details.
5.2.26.3 NVDIMM Region Mapping Structure
The NVDIMM Region Mapping structure describes an NVDIMM region and its mapping, if any, to an SPA range.
Table 5.129: NVDIMM Region Mapping Structure
Field Byte
Type 2 0 1 - NVDIMM Region Mapping Structure
NFIT Device Handle 4 4 The _ADR of the NVDIMM device (see Section 9.19.3) con-
taining the NVDIMM region
NVDIMM Physical ID 2 8 Handle (i.e., instance number) for the SMBIOS Memory De-
vice (Type 17) structure describing the NVDIMM containing
the NVDIMM region. See the DSP0134 System Manage-
ment BIOS (SMBIOS) Reference Speciﬁcation, Version 3.0.0
(2015-02-12) by the Distributed Management Task Force, Inc.

details.
Field Byte
(DMTF) at http://www.dmtf.org/standards/smbios
NVDIMM Region ID 2 10 Unique identiﬁer for the NVDIMM region. This identi-
ﬁer shall be unique across all the NVDIMM regions in the
NVDIMM. There could be multiple regions within the device
corresponding to different address types. Also, for a given ad-
dress type, there could be multiple regions due to interleave
discontinuity.
SPA Range Structure In-
dex2 12
The SPA range, if any, associated with the NVDIMM region::
0x0000: The NVDIMM region does not map to a SPA range.
The following ﬁelds are not valid and should be ignored:
- NVDIMM Region Size;
- Region Offset;
- NVDIMM Physical Address Region Base;
- Interleave Structure Index; and
- Interleave Ways.
Fields other than the above (e.g. NFIT Device Handle,
NVDIMM Physical ID, NVDIMM Region ID, and
NVDIMM State Flags) are valid:
- 0x0001 to 0xFFFF: The index of the SPA Range Structure
(see Section 5.2.26.2) for the NVDIMM region.
NVDIMM Control Re-
gion Structure Index2 14 The index of the NVDIMM Control Region Structure (see
Section 5.2.26.6 ) for the NVDIMM region.
5.2. ACPI System Description Tables 208Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.129 – continued from previous page
Field Byte
NVDIMM Region Size 8 16 The size of the NVDIMM region, in bytes. If SPA Range
Structure Index and Interleave Ways are both non-zero, this
ﬁeld shall match System Physical Address Range Length di-
vided by Interleave Ways. NOTE: the size in SPA Range oc-
cupied by the NVDIMM for this region will not be the same
as the NVDIMM Region Size when Interleave Ways is greater
than 1.
Region Offset 8 24 In bytes: The Starting Offset for the NVDIMM region in the
Interleave Set. This offset is with respect to System Physi-
cal Address Range Base in the SPA Range Structure. NOTE:
The starting SPA of the NVDIMM region in the NVDIMM is
provided by System Physical Address Range Base + Region
Offset
NVDIMM Physical Ad-
dress Region Base8 32 In bytes. The base physical address within the NVDIMM of
the NVDIMM region.
Interleave Structure Index 2 40 TheInterleave Structure , if any, for the NVDIMM region, as
deﬁned in Table 5.130.
Interleave Ways 2 42 Number of NVDIMMs in the interleave set, including the
NVDIMM containing the NVDIMM region, as deﬁned in Ta-
ble 5.130.
5.2. ACPI System Description Tables 209Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Field Byte
NVDIMM State Flags 2 44
Bit [0] set to 1 indicates that the previous SA VE operation to
the NVDIMM containing the NVDIMM region failed.
Bit [0] set to 0 indicates that the previous SA VE succeeded,
or there was no previous SA VE.
Bit [1] set to 1 indicates that the last RESTORE operation
from the NVDIMM containing the NVDIMM region failed.
Bit [1] set to 0 indicates that the last RESTORE succeeded or
there was no last RESTORE.
Bit [2] set to 1 indicates that the platform ﬂush of data to the
NVDIMM containing the NVDIMM region before the
previous SA VE failed. As a result, the restored data content
may be inconsistent even if Bit [0] and Bit [1] do not indicate
failure.
Bit [2] set to 0 indicates that the platform ﬂush succeeded, or
there was no platform ﬂush.
Bit [3] set to 1 indicates that the NVDIMM containing the
NVDIMM region is not able to accept persistent writes. For
an energy-source backed NVDIMM device, Bit [3] is set if it
is not armed or the previous ERASE operation did not
complete.
Bit [3] set to 0 indicates that the NVDIMM containing the
NVDIMM region is armed.
Bit [4] set to 1 indicates that the NVDIMM containing the
NVDIMM region observed SMART and health events prior
to OSPM handoff.
Bit [5] set to 1 indicates that platform ﬁrmware is enabled to
notify OSPM of SMART and health events related to the
NVDIMM containing the NVDIMM region using Notify
codes as speciﬁed in NVDIMM Device Notiﬁcation Values.
Bit [6] set to 1 indicates that the platform ﬁrmware did not
map the NVDIMM containing the NVDIMM region into an
SPA range. This could be due to various issues such as a
device initialization error, device error, insufﬁcient hardware
resources to map the device, or a disabled device.
Implementation Note: In case of device error, Bit [4] might
be set along with Bit [6].
Bit [7] to Bit [15] are reserved.
Implementation Note: Platform ﬁrmware might report
several set bits.
Reserved 2 46 Reserved
5.2. ACPI System Description Tables 210Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.130: Interleave Structure Index and Interleave Ways deﬁni-
tion
Interleave
Structure
IndexInterleave
WaysInterpretation
0 0 Interleaving, if any, of the NVDIMM region is not reported
0 1 The NVDIMM region is not interleaved with other NVDIMMs (i.e., it is one-
way interleaved)
0 >1 The NVDIMM region is part of an interleave set with the number of NVDIMMs
indicated in the Interleave Ways ﬁeld, including the NVDIMM containing the
NVDIMM region, but the Interleave Structure is not described.
> 0 > 1 The NVDIMM region is part of an interleave set with: a) the number of
NVDIMMs indicated in the Interleave Ways ﬁeld, including the NVDIMM
containing the NVDIMM region; and b) the Interleave Structure (see Section
5.2.26.4) indicated by the Interleave Structure Index ﬁeld.
All other com-
binationsInvalid case
Note: Interleave Structure Index=0, Interleave Ways !=1 is to allow a PM range which is interleaved but the actual
interleave is not described but only provides the physical Memory Devices (as described by SMBIOS Type 17) that
contribute to the PM region. Typically, only block region requires the interleave structure since software has to undo
the effect of interleave.
5.2.26.4 Interleave Structure
Memory from DIMMs/NVDIMMs could be interleaved across memory channels, memory controller and processor
sockets. This structure describes the memory interleave for a given address range. Since interleave is a repeating
pattern, this structure only describes the lines involved in the memory interleave before the pattern start to repeat.
Table 5.131: Interleave Structure
Field Byte
Type 2 0 2 - Interleave Structure
Structure
Index2 4 Index Number uniquely identiﬁes the interleave description - this
allows reuse of interleave description across multiple NVDIMMs.
Index must be non-zero.
Reserved 2 6
Number
of Lines
Described (m)4 8 Only need to describe the number of lines needed before the inter-
leave pattern repeats
Line Size ( in
bytes )4 12 e.g. 64, 128, 256, 4096
Line 1 Offset 4 16 Line 1 Offset refers to the offset of the line, in multiples of Line
Size, from the corresponding SPA Range Base for the NVDIMM
region. Line 1 SPA = SPA Range Base + Region Offset + (Line 1
Offset*Line Size). Line SPA is naturally aligned to the Line size.
. . . 4
5.2. ACPI System Description Tables 211Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.131 – continued from previous page
Field Byte
Line m Offset 4 16+((m-1)*4) Line m Offset refers to the offset of the line, in multiples of Line
region. Line m SPA = SPA Range Base + Region Offset + (Line m
Offset*Line Size) where m is the last line number before the pattern
repeats.
5.2.26.5 SMBIOS Management Information Structure
This structure enables platform to communicate the additional SMBIOS entries beyond the entries provided by SM-
BIOS Table at boot to the OS (e.g. Type 17 entries corresponding to hot added NVDIMMs).
Table 5.132: SMBIOS Management Information Structure
Field Byte
Type 2 0 3 - SMBIOS Management Information Structure
Reserved 4 4
Data _ 8 SMBIOS Table Entries
5.2.26.6 NVDIMM Control Region Structure
The system shall include an NVDIMM Control Region Structure for every Function Interface in the NVDIMM.
Table 5.133: NVDIMM Control Region Structure Mark
Field Byte
Type 2 0 4 - NVDIMM Control Region Structure
Length 2 2 Length in bytes for entire structure. The length of this struc-
ture is either 32 bytes or 80 bytes. The length of the structure
can be 32 bytes only if the Number of Block Control Windows
ﬁeld has a value of 0.
gion Structure Index2 4 Index Number uniquely identiﬁes the NVDIMM Control Re-
gion Structure.
Vendor ID 2 6 Identiﬁer indicating the vendor of the NVDIMM. This ﬁeld
shall be set to the value of the NVDIMM SPD Module Man-
ufacturer ID Code ﬁeld(a)with byte 0 set to DDR4 SPD byte
320 and byte 1 set to DDR4 SPD byte 321.
Device ID 2 8 Identiﬁer for the NVDIMM, assigned by the module vendor.
This ﬁeld shall be set to the value of the NVDIMM SPD Mod-

Field Byte
ule Product Identiﬁer ﬁeld(b)with byte 0 set to SPD byte 192
and byte 1 set to SPD byte 193.
Revision ID 2 10 Revision of the NVDIMM, assigned by the module vendor.
Byte 1 of this ﬁeld is reserved. Byte 0 of this ﬁeld shall be
set to the value of the NVDIMM SPD Module Revision Code
ﬁeld(a)(i.e., SPD byte 349).
5.2. ACPI System Description Tables 212Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.133 – continued from previous page
Field Byte
Subsystem Vendor ID 2 12 Vendor of the NVDIMM non-volatile memory subsystem
controller(c). This ﬁeld shall be set to the value of the
NVDIMM SPD Non-V olatile Memory Subsystem Controller
Vendor ID ﬁeld(b)with byte 0 set to SPD byte 194 and byte 1
set to SPD byte 195.
Subsystem Device ID 2 14 Identiﬁer for the NVDIMM non-volatile memory subsystem
controller, assigned by the non-volatile memory subsystem
controller vendor. This ﬁeld shall be set to the value of the
Device ID ﬁeld(b)with byte 0 set to SPD byte 196 and byte 1
set to SPD byte 197.
Subsystem Revision ID 2 16 Revision of the NVDIMM non-volatile memory subsystem
controller vendor. Byte 1 of this ﬁeld is reserved. Byte 0 of
this ﬁeld shall be set to the value of the NVDIMM SPD Non-
V olatile Memory Subsystem Controller Revision Code ﬁeldb
(i.e. SPD byte 198).
Valid Fields 1 18
Valid bits for ﬁelds deﬁned after the initial NFIT deﬁnition in
ACPI 6.0 within the initially deﬁned lengths of 32 and 80
bytes.
Bits [7-1]: Reserved. Bit [0]: Manufacturing Location ﬁeld
and Manufacturing Date ﬁeld.
Bit [0] set to one indicates that the Manufacturing Location
ﬁeld and Manufacturing Date ﬁeld are valid.
Bit [0] set to zero indicates that the Manufacturing Location
ﬁeld and Manufacturing Date ﬁeld are not valid and should
be ignored. Systems compliant with this speciﬁcation shall
set Bit [0] to one. Systems that were compliant with ACPI
6.0 had Bit [0] set to zero, meaning they did not have
Manufacturing Location and Manufacturing Date ﬁelds.
Manufacturing Location 1 19 Manufacturing location for the NVDIMM, assigned by the
module vendor. This ﬁeld shall be set to the value of the
NVDIMM SPD Module Manufacturing Location ﬁelda(SPD
byte 322). Validity of this ﬁeld is indicated in Valid Fields Bit
[0].
Manufacturing Date 2 20 Date the NVDIMM was manufactured, assigned by the mod-
ule vendor. This ﬁeld shall be set to the value of the NVDIMM
SPD Module Manufacturing Date ﬁeld(a)with byte 0 set to
SPD byte 323 and byte 1 set to SPD byte 324. Validity of this
ﬁeld is indicated in Valid Fields Bit [0].
Reserved 2 22 Reserved
Serial Number 4 24 Serial number of the NVDIMM, assigned by the module ven-
dor. This ﬁeld shall be set to the value of the NVDIMM SPD
Module Serial Number ﬁeld with byte 0 set to SPD byte 325,
byte 1 set to SPD byte 326, byte 2 set to SPD byte 327, and
byte 3 set to SPD byte 328.
5.2. ACPI System Description Tables 213Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Field Byte
Region Format Interface
Code2 28
Identiﬁer for the programming interface. This ﬁeld shall be
set to the value of the NVDIMM SPD Function Interface
descriptorbfor the function interface represented by the
NVDIMM Control Region structure, with:
a. byte 0 bits 7:5 set to 000b;
b. byte 0 bits 4:0 set to the Function Interface ﬁeld
(Function Interface descriptor bits 4:0);
c. byte 1 bits 7:5 set to 000b; and
d. byte 1 bits 4:0 set to the Function Class ﬁeld
(Function Interface descriptor bits 9:5).
EXAMPLE - A Function Interface Descriptor of 0x8021
means:
a. Function Interface Descriptor is implemented;
b. there is no Extended Function Parameter Block;
c. function class is byte-addressable energy backed
(0x01); and
d. function interface is byte addressable energy backed
function interface 1 (0x01)d, and maps to a Region
Format Interface Code of 0x0101.
Number of Block Control
Windows2 30 Number of Block Control Windows must match the corre-
sponding number of Block Data Windows. Fields that follow
this ﬁeld are valid only if the number of Block Control Win-
dows is non-zero.
Size of Block Control
Window8 32 In Bytes
Command Register Offset
in Block Control Window8 40 In Bytes. Logical offset. Refer to Note. The start of the sub-
sequent Block Control Windows is calculated by adding Size
of Block Control Window.
Size of Command Regis-
ter in Block Control Win-
dows8 48 In Bytes
Status Register Offset in
Block Control Window8 56 Logical offset in bytes. Refer to Note1. The start of the sub-
sequent Block Control Window is calculated by adding Size
Size of Status Register in
Block Control Windows8 64 In Bytes
gion Flag2 72 Bit [0] set to 1 to indicate that the Block Data Windows im-
plementation is buffered. The content of the data window is
only valid when so indicated by Status Register.
Reserved 6 74 Reserved
Notes for above table:
(a) See JEDEC Standard No. 21-C JEDEC Conﬁgurations for Solid State Memories , Annex L: Serial Presence
Detect (SPD) for DDR4 SDRAM modules, DDR4 SPD Document Release 2.
(b) See JEDEC Standard No. 21-C JEDEC Conﬁgurations for Solid State Memories , Annex L: Serial Presence
Detect (SPD) for DDR4 SDRAM modules, DDR4 SPD Document Release 3 (forthcoming).
5.2. ACPI System Description Tables 214Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
(c) In an NVDIMM, the module contains a non-volatile memory subsystem controller.
(d) See JEDEC Standard No. 2233-22 B yte Addressable Energy Backed Interface, Version 1.0 (forthcoming).
Note: “Logical offset” in the structure above refers to the offset from the start of NVDIMM Control Region. The
logical offset is with respect to the device, not with respect to system physical address space. Software should construct
the device address space (accounting for interleave) before applying the block control start offset.
5.2.26.7 NVDIMM Block Data Window Region Structure
This structure shall be provided only if the number of Block Data Windows is non-zero.
Table 5.134: NVDIMM Block Data Windows Region Structure
Field Byte
Type 2 0 5 - NVDIMM Block Data Window Region Structure
gion Structure Index2 4 Provides association for the corresponding NVDIMM Control
Region. Shall be Non-zero.
Number of Block Data
Windows2 6 Number of Block Data Windows shall match the correspond-
ing number of Block Control Windows.
Block Data Window Start
Offset8 8 Logical offset in bytes (see note below). The start of the sub-
sequent Block Data Window is calculated by adding Size of
Block Data Window.
Size of Block Data Win-
dow8 16 In Bytes
Block Accessible Mem-
ory Capacity8 24 In Bytes
Beginning address of ﬁrst
block in Block Accessible
Memory8 32 In Bytes. The address of the next block is obtained by adding
the value of this ﬁeld to Size of Block Data Window.
Note: Logical offset in table above refers to offset from the start of NVDIMM Data Window Region. The logical
offset is with respect to the device not with respect to system physical address space. Software should construct the
device address space (accounting for interleave) before applying the Block Data Window start offset.
5.2.26.8 Flush Hint Address Structure
Software needs an assurance of durability (i.e. a guarantee that the writes have reached the target NVDIMM) after
writing to a NVDIMM region. The Flush Hint feature is platform speciﬁc and if supported, the platform exposes this
durability mechanism to OSPM by providing a Flush Hint Address Structure.
For a given NVDIMM (as indicated by the NFIT Device Handle in the Flush Hint Address Structure), software can
write to any one of these Flush Hint Addresses to cause any preceding writes to the NVDIMM region to be ﬂushed out
of the intervening platform buffers to the targeted NVDIMM (to achieve durability). Note that the platform buffers do
not include processor cache(s)! Processors typically include ISA to ﬂush data out of processor caches.
5.2. ACPI System Description Tables 215Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.135: Flush Hint Address Structure
Field Byte
Type 2 0 6 - Flush Hint Address Structure
NFIT Device Handle 4 4 Indicates the NVDIMM supported by the Flush Hint Ad-
dresses in this structure.
Number of Flush Hint Ad-
dresses in this structure
(m)2 8 Number of Flush Hint Addresses in this structure.
Reserved 6 10 Reserved
Flush Hint Address 1 8 16 64-bit system physical address that needs to be written to
cause durability ﬂush. Software is allowed to write up to a
cache line of data. The content of the data is not relevant to

Field Byte
the functioning of the ﬂush hint mechanism.
. . . 8 24
Flush Hint Address m 8 16+
((m-
1)*8)64-bit system physical address that needs to be written to
5.2.26.9 Platform Capabilities Structure
This structure informs OSPM of the NVDIMM platform capabilities.
Table 5.136: Platform Capabilities Structure
Field Byte
Type 2 0 7 - Platform Capabilities Structure
Highest Valid Capability 1 4 The bit index of the highest valid capability implemented by
the platform. The subsequent bits shall not be considered to
determine the capabilities supported by the platform.
Reserved 3 5 Reserved (0)
5.2. ACPI System Description Tables 216Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.136 – continued from previous page
Field Byte
Capabilities 4 8
Bit[0] - CPU Cache Flush to NVDIMM Durability on Power
Loss Capable. If set to 1, indicates that platform ensures the
entire CPU store data path is ﬂushed to persistent memory on
system power loss.
Bit[1] - Memory Controller Flush to NVDIMM Durability
on Power Loss Capable. If set to 1, indicates that platform
provides mechanisms to automatically ﬂush outstanding
write data from the memory controller to persistent memory
in the event of platform power loss. Note: If bit 0 is set to 1
then this bit shall be set to 1 as well.
Bit[2] - Byte Addressable Persistent Memory Hardware
Mirroring Capable. If set to 1, indicates that platform
supports mirroring multiple byte addressable persistent
memory regions together. If this feature is supported and
enabled, healthy hardware mirrored interleave sets will have
the EFI_MEMORY_MORE_RELIABLE Address Range
Memory Mapping Attribute set in the System Physical
Address Range structure in the NFIT table.
Bits[31:3] - Reserved
Reserved 4 12 Reserved (1)
5.2.26.10 NVDIMM Representation Format
If software or an NVDIMM manufacturer displays, prints on a label, or otherwise makes available an identiﬁer for an
NVDIMM (e.g., to uniquely identify the NVDIMM), then the following hexadecimal format should be used:
• If the Manufacturing Location and Manufacturing Date ﬁelds are valid:
C language format string: " %02x%02x -%02x-%02x%02x -%02x%02x%02x%02x "
Format values:
1. Vendor ID byte 0 (including the parity bit)
2. Vendor ID byte 1
3. Manufacturing Location byte
4. Manufacturing Date byte 0 (i.e., the year)
5. Manufacturing Date byte 1 (i.e., the week)
6. Serial Number byte 0
7. Serial Number byte 1
8. Serial Number byte 2
9. Serial Number byte 3
• If the Manufacturing Location and Manufacturing Date ﬁelds are not valid:
5.2. ACPI System Description Tables 217Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
C language format string: " %02x%02x -%02x%02x%02x%02x "
3. Serial Number byte 0
4. Serial Number byte 1
5. Serial Number byte 2
6. Serial Number byte 3
This format matches the order of SPD bytes 320 to 328 from low to high (i.e., showing the lowest or ﬁrst byte on the
left).
5.2.27 Secure Devices (SDEV) ACPI Table
The Secure DEVices (SDEV) table is a list of secure devices known to the system. The table is applicable to systems
where a secure OS partition and a non-secure OS partition co-exist. A secure device is a device that is protected by
the secure OS, preventing accesses from non-secure OS.
The table provides a hint as to which devices should be protected by the secure OS. The enforcement of the table is
provided by the secure OS and any pre-boot environment preceding it. The table itself does not provide any security
guarantees. It is the responsibility of the system manufacturer to ensure that the operating system is conﬁgured to
enable security features that make use of the SDEV table.
There are three options for each device in the system:
1) Device is listed in SDEV . “Allow handoff. . . ” ﬂag is clear. This provides a hint that the device should be
always protected within the secure OS. For example, the secure OS may require that a device used for user
authentication must be protected to guard against tampering by malicious software.
2) Device is listed in SDEV . “Allow handoff. . . ” ﬂag is set. This provides a hint that the device should be initially
protected by the secure OS, but it is up to the discretion of the secure OS to allow the device to be handed off
to the non-secure OS when requested. Any OS component that expected the device to be operating in secure
mode would not correctly function after the handoff has been completed. For example, a device may be used for
variety of purposes, including user authentication. If the secure OS determines that the necessary components
for driving the device are missing, it may release control of the device to the non-secure OS. In this case, the
device cannot be used for secure authentication, but other operations can correctly function.
3) Device not listed in SDEV . For example, the status quo is that no hints are provided. Any OS component that
expected the device to be in secure mode would not correctly function.
The OS vendor provides guidance on which devices can be listed in the SDEV table. In other words, which devices
are compatible with the secure OS, and which devices should have the “allow handoff” ﬂag set.
See the following table for the SDEV ACPI deﬁnition.
Table 5.137: SDEV ACPI Table
Field Byte
Header
- Signature 4 0 ‘SDEV’. Signature for the Table
- Length 4 4 Length, in bytes, of the entire Table.
5.2. ACPI System Description Tables 218Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.137 – continued from previous page
Field Byte
- OEM ID 6 10 OEM ID
- OEM Table ID 8 16 For the SDEV Table, the table ID is the manufacturer model
ID.
- OEM Revision 4 24 OEM revision of SDEV Table for supplied OEM Table ID.
Secure Device Structures
[]— 36 A list of structures containing one or more Secure Device
Structures as deﬁned in next section.
5.2.27.1 Secure Device Structures
Table 5.138: Secure Device Structures
0 ACPI_NAMESPACE_DEVICE based Secure Device.
1 PCIe Endpoint Device-based Secure Device.
All Other Values Reserved for future use. For forward compatibility, software skips structures it does not
comprehend by skipping the appropriate number of bytes indicated by the Length ﬁeld. All
new device structures must include the Type, Flags, and Length ﬁelds as the ﬁrst 3 ﬁelds
5.2.27.1.1 ACPI_NAMESPACE_DEVICE based Secure Device Structure
Table 5.139: ACPI_NAMESPACE_DEVICE based Secure Device
Structure
Field Byte
Type 1 0 0x00: ACPI integrated devices
Flags 1 1
Bit 0: Allow handoff to non-secure OS. All other bits are
reserved and must be zero.
Bit 1: Secure Access Components present.
Length 2 2 Length of this entry in bytes.
Device Identiﬁer Offset 2 4 Offset, in the Secure ACPI Device structure, of a null termi-
nated ASCII string that contains a fully qualiﬁed reference to
the ACPI namespace object that is this device. (For example,
\\_SB.I2C0 represents the ACPI object name for an embed-
ded I2C Device in southbridge; Quotes are omitted in the data
ﬁeld). Refer to ACPI speciﬁcation for fully qualiﬁed refer-
ences for ACPI name-space objects.
Device Identiﬁer Length 2 6 Length of Device Identiﬁer string in bytes, including the ter-
mination byte.
5.2. ACPI System Description Tables 219Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.139 – continued from previous page
Field Byte
Vendor speciﬁc data Off-
set2 8 Offset, in Secure ACPI Device Structure, of the data speciﬁc
to the device supplied by the vendor.
Vendor speciﬁc data
Length2 10 Length of the data speciﬁc to the device supplied by the ven-
dor.
Secure Access Compo-
nents Offset2 12 Offset, in ACPI_NAMESPACE_DEVICE based Secure De-
vice Structure, of the list of Secure Access Components
needed for device execution in a secure OS. Only present if
the “secure access components present” bit is set.
nents Length2 14 Length of the list of Secure Access Components data. Only
present if the “secure access components present” bit is set.
Table 5.140: Secure Access Component Types
0 Identiﬁcation Based Secure Access Component. A minimum of one is required for a secure

Field Byte
dor.
device. When there are multiple Identiﬁcation Components present, priority is determined
by list order. See Table 5.141
1 Memory Based Secure Access Component. See Table 5.142
All other values Reserved for future use. For forward compatibility, software skips structures that it does not
new device structures must include the Type, Flags, and Length ﬁelds as the ﬁrst 3 ﬁelds,
Table 5.141: Identiﬁcation Based Secure Access Component
Field Byte
Type 1 0 0x00: Identiﬁcation Component. See Table 5.140
Flags 1 1 Reserved for future use.
Length 2 2 Length of this Entry in Bytes.
Hardware Identiﬁer Offset 2 4
Offset, in Identiﬁcation Component Structure, of a null
terminated ASCII string that contains the Hardware
Identiﬁer.
The Hardware Identiﬁer is a PNP or ACPI ID. A valid PNP
ID must be of the form “AAA####” where A is an uppercase
letter and # is a hex digit.
A valid ACPI ID must be of the form “NNNN####” where N
is an uppercase letter or a digit.
The Hardware Identiﬁer is a required ﬁeld.
Hardware Identiﬁer
Length2 6 Length of the Hardware Identiﬁer in bytes including the ter-
5.2. ACPI System Description Tables 220Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.141 – continued from previous page
Field Byte
Subsystem Identiﬁer Off-
set2 8
terminated ASCII string that contains the Subsystem
The Subsystem Identiﬁer is a PNP or ACPI ID. The
Hardware Identiﬁer is a PNP or ACPI ID. A valid PNP ID
must be of the form “AAA####” where A is an uppercase
The Subsystem Identiﬁer is optional. If a Subsystem
Identiﬁer is not present. This value should be 0.
Subsystem Identiﬁer
Length2 10 Length of the Subsystem Identiﬁer in bytes including the ter-
Hardware Revision 2 12 The Hardware Revision.
Hardware Revision
Present1 14 If 0, the Hardware Revision is ignored.
Class Code Present 1 15 If 0, the PCI-Compatible Class code is ignored.
PCI-Compatible Base-
Class1 16 The PCI-Compatible Base-Class code.
PCI-Compatible Sub-
Class1 17 The PCI-Compatible Sub-Class code.
PCI-Compatible Pro-
gramming Interface1 18 The PCI-Compatible Programming Interface Code.
Table 5.142: Memory-based Secure Access Component
Field Byte
Type 1 0 0x01: Memory Component.
Reserved 4 4 Padding.
Memory Address Base 8 8 Starting address of the memory component.
Memory Length 8 16 Length of the memory component in Bytes.
5.2.27.1.2 PCIe Endpoint Device-based Device Structure
Table 5.143: PCIe Endpoint Device-based Device Structure
Field Byte
Type 1 0 0x01: PCIe Endpoint device.
Flags 1 1 Bit 0: Allow handoff to non-secure OS. All other bits are re-
served and must be zero.
5.2. ACPI System Description Tables 221Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.143 – continued from previous page
Field Byte
PCI Segment Number 2 4 PCI segment number of the device .
Start Bus Number 2 6 This ﬁeld describes the bus number (bus number of the ﬁrst
PCI Bus produced by the PCI Host Bridge) under which the
secure device resides.
PCI Path Offset 2 8 Pointer to the PCI path entry offset in the Secure PCI Device
Structure data region. A PCI Path describes the hierarchal
path from the Host Bridge to the device. For example, a de-
vice in an N-deep hierarchy is identiﬁed by N {PCI Device
Number, PCI Function Number} pairs, where N is a positive
integer. Even numbered offsets contain the Device numbers,
and odd numbered offsets contain the Function numbers. The
ﬁrst {Device, Function} pair resides on the bus identiﬁed by
the ‘Start Bus Number’ ﬁeld. Each subsequent pair resides on
the bus directly behind the bus of the device identiﬁed by the
previous pair. The identity (Bus, Device and Function) of the
target device is obtained by recursively walking down these N
{Device, Function} pairs.
PCI Path Length 2 10 Length of the PCI path entry.
set2 12 Offset of the data speciﬁc to the device.
Length2 14 Length of the data speciﬁc to the device.
Example
The following table is an example for implementing a PCIe Endpoint Device Based Device Structure for a PCIe device
(Bus 1, Dev 2, Function 1), that is a child of a PCIe Root Port (Bus 0, Dev 18, Function 0).
Table 5.144: PCIe Endpoint Device-based Device Structure Example
Field Byte
OffsetValue
Flags 1 1 0x01
Length 2 2 0x18
PCI Segment Number 2 4 0x0
Start Bus Number 2 6 0x0
PCI Path Offset 2 8 0x10 (16 DEC)
PCI Path Length 2 10 0x4
Vendor-speciﬁc data Off-
set2 12 0x14 (20 DEC)
Vendor-speciﬁc data
Length2 14 0x4
PCI Path
PCI Device 1 16 0x12 (18 DEC)
PCI Function 1 17 0x0
PCI Device 1 18 0x2
PCI Function 1 19 0x1
Vendor speciﬁc data 4 20 0xDEADBEEF
5.2. ACPI System Description Tables 222Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.28 Heterogeneous Memory Attribute Table (HMAT)
5.2.28.1 HMAT Overview
The Heterogeneous Memory Attribute Table (HMAT) describes the memory attributes, such as memory side cache
attributes and bandwidth and latency details, related to Memory Proximity Domains. The software is expected to use
this information as a hint for optimization, or when the system has heterogeneous memory.
OSPM evaluates HMAT only during system initialization. Any changes to the HMAT state at runtime or information
regarding HMAT for hot plug are communicated using the _HMA method.
The HMAT consists of the following structures:
1. Memory Proximity Domain Attributes Structure(s). Describes attributes of memory proximity domains. See
Table 5.147.
2. System Locality Latency and Bandwidth Information Structure(s). Describes the memory access latency and
bandwidth information from various memory access initiator proximity domains. See Section 5.2.28.4. The op-
tional access mode and transfer size parameters indicate the conditions under which the Latency and Bandwidth
are achieved.
3. Memory Side Cache Information Structure(s). Describes memory side cache information for memory proximity
domains if the memory side cache is present and the physical device (SMBIOS handle) forms the memory side
cache. See Table 5.149.
These structures are illustrated by the following ﬁgure.
Fig. 5.10: HMAT Representation
5.2. ACPI System Description Tables 223Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.145: Heterogeneous Memory Attribute Table Header
Field Byte
Header
- Signature 4 0 ‘HMAT’ is Signature for this table
- Revision 1 8 2
Reserved 4 36 To make the structures 8 byte aligned
HMAT Table Structures[n] — 40 A list of HMAT table structures for this implementation.
Table 5.146: HMAT Structure Types
0 Memory Proximity Domain Attributes Structure
1 System Locality Latency and Bandwidth Information Structure
2 Memory Side Cache Information Structure
3-0xFFFF Reserved
5.2.28.2 Memory Side Cache Overview
Memory side cache allows to optimize the performance of memory subsystems. Fig. 5.11 shows an example of system
physical address (SPA) range with memory side cache in front of actual memory that is seen by the software. When
the software accesses an SPA, if it is present in the near memory (hit) it would be returned to the software, if it is not
present in the near memory (miss) it would access the next level of memory and so on.
The term “far memory” is used to denote the last level memory (Level 0 Memory) in the memory hierarchy as shown in
Fig. 5.11. The Level n Memory acts as memory side cache to Level n-1 Memory and Level n-1 memory acts as memory
side cache for Level n-2 memory and so on. If Non-V olatile memory is cached by memory side cache, then platform is
responsible for persisting the modiﬁed contents of the memory side cache corresponding to the Non-V olatile memory
area on power failure, system crash or other faults.
5.2.28.3 Memory Proximity Domain Attributes Structure
This structure describes the system physical address (SPA) range occupied by the memory subsystem and its associa-

tivity with processor proximity domain as well as hint for memory usage.
Table 5.147: Memory Proximity Domain Attributes Structure
Field Byte
Type 2 0 0 - Memory Proximity Domain Attributes Structure
Reserved 2 2
Length 4 4 40 - Length in bytes for entire structure.
5.2. ACPI System Description Tables 224Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.147 – continued from previous page
Field Byte
Flags 2 8 Bit [0]: set to 1 to indicate that data in the Proximity
Domain for the Attached Initiator ﬁeld is valid. Bit [1]:
Reserved. Previously deﬁned as Memory Proximity Do-
main ﬁeld is valid. Deprecated since ACPI 6.3. Bit [2]:
Reserved. Previously deﬁned as Reservation Hint. Dep-
recated since ACPI 6.3. Bits [15:3] : Reserved.
Reserved 2 10
Proximity Domain for the At-
tached Initiator4 12 This ﬁeld is valid only if the memory controller respon-
sible for satisfying the access to memory belonging to
the speciﬁed memory proximity domain is directly at-
tached to an initiator that belongs to a proximity do-
main. In that case, this ﬁeld contains the integer that
represents the proximity domain to which the initiator
(Generic Initiator or Processor) belongs. This num-
ber shall match the corresponding entry in the SRAT
table’s processor afﬁnity structure (e.g., Processor Lo-
cal APIC/SAPIC Afﬁnity Structure, Processor Local
x2APIC Afﬁnity Structure, GICC Afﬁnity Structure) if
the initiator is a processor, or the Generic Initiator Afﬁn-
ity Structure if the initator is a generic initiator. Note:
this ﬁeld provides additional information as to the ini-
tiator node that is closest (as in directly attached) to
the memory address ranges within the speciﬁed mem-
ory proximity domain, and therefore should provide the
best performance.
Proximity Domain for the Mem-
ory4 16 Integer that represents the memory proximity domain to
which this memory belongs.
Reserved 4 20
Reserved 8 24 Previously deﬁned as the Start Address of the System
Physical Address Range. Deprecated since ACPI Spec-
iﬁcation 6.3.
Reserved 8 32 Previously deﬁned as the Range Length of the region in
bytes. Deprecated since ACPI Speciﬁcation 6.3.
5.2.28.4 System Locality Latency and Bandwidth Information Structure
This structure provides a matrix that describes the normalized memory read/write latency, the read/write bandwidth
between Initiator Proximity Domains (Processor or I/O) and Target Proximity Domains (Memory).
The Entry Base Unit for latency is in picoseconds. The Entry Base Unit for bandwidth is in megabytes per second
(MB/s). The Initiator to Target Proximity Domain matrix entry can have one of the following values:
• 1-0xFFFE: the corresponding latency or bandwidth information expressed in multiples of Entry Base Unit.
• 0xFFFF: the initiator and target domains are unreachable from each other.
The represented latency or bandwidth value is determined as follows:
• Represented latency = (Initiator to Target Proximity Domain matrix entry value * Entry Base Unit) picoseconds.
• Represented bandwidth = (Initiator to Target Proximity Domain matrix entry value * Entry Base Unit) MB/s.
The following examples show how to report latency and throughput values:
5.2. ACPI System Description Tables 225Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 5.11: Memory Side Cache Example
• If the “Entry Base Unit” is 1 for latency and the matrix entry has the value of 10, the latency is 10 picoseconds.
• If the “Entry Base Unit” is 1000 for latency and the matrix entry has the value of 100, the latency is 100
• If the “Entry Base Unit” is 1 for BW and the matrix entry has the value of 10, the BW is 10 MB/s.
• If the “Entry Base Unit” is 1024 for BW and the matrix entry has the value of 100, the BW is 100 GB/s.
Note: The lowest latency number represents best performance and the highest bandwidth number represents best
performance. The latency and bandwidth numbers represented in this structure correspond to speciﬁcation rated
latency and bandwidth for the platform. The represented latency is determined by aggregating the speciﬁcation rated
latencies of the memory device and the interconnects from initiator to target. The represented bandwidth is determined
by the lowest bandwidth among the speciﬁcation rated bandwidth of the memory device and the interconnects from
the initiator to target.
Multiple table entries may be present, based on qualifying parameters, like minimum transfer size, etc. They may
be ordered starting from most- to least-optimal performance. Unless speciﬁed otherwise in the table, the reported
numbers assume naturally aligned data and sequential access transfers. The platform should declare “Minimum trans-
fer size” based on distinct, software observable boundaries for latency or bandwidth, as appropriate for the platform
5.2. ACPI System Description Tables 226Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.148: System Locality Latency and Bandwidth Information
Structure
Field Byte
Type 2 0 1 - System Locality Latency and Bandwidth Information
Structure
Length 4 4 Length in bytes for entire structure.
Flags 1 8
Bits [3:0] Memory hierarchy:
0x00 - Memory: If the memory side cache is not
present, this structure represents the memory
performance. If memory side cache is present, this
structure represents the memory performance when no
hits occur in any of the memory side caches associated
with the memory.
0x01 - 1st level memory side cache
0x02 - 2nd level memory side cache
0x03 - 3rd level memory side cache
Bits [5:4] Access attributes:
0x10 – minimum transfer size to achieve values
0x20 – non-sequential transfers
Bits [7:6] Reserved
Data Type 1 9
Type of data represented by this structure instance:
If Memory Hierarchy = 0:
- 0 - Access Latency (if read and write latencies are
same)
- 1 - Read Latency
- 2 - Write Latency
- 3 - Access Bandwidth (if read and write bandwidth
are same)
- 4 - Read Bandwidth
- 5 - Write Bandwidth
If Memory Hierarchy = 1, 2, or 3:
- 0 - Access Hit Latency (if read hit and write hit
latencies are same)
- 1 - Read Hit Latency
- 2 - Write Hit Latency
- 3 - Access Hit Bandwidth (if read hit and write hit
latency are same)
- 4 - Read Hit Bandwidth
- 5 - Write Hit Bandwidth
5.2. ACPI System Description Tables 227Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.148 – continued from previous page
Field Byte
MinTransferSize 1 10
Transfer size deﬁned as a 5-biased power of 2 exponent,
when the bandwith/latency value is achieved. The values are
0 – byte-aligned (any alignment)
1 – 64 Bytes
2 – 128 Bytes
3 – 256 Bytes
. . .
7 – 4096 Bytes
8 - 8192 Bytes
. . .
11 – 64KiByte
. . .
Reserved 1 11 Reserved
Number of Initiator Prox-
imity Domains (s)4 12 Indicates total number of Proximity Domains that can initiate
memory access requests to other proximity domains. This is
typically the processor or I/O proximity domains.
Number of Target Proxim-
ity Domains (t)4 16 Indicates total number of Proximity Domains that can act as
target. This is typically the Memory Proximity Domains.
Reserved 4 20 Reserved
Entry Base Unit 8 24 Base unit for Matrix Entry Values (latency or bandwidth).
Base unit for latency in picoseconds. Base unit for bandwidth
in megabytes per second (MB/s). This ﬁeld shall be non-zero.
Initiator Proximity Do-
main List[0]4 32
main List[1]4
. . .
main List[s-1]4
Target Proximity Domain
List[0]4 32 + 4 x
s
List[1]4
. . .
List[t-1]4
Latency / bandwith val-
uesTotal Number Entry shall be equal to Number of Initiator
Proximity Domains * Number of Target Proximity Domains
Entry[0][0] 2 32 + 4 x
s + 4 x tMatrix entry (Initiator Proximity Domain List[0], Target
Proximity Domain List[0])
Entry[0][1] 2 Matrix entry (Initiator Proximity Domain List[0], Target
Proximity Domain List[1])
. . .
5.2. ACPI System Description Tables 228Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Field Byte
Entry[0][Number of Tar-
get Proximity Domains -
1]2 Matrix entry (Initiator Proximity Domain List[0], Target
Proximity Domain List[t-1])
Entry[1][0] 2 Matrix entry (Initiator Proximity Domain List[1], Target
Entry[1][1] 2 Matrix entry (Initiator Proximity Domain List[1], Target
. . .
Entry[1][Number of Tar-
1]Matrix entry (Initiator Proximity Domain List[1], Target
. . .
Entry[Number of Initiator
Proximity Domains - 1][
ity Domains -1]2 Matrix entry (Initiator Proximity Domain List[s-1], Target
Implementation notes:

. . .
Field Byte
. . .
. . .
The Flag ﬁeld in this table allows read latency, write latency, read bandwidth and write bandwidth as well
as Memory Hierarchy levels, minimum transfer size and access attributes. Hence this structure could be
repeated several times, to express all the appropriate combinations of Memory Hierarchy levels, memory
and transfer attributes expressed for each level. If multiple structures are present, they may be ordered
starting from most- to least-optimal performance. Unless speciﬁed otherwise in the table, the reported
numbers assume naturally aligned data and sequential access transfers.
If either latency or bandwidth information is being presented in the HMAT, it is required to be complete
with respect to initiator-target pair entries. For example, if read latencies are being included in the SLLBI,
then read latencies for all initiator-target pairs must be present. If some pairs are incalculable, then the
read latency dataset must be omitted entirely. It is acceptable to provide only a subset of the possible
datasets. For example, it is acceptable to provide read latencies but omit write latencies. This provides
OSPM a complete picture for at least one set of attributes, and it has the choice of keeping that data or
discarding it.
The platform should declare “Minimum transfer size” based on distinct, software-observable boundaries
for latency or bandwidth, as appropriate for the platform architecture.
If both SLIT table and the HMAT table with the memory latency information are present, the OSPM
should attempt to use the data in the HMAT rather than the data in the SLIT.
5.2.28.5 Memory Side Cache Information Structure
System memory hierarchy could be constructed to have a large size of low performance far memory and smaller size
of high performance near memory. The Memory Side Cache Information Structure describes memory side cache
information for a given memory domain. The software could use this information to effectively place the data in
memory to maximize the performance of the system memory that use the memory side cache.
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Table 5.149: Memory Side Cache Information Structure
Field Byte
Type 2 0 2 - Memory Side Cache Information Structure
Proximity Domain for the
Memory4 8 Integer that represents the memory proximity domain to
which the memory side cache information applies. This num-
ber shall match the corresponding entry in the SRAT table’s
Reserved 4 12
Memory Side Cache Size 8 16 Size of memory side cache in bytes for the above memory
proximity domain.
Cache Attributes 4 24
Bits [3:0] - Total Cache Levels for this Memory Proximity
Domain:
- 0 - None
- 1 - One level cache
- 2 - Two level cache
- 3 - Three level cache
Bits [7:4] - Cache Level described in this structure:
- 0 - None
Bits [11:8] - Cache Associativity:
- 0 - None
- 1 - Direct Mapped
- 2 - Complex Cache Indexing (implementation
speciﬁc)
Bits [15:12] - Write Policy
- 0 - None
- 1 - Write Back (WB)
- 2 - Write Through (WT)
Bits [31:16] - Cache Line size in bytes. Number of bytes
accessed from next cache level on cache miss.
Reserved 2 28
Number of SMBIOS han-
dles (n)2 30 Number of SMBIOS handles that contributes to the memory
side cache physical devices.
SMBIOS Handles 2xn 32 Refers to corresponding SMBIOS Type-17 Handles Structure
that contains Physical Memory Component related informa-
tion
Implementation Note: A proximity domain should contain only one set of memory attributes. If memory attributes
differ, represent them in different proximity domains. If the Memory Side Cache Information Structure is present, the
5.2. ACPI System Description Tables 230Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
System Locality Latency and Bandwidth Information Structure shall contain latency and bandwidth information for
each memory side cache level.
5.2.29 Platform Debug Trigger Table (PDTT)
This section describes the format of the Platform Debug Trigger Table (PDTT) description table, which is an optional
table that describes one or more PCC subspace identiﬁers that can be used to trigger/notify the platform speciﬁc debug
facilities to capture non-architectural system state. This is intended as a standard mechanism for the OSPM to notify
the platform of a fatal crash (e.g. kernel panic or bug check).
This table is intended for platforms that provide debug hardware facilities that can capture system info beyond the
normal OS crash dump. This trigger could be used to capture platform speciﬁc state information (e.g. ﬁrmware state,
on-chip hardware facilities, auxiliary controllers, etc.). This type of debug feature could be leveraged on mobile, client,
and enterprise platforms.
Certain platforms may have multiple debug subsystems that must be triggered individually. This table accommodates
such systems by allowing multiple triggers to be listed.
After triggering debug facilities, the CPU may continue to operate as expected so that the kernel may continue with
crash processing/handling (e.g. possibly attempting to attach a debugger or proceed with a full crash dump prior to
rebooting the system), depending on the value deﬁned in Trigger order. Please refer to Section 5.2.29.2 for more
details.
After triggering debug facilities, the CPU must continue to operate as expected so that the kernel may continue with
rebooting the system).
On some platforms, the debug trigger may put some hardware components/peripherals into a frozen non-operational
state, and so the debug trigger is not recommended to be used during normal run-time operation.
Other platforms may allow the debug trigger for capture system state to debug run-time behavioral issues (e.g. system
performance and power issues), speciﬁed by the “Run-time” ﬂag ﬁeld in Table 5.151.
When multiple triggers exist, the triggers within each of the two groups, deﬁned by trigger order, will be executed in
order. OSPM may need to wait for PCC completion before executing next trigger based on the “Wait for Completion”
ﬂag ﬁeld in Table 5.151.
Note: The mechanism by which this system debug state information is retrieved by the user is platform and vendor
speciﬁc. This will most likely will require special tools and privileges in order to access and parse the platform debug
information captured by this trigger.
Table 5.150: PDTT Structure
Field Byte
Signature 4 0 ‘PDTT’
Length 4 4 Length in bytes of the entire Platform Debug Trigger
Table
Revision 1 8 0
OEM ID 6 10 OEM ID
OEM Table ID 8 16 The table ID is the manufacturer model ID.
OEM Revision 4 24 OEM revision for supplied OEM Table ID.
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Table 5.150 – continued from previous page
Field Byte
Trigger Count 1 36 Number of PDTT Platform Communication Channel
Identiﬁers
Reserved 3 37 Must be zero
Trigger Identiﬁer Array Offset 4 40 Offset to the “PDTT Platform Communication Channel
Identiﬁers[]” Array
PDTT Platform Communication
Channel Identiﬁers []— Trigger
Iden-
tiﬁer
Array
OffsetArray of PDTT Platform Communication Channel Iden-
tiﬁers to notify various platform debug facilities. This
identiﬁer selects the PCC subspace index that must be
listed in the PCCT. It also describes per trigger ﬂags.
Each Identiﬁer is 2 bytes. Must provide a minimum of
one identiﬁer. See Table 5.151 below.
Table 5.151: PDTT Platform Communication Channel Identiﬁer
Structure
Field Bit
PDTT PCC Sub Channel Identi-
ﬁer8 0 PCC sub channel ID. Note: this must be an index listed
in the PCCT
Run-time 1 8 0: Trigger must only be invoked in fatal crash scenar-
ios. This debug trigger may put some hardware compo-
nents/peripherals into a frozen non-operational state. |
1: Trigger may be invoked at run-time as well as in fatal
crash scenarios.
Wait for Completion 1 9 0: OSPM may initiate next trigger immediately | 1:
OSPM must wait for PCC complete prior to initiating
the next trigger in the list
Trigger Order 1 10 Used in fatal crash scenarios: 0: OSPM must initiate
trigger before kernel crash dump processing | 1: OSPM
must initiate trigger at the end of crash dump process-
ing.
Reserved 5 11 Must be zero
5.2.29.1 PDTT PCC Sub Channel
The PDTT PCC Sub Channel Identiﬁer value provided by the platform in this ﬁeld is index in the PCCT table (as shown

Structure
Field Bit
in the PCCT
ing.
in the picture below). PCC Communications Subspace Structure for PDTT can use any type of PCC communication
subspace. PCC Sub Channel entry in PCCT table identiﬁed by the PDTT PCC Sub Channel Identiﬁer will have the
information on type of PCC Sub channel deﬁnition associated with the debug trigger. The PDTT references its PCC
Subspace in a given platform by this identiﬁer, as shown in Table 5.151.
Section 5.2.29.1 below shows how the right PCC subspace entry associated with a debug trigger in PDTT can be found
from the PCTT table.
5.2. ACPI System Description Tables 232Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 5.12: Mapping a PDTT Debug Trigger Table Entry to a PCCT PCC Subspace
5.2.29.1.1 Using PCC registers
A platform debug trigger can choose to use any type of PCC subspace. The deﬁnition of the shared memory region for
a debug trigger will follow the deﬁnition of shared memory region associated with the PCC subspace type used for the
debug trigger. For example if a platform debug trigger chooses to use Generic PCC communication subspace (Type
0), then it will use the Generic Communication Channel shared memory region described in Section 14.2. OSPM will
write PCC registers by ﬁlling in the register values in PCC sub channel space. If a platform debug trigger choose to
use a PCC communication subchannel that uses a Generic Communication shared memory region then it will write
the debug trigger command in the command ﬁeld. See Table 5.151 for allowed debug commands. All other command
values are reserved.
The platform can also use the PCC sub channel Type 5 for debug a trigger. In this case, OSPM will follow the PCC
sub channel deﬁnition and write to the doorbell register to trigger a debug log. A platform debug trigger using PCC
Communication sub channel Type 5 will use the shared memory region to share vendor-speciﬁc debug information.
The following table deﬁnes the Type-5 PCC channel shared memory region deﬁnition for debug trigger.
Table 5.152: Type 5 Platform Communication Channel Shared Mem-
ory
Field Byte
Signature 4 0 The PCC signature. The signature of a subspace is computed by
a bitwise-or of the value 0x50434300 with the subspace ID. For
example, subspace 3 has the signature 0x50434303.
Subspace
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Table 5.152 – continued from previous page
Field Byte
Vendor speciﬁc
space— 4 Vendor speciﬁc area to share additional information between OSPM
and platform. The length of the vendor speciﬁed area must be 4
bytes less than the Length ﬁeld speciﬁed in the PCCT entry referring
to this shared memory space.
Table 5.153: PCC Commands Codes used by Platform Debug Trigger
Table
0x00 Execute Platform Debug Trigger (doorbell only - no command/response).
0x01 Execute Platform Debug Trigger (with vendor speciﬁc command in communication space).
0x01-0xFF All other values are reserved.
Table 5.154: PDTT Platform Communication Channel
Field Bit
Signature 4 0 The PCC signature. The signature of a subspace is computed
by a bitwise-or of the value 0x50434300 with the subspace
ID. For example, subspace 3 has signature 0x50434303.
Command 2 4 PCC command ﬁeld, see Section 14 and Table 5.153
Status 2 6 PCC status ﬁeld (see Section 14)
Communication Space — — —
Vendor-speciﬁc Variable 8 Optional vendor speciﬁc command/response area written by
OSPM - must be zero if not supported
5.2.29.2 PDTT PCC Trigger Order
The trigger order deﬁnes two categories for triggers
Trigger Order 0: Triggers are invoked by OSPM before executing its crash dump processing functions.
Trigger Order 1: Triggers are invoked by OSPM at the end of crash dump processing functions, typically after the
kernel has processed crash dumps.
Capturing platform speciﬁc debug information from certain IPs would require intrusive mechanism which may limit
kernel operations after the operations. Trigger order allows the platform to deﬁne such operations that will be invoked
at the end of kernel operations by OSPM.
5.2.29.3 Example: OS Invoking Multiple Debug Triggers
To illustrate how these debug triggers are intended to be used by the OS, consider this example of a system with 4
independent debug triggers as shown in Fig. 5.13. These triggers are described to the OS via the PDTT example in
Table 5.155.
Note: This example assumes no vendor speciﬁc communication is required, so only PCC command 0x0 is used.
When the OS encounters a fatal crash, prior to collecting a crash dump and rebooting the system, the OS may choose
to invoke the debug triggers in the order listed in the PDTT. The addresses of the doorbell register and the PCC general
communication space (if needed) are retrieved from the PCCT, depending on the PCC subspace type (see Table 14.4,
Table 14.5, or Table 14.6).
5.2. ACPI System Description Tables 234Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 5.13: Example: Platform with four debug triggers
Table 5.155: Example: Platform with 4 debug triggers
Field Value Notes
Signature ‘PDTT’
. . . . . . . . .
Trigger Count 4 Describing the 4 triggers illustrated in Fig. 5.13 above
Reserved 0
Trigger Identiﬁer Array Offset 44
PDTT PCC Identiﬁers [0] 0x0004
[Bits 0:7] - 4 (channel subspace ID 4)
[Bit 8] - 0 (Trigger may only be invoked in fatal crash scenarios)
[Bit 9] - 0 (OSPM may initiate next trigger immediately)
PDTT PCC Identiﬁers [1] 0x0201
[Bits 0:7] - 1 (channel ID subspace 1)
[Bit 9] - 1 (OSPM must wait for PCC complete prior to initiating
the next trigger in the list)
PDTT PCC Identiﬁers [2] 0x0002
[Bits 0:7] - 2 (channel ID subspace 2)
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Table 5.155 – continued from previous page
PDTT PCC Identiﬁers [3] 0x0203
[Bits 0:7] - 3 (channel ID subspace 3)
Walking through the list of triggers in the PDTT, the OS may execute the following steps:
1. For Trigger 0, retrieves doorbell register address from PCCT per PCC subspace ID 4 and writes to it with
appropriate write/preserve mask. Since OS does not need to wait for completion, OS does not need to send a
PCC command and should ignore the PCC subspace base address
2. For Trigger 1, retrieves doorbell register address and PCC subspace address from PCCT per PCC subspace ID
1. Since OS must wait for completion, OS must write PCC command (0x0) and write to the doorbell register
per section 14 and poll for the completion bit.
3. For Trigger 2, , retrieves doorbell register address from PCCT per PCC subspace ID 2 and writes to it with
4. For Trigger 3, retrieves doorbell register address and PCC subspace address from PCCT per PCC subspace ID
3. Since OS must wait for completion, OS must write PCC command (0x0) and write to the doorbell register
Note: When wait for completion is necessary, the OS must poll bit zero (completion bit) of the status ﬁeld of that
PCC channel (see Table 14.6 and the Generic Communications Channel Shared Memory Region.
5.2.30 Processor Properties Topology Table (PPTT)
This optional table is used to describe the topological structure of processors controlled by the OSPM, and their shared
resources, such as caches. The table can also describe additional information such as which nodes in the processor
topology constitute a physical package. The structure of PPTT is described in Table 5.156 .
Table 5.156: Processor Properties Topology Table
Field Byte
Header
- Signature 4 0 ‘PPTT’ Processor Properties Topology Table
- Length 4 4 Length of entire PPTT table in bytes
- Checksum 1 9 The entire table must sum to zero.
- OEM Table ID 8 16 OEM revision of table for supplied OEM Table ID
- OEM Revision 4 24 OEM revision of the PPTT for the supplied OEM Table
ID.
Body
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Table 5.156 – continued from previous page
Field Byte
• Processor topology struc-

Field Byte
Header
ID.
Body
Field Byte
ture[N]— 36 List of processor topology structures
Note: Processor topology structures are described in the following sections.
5.2.30.1 Processor hierarchy node structure (Type 0)
The processor hierarchy node structure is described in Table 5.157 . This structure can be used to describe a single
processor or a group. To describe topological relationships, each processor hierarchy node structure can point to a
parent processor hierarchy node structure. This allows representing tree like topology structures. Multiple trees may
be described, covering for example multiple packages. For the root of a tree, the parent pointer should be 0.
If PPTT is present, one instance of this structure must be present for every individual processor presented through the
MADT interrupt controller structures. In addition, an individual entry must be present for every instance of a group
of processors that shares a common resource described in the PPTT. Resources are described in other PPTT structures
such as Type 1 cache structures. Each physical package in the system must also be represented by a processor node
Each processor node includes a list of resources that are private to that node. Resources are described in other PPTT
structures such as Type 1 cache structures. The processor node’s private resource list includes a reference to each of
the structures that represent private resources to a given processor node. For compactness, separate instances of an
identical resource can be represented with a single structure that is listed as a resource of multiple processor nodes.
For example, is expected that in the common case all processors will have identical L1 caches. For these platforms a
single L1 cache structure could be listed by all processors, as shown in the following ﬁgure.
Fig. 5.14: L1 Cache Structure
5.2. ACPI System Description Tables 237Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Note: though less space efﬁcient, it is also acceptable to declare a node for each instance of a resource. In the example
above, it would be legal to declare an L1 for each processor.
Note: Compaction of identical resources must be avoided if an implementation requires any resource instance to be
referenced uniquely. For example, in the above example, the L1 resource of each processor must be declared using a
dedicated structure to permit unique references to it.
Table 5.157: Processor Hierarchy Node Structure
Field Byte
Type 1 0 0 - processor structure
Length 1 1 Length of the local processor structure in bytes
Reserved 2 2 Must be zero
Flags 4 4 See Processor Structure Flags.
Parent 4 8 Reference to parent processor hierarchy node structure. The
reference is encoded as the difference between the start of the
PPTT table and the start of the parent processor structure en-
try. A value of zero must be used where a node has no parent.
ACPI Processor ID 4 12 If the processor structure represents an actual processor, this
ﬁeld must match the value of ACPI processor ID ﬁeld in the
processor’s entry in the MADT. If the processor structure rep-
resents a group of associated processors, the structure might
match a processor container in the name space. In that case
this entry will match the value of the _UID method of the as-
sociated processor container. Where there is a match it must
be represented. The ﬂags ﬁeld, described in Processor Struc-
ture Flags , includes a bit to describe whether the ACPI pro-
cessor ID is valid.
Number of private re-
sources4 16 Number of resource structure references in Private Resources
(below)
Private resources[N] N*4 20 Each resource is a reference to another PPTT structure. The
structure referred to must not be a processor hierarchy node.
Each resource structure pointed to represents resources that
are private the processor hierarchy node. For example, for
cache resources, the cache type structure represents caches
that are private to the instance of processor topology repre-
sented by this processor hierarchy node structure. The refer-
ences are encoded as the difference between the start of the
PPTT table and the start of the resource structure entry.
Processor Structure Flags are described in the following table.
Table 5.158: Processor Structure Flags
Field Bit
Physical package 1 0 Set to 1 if this node of the processor topology represents the
boundary of a physical package, whether socketed or surface
mounted. Set to 0 if this instance of the processor topology
does not represent the boundary of a physical package. Each
valid processor must belong to exactly one package. That is,
the leaf must itself be a physical package or have an ancestor
marked as a physical package.
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Table 5.158 – continued from previous page
Field Bit
ACPI Processor ID valid 1 1 For non-leaf entries in the processor topology, the ACPI Pro-
cessor ID entry can relate to a Processor container in the
namespace. The processor container will have a matching ID
value returned through the _UID method. As not every pro-
cessor hierarchy node structure in PPTT may have a matching
processor container, this ﬂag indicates whether the ACPI pro-
cessor ID points to valid entry. Where a valid entry is possible
the ACPI Processor ID and _UID method are mandatory. For
leaf entries in PPTT that represent processors listed in MADT,
the ACPI Processor ID must always be provided and this ﬂag
must be set to 1.
Processor is a Thread 1 2 For leaf entries: must be set to 1 if the processing element
representing this processor shares functional units with sibling
nodes. For non-leaf entries: must be set to 0.
Node is a Leaf 1 3 Must be set to 1 if node is a leaf in the processor hierarchy.
Else must be set to 0.
Identical Implementation 1 4 A value of 1 indicates that all children processors share an
identical implementation revision. This ﬁeld should be ig-
nored on leaf nodes by the OSPM. Note: this implies an
identical processor version and identical implementation re-
version, not just a matching architecture revision.
Reserved 27 5 Must be zero
Note: Threads sharing a core must be grouped under a unique Processor hierarchy node structure for each group of
threads.
Note: Processors may be marked as disabled in the MADT. In this case, the corresponding processor hierarchy node
structures in PPTT should be considered as disabled. Additionally, all processor hierarchy node structures representing
a group of processors with all child processors disabled should be considered as being disabled. All resources attached
to disabled processor hierarchy node structures in PPTT should also be considered disabled.
5.2.30.2 Cache Type Structure - Type 1
The cache type structure is described in Table 5.159. The cache type structure can be used to represent a set of caches
that are private to a particular processor hierarchy node structure, that is, to a particular node in the processor topology
tree. The set of caches is described as a NULL, or zero, terminated linked list. Only the head of the list needs to be
listed as a resource by a processor node (and counted toward Number of Private Resources), as the cache node itself
contains a link to the next level of cache.
Cache type structures are optional, and can be used to complement or replace cache discovery mechanisms provided
by the processor architecture. For example, some processor architectures describe individual cache properties, but do
not provide ways of discovering which processors share a particular cache. When cache structures are provided, all
processor caches must be described in a cache type structure.
Each cache type structure includes a reference to the cache type structure that represents the next level cache. The
level in this context must relate to the CPU architecture’s deﬁnition of cache level. The list must include all caches
that are private to a processor hierarchy node. It is not permissible to skip levels. That is, a cache node included in a
5.2. ACPI System Description Tables 239Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
given hierarchy processor node level must not point to a cache structure referred to by a processor node in a different
level of the hierarcy.
For example, if a node represents a CPU that has a private L1 and private L2 cache, the list would contain both caches
(L1->L2->0). If on the other hand the L2 cache was shared, the list would just include the L1 (L1->0), and a parent
processor topology node, to all processors that share the L2, would contain the cache type structure that represents the
shared L2.
Processors, or higher level nodes within the hierarchy, with separate instruction and data caches must describe the
instruction and data caches with separate linked lists of cache type structures both listed as private resources of the

shared L2.
relevant processor hierarchy node structure. If the separate instruction are data caches are uniﬁed at a higher level of
cache then the linked lists should converge.
Consider the example shown in the following ﬁgure.
Fig. 5.15: Cache Type Structure - Type 1 Example
5.2. ACPI System Description Tables 240Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
In this Type 1 example:
• Each processor has private L1 data, L1 intruction and L2 caches. The two processors are contained in a cluster
which provides an L3 cache.
• Each processor’s hierarchy node has two separate cache type structures as private resources for L1I and L1D
• Both the L1I and L1D cache structures point to the L2 cache structure as their next level of cache
• L2 cache type structure terminates the linked list of the CPU’s caches. The resulting list denotes all private
caches at the processor level
• Both processor nodes have their parent pointer pointing to node that represents the cluster.
• The cluster node includes the L3 cache as it’s private resource. The L3 node in turn has no next level of cache.
An entry in the list indicates primarily that a cache exists at this node in the hierarchy. Where possible, cache properties
should be discovered using processor architectural mechanisms, but the cache type structure may also provide the
properties of the cache. A ﬂag is provided to indicate whether properties provided in the table are valid, in which case
the table content should be used in preference to processor architected discovery. On Arm-based systems, all cache
properties must be provided in the table.
Table 5.159: Cache Type Structure
Field Byte
Type 1 0 1 - Cache type structure
Length 1 1 28
Flags 4 4 SeeCache Structure Flags .
Next Level of Cache 4 8 Reference to next level of cache that is private to the processor
topology instance. The reference is encoded as the difference be-
tween the start of the PPTT table and the start of the cache type
structure entry. This value will be zero if this entry represents
the last cache level appropriate to the the processor hierarchy node
structures using this entry.
Size 4 12 Size of the cache in bytes.
Number of sets 4 16 Number of sets in the cache
Associativity 1 20 Integer number of ways.
Attributes 1 21
Bits 1:0: Allocation type:
0x0 - Read allocate
0x1 - Write allocate
0x2 or 0x03 indicate Read and Write allocate
Bits:3:2: Cache type:
0x0 Data
0x1 Instruction
0x2 or 0x3 Indicate a uniﬁed cache
Bits 4: Write policy:
0x0 Write back
0x1 Write through
Bits:7:5 Reserved must be zero.
Line size 2 22 Line size in bytes
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Table 5.159 – continued from previous page
Field Byte
Cache ID 4 24 Unique, non-zero identiﬁer for this cache. If Cache ID is valid as in-
dicated by the Flags ﬁeld, then this structure deﬁnes a unique cache
in the system. A Cache ID value of 0 indicates a NULL identiﬁer
that is not valid.
The cache type structure ﬂags are described in the following table.
Table 5.160: Cache Structure Flags
Field Bit
Size property valid 1 0 Set to 1 if the size properties described is valid. A value of 0
indicates that, where possible, processor architecture speciﬁc
discovery mechanisms should be used to ascertain the value
of this property.
Number of sets valid 1 1 Set to 1 if the number of sets property described is valid. A
value of 0 indicates that, where possible, processor architec-
ture speciﬁc discovery mechanisms should be used to ascer-
tain the value of this property.
Associativity valid 1 2 Set to 1 if the associativity property described is valid. A value
of 0 indicates that, where possible, processor architecture spe-
ciﬁc discovery mechanisms should be used to ascertain the
value of this property.
Allocation type valid 1 3 Set to 1 if the allocation type attribute described is valid. A
tain the value of this attribute.
Cache type valid 1 4 Set to 1 if the cache type attribute described is valid. A value
value of this attribute.
Write policy valid 1 5 Set to 1 if the write policy attribute described is valid. A value
Line size valid 1 6 Set to 1 if the line size property described is valid. A value of 0
Cache ID Valid 1 7 Set to 1 if the Cache ID property described is valid. A value
Reserved 24 8 Must be zero
5.2. ACPI System Description Tables 242Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.2.31 Platform Health Assessment Table (PHAT)
This section describes the format of the Platform Health Assessment Table (PHAT), which provides a means by which
a platform can expose an extensible set of platform health related telemetry that may be useful for software running
within the constraints of an operating system. These elements are typically going to encompass things that are likely
otherwise not enumerable during the OS runtime phase of operations, such as version of pre-OS components, or health
status of ﬁrmware drivers that were executed by the platform prior to launch of the OS. It is not expected that the OSPM
would act on the data being exposed.
Table 5.161: Platform Health Assessment Table (PHAT) Format
Field Byte
Header
- Signature 4 0 PHAT Signature for the Platform Health Assessment Table.
- Length 4 4 The length of the table, in bytes, of the entire PHAT
ﬁeld for this table. For the PHAT conﬁrming to this revision
of the speciﬁcation, the revision is 1.
particular data table
- OEM Revision 4 24 OEM-supplied revision number.
Platform Telemetry Records – 36 The set of Platform Telemetry Records
5.2.31.1 Platform Health Assessment Record Format
A platform health assessment record is comprised of a sub-header including a record type and length, and a set of data.
The format of the record layout is speciﬁc to the record type. In this manner, records are only as large as needed to
contain the speciﬁc type of data to be conveyed.
Table 5.162: Platform Health Assessment Record Format
Field Byte
Platform Health Assess-
ment Record Type2 0 This value depicts the format and contents of the platform
health assessment record.
Record Length 2 2 This value depicts the length of the platform health assessment
record, in bytes.
Revision 1 4 This value is updated if the format of the record type is ex-
tended. Any changes to a platform health assessment record
layout must be backwards compatible in that all previously de-
ﬁned ﬁelds must be maintained if still applicable, but newly
deﬁned ﬁelds allow the length of the platform health record
to be increased. Previously deﬁned record ﬁelds must not be
redeﬁned, but are permitted to be deprecated.
Data – 5 The content of this ﬁeld is deﬁned by the Platform Health As-
sessment Record Type deﬁnition.
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5.2.31.2 Platform Health Assessment Record Type Format
The table below describes the various types of records contained within the PHAT, and their associated Platform Health
Assessment Record Type. Note that unless otherwise speciﬁed, multiple platform telemetry records are permitted in
the PHAT for a given type.
Table 5.163: Platform Health Assessment Record Type Format
0x0000 Firmware Version
Data RecordPre-OS platform health assessment record containing version data for
components within the platform ﬁrmware, option ROMs, and other
pre-OS platform components.
0x0001 Firmware Health
Data RecordPre-OS platform health assessment record containing health-related
information for pre-OS platform components.

0x0002 – 0x0FFF Reserved Reserved for ACPI speciﬁcation usage.
0x1000 – 0x1FFF Reserved Reserved for Platform Vendor usage.
0x2000 – 0x2FFF Reserved Reserved for Hardware Vendor usage.
0x3000 – 0x3FFF Reserved Reserved for Platform Firmware Vendor usage.
0x4000 – 0x4FFF Reserved Reserved for future use.
5.2.31.3 Firmware Version Data Record Structure
A platform health assessment record which contains the version-related information associated with pre-OS compo-
nents in the platform.
Table 5.164: PHAT Version Element
Field Byte
Component ID 16 0 Unique GUID associated with this component.
Version Value 8 16 64-bit version value
Producer ID 4 24
The ACPI Vendor ID (e.g. ‘ABCD’):
0xFFFF – no ID deﬁned
0x0000 – invalid value
Table 5.165: Firmware Version Data Record
Field Byte
Platform Record Type 2 0 0 – Firmware Version Data Record
Record Length 2 2 12+28*RecordCount – This value depicts the length of the
version data record, in bytes.
Revision 1 4 1 – Revision of this Firmware Version Data Record.
Reserved 3 5 Reserved
Record Count 4 8 PHAT Version Element Count
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Table 5.165 – continued from previous page
Field Byte
PHAT Version Element Varies 12 Array of PHAT Version Elements. First entry is the origi-
nal producer of the component, and if there’s a subsequent
entry, that means a second agent modiﬁed the original com-
ponent in some way, and whichever the last entry is, that’s
the currently running instance of the component. This allows
for IHV/IBV/OEM/others to establish a chain of data records
associated with a given component.
5.2.31.4 Firmware Health Data Record Structure
A platform health assessment record which contains the health-related information associated with pre-OS components
in the platform. This structure is intended to be used to identify the barebones state of a pre-OS component in a generic
fashion. In addition, the Device Path can give standardized hints of where in the pre-OS the platform resides, whether
it’s a well-known hardware node (e.g. storage controller) or some other vendor speciﬁc location that may be hanging
off another bus.
This structure also provides a means by which a platform could also expose device-speciﬁc data that goes beyond the
simple healthy and not healthy statement.
Table 5.166: Firmware Health Data Record Structure
Field Byte
Platform Record
Type2 0 1 – Firmware Health Data Record
Record Length 2 2 varies – This value depicts the length of the health data record, in
bytes.
Revision 1 4 1 – Revision of this Firmware Health Data Record.
Reserved 2 5 Reserved
AmHealthy 1 7
Has the device encountered any issues? This allows any agent
parsing this record to understand in whether or not the device is
healthy without needing to parse the device-speciﬁc health data.
Any device health state may expose device-speciﬁc data:
0= Errors found
1= No errors found
2= Unknown
3= Advisory – additional device-speciﬁc data exposed
DeviceSignature 16 8 The unique GUID associated with this device.
Device-speciﬁc
Data Offset4 24 Offset to the Device-speciﬁc Data from the start of this Data Record.
If 0, then there is no device-speciﬁc data.
Device Path Varies 28 The UEFI Device Path associated with the record producer. See
the UEFI speciﬁcation for the EFI_DEVICE_PATH_PROTOCOL
DataVaries Device-
speciﬁc
Data
OffsetThe health record associated with a particular device. Its deﬁnition
is speciﬁc to the given device that produced this record.
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5.2.31.5 Reset Reason Health Record
The Reset Reason Health Record deﬁnes a mechanism to describe the cause of the last system reset or boot. The record
will be created as a Health Record in the PHAT table. This provides a standard way for system ﬁrmware to inform the
operating system of the cause of the last reset. This includes both expected and unexpected events to support insights
across a ﬂeet of systems by way of collecting the reset reason records on each boot.
The record provides an optional vendor reason to capture the underlying state used to generate the reset reason (e.g.
hardware registers) to support vendor speciﬁc details. The reset reason is intended to supplement existing fault report-
ing mechanisms on the platform (e.g. BERT tables, CPER) or in the operating system (e.g. event logs)
Table 5.167: Reset Reason Health Record Header
Field Byte
Type2 0
1 - Firmware Health Data Record. Pre-OS platform health
assessment record containing health-related information for
Record Length 2 2
Varies - This value depicts the length of the health data record, in
bytes.
Revision 1 4
1 - Revision of this Firmware Health Data Record.
Reserved 2 5
Reserved
0 = Errors found
1 = No errors found
2 = Unknown
3 = Advisory - additional device-speciﬁc data exposed
The Reset Reason should set this value to ‘1’ (no error) for
expected resets/boots, and ‘0’ (error) for unexpected conditions.
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Table 5.167 – continued from previous page
DeviceSignature 16 8
The unique GUID associated with this health record type.
7a014ce2-f263-4b77-b88a-e6336b782c14
{0x7a014ce2, 0xf263, 0x4b77,
{0xb8, 0x8a, 0xe6, 0x33, 0x6b, 0x78, 0x2c, 0x14}}
This GUID is normative for this record type and must not be
changed.
Data Offset4 24
Offset to the Device-speciﬁc Data from the start of this Data
Record.
Offset = 0x0074
Device Path 88 28
The UEFI Device Path associated with the record producer. See the
UEFI speciﬁcation (https://ueﬁ.org/speciﬁcations) for the
EFI_DEVICE_PATH_PROTOCOL deﬁnition.
VenHw(7A014CE2-F263-4B77-B88A-E6336B782C14)
Data116 Varies
The reset reason health record associated with this reset/boot event.
Table 5.168: Reset Reason Health Record Structure
Field Byte
Supported Sources 1 0
This ﬁeld indicates which sources are supported on the platform. A
source that is unavailable may still provide insight into
interpretation of the reset. For example, a reset due to an operating
system fault without the operating system source supported may
appear as a warm reset.
[0]: Unknown source
[1]: Hardware source
[2]: Firmware source
[3]: Software source
[4]: Supervisor source
[7:5]: Reserved
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Table 5.168 – continued from previous page
Source 1 1
This ﬁeld indicates the source of the reset. Only one bit should be
set, or the ﬁeld should be set to zero if unknown.
[3]: Software initiated reset
[4]: Supervisor initiated reset
A ﬁrmware device may include a baseboard management
controller (BMC). A supervisor may include devices external to the
system such as an uninterruptible power supply or a KVM over IP
with power control.
Sub Source 1 2
The sub-source ﬁeld allows for an optional categorization of the
source ﬁeld. It must be zero if a sub-source is not deﬁned.
Unknown Source
[0]: Unknown
Hardware Source
Firmware Source
Software Source
1: Operating System
2: Hypervisor
Supervisor Source
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Reason 1 3
The reset reason represents the best explanation of the last system
reset or boot. The implementation should choose the reason that
best categorizes the last system reset or boot. The platform
implementation may choose which value to use when multiple
choices are possible, and should prefer a more speciﬁc reason over
a generic reason and an error condition over a non-error condition.
The reason ﬁeld is used in conjunction with the Source ﬁelds to
categorize and interpret the record.
0: UNKNOWN
The reset reason is unknown.
Expected reset reasons
1: COLD BOOT
The system was successfully booted from an ‘off’ state
(e.g. the user pressed the power button to boot).
2: COLD RESET
The system was successfully rebooted and performed a full
cold reset.
3: WARM RESET
The system was successfully reset. (e.g. a user initiated
reboot in the OS)
4: UPDATE
A system or software update was applied that required a
reset.

Reason 1 3
0: UNKNOWN
4: UPDATE
reset.
Unexpected reset reasons
32: UNEXPECTED RESET
An unexpected reset occurred. This may also include
undocumented reasons that do not ﬁt into another category.
A more speciﬁc category should be preferred when possible.
33: FAULT
A hardware, ﬁrmware or software fault occurred (e.g. an
uncorrectable
machine check, a uncorrectable software fault).
34: TIMEOUT
A timeout occurred. (e.g. a hardware, ﬁrmware or software
watchdog timeout).
35: THERMAL
A thermal limit was exceeded. (e.g. a hardware triggered
reset due to proc hot)
36: POWER LOSS
The system unexpectedly loss power.
37: POWER BUTTON
The user or external actor reset the system via a power
button press.
5.2. ACPI System Description Tables 249Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Vendor Count 2 4
The number of Vendor Speciﬁc Reset Reason entries.
Vendor Speciﬁc Re-
set Reason Entry[n]Varies 6
A series of Vendor Speciﬁc Reset Reason Entries.
The vendor portion of the record provides an optional means to store the underlying raw data that was interpreted to
produce the reset reason. Storing the underlying data associated with a reset may allow for further analysis (e.g. an
unexpected reset reason) and insight into the speciﬁcs of the reset.
Table 5.169: Reset Reason Health Record Vendor Data Entry
Field Byte
Vendor Data ID 16 0
A vendor deﬁned GUID that describes this entry type.
Length 2 16
The length of the vendor data entry.
Revision 2 18
Minor.Major Version
Byte 0 (Minor) indicates that changes to the vendor-speciﬁc data
are backwards compatible with the Vendor Data ID.
Byte 1 (Major) indicates that changes to the data are not backwards
compatible.
Data Varies 20
Vendor-speciﬁc data payload.
5.2.32 Virtual I/O Translation (VIOT) Table
The Virtual I/O Translation (VIOT) Table describes the topology of para-virtual I/O translation devices (e.g., virtio-
iommu in Linux) and the endpoints they manage. This is analogous to the vendor-speciﬁc IOMMU tables currently
deﬁned: the IORT for the ARM SMMU, the DMAR for Intel VT-d, and the IVRS for the AMD IOMMU. In this
case, however, we are deﬁning the topology connecting a hypervisor to a virtual machine through a para-virtualized
IOMMU, instead a vendor-speciﬁc device. Since this para-virtualized IOMMU is a software component between the
hypervisor and a virtual machine, the VIOT can be supported across multiple platforms; by deﬁning the VIOT here,
we help ensure consistency across those platforms since a para-virtualized IOMMU cannot be enumerated via any
other mechanisms.
This table is optional. If the VIOT table is present, the OSPM should assume this functionality is available for use and
must be conﬁgured properly.
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5.2.32.1 Virtual I/O Translation (VIOT) Table Header
The VIOT table starts with a standard ACPI header.
Table 5.170: Virtual I/O Translation (VIOT) Table format
Field Byte
Signature 4 0 “VIOT”, Virtual I/O Translation Table
Length 4 4 Length in bytes of the entire VIOT
Checksum 1 9 The entire table must sum to zero.
OEM ID 6 10 OEM Identiﬁer
OEM Table ID 8 16 For the VIOT, the table ID is the manufacture model ID
OEM Revision 4 24 OEM revision of the VIOT for the supplied OEM Table ID
Creator ID 4 28 The vendor ID of the utility that created the table
Creator Revision 4 32 The revision of the utility that created the table
Node Count 2 36 Number of nodes deﬁned in the table
Node Offset 2 38 Offset from the start of the table to the ﬁrst node
Reserved 8 40 Reserved, must be zero
Node Stucture[n] — 48 A list of Node structures
After the Creator Revision , the remainder of the VIOT table is a list of Node Count nodes, each describing either
endpoints or translation devices. The ﬁrst Node Structure is located Node Offset bytes from the beginning of the table.
Each node has a Type andLength ﬁeld followed by a varying number of additional ﬁelds, deﬁned by the Type of the
node being described, deﬁned below. The Length ﬁeld deﬁnes the node’s length, and the following node is located
Length bytes from the beginning of the current node. Nodes must be aligned on eight byte boundaries.
Each node identiﬁes one or more devices using either their PCI Handle or their base MMIO (Memory-Mapped I/O)
address. A PCI Handle is a PCI Segment number and a BDF (Bus-Device-Function) with the following layout:
•Bits 15:8 Bus Number
•Bits 7:3 Device Number
•Bits 2:0 Function Number
This identiﬁer corresponds to the one observed by the operating system when parsing the PCI conﬁguration space for
the ﬁrst time after boot.
Endpoint nodes declare an Output Node that corresponds to the offset from the beginning of the table to the node
describing the next translation device that manages these endpoints. They also declare one or more endpoint IDs that
system software uses to identify endpoints when programming the translation device.
5.2.32.2 VIOT Node Structures
Each Node in the VIOT table can be one of the following types.
Table 5.171: VIOT Node Structure Types
Type Description
0 Reserved. Do Not Use.
1 PCI Range Structure
2 MMIO Endpoint Structure
3 virtio-pci IOMMU Structure
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Table 5.171 – continued from previous page
4 virtio-mmio IOMMU Structure
5-0xFF Reserved
5.2.32.3 PCI Range Node Structure
This structure describes a range of PCI endpoints, identiﬁed by their structure and BDF number.
Table 5.172: PCI Range Node Structure format
Field Byte
Type 1 0 1 – PCI Range
Reserved 1 1 Reserved
Length 2 2 Length of this node in bytes (24)
Endpoint Start 4 4 First endpoint ID
PCI Segment Start 2 8 First PCI Segment number in the range
PCI Segment End 2 10 Last PCI Segment number in the range
PCI BDF Start 2 12 First Bus-Device-Function number in the range
PCI BDF End 2 14 Last Bus-Device-Function number in the range
Output Node 2 16 Offset from the start of the table to the next translation element
Reserved 6 18 Reserved, must be zero
The node refers to a PCI endpoint if the endpoint’s segment number is in the range [Segment Start, Segment End]
and its BDF number is in the range [BDF Start, BDF End]. The corresponding endpoint ID is obtained by combining
segment and BDF:
Endpoint ID = ((segment - Segment Start) << 16) + BDF - BDF Start + Endpoint Start
5.2.32.4 Single MMIO Endpoint Node Structure
A single endpoint is identiﬁed by its base MMIO address.
Table 5.173: Single MMIO Endpoint Node Structure format
Field Byte
Type 1 0 2 - MMIO Endpoint
Reserved 1 1 Reserved, must be zero
Endpoint ID 4 4 The endpoint ID
Base Address 8 8 Base MMIO address of the endpoint
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5.2.32.5 virtio-iommu based on virtio-pci Node Structure
A virtio-iommu device can be based on the virtio-pci transport, and identiﬁed by the BDF of the virtio device.
Table 5.174: virtio-iommu based on virtio-pci Node Structure
Field Byte
Type 1 0 3 - virtio-pci IOMMU
Length 2 2 Length of this node in bytes (16)
PCI Segment 2 4 The PCI segment number of the virtio-iommu programming inter-
face as returned by _SEG in the ACPI namespace
PCI BDF Number 2 6 Identiﬁer for the PCI Device
Reserved 8 8 Reserved, must be zero
5.2.32.6 virtio-iommu based on virtio-mmioNode Structure
A virtio-iommu device can be based on the virtio-mmio transport, and identiﬁed by the base address of the virtio
device. Like other virtio-iommu devices, properties of the virtio-iommu are described with an LNRO0005 element in
the ACPI namespace.
Table 5.175: virtio-iommu based on virtio-mmio Node Structure for-
mat
Field Byte
Type 1 0 3 - virtio-mmio IOMMU
Reserved 4 4 Reserved, must be zero
Base Address 8 8 Base MMIO address for the device
5.2.33 Miscellaneous GUIDed Table Entries
This section describes a means by which a platform can expose data through a GUIDed entry through a single well-
known MISC table signature. The MISC table and each GUIDed entry is deﬁned sufﬁciently in this speciﬁcation to
allow for the discovery of the MISC table and walking the GUIDed entries that it may contain. The format of the data
within each GUIDed entry is vendor speciﬁc and deﬁned by the Entry GUID ID.
GUIDs in the MISC table shall meet the following expectations:
1. There is no requirement to register a GUID that’s used in an MISC table entry.

mat
Field Byte
2. Optionally, GUIDs in the MISC table can be registered using the same process are ACPI table signatures.
Table 5.176: Miscellaneous GUIDed Table Entries (MISC) Format
Field Byte
Signature 4 0 “MISC” Signature for the GUIDed Table Entries.
Length 4 4 The length of the table, in bytes, of the entire MISC.
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Table 5.176 – continued from previous page
Revision 1 8 The revision of the structure corresponding to the signature ﬁeld for
this table. For the Miscellaneous GUIDed Table Entries conforming
to this revision of the speciﬁcation, the revision is 1.
Checksum 1 9 The entire table, including the checksum ﬁeld, must add to zero to
be considered valid.
OEM Table ID 8 16 An OEM-supplied string that the OEM uses to identify this particu-
lar data table.
OEM Revision 4 24 An OEM-supplied revision number.
Creator ID 4 28 The Vendor ID of the utility that created this table.
Creator Revision 4 32 The revision of the utility that created this table.
GUIDed Entries – 36 The set of one or more GUIDed Entries.
Table 5.177: GUIDed Entry Format
Field Byte
Entry GUID ID 16 0 This value speciﬁes the format and contents of the GUIDed entry.
Entry Length 4 16 This value speciﬁes the length of the GUIDed entry, in bytes.
Revision 4 20 This value is updated every time the entry format speciﬁed by the
given GUID ID is extended.
Producer ID 4 24 The ACPI Vendor ID (e.g. ‘ABCD’).
Data – 28 The content of this ﬁeld is deﬁned by the Entry GUID ID.
5.2.34 CC Event Log ACPI Table
This section describes the format of the conﬁdential computing (CC) event log ACPI table. A virtual ﬁrmware with
CC capability may set up an ACPI table to pass the CC event log information. The event log created by the virtual
ﬁrmware owner contains the hashes to reconstruct the CC measurement registers.
Table 5.178: CC Event Log ACPI Table
Field Byte
Header
Signature 4 0 ‘CCEL’ Signature
- Length 4 4 Length, in bytes, of the entire table.
- OEMID 6 10 Standard ACPI header
- OEM Table ID 8 16 Standard ACPI header
- OEM Revision 4 24 Standard ACPI header
- Creator ID 4 28 Standard ACPI header
- Creator Revision 4 32 Standard ACPI header
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Table 5.178 – continued from previous page
CC Type 1 36
Conﬁdential computing (CC) type.
0: Reserved
1: AMD SEV
2: Intel TDX
3~0xFF: Reserved
CC Subtype 1 37 Conﬁdential computing (CC) type speciﬁc sub type.
Reserved 2 38 Reserved. Must be 0.
Log Area Minimum Length
(LAML)8 40 Identiﬁes the minimum length (in bytes) of the system’s pre-
boot CC event log area.
Log Area Start Address
(LASA)8 48 Contains the 64-bit-physical address of the start of the sys-
tem’s pre-boot CC event log area in QWORD format. Note:
The log area ranges from address LASA to LASA+(LAML-
1).
5.2.35 Storage Volume Key Location Table
This section describes the format of the conﬁdential computing (CC) storage volume key location ACPI table. In the
CC environment, the storage volume will typically be an encrypted volume. In that case, the virtual ﬁrmware may
need to support quote generation and attestation to be able to fetch a set of storage-volume key(s) from a remote-key
server during boot and pass the key to the guest kernel. Typically, the key is stored in memory, and the information of
the key is passed from virtual ﬁrmware via an ACPI table.
Table 5.179: Storage Volume Key Location Table
Field Byte
Header
Signature 4 0 ‘SKVL’ Signature
Key Count (C) 4 36 The count of key structure
Key Structure 16 * C 40 The key structure
Table 5.180: Storage Volume Key Structure
Field Byte
Key Type 2 0
The type of the key.
0: the main storage volume key.
1~0xFFFF: reserved.
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Table 5.180 – continued from previous page
Key Format 2 2
The format of the key.
0: raw binary.
Key Size 4 4 The size of the key in bytes.
Key Address 8 8 The guest-physical address (GPA) of the key. The address
must be in ACPI-Reserved Memory.
5.3 ACPI Namespace
For all Deﬁnition Blocks, the system maintains a single hierarchical namespace that it uses to refer to objects. All
Deﬁnition Blocks load into the same namespace. Although this allows one Deﬁnition Block to reference objects and
data from another (thus enabling interaction), it also means that OEMs must take care to avoid any naming collisions.
For the most part, since the name space is hierarchical, typically the bulk of a dynamic deﬁnition ﬁle will load into a
different part of the hierarchy. The root of the name space and certain locations where interaction is being designed
are the areas in which extra care must be taken.
A name collision in an attempt to load a Deﬁnition Block is considered fatal. The contents of the namespace changes
only on a load operation.
The namespace is hierarchical in nature, with each name allowing a collection of names “below” it. The following
naming conventions apply to all names:
• All names are a ﬁxed 32 bits.
• The ﬁrst byte of a name is inclusive of: ‘A’-‘Z’, ‘_’, (0x41-0x5A, 0x5F).
• The remaining three bytes of a name are inclusive of: ‘A’-‘Z’, ‘0’-‘9’, ‘_’, (0x41-0x5A, 0x30-0x39, 0x5F).
• By convention, when an ASL compiler pads a name shorter than 4 characters, it is done so with trailing under-
scores (‘_’). See the language deﬁnition for AML NameSeg in the ASL Reference chapter.
• Names beginning with ‘_’ are reserved by this speciﬁcation. Deﬁnition Blocks can only use names beginning
with ‘_’ as deﬁned by this speciﬁcation.
• A name proceeded with ‘' causes the name to refer to the root of the namespace (‘' is not part of the 32-bit
ﬁxed-length name).
• A name proceeded with ‘^’ causes the name to refer to the parent of the current namespace (‘^’ is not part of the
32-bit ﬁxed-length name).
Except for names preceded with a ‘', the current namespace determines where in the namespace hierarchy a name
being created goes and where a name being referenced is found. A name is located by ﬁnding the matching name
in the current namespace, and then in the parent namespace. If the parent namespace does not contain the name, the
search continues recursively upwards until either the name is found or the namespace does not have a parent (the
root of the namespace). This indicates that the name is not found - unless the operation being performed is explicitly
prepared for failure in name resolution, this is considered an error and may cause the system to stop working.
An attempt to access names in the parent of the root will result in the name not being found.
There are two types of namespace paths: an absolute namespace path (that is, one that starts with a ‘' preﬁx), and a
relative namespace path (that is, one that is relative to the current namespace). The namespace search rules discussed
above, only apply to single NameSeg paths, which is a relative namespace path. For those relative name paths that
contain multiple NameSegs or Parent Preﬁxes, ‘^’, the search rules do not apply. If the search rules do not apply to a
relative namespace path, the namespace object is looked up relative to the current namespace. For example:
5.3. ACPI Namespace 256Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ABCD //search rules apply
^ABCD //search rules do notapply
XYZ.ABCD //search rules do notapply
\\XYZ.ABCD //search rules do notapply
All name references use a 32-bit ﬁxed-length name or use a Name Extension preﬁx to concatenate multiple 32-bit
ﬁxed-length name components together. This is useful for referring to the name of an object, such as a control method,
that is not in the scope of the current namespace.
Namepaths are used primarily for two purposes:
• To reference an existing object. In this case, all NameSegs within the Namepath must already exist.
• To create a new object. For example:
Device (XYZ.ABCD) {...}
OperationRegion (\XYZ.ABCD, SystemMemory, 0, 0x200)
Each of these declarations is intended to create a new object with the name ABCD according the following rules:
• Object XYZ must already exist for the ABCD object to be created
• If XYZ does not exist, that will cause a fatal error

In general, it is only the ﬁnal Nameseg that will be used as the name of the new object. If any other Nameseg along
the Namepath does not exist, it is a fatal error. In this sense, the Namepath is similar to a ﬁle pathname in a ﬁlesystem
consisting of some number of existing directories followed by a ﬁnal ﬁlename.
The ﬁgure below shows a sample of the ACPI namespace after a Differentiated Deﬁnition Block has been loaded.
Fig. 5.16: Example ACPI NameSpace
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Care must be taken when accessing namespace objects using a relative single segment name because of the namespace
search rules. An attempt to access a relative object recurses toward the root until the object is found or the root
is encountered. This can cause unintentional results. For example, using the namespace described in Figure 5.5,
attempting to access a _CRS named object from within the \_SB_.PCI0.IDE0 will have different results depending
on if an absolute or relative path name is used. If an absolute pathname is speciﬁed (_SB_.PCI0.IDE0._CRS) an
error will result since the object does not exist. Access using a single segment name (_CRS) will actually access the
\_SB_.PCI0._CRS object. Notice that the access will occur successfully with no errors.
5.3.1 Predeﬁned Root Namespaces
The following namespaces are deﬁned under the namespace root.
Table 5.181: Namespaces Deﬁned Under the Namespace Root
\_GPE General events in GPE register block.
\_PR ACPI 1.0 Processor Namespace. ACPI 1.0 requires all Processor objects to be deﬁned
under this namespace. ACPI 2.0 and later allow Processor object deﬁnitions under the
\_SB namespace. Platforms may maintain the \_PR namespace for compatibility with
ACPI 1.0 operating systems, but it is otherwise deprecated. see the compatibility note
inProcessor Local x2APIC Structure . An ACPI-compatible namespace may deﬁne
Processor objects in either the \_SB or \_PR scope but not both. For more information
about deﬁning Processor objects, see Processor Conﬁguration and Control.
\_SB All Device/Bus Objects are deﬁned under this namespace.
\_SI System indicator objects are deﬁned under this namespace. For more information
about deﬁning system indicators, see \_SI System Indicators.
\_TZ ACPI 1.0 Thermal Zone namespace. ACPI 1.0 requires all Thermal Zone objects
to be deﬁned under this namespace. Thermal Zone object deﬁnitions may now be
deﬁned under the \_SB namespace. ACPI-compatible systems may maintain the \_TZ
namespace for compatibility with ACPI 1.0 operating systems. An ACPI-compatible
namespace may deﬁne Thermal Zone objects in either the \_SB or \_TZ scope but
not both. For more information about deﬁning Thermal Zone objects, see Thermal
Management.
5.3.2 Objects
All objects, except locals, have a global scope. Local data objects have a per-invocation scope and lifetime and are
used to process the current invocation from beginning to end.
The contents of objects vary greatly. Nevertheless, most objects refer to data variables of any supported data type, a
control method, or system software-provided functions.
Objects may contain a revision ﬁeld. Successive ACPI speciﬁcations deﬁne object revisions so that they are backwards
compatible with OSPM implementations that support previous speciﬁcations / object revisions. New object ﬁelds are
added at the end of previous object deﬁnitions. OSPM interprets objects according to the revision number it supports
including all earlier revisions. As such, OSPM expects that an object’s length can be greater than or equal to the length
of the known object revision. When evaluating objects with revision numbers greater than that known by OSPM,
OSPM ignores internal object ﬁelds values that are beyond the deﬁned object ﬁeld range for the known revision.
5.3. ACPI Namespace 258Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.4 Deﬁnition Block Encoding
This section speciﬁes the encoding used in a Deﬁnition Block to deﬁne names (load time only), objects, and packages.
5.4.1 AML Encoding
The Deﬁnition Block is encoded as a stream from beginning to end. The lead byte in the stream comes from the
AML encoding tables shown in ACPI Source Language (ASL) Reference and signiﬁes how to interpret some number
of following bytes, where each following byte can in turn signify how to interpret some number of following bytes.
For a full speciﬁcation of the AML encoding, see ACPI Source Language (ASL) Reference
Within the stream there are two levels of data being deﬁned. One is the packaging and object declarations (load time),
and the other is an object reference (package contents/run-time).
All encodings are such that the lead byte of an encoding signiﬁes the type of declaration or reference being made. The
type either has an implicit or explicit length in the stream. All explicit length declarations take the form shown below,
where PkgLength is the length of the inclusive length of the data for the operation.
Fig. 5.17: AML Encoding
Encodings of implicit length objects either have ﬁxed length encodings or allow for nested encodings that, at some
point, either result in an explicit or implicit ﬁxed length.
The PkgLength is encoded as a series of 1 to 4 bytes in the stream with the most signiﬁcant two bits of byte zero,
indicating how many following bytes are in the PkgLength encoding. The next two bits are only used in one-byte
encodings, which allows for one-byte encodings on a length up to 0x3F. Longer encodings, which do not use these
two bits, have a maximum length of the following: two-byte encodings of 0x0FFF, three-byte encodings of 0x0FFFFF,
and four-byte length encodings of 0x0FFFFFFFF.
It is fatal for a package length to not fall on a logical boundary. For example, if a package is contained in another
package, then by deﬁnition its length must be contained within the outer package, and similarly for a datum of implicit
length.
5.4.2 Deﬁnition Block Loading
At some point, the system software decides to “load” a Deﬁnition Block. Loading is accomplished when the system
makes a pass over the data and populates the ACPI namespace and initializes objects accordingly. The namespace for
which population occurs is either from the current namespace location, as deﬁned by all nested packages or from the
root if the name is preceded with ‘'.
The ﬁrst object present in a Deﬁnition Block must be a named control method. This is the Deﬁnition Block’s initial-
ization control.
Packages are objects that contain an ordered reference to one or more objects. A package can also be considered a
vertex of an array, and any object contained within a package can be another package. This permits multidimensional
arrays of ﬁxed or dynamic depths and vertices.
Unnamed objects are used to populate the contents of named objects. Unnamed objects cannot be created in the “root.”
Unnamed objects can be used as arguments in control methods.
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Control method execution may generate errors when creating objects. This can occur if a Method that creates named
objects blocks and is reentered while blocked. This will happen because all named objects have an absolute path. This
is true even if the object name speciﬁed is relative. For example, the following ASL code segments are functionally
identical.
(1)
Method (DEAD)
{
Scope (\_SB_.FOO)
{
Name (BAR,0x1234) // Run time definition
}
}
(2)
Scope (\_SB_)
{
Name (\_SB_. FOO.BAR,) // Load time definition
}
Notice that in the above example the execution of the DEAD method will always fail because the object
\_SB_.FOO.BAR is created at load time.
The term of “Deﬁnition Block level” is used to refer to the AML byte streams that are not contained in any control
method. Such AML byte streams can appear in the “root” scope or in the scopes created/opened by the “Device,
PowerResource, Processor, Scope and ThermalZone” operators. Please refer to “ ASL Operator Reference , ASL
Operator Reference”for detailed descriptions.
Not only the named objects, but all term objects (mathematical, logical, and conditional expressions, etc., see “ Term
Objects Encoding , Term Object Encoding”) are allowed at the Deﬁnition Block level. Allowing such executable
AML opcodes at the Deﬁnition Block level allows BIOS writers to deﬁne dynamic object lists according to the system
settings. For example:
DefinitionBlock ("DSDT.aml", "DSDT", 2, "OEM", "FOOBOOK", 0x1000)
{
...
If (CFG1 () == 1))
{
...
Scope (_SB.PCI0.XHC.RHUB)
{
...
If (CFG2 () == 1)
{
...
Device (HS11)
{
...
If (CFG3 () == 1)
{
...
Device (CAM0)
{
...
}
...
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}
...
}
...
}
...
}
...
}
...
}
The interpretation of the deﬁnition block during the deﬁnition block loading is similar to the interpretation of the

{
...
{
...
{
...
{
...
{
...
{
...
{
...
}
...
}
...
}
...
}
...
}
...
}
...
}
control method during the control method execution.
5.5 Control Methods and the ACPI Source Language (ASL)
OEMs and platform ﬁrmware vendors write deﬁnition blocks using the ACPI Source Language (ASL) and use a trans-
lator to produce the byte stream encoding described in Deﬁnition Block Encoding . For example, the ASL statements
that produce the example byte stream shown in that earlier section are shown in the following ASL example. For a full
speciﬁcation of the ASL statements, see ACPI Source Language (ASL) Reference .
DefinitionBlock (
"forbook.aml", // Output Filename
"DSDT", // Signature
0x02, // DSDT Compliance Revision
"OEM", // OEMID
"forbook", // TABLE ID
0x1000 // OEM Revision
)
{ // start of definition block
OperationRegion(\GIO, SystemIO, 0x125, 0x1)
Field(\GIO, ByteAcc, NoLock, Preserve)
{
CT01, 1,
}
Scope(\_SB)
{ // start of scope
Device(PCI0)
{ // start of device
PowerResource(FET0, 0, 0)
{ // start of pwr
Method (_ON)
{
CT01 = Ones // assertpower
Sleep (30) // wait 30ms
}
Method (_OFF)
{
CT01 = Zero // assertreset #
}
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Method (_STA)
{
Return (CT01)
}
} // end of power
} // end of device
} // end of scope
} // end of definition block
5.5.1 ASL Statements
ASL is principally a declarative language. ASL statements declare objects. Each object has three parts, two of which
can be null:
Object := ObjectType FixedList VariableList
FixedList refers to a list of known length that supplies data that all instances of a given ObjectType must have. It is
written as (a, b, c,), where the number of arguments depends on the speciﬁc ObjectType, and some elements can be
nested objects, that is (a, b, (q, r, s, t), d). Arguments to a FixedList can have default values, in which case they can be
skipped. Some ObjectTypes can have a null FixedList.
VariableList refers to a list, not of predetermined length, of child objects that help deﬁne the parent. It is written as {x,
y, z, aa, bb, cc}, where any argument can be a nested object. ObjectType determines what terms are legal elements of
the VariableList. Some ObjectTypes can have a null variable list.
For a detailed speciﬁcation of the ASL language, see ACPI Source Language (ASL) Reference
5.5.2 Control Method Execution
OSPM evaluates control method objects as necessary to either interrogate or adjust the system-level hardware state.
This is called an invocation.
A control method can use other internal, or well deﬁned, control methods to accomplish the task at hand, which
can include deﬁned control methods provided by the operating software. Control Methods can reference any objects
anywhere in the Namespace. Interpretation of a Control Method is not preemptive, but it can block. When a control
method does block, OSPM can initiate or continue the execution of a different control method. A control method can
only assume that access to global objects is exclusive for any period the control method does not block.
Global objects are those NameSpace objects created at table load time.
5.5.2.1 Arguments
Up to seven arguments can be passed to a control method. Each argument is an object that in turn could be a “package”
style object that refers to other objects. Access to the argument objects is provided via the ASL ArgTerm (ArgX)
language elements. The number of arguments passed to any control method is ﬁxed and is deﬁned when the control
method package is created.
Method arguments can take one of the following forms:
• An ACPI name or namepath that refers to a named object. This includes the LocalX and ArgX names. In this
case, the object associated with the name is passed as the argument.
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• An ACPI name or namepath that refers to another control method. In this case, the method is invoked and the
return value of the method is passed as the argument. A fatal error occurs if no object is returned from the
method. If the object is not used after the method invocation it is automatically deleted.
• A valid ASL expression. In the case, the expression is evaluated and the object that results from this evaluation
is passed as the argument. If this object is not used after the method invocation it is automatically deleted.
5.5.2.2 Method Calling Convention
The calling convention for control methods can best be described as call-by-reference-constant. In this convention,
objects passed as arguments are passed by “reference”, meaning that they are not copied to new objects as they are
passed to the called control method (A calling convention that copies objects or object wrappers during a call is known
as call-by-value or call-by-copy).
This call-by-reference-constant convention allows internal objects to be shared across each method invocation, there-
fore reducing the number of object copies that must be performed as well as the number of buffers that must be copied.
This calling convention is appropriate to the low-level nature of the ACPI subsystem within the kernel of the host op-
erating system where non-paged dynamic memory is typically at a premium. The ASL programmer must be aware of
the calling convention and the related side effects.
However, unlike a pure call-by-reference convention, the ability of the called control method to modify arguments
is extremely limited. This reduces aliasing issues such as when a called method unexpectedly modiﬁes a object or
variable that has been passed as an argument by the caller. In effect, the arguments that are passed to control methods
are passed as constants that cannot be modiﬁed except under speciﬁc controlled circumstances.
Generally, the objects passed to a control method via the ArgX terms cannot be directly written or modiﬁed by the
called method. In other words, when an ArgX term is used as a target operand in an ASL statement, the existing ArgX
object is not modiﬁed. Instead, the new object replaces the existing object and the ArgX term effectively becomes a
LocalX term.
The only exception to the read-only argument rule is if an ArgX term contains an Object Reference created via the
RefOf ASL operator. In this case, the use of the ArgX term as a target operand will cause any existing object stored at
the ACPI name referred to by the RefOf operation to be overwritten.
In some limited cases, a new, writable object may be created that will allow a control method to change the value of
an ArgX object. These cases are limited to Buffer and Package objects where the “value” of the object is represented
indirectly. For Buffers, a writable Index or Field can be created that refers to the original buffer data and will allow the
called method to read or modify the data. For Packages, a writable Index can be created to allow the called method to
modify the contents of individual elements of the Package.
5.5.2.3 Local Variables and Locally Created Data Objects
Control methods can access up to eight local data objects. Access to the local data objects have shorthand encodings.
On initial control method execution, the local data objects are NULL. Access to local objects is via the ASL LocalTerm
language elements.
Upon control method execution completion, one object can be returned that can be used as the result of the execution
of the method. The “caller” must either use the result or save it to a different object if it wants to preserve it. See the
description of the Return ASL operator for additional details
NameSpace objects created within the scope of a method are dynamic. They exist only for the duration of the method
execution. They are created when speciﬁed by the code and are destroyed on exit. A method may create dynamic
objects outside of the current scope in the NameSpace using the scope operator or using full path names. These
objects will still be destroyed on method exit. Objects created at load time outside of the scope of the method are
static. For example:
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Scope (\XYZ)
{
Name (BAR, 5) // Creates \\XYZ.BAR
Method (FOO, 1)
{
CREG = BAR // same effect asCREG = \XYZ.BAR
Name (BAR, 7) // Creates \\XYZ.FOO.BAR
DREG = BAR // same effect asDREG = \XYZ.FOO.BAR
Name (\XYZ.FOOB, 3) // Creates \\XYZ.FOOB
} // end method
} // end scope
The object \XYZ.BAR is a static object created when the table that contains the above ASL is loaded. The object
\XYZ.FOO.BAR is a dynamic object that is created when the Name (BAR, 7) statement in the FOO method is exe-
cuted. The object \XYZ.FOOB is a dynamic object created by the \XYZ.FOO method when the Name (XYZ.FOOB,
3) statement is executed. Notice that the \XYZ.FOOB object is destroyed after the \XYZ.FOO method exits.
5.5.2.4 Access to Operation Regions
5.5.2.4.1 Operation Regions

{
{
Control Methods read and write data to locations in address spaces (for example, System memory and System I/O) by
using the Field operator (see Declare Field Objects) to declare a data element within an entity known as an “Operation
Region” and then performing accesses using the data element name. An Operation Region is a speciﬁc region of
operation within an address space that is declared as a subset of the entire address space using a starting address
(offset) and a length (see OperationRegion (Declare Operation Region) . Control methods must have exclusive access
to any address accessed via ﬁelds declared in Operation Regions. Control methods may not directly access any
other hardware registers, including the ACPI-deﬁned register blocks. Some of the ACPI registers, in the deﬁned
ACPI registers blocks, are maintained on behalf of control method execution. For example, the GPEx_BLK is not
directly accessed by a control method but is used to provide an extensible interrupt handling model for control method
invocation.
• Accessing an OpRegion may block, even if the OpRegion is not protected by a mutex. For example, because of
the slow nature of the embedded controller, an embedded controller OpRegion ﬁeld access may block.
The following table deﬁnes Operation Region spaces.
Table 5.182: Operation Region Address Space Identiﬁers
Value Name (RegionSpace Keyword) Reference
0 SystemMemory
1 SystemIO
2 PCI_Conﬁg
3 EmbeddedControl See ACPI Embedded Controller Interface
Speciﬁcation
4 SMBus See ACPI System Management Bus Inter-
face Speciﬁcation
5 SystemCMOS See CMOS Protocols
6 PciBarTarget See PCI Device BAR Target Protocols
7 IPMI See Declaring IPMI Operation Regions
8 GeneralPurposeIO See Declaring GeneralPurposeIO Operation
Regions
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Table 5.182 – continued from previous page
9 GenericSerialBus See Declaring GenericSerialBus Operation
Regions
0x0A PCC See Declaring PCC Operation Regions
0x0B PlatformRtMechanism Operation Region used by the Platform
Runtime Mechanism Table. See Links to
ACPI-Related Documents (https://ueﬁ.org/
acpi) under the heading “Platform Runtime
Mechanism Table”.
0x0C-0x7E Reserved
0x07F FFixedHW (FFH) See Declaring Functional Fixed Hard-
ware (FFH) Operation Regions (Section
5.5.2.4.2).
0x80 to 0xFF OEM deﬁned
5.5.2.4.2 Declaring Functional Fixed Hardware (FFH) Operation Regions
The syntax for declaring and using the Functional Fixed Hardware (FFH) Operation Region is architecture speciﬁc.
Please refer to architecture speciﬁc documentation for the deﬁnition. For ARM FFixedHW Operation Region deﬁni-
tion, see Links to ACPI-Related Documents (https://ueﬁ.org/acpi) under the heading “ARM FFH Speciﬁcation”.
The use of functional ﬁxed hardware carries with it a reliance on OS speciﬁc software that must be considered.
OEMs should consult OS vendors to ensure that speciﬁc functional ﬁxed hardware interfaces are supported by speciﬁc
operating systems. The OS and the platform can handshake on support for the FFH Operation Regions using the _OSC
method as described in Platform-Wide OSPM Capabilities (Section 6.2.11.2).
5.5.2.4.3 CMOS Protocols
This section describes how CMOS battery-backed non-volatile memory can be accessed from ASL. Most computers
contain an RTC/CMOS device that can be represented as a linear array of bytes of non-volatile memory. There is
a standard mechanism for accessing the ﬁrst 64 bytes of non-volatile RAM in devices that are compatible with the
Motorola RTC/CMOS device used in the original IBM PC/AT. Existing RTC/CMOS devices typically contain more
than 64 bytes of non-volatile RAM, and no standard mechanism exists for access to this additional storage area. To
provide access to all of the non-volatile memory in these devices from AML, PnP IDs exist for each type of extension.
These are PNP0B00, PNP0B01, and PNP0B02. The speciﬁc devices that these PnP IDs support are described in
PC/AT RTC/CMOS Devices , along with ﬁeld deﬁnition ASL example code. The drivers corresponding to these device
handle operation region accesses to the SystemCMOS operation region for their respective device types.
All bytes of CMOS that are related to the current time, day, date, month, year and century are read-only.
5.5.2.4.4 PCI Device BAR Target Protocols
This section describes how PCI devices’ control registers can be accessed from ASL. PCI devices each have an address
space associated with them called the Conﬁguration Space. At offset 0x10 through offset 0x27, there are as many as
six Base Address Registers, (BARs). These BARs contain the base address of a series of control registers (in I/O or
Memory space) for the PCI device. Since a Plug and Play OS may change the values of these BARs at any time, ASL
cannot read and write from these deterministically using I/O or Memory operation regions. Furthermore, a Plug and
Play OS will automatically assign ownership of the I/O and Memory regions associated with these BARs to a device
driver associated with the PCI device. An ACPI OS (which must also be a Plug and Play operating system) will not
allow ASL to read and write regions that are owned by native device drivers.
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If a platform uses a PCI BAR Target operation region, an ACPI OS will not load a native device driver for the
associated PCI function. For example, if any of the BARs in a PCI function are associated with a PCI BAR Target
operation region, then the OS will assume that the PCI function is to be entirely under the control of the ACPI system
ﬁrmware. No driver will be loaded. Thus, a PCI function can be used as a platform controller for some task (hot-plug
PCI, and so on) that the ACPI system ﬁrmware performs.
5.5.2.4.4.1 Declaring a PCI BAR Target Operation Region
PCI BARs contain the base address of an I/O or Memory region that a PCI device’s control registers lie within. Each
BAR implements a protocol for determining whether those control registers are within I/O or Memory space and how
much address space the PCI device decodes. (See the PCI Speciﬁcation for more details.)
PCI BAR Target operation regions are declared by providing the offset of the BAR within the PCI device’s PCI
conﬁguration space. The BAR determines whether the actual access to the device occurs through an I/O or Memory
cycle, not by the declaration of the operation region. The length of the region is similarly implied.
In the term OperationRegion(PBAR, PciBarTarget, 0x10, 0x4), the offset is the offset of the BAR within the conﬁgu-
ration space of the device. This would be an example of an operation region that uses the ﬁrst BAR in the device.
5.5.2.4.4.2 PCI Header Types and PCI BAR Target Operation Regions
PCI BAR Target operation regions may only be declared in the scope of PCI devices that have a PCI Header Type of
0. PCI devices with other header types are bridges. The control of PCI bridges is beyond the scope of ASL.
5.5.2.4.5 Declaring IPMI Operation Regions
This section describes the Intelligent Platform Management Interface (IPMI) address space and the use of this address
space to communicate with the Baseboard Management Controller (BMC) hardware from AML.
Similar to SMBus, IPMI operation regions are command based, where each offset within an IPMI address space
represent an IPMI command and response pair. Given this uniqueness, IPMI operation regions include restrictions
on their ﬁeld deﬁnitions and require the use of an IPMI-speciﬁc data buffer for all transactions. The IPMI interface
presented in this section is intended for use with any hardware implementation compatible with the IPMI speciﬁcation,
regardless of the system interface type.
Support of the IPMI generic address space by ACPI-compatible operating systems is optional, and is contingent on
the existence of an ACPI IPMI device, i.e. a device with the “IPI0001” plug and play ID. If present, OSPM should
load the necessary driver software based on the system interface type as speciﬁed by the _IFT (IPMI Interface Type)
control method under the device, and register handlers for accesses into the IPMI operation region space.
For more information, refer to the IPMI speciﬁcation.
Each IPMI operation region deﬁnition identiﬁes a single IPMI network function. Operation regions are deﬁned only
for those IPMI network functions that need to be accessed from AML. As with other regions, IPMI operation regions
are only accessible via the Field term (see Declaring IPMI Fields ).
This interface models each IPMI network function as having a 256-byte linear address range. Each byte offset within
this range corresponds to a single command value (for example, byte offset 0xC1 equates to command value 0xC1),
with a maximum of 256 command values. By doing this, IPMI address spaces appear linear and can be processed in a
manner similar to the other address space types.

The syntax for the OperationRegion term (from OperationRegion (Declare Operation Region) ) is described below:
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OperationRegion (
RegionName, // NameString
RegionSpace, // RegionSpaceKeyword
Offset, // TermArg=>Integer
Length // TermArg=>Integer
)
Where:
• RegionName speciﬁes a name for this IPMI network function (for example, “POWR”).
• RegionSpace must be set to IPMI (operation region type value 0x07).
• Offset is a word-sized value specifying the network function and initial command value offset for the target
device. The network function address is stored in the high byte and the command value offset is stored in the
low byte. For example, the value 0x3000 would be used for a device with the network function of 0x06, and an
initial command value offset of zero (0).
• Length is set to the 0x100 (256), representing the maximum number of possible command values, for regions
with an initial command value offset of zero (0). The difference of these two values is used for regions with
non-zero offsets. For example, a region with an Offset value of 0x3010 would have a corresponding Length of
0xF0 (0x100 minus 0x10).
For example, a Baseboard Management Controller will support power metering capabilities at the network function
0x30, and IPMI commands to query the BMC device information at the network function 0x06.
The following ASL code shows the use of the OperationRegion term to describe these IPMI functions:
Device (IPMI)
{
Name (_HID, "IPI0001") // IPMI device
Name (_IFT, 0x1) // KCS system interface type
OperationRegion (DEVC, IPMI, 0x0600, 0x100) // Device info network function
OperationRegion (POWR, IPMI, 0x3000, 0x100) // Power network function
}
Notice that these operation regions in this example are deﬁned within the immediate context of the ‘owning’ IPMI
device. This ensures the correct operation region handler will be used, based on the value returned by the _IFT object.
Each deﬁnition corresponds to a separate network function, and happens to use an initial command value offset of zero
(0).
5.5.2.4.5.1 Declaring IPMI Fields
As with other regions, IPMI operation regions are only accessible via the Field term. Each ﬁeld element is assigned a
unique command value and represents a virtual command for the targeted network function.
The syntax for the Field term (from Event (Declare Event Synchronization Object) ) is described below:
Field(
RegionName, // NameString=>OperationRegion
AccessType, // AccessTypeKeyword - BufferAcc
LockRule, // LockRuleKeyword
UpdateRule // UpdateRuleKeyword - ignored
) {FieldUnitList}
Where:
• RegionName speciﬁes the operation region name previously deﬁned for the network function.
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• AccessType must be set to BufferAcc. This indicates that access to ﬁeld elements will be done using a region-
speciﬁc data buffer. For this access type, the ﬁeld handler is not aware of the data buffer’s contents which may
be of any size. When a ﬁeld of this type is used as the source argument in an operation it simply evaluates
to a buffer. When used as the destination, however, the buffer is passed bi-directionally to allow data to be
returned from write operations. The modiﬁed buffer then becomes the response message of that command. This
is slightly different than the normal case in which the execution result is the same as the value written to the
destination. Note that the source is never changed, since it only represents a virtual register for a particular IPMI
command.
• LockRule indicates if access to this operation region requires acquisition of the Global Lock for synchronization.
This ﬁeld should be set to Lock on system with ﬁrmware that may access the BMC via IPMI, and NoLock
otherwise.
• UpdateRule is not applicable to IPMI operation regions since each virtual register is accessed in its entirety.
This ﬁeld is ignored for all IPMI ﬁeld deﬁnitions.
IPMI operation regions require that all ﬁeld elements be declared at command value granularity. This means that each
virtual register cannot be broken down to its individual bits within the ﬁeld deﬁnition.
Access to sub-portions of virtual registers can be done only outside of the ﬁeld deﬁnition. This limitation is im-
posed both to simplify the IPMI interface and to maintain consistency with the physical model deﬁned by the IPMI
Since the system interface used for IPMI communication is determined by the _IFT object under the IPMI device,
there is no need for using of the AccessAs term within the ﬁeld deﬁnition. In fact its usage will be ignored by the
operation handler.
For example, the register at command value 0xC1 for the power meter network function might represent the command
to set a BMC enforced power limit, while the register at command value 0xC2 for the same network function might
represent the current conﬁgured power limit. At the same time, the register at command value 0xC8 might represent
the latest power meter measurement.
The following ASL code shows the use of the OperationRegion, Field, and Offset terms to represent these virtual
registers:
OperationRegion(POWR, IPMI, 0x3000, 0x100) // Power network function
Field(POWR, BufferAcc, NoLock, Preserve)
{
Offset(0xC1), // Skip to command value 0xC1
SPWL, 8, // Set power limit [command value 0xC1]
GPWL, 8, // Get power limit [command value 0xC2]
Offset(0xC8), // Skip to command value 0xC8
GPMM, 8 // Get power meter measurement [command value 0xC8]
}
Notice that command values are equivalent to the ﬁeld element’s byte offset (for example, SPWL=0xC1,
GPWL=0xC2, GPMM=0xC8).
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5.5.2.4.5.2 Declaring and Using IPMI Request and Response Buffer
Since each virtual register in the IPMI operation region represents an individual IPMI command, and the operation
relies on use of bi-directional buffer, a common buffer structure is required to represent the request and response
messages. The use of a data buffer for IPMI transactions allows AML to receive status and data length values.
The IPMI data buffer is deﬁned as a ﬁxed-length 66-byte buffer that, if represented using a ‘C’-styled declaration,
would be modeled as follows:
{
BYTE Status; // Byte 0 of the data buffer
BYTE Length; // Byte 1 of the data buffer
BYTE[64] Data; // Bytes 2 through 65 of the data buffer
}
Where:
• Status (byte 0) indicates the status code of a given IPMI command. See IPMI Status Code for more information.
• Length (byte 1) speciﬁes the number of bytes of valid data that exists in the data buffer. Valid Length values
are 0 through 64. Before the operation is carried out, this value represents the length of the request data buffer.
Afterwards, this value represents the length of the result response data buffer.
• Data (bytes 65-2) represents a 64-byte buffer, and is the location where actual data is stored. Before the operation
is carried out, this represents the actual request message payload. Afterwards, this represents the response
message payload as returned by the IPMI command.
For example, the following ASL shows the use of the IPMI data buffer to carry out a command for a power function.
This code is based on the example ASL presented in Declaring IPMI Fields which lists the operation region and ﬁeld
deﬁnitions for relevant IPMI power metering commands.
/*Create the IPMI data buffer */
Name(BUFF, Buffer(66){}) // Create IPMI data buffer as BUFF
CreateByteField(BUFF, 0x00, STAT) // STAT = Status (Byte)
CreateByteField(BUFF, 0x01, LENG) // LENG = Length (Byte)
CreateByteField(BUFF, 0x02, MODE) // MODE = Mode (Byte)
CreateByteField(BUFF, 0x03, RESV) // RESV = Reserved (Byte)
LENG = 0x2 // Request message is 2 bytes long
MODE = 0x1 // Set Mode to 1
BUFF = (GPMM = BUFF) // Write the request into the GPMM command,
// then read the results
CreateByteField (BUFF, 0x02, CMPC) // CMPC = Completion code (Byte)
CreateWordField (BUFF, 0x03, APOW) // APOW = Average power measurement (Word)
If ((STAT == 0x0) && (CMPC == 0x0)) // Successful?
{
Return (APOW) // Return the average power measurement
}
Else
{
Return (Ones) // Return invalid
}
Notice the use of the CreateField primitives to access the data buffer’s sub-elements (Status, Length, and Data), where
Data (bytes 65-2) is ‘typecast’ into different ﬁelds (including the result completion code).
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The example above demonstrates the use of the Store() operator and the bi-directional data buffer to invoke the actual
IPMI command represented by the virtual register. The inner Store() writes the request message data buffer to the

{
}
Else
{
}
IPMI operation region handler, and invokes the command. The outer Store() takes the result of that command and
writes it back into the data buffer, this time representing the response message.
5.5.2.4.5.3 IPMI Status Code
Every IPMI command results in a status code returned as the ﬁrst byte of the response message, contained in the
bi-directional data buffer. This status code can indicate success, various errors, and possibly timeout from the IPMI
operation handler. This is necessary because it is possible for certain IPMI commands to take up to 5 seconds to carry
out, and since an AML Store() operation is synchronous by nature, it is essential to make sure the IPMI operation
returns in a timely fashion so as not to block the AML interpreter in the OSPM.
• This status code is different than the IPMI completion code, which is returned as the ﬁrst byte of the response
message in the data buffer payload. The completion code is described in the complete IPMI speciﬁcation.
Table 5.183: IPMI Status Codes
Status
CodeName Description
00h IPMI OK Indicates the command has been successfully completed.
07h IPMI Unknown
FailureIndicates failure because of an unknown IPMI error.
10h IPMI Command
Operation TimeoutIndicates the operation timed out.
5.5.2.4.6 Declaring GeneralPurposeIO Operation Regions
For GeneralPurposeIO Operation Regions, the syntax for the OperationRegion term (from section OperationRegion
(Declare Operation Region) ) is described below:
)
Where:
• RegionName speciﬁes a name for this GeneralPurposeIO region (for example, “GPI1”).
• RegionSpace must be set to GeneralPurposeIO (operation region type value 0x08).
• Offset is ignored for the GeneralPurposeIO RegionSpace.
• Length is the maximum number of GPIO IO pins to be included in the Operation Region, rounded up to the next
byte.
GeneralPurposeIO OpRegions must be declared within the scope of the GPIO controller device being accessed.
5.5. Control Methods and the ACPI Source Language (ASL) 270Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.5.2.4.6.1 Declaring GeneralPurposeIO Fields
As with other regions, GeneralPurposeIO operation regions are only accessible via the Field term. Each ﬁeld element
represents a subset of the length bits declared in the OpRegion declaration. The pins within the OpRegion that are
accessed via a given ﬁeld name are deﬁned by a Connection descriptor. The total number of deﬁned ﬁeld bits following
a connection descriptor must equal the number of pins listed in the descriptor.
The syntax for the Field term (from Field (Declare Field Objects) ) is described below:
Field(
AccessType, // AccessTypeKeyword
Where:
• RegionName speciﬁes the operation region name previously declared.
• AccessType must be set to ByteAcc.
Note that, on HW-reduced ACPI platforms, this ﬁeld must be set to NoLock.
• UpdateRule is not applicable to GeneralPurposeIO operation regions since Preserve is always required. This
ﬁeld is ignored for all GeneralPurposeIO ﬁeld deﬁnitions.
The following ASL code shows the use of the OperationRegion, Field, and Offset terms as they apply to GeneralPur-
poseIO space.
Device(DEVA) //An Arbitrary Device Scope
{
// Other required stuff forthis device
Name (GMOD, ResourceTemplate ()
//An existing GPIO Connection (to be used later)
{
//2 Outputs that define the Power mode of the device
GpioIo (Exclusive, PullDown, , , , " \\_SB.GPI2") {10, 12}
})
} //End DEVA
Device (GPI2) //The OpRegion declaration, andthe \_REG method,
//must be inthe controller's namespace scope
{
//Other required stuff forthe GPIO controller
OperationRegion(GPO2, GeneralPurposeIO, 0, 1)
// Note: length of 1 means region isless than 1 byte (8 pins) long
{
// Track availability of GeneralPurposeIO space
}
}
Device (DEVB) //Access some GPIO Pins from this device scope
//to change the device's power mode
{
//.. Other required stuff forthis device
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Name(_DEP, Package() {" \\_SB.GPI2"}) //OpRegion Dependency hint forOSPM
Field(\_SB.GPI2.GPO2, ByteAcc, NoLock, Preserve)
{
Connection (GMOD), // Re-Use an existing connection (defined elsewhere)
MODE, 2, // Power Mode
Connection (GpioIo(Exclusive, PullUp, , , , " \\_SB.GPI2") {7}),
STAT, 1, // e.g. Status signal from the device
Connection (GpioIo (Exclusive, PullUp, , , , " \\_SB.GPI2") {9}),
RSET, 1 // e.g. Reset signal to the device
}
Method(_PS3)
{
If (1) // Make sure GeneralPurposeIO OpRegion isavailable
{
MODE = 0x03 //Set both MODE bits. Power Mode 3
}
}
} //End DEVB
5.5.2.4.7 Declaring GenericSerialBus Operation Regions
For GenericSerialBus Operation Regions, the syntax for the OperationRegion term (from OperationRegion (Declare
Operation Region) ) is described below:
)
Where:
• RegionName speciﬁes a name for this region (for example, TOP1).
• RegionSpace must be set to GenericSerialBus (operation region type value 0x09).
• Offset speciﬁes the initial command value offset for the target device. For example, the value 0x00 refers to a
command value offset of zero (0). Raw protocols ignore this value.
• Length is set to the 0x100 (256), representing the maximum number of possible command values.
• The Operation Region must be declared within the scope of the Serial Bus controller device.
The following ASL code shows the use of the OperationRegion, Field, and Offset terms as they apply to SPB space.
Scope(\_SB.I2C)
{
Name (SDB0, ResourceTemplate()
{
I2CSerialBusV2(0x4a,,100000,,"
\\_SB.I2C",,,,,RawDataBuffer(){1,2,3,4,5,6})
})
OperationRegion(TOP1, GenericSerialBus, 0x00, 0x100)
// GenericSerialBus device at command offset 0x00
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Field(TOP1, BufferAcc, NoLock, Preserve)
{
Connection(SDB0),
// Use the Resource Descriptor defined above
AccessAs(BufferAcc, AttribWord),
// Use the GenericSerialBus Read/Write Word protocol
FLD0, 8, // Virtual register at command value 0.
FLD1, 8 // Virtual register at command value 1.
}
{
Connection(I2CSerialBusV2(0x5a,,100000,,"
\\_SB.I2C",,,,,RawDataBuffer(){1,6})),
AccessAs(BufferAcc, AttribBytes (16)),
FLD2, 8 // Virtual register at command value 0.
}
// Create the GenericSerialBus data buffer
Name(BUFF, Buffer(34){}) // Create GenericSerialBus data buffer asBUFF
CreateWordField(BUFF, 0x02, DATA) // DATA = Data (Word)
}
The Operation Region in this example is deﬁned within the scope of the target controller device, I2C.
GenericSerialBus regions are only accessible via the Field term (see Declare Field Objects). GenericSerialBus proto-
cols are assigned to ﬁeld elements using the AccessAs term (see “ASL Macros”) within the ﬁeld deﬁnition.
Table 5.184: Accsessor Type Values
Accessor Type Value Description
AttribQuick 0x02 Read/Write Quick Protocol
AttribSendReceive 0x04 Send/Receive Byte Protocol
AttribByte 0x06 Read/Write Byte Protocol
AttribWord 0x08 Read/Write Word Protocol
AttribBlock 0x0A Read/Write Block Protocol
AttribBytes 0x0B Read/Write N-Bytes Protocol
AttribProcessCall 0x0C Process Call Protocol
AttribBlockProcessCall 0x0D Write Block-Read Block Process Call Pro-
tocol
AttribRawBytes 0x0E Raw Read/Write N-Bytes Protocol
AttribRawProcessBytes 0x0F Raw Process Call Protocol
5.5. Control Methods and the ACPI Source Language (ASL) 273Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.5.2.4.7.1 Declaring GenericSerialBus Fields
As with other regions, GenericSerialBus operation regions are only accessible via the Field term. Each ﬁeld element
is assigned a unique command value and represents a virtual register on the targeted GenericSerialBus device.
The syntax for the Field term (see Section 19.6.47) is described below:
Field(
LockRule, // LockRuleKeyword - ignored forHardware-reduced ACPI platforms
Where:
• RegionName speciﬁes the operation region name previously deﬁned for the device.

Field(
Where:
returned from write operations. The modiﬁed buffer then becomes the execution result of that operation. This
destination. Note that the source is never changed, since it could be a read only object (see Declaring and Using
a GenericSerialBus Data Buffer ).
This ﬁeld should be set to Lock on system with ﬁrmware that may access the GenericSerialBus, and NoLock
otherwise. On Hardware-reduced ACPI platforms, there is not a global lock so this parameter is ignored.
• UpdateRule is not applicable to GenericSerialBus operation regions since each virtual register is accessed in its
entirety. This ﬁeld is ignored for all GenericSerialBus ﬁeld deﬁnitions.
GenericSerialBus operation regions require that all ﬁeld elements be declared at command value granularity. This
means that each virtual register cannot be broken down to its individual bits within the ﬁeld deﬁnition.
Access to sub-portions of virtual registers can be done only outside of the ﬁeld deﬁnition. This limitation is imposed
to simplify the GenericSerialBus interface.
GenericSerialBus protocols are assigned to ﬁeld elements using the AccessAs term within the ﬁeld deﬁnition. The
syntax for this term (from ASL Root and Secondary Terms ) is described below:
AccessAs(
AccessType, //AccessTypeKeyword
AccessAttribute //Nothing \| ByteConst \| AccessAttribKeyword
)
Where:
• AccessType must be set to BufferAcc.
• AccessAttribute indicates the GenericSerialBus protocol to assign to command values that follow this term.
See:ref: using-the-genericserialbus-protocols for a listing of the GenericSerialBus protocols.
An AccessAs term must appear in a ﬁeld deﬁnition to set the initial GenericSerialBus protocol for the ﬁeld elements
that follow. A maximum of one GenericSerialBus protocol may be deﬁned for each ﬁeld element. Devices supporting
multiple protocols for a single command value can be modeled by specifying multiple ﬁeld elements with the same
offset (command value), where each ﬁeld element is preceded by an AccessAs term specifying an alternate protocol.
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For GenericSerialBus operation regions, connection attributes must be deﬁned for each set of ﬁeld elements. Gener-
icSerialBus resources are assigned to ﬁeld elements using the Connection term within the ﬁeld deﬁnition. The syntax
for this term (from Connection (Declare Field Connection Attributes) “Connection (Declare Field Connection At-
tributes)”) is described below:
Connection (ConnectionResourceObj)
Where:
• ConnectionResourceObj points to a Serial Bus Resource Connection Descriptor (see GenericSerialBus Con-
nection Descriptors for valid types), or a named object that speciﬁes a buffer ﬁeld containing the connection
resource information.
Each Field deﬁnition references the initial command offset speciﬁed in the operation region deﬁnition. The offset is
iterated for each subsequent ﬁeld element deﬁned in that respective Field. If a new connection is described in the same
Field deﬁnition, the offset will not be returned to its initial value and a new Field must be deﬁned to inherit the initial
command value offset from the operation region deﬁnition. The following example illustrates this point.
OperationRegion (TOP1, GenericSerialBus, 0x00, 0x100) //Initial offset is0
Field (TOP1, BufferAcc, NoLock, Preserve)
{
Connection (I2CSerialBusV2 (0x5a,,100000,," \\_SB.I2C",,,,,RawDataBuffer(){1,6})),
Offset (0x0),
AccessAs(BufferAcc, AttribBytes (4)),
TFK1, 8, //TFK1 at command value offset 0
TFK2, 8, //TFK2 at command value offset 1
Connection(I2CSerialBusV2(0x5c,,100000,," \\_SB.I2C",,,,,RawDataBuffer(){3,1})),
AccessAs(BufferAcc, AttribBytes (12)),
TS1, 8 //TS1 at command value offset 2
}
{
Connection(I2CSerialBusV2(0x5b,,100000,," \\_SB.I2C",,,,,RawDataBuffer(){2,9})),
AccessAs(BufferAcc, AttribByte),
TM1, 8 //TM1 at command value offset 0
}
5.5.2.4.7.2 Declaring and Using a GenericSerialBus Data Buffer
The use of a data buffer for GenericSerialBus transactions allows AML to receive status and data length values, as
well as making it possible to implement the Process Call protocol. The BufferAcc access type is used to indicate to
the ﬁeld handler that a region-speciﬁc data buffer will be used.
For GenericSerialBus operation regions, this data buffer is deﬁned as an arbitrary length buffer that, if represented
using a ‘C’-styled declaration, would be modeled as follows:
{
BYTE[x-1] Data; // Bytes 2-x of the arbitrary length data buffer,
} // where x isthe last index of the overall buffer
Where:
• Status (byte 0) indicates the status code of a given GenericSerialBus transaction.
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• Length (byte 1) speciﬁes the number of bytes of valid data that exists in the data buffer (bytes 2-x). Use of this
ﬁeld is only deﬁned for the Read/Write Block protocol. For other protocols–where the data length is implied by
the protocol–this ﬁeld is reserved. Since this ﬁeld is one byte, the maximum length of the data buffer is 255.
• Data (bytes 2-x) represents an arbitrary length buffer, and is the location where actual data is stored.
For example, the following ASL shows the use of the GenericSerialBus data buffer for performing transactions to a
Smart Battery device.
/*Create the GenericSerialBus data buffer */
Name (BUFF, Buffer (34){}) // Create GenericSerialBus data buffer as BUFF
CreateByteField (BUFF, 0x00, STAT) // STAT = Status (Byte)
CreateByteField (BUFF, 0x01, LEN) // LEN = Length (Byte)
CreateWordField (BUFF, 0x02, DATW) // DATW = Data (Word - Bytes 2 & 3)
CreateField (BUFF, 0x10, 256, DBUF) // DBUF = Data (Block - Bytes 2-33)
/*Read the battery temperature */
BUFF = BTMP // Invoke Read Word transaction
If (STAT == 0x00) // Successful?
{
// DATW = Battery temperature in 1/10th degrees Kelvin
}
/*Read the battery manufacturer name */
BUFF = MFGN // Invoke Read Blocktransaction
{
// LEN = Length of the manufacturer name
// DBUF = Manufacturer name (as a counted string)
}
Data (bytes 2-33) is ‘typecast’ as both word (DATW) and block (DBUF) data.
The example above demonstrates the use of the Store() operator to invoke a Read Block transaction to obtain the name
of the battery manufacturer. Evaluation of the source operand (MFGN) results in a 34-byte buffer that gets copied by
Store() to the destination buffer (BUFF).
Capturing the results of a write operation, for example to check the status code, requires an additional Store() operator,
as shown below:
BUFF = (MFGN = BUFF)
If (STAT == 0x00) // Transaction successful?
{
...
}
Note that the outer Store() copies the results of the Write Block transaction back into BUFF. This is the nature of
BufferAcc’s bi-directionality. It should be noted that storing (or parsing) the result of a GenericSerialBus Write
transaction is not required although useful for ascertaining the outcome of a transaction.
GenericSerialBus Process Call protocols require similar semantics due to the fact that only destination operands are
passed bi-directionally. These transactions require the use of the double-Store() semantics to properly capture the
return results.
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5.5.2.4.7.3 Using the GenericSerialBus Protocols
This section provides information and examples on how each of the GenericSerialBus protocols can be used to access
GenericSerialBus devices from AML.
Read/Write Quick (AttribQuick)
The GenericSerialBus Read/Write Quick protocol (AttribQuick) is typically used to control simple devices using a
device-speciﬁc binary command (for example, ON and OFF). Command values are not used by this protocol and thus
only a single element (at offset 0) can be speciﬁed in the ﬁeld deﬁnition. This protocol transfers no data.
The following ASL code illustrates how a device supporting the Read/Write Quick protocol should be accessed:
OperationRegion (TOP1, GenericSerialBus, 0x00, 0x100)
// GenericSerialBus device at command value offset 0

{
Connection (I2CSerialBusV2 (0x5a,,100000,,"\\_SB.I2C",,,,,RawDataBuffer (){1,6})),
AccessAs (BufferAcc, AttribQuick),
// Use the GenericSerialBus Read/Write Quick protocol
FLD0, 8 // Virtual register at command value 0.
}
Name (BUFF, Buffer (2){}) // Create GenericSerialBus data buffer as BUFF
/*Signal device (e.g. OFF) */
BUFF = FLD0 // Invoke Read Quick transaction
If (STAT == 0x00) // Was the transactions successful?
{
...
}
/*Signal device (e.g. ON) */
FLD0 = FLD0 // Invoke Write Quick transaction
In this example, a single ﬁeld element (FLD0) at offset 0 is deﬁned to represent the protocol’s read/write bit. Access
to FLD0 will cause a GenericSerialBus transaction to occur to the device. Reading the ﬁeld results in a Read Quick,
and writing to the ﬁeld results in a Write Quick. In either case data is not transferred–access to the register is simply
used as a mechanism to invoke the transaction.
Send/Receive Byte (AttribSendReceive)
The GenericSerialBus Send/Receive Byte protocol (AttribSendReceive) transfers a single byte of data. Like
Read/Write Quick, command values are not used by this protocol and thus only a single element (at offset 0) can
be speciﬁed in the ﬁeld deﬁnition.
The following ASL code illustrates how a device supporting the Send/Receive Byte protocol should be accessed:
{
AccessAs(BufferAcc, AttribSendReceive),
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// Use the GenericSerialBus Send/Receive Byte protocol
}
Name (BUFF, Buffer (3){}) // Create GenericSerialBus data buffer as BUFF
CreateByteField (BUFF, 0x02, DATA) // DATA = Data (Byte)
// Receive a byte of data from the device
BUFF = FLD0 // Invoke a Receive Byte transaction
{
// DATA = Received byte...
}
// Send the byte '0x16' to the device
DATA = 0x16 // Save 0x16 into the data buffer
FLD0 = BUFF //Invoke a Send Byte transaction
In this example, a single ﬁeld element (FLD0) at offset 0 is deﬁned to represent the protocol’s data byte. Access to
FLD0 will cause a GenericSerialBus transaction to occur to the device. Reading the ﬁeld results in a Receive Byte,
and writing to the ﬁeld results in a Send Byte.
Read/Write Byte (AttribByte)
The GenericSerialBus Read/Write Byte protocol (AttribByte) also transfers a single byte of data. But unlike
Send/Receive Byte, this protocol uses a command value to reference up to 256 byte-sized virtual registers.
The following ASL code illustrates how a device supporting the Read/Write Byte protocol should be accessed:
// GenericSerialBus device at command value offset
{
AccessAs(BufferAcc, AttribByte), // Use the GenericSerialBus Read/Write Byte
˓→protocol
FLD1, 8, // Virtual register at command value 1.
FLD2, 8 // Virtual register at command value 2.
}
Name (BUFF, Buffer (3){})
// Create GenericSerialBus data buffer as BUFF
// Read a byte of data from the device using command value 1
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BUFF = FLD1 // Invoke a Read Byte transaction
{
// DATA = Byte read from FLD1...
}
// Write the byte '0x16' to the device using command value 2
FLD2 = BUFF // Invoke a Write Byte transaction
In this example, three ﬁeld elements (FLD0, FLD1, and FLD2) are deﬁned to represent the virtual registers for com-
mand values 0, 1, and 2. Access to any of the ﬁeld elements will cause a GenericSerialBus transaction to occur to the
device. Reading FLD1 results in a Read Byte with a command value of 1, and writing to FLD2 results in a Write Byte
with command value 2.
Read/Write Word (AttribWord)
The GenericSerialBus Read/Write Word protocol (AttribWord) transfers 2 bytes of data. This protocol also uses a
command value to reference up to 256 word-sized virtual device registers.
The following ASL code illustrates how a device supporting the Read/Write Word protocol should be accessed:
{
AccessAs (BufferAcc, AttribWord),
}
Name(BUFF, Buffer(6){}) // Create GenericSerialBus data buffer as BUFF
/*Read two bytes of data from the device using command value 1 */
BUFF = FLD1 // Invoke a Read Word transaction
If (STAT == 0x00) // Was the transaction successful?
{
// DATA = Word read from FLD1...
}
/*Write the word '0x5416' to the device using command value 2 */
DATA = 0x5416 // Save 0x5416 into the data buffer
FLD2 = BUFF // Invoke a Write Word transaction
device. Reading FLD1 results in a Read Word with a command value of 1, and writing to FLD2 results in a Write
Word with command value 2.
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Notice that although accessing each ﬁeld element transmits a word (16 bits) of data, the ﬁelds are listed as 8 bits each.
The actual data size is determined by the protocol. Every ﬁeld element is declared with a length of 8 bits so that
command values and byte offsets are equivalent.
Read/Write Block (AttribBlock)
The GenericSerialBus Read/Write Block protocol (AttribBlock) transfers variable-sized data. This protocol uses a
command value to reference up to 256 block-sized virtual registers.
The following ASL code illustrates how a device supporting the Read/Write Block protocol should be accessed:
{
Offset(0x0),
AccessAs(BufferAcc, AttribBlock),
TFK1, 8,
TFK2, 8
}
Name (BUFF, Buffer (34){}) // Create SerialBus buf asBUFF
CreateBytefield (BUFF, 0x01, LEN) // LEN = Length (Byte)
CreateWordField (BUFF, 0x03, DATW) // DATW = Data (Word - Bytes 2 & 3, or16 bits)
CreateField (BUFF, 16, 256, DBUF) // DBUF = Data (Bytes 2-33)
CreateField (BUFF, 16, 32, DATD) // DATD = Data (DWord)
/*Read block of data from the device using command value 0 */
BUFF = TFK1
If (STAT != 0x00)
{
Return (0)
}
/*Read block of data from the device using command value 1 */
BUFF = TFK2
{
Return (0)
}
In this example, two ﬁeld elements (TFK1, and TFK2) are deﬁned to represent the virtual registers for command
values 0 and 1. Access to any of the ﬁeld elements will cause a GenericSerialBus transaction to occur to the device.
Writing blocks of data requires similar semantics, such as in the following example:
Store (16, LEN) // In bits, so 4 bytes
LEN = 16
BUFF = (TFK1 = BUFF)
{
...
}
This accessor is not viable for some SPBs because the bus may not support the appropriate functionality. In cases that
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variable length buffers are desired but the bus does not support block accessors, refer to the SerialBytes protocol.
Word Process Call (AttribProcessCall)

{
Return (0)
}
BUFF = TFK2
{
Return (0)
}
LEN = 16
{
...
}
The GenericSerialBus Process Call protocol (AttribProcessCall) transfers 2 bytes of data bi-directionally (performs a
Write Word followed by a Read Word as an atomic transaction). This protocol uses a command value to reference up
to 256 word-sized virtual registers.
The following ASL code illustrates how a device supporting the Process Call protocol should be accessed:
// GenericSerialBus device at slave address 0x42
{
Connection (I2CSerialBusV2 (0x5a,,100000,,"\\_SB.I2C",,,,,RawDataBuffer(){1,6})),
AccessAs (BufferAcc, AttribProcessCall),
// Use the GenericSerialBus Process Call protocol
}
Name (BUFF, Buffer (6){}) // Create GenericSerialBus data buffer as BUFF
CreateWordField (BUFF, 0x02, DATA) // DATA = Data (Word)
/*Process Call with input value '0x5416' to the device using command value 1 */
BUFF = (FLD1 = BUFF) // Invoke a Process Call transaction
{
// DATA = Word returned from FLD1...
}
mand values 0, 1, and 2. Access to any of the ﬁeld elements will cause a GenericSerialBus transaction to occur to
the device. Reading or writing FLD1 results in a Process Call with a command value of 1. Notice that unlike other
protocols, Process Call involves both a write and read operation in a single atomic transaction. This means that the
Data element of the GenericSerialBus data buffer is set with an input value before the transaction is invoked, and holds
the output value following the successful completion of the transaction.
Block Process Call (AttribBlockProcessCall)
The GenericSerialBus Block Write-Read Block Process Call protocol (AttribBlockProcessCall) transfers a block of
data bi-directionally (performs a Write Block followed by a Read Block as an atomic transaction). This protocol uses
a command value to reference up to 256 block-sized virtual registers.
{
AccessAs (BufferAcc, AttribBlockProcessCall),
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// Use the Block Process Call protocol
FLD0, 8, // Virtual register representing a command value of 0
FLD1, 8 // Virtual register representing a command value of 1
}
// Create the GenericSerialBus data buffer asBUFF
Name (BUFF, Buffer (35){}) // Create GenericSerialBus data buffer asBUFF
CreateField (BUFF, 0x10, 256, DATA) // Data (Block)
/*Process Call withinput value "ACPI" to the device using command value 1 */
DATA = "ACPI" // Fill inoutgoing data
LEN = 4 // Length of the valid data notincluding status (STAT)
//andlength (LEN) bytes.
BUFF = (FLD1 = BUFF)
If (STAT == 0x00) // Test the status
{
// BUFF now contains information returned from PC
// LEN now equals size of data returned
}
Read/Write N Bytes (AttribBytes)
The GenericSerialBus Read/Write N Bytes protocol (AttribBytes) transfers variable-sized data. The read transfer byte
length of the bi-directional call speciﬁed as a part of the AccessAs attribute.
The following ASL code illustrates how a device supporting the Read/Write N Bytes protocol should be accessed:
{
AccessAs (BufferAcc, AttribBytes (4)),
TFK1, 8, //TFK1 at command value 0
TFK2, 8, //TFK2 at command value 1
Connection (I2CSerialBus (0x5b,,100000,," \\_SB.I2C",,,,RawDataBuffer (){2,9})),
// same connection attribute, but different vendor data passed to driver
AccessAs (BufferAcc, AttribByte),
TM1, 8 //TM1 at command value 2
}
Name (BUFF, Buffer(34) {}) // Create SerialBus buf asBUFF
CreateWordField (BUFF, 0x02, DATW) // DATW = Data (Word - Bytes 2 & 3, or16 bits)
CreateField (BUFF, 16, 256, DBUF) // DBUF = Data (Bytes 2-34)
// Read block of data from the device using command value 0
BUFF = TFK1
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{
Return (0)
}
// Write block of data to the device using command value 1
BUFF = (TFK2 = BUFF)
{
Return (0)
}
values 0 and 1. Access to any of the ﬁeld elements will cause a GenericSerialBus transaction to occur to the device of
the length speciﬁed in the AccessAttributes.
Raw Read/Write N Bytes (AttribRawBytes)
The GenericSerialBus Raw Read/Write N Bytes protocol (AttribRawBytes) transfers variable-sized data. The read
transfer byte length of the bi- directional transaction speciﬁed as a part of the AccessAs attribute. The initial command
value speciﬁed in the operation region deﬁnition is ignored by Raw accesses.
{
AccessAs(BufferAcc, AttribRawBytes (4)),
TFK1, 8
}
Name(BUFF, Buffer (34){}) // Create SerialBus buf asBUFF
DATW = 0x0B // Store appropriate reference data fordriver to interpret
/*Read from TFK1 */
BUFF = TFK1
{
Return (0)
}
/*Write to TFK1 */
{
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Return(0)
}
Access to any ﬁeld elements will cause a GenericSerialBus transaction to occur to the device of the length speciﬁed in
the AccessAttributes.
Raw accesses assume that the writer has knowledge of the bus that the access is made over and the device that is being
accessed. The protocol may only ensure that the buffer is transmitted to the appropriate driver, but the driver must be
able to interpret the buffer to communicate to a register.
Raw Block Process Call (AttribRawProcessBytes)
The GenericSerialBus Raw Write-Read Block Process Call protocol (AttribRawProcessBytes) transfers a block of
data bi-directionally (performs a Write Block followed by a Read Block as an atomic transaction). The read transfer
byte length of the bi-directional transaction speciﬁed as a part of the AccessAs attribute. The initial command value
speciﬁed in the operation region deﬁnition is ignored by Raw accesses.
{
Connection (I2CSerialBusV2 (0x5a,,100000,," \\_SB.I2C",,,,,RawDataBuffer (){1,6})),
AccessAs (BufferAcc, AttribRawProcessBytes (2)),
// Use the Raw Bytes Process Call protocol
FLD0, 8
}
Name (BUFF, Buffer (34){}) // Create GenericSerialBus data buffer asBUFF
CreateWordField (BUFF,0x02, DATW) // Data (Bytes 2 and3)
DATW = 0x0B //Store appropriate reference data fordriver to interpret
/*Process Call withinput value "ACPI" to the device */

{
FLD0, 8
}
LEN = 4 // Length of the valid data
BUFF = (FLD0 = BUFF) // Execute the PC
{
}
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5.5.2.4.8 Declaring PCC Operation Regions
The Platform Communication Channel (PCC) is described in Chapter 14. The PCC table, described in Platform
Communications Channel Table , contains information about PCC subspaces implemented in a given platform, where
each subspace is a unique channel.
5.5.2.4.8.1 Overview
The PCC Operation Region works in conjunction with the PCC Table ( Platform Communications Channel Table ).
The PCC Operation Region is associated with the region of the shared memory that follows the PCC signature. PCC
Operation Region must not be used for extended subspaces of Type 4 (Responder subspaces). PCC subspaces that are
earmarked for use as PCC Operation Regions must not be used as PCC subspaces for standard ACPI features such as
CPPC, RASF, PDTT and MPST. These standard features must always use the PCC Table instead.
5.5.2.4.8.2 Declaring a PCC OperationRegion
The syntax for the OperationRegion term ( OperationRegion (Declare Operation Region) ) is described below:
)
The PCC Operation Region term in ACPI namespace will be deﬁned as follows:
OperationRegion ([subspace-name], PCC, [subspace-id], Length)
Where:
• RegionName is set to [subspace-name] , which is a unique name for this PCC subspace.
• RegionSpace must be set to PCC, operation region type 0x0A
• Offset must be set to [subspace-id] , the subspace ID of this channel, as deﬁned in the PCC table (PCCT).
• Length is the total size of the operation region, and is equal to the total size of the ﬁelds that succeed the PCC
signature in the shared memory.
5.5.2.4.8.3 Declaring message ﬁelds within a PCC OperationRegion
For all PCC subspace types, the PCC Operation Region pertains to the region of PCC subspace that succeeds the PCC
signature. The layout of the Shared Memory Regions is speciﬁc to the PCC subspace. The Operation Region handler
must therefore obtain the subspace type ﬁrst before it can comprehend and access individual ﬁelds within the subspace.
Fields within an Operation region are accessed using the Field keyword, and correspond to the ﬁelds that succeed the
PCC signature in the subspace shared memory. The syntax for the Field term (from Field (Declare Field Objects) ) is
Field (
RegionName,
AccessType,
LockRule,
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UpdateRule
For PCC Operation Regions:
• RegionName speciﬁes the name of the operation region, declared above the ﬁeld term.
• LockRule indicates if access to this operation region requires acquisition of the Global lock for synchronization.
This ﬁeld must be set to NoLock.
• UpdateRule is not applicable to PCC operation regions, since each command region is accessed in its entirety.
The FieldUnitList speciﬁes individual ﬁelds within the Shared Memory Region of the subspace, which depends on the
type of subspace. The declaration of the ﬁelds must match the layout of the subspace. Accordingly, for the Generic
Communications subspaces (Types 0-2), the FieldUnitList may be declared as follows:
Field(NAME, ByteAcc, NoLock, Preserve)
{
CMD, 16, // Command field
STAT, 16, // Status field, to be read on completion of the command
DATA, [Size] // Communication space of size [Size] bits
}
Likewise, for the Extended Communication subspaces (Type 3), the FieldUnitList may be declared as follows:
{
FLGS, 32, // Command Flags field
LEN, 32, // Length field
CMD, 32, // Command field
}
5.5.2.4.8.4 An Example of PCC Operation Region Declaration
As an example, if a platform feature uses PCC subspace with subspace ID of 0x02 of subspace Type 3 (Extended PCC
communication channel), then the caller may declare the operation region as follows:
OperationRegion(PFRM, PCC, 0x02, 0x10C)
Field(PFRM, ByteAcc, NoLock, Preserve)
{
Offset (4), // Flags start at offset 4 from beginning of shared memory
LGTH, 32, // Length field
COMD, 32, // Command field
COSP, 0x800 // Communication space of size 256 bytes
}
In this example, PFRM is the name of the subspace dedicated to the platform feature, and the size of the shared memory
region is 0x10C bytes (256 bytes of communication space and 16 bytes of ﬁelds excluding the PCC Signature).
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5.5.2.4.8.5 Using a PCC OperationRegion
The PCC Operation Region handler begins transmission of the message on the channel when it detects a write to the
CMD ﬁeld. The caller must therefore update all other ﬁelds relevant to the operation region ﬁrst, and then in the ﬁnal
step, write the command itself. As explained in Declaring message ﬁelds within a PCC OperationRegion , the ﬁelds to
be updated are speciﬁc to the subspace type.
For the Generic Communication subspace type (Types 0, 1 and 2), the order of Operation Region writes would be as
follows:
1. Write the command payload into the DATA ﬁeld. StepNumList-1 Write the command payload into the DATA
ﬁeld.
2. Write the command into the CMD ﬁeld.
For the Extended Communication subspace type (Type 3), the order of Operation Region writes would be as follows:
1. Write the command payload, length and ﬂags into the CMD, LEN and FLGS ﬁelds, respectively, in any order of
preference. StepNumList-1 Write the command payload, length and ﬂags into the CMD, LEN and FLGS ﬁelds,
respectively, in any order of preference.
In the above steps, the ﬁelds are as described in Section 5.5.2.4.8.4. When the platform completes processing the
command, it uses the same subspace Shared Memory Region to return the response data. The caller can thus read the
Operation Region to retrieve the response data.
If channel errors are encountered during transmission of the command or its response, the channel reports an error
status in the Channel Status register. The caller must therefore ﬁrst check the Channel Status register before processing
the return data. For the Generic PCC Communication Subspaces, the Channel Status register is located in the Shared
Memory Region itself, as described in Generic Communications Channel Status Field . The caller must thus check the
STAT ﬁeld in the Operation Region for the purpose. For the Extended PCC Communication Subspaces, the Channel
Status register is located anywhere in system memory or IO, and pointed to by the Error Status register ﬁeld within the
Type 3 PCC Subspace structure, as described in Extended PCC subspaces (types 3 and 4) .
5.5.2.4.8.6 Using the _REG Method for PCC Operation Regions
It is possible for the OS to include PCC operation region handlers that only comprehend and support a subset of the
possible subspaces deﬁned in this speciﬁcation. The OS can provide supplementary information in the _REG method
in order to indicate which exact subspaces(s) are supported. To accomplish this, the Arg0 parameter passed to the
_REG method must include both the Address Space ID (PCC) and a qualifying Address Space sub-type in Byte 1, as
follows:
Arg0, Byte 0 = PCC = 0x0A Arg0, Byte 1 = subspace type as deﬁned in Section 14.1.2.
The OS may now indicate support for handling PCC operation region subspace Type 3 by invoking the _REG method
with Arg0=0x030A and Arg1 = 0x01.
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5.5.2.4.8.7 Example Use of a PCC OperationRegion
The following sample ACPI Power Meter ( Power Meters ) implementation describes how a PCC Operation Region
can be used to read a platform power sensor that is exposed through a platform services channel. In this sample
system, the platform services channel is implemented as an Extended PCC Communication Channel (Type 3), and
assigned a PCC subspace ID of 0x07 in the PCCT. The sample platform implements three sensors - two power sen-

follows:
sors, associated with CPU cluster 0 and cluster 1 respectively, and a SoC-level thermal sensor. The power sensors
are read using command 0x15 (READ_POWER_SENSOR), while the thermal sensor is read using command 0x16
(READ_THERMAL_SENSOR), both on the platform services channel. The READ_POWER_SENSOR command
take two input parameters called SensorInstance and MeasurementFormat, which are appended together to the com-
mand as the payload. SensorInstance speciﬁes which power sensor is being referenced. MeasurementFormat speciﬁes
the measurement unit (watts or milliwatts) in which the power consumption is expressed. The command payload is
thus formatted as follows:
{
BYTE SensorInstance; // Which instance of the sensor isbeing read
BYTE MeasurementFormat; // 0 = mW, 1 = W
} COMMAND_PAYLOAD;
The power sensor for CPU cluster 0 is read by setting SensorInstance to 0x01, while the power sensor for CPU cluster
1 is read by setting SensorInstance to 0x02.
The response to the command from the platform is of the form:
{
DWORD Reading; // The sensor value read
DWORD Status; // Status of the operation - 0: success, non-zero: error
} SENSOR_RESPONSE;
Here, the ﬁeld Status pertains to the success or failure of the requested service. Channel errors can occur independent
of the service, during transmission of the request. A generic placeholder register, CHANNEL_STATUS_REG, and an
associated error status ﬁeld, ERROR_STATUS_BIT, is used as an illustration of how the channel status register may
be read to detect channel errors during transit.
The ACPI Power Meter object may now be implemented for this example platform as follows:
Device (PMT0) // ACPI Power Meter object for CPU Cluster 0 Power Sensor
{
Name (_HID, "ACPI000D") // ACPI Power Meter device
// The Operation Region declaration, based on "An Example of PCC Operation
// Region Declaration" described earlier in this chapter.
OperationRegion (PFRM, PCC, 0x07, 0x8C)
{
DATA, 0x400 // Communication space of size 128 bytes
}
Method (_REG, 2) // Check if OS Op region handler is available
{
/*
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*Check if Arg0.Byte0 = 0xA, PCC Operation Region Supported?
*Check if Arg0.Byte1 = 0x3, subchannel type 3 as defined in Table 14-357
*Disallow further processing until support for Type 3 becomes available
*/
}
// Read a Power sensor
Method (_PMM, 0, Serialized)
{
// Create the command buffer
Name(BUFF, Buffer(0x80){}) // Create PCC data buffer as BUFF
Name(PAYL, Buffer(2) {0x02, 0x01}) // Instance = CPU cluster 1
// Read power in units of Watts
DATA = PAYL // Only first two bytes written, the rest default to 0
// Update the length and status fields
LEN = 0x06 // 4B (command) + 2B (payload)
FLGS = 0x01 // Set Notify on Completion
/*
*All done. Now write to the command field to begin transmission of
*the message over the PCC subspace. On receipt, the platform will
*read power sensor of CPU cluster 0 and return the power consumption
*reading in the Operation Region itself
*/
CMD = 0x15 // READ_POWER_SENSOR command = 0x15
If(LEqual( LAnd (CHANNEL_STATUS_REG, ERROR_STATUS_BIT), 0x01)
{
Return (Ones). // Return invalid, so that the caller can take remedial
˓→steps
}
BUFF = DATA
CreateDWordField(BUFF, 0x00, PCL1) // Power consumed by CPU cluster 1
CreateDWordField(BUFF, 0x01, STAT) // Return status
If (STAT == 0x0)) // Successful?
{
Return (PCL1) // Return the power measurement for CPU cluster 1
}
Else
{
}
}
}
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5.6 ACPI Event Programming Model
The ACPI event programming model is based on the SCI interrupt and General-Purpose Event (GPE) register. ACPI
provides an extensible method to raise and handle the SCI interrupt, as described in this section.
Hardware-Reduced ACPI platforms use GPIO-signaled ACPI Events , orInterrupt-signaled ACPI events . Note that
any ACPI platform may utilize GPIO-signaled and/or Interrupts-signaled ACPI events (in other words, these events
are not limited to Hardware-reduced ACPIvplatforms).
5.6.1 ACPI Event Programming Model Components
The components of the ACPI event programming model are the following:
• OSPM
• FADT
• PM1a_STS, PM1b_STS and PM1a_EN, PM1b_EN ﬁxed register blocks
• GPE0_BLK and GPE1_BLK register blocks
• GPE register blocks deﬁned in GPE block devices
• SCI interrupt
• ACPI AML code general-purpose event model
• ACPI device-speciﬁc model events
• ACPI Embedded Controller event model
The role of each component in the ACPI event programming model is described in the following table.
Table 5.185: ACPI Event Programming Model Components
Component Description
OSPM Receives all SCI interrupts raised (receives all SCI events). Either
handles the event or masks the event off and later invokes an OEM-
provided control method to handle the event. Events handled di-
rectly by OSPM are ﬁxed ACPI events; interrupts handled by con-
trol methods are general-purpose events.
FADT Speciﬁes the base address for the following ﬁxed register blocks
on an ACPI-compatible platform: PM1x_STS and PM1x_EN ﬁxed
registers and the GPEx_STS and GPEx_EN ﬁxed registers.
PM1x_STS and PM1x_EN ﬁxed registers PM1x_STS bits raise ﬁxed ACPI events. While a PM1x_STS bit
is set, if the matching PM1x_EN bit is set, the ACPI SCI event is
raised.
GPEx_STS and GPEx_EN ﬁxed registers GPEx_STS bits that raise general-purpose events. For every event
bit implemented in GPEx_STS, there must be a comparable bit in
GPEx_EN. Up to 256 GPEx_STS bits and matching GPEx_EN bits
can be implemented. While a GPEx_STS bit is set, if the matching
GPEx_EN bit is set, then the general-purpose SCI event is raised.
SCI interrupt A level-sensitive, shareable interrupt mapped to a declared inter-
rupt vector. The SCI interrupt vector can be shared with other low-
priority interrupts that have a low frequency of occurrence.
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Table 5.185 – continued from previous page
ACPI AML code general-purpose event
modelA model that allows OEM AML code to use GPEx_STS events.
This includes using GPEx_STS events as “wake” sources as well as
other general service events deﬁned by the OEM (“button pressed,”
“thermal event,” “device present/not present changed,” and so on).
ACPI device-speciﬁc model events Devices in the ACPI namespace that have ACPI-speciﬁc device IDs
can provide additional event model functionality. In particular, the
ACPI embedded controller device provides a generic event model.
ACPI Embedded Controller event model A model that allows OEM AML code to use the response from the
Embedded Controller Query command to provide general-service
event deﬁned by the OEM.
5.6.2 Types of ACPI Events
At the ACPI hardware level, two types of events can be signaled by an SCI interrupt:
• Fixed ACPI events
• General-purpose events
In turn, the general-purpose events can be used to provide further levels of events to the system. And, as in the case of
the embedded controller, a well-deﬁned second-level event dispatching is deﬁned to make a third type of typical ACPI
event. For the ﬂexibility common in today’s designs, two ﬁrst-level general-purpose event blocks are deﬁned, and the
embedded controller construct allows a large number of embedded controller second-level event-dispatching tables to
be supported. Then if needed, the OEM can also build additional levels of event dispatching by using AML code on a
general-purpose event to sub-dispatch in an OEM deﬁned manner.
5.6.3 Fixed Event Handling
When OSPM receives a ﬁxed ACPI event, it directly reads and handles the event registers itself. The following table
lists the ﬁxed ACPI events. For a detailed speciﬁcation of each event, see the ACPI Hardware Speciﬁcation
Table 5.186: Fixed ACPI Events
Event Comment
Power management timer carry bit set. For more information, see the description of the TMR_STS and TMR_EN
bits of the PM1x ﬁxed register block in PM1 Event Grouping
Power button signal A power button can be supplied in two ways. One way is to simply use the
ﬁxed status bit, and the other uses the declaration of an ACPI power device
and AML code to determine the event. For more information about the
alternate-device based power button, see Control Method Power Button .
Notice that during the S0 state, both the power and sleep buttons merely
notify OSPM that they were pressed. If the system does not have a sleep
button, it is recommended that OSPM use the power button to initiate
sleep operations as requested by the user.

Sleep button signal A sleep button can be supplied in one of two ways. One way is to simply
use the ﬁxed status button. The other way requires the declaration of an
ACPI sleep button device and AML code to determine the event.
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Table 5.186 – continued from previous page
RTC alarm ACPI-deﬁnes an RTC wake alarm function with a minimum of one-month
granularity. The ACPI status bit for the device is optional. If the ACPI
status bit is not present, the RTC status can be used to determine when
an alarm has occurred. For more information, see the description of the
RTC_STS and RTC_EN bits of the PM1x ﬁxed register block in PM1
Event Grouping
Wake status The wake status bit is used to determine when the sleeping state has been
completed. For more information, see the description of the WAK_STS
and WAK_EN bits of the PM1x ﬁxed register block in PM1 Event Group-
ing
System bus master request The bus-master status bit provides feedback from the hardware as to when
a bus master cycle has occurred. This is necessary for supporting the pro-
cessor C3 power savings state. For more information, see the description
of the BM_STS bit of the PM1x ﬁxed register block in PM1 Event Group-
ing
Global Release Status This status is raised as a result of the Global Lock protocol, and is handled
by OSPM as part of Global Lock synchronization. For more information,
see the description of the GBL_STS bit of the PM1x ﬁxed register block
inPM1 Event Grouping .
5.6.4 General-Purpose Event Handling
When OSPM receives a general-purpose event, it either passes control to an ACPI-aware driver, or uses an OEM-
supplied control method to handle the event. An OEM can implement up to 128 general-purpose event inputs in
hardware per GPE block, each as either a level or edge event. It is also possible to implement a single 256-pin block
as long as it’s the only block deﬁned in the system.
An example of a general-purpose event is speciﬁed in ACPI Hardware Speciﬁcation where EC_STS and EC_EN bits
are deﬁned to enable OSPM to communicate with an ACPI-aware embedded controller device driver. The EC_STS bit
is set when either an interface in the embedded controller space has generated an interrupt or the embedded controller
interface needs servicing. Notice that if a platform uses an embedded controller in the ACPI environment, then the
embedded controller’s SCI output must be directly and exclusively tied to a single GPE input bit.
Hardware can cascade other general-purpose events from a bit in the GPEx_BLK through status and enable bits
in Operational Regions (I/O space, memory space, PCI conﬁguration space, or embedded controller space). For
more information, see the speciﬁcation of the General-Purpose Event Blocks (GPEx_BLK) in General-Purpose Event
Register Blocks
OSPM manages the bits in the GPEx blocks directly, although the source to those events is not directly known and is
connected into the system by control methods. When OSPM receives a general-purpose event (the event is from either
a GPEx_BLK STS bit, a GPIO pin, or an Interrupt), OSPM does the following:
1. Disables the interrupt source
2. (GPEx_BLK EN bit): GPIO interrupt for GPIO-signaled events. | Interrupt for Interrupt-signaled events. | If an
edge event, clears the status bit.
3. Performs one of the following: Dispatches to an ACPI-aware device driver. | Queues the matching control
method for execution. | Manages a wake event using device _PRW objects.
4. If a level event, waits for the control method handler to complete and clears the status bit.
5. Enables the interrupt source.
For OSPM to manage the bits in the GPEx_BLK blocks directly:
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• Enable bits must be read/write.
• Status bits must be latching.
• Status bits must be read/clear, and cleared by writing a “1” to the status bit.
5.6.4.1 _Exx, _Lxx, and _Qxx Methods for GPE Processing
The OEM AML code can perform OEM-speciﬁc functions custom to each event the particular platform might gen-
erate by executing a control method that matches the event. For GPE events, OSPM will execute the control method
of the name \_GPE._TXX where XX is the hex value format of the event that needs to be handled and T indicates
the event handling type (T must be either ‘E’ for an edge event or ‘L’ for a level event). The event values for sta-
tus bits in GPE0_BLK start at zero (_T00) and end at the (GPE0_BLK_LEN / 2) - 1. The event values for status
bits in GPE1_BLK start at GPE1_BASE and end at GPE1_BASE + (GPE1_BLK_LEN / 2) - 1. GPE0_BLK_LEN,
GPE1_BASE, and GPE1_BLK_LEN are all deﬁned in the FADT.
The _Qxx methods are used for the Embedded Controller and SMBus (see below).
5.6.4.1.1 Queuing the Matching Control Method for Execution
When a general-purpose event is raised, OSPM uses a naming convention to determine which control method to queue
for execution and how the GPE EOI is to be handled. The GPEx_STS bits in the GPEx_BLK are indexed with a
number from 0 through FF. The name of the control method to queue for an event raised from an enable status bit
is always of the form \_GPE._Txx where xx is the event value and T indicates the event EOI protocol to use (either
‘E’ for edge triggered, or ‘L’ for level triggered). The event values for status bits in GPE0_BLK start at zero (_T00),
end at the (GPE0_BLK_LEN / 2) - 1, and correspond to each status bit index within GPE0_BLK. The event values
for status bits in GPE1_BLK are offset by GPE_BASE and therefore start at GPE1_BASE and end at GPE1_BASE +
(GPE1_BLK_LEN / 2) - 1.
For example, suppose an OEM supplies a wake event for a communications port and uses bit 4 of the GPE0_STS bits
to raise the wake event status. In an OEM-provided Deﬁnition Block, there must be a Method declaration that uses the
name \_GPE._L04 or \GPE._E04 to handle the event. An example of a control method declaration using such a name
is the following:
Method (\_GPE._L04) { // GPE 4 level wake handler
Notify (\_SB.PCIO.COM0, 2)
}
The control method performs whatever action is appropriate for the event it handles. For example, if the event means
that a device has appeared in a slot, the control method might acknowledge the event to some other hardware register
and signal a change notify request of the appropriate device object. Or, the cause of the general-purpose event can
result from more then one source, in which case the control method for that event determines the source and takes the
appropriate action.
When a general-purpose event is raised from the GPE bit tied to an embedded controller, the embedded controller
driver uses another naming convention deﬁned by ACPI for the embedded controller driver to determine which con-
trol method to queue for execution. The queries that the embedded controller driver exchanges with the embedded
controller are numbered from 0 through FF, yielding event codes 01 through FF. (A query response of 0 from the em-
bedded controller is reserved for “no outstanding events.”) The name of the control method to queue is always of the
form _Qxx where xx is the number of the query acknowledged by the embedded controller. An example declaration
for a control method that handles an embedded controller query is the following:
Method(_Q34) { // embedded controller event forthermal
Notify (\_SB.TZ0.THM1, 0x80)
}
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When an SMBus alarm is handled by the SMBus driver, the SMBus driver uses a similar naming convention deﬁned
by ACPI for the driver to determine the control method to queue for execution. When an alarm is received by the
SMBus host controller, it generally receives the SMBus address of the device issuing the alarm and one word of data.
On implementations that use SMBALERT# for notiﬁcations, only the device address will be received. The name of
the control method to queue is always of the form _Qxx where xx is the SMBus address of the device that issued
the alarm. The SMBus address is 7 bits long corresponding to hex values 0 through 7F, although some addresses are
reserved and will not be used. The control method will always be queued with one argument that contains the word of
data received with the alarm. An exception is the case of an SMBus using SMBALERT# for notiﬁcations, in this case
the argument will be 0. An example declaration for a control method that handles a SMBus alarm follows:
Method(_Q18, 1) { // Thermal sensor device at address 001 1000
// Arg0 contains notification value ( ifany)
// Arg0 = 0 ifdevice supports only SMBALERT #
}
5.6.4.1.2 Dispatching to an ACPI-Aware Device Driver
Certain device support, such as an embedded controller, requires a dedicated GPE to service the device. Such GPEs

}
are dispatched to native OS code to be handled and not to the corresponding GPE-speciﬁc control method.
In the case of the embedded controller, an OS-native, ACPI-aware driver is given the GPE event for its device. This
driver services the embedded controller device and determines when events are to be reported by the embedded con-
troller by using the Query command. When an embedded controller event occurs, the ACPI-aware driver dispatches
the requests to other ACPI-aware drivers that have registered to handle the embedded controller queries or queues
control methods to handle each event. If there is no device driver to handle speciﬁc queries, OEM AML code can per-
form OEM-speciﬁc functions that are customized to each event on the particular platform by including speciﬁc control
methods in the namespace to handle these events. For an embedded controller event, OSPM will queue the control
method of the name _QXX, where XX is the hex format of the query code. Notice that each embedded controller
device can have query event control methods.
Similarly, for an SMBus driver, if no driver registers for SMBus alarms, the SMBus driver will queue control methods
to handle these. Methods must be placed under the SMBus device with the name _QXX where XX is the hex format
of the SMBus address of the device sending the alarm.
5.6.4.2 GPE Wake Events
An important use of the general-purpose events is to implement device wake events. The components of the ACPI
event programming model interact in the following way:
• When a device asserts its wake signal, the general-purpose status event bit used to track that device is set.
• While the corresponding general-purpose enable bit is enabled, the SCI interrupt is asserted.
• If the system is sleeping, this will cause the hardware, if possible, to transition the system into the S0 state.
• Once the system is running, OSPM will dispatch the corresponding GPE handler.
• The handler needs to determine which device object has signaled wake and performs a wake Notify command
on the corresponding device object(s) that have asserted wake.
• In turn OSPM will notify OSPM native driver(s) for each device that will wake its device to service it.
Events that wake may not be intermixed with non-wake (runtime) events on the same GPE input. The only exception
to this rule is made for the special devices below. Only the following devices are allowed to utilize a single GPE for
both wake and runtime events:
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1. Button Devices: PNP0C0C - Power Button Device | PNP0C0D - Lid Device | PNP0C0E - Sleep Button Device
2. PCI Bus Wakeup Event Reporting (PME): PNP0A03 - PCI Host Bridge
All wake events that are not exclusively tied to a GPE input (for example, one input is shared for multiple wake events)
must have individual enable and status bits in order to properly handle the semantics used by the system.
5.6.4.2.1 Managing a Wake Event Using Device _PRW Objects
A device’s _PRW object provides the zero-based bit index into the general-purpose status register block to indicate
which general-purpose status bit from either GPE0_BLK or GPE1_BLK is used as the speciﬁc device’s wake mask.
Although the hardware must maintain individual device wake enable bits, the system can have multiple devices using
the same general-purpose event bit by using OEM-speciﬁc hardware to provide second-level status and enable bits. In
this case, the OEM AML code is responsible for the second-level enable and status bits.
OSPM enables or disables the device wake function by enabling or disabling its corresponding GPE and by executing
its _PSW control method (which is used to take care of the second-level enables). When the GPE is asserted, OSPM
still executes the corresponding GPE control method that determines which device wakes are asserted and notiﬁes the
corresponding device objects. The native OS driver is then notiﬁed that its device has asserted wake, for which the
driver powers on its device to service it.
If the system is in a sleeping state when the enabled GPE bit is asserted the hardware will transition the system into
the S0 state, if possible.
5.6.4.2.2 Determining the System Wake Source Using _Wxx Control Methods
After a transition to the S0 state, OSPM may evaluate the _SWS object in the \_GPE scope to determine the index of
the GPE that was the source of the transition event. When a single GPE is shared among multiple devices, the platform
provides a _Wxx control method, where xx is GPE index as described in Determining the System Wake Source Using
_Wxx Control Methods , that allows the source device of the transition to be determined. If implemented, the _Wxx
control method must exist in the \_GPE scope or in the scope of a GPE block device.
If_Wxx is implemented, either hardware or ﬁrmware must detect and save the source device as described in sws-
system-wake-source . During invocation, the _Wxx control method determines the source device and issues a No-
tify(<device>,0x2) on the device that caused the system to transition to the S0 state. If the device uses a bus-speciﬁc
method of arming for wakeup, then the Notify must be issued on the parent of the device that has a _PRW method.
The_Wxx method must issue a Notify(<device>,0x2) only to devices that contain a _PRW method within their device
scope. OSPM’s evaluation of the _SWS and _Wxx objects is indeterminate. As such, the platform must not rely on
_SWS or _Wxx evaluation to clear any hardware state, including GPEx_STS bits, or to perform any wakeup-related
actions.
If the GPE index returned by the _SWS object is only referenced by a single _PRW object in the system, it is implied
that the device containing that _PRW is the wake source. In this case, it is not necessary for the platform to provide a
_Wxx method.
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5.6.5 GPIO-signaled ACPI Events
On Hardware-reduced ACPI platforms, ACPI events can be signaled when a GPIO Interrupt is received by OSPM,
and that GPIO Interrupt Connection is listed in a GPIO controller device’s _AEI object. OSPM claims all such GPIO
interrupts, and maps them to the appropriate event method required by the ACPI event model.
5.6.5.1 Declaring GPIO Controller Devices
A GPIO controller is modeled as a device in the namespace, with _HID or _ADR and _CRS objects, at a minimum. Op-
tionally, the GPIO controller device scope may include GeneralPurposeIO OpRegion declarations ( Section 5.5.2.4.5)
and GPIO interrupt-to-ACPI Event mappings (Section 5.6.5.2). Note that for GPIO-signaled ACPI Events , the corre-
sponding event method (e.g. _Exx, _Lxx, or _EVT) must also appear in the target GPIO controller’s scope. For GPIO
event numbers larger than 255 (0xFF), the _EVT method is used.
Each pin on a GPIO Controller has a conﬁguration (e.g. level-sensitive interrupt, de-bounced input, high-drive output,
etc.), which is described to OSPM in the GPIO Interrupt or GPIO IO Connection resources claimed by peripheral
devices or used in operation region accesses.
5.6.5.2 _AEI Object for GPIO-signaled Events
The _AEI object designates those GPIO interrupts that shall be handled by OSPM as ACPI events (see Section 5.6.5).
This object appears within the scope of the GPIO controller device whose pins are to be used as GPIO-signaled events.
None
Return Value:
A resource template Buffer containing only GPIO Interrupt Connection descriptors.
Example :
Device (\_SB.GPI2)
{
Name(_HID, "XYZ0003")
Name(_UID, 2) //Third instance of this controller on the
˓→platform
Name(_CRS, ResourceTemplate ()
{ //Register Interface
MEMORY32FIXED(ReadWrite, 0x30000000, 0x200, ) //Interrupt line (GSIV 21)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {21}
})
Name(_AEI, ResourceTemplate ()
{ //Thermal Zone Event
GpioInt(Edge, ActiveHigh, Exclusive, PullDown, , " \\\_SB.GPI2") {14}
//Power Button
GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, , " \\\_SB.GPI2") {36}
})
}
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5.6.5.3 The Event (_EVT) Method for Handling GPIO-signaled Events
GPIO Interrupt Connection Descriptors assign GPIO pins a controller-relative, 0-based pin number. GPIO Pin numbers
can be as large as 65, 535. GPIO Interrupt Connections that are assigned by the platform to signal ACPI events are
listed in the _AEI object under the GPIO controller. Since the GPIO interrupt connection descriptor also provides the
mode of the interrupt associated with an event, it gives OSPM all the information it needs to invoke a handler method
for the event. No naming convention is required to encode the mode and pin number of the event. Instead, a handler for
a GPIO-signaled event simply needs to have a well-known name and take the pin number of the event as a parameter.
A single instance of the method handles all ACPI events for a given GPIO controller device.

})
}
For GPIO-signaled events, the Event (_EVT) method is used. _EVT is deﬁned as follows:
Arguments (1):
Arg0 - EventNumber. An Integer indicating the event number (Controller-relative zero-based GPIO pin
number) of the current event. Must be in the range 0x0000 - 0xffff.
None
Description:
The _EVT method handles a GPIO-signaled event. It must appear within the scope of the GPIO controller
device whose pins are used to signal the event.
OSPM handles GPIO-signaled events as follows:
• The GPIO interrupt is handled by OSPM because it is listed in the _AEI object under a GPIO
• When the event ﬁres, OSPM handles the interrupt according to its mode and invokes the _EVT
method, passing it the pin number of the event.
• From this point on, handling is exactly like that for GPEs. The _EVT method does a Notify() on the
appropriate device, and OS-speciﬁc mechanisms are used to notify the driver of the event.
• For event numbers less than 255, _Exx and _Lxx methods may be used instead. In this case, they
take precedence and _EVT will not be invoked.
Note: For event numbers less than 255, _Exx and _Lxx methods may be used instead. In this case, they take
precedence and _EVT will not be invoked.
Example :
Scope (\_SB.GPI2)
{
Method (_EVT,1) { // Handle all ACPI Events signaled by GPIO Controller GPI2
Switch (Arg0)
{
Case (300) {
...
Notify (\_SB.DEVX, 0x80)
}
Case (1801) {
...
Notify (\_SB.DEVY, 0x80)
}
Case (14...) {
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...
Notify (\_SB.DEVZ, 0x80)
}
...
}
} //End of Method
} //End of Scope
5.6.6 Device Object Notiﬁcations
During normal operation, the platform needs to notify OSPM of various device-related events. These notiﬁcations
are accomplished using the Notify operator, which indicates a target device, thermal zone, or processor object and a
notiﬁcation value that signiﬁes the purpose of the notiﬁcation. Notiﬁcation values from 0 through 0x7F are common
across all device object types. Notiﬁcation values of 0xC0 and above are reserved for deﬁnition by hardware vendors
for hardware speciﬁc notiﬁcations. Notiﬁcation values from 0x80 to 0xBF are device-speciﬁc and deﬁned by each
such device. For more information on the Notify operator, see Section 19.6.94.
Table 5.187: Device Object Notiﬁcation Values
0 Bus Check. This notiﬁcation is performed on a device object to indicate to OSPM that it needs
to perform a Plug and Play re-enumeration operation on the device tree starting from the point
where it has been notiﬁed. OSPM will typically perform a full enumeration automatically at boot
time, but after system initialization it is the responsibility of the ACPI AML code to notify OSPM
whenever a re-enumeration operation is required. The more accurately and closer to the actual
change in the device tree the notiﬁcation can be done, the more efﬁcient the operating system’s
response will be; however, it can also be an issue when a device change cannot be conﬁrmed.
For example, if the hardware cannot recognize a device change for a particular location during a
system sleeping state, it issues a Bus Check notiﬁcation on wake to inform OSPM that it needs to
check the conﬁguration for a device change.
1 Device Check. Used to notify OSPM that the device either appeared or disappeared. If the device
has appeared, OSPM will re-enumerate from the parent. If the device has disappeared, OSPM
will invalidate the state of the device. OSPM may optimize out re-enumeration. If _DCK is
present, then Notify(object,1) is assumed to indicate an undock request. If the device is a bridge,
OSPM may re-enumerate the bridge and the child bus.
2 Device Wake. Used to notify OSPM that the device has signaled its wake event, and that OSPM
needs to notify OSPM native device driver for the device. This is only used for devices that
support _PRW.
3 Eject Request. Used to notify OSPM that the device should be ejected, and that OSPM needs to
perform the Plug and Play ejection operation. OSPM will run the _EJx method.
4 Device Check Light. Used to notify OSPM that the device either appeared or disappeared. If the
device has appeared, OSPM will re-enumerate from the device itself, not the parent. If the device
has disappeared, OSPM will invalidate the state of the device.
5 Frequency Mismatch. Used to notify OSPM that a device inserted into a slot cannot be attached
to the bus because the device cannot be operated at the current frequency of the bus. For example,
this would be used if a user tried to hot-plug a 33 MHz PCI device into a slot that was on a bus
running at greater than 33 MHz.
6 Bus Mode Mismatch. Used to notify OSPM that a device has been inserted into a slot or bay that
cannot support the device in its current mode of operation. For example, this would be used if a
user tried to hot-plug a PCI device into a slot that was on a bus running in PCI-X mode.
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Table 5.187 – continued from previous page
7 Power Fault. Used to notify OSPM that a device cannot be moved out of the D3 state because of
a power fault.
8 Capabilities Check. This notiﬁcation is performed on a device object to indicate to OSPM that it
needs to re-evaluate the _OSC control method associated with the device.
9 Device _PLD Check. Used to notify OSPM to reevaluate the _PLD object, as the Device’s con-
nection point has changed.
0xA Reserved.
0xB System Locality Information Update. Dynamic reconﬁguration of the system may cause existing
relative distance information to change. The platform sends the System Locality Information
Update notiﬁcation to a point on a device tree to indicate to OSPM that it needs to invoke the
_SLI objects associated with the System Localities on the device tree starting from the point
notiﬁed.
0x0C Reserved.
0x0D System Resource Afﬁnity Update. Dynamic migration of devices may cause existing system
resource afﬁnity to change. The platform software issues the System Resource Afﬁnity Update
notiﬁcation to a point on a device tree to indicate to OSPM that it needs to invoke the _PXM
object of the notiﬁed device to update the resource afﬁnity.
0x0E Heterogeneous Memory Attributes Update. Dynamic reconﬁguration of the system may cause
existing latency, bandwidth or memory side caching attribute to change. The platform software
issues the Heterogeneous Memory Attributes Update notiﬁcation to a point on a device tree to
indicate to OSPM that it needs to invoke the _HMA objects associated with the Heterogeneous
Memory Attributes on the device tree starting from the point notiﬁed.
0x0F Error Disconnect Recover: Used to notify OSPM of asynchronous removal of devices for error
containment purposes. The notiﬁcation is issued on a bus device that is still present, but one
or more of its child device have been disconnected from the system due to an error condition.
OSPM should invalidate the software state associated with the disconnected child devices without
attempting to access these child devices. Subsequently, OSPM can optionally attempt to recover
the disconnected child devices and ,if possible, bring them back to functional state via bus speciﬁc
methods. OSPM communicates the status of these recovery operations to the Firmware via the
_OST method. Section 6.3.5.2 describes the associated _OST status codes. OSPM support for
Error Disconnect Recover notiﬁcation for a given type of bus is enumerated via a bus speciﬁc
mechanism.
0x10-0xFF Reserved.
Below are the notiﬁcation values deﬁned for speciﬁc ACPI devices. For more information concerning the object-
speciﬁc notiﬁcation, see the section for the corresponding device/object.
Table 5.188: System Bus Notiﬁcation Values
Hex value Description
0x80 Reserved.
0x81 Graceful Shutdown Request . Used to notify OSPM that a graceful shutdown of the operating
system has been requested. Once the operating system has ﬁnished its graceful shutdown proce-
dure it should initiate a transition to the G2 “soft off” state. The Notify operator must target the
System Bus: (_SB). See Section 6.3.5 for a description of shutdown processing.
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Table 5.189: Control Method Battery Device Notiﬁcation Values
0x80 Battery Status Changed . Used to notify OSPM that the Control Method Battery device status
0x81 Battery Information Changed . Used to notify OSPM that the Control Method Battery device
information has changed. This only occurs when a battery is replaced.
0x82 Battery Maintenance Data Status Flags Check . Used to notify OSPM that the Control Method
Battery device battery maintenance data status ﬂags should be checked.
0x83-0xBF Reserved
Table 5.190: Power Source Object Notiﬁcation Values

0x80 Power Source Status Changed . Used to notify OSPM that the power source status has changed.
0x81 Power Source Information Changed . Used to notify OSPM that the power source information
0x82-0xBF Reserved
Table 5.191: Thermal Zone Object Notiﬁcation Values
0x80 Thermal Zone Status Changed . Used to notify OSPM that the thermal zone temperature has
changed.
0x81 Thermal Zone Trip points Changed . Used to notify OSPM that the thermal zone trip points
have changed.
0x82 Device Lists Changed . Used to notify OSPM that the thermal zone device lists (_ALx, _PSL,
_TZD) have changed.
0x83 Thermal / Active Cooling Relationship Table Changed . Used to notify OSPM that values in
the either the thermal relationship table or the active cooling relationship table have changed.
0x84-0xBF Reserved
Table 5.192: Control Method Power Button Notiﬁcation Values
0x80 S0 Power Button Pressed . Used to notify OSPM that the power button has been pressed while
the system is in the S0 state. Notice that when the button is pressed while the system is in the
S1-S4 state, a Device Wake notiﬁcation must be issued instead.
0x81-0xBF Reserved
Table 5.193: Control Method Sleep Button Notiﬁcation Values
0x80 S0 Sleep Button Pressed . Used to notify OSPM that the sleep button has been pressed while the
system is in the S0 state. Notice that when the button is pressed while the system is in the S1-S4
state, a Device Wake notiﬁcation must be issued instead.
Table 5.194: Control Method Lid Notiﬁcation Values
0x80 Lid Status Changed . Used to notify OSPM that the control method lid device status has changed.
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Table 5.194 – continued from previous page
Table 5.195: NVDIMM Root Device Notiﬁcation Values
0x80 NFIT Update Notiﬁcation . Used to notify OSPM that it needs to re-evaluate the _FIT method
under the NVDIMM root device (see Section 9.19.2).
0x81 Unconsumed Uncorrectable Memory Error Detected . Used to pro-actively notify OSPM of
uncorrectable memory errors detected (for example a memory scrubbing engine that continuously
scans the NVDIMMs memory). This is an optional notiﬁcation. Only locations that were mapped
in to SPA by the platform will generate a notiﬁcation.
0x82 ARS Stopped Notiﬁcation . This is an optional notiﬁcation, used to notify OSPM when the
platform completes ARS or when ARS has stopped prematurely for any ARS that was either
started by the platform or by OSPM via Start ARS (see Section 9.19.7.5). The OSPM can
evaluate Query ARS Status on receiving this event notiﬁcation.
Table 5.196: NVDIMM Device Notiﬁcation Values
0x80 Reserved
0x81 NFIT Health Event Notiﬁcation . Used to notify OSPM of health event(s) for the NVDIMM de-
vice (see Section 9.19.3). On receiving the NFIT Health Event Notiﬁcation, the OSPM is required
to determine new health event by re-enumerating the health of the corresponding NVDIMM de-
vice. This could be accomplished by evaluating the _NCH method (see Section 9.19.8.1) or
_DSM method under the NVDIMM device. This is also used to notify OSPM of a change in the
“Overall Health Status Attributes” ﬁeld reported by the _NCH method.
Table 5.197: Processor Device Notiﬁcation Values
0x80 Performance Present Capabilities Changed . Used to notify OSPM that the number of sup-
ported processor performance states has changed. This notiﬁcation causes OSPM to re-evaluate
the _PPC object. See Section 8.4.5.3 for more information.
0x81 C States Changed . Used to notify OSPM that the number or type of supported processor C
States has changed. This notiﬁcation causes OSPM to re-evaluate the _CST object. See Section
8.4.1.1 for more information.
0x82 Throttling Present Capabilities Changed . Used to notify OSPM that the number of supported
processor throttling states has changed. This notiﬁcation causes OSPM to re-evaluate the _TPC
object. See Section 8.4.4.3 for more information.
0x83 Guaranteed Changed . Used to notify OSPM that the value of the CPPC Guaranteed Register
0x84 Minimum Excursion . Used to notify OSPM that an excursion to CPPC Minimum has occurred.
0x85 Highest Performance Changed . Used to notify OSPM that the value of the CPPC Highest
Performance Register has changed.
0x86-0xBF Reserved
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Table 5.198: User Presence Device Notiﬁcation Values
0x80 User Presence Changed . Used to notify OSPM that a meaningful change in user presence has
occurred, causing OSPM to re-evaluate the _UPD object.
Table 5.199: Ambient Light Sensor Device Notiﬁcation Values
0x80 ALS Illuminance Changed . Used to notify OSPM that a meaningful change in ambient light
illuminance has occurred, causing OSPM to re-evaluate the _ALI object.
0x81 ALS Color Temperature Changed . Used to notify OSPM that a meaningful change in ambient
light color temperature or chromaticity has occurred, causing OSPM to re-evaluate the _ALT
and/or _ALC objects.
0x82 ALS Response Changed . Used to notify OSPM that the set of points used to convey the ambient
light response has changed, causing OSPM to re-evaluate the _ALR object.
Table 5.200: Power Meter Object Notiﬁcation Values
0x80 Power Meter Capabilities Changed . Used to notify OSPM that the power meter information
0x81 Power Meter Trip Points Crossed . Used to notify OSPM that one of the power meter trip points
has been crossed.
0x82 Power Meter Hardware Limit Changed . Used to notify OSPM that the hardware limit has been
changed by the platform.
0x83 Power Meter Hardware Limit Enforced . Used to notify OSPM that the hardware limit has
been enforced by the platform.
0x84 Power Meter Averaging Interval Changed. Used to notify OSPM that the power averaging interval
0x85-0xBF Reserved
Table 5.201: Processor Aggregator Device Notiﬁcation Values
0x80 Processor Utilisation Request . Used to notify OSPM that OSPM evaluates the _PUR object
which indicates to OSPM the number of logical processors to be idled.
Table 5.202: Error Device Notiﬁcation Values
0x80 Notiﬁcation For Generic Error Sources . Used to notify OSPM to respond to this notiﬁcation
by checking the error status block of all generic error sources to identify the source reporting the
error.
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Table 5.203: Fan Device Notiﬁcation Values
0x80 Low Fan Speed . Used to notify OSPM of a low (errant) fan speed. Causes OSPM to re-evaluate
the _FSL object.
Table 5.204: Memory Device Notiﬁcation Values
0x80 Memory Bandwidth Low Threshold crossed . Used to notify OSPM that bandwidth of memory
described by the memory device has been reduced by the platform to less than the low memory
bandwidth threshold.
0x81 Memory Bandwidth High Threshold crossed . Used to notify OSPM that bandwidth of memory
described by the memory device has been increased by the platform to greater than or equal to
the high memory bandwidth threshold.
5.6.7 Device Class-Speciﬁc Objects
Most device objects are controlled through generic objects and control methods and they have generic device IDs.
These generic objects, control methods, and device IDs are speciﬁed in Section 6, through Section 11 . Section 5.6.8,
“Predeﬁned ACPI Names for Objects, Methods, and Resources,” lists all the generic objects and control methods
deﬁned in this speciﬁcation.
However, certain integrated devices require support for some device-speciﬁc ACPI controls. This section lists these
devices, along with the device-speciﬁc ACPI controls that can be provided.
Some of these controls are for ACPI-aware devices and as such have Plug and Play IDs that represent these devices.
The table below lists the Plug and Play IDs deﬁned by the ACPI speciﬁcation.
Note: Plug and Play IDs that are not deﬁned by the ACPI speciﬁcation are deﬁned and described in the “Links to
ACPI-Related Documents” (http://ueﬁ.org/acpi) under the heading “Legacy PNP Guidelines”.
Table 5.205: ACPI Device IDs
Plug and Play ID Description
PNP0C08 ACPI . Not declared in ACPI as a device. This ID is used by OSPM for the hardware
resources consumed by the ACPI ﬁxed register spaces, and the operation regions used by
AML code. It represents the core ACPI hardware itself.
PNP0A05 Generic Container Device . A device whose settings are totally controlled by its ACPI

resource information, and otherwise needs no device or bus-speciﬁc driver support. This
was originally known as Generic ISA Bus Device. This ID should only be used for contain-
ers that do not produce resources for consumption by child devices. Any system resources
claimed by a PNP0A05 device’s _CRS object must be consumed by the container itself.
PNP0A06 Generic Container Device . This device behaves exactly the same as the PNP0A05 device.
This was originally known as Extended I/O Bus. This ID should only be used for containers
that do not produce resources for consumption by child devices. Any system resources
claimed by a PNP0A06 device’s _CRS object must be consumed by the container itself.
PNP0C09 Embedded Controller Device . A host embedded controller controlled through an ACPI-
aware driver.
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Table 5.205 – continued from previous page
PNP0C0A Control Method Battery . A device that solely implements the ACPI Control Method
Battery functions. A device that has some other primary function would use its normal
device ID. This ID is used when the devices primary function is that of a battery.
PNP0C0B Fan. A device that causes cooling when “on” (D0 device state).
PNP0C0C Power Button Device . A device controlled through an ACPI-aware driver that provides
power button functionality. This device is only needed if the power button is not supported
using the ﬁxed register space.
PNP0C0D Lid Device . A device controlled through an ACPI-aware driver that provides lid status
functionality. This device is only needed if the lid state is not supported using the ﬁxed
register space.
PNP0C0E Sleep Button Device . A device controlled through an ACPI-aware driver that provides
power button functionality. This device is optional.
PNP0C0F PCI Interrupt Link Device . A device that allocates an interrupt connected to a PCI inter-
rupt pin. See Section 6.2.13 for more details.
PNP0C80 Memory Device . This device is a memory subsystem.
ACPI0001 SMBus 1.0 Host Controller . An SMBus host controller (SMB-HC) compatible with the
embedded controller-based SMB-HC interface (see Section 12.9), and implementing the
SMBus 1.0 Speciﬁcation.
ACPI0002 Smart Battery Subsystem . The Smart battery Subsystem speciﬁed in Section 10, “Power
Source Devices.”
ACPI0003 Power Source Device . The Power Source device speciﬁed in Section 10, “Power Source
Devices.” This can represent either an AC Adapter (on mobile platforms) or a ﬁxed Power
Supply.
ACPI0004 Module Device . This device is a container object that acts as a bus node in a namespace. A
Module Device without any of the _CRS, _PRS and _SRS methods behaves the same way
as the Generic Container Devices (PNP0A05 or PNP0A06). If the Module Device contains
a _CRS method, only these resources described in the _CRS are available for consumption
by its child devices. Also, the Module Device can support _PRS and _SRS methods if
_CRS is supported.
ACPI0005 SMBus 2.0 Host Controller . An SMBus host controller (SMB-HC compatible with the
SMBus 2.0 Speciﬁcation.
ACPI0006 GPE Block Device . This device allows a system designer to describe GPE blocks beyond
the two that are described in the FADT.
ACPI0007 Processor Device . This device provides an alternative to declaring processors using the
processor ASL statement. See Section 8.4 for more details.
ACPI0008 Ambient Light Sensor Device . This device is an ambient light sensor. See Section 9.3.
ACPI0009 I/OxAPIC Device . This device is an I/O unit that complies with both the APIC and SAPIC
interrupt models.
ACPI000A I/O APIC Device . This device is an I/O unit that complies with the APIC interrupt model.
ACPI000B I/O SAPIC Device . This device is an I/O unit that complies with the SAPIC interrupt
model.
ACPI000C Processor Aggregator Device . This device provides a control point for all processors in
the platform. See Section 8.5.
ACPI000D Power Meter Device . This device is a power meter. See Section 10.4.
ACPI000E Time and Alarm Device . This device is a control method-based real-time clock and wake
alarm. See Section 9.17.
ACPI000F User Presence Detection Device . This device senses user presence (proximity). See Sec-
tion 9.15)
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ACPI0010 Processor container device . Used to declare hierarchical processor topologies (see Section
8.4.2, and Section 8.4.2.1).
ACPI0011 Generic Buttons Device. This device reports button events corresponding to Human Inter-
face Device (HID) control descriptors (see Section 9.18).
ACPI0012 NVDIMM Root Device. This device contains the NVDIMM devices. See Section 9.19 and
Table 5.126.
ACPI0013 Generic Event Device . This device maps Interrupt-signaled events. See Section 5.6.9.
ACPI0014 Wireless Power Calibration Device . This device uses user presence and notiﬁcation.
ACPI0015 USB4 host interface device . See Links to ACPI-Related Documents under the heading
“USB4 Host Interface Speciﬁcation”
ACPI0016 Compute Express Link Host Bridge . This device is a Compute Express Link Host bridge.
ACPI0017 Compute Express Link Root Object . This device represents the root of a CXL capable
device hierarchy. It shall be present whenever the platform allows OSPM to dynamically
assign CXL endpoints to a platform address space.
ACPI0018 Audio Composition Device . This is an ACPI-enumerated device that describes audio com-
ponent logical connection information within a system.
5.6.8 Predeﬁned ACPI Names for Objects, Methods, and Resources
The following table summarizes the predeﬁned names for the ACPI namespace objects, control methods, and resource
descriptor ﬁelds deﬁned in this speciﬁcation. Provided for each name is a short description and a reference to the
section number and page number of the actual deﬁnition of the name. ACPI names that are predeﬁned by other
speciﬁcations are also listed along with their corresponding speciﬁcation reference.
Note: All names that begin with an underscore are reserved for ACPI use only.
Table 5.206: Predeﬁned ACPI Names
_ACx Active Cooling – returns the active cooling policy threshold values.
_ADR Address: (1) returns the address of a device on its parent bus. (2) returns a unique ID for the
display output device. (3) resource descriptor ﬁeld.
_AEI Designates those GPIO interrupts that shall be handled by OSPM as ACPI events.
_ALC Ambient Light Chromaticity – returns the ambient light color chromaticity.
_ALI Ambient Light Illuminance – returns the ambient light brightness.
_ALN Alignment – base alignment, resource descriptor ﬁeld.
_ALP Ambient Light Polling – returns the ambient light sensor polling frequency.
_ALR Ambient Light Response – returns the ambient light brightness to display brightness mappings.
_ALT Ambient Light Temperature – returns the ambient light color temperature.
_ALx Active List – returns a list of active cooling device objects.
_ART Active cooling Relationship Table – returns thermal relationship information between platform
devices and fan devices.
_ASI Address Space Id – resource descriptor ﬁeld.
_ASZ Access Size – resource descriptor ﬁeld.
_ATT Type-Speciﬁc Attribute – resource descriptor ﬁeld.
_BAS Base Address – range base address, resource descriptor ﬁeld.
_BBN Bios Bus Number – returns the PCI bus number returned by the platform ﬁrmware.
_BCL Brightness Control Levels – returns a list of supported brightness control levels.
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Table 5.206 – continued from previous page
_BCM Brightness Control Method – sets the brightness level of the display device.
_BCT Battery Charge Time – returns time remaining to complete charging battery.
_BDN Bios Dock Name – returns the Dock ID returned by the platform ﬁrmware.
_BIF Battery Information – returns a Control Method Battery information block.
_BIX Battery Information Extended – returns a Control Method Battery extended information block.
_BLT Battery Level Threshold – set battery level threshold preferences.
_BM Bus Master – resource descriptor ﬁeld.
_BMA Battery Measurement Averaging Interval – Sets battery measurement averaging interval.
_BMC Battery Maintenance Control – Sets battery maintenance and control features.
_BMD Battery Maintenance Data – returns battery maintenance, control, and state data.
_BMS Battery Measurement Sampling Time – Sets the battery measurement sampling time.
_BPC Battery Power Characteristics
_BPS Battery Power State
_BPT Battery Power Threshold
_BQC Brightness Query Current – returns the current display brightness level.

_BST Battery Status – returns a Control Method Battery status block.
_BTH Battery Throttle Limit - speciﬁes the thermal throttle limit of battery for the ﬁrmware when en-
gaging charging.
_BTM Battery Time – returns the battery runtime.
_BTP Battery Trip Point – sets a Control Method Battery trip point.
_CBA Conﬁguration Base Address – returns the base address of the MMIO range corresponding to the
Enhanced Conﬁguration Access Mechanism for a PCI Express or Compute Express Link host bus.
The full description for the _CBA object resides in the PCI Firmware Speciﬁcation. A reference
to that speciﬁcation is found in the “Links to ACPI-Related Documents” (http://ueﬁ.org/acpi)
under the heading “PCI SIG”.
_CBR CXL Host Bridge Register Info
_CCA Cache Coherency Attribute – speciﬁes whether a device and its descendants support hardware
managed cache coherency.
_CDM Clock Domain – returns a logical processor’s clock domain identiﬁer.
_CID Compatible ID – returns a device’s Plug and Play Compatible ID list.
_CLS Class Code – supplies OSPM with the PCI-deﬁned class, subclass and programming interface for
a device. Optional.
_CPC Continuous Performance Control – declares an interface that allows OSPM to transition the pro-
cessor into a performance state based on a continuous range of allowable values.
_CRS Current Resource Settings – returns the current resource settings for a device.
_CRT Critical Temperature – returns the shutdown critical temperature.
_CSD C State Dependencies – returns a list of C-state dependencies.
_CST C States – returns a list of supported C-states.
_CWS Clear Wake Status – Clears the wake status of a Time and Alarm Control Method Device.
_DBT Debounce Timeout -Debounce timeout setting for a GPIO input connection, resource descriptor
ﬁeld
_DCK Dock – sets docking isolation. Presence indicates device is a docking station.
_DCS Display Current Status – returns status of the display output device.
_DDC Display Data Current – returns the EDID for the display output device.
_DDN Dos Device Name – returns a device logical name.
_DEC Decode – device decoding type, resource descriptor ﬁeld.
_DEP Operation Region Dependencies – evaluates to a package and designates device objects that
OSPM should assign a higher priority in start ordering due to future operation region accesses.
_DGS Display Graphics State – returns the current state of the output device.
_DIS Disable – disables a device.
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_DLM Device Lock Mutex- Designates a mutex as a Device Lock.
_DMA Direct Memory Access – returns a device’s current resources for DMA transactions.
_DOD Display Output Devices – enumerate all devices attached to the display adapter.
_DOS Disable Output Switching – sets the display output switching mode.
_DPL Device Selection Polarity - The polarity of the Device Selection signal on a SPISerialBus con-
nection, resource descriptor ﬁeld
_DRS Drive Strength – Drive strength setting for a GPIO output connection, resource descriptor ﬁeld
_DSD Device Speciﬁc Data– returns device-speciﬁc information.
_DSM Device Speciﬁc Method – executes device-speciﬁc functions.
_DSS Device Set State – sets the display device state.
_DSW Device Sleep Wake – sets the sleep and wake transition states for a device.
_DTI Device Temperature Indication – conveys native device temperature to the platform.
_Exx Edge GPE – method executed as a result of a general-purpose event.
_EC Embedded Controller – returns EC offset and query information.
_EDL Eject Device List – returns a list of devices that are dependent on a device (docking).
_EJD Ejection Dependent Device – returns the name of dependent (parent) device (docking).
_EJx Eject – begin or cancel a device ejection request (docking).
_END Endian-ness – Endian orientation of a UART SerialBus connection, resource descriptor ﬁeld
_EVT Event Method - Event method for GPIO-signaled events numbered larger than 255.
_FDE Floppy Disk Enumerate – returns ﬂoppy disk conﬁguration information.
_FDI Floppy Drive Information – returns a ﬂoppy drive information block.
_FDM Floppy Drive Mode – sets a ﬂoppy drive speed.
_FIF Fan Information – returns fan device information.
_FIT Firmware Interface Table - returns a list of NFIT Structures.
_FIX Fixed Register Resource Provider – returns a list of devices that implement FADT register blocks.
_FLC Flow Control – Flow Control mechanism for a UART SerialBus connection, resource descriptor
ﬁeld
_FPS Fan Performance States – returns a list of supported fan performance states.
_FSL Fan Set Level – Control method that sets the fan device’s speed level (performance state).
_FST Fan Status – returns current status information for a fan device.
_GAI Get Averaging Interval – returns the power meter averaging interval.
_GCP Get Capabilities – Returns the capabilities of a Time and Alarm Control Method Device
_GHL Get Hardware Limit – returns the hardware limit enforced by the power meter.
_GL Global Lock – OS-deﬁned Global Lock mutex object.
_GLK Global Lock – returns a device’s Global Lock requirement for device access.
_GPD Get Post Data – returns the value of the VGA device that will be posted at boot.
_GPE General Purpose Events: (1) predeﬁned Scope (_GPE). (2) Returns the SCI interrupt associated
with the Embedded Controller.
_GRA Granularity – address space granularity, resource descriptor ﬁeld.
_GRT Get Real Time – Returns the current time from a Time and Alarm Control Method Device.
_GSB Global System Interrupt Base – returns the GSB for a I/O APIC device.
_GTF Get Task File – returns a list of ATA commands to restore a drive to default state.
_GTM Get Timing Mode – returns a list of IDE controller timing information.
_GWS Get Wake Status – Gets the wake status of a Time and Alarm Control Method Device.
_HE High-Edge – interrupt triggering, resource descriptor ﬁeld.
_HID Hardware ID – returns a device’s Plug and Play Hardware ID.
_HMA Heterogeneous Memory Attributes - returns a list of HMAT structures.
_HOT Hot Temperature – returns the critical temperature for sleep (entry to S4).
_HPP Hot Plug Parameters – returns a list of hot-plug information for a PCI device.
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_HPX Hot Plug Parameter Extensions – returns a list of hot-plug information for a PCI device. Super-
sedes _HPP.
_HRV Hardware Revision– supplies OSPM with the device’s hardware revision. Optional.
_IFT IPMI Interface Type. See the Intelligent Platform Management Interface Speciﬁcation at “Links
to ACPI-Related Documents” (http://ueﬁ.org/acpi) under the heading “Server Platform Manage-
ment Interface Table”.
_INI Initialize – performs device speciﬁc initialization.
_INT Interrupts – interrupt mask bits, resource descriptor ﬁeld.
_IOR IO Restriction – IO restriction setting for a GPIO IO connection, resource descriptor ﬁeld
_IRC Inrush Current – presence indicates that a device has a signiﬁcant inrush current draw.
_Lxx Level GPE – Control method executed as a result of a general-purpose event.
_LCK Lock – locks or unlocks a device (docking).
_LEN Length – range length, resource descriptor ﬁeld.
_LID Lid – returns the open/closed status of the lid on a mobile system.
_LIN Lines in Use - Handshake lines in use in a UART SerialBus connection, resource descriptor ﬁeld
_LL Low Level – interrupt polarity, resource descriptor ﬁeld.
_LPI Low Power Idle States – returns the list of low power idle states supported by a processor or
processor container.
_LSI Label Storage Information – Returns information about the Label Storage Area associated with
the NVDIMM object, including its size.
_LSR Label Storage Read – Returns label data from the Label Storage Area of the NVDIMM object.
_LSW Label Storage Write – Writes label data in to the Label Storage Area of the NVDIMM object.
_MAF Maximum Address Fixed – resource descriptor ﬁeld.
_MAT Multiple Apic Table Entry – returns a list of Interrupt Controller Structures.
_MAX Maximum Base Address – resource descriptor ﬁeld.
_MBM Memory Bandwidth Monitoring Data – returns bandwidth monitoring data for a memory device.
_MEM Memory Attributes – resource descriptor ﬁeld.
_MIF Minimum Address Fixed – resource descriptor ﬁeld.
_MIN Minimum Base Address – resource descriptor ﬁeld.
_MLS Multiple Language String – returns a device description in multiple languages.
_MOD Mode –Resource descriptor ﬁeld
_MSG Message – sets the system message waiting status indicator.
_MSM Memory Set Monitoring – sets bandwidth monitoring parameters for a memory device.
_MTL Minimum Throttle Limit – returns the minimum throttle limit of a speciﬁc thermal.
_MTP Memory Type – resource descriptor ﬁeld.

_NTT Notiﬁcation Temperature Threshold – returns a threshold for device temperature change that re-
quires platform notiﬁcation.
_OFF Off – sets a power resource to the off state.
_ON On – sets a power resource to the on state.
_OS Operating System – returns a string that identiﬁes the operating system.
_OSC Operating System Capabilities – inform AML of host features and capabilities.
_OSI Operating System Interfaces – returns supported interfaces, behaviors, and features.
_OST Ospm Status Indication – inform AML of event processing status.
_PAI Power Averaging Interval – sets the averaging interval for a power meter.
_PAR Parity – Parity for a UART SerialBus connection, resource descriptor ﬁeld
_PCL Power Consumer List – returns a list of devices powered by a power source.
_PCT Performance Control – returns processor performance control and status registers.
_PDC Processor Driver Capabilities – inform AML of processor driver capabilities.
_PDL P-state Depth Limit – returns the lowest available performance P-state.
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_PHA Clock Phase – Clock phase for a SPISerialBus connection, resource descriptor ﬁeld
_PIC PIC – inform AML of the interrupt model in use.
_PIF Power Source Information – returns a Power Source information block.
_PIN Pin List – List of GPIO pins described, resource descriptor ﬁeld.
_PLD Physical Location of Device – returns a device’s physical location information.
_PMC Power Meter Capabilities – returns a list of Power Meter capabilities info.
_PMD Power Metered Devices – returns a list of devices that are measured by the power meter device.
_PMM Power Meter Measurement – returns the current value of the Power Meter.
_POL Polarity – Resource descriptor ﬁeld
_PPC Performance Present Capabilites – returns a list of the performance states currently supported by
the platform.
_PPE Polling for Platform Error – returns the polling interval to retrieve Corrected Platform Error in-
formation.
_PPI Pin Conﬁguration – Pin conﬁguration for a GPIO connection, resource descriptor ﬁeld
_PR Processor – predeﬁned scope for processor objects.
_PR0 Power Resources for D0 – returns a list of dependent power resources to enter state D0 (fully on).
_PR1 Power Resources for D1 – returns a list of dependent power resources to enter state D1.
_PR2 Power Resources for D2 – returns a list of dependent power resources to enter state D2.
_PR3 Power Resources for D3hot – returns a list of dependent power resources to enter state D3hot.
_PRE Power Resources for Enumeration - Returns a list of dependent power resources to enumerate
devices on a bus.
_PRL Power Source Redundancy List – returns a list of power source devices in the same redundancy
grouping.
_PRR Power Resource for Reset – executes a reset on the associated device or devices.
_PRS Possible Resource Settings – returns a list of a device’s possible resource settings.
_PRT Pci Routing Table – returns a list of PCI interrupt mappings.
_PRW Power Resources for Wake – returns a list of dependent power resources for waking.
_PS0 Power State 0 – sets a device’s power state to D0 (device fully on).
_PS1 Power State 1 – sets a device’s power state to D1.
_PS2 Power State 2 – sets a device’s power state to D2.
_PS3 Power State 3 – sets a device’s power state to D3 (device off).
_PSC Power State Current – returns a device’s current power state.
_PSD Power State Dependencies – returns processor P-State dependencies.
_PSE Power State for Enumeration
_PSL Passive List – returns a list of passive cooling device objects.
_PSR Power Source – returns the power source device currently in use.
_PSS Performance Supported States – returns a list of supported processor performance states.
_PSV Passive – returns the passive trip point temperature.
_PSW Power State Wake – sets a device’s wake function.
_PTC Processor Throttling Control – returns throttling control and status registers.
_PTP Power Trip Points – sets trip points for the Power Meter device.
_PTS Prepare To Sleep – inform the platform of an impending sleep transition.
_PUR Processor Utilization Request – returns the number of processors that the platform would like to
idle.
_PXM Proximity – returns a device’s proximity domain identiﬁer.
_Qxx Query – Embedded Controller query and SMBus Alarm control method.
_RBO Register Bit Offset – resource descriptor ﬁeld.
_RBW Register Bit Width – resource descriptor ﬁeld.
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_RDI Resource Dependencies for Idle - returns the list of power resource dependencies for system level
low power idle states.
_REG Region – inform AML code of an operation region availability change.
_REV Revision – returns the revision of the ACPI speciﬁcation that is implemented.
_RMV Remove – returns a device’s removal ability status (docking).
_RNG Range – memory range type, resource descriptor ﬁeld.
_ROM Read-Only Memory – returns a copy of the ROM data for a display device.
_RST Device Reset – executes a reset on the associated device or devices.
_RT Resource Type – resource descriptor ﬁeld.
_RTV Relative Temperature Values – returns temperature value information.
_RW Read-Write Status – resource descriptor ﬁeld.
_RXL Receive Buffer Size - Size of the receive buffer in a UART Serialbus connection, resource de-
scriptor ﬁeld.
_S0 S0 System State – returns values to enter the system into the S0 state.
_S1 S1 System State – returns values to enter the system into the S1 state.
_S2 S2 System State – returns values to enter the system into the S2 state.
_S3 S3 System State – returns values to enter the system into the S3 state.
_S4 S4 System State – returns values to enter the system into the S4 state.
_S5 S5 System State – returns values to enter the system into the S5 state.
_S1D S1 Device State – returns the highest D-state supported by a device when in the S1 state.
_S2D S2 Device State – returns the highest D-state supported by a device when in the S2 state.
_S3D S3 Device State – returns the highest D-state supported by a device when in the S3 state.
_S4D S4 Device State – returns the highest D-state supported by a device when in the S4 state.
_S0W S0 Device Wake State – returns the lowest D-state that the device can wake itself from S0.
_S1W S1 Device Wake State – returns the lowest D-state for this device that can wake the system from
S1.
_S2W S2 Device Wake State – returns the lowest D-state for this device that can wake the system from
S2.
_S3W S3 Device Wake State – returns the lowest D-state for this device that can wake the system from
S3.
_S4W S4 Device Wake State – returns the lowest D-state for this device that can wake the system from
S4.
_SB System Bus – scope for device and bus objects.
_SBS Smart Battery Subsystem – returns the subsystem conﬁguration.
_SCP Set Cooling Policy – sets the cooling policy (active or passive).
_SDD Set Device Data – sets data for a SATA device.
_SEG Segment – returns a device’s PCI Segment Group number.
_SHL Set Hardware Limit – sets the hardware limit enforced by the Power Meter.
_SHR Shareable - interrupt share status, resource descriptor ﬁeld.
_SI System Indicators – predeﬁned scope.
_SIZ Size – DMA transfer size, resource descriptor ﬁeld.
_SLI System Locality Information – returns a list of NUMA system localities.
_SLV Slave Mode – Slave mode setting for a SerialBus connection, resource descriptor ﬁeld.
_SPD Set Post Device – sets which video device will be posted at boot.
_SPE Connection Speed – Connection speed for a SerialBus connection, resource descriptor ﬁeld
_SRS Set Resource Settings – sets a device’s resource allocation.
_SRT Set Real Time – Sets the current time to a Time and Alarm Control Method Device.
_SRV IPMI Spec Revision. See the Intelligent Platform Management Interface Speciﬁcation at “Links
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_SST System Status – sets the system status indicator.
_STA Status : (1) returns the current status of a device. (2) Returns the current on or off state of a Power
Resource.
_STB Stop Bits - Number of stop bits used in a UART SerialBus connection, resource descriptor ﬁeld
_STM Set Timing Mode – sets an IDE controller transfer timings.
_STP Set Expired Timer Wake Policy – sets expired timer policies of the wake alarm device.
_STR String – returns a device’s description string.
_STV Set Timer Value – set timer values of the wake alarm device.
_SUB Supplies OSPM with the device’s Subsystem ID. Optional.

Resource.
_SUN Slot User Number – returns the slot unique ID number.
_SWS System Wake Source – returns the source event that caused the system to wake.
_T_x Temporary – reserved for use by ASL compilers.
_TC1 Thermal Constant 1 – returns TC1 for the passive cooling formula.
_TC2 Thermal Constant 2 – returns TC2 for the passive cooling formula.
_TDL T-State Depth Limit – returns the _TSS entry number of the lowest power throttling state.
_TFP Thermal Fast Sampling Period - returns the thermal sampling period for passive cooling.
_TIP Expired Timer Wake Policy – returns timer policies of the wake alarm device.
_TIV Timer Values – returns remaining time of the wake alarm device.
_TMP Temperature – returns a thermal zone’s current temperature.
_TPC Throttling Present Capabilities – returns the current number of supported throttling states.
_TPT Trip Point Temperature – inform AML that a devices’ embedded temperature sensor has crossed
a temperature trip point.
_TRA Translation – address translation offset, resource descriptor ﬁeld.
_TRS Translation Sparse – sparse/dense ﬂag, resource descriptor ﬁeld.
_TRT Thermal Relationship Table – returns thermal relationships between platform devices.
_TSD Throttling State Dependencies – returns a list of T-state dependencies.
_TSF Type-Speciﬁc Flags – resource descriptor ﬁeld.
_TSN Thermal Sensor Device - returns a reference to the thermal sensor reporting a zone temperature
_TSP Thermal Sampling Period – returns the thermal sampling period for passive cooling.
_TSS Throttling Supported States – returns supported throttling state information.
_TST Temperature Sensor Threshold – returns the minimum separation for a device’s temperature trip
points.
_TTP Translation Type – translation/static ﬂag, resource descriptor ﬁeld.
_TTS Transition To State – inform AML of an S-state transition.
_TXL Transmit Buffer Size – Size of the transmit buffer in a UART Serialbus connection, resource
descriptor ﬁeld
_TYP Type – DMA channel type (speed), resource descriptor ﬁeld.
_TZ Thermal Zone – predeﬁned scope: ACPI 1.0.
_TZD Thermal Zone Devices – returns a list of device names associated with a Thermal Zone.
_TZM Thermal Zone Member – returns a reference to the thermal zone of which a device is a member.
_TZP Thermal Zone Polling – returns a Thermal zone’s polling frequency.
_UID Unique ID – return a device’s unique persistent ID.
_UPC USB Port Capabilities – returns a list of USB port capabilities.
_UPD User Presence Detect – returns user detection information.
_UPP User Presence Polling – returns the recommended user presence polling interval.
_VEN Vendor-deﬁned Data – Vendor-deﬁned data for a GPIO or SerialBus connection, resource de-
scriptor ﬁeld
_VPO Video Post Options – returns the implemented video post options.
_WAK Wake – inform AML that the system has just awakened.
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_WPC Wireless Power Calibration - returns the notiﬁer to wireless power controller.
_WPP Wireless Power Polling - returns the recommended polling frequency
_Wxx Wake Event – method executed as a result of a wake event.
5.6.9 Interrupt-signaled ACPI events
ACPI 6.1introduces support for generating ACPI events when an interrupt is received by the OSPM, and that interrupt
is listed in the Generic Event Device (GED) _CRS object. OSPM claims all such interrupts, and maps them to the
appropriate event method required by the ACPI event model.
5.6.9.1 Declaring Generic Event Device
The Generic Event Device (GED) is modelled as a device in the namespace with a _HID deﬁned to be ACPI0013.
The GED must also provide one _CRS and _EVT object for claiming interrupts and mapping them to ACPI events, as
described in the following sections. The platform declare its support for the GED, and query whether an OS supports
it, via the _OSC method, see Section 6.2.11.2.
5.6.9.2 _CRS Object for Interrupt-signaled Events
The _CRS object designates those interrupts that shall be handled by OSPM as ACPI events. This object appears
within the scope of the GED whose interrupts sources are to be used as Interrupt-signaled events.
Arguments :
None
Return Value :
A resource template Buffer containing only Interrupt Resource descriptors.
• For event numbers less than 255, _Exx and _Lxx methods may be used instead. In this case, they take precedence
and _EVT will not be invoked.
Example :
Device (\_SB.GED1)
{
Name(_HID,"ACPI0013")
{
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {41}
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {42}
Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake) {43}
})
...
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5.6.9.3 The Event (_EVT) Method for Handling Interrupt-signaled Events
Interrupts that are assigned by the platform to signal ACPI events are listed in the _CRS object under the GED device.
Since the interrupt descriptor also provides the mode of the interrupt associated with an event, it gives OSPM all the
information it needs to invoke a handler method for the event. A single instance of the method handles all ACPI events
for a given GED.
• Please refer to Section 5.6.4 for the OSPM requirements of handling an event (steps 1-5).
For Interrupt-signaled events, the Event (_EVT) method is used.
_EVT is deﬁned as follows:
Arguments: (1)
Arg0 - EventNumber. An Integer indicating the event number (GSIV number) of the current event. Must
be in the range 0x00000000 - 0xffffffff.
None
The _EVT method handles an Interrupt-signaled event. It must appear within the scope of the GED whose interrupts
are used to signal the event.
OSPM handles Interrupt-signaled events as follows:
• The interrupt is handled by OSPM because it is listed in the _CRS object under a GED.
• When the event ﬁres, OSPM handles the interrupt according to its mode and invokes the _EVT method, passing
it the interrupt number of the event. In the case of level interrupts, the ASL within the _EVT method must be
responsible for clearing the interrupt at the device.
• From this point on, handling is exactly like that for GPEs. The _EVT method may optionally call Notify() on
the appropriate device, and OS-speciﬁc mechanisms are used to notify the driver of the event.
Example :
{
{
Interrupt(ResourceConsumer, Edge, ActiveHigh, Shared) {42}
}
Method (_EVT,1) { // Handle all ACPI Events signaled by the Generic
Event Device(GED1)
Switch (Arg0) // Arg0 = GSIV of the interrupt
{
Case (41) { // interrupt 41
Store(One, ISTS) // clear interrupt status register at device X
// which is mapped via an operation region
Notify (\_SB.DEVX, 0x0) // insertion request
}
Case (42) { // interrupt 42
Notify (\_SB.DEVX, 0x3) // ejection request
}
Case (43) { // interrupt 43
5.6. ACPI Event Programming Model 313Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Notify (\_SB.DEVX, 0x2) // wake event
}
}
} //End of GED1 Scope
Device (\_SB.DEVX)
{
...
Name(_PRW,Package()
{
Package(2){ // EventInfo
\\_SB.GED1, // device reference
0x2 // event (zero-based CRS index) = 2 (maps to interrupt 43)
},
0x03, // Can wake up from S3 state
PWRA // PWRA must be ON for DEVX to wake system
})
...
} //End of DEVX Scope
5.6.9.4 GED Wake Events
An important use of the interrupt-signaled events is to implement device wake events. Interrupt-based Wake Events
are described in Section 4.1.1.2. Note that the interrupt associated with that wake event must be wake-capable per the
Extended Interrupt resource descriptor listed under the _CRS object.
Consider the ASL example in the previous section, note that the interrupts that map to the wake event for DEVX are
wake-capable. The components of the Interrupt-signaled ACPI event programming model interact in the following
way:
• When a device asserts its wake signal and the interrupt has been enabled by the GED driver, the interrupt is
asserted.
• Once the system is running, OSPM will dispatch the GED interrupt service routine.
• The GED needs to determine which interrupt has been asserted and may perform a Notify command on the
corresponding device object(s) that have asserted wake.
Wake events must be exclusively tied to a GED interrupt (for example, one interrupt cannot be shared by multiple

way:
asserted.
wake events) in order to properly handle the semantics used by the system
Note that any ACPI platform may utilize GPIO-signaled and/or Interrupts-signaled ACPI events (i.e. they are not
limited to Hardware-reduced ACPI platforms).
5.6. ACPI Event Programming Model 314Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.6.10 Managing a Wake Event Using Device _PRW Objects
A device’s _PRW object provides the zero-based index into the _AEI object of a GPIO controller device or zero-based
index into the _CRS object of a Generic Event Device (GED).
OSPM enables or disables the device wake function by enabling or disabling its corresponding event and by executing
its _PSW control method (which is used to take care of the second-level enables). When the event is asserted, OSPM
still executes the corresponding event control method that determines which device wakes are asserted and notiﬁes the
If the system is in a sleeping state when the enabled event is asserted the hardware will transition the system into the
S0 state, if possible.
5.7 Predeﬁned Objects
The AML interpreter of an ACPI compatible operating system supports the evaluation of a number of predeﬁned
objects. The objects are considered “built in” to the AML interpreter on the target operating system.
A list of predeﬁned object names are shown in the following table.
Table 5.207: Predeﬁned Object Names
\_GL Global Lock mutex
\_OS Name of the operating system
\_OSI Operating System Interface support
\_REV Revision of the ACPI speciﬁcation that is implemented
5.7.1 \_GL (Global Lock Mutex)
This predeﬁned object is a Mutex object that behaves like a Mutex as deﬁned in Section 19.6.87, “Mutex (Declare
Synchronization/Mutex Object),” with the added behavior that acquiring this Mutex also acquires the shared environ-
ment Global Lock deﬁned in Section 5.2.10.1, “Global Lock.” This allows Control Methods to explicitly synchronize
with the Global Lock if necessary.
5.7.2 \_OSI (Operating System Interfaces)
This method is used by the system ﬁrmware to query OSPM about interfaces and features that are supported by the
host operating system. The usage and implementation model for this method is as follows:
• The _OSI method is implemented within the operating system.
• OSI is called by the ﬁrmware AML code, usually during initialization (such as via _INI method). Thus, _OSI is
actually an “up-call” from the ﬁrmware AML to the OS – exactly the opposite of other control methods.
• An _OSI invocation by the ﬁrmware is a request to the operating system: “Do you support this inter-
face/feature?”
5.7. Predeﬁned Objects 315Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• The host responds to this _OSI request with a simple yes or no (Ones/Zero, TRUE/FALSE, Sup-
ported/NotSupported).
The _OSI method requires one argument and returns an integer. The argument is a string that contains an optional
ACPI-deﬁned OsVendorString followed by a required FeatureGroupString. The feature group string can be either
ACPI-deﬁned or OS vendor deﬁned.
_OSI cannot and should not be used by the ﬁrmware in an attempt to identify the host operating system; rather, this
method is intended to be used to identify speciﬁc features and interfaces that are supported by the OS. The example
below illustrates this:
\_OSI ("Windows 2009")
In the _OSI invocation above, “Windows” is the OsVendorString, and “2009” is the vendor-deﬁned FeatureGroup-
String. A return value of TRUE (Ones) from this call does NOT indicate that the executing operating system is
Windows. It simply indicates that the actual OS conforms to “Windows 2009” features and interfaces, and is thus
compatible with Windows 2009. ACPI implementations other than Windows often reply TRUE to all Windows _OSI
requests.
The OsVendorString should always be accompanied by a FeatureGroupString. However, the OsVendorString itself
is optional and can be omitted if the feature group string applies to all operating systems. The ACPI-deﬁned feature
group strings may be used in this standalone manner. For feature group strings may be used in this standalone manner.
For example:
\_OSI ("3.0 Thermal Model")
Arg0 – A String containing the optional OS vendor preﬁx (as deﬁned in Table 5-186) and/or the required Feature
Group string (as ACPI-deﬁned in Table 5-187 , or a vendor-deﬁned custom feature/interface string). The optional OS
vendor string is not needed in the case of the ACPI-deﬁned feature group strings.
AnInteger containing a Boolean that indicates whether the requested feature is supported:
0x0 ( Zero ) – The interface, behavior, or feature is not supported
Ones (-1) – The interface, behavior, or feature is supported. Note: The value of Ones is 0xFFFFFFFF in 32-bit mode
(DSDT revision 1) or 0xFFFFFFFFFFFFFFFF in 64-bit mode (DSDT revision 2 and greater).
Table 5.208: Predeﬁned Operating System Vendor String Preﬁxes
Operating System Vendor String Pre-
ﬁxDescription
“FreeBSD” <FeatureGroupString> Free BSD OS features/interfaces
“HP-UX” <FeatureGroupString> HP Unix Operating Environment OS features/interfaces
“Linux” <FeatureGroupString> GNU/Linux Operating system OS features/interfaces
“OpenVMS” <FeatureGroupString> HP OpenVMS Operating Environment OS features/interfaces
“Windows” <FeatureGroupString> Microsoft Windows OS features/interfaces
Table 5.209: Standard ACPI-Deﬁned Feature Group Strings
Feature Group String Description
“Module Device” OSPM supports the declaration of module device (ACPI0004) in the
namespace and will enumerate objects under the module device scope.
“Processor Device” OSPM supports the declaration of processors in the namespace using the
ACPI0007 processor device HID.
5.7. Predeﬁned Objects 316Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.209 – continued from previous page
“3.0 Thermal Model” OSPM supports the extensions to the ACPI thermal model in Revision
3.0.
“Extended Address Space Descriptor” OSPM supports the Extended Address Space Descriptor
“3.0 _SCP Extensions” OSPM evaluates _SCP with the additional acoustic limit and power limit
arguments deﬁned in ACPI 3.0.
“Processor Aggregator Device” OSPM supports the declaration of the processor aggregator device in the
namespace using the ACPI000C processor aggregator device HID.
OSPM may indicate support for multiple OS interface / behavior strings if the operating system supports the behaviors.
For example, a newer version of an operating system may indicate support for strings from all or some of the prior
versions of that operating system.
_OSI provides the platform with the ability to support new operating system versions and their associated features
when they become available. OSPM can choose to expose new functionality based on the _OSI argument string. That
is, OSPM can use the strings passed into _OSI to ensure compatibility between older platforms and newer operating
systems by maintaining known compatible behavior for a platform. As such, it is recommended that _OSI be evaluated
by the \_SB.INI control method so that platform compatible behavior or features are available early in operating system
Since feature group functionality may be dependent on OSPM implementation, it may be required that OS vendor-
deﬁned strings be checked before feature group strings.
Platform developers should consult OS vendor speciﬁc information for OS vendor deﬁned strings representing a set
of OS interfaces and behaviors. ACPI deﬁned strings representing an operating system and an ACPI feature group are
listed in the following tables.
5.7.2.1 _OSI Examples
Use of standard ACPI-deﬁned feature group strings ::
Scope (_SB)
{
Name (PAD1, 0)
Name (MDEV, 0)
Method (_INI)
{
If (CondRefOf (\_OSI) // Ensure \_OSI exists in the OS
{
If (\_OSI ("Processor Aggregator Device")
{
Store (1, PAD1)
}
If (\_OSI ("Module Device")
{
// Expose PCI Root Bridge under Module Device -
// OS support Module Device
Store (0, MDEV1)
Loadtable ("OEM1", "OEMID", "Table1")
}
Else
{
// Expose PCI Root Bridge under \\_SB -
// OS does not support Module Device
Store (1, MDEV1)

{
{
{
{
}
{
}
Else
{
5.7. Predeﬁned Objects 317Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Loadtable ("OEM2", "OEMID", "Table2")
}
}
}
}
Use of OS vendor-deﬁned feature group strings :
//
// In this example, "Windows" isthe OsVendorString, andthe year strings
// (2009, 2012, and2105) are the vendor-defined FeatureGroupStrings
//
{
Name (OSYS, 0x7D0) // Type of OS indicating supported features
{
If (CondRefOf (\_OSI) // Ensure \_OSI exists inthe OS
{
If (\_OSI ("Windows 2009")
{
Store (0x7D1, OSYS)
}
If (\_OSI ("Windows 2012")
{
}
If (\_OSI ("Windows 2015")
{
}
}
}
}
5.7.3 \_OS (OS Name Object)
This predeﬁned object evaluates to a string that identiﬁes the operating system. In robust OSPM implementations,
\_OS evaluates differently for each OS release. This may allow AML code to accommodate differences in OSPM
implementations. This value does not change with different revisions of the AML interpreter.
None
AString containing the operating system name.
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5.7.4 \_REV (Revision Data Object)
This predeﬁned object evaluates to an Integer (DWORD) representing the revision of the ACPI Speciﬁcation imple-
mented by the speciﬁed \_OS.
None
AnInteger representing the revision of the currently executing ACPI implementation.
1. Only ACPI 1 is supported, only 32-bit integers.
2. ACPI 2 or greater is supported. Both 32-bit and 64-bit integers are supported.
Actual integer width depends on the revision of the DSDT (revision < 2 means 32-bit. >= 2 means 64-bit).
Other values - Reserved
5.7.5 \_DLM (DeviceLock Mutex)
This object appears in a device scope when AML access to the device must be synchronized with the OS environment.
It is used in conjunction with a standard Mutex object. With _DLM, the standard Mutex provides synchronization
within the AML environment as usual, but also synchronizes with the OS environment.
_DLM evaluates to a package of packages, each containing a reference to a Mutex and an optional resource template
protected by the Mutex, If only the Mutex name is speciﬁed, then the sharing rules (i.e. which resources are protected
by the lock) are deﬁned by a predeﬁned contract between the AML and the OS device driver. If the resource template
is speciﬁed, then only those resources within the resource template are protected.
None
A variable-length Package containing sub- packages of Mutex References and resource templates. The resource
template in each subpackage is optional.
Return Value Information :
Package {
DeviceLockInfo [0] // **Package**
. . .
DeviceLockInfo [n] **// Package **
}
Each variable-length DeviceLockInfo sub- Package contains either one element or 2 elements, as described below:
Package {
DeviceLockMutex // **Reference **to a Mutex object
Resources // **Buffer**or**Reference **(Resource Template)
}
5.7. Predeﬁned Objects 319Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 5.210: DeviceLockInfo Package Values
Element Object Type Description
DeviceLockMutex Reference A reference to the mutex that is to be shared be-
tween the AML code and the host operating sys-
tem.
Resources Buffer* (or reference to a Buffer) Optional. Contains a Resource Template that de-
scribes the resources that are to be protected by
the Device Lock Mutex.
Example :
Device (DEV1)
{
Mutex (MTX1, 0)
Name (RES1, ResourceTemplate ()
{
I2cSerialBusV2 (0x0400, DeviceInitiated, 0x00001000,
AddressingMode10Bit, " \\_SB.DEV1",
0, ResourceConsumer, I2C1)
})
Name (_DLM, Package (1)
{
Package (2)
{
MTX1,
RES1
}
})
}
Device (DEV2)
{
Mutex (MTX2, 0)
Mutex (MTX3, 0)
Name (_DLM, Package (2)
{
{
\\DEV2.MTX2,
ResourceTemplate ()
{
AddressingMode10Bit, " \\_SB.DEV2",
0, ResourceConsumer, I2C2)
}
},
Package (1) // Optional resource notneeded
{
\\DEV2.MTX3
}
})
}
5.7. Predeﬁned Objects 320Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
5.8 System Conﬁguration Objects
5.8.1 \_PIC Method
The \_PIC optional method is used to report to the platform runtime ﬁrmware the current interrupt model used by the
OS. This control method returns nothing. The argument passed into the method signiﬁes the interrupt model OSPM
has chosen, PIC mode, APIC mode, or SAPIC mode. Notice that calling this method is optional for OSPM. If the
platform CPU architecture supports PIC mode and the method is never called, the platform runtime ﬁrmware must
assume PIC mode. It is important that the platform runtime ﬁrmware save the value passed in by OSPM for later use
during wake operations.
Arg0 – An Integer containing a code for the current interrupt model:
0 - PIC mode
1 - APIC mode
2 - SAPIC mode
None
5.8. System Conﬁguration Objects 321CHAPTER
SIX
DEVICE CONFIGURATION
This section speciﬁes the objects OSPM uses to conﬁgure devices. There are three types of conﬁguration objects:
• Device identiﬁcation objects associate platform devices with Plug and Play IDs.
• Device conﬁguration objects declare and conﬁgure hardware resources and characteristics for devices enumer-
ated via ACPI.
• Device insertion and removal objects provide mechanisms for handling dynamic insertion and removal of de-
vices.
There are two types of Device objects:
• A Full Device Descriptor, which contains the complete description of a devices that cannot be discovered
through any other standard Bus enumeration mechanism. This type of Device object is enumerated by the
ACPI subsystem (OSPM), and contains a Hardware ID object (_HID).
• An Agumented Device Descriptor, which contains additional device information that is not provided from the
Device itself, yet is needed by the Device or Bus driver in order to properly conﬁgure and use the device. This
type of device is enumerated by a bus-speciﬁc enumeration mechanism, and OSPM uses the Address (_ADR)
to match the ACPI Device object in the Namespace to the device discovered through bus enumeration.
This section also deﬁnes the ACPI device-resource descriptor formats. Device-resource descriptors are used as param-
eters by some of the device conﬁguration objects.
6.1 Device Identiﬁcation Objects
Device identiﬁcation objects associate each platform device with a Plug and Play device ID for each device. All the
device identiﬁcation objects are listed in the table below:
Table 6.1: Device Identiﬁcation Objects
Object Description
_ADR Object that evaluates to a device’s address on its parent bus.
_CID Object that evaluates to a device’s Plug and Play-compatible ID list.
_CLS Object that evaluates to a package of coded device-class information.
_DDN Object that associates a logical software name (for example, COM1) with a device.
_HID Object that evaluates to a device’s Plug and Play hardware ID.
_HRV Object that evaluates to an integer hardware revision number.
_MLS Object that provides a human readable description of a device in multiple languages.
_PLD Object that provides physical location description information.
_SUB Object that evaluates to a device’s Plug and Play subsystem ID.
_SUN Object that evaluates to the slot-unique ID number for a slot.
322Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.1 – continued from previous page
_STR Object that contains a Unicode identiﬁer for a device. Can also be used for thermal zones.
_UID Object that speciﬁes a device’s unique persistent ID, or a control method that generates it.
For any device that is on a non-enumerable type of bus (for example, an ISA bus), OSPM enumerates the devices’
identiﬁer(s) and the ACPI system ﬁrmware must supply an _HID object (plus one or more optional objects such as
_CID, _CLS, _HRV , _SUB) for each device to enable OSPM to do that. For devices on an enumerable type of bus,
such as a PCI bus, the ACPI system must identify which device on the enumerable bus is identiﬁed by a particular
address; the ACPI system ﬁrmware must supply an _ADR object for each device to enable this. A device object must
contain either an _HID object or an _ADR object, but must not contain both.
If any of these objects are implemented as control methods, these methods may depend on operation regions. Since
the control methods may be evaluated before an operation region provider becomes available, the control method must
be structured to execute in the absence of the operation region provider. (_REG methods notify the platform runtime
ﬁrmware of the presence of operation region providers.) When a control method cannot determine the current state of
the hardware due to a lack of operation region provider, it is recommended that the control method should return the

condition that was true at the time that control passed from the platform boot ﬁrmware to the OS. (The control method
should return a default, boot value).
6.1.1 _ADR (Address)
This object is used to supply OSPM with the address of a device on its parent bus. An _ADR object must be used
when specifying the address of any device on a bus that has a standard enumeration algorithm (see Conﬁguration and
“Plug and Play” , for the situations when these devices do appear in the ACPI namespace). The _ADR object is valid
only within an Augmented Device Descriptor.
None
AnInteger containing the address of the device
An _ADR object can be used to provide capabilities to the speciﬁed address even if a device is not present.
This allows the system to provide capabilities to a slot on the parent bus.
OSPM infers the parent bus and segment from the location of the _ADR object’s device package in the
ACPI namespace. For more information about the positioning of device packages in the ACPI namespace,
seeDevice (Declare Device Package)
_ADR object information must be static and can be deﬁned for the following bus types listed in ADR
Object Address Encodings .
Table 6.2: ADR Object Address Encodings
BUS Address Encoding
EISA EISA slot number 0-F
Floppy Bus Drive select values used for programming the ﬂoppy controller to access the
speciﬁed INT13 unit number. The _ADR Objects should be sorted based on
drive select encoding from 0-3.
6.1. Device Identiﬁcation Objects 323Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.2 – continued from previous page
I3C Bits [63:52] - Reserved
Bits [51:48] - Master Instance
Bits [47:0] - I3C Device Provisional ID, following encoding deﬁned in the MIPI
Speciﬁcation for I3C.
If an I3C device supports a static address instead of a Provisional ID, then bits
[47:7] are Reserved (zero), and bits [6:0] are the 7-bit static address.
IDE Controller 0-Primary Channel, 1-Secondary Channel
IDE Channel 0-Master drive, 1-Slave drive
Intel® High Deﬁnition Audio High word - SDI (Serial Data In) ID of the codec that contains the function
group. Low word - Node ID of the function group.
PCI High word-Device #, Low word-Function #. (for example, device 3, function
2 is 0x00030002). To refer to all the functions on a device #, use a function
number of FFFF).
PCMCIA Socket #; 0-First Socket
PC CARD Socket #; 0-First Socket
Serial ATA SATA Port: High word–Root port #, Low word–port number off of a SATA port
multiplier, or 0xFFFF if no port multiplier attached. (For example, root port
2 would be 0x0002FFFF. If instead a port multiplier had been attached to root
port 2, the ports connected to the multiplier would be encoded 0x00020000,
0x00020001, etc.) The value 0xFFFFFFFF is reserved.
SMBus Lowest Slave Address
USB Root HUB Only one child of the host controller. It must have an _ADR of 0. No other
children or values of _ADR are allowed.
USB Ports Port number (1-n)
SDIO Bus High word - Slot number (0-First Slot) Low word - Function number (see SD
speciﬁcation for deﬁnitions.)
NVDIMM NFIT Device handle as deﬁned by the NVDIMM Region Mapping Structure
6.1.2 _CID (Compatible ID)
This optional object is used to supply OSPM with a device’s Plug and Play-Compatible Device ID. Use _CID objects
when a device has no other deﬁned hardware standard method to report its compatible IDs. The _CID object is valid
only within a Full Device Descriptor. An _HID object must also be present.
None
AnInteger orString containing a single CID oraPackage containing a list of CIDs
A _CID object evaluates to either:
• A single Compatible Device ID
• A package of Compatible Device IDs for the device – in the order of preference, highest preference
ﬁrst.
Each Compatible Device ID must be either:
• A valid HID value (a 32-bit compressed EISA type ID or a string such as “ACPI0004”).
• A string that uses a bus-speciﬁc nomenclature. For example, _CID can be used to specify the PCI
ID. The format of a PCI ID string is one of the following:
6.1. Device Identiﬁcation Objects 324Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
"PCI\CC_ccss"
"PCI\CC_ccsspp"
"PCI\VEN_vvvv&DEV_dddd&SUBSYS_ssssssss&REV_rr"
"PCI\VEN_vvvv&DEV_dddd&SUBSYS_ssssssss"
"PCI\VEN_vvvv&DEV_dddd&REV_rr"
"PCI\VEN_vvvv&DEV_dddd"
Where:
cc - hexadecimal representation of the Class Code byte
ss - hexadecimal representation of the Subclass Code byte
pp - hexadecimal representation of the Programming Interface byte
vvvv - hexadecimal representation of the Vendor ID
dddd - hexadecimal representation of the Device ID
ssssssss - hexadecimal representation of the Subsystem ID
rr - hexadecimal representation of the Revision byte
A compatible ID retrieved from a _CID object is only meaningful if it is a non-NULL value.
Example ASL :
Device (XYZ) {
Name (_HID, EISAID ("PNP0303")) // PC Keyboard Controller
Name (_CID, EISAID ("PNP030B"))
}
6.1.3 _CLS (Class Code)
This object is used to supply OSPM with the PCI-deﬁned base-class, sub-class and programming interface for a device.
This object is optional. However, it may be useful for loading generic drivers on hardware that is compatible with PCI
-deﬁned device classes, but that is not implemented on the PCI bus (and is therefore enumerated by ACPI.)
None
APackage containing the PCI -deﬁned class information as a list of Integers :
Package(3) {<base-class code>, <sub-class code>, <Programming Interface code>
˓→}
A list of available class codes and programming interface codes is provided by the PCI SIG. See “PCI Code and
ID Assignment Speciﬁcation”, available from “Links to ACPI-Related Documents” ( http://ueﬁ.org/acpi ) under the
heading “PCI Code and ID Assignment Speciﬁcation
Example ASL:
Device(SATA) //AHCI- compatible SATA controller
{
Name(_HID, "...")
Name(_CLS, Package (3)
{
0x01, // Base Class (01h == Mass Storage)
0x06, // Sub-Class (06h == SATA)
0x01, // Programming Interface (01h == AHCI)
6.1. Device Identiﬁcation Objects 325Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
})
Name(_CRS, ResourceTemplate()
{
... // AHCI-defined system resources
})
}
6.1.4 _DDN (DOS Device Name)
This object is used to associate a logical name (for example, COM1) with a device. This name can be used by
applications to connect to the device.
None
AString containing the DOS device name
6.1.5 _HID (Hardware ID)
This object is used to supply OSPM with the device’s PNP ID or ACPI ID.
See also:
PNP ID and ACPI ID Registry is at http://www.ueﬁ.org/PNP_ACPI_Registry .
When describing a platform, use of any _HID objects is optional. However, a _HID object must be used to describe
any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the
device ID. For example, devices on an ISA bus are enumerated by OSPM. Use the _ADR object to describe devices
enumerated by bus enumerators other than OSPM. The _HID object is valid only within a Full Device Descriptor.
None
AnInteger orString containing the HID
A _HID object evaluates to either a numeric 32-bit compressed EISA type ID or a string. If a
string, the format must be an alphanumeric PNP or ACPI ID with no asterisk or other leading
A valid PNP ID must be of the form “AAA####” where A is an uppercase letter and # is a
hex digit. A valid ACPI ID must be of the form “NNNN####” where N is an uppercase letter
or a digit (‘0’-‘9’) and # is a hex digit. This speciﬁcation reserves the string “ACPI” for use
only with devices deﬁned herein. It further reserves all strings representing 4 HEX digits for
exclusive use with PCI-assigned Vendor IDs.
Name (_HID, EISAID ("PNP0C0C")) // Control-Method Power Button
Name (_HID, EISAID ("INT0800")) // Firmware Hub
Name (_HID, "ACPI0003") // AC adapter device
Name (_HID, "MSFT0003") // Vendor-defined device
Name (_HID, "80860003") // PCI-assigned device identifier
6.1. Device Identiﬁcation Objects 326Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.1.6 _HRV (Hardware Revision)
This object is used to supply OSPM with the device’s hardware revision. The use of _HRV is optional.
None
AnInteger (DWORD) containing the hardware revision number
Name (_HRV, 0x0003) // Revision number 3 of this hardware device
6.1.7 _MLS (Multiple Language String)
The _MLS object provides OSPM a human readable description of a device in multiple languages. This information
may be provided to the end user when the OSPM is unable to get any other information about this device. Although
this functionality is also provided by the _STR object, _MLS expands that functionality and provides vendors with
the capability to provide multiple strings in multiple languages. The _MLS object evaluates to a package of packages.

None
Each sub-package consists of a Language identiﬁer and corresponding unicode string for a given locale. Specifying a
language identiﬁer allows OSPM to easily determine if support for displaying the Unicode string is available. OSPM
can use this information to determine whether or not to display the device string, or which string is appropriate for a
user’s preferred locale.
It is assumed that OSPM will always support the primary English locale to accommodate English embedded in a
non-English string, such as a brand name.
If OSPM doesn’t support the speciﬁc sub-language ID it may choose to use the primary language ID for displaying
device text.
None
A variable-length Package containing a list of language descriptor Packages as described below.
Package {
LanguageDescriptor[0] // Package
LanguageDescriptor[n] // Package
}
Each Language Descriptor sub-Package contains the elements described below:
Package {
LanguageId // String
UnicodeDescription // Buffer
}
LanguageId is a string identifying the language. This string follows the format speciﬁed in the Internet RFC 3066
document (Tags for the Identiﬁcation of Languages). In addition to supporting the existing strings in RFC 3066, the
table below lists aliases that are also supported.
6.1. Device Identiﬁcation Objects 327Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.3: Additional Language ID Alias Strings
RFC String Supported Alias String
UnicodeDescription is a Buffer containing a Unicode (UTF-16) string. This string contains the language-speciﬁc
description of the device corresponding to the LanguageID. The Unicode() ASL macro can be used to create this
Buffer.
Example :
Name (_ADR, 0x00020001)
Name ( \_MLS, Package(){(2){"en", Unicode("ACME super DVD controller")}})
}
6.1.8 _PLD (Physical Location of Device)
This optional object is a method that conveys to OSPM a general description of the physical location of a device’s
external connection point. The _PLD may be child object for any ACPI Namespace object the system wants to
describe. This information can be used by system software to describe to the user which speciﬁc connector or device
input mechanism may be used for a given task or may need user intervention for correct operation. The _PLD should
only be evaluated when its parent device is present as indicated by the device’s presence mechanism (i.e. _STA or
other)
An externally exposed device connection point can reside on any surface of a system’s housing. The respective surfaces
of a system’s housing are identiﬁed by the “Panel” ﬁeld (described below). The _PLD method returns data to describe
the location of where the device’s connection point resides and a Shape (described below) that may be rendered at
that position. One physical device may have several connection points. A _PLD describes the offset and rotation of a
single device connection point from an “origin” that resides in the lower left hand corner of its Panel.
All Panel references (Top, Bottom, Right, Left, etc.) are interpreted as though the user is facing the front of the system.
For handheld mobile devices, the front panel is the one holding the display screen, and its origin is in the lower-left
corner when the display is viewed in the Portrait orientation. For example, the Right Panel is the right side of the
system as viewed from the front.
All “origin” references for a Panel are interpreted as its lower left corner when the user is facing the respective Panel.
The Top Panel shall be viewed with the system is viewed resting on its Front Panel, and the Bottom Panel shall be
viewed with the system resting on its Back Panel. All other Panels shall be viewed with the system resting on its
Bottom Panel. See System Panel and Panel Origin Positions for more information.
The data bits also assume that if the system is capable of opening up like a laptop that the device may exist on the base
of the laptop system or on the lid. In the case of the latter, the “Lid” bit (described below) should be set indicating the
device connection point is on the lid. If the device is on the lid, the description describes the device’s connection point
location when the system is opened with the lid up. If the device connection point is not on the lid, then the description
describes the device’s connection point location when the system with the lid closed.
6.1. Device Identiﬁcation Objects 328Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 6.1: System Panel and Panel Origin Positions
Fig. 6.2: Laptop Panel and Panel Origin Positions
To render a view of a system Panel, all _PLDs that deﬁne the same Panel and Lid values are collected. The _PLDs
are then sorted by the value of their Order ﬁeld and the view of the panel is rendered by drawing the shapes of each
connection point (in their correct Shape, Color, Horizontal Offset, Vertical Offset, Width, Height, and Orientation)
starting with all Order = 0 _PLDs ﬁrst. Refer to PLD Back Panel Rendering for an example.
The location of a device connection point may change as a result of the system connecting or disconnecting to a
docking station or a port replicator. As such, Notify event of type 0x09 will cause OSPM to re-evaluate the _PLD object
residing under the particular device notiﬁed. If a platform is unable to detect the change of connecting or disconnecting
to a docking station or port replicator, a _PLD object should not be used to describe the device connection points that
will change location after such an event.
None
A variable-length Package containing a list of Buffers
This method returns a package containing a single or multiple buffer entries. At least one buffer entry must be returned
using the bit deﬁnitions below.
6.1. Device Identiﬁcation Objects 329Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.4: _PLD Buffer 0 Return Value
Name Deﬁnition DWORD Bit Offset
(DWORD)Bit Offset
(Buffer)Length
(bits)
Revision The current Revision is 0x2 0 0 0 7
Ignore Color If this bit is set, the Color ﬁeld is ig-
nored, as the color is unknown.0 7 7 1
Color
24-bit RGB value for the color of the
device connection point:
Bits [7:0]=red value
Bits [15:8]=green value
Bits [23:16]=blue value0 8 8 24
Width Width of the widest point of the device
connection point, in millimeters1 0 32 16
Height Height of the tallest point of the device
connection point, in millimeters1 16 48 16
User Visible Set if the device connection point can
be seen by the user without disassem-
bly.2 0 64 1
Dock Set if the device connection point re-
sides in a docking station or port repli-
cator.2 1 65 1
Lid Set if this device connection point re-
sides on the lid of laptop system.2 2 66 1
Panel
Describes which panel surface of the
system’s housing the device
connection point resides on:
0 - Top
1 - Bottom
2 - Left
3 - Right
4 - Front
5 - Back
6 - Unknown (Vertical Position and
Horizontal Position will be ignored)2 3 67 3
Vertical Position
on the panel
where the device
connection point
resides0 - Upper
1 - Center
2 - Lower2 6 70 2
Horizontal Posi-
tion on the panel
resides.0 - Left
1 - Center
2 - Right2 8 72 2
6.1. Device Identiﬁcation Objects 330Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.4 – continued from previous page
Shape
Describes the shape of the device
connection point. The Width and
Height ﬁelds may be used to distort a
shape, e.g. A Round shape will look
like an Oval shape if the Width and
Height are not equal. And a Vertical
Rectangle or Horizontal Rectangle
may look like a square if Width and
Height are equal. See Default Shape
Deﬁnitions :
0 - Round
1 - Oval
2 - Square
3 - Vertical Rectangle
4 - Horizontal Rectangle
5 - Vertical Trapezoid
6 - Horizontal Trapezoid
7 - Unknown - Shape rendered as a
Rectangle with dotted lines
8 - Chamfered
15:9 - Reserved2 10 74 4
Group Orienta-
tionif Set, indicates vertical grouping, oth-
erwise horizontal is assumed.2 14 78 1
Group Token Unique numerical value identifying a
group.2 15 79 8
Group Position Identiﬁes this device connection
point’s position in the group (i.e. 1st,
2nd)2 23 87 8
Bay Set if describing a device in a bay or if
device connection point is a bay.2 31 95 1
Ejectable Set if the device is ejectable. Indicates
ejectability in the absence of _EJx ob-
jects.3 0 96 1
OSPM Ejection
requiredOSPM Ejection required: Set if OSPM
needs to be involved with ejection pro-
cess. User-operated physical hardware
ejection is not possible.3 1 97 1
Cabinet Number For single cabinet system, this ﬁeld is
always 0.3 2 98 8
Card Cage Num-
berFor single card cage system, this ﬁeld
is always 0.3 10 106 8
Reference if Set, this _PLD deﬁnes a “reference”
shape that is used to help orient the
user with respect to the other shapes
when rendering _PLDs.3 18 114 1

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Rotation
Rotates the Shape clockwise in 45
degree steps around its origin where:
0 - 0°
1 - 45°
2 - 90°
3 - 135°
4 - 180°
5 - 225°
6 - 270°
7 - 315°3 19 115 4
Order
Identiﬁes the drawing order of the
connection point described by a
_PLD:
Order = 0 connection points are drawn
before Order = 1 connection points.
Order = 1 before Order = 2, and so on.
Order = 31 connection points are
drawn last.
Order should always start at 0 and be
consecutively assigned.3 23 119 5
Reserved Reserved, must contain a value of 0. 3 28 124 4
Vertical Offset Offset of Shape Origin from Panel Ori-
gin (0.1 mm / 100 microns). A value of
0xFFFFFFFF indicates that this ﬁeld
is not supplied.4 0 128 16
Horizontal Offset Offset of Shape Origin from Panel Ori-
is not supplied.4 16 144 16
Note: All additional buffer entries returned may contain OEM-speciﬁc data, but must begin in a {GUID, data} pair.
These additional data may provide complimentary physical location information speciﬁc to certain systems or class of
machines.
6.1. Device Identiﬁcation Objects 332Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 6.3: Default Shape Deﬁnitions
Buffers 1–N Return Value (Optional) :
• Buffer 1 Bit [127:0] - GUID 1
• Buffer 2 Bit [127:0] - Data 1
• Buffer 3 Bit [127:0] - GUID 2
• Buffer 4 Bit [127:0] - Data 2
• etc.
PLD Back Panel Rendering provides an example of a rendering of the external device connection points that may
be conveyed to the user by _PLD information. Note that three _PLDs (System Back Panel, Power Supply, and
Motherboard (MB) Connector Area) that are associated with the System Bus tree (_SB) object. Their Reference
ﬂag is set indicating that are used to provide the user with visual queues for identifying the relative locations of the
other device connection points.
The connection points (C1 through C16) are deﬁned by _PLD objects found in the System bus tree.
The following connection points all have their Panel and Lid ﬁelds set to Back and 0, respectively. And the Reference
ﬂag of the System Back Panel, Power Supply, and MB Connector Area connection points are set to 1. in this example
are used to render PLD Back Panel Rendering :
Table 6.5: PLD Back Panel Example Settings
Name Ignore
ColorR G B Width Height VOff HOff Shape Notation Goup Po-
sitionRotation
Back
PanelYes 0 0 0 203 432 0 0 V Rect 1 0
MB
Conn
areaYes 0 0 0 45 156 159 13 V Rect 2 0
6.1. Device Identiﬁcation Objects 333Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.5 – continued from previous page
Power
Sup-
plyYes 0 0 0 152 890 330 13 H Rect 2 0
USB
Port 1No 0 0 0 13 5 222 16 H Rect C1 3 90
USB
Port 2No 0 0 0 13 5 222 25 H Rect C2 3 90
USB
Port 3No 0 0 0 13 5 222 35 H Rect C3 3 90
USB
Port 4No 0 0 0 13 5 222 45 H Rect C4 3 90
USB
Port 5No 0 0 0 13 5 201 16 H Rect C5 3 90
USB
Port 6No 0 0 0 13 5 201 25 H Rect C6 3 90
Ethernet No 0 0 0 16 17 201 35 V Rect C7 3 90
Audio
1No FF FF FF 13 13 195 15 Round C8 3 90
Audio
2No 151 247 127 13 13 195 29 Round C9 3 90
Audio
3No 0 0 0 13 13 195 48 Round C10 3 90
SPDIF No 0 0 0 11 13 176 18 V Trap C11 3 90
Audio
4No 0 FF 0 13 13 177 29 Round C12 3 90
Audio
5No 0 0 FF 13 13 177 43 Round C13 3 90
SATA No 0 0 0 24 9 309 16 H Rect C14 3 90
1394 No 0 0 0 11 16 289 25 H Trap C15 3 0
Coax No 0 0 0 16 16 284 14 Round C16 3 90
PCI 1 No 0 0 0 102 13 13 13 H Rect 1 3 0
PCI 2 No 0 0 0 102 13 33 13 H Rect 2 3 0
PCI 3 No 0 0 0 102 13 54 13 H Rect 3 3 0
PCI 4 No 0 0 0 102 13 75 13 H Rect 4 3 0
PCI 5 No 0 0 0 102 13 95 13 H Rect 5 3 0
PCI 6 No 0 0 0 102 13 116 13 H Rect 6 3 0
PCI 7 No 0 0 0 102 13 137 13 H Rect 7 3 0
Note that the origin is in the lower left hand corner of the Back Panel, where positive Horizontal and Vertical Offset
values are to the right and up, respectively.
6.1.9 _SUB (Subsystem ID)
This object is used to supply OSPM with the device’s Subsystem ID. The use of _SUB is optional.
None
A String containing the SUB
6.1. Device Identiﬁcation Objects 334Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 6.4: PLD Back Panel Rendering
6.1. Device Identiﬁcation Objects 335Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A _SUB object evaluates to a string and the format must be a valid PNP or ACPI ID with no
asterisk or other leading characters.
See the deﬁnition of _HID ( _HID (Hardware ID) ) for the deﬁnition of PNP and ACPI ID
strings.
Name (_SUB, "MSFT3000") // Vendor-defined subsystem
6.1.10 _STR (String)
The _STR object evaluates to a Unicode string that describes the device or thermal zone. It may be used by an OS to
provide information to an end user. This information is particularly valuable when no other information is available.
None
ABuffer containing a Unicode string that describes the device
Name (_STR, Unicode ("ACME super DVD controller"))
}
Then, when all else fails, an OS can use the info included in the _STR object to describe the hardware to the user.
6.1.11 _SUN (Slot User Number)
_SUN is an object that evaluates to the slot-unique ID number for a slot. _SUN is used by OSPM UI to identify
slots for the user. For example, this can be used for battery slots, PCI slots, PCMCIA slots, or swappable bay slots to
inform the user of what devices are in each slot. _SUN evaluates to an integer that is the number to be used in the user
None
AnInteger containing the slot’s unique ID
The _SUN value is required to be unique among the slots of the same type. It is also recommended that
this number match the slot number printed on the physical slot whenever possible.
6.1. Device Identiﬁcation Objects 336Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.1.12 _UID (Unique ID)
This object provides OSPM with a logical device ID that does not change across reboots. This object is optional,
but is required when the device has no other way to report a persistent unique device ID. The _UID must be unique
across all devices with either a common _HID or _CID. This is because a device needs to be uniquely identiﬁed to
the OSPM, which may match on either a _HID or a _CID to identify the device. The uniqueness match must be true
regardless of whether the OSPM uses the _HID or the _CID. OSPM typically uses the unique device ID to ensure that
the device-speciﬁc information, such as network protocol binding information, is remembered for the device even if
its relative location changes. For most integrated devices, this object contains a unique identiﬁer.
In general, a _UID object evaluates to either a numeric value or a string. However, when deﬁning an object with an
_HID of ACPI0007 (processor deﬁnition objects), the _UID object must return an integer. This integer is used as
an identiﬁer in the MADT, PPTT and other tables to connect non-enumerable devices to a processor object. When a
string is used in these cases, there is no mechanism for connecting these devices.
None
AnInteger orString containing the Unique ID
6.2 Device Conﬁguration Objects
This section describes objects that provide OSPM with device speciﬁc information and allow OSPM to conﬁgure
device operation and resource utilization.
OSPM uses device conﬁguration objects to conﬁgure hardware resources for devices enumerated via ACPI. Device
conﬁguration objects provide information about current and possible resource requirements, the relationship between
shared resources, and methods for conﬁguring hardware resources.
Note: these objects must only be provided for devices that cannot be conﬁgured by any other hardware standard such
as PCI, PCMCIA, and soon.
When OSPM enumerates a device, it calls _PRS to determine the resource requirements of the device. It may also call
_CRS to ﬁnd the current resource settings for the device. Using this information, the Plug and Play system determines
what resources the device should consume and sets those resources by calling the device’s _SRS control method.
In ACPI, devices can consume resources (for example, legacy keyboards), provide resources (for example, a propri-
etary PCI bridge), or do both. Unless otherwise speciﬁed, resources for a device are assumed to be taken from the
nearest matching resource above the device in the device hierarchy.
Some resources, however, may be shared amongst several devices. To describe this, devices that share a resource
(resource consumers) must use the extended resource descriptors (0x7-0xA) described in Large Resource Data Type .
These descriptors point to a single device object (resource producer) that claims the shared resource in its _PRS. This

allows OSPM to clearly understand the resource dependencies in the system and move all related devices together if
it needs to change resources. Furthermore, it allows OSPM to allocate resources only to resource producers when
devices that consume that resource appear.
The device conﬁguration objects are listed in the table below.
Table 6.6: Device Conﬁguration Objects
6.2. Device Conﬁguration Objects 337Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.6 – continued from previous page
_CDM Object that speciﬁes a clock domain for a processor.
_CRS Object that speciﬁes a device’s current resource settings, or a control method that generates such
an object.
_DIS Control method that disables a device.
_DMA Object that speciﬁes a device’s current resources for DMA transactions.
_DSD Object that evaluates to device speciﬁc information
_FIX Object used to provide correlation between the ﬁxed-hardware register blocks deﬁned in the
FADT and the devices that implement these ﬁxed-hardware registers.
_GSB Object that provides the Global System Interrupt Base for a hot-plugged I/O APIC device.
_HMA Object that provides updated HMAT structures.
_HPP Object that speciﬁes the cache-line size, latency timer, SERR enable, and PERR enable values to
be used when conﬁguring a PCI device inserted into a hot-plug slot or initial conﬁguration of a
PCI device at system boot.
_HPX Object that provides device parameters when conﬁguring a PCI device inserted into a hot-plug
slot or initial conﬁguration of a PCI device at system boot. Supersedes _HPP.
_MAT Object that evaluates to a buffer of Interrupt Controller Structures.
_OSC An object OSPM evaluates to convey speciﬁc software support / capabilities to the platform al-
lowing the platform to conﬁgure itself appropriately.
_PRS An object that speciﬁes a device’s possible resource settings, or a control method that generates
such an object.
_PRT Object that speciﬁes the PCI interrupt routing table.
_PXM Object that speciﬁes a proximity domain for a device.
_SLI Object that provides updated distance information for a system locality.
_SRS Control method that sets a device’s settings.
6.2.1 _CDM (Clock Domain)
This optional object conveys the processor clock domain to which a processor belongs. A processor clock domain
is a unique identiﬁer representing the hardware clock source providing the input clock for a given set of processors.
This clock source drives software accessible internal counters, such as the Time Stamp Counter, in each processor.
Processor counters in the same clock domain are driven by the same hardware clock source. In multi-processor plat-
forms that utilize multiple clock domains, such counters may exhibit drift when compared against processor counters
on different clock domains.
The _CDM object evaluates to an integer that identiﬁes the device as belonging to a speciﬁc clock domain. OSPM
assumes that two devices in the same clock domain are connected to the same hardware clock.
None
AnInteger (DWORD) containing a clock domain identiﬁer.
In the case the platform does not convey any clock domain information to OSPM via the SRAT or the _CDM object,
OSPM assumes all logical processors to be on a common clock domain. If the platform deﬁnes _CDM object under
a logical processor then it must deﬁne _CDM objects under all logical processors whose clock domain information is
not provided via the SRAT.
6.2. Device Conﬁguration Objects 338Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.2.2 _CRS (Current Resource Settings)
This required object evaluates to a byte stream that describes the system resources currently allocated to a device.
Additionally, a bus device must supply the resources that it decodes and can assign to its children devices. If a device
is disabled, then _CRS returns a valid resource template for the device, but the actual resource assignments in the
return byte stream are ignored. If the device is disabled when _CRS is called, it must remain disabled.
The format of the data contained in a _CRS object follows the formats deﬁned in Resource Data Types for ACPI ,
which is a compatible extension of the Plug and Play BIOS Speciﬁcation (see reference below). The resource data
is provided as a series of data structures, with each of the resource data structures having a unique tag or identiﬁer.
The resource descriptor data structures specify the standard PC system resources, such as memory address ranges, I/O
ports, interrupts, and DMA channels.
None
ABuffer containing a resource descriptor byte stream
A link to the Plug and Play BIOS Speciﬁcation can be found at http://ueﬁ.org/acpi under the heading “Plug and Play
BIOS Speciﬁcation.”
Also see the related link on the above website for the Windows Generic Device IDs and Plug and Play BIOS device
type codes .
6.2.3 _DIS (Disable)
This control method disables a device. When the device is disabled, it must not be decoding any hardware resources.
Prior to running this control method, OSPM will have already put the device in the D3 state.
When a device is disabled via _DIS, the _STA control method for this device must return with the Enabled bit (Bit 1)
clear.
None
None
6.2.4 _DMA (Direct Memory Access)
This optional object returns a byte stream in the same format as a _CRS object. _DMA is only deﬁned under devices
that represent buses. It speciﬁes the ranges the bus controller (bridge) decodes on the child-side of its interface. (This
is analogous to the _CRS object, which describes the resources that the bus controller decodes on the parent-side of
its interface.) Any ranges described in the resources of a _DMA object can be used by child devices for DMA or bus
master transactions.
The _DMA object is only valid if a _CRS object is also deﬁned. OSPM must re-evaluate the _DMA object after an
_SRS object has been executed because the _DMA ranges resources may change depending on how the bridge has
been conﬁgured.
If the _DMA object is not present for a bus device, the OS assumes that any address placed on a bus by a child device
will be decoded either by a device on the bus or by the bus itself, (in other words, all address ranges can be used for
DMA).
6.2. Device Conﬁguration Objects 339Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
For example, if a platform implements a PCI bus that cannot access all of physical memory, it has a _DMA object
under that PCI bus that describes the ranges of physical memory that can be accessed by devices on that bus.
A _DMA object is not meant to describe any “map register” hardware that is set up for each DMA transaction. It is
meant only to describe the DMA properties of a bus that cannot be changed without reevaluating the _SRS method.
None
_DMA Example ASL:
Device(BUS0)
{
//
// The _DMA method returns a resource template describing the
// addresses that are decoded on the child side of this
// bridge. The contained resource descriptors thus indicate
// the address ranges that bus masters living below this
// bridge can use to send accesses through the bridge toward a
// destination elsewhere in the system (e.g. main memory).
//
// In our case, any bus master addresses need to fall between
// 0 and 0x80000000 and will have 0x200000000 added as they
// cross the bridge. Furthermore, any child-side accesses
// falling into the range claimed in our _CRS will be
// interpreted as a peer-to-peer traffic and will not be
// forwarded upstream by the bridge.
//
// Our upstream address decoder will only claim one range from
// 0x20000000 to 0x5fffffff in the _CRS. Therefore _DMA
// should return two QWORDMemory descriptors, one describing
// the range below and one describing the range above this
// "peer-to-peer" address range.
//
Method(_DMA, ResourceTemplate()
{
QWORDMemory(
ResourceProducer,
PosDecode, // _DEC
MinFixed, // _MIF
MaxFixed, // _MAF
Prefetchable, // _MEM
ReadWrite, // _RW
0, // _GRA
0, // _MIN
0x1fffffff, // _MAX
0x200000000, // _TRA
0x20000000, // _LEN
,
,
,
)
6.2. Device Conﬁguration Objects 340Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
0, // _GRA
0x60000000, // _MIN
0x7fffffff, // _MAX
,
,
,
)
})
}
6.2.5 _DSD (Device Speciﬁc Data)
This optional object is used to provide device drivers (via OSPM) with additional device properties and information.

//
{
0, // _GRA
0, // _MIN
,
,
,
)
0, // _GRA
,
,
,
)
})
}
_DSD returns a variable-length package containing a list of Device Data Descriptor structures each consisting of a
UUID (see Universally Unique Identiﬁers (UUIDs) ) and a package (Data Structure). The UUID is all that is needed to
deﬁne the Data Structure. The UUID itself may place a restriction based on _HID or the optional _CID, _CLS, _HRV ,
_SUB objects, or _HID and one of those optional objects. However, it also may not place such a restriction.
New UUIDs may be created by OEMs and IHVs or other interface or device governing bodies (e.g. the PCI SIG or
the UEFI Forum), as long as the UUID is different from other published UUIDs.
The list of well-known UUIDs allocated for _DSD and the deﬁnition of data formats associated with them is available
in an auxiliary document hosted on the UEFI Forum: http://www.ueﬁ.org/acpi .
None
A variable-length Package containing a list of Device Data Descriptor structures as described below.
Return Value Information:
Package ()
{
Device Data Descriptor 0
...
Device Data Descriptor n
}
Each Device Data Descriptor structure consists of two elements, as follows:
UUID // Buffer (16 bytes)
Data Structure // Package (depending on UUID)
UUID uniquely determines the format of Data Structure.
Data Structure is a set of device speciﬁc data items the format of which is uniquely determined by the UUID and the
meaning of which is uniquely determined by the UUID possibly in combination with a PNP or ACPI device ID.
Multiple Device Data Descriptor structures with the same UUID are not permitted.
6.2. Device Conﬁguration Objects 341Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
_DSD must return the same data each time it is evaluated. Firmware should not expect it to be evaluated every time
(in case it is implemented as a method).
Examples:
Note: The UUID used in the following examples is assumed to deﬁne the data format for Data Structure as a list
of packages of length 2 (Properties) whose ﬁrst element (Key) must be a String and the second element is a Value
associated with that key. The set of valid Keys and the format and interpretation of the Values associated with them is
then dependent on the PNP or ACPI device ID of the device.
Device (MDEV) {
Name (_HID, "PNP####")
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) {...}, // Property 1
...
Package (2) {...} // Property n
}
})
}
//
// PWM controller with two pins that can be driven and a device using
// those pins with the periods of 5000000 and 4500000 nanoseconds,
// respectively.
//
Device (\_SB.PCI0.PWM) {
Package (2) {"#pwm-cells", 2}
}
})
}
Device (\_SB.PCI0.BL) {
Name (_HID, "ACPI####")
Package (2) {
"pwms",
\_SB.PCI0.PWM, 0, 5000000,
\_SB.PCI0.PWM, 1, 4500000
}
}
}
})
}
//
// SPI controller using a fixed frequency clock represented by the CLKO
6.2. Device Conﬁguration Objects 342Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
// device object.
//
Device (\_SB_.PCI0) {
Device (CLK0) {
Package (2) {"#clock-cells", 0},
Package (2) {"clock-frequency", 120000000}
}
})
}
Device (SPI0) {
Package (2) {"clocks", Package () {1, ^CLK0}}
}
})
...
}
}
6.2.6 _FIX (Fixed Register Resource Provider)
This optional object is used to provide a correlation between the ﬁxed-hardware register blocks deﬁned in the FADT
and the devices in the ACPI namespace that implement these ﬁxed-hardware registers. This object evaluates to a
package of Plug and Play-compatible IDs (32-bit compressed EISA type IDs) that correlate to the ﬁxed-hardware
register blocks deﬁned in the FADT. The device under which _FIX appears plays a role in the implementation of
the ﬁxed-hardware (for example, implements the hardware or decodes the hardware’s address). _FIX conveys to
OSPM whether a given device can be disabled, powered off, or should be treated specially by conveying its role in the
implementation of the ACPI ﬁxed-hardware register interfaces. This object takes no arguments.
The _CRS object describes a device’s resources. That _CRS object may contain a superset of the resources in the
FADT, as the device may actually decode resources beyond what the FADT requires. Furthermore, in a machine that
performs translation of resources within I/O bridges, the processor-relative resources in the FADT may not be the same
as the bus-relative resources in the _CRS.
None
A variable-length Package containing a list of Integers , each containing a PNP ID
Each of ﬁelds in the FADT has its own corresponding Plug and Play ID, as shown below:
PNP0C20 - SMI_CMD
PNP0C21 - PM1a_EVT_BLK / X\_ PM1a_EVT_BLK
6.2. Device Conﬁguration Objects 343Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PNP0C22 - PM1b_EVT_BLK / X_PM1b_EVT_BLK
PNP0C23 - PM1a_CNT_BLK / X_PM1a_CNT_BLK
PNP0C24 - PM1b_CNT_BLK / X\_ PM1b_CNT_BLK
PNP0C25 - PM2_CNT_BLK / X\_ PM2_CNT_BLK
PNP0C26 - PM_TMR_BLK / X\_ PM_TMR_BLK
PNP0C27 - GPE0_BLK / X_GPE0_BLK
PNP0C28 - GPE1_BLK / X\_ GPE1_BLK
PNP0B00 - FIXED_RTC
PNP0B01 - FIXED_RTC
PNP0B02 - FIXED_RTC
Example ASL for _FIX usage:
Scope(\_SB) {
Device(PCI0) { // Root PCI Bus
Name(_HID, EISAID("PNP0A03")) // Need \_HID for root device
Method (_CRS,0){ // Need current resources for root device
// Return current resources for root bridge 0
}
Name(_PRT, Package(){ // Need PCI IRQ routing for PCI bridge
// Package with PCI IRQ routing table
˓→information
})
Name(_FIX, Package(1) {
EISAID("PNP0C25")} // PM2 control ID
)
Device (PX40) { // ISA
Name(_ADR,0x00070000)
EISAID("PNP0C20")} // SMI command port
)
Device (NS17) { // NS17 (Nat. Semi 317, an ACPI part)
Name(_HID, EISAID("PNP0C02"))
Name(_FIX, Package(3) {
EISAID("PNP0C22"), // PM1b event ID
EISAID("PNP0C24"), // PM1b control ID
EISAID("PNP0C28")} // GPE1 ID
}
} // end PX40
Device (PX43) { // PM Control
Name(_ADR,0x00070003)
Name(_FIX, Package(4) {
EISAID("PNP0C21"), // PM1a event ID
EISAID("PNP0C23"), // PM1a control ID
EISAID("PNP0C26"), // PM Timer ID
EISAID("PNP0C27")} // GPE0 ID
)
} // end PX43
} // end PCI0
} // end scope SB
6.2. Device Conﬁguration Objects 344Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.2.7 _GSB (Global System Interrupt Base)
_GSB is an optional object that evaluates to an integer that corresponds to the Global System Interrupt Base for
the corresponding I/O APIC device. The I/O APIC device may either be bus enumerated (e.g. as a PCI device) or
enumerated in the namespace as described in I/O APIC Device . Any I/O APIC device that either supports hot-plug or
is not described in the MADT must contain a _GSB object.
If the I/O APIC device also contains a _MAT object, OSPM evaluates the _GSB object ﬁrst before evaluating the
_MAT object. By providing the Global System Interrupt Base of the I/O APIC, this object enables OSPM to process
only the _MAT entries that correspond to the I/O APIC device. See _MAT (Multiple APIC Table Entry) . Since _MAT
is allowed to potentially return all the MADT entries for the entire platform, _GSB is needed in the I/O APIC device
scope to enable OSPM to identify the entries that correspond to that device.
If an I/O APIC device is activated by a device-speciﬁc driver, the physical address used to access the I/O APIC will
be exposed by the driver and cannot be determined from the _MAT object. In this case, OSPM cannot use the _MAT
object to determine the Global System Interrupt Base corresponding to the I/O APIC device and hence requires the
_GSB object.
The Global System Interrupt Base is a 64-bit value representing the corresponding I/OAPIC device as deﬁned in
Global System Interrupts .
None Return Value: AnInteger containing the interrupt base
Example ASL for _GSB usage for a non-PCI based I/O APIC Device:
...
Device(APIC) { // I/O APIC Device
Name(_HID, "ACPI0009") // ACPI ID for I/O APIC
{ ...}) // only one resource pointing to I/O APIC register base
Method(_GSB){
Return (0x10) // Global System Interrupt Base for I/O APIC starts at 16
}
} // end APIC
Example ASL for _GSB usage for a PCI-based I/O APIC Device:
Device(PCI0) // Host bridge
Device(PCI1) { // I/O APIC PCI Device
Return (0x18) // Global System Interrupt Base for I/O APIC
˓→starts at 24
}
} // end PCI1

...
}
}
6.2. Device Conﬁguration Objects 345Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.2.8 _HPP (Hot Plug Parameters)
This optional object evaluates to a package containing the cache-line size, latency timer, SERR enable, and PERR
enable values to be used when conﬁguring a PCI device inserted into a hot-plug slot or for performing conﬁguration
of a PCI devices not conﬁgured by the platform boot ﬁrmware at system boot. The object is placed under a PCI bus
where this behavior is desired, such as a bus with hot-plug slots. _HPP provided settings apply to all child buses, until
another _HPP object is encountered.
None
APackage containing the Integer hot-plug parameters
Example:
Method (_HPP, 0) {
Return (Package(4){
0x08, // CacheLineSize in DWORDS
0x40, // LatencyTimer in PCI clocks
0x01, // Enable SERR (Boolean)
0x00 // Enable PERR (Boolean)
})
}
Table 6.7: HPP Package Contents
Field Object Type Deﬁnition
Cache-line
sizeInteger Cache-line size reported in number of DWORDs.
Latency timer Integer Latency timer value reported in number of PCI clock cycles.
Enable SERR Integer When set to 1, indicates that action must be performed to enable SERR in the
command register.
Enable PERR Integer When set to 1, indicates that action must be performed to enable PERR in the
Example: Using _HPP
Name(_HID, EISAID("PNP0A03")) // \_HID for root device
Method (_CRS,0){ // Need current resources for root dev
}
// Package with PCI IRQ routing table information
})
Device (P2P1) { // First PCI-to-PCI bridge (No Hot Plug slots)
Name(_ADR,0x000C0000) // Device#Ch, Func#0 on bus PCI0
})
} // end P2P1
Device (P2P2) {
// Second PCI-to-PCI bridge (Bus contains Hot plug
˓→slots)
6.2. Device Conﬁguration Objects 346Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Name(_ADR,0x000E0000) // Device#Eh, Func#0 on bus PCI0
})
Name(_HPP, Package(){0x08,0x40, 0x01, 0x00})
// Device definitions for Slot 1- HOT PLUG SLOT
Device (S1F0) { // Slot 1, Func#0 on bus P2P2
Name(_ADR,0x00020000)
Method(_EJ0, 1) { // Remove all power to device}
}
Device (S1F1) { // Slot 1, Func#1 on bus P2P2
Name(_ADR,0x00020001)
}
Device (S1F2) { // Slot 1, Func#2 on bus P2P2
Name(_ADR,0x000200 02)
}
Device (S1F3) { // Slot 1, Func#3 on bus P2P2
Name(_ADR,0x00020003)
}
Device (S1F4) { // Slot 1, Func#4 on bus P2P2
Name(_ADR,0x00020004)
}
Device (S1F5) { // Slot 1, Func#5 on bus P2P2
Name(_ADR,0x00020005)
}
Device (S1F6) { // Slot 1, Func#6 on bus P2P2
Name(_ADR,0x00020006)
}
Device (S1F7) { // Slot 1, Func#7 on bus P2P2
Name(_ADR,0x00020007)
}
// Device definitions for Slot 2- HOT PLUG SLOT
Device (S2F0) { // Slot 2, Func#0 on bus P2P2
Name(_ADR,0x00030000)
}
Device (S2F1) { // Slot 2, Func#1 on bus P2P2
Name(_ADR,0x00030001)
}
Device (S2F2) { // Slot 2, Func#2 on bus P2P2
Name(_ADR,0x00030002)
}
Device (S2F3) { // Slot 2, Func#3 on bus P2P2
Name(_ADR,0x00030003)
}
Device (S2F4) { // Slot 2, Func#4 on bus P2P2
Name(_ADR,0x00030004)
6.2. Device Conﬁguration Objects 347Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
}
Device (S2F5) { // Slot 2, Func#5 on bus P2P2
Name(_ADR,0x00030005)
}
Device (S2F6) { // Slot 2, Func#6 on bus P2P2
Name(_ADR,0x00030006)
}
Device (S2F7) { // Slot 2, Func#7 on bus P2P2
Name(_ADR,0x00030007)
}
} // end P2P2
} // end Scope (\_SB)
OSPM will conﬁgure a PCI device on a card hot-plugged into slot 1 or slot 2, with a cache line size of 32 (Notice this
ﬁeld is in DWORDs), latency timer of 64, enable SERR, but leave PERR alone.
6.2.9 _HPX (Hot Plug Parameter Extensions)
This optional object provides platform-speciﬁc information to the OSPM PCI driver component responsible for con-
ﬁguring PCI, PCI-X, or PCI Express Functions. The information conveyed applies to the entire hierarchy downward
from the scope containing the _HPX object. If another _HPX object is encountered downstream, the settings conveyed
by the lower-level object apply to that scope downward.
OSPM uses the information returned by _HPX to determine how to conﬁgure PCI Functions that are hot-plugged into
the system, to conﬁgure Functions not conﬁgured by the platform ﬁrmware during initial system boot, and to conﬁgure
Functions any time they lose conﬁguration space settings (e.g. OSPM issues a Secondary Bus Reset/Function Level
Reset or Downstream Port Containment is triggered). The _HPX object is placed within the scope of a PCI-compatible
bus where this behavior is desired, such as a bus with hot-plug slots. It returns a single package that contains one or
more sub-packages, each containing a single Setting Record. Each such Setting Record contains a Setting Type
(INTEGER), a Revision number (INTEGER) and type/revision speciﬁc contents.
The format of data returned by the _HPX object is extensible. The Setting Type and Revision number determine the
format of the Setting Record. OSPM ignores Setting Records of types that it does not understand. A Setting Record
with higher Revision number supersedes that with lower revision number, however, the _HPX method can return
both together, OSPM shall use the one with highest revision number that it understands. Type 3 records may have
multiple records with the same revision or different revision (refer to the Revision ﬁeld in PCI Express Descriptor
Setting Record Content . Out of all the Type 3 records, the OSPM shall determine the highest revision number that it
understands and use all Type 3 records with that revision.
_HPX may return multiple types or Record Settings (each setting in a single sub-package.) OSPM is responsible
for detecting the type of Function and for applying the appropriate settings. OSPM is also responsible for detecting
the device / port type of the PCI Express Function and applying the appropriate settings provided. For example, the
Secondary Uncorrectable Error Severity and Secondary Uncorrectable Error Mask settings of Type 2 record are only
applicable to PCI Express to PCI-X/PCI Bridge whose device / port type is 1000b. Similarly, AER settings are only
applicable to hot plug PCI Express devices that support the optional AER capability.
None
6.2. Device Conﬁguration Objects 348Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A variable-length Package containing a list of Packages , each containing a single PCI, PCI-X, PCI Ex-
press, or PCI Express Descriptor Record Setting as described below
The _HPX object supersedes the _HPP object. If the _HPP and _HPX objects exist within a device’s
scope, OSPM will only evaluate the _HPX object.
Note: OSPM may override the settings provided by the _HPX object’s Type2 record (PCI Express Settings) or Type3
record (PCI Express Descriptor Settings) when OSPM has assumed native control of the corresponding feature. For
example, if OSPM has assumed ownership of AER (via _OSC), OSPM may override AER related settings returned
by _HPX.
Note: Since error status registers do not drive error signaling, OSPM is not required to clear error status registers as
part of _HPX handling.
Note: There are other mechanisms besides _HPX that provide platform-speciﬁc information to the OSPM PCI driver
component responsible for conﬁguring PCI, PCI-X, or PCI Express Functions (e.g., _DSM Deﬁnitions for Latency
Tolerance Reporting as deﬁned in the PCI Firmware Speciﬁcation). System ﬁrmware should only provide platform-
speciﬁc information via one of these mechanisms for any given register or feature (i.e., if Latency Tolerance Reporting
information is provided via _DSM Deﬁnitions for Latency Tolerance Reporting then no information related to Latency
Tolerance Reporting should be provided by _HPX and vice versa). Failure to do so will result in undeﬁned behavior
from the OSPM.

by _HPX.
6.2.9.1 PCI Setting Record (Type 0)
The PCI setting record contains the setting type 0, the current revision 1 and the type/revision speciﬁc content: cache-
line size, latency timer, SERR enable, and PERR enable values.
Table 6.8: PCI Setting Record Content
Header
- Type Integer 0x00: Type 0 (PCI) setting record.
- Revision Integer 0x01: Revision 1, deﬁning the set of ﬁelds below.
Cache-line size Integer Cache-line size reported in number of DWORDs.
Enable SERR Integer When set to 1, indicates that action must be performed to enable
SERR in the command register.
Enable PERR Integer When set to 1, indicates that action must be performed to enable
PERR in the command register.
If the hot plug device includes bridge(s) in the hierarchy, the above settings apply to the primary side (command
register) of the hot plugged bridge(s). The settings for the secondary side of the bridge(s) (Bridge Control Register)
are assumed to be provided by the bridge driver.
The Type 0 record is applicable to hot plugged PCI, PCI-X and PCI Express devices. OSPM will ignore settings
provided in the Type0 record that are not applicable (for example, Cache-line size and Latency Timer are not applicable
to PCI Express).
6.2. Device Conﬁguration Objects 349Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.2.9.2 PCI-X Setting Record (Type 1)
The PCI-X setting record contains the setting type 1, the current revision 1 and the type/revision speciﬁc content:
the maximum memory read byte count setting, the average maximum outstanding split transactions setting and the
total maximum outstanding split transactions to be used when conﬁguring PCI-X command registers for PCI-X buses
and/or devices.
Table 6.9: PCI-X Setting Record Content
Header
- Type Integer 0x01: Type 1 (PCI-X) setting record.
Maximum
memory read
byte countInteger Maximum memory read byte count reported: Value 0: Maximum byte count
512 Value 1: Maximum byte count 1024 Value 2: Maximum byte count 2048
Value 3: Maximum byte count 4096
Average
maximum
outstanding
split transac-
tionsInteger The following values are deﬁned: Value 0: Maximum outstanding split trans-
action 1 Value 1: Maximum outstanding split transaction 2 Value 2: Maximum
outstanding split transaction 3 Value 3: Maximum outstanding split transaction
4 Value 4: Maximum outstanding split transaction 8 Value 5: Maximum out-
standing split transaction 12 Value 6: Maximum outstanding split transaction
16 Value 7: Maximum outstanding split transaction 32
Total max-
imum out-
standing split
transactionsInteger See the deﬁnition for the average maximum outstanding split transactions.
For simplicity, OSPM could use the Average Maximum Outstanding Split Transactions value as the Maximum Out-
standing Split Transactions register value in the PCI-X command register for each PCI-X device. Another alternative
is to use a more sophisticated policy and the Total Maximum Outstanding Split Transactions Value to gain even more
performance. In this case, the OS would examined each PCI-X device that is directly attached to the host bridge,
determine the number of outstanding split transactions supported by each device, and conﬁgure each device accord-
ingly. The goal is to ensure that the aggregate number of concurrent outstanding split transactions does not exceed the
Total Maximum Outstanding Split Transactions Value: an integer denoting the number of concurrent outstanding split
transactions the host bridge can support (the minimum value is 1).
This object does not address providing additional information that would be used to conﬁgure registers in bridge
devices, whether architecturally-deﬁned or speciﬁcation-deﬁned registers or device speciﬁc registers. It is expected
that a driver for a bridge would be the proper implementation mechanism to address both of those issues. However,
such a bridge driver should have access to the data returned by the _HPX object for use in optimizing its decisions on
how to conﬁgure the bridge. Conﬁguration of a bridge is dependent on both system speciﬁc information such as that
provided by the _HPX object, as well as bridge speciﬁc information.
6.2.9.3 PCI Express Setting Record (Type 2)
The PCI Express setting record contains the setting type 2, the current revision 1 and the type/revision speciﬁc content
(the control registers as listed in the table below) to be used when conﬁguring registers in the Advanced Error Reporting
Extended Capability Structure or PCI Express Capability Structure for the PCI Express devices.
The Type 2 Setting Record allows a PCI Express-aware OS that supports native hot plug to conﬁgure the speciﬁed
registers of the hot plugged PCI Express device. A PCI Express-aware OS that has assumed ownership of native
hot plug (via _OSC) but does not support or does not have ownership of the AER register set must use the data
values returned by the _HPX object’s Type 2 record to program the AER registers of a hot-added PCI Express device.
6.2. Device Conﬁguration Objects 350Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
However, since the Type 2 record also includes register bits that have functions other than AER, OSPM must ignore
values contained within this setting record that are not applicable.
To support PCIe RsvdP semantics for reserved bits, two values for each register are provided: an “AND mask” and
an “OR mask”. Each bit understood by ﬁrmware to be RsvdP shall be set to 1 in the “AND mask” and 0 in the “OR
mask”. Each bit that ﬁrmware intends to be conﬁgured as 0 shall be set to 0 in both the “AND mask” and the “OR
mask”. Each bit that ﬁrmware intends to be conﬁgured a 1 shall be set to 1 in both the “AND mask” and the “OR
mask”.
When conﬁguring a given register, OSPM uses the following algorithm:
1. Read the register’s current value, which contains the register’s default value.
2. Perform a bit-wise AND operation with the “AND mask” from the table below.
3. Perform a bit-wise OR operation with the “OR mask” from the table below.
4. Override the computed settings for any bits if deemed necessary. For example, if OSPM is aware of an ar-
chitected meaning for a bit that ﬁrmware considers to be RsvdP, OSPM may choose to override the computed
setting for that bit. Note that ﬁrmware sets the “AND value” to 1 and the “OR value” to 0 for each bit that it
considers to be RsvdP.
5. Write the end result value back to the register.
Note that the size of each ﬁeld in the following table matches the size of the corresponding PCI Express register.
Table 6.10: PCI Express Setting Record Content
Field Object
TypeDeﬁnition
Header
- Type Integer 0x02: Type 2 (PCI Express) setting record.
Uncorrectable Error Mask Register
AND MaskInteger Bits [31:0] contain the “AND mask” to be used in the OSPM
algorithm described above.
OR MaskInteger Bits [31:0] contain the “OR mask” to be used in the OSPM
Uncorrectable Error Severity Register
Correctable Error Mask Register
Correctable Error Mask Register OR
MaskInteger Bits [31:0] contain the “OR mask” to be used in the OSPM
Advanced Error Capabilities and Con-
trol Register AND MaskInteger Bits [31:0] contain the “AND mask” to be used in the OSPM
trol Register OR MaskInteger Bits [31:0] contain the “OR mask” to be used in the OSPM
Device Control Register AND Mask Integer Bits [15 :0] contain the “AND mask” to be used in the OSPM
Device Control Register OR Mask Integer Bits [15:0] contain the “OR mask” to be used in the OSPM
Link Control Register AND Mask Integer Bits [15 :0] contain the “AND mask” to be used in the OSPM
Link Control Register OR Mask Integer Bits [15 :0] contain the “OR mask” to be used in the OSPM
6.2. Device Conﬁguration Objects 351Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.10 – continued from previous page
Secondary Uncorrectable Error Sever-
ity Register AND MaskInteger Bits [31 :0] contain the “AND mask” to be used in the OSPM
algorithm described above
ity Register OR MaskInteger Bits [31 :0] contain the “OR mask” to be used in the OSPM

Secondary Uncorrectable Error Mask
Register AND MaskInteger Bits [31 :0] contain the “AND mask” to be used in the OSPM
Register OR MaskInteger Bits [31 :0] contain the “OR mask” to be used in the OSPM
6.2.9.4 PCI Express Descriptor Setting Record (Type 3)
The PCI Express Descriptor setting record contains the setting type 3, the current revision 1 and the type/revision
speciﬁc content (the control registers as listed in the tables below) to be used when conﬁguring registers in PCI
Express Functions. There may be multiple PCI Express Descriptor setting records in a single _HPX object with the
same or different revision. Each PCI Express Descriptor setting record shall contain at least one, and may contain
more than one, PCI Express Register Descriptors as deﬁned in PCI Express Register Descriptor .
The Type 3 Setting Record allows a PCI Express-aware OS to conﬁgure the indicated registers of the PCI Express
Function. A PCI Express-aware OS that does not support or does not have ownership of a register in this record
must use the data values returned by the _HPX object’s Type 3 record to program that register of a PCI Express
Function that has lost its conﬁguration space settings (e.g. a hot-added device, a device not conﬁgured by the platform
ﬁrmware during initial system boot, a Device/Function that was reset via Secondary Bus Reset/Function Level Reset,
Downstream Port Containment was triggered, etc.).
To support PCIe RsvdP semantics for reserved bits, two values for each register indicated by Write Register Offset are
provided: a Write AND Mask and a Write OR Mask. Each bit understood by ﬁrmware to be RsvdP shall be set to 1 in
the Write AND Mask and 0 in the Write OR Mask. Each bit that ﬁrmware intends to be conﬁgured as 0 shall be set to
0 in both the Write AND Mask and the Write OR Mask. Each bit that ﬁrmware intends to be conﬁgured a 1 shall be
set to 1 in both the Write AND Mask and the Write OR Mask.
OSPM evaluates each PCI Express Register Descriptor in order starting with the ﬁrst PCI Express Register Descriptor
and continuing through the Nth PCI Express Register Descriptor as shown in PCI Express Descriptor Setting Record
Content for each PCI Express Function that has lost its conﬁguration space settings (e.g. a hot-added device, a device
not conﬁgured by the platform ﬁrmware during initial system boot, a Device/Function that was reset via Secondary
Bus Reset/Function Level Reset, Downstream Port Containment was triggered, etc.) in the scope of the _HPX method
using the following algorithm:
1. Verify the PCI Express Register Descriptor applies to the PCI Express Function.
a. Read the PCI Express Function’s Device Type/Port from its PCI Express Capabilities Register.
b. Read the bit corresponding to the PCI Express Function’s Device Port/Type in the Device/Port Type from
PCI Express Register Descriptor below.
If set to 0b, then the PCI Express Register Descriptor does not apply to the PCI Express Function and
OSPM moves to the next Function in the scope of the _HPX method or the next PCI Express Register
Descriptor if there are no more Functions.
If set to 1b, then continue to the next step.
c. Determine if the PCI Express Function is a non-SR-IOV Function, an SR-IOV Physical Function, or an
SR-IOV Virtual Function.
d. Read the bit corresponding to the PCI Express Function’s type in the Function Type from PCI Express
Register Descriptor below.
6.2. Device Conﬁguration Objects 352Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
OSPM moves to the next Function in the scope of the _HPX method or to the next PCI Express Register
If set to 1b, then the PCI Express Register Descriptor applies to the PCI Express Function and OSPM
continues to the next step.
2. Read the Conﬁguration Space Location from PCI Express Register Descriptor below.
a. If Conﬁguration Space Location is 0, then the Match Register Offset and Write Register Offset ﬁeld’s byte
offset is relative to offset 0 of the Function’s conﬁguration space.
b. If Conﬁguration Space Location is 1, then the Match Register Offset and Write Register Offset ﬁeld’s byte
offset is relative to the starting offset of the Capability Structure indicated by PCIe Capability ID.
If the Capability ID is 01h (PCI Power Management Capability Structure) or 10h (PCI Express Capability
Structure) then OSPM shall check the Capability Version of the Function’s Capability Structure against
the PCIe Capability ID ﬁeld. In the event that there are more than one PCI Express Register Descriptors
for a given PCIe Capability ID with different PCIe Capability Versions, OSPM shall use the PCI Express
Register Descriptors with the highest PCIe Capability Version supported by the Function.
There may be more than one instance of a Capability Structure that matches the indicated PCIe Capability
ID. Continue to step 3 for each such instance. If no Capability Structures indicated by PCIe Capability ID
are found, then start back at step 1 above for the next Function in the scope of the _HPX method or the
next PCI Express Register Descriptor if there are no more Functions.
c. If Conﬁguration Space Location is 2, then the Match Register Offset and Write Register Offset ﬁeld’s byte
offset is relative to the starting offset of the Extended Capability Structure indicated by PCIe Capability
ID and PCIe Capability Version.
In the event that there are more than one PCI Express Register Descriptors for a given PCIe Capability ID
with different PCIe Capability Versions, OSPM shall use the PCI Express Register Descriptors with the
highest PCIe Capability Version supported by the Function.
There may be more than one instance of an Extended Capability Structure that matches the indicated PCIe
Capability ID and PCIe Capability Version. Continue to step 3 for each such instance. If no Extended
Capability Structures indicated by PCIe Capability ID and PCIe Capability Version are found, then start
back at step 1 above for the next Function in the scope of the _HPX method or the next PCI Express
Register Descriptor if there are no more Functions.
d. If Conﬁguration Space Location is 3, then the Match Register Offset and Write Register Offset ﬁeld’s byte
ID, PCIe Capability Version, PCIe Vendor ID, VSEC ID, and VSEC Rev.
Once the PCI Express Register Descriptors that match the PCIe Capability ID with the highest PCIe Capa-
bility Version supported by the Function are found, the OSPM shall use PCI Express Register Descriptors
among those with the highest VSEC Rev supported by the Function.
Capability ID, PCIe Capability Version, PCIe Vendor ID, VSEC ID, and VSEC Rev. Continue to step 3 for
each such instance. If no Extended Capability Structures indicated by PCIe Capability ID, PCIe Capability
Version, PCIe Vendor ID, VSEC ID, and VSEC Rev are found, then start back at step 1 above for the next
Function in the scope of the _HPX method or the next PCI Express Register Descriptor if there are no
more Functions.
e. If Conﬁguration Space Location is 4, then the Match Register Offset and Write Register Offset ﬁeld’s byte
6.2. Device Conﬁguration Objects 353Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ID, PCIe Capability Version, PCIe Vendor ID, DVSEC ID, and DVSEC Rev.
among those with the highest DVSEC Rev supported by the Function.
Capability ID, PCIe Capability Version, PCIe Vendor ID, DVSEC ID, and DVSEC Rev. Continue to step
3 for each such instance. If no Extended Capability Structures indicated by PCIe Capability ID, PCIe
Capability Version, PCIe Vendor ID, DVSEC ID, and DVSEC Rev are found, then start back at step 1

above for the next Function in the scope of the _HPX method or the next PCI Express Register Descriptor
if there are no more Functions.
3. Check the Match Register to see if the Write Register should be updated.
a. Read the current value from the register indicated by the Match Register Offset.
b. Perform a bit-wise AND operation on the result of step 3a with the Match AND Mask.
c. Compare the result of step 3b with the Match Value. If they are equal then continue to step 4, else start
back at step 1 above for the next Function
d. In the scope of the _HPX method or the next PCI Express Register Descriptor if there are no more Func-
tions.
4. Update the Write Register.
a. Read the current value from the register indicated by the Write Register Offset.
b. Perform a bit-wise AND operation on the result of step 4a with the Write AND Mask.
c. Perform a bit-wise OR operation on the result of step 4b with the Write OR Mask.
d. Override the computed settings from step 4c for any bits if deemed necessary. For example, if OSPM
is aware of an architected meaning for a bit that ﬁrmware considers to be RsvdP, OSPM may choose to
override the computed setting for that bit. Note that ﬁrmware sets the Write AND Mask to 1 and the Write
OR Mask to 0 for each bit that it considers to be RsvdP.
e. Write the result of step 4d back to the register indicated by the Write Register Offset.
Table 6.11: PCI Express Descriptor Setting Record Content
Header
- Type Integer 0x03: Type 3 (PCI Express Descriptor) setting record.
PCI Express Regis-
ter Descriptor CountInteger Number of Register Descriptors in this setting record.
First PCI Express
Register DescriptorPCI Express Regis-
ter DescriptorThe ﬁrst PCI Express Register Descriptor as described in Table 6.12
Second PCI Express
ter DescriptorThe second PCI Express Register Descriptor as described in Table
6.12
. . . . . . . . .
Nth PCI Express
ter DescriptorThe Nth PCI Express Register Descriptor as described in Table 6.12
6.2. Device Conﬁguration Objects 354Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.12: PCI Express Register Descriptor
Device/Port Type Integer
This ﬁeld is a bitmask of Device/Port Types to which the PCI Express
Register Descriptor applies. A bit is set to 1 to indicate the PCI Express
Register Descriptor applies to the corresponding Device/Port Type and is
set to 0 to indicate it does not apply to the corresponding Device/Port
Type. At least one bit shall be set. More than one bit may be set.
Bit [0]: PCI Express Endpoint
Bit [1]: Legacy PCI Express Endpoint
Bit [2]: RCiEP Bit [3]: Root Complex Event Collector
Bit [3]: Root Complex Event Collector
Bit [4]: Root Port of PCI Express Root Complex
Bit [5]: Upstream Port of PCI Express Switch
Bit [6]: Downstream Port of PCI Express Switch
Bit [7]: PCI Express to PCI/PCI-X Bridge
Bit [8]: PCI/PCI-X to PCI Express Bridge
Function Type Integer
This ﬁeld is a bitmask of Function Types to which the PCI Express
Register Descriptor applies to the corresponding Function Type and is set
to 0 to indicate it does not apply to the corresponding Function Type. At
least one bit shall be set. More than one bit may be set.
Bit [0]: Non-SR-IOV Function
Bit [1]: SR-IOV Physical Function
Bit [2]: SR-IOV Virtual Function
All other bits are reserved
6.2. Device Conﬁguration Objects 355Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.12 – continued from previous page
Conﬁguration Space Lo-
cationInteger
A value of 0 indicates the Match Register Offset and Write Register
Offset ﬁelds are relative to offset 0 of the Function’s conﬁguration space.
A value of 1 indicates the Match Register Offset and Write Register
Offset ﬁelds are located in a Capability Structure within the ﬁrst 256
bytes of PCIe conﬁguration space and are relative to offset 0 of the
Capability Structure.
A value of 2 indicates the Match Register Offset and Write Register
Offset ﬁelds are located in an Extended Capability Structure beyond the
ﬁrst 256 bytes of PCI conﬁguration space and are relative to offset 0 of
the Extended Capability Structure.
A value of 3 indicates the Match Register Offset and Write Register
ﬁelds are located in a PCI Express Vendor-Speciﬁc Extended Capability
and are relative to offset 0 of the Vendor-Speciﬁc Extended Capability.
A value of 4 indicates the Match Register Offset and Write Register
Offset ﬁelds are located in a PCI Express Designated Vendor-Speciﬁc
Extended Capability and are relative to offset 0 of the Designated
Vendor-Speciﬁc Extended Capability.
PCIe Capability ID Integer
PCIe Capability ID indicates the capability ID to which the PCI Express
Register Descriptor applies: Capability Structure (if Conﬁguration Space
Location is 1) or Extended Capability Structure (if Conﬁguration Space
Location is 2).
This ﬁeld only applies if Conﬁguration Space Location is 1 (Capability
Structure), 2 (Extended Capability Structure), 3 (Vendor-Speciﬁc
Extended Capability), or 4 (Designated Vendor-Speciﬁc Extended
Capability).
6.2. Device Conﬁguration Objects 356Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PCIe Capability Version Integer
This ﬁeld contains information about the Capability Version/Extended
Capability Version and applies in the following conditions:
- Conﬁguration Space Location is 1 (Capability Structure) and Capability
ID is 01h (PCI Power Management Capability Structure); or
ID is 10h (PCI Express Capability Structure); or
- Conﬁguration Space Location is 2 (Extended Capability Structure); or
- Conﬁguration Space Location is 3 (Vendor-Speciﬁc Extended
Capability); or
- Conﬁguration Space Location is 4 (Designated Vendor-Speciﬁc
Extended Capability).
Bit [4] indicates the applicability of the Capability Version/Extended
Capability Version in bits [3:0]. Deﬁned values are:
- 0b: The PCI Express Register Descriptor applies to Capability
Structures/Extended Capability Structures with Capability Versions that
are equal to the version in bits [3:0].
- 1b: The PCI Express Register Descriptor applies to Capability
are greater than or equal to the version in bits [3:0].
Bits [3:0] indicate the Capability Version of the Capability
Structures/Extended Capability Structure. Note that the version of the
Capability Structure/Extended Capability Structure is always 4 bits
except for the PCI Power Management Capability Structure whose
Version ﬁeld is only 3 bits. For the PCI Power Management Capability
structure, this ﬁeld shall contain the Version in bits [2:0] and bit [3] shall
be 0b.
PCIe Vendor ID Integer
If Conﬁguration Space Location is 3 (Vendor-Speciﬁc Extended
Capability Structure), this ﬁeld indicates the vendor in the Vendor ID
register at offset 0 of the Function’s conﬁguration space to which the PCI
Express Register Descriptor applies.
If Conﬁguration Space Location is 4 (Designated Vendor-Speciﬁc
Extended Capability Structure), this ﬁeld indicates the vendor in the
DVSEC Vendor ID register at offset 4 in the Designated Vendor-Speciﬁc
Extended Capability Structure to which the PCI Express Register
Descriptor applies.
This ﬁeld only applies if Conﬁguration Space Location is 3
(Vendor-Speciﬁc Extended Capability Structure) or 4 (Designated
Vendor-Speciﬁc Extended Capability Structure).
6.2. Device Conﬁguration Objects 357Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
VSEC/DVSEC ID Integer
Capability Structure), this ﬁeld indicates the vendor-deﬁned ID number
(VSEC ID) of the Vendor-Speciﬁc Extended Capability Structure to
which the PCI Express Register Descriptor applies.
Extended Capability Structure), this ﬁeld indicates the DVSEC ID of the
Designated Vendor-Speciﬁc Extended Capability Structure to which the
PCI Express Register Descriptor applies.
VSEC/DVSEC Rev Integer
This ﬁeld contains information about the VSEC/DVSEC Rev and only
applies if Conﬁguration Space Location is 3 (Vendor-Speciﬁc Extended
Capability Structure) or 4 (Designated Vendor-Speciﬁc Extended
Capability Structure).

Bit [4] indicates the applicability of the VSEC/DVSEC Rev in bits [3:0].
Deﬁned values are:
- 0b: The PCI Express Register Descriptor applies to Vendor Speciﬁc
Extended Capabilities/Designat ed Vendor-Speciﬁc Capabilities with
VSEC/DVSEC Revs that are equal to the revision in bits [3:0].
- 1b: The PCI Express Register Descriptor applies to Vendor Speciﬁc
VSEC/DVSEC Revs that are greater than or equal to the revision in bits
[3:0].
Bits [3:0] - If Conﬁguration Space Location is 3 (Vendor-Speciﬁc
Extended Capability Structure), this ﬁeld indicates the VSEC Rev of the
Vendor-Speciﬁc Extended Capability Structure. If Conﬁguration Space
Location is 4 (Designated Vendor-Speciﬁc Extended Capability
Structure), this ﬁeld indicates the DVSEC Revision of the Designated
Vendor-Speciﬁc Extended Capability Structure.
Match Register Offset Integer Byte offset of the PCIe conﬁguration space register that is checked before
the write. This offset shall be dword aligned (i.e. bits [1:0] are 00b).
Match AND Mask Integer Bits 0 to 31 contain the AND mask to be used by the operating system
engine during the check.
Match Value Integer Bits 0 to 31 contain the value to be compared by Operating system engine
before the write.
Write Register Offset Integer Byte offset of the PCIe conﬁguration space register to be modiﬁed. This
offset shall be dword aligned (i.e. bits [1:0] are 00b).
Write AND Mask Integer Bits 0 to 31 contain the AND mask to be used by the operating system
engine to modify the value to be written to the register indicated by Write
Register Offset.
Write OR Mask Integer Bits 0 to 31 contain the OR mask to be used by the operating system
6.2. Device Conﬁguration Objects 358Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.2.9.5 _HPX Example
Method (_HPX, 0) {
Return (Package(2){
Package(6){ // PCI Setting Record
0x00, // Type 0
0x01, // Revision 1
},
Package(5){ // PCI-X Setting Record
0x01, // Type 1
0x03, // Maximum Memory Read Byte Count
0x04, // Average Maximum Outstanding Split Transactions
0x07 // Total Maximum Outstanding Split Transactions
}
Package(17){ // PCI Express Descriptor setting Record (Type 3)
0x03, // Type 3
0x01, // Number of Register Descriptors
0x01FF, // Device/Port Type - All types in PCIe 4.0
0x03, // Function Type - All but VFs
0x01, // Configuration Space Location - Capability Structure
0x10, // PCIe Capability ID - PCI Express Cap Struct
0x12, // PCIe Capability Version - Applies to rev 2 and higher
0x0000, // PCIe Vendor ID - N/A
0x00, // VSEC/DVSEC ID - N/A
0x00, // VSEC/DVSEC Rev - N/A
0x24, // Match Register Offset - Device Cap 2
0x00000002, // Match AND Mask - Check Range B
0x00000002 // Match Value - CTO Range B supported?
0x28, // Write Register Offset - Device Ctrl 2
0xFFFFFFF0, // Write AND Mask - Clear CTO Range
0x00000006 // Write OR Mask - Set CTO range 65 ms to 210 ms
}
0x00000006, // Match AND Mask - Check Range B/C
0x00000004 // Match Value - CTO Range B not supported but C is?
0x00000009 // Write OR Mask - Set CTO range 260 to 900 ms
}
6.2. Device Conﬁguration Objects 359Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
0x00000016, // Match AND Mask - Check Range B/C and CTO Disable
0x00000010 // Match Value - CTO Disable support but no range B/C?
0xFFFFFFFF, // Write AND Mask - Don't mask anything
0x00000010 // Write OR Mask - Set CTO Disable
}
})
}
6.2.10 _MAT (Multiple APIC Table Entry)
This optional object evaluates to a buffer returning data in the format of a series of Multiple APIC Description Table
(MADT) APIC Structure entries. This object can appear under an I/O APIC or processor object deﬁnition as processors
may contain Local APICs. Speciﬁc types of MADT entries are meaningful to (in other words, processed by) OSPM
when returned via the evaluation of this object as described in Table 5.21. Other entry types returned by the evaluation
of _MAT are ignored by OSPM.
When _MAT appears under a Processor object, OSPM uses the ACPI processor ID in the entries returned from the
object’s evaluation to identify the entries corresponding to either the ACPI processor ID of the Processor object or the
value returned by the _UID object under a Processor device.
None
ABuffer containing a list of Interrupt Controller Structures.
Example ASL for _MAT usage:
Device (P64A) { // P64A ACPI
Name (_ADR,0)
OperationRegion (OPRM, SystemMemory,
Offset in system memory of Interrupt Controller Structures,
Length in bytes)
Field (OPRM, ByteAcc, NoLock, Preserve) {
MATD, Length in bits
}
Method(_MAT, 0){
Return (MATD)
6.2. Device Conﬁguration Objects 360Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
}
...
} // end P64A
...
...
6.2.11 _OSC (Operating System Capabilities)
This optional object is a control method that is used by OSPM to communicate to the platform the feature support
or capabilities provided by a device’s driver. This object is a child object of a device and may also exist in the
\_SB scope, where it can be used to convey platform wide OSPM capabilities. When supported, _OSC is invoked
by OSPM immediately after placing the device in the D0 power state. Device speciﬁc objects are evaluated after
_OSC invocation. This allows the values returned from other objects to be predicated on the OSPM feature support
/ capability information conveyed by _OSC. OSPM may evaluate _OSC multiple times to indicate changes in OSPM
capability to the device but this may be precluded by speciﬁc device requirements. As such, _OSC usage descriptions
inACPI-Deﬁned Devices and Device-Speciﬁc Objects , or other governing speciﬁcations describe superseding device
speciﬁc _OSC capabilities and / or preclusions.
_OSC enables the platform to conﬁgure its ACPI namespace representation and object evaluations to match the capa-
bilities of OSPM. This enables legacy operating system support for platforms with new features that make use of new
namespace objects that if exposed would not be evaluated when running a legacy OS. _OSC provides the capability
to transition the platform to native operating system support of new features and capabilities when available through
dynamic namespace reconﬁguration. _OSC also allows devices with Compatible IDs to provide superset functionality
when controlled by their native (For example, _HID matched) driver as appropriate objects can be exposed accordingly
as a result of OSPM’s evaluation of _OSC.
Arguments: (4)
Arg0 - A Buffer containing a UUID
Arg1 - An Integer containing a Revision ID of the buffer format
Arg2 - An Integer containing a count of entries in Arg3
Arg3 - A Buffer containing a list of DWORD capabilities
ABuffer containing a list of capabilities
Argument Information
Arg0: UUID - used by the platform in conjunction with Revision ID to ascertain the format of the Capabilities buffer.
Arg1: Revision ID - The revision of the Capabilities Buffer format. The revision level is speciﬁc to the UUID.
Arg2: Count - Number of DWORDs in the Capabilities Buffer in Arg3
Arg3: Capabilities Buffer - Buffer containing the number of DWORDs indicated by Count. The ﬁrst DWORD of

this buffer contains standard bit deﬁnitions as described below. Subsequent DWORDs contain UUID-speciﬁc bits
that convey to the platform the capabilities and features supported by OSPM. Successive revisions of the Capabilities
Buffer must be backwards compatible with earlier revisions. Bit ordering cannot be changed.
Capabilities Buffers are device-speciﬁc and as such are described under speciﬁc device deﬁnitions. See ACPI-Deﬁned
Devices and Device-Speciﬁc Objects for any _OSC deﬁnitions for ACPI devices. The format of the Capabilities
Buffer and behavior rules may also be speciﬁed by OEMs and IHVs for custom devices and other interface or device
governing bodies for example, the PCI SIG.
6.2. Device Conﬁguration Objects 361Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The ﬁrst DWORD in the capabilities buffer is used to return errors deﬁned by _OSC. This DWORD must always be
present and may not be redeﬁned/reused by unique interfaces utilizing _OSC.
• Bit [0]- Query Support Flag. If set, the _OSC invocation is a query by OSPM to determine or negotiate with
the platform the combination of capabilities for which OSPM may take control. In this case, OSPM sets bits in
the subsequent DWORDs to specify the capabilities for which OSPM intends to take control. If clear, OSPM is
attempting to take control of the capabilities corresponding to the bits set in subsequent DWORDs. OSPM may
only take control of capabilities as indicated by the platform by the result of the query.
• Bit [1] - Always clear (0).
• Bit [2] - Always clear (0).
• Bit [3] - Always clear (0).
• All others - reserved.
Return Value Information
Capabilities Buffer (Buffer) - The platform acknowledges the Capabilities Buffer by returning a buffer of DWORDs
of the same length. Set bits indicate acknowledgment that OSPM may take control of the capability and cleared bits
indicate that the platform either does not support the capability or that OSPM may not assume control.
• Bit [0] - Reserved (not used)
• Bit [1] - _OSC failure. Platform Firmware was unable to process the request or query. Capabilities bits may
have been masked.
• Bit [2] - Unrecognized UUID. This bit is set to indicate that the platform ﬁrmware does not recognize the UUID
passed in via Arg0. Capabilities bits are preserved.
• Bit [3] - Unrecognized Revision. This bit is set to indicate that the platform ﬁrmware does not recognize the
Revision ID passed in via Arg1. Capabilities bits beyond those comprehended by the ﬁrmware will be masked.
• Bit [4] - Capabilities Masked. This bit is set to indicate that capabilities bits set by driver software have been
cleared by platform ﬁrmware.
Note: OSPM must not use the results of _OSC evaluation to choose a compatible device driver. OSPM must use
_HID, _CID, or native enumerable bus device identiﬁcation mechanisms to select an appropriate driver for a device.
The platform may issue a Notify**(device, 0x08) to inform OSPM to re-evaluate _OSC when the availability of
feature control changes. Platforms must **not **rely, however, on OSPM to evaluate _OSC after issuing a
**Notify for proper operation as OSPM cannot guarantee the presence of a target entity to receive and process the
Notify for the device. For example, a device driver for the device may not be loaded at the time the Notify is signaled.
Further, the issuance and processing rules for notiﬁcation of changes in the Capabilities Buffer is device speciﬁc. As
such, the allowable behavior is governed by device speciﬁcations either in ACPI-Deﬁned Devices and Device-Speciﬁc
Objects , for ACPI-deﬁne devices, or other OEM, IHV , or device governing body’s’ device speciﬁcations.
It is permitted for _OSC to return all bits in the Capabilities Buffer cleared. An example of this is when signiﬁcant
time is required to disable platform-based feature support. The platform may then later issue a Notify to tell OSPM to
re-evaluate _OSC to take over native control. This behavior is also device speciﬁc but may also rely on speciﬁc OS
In general, platforms should support both OSPM taking and relinquishing control of speciﬁc feature support via
multiple invocations of _OSC but the required behavior may vary on a per device basis.
6.2. Device Conﬁguration Objects 362Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Since platform context is lost when the platform enters the S4 sleeping state, OSPM must re-evaluate _OSC upon
wake from S4 to restore the previous platform state. This requirement will vary depending on the device speciﬁc
_OSC functionality.
6.2.11.1 Rules for Evaluating _OSC
This section deﬁnes when and how the OS must evaluate _OSC, as well as restrictions on ﬁrmware implementation.
6.2.11.1.1 Query Flag
If the Query Support Flag (Capabilities DWORD 1, bit 0 ) is set by the OS when evaluating _OSC, no hardware
settings are permitted to be changed by ﬁrmware in the context of the _OSC call. It is strongly recommended that the
OS evaluate _OSC with the Query Support Flag set until _OSC returns the Capabilities Masked bit clear, to negotiate
the set of features to be granted to the OS for native support; a platform may require a speciﬁc combination of features
to be supported natively by an OS before granting native control of a given feature. After negotiation with the query
ﬂag set, the OS should evaluate without it so that any negotiated values can be made effective to hardware.
6.2.11.1.2 Evaluation Conditions
The OS must evaluate _OSC under the following conditions:
During initialization of any driver that provides native support for features described in the section above. These
features may be supported by one or many drivers, but should only be evaluated by the main bus driver for that
hierarchy. Secondary drivers must coordinate with the bus driver to install support for these features. Drivers may not
relinquish control of features previously obtained (i.e., bits set in Capabilities DWORD3 after the negotiation process
must be set on all subsequent negotiation attempts.)
When a Notify(<device>, 8) is delivered to the PCI Host Bridge device.
Upon resume from S4. Platform ﬁrmware will handle context restoration when resuming from S1-S3.
6.2.11.1.3 Sequence of _OSC Calls
The following rules govern sequences of calls to _OSC that are issued to the same host bridge and occur within the
same boot.
• The OS is permitted to evaluate _OSC an arbitrary number of times.
• If the OS declares support of a feature in the Support Field in one call to _OSC, then it must preserve the set
state of that bit (declaring support for that feature) in all subsequent calls.
• If the OS is granted control of a feature in the Control Field in one call to _OSC, then it must preserve the set
state of that bit (requesting that feature) in all subsequent calls.
• Firmware may not reject control of any feature it has previously granted control to.
• There is no mechanism for the OS to relinquish control of a feature previously requested and granted.
6.2. Device Conﬁguration Objects 363Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.2.11.2 Platform-Wide OSPM Capabilities
OSPM evaluates \_SB._OSC to convey platform-wide OSPM capabilities to the platform. Argument deﬁnitions are as
follows:
Arguments(4) :
• Arg0 - UUID (Buffer): 0811B06E-4A27-44F9-8D60-3CBBC22E7B48
• Arg1 - Revision ID (Integer): 1
• Arg2 - Count of Entries in Arg3 (Integer): 2
• Arg3 - DWORD capabilities (Buffer):
–First DWORD: as described in Section 6.2.11
–Second DWORD: see the following table.
Table 6.13: Platform-Wide _OSC Capabilities DWORD 2
Bits Field Name Deﬁnition
0 Processor Aggregator Device
SupportThis bit is set if OSPM supports the Processor Aggregator device as
described in Section 8.5
1 _PPC _OST Processing Support This bit is set if OSPM will evaluate the _OST object deﬁned under
a processor as a result of _PPC change notiﬁcation (Notify 0x80).
2 _PR3 Support This bit is set if OSPM supports reading _PR3and using power re-
sources to switch power. Note this handshake translates to an oper-
ating model that the platform and OSPM supports both the power
model containing both D3hot and D3.
3 Insertion / Ejection _OST Pro-
cessing SupportThis bit is set if OSPM will evaluate the _OST object deﬁned under
a device when processing insertion and ejection source event codes.
4 APEI Support This bit is set if OSPM supports the ACPI Platform Error Interfaces.
See Section 18
5 CPPC Support This bit is set if OSPM supports controlling processor performance
via the interfaces described in the _CPC object.
6 CPPC 2 Support This bit is set if OSPM supports revision 2 of the _CPC object.
7 Platform Coordinated Low
Power Idle SupportThis bit is set if OSPM supports platform coordinated low power

idle states (see note below)*.
8 OS Initiated Low Power Idle
SupportThis bit is set if OSPM supports OS initiated low power idle states.
*(see note, below).
9 Fast Thermal Sampling support This bit is set if OSPM supports _TFP.
10 Greater Than 16 p-state support This bit is set if OSPM supports greater than 16 p-states. If clear,
no more than 16 p-states are supported.
11 Generic Event Device support This bit is set if OSPM supports parsing of the generic event device.
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Table 6.13 – continued from previous page
12 Diverse CPPC Highest Opti-
mization Support This bit is set if OSPM can process processor device notiﬁcations
for changes in CPPC Highest Performance. It also indicates
support for optimizing for performance domains with diverse
Highest Performance capabilities.
Potential OS optimizations for diverse CPPC highest performance
include but are not limited to placement of work on speciﬁc logical
processors yielding a performance or power beneﬁt.
Note: These optimizations are independent of the platform’s
existing ability to expose diverse Highest Performance to OSPM as
well as OSPM support for the MADT GICC’s Processor Power
Efﬁciency Class.
13 Interrupt ResourceSource sup-
portThis bit is set if OSPM supports the usage of the ResourceSource in
the extended interrupt descriptor. As part of the handshake provided
through _OSC, the platform will indicate to the OS whether or not
it supports usage of ResourceSource. If not set, the OS may choose
to ignore the ResourceSource parameter in the extended interrupt
14 Flexible Address Space for
CPPC RegistersThis bit is set if OSPM supports any CPPC register being located
in PCC, SystemMemory, SystemIO, or Functional Fixed Hardware
address spaces. If not set, per-register restrictions described in ACPI
Speciﬁcation 6.1 apply.
15 GHES_ASSIST Support This bit is set if OSPM supports the GHES_ASSIS Flag in HEST
Error Structures. See Section 18
16 Multi PCC channel support for
CPPCThe OSPM sets this bit when it supports multiple PCC channels for
the CPPC protocol.
17 Generic Initiator Support This bit is set if OSPM supports the Generic Initiator Afﬁnity Struc-
ture in SRAT.
18 Native USB4 Support The OS sets this bit to indicate support for an OSPM-native USB4
Connection Manager, which handles USB4 connection events and
link management.
19 Battery Charge Limiting Sup-
portThe OS sets this bit to indicate support for Battery Charge Limit-
ing. This bit promises that the platform will advertise “true” state
of charge to the OSPM at all times.
20 PCI BAR Target GAS Support The OS sets this bit to indicate support for the PCI BAR Target GAS
structure, as described in Table 5.2.
21 Platform Runtime Mechanism
SupportThe OS sets this bit to indicate support for the Platform Runtime
Mechanism (PRM). See Links to ACPI-Related Documents (https:
//ueﬁ.org/acpi) under the heading “Platform Runtime Mechanism
Table”.
22 Functional Fixed Hardware The OS sets this bit to indicate support for the usage of Functional
Fixed Hardware (FFixedHW) Operation Regions.
31:23 Reserved (must be 0)
Note: As part of the handshake provided through _OSC, the OS will pass in ﬂags to indicate whether it supports
Platform Coordinated Low Power Idle or OS Initiated Low Power Idle or both (see Section 8.4.3.2), through ﬂags 7
and 8. The platform will indicate which of the modes it supports in its response by clearing ﬂags that are not supported.
If both are supported, the default is platform coordinated and OSPM can switch the platform to OS Initiated via a
processor architecture speciﬁc mechanism. By setting either ﬂag 7 or 8 or both, the OSPM is asserting it supports
any objects associated with Low Power Idle states (see Section 8.4.3.3, Table 8.16, and Section 7.2.5), and supports a
6.2. Device Conﬁguration Objects 365Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Processor Container Device .
of the same length. Set bits indicate acknowledgment and cleared bits indicate that the platform does not support the
6.2.11.3 Operating System Capabilities (_OSC) for USB
Platform hardware and operating systems with support for USB4 require a few controls for passing information back
and forth. The following deﬁnition is used to convey this information.
Along with the Platform-Wide OSPM Capabilities deﬁned in Section 6.2.11.2, this _OSC interface is implemented
within the same scope, and therefore the same _OSC Control Method, using a different UUID value. If the platform
does not support USB4, the UUID deﬁned in this section should not be supported.
Note that if control of any features described in Table 6.15 are granted to OSPM, system ﬁrmware must not attempt to
control any other features not granted to OSPM; only one Connection Manager is permitted to be active at any point
in time. OSPM evaluates \_SB._OSC to manage USB capabilities within the platform. Argument deﬁnitions are as
follows.
Arguments (4):
Arg0 – UUID (Buffer): 23A0D13A-26AB-486C-9C5F-0FFA525A575A
Arg1 – Revision ID (Integer): 1
Arg2 – Count of entries (DWORDS) in Arg3 (Integer): 3
Arg3 – DWORD capabilities buffer:
• First DWORD: As described in Section 6.2.11.1
• Second DWORD: OSPM Support Field for USB. See Table 6.14 for details.
• Third DWORD: OSPM Control Field for USB. See Table 6.15 for details.
Note:: OSPM must re-invoke _OSC during S4 resume.
Table 6.14: OSPM USB Support Field
Support Field Bit
OffsetInterpretation
5:0
OS-Supported USB4 Version: The revision of the USB4 speciﬁcation supported by
OSPM.
0: USB4 Version 1.0
31:6 Reserved
Table 6.15: OSPM USB Control Field
0 USB Tunneling OSPM requests control of USB tunneling across USB4 connections via the
OSPM-native Connection Manager. Once OSPM receives control of this fea-
ture, it must not relinquish support to the platform.
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Table 6.15 – continued from previous page
1 DisplayPort Tunnel-
ingOSPM requests control of DisplayPort tunneling across USB4 connections via
the OSPM-native Connection Manager. Once OSPM receives control of this
feature, it must not relinquish support to the platform.
2 PCI Express Tun-
nelingOSPM requests control of PCI Express tunneling across USB4 connections via
3 Inter-domain USB4 Inter-domain USB4 protocol: OSPM requests control of inter-domain USB4
connections via the OSPM-native Connection Manager. Once OSPM receives
control of this feature, it must not relinquish support to the platform.
31:4 Reserved
Capabilities Buffer (Buffer): The platform acknowledges the Capabilities Buffer by returning a buffer of DWORDs of
the same length. Preserved bits in the Control Field convey control from the platform to OSPM, while masked/cleared
bits in the Control Field indicate that the platform does not permit OSPM control of the respective capability or feature.
6.2.12 _PRS (Possible Resource Settings)
This optional object evaluates to a byte stream that describes the possible resource settings for the device. When
describing a platform, specify a _PRS for all the conﬁgurable devices. Static (non-conﬁgurable) devices do not specify
a _PRS object. The information in this package is used by OSPM to select a conﬂict-free resource allocation without
user intervention. This method must not reference any operation regions that have not been declared available by a
_REG method.
The format of the data in a _PRS object follows the same format as the _CRS object (for more information, see Section
6.2.2).
If the device is disabled when _PRS is called, it must remain disabled.
None
A Buffer containing a Resource Descriptor byte stream
6.2.13 _PRT (PCI Routing Table)
PCI interrupts are inherently non-hierarchical. PCI interrupt pins are wired to interrupt inputs of the interrupt con-
trollers. The _PRT object provides a mapping from PCI interrupt pins to the interrupt inputs of the interrupt controllers.
The _PRT object is required under all PCI root bridges. _PRT evaluates to a package that contains a list of packages,
each of which describes the mapping of a PCI interrupt pin.
None
APackage containing variable-length list of PCI interrupt mapping packages, as described below
Note: The PCI function number in the Address ﬁeld of the _PRT packages must be 0xFFFF, indicating “any” function
number or “all functions”.
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6.2.2).
None
None
The _PRT mapping packages have the ﬁelds listed in the table below.
Table 6.16: Mapping Fields
Field Type Description
Address DWORD The address of the device (uses the same format as _ADR).
Pin Byte The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD).
Source NamePath Or
ByteName of the device that allocates the interrupt to which the above pin is connected.
The name can be a fully qualiﬁed path, a relative path, or a simple name segment that
utilizes the namespace search rules. Note: This ﬁeld is a NamePath and not a String
literal, meaning that it should not be surrounded by quotes. If this ﬁeld is the integer
constant Zero (or a Byte value of 0), then the interrupt is allocated from the global
interrupt pool.
Source
IndexDWORD Index that indicates which resource descriptor in the resource template of the device
pointed to in the Source ﬁeld this interrupt is allocated from. If the Source ﬁeld is the
Byte value zero, then this ﬁeld is the global system interrupt number to which the pin
is connected.
There are two ways that _PRT can be used. Typically, the interrupt input that a given PCI interrupt is on is conﬁgurable.
For example, a given PCI interrupt might be conﬁgured for either IRQ 10 or 11 on an 8259 interrupt controller. In this
model, each interrupt is represented in the ACPI namespace as a PCI Interrupt Link Device.
These objects have _PRS, _CRS, _SRS, and _DIS control methods to allocate the interrupt. Then, OSPM handles the
interrupts not as interrupt inputs on the interrupt controller, but as PCI interrupt pins. The driver looks up the device’s
pins in the _PRT to determine which device objects allocate the interrupts. To move the PCI interrupt to a different
interrupt input on the interrupt controller, OSPM uses _PRS, _CRS, _SRS, and _DIS control methods for the PCI
Interrupt Link Device.
In the second model, the PCI interrupts are hardwired to speciﬁc interrupt inputs on the interrupt controller and are not
conﬁgurable. In this case, the Source ﬁeld in _PRT does not reference a device, but instead contains the value zero,
and the Source Index ﬁeld contains the global system interrupt to which the PCI interrupt is hardwired.
6.2.13.1 Example: Using _PRT to Describe PCI IRQ Routing
The following example describes two PCI slots and a PCI video chip. Notice that the interrupts on the two PCI slots
are wired differently (barber-poled):
Device(LNKA){
Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
Name(_UID, 1)
Name(_PRS, ResourceTemplate(){
Interrupt(ResourceProducer,...) {10,11} // IRQs 10,11
})
Method(_DIS) {...}
Method(_CRS) {...}
Method(_SRS, 1) {...}
}
Device(LNKB){
Name(_UID, 2)
Interrupt(ResourceProducer,...) {11,12} // IRQs 11,12
})
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}
Device(LNKC){
Name(_UID, 3)
Interrupt(ResourceProducer,...) {12,14} // IRQs 12,14
})
}
Device(LNKD){
Name(_UID, 4)
Interrupt(ResourceProducer,...) {10,15} // IRQs 10,15
})
}
Device(PCI0){
...
Name(_PRT, Package{ // A fully qualified pathname can be used, or a
// osimple name segment utilizing the search rules.
Package{0x0004FFFF, 0, \\_SB_.LNKA, 0}, // Slot 1, INTA
Package{0x0004FFFF, 1, \\_SB_.LNKB, 0}, // Slot 1, INTB
Package{0x0004FFFF, 2, \\_SB_.LNKC, 0}, // Slot 1, INTC
Package{0x0004FFFF, 3, \\_SB_.LNKD, 0}, // Slot 1, INTD
Package{0x0005FFFF, 0, LNKB, 0}, // Slot 2, INTA
Package{0x0005FFFF, 1, LNKC, 0}, // Slot 2, INTB
Package{0x0005FFFF, 2, LNKD, 0}, // Slot 2, INTC
Package{0x0005FFFF, 3, LNKA, 0}, // Slot 2, INTD
Package{0x0006FFFF, 0, LNKC, 0} // Video, INTA
})
}
}
6.2.14 _PXM (Proximity)
This optional object is used to describe proximity domain associations within a machine. _PXM evaluates to an integer
that identiﬁes a device as belonging to a Proximity Domain deﬁned in the System Resource Afﬁnity Table (SRAT).
OSPM assumes that two devices in the same proximity domain are tightly coupled. OSPM could choose to optimize
its behavior based on this. For example, in a system with four processors and six memory devices, there might be
two separate proximity domains (0 and 1), each with two processors and three memory devices. In this case, the OS
may decide to run some software threads on the processors in proximity domain 0 and others on the processors in
proximity domain 1. Furthermore, for performance reasons, it could choose to allocate memory for those threads from
the memory devices inside the proximity domain common to the processor and the memory device rather than from a
memory device outside of the processor’s proximity domain.
Children of a device belong to the same proximity domain as their parent unless they contain an overriding _PXM.
Proximity domains do not imply any ejection relationships.
OSPM shall make no assumptions about the proximity or nearness of different proximity domains. The difference
6.2. Device Conﬁguration Objects 369Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
between two integers representing separate proximity domains does not imply distance between the proximity domains
(in other words, proximity domain 1 is not assumed to be closer to proximity domain 0 than proximity domain 6).
If the Local APIC ID / Local SAPIC ID / Local x2APIC ID or the GICC ACPI Processor UID of a dynamically added
processor is not present in the System Resource Afﬁnity Table (SRAT), a _PXM object must exist for the processor’s
device or one of its ancestors in the ACPI Namespace. See Section 5.2.16 for more information.
None
AnInteger (DWORD) containing a proximity domain identiﬁer.
6.2.15 _SLI (System Locality Information)
The System Locality Information Table (SLIT) table deﬁned in Generic Initiator Afﬁnity Structure provides relative
distance information between all System Localities for use during OS initialization.
The value of each Entry[ i,j] in the SLIT table, where i represents a row of a matrix and jrepresents a column of a
matrix, indicates the relative distances from System Locality / Proximity Domain i to every other System Locality jin
Thei,jrow and column values correlate to the value returned by the _PXM object in the ACPI namespace. See _PXM
(Proximity) for more information.
Dynamic runtime reconﬁguration of the system may cause the distance between System Localities to change.
_SLI is an optional object that enables the platform to provide the OS with updated relative System Locality distance
information at runtime. _SLI provide OSPM with an update of the relative distance from System Locality i to all other
System Localities in the system.
None
ABuffer containing a system locality information table
If System Locality i >= N, where N is the number of System Localities, the _SLI method returns a buffer that contains
these relative distances:
[(i, 0), (i, 1), ..., (i, i-1), (i, i), (0, i), (1, i), ...(i-1, i), (i, i)]
If System Locality i < N, the _SLI method returns a buffer that contains these relative distances:
[(i, 0), (i, 1), ..., (i, i), ...,(i, N-1), (0, i), (1, i),...(i, i), ..., (N-1, i)]
Note: (i, i) is always a value of 10.
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Fig. 6.5: System Locality information Table
The System Locality Information Table diagrams a 4-node system where the nodes are numbered 0 through 3 (Node
n = Node 3) and the granularity is at the node level for the NUMA distance information. In this example we assign
System Localities / Proximity Domain numbers equal to the node numbers (0-3). The NUMA relative distances
between proximity domains as implemented in this system are described in the matrix represented in Example Relative
Distances Between Proximity Domains . Proximity Domains are represented by the numbers in the top row and left
column. Distances are represented by the values in cells internal in the table from the domains.
Table 6.17: Example Relative Distances Between Proximity Domains
ProximityDomain 0 1 2 3
0 10 15 20 18
1 15 10 16 24
2 20 16 10 12
3 18 24 12 10
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An example of these distances between proximity domains encoded in a System Locality Information Table for con-
sumption by OSPM at boot time is described in the table below.
Table 6.18: Example System Locality Information Table
Field Byte

0 10 15 20 18
1 15 10 16 24
2 20 16 10 12
3 18 24 12 10
Field Byte
Header
Signature 4 0 ‘SLIT’.
Length 4 4 60
OEM Table ID 8 16 For the System Locality Information Table, the table ID
is the manufacturer model ID.
OEM Revision 4 24 OEM revision of System Locality Information Table for
supplied OEM Table ID.
Creator ID 4 28 Vendor ID of utility that created the table. For the
DSDT, RSDT, SSDT, and PSDT tables, this is the ID
for the ASL Compiler.
Creator Revision 4 32 Revision of utility that created the table. For the DSDT,
RSDT, SSDT, and PSDT tables, this is the revision for
Creator Revision
Number of System Localities 8 36 4
Entry[0][0] 1 44 10
Entry[0][1] 1 45 15
Entry[0][2] 1 46 20
Entry[0][3] 1 47 18
Entry[1][0] 1 48 15
Entry[1][1] 1 49 10
Entry[1][2] 1 50 16
Entry[1][3] 1 51 24
Entry[2][0] 1 52 20
Entry[2][1] 1 53 16
Entry[2][2] 1 54 10
Entry[2][3] 1 55 12
Entry[3][0] 1 56 18
Entry[3][1] 1 57 24
Entry[3][2] 1 58 12
Entry[3][3] 1 59 10
If a new “Node 4” is added, then the following table represents the updated system’s NUMA relative distances of
proximity domains.
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Table 6.19: Example Relative Distances Between Proximity Domains
- 5 Node
Proximity Domain 0 1 2 3 4
0 10 15 20 18 17
1 15 10 16 24 21
2 20 16 10 12 14
3 18 24 12 10 23
4 17 21 14 23 10
The new node’s _SLI object would evaluate to a buffer containing [17,21,14,23,10,17,21,14,23,10].
Note: Some systems support interleave memory across the nodes. The SLIT representation of these systems is
implementation speciﬁc.
6.2.16 _SRS (Set Resource Settings)
This optional control method takes one byte stream argument that speciﬁes a new resource allocation for a device.
The resource descriptors in the byte stream argument must be speciﬁed exactly as listed in the _CRS byte stream -
meaning that the identical resource descriptors must appear in the identical order, resulting in a buffer of exactly the
same length. Optimizations such as changing an IRQ descriptor to an IRQNoFlags descriptor (or vice-versa) must not
be performed. Similarly, changing StartDependentFn to StartDependentFnNoPri is not allowed. A _CRS object can
be used as a template to ensure that the descriptors are in the correct format. For more information, see the _CRS
object deﬁnition.
The settings must take effect before the _SRS control method returns.
This method must not reference any operation regions that have not been declared available by a _REG method.
If the device is disabled, _SRS enables the device at the speciﬁed resources. _SRS is not used to disable a device; use
the _DIS control method instead.
Arg0 - A Buffer containing a Resource Descriptor byte stream
None
6.2.17 _CCA (Cache Coherency Attribute)
The _CCA object returns whether or not a bus-master device supports hardware managed cache coherency. Expected
values are 0 to indicate it is not supported, and 1 to indicate that it is supported. All other values are reserved.
On platforms for which existing default cache-coherency behavior of the OS is not adequate, _CCA enables the OS to
adapt to the differences. If used, _CCA must be included under all bus-master-capable devices deﬁned as children of
\_SB, to ensure that the operating system knows when it can rely on hardware managed cache coherency. The value
of _CCA is inherited by all descendants of these devices, so it need not be repeated for their children devices and will
be ignored by OSPM if it is provided there. This includes slave devices on a shared DMA controller; thus these DMA
controllers must also be deﬁned in the namespace under the System Bus and include a _CCA object.
If a device indicates it does not have hardware cache coherency support, then OSPM must use a software cache ﬂushing
algorithm to ensure stale or invalid data is not accessed from the caches.
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__CCA objects are only relevant for devices that can access CPU-visible memory, such as devices that are DMA
capable. On ARM based systems, the _CCA object must be supplied all such devices. On Intel platforms, if the _CCA
object is not supplied, the OSPM will assume the devices are hardware cache coherent.
None
AnInteger indicating the device’s support for hardware cache coherency:
0 - The device does not have hardware managed cache coherency
1 - The device has hardware managed cache coherency
Other Values - Reserved
Note: There are restrictions related to when this object is evaluated which have implications for implementing this
object as a control method. The _CCA method must only access Operation Regions that have been indicated to be
available as deﬁned by the _REG method. The _REG method is described in _REG (Region) .
6.2.17.1 _CCA Example ASL:
...
Device (XHCI) {
...
Name (_CCA, ZERO) // Cache-incoherent bus-master, child of \\_SB
...
}
...
Device (PCI0) { // Root PCI Bus
...
Name (_CCA, ONE) // Cache-coherent bus-master, child of \\_SB
...
Device (PRT0) {
... // Bus-master-capable, not a child of \\_SB
... // Will inherit coherency from PCI0, no \_CCA required
Device (NIC0) {
... // Will inherit coherency from PRT0, no \_CCA required
}
}
}
...
Device (SDHC) {
...
Name (_CCA, ONE) // Cache-coherent bus-master-capable, child of \\_SB
...
}
...
Device (GPIO) {
... // Not bus-master-capable
... // \_CCA not valid
}
...
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Device (DMAC) {
... // DMA controller; \_CCA must be specified
Name (_CCA, ONE) // Cache coherent bus-master, child of \\_SB
...
}
...
Device (SPI1) {
...
{
FixedDMA(...) // Sharing the DMA, thus inherits coherency from it
...
...
})
}
}
6.2.18 _HMA(Heterogeneous Memory Attributes)
The Heterogeneous Memory Attributes Table (HMAT) deﬁned in Heterogeneous Memory Attribute Table (HMAT)
provides Heterogeneous Memory Attributes. Dynamic runtime reconﬁguration of the system may cause proximities
domains or memory attributes to change. If the “Reservation Hint” is set, new HMAT update shall not reset the
“Reservation Hint” unless the memory range is removed.
_HMA is an optional object that enables the platform to provide the OS with updated Heterogeneous Memory At-
tributes information at runtime. _HMA provides OSPM with the latest HMAT in entirety overriding existing HMAT.
None
ABuffer containing entire HMAT.
Example ASL for _HMA usage:
Device (Dev1) {
...
}
Device (Dev2) {
...
}
Method (_HMA, 0) {
Return (HMAD)
}
} // end of \\_SB scope
6.2. Device Conﬁguration Objects 375Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.3 Device Insertion, Removal, and Status Objects
The objects deﬁned in this section provide mechanisms for handling dynamic insertion and removal of devices and for
determining device and notiﬁcation processing status.
Device insertion and removal objects are also used for docking and undocking mobile platforms to and from a pe-
ripheral expansion dock. These objects give information about whether or not devices are present, which devices are
physically in the same device (independent of which bus the devices live on), and methods for controlling ejection or
interlock mechanisms.
The system is more stable when removable devices have a software-controlled, VCR-style ejection mechanism instead
of a “surprise-style” ejection mechanism. In this system, the eject button for a device does not immediately remove
the device, but simply signals the operating system. OSPM then shuts down the device, closes open ﬁles, unloads the
driver, and sends a command to the hardware to eject the device.
1. If the device is physically inserted while the system is in the working state (in other words, hot insertion), the
hardware generates a general-purpose event.
2. The control method servicing the event uses the Notify(device,0) command to inform OSPM of the bus that the
new device is on or the device object for the new device. If the Notify command points to the device object for
the new device, the control method must have changed the device’s status returned by _STA to indicate that the
device is now present. The performance of this process can be optimized by having the object of the Notify as
close as possible, in the namespace hierarchy, to where the new device resides. The Notify command can also
be used from the _WAK control method (see Section 7.4.5) to indicate device changes that may have occurred
while the system was sleeping. For more information about the Notify command, see Section 5.6.6.
3. OSPM uses the identiﬁcation and conﬁguration objects to identify, conﬁgure, and load a device driver for the

new device and any devices found below the device in the hierarchy.
4. If the device has a _LCK control method, OSPM may later run this control method to lock the device.
The new device referred to in step 2 need not be a single device, but could be a whole tree of devices. For example, it
could point to the PCI-PCI bridge docking connector. OSPM will then load and conﬁgure all devices it found below
that bridge. The control method can also point to several different devices in the hierarchy if the new devices do not
all live under the same bus. (in other words, more than one bus goes through the connector).
For removing devices, ACPI supports both hot removal (system is in the S0 state), and warm removal (system is in a
sleep state: S1-S4). This is done using the _EJx control methods. Devices that can be ejected include an _EJx control
method for each sleeping state the device supports (a maximum of 2 _EJx objects can be listed). For example, hot
removal devices would supply an _EJ0; warm removal devices would use one of _EJ1-EJ4. These control methods
are used to signal the hardware when an eject is to occur.
The sequence of events for dynamically removing a device goes as follows:
1. The eject button is pressed and generates a general-purpose event. (If the system was in a sleeping state, it
should wake the system).
2. The control method for the event uses the Notify(device, 3) command to inform OSPM which speciﬁc device
the user has requested to eject. Notify does not need to be called for every device that may be ejected, but for
the top-level device. Any child devices in the hierarchy or any ejection-dependent devices on this device (as
described by _EJD, below) are automatically removed.
3. The OS shuts down and unloads devices that will be removed.
4. If the device has a _LCK control method, OSPM runs this control method to unlock the device.
5. The OS looks to see what _EJx control methods are present for the device. If the removal event will cause the
system to switch to battery power (in other words, an undock) and the battery is low, dead, or not present, OSPM
uses the lowest supported sleep state _EJx listed; otherwise it uses the highest state _EJx. Having made this
decision, OSPM runs the appropriate _EJx control method to prepare the hardware for eject.
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6. Warm removal requires that the system be put in a sleep state. If the removal will be a warm removal, OSPM
puts the system in the appropriate Sx state. If the removal will be a hot removal, OSPM skips to step 8, below.
7. For warm removal, the system is put in a sleep state. Hardware then uses any motors, and so on, to eject the
device. Immediately after ejection, the hardware transitions the system to S0. If the system was sleeping when
the eject notiﬁcation came in, the OS returns the system to a sleeping state consistent with the user’s wake
settings.
8. OSPM calls _STA to determine if the eject successfully occurred. (In this case, control methods do not need to
use the Notify(device,3) command to tell OSPM of the change in _STA) If there were any mechanical failures,
_STA returns 3: device present and not functioning, and OSPM informs the user of the problem.
Note: This mechanism is the same for removing a single device and for removing several devices, as in an undock.
ACPI does not disallow surprise-style removal of devices; however, this type of removal is not recommended because
system and data integrity cannot be guaranteed when a surprise-style removal occurs. Because the OS is not informed,
its device drivers cannot save data buffers and it cannot stop accesses to the device before the device is removed. To
handle surprise-style removal, a general-purpose event must be raised. Its associated control method must use the
Notify command to indicate which bus the device was removed from.
The device insertion and removal objects are listed in the table below.
Table 6.20: Device Insertion, Removal, and Status Objects
_EDL Object that evaluates to a package of namespace references of device objects that depend on the
device containing _EDL.
_EJD Object that evaluates to the name of a device object on which a device depends. Whenever the
named device is ejected, the dependent device must receive an ejection notiﬁcation.
_EJx Control method that ejects a device.
_LCK Control method that locks or unlocks a device.
_OST Control method invoked by OSPM to convey processing status to the platform.
_RMV Object that indicates that the given device is removable.
_STA Control method that returns a device’s status.
6.3.1 _EDL (Eject Device List)
This object evaluates to a package of namespace references containing the names of device objects that depend on the
device under which the _EDL object is declared. This is primarily used to support docking stations. Before the device
under which the _EDL object is declared may be ejected, OSPM prepares the devices listed in the _EDL object for
physical removal.
None
A variable-length Package containing a list of namespace references
Before OSPM ejects a device via the device’s _EJx methods, all dependent devices listed in the package returned by
_EDL are prepared for removal. Notice that _EJx methods under the dependent devices are not executed.
When describing a platform that includes a docking station, an _EDL object is declared under the docking station
device. For example, if a mobile system can attach to two different types of docking stations, _EDL is declared under
6.3. Device Insertion, Removal, and Status Objects 377Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
both docking station devices and evaluates to the packaged list of devices that must be ejected when the system is
ejected from the docking station.
An ACPI-compliant OS evaluates the _EDL method just prior to ejecting the device.
6.3.2 _EJD (Ejection Dependent Device)
This object is used to specify the name of a device on which the device, under which this object is declared, is
dependent. This object is primarily used to support docking stations. Before the device indicated by _EJD is ejected,
OSPM will prepare the dependent device (in other words, the device under which this object is declared) for removal.
None
AString containing the device name
_EJD is evaluated once when the ACPI table loads. The EJx methods of the device indicated by _EJD will be used to
eject all the dependent devices. A device’s dependents will be ejected when the device itself is ejected.
Note: OSPM will not execute a dependent device’s _EJx methods when the device indicated by _EJD is ejected.
When describing a platform that includes a docking station, usually more than one _EJD object will be needed. For
example, if a dock attaches both a PCI device and an ACPI-conﬁgured device to a mobile system, then both the PCI
device description package and the ACPI-conﬁgured device description package must include an _EJD object that
evaluates to the name of the docking station (the name speciﬁed in an _ADR or _HID object in the docking station’s
description package). Thus, when the docking connector signals an eject request, OSPM ﬁrst attempts to disable and
unload the drivers for both the PCI and ACPI conﬁgured devices.
Note: An ACPI 1.0 OS evaluates the _EJD methods only once during the table load process. This greatly re-
stricts a table designer’s freedom to describe dynamic dependencies such as those created in scenarios with multiple
docking stations. This restriction is illustrated in the example below; the _EJD information supplied via and ACPI
1.0-compatible namespace omits the IDE2 device from DOCK2’s list of ejection dependencies. Starting in ACPI 2.0,
OSPM is presented with a more in-depth view of the ejection dependencies in a system by use of the _EDL methods.
Example
An example use of _EJD and _EDL is as follows:
Scope(\_SB.PCI0) {
Device(DOCK1) { // Pass through dock - DOCK1
Name(_ADR, ...)
Method(_EJ0, 0) {...}
Method(_DCK, 1) {...}
Name(_BDN, ...)
Method(_STA, 0) {0xF}
Name(_EDL, Package( ) { // DOCK1 has two dependent devices - IDE2 and CB2
\\_SB.PCI0.IDE2,
\\_SB.PCI0.CB2})
}
Device(DOCK2) { // Pass through dock - DOCK2
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Method(_STA, 0) {0x0}
Name(_EDL, Package( ) { // DOCK2 has one dependent device - IDE2
\\_SB.PCI0.IDE2})
}
Device(IDE1) { // IDE Drive1 not dependent on the dock
}
Device(IDE2) { // IDE Drive2
Name(_EJD,"\\_SB.PCI0.DOCK1") // Dependent on DOCK1
}
Device(CB2) { // CardBus Controller
}
} // end \\_SB.PCIO
6.3.3 _EJx (Eject)

}
}
}
}
}
These control methods are optional and are supplied for devices that support a software-controlled VCR-style ejection
mechanism or that require an action be performed such as isolation of power/data lines before the device can be
removed from the system. To support warm (system is in a sleep state) and hot (system is in S0) removal, an _EJx
control method is listed for each sleep state from which the device supports removal, where x is the sleeping state
supported. For example, _EJ0 indicates the device supports hot removal; _EJ1-EJ4 indicate the device supports warm
removal.
Arg0 - An Integer containing a device ejection control
0 - Cancel a mark for ejection request (EJ0 will never be called with this value)
1 - Hot eject or mark for ejection
None
For hot removal, the device must be immediately ejected when OSPM calls the _EJ0 control method. The _EJ0 control
method does not return until ejection is complete. After calling _EJ0, OSPM veriﬁes the device no longer exists to
determine if the eject succeeded. For _HID devices, OSPM evaluates the _STA method. For _ADR devices, OSPM
checks with the bus driver for that device.
For warm removal, the _EJ1-_EJ4 control methods do not cause the device to be immediately ejected. Instead, they
set proprietary registers to prepare the hardware to eject when the system goes into the given sleep state. The hardware
ejects the device only after OSPM has put the system in a sleep state by writing to the SLP_EN register. After the
system resumes, OSPM calls _STA to determine if the eject succeeded.
A device object may have multiple _EJx control methods. First, it lists an EJx control method for the preferred sleeping
state to eject the device. Optionally, the device may list an EJ4 control method to be used when the system has no
power (for example, no battery) after the eject. For example, a hot-docking notebook might list _EJ0 and _EJ4.
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6.3.4 _LCK (Lock)
This control method is optional and is required only for a device that supports a software-controlled locking mech-
anism. When the OS invokes this control method, the associated device is to be locked or unlocked based upon the
value of the argument that is passed. On a lock request, the control method must not complete until the device is
completely locked.
Arg0 - An Integer containing a device lock control
0 - Unlock the device
1 - Lock the device
None
When describing a platform, devices use either a _LCK control method or an _EJx control method for a device.
6.3.5 _OST (OSPM Status Indication)
This object is an optional control method that is invoked by OSPM to indicate processing status to the platform.
During device ejection, device hot add, Error Disconnect Recover, or other event processing, OSPM may need to
perform speciﬁc handshaking with the platform. OSPM may also need to indicate to the platform its inability to
complete a requested operation; for example, when a user presses an ejection button for a device that is currently
in use or is otherwise currently incapable of being ejected. In this case, the processing of the ACPI Eject Request
notiﬁcation by OSPM fails. OSPM may indicate this failure to the platform through the invocation of the _OST control
method. As a result of the status notiﬁcation indicating ejection failure, the platform may take certain action including
reissuing the notiﬁcation or perhaps turning on an appropriate indicator light to signal the failure to the user.
Arguments: (3)
Arg0 - An Integer containing the source event
Arg1 - An Integer containing the status code
Arg2 - A Buffer containing status information
None
Argument Information:
Arg0 - source_event: DWordConst
If the value of source_event is <= 0xFF, this argument is the ACPI notiﬁcation value whose processing generated the
status indication. This is the value that was passed into the Notify operator.
If the value of source_event is 0x100 or greater then the OSPM status indication is a result of an OSPM action as
indicated in OST Source Event Codes . For example, a value of 0x103 will be passed into _OST for this argument upon
the failure of a user interface invoked device ejection.
If OSPM is unable to identify the originating notiﬁcation value, OSPM invokes _OST with a value that contains all
bits set (ones) for this parameter.
Arg1 – Status Code: DWordConst. OSPM indicates a notiﬁcation value speciﬁc status. See Table 6.22, Table 6.23,
and Table 6.25 for status code descriptions.
Arg2 - A buffer containing detailed OSPM-speciﬁc information about the status indication. This argument may be
null.
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Table 6.21: OST Source Event Codes
Source Event
CodeDescription
0-0xFF Reserved for Notiﬁcation Values
0x100 Operation System Shutdown Processing
0x101-0x102 Reserved
0x103 Ejection Processing
0x104-0x1FF Reserved
0x200 Insertion Processing
0x201-
0xFFFFFFFFReserved
Table 6.22: General Processing Status Codes
Status Code Description
0 Success
1 Non-speciﬁc failure
2 Unrecognized Notify Code
3-0x7F Reserved
0x80-
0xFFFFFFFFNotiﬁcation value speciﬁc status codes
Table 6.23: Operating System Shutdown Processing (Source Events :
0x100) Status Codes
0x80 OS Shutdown Request denied
0x81 OS Shutdown in progress
0x82 OS Shutdown completed
0x83 OS Graceful Shutdown not supported
0x84-
6.3.5.1 Processing Sequence for Graceful Shutdown Request:
Following receipt of the Graceful Shutdown Request (see Table 5.188, value 0x81), the OS will be responsible for
responding with one of the following status codes:
• 0x80 (OS Shutdown Request denied) - This value will be sent if the OS is not capable of performing a graceful
shutdown.
• 0x81 (OS Shutdown in progress) - The OS has initiated the graceful shutdown procedure.
• 0x83 (OS Graceful Shutdown not supported) - The OS does not support the Graceful Shutdown Request.
If the OS does initiate a graceful shutdown it should continue to generate the “OS Shutdown in progress” message
(_OST source event 0x100 status code 0x81) every 10 seconds. This functions as a heartbeat so that the service which
requested the graceful shutdown knows that the request is currently being processed. The platform should assume that
the OS shutdown is not proceeding if it does not receive the “OS Shutdown in progress” message for 60 seconds.
When the graceful shutdown procedure has completed the OSPM will send the “OS Shutdown completed” message
and then transition the platform to the G2 “soft-off” power state.
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Table 6.24: Ejection Request / Ejection Processing (Source Events:
0x03 and 0x103) Status Codes
0x80 Device ejection not supported by OSPM
0x81 Device in use by application
0x82 Device Busy
0x83 Ejection dependency is busy or not supported for ejection by OSPM
0x84 Ejection is in progress (pending)
0x85-
Table 6.25: Insertion Processing (Source Event: 0x200) Status Codes
0x80 Device insertion in progress (pending)
0x81 Device driver load failure
0x82 Device insertion not supported by OSPM
0x83-0x8F Reserved
0x90-0x9F Insertion failure - Resources Unavailable as described by the following bit encodings: Bit [3] Bus
or Segment Numbers Bit [2] Interrupts Bit [1] I/O Bit [0] Memory
0xA0-
It is possible for the platform to issue multiple notiﬁcations to OSPM and for OSPM to process the notiﬁcations
asynchronously. As such, OSPM may invoke _OST for notiﬁcations independent of the order the notiﬁcation are
conveyed by the platform or by software to OSPM.
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The ﬁgure below provides and example event ﬂow of device ejection on a platform employing the _OST object.
Fig. 6.6: Device Ejection Flow Example Using _OST
Note: To maintain compatibility with OSPM implementations of previous revisions of the ACPI speciﬁcation, the
platform must not rely on OSPM’s evaluation of the _OST object for proper platform operation.
6.3. Device Insertion, Removal, and Status Objects 383Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Example ASL for _OST usage:
External (\_SB.PCI4, DeviceObj)
Scope(\_SB.PCI4) {
OperationRegion(LED1, SystemIO, 0x10C0, 0x20)
Field(LED1, AnyAcc, NoLock, Preserve)
{ // LED controls
S0LE, 1, // Slot 0 Ejection Progress LED
S0LF, 1, // Slot 0 Ejection Failure LED
S1LE, 1, // Slot 1 Ejection Progress LED
S1LF, 1, // Slot 1 Ejection Failure LED
S2LE, 1, // Slot 2 Ejection Progress LED
S2LF, 1, // Slot 2 Ejection Failure LED

S3LE, 1, // Slot 3 Ejection Progress LED
S3LF, 1 // Slot 3 Ejection Failure LED
}
Device(SLT3) { // hot plug device
Name(_ADR, 0x000C0003)
Method(_OST, 3, Serialized) { // OS calls \_OST with notify code 3 or 0x103
// and status codes 0x80-0x83
// to indicate a hot remove request failure.
// Status code 0x84 indicates an ejection
// request pending.
If(LEqual(Arg0,Ones)) // Unspecified event
{
// Perform generic event processing here
}
Switch(And(Arg0,0xFF)) // Mask to retain low byte
{
Case(0x03) // Ejection request
{
Switch(Arg1)
{
Case(Package(){0x80, 0x81, 0x82, 0x83})
{ // Ejection Failure for some reason
Store(Zero, ^^S3LE) // Turn off Ejection Progress LED
Store(One, ^^S3LF) // Turn on Ejection Failure LED
}
Case(0x84) // Eject request pending
{
Store(One, ^^S3LE) // Turn on Ejection Request LED
Store(Zero, ^^S3LF) // Turn off Ejection Failure LED
}
}
}
}
} // end \_OST
Method(_EJ0, 1) // Successful ejection sequence
{
}
} // end SLT3
} // end scope \\_SB.PCI4
Scope (\_GPE)
{
Method(_E13)
{
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Store(One, \\_SB.PCI4.S3LE) // Turn on ejection request LED
Notify(\_SB.PCI4.SLT3, 3) // Ejection request driven from GPE13
}
}
6.3.5.2 Processing Sequence for Error Disconnect Recover
If the OS attempts recovery operation following the receipt of the Error Disconnect Recover Request (see IPMI Status
Codes , value 0x0F) the OS will be responsible for invoking _OST with one of the following status codes in the lower
word of Arg1:
• 0x80 (Success) -This value will be sent if the OS successfully recovers all the child devices affected by Error
Disconnect Recover, reconﬁgures then and brings them back to functional state. All child devices are accessible
at the time _OST is evaluated.
• 0x81 (Not recovered) - The OS did not successfully recover one or more child devices that were affected by
Error Disconnect Recover. Access to the child devices affected by Error Disconnect Recover may be unreliable.
The upper word of Arg1 can be used to communicate bus-speciﬁc status information.
6.3.6 _RMV (Remove)
The optional _RMV object indicates to OSPM whether the device can be removed while the system is in the working
state and does not require any ACPI system ﬁrmware actions to be performed for the device to be safely removed from
the system (in other words, any device that only supports surprise-style removal). Any such removable device that
does not have _LCK or _EJx control methods must have an _RMV object. This allows OSPM to indicate to the user
that the device can be removed and to provide a way for shutting down the device before removing it. OSPM will
transition the device into D3 before telling the user it is safe to remove the device.
This method is reevaluated after a device-check notiﬁcation.
None
An Integer containing the device removal status:
0 - The device cannot be removed
1 - The device can be removed
Note: Operating Systems implementing ACPI 1.0 interpret the presence of this object to mean that the device is
removable.
6.3. Device Insertion, Removal, and Status Objects 385Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.3.7 _STA (Device Status)
This object returns the current status of a device, which can be one of the following: enabled, disabled, or removed.
OSPM evaluates the _STA object before it evaluates a device _INI method. The return values of the Present and Func-
tioning bits determines whether _INI should be evaluated and whether children of the device should be enumerated
and initialized. See _INI (Init) . If _INI is not present within the scope of a Device, it is unspeciﬁed whether _STA is
evaluated prior to other objects within the Device scope.
Evaluation of _STA must not cause any change to platform context - it should be viewed as a “read only” operation.
If a device object describes a device that is not on an enumerable bus and the device object does not have an _STA
object, then OSPM assumes that the device is present, enabled, shown in the UI, and functioning.
None
AnInteger containing a device status bitmap:
• Bit [0] - Set if the device is present.
• Bit [1] - Set if the device is enabled and decoding its resources.
• Bit [2] - Set if the device should be shown in the UI.
• Bit [3] - Set if the device is functioning properly (cleared if device failed its diagnostics).
• Bit [4] - Set if the battery is present.
• Bits [31:5] - Reserved (must be cleared).
If bit [0] is cleared, then bit 1 must also be cleared (in other words, a device that is not present cannot be enabled).
A device can only decode its hardware resources if both bits 0 and 1 are set. If the device is not present (bit [0] cleared)
or not enabled (bit [1] cleared), then the device must not decode its resources.
If a device is present in the machine, but should not be displayed in OSPM user interface, bit 2 is cleared. For example,
a notebook could have joystick hardware (thus it is present and decoding its resources), but the connector for plugging
in the joystick requires a port replicator. If the port replicator is not plugged in, the joystick should not appear in the
UI, so bit [2] is cleared.
_STA may return bit 0 clear (not present) with bit [3] set (device is functional). This case is used to indicate a valid
device for which no device driver should be loaded (for example, a bridge device.) Children of this device may be
present and valid. OSPM should continue enumeration below a device whose _STA returns this bit combination.
Bit [4] of _STA applies only to the Control Method Battery Device (PNP0C0A). For all other devices, OSPM must
ignore this bit.
If a device object (including the processor object) does not have an _STA object, then OSPM assumes that all of the
above bits are set (i.e., the device is present, enabled, shown in the UI, and functioning).
If a device is present on an enumerable bus, then _STA must not return 0. In that case, bit[0] must be set and if
the status of the device can be determined through a bus-speciﬁc enumeration and discovery mechanism, it must be
reﬂected by the values of bit[1] and bit[3], even though the OSPM is not required to take them into account.
6.3. Device Insertion, Removal, and Status Objects 386Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4 Resource Data Types for ACPI
The _CRS, _PRS, and _SRS control methods use packages of resource descriptors to describe the resource require-
ments of devices.
6.4.1 ASL Macros for Resource Descriptors
ASL includes some macros for creating resource descriptors. The ASL syntax for these macros is deﬁned in ASL
Operator Reference , along with the other ASL operators.
6.4.2 Small Resource Data Type
A small resource data type may be 2 to 8 bytes in size and adheres to the following format:
Table 6.26: Small Resource Data Type Tag Bit Deﬁnitions
Offset Field Description
Byte 0 Tag Bit [7]: Type-0 (Small item) || Tag Bits [6:3]: Small item name || Tag Bits [2:0]: Length- n
bytes
Bytes 1 to n Data bytes (Length 0 - 7)
The following small information items are currently deﬁned for Plug and Play devices:
Table 6.27: Small Resource Items
Small Item Name Value
Reserved 0x00-0x03
IRQ Format Descriptor 0x04
DMA Format Descriptor 0x05
Start Dependent Functions Descriptor 0x06
End Dependent Functions Descriptor 0x07
I/O Port Descriptor 0x08
Fixed Location I/O Port Descriptor 0x09
Fixed DMA Descriptor 0x0A
Reserved 0x0B-0x0D
Vendor Deﬁned Descriptor 0x0E
End Tag Descriptor 0x0F
6.4.2.1 IRQ Descriptor
Type 0, Small Item Name 0x4, Length = 2 or 3
The IRQ data structure indicates that the device uses an interrupt level and supplies a mask with bits set indicating the
levels implemented in this device. For standard PC-AT implementation there are 15 possible interrupts so a two-byte
ﬁeld is used. This structure is repeated for each separate interrupt required.
Table 6.28: IRQ Descriptor Deﬁnition
Offset Field Name
Byte 0 Value = 0x22 or 0x23 (0010001nB) - Type = 0, Small item name = 0x4, Length = 2 or 3
Byte 1 IRQ mask bits[7:0], _INT Bit [0] represents IRQ0, bit[1] is IRQ1, and so on.
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Table 6.28 – continued from previous page
Byte 2 IRQ mask bits[15:8], _INT Bit [0] represents IRQ8, bit[1] is IRQ9, and so on.
Byte 3
IRQ Information. Each bit, when set, indicates this device is capable of driving a certain type of
interrupt. (Optional–if not included then assume edge sensitive, high true interrupts.) These bits

Byte 3
can be used both for reporting and setting IRQ resources. Note: This descriptor is meant for
describing interrupts that are connected to PIC-compatible interrupt controllers, which can only
be programmed for Active-High-Edge-Triggered or Active-Low-Level-Triggered interrupts.
Any other combination is invalid. The Extended Interrupt Descriptor can be used to describe
other combinations:
Bit [7:6] Reserved (must be 0)
Bit [5] Wake Capability, _WKC
0x0 = Not Wake Capable: This interrupt is not capable of waking the system.
0x1 = Wake Capable: This interrupt is capable of waking the system from a low-power
idle state or a system sleep state.
Bit [4] Interrupt Sharing, _SHR
0x0 = Exclusive: This interrupt is not shared with other devices.
0x1 = Shared: This interrupt is shared with other devices.
Bit [3] Interrupt Polarity, _LL
0 Active-High - This interrupt is sampled when the signal is high, or true
1 Active-Low - This interrupt is sampled when the signal is low, or false.
Bit [2:1] Ignored
Bit [0] Interrupt Mode, _HE
0 Level-Triggered - Interrupt is triggered in response to signal in a low state.
1 Edge-Triggered - Interrupt is triggered in response to a change in signal state from low
to high.
Note: Low true, level sensitive interrupts may be electrically shared, but the process of how this might work is beyond
the scope of this speciﬁcation.
Note: If byte 3 is not included, High true, edge sensitive, non-shareable is assumed.
SeeIRQ (Interrupt Resource Descriptor Macro) for a description of the ASL macros that create an IRQ descriptor.
6.4.2.2 DMA Descriptor
Type 0, Small Item Name 0x5, Length = 2
The DMA data structure indicates that the device uses a DMA channel and supplies a mask with bits set indicating the
channels actually implemented in this device. This structure is repeated for each separate channel required.
Table 6.29: DMA Descriptor Deﬁnition
Byte 0 Value = 0x2A (00101010B) - Type = 0, Small item name = 0x5, Length = 2
Byte 1 DMA channel mask bits [7:0] (channels 0 - 7), _DMA - Bit [0] is channel 0, etc.
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Table 6.29 – continued from previous page
Byte 2
Bit [7] Reserved (must be 0)
Bits [6:5] DMA channel speed supported, _TYP:
00 Indicates compatibility mode
01 Indicates Type A DMA as described in the EISA
10 Indicates Type B DMA
11 Indicates Type F
Bits [4:3] Ignored
Bit [2] Logical device bus master status, _BM:
0 Logical device is not a bus master
1 Logical device is a bus master
Bits [1:0] DMA transfer type preference, _SIZ:
00 8-bit only
01 8- and 16-bit
10 16-bit only
11Reserved
SeeDMA (DMA Resource Descriptor Macro) for a description of the ASL macro that creates a DMA descriptor.
6.4.2.3 Start Dependent Functions Descriptor
Type 0, Small Item Name 0x6, Length = 0 or 1
Each logical device requires a set of resources. This set of resources may have interdependencies that need to be
expressed to allow arbitration software to make resource allocation decisions about the logical device. Dependent
functions are used to express these interdependencies. The data structure deﬁnitions for dependent functions are
shown here. For a detailed description of the use of dependent functions refer to the next section.
Table 6.30: Start Dependent Functions Descriptor Deﬁnition
Byte 0
Value = 0x30 or 0x31 (0011000nB)
Type = 0, small item name = 0x6
Length = 0 or 1
Start Dependent Function ﬁelds may be of length 0 or 1 bytes. The extra byte is optionally used to denote the
compatibility or performance/robustness priority for the resource group following the Start DF tag. The compatibility
priority is a ranking of conﬁgurations for compatibility with legacy operating systems. This is the same as the priority
used in the PNPBIOS interface. For example, for compatibility reasons, the preferred conﬁguration for COM1 is IRQ4,
I/O 3F8-3FF. The performance/robustness performance is a ranking of conﬁgurations for performance and robustness
reasons. For example, a device may have a high-performance, bus mastering conﬁguration that may not be supported
by legacy operating systems. The bus-mastering conﬁguration would have the highest performance/robustness priority
while its polled I/O mode might have the highest compatibility priority.
If the Priority byte is not included, this indicates the dependent function priority is ‘acceptable’. This byte is deﬁned
as:
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Table 6.31: Start Dependent Function Priority Byte Deﬁnition
Bits Deﬁnition
1:0
Compatibility priority. Acceptable values are:
0 Good conﬁguration: Highest Priority and preferred conﬁguration
1 Acceptable conﬁguration: Lower Priority but acceptable conﬁguration
2 Sub-optimal conﬁguration: Functional conﬁguration but not optimal
3 Reserved
3:2
Performance/robustness. Acceptable values are:
3 Reserved
7:4 Reserved (must be 0)
Notice that if multiple Dependent Functions have the same priority, they are further prioritized by the order in which
they appear in the resource data structure. The Dependent Function that appears earliest (nearest the beginning) in the
structure has the highest priority, and so on.
SeeStartDependentFn (Start Dependent Function Resource Descriptor Macro) for a description of the ASL macro
that creates a Start Dependent Function descriptor.
6.4.2.4 End Dependent Functions Descriptor
Type 0, Small Item Name 0x7, Length = 0
Only one End Dependent Function item is allowed per logical device. This enforces the fact that Dependent Functions
cannot be nested.
Table 6.32: End Dependent Functions Descriptor Deﬁnition
Byte 0 Value = 0x38 (00111000B) - Type = 0, Small item name = 0x7, Length =0
SeeEndDependentFn (End Dependent Function Resource Descriptor Macro) for a description of the ASL macro that
creates an End Dependent Functions descriptor.
6.4.2.5 I/O Port Descriptor
Type 0, Small Item Name 0x8, Length = 7
There are two types of descriptors for I/O ranges. The ﬁrst descriptor is a full function descriptor for programmable
devices. The second descriptor is a minimal descriptor for old ISA cards with ﬁxed I/O requirements that use a 10-bit
ISA address decode. The ﬁrst type descriptor can also be used to describe ﬁxed I/O requirements for ISA cards that
require a 16-bit address decode. This is accomplished by setting the range minimum base address and range maximum
base address to the same ﬁxed I/O value.
6.4. Resource Data Types for ACPI 390Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.33: I/O Port Descriptor Deﬁnition
Offset Field Name Deﬁnition
Byte 0 I/O Port Descriptor Value = 0x47 (01000111B) - Type = 0, Small item name =
0x8, Length = 7
Byte 1 Information Bits [7:1] Reserved and must be 0 Bit [0] (_DEC) 1 The logi-
cal device decodes 16-bit addresses 0 The logical device only
decodes address bits[9:0]
Byte 2 Range minimum base address, _MIN
bits[7:0]Address bits [7:0] of the minimum base I/O address that the
card may be conﬁgured for.
Byte 3 Range minimum base address, _MIN
bits[15:8]Address bits [15:8] of the minimum base I/O address that the
Byte 4 Range maximum base address,
_MAX bits[7:0]Address bits [7:0] of the maximum base I/O address that the
Byte 5 Range maximum base address,
_MAX bits[15:8]Address bits [15:8] of the maximum base I/O address that the
Byte 6 Base alignment, _ALN Alignment for minimum base address, increment in 1-byte
blocks.
Byte 7 Range length, _LEN The number of contiguous I/O ports requested.
SeeIO (IO Resource Descriptor Macro) for a description of the ASL macro that creates an I/O Port descriptor.
6.4.2.6 Fixed Location I/O Port Descriptor
Type 0, Small Item Name 0x9, Length = 3
This descriptor is used to describe 10-bit I/O locations.
Table 6.34: Fixed-Location I/O Port Descriptor Deﬁnition
Byte 0 Fixed Location I/O Port Descriptor Value = 0x4B (01001011B) - Type = 0, Small item name =
0x9, Length = 3
Byte 1 Range base address, _BAS bits[7:0] Address bits [7:0] of the base I/O address that the card may be
conﬁgured for. This descriptor assumes a 10-bit ISA address
decode.
Byte 2 Range base address, _BAS bits[9:8] Address bits [9:8] of the base I/O address that the card may be
decode.
Byte 3 Range length, _LEN The number of contiguous I/O ports requested.
SeeFixedIO (Fixed IO Resource Descriptor Macro) for a description of the ASL macro that creates a Fixed I/O Port
6.4. Resource Data Types for ACPI 391Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4.2.7 Fixed DMA Descriptor

decode.
decode.
Type 0, Small Item Name 0xA, Length = 5
The Fixed DMA descriptor provides a means for platforms to statically assign DMA request lines and channels to
devices connected to a shared DMA controller. This descriptor differs from the DMA descriptor in that it supports
many more DMA request lines and DMA controller channels, as well as a ﬂexible mapping between the two. The
width of the bus used for transfers to the device is also provided. This structure is repeated for each separate request
line/channel pair required, and can only be used in the _CRS object. (Dynamic arbitration of Fixed DMA resource is
not supported.)
Table 6.35: Fixed DMA Resource Descriptor
Byte 0 Value = 0x55 (01010101B) - Type = 0, Small item name = 0xA, Length = 0x5
Byte 1 DMA Request Line bits [7:0] _DMA[7:0]. A platform-relative number uniquely identifying the
request line assigned. Request line-to-Controller mapping is done in a controller-speciﬁc OS
driver.
Byte 2 DMA Request Line bits [15:8] _DMA[15:8]
Byte 3 DMA Channel bits[7:0] _TYP[7:0]. A controller-relative number uniquely identifying the con-
troller’s logical channel assigned. Channel numbers can be shared by multiple request lines.
Byte 4 DMA Channel bits[15:8] _TYP[15:8]
Byte 5 DMA Transfer Width. _SIZ. Bus width that the device connected to this request line supports.
0x00 8-bit 0x01 16-bit 0x02 32-bit 0x03 64-bit 0x04 128-bit 0x05 256-bit 0x06-0xFF Reserved
6.4.2.8 Vendor-Deﬁned Descriptor, Type 0
Type 0, Small Item Name 0xE, Length = 1 to 7
The vendor deﬁned resource data type is for vendor use.
Table 6.36: Vendor-Deﬁned Resource Descriptor Deﬁnition
Byte 0 Value = 0x71 - 0x77 (01110nnnB) - Type = 0, small item name = 0xE, Length = 1-7
Byte 1 to 7 Vendor deﬁned
SeeVendorShort (Short Vendor Resource Descriptor) for a description of the ASL macro that creates a short vendor-
deﬁned resource descriptor.
6.4.2.9 End Tag
Type 0, Small Item Name 0xF, Length = 1
The End tag identiﬁes an end of resource data.
Note: If the checksum ﬁeld is zero, the resource data is treated as if the checksum operation succeeded. Conﬁguration
proceeds normally.
6.4. Resource Data Types for ACPI 392Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.37: End Tag Deﬁnition
Byte 0 Value = 0x79 (01111001B) - Type = 0, Small item name = 0xF, Length = 1
Byte 1 Checksum covering all resource data after the serial identiﬁer. This checksum is generated such
that adding it to the sum of all the data bytes will produce a zero sum.
The End Tag is automatically generated by the ASL compiler at the end of the ResourceTemplate statement.
6.4.3 Large Resource Data Type
To allow for larger amounts of data to be included in the conﬁguration data structure the large format is shown below.
This includes a 16-bit length ﬁeld allowing up to 64 KB of data.
Table 6.38: Large Resource Data Type Tag Bit Deﬁnitions
Byte 0
Value = 1xxxxxxxB
Type = 1 (Large item)
Large item name = xxxxxxxB
Byte 1 Length of data items bits[7:0]
Byte 2 Length of data items bits[15:8]
Bytes 3 to (Length + 2) Actual data items
The following large information items are currently deﬁned:
Table 6.39: Large Resource Items
Large Item Name Value
Reserved 0x00
24-Bit Memory Range Descriptor 0x01
Generic Register Descriptor 0x02
Reserved 0x03
Vendor-Deﬁned Descriptor 0x04
32-Bit Memory Range Descriptor 0x05
32-Bit Fixed Memory Range Descriptor 0x06
Address Space Resource Descriptors 0x07
Word Address Space Descriptor 0x08
Extended Interrupt Descriptor 0x09
QWord Address Space Descriptor 0x0A
Extended Address Space Descriptor 0x0B
GPIO Connection Descriptor 0x0C
Pin Function Descriptor 0x0D
GenericSerialBus Connection Descriptors 0x0E
Pin Conﬁguration Descriptor 0x0F
Pin Group Descriptor 0x10
Pin Group Function Descriptor 0x11
Pin Group Conﬁguration Descriptor 0x12
Clock Input Resource Descriptor 0x13
Reserved 0x14-0x7F
6.4. Resource Data Types for ACPI 393Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4.3.1 24-Bit Memory Range Descriptor
Type 1, Large Item Value 0x1
The 24-bit memory range descriptor describes a device’s memory range resources within a 24-bit address space
Table 6.40: 24-bit Memory Range Descriptor Deﬁnition
Offset Field Name, ASL Field Name Deﬁnition
Byte 0 24-bit Memory Range Descriptor Value = 0x81 (10000001B) - Type = 1, Large item name =
0x01
Byte 1 Length, bits[7:0] Value = 0x09 (9)
Byte 2 Length, bits[15:8] Value = 0x00
Byte 3 Information
This ﬁeld provides extra information about this memory:
Bit [7:1] Ignored
Bit [0] Write status, _RW:
1 writeable (read/write)
0 non-writeable (read-only)
Byte 4 Range minimum base address, _MIN,
bits[7:0]Address bits [15:8] of the minimum base memory address for
which the card may be conﬁgured.
Byte 5 Range minimum base address, _MIN,
bits[15:8]Address bits [23:16] of the minimum base memory address
for which the card may be conﬁgured
Byte 6 Range maximum base address,
_MAX, bits[7:0]Address bits [15:8] of the maximum base memory address for
Byte 7 Range maximum base address,
_MAX, bits[15:8]Address bits [23:16] of the maximum base memory address
Byte 8 Base alignment, _ALN, bits[7:0] This ﬁeld contains the lower eight bits of the base alignment.
The base alignment provides the increment for the minimum
base address. (0x0000 = 64 KB)
Byte 9 Base alignment, _ALN, bits[15:8] This ﬁeld contains the upper eight bits of the base alignment.
Byte 10 Range length, _LEN, bits[7:0] This ﬁeld contains the lower eight bits of the memory range
length. The range length provides the length of the memory
range in 256 byte blocks.
Byte 11 Range length, _LEN, bits[15:8] This ﬁeld contains the upper eight bits of the memory range
length. The range length ﬁeld provides the length of the mem-
ory range in 256 byte blocks.
Note: Address bits [7:0] of memory base addresses are assumed to be 0.
Note: A Memory range descriptor can be used to describe a ﬁxed memory address by setting the range minimum
base address and the range maximum base address to the same value.
Note: 24-bit Memory Range descriptors are used for legacy devices.
6.4. Resource Data Types for ACPI 394Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Note: Mixing of 24-bit and 32-bit memory descriptors on the same device is not allowed.
SeeMemory24 (Memory Resource Descriptor Macro) for a description of the ASL macro that creates a 24-bit Memory
6.4.3.2 Vendor-Deﬁned Descriptor, Type 1
Type 1, Large Item Value 0x4
Table 6.41: Large Vendor-Deﬁned Resource Descriptor Deﬁnition
Byte 0 Vendor Deﬁned Descriptor Value = 0x84 (10000100B) - Type = 1, Large item name =
0x04
Byte 1 Length, bits [7:0] Lower eight bits of data length (UUID and vendor data)
Byte 2 Length, bits [15:8] Upper eight bits of data length (UUID and vendor data)
Byte 3 UUID speciﬁc descriptor sub
typeUUID speciﬁc descriptor sub type value
Byte 4-19 UUID UUID Value
Byte 20-
(Length+20)Vendor Deﬁned Data Vendor deﬁned data bytes
This speciﬁcation (ACPI) deﬁnes the UUID speciﬁc descriptor subtype ﬁeld and the UUID ﬁeld to address potential
collision of the use of this descriptor. It is strongly recommended that all newly deﬁned vendor descriptors use these
ﬁelds prior to Vendor Deﬁned Data.
See VendorLong for a description of the ASL macro that creates a long vendor-deﬁned resource descriptor.
6.4.3.3 32-Bit Memory Range Descriptor
Type 1, Large Item Value 0x5
This memory range descriptor describes a device’s memory resources within a 32-bit address space.
Table 6.42: 32-Bit Memory Range Descriptor Deﬁnition
Byte 0 32-bit Memory Range Descrip-
torValue = 0x85 (10000101B) - Type = 1, Large item name =
0x05
Byte 1 Length, bits [7:0] Value = 0x11 (17)
Byte 2 Length, bits [15:8] Value = 0x00
6.4. Resource Data Types for ACPI 395Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.42 – continued from previous page
Byte 4 Range minimum base address,
_MIN, bits [7:0]Address bits [7:0] of the minimum base memory address for
Byte 5 Range minimum base address,
_MIN, bits [15:8]Address bits [15:8] of the minimum base memory address for
Byte 6 Range minimum base address,
_MIN, bits [23:16]Address bits [23:16] of the minimum base memory address
for which the card may be conﬁgured.
Byte 7 Range minimum base address,
_MIN, bits [31:24]Address bits [31:24] of the minimum base memory address

Byte 8 Range maximum base address,
_MAX, bits [7:0]Address bits [7:0] of the maximum base memory address for
Byte 9 Range maximum base address,
_MAX, bits [15:8]Address bits [15:8] of the maximum base memory address for
Byte 10 Range maximum base address,
_MAX, bits [23:16]Address bits [23:16] of the maximum base memory address
Byte 11 Range maximum base address,
_MAX, bits [31:24]Address bits [31:24] of the maximum base memory address
Byte 12 Base alignment, _ALN bits
[7:0]This ﬁeld contains bits [7:0] of the base alignment. The base
alignment provides the increment for the minimum base ad-
dress.
Byte 13 Base alignment, _ALN bits
[15:8]This ﬁeld contains bits [15:8] of the base alignment. The base
dress.
Byte 14 Base alignment, _ALN bits
[23:16]This ﬁeld contains bits [23:16] of the base alignment. The
base alignment provides the increment for the minimum base
address.
Byte 15 Base alignment, _ALN bits
[31:24]This ﬁeld contains bits [31:24] of the base alignment. The
address.
Byte 16 Range length, _LEN bits [7:0] This ﬁeld contains bits [7:0] of the memory range length. The
range length provides the length of the memory range in 1-
byte blocks.
Byte 17 Range length, _LEN bits [15:8] This ﬁeld contains bits [15:8] of the memory range length.
The range length provides the length of the memory range in
1-byte blocks.
Byte 18 Range length, _LEN bits
[23:16]This ﬁeld contains Bits [23:16] of the memory range length.
Byte 19 Range length, _LEN bits
[31:24]This ﬁeld contains Bits [31:24] of the memory range length.
SeeMemory32 (Memory Resource Descriptor Macro) for a description of the ASL macro that creates a 32-bit Memory
6.4. Resource Data Types for ACPI 396Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4.3.4 32-Bit Fixed Memory Range Descriptor
Type 1, Large Item Value 0x6
Table 6.43: 32-bit Fixed-Location Memory Range Descriptor Deﬁni-
tion
Byte 0 32-bit Fixed Memory Range Descriptor Value = 0x86 (10000110B) - Type = 1, Large item name
= 0x06
Byte 1 Length, bits [7:0] Value = 0x09 (9)
Byte 3 Information This ﬁeld provides extra information about this memory.
Bit [7:1] Ignored Bit [0] Write status, _RW 1 writeable
(read/write) 0 non-writeable (read-only))
Byte 4 Range base address, _BAS bits [7:0] Address bits [7:0] of the base memory address for which
the card may be conﬁgured.
Byte 5 Range base address, _BAS bits [15:8] Address bits [15:8] of the base memory address for
Byte 6 Range base address, _BAS bits [23:16] Address bits [23:16] of the base memory address for
Byte 7 Range base address, _BAS bits [31:24] Address bits [31:24] of the base memory address for
Byte 8 Range length, _LEN bits [7:0] This ﬁeld contains bits [7:0] of the memory range
length. The range length provides the length of the
memory range in 1-byte blocks.
Byte 9 Range length, _LEN bits[15:8] This ﬁeld contains bits [15:8] of the memory range
Byte 10 Range length, _LEN bits [23:16] This ﬁeld contains bits [23:16] of the memory range
Byte 11 Range length, _LEN bits [31:24] This ﬁeld contains bits [31:24] of the memory range
SeeMemory32Fixed (Memory Resource Descriptor Macro) for a description of the ASL macro that creates a 32-bit
Fixed Memory descriptor.
6.4. Resource Data Types for ACPI 397Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4.3.5 Address Space Resource Descriptors
The QWORD, DWORD, WORD, and Extended Address Space Descriptors are general-purpose structures for de-
scribing a variety of types of resources. These resources also include support for advanced server architectures (such
as multiple root buses), and resource types found on some RISC processors. These descriptors can describe various
kinds of resources. The following table deﬁnes the valid combination of each ﬁeld and how they should be interpreted.
Table 6.44: Valid Combination of Address Space Descriptor Fields
_LEN _MIF _MAF Deﬁnition
0 0 0 Variable size, variable location resource descriptor for _PRS.
If _MIF is set, _MIN must be a multiple of (_GRA+1). If _MAF is set, _MAX
must be (a multiple of (_GRA+1))-1.
OS can pick the resource range that satisﬁes following conditions:
If _MIF is not set, start address is a multiple of (_GRA+1) and greater or equal
to _MIN. Otherwise, start address is _MIN.
If _MAF is not set, end address is (a multiple of (_GRA+1))-1 and less or equal
to _MAX. Otherwise, end address is _MAX.
0 0 1 Variable size, variable location resource descriptor for _PRS.
0 1 0 Variable size, variable location resource descriptor for _PRS.
0 1 1 (Invalid combination)
> 0 0 0 Fixed size, variable location resource descriptor for _PRS.
_LEN must be a multiple of (_GRA+1).
Start address is a multiple of (_GRA+1) and greater or equal to _MIN.
End address is (start address+_LEN-1) and less or equal to _MAX.
> 0 0 1 (Invalid combination)
> 0 1 0 (Invalid combination)
> 0 1 1 Fixed size, ﬁxed location resource descriptor.
_GRA must be 0 and _LEN must be (_MAX - _MIN +1).
6.4. Resource Data Types for ACPI 398Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4.3.5.1 QWord Address Space Descriptor
Type 1, Large Item Value 0xA
The QWORD address space descriptor is used to report resource usage in a 64-bit address space (like memory and
I/O).
Table 6.45: WORD Address Space Descriptor Deﬁnition
Byte 0 QWORD Address Space
DescriptorValue = 0x8A (10001010B) - Type = 1, Large item name = 0x0A
Byte 1 Length, bits[7:0] Variable length, minimum value = 0x2B (43)
Byte 2 Length, bits[15:8] Variable length, minimum value = 0x00
Byte 3 Resource Type Indicates which type of resource this descriptor describes. Deﬁned values
are: 0 Memory range 1 I/O range 2 Bus number range 3-191 Reserved
192-255 Hardware Vendor Deﬁned
Byte 4 General Flags
Flags that are common to all resource types:
Bits [7:4] Reserved (must be 0)
Bit [3] Max Address Fixed, _MAF:
1 The speciﬁed maximum address is ﬁxed
0 The speciﬁed maximum address is not ﬁxed and can be changed
Bit [2] Min Address Fixed,_MIF:
1 The speciﬁed minimum address is ﬁxed
0 The speciﬁed minimum address is not ﬁxed and can be changed
Bit [1] Decode Type, _DEC:
1 This bridge subtractively decodes this address (top level bridges
only)
0 This bridge positively decodes this address Bit [0] Ignored
Byte 5 Type Speciﬁc Flags Flags that are speciﬁc to each resource type. The meaning of the ﬂags in
this ﬁeld depends on the value of the Resource Type ﬁeld (see above).
Byte 6 Address space granularity,
_GRA bits[7:0]A set bit in this mask means that this bit is decoded. All bits less signiﬁ-
cant than the most signiﬁcant set bit must be set. That is, the value of the
full Address Space Granularity ﬁeld (all 64 bits) must be a number (2n-1).
Byte 7 Address space granularity,
_GRA bits[15:8]
Byte 8 Address space granularity,
_GRA bits[23:16]
Byte 9 Address space granularity,
_GRA bits[31:24]
Byte 10 Address space granularity,
_GRA bits[39:32]
Byte 11 Address space granularity,
_GRA bits[47:40]

only)
Byte 12 Address space granularity,
_GRA bits[55:48]
Byte 13 Address space granularity,
_GRA bits[63:56]
Byte 14 Address range minimum,
_MIN bits[7:0]For bridges that translate addresses, this is the address space on the sec-
ondary side of the bridge.
6.4. Resource Data Types for ACPI 399Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 15 Address range minimum,
_MIN bits[15:8]
Byte 16 Address range minimum,
_MIN bits[23:16]
Byte 17 Address range minimum,
_MIN bits[31:24]
Byte 18 Address range minimum,
_MIN bits[39:32]
Byte 19 Address range minimum,
_MIN bits[47:40]
Byte 20 Address range minimum,
_MIN bits[55:48]
Byte 21 Address range minimum,
_MIN bits[63:56]
Byte 22 Address range maximum,
_MAX bits[7:0]For bridges that translate addresses, this is the address space on the sec-
Byte 23 Address range maximum,
_MAX bits[15:8]
Byte 24 Address range maximum,
_MAX bits[23:16]
Byte 25 Address range maximum,
_MAX bits[31:24]
Byte 26 Address range maximum,
_MAX bits[39:32]For bridges that translate addresses, this is the address space on the sec-
Byte 27 Address range maximum,
_MAX bits[47:40]
Byte 28 Address range maximum,
_MAX bits[55:48]
Byte 29 Address range maximum,
_MAX bits[63:56]
Byte 30 Address Translation off-
set, _TRA bits[7:0]For bridges that translate addresses across the bridge, this is the offset
that must be added to the address on the secondary side to obtain the ad-
dress on the primary side. Non-bridge devices must list 0 for all Address
Translation offset bits.
Byte 31 Address Translation off-
set, _TRA bits[15:8]
Byte 32 Address Translation off-
set, _TRA bits[23:16]
Byte 33 Address Translation off-
set, _TRA bits[31:24]
Byte 34 Address Translation off-
set, _TRA bits[39:32]
Byte 35 Address Translation off-
set, _TRA bits[47:40]
Byte 36 Address Translation off-
set, _TRA bits[55:48]
Byte 37 Address Translation off-
set, _TRA bits[63:56]
Byte 38 Address length, _LEN
bits[7:0]
6.4. Resource Data Types for ACPI 400Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 39 Address length, _LEN,
bits[15:8]
Byte 40 Address length, _LEN
bits[23:16]
Byte 41 Address length, _LEN
bits[31:24]
Byte 42 Address length, _LEN
bits[39:32]
Byte 43 Address length, _LEN
bits[47:40]
Byte 44 Address length, _LEN
bits[55:48]
Byte 45 Address length, _LEN
bits[63:56]
Byte 46 Resource Source Index Reserved. If the platform speciﬁes “Interrupt ResourceSource support”
in bit 13 of Platform-Wide _OSC Capabilities DWORD 2 , then this ﬁeld
must be zero.
String Resource Source (Optional) If present, the device that uses this descriptor consumes its
resources from the resources produced by the named device object. If not
present, the device consumes its resources out of a global pool.
See QWordIO, QWordMemory, and ASL_QWordAddressSpace for a description of the ASL macros that creates a
QWORD Address Space descriptor.
6.4.3.5.2 DWord Address Space Descriptor
Type 1, Large Item Value 0x7
The DWORD address space descriptor is used to report resource usage in a 32-bit address space (like memory and
I/O).
Table 6.46: DWORD Address Space Descriptor Deﬁnition
Byte 0 DWORD Address Space
DescriptorValue = 0x87 (10000111B) - Type = 1, Large item name = 0x07
Byte 1 Length, bits [7:0] Variable: Value = 23 (minimum)
Byte 2 Length, bits [15:8] Variable: Value = 0 (minimum)
Byte 3 Resource Type
Indicates which type of resource this descriptor describes. Deﬁned
0 Memory range
1 I/O range
2 Bus number range
3-191 Reserved
6.4. Resource Data Types for ACPI 401Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.46 – continued from previous page
only)
0 This bridge positively decodes this address
Bit [0] Ignored
_GRA bits[7:0]A set bit in this mask means that this bit is decoded. All bits less signif-
icant than the most signiﬁcant set bit must be set. (in other words, the
value of the full Address Space Granularity ﬁeld (all 32 bits) must be a
number (2n-1).
_GRA bits [23:16]
_GRA bits [31:24]
Byte 10 Address range minimum,
_MIN bits [7:0]For bridges that translate addresses, this is the address space on the sec-
Byte 11 Address range minimum,
_MIN bits [15:8]
Byte 12 Address range minimum,
_MIN bits [23:16]
Byte 13 Address range minimum,
_MIN bits [31:24]
Byte 14 Address range maximum,
_MAX bits [7:0]For bridges that translate addresses, this is the address space on the sec-
Byte 15 Address range maximum,
_MAX bits [15:8]
Byte 16 Address range maximum,
_MAX bits [23:16]
Byte 17 Address range maximum,
_MAX bits [31:24]
Byte 18 Address Translation off-
set, _TRA bits [7:0]For bridges that translate addresses across the bridge, this is the offset
Byte 19 Address Translation off-
set, _TRA bits [15:8]
6.4. Resource Data Types for ACPI 402Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 20 Address Translation off-
set, _TRA bits [23:16]
Byte 21 Address Translation off-
set, _TRA bits [31:24]
Byte 22 Address Length, _LEN,
bits [7:0]
Byte 23 Address Length, _LEN,
bits [15:8]
Byte 24 Address Length, _LEN,
bits [23:16]
Byte 25 Address Length, _LEN,
bits [31:24]
Byte 26 Resource Source Index (Optional) Only present if Resource Source (below) is present. This ﬁeld
gives an index to the speciﬁc resource descriptor that this device consumes
from in the current resource template for the device object pointed to in
Resource Source.
present, the device consumes its resources out of a global pool. If not
present, the device consumes this resource from its hierarchical parent.
See DWordIO, DWordMemory and ASL_DWordAddressSpace for a description of the ASL macro that creates a
DWORD Address Space descriptor
6.4.3.5.3 Word Address Space Descriptor
Type 1, Large Item Value 0x8
The WORD address space descriptor is used to report resource usage in a 16-bit address space (like memory and I/O).
Note: This descriptor is exactly the same as the DWORD descriptor speciﬁed in End Dependent Functions Descrip-
tor; the only difference is that the address ﬁelds are 16 bits wide rather than 32 bits wide.
Table 6.47: WORD Address Space Descriptor Deﬁnition
Byte 0 WORD Address Space
DescriptorValue = 0x88 (10001000B) - Type = 1, Large item name = 0x08
Byte 1 Length, bits [7:0] Variable length, minimum value = 0x0D (13)
Byte 2 Length, bits [15:8] Variable length, minimum value = 0x00
1 I/O range
6.4. Resource Data Types for ACPI 403Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.47 – continued from previous page
only)

1 I/O range
only)
icant than the most signiﬁcant set bit must be set. (In other words, the
value of the full Address Space Granularity ﬁeld (all 16 bits) must be a
Byte 8 Address range minimum,
_MIN, bits [7:0]For bridges that translate addresses, this is the address space on the sec-
Byte 9 Address range minimum,
_MIN, bits [15:8]
Byte 10 Address range maximum,
_MAX, bits [7:0]For bridges that translate addresses, this is the address space on the sec-
Byte 11 Address range maximum,
_MAX, bits [15:8]
Byte 12 Address Translation off-
set, _TRA, bits [7:0]For bridges that translate addresses across the bridge, this is the offset
Byte 13 Address Translation off-
set, _TRA, bits [15:8]
Byte 14 Address Length, _LEN,
bits [7:0]
Byte 15 Address Length, _LEN,
Byte 16 Resource Source Index (Optional) Only present if Resource Source (below) is present. This ﬁeld
See WordIO, WordBusNumber, and ASL_WordAddressSpace for a description of the ASL macros that create a Word
6.4. Resource Data Types for ACPI 404Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
address descriptor.
6.4.3.5.4 Extended Address Space Descriptor
Type 1, Large Item Value 0xB
The Extended Address Space descriptor is used to report resource usage in the address space (like memory and I/O).
Table 6.48: Extended Address Space Descriptor Deﬁnition
Byte 0 Extended Address Space
DescriptorValue = 0x8B (10001011B) - Type = 1, Large item name = 0x0B
Byte 1 Length, bits[7:0] Value = 0x35 (53)
1 I/O range
only)
Bit [0] Consumer/Producer:
1-This device consumes this resource
0-This device produces and consumes this resource
this ﬁeld depends on the value of the Resource Type ﬁeld (see above). For
the Memory Resource Type, the deﬁnition is deﬁned in Resource Type
Speciﬁc Flags . For other Resource Types, refer to the existing deﬁnitions
for the Address Space Descriptors.
Byte 6 Revision ID Indicates the revision of the Extended Address Space descriptor. For
ACPI 3.0, this value is 1.
Byte 7 Reserved 0
6.4. Resource Data Types for ACPI 405Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.48 – continued from previous page
Byte 14 Address space granularity,
Byte 15 Address space granularity,
Byte 22 Address range minimum,
Byte 23 Address range minimum,
Byte 30 Address range maximum,
Byte 31 Address range maximum,
6.4. Resource Data Types for ACPI 406Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 38 Address Translation off-
Byte 39 Address Translation off-
bits[7:0]
Byte 41 Address length, _LEN,
Byte 46 Address length, _LEN
Byte 47 Address length, _LEN
Byte 48 Type Speciﬁc Attribute,
_ATT bits[7:0]Attributes that are speciﬁc to each resource type. The meaning of the
attributes in this ﬁeld depends on the value of the Resource Type ﬁeld
(see above). For the Memory Resource Type deﬁnition, see Type Speciﬁc
Attributes . For other Resource Types, this ﬁeld is reserved to 0.
Byte 49 Type Speciﬁc Attribute,
_ATT bits[15:8]
Byte 50 Type Speciﬁc Attribute,
_ATT bits[23:16]
Byte 51 Type Speciﬁc Attribute,
_ATT bits[31:24]
Byte 52 Type Speciﬁc Attribute,
_ATT bits[39:32]
Byte 53 Type Speciﬁc Attribute,
_ATT bits[47:40]
Byte 54 Type Speciﬁc Attribute,
_ATT bits[55:48]
6.4. Resource Data Types for ACPI 407Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 55 Type Speciﬁc Attribute,
_ATT bits[63:56]
SeeExtendedSpace (Extended Address Space Resource Descriptor Macro) for a description of the ASL macro that
creates an Extended Address Space descriptor.
6.4.3.5.4.1 Type Speciﬁc Attributes
The meaning of the Type Speciﬁc Attributes ﬁeld of the Extended Address Space Descriptor depends on the value of
the Resource Type ﬁeld in the descriptor. When Resource Type = 0 (memory resource), the Type Speciﬁc Attributes
ﬁeld values are deﬁned per Memory Attribute Deﬁnitions in the UEFI Speciﬁcation under section titled GetMemo-
ryMap() . This is the only well-deﬁned and OS-agnostic mechanism for describing speciﬁc resource descriptor map-
ping attributes. For the architectural meaning behind the Memory Attribute Deﬁnitions, please see the ISA-speciﬁc
binding in the Calling Conventions section of the UEFI Speciﬁcation at https://ueﬁ.org/speciﬁcations.
Note: EFI_MEMORY_WC is treated as equivalent to MEM == 3 for the purpose of describing PCI(e) RC resources
matching prefetchable BAR requirements
6.4.3.5.5 Resource Type Speciﬁc Flags
The meaning of the ﬂags in the Type Speciﬁc Flags ﬁeld of the Address Space Descriptors depends on the value of the
Resource Type ﬁeld in the descriptor. The ﬂags for each resource type are deﬁned in the following tables:

Table 6.49: Memory Resource Flag (Resource Type = 0) Deﬁnitions
Bits [7:6] Reserved (must be 0)
Bit [5]
Memory to I/O Translation, _TTP:
1 TypeTranslation: This resource, which is memory on the secondary side of the
bridge, is I/O on the primary side of the bridge.
0 TypeStatic: This resource, which is memory on the secondary side of the bridge, is
also memory on the primary side of the bridge.
Bits [4:3]
Memory attributes, _MTP. These bits are only deﬁned if this memory resource describes
system RAM (see System Address Map Interfaces ):
0 - AddressRangeMemory
1 - AddressRangeReserved
2 - AddressRangeACPI
3 - AddressRangeNVS
6.4. Resource Data Types for ACPI 408Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.49 – continued from previous page
Bits [2:1]
Memory attributes, _MEM:
0 - The memory is non-cacheable:
- To mean “uncached access” as deﬁned below.
1 - The memory is cacheable
2 - The memory is cacheable and supports write combining:
- Values 1 and 2 are deprecated. If they exist, they are interpreted as follows:
- In the context of describing PCI/PCIe MMIO apertures, be treated
equivalently to _MEM == 3.
- In other contexts, to mean an “uncached access” (potentially
equivalent to _MEM == 0)
3 - The memory is prefetchable:
- In the context of describing PCI/PCIe MMIO apertures, this is used to deﬁne
resources matching prefetchable BAR requirements. In this case, the value is
interpreted to mean an “uncached access”, as deﬁned below.
- In other contexts, to mean an “uncached access” (potentially equivalent to
_MEM == 0)
Note: For all above deﬁnitions, an “uncached access” is deﬁned to be without any speciﬁc
constraints, and made in an OS, driver, platform and architecture speciﬁc manner, where
different uncached access types exist including reordering, prefetching,
combining/grouping and early-acknowledgement.
Note: OSPM ignores this ﬁeld in the Extended address space descriptor. Instead, it uses
the Type Speciﬁc Attributes ﬁeld to determine memory attributes.
Bit [0]
Write status, _RW:
1 - This memory range is read-write
0 - This memory range is read-only
Table 6.50: I/O Resource Flag (Resource Type = 1) Deﬁnitions
Bit [5] Sparse Translation, _TRS. This bit is only meaningful if Bit [4] is set. 1 SparseTranslation:
The primary-side memory address of any speciﬁc I/O port within the secondary-side range
can be found using the following function. address = (((port & 0xFFFc) << 10) || (port &
0xFFF)) + _TRA In the address used to access the I/O port, bits[11:2] must be identical to
bits[21:12], this gives four bytes of I/O ports on each 4 KB page. 0 DenseTranslation: The
primary-side memory address of any speciﬁc I/O port within the secondary-side range can
be found using the following function. address = port + _TRA
Bit [4] I/O to Memory Translation, _TTP 1 TypeTranslation: This resource, which is I/O on the
secondary side of the bridge, is memory on the primary side of the bridge. 0 TypeStatic:
This resource, which is I/O on the secondary side of the bridge, is also I/O on the primary
side of the bridge.
Bit [3:2] Reserved (must be 0)
6.4. Resource Data Types for ACPI 409Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.50 – continued from previous page
Bit [1:0] _RNG 3 Memory window covers the entire range 2 ISARangesOnly. This ﬂag is for bridges
on systems with multiple bridges. Setting this bit means the memory window speciﬁed in
this descriptor is limited to the ISA I/O addresses that fall within the speciﬁed window. The
ISA I/O ranges are: n000-n0FF, n400-n4FF, n800-n8FF, nC00-nCFF. This bit can only be
set for bridges entirely conﬁgured throughACPI namespace. 1 NonISARangesOnly. This
ﬂag is for bridges on systems with multiple bridges. Setting this bit means the memory win-
dow speciﬁed in this descriptor is limited to the non-ISA I/O addresses that fall within the
speciﬁed window. The non-ISA I/O ranges are: n100-n3FF, n500-n7FF, n900-nBFF, nD00-
nFFF. This bit can only be set for bridges entirely conﬁgured through ACPI namespace. 0
Reserved
Table 6.51: Bus Number Range Resource Flag (Resource Type = 2)
Deﬁnitions
Bit [7:0] Reserved (must be 0)
6.4.3.6 Extended Interrupt Descriptor
Type 1, Large Item Value 0x9
The Extended Interrupt Descriptor is necessary to describe interrupt settings and possibilities for systems that support
interrupts above 15.
To specify multiple interrupt numbers, this descriptor allows vendors to list an array of possible interrupt numbers,
any one of which can be used.
Table 6.52: Extended Interrupt Descriptor Deﬁnition
Byte 0 Extended Interrupt De-
scriptorValue = 0x89 (10001001B) - Type = 1, Large item name = 0x09
Byte 1 Length, bits [7:0] Variable length, minimum value = 0x06
6.4. Resource Data Types for ACPI 410Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.52 – continued from previous page
Byte 3 Interrupt Vector Flags
Interrupt Vector Information:
Bit [7:5] Reserved (must be 0)
Bit [4] Wake Capability, _WKC:
0x0 = Not Wake Capable: This interrupt is not capable of
waking the system.
0x1 = Wake Capable: This interrupt is capable of waking the
system from a low-power idle state or a system sleep state.
Bit [3] Interrupt Sharing, _SHR:
0x0 = Exclusive: This interrupt is not shared with other
devices.
Bit [2] Interrupt Polarity, _LL:
0 Active-High: This interrupt is sampled when the signal is
high, or true.
1 Active-Low: This interrupt is sampled when the signal is
low, or false.
Bit [1] Interrupt Mode, _HE:
0 Level-Triggered: Interrupt is triggered in response to the
signal being in either a high or low state.
1 Edge-Triggered: This interrupt is triggered in response to a
change in signal state, either high to low or low to high.
1 This device consumes this resource
0 This device produces this resource
Byte 4 Interrupt table length Indicates the number of interrupt numbers that follow. When this
descriptor is returned from _CRS, or when OSPM passes this de-
scriptor to _SRS, this ﬁeld must be set to 1.
Byte 4 n+5 Interrupt Number, _INT
bits [7:0]Interrupt number
Byte 4 n+6 Interrupt Number, _INT
Byte 4 n+7 Interrupt Number, _INT
Byte 4 n+8 Interrupt Number, _INT
. . . . . . Additional interrupt numbers
Byte x Resource Source Index Reserved. If the platform speciﬁes “Interrupt ResourceSource sup-
port” in bit 13 of Platform-Wide _OSC Capabilities DWORD 2 , then
String Resource Source (Optional) If present, the device that uses this descriptor consumes
its resources from the resources produces by the named device ob-
ject. If not present, the device consumes its resources out of a global
pool.
Note: Low true, level sensitive interrupts may be electrically shared, the process of how this might work is beyond
6.4. Resource Data Types for ACPI 411Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
If the OS is running using the 8259 interrupt model, only interrupt number values of 0-15 will be used, and interrupt
numbers greater than 15 will be ignored. See the Interrupt section for a description of the ASL macro that creates an
Extended Interrupt descriptor.
6.4.3.7 Generic Register Descriptor
Type 1, Large Item Value 0x2
The generic register descriptor describes the location of a ﬁxed width register within any of the ACPI-deﬁned address
spaces. See Generic Register Descriptor for details.
Table 6.53: Generic Register Descriptor Deﬁnition
Offset Field Name, ASL Field
NameDeﬁnition
Byte 0 Generic Register Descrip-
torValue = 0x82 (10000010B) Type = 1, Large item name = 0x02
Byte 1 Length, bits[7:0] Value = 0x0C (12)
Byte 3 Address Space ID, _ASI
The address space where the data structure or register exists.
0x00 System Memory
0x01 System I/O
0x02 PCI Conﬁguration Space
0x04 SMBus
0x07 IPMI
0x08 GeneralPurposeIO
0x0A PCC
Byte 4 Register Bit Width,
_RBWIndicates the register width in bits.
Byte 5 Register Bit Offset, _RBO Indicates the offset to the start of the register in bits from the Regis-
ter Address.
Byte 6 Access Size, _ASZ
Speciﬁes access size:
0 - Undeﬁned (legacy reasons)
1 - Byte access
2 - Word access
3 - Dword access
4 - QWord access
Byte 7 Register Address, _ADR
bits[7:0]Register Address
6.4. Resource Data Types for ACPI 412Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.53 – continued from previous page
Byte 8 Register Address, _ADR

0x04 SMBus
0x07 IPMI
0x0A PCC
Byte 9 Register Address, _ADR
Byte 10 Register Address, _ADR
Byte 11 Register Address, _ADR
Byte 12 Register Address, _ADR
Byte 13 Register Address, _ADR
Byte 14 Register Address, _ADR
See Section 19.6.114 for a description of the Generic Register Resource Descriptor Macro.
6.4.3.8 Connection Descriptors
support mobile platform architectures, ACPI abstracts these connections as resources.
6.4.3.8.1 GPIO Connection Descriptor
Type 1, Large Item Name 0xC
The GPIO Connection Descriptor describes connections between GPIO controllers and peripheral devices. Two types
of GPIO connections can be described: IO connections and Interrupt connections, distinguished by the GPIO Connec-
tion Type value in the descriptor. GPIO controllers and the devices that connect to them may be located anywhere in
the namespace, but the connection must be described in the peripheral device’s resource objects (PRS, _CRS, etc.).
Table 6.54: GPIO Connection Descriptor Deﬁnition
Byte 0 GPIO Connection De-
scriptorValue = 0x8C, (10001100B) - Type = 1, Large item name = 0x0C
Byte 1 Length, bits[7:0] Variable length, minimum value = 0x16 + L (22 + length of the
Resource Source Name string)
Byte 3 Revision ID Indicates the revision for the GPIO interrupt descriptor. This value
must be 1.
Byte 4 GPIO Connection Type Indicates the type of the descriptor: 0x00 = Interrupt Connection
0x01 = IO Connection 0x02 - 0xFF Reserved
Byte 5 General Flags, bits [7:0] Flags. Bit [7:1] Reserved (must be 0) Bit [0] Consumer/Producer:
0x0 = This device produces and consumes this resource 0x1 = This
device consumes this resource
Byte 6 General Flags, bits [15:8] Bit [15:8] Reserved (must be 0).
6.4. Resource Data Types for ACPI 413Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.54 – continued from previous page
Byte 7 Interrupt and IO Flags,
bits [7:0] for Interrupt
ConnectionsBit [7:5] Reserved (must be 0)
devices.
Bit [2:1] Interrupt Polarity, _POL:
0x0 = Active-High: This interrupt is sampled when the
signal is high, or true.
0x1 = Active-Low: This interrupt is sampled when the signal
is low, or false.
0x2 = Active-Both: This interrupt is sampled on both rising
and falling edges. Interrupt mode must be set to
Edge-triggered.
0x3 - Reserved (do not use)
Bit [0] Interrupt Mode, _MOD
0x0 = Level-Triggered: Interrupt is triggered in response to
the signal being in either a high or low state.
0x1 = Edge-Triggered: This interrupt is triggered in response
to a change in signal state, either high to low or low to high.
bits [7:0] for IO Connec-
tionsBit [7:4] Reserved (must be 0)
Bit [3] IO Sharing, _SHR:
0x0 = Exclusive: This IO connection is used exclusively by
one device.
0x1 = Shared: This IO connection is shared by two or more
devices.
Bit [2] Reserved (must be 0)
Bit [1:0] IO Restriction _IOR:
0x0 = This pin or pins can be used for either Input or Output.
0x1 = This pin or pins can only be used for Input, and the pin
conﬁguration must be preserved while not in use.
0x2 = This pin or pins can only be used for Output, and the
pin conﬁguration must be preserved while not in use.
0x3 = This pin or pins can be used for either input or output,
but the conﬁguration must be preserved until explicitly
changed.
Byte 8 Interrupt and IO Flags,
bits [15:8]Bit [15:8] Reserved (must be 0)
6.4. Resource Data Types for ACPI 414Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 9 Pin Conﬁguration
_PPI:
0x00 = Default Conﬁguration (no conﬁguration is applied)
0x01 = Pull-up
0x02 = Pull-down
0x03 = No Pull
0x04 - 0x7F; Reserved (do not use)
0x80 - 0xFF; Vendor-deﬁned values
Byte 10 Output Drive Strength,
bits [7:0]The output-drive capability, in hundredths of milliamperes, to be
applied when conﬁguring the pin for output (high byte). _DRS[7:0]
Byte 11 Output Drive Strength,
bits [15:8]The output-drive capability, in hundredths of milliamperes, to be ap-
plied when conﬁguring the pin for output (high byte). _DRS[15:8]
Byte 12 Debounce timeout, bits
[7:0]The debounce timeout, in hundredths of milliseconds, to be applied
when conﬁguring the pin for interrupt (low byte). _DBT[7:0]
Byte 13 Debounce timeout, bits
[15:8]The debounce timeout, in hundredths of milliseconds, to be applied
when conﬁguring the pin for interrupt (high byte). _DBT [15:8]
Byte 14 Pin Table Offset[7:0] Offset to the start of the pin table (low byte). The offset is relative
to the start of this descriptor. NOTE: The number of pins in the
table can be calculated from PinCount = (Resource Source Name
Offset - Pin Table Offset) / 2
Byte 15 Pin Table Offset[15:8] Offset to the start of the pin table (high byte). The offset is relative
to the start of this descriptor.
Byte 16 Resource Source Index Reserved for future use. This ﬁeld must be 0.
Byte 17 Resource Source Name
Offset[7:0]Offset to the start of the resource source name (low byte). The off-
set is relative to the start of this descriptor. NOTE: The length of
the ResourceSource name string can be calculated from Length L
= Vendor Data Offset - Resource Source Name Offset. The length
includes the string’s terminating NULL character (if present)
Byte 18 Resource Source Name
Offset[15:8]Offset to the start of the resource source name (high byte). The
offset is relative to the start of this descriptor.
Byte 19 Vendor Data Offset[7:0] (low byte) Offset to the start of the Vendor-deﬁned Data (the last
byte of the ResourceSource + 1). This value must always be valid
to allow for length calculations. In the case where there is no Ven-
dor Data, this offset still must refer to the last byte of the Resource-
Source + 1. The offset is relative to the start of this descriptor.
Byte 20 Vendor Data Offset[15:8] (high byte) Offset to the start of the Vendor-deﬁned Data .(the last
byte of the ResourceSource + 1). This value must always be valid to
allow for length calculations. In the case where there is no Vendor
Data, this offset still must refer to the last byte of the Resource-
Byte 21 Vendor Data Length [7:0] Length of Vendor-deﬁned Data (low-byte).
Byte 22 Vendor Data Length
[15:8]Length of Vendor-deﬁned Data (high-byte).
Byte
PinTable-
Offset[15:0]
+ 2n (n is the
index into the
pin table)Pin Number, bits [7:0]
GPIO controller-relative pin number (low byte):
_PIN[7:0]. Pin numbers are zero-based.
Pin number 0xFFFF = No Pin. OSPM will ignore this pin
number.
6.4. Resource Data Types for ACPI 415Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte
PinTable-
+ 2n + 1 (n is
the index into
the pin table)Pin Number, bits [15:8]
GPIO controller-relative pin number (high byte):
_PIN[15:8]. Pin numbers are zero-based.
number.
Byte Re-
sourceSource-
NameOff
set[15:0]Resource Source (length =
L)Name of the GPIO controller device to which this descriptor applies.
The name can be a fully-qualiﬁed name, a relative name or a name
segment that utilizes the namespace search rules.
Byte Ven-
dorDataOff-
set[15:0 ]Vendor-deﬁned Data (Optional) Data speciﬁc to the GPIO controller device supplied by
a vendor. This data is provided to the device driver for this GPIO
Controller. _VEN.
6.4.3.8.2 GenericSerialBus Connection Descriptors
Type 1, Large Item Value 0x0E
All Serial Bus Resource descriptors utilize the following format. For speciﬁc bus types, the type-speciﬁc ﬁelds are
used.
Table 6.55: GenericSerialBus Connection Descriptors
Byte 0 Serial Bus Type Value = 0x8E (10001110B) - Type = 1, Large item name = 0x0E
Byte 1 Length, bits[7:0] Variable length, minimum value = 0x09 + L(9 + ResourceSource string length)”

number.
Byte Re-
NameOff
Byte Ven-
used.
Byte 3 Revision ID Indicates the revision of the Serial Bus Connection Descriptor. This value is 2.
Byte 4 Resource Source In-
dexResource Connection Instance. If the device speciﬁed in the Resource Source
ﬁeld in this structure supports more than one connection (e.g. port), this ﬁeld
describes the instance of the connection to which this Device is connected.
Byte 5 Serial Bus Type
Indicates which type of serial bus connection this descriptor describes. Deﬁned
0 - Reserved
1 - I2C
2 - SPI
3 - UART
4 - CSI-2
5-191 - Reserved
192-255 - Hardware Vendor Deﬁned
6.4. Resource Data Types for ACPI 416Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.55 – continued from previous page
Byte 6 General Flags [7:0]
Flags that are common to all serial bus connection types:
Bits[7:3] Reserved. Must be 0.
Bit[2] Connection Sharing, _SHR:
0x0: Exclusive: This Serial Bus connection is used exclusively by one
device. If Serial Bus Type is CSI, UART, or SPI then Bit 2 must be 0.
Bit[1] Consumer/Producer:
0x1: This device consumes this resource
0x0: This device produces and consumes this resource
Bit[0] Slave Mode:
0x1: The communication over this connection is initiated by the device.
0x0: The communication over this connection is initiated by the
Byte 7 Type Speciﬁc Flags,
Bits[7:0]Flags speciﬁc to the indicated Serial Bus Type (see above).
Byte 8 Type Speciﬁc Flags,
bits[15:8]Flags speciﬁc to the indicated Serial Bus Type (see above).
Byte 9 Type Speciﬁc Revi-
sion IDRevision ID for the data describing the serial bus connection speciﬁed by Serial
Bus Type (see above).
Byte 10 Type Data Length,
bits[7:0]Variable length, minimum size depends on the indicated Serial Bus Type (see
above).
Byte 11 Type Data Length,
bits [15:8]Variable length, minimum size depends on the indicated Serial Bus Type (see
above).
Byte 12 Type Speciﬁc Data (Optional) Data speciﬁc to the serial bus connection type indicated in Serial Bus
Type (see above).
. . . . . . Additional data speciﬁc to the serial bus connection type.
String Resource Source Name of the serial bus controller device to which this connection descriptor
applies. The name can be a fully qualiﬁed path, a relative path, or a simple
name segment that utilizes the namespace search rules.
6.4.3.8.2.1 I2C Serial Bus Connection Resource Descriptor
Table 6.56: I2C Serial Bus Connection Descriptor
Byte 0 I2C Bus Connection
DescriptorValue = 0x8E (10001110B) - Type = 1, Large item name = 0x0E
Byte 1 Length, bits [7:0] Variable length, minimum value = 0xF + L (15 + ResourceSource string length)
Byte 2 Length, bits [15:8] Variable, length minimum value = 0x00
Byte 3 Revision ID Indicates the revision for the I2C Resource Descriptor. This value is 2.
dexMaster Instance. If the controller device speciﬁed in the Resource Source ﬁeld
in this structure supports more than one Master, this ﬁeld describes the instance
of the Master to which the I2C Slave is connected. The ﬁrst Master Instance is
0.
Byte 5 Serial Bus Type Serial Bus Type value must be 1 for I2C
6.4. Resource Data Types for ACPI 417Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.56 – continued from previous page
Bits [7:3] Reserved. Must be 0.
Bit [2] Connection Sharing, _SHR:
0x1: Shared: This Serial Bus connection is shared by two or more
devices.
0x0: Exclusive: This Serial Bus connection is used exclusively by
Bit [1] Consumer/Producer:
0x1: This device consumes this resource.
0x0: This device produces and consumes this resource.
Bit [0] Slave Mode, _SLV:
control
Bits[7:0]: Bits[7:1] Reserved. Must be 0.
Bit[0] 10-bit addressing mode, _MOD:
0x1: The connection uses 10-bit addressing
0x0: The connection uses 7-bit addressing.
Note: If this device is connected to an I3C Host Controller, _MOD must be 0.
bits[15:8]Legacy Virtual Register, _LVR This ﬁeld is used to provide LVR data as speci-
ﬁed in the MIPI I3C Speciﬁcation for an I2C device connected to an I3C Host
Controller. For I2C devices on an I2C bus, this ﬁeld is Reserved and unused.
sion IDIndicates the revision of the I2C-speciﬁc Serial Bus Connection Descriptor
Data. This value is 1.
bits[7:0]Variable length, minimum value = 0x6 (6).
bits [15:8]Variable length, minimum size = 0x0 (0)
Byte 12 Connection Speed,
bits [7:0]Connection speed bits [7:0] of the maximum speed in hertz supported by this
connection. _SPE[7:0]
Byte 13 Connection Speed,
bits [15:8]Connection speed bits [15:8] of the maximum speed in hertz supported by this
connection. _SPE[15:8]
Byte 14 Connection Speed,
bits [23:16]Connection speed bits [23:16] of the maximum speed in hertz supported by this
connection. _SPE[23:16]
Byte 15 Connection Speed,
bits [31:24]Connection speed bits [31:24] of the maximum speed in hertz supported by this
connection. _SPE[31:24]
Byte 16 Slave Address, bits
[7:0] Lower eight bits of the I2C bus address for this connection, _ADR[7:0]:
Bits[6:0] The lowest 7 bits of the address. In 7-bit addressing mode this
represents the complete address.
6.4. Resource Data Types for ACPI 418Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 17 Slave Address,
bits[15:8] Upper eight bits of the I2C bus address for this connection. The upper eight
bits are to support 10-bit addressing and should be set to 0 if 7-bit addressing is
being used. _ADR[15:8]:
Bits [15:10] Reserved. Must be 0.
Bits [9:8] In 7-bit addressing mode these are reserved and must be 0. In 10-bit
addressing mode these are the highest two bits of the address.
Byte 18 Vendor-deﬁned
Data(Optional) Data speciﬁc to the controller device supplied by a vendor. The
number of bytes in this ﬁeld is Type Data Length - 6.
. . . . . . (Optional) Additional vendor supplied data.
String Resource Source
(Length = L)Name of the serial bus controller device to which this connection descriptor
name segment that utilizes the namespace search rules
6.4.3.8.2.2 SPI Serial Bus Connection Resource Descriptor
Table 6.57: SPI Serial Bus Connection Descriptor
Byte 0 SPI Bus Connection
Byte 1 Length, bits[7:0] Variable length, minimum value = 0x12 + L (18 + Resource Source string
length)
Byte 3 Revision ID Indicates the revision of the Serial Bus Connection Descriptor. This value is 1.
dexReserved (must be 0)
Byte 5 Serial Bus Type Serial Bus Type value must be 2 for SPI
Byte 6 General Flags[7:0]
Flags that are common to all serial bus connection types.
Bits[7:2] Reserved. Must be 0.
Bit[0] Slave Mode, _SLV:
6.4. Resource Data Types for ACPI 419Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.57 – continued from previous page
bits[7:0] Bits [7:2] Reserved (must be 0)
Bit[1]: Device Polarity, _DPL
1 - The device selection line is active high
0 - The device selection line is active low
Bit[0]: Wire Mode. _MOD
1 - The connection is over 3 wires
0 - The connection is over 4 wires
bits[15:8]Reserved. Must be 0.
sion IDIndicates the revision of the SPI-speciﬁc Serial Bus Connection Descriptor
Data. This value must be 1.
bits[7:0]Variable length, minimum value = 0x9 (9).
Byte 16 Data Bit Length The size in bits of the smallest transfer unit. _LEN
Byte 17 Phase

The phase (CPHA) of the clock pulse on which to capture data (the other being
used to transmit), _PHA:
0 - First phase
1 - Second phase
Byte 18 Polarity
The polarity of the clock (CPOL). This value indicates if the clock is low or
high during the ﬁrst phase (see Phase above). _POL
0-Start Low
1 -Start High
Byte 19 Device Selection,
bits [7:0]Lower eight bits of the device selection value. This value is speciﬁc to the
device and may refer to a chip-select line, GPIO line or other line selection
mechanism. _ADR[7:0]
Byte 20 Device Selection,
bits [15:8]Upper eight bits of the device selection value. This value is speciﬁc to the device
and may refer to a chip-select line, GPIO line or other line selection mechanism.
_ADR[15:8]
Byte 21 Vendor Deﬁned
number of bytes in this ﬁeld is Type Data Length - 9.
6.4. Resource Data Types for ACPI 420Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4.3.8.2.3 UART Serial Bus Connection Resource Descriptor
Table 6.58: UART Serial Bus Connection Descriptor
Byte 0 Serial Bus Connection
Byte 1 Length, bits[7:0] Variable length, minimum value = 0x13 + L (17 + Resource Source
string length)
Byte 3 Revision ID Indicates the revision of the Serial Bus Connection Descriptor. This
value is 1.
Byte 4 Resource Source Index Reserved (must be 0)
Byte 5 Serial Bus Type Serial Bus Type value must be 3 for UART
Bits[17:2] Reserved. Must be 0.
Bit[0] Slave Mode. _SLV 0x0: The communication over this
connection is initiated by the controller:
0x1: The communication over this connection is initiated by
bits[7:0] Bit [7] - Endian-ness. _END
Little Endian = 0
Big Endian = 1
Bit [6:4] - Data bits. Number of bits per byte. _LEN
000B - 5 bits
001B - 6 bits
010B - 7 bits
011B - 8 bits
100B - 9 bits
Bits [3:2] - Stop Bits. Number of stop bits per character. _STB
00B (0) - none
01B (1) - 1
10B (2) - 1.5
11B (3) - 2 Bits [1:0] - Flow control. Indicates type of ﬂow
control for the connection. _FLC
00B (0) - None
01B (1) - Hardware ﬂow control
10B (2) - XON/XOFF
Byte 9 Type Speciﬁc Revision ID Indicates the revision of the UART-speciﬁc Serial Bus Connection
Descriptor Data. This value must be 1.
6.4. Resource Data Types for ACPI 421Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.58 – continued from previous page
bits[7:0]Variable length, minimum value = 0x0A (10).
Byte 11 Type Data Length, bits
[15:8]Variable length, minimum size = 0x0 (0)
Byte 12 Default Baud rate,
bits[7:0]Default baud rate of connection, in bits-per-second. _SPE[7:0] Bits
[7:0]
Byte 13 Default Baud rate,
bits[15:8]Default baud rate of connection, in bits-per-second. _SPE[15:8]
Bits [15:8]
Byte 14 Default Baud rate,
bits[23:16]Default baud rate of connection, in bits-per-second. _SPE[23:16]
Bits [23:16]
Byte 15 Default Baud rate,
bits[31:24]Default baud rate of connection, in bits-per-second. _SPE[31:24]
Bits [31:24].
Byte 16 Rx FIFO, bits[7:0] Maximum receive buffer, in bytes, supported by this connection.
_RXL[7:0] Bits [7:0]
Byte 17 Rx FIFO, bits[15:8] Maximum receive buffer, in bytes, supported by this connection.
_RXL[15:8] Bits [15:8]
Byte 18 Tx FIFO, bits[7:0] Maximum receive buffer, in bytes, supported by this connection.
_TXL[7;0] Bits [7:0]
Byte 19 Tx FIFO, bits[15:8] Maximum receive buffer, in bytes, supported by this connection.
_TXL[15:8] Bits [15:8]
Byte 20 Parity Parity. _PAR None = 0x00 Even = 0x01 Odd = 0x02 Mark = 0x03
Space = 0x04
Byte 21 Serial Lines Enabled
Serial lines enabled (Enabled = 1, Disabled = 0), _LIN:
Bit [7] - Request to Send (RTS)
Bit [6] - Clear to Send (CTS)
Bit [5] - Data Terminal Ready (DTR)
Bit [4] - Data Set Ready (DSR)
Bit [3] - Ring Indicator (RI)
Bit [2] - Data Carrier Detect (DTD)
Bit [1] - Reserved. Must be 0.
Bit [0] - Reserved. Must be 0.
Byte 22 Vendor Deﬁned Data (Optional) Data speciﬁc to the controller device supplied by a ven-
dor. The number of bytes in this ﬁeld is Type Data Length - 10.
String Resource Source (Length
= L)Name of the serial bus controller device to which this connection
descriptor applies. The name can be a fully qualiﬁed path, a relative
path, or a simple name segment that utilizes the namespace search
rules.
6.4. Resource Data Types for ACPI 422Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4.3.8.2.4 Camera Serial Interface (CSI-2) Connection Resource Descriptor
Table 6.59: CSI-2 Connection Resource Descriptor
Byte 0 CSI-2 Connection Descriptor Value = 0x8E (10001110B) – Type = 1, Large item
name = 0x0E
Byte 1 Length, bits [7:0] Variable length, minimum value = 0xF + L (15 + Re-
sourceSource string length)
Byte 3 Revision ID Indicates the revision for the CSI Resource Descriptor.
This value is 1.
Byte 4 Resource Source Index Remote Port Instance. If the controller device speciﬁed
in the Resource Source ﬁeld in this structure supports
more than one Port, this ﬁeld describes the instance of
the Port to which the CSI sensor is connected. The ﬁrst
Port instance is 0.
Byte 5 Serial Bus Type Serial Bus Type value must be 4 for CSI-2
Flags that are common to all serial bus connection
types:
Bits [7:2] Reserved. Must be 0.
0x0: This device produces and consumes this
resource
Bit [0] Slave Mode. _SLV
0x0: The communication over this connection is
initiated by the controller.
0x1: The communication over this connection is
initiated by the device.
Byte 7 Type Speciﬁc Flags, bits[7:0]
Bits [7:2] Local Port Instance _PRT. If this device
supports more than one local CSI-2 Port,
this value reﬂects the index of the local Port for this
connection. The ﬁrst Port instance is 0.
Bits [1:0] PHY Type _PHY:
00b - C-PHY
01b - D-PHY
Other values Reserved
Byte 8 Type Speciﬁc Flags, bits[15:8] Reserved . Must be 0.
Byte 9 Type Speciﬁc Revision ID Indicates the revision of the CSI-speciﬁc Serial Bus
Connection Descriptor Data. This value is 1.
Byte 10 Type Data Length, bits[7:0] Variable length, minimum size = 0.
Byte 11 Type Data Length, bits [15:8] Variable length, minimum size = 0.
Byte 12 Vendor-deﬁned Data (Optional) Data speciﬁc to the controller device sup-
plied by a vendor. The number of bytes in this ﬁeld
is Type Data Length. _VEN
6.4. Resource Data Types for ACPI 423Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 12 + Type
Data Length
(String)Resource Source (Length = L) Name of the CSI-2 controller device to which this con-
nection descriptor applies. The name can be a fully
qualiﬁed path, a relative path, or a simple name segment
that utilizes the namespace search rules.
6.4.3.9 Pin Function Descriptor
Table 6.60: Pin Function Description Deﬁnition
Byte Offset Field Name Description
Byte 0 Resource Identiﬁer Value = 0x8D, (10001101B) - Type = 1,
Large item name = 0x0D
Byte 1 Length, bits[7:0] Variable length, minimum value = 0x0F + L
(15 + length of the Resource Source Name
string)
Byte 3 Revision ID Indicates the revision for the Pin Function
Descriptor. This value is 1
Byte 4 Flags [7:0]
Bit [7:1] - Reserved. Must be 0.
Bit [0] - IO Sharing, _SHR
0x0 = Exclusive: This function is
used exclusively by one device.
0x1 = Shared: This function is shared
by two or more devices.
Byte 5 Flags [15:8] Reserved. Must be 0.
Byte 6 Pin pull conﬁguration Can be one of PullDefault, PullUp, Pull-
Down, PullNone or a vendor-supplied value
in the range 128-255.
Byte 7 Function number (low byte) The function number in which the pin
is conﬁgured. This number is provider-
speciﬁc.
Byte 8 Function number (high byte) The function number in which the pin
speciﬁc.
Byte 9 Pin table offset (low byte) Offset to the start of the pin table (low byte).

string)
speciﬁc.
speciﬁc.
The offset is relative to the start of this de-
scriptor.
Byte 10 Pin table offset (high byte) Offset to the start of the pin table (high
byte). The offset is relative to the start of
this descriptor.
Byte 11 Resource source index Reserved for future use. This ﬁeld must be
0.
Byte 12 Resource source name index
(low byte)Offset to the start of the resource source
name (low byte). The offset is relative to
the start of this descriptor.
6.4. Resource Data Types for ACPI 424Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.60 – continued from previous page
Byte 13 Resource source name index
(high byte)Offset to the start of the resource source
name (high byte). The offset is relative to
Byte 14 Vendor data offset (low byte) (low byte) Offset to the start of the Vendor-
deﬁned Data (the last byte of the Resource-
Source + 1). This value must always be
valid to allow for length calculations. In the
case where there is no Vendor Data, this off-
set still must refer to the last byte of the Re-
sourceSource + 1. The offset is relative to
Byte 15 Vendor data offset (high byte) (high byte) Offset to the start of the Vendor-
Byte 16 Vendor data length (low byte) Length of Vendor-deﬁned Data (low-byte).
Byte 17 Vendor data length (high byte) Length of Vendor-deﬁned Data (high-byte).
Byte PinTableOffset[15:0] + 2n
(n is the index into the pin ta-
ble)Byte PinTableOffset[15:0] +
2n + 1 (n is the index into the pin
table)Pin Number, bits [15:8] Provider-relative pin number (high byte).
+ 1 (n is the index into
the pin table) Byte Resource-
SourceNameOff set[15:0]Resource Source (length = L) Name of the function conﬁg provider to
which this descriptor applies. The name can
be a fully-qualiﬁed name, a relative name or
a name segment that utilizes the namespace
search
Byte VendorDataOffset[15:0 ] Vendor-deﬁned Data (Optional) Data speciﬁc to the GPIO con-
troller device supplied by a vendor. This
data is provided to the device driver for this
GPIO Controller. _VEN.
6.4.3.10 Pin Conﬁguration Descriptor
Table 6.61: Pin Conﬁguration Descriptor Deﬁnition
Byte 0 Resource Identiﬁer Value = 0x8F, (10001110B) - Type = 1,
Large item name = 0x0F
Byte 1 Length, bits[7:0] Variable length, minimum value = 0x13 + L
(19 + length of the Resource Source Name
string)
Byte 3 Revision ID Indicates the revision for the Function Con-
ﬁguration Descriptor. This value is 1
6.4. Resource Data Types for ACPI 425Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.61 – continued from previous page
Bit [7:2] - Reserved. Must be 0.
Bit [1] - Consumer/Producer
0x1: This device consumes this
resource
0x0: This device produces and
consumes this resource
Byte6 Pin Conﬁguration Type, _TYP The pin conﬁguration type (see Pin Conﬁg-
uration Types and Values).
Byte 7 Pin Conﬁguration Value, _V AL,
bits [7:0]The pin conﬁguration value associated with
the pin conﬁguration type (see Pin Conﬁgu-
ration Types and Values).
Byte 8 Pin Conﬁguration Value, _V AL,
bits [15:8]The pin conﬁguration value associated with
Byte 9 Pin Conﬁguration Value, _V AL,
bits [23:16]The pin conﬁguration value associated with
Byte 10 Pin Conﬁguration Value, _V AL,
bits [31:24]The pin conﬁguration value associated with
Byte 11 Pin Table Offset[7:0] Offset to the start of the pin table (low byte).
scriptor.
Byte 12 Pin Table Offset[15:8] Offset to the start of the pin table (high
Byte 13 Resource Source Index Reserved for future use. This ﬁeld must be
0.
Byte 14 Resource Source Name Off-
set[7:0]Offset to the start of the resource source
Byte 15 Resource Source Name Off-
set[15:8]Offset to the start of the resource source
Byte 16 Vendor Data Offset[7:0] (low byte) Offset to the start of the Vendor-
6.4. Resource Data Types for ACPI 426Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte 17 Vendor Data Offset[15:8] (high byte) Offset to the start of the Vendor-
Byte 18 Vendor Data Length [7:0] Length of Vendor-deﬁned Data (low-byte).
Byte 19 Vendor Data Length [15:8] Length of Vendor-deﬁned Data (high-byte).
(n is the index into the pin table)Pin Number, _PIN, bits [7:0] Provider-relative pin number (low byte). Pin
numbers are zero-based.
+ 1 (n is the index into the pin
table)Pin Number, _PIN, bits [15:8] Provider-relative pin number (high byte).
Pin numbers are zero-based.
Byte ResourceSourceNameOff
set[15:0]Resource Source (length = L) Name of the pin controller to which this de-
scriptor applies. The name can be a fully-
qualiﬁed name, a relative name or a name
segment that utilizes the namespace search
Byte VendorDataOffset[15:0 ] Vendor-deﬁned Data, _VEN (Optional) Data speciﬁc to the pin controller
device supplied by a vendor. This data is
provided to the device driver for this pin
6.4.3.11 Pin Group Descriptor
Table 6.62: Pin Group Descriptor Deﬁnition
Byte 0 Resource Identiﬁer Value = 0x90, (10010000B) - Type = 1,
Large item name = 0x10
Byte 1 Length [7:0] Variable length, minimum value = 0x0B + L
(11 + length of the Resource Label)
Byte 2 Length [15:8] Value = 0x00
Byte 3 Revision ID Indicates the revision for the Pin Group De-
scriptor. This value is 1.
Bits [7:1] Reserved. Must be 0.
Bit [0] - Consumer/Producer:
resource
Byte 6 Pin table offset [7:0] Offset to the start of the pin table (low byte).
scriptor.
6.4. Resource Data Types for ACPI 427Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.62 – continued from previous page
Byte 7 Pin table offset [15:8] Offset to the start of the pin table (high
Byte 8 Resource label offset [7:0] Offset to the start of the resource label (low
this descriptor. The length of the resource
label string can be calculated from length L
= Vendor data offset - Resource label offset.
The length includes the string’s terminating
‘0’ character.
Byte 9 Resource label offset [15:8] Offset to the start of the resource label (high
Byte 10 Vendor data offset [7:0] (low byte) Offset to the start of the Vendor-
deﬁned Data (the last byte of the Resource
label offset (high byte) + 1). This value must
always be valid to allow for length calcula-
tions. In the case where there is no Vendor
Data, this offset still must refer to the last
byte of the Resource label offset (high byte)
+ 1. The offset is relative to the start of this
Byte11 Vendor data offset [15:8] (high byte) Offset to the start of the Vendor-
deﬁned Data (the last byte of the Pin table
offset (high byte) + 1). This value must al-
ways be valid to allow for length calcula-

byte of the Pin table offset (high byte) + 1.
scriptor.
Byte 12 Vendor data length [7:0] Length of Vendor-deﬁned Data (low-byte).
Byte 13 Vendor data length [15:8] Length of Vendor-deﬁned Data (high-byte).
(n is the index into the pin table)Pin Number, _PIN [7:0] Provider-relative pin number (low byte). Pin
table)Pin Number, _PIN [15:8] Provider-relative pin number (high byte).
Byte ResourceLabelOffset[1
5:0]Resource Label (length = L) Label for the resource (string). Can be any
non-empty string and is used by resource
consumers to refer to this resource by name.
Always terminated by ‘0’.
Byte VendorDataOffset[15:0 ] Vendor-deﬁned Data, _VEN (Optional) Data speciﬁc to the GPIO con-
GPIO Controller.
6.4. Resource Data Types for ACPI 428Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.4.3.12 Pin Group Function Descriptor
Table 6.63: Pin Group Function Descriptor Deﬁnition
Byte 0 Resource Identiﬁer Value = 0x91, (10010001B) - Type = 1,
Large item name = 0x11
Byte 1 Length [7:0] Variable length, minimum value = 0x0E
+ L1 + L2 (14 + length of the Resource
Source Name string + length of the Re-
source Source Label string)
Byte 2 Length [15:8] Variable length, minimum value = 0x00
Bits [7:2] - Reserved. Must be 0.
resource
used exclusively by one device
Byte 6 Function number, _FUN [7:0] The function number in which the pin
speciﬁc.
Byte 7 Function number, _FUN [15:8] The function number in which the pin
speciﬁc.
Byte 8 Resource source index Reserved for future use. This ﬁeld must be
0.
Byte 9 Resource source name index
[7:0]Offset to the start of the resource source
Byte 10 Resource source name index
[15:8]Offset to the start of the resource source
Byte 11 Resource source label offset
[7:0]Offset to the start of the Resource source la-
bel (low byte). The offset is relative to the
start of this descriptor. The length of the re-
source source label string can be calculated
from length L2 = Vendor data offset - Re-
source source label offset. The length in-
cludes the string’s terminating ‘0’ character.
6.4. Resource Data Types for ACPI 429Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.63 – continued from previous page
Byte 12 Resource source label offset
[15:8]Offset to the start of the resource source la-
bel (high byte). The offset is relative to the
start of this descriptor.
Byte 13 Vendor data offset [7:0] (low byte) Offset to the start of the Vendor-
Byte 14 Vendor data offset [15:8] (high byte) Offset to the start of the Vendor-
Byte 15 Vendor data length [7:0] Length of Vendor-deﬁned Data (low-byte).
Byte 16 Vendor data length [15:8] Length of Vendor-deﬁned Data (high-byte).
set[15:0]Resource Source (length = L1) Name of the function conﬁg provider to
search
Byte ResourceSourceLabelOf
fset[15:0]Resource Source Label (length
= L2)This name refers to the PinGroup resource
in the current resource template buffer of
the GPIO controller. The PinGroup resource
is matched by comparing its ResourceLabel
string to this ﬁeld. Always terminated by
‘0’.
6.4.3.13 Pin Group Conﬁguration Descriptor
Table 6.64: Pin Group Conﬁguration Descriptor Description
Byte 0 Resource Identiﬁer Value = 0x92, (10010010B) - Type = 1, Large item name = 0x12
Byte 1 Length, bits[7:0] Variable length, minimum value = 0x11 + L1 + L2 (17 + length
of the Resource Source Name string + length of the Resource
Source Label string)
Byte 3 Revision ID Indicates the revision for the Function Conﬁguration Descriptor.
This value is 1
6.4. Resource Data Types for ACPI 430Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.64 – continued from previous page
0x0 = Exclusive: This function is used exclusively by one
device.
0x1 = Shared: This function is shared by two or more
devices.
Byte6 Pin Conﬁguration Type,
_TYPThe pin conﬁguration type (see Pin Group Conﬁguration Types
and Values ).
Byte 7 Pin Conﬁguration Value,
_V AL, bits [7:0]The pin conﬁguration value associated with the pin conﬁguration
type (see Pin-Group-Conﬁguration-Types-and-Values ).
Byte 8 Pin Conﬁguration Value,
_V AL, bits [15:8]The pin conﬁguration value associated with the pin conﬁguration
Byte 9 Pin Conﬁguration Value,
_V AL, bits [23:16]The pin conﬁguration value associated with the pin conﬁguration
Byte 10 Pin Conﬁguration Value,
_V AL, bits [31:24]The pin conﬁguration value associated with the pin conﬁguration
Byte 11 Resource Source Index Reserved for future use. This ﬁeld must be 0.
Byte 12 Resource Source Name
Offset[7:0]Offset to the start of the resource source name (low byte). The
Byte 13 Resource Source Name
Byte 14 Resource source label
offset (low byte)Offset to the start of the resource source label (low byte). The
offset is relative to the start of this descriptor. The length of the
resource source label string can be calculated from length L2 =
Vendor data offset - Resource source label offset. The length
includes the string’s terminating ‘0’ character.
Byte 15 Resource source label
offset (high byte)Offset to the start of the resource source label (high byte). The
Byte 16 Vendor Data Offset[7:0] (low byte) Offset to the start of the Vendor-deﬁned Data (the last
byte of the ResourceSource + 1). This value must always be
valid to allow for length calculations. In the case where there
is no Vendor Data, this offset still must refer to the last byte of
the ResourceSource + 1. The offset is relative to the start of this
Byte 17 Vendor Data Off-
set[15:8](high byte) Offset to the start of the Vendor-deﬁned Data (the
last byte of the ResourceSource + 1). This value must always
be valid to allow for length calculations. In the case where there
Byte 18 Vendor Data Length
[7:0]Length of Vendor-deﬁned Data (low-byte).
Byte 19 Vendor Data Length
6.4. Resource Data Types for ACPI 431Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Byte Resource-
SourceNameOff
set[15:0]Resource Source (length
= L1)Name of the pin controller to which this descriptor applies. The

name can be a fully-qualiﬁed name, a relative name or a name
SourceLabelOf
fset[15:0]Resource Source Label
(length = L2)This name refers to the PinGroup resource in current resource
template buffer of the GPIO controller. The PinGroup resource
is matched by comparing its ResourceLabel string to this ﬁeld.
Byte Vendor-
DataOffset[15:0
]Vendor-deﬁned Data,
_VEN(Optional) Data speciﬁc to the pin controller device supplied by
a vendor. This data is provided to the device driver for this pin
6.4.3.14 Clock Input Resource Descriptor
A Clock Input Resource Descriptor is used to describe the frequency and source device of a clock input supplied by
the platform to this Device. For a clock signal with a ﬁxed frequency, a Clock Source entry is not required. If a Clock
Source is provided, control of the clock is managed by that Clock Source Device. The frequency of the input clock is
determined by Numerator and Divisor values along with a Scale value used for units. For example, a PCI clock could
be described by a numerator of 100, a divisor of 3, and a Scale of MHz.
Table 6.65: Clock Resource Descriptor Deﬁnition
Byte
OffsetField Name Description
Byte 0 Resource Identiﬁer Value = 0x93, (10010011B) - Type = 1, Large item name =
0x13
Byte 1 Length [7:0] Variable length, minimum value = 0x0C + L (12 + length of
the Resource Source)
Byte 3 Revision ID Indicates the revision for the Clock Resource Descriptor. This
value is 1.
Bits [7:4] Reserved. Must be 0.
Bits [3:1] Scale of value described in Clock Frequency
00b: Hz
01b: kHz
10b: MHz
11b: Reserved
Bit [0] – Fixed/Variable:
0x1: The clock input frequency is variable and managed by
the Clock Source speciﬁed by ResourceSource
0x0: The clock input frequency is ﬁxed.
Byte 6 Clock Frequency Divisor_FQD value,
bits [7:0]Clock frequency divisor value, bits [7:0]. This value is used
to calculate the clock frequency. This value must not be zero.
Byte 7 Clock Frequency Divisor_FQD value,
bits [15:8]Clock frequency divisor value, bits [15:8]. This value is used
Byte 8 Clock Frequency Numerator _FQN
value, bits [7:0]Clock frequency numerator, bits [7:0]. This value is used
to calculate the clock frequency..Scale/unit is determined by
Flags [3:1]
6.4. Resource Data Types for ACPI 432Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.65 – continued from previous page
Byte 9 Clock Frequency Numerator _FQN
value, bits [15:8]Clock frequency for this clock input, bits [15:8]. This value is
used to calculate the clock frequency. Scale/unit is determined
by Flags [3:1]
Byte 10 Clock Frequency Numerator _FQN
value, bits [23:16]Default frequency for this clock input, bits [23:16]. This value
is used to calculate the clock frequency. Scale/unit is deter-
mined by Flags [3:1]
Byte 11 Clock Frequency Numerator _FQN
value, bits [31:24]Default frequency for this clock input, bits [31:24]. This value
Byte 12 Clock Source Index Clock Source Instance. If the Device speciﬁed in the Clock
Source ﬁeld in this structure supports more than one connec-
tion (e.g. clock output), this ﬁeld describes the instance of the
connection to which this Device is connected. If the Resource
Source provides a single clock signal, or the clock source de-
vice is not speciﬁed, this ﬁeld contains 0.
Byte 13 Clock Source (length = L) Name of the Clock Source Device which supplies this clock
signal. The name can be a fully qualiﬁed path, a relative path,
or a simple name segment that utilizes the namespace search
rules. This ﬁeld is optional for a clock input with a ﬁxed fre-
quency (L = 0).
6.5 Other Objects and Control Methods
Table 6.66: Other Objects and Methods
_BBN PCI bus number set up by the platform boot ﬁrmware.
_BDN Correlates a docking station between ACPI and legacy interfaces.
_DCK Indicates that the device is a docking station.
_DEP Indicates device objects that OSPM should assign a higher priority in start ordering due to future
operation region accesses.
_FIT Object that evaluates to a buffer of NFIT Structures.
_GLK Indicates the Global Lock must be acquired when accessing a device.
_INI Device initialization method that is run shortly after ACPI has been enabled.
_LSI Label Storage Information - Returns information about the Label Storage Area associated with
_LSR Label Storage Read - Returns label data from the Label Storage Area of the NVDIMM object.
_LSW Label Storage Write - Writes label data in to the Label Storage Area of the NVDIMM object.
_REG Notiﬁes AML code of a change in the availability of an operation region.
_SEG Indicates a bus segment location.
6.5. Other Objects and Control Methods 433Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.5.1 _INI (Init)
_INI is a device initialization object that performs device speciﬁc initialization. This control method is located under a
device object and is run only when OSPM loads a description table. There are restrictions related to when this method
is called and governing writing code for this method. The _INI method must only access Operation Regions that have
been indicated to available as deﬁned by the _REG method. The _REG method is described in _REG (Region) . This
control method is run before _ADR, _CID, _HID, _SUN, and _UID are run.
None
None
Before evaluating the _INI object, OSPM evaluates the _STA object for the device. If the _STA object does not exist
for the device, the device is assumed to be both present and functional. If the _STA method indicates that the device is
present, OSPM will evaluate the _INI for the device (if the _INI method exists) and will examine each of the children
of the device for _INI methods. If the _STA method indicates that the device is not present and is not functional,
OSPM will not run the _INI and will not examine the children of the device for _INI methods. If the _STA object
evaluation indicates that the device is not present but is functional, OSPM will not evaluate the _INI object, but will
examine each of the children of the device for _INI objects (see the description of _STA for the explanation of this
special case.) If the device becomes present after the table has already been loaded, OSPM will not evaluate the _INI
method, nor examine the children for _INI methods.
The OSPM performed _INI object actions based upon the _STA Present and Functional bits are summarized in the
table below.
Table 6.67: OSPM _INI Object Actions
_STA Present Bit _STA Functional Bit Actions
0 0 Do not run _INI, do not examine device children
0 1 Do not run _INI, examine device children
1 0 Run _INI, examine device children
1 1 Run _INI, examine device children
The _INI control method is generally used to switch devices out of a legacy operating mode. For example, platform
boot ﬁrmware often conﬁgures CardBus controllers in a legacy mode to support legacy operating systems. Before
enumerating the device with an ACPI operating system, the CardBus controllers must be initialized to CardBus mode.
For such systems, the vendor can include an _INI control method under the CardBus controller to switch the device
into CardBus mode.
In addition to device initialization, OSPM unconditionally evaluates an _INI object under the \_SB namespace, if
present, at the beginning of namespace initialization.
6.5.2 _DCK (Dock)
This control method is located in the device object that represents the docking station (that is, the device object with
all the _EJx control methods for the docking station). The presence of _DCK indicates to the OS that the device is
really a docking station.
_DCK also controls the isolation logic on the docking connector. This allows an OS to prepare for docking before the
bus is activated and devices appear on the bus.
Arg0 - An Integer containing a docking action code
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0 - Undock (isolate from connector)
1 - Dock (remove isolation from connector)
An Integer containing the docking status code
1 - Successful
0 - Failed
Note: When _DCK is called with 0, OSPM will ignore the return value. The _STA object that follows the _EJx
control method will notify whether or not the portable has been ejected.
6.5.3 _BDN (BIOS Dock Name)
_BDN is used to correlate a docking station reported via ACPI and the same docking station reported via legacy
interfaces. It is primarily used for upgrading over non-ACPI environments.
None
AnInteger that contains the EISA Dock ID

0 - Failed
None
_BDN must appear under a device object that represents the dock, that is, the device object with _Ejx
methods. This object must return a DWORD that is the EISA-packed DockID returned by the Plug and
Play BIOS Function 5 (Get Docking Station Identiﬁer) for a dock.
Note: If the machine does not support PNPBIOS, this object is not required.
6.5.4 _REG (Region)
The OS runs _REG control methods to inform AML code of a change in the availability of an operation region. When
an operation region handler is unavailable, AML cannot access data ﬁelds in that region. (Operation region writes will
be ignored and reads will return indeterminate data.)
Arguments: (2)
Arg0 – An Integer containing the Operation Region address space ID and optional supplementary qualiﬁer
(See Section 5.5.2.4 and Table 5.1.)
Arg1 - An Integer containing the handler connection code:
0 - disconnect the handler
1 - connect the handler
None
Except for the cases shown below, control methods must assume all operation regions are inaccessible until the
_REG(RegionSpace, 1) method is executed, where RegionSpace is the address space ID, or the address space ID
with an additional qualiﬁer, depending on the operation region. For more information on which operation regions
6.5. Other Objects and Control Methods 435Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
have address space qualiﬁers, see Access to Operation Regions . Once _REG has been executed for a particular oper-
ation region, indicating that the operation region handler is ready, a control method can access ﬁelds in the operation
region. Conversely, control methods must not access ﬁelds in operation regions when _REG method execution has not
indicated that the operation region handler is ready.
For example, until the Embedded Controller driver is ready, the control methods cannot access the Embedded Con-
troller. Once OSPM has run _REG(EmbeddedControl, 1), the control methods can then access operation regions in
Embedded Controller address space. Furthermore, if OSPM executes _REG(EmbeddedControl, 0), control methods
must stop accessing operation regions in the Embedded Controller address space.
The exceptions for the above rule are:
1. OSPM must guarantee that the following operation regions are always accessible: StepNumList-1
OSPM must guarantee that the following operation regions are always accessible:
• PCI_Conﬁg operation regions on a PCI root bus containing a _BBN object.
• SystemIO operation regions.
• SystemMemory operation regions when accessing memory returned by the System Address Map
Interfaces .
Note: Since the region types above are permanently available, no _REG methods are required, nor will
OSPM evaluate any _REG methods that appear in the same scope as the operation region declaration(s)
of these types.
2. OSPM must make Embedded Controller operation regions, accessed via the Embedded Controllers
described in ECDT, available before executing any control method. These operation regions may
become inaccessible after OSPM runs _REG(EmbeddedControl, 0).
Place _REG in the same scope as operation region declarations. The OS will run the _REG in a given scope when the
operation regions declared in that scope are available for use.
Example:
OperationRegion(OPR1, PCI_Config, ...)
Method(_REG, 2) {...} // OSPM executes this when PCIO operation region
˓→handler
// status changes
Device(PCI1) {
Method(2) {...}
Device(ETH0) {
OperationRegion(OPR2, PCI_Config, ...)
Method(_REG,2) {...}
}
}
OperationRegion(OPR4, EmbeddedControl, ...)
Method(_REG, 2) {...} // OSPM executes this when EC operation region
// handler status changes
}
}
}
When the PCI0 operation region handler is ready, OSPM will run the _REG method declared in PCI0 scope to indicate
that PCI Conﬁg space operation region access is available within the PCI0 scope (in other words, OPR1 access is
allowed). Finally, when the Embedded Controller operation region handler is ready, OSPM will run the _REG method
6.5. Other Objects and Control Methods 436Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
in the EC0 scope to indicate that EC space operation region access is available within the EC0 scope (in other words,
OPR4 access is allowed). It should be noted that PCI Conﬁg Space Operation Regions are ready as soon the host
controller or bridge controller has been programmed with a bus number. PCI1’s _REG method would not be run until
the PCI-PCI bridge has been properly conﬁgured. At the same time, the OS will also run ETH0’s _REG method since
its PCI Conﬁg Space would be also available. The OS will again run ETH0’s _REG method when the ETH0 device
is started. Also, when the host controller or bridge controller is turned off or disabled, PCI Conﬁg Space Operation
Regions for child devices are no longer available. As such, ETH0’s _REG method will be run when it is turned off
and will again be run when PCI1 is turned off.
Note: The OS only runs _REG methods that appear in the same scope as operation region declarations that use the
operation region type that has just been made available. For example, _REG in the EC device would not be run when
the PCI bus driver is loaded since the operation regions declared under EC do not use any of the operation region types
made available by the PCI driver (namely, conﬁg space, I/O, and memory).
6.5.5 _BBN (Base Bus Number)
For multi-root PCI platforms, the _BBN object evaluates to the PCI bus number that the platform boot ﬁrmware
assigns. This is needed to access a PCI_Conﬁg operation region for the speciﬁc bus. The _BBN object is located
under a PCI host bridge and must be unique for every host bridge within a segment since it is the PCI bus number.
None
An Integer that contains the PCI bus number. The lower 8 bits of _BBN returned integer is the PCI Base
Bus number. Other bits are reserved.
6.5.6 _SEG (Segment)
The optional _SEG object is located under a PCI host bridge and evaluates to an integer that describes the PCI Segment
Group (see PCI Firmware Speciﬁcation v3.0). If _SEG does not exist, OSPM assumes that all PCI bus segments are
in PCI Segment Group 0.
None
PCI Segment Group is purely a software concept managed by system ﬁrmware and used by OSPM. It is a logical
collection of PCI buses (or bus segments). There is no tie to any physical entities. It is a way to logically group the
PCI bus segments and PCI Express Hierarchies. _SEG is a level higher than _BBN.
PCI Segment Group supports more than 256 buses in a system by allowing the reuse of the PCI bus numbers. Within
each PCI Segment Group, the bus numbers for the PCI buses must be unique. PCI buses in different PCI Segment
Group are permitted to have the same bus number.
A PCI Segment Group contains one or more PCI host bridges.
The lower 16 bits of _SEG returned integer is the PCI Segment Group number. Other bits are reserved.
Example:
6.5. Other Objects and Control Methods 437Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Device(ND0) { // this is a node 0
Name(_HID, "ACPI0004")
// Returns the "Current Resources"
Name(_CRS,
ResourceTemplate() {
...
}
)
Device(PCI0) {
Name(_HID, EISAID("PNP0A03"))
Name(_ADR, 0x00000000)
Name(_SEG, 0) // The buses below the host bridge belong to PCI segment 0
...
Name(_BBN, 0)
...
}
...
...
Name(_BBN, 16)
...
}
...
}
Device(ND1) { // this is a node 1
...
}
)
Name(_SEG, 1) // The buses below the host bridge belong to PCI segment 1
...
...
}
...
...
...
}
}
6.5. Other Objects and Control Methods 438Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.5.7 _GLK (Global Lock)
This optional named object is located within the scope of a device object. This object returns a value that indicates
to any entity that accesses this device (in other words, OSPM or any device driver) whether the Global Lock must
be acquired when accessing the device. OS-based device accesses must be performed while in acquisition of the
Global Lock when potentially contentious accesses to device resources are performed by non-OS code, such as System
Management Mode (SMM)-based code in Intel architecture-based systems.
Note: Default behavior: if _GLK is not present within the scope of a given device, then the Global Lock is not
required for that device.
None
AnInteger that contains the Global Lock requirement code:
0 - The Global Lock is not required for this device
1 - The Global lock is required for this device

}
}
None
An example of device resource contention is a device driver for an SMBus-based device contending with SMM-based
code for access to the Embedded Controller, SMB-HC, and SMBus target device. In this case, the device driver must
acquire and release the Global Lock when accessing the device to avoid resource contention with SMM-based code
that accesses any of the listed resources.
6.5.8 _DEP (Operation Region Dependencies)
_DEP evaluates to a package and designates device objects that OSPM should assign a higher priority in start ordering
due to future operation region accesses.
To increase the likelihood that an SPB operation region handler is available when needed, OSPM needs to know in
advance which methods will access it – _DEP provides OSPM with this information. While the _DEP keyword may
be used to determine start ordering, only the _REG method ( _REG (Region) ) callbacks can be relied upon to determine
whether a region is accessible at a given point in time.
None.
A variable-length Package containing object references.
Example:
Device(\_SB.TC3) {
...
OperationRegion(OPRG,
GenericSerialBus,
0x00,
0x100)
...
}
Device(\_SB.TP1) {
...
6.5. Other Objects and Control Methods 439Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Name (_DEP, Package() {\_SB.TC3})
...
}
6.5.9 _FIT (Firmware Interface Table)
This method evaluates to a buffer returning data in the format of a series of NFIT Structures (See NVDIMM Firmware
Interface Table (NFIT) ). This method may appear under the NVDIMM root device (see NVDIMM Root Device ). The
_FIT method, when present, is always evaluated by OSPM.
_FIT returns all the entries in the NFIT.
The NFIT Update Notiﬁcation notiﬁcation value for the NVDIMM root device (see NVDIMM Root Device Notiﬁcation
Values ) notiﬁes OSPM that it needs to re-evaluate the _FIT method.
Note: NFIT is an ACPI table enumerated at OS boot. In case of hot plug of NVDIMMs, the corresponding NFIT
structures will not be present in NFIT. _FIT method is also used to provide these structures dynamically during hot
plug.
None
A Buffer containing a list of NFIT Structures
Example ASL for _FIT usage:
Device (NVDR) {
Name(_HID, "ACPI0012")
OperationRegion (OPRN, SystemMemory,
Offset in system memory of NFIT Structures, Length in bytes)
Field (OPRN, ByteAcc, NoLock, Preserve) {
FITD, Length in bits
}
Method (_FIT, 0) {
Return (FITD)
}
...
} // end NVDR
...
} // end scope \\_SB
6.5. Other Objects and Control Methods 440Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.5.10 NVDIMM Label Methods
The following table outlines the NVDIMM Label methods that are attached to the NVDIMM object.
Table 6.68: NVDIMM Label Methods
6.5.10.1 _LSI (Label Storage Information)
This optional object returns information about the Label Storage Area for the requested device.
None.
APackage containing the Label Storage Area information as described below
_LSI returns a package in the format below:
Package {
Status // Integer (DWORD)
SizeOfLabelStorageArea // Integer (DWORD)
MaxTransferLength // Integer (DWORD)
}
Table 6.69: _LSI Return Package Values
Field Format Description
Status Integer
(DWORD) Indicates the status of the _LSI request.
0x00000000 - Success - Returned package is valid
0x00000001 - Failure - The rest of the returned package is not valid
SizeOfLabelStorageArea Integer
(DWORD)Size of the Label Storage Area in bytes
MaxTransferLength Integer
(DWORD) Maximum amount of data in bytes supported by a single call to the
_LSR and _LSW methods. This is the minimum of the platform
supported transfer size and the transfer size supported by the
NVDIMM.
0x00000000 - the NVDIMM does not support label storage.
A non-zero value - the NVDIMM supports label storage.
6.5. Other Objects and Control Methods 441Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
6.5.10.2 _LSR (Label Storage Read)
This optional object returns label data from the Label Storage Area starting at the speciﬁed offset.
Arg0 - Offset (Integer(DWORD) the byte offset in the Label Storage Area to start reading from Arg1
- TransferLength (Integer(DWORD) the number of bytes to transfer from the Label Storage Area. A
A Package containing label data from the Label Storage Area as described below
_LSR returns a package in the format below:
Package {
LabelData // Buffer
}
Table 6.70: _LSR Return Package Values
(DWORD) Indicates the status of the _LSR request:
0x00000000 - Success
0x00000001 - Failure
0x00000002 - Invalid Input Parameters
- Offset > SizeOfLabelStorageArea reported with _LSI
- Offset + TransferLength > SizeOfLabelStorageArea reported with _LSI
- TransferLength > MaxTransferLength reported with _LSI
0x00000003 - Label Storage Area is locked and cannot be accessed
0x00000004 - HW failure prevented data from being read
Note: Any other non-zero values reﬂect a failure.
LabelData Buffer Contains the returned label storage data. The size of the output is equal to Transfer-
Length if Status is Success; otherwise, the contents of the output buffer shall be 0.
The format of the Label Storage Area data is deﬁned in UEFI.
6.5.10.3 _LSW (Label Storage Write)
This optional object writes label data to the Label Storage Area starting at the speciﬁed offset.
• Arg0 - Offset (Integer(DWORD) the byte offset in the Label Storage Area to which the Label Data is to be
written to the target NVDIMM
• Arg1 - TransferLength (Integer(DWORD) the number of bytes to transfer to the Label Storage Area. A Trans-
ferLength of 0 writes no data.
• Arg2 - LabelData (Buffer) the label data to write in to the Label Storage Area. The size of the LabelData is as
indicated by TransferLength ﬁeld above. The format of the Label Storage Area data is deﬁned in UEFI.
6.5. Other Objects and Control Methods 442Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
An Integer (DWORD) containing the status of the _LSW as follows:
• 0x00000000 - Success
• 0x00000001 - Failure
• 0x00000002 - Invalid Input Parameters:
–Offset > SizeOfLabelStorageArea reported with _LSI
–Offset + TransferLength > SizeOfLabelStorageArea reported with _LSI
–TransferLength > MaxTransferLength reported with _LSI
• 0x00000003 - Label Storage Area is locked and cannot be accessed
• 0x00000004 - HW failure prevented data from being written
Note: Any other non-zero values indicate a failure.
6.5.11 _CBR (CXL Host Bridge Register Info)
This object is an optional control method that is invoked by OSPM to determine the memory location of CXL Host
Bridge Registers and the version that represents the register layout. The _CBR object is located under a CXL Host
Bridge Device and must return unique value for every CXL Host Bridge instance within a system.
For CXL host bridges that are present at boot time, CEDT shall provide the Host bridge register base address. The
_UID object is required in the Host Bus Device in order to allow OSPM to match entries in the CEDT to devices
present in the ACPI namespace.
For more information on CEDT, see http://ueﬁ.org/acpi for the heading “CXL Early Discovery Table”.
None
A package containing the CXL Host Bridge Register Information as described below:
Package {
Version, //Integer (DWORD)
Base, //Integer (DWORDQWORD)
Length //Integer (DWORD)
}
Table 6.71: _CBR Return Package Values
Version Integer (DWORD)
The version number that represents the layout of Host Bridge Register
Block:
0x00000000: Follow the CXL 1.1 Speciﬁcation
0x00000001: Follow the CXL 2.0 Speciﬁcation
6.5. Other Objects and Control Methods 443Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 6.71 – continued from previous page
Base Integer (QWORD)
64-bit memory address of the Host Bridge Register block:
If Version = 0, this represents the base address of CXL 1.1
downstream port RCRB
If Version = 1, this represents the base address of the CXL 2.0
Host Bridge Component Registers (CHBCR)
Length Integer (DWORD)
Length of the Host Bridge Register Block in bytes:
If Version = 0, this ﬁeld must be set to 8 KB (0x2000)
If Version = 1, this ﬁeld must be set to 64 KB (0x10000)
Note: Links to the CXL 1.1 and CXL 2.0 Speciﬁcations can be found at http://ueﬁ.org/acpi, under the corresponding

}
Block:
headings for each spec.
Example :
Device(CXL0 ) {
Name(_HID, "ACPI0016") // New HID to indicate CXL hierarchy
Name(_CID, EISAID ("PNP0A08")) // To support legacy OSs that understands PCIe
// but not the new HID
Name(_UID, 0)
Method (_CBR, 0) {
Return( 0x00, DP_RCRB_BASE, 0x2000)
}
// Standard PCIe methods like _ BBN, _CRS.
// PCIe _CRS describes .IO resources. PCIe _BBN describes bus number of CXL RCiEP
// PCIe _OSC is used to negotiate control of CXL.IO capabilities
...
}
6.5. Other Objects and Control Methods 444CHAPTER
SEVEN
POWER AND PERFORMANCE MANAGEMENT
This section speciﬁes the objects that support the device power management and system power management models
described in ACPI Concepts . OSPM uses these objects to manage the platform by achieving a desirable balance
between performance and energy conservation goals.
The system state indicator objects are also speciﬁed in this section.
7.1 Power Resource Objects and the Power Management Models
A Power Resource object refers to a software-controllable power plane, clock plane, or other resource upon which
an ACPI power-managed device might rely. The unique way that these power resources are distributed to the devices
across a given system sets the constraints within which OSPM must optimize the use of power, by individual devices
as well as by the system as a whole. ACPI deﬁnes objects that reference power resources (or device states that, in
turn, reference power resources) to enable OSPM to discover the constraints and capabilities of a given system. As
power is managed during system operation, power savings are obtained by turning power resources off and on at the
appropriate times. The following table describes how objects from this section provide the information and control
required by OSPM to implement and coordinate the power management models.
Table 7.1: Power Resource Object Provisions for Information and
Control
Power mgmt function
to be performedSystem entity
performing itPlatform info re-
quiredObject providing
informationComments
Choose a supported de-
vice state to save power
while device is idleDevice Power
Policy OwnerList of states (D0
through D3hot,
and D3cold)
supported by the
device_PRx, PSx D3cold support is indi-
cated by explicitly pro-
viding _PR3. D3hot
is assumed to be sup-
ported in all cases.
445Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 7.1 – continued from previous page
vice state to enable a
targeted system sleep or
Low-power Idle stateDevice Power
supported by
the device in the
targeted system
sleep state_PRx, Power
Resource Decla-
ration, _SxD_PRx maps device
states to Power Re-
sources, Power Re-
source deﬁnition maps
Power Resources to
system states. _SxD
provides the system
state-to-device state
mapping explicitly in
case power resources
do not produce the
information (*see note
below).
Choose a device state
that supports WakeDevice Power
Policy OwnerList of supported
states, ﬁltered by
ability to cause a
wake event_PRW, _SxW Addition of the require-
ment for additional
power resources listed
in _PRW cause wake-
incapable states to be
removed from the list
of supported states
(above) SxW deﬁnes
the mapping of wake
capable device states to
system states
Arm a device for wake OSPM Control mech-
anisms for
enabling wake at
the platform level_PRW, Wake-
capable device
interrupt, _DSW_PRW speciﬁes the
GPE bit to enable for
wake. On HW-reduced
platforms, the wake-
capable attribute of a
device interrupt indi-
cates which interrupt
to enable for wake
_DSW is optional,
depending on the needs
of the platform wake
hardware
Enter a selected device
stateOSPM Control mecha-
nisms for power
resources_ON, _OFF, _PSx _ON and _OFF con-
trol the power resources
PSx controls other plat-
form hardware relevant
to state changes but not
exposed to OSPM as
power resources (*see
note below).
Choose a targeted sys-
tem sleep stateSystem Power
system Sleep
states (S1-S4)_Sx S0 and S5 are assumed
to be supported in all
cases
7.1. Power Resource Objects and the Power Management Models 446Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Enter a selected system
nisms for system
states_PTS, _TTS and
_WAKIf _S5 exists, ACPI uses
the SLP_TYP/SLP_EN
bit ﬁelds in the PM1
Control Register (or the
SLEEP_CONTROL/
SLEEP_STATUS reg-
isters speciﬁed in the
FADT). If _S5 is not
speciﬁed, alternative
methods are used to
turn-off the system.
Note: * Support for Low-power Idle states requires the use of power resources to describe the device state and wake
dependencies. See Processor Aggregator Device and_LPI (Low Power Idle States) .
7.2 Declaring a Power Resource Object
An ASL PowerResource statement is used to declare a PowerResource object. A Power Resource object refers to
a software-controllable power plane, clock plane, or other resource upon which an integrated ACPI power-managed
device might rely. Power resource objects can appear wherever is convenient in the namespace.
The syntax of a PowerResource statement is:
PowerResource (resourcename, systemlevel, resourceorder) {TermList}
where the systemlevel parameter is a number and the resourceorder parameter is a numeric constant (a WORD). For a
formal deﬁnition of the PowerResource statement syntax, see Section 7.2.
Systemlevel is the deepest system sleep level OSPM must maintain to keep this power resource on (0 equates to S0, 1
equates to S1, and so on).
Each power-managed ACPI device lists the resources it requires for its supported power states. OSPM multiplexes this
information from all devices and then enables and disables the required Power Resources accordingly. The resource-
order ﬁeld in the Power Resource object is a value per Power Resource that provides the system with the order in which
Power Resources must be enabled or disabled. Each unique resourceorder value represents a level, and any number of
power resources may have the same level. Power Resource levels are enabled from low values to high values and are
disabled from high values to low values. The operating software enables or disables all Power Resources in any one
resourceorder level at a time before moving on to the next ordered level. Putting Power Resources in different order
levels provides power sequencing and serialization where required. Note that no ordering is guaranteed within each
level (i.e. between Power Resources with the same resourceorder value).
A Power Resource can have named objects under its Namespace location. For a description of the ACPI-deﬁned
named objects for a Power Resource, see Device Power Management Objects
The power management object list is encoded as TermList, so that rather than describing a static power management
object list, it is possible to describe a dynamic power management object list according to the system settings. See
“Deﬁnition Block Loading .
The following ASL code block example demonstrates the use of a PowerResource:
7.2. Declaring a Power Resource Object 447Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PowerResource(PIDE, 0, 0) {
Method(_STA) {
Return (Xor (GIO.IDEI, One, Zero)) // inverse of isolation
}
Method(_ON) {
Store (One, GIO.IDEP) // assertpower
Sleep (10) // wait 10ms
Store (One, GIO.IDER) // de- assertreset #
Stall (10) // wait 10us
Store (Zero, GIO.IDEI) // de- assertisolation
}
Method(_OFF) {
Store (One, GIO.IDEI) // assertisolation
Store (Zero, GIO.IDER) // assertreset #
Store (Zero, GIO.IDEP) // de- assertpower
}
}
7.2.1 Deﬁned Methods for a Power Resource
The Power Resource Methods table below lists the control methods that may be deﬁned under a power resource. _ON,
_OFF and _STA are required to allow basic control of each power resource. _RST is required in cases where reset of
devices is managed through a shared power resource. As OSPM changes the state of device objects in the system, the
power resources that are needed will also change, causing OSPM to turn power resources on and off. To determine
the initial power resource settings the _STA method can be used. _RST is required in cases where reset of devices is
controlled through a shared Power Resource (see _RST (Device Reset) ).
Table 7.2: Power Resource Methods
_OFF Set the resource off.
_ON Set the resource on.
_RST Object that executes a platform level reset of all devices that list this resource in their _PRR
object. (See _RST (Device Reset) for a description of this object.)

}
}
_STA Object that evaluates to the current on or off state of the Power Resource. 0-OFF, 1-ON
7.2.2 _OFF
This power resource control method puts the power resource into the OFF state. The control method must not complete
until the power resource is off, including any required sequencing delays between, or after, operations on the power
resource. OSPM is required to turn on or off only one resource at a time. The AML code can use Stall or Sleep within
the method to cause the proper sequencing delays. OSPM is not required to run the _STA method to conﬁrm that the
resource has been successfully turned off, and may run the _OFF method repeatedly, even if the resource is already
off.
None
None
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7.2.3 _ON
This power resource control method puts the power resource into the ON state. The control method must not complete
until the power resource is on, including any required sequencing delays between, or after, operations on the power
resource has been successfully turned on, and may run the _ON method repeatedly, even if the resource is already on.
None
None
7.2.4 _STA (Power Resource Status)
Returns the current ON or OFF status for the power resource.
None
An Integer containing the current power status of the device:
• 0 - The power resource is currently off
• 1 - The power resource is currently on
7.2.5 Passive Power Resources
In some platforms, certain power resources may be shared between devices and processors, requiring both to be in
speciﬁc idle states before they can be turned off. Direct OSPM control of such resources is not possible while the
OS is running because the processors depend on the resources being enabled whilst they are running. It is only when
processors go idle that it may be possible to turn off these shared resources. For a given resource of this type this is
only possible if, in addition to the processors being idle, any other devices that depend on the resource are in a state
that allows powering it down. In these cases, the platform can manage the power resource as part of entry/exit from a
Low Power Idle (LPI) state and OSPM can guide the decision on whether or not to turn off the resources with its LPI
state request. In those cases the power resource _ON/_OFF/_STA methods are completely redundant.
Passive power resources, which are just like traditional power resources except they do not include _ON, _OFF, or
_STA, are introduced to support this case. Omission of these methods reduces overhead by avoiding redundant evalu-
ations and saves the platform from having to supply (working) methods which it does not need. Since OSPM cannot
manage passive power resources directly via _ON/_OFF, passive power resources must be listed as a dependency of
at least one LPI state where the platform will manipulate them. The dependencies between LPI states and power
resources are described in the _RDI object. See _RDI (Resource Dependencies for Idle) for additional details.
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7.3 Device Power Management Objects
For a device that is power-managed using ACPI, a Deﬁnition Block contains one or more of the objects found in the
table below. Power management of a device is done using Power Resource control.
Power Resources are resources that could be shared amongst multiple devices. The operating software will automat-
ically handle control of these devices by determining which particular Power Resources need to be in the ON state at
any given time. This determination is made by considering the state of all devices connected to a Power Resource. At
all times, OSPM ensures that any Power Resources no longer referenced by any device in the system is in the OFF
state.
For systems that do not control device power states through power resource management (i.e. _PSx controls power
transitions), but whose devices support multiple D-states, more information is required by the OS to determine the
S-state to D-state mapping for the device. The ACPI ﬁrmware can give this information to OSPM by way of the _SxD
methods. These methods tell OSPM for S-state “x”, the shallowest D-state supported by the device is “y.” OSPM is
allowed to pick a deeper D-state for a given S-state, but OSPM is not allowed to go shallower than the given D-state.
Additional rules that apply to device power management objects are:
• A device cannot be in a shallower D-state than its parent device.
• If there exists an ACPI Object to set a device to D0 (either through _PSx or _PRx objects), then the correspond-
ing object to set the device into a deeper Dx must also be declared, and vice versa.
• If any ACPI Object that controls power (_PSx or _PRx, where x =0, 1, 2, or 3) exists, then methods to set the
device into D0 and D3 device states (at least) must be present.
• If a mixture of _PSx and _PRx methods is declared for the device, then the device states supported through _PSx
methods must be identical to the device states supported through _PRx methods.
Note: For non-ACPI devices (bus-enumerated devices like USB or PCI), architectural bus deﬁnitions may have more
stringent requirements.
When controlling power to devices which must wake the system during a system sleeping state:
• The device must declare its ability to wake the system by declaring either the _PRW or _PSW object.
• After OSPM has called _PTS, it must call the device’s _PSW to enable wake.
• OSPM must transition a device into a D-state which is deeper than or equal to that speciﬁed by the device’s
_SxD object (if present) to enable entry into Sx, but shallower than or equal to that speciﬁed by the device’s
_SxW object so that it can still wake the system.
• OSPM may transition the system to the speciﬁed sleep state.
Table 7.3: Device Power Management Child Objects
_DSW Control method that enables or disables the device’s wake function for device-only wake.
_PS0 Control method that puts the device in the D0 device state (device fully on).
_PS1 Control method that puts the device in the D1 device state.
_PS2 Control method that puts the device in the D2 device state.
_PS3 Control method that puts the device in the D3 device state (device off).
_PSC Object that evaluates to the device’s current power state.
_PR0 Object that evaluates to the device’s power requirements in the D0 device state (device fully on).
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_PR1 Object that evaluates to the device’s power requirements in the D1 device state. The only devices
that supply this level are those that can achieve the deﬁned D1 device state according to the related
device class.
_PR2 Object that evaluates to the device’s power requirements in the D2 device state. The only devices
that supply this level are those that can achieve the deﬁned D2 device state according to the related
_PR3 Object that evaluates to the device’s power requirements in the D3hot device state.
_PRW Object that evaluates to the device’s power requirements in order to wake the system from a
system sleeping state.
_PSW Control method that enables or disables the device’s wake function.
_IRC Object that signiﬁes the device has a signiﬁcant inrush current draw.
_S1D Shallowest D-state supported by the device in the S1 state
_S2D Shallowest D-state supported by the device in the S2 state
_S3D Shallowest D-state supported by the device in the S3 state
_S4D Shallowest D-state supported by the device in the S4 state
_S0W Deepest D-state supported by the device in the S0 state which can wake the device
_S1W Deepest D-state supported by the device in the S1 state which can wake the system.
_S2W Deepest D-state supported by the device in the S2 state which can wake the system.
_S3W Deepest D-state supported by the device in the S3 state which can wake the system.
_S4W Deepest D-state supported by the device in the S4 state which can wake the system.
_RST Control method that executes a function level reset of the device.
_PRR Object that evaluates to the device’s platform level reset requirements.
_DSC Object that evaluates to the device’s deepest power state for conﬁguration.
7.3.1 _DSW (Device Sleep Wake)
In addition to _PRW, this control method can be used to enable or disable the device’s ability to wake a sleeping
system. This control method can only access Operation Regions that are either always available while in a system

working state or that are available when the Power Resources referenced by the _PRW object are all ON. For example,
do not put a power plane control for a bus controller within conﬁguration space located behind the bus. The method
should enable the device only for the last system state/device state combination passed in by OSPM. OSPM will only
pass in combinations allowed by the _SxD and _SxW objects.
The arguments provided to _DSW indicate the eventual Device State the device will be transitioned to and the eventual
system state that the system will be transitioned to. The target system state is allowed to be the system working state
(S0). The _DSW method will be run before the device is placed in the designated state and also before the system is
placed in the designated system state.
Compatibility Note: The _PSW method was deprecated in ACPI 3.0. The _DSW method should be used instead.
OSPM will only use the _PSW method if OSPM does not support _DSW or if the _DSW method is not present.
Arguments (3):
• Arg0 - An Integer that contains the device wake capability control
–0 - Disable the device’s wake capabilities
–1 - Enable the device’s wake capabilities
• Arg1 - An Integer that contains the target system state (0-4)
• Arg2 - An Integer that contains the target device state
–0 - The device will remain in state D0
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–1 - The device will be placed in either state D0 or D1
–2 - The device will be placed in either state D0, D1, or D2
–3 - The device will be placed in either state D0, D1, D2, or D3
None
7.3.2 _PS0 (Power State 0)
This Control Method is used to put the speciﬁc device into its D0 state. This Control Method can only access Operation
Regions that are either always available while in a system working state or that are available when the Power Resources
references by the _PR0 object are all ON.
None
None
7.3.3 _PS1 (Power State 1)
This control method is used to put the speciﬁc device into its D1 state. This control method can only access Operation
Regions that are either always available while in the system working state (S0) or that are available when the Power
Resources referenced by the _PR0 object are all ON.
None
None
7.3.4 _PS2 (Power State 2)
This control method is used to put the speciﬁc device into its D2 state. This control method can only access Operation
Resources referenced by the _PR0 and _PR1 objects are all ON.
None
None
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7.3.5 _PS3 (Power State 3)
This control method is used to put the speciﬁc device into its D3 state. This control method can only access Operation
Resources referenced by the _PR0, _PR1 and PR2 objects are all ON.
None
None
7.3.6 _PSC (Power State Current)
This control method evaluates to the current device state. This control method is not required if the device state can
be inferred by the Power Resource settings. This would be the case when the device does not require a _PS0, _PS1,
_PS2, or _PS3 control method.
None
An Integer that contains a code for the current device state. The device state codes are shown in :the
following table.
Table 7.4: PSC Device State Codes
0D0
1D1
2D2
3D3
7.3.7 _PSE (Power State for Enumeration)
This control method is used to put a device into a powered mode appropriate for enumeration by its parent bus. This
control method can only access Operation Regions that are either always available while in a system working state or
that are available when the Power Resources referenced by the _PRE object are all ON.
Arg1 - An Integer indicating whether Enumeration power has been turned ON or will be turned OFF:
• 0 - OFF
• 1 - ON
None
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7.3.8 _PR0 (Power Resources for D0)
This object evaluates to a list of power resources upon which this device is dependent when it is operating in the D0
state. For OSPM to put the device into the D0 device state, the following must occur in this order:
1. All Power Resources referenced by elements 1 through N must be in the ON state.
2. All Power Resources no longer referenced by any device in the system must be in the OFF state.
3. If present, the _PS0 control method is executed to set the device into the D0 device state.
None
A variable-length Package containing a list of References to power resources.
This object returns a package as deﬁned below:
Table 7.5: Power Resource Requirements Package
Element Object Description
1 object reference Reference to required Power Resource #0
N object reference Reference to required Power Resource #N
_PR0 must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
7.3.9 _PR1 (Power Resources for D1)
This object evaluates to a list of power resources upon which this device is dependent when it is in the D1 state. For
OSPM to transition the device from the D0 state into the D1 state, the following must occur, in order:
1. If present, the _PS1 control method is executed to set the device into the D1 device state.
2. All Power Resources referenced by elements 1 through N must be in the ON state.
3. All Power Resources no longer referenced by any device in the system must be in the OFF state.
None
This object evaluates to a package as deﬁned in Power Resource Requirements Package .
_PR1 must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
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7.3.10 _PR2 (Power Resources for D2)
This object evaluates to a list of power resources upon which this device is dependent when it is in the D2 state. For
OSPM to transition the device into the D2 state, the following must occur, in order:
1. If present, the _PS2 control method is executed to set the device into the D2 device state.
None
_PR2 must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
7.3.11 _PR3 (Power Resources for D3hot)
This object evaluates to a list of power resources upon which this device is dependent when it is in the D3hot state.
For OSPM to transition the device into the D3hot state, the following must occur, in order:
1. If present, the _PS3 control method is executed to set the device into the D3hot device state.
None
_PR3 must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
Interaction between _PR3 and entry to D3/D3hot (only applicable if platform and OSPM have performed the necessary
handshake via _OSC):
• Platform/drivers must assume that the device will have power completely removed when the device is place into
“D3” via _PS3
• It is up to OSPM to determine whether to use D3 or D3hot. If there is a _PR3 for the device, it is up to OSPM
to decide whether to keep those power resources on or off after executing _PS3. The decision may be based on
other factors (e.g., being armed for wake).
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7.3.12 _PRE (Power Resources for Enumeration)
This object appears under a device and evaluates to a list of power resources that are required for enumeration of the
device by its parent bus. For the bus driver to enumerate any devices while they are in the D3Cold device state, OSPM
must ensure that the following occur:
2. If present, the _PSE control method is executed to perform any actions on the device to make it accessible for
enumeration.
None

None
_PRE must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
7.3.13 _PRW (Power Resources for Wake)
This object evaluates to a list of power resources upon which this device depends for wake. It also contains additional
information needed for wake, including wake events and sleep or soft-off state information. _PRW is only required
for devices that have the ability to wake the system from a system sleeping state.
Four types of general purpose events are supported:
• GPEs that are deﬁned by a GPE block described within the FADT.
• GPEs that are deﬁned by a GPE Block Device.
• GPIO-signaled events that are deﬁned by _AEI object of the GPIO controller device
• Interrupt-signaled events that are deﬁned by _CRS object of the Generic Event Device (GED)
The four types of events are differentiated by the type of the EventInfo object in the returned package. For FADT-
based GPEs, EventInfo is an Integer containing a bit index. For Block Device-based GPEs, EventInfo is aPackage
containing a Reference to the parent block device and an Integer containing a bit index. For GPIO-signaled events,
EventInfo is aPackage containing a Reference to the GPIO controller device and an Integer containing the index of
the event in the _AEI object (starting from zero). For Interrupt-signaled events, EventInfo is aPackage containing a
Reference to the GED and an Integer containing the index of the event in the _CRS object (starting from zero).
For HW-Reduced ACPI platforms that do not support wake on GPIO-signaled or Interrupt-signaled events, the
EventInfo structure is an Integer with value of zero, and is ignored by OSPM. Therefore, _PRW is only required
on such platforms if power resources for wakeup must be managed by OSPM (e.g. the _PRW provides a list of Power
Resources). Instead, for a device to wake the system, its interrupt must be wake-capable and enabled by the driver.
SeeInterrupt-based Wake Events .
None
A variable-length Package containing wake information and a list of References to power resources.
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Package {
EventInfo // Integer orPackage
DeepestSleepState // Integer
PowerResource [0] // Reference
. . .
PowerResource [n] // Reference
}
IfEventInfo is aPackage , it contains event block device information as described below:
Package {
DeviceName // Reference
Index // Integer
}
EventInfo may be either an Integer or aPackage , depending on the event type:
• If it is an Integer , then it contains the bit index of the wake event within the FADT-based GPE enable register.
• If it is a Package , then the package contains event info for an event within either a GPE block device, GPIO
controller device, or a GED. It contains a Reference to the device and an Integer . IfEventInfo references
a GPE block device, the integer contains the bit index of the wake GPE within the Block Device-based GPE
enable register. If the EventInfo references a GPIO controller device, the integer contains the zero-based index
of the event within the _AEI object. If the EventInfo references a GED, the integer contains the zero-based index
of the event within the _CRS object.
DeepestSleepState is an Integer that contains the deepest power system sleeping state that can be entered while still
providing wake functionality.
PowerResource 0-n areReferences to required power resource objects.
Additional Information
For OSPM to have the deﬁned wake capability properly enabled for the device, the following must occur:
1. All Power Resources referenced by elements 2 through N are put into the ON state.
a. If present, the _DSW control method is executed to set the device-speciﬁc registers to enable
the wake functionality of the device.
b. The D-state being entered must be deeper than or equal to that speciﬁed in the _SxD state
but shallower than or equal to that speciﬁed in the _SxW state.
Then, if the system enters a sleeping state OSPM must ensure:
2. Interrupts are disabled.
3. The sleeping state being entered must be less than or equal to the power state declared in element 1 of the _PRW
object.
4. The proper general-purpose register bits are enabled.
The system sleeping state speciﬁed must be a state that the system supports (in other words, a corresponding \_Sx
object must exist in the namespace).
_PRW must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
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7.3.14 _PSW (Power State Wake)
In addition to the _PRW control method, this control method can be used to enable or disable the device’s ability to
wake a sleeping system. This control method can only access Operation Regions that are either always available while
in a system working state or that are available when the Power Resources references by the _PRW object are all ON.
For example, do not put a power plane control for a bus controller within conﬁguration space located behind the bus.
Note: Regarding compatability–The _PSW method was deprecated in ACPI 3.0. OSPM must use _DSW if it is
present. Otherwise, it may use _PSW.
Arg0 - An Integer containing a wake capability control:
0 - Disable the device’s wake capabilities
1 - Enable the device’s wake capabilities
None
7.3.15 _IRC (In Rush Current)
Indicates that this device can cause a signiﬁcant in-rush current when transitioning to state D0.
None
None
The presence of this object signiﬁes that transitioning the device to its D0 state causes a system-signiﬁcant in-rush
current load. In general, such operations need to be serialized such that multiple operations are not attempted concur-
rently. Within ACPI, this type of serialization can be accomplished with the ResourceOrder parameter of the device’s
Power Resources; however, this does not serialize ACPI-controlled devices with non-ACPI controlled devices. _IRC
is used to signify this fact outside of OSPM to OSPM such that OSPM can serialize all devices in the system that have
in-rush current serialization requirements.
OSPM can only transition one device containing an _IRC object within its device scope to the D0 state at a time.
It is important to note that OSPM does not evaluate the _IRC object. It has no deﬁned input arguments nor does it
return any value. OSPM derives meaning simply from the existence of the _IRC object.
7.3.16 _S1D (S1 Device State)
This object evaluates to an integer that conveys to OSPM the shallowest D-state supported by this device in the S1
system sleeping state. _S1D must return the same integer each time it is evaluated. This value overrides an S-state to
D-state mapping OSPM may ascertain from the device’s power resource declarations. See PSC Device State Codes
for valid return values.
None
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AnInteger containing the shallowest D-state supported in state S2
If the device can wake the system from the S1 system sleeping state (see _PRW) then the device must support wake
in the D-state returned by this object. However, OSPM cannot assume wake from the S1 system sleeping state is
supported in any deeper D-state unless speciﬁed by a corresponding _S1W object. The table below provides a mapping
from Desired Actions to Resultant D-state entered based on the values returned from the _S1D, _PRW, and _S1W
objects if they exist . (D/C means Don’t Care - evaluation is irrelevant, and N/A means Non Applicable - object does
not exist).
Table 7.6: S1 Action / Result Table
Desired Action _S1D _PRW _S1W Resultant D-state
Enter S1 D/C D/C D/C OSPM decides
Enter S1, No Wake 2 D/C D/C Enter D2 or D3
Enter S1, Wake 2 1 N/A Enter D2
Enter S1, Wake 2 1 3 Enter D2 or D3
Enter S1, Wake N/A 1 2 Enter D0,D1 or D2
7.3.17 _S2D (S2 Device State)
This object evaluates to an integer that conveys to OSPM the shallowest D-state supported by this device in the S2
system sleeping state. _S2D must return the same integer each time it is evaluated. This value overrides an S-state to
None
If the device can wake the system from the S2 system sleeping state (see _PRW) then the device must support wake
in the D-state returned by this object. However, OSPM cannot assume wake from the S2 system sleeping state is
supported in any deeper D-state unless speciﬁed by a corresponding _S2W object. The table below provides a mapping

None
from Desired Actions to Resultant D-state entered based on the values returned from the _S2D, _PRW, and _S2W
Table 7.7: S2 Action / Result Table
Desired Action _S2D _PRW _S2W Resultant D-state
Enter S2 D/C D/C D/C OSPM decides
Enter S2, No Wake 2 D/C D/C Enter D2 or D3
Enter S2, Wake 2 2 N/A Enter D2
Enter S2, Wake 2 2 3 Enter D2 or D3
Enter S2, Wake N/A 2 2 Enter D0,D1 or D2
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7.3.18 _S3D (S3 Device State)
This object evaluates to an integer that conveys to OSPM the shallowest D-state supported by this device in the S3
system sleeping state. _S3D must return the same integer each time it is evaluated. This value overrides an S-state to
None
AnInteger containing the shallowest D-state supported in state S3
If the device can wake the system from the S3 system sleeping state (see _PRW) then the device must support wake
in the D-state returned by this object. However, OSPM cannot assume wake from the S3 system sleeping state is
supported in any deeper D-state unless speciﬁed by a corresponding _S3W object. The table below provides a mapping
from Desired Actions to Resultant D-state entered based on the values returned from the _S3D, _PRW, and _S3W
Table 7.8: S3 Action / Result Table
Desired Action _S3D _PRW _S3W Resultant D-state
Enter S3 N/A D/C N/A OSPM decides
Enter S3, No Wake 2 D/C D/C Enter D2 or D3
Enter S3, Wake 2 3 N/A Enter D2
Enter S3, Wake 2 3 3 Enter D2 or D3
Enter S3, Wake N/A 3 2 Enter D0, D1, or D2
7.3.19 _S4D (S4 Device State)
This object evaluates to an integer that conveys to OSPM the shallowest D-state supported by this device in the S4
system sleeping state. _S4D must return the same integer each time it is evaluated. This value overrides an S-state to
D-state mapping OSPM may ascertain from the device’s power resource declarations. See Table 7.9 for valid return
values.
None
AnInteger containing the shallowest D-state supported in state S4.
If the device can wake the system from the S4 system sleeping state (see _PRW) then the device must support wake
in the D-state returned by this object. However, OSPM cannot assume wake from the S4 system sleeping state is
supported in any deeper D-state unless speciﬁed by a corresponding _S4W object. The table below provides a mapping
from Desired Actions to Resultant D-state entered based on the values returned from the _S4D, _PRW, and _S4W
objects if they exist. (D/C means Don’t Care - evaluation is irrelevant, and N/A means Non Applicable - object does
Table 7.9: S4 Action / Result Table
Desired Action _S4D _PRW _S4W Resultant D-state
Enter S4, No Wake 2 D/C D/C Enter D2 or D3
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Enter S4, Wake 2 4 N/A Enter D2
Enter S4, Wake 2 4 3 Enter D2 or D3
Enter S4, Wake N/A 4 2 Enter D0, D1, or D2
7.3.20 _S0W (S0 Device Wake State)
This object evaluates to an integer that conveys to OSPM the deepest D-state supported by this device in the S0 system
sleeping state where the device can wake itself.
None
An Integer containing the deepest D-state that supports wake in state S0. If OSPM has not indicated that it
supports _PR3 through the OSPM Platform-Wide Capabilities (see Platform-Wide OSPM Capabilities ),
then the value “3” corresponds to D3. If it has indicated _PR3 support, the value “3” represents D3hot
and the value “4” represents D3cold.
_S0W must return the same integer each time it is evaluated. This value allows OSPM to choose the
deepest power D-state and still achieve wake functionality. If object evaluates to zero, then the device
cannot wake itself from any deeper D state.
7.3.21 _S1W (S1 Device Wake State)
This object evaluates to an integer that conveys to OSPM the deepest D-state supported by this device in the S1 system
sleeping state that can wake the system.
None
An Integer containing the deepest D-state that supports wake in state S1. If OSPM has not indicated that it
_S1W must return the same integer each time it is evaluated. This value allows OSPM to choose a deeper
S-state to D-state mapping than speciﬁed by _S1D. This value must always be greater than or equal to
_S1D, if _S1D is present.
7.3.22 _S2W (S2 Device Wake State)
This object evaluates to an integer that conveys to OSPM the deepest D-state supported by this device in the S2 system
None
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An Integer containing the deepest D-state that supports wake in state S2. If OSPM has not indicated that it
_S2W must return the same integer each time it is evaluated. This value allows OSPM to choose a deeper
S-state to D-state mapping than speciﬁed by _S2D. This value must always be greater than or equal to
_S2D, if _S2D is present.
7.3.23 _S3W (S3 Device Wake State)
This object evaluates to an integer that conveys to OSPM the deepest D-state supported by this device in the S3 system
None
An Integer containing the deepest D-state that supports wake in state S3. If OSPM has not indicated that it
_S3W must return the same integer each time it is evaluated. This value allows OSPM to choose a deeper
S-state to D-state mapping than speciﬁed by _S3D. This value must always be greater than or equal to
_S3D, if _S3D is present.
7.3.24 _S4W (S4 Device Wake State)
This object evaluates to an integer that conveys to OSPM the deepest D-state supported by this device in the S4 system
None
An Integer containing the deepest D-state that supports wake in state S4. If OSPM has not indicated that it
_S4W must return the same integer each time it is evaluated. This value allows OSPM to choose a deeper
S-state to D-state mapping than speciﬁed by _S4D. This value must always be greater than or equal to
_S4D, if _S4D is present.
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7.3.25 _RST (Device Reset)
This object executes a reset on the associated device or devices. If included in a device context, the reset must not
affect any other ACPI-described devices; if included in a power resource for reset (_PRR), the reset must affect all
ACPI-described devices that reference it.
When this object is described in a device context, it executes a function level reset that only affects the device it is
associated with; neither parent nor children should be affected by the execution of this reset. Executing this must only
result in this device resetting without the device appearing as if it has been removed from the bus altogether, to prevent
OSPM re-enumeration of devices on hot-pluggable buses (e.g. USB).
If a device reset is supported by the platform, but cannot meet the function level and bus requirement, the device should
instead implement a _PRR ( _PRR (Power Resource for Reset) ).
Devices can deﬁne both an _RST and a _PRR if supported by the hardware.
None
None
7.3.26 _PRR (Power Resource for Reset)
This object evaluates to a single reference to a power resource. The power resource that this references must implement
a _RST method ( _RST (Device Reset) ).

None
None
None
A single element Package containing a Reference to the power reset resource.
7.3.27 _DSC (Deepest State for Conﬁguration)
This optional object evaluates to an integer that conveys to OSPM the deepest D-state the device can be in before
evaluating the _CRS, _PRS and _SRS conﬁguration objects for it.
If _DSC is present and the current power state of the device is not deeper than the one represented by its return value,
the device’s _CRS, _PRS (if present) and _SRS (if present) conﬁguration objects (see Device Conﬁguration Objects )
can be safely evaluated without putting the device into D0.
Therefore, when present, the _DSC object allows the OSPM to optimize device power management by avoiding an
unnecessary change to device power state that would be otherwise made before evaluating conﬁguration objects for
None
An Integer representing the deepest D-state the device can be in during conﬁguration. If OSPM has not
indicated that it supports _PR3 through the OSPM Platform-Wide Capabilities (see Platform-Wide OSPM
Capabilities ), then the value “3” corresponds to D3. If it has indicated _PR3 support, the value “3”
represents D3hot and the value “4” represents D3cold.
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The _DSC return value must represent a D-state that is supported by the device. In particular, “4” (D3cold)
can be returned only if _PR3 is present.
_DSC must return the same integer each time it is evaluated.
The _DSC return value must not represent a D-state shallower then the one resulting from turning ON all
of the power resources listed by _PRE (if present) and evaluating _PSE (if present).
7.4 OEM-Supplied System-Level Control Methods
An OEM-supplied Deﬁnition Block provides some number of controls appropriate for system-level management.
These are used by OSPM to integrate to the OEM-provided features. The following table lists the deﬁned OEM
system controls that can be provided.
Table 7.10: BIOS-Supplied Control Methods for System-Level Func-
tions
\_PTS Control method used to notify the platform of impending sleep transition.
\_S0 Package that deﬁnes system \_S0 state mode.
\_S1 Package that deﬁnes system \_S1 state mode.
\_S2 Package that deﬁnes system \_S2 state mode.
\_S3 Package that deﬁnes system \_S3 state mode.
\_S4 Package that deﬁnes system \_S4 state mode.
\_S5 Package that deﬁnes system \_S5 state mode.
\_TTS Control method used to prepare to sleep and run once awakened
\_WAK Control method run once awakened.
Note: Compatibility issue: The _BFS (Back From Sleep) and _GTS (Going To Sleep) methods were deprecated in
ACPI 5.0A.
7.4.1 \_PTS (Prepare To Sleep)
The _PTS control method is executed by the OS during the sleep transition process for S1, S2, S3, S4, and for orderly
S5 shutdown. The sleeping state value (For example, 1, 2, 3, 4 or 5 for the S5 soft-off state) is passed to the _PTS
control method. This method is called after OSPM has notiﬁed native device drivers of the sleep state transition and
before the OSPM has had a chance to fully prepare the system for a sleep state transition. Thus, this control method
can be executed a relatively long time before actually entering the desired sleeping state. If OSPM aborts the sleep
state transition, OSPM should run the _WAK method to indicate this condition to the platform.
Arg0 - An Integer containing the value of the sleeping state (1 for S1, 2 for S2, etc.)
None
The _PTS control method cannot modify the current conﬁguration or power state of any device in the system. For
example, _PTS would simply store the sleep type in the embedded controller in sequencing the system into a sleep
state when the SLP_EN bit is set.
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The platform must not make any assumptions about the state of the machine when _PTS is called. For example,
operation region accesses that require devices to be conﬁgured and enabled may not succeed, as these devices may be
in a non-decoding state due to plug and play or power management operations.
7.4.2 \_Sx (System States)
All system states supported by the system must provide a package containing the DWORD value of the following
format in the static Deﬁnition Block. The system states, known as S0-S5, are referenced in the namespace as \_S0-_S5
and for clarity the short Sx names are used unless speciﬁcally referring to the named \_Sx object. For each Sx state,
there is a deﬁned system behavior.
None
A Package containing an Integer containing register values for sleeping
Table 7.11: System State Package
Byte
1 0 Value for PM1a_CNT.SLP_TYP register to enter this system state. On HW-reduced plat-
forms, this is the HW-reduced Sleep Type value for SLEEP_CONTROL_REG.SLP_TYP.
1 1 Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any given state,
OSPM must write the PM1a_CNT.SLP_TYP register before the PM1b_CNT.SLP_TYP
register. On HW-reduced platforms, this value is ignored.
2 2 Reserved
States S1-S4 represent some system sleeping state. The S0 state is the system working state. Transition into the S0
state from some other system state (such as sleeping) is automatic, and, by virtue that instructions are being executed,
OSPM assumes the system to be in the S0 state. Transition into any system sleeping state is only accomplished by the
operating software directing the hardware to enter the appropriate state, and the operating software can only do this
within the requirements deﬁned in the Power Resource and Bus/Device Package objects.
All run-time system state transitions (for example, to and from the S0 state), except S4 and S5, are done similarly such
that the code sequence to do this is the following:
/*
*Intel Architecture SetSleepingState example
*/
ULONG
SetSystemSleeping (
IN ULONG NewState
)
{
PROCESSOR_CONTEXT Context;
ULONG PowerSeqeunce;
BOOLEAN FlushCaches;
USHORT SlpTyp;
// Required environment: Executing on the system boot
// processor. All other processors stopped. Interrupts
// disabled. All Power Resources ( anddevices) are in
// corresponding device state to support NewState.
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// Get h/w attributes forthis system state
FlushCaches = SleepType[NewState].FlushCache;
SlpTyp = SleepType[NewState].SlpTyp & SLP_TYP_MASK;
_asm {
lea eax, OsResumeContext
push eax ; Build real mode handler the resume
push offset sp50 ; context, witheip = sp50
call SaveProcessorState
mov eax, ResumeVector ; set firmware's resume vector
mov [eax], offset OsRealModeResumeCode
mov edx, PM1a_STS ; Make sure wake status isclear
mov ax, WAK_STS ; (cleared by asserting the bit
out dx, ax ; inthe status register)
mov edx, PM1b_STS ;
out dx, ax ;
and eax, notSLP_TYP_MASK
or eax, SlpTyp ; set SLP_TYP
or ax, SLP_EN ; set SLP_EN
cmp FlushCaches, 0
jz short sp10 ; If needed, ensure no dirty data in
call FlushProcessorCaches ; the caches whilesleeping
sp10: mov edx, PM1a_SLP_TYP ; get address forPM1a_SLP_TYP
out dx, ax ; start h/w sequencing
mov edx, PM1b_SLP_TYP ; get address forPM1b_SLP_TYP
mov edx, PM1a_STS ; get address forPM1x_STS
mov ecx, PM1b_STS
sp20: inax, dx ; wait forWAK status
xchg edx, ecx
test ax, WAK_STS
jz short sp20
sp50:
}
// Done..
*ResumeVector = NULL;
return0;
}
On HW-reduced ACPI platforms all run-time system state transitions (for example, to and from the S0 state) are done
similarly, but include the following instead of PM1*_BLK register bit manipulation:
After ensuring that any desired wake-capable interrupts are enabled, OSPM writes the HW-reduced Sleep Type value
to the Sleep Control Register and spins waiting for the WAK_STS bit of the Sleep Status Register to be set, indicating
a platform transition to the Working state.
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7.4.2.1 System \_S0 State (Working)
While the system is in the S0 state, it is in the system working state. The behavior of this state is deﬁned as:
• The processors are either running, or in a C-state, or in an LPI state. The processor-complex context is main-
tained and instructions are executed as deﬁned by any of these processor states.
• Dynamic RAM context is maintained and is read/write by the processors.
• Devices states are individually managed by the operating software and can be in any device state (D0, D1, D2,
D3hot, or D3).
• Power Resources are in a state compatible with the current device states.
Transition into the S0 state from some system sleeping state is automatic, and by virtue that instructions are being

executed OSPM, assumes the system to be in the S0 state.
7.4.2.2 System \_S1 State (Sleeping with Processor Context Maintained)
While the system is in the S1 sleeping state, its behavior is the following:
• The processors are not executing instructions. The processor-complex context is maintained.
• Dynamic RAM context is maintained.
• Power Resources are in a state compatible with the system S1 state. All Power Resources that supply a System-
Level reference of S0 are in the OFF state.
• Devices states are compatible with the current Power Resource states. Only devices that solely reference Power
Resources that are in the ON state for a given device state can be in that device state. In all other cases, the
device is in the D3 (off) state. (Or it is at least assumed to be in the D3 state by its device driver. For example,
if the device doesn’t explicitly describe how it can stay in some non-off state while the system is in a sleeping
state, the operating software must assume that the device can lose its power and state.)
• Devices that are enabled to wake the system and that can do so from their current device state can initiate a
hardware event that transitions the system state to S0. This transition causes the processor to continue execution
where it left off.
To transition into the S1 state, the OSPM must ﬂush all processor caches.
7.4.2.3 System \_S2 State
The S2 sleeping state is logically deeper than the S1 state and is assumed to conserve more power. The behavior of
this state is deﬁned as:
• The processors are not executing instructions. The processor-complex context is not maintained.
• Power Resources are in a state compatible with the system S2 state. All Power Resources that supply a System-
Level reference of S0 or S1 are in the OFF state.
device is in the D3 (off) state.
hardware event that transitions the system state to S0. This transition causes the processor to begin execution at
its boot location. The platform runtime ﬁrmware performs initialization of core functions as needed to exit an
S2 state and passes control to the ﬁrmware resume vector. See Platform Boot Firmware Initialization of Memory
for more details on platform ﬁrmware initialization.
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Because the processor context can be lost while in the S2 state, the transition to the S2 state requires that the operating
software ﬂush all dirty cache to dynamic RAM (DRAM).
7.4.2.4 System \_S3 State
The S3 state is logically deeper than the S2 state and is assumed to conserve more power. The behavior of this state is
deﬁned as follows:
• Power Resources are in a state compatible with the system S3 state. All Power Resources that supply a System-
Level reference of S0, S1, or S2 are in the OFF state.
its boot location. The platform runtime ﬁrmware performs initialization of core functions as necessary to exit an
S3 state and passes control to the ﬁrmware resume vector. See Platform Boot Firmware Initialization of Memory
From the software viewpoint, this state is functionally the same as the S2 state. The operational difference can be that
some Power Resources that could be left ON to be in the S2 state might not be available to the S3 state. As such,
additional devices may need to be in a deeper state for S3 than S2. Similarly, some device wake events can function
in S2 but not S3.
Because the processor context can be lost while in the S3 state, the transition to the S3 state requires that the operating
software ﬂush all dirty cache to DRAM.
7.4.2.5 System \_S4 State
While the system is in this state, it is in the system S4 sleeping state. The state is logically deeper than the S3 state
and is assumed to conserve more power. The behavior of this state is deﬁned as follows:
• DRAM context is not maintained.
• Power Resources are in a state compatible with the system S4 state. All Power Resources that supply a System-
Level reference of S0, S1, S2, or S3 are in the OFF state.
• Devices states are compatible with the current Power Resource states. In other words, all devices are in the D3
state when the system state is S4.
• Devices that are enabled to wake the system and that can do so from their device state in S4 can initiate a
its boot location.
After OSPM has executed the _PTS control method and has put the entire system state into main memory, there are
two ways that OSPM may handle the next phase of the S4 state transition; saving and restoring main memory. The ﬁrst
way is to use the operating system’s drivers to access the disks and ﬁle system structures to save a copy of memory
to disk and then initiate the hardware S4 sequence by setting the SLP_EN register bit. When the system wakes, the
ﬁrmware performs a normal boot process and transfers control to the OS via the ﬁrmware_waking_vector loader. The
OS then restores the system’s memory and resumes execution.
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The alternate method for entering the S4 state is to utilize the platform runtime ﬁrmware via the S4BIOS transition.
The platform runtime ﬁrmware uses ﬁrmware to save a copy of memory to disk and then initiates the hardware S4
sequence. When the system wakes, the ﬁrmware restores memory from disk and wakes OSPM by transferring control
to the FACS waking vector.
The S4BIOS transition is optional, but any system that supports this mechanism must support entering the S4 state
via the direct OS mechanism. Thus the preferred mechanism for S4 support is the direct OS mechanism as it provides
broader platform support. The alternate S4BIOS transition provides a way to achieve S4 support on operating systems
that do not have support for the direct method.
7.4.2.6 System \_S5 State (Soft Off)
The S5 state is similar to the S4 state except that OSPM does not save any context. The system is in the soft off
state and requires a complete boot when awakened (platform boot ﬁrmware and OS). Software uses a different state
value to distinguish between this state and the S4 state to allow for initial boot operations within the platform boot
ﬁrmware to distinguish whether or not the boot is going to wake from a saved memory image. OSPM does not
disable wake events before setting the SLP_EN bit when entering the S5 system state. This provides support for
remote management initiatives by enabling Remote Start capability. An ACPI-compliant OS must provide an end user
accessible mechanism for disabling all wake devices, with the exception of the system power button, from a single
point in the user interface.
7.4.3 \_SWS (System Wake Source)
This object provides a means for OSPM to deﬁnitively determine the source of an event that caused the system to enter
the S0 state. General-purpose event and ﬁxed-feature hardware registers containing wake event sources information
are insufﬁcient for this purpose as the source event information may not be available after transitions to the S0 state
from all other system states (S1-S5).
To determine the source event that caused the system to transition to the S0 state, OSPM will evaluate the _SWS
object, when it exists, under the \_GPE scope (for all ﬁxed-feature general-purpose events from the GPE Blocks),
under the \_SB scope (for ﬁxed-feature hardware events), and within the scope of a GPE Block device (for GPE events
from this device). _SWS objects may exist in any or all of these locations as necessary for the platform to determine
the source event that caused the system to transition to the S0 state.
None
An Integer containing the Source Event as described below
The value of the Source Event is dependent on the location of the _SWS object:

None
1. If _SWS is evaluated under the \_GPE scope, Source Event is the index of the GPE that caused the system to
transition to S0. StepNumList-1 If _SWS is evaluated under the \_GPE scope, Source Event is the index of the
GPE that caused the system to transition to S0.
2. If _SWS is evaluated within the scope of a GPE block device, Source Event is the index of the GPE that caused
the system to transition to S0. In this case, the index is relative to the GPE block device and is not unique
system-wide.
3. If _SWS is evaluated under the \_SB scope, Source Event is the the index in the PM1 status register that caused
the system to transition to S0.
In all cases above, if the cause of the S0 transition cannot be determined, _SWS returns Ones (-1).
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To enable OSPM to determine the source of the S0 state transition via the _SWS object,the hardware or ﬁrmware
should detect and save the event that caused the transition so that it can be returned during _SWS object evaluation.
The single wake source for the system may be latched in hardware during the transition so that no false wake events
can be returned by _SWS. An implementation that does not use hardware to latch a single wake source for the system
and instead uses ﬁrmware to save the wake source must do so as quickly as possible after the wakeup event occurs, so
that _SWS does not return values that correspond to events that occurred after the sleep-to-wake transition. Such an
implementation must also take care to ensure that events that occur subsequent to the wakeup source being saved do
not overwrite the original wakeup source.
The source event data returned by _SWS must be determined for each transition into the S0 state. The value returned
by _SWS must also be persistent during the system’s residency in the S0 state as OSPM may evaluate _SWS multiple
times. In this case, the platform must return the same source event information for each invocation.
After evaluating an _SWS object within the \_GPE scope or within the scope of a GPE block device, OSPM will invoke
the _Wxx control method corresponding to the GPE index returned by _SWS if it exists. This allows the platform to
further determine source event if the GPE is shared among multiple devices. See Determining the System Wake Source
Using _Wxx Control Methods for details.
7.4.4 \_TTS (Transition To State)
The _TTS control method is executed by the OSPM at the beginning of the sleep transition process for S1, S2, S3, S4,
and orderly S5 shutdown. OSPM will invoke _TTS before it has notiﬁed any native mode device drivers of the sleep
state transition. The sleeping state value (For example, 1, 2, 3, 4 or 5 for the S5 soft-off state) is passed to the _TTS
control method.
The _TTS control method is also executed by the OSPM at the end of any sleep transition process when the system
transitions to S0 from S1, S2, S3, or S4. OSPM will invoke _TTS after it has notiﬁed any native mode device drivers
of the end of the sleep state transition. The working state value (0) is passed to the _TTS control method.
None
If OSPM aborts the sleep transition process, OSPM will still run _TTS for an S0 transition to indicate the OSPM has
returned to the S0 state. The platform must assume that if OSPM invokes the _TTS control method for an S1, S2, S3,
or S4 transition, that OSPM will invoke _TTS control method for an S0 transition before returning to the S0 state.
The platform must not make any assumptions about the state of the machine when _TTS is called. For example,
7.4.5 \_WAK (System Wake)
After the system wakes from a sleeping state, it will invoke the \_WAK method and pass the sleeping state value
that has ended. This operation occurs asynchronously with other driver notiﬁcations in the system and is not the ﬁrst
action to be taken when the system wakes. The AML code for this control method issues device, thermal, and other
notiﬁcations to ensure that OSPM checks the state of devices, thermal zones, and so on, that could not be maintained
during the system sleeping state. For example, if the system cannot determine whether a device was inserted or
removed from a bus while in the S2 state, the _WAK method would issue a devicecheck type of notiﬁcation for that
bus when issued with the sleeping state value of 2 (for more information about types of notiﬁcations, see Device Object
Notiﬁcations .
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Notice that a device check notiﬁcation from the _SB node will cause OSPM to re-enumerate the entire tree. Only
buses that support hardware-deﬁned enumeration methods are done automatically at run-time. This would include
ACPI-enumerated devices.
Hardware is not obligated to track the state needed to supply the resulting status; however, this method must return
status concerning the last sleep operation initiated by OSPM. The return values can be used to provide additional
information to OSPM or user.
Return value:
A Package containing two Integers containing status and the power supply S-state
_WAK returns a package with the following format:
Element 0 - An Integer containing a bitﬁeld that represents conditions that occurred during sleep:
• 0x00000000 - Wake was signaled and was successful
• 0x00000001 - Wake was signaled but failed due to lack of power
• 0x00000002 - Wake was signaled but failed due to thermal condition
• Other values - Reserved
Element 1 - An Integer containing the power supply S-state:
If non-zero, this is the effective S-state the power supply that was actually entered. This value is used
to detect when the targeted S-state was not entered because of too much current being drawn from the
power supply. For example, this might occur when some active device’s current consumption pushes the
system’s power requirements over the low power supply mark, thus preventing the deeper system sleeping
state from being entered as desired.
7.5 OSPM usage of _PTS, _TTS, and _WAK
OSPM will invoke _PTS, _TTS,and _WAK in the following order:
1. OSPM decides (through a policy scheme) to place the system into a sleeping state StepNumList-1 OSPM decides
(through a policy scheme) to place the system into a sleeping state
2. _TTS(Sx) is run, where Sx is the desired sleep state to enter
3. OSPM notiﬁes all native device drivers of the sleep state transition
4. _PTS is run
5. OSPM readies system for the sleep state transition
6. OSPM writes the sleep vector and the system enters the speciﬁed Sx sleep state
7. System Wakes up
8. OSPM readies system for the return from the sleep state transition
9. _WAK is run
10. OSPM notiﬁes all native device drivers of the return from the sleep state transition
11. _TTS(0) is run to indicate the return to the S0 state
7.5. OSPM usage of _PTS, _TTS, and _WAK 471Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 7.1: Working / Sleeping State object evaluation ﬂow
7.5. OSPM usage of _PTS, _TTS, and _WAK 472CHAPTER
EIGHT
PROCESSOR CONFIGURATION AND CONTROL
This section describes the conﬁguration and control of the processor’s power and performance states. The major
controls over the processors are:
• Processor power states: C0, C1, C2, C3, . . . Cn
• Processor clock throttling
• Processor performance states: P0, P1, . . . Pn
These controls are used in combination by OSPM to achieve the desired balance of the following sometimes conﬂicting
goals:
• Performance
• Power consumption and battery life
• Thermal requirements
• Noise-level requirements
Because the goals interact with each other, the operating software needs to implement a policy as to when and where
tradeoffs between the goals are to be made (see note below). For example the operating software would determine
when the audible noise of the fan is undesirable and would trade off that requirement for lower thermal requirements,
which can lead to lower processing performance. Each processor conﬁguration and control interface is discussed in
the following sections along with how controls interacts with the various goals.
Note: A thermal warning leaves room for operating system tradeoffs (to start the fan or reduce performance), without
issuing a critical thermal alert.
8.1 Processor Power States
ACPI deﬁnes the power state of system processors while in the G0 working state as being either active executing or

goals:
sleeping (not executing) - see note below. Processor power states include are designated C0, C1, C2, C3, . . . Cn. The
C0 power state is an active power state where the CPU executes instructions. The C1 through Cn power states are
processor sleeping states where the processor consumes less power and dissipates less heat than leaving the processor
in the C0 state. While in a sleeping state, the processor does not execute any instructions. Each processor sleeping
state has a latency associated with entering and exiting that corresponds to the power savings. In general, the longer the
entry/exit latency, the greater the power savings when in the state. To conserve power, OSPM places the processor into
one of its supported sleeping states when idle. While in the C0 state, ACPI allows the performance of the processor to
be altered through a deﬁned “throttling” process and through transitions into multiple performance states (P-states). A
diagram of processor power states is provided below.
473Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Note: These CPU states map into the G0 working state, and the Cx states only apply to the G0 state. In the G3
sleeping state, the state of the CPU is undeﬁned.
Fig. 8.1: Processor Power States
ACPI deﬁnes logic on a per-CPU basis that OSPM uses to transition between the different processor power states.
This logic is optional, and is described through the FADT table and processor objects (contained in the hierarchical
namespace). The ﬁelds and ﬂags within the FADT table describe the symmetrical features of the hardware, and the
processor object contains the location for the particular CPU’s clock logic (described by the P_BLK register block and
_CST objects).
The P_LVL2 and P_LVL3 registers provide optional support for placing the system processors into the C2 or C3 states.
The P_LVL2 register is used to sequence the selected processor into the C2 state, and the P_LVL3 register is used to
sequence the selected processor into the C3 state. Additional support for the C3 state is provided through the bus
master status and arbiter disable bits (BM_STS in the PM1_STS register and ARB_DIS in the PM2_CNT register).
System software reads the P_LVL2 or P_LVL3 registers to enter the C2 or C3 power state. The Hardware must put the
processor into the proper clock state precisely on the read operation to the appropriate P_LVLx register. The platform
may alternatively deﬁne interfaces allowing OSPM to enter C-states using the _CST object, which is deﬁned in _CST
(C States) .
Processor power state support is symmetric when presented via the FADT and P_BLK interfaces; OSPM assumes all
processors in a system support the same power states. If processors have non-symmetric power state support, then the
8.1. Processor Power States 474Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
platform runtime ﬁrmware will choose and use the lowest common power states supported by all the processors in the
system through the FADT table. For example, if the CPU0 processor supports all power states up to and including the
C3 state, but the CPU1 processor only supports the C1 power state, then OSPM will only place idle processors into
the C1 power state (CPU0 will never be put into the C2 or C3 power states). Notice that the C1 power state must be
supported. The C2 and C3 power states are optional (see the PROC_C1 ﬂag in the FADT table description in System
Description Table Header ).
The following sections describe processor power states in detail.
8.1.1 Processor Power State C0
While the processor is in the C0 power state, it executes instructions. While in the C0 power state, OSPM can generate
a policy to run the processor at less than maximum performance. The clock throttling mechanism provides OSPM
with the functionality to perform this task in addition to thermal control. The mechanism allows OSPM to program a
value into a register that reduces the processor’s performance to a percentage of maximum performance.
Fig. 8.2: Throttling Example
The FADT contains the duty offset and duty width values. The duty offset value determines the offset within the
P_CNT register of the duty value. The duty width value determines the number of bits used by the duty value (which
determines the granularity of the throttling logic). The performance of the processor by the clock logic can be ex-
pressed with the following equation:
Fig. 8.3: Equation 1 Duty Cycle Equation
Nominal performance is deﬁned as “close as possible, but not below the indicated performance level.” OSPM will
use the duty offset and duty width to determine how to access the duty setting ﬁeld. OSPM will then program the
duty setting based on the thermal condition and desired power of the processor object. OSPM calculates the nom-
inal performance of the processor using the equation expressed in Equation 1. Notice that a dutysetting of zero is
reserved.For example, the clock logic could use the stop grant cycle to emulate a divided processor clock frequency
on an IA processor (through the use of the STPCLK# signal). This signal internally stops the processor’s clock when
asserted LOW. To implement logic that provides eight levels of clock control, the STPCLK# pin could be asserted as
follows (to emulate the different frequency settings):
8.1. Processor Power States 475Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 8.4: Example Control for the STPCLK
To start the throttling logic OSPM sets the desired duty setting and then sets the THT_EN bit HIGH. To change the
duty setting, OSPM will ﬁrst reset the THT_EN bit LOW, then write another value to the duty setting ﬁeld while
preserving the other unused ﬁelds of this register, and then set the THT_EN bit HIGH again.
The example logic model is shown below:
Implementation of the ACPI processor power state controls minimally requires the support a single CPU sleeping state
(C1). All of the CPU power states occur in the G0/S0 system state; they have no meaning when the system transitions
into the sleeping state(S1-S4). ACPI deﬁnes the attributes (semantics) of the different CPU states (deﬁnes four of
them). It is up to the platform implementation to map an appropriate low-power CPU state to the deﬁned ACPI CPU
state.
ACPI clock control is supported through the optional processor register block (P_BLK). ACPI requires that there be
a unique processor register block for each CPU in the system. Additionally, ACPI requires that the clock logic for
multiprocessor systems be symmetrical when using the P_BLK and FADT interfaces; if the P0 processor supports the
C1, C2, and C3 states, but P1 only supports the C1 state, then OSPM will limit all processors to enter the C1 state
when idle.
The following sections deﬁne the different ACPI CPU sleeping states.
8.1.2 Processor Power State C1
All processors must support this power state. This state is supported through a native instruction of the processor (HLT
for IA 32-bit processors), and assumes no hardware support is needed from the chipset. The hardware latency of this
state must be low enough that OSPM does not consider the latency aspect of the state when deciding whether to use
it. Aside from putting the processor in a power state, this state has no other software-visible effects. In the C1 power
state, the processor is able to maintain the context of the system caches.
The hardware can exit this state for any reason, but must always exit this state when an interrupt is to be presented to
the processor.
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Fig. 8.5: ACPI Clock Logic (One per Processor)
8.1.3 Processor Power State C2
This processor power state is optionally supported by the system. If present, the state offers improved power savings
over the C1 state and is entered by using the P_LVL2 command register for the local processor or an alternative
mechanism as indicated by the _CST object. The worst-case hardware latency for this state is declared in the FADT
and OSPM can use this information to determine when the C1 state should be used instead of the C2 state. Aside from
putting the processor in a power state, this state has no other software-visible effects. OSPM assumes the C2 power
state has lower power and higher exit latency than the C1 power state.
The C2 power state is an optional ACPI clock state that needs chipset hardware support. This clock logic consists
of an interface that can be manipulated to cause the processor complex to precisely transition into a C2 power state.
In a C2 power state, the processor is assumed capable of keeping its caches coherent; for example, bus master and
multiprocessor activity can take place without corrupting cache context.
The C2 state puts the processor into a low-power state optimized around multiprocessor and bus master systems.
OSPM will cause an idle processor complex to enter a C2 state if there are bus masters or Multiple processor activity

(which will prevent OSPM from placing the processor complex into the C3 state). The processor complex is able to
snoop bus master or multiprocessor CPU accesses to memory while in the C2 state.
The hardware can exit this state for any reason, but must always exit this state whenever an interrupt is to be presented
to the processor.
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8.1.4 Processor Power State C3
over the C1 and C2 state and is entered by using the P_LVL3 command register for the local processor or an alternative
mechanism as indicated by the _CST object. The worst-case hardware latency for this state is declared in the FADT,
and OSPM can use this information to determine when the C1 or C2 state should be used instead of the C3 state.
While in the C3 state, the processor’s caches maintain state but the processor is not required to snoop bus master or
multiprocessor CPU accesses to memory.
the processor or when BM_RLD is set and a bus master is attempting to gain access to memory.
OSPM is responsible for ensuring that the caches maintain coherency. In a uniprocessor environment, this can be done
by using the PM2_CNT.ARB_DIS bus master arbitration disable register to ensure bus master cycles do not occur
while in the C3 state. In a multiprocessor environment, the processors’ caches can be ﬂushed and invalidated such that
no dynamic information remains in the caches before entering the C3 state.
There are two mechanisms for supporting the C3 power state:
• Having OSPM ﬂush and invalidate the caches prior to entering the C3 state.
• Providing hardware mechanisms to prevent masters from writing to memory (uniprocessor-only support).
In the ﬁrst case, OSPM will ﬂush the system caches prior to entering the C3 state. As there is normally much latency
associated with ﬂushing processor caches, OSPM is likely to only support this in multiprocessor platforms for idle
processors. Flushing of the cache is accomplished through one of the deﬁned ACPI mechanisms (described below in
Flushing Caches ).
In uniprocessor-only platforms that provide the needed hardware functionality (deﬁned in this section), OSPM will
attempt to place the platform into a mode that will prevent system bus masters from writing into memory while the
processor is in the C3 state. This is accomplished by disabling bus masters prior to entering a C3 power state. Upon a
bus master requesting an access, the CPU will awaken from the C3 state and re-enable bus master accesses.
OSPM uses the BM_STS bit to determine the power state to enter when considering a transition to or from the C2/C3
power state. The BM_STS is an optional bit that indicates when bus masters are active. OSPM uses this bit to
determine the policy between the C2 and C3 power states: a lot of bus master activity demotes the CPU power state
to the C2 (or C1 if C2 is not supported), no bus master activity promotes the CPU power state to the C3 power state.
OSPM keeps a running history of the BM_STS bit to determine CPU power state policy.
The last hardware feature used in the C3 power state is the BM_RLD bit. This bit determines if the Cx power state
is exited as a result of bus master requests. If set, then the Cx power state is exited upon a request from a bus master.
If reset, the power state is not exited upon bus master requests. In the C3 state, bus master requests need to transition
the CPU back to the C0 state (as the system is capable of maintaining cache coherency), but such a transition is not
needed for the C2 state. OSPM can optionally set this bit when using a C3 power state, and clear it when using a C1
or C2 power state.
8.1.5 Additional Processor Power States
ACPI introduced optional processor power states beyond C3 starting in ACPI 2.0. These power states, C4. . . Cn, are
conveyed to OSPM through the _CST object deﬁned in _CST (C States) These additional power states are characterized
by equivalent operational semantics to the C1 through C3 power states, as deﬁned in the previous sections, but with
different entry/exit latencies and power savings. See _CST (C States) for more information.
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8.2 Flushing Caches
To support the C3 power state without using the ARB_DIS feature, the hardware must provide functionality to ﬂush
and invalidate the processors’ caches (for an IA processor, this would be the WBINVD instruction). To support the
S1, S2 or S3 sleeping states, the hardware must provide functionality to ﬂush the platform caches. Flushing of caches
is supported by one of the following mechanisms:
• Processor instruction to write back and invalidate system caches (WBINVD instruction for IA processors).
• Processor instruction to write back but not invalidate system caches (WBINVD instruction for IA processors
and some chipsets with partial support; that is, they don’t invalidate the caches).
The ACPI speciﬁcation expects all platforms to support the local CPU instruction for ﬂushing system caches (with
support in both the CPU and chipset), and provides some limited “best effort” support for systems that don’t currently
meet this capability. The method used by the platform is indicated through the appropriate FADT ﬁelds and ﬂags
indicated in this section.
ACPI speciﬁes parameters in the FADT that describe the system’s cache capabilities. If the platform properly supports
the processor’s write back and invalidate instruction (WBINVD for IA processors), then this support is indicated to
OSPM by setting the WBINVD ﬂag in the FADT.
If the platform supports neither of the ﬁrst two ﬂushing options, then OSPM can attempt to manually ﬂush the cache
if it meets the following criteria:
• A cache-enabled sequential read of contiguous physical memory of not more than 2 MB will ﬂush the platform
caches.
• There are two additional FADT ﬁelds needed to support manual ﬂushing of the caches:
• FLUSH_SIZE, typically twice the size of the largest cache in the system.
• FLUSH_STRIDE, typically the smallest cache line size in the system.
8.3 Power, Performance, and Throttling State Dependencies
Cost and complexity trade-off considerations have driven into the platform control dependencies between logical
processors when entering power, performance, and throttling states. These dependencies exist in various forms in
multi-processor, multi-threaded processor, and multi-core processor-based platforms. These dependencies may also
be hierarchical. For example, a multi-processor system consisting of processors containing multiple cores containing
multiple threads may have various dependencies as a result of the hardware implementation.
Unless OSPM is aware of the dependency between the logical processors, it might lead to scenarios where one logical
processor is implicitly transitioned to a power, performance, or throttling state when it is unwarranted, leading to
incorrect / non-optimal system behavior. Given knowledge of the dependencies, OSPM can coordinate the transitions
between logical processors, choosing to initiate the transition when doing so does not lead to incorrect or non-optimal
system behavior. This OSPM coordination is referred to as Software (SW) Coordination. Alternately, it might be
possible for the underlying hardware to coordinate the state transition requests on multiple logical processors, causing
the processors to transition to the target state when the transition is guaranteed to not lead to incorrect or non-optimal
system behavior. This scenario is referred to as Hardware (HW) coordination. When hardware coordinates transitions,
OSPM continues to initiate state transitions as it would if there were no dependencies. However, in this case it is
required that hardware provide OSPM with a means to determine actual state residency so that correct / optimal
control policy can be realized.
Platforms containing logical processors with cross-processor dependencies in the power, performance, or throttling
state control areas use ACPI deﬁned interfaces to group logical processors into what is referred to as a dependency
domain. The Coordination Type characteristic for a domain speciﬁes whether OSPM or underlying hardware is re-
sponsible for the coordination. When OSPM coordinates, the platform may require that OSPM transition ALL (0xFC)
8.2. Flushing Caches 479Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
or ANY ONE (0xFD) of the processors belonging to the domain into a particular target state. OSPM may choose at its
discretion to perform coordination even though the underlying hardware supports hardware coordination. In this case,

OSPM must transition all logical processors in the dependency domain to the particular target state.
Table 8.1: C-state/T-state/P-state Coordination Types
0xFC SW_ALL: The OSPM coordinates the state for all processors in the domain by making the same
state request on the control interface of each processor in the domain. ALL refers to the require-
ment that all processors in the domain must agree on the requested state for the domain to enter
that state.
0xFD SW_ANY: The OSPM coordinates the state for all processors in the domain by making a state
request on the control interface of only one processor in the domain. ANY refers to the hard-
ware requirement for all processors in the domain to transition to the last requested state on any
processor in the domain.
0xFE HW_ALL: As the OSPM requests a state transition on the control interface of any processor in
the domain, hardware coordinates the state for all processors in the domain and transitions all
processors in the domain to the coordinated state. ALL refers to the requirement for hardware
maintaining coordination as OPSM makes independent state requests on any processor in the
domain. Unlike SW_ALL, OSPM can make different state requests for processors in the do-
main, while hardware determines the resulting state for all processors in the domain. Note: The
hardware coordination policy is implementation-deﬁned.
There are no dependencies implied between a processor’s C-states, P-states or T-states. Hence, for example it is
possible to use the same dependency domain number for specifying dependencies between P-states among one set of
processors and C-states among another set of processors without any dependencies being implied between the P-State
transitions on a processor in the ﬁrst set and C-state transitions on a processor in the second set.
8.4 Declaring Processors
Each processor in the system must be declared in the ACPI namespace in the \_SB scope. A Device deﬁnition for a
processor is declared using the ACPI0007 hardware identiﬁer (HID). Processor conﬁguration information is provided
exclusively by objects in the processor device’s object list.
When the platform uses the APIC interrupt model, UID object values under a processor device are used to associate
processor devices with entries in the MADT.
Processor-speciﬁc objects may be declared within the processor device’s scope. These objects serve multiple purposes
including processor performance state control. Other ACPI-deﬁned device-related objects are also allowed under the
processor device’s scope (for example, the unique identiﬁer object _UID mentioned above).
With device-like characteristics attributed to processors, it is implied that a processor device driver will be loaded by
OSPM to, at a minimum, process device notiﬁcations. OSPM will enumerate processors in the system using the ACPI
Namespace, processor-speciﬁc native identiﬁcation instructions, and the _HID method.
For more information on the declaration of the processor device object, see Device (Declare Device Package) .
Processor-speciﬁc child objects are described in the following sections.
ACPI 6.0 introduces the notion of processor containers. Processor containers are declared using the Processor Con-
tainer Device . A processor container can be used to describe a collection of associated processors that share common
resources, such as shared caches, and which have power states that affect the processors in the collection. For more
information see Processor Container Device .
8.4. Declaring Processors 480Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
8.4.1 Processor Power State Control
ACPI deﬁnes multiple processor power state (C state) control interfaces. These are:
1. The Processor Register Block’s (P_BLK’s) P_LVL2 and P_LVL3 registers coupled with FADT P_LVLx_LAT
values and
2. The _CST object in the processor’s object list.
3. The _LPI objects for processors and processor containers.
P_BLK based C state controls are described in ACPI Hardware Speciﬁcation . _CST based C state controls expand the
functionality of the P_BLK based controls allowing the number and type of C states to be dynamic and accommodate
CPU architecture speciﬁc C state entry and exit mechanisms as indicated by registers deﬁned using the Functional
Fixed Hardware address space.
_CST is an optional object that provides:
• The Processor Register Block’s (P_BLK’s) P_LVL2 and P_LVL3 registers coupled with FADT P_LVLx_LAT
values.
• The _CST object in the processor’s object list.
ACPI 6.0 introduces _LPI, the low power idle state object. _LPI provides more detailed power state information and
can describe idle states at multiple levels of hierarchy in conjunction with Processor Containers. See _LPI (Low Power
Idle States) for details.
8.4.1.1 _CST (C States)
_CST is an optional object that provides an alternative method to declare the supported processor power states (C
States). Values provided by the _CST object override P_LVLx values in P_BLK and P_LVLx_LAT values in the
FADT. The _CST object allows the number of processor power states to be expanded beyond C1, C2, and C3 to an
arbitrary number of power states. The entry semantics for these expanded states, (in other words), the considerations
for entering these states, are conveyed to OSPM by the C state Type ﬁeld and correspond to the entry semantics for
C1 C2 and C3 as described in Section 8.1.2 through Section 8.1.4. _CST deﬁnes ascending C-states characterized by
lower power and higher entry/exit latency.
None
A variable-length Package containing a list of C-state information Packages as described below
_CST returns a variable-length Package that contains the following elements:
• Count An Integer that contains the number of CState sub-packages that follow
• CStates[] A list of Count CState sub-packages
Package {
Count // Integer
CStates[0] // Package
...
CStates[Count-1] // Package
}
Each ﬁxed-length Cstate sub-Package contains the elements described below:
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Package {
Register // Buffer (Resource Descriptor)
Type // Integer (BYTE)
Latency // Integer (WORD)
Power // Integer (DWORD)
}
Table 8.2: Cstate Package Values
Register Buffer Contains a Resource Descriptor with a single Register() descriptor that de-
scribes the register that OSPM must read to place the processor in the corre-
sponding C state.
Type Integer (BYTE) The C State type (1=C1, 2=C2, 3=C3). This ﬁeld conveys the semantics to be
used by OSPM when entering/exiting the C state. Zero is not a valid value.
Latency Integer (WORD) The worst-case latency to enter and exit the C State (in microseconds). There
are no latency restrictions.
Power Integer (DWORD) The average power consumption of the processor when in the corresponding C
State (in milliwatts).
The platform must expose a _CST object for either all or none of its processors. If the _CST object exists, OSPM uses
the C state information speciﬁed in the _CST object in lieu of P_LVL2 and P_LVL3 registers deﬁned in P_BLK and
the P_LVLx_LAT values deﬁned in the FADT. Also notice that if the _CST object exists and the _PTC object does
not exist, OSPM will use the Processor Control Register deﬁned in P_BLK and the C_State_Register registers in the
_CST object.
The platform may change the number or type of C States available for OSPM use dynamically by issuing a Notify
event on the processor object with a notiﬁcation value of 0x81. This will cause OSPM to re-evaluate any _CST
object residing under the processor object notiﬁed. For example, the platform might notify OSPM that the number of
supported C States has changed as a result of an asynchronous AC insertion / removal event.
The platform must specify unique C_State_Register addresses for all entries within a given _CST object.
_CST eliminates the ACPI 1.0 restriction that all processors must have C State parity. With _CST, each processor can
have its own characteristics independent of other processors. For example, processor 0 can support C1, C2 and C3,
while processor 1 supports only C1.
The ﬁelds in the processor structure remain for backward compatibility.
Example
Processor (
\_SB.CPU0, // Processor Name
1, // ACPI Processor number
0x120, // PBlk system IO address
6 // PBlkLen
)
{
Name(_CST, Package()
{
4, // There are four C-states defined here withthree semantics
// The third andfourth C-states defined have the same C3 entry semantics
Package(){ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, 1, 20, 1000},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x161)}, 2, 40, 750},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x162)}, 3, 60, 500},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x163)}, 3, 100, 250}
}
8.4. Declaring Processors 482Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
)
}

Example
)
{
{
}
)
}
Notice in the example above that OSPM should anticipate the possibility of a _CST object providing more than one
entry with the same C_State_Type value. In this case OSPM must decide which C_State_Register it will use to enter
that C state.
Example
This is an example usage of the _CST object using the typical values as deﬁned in ACPI 1.0.
\\_SB.CPU0, // Processor Name
0x120, // PBLK system IO address
6 ) // PBLK Len
{
{
2, // There are two C-states defined here - C2 andC3
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x124)}, 2, 2, 750},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x125)}, 3, 65, 500}
})
}
The platform will issue a Notify (_SB.CPU0, 0x81) to inform OSPM to re-evaluate this object when the number of
available processor power states changes.
8.4.1.2 _CSD (C-State Dependency)
This optional object provides C-state control cross logical processor dependency information to OSPM. The _CSD
object evaluates to a packaged list of information that correlates with the C-state information returned by the _CST
object. Each packaged list entry identiﬁes the C-state for which the dependency is being speciﬁed (as an index into the
_CST object list), a dependency domain number for that C-state, the coordination type for that C-state and the number
of logical processors belonging to the domain for the particular C-state. It is possible that a particular C-state may
belong to multiple domains. That is, it is possible to have multiple entries in the _CSD list with the same CStateIndex
value.
None
A variable-length Package containing a list of C-state dependency Packages as described below.
Package {
CStateDependency[0] // Package
...
CStateDependency[n] // Package
}
Each CstateDependency sub-Package contains the elements described below:
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Package {
NumEntries // Integer
Revision // Integer (BYTE)
Domain // Integer (DWORD)
CoordType // Integer (DWORD)
NumProcessors // Integer (DWORD)
Index // Integer (DWORD)
}
Table 8.3: C-State Dependency Package Values
NumEntries Integer The number of entries in the CStateDependency package including this ﬁeld.
Current value is 6.
Revision Integer
(BYTE)The revision number of the CStateDependency package format. Current value
is 0.
Domain Integer
(DWORD)The dependency domain number to which this C state entry belongs.
CoordType Integer
(DWORD)See Table 8.1 for supported C-state coordination types.
Num Proces-
sorsInteger
(DWORD)The number of processors belonging to the domain for the particular C-state.
OSPM will not start performing power state transitions to a particular C-state
until this number of processors belonging to the same domain for the particular
C-state have been detected and started.
Index Integer
(DWORD)Indicates the index of the C-State entry in the _CST object for which the depen-
dency applies.
Given that the number or type of available C States may change dynamically, ACPI supports Notify events on the
processor object, with Notify events of type 0x81 causing OSPM to re-evaluate any _CST objects residing under the
particular processor object notiﬁed. On receipt of Notify events of type 0x81, OSPM should re-evaluate any present
_CSD objects also.
Example
This is an example usage of the _CSD structure in a Processor structure in the namespace. The example represents a
two processor conﬁguration. The C1-type state can be independently entered on each processor. For the C2-type state,
there exists dependence between the two processors, such that one processor transitioning to the C2-type state, causes
the other processor to transition to the C2-type state. A similar dependence exists for the C3-type state. OSPM will be
required to coordinate the C2 and C3 transitions between the two processors. Also OSPM can initiate a transition on
either processor to cause both to transition to the common target C-state.
6 ) // PBlkLen
{
Name (_CST, Package()
{
3, // There are three C-states defined here with
˓→three semantics
Package(){ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, 1, 20,1000},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x162)}, 3, 60, 500}
})
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Name(_CSD, Package()
{
Package(){6, 0, 0, 0xFD, 2, 1} , // 6 entries,Revision 0,Domain 0,OSPM Coordinate
// Initiate on Any Proc,2 Procs, Index 1 (C2-type)
Package(){6, 0, 0, 0xFD, 2, 2} // 6 entries,Revision 0 Domain 0,OSPM Coordinate
// Initiate on Any Proc,2 Procs, Index 2 (C3-type)
})
}
\_SB.CPU1, // Processor Name
2, // ACPI Processor number
, // PBlk system IO address
) // PBlkLen
{
{
3, // There are three C-states defined here withthree semantics
})
{
Package(){6, 0, 0, 0xFD, 2, 1}, // 6 entries,Revision 0,Domain 0,OSPM Coordinate
// Initiate on any Proc,2 Procs, Index 1 (C2-type)
Package(){6, 0, 0, 0xFD, 2, 2} // 6 entries,Revision 0,Domain 0,OSPM Coordinate
// Initiate on any Proc,2 Procs,Index 2 (C3-type)
})
}
When the platform issues a Notify (\_SB.CPU0, 0x81) to inform OSPM to re-evaluate _CST when the number of
available processor power states changes, OSPM should also evaluate _CSD.
8.4.2 Processor Hierarchy
It is very typical for computing platforms to have a multitude of processors that share common resources, such as
caches, and which have common power states that affect groups of processors. These are arranged in a hierarchical
manner. For example, a system may contain a set of NUMA nodes, each with a number of sockets, which may
contain multiple groups of processors, each of which may contain individual processor cores, each of which may
contain multiple hardware threads. Different architectures use different terminology to denominate logically associated
processors, but terms such as package, cluster, module, and socket are typical examples. ACPI uses the term processor
container to describe a group of associated processors. Processors are said to belong to a container if they are associated
in some way, such as a shared cache or a low power mode which affects them all.
The ﬁgure above depicts an example system, which comprises a system level processor container, which in turn
contains two cluster processor containers, each of which contains two processors. The overall collection is called the
processor hierarchy and standard tree terminology is used to refer to different parts of it. For example, an individual
processor or container is called a node, the nodes which reside within a processor container are called children of
that parent, etc. This example is symmetric but that is not a requirement. For example, a system may contain a
different number of processors in different containers or an asymmetric hierarchy where one side of the topology tree
is deeper than another. Also note that while this example includes a single top level processor container encompassing
all processors, this is not a requirement. It is legal for a system to be described using a collection of trees. ( See Note
below )
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Fig. 8.6: Processor Hierarchy
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Note: The processor hierarchy can be used to describe a number of different characteristics of system topology. The
main example is shared power states, see the Low Power Idle states in Lower Power Idle States for details.
8.4.2.1 Processor Container Device
This optional device is a container object that acts much like a bus node in a namespace. It may contain child objects
that are either processor devices or other processor containers. This allows representing hierarchical processor topolo-
gies. Each processor container or processor in the hierarchy is herein referred to as a node. The processor container
device is declared using the hardware identiﬁer (_HID) ACPI0010.
To aid support of operating systems which do not parse processor containers, a container can carry a Compatible ID
(_CID) of PNP0A05, which represents a generic container device (see Device Class-Speciﬁc Objects )
A processor container declaration must supply a _UID method returning an ID that is unique in the processor container

hierarchy. A processor container must contain either other processor containers or other processor devices declared
within its scope. In addition, a processor container may also contain the following methods in its scope:
Table 8.4: Processor Container Device Objects
_LPI Declares local power states for the hierarchy node represented by the processor container
_RDI Declares power resource dependencies that affect system level power states
_STA Determines the status of a processor container. See Device Class-Speciﬁc Objects.
_LPI may be present under a processor device, and is described in _LPI (Low Power Idle States) . RDI can only be
present under a singular top level processor container object, and is described below.
ACPI allows the deﬁnition of more than one root level processor container. In other words, it is possible to deﬁne
multiple top level containers. For example, in a NUMA system if there are no idle states or other objects that need to
be encapsulated at the system level, multiple NUMA-node level processor containers may be deﬁned at the top level
of the hierarchy.
Processor Container Device objects are only valid for implementations conforming to ACPI 6.0 or higher. A platform
can ascertain whether an operating system supports parsing of processor container objects via the _OSC method (see
Platform-Wide OSPM Capabilities ).
8.4.3 Lower Power Idle States
ACPI 6.0 introduces Lower Power Idle states (LPI). This extends the speciﬁcation to allow expression of idle states
that, like C-states, are selected by the OSPM when a processor goes idle, but which may affect more than one processor,
and may affect other system components. LPI extensions in the speciﬁcation leverage the processor container device,
and in this way can express which parts of the system are affected by a given LPI state.
LPI states are deﬁned via the following objects:
• _LPI objects deﬁne the states themselves, and may be declared inside a processor or a processor container device
• _RDI allows expressing constraints on LPI usage borne out of device usage
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8.4.3.1 Hierarchical Idle States
Processor containers ( Processor Container Device ) can be used in conjunction with _LPI ( _LPI (Low Power Idle
States) ) to describe idle states in a hierarchical manner. Within the processor hierarchy, each node has low power
states that are speciﬁc to that node. ACPI refers to states that are speciﬁc to a node in the hierarchy as Local Power
States. For example in the system depicted in Power states for processor hierarchy , the local power states of CPU0
are clock gate, retention and power down.
When the OS running on a given processor detects there is no more work to schedule on that processor, it needs to
select an idle state. The state may affect more than just that processor. A processor going idle could be the last one
in the system, or in a processor container, and therefore may select a power state what affects multiple processors.
In order to select such a state, the OS needs to choose a local power state for each affected level in the processor
hierarchy.
Fig. 8.7: Power states for processor hierarchy
Consider a situation where Core 0 is the last active core depicted in the example system, Power states for processor
hierarchy . It may put the system into the lowest possible idle state. To do so, the OS chooses local state 3 (Power
Down) for Core0, local state 3 (Power Down) for Cluster0, and local state 1 (Power Down) for the system. However,
most HW architectures only support a single power state request from the OS to the platform. That is, it is not possible
to make a separate local power state request per hierarchy node to the platform. Therefore, the OS must combine the
per level local power states into a single Composite power state. The platform then acts on the Composite power state
request.
A platform can only support a limited set of Composite power states, and not every combination of Local Power states
across levels is valid. The valid power states in our example system are depicted in the following table.
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Table 8.5: Valid Local State Combinations in preceding example sys-
tem
System Level Processor Container Cluster level Processor Container Processor
Running Running Clock Gated
Running Running Retention
Running Running Power Down
Running Clock Gated Clock Gated
Running Clock Gated Retention
Running Clock Gated Power Down
Running Retention Retention
Running Retention Power Down
Running Power Down Power Down
Power Down Power Down Power Down
8.4.3.2 Idle State Coordination
With hierarchical idle states, multiple processors affect the idle state for any non-leaf hierarchy node. Taking our
example system in Power states for processor hierarchy , for cluster 0 to enter a low power state, both Core 0 and Core
1 must be idle. In addition, the power state selection done for Core 0 and Core 1 as they go idle has bearing on the
state that can be used for Cluster 0. This requires coordination of idle state requests between the two processors. ACPI
supports two different coordination schemes (detailed in subsections following):
• Platform coordinated
• OS initiated.
The OS and the platform can handshake on support for OS Initiated Idle or Platform Coordinated Idle using the
_OSC method as described in Platform-Wide OSPM Capabilities . Note that an Architecture speciﬁc command may
be required to enter OS Initiated mode, in which case please refer to architecture speciﬁc documentation. (For PSCI
documentation see http://ueﬁ.org/acpi under the heading “PCSI Speciﬁcation”; for ARM FFH documentation, see
http://ueﬁ.org/acpi under the heading “ARM FFH Speciﬁcation”.)
8.4.3.2.1 Platform Coordinated
With the Platform Coordinated scheme, the platform is responsible for coordination of idle states across processors.
OSPM makes a request for all levels of hierarchy from each processor meaning that each processor makes a vote by
requesting a local power state for itself, its parent, its parent’s parent, etc. (In some cases, the vote for a particular
hierarchy level may be implicit - see the autopromotion discussion below for more details). When choosing idle states
at higher levels, the OSPM on a processor may opt to keep a higher level node in a running state - this is still a vote
for that node which the platform must respect. The vote expressed by the OSPM sets out the constraints on the local
power state that the platform may choose for processor, and any parent nodes affected by the vote. In particular the
vote expresses that the platform must not enter:
1. A deeper (lower power) local state than the requested one.
2. A local power state with a higher wake up latency than the requested one.
3. A local power state with power resource dependencies that the requested state does not have.
The platform looks across the votes for each hierarchy node from all underlying cores and chooses the deepest lo-
cal state which satisﬁes all of the constraints associated with all of the votes. Normally, this just means taking the
shallowest state that one of the cores voted for, since shallower states have lower wakeup latencies, lower minimum
residencies, and fewer power resource dependencies. However, this may not always be the true, as state depth and
latencies do not always increase together. For the sake of efﬁciency, the platform should generally not enter a power
state with a higher minimum residency than the requested one. However, this is not a strict functional requirement.
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The platform may resolve to a state with higher minimum residency if it believes that is the most efﬁcient choice based
on the speciﬁc states and circumstances.
Using the above example in Power states for processor hierarchy , a simple ﬂow would look like this:
• Core0 goes idle - OS requests Core0 Power Down, Cluster0 Retention
• Platform receives Core0 requests - place Core0 in the Power Down state
• Core1 goes idle - OS requests Core1 Power Down, Cluster0 Power Down
• Platform receives Core1 request - puts Core1 in the Power Down state, and takes shallowest vote for Cluster0,
thus placing it into the Retention state
If the OSPM wanted to request power states beyond the cluster level, then Core0 and Core1 would both vote for an
idle state at System level too, and the platform would resolve the ﬁnal state selection across their votes and votes from
any other processors under the System hierarchy via the method described above.
As mentioned above, certain platforms support a mechanism called autopromotion where the votes for higher level
states may be implicit rather than explicit. In this scheme, the platform provides OSPM with commands to request
idle states at a lower level of the processor hierarchy which automatically imply a speciﬁc idle state request at the

respective higher level of the hierarchy. There is no command to explicitly request entry into the higher level state,
only the implicit request based on the lower level state.
For example, if the platform illustrated in Power states for processor hierarchy uses autopromotion for the Cluster0
Clock Gated state, neither Core0 nor Core1 can explicitly request it. However, a core level Clock Gate request from
either Core0 or Core1 would imply a Cluster0 Clock Gate request. Therefore, if both cores request core clock gating
(or deeper), Cluster0 will be clock gated automatically by the platform. Additional details on how autopromotion is
supported by ACPI can be found in Entry Method and Composition .
8.4.3.2.2 OS Initiated
In the OS Initiated coordination scheme, OSPM only requests an idle state for a particular hierarchy node when the
last underlying processor goes to sleep. Obviously a processor always selects an idle state for itself, but idle states
for higher level hierarchy nodes like clusters are only selected when the last processor in the cluster goes idle. The
platform only considers the most recent request for a particular node when deciding on its idle state.
The main motivations for OS Initiated coordination are:
1. Avoid overhead of OSPM evaluating selection for higher level idle states which will not be used since other
processors are still awake
2. Allow OSPM to make higher level idle state selections based on the latest information by taking only the most
recent request for a particular node and ignoring requests from processors which went to sleep in the past (and
may have been based on information which is now stale)
Using the above example in a simple ﬂow would look like the following.
Table 8.6: OS Initiated Flow
Step OS View of power states Platform view of power
states
0: Cores 0 and 1 are both awake
and running codeCore0: Running
Core1: Running
Cluster0: RunningCore0: Running
Cluster0: Running
1 OS on Core0 requests Core0
PowerDownCore0: PowerDown
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Table 8.6 – continued from previous page
states
2 Platform observes request and
places Core0 into power downCore0: PowerDown
Cluster0: RunningCore0: PowerDown
3 OS on Core1 requests Core1
PowerDown and Cluster0 Pow-
erDownCore0: PowerDown
Core1: PowerDown
Cluster0: PowerDownCore0: PowerDown
4 Platform observes requests for
Core1 and Cluster0 and pro-
cesses themCore0: PowerDown
Cluster0: PowerDown
Note that Core1 is making a cluster decision which affects both Core0 and Core1 so OSPM should consider expected
sleep duration, wake up latency requirements, device dependencies, etc. for both cores and not just Core1 when
requesting the cluster state.
The platform is still responsible for ensuring functional correctness. For example, if Core0 wakes back up, the cluster
state requested by Core1 in the above example should be exited or the entry into the state should be aborted. OSPM
has no responsibility to guarantee that the last core down is also the ﬁrst core up, or that a core does not wake up just
as another is requesting a higher level sleep state.
8.4.3.2.2.1 OS Initiated Request Semantics
With OS Initiated coordination, the ordering of requests from different cores is critically important since the platform
acts upon the latest one. If the platform does not process requests in the order the OS intended then it may put the
platform into the wrong state. Consider this scenario in our example system in Power states for processor hierarchy ,
as shown in the following table.
Table 8.7: Example of incorrect platform state in OS Initiated Re-
quest without Dependency Check
Step OS View of power states Platform view of power states
0: Core0 in PowerDown, and
Core1 is runningCore0: PowerDown
1 Core1 goes idle – the OSPM re-
quests Core1 PowerDown and
Cluster0 RetentionCore0: PowerDown
Cluster0: RetentionCore0: PowerDown
2 Core0 receives an interrupt and
wakes up into platformCore0: PowerDown
Cluster0: RetentionCore0: Running
3 Core0 moves into OSPM and
starts processing interruptCore0: Running
4 Core0 goes idle and OSPM re-
quest Core0 Power Down, Clus-
ter0 Power DownCore0: PowerDown
Cluster0: PowerDownCore0: Running
5 Core0’s idle request “passes”
Core1’s request. Platform puts
Core0 to Power Down but
ignores cluster request since
Core1 is still runningCore0: PowerDown
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Table 8.7 – continued from previous page
6 Core1’s request is observed by
the platform. Platform puts
Core1 to Power Down and Clus-
ter0 to retention.Core0: PowerDown
Cluster0: PowerDown!! (See
Note below)Core0: PowerDown
Cluster0: Retention!! (See Note
below)
Note: In the last row of the table above, the Cluster0 values are mismatched.
The key issue here is the race condition between the requests from the two cores; there is no guarantee that they reach
the platform in the same order the OS made them. It is not expected to be common, but Core0’s request could “pass”
Core1’s for a variety of potential reasons - lower frequency, different cache behavior, handling of some non-OS visible
event, etc. This sequence of events results in the platform incorrectly acting on the stale Cluster0 request from Core1
rather than the latest request from Core0. The net result is that Cluster0 is left in the wrong state until the next wakeup.
To address such race conditions and ensure that the platform and OS have a consistent view of the request ordering,
OS Initiated idle state request semantics are enhanced to include a hierarchical dependency check. When the platform
receives a request, it is responsible for checking whether the requesting core is really the last core down in the requested
domain and rejecting the request if not. Note that even if OSPM and the platform are behaving correctly, they may
not always agree on the state of the system due to various races. For example, the platform may see a core waking
up before OSPM, and therefore see that core as running, whilst the OSPM still sees it as sleeping. The platform can
start treating a particular core as being in a low power state, for the sake of the dependency check, once it has seen the
core’s request (so that it can be correctly ordered versus other OS requests). The platform must start treating a core as
running before returning control to the OS after it wakes up from an idle state.
With this dependency check, the above example would change as follows:
Table 8.8: OS Initiated Request Semantics with Dependency Check
Step: OS View of power states Platform view of power
states
0-4: Same as above Core0: PowerDown
Core1’s request. Platform re-
jects Core0’s request since it in-
cludes Cluster0 but Core1 is still
awake.Core0: PowerDown
the platform. Platform re-
jects Core1’s request since it in-
cludes Cluster0 but Core0 is still
7 OS resumes on Core0 Core0: Running
8 OS resumes on Core1 Core0: Running
Once control is returned to the OS, it can handle as it sees ﬁt - likely just re-evaluating the idle state on both cores.
When requests are received out of order, some overhead is introduced by rejecting the command and forcing the OS to
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re-evaluate, but this is expected to be rare. Requests sent by the OS should be seen by the platform in the same order
the vast majority of the time, and in this case, the idle command will proceed as normal.
It is possible that the OS may choose to keep a particular hierarchy node running even if all CPUs underneath it are

asleep. This gives rise to another potential corner case - see below.
Table 8.9: Example of incorrect platform state in OS Initiated Re-
quest without Hierarchy Parameter
1 Core1 goes idle – the OSPM OS
requests Core1 PowerDown and
quest Core0 Power Down and
requests Cluster0 to stay run-
ningCore0: PowerDown
Core0 to PowerDown. Even
though the OS made a request
for the cluster to run, Platform
does not know to reject Core0’s
request since it doesn’t include a
Cluster idle stateCore0: PowerDown
Cluster0: Running!! (See Note,
below)Core0: PowerDown
below)
The fundamental issue is that the platform cannot infer what hierarchy level a request is for, based on what levels are
being placed into a low power mode. To mitigate this, each idle state command must include a hierarchy parameter
specifying the highest level hierarchy node for which the OS is making a request in addition to the normal idle state
identiﬁer. Even if the OS does not want some higher level hierarchy node to enter an idle state, it should indicate if
the core is the last core down for that node. This allows the platform to understand the OS’s view of the state of the
hierarchy and ensure ordering of requests even if the OS requests a particular node to stay running.
This enhancement is illustrated in the following table.
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Table 8.10: OS Initiated Request Semantics with Hierarchy Parame-
ter
Step OS View of power
statesPlatform view of
power states
0: Core0 in PowerDown, and Core1 is running Core0: PowerDown
1 Core1 goes idle – the OSPM OS requests Core1 Power-
Down and Cluster0 Retention and identiﬁes itself as last
down in Cluster0Core0: PowerDown
2 Core0 receives an interrupt and wakes up into platform Core0: PowerDown
3 Core0 moves into OSPM and starts processing interrupt Core0: Running
4 Core0 goes idle and OSPM request Core0 Power Down
and requests Cluster0 to stay running and identiﬁes it-
self as last down in Cluster0Core0: PowerDown
5 Core0’s idle request “passes” Core1’s request. Platform
rejects Core0’s request since it is a request for Cluster0
but Core1 is still awake.Core0: PowerDown
Cluster0: Power-
DownCore0: Running
6 Core1’s request is observed by the platform. Platform
rejects Core1’s request since it is a request for Cluster0
but Core0 is still awake.Core0: PowerDown
As before, once control is returned to the OS, it can handle as it sees ﬁt - likely just re-requesting the idle state on both
cores.
8.4.3.3 _LPI (Low Power Idle States)
_LPI is an optional object that provides a method to describe Low Power Idle states that deﬁnes the local power states
for each node in a hierarchical processor topology. The OSPM uses the _LPI object to select a local power state for
each level of processor hierarchy in the system. These local state selections are then used to produce a composite
power state request that is presented to the platform by the OSPM.
This object may be used inside a Processor Container or a processor declaration. _LPI takes the following format:
None
A variable-length Package containing the local power states for the parent Processor or Processor Con-
tainer device as described in the table below. _LPI evaluation returns the following format:
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Package {
Revision, // Integer (WORD)
LevelID, // Integer (QWORD)
Count, // Integer (WORD)
LPI[1], // Package
...
LPI[N] // Package
}
Table 8.11: Local Power States for the Parent Processor or Processor
Container
Revision Integer (WORD) The revision number of the _LPI object. Current revision is 0.
LevelID Integer (QWORD) A platform deﬁned number that identiﬁes the level of hierarchy of the
processor node to which the LPI states apply. This is used in composition
of IDs for OS Initiated states described in Entry Method and Composition.
In a platform that only supports platform coordinated mode, this ﬁeld
must be 0.
Count Integer (WORD) The count of following LPI packages.
LPI[1] Package A Package containing the deﬁnition of LPI state 1.
LPI[N] Package A Package containing the deﬁnition of LPI state N.
Each LPI sub-Package contains the elements described below:
Package() {
Min Residency, // Integer (DWORD)
Worst case wakeup latency, // Integer (DWORD)
Flags, // Integer (DWORD)
Arch. Context Lost Flags, // Integer (DWORD)
Residency Counter Frequency, // Integer (DWORD)
Enabled Parent State, // Integer (DWORD)
Entry Method, // Buffer (ResourceDescriptor) or
// Integer (QWORD)
Residency Counter Register // Buffer (ResourceDescriptor)
Usage Counter Register // Buffer (ResourceDescriptor)
State Name // String (ASCIIZ)
}
Table 8.12: Extended LPI Fields
Min Residency Integer (DWORD) Minimum Residency - time in microseconds after which
a state becomes more energy efﬁcient than any shal-
lower state. See Power, Minimum Residency, and Worst
Case Wakeup Latency .
Worst case wakeup la-
tencyInteger (DWORD) Worst case time in microseconds from a wake inter-
rupt being asserted to the return to a running state of
the owning hierarchy node (processor or processor con-
tainer). See Power, Minimum Residency, and Worst
Flags Integer (DWORD) Valid ﬂags are described in Flags for LPI states .
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Table 8.12 – continued from previous page
Arch. Context Lost Flags Integer (DWORD) Architecture speciﬁc context loss ﬂags. These ﬂags may
be used by a processor architecture to indicate processor
context that may be lost by the power state and must
be handled by OSPM. See Architecture Speciﬁc Context
Loss Flags for more details.
Residency Counter Fre-
quencyInteger (DWORD) Residency counter frequency in cycles-per-second (Hz).
Value 0 indicates that counter runs at an architectural-
speciﬁ c frequency. Valid only if a Residency Counter
Register is deﬁned.
Enabled Parent State Integer (DWORD) Every shallower power state in the parent is also en-
abled. 0 implies that no local idle states may be entered
at the parent node.
Entry Method Buffer or Integer
(QWORD)This may contain a resource descriptor or an integer. A
Resource Descriptor with a single Register() descriptor
may be used to describe the register that must be read
in order to enter the power state. Alternatively, an in-
teger may be provided in which case the integer would
be used in composing the ﬁnal Register Value that must
be used to enter this state. This composition process is
described below in Entry Method and Composition .
Residency Counter Regis-
terBuffer Optional residency counter register which provides the
amount of time the owning hierarchy node has been
in this local power state. The time is provided in a
frequency denoted by the Residency counter frequency

ﬁeld (see above). The register is optional. If the plat-
form does not support it, then the following NULL
register descriptor should be used: ResourceTemplate()
{Register {(SystemMemory, 0, 0, 0, 0)}} .
Usage Counter Register Buffer
Optional register that provides the number of times the
owning hierarchy node has been in this local power
state. If the platform does not support this register, then
the following NULL register descriptor should be used:
ResourceTemplate() {Register
{(SystemMemory, 0, 0, 0, 0)}}
State Name String (ASCIIZ) String containing a human-readable identiﬁer of this
LPI state. This element is optional and an empty string
(a null character) should be used if this is not supported.
Table 8.13: Flags for LPI states
Element Bits Description
Enabled 0 1 if the power state is enabled for use | 0 if the power state is disabled
It is not required that all processors or processor containers include _LPI objects. However, if a processor container
includes an _LPI object, then all children processors or processor containers must have _LPI objects.
The following sections describe the more complex properties of LPI in more detail, as well as rules governing wakeup
for LPI states.
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8.4.3.3.1 Disabling a State
When a local state is disabled by clearing the Enabled bit in the Flags ﬁeld, any deeper states for that node are not
renumbered. This allows other properties which rely on indexing into the state list for that node (Enabled Parent State
for example) to not change.
Disabled states should not be requested by the OS and values returned by Residency/Usage Counter Registers are
undeﬁned.
8.4.3.3.2 Enabled Parent State
As mentioned above, LPI represent local states, which must be combined into a composite state. However not every
combination is possible. Consider the example system described in Power states for processor hierarchy . In this
system it would not be possible to simultaneously select clock gating as local state for Core0 and power down as local
state for Cluster0. As Core0 is physically in Cluster0, power gating the cluster would imply power gating the core.
The correct combinations of local states for this example system are described in Valid Local State Combinations in
preceding example system . LPI states support enumeration of the correct combinations through the Enabled Parent
State (EPS) property.
LPI States are 1-indexed. Much like C and S states, LPI0 is considered to be a running state. For a given LPI, the EPS
is a 1-based index into the processor containers’ _LPI states. The index points at the deepest local power state of the
parent processor that the given LPI state enables. Every shallower power state in the parent is also enabled. Taking the
system described in Fig. 8.7, the states and EPS value for the states is described in Table 8.14 below.
Table 8.14: Enabled Parent State values for example system
Category / Bit Value State Enabled Parent State
System Level ProcessorContainer LPI
States
0 Running N/A
1 Power Down 0
Cluster Level ProcessorContainer LPI
States
1 Clock Gating 0 – System must be running if cluster is clock gated
2 Retention 0 – System must be running if cluster is in retention
3 Power Down 1 – System may be in power down if cluster is in power
down
Core Level ProcessorContainer LPI
States
1 Clock Gating 1 – Cluster may be clock gated or running of core is
clock gated
2 Retention 2 – Cluster may running, or clock gated, or in retention
if core is in retention
3 Power Down 3 – All states at cluster level are supported if the core is
powered down
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8.4.3.3.3 Power, Minimum Residency, and Worst Case Wakeup Latency
Power is not included in _LPI since relative power of different states (along with minimum residency to comprehend
transition energy), and not absolute power, drive OSPM idle state decisions. To correctly convey relative power, local
states in _LPI must be declared in power consumption order. That is, the local states for a particular hierarchy node
must be listed from highest power (shallowest) to lowest power (deepest).
The worst case wakeup latency (WCWL) for a particular local state is the longest time from when a wake interrupt is
asserted, to when the hierarchy node can return to execution. Generally, the WCWL will be the idle state’s exit latency
plus some portion of its entry latency. How much of the entry ﬂow is included depends on where (and if) the platform
supports checking for pending wake events and aborting the idle state entry. For any given power state there will be
a “point of no return” after which the entry into the power state cannot be reversed. This is illustrated in Worst case
wake latency below. The WCWL must include the time period from the point of no return to the time at which a wake
up interrupt can be handled.
Fig. 8.8: Worst case wake latency
Note that other worst case paths could end up determining the WCWL, but what is described above is expected to be
the most common. For example, there could be another period between the OS making the idle request and the point
of no return where the platform does not check for wake up events, and which is longer than the time taken to enter
and exit the power state. In that case that period would become the worst case wakeup latency.
Minimum residency (MR) is the time after which a state becomes more energy efﬁcient than any shallower state.
This parameter answers the fundamental question: how long does the hierarchy node need to stay in the idle state
to overcome the energy cost of transitioning in/out, and make choosing that state a net win relative to shallower
alternatives? Note that this also includes comparing against not entering an idle state and keeping the node running.
This is illustrated in Energy of states A,B and C versus sleep duration , which shows the energy associated with three
different state choices as a function of the sleep duration. Note that State A’s MR relative to keeping the node running
is not pictured.
Generally, minimum residency and worst case wakeup latency will be larger for deeper states, however this may not
always be the case. Taking a different example to the above, consider two system level states, StateY and StateZ, with
similar entry overhead but where StateZ saves more power than StateY . An abstract state list might look like:
StateX: MR = 100 us
StateY: MR = 1000 us
StateZ: MR = 800 us, power resource A must be OFF
8.4. Declaring Processors 498Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 8.9: Energy of states A,B and C versus sleep duration
From an energy perspective, StateZ is always preferred, but in this example, StateZ is only available when certain
device dependencies are met. This makes StateY attractive when the dependencies cannot be met. Despite being the
deeper (lower power) state, StateZ has a lower MR than StateY since the entry overheads are similar and StateZ’s lower
power more quickly amortizes the transition cost. Although the crossover, which sets MR, should generally be versus
the next shallowest state, MR is deﬁned relative to any shallower (higher power) state to deal with cases like this. In
this case, StateZ’s MR is set by the crossover with StateX since StateZ (if allowed based on device dependencies)
is always preferred to StateY . To achieve the lowest energy, OSPM must select the deepest (lowest power) state for
which all entry constraints are satisﬁed and should not assume that deeper states are not viable just because a shallower
state’s WCWL/MR threshold was not met.
Since WCWL may be used by OSPM to restrict idle state selection and guarantee response times to critical interrupts,
it should be set conservatively (erring on the high side) so that OSPM is not surprised with worse than speciﬁed
interrupt response time. On the other hand, MR helps OSPM make efﬁcient decisions. If MR is inaccurate in a certain
scenario and OSPM chooses a state which is deeper or shallower than optimal for a particular idle period, there may be
some wasted energy but the system will not be functionally broken. This is not to say that MR doesn’t matter -energy
efﬁciency is important - just that the platform may choose to optimize MR based on the typical case rather than the
worst case.
8.4.3.3.3.1 Minimum Residency and Worst Case Wakeup Latency Combination Across Hierarchy
Levels
The WCWL in _LPI is for a particular local state. When evaluating composite state choices versus system latency
tolerance as part of idle state selection, OSPM will add wakeup latencies across hierarchy levels. For example, if
a system has core powerdown with WCWL = 50 us and cluster powerdown with WCWL = 20 us then the core
powerdown + cluster powerdown composite state latency is calculated as 70 us.

Levels
MRs deﬁned in _LPI apply to a particular hierarchy node. The implicit assumption is that each hierarchy node
represents an independent power manageable domain and can be considered separately. For example, assume that a
cluster retention state is legal if the underlying cores are in core powerdown or core retention. The MR for cluster
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retention is based on the energy cost of taking shared logic outside of the cores in and out of retention versus the steady
state power savings achieved in that shared logic while in that state. The key is that the speciﬁc state chosen at the
core level does not fundamentally affect the cluster level decision since it is tied to properties of shared logic outside
the core. The energy cost of entering/exiting the cluster state and the power savings it provides are independent of
whether the core is in retention or powerdown. Based on this, MRs are considered independent per level in ACPI.
That is, when comparing MR for different states to expected sleep duration for a particular node, OSPM uses the MRs
deﬁned in that node’s _LPI as is with no adjustment based on states at lower levels of hierarchy (though of course the
state must be legal based on the lower level state’s Enabled Parent State property).
8.4.3.3.3.2 Known Limitations with Minimum Residency and Worst Case Wakeup Latency
Note that the WCWL and MR parameters are not perfect. For example, they do not scale with frequency, voltage,
temperature, and various other factors which may affect them. Nor are the rules for how they combine across levels
perfect. For example, cluster level MRs may move slightly based on core state choice since the entry latency of the core
state will delay entry into the cluster state, derating the expected sleep duration. The cluster level MR can be adjusted
to comprehend this, but if multiple core level states with different entry latencies enable the same cluster state, then its
MR cannot perfectly comprehend them all. With that said, this set of parameters and combination scheme is believed
to strike a good balance between simplicity/usability and accuracy.
8.4.3.3.4 Entry Method and Composition
The OSPM combines Local LPI states to create an overall composite power state. Each LPI state provides an entry
method ﬁeld. These ﬁelds, for the selected local power states, are combined to create the entry method register that
must be read in order to enter a given composite power state.
To derive the appropriate register address from the local states’ entry methods, the following approach is used:
1. Local states for Processors always declare a register based entry method. This provides a base register.
2. Higher levels may use an integer or a register. If an Integer is used, then its value must be added to the base
register obtained in step 1. If a register is used, then this becomes the new base register, overriding any previous
value. Note that in this case, the selected LPI must imply speciﬁc local LPI selections for all lower level nodes.
3. In OS Initiated mode it is also necessary for the OSPM to tell the platform on which hierarchy level the calling
processor is the last to go idle. This is done by adding the Level ID property of the hierarchy node’s LPI to the
base register.
The basic composition algorithm for entry state is shown in the pseudo-code below for a platform coordinated system:
Reg = SelectedLocalState(CurrentProcessor).EntryMethod
WCWL = SelectedLocalState(CurrentProcessor).WCWL
MR = SelectedLocalState(CurrentProcessor).MR
forlevel = Parent(CurrentProcessor) to system
LocalState = SelectedLocalState(level)
If LocalState == Run
break
EM = LocalState.EntryMethod
WCWL = WCWL+ LocalState.WCWL
MR = LocalState.MR
If IsInteger(EM)
Reg.Addr = Reg.Addr+ZeroExtend(EM)
Else
// Entry method here overrides any previous method
Reg = EM
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CompositeState.EntryMethod = Reg
CompositeState.WCWL=WCWL
CompositeState.MR=MR
In OS Initiated mode it is also necessary for the OSPM to tell the platform on which hierarchy level the calling
processor is the last to go idle and request a power state. To do this, the algorithm above is modiﬁed as follows:
RegDecided = False
// Retrieve Level Index from Processor 's \_LPI object
LastLevel = GetLevelIDOfLevel(CurrentProcessor)
break
Else
// Entry method isregister
Reg = EM
If IsProcessorLastInLevel(CurrentProcessor,level)
// If calling processor islast one to go idle in
// current level, retrieve Level Index from
// the container's \_LPI object
LastLevel = GetLevelIDOfLevel(level)
Reg.Addr = Reg.Addr+LastLevel
In a platform coordinated system, it is possible for an LPI belonging to a hierarchy node above the processor level to
use an integer value of zero as its entry method. Since entry method composition is done by addition, this results in the
entry command for that state being the same as for a composite state which only includes its children. An entry value
of 0 essentially identiﬁes a state as “autopromotable.” This means that the OS does not explicitly request entry into this
state, but that the platform can automatically enter it when all children have entered states which allow the parent state
based on their EPS properties. OSPM should follow normal composition procedure for other parameters (worst case
wakeup latency, minimum residency, etc.) when including composite states involving autopromotable local states.
This is described in the following example:
Device (SYSM) { // System level states
Name (_HID, "ACPI0010")
Name (_UID, 0)
Name (_LPI,
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0, // Version
0, // Level ID
1, // Count
Package () { // Power gating state forsystem
900, // Min residency (uS)
400, // Wake latency (uS)
0, // Enabled Parent State
... // (skipped fields). . .
ResourceTemplate () {
// Register Entry method
Register(FFH,0x20,0x00,0x00000000DECEA5ED,0x3)
},
}
)
Device (CLU0) { // Package0 state
Name (_UID, 1)
2, // Count
Package () { // Retention state forCluster
40, // Min residency (uS)
20, // Wake latency (uS)
0, // System must be running
0, // Integer Entry method
},
Package () { // Power Gating state forCluster
100, // Min residency (uS)
80, // Wake latency (uS)
1, // System may power down
0x1020000, // Integer Entry method
}
}
)
Name(PLPI,
2, // Count
Package () { // Retention state forCPU
1, // Parent node can be
//inretention orrunning
Register(FFH,
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0x20,0x00,
0x000000000000DEAF,0x3),
}
},
Package () { // Power Gating state forCPU
2, // Parent node can be inany state
0x0000000000000DEAD,0x3),
}
}
}
)
Device (CPU0) { // Core0
Name (_HID, "ACPI0007")
Method (_LPI, 0, NotSerialized)
{
return(PLPI)
}
}
Device (CPU1) { // Core1
{
}
}
} // end of NOD0
Device (CLU1) { // Package1 state
Name (_UID, 2)
....
}
} // End of SYM
In the example above, the OSPM on CPU0 and CPU1 would be able to select the following composite states:
Table 8.15: Entry method example
Core LPI Cluster LPI System LPI Composite State Entry Method
Retention Register:
0xDEAFRun Run Core Retention Register: 0xDEAF
Power Down Regis-
ter 0xDEADRun Run Core Power Down Register: 0xDEAD
0xDEAFRetention Integer:
0x0Run Core Retain Retention Register
0xDEAF+0x0 = 0xDEAF
ter: 0xDEADRetention Integer:
0x0Run Core Power Down Retention Register
0xDEAD+0x102000 0 = 0xDEAD

}
}
}
)
{
}
}
{
}
}
....
}
8.4. Declaring Processors 503Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 8.15 – continued from previous page
ter: 0xDEADPower Down Inte-
ger: 0x1020000Run Core Power Down Power Down Register
0xDEAD+0x102000 0 = 0x102DEAD
ger: 0x1020000Power Down Regis-
ter : 0xDECEA5EDSystem Power Down Register 0xDE-
CEA5ED
As can be seen in the example, the cluster level retention state deﬁnes the integer value of 0 as its entry method. By
virtue of composition, this means that the entry methods for the composite states Core Power Down and Core Power
Down|Cluster Retention are the same (FFH register 0xDEAD). Similarly the composite states for Core Retention and
Core Retention|Cluster Retention are the same (FFH register 0xDEAF). Consequently, if both CPU0 and CPU1 are in
either Power Down or Power Retention, then the platform may enter cluster CLU0 into Retention.
The example also shows how a register based entry method at a high level overrides entry method deﬁnitions of lower
levels. As pointed above this is only possible if the selected LPI implies speciﬁc LPIs at all lower levels. In this
example the System Power Down LPI, entered through FFH register 0xDECEA5ED, implies Power Down LPIs at
core and cluster level since based on EPS, no other core/cluster local states could enable System Power Down.
8.4.3.3.5 Architecture Speciﬁc Context Loss Flags
For Intel based systems the value of this ﬂags register is 0.
For ARM based systems please refer to links to ACPI-Related Documents ( http://ueﬁ.org/acpi ) under the heading
“ARM FFH Speciﬁcation”.
8.4.3.3.6 Residency and Entry Counter Registers
LPI state descriptions may optionally provide Residency and Usage Count registers to allow the OSPM to gather
statistics about the platform usage of a given local state. Both registers provide running counts of their respective
statistics. To measure a statistic over some time window, OSPM should sample at the beginning and end and calculate
the delta. Whether the counters restart from 0 on various ﬂavors of reset/S-state exit is implementation deﬁned so
OSPM should resynchronize its baseline on any reset or Sx exit.
The registers are optional, and if the feature is not present the platform must use a NULL register of the following
form:
ResourceTemplate() {Register {(SystemMemory, 0, 0, 0, 0)}}
The Usage Count register counts how many times the local state has been used. Whether it counts entries or exits is
implementation deﬁned.
The Residency register counts how long the hierarchy node has been in the given LPI state, at a rate given by LPI’s Res-
idency Counter Frequency ﬁeld. A frequency of 0 indicates that the counter runs at an architecture-speciﬁc frequency.
Whether the Residency counter runs continuously while in a local state or updates only on exit is implementation de-
ﬁned. If OSPM wants to guarantee that the reading for a particular state is current, it should read from that processor
itself (or one of the underlying child processors in the case of a higher level idle state).
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8.4.3.3.7 Wake from LPI States
With _LPI, the platform can describe deep S0-idle states which may turn off fundamental resources like bus clocks,
interrupt controllers, etc. so special care must be taken to ensure that the platform can be woken from these states.
This section describes handling for device initiated wakes. There are other wake sources such as timers, which are
described elsewhere.
For device wakes, the requirement is that OSPM must not enter any LPI state that would prevent a device enabled
for wake from waking the system. This means not entering any LPI state for which any Power Resource listed in
_RDI (see the _RDI section _RDI (Resource Dependencies for Idle) ) is required to be ON. Note that on a platform
coordinated system, the OSPM may choose to enter an _LPI state even if there are resources listed in its companion
RDI that are still on. However, if the OSPM has already enabled a device for wake, and ensured the power resources
needed for wake are on, the platform will demote the LPI state to one where said resources remain on.
The wake device uses the standard _PRx and _PRW methods to describe power resources it requires to be ON based
on its D-state and wake enabled status. This further implies that any device enabled for wake which depends on a
resource which may be turned off as part of an LPI state must describe that dependency via _PRx/_PRW => _RDI =>
_LPI.
This is illustrated in the following example:
PowerResource(PWRA,0,0) {...}
PowerResource(PWRB,0,0) {...}
PowerResource(PWRC,0,0) {...}
PowerResource(PWRD,0,0) {...}
PowerResource(PWRE,0,1) {...}
Device (FOO) {
Name(_S0W, 4) //Device inD3Cold can wake system from S0-idle
Name(_PR0,Package(){PWRA, PWRB, PWRC})
Name(_PR2,Package(){PWRA, PWRB})
Name(_PR3,Package(){PWRA})
Name(_PRE,Package(){PWRD})
Name(_PRW,Package(){0, 0, PWRD} // PWRD must be ON forFOO to wake system
}
Device (BAR) {
Name(_S0W, 3) // Device inD3Hot can wake system from S0-idle
Name(_PR0,Package(){PWRA, PWRB})
Name(_PR3,Package(){PWRC})
Name(_PRW,Package(){PWRC}) // PWRC must be ON forBAR to wake system
}
Device (BAH) {
Name(_S0W, 0) // This device can only wake the system from
// S0-idle ifitis inD0
}
Device (SYM) {
Name(_RDI,
Package(){} // Local State 1 isShallow;
// Devices FOO, BAR andBAH can wake
// the system ifenabled forwake
Package(){PWRA, PWRB} // RDI forLocal State 2. State isdeeper
// Device BAH cannot wake the system ifthis
// state isused, asit needs PWRA andPWRB
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// to be able to wake the system
Package(){PWRA, PWRB, PWRC} // RDI forLocal State 3.
// Devices BAH andBAR cannot wake
// the system, BAH needs PWRA, PWRB
//andPWRC, andBAR needs PWRC
//forall devices
Package(){PWRA, PWRB, PWRC, PWRD} // Noneof the devices listed
// above could wake the system
})
...
The example above declares a set of power resources (PWRA/B/C/D). Additionally, it has four system level local
states that have the following dependencies:
• LPI 1: Has no power resources dependencies
• LPI 2: Requires PWRA and PWRB to be off
• LPI 3: Requires PWRA, PWRB and PWRC to be off
• LPI 4: Requires all of the power resources in the example to be off
Device BAH can only wake the system if it is in the D0 state. To be in D0 it requires PWRA, PWRB and PWRC to
be on. Therefore device BAH could only wake the system from LPI 1. If this device is enabled for wake, then the
platform must not enter LPI 2 or deeper.
Device BAR can wake the system in whilst it is in any device state other than D3Cold. However, to do so, it requires
PWRC to be on. Therefore it can only wake the system from LPI 1 or LPI 2. If this device is enabled for wake, then
the platform must not enter LPI 3 or deeper.
Device FOO can wake the system whilst it is in any device state. However to do so, it requires PWRD to be on.
Therefore it can only wake the system from LPI 1 or LPI 2 or LPI 3. If this device is enabled for wake, then the
platform must not enter LPI 4.
8.4.3.3.8 Default Idle State
The shallowest idle state for each leaf node in the hierarchy is the “default” idle state for that processor and is assumed
to always be enterable. The worst case wakeup latency and minimum residency for this state must be low enough that
OSPM need not consider them when deciding whether to use it. Aside from putting the processor in a power state,
this state has no other software-visible effects. For example, it does not lose any context that OSPM must save/restore
or have any device dependencies.
8.4.3.4 _RDI (Resource Dependencies for Idle)
Some platforms may have power resources that are shared between devices and processors. Abstractly, these resources
are managed in two stages. First, the OS does normal power resource reference counting to detect when all device
dependencies have been satisﬁed and the resource may be power managed from the device perspective. Then, when
the processors also go idle, the OS requests entry into speciﬁc LPI states and the platform physically power manages
the resources as part of the transition. The dependency between the power resources and the LPI state is described in
_RDI.
_RDI objects may only be present at the root processor container that describes the processor hierarchy of the system.
_RDI is not supported in a system that has more than one root node. _RDI is valid only in a singular top level container
which encompasses all processors in the system.
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_RDI.
The OSPM will ignore _RDI objects that are present at any node other than the root node. This simpliﬁcation avoids
complicated races between processors in one part of the hierarchy choosing idle states with resource dependencies
while another processor is changing device states/power resources.
None
A variable-length Package containing the resource dependencies with the following format:
Package {
RDI[1], // Package
...
RDI[N] // Package
}
Table 8.16: _RDI package return values
Revision Integer (WORD) The revision number of the _RDI object. Current revision is 0.
RDI[1] Package A variable length Package containing the power resource dependencies of
system level power state 1.
RDI[N] Package A variable length Package containing the power resource dependencies of
system level power state N.
Each RDI[x] sub-Package contains a variable number of References to power resources:
Package {
Resource[0], // Object Reference to a Power Resource Object
...
Resource[M] // Object Reference to a Power Resource Object
}
ThePackage contains as many RDI packages as there are system level power states in the root processor container
node’s _LPI object. The indexing of LPI power states in this _LPI object matches the indexing of the RDI packages
in the _RDI object. Thus the nth LPI state at the system level has resource dependencies listed in the nth RDI. Each
RDI package returns a list of the power resource objects (passive or standard power resources) that must be in an OFF
state to allow the platform to enter the LPI state. If a system level LPI does not have any resource dependencies, the
corresponding RDI should be an empty Package .
Both traditional and passive power resources can be listed as dependencies in _RDI. For traditional power resources,
OSPM should ensure that the resource is OFF before requesting a dependent LPI state. For passive power resources,
there are no _ON/_OFF/_STA methods so the only requirement is to check that the reference count is 0 before re-
questing a dependent LPI state.
OSPM requirements for ordering between device/power resource transitions and power resource dependent LPI states
differ based on the coordination scheme.
In a platform coordinated system the platform must guarantee correctness and demote the requested power state to one
that will satisfy the resource and processor dependencies. OSPM may use the dependency info in _RDI as it sees ﬁt,
and may select a dependent LPI state even if resources remain ON.
In an OS initiated system, OSPM must guarantee that all power resources are off (or reference counts are 0, for passive
power resources) before requesting a dependent LPI state.
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_RDI Example
The following ASL describes a system that uses _RDI to describe the dependencies between three power resources
and system level power states:
PowerResource(PWRA,0,0) { // power rail local to DEVA
Method(_ON) {...} // active power resource (_OFF turns rail off)
Method(_OFF) {...}
Method(_STA) {...}
}
PowerResource(PWRB,0,0) { // power rail shared between DEVB andthe processor
Method(_ON) {...} // active power resource (_OFF drives platform vote)
}
PowerResource(PWRC,0,0) {} // clock rail shared between DEVC andthe processor
// passive power resource
Device (DEVA) {
Name(_PR0,Package(){PWRA})
}
Device (DEVB) {
Name(_PR0,Package(){PWRB})
}
Device (DEVC) {
Name(_PR0,Package(){PWRC})
}
0, // Revision
Package(){} // Local State 1 has no power resource
// dependencies
Package(){PWRA} // Local State 2 cannot be entered ifDEVA
//is inD0 due to PWRA
Package(){PWRA, PWRB, PWRC} // Local State 3 cannot be entered if
// DEVA is inD0 (due to PWRA), DEVB is in
// D0 (due to PWRB) orDEVC is inD0
// (due to PWRC)
})
...
OSPM will turn the traditional power resource (PWRA) ON or OFF by waiting for the reference count to reach 0
(meaning DEV A has left D0) and running the _OFF method. Similarly, PWRB is turned ON or OFF based on the state
of DEVB. Note that because the CPUs require the shared power rail to be ON while they are running, PWRB’s _ON
and _OFF drive a vote rather than the physical HW controls for the power rail. In this case, _STA reﬂects the status of
the vote rather than the physical state of PWRB.
OSPM guarantees ordering between PWRA/PWRB’s _ON and _OFF transitions and DEV A/DEVB’s D-state transi-
tions. That is, PWRA can only be turned OFF after DEV A has left D0, and must be turned ON before transitioning
DEV A to D0. However, the OS requirements for ordering between power resource transitions and power resource
dependent LPI states differ based on the coordination scheme.
In a platform coordinated system, OSPM may or may not track the power state of PWRA before selecting local state
2 or 3. The platform must independently guarantee that PWRA is OFF before entering local state 2 or 3, and must
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demote to a shallower state if OSPM selects local state 2 or 3 when PWRA is still on. Note that because OSPM is
required to correctly sequence power resource transitions with device power transitions, the platform does not need to
check the state of DEV A; it can rely on the state of PWRA to infer that DEV A is in an appropriate D-state.
Similarly, OSPM may or may not track the state of PWRB and PWRC before selecting local state 3, and the platform
must independently guarantee that PWRB is off before entering either state. Because PWRC is a passive power
resource, the platform does not know when the reference count on the power resource reaches 0 and instead must track
DEVC’s state itself. Unless the platform has other mechanisms to track the state of DEVC, PWRC should be deﬁned
as a traditional power resource so that the platform can use its _ON and _OFF methods to guarantee correctness of
In an OS initiated system, OSPM is required to guarantee that PWRA is OFF before selecting either local state 2 or
3. OSPM may meet this guarantee by waiting until it believes a processor is the last man down in the system, before
checking the state of PWRA, and only selecting local state 2 or 3 in this case. If the processor was the last man
down, then the request to enter local state 2 or 3 is legal and the platform can honor it. If another processor woke up
in the meantime and turned PWRA on, then this becomes a race between processors which is addressed in the OS
Initiated Request Semantics section ( OS Initiated Request Semantics ). Similarly, OSPM must guarantee PWRB is off
and PWRC’s reference count is 0 before selecting local state 3.
In an OS initiated system, because OSPM guarantees that power resources are in their correct states before selecting
system power states, the platform should use passive power resources unless there is additional runtime power savings
to turning a power resource OFF. On a platform that only supports OS Initiated transitions, PWRB should be deﬁned
as a passive power resource because it is shared with processors and can only be turned off when the system power
state is entered.
8.4.3.5 Compatibility
In order to support older operating systems which do not support the new idle management infrastructure, the _OSC
method can be used to detect whether the OSPM supports parsing processor containers and objects associated with
LPIs and (_LPI, _RDI). This is described in Rules for Evaluating _OSC .
A platform may choose to expose both _CST and _LPI for backward compatibility with operating systems which do
not support _LPI. In this case, if OSPM supports _LPI, then it should be used in preference to _CST. At run time only
one idle state methodology should be used across the entire processor hierarchy - _LPI or _CST, but not a mixture of
both.
8.4.4 Processor Throttling Controls
ACPI deﬁnes two processor throttling (T state) control interfaces. These are:
• The Processor Register Block’s (P_BLK’s) P_CNT register.
• The combined _PTC, _TSS, and _TPC objects in the processor’s object list.
P_BLK based throttling state controls are described in ACPI Hardware Speciﬁcation . Combined _PTC, _TSS, and
_TPC based throttling state controls expand the functionality of the P_BLK based control allowing the number of T
states to be dynamic and accommodate CPU architecture speciﬁc T state control mechanisms as indicated by registers
deﬁned using the Functional Fixed Hardware address space. While platform deﬁnition of the _PTC, _TSS, and _TPC
objects is optional, all three objects must exist under a processor for OSPM to successfully perform processor throttling
via these controls.
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8.4.4.1 _PTC (Processor Throttling Control)

both.
_PTC is an optional object that deﬁnes a processor throttling control interface alternative to the I/O address spaced-
based P_BLK throttling control register (P_CNT) described in ACPI Hardware Speciﬁcation
OSPM performs processor throttling control by writing the Control ﬁeld value for the target throttling state (T-state),
retrieved from the Throttling Supported States object (_TSS), to the Throttling Control Register (THROTTLE_CTRL)
deﬁned by the _PTC object. OSPM may select any processor throttling state indicated as available by the value
returned by the _TPC control method.
Success or failure of the processor throttling state transition is determined by reading the Throttling Status Register
(THROTTLE_STATUS) to determine the processor’s current throttling state. If the transition was successful, the
value read from THROTTLE_STATUS will match the “Status” ﬁeld in the _TSS entry that corresponds to the targeted
processor throttling state.
None
A Package as described below
Package
{
ControlRegister // Buffer (Resource Descriptor)
StatusRegister // Buffer (Resource Descriptor)
}
Table 8.17: _PTC Package Values
Control Register Buffer Contains a Resource Descriptor with a single Register() descriptor
that describes the throttling control register.
Status Register Buffer Contains a Resource Descriptor with a single Register() descriptor
that describes the throttling status register.
The platform must expose a _PTC object for either all or none of its processors. Notice that if the _PTC object exists,
the speciﬁed register is used instead of the P_CNT register speciﬁed in the Processor term. Also notice that if the
_PTC object exists and the _CST object does not exist, OSPM will use the processor control register from the _PTC
object and the P_LVLx registers from the P_BLK.
Example
This is an example usage of the _PTC object in a Processor object list:
{ // Object List
Name(_PTC, Package () // Processor Throttling Control object
{
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, // Throttling_CTRL
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} // Throttling_STATUS
}) // End of \_PTC object
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} // End of Object List
Example
This is an example usage of the _PTC object using the values deﬁned in ACPI 1.0. This is an illustrative example to
demonstrate the mechanism with well-known values.
Name(_PTC, Package () // Processor Throttling Control object -
// 32 bit wide IO space-based register at the <p_blk> address
{
ResourceTemplate(){Register(SystemIO, 32, 0, 0x120)}, // Throttling_CTRL
ResourceTemplate(){Register(SystemIO, 32, 0, 0x120)} // Throttling_STATUS
8.4.4.2 _TSS (Throttling Supported States)
This optional object indicates to OSPM the number of supported processor throttling states that a platform supports.
This object evaluates to a packaged list of information about available throttling states including percentage of maxi-
mum internal CPU core frequency, maximum power dissipation, control register values needed to transition between
throttling states, and status register values that allow OSPM to verify throttling state transition status after any OS-
initiated transition change request. The list is sorted in descending order by power dissipation. As a result, the zeroth
entry describes the highest performance throttling state (no throttling applied) and the ‘nth’ entry describes the lowest
performance throttling state (maximum throttling applied).
When providing the _TSS, the platform must supply a _TSS entry whose Percent ﬁeld value is 100. This provides a
means for OSPM to disable throttling and achieve maximum performance.
None
A variable-length Package containing a list of Tstate sub-packages as described below.
Package {
TState [0] // Package - Throttling state 0
....
TState [n] // Package - Throttling state n
}
Each Tstate sub-Package contains the elements described below.
Package {
Percent // Integer (DWORD)
Latency // Integer (DWORD)
Control // Integer (DWORD)
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}
Table 8.18: TState Package Values
Percent Integer
(DWORD)Indicates the percent of the core CPU operating frequency that will be available
when this throttling state is invoked. The range for this ﬁeld is 1-100. This
percentage applies independent of the processor’s performance state (P-state).
That is, this throttling state will invoke the percentage of maximum frequency
indicated by this ﬁeld as applied to the CoreFrequency ﬁeld of the _PSS entry
corresponding to the P-state for which the processor is currently resident.
Power Integer
(DWORD)Indicates the throttling state’s maximum power dissipation (in milliWatts).
OSPM ignores this ﬁeld on platforms the support P-states, which provide power
dissipation information via the _PSS object.
Latency Integer
(DWORD)Indicates the worst-case latency in microseconds that the CPU is unavailable
during a transition from any throttling state to this throttling state.
Control Integer
(DWORD)Indicates the value to be written to the Processor Control Register (THROT-
TLE_CTRL) in order to initiate a transition to this throttling state.
(DWORD)Indicates the value that OSPM will compare to a value read from the Throt-
tle Status Register (THROTTLE_STATUS) to ensure that the transition to the
throttling state was successful. OSPM may always place the CPU in the lowest
power throttling state, but additional states are only available when indicated by
the _TPC control method. A value of zero indicates the transition to the Throt-
tling state is asynchronous, and as such no status value comparison is required.
8.4.4.3 _TPC (Throttling Present Capabilities)
This optional object is a method that dynamically indicates to OSPM the number of throttling states currently supported
by the platform. This method returns a number that indicates the _TSS entry number of the highest power throttling
state that OSPM can use at a given time. OSPM may choose the corresponding state entry in the _TSS as indicated by
the value returned by the _TPC method or any lower power (higher numbered) state entry in the _TSS.
None
AnInteger containing the number of states supported:
0 - states 0 . . . nth state available (all states available)
1 - state 1 . . . nth state available
2 - state 2 . . . nth state available
. . .
n- state navailable only
In order to support dynamic changes of _TPC object, Notify events on the processor object of type 0x82 will cause
OSPM to reevaluate any _TPC object in the processor’s object list. This allows AML code to notify OSPM when the
number of supported throttling states may have changed as a result of an asynchronous event. OSPM ignores _TPC
Notify events on platforms that support P-states unless the platform has limited OSPM’s use of P-states to the lowest
power P-state. OSPM may choose to disregard any platform conveyed T-state limits when the platform enables OSPM
usage of other than the lowest power P-state.
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8.4.4.4 _TSD (T-State Dependency)
This optional object provides T-state control cross logical processor dependency information to OSPM. The _TSD
object evaluates to a packaged list containing a single entry that expresses the T-state control dependency among a set
of logical processors.
None
A Package containing a single entry consisting of a T-state dependency Package as described below.
Package {
TStateDependency[0] // Package
}
The TStateDependency sub-Package contains the elements described below:
Package {
}
Table 8.19: T-State Dependency Package Values
NumEntries Integer The number of entries in the TStateDependency package including this ﬁeld.
Current value is 5.
(BYTE)The revision number of the TStateDependency package format. Current value
is 0.
(DWORD)The dependency domain number to which this T state entry belongs.
(DWORD)See Table 8.1 for supported T-state coordination types.

None
Package {
}
Package {
}
is 0.
(DWORD)The number of processors belonging to the domain for this logical processor’s
T-states. OSPM will not start performing power state transitions to a particular
T-state until this number of processors belonging to the same domain have been
detected and started.
Example
This is an example usage of the _TSD structure in a Processor structure in the namespace. The example represents
a two processor conﬁguration with three T-states per processor. For all T-states, there exists dependence between the
two processors, such that one processor transitioning to a particular T-state, causes the other processor to transition
to the same T-state. OSPM will be required to coordinate the T-state transitions between the two processors and can
initiate a transition on either processor to cause both to transition to the common target T-state.
6) // PBlkLen
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{ //Object List
{
Name (_TSS, Package()
{
0x64, // Frequency Percentage (100%, Throttling OFF state)
0x0, // Power
0x0, // Transition Latency
0x7, // Control THT_EN:0 THTL_DTY:111
0x0, // Status
}
0x58, // Frequency Percentage (87.5%)
0xF, // Control THT_EN:1 THTL_DTY:111
}
0x4B, // Frequency Percentage (75%)
0xE, // Control THT_EN:1 THTL_DTY:110
}
})
Name (_TSD, Package()
{
Package(){5, 0, 0, 0xFD, 2} // 5 entries, Revision 0, Domain 0,
// OSPM Coordinate, 2 Procs
}) // End of \_TSD object
Method (_TPC, 0) // Throttling Present Capabilities method
{
If (\_SB.AC)
{
Return(0) // All Throttle States are available foruse.
}
Else
{
Return(2) // Throttle States 0 an 1 won't be used.
}
} // End of \_TPC method
} // End of processor object list
8.4. Declaring Processors 514Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
// 32 bit wide IO space-based register at the
// <p_blk> address
{
{
}
}\'
}
})
{
{
{
}
Else
{
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}
8.4.4.5 _TDL (T-state Depth Limit)
This optional object evaluates to the _TSS entry number of the lowest power throttling state that OSPM may use.
_TDL enables the platform to limit the amount of performance reduction that OSPM may invoke using processor
throttling controls in an attempt to alleviate an adverse thermal condition. OSPM may choose the corresponding state
entry in the _TSS as indicated by the value returned by the _TDL object or a higher performance (lower numbered)
state entry in the _TSS down to and including the _TSS entry number returned by the _TPC object or the ﬁrst entry in
the table (if _TPC is not implemented). The value returned by the _TDL object must be greater than or equal to the
value returned by the _TPC object or the corresponding value to the last entry in the _TSS if _TPC is not implemented.
In the event of a conﬂict between the values returned by the evaluation of the _TDL and _TPC objects, OSPM gives
precedence to the _TPC object, limiting power consumption.
None
An Integer containing the Throttling Depth Limit _TSS entry number:
0 - throttling disabled.
1 - state 1 is the lowest power T-state available.
2 - state 2 is the lowest power T-state available.
. . .
n- state nis the lowest power T-state available.
In order for the platform to dynamically indicate the limit of performance reduction that is available for OSPM use,
Notify events on the processor object of type 0x82 will cause OSPM to reevaluate any _TDL object in the processor’s
object list. This allows AML code to notify OSPM when the number of supported throttling states may have changed
as a result of an asynchronous event. OSPM ignores _TDL Notify events on platforms that support P-states unless the
platform has limited OSPM’s use of P-states to the lowest power P-state. OSPM may choose to disregard any platform
conveyed T-state depth limits when the platform enables OSPM usage of other than the lowest power P-state.
8.4.5 Processor Performance Control
Processor performance control is implemented through three optional objects whose presence indicates to OSPM
that the platform and CPU are capable of supporting multiple performance states. The platform must supply all
three objects if processor performance control is implemented. The platform must expose processor performance
control objects for either all or none of its processors. The processor performance control objects deﬁne the supported
processor performance states, allow the processor to be placed in a speciﬁc performance state, and report the number
of performance states currently available on the system.
In a multiprocessing environment, all CPUs must support the same number of performance states and each processor
performance state must have identical performance and power-consumption parameters. Performance objects must be
present under each processor object in the system for OSPM to utilize this feature.
Processor performance control objects include the ‘_PCT’ package, ‘_PSS’ package, and the ‘_PPC’ method as de-
tailed below.
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8.4.5.1 _PCT (Performance Control)
This optional object declares an interface that allows OSPM to transition the processor into a performance state. OSPM
performs processor performance transitions by writing the performance state-speciﬁc control value to a Performance
Control Register (PERF_CTRL).
OSPM may select a processor performance state as indicated by the performance state value returned by the _PPC
method, or any lower power (higher numbered) state. The control value to write is contained in the corresponding
_PSS entry’s “Control” ﬁeld.
Success or failure of the processor performance transition is determined by reading a Performance Status Register
(PERF_STATUS) to determine the processor’s current performance state. If the transition was successful, the value
read from PERF_STATUS will match the “Status” ﬁeld in the _PSS entry that corresponds to the desired processor
performance state.
None
Package
{
}
Table 8.20: _PCT Package Values
Element Object
TypeDescription
Control Reg-
isterBuffer Contains a Resource Descriptor with a single Register() descriptor that describes the
performance control register.
Status Regis-
terBuffer Contains a Resource Descriptor with a single Register() descriptor that describes the
performance status register.
Example
Name (_PCT, Package()
{
ResourceTemplate(){Perf_Ctrl_Register}, //Generic Register Descriptor
ResourceTemplate(){Perf_Status_Register} //Generic Register Descriptor
}) // End of \_PCT
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8.4.5.2 _PSS (Performance Supported States)
This optional object indicates to OSPM the number of supported processor performance states that any given system

None
Package
{
}
Example
{
can support. This object evaluates to a packaged list of information about available performance states including inter-
nal CPU core frequency, typical power dissipation, control register values needed to transition between performance
states, and status register values that allow OSPM to verify performance transition status after any OS-initiated transi-
tion change request. The list is sorted in descending order by typical power dissipation. As a result, the zeroth entry
describes the highest performance state and the ‘nth’ entry describes the lowest performance state.
None
A variable-length Package containing a list of Pstate sub-packages as described below
Package {
PState [0] // Package - Performance state 0
....
PState [n] // Package - Performance state n
}
Each Pstate sub-Package contains the elements described below:
Package {
CoreFrequency // Integer (DWORD)
BusMasterLatency // Integer (DWORD)
}
Table 8.21: PState Package Values
Core Frequency Integer (DWORD) Indicates the core CPU operating frequency (in MHz).
Power Integer (DWORD) Indicates the performance state’s maximum power dissipation (in
milliwatts).
Latency Integer (DWORD) Indicates the worst-case latency in microseconds that the CPU is
unavailable during a transition from any performance state to this
Bus Master Latency Integer (DWORD) Indicates the worst-case latency in microseconds that Bus Masters
are prevented from accessing memory during a transition from any
performance state to this performance state.
Control Integer (DWORD) Indicates the value to be written to the Performance Control Register
(PERF_CTRL) in order to initiate a transition to the performance
state.
Status Integer (DWORD) Indicates the value that OSPM will compare to a value read from
the Performance Status Register (PERF_STATUS) to ensure that the
transition to the performance state was successful. OSPM may al-
ways place the CPU in the lowest power state, but additional states
are only available when indicated by the _PPC method.
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8.4.5.3 _PPC (Performance Present Capabilities)
This optional object is a method that dynamically indicates to OSPM the number of performance states currently sup-
ported by the platform. This method returns a number that indicates the _PSS entry number of the highest performance
state that OSPM can use at a given time. OSPM may choose the corresponding state entry in the _PSS as indicated by
the value returned by the _PPC method or any lower power (higher numbered) state entry in the _PSS.
None
An Integer containing the range of states supported
0 - States 0 through nth state are available (all states available)
1 - States 1 through nth state are available
2 - States 2 through nth state are available
. . .
n- State nis available only
In order to support dynamic changes of _PPC object, Notify events on the processor object are allowed. Notify events
of type 0x80 will cause OSPM to reevaluate any _PPC objects residing under the particular processor object notiﬁed.
This allows AML code to notify OSPM when the number of supported states may have changed as a result of an
asynchronous event (AC insertion/removal, docked, undocked, and so on).
8.4.5.3.1 OSPM _OST Evaluation
When processing of the _PPC object evaluation completes, OSPM evaluates the _OST object, if present under the
Processor device, to convey _PPC evaluation status to the platform. _OST arguments speciﬁc to _PPC evaluation are
described below.
Arg0 - Source Event (Integer) : 0x80 Arg1 - Status Code (Integer) : see below
None
Arg1 - Status Code 0: Success - OSPM is now using the performance states speciﬁed 1: Failure - OSPM
has not changed the number of performance states in use.
8.4.5.4 Processor Performance Control Example
This is an example of processor performance control objects in a processor object list.
In this example, a uniprocessor platform that has processor performance capabilities with support for three perfor-
mance states as follows:
1. 500 MHz (8.2W) supported at any time
2. 600 MHz (14.9W) supported only when AC powered
3. 650 MHz (21.5W) supported only when docked
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It takes no more than 500 microseconds to transition from one performance state to any other performance state.
During a performance transition, bus masters are unable to access memory for a maximum of 300 microseconds.
The PERF_CTRL and PERF_STATUS registers are implemented as Functional Fixed Hardware.
The following ASL objects are implemented within the system:
_SB.DOCK: Evaluates to 1 if system is docked, zero otherwise.
_SB.AC: Evaluates to 1 if AC is connected, zero otherwise.
{
Name(_PCT, Package () // Performance Control object
{
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, // PERF_CTRL
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} // PERF_STATUS
}) // End of _PCT object
Name (_PSS, Package()
{
Package(){650, 21500, 500, 300, 0x00, 0x08}, // Performance State zero (P0)
Package(){600, 14900, 500, 300, 0x01, 0x05}, // Performance State one (P1)
Package(){500, 8200, 500, 300, 0x02, 0x06} // Performance State two (P2)
}) // End of _PSS object
Method (_PPC, 0) // Performance Present Capabilities method
{
If (\_SB.DOCK)
{
Return(0) // All _PSS states available (650, 600, 500).
}
{
Return(1) // States 1 and2 available (600, 500).
}
Else
{
Return(2) // State 2 available (500)
}
} // End of _PPC method
The platform will issue a Notify(_SB.CPU0, 0x80) to inform OSPM to re-evaluate this object when the number of
available processor performance states changes.
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8.4.5.5 _PSD (P-State Dependency)
This optional object provides performance control, P-state or CPPC, logical processor dependency information to
OSPM. The _PSD object evaluates to a packaged list containing a single entry that expresses the performance control
dependency among a set of logical processors.
None
A Package with a single entry consisting of a P-state dependency Package as described below.
Package {
PStateDependency[0] // Package
}
The PStateDependency sub-Package contains the elements described below:
Package {
}
Table 8.22: P-State Dependency Package Values
NumEntries Integer The number of entries in the PStateDependency package including this ﬁeld.
(BYTE)The revision number of the PStateDependency package format. Current value
is 0.
(DWORD)The dependency domain number to which this P state entry belongs.
(DWORD)See Table 8.1 for supported P-state coordination types.
P-states. OSPM will not start performing power state transitions to a particular
P-state until this number of processors belonging to the same domain have been
Example
This is an example usage of the _PSD structure in a Processor structure in the namespace. The example represents
a two processor conﬁguration with three performance states per processor. For all performance states, there exists
dependence between the two processors, such that one processor transitioning to a particular performance state, causes
the other processor to transition to the same performance state. OSPM will be required to coordinate the P-state
transitions between the two processors and can initiate a transition on either processor to cause both to transition to
the common target P-state.
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{
{
}) // End of \_PCT object
{

{
{
{
}) // End of \_PSS object
{
} // End of \_PPC method
Name (_PSD, Package()
{
Package(){5, 0, 0, 0xFD, 2} // 5 entries, Revision 0), Domain 0, OSPM
// Coordinate, Initiate on any Proc, 2 Procs
}) // End of \_PSD object
{
{
{
{
{
Package(){5, 0, 0, 0xFD, 2} // 5 entries, Revision 0, Domain 0, OSPM
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8.4.5.6 _PDL (P-state Depth Limit)
This optional object evaluates to the _PSS entry number of the lowest performance P-state that OSPM may use when
performing passive thermal control. OSPM may choose the corresponding state entry in the _PSS as indicated by
the value returned by the _PDL object or a higher performance (lower numbered) state entry in the _PSS down to
and including the _PSS entry number returned by the _PPC object or the ﬁrst entry in the table (if _PPC is not
implemented). The value returned by the _PDL object must be greater than or equal to the value returned by the _PPC
object or the corresponding value to the last entry in the _PSS if _PPC is not implemented. In the event of a conﬂict
between the values returned by the evaluation of the _PDL and _PPC objects, OSPM gives precedence to the _PPC
object, limiting power consumption.
None
An Integer containing the P-state Depth Limit _PSS entry number:
0 - P0 is the only P-state available for OSPM use
1 - state 1 is the lowest power P-state available
2 - state 2 is the lowest power P-state available
. . .
n- state nis the lowest power P-state available
In order for the platform to dynamically indicate a change in the P-state depth limit, Notify events on the processor ob-
ject of type 0x80 will cause OSPM to reevaluate any _PDL object in the processor’s object list. This allows AML code
to notify OSPM when the number of supported performance states may have changed as a result of an asynchronous
event.\
8.4.6 Collaborative Processor Performance Control
Collaborative processor performance control deﬁnes an abstracted and ﬂexible mechanism for OSPM to collaborate
with an entity in the platform to manage the performance of a logical processor. In this scheme, the platform entity
is responsible for creating and maintaining a performance deﬁnition that backs a continuous, abstract, unit-less per-
formance scale. During runtime, OSPM requests desired performance on this abstract scale and the platform entity
is responsible for translating the OSPM performance requests into actual hardware performance states. The platform
may also support the ability to autonomously select a performance level appropriate to the current workload. In this
case, OSPM conveys information to the platform that guides the platform’s performance level selection.
Prior processor performance controls (P-states and T-states) have described their effect on processor performance in
terms of processor frequency. While processor frequency is a rough approximation of the speed at which the processor
completes work, workload performance isn’t guaranteed to scale with frequency. Therefore, rather than prescribe a
speciﬁc metric for processor performance, Collaborative Processor Performance Control leaves the deﬁnition of the
exact performance metric to the platform. The platform may choose to use a single metric such as processor frequency,
or it may choose to blend multiple hardware metrics to create a synthetic measure of performance. In this way the
platform is free to deliver the OSPM requested performance level without necessarily delivering a speciﬁc processor
frequency. OSPM must make no assumption about the exact meaning of the performance values presented by the
platform, or how they may correlate to speciﬁc hardware metrics like processor frequency.
Platforms must use the same performance scale for all processors in the system. On platforms with heterogeneous
processors, the performance characteristics of all processors may not be identical. In this case, the platform must
synthesize a performance scale that adjusts for differences in processors, such that any two processors running the same
workload at the same performance level will complete in approximately the same time. The platform should expose
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different capabilities for different classes of processors, so as to accurately reﬂect the performance characteristics of
each processor.
The control mechanisms are abstracted by the _CPC object method, which describes how to control and monitor pro-
cessor performance in a generic manner. The register methods may be implemented in the Platform Communications
Channel (PCC) interface (see Platform Communications Channel (PCC) ). This provides sufﬁcient ﬂexibility that the
entity OSPM communicates with may be the processor itself, the platform chipset, or a separate entity (e.g., a BMC).
In order to provide backward compatibility with existing tools that report processor performance as frequencies, the
_CPC object can optionally provide processor frequency range values for use by the OS. If these frequency values
are provided, the restrictions on _CPC information usage still remain: the OSPM must make no assumption about the
exact meaning of the performance values presented by the platform, and all functional decisions and interaction with
the platform still happen using the abstract performance scale. The frequency values are only contained in the _CPC
object to allow the OS to present performance data in a simple frequency range, when frequency is not discoverable
from the platform via another mechanism.
8.4.6.1 _CPC (Continuous Performance Control)
This optional object declares an interface that allows OSPM to transition the processor into a performance state based
on a continuous range of allowable values. OSPM writes the desired performance value to the Desired Performance
Register, and the platform maps the desired performance to an internal performance state.. If supported by the platform,
OSPM may alternatively enable autonomous performance level selection while specifying minimum and maximum
performance requirements.
Optional _CPC package ﬁelds that are not supported by the platform should be encoded as follows:
• Integer ﬁelds: Integer 0
• Register ﬁelds: the following NULL register descriptor should be used:
None
A Package containing the performance control information.
The performance control package contains the elements described below:
Package
{
NumEntries, // Integer
Revision, // Integer
HighestPerformance, // Integer orBuffer (Resource Descriptor)
NominalPerformance, // Integer orBuffer (Resource Descriptor)
LowestNonlinearPerformance, // Integer orBuffer (Resource Descriptor)
LowestPerformance, // Integer orBuffer (Resource Descriptor)
GuaranteedPerformanceRegister, // Buffer (Resource Descriptor)
DesiredPerformanceRegister , // Buffer (Resource Descriptor)
MinimumPerformanceRegister , // Buffer (Resource Descriptor)
MaximumPerformanceRegister , // Buffer (Resource Descriptor)
PerformanceReductionToleranceRegister, // Buffer (Resource Descriptor)
TimeWindowRegister, // Buffer (Resource Descriptor)
CounterWraparoundTime, // Integer orBuffer (Resource Descriptor)
ReferencePerformanceCounterRegister, // Buffer (Resource Descriptor)
DeliveredPerformanceCounterRegister, // Buffer (Resource Descriptor)
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PerformanceLimitedRegister, // Buffer (Resource Descriptor)
CPPCEnableRegister // Buffer (Resource Descriptor)
AutonomousSelectionEnable, // Integer orBuffer (Resource Descriptor)
AutonomousActivityWindowRegister, // Buffer (Resource Descriptor)
EnergyPerformancePreferenceRegister, // Buffer (Resource Descriptor)
ReferencePerformance // Integer orBuffer (Resource Descriptor)
LowestFrequency, // Integer orBuffer (Resource Descriptor)

NominalFrequency // Integer orBuffer (Resource Descriptor)
}
Table 8.23: Continuous Performance Control Package Values
NumEntries Integer The number of entries in the _CPC package, including
this one. Current value is 23.
Revision Integer (BYTE) The revision number of the _CPC package format. Cur-
rent value is 3.
Highest Performance Integer (DWORD)
or BufferIndicates the highest level of performance the processor
is theoretically capable of achieving, given ideal oper-
ating conditions. If this element is an Integer, OSPM
reads the integer value directly. If this element is a
Buffer, it must contain a Resource Descriptor with a sin-
gle Register() to read the value from.
Nominal Performance Integer (DWORD)
or BufferIndicates the highest sustained performance level of the
processor. If this element is an Integer, OSPM reads the
integer value directly. If this element is a Buffer, it must
contain a Resource Descriptor with a single Register()
to read the value from.
Lowest Nonlinear Performance Integer (DWORD)
or BufferIndicates the lowest performance level of the processor
with non-linear power savings. If this element is an In-
teger, OSPM reads the integer value directly. If this ele-
ment is a Buffer, it must contain a Resource Descriptor
with a single Register() to read the value from.
Lowest Performance Integer (DWORD)
or BufferIndicates the lowest performance level of the processor.
If this element is an Integer, OSPM reads the integer
value directly. If this element is a Buffer, it must contain
a Resource Descriptor with a single Register() to read
the value from.
Guaranteed Performance Regis-
terBuffer Optional. If supported, contains a resource descriptor
with a single Register() descriptor that describes the reg-
ister to read the current guaranteed performance from.
See the section “Performance Limiting” for more de-
tails.
Desired Performance Register Buffer Contains a resource descriptor with a single Register()
descriptor that describes the register to write the de-
sired performance level. This register is optional when
OSPM indicates support for CPPC2 in the platform-
wide _OSC capabilities and the Autonomous Selection
Enable register is Integer 1
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Minimum Performance Register Buffer Optional. If supported, contains a resource descriptor
ister to write the minimum allowable performance level
to. The value 0 is equivalent to Lowest Performance (no
limit).
Maximum Performance Regis-
ister to write the maximum allowable performance level
to. All 1s is equivalent to Highest Performance (no
limit).
Performance Reduction Toler-
ance RegisterBuffer Optional. If supported, contains a resource descriptor
ister to write the performance reduction tolerance.
Time Window Register Buffer Optional. If supported, contains a resource descriptor
ister to write the nominal length of time (in ms) be-
tween successive reads of the platform’s delivered per-
formance register. See the section “Time Window Reg-
ister” for more details.
Counter Wraparound Time Integer (DWORD)
or BufferOptional. If supported, indicates the minimum time to
counter wraparound, in seconds. If this element is an
Integer, OSPM reads the integer value directly. If this
element is a Buffer (and supported), it must contain a
Resource Descriptor with a single Register() to read the
value from.
Reference Performance Counter
RegisterBuffer Contains a resource descriptor with a single Register()
descriptor that describes the register to read a counter
that accumulates at a rate proportional the reference per-
formance of the processor.
Delivered Performance Counter
that accumulates at a rate proportional to the delivered
performance of the processor.
Performance Limited Register Buffer Contains a resource descriptor with a single Register()
descriptor that describes the register to read to determine
if performance was limited. A nonzero value indicates
performance was limited. This register is sticky, and
will remain set until reset or OSPM clears it by writ-
ing 0. See the section “Performance Limiting” for more
details.
CPPC EnableRegister Buffer Optional. If supported, contains a resource descriptor
with a single Register() descriptor that describes a reg-
ister to which OSPM writes a One to enable CPPC on
this processor. Before this register is set, the proces-
sor will be controlled by legacy mechanisms (ACPI P-
states, ﬁrmware, etc.).
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Autonomous Selection Enable Integer (DWORD)
or BufferOptional. If supported, contains a resource descriptor
ister to which OSPM writes a One to enable autonomous
performance level selection. Platforms that exclusively
support Autonomous Selection must populate this ﬁeld
as an Integer with a value of 1.
AutonomousActivity-
WindowRegisterBuffer Optional. If supported, contains a resource descrip-
tor with a single Register() descriptor that describes a
register to which OSPM writes a time value that indi-
cates a moving utilization sensitivity window for the au-
tonomous selection policy.
EnergyPerformance-
PreferenceRegisterBuffer Optional. If supported, contains a resource descriptor
ister to which OSPM writes a value to control the En-
ergy vs. Performance preference of the platform’s en-
ergy efﬁciency and performance optimization policies
when Autonomous Selection is enabled
Reference Performance Integer (DWORD)
or BufferOptional. If supported, indicates the performance level
at which the Reference Performance Counter accumu-
lates. If not supported, The Reference Performance
Counter accumulates at the Nominal performance level.
value directly. If this element is a Buffer (and sup-
ported), it must contain a Resource Descriptor with a
single Register() to read the value from
Lowest Frequency Integer (DWORD)
or BufferOptional. If supported, indicates the lowest frequency
for this processor in MHz. It should correspond roughly
to the Lowest Performance value, but is not guaranteed
to have any precise correlation. This value should only
be used for the purpose of reporting processor perfor-
mance in absolute frequency rather than on an abstract
scale, and not for functional decisions or platform com-
munication. If this element is an Integer, OSPM reads
the integer value directly. If this element is a Buffer (and
supported), it must contain a Resource Descriptor with
a single Register() to read the value from.
Nominal Frequency Integer (DWORD)
or BufferOptional. If supported, indicates the nominal frequency
to the Nominal Performance value, but is not guaranteed
The _CPC object provides OSPM with platform-speciﬁc performance capabilities / thresholds and control registers that
OSPM uses to control the platform’s processor performance settings. These are described in the following sections.
While the platform may specify register sizes within an allowable range, the size of the capabilities / thresholds
registers must be compatible with the size of the control registers. If the platform supports CPPC, the _CPC object
8.4. Declaring Processors 527Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
must exist under all processor objects. That is, OSPM is not expected to support mixed mode (CPPC & legacy PSS,
_PCT, _PPC) operation.
Starting with ACPI Speciﬁcation 6.2, all _CPC registers can be in PCC, System Memory, System IO, or Functional
Fixed Hardware address spaces. OSPM support for this more ﬂexible register space scheme is indicated by the “Flex-
ible Address Space for CPPC Registers” _OSC bit.

8.4.6.1.1 Performance Capabilities / Thresholds
Performance-based controls operate on a continuous range of processor performance levels, not discrete processor
states. As a result, platform capabilities and OSPM requests are speciﬁed in terms of performance thresholds. Plat-
form performance thresholds outlines the static performance thresholds of the platform and the dynamic guaranteed
performance threshold.
Fig. 8.10: Platform performance thresholds
Note: Not all performance levels need be unique. A platform’s nominal performance level may also be its highest
performance level, for example.*
8.4.6.1.1.1 Highest Performance
Register orDWORD Attribute: Read
Size: 8-32 bits
Highest performance is the absolute maximum performance an individual processor may reach, assuming ideal condi-
tions. This performance level may not be sustainable for long durations, and may only be achievable if other platform
components are in a speciﬁc state; for example, it may require other processors be in an idle state.
8.4. Declaring Processors 528Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Notify events of type 0x85 to the processor device object cause OSPM to re-evaluate the Highest Performance Register,
but only when it is encoded as a buffer. Note: OSPM will not re-evaluate the _CPC object as a result of the notiﬁcation.
8.4.6.1.1.2 Nominal Performance
Nominal Performance is the maximum sustained performance level of the processor, assuming ideal operating condi-
tions. In absence of an external constraint (power, thermal, etc.) this is the performance level the platform is expected
to be able to maintain continuously. All processors are expected to be able to sustain their nominal performance state
8.4.6.1.1.3 Reference Performance
Optional Register orDWORD Attribute: Read
If supported by the platform, Reference Performance is the rate at which the Reference Performance Counter incre-
ments. If not implemented (or zero), the Reference Performance Counter increments at a rate corresponding to the
Nominal Performance level.
8.4.6.1.1.4 Lowest Nonlinear Performance
Lowest Nonlinear Performance is the lowest performance level at which nonlinear power savings are achieved, for
example, due to the combined effects of voltage and frequency scaling. Above this threshold, lower performance
levels should be generally more energy efﬁcient than higher performance levels. In traditional terms, this represents
the P-state range of performance levels.
This register effectively conveys the most efﬁcient performance level to OSPM.
8.4.6.1.1.5 Lowest Performance
Lowest Performance is the absolute lowest performance level of the platform. Selecting a performance level lower than
the lowest nonlinear performance level may actually cause an efﬁciency penalty, but should reduce the instantaneous
power consumption of the processor. In traditional terms, this represents the T-state range of performance levels.
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8.4.6.1.1.6 Guaranteed Performance Register
Optional Attribute: Read
Guaranteed Performance Register conveys to OSPM a Guaranteed Performance level, which is the current maximum
sustained performance level of a processor, taking into account all known external constraints (power budgeting, ther-
mal constraints, AC vs DC power source, etc.). All processors are expected to be able to sustain their guaranteed
performance levels simultaneously. The guaranteed performance level is required to fall in the range [Lowest Perfor-
mance, Nominal performance], inclusive.
If this register is not implemented, OSPM assumes guaranteed performance is always equal to nominal performance.
Notify events of type 0x83 to the processor device object will cause OSPM to re-evaluate the Guaranteed Performance
Register. Changes to guaranteed performance should not be more frequent than once per second. If the platform is
not able to guarantee a given performance level for a sustained period of time (greater than one second), it should
guarantee a lower performance level and opportunistically enter the higher performance level as requested by OSPM
and allowed by current operating conditions.
8.4.6.1.1.7 Lowest Frequency and Nominal Frequency
If supported by the platform, Lowest Frequency and Nominal Frequency values convey are the lowest and nominal
CPU frequencies of the platform, respectively, in megahertz (MHz). They should correspond roughly to Lowest Per-
formance and Nominal Performance on the CPPC abstract performance scale but precise correlation is not guaranteed.
SeeLowest Performance andNominal Performance for more details.
These values should not be used for functional decision making or platform communication which are based on the
CPPC abstract performance scale. They are only intended to enable CPPC platforms to be backwards compatible with
OSs that report performance as CPU frequencies. The OS should use Lowest Frequency/Performance and Nominal
Frequency/Performance as anchor points to create a linear mapping of CPPC abstract performance to CPU frequency,
interpolating between Lowest and Nominal, and extrapolating from Nominal to Highest. Note that this mapping is not
guaranteed to be accurate since CPPC abstract performance is not required to be based purely on CPU frequency, but
it is better than no data if the OS must report performance as CPU frequency. Platforms should provide these values
when they must work with OSs which need to report CPU frequency, and there is no alternate mechanism to discover
this information.
8.4.6.1.2 Performance Controls
Under CPPC, OSPM has several performance settings it may use in conjunction to control/inﬂuence the performance
of the platform. These control inputs are outlined in the following ﬁgure.
OSPM may select any performance value within the continuous range of values supported by the platform. Internally,
the platform may implement a small number of discrete performance states and may not be capable of operating at
the exact performance level desired by OSPM. If a platform-internal state does not exist that matches OSPM’s desired
performance level, the platform should round desired performance as follows:
• If OSPM has selected a desired performance level greater than or equal to guaranteed performance, the platform
may round up or down. The result of rounding must not be less than guaranteed performance.
• If OSPM has selected a desired performance level less than guaranteed performance and a maximum perfor-
mance level not less than guaranteed performance, the platform must round up.
8.4. Declaring Processors 530Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 8.11: OSPM performance controls
If OSPM has selected both desired performance level and maximum performance level less than guaranteed perfor-
mance, the platform must round up if rounding up does not violate the maximum performance level. Otherwise, round
down. OSPM must tolerate the platform rounding down if it chooses to set the maximum performance level less than
guaranteed performance.This approach favors performance, except in the case where performance has been limited
due to a platform or OSPM constraint.
When Autonomous Selection is enabled, OSPM limits the processor’s performance selection by writing appropriate
constraining values to the Minimum and Maximum Performance registers. Setting Minimum and Maximum to the
same value effectively disables Autonomous selection.
Note: When processors are within the same dependency domain, Maximum performance may only be actually limited
when allowed by hardware coordination.
8.4.6.1.2.1 Maximum Performance Register
Optional Attribute: Read/Write
Maximum Performance Register conveys the maximum performance level at which the platform may run. Maximum
performance may be set to any performance value in the range [Lowest Performance, Highest Performance], inclusive.
The value written to the Maximum Performance Register conveys a request to limit maximum performance for the
purpose of energy efﬁciency or thermal control and the platform limits its performance accordingly as possible. How-
ever, the platform may exceed the requested limit in the event it is necessitated by internal package optimization. For
Example, hardware coordination among multiple logical processors with interdependencies.
OSPM’s use of this register to limit performance for the purpose of thermal control must comprehend multiple logical
processors with interdependencies. i.e. the same value must be written to all processors within a domain to achieve
the desired result.

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The platform must implement either both the Minimum Performance and Maximum Performance registers or neither
register. If neither register is implemented and Autonomous Selection is disabled, the platform must always deliver
the desired performance.
8.4.6.1.2.2 Minimum Performance Register
The Minimum Performance Register allows OSPM to convey the minimum performance level at which the platform
may run. Minimum performance may be set to any performance value in the range [Lowest Performance, Highest Per-
formance], inclusive but must be set to a value that is less than or equal to that speciﬁed by the Maximum Performance
Register.
In the presence of a physical constraint, for example a thermal excursion, the platform may not be able to successfully
maintain minimum performance in accordance with that set via the Minimum Performance Register. In this case, the
platform issues a Notify event of type 0x84 to the processor device object and sets the Minimum_Excursion bit within
the Performance Limited Register.
8.4.6.1.2.3 Desired Performance Register
Optional Attribute (depending on Autonomous Selection support): Read/Write
When Autonomous Selection is disabled, the Desired Performance Register is required and conveys the performance
level OSPM is requesting from the platform. Desired performance may be set to any performance value in the range
[Minimum Performance, Maximum Performance], inclusive. Desired performance may take one of two meanings,
depending on whether the desired performance is above or below the guaranteed performance level.
• Below the guaranteed performance level, desired performance expresses the average performance level the
platform must provide subject to the Performance Reduction Tolerance.
• Above the guaranteed performance level, the platform must provide the guaranteed performance level. The
platform should attempt to provide up to the desired performance level, if current operating conditions allow for
it, but it is not required to do so
When Autonomous Selection is enabled, it is not necessary for OSPM to assess processor workload performance
demand and convey a corresponding performance delivery request to the platform via the Desired Register. If the
Desired Performance Register exists, OSPM may provide an explicit performance requirement hint to the platform by
writing a non-zero value. In this case, the delivered performance is not bounded by the Performance Reduction Tol-
erance Register, however, OSPM can inﬂuence the delivered performance by writing appropriate values to the Energy
Performance Preference Register. Writing a zero value to the Desired Performance Register or the non-existence of
the Desired Performance Register causes the platform to autonomously select a performance level appropriate to the
current workload.
Note: The Desired Performance Register is optional only when OPSM indicates support for CPPC2 in the platform-
wide _OSC capabilities and the Autonomous Selection Enable ﬁeld is encoded as an Integer with a value of 1.*
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8.4.6.1.2.4 Performance Reduction Tolerance Register
The Performance Reduction Tolerance Register is used by OSPM to convey the deviation below the Desired Per-
formance that is tolerable. It is expressed by OSPM as an absolute value on the performance scale. Performance
Tolerance must be less than or equal to the Desired Performance. If the platform supports the Time Window Register,
the Performance Reduction Tolerance conveys the minimal performance value that may be delivered on average over
the Time Window. If this register is not implemented, the platform must assume Performance Reduction Tolerance =
Desired Performance.
When Autonomous Selection is enabled, values written to the Performance Reduction Tolerance Register are ignored.
8.4.6.1.2.5 Time Window Register
Units: milliseconds
When Autonomous Selection is not enabled, OSPM may write a value to the Time Window Register to indicate a time
window over which the platform must provide the desired performance level (subject to the Performance Reduction
Tolerance). OSPM sets the time window when electing a new desired performance The time window represents the
minimum time duration for OSPM’s evaluation of the platform’s delivered performance (see Performance Counters
“Performance Counters” for details on how OSPM computes delivered performance). If OSPM evaluates delivered
performance over an interval smaller than the speciﬁed time window, it has no expectations of the performance deliv-
ered by the platform. For any evaluation interval equal to or greater than the time window, the platform must deliver
the OSPM desired performance within the speciﬁed tolerance bound.
If OSPM speciﬁes a time window of zero or if the platform does not support the time window register, the platform
must deliver performance within the bounds of Performance Reduction Tolerance irrespective of the duration of the
evaluation interval.
When Autonomous Selection is enabled, values written to the Time Window Register are ignored. Reads of the Time
Window register indicate minimum length of time (in ms) between successive reads of the platform’s performance
counters. If the Time Window register is not supported then there is no minimum time requirement between successive
reads of the platform’s performance counters.
8.4.6.1.3 Performance Feedback
The platform provides performance feedback via set of performance counters, and a performance limited indicator.
8.4.6.1.3.1 Performance Counters
To determine the actual performance level delivered over time, OSPM may read a set of performance counters from
the Reference Performance Counter Register and the Delivered Performance Counter Register.
OSPM calculates the delivered performance over a given time period by taking a beginning and ending snapshot of
both the reference and delivered performance counters, and calculating:
The delivered performance should always fall in the range [Lowest Performance, Highest Performance], inclusive.
OSPM may use the delivered performance counters as a feedback mechanism to reﬁne the desired performance state
it selects.
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When Autonomous Selection is not enabled, there are constraints that govern how and when the performance deliv-
ered by the platform may deviate from the OSPM Desired Performance. Corresponding to OSPM setting a Desired
Performance: at any time after that, the following constraints on delivered performance apply
• Delivered performance can be higher than the OSPM requested desired performance if the platform is able to
deliver the higher performance at same or lower energy than if it were delivering the desired performance.
• Delivered performance may be higher or lower than the OSPM desired performance if the platform has dis-
crete performance states and needed to round down performance to the nearest supported performance level in
accordance to the algorithm prescribed in the OSPM controls section.
• Delivered performance may be lower than the OSPM desired performance if the platform’s efﬁciency optimiza-
tions caused the delivered performance to be less than desired performance. However, the delivered performance
should never be lower than the OSPM speciﬁed Performance Reduction Tolerance. The Performance Reduction
Tolerance provides a bound to the platform on how aggressive it can be when optimizing performance delivery.
The platform should not perform any optimization that would cause delivered performance to be lower than the
OSPM speciﬁed Performance Reduction Tolerance.
Reference Performance Counter Register
Attribute: Read
Size: 32 or64 bits
The Reference Performance Counter Register counts at a ﬁxed rate any time the processor is active. It is not affected by
changes to Desired Performance, processor throttling, etc. If Reference Performance is supported, the Reference Per-
formance Counter accumulates at a rate corresponding to the Reference Performance level. Otherwise, the Reference
Performance Counter accumulates at the Nominal performance level.
Delivered Performance Counter Register :
The Delivered Performance Counter Register increments any time the processor is active, at a rate proportional to the

current performance level, taking into account changes to Desired Performance. When the processor is operating at
its reference performance level, the delivered performance counter must increment at the same rate as the reference
performance counter.
Counter Wraparound Time :
Units: seconds
Counter Wraparound Time provides a means for the platform to specify a rollover time for the Reference/Delivered
performance counters. If greater than this time period elapses between OSPM querying the feedback counters, the
counters may wrap without OSPM being able to detect that they have done so.
If not implemented (or zero), the performance counters are assumed to never wrap during the lifetime of the platform.
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8.4.6.1.3.2 Performance Limited Register
Size: >=2 bit(s)
In the event that the platform constrains the delivered performance to less than the minimum performance or the desired
performance (or, less than the guaranteed performance, if desired performance is greater than guaranteed performance)
due to an unpredictable event, the platform sets the performance limited indicator to a non-zero value. This indicates to
OSPM that an unpredictable event has limited processor performance, and the delivered performance may be less than
desired / minimum performance. If the platform does not support signaling performance limited events, this register
is permitted to always return zero when read.
Table 8.24: Performance Limited Register Status Bits
0 Desired_Excursion Set when Delivered Performance has been constrained to less than Desired
Performance (or, less than the guaranteed performance, if desired perfor-
mance is greater than guaranteed performance). This bit is not utilized when
Autonomous Selection is enabled.
1 Minimum_Excursion Set when Delivered Performance has been constrained to less than Mini-
mum Performance
2-n Reserved Reserved
Bits within the Performance Limited Register are sticky, and will remain non-zero until OSPM clears the bit. The
platform should only issue a Notify when Minimum Excursion transitions from 0 to 1 to avoid repeated events when
there is sustained or recurring limiting but OSPM has not cleared the previous indication.
Note: All accesses to the Performance Limited Register must be made using interlocked operations, by both accessing
entities.*
The performance limited register should only be used to report short term, unpredictable events (e.g., PROCHOT
being asserted). If the platform is capable of identifying longer term, predictable events that limit processor perfor-
mance, it should use the guaranteed performance register to notify OSPM of this limitation. Changes to guaranteed
performance should not be more frequent than once per second. If the platform is not able to guarantee a given per-
formance level for a sustained period of time (greater than one second), it should guarantee a lower performance level
and opportunistically enter the higher performance level as requested by OSPM and allowed by current operating
conditions.
8.4.6.1.4 CPPC Enable Register
Size: >=1 bit(s)
If supported by the platform, OSPM writes a one to this register to enable CPPC on this processor.
If not implemented, OSPM assumes the platform always has CPPC enabled.
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8.4.6.1.5 Autonomous Selection Enable Register
Optional Register orDWORD Attribute: Read/Write
If supported by the platform, OSPM writes a one to this register to enable Autonomous Performance Level Selection
on this processor. CPPC must be enabled via the CPPC Enable Register to enable Autonomous Performance Level
Selection. Platforms that exclusively support Autonomous Selection must populate this ﬁeld as an Integer with a value
of 1.
When Autonomous Selection is enabled, the platform is responsible for selecting performance states. OSPM is not
required to assess processor workload performance demand and convey a corresponding performance delivery request
to the platform via the Desired Performance Register.
8.4.6.1.6 Autonomous Activity Window Register
Size: 10 bit(s)
Units: Bits 06:00 - Significand,
Bits 09:07 - Exponent, Base_Time_Unit = 1E-6 seconds (1
˓→microsecond)
If supported by the platform, OSPM may write a time value (10^3-bit exp * 7-bit mantissa in 1µsec units: 1us to
1270 sec) to this ﬁeld to indicate a moving utilization sensitivity window to the platform’s autonomous selection
policy. Combined with the Energy Performance Preference Register value, the Activity Window inﬂuences the rate
of performance increase / decrease of the platform’s autonomous selection policy. OSPM writes a zero value to this
register to enable the platform to determine an appropriate Activity Window depending on the workload.
Writes to this register only have meaning when Autonomous Selection is enabled.
8.4.6.1.7 Energy Performance Preference Register
Size: 4-8 bit(s
If supported by the platform, OSPM may write a range of values from 0 (performance preference) to 0xFF (energy
efﬁciency preference) that inﬂuences the rate of performance increase /decrease and the result of the hardware’s energy
efﬁciency and performance optimization policies.This provides a means for OSPM to limit the energy efﬁciency im-
pact of the platform’s performance-related optimizations / control policy and the performance impact of the platform’s
energy efﬁciency-related optimizations / control policy.
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8.4.6.1.8 OSPM Control Policy
8.4.6.1.8.1 In-Band Thermal Control
A processor using performance controls may be listed in a thermal zone’s _PSL list. If it is and the thermal zone
engages passive cooling as a result of passing the _PSV threshold, OSPM will apply the 𝑃[%]to modify the value
in the desired performance register. Any time that passive cooling is engaged, OSPM must also set the maximum
performance register equal to the desired performance register, to enforce the platform does not exceed the desired
performance opportunistically.
Note: In System-on-Chip-based platforms where the SoC is comprised of multiple device components in addition to
the processor, OSPM’s use of the Desired and Maximum registers for thermal control may not produce an optimal
result because of SoC device interaction. The use of proprietary package level thermal controls (if they exist) may
produce more optimal results.
8.4.6.1.9 Using PCC Registers
If the PCC register space is used, then all PCC registers for all processors in the same performance domain (as deﬁned
by _PSD), must be deﬁned to be in the same subspace. If _PSD is not used, the restriction applies to all registers
within a given _CPC object.
OSPM will write registers by ﬁlling in the register value and issuing a PCC write command. It may also read static
registers, counters, and the performance limited register by issuing a read command (see Table 8.25).
To amortize the cost of PCC transactions, OSPM should read or write all PCC registers via a single read or write
command when possible.
Table 8.25: PCC Command Codes Used by Collaborative Processor
Performance Control
0x00 Read registers. Executed to request the platform update all registers for all enabled processors
with their current value.
0x01 Write registers. Executed to notify the platform one or more read/write registers for an enabled
processor has been updated.
8.4.6.1.10 Relationship to other ACPI-deﬁned Objects and Notiﬁcations
If _CPC is present, its use supersedes the use of the following existing ACPI objects:
• The P_BLK P_CNT register
• _PTC
• _TSS
• _TPC
• _TSD
• _TDL
• _PCT
• _PSS
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• _PPC
• _PDL
• Notify 0x80 on the processor device
• Notify 0x82 on the processor device
The _PSD object may be used to specify domain dependencies between processors. On a system with heterogeneous
processors, all processors within a single domain must have the same performance capabilities.
8.4.6.1.11 _CPC Implementation Example
This example shows a two processor implementation of the _CPC interface via the PCC interface, in PCC subspace
2. This implementation uses registers to describe the processor’s capabilities, and does not support the Minimum
Performance, Maximum Performance, or Time Window registers.
Processor (\_SB.CPU0, 1, 0, 0)
{
Name(_CPC, Package()
{
21, // NumEntries
2, // Revision
ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
// Highest Performance

• _PTC
• _TSS
• _TPC
• _TSD
• _TDL
• _PCT
• _PSS
• _PPC
• _PDL
{
{
ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
// Nominal Performance
ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
// Lowest Nonlinear Performance
ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
// Lowest Performance
ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
// Guaranteed Performance Register
ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
// Desired Performance Register
ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
// Minimum Performance Register
// Maximum Performance Register
// Performance Reduction Tolerance Register
// Time Window Register
ResourceTemplate(){Register(PCC, 8, 0, 0x11B, 2)},
// Counter Wraparound Time
ResourceTemplate(){Register(PCC, 32, 0, 0x114, 2)},
// Reference Performance Counter Register
ResourceTemplate(){Register(PCC, 32, 0, 0x116, 2)},
// Delivered Performance Counter Register
ResourceTemplate(){Register(PCC, 8, 0, 0x11A, 2)},
// Performance Limited Register
ResourceTemplate(){Register(PCC, 1, 0, 0x100, 2)},
// CPPC Enable Register
// Autonomous Selection Enable
// Autonomous Activity Window Register
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// Energy Performance Preference Register
ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}
// Reference Performance
})
}
Processor (\_SB.CPU1, 2, 0, 0)
{
{
ResourceTemplate(){Register(PCC, 32, 0, 0x220, 2)},
ResourceTemplate(){Register(PCC, 32, 0, 0x224, 2)},
ResourceTemplate(){Register(PCC, 32, 0, 0x228, 2)},
ResourceTemplate(){Register(PCC, 32, 0, 0x22C, 2)},
ResourceTemplate(){Register(PCC, 32, 0, 0x230, 2)},
ResourceTemplate(){Register(PCC, 32, 0, 0x210, 2)},
ResourceTemplate(){Register(PCC, 8, 0, 0x21B, 2)},
ResourceTemplate(){Register(PCC, 32, 0, 0x214, 2)},
ResourceTemplate(){Register(PCC, 32, 0, 0x216, 2)},
ResourceTemplate(){Register(PCC, 8, 0, 0x21A, 2)},
ResourceTemplate(){Register(PCC, 1, 0, 0x200, 2)},
})
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8.4.7 _PPE (Polling for Platform Errors)
This optional object, when present, is evaluated by OSPM to determine if the processor should be polled to retrieve
corrected platform error information. This object augments /overrides information provided in the CPEP, if supplied.
SeeCorrected Platform Error Polling Table (CPEP) .
None
An Integer containing the recommended polling interval in milliseconds.
0 - OSPM should not poll this processor.
Other values - OSPM should poll this processor at <= the speciﬁed interval.
OSPM evaluates the _PPE object during processor object initialization and Bus Check notiﬁcation processing.
8.5 Processor Aggregator Device
The following section describes the deﬁnition and operation of the optional Processor Aggregator device. The Proces-
sor Aggregator Device provides a control point that enables the platform to perform speciﬁc processor conﬁguration
and control that applies to all processors in the platform.
The Plug and Play ID of the Processor Aggregator Device is ACPI000C.
Table 8.26: Processor Aggregator Device Objects
_PUR Requests a number of logical processors to be placed in an idle state
8.5.1 Logical Processor Idling
In order to reduce the platform’s power consumption, the platform may direct OSPM to remove a logical processor
from the operating system scheduler’s list of processors where non-processor afﬁnitized work is dispatched. This
capability is known as Logical Processor Idling and provides a means to reduce platform power consumption without
undergoing processor ejection / insertion processing overhead. Interrupts directed to a logical processor and processor
afﬁnitized workloads will impede the effectiveness of logical processor idling in reducing power consumption as
OSPM is not expected to re-target this work when a logical processor is idled.
8.5.1.1 _PUR (Processor Utilization Request)
The _PUR object is an optional object that may be declared under the Processor Aggregator Device and provides a
means for the platform to indicate to OSPM the number of logical processors to be idled. OSPM evaluates the _PUR
object as a result of the processing of a Notify event on the Processor Aggregator device object of type 0x80.
None
A Package as described below.
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Package
{
RevisionID // Integer: Current value is1
NumProcessors // Integer
}
The NumProcessors package element conveys the number of logical processors that the platform wants OSPM to idle.
This number is an absolute value. OSPM increments or decrements the number of logical processors placed in the idle
state to equal the NumProcessors value as possible. A NumProcessors value of zero causes OSPM to place all logical
processor in the active state as possible.
OSPM uses internal logical processor to physical core and package topology knowledge to idle logical processors
successively in an order that maximizes power reduction beneﬁt from idling requests. For example, all SMT threads
constituting logical processors on a single processing core should be idled to allow the core to enter a low power state
before idling SMT threads constituting logical processors on another core.
8.5.2 OSPM _OST Evaluation
When processing of the _PUR object evaluation completes, OSPM evaluates the _OST object, if present under the
Processor Aggregator device, to convey _PUR evaluation status to the platform. _OST arguments speciﬁc to _PUR
evaluation are described below.
Arg0 - Source Event (Integer) : 0x80
Arg1 - Status Code (Integer) : see below
Arg2 - Idled Procs (Buffer) : see below
None
Arg1 - Status Code:
0 -success - OSPM idled the number of logical processors indicated by the value of Arg2
1: no action was performed
Arg2 - A 4-byte buffer that represents a DWORD that is the number of logical processors that are now
idled)
The platform may request a number of logical processors to be idled that exceeds the available number of logical
processors that can be idled from an OSPM context for the following reasons:
• The requested number is larger than the number of logical processors currently deﬁned.
• Not all the deﬁned logical processors were onlined by the OS (for example. for licensing reasons)
Logical processors critical to OS function (for example, the BSP) cannot be idled.
8.5. Processor Aggregator Device 541CHAPTER
NINE
ACPI-DEFINED DEVICES AND DEVICE-SPECIFIC OBJECTS
This chapter describes ACPI deﬁned devices and device-speciﬁc objects, plus the system status indicator objects
declared under the \_SI scope in the ACPI Namespace.
9.1 Device Object Name Collision
Devices containing both _HID and _CID may have device speciﬁc control methods pertaining to both the device ID
in the _HID and the device ID in the _CID. These device speciﬁc control methods are deﬁned by the device owner
(a standard body or a vendor or a group of vendor partners). Since these object names are not controlled by a central
authority, there is a likelihood that the names of objects will conﬂict between two deﬁning parties. The _DSM object
described in the next section solves this conﬂict.
9.1.1 _DSM (Device Speciﬁc Method)
This optional object is a control method that enables devices to provide device speciﬁc control functions that are
consumed by the device driver.

NINE
Arg1 - An Integer containing the Revision ID
Arg2 - An Integer containing the Function Index
Arg3 - A Package that contains function-speciﬁc arguments
If Function Index = 0, a Buffer containing a function index bitﬁeld. Otherwise, the return value and type
depends on the UUID and revision ID (see below).
Arg0: UUID - A Buffer containing the 16-byte UUID (see Universally Unique Identiﬁers (UUIDs) )
Arg1: Revision ID - the function’s revision. This revision is speciﬁc to the UUID.
Arg2: Function Index - Represents a speciﬁc function whose meaning is speciﬁc to the UUID and Revi-
sion ID. Function indices should start with 1. Function number zero is a query function (see the special
return code deﬁned below).
Arg3: Function Arguments - a package containing the parameters for the function speciﬁed by the UUID,
Revision ID and Function Index.
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Successive revisions of Function Arguments must be backward compatible with earlier revisions. New UUIDs may
also be created by OEMs and IHVs for custom devices and other interface or device governing bodies (e.g. the PCI
SIG), as long as the UUID is different from other published UUIDs. Only the issuer of a UUID can authorize a new
Function Index, Revision ID or Function Argument for that UUID.
If Function Index is zero, the return is a buffer containing one bit for each function index, starting with zero. Bit 0
indicates whether there is support for any functions other than function 0 for the speciﬁed UUID and Revision ID.
If set to zero, no functions are supported (other than function zero) for the speciﬁed UUID and Revision ID. If set
to one, at least one additional function is supported. For all other bits in the buffer, a bit is set to zero to indicate if
that function index is not supported for the speciﬁc UUID and Revision ID. (For example, bit 1 set to 0 indicates that
function index 1 is not supported for the speciﬁc UUID and Revision ID.)
If the bit representing a particular function index would lie outside of the buffer, it should be assumed to be 0 (that is,
not supported).
If Function Index is non-zero, the return is any data object. The type and meaning of the returned data object depends
on the UUID, Revision ID, Function Index, and Function Arguments.
Note: For backward compatibility _DSM requires that each Revision ID support all of the functions deﬁned by all
previous Revision IDs for the same UUID.*
Implementation Note
Since the purpose of the _DSM method is to avoid the namespace collision, the implementation of this method shall not
use any other method or data object which is not deﬁned in this speciﬁcation unless its driver and usage is completely
under the control of the platform vendor.
Example:
// _DSM - Device Specific Method
//
// Arg0: UUID Unique function identifier
// Arg1: Integer Revision Level
// Arg2: Integer Function Index (0 = Return Supported Functions)
// Arg3: Package Parameters
Function(_DSM,{IntObj,BuffObj},{BuffObj, IntObj, IntObj, PkgObj})
{
//
// Switch based on which unique function identifier was passed in
//
switch(Arg0)
{
//
// First function identifier
//
case(ToUUID("893f00a6-660c-494e-bcfd-3043f4fb67c0"))
{
switch(Arg2)
{
//
// Function 0: Return supported functions, based on revision
//
case(0)
{
switch(Arg1)
{
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// revision 0: functions 1-4 are supported
case(0) {return (Buffer() {0x1F})}
// revision 1: functions 1-5 are supported
case(1) {return (Buffer() {0x3F})}
}
// revision 2+: functions 1-7 are supported
return (Buffer() {0xFF})
}
//
// Function 1:
//
case(1)
{
... function 1 code ...
}
//
// Function 2:
//
case(2)
{
... function 2 code ...
Return(Buffer(){0x00})
}
case(3) { ... function 3 code ...}
case(4) { ... function 4 code ...}
case(5) { if (LLess(Arg1,1) BreakPoint; ... function 5 code ... }
case(6) { if (LLess(Arg1,2) BreakPoint; ... function 6 code ... )
case(7) { if (LLess(Arg1,3) BreakPoint; ... function 7 code ... )
default {BreakPoint }
}
}
//
// Second function identifier
//
case(ToUUID("107ededd-d381-4fd7-8da9-08e9a6c79644"))
{
//
// Function 0: Return supported functions (there is only one revision)
//
if (LEqual(Arg2,Zero))
return (Buffer() {0x3}) // only one function supported
//
// Function 1
//
if (LEqual(Arg2,One))
{
Return(Unicode("text"))
}
//
// Function 2+: Runtime Error
//
else
BreakPoint;
}
}
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//
// If not one of the UUIDs we recognize, then return a buffer
// with bit 0 set to 0 indicating no functions supported.
//
return(Buffer(){0})
}
9.2 \_SI System Indicators
ACPI provides an interface for a variety of simple and icon-style indicators on a system. All indicator controls are in
the \_SI portion of the namespace. The following table lists all deﬁned system indicators. (Notice that there are also
per-device indicators speciﬁed for battery devices).
Table 9.1: System Indicator Control Methods
_SST System status indicator
_MSG Messages waiting indicator
_BLT Battery Level Threshold
9.2.1 _SST (System Status)
This optional object is a control method that OSPM invokes to set the system status indicator as desired.
Arguments:(1)
Arg0 - An Integer containing the system status indicator identiﬁer:
0 - No system state indication. Indicator off
1 - Working
2 - Waking
3 - Sleeping. Used to indicate system state S1, S2, or S3
4 - Sleeping with context saved to non-volatile storage
None
9.2.2 _MSG (Message)
This control method sets the system’s message-waiting status indicator.
Arg0 - An Integer containing the number of waiting messages
None
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9.2.3 _BLT (Battery Level Threshold)
This optional control method is used by OSPM to indicate to the platform the user’s preference for various battery
level thresholds. This method allows platform battery indicators to be synchronized with OSPM provided battery
notiﬁcation levels. Note that if _BLT is implemented on a multi-battery system, it is required that the power unit for
all batteries must be the same (see Section 10.2 for more details on battery levels.
Arguments:(3)
Arg0 - An Integer containing the preferred threshold for the battery warning level
Arg1 - An Integer containing the preferred threshold for the battery low level
Arg2 - An Integer containing the preferred threshold for the battery wake level
None
The battery warning level in the range 0x00000001 - 0x7FFFFFFF (in units of mWh or mAh, depending on the Power
Units value) is the user’s preference for battery warning. If the level speciﬁed is less than the design capacity of
warning, it may be ignored by the platform so that the platform can ensure a successful wake on low battery.
The battery low level in the range 0x00000001 - 0x7FFFFFFF (in units of mWh or mAh, depending on the Power
Units value) is the user’s preference for battery low. If this level is less than the design capacity of low, it may be
ignored by the platform.
The battery wake level in the range 0x00000001 - 0x7FFFFFFF (in units of mWh or mAh, depending on the Power
Units value) is the user’s preference for battery wake. If this level is less than the platform’s current wake on low
battery level, it may be ignored by the platform. If the platform does not support a conﬁgurable wake on low battery
level, this may be ignored by the platform.
9.3 Ambient Light Sensor Device
The following section illustrates the operation and deﬁnition of the control method-based Ambient Light Sensor (ALS)
device.
The ambient light sensor device can optionally support power management objects (e.g. _PS0, _PS3) to allow the OS
to manage the device’s power consumption.
The Plug and Play ID of an ACPI control method ambient light sensor device is ACPI0008.
Table 9.2: Control Method Ambient Light Sensor Device
_ALI The current ambient light illuminance reading in lux (lumen per square meter). [Required]
_ALC The current ambient light color chromaticity reading, speciﬁed using x and y coordinates per the
CIE Yxy color model. [Optional]
_ALT The current ambient light color temperature reading in degrees Kelvin. [Optional]
_ALR Returns a set of ambient light illuminance to display brightness mappings that can be used by an
OS to calibrate its ambient light policy. [Required]
_ALP Ambient light sensor polling frequency in tenths of seconds. [Optional]

device.
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9.3.1 Overview
This deﬁnition provides a standard interface by which the OS may query properties of the ambient light environment
the system is currently operating in, as well as the ability to detect meaningful changes in these values when the
environment changes. Two ambient light properties are currently supported by this interface: illuminance and color.
Ambient light illuminance readings are obtained via the _ALI method. Illuminance readings indicate the amount of
light incident upon (falling on) a speciﬁed surface area. Values are speciﬁed in lux (lumen per square meter) and give
an indication of how “bright” the environment is. For example, an overcast day is roughly 1000 lux, a typical ofﬁce
environment 300-400 lux, and a dimly-lit conference room around 10 lux.
A possible use of ambient light illuminance data by the OS is to automatically adjust the brightness (or luminance)
of the display device - e.g. increase display luminance in brightly-lit environments and decrease display luminance
in dimly-lit environments. Note that Luminance is a measure of light radiated (reﬂected, transmitted, or emitted) by
a surface, and is typically measured in nits. The _ALR method provides a set of ambient light illuminance to display
luminance mappings that can be used by an OS to calibrate its policy for a given platform conﬁguration.
Ambient light color readings are obtained via the _ALT and/or _ALC methods. Two methods are deﬁned to allow
varying types/complexities of ambient light sensor hardware to be used. _ALT returns color temperature readings
in degrees Kelvin. Color temperature values correlate a light source to a standard black body radiator and give an
indication of the type of light source present in a given environment (e.g. daylight, ﬂuorescent, incandescent). ALC
returns color chromaticity readings per the CIE Yxy color model. Chromaticity x and y coordinates provide a more
straightforward indication of ambient light color characteristics. Note that the CIE Yxy color model is deﬁned by
the International Commission on Illumination (abbreviated as CIE from its French title Commission Internationale de
l’Eclairage) and is based on human perception instead of absolute color.
A possible use of ambient light color data by the OS is to automatically adjust the color of displayed images depending
on the environment the images are being viewed in. This may be especially important for reﬂective/transﬂective
displays where the type of ambient light may have a large impact on the colors perceived by the user.
9.3.2 _ALI (Ambient Light Illuminance)
This control method returns the current ambient light illuminance reading in lux (lumen per square meter). Expected
values range from ~1 lux for a dark room, ~300 lux for a typical ofﬁce environment, and 10,000+ lux for daytime
outdoor environments - although readings may vary depending on the location of the sensor to the light source. Special
values are reserved to indicate out of range conditions (see below).
None
An Integer containing the ambient light brightness in lux (lumens per square meter)
0 - The current reading is below the supported range or sensitivity of the sensor.
Ones (-1) - The current reading is above the supported range or sensitivity of the sensor.
Other values - The current ambient light brightness in lux (lumens per square meter)
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9.3.3 _ALT (Ambient Light Temperature)
This optional control method returns the current ambient light color temperature reading in degrees Kelvin (°K). Lower
color temperatures imply warmer light (emphasis on yellow and red); higher color temperatures imply a colder light
(emphasis on blue). This value can be used to gauge various properties of the lighting environment - for example, the
type of light source. Expected values range from ~1500°K for candlelight, ~3000°K for a 200-Watt incandescent bulb,
and ~5500°K for full sunlight on a summer day - although readings may vary depending on the location of the sensor
to the light source. Special values are reserved to indicate out of range conditions (see below).
None
An Integer containing the ambient light temperature in degrees Kelvin
0 - The current reading is below the supported range or sensitivity of the sensor
Ones (-1) - The current reading is above the supported range or sensitivity of the sensor
Other values - The current ambient light temperature in degrees Kelvin
9.3.4 _ALC (Ambient Light Color Chromaticity)
This optional control method returns the current ambient light color chromaticity readings per the CIE Yxy color
model. The x and y (chromaticity) coordinates are speciﬁed using a ﬁxed 10-4 notation due to the lack of ﬂoating
point values in ACPI. Valid values are within the range 0 (0x0000) through 1 (0x2710). A single 32-bit integer value
is used, where the x coordinate is stored in the high word and the y coordinate in the low word. For example, the value
0x0C370CDA would be used to specify the white point for the CIE Standard Illuminant D65 (a standard representation
of average daylight) with x = 0.3127 and y = 0.3290. Special values are reserved to indicate out of range conditions
(see below).
None
Other values - The current ambient light color chromaticity x and y coordinate values, per the
CIE Yxy color model
9.3.5 _ALR (Ambient Light Response)
This object evaluates to a package of ambient light illuminance to display luminance mappings that can be used by an
OS to calibrate its ambient light policy for a given sensor conﬁguration. The OS can use this information to extrapolate
an ALS response curve - noting that these values may be treated differently depending on the OS implementation but
should be used in some form to calibrate ALS policy.
None
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A variable-length Package containing a list of luminance mapping Packages. Each mapping package consists of two
Integers.
The return data is speciﬁed as a package of packages, where each tuple (inner package) consists of the pair of Integer
values of the form:
{<display luminance adjustment>, <ambient light illuminance>}
Package elements should be listed in monotonically increasing order based upon the ambient light illuminance value
(the Y-coordinate on the graph) to simplify parsing by the OS.
Ambient light illuminance values are speciﬁed in lux (lumens per square meter). Display luminance (or brightness)
adjustment values are speciﬁed using relative percentages in order simplify the means by which these adjustments are
applied in lieu of changes to the user’s display brightness preference. A value of 100 is used to indicate no (0%) display
brightness adjustment given the lack of signed data types in ACPI. Values less than 100 indicate a negative adjustment
(dimming); values greater than 100 indicate a positive adjustment (brightening). For example, a display brightness
adjustment value of 75 would be interpreted as a -25% adjustment, and a value of 110 as a +10% adjustment.
Fig. 9.1: A ﬁve-point ALS Response Curve
The ﬁgure above illustrates the use of ﬁve points to approximate an example response curve, where the dotted line
represents an approximation of the desired response (solid curve). Extrapolation of the values between these points
is OS-speciﬁc - although for the purposes of this example we’ll assume a piecewise linear approximation. The ALS
response curve (_ALR) would be speciﬁed as follows:
Name(_ALR, Package() {
Package{70, 0}, // Min ( -30% adjust at 0 lux)
Package{73, 10}, // ( -27% adjust at 10 lux)
Package{85, 80}, // ( -15% adjust at 80 lux)
Package{100,300}, // Baseline ( 0% adjust at 300 lux)
Package{150,1000} // Max ( +50% adjust at 1000 lux)
})
Within this data set exist three points of particular interest: baseline, min, and max. The baseline value represents
an ambient light illuminance value (in lux) for the environment where this system is most likely to be used. When
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the system is operating in this ambient environment the ALS policy will apply no (0%) adjustment to the default
display brightness setting. For example, given a system with a 300 lux baseline, operating in a typical ofﬁce ambient
environment (~300 lux), conﬁgured with a default display brightness setting of 50% (e.g. 60 nits), the ALS policy

})
would apply no backlight adjustment, resulting in an absolute display brightness setting of 60 nits.
Min and max are used to indicate cutoff points in order to prevent an over-zealous response by the ALS policy and
to inﬂuence the policy’s mode of operation. For example, the min and max points from the ﬁgure above would be
speciﬁed as (70,0) and (150,1000) respectively - where min indicates a maximum negative adjustment of 30% and max
represents a maximum positive adjustment of 50%. Using a large display brightness adjustment for max allows an
ALS response that approaches a fully-bright display (100% absolute) in very bright ambient environments regardless
of the user’s display brightness preference. Using a small value for max (e.g. 0% @ 300 lux) would inﬂuence the ALS
policy to limit the use of this technology solely as a power-saving feature (never brighten the display). Conversely,
setting min to a 0% adjustment instructs ALS policy to brighten but never dim.
A minimum of two data points are required in the return package, interpreted as min and max. Note that the baseline
value does not have to be explicitly stated; it can be derived from the response curve. Addition elements can be
provided to ﬁne-tune the response between these-points. The following ﬁgure illustrates the use of two data points to
achieve a response similar to (but simpler than) that described in the ﬁve-point ALS response curve example.
Fig. 9.2: A two-point ALS Response Curve
This example lacks an explicit baseline and includes a min with an ambient light value above 0 lux. The baseline can
easily be extrapolated by ALS Policy (e.g. 0% adjustment at ~400 lux). All ambient light brightness settings below
min (20 lux) would be treated in a similar fashion by ALS policy (e.g. -30% adjustment). This two-point response
curve would be modeled as:
Package{70, 30}, // Min ( -30% adjust at 30 lux)
})
This model can be used to convey a wide range of ambient light to display brightness responses. For example, a
transﬂective display - a technology where illumination of the display can be achieved by reﬂecting available ambient
light, but also augmented in dimly-lit environments with a backlight - could be modeled as illustrated in the following
ﬁgure.
This three-point approximation would result in an ALS response that allows the backlight to increase as the ambient
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Fig. 9.3: Example Response Curve for a Transﬂective Display
lighting decreases. In this example, no backlight adjustment is needed in bright environments (1000+ lux), maximum
backlight may be needed in dim environments (~30 lux), but a lower backlight setting may be used in a very-dark
room (~0 lux) - resulting in an elbow around 30 lux. This response would be modeled in _ALR as follows:
Package{180, 0} ( +80% adjust at 0 lux)
Package{200, 30}, // Max (+100% adjust at 30 lux)
Package{0, 1000}, // Min ( 0% adjust at 1,000 lux)
})
Note the ordering of package elements: monotonically increasing from the lowest ambient light value (0 lux) to the
highest ambient light value (1000 lux).
The transﬂective display example also highlights the need for non-zero values for the user’s display brightness pref-
erence - which we’ll refer to as the reference display brightness value. This requirement is derived from the model’s
use of relative adjustments. For example, applying any adjustment to a 0% reference display brightness value always
results in a 0% absolute display brightness setting. Likewise, using a very small reference display brightness (e.g. 5%)
results in a muted response (e.g. +30% of 5% = 6.5% absolute). The solution is to apply a reasonably large value
(e.g. 50%) as the reference display brightness setting - even in the case where no backlight is applied. This allows
relative adjustments to be applied in a meaningful fashion while conveying to the user that the display is still usable
(via reﬂected light) under typical ambient conditions.
The OS derives the user’s display brightness preference (this reference value) either from the Brightness Control Levels
(_BCL) object or another OS-speciﬁc mechanism (see Section 9.3.8).
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9.3.6 _ALP (Ambient Light Polling)
This optional object evaluates to a recommended polling frequency (in tenths of seconds) for this ambient light sensor.
A value of zero - or the absence of this object when other ALS objects are deﬁned - indicates that OSPM does not
need to poll the sensor in order to detect meaningful changes in ambient light (the hardware is capable of generating
asynchronous notiﬁcations).
The use of polling is allowed but strongly discouraged by this speciﬁcation. OEMs should design systems that asyn-
chronously notify OSPM whenever a meaningful change in the ambient light occurs–relieving the OS of the overhead
associated with polling.
This value is speciﬁed as tenths of seconds. For example, a value of 10 would be used to indicate a 1 second polling
frequency. As this is a recommended value, OSPM will consider other factors when determining the actual polling
frequency to use.
None
An Integer containing the recommended polling frequency in tenths of seconds
0 - Polling by the host OS is not required
Other - The recommended polling frequency in tenths of seconds
9.3.7 Ambient Light Sensor Events
To communicate meaningful changes in ALS illuminance to OSPM, AML code should issue a Notify(als_device,
0x80) whenever the lux reading changes more than 10% (from the last reading that resulted in a notiﬁcation). OSPM
receives this notiﬁcation and evaluates the _ALI control method to determine the current ambient light status. The OS
then adjusts the display brightness based upon its ALS policy (derived from _ALR).
The deﬁnition of what constitutes a meaningful change is left to the system integrator, but should be at a level of
granularity that provides an appropriate response without overly taxing the system with unnecessary interrupts. For
example, an ALS conﬁguration may be tuned to generate events for all changes in ambient light illuminance that result
in a minimum±5% display brightness response (as deﬁned by _ALR).
To communicate meaningful changes in ALS color temperature to OSPM, AML code should issue a Notify(als_device,
0x81) whenever the lux reading changes more than 10% (from the last reading that resulted in a notiﬁcation). OSPM
receives this notiﬁcation and evaluates the _ALT and _ALC control method to determine the current ambient light
color temperature.
To communicate meaningful changes in ALS response to OSPM, AML code should issue a Notify(als_device, 0x82)
whenever the set of points used to convey ambient light response has changed. OSPM receives this notiﬁcation and
evaluates the _ALR object to determine the current response points.
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9.3.8 Relationship to Backlight Control Methods
The Brightness Control Levels (_BCL) method - described in section 0 - can be used to indicate user-selectable
display brightness levels. The information provided by this method indicates the available display brightness settings,
the recommended default brightness settings for AC and DC operation, and the absolute maximum and minimum
brightness settings. These values indirectly inﬂuence the operation of the OSPM’s ALS policy.
Display brightness adjustments produced by ALS policy are relative to the current user backlight setting, and the
resulting absolute value must be mapped (rounded) to one of the levels speciﬁed in _BCL. This introduces the re-
quirement for ﬁne-grain display brightness control in order to achieve a responsive ALS system - which typically
materializes as a need for additional entries in the _BCL list in order to provide reasonable resolution to the OS (e.g.
3-10% granularity). Note that user brightness controls (e.g. hotkeys) are not required to make use of all levels speciﬁed
in _BCL.
9.4 Control Method Lid Device
Platforms containing lids convey lid status (open / closed) to OSPM using a Control Method Lid Device.
To implement a control method lid device, AML code should issue a Notify(lid_device, 0x80) for the device whenever
the lid status has changed. The _LID control method for the lid device must be implemented to report the current state
of the lid as either opened or closed.
The lid device can support _PRW and _PSW methods to select the wake functions for the lid when the lid transitions
from closed to opened.
The Plug and Play ID of an ACPI control method lid device is PNP0C0D.
Table 9.3: Control Method Lid Device
_LID Returns the current status of the lid.
9.4.1 _LID
Evaluates to the current status of the lid.

in _BCL.
9.4.1 _LID
None
An Integer containing the current lid status:
0 - The lid is closed Non-zero - The lid is open
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9.5 Control Method Power and Sleep Button Devices
The system’s power or sleep button can either be implemented using the ﬁxed register space as deﬁned in Console But-
tons or implemented in AML code as a control method power button device. In either case, the power button override
function or similar unconditional system power or reset functionality is still implemented in external hardware.
To implement a control method power-button or sleep-button device, implement AML code that delivers two types of
notiﬁcations concerning the device. The ﬁrst is Notify(Object, 0x80) to signal that the button was pressed while the
system was in the S0 state to indicate that the user wants the machine to transition from S0 to some sleeping state. The
other notiﬁcation is Notify(Object, 0x2) to signal that the button was pressed while the system was in an S1 to S4 state
and to cause the system to wake. When the button is used to wake the system, the wake notiﬁcation (Notify(Object,
0x2)) must occur after OSPM actually wakes, and a button-pressed notiﬁcation (Notify(Object, 0x80)) must not occur.
The Wake Notiﬁcation indicates that the system is awake because the user pressed the button and therefore a complete
system resume should occur (for example, turn on the display immediately, and so on).
9.6 Generic Container Device
A generic container device is a bridge that does not require a special OS driver because the bridge does not provide
or require any features not described within the normal ACPI device functions. The resources the bridge requires
are speciﬁed via normal ACPI resource mechanisms. Device enumeration for child devices is supported via ACPI
namespace device enumeration and OS drivers require no other features of the bus. Such a bridge device is identiﬁed
with the Plug and Play ID of PNP0A05 or PNP0A06.
A generic bus bridge device is typically used for integrated bridges that have no other means of controlling them
and that have a set of well-known devices behind them. For example, a portable computer can have a “generic bus
bridge” known as an EIO bus that bridges to some number of Super-I/O devices. The bridged resources are likely to
be positively decoded as either a function of the bridge or the integrated devices. In this example, a generic bus bridge
device would be used to declare the bridge then child devices would be declared below the bridge; representing the
integrated Super-I/O devices.
9.7 ATA Controller Devices
There are two types of ATA Controllers: IDE controllers (also known as ATA controllers) and Serial ATA (SATA)
controllers. IDE controllers are those using the traditional IDE programming interface, and may support Parallel ATA
(P-ATA) or SATA connections. SATA controllers may be designed to operate in emulation mode only, native mode
only, or they may be designed to support both native and non-native SATA modes. Regardless of the mode supported,
SATA controllers are designed to work solely with drives supporting the Serial ATA physical interface. As described
below, SATA controllers are treated similarly but not identically to traditional IDE controllers.
Platforms that contain controllers that support native and non-native SATA modes must take steps to ensure the proper
objects are placed in the namespace for the mode in which they are operating.
Table 9.4: ATA Speciﬁc Objects
Object Description Controller Type
_GTF Optional object that returns the ATA task ﬁle needed to re-initialize the drive to
boot up defaults.Both
_GTM Optional object that returns the IDE controller timing information. IDE-only
_STM Optional control method that sets the IDE controller’s transfer timing settings. IDE-only
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Table 9.4 – continued from previous page
_SDD Optional control method that informs the platform of the type of device attached
to a port.SATA-only
9.7.1 Objects for Both ATA and SATA Controllers
9.7.1.1 _GTF (Get Task File)
This optional object returns a buffer containing the ATA commands used to restore the drive to boot up defaults (that
is, the state of the drive after POST). The returned buffer is an array with each element in the array consisting of seven
8-bit register values (56 bits) corresponding to ATA task registers 1F1 thru 1F7. Each entry in the array deﬁnes a
command to the drive.
None
A Buffer containing a byte stream of ATA commands for the drive
This object may appear under SATA port device objects or under IDE channel objects.
ATA task ﬁle array deﬁnition:
• Seven register values for command 1
–Reg values: (1F1, 1F2, 1F3, 1F4, 1F5, 1F6, 1F7)
• Seven register values for command 2
• Seven register values for command 3
• Etc.
After powering up the drive, OSPM will send these commands to the drive, in the order speciﬁed. On SATA HBAs,
OSPM evaluates _SDD before evaluating _GTF. The IDE driver may modify some of the feature commands or append
its own to better tune the drive for OSPM features before sending the commands to the drive.
This Control Method is listed under each drive device object. OSPM must evaluate the _STM object or the _SDD
object before evaluating the _GTF object.
Example of the return from _GTF:
Method(_GTF, 0x0, NotSerialized)
{
Return(GTF0)
}
Name(GTF0, Buffer(0x1c)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xef, 0x03, 0x00, 0x00, 0x00, 0x00,
0xa0, 0xef, 0x00, 0x10, 0x00, 0x00, 0x00, 0xa0, 0xc6, 0x00, 0x00, 0x00,
0x00, 0x00, 0xa0, 0x91
}
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9.7.2 IDE Controller Device
Most device drivers can save and restore the registers of their device. For IDE controllers and drives, this is not true
because there are several drive settings for which ATA does not provide mechanisms to read. Further, there is no
industry standard for setting timing information for IDE controllers. Because of this, ACPI interface mechanisms are
necessary to provide the operating system information about the current settings for the drive and channel, and for
setting the timing for the channel.
OSPM and the IDE driver will follow these steps when powering off the IDE subsystem:
1. The IDE driver will call the _GTM control method to get the current transfer timing settings for the IDE channel.
This includes information about DMA and PIO modes.
2. The IDE driver will call the standard OS services to power down the drives and channel.
3. As a result, OSPM will execute the appropriate _PS3 methods and turn off unneeded power resources.
To power on the IDE subsystem, OSPM and the IDE driver will follow these steps:
1. The IDE driver will call the standard OS services to turn on the drives and channel.
2. As a result, OSPM will execute the appropriate _PS0 methods and turn on required power resources.
3. The IDE driver will call the _STM control method passing in transfer timing settings for the channel, as well as
the ATA drive ID block for each drive on the channel. The _STM control method will conﬁgure the IDE channel
based on this information.
4. For each drive on the IDE channel, the IDE driver will run the _GTF to determine the ATA commands required
to reinitialize each drive to boot up defaults.
5. The IDE driver will ﬁnish initializing the drives by sending these ATA commands to the drives, possibly modi-
fying or adding commands to suit the features supported by the operating system.
The following shows the namespace for these objects:
\_SB // System bus
PCI0 // PCI bus
IDE1 // First IDE channel
_ADR // Indicates address of the channel on the PCI bus
_GTM // Control method to get current IDE channel settings
_STM // Control method to set current IDE channel settings
_PR0 // Power resources needed for D0 power state
DRV1 // Drive 0
_ADR // Indicates address of master IDE device
_GTF // Control method to get task file
DRV2 // Drive 1
_ADR // Indicates address of slave IDE device
IDE2 // Second IDE channel
The sequential order of operations is as follows:
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Powering down
• Call _GTM.

• Power down drive (calls _PS3 method and turns off power planes).
Powering up
• Power up drive (calls _PS0 method if present and turns on power planes).
• Call _STM passing info from _GTM (possibly modiﬁed), with ID data from each drive.
• Initialize the channel.
• May modify the results of _GTF.
• For each drive:
– Call _GTF.
– Execute task ﬁle (possibly modiﬁed).
9.7.2.1 IDE Controller-speciﬁc Objects
9.7.2.1.1 _GTM (Get Timing Mode)
This Control Method exists under each channel device object and returns the current settings for the IDE channel.
None
A Buffer containing the current IDE channel timing information block as described in the GTM Method
Result Codes table below.
_GTM returns a buffer with the following format
Buffer (){
PIO Speed 0 //DWORD
DMA Speed 0 //DWORD
PIO Speed 1 //DWORD
DMA Speed 1 //DWORD
Flags //DWORD
}
Table 9.5: GTM Method Result Codes
PIO Speed 0 DWORD The PIO bus-cycle timing for drive 0 in nanoseconds. 0xFFFFFFFF indicates
that this mode is not supported by the channel. If the chipset cannot set timing
parameters independently for each drive, this ﬁeld represents the timing for both
drives.
DMA Speed 0 DWORD The DMA bus-cycle for drive 0 timing in nanoseconds. If bit 0 of the Flags reg-
ister is set, this DMA timing is for UltraDMA mode, otherwise the timing is for
multi-word DMA mode. 0xFFFFFFFF indicates that this mode is not supported
by the channel. If the chipset cannot set timing parameters independently for
each drive, this ﬁeld represents the timing for both drives.
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Table 9.5 – continued from previous page
PIO Speed 1 DWORD The PIO bus-cycle timing for drive 1 in nanoseconds. 0xFFFFFFFF indicates
parameters independently for each drive, this ﬁeld must be 0xFFFFFFFF.
DMA Speed 1 DWORD The DMA bus-cycle timing for drive 1 in nanoseconds. If bit 0 of the Flags reg-
each drive, this ﬁeld must be 0xFFFFFFFF.
Flags DWORD Mode ﬂags Bit [0]: 1 indicates using UltraDMA on drive 0 Bit [1]: 1 indicates
IOChannelReady is used on drive 0 Bit [2]: 1 indicates using UltraDMA on
drive 1 Bit [3]: 1 indicates IOChannelReady is used on drive 1 Bit [4]: 1 indi-
cates chipset can set timing independently for each drive Bits [31:5]: reserved
(must be 0)
9.7.2.1.2 _STM (Set Timing Mode)
This Control Method sets the IDE channel’s transfer timings to the setting requested. The AML code is required to
convert and set the nanoseconds timing to the appropriate transfer mode settings for the IDE controller. _STM may
also make adjustments so that _GTF control methods return the correct commands for the current channel settings.
This control method takes three arguments: Channel timing information (as described in Table 9-6), and the ATA drive
ID block for each drive on the channel. The channel timing information is not guaranteed to be the same values as
returned by _GTM; the OS may tune these values as needed.
Arg0 - A Buffer containing a channel timing information block (described in Table 9-6)
Arg1 - A Buffer containing the ATA drive ID block for channel 0
Arg2 - A Buffer containing the ATA drive ID block for channel 1
None
The ATA drive ID block is the raw data returned by the Identify Drive ATA command, which has the command code
“0ECh.” The _STM control method is responsible for correcting for drives that misreport their timing information.
9.7.3 Serial ATA (SATA) Controller Device
9.7.3.1 Deﬁnitions
HBA Host Bus Adapter
Native SATA aware Refers to system software (platform ﬁrmware, option ROM, operating system, etc) that compre-
hends a particular SATA HBA implementation and understands its programming interface and power manage-
ment behavior.
Non-native SATA aware Refers to system software (platform ﬁrmware, option ROM, operating system, etc) that
does not comprehend a particular SATA HBA implementation and does not understand its programming in-
terface or power management behavior. Typically, non-native SATA aware software will use a SATA HBA’s
emulation interface (e.g. task ﬁle registers) to control the HBA and access its devices.
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Emulation mode Optional mode supported by a SATA HBA. Allows non-native SATA aware software to access
SATA devices via traditional task ﬁle registers.
Native mode Optional mode supported by a SATA HBA. Allows native SATA aware software to access SATA devices
via registers that are speciﬁc to the HBA.
Hybrid Device Refers to a SATA HBA that implements both an emulation and a native programming interface.
9.7.3.2 Overview
A SATA HBA differs from an IDE controller in a number of ways. First, it can save its complete device context.
Second, it replaces IDE channels, which may support up to 2 attached devices, with ports, which support only a single
attached device, unless a port multiplier is present. See the SATA spec at “Links to ACPI-Related Documents” (
http://ueﬁ.org/acpi ) under the heading “SATA Speciﬁcation”for more information. Finally, SATA does not require
timing information from the platform, allowing a simpliﬁcation in how SATA controllers are represented in ACPI.
(_GTM and _STM are replaced by the simpler _SDD method.)
All ports, even those attached off a port multiplier, are represented as children directly under the SATA controller
device. This is practical because the SATA speciﬁcation does not allow a port multiplier to be attached to a port
multiplier. Each port’s _ADR indicates to which root port they are connected, as well as the port multiplier location,
if applicable (see Table 6.2)
Since this speciﬁcation only covers the conﬁguration of motherboard devices, it is also the case that the control methods
deﬁned in this section cannot be used to send taskﬁles to devices attached via either an add-in SATA HBA, or attached
via a motherboard SATA HBA, if used with a port multiplier that is not also on the motherboard.
The following shows an example SATA namespace:
\_SB - System bus
PCI0 - PCI bus
SATA - SATA Controller device
ADR - Indicates address of the controller on the PCI bus
PR0 - Power resources needed for D0 power state
PRT0 - Port 0 device
_ADR - Indicates physical port and port multiplier topology
_SDD - Identify information for drive attached to this port
_GTF - Control method to get task file
PRTn - Port n device
9.7.3.3 SATA controller-speciﬁc control methods
In order to ensure proper interaction between OSPM, the ﬁrmware, and devices attached to the SATA controller, it is
a requirement that OSPM execute the _SDD and _GTF control methods when certain events occur. OSPM’s response
to events must be as follows:
COMRESET, Initial OS load, device insertion, HBA D3 to D0 transition, asynchronous loss of signal:
1. OSPM sends IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command to the attached device.
2. OS executes _SDD. _SDD control method requires 1 argument that consists of the data block received from an
attached device as a result of a host issued IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command.
3. After the _SDD method completes, the OS executes the _GTF method. Using the task ﬁle information provided
by _GTF, the OS then sends the _GTF taskﬁles to the attached device.
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Device removal and HBA D0 to D3 transition:
1. No OSPM action required.
9.7.3.3.1 _SDD (Set Device Data)
This optional object is a control method that conveys to the platform the type of device connected to the port. The
_SDD object may exist under a SATA port device object. The platform typically uses the information conveyed by the
_SDD object to construct the values returned by the _GTF object.
OSPM conveys to the platform the ATA drive ID block, which is the raw data returned by the Identify (Packet) Device,
ATA command (command code “0ech.”). Please see the ATA/ATAPI-6 speciﬁcation for more details.
Arg0 - A Buffer containing an ATA drive identify block, contents described by the ATA speciﬁcation
None
9.8 Floppy Controller Device Objects
9.8.1 _FDE (Floppy Disk Enumerate)
Enumerating devices attached to a ﬂoppy disk controller is a time-consuming function. In order to speed up the
process of ﬂoppy enumeration, ACPI deﬁnes an optional enumeration object that is deﬁned directly under the device

None
object for the ﬂoppy disk controller. It returns a buffer of ﬁve 32-bit values. The ﬁrst four values are Boolean values
indicating the presence or absence of the four ﬂoppy drives that are potentially attached to the controller. A non-zero
value indicates that the ﬂoppy device is present. The ﬁfth value returned indicates the presence or absence of a tape
controller. Deﬁnitions of the tape presence value can be found in Tape Presence .
None
A Buffer containing a ﬂoppy drive information block, as decribed below:
Buffer (){
Floppy 0 // Boolean DWORD
Floppy 1 // Boolean DWORD
Floppy 2 // Boolean DWORD
Floppy 3 // Boolean DWORD
Tape // DWORD - See the Tape Presence table below
}
Table 9.6: Tape Presence
0 Device presence is unknown or unavailable
1 Device is present
2 Device is never present
>2 Reserved
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9.8.2 _FDI (Floppy Disk Information)
This object returns information about a ﬂoppy disk drive. This information is the same as that returned by the INT 13
Function 08H on IA-PCs.
None
A Package containing the ﬂoppy disk information as a list of Integers:
Package {
Drive Number // Integer (BYTE)
Device Type // Integer (BYTE)
Maximum Cylinder Number // Integer (WORD)
Maximum Sector Number // Integer (WORD)
Maximum Head Number // Integer (WORD)
disk_specify_1 // Integer (BYTE)
disk_specify_2 // Integer (BYTE)
disk_motor_wait // Integer (BYTE)
disk_sector_siz // Integer (BYTE)
disk_eot // Integer (BYTE)
disk_rw_gap // Integer (BYTE)
disk_dtl // Integer (BYTE)
disk_formt_gap // Integer (BYTE)
disk_fill // Integer (BYTE)
disk_head_sttl // Integer (BYTE)
disk_motor_strt // Integer (BYTE)
}
Table 9.7: ACPI Floppy Drive Information
Package Element Element Object Type Actual Valid Data Width
00 - Drive Number Integer BYTE
01 - Device Type Integer BYTE
02 - Maximum Cylinder Number Integer WORD
03 - Maximum Sector Number Integer WORD
04 - Maximum Head Number Integer WORD
05 - Disk_specify_1 Integer BYTE
06 - Disk_specify_2 Integer BYTE
07 - Disk_motor_wait Integer BYTE
08 - Disk_sector_siz Integer BYTE
09 - Disk_eot Integer BYTE
10 - Disk_rw_gap Integer BYTE
11 - Disk_dtl Integer BYTE
12 - Disk_formt_gap Integer BYTE
13 - Disk_ﬁll Integer BYTE
14 - Disk_head_sttl Integer BYTE
15 - Disk_motor_strt Integer BYTE
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9.8.3 _FDM (Floppy Disk Drive Mode)
This control method switches the mode (300 RPM or 360 RPM) of all ﬂoppy disk drives attached to this controller. If
this control method is implemented, the platform must reset the mode of all drives to 300RPM mode after a Dx to D0
transition of the controller.
Arg0 - An Integer containing the new drive mode
0 - Set the mode of all drives to 300 RPM mode
1 - Set the mode of all drives to 360 RPM mode
None
9.9 GPE Block Device
The GPE Block device is an optional device that allows a system designer to describe GPE blocks beyond the two that
are described in the FADT. Control methods associated with the GPE pins of GPE block devices exist as children of
the GPE Block device, not within the \_GPE namespace. Because GPE block devices are meant as an extension to
the GPE blocks deﬁned in the FADT, and that portion of the FADT is to be ignored in hardware-reduced ACPI, GPE
block devices are not supported in hardware-reduced ACPI.
A GPE Block device consumes I/O or memory address space, as speciﬁed by its _PRS or _CRS child objects. The
interrupt vector used by the GPE block does not need to be the same as the SCI_INT ﬁeld. The interrupt used by the
GPE block device is speciﬁed in the _CRS and _PRS methods associated with the GPE block. The _CRS of a GPE
Block device may only specify a single register address range, either I/O or memory. This range contains two registers:
the GPE status and enable registers. Each register’s length is deﬁned as half of the length of the _CRS-deﬁned register
address range.
A GPE Block device must have a _HID or a _CID of “ACPI0006.”
Note: A system designer must describe the GPE block necessary to bootstrap the system in the FADT as a
GPE0/GPE1 block. GPE Block devices cannot be used to implement these GPE inputs.*
A GPE Block Device must contain the _Lxx, _Exx, _Wxx, _CRS, _PRS, and _SRS methods required to use and
program that block.
To represent the GPE block associated with the FADT, the system designer shouldinclude in the namespace a Device
object with the ACPI0006 _HID that contains no _CRS, _PRS, _SRS, _Lxx, _Exx, or _Wxx methods. OSPM assumes
that the ﬁrst such ACPI0006 device is the GPE Block Device that is associated with the FADT GPEs. (See the example
below).
// ASL example of a standard GPE block device
Device(\_SB.PCI0.GPE1) {
Name(_HID, "ACPI0006")
Name(_CRS, Buffer () {
IO(Decode16, FC00, FC03, 4, 4,)
IRQ( Level, ActiveHigh, Shared,) { 5 }
})
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Method(_L02) { ... }
Method(_E07) { ... }
Method(_W04) { ... }
}
// ASL example of a GPE block device that refers to the FADT GPEs.
// Cannot contain any \_Lxx, \_Exx, \_Wxx, \_CRS, \_PRS, or. \_SRS methods.
Device(\_SB.PCI0.GPE0) {
Name(_HID,"ACPI0006")
Name(_UID,1)
}
Notice that it is legal to replace the I/O descriptors with Memory descriptors if the register is memory mapped.
If the system must run any GPEs to bootstrap the system (for example, when Embedded Controller events are required),
the associated block of GPEs must be described in the FADT. This register block is not relocatable and will always be
available for the life of the operating system boot.
A GPE block associated with the ACPI0006 _HID can be stopped, ejected, reprogrammed, and so on. The system can
also have multiple such GPE blocks.
9.9.1 Matching Control Methods for Events in a GPE Block Device
When a GPE Device raises an interrupt, OSPM executes a corresponding control method (see Queuing the matching
control method for execution ). These control methods for GPE Devices (of the form _Lxx, _Exx, and _Wxx) are not
within the _GPE namespace. They are children of the GPE Block device.
Device(GPE5) {
}
9.10 Module Device
This optional device is a container object that acts as a bus node in a namespace. It may contain child objects that are
devices or buses. The module device is declared using the ACPI0004 hardware identiﬁer (HID).
If the module device contains a _CRS object, the bus described by this object is assumed to have these resources
available for consumption by its child devices. If a _CRS object is present, any resources not produced in the module
device’s _CRS object may not be allocated to child devices.
Providing a _CRS object is undesirable in some module devices. For example, consider a module device used to
describe an add-in board containing multiple host bridges without any shared resource decoding logic. In this case the
resource ranges available to the host bridges are not controlled by any entity residing on the add-in board, implying
that a _CRS object in the associated module device would not describe any real feature of the underlying hardware. A
module device must contain a _CRS object if the device contains any PCI host bridge devices.
To account for cases like this, the system designer may optionally omit the module device’s _CRS object. If no _CRS
object is present, OSPM will assume that the module device is a simple container object that does not produce the
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resources consumed by its child devices. In this case, OSPM will assign resources to the child devices as if they were
direct children of the module device’s parent object.
For an example with a module device _CRS object present, consider a Module Device containing three child memory
devices. If the _CRS object for the Module Device contains memory from 2 GB through 6 GB, then the child memory
devices may only be assigned addresses within this range.
Example:
Device (\_SB.NOD0) {
Name (_HID, "ACPI0004") // Module device
Name (_PRS, ResourceTemplate() {
WordIO (
MinFixed, // \_MIF
MaxFixed,,, // \_MAF
0x0000, // \_GRA
0x0000, // \_MIN
0x7FFF, // \_MAX
0x0, // \_TRA
0x8000) // \_LEN
DWordMemory (
ResourceProducer,, // For Main Memory + PCI
MinNotFixed, // _MIF
MaxNotFixed, // _MAF
Cacheable, // _MEM
0x0FFFFFFF, // _GRA
0x40000000, // _MIN
0x7FFFFFFF, // _MAX
0x0, // _TRA
0x00000000) // _LEN
})
Method (_SRS, 1) { ... }
Method (_CRS, 0) { ... }
Device (MEM0) { // Main Memory (256MB module)
Name (_HID, EISAID("PNP0C80"))

Example:
WordIO (
})
Method (_STA, 0) { // If memory not present --> Return(0x00),
// Else if memory is disabled --> Return(0x0D),
// Else --> Return(0x0F)
}
Name (_PRS, ResourceTemplate () {
DWordMemory (,,,,
0x10000000) // _LEN
})
Method (_DIS, 0) { ... }
}
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Device (MEM1) { // Main Memory (512MB module)
Method (_STA, 0) { // If memory not present --> Return(0x00)
// Else if memory is disabled --> Return(0x0D)
}
0x1FFFFFFF, // _GRA
0x20000000) // _LEN
})
}
Device (PCI0) { // PCI Root Bridge
Name (_HID, EISAID("PNP0A03"))
Name (_BBN, 0x00)
WordBusNumber (
MaxFixed,, // _MAF
0x00, // _GRA
0x00, // _MIN
0x7F, // _MAX
0x80) // _LEN
WordIO (
MaxFixed,,, // _MAF
0x0000, // _GRA
0x0000, // _MIN
0x0CF7, // _MAX
0x0CF8) // _LEN
WordIO (
0x0D00, // _MIN
0x7FFF, // _MAX
0x7300) // _LEN
ResourceProducer,,
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NonCacheable, // _MEM
})
}
}
9.11 Memory Devices
Memory devices allow a platform to convey dynamic properties of memory to OSPM and are required when a plat-
form supports the addition or removal of memory while the system is active or when the platform supports memory
bandwidth monitoring and reporting (see Section 9.11.2). Memory devices may describe exactly the same physical
memory that the System Address Map interfaces describe (see Section 15). They do not describe how that memory
is, or has been, used. If a region of physical memory is marked in the System Address Map interface as AddressRan-
geReserved or AddressRangeNVS and it is also described in a memory device, then it is the responsibility of the OS
to guarantee that the memory device is never disabled.
It is not necessary to describe all memory in the system with memory devices if there is some memory in the system
that is static in nature. If, for instance, the memory that is used for the ﬁrst 16 MB of system RAM cannot be ejected,
inserted, or disabled, that memory may only be represented by the System Address Map interfaces. But if memory can
be ejected, inserted, or disabled, or if the platform supports memory bandwidth monitoring and reporting, the memory
must be represented by a memory device.
9.11.1 Address Decoding
Memory devices must provide a _CRS object that describes the physical address space that the memory decodes. If
the memory can decode alternative ranges in physical address space, the devices may also provide _PRS, _SRS and
_DIS objects. Other device objects may also apply if the device can be ejected.
9.11.2 Memory Bandwidth Monitoring and Reporting
During platform operation, an adverse condition external to the platform may arise whose remedy requires a reduc-
tion in the platform’s available memory bandwidth. For example, a server management controller’s detection of an
adverse thermal condition or the need to reduce the total power consumption of platforms in the data center to stay
within acceptable limits. Providing OSPM with knowledge of a platform induced reduction of memory bandwidth
enables OSPM to provide more robust handling of the condition. The following sections describe objects OSPM uses
to conﬁgure platform-based memory bandwidth monitoring and to ascertain available memory bandwidth when the
platform performs memory bandwidth throttling.
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9.11.2.1 _MBM (Memory Bandwidth Monitoring Data)
The optional _MBM object provides memory bandwidth monitoring information for the memory device.
None
A Package containing memory device status information as described in the MBM Package Details below.
_MBM evaluation returns a package of the following format:
Package (){
WindowSize, // Integer DWORD
SamplingInterval, // Integer DWORD
MaximumBandwidth, // Integer DWORD
AverageBandwidth, // Integer DWORD
LowBandwidth, // Integer DWORD
LowNotficationThreshold, // Integer DWORD
HighNotificationThreshold // Integer DWORD
}
Table 9.8: MBM Package Details
Revision Integer Current revision is: 0
Window Size Integer
(DWORD)This ﬁeld indicates the size of the averaging window (in seconds) that the plat-
form uses to report average bandwidth.
Sampling In-
tervalInteger
(DWORD)This ﬁeld indicates the sampling interval (in seconds) that the platform uses to
record bandwidth during the averaging window.
Maximum
BandwidthInteger
(DWORD)This ﬁeld indicates the maximum memory bandwidth (in megabytes per second)
for the memory described by this memory device.
Average
(DWORD)This ﬁeld indicates the moving average memory bandwidth (in percent) for the
averaging window.
Low Band-
widthInteger
(DWORD)This ﬁeld indicates the lowest memory bandwidth (in percent) recorded for the
Low No-
tiﬁcation
ThresholdInteger
(DWORD)The platform to issues a Notify (0x80) on the memory device when the moving
average memory bandwidth value (in percent) falls below the value indicated
by this ﬁeld.
High No-
tiﬁcation
(DWORD)The platform to issues a Notify (0x81) on the memory device when the moving
average memory bandwidth value (in percent) increases to or exceeds the value
indicated by this ﬁeld.
9.11. Memory Devices 567Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.11.2.2 _MSM (Memory Set Monitoring)
This optional object sets the memory bandwidth monitoring parameters described in Section 9.11.2.1 above.
Arguments(4)
Arg0 - WindowSize (Integer(DWORD)): indicates the window size in seconds.
Arg1 - SamplingInterval (Integer(DWORD)): indicates the sampling interval in seconds.
Arg2 - LowNotiﬁcationThreshold (Integer(DWORD)): indicates the low notiﬁcation threshold in percent.
Must be <= HighNotiﬁcationThreshold.
Arg3 - HighNotiﬁcationThreshold (Integer(DWORD)): indicates the high notiﬁcation threshold in per-
cent. Must be >= LowNotiﬁcationThreshold.
An Integer (DWORD) containing a bit encoded result code as follows:
0x00000000 - Succeeded to set all memory bandwidth monitoring parameters.
Non-Zero - At least one memory bandwith monitoring parameter value could not be set as
follows:
Table 9.9: MSM Result Encoding
0 If clear indicates WindowSize was set successfully. If set, indicates invalid WindowSize argu-
ment.
1 If clear indicates SamplingInterval was set successfully. If set, indicates invalid SamplingInterval
argument.
2 If clear indicates LowNotiﬁcationThreshold was set successfully. If set, indicates invalid LowNo-
tiﬁcationThreshold argument.
3 If clear indicates HighNotiﬁcationThreshold was set successfully. If set, indicates invalid High-
NotiﬁcationThreshold argument.
31:4 Reserved (must be 0)
9.11.3 _OSC Deﬁnition for Memory Device
OSPM evaluates _OSC under the Memory Device to convey OSPM capabilities to the platform. Argument deﬁnitions
are as follows
Arg0 - UUID (Buffer): 03B19910-F473-11DD-87AF-0800200C9A66
Arg1 - Revision ID (Integer): 1
Arg2 - Count of Entries in Arg3 (Integer): 2
Arg3 - DWORD capabilities (Buffer):
• First DWORD: Described in Section 6.2.10
• Second DWORD: See Section 6.4.3.5.2.
A Buffer containing platform capabilities
9.11. Memory Devices 568Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.10: Memory Device _OSC Capabilities DWORD number 2
0 Memory Band-
width Change
NotiﬁcationsThis bit is set if OSPM supports the processing of memory bandwidth change
notiﬁcations. If the platform supports the ability to issue a notiﬁcation when
Memory Bandwidth changes, it may only do so after _OSC has been evaluated
with this bit set. _OSC evaluation with this bit clear will cause the platform to
cease issuing notiﬁcations if previously enabled.
31:1 Reserved (must be 0)

Capabilities Buffer (Buffer) - The platform acknowledges the Capabilities Buffer by returning a buffer
of DWORDs of the same length. Set bits indicate acknowledgement and cleared bits indicate that the
platform does not support the capability.
9.11.4 Example: Memory Device
Scope (\_SB){
QWordMemory
,
MinFixed,
MaxFixed,
0,
,,)
}
}
}
9.12 _UPC (USB Port Capabilities)
This optional object is a method that allows the platform to communicate to the operating system, certain USB port
capabilities that are not provided for through current USB host bus adaptor speciﬁcations (e.g. UHCI, OHCI and
EHCI). If implemented by the platform, this object will be present for each USB port (child) on a given USB host bus
adaptor; operating system software can examine these characteristics at boot time in order to gain knowledge about
the system’s USB topology, available USB ports, etc. This method is applicable to USB root hub ports as well as ports
that are implemented through integrated USB hubs.
Arguments
None
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Package {
Connectable // Integer (BYTE)
Reserved0 // Integer
Reserved1 // Integer)
}
Table 9.11: UPC Return Package Values
Connectable Integer
(BYTE)If this value is non-zero, then the port is connectable. If this value is zero, then
the port is not connectable.
Type Integer
(BYTE) Speciﬁes the host connector type. It is ignored by OSPM if the port is not user
visible:
0x00: Type ‘A’ connector
0x01: Mini-AB connector
0x02: ExpressCard
0x03: USB 3 Standard-A connector
0x04: USB 3 Standard-B connector
0x05: USB 3 Micro-B connector
0x06: USB 3 Micro-AB connector
0x07: USB 3 Power-B connector
0x08: USB-C connector - USB2-only
0x09: USB-C connector - USB2 and SS with Switch
0x0A: USB-C connector - USB2 and SS without Switch
0x0B- 0xFE: Reserved
0xFF: Proprietary connector
USB-C Port
CapabilitiesInteger
Fields in this entry are valid only for a USB-C port (values 0x08, 0x09, or
0x0A) described by the the host connector Type (above):
- Bits [1:0]: Retimer Count- number of retimer devices present on the board
between the Host Router and this Port (connector) The maximum value is 2
(10b). If present, the retimer devices apply to USB4, USB 3, and any Alternate
Modes supported.
- Bit [2]: PCI Express Tunneling supported. This bit is valid only for ports that
support USB4 or TBT3. If PCI Express Tunneling for USB4 is not supported
via the USB4 _OSC mechanism, then the value of this bit is indeterminate.
- Bit [3]: DisplayPort Alternative Mode (DP Alt Mode) supported. This bit is
required to be set for ports that support USB4 or Thunderbolt™ 3.
- Bit [4]: USB4 Supported.
- Bit [5] Thunderbolt™ 3 Alternate Mode (TBT3) supported.
All other bits Reserved and set to zero (0).
Reserved1 Integer This value is reserved for future use and must be zero.
Additional Notes:
The deﬁnition of a connectable port is dependent on the implementation of the USB port within a particular platform.
9.12. _UPC (USB Port Capabilities) 570Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• If a USB port is user visible (as indicated by the _PLD object) and connectable, then an end user can freely
connect and disconnect USB devices to the USB port.
• If a USB port is not user visible and is connectable, then an end user cannot freely connect and disconnect USB
devices to the USB port. A USB device that is directly “hard-wired” to a USB port is an example of a USB port
that is not user visible and is connectable.
• If a USB port is not user visible and is not connectable, then the USB port is physically implemented by the
USB host controller, but is not being used by the platform and therefore cannot be accessed by an end user.
A USB port cannot be speciﬁed as both visible and not connectable.
The pins of a Type-C connector support one USB2 signal pair (D+/D-) and two SuperSpeed signal pairs
(SSTXp1/SSTXn1 and SSRXp2/SSRXn2). The use of two SS signal pairs allows the CC wire and USB SuperSpeed
data bus wires to be used for signaling within the cable track without regard to the orientation and twist of the cable.
Type C connector - USB2 USB2-only receptacles
These only implement the USB2 signal pair, and do not implement the SS signal pairs.
Type C connector - USB2 and SS with Switch receptacles
These implement the USB2 signal pair, and a Functional Switch with a physical Multiplexer that is used to dynamically
connect one of the two receptacle SuperSpeed signal pairs to a single USB Host Controller port as function of the
Type-C plug orientation.
Type C connector - USB2 and SS *without* Switch receptacles
These implement the USB2 signal pair and a Functional Switch by connecting each receptacle SuperSpeed signal pair
to a separate USB Host Controller port.
Note: See the USB Type-C Speciﬁcation at https://www.usb.org/documents for more information.
Example
The following is an example of a port characteristics object implemented for a USB host controller’s root hub where:
• Three Ports are implemented; Port 1 is not user visible/not connectable and Ports 2 and 3 are user visible and
connectable.
• Port 2 is located on the back panel
• Port 3 has an integrated 2 port hub. Note that because this port hosts an integrated hub, it is therefore not
shareable with another host controller (e.g. If the integrated hub is a USB2.0 hub, the port can never be shared
with a USB1.1 companion controller).
• The ports available through the embedded hub are located on the front panel and are adjacent to one another.
//
// Root hub device for this host controller.
// This controller implements 3 root hub ports.
//
Device( RHUB) {
Name( \_ADR, 0x00000000) // Value of 0 is reserved for root HUB
//
// Root hub, port 1
//
Device( PRT1) {
// Address object for port 1. This value must be 1.
Name( \_ADR, 0x00000001)
// USB port capabilities object. This object returns the system
9.12. _UPC (USB Port Capabilities) 571Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 9.4: USB ports
// specific USB port configuration information for port number 1
// Because this port is not connectable it is assumed to be not visible.
// Therefore a \_PLD descriptor is not required.
Name( \_UPC, Package(){
0x00, // Port is not connectable
0xFF, // Connector type (N/A for non-visible ports)
0x00000000, // Reserved 0 - must be zero
0x00000000}) // Reserved 1 - must be zero
} // Device( PRT1)
//
// Root Hub, Port 2
//
Device( PRT2) {
// Address object for port 2. This value must be 2
Name(_ADR, 0x00000002)
0xFF, // Port is connectable
0x00, // Connector type - Type 'A'
// provide physical port location info
Name( \_PLD, Package(1) {
Buffer(0x14) {
0x82,0x00,0x00,0x00, // Revision 2, Ignore color
// Color (ignored), width and height not
0x00,0x00,0x00,0x00, // required as this is a standard USB 'A' type
// connector
0x69,0x0c,0x00,0x00, // User visible, Back panel, Vertical
// Center, shape = vert. rectangle
0x03,0x00,0x00,0x00, // ejectable, requires OPSM eject assistance
0xFF,0xFF,0xFF,0xFF})} // Vert. and Horiz. Offsets not supplied
} // Device( PRT2)
//
// Root Hub, Port 3
//
Device( PRT3) { // This device is the integrated USB hub.
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// Address object for port 3. This value must be 3
Name(_ADR, 0x00000003)
//
// Integrated hub, port 1
//
// Address object for the port. Because the port is implemented on
// integrated hub port #1, this value must be 1
// USB port characteristics object. This object returns the system
// specific USB port configuration information for integrated hub port
// number 1
0x82,0x00,0x00,0x00,, // Revision 2, Ignore color

//
//
// number 1
0xa1,0x10,0x00,0x00, // User visible, front panel, Vertical
// lower, horz. Left, shape = horz. rectangle
//
// Integrated hub, port 2
//
Device( PRT2) { // Address object for the port. Because the port
// is implemented on integrated hub port #2,
// this value must be 2
Name( \_ADR, 0x00000002)
// USB port characteristics object. This object
// returns the system-specific USB port
˓→configuration
// information for integrated hub port number 2
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0xa1,0x12,0x00,0x00, // User visible, front panel, Vertical
// lower, horz. right, shape = horz. rectangle
0xFF,0xFF,0xFF,0xFF}) // Vert. and Horiz. Offsets not supplied
} // Device( PRT3)
} // Device( RHUB)
9.12.1 USB 2.0 Host Controllers and _UPC and _PLD
Platforms implementing USB2.0 host controllers that consist of one or more USB1.1 compliant companion controllers
(e.g. UHCI or OHCI) must implement a _UPC and a _PLD object for each port USB port that can be routed between
the EHCI host controller and its associated companion controller. This is required because a USB Port Capabilities
object implemented for a port that is a child of an EHCI host controller may not be available if the OSPM disables the
parent host controller. For example, if root port 1 on an EHCI host controller is routable to root port 1 on its companion
controller, then the namespace must provide a _UPC and a _PLD object under each host controller’s associated port 1
child object.
Example
...
...
// Host controller (EHCI)
Device( USB0) {
// PCI device#/Function# for this HC. Encoded as specified in
˓→the ACPI
// specification
Name(_ADR, 0xyyyyzzzz)
// Root hub device for this HC #1.
Device(RHUB) {
Name(_ADR, 0x00000000) // must be zero for USB root hub
Device(PRT1) {
Name(_ADR, 0x00000001)
// USB port configuration object. This object returns the system
// Must match the \_UPC declaration for USB1.RHUB.PRT1 as it is
˓→this
// host controller's companion
// provide physical port location info for port 1
˓→this
9.12. _UPC (USB Port Capabilities) 574Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
0x00,0x00,0x00,0x00, // required as this is a standard USB 'A'
// type connector
// lower, horz. Left, shape = horz. Rect.
0x03,0x00,0x00,0x00, // ejectable, needs OPSM eject assistance
//
// Define other ports, control methods, etc
...
...
} // Device( USB0)
// Companion Host controller (OHCI or UHCI)
Device( USB1) {
˓→the ACPI
// Must match the \_UPC declaration for USB0.RHUB.PRT1 as this
˓→host
// controller is a companion to the EHCI host controller
// Must match the \_PLD declaration for USB0.RHUB.PRT1 as this
˓→host
Buffer( 0x14) {
9.12. _UPC (USB Port Capabilities) 575Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
//
...
...
} // Device( USB1)
} // Device( PCI0)
} // Scope( _\SB)
9.12.2 SuperSpeed USB Port and Connector Mapping
This also applies to USB 3.x host controllers. They may have USB 2.0 companion controllers with the switching
capability and without, or Low/Full/High-speed ports in conjunction with SuperSpeed ports on the same Root Hub.
Each USB port implementing _UPC and a _PLD as a child of the xHCI controller will indicate to OSPM which Super
Speed USB and ports are electrically connected to the same connector as Low/Full/High-Speed USB ports on the same
or other controllers.
9.12.3 USB4 Port and USB-C Connector Mapping
USB-C connectors support multiple electrical protocols, including SuperSpeed USB, DisplayPort Alternative Mode,
Thunderbolt™ 3, and USB4. The _PLD objects within the port Device scope for each connected controller port (e.g.
SS USB, DP, PCIe) that are routed to the same USB connector must return the same value, even if no connector is
user-accessible. USB4 tunnels other protocols based on the USB4 speciﬁcation: SS USB and DP are required; PCI
Express is optional. The _UPC object describes to OSPM whether PCIe is tunneled on that port or not.
Scope (\_SB)
{
Device (PLDS) // Device container for board-specific _PLD objects
{
Name (_HID, EISAID ("PNP0A05") )
Name (_UID, "_PLD Object Container")
Name(PLD0, Package () { // USB-C Connector, Left Panel
ToPLD(
PLD_Revision = 2,
PLD_IgnoreColor = 1,
PLD_Width = 8,
PLD_Height = 3,
PLD_UserVisible = 1,
PLD_Panel = "LEFT",
PLD_HorizontalPosition = "CENTER",
PLD_VerticalPosition = "CENTER",
PLD_Shape = "OVAL",
PLD_Ejectable = 1,
PLD_EjectRequired = 1
)
})
Name(PLD1, Package () { // USB-C Connector, Right Panel
ToPLD(
9.12. _UPC (USB Port Capabilities) 576Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PLD_Panel = "RIGHT",
)
})
Name (PLDP, Package () { // Mini DisplayPort connector, Right Panel
ToPLD(
PLD_Height = 5,
PLD_HorizontalPosition = "RIGHT",
PLD_Shape = "HORIZONTALTRAPEZOID",
)
}) // End PLDP
} // End PLDS
Device (UPCS) // Device container for board-specific _UPC objects
{
Name (_UID, "_UPC Object Container")
Name (UPC0, Package () { // Left USB-C connector properties
1, // Connectable
9, // USB-C, USB 2 and SS, no switch
0x0D, // Retimers: 1; PCIe Tunneling, DP AltMode, USB4
0 // Reserved
})
Name (UPC1, Package () { // Right USB-C connector properties
0x0C, // Retimers: 0; PCIe Tunneling, DP AltMode, USB4
})
} // End UPCS
}
Scope(\_SB.HB0) // PCI Express Host Bus
{
Device (XHC0) // XHCI conroller 0
{
Name (_ADR, 0x00030000) // Dev3, Fn0
Device (RHUB) // USB Root Hub
9.12. _UPC (USB Port Capabilities) 577Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
{
Name (_ADR, 0)
Device (PRT1) // Port 1 on Root Hub, Low/Full/High Speed
{
Name (_ADR, 1)
Method (_PLD, 0) { Return (\_SB.PLDS.PLD0) } // Left USB-C Connector

{
})
})
}
{
{
{
{
Method (_UPC, 0) { Return (\_SB.UPCS.UPC0) } // USB Capabilities
}
Device (PRT2) // Port 2 on Root Hub, Low/Full/High Speed
{
Name (_ADR, 2)
Method (_PLD, 0) { Return (\_SB.PLDS.PLD1) } // Right USB-C Connector
Method (_UPC, 0) { Return (\_SB.UPCS.UPC1) } // USB Capabilities
}
Device (PRT3) // Port 3 on Root Hub, SuperSpeed
{
Name (_ADR, 3)
}
Device (PRT4) // Port 4 on Root Hub, SuperSpeed
{
Name (_ADR, 4)
}
Device (PRT5) // Port 5 on Root Hub, SuperSpeed Tunneled over USB4
{
Name (_ADR, 5)
}
Device (PRT6) // Port 2 on Root Hub, SuperSpeed Tunneled over USB4
{
Name (_ADR, 6)
}
}
}
Device (PRP0) // PCI Express Root Port 0
{
Name (_ADR, 0x00050000) // Dev5, Fn0
// Describe routing to Left USB-C connector, USB4 Tunneling
Method (_PLD){ Return (\_SB.PLDS.PLD0) }
}
Device (PRP1) // PCI Express Root Port 1
{
Name (_ADR, 0x00050001) // Dev5, Fn1
// Describe routing to Right USB-C connector, USB4 Tunneling
Method (_PLD, 0) { Return (\_SB.PLDS.PLD1) }
}
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Device(GFX) // Graphics Controller
{
Name(_ADR, 0x00080000) // Dev8, Fn0
// ...
Device(DPR) // Mini DisplayPort Right Connector
{
Name(_ADR, 0)
Method (_PLD, 0) { Return (\_SB.PLDS.PLDP) }
}
Device(UCAL) // USB-C DP AltMode Left
{
Name(_ADR, 1)
Method (_PLD, 0) { Return (\_SB.PLDS.PLD0) }
}
Device(UCAR) // USB-C DP AltMode Right
{
Name(_ADR, 2)
}
Device(UCNL) // USB-C Native USB4 Left
{
Name(_ADR, 3)
}
Device(UCNR) // USB-C Native USB4 Right
{
Name(_ADR, 4)
}
}
Device(PDC0) // USB-C PD Controller (UCSI 0)
{
Name(_HID, EISAID ("PNP0CA0") )
Method (_PLD, 0) { Return (\_SB.PLDS.PLD0) } // Left USB-C connector
}
Device(PDC1) // USB-C PD Controller (UCSI 1)
{
Method (_PLD, 0) { Return (\_SB.PLDS.PLD1) } // Right USB-C connector
}
}
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9.13 _PDO (USB Power Data Object)
Location:
This object is provided within the scope of a Device representing a USB-C connector.
None
A Package as follows:
Package {
SourcePDOList, // Package
SinkPDOList // Package
}
The Revision field describes the revision of the USB PD Specification upon which the
˓→PDOList entries are defined.
The Revision field is encoded as an integer, where the MSB is the major version, and
˓→the LSB is the minor version.
For example, the PD 3.1 specification is represented as the value 0x0301.
The Flags integer is encoded as follows:
Bits [2:0]: Preferred Power Role:
000b: Power Source Only
001b: Power Sink Only
010b: Dual Role Power - with a preference to be a Source
011b: Dual Role Power - with a preference to be a Sink
100b: Dual Role Power with no Source/Sink preference
101b-111b: Reserved
Bit[3]: PPS Supported:
If set, this USB-C connector supports Programable Power Supply (PPS) as specified
˓→in the USB PD Specification.
All other bits: Reserved, and must be 0.
The SourcePDOList and SinkPDOList are defined as follows:
Package {
PDO[0], // Integer (DWORD)
...
PDO[N] // Integer (DWORD)
}
If the USB-C connector does not support either Source or Sink power role, the corresponding SourcePDOList or
SinkPDOList may be omitted. However, if _PDO is implemented, it’s required to have at least one entry in either of
them. Each entry in the list of PDOs is a 32-bit Integer. The encoding for these entries is deﬁned in the USB Power
Delivery Speciﬁcation.
Here is a sample:
Device(UCM0) {USB Connector Manager device
Device(CON0) // USB-C connector 0 {
...
9.13. _PDO (USB Power Data Object) 580Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
...
Name(_PDO, Package(){
0x0301, // USB PD Spec Revision
0x0000000A, // 0011b- PPS Not Supported, Dual Role Power, Prefers to be a
˓→Sink
Package(){ // SourcePDOList
0x2C2F012C // Fixed Supply Source PDO
},
Package(){ // SinkPDOList
0x3503C12C // Fixed Supply Sink PDO
}
})
}
}
9.14 PC/AT RTC/CMOS Devices
Most computers contain an RTC device which also contains battery-backed RAM represented as a linear array of bytes.
There is a standard mechanism for accessing the ﬁrst 64 bytes of non-volatile RAM in devices that are compatible
with the Motorola RTC/CMOS device that was in the IBM PC/AT. Newer devices usually contain at least 128 bytes
of battery-backed RAM. New PNP IDs were assigned for these devices.
Certain bytes within the battery-backed RAM have pre-deﬁned values. In particular, the time, date, month, year,
century, alarm time and RTC periodic interrupt are read-only.
9.14.1 PC/AT-compatible RTC/CMOS Devices (PNP0B00)
The standard PC/AT-compatible RTC/CMOS device is denoted by the PnP ID PNP0B00. If an ACPI platform uses
a device that is compatible with this device, it may describe this in its ACPI namespace. ASL may then read and
write this as a linear 64-byte array. If PNP0B00 is used, ASL and ACPI operating systems may not assume that any
extensions to the CMOS exist.
Note: This means that the CENTURY ﬁeld in the Fixed ACPI Description Table may only contain values between 0
and 63.
Example:
The following is an example of how this device could be described:
Device (RTC0) {
Name(_HID, EISAID("PNP0B00"))
Name (_FIX, Package(1) { EISAID("PNP0B00") } )
Name(_CRS, ResourceTemplate() {
IO(Decode16, 0x70, 0x70, 0x1, 0x2)
}
OperationRegion(CMS1, SystemCMOS, 0, 0x40)
Field(CMS1, ByteAcc, NoLock, Preserve) {
CM00, 8,
, 256,
9.14. PC/AT RTC/CMOS Devices 581Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
CM01, 8,
CM02, 16,
, 216,
CM03, 8
}
}
9.14.2 Intel PIIX4-compatible RTC/CMOS Devices (PNP0B01)
The Intel PIIX4 contains an RTC/CMOS device that is compatible with the one in the PC/AT. But it contains 256
bytes of non-volatile RAM. The ﬁrst 64 bytes are accessed via the same mechanism as the 64 bytes in the PC/AT. The
upper 192 bytes are accessed through an interface that is only used on Intel chips. (See the Intel® 82371AB PIIX4
speciﬁcation for details.)
Any platform containing this device or one that is compatible with it may use the PNP ID PNP0B01. This will allow
an ACPI-compatible OS to recognize the RTC/CMOS device as using the programming interface of the PIIX4. Thus,
the array of bytes that ASL can read and write with this device is 256 bytes long.
Note: This also means that the CENTURY ﬁeld in the Fixed ACPI Description Table may contain values between 0
and 255.
Example:
This is an example of how this device could be described:
Name(_HID, EISAID("PNP0B01"))
Name (_FIX, Package(1) {
EISAID("PNP0B01") }
)
IO(Decode16, 0x72, 0x72, 0x1, 0x2)
}
OperationRegion(CMS1, SystemCMOS, 0, 0x100)
AccessAs(ByteAcc, 0),
CM00, 8,
,256,
CM01, 8,
CM02, 16,
, 224,
CM03, 8,
, 184,
CENT, 8
}
9.14. PC/AT RTC/CMOS Devices 582Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.14.3 Dallas Semiconductor-compatible RTC/CMOS Devices (PNP0B02)
Dallas Semiconductor RTC/CMOS devices are compatible with the one in the PC/AT, but they contain 256 bytes of
non-volatile RAM or more. The ﬁrst 64 bytes are accessed via the same mechanism as the 64 bytes in the PC/AT. The
upper bytes are accessed through an interface that is only used on Dallas Semiconductor chips.
Any platform containing this device or one that is compatible with it may use the PNP ID PNP0B02. This will allow an
ACPI-compatible OS to recognize the RTC/CMOS device as using the Dallas Semiconductor programming interface.
Thus, the array of bytes that ASL can read and write with this device is 256 bytes long.
Description of these devices is similar to the PIIX4 example above, and the CENTURY ﬁeld of the FADT may also
contain values between 0 and 255.
9.15 User Presence Detection Device
The following section illustrates the operation and deﬁnition of the control method-based User Presence Detection
(UPD) device.
The user presence detection device can optionally support power management objects (e.g. _PS0, _PS3) to allow the

OS to manage the device’s power consumption.
The Plug and Play ID of an ACPI control method user presence detection device is ACPI000F.
Table 9.12: User Presence Detection Device
_UPD The current user presence detection reading. [Required]
_UPP User presence detection polling frequency in tenths of seconds. [Optional]
9.15.1 _UPD (User Presence Detect)
This control method returns the user presence detection reading, indicating whether or not the user is currently present
from the perspective of this sensor. Three states are currently deﬁned for UPD sensor readings: absent, present, and
unknown, represented by the values 0x00, 0x01, and 0xFF respectively. The unknown state is used to convey that the
sensor is currently unable to determine user presence due to some environmental or other transient factor. All other
None
An Integer containing the user presence code:
0x00 - Absent: A user is not currently detected by this sensor.
0x01 - Present: A user is currently detected by this sensor.
0xFF - Unknown: The sensor is currently unable to determine if a user is present or absent.
9.15. User Presence Detection Device 583Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.15.2 _UPP (User Presence Polling)
This optional object evaluates to a recommended polling frequency (in tenths of seconds) for this user presence sensor.
A value of zero - or the absence of this object when other UPD objects are deﬁned - indicates that the OS does not
need to poll the sensor in order to detect meaningful changes in user presence (the hardware is capable of generating
None
An Integer containing the recommended polling frequency in tenths of seconds. A value of zero indicates
that polling is not required.
chronously notify OSPM whenever a meaningful change in user presence occurs–relieving the OS of the overhead
9.15.3 User Presence Sensor Events
To communicate changes in user presence to OSPM, AML code should issue a Notify(upd_device, 0x80) whenever
a change in user presence has occurred. The OS receives this notiﬁcation and calls the _UPD control method to
determine the current user presence status.
UPD notiﬁcations should be generated whenever a transition occurs between one of the user presence states (absent,
present, or unknown) - but at a level of granularity that provides an appropriate response without overly taxing the
system with unnecessary interrupts.
9.16 I/O APIC Device
This optional device describes a discrete I/O APIC device that is not bus enumerated (e.g., as a PCI device). Describing
such a device in the ACPI namespace is only necessary if hot plug of this device is supported. If hot plug of this device
is not supported, an MADT I/O APIC entry is sufﬁcient to describe this device.
An I/O APIC device is an I/O unit that complies with either of the APIC interrupt models supported by ACPI. These
interrupt models are described in Section 5.2.12.3 and Section 5.2.12.9.
If the device is an I/O unit that complies with the APIC interrupt model, it is declared using the ACPI000A identiﬁer. If
this device is an I/O unit that complies with the SAPIC interrupt model, it is declared using the ACPI000B identiﬁer. If
this device complies with both the APIC and SAPIC interrupt models (I/OxAPIC), it is declared using the ACPI0009
An I/O APIC device declared using any of the above identiﬁers must contain a _GSB object to report its _GSB (Global
System Interrupt Base) . It must also contain a _CRS object that reports the base address of the I/O APIC device. The
_CRS object is required to contain only one resource, a memory resource pointing to the I/O APIC register base.
Note: Because the _CRS and _GSB methods provide sufﬁcient information, it is not necessary to provide _MAT
under an I/O APIC device.
9.16. I/O APIC Device 584Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
For an I/O APIC device that is described both in the MADT and in the namespace, the base address described in
the MADT entry must be the same as the base address in the IO APIC device _CRS at boot time. OSPM must use
the information from the MADT until such a time as the _CRS and _GSB methods in the namespace device can be
processed. At this point OSPM must ignore the MADT entry.
9.17 Time and Alarm Device
The following sections deﬁne the operation and deﬁnition of the optional control method-based Time and Alarm
device, which provides a hardware independent abstraction and a more robust alternative to the Real Time Clock
(RTC) (See PC/AT RTC/CMOS Devices .)
The time capabilities of the time and alarm device maintain the time of day information across platform power transi-
tions, and keep track of time even when the platform is turned off. It is expected that the time on the platform will be
consistent when different ﬁrmware interfaces are used to query the platform time. For example, a UEFI call to get the
time should return the same time as if the OSPM used the time and alarm device at the same point in time.
The Time and Alarm device can optionally support power management objects (e.g. _PS0, _PS3) to allow the OS to
manage the device’s power consumption.
The Time and Alarm device must support control method _PRW for being enabled to wake up the system. It might
support _DSW or _PSW to provide the functionality to enable or disable the device’s ability to wake a sleep system. On
Hardware-reduced ACPI platforms, _PRW is only required if the device depends on ACPI-deﬁned power resources.
_PRW’s GPEInfo structure is ignored by OSPM. For enabling Wakeup, _DSW and _SxW are used, and the wakeup
event is signaled by the GPIO-signaled ACPI event mechanism (see Section 5.6.5).
The Plug and Play ID of the Time and Wake Alarm device is ACPI000E.
Table 9.13: Time and Alarm Device
_GCP Get the capabilities of the time and alarm device
_GRT Get the Real time
_SRT Set the Real time
_GWS Get Wake status
_CWS Clear Wake Status
_STP Sets expired timer wake policy for the speciﬁed timer.
_STV Sets the value in the speciﬁed timer.
_TIP Returns the current expired timer policy setting of the speciﬁed timer.
_TIV Returns the remaining time of the speciﬁed timer.
9.17.1 Overview
The Time and Alarm device provides an alternative to the real time clock (RTC), which is deﬁned as a ﬁxed feature
hardware device. The wake timers allow the system to transition from the S3 (or optionally S4/S5) state to S0 state
after a time period elapses. In comparison with the Real Time Clock (RTC) Alarm, the Time and Alarm device
provides a larger scale of ﬂexibility in the operation of the wake timers, and allows the implementation of the time
source to be abstracted from the OSPM.
Time and Alarm device provides the OSPM with a ﬁrmware abstraction of time and alarm services that can be ap-
plicable to a variety of hardware designs. The methods for setting and getting real time provide an alternative to the
(RTC).
Time and Alarm devices that implement AC/DC wake service contain two programmable timers that can be conﬁgured
to wake the system depending on the platform’s current power source (AC or DC) when the timers expire. The
9.17. Time and Alarm Device 585Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
two timers, which are referred to as the AC timer and the DC timer, are independent in that they are individually
programmable and applicable without interfering each other. Each of the timers can be programmed with the number
of seconds to elapse from the time the timer is programmed until a wake is requested. When a timer expires, the Time
and Alarm device decides whether to wake the system based on the current power source. If the current power source
is consistent with the timer type that expired, a wake signal will be asserted. Otherwise, the wake signal will not be
asserted.
Time and Alarm devices that implement the AC only (power independent) wake contain one programmable timer that
can be conﬁgured to wake up the system regardless of the platform’s power source when the timer expires. To simplify
the programming interface the AC wake will use the AC timer portion of the AC/DC wake; writes to the DC timer
when AC only wake is supported will be ignored.
To simplify the programming interface for the time and alarm device, timer expiration events will persist. This means
that if the OSPM programs a wake timer that expires before the OSPM completes the transition into S3 (or S4/S5 if

asserted.
supported) the time and alarm device will wake the system immediately after the OSPM completes the transition. Fig.
9.6 illustrates this behavior.
Fig. 9.5: Persistence of expired timer events
The time and alarm device will provide the OSPM with an interface to query the status of the wake timers and discover
what timers have expired. This interface enables the OSPM to discover the wake source. The status of wake timers
can be reset by setting the wake alarm; the OSPM may clear the alarm status using the clear wake status method. All
expired wake timer must be cleared if the OSPM requires the platform to stay in S3 (S4/S5), otherwise the expired
timers will immediately wake up the system.
For the AC/DC wake services, and in case the current power source is inconsistent with the timer type that expires,
an expired timer wake policy value, in units of seconds, is deﬁned that enables the time and alarm device to wake
the system when the power source corresponding to the expired timer becomes active (wake either immediately, after
some time period, or never). The expired timer wake policy is applicable only on devices that support AC/DC wake
and only when the timer expires and the power source is not consistent with the timer type. The expired timer policy
is applied in conjunction with expired timer persistence described earlier.
For example, if a mobile platform programs the AC timer to be 2 hours long and DC timer to be 4 hours long and then
transitions from the S0 state to S3 state at 1:00 AM, the AC timer is set to expire at 3:00 AM and the DC timer is set
to expire at 5:00 AM. For the AC Timer, a expired timer wake policy value is programmed as 60 seconds.
9.17. Time and Alarm Device 586Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
If the platform is unplugged from AC power at 1:40 AM and remains unplugged, the Time and Alarm Device will not
wake up the system at 3:00 AM. If the platform remains on DC power until 5:00 AM when the DC timer expires, a
wake signal will then be asserted. The following graph illustrates the above example.
Fig. 9.6: System transitions with WakeAlarm — Timer
If the AC power is plugged in again at 4:00 AM, then the system will be woken up at 4:01 AM due to the AC expired
timer wake policy value setting. The following graph illustrates this.
Fig. 9.7: System transitions with WakeAlarm — Policy
The Time and Alarm device can support a range of services, the OSPM evaluates the _GCP object to get the supported
capabilities of the device. If the capabilities indicate that the device supports time services, the OSPM evaluates the
_GRT and _SRT objects to get and set time respectively.
If alarm services are supported by the device, the OSPM evaluates the _STV object to program both the AC and DC
timer values. The values, which are in units of seconds, indicate the elapsed time before the timer expires. OSPM
evaluates the _TIV object to read the current AC and DC timer values (seconds remaining until expiration).
OSPM evaluates the _STP object to set timer policies for both the AC and DC timers OSPM reads the current timer
9.17. Time and Alarm Device 587Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
policy by evaluating the _TIP object, which return policy settings for both the AC and DC timer.
The OSPM evaluates the _GWS object to identify expired timers that may have waked the platform. The OSPM
must evaluate the _CWS object to clear any expired timer events that can prevent the system from performing a sleep
transition according the expired timer wake policy, and the expired timer persistence described above.
The Time and Alarm device, if implemented with wake support, must support waking up the system from S3. Waking
from S4/S5 support is optional.
9.17.2 _GCP (Get Capability)
This object is required and provides the OSPM with a bit mask of the device capabilities. The device can implement
the time function in addition to the wake function. The capabilities bitmask will indicate to the OSPM what support is
implemented. If the platform implements both AC and DC timers then it is capable of waking up based on the power
source.
Arguments:(0)
A 32-bit integer containing a result bitmask as follows:
Bit [0] - 1 = AC wake implemented, 0 = not supported
Bit [1] - 1 = DC wake implemented, 0 = not supported
Bit [2] - 1 = Get/Set real time features implemented, 0 = not supported
Bit [3] - 1 = Real time accuracy in milliseconds, 0 = Real time accuracy in seconds
Bit [4] - 1 = _GWS returns correct values for wakes from S4/S5 caused by timer. 0 = not supported
Bit [5] - 1 = Wake supported from S4 on AC, 0 = Wake not supported from S4 on AC
Bit [6] - 1 = Wake supported from S5 on AC, 0 = Wake not supported from S5 on AC
Bit [7] - 1 = Wake supported from S4 on DC, 0 = Wake not supported from S4 on DC
Bit [8] - 1 = Wake supported from S5 on DC, 0 = Wake not supported from S5 on DC
Bit [9] to Bit [31] are reserved and must be 0.
Note: The following rules apply for the _GCP returned value:
• If wake on DC is supported (bit 1), then wake from AC (bit 0) must be supported
• If wake on AC from S5 is supported (bit 6), then wake on AC from S4 must be supported (bit 5)
• If wake on AC from S4 is supported (bit 5), then wake on AC must be supported (bit 0)
• If wake on DC from S5 is supported (bit 8), then wake on DC from S4 must be supported (bit 7)
• If wake on DC from S4 is supported (bit 7), then wake on DC must be supported (bit 1)
• If wake on DC from S4 is supported (bit 7), then wake on AC from S4 must be supported (bit 5)
• If wake on DC from S5 is supported (bit 8), then wake on AC from S5 must be supported (bit 6)
• If wake from S4/S5 is supported (bits 5-8), then _GWS must be supported (bit 4)
9.17. Time and Alarm Device 588Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.17.3 _GRT (Get Real Time)
This object is required if the capabilities bit 2 is set to 1. The OSPM can use this object to get time. The return value
is a buffer containing the time information as described below.
Arguments: (0)
A buffer containing the time information, in the following format:
Buffer(){
WORD Year; // 1900 - 9999
BYTE Month; // 1 - 12
BYTE Day; // 1 - 31
BYTE Hour; // 0 - 23
BYTE Minute; // 0 - 59
BYTE Second: // 0 - 59
BYTE Valid; // 0 - Time is not valid (request failed); 1 - Time is
˓→valid
WORD milliseconds, // 1-1000
WORD TimeZone; // -1440 to 1440 or 2047 (unspecified)
BYTE Daylight;
BYTE Pad2[3]; // Reserved, must be zero
}
9.17.4 _SRT (Set Real Time)
This object is required if the capabilities bit 2 is set to 1. The OSPM can use this object to set the time. The argument
is a buffer containing the time information, as deﬁned above.
Buffer(){
BYTE Second; // 0 - 59
BYTE Pad1;
}
An Integer:
0 - success 0xFFFFFFFF- Failed
Note:
Time is maintained using a battery backed time device (e.g. a real time clock).
The time will always be local time; the time zone value can be used to determine the offset from UTC.
9.17. Time and Alarm Device 589Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Time zone ﬁeld is the number of minutes that the local time lags behind the UTC time. (i.e. time zone = UTC - local
time). The time zone is in 2’s complement format.
Time zone value of 2047, means that time zone value is not speciﬁed, and no relation to UTC can be inferred.
Daylight is a bitmask containing the daylight savings time information for the time, as follows:
Bit [0]: 1 = the time is affected by daylight savings time, 0= time is not affected by daylight savings. This value
does not indicate that the time has been adjusted for daylight savings time. It indicates only that it should be
adjusted when the time enters daylight savings time.
Bit [1]: 1= the time has been adjusted for daylight savings time, 0= the time hasn’t been adjusted for daylight
savings.
When entering daylight saving time, if the time is affected, but hasn’t been adjusted (DST = 1), use the new calculation:
• The date/time should be increased by the appropriate amount.
• The TimeZone should be decreased by the appropriate amount (EX: +480 changes to +420 when moving from
PST to PDT).
• The Daylight value changes to 3.
When exiting daylight saving time, if the time is affected and has been adjusted (DST = 3), use the new calculation:
• The date/time should be decreased by the appropriate amount.
• The TimeZone should be increased by the appropriate amount.
• The Daylight value changes to 1.
9.17.5 _GWS (Get Wake alarm status)

savings.
This object is required if the capabilities bit 0 is set to 1. It enables the OSPM to read the status of wake alarms.
Expired wake timers will wake the platform even if the transition to a sleep state was completed after the wake timer
has expired. This method enables the OSPM to retrieve the status of wake timers and clear any of them if needed.
Arg0 - Timer Identiﬁer (Integer (DWORD)): indicates the timer to be cleared:
0x00000000 - AC Timer
0x00000001 - DC Timer
An Integer (DWORD) containing current expired timers in bit ﬁeld
Bit [0]- 1 = timer expired, 0 = timer did not expired
Bit [ 1]- 1= timer caused a platform wake, 0 = timer did not cause a platform wake
Bit [31:2] reserved and should be 0.
9.17. Time and Alarm Device 590Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.17.6 _CWS (Clear Wake alarm status)
This object is required if the capabilities bit 0 is set to 1. It enables the OSPM to clear the status of wake alarms.
has expired. This method enables the OSPM to clear the status of expired wake timers.
An Integer (DWORD) containing current expired timer wake policy:
9.17.7 _STP (Set Expired Timer Wake Policy)
This object is required if the capabilities bit 0 is set to 1. It sets the expired timer wake policy. The policy is applied
when a corresponding timer expired but the wake signal was not asserted as a result of the power source. The platform
accumulates elapsed time on the power source and asserts the wake signal when the elapsed timer on the power source
exceeds the expired timer wake policy value. Power source transitions do not reset the expired timer wake policy
values. When the Wake Alarm device asserts the wake, the expired timer wake policy values of both the AC timer and
DC timer are reset to 0xFFFFFFFF automatically by hardware.
Arguments:(2)
Arg0 - TimerIdentiﬁer (Integer(DWORD)): indicates the timer to be set:
Arg1 - ExpiredTimerWakePolicy (Integer(DWORD)): indicates the expired timer wake policy:
0x00000000 - The timer will wake up the system instantly after the power source
changes.
0x00000001 - 0xFFFFFFFE: time between the power source changes and the timer
wakes up the system (in units of second).
0xFFFFFFFF - The timer will never wake up the system after the power source changes.
An Integer containing a result code as follows:
0x00000000 - Succeeded to set the expired timer wake policy.
0x00000001 - Failed to set the timer policy. Actual timer policy unknown.
9.17. Time and Alarm Device 591Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.17.8 _STV (Set Timer Value)
This object is required if the capabilities bit 0 is set to 1. It sets the timer to the speciﬁed value. As deﬁned in _TIV ,
the value indicates the number of seconds between the time when the timer is programmed and the time when it
expires. When the Wake Alarm device asserts the wake signal, the timer value is automatically reset to 0xFFFFFFFF
(disabled).
Arg0 - TimerIdentiﬁer (Integer (DWORD)): indicates the timer to be set:
Arg1 - TimerValue (Integer): indicates the value to be set.
0x00000000 - Succeeded to set timer value.
0x00000001 - Failed to set timer value. Actual timer value unknown.
9.17.9 _TIP (Expired Timer Wake Policy)
This object is required if the capabilities bit 0 is set to 1. It returns the current expired timer wake policy setting of the
speciﬁed timer.
Arg0 - TimerIdentiﬁer (Integer (DWORD)): indicates the timer to be read:
0x00000000 - The timer will wake up the system instantly after the power source changes
0x00000001 - 0xFFFFFFFE: Time between the power source changes and the timer wakes up
the system ( in units of seconds)
0xFFFFFFFF - The timer will never wake up the system after the power source changes
9.17.10 _TIV (Timer Values)
This object is required if the capabilities bit 0 is set to 1. It returns the remaining time of the speciﬁed timer before
that expires.
Arg0 - TimerIdentiﬁer (Integer(DWORD)): indicates the timer to be read:
9.17. Time and Alarm Device 592Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
An Integer containing the current timer value. A value of 0xFFFFFFFF indicates that the timer is disabled.
9.17.11 ACPI Wakeup Alarm Events
The Wake Alarm, device as a generic hardware, supports control methods _PSW and _PRW to wake up the system
and issues a Notify(<device>, 0x2) on the wakeup alarm device.
9.17.12 Relationship to Real Time Clock Alarm
Though both of the devices support wakeup timers to wake up system from sleeping state, they work independently.
The Real Time Clock Alarm is deﬁned as a ﬁxed feature hardware whereas Time and Alarm device is deﬁned as a
generic hardware and can replace or coexist with the real time clock. OSPM may choose which device to utilize to
provide timed wake capability.
9.17.13 Time and Alarm device as a replacement to the RTC
The Time and Alarm device can be an alternative to the RTC on some platforms where the legacy RTC hardware is
not available, on these platforms the OSPM can use the Time and Alarm device to obtain time and set wake alarms.
For platforms that don’t require AC/DC wake service (e.g. a platform that have one power source only) the AC timer
can be used to provide all the functions that were traditionally provided by the RTC. Using the capabilities object the
Time and Alarm device can provide a scalable range of services to the OSPM.
9.17.14 Relationship to UEFI time source
The Time and Alarm device must be driven from the same time source as UEFI time services. This ensures that the
platform has a consistent value of real time (time of day) and wake alarms. The OSPM can interact with this value
using either ACPI or UEFI.
• OSPM must use only one runtime interface to conﬁgure/query the platform alarm(s); undeﬁned behavior may
occur if the two wakeup interfaces are used on the same hardware.
• If OSPM is trying to set an alarm using EFI runtime services, the alarm should be honored regardless of the
power source (i.e. if the platform has an independent timer for each power source, they should both be conﬁgured
with that alarm).
9.17.15 Example ASL code
The following ASL code serves as an example of how the Time and Alarm Device could be implemented. It is beyond
the capability and the scope of this speciﬁcation to provide a complete hardware implementation example.
Example 1: Deﬁne an ACPI Wake Alarm device
Device(\_SB.AWAK){
Name(_HID, "ACPI000E") //device ID
Name(_PRW, Package(){...}) //enable or disable to wake up the system
OperationRegion(CMOP, EmbeddedControl, ...)
Field(CMOP, ByteAcc, ...){
// timer status and policies
}
Method(_GCP) {
Return (0x03) // Both AC and DC alarms are implemented;
9.17. Time and Alarm Device 593Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
// Time capability is NOT supported
}
Method(_STP, 2){
If(LEqual(Arg0, 0) {
Store(Arg1, ...) // Set AC timer policy
}
Else {
Store(Arg1, ...) // Set DC timer policy
}
Return(0)
}
Method(_TIP, 1){
If(LEqual(Arg0, 1) {
Store(..., Local0) // Get DC timer policy
}
Else {
Store(..., Local0) // Get AC timer policy
}
Return (Local0)
}
Method(_STV, 2){
Store(Arg1, ...) // Set AC timer value
}
Else {
Store(Arg1, ...) //Set DC timer value
}
Return(0)
}
Method(_TIV, 1){
Store(..., Local0) //Get DC timer value
}
Else {
Store(..., Local0) //Get AC timer value
}
}
Method(_GWS, 1){
Store(..., Local0) //Get DC timer wake status
}
Else {
Store(..., Local0) //Get AC timer wake status
}
}
Method(_CWS, 2){
Store(0, ...) //Clear AC Wake status
}
Else {
Store(0, ...) //Clear DC Wake status
}
Return(0)
}
} // end of ACPI Wake Alarm device object
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Scope(\_GPE) { // Root level event handlers
Method(_Lxx){
Store(One, ...)
Notify(\_SB.AWA, 0x2) //notify the OSPM of device wake
}
} // end of \_GPE scope
Example 2: Deﬁne an ACPI Real Time device on a HW-Reduced ACPI platform
Device(\_SB.I2C1) //The controller used to access the RTC hardware
{
Name (_HID, ...)

}
Return(0)
}
}
Else {
}
}
}
Else {
}
}
}
Else {
}
Return(0)
}
}
{
... // Other objects required for this I2C controller
// Track status of SPB OpRegion availability for this controller
Name(AVBL, 0)
{
/*9 is the OpRegion type for SPB. (8 == GPIO, etc) */
If (Lequal(Arg0, 9))
1{
Store(Arg1, ^AVBL)
}
}
}
Device(\_SB.TAAD) { //The Time and Alarm Device
Name (_HID, "ACPI000E")
Scope(\_SB.I2C1) //OpRegion declaration must appear under the
˓→controller
{
OperationRegion(TOP1, GenericSerialBus, 254, 0x100)
{
Connection(I2CSerialBusV2(0x4a,,400000,,"\\_SB.I2C1",,,,,)),
//Connection to the controller for the following field accesses
AccessAs(BufferAcc, AttribWord), //AccessProtocol for the following field(s)
Y, 8,
M, 8,
D, 8,
H, 8,
Mi,8,
S, 8,
P, 8,
Ms, 8,
Tz, 8,
Dl, 8,
P2, 8
} // End of Field
} // End of Scope
Method (_GCP, 0x0, NotSerialized)
{
Return(0x4) //Implements Real Time interface, but no alarms
}
Method(_GRT, 0x0, NotSerialized)
{
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If(LNotEqual(\_SB.TC1.AVBL, 1)) // Verify that SPB OpRegion is available
// for this access
{
Return(0)
}
Name(BUFF, Buffer(4){}) // Create SerialBus data buffer as BUFF
CreateWordField(BUFF, 0x02, DATA) // DATA = Data (Byte)
Name(BUF2,Buffer(0x10){}) // Create buffer to hold the Real Time structure
//as BUF2
CreateWordField(BUF2, 0x0,Y) // Year
CreateByteField(BUF2,0x2,M) // Month
...
CreateByteField(BUF2,0xc,Dl) // Dl
CreateByteField(BUF2,0xd,P2) // Pad2
Store(\_SB.I2C1.Y, BUFF) // Get each member from the OpRegion and store
// in the structure
Store(DATA,Y)
Store(\_SB.I2C1.M, BUFF)
Store(DATA,M)
...
Store(\_SB.I2C1.Dl, BUFF)
Store(DATA,Dl)
Store(\_SB.I2C1.P2, BUFF)
Store(DATA,P2)
Return(BUF2) // Success -> return what was last in buffer
}
Method(_SRT,0x1, NotSerialized)
{
// Verify that SPB OpRegion is available for this access
If(LNotEqual(\_SB.I2C1.AVBL, 1))
{
Return(0)
}
CreateWordField(Arg0,0x0,Y) // Create Fields to access each member of the
// input data
...
CreateByteField(Arg0,0xd,P2)
Store(Store(Y, \\_SB.I2C1.Y), BUFF) // Store each input member into the hardware,
// and set the transaction status into BUFF
If(LEqual(STAT, 0x00)) // transaction was *NOT*successful
{
Return(0xFFFFFFFF)
}
...
Store(Store(P2, \\_SB.I2C1.P2), BUFF)
If(LEqual(STAT, 0x00)) // Transaction was \_NOT_successful
{
}
}
Name(_DEP, Package() {"\\_SB.I2C1"}) // Identify the OpRegion dependency for
// this device
} // End of Time and Alarm Device definition
9.17. Time and Alarm Device 596Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.18 Generic Buttons Device
The-Generic-Button device is a standard device for reporting button events via hardware interrupts, and mapping
those interrupts to speciﬁc usages deﬁned in the Human Interface Device (HID) speciﬁcation. In order to express the
functionality of a button to the OS, two pieces of information are required: Usage of the HID Control, and Usage of the
HID Collection that the Control belongs to. A Usage is a combination of a Usage Page and Usage ID. For example, the
V olume Up button is identiﬁed as the V olume Up Usage (Usage Page 0x0C, Usage Id 0xE9) in the Consumer Control
Collection (Usage Page 0x0C, Usage Id 0x01).
The Plug and Play ID of the Generic Button device is ACPI0011.
Note: If the Power button is described using this device, it must also support the Power Button Override feature
deﬁned in Section 4.8.2.2.1.3.
Table 9.14: Generic Buttons Device Child Objects
_CRS Lists the resources consumed by the Generic Button device. Only interrupt resources (GpioInt()
and Interrupt() ) are valid for this device. Each interrupt listed must signal one distinct button
event.
_DSD Provides a list of HID Button Descriptors, as deﬁned by UUID FA6BD625-9CE8-470D-A2C7-
B3CA36C4282E. Only HID 2-state button usages are valid for the descriptors returned for this
device.
Note: If there are more HID Button Descriptors returned by _DSD than there are interrupts listed in _CRS, behavior
is OS-speciﬁc.
9.18.1 Button Interrupts
Interrupts for the Generic Buttons Device are required to be edge-triggered and not level-triggered since there is no
interface deﬁned for the driver to quiesce the interrupt line once the interrupt is received. The polarity (ActiveLow/High
vs. ActiveBoth) of the interrupt is determined by the Usage Type of the HID Usage associated with the interrupt, as
described in the table below.
Table 9.15: Usage Types and Interrupt Polarity
Usage Type Interrupt Polarity Explanation
OSC - One Shot Control ActiveHigh/ ActiveLow An interrupt should be triggered on a button press. This
is for a toggle button. On every such event (interrupt),
the Operating System will toggle the internal property
of the entity that it controls. Example: Mute button
MC - Momentary Control ActiveBoth An interrupt should be triggered on both the button press
and release. Example: Left mouse button.
RTC - Re-trigger Control ActiveBoth An interrupt should be triggered on both the button press
and release. While the button is pressed, the Operat-
ing System will repeatedly re-execute the action that it
would take when the button is pressed. Example: A V ol-
ume Up button when pressed and held, will repeatedly
increment the V olume.
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Table 9.15 – continued from previous page
OOC - On/Off Control ActiveHigh/ ActiveLow
OR ActiveBothActiveHigh/ActiveLow polarity should be speciﬁed if
implemented as a button that goes back to its initial
state automatically. E.g. A Push Button or a spring-
loaded Slider switch. Only one interrupt should be ﬁred
for press/release pair. Example: A spring-loaded Wire-
less Radio Slider Switch. ActiveBoth polarity should
be speciﬁed if implemented as a button that stays in its
state until the user moves it again. E.g. A button that
stays in pressed state, or a Slider switch that sticks to its
position. Example: Wireless Radio Slider Switch.
9.18.2 Button Usages and Collections
The HID Usage tables have an extensive list of Standardized Usages for various kinds of buttons. Some of the common
buttons found on Computing devices and their Usages are listed in the table below.
For the full list, see “HID Usage Tables”, available from “Links to ACPI-Related Documents” (http://ueﬁ.org/acpi)
under the heading “HID Usage Tables”.
Buttons are grouped under an HID Collection. Several HID Collections are commonly understood by Operating
Systems, e.g., Keyboard Collection, Consumer Controls Collection, Wireless Radio Controls Collection, etc.
Table 9.16: Common HID Button Usages
Button Usage Page / Usage Usage
TypeInterrupt
PolaritySpec Reference
Power Generic Desktop Page (0x01)
System Power Down (0x01)OSC ActiveBoth * USB HID Usage Tables, version
1.2: see https://www.usb.org/hid,
under the heading HID Usage Ta-
bles
V olume Up Consumer Page (0x0C) V ol-
ume Increment (0xE9)RTC ActiveBoth USB HID Usage Tables, version
bles
V olume
DownConsumer Page (0x0C) V ol-
ume Decrement (0xEA)RTC ActiveBoth USB HID Usage Tables, version
bles
Camera
ShutterCamera Control Page (0x90)
Camera Shutter (0x21)OSC Active High/
Active LowUSB Review Request 49: Camera
Controls - see https://www.usb.org/
hid, under the heading Approved
Usage Table Review Requests
Display
Brightness
UpConsumer Page (0x0C) Dis-
play Brightnes s Increment
(0x6F)RTC ActiveBoth USB Review Request 41: Dis-
play Brigtness Controls - see https:
//www.usb.org/hid, under the head-
ingApproved Usage Table Review
Requests
9.18. Generic Buttons Device 598Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.16 – continued from previous page
Display
DownConsumer Page (0x0C) Dis-
play Brightnes s Decrement
Requests
Wireless Ra-
dio ButtonGeneric Desktop Page (0x01)
Wireless Radio Button (0xC6)OOC ActiveHigh/
ActiveLowUSB Review Request 40: HID Ra-
dio On/Off Usages - see https://
www.usb.org/hid, under the heading
Approved Usage Table Review Re-
quests
Wireless
Radio Slider
SwitchGeneric Desktop Page (0x01)
Wireless Radio Slider Switch

Requests
Display
Requests
quests
Wireless
(0xC8)OOC ActiveBoth USB Review Request 40: HID Ra-
quests
Note: * The System Power Down Usage (Page:01, ID: 81) has Type OSC, although its interrupt must be ActiveBoth
in order to allow drivers to perform functions based on “hold-down” timing. This is an exception to the Usage Type
Rules for Interrupt Polarity (see Table 9.15).
9.18.3 Generic Buttons Device Example
Device(BTNS)
{
Name(_HID, "ACPI0011")
GpioInt(Edge, ActiveBoth...) {pin} //Vol Down
GpioInt(Edge, ActiveBoth...) {pin} //Vol Up
GpioInt(Edge, ActiveBoth,...) {pin} //Power (MUST BE ACTIVEBOTH!)
})
Name(_DSD, Package(2) {
//UUID for HID Button Descriptors:
//ToUUID("FA6BD625-9CE8-470D-A2C7-B3CA36C4282E"),
//Data structure for this UUID:
Package(5) {
0, //Declare a Collection
1, //Unique ID for this collection
0, //It is a top-level collection
0x0c, //Usage Page ("Consumer")
0x01 //Usage ("Consumer Control")
},
0, //Declare another Collection
2, //Unique ID for this collection
0, //Also a top-level collection
0x01, // Usage Page ("Generic Desktop")
0x80 //Usage ("System Control")
},
9.18. Generic Buttons Device 599Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
1, //Declare a Control
0, //Interrupt index in \_CRS for Vol Down
1, //In the "Consumer Control" collection
0xEA //Usage ("Volume Decrement")
},
1, //Declare another Control
2, //Interrupt index for the Power Button
2, //In the "System Control" collection
0x01, //Usage Page ("Generic Desktop")
0x81 //Usage ("System Power Down")
},
1, //Interrupt index for the Vol Up button
0xE9 //Usage ("Volume Increment")
},
1, //Another Control
0xFF, //No Interrupt for this one... e.g. OS-
// specific signaling for Rotation Lock
0x0C, //Usage Page ("Consumer")
0x245 //Usage ("AC Rotate")
}
}
})
}// End Device
9.19 NVDIMM Devices
9.19.1 Overview
In order to handle NVDIMMs, the OS must ﬁrst be able to detect and enumerate the NVDIMMs. To facilitate the plug
and play discovery of NVDIMM and driver loading, ACPI namespace devices are used.
9.19.2 NVDIMM Root Device
The NVDIMM root device is represented by an ACPI namespace device with an _HID of “ACPI0012” (see Section
6.1.5 and Table 5.205). If the platform supports NVDIMMs, then platform ﬁrmware shall report one NVDIMM root
device in the SB scope (see Section 5.3.1). This device allows the OS to trigger enumeration of NVDIMMs through
NFIT (see Table 5.126) at boot time and re-enumeration at root level via the Section 6.5.9 during runtime.
For each NVDIMM present or intended to be supported by platform, platform ﬁrmware also exposes an NVDIMM
device (see Section 9.19.3) under the NVDIMM root device.
9.19. NVDIMM Devices 600Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.19.3 NVDIMM Device
Each NVDIMM is represented by an ACPI namespace device under the NVDIMM root device (see Section 9.19.2)
with an _ADR (see Section 6.1.1) containing the NFIT Device Handle. The NFIT Device Handle is a 32-bit value. Bit
[31] indicates the format of the NFIT Device Handle.
If Bit [31] is clear, then Bits [30:0] are deﬁned as follows:
• Bits [3:0] DIMM number within the memory channel
• Bits [7:4] memory channel number within the memory controller
• Bits [11:8] memory controller ID within the socket
• Bits [15:12] socket ID within the node controller, if any
• Bits [27:16] node controller ID, if any
• Bits [31:28] Reserved
If Bit [31] is set, then Bits [30:0] are deﬁned as follows:
• Bits [30:0] platform unique value assigned by the platform ﬁrmware that is consistent across boots when the
NVDIMM is in the same physical location but may change if the NVDIMM is in a different physical location.
NOTE: Bit 31 was introduced in ACPI Speciﬁcation 6.4, so software compliant with previous versions of ACPI might
parse the structure as if bit [31] is set to zero.
Table 5.196 deﬁnes NVDIMM Device Notiﬁcation Values for an NVDIMM device.
Information about the Label Storage Area on the NVDIMM is provided by the _LSI (see Section 6.5.10.1) method.
The OSPM uses the methods _LSR (see Section 6.5.10.2) and _LSW (see Section 6.5.10.3) to read and write to the
Label Storage Area. The format of the Label Storage Area data is deﬁned in UEFI.
9.19.4 Example
An example name space is shown below for a platform containing one NVDIMM:
Device (NVDR) // NVDIMM root device
{
Name (_HID, "ACPI0012")
Method (_STA) {...}
Method (_FIT) {...}
Method (_DSM, ...) {
...
}
Device (NVD) // NVDIMM device
{
Name(_ADR, h) //where h is NFIT Device Handle for this NVDIMM
...
}
}
}
}
9.19. NVDIMM Devices 601Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.19.5 Loading NVDIMM drivers
While using ACPI namespace devices allows for OS handling of NVDIMMs in a standard manner, the format of the
address ranges described by this scheme may still vary depending on the vendor (or even different NVDIMM version
of the vendor). For example, the command and status values supported by a Block Control Window are vendor speciﬁc
and possibly even vary for a given vendor.
The NVDIMM Control Region Structure (see Section 5.2.26.6) includes a Vendor ID, Device ID, and Revision ID.
Because an NVDIMM could be a combination device consisting of different region types (e.g. Persistent Memory and
Block), a Region Format Interface Code is also included to indicate the region type as well as the speciﬁc implemen-
tation within that type. This allows for variability across vendors as well as within vendor offerings.
These ﬁelds enable loading of drivers for managing the NVDIMM as well as for handling the address ranges supported
by the NVDIMM. The Region Format Interface Code is used to load generic drivers for the following: management
driver, persistent memory driver and block driver. A vendor speciﬁc driver for each of the above can be loaded by
matching on Vendor ID, Device ID and Revision ID (in addition to the Region Format Interface Code).
Region Format Interface Code requirements shall be met by all compliant NVDIMMs. Any Vendor speciﬁc extensions
are only allowed to extend on top of the Region Format Interface Code requirements.
It is assumed that the OSPM is capable of loading the Region Format Interface Code speciﬁc driver or vendor speciﬁc
drivers based on such discovery. This scheme is as shown in the following ﬁgure.
Fig. 9.8: Vendor/Device Speciﬁc Driver Loading
The Subsystem Vendor ID, Subsystem Device ID and Subsystem Revision ID ﬁelds allow selection of speciﬁc solution
provider drivers that may span across devices from multiple vendors.
9.19.6 Hot Plug Support
The NVDIMM memory hot plug representation of the ACPI Name Space is described in this section. The NVDR
device is the NVDIMM root device, the NVD1 and NVD2 are NVDIMM devices, the MEM0 is memory module
device corresponding to the NVD1 and NVD2 devices. The _FIT method under NVDR device returns all NFIT
entries including the hot added devices.
Device (NVDR) // Root device
{
9.19. NVDIMM Devices 602Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
...
}
Device (NVD1) // NVDIMM1
{
Name(_ADR, h1) // where h1 is NFIT Device Handle for this NVDIMM1
...
}
}
Device (NVD2) // NVDIMM2
{
Name(_ADR, h2) // where h2 is NFIT Device Handle for this NVDIMM2
...
}
}
}
Device (MEM0) // Memory module
{
Method (_CRS) {...}
}
{
Method (_L00) {
Notify (\_SB.NVDR, 0x80) // Notify to NVDIMM root device
Notify (\_SB.MEM0, 1) // Device Check to Memory Module
}
}
Hot Plugged memory is indicated to OS using ACPI Name Space device with PNPID of PNP0C80. The NFIT entries
created by the hot plug NVDIMM are communicated by the ACPI Name Space device with ACPI0012.
NVDIMM hot add ﬂow:
1. Prior to hot add of the NVDIMM, the corresponding ACPI Name Space devices, NVD1, NVD2 return an address
from _ADR object (NFIT Device handle) which does not match any entries present in NFIT (either the static
or from _FIT) indicating that the corresponding NVDIMM is not present. Further ACPI Name Space Device
MEM0 returns _STA status of 0 indicating that the devices are not present, not enabled and not functioning.
2. On hot add:
a. Send Notify 0x80 to NVDR to cause NVDIMM bus driver to enumerate all the devices under the
root hierarchy

{
}
{
}
}
b. NVDIMM bus driver evaluates the _FIT method under the NVDR device and identiﬁes the changes
to the NVDIMM devices present (by identifying new NFIT Device handles that have been added).
c. NVDIMM bus driver now ﬁnds matching entries for addresses returned by _ADR objects of NVD1
and NVD2 and loads the corresponding drivers.
d. Send Notify Device Check to MEM0 to cause re-enumeration of device causing the memory
manager to add _CRS range to the memory pool.
3. MEM0 will now report all the memory ranges now created and made visible.
9.19. NVDIMM Devices 603Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.19.7 NVDIMM Root Device _DSMs
A device speciﬁc method (_DSM) for an NVDIMM root device is described below.
9.19.7.1 Input Parameters:
Arg0 - UUID (set to 2f10e7a4-9e91-11e4-89d3-123b93f75cba)
Arg1 - Revision ID (set to 1)
Arg2 - Function Index
Table 9.17: NVDIMM Root Device Function Index
Function Index Description
0 Query command implemented (see Section 9.1.1)
1 Query Address Range Scrub (ARS) Capabilities (see Section 9.19.7.4)
2 Start Address Range Scrub (ARS) (see Section 9.19.7.5)
3 Query Address Range Scrub (ARS) Status (see Section 9.19.7.6)
4 Clear Uncorrectable Error (see Section 9.19.7.7)
5 Translate SPA
6 Reserved
7 ARS Error Inject
8 ARS Error Inject Clear
9 ARS Error Inject Status Query
0xA Query ARS Error Inject Capabilities
0xB - 0xFFFF Reserved
Arg3 - a package containing parameters for the function speciﬁed by the UUID ,Revision ID , and Function Index . The
layout of the package for each command along with the corresponding output is illustrated in the following tables. The
input and output package are a list of bytes (Buffer).
9.19.7.2 Address Range Scrubbing (ARS) Overview
ARS allows the platform to communicate memory errors to system software. This capability allows system software
to prevent accesses to addresses with uncorrectable errors in memory.
The ARS functions are system scope and are not speciﬁc to a single NVDIMM, i.e., they manage all NVDIMMs
present in the system.
TheQuery ARS Capabilities function indicates if ARS is supported for an address range and to discover system-wide
attributes, such as the maximum amount of data that can be returned from a Query ARS Status function and whether
the platform provides an asynchronous ACPI notiﬁcation that a new uncorrectable error has been discovered.
Only one scrub can be in progress system wide at any given time. OSPM should ﬁrst issue a Query ARS Status
function and ensure no ARS is in progress before issuing a Start ARS function. If a successful status is returned, the
extended status of the Query ARS Status function indicates to OSPM one of the following:
• An ARS has been completed and ARS results are returned. These results should be processed by OSPM before
issuing another Start ARS function. When a new address range scrub operation is started, the previous ARS
results are lost.
• An ARS is in progress and no ARS results are returned. A Start ARS function fails while an ARS is in progress.
OSPM should periodically issue Query ARS Status functions until the ARS is no longer in progress.
9.19. NVDIMM Devices 604Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• There has been no ARS since the platform was booted so there are no ARS results returned. A new Start ARS
function may be issued.
• An ARS stopped prematurely and partial results are returned. If the platform has more data to return than will
ﬁt in the Max Query ARS Status Output Buffer Size (see Section 9.19.7.4). OSPM may issue Start ARS and
Query ARS Status functions in a loop and retrieve all of the ARS Error Records, modifying the ARS Start SPA
Address and length with each iteration.
If aStart ARS function is issued, the OSPM provides the ARS Start SPA Address and ARS Length for the range to
be scrubbed. If the previous ARS stopped prematurely, these ﬁelds should be set to the values from the Restart ARS
Start SPA Address and Restart ARS Length from the previous Query ARS Status output buffer. For any Start ARS
function, OSPM may optionally set the Flags Bit[0] to indicate to the platform that the ARS is a priority and may
cause delays in other processing, such as when booting. The output from a successful Start ARS function provides an
estimated time for the scrub to complete as a hint to the OSPM regarding when to issue a Query ARS Status function.
As indicated in the Query ARS Capabilities function output, a platform may issue the asynchronous event notiﬁcation
0x81 (Unconsumed Uncorrectable Memory Error Detected Notiﬁcation) when new uncorrectable errors are detected.
Upon receiving the notiﬁcation, the OSPM may decide to issue a Start ARS with Flags Bit [1] set to prepare for
the retrieval of existing records and issue the Query ARS Status function to retrieve the records. The OSPM can
pass the entire range of persistent memory as ‘ARS Start SPA Address’ and ‘ARS Length’ for Start ARS , even if the
persistent memory range is not contiguous. Alternatively, the OSPM may decide to ignore event notiﬁcation 0x81. If
the memory range is accessed before OSPM can process the ARS data, default platform error handing sequences, such
as Machine Check, may occur.
Platforms may support the ability for OSPM to clear an error previously reported from an ARS. OSPM should only
issue the Clear Uncorrectable Error function for a memory address range if that the address range has been retired
from further use or if valid error-free data is written to the range before those locations are read. If the Clear Uncor-
rectable Error function is not supported by the platform or if a Clear Uncorrectable Error function for an address
range fails, the OSPM should continue to prevent accesses to the address ranges.
The ARS related functions use the following convention for the Status and Extended Status ﬁelds.
9.19.7.3 Address Range Scrub (ARS) Error Injection Overview
The expected OSPM ARS Error Injection ﬂow is:
1. Inject an error with ARS Error Inject.
2. Optionally and if ARS Unconsumed Uncorrectable Memory Error Detected Notiﬁcation is supported by the
host, system ﬁrmware triggers an ACPI NVDIMM root device notiﬁcation 0x81 for the OSPM.
3. Use Start ARS with Flags Bit[1] set for OSPM acknowledgment of the notiﬁcation to system ﬁrmware and use
ARS Query Status to query ARS status.
4. Optionally, use ARS Error Inject Status Query to query the error injected ranges.
5. Use ARS Error Inject Clear to clear the ARS error injected ranges. Until the error is cleared, system ﬁrmware
will report the error in the ARS Query Status output buffer.
9.19. NVDIMM Devices 605Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.18: Status and Extended Status Field Generic Interpretations
Bytes Field Name Description
1-0 Status
0 - Success
1 - Function Not Supported
2 - Invalid Input Parameters
3 - Hardware Error
4 - Retry Suggested; it is up to the OSPM regarding the number of retries to
perform.
5 - Error - Unknown Reason
6 - Function-Speciﬁc Error Code
7 - FFFFh Reserved for errors
3-2 Extended Status Function Speciﬁc
Note: If Status is nonzero, the Output Buffer for all the functions in the _DSM (Device Speciﬁc Method) is limited to
only the Status and Extended Status ﬁelds.
9.19.7.4 Function Index 1 - Query ARS Capabilities
This function provides ARS capabilities for a given address range. The format of the input and output for this function
is given below.
9.19.7.4.1 Function Input
Table 9.19: Query ARS Capabilities - Input Buffer
Field Byte
ARS Start SPA Ad-
dress8 0 Starting of System Physical Address of ARS
ARS Length 8 8
9.19.7.4.2 Function Output
Table 9.20: Query ARS Capabilities - Output Buffer
Field Byte
Status 2 0 Deﬁned in Table 9.18. All other ﬁelds in this structure are Reserved
if Status is not set to 0 (Success).
9.19. NVDIMM Devices 606Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.20 – continued from previous page
Field Byte
Extended Status 2 2
Bit[0] - If set to 1, indicates scrub of V olatile Memory is supported.
V olatile memory is any region that is not marked as Persistent
Memory in UEFI or in an ACPI Address Range Type.
Bit[1] - If set to 1, indicates scrub of Persistent Memory is
supported. Persistent Memory is any region that has one of the
following memory range types:
- UEFI memory type of EﬁPersisten tMemory
- Any UEFI memory type that has the EFI_MEMORY_N V
memory attribute set
- ACPI Address Range Type of AddressRange
PersistentMemory
Bits[15:2] - Reserved
Max Query ARS
Status Output
Buffer Size4 4 In bytes. Maximum size of buffer (including the Status and Ex-
tended Status ﬁelds) returned by the Query ARS Status function.
This can be used to calculate the maximum number of ARS Error
Records that are supported. This value shall be a constant for the

Field Byte
platform, independent of the input SPA range. As long as a valid
input SPA range is speciﬁed, the value returned for this shall always
be the same.
Clear Uncorrectable
Error Range Length
Unit Size4 8
In bytes.
- This ﬁeld describes the uncorrectable error clearing unit size.
This value shall be a power of two.
- The Clear Uncorrectable Error Range Length argument to the
Clear Uncorrectable Errors LSM function shall be an integer
multiple of this unit size.
- The Query ARS Status ARS Error Record Format “Length” ﬁeld
shall be an integer multiple of this unit size.
- The ARS Error Inject SPA Range Length argument to the ARS
Error Inject DSM function shall be an integer multiple of this unit
size.
- This value shall be a constant for the platform, independent of the
input SPA range.
Flags 2 12
Bit[0] - Unconsumed Uncorrectable Memory Error Detected
Notiﬁcation ﬂag. If set to 1, indicates platform supports the ACPI
NVDIMM Root Device Unconsumed Error Notiﬁcation (0x81) as
described in nvdimm-root-device-notiﬁcation-values. If set to 0,
the platform doesn’t support this notiﬁcation mechanism.
Bit[1] - ARS Stopped Notiﬁcation ﬂag. If set to 1, indicates the
platform supports ARS Stopped Notiﬁcation (0x82) as described in
NVDIMM Root Device Notiﬁcation Values . If set to 0, the platform
does not support this notiﬁcation.
Bit[15-2] - Reserved.
9.19. NVDIMM Devices 607Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Field Byte
Reserved 2 14
Error Max Range
Length4 16
In bytes.
- Allows the platform to report max number of bytes that can be
cleared of uncorrectable errors at a time.
- This value shall be an integer multiple of the unit size, Query
ARS Capabilities Clear Uncorrectable Error Range Length Unit
Size
Reserved1 4 20
9.19.7.5 Function Index 2 - Start ARS
The Start ARS function triggers an Address Range Scrub for the given memory range. Address scrubbing can be done
for volatile memory, persistent memory, or both. For the given input ARS Start SPA and length, there may be one or
more ranges, including gaps between them for the given Type parameter.
9.19.7.5.1 Function Input
Table 9.21: Start ARS - Input Buffer
Field Byte
dress8 0 In bytes
ARS Length 8 8 In bytes
Type 2 16
Bit[0] - If set to 1, Scrub V olatile Memory
Bit[1] - If set to 1, Scrub Persistent Memory
Bits[15:2] Reserved - Note: If the range provided includes both
volatile and persistent sub-ranges, only the types indicated here
will be scrubbed.
Flags 1 18
Bit[0] - If set to 1 speciﬁes that the platform may cause delays in
processing other operations while performing the ARS (e.g., for
use during system boot). If set to 0 speciﬁes that the platform shall
not cause delays in processing other operations while performing
the ARS (e.g., for use during run time).
Bit[1]: If set to 1 the ﬁrmware shall return data from a previous
scrub, if any, without starting a new scrub. If set to 0 ﬁrmware shall
start a new ARS.
Reserved 5 19
9.19. NVDIMM Devices 608Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.19.7.5.2 Function Output
Table 9.22: Start ARS - Output Buffer
Field Byte
Status 2 0 6 - ARS already in progress All other values deﬁned in Status and
Extended Status Field Generic Interpretations
Extended Status 2 2 Reserved
Estimated Time for
Scrub4 4 In seconds Estimated time to scrub the given address range.
9.19.7.6 Function Index 3 - Query ARS Status
TheQuery ARS Status command allows software to get the status of ARS.
If the platform supports ARS error injection, then it shall also include injected errors as part of its payload.
9.19.7.6.1 Function Input
None
9.19.7.6.2 Function Output
Table 9.23: Query ARS Status - Output Buffer
Field Byte
Status 2 0 Deﬁned in Status and Extended Status Field Generic Interpretations
0 - ARS complete
1 - ARS in progress. Any returned ARS data shall be all zeros.
2 - No ARS performed for current boot. Any returned ARS data
shall be all zeros.
3 - ARS Stopped Prematurely - This may occur when the
implementation reaches the maximum number of errors that can be
reported.
4 ..0xFFFF- Reserved. Any returned ARS Data shall be all zeros.
ARS Data Varies 4 SeeARS Data .
The output SPA range return indicates the scope of the ARS scrub for the speciﬁed type.
Table 9.24: ARS Data
Field Byte
Output (Size) 4 0 Size of Output Buffer in bytes, including this ﬁeld.
Start SPA 8 4 In bytes
9.19. NVDIMM Devices 609Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.24 – continued from previous page
Field Byte
Length 8 12 In bytes ARS performed range is from Start SPA to Start SPA +
Length
Restart ARS Start
SPA Address8 20 Starting SPA to restart the ARS if Status is Success and Extended
Status was reported as ARS Stopped Prematurely. The value speci-
ﬁed here is used without modiﬁcation as the ARS Start SPA Address
when calling Start ARS to continue an ARS that stopped prema-
turely before completing the requested ARS Length. Note: It is not
required to continue an ARS that has stopped prematurely.
Restart ARS Length 8 28 SPA Length to restart the ARS if Status is Success and Extended
Status was reported as ARS Stopped Prematurely. The value spec-
iﬁed here is used without modiﬁcation as the ARS Length when
calling Start ARS to continue an ARS that stopped prematurely be-
fore completing the requested ARS Length.
Type 2 36
Bit[0] - V olatile Memory range if set to 1
Bit[1] - Persistent Memory range if set to 1. If both bit[0] and
bit[1] are set, both Persistent Memory and volatile memory are in
Flags 2 38
Bit[0] - If set to 1, indicates an overﬂow condition has occurred.
This means that more errors were reported in the error log than will
ﬁt in the maximum total buffer size of Max Query ARS Status Data
Size from the Query ARS Capabilities. The returned Extended
Status should be ARS Stopped Prematurely when this bit is set to 1.
Bits[15:1] Reserved
Number of Error
Records4 40 Number of ARS Error Record structures reported
ARS Error Records Varies 44 See the next table below for the the format of the ARS error record.
Table 9.25: ARS Error Record Format
Field Byte
NFIT Handle 4 0 NFIT Handle indicates the speciﬁc NVDIMM at Start SPA of Error
Location (offset 8)
Start SPA of Error
Location8 8 Start of System Physical Address of the error.
9.19. NVDIMM Devices 610Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.25 – continued from previous page
Field Byte
Length 8 16 Length indicates the consecutive bytes from Start SPA of Error Lo-
cation that are in error. Due to interleaving, the range covered by
Start SPA of Error Location and Length may include addresses that
are present in other NVDIMMs in an interleave set. In case of over-
ﬂow, the address range indicated by Start SPA of Error Location
and Length will cover the NVDIMM interleave set that is impacted
by the error. The range covered by Start SPA of Error Location
and Length may exceed the requested scrub range due to platform
limitations.
9.19.7.7 Function Index 4 - Clear Uncorrectable Error
The Clear Uncorrectable Error Function allows system software to clear uncorrectable errors from the NVDIMM
based on System Physical Address (SPA). Uncorrectable errors reported by the Query ARS Status function can be
cleared utilizing this mechanism.
For each uncorrectable error range length covered by the speciﬁed SPA range that contains an uncorrectable error,
platform software shall clear the error and may modify the data at those addresses. For each uncorrectable error range
length covered by the speciﬁed SPA range that does not contain an uncorrectable error, platform software shall do
nothing.
The Clear Uncorrectable Error SPA Range Base shall be aligned to the Clear Uncorrectable Error Range Length Unit
Size and the Clear Uncorrectable Error Range Length must be an integer multiple of the Clear Uncorrectable Error
Range Length Unit Size. The Clear Uncorrectable Error request shall result in an Invalid Parameter error status if
these rules are not followed.
Attempting to clear an error with a range length that overruns the end of a region shall result in an Invalid Parameter
error status.
Attempting to clear an error with a range length that is greater than the range of uncorrectable errors is not considered
a failure.
Attempting to clear an error from an address that does not currently have an uncorrectable error is not considered a
failure.
Note: The data contained in the locations that are cleared with this command are indeterminate. Care must be taken

nothing.
a failure.
failure.
when using this command since once the error has been cleared, subsequent reads of those cleared locations will cause
silent data corruption if software is unaware that the original contents were lost. Software should only utilize this
command if it can guarantee that the locations have been retired from further use or will be written with valid data
before the locations are read.
OSPM may call Clear Uncorrectable Error on an ARS error range that was injected via the ARS Error Inject
function. If the platform supports this, it should ultimately treat it as if the ARS Error Inject Clear function was
called. If the platform does not support this, it should fail with an Invalid Input Parameter error.
9.19. NVDIMM Devices 611Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.19.7.7.1 Function Input
Table 9.26: Clear Uncorrectable Error - Input Buffer
Field Byte
Error SPA Range
Base8 0 In bytes Starting location from which to clear the uncorrectable er-
ror. This address should be aligned to the Clear Uncorrectable Error
Range Length Unit Size reported in the Query ARS Capabilities
function (see Function Index 1 - Query ARS Capabilities .
Error Range Length8 8 In bytes Length of the region to clear the uncorrectable error from.
This length should be an integer multiple of the Clear Uncorrectable
Error Range Length Unit Size reported in the Query ARS Capabili-
ties function (see Function Index 1 - Query ARS Capabilities ).
9.19.7.7.2 Function Output
Table 9.27: Clear Uncorrectable Error - Output Buffer
Field Byte
Status 2 0 Deﬁned in Status and Extended Status Field Generic Interpreta-
tions .
Cleared Uncor-
rectable Error
Range Length8 8 The range of errors actually cleared by the platform, starting from
the requested Clear Uncorrectable Error SPA Range Base. This
length shall be an integer multiple of the Clear Uncorrectable Er-
ror Range Length Unit Size reported in the Query ARS Capabilities
function (see Function Index 1 - Query ARS Capabilities Note: This
range length may be smaller than the length requested by the input
range length.
9.19.7.8 Function Index 5 - Translate SPA
This command instructs the platform to translate the requested System Physical Address (SPA) in to one or more
NVDIMM devices consisting of an NFIT Device Handle and Device Physical Address (DPA) on that device.
• The SPA address to translate must lie within one of the SPA ranges described in the NFIT System Physical
Address Range table.
• For non-mirrored interleave sets, the SPA address will translate to a single NVDIMM and single DPA.
• For a HW mirrored interleave set, the Flags Bit[0] - Mirrored SPA Location bit is set and all NVDIMM Devices
the SPA translates to are included in the returned NVDIMM Device List.
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9.19.7.8.1 Function Input
The following table outlines the expected input payload for this command.
Table 9.28: Translate SPA - Input Payload Format
Field Byte
SPA 8 0 System Physical Address to translate. This is a byte aligned address
and all bits are considered valid. No masking or shifting occurs.
9.19.7.8.2 Function Output
The following tables outline the expected output payload for this command.
Table 9.29: Translate SPA - Output Payload Format
Field Byte
tions . If the SPA does not lie within one of the SPA ranges described
in the NFIT System Physical Address Range table, a status of 2, In-
valid Input Parameter, is returned. All other ﬁelds in this structure
are Reserved if Status is not set to 0 (i.e., Success).
Extended Status 2 2 Extended Status Field (Vendor Deﬁned)
Flags 1 4 Bit[0] - Mirrored SPA Location - If set to 1, indicates the SPA lo-
cation maps to one or more NVDIMMs that are mirrored together
and contributing to a single SPA range. All NVDIMMs currently
contributing to the HW Mirror shall be reported and the Number
of NVDIMMs shall report all of the devices in the Mirrored SPA
range.
Reserved 3 5 Must be 0
Translated Length 8 8 The number of bytes the returned SPA translation applies to. The
SPA range deﬁned by the input SPA + output Translated Length
-1 will yield an address translation with a constant Translated
NVDIMM Device List containing a constant set of NFIT Device
Handles.
Number of
NVDIMMs4 16 The number of NVDIMM devices being returned in the list of
Translated NVDIMM Devices. This is typically 1 for a given SPA
location but for Mirrored SPA Locations, it is possible to have mul-
tiple NVDIMMs that provide the same SPA.
Translated
NVDIMM De-
vice ListVaries 20 List of one or more Translated NVDIMM Devices
9.19. NVDIMM Devices 613Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.19.7.8.3 Translated NVDIMM Device
Table 9.30: Translate SPA - Translated NVDIMM Device List Output
Payload Format
Field Byte
dle4 0 Handle to physical NVDIMM that the SPA maps to. This handle can
be utilized to retrieve other NFIT table data that further describes the
physical device.
Reserved 4 4 Returned as zero
DPA 8 8 Device Physical Address that the SPA translates to.
9.19.7.9 Function Index 7 - ARS Error Inject
ARS Error Inject allows the injection of an error for the memory range in the deﬁned input payload. Input is a package
containing a single buffer, where the buffer is formatted as shown in ARS Error Inject - Input Format .
9.19.7.9.1 Input (Arg3)
Table 9.31: ARS Error Inject - Input Format
Field Byte
ARS Error Inject
SPA Range Base8 0 Starting location from which to inject the error.
SPA Range Length8 8 In bytes Length of the region to inject the error from. If Length
makes the range cross NVDIMM SPA ranges, the system ﬁrmware
implementation may report more than one ARS error record in the
output buffer of the ARS Query Status _DSM function.
Options1 16
Bit 0: Unconsumed Uncorrectable Memory Error Detected
Notiﬁcation. Set to 1 Firmware shall notify the OSPM. Set to 0 the
notiﬁcation will not occur.
Bit 1: Force Overﬂow. Set to 1 to trigger a Query ARS Status
overﬂow condition with this range. A value of 0 is ignored. See
Bit 2: Persistent Error. Set to 1 to persist this error across reboots.
These are uncorrectable errors injected to speciﬁed memory
locations. Set to 0 to ensure this error is cleared on reboot.
Bits 7-3: Reserved.
OSPM can trigger a Query ARS Status overﬂow condition by setting the Force Overﬂow bit (bit 1) in the ARS Error
Inject Options in the input structure.
If the Force Overﬂow bit is set to 0 then the platform may still trigger an overﬂow condition if necessary (e.g. the
number of error records to return from Query ARS Status exceeds Query ARS Status Data Size).
The typical sequence to force an overﬂow condition is as follows:
1. OSPM calls ARS Error Inject to inject an error for a particular range and sets the following ﬁelds in
9.19. NVDIMM Devices 614Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
the input structure:
a. ARS Error Inject Options bit 0 to 0 so that the Unconsumed Uncorrectable Memory Error
Detected notiﬁcation does not occur for this range.
b. ARS Error Inject Options bit 1 set to 1 to indicate system ﬁrmware should force an overﬂow
condition when it encounters this range.
2. OSPM injects a second error with ARS Error inject, setting ARS Error Inject Options bit 0 to 1 and
clearing bit 1 to 0.
3. System ﬁrmware notiﬁes the OSPM of the new errors with the Unconsumed Uncorrectable Memory
Error Detected notiﬁcation.
4. OSPM calls Query ARS Status in response to the notiﬁcation.
5. When system ﬁrmware encounters the ﬁrst injected range, it sees that ARS Error Inject Options bit
1 was set and sets Flags bit 0 to 1 in the output ARS Data to indicate an overﬂow condition. System
ﬁrmware also sets the Restart ARS Start SPA Address and Restart ARS Length accordingly.
6. OSPM calls Start ARS with the following ﬁelds set in the input structure:
a. Flags bit 1 set to 1 to indicate it does not want to initiate a new scrub.
b. ARS Start SPA Address set to the Restart ARS Start SPA Address from the Query ARS
Status output.
c. ARS Length set to the Restart ARS Length from the Query ARS Status output.
7. OSPM calls Query ARS Status.
8. System ﬁrmware returns the second injected range.
When the Persistent Error bit is set, the error range and the ARS Error Inject Options bits should persist across reboots.
9.19.7.9.2 Output
Return Value for this function is a buffer formatted as shown in the table below.
Table 9.32: ARS Error Inject - Output Format
Field Byte
Status 2 0
Bytes[1-0]
0 - Success
1 - Not Supported. The ARS Error Inject method is not supported
by the platform.

Field Byte
Status 2 0
0 - Success
2 - Invalid Input Parameters. Platform reports that the SPA range
parameters passed to the ARS Error Inject method are invalid or if
notiﬁcation is not supported.
9.19. NVDIMM Devices 615Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
9.19.7.10 Function Index 8 - ARS Error Inject Clear
ARS Error Clear allows the clearing of the injected error state in the persistent memory range in the deﬁned input
payload.
9.19.7.10.1 Input (Arg3)
Input is a package containing a single buffer, where the buffer is formatted as shown in the table below.
Table 9.33: ARS Error Inject Clear - Input Format
Field Byte
ARS Error Inject Clear SPA Range Base 8 0
ARS Error Inject Clear SPA Range Length 8 8 In bytes
9.19.7.10.2 Output
Table 9.34: ARS Error Inject Clear - Output Format
Field Byte
Status 2 0
0 - Success
1 - Not Supported. The ARS Error Inject Clear method is not
supported by the platform.
parameters passed to the ARS Error Inject method are invalid or
the speciﬁed range does not have an injected error.
9.19.7.11 Function Index 9 - ARS Error Inject Status Query
The maximum buffer size returned by the ARS Error Inject Status Query function is the same as the Max Query ARS
Status Output Buffer Size reported by the Query ARS Capabilities function.
This ARS Error Inject Status Query allows the OSPM to list the currently active injected errors in the persistent
memory ranges presented in the output buffer payload.
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9.19.7.11.1 Input (Arg3)
None.
9.19.7.11.2 Output
Return Value for this function is a buffer, formatted as shown below.
Table 9.35: ARS Error Inject Status Query - Output Format
Field Byte
Status 2 0
0 - Success.
1 - Not Supported. The ARS Error Inject Status Query method is
not supported by the platform.
Injected Error
Record Count4 4 Number of Error Records in the following array of Error Records.
If no ARS injected error, the Injected Error Count ﬁeld is 0.
Status Query Error
RecordsVaries 8 See the next table below for the format of the ARS Error Inject
Status Query Error Record.
Table 9.36: ARS Error Inject Status Query - Error Record Format
Field Byte
Record SPA Range
Base8 0 Starting SPA range of an injected error.
Length8 8 Length in bytes of the injected error starting at the SPA range.
9.19.7.12 Function Index 0xA - Query ARS Error Inject Capabilities
Query ARS Error Inject Capabilities is used by software to detect the system platforms capabilities related to injecting
ARS errors.
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9.19.7.12.1 Function Input (Arg3)
None.
9.19.7.12.2 Function Output
Table 9.37: ARS Error Inject Options Support
Field Byte
Status 2 0 Deﬁned in NVDIMM Root Device Function Index
Platform Support 4 4
Bit 0: Injected ARS Error Persistence. This bit only applies if Bit 2
of the ARS Error Inject Options Support, Persistent Error Support,
is 0. If set to 1, all injected ARS errors persist across reboots and
the OSPM must explicitly clear them. These are uncorrectable
errors injected to speciﬁed memory locations. If set to 0, all
injected ARS errors are cleared on reboot.
Bits 31-1: Reserved
Options Support1 8
Notiﬁcation Support. If set to 1, indicates system platform supports
Bit 0 in the ARS Error Inject Options ﬁeld in the ARS Error Inject
input structure.
Bit 1: Force Overﬂow Support. If set to 1, indicates system
platform supports Bit 1 in the ARS Error Inject Options ﬁeld in the
ARS Error Inject input structure.
Bit 2: Persistent Error Support. If set to 1, indicates system
platform supports Bit 2 in the ARS Error Inject Options ﬁeld in the
Bits 7-3: Reserved
9.19.8 NVDIMM Device Methods
The return status codes for NVDIMM device methods is described in the following table.
9.19. NVDIMM Devices 618Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.38: NVDIMM Device Method Return Status Code
Field Byte
Status 2 0
0 - Success
1 - Not Implemented
4 - Retry Suggested
6 - Method Speciﬁc Error Code
7 - FFFFh Reserved
Extended Status 2 2 Method Speciﬁc
9.19.8.1 _NCH (Get NVDIMM Current Health Information)
This method provides current health information of the NVDIMM device. The platform notiﬁes OSPM by NVDIMM
Device NFIT Health Event Notiﬁcation (see Table 5.196) whenever anything happens that can impact health of
NVDIMM device (see Table 9.39). When OSPM receives the notiﬁcation, it can get the current health informa-
tion by calling this method. Regardless of health notiﬁcation, OSPM can call this method at any time to get the current
health of the NVDIMM device.
During boot time, the OSPM can call this method to get the current health of NVDIMM device and take appropriate
action. During OSPM runtime, if a health problem gets corrected then also the platform shall notify OSPM by the
NVDIMM Device NFIT Health Event Notiﬁcation.
None
A buffer containing the current health information as described below
Table 9.39: NCH Return Value
Field Byte
Off-
Status 2 0 SeeNVDIMM Device Method Return Status Code
Extended
Status2 2 Reserved
Flags2 4
Bit [0] - Set to 1 to indicate that the Overall Health Status Flags ﬁeld is valid.
This bit is set to 1.
Bit [1] - Set to 1 to indicate that the Overall Health Status Attributes ﬁeld is
valid.
Bit [2-15] - Reserved
9.19. NVDIMM Devices 619Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.39 – continued from previous page
Field Byte
Off-
Overall
Health Status
Flags4 6
Multiple bits may be set as appropriate. A bit set to 0 means the respective
health problem does not exist or the bit is not applicable to the NVDIMM. If
all bits are 0, the NVDIMM is healthy.
Bit [0] - MAINTENANCE NEEDED. This bit is set to 1 to indicate that
maintenance is required - e.g. temperature alarm tripped, energy source
lifetime alarm tripped.
Bit [1] - PERFORMANCE DEGRADED. This bit is set to 1 to indicate that
performance is degraded.
Bits [2-7] - Reserved Following bits indicate situations where the OSPM
should assume write persistency loss but reads still function properly.
Bit [8] - WRITE PERSISTENCY LOSS IN EVENT OF POWER LOSS. This
bit is set to 1 to indicate that the OSPM should assume that all the writes since
last time the NVDIMM was brought online may be lost in event of power loss.
Bit [9] - WRITE PERSISTENCY LOSS IN EVENT OF OFFLINE. This bit is
set to 1 to indicate that the OSPM should assume that all the writes since last
time the NVDIMM was brought online may be lost when any subsequent
ofﬂine operation is attempted.
Bit [10] - WRITE PERSISTENCY LOSS IMMINENT. This bit is set to 1 to
indicate that the OSPM should assume that subsequent writes may not persist.
Bit [11-15] - Reserved The gollowing bits indicate situations where the OSPM
should assume all data loss.
Bit [16] - ALL DATA LOSS IN THE EVENT OF POWER LOSS. This bit is
set to 1 to indicate that the OSPM should assume that all data may be lost in
the event of power loss.
Bit [17] - ALL DATA LOSS IN THE EVENT OF OFFLINE. This bit is set to
1 to indicate that the OSPM should assume that all data may be lost when any
subsequent ofﬂine operation is attempted.
Bit [18] - ALL DATA LOSS IMMINENT. This bit is set to 1 to indicate that
the OSPM should assume that subsequent reads may fail or return invalid data
and subsequent writes may not persist.
Bit [19-31] - Reserved
Overall
Attributes4 10
Bit [0] - PERMANENT HEALTH CONDITION - This bit is set to 1 to
indicate that the health problem(s) reported in Overall Health Status Flags are
permanent. If all the bits of Overall Health Status Flags are 0’s, then
NVDIMM is healthy and this bit shall be ignored by OSPM.
Bit [1-31] - Reserved
Reserved 50 14 Reserved
Note: These ﬁelds do not track data loss during the previous shutdown or any failures during boot time. If the
condition that caused those failures still exists when _NCH method is called, then platform shall reﬂect appropriately
in the ﬁelds of this method.
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Overall
9.19.8.2 _NBS (Get NVDIMM Boot Status)
This method provides information about NVDIMM device’s status at boot time. The information provided by this
method is updated by the platform during boot and remains unchanged during runtime.
None
A buffer containing device boot status information as described below
Table 9.40: _NBS Return Value
Field Byte
Status 2 0 See Table 9.38
Validation Flags 2 4
Bit [0] - Set to 1 to indicate that Data Loss Count ﬁeld is valid.
Bit [1-15] - Reserved
Data Loss Count 4 6 A monotonically increasing counter which is incremented whenever
the NVDIMM device fails to save and/or ﬂush data to the persistent
media. This also includes any data corruption or loss which is not
signaled to the OSPM by any other architected means. This counter
is intended for the OSPM to compare against one previously saved
by the OSPM in determining the possibility of catastrophic data
loss. For example, since data loss counter is monotonically increas-
ing, OSPM can detect data loss if another OSPM was booted on the
machine between the shutdown and boot of the original OSPM.
Reserved 54 10 Reserved
9.19.8.3 _NIC (Get NVDIMM Health Error Injection Capabilities)
This method reports health error injection capabilities that are supported by the platform. The health errors mentioned
in table 9-320 are same as those mentioned in the _NCH method .
None
See Table 9.41 below.
Table 9.41: _NIC Output Buffer
Field Byte
9.19. NVDIMM Devices 621Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.41 – continued from previous page
Field Byte
Health Error Injec-
tion Capabilities4 4
A bit is set to 1 if the respective health error injection is supported,
otherwise the bit is set to 0:
Bit [0] - MAINTENANCE NEEDED
Bit [1] - PERFORMANCE DEGRADED
Bits [2-7] - Reserved
Bit [8] - WRITE PERSISTENCY LOSS IN EVENT OF POWER
LOSS
Bit [9] - WRITE PERSISTENCY LOSS IN EVENT OF OFFLINE
Bit [10] - WRITE PERSISTENCY LOSS IMMINENT
Bit [11-15] - Reserved
Bit [16] - ALL DATA LOSS IN THE EVENT OF POWER LOSS
Bit [17] - ALL DATA LOSS IN THE EVENT OF OFFLINE
Bit [18] - ALL DATA LOSS IMMINENT
Bits [19-31] - Reserved
Overall Health Sta-
tus Attributes Capa-
bilities4 8
Bit [0] - PERMANENT HEALTH CONDITION. This bit is set to
1 if permanent health errors can be injected, otherwise the bit is set
to 0.
Reserved 52 12
9.19.8.4 _NIH (NVDIMM Inject/Clear Health Errors)
This method has two modes: Inject mode and Clear mode. The OSPM should use this method for health error injection
only after verifying that the NVDIMM device has no real health errors.
In Inject mode, the OSPM can request the platform to:
• inject one or more health errors
• set one or more “Overall Health Status Attributes”
The OSPM can request either or both the items mentioned above in a single call. Unless errors are cleared, the platform
shall accumulate the injected errors and attributes through subsequent calls of this method.
If a platform can inject at least one error or set at least one attribute, then the platform shall send NVDIMM Device
Health Event Notiﬁcation if supported (see Table 5.196). The OSPM can call _NCH (see Table 9.39) and the platform
shall report the currently injected errors and attributes in the return buffer.
If a platform can inject only a subset of OSPM requested errors or set only a subset of OSPM requested attributes,
then the platform shall return an output buffer with Status set to 6 (see Table 9.38) and Extended Status set to 1 (see
Table 9.43). At that time, the OSPM can call the _NIG method (see Section 9.19.8.5) to get currently injected errors.
If the OPSM requests to inject errors which is already injected, then the platform shall return Success. If the OSPM
requests to inject an error or set an attribute which is not supported by method _NIC, then that method shall return
output buffer with Status set to 2 (see Table 9.38).
The impact of the injected errors on ﬁelds reported by the method _NCH, NVDIMM State Flags of NVDIMM Region
Mapping Structure (see Section 5.2.26.3) and on ﬁelds reported by NVDIMM device method _NBS (see Section
9.19.8.2) after a reset is implementation speciﬁc.
9.19. NVDIMM Devices 622Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
In Clear mode, the OSPM can request the platform to:
• clear one or more currently injected errors
• clear one or more “Overall Health Status Attributes” of currently injected error(s)
• The OSPM can request either or both the items mentioned above in a single call.
If platform can clear at least one error or one attribute, then it shall send NVDIMM Device Health Event Notiﬁcation
(see Table 5.196) if supported. The OSPM can call _NCH (see Table 9.39) and the platform shall report any remaining
injected errors and the attributes in the return buffer.
If a platform can clear only a subset of OSPM requested errors and attributes, then the platform shall return an output
buffer with Status set to 6 (see Table 9.38) and Extended Status set to 1 (see:numref: nih-output-buffer ). At that time,
the OSPM can call _NIG method (see Section 9.19.8.5) to get currently injected errors. If the OPSM requests to clear
error(s) which are not currently injected or requests to clear attribute(s) which are not currently set, then the platform
shall return Success. If the OSPM requests to clear an error or clear an attribute which is not supported by method
_NIC, then this method shall return output buffer with Status set to 2 (see Table 9.38).
One implementation of the health error injection is to emulate at ﬁrmware level without injecting any errors in real
hardware.
Table 9.42: _NIH Input Buffer
Field Byte
Mode 1 0
1 - Inject error(s)
2 - Clear error(s)
3 - 255 - Reserved
Reserved 3 1 Reserved
tus Errors4 4
These bits are used to inject/clear health error(s) reported by _NIC
method (see Section 9.19.8.4). If Mode is set to 1, a bit is set to 1
to inject the respective error. OSPM can set one or more error bits
to 1. If Mode is set to 2, a bit is set to 1 to clear the respective error.
OSPM can set one or more error bits to 1 (see below).
Bit [2-7] - Reserved
LOSS
9.19. NVDIMM Devices 623Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.42 – continued from previous page
Field Byte
tus Attributes4 8
Bit [0] - PERMANENT HEALTH CONDITION. If Mode is set to
1, this bit is set to 1 to inject health errors as permanent errors,
otherwise the bit is set to 0. If Mode is set to 2, this bit is set to 1 to
clear the “Permanent Health Condition” of the injected errors.
Reserved 52 12 Reserved
Table 9.43: _NIH Output Buffer
Field Byte
Status 2 0 Set :ref: nvdimm-device-method-return-status-code
1 - If Mode is 1, only a subset of requested errors is injected or
only a subset of requested attributes is set. If Mode is 2, only a
subset of requested errors is cleared or only a subset of requested
attributes is cleared.
2 - FFFFh Reserved
9.19.8.5 _NIG (Get NVDIMM Inject Health Error Status)
This method reports currently active health errors and their error attributes that are injected by NVDIMM device
method _NIH.
None
Table 9.44: _NIG Output Buffer
Field Byte
Bit [0] - Set to 1 to indicate that the Injected Overall Health Status
Flags ﬁeld is valid. This bit is set to 1.
Bit [1] - Set to 1 to indicate that the Overall Health Status
Attributes of Injected Errors ﬁeld is valid.
9.19. NVDIMM Devices 624Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 9.44 – continued from previous page
Field Byte
Injected Overall
Health Status Errors4 6
If a bit is set to 1 then the respective error is currently injected:
LOSS

None
Field Byte
Field Byte
LOSS
tus Attributes of In-
jected Errors4 10
1 to indicate that the injected error(s) are permanent health error(s),
otherwise the bit is set to 0.
9.19. NVDIMM Devices 625CHAPTER
TEN
POWER SOURCE AND POWER METER DEVICES
This section speciﬁes the battery, AC adapter, and power source device objects OSPM uses to manage power resources,
as well as the power meter device objects OSPM uses to measure power consumption.
A battery device is required to either have a Smart Battery subsystem or a Control Method Battery interface as de-
scribed in this section. OSPM is required to be able to connect and manage a battery on either of these interfaces. This
section describes these interfaces.
In the case of a compatible ACPI Smart Battery Table, the Deﬁnition Block needs to include a Bus/Device package
for the SMB-HC. This will install an OS-speciﬁc driver for the SMBus, which in turn will locate the components of
the Smart Battery subsystem. In addition to the battery or batteries, the Smart Battery subsystem includes a charger
and a manager device to handle subsystems with multiple batteries.
The Smart Battery System Manager is one implementation of a manager device that is capable of arbitrating among
the available power sources (AC power and batteries) for a system. It provides a superset of the Smart Battery Selector
functionality, such as safely responding to power events (AC versus battery power), inserting and removing batteries
and notifying the OS of all such changes. Additionally, the Smart Battery System Manager is capable of handling
conﬁgurations including simultaneous charging and discharging of multiple batteries. Unlike the Smart Battery Selec-
tor that shares responsibility for conﬁguring the battery system with OSPM, the Smart Battery System Manager alone
controls the safe conﬁguration of the battery system and simply issues status changes to OSPM when the conﬁguration
changes. Smart Battery System Manager is the recommended solution for handling multiple-battery systems.
A Power Meter device is the logical representation of a platform sensor that measures the power consumption of one
or more devices in the system. A basic platform implementation implements interfaces that query the current power
consumption and get the currently conﬁgured power consumption hardware limit, while more advance power meter
device implementations provide interfaces that support OSPM conﬁgurable power consumption trip points that trigger
SCI events, or enable conﬁguration of the underlying hardware to enforce a hard limit on the maximum amount of
power that can be consumed.
10.1 Smart Battery Subsystems
The Smart Battery subsystem is deﬁned by the:
• System Management Bus Speciﬁcation (SMBS)
• Smart Battery Data Speciﬁcation (SBDS)
• Smart Battery Charger Speciﬁcation (SBCS)
• Smart Battery System Manager Speciﬁcation (SBSM)
• Smart Battery Selector Speciﬁcation (SBSS)
An ACPI-compatible Smart Battery subsystem consists of:
• An SMB-HC (CPU to SMB-HC) interface
626Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• At least one Smart Battery
• A Smart Battery Charger
• Either a Smart Battery System Manager or a Smart Battery Selector if more than one Smart Battery is supported
In such a subsystem, a standard way of communicating with a Smart Battery and Smart Battery Charger is through the
SMBus physical protocols. The Smart Battery System Manager or Smart Battery Selector provides event notiﬁcation
(battery insertion/removal, and so on) and charger SMBus routing capability for any Smart Battery subsystem. A
typical Smart Battery subsystem is illustrated below:
Fig. 10.1: Typical Smart Battery Subsystem (SBS)
SMBus deﬁnes a ﬁxed 7-bit slave address per device. This means that all batteries in the system have the same
address (deﬁned to be 0xB). The slave addresses associated with Smart Battery subsystem components are shown in
the following table.
Table 10.1: Example SMBus Device Slave Addresses
SMBus Device Description SMBus Slave Address (A0-A6)
SMBus Host Slave Interface 0x8
Smart Battery Charger/Charger Selector or Charger System Manager 0x9
Smart Battery System Manager or Smart Battery Selector 0xA
Smart Battery 0xB
Each SMBus device has up to 256 registers that are addressed through the SMBus protocol’s Command value. SMBus
devices are addressed by providing the slave address with the desired register’s Command value. Each SMBus register
can have non-linear registers; that is, command register 1 can have a 32-byte string, while command register 2 can
have a byte, and command register 3 can have a word.
The SMBus host slave interface provides a standard mechanism for the host CPU to generate SMBus protocol com-
mands that are required to communicate with SMBus devices (in other words, the Smart Battery components). ACPI
deﬁnes such an SMB-HC that resides in embedded controller address space; however, an OS can support any SMB-HC
that has a native SMB-HC device driver.
• Event notiﬁcation for battery insertion and removal
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• Event notiﬁcation for AC power connected or disconnected
• Status of which Smart Battery is communicating with the SMB-HC
• Status of which Smart Battery(s) are powering the system
• Status of which Smart Battery(s) are connected to the charger
• Status of which Smart Batteries are present in the system
• Event notiﬁcation when the Smart Battery System Manager switches from one power source to another
• Hardware-switching to an alternate Smart Battery when the Smart Battery supplying power runs low
• Hardware switching between battery-powered and AC-powered powered operation
The Smart Battery System Manager function can reside in a standalone SMBus slave device (Smart Battery System
Manager that responds to the 0xA slave address), may be present within a smart charger device (Smart Battery Charger
that responds to the 0x9 slave address), or may be combined within the embedded controller (that responds to the 0xA
slave address). If both a Smart Battery Charger and a standalone Smart Battery System Manager are present in the
same Smart Battery subsystem, then the driver assumes that the standalone Smart Battery System Manager is wired to
the batteries.
The Smart Battery charger is an SMBus device that provides a standard programming model to control the charging
of Smart Batteries present in a Smart Battery subsystem. For single battery systems, the Smart Battery Charger is also
responsible for notifying the system of the battery and AC status.
The Smart Battery provides intelligent chemistry-independent power to the system. The Smart Battery is capable
of informing the Smart Battery charger of its charging requirements (which provides chemistry independence) and
providing battery status and alarm features needed for platform battery management.
10.1.1 ACPI Smart Battery Status Change Notiﬁcation Requirements
The Smart Battery System Manager, the Smart Battery Selector, and the Smart Battery Charger each have an optional
mechanism for notifying the system that the battery conﬁguration or AC status has changed. ACPI requires that this
interrupt mechanism be through the SMBus Alarm Notify mechanism.
For systems using an embedded controller as the SMBus host, a battery system device issues a status change notiﬁ-
cation by either mastering the SMBus to send the notiﬁcation directly to the SMBus host, or by emulating it in the
embedded controller. In either case, the process is the same. After the notiﬁcation is received or emulated, the em-
bedded controller asserts an SCI. The source of the SCI is identiﬁed by a GPE that indicates the SCI was caused by
the embedded controller. The embedded controller’s status register alarm bit is set, indicating that the SMBus host
received an alarm message. The Alarm Address Register contains the address of the SMBus device that originated the
alarm and the Alarm Data Registers contain the contents of that device’s status register.
10.1.1.1 Smart Battery Charger
This requires a Smart Battery Charger, on a battery or AC status change, to generate an SMBus Alarm Notify. The con-
tents of the Smart Battery Charger’s ChargerStatus() command register (0x13) is placed in the embedded controller’s
Alarm Data Registers, the Smart Battery Charger’s slave address ( See Note Below ) (0x09) is placed in the embedded
controller’s Alarm Address Register and the EC’s Status Register’s Alarm bit is set. The embedded controller then
asserts an SCI.
Note: The 1.0 SMBus protocol speciﬁcation is ambiguous about the deﬁnition of the “slave address” written into

the command ﬁeld of the host controller. In this case, the slave address is actually the combination of the 7-bit slave
address and the Write protocol bit. Therefore, bit 0 of the initiating device’s slave address is aligned to bit 1 of the
10.1. Smart Battery Subsystems 628Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
host controller’s slave command register, bit 1 of the slave address is aligned to bit 2 of the controller’s slave command
register, and so on.
10.1.1.2 Smart Battery Charger with optional System Manager or Selector
A Smart Battery Charger that contains the optional System Manager or Selector function (as indicated by the Charg-
erSpecInfo() command register, 0x11, bit 4) is required to generate an SMBus Alarm Notify on a battery or AC status
change. The content of the Smart Battery Charger with an optional System Manager, the BatterySystemState() com-
mand register (0x21) (or in the case of an optional Selector, the SelectorState() (0x01) ), is placed in the EC’s Alarm
Data Registers, the Smart Battery Charger’s slave address (0x09) is placed in the embedded controller’s Alarm Ad-
dress Register, and the embedded controller’s Status Register’s Alarm bit is set. The embedded controller then asserts
an SCI.
10.1.1.3 Smart Battery System Manager
The Smart Battery System Manager is required to generate an SMBus Alarm Notify on a battery or AC status change.
The content of the Smart Battery System Manager’s BatterySystemState() command register (0x01) is placed in the
EC’s Alarm Data Registers, the Smart Battery System Manager’s slave address (0x0A) is placed in the EC’s Alarm
Address Register, and the embedded controller’s Status Register’s Alarm bit is set. The embedded controller then
10.1.1.4 Smart Battery Selector
The requirements for the Smart Battery Selector are the same as the requirements for the Smart Battery System
Manager, with the exception that the contents of the SelectorState() command register (0x01) are used instead of
BatterySystemState(). The Smart Battery Selector is a subset of the Smart Battery System Manager and does not
have the added support for simultaneous charge/discharge of multiple batteries. The System Manager is the preferred
10.1.2 Smart Battery Objects
The Smart Battery subsystem requires a number of objects to deﬁne its interface. These are summarized below:
Table 10.2: Smart Battery Objects
_HID This is the hardware ID named object that contains a string. For Smart Battery subsystems, this
object returns the value of “ACPI0002.” This identiﬁes the Smart Battery subsystem to the Smart
Battery driver.
_SBS This is the Smart Battery named object that contains a DWORD. This named object returns the
conﬁguration of the Smart Battery.
10.1. Smart Battery Subsystems 629Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
10.1.3 _SBS (Smart Battery Subsystem)
The _SBS control method returns the conﬁguration of the Smart Battery subsystem. This named object returns a
DWORD value with a number from 0 to 4. If the number of batteries is greater than 0, then the Smart Battery driver
assumes that a Smart Battery System Manager or Smart Battery Selector is present. If 0, then the Smart Battery driver
assumes a single Smart Battery and neither a Smart Battery System Manager nor Smart Battery Selector is present.
None
The DWORD returned by _SBS is an Integer containing the Smart Battery subsystem conﬁguration:
• 0 - Maximum of one Smart Battery and no Smart Battery System Manager or Smart Battery Selector.
• 1 - Maximum of one Smart Battery and a Smart Battery System Manager or Smart Battery Selector.
• 2 - Maximum of two Smart Batteries and a Smart Battery System Manager or Smart Battery Selector.
• 3 - Maximum of three Smart Batteries and a Smart Battery System Manager or Smart Battery Selector.
• 4 - Maximum of four Smart Batteries and a Smart Battery System Manager or Smart Battery Selector.
The maximum number of batteries is for the entire system. Therefore, if the platform is capable of supporting four
batteries, but only two are normally present in the system, then this ﬁeld should return 4. Notice that a value of 0
indicates a maximum support of one battery and there is no Smart Battery System Manager or Smart Battery Selector
present in the system
As the SMBus is not an enumerable bus, all devices on the bus must be declared in the ACPI name-space. As the
Smart Battery driver understands Smart Battery, Smart Battery Charger, and Smart Battery System Manager or Smart
Battery Selector; only a single device needs to be declared per Smart Battery subsystem. The driver gets information
about the subsystem through the hardware ID (which deﬁnes a Smart Battery subsystem) and the number of Smart
Batteries supported on this subsystem (_SBS named object). The ACPI Smart Battery table indicates the energy levels
of the platform at which the system should warn the user and then enter a sleeping state. The Smart Battery driver then
reﬂects these as threshold alarms for the Smart Batteries.
A Smart Battery device declaration in the ACPI namespace requires the _GLK object if potentially contentious ac-
cesses to device resources are performed by non-OS code. See _GLK (Global Lock) for details about the _GLK
object.
10.1.3.1 Example: Single Smart Battery Subsystem
This section illustrates how to deﬁne a Smart Battery subsystem containing a single Smart Battery and charger. The
platform implementation is illustrated below:
In this example, the platform is using an SMB-HC that resides within the embedded controller and meets the ACPI
standard for an embedded controller interface and SMB-HC interface. The embedded controller interface sits at system
I/O port addresses 0x62 and 0x66. The SMB-HC is at base address 0x80 within embedded controller address space
(as deﬁned by the ACPI embedded controller speciﬁcation) and responds to events on query value 0x30.
In this example the Smart Battery subsystem only supports a single Smart Battery. The ASL code for describing this
interface is shown below:
Device (EC0) {
Name (_HID, EISAID("PNP0C09"))
Name (_CRS,
ResourceTemplate () { // port 0x62 and 0x66
IO (Decode16, 0x62, 0x62, 0, 1),
10.1. Smart Battery Subsystems 630Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 10.2: Single Smart Battery Subsystem
IO (Decode16, 0x66, 0x66, 0, 1)
}
)
Name (_GPE, 0)
Device (SMB0) {
Name (_HID, "ACPI0001") // Smart Battery Host Controller
Name (_EC, 0x8030) // EC offset (0x80), Query (0x30)
Device (SBS0){ // Smart Battery Subsystem
Name (_HID, "ACPI0002") // Smart Battery Subsystem ID
Name(_SBS, 0x1) // Indicates support for one battery
} // end of SBS0
} // end of SMB0
} // end of EC
10.1.3.2 Multiple Smart Battery Subsystem: Example
This section illustrates how to deﬁne a Smart Battery subsystem that contains three Smart Batteries, a Smart Battery
System Manager, and a Smart Battery Charger. The platform implementation is illustrated below:
I/O port addresses 0x100 and 0x101. The SMB-HC resides at base address 0x90 within embedded controller address
space (as deﬁned by the ACPI embedded controller speciﬁcation) and responds to events on query value 0x31.
In this example the Smart Battery subsystem supports three Smart Batteries. The Smart Battery Charger and Smart
Battery System Manager reside within the embedded controller, meet the Smart Battery System Manager and Smart
Battery Charger interface speciﬁcation, and respond to their 7-bit addresses (0xA and 0x9 respectively). The ASL
code for describing this interface is shown below:
10.1. Smart Battery Subsystems 631Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 10.3: Smart Battery Subsystem
Device (EC1) {
ResourceTemplate () { // port 0x100 and 0x101
IO(Decode16, 0x100, 0x100, 0, 2)
}
)
Name (_GPE, 1)
Device (SMB1) {
Name (_EC, 0x9031) // EC offset (0x90), Query (0x31)
Device (SBS1){ // Smart Battery Subsystem
Name (_SBS, 0x3) // Indicates support for three batteries
} // end of SBS1
} // end of SMB1
10.1. Smart Battery Subsystems 632Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
10.2 Control Method Batteries
The following section illustrates the operation and deﬁnition of the Control Method Battery.
The Hardware ID for a Control Method Battery is PNP0C0A .
10.2.1 Battery Events
The AML code handling an SCI for a battery event notiﬁes the system of which battery’s status may have changed.

}
)
The OS uses the _BST control method to determine the current status of the batteries and what action, if any, should
be taken (for more information about the _BST control method, see Battery Control Methods ). The typical action is
to notify applications monitoring the battery status to provide the user with an up-to-date display of the system battery
state. But in some cases, the action may involve generating an alert or even forcing a system into a sleeping state. In
any case, any changes in battery status should generate an SCI in a timely manner to keep the system power state UI
consistent with the actual state of the system battery (or batteries).
Unlike most other devices, when a battery is inserted or removed from the system, the device itself (the battery bay) is
still considered to be present in the system. For most systems, the _STA for this device will always return a value with
bits 0-3 set and will toggle bit 4 to indicate the actual presence of a battery (see Section 7.2.4 ). When this insertion or
removal occurs, the AML code handler for this event should issue a Notify(battery_device, 0x81) to indicate that the
static battery information has changed. For systems that have battery slots in a docking station or batteries that cannot
be surprise-removed, it may be beneﬁcial or necessary to indicate that the entire device has been removed. In this case,
the standard methods and notiﬁcations described in Device Insertion, Removal, and Status Objects should be used.
When the present state of the battery has changed or when the trip point set by the _BTP control method is reached
or crossed, the hardware will assert a general purpose event. The AML code handler for this event issues a No-
tify(battery_device, 0x80) on the battery device. This notiﬁcation is also sent when the Status Flags returned from
_BMD change.
In the case where the remaining battery capacity becomes critically low, the AML code handler issues a No-
tify(battery_device, 0x80) and reports the battery critical ﬂag in the _BST object. The OS performs an emergency
10.2. Control Method Batteries 633Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
shutdown. For a full description of the critical battery state, see Low Battery Levels .
Sometimes the value to be returned from _BST or _BIF will be temporarily unknown. In this case, the method may
return the value 0xFFFFFFFF as a placeholder. When the value becomes known, the appropriate notiﬁcation (0x80
for _BST or 0x81 for BIF) should be issued, in like manner to any other change in the data returned by these methods.
This will cause OSPM to re-evaluate the method–obtaining the correct data value.
When one or more of the status ﬂags returned by the _BMD control method change, AML code issues a No-
tify(battery_device, 0x82) on the battery device unless this change occurs during a call to _BMC and the value of
the status ﬂags in _BMD match the value passed in to _BMC. If the value of the status bits cannot be set to reﬂect the
action requested by the executing _BMC, the AML code will issue this notiﬁcation. For example, calling _BMC with
bit 0 set to initiate a calibration cycle while AC power is not available will cause AML to issue a Notify(battery_device,
0x82).
A user can program peak power delivery thresholds in the _BPT control method for each battery. When a threshold is
crossed, the platform ﬁrmware such as the embedded controller will assert an SCI interrupt. The AML event handler
for this interrupt issues a Notify(<battery_device>, 0x83) on the battery device.
10.2.2 Battery Control Methods
The Control Method Battery is a battery with an AML code interface between the battery and the host PC. The battery
interface is completely accessed by AML code control methods, allowing the OEM to use any type of battery and any
kind of communication interface supported by ACPI. OSPM requires accurate battery data to perform optimal power
management policy and to provide the end user with a meaningful estimation of remaining battery life. As such,
control methods that return battery information should calculate this information rather than return hard coded data.
A Control Method Battery is described as a device object. Each device object supporting the Control Method Battery
interface contains the following additional control methods. When there are two or more batteries in the system, each
battery will have an independent device object in the namespace.
Table 10.3: Battery Control Methods
_BCT Returns battery estimated charging time.
_BIF Returns static information about a battery (in other words, model number, serial number, design
voltage, and so on).
_BIX Returns extended static information about a battery (in other words, model number, serial number,
design voltage, and so on).
_BMA Sets the averaging interval of the battery capacity measurement, in milliseconds.
_BMC Control calibration and charging.
_BMD Returns battery information related to battery recalibration and charging control.
_BMS Sets the sampling time of the battery capacity measurement, in milliseconds.
_BPC Returns static variables that are associated with system power characteristics on the battery path
and power threshold support settings.
_BPS Returns the power delivery capabilities of the battery at the present time.
_BPT Control method to set a Battery Power Threshold.
_BST Returns the current battery status (in other words, dynamic information about the battery, such
as whether the battery is currently charging or discharging, an estimate of the remaining battery
capacity, and so on).
_BTH Communicates battery thermal throttle limit set by battery thermal zone.
_BTM Returns battery estimated runtime at the present average rate of drain, or the runtime at a speciﬁed
rate.
_BTP Sets the Battery Trip point, which generates an SCI when batterycapacity reaches the speciﬁed
point.
10.2. Control Method Batteries 634Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 10.3 – continued from previous page
_OSC OSPM Capabilities conveyance for batteries.
_PCL List of pointers to the device objects representing devices powered by the battery - see Section
10.3.2
_STA Returns general status of the battery - see Section 6.3.7.
A Control Method Battery device declaration in the ACPI namespace requires the _GLK object if potentially con-
tentious accesses to device resources are performed by non-OS code. See _GLK (Global Lock) for details about the
_GLK object.
10.2.2.1 _BCT (Battery Charge Time)
When the battery is charging, this optional object returns the estimated time from present to when it is charged to a
given percentage of Last Full Charge Capacity.
Arg0 - ChargeLevel (Integer (DWORD)): The queried charge level in units of percent of Last Full Charge
Capacity. For example: 96 refers to 96% of Last Full Charge Capacity. Valid values are 1 - 100
(0x00000001 - 0x00000064).
An Integer (DWORD) containing a result code as follows:
0x00000000 - Speciﬁed targeted charging capacity is smaller than the current remaining capac-
ity or larger than 100% of Last Full Charge Capacity. 0x00000001 - 0xFFFFFFFE - Estimated
charging time in seconds 0xFFFFFFFF - Charging time is unknown
10.2.2.2 _BIF (Battery Information)
This object returns the static portion of the Control Method Battery information. This information remains constant
until the battery is changed. This object is deprecated in ACPI 4.0. The _BIX object provides expanded battery
information and includes all of the information provide by _BIF. See _BIX (Battery Information Extended) ).
None
A Package containing the battery information as described below.
_BIF returns a package in the format shown below:
Package {
Power Unit // Integer (DWORD)
Design Capacity // Integer (DWORD)
Last Full Charge Capacity // Integer (DWORD)
Battery Technology // Integer (DWORD)
Design Voltage // Integer (DWORD)
Design Capacity of Warning // Integer (DWORD)
Design Capacity of Low // Integer (DWORD)
Battery Capacity Granularity 1 // Integer (DWORD)
Battery Capacity Granularity 2 // Integer (DWORD)
10.2. Control Method Batteries 635Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Model Number // String (ASCIIZ)
Serial Number // String (ASCIIZ)
Battery Type // String (ASCIIZ)
OEM Information // String (ASCIIZ)
}
Table 10.4: BIF Return Package Values
Power Unit Integer (DWORD)
Indicates the units used by the battery to report its capacity and
charge/discharge rate information to the OS.
0x00000000 - Capacity information is reported in [mWh] and
charge/discharge rate information in [mW].
0x00000001 - Capacity information is reported in [mAh] and
charge/discharge rate information in [mA].
Design Capacity Integer (DWORD)

}
Battery’s design capacity. Design Capacity is the nominal capacity
of a new battery. The Design Capacity value is expressed as power
[mWh] or current [mAh] depending on the Power Unit value.
0x000000000 - 0x7FFFFFFF (in [mWh] or [mAh] )
0xFFFFFFFF - Unknown design capacity
Last Full Charge
CapacityInteger (DWORD)
Predicted battery capacity when fully charged. The Last Full
Charge Capacity value is expressed as power (mWh) or current
(mAh) depending on the Power Unit value.
0x000000000h - 0x7FFFFFFF (in [mWh] or [mAh] )
0xFFFFFFFF - Unknown last full charge capacity
Battery Technology Integer (DWORD)
0x00000000 - Primary (for example, non-rechargeable)
0x00000001 - Secondary (for example, rechargeable)
Design V oltage Integer (DWORD)
Nominal voltage of a new battery.
0x000000000 - 0x7FFFFFFF in [mV]
0xFFFFFFFF - Unknown design voltage
Design capacity of
WarningInteger (DWORD)
OEM-designed battery warning capacity. See Low Battery Levels
0x000000000 - 0x7FFFFFFF in [mWh] or [mAh]
Design Capacity of
LowInteger (DWORD)
OEM-designed low battery capacity. See Low Battery Levels
10.2. Control Method Batteries 636Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 10.4 – continued from previous page
Battery Capacity
Granularity 1Integer (DWORD) Battery capacity granularity between low and warning in [mAh] or
[mWh]. That is, this is the smallest increment in capacity that the
battery is capable of measuring. See note below for more details
Granularity 2Integer (DWORD) Battery capacity granularity between warning and Full in [mAh] or
battery is capable of measuring. This may be a different value than
Battery Capacity Granularity 1 to accommodate systems where the
granularity accuracy may change depending on the battery level.
See note below for more details.
Model Number String (ASCIIZ) OEM-speciﬁc Control Method Battery model number
Serial Number String (ASCIIZ) OEM-speciﬁc Control Method Battery serial number
Battery Type String (ASCIIZ) The OEM-speciﬁc Control Method Battery type
OEM Information String (ASCIIZ) OEM-speciﬁc information for the battery that the UI uses to dis-
play the OEM information about the Battery. If the OEM does not
support this information, this ﬁeld should contain a NULL string.
• A secondary-type battery should report the corresponding capacity (except for Unknown).
• On a multiple-battery system, all batteries in the system should return the same granularity.
• Operating systems prefer these control methods to report data in terms of power (watts).
• On a multiple-battery system, all batteries in the system must use the same power unit.
• The deﬁnition of battery capacity granularity has been clariﬁed. For OSPM to determine if systems support the
clariﬁed deﬁnition of battery capacity granularity, OSPM may evaluate an _OSC method at
• the battery scope to indicate support for this capability, and for the platform to indicate if it supports these
extended capabilities.
10.2.2.3 _BIX (Battery Information Extended)
The _BIX object returns the static portion of the Control Method Battery information. This information remains
constant until the battery is changed. The _BIX object returns all information available via the _BIF object plus
additional battery information. The _BIF object is deprecated in lieu of _BIX in ACPI 4.0.
None
A Package containing the battery information as described below
_BIX returns a package in the format below.
Package {
// ASCIIZ is ASCII character string terminated with a 0x00.
Revision //Integer
Power Unit //Integer (DWORD)
Design Capacity //Integer (DWORD)
Last Full Charge Capacity //Integer (DWORD)
Battery Technology //Integer (DWORD)
10.2. Control Method Batteries 637Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Design Voltage //Integer (DWORD)
Design Capacity of Warning //Integer (DWORD)
Design Capacity of Low //Integer (DWORD)
Cycle Count //Integer (DWORD)
Measurement Accuracy //Integer (DWORD)
Max Sampling Time //Integer (DWORD)
Min Sampling Time //Integer (DWORD)
Max Averaging Interval //Integer (DWORD)
Min Averaging Interval //Integer (DWORD)
Battery Capacity Granularity 1 //Integer (DWORD)
Battery Capacity Granularity 2 //Integer (DWORD)
Model Number //String (ASCIIZ)
Serial Number //String (ASCIIZ)
Battery Type //String (ASCIIZ)
OEM Information //String (ASCIIZ)
Battery Swapping Capability //Integer (DWORD)
}
Table 10.5: BIX Return Package Values
Revision Integer Current revision is: 1
0x000000000h - 0x7FFFFFFF (in [mWh] or [mAh])
10.2. Control Method Batteries 638Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 10.5 – continued from previous page
Cycle Count Integer (DWORD)
The number of cycles the battery has experienced. A cycle is
deﬁned as: An amount of discharge approximately equal to the
value of Design Capacity.
0x000000000 - 0xFFFFFFFE
0xFFFFFFFF - Unknown cycle count
Measurement Accu-
racyInteger (DWORD) The accuracy of the battery capacity measurement, in thousandth of
a percent. (0% - 100.000%) For example, The value 80000 would
mean 80% accuracy.
Max Sampling Time Integer (DWORD) The sampling time is the duration between two consecutive mea-
surements of the battery’s capacities speciﬁed in _BST, such as
present rate and remaining capacity. If the OSPM makes two
succeeding readings through _BST beyond the duration, two dif-
ferent results will be returned. The Max Sampling Time is the
maximum sampling time the battery can support, in milliseconds.
0xFFFFFFFF is returned if the information is unavailable.
Min Sampling Time Integer (DWORD) The Min Sampling Time is the minimum sampling time the battery
can support, in milliseconds. 0xFFFFFFFF is returned if the infor-
mation is unavailable.
Max Averaging In-
tervalInteger (DWORD) The Average Interval is the length of time (in milliseconds) within
which the battery averages the capacity measurements speciﬁed in
_BST, such as remaining capacity and present rate. The Sampling
time speciﬁes the frequency of measurements, and the average in-
terval speciﬁes the width of the time window of every measurement.
This ﬁeld indicates the maximum Average Interval that the battery
supports.
Min Averaging In-
tervalInteger (DWORD) This ﬁeld indicates the minimum Average Interval that the battery
supports
10.2. Control Method Batteries 639Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5

supports.
supports
Battery Swapping
CapabilityInteger (DWORD)
0x00000000 Non swappable battery (for example, sealed internal
battery not accessible to user)
0x00000001 Cold swappable battery, i.e. batteries that require
system to be shut down in order to replace the battery while on DC
power (for example, phone and laptop batteries accessible to user)
0x00000010 Hot swappable battery, i.e. batteries that do not
require the system to be shut down in order to replace/remove the
battery while on DC power (for example, accessory batteries, cd
tray batteries, external batteries, dock batteries, keyboard batteries)
Note: A secondary-type battery should report the corresponding capacity (except for Unknown).
On a multiple-battery system, all batteries in the system should return the same granularity.
Operating systems prefer these control methods to report data in terms of power (watts).
On a multiple-battery system, all batteries in the system must use the same power unit.
The deﬁnition of battery capacity granularity has been clariﬁed. For OSPM to determine if systems support the clariﬁed
deﬁnition of battery capacity granularity, OSPM may evaluate an _OSC method at the battery scope to indicate support
for this capability, and for the platform to indicate if it supports these extended capabilities.
10.2.2.4 _BMA (Battery Measurement Averaging Interval)
This object is used to set the averaging interval of the battery capacity measurement, in milliseconds. The Battery
Measurement Averaging Interval is the length of time within which the battery averages the capacity measurements
speciﬁed in _BST, such as remaining capacity and present rate.
The OSPM may read the Max Average Interval and Min Average Interval with _BIX during boot time, and set a
speciﬁc average interval within the range with _BMA.
Arg0 - AveragingInterval (Integer(DWORD)) the averaging interval of battery capacity measurement:
0x00000001 - 0xFFFFFFFF (in units of millisecond)
10.2. Control Method Batteries 640Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
0x00000000 - Success.
0x00000001 - Failure to set Battery Measurement Averaging Interval because it is out of the
battery’s measurement capability.
0x00000002 - 0xFFFFFFFF - Reserved.
10.2.2.5 _BMC (Battery Maintenance Control)
This object is used to initiate calibration cycles or to control the charger and whether or not a battery is powering the
system. This object is only present under a battery device if the _BMD Capabilities Flags ﬁeld has bit 0, 1, 2, or 5 set.
Arg0 - An Integer containing feature control ﬂags:
Bit [0] - Set to initiate an AML controlled calibration cycle. Clear to end the calibration cycle
Bit [1] - Set to disable charging. Clear to enable charging
Bit [2] - Set to allow the battery to discharge while AC power is available. Clear to prevent
discharging while AC power is available
Bit [3] – Set to request suspension of Battery Charge Limiting mode
None
SeeBattery Calibration for more information.
Evaluating this object with bit0 set will initiate an AML controlled recalibration cycle if _BMD indicates that this is
supported. The calibration cycle is controlled by the platform and will typically include disabling the AC adapter and
discharging the battery, then charging the battery. While the battery is charging, the platform runtime ﬁrmware should
set Bit [4] of the Status ﬂags returned by _BMD if it is possible to put the system into standby during calibration
to speed up charging. Evaluating this with Bit [0] equal to 0 will abort the calibration cycle if one is in process. If
the platform runtime ﬁrmware determines that the calibration cycle must be aborted (for example AC power is lost),
or the calibration completes successfully, the platform runtime ﬁrmware will end the cycle automatically, clear the
_BMD Status Flag Bit [0], and send a notify 0x82. While the calibration cycle is in process, the battery will report
data normally, so the OS must disable battery alarms.
Bit [1], Bit [2], and Bit [3] may not be used in conjunction with the AML controlled calibration cycle. Having Bit [0]
set will override Bit [1], Bit [2], and Bit [3]. Bit [1] will prevent the battery from charging even though AC power is
connected. Bit [2] will allow the system to draw its power from the battery even though AC power is available. When
the battery is no longer capable of delivering current, this setting is automatically cleared, and the system will continue
running off AC power without interruption. In addition, if AC power is lost this bit will be cleared. When AC power
comes back, the OS must set the bit again if the user wants to continue discharging. When the system clears this bit
automatically, it will result in a change in the Status Flags returned by _BMD. This will cause a notify 0x82. Bit [1] is
only cleared automatically if an AML controlled calibration cycle is initiated.
When a battery is discharging because Bit [2] is set, the _PSR method of the AC adapter device will report that AC
is ofﬂine because the system is not running off of the AC adapter. If the batteries are controlled individually (Bit [3]
of the _BMD Capabilities Flags), setting either battery to discharge will cause _PSR to report AC ofﬂine. If more
than one battery in the system has Bit [2] set to discharge the battery, it is up to the system to decide which battery to
discharge, so only on a system that discharges the batteries one at a time, a battery with Bit2 set may not be discharging
if another battery in the system is being discharged.
If Batteries are not controlled individually, calling _BMC will initiate calibration, disable charge, and/or allow dis-
charge on all batteries in the system. The state of these batteries will be reﬂected in the _BMD Status Flags for all
batteries.
10.2. Control Method Batteries 641Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Bit [3] is set to request temporary suspension of Battery Charge Limiting. This bit may not be set unless Bit [6] of the
_BMD Capabilities Flags is also set.
10.2.2.6 _BMD (Battery Maintenance Data)
This optional object returns information about the battery’s capabilities and current state in relation to battery calibra-
tion and charger control features. If the _BMC object (deﬁned below) is present under a battery device, this object
must also be present. Whenever the Status Flags value changes, AML code will issue a Notify(battery_device, 0x82).
In addition, AML will issue a Notify(battery_device, 0x82) if evaluating _BMC did not result in causing the Status
Flags to be set as indicated in that argument to _BMC. AML is not required to issue Notify(battery_device, 0x82)
if the Status Flags change while evaluating _BMC unless the change does not correspond to the argument passed to
_BMC.
None
A Package containing the battery maintenance data as described below
_BMD returns a package in the format below:
Package {
Status Flags // Integer (DWORD)
Capability Flags // Integer (DWORD)
Recalibrate Count // Integer (DWORD)
Quick Recalibrate Time // Integer (DWORD)
Slow Recalibrate Time // Integer (DWORD)
}
10.2. Control Method Batteries 642Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 10.6: BMD Return Package Values
Status Flags Integer (DWORD)
Bit values.
Bit [0] is mutually exclusive with bit [1] and bit [2]. If the charger
is being manually controlled, there cannot be an AML controlled
calibration cycle.
Bit[0] - 1 indicates the battery is running an AML controlled
calibration cycle
Bit[1] - 1 indicates that charging has been disabled.
Bit[2] - 1 indicates the battery is conﬁgured to discharge while AC
power is available.
Bit[3] - 1 indicates that the battery should be recalibrated.
Bit[4] - 1 indicates that the OS should put the system into standby
to speed charging during a calibration cycle. This is optional
(based on user preference) if “Slow Recalibrate Time” is not equal
to 0x00000000.
Bit[5] – 1 indicates that Battery Charge Limiting cannot be
suspended due to Thermal Conditions.
Bit[6] – 1 indicates that Battery Charge Limiting cannot be
suspended for Battery Protection reasons.
Bit [31:7] - reserved.
Capability Flags Integer (DWORD)
Bit values that describe the capabilities of the battery system.
These bits allows a battery system with more limited capabilities to

still be calibrated by OSPM.
Bit[0] - 1 indicates that an AML controlled calibration cycle is
Bit[1] - 1 indicates that disabling the charger is supported.
Bit[2] - 1 indicates that discharging while running on AC is
Bit[3] - 1 indicates that calling _BMC for one battery will affect
the state of all batteries in the system. This is for battery systems
that cannot control batteries individually.
Bit[4] - 1 indicates that calibration should be done by ﬁrst fully
charging the battery and then discharging it. Not setting this bit
will indicate that calibration can be done by simply discharging the
battery.
Bit[5] – 1 indicates that Battery Charge Limiting suspension is
Bits[31:6] - Reserved
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Table 10.6 – continued from previous page
Recalibrate Count Integer (DWORD)
This is used by battery systems that can’t detect when calibration is
required, but wish to recommend that the battery should be
calibrated after a certain number of cycles. Counting the number of
cycles and partial cycles is done by the OS.
0x00000000 - Only calibrate when Status Flag bit [3] is set.
0x00000000-0xFFFFFFFF - calibrate battery after detecting this
many battery cycles.
Quick Recalibrate
TimeInteger (DWORD)
Returns the estimated time it will take to calibrate the battery if the
system is put into standby whenever Status Flags bit [4] is set.
While the AML controlled calibration cycle is in progress, this
returns the remaining time in the calibration cycle.
0x000000000 - indicates that standby while calibrating the battery
is not supported. The system should remain in S0 until calibration
is completed.
0x00000001 - 0xFFFFFFFE - estimated recalibration time in
seconds.
0xFFFFFFFF - indicates that the estimated time to recalibrate the
battery is unknown.
Slow Recalibrate
Returns the estimated time it will take to calibrate the battery if
Status Flag Bit [4] is ignored. While the AML controlled
calibration cycle is in progress, this returns the remaining time in
the calibration cycle.
0x000000000 - indicates that battery calibration may not be
successful if Status Flags Bit [4] is ignored.
seconds.
SeeBattery Calibration for amore information.
TheCapability Flags and Recalibration Count are used to indicate what functions are controlled by AML and what
functions are controlled by OSPM as described in section 3.9.5, “Battery Calibration”. If the system does not imple-
ment an AML controlled calibration cycle (bit [0]), it may indicate using bit [1] and bit [2] that the OS can control
a generic calibration cycle without prompting the user to remove the power cord. Recalibration Count may be used
to indicate that the platform runtime ﬁrmware cannot determine when calibration should be preformed so bit 3 of the
Status Flags will never be set. In that case, OSPM will attempt to count the number of cycles.
Bit [3] is used by systems that do not have individual control over the batteries and can only perform calibration on all
batteries in the system at once. On such a system, if one battery requests calibration and another battery does not, the
OS may suggest that the user remove the battery that doesn’t need calibration, before initiating the calibration cycle.
When this bit is set, reading the Recalibrate Time from either battery should give the time to recalibrate all batteries
10.2. Control Method Batteries 644Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
10.2.2.7 _BMS (Battery Measurement Sampling Time)
This object is used to set the sampling time of the battery capacity measurement, in milliseconds.
The Sampling Time is the duration between two consecutive measurements of the battery’s capacities speciﬁed in
_BST, such as present rate and remaining capacity. If the OSPM makes two succeeding readings through _BST
beyond the duration, two different results will be returned.
The OSPM may read the Max Sampling Time and Min Sampling Time with _BIX during boot time, and set a speciﬁc
sampling time within the range with _BMS.
Arg0 - SamplingTime (Integer(DWORD)) the sampling time of battery capacity measurement:
• 0x00000000 - Success.
• 0x00000001 - Failure to set Battery Measurement Sampling Time because it is out of the battery’s
measurement capability.
• 0x00000002 - 0xFFFFFFFF - Reserved.
10.2.2.8 _BPC (Battery Power Characteristics)
This optional object returns static values that are used to conﬁgure power threshold support in the platform ﬁrmware.
OSPM can use the information to determine the capabilities of power delivery and threshold support for each battery
None
A Package containing the system power characteristics on the battery path and the power threshold support in the
platform ﬁrmware like the Embedded Controller.
_BPC returns a package in the format below:
Power Threshold Support, // Integer
Max Instantaneous Peak Power Threshold, // Integer
Max Sustainable Peak Power Threshold // Integer
}
Table 10.7: _BPC Return Package Values
Revision Integer Current revision is 1
Power Threshold
Support CapabilityInteger This is the power threshold support capability that must be declared
by the platform ﬁrmware to indicate what power threshold it sup-
ports. Refer to the table below for more details.
10.2. Control Method Batteries 645Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Maximum Instanta-
neous Peak Power
Threshold ValueInteger The maximum threshold for instantaneous peak output power of the
battery. This deﬁnes the maximum threshold setting for use as an
input to _BPT. The unit for this value is mW or mA, based on the
Power Unit value returned by _BIX.
Maximum Sustain-
able Peak Power
Threshold ValueInteger The maximum threshold for sustainable peak output power of the
Table 10.8: Battery Power Threshold Support Capability
Bit Interpretation
[1:0]
0 – The platform ﬁrmware does not support thresholds for the battery Peak Power.
1 – The platform ﬁrmware supports the threshold for the battery Instantaneous Peak Power.
2 – The platform ﬁrmware supports the threshold for the battery Sustainable Peak Power.
3 – The platform ﬁrmware supports the threshold for both the battery Instantaneous Peak Power
and the Sustainable Peak Power.
[31:2]
Reserved (must be 0)
10.2.2.9 _BPS (Battery Power State)
This optional object returns the power delivery capabilities of the battery at the present time. If multiple batteries are
present within the system, the sum of peak power levels from each battery can be used to determine the total available
power.
None
A Package containing the battery power delivery capabilities as described below
_BPS returns a package in the format below:
Instantaneous Peak Power Level, // Integer
Instantaneous Peak Power Period, // Integer
Sustainable Peak Power Level, // Integer
Sustainable Peak Power Period, // Integer
}
Table 10.9: _BPS Return Package Values
10.2. Control Method Batteries 646Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 10.9 – continued from previous page
Instantaneous Peak
Power LevelInteger The instantaneous peak output power of the battery in mW or mA,
based on the Power Unit value returned by _BIX. The time period is
speciﬁed in the “Instantaneous Peak Power Period” variable. This
value shall account for the battery resistances, and the minimum
system voltage. If this feature is not supported, then the platform
ﬁrmware shall report Zero for this ﬁeld.
Power PeriodInteger The time period in milliseconds that the battery can supply as spec-
iﬁed in the “Instantaneous Peak Power Level” variable. If this fea-
ture is not supported, then the platform ﬁrmware shall report Zero
for this ﬁeld.
Sustainable Peak
Power LevelInteger The sustainable peak output power of the battery in mW or mA,
based on the Power Unit value returned by _BIX. The time period
is speciﬁed by the “Sustainable Peak Power Period” variable. This

iﬁed in the “Sustainable Peak Power Level” variable. If this feature
is not supported, then the platform ﬁrmware shall report Zero for
this ﬁeld.
10.2.2.10 _BPT (Battery Power Threshold)
This optional object may be present under a battery device. OSPM must read _BPC ﬁrst to determine the power
delivery capability threshold support in the platform ﬁrmware and invoke this Method in order to program the threshold
accordingly. If the platform does not support battery peak power thresholds, this Method should not be included in the
OSPM can call this object to set a relative battery peak power capability change threshold. A notiﬁcation must be
issued when the value from the fuel gauge has changed by the amount that is greater than or equal to the last argument
passed to _BPT. For example, if the last threshold passed to _BPT is 250mW and ID is 0x1 (Instantaneous Peak
Power), the platform must generate a GPE when the battery instantaneous peak power delivery capability has changed
by 250mW or more since the threshold was last set. The AML handler for the SCI interrupt should issue a Notify
(<battery_device>, 0x83). This will cause the OSPM to re-evaluate _BPS to obtain the current battery power delivery
capability, and may call _BPT to set a new threshold value or re-arm the threshold crossing event for the same relative
threshold value.
OSPM determines an appropriate threshold value for the battery device based on the power delivery capability from
the battery and the requirements of the power control algorithm. The upper bound of instantaneous peak power or
sustainable peak power can be queried through _BPS when the battery state of charge is 100%. If the battery power
delivery capability is used to adjust the peak system performance, then a low threshold will be desired. If it is used for
fail-safe protection, then a high threshold value can be used.
OSPM checks the power threshold support capability of the ﬁrmware through _BPC before it programs the power
threshold through _BPT. The power threshold ID selected must be supported by the platform ﬁrmware. If the platform
ﬁrmware does not support the power threshold for the Instantaneous Peak Power of the battery, setting a threshold
for the Instantaneous Peak Power through _BPT will be ignored by the platform ﬁrmware. The ﬁrmware should set
the return value 0x00000004 to indicate that the threshold request is not supported. If the threshold ID matches and
the ﬁrmware is able to process the request, the return value should be 0x00000000. Otherwise, a proper return value
should be set.
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Arg0 – Revision, Integer. For this version of the speciﬁcation, this version is 1.
Arg1 – Threshold ID, Integer:
• 0: Clear all threshold trip points
• 1: Set Instantaneous Peak Power Threshold
• 2: Set Sustainable Peak Power Threshold
Arg2 – Threshold value, integer. This is the value in mW or mA, based on the Power Unit ﬁeld returned by _BIX,
used to set a threshold. A value of 0 disables the selected threshold. The value for either threshold must not be greater
than the maximum values reported by _BPC.
An Integer containing the status of the operation:
• 0x00000000 – Success
• 0x00000001 – Failure, invalid threshold value
• 0x00000002 – Failure, hardware timeout
• 0x00000003 – Failure, unknown hardware error
• 0x00000004 – Failure, unsupported threshold type
• 0x00000005 – Failure, unsupported revision
• 0x00000006 and above - Reserved
10.2.2.11 _BST (Battery Status)
This object returns the present battery status. Whenever the Battery State value changes, the system will generate an
SCI to notify the OS.
None
A Package containing the battery status as described below
_BST returns a package in the format below
Package {
Battery State // Integer (DWORD)
Battery Present Rate // Integer (DWORD)
Battery Remaining Capacity // Integer (DWORD)
Battery Present Voltage // Integer (DWORD)
}
10.2. Control Method Batteries 648Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 10.10: BST Return Package Values
Element Format Description
Battery State Integer (DWORD)
Bit values. Notice that the Charging bit and the Discharging bit are
mutually exclusive and must not both be set at the same time. Even
in critical state, hardware should report the corresponding
charging/discharging state.
Bit [0] - 1 indicates the battery is discharging.
Bit [1] - 1 indicates the battery is charging.
Bit [2] - 1 indicates the battery is in the critical energy state (see
Low Battery Levels ). This does not mean battery failure.
Bit [3] – 1 indicates the battery is in the Battery Charge Limiting
state (see Section 3.9.6).
Battery Present Rate Integer (DWORD)
Returns the power or current being supplied or accepted through
the battery’s terminals (direction depends on the Battery State
value). The Battery Present Rate value is expressed as power
Batteries that are rechargeable and are in the discharging state are
required to return a valid Battery Present Rate value.
0x00000000 - 0x7FFFFFFF in [mW] or [mA] 0xFFFFFFFF -
Unknown rate
Battery Remaining
Returns the estimated remaining battery capacity. The Battery
Remaining Capacity value is expressed as power [mWh] or current
[mAh] depending on the Power Unit value. Batteries that are
rechargeable are required to return a valid Battery Remaining
Capacity value.
0x00000000 - 0x7FFFFFFF in [mWh] or [mAh]
0xFFFFFFFF - Unknown capacity
Battery Present
V oltageInteger (DWORD)
Returns the voltage across the battery’s terminals. Batteries that are
rechargeable must report Battery Present V oltage.
0xFFFFFFFF - Unknown voltage Note: Only a primary battery can
report unknown voltage.
Note that when the battery is a primary battery (a non-rechargeable battery such as an Alkaline-Manganese battery)
and cannot provide accurate information about the battery to use in the calculation of the remaining battery life,
the Control Method Battery can report the percentage directly to OS. It does so by reporting the Last Full Charged
Capacity =100 and BatteryPresentRate=0xFFFFFFFF. This means that Battery Remaining Capacity directly reports
the battery’s remaining capacity [%] as a value in the range 0 through 100 as follows:
10.2. Control Method Batteries 649Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 10.4: Remaining Battery Percent Formula
Fig. 10.5: Remaining Battery Life Formula
10.2.2.12 _BTH (Battery Throttle Limit)
This method will communicate to the platform ﬁrmware the thermal throttle limit set by on the battery.
Arg0 - An integer from 0 to 100 containing the battery thermal throttle limit in percentage. At 100%, the
battery can be charged at maximum current.
None.
Note:: Firmware is responsible for taking the current thermal throttle limit into account when engaging charging
Example:
Scope(\_SB.PCI0.ISA0) {
Name(_HID, EISAID("PNP0C09")) // ID for this EC
// current resource description for this EC
IO(Decode16,0x62,0x62,0,1)
IO(Decode16,0x66,0x66,0,1)
})
Name(_GPE, 0) // GPE index for this EC
// create EC's region and field for thermal support
OperationRegion(EC0, EmbeddedControl, 0, 0xFF)
Field(EC0, ByteAcc, Lock, Preserve) {
TMP, 16, // current temp
PSV, 16, // passive cooling temp
BTH 16, // battery charge rate limit
}
// following is a method that OSPM will schedule after
// it receives an SCI and queries the EC to receive value 7
Method(_Q07) {
Notify (\_SB.PCI0.ISA0.EC0.TZ0, 0x80) } // end of Notify method
// create a thermal zone
ThermalZone (TZ0) {
Method(_TMP) { Return (\_SB.PCI0.ISA0.EC0.TMP )} // get current temp
Method(_PSV) { Return (\_SB.PCI0.ISA0.EC0.PSV) } // passive cooling temp
Name(_TZD, Package (){\_SB.PCI0.ISA0.EC0.BAT0}) // passive cooling devices
Name(_TC1, 4) // bogus example constant
Name(_TC2, 3) // bogus example constant
Name(_TSP, 150) // passive sampling = 15 sec
10.2. Control Method Batteries 650Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
} // end of TZ0
Device (BAT0) {
Name(_HID, "PNP0C0A")
Name(_UID, One)
Method (_BTH, 0x1, NotSerialized) {
Store(Arg0, \_SB.PCI0.ISA0.EC0.BTH)
}
// additional battery objects
}
} // end of ECO
} // end of \\_SB.PCI0.ISA0
˓→scope
10.2.2.13 _BTM (Battery Time)
This optional object returns the estimated runtime of the battery while it is discharging.

}
}
˓→scope
Arg0 - An Integer containing the rate at which the battery is expected to discharge
0 - Indicates that the battery will continue discharging at the current rate. The rate should be
based on the average rate of drain, not the current rate of drain.
1 - 0x7FFFFFFF The discharge rate (in mA or mW)
An Integer containing the estimated remaining runtime:
0 - The input discharge rate (Arg0) is too large for the battery or batteries to supply. If the input
argument was 0, this value indicates that the battery is critical. 1 - 0xFFFFFFFE - Estimated
runtime in seconds 0xFFFFFFFF - Runtime is unknown
10.2.2.14 _BTP (Battery Trip Point)
This object is used to set a trip point to generate an SCI whenever the Battery Remaining Capacity reaches or crosses
the value speciﬁed in the _BTP object. Speciﬁcally, if Battery Remaining Capacity is less than the last argument
passed to _BTP, a notiﬁcation must be issued when the value of Battery Remaining Capacity rises to be greater than
or equal to this trip-point value. Similarly, if Battery Remaining Capacity is greater than the last argument passed to
_BTP, a notiﬁcation must be issued when the value of Battery Remaining Capacity falls to be less than or equal to this
trip-point value. The last argument passed to _BTP will be kept by the system.
If the battery does not support this function, the _BTP control method is not located in the namespace. In this case,
the OS must poll the Battery Remaining Capacity value.
Arg0 - An Integer containing the new battery trip point 0 - Clear the trip point 1 - 0x7FFFFFFF -
New trip point, in units of mWh or mAh depending on the Power Units value
None
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10.2.2.15 _OSC Deﬁnition for Control Method Battery
_OSC for a control method battery is uniquely identiﬁed by the following UUID:
F18FC78B-0F15-4978-B793-53F833A1D35B
The Revision 1 capabilities described under this _OSC are deﬁned in the table below.
Table 10.11: Control Method Battery _OSC Capabilities DWORD2
Bit Deﬁnitions
Capabilities DWORD2 bits Interpretation
0
0 - OS does not support revised battery granularity deﬁnition.
1 - OS supports revised battery granularity deﬁnition.
1
0 - OS does not support specifying wake on low battery user preference.
1 - OS supports specifying wake on low battery user preference, See _BLT
(Battery Level Threshold) for more information.
2
0 - OS does not support battery power delivery capability threshold
notiﬁcations.
1 - OS supports battery power delivery capability threshold notiﬁcations.
3-31 Reserved
Bits deﬁned in Capabilities DWORD2 provide information regarding OS supported features. Contents in DWORD2
are passed one-way; the OS will disregard the corresponding bits of DWORD2 in the Return Code.
10.3 AC Adapters and Power Source Objects
The Power Source objects describe the system’s power source. These objects may be deﬁned under a Power Source
device which is declared using a hardware identiﬁer (_HID) of “ACPI0003”. Typically there will be a power source
device for each physical power supply contained within the system. However, in cases where the power supply is
shared, as in a blade server conﬁguration, this may not be possible. Instead the ﬁrmware can choose to expose a virtual
power supply that represents one or more of the physical power supplies.
Table 10.12: Power Source Objects
_PSR Returns whether this power source device is currently online.
_PCL List of pointers to devices this power source is powering.
_PIF Returns static information about a power source.
_PRL List of pointers to all the other power source devices that belong in the same redundancy group
of which the power supply device is a member.
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10.3.1 _PSR (Power Source)
Returns whether the power source device is currently in use. This can be used to determine if system is running off
this power supply or adapter. On mobile systes this will report that the system is not running on the AC adapter if any
of the batteries in the system is being forced to discharge. In systems that contains multiple power sources, this object
reports the power source’s online or ofﬂine status.
None
An Integer containing the power source status:
0 - Off-line (not on AC power) 1 - On-line
10.3.2 _PCL (Power Consumer List)
This object evaluates to a list of pointers, each pointing to a device or a bus powered by the power source device.
Pointing to a bus indicates that all devices under the bus are powered by the power source device.
None
A variable-length Package containing a list of References to devices or buses
10.3.3 _PIF (Power Source Information)
This object returns information about the Power Source, which remains constant until the Power Source is changed.
When the power source changes, the platform issues a Notify(0x0) (Bus Check) to the Power Source device to indicate
that OSPM must re-evaluate the _PIF object.
None
A Package with the following format:
Package {
Power Source State // Integer (DWORD)
Maximum Output Power // Integer (DWORD)
Maximum Input Power // Integer (DWORD)
}
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Table 10.13: PIF Method Result Codes
Power Source State Integer (DWORD)
Bit values that describe the type of this Power Source. These bits
are especially useful in server scenarios.
Bit [0] - indicates the power source is a redundant one. If this bit is
set, this Power Source device should have a _PRL object.
Bit [1] - indicates the power source is being shared across multiple
machines.
Bit [31:2] - Reserved.
Maximum Output
PowerInteger (DWORD) The maximum rated output wattage of the power source device.
[mW] 0xFFFFFFFF is returned if the information is unavailable.
Maximum Input
PowerInteger (DWORD) The maximum rated input wattage of the power source device.
Model Number String (ASCIIZ) OEM-speciﬁc Power Source model number. This element is op-
tional and an empty string (a null character) should be used if this is
Serial Number String (ASCIIZ) OEM-speciﬁc Power Source serial number. This element is optional
and an empty string (a null character) should be used if this is not
OEM Information String (ASCIIZ) OEM-speciﬁc information that the UI uses to display about the
Power Source device. This element is optional and a NULL string
should be used if this is not supported.
10.3.4 _PRL (Power Source Redundancy List)
This optional object evaluates to a list of Power Source devices that are in the same redundancy grouping as Power
Source device under which this object is deﬁned. A redundancy grouping is a group of power supplies that together
provide redundancy. For example, on a system that contains two power supplies that each could independently power
the system, both power supplies would be part of the same redundancy group. This is used in conjunction with the
Power Source State values speciﬁed by the _PIF object.
The entries should be in the format of a fully qualiﬁed ACPI namespace path.
None
A variable-length Package containing a list of References to power source devices. It has the following
format:
Package {
Power source[0], // Reference
Power source[1], // Reference
Power source[n] // Reference
}
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10.4 Power Meters
The following section describes Power Metering objects. These objects may be deﬁned under a Power Meter device
which is declared using the ACPI000D hardware identiﬁer (_HID).
Table 10.14: Power Meter Objects
_GAI Gets the averaging interval used by the power meter.
_GHL Gets the hardware power consumption limit that is enforced by the Power Meter.
_PAI Sets the power averaging interval used by the Power Meter.
_PMC Returns Power Meter capabilities.
_PMD Returns a list of devices whose power consumption is measured by the Power Meter.
_PMM Returns the power consumption measured by the Power Meter.
_PTP Sets Power Meter device trip points.
_SHL Sets the hardware power consumption limit that is enforced by the Power Meter.
10.4.1 _PMC (Power Meter Capabilities)
This object returns the capabilities of a power meter. This information remains constant unless either the power meter’s
ﬁrmware or the BMC hardware changes, at which time the platform is required to send Notify(power_meter, 0x80)
for the OSPM to re-evaluate _PMC.
None
Package {

None
Package {
Supported Capabilities // Integer (DWORD)
Measurement Unit // Integer (DWORD)
Measurement Type // Integer (DWORD)
Measurement Accuracy // Integer (DWORD)
Measurement Sampling Time // Integer (DWORD)
Minimum Averaging Interval // Integer (DWORD)
Maximum Averaging Interval // Integer (DWORD)
Hysteresis Margin // Integer (DWORD)
Hardware Limit Is Configurable // Boolean (DWORD)
Min Configurable Hardware Limit // Integer (DWORD)
Max Configurable Hardware Limit // Integer (DWORD)
Model Number // String
Serial Number // String
OEM Information // String
}
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Table 10.15: PMC Method Result Codes
Supported Capabili-
tiesInteger (DWORD)
A bitmask that represents the capability ﬂags:
Bit [0] - indicates the power meter supports measurement.
Bit [1] - indicates the power meter supports trip points.
Bit [2] - indicates the power meter supports hardware enforced
limit.
Bit [3 ]- indicates that the power meter supports notiﬁcations when
the hardware limit is enforced.
Bit [7:4] - reserved.
Bit [8] - indicates the power meter only reports data when
discharging. This applies to power meters that are battery-type
devices.
Bit [9:31] Reserved
Measurement Unit Integer (DWORD) The units used by the power meter to report measurement and con-
ﬁgure trip points and hardware enforced limits. 0x00000000 - indi-
cates measurements are reported in [mW].
Measurement Type Integer (DWORD)
The type of measurement the power meter is measuring. A power
meter may measure either input or output power, not both.
0x00000000 - indicates the power meter is measuring input power.
0x00000001 - indicates the power meter is measuring output
power.
racyInteger (DWORD) The accuracy of the power meter device, in thousandth of a percent.
(0% - 100.000%) For example, The value 80000 would mean 80%
accuracy.
Measurement Sam-
pling TimeInteger (DWORD) The sampling time of the power meter device, in milliseconds. This
is the minimum amount of time at which the measurement value will
change. In other words, the same reading will be returned by _PMM
if OSPM makes 2 consecutive reads within a measurement sampling
time. 0xFFFFFFFF is returned if the information is unavailable.
Minimum Averag-
ing IntervalInteger (DWORD) This is the minimum length of time (in milliseconds) within which
the power meter ﬁrmware is capable of averaging the measurements
within it.
Maximum Averag-
ing IntervalInteger (DWORD) This is the maximum length of time (in milliseconds) within which
within it.
Hysteresis Margin Integer (DWORD) The margin used by the BMC for hysteresis, in the unit of [Mea-
surement Unit / Measurement Sampling Time]. This indicates the
margin built around the trip points and hardware limit notiﬁcations.
This margin prevents unnecessary notiﬁes to the OSPM when the
reading is ﬂuctuating very close to one of the trip points or the hard-
ware limit. 0xFFFFFFFF is returned if the information is unavail-
able.
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Table 10.15 – continued from previous page
Hardware Limit Is
ConﬁgurableInteger (DWORD)
This boolean value represents whether hardware enforced limit is
conﬁgurable by the OSPM:
0x00000000 (zeros) - indicates the limit is read-only.
0xFFFFFFFF (ones) - indicates the limit is writable.
Minimum Conﬁg-
urable Hardware
LimitInteger (DWORD) The minimum value that can be conﬁgured into the hardware en-
forced limit, expressed in the units as speciﬁed by Measurement
Unit.
Maximum Conﬁg-
LimitInteger (DWORD) The maximum value that can be conﬁgured into the hardware en-
Unit.
Model Number String (ASCIIZ) OEM-speciﬁc Power meter model number. This element is optional
Serial Number String (ASCIIZ) OEM-speciﬁc Power meter serial number. This element is optional
Power meter device. This element is optional and a NULL string
10.4.2 _PTP (Power Trip Points)
This object sets the upper and lower trip points for the power meter device. These 2 trip points deﬁne a hysteresis range
for which the OSPM can tolerate without re-reading the current measurement via _PMM. When the power meter draw
goes outside the range, a Notify(power_meter, 0x81) should be sent to notify the OSPM, at which time the OSPM
should re-evaluate _PMM and also set a pair of trip points around the newest reading. If the latest value measured by
the power meter is outside of the range deﬁned by the trip points by the time _PTP is called, a result code is returned.
Arg0 (Integer) : Upper Trip Point
Arg1 (Integer) : Lower Trip Point
• 0x00000001 - Failure to set trip points because latest measurement is out of range
• 0x00000002 - Failure to set trip points due to hardware timeout
• 0x00000003 - Failure to set trip points due to unknown hardware error
• 0x00000004 - 0xFFFFFFFF - Reserved
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10.4.3 _PMM (Power Meter Measurement)
This object returns the latest measurement reading from the power meter device. The value returned represents real
power (i.e. power factor is included in the value). In most cases this is a rolling average value that is computed by
the ﬁrmware over an averaging interval. On systems where this interval can be conﬁgured, the _PAI object should be
present under the power meter device (see Section 10.4.4).
Arguments
None
An Integer is returned to represent the latest measurement reading from the power meter device. This value
should be in the unit speciﬁed in the power meter capabilities (typically in milliwatts), and is required to
be the RMS value if the power meter is measuring in AC. If an error occurs while obtaining the meter
reading or if the value is not available then an Integer with all bits set is returned.
10.4.4 _PAI (Power Averaging Interval)
This object sets the averaging interval used by the power meter. The averaging interval is the total time the power meter
will take instantaneous measurement samples for, before averaging them to produce the average power measurement as
returned by _PMM. If the platform changes the averaging interval independently from OSPM, the platform must issue
a Notify(power_meter, 0x84) to indicate the change to the OSPM. Upon receiving the notiﬁcation, OSPM evaluates
the _GAI object to read the new averaging interval.
Arg0 - An Integer that represents the desired value OSPM chose to be the power averaging interval, in
milliseconds. This value needs to be within the minimum and maximum averaging interval as speciﬁed
by _PMC. Otherwise, a failure result code is returned.
• 0x00000001 - Failure to set power averaging interval because it is out of range
• 0x00000002 - Failure to set power averaging interval due to hardware timeout
• 0x00000003 - Failure to set power averaging interval due to unknown hardware error
10.4.5 _GAI (Get Averaging Interval)
This object gets the averaging interval used by the power meter. The averaging interval is the total time the power meter
None
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An Integer containing the currently conﬁgured power averaging interval,in milliseconds. If an error occurs
while obtaining the averaging interval or if the value is not available then an Integer with all bits set is
returned.
10.4.6 _SHL (Set Hardware Limit)
This object sets the hardware limit enforced by the power meter. This limit, if supported, will be enforced by the
circuitry on the platform hardware, to the best of its effort. This value is typically also conﬁgurable via other out-
of-band management mechanism. When the enforcement happens, the platform should send a Notify(power_meter,
0x83) to the OSPM.

None
returned.
Arg0 - An Integer value that represent the desired value OSPM chose as the hardware enforced limit of
this power meter, in the unit speciﬁed in _PMC. This value needs to be within the minimum and maximum
hardware limit as speciﬁed by _PMC. Otherwise, a failure result code is returned.
- 0x00000000 - Success
- 0x00000001 - Failure to set hardware limit because it is out of range
- 0x00000002 - Failure to set hardware limit due to the hardware timeout
- 0x00000003 - Failure to set hardware limit due to unknown hardware error
- 0x00000004 - 0xFFFFFFFF - Reserved
10.4.7 _GHL (Get Hardware Limit)
This object gets the hardware limit enforced by the power meter. This limit can be changed by either the OSPM or by
the platform through some out-of-band mechanism. When this value is changed, a Notify(power_meter, 0x82) should
be sent to notify the OSPM to re-read the hardware limit. If an error occurs while obtaining the hardware limit or if
the value is not available then an Integer with all bits set is returned.
None
An Integer is returned to represent the currently conﬁgured hardware enforced limit of the power meter,
in the unit speciﬁed in _PMC.
10.4.8 _PMD (Power Metered Devices)
This object evaluates to a package of device names. Each name corresponds to a device in the ACPI namespace that is
being measured by the power meter device. The measurement reported by the power meter is roughly correspondent
to the total power draw of all the devices returned.
If this control method is present, the package needs to contain at least 1 device. On a system that supports power
metering, a system power meter that measures the power draw of the entire system should always be present and have
a _PMD that contains \_SB as its sole entry.
None
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A variable-length Package consisting of references to devices being measured by the power meter:
Package {
Power Meter[0] // NamePath
Power Meter[1] // NamePath
...
Power Meter[n] // NamePath
}
10.5 Wireless Power Controllers
FCC regulations dictate reduced output power levels for wireless devices in the presence of a human body. To get
platform certiﬁcations and for regulatory compliance, wireless devices put static transmit power limit data in device
memory (either EEPROM or ﬂash) and apply it on a per band/country basis. FCC regulations allow devices to dynam-
ically reduce Effective Isotropically Radiated Power (EIRP) when in close proximity to a human body to mitigate its
adverse effects.
On current platforms, a dedicated Speciﬁc Absorption Rate (SAR) sensor for each wireless device is used for notifying
the wireless device that the system is in close proximity to a human body. This solution requires multiple SAR
sensors for systems that have multiple wireless devices, and doesn’t provide any mechanism for the wireless devices
to collaborate for better efﬁciency.
The idea is to create a well-deﬁned Wireless Power Calibration ACPI device with an ACPI event which can constitute
the basis for notifying the Operating System (OS) and all other wireless devices on a given system. Wireless Power
Calibration device event can be triggered from any proximity sensor device or by wireless device to mitigate interfer-
ence from other wireless devices as well. The OS can then map speciﬁc notiﬁcations to each wireless device to invoke
speciﬁc actions.
1. Deﬁne Plug and play ID for Wireless Power Calibration device(ACPI0014)
Wireless Power Calibration Device. This device can have a control method to sense proximity using platform
deﬁned sensor such as SAR, depth camera, touch device etc.
Device can also have control method to broadcast other wireless device notifying the user proximity change or
in band interference.
2. Deﬁne a notiﬁcation value for the device
Notifying the Wireless Power Calibration device with speciﬁc ACPI notify event id will enable wireless device
or platform drivers to notify if EIRP needs to be regulated.
Table 10.16: Wireless Power Calibration
_WPC Indicate the WPC device current operational state.[Required]
_WPP Evaluate the WPC object and return the status of last operational state.[Optional]
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10.5.1 Wireless Power Calibration Device
The following sections illustrate the operation and deﬁnition of the control method based Wireless Power Calibration
Device (WPC).
10.5.2 Wireless Power Calibration (_WPC)
The wireless power calibration can support the _WPC methods per participant device to calibrate power and notify
the participant device as the case me be. (i.e. Either direct proximity based power calibration or notiﬁcation for
interference mitigation).
The _WPC method of the WPC device functions as a notiﬁer to the participant wireless devices and indicates either
the messaging is for interference mitigation or direct power calibration.
0x00 - Direct Proximity Power Control
0x01 - Interference Mitigation Control
0x02 - Operational Band Change Control
0xFF - Reserved
10.5.3 Wireless Power Polling (_WPP)
This optional method evaluates the recommended polling frequency (in tenths of seconds) for this Wireless Power
Calibration device. A value of zero - or the absence of this object when other WPC objects are deﬁned - indicates that
the OS does not need to poll the WPC device in order to detect meaningful changes in Wireless power calibration (the
hardware is capable of generating asynchronous notiﬁcations).
Argument:
None
Return:
10.6 Wireless Power Calibration Event
To communicate the changes in wireless power transmission or interference mitigation to the OSPM. AML code should
issue a Notify (wpc_device, 0xXX) whenever a change in power calibration or interference mitigation is required to
happen. The OS receives this notiﬁcation and may call the _WPD control method to determine the notiﬁcation action
associated with it. Event generated may contain the information related to associate action that recipient devices need
to take.
WPD notiﬁcation should occur whenever a change in power transmission needed either as a result of human proximity
or interference mitigation. The granularity of the interference mitigation and power transmission can be address as per
the operational device characteristics.
The WPC notiﬁcation for interference mitigation will generate pairwise event among participant devices or multicast
is if the interference is observed in all the bands of operations involving the wireless devices.
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Table 10.17: Wireless Power Control Notiﬁcation Values
Hex Value Description
0x80 Proximity based power calibration
0x81 Interference mitigation between Wiﬁ (802.11) and Bluetooth devices
0x82-85 Reserved for Wiﬁ/BT interference mitigation for later use
0x86 Interference mitigation between Wiﬁ (802.11) and LTE/3GPP bands
0x87-90 Reserved for Wiﬁ/LTE/3GPP interference mitigation for later use
0x91 Interference mitigation between Bluetooth and LTE/3GPP devices
0x92-0x95 Reserved for Bluetooth and LTE/3GPP interference mitigation for later use
10.7 Example: Power Source and Power Meter Namespace
Figure below-shows the ACPI namespace for a computer with a power meter, AC adapter and two batteries associated
with a docking station which itself has an AC adapter.
Fig. 10.6: Power Meter and Power Source/Docking Namespace Example
10.7. Example: Power Source and Power Meter Namespace 662CHAPTER
ELEVEN
THERMAL MANAGEMENT
This chapter describes the ACPI thermal model and speciﬁes the ACPI Namespace objects OSPM uses for thermal
management of the platform.
11.1 Thermal Control
ACPI deﬁnes interfaces that allow OSPM to be proactive in its system cooling policies. With OSPM in control of the
operating environment, cooling decisions can be made based on the system’s application load, the user’s preference
towards performance or energy conservation, and thermal heuristics. Graceful shutdown of devices or the entire system
at critical heat levels becomes possible as well. The following sections describe the ACPI thermal model and the ACPI
Namespace objects available to OSPM to apply platform thermal management policy.
The ACPI thermal model is based around conceptual platform regions called thermal zones that physically contain
devices, thermal sensors, and cooling controls. Generally speaking, the entire platform is one large thermal zone, but
the platform can be partitioned into several ACPI thermal zones if necessary to enable optimal thermal management.
ACPI Thermal zones are a logical collection of interfaces to temperature sensors, trip points, thermal property infor-

mation, and thermal controls. Thermal zone interfaces apply either thermal zone wide or to speciﬁc devices, including
processors, contained within the thermal zone. ACPI deﬁnes namespace objects that provide the thermal zone-wide in-
terfaces in Section 11.4. A subset of these objects may also be deﬁned under devices. OS implementations compatible
with the ACPI 3.0 thermal model, interface with these objects but also support OS native device driver interfaces that
perform similar functions at the device level. This allows the integration of devices with embedded thermal sensors
and controls, perhaps not accessible by AML, to participate in the ACPI thermal model through their inclusion in the
ACPI thermal zone. OSPM is responsible for applying an appropriate thermal policy when a thermal zone contains
both thermal objects and native OS device driver interfaces for thermal control.
Some devices in a thermal zone may be comparatively large producers of thermal load in relation to other devices in the
thermal zone. Devices may also have varying degrees of thermal sensitivity. For example, some devices may tolerate
operation at a signiﬁcantly higher temperature than other devices. As such, the platform can provide OSPM with
information about the platform’s device topology and the resulting inﬂuence of one device’s thermal load generation
on another device. This information must be comprehended by OSPM for it to achieve optimal thermal management
through the application of cooling controls.
ACPI expects all temperatures to be represented in tenths of degrees. This resolution is deemed sufﬁcient to enable
OSPM to perform robust platform thermal management.
663Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 11.1: ACPI Thermal Zone
11.1.1 Active, Passive, and Critical Policies
There are three cooling policies that OSPM uses to control the thermal state of the hardware. The policies are active,
passive and critical.
• Active Cooling. OSPM takes a direct action such as turning on one or more fans. Applying active cooling
controls typically consume power and produce some amount of noise, but are able to cool a thermal zone
without limiting system performance. Active cooling temperature trip points declare the temperature thresholds
OSPM uses to decide when to start or stop different active cooling devices.
• Passive Cooling. OSPM reduces the power consumption of devices to reduce the temperature of a thermal zone,
such as slowing (throttling) the processor clock. Applying passive cooling controls typically produces no user-
noticeable noise. Passive cooling temperature trip points specify the temperature thresholds where OSPM will
start or stop passive cooling.
• Critical Trip Points. These are threshold temperatures at which OSPM performs an orderly, but critical, shut-
down of a device or the entire system. The _HOT object declares the critical temperature at which OSPM may
choose to transition the system into the S4 sleeping state, if supported, The _CRT object declares the critical
temperature at which OSPM must perform a critical shutdown.
When a thermal zone appears in the ACPI Namespace or when a new device becomes a member of a thermal zone,
OSPM retrieves the temperature thresholds (trip points) at which it executes a cooling policy. When OSPM receives a
temperature change notiﬁcation, it evaluates the thermal zone’s temperature interfaces to retrieve current temperature
values. OSPM compares the current temperature values against the temperature thresholds. If any temperature is
greater than or equal to a corresponding active trip point then OSPM will perform active cooling . If any temperature
is greater than or equal to a corresponding passive trip point then OSPM will perform passive cooling. If the _TMP
object returns a value greater than or equal to the value returned by the _HOT object then OSPM may choose to
transition the system into the S4 sleeping state, if supported. If the _TMP object returns a value greater than or equal
11.1. Thermal Control 664Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
to the value returned by the _CRT object then OSPM must shut the system down. Embedded Hot and Critical trip
points may also be exposed by individual devices within a thermal zone. Upon passing of these trip points, OSPM
must decide whether to shut down the device or the entire system based upon device criticality to system operation.
OSPM must also evaluate the thermal zone’s temperature interfaces when any thermal zone appears in the namespace
(for example, during system initialization) and must initiate a cooling policy as warranted independent of receipt of a
temperature change notiﬁcation. This allows OSPM to cool systems containing a thermal zone whose temperature has
already exceeded temperature thresholds at initialization time.
An optimally designed system that uses several thresholds can notify OSPM of thermal increase or decrease by raising
an event every several degrees. This enables OSPM to anticipate thermal trends and incorporate heuristics to better
manage the system’s temperature.
To implement a preference towards performance or energy conservation, OSPM can request that the platform change
the priority of active cooling (performance) versus passive cooling (energy conservation/silence) by evaluating the
_SCP (Set Cooling Policy) object for the thermal zone or a corresponding OS-speciﬁc interface to individual devices
within a thermal zone.
11.1.2 Dynamically Changing Cooling Temperature Trip Points
The platform or its devices can change the active and passive cooling temperature trip points and notify OSPM to
reevaluate the trip point interfaces to establish the new policy threshold settings. The following are the primary uses
for this type of thermal notiﬁcation:
• When OSPM changes the platform’s cooling policy from one cooling mode to another.
• When a swappable bay device is inserted or removed. A swappable bay is a slot that can accommodate several
different devices that have identical form factors, such as a CD-ROM drive, disk drive, and so on. Many mobile
PCs have this concept already in place.
• After the crossing of an active or passive trip point is signaled to implement hysteresis.
In each situation, OSPM must be notiﬁed to re-evaluate the thermal zone’s trip points via the AML code execution
of a Notify(thermal_zone, 0x81) statement or via an OS speciﬁc interface invoked by device drivers for zone devices
participating in the thermal model.
11.1.2.1 OSPM Change of Cooling Policy
When OSPM changes the platform’s cooling policy from one cooling mode to the other, the following occurs:
1. OSPM notiﬁes the platform of the new cooling mode by running the Set Cooling Policy (_SCP) control method
in all thermal zones and invoking the OS-speciﬁc Set Cooling Policy interface to all participating devices in
each thermal zone.
2. Thresholds are updated in the hardware and OSPM is notiﬁed of the change.
3. OSPM re-evaluates the active and passive cooling temperature trip points for the zone and all devices in the zone
to obtain the new temperature thresholds.
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11.1.2.2 Resetting Cooling Temperatures to Adjust to Bay Device Insertion or Removal
The platform can adjust the thermal zone temperature to accommodate the maximum operating temperature of a bay
device as necessary. For example:
1. Hardware detects that a device was inserted into or removed from the bay, updates the temperature thresholds,
and then notiﬁes OSPM of the thermal policy change and device insertion events.
2. OSPM re-enumerates the devices and re-evaluates the active and passive cooling temperature trip points.
11.1.2.3 Resetting Cooling Temperatures to Implement Hysteresis
An OEM can build hysteresis into platform thermal design by dynamically resetting cooling temperature thresholds.
1. When the temperature increases to the designated threshold, OSPM will turn on the associated active cooling
device or perform passive cooling.
2. The platform resets the threshold value to a lower temperature (to implement hysteresis) and notiﬁes OSPM of
the change. Because of this new threshold value, the fan will be turned off at a lower temperature than when it
was turned on (therefore implementing a negative hysteresis).
3. When the temperature hits the lower threshold value, OSPM will turn off the associated active cooling device or
cease passive cooling. The hardware will reset _ACx to its original value and notify OSPM that the trip points
have once again been altered.
11.1.3 Detecting Temperature Changes
The ability of the platform and its devices to asynchronously notify an ACPI-compatible OS of meaningful changes
in the thermal zone’s temperature is a highly desirable capability that relieves OSPM from implementing a poll-based
policy and generally results in a much more responsive and optimal thermal policy implementation. Each notiﬁcation

instructs OSPM to evaluate whether a trip point has been crossed and allows OSPM to anticipate temperature trends
for the thermal zone.
It is recognized that much of the hardware used to implement thermal zone functionality today is not capable of
generating ACPI-visible notiﬁcations (SCIs) or only can do so with wide granularity (for example, only when the
temperature crosses the critical threshold). In these environments, OSPM must poll the thermal zone’s temperature
periodically to implement an effective policy.
While ACPI speciﬁes a mechanism that enables OSPM to poll thermal zone temperature, platform reliance on thermal
zone polling is strongly discouraged by this speciﬁcation. OEMs should design systems that asynchronously notify
OSPM whenever a meaningful change in the zone’s temperature occurs - relieving OSPM of the overhead associ-
ated with polling. In some cases, embedded controller ﬁrmware can overcome limitations of existing thermal sensor
capabilities to provide the desired asynchronous notiﬁcation.
Notice that the _TZP (thermal zone polling) object is used to indicate whether a thermal zone must be polled by
OSPM, and if so, a recommended polling frequency. See _TZP (Thermal Zone Polling) for more information.
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11.1.3.1 Temperature Change Notiﬁcations
Thermal zone-wide temperature sensor hardware that supports asynchronous temperature change notiﬁcations does
so using an SCI. The AML code that responds to this SCI must execute a Notify(thermal_zone, 0x80) statement to
inform OSPM that a meaningful change in temperature has occurred. Alternatively, devices with embedded temper-
ature sensors may signal their associated device drivers and the drivers may use an OS-speciﬁc interface to signal
OSPM’s thermal policy driver. A device driver may also invoke a device speciﬁc control method that executes a
Notify(thermal_zone, 0x80) statement. When OSPM receives this thermal notiﬁcation, it will evaluate the thermal
zone’s temperature interfaces to evaluate the current temperature values. OSPM will then compare the values to the
corresponding cooling policy trip point values (either zone-wide or device-speciﬁc). If the temperature has crossed
over any of the policy thresholds, then OSPM will actively or passively cool (or stop cooling) the system, or shut the
system down entirely.
Both the number and granularity of thermal zone trip points are OEM-speciﬁc. However, it is important to notice
that since OSPM can use heuristic knowledge to help cool the system, the more events OSPM receives the better
understanding it will have of the system’s thermal characteristic.
Fig. 11.2: Thermal Events
For example, the simple thermal zone illustrated above includes hardware that will generate a temperature change
notiﬁcation using a 5° Celsius granularity. All thresholds (_PSV , _AC1, _AC0, and _CRT) exist within the monitored
range and fall on 5 boundaries. This granularity is appropriate for this system as it provides sufﬁcient opportunity
for OSPM to detect when a threshold is crossed as well as to understand the thermal zone’s basic characteristics
(temperature trends).
Note: The ACPI speciﬁcation deﬁnes Kelvin as the standard unit for absolute temperature values. All thermal zone
objects must report temperatures in Kelvin when reporting absolute temperature values. All ﬁgures and examples in
this section of the speciﬁcation use Celsius for reasons of clarity. ACPI allows Kelvin to be declared in precision of
1/10th of a degree (for example, 310.5).
Kelvin is expressed as follows:
𝜃/𝐾 =𝑇/(𝑑𝑒𝑔𝑟𝑒𝑒𝑠𝐶𝑒𝑙𝑠𝑖𝑢𝑠 ) + 273 .2
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11.1.3.2 Polling
Temperature sensor hardware that is incapable of generating thermal change events, or that can do so for only a few
thresholds should inform OSPM to implement a poll-based policy. OSPM does this to ensure that temperature changes
across threshold boundaries are always detectable.
Polling can be done in conjunction with hardware notiﬁcations. For example, thermal zone hardware that only supports
a single threshold might be conﬁgured to use this threshold as the critical temperature trip point. Assuming that
hardware monitors the temperature at a ﬁner granularity than OSPM would, this environment has the beneﬁt of being
more responsive when the system is overheating.
A thermal zone advertises the need to be polled by OSPM via the _TZP object. See _TZP (Thermal Zone Polling) for
11.1.4 Active Cooling
Active cooling devices typically consume power and produce some amount of noise when enabled. These devices
attempt to cool a thermal zone through the removal of heat rather than limiting the performance of a device to address
an adverse thermal condition.
The active cooling interfaces in conjunction with the active cooling lists or the active cooling relationship table (_ART)
allow the platform to use an active device that offers varying degrees of cooling capability or multiple cooling devices.
The active cooling temperature trip points designate the temperature where Active cooling is engaged or disengaged
(depending upon the direction in which the temperature is changing). For thermal zone-wide active cooling controls,
the _ALx object evaluates to a list of devices that actively cool the zone or the _ART object evaluates to describe the
entire active cooling relationship of various devices. For example:
• If a standard single-speed fan is the Active cooling device, then _AC0 evaluates to the temperature where active
cooling is engaged and the fan is listed in _AL0.
• If the zone uses two independently controlled single-speed fans to regulate the temperature, then _AC0 will
evaluate to the maximum cooling temperature using two fans, and _AC1 will evaluate to the standard cooling
temperature using one fan.
• If a zone has a single fan with a low speed and a high speed, the _AC0 will evaluate to the temperature associated
with running the fan at high-speed, and _AC1 will evaluate to the temperature associated with running the fan
at low speed. _AL0 and _AL1 will both point to different device objects associated with the same physical fan,
but control the fan at different speeds.
• If the zone uses two independently controlled multiple-speed fans to regulate the temperature, _AC0 of the target
devices evaluates to the temperature at which OSPM will engage fan devices described by the _ART object as
needed up to a maximum capability level.
For ASL coding examples that illustrate these points, see Thermal Zone Interface Requirements andThermal Zone
Examples .
11.1.5 Passive Cooling
Passive cooling controls are able to cool a thermal zone without creating noise and without consuming additional
power (actually saving power), but do so by decreasing the performance of the devices in the zone .
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11.1.5.1 Processor Clock Throttling
The processor passive cooling threshold (_PSV) in conjunction with the processor list (_PSL) allows the platform to
indicate the temperature at which a passive control, for example clock throttling, will be applied to the processor(s)
residing in a given thermal zone. Unlike other cooling policies, during passive cooling of processors OSPM may take
the initiative to actively monitor the temperature in order to cool the platform.
On an ACPI-compatible platform that properly implements CPU throttling, the temperature transitions will be similar
to the following ﬁgure, in a coolable environment, running a coolable workload:
Fig. 11.3: Temperature and CPU Performance Versus Time
The following equation should be used by OSPM to assess the optimum CPU performance change necessary to lower
the thermal zone’s temperature:
Equation #1
𝑃[%] = _𝑇𝐶1*(𝑇𝑛−𝑇𝑛−1) +_𝑇𝐶2*(𝑇𝑛−𝑇𝑡)
Where:
Tn= current temperature
Tt= target temperature (_PSV)
The two coefﬁcients _TC1 and _TC2 and the sampling period _TSP are hardware-dependent constants the OEM must
supply to OSPM (for more information, see Section 11.4). The _TSP object contains a time interval that OSPM uses
to poll the hardware to sample the temperature. Whenever the time value returned by _TSP has elapsed, OSPM will
evaluate _TMP to sample the current temperature (shown as T nin the above equation). Then OSPM will use the
11.1. Thermal Control 669Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
sampled temperature and the passive cooling temperature trip point (_PSV) (which is the target temperature T t) to
evaluate the equation for 𝑃. The granularity of 𝑃is determined by the CPU duty width of the system.
Note: Equation #1 has an implied formula.
Equation #2 :
𝑃𝑛=𝑃𝑛−1+𝐻𝑊[−?𝑃]
where:
𝑀𝑖𝑛𝑖𝑚𝑢𝑚 %<=𝑃𝑛<= 100%
For this equation, whenever Pn-1 + ?P lies outside the range Minimum0-100%, then Pn will be truncated to

where:
Minimum0-100%. Minimum% is the _MTL limit, or 0% if _MTL is not deﬁned. For hardware that cannot assume all
possible values of Pn between Minimum0 and 100%, a hardware speciﬁc mapping function HW is used.
In addition, the hardware mapping function in Equation #2 should be interpreted as follows.
For absolute temperatures:
1. If the right hand side of Equation #1 is negative, 𝐻𝑊[𝑃]is rounded to the next available higher setting of
2. If the right hand side of Equation #1 is positive, 𝐻𝑊[𝑃]is rounded to the next available lower setting of
For relative temperatures:
1. If the right hand side of Equation #1 is positive, 𝐻𝑊[𝑃]is rounded to the next available higher setting of
2. If the right hand side of Equation #1 is negative, 𝐻𝑊[𝑃]is rounded to the next available lower setting of
• The calculated Pn becomes Pn-1 during the next sampling period.
• For more information about CPU throttling, see Processor Power State C0 . A detailed explanation of this
thermal feedback equation is beyond the scope of this speciﬁcation.
11.1.6 Critical Shutdown
When the thermal zone-wide temperature sensor value reaches the threshold indicated by _CRT, OSPM must imme-
diately shut the system down. The system must disable the power either after the temperature reaches some hardware-
determined level above _CRT or after a predetermined time has passed. Before disabling power, platform designers
should incorporate some time that allows OSPM to run its critical shutdown operation. There is no requirement for
a minimum shutdown operation window that commences immediately after the temperature reaches _CRT. This is
because:
• Temperature might rise rapidly in some systems and slowly on others, depending on casing design and environ-
mental factors.
• Shutdown can take several minutes on a server and only a few seconds on a hand-held device.
Because of this indistinct discrepancy and the fact that a critical heat situation is a remarkably rare occurrence, ACPI
does not specify a target window for a safe shutdown. It is entirely up to the OEM to build in a safe buffer that it sees
ﬁt for the target platform.
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11.2 Cooling Preferences
A robust OSPM implementation provides the means for the end user to convey a preference (or a level of preference)
for either performance or energy conservation to OSPM. Allowing the end user to choose this preference is most
realizing maximum system performance. For example, if a user is taking notes on her PC in a quiet environment, such
as a library or a corporate meeting, she may want the system to emphasize passive cooling so that the system operates
quietly, even at the cost of system performance.
A user preference towards performance corresponds to the Active cooling mode while a user’s preference towards
energy conservation or quiet corresponds to the Passive cooling mode. ACPI deﬁnes an interface to convey the cooling
mode to the platform. Active cooling can be performed with minimal OSPM thermal policy intervention. For example,
the platform indicates through thermal zone parameters that crossing a thermal trip point requires a fan to be turned
on. Passive cooling requires OSPM thermal policy to manipulate device interfaces that reduce performance to reduce
Either cooling mode will be activated only when the thermal condition requires it. When the thermal zone is at
an optimal temperature level where it does not warrant any cooling, both modes result in a system operating at its
maximum potential with all fans turned off.
Thermal zones supporting the Set Cooling Policy interface allow the user to switch the system’s cooling mode empha-
sis. See _SCP (Set Cooling Policy) for more information.
Fig. 11.4: Active and Passive Threshold Values
As illustrated in Active and Passive Threshold Values , the platform must convey the value for each threshold to instruct
OSPM to initiate the cooling policies at the desired target temperatures. The platform can emphasize active or passive
cooling modes by assigning different threshold values. Generally, if _ACx is set lower than _PSV , then the system
emphasizes active cooling. Conversely, if _PSV is set lower than _ACx, then the emphasis is placed on passive cooling.
For example, a thermal zone that includes a processor and one single-speed fan may use _PSV to indicate the tempera-
ture value at which OSPM would enable passive cooling and _AC0 to indicate the temperature at which the fan would
be turned on. If the value of _PSV is less than _AC0 then the system will favor passive cooling (for example, CPU
clock throttling). On the other hand, if _AC0 is less than _PSV the system will favor active cooling (in other words,
using the fan). See the ﬁgure below for more details.
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Fig. 11.5: Cooling Preferences
The example on the left enables active cooling (for example, turn on a fan) when OSPM detects the temperature has
risen above 50°. If for some reason the fan does not reduce the system temperature, then at 75° OSPM will initiate
passive cooling (for example, CPU throttling) while still running the fan. If the temperature continues to climb, OSPM
will quickly shut the system down when the temperature reaches 90°C. The example on the right is similar but the
_AC0 and _PSV threshold values have been swapped to emphasize passive cooling.
The ACPI thermal model allows ﬂexibility in the thermal zone design. An OEM that needs a less elaborate thermal
implementation may consider using only a single threshold (for example, _CRT). Complex thermal implementations
can be modeled using multiple active cooling thresholds and devices, or through the use of additional thermal zones.
11.2.1 Evaluating Thermal Device Lists
The Notify(thermal_zone, 0x82) statement is used to inform OSPM that a change has been made to the thermal zone
device lists. This thermal event instructs OSPM to re-evaluate the _ALx, _PSL, and _TZD objects.
For example, a system that supports the dynamic insertions of processors might issue this notiﬁcation to inform OSPM
of changes to _PSL following the insertion or removal of a processor. OSPM would re-evaluate all thermal device lists
and adjust its policy accordingly.
Notice that this notiﬁcation can be used with the Notify(thermal_zone, 0x81) statement to inform OSPM to both
re-evaluate all device lists and all thresholds.
Alternatively, devices may include the _TZM (Thermal Zone Member) object their device scope to convey their
thermal zone association to OSPM. See _TZM (Thermal Zone Member) below for more information.
11.2.2 Evaluating Device Thermal Relationship Information
The Notify(thermal_zone, 0x83) statement is used to inform OSPM that a change has been made to the thermal
relationship information. This thermal event instructs OSPM to re-evaluate the _TRT and _ART objects. The thermal
inﬂuence between devices may change when active cooling moves air across device packages as compared to when
only passive cooling controls are applied. Similarly, the active cooling relationship may change as various fans are
engaged to actively cool a platform or if user preferences change.
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11.2.3 Fan Device Notiﬁcations
Notify events of type 0x80 will cause OSPM to evaluate the _FST object to evaluate the fan’s current speed.
11.3 Fan Device
ACPI 1.0 deﬁned a simple fan device that is assumed to be in operation when it is in the D0 state. Thermal zones
reference fan device(s) as being responsible primarily for cooling within that zone. Notice that multiple fan devices
can be present for any one thermal zone. They might be actual different fans, or they might be used to implement one
fan of multiple speeds (for example, by turning both “fans” on the one fan will run full speed).
ACPI 4.0 deﬁnes additional fan device interface objects enabling OSPM to perform more robust active cooling thermal
control. These objects are summarized (see Table 11.1 below). OSPM requires that all of the objects listed in the table
below be deﬁned under a fan device to enable advanced active cooling control. The absence of any of these objects
causes OSPM to perform ACPI 1.0 style simple fan control .
The Plug and Play ID of a fan device is PNP0C0B.
Table 11.1: Fan Speciﬁc Objects
_FIF Returns fan device information.
_FPS Returns a list of supported fan performance states.
_FSL Control method that sets the fan device’s speed level (performance state).
_FST Returns current status information for a fan device.

While the Fan Device and its associated objects are optional, if the Fan Device is implemented by the platform, all
objects listed in the table above are required and must be provided.
11.3.1 Fan Objects
11.3.1.1 _FIF (Fan Information)
The optional _FIF object provides OSPM with fan device capability information.
None
A Package containing the fan device parameters as described in the table below
_FIF evaluation returns a package of the following format:
FineGrainControl, // Integer Boolean
StepSize // Integer DWORD
LowSpeedNotificationSupport // Integer Boolean
}
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Table 11.2: FIF Package Details
Fine Grain
ControlInteger
(Boolean)A non zero value in this ﬁeld indicates OSPM may evaluate the fan device’s
_FSL object with a Level argument value in the range of 0-100, which repre-
sents a percentage of maximum speed. A zero value in this ﬁeld indicates that
OSPM may evaluate the fan device’s _FSL object with a Level argument value
that is a Control ﬁeld value from a package in the _FPS object’s package list
only.
Step Size Integer
(DWORD)The recommended minimum step size in percentage points to be used when
OSPM performs ﬁne-grained fan speed control. OSPM may utilize the value
of this ﬁeld if the FineGrainControl ﬁeld is non-zero the value in this ﬁeld is
between 1 and 9.
Low Speed
SupportInteger
(Boolean)A non zero value in this ﬁeld indicates that the platform will issue a Notify
(0x80) to the fan device if a low (errant) fan speed is detected.
If a fan device supports ﬁne-grained control, OSPM may evaluate a fan device’s _FSL object with any Level argument
value that is less than or equal to the Control ﬁeld value speciﬁed in the package of the _FPS object’s package list
that corresponds to the active cooling trip point that has been exceeded. This capability provides OSPM access to one
hundred fan speed settings thus enabling ﬁne-grained fan speed control. The platform uses the StepSize ﬁeld to help
OSPM optimize its fan level selection policy by ﬁne-grained fan speed control. The platform uses the StepSize ﬁeld
to help OSPM optimize its fan level selection policy by indicating recommended increments in the fan speed level
value that are appropriate for the fan when one percent increments are not optimal. In the event OSPM’s incremental
selections of Level using the StepSize ﬁeld value do not sum to 100%, OSPM may select an appropriate ending Level
increment to reach 100%. OSPM should use the same residual step value ﬁrst when reducing Level.
11.3.1.2 _FPS (Fan Performance States)
The optional _FPS object evaluates to a variable-length package containing a list of packages that describe the fan
device’s performance states. A temperature reading above an active cooling trip point deﬁned by an _ACx object in
a thermal zone or above a native active cooling trip point of a device within the thermal zone causes OSPM thermal
control to engage the appropriate corresponding fan performance state from the list of fan performance states described
by the _FPS object if the fan device is present in the corresponding _ALx device list or if an entry exists for the fan
and trip point in the active cooling relationship table (_ART).
OSPM assumes a linear relationship for the acoustic impact and power consumption values between successive entries
in the fan performance state list. Notice that the acoustic impact measurement unit (Decibels) is inherently non-linear.
As such, the platform should populate _FPS entries as necessary to enable OSPM to achieve optimal results.
None
A variable-length Package containing a Revision ID and a list of Packages that describe the fan device’s
performance states as described in the table below.
Package {
Revision, // Integer - Current revision is: 0
FanPState[0], // Package
....
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FanPState[n] // Package
}
Each FanPState sub-Package contains the elements described below:
Package () // Fan P-State
{
Control, // Integer DWORD
TripPoint, // Integer DWORD
Speed, // Integer DWORD
NoiseLevel, // Integer DWORD
Power // Integer DWORD
}
Table 11.3: FPS FanPstate Package Details
Control Integer (DWORD) Indicates the value to be used to set the fan speed to a speciﬁc level
using the _FSL object. If the fan device supports ﬁne-grained con-
trol as indicated by the _FIF object, this value is a percentage (0-
100) of maximum speed level. If the fan device does not support
ﬁne-grained control, this ﬁeld is an opaque value that OSPM must
simply use in its evaluation of the _FSL object to set the level to this
TripPoint Integer (DWORD) 0-9: The active cooling trip point number that corresponds to this
performance state. If the _ART object is deﬁned, OSPM may op-
tionally use information provided by the _ART object and _FPS
objects to select alternative fan performance states. Only one en-
try per unique trip point number is allowed in the _FPS. 0x0A-
0xFFFFFFFE: Reserved 0x0FFFFFFFF: Indicates that this perfor-
mance state does not correspond with a speciﬁc active cooling trip
point.
Speed Integer (DWORD) Indicates the speed of the fan in revolutions per minute in this per-
formance state.
NoiseLevel Integer (DWORD) This optional ﬁeld indicates the audible noise emitted by the fan
in this performance state. The value represents the noise in 10ths
of decibels. For example, if the fan emits noise at 28.3dB in this
performance state, the value of this ﬁeld would be 283. A value of
0xFFFFFFFF indicates that this ﬁeld is not populated.
Power Integer (DWORD) This optional ﬁeld indicates the power consumption (in milliwatts)
of the fan in this performance state. For example, if the fan con-
sumes .5W in this performance state, the value of this ﬁeld would
be 500. A value of 0xFFFFFFFF indicates that this ﬁeld is not pop-
ulated.
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11.3.1.3 _FSL (Fan Set Level)
The optional _FSL object is a control method that OSPM evaluates to set a fan device’s speed (performance state) to
a speciﬁc level
Arg0 - Level (Integer): conveys to the platform the fan speed level to be set.
None
Arg0: Level. If the fan supports ﬁne-grained control, Level is a percentage of maximum level (0-100) that
the platform is to engage the fan. If the fan does not support ﬁne-grained control, Level is a Control ﬁeld
value from a package in the _FPS object’s package list. A Level value of zero causes the platform to turn
off the fan.
11.3.1.4 _FST (Fan Status)
The optional _FST object provides status information for the fan device.
None
A Package containing fan device status information as described in the table below
_FST evaluation returns a package of the following format:
Speed // Integer DWORD
}
Table 11.4: FST Package Details
Control Integer (DWORD) The current control value used to operate the Fan. If the fan is not
operating Control will be zero. If the fan is operating, Control is the
Level argument passed in the evaluation of the _FSL object.
Speed Integer (DWORD) The current fan speed in revolutions per minute at which the fan is
rotating. A value of 0xFFFFFFFF indicates that the fan does not
support speed reporting.
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11.4 Thermal Objects
Objects related to thermal management are listed in the following table.
Table 11.5: Thermal Objects
_ACx Returns active cooling policy threshold values in tenths of degrees.
_ALx List of active cooling device objects.
_ART Table of values that convey the Active Cooling Relationship between devices
_CRT Returns critical trip point in tenths of degrees where OSPM must perform a critical shutdown.
_HOT Returns critical trip point in tenths of degrees where OSPM may choose to transition the system
into S4.
_MTL Returns the minimum throttle limit of a zone, when deﬁned under a thermal zone. T
_NTT Returns the temperature change threshold for devices containing native temperature sensors to
cause evaluation of the _TPT object
_PSL List of processor device objects for clock throttling.
_PSV Returns the passive cooling policy threshold value in tenths of degrees.
_RTV Conveys whether temperatures are expressed in terms of absolute or relative values.
_SCP Sets platform cooling policy (active or passive).
_STR String name for this thermal zone.
_TC1 Thermal constant for passive cooling.

into S4.
_TC2 Thermal constant for passive cooling.
_TFP Thermal fast sampling period for Passive cooling in milliseconds.
_TMP Returns the thermal zone’s current temperature in tenths of degrees.
_TPT Conveys the temperature of a devices internal temperature sensor to the platform when a temper-
ature trip point is crossed or a meaningful change in temperature occurs.
_TRT Table of values that convey the Thermal Relationship between devices
_TSN Returns a reference to the thermal sensor device used to monitor the temperature of the thermal
zone (when deﬁned under a thermal zone).
_TSP Thermal sampling period for Passive cooling in tenths of seconds.
_TST Conveys the minimum separation for a devices’ programmable temperature trip points.
_TZD List of devices whose temperature is measured by this thermal zone.
_TZM Returns the thermal zone for which a device is a member.
_TZP Thermal zone polling frequency in tenths of seconds.
With the exception of _TPT, _TST, and the _TZM objects, the objects described in the following sections may exist
under a thermal zone. Devices with embedded thermal sensors and controls may contain static cooling temperature
trip points or dynamic cooling temperature trip points that must be programmed by the device’s driver. In this case,
thermal objects deﬁned under a device serve to convey the platform speciﬁc values for these settings to the devices
driver.
11.4.1 _ACx (Active Cooling)
This optional object, if present under a thermal zone, returns the temperature trip point at which OSPM must start or
stop Active cooling, where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal
zone. If the Active cooling device has one cooling level (that is, “on”) then that cooling level must be deﬁned as _AC0.
If the cooling device has two levels of capability, such as a high fan speed and a low fan speed, then they must be
deﬁned as _AC0 and _AC1 respectively. The smaller the value of x, the greater the cooling strength _ACx represents.
In the above example, _AC0 represents the greater level of cooling (the faster fan speed) and _AC1 represents the
lesser level of cooling (the slower fan speed). For every _ACx method, there must be a matching _ALx object or a
corresponding entry in an _ART object’s active cooling relationship list.
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If this object it present under a device, the device’s driver evaluates this object to determine the device’s corresponding
active cooling temperature trip point. This value may then be used by the device’s driver to program an internal device
temperature sensor trip point. When this object is present under a device, the device must contain a native OS device
driver interface supporting a corresponding active cooling control, a matching _ALx object under the thermal zone of
which the device is a member must exist, or a corresponding entry in an _ART object’s active cooling relationship list
must.
None
An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin
The return value is an integer that represents tenths of degrees Kelvin. For example, 300.0K is represented by the
integer 3000.
11.4.2 _ALx (Active List)
This object is deﬁned under a thermal zone and evaluates to a list of Active cooling devices to be turned on when the
corresponding _ACx temperature threshold is exceeded. For example, these devices could be fans.
None
A variable-length Package containing a list of References to active cooling devices
The return value is a package consisting of references to all active cooling devices that should be engaged when the
associated active cooling threshold (_ACx) is exceeded.
When the returned package consists of references to an active cooling device that is a fan device and the fan device
implements _FPS and _FSL objects, OSPM activates the identiﬁed fan at a capability level matching the level identiﬁed
by this object. For example, if the system has a fan that implements _FPS object with 5 levels, and if _AL3 is evaluated
by the OSPM causing it to return this fan’s reference, then the fan is activated by evaluating _FSL with the value from
the Control ﬁeld of an _FPS entry whose TripPoint ﬁeld value equals 3.
If a thermal zone has the _ART object deﬁned, then it is not necessary to have any _ALx objects implemented.
Note: If a thermal zone has _ART object deﬁned as well as _ALx deﬁned, the OSPM ignores _ALx objects and uses
_ART exclusively.
11.4.3 _ART (Active Cooling Relationship Table)
The optional _ART object evaluates to a variable-length package containing a list of packages each of which describes
the active cooling relationship between a device within a thermal zone and an active cooling device. OSPM uses the
combined information about the active cooling relationships of all devices in the thermal zone to make active cooling
policy decisions.
If _ART is implemented within a thermal zone, OSPM ignores all _ALx objects as _ART conveys a mapping for each
of the _ACx trip points to active cooling devices.
The platform can dynamically change the _ART object by notifying the thermal zone object with a Notify code of
0x83, which will cause OSPM to re-evaluate both the _TRT and _ART objects. This allows the platform to change the
capability level mapping to various _ACx trip points dynamically at run time.
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None
A variable-length Package containing a Revision ID and a list of Active Relationship Packages as de-
scribed below:
Package {
ActiveRelationship[0] // Package
....
ActiveRelationship[n] // Package
}
Each ActiveRelationship sub-Package contains the elements described below:
Package {
SourceDevice, // Object Reference to a Fan Device Object
TargetDevice, // Object Reference to a Device Object
Weight, // Integer
AC0MaxLevel, // Integer
AC1MaxLevel, // Integer
AC2MaxLevel, // Integer
AC3MaxLevel, // Integer
AC4MaxLevel, // Integer
AC5MaxLevel, // Integer
AC6MaxLevel, // Integer
AC7MaxLevel, // Integer
AC8MaxLevel, // Integer
AC9MaxLevel // Integer
}
Table 11.6: Thermal Relationship Package Values 1
SourceDevice Reference (to a de-
vice)The fan device that has an impact on the cooling of the device indi-
cated by TargetDevice.
TargetDevice Reference (to a de-
vice)The device that is impacted by the fan device indicated by
SourceDevice.
Weight Integer Indicates the SourceDevice’s contribution to the platform’s Target-
Device total cooling capability when the fans of all entries in the
_ART with the same target device are engaged at their highest (max-
imum capability) performance state. This is represented as a per-
centage value (0-100).
AC0MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
OSPM may engage on the SourceDevice when a temperature ex-
ceeds the _AC0 trip point value. A value of 0xFFFFFFFF in this
ﬁeld indicates that the SourceDevice is not to be engaged for the
trip point.
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AC1MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
ceeds the _AC1 trip point value. A value of 0xFFFFFFFF in this
AC2MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
ceeds the _AC2 trip point value. A value of 0xFFFFFFFF in this
AC3MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
ceeds the _AC3 trip point value. A value of 0xFFFFFFFF in this
AC4MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
ceeds the _AC4 trip point value. A value of 0xFFFFFFFF in this
AC5MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
ceeds the _AC5 trip point value. A value of 0xFFFFFFFF in this
AC6MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that

ceeds the _AC6 trip point value. A value of 0xFFFFFFFF in this
AC7MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
ceeds the _AC7 trip point value. A value of 0xFFFFFFFF in this
AC8MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
ceeds the _AC8 trip point value. A value of 0xFFFFFFFF in this
AC9MaxLevel Integer (DWORD) Indicates the maximum fans speed level in percent (0-100) that
ceeds the _AC9 trip point value. A value of 0xFFFFFFFF in this
In the case multiple active cooling trip points have been exceeded and _ART entries indicate various maximum limits
for the same SourceDevice, OSPM may operate the SourceDevice up to the highest ACxMaxLevel value indicated for
all exceeded trip points.
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11.4.4 _CRT (Critical Temperature)
This object, when deﬁned under a thermal zone, returns the critical temperature at which OSPM must shutdown the
system. If this object it present under a device, the device’s driver evaluates this object to determine the device’s
critical cooling temperature trip point. This value may then be used by the device’s driver to program an internal
device temperature sensor trip point.
None
An Integer containing the critical temperature threshold in tenths of degrees Kelvin
The result is an integer value that represents the critical shutdown threshold in tenths of degrees. For example, 300.0K
is represented by the integer 3000.
11.4.5 _CR3 (Warm/Standby Temperature)
This object, when deﬁned under a thermal zone, returns the critical temperature at which OSPM may choose to
transition the system into a low power state with a faster exit latency than S4 sleeping state (e.g. S3, or an equivalent
low power state if the LOW_POWER_S0_IDLE_CAPABLE FADT ﬂag is set). The platform vendor should deﬁne
_CR3 to be sufﬁciently below _CRT so as to allow enough time to transition the system into this low power state.
It may be sufﬁcient to deﬁne either _CR3 or _HOT depending on the type and thermal characteristics of the speciﬁc
thermal zone under consideration. If this object it present under a device, the device’s driver evaluates this object to
determine the device’s warm/standby cooling temperature trip point. This value may then be used by the device’s
driver to program an internal device temperature sensor trip point.
None
11.4.6 _DTI (Device Temperature Indication)
This optional object may be present under a device and is evaluated by OSPM when the device’s native (driver man-
aged) temperature sensor has crossed a cooling temperature trip point or when a meaningful change in temperature (as
indicated by evaluation of the _NTT object) has occurred. OSPM evaluation of the _DTI object enables the platform
to take action as a result of these events. For example, the platform may choose to implement fan control hysteresis
based on the conveyed value or signal the revaluation of the _TDL or _PDL objects.
Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin)
None
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11.4.7 _HOT (Hot Temperature)
This optional object, when deﬁned under a thermal zone, returns the critical temperature at which OSPM may choose
to transition the system into the S4 sleeping state. The platform vendor should deﬁne _HOT to be far enough below
_CRT so as to allow OSPM enough time to transition the system into the S4 sleeping state. While dependent on
the amount of installed memory, on typical platforms OSPM implementations can transition the system into the S4
sleeping state in tens of seconds. If this object it present under a device, the device’s driver evaluates this object
to determine the device’s hot cooling temperature trip point. This value may then be used by the device’s driver to
program an internal device temperature sensor trip point.
None
The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. For example, 300.0K
11.4.8 _MTL (Minimum Throttle Limit)
This object, when deﬁned under a thermal zone, returns the minimum throttle limit of a zone. This will determine how
much a thermal zone limits the performance of its controlled devices. This value can be used by OSPM to calculate
the changes in performance limits it applies to the devices of the thermal zone.
None
An Integer value with the current minimum throttle limit, expressed as a percentage
11.4.9 _NTT (Notiﬁcation Temperature Threshold)
This optional object may be deﬁned under devices containing native temperature sensors and evaluates to the tempera-
ture change threshold for the device where the platform requires notiﬁcation of the change via evaluation of the _TPT
object.
None
An Integer containing the temperature threshold in tenths of degrees Kelvin.
The return value is an integer that represents the amount of change in device temperature that is meaningful to the
platform and for which the platform requires notiﬁcation via evaluation of the _TPT object.
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11.4.10 _PSL (Passive List)
This object is deﬁned under a thermal zone and evaluates to a list of processor objects to be used for passive cooling.
None
A variable-length Package containing a list of References to processor objects
The return value is a package consisting of references to all processor objects that will be used for passive cooling
when the zone’s passive cooling threshold (_PSV) is exceeded.
11.4.11 _PSV (Passive)
This optional object, if present under a thermal zone, evaluates to the temperature at which OSPM must activate
passive cooling policy.
None
An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin
The return value is an integer that represents tenths of degrees Kelvin. For example, 300.0 Kelvin is represented by
3000.
passive cooling temperature trip point. This value may then be used by the device’s driver to program an internal
device temperature sensor trip point. When this object is present under a device, the device must contain a native OS
device driver interface supporting a passive cooling control.
11.4.12 _RTV (Relative Temperature Values)
This optional object may be present under a device or a thermal zone and is evaluated by OSPM to determine whether
the values returned by temperature trip point and current operating temperature interfaces under the corresponding
device or thermal zone represent absolute or relative temperature values.
None
An Integer containing a relative versus absolute indicator:
0 Temperatures are absolute Other Temperatures are relative
The return value is an integer that indicates whether values returned by temperature trip point and current operating
temperature interfaces represent absolute or relative temperature values.
If the _RTV object is not present or is present and evaluates to zero then OSPM assumes that all values returned by
temperature trip point and current operating temperature interfaces under the device or thermal zone represent absolute
temperature values expressed in tenths of degrees Kelvin.
If the _RTV object is present and evaluates to a non zero value then all values returned by temperature trip point
and current operating temperature interfaces under the corresponding device or thermal zone represent temperature
values relative to a zero point that is deﬁned as the maximum value of the device’s or thermal zone’s critical cooling
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temperature trip point. In this case, temperature trip point and current operating temperature interfaces return values
in units that are tenths of degrees below the zero point.
OSPM evaluates the _RTV object before evaluating any other temperature trip point or current operating temperature
11.4.13 _SCP (Set Cooling Policy)
This optional object is a control method that OSPM invokes to set the platform’s cooling mode policy setting. The
platform may use the evaluation of _SCP to reassign _ACx and _PSV temperature trip points according to the mode
or limits conveyed by OSPM. OSPM will automatically evaluate _ACx and _PSV objects after executing _SCP. This
object may exist under a thermal zone or a device.
Arg0 - Mode An Integer containing the cooling mode policy code
Arg1 - AcousticLimit An Integer containing the acoustic limit
Arg2 - PowerLimit An Integer containing the power limit
None
Mode - 0 = Active, 1 = Passive
Acoustic Limit - Speciﬁes the maximum acceptable acoustic level that active cooling devices may generate. Values are
1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance.
Power Limit - Speciﬁes the maximum acceptable power level that active cooling devices may consume. Values are
from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool.
Example:
// Fan Control isdefined asfollows:
// Speed 1 (Fan isOff): Acoustic Limit 1, Power Limit 1, <= 64C
// Speed 2: Acoustic Limit 2, Power Limit 2, 65C - 74C
// Speed 3: Acoustic Limit 3, Power Limit 3, 75C - 84C
// Speed 4: Acoustic Limit 4, Power Limit 4, 85C - 94C
// Speed 5: Acoustic Limit 5, Power Limit 5, >= 95C
// _SCP Notifies the platform the current cooling mode.
// Arg0 = Mode
// 0 - Active cooling
// 1 - Passive cooling
// Arg1 = Acoustic Limit
// 1 = No acoustic tolerance
// ...
// 5 = maximum acoustic tolerance
// Arg2 = Power Limit
// 1 = No power may be used to cool
// ...
// 5 = maximum power may be used to cool
Method(_SCP,3,Serialized)
{
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// Store the Cooling Mode inNVS anduse asneeded in
// the rest of the ASL Code.
Store(Arg0, CTYP)
// Set PSVT to account fora Legacy OS that does not pass
//ineither the acoustic limit orPower Limit.
If(Arg0)
{
Store(60,PSVT)
}
Else
{
Store(97,PSVT)
}
If (CondRefOf (_OSI,Local0))
{
If (\_OSI ("3.0 _SCP Extensions"))
{
// Determine Power Limit.
//
// NOTE1: PSVT = Passive Cooling Trip Point stored
//inNVS inCelsius.
//
// NOTE2: 4 Active Cooling Trips Points correspond to 5
// unique Power Limit regions and5 unique acoustic limit
// regions.
//
// NOTE3: This code will define Passive cooling so that
// CPU throttling will be initiated within the Power Limit
// Region passed insuch that the next higher Power Limit
// Region will notbe reached.
Switch(Arg2)
{
Case(1) // Power Limit = 1.
{
// Stay inAcoustic Limit 1.
Store(60,PSVT) // Passive = 60C.
}
Case(2) // Power Limit = 2.
{
// Store Highest supported Acoustic Level
// at this Power Limit (1 or2).
Store(70,PSVT)
If(Lequal(Arg1,1))
{
// Stay inAcoustic Level 1.
}
}
Case(3) // Power Limit = 3.
{
// at this Power Limit (1, 2, or3).
Store(80,PSVT)
If(Lequal(Arg1,2))
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{
// Stay inAcoustic Level 1 or2.
}
{
}
}
Case(4) // Power Limit = 4.
{
// at this Power Limit (1, 2, 3, or4).
Store(90,PSVT)
If(Lequal(Arg1,3))
{
}
{
}
{
}
}
Case(5) // Power Limit = 5.
{
// at this Power Limit (1, 2, 3, 4, or5).
If(Lequal(Arg1,4))
{
}
{
}
{
}
{
}
} // Case 5
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} // Switch Arg 2
} // \_OSI - Extended \_SCP
} // CondRefOf \_OSI
} // Method \_SCP
11.4.14 _STR (String)
This optional object, when deﬁned under a thermal zone, returns a string name for this thermal zone. See below for
more details.
11.4.15 _TC1 (Thermal Constant 1)
This object evaluates to the constant _TC1 for use in the Passive cooling formula:
𝑃𝑒𝑟𝑓𝑜𝑟𝑚𝑎𝑛𝑐𝑒 [%] = _𝑇𝐶1*(𝑇𝑛−𝑇𝑛−1) +_𝑇𝐶2*(𝑇𝑛−𝑇𝑡)
None
An Integer containing Thermal Constant #1
11.4.16 _TC2 (Thermal Constant 2)
This object evaluates to the constant _TC2 for use in the Passive cooling formula:
None
An Integer containing Thermal Constant #2
11.4.17 _TFP (Thermal fast Sampling Period)
This object evaluates to a thermal sampling period (in milliseconds) used by OSPM to implement the Passive cooling
equation. This value, along with _TC1 and _TC2, will enable OSPM to provide the proper hysteresis required by the
system to accomplish an effective passive cooling policy.
None
An Integer containing the sampling period in milliseconds
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The granularity of the sampling period is 1 milliseconds. For example, if the sampling period is 30.0 seconds, then
_TFP needs to report 30,000; if the sampling period is 0.5 seconds, then it will report 500. OSPM can normalize the
sampling over a longer period if necessary.
If both _TFP and _TSP are present in a Thermal Zone, _TFP overrides _TSP. Platforms which need to support legacy
operating systems from before _TFP in ACPI 6.0, must specify a _TSP if a sampling period is required. OS support
for _TFP can be discovered via _OSC See Platform-Wide _OSC Capabilities DWORD 2 .
11.4.18 _TMP (Temperature)
This control method returns the thermal zone’s current operating temperature.
None
An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin)
The return value is the current temperature of the thermal zone in tenths of degrees Kelvin. For example, 300.0K is
represented by the integer 3000.
11.4.19 _TPT (Trip Point Temperature)
This optional object may be present under a device and is invoked by OSPM to indicate to the platform that the devices’
embedded temperature sensor has crossed a cooling temperature trip point. After invocation, OSPM immediately
evaluates the devices’ Active and Passive cooling temperature trip point values. This enables the platform to implement
hysteresis.
None
The _TPT object is deprecated in ACPI 4.0. The _DTI object should be used instead (see _DTI (Device Temperature
Indication) ).
11.4.20 _TRT (Thermal Relationship Table)
This object evaluates to a package of packages each of which describes the thermal relationship between devices within
a thermal zone. OSPM uses the combined information about the thermal relationships of all devices in the thermal
zone to make thermal policy decisions.
None
A variable-length Package containing a list of Thermal Relationship Packages as described below
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Package {
ThermalRelationship[0] // Package
....
ThermalRelationship[n] // Package
}
Each ThermalRelationship sub-Package contains the elements described below:
Package {
SourceDevice, // Object Reference to a Device Object
Influence, // Integer
SamplingPeriod, // Integer
Reserved1, // Integer
Reserved2, // Integer
Reserved3, // Integer
Reserved4 // Integer
},
Table 11.7: Thermal Relationship Package Values 2
Source Device Reference (to a de-
vice)The device that is inﬂuencing the device indicated by TargetDevice.
Target Device Reference (to a de-
vice)The device that is inﬂuenced by the device indicated by SourceDe-
vice.
Inﬂuence Integer The thermal inﬂuence of SourceDevice on TargetDevice - repre-
sented as tenths of degrees Kelvin that the device indicated by
SourceDevice raises the temperature of the device indicated by Tar-
getDevice per watt of thermal load that SourceDevice generates.

Package {
....
}
Package {
},
vice.
Sampling Period Integer The minimum period of time in tenths of seconds that OSPM should
wait after applying a passive control to the device indicated by
SourceDevice to detect its impact on the device indicated by Tar-
getDevice.
Reserved (1-4) Integer Reserved for future use.
11.4.21 _TSN (Thermal Sensor Device)
This object, when deﬁned under a thermal zone, returns a reference to the thermal sensor device used to monitor the
temperature of the thermal zone. See Native OS Device Driver Thermal Interfaces .
None
A single Reference to the namespace device object that monitors the temperature of the thermal zone.
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11.4.22 _TSP (Thermal Sampling Period)
This object evaluates to a thermal sampling period (in tenths of seconds) used by OSPM to implement the Passive
cooling equation. This value, along with _TC1 and _TC2, will enable OSPM to provide the proper hysteresis required
by the system to accomplish an effective passive cooling policy.
None
An Integer containing the sampling period in tenths of seconds
The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 seconds, then _TSP
needs to report 300; if the sampling period is 0.5 seconds, then it will report 5. OSPM can normalize the sampling
over a longer period if necessary.
operating systems from before _TFP in ACPI 6.0 must specify a _TSP if a sampling period is required. OS support
for _TFP can be discovered via _OSC (see Platform-Wide _OSC Capabilities DWORD 2 ).
11.4.23 _TST (Temperature Sensor Threshold)
This optional object may be present under a device and is evaluated by OSPM to determine the minimum separation
for a devices’ programmable temperature trip points. When a device contains multiple programmable temperature trip
points, it may not be necessary for OSPM to poll the device’s temperature after crossing a temperature trip point when
performing passive cooling control policy.
None
An Integer containing the sensor threshold (in tenths of degrees Kelvin)
To eliminate polling, the device can program intermediate trip points of interest (higher or lower than the current tem-
perature) and signal the crossing of the intermediate trip points to OSPM. The distance between the current temperature
and these intermediate trip points may be platform speciﬁc and must be set far enough away from the current temper-
ature so as to not to miss the crossing of a meaningful temperature point. The _TST object conveys the recommended
minimum separation between the current temperature and an intermediate temperature trip point to OSPM.
11.4.24 _TZD (Thermal Zone Devices)
This optional object evaluates to a package of device names. Each name corresponds to a device in the ACPI names-
pace that is associated with the thermal zone. The temperature reported by the thermal zone is roughly correspondent
to that of each of the devices.
None
A variable-length Package containing a list of References to thermal zone devices
The list of devices returned by the control method need not be a complete and absolute list of devices affected by
the thermal zone. However, the package should at least contain the devices that would uniquely identify where this
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thermal zone is located in the machine. For example, a thermal zone in a docking station should include a device in
the docking station, a thermal zone for the CD-ROM bay, should include the CD-ROM.
11.4.25 _TZM (Thermal Zone Member)
This optional object may exist under any device deﬁnition and evaluates to a reference to the thermal zone of which
the device is a member.
None
A Reference to the parent device
11.4.26 _TZP (Thermal Zone Polling)
This optional object evaluates to a recommended polling frequency (in tenths of seconds) for this thermal zone. A value
of zero indicates that OSPM does not need to poll the temperature of this thermal zone in order to detect temperature
changes (the hardware is capable of generating asynchronous notiﬁcations).
None
The return value contains the recommended polling frequency, in tenths of seconds. A value of zero indicates that
polling is not necessary.
The _TZP value is speciﬁed as tenths of seconds with a 1 second granularity. For example, a _TZP value of 300 equals
30 seconds, while a value of 3000 equals 5 minutes. This is only a recommended value, and OSPM will consider other
factors when determining the actual polling frequency to use.
chronously notify OSPM whenever a meaningful change in the zone’s temperature occurs–relieving the OS of the
overhead associated with polling (see Detecting Temperature Changes for more details).
11.5 Native OS Device Driver Thermal Interfaces
OS implementations compatible with the ACPI 3.0 thermal model, interface with the thermal objects of a thermal zone
but also comprehend the thermal zone devices’ OS native device driver interfaces that perform similar functions to the
thermal objects at the device level.
The recommended native OS device driver thermal interfaces that enable OSPM to perform optimal performance /
thermal management include:
• Reading a value from a device’s embedded thermal sensor
• Reading a value that indicates whether temperature and trip point values are reported in absolute or relative
temperatures
• Setting the platform’s cooling mode policy setting
• Reading the embedded thermal sensor’s threshold
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• Reading the device’s active and passive cooling temperature trip points
• Reading the device’s association to a thermal zone
• Signaling the crossing of a thermal trip point
• Reading the desired polling frequency at which to check the devices temperature if the device cannot signal
OSPM or signal OSPM optimally (both before and after a temperature trip point is crossed)
• Setting / limiting a device’s performance / throttling states
• Engaging / disengaging a device’s active cooling controls
These interfaces are OS speciﬁc and as such the OS vendor deﬁnes the exact interface deﬁnition for each target
operating system.
11.6 Thermal Zone Interface Requirements
While not all thermal zone interfaces are required to be present in each thermal zone, OSPM levies conditional re-
quirements for the presence of speciﬁc thermal zone interfaces based on the existence of other related thermal zone
interfaces. These interfaces may be implemented by thermal zone-wide objects or by OS-speciﬁc device driver ex-
posed thermal interfaces. The requirements are outlined below:
• A thermal zone must contain at least one temperature interface; either the _TMP object or a member device
temperature interface.
• A thermal zone must contain at least one trip point (critical, near critical, active, or passive).
• If _ACx is deﬁned then an associated _ALx must be deﬁned (e.g. deﬁning _AC0 requires _AL0 also be deﬁned).
• If _PSV is deﬁned then either the _PSL or _TZD objects must exist. The _PSL and _TZD objects may both
exist.
• If _PSL is deﬁned then:
–If a linear performance control register is deﬁned (via either P_BLK or the _PTC, _TSS, _TPC objects)
for a processor deﬁned in _PSL or for a processor device in the zone as indicated by _TZM then the _TC1,
_TC2, and objects must exist. A_TFP or _TSP object must also be deﬁned if the device requires polling.
–If a linear performance control register is not deﬁned (via either P_BLK or the _PTC, _TSS, _TPC objects)
for a processor deﬁned in _PSL or for a processor device in the zone as indicated by _TZM then the
processor must support processor performance states (in other words, the processor’s processor object
must include _PCT, _PSS, and _PPC).
• If _PSV is deﬁned and _PSL is not deﬁned then at least one device in thermal zone, as indicated by either the
_TZD device list or devices’ _TZM objects, must support device performance states.
• _SCP is optional.
• _TZD is optional outside of the _PSV requirement outlined above.
• If _HOT is deﬁned then the system must support the S4 sleeping state.
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11.7 Thermal Zone Examples
11.7.1 Example: The Basic Thermal Zone
The following ASL describes a basic conﬁguration where the entire system is treated as a single thermal zone. Cooling

devices for this thermal zone consist of a processor and one single-speed fan. This is an example only.
Notice that this thermal zone object (TZ0) is deﬁned in the \_SB scope. Thermal zone objects should appear in the
namespace under the portion of the system that comprises the thermal zone. For example, a thermal zone that is
isolated to a docking station should be deﬁned within the scope of the docking station device. Besides providing for
a well-organized namespace, this conﬁguration allows OSPM to dynamically adjust its thermal policy as devices are
Device(CPU0) {
Name(_HID, "ACPI0007")
Name(_UID, 1) // unique number forthis processor
}
<...>
Name(_HID, EISAID("PNP0C09")) // ID forthis EC
// current resource description forthis EC
})
Name(_GPE, 0) // GPE index forthis EC
MODE, 1, // thermal policy (quiet/perform)
FAN, 1, // fan power (on/off)
, 6, // reserved
AC0, 16, // active cooling temp (fan high)
, 16, // reserved
HOT 16, // critical S4 temp
CRT, 16 // critical temp
}
// following isa method that OSPM will schedule after
// it receives an SCI andqueries the EC to receive value 7
Notify (\_SB.PCI0.ISA0.EC0.TZ0, 0x80)
} // end of Notify method
// fan cooling on/off - engaged at AC0 temp
PowerResource(PFAN, 0, 0) {
Method(_STA) { Return (\_SB.PCI0.ISA0.EC0.FAN) } // check power state
Method(_ON) { Store (One, \\_SB.PCI0.ISA0.EC0.FAN) } // turn on fan
Method(_OFF) { Store ( Zero, \\_SB.PCI0.ISA0.EC0.FAN) } // turn off fan
}
// Create FAN device object
Device (FAN) {
// Device ID forthe FAN
Name(_HID, EISAID("PNP0C0B"))
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// list power resource forthe fan
Name(_PR0, Package(){PFAN})
}
Method(_AC0) { Return (\_SB.PCI0.ISA0.EC0.AC0) } // fan high temp
Name(_AL0, Package(){\_SB.PCI0.ISA0.EC0.FAN}) // fan isact cool dev
Name(_PSL, Package (){\_SB.CPU0}) // passive cooling devices
Method(_HOT) { Return (\_SB.PCI0.ISA0.EC0.HOT) } // get critical S4 temp
Method(_CRT) { Return (\_SB.PCI0.ISA0.EC0.CRT) } // get critical temp
Method(_SCP, 1) { Store (Arg1, \\_SB.PCI0.ISA0.EC0.MODE) } // set cooling mode
Name(_TZP, 0) // polling notrequired
Name (_STR, Unicode ("System thermal zone"))
} // end of \\_SB.PCI0.ISA0 scope-
11.7.2 Example: Multiple-Speed Fans
The following ASL describes a thermal zone consisting of a processor and one dual-speed fan. As with the previous
example, this thermal zone object (TZ0) is deﬁned in the _SB scope and represents the entire system. This is an
example only.
}
<...>
})
FAN0, 1, // fan strength high/off
FAN1, 1, // fan strength low/off
, 5, // reserved
AC0, 16, // active cooling temp (high)
AC1, 16, // active cooling temp (low)
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HOT 18, // critical S4 temp
}
// following isa method that OSPM will schedule after it
// receives an SCI andqueries the EC to receive value 7
} end of Notify method
// fan cooling mode high/off - engaged at AC0 temp
PowerResource(FN10, 0, 0) {
Method(_STA) { Return (\_SB.PCI0.ISA0.EC0.FAN0) } // check power state
Method(_ON) { Store (One, \\_SB.PCI0.ISA0.EC0.FAN0) } // turn on fan at
˓→high
Method(_OFF) { Store (Zero, \\_SB.PCI0.ISA0.EC0.FAN0) } // turn off fan
}
// fan cooling mode low/off - engaged at AC1 temp
PowerResource(FN11, 0, 0) {
Method(_STA) { Return (\_SB.PCI0.ISA0.EC0.FAN1) } // check power state
Method(_ON) { Store (One, \\_SB.PCI0.ISA0.EC0.FAN1) } // turn on fan at
˓→low
Method(_OFF) { Store (Zero, \\_SB.PCI0.ISA0.EC0.FAN1) } // turn off fan
}
// Following isa single fan withtwo speeds. This isrepresented
// by creating two logical fan devices. When FN2 isturned on then
// the fan isat a low speed. When FN1 andFN2 are both on then
// the fan isat high speed.
//
// Create FAN device object FN1
Device (FN1) {
Name(_PR0, Package(){FN10, FN11})
}
// Create FAN device object FN2
Device (FN2) {
Name(_PR0, Package(){FN10})
}
Method(_AC1) { Return (\_SB.PCI0.ISA0.EC0.AC1) } // fan low temp
Name(_AL0, Package() {\_SB.PCI0.ISA0.EC0.FN1}) // active cooling (high)
Name(_AL1, Package() {\_SB.PCI0.ISA0.EC0.FN2}) // active cooling (low)
Name(_PSL, Package() {\_SB.CPU0}) // passive cooling devices
Method(_CRT) { Return (\_SB.PCI0.ISA0.EC0.CRT) } // get crit. temp
Method(_SCP, 1) { Store (Arg1, \\_SB.PCI0.ISA0.EC0.MODE) } // cooling mode
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} // end of \\_SB.PCI0.ISA0 scope
11.7.3 Example: Thermal Zone with Multiple Devices
//
// Load additional objects if3.0 Thermal model support isavailable
//
Method(_INI, 0) {
If (\_OSI("3.0 Thermal Model")) {
LoadTable("OEM1", "PmRef", "Cpu0", " \\_SB.CPU0") // 3.0 Thermal Model
}
}
// For brevity, most processor objects have been excluded
//from this example (such as\_PSS, \_CST, \_PCT, \_PPC, etc.)
// Processor Throttle Control object
Name(_PTC, ResourceTemplate() {
Register(SystemIO, 32, 0, 0x120) // Processor Control
Register(SystemIO, 32, 0, 0x120) // Processor Status
})
// Throttling Supported States
// The values shown are forexemplary purposes only
Name(_TSS, Package() {
// Read: freq percentage, power, latency, control, status
Package() {0x64, 1000, 0x0, 0x7, 0x0}, // Throttle off (100%)
Package() {0x58, 800, 0x0, 0xF, 0x0}, // 87.5%
Package() {0x4B, 600, 0x0, 0xE, 0x0}, // 75%
Package() {0x3F, 400, 0x0, 0xD, 0x0} // 62.5%
})
// Throttling Present Capabilities
Method(_TPC) {
If(\_SB.AC) {
Return(0) // All throttle states available
} Else {
Return(2) // Throttle states >= 2 are available
}
}
} // end of CPU0 scope
Device(CPU1) {
//
//
LoadTable("OEM1", "PmRef", "Cpu1", " \\_SB.CPU1") // 3.0 Thermal Model
}
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}
//from this example (such as\_PSS, \_CST, \_PCT, \_PPC, \_PTC, etc.)
})
})

//
}
}
})
})
If(\_SB.AC)
{Return(0) // All throttle states available
} Else {
}
}
} // end of CPU1 scope
//
//
LoadTable("OEM1", "PmRef", "Tz3", " \\_SB.PCI0.ISA0.EC0") // 3.0 Tz
}
}
// Current resource description forthis EC
})
// Create EC's region and field for thermal support
AC0, 16, // active cooling temp
HOT, 16, // critical S4 temp
}
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// Following isa method that OSPM will schedule after it
Method(_ON) { Store (One, \\_SB.PCI0.ISA0.EC0.FAN0) } // turn on fan at high
}
// Following isa single fan withone speed.
}
// Receives an SCI andqueries the EC to receive value 7
// Create standard specific thermal zone
Name(_PSL, Package() {\_SB.CPU0, \\_SB.CPU1}) // passive cooling devices
Name(_AL0, Package() {\_SB.PCI0.ISA0.EC0.FN1}) // active cooling
Method(_AC0) { Return (\_SB.PCI0.ISA0.EC0.AC0) } // fan temp (high)
Method(_AC1) { Return (\_SB.PCI0.ISA0.EC0.AC1) } // fan temp (low)
Method(_SCP, 1) { Store (Arg0, \\_SB.PCI0.ISA0.EC0.MODE) } // set cooling mode
//
// ACPI 3.0 Thermal Model SSDT
//
"TZASSDT.aml",
"OEM1",
0x01,
"PmRef",
"Tz3",
0x3000
)
{
External(\_SB.PCI0.ISA0.EC0, DeviceObj)
External(\_SB.CPU0, DeviceObj)
External(\_SB.CPU1, DeviceObj)
Scope(\_SB.PCI0.ISA0.EC0)
{
// Create an ACPI 3.0 specific thermal zone
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// This TRT is forexemplary purposes only
Name(_TRT, Package() {
// Thermal relationship package data. A package isgenerated for
// each permutation of device sets. 2 devices = 4 entries.
// Read: source, target, thermal influence, sampling period, 4 reserved
Package () {\_SB.CPU0, \\_SB.CPU0, 20, 1, 0, 0, 0, 0},
Package () {\_SB.CPU0, \\_SB.CPU1, 10, 15, 0, 0, 0, 0},
Package () {\_SB.CPU1, \\_SB.CPU0, 10, 15, 0, 0, 0, 0},
Package () {\_SB.CPU1, \\_SB.CPU1, 20, 1, 0, 0, 0, 0}
}) // end of TRT
} // end of EC0 Scope
} // end of SSDT
//
// CPU0 3.0 Thermal Model SSDT
//
"CPU0SSDT.aml",
"OEM1",
0x01,
"PmRef",
"CPU0",
0x3000
)
{
External(\_SB.PCI0.ISA0.TZ0, ThermalZoneObj)
Scope(\_SB.CPU0)
{
//
// Add the objects required for3.0 extended thermal support
//
// Create a region andfields forthermal support; the platform
// fills inthe values andtraps on writes to enable hysteresis.
// The Operation Region location isinvalid
OperationRegion(CP00, SystemMemory, 0x00000000, 0xA)
Field(CP00, ByteAcc, Lock, Preserve) {
SCP, 1, // thermal policy (passive/active)
RTV, 1, // absolute orrelative temperature
CRT, 16, // critical temp
TPT, 16, // Temp trip point crossed
TST, 8 // Temp sensor threshold
}
Method(_TZM, 0) { Return(\_SB.PCI0.ISA0.TZ0) } // thermal zone member
// Some thermal zone methods are now located under the
// thermal device participating inthe 3.0 thermal model.
// These methods provide device specific thermal information
Method(_SCP, 1) { Store (Arg0, \\_SB.CPU0.SCP) } // set cooling mode
Method(_RTV) { Return (\_SB.CPU0.RTV) } // absolute orrelative temp
Method(_AC0) { Return (\_SB.CPU0.AC0) } // active cooling (fan) temp
Method(_PSV) { Return (\_SB.CPU0.PSV) } // passive cooling temp
Method(_CRT) { Return (\_SB.CPU0.CRT) } // critical temp
Name(_TC1, 4) // thermal constant 1 (INVALID)
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Name(_TC2, 3) // thermal constant 2 (INVALID)
Method(_TPT, 1) { Store (Arg0, \\_SB.CPU0.TPT)} // trip point temp
Method(_TST) { Return (\_SB.CPU0.TST) } // temp sensor threshold
//
// CPU1 3.0 Thermal Model SSDT
//
"CPU1SSDT.aml",
"OEM1",
0x01,
"PmRef",
"CPU1",
0x3000
)
{
Scope(\_SB.CPU1)
{
//
//
OperationRegion(CP01, SystemIO, 0x00000008, 0xA)
Field(CP01, ByteAcc, Lock, Preserve) {
}
Method(_SCP, 1) { Store (Arg0, \\_SB.CPU1.SCP) } // set cooling mode
Method(_RTV) { Return (\_SB.CPU1.RTV) } // absolute orrelative temp
Method(_AC0) { Return (\_SB.CPU1.AC0) } // active cooling (fan) temp
Method(_PSV) { Return (\_SB.CPU1.PSV) } // passive cooling temp
Method(_CRT) { Return (\_SB.CPU1.CRT) } // critical temp
Method(_TPT, 1) { Store (Arg0, \\_SB.CPU1.TPT)} // trip point temp
Method(_TST) { Return (\_SB.CPU1.TST) } // temp sensor threshold
11.7. Thermal Zone Examples 700CHAPTER
TWELVE
ACPI EMBEDDED CONTROLLER INTERFACE SPECIFICATION
ACPI deﬁnes a standard hardware and software communications interface between an OS driver and an embedded
controller. This allows any OS to provide a standard driver that can directly communicate with an embedded controller
in the system, thus allowing other drivers within the system to communicate with and use the resources of system
embedded controllers. This in turn enables the OEM to provide platform features that the OS OSPM and applications
can take advantage of.
ACPI also deﬁnes a standard hardware and software communications interface between an OS driver and an Embedded
Controller-based SMB-HC (EC-SMB-HC).
The ACPI standard supports multiple embedded controllers in a system, each with its own resources. Each embedded
controller has a ﬂat byte-addressable I/O space, currently deﬁned as 256 bytes. Features implemented in the embedded
controller have an event “query” mechanism that allows feature hardware implemented by the embedded controller
to gain the attention of an OS driver or ASL/AML code handler. The interface has been speciﬁed to work on the
most popular embedded controllers on the market today, only requiring changes in the way the embedded controller is
“wired” to the host interface.
Two interfaces are speciﬁed:
• A private interface, exclusively owned by the embedded controller driver.
• A shared interface, used by the embedded controller driver and some other driver.
This interface is separate from the traditional PC keyboard controller. Some OEMs might choose to implement the
ACPI Embedded Controller Interface (ECI) within the same embedded controller as the keyboard controller function,

but the ECI requires its own unique host resources (interrupt event and access registers).
This interface does support sharing the ECI with an inter-environment interface (such as SMI) and relies on the ACPI-
deﬁned “Global Lock” protocol. Note, however, that HW-reduced ACPI platforms, which do not support the Global
Lock, cannot share the EC interface. For information about the Global Lock interface, see Section 6.5.7.
Both the shared and private EC interfaces are described in the following sections.
The ECI has been designed such that a platform can use it in either the legacy or ACPI modes with minimal changes
between the two operating environments. This is to encourage standardization for this interface to enable faster
development of platforms as well as opening up features within these controllers to higher levels of software.
701Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
12.1 Embedded Controller Interface Description
Embedded controllers are the general class of microcontrollers used to support OEM-speciﬁc implementations. The
ACPI speciﬁcation supports embedded controllers in any platform design, as long as the microcontroller conforms to
one of the models described in this section. The embedded controller is a unique feature in that it can perform complex
low-level functions through a simple interface to the host microprocessor(s).
Although there is a large variety of microcontrollers in the market today, the most commonly used embedded con-
trollers include a host interface that connects the embedded controller to the host data bus, allowing bi-directional
communications. A bi-directional interrupt scheme reduces the host processor latency in communicating with the
embedded controller.
Currently, the most common host interface architecture incorporated into microcontrollers is modeled after the stan-
dard IA-PC architecture keyboard controller. This keyboard controller is accessed at 0x60 and 0x64 in system I/O
space. Port 0x60 is termed the data register, and allows bi-directional data transfers to and from the host and embed-
ded controller. Port 0x64 is termed the command/status register; it returns port status information upon a read, and
generates a command sequence to the embedded controller upon a write. This same class of controllers also includes
a second decode range that shares the same properties as the keyboard interface by having a command/status register
and a data register. The following diagram graphically depicts this interface.
Fig. 12.1: Shared Interface
The diagram above depicts the general register model supported by the ACPI Embedded Controller Interface.
The ﬁrst method uses an embedded controller interface shared between OSPM and the system management code,
which requires the Global Lock semaphore overhead to arbitrate ownership. The second method is a dedicated embed-
ded controller decode range for sole use by OSPM driver. The following diagram illustrates the embedded controller
architecture that includes a dedicated ACPI interface.
The private interface allows OSPM to communicate with the embedded controller without the additional software
overhead associated with using the Global Lock. Several common system conﬁgurations can provide the additional
embedded controller interfaces:
12.1. Embedded Controller Interface Description 702Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 12.2: Private Interface
12.1. Embedded Controller Interface Description 703Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
• Non-shared embedded controller. This will be the most common case where there is no need for the system
management handler to communicate with the embedded controller when the system transitions to ACPI mode.
OSPM processes all normal types of system management events, and the system management handler does not
need to take any actions.
• Integrated keyboard controller and embedded controller. This provides three host interfaces as described earlier
by including the standard keyboard controller in an existing component (chip set, I/O controller) and adding a
discrete, standard embedded controller with two interfaces for system management activities.
• Standard keyboard controller and embedded controller. This provides three host interfaces by providing a key-
board controller as a distinct component, and two host interfaces are provided in the embedded controller for
system management activities.
• Two embedded controllers. This provides up to four host interfaces by using two embedded controllers; one
controller for system management activities providing up to two host interfaces, and one controller for keyboard
controller functions providing up to two host interfaces.
• Embedded controller and no keyboard controller. Future platforms might provide keyboard functionality
through an entirely different mechanism, which would allow for two host interfaces in an embedded controller
for system management activities.
To handle the general embedded controller interface (as opposed to a dedicated interface) model, a method is available
to make the embedded controller a shareable resource between multiple tasks running under the operating system’s
control and the system management interrupt handler. This method, as described in this section, requires several
changes:
• Additional external hardware
• Embedded controller ﬁrmware changes
• System management interrupt handler ﬁrmware changes
• Operating software changes
Access to the shared embedded controller interface requires additional software to arbitrate between the operating
system’s use of the interface and the system management handler’s use of the interface. This is done using the Global
Lock as described in Section 6.5.7, but is not supported on HW-reduced ACPI platforms.
This interface sharing protocol also requires embedded controller ﬁrmware changes, in order to ensure that collisions
do not occur at the interface. A collision could occur if a byte is placed in the system output buffer and an interrupt is
then generated. There is a small window of time when the incorrect recipient could receive the data. This problem is
resolved by ensuring that the ﬁrmware in the embedded controller does not place any data in the output buffer until it
is requested by OSPM or the system management handler.
More detailed algorithms and descriptions are provided in the following sections.
12.2 Embedded Controller Register Descriptions
The embedded controller contains three registers at two address locations: EC_SC and EC_DATA. The EC_SC, or
Embedded Controller Status/Command register, acts as two registers: a status register for reads to this port and a
command register for writes to this port. The EC_DATA (Embedded Controller Data register) acts as a port for
transferring data between the host CPU and the embedded controller.
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12.2.1 Embedded Controller Status, EC_SC (R)
This is a read-only register that indicates the current status of the embedded controller interface.
Table 12.1: Read Only Register Table
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IGN SMI_EVT SCI_EVT BURST CMD IGN IBF OBF
Where:
IGN Ignored
SMI_EVT: 1 - Indicates SMI event is pending (requesting SMI query).
0 - No SMI events are pending.
SCI_EVT: 1 - Indicates SCI event is pending (requesting SCI query).
0 - No SCI events are pending.
BURST: 1 - Controller is in burst mode for polled command processing.
0 - Controller is in normal mode for interrupt-driven command processing.
CMD: 1 - Byte in data register is a command byte (only used by controller).
0 - Byte in data register is a data byte (only used by controller).
IBF: 1 - Input buffer is full (data ready for embedded controller).
0 - Input buffer is empty.
OBF: 1 - Output buffer is full (data ready for host).
0 - Output buffer is empty.
The Output Buffer Full (OBF) ﬂag is set when the embedded controller has written a byte of data into the command
or data port but the host has not yet read it. After the host reads the status byte and sees the OBF ﬂag set, the host
reads the data port to get the byte of data that the embedded controller has written. After the host reads the data byte,
the OBF ﬂag is cleared automatically by hardware. This signals the embedded controller that the data has been read
by the host and the embedded controller is free to write more data to the host.
The Input Buffer Full (IBF) ﬂag is set when the host has written a byte of data to the command or data port, but the
embedded controller has not yet read it. After the embedded controller reads the status byte and sees the IBF ﬂag
set, the embedded controller reads the data port to get the byte of data that the host has written. After the embedded
controller reads the data byte, the IBF ﬂag is automatically cleared by hardware. This is the signal to the host that the

data has been read by the embedded controller and that the host is free to write more data to the embedded controller.
The SCI event (SCI_EVT) ﬂag is set when the embedded controller has detected an internal event that requires the
operating system’s attention. The embedded controller sets this bit in the status register, and generates an SCI to
OSPM. OSPM needs this bit to differentiate command-complete SCIs from notiﬁcation SCIs. OSPM uses the query
command to request the cause of the SCI_EVT and take action. For more information, see Embedded Controller
Command Set .
The SMI event (SMI_EVT) ﬂag is set when the embedded controller has detected an internal event that requires the
system management interrupt handler’s attention. The embedded controller sets this bit in the status register before
generating an SMI.
The Burst (BURST) ﬂag indicates that the embedded controller has received the burst enable command from the host,
has halted normal processing, and is waiting for a series of commands to be sent from the host. This allows OSPM
or system management handler to quickly read and write several bytes of data at a time without the overhead of SCIs
between the commands.
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12.2.2 Embedded Controller Command, EC_SC (W)
This is a write-only register that allows commands to be issued to the embedded controller. Writes to this port are
latched in the input data register and the input buffer full ﬂag is set in the status register. Writes to this location also
cause the command bit to be set in the status register. This allows the embedded controller to differentiate the start of
a command sequence from a data byte write operation.
12.2.3 Embedded Controller Data, EC_DATA (R/W)
This is a read/write register that allows additional command bytes to be issued to the embedded controller, and allows
OSPM to read data returned by the embedded controller. Writes to this port by the host are latched in the input data
register, and the input buffer full ﬂag is set in the status register. Reads from this register return data from the output
data register and clear the output buffer full ﬂag in the status register.
12.3 Embedded Controller Command Set
The embedded controller command set allows OSPM to communicate with the embedded controllers. ACPI deﬁnes
the commands and their byte encodings for use with the embedded controller that are shown in the following table.
Table 12.3: Embedded Controller Commands
Embedded Controller Command Command Byte Encoding
Read Embedded Controller (RD_EC) 0x80
Write Embedded Controller (WR_EC) 0x81
Burst Enable Embedded Controller (BE_EC) 0x82
Burst Disable Embedded Controller (BD_EC) 0x83
Query Embedded Controller (QR_EC) 0x84
12.3.1 Read Embedded Controller, RD_EC (0x80)
This command byte allows OSPM to read a byte in the address space of the embedded controller. This command byte
is reserved for exclusive use by OSPM, and it indicates to the embedded controller to generate SCIs in response to
related transactions (that is, IBF=0 or OBF=1 in the EC Status Register), rather than SMIs. This command consists of
a command byte written to the Embedded Controller Command register (EC_SC), followed by an address byte written
to the Embedded Controller Data register (EC_DATA). The embedded controller then returns the byte at the addressed
location. The data is read at the data port after the OBF ﬂag is set.
12.3.2 Write Embedded Controller, WR_EC (0x81)
This command byte allows OSPM to write a byte in the address space of the embedded controller. This command
byte is reserved for exclusive use by OSPM, and it indicates to the embedded controller to generate SCIs in response
to related transactions (that is, IBF=0 or OBF=1 in the EC Status Register), rather than SMIs. This command allows
OSPM to write a byte in the address space of the embedded controller. It consists of a command byte written to the
Embedded Controller Command register (EC_SC), followed by an address byte written to the Embedded Controller
Data register (EC_DATA), followed by a data byte written to the Embedded Controller Data Register (EC_DATA);
this is the data byte written at the addressed location.
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12.3.3 Burst Enable Embedded Controller, BE_EC (0x82)
This command byte allows OSPM to request dedicated attention from the embedded controller and (except for critical
events) prevents the embedded controller from doing tasks other than receiving command and data from the host
processor (either the system management interrupt handler or OSPM). This command is an optimization that allows
the host processor to issue several commands back to back, in order to reduce latency at the embedded controller
interface. When the controller is in the burst mode, it should transition to the burst disable state if the host does not
issue a command within the following guidelines:
• First Access - 400 microseconds
• Subsequent Accesses - 50 microseconds each
• Total Burst Time - 1 millisecond
In addition, the embedded controller can disengage the burst mode at any time to process a critical event. If the
embedded controller disables burst mode for any reason other than the burst disable command, it should generate an
SCI to OSPM to indicate the change.
While in burst mode, the embedded controller follows these guidelines for OSPM driver:
SCIs are generated as normal, including IBF=0 and OBF=1.
Accesses should be responded to within 50 microseconds.
Burst mode is entered in the following manner:
OSPM driver writes the Burst Enable Embedded Controller, BE_EC (0x82) command byte and then the Embedded
Controller will prepare to enter the Burst mode. This includes processing any routine activities such that it should be
able to remain dedicated to OSPM interface for ~ 1 microsecond.
The Embedded Controller sets the Burst bit of the Embedded Controller Status Register, puts the Burst Acknowledge
byte (0x90) into the SCI output buffer, sets the OBF bit, and generates an SCI to signal OSPM that it is in Burst mode.
Burst mode is exited the following manner:
OSPM driver writes the Burst Disable Embedded Controller, BD_EC (0x83) command byte and then the Embedded
Controller will exit Burst mode by clearing the Burst bit in the Embedded Controller Status register and generating an
SCI signal (due to IBF=0).
The Embedded Controller clears the Burst bit of the Embedded Controller Status Register.
12.3.4 Burst Disable Embedded Controller, BD_EC (0x83)
This command byte releases the embedded controller from a previous burst enable command and allows it to resume
normal processing. This command is sent by OSPM or system management interrupt handler after it has completed
its entire queued command sequence to the embedded controller.
12.3.5 Query Embedded Controller, QR_EC (0x84)
OSPM driver sends this command when the SCI_EVT ﬂag in the EC_SC register is set. When the embedded controller
has detected a system event that must be communicated to OSPM, it ﬁrst sets the SCI_EVT ﬂag in the EC_SC register,
generates an SCI, and then waits for OSPM to send the query (QR_EC) command. OSPM detects the embedded
controller SCI, sees the SCI_EVT ﬂag set, and sends the query command to the embedded controller. Upon receipt of
the QR_EC command byte, the embedded controller places a notiﬁcation byte with a value between 0-255, indicating
the cause of the notiﬁcation. The notiﬁcation byte indicates which interrupt handler operation should be executed by
OSPM to process the embedded controller SCI. The query value of zero is reserved for a spurious query result and
indicates “no outstanding event.”
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12.4 SMBus Host Controller Notiﬁcation Header (Optional),
OS_SMB_EVT
This query command notiﬁcation header is the special return code that indicates events with an SMBus controller
implemented within an embedded controller. These events include:
• Command completion
• Command error
• Alarm reception
The actual notiﬁcation value is declared in the EC-SMB-HC device object in the ACPI Namespace.
12.5 Embedded Controller Firmware
The embedded controller ﬁrmware must obey the following rules in order to be ACPI-compatible:
•SMI Processing . Although it is not explicitly stated in the command speciﬁcation section, a shared embedded
controller interface has a separate command set for communicating with each environment it plans to support.
In other words, the embedded controller knows which environment is generating the command request, as well
as which environment is to be notiﬁed upon event detection, and can then generate the correct interrupts and no-
tiﬁcation values. This implies that a system management handler uses commands that parallel the functionality

of all the commands for ACPI including query, read, write, and any other implemented speciﬁc commands.
•SCI/SMI Task Queuing . If the system design is sharing the interface between both a system management
interrupt handler and OSPM, the embedded controller should always be prepared to queue a notiﬁcation if
it receives a command. The embedded controller only sets the appropriate event ﬂag in the status (EC_SC)
register if the controller has detected an event that should be communicated to the OS or system management
handler. The embedded controller must be able to ﬁeld commands from either environment without loss of the
notiﬁcation event. At some later time, the OS or system management handler issues a query command to the
embedded controller to request the cause of the notiﬁcation event.
•Notiﬁcation Management . The use of the embedded controller means using the query (QR_EC) command to
notify OSPM of system events requiring action. If the embedded controller is shared with the operating system,
the SMI handler uses the SMI_EVT ﬂag and an SMI query command (not deﬁned in this document) to receive
the event notiﬁcations. The embedded controller doesn’t place event notiﬁcations into the output buffer of a
shared interface unless it receives a query command from OSPM or the system management interrupt handler.
12.6 Interrupt Model
The EC Interrupt Model uses pulsed interrupts to speed the clearing process. The Interrupt is ﬁrmware generated
using an EC general-purpose output and has the waveform shown in Interrupt Model . The embedded controller SCI
is always wired directly to a GPE input or a GPIO pin, and OSPM driver treats this as an edge event (the EC SCI
cannot be shared).
12.4. SMBus Host Controller Notiﬁcation Header (Optional), OS_SMB_EVT 708Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 12.3: Interrupt Model
12.6.1 Event Interrupt Model
The embedded controller must generate SCIs for the events listed in the following table.
Table 12.4: Events for Which Embedded Controller Must Generate
SCIs
Event Description
IBF=0 Signals that the embedded controller has read the last command or data from the input
buffer and the host is free to send more data.
OBF=1 Signals that the embedded controller has written a byte of data into the output buffer and
the host is free to read the returned data.
SCI_EVT=1 Signals that the embedded controller has detected an event that requires OS attention.
OSPM should issue a query (QR_EC) command to ﬁnd the cause of the event.
12.6.2 Command Interrupt Model
The embedded controller must generate SCIs for commands as follows:
Table 12.5: Read Command (3 Bytes)
Byte #1 (Command byte Header) Interrupt on IBF=0
Byte #2 (Address byte to read) No Interrupt
Byte #3 (Data read to host) Interrupt on OBF=1
Table 12.6: Write Command (3 Bytes)
Byte #2 (Address byte to write) Interrupt on IBF=0
Byte #3 (Data to read ) Interrupt on IBF=0
Table 12.7: Query Command (2 Bytes)
Byte #1 (Command byte Header) No Interrupt
Byte #2 (Query value to host) Interrupt on OBF=1
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Table 12.8: Burst Enable Command (2 Bytes)
Byte #2 (Burst acknowledge byte) Interrupt on OBF=1
Table 12.9: Burst Disable Command (1 Byte)
12.7 Embedded Controller Interfacing Algorithms
To initiate communications with the embedded controller, OSPM or system management handler acquires ownership
of the interface. This ownership is acquired through the use of the Global Lock , or is owned by default by OSPM as a
non-shared resource (and the Global Lock is not required for accessibility).
After ownership is acquired, the protocol always consists of the passing of a command byte. The command byte will
indicate the type of action to be taken. Following the command byte, zero or more data bytes can be exchanged in
either direction. The data bytes are deﬁned according to the command byte that is transferred.
The embedded controller also has two status bits that indicate whether the registers have been read. This is used to
ensure that the host or embedded controller has received data from the embedded controller or host. When the host
writes data to the command or data register of the embedded controller, the input buffer ﬂag (IBF) in the status register
is set within 1 microsecond. When the embedded controller reads this data from the input buffer, the input buffer ﬂag
is reset. When the embedded controller writes data into the output buffer, the output buffer ﬂag (OBF) in the status
register is set. When the host processor reads this data from the output buffer, the output buffer ﬂag is reset.
12.8 Embedded Controller Description Information
Certain aspects of the embedded controller’s operation have OEM-deﬁnable values associated with them. The follow-
ing is a list of values that are deﬁned in the software layers of the ACPI speciﬁcation:
• Status ﬂag indicating whether the interface requires the use of the Global Lock.
• Bit position of embedded controller interrupt in general-purpose status register.
• Decode address for command/status register.
• Decode address for data register.
• Base address and query value of any EC-SMBus controller.
For implementation details of the above information, see Deﬁning an Embedded Controller Device in ACPI Namespace
andDeﬁning an EC SMBus Host Controller in ACPI Namespace .
An embedded controller will require the inclusion of the GLK method in its ACPI namespace if potentially contentious
accesses to device resources are performed by non-OS code. See _GLK (Global Lock) for details about the _GLK
method.
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12.9 SMBus Host Controller Interface via Embedded Controller
This section speciﬁes a standard interface that an ACPI-compatible OS can use to communicate with embedded
controller-based SMBus host controllers (EC-SMB-HC). This interface allows the host processor (under control of
OSPM) to manage devices on the SMBus. Typical devices residing on the SMBus include Smart Batteries, Smart
Battery Chargers, contrast/backlight control, and temperature sensors.
The EC-SMB-HC interface consists of a block of registers that reside in embedded controller space. These registers
are used by software to initiate SMBus transactions and receive SMBus notiﬁcations. By using a well-deﬁned register
set, OS software can be written to operate with any vendor’s embedded controller hardware.
Certain SMBus segments have special requirements that the host controller ﬁlters certain SMBus commands (for
example, to prevent an errant application or virus from potentially damaging the battery subsystem). This is most easily
accomplished by implementing the host interface controller through an embedded controller–as embedded controller
can easily ﬁlter out potentially problematic commands.
Notice that an EC-SMB-HC interface will require the inclusion of the GLK method in its ACPI namespace if poten-
tially contentious accesses to device resources are performed by non-OS code. See _GLK (Global Lock) for details on
using the _GLK method.
12.9.1 Register Description
The EC-SMBus host interface is a ﬂat array of registers that are arranged sequentially in the embedded controller
12.9.1.1 Status Register, SMB_STS
This register indicates general status on the SMBus. This includes SMB-HC command completion status, alarm
received status, and error detection status (the error codes are deﬁned later in this section). This register is cleared to
zeroes (except for the ALRM bit) whenever a new command is issued using a write to the protocol (SMB_PRTCL)
register. This register is always written with the error code before clearing the protocol register. The SMB-HC query
event (that is, an SMB-HC interrupt) is raised after the clearing of the protocol register.
Note: OSPM must ensure the ALRM bit is cleared after it has been serviced by writing ‘00’ to the SMB_STS register.
Table 12.10: Status Register, SMB_STS
Done ALRM RES STATUS
Where:
DONE: Indicates the last command has completed and no error.
ALRM: Indicates an SMBus alarm message has been received.
RES: Reserved
STATUS: Indicates SMBus communication status for one of the reasons listed in the following table.
Table 12.11: SMBus Status Codes
Status Code Name Description
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00h SMBus OK Indicates the transaction has been successfully completed.
07h SMBus Unknown
FailureIndicates failure because of an unknown SMBus error.
10h SMBus Device Ad-
dress Not Acknowl-
edgedIndicates the transaction failed because the slave device address was not

Where:
11h SMBus Device Er-
ror DetectedIndicates the transaction failed because the slave device signaled an error
condition.
12h SMBus Device
Command Access
DeniedIndicates the transaction failed because the SMBus host does not allow
the speciﬁc command for the device being addressed. For example, the
SMBus host might not allow a caller to adjust the Smart Battery Charger’s
output.
13h SMBus Unknown
ErrorIndicates the transaction failed because the SMBus host encountered an
unknown error.
17h SMBus Device Ac-
cess DeniedIndicates the transaction failed because the SMBus host does not allow
access to the device addressed. For example, the SMBus host might not
allow a caller to directly communicate with an SMBus device that controls
the system’s power planes.
18h SMBus Timeout Indicates the transaction failed because the SMBus host detected a time-
out on the bus.
19h SMBus Host Un-
supported ProtocolIndicates the transaction failed because the SMBus host does not support
the requested protocol.
1Ah SMBus Busy Indicates that the transaction failed because the SMBus host reports that
the SMBus is presently busy with some other transaction. For example,
the Smart Battery might be sending charging information to the Smart
Battery Charger.
1Fh SMBus PEC (CRC-
8) ErrorIndicates that a Packet Error Checking (PEC) error occurred during the
last transaction.
All other error codes are reserved.
12.9.1.2 Protocol Register, SMB_PRTCL
This register determines the type of SMBus transaction generated on the SMBus. In addition to indicating the protocol
type to the SMB-HC, a write to this register initiates the transaction on the SMBus. Notice that bit 7 of the protocol
value is used to indicate whether packet error checking should be employed. A value of 1 (one) in this bit indicates
that PEC format should be used for the speciﬁed protocol, and a value of 0 (zero) indicates the standard (non-PEC)
format should be used.
Table 12.12: Protocol Register, SMB_PRTCL
Bit7 Bit6 to Bit0
PEC PROTOCOL
Where the PROTOCOL values are as follows:
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0x00 Controller Not In Use
0x01 Reserved
0x02 Write Quick Command
0x03 Read Quick Command
0x04 Send Byte
0x05 Receive Byte
0x06 Write Byte
0x07 Read Byte
0x08 Write Word
0x09 Read Word
0x0A Write Block
0x0B Read Block
0x0C Process Call
0x0D Block Write-Block Read Process Call
For example, the protocol value of 0x09 would be used to communicate to a device that supported the standard read
word protocol. If this device also supported packet error checking for this protocol, a value of 0x89 (read word with
PEC) could optionally be used. See the SMBus speciﬁcation for more information on packet error checking.
When OSPM initiates a new command such as write to the SMB_PRTCL register, the SMBus controller ﬁrst updates
the SMB_STS register and then clears the SMB_PRTCL register. After the SMB_PRTCL register is cleared, the host
controller query value is raised.
All other protocol values are reserved.
12.9.1.3 Address Register, SMB_ADDR
This register contains the 7-bit address to be generated on the SMBus. This is the ﬁrst byte to be sent on the SMBus
for all of the different protocols.
Table 12.13: Address Register, SMB_ADDR
Bit7 to Bit1 Bit0
ADDRESS (A6:A0) RES
Where:
ADDRESS: 7-bit SMBus address. This address is not zero-aligned (in other words, it is only a 7-bit address
(A6:A0) that is aligned from bit 1-7).
12.9.1.4 Command Register, SMB_CMD
This register contains the command byte that will be sent to the target device on the SMBus and is used for the
following protocols: send byte, write byte, write word, read byte, read word, process call, block read and block write.
It is not used for the quick commands or the receive byte protocol, and as such, its value is a “don’t care” for those
commands.
Table 12.14: Command Register, SMB_CMD
Bit7 to Bit0 COMMAND
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Where:
COMMAND Command byte to be sent to SMBus device.
12.9.1.5 Data Register Array, SMB_DATA[i], i=0-31
This bank of registers contains the remaining bytes to be sent or received in any of the different protocols that can be
run on the SMBus. The SMB_DATA[i] registers are deﬁned on a per-protocol basis and, as such, provide efﬁcient use
of register space.
Table 12.15: Data Register Array, SMB_DATA[i], i=0-31
Bit7 to Bit0 DATA
Where:
DATA One byte of data to be sent or received (depending upon protocol).
12.9.1.6 Block Count Register, SMB_BCNT
This register contains the number of bytes of data present in the SMB_DATA[i] registers preceding any write block
and following any read block transaction. The data size is deﬁned on a per protocol basis.
Table 12.16: Block Count Register, SMB_BCNT
Bit7 to Bit5 Bit4 to Bit0
RES BCNT
12.9.1.7 Alarm Address Register, SMB_ALRM_ADDR
This register contains the address of an alarm message received by the host controller, at slave address 0x8, from
the SMBus master that initiated the alarm. The address indicates the slave address of the device on the SMBus that
initiated the alarm message. The status of the alarm message is contained in the SMB_ALRM_DATAx registers. Once
an alarm message has been received, the SMB-HC will not receive additional alarm messages until the ALRM status
bit is cleared.
Table 12.17: Alarm Address Register, SMB_ALRM_ADDR
Where:
ADDRESS: Slave address (A6:A0) of the SMBus device that initiated the SMBus alarm message.
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12.9.1.8 Alarm Data Registers, SMB_ALRM_DATA[0], SMB_ALRM_DATA[1]
These registers contain the two data bytes of an alarm message received by the host controller, at slave address 0x8,
from the SMBus master that initiated the alarm. These data bytes indicate the speciﬁc reason for the alarm message,
such that OSPM can take actions. Once an alarm message has been received, the SMB-HC will not receive additional
alarm messages until the ALRM status bit is cleared.
Table 12.18: Alarm Data Registers, SMB_ALRM_DATA[0],
SMB_ALRM_DATA[1]
Bit7 to Bit0 DATA (D7:D0)
Where:
DATA Data byte received in alarm message.
The alarm address and alarm data registers are not read by OSPM until the alarm status bit is set. OSPM driver then
reads the 3 bytes, and clears the alarm status bit to indicate that the alarm registers are now available for the next event.
12.9.2 Protocol Description
This section describes how to initiate the different protocols on the SMBus through the interface described in Register
Description . The registers should all be written with the appropriate values before writing the protocol value that starts
the SMBus transaction. All transactions can be completed in one pass.
12.9.2.1 Write Quick
Data Sent:
SMB_ADDR: Address of SMBus device.
SMB_PRTCL: Write 0x02 to initiate the write quick protocol.
Data Returned:
SMB_STS: Status code for transaction.
SMB_PRTCL: 0x00 to indicate command completion.
12.9.2.2 Read Quick
Data Sent:
SMB_PRTCL: Write 0x03 to initiate the read quick protocol.
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12.9.2.3 Send Byte
Data Sent:
SMB_CMD: Command byte to be sent.
SMB_PRTCL: Write 0x04 to initiate the send byte protocol, or 0x84 to initiate the send byte protocol with PEC.
12.9.2.4 Receive Byte
Data Sent:
SMB_PRTCL: Write 0x05 to initiate the receive byte protocol, or 0x85 to initiate the receive byte protocol with
PEC.
SMB_DATA[0]: Data byte received.
12.9.2.5 Write Byte
Data Sent:
SMB_DATA[0]: Data byte to be sent.
SMB_PRTCL: Write 0x06 to initiate the write byte protocol, or 0x86 to initiate the write byte protocol with
PEC.
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12.9.2.6 Read Byte
Data Sent:
SMB_PRTCL: Write 0x07 to initiate the read byte protocol, or 0x87 to initiate the read byte protocol with PEC.
12.9.2.7 Write Word
Data Sent:

Data Sent:
PEC.
Data Sent:
Data Sent:
SMB_DATA[0]: Low data byte to be sent.
SMB_DATA[1]: High data byte to be sent.
SMB_PRTCL: Write 0x08 to initiate the write word protocol, or 0x88 to initiate the write word protocol with
PEC.
12.9.2.8 Read Word
Data Sent:
SMB_PRTCL: Write 0x09 to initiate the read word protocol, or 0x89 to initiate the read word protocol with PEC.
SMB_DATA[0]: Low data byte received.
SMB_DATA[1]: High data byte received.
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12.9.2.9 Write Block
Data Sent:
SMB_DATA[0-
31]:Data bytes to write (1-32).
SMB_BCNT: Number of data bytes (1-32) to be sent.
SMB_PRTCL: Write 0x0A to initiate the write block protocol, or 0x8A to initiate the write block protocol
with PEC.
12.9.2.10 Read Block
Data Sent:
SMB_PRTCL: Write 0x0B to initiate the read block protocol, or 0x8B to initiate the read block protocol with
PEC.
SMB_BCNT: Number of data bytes (1-32) received.
SMB_DATA[0-31]: Data bytes received (1-32).
12.9.2.11 Process Call
Data Sent:
SMB_PRTCL: Write 0x0C to initiate the process call protocol, or 0x8C to initiate the process call protocol with
PEC.
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12.9.2.12 Block Write-Block Read Process Call
Data Sent:
31]:Data bytes to write (1-31).
SMB_BCNT: Number of data bytes (1-31) to be sent.
SMB_PRTCL: Write 0x0D to initiate the write block-read block process call protocol, or 0x8D to initiate the write
block-read block process call protocol with PEC.
SMB_BCNT: Number of data bytes (1-31) received.
SMB_DATA[0-31]: Data bytes received (1-31).
Note: The following restrictions apply above: The aggregate data length of the write and read blocks must not exceed
32 bytes and each block (write and read) must contain at least 1 byte of data.
12.9.2.13 SMBus Register Set
The register set for the SMB-HC has the following format. All registers are 8 bit.
Table 12.19: SMB EC Interface
Location Register Name Description
BASE+0 SMB_PRTCL Protocol register
BASE+1 SMB_STS Status register
BASE+2 SMB_ADDR Address register
BASE+3 SMB_CMD Command register
BASE+4 SMB_DATA[0] Data register zero
BASE+5 SMB_DATA[1] Data register one
BASE+6 SMB_DATA[2] Data register two
BASE+7 SMB_DATA[3] Data register three
BASE+8 SMB_DATA[4] Data register four
BASE+9 SMB_DATA[5] Data register ﬁve
BASE+10 SMB_DATA[6] Data register six
BASE+11 SMB_DATA[7] Data register seven
BASE+12 SMB_DATA[8] Data register eight
BASE+13 SMB_DATA[9] Data register nine
BASE+14 SMB_DATA[10] Data register ten
BASE+15 SMB_DATA[11] Data register eleven
BASE+16 SMB_DATA[12] Data register twelve
BASE+17 SMB_DATA[13] Data register thirteen
BASE+18 SMB_DATA[14] Data register fourteen
BASE+19 SMB_DATA[15] Data register ﬁfteen
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Table 12.19 – continued from previous page
BASE+20 SMB_DATA[16] Data register sixteen
BASE+21 SMB_DATA[17] Data register seventeen
BASE+22 SMB_DATA[18] Data register eighteen
BASE+23 SMB_DATA[19] Data register nineteen
BASE+24 SMB_DATA[20] Data register twenty
BASE+25 SMB_DATA[21] Data register twenty-one
BASE+26 SMB_DATA[22] Data register twenty-two
BASE+27 SMB_DATA[23] Data register twenty-three
BASE+28 SMB_DATA[24] Data register twenty-four
BASE+29 SMB_DATA[25] Data register twenty-ﬁve
BASE+30 SMB_DATA[26] Data register twenty-six
BASE+31 SMB_DATA[27] Data register twenty-seven
BASE+32 SMB_DATA[28] Data register twenty-eight
BASE+33 SMB_DATA[29] Data register twenty-nine
BASE+34 SMB_DATA[30] Data register thirty
BASE+35 SMB_DATA[31] Data register thirty-one
BASE+36 SMB_BCNT Block Count Register
BASE+37 SMB_ALRM_ADDR Alarm address
BASE+38 SMB_ALRM_DATA[0] Alarm data register zero
BASE+39 SMB_ALRM_DATA[1] Alarm data register one
12.10 SMBus Devices
The embedded controller interface provides the system with a standard method to access devices on the SMBus. It does
not deﬁne the data and/or access protocol(s) used by any particular SMBus device. Further, the embedded controller
can (and probably will) serve as a gatekeeper to prevent accidental or malicious access to devices on the SMBus.
Some SMBus devices are deﬁned by their address and a speciﬁcation that describes the data and the protocol used to
access that data. For example, the Smart Battery System devices are deﬁned by a series of speciﬁcations including:
• Smart Battery Data speciﬁcation
• Smart Battery Charger speciﬁcation
• Smart Battery Selector speciﬁcation
• Smart Battery System Manager speciﬁcation
The embedded controller can also be used to emulate (in part or totally) any SMBus device.
12.10.1 SMBus Device Access Restrictions
In some cases, the embedded controller interface will not allow access to a particular SMBus device. Some SMBus
devices can and do communicate directly between themselves. Unexpected accesses can interfere with their normal
operation and cause unpredictable results.
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12.10.2 SMBus Device Command Access Restriction
There are cases where part of an SMBus device’s commands are public while others are private. Extraneous attempts
to access these commands might cause interference with the SMBus device’s normal operation.
The Smart Battery and the Smart Battery Charger are good examples of devices that should not have their entire
command set exposed. The Smart Battery commands the Smart Battery Charger to supply a speciﬁc charging voltage
and charging current. Attempts by anyone to alter these values can cause damage to the battery or the mobile system.
To protect the system’s integrity, the embedded controller interface can restrict access to these commands by returning
one of the following error codes: Device Command Access Denied (0x12) or Device Access Denied (0x17).
12.11 Deﬁning an Embedded Controller Device in ACPI Namespace
An embedded controller device is created using the named device object. The embedded controller’s device object
requires the following elements:
Table 12.20: Embedded Controller Device Object Control Methods
_CRS Named object that returns the Embedded Controller’s current resource settings. Embedded Con-
trollers are considered static resources; hence only return their deﬁned resources. The embedded
controller resides only in system I/O or memory space. The ﬁrst address region returned is the
data port, and the second address region returned is the status/command port for the embedded
controller. If the EC is used on a HW-Reduced ACPI platform, a third resource is required, which
is the GPIO Interrupt Connection resource for the EC’s SCI Interrupt. CRS is a standard device
conﬁguration control method deﬁned in _CRS (Current Resource Settings) .
_HID Named object that provides the Embedded Controller’s Plug and Play identiﬁer. This value is set
to PNP0C09. _HID is a standard device conﬁguration control method deﬁned in _HID (Hardware
ID).
_GPE Named Object that evaluates to either an integer or a package. If _GPE evaluates to an integer,
the value is the bit assignment of the SCI interrupt within the GPEx_STS register of a GPE
block described in the FADT that the embedded controller will trigger. If _GPE evaluates to a
package, then that package contains two elements. The ﬁrst is an object reference to the GPE
Block device that contains the GPE register that will be triggered by the embedded controller.
The second element is numeric (integer) that speciﬁes the bit assignment of the SCI interrupt

ID).
within the GPEx_STS register of the GPE Block device referenced by the ﬁrst element in the
package. This control method is speciﬁc to the embedded controller. This method is not required
on Hardware-reduced ACPI platforms.
_DSM Device Speciﬁc Method that allows a supported OSV to negotiate the platform FW preferred
interactions for the onboard embedded controller.
Arguments (Function 1):
• Arg0: A Buffer containing the UUID = {ecc0d5e9-3ee7-4f53-8c8f-766b839dddce}
• Arg1: An Integer containing the Revision ID = 0
• Arg2: An Integer containing the Function Index = 1
• Arg3: Empty package (not used)
Return Value (Function 1):
{FW-Granted Min Burst Length} A 32-bit buffer containing the minimum number of bytes the platform
FW has granted to be performed in ACPI Burst Mode when communicating with the EC opregion (a value
of 0 or all FFs is reserved).
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Implementation Note:
The intent of _DSM Function 1 is to optimize the OSV’s EC Opregion accesses performed in ACPI Burst Mode in a
regression-safe way. For legacy platforms that do not implement this change, the existing ACPI Burst Mode behavior
will remain unchanged, resolving concerns for regression. Platforms that do implement EC _DSM Function 1 must
do so only after conﬁrming that the platform takes no dependency on ACPI burst mode for opregion accesses less than
the return value of _DSM Function 1.
After the OSV has discovered both an ACPI EC namespace deﬁnition and a paired opregion deﬁnition under that
namespace, a supported OSV must invoke this _DSM before communicating with that opregion.
Other OSV changes are optional and implementation speciﬁc.
Example :
Device (H_EC) {
//
{
{
case(ToUUID("ecc0d5e9-3ee7-4f53-8c8f-766b839dddce"))
{
{
//
//
case(0)
{
{
// revision 0: function 1 issupported
case(0) { return(Buffer() {0x1})}
}
// revision 1+: No function yet supported
return(Buffer() {0x0})
}
//
// Function 1: Return Platform-FW Granted min number of bytes to use burst
// mode for
//
case(1)
{
... Platform FW logic to get min number of bytes to use Burst Mode for...
... It isrecommended to returna value larger than 1 ...
Return(Buffer() {0x2})
}
}
}
//
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// If notone of the UUIDs we recognize, then returna buffer
//withbit 0 set to 0 indicating no functions supported.
//
}
...
...
}
12.11.1 Example: EC Deﬁnition ASL Code
Example ASL code that deﬁnes an embedded controller device is shown below:
// PnP ID
ResourceTemplate(){ // port 0x62 and0x66
IO(Decode16, 0x62, 0x62, 0, 1),
/*For HW-Reduced ACPI Platforms, include a GPIO Interrupt Connection
˓→resource,
e.g. GPIO controller #2, pin 43.
GpioInt(Edge, ActiveHigh, ExclusiveAndWake,PullUp 0, " \\_SB.GPI2"){43}
*/
}
)
// Define that the EC SCI isbit 0 of the GP_
˓→STS register
Name(_GPE, 0) // Not required forHW-Reduced ACPI platforms
OperationRegion(ECOR, EmbeddedControl, 0, 0xFF)
Field(ECOR, ByteAcc, Lock, Preserve) {
// Field definitions go here
}
}
12.12 Deﬁning an EC SMBus Host Controller in ACPI Namespace
An EC-SMB-HC device is deﬁned using the named device object. The EC-SMB- HC’s device object requires the
following elements:
Table 12.21: EC SMBus HC Device Objects
_HID Named object that provides the EC-SMB- HC’s Plug and Play identiﬁer. This value is be set to
ACPI0001. _HID is a standard device conﬁguration control method deﬁned in _HID (Hardware
ID).
_EC Named object that evaluates to a WORD that deﬁnes the SMBus attributes needed by the SMBus
driver. _EC is the Embedded Controller Offset Query Control Method. The most signiﬁcant byte
is the address offset in embedded controller space of the SMBus controller; the least signiﬁcant
byte is the query value for all SMBus events.
12.12. Deﬁning an EC SMBus Host Controller in ACPI Namespace 723Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
12.12.1 Example: EC SMBus Host Controller ASL-Code
Example ASL code that deﬁnes an SMB-HC from within an embedded controller device is shown below:
{
{
IO(Decode16, 0x62, 0x62, 0, 1), // Status port
IO(Decode16, 0x66, 0x66, 0, 1) // command port
})
Name(_GPE, 0)
Device (SMB0)
{
Name(_HID, "ACPI0001") // EC-SMB-HC
Name(_UID, 0) // Unique device identifier
Name(_EC, 0x2030) // EC offset 0x20, query bit 0x30
:
}
Device (SMB1)
{
Name(_UID, 1) // Unique device identifier
Name(_EC, 0x8031) // EC offset 0x80, query bit 0x31
:
}
} // end of EC0.
12.12. Deﬁning an EC SMBus Host Controller in ACPI Namespace 724CHAPTER
THIRTEEN
ACPI SYSTEM MANAGEMENT BUS INTERFACE SPECIFICATION
This section describes the System Management Bus (SMBus) generic address space and the use of this address space
to access SMBus devices from AML.
Unlike other address spaces, SMBus operation regions are inherently non-linear, where each offset within an SMBus
address space represents a variable-sized (from 0 to 32 bytes) ﬁeld. Given this uniqueness, SMBus operation regions
include restrictions on their ﬁeld deﬁnitions and require the use of an SMBus-speciﬁc data buffer for all transactions.
The SMBus interface presented in this section is intended for use with any hardware implementation compatible
with the SMBus speciﬁcation. SMBus hardware is broadly classiﬁed as either non-EC-based or EC-based. EC-
based SMBus implementations comply with the standard register set deﬁned in ACPI Embedded Controller Interface
Non-EC SMBus implementations can employ any hardware interface and are typically used for their cost savings
when SMBus security is not required. Non-EC-based SMBus implementations require the development of hardware
speciﬁc drivers for each OS implementation. See Declaring SMBus Host Controller Objects for more information.
Support of the SMBus generic address space by ACPI-compatible operating systems is optional. As such, the Smart
Battery System Implementer’s Forum (SBS-IF) has deﬁned an SMBus interface based on a standard set of control
methods. This interface is documented in the SMBus Control Method Interface Speciﬁcation at http://smbus.org/specs/
(or see http://ueﬁ.org/acpi under the heading “Smart Battery System Components and SMBus Speciﬁcation”).
13.1 SMBus Overview
SMBus is a two-wire interface based upon the I2C protocol. The SMBus is a low-speed bus that provides positive ad-
dressing for devices, as well as bus arbitration. For more information, refer to the complete set of SMBus speciﬁcations
published by the SBS-IF.
13.1.1 SMBus Slave Addresses
Slave addresses are speciﬁed using a 7-bit non-shifted notation. For example, the slave address of the Smart Battery
Selector device would be speciﬁed as 0x0A (1010b), not 0x14 (10100b) as might be found in other documents. These
two different forms of addresses result from the format in which addresses are transmitted on the SMBus.
During transmission over the physical SMBus, the slave address is formatted in an 8-bit block with bits 7-1 containing
the address and bit 0 containing the read/write bit. ASL code, on the other hand, presents the slave address simply
as a 7-bit value making it the responsibility of the OS (driver) to shift the value if needed. For example, the ASL
value would have to be shifted left 1 bit before being written to the SMB_ADDR register in the EC based SMBus as
described in Address Register, SMB_ADDR .
725Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
13.1.2 SMBus Protocols
There are seven possible command protocols for any given SMBus slave device, and a device may use any or all of
the protocols to communicate. The protocols and associated access type indicators are listed below. Notice that the
protocols values are similar to those deﬁned for the EC-based SMBus in Protocol Register, SMB_PRTCL except that
protocol pairs (for example, Read Byte, Write Byte) have been joined.
Table 13.1: SMBus Protocol Types
Value Type Description
0x02 SMBQuick SMBus Read/Write Quick Protocol
0x04 SMBSendReceive SMBus Send/Receive Byte Protocol
0x06 SMBByte SMBus Read/Write Byte Protocol
0x08 SMBWord SMBus Read/Write Word Protocol
0x0A SMBBlock SMBus Read/Write Block Protocol

0x0C SMBProcessCall SMBus Process Call Protocol
0x0D SMBBlockProcessCall SMBus Write Block-Read Block Process Call Protocol
Notice that bit 7 of the protocol value is used by this interface to indicate to the SMB-HC whether or not packet error
checking (PEC) should be employed for a transaction. Packet error checking is described in section 7.4 of the System
Management Bus Speciﬁcation, Version 1.1. This highly desirable capability improves the reliability and robustness
of SMBus communications.
The bit encoding of the protocol value is shown below. For example, the value 0x86 would be used to specify the PEC
version of the SMBus Read/Write Byte protocol.
Fig. 13.1: Bit Encoding Example
Notice that bit 0 of the protocol value is always zero (even number hexadecimal values). In a manner similar to the
slave address, software that implements the SMBus interface is responsible for setting this bit to indicate whether the
transaction is a read (for example, Read Byte) or write (for example, Write Byte) operation.
For example, software implanting this interface for EC-SMBus segments would set bit 0 for read transactions. For the
SMBByte protocol (0x06), this would result in the value 0x07 being placed into the SMB_PRTCL register (or 0x87 if
PEC is requested) for write transactions.
13.1.3 SMBus Status Codes
The use of status codes helps AML determine whether an SMBus transaction was successful. In general, a status code
of zero indicates success, while a non-zero value indicates failure. The SMBus interface uses the same status codes
deﬁned for the EC-SMBus (see Status Register, SMB_STS ).
13.1. SMBus Overview 726Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
13.1.4 SMBus Command Values
SMBus devices may optionally support up to 256 device-speciﬁc commands. For these devices, each command value
supported by the device is modeled by this interface as a separate virtual register. Protocols that do not transmit a
command value (for example, Read/Write Quick and Send/Receive Byte) are modeled using a single virtual register
(with a command value = 0x00).
13.2 Accessing the SMBus from ASL Code
The following sections demonstrate how to access and use the SMBus from ASL code.
13.2.1 Declaring SMBus Host Controller Objects
EC-based SMBus 1.0-compatible HCs should be modeled in the ACPI namespace as described in Deﬁning an Em-
bedded Controller Device in ACPI Namespace , “Deﬁning an Embedded Controller SMBus Host Controller in ACPI
Namespace.” An example deﬁnition is given below. Using the HID value “ACPI0001” identiﬁes that this SMB-HC
is implemented on an embedded controller using the standard SMBus register set deﬁned in SMBus Host Controller
Interface via Embedded Controller .
{
Name(_HID, "ACPI0001") // EC-based SMBus 1.0 compatible Host Controller
:
}
EC-based SMBus 2.0-compatible host controllers should be deﬁned similarly in the namespace as follows:
{
Name(_HID, "ACPI0005") // EC-based SMBus 2.0 compatible Host Controller
:
}
Non-EC-based SMB-HCs should be modeled in a manner similar to the EC-based SMBus HC. An example deﬁnition
is given below. These devices use a vendor-speciﬁc hardware identiﬁer (HID) to specify the type of SMB-HC (do not
use “ACPI0001” or “ACPI0005”). Using a vendor-speciﬁc HID allows the correct software to be loaded to service this
segment’s SMBus address space.
Device(SMB0)
{
Name(_HID, "<vendor-specific hid>") // Vendor-Specific HID
:
}
Regardless of the type of hardware, some OS software element (for example, the SMBus HC driver) must register
with OSPM to support all SMBus operation regions deﬁned for the segment. This software allows the generic SMBus
interface deﬁned in this section to be used on a speciﬁc hardware implementation by translating between the conceptual
(for example, SMBus address space) and physical (for example, process of writing/reading registers) models. Because
of this linkage, SMBus operation regions must be deﬁned immediately within the scope of the corresponding SMBus
device.
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13.2.2 Declaring SMBus Devices
The SMBus, as deﬁned by the SMBus Speciﬁcations <http://smbus.org/specs/> , is not an enumerable bus. As a result,
an SMBus 1.0-compatible SMB-HC driver cannot discover child devices on the SMBus and load the appropriate
corresponding device drivers. As such, SMBus 1.0-compatible devices are declared in the ACPI namespace, in like
manner to other motherboard devices, and enumerated by OSPM.
The SMBus 2.0 speciﬁcation adds mechanisms enabling device enumeration on the bus while providing compatibil-
ity with existing devices. ACPI deﬁnes and associates the “ACPI0005” HID value with an EC-based SMBus 2.0-
compatible host controller. OSPM will enumerate SMBus 1.0-compatible devices when declared in the namespace
under an SMBus 2.0-compatible host controller.
The responsibility for the deﬁnition of ACPI namespace objects, required by an SMBus 2.0-compatible host controller
driver to enumerate non-bus-enumerable devices, is relegated to the Smart Battery System Implementers Forum. See
the SMBus Speciﬁcations at the link mentioned above.
Starting in ACPI 2.0, _ADR is used to associate SMBus devices with their lowest SMBus slave address.
13.2.3 Declaring SMBus Operation Regions
Each SMBus operation region deﬁnition identiﬁes a single SMBus slave address. Operation regions are deﬁned only
for those SMBus devices that need to be accessed from AML. As with other regions, SMBus operation regions are
only accessible via the Field term (see Declaring SMBus Devices ).
This interface models each SMBus device as having a 256-byte linear address range. Each byte offset within this
range corresponds to a single command value (for example, byte offset 0x12 equates to command value 0x12), with
a maximum of 256 command values. By doing this, SMBus address spaces appear linear and can be processed in a
The syntax for the OperationRegion term (from OperationRegion (Declare Operation Region) ) is described below.
)
Where:
•RegionName speciﬁes a name for this slave device (for example, “SBD0”).
•RegionSpace must be set to SMBus (operation region type value 0x04).
•Offset is a word-sized value specifying the slave address and initial command value offset for the target device.
The slave address is stored in the high byte and the command value offset is stored in the low byte. For example,
the value 0x4200 would be used for an SMBus device residing at slave address 0x42 with an initial command
value offset of zero (0).
•Length is set to the 0x100 (256), representing the maximum number of possible command values, for regions
non-zero offsets. For example, a region with an Offset value of 0x4210 would have a corresponding Length of
For example, the Smart Battery Subsystem (illustrated below) consists of the Smart Battery Charger at slave address
0x09, the Smart Battery System Manager at slave address 0x0A, and one or more batteries (multiplexed) at slave
address 0x0B. (Notice that Figure 13-2 represents the logical connection of a Smart Battery Subsystem. The actual
physical connections of the Smart Battery(s) and the Smart Battery Charger are made through the Smart Battery
13.2. Accessing the SMBus from ASL Code 728Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
System Manager.) All devices support the Read/Write Word protocol. Batteries also support the Read/Write Block
protocol.
Fig. 13.2: Smart Battery Subsystem Devices
The following ASL code shows the use of the OperationRegion term to describe these SMBus devices:
{
Name(_HID, "ACPI0001") // EC-SMBus Host Controller
OperationRegion(SBC0, SMBus, 0x0900, 0x100) // Smart Battery Charger
OperationRegion(SBS0, SMBus, 0x0A00, 0x100) // Smart Battery Selector
OperationRegion(SBD0, SMBus, 0x0B00, 0x100) // Smart Battery Device(s)
:
}
Notice that these operation regions in this example are deﬁned within the immediate context of the ‘owning’ EC-
SMBus device. Each deﬁnition corresponds to a separate slave address (device), and happens to use an initial command
13.2.4 Declaring SMBus Fields
As with other regions, SMBus operation regions are only accessible via the Field term. Each ﬁeld element is assigned
a unique command value and represents a virtual register on the targeted SMBus device.

protocol.
{
:
}
The syntax for the Field term (from Event (Declare Event Synchronization Object) ) is described below.
Field(
UpdateRule // UpdateRuleKeyword - *ignored*
Where:
•RegionName speciﬁes the operation region name previously deﬁned for the device.
•AccessType must be set to BufferAcc . This indicates that access to ﬁeld elements will be done using a region-
be of any size. When a ﬁeld of this type is used as the source argument in an operation it simply evaluates to a
buffer. When used as the destination, however, the buffer is passed bi-directionally to allow data to be returned
13.2. Accessing the SMBus from ASL Code 729Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
from write operations. The modiﬁed buffer then becomes the execution result of that operation. This is slightly
different than the normal case in which the execution result is the same as the value written to the destination.
Note that the source is never changed, since it could be a read only object (see Declaring and Using an SMBus
Data Buffer andASL Opcode Terms ).
•LockRule indicates if access to this operation region requires acquisition of the Global Lock for synchronization.
This ﬁeld should be set to Lock on system with ﬁrmware that may access the SMBus, and NoLock otherwise.
•UpdateRule is not applicable to SMBus operation regions since each virtual register is accessed in its entirety.
This ﬁeld is ignored for all SMBus ﬁeld deﬁnitions.
SMBus operation regions require that all ﬁeld elements be declared at command value granularity. This means that
each virtual register cannot be broken down to its individual bits within the ﬁeld deﬁnition.
both to simplify the SMBus interface and to maintain consistency with the physical model deﬁned by the SMBus
SMBus protocols are assigned to ﬁeld elements using the AccessAs term within the ﬁeld deﬁnition. The syntax for
this term (from ASL Root and Secondary Terms ) is described below.
AccessAs(
)
Where:
•AccessType must be set to BufferAcc .
•AccessAttribute indicates the SMBus protocol to assign to command values that follow this term. See SMBus
Protocols for a listing of the SMBus protocol types and values.
An AccessAs term must appear as the ﬁrst entry in a ﬁeld deﬁnition to set the initial SMBus protocol for the ﬁeld
elements that follow. A maximum of one SMBus protocol may be deﬁned for each ﬁeld element. Devices supporting
For example, the register at command value 0x08 for a Smart Battery device (illustrated below) represents a word
value specifying the battery temperature (in degrees Kelvin), while the register at command value 0x20 represents a
variable-length (0 to 32 bytes) character string specifying the name of the company that manufactured the battery.
The following ASL code shows the use of the OperationRegion, Field, AccessAs, and Offset terms to represent these
Smart Battery device virtual registers:
OperationRegion(SBD0, SMBus, 0x0B00, 0x0100)
Field(SBD0, BufferAcc, NoLock, Preserve)
{
AccessAs(BufferAcc, SMBWord) // Use the SMBWord protocol for the following...
MFGA, 8, // ManufacturerAccess() [command value 0x00]
RCAP, 8, // RemainingCapacityAlarm() [command value 0x01]
Offset(0x08) // Skip to command value 0x08...
BTMP, 8, // Temperature() [command value 0x08]
Offset(0x20) // Skip to command value 0x20...
AccessAs(BufferAcc, SMBBlock) // Use the SMBBlock protocol for the following...
MFGN, 8, // ManufacturerName() [command value 0x20]
DEVN, 8 // DeviceName() [command value 0x21]
}
Notice that command values are equivalent to the ﬁeld element’s byte offset (for example, MFGA=0, RCAP=1,
BTMP=8). The AccessAs term indicates which SMBus protocol to use for each command value.
13.2. Accessing the SMBus from ASL Code 730Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 13.3: Smart Battery Device Virtual Registers
13.2.5 Declaring and Using an SMBus Data Buffer
The use of a data buffer for SMBus transactions allows AML to receive status and data length values, as well as making
it possible to implement the Process Call protocol. As previously mentioned, the BufferAcc access type is used to
indicate to the ﬁeld handler that a region-speciﬁc data buffer will be used.
For SMBus operation regions, this data buffer is deﬁned as a ﬁxed-length 34-byte buffer that, if represented using a
‘C’-styled declaration, would be modeled as follows:
{
BYTE[32] Data; // Bytes 2 through 33 of the data buffer
}
Where:
•Status (byte 0) indicates the status code of a given SMBus transaction. See SMBus Status Codes for more
•Length (byte 1) speciﬁes the number of bytes of valid data that exists in the data buffer. Use of this ﬁeld
is only deﬁned for the Read/Write Block protocol, where valid Length values are 0 through 32. For other
protocols–where the data length is implied by the protocol–this ﬁeld is reserved.
•Data (bytes 33-2) represents a 32-byte buffer, and is the location where actual data is stored.
For example, the following ASL shows the use of the SMBus data buffer for performing transactions to a Smart Battery
device. This code is based on the example ASL presented in Declaring SMBus Fields which lists the operation region
and ﬁeld deﬁnitions for the Smart Battery device.
/*Create the SMBus data buffer */
Name(BUFF, Buffer(34){}) // Create SMBus data buffer as BUFF
13.2. Accessing the SMBus from ASL Code 731Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
CreateByteField(BUFF, 0x00, OB1) // OB1 = Status (Byte)
CreateByteField(BUFF, 0x01, OB2) // OB2 = Length (Byte)
CreateWordField(BUFF, 0x02, OB3) // OB3 = Data (Word - Bytes 2 & 3)
CreateField(BUFF, 0x10, 256, OB4) // OB4 = Data (Block - Bytes 2-33)
Store(BTMP, BUFF) // Invoke Read Word transaction
If(LEqual(OB1, 0x00)) // Successful?
{
// OB3 = Battery temperature in 1/10th degrees
˓→Kelvin
}
Store(MFGN, BUFF) // Invoke Read Block transaction
{
// OB2 = Length of the manufacturer name
// OB4 = Manufacturer name (as a counted string)
}
Notice the use of the CreateField primitives to access the data buffer’s sub-elements ( Status ,Length , and Data ), where
Data (bytes 33-2) is ‘typecast’ as both word (OB3) and block (OB4) data.
as shown below.
Store(Store(BUFF, MFGN), BUFF) // Invoke Write Block transaction
If(LEqual(OB1, 0x00)) {...} // Transaction successful?
BufferAcc’s bi-directionality described in Declaring SMBus Fields . It should be noted that storing (or parsing) the
result of an SMBus Write transaction is not required although useful for ascertaining the outcome of a transaction.
SMBus Process Call protocols require similar semantics due to the fact that only destination operands are passed
bi-directionally. These transactions require the use of the double-Store() semantics to properly capture the return
results.
13.2. Accessing the SMBus from ASL Code 732Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
13.3 Using the SMBus Protocols
This section provides information and examples on how each of the SMBus protocols can be used to access SMBus
devices from AML.
13.3.1 Read/Write Quick (SMBQuick)
The SMBus Read/Write Quick protocol (SMBQuick) is typically used to control simple devices using a device-speciﬁc
binary command (for example, ON and OFF). Command values are not used by this protocol and thus only a single
element (at offset 0) can be speciﬁed in the ﬁeld deﬁnition. This protocol transfers no data.

results.
OperationRegion(SMBD, SMBus, 0x4200, 0x100) // SMBus device at slave address 0x42
Field(SMBD, BufferAcc, NoLock, Preserve)
{
AccessAs(BufferAcc, SMBQuick) // Use the SMBus Read/Write Quick protocol
}
Store(FLD0, BUFF) // Invoke Read Quick transaction
If(LEqual(OB1, 0x00)) {...} // Successful?
Store(BUFF, FLD0) // Invoke Write Quick transaction
In this example, a single ﬁeld element (FLD0) at offset 0 is deﬁned to represent the protocol’s read/write bit. Access to
FLD0 will cause an SMBus transaction to occur to the device. Reading the ﬁeld results in a Read Quick, and writing
to the ﬁeld results in a Write Quick. In either case data is not transferred–access to the register is simply used as a
mechanism to invoke the transaction.
13.3.2 Send/Receive Byte (SMBSendReceive)
The SMBus Send/Receive Byte protocol (SMBSendReceive) transfers a single byte of data. Like Read/Write Quick,
command values are not used by this protocol and thus only a single element (at offset 0) can be speciﬁed in the ﬁeld
{
AccessAs(BufferAcc, SMBSendReceive) // Use the SMBus Send/Receive Byte protocol
}
// Create the SMBus data buffer
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CreateByteField(BUFF, 0x02, DATA) // DATA = Data (Byte)
Store(FLD0, BUFF) // Invoke a Receive Byte transaction
If(LEqual(STAT, 0x00)) // Successful?
{
}
Store(0x16, DATA) // Save 0x16 into the data buffer
Store(BUFF, FLD0) // Invoke a Send Byte transaction
FLD0 will cause an SMBus transaction to occur to the device. Reading the ﬁeld results in a Receive Byte, and writing
to the ﬁeld results in a Send Byte.
13.3.3 Read/Write Byte (SMBByte)
The SMBus Read/Write Byte protocol (SMBByte) also transfers a single byte of data. But unlike Send/Receive Byte,
this protocol uses a command value to reference up to 256 byte-sized virtual registers.
{
AccessAs(BufferAcc, SMBByte) // Use the SMBus Read/Write Byte protocol
}
Store(FLD1, BUFF) // Invoke a Read Byte transaction
{
}
Store(BUFF, FLD2) // Invoke a Write Byte transaction
mand values 0, 1, and 2. Access to any of the ﬁeld elements will cause an SMBus transaction to occur to the device.
13.3. Using the SMBus Protocols 734Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Reading FLD1 results in a Read Byte with a command value of 1, and writing to FLD2 results in a Write Byte with
command value 2.
13.3.4 Read/Write Word (SMBWord)
The SMBus Read/Write Word protocol (SMBWord) transfers 2 bytes of data. This protocol also uses a command
value to reference up to 256 word-sized virtual device registers.
{
AccessAs(BufferAcc, SMBWord) // Use the SMBus Read/Write Word protocol
}
// Read two bytes of data from the device using command value 1
Store(FLD1, BUFF) // Invoke a Read Word transaction
{
}
// Write the word '0x5416' to the device using command value 2
Store(0x5416, DATA) // Save 0x5416 into the data buffer
Store(BUFF, FLD2) // Invoke a Write Word transaction
Reading FLD1 results in a Read Word with a command value of 1, and writing to FLD2 results in a Write Word with
13.3.5 Read/Write Block (SMBBlock)
The SMBus Read/Write Block protocol (SMBBlock) transfers variable-sized (0-32 bytes) data. This protocol uses a
{
AccessAs(BufferAcc, SMBBlock) // Use the SMBus Read/Write Block protocol
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}
CreateByteField(BUFF, 0x01, SIZE) // SIZE = Length (Byte)
CreateField(BUFF, 0x10, 256, DATA) // DATA = Data (Block)
// Read block data from the device using command value 1
Store(FLD1, BUFF) // Invoke a Read Block transaction
{
// SIZE = Size (number of bytes)
// of the block data read from FLD1...
// DATA = Block data read from FLD1...
}
// Write the block 'TEST' to the device using command value 2
Store("TEST", DATA) // Save "TEST" into the data buffer
Store(4, SIZE) // Length of valid data in the data buffer
Reading FLD1 results in a Read Block with a command value of 1, and writing to FLD2 results in a Write Block with
13.3.6 Word Process Call (SMBProcessCall)
The SMBus Process Call protocol (SMBProcessCall) transfers 2 bytes of data bi-directionally (performs a Write Word
followed by a Read Word as an atomic transaction). This protocol uses a command value to reference up to 256 word-
sized virtual registers.
{
AccessAs(BufferAcc, SMBProcessCall) // Use the SMBus Process Call protocol
}

{
}
// Process Call with input value '0x5416' to the device using command value 1
Store(Store(BUFF, FLD1), BUFF) // Invoke a Process Call transaction
13.3. Using the SMBus Protocols 736Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
{
}
Reading or writing FLD1 results in a Process Call with a command value of 1. Notice that unlike other protocols, Pro-
cess Call involves both a write and read operation in a single atomic transaction. This means that the Data element of
the SMBus data buffer is set with an input value before the transaction is invoked, and holds the output value following
the successful completion of the transaction.
13.3.7 Block Process Call (SMBBlockProcessCall)
The SMBus Block Write-Read Block Process Call protocol (SMBBlockProcessCall) transfers a block of data bi-
directionally (performs a Write Block followed by a Read Block as an atomic transaction). The maximum aggregate
amount of data that may be transferred is limited to 32 bytes. This protocol uses a command value to reference up to
256 block-sized virtual registers.
OperationRegion(SMBD, SMBus, 0x4200, 0x100) // SMbus device at slave address 0x42
{
AccessAs(BufferAcc, SMBBlockProcessCall) // Use the Block Process Call protocol
}
// Create the SMBus data buffer as BUFF
Name(BUFF, Buffer(34)()) // Create SMBus data buffer as BUFF
CreateField(BUFF, 0x10, 256, DATA) // Data (Block)
// Process Call with input value "ACPI" to the device using command value 1
Store("ACPI", DATA) // Fill in outgoing data
Store(8, SIZE) // Length of the valid data
Store(Store(BUFF, FLD1), BUFF) // Execute the PC
if (LEqual(STAT, 0x00)) // Test the status
{
// BUFF now contains information returned
// from PC
// SIZE now equals size of data returned
}
13.3. Using the SMBus Protocols 737CHAPTER
FOURTEEN
PLATFORM COMMUNICATIONS CHANNEL (PCC)
The platform communication channel (PCC) is a generic mechanism for OSPM to communicate with an entity in
the platform (e.g. a platform controller, or a Baseboard Management Controller (BMC)). Neither the entity that
OSPM communicates with, nor any aspects of the information passed back and forth is deﬁned in this section. That
information is deﬁned by the actual interface that that employs PCC register address space as the communication
channel.
PCC deﬁnes a new address space type (PCC Space, 0xA), which is implemented as one or more independent commu-
nications channels, or subspaces.
This chapter is arranged as follows:
• The Platform Communications Channel Table andGeneric Communications Channel Shared Memory Region
provide reference information about the PCCT, and expected data structures used for the Platform Communica-
tions Channel.
•Doorbell Protocol ,Platform Notiﬁcation , and Referencing the PCC address space describe how communica-
tions takes place between the OSPM and the platform over PCC.
The PCC interface is described in the following ACPI system description table.
14.1 Platform Communications Channel Table
Table 14.1: Platform Communications Channel Table (PCCT)
Field Byte
Header
Signature 4 0 ‘PCCT’ Signature for the Platform Communications Channel Table.
Length 4 4 Length, in bytes, of the entire PCCT.
OEM Table
ID8 16 For the PCCT, the table ID is the manufacturer model ID.
OEM Revi-
sion4 24 OEM revision of PCCT for supplied OEM Table ID.
Creator ID 4 28 Vendor ID of utility that created the table. For tables containing Deﬁnition
Blocks, this is the ID for the ASL Compiler.
sion4 32 Revision of utility that created the table. For tables containing Deﬁnition
Blocks, this is the revision for the ASL Compiler.
738Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 14.1 – continued from previous page
Flags 4 36 Platform Communications Channel Global ﬂags, described in Platform
Communications Channel Global Flags .
PCC Sub-
space Struc-
ture[n] (n =
subspace ID)– 48 A list of Platform Communications Channel Subspace structures for this
platform. This structure is described in the following section. At most
256 subspaces are supported.
14.1.1 Platform Communications Channel Global Flags
Table 14.2: Platform Communications Channel Global Flags
PCC Global Flags Bit
Platform Interrupt 1 0 If set, the platform is capable of generating an interrupt
to indicate completion of a command.
14.1.2 Platform Communications Channel Subspace Structures
PCC Subspaces are described by the PCC Subspace structure in the PCCT table. The subspace ID of a PCC subspace is
its index in the array of subspace structures, starting with subspace 0. All subspaces have a common header, followed
by a set of type-speciﬁc ﬁelds:
Table 14.3: Generic PCC Subspace Structure
Field Byte
Type 1 0 The type of subspace.
Length 1 1 Length of the subspace structure, in bytes. The next subspace structure
begins length bytes after the start of this one.
Type speciﬁc
ﬁeldsvariable 2 See speciﬁc subspace types for more details
This speciﬁcation deﬁnes the following subspaces:
• Type 0, the Generic Communications Subspace,
• Types 1 to 2, HW-Reduced Communications Subspaces,
• Types 3 and 4 are extended PCC subspaces.
• Type 5 is the Hardware Register-Based PCC Subspace.
All other subspace types are reserved.
14.1. Platform Communications Channel Table 739Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
14.1.3 Generic Communications Subspace Structure (type 0)
Table 14.4: PCC Subspace Structure type 0 (Generic Communica-
tions Subspace)
Field Byte
Type 1 0 0 (Generic Communications Subspace)
Length 1 1 62
Reserved 6 2 Reserved
Base Address 8 8 Base Address of the shared memory range, described in Generic Commu-
nications Channel Shared Memory Region .
Memory
Length8 16 Length of the memory range. Must be > 8.
Doorbell Reg-
ister12 24 Contains the processor relative address, represented in Generic Address
Structure format, of the PCC doorbell. Note: Only System I/O space and
System Memory space are valid for values for Address_Space_I D.
Doorbell Pre-
serve8 36 Contains a mask of bits to preserve when writing the doorbell register.
Doorbell
Write8 44 Contains a mask of bits to set when writing the doorbell register.
Nominal
Latency4 52 Expected latency to process a command, in microseconds.
Maximum Pe-
riodic Access
Rate4 56 The maximum number of periodic requests that the subspace channel can
support, reported in commands per minute. 0 indicates no limitation.
Minimum
Request
Turnaround
Time2 60 The minimum amount of time that OSPM must wait after the completion
of a command before issuing the next command, in microseconds.
Note: Inaccurate values for the Maximum Periodic Access Rate and Minimum Request Turnaround Time ﬁelds can
result in punitive side effects for features that rely on the PCC interface. The Platform should report accurate values
that allow for maximum channel efﬁciency while maintaining maximum channel stability.
The Maximum Periodic Access Rate is used by OSPM to determine the maximum rate for periodic evaluation of
commands. Infrequent, event driven commands are not restricted by the maximum periodic access rate.
14.1.4 HW-Reduced Communications Subspace Structure (type 1)
The HW-Reduced Communications Subspace is deﬁned in Table 14.5. It is intended for use on HW-Reduced ACPI
Platforms, which do not support the SCI. Aside from the interrupt change, and the allowed use of the Functional Fixed
HW address space for the Doorbell Register, this subspace is identical to the Generic Communications Subspace
described in Section 14.2 and Section 14.5.
Table 14.5: PCC Subspace Structure type 1 (HW-Reduced Commu-
nications Subspace)
Field Byte
14.1. Platform Communications Channel Table 740Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5

Field Byte
Table 14.5 – continued from previous page
Type 1 0 1 (HW-Reduced Communications Subspace)
Platform
Interrupt4 2 GSIV of the interrupt used for the PCC platform interrupt for this Sub-
space.
Platform
Interrupt
Flags1 6
Bit [2-7] Reserved
Bit [1] Platform interrupt mode 1: Interrupt is Edge triggered 0: Interrupt
is Level triggered
Bit [0] Platform interrupt polarity 1: Interrupt is Active low 0: Interrupt
is Active high
Reserved 1 7 Reserved
Memory
Structure format, of the PCC doorbell. Note: Only the System I/O, Sys-
tem Memory, and Functional Fixed Hardware spaces are valid for values
for Address_Space_I D.
Doorbell
Nominal
Minimum
Request
Type 1 subspaces do not support a level triggered platform interrupt as no method is provided to clear the interrupt.
Where level interrupts are required, type 2 or type 3 subspaces should be used.
14.1. Platform Communications Channel Table 741Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
14.1.5 HW-Reduced Communications Subspace Structure (type 2)
The HW-Reduced Communications Subspace is deﬁned below in Table 14.6. This is intended for use on HW-Reduced
ACPI Platforms, which require read-modify-write sequence to acknowledge Platform Interrupt. Aside from three
Platform Ack ﬁelds at the bottom of the table, this subspace is identical to HW-Reduced Communications Subspace
Structure (type 1) described above.
Table 14.6: PCC Subspace Structure type 2 (HW-Reduced Commu-
Field Byte
Type 1 0 2 (HW-Reduced Communications Subspace)
Length 1 1 90
Platform
space.
Platform
Interrupt
Flags1 6
Memory
Doorbell
Nominal
Minimum
Request
Platform In-
terrupt Ack
Register12 62 Contains the processor relative address, represented in Generic Address
Structure format, of the platform interrupt ack register. Note: Only the
System I/O, System Memory, and Functional Fixed Hardware spaces are
valid for values for Address_Space_I D.
Preserve8 74 Contains a mask of bits to preserve when writing the platform interrupt
ack register.
14.1. Platform Communications Channel Table 742Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Write8 82 Contains a mask of bits to set when writing the platform interrupt ack
register.
14.1.6 Extended PCC subspaces (types 3 and 4)
Extended PCC communication subspaces are of two types:
Type 3 Initiator subspace: used by the OSPM to communicate with the platform.
Type 4 Responder subspace: Used by the platform to send asynchronous notiﬁcations to the OSPM.
Initiator subspaces are not substantially different to type 0,1, or 2 subspaces, the most notable difference is that a
type 3 Initiator subspace does not support asynchronous notiﬁcations. Responder subspaces, type 4, provide those
notiﬁcations, and cannot be used by the OSPM to send messages to the platform. Together an Initiator and Responder
pair create a bidirectional interface between the OSPM and the platform.
The format for PCCT entries describing Initiator (type 3), and Responder (type 4) subspaces is shown in the following
table.
Table 14.7: PCC Subspace Structure type 3 and type 4
Field Byte
Type 1 0 3 - Initiator subspace 4 - Responder subspace
Length 1 1 164
Platform
Interrupt4 2 GSIV of an interrupt triggered by the platform: For Initiator subspaces
(type 3) this is raised when a command is completed on this subspace.
For Responder subspaces (type 4) this is raised when platform sends a
notiﬁcation. For a Initiator subspace, this ﬁeld is ignored if the platform
interrupt ﬂag in Table 14.2 is set to zero. If a Responder-subspace is
present in the PCCT, then the platform interrupt ﬂag must be set to 1.
Note that if interrupts are edge triggered, then each subspace must have
its own unique interrupt. If interrupts are level, a GSIV may be shared
by multiple subspaces, but each one must have unique Platform interrupt
Ack preserve and Ack Set masks.
Platform
Interrupt
Flags1 6
Bit 7:2 Reserved
Bit 1: Platform interrupt mode - Set to 1 if interrupt is Edge triggered -
Set to 0 if interrupt Level triggered
Bit 0: Platform interrupt polarity - Set to 1 if interrupt is Active low - Set
to 0 if interrupt is Active high
Reserved 1 7 Reserved must be zero
14.1. Platform Communications Channel Table 743Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 14.7 – continued from previous page
Base Address 8 8 Base Address of the shared memory range, described in the Initiator Re-
sponder Communications Channel Shared Memory Region .
Memory
Length4 16 Length of the memory range. Must be >= 16.
ister12 20 Contains the processor relative address, represented in Generic Address
Structure (GAS) format, of the PCC doorbell. Note: Only the System I/O,
System Memory, and Functional Fixed Hardware spaces are valid values
for Address_Space_I D For Responder subspaces this ﬁeld is optional, if
not present the ﬁeld should just contain zeros.
serve8 32 Contains a mask of bits to preserve when writing the doorbell register.
Doorbell
Write8 40 Contains a mask of bits to set when writing the doorbell register.
Nominal
Latency4 48 Expected latency to process a command, in microseconds. This ﬁeld is
only relevant for Initiator subspaces.
Rate4 52 The maximum number of periodic requests that the subspace subspace
can support, reported in commands per minute. 0 indicates no limitation.
This ﬁeld is only relevant for Initiator subspaces.
Minimum
Request
Time4 56 The minimum amount of time that OSPM must wait after the completion

Doorbell
Nominal
Minimum
Request
of a command before issuing the next command, in microseconds. This
ﬁeld is only relevant for Initiator subspaces.
Platform in-
Register12 60 Contains the processor relative address, represented in Generic Address
Structure (GAS) format, of the platform interrupt acknowledge register.
Note: Only the System I/O, System Memory, and Functional Fixed Hard-
ware spaces are valid for values for Address_Space_I D. If the subspace
does not support interrupts or the interrupt is edge driven the register may
be omitted. A value of 0x0 on all 12 bytes of the GAS structure indicates
the register is not present. If the subspace does support interrupts, and
these are level, this register must be supplied. And is used to clear the
interrupt by using a read, modify, write sequence.
Preserve8 72 Contains a mask of bits to preserve when writing the platform interrupt
Set8 80 Contains a mask of bits to set when writing the platform interrupt ack
register.
Reserved 8 88 Reserved must be zero
Command
complete
check register
address12 96 Contains the processor relative address, represented in Generic Address
Structure (GAS) format, of the Command complete check register. Note:
Only the System I/O, System Memory, and Functional Fixed Hardware
spaces are valid for values for Address_Space_I D
Command
complete
check mask8 108 Mask to determine whether a command is complete, using the command
complete check register. A command is complete if the value of the regis-
ter when combined through a logical AND with this mask, yields a non-
zero value
Command
complete up-
date register
address12 116 Contains the processor relative address, represented in Generic Address
Structure (GAS) format, of the command complete update register. Note:
14.1. Platform Communications Channel Table 744Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Command
date preserve
mask8 128 Mask of bits to preserve in the command complete update register, when
updating command complete in this subspace.
Command
complete
update set
mask8 136 Mask of bits to set in the command complete update register, when updat-
ing command complete in this subspace. For Initiator subspaces the mask
must indicate how to clear the command complete bit. For Responder
subspaces, the mask must indicate how to set the command complete bit.
Error status
register12 144 Contains the processor relative address, represented in Generic Address
Structure (GAS) format, of the Error status register. This ﬁeld is ignored
by the OSPM on Responder channels Note: Only the System I/O, System
Memory, and Functional Fixed Hardware spaces are valid for values for
Address_Space_I D Note: this register can be the same as the command
complete check register.
mask8 156 The mask contained here can be combined through a logical AND with
content of the Error status register to ascertain whether an error occurred
in the transmission of the command through the subspace. The logical
NOT of this mask is be used to clear the error. The inverted mask is com-
bined through a logical AND with the content of the Error status register,
and the result is written back into said register. This ﬁeld is ignored for
Responder channels.
Responder subspaces may be used by the platform to send asynchronous notiﬁcations to the OSPM. Responder sub-
space entries in the PCCT share the same format as Initiator subspaces, with the following modiﬁcations:
• Type is set to 4 - Responder subspace
• The doorbell may be zero and if so must be ignored by the OSM. If present, the platform can request that the
OSPM writes to the doorbell after it has processed a notiﬁcation.
A Responder subspace is associated with an Initiator, that is both an Initiator/Responder pair will connect the OSPM
to the same processing entity in the platform.
If a Responder subspace is included in the PCCT, then the global Plaform Interrupt ﬂag (see Table 14.2) must be set
to 1.
14.1.7 HW Registers based Communications Subspace Structure (Type 5)
Table 14.8: HW Registers based Communications Subspace Struc-
ture (Type 5)
Field Length
(in
bytes)Offset Value
Type 1 0 5
Length 1 1 Length (includes vendor deﬁned area)
Version 2 2 0x0001 (Version 1 of this PCC deﬁnition)
14.1. Platform Communications Channel Table 745Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 14.8 – continued from previous page
Base Address 8 4 Base Address of the shared memory range, described in Section
14.4
Shared Memory
Range Length8 12 Length of the shared memory range described in Table 14.14. If this
length is zero then based address is ignored.
Doorbell Register 12 20 Contains the processor relative address, represented in Generic Ad-
dress Structure format, of the PCC doorbell. Note: Only System
I/O space and System Memory space are valid for values for Ad-
Doorbell Preserve 8 32 Contains a mask of bits to preserve when writing the doorbell reg-
ister
Doorbell Write 8 40 Contains a mask of bits to set when writing the doorbell register.
This is used to send speciﬁc commands to the Platform.
Command Com-
plete Check Regis-
ter12 48 Contains the processor relative address, represented in Generic Ad-
dress Structure format, of Command complete Check register. Note:
Only System I/O space and System Memory space are valid for val-
ues for Address_Space_ID.
plete Check mask8 60 Contains a mask of bits to query completion status of the previously
issued command from the Command Complete Status Register. OS
shall do an AND operation with the Command Complete Check
Register value. The OS must check the completion status before
writing to doorbell register for the next command. If calculated
value is 0 then previous operation has been completed. If comple-
tion status is not implemented then this mask should be 0. In this
case OS shall only wait for Minimum Request Turnaround Time.
Note: Command complete check needs be done before writing to
doorbell register to avoid any race condition with a previous use of
the doorbell register. In addition to that command complete check
needs to be done after writing to doorbell register and before reading
Status from Error Status Register.
Error Status Regis-
ter12 68 Contains the processor relative address, represented in Generic Ad-
dress Structure format, of Error Status register. Note: Only System
Error Status mask 8 80 Contains a mask of bits to get error status of the previous command
request from Error Status Register. OS shall do an AND operation
with Error Status register value. If this mask value is 0 then Error
Status register is ignored. Error Status needs to be checked after
completion status indicates issued command has been completed.
If Command Complete Check is not implemented (means Com-
mand Complete Check mask is 0) then wait for Minimum Request
Turnaround Time. If the calculated value is zero, then it indicates
success. Any other value indicates failure.
Nominal Latency 4 88 Expected latency to process a command, in microseconds.
Minimum Request
Turnaround Time4 92 The minimum amount of time that OSPM must wait after the com-
pletion of a command before issuing the next command, in mi-
croseconds.
14.1. Platform Communications Channel Table 746Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
14.2 Generic Communications Channel Shared Memory Region
Table 14.9: Generic Communications Channel Shared Memory Re-
gion
Field Byte
Signature 4 0 The PCC signature. The signature of a subspace is computed by a bitwise-
or of the value 0x50434300 with the subspace ID. For example, subspace
3 has the signature 0x50434303.
Command 2 4 PCC command ﬁeld, described in the Generic Communications Channel
Command Field .
Status 2 6 PCC status ﬁeld, described in the Generic Communications Channel Sta-
tus Field .
Space– 8 Memory region for reading/writing PCC data. The size of this region is 8
bytes smaller than the size of the shared memory region (speciﬁed in the
General Communications Subspace structure). The ﬁrst byte of this ﬁeld
represents PCC address 0.
14.2.1 Generic Communications Channel Command Field
For channels of type 0 to 2, this 16-bit ﬁeld is used to select one of the deﬁned commands for the platform to perform.

gion
Field Byte
tus Field .
OSPM is responsible for populating this ﬁeld before each command invocation.
Table 14.10: Generic Communications Channel Command Field
Field Bit
Command 8 0 Command code to execute. Command codes are application speciﬁc and
deﬁned by the consumer of this interface.
Reserved 7 8 Reserved.
Notify on
completion1 15 If set, the platform should generate a Doorbell interrupt at the completion
of this command. The interrupt is an SCI for a Type 0 subspace structure,
or as described by the Doorbell Interrupt ﬁeld for Type 1 and Type 2
subspace structures. If the Doorbell bit is not set in the PCC global ﬂags,
this bit must be cleared.
14.2.2 Generic Communications Channel Status Field
Table 14.11: Generic Communications Channel Status Field
Field Bit
plete1 0 If set, the platform has completed processing the last command.
Platform interrupt 1 1 If set, the platform has issued a Platform Interrupt to this subspace.
OSPM must check the Command Complete and Platform Notiﬁca-
tion ﬁelds to determine the cause of the Interrupt.
14.2. Generic Communications Channel Shared Memory Region 747Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 14.11 – continued from previous page
Platform Notiﬁca-
tion1 3 If set, indicates the platform is issuing an asynchronous notiﬁcation
to OSPM.
Note: OSPM (either in an Interrupt handler or via polling) is required to detect that the Command Complete bit has
been set and to clear it before issuing another command. While waiting for this bit to be set, OSPM must not modify
any portion of the shared memory region.
Note: The Platform Interrupt bit is required to be cleared in OSPM’s Interrupt handler so that a new event can be
detected.
14.3 Extended PCC Subspace Shared Memory Region
Table 14.12: Initiator Responder Communications Channel Shared
Memory Region
Field Byte
Flags 4 4 SeeInitiator Responder Communications Channel Flags below.
Length 4 8 Length of payload being transmitted including command ﬁeld.
Command 4 12 Command being sent over the subspace.
subspace– 16 Memory region for reading/writing PCC data. The maximum size of this
region is 16 bytes smaller than the size of the shared memory region
(speciﬁed in the Initiator Responder Communications Subspace struc-
ture). When a command is sent to or received from the platform, the
size of the data in this space will be Length (expressed above) minus the
4 bytes taken up by the command.
The 32-bit command ﬁeld is used to select one of the deﬁned commands for the platform to perform. On Initiator
subspaces the OSPM is responsible for populating this ﬁeld, alongside the command’s payload, length and ﬂags. For
Responder subspaces, the OSPM is responsible for interpreting the command and payload ﬁelds to ascertain the nature
of the notiﬁcation that was sent. The format for the ﬂags ﬁeld is shown in the table below.
Table 14.13: Initiator Responder Communications Channel Flags
Field Bit
14.3. Extended PCC Subspace Shared Memory Region 748Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 14.13 – continued from previous page
Notify on comple-
tion1 0 For Initiator subspaces this ﬁeld indicates to the platform that it must
generate an interrupt when the command has completed. - Setting
this bit to 1 when sending a command, requests that completion of
the command is signaled via the platform interrupt. - Setting it to
0 when sending a command, requests that no interrupt is asserted
when the command is completed. For Responder subspaces, if the
doorbell ﬁeld of the Responder subspace is non zero, and this ﬂag
is set, the OSPM must access the doorbell once it has processed
the notiﬁcation. This bit is ignored by the platform if the Platform
Interrupt ﬁeld of the PCC ﬂags ( Platform Communications Channel
Global Flags ) is set to zero.
Reserved 31 1
14.4 Reduced PCC Subspace Shared Memory Region
Table 14.14: Reduced PCC Subspace Shared Memory Region
Field Byte
Subspace– 4 Memory region for reading/writing PCC data. The maximum size
of this region is 4 bytes smaller than the size of the shared memory
region (speciﬁed in the Type 5 PCC Subspace structure). When a
command is sent to or received from the platform, the size of the
data in this space will be Length (expressed above) minus the 4
bytes taken up by the Signature.
14.5 Doorbell Protocol
Other than on Responder subspaces, the doorbell is used by OSPM to notify the platform that the shared memory
region contains a valid command that is ready to be processed. A doorbell consists of a hardware register that is
accessed via I/O or memory mapped I/O, abstracted in the doorbell ﬁeld of the PCC subspace structure. OSPM rings
the doorbell by performing a read/modify/write cycle on the speciﬁed register, preserving and setting the bits speciﬁed
in the preserve and write mask of the PCC subspace structure.
The ﬁgure above illustrates the steps that the OPSM takes to send message to the platform over a PCC subspace.
1. First the OSPM checks that there is no command pending completion on the subspace, indicating that the
subspace is free for use. This is done by checking that the command complete bit is set in the status ﬁeld of the
subspace. If the bit is set the subspace is free for use, and the shared memory associated with the subspace is
exclusively owned by the OSPM.
2. The OSPM places a command into the shared memory of the subspace to update the ﬂags, length, command
and payload ﬁelds (See Generic Communications Channel Shared Memory Region ). If the platform indicates
support for platform interrupts in the PCCT (See Platform Communications Channel Global Flags ), then the
OSPM can request that the platform generate an interrupt once it has completed processing the command. This
is requested by setting the Notify on completion bit in the ﬂags (See Platform Communications Channel Global
Flags andInitiator Responder Communications Channel Flags ).
14.5. Doorbell Protocol 749Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 14.1: Communication ﬂow of the doorbell protocol
3. The OSPM then clears the command complete bit. This step transfers ownership of the shared memory to the
platform.
4. OSPM rings the doorbell by performing a read/modify/write cycle on the speciﬁed register, preserving and
setting the bits speciﬁed in the preserve and write mask of the PCC subspace structure.
The management of the command complete bit differs slightly between subspaces of types 0-2 and those of type 3.
For the former, the command complete bit is in a status register which follows a speciﬁc format described in Generic
Communications Channel Status Field . Type 3 subspaces still use a single command complete bit, however allow the
platform to dictate the location and format of the register holding it. Therefore, PCCT structures describing type 3
subspaces use masks and an address to describe how to set the bit. Equally, masks are used for describing how to clear
the bit. For these subspaces to check if the command complete bit is set, the OSPM combines the content of command
complete check register, through a bitwise AND, with the command complete check mask. A non-zero value indicates
the command complete bit is set.
Clearing the command complete bit is done through the command complete update register, which can differ in
address from the command complete check register. In this case the content of the update register is combined through
a bitwise AND with the preserve mask, the result is then combined through a bitwise inclusive OR with the set mask,
and that result is written back to the update register.
For subspaces of type 1-3, the command complete bit must be initialized to one, command complete set, prior to
OSPM sending a command. On type 0 channels, whether the platform sets command complete when the subspace is
initialized is implementation deﬁned. On these subspaces, the OSPM does not have to check for command complete
to be set before sending the ﬁrst command.
The ﬁgure Communication ﬂow of the doorbell protocol above illustrates the steps the platform takes when it receives
the command:
5. For robustness the platform might optionally check that command complete bit is clear
6. Processes the command
7. Sets the command complete bit

14.5. Doorbell Protocol 750Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
8. Triggers the platform interrupt indicated by the GSIV of the subspace’s PCCT entry (see Table 14.7). This will
only occur if an interrupt has been requested in step 2, and interrupts are supported by the platform. A platform
can indicate support for interrupts through the Platform interrupt ﬂag (See Table 14.2)
OSPM can detect command completion either by polling on the command complete bit or via a platform interrupts.
When the OSPM detects that the command has completed it proceeds with the following steps:
9. If necessary clears platform interrupt. This step applies if:
• Platform interrupts are supported by the platform on command completion (see Table 14.2).
• The interrupt was requested by the OSPM through the Notify on completion ﬂag (see Table 14.9 and
Initiator Responder Communications Channel Flags ).
• The interrupt is described as being a level triggered through the Platform Interrupt ﬂags, and Platform
Interrupt Ack register address, and associated masks are provided by the subspace PCCT entry (see table
entries for types 2 and 3).
10. If detecting command completion via interrupt, optionally checks command is complete.
11. Processes the command response.
To ensure correct operation, it is necessary to ensure that all memory updates performed by the OSPM in step 2 are
observable by the platform before step 3 completes. Equally all memory updates performed by the platform in step 6
must be observable by the OSPM before step 7 completes.
Note: For subspace types 0 to 2, all accesses to the Status Field must be made using interlocked operations, by both
entities sharing the subspace. Types 3-4 avoid this requirement. This requirement will be removed for subspace types
0 to 2 as part of deprecation of platform async notiﬁcations in a future spec revision (See the Platform Notiﬁcation
section below).
14.6 Platform Notiﬁcation
The following sections describe platform notiﬁcations on subspace types 0-2 and types 3-4.
14.6.1 Platform Notiﬁcation for Subspace Types 0, 1 and 2
The doorbell protocol is a synchronous notiﬁcation from OSPM to the platform to process a command. If the platform
wants to notify OSPM of an event asynchronously, it may set the Platform Interrupt and Platform Notiﬁcation status
bits and issue a Platform Interrupt. OSPM will service the Interrupt, clear the Platform Interrupt and Platform Noti-
ﬁcation bits, and service the platform notiﬁcation. The meaning of the platform notiﬁcation and the steps required to
service it are deﬁned by the individual components utilizing the PCC interface.
The platform must wait until OSPM has issued a consumer deﬁned command that serves to notify the platform that
OSPM is ready to service Platform Notiﬁcations. The command is subspace speciﬁc and may not be supported by all
subspaces. Platform Notiﬁcations must be used in conjunction with an interrupt. Polling for Platform Notiﬁcations is
The platform may not modify any portion of the shared memory region other than the status ﬁeld when issuing a
platform notiﬁcation.
Platform notiﬁcations for subspace types 0, 1, and 2 will be deprecated in a future revision of the speciﬁcation. Im-
plementers requiring the platform be able to send asynchronous notiﬁcations to OSPM should use Initiator/Responder
subspaces.
14.6. Platform Notiﬁcation 751Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Note: All accesses to the Status Field must be made using interlocked operations, by both entities sharing the subspace.
This requirement will be removed for subspace types 0 to 2 as part of deprecation of platform async notiﬁcations in a
future spec revision .
14.6.2 Platform Notiﬁcation for Responder PCC subspaces (type 4)
Initiator and subspaces only allow synchronous communication from the OSPM to the platform, and do not use the
platform notiﬁcation mechanism provided for subspaces of types 0 to 2. Instead a Initiator subspace can be paired
with a Responder subspace, type 4, which is speciﬁcally provided for platform to OSPM communications.
Fig. 14.2: Communication ﬂow for notiﬁcations on Responder subspaces
Like type 3 Initiator subspaces, type 4 Responder subspaces include a command complete bit. Responder subspaces
are owned by the OSPM by default, and therefore it must set the set the command complete bit when it is ready to
receive notiﬁcations from the platform.
The ﬂow of communications for a notiﬁcation is illustrated in the ﬁgure Communication ﬂow for notiﬁcations on
Responder subspaces above. As can be seen the communication ﬂow is very similar to that of an Initiator subspace,
shown in the ﬁgure Communication ﬂow of the doorbell protocol above, except that the roles of the platform and the
OSPM are reversed. The steps are as follows:
1. First, the platform checks that there no command pending completion on the subspace, indicating that the
exclusively owned by the platform.
2. The platform places a notiﬁcation command into the shared memory in the subspace, updating the ﬂags, length,
command and payload ﬁelds (See Initiator Responder Communications Channel Shared Memory Region ) The
platform can request the OSPM rings the doorbell once it has completed processing the notiﬁcation command
by setting the Generate Signal bit in the ﬂags (see Table 14.13).
14.6. Platform Notiﬁcation 752Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
3. The platform then clears the command complete bit. This transfers ownership of the shared memory to the
OSPM.
4. The platform raises the platform interrupt indicated by the GSIV of the Responder subspace.
When the OSPM receives the interrupt it executes the following steps:
5. Clears the platform interrupt. This is required if the interrupt is described as being a level triggered through the
Platform Interrupt ﬂags, and Platform Interrupt Ack register address, and associated masks are provided by the
subspace PCCT entry (see Table 14.7).
6. Optionally checks the command complete bit is clear.
7. Processes the notiﬁcation command.
8. Sets the command complete bit using the command complete update register and masks.
9. Rings the doorbell. This is required if the doorbell ring was requested by the platform in step 2 above. This also
requires that the PCCT entry for the subspace has a non-zero doorbell register address.
The platform can check whether a notiﬁcation has been processed by the OSPM either by polling the command
complete bit, or where supported through receiving a doorbell interrupt from the OSPM. When the platform detects
that the notiﬁcation has been processed by the OSPM, the platform takes the following steps:
10. If polling check command complete is set. If using a doorbell this step is optional.
11. Processes the command response
The platform must ensure that any writes in step 2, are observable by the OSPM application processors before writes
in step 3. Similarly, the OSPM must ensure that any writes in step 7 are observable by the platform before step 8
completes.
Individual protocols that use PCC deﬁne the meaning of notiﬁcations.
14.7 Referencing the PCC address space
An individual PCC register may be referenced by the Generic Address Structure or in a Generic Register Descriptor
by using the Address Space ID PCC (0xA). When using the PCC address space, the Access Size ﬁeld is redeﬁned to
Subspace ID, and identiﬁes which PCC subspace the descriptor refers to.
As an example, the following resource template refers to the ﬁeld occupying bits 8 through 15 at address 0x30 in PCC
subspace 9:
ResourceTemplate()
{
Register (
PCC, //AddressSpaceKeyword
8, //RegisterBitWidth
8, //RegisterBitOffset
0x30, //RegisterAddress
9 //AccessSize (subspace ID)
)
}
Note that the PCC address space may not be used in any resource template or register unless the register/resource ﬁeld
explicitly allows the use of the PCC address space.
14.7. Referencing the PCC address space 753CHAPTER
FIFTEEN
SYSTEM ADDRESS MAP INTERFACES
This section explains how an ACPI-compatible system conveys its memory resources/type mappings to OSPM. There
are three ways for the system to convey memory resources /mappings to OSPM. The ﬁrst is an INT 15 BIOS interface
that is used in IA-PC-based systems to convey the system’s initial memory map. UEFI enabled systems use the UEFI
GetMemoryMap() boot services function to convey memory resources to the OS loader. These resources must then be
conveyed by the OS loader to OSPM. See the UEFI Speciﬁcation for more information on UEFI services.
Lastly, if memory resources may be added or removed dynamically, memory devices are deﬁned in the ACPI Names-
pace conveying the resource information described by the memory device (see Memory Devices ).

FIFTEEN
ACPI deﬁnes the following address range types.
Table 15.1: Address Range Types
Value Mnemonic Save in S4 Description
1 AddressRangeMemory Yes This range is available RAM usable by the
2 AddressRangeReserved No This range of addresses is in use or reserved
by the system and is not to be included in
the allocatable memory pool of the operat-
ing system’s memory manager.
3 AddressRangeACPI Yes ACPI Reclaim Memory. This range is avail-
able RAM usable by the OS after it reads the
ACPI tables.
4 AddressRangeNVS Yes ACPI NVS Memory. This range of ad-
dresses is in use or reserved by the system
and must not be used by the operating sys-
tem. This range is required to be saved and
restored across an NVS sleep.
5 AddressRangeUnusable No This range of addresses contains memory in
which errors have been detected. This range
must not be used by OSPM.
6 AddressRangeDisabled No This range of addresses contains memory
that is not enabled. This range must not be
used by OSPM.
754Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 15.1 – continued from previous page
7 AddressRangePersistent-
MemoryNo OSPM must comprehend this memory as
having non-volatile attributes and handle
distinct from conventional volatile mem-
ory. The memory region supports byte-
addressable non-volatility. NOTE: Ex-
tended Attributes for the memory re-
ported using AddressRangePersistentMem-
ory should set Bit [0] to 1 (see Extended
Attributes for Address Range Descriptor
Structure ).
8 AddressRangeUnaccepted No A memory region that represents unac-
cepted memory, that must be accepted by
the boot target before it can be used. Unless
otherwise noted, all other memory types are
accepted. For platforms that support unac-
cepted memory, all unaccepted valid mem-
ory will be reported as unaccepted in the
memory map. Unreported physical address
ranges must be treated as not-present mem-
ory.
9-11 Undeﬁned No Reserved for future use. OSPM must treat
any range of this type as if the type returned
wasAddressRangeRe served .
12 OEM deﬁned No An OS should not use a memory type in
the vendor-deﬁned range because collisions
may occur between different vendors.
13 to 0xEFFFFFFF Undeﬁned No Reserved for future use. OSPM must treat
0xF0000000 to
0xFFFFFFFFOEM deﬁned No An OS should not use a memory type in
Platform runtime ﬁrmware can use the AddressRangeReserved address range type to block out various addresses as
not suitable for use by a programmable device. Some of the reasons a platform runtime ﬁrmware would do this are:
• The address range contains system ROM.
• The address range contains RAM in use by the ROM.
• The address range is in use by a memory-mapped system device.
• The address range is, for whatever reason, unsuitable for a standard device to use as a device memory space.
• The address range is within an NVRAM device where reads and writes to memory locations are no longer
successful, that is, the device was worn out.
• OSPM will not save or restore memory reported as AddressRangeReserved, AddressRangeUnusable, Address-
RangeDisabled, or AddressRangePersistentMemory when transitioning to or from the S4 sleeping state.
• Platform boot ﬁrmware must ensure that contents of memory that is reported as AddressRangePersistentMemory
is retained after a system reset or a power cycle event.
755Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
15.1 INT 15H, E820H - Query System Address Map
This interface is used in real mode only on IA-PC-based systems and provides a memory map for all of the installed
RAM, and of physical memory ranges reserved by the BIOS. The address map is returned through successive invoca-
tions of this interface; each returning information on a single range of physical addresses. Each range includes a type
that indicates how the range of physical addresses is to be treated by the OSPM.
If the information returned from E820 in some way differs from INT-15 88 or INT-15 E801, the information returned
from E820 supersedes the information returned from INT-15 88 or INT-15 E801. This replacement allows the BIOS
to return any information that it requires from INT-15 88 or INT-15 E801 for compatibility reasons. For compatibility
reasons, if E820 returns any AddressRangeACPI or AddressRangeNVS memory ranges below 16 MiB, the INT-15
88 and INT-15 E801 functions must return the top of memory below the AddressRangeACPI and AddressRangeNVS
memory ranges.
The memory map conveyed by this interface is not required to reﬂect any changes in available physical memory that
have occurred after the BIOS has initially passed control to the operating system. For example, if memory is added
dynamically, this interface is not required to reﬂect the new system memory conﬁguration.
Table 15.2: Input to the INT 15h E820h Call
Register Contents Description
EAX Function
CodeE820h
EBX Continuation Contains the continuation value to get the next range of physical memory. This is the
value returned by a previous call to this routine. If this is the ﬁrst call, EBX must
contain zero.
ES:DI Buffer Pointer Pointer to an Address Range Descriptor structure that the BIOS ﬁlls in.
ECX Buffer Size The length in bytes of the structure passed to the BIOS. The BIOS ﬁlls in the number
of bytes of the structure indicated in the ECX register, maximum, or whatever amount
of the structure the BIOS implements. The minimum size that must be supported by
both the BIOS and the caller is 20 bytes. Future implementations might extend this
EDX Signature ‘SMAP’ Used by the BIOS to verify the caller is requesting the system map informa-
tion to be returned in ES:DI.
Table 15.3: Output from the INT 15h E820h Call
CF Carry Flag Non-Carry - Indicates No Error
EAX Signature ‘SMAP.’ Signature to verify correct BIOS revision.
ES:DI Buffer Pointer Returned Address Range Descriptor pointer. Same value as on input.
ECX Buffer Size Number of bytes returned by the BIOS in the address range descriptor. The minimum
size structure returned by the BIOS is 20 bytes.
EBX Continuation Contains the continuation value to get the next address range descriptor. The actual
signiﬁcance of the continuation value is up to the discretion of the BIOS. The caller
must pass the continuation value unchanged as input to the next iteration of the E820
call in order to get the next Address Range Descriptor. A return value of zero means
that this is the last descriptor. Note: the BIOS can also indicate that the last descriptor
has already been returned during previous iterations by returning the carry ﬂag set.
The caller will ignore any other information returned by the BIOS when the carry ﬂag
is set.
15.1. INT 15H, E820H - Query System Address Map 756Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 15.4: Address Range Descriptor Structure
Offset
in
BytesName Description
0 BaseAddrLow Low 32 Bits of Base Address
4 BaseAddrHigh High 32 Bits of Base Address
8 LengthLow Low 32 Bits of Length in Bytes
12 LengthHigh High 32 Bits of Length in Bytes
16 Type Address type of this range
20 Extended Attributes See the Extended Attributes for Address Range Descriptor Structure
The BaseAddrLow and BaseAddrHigh together are the 64-bit base address of this range. The base address is the
physical address of the start of the range being speciﬁed.
The LengthLow and LengthHigh together are the 64-bit length of this range. The length is the physical contiguous
length in bytes of a range being speciﬁed.
The Type ﬁeld describes the usage of the described address range as deﬁned in Address Range Types .
Table 15.5: Extended Attributes for Address Range Descriptor
Structure
Bit Mnemonic Description
0 Reserved Reserved, must be set to 1.
2:1 Reserved Reserved, must be set to 0.
3 AddressRangeErrorLog If set, the address range descriptor represents memory used for logging
hardware errors.
31:4 Reserved Reserved for future use.
Note: Bit [1] and [2] above were deprecated as of ACPI 6.1. Bit [3] is used only on PC-AT BIOS systems to pinpoint
the error log in memory. On UEFI-based systems, either UEFI Hardware Error Record HwErrRec#### runtime UEFI
variable interface or the Error Record Serialization Actions 0xD, 0xE and 0xF for the APEI ERST interface must be
implemented for the error logs.
15.2 E820 Assumptions and Limitations
• The platform boot ﬁrmware returns address ranges describing baseboard memory.
• The platform boot ﬁrmware does not return a range description for the memory mapping of PCI devices, ISA
Option ROMs, and ISA Plug and Play cards because the OS has mechanisms available to detect them.
• The platform boot ﬁrmware returns chip set-deﬁned address holes that are not being used by devices as reserved.
• Address ranges deﬁned for baseboard memory-mapped I/O devices, such as APICs, are returned as reserved.

• All occurrences of the system platform boot ﬁrmware are mapped as reserved, including the areas below 1 MB,
at 16 MB (if present), and at end of the 4-GB address space.
• Standard PC address ranges are not reported. For example, video memory at A0000 to BFFFF physical addresses
are not described by this function. The range from E0000 to EFFFF is speciﬁc to the baseboard and is reported
as it applies to that baseboard.
• All of lower memory is reported as normal memory. The OS must handle standard RAM locations that are
reserved for speciﬁc uses, such as the interrupt vector table (0:0) and the platform boot ﬁrmware data area
15.2. E820 Assumptions and Limitations 757Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
(40:0).
15.3 UEFI GetMemoryMap() Boot Services Function
EFI enabled systems use the UEFI GetMemoryMap() boot services function to convey memory resources to the OS
loader. These resources must then be conveyed by the OS loader to OSPM.
The GetMemoryMap interface is only available at boot services time. It is not available as a run-time service after
OSPM is loaded. The OS or its loader initiates the transition from boot services to run-time services by calling
ExitBootServices() . After the call to ExitBootServices() all system memory map information must be derived from
objects in the ACPI Namespace.
The GetMemoryMap() interface returns an array of UEFI memory descriptors. These memory descriptors deﬁne
a system memory map of all the installed RAM, and of physical memory ranges reserved by the ﬁrmware. Each
descriptor contains a type ﬁeld that dictates how the physical address range is to be treated by the operating system.
The table below deﬁnes the mapping from UEFI memory types (see UEFI Speciﬁcation) to ACPI Address Range
Types that:
• Platform boot ﬁrmware shall follow if describing the memory range in both UEFI and legacy BIOS modes; and
• aAn OS loader should use if it conveys that information to the OS using an ACPI E820h system address map
table.
Table 15.6: UEFI Memory Types and mapping to ACPI address
range types
Type Mnemonic ACPI Address Range Type
0 EﬁReservedMemoryType AddressRangeReserved
1 EﬁLoaderCode AddressRangeMemory
2 EﬁLoaderData AddressRangeMemory
3 EﬁBootServicesCode AddressRangeMemory
4 EﬁBootServicesData AddressRangeMemory
5 EﬁRuntimeServiceCode AddressRangeReserved
6 EﬁRuntimeServicesDat a AddressRangeReserved
7 EﬁConventionalMemory AddressRangeMemory
8 EﬁUnusableMemory AddressRangeReserved
9 EﬁACPIReclaimMemory AddressRangeACPI
10 EﬁACPIMemoryNVS AddressRangeNVS
11 EﬁMemoryMappedIO AddressRangeReserved
12 EﬁMemoryMappedIOPort Space AddressRangeReserved
13 EﬁPalCode AddressRangeReserved
14 EﬁPersistentMemory AddressRangePersistentMemory
15 to 0x6FFFFFFF Reserved. AddressRangeReserved
0x70000000 to
0x7FFFFFFFReserved for OEM used An OS should not use a memory type in
0x80000000 to
0xFFFFFFFFReserved for use by UEFI OS loaders that
are provided by operating system vendorsOSV deﬁned
The table above applies to system ﬁrmware that supports legacy BIOS mode plus UEFI mode, and OS loaders.
15.3. UEFI GetMemoryMap() Boot Services Function 758Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
15.4 UEFI Assumptions and Limitations
• The ﬁrmware returns address ranges describing the current system memory conﬁguration.
• The ﬁrmware does not return a range description for the memory mapping of PCI devices, ISA Option ROMs,
and ISA Plug and Play cards because the OS has mechanisms available to detect them.
• The ﬁrmware does not return a range description for address space regions that are not backed by physical
hardware except those mentioned above. Regions that are backed by physical hardware, but are not supposed to
be accessed by the OS, must be returned as reserved. Herein ‘reserved’ is the deﬁnition of the term as noted by
the ACPI speciﬁcation as ACPI address range reserved. OS may use addresses of memory ranges that are not
described in the memory map at its own discretion
• All occurrences of the system ﬁrmware are mapped as reserved, including the areas below 1 MB, at 16 MB
(if present), and at end of the 4-GB address space. This can include PAL code on Itanium™ Processor Family
(IPF)- based platforms.
(40:0). To preserve backward compatibility, platform should avoid using persistent memory to materialize the
lower memory. If persistent memory is used for lower memory, platform boot ﬁrmware must report the lower
memory address range using AddressRangeMemory and must not report using AddressRangePersistentMemory.
• EFI contains descriptors for memory mapped I/O and memory mapped I/O port space to allow for virtual mode
calls to UEFI run-time functions. The OS must never use these regions.
15.4. UEFI Assumptions and Limitations 759Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
15.5 Example Address Map
This sample address map (for an Intel processor-based system) describes a machine that has 128 MiB of RAM, 640
KiB of base memory and 127 MiB of extended memory. The base memory has 639 KiB available for the user and
1 KiB for an extended BIOS data area. A 4-MiB Linear Frame Buffer (LFB) is based at 12 MiB. The memory hole
created by the chip set is from 8 MiB to 16 MiB. Memory-mapped APIC devices are in the system. The I/O Unit is at
FEC00000 and the Local Unit is at FEE00000. The system BIOS is remapped to 1 GB-64 KiB.
The 639-KiB endpoint of the ﬁrst memory range is also the base memory size reported in the BIOS data segment at
40:13. The following table shows the memory map of a typical system.
Table 15.7: Sample Memory Map
Base (Hex) Length Type Description
0000 0000 639 KiB AddressRangeMemory Available Base memory. Typically the same value as is
returned using the INT 12 function.
0009 FC00 1 KiB AddressRangeReserved Memory reserved for use by the BIOS(s). This area typ-
ically includes the Extended BIOS data area.
000F 0000 64 KiB AddressRangeReserved System BIOS
0010 0000 7 MiB AddressRangeMemory Extended memory, which is not limited to the 64-MiB
0080 0000 4 MiB AddressRangeReserved Chip set memory hole required to support the LFB map-
ping at 12 MiB.
0100 0000 60 MiB AddressRangeMemory Baseboard RAM relocated above a chip set memory
hole.
04C0 0000 60 MiB AddressRangePersistentMemory Persistent memory that has non-volatile attributes lo-
cated in this region.
FEC0 0000 4 KiB AddressRangeReserved I/O APIC memory mapped I/O at FEC00000.
FEE0 0000 4 KiB AddressRangeReserved Local APIC memory mapped I/O at FEE00000.
FFFF 0000 64 KiB AddressRangeReserved Remapped System BIOS at end of address space.
15.5. Example Address Map 760Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
15.6 Example: Operating System Usage
The following code segment illustrates the algorithm to be used when calling the Query System Address Map function.
This is an implementation example and uses non-standard mechanisms:
E820Present = FALSE;
Reg.ebx = 0;
do {
Reg.eax = 0xE820;
Reg.es = SEGMENT (&Descriptor);
Reg.di = OFFSET (&Descriptor);
Reg.ecx = sizeof (Descriptor);
Reg.edx = 'SMAP';
\_int( 15, regs );
if ((Regs.eflags & EFLAG_CARRY) \|\| Regs.eax != 'SMAP') {
break;
}
if (Regs.ecx < 20 \|\| reg.ecx > sizeof (Descriptor) ) {
// bug in bios - all returned descriptors must be
// at least 20 bytes long, and cannot be larger then
// the input buffer.
break;
}
E820Present = TRUE;
.
.
.
Add address range Descriptor.BaseAddress through
Descriptor.BaseAddress + Descriptor.Length
as type Descriptor.Type
.
.
.
} while (Regs.ebx != 0);
if (!E820Present) {
.
.
.
call INT-15 88 and/or INT-15 E801 to obtain old style memory information
.
.
.
}
15.6. Example: Operating System Usage 761CHAPTER
SIXTEEN
WAKING AND SLEEPING
ACPI deﬁnes a mechanism to transition the system between the working state (G0) and a sleeping state (G1) or the
soft-off (G2) state. During transitions between the working and sleeping states, the context of the user’s operating
environment is maintained. ACPI deﬁnes the quality of the G1 sleeping state by deﬁning the system attributes of four
types of ACPI sleeping states (S1, S2, S3, and S4). Each sleeping state is deﬁned to allow implementations that can
tradeoff cost, power, and wake latencies. Additionally, ACPI deﬁnes the sleeping states such that an ACPI platform

break;
}
.
.
.
.
.
.
.
.
.
.
.
.
}
SIXTEEN
can support multiple sleeping states, allowing the platform to transition into a particular sleeping state for a predeﬁned
period of time and then transition to a lower power/higher wake latency sleeping state (transitioning through the G0
state) (See note below).
OSPM uses the RTC wakeup feature or the Time and Alarm Namespace
device to program in the time transition delay. Prior to sleeping, OSPM
will program the alarm to the closest (in time) wakeup event: either a
transition to a lower power sleeping state, or a calendar event (to run
some application).
ACPI deﬁnes a programming model that provides a mechanism for OSPM to initiate the entry into a sleeping or soft-
off state (S1-S5); this consists of a 3 bit ﬁeld SLP_TYPx (See note below) that indicates the type of sleep state to enter,
and a single control bit SLP_EN to start the sleeping process. On HW-reduced ACPI systems, the register described
by the SLEEP_CONTROL_REG ﬁeld in the FADT is used instead of the ﬁxed SLP_TYPx and SLP_EN register bit
ﬁelds.
Notice that there can be two fixed PM1x_CNT registers, each pointing
to a different system I/O space region. Normally a register grouping
only allows a bit or bit field to reside in a single register group
instance (a or b); however, each platform can have two instances of the
SLP_TYP (one for each grouping register: a and b). The \_Sx control
method gives a package with two values: the first is the SLP_TYPa value
and the second is the SLP_TYPb value.
Note: Systems containing processors without a hardware mechanism to place the processor in a low-power state may
additionally require the execution of appropriate native instructions to place the processor in a low-power state after
OSPM sets the SLP_EN bit. The hardware may implement a number of low-power sleeping states and then associate
these states with the deﬁned ACPI sleeping states (through the SLP_TYPx ﬁelds). The ACPI system ﬁrmware creates
a sleeping object associated with each supported sleeping state (unsupported sleeping states are identiﬁed by the lack
of the sleeping object). Each sleeping object contains two constant 3-bit values that OSPM will program into the
SLP_TYPa and SLP_TYPb ﬁelds (in ﬁxed register space), or, on HW-reduced ACPI platforms, a single 3-bit value
that OSPM will write to the register speciﬁed by the FADT’s SLEEP_CONTROL_REG ﬁeld.
On systems that are not HW-reduced ACPI platforms, an alternate mechanism for entering and exiting the S4 state is
deﬁned. This mechanism passes control to the platform runtime ﬁrmware to save and restore platform context. Context
ownership is similar in deﬁnition to the S3 state, but hardware saves and restores the context of memory to non-volatile
762Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
storage (such as a disk drive), and OSPM treats this as an S4 state with implied latency and power constraints. This
alternate mechanism of entering the S4 state is referred to as the S4BIOS transition.
Prior to entering a sleeping state (S1-S4), OSPM will execute OEM-speciﬁc AML/ASL code contained in the _PTS
(Prepare To Sleep) control method. One use of the _PTS control method is that it can indicate to the embedded
controller what sleeping state the system will enter. The embedded controller can then respond by executing the
proper power-plane sequencing upon sleep state entry.
The _WAK (Wake) control method is then executed. This control method again contains OEM-speciﬁc AML/ASL
code. One use of the _WAK control method requests OSPM to check the platform for any devices that might have
been added or removed from the system while the system was asleep. For example, a PC Card controller might have
had a PC Card added or removed, and because the power to this device was off in the sleeping state, the status change
event was not generated.
This section discusses the system initialization sequence of an ACPI-enabled platform. This includes the boot se-
quence, different wake scenarios, and an example to illustrate how to use the system address map reporting interfaces.
This sequence is part of the ACPI event programming model.
Note: HW-reduced ACPI platforms do not implement the Legacy Mode nor the S4BIOS state described below.
For detailed information on the power management control methods described above, see Power and Performance
16.1 Sleeping States
The illustration below shows the transitions between the working state, the sleeping states, and the Soft Off state.
Fig. 16.1: Example Sleeping States
16.1. Sleeping States 763Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ACPI deﬁnes distinct differences between the G0 and G1 system states.
• In the G0 state, work is being performed by the OS/application software and the hardware. The CPU or any
particular hardware device could be in any one of the deﬁned power states (C0-C3 or D0-D3); however, some
work will be taking place in the system.
• In the G1 state, the system is assumed to be doing no work. Prior to entering the G1 state, OSPM will place
devices in a device power state compatible with the system sleeping state to be entered; if a device is enabled to
wake the system, then OSPM will place these devices into the lowest Dx state from which the device supports
wake. This is deﬁned in the power resource description of that device object. This deﬁnition of the G1 state
implies:
• The CPUs execute no instructions in the G1 state.
• Hardware devices are not operating (except possibly to generate a wake event).
• If not HW-reduced, ACPI registers are affected as follows:
–Wake event bits are enabled in the corresponding ﬁxed or general-purpose registers according to enabled
wake options.
–PM1 control register is programmed for the desired sleeping state.
–WAK_STS is set by hardware in the sleeping state.
All sleeping states have these speciﬁcations. ACPI deﬁnes additional attributes that allow an ACPI platform to have
up to four different sleeping states, each of which has different attributes. The attributes were chosen to allow differ-
entiation of sleeping states that vary in power, wake latency, and implementation cost tradeoffs.
Running processors at reduced levels of performance is not an ACPI sleeping state (G1); this is a working (G0)
state-deﬁned event.
The CPU cannot execute any instructions when in the sleeping state; OSPM relies on this fact. A platform designer
might be tempted to support a sleeping system by reducing the clock frequency of the system, which allows the plat-
form to maintain a low-power state while at the same time maintaining communication sessions that require constant
interaction (as with some network environments). This is deﬁnitely a G0 activity where an OS policy decision has been
made to turn off the user interface (screen) and run the processor in a reduced performance mode. This type of reduced
performance state as a sleeping state is not deﬁned by the ACPI speciﬁcation; ACPI assumes no code execution during
sleeping states.
ACPI deﬁnes attributes for four sleeping states: S1, S2, S3 and S4. (Notice that S4 and S5 are very similar from a
hardware standpoint.) ACPI-compatible platforms can support multiple sleeping states. ACPI speciﬁes that a 3-bit
binary number be associated with each sleeping state (these numbers are given objects within ACPI’s root namespace:
(\_S0, \_S1, \_S2, \_S3, \_S4 and \_S5). When entering a system sleeping state, OSPM will do the following:
1. Pick the deepest sleeping state supported by the platform and enabled waking devices.
2. Execute the _PTS control method (which passes the type of intended sleep state to OEM AML code).
3. If OS policy decides to enter the S4 state and chooses to use the S4BIOS mechanism and S4BIOS is supported
by the platform, OSPM will pass control to the platform runtime ﬁrmware software by writing the S4BIOS_REQ
value to the SMI_CMD port.
4. If not using the S4BIOS mechanism, OSPM gets the SLP_TYPx value from the associated sleeping object (\_S1,
\_S2, \_S3, \_S4 or \_S5).
5. Program the SLP_TYPx ﬁelds with the values contained in the selected sleeping object.
Note: Compatibility — The _GTS method is deprecated in ACPI 5.0A. For earlier versions, execute the _GTS
control method, passing an argument that indicates the sleeping state to be entered (1, 2, 3, or 4 representing S1,
S2, S3, and S4).
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6. If entering S1, S2, or S3, ﬂush the processor caches.
7. If not entering S4BIOS, set the SLP_EN bit to start the sleeping sequence. (This actually occurs on the same
write operation that programs the SLP_TYPx ﬁeld in the PM1_CNT register.) If entering S4BIOS, write the
S4BIOS_REQ value into the SMI_CMD port.
8. If HW-reduced, program the register indicated by the SLEEP_CONTROL_REG FADT ﬁeld with the HW-
reduced ACPI Sleep Type value (retrieved from the sleep state object in step 4 above) and with the SLP_EN bit
set to one.

set to one.
9. On systems containing processors without a hardware mechanism to place the processor in a low-power state,
execute appropriate native instructions to place the processor in a low-power state.
The _PTS control method provides the platform runtime ﬁrmware a mechanism for performing some housekeeping,
such as writing the sleep type value to the embedded controller, before entering the system sleeping state. Control
method execution occurs “just prior” to entering the sleeping state and is not an event synchronized with the write to
the PM1_CNT register. Execution can take place several seconds prior to the system actually entering the sleeping
state. As such, no hardware power-plane sequencing takes place by execution of the _PTS control method.
Note: Compatibility — The _BFS method is deprecated in ACPI 5.0A. In earlier versions, on waking, the _BFS
control method is executed. OSPM then executes the _WAK control method. This control method executes OEM-
speciﬁc ASL/AML code that can search for any devices that have been added or removed during the sleeping state.*
The following sections describe the sleeping state attributes.
16.1.1 S1 Sleeping State
The S1 state is deﬁned as a low wake-latency sleeping state. In this state, all system context is preserved with the
exception of CPU caches. Before entering S1, OSPM will ﬂush the system caches. If the platform supports the
WBINVD instruction (as indicated by the WBINVD and WBINVD_FLUSH ﬂags in the FADT), OSPM will execute
the WBINVD instruction. The hardware is responsible for maintaining all other system context, which includes the
context of the CPU, memory, and chipset.
Examples of S1 sleeping state implementation alternatives follow.
16.1.1.1 Example 1: S1 Sleeping State Implementation
This example references an IA processor that supports the stop grant state through the assertion of the STPCLK#
signal. When SLP_TYPx is programmed to the S1 value (the OEM chooses a value, which is then placed in the
\_S1 object) and the SLP_ENx bit is subsequently set, or when the HW-reduced ACPI Sleep Type value for S1 and
the SLP_EN bit are written to the Sleep Control Register, the hardware can implement an S1 state by asserting the
STPCLK# signal to the processor, causing it to enter the stop grant state.
In this case, the system clocks (PCI and CPU) are still running. Any enabled wake event causes the hardware to de-
assert the STPCLK# signal to the processor whereby OSPM must ﬁrst invalidate the CPU caches and then transition
back into the working state.
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16.1.1.2 Example 2: S1 Sleeping State Implementation
When SLP_TYPx is programmed to the S1 value and the SLP_ENx bit is subsequently set, or the HW-reduced ACPI
Sleep Type value for S1 and the SLP_EN bit are written to the Sleep Control Register, the hardware will implement
an S1 sleeping state transition by doing the following:
1. Placing the processor into the stop grant state.
2. Stopping the processor’s input clock, placing the processor into the stop clock state.
3. Placing system memory into a self-refresh or suspend-refresh state. Refresh is maintained by the memory itself
or through some other reference clock that is not stopped during the sleeping state.
4. Stopping all system clocks (asserts the standby signal to the system PLL chip). Normally the RTC will continue
running.
In this case, all clocks in the system have been stopped (except for the RTC). Hardware must reverse the process
(restarting system clocks) upon any enabled wake event whereby OSPM must ﬁrst invalidate the CPU caches and then
transition back into the working state.
16.1.2 S2 Sleeping State
The S2 state is deﬁned as a low wake latency sleep state. This state is similar to the S1 sleeping state where any
context except for system memory may be lost. Additionally, control starts from the processor’s reset vector after the
wake event. Before entering S2 the SLP_EN bit, OSPM will ﬂush the system caches. If the platform supports the
the WBINVD instruction. The hardware is responsible for maintaining chip set and memory context. An example of
an S2 sleeping state implementation follows.
16.1.2.1 Example: S2 Sleeping State Implementation
When the SLP_TYPx register(s) are programmed to the S2 value (found in the \_S2 object) and the SLP_EN bit is set,
or the HW-reduced ACPI Sleep Type value for S2 and the SLP_EN bit are written to the Sleep Control Register, the
hardware will implement an S2 sleeping state transition by doing the following:
1. Stopping system clocks (the only running clock is the RTC).
2. Placing system memory into a self-refresh or suspend-refresh state.
3. Powering off the CPU and cache subsystem.
From S2 Sleeping State the CPU is reset upon detection of the wake event; however, core logic and memory maintain
their context. Execution control starts from the CPU’s boot vector. The platform boot ﬁrmware is required to:
1. Program the initial boot conﬁguration of the CPU (such as the CPU’s MSR and MTRR registers).
2. Initialize the cache controller to its initial boot size and conﬁguration.
3. Enable the memory controller to accept memory accesses.
4. Jump to the waking vector.
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16.1.3 S3 Sleeping State
The S3 state is deﬁned as a low wake-latency sleep state. From the software viewpoint, this state is functionally the
same as the S2 state. The operational difference is that some Power Resources that may have been left ON in the S2
state may not be available to the S3 state. As such, some devices may be in a lower power state when the system is in
S3 state than when the system is in the S2 state. Similarly, some device wake events can function in S2 but not S3. An
example of an S3 sleeping state implementation follows.
16.1.3.1 Example: S3 Sleeping State Implementation
When the SLP_TYPx register(s) are programmed to the S3 value (found in the \_S3 object) and the SLP_EN bit is set,
or the HW-reduced ACPI Sleep Type value for S3 and the SLP_EN bit are written to the Sleep Control Register, the
hardware will implement an S3 sleeping state transition by doing the following:
1. Placing the memory into a low-power auto-refresh or self-refresh state.
2. Devices that are maintaining memory isolating themselves from other devices in the system.
3. Removing power from the system. At this point, only devices supporting memory are powered (possibly par-
tially powered). The only clock running in the system is the RTC clock.
From S3 Sleeping State, the wake event repowers the system and resets most devices (depending on the implementa-
tion). Execution control starts from the CPU’s boot vector. The platform boot ﬁrmware is required to:
1. Program the initial boot conﬁguration of the CPU (such as the MSR and MTRR registers).
Notice that if the conﬁguration of cache memory controller is lost while the system is sleeping, the platform boot
ﬁrmware is required to reconﬁgure it to either the pre-sleeping state or the initial boot state conﬁguration. The platform
boot ﬁrmware can store the conﬁguration of the cache memory controller into the reserved memory space, where it
can then retrieve the values after waking. OSPM will call the _PTS method once per session (prior to sleeping).
The platform boot ﬁrmware is also responsible for restoring the memory controller’s conﬁguration. If this conﬁgura-
tion data is destroyed during the S3 sleeping state, then the platform boot ﬁrmware needs to store the pre-sleeping state
or initial boot state conﬁguration in a non-volatile memory area (as with RTC CMOS RAM) to enable it to restore the
values during the waking process.
When OSPM re-enumerates buses coming out of the S3 sleeping state, it will discover any devices that have been
inserted or removed, and conﬁgure devices as they are turned on.
16.1.4 S4 Sleeping State
The S4 sleeping state is the lowest-power, longest wake-latency sleeping state supported by ACPI. In order to reduce
power to a minimum, it is assumed that the hardware platform has powered off all devices. Because this is a sleeping
state, the platform context is maintained. Depending on how the transition into the S4 sleeping state occurs, the
responsibility for maintaining system context changes. S4 supports two entry mechanisms: OS initiated and platform
runtime ﬁrmware-initiated. The OSPM-initiated mechanism is similar to the entry into the S1-S3 sleeping states;
OSPM driver writes the SLP_TYPx ﬁelds and sets the SLP_EN bit, or writes the HW-reduced ACPI Sleep Type value

for S3 and the SLP_EN bit to the Sleep Control Register. The platform runtime ﬁrmware-initiated mechanism occurs
by OSPM transferring control to the platform runtime ﬁrmware by writing the S4BIOS_REQ value to the SMI_CMD
port, and is not supported on HW-reduced ACPI platforms.
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In OSPM-initiated S4 sleeping state, OSPM is responsible for saving all system context. Before entering the S4 state,
OSPM will save context of all memory as speciﬁed in System Address Map Interfaces .
Upon waking, OSPM shall then restore the system context. When OSPM re-enumerates buses coming out of the S4
sleeping state, it will discover any devices that have come and gone, and conﬁgure devices as they are turned on.
In the platform runtime ﬁrmware-initiated S4 sleeping state, OSPM is responsible for the same system context as
described in the S3 sleeping state (platform runtime ﬁrmware restores the memory and some chip set context). The
S4BIOS transition transfers control to the platform runtime ﬁrmware, allowing it to save context to non-volatile mem-
ory (such as a disk partition).
16.1.4.1 Operating System-Initiated S4 Transition
If OSPM supports OSPM-initiated S4 transition, it will not generate a platform ﬁrmware-initiated S4 transition. Plat-
forms that support the platform ﬁrmware-initiated S4 transition also support OSPM-initiated S4 transition.
OSPM-initiated S4 transition is initiated by OSPM by saving system context, writing the appropriate values to the
SLP_TYPx register(s), and setting the SLP_EN bit, or writes the HW-reduced ACPI Sleep Type value for S4 and the
SLP_EN bit to the Sleep Control Register. Upon exiting the S4 sleeping state, the platform boot ﬁrmware restores the
chipset to its POST condition, updates the hardware signature (described later in this section), and passes control to
OSPM through a normal boot process.
When the platform boot ﬁrmware builds the ACPI tables, it generates a hardware signature for the system. If the
hardware conﬁguration has changed during an OS-initiated S4 transition and it changes the content or structure of the
ACPI tables, the platform boot ﬁrmware updates the hardware signature in the FACS table as described in Section
5.2.10 (Firmware ACPI Control Structure (FACS)).
Upon waking, in order to locate the hardware signature, the physical address of the RSDP must be reacquired via
methods described in 5.2.5.1 (Finding the RSDP on IA-PC Systems) or 5.2.5.2 (Finding the RSDP on UEFI Enable
Systems) and therefore it must not be assumed that the FACS and its Hardware Signature would be located in the same
physical memory address as the prior boot.
16.1.4.2 The S4BIOS Transition
This transition is not supported on HW-reduced ACPI platforms. On other systems, the platform runtime ﬁrmware-
initiated S4 transition begins with OSPM writing the S4BIOS_REQ value into the SMI_CMD port (as speciﬁed in the
FADT). Once gaining control, the platform runtime ﬁrmware then saves the appropriate memory and chip set context,
and then places the platform into the S4 state (power off to all devices).
In the FACS memory table, there is the S4BIOS_F bit that indicates hardware support for the platform runtime
ﬁrmware-initiated S4 transition. If the hardware platform supports the S4BIOS state, it sets the S4BIOS_F ﬂag within
the FACS memory structure prior to booting the OS. If the S4BIOS_F ﬂag in the FACS table is set, this indicates that
OSPM can request the platform runtime ﬁrmware to transition the platform into the S4BIOS sleeping state by writing
the S4BIOS_REQ value (found in the FADT) to the SMI_CMD port (identiﬁed by the SMI_CMD value in the FADT).
Upon waking the platform boot ﬁrmware restores memory context and jumps to the waking vector (similar to wake
from an S3 state). Coming out of the S4BIOS state, the platform boot ﬁrmware must only conﬁgure boot devices (so
it can read the disk partition where it saved system context). When OSPM re-enumerates buses coming out of the
S4BIOS state, it will discover any devices that have come and gone, and conﬁgure devices as they are turned on.
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16.1.5 S5 Soft Off State
OSPM places the platform in the S5 soft off state to achieve a logical off. Notice that the S5 state is not a sleeping
state (it is a G2 state) and no context is saved by OSPM or hardware but power may still be applied to parts of the
platform in this state, and, as such, it is not safe to disassemble. Also notice that from a hardware perspective, the S4
and S5 states are nearly identical. When initiated, the hardware will sequence the system to a state similar to the off
state. The hardware has no responsibility for maintaining any system context (memory or I/O); however, it does allow
a transition to the S0 state due to a power button press or a Remote Start. Upon start-up, the platform boot ﬁrmware
performs a normal power-on reset, loads the boot sector, and then executes (but not the waking vector, as all ACPI
table context is lost when entering the S5 soft off state).
The _TTS control method allows the platform runtime ﬁrmware a mechanism for performing some housekeeping,
such as storing the targeted sleep state in a “global” variable that is accessible by other control methods (such as _PS3
and _DSW).
16.1.6 Transitioning from the Working to the Sleeping State
On a transition of the system from the working to the sleeping state, the following occurs:
1. OSPM decides (through a policy scheme) to place the system into the sleeping state.
2. OSPM invokes the _TTS method to indicate the deepest possible system state the system will transition to (1, 2,
3, or 4 representing S1, S2, S3, and S4).
3. OSPM examines all devices enabled to wake the system and determines the deepest possible sleeping state
the system can enter to support the enabled wake functions. The _PRW named object under each device is
examined, as well as the power resource object it points to.
4. OSPM places all device drivers into their respective Dx state. If the device is enabled for wake, it enters the Dx
state associated with the wake capability. If the device is not enabled to wake the system, it enters the D3 state.
5. OSPM executes the _PTS control method, passing an argument that indicates the desired sleeping state (1, 2, 3,
or 4 representing S1, S2, S3, and S4).
6. OSPM saves any other processor’s context (other than the local processor) to memory.
7. OSPM writes the waking vector into the FACS table in memory.
Note: Compatibility — The _GTS method is deprecated in ACPI 5.0A. For earlier versions, OSPM executes
the _GTS control method, passing an argument that indicates the sleeping state to be entered (1, 2, 3, or 4
representing S1, S2, S3, and S4).*
8. If not a HW-reduced ACPI platform, OSPM clears the WAK_STS in the PM1a_STS and PM1b_STS registers.
On HW-reduced ACPI platforms, OSPM clears the WAK_STS bit in the Sleep Status Register.
9. OSPM saves the local processor’s context to memory.
10. OSPM ﬂushes caches (only if entering S1, S2 or S3).
11. OSPM sets GPE enable registers or enables wake-capable interrupts to ensure that all appropriate wake signals
are armed.
12. If entering an S4 state using the S4BIOS mechanism, OSPM writes the S4BIOS_REQ value (from the FADT) to
the SMI_CMD port. This passes control to the platform runtime ﬁrmware, which then transitions the platform
into the S4BIOS state.
13. If not entering an S4BIOS state, and not a HW-reduced ACPI platform, then OSPM writes SLP_TYPa (from
the associated sleeping object) with the SLP_ENa bit set to the PM1a_CNT register.
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14. OSPM writes SLP_TYPb with the SLP_EN bit set to the PM1b_CNT register, or writes the HW-reduced ACPI
Sleep Type value and the SLP_EN bit to the Sleep Control Register.
15. On systems containing processors without a hardware mechanism to place the processor in a low-power state,
OSPM executes appropriate native instructions to place the processor in a low-power state.
16. OSPM loops on the WAK_STS bit, either in both the PM1a_CNT and PM1b_CNT registers, or in the
SLEEP_STATUS_REG, in the case of HW-reduced ACPI platforms.
17. The system enters the speciﬁed sleeping state.
Note: This is accomplished after step 14 or 15 above.
16.1.7 Transitioning from the Working to the Soft Off State
On a transition of the system from the working to the soft off state, the following occurs:
1. OSPM executes the _PTS control method, passing the argument 5.
2. OSPM prepares its components to shut down (ﬂushing disk caches).
Note: Compatibility — The _GTS method is deprecated in ACPI 5.0A. For earlier versions, OSPM executes the
_GTS control method, passing the argument 5.
3. If not a HW-reduced ACPI platform, OSPM writes SLP_TYPa (from the \_S5 object) with the SLP_ENa bit set
to the PM1a_CNT register.

4. OSPM writes SLP_TYPb (from the \_S5 object) with the SLP_ENb bit set to the PM1b_CNT register, or writes
the HW-reduced ACPI Sleep Type value for S5 and the SLP_EN bit to the Sleep Control Register.
5. The system enters the Soft Off state.
16.2 Flushing Caches
Before entering the S1, S2 or S3 sleeping states, OSPM is responsible for ﬂushing the system caches. ACPI provides
a number of mechanisms to ﬂush system caches. These include:
• Using a native instruction (for example, the IA-32 architecture WBINVD instruction) to ﬂush and invalidate
platform caches.
–WBINVD_FLUSH ﬂag set (1) in the FADT indicates the system provides this support level.
• Using the IA-32 instruction WBINVD to ﬂush but notinvalidate the platform caches.
–WBINVD ﬂag set (1) in the FADT indicates the system provides this support level.
The manual ﬂush mechanism has two caveats:
• Largest cache is 1 MB in size ( FLUSH_SIZE is a maximum value of 2 MB ).
• No victim caches (for which the manual ﬂush algorithm is unreliable).
Processors with built-in victim caches will not support the manual ﬂush mechanism and are therefore required to
support the WBINVD mechanism to use the S2 or S3 state.
The manual cache-ﬂushing mechanism relies on the two FADT ﬁelds:
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•FLUSH_SIZE. Indicates twice the size of the largest cache in bytes.
•FLUSH_STRIDE. Indicates the smallest line size of the caches in bytes.
The cache ﬂush size value is typically twice the size of the largest cache size, and the cache ﬂush stride value is
typically the size of the smallest cache line size in the platform. OSPM will ﬂush the system caches by reading a
contiguous block of memory indicated by the cache ﬂush size.
16.3 Initialization
This section covers the initialization sequences for an ACPI platform. After a reset or wake from an S2, S3, or S4
sleeping state (as deﬁned by the ACPI sleeping state deﬁnitions), the CPU will start execution from its boot vector.
At this point, the initialization software has many options, depending on what the hardware platform supports. This
section describes at a high level what should be done for these different options. The ﬁgure below illustrates the ﬂow
of the boot-up software.
The processor will start executing at its power-on reset vector when waking from an S2, S3, or S4 sleeping state,
during a power-on sequence, or as a result of a hard or soft reset.
When executing from the power-on reset vector as a result of a power-on sequence, a hard or soft reset, or waking
from an S4 sleep state, the platform ﬁrmware performs complete hardware initialization; placing the system in a boot
conﬁguration. The ﬁrmware then passes control to the operating system boot loader.
When executing from the power-on reset vector as a result of waking from an S2 or S3 sleep state, the platform
ﬁrmware performs only the hardware initialization required to restore the system to either the state the platform
was in prior to the initial operating system boot, or to the pre-sleep conﬁguration state. In multiprocessor sys-
tems, non-boot processors should be placed in the same state as prior to the initial operating system boot. The plat-
form ﬁrmware then passes control back to OSPM system by jumping to either the Firmware_Waking_Vector or the
X_Firmware_Waking_Vector in the FACS (see Firmware ACPI Control Structure (FACS) for more information). The
contents of operating system memory contents may not be changed during the S2 or S3 sleep state.
First, the platform runtime ﬁrmware determines whether this is a wake from S2 or S3 by examining the SLP_TYP
register value, which is preserved between sleeping sessions. If this is an S2 or S3 wake, then the platform runtime
ﬁrmware restores minimum context of the system before jumping to the waking vector. This includes:
CPU conﬁguration. Platform runtime ﬁrmware restores the pre-sleep conﬁguration or initial boot conﬁguration of
each CPU (MSR, MTRR, ﬁrmware update, SMBase, and so on). Interrupts must be disabled (for IA-32 proces-
sors, disabled by CLI instruction).
Memory controller conﬁguration. the conﬁguration is lost during the sleeping state, the platform runtime ﬁrmware
initializes the memory controller to its pre-sleep conﬁguration or initial boot conﬁguration.
Cache memory conﬁguration. If the conﬁguration is lost during the sleeping state, the platform runtime ﬁrmware
initializes the cache controller to its pre-sleep conﬁguration or initial boot conﬁguration.
Functional device conﬁguration. The platform runtime ﬁrmware doesn’t need to conﬁgure/restore context of func-
tional devices such as a network interface (even if it is physically included in chipset) or interrupt controller.
OSPM is responsible for restoring all context of these devices. The only requirement for the hardware and
platform runtime ﬁrmware is to ensure that interrupts are not asserted by devices when the control is passed to
OS.
ACPI registers. SCI_EN bit must be set on non-HW-reduced ACPI platforms, and all event status/enable bits
(PM1x_STS, PM1x_EN, GPEx_STS and GPEx_EN) must not be changed by platform runtime ﬁrmware.
Note: The platform runtime ﬁrmware may reconﬁgure the CPU, memory controller, and cache memory controller to
either the pre-sleeping conﬁguration or the initial boot conﬁguration. OSPM must ccommodate both conﬁgurations.
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Fig. 16.2: Platform Firmware Initialization
16.3. Initialization 772Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
When waking from an S4BIOS sleeping state, the platform boot ﬁrmware initializes a minimum number of devices
such as CPU, memory, cache, chipset and boot devices. After initializing these devices, the platform boot ﬁrmware
restores memory context from non-volatile memory such as hard disk, and jumps to waking vector.
As mentioned previously, waking from an S4 state is treated the same as a cold boot: the platform boot ﬁrmware runs
POST and then initializes memory to contain the ACPI system description tables. After it has ﬁnished this, it can call
OSPM loader, and control is passed to OSPM.
When waking from S4 (either S4OS or S4BIOS), the platform boot ﬁrmware may optionally set SCI_EN bit before
passing control to OSPM. In this case, interrupts must be disabled (for IA-32 processors, disabled CLI instruction)
until the control is passed to OSPM and the chipset must be conﬁgured in ACPI mode.
16.3.1 Placing the System in ACPI Mode
When a platform initializes from a cold boot (mechanical off or from an S4 or S5 state), the hardware platform may
be conﬁgured in a legacy conﬁguration, if not a HW-reduced ACPI platform. From these states, the platform boot
ﬁrmware software initializes the computer as it would for a legacy operating system. When control is passed to the
operating system, OSPM will check the SCI_EN bit and if it is not set will then enable ACPI mode by ﬁrst ﬁnding
the ACPI tables, and then by generating a write of the ACPI_ENABLE value to the SMI_CMD port (as described in
the FADT). The hardware platform will set the SCI_EN bit to indicate to OSPM that the hardware platform is now
conﬁgured for ACPI.
Note: Before SCI is enabled, no SCI interrupt can occur. Nor can any SCI interrupt occur immediately after ACPI is
on. The SCI interrupt can only be signaled after OSPM has enabled one of the GPE/PM1 enable bits.
When the platform is waking from an S1, S2 or S3 state, and from S4 and S5 on HW-reduced ACPI platforms, OSPM
assumes the hardware is already in the ACPI mode and will not issue an ACPI_ENABLE command to the SMI_CMD
port
16.3.2 Platform Boot Firmware Initialization of Memory
During a power-on reset, an exit from an S4 sleeping state, or an exit from an S5 soft-off state, the platform boot
ﬁrmware needs to initialize memory. This section explains how the platform boot ﬁrmware should conﬁgure memory
for use by a number of features including:
• ACPI tables.
• Platform ﬁrmware memory that wants to be saved across S4 sleeping sessions and should be cached.
• Platform ﬁrmware memory that does not require saving and should be cached.
For example, the conﬁguration of the platform’s cache controller requires an area of memory to store the conﬁguration
data. During the wake sequence, the platform boot ﬁrmware will re-enable the memory controller and can then use
its conﬁguration data to reconﬁgure the cache controllers. To support these three items, IA-PC-based systems contain
System Address Map Interfaces that return the following memory range types:
ACPI Reclaim Memory. Memory identiﬁed by the platform boot ﬁrmware that contains the ACPI tables. This mem-
ory can be any place above 8 MB and contains the ACPI tables. When OSPM is ﬁnished using the ACPI tables,
it is free to reclaim this memory for system software use (application space).
ACPI Non-Volatile-Sleeping Memory (NVS). Memory identiﬁed by the BIOS as being reserved by the platform

boot ﬁrmware for its use. OSPM is required to tag this memory as cacheable, and to save and restore its image
before entering an S4 state. Except as directed by control methods, OSPM is not allowed to use this physical
memory. OSPM will call the _PTS control method some time before entering a sleeping state, to allow the
platform’s AML code to update this memory image before entering the sleeping state. After the system awakes
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from an S4 state, OSPM will restore this memory area and call the _WAK control method to enable the platform
boot ﬁrmware to reclaim its memory image.
Note: The memory information returned from the system address map reporting interfaces should be the same before
and after an S4 sleep.
When the system is ﬁrst booting, OSPM will invoke E820 interfaces on IA-PC-based legacy systems or the GetMemo-
ryMap() interface on UEFI-enabled systems to obtain a system memory map, System Address Map Interfaces for more
information). As an example, the following memory map represents a typical IA-PC-based legacy platform’s physical
memory map.
Fig. 16.3: Example Physical Memory Map
The names and attributes of the different memory regions are listed below:
•0-640 KB. Compatibility Memory. Application executable memory for an 8086 system.
•640 KB-1 MB. Compatibility Holes. Holes within memory space that allow accesses to be directed to the PC-
compatible frame buffer (A0000h-BFFFFh), to adapter ROM space (C0000h-DFFFFh), and to system platform
ﬁrmware space (E0000h-FFFFFh).
•1 MB-8 MB. Contiguous RAM. An area of contiguous physical memory addresses. Operating systems may
require this memory to be contiguous in order for its loader to load the OS properly on boot up. (No memory-
mapped I/O devices should be mapped into this area.)
•8 MB-Top of Memory1. This area contains memory to the “top of memory1” boundary. In this area, memory-
mapped I/O blocks are possible.
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•Boot Base-4 GB. This area contains the bootstrap ROM.
The platform boot ﬁrmware should decide where the different memory structures belong, and then conﬁgure the E820
handler to return the appropriate values.
For this example, the platform boot ﬁrmware will report the system memory map by E820 as shown in Figure 15-4.
Notice that the memory range from 1 MB to top of memory is marked as system memory, and then a small range is
additionally marked as ACPI reclaim memory. A legacy OS that does not support the E820 extensions will ignore the
extended memory range calls and correctly mark that memory as system memory.
Fig. 16.4: Memory as Conﬁgured after Boot
Also, from the Top of Memory1 to the Top of Memory2, the platform boot ﬁrmware has set aside some memory for
its own use and has marked as reserved both ACPI NVS Memory and Reserved Memory. A legacy OS will throw out
the ACPI NVS Memory and correctly mark this as reserved memory (thus preventing this memory range from being
allocated to any add-in device).
OSPM will call the _PTS control method prior to initiating a sleep (by programming the sleep type, followed by setting
the SLP_EN bit). During a catastrophic failure (where the integrity of the AML code interpreter or driver structure is
questionable), if OSPM decides to shut the system off, it will not issue a _PTS, but will immediately issue a SLP_TYP
of “soft off” and then set the SLP_EN bit, or directly write the HW-reduced ACPI Sleep Type value and the SLP_EN
bit to the Sleep Control Register. Hence, the hardware should not rely solely on the _PTS control method to sequence
the system to the “soft off” state. After waking from an S4 state, OSPM will restore the ACPI NVS memory image
and then issue the _WAK control method that informs platform runtime ﬁrmware that its memory image is back.
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16.3.3 OS Loading
At this point, the platform boot ﬁrmware has passed control to OSPM, either by using OSPM boot loader (a result of
waking from an S4/S5 or boot condition) or OSPM waking vector (a result of waking from an S2 or S3 state). For the
Boot OS Loader path, OSPM will get the system address map via one of the mechanisms describe in System Address
Map Interfaces If OSPM is booting from an S4 state, it will then check the NVS image ﬁle’s hardware signature with
the hardware signature within the FACS table (built by platform boot ﬁrmware) to determine whether it has changed
since entering the sleeping state (indicating that the platforms fundamental hardware conﬁguration has changed during
the current sleeping state). If the signature has changed, OSPM will not restore the system context and can boot from
scratch (from the S4 state). Next, for an S4 wake, OSPM will check the NVS ﬁle to see whether it is valid. If valid,
then OSPM will load the NVS image into system memory. Next, if not a HW-reduced ACPI platform, OSPM will
check the SCI_EN bit and if it is not set, will write the ACPI_ENABLE value to the SMI_CMD register to switch into
the system into ACPI mode and will then reload the memory image from the NVS ﬁle.
If an NVS image ﬁle did not exist, then OSPM loader will load OSPM from scratch. At this point, OSPM will generate
a _WAK call that indicates to the platform runtime ﬁrmware that its ACPI NVS memory image has been successfully
and completely updated.
16.3.4 Exiting ACPI Mode
For machines that do not boot in ACPI mode, ACPI provides a mechanism that enables the OS to disable ACPI. The
following occurs:
1. OSPM unloads all ACPI drivers (including the ACPI driver).
2. OSPM disables all ACPI events.
3. OSPM ﬁnishes using all ACPI registers.
4. OSPM issues an I/O access to the port at the address contained in the SMI_CMD ﬁeld (in the FADT) with the
value contained in the ACPI_DISABLE ﬁeld (in the FADT).
5. Platform runtime ﬁrmware then remaps all SCI events to legacy events and resets the SCI_EN bit.
6. Upon seeing the SCI_EN bit cleared, the ACPI OS enters the legacy OS mode.
When and if the legacy OS returns control to the ACPI OS, if the legacy OS has not maintained the ACPI tables
(in reserved memory and ACPI NVS memory), the ACPI OS will reboot the system to allow the platform runtime
ﬁrmware to re-initialize the tables.
16.3. Initialization 776Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Fig. 16.5: OS Initialization
16.3. Initialization 777CHAPTER
SEVENTEEN
NON-UNIFORM MEMORY ACCESS (NUMA) ARCHITECTURE
PLATFORMS
including processors, memory, and I/O buses, that comprise what is commonly known as a “NUMA node”. Two
or more NUMA nodes are linked to each other via a high-speed interconnect. Processor accesses to memory or I/O
resources within the local NUMA node are generally faster than processor accesses to memory or I/O resources outside
of the local NUMA node, accessed via the node interconnect. ACPI deﬁnes interfaces that allow the platform to convey
In addition, devices such as coherent accelerators, coherent memory devices, or coherent switches can describe their
NUMA characteristics information to OSPM or to system ﬁrmware using the Coherent Device Attribute Table (CDAT)
structures. For more information, see the CDAT reference link at http://ueﬁ.org/acpi, under the heading “Coherent
Device Attribute Table (CDAT) Speciﬁcation”.
17.1 NUMA Node
A conceptual model for a node in a NUMA conﬁguration may contain one or more of the following components:
• Processor
• Memory
• I/O Resources
• Networking, Storage
• Chipset
The components deﬁned as part of the model are intended to represent all possible components of a NUMA node. A
speciﬁc node in an implementation of a NUMA platform may not provide all of these components. At a minimum,
each node must have a chipset with an interface to the interconnect between nodes.
The deﬁning characteristic of a NUMA system is a coherent global memory and/or I/O address space that can be
accessed by all of the processors. Hence, at least one node must have memory, at least one node must have I/O
resources, and at least one node must have processors. Other than the chipset, which must have components present
on every node, each is implementation dependent. In the ACPI namespace, NUMA nodes are described as module
devices. See the Module Device section.
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17.2 System Locality
A collection of components that are presented to OSPM as a Symmetrical Multi-Processing (SMP) unit belong to the

same System Locality, also known as a Proximity Domain. The granularity of a System Locality is typically at the
NUMA Node level although the granularity can also be at the sub-NUMA node level or the processor, memory and
host bridge level.
A System Locality is reported to the OSPM using Proximity Domain entries in the System Resource Afﬁnity Table
(SRAT), or using _PXM (Proximity) methods in the ACPI namespace. If OSPM only needs to know a near/far distinc-
tion among the System Localities, comparing Proximity Domain values is sufﬁcient. See the System Resource Afﬁnity
Table (SRAT) and_PXM (Proximity) sections for more information.
OSPM makes no assumptions about the proximity or nearness of different proximity domains. The difference between
two integers representing separate proximity domains does not imply distance between the proximity domains (in other
words, proximity domain 1 is not assumed to be closer to proximity domain 0 than proximity domain 6).
17.2.1 System Resource Afﬁnity Table Deﬁnition
The optional System Resource Afﬁnity Table (SRAT) provides the boot time description of the processor and memory
ranges belonging to a system locality. OSPM will consume the SRAT only at boot time. For any devices not in the
SRAT, OSPM should use _PXM (Proximity) for them or their ancestors that are hot-added into the system after boot
up.
The SRAT describes the system locality that all processors and memory present in a system belong to at system boot.
This includes memory that can be hot-added (that is memory that can be added to the system while it is running,
without requiring a reboot). OSPM can use this information to optimize the performance of NUMA architecture
systems. For example, OSPM could utilize this information to optimize allocation of memory resources and the
scheduling of software threads.
17.2.2 System Resource Afﬁnity Update
Dynamic migration of the devices may cause the relative system resource afﬁnity information (if the optional SRAT is
present) to change. If this occurs, the System Resource Afﬁnity Update notiﬁcation (Notify event of type 0x0D) may
be generated by the platform to a device at a point on the device tree that represents a System Resource Afﬁnity. This
indicates to OSPM to invoke the _PXM (Proximity) object of the notiﬁed device to update the resource afﬁnity.
17.3 System Locality Distance Information
Optionally, OSPM may further optimize a NUMA architecture system using information about the relative memory
latency distances among the System Localities. This may be useful if the distance between multiple system localities
is signiﬁcantly different. In this case, a simple near/far distinction may be insufﬁcient. This information is contained
in the optional System Locality information Table , and is returned from the evaluation of the _SLI object.
The SLIT is a matrix that describes the relative distances between all System Localities. To include devices that are
not in the System Resource Afﬁnity Table (SRAT), support for the _PXM object is required. The Proximity Domain
values from SRAT, or the values returned by the _PXM objects are used as the row and column indices of the matrix.
Implementation Note : The size of the SLIT is determined by the largest Proximity Domain value used in the system.
Hence, to minimize the size of the SLIT, the Proximity Domain values assigned by the system ﬁrmware should be in
the range 0, . . . , N-1, where N is the number of System Localities. If Proximity Domain values are not packed into
this range, the SLIT will still work, but more memory will have to be allocated to store the “Entries” portion of the
SLIT for the matrix.
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The static SLIT table provides the boot time description of the relative distances among all System Localities. For
hot-added devices and dynamic reconﬁguration of the system localities, the _SLI object must be used for runtime
update.
The _SLI method is an optional object that provides the runtime update of the relative distances from the System
Locality i to all other System Localities in the system. Since _SLI method is providing additional relative distance
information among System Localities, if implemented, it is provided alongside with the _PXM method.
17.3.1 Online Hot Plug
In the case of online device addition, the Bus Check notiﬁcation (0x0) is performed on a device object to indicate to
OSPM that it needs to perform the Plug and Play re-enumeration operation on the device tree starting from the point
where it has been notiﬁed. OSPM needs to evaluate all _PXM objects associated with the added devices, and _SLI
objects if the SLIT is present.
In the case of online device removal, OSPM needs to perform the Plug and Play ejection operation when it receives
the Eject Request notiﬁcation (0x03). OSPM needs to remove the relative distance information from its internal data
structure for the removed devices.
17.3.2 Impact to Existing Localities
Dynamic reconﬁguration of the system may cause the relative distance information (if the optional SLIT is present) to
become stale. If this occurs, the “System Locality Information Update” notiﬁcation (Notify event of type 0xB) may be
generated by the platform to a device at a point on the device tree that represents a System Locality. This indicates to
OSPM that it needs to invoke the _SLI objects associated with the System Localities on the device tree starting from
the point where it has been notiﬁed.
17.4 Heterogeneous Memory Attributes Information
Optionally, OSPM may further optimize a NUMA architecture system using the Heterogeneous Memory Attributes.
This may be useful if the memory latency and bandwidth attributes between system localities is signiﬁcantly different.
In this case, the information is contained in the optional Heterogeneous Memory Attributes (HMAT) and is returned
from the evaluation of the _HMA object.
The HMAT structure describes the latency and bandwidth information between memory access Initiator and memory
Target System Localities. System Locality proximity domain identiﬁers, as deﬁned by Proximity Domain entries in
the System Resource Afﬁnity Table (SRAT), or as returned by _PXM object, are used in the HMAT structure.
Implementation Note : The size of the HMAT table is determined by number of memory initiator System Localities
and the memory target System Localities. The static HMAT table provides the boot time description of the memory
latency and bandwidth among all memory access Initiator and memory Target System Localities. For hot-added
devices and dynamic reconﬁguration of the system localities, the _HMA object must be used for runtime update.
The _HMA method is an optional object that provides the runtime update of the latency and bandwidth from the
memory access Initiator System Locality “i” to all other memory Target System Localities “j” in the system.
Since _HMA method is providing additional memory latency and bandwidth information among System Localities, if
implemented, it is provided alongside with the _PXM method.
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17.4.1 Online Hot Plug
In the case of online device addition, the “Bus Check” notiﬁcation (0x0) is performed on a device object to indicate to
where it has been notiﬁed. OSPM needs to evaluate all _PXM objects associated with the added devices, and _HMA
objects if the HMAT is present.
In the case of online device removal, OSPM needs to perform the Plug and Play ejection operation when it receives the
“Eject Request” notiﬁcation (0x03). OSPM needs to remove the ejected System Localities related information from
its internal data structure for the removed devices.
17.4.2 Impact to Existing Localities
Dynamic reconﬁguration of the system may cause the memory latency and bandwidth information (if the optional
HMAT is present) to become stale. If this occurs, the Heterogeneous Memory Attributes Update notiﬁcation (Notify
event of type 0xE) may be generated by the platform to a device at a point on the device tree that represents a System
Locality. This indicates to OSPM that it needs to invoke the _HMA objects associated with the System Localities on
the device tree starting from the point where it has been notiﬁed.
17.4. Heterogeneous Memory Attributes Information 781CHAPTER
EIGHTEEN
ACPI PLATFORM ERROR INTERFACES (APEI)
This section describes the ACPI Platform Error Interfaces (APEI), which provide a means for a computer platform
to convey error information to OSPM. APEI extends existing hardware error reporting mechanisms and brings them
together as components of a coherent hardware error infrastructure. APEI takes advantage of the additional hardware

EIGHTEEN
error information available in today’s hardware devices, and integrates much more closely with the system ﬁrmware.
As a result, APEI provides the following beneﬁts:
• Allows for more extensive error data to be made available in a standard error record format for determining the
root cause of hardware errors.
• Is extensible, so that as hardware vendors add new and better hardware error reporting mechanisms to their
devices, APEI allows the platform and the OSPM to gracefully accommodate the new mechanisms.
This provides information to help system designers understand basic issues about hardware errors, the relationship
between the ﬁrmware and OSPM, and information about error handling and the APEI architecture components.
APEI consists of four separate tables:
• Error Record Serialization Table (ERST)
• Boot Error Record Table (BERT)
• Hardware Error Source Table (HEST)
• Error Injection Table (EINJ)
18.1 Hardware Errors and Error Sources
A hardware error is a recorded event related to a malfunction of a hardware component in a computer platform.
The hardware components contain error detection mechanisms that detect when a hardware error condition exists.
Hardware errors can be classiﬁed as either corrected errors or uncorrected errors as follows:
• A corrected error is a hardware error condition that has been corrected by the hardware or by the ﬁrmware by
the time the OSPM is notiﬁed about the existence of the error condition.
• An uncorrected error is a hardware error condition that cannot be corrected by the hardware or by the ﬁrmware.
Uncorrected errors are either fatal or non-fatal.
• A fatal hardware error is an uncorrected or uncontained error condition that is determined to be unrecoverable
by the hardware. When a fatal uncorrected error occurs, the system is restarted to prevent propagation of the
error.
• A non-fatal hardware error is an uncorrected error condition from which OSPM can attempt recovery by trying
to correct the error. These are also referred to as correctable or recoverable errors.
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Central to APEI is the concept of a hardware error source. A hardware error source is any hardware unit that alerts
OSPM to the presence of an error condition. Examples of hardware error sources include the following:
• Processor machine check exception (for example, MC#)
• Chipset error message signals (for example, SCI, SMI, SERR#, MCERR#)
• I/O bus error reporting (for example, PCI Express root port error interrupt)
• I/O device errors
A single hardware error source might handle aggregate error reporting for more than one type of hardware error
condition. For example, a processor’s machine check exception typically reports processor errors, cache and memory
errors, and system bus errors.
A hardware error source is typically represented by the following:
• One or more hardware error status registers.
• One or more hardware error conﬁguration or control registers.
• A signaling mechanism to alert OSPM to the existence of an error condition.
In some situations, there is not an explicit signaling mechanism and OSPM must poll the error status registers to
test for an error condition. However, polling can only be used for corrected error conditions since uncorrected errors
require immediate attention by OSPM.
18.2 Relationship between OSPM and System Firmware
Both OSPM and system ﬁrmware play important roles in hardware error handling. APEI improves the methods by
which both of these can contribute to the task of hardware error handling in a complementary fashion. APEI allows
the hardware platform vendor to determine whether the ﬁrmware or OSPM will own key hardware error resources.
APEI also allows the ﬁrmware to pass control of hardware error resources to OSPM when appropriate.
18.3 Error Source Discovery
Platforms enumerate error sources to OSPM via a set of tables that describe the error sources. OSPM may also
support non-ACPI enumerated error sources such as: Machine Check Exception, Corrected Machine Check, NMI,
PCI Express AER, and on Itanium™ Processor Family (IPF) platforms the INIT error source. Non-ACPI error sources
are not described by this speciﬁcation.
During initialization, OSPM examines the tables and uses this information to establish the necessary error handlers
that are responsible for processing error notiﬁcations from the platform.
18.3.1 Boot Error Source
Under normal circumstances, when a hardware error occurs, the error handler receives control and processes the error.
This gives OSPM a chance to process the error condition, report it, and optionally attempt recovery. In some cases, the
system is unable to process an error. For example, system ﬁrmware or a management controller may choose to reset
the system or the system might experience an uncontrolled crash or reset.
The boot error source is used to report unhandled errors that occurred in a previous boot. This mechanism is described
in the BERT table. The boot error source is reported as a ‘one-time polled’ type error source. OSPM queries the boot
error source during boot for any existing boot error records. The platform will report the error condition to OSPM via
a Common Platform Error Record (CPER) compliant error record. The CPER format is described in the appendices
of the UEFI Speciﬁcation.
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The following table describes the format for the Boot Error Record Table (BERT).
Table 18.1: Boot Error Record Table (BERT)
Field Byte length Byte offset Description
Header Signature 4 0 ‘BERT’. Signature for the Boot Error Record Table.
Length 4 4 Length, in bytes, of BERT.
OEM Table ID 8 16 The manufacturer model ID.
OEM Revision 4 24 OEM revision of the BERT for the supplied OEM table ID.
Creator ID 4 28 Vendor ID of the utility that created the table.
Creator Revision 4 32 Revision of the utility that created the table.
Boot Error Region Length 4 36 The length in bytes of the boot error region.
Boot Error Region 8 40 64-bit physical address of the Boot Error Region.
The Boot Error Region is a range of addressable memory that OSPM can access during initialization, to determine if
an unhandled error condition occurred. System ﬁrmware must report this memory range as ﬁrmware reserved. The
format of the Boot Error Region follows that of an Error Status Block, as deﬁned in the Generic Hardware Error
Source Structure . The format of the error status block is described by the Generic Error Status Block table.
For details of some of the ﬁelds listed in the Generic Error Data Entry table, please see the Section Descriptors
deﬁnitions in the the UEFI Speciﬁcation appendices, under the description of the Common Platform Error Record.
18.3.2 ACPI Error Source
The hardware error source describes a standardized mechanism platforms may use to describe their error sources.
Use of this interface is the preferred way for platforms to describe their error sources as it is platform and processor-
architecture independent and allows the platform to describe the operational parameters associated with error sources.
This mechanism allows for the platform to describe error sources in detail; communicating operational parameters (i.e.
severity levels, masking bits, and threshold values) to OSPM as necessary. It also allows the platform to report error
sources for which OSPM would typically not implement support (for example, chipset-speciﬁc error registers).
The Hardware Error Source Table (HEST) provides the platform ﬁrmware a way to describe a system’s hardware error
sources to OSPM. The HEST format is shown in the following table.
Table 18.2: Hardware Error Source Table (HEST)
Field Byte
lengthByte
Header Signature 4 0 “HEST”. Signature for the Hardware Error Source Table.
Length 4 4 Length, in bytes, of entire HEST. Entire table must be contiguous.
OEM Revision 4 24 OEM revision of the HEST for the supplied OEM table ID.
Error Source Count 4 36 The number of error source descriptors.
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Table 18.2 – continued from previous page
Field Byte
Error Source Struc-
ture[n] •40 A series of Error Source Descriptor Entries.
Note: Error source types 3, 4, and 5 are reserved for legacy reasons and must not be used.
Note: Starting with revision 2 of HEST, the Error Source Structures must be sorted in Type ascending order for Error
Source Structure Types of less than 12.

Field Byte
Note: Beginning with error source type 12 and onward, each Error Source Structure must use the standard Error
Source Structure Header as deﬁned in Section 18.3.2.11.
The following sections detail each of the speciﬁc error source descriptors.
18.3.2.1 IA-32 Architecture Machine Check Exception
Processors implementing the IA-32 Instruction Set Architecture employ a machine check exception mechanism to
alert OSPM to the presence of an uncorrected hardware error condition. The information in this table is used by
OSPM to conﬁgure the machine check exception mechanism for each processor in the system.
Only one entry of this type is permitted in the HEST. OSPM applies the information speciﬁed in this entry to all
Table 18.3: IA-32 Architecture Machine Check Exception Structure
Field Byte
Type 2 0 0 - IA-32 Architecture Machine Check Exception Structure.
Source Id 2 2 This value serves to uniquely identify this error source against other error
sources reported by the platform.
Reserved 2 4 Reserved.
Flags 1 6
Bit [0] - FIRMWARE_FIRST: If set, this bit indicates to the OSPM that
the interrupt handler from system ﬁrmware will run ﬁrst for this error
source.
Bit [2] - GHES_ASSIST: If set, this bit indicates that although OSPM is
responsible for directly handling the error (as expected when
FIRMWARE_FIRST is not set), system ﬁrmware may report additional
information in the context of the error reported by hardware. The
additional information is reported in a Generic Hardware Error Source
structure with a matching Related Source ID. See Section 18.7,
GHES_ASSIST Error Reporting . NOTE: If FIRMWARE_FIRST is set,
this bit is reserved.
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Table 18.3 – continued from previous page
Field Byte
Enabled 1 7 Speciﬁes whether MCE is to be enabled. If set to 1, this ﬁeld indicates
this error source is to be enabled. If set to 0, this ﬁeld indicates that the
error source is not to be enabled.
Number of
Records To
Pre-allocate4 8 Indicates the number of error records to pre-allocate for this error source.
Max Sections
Per Record4 12 Indicates the maximum number of error sections included in an error
record created as a result of an error reported by this error source.
Global Capa-
bility Init Data8 16 Indicates the value of the machine check global capability register.
Global Con-
trol Init Data8 24 Indicates the value to be written to the machine check global control reg-
ister.
Number Of
Hardware
Banks1 32 Indicates the number of hardware error reporting banks.
Reserved 7 33 Reserved.
Machine
Check Bank
Structure[n]•40 A list of Machine Check Bank structures deﬁned in the IA-32 Architecture
Machine Check Bank Structure
18.3.2.1.1 IA-32 Architecture Machine Check Bank Structure
This table describes the attributes of a speciﬁc IA-32 architecture machine check hardware error bank.
Table 18.4: IA-32 Architecture Machine Check Error Bank Struc-
ture
Field Byte
Bank Number 1 0 Zero-based index identiﬁes the machine check error bank.
Clear Status
On Initializa-
tion1 1 If set, indicates the status information in this machine check bank is to be
cleared during system initialization as follows: 0 - Clear 1 - Don’t clear
Status Data
Format1 2
Identiﬁes the format of the data in the status register:
0 - IA-32 MCA
1 - Intel® 64 MCA
2 - AMD64MCA All other values are reserved
Reserved 1 3 Reserved.
ister MSR Ad-
dress4 4 Address of the hardware bank’s control MSR. Ignored if zero.
Control Init
Data8 8 This is the value the OSPM will program into the machine check bank’s
control register.
ter MSR Ad-
dress4 16 Address of the hardware bank’s MCi_STAT MSR. Ignored if zero.
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Table 18.4 – continued from previous page
Field Byte
Address Reg-
dress4 20 Address of the hardware bank’s MCi_ADDR MSR. Ignored if zero.
Misc Register
MSR Address4 24 Address of the hardware bank’s MCi_MISC MSR. Ignored if zero.
18.3.2.2 IA-32 Architecture Corrected Machine Check
Processors implementing the IA-32 Instruction Set Architecture may report corrected processor errors to OSPM. The
information in this table allows platform ﬁrmware to communicate key parameters of the corrected processor error
reporting mechanism to OSPM, including whether CMC processing should be enabled.
Table 18.5: IA-32 Architecture Corrected Machine Check Structure
Field Byte
Type 2 0 1 - IA-32 Architecture Corrected Machine Check Structure.
Source Id 2 2 Uniquely identiﬁes the error source.
Reserved 2 4 Reserved
Flags 1 6
source.
All other bits must be set to zero.
Enabled 1 7
If the ﬁeld value is 1, indicates this error source is to be enabled.
If the ﬁeld value is 0, indicates that the error source is not to be enabled.
If FIRMWARE_FIRST is set in the ﬂags ﬁeld, the Enabled ﬁeld is
Number of
Records To
Must be >= 1.
record created as a result of an error reported by this error source. Must
be >= 1.
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Table 18.5 – continued from previous page
Field Byte
Structure28 16 Hardware Error Notiﬁcation Structure as deﬁned in Hardware Error No-
tiﬁcation Structure .
Number Of
Hardware
Banks1 44 The number of hardware error reporting banks.
Reserved 3 45 Reserved.
Machine
Check Bank
Structure[n]•48 A list of Machine Check Bank structures deﬁned in IA-32 Architecture
Machine Check Bank Structure .
18.3.2.3 IA-32 Architecture Non-Maskable Interrupt
Uncorrected platform errors are typically reported using the Non-Maskable Interrupt (NMI) vector (for example, INT
2). This table allows platform ﬁrmware to communicate parameters regarding the conﬁguration and handling of NMI
error conditions.
Only one entry of this type is permitted in the HEST.
Table 18.6: IA-32 Architecture NMI Error Structure
Field Byte
Type 2 0 2 - IA-32 Architecture NMI Structure.
Source Id 2 2 Uniquely identiﬁes this error source.
Reserved 4 4 Must be zero.
Number of
Records To
Pre-allocate4 8 Indicates number of error records to pre-allocate for this error source.
Per Record4 12 Indicates maximum number of error sections included in an error record
created as a result of an error reported by this error source. Must be >= 1.
Max Raw
Data Length4 16 The size in bytes of the NMI error data.
18.3.2.4 PCI Express Root Port AER Structure
PCI Express (PCIe) root ports may implement PCIe Advanced Error Reporting (AER) support. This table contains
information platform ﬁrmware supplies to OSPM for conﬁguring AER support on a given root port.
The HEST may contain one entry of this type for each PCI Express root port if none of the entries has the GLOBAL
ﬂag set. If the GLOBAL ﬂag is set, there may only be one entry of this type and the information contained in that
entry is applied to all PCIe root ports.
Table 18.7: PCI Express Root Port AER Structure
Field Byte
Type 2 0 6 - AER Root Port.
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Table 18.7 – continued from previous page
Field Byte
Flags 1 6
source. This ﬂag does not grant nor deny access to AER registers. OSPM
should evaluate _OSC for PCI hierarchies to determine AER register
ownership.
Bit [1] - GLOBAL: If set, indicates that the settings contained in this

Field Byte
Field Byte
Flags 1 6
structure apply globally to all PCI Express Devices.
Enabled 1 7 If the ﬁeld value is 1, indicates this error source is to be enabled. If the
ﬁeld value is 0, indicates that the error source is not to be enabled. If
FIRMWARE_FIRST is set in the ﬂags ﬁeld, the Enabled ﬁeld is ignored
by the OSPM.
Number of
Records To
Pre-allocate4 8 Indicates the number error records to pre-allocate for this error source.
be >= 1.
Bus 4 16
Identiﬁes the PCI Bus and Segment of the root port.
The Bus is encoded in bits [7:0].
For systems that expose multiple PCI segment groups, the segment
number is encoded in bits [23:8], and bits [31-24] must be zero.
For systems that do not expose multiple PCI segment groups, bits [31:8]
If the GLOBAL ﬂag is speciﬁed, this ﬁeld is ignored.
Device 2 20 Identiﬁes the PCI Device Number of the root port. If the GLOBAL ﬂag is
speciﬁed, this ﬁeld is ignored.
Function 2 22 Identiﬁes the PCI Function number of the root port. If the GLOBAL ﬂag
is speciﬁed, this ﬁeld is ignored.
Device Con-
trol2 24 Device control bits with which to initialize the device.
Reserved 2 26 Must be zero.
Uncorrectable
Error Mask4 28 Value to write to the root port’s Uncorrectable Error Mask register.
Error Severity4 32 Value to write to the root port’s Uncorrectable Error Severity register.
Correctable
Error Mask4 36 Value to write to the root port’s Correctable Error Mask register.
Advanced
Error Capa-
bilities and
Control4 40 Value to write to the root port’s Advanced Error Capabilities and Control
Register.
Root Error
Command4 44 Value to write to the root port’s Root Error Command Register.
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Note: For PCI Express Advanced Error Reporting (AER) resources, ownership and control of AER registers are
determined by the evaluation of the PCI _OSC() method as described in the most current revision of the PCI Firmware
Speciﬁcation. The FIRMWARE_FIRST bit in the Flags Field does not serve to grant, nor deny, access to the AER
registers within the PCI Express device(s) that are described by the structure.
18.3.2.5 PCI Express Device AER Structure
PCI Express devices may implement AER support. This table contains information platform ﬁrmware supplies to
OSPM for conﬁguring AER support on a given PCI Express device.
The HEST may contain one entry of this type for each PCI Express endpoint device if none of the entries has the
GLOBAL ﬂag set. If the GLOBAL ﬂag is set, there may only be one entry of this type and the information contained
in that entry will be applied to all PCI Express endpoint devices.
Table 18.8: PCI Express Device AER Structure
Field Byte
Type 2 0 7 - AER Endpoint.
Flags 1 6
Enabled 1 7
Number of
Records To
be >= 1.
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Table 18.8 – continued from previous page
Field Byte
Bus 4 16
Identiﬁes the PCI Bus and Segment of the device.
number is encoded in bits [23:8], and bits [31:24] must be zero.
For systems that do not expose multiple PCI segment groups, bits 8-31
Device 2 20 Identiﬁes the PCI Device Number of the device. If the GLOBAL ﬂag is
Function 2 22 Identiﬁes the PCI Function Number of the device. If the GLOBAL ﬂag is
Advanced
Register.
18.3.2.6 PCI Express/PCI-X Bridge AER Structure
PCI Express/PCI-X bridges that implement AER support implement ﬁelds that control the behavior how errors are
reported across the bridge.
The HEST may contain one entry of this type for each PCI Express/PCI-X bridges if none of the entries has the
in that entry will be applied to all PCI Express/ PCI-X bridges.
Table 18.9: PCI Express/PCI-X Bridge AER Structure
Field Byte
Type 2 0 8 - AER Bridge.
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Table 18.9 – continued from previous page
Field Byte
Flags 1 6
Enabled 1 7
Number of
Records To
be >= 1.
Bus 4 16
Identiﬁes the PCI Bus and Segment of the bridge.
must be zero. If the GLOBAL ﬂag is speciﬁed, this ﬁeld is ignored.
Device 2 20 Identiﬁes the PCI device number of the bridge. If the GLOBAL ﬂag is
Function 2 22 Identiﬁes the PCI function number of the bridge. If the GLOBAL ﬂag is
Reserved 2 26 This value must be zero.
Error Mask4 28 Value to write to the bridge’s Uncorrectable Error Mask register.
Error Severity4 32 Value to write to the bridge’s Uncorrectable Error Severity register.
Error Mask4 36 Value to write to the bridge’s Correctable Error Mask register.
Advanced
Control4 40 Value to write to the bridge’s Advanced Error Capabilities and Control
Register.
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Field Byte
Secondary

Advanced
Register.
Field Byte
Secondary
Error Mask4 44 Value to write to the bridge’s secondary uncorrectable error mask register.
Secondary
Error Severity4 48 Value to write to the bridge’s secondary uncorrectable error severity reg-
ister.
Secondary
Advanced
and Control4 52 Value to write to the bridge’s secondary advanced capabilities and control
register.
18.3.2.7 Generic Hardware Error Source
The platform may describe a generic hardware error source to OSPM using the Generic Hardware Error Source
structure. A generic hardware error source is an error source that either notiﬁes OSPM of the presence of an error
using a non-standard notiﬁcation mechanism or reports error information that is encoded in a non-standard format.
Using the information in a Generic Hardware Error Source structure, OSPM conﬁgures an error handler to read the
error data from an error status block - a memory range set aside by the platform for recording error status information.
As the generic hardware error source is non-standard, OSPM does not implement built-in support for conﬁguration
and control operations. The error source must be conﬁgured by system ﬁrmware during boot.
Some platforms may describe multiple Generic Hardware Error Source structures with different notiﬁcation types, as
deﬁned in Table 18.10. For example, a platform may describe one error source for the handling of synchronous errors
(e.g. MCE or SEA), and a second source for handling asynchronous errors (e.g. SCI or External Interrupt).
Table 18.10: Generic Hardware Error Source Structure
Field Byte
Type 2 0 9 - Generic Hardware Error Source Structure.
Source Id 2 2 Uniquely identify the error source.
Related
Source ID2 4
This ﬁeld represents the Source ID of an alternate error source for which
the platform:
(a) Requires Firmware-First handling (FIMWARE_FIRST ﬂag is
set on alternate error source). See Section 18.4.
(b) Provides additional information in the context of an error
reported by hardware (GHES_ASSIST ﬂag is set on alternate error
source). See Section 18.7.
If this generic error source does not represent an alternate source, this
ﬁeld must be set to 0xFFFF.
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Table 18.10 – continued from previous page
Field Byte
Flags 1 6 Reserved.
Enabled 1 7
Number of
Records To
be >= 1.
Max Raw
Data Length4 16 Indicates the size in bytes of the error data recorded by this error source.
Error Status
Address12 20 Generic Address Structure as deﬁned in Section 5.2.3.2. This ﬁeld speci-
ﬁes the location of a register that contains the physical address of a block
of memory that holds the error status data for this error source. This
memory range must reside in ﬁrmware reserved memory. OSPM maps
this range into system address space and reads the error status informa-
tion from the mapped address.
Structure28 32 Hardware Error Notiﬁcation Structure as deﬁned in Table 18.14. This
structure speciﬁes how this error source notiﬁes OSPM that an error has
occurred.
Block Length4 60 Identiﬁes the length in bytes of the error status data block.
The Error Status Address ﬁeld speciﬁes the location of an 8-byte memory-mapped register that holds the physical
address of the error status block. This error status block must reside in a memory range reported to OSPM as ﬁrmware
reserved. OSPM maps the error status buffer into system address space in order to read the error data.
18.3.2.7.1 Generic Error Data
The Error Status Block contains the error status information for a given generic error source. OSPM provides an error
handler that formats one or more of these blocks as necessary for the speciﬁc operating system.
The generic error status block includes two levels of information. The top level is a Generic Error Status Block
structure as deﬁned in the following table. The next level is one or more Generic Error Data Entry structures, deﬁned
in the second table below.
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Table 18.11: Generic Error Status Block
Field Byte
Block Status 4 0
Indicates the type of error information reported in the error packet:
Bit [0] - Uncorrectable Error Valid: If set to one, indicates that an
uncorrectable error condition exists.
Bit [1] - Correctable Error Valid: If set to one, indicates that a correctable
error condition exists.
Bit [2] - Multiple Uncorrectable Errors: If set to one, indicates that more
than one uncorrectable errors have been detected.
Bit [3] - Multiple Correctable Errors: If set to one, indicates that more
than one correctable error has been detected.
Bits [13:4] - Error Data Entry Count: This value indicates the number of
Error Data Entries found in the Data section.
Bits [31:14] - Reserved
Raw Data Off-
set4 4 Offset in bytes from the beginning of the Error Status Block to raw error
data. The raw data must follow any Generic Error Data Entries.
Raw Data
Length4 8 Length in bytes of the raw data.
Data Length 4 12 Length in bytes of the generic error data.
Error Severity 4 16
Identiﬁes the error severity of the reported error::
0 - Recoverable
1 - Fatal
3 - None. Note: This is the error severity of the entire event. Each
Generic Error Data Entry also includes its own Error Severity ﬁeld.
Generic Error
Data EntriesData
Length20 The information contained in this ﬁeld is a collection of zero or more
Generic Error Data Entries .
One or more Generic Error Data Entry structures may be recorded in the Generic Error Data Entries ﬁeld of the Generic
Error Status Block structure. This allows the platform to accumulate information for multiple hardware components
related to a given error event. For example, if the generic error source represents an error that occurs on a device on the
secondary side of a PCI Express / PCI-X Bridge, it is useful to record error information from the PCI Express Bridge
and from the PCI-X device. Utilizing two Generic Error Data Entry structures enables this - see Table 18.12 below.
For more details of the ﬁelds described in the following table, see the deﬁnition of Section Descriptors in the UEFI
Speciﬁcation appendix for the Common Platform Error Record.
Table 18.12: Generic Error Data Entry
Field Byte
Section Type 16 0 Identiﬁes the type of error data in this entry. See the Section Type ﬁeld of
the Section Descriptor in the UEFI Speciﬁcation .
Error Severity 4 16 Identiﬁes the severity of the reported error. 0 - Recoverable 1 - Fatal 2 -
Corrected 3 - None
Revision 2 20 The revision number is 0x300. See the Revision ﬁeld of the Section De-
scriptor in the UEFI Speciﬁcation .
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Table 18.12 – continued from previous page
Field Byte
Bits1 22
Identiﬁes whether certain ﬁelds are populated with valid data. This ﬁeld
indicates the validity of the following ﬁelds:
Bit 0 - If 1, the FRUId ﬁeld contains valid information.
Bit 1 - If 1, the FRUString FRU Text ﬁeld contains valid information.
Bit 2 - If 1, the TimeStamp ﬁeld contains valid information.
Bit 7:3 - Reserved, must be zero..
Flags 1 23 Flags describing the error data. See the Flags ﬁeld of the Section Descrip-
tor in the UEFI Speciﬁcation appendix titled “Common Platform Error
Record” .
Error Data
Length4 24 Length in bytes of the generic error data. It is valid to have a Data Length
of zero. This would be used for instance in ﬁrmware-ﬁrst error handling
where the platform reports errors to the OSPM using NMI.
FRU Id 16 28 Identiﬁes the Field Replaceable Unit. See the FRU Id ﬁeld of the Section
Descriptor in the UEFI Speciﬁcation appendix titled “Common Platform
Error Record”.
FRU Text 20 44 Text ﬁeld describing the Field Replaceable Unit. See the FRU Text ﬁeld
of the Section Descriptor in the UEFI Speciﬁcation appendix titled “Com-
mon Platform Error Record”.

Record” .
Error Data
Timestamp 8 64 If marked valid per the validation bits ﬁeld, this ﬁeld correlates to the time
when the error information was collected by the system software and may
not necessarily represent the time of the error event. The timestamp con-
tains the local time in BCD format. See the Timestamp ﬁeld of the Error
Record Header section in the EFI Speciﬁcation appendix titled “Common
Platform Error Record “.
Data Error
Data
Length64 Generic error data. The information contained in this ﬁeld must match
one of the error record section types deﬁned in the UEFI Speciﬁcation
appendix, “Common Platform Error Record”.
18.3.2.7.2 Event Notiﬁcation For Generic Error Sources
An event notiﬁcation is recommended for corrected errors where latency in processing error reports is not critical to
proper system operation. The implementation of Event notiﬁcation requires the platform to deﬁne a device with PNP
ID PNP0C33 in the ACPI namespace, referred to as the error device. This device is used to notify the OSPM that
a generic error source is reporting an error. Since multiple generic error sources can use event notiﬁcation, it is the
responsibility of the OSPM to scan the list of these generic error sources and check the block status ﬁeld ( Generic
Error Status Block ) to identify the source that reported the error.
The platform is responsible for providing a control method that issues a NOTIFY on the error device (PNP0C33), with
a notiﬁcation code of type 0x80.
For traditional ACPI platforms the event signaling follows the model described in Queuing the matching control
method for execution . The platform implements a general purpose event (GPE) for the error notiﬁcation, and the GPE
has an associated control method.
An example of a GPE control method for error notiﬁcation is the following:
Method (\_GPE._L08) { // GPE 8 level error notification
Notify (error_device, 0x80)
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}
For HW-reduced ACPI platforms, the event signaling follows the model described in GPIO-signaled ACPI Events and
Interrupt-signaled ACPI events . The platform implements a notiﬁcation of error events via interrupts or a GPIO pin.
In both cases these are associated with an _EVT control method.
An example of an _EVT control method for GPIO-based error notiﬁcation is the following:
Method (\_EVT) { // GPIO pin 300 error notification
Switch (Arg1) {
}
}
}
The overall ﬂow when the platform uses the event notiﬁcation is:
• The platform enumerates the error source with event as the notiﬁcation method using the format in the Generic
Hardware Error Source Structure and the Generic Error Status Block .
• The platform surfaces an error device, PNP ID PNP0C33, to the OSPM
• When the platform is ready to report an error, the platform populates the error status block including the block
status ﬁeld ( Generic Error Status Block ).
Traditional ACPI platforms signal the error using an SCI, on the appropriate GPE:
• The OSPM evaluates the GPE control method associated with this event as indicated on Queuing the matching
control method for execution
• OSPM responds to this notiﬁcation by checking the error status block of all generic error sources with the SCI
Generic notiﬁcation type to identify the source reporting the error
HW-reduced ACPI platforms signal the error using a GPIO interrupt or another interrupt declared under a generic event
device ( Interrupt-signaled ACPI events ). In the case of GPIO-signaled events, an _AEI object lists the appropriate
GPIO pin, while for Interrupt-signaled events a _CRS object is used to list the interrupt:
• The OSPM evaluates the control method associated with this event as indicated in The Event Method for Han-
dling GPIO Signaled Events andThe Event Method for Handling Interrupt Signaled Events .
• OSPM responds to this notiﬁcation by checking the error status block of all generic error sources with the
GPIO-Signal notiﬁcation or Interrupt-signaled notiﬁcation types to identify the source reporting the error.
18.3.2.8 Generic Hardware Error Source version 2 (GHESv2 - Type 10)
This is an extension to the Generic Hardware Error source structure (Section 18.3.2.7 ) for hardware-reduced plat-
forms that rely on RAS controllers for generation of generic error records. A RAS controller may be a hardware or
ﬁrmware entity that may execute in parallel with OS execution (e.g., a RAS controller may be ﬁrmware running on
an independent microcontroller, or it could be in the form of platform ﬁrmware that runs on one of the application
processors). Platforms with RAS controllers must prevent concurrent accesses to the Error Status Block (i.e., the RAS
controller must not overwrite the Error Status Block before the OS has completed reading it). The table below provides
a high-level example of how the RAS controller might interact with the OS.
For GHESv2 error sources, the OSPM must acknowledge the consumption of the Error Status Block by writing to the
“Read Ack Register” listed in the GHESv2 structure (described in the following table). For platforms that describe
multiple Generic Hardware Error Sources, the platform must provide a unique memory region for the Error Status
Block of each error source.
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Fig. 18.1: APEI error ﬂow example with external RAS controller
Table 18.13: Generic Hardware Error Source version 2 (GHESv2)
Structure
Name Byte
Type 2 0 10 - Generic Hardware Error Source (version 2) structure
Equivalent ﬁelds in Table
18.1062 2 Same format as ﬁelds in Table 18.10, starting from Source Id
and ending in Error Status Block Length (inclusive).
Read Ack Register 12 64 Generic Address Structure as deﬁned in Table 18.10. This
ﬁeld speciﬁes the location of the Read Ack Register used to
notify the RAS controller that OSPM has processed the Error
Status Block. The OSPM writes the bit(s) speciﬁed in Read
Ack Write, while preserving the bit(s) speciﬁed in Read Ack
Preserve.
Read Ack Preserve 8 76 Contains a mask of bits to preserve when writing the Read
Ack register.
Read Ack Write 8 84 Contains a mask of bits to set when writing the Read Ack
register.
These are the steps the OS must take once detecting an error from a particular GHESv2 error source:
• OSPM detects error (via interrupt/exception or polling the block status)
• OSPM copies the error status block
• OSPM clears the block status ﬁeld of the error status block
• OSPM acknowledges the error via Read Ack register. For example:
–OSPM reads the Read Ack register –> X
–OSPM writes –> (( X & ReadAckPreserve) | ReadAckWrite)
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18.3.2.9 Hardware Error Notiﬁcation
This table describes the notiﬁcation mechanism associated with a hardware error source.
Table 18.14: Hardware Error Notiﬁcation Structure
Field Byte
Type 1 0
Identiﬁes the notiﬁcation type:
0 - Polled
1 - External Interrupt
2 - Local Interrupt
3 - SCI
4 - NMI
5 - CMCI
6 - MCE
7 - GPIO-Signal
8 - ARMv8 SEA
9 - ARMv8 SEI
10 - External Interrupt - GSIV
11 - Software Delegated Exception. For deﬁnitions of the
ﬁelds in this structure for this type, see Links to
ACPI-Related Documents (http://ueﬁ.org/acpi) under the
heading, “SDEI Speciﬁcation.”
Length 1 1 Total length of the structure in bytes.
Conﬁguration Write En-
able2 2
This ﬁeld indicates whether conﬁguration parameters may be
modiﬁed by OSPM. If the bit for the associated parameter is
set, the parameter is writeable by OSPM:
Bit [0]: Type
Bit [1]: Poll Interval
Bit [2]: Switch To Polling Threshold Value
Bit [3]: Switch To Polling Threshold Window
Bit [4]: Error Threshold Value
Bit [5]: Error Threshold Window All other bits are reserved.
Poll Interval 4 4 Indicates the poll interval in milliseconds OSPM should use
to periodically check the error source for the presence of an
error condition.
Vector 4 8 Interrupt vector. For type 10 “External Interrupt - GSIV”, this
ﬁeld speciﬁes the GSIV triggered by the error source. For
type 11 “Software Delegated Exception,” this ﬁeld speciﬁes
the SDEI event number (see the SDEI Speciﬁcation).
Switch To Polling Thresh-
old Value4 12 The number of error interrupts that must occur within Switch
To Polling Threshold Interval before OSPM switches the error
source to polled mode.
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Table 18.14 – continued from previous page
old Window4 16 Indicates the time interval in milliseconds that Switch To
Polling Threshold Value interrupts must occur within before
OSPM switches the error source to polled mode.

Error Threshold Value 4 20 Indicates the number of error events that must occur within
Error Threshold Interval before OSPM processes the event as
an error condition.
Error Threshold Window 4 24 Indicates the time interval in milliseconds that Error Thresh-
old Value errors must occur within before OSPM processes
the event as an error condition.
18.3.2.10 IA-32 Architecture Deferred Machine Check
Processors implementing the IA-32 Instruction Set Architecture may report Deferred errors to OSPM. These errors
indicate that data has been corrupted but not consumed. The information in this table allows platform ﬁrmware
to communicate key parameters of the deferred processor error reporting mechanism to OSPM, including whether
Deferred Machine Check (DMC) processing should be enabled.
Table 18.15: IA-32 Architecture Deferred Machine Check Structure
Field Byte
Type 2 0 11 - IA-32 Architecture Deferred Machine Check Structure.
Source Id 2 2 This value serves to uniquely identify this error source against
other error sources reported by the platform.
Flags 1 6
Bit [0] - FIRMWARE_FIRST: If set, this bit indicates to the
OSPM that the interrupt handler from system ﬁrmware will
run ﬁrst for this error source.
Bit [2] - GHES_ASSIST: If set, this bit indicates that
although OSPM is responsible for directly handling the error
(as expected when FIRMWARE_FIRST is not set), system
ﬁrmware may report additional information in the context of
the error reported by hardware. The additional information is
reported in a Generic Hardware Error Source structure with a
matching Related Source ID. See Section 18.7,
GHES_ASSIST Error Reporting . NOTE: If
FIRMWARE_FIRST is set, this bit is reserved.
Enabled 1 7
If the ﬁeld value is 1, indicates this error source is to be
enabled.
If the ﬁeld value is 0, indicates that the error source is not to
be enabled.
If FIRMWARE_FIRST is set in the ﬂags ﬁeld, the Enabled
ﬁeld is ignored by OSPM.
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Table 18.15 – continued from previous page
Field Byte
Number of Records To
Pre-allocate4 8 Indicates the number of error records to pre-allocate for this
error source. Must be >= 1.
Max Sections Per Record 4 12 Indicates the maximum number of error sections included in
an error record created as a result of an error reported by this
Notiﬁcation Structure 28 16 Hardware Error Notiﬁcation Structure, as deﬁned in Table
18.14.
Number Of Hardware
Banks1 44 Indicates the number of hardware error reporting banks.
Machine Check Bank
Structure[n] •48 A list of Machine Check Bank structures deﬁned in IA-32 Ar-
chitecture Machine Check Bank Structure .
18.3.2.11 Error Source Structure Header (Type 12 Onward)
Beginning with error source type 12 and onward, each Error Source Structure must use the standard Error Source
Structure Header as deﬁned below.
Table 18.16: Error Source Structure Header (Type 12 and Onward)
Type 2 0 Error Type
Error Source Structure
Length2 2 The length of the error source structure in bytes
18.4 Firmware First Error Handling
It may be necessary for the platform to process certain classes of errors in ﬁrmware before relinquishing control to
OSPM for further error handling. Errata management and error containment are two examples where ﬁrmware-ﬁrst
error handling is beneﬁcial. Generic hardware error sources support this model through the related source ID.
The platform reports the original error source to OSPM via the hardware error source table (HEST) and sets the
FIRMWAREFIRST ﬂag for this error source. In addition, the platform must report a generic error source with a
related source ID set to the original source ID. This generic error source is used to notify OSPM of the errors on the
original source and their status after the ﬁrmware ﬁrst handling.
There are different notiﬁcation strategies that can be used in ﬁrmware ﬁrst handling; the following options are available
to the platform:
• Traditional ACPI platforms may use NMI to notify the OSPM of both corrected and uncorrected errors for a
given error source
• Traditional ACPI platforms may use NMI to report uncorrected errors and the SCI to report corrected errors
• Traditional ACPI platforms may use NMI to report uncorrected errors and polling to notify the OSPM of cor-
rected errors
• HW-reduced ACPI platforms may use GPIO-signaled events, Interrupt-signaled events, or polling to report
corrected errors.
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18.4.1 Example: Firmware First Handling Using NMI Notiﬁcation
If the platform chooses to use NMI to report errors, which is the recommended method for uncorrected errors, the
platform follows these steps:
1. System ﬁrmware conﬁgures the platform to trigger a ﬁrmware handler when the error occurs
2. System ﬁrmware identiﬁes the error source for which it will handle errors via the error source enumeration
interface by setting the FIRMWARE_FIRST ﬂag
3. System ﬁrmware describes the generic error source, and the associated error status block, as described in Generic
Hardware Error Source . System ﬁrmware identiﬁes the relation between the generic error sourcde and the
original error source by using the original source ID in the related source ID of Generic Hardware Error Source
Structure .
4. When a hardware error reported by the error source occurs, system ﬁrmware gains control and handles the error
condition as required. Upon completion system ﬁrmware should do the following:
5. Extract the error information from the error source and ﬁll in the error information in the data block of the
generic error source it identiﬁed as an alternate in step 3. The error information format follows the speciﬁcation
inGeneric Error Data
6. Set the appropriate bit in the block status ﬁeld ( Generic Error Status Block ) to indicate to the OSPM that a valid
error condition is present.
7. Clears error state from the hardware.
8. Generates an NMI.
At this point, the OSPM NMI handler scans the list of generic error sources to ﬁnd the error source that reported the
error and processes the error report
18.5 Error Serialization
• The error record serialization feature is used to save and retrieve hardware error information to and from a
persistent store. OSPM interacts with the platform through a platform interface. If the Error Record Serialization
Table (ERST) is present, OSPM uses the ACPI solution described below. Otherwise, OSPM uses the UEFI
runtime variable services to carry out error record persistence operations on UEFI based platforms.
• For error persistence across boots, the platform must implement some form of non-volatile store to save error
records. The amount of space required depends on the platform’s processor architecture. Typically, this store
will be ﬂash memory or some other form of non-volatile RAM.
• Serialized errors are encoded according to the Common Platform Error Record (CPER) format, which is de-
scribed in the appendices of the UEFI Speciﬁcation. These entries are referred to as error records.
• The Error Record Serialization Interface is designed to be sufﬁciently abstract to allow hardware vendors ﬂexi-
bility in how they implement their error record serialization hardware. The platform provides details necessary
to communicate with its serialization hardware by populating the ERST with a set of Serialization Instruction
Entries. One or more serialization instruction entries comprise a Serialization Action. OSPM carries out se-
rialization operations by executing a series of Serialization Actions. Serialization Actions and Serialization
Instructions are described in detail in the following sections.
The following table details the ERST layout, which system ﬁrmware is responsible for building.
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Table 18.17: Error Record Serialization Table (ERST)
Field Byte
ACPI Standard Header
Header Signature 4 0 “ERST”. Signature for the Error Record Serialization
Table.
Length 4 4 Length, in bytes, of entire ERST. Entire table must be
contiguous.
OEM Revision 4 24 OEM revision of the ERST for the supplied OEM table
ID.
Serialization Header
Serialization Header Size 4 36 Length in bytes of the serialization header.
Reserved 4 40 Must be zero.

Field Byte
Table.
ID.
Instruction Entry Count 4 44 The number of Serialization Instruction Entries in the-
Serialization Action Table.
Serialization Action Table
Serialization Instruction Entries 48 A series of error logging instruction entries.
18.5.1 Serialization Action Table
A Serialization Action is deﬁned as a series of Serialization Instructions on registers that result in a well known action.
A Serialization Instruction is a Serialization Action primitive and consists of either reading or writing an abstracted
hardware register. The Serialization Action Table contains Serialization Instruction Entries for all the Serialization
Actions the platform supports.
In most cases, a Serialization Action comprises only one Serialization Instruction, but it is conceivable that a more
complex device will require more than one Serialization Instruction. When an action does comprise more than one
instruction, the instructions must be listed consecutively and they will consequently be performed sequentially, ac-
cording to their placement in the Serialization Action Table.
18.5.1.1 Serialization Actions
This section identiﬁes the Serialization Actions that comprise the Error Record Serialization interface, as shown in the
Table 18.18: Error Record Serialization Actions
Value Name Description
0x0 BEGIN_WRITE_OPERATION Indicates to the platform that an error record write op-
eration is beginning. This allows the platform to set its
operational context.
0x1 BEGIN_READ_OPERATION Indicates to the platform that an error record read op-
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Table 18.18 – continued from previous page
0x2 BEGIN_CLEAR_OPERATION Indicates to the platform that an error record clear op-
operation context.
0x3 END_OPERATION Indicates to the platform that the current error record
operation has ended. This allows the platform to clear
its operational context.
0x4 SET_RECORD_OFFSET Sets the offset from the base of the Error Log to transfer
an error record.
0x5 EXECUTE_OPERATION Instructs the platform to carry out the current operation
based on the current operational context.
0x6 CHECK_BUSY_STATUS Returns the state of the current operation. Once
an operation has been executed through the EXE-
CUTE_OPERATION action, the platform is required
to return an indication that the operation is in progress
until the operation completes. This allows the OS
to poll for completion by repeatedly executing the
CHECK_BUSY_STATUS action until the platform in-
dicates that the operation not busy.
0x7 GET_COMMAND_STATUS Returns the status of the current operation. The platform
is expected to maintain a status code for each operation.
Bits [8:1] of the value returned from the Register Re-
gion indicate the command status, which requires that
the Bit Offset of the GAS for the Register Region is set
to 1. See Command-Status-Deﬁnition for a list of valid
command status codes.
0x8 GET_RECORD_IDENTIFIER Returns the record identiﬁer of an existing error record
on the persistent store. The error record identiﬁer is a
64-bit unsigned value as deﬁned in the appendices of
the UEFI Speciﬁcation. If the record store is empty, this
action must return 0xFFFFFFFFFFFFFFFF.
0x9 SET_RECORD_IDENTIFIER Sets the record identiﬁer. The error record identiﬁer is
a 64-bit unsigned value as deﬁned in the appendices of
the UEFI Speciﬁcation.
0xA GET_RECORD_COUNT Retrieves the number of error records currently stored
on the platforms persistent store. The platform is ex-
pected to maintain a count of the number of error
records resident in its persistent store.
0xB BEGIN_DUMMY_WRITE-
_OPERATIONIndicates to the platform that a dummy error record
write operation is beginning. This allows the platform
to set its operational context. A dummy error record
write operation performs no actual transfer of informa-
tion from the Error Log Address Range to the persistent
store.
0xC RESERVED Reserved.
0xD GET_ERROR_LOG-
_ADDRESS_RANGEReturns the 64-bit physical address OSPM uses as the
buffer for reading/writing error records.
0xE GET_ERROR_LOG-
_ADDRESS_RANGE_LENGTHReturns the length in bytes of the Error Log Address
Range
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0xF GET_ERROR_LOG-
_ADDRESS_RANGE_ATTRIBUTES Returns attributes that describe the behavior of the
error log address range:
Bit [0] (0x1) - Reserved.
Bit [1] (0x2) - Non-V olatile: Indicates that the error log
address range is in non-volatile RAM.
Bit [2] (0x4) - Slow: Indicates that the memory in
which the error log address range is locates has slow
access times.
All other bits reserved.
0x10 GET_EXECUTE-
_OPERATION_TIMINGS Returns an encoded QWORD:
[63:32] value in microseconds that the platform expects
would be the maximum amount of time it will take to
process and complete an EXECUTE_OPERATION.
[31:0] value in microseconds that the platform expects
would be the nominal amount of time it will take to
The following table deﬁnes the serialization action status codes returned from GET_COMMAND_STATUS.
Table 18.19: Command Status Deﬁnition
0x00 Success
0x01 Not Enough Space
0x02 Hardware Not Available
0x03 Failed
0x04 Record Store Empty
0x05 Record Not Found
18.5.1.2 Serialization Instruction Entries
Each Serialization Action consists of a series of one or more Serialization Instructions. A Serialization Instruction
represents a primitive operation on an abstracted hardware register represented by the register region as deﬁned in a
Serialization Instruction Entry.
A Serialization Instruction Entry describes a region in a serialization hardware register and the serialization instruction
to be performed on that region. The following table details the layout of a Serialization Instruction Entry.
Table 18.20: Serialization Instruction Entry
Field Byte
Serialization Action 1 N+0 The serialization action that this serialization instruction is a part of.
Instruction 1 N+1 Identiﬁes the instruction to execute. See the Serialization Instruc-
tions table for a list of valid serialization instructions.
Flags 1 N+2 Flags that qualify the instruction.
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Table 18.20 – continued from previous page
Field Byte
Reserved 1 N+3 Must be zero.
Register Region 12 N+4 Generic Address Structure as deﬁned in Section 5.2.3.2 to describe
the address and bit.
Value 8 N+16 Value used with READ_REGISTER_V ALUE and
WRITE_REGISTER_V ALUE instructions.
Mask 8 N+24 The bit mask required to obtain the bits corresponding to the serial-
ization instruction in a given bit range deﬁned by the register region.
Register Region is described as a generic address structure. This structure describes the physical address of a register
as well as the bit range that corresponds to a desired region of the register. The bit range is deﬁned as the smallest
set of consecutive bits that contains every bit in the register that is associated with the Serialization Instruction. If bits
[6:5] and bits [3:2] all correspond to a Serialization Instruction, the bit range for that instruction would be [6:2].
Because a bit range could contain bits that do not pertain to a particular Serialization Instruction (i.e. bit 4 in the
example above), a bit mask is required to distinguish all the bits in the region that correspond to the instruction. The
Mask ﬁeld is deﬁned to be this bit mask with a bit set to ‘1’ for each bit in the bit range (deﬁned by the register region)
corresponding to the Serialization Instruction. Note that bit 0 of the bit mask corresponds to the lowest bit in the bit
range. In the example used above, the mask would be 11011b or 0x1B.
The Instruction ﬁeld identiﬁes the operation to be performed on the register region by the instruction entry. The
following table identiﬁes the instructions that are supported.
Table 18.21: Serialization Instructions
0x00 READ_REGISTER A READ_REGISTER instruction reads the designated
information from the speciﬁed Register Region.
0x01 READ_REGISTER_V ALUE A READ_REGISTER_V ALUE instruction reads the
designated information from the speciﬁed Register Re-
gion and compares the results with the contents of the
Value ﬁeld. If the information read matches the con-
tents of the Value ﬁeld, TRUE is returned, else FALSE
0x02 WRITE_REGISTER A WRITE_REGISTER instruction writes a value to the
speciﬁed Register Region. The Value ﬁeld is ignored.

0x03 WRITE_REGISTER_V ALUE A WRITE_REGISTER_V ALUE instruction writes the
contents of the Value ﬁeld to the speciﬁed Register Re-
gion.
0x04 NOOP This instruction is a NOOP.
0x05 LOAD_V AR1 Loads the V AR1 variable from the register region.
0x06 LOAD_V AR2 Loads the V AR2 variable from the register region.
0x07 STORE_V AR1 Stores the value in V AR1 to the indicate register region.
0x08 ADD Adds V AR1 and V AR2 and stores the result in V AR1.
0x09 SUBTRACT Subtracts V AR1 from V AR2 and stores the result in
V AR1.
0x0A ADD_V ALUE Adds the contents of the speciﬁed register region to
Value and stores the result in the register region.
0x0B SUBTRACT_V ALUE Subtracts Value from the contents of the speciﬁed regis-
ter region and stores the result in the register region.
0x0C STALL Stall for the number of microseconds speciﬁed in Value.
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Table 18.21 – continued from previous page
0x0D STALL_WHILE_TRUE OSPM continually compares the contents of the spec-
iﬁed register region to Value until the values are not
equal. OSPM stalls between each successive compar-
ison. The amount of time to stall is speciﬁed by V AR1
and is expressed in microseconds.
0x0E SKIP_NEXT_INSTRUCTION_IF_TRUE This is a control instruction which compares the con-
tents of the register region with Value. If the values
match, OSPM skips the next instruction in the sequence
for the current action.
0x0F GOTO OSPM will go to the instruction speciﬁed by Value. The
instruction is speciﬁed as the zero-based index. Each
instruction for a given action has an index based on its
relative position in the array of instructions for the ac-
tion.
0x10 SET_SRC_ADDRESS_BASE Sets the SRC_BASE variable used by the
MOVE_DATA instruction to the contents of the
register region.
0x11 SET_DST_ADDRESS_BASE Sets the DST_BASE variable used by the
0x12 MOVE_DATA Moves V AR2 bytes of data from SRC_BASE + Offset
to DST_BASE + Offset, where Offset is the contents of
the register region.
The Flags ﬁeld allows qualifying ﬂags to be associated with the instruction. The following table identiﬁes the ﬂags
that can be associated with Serialization Instructions.
Table 18.22: Instruction Flags
0x01 PRESERVE_REGISTER For WRITE_REGISTER and WRITE_REGISTER_V ALUE instructions,
this ﬂag indicates that bits within the register that are not being written
must be preserved rather than destroyed. For READ_REGISTER instruc-
tions, this ﬂag is ignored.
18.5.1.2.1 READ_REGISTER_VALUE
A read register value instruction reads the register region and compares the result with the speciﬁed value. If the values
are not equal, the instruction failed. This can be described in pseudo code as follows:
X = Read(register)
X = X >> Bit Offset described inRegister Region
X = X & Mask
If (X != Value) FAIL
SUCCEED
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18.5.1.2.2 READ_REGISTER
A read register instruction reads the register region. The result is a generic value and should not be compared with
Value. Value will be ignored. This can be described in pseudo code as follows:
X = X & Mask
Return X
18.5.1.2.3 WRITE_REGISTER_VALUE
A write register value instruction writes the speciﬁed value to the register region. If PRESERVE_REGISTER is set
in Instruction Flags, then the bits not corresponding to the write value instruction are preserved. If the register is
preserved, the write value instruction requires a read of the register. This can be described in pseudo code as follows:
X = Value & Mask
X = X << Bit Offset described inRegister Region
If (Preserve Register)
Y = Read(register)
Y = Y & ~(Mask << Bit Offset)
X = X \| Y
Write(X, Register)
18.5.1.2.4 WRITE_REGISTER
A write register instruction writes a value to the register region. Value will be ignored. If PRESERVE_REGISTER
is set in Instruction Flags, then the bits not corresponding to the write instruction are preserved. If the register is
X = supplied value
X = X & Mask
X = X \| Y
18.5.1.3 Error Record Serialization Information
The APEI error record includes an 8 byte ﬁeld called OSPM Reserved. The following table deﬁnes the layout of this
ﬁeld. The error record serialization information is a small buffer the platform can use for serialization bookkeeping.
The platform is free to use the 48 bits starting at bit offset 16 for its own purposes. It may use these bits to indicate the
busy/free status of an error record, to record an internal identiﬁer, etc.
Table 18.23: Error Record Serialization Info
Field Bit Length Bit Offset Description
Signature 16 0 16-bit signature (‘ER’) identifying the start of the
error record serialization data.
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Table 18.23 – continued from previous page
Platform Serialization
Data48 16 Platform private error record serialization infor-
mation.
18.5.2 Operations
The error record serialization interface comprises three operations: Write, Read, and Clear. OSPM uses the Write
operation to write a single error record to the persistent store. The Read operation is used to retrieve a single error
record previously recorded to the persistent store using the write operation. The Clear operation allows OSPM to
notify the platform that a given error record has been fully processed and is no longer needed, allowing the platform
to recover the storage associated with a cleared error record.
Where the Error Log Address Range is NVRAM, signiﬁcant optimizations are possible since transfer from the Error
Log Address Range to a separate storage device is unnecessary. The platform may still, however, copy the record
from NVRAM to another device, should it choose to. This allows, for example, the platform to copy error records
to private log ﬁles. In order to give the platform the opportunity to do this, OSPM must use the Write operation to
persist error records even when the Error Log Address Range is NVRAM. The Read and Clear operations, however,
are unnecessary in this case as OSPM is capable of reading and clearing error records without assistance from the
platform.
18.5.2.1 Writing
To write a single HW error record, OSPM executes the following steps:
1. Initializes the error record’s serialization info. OSPM must ﬁll in the Signature.
2. Writes the error record to be persisted into the Error Log Address Range.
3. Executes the BEGIN_WRITE_OPERATION action to notify the platform that a record write operation is be-
ginning.
4. Executes the SET_RECORD_OFFSET action to inform the platform where in the
5. Error Log Address Range the error record resides.
6. Executes the EXECUTE_OPERATION action to instruct the platform to begin the write operation.
7. Busy waits by continually executing CHECK_BUSY_STATUS action until FALSE is returned.
8. Executes a GET_COMMAND_STATUS action to determine the status of the write operation. If an error is
indicated, the OS
9. PM may retry the operation.
10. Executes an END_OPERATION action to notify the platform that the record write operation is complete.
When OSPM performs the EXECUTE_OPERATION action in the context of a record write operation, the platform
attempts to transfer the error record from the designated offset in the Error Log Address Range to a persistent store of
its choice. If the Error Log Address Range is non-volatile RAM, no transfer is required.
Where the platform is required to transfer the error record from the Error Log Address Range to a persistent store, it
performs the following steps in response to receiving a write command:
1. Sets some internal state to indicate that it is busy. OSPM polls by executing a CHECK_BUSY_STATUS action
until the operation is completed.
2. Reads the error record’s Record ID ﬁeld to determine where on the storage medium the supplied error record is
to be written. The platform attempts to locate the speciﬁed error record on the persistent store.
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• If the speciﬁed error record does not exist, the platform attempts to write a new record to the persistent
store.
• If the speciﬁed error record does exists, then if the existing error record is large enough to be overwritten
by the supplied error record, the platform can do an in-place replacement. If the existing record is not large

store.
enough to be overwritten, the platform must attempt to locate space in which to write the new record. It
may mark the existing record as Free and coalesce adjacent free records in order to create the necessary
space.
3. Transfers the error record to the selected location on the persistent store.
4. Updates an internal Record Count if a new record was written.
5. Records the status of the operation so OSPM can retrieve the status by executing a GET_COMMAND_STATUS
action.
6. Modiﬁes internal busy state as necessary so when OS PM executes CHECK_BUSY_STATUS, the result indi-
cates that the operation is complete.
If the Error Log Address Range resides in NVRAM, the minimum steps required of the platform are:
1. Sets some internal state to indication that it is busy. OSPM polls by executing a CHECK_BUSY_STATUS
action until the operation is completed.
2. Records the status of the operation so OSPM can retrieve the status by executing a GET_COMMAND_STATUS
action.
3. Clear internal busy state so when OS PM executes CHECK_BUSY_STATUS, the result indicates that the oper-
ation is complete.
18.5.2.2 Reading
During boot, OSPM attempts to retrieve all serialized error records from the persistent store. If the Error Log Address
Range does not reside in NVRAM, the following steps are executed by OSPM to retrieve all error records:
1. Executes the BEGIN_ READ_OPERATION action to notify the platform that a record read operation is begin-
ning.
2. Executes the SET_ RECORD_OFFSET action to inform the platform at what offset in the Error Log Address
Range the error record is to be transferred.
3. Executes the SET_RECORD_IDENTIFER action to inform the platform which error record is to be read from
its persistent store.
4. Executes the EXECUTE_OPERATION action to instruct the platform to begin the read operation.
5. Busy waits by continually executing CHECK_BUSY_STATUS action until FALSE is returned.
6. Executes a GET_COMMAND_STATUS action to determine the status of the read operation.
• If the status is Record Store Empty (0x04), continue to step 7.
• If an error occurred reading a valid error record, the status will be Failed (0x03), continue to step 7.
• If the status is Record Not Found (0x05), indicating that the speciﬁed error record does not exist, OSPM
retrieves a valid identiﬁer by executing a GET_RECORD_IDENTIFIER action. The platform will return
a valid record identiﬁer.
• If the status is Success, OSPM transfers the retrieved record from the Error Log Address Range to a private
buffer and then executes the GET_RECORD_IDENTIFIER action to determine the identiﬁer of the next
record in the persistent store.
7. Execute an END_OPERATION to notify the platform that the record read operation is complete.
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The steps performed by the platform to carry out a read request are as follows:
2. Using the record identiﬁer supplied by OSPM through the SET_RECORD_IDENTIFIER operation, determine
which error record to read:
• If the identiﬁer is 0x0 (unspeciﬁed), the platform reads the ‘ﬁrst’ error record from its persistent store (ﬁrst
being implementation speciﬁc).
• If the identiﬁer is non-zero, the platform attempts to locate the speciﬁed error record on the persistent store.
• If the speciﬁed error record does not exist, set the status register’s Status to Record Not Found (0x05), and
update the status register’s Identiﬁer ﬁeld with the identiﬁer of the ‘ﬁrst’ error record.
3. Transfer the record from the persistent store to the offset speciﬁed by OSPM from the base of the Error Log
Address Range.
4. Record the Identiﬁer of the ‘next’ valid error record that resides on the persistent store. This allows OSPM to
retrieve a valid record identiﬁer by executing a GET_RECORD_IDENTIFIER operation.
5. Record the status of the operation so OSPM can retrieve the status by executing a GET_COMMAND_STATUS
action.
6. Clear internal busy state so when OSPM executes CHECK_BUSY_STATUS, the result indicates that the oper-
Where the Error Log Address Range does reside in NVRAM, OSPM requires no platform support to read persisted
error records. OSPM can scan the Error Log Address Range on its own and retrieve the error records it previously
persisted.
18.5.2.3 Clearing
After OSPM has ﬁnished processing an error record, it will notify the platform by clearing the record. This allows the
platform to delete the record from the persistent store or mark it such that the space is free and can be reused. The
following steps are executed by OSPM to clear an error record:
1. Executes a BEGIN_ CLEAR_OPERATION action to notify the platform that a record clear operation is begin-
ning.
2. Executes a SET_RECORD_IDENTIFER action to inform the platform which error record is to be cleared. This
value must not be set to 0x0 (unspeciﬁed).
3. Executes an EXECUTE_OPERATION action to instruct the platform to begin the clear operation.
4. Busy waits by continually executing CHECK_BUSY_STATUS action until FALSE is returned.
5. Executes a GET_COMMAND_STATUS action to determine the status of the clear operation.
6. Execute an END_OPERATION to notify the platform that the record read operation is complete.
The platform carries out a clear request by performing the following steps:
which error record to clear. This value may not be 0x0 (unspeciﬁed).
3. Locate the speciﬁed error record on the persistent store.
4. Mark the record as free by updating the Attributes in its serialization header.
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5. Update internal record count.
6. Clear internal busy state so when OS PM executes CHECK_BUSY_STATUS, the result indicates that the oper-
When the Error Log Address Range resides in NVRAM, the OS requires no platform support to Clear error records.
18.5.2.4 Usage
This section describes several possible ways the error record serialization mechanism might be implemented.
18.5.2.4.1 Error Log Address Range Resides in NVRAM
If the Error Log Address Range resides in NVRAM, then when OSPM writes a record into the logging range, the
record is automatically persistent and the busy bit can be cleared immediately. On a subsequent boot, OSPM can read
any persisted error records directly from the persistent store range. The size of the persistent store, in this case, is
expected to be enough for several error records.
18.5.2.4.2 Error Log Address Range Resides in (volatile) RAM
In this implementation, the Error Log Address Range describes an intermediate location for error records. To persist
a record, OSPM copies the record into the Error Log Address Range and sets the Execute, at which time the platform
runs necessary code (SMM code on non-UEFI based systems and UEFI runtime code on UEFI-enabled systems) to
transfer the error record from main memory to some persistent store. To read a record, OSPM asks the platform to
copy a record from the persistent store to a speciﬁed offset within the Error Log Address Range. The size of the Error
Log Address Range is at least large enough for one error record.
18.5.2.4.3 Error Log Address Range Resides on Service Processor
In this type of implementation, the Error Log Address Range is really MMIO. When OSPM writes an error record to
the Error Log Address Range, it is really writing to memory on a service processor. When the OSPM sets the Execute
control bit, the platform knows that the OSPM is done writing the record and can do something with it, like move
it into a permanent location (i.e. hard disk) on the service processor. The size of the persistent store in this type of
implementation is typically large enough for one error record.
18.5.2.4.4 Error Log Address Range is Copied Across Network
In this type of implementation, the Error Log Address Range is an intermediate cache for error records. To persist
an error record, OSPM copies the record into the Error Log Address Range and set the Execute control bit, and the
platform runs code to transmit this error record over the wire. The size of the Error Log Address Range in this type of
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18.6 Error Injection
This section outlines an ACPI table mechanism, called EINJ, which allows for a generic interface mechanism through
which OSPM can inject hardware errors to the platform without requiring platform speciﬁc OSPM level software.

The primary goal of this mechanism is to support testing of OSPM error handling stack by enabling the injection of
hardware errors. Through this capability OSPM is able to implement a simple interface for diagnostic and validation
of errors handling on the system.
18.6.1 Error Injection Table (EINJ)
The Error Injection (EINJ) table provides a generic interface mechanism through which OSPM can inject hardware
errors to the platform without requiring platform speciﬁc OSPM software. System ﬁrmware is responsible for building
this table, which is made up of Injection Instruction entries. The following table describes the necessary details for
EINJ.
Table 18.24: Error Injection Table (EINJ)
Field Byte
Header Signature 4 0 EINJ. Signature for the Error Record Injection Table.
Length 4 4 Length, in bytes, of entire EINJ. Entire table must be
OEM Revision 4 24 OEM revision of EINJ.
Injection Header
Injection Header Size 4 36 Length in bytes of the Injection Interface header.
Injection Flags 1 40 Reserved. Must be zero
Reserved 3 41 Must be zero.
Injection Entry Count 4 44 The number of Instruction Entries in the Injection Ac-
tion Table
Injection Action Table
Injection Instruction Entries 48 A series of error injection instruction entries, per Injec-
tion Entry Count See Table 18.26.
The following table identiﬁes the supported error injection actions.
Table 18.25: Error Injection Actions
0x0 BEGIN_INJECTION_OPERATION
Indicates to the platform that an error injection is beginning.
This allows the platform to set its operational context.
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Table 18.25 – continued from previous page
0x1 GET_TRIGGER_ERROR_ACTION-
_TABLE Returns a 64-bit physical memory pointer to the Trigger
Action Table. See Table 18.36
0x2 SET_ERROR_TYPE
Type of error to Inject. Only one ERROR_TYPE can be
injected at any given time. If there is request for multiple
injections at the same time, then the platform will return an
error condition. See Section 18.6.4.
0x3 GET_ERROR_TYPE
Returns the error injection capabilities of the platform.
0x4 END_OPERATION
Indicates to the platform that the current injection operation
has ended. This allows the platform to clear its operational
context.
0x5 EXECUTE_OPERATION
Instructs the platform to carry out the current operation based
on the current operational context.
0x6 CHECK_BUSY_STATUS
Returns the state of the current operation. Once an operation
has been executed through the EXECUTE_OPERATION
action, the platform is required to return an indication that
the operation is busy until the operation is completed. This
allows software to poll for completion by repeatedly
executing the CHECK_BUSY_STATUS action until the
platform indicates that the operation is complete by setting
not busy.
The lower most bit (bit0) of the returned value indicates the
busy status by setting it to 1 and not busy status by setting it
to 0.
0x7 GET_COMMAND_STATUS Returns the status of the current operation. See Table 18.29
for a list of valid command status codes.
0x8 SET_ERROR_TYPE-
_WITH_ADDRESS Type of error to Inject, and the address to inject. Only one
Error type can be injected at any given time. If there is
request for multiple injections at the same time, then the
platform will return an error condition.
The RegisterRegion ﬁeld (See Table 18.26) in
SET_ERROR_TYPE_WITH_ADDRESS points to a data
structure whose format is deﬁned in Table 18.31.
Note that executing
SET_ERROR_TYPE_WITH_ADDRESS without specifying
an address has the same effect as executing
SET_ERROR_TYPE. See Table 18.30, error type deﬁnition.
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0x9 GET_EXECUTE_OPERATION-
_TIMINGS Returns an encoded QWORD: [63:32] value in microseconds
that the platform expects would be the maximum amount of
time it will take to process and complete an
EXECUTE_OPERATION. [31:0] value in microseconds that
the platform expects would be the nominal amount of time it
will take to process and complete an
EXECUTE_OPERATION.
0x10 EINJV2_SET_ERROR_TYPE
New Error Injection action introduced in EINJv2 for the
purpose of injecting an EINJv2 error type, with address,
severity, and detailed syndrome. Only one Error type can be
injected at any given time. For multiple injections at the
same time, then the platform will return an error condition.
The RegisterRegion ﬁeld (see Table 18.26) in
EINJV2_SET_ERROR_TYPE points to a data structure
whose format is deﬁned in Table 18.34
See Section 18.6.4.1, for the EINJv2 error type deﬁnition.
0x11 EINJV2_GET_ERROR_TYPE
Returns the extended error injection capabilities (EINJv2
features) of the platform:
Bit 0 - EINJv2 Processor Error Type supported
Bit 1 - EINJv2 Memory Error Type supported
Bit 2 - EINJv2 PCIe Error Type supported
Bit 3-30 - Reserved (Must be zero)
Bit 31 - EINJv2 Vendor speciﬁc error codes
0xFF TRIGGER_ERROR
This Value is reserved for entries declared in the Trigger
Error Action Table returned in response to a
GET_TRIGGER_ERROR_ACTION_TABLE action. The
returned table consists of a series of actions each of which is
set to TRIGGER_ERROR (see Table 18.36). When executed
by software, the series of TRIGGER_ERROR actions
triggers the error injected as a result of the successful
completion of an EXECUTE_OPERATION action.
18.6.2 Injection Instruction Entries
An Injection action consists of a series of one or more Injection Instructions. An Injection Instruction represents a
primitive operation on an abstracted hardware register, represented by the register region as deﬁned in an Injection
Instruction Entry.
An Injection Instruction Entry describes a region in an injection hardware register and the injection instruction to be
performed on that region.
The following table details the layout of an Injection Instruction Entry.
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Table 18.26: Injection Instruction Entry
Field Byte
Injection Ac-
tion1 0 The injection action that this instruction is a part of. See the Error Injec-
tion Actions table for supported injection actions.
Instruction 1 1 Identiﬁes the instruction to execute. See the Injection Instructions table
for a list of valid instructions.
Flags 1 2 Flags that qualify the instruction.
Reserved 1 3 Must be zero.
Register
Region12 4 The Generic Address Structure is used to describe the address and bit.
Address_Space_ID must be 0 (System Memory) or 1 (System IO). This
constraint is an attempt to ensure that the registers are accessible in the
presence of hardware error conditions.
Value 8 16 This is the value ﬁeld that is used by the instruction READ or
WRITE_REGISTER_V ALUE.
Mask 8 24 The bit mask required to obtain the bits corresponding to the injection
instruction in a given bit range deﬁned by the register region.
as well as the bit range that corresponds to a desired region of the register. The bit range is deﬁned as the smallest set
of consecutive bits that contains every bit in the register that is associated with the injection Instruction. If bits [6:5]
and bits [3:2] all correspond to an Injection Instruction, the bit range for that instruction would be [6:2].
Because a bit range could contain bits that do not pertain to a particular injection Instruction (i.e. bit 4 in the example
above), a bit mask is required to distinguish all the bits in the region that correspond to the instruction. The Mask
ﬁeld is deﬁned to be this bit mask with a bit set to a ‘1’ for each bit in the bit range (deﬁned by the register region)
corresponding to the Injection Instruction. Note that bit 0 of the bit mask corresponds to the lowest bit in the bit range.
In the example used above, the mask would be 11011b or 0x1B.
Table 18.27: Instruction Flags
0x01 PRESERVE_REGISTER For WRITE_REGISTER and WRITE_REGISTER_V ALUE in-
structions, this ﬂag indicates that bits within the register that are
not being written must be preserved rather than destroyed.
For READ_REGISTER instructions, this ﬂag is ignored.
18.6.3 Injection Instructions
The table below lists the supported Injection Instructions for Injection Instruction Entries.
Table 18.28: Injection Instructions
Opcode Instruction name Description
0x00 READ_REGISTER A READ_REGISTER instruction reads the value from the speciﬁed
0x01 READ_REGISTER_V ALUE A READ_REGISTER_V ALUE instruction reads the designated in-

formation from the speciﬁed Register Region and compares the re-
sults with the contents of the Value ﬁeld.
If the information read matches the contents of the Value ﬁeld,
TRUE is returned, else FALSE is returned.
0x02 WRITE_REGISTER A WRITE_REGISTER instruction writes a value chosen by soft-
ware to the speciﬁed Register Region. The Value ﬁeld is ignored.
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Table 18.28 – continued from previous page
0x03 WRITE_REGISTER_V ALUE A WRITE_REGISTER_V ALUE instruction writes the contents of
the Value ﬁeld to the speciﬁed Register Region.
0x04 NOOP No operation.
The table below deﬁnes the error injection status codes returned from GET_COMMAND_STATUS.
Table 18.29: Command Status Deﬁnition
0x0 Success
0x1 Unknown Failure
0x2 Invalid Access
18.6.4 Error Types
The table below deﬁnes the error type codes returned from GET_ERROR_TYPE, as well as the error type set by
SET_ERROR_TYPE and the Error Type ﬁeld set by SET_ERROR_TYPE_WITH_ADDRESS (see Table 18.31).
Both the SET_ERROR_TYPE and SET_ERROR_TYPE_WITH_ADDRESS actions must be present as part of the
EINJ Action Table. OSPM is free to choose either of these two actions to inject an error type. The platform
will give precedence to SET_ERROR_TYPE_WITH_ADDRESS. That is, if a non-zero Error Type value is set
by SET_ERROR_TYPE_WITH_ADDRESS, then any Error Type value set by SET_ERROR_TYPE will be ig-
nored. But if no Error Type is speciﬁed by SET_ERROR_TYPE_WITH_ADDRESS, then the platform will use
SET_ERROR_TYPE to identify the error type to inject.
Table 18.30: Error Type Deﬁnition
0 Processor Correctable
1 Processor Uncorrectable non-fatal
2 Processor Uncorrectable fatal
3 Memory Correctable
4 Memory Uncorrectable non-fatal
5 Memory Uncorrectable fatal
6 PCI Express Correctable
7 PCI Express Uncorrectable non-fatal
8 PCI Express Uncorrectable fatal
9 Platform Correctable
10 Platform Uncorrectable non-fatal
11 Platform Uncorrectable fatal
12 CXL.cache Protocol Correctable
13 CXL.cache Protocol Uncorrectable non-fatal
14 CXL.cache Protocol Uncorrectable fatal
15 CXL.mem Protocol Correctable
16 CXL.mem Protocol Uncorrectable non-fatal
17 CXL.mem Protocol Uncorrectable fatal
18:29 RESERVED
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Table 18.30 – continued from previous page
30
EINJv2 Error Type. If this bit is set, then the support for EINJV2_SET_ERROR_TYPE and
EINJV2_GET_ERROR_TYPE actions are supported.
NOTE: This may only be used with the action GET_ERROR_TYPE and it is not permitted to set
this bit with SET_ERROR_TYPE or SET_ERROR_TYPE_WITH_ADDRESS
31 Vendor Deﬁned Error Type. If this bit is set, then the Error types and related data structures are
deﬁned by the Vendor, as shown in Table 18.32.
Note: CXL errors (Bits 17:12) are intended to target the CXL port (for example via Link or Protocol errors, not actual
Component errors).
Table 18.31: SET_ERROR_TYPE_WITH_ADDRESS Data Struc-
ture
Field Byte
Error Type 4 0 Bitmap of error types to inject. See Table 18.30. This ﬁeld is
cleared by the platform once it is consumed.
Vendor Error Type Exten-
sion Structure Offset4 4 Speciﬁes the offset from the beginning of the table to the ven-
dor error type extension structure. If no vendor error type
extension is present, bit31 in error type must be clear and this
ﬁeld must be set to 0.
Flags 4 8
Bit [0] - Processor Identiﬁcation Field Valid
Bit [1]- Memory Address and Memory address Mask Field
Valid
NOTE: For CXL errors, the Memory Address points to
a CXL 1.1 compliant memory-mapped Downstream
port
Bit [2] - PCIe SBDF ﬁeld valid
NOTE: For CXL errors, the SBDF points to a CXL 2.0
compliant Root port.
Bit [31:3] - RESERVED
This ﬁeld is cleared by the platform once it is consumed.
Processor Error
Processor Identiﬁcation 4 12 Optional ﬁeld: on non-ARM architectures, this is the physical
APIC ID or the X2APIC ID of the processor which is a target
for the injection; on ARM systems, this is the ACPI Processor
UID value as used in the MADT.
Memory Address 8 16 Optional ﬁeld specifying the physical address of the memory
that is the target for the injection. Valid if Bit [1] of the Flags
ﬁeld is set.
Memory Address Range 8 24 Optional ﬁeld that provides a range mask for the address ﬁeld.
Valid if Bit [1] of the Flags ﬁeld is set. If the OSPM doesn’t
want to provide a range of addresses, then this ﬁeld should be
zero.
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Table 18.31 – continued from previous page
PCIe SBDF 4 32
Byte 3 - PCIe Segment
Byte 2 - Bus Number
Byte 1:
Bits [7:3] Device Number
Bits [2:0] Function Number
Byte 0 - RESERVED
Table 18.32: Vendor Error Type Extension Structure
Field Byte
OffsetAttribute Description
Length 4 0x0 Set by Platform. RO for
Software.Length, in bytes, of the entire Vendor Error
Type Extension Structure.
SBDF 4 0x04 Set by Platform. RO for
SoftwareThis provides a PCIe Segment, Bus, Device
and Function number which can be used to
read the Vendor ID, Device ID and Rev ID,
so that software can identify the system for
error injection purposes. The platform sets
this ﬁeld and is RO for Software.
Vendor ID 2 0x08 Set by Platform. RO for
SoftwareVendor ID which identiﬁes the device man-
ufacturer. This is the same as the PCI SIG
deﬁned Vendor ID. The platform sets this
ﬁeld and is RO for Software
Device ID 2 0x0A Set by Platform. RO for
SoftwareThis 16-bit ID is assigned by the manufac-
turer that identiﬁes this device. The plat-
form sets this ﬁeld and is RO for Software
Rev ID 1 0x0C Set by Platform. RO for
SoftwareThis 8-bit value is assigned by the manufac-
turer and identiﬁes the revision number of
the device. The platform sets this ﬁeld and
is RO for Software
Reserved 3 0x0D Set by Platform. RO for
SoftwareReserved
OEM Deﬁned
structureN 0x10 The rest of the ﬁelds are deﬁned by the
OEM.
18.6.4.1 EINJv2 Error Types
EINJ version 2 (EINJv2) introduces a new error injection action The table below deﬁnes the error type codes returned
from EINJV2_GET_ERROR_TYPE, as well as the error type set by EINJV2_SET_ERROR_TYPE.
EINJV2_SET_ERROR_TYPE actions must be present as part of the EINJ Action Table. OSPM is free to choose
this action for advanced error injection options. The platform will give precedence to EINJV2_SET_ERROR_TYPE.
That is, if a non-zero Error Type value is set by EINJV2_SET_ERROR_TYPE, then any Error Type value set by
SET_ERROR_TYPE_WITH_ADDRESS and/or SET_ERROR_TYPE will be ignored.
Also, EINJv2 breaks out the Error Type from the severity. The following table describes the new Error Type encoding.
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Table 18.33: EINJv2 Error Type
0 Processor Error
1 Memory Error
2 PCIe Error
3-30 Reserved
31 Vendor Deﬁned Error
Table 18.34: EINJV2_SET_ERROR_TYPE Data Structure
Field Byte
Error Type 4 0 Bit map of error types to inject (see Table 18.30). Only one Error
Type bit may be set at a time. This ﬁeld is cleared by the platform
once it is consumed.
Error Type Code 1 4 Vendor speciﬁc code for each error type used to indicate error in-
jection behavior. Value of zero is default error injection behavior
as deﬁned by EINJv2. Non-zero value indicates vendor speciﬁc be-
havior.
Flags 3 5
This ﬁeld indicates which of the remaining ﬁelds are valid:
Bit 0 - Address Valid
Bit 1 - Address Range Valid
Bit 2 - Severity Valid
Bit 3 - Component Syndrome Count and Array is valid
Length 4 8 This speciﬁes the length of the entire structure including the com-
ponent syndrome array.
Severity 4 12
Optional ﬁeld specifying the severity of the injected error:
0 - Corrected Error
1 - Uncorrected Non-Fatal
2 - Uncorrected Fatal
Address 8 16 Optional ﬁeld specifying the physical address of the memory that is
the target for the injection. Valid if Bit [0] of the Flags ﬁeld is set.
Address Range 8 24 Optional ﬁeld specifying the physical address range mask of the
memory that is the target for the injection. Valid if Bit [1] of the
Flags ﬁeld is set.
Component Syn-
drome Count (N)4 28 This represents the maximum number of components supported in
the Component Syndrome Array. This is intended to support in-
jecting an error into multiple components / devices simultaneously.
For Example: If Component Syndrome Count is valid per the Flags
ﬁeld and the value Count (N) is 4, this structure contains the error
Component Syndrome Array for 4 unique components.
drome ArrayN * 32 32 This is an array based on the Component Syndrome Entry Structure,
each entry being 32-bytes as described in Table 18.35. The length

of this structure is 32 x Component Syndrome Count.
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Table 18.35: EINJV2_SET_ERROR_TYPE Component Syndrome
Structure
Field Byte
Component
ID16 0
Component ID deﬁnition depends on the Error Type Value. Note that
because this is a union structure, the byte length is 16 bytes to
accommodate the largest possible ID (i.e. FRU ID for vendor speciﬁc
errors).
Processor Error (0x1):
The bottom 32-bit represents the ACPI ID (represented in MADT)
The remaining bits are vendor speciﬁc.
Memory Error (0x2):
This represents the Device ID within the memory module (e.g.
DDR DIMM) for a particular system physical address. For
example: 18 x 4 DIMMs support up to 18 devices (0-17) per
address. 9 x 8 DIMMs support up to 9 devices (0-8) per address.
It is possible to inject error syndrome into multiple device
instances up to the Component Syndrome Count.
PCIe Error (0x4):
This represents the SBDF.
Vendor Speciﬁc Error (0x80000000)
This represents some platform speciﬁc identiﬁer (e.g. FRU ID or
other vendor speciﬁc error format).
Component
Syndrome16 16
The Component Syndrome deﬁnition depends on the Error Type Value.
The usage of the syndrome bits will be vendor speciﬁc.
This indicates bit mask of data bits that must be ﬂipped within a
memory device. (e.g. If the set syndrome bit value is zero, the bit
value will be changed to one. if the set syndrome bit value is one,
the bit value will be changed to zero). The range of valid bits
depends on the component error injection granularity.
Example 1: For a DDR4 18x4 memory device topology with a
burst length of 8 (e.g., 64-byte cache line in a single burst), there
will be up to 32 valid bits per device that may be modiﬁed per
burst. If bit 3 in this mask is set, bit offset 3 of the device in that
burst will be ﬂipped.
Example 2: For a DDR5 5x8 memory device topology with a burst
length of 16 (e.g., 64-byte cache line in a single burst), there will
be up to 128 valid bits per device that may be modiﬁed per burst.
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18.6.5 Trigger Action Table
An error injection operation is a two-step process where the error is injected into the platform and subsequently
triggered. After software injects an error into the platform using the EXECUTE_OPERATION action, it then needs
to trigger the error. In order to trigger the error, software executes the GET_TRIGGER_ERROR_ACTION_TABLE
action, which returns a pointer to a Trigger Error Action table. The format of this table is shown in the table below.
Software then executes the instruction entries speciﬁed in the Trigger Error Action Table in order to trigger the injected
error.
Table 18.36: Trigger Error Action
TRIGGER_ERROR Header Byte Length Byte Offset Description
Header Size 4 0 Length in bytes of this header.
Revision 4 4
Table Size 4 8 Size in Bytes of the entire table.
Entry Count 4 12 The number of Instruction Entries in the
TRIGGER_ERROR Action Sequence - see
note (1) below.
Action Table
TRIGGER_ERROR Instruction
Entries - see note (2) below16 A series of error injection instruction entries
as deﬁned in Table 18-405.
Note: (1) If the “Entry Count” ﬁeld above is ZERO, then there are no action structures in the TRIGGER_ERROR
action table. The platform may make this ﬁeld ZERO in situations where there is no need for a TRIGGER_ERROR
action (for example, in cases where the error injection action seeds as well as consumes the error).
Note: (2) The format of TRIGGER_ERROR Instructions Entries is the same as Injection Instruction entries as
described in Table 18-407.
18.6.6 Error Injection Operation
Before OSPM can use this mechanism to inject errors, it must discover the error injection capabilities of the platform
by executing a GET_ERROR_TYPE. See Table 18.30 for a deﬁnition of error types.
After discovering the error injection capabilities, OSPM can inject and trigger an error according to the sequence
Note that injecting an error into the platform does not automatically consume the error. In response to an error
injection, the platform returns a trigger error action table. The software that injected the error must execute the actions
in the trigger error action table in order to consume the error. If a speciﬁc error type is such that it is automatically
consumed on injection, the platform will return a trigger error action table consisting of NO_OP.
1. Executes a BEGIN_INJECTION_OPERATION action to notify the platform that an error injection operation is
beginning.
2. Executes a GET_ERROR_TYPE action to determine the error injection capabilities of the system. This action
returns a DWORD bit map of the error types supported by the platform (see Table 18.30).
3. If GET_ERROR_TYPE returns the DWORD with Bit [31] set, it means that vendor deﬁned error types are
present, apart from the standard error types (see Table 18.30).
4. OSPM chooses the type of error to inject by executing a SET_ERROR_TYPE or a
SET_ERROR_TYPE_WITH_ADDRESS _WITH_ADDRESS action (see Section 18.6.4).
18.6. Error Injection 822Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
a. If the OSPM chooses to inject one of the supported standard error types, then it sets the corresponding bit
in the error type bitmap. For example, if OSPM chooses to inject a “Memory Correctable” error, then the
OSPM sets the value 0x0000_0080 in the error type bitmap.
b. If the OSPM chooses to inject one of the vendor deﬁned error types, then it sets bit[31] in the error type
bitmap.
* OSPM exectures the SET_ERROR_TYPE_WITH_ADDRESS_WITH_ADDRESS action to retrieve the
location of the “SET_ERROR_TYPE_WITH_ADDRESS data structure”, to then get the location of the
“Vendor Error Type Extension Structure” by reading the “Vendor Error Type Extension Structure Offset”
(see Table 18.32).
- OSPM reads the Vendor ID, Device ID and Rev ID from the PCI conﬁg space whose path (PCIe
Segment/Device/Function) is provided in the “SBDF” ﬁeld of the Vendor Error Type Extension
- If the Vendor ID/Device ID and Rev IDs match, then the OSPM can identify the platform it is
running on and would know the Vendor error types that are supported by this platform.
- The OSPM writes the vendor error type to inject in the “OEM Deﬁned Structure” ﬁeld (see
Table 18.32).
* Optionally, for either standard or vendor-deﬁned error types, the OSPM can choose the target of the
injection, such as a memory range, PCIe Segment/Device/Function or Processor APIC ID, depending on
the type of error. The OSPM does this by executing the SET_ERROR_TYPE_WITH_ADDRESS action
to ﬁll in the appropriate ﬁelds of the “SET_ERROR_TYPE_WITH_ADDRESS Data structure” (see Table
18.31).
5. Executes an EXECUTE_OPERATION action to instruct the platform to begin the injection operation.
6. Busy waits by continually executing CHECK_BUSY_STATUS action until the platform indicates that the oper-
ation is complete by clearing the abstracted Busy bit.
7. Executes a GET_COMMAND_STATUS action to determine the status of the completed operation.
8. If the status indicates that the platform cannot inject errors, stop.
9. Executes a GET_TRIGGER_ERROR_ACTION_TABLE operation to get the physical pointer to the TRIG-
GER_ERROR action table. This provides the ﬂexibility in systems where injecting an error is a two (or more)
step process.
10. Executes the actions speciﬁed in the TRIGGER_ERROR action table.
11. Execute an END_OPERATION to notify the platform that the error injection operation is complete.
18.6.7 Error Injection Version 2 Operation
by executing a EINJV2_GET_ERROR_TYPE. See Table 18.30 for a deﬁnition of error types.
After discovering the EINJv2 error injection capabilities, OSPM can inject and trigger an error according to the
sequence described below.
consumed on injection, the platform will return a trigger error action table consisting of NO_OP:
18.6. Error Injection 823Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5

2. Executes a EINJ_GET_ERROR_TYPE action to determine the error injection capabilities of the system. This
action returns a DWORD bit map of the error types supported by the platform (see Table 18.30).
3. If EINJV2_GET_ERROR_TYPE returns the DWORD with Bit [30] set, it means that EINJv2 error types are
4. Executes a EINJV2_GET_ERROR_TYPE action to determine the error injection capabilities of the system.
This action returns a DWORD bit map of the error types supported by the platform (see Table 18.33).
5. If EINJV2_GET_ERROR_TYPE returns the DWORD with Bit [1] set, it means that memory error types are
present.
6. OSPM chooses the type of error to inject by executing a EINJV2_SET_ERROR_TYPE action.
in the error type bitmap.
For example: if OSPM chooses to inject a Memory error, then the OSPM sets the value 0x0000_0002
in the error type bitmap. If OSPM chooses to inject a memory error pattern into a device at a particular
DRAM address, the Flags will be set to 0x9 to indicate component syndrome and address are valid. OSPM
will populate the Address ﬁeld with the system physical address and the component syndrome count and
array syndrome.
Error Type = 0x2 (Memory Error)
Error Code = 0x0 (no vendor speciﬁc behavior)
Length=0x44
Severity=0 (not used)
Address=0000FFFFFFF00000
Address Range=0x0
Flags = 0x9 (Address and Component Syndrome Array is Valid)
Component Syndrome Count = 1
Component Syndrome Array [0] = { 00000000000000000000000000000004 ,
000000000000000000000000A5A5A5A5 }
So in this example software is trying to inject a 32-bit bit ﬂip pattern on
one device across a single burst for a particular system physical address.
EINJV2_SET_ERROR_TYPE=000000000000000000000000A5A5A5A50000000000000000000000000000000400000001000000
00000000000000FFFFFFF000000000000000000044000009000000002
7. Executes an EXECUTE_OPERATION action to instruct the platform to begin the injection operation.
8. Busy waits by continually executing CHECK_BUSY_STATUS action until the platform indicates that the oper-
9. Executes a GET_COMMAND_STATUS action to determine the status of the completed operation.
10. If the status indicates that the platform cannot inject errors, stop.
18.6. Error Injection 824Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
18.7 GHES_ASSIST Error Reporting
In some cases, errors reported by hardware may provide a limited amount of information, as additional information
may require platform-speciﬁc knowledge. Hence, the GHES_ASSIST mechanism, as marked in the Flags ﬁeld of
a given Error Source Structure, allows system ﬁrmware to provide additional information in the context of an error
reported by hardware. Speciﬁcally, system ﬁrmware provides additional information via a Generic Hardware Error
Source (GHES) structure which has its Related Source ID pointing back to the Error Source structure that represents
the hardware. OSPM conveys support for GHES_ASSIST as declared by the GHES_ASSIST Support ﬂag of the
Platform-Wide _OSC Capabilities DWORD 2. See Section 6.2.11.2, Platform-Wide OSPM Capabilities .
Note: System ﬁrmware must ensure that additional information provided by GHES_ASSIST structures is aligned
with the current error status information reported by the hardware. The implication is that as errors are generated by
the hardware, system ﬁrmware must have mechanisms to get control before those errors are delivered to OSPM.
Since OSPM is expected to consume the additional GHES_ASSIST information in the context of an error reported by
hardware, the Notiﬁcation Structure associated with the pertinent GHES should have the Type ﬁeld set to Polled , or a
to type that is aligned with the signaling of the hardware error event. See Table 18.14, Hardware Error Notiﬁcation
OSPM is expected clear the hardware error condition after consuming any additional information from the pertinent
GHES_ASSIST structures.
18.7.1 GHES_ASSIST on Machine Check Architecture
To support GHES_ASSIST on Machine Check Architecture (MCA) error sources, system ﬁrmware provides a set
of GHES structures for each MCA error source (see Table 18.3 Machine Check Exception, Table 18.5 Corrected
Machine Check, and Table 18.15 Deferred Machine Check). Each set consists of a GHES structure per MCA bank on
each Logical Processor (CPU), where the GHES structures from each set share a common Related Source ID .
For each MCA error source, OSPM can index thorough the set of GHES_ASSIST structures using the following
formula:
Index = ((CPU number) *(MCA Banks per CPU)) + (MCA Bank index)
Where CPU number represents the index of the corresponding Processor Local APIC or x2APIC structure with
(Flags.Enabled = 1) in MADT (e.g. 0 represents the ﬁrst enabled Processor Local APIC or x2APIC entry in MADT),
andMCA Banks per CPU represents the value of the Number Of Hardware Banks ﬁeld from the pertinent MCA error
source structure.
Note: System ﬁrmware must ensure that each set of GHES_ASSIST structures is laid out sequentially in system
memory, so that OSPM may consume them as speciﬁed by the Index formula described above.
18.7. GHES_ASSIST Error Reporting 825CHAPTER
NINETEEN
ACPI SOURCE LANGUAGE (ASL) REFERENCE
This section formally deﬁnes the ACPI Source Language (ASL). ASL is a source language for deﬁning ACPI objects
including writing ACPI control methods. OEMs and platform ﬁrmware developers deﬁne objects and write control
methods in ASL and then use a translator tool (compiler) to generate ACPI Machine Language (AML) versions of the
control methods. For a formal deﬁnition of AML, see the ACPI Machine Language (AML) Speciﬁcation chapter.
AML and ASL are different languages though they are closely related.
Every ACPI-compatible OS must support AML. A given user can deﬁne some arbitrary source language (to replace
ASL) and write a tool to translate it to AML.
An OEM or platform ﬁrmware vendor needs to write ASL and be able to single-step AML for debugging. (Debuggers
and similar tools are expected to be AML-level tools, not source-level tools.) An ASL translator implementer must
understand how to read ASL and generate AML. An AML interpreter author must understand how to execute AML.
This section has two parts:
• The ASL grammar, which is the formal ASL speciﬁcation and also serves as a quick reference.
• A full ASL reference, which includes for each ASL operator: the operator invocation syntax, the type of each
argument, and a description of the action and use of the operator.
19.1 ASL 2.0 Symbolic Operators and Expressions
For the math and logical operations, ASL supports standard symbolic operators and expressions that are similar to the
C language. Compound assignment operators are also supported. The AML code that is generated from the symbolic
operators and expressions is identical to the AML code generated for the equivalent legacy ASL operators.
The tables below summarize the ASL 2.0 support for symbolic operators, compared to the legacy ASL equivalent.
Math operators
826Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ASL 2.0 Syntax Legacy ASL Equivalent
Z = X + Y Add (X, Y , Z)
Z = X / Y Divide (X, Y , , Z)
Z = X % Y Mod (X, Y , Z)
Z = X * Y Multiply (X, Y , Z)
Z = X - Y Subtract (X, Y , Z)
Z = X << Y ShiftLeft (X, Y , Z)
Z = X >> Y ShiftRight (X, Y , Z)
Z = X & Y And (X, Y , Z)
Z = X | Y Or (X, Y , Z)
Z = X ^ Y Xor (X, Y , Z)
Z = ~X Not (X, Z)
X++ Increment (X)
X– Decrement (X)
Logical operators
(X == Y) LEqual (X, Y)
(X != Y) LNotEqual (X, Y)
(X < Y) LLess (X, Y)
(X > Y) LGreater (X, Y)
(X <= Y) LLessEqual (X, Y)
(X >= Y) LGreaterEqual (X, Y)
(X && Y) LAnd (X, Y)
(X || Y) LOr (X, Y)
!X LNot (X)
Assignment and Compound Assignment operations
X = Y Store (Y , X)
X += Y Add (X, Y , X)
X /= Y Divide (X, Y , , X)
X %= Y Mod (X, Y , X)
X *= Y Multiply (X, Y , X)
X -= Y Subtract (X, Y , X)
X <<= Y ShiftLeft (X, Y , X)
X >>= Y ShiftRight (X, Y , X)
X &= Y And (X, Y , X)
X |= Y Or (X, Y , X)
X ^= Y Xor (X, Y , X)
Miscellaneous
Z = X[Y] Index (X, Y , Z)
19.1. ASL 2.0 Symbolic Operators and Expressions 827Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.2 ASL Language Grammar
The purpose of this section is to unambiguously state the grammar rules used by the syntax checker of an ASL
compiler.
ASL statements declare objects. Each object has three parts, one of which is required and two of which are optional:
FixedList refers to a list, of known length, that supplies data that all instances of a given ObjectType must have. A
ﬁxed list is written as ( a , b , c , . . . ) where the number of arguments depends on the speciﬁc ObjectType, and

compiler.
some elements can be nested objects, that is (a, b, (q, r, s, t), d). Arguments to a FixedList can have default values, in
which case they can be skipped. Thus, (a„c) will cause the default value for the second argument to be used. Some
ObjectTypes can have a null FixedList, which is simply omitted. Trailing arguments of some object types can be left
out of a ﬁxed list, in which case the default value is used.
VariableList refers to a list, not of predetermined length, of child objects that help deﬁne the parent. It is written as {
x, y, z, aa, bb, cc } where any argument can be a nested object. ObjectType determines what terms are legal elements
of the VariableList. Some ObjectTypes may have a null variable list, which is simply omitted.
Other rules for writing ASL statements are the following:
• Multiple blanks are the same as one. Blank, (, ), ‘,’ and newline are all token separators.
• // marks the beginning of a comment, which continues from the // to the end of the line.
• /* marks the beginning of a comment, which continues from the /* to the next */.
• “” (quotes) surround an ASCII string.
• Numeric constants can be written in three ways: ordinary decimal, octal (using 0ddd) or hexadecimal, using the
notation 0xdd.
• Nothing indicates an empty item. For example, { Nothing } is equivalent to {}.
19.2.1 ASL Grammar Notation
The notation used to express ASL grammar is speciﬁed in the following table.
Table 19.1: ASL Grammar Notation
Notation Convention Description Example
Term := Term Term . . . The term to the left of := can be
expanded into the sequence of
terms on the right.aterm := bterm cterm means that aterm can be ex-
panded into the two-term sequence of bterm fol-
lowed by cterm.
Angle brackets (< > ) used to group items. <a b> | <c d> means either a b or c d.
Arrow (=>) Indicates required run-time re-
duction of an ASL argument to
an AML data type. Means “re-
duces to” or “evaluates to” at
run-time.“TermArg => Integer” means that the argument
must be an ASL TermArg that must resolve to an
Integer data type when it is evaluated by an AML
interpreter.
19.2. ASL Language Grammar 828Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Bar symbol ( | ) Separates alternatives.
aterm := bterm | <cterm dterm> means the
following constructs are possible:
bterm
cterm dterm
aterm := <bterm | cterm> dterm means the
bterm dterm
Term Term Term Terms separated from each
other by spaces form an ordered
list.N/A
Word in bold Denotes the name of a term
in the ASL grammar, repre-
senting any instance of such a
term. ASL terms are not case-
sensitive.In the following ASL term deﬁnition: Thermal-
Zone (ZoneName) {TermList} the item in bold is
the name of the term.
Word in italics Names of arguments to objects
that are replaced for a given in-
stance.In the following ASL term deﬁnition: Thermal-
Zone (ZoneName) {TermList} the italicized item
is an argument. The item that is not bolded or ital-
icized is deﬁned elsewhere in the ASL grammar.
Single quotes (‘ ‘) Indicate constant characters. ‘A’
0xdd Refers to a byte value expressed
as two hexadecimal digits.0x21 means a value of hexadecimal 21, or decimal
37. Notice that a value expressed in hexadecimal
must start with a leading zero (0).
Dash character ( - ) Indicates a range. 1-9 means a single digit in the range 1 to 9 inclu-
sive.
19.2.2 ASL Name and Pathname Terms
// Name and path characters supported
LeadNameChar := ‘A’-‘Z’ | ‘a’-‘z’ | ‘_’
DigitChar := ‘0’-‘9’
NameChar := DigitChar |LeadNameChar
RootChar := ‘'
ParentPreﬁxChar := ‘^’
PathSeparatorChar := ‘.’
CommaChar := ‘,’
SemicolonDelimiter := Nothing | ‘;’
// Names and paths
NameSeg :=
<LeadNameChar > |
<LeadNameChar NameChar > |
19.2. ASL Language Grammar 829Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
<LeadNameChar NameChar NameChar> |
<LeadNameChar NameChar NameChar NameChar>
NameString := <RootChar NamePath > | < ParentPreﬁxChar PreﬁxPath NamePath > | NonEmpty-
NamePath
NamePath := Nothing | < NameSeg NamePathTail >
NamePathTail := Nothing | < PathSeparatorChar NameSeg NamePathTail >
NonEmptyNamePath := NameSeg | <NameSeg NamePathTail >
PreﬁxPath := Nothing | < ParentPreﬁxChar PreﬁxPath >
19.2.3 ASL Root and Secondary Terms
// Root Terms
ASLCode := DeﬁnitionBlockList
DeﬁnitionBlockList := DeﬁnitionBlockTerm | <DeﬁnitionBlockTerm DeﬁnitionBlockList>
// Major Terms
SuperName := NameString |ArgTerm |LocalTerm |DebugTerm |ReferenceTypeOpcode |MethodInvo-
cationTerm
Target := Nothing | SuperName
TermArg := ExpressionOpcode |DataObject |ArgTerm |LocalTerm |NameString | SymbolicExpression
MethodInvocationTerm :=
NameString ( // NameString => Method
ArgList
) => Nothing | DataRefObject
// List Terms
ArgList := Nothing | < TermArg ArgListTail >
ArgListTail := Nothing | < CommaChar TermArg ArgListTail>
ByteList := Nothing | < ByteConstExpr ByteListTail >
ByteListTail := Nothing | < CommaChar ByteConstExpr ByteListTail>
DWordList := Nothing | < DwordConstExpr DwordListTail >
DWordListTail := Nothing | < CommaChar DwordConstExpr DwordListTail>
ExtendedAccessAttribTerm :=
ExtendedAccessAttribKeyword (
AccessLength // ByteConst
)
FieldUnitList := Nothing | < FieldUnit FieldUnitListTail >
FieldUnitListTail := Nothing | < CommaChar FieldUnit FieldUnitListTail>
FieldUnit := FieldUnitEntry | OffsetTerm |AccessAsTerm |ConnectionTerm
FieldUnitEntry := <Nothing | NameSeg >CommaChar Integer
PackageList := Nothing | < PackageElement PackageListTail >
19.2. ASL Language Grammar 830Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PackageListTail := Nothing | < CommaChar PackageElement PackageListTail >
PackageElement := DataObject |NameString
ParameterTypePackage := ObjectTypeKeyword | {Nothing | ParameterTypePackageList }
ParameterTypePackageList := ObjectTypeKeyword | <ObjectTypeKeyword CommaChar Parameter-
TypePackageList>
ParameterTypesPackage := ObjectTypeKeyword | {Nothing | ParameterTypesPackageList }
ParameterTypesPackageList := ParameterTypePackage | <ParameterTypePackage CommaChar Pa-
rameterTypesPackageList>
TermList := Nothing | < Term SemiColonDelimiter TermList>
Term := Object |StatementOpcode |ExpressionOpcode | SymbolicExpression
Object := CompilerDirective |NamedObject |NameSpaceModiﬁer
// Conditional Execution List Terms
CaseTermList := Nothing | CaseTerm |DefaultTerm DefaultTermList |CaseTerm CaseTermList
DefaultTermList := Nothing | CaseTerm |CaseTerm DefaultTermList
IfElseTerm := IfTerm ElseTerm
19.2.4 ASL Data and Constant Terms
// Numeric Value Terms
LeadDigitChar := ‘1’-‘9’
HexDigitChar := DigitChar | ‘A’-‘F’ | ‘a’-‘f’
OctalDigitChar := ‘0’-‘7’
NullChar := 0x00
// Data Terms
BufferData := BufferTypeOpcode |BufferTerm
ComputationalData := BufferData |IntegerData |StringData
DataObject := BufferData |PackageData |IntegerData |StringData
DataRefObject := DataObject |ObjectReference
IntegerData := IntegerTypeOpcode | Integer | ConstTerm
PackageData := PackageTerm
StringData := StringTypeOpcode |String
// Integer Terms
Integer := DecimalConst |OctalConst |HexConst
DecimalConst := LeadDigitChar | <DecimalConst DigitChar >
OctalConst := ‘0’ | < OctalConst OctalDigitChar >
HexConst := <0xHexDigitChar > | <0X HexDigitChar > | <HexConst HexDigitChar >
ByteConst := Integer => 0x00-0xFF
WordConst := Integer => 0x0000-0xFFFF
19.2. ASL Language Grammar 831Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
DWordConst := Integer => 0x00000000-0xFFFFFFFF
QWordConst := Integer => 0x0000000000000000-0xFFFFFFFFFFFFFFFF
ByteConstExpr := <IntegerTypeOpcode |ConstExprTerm | Integer> => ByteConst
WordConstExpr := <IntegerTypeOpcode |ConstExprTerm | Integer> => WordConst
DWordConstExpr := <IntegerTypeOpcode |ConstExprTerm | Integer> => DWordConst
QWordConstExpr := <IntegerTypeOpcode |ConstExprTerm | Integer> => QWordConst
ConstTerm := ConstExprTerm | Revision
ConstExprTerm := Zero | One | Ones
// String Terms
String := ‘”’Utf8CharList ‘”’
Utf8CharList := Nothing | < EscapeSequence Utf8CharList> | < Utf8Char Utf8CharList>
Utf8Char := 0x01-0x21 | 0x23-0x5B | 0x5D-0x7F | 0xC2-0xDF 0x80-0xBF | 0xE0 0xA0-0xBF 0x80-
0xBF | 0xE1-0xEC 0x80-0xBF 0x80-0xBF | 0xED 0x80-0x9F 0x80-0xBF | 0xEE-0xEF 0x80-0xBF
0x80-0xBF | 0xF0 0x90-0xBF 0x80-0xBF 0x80-0xBF | 0xF1-0xF3 0x80-0xBF 0x80-0xBF 0x80-
0xBF
// Escape sequences
EscapeSequence := SimpleEscapeSequence |OctalEscapeSequence |HexEscapeSequence
HexEscapeSequence := \xHexDigitChar | \xHexDigitChar HexDigitChar
SimpleEscapeSequence := \’ | \” | \a | \b | \f | \n | \r | \t | \v | \\
OctalEscapeSequence := \OctalDigitChar | \ OctalDigitChar OctalDigitChar | \ OctalDigitChar Oc-
talDigitChar OctalDigitChar
// Miscellaneous Data Type Terms
ObjectReference := Integer
Boolean := True | False
True := Ones
False := Zero
// Symbolic Operator terms

0xBF
Operators := ‘+’ | ‘-‘ | ‘*’ | ‘/’ | ‘%’ | ‘&’ | ‘|’ | ‘^’ | ‘~’ | ‘<’ | ‘>’ | ‘!’ | ‘=’
CompoundOperators := “<<” | “>>” | “++” | “-” | “==” | “!=” | “<=” | “>=” | “&&” | “||” | “+=” | “-=” |
“*=” | “/=” | “%=” | “<<=” | “>>=” | “&=” | “|=” | “^=”
19.2.5 ASL Opcode Terms
CompilerDirective := IncludeTerm |ExternalTerm
NamedObject := BankFieldTerm |CreateBitFieldTerm |CreateByteFieldTerm |CreateDWordFieldTerm |
CreateFieldTerm |CreateQWordFieldTerm |CreateWordFieldTerm |DataRegionTerm |DeviceTerm |
EventTerm |FieldTerm |FunctionTerm |IndexFieldTerm |MethodTerm |MutexTerm |OpRegionTerm
|PowerResTerm |ProcessorTerm |ThermalZoneTerm
NameSpaceModiﬁer := AliasTerm |NameTerm |ScopeTerm
19.2. ASL Language Grammar 832Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
SymbolicExpressionTerm := (TermArg ) |AddSymbolicTerm |AndSymbolicTerm |DecSymbol-
icTerm |DivideSymbolicTerm |IncSymbolicTerm |LAndSymbolicTerm |LEqualSymbolicTerm |
LGreaterEqualSymbolicTerm |LGreaterSymbolicTerm |LLessEqualSymbolicTerm |LLessSymbol-
icTerm |LNotEqualSymbolicTerm |LNotSymbolicTerm |LOrSymbolicTerm |ModSymbolicTerm |
MultiplySymbolicTerm |NotSymbolicTerm |OrSymbolicTerm |ShiftLeftSymbolicTerm |ShiftRight-
SymbolicTerm |SubtractSymbolicTerm |XorSymbolicTerm
SymbolicAssignmentTerm := StoreSymbolicTerm |AddCompoundTerm |AndCompoundTerm |Divide-
CompoundTerm |ModCompoundTerm |MultiplyCompoundTerm |OrCompoundTerm |ShiftLeft-
CompoundTerm |ShiftRightCompoundTerm |SubtractCompoundTerm |XorCompoundTerm
StatementOpcode := BreakTerm |BreakPointTerm |ContinueTerm |FatalTerm |ForTerm |IfElseTerm |
NoOpTerm |NotifyTerm |ReleaseTerm |ResetTerm |ReturnTerm |SignalTerm |SleepTerm |StallTerm
|SwitchTerm |UnloadTerm |WhileTerm
A statement opcode term does not return a value and can only be used standalone on a line of ASL
code. Since these opcodes do not return a value, they cannot be used as a term in an expression.
ExpressionOpcode := AcquireTerm |AddTerm |AndTerm |ConcatTerm |ConcatResTerm |Con-
dRefOfTerm |CopyObjectTerm |DecTerm |DerefOfTerm |DivideTerm |FindSetLeftBitTerm |Find-
SetRightBitTerm |FprintfTerm |FromBCDTerm |IncTerm |IndexTerm |LAndTerm |LEqualTerm |
LGreaterTerm |LGreaterEqualTerm |LLessTerm |LLessEqualTerm |LNotTerm |LNotEqualTerm
|LOrTerm |MatchTerm |MidTerm |ModTerm |MultiplyTerm |NAndTerm |NOrTerm |NotTerm |
ObjectTypeTerm |OrTerm |PrintfTerm |RefOfTerm |ShiftLeftTerm |ShiftRightTerm |SizeOfTerm
|StoreTerm |SubtractTerm |TimerTerm |ToBCDTerm |ToBufferTerm |ToDecimalStringTerm |To-
HexStringTerm |ToIntegerTerm |ToStringTerm |WaitTerm |XorTerm |MethodInvocationTerm |Sym-
bolicExpressionTerm |SymbolicAssignmentTerm
An expression opcode returns a value and can be used in an expression.
IntegerTypeOpcode := AddTerm |AndTerm |DecTerm |DerefOfTerm |DivideTerm |EISAIDTerm |
FindSetLeftBitTerm |FindSetRightBitTerm |FromBCDTerm |IncTerm |LAndTerm |LEqualTerm |
LGreaterTerm |LGreaterEqualTerm |LLessTerm |LLessEqualTerm |LNotTerm |LNotEqualTerm |
MatchTerm |ModTerm |MultiplyTerm |NAndTerm |NOrTerm |NotTerm |OrTerm |ShiftLeftTerm |
ShiftRightTerm |SubtractTerm |ToBCDTerm |ToIntegerTerm |XorTerm |SymbolicExpressionTerm
Integer opcodes are a subset of expression opcodes that return an Integer value and can be used in
an expression that evaluates to a constant. These opcodes may be evaluated at ASL compile-time.
To ensure that these opcodes will evaluate to a constant, the following rules apply: The term cannot
have a destination (target) operand, and must have either an IntegerTypeOpcode, StringTypeOpcode,
BufferTypeOpcode, ConstExprTerm, Integer, BufferTerm, Package, or String for all arguments.
StringTypeOpcode := ConcatTerm |DerefOfTerm |FprintfTerm |MidTerm |PrintfTerm |ToDecimal-
StringTerm |ToHexStringTerm |ToStringTerm
String type opcodes are a subset of expression opcodes that return a String value and can be used in
BufferTypeOpcode := ConcatTerm |ConcatResTerm |DerefOfTerm |MidTerm | ResourceTemplateTerm
|ToBufferTerm |ToPLDTerm |ToUUIDTerm |UnicodeTerm
Buffer type opcodes are a subset of expression opcodes that return a Buffer value and can be used in
19.2. ASL Language Grammar 833Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ReferenceTypeOpcode := RefOfTerm |DerefOfTerm |IndexTerm |IndexSymbolicTerm | UserTermObj
Reference type opcodes are a subset of expression opcodes that return a Reference value and can be
used in an expression. They cannot be evaluated at compile time. Reference type also includes the
UserTerm, which is a control method invocation.
19.2.6 ASL Primary (Terminal) Terms
AccessAsTerm :=
AccessAs (
AccessAttribute // Nothing | ByteConstExpr |AccessAttribKeyword |
ExtendedAccessAttribTerm
)
AcquireTerm :=
Acquire (
SyncObject, // SuperName => Mutex
TimeoutValue // WordConstExpr
) => Boolean // True means the operation timed out and the Mutex was not acquired
AddCompoundTerm := Addend1-Result // TermArg => Integer => Target += Addend2 // TermArg =>
Integer => Integer
AddSymbolicTerm := Addend1 // TermArg => Integer + Addend2 // TermArg => Integer => Integer
AddTerm :=
Add (
Addend1, // TermArg => Integer
Addend2, // TermArg => Integer
Result // Target
) => Integer
AliasTerm :=
Alias (
SourceObject, // NameString
AliasObject // NameString
)
AndCompoundTerm :=
Source1-Result // TermArg => Integer => Target
&=
Source2 // TermArg => Integer
=> Integer
AndSymbolicTerm :=
Source1 // TermArg => Integer
&
=> Integer
AndTerm :=
19.2. ASL Language Grammar 834Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
And (
Source1, // TermArg => Integer
Source2, // TermArg => Integer
ArgTerm := Arg0 | Arg1 | Arg2 | Arg3 | Arg4 | Arg5 | Arg6
BankFieldTerm :=
BankField (
RegionName, // NameString => OperationRegion
BankName, // NameString => FieldUnit
BankValue, // TermArg => Integer
UpdateRule // UpdateRuleKeyword
) {FieldUnitList }
BreakPointTerm := BreakPoint
BreakTerm := Break
BufferTerm :=
Buffer (
BuffSize // Nothing | TermArg => Integer
) {StringData |ByteList } => Buffer
CaseTerm :=
Case (
Value // DataObject
) {TermList }
ConcatResTerm :=
ConcatenateResTemplate (
Source1, // TermArg => Buffer
Source2, // TermArg => Buffer
) => Buffer
ConcatTerm :=
Concatenate (
Source1, // TermArg => SuperName
Source2, // TermArg => SuperName
) => Buffer | String
ConnectionTerm :=
Connection (
ConnectionResource // NameString |ResourceMacroTerm
)
CondRefOfTerm :=
19.2. ASL Language Grammar 835Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
CondRefOf (
Source // NameString |ArgTerm |LocalTerm |DerefOfTerm
Destination // Target
) => Boolean
ContinueTerm := Continue
CopyObjectTerm :=
CopyObject (
Source, // TermArg =>DataRefObject
Result, // NameString |LocalTerm |ArgTerm
) => DataRefObject
CreateBitFieldTerm :=
CreateBitField (
SourceBuffer, // TermArg => Buffer
BitIndex, // TermArg => Integer
BitFieldName // NameString
)
CreateByteFieldTerm :=
CreateByteField (
ByteIndex, // TermArg => Integer
ByteFieldName // NameString
)
CreateDWordFieldTerm :=
CreateDWordField (
DWordFieldName // NameString
)
CreateFieldTerm :=
CreateField (
NumBits, // TermArg => Integer
FieldName // NameString
)
CreateQWordFieldTerm :=
CreateQWordField (
QWordFieldName // NameString
)
CreateWordFieldTerm :=
19.2. ASL Language Grammar 836Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
CreateWordField (
WordFieldName // NameString
)
DataRegionTerm :=
DataTableRegion (
SignatureString, // TermArg =>String
OemIDString, // TermArg => String
OemTableIDString // TermArg => String
)
DebugTerm := Debug
DecSymbolicTerm :=
Minuend // SuperName => Integer
–
=> Integer
DecTerm :=
Decrement (
Minuend // SuperName

)
)
)
)
)
)
–
=> Integer
DecTerm :=
DefaultTerm := Default { TermList }
DeﬁnitionBlockTerm := | DeﬁnitionBlock ( | AMLFileName, // String | TableSignature, // String | Com-
plianceRevision, // ByteConst | OEMID, // String | TableID, // String | OEMRevision // DWordConst | )
{TermList}
DerefOfTerm := | DerefOf ( | Source // NameString |ArgTerm |LocalTerm |RefOfTerm |CondRefOfTerm
| //IndexTerm |MethodInvocationTerm | ) => DataRefObject
DeviceTerm := | Device ( | DeviceName // NameString | ) {TermList}
DivideCompoundTerm := | Dividend-Result // TermArg => Integer => Target | /= | Divisor // TermArg =>
Integer | => Integer
DivideSymbolicTerm :=
Dividend // TermArg => Integer
/
Divisor // TermArg => Integer
=> Integer
DivideTerm :=
Divide (
Dividend, // TermArg => Integer
Divisor, // TermArg => Integer
Remainder, // Target
) => Integer // Returns Result
19.2. ASL Language Grammar 837Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
EISAIDTerm :=
EISAID (
EisaIdString // StringData
) => DWordConst
ElseIfTerm :=
ElseIf (
Predicate // TermArg => Integer
) {TermList} ElseTerm
ElseTerm := Else { TermList } |ElseIfTerm | Nothing
EventTerm :=
Event (
EventName // NameString
)
ExternalTerm :=
External (
ObjName, // NameString
ObjType, // Nothing | ObjectTypeKeyword
ResultType, // Nothing | ParameterTypePackage
ParameterTypes // Nothing | ParameterTypesPackage
)
FatalTerm :=
Fatal (
Type, // ByteConstExpr
Code, // DWordConstExpr
Arg // TermArg => Integer
)
FieldTerm :=
Field (
FindSetLeftBitTerm :=
FindSetLeftBit (
Source, // TermArg => Integer
FindSetRightBitTerm :=
FindSetRightBit (
19.2. ASL Language Grammar 838Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ForTerm :=
For (
Initialize, // Nothing | TermArg =>ComputationalData
Predicate, // Nothing | TermArg => ComputationalData
Update // Nothing | TermArg => ComputationalData
) {TermList}
FprintfTerm :=
Fprintf (
TermArg ,
String ,
PrintfArgList
) => String
FromBCDTerm :=
FromBCD (
BCDValue, // TermArg => Integer
FunctionTerm :=
Function (
FunctionName, // NameString
ReturnType, // Nothing | ParameterTypePackage
IfTerm :=
If (
IncludeTerm :=
Include (
FilePathName // StringData
)
IncSymbolicTerm :=
Addend // SuperName => Integer
++
=> Integer
IncTerm :=
Increment (
Addend // SuperName
IndexFieldTerm :=
19.2. ASL Language Grammar 839Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
IndexField (
IndexName, // NameString =>FieldUnit
DataName, // NameString => FieldUnit
IndexSymbolicTerm :=
Source // TermArg => <string | buffer | packageterm >
[Index ] // TermArg => Integer
=> ObjectReference
IndexTerm :=
Index (
Source, // TermArg => <string | buffer | packageterm >
Index, // TermArg => Integer
) => ObjectReference
LAndSymbolicTerm :=
&&
=> Boolean
LAndTerm :=
LAnd (
LEqualSymbolicTerm :=
Source1 // TermArg =>ComputationalData
==
Source2 // TermArg => ComputationalData
=> Boolean
LEqualTerm :=
LEqual (
Source1, // TermArg =>ComputationalData
LGreaterEqualSymbolicTerm :=
>=
=> Boolean
19.2. ASL Language Grammar 840Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
LGreaterEqualTerm :=
LGreaterEqual (
LGreaterSymbolicTerm :=
>
=> Boolean
LGreaterTerm :=
LGreater (
LLessEqualSymbolicTerm :=
<=
=> Boolean
LLessEqualTerm :=
LLessEqual (
LLessSymbolicTerm :=
<
=> Boolean
LLessTerm :=
LLess (
LNotEqualTerm :=
LNotEqual (
LNotEqualSymbolicTerm :=
19.2. ASL Language Grammar 841Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
!=
=> Boolean
LNotSymbolicTerm :=
!
Source // TermArg => Integer
=> Boolean
LNotTerm :=
LNot (
LOrSymbolicTerm :=
||
=> Boolean
LoadTableTerm :=
LoadTable (
OemTableIDString, // TermArg => String
RootPathString, // Nothing | TermArg => String
ParameterPathString, // Nothing | TermArg => String
ParameterData // Nothing | TermArg => DataRefObject
) => Boolean // True (non-zero) means table was successfully loaded
LoadTerm :=
Load (
Object, // NameString
Result // SuperName => Boolean – True (non-zero) // means the table was successfully
loaded
) => Boolean // True (Ones) means the table was successfully loaded
LocalTerm := Local0 | Local1 | Local2 | Local3 | Local4 | Local5 | Local6 | Local7
LOrTerm :=
LOr (
MatchTerm :=
Match (
SearchPackage, // TermArg => Package
Op1, // MatchOpKeyword
MatchObject1, // TermArg => ComputationalData
19.2. ASL Language Grammar 842Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Op2, // MatchOpKeyword
MatchObject2, // TermArg => ComputationalData
StartIndex // TermArg => Integer
) => <ones | integer>
MethodTerm :=
Method (
MethodName, // NameString
NumArgs, // Nothing | ByteConstExpr
SerializeRule, // Nothing | SerializeRuleKeyword
SyncLevel, // Nothing | ByteConstExpr
MidTerm :=
Mid (
Source, // TermArg => <buffer | String >
Length, // TermArg => Integer
) => <buffer | string>
ModCompoundTerm :=
Dividend-Result // TermArg => Integer => Target
%=
=> Integer
ModSymbolicTerm :=
%
=> Integer
ModTerm :=
Mod (
MultiplyCompoundTerm :=
Multiplicand-Result // TermArg => Integer => Target
*=
Multiplier // TermArg => Integer
=> Integer
MultiplySymbolicTerm :=
Multiplicand // TermArg => Integer
19.2. ASL Language Grammar 843Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
*
=> Integer
MultiplyTerm :=
Multiply (
Multiplicand, // TermArg => Integer
Multiplier, // TermArg => Integer
MutexTerm :=
Mutex (
MutexName, // NameString
SyncLevel // ByteConstExpr
)
NameTerm :=
Name (
ObjectName, // NameString
Object // DataObject
)
NAndTerm :=
NAnd (
NoOpTerm := NoOp
NOrTerm :=
NOr (
NotifyTerm :=
Notify (
Object, // SuperName => <thermalzone | processor | device>
NotiﬁcationValue // TermArg => Integer
)
NotSymbolicTerm :=
~
=> Integer
NotTerm :=
19.2. ASL Language Grammar 844Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Not (
ObjectTypeTerm :=
ObjectType (
Object // NameString |ArgTerm |LocalTerm |DebugTerm |
//RefOfTerm |DerefOfTerm |IndexTerm
OffsetTerm :=
Offset (
ByteOffset // IntegerData
)
OpRegionTerm :=
Offset, // TermArg => Integer
Length // TermArg => Integer
)
OrCompoundTerm :=
|=
=> Integer
OrSymbolicTerm :=
|
=> Integer
OrTerm :=
Or (

Notify (
)
~
=> Integer
NotTerm :=
Not (
Offset (
)
)
|=
=> Integer
|
=> Integer
OrTerm :=
Or (
PackageTerm :=
Package (
NumElements // Nothing | ByteConstExpr |TermArg => Integer
) {PackageList} => Package
PLDKeyword := PLD_Revision | PLD_IgnoreColor | PLD_Red | PLD_Green | PLD_Blue | PLD_Width
| PLD_Height | PLD_UserVisible | PLD_Dock | PLD_Lid | PLD_Panel | PLD_VerticalPosition
19.2. ASL Language Grammar 845Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
| PLD_HorizontalPosition | PLD_Shape | PLD_GroupOrientation | PLD_GroupToken |
PLD_GroupPosition | PLD_Bay PLD_Ejectable | PLD_EjectRequired | PLD_CabinetNumber
PLDKeywordList := PLDKeyword = StringDataPLD_Revision | PLDKeyword = IntegerData-
PLD_Revision | PLDKeyword = StringDataPLD_Revision, PLDKeywordListPLD_Revision, PLD-
Keyword = IntegerDataPLD_Revision, PLDKeywordListPLD_Revision
PowerResTerm :=
PowerResource (
ResourceName, // NameString
SystemLevel, // ByteConstExpr
ResourceOrder // WordConstExpr
PrintfArgList := TermArg |TermArg ,PrintfArgList
PrintfTerm :=
Printf (
String,
) => String
ProcessorTerm :=
ProcessorName, // NameString
ProcessorID, // ByteConstExpr
PBlockAddress, // DWordConstExpr | Nothing (=0)
PblockLength // ByteConstExpr | Nothing (=0)
RawDataBufferTerm :=
RawDataBuffer (
BuffSize // Nothing | WordConst
) { ByteList} => RawDataBuffer
RefOfTerm :=
RefOf (
ReleaseTerm :=
Release (
SyncObject // SuperName
)
ResetTerm :=
Reset (
)
ReturnTerm :=
Return (
19.2. ASL Language Grammar 846Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Arg // Nothing | TermArg =>DataRefObject
)
ScopeTerm :=
Scope (
Location // NameString
ShiftLeftCompoundTerm :=
Source-Result // TermArg => Integer => Target
<<=
ShiftCount // TermArg => Integer
=> Integer
ShiftLeftSymbolicTerm :=
<<
=> Integer
ShiftLeftTerm :=
ShiftLeft (
ShiftCount, // TermArg => Integer
ShiftRightCompoundTerm :=
>>=
=> Integer
ShiftRightSymbolicTerm :=
>>
=> Integer
ShiftRightTerm :=
ShiftRight (
SignalTerm :=
Signal (
)
19.2. ASL Language Grammar 847Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
SizeOfTerm :=
SizeOf (
DataObject // SuperName => <string | buffer | package>
SleepTerm :=
Sleep (
MilliSeconds // TermArg => Integer
)
StallTerm :=
Stall (
MicroSeconds // TermArg => Integer
)
StoreSymbolicTerm :=
Destination // SuperName
=
Source // TermArg =>DataRefObject
=>DataRefObject
StoreTerm :=
Store (
SubtractCompoundTerm :=
Minuend-Result // TermArg => Integer => Target
-=
Subtrahend // TermArg => Integer
=> Integer
SubtractSymbolicTerm :=
Minuend // TermArg => Integer
=> Integer
SubtractTerm :=
Subtract (
Minuend, // TermArg => Integer
Subtrahend, // TermArg => Integer
SwitchTerm :=
Switch (
Predicate // TermArg =>ComputationalData
) {CaseTermList }
19.2. ASL Language Grammar 848Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ThermalZoneTerm :=
ThermalZone (
ThermalZoneName // NameString
TimerTerm := Timer => Integer
ToBCDTerm :=
ToBCD (
Value, // TermArg => Integer
ToBufferTerm :=
ToBuffer (
Data, // TermArg =>ComputationalData
) => ComputationalData
ToDecimalStringTerm :=
ToDecimalString (
) => String
ToHexStringTerm :=
ToHexString (
) => String
ToIntegerTerm :=
ToInteger (
ToPLDTerm :=
ToPLD (
PLDKeywordList
) => Buffer
ToStringTerm :=
ToString (
Source, // TermArg => Buffer
Length, // Nothing | TermArg => Integer
) => String
ToUUIDTerm :=
19.2. ASL Language Grammar 849Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ToUUID (
String //StringData
) => Buffer
UnicodeTerm :=
Unicode (
) => Buffer
UnloadTerm :=
Unload (
DDBHandle // SuperName
)
WaitTerm :=
Wait (
SyncObject, // SuperName => Event
TimeoutValue // TermArg => Integer
) => Boolean // True means timed-out
WhileTerm :=
While (
XorCompoundTerm :=
^=
=> Integer
XorSymbolicTerm :=
^
=> Integer
XOrTerm :=
XOr (
19.2. ASL Language Grammar 850Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.2.7 ASL Parameter Keyword Terms
AccessAttribKeyword := AttribQuick | AttribSendReceive | AttribByte | AttribBytes (n) | AttribRaw-
Bytes (n) | AttribRawProcessBytes (n) | AttribWord | AttribBlock |AttribProcessCall | AttribBlock-
ProcessCall // Note: Used for SMBus and GenericSerialBus BufferAcc only |
AccessTypeKeyword := AnyAcc | ByteAcc | WordAcc | DWordAcc | QWordAcc | BufferAcc
AddressKeyword := AddressRangeMemory | AddressRangeReserved | AddressRangeNVS | Address-
RangeACPI
AddressSpaceKeyword := RegionSpaceKeyword
AddressingModeKeyword := AddressingMode7Bit | AddressingMode10Bit
ByteLengthKeyword := DataBitsFive | DataBitsSix | DataBitsSeven | DataBitsEight | DataBitsNine
BusMasterKeyword := BusMaster | NotBusMaster
ClockPhaseKeyword := ClockPhaseFirst | ClockPhaseSecond
ClockPolarityKeyword := ClockPolarityLow | ClockPolarityHigh
DecodeKeyword := SubDecode | PosDecode
EndianKeyword := BigEndianing | LittleEndian
ExtendedAccessAttribKeyword := AttribBytes | AttribRawBytes | AttribRawProcessBytes // Note:
Used for GenericSerialBus BufferAcc only.
FlowControlKeyword := FlowControlNone | FlowControlXon | FlowControlHardware
InterruptTypeKeyword := Edge | Level
InterruptLevel := ActiveHigh | ActiveLow
InterruptLevelKeyword := ActiveHigh | ActiveLow | ActiveBoth
IODecodeKeyword := Decode16 | Decode10
IoRestrictionKeyword := IoRestrictionNone | IoRestrictionInputOnly | IoRestrictionOutputOnly | IoRe-
strictionNoneAndPreserve
LockRuleKeyword := Lock | NoLock
MatchOpKeyword := MTR | MEQ | MLE | MLT | MGE | MGT
MaxKeyword := MaxFixed | MaxNotFixed
MemTypeKeyword := Cacheable | WriteCombining | Prefetchable | NonCacheable
MinKeyword := MinFixed | MinNotFixed
ObjectTypeKeyword := UnknownObj | IntObj | StrObj | BuffObj | PkgObj | FieldUnitObj | DeviceObj |
EventObj | MethodObj | MutexObj | OpRegionObj | PowerResObj | ThermalZoneObj | BuffFieldObj
ParityKeyword := ParityTypeNone | ParityTypeSpace | ParityTypeMark | ParityTypeOdd | ParityType-
Even
PinConﬁgKeyword := PullDefault | PullUp | PullDown | PullNone
PolarityKeyword := PolarityHigh | PolarityLow
RangeTypeKeyword := ISAOnlyRanges | NonISAOnlyRanges | EntireRange
ReadWriteKeyword := ReadWrite | ReadOnly
19.2. ASL Language Grammar 851Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
RegionSpaceKeyword := SystemIO | SystemMemory | PCI_Conﬁg | EmbeddedControl | SMBus | Sys-
temCMOS | PciBarTarget | IPMI | GeneralPurposeIO | GenericSerialBus | PCC | PRM | FFixedHW
ResourceTypeKeyword := ResourceConsumer | ResourceProducer
SerializeRuleKeyword := Serialized | NotSerialized
ShareTypeKeyword := Shared | Exclusive | SharedAndWake | ExclusiveAndWake
SlaveModeKeyword := ControllerInitiated | DeviceInitiated
StopBitsKeyword := StopBitsZero | StopBitsOne | StopBitsOnePlusHalf | StopBitsTwo
TransferWidthKeyword := Width8Bit | Width16Bit | Width32Bit | Width64Bit | Width128Bit |
Width256Bit
TranslationKeyword := SparseTranslation | DenseTranslation
TypeKeyword := TypeTranslation | TypeStatic
UpdateRuleKeyword := Preserve | WriteAsOnes | WriteAsZeros
UserDefRegionSpace := IntegerData => 0x80 - 0xFF
XferTypeKeyword := Transfer8 | Transfer16 | Transfer8_16
WireModeKeyword := ThreeWireMode | FourWireMode
19.2.8 ASL Resource Template Terms
ResourceMacroList := Nothing | < resourcemacroterm resourcemacrolist >
ResourceMacroTerm := DMATerm |DWordIOTerm |DWordMemoryTerm |DWordSpaceTerm |End-
DependentFnTerm |ExtendedIOTerm |ExtendedMemoryTerm |ExtendedSpaceTerm |FixedD-
MATerm |FixedIOTerm |GpioIntTerm |GpioIOTerm |I2CSerialBusTerm |InterruptTerm |IOTerm
|IRQNoFlagsTerm |IRQTerm |Memory24Term |Memory32FixedTerm |Memory32Term |Pin-
ConﬁgTerm |PinFunctionTerm |PinGroupTerm |PinGroupConﬁgTerm |PinGroupFunctionTerm |

QWordIOTerm |QWordMemoryTerm |QWordSpaceTerm |RegisterTerm |SPISerialBusTerm |Start-
DependentFnTerm |StartDependentFnNoPriTerm |UARTSerialBusTerm |VendorLongTerm |Ven-
dorShortTerm |WordBusNumberTerm |WordIOTerm |WordSpaceTerm
DMATerm :=
DMA (
DMAType, // DMATypeKeyword (_TYP)
BusMaster, // BusMasterKeyword (_BM)
XferType, // XferTypeKeyword (_SIZ)
DescriptorName // Nothing | NameString
) {ByteList} // List of channels (0-7 bytes)
DWordIOTerm :=
DWordIO (
ResourceUsage, // Nothing (ResourceConsumer)| ResourceTypeKeyword
MinType, // Nothing (MinNotFixed) | MinKeyword (_MIF)
MaxType, // Nothing (MaxNotFixed) | MaxKeyword (_MAF)
Decode, // Nothing (PosDecode) | DecodeKeyword (_DEC)
RangeType, // Nothing (EntireRange) | RangeTypeKeyword (_RNG)
AddressGranularity, // DWordConstExpr (_GRA)
MinAddress, // DWordConstExpr (_MIN)
19.2. ASL Language Grammar 852Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
MaxAddress, // DWordConstExpr (_MAX)
AddressTranslation, // DWordConstExpr (_TRA)
AddressLength, // DWordConstExpr (_LEN)
ResourceSourceIndex, // Nothing | ByteConstExpr
ResourceSource, // Nothing | StringData
DescriptorName, // Nothing | NameString
TranslationType, // Nothing | TypeKeyword (_TTP)
TranslationDensity // Nothing | TranslationKeyword (_TRS)
)
DWordMemoryTerm :=
MemType, // Nothing (NonCacheable) | MemTypeKeyword (_MEM)
ReadWriteType, // ReadWriteKeyword (_RW)
MemoryRangeType, // Nothing | AddressKeyword (_MTP)
TranslationType // Nothing | TypeKeyword (_TTP)
)
DWordSpaceTerm :=
DWordSpace (
ResourceType, // ByteConstExpr (_RT), 0xC0 - 0xFF
TypeSpeciﬁcFlags, // ByteConstExpr (_TSF)
)
19.2. ASL Language Grammar 853Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
EndDependentFnTerm := EndDependentFn ()
ExtendedIOTerm :=
ExtendedIO (
AddressGranularity, // QWordConstExpr (_GRA)
MinAddress, // QWordConstExpr (_MIN)
MaxAddress, // QWordConstExpr (_MAX)
AddressTranslation, // QWordConstExpr (_TRA)
AddressLength, // QWordConstExpr (_LEN)
TypeSpeciﬁcAttributes, // Nothing | QWordConstExpr
)
ExtendedMemoryTerm :=
ExtendedMemory (
)
ExtendedSpaceTerm :=
ExtendedSpace (
19.2. ASL Language Grammar 854Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
TypeSpeciﬁcAttributes, // Nothing | QWordConstExpr (_ATT)
)
FixedDMATerm :=
FixedDMA (
DMAReq, // WordConstExpr (_DMA)
Channel, // WordConstExpr (_TYP)
XferWidth, // Nothing (Width32Bit) | TransferWidthKeyword (_SIZ)
)
FixedIOTerm :=
FixedIO (
AddressBase, // WordConstExpr (_BAS)
RangeLength, // ByteConstExpr (_LEN)
)
GpioIntTerm :=
GpioInt (
InterruptType, // InterruptTypeKeyword (_MOD)
InterruptLevel, // InterruptLevelKeyword (_POL)
ShareType, // Nothing (Exclusive) | ShareTypeKeyword (_SHR)
PinConﬁg, // PinConﬁgKeyword | ByteConstExpr (_PPI)
DeBounceTime // Nothing | WordConstExpr (_DBT)
ResourceSource, // StringData
ResourceSourceIndex, // Nothing (0) | ByteConstExpr
VendorData // Nothing | RawDataBuffer (_VEN)
) {DWordList} // List of GPIO pins (_PIN)
GpioIOTerm :=
GpioIO (
PinConﬁg, // PinConﬁgKeyword |ByteConstExpr (_PPIC)
DriveStrength // Nothing | WordConstExpr (_DRS)
IORestriction // Nothing (None) | IORestrictionKeyword (_IOR)
19.2. ASL Language Grammar 855Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
I2CSerialBusTerm :=
I2CSerialBusV2 (
SlaveAddress, // WordConstExpr (_ADR)
SlaveMode, // Nothing (ControllerInitiated) | SlaveModeKeyword (_SLV)
ConnectionSpeed, // DWordConstExpr (_SPE)
AddressingMode, // Nothing (AddressingMode7Bit) | AddressModeKeyword (_MOD)
)
InterruptTerm :=
Interrupt (
ResourceType, // Nothing (ResourceConsumer)| ResourceTypeKeyword
InterruptType, // InterruptTypeKeyword (_LL, _HE)
InterruptLevel, // InterruptLevelKeyword (_LL, _HE)
ShareType, // Nothing (Exclusive) ShareTypeKeyword (_SHR)
) {DWordList} // list of interrupts (_INT)
IOTerm :=
IO (
IODecode, // IODecodeKeyword (_DEC)
MinAddress, // WordConstExpr (_MIN)
MaxAddress, // WordConstExpr (_MAX)
Alignment, // ByteConstExpr (_ALN)
)
IRQNoFlagsTerm :=
IRQNoFlags (
) {ByteList} // list of interrupts (0-15 bytes)
IRQTerm :=
IRQ (
19.2. ASL Language Grammar 856Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Memory24Term :=
Memory24 (
MinAddress[23:8], // WordConstExpr (_MIN)
MaxAddress[23:8], // WordConstExpr (_MAX)
Alignment, // WordConstExpr (_ALN)
RangeLength, // WordConstExpr (_LEN)
)
Memory32FixedTerm :=
Memory32Fixed (
AddressBase, // DWordConstExpr (_BAS)
RangeLength, // DWordConstExpr (_LEN)
)
Memory32Term :=
Memory32 (

IRQTerm :=
IRQ (
Memory24 (
)
)
Memory32 (
Alignment, // DWordConstExpr (_ALN)
)
PinConﬁgTerm :=
PinConﬁg (
PinConﬁgType, // ByteData (_TYP)
PinConﬁgValue, // ByteData (_V AL)
) {DWordList} (_PIN)
PinFunctionTerm :=
PinFunction (
PinPullConﬁguration, // PinConﬁgKeyword | ByteConstExpr (_PPI)
FunctionNumber, // WordData
19.2. ASL Language Grammar 857Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PinGroupTerm :=
PinGroup (
ResourceLabel, // StringData
PinGroupConﬁgTerm :=
PinGroupConﬁg (
ResourceSourceLabel, // StringData
)
PinGroupFunctionTerm :=
PinGroupFunction (
FunctionNumber, // WordData (_FUN)
)
QWordIOTerm :=
QWordIO (
19.2. ASL Language Grammar 858Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
)
QWordMemoryTerm :=
QWordMemory (
)
QWordSpaceTerm :=
QWordSpace (
)
RegisterTerm :=
19.2. ASL Language Grammar 859Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Register (
AddressSpaceID, // AddressSpaceKeyword (_ASI)
RegisterBitWidth, // ByteConstExpr (_RBW)
RegisterOffset, // ByteConstExpr (_RBO)
RegisterAddress, // QWordConstExpr (_ADR)
AccessSize, // ByteConstExpr (_ASZ)
)
SPISerialBusTerm :=
SPISerialBusV2 (
DeviceSelection, // WordConstExpr (_ADR)
DeviceSelectionPolarity, // Nothing (PolarityLow) |
DevicePolarityKeyword (_DPL)
WireMode, // Nothing (FourWireMode) | WireModeKeyword (_MOD)
DataBitLength, // ByteConstExpr (_LEN)
ClockPolarity, // ClockPolarityKeyword (_POL)
ClockPhase, // ClockPhaseKeyword (_PHA)
)
StartDependentFnNoPriTerm :=
StartDependentFnNoPri () {ResourceMacroList}
StartDependentFnTerm :=
StartDependentFn (
CompatPriority, // ByteConstExpr (0-2)
PerfRobustPriority // ByteConstExpr (0-2)
) {ResourceMacroList}
UARTSerialBusTerm :=
UARTSerialBusV2(
Initial BaudRate, // DwordConstExpr (_SPE)
BitsPerByte, // Nothing (DataBitsEight) | DataBitsKeyword (_LEN)
StopBits, // Nothing (StopBitsOne) | StopBitsKeyword (_STB)
LinesInUse, // ByteConstExpr (_LIN)
IsBigEndian, // Nothing (LittleEndian) | EndianessKeyword (_END)
Parity, // Nothing (ParityTypeNone) | ParityTypeKeyword (_PAR)
FlowControl, // Nothing (FlowControlNone) | FlowControlKeyword (_FLC)
ReceiveBufferSize, // WordConstExpr (_RXL)
TransmitBufferSize, // WordConstExpr (_TXL)
19.2. ASL Language Grammar 860Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
VendorData // Nothing | Object (_VEN)
)
VendorLongTerm :=
VendorLong (
) {ByteList}
VendorShortTerm :=
VendorShort (
) {ByteList} // Up to 7 bytes
WordBusNumberTerm :=
AddressGranularity, // WordConstExpr (_GRA)
AddressTranslation, // WordConstExpr (_TRA)
AddressLength, // WordConstExpr (_LEN)
)
WordIOTerm :=
WordIO (
19.2. ASL Language Grammar 861Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
)
WordSpaceTerm :=
WordSpace (

)
)
19.3 ASL Concepts
This reference section is for developers who are writing ASL code while developing deﬁnition blocks for platforms.
19.3.1 ASL Names
This section describes how to encode object names using ASL.
The following table lists the characters legal in any position in an ASL object name. ASL names are not case-sensitive
and will be converted to upper case.
Table 19.2: Named Object Reference Encodings
Value Description Title
0x41-0x5A, 0x5F, 0x61-0x7A Lead character of name (‘A’-‘Z’, ‘_’ , ‘a’-‘z’) LeadNameChar
0x30-0x39, 0x41-0x5A, 0x5F,
0x61-0x7ANon-lead (trailing) character of name (‘A’-‘Z’, ‘_’, ‘a’-
‘z’, ‘0’-‘9’)NameChar
The following table lists the name modiﬁers that can be preﬁxed to an ASL name.
Table 19.3: Deﬁnition Block Name Modiﬁer Encodings
Value Description NamePreﬁx := Follows by. . .
0x5C Namespace root (‘') RootPreﬁx Name
0x5E Parent namespace (‘^’) ParentPreﬁx ParentPreﬁx or Name
19.3. ASL Concepts 862Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.3.1.1 _T_x Reserved Object Names
The ACPI speciﬁcation reserves object names with the preﬁx _T_ for internal use by the ASL compiler. The ASL
compiler may, for example, use these objects to store temporary values when implementing translation of complicated
control structures into AML. The ASL compiler must declare _T_x objects normally (using Name) and must not deﬁne
them more than once within the same scope.
19.3.2 ASL Literal Constants
This section describes how to encode integer and string constants using ASL.
19.3.2.1 Integers
DigitChar := '0'-'9'
LeadDigitChar := '1'-'9'
OctalDigitChar := '0'-'7'
HexDigitChar := DigitChar \| 'A'-'F' \| 'a'-'f'
Integer := DecimalConst \| OctalConst \| HexConst
DecimalConst := LeadDigitChar \| <decimalconst digitchar>
OctalConst := '0' \| <octalconst octaldigitchar>
HexConst := <0x hexdigitchar> \| <0x hexdigitchar> \| <HexConst HexDigitChar>
Numeric constants can be speciﬁed in decimal, octal, or hexadecimal. Octal constants are preceded by a leading zero
(0), and hexadecimal constants are preceded by a leading zero and either a lower or upper case ‘x’. In some cases, the
grammar speciﬁes that the number must evaluate to an integer within a limited range, such as 0x00-0xFF, and so on.
19.3.2.2 Strings
String := '"' Utf8CharList '"'
Utf8CharList := Nothing | <escapesequence utf8charlist> | <Utf8Char Utf8CharList>
Utf8Char := 0x01-0x21 |
0x23-0x5B |
0x5D-0x7F |
0xC2-0xDF 0x80-0xBF |
0xE0 0xA0-0xBF 0x80-0xBF |
0xE1-0xEC 0x80-0xBF 0x80-0xBF |
0xED 0x80-0x9F 0x80-0xBF |
0xEE-0xEF 0x80-0xBF 0x80-0xBF |
0xF0 0x90-0xBF 0x80-0xBF 0x80-0xBF |
0xF1-0xF3 0x80-0xBF 0x80-0xBF 0x80-0xBF |
0xF4 0x80-0x8F 0x80-0xBF 0x80-0xBF
EscapeSeq := SimpleEscapeSeq | OctalEscapeSeq | HexEscapeSeq
SimpleEscapeSeq := \' | \" | \a | \b | \f | \n | \r | \t | \v | \\
OctalEscapeSeq := \ OctalDigitChar |
\ OctalDigitChar OctalDigitChar |
\ OctalDigitChar OctalDigitChar OctalDigitChar
HexEscapeSeq := \x HexDigitChar |
19.3. ASL Concepts 863Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
\x HexDigitChar HexDigitChar
String literals consist of zero or more ASCII characters surrounded by double quotation marks (“). A string literal
represents a sequence of characters that, taken together, form a null-terminated string. After all adjacent strings in the
constant have been concatenated, a null character is appended.
Strings in the source ﬁle may be encoded using the UTF-8 encoding scheme as deﬁned in the Unicode 4.0 speciﬁcation.
UTF-8 is a byte-oriented encoding scheme, where some characters take a single byte and others take multiple bytes.
The ASCII character values 0x01-0x7F take up exactly one byte.
However, only one operator currently supports UTF-8 strings: Unicode. Since string literals are deﬁned to contain
only non-null character values, both Hex and Octal escape sequence values must be non-null values in the ASCII
range 0x01 through 0xFF. For arbitrary byte data (outside the range of ASCII values), the Buffer object should be
used instead.
Since the backslash is used as the escape character and also the namespace root preﬁx, any string literals that are to
contain a fully qualiﬁed namepath from the root of the namespace must use the double backslash to indicate this:
Name (_EJD, "\\_SB.PCI0.DOCK1")
The double backslash is only required within quoted string literals.
Since double quotation marks are used close a string, a special escape sequence (") is used to allow quotation marks
within strings. Other escape sequences are listed in the table below.
Table 19.4: ASL Escape Sequences
Escape Sequence ASCII Character
\a 0x07 (BEL)
\b 0x08 (BS)
\f 0x0C (FF)
\n 0x0A (LF)
\r 0x0D (CR)
\t 0x09 (TAB)
\v 0x0B (VT)
\” 0x22 (“)
\’ 0x27 (‘)
\ \ 0x5C ()
Since literal strings are read-only constants, the following ASL statement (for example) is not supported:
Store ("ABC", "DEF")
However, the following sequence of statements is supported:
Name (STR, "DEF")
...
Store ("ABC", STR)
19.3. ASL Concepts 864Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.3.3 ASL Resource Templates
ASL includes some macros for creating resource descriptors. The ResourceTemplate macro creates a Buffer in which
resource descriptor macros can be listed. The ResourceTemplate macro automatically generates an End descriptor and
calculates the checksum for the resource template. The format for the ResourceTemplate macro is as follows:
{
// List of resource macros
}
The following is an example of how these macros can be used to create a resource template that can be returned from
a _PRS control method:
Name (PRS0, ResourceTemplate ()
{
StartDependentFn (1, 1)
{
IRQ (Level, ActiveLow, Shared) {10, 11}
DMA (TypeF, NotBusMaster, Transfer16) {4}
IO (Decode16, 0x1000, 0x2000, 0, 0x100)
IO (Decode16, 0x5000, 0x6000, 0, 0x100, IO1)
}
{
IRQ (Level, ActiveLow, Shared) {}
DMA (TypeF, NotBusMaster, Transfer16){5}
IO (Decode16, 0x3000, 0x4000, 0, 0x100)
IO (Decode16, 0x5000, 0x6000, 0, 0x100, IO2)
}
EndDependentFn ()
})
Occasionally, it is necessary to change a parameter of a descriptor in an existing resource template at run-time (i.e.,
during a method execution.) To facilitate this, the descriptor macros optionally include a name declaration that can be
used later to refer to the descriptor. When a name is declared with a descriptor, the ASL compiler will automatically
create ﬁeld names under the given name to refer to individual ﬁelds in the descriptor.
The offset returned by a reference to a resource descriptor ﬁeld name is either in units of bytes (for 8-, 16-, 32-, and
64-bit ﬁeld widths) or in bits (for all other ﬁeld widths). In all cases, the returned offset is the integer offset (in either
bytes or bits) of the name from the ﬁrst byte (offset 0) of the parent resource template.
For example, given the above resource template, the following code changes the minimum and maximum addresses
for the I/O descriptor named IO2:
CreateWordField (PRS0, IO2._MIN, IMIN)
Store (0xA000, IMIN)
CreateWordField (PRS0, IO2._MAX, IMAX)
Store (0xB000, IMAX)
The resource template macros for each of the resource descriptors are listed below, after the table that deﬁnes the
resource descriptor. The resource template macros are formally deﬁned in ASL Macros for Resource Descriptors
The reserved names (such as _MIN and _MAX) for the ﬁelds of each resource descriptor are deﬁned in the appropriate
table entry of the table that deﬁnes that resource descriptor.
19.3. ASL Concepts 865Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.3.4 ASL Macros
ASL compilers support built in macros to assist in various ASL coding operations. These macros do not have a
corresponding AML opcode, but are instead fully processed by the compiler itself, and may result in the generation
of AML opcodes for other ASL/AML operators. The following table lists some of the supported directives and an
explanation of their function.
The ASL language provides a wide variety of data types and operators that manipulate data. It also provides mecha-
nisms for both explicit and implicit conversion between the data types when used with ASL operators.
Each of the available ASL macros are described below.
EISAID (TextID)
Converts and compresses the 7-character text argument into its corresponding 4-byte numeric EISA ID encoding
(Integer). This can be used when declaring IDs for devices that are EISA IDs.
The algorithm used to convert the TextID is as shown in the following example:
Starting with a seven character input string “PNP0303”, we want to create a DWordConst. This string

contains a three character manufacturer code “PNP”, a three character hex product identiﬁer “030”, and a
one character revision identiﬁer “3”.
The compressed manufacturer code is created as follows:
1) Find hex ASCII value for each letter
2) Subtract 40h from each ASCII value
3) Retain 5 least signiﬁcant bits for each letter and discard remaining 0’s:
Byte 0:
Bit 7: reserved (0)
Bit 6-2: 1st character of compressed mfg code “P”
Bit 1-0: Upper 2 bits of 2nd character of mfg code “N”
Byte 1:
Bit 7-5: Lower 3 bits of 2nd character of mfg code “N”
Bit 4-0: 3rd character of mfg code “P”
Byte 2:
Bit 7-4: 1st hex digit of product number “0”
Bit 3-0: 2nd hex digit of product number “3”
Byte 3:
Bit 7-4: 3rd hex digit of product number “0”
Bit 3-0: 4th hex digit of product number “3”
For (Initialize, Predicate, Update) {TermList}
Implements a standard For() loop by converting the For() arguments and TermList into an AML While
loop.
Fprintf (Target, FormatString, FormatArgs)
Converts a format string to a series of string Concatenate operations and stores the result to a Named
Object (Target).
Printf (FormatString, FormatArgs)
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Converts a format string to a series of string Concatenate operations and automatically stores the result to
the Debug Object.
Used to supply Plug and Play resource descriptor information in human readable form, which is then
translated into the appropriate binary Plug and Play resource descriptor encodings in a Resource Template
Buffer object. For more information about resource descriptor encodings, (See: Resource Data Types for
ACPI ).
ToPLD (PLDKeywordList)
Converts a PLD (Physical Location of Device) Keyword List into a _PLD Buffer object.
ToUUID (AsciiString)
Converts an ASCII UUID or GUID string to an encoded 128-bit Buffer object.
Unicode (StringData)
Converts a standard ASCII string to a Unicode string returned in a Buffer object.
19.3.5 ASL Data Types
ASL provides a wide variety of data types and operators that manipulate data. It also provides mechanisms for both
explicit and implicit conversion between the data types when used with ASL operators.
The table below describes each of the available ASL data types.
Table 19.5: Summary of ASL Data Types
ASL Data Type Description
[Uninitialized] No assigned type or value. This is the type of all control method LocalX variables and
unused ArgX variables at the beginning of method execution, as well as all uninitialized
Package elements. Uninitialized objects must be initialized (via Store or CopyObject) be-
fore they may be used as source operands in ASL expressions.
Buffer An array of bytes. Uninitialized elements are zero by default.
Buffer Field Portion of a buffer created using CreateBitField, CreateByteField, CreateWordField, Cre-
ateQWordField, CreateField, or returned by the Index operator.
Debug Object Debug output object. Formats an object and prints it to the system debug port. Has no effect
if debugging is not active.
Device Device or bus object
Event Event synchronization object
Field Unit (within
an Operation Re-
gion)Portion of an address space, bit-aligned and of one-bit granularity. Created using Field,
BankField, or IndexField.
Integer Ann-bit little-endian unsigned integer. In ACPI 1.0 this was 32 bits. In ACPI 2.0 and later,
this is 64 bits. The Integer (DWORD) designation indicates that only the lower 32 bits have
meaning and the upper 32 bits of 64-bit integers must be zero (masking of upper bits is not
required).
Integer Constant Created by the ASL terms “Zero”, “One”, “Ones”, and “Revision”.
Method Control Method (Executable AML function)
Mutex Mutex synchronization object
Object Reference Reference to an object created using the RefOf, Index, or CondRefOf operators
Operation Region Operation Region (A region within an Address Space)
Package Collection of ASL objects with a ﬁxed number of elements (up to 255).
Power Resource Power Resource description object
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Table 19.5 – continued from previous page
Processor Processor description object
RawDataBuffer An array of bytes. Uninitialized elements are zero by default. RawDataBuffer does not
contain any AML encoding bytes, only the raw bytes.
String Null-terminated ASCII string.
Thermal Zone Thermal Zone description object
Note: Compatibility Note: The ability to store and manipulate object references was introduced in ACPI 2.0. In
ACPI 1.0 references could not be stored in variables, passed as parameters or returned from functions.
19.3.5.1 Data Type Conversion Overview
ASL provides two mechanisms to convert objects from one data type to another data type at run-time (during execution
of the AML interpreter). The ﬁrst mechanism, Explicit Data Type Conversion, allows the use of explicit ASL operators
to convert an object to a different data type. The second mechanism, Implicit Data Type Conversion, is invoked by the
AML interpreter when it is necessary to convert a data object to an expected data type before it is used or stored.
The following general rules apply to data type conversions:
• Input parameters are always subject to implicit data type conversion (also known as implicit source operand
conversion) whenever the operand type does not match the expected input type.
• Output (target) parameters for all operators except the explicit data conversion operators are subject to implicit
data type conversion (also known as implicit result object conversion) whenever the target is an existing named
object or named ﬁeld that is of a different type than the object to be stored.
• Output parameters for the explicit data conversion operators, as well as output parameters that refer to a method
local or argument (LocalX or ArgX) are not subject to implicit type conversion.
Both of these mechanisms (explicit and implicit conversion) are described in detail in the sections that follow.
19.3.5.2 Explicit Data Type Conversions
The following ASL operators are provided to explicitly convert an object from one data type to another:
ToBuffer
Convert an Integer, String, or Buffer to an object of type Buffer
ToDecimalString
Convert an Integer, String, or Buffer to an object of type String. The string contains the ASCII represen-
tation of the decimal value of the source operand.
ToHexString
tation of the hexadecimal value of the source operand.
ToInteger
Convert an Integer, String, or Buffer to an object of type Integer.
ToString
Copy directly and convert a Buffer to an object of type String.
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The following ASL operator is provided to copy and transfer objects with an explicit result conversion of the type of
the target to match the type of the source object:
CopyObject
Explicitly store a copy of the operand object to the target name. No implicit type conversion is performed.
(This operator is used to avoid the implicit conversion inherent in the ASL Store operator.)
19.3.5.3 Implicit Data Type Conversions
Automatic or Implicit type conversions can take place at two different times during the execution of an ASL operator.
First, it may be necessary to convert one or more of the source operands to the data type(s) expected by the ASL
operator. Second, the result of the operation may require conversion before it is stored into the destination. (Many of
the ASL operators can store their result optionally into an object speciﬁed by the last parameter. In these operators,
if the destination is speciﬁed, the action is exactly as if a Store operator had been used to place the result in the
destination.)
Such data conversions are performed by an AML interpreter during execution of AML code and are known collec-
tively as Implicit Operand Conversions. As described brieﬂy above, there are two different types of implicit operand
conversion:
1. Conversion of a source operand from a mismatched data type to the correct data type required by an ASL
operator, called Implicit Source Conversion. This conversion occurs when a source operand must be converted
to the operand type expected by the operator. Any or all of the source operands may be converted in this manner
before the execution of the ASL operator can proceed.
2. Conversion of the result of an operation to the existing type of a target operand before it is stored into the target
operand, called Implicit Result Conversion. This conversion occurs when the target is a ﬁxed type such as a
named object or a ﬁeld. When storing to a method Local or Arg, no conversion is performed or required because
these data types are of variable type (the store simply overwrites any existing object and the existing type).

The following ASL operator is provided to copy and transfer objects with an implicit result conversion to the existing
type of the target object:
Store
Store a copy of the operand object to the target name. Implicit result conversion is performed if the target
name is of a ﬁxed data type (see above). However, Stores to method locals and arguments do not perform
implicit conversion and are therefore the same as using CopyObject.
19.3.5.4 Implicit Source Operand Conversion
During the execution of an ASL operator, each source operand is processed by the AML interpreter as follows:
• If the operand is of the type expected by the operator, no conversion is necessary.
• If the operand type is incorrect, attempt to convert it to the proper type.
• For the Concatenate operator and logical operators (LEqual, LGreater, LGreaterEqual, LLess, LLessEqual,
and LNotEqual), the data type of the ﬁrst operand dictates the required type of the second operand, and for
Concatenate only, the type of the result object. (The second operator is implicitly converted, if necessary, to
match the type of the ﬁrst operand.)
• If conversion is impossible, abort the running control method and issue a fatal error.
An implicit source conversion will be attempted anytime a source operand contains a data type that is different that
the type expected by the operator. For example:
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Store ("5678", Local1)
Add (0x1234, Local1, BUF1)
In the Add statement above, Local1 contains a String object and must undergo conversion to an Integer object before
the Add operation can proceed.
In some cases, the operator may take more than one type of operand (such as Integer and String). In this case,
depending on the type of the operand, the highest priority conversion is applied. The table below describes the source
operand conversions available. For example:
Store (Buffer (1) {}, Local0)
Name (ABCD, Buffer (10) {1, 2, 3, 4, 5, 6, 7, 8, 9, 0})
CreateDWordField (ABCD, 2, XYZ)
Name (MNOP, "1234")
Concatenate (XYZ, MNOP, Local0)
The Concatenate operator can take an Integer, Buffer or String for its ﬁrst two parameters and the type of the ﬁrst
parameter determines how the second parameter will be converted. In this example, the ﬁrst parameter is of type Buffer
Field (from the CreateDWordField operator). What should it be converted to: Integer, Buffer or String? According
to the table Object Conversion Rules the highest priority conversion is to Integer. Therefore, both of the following
objects will be converted to Integers:
XYZ (0x05040302)
MNOP (0x31, 0x32, 0x33, 0x34)
And will then be joined together and the resulting type and value will be:
Buffer (0x02, 0x03, 0x04, 0x05, 0x31, 0x32, 0x33, 0x34)
19.3.5.5 Implicit Result Object Conversion
For all ASL operators that generate and store a result value (including the Store operator), the result object is processed
and stored by the AML interpreter as follows:
• If the ASL operator is one of the explicit conversion operators (ToString, ToInteger, etc., and the CopyObject
operator), no conversion is performed. (In other words, the result object is stored directly to the target and
completely overwrites any existing object already stored at the target.)
• If the target is a method local or argument (LocalX or ArgX), no conversion is performed and the result is stored
directly to the target.
• If the target is a ﬁxed type such as a named object or ﬁeld object, an attempt is made to convert the source to the
existing target type before storing.
An implicit result conversion can occur anytime the result of an operator is stored into an object that is of a ﬁxed type.
Name (BUF1, Buffer (10))
Add (0x1234, 0x789A, BUF1)
Since BUF1 is a named object of ﬁxed type Buffer , the Integer result of the Add operation must be converted to a
Buffer before it is stored into BUF1.
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19.3.5.6 Data Types and Type Conversions
The following table lists the available ASL data types and the available data type conversions (if any) for each. The
entry for each data type is fully cross-referenced, showing both the types to which the object may be converted as well
as all other types that may be converted to the data type.
The allowable conversions apply to both explicit and implicit conversions.
Table 19.6: Data Types and Type Conversions
ASL Data Type Can be implicitly or explicitly con-
verted to these Data Types (In priority
order)Can be implicitly or explicitly con-
verted from these Data Types
[Uninitialized] None. Causes a fatal error when used as a
source operand in any ASL statement.Integer, String, Buffer, Package, Object Ref-
erence
Buffer Integer, String, Debug Object Integer, String
Buffer Field Integer, Buffer, String, Debug Object Integer, Buffer, String
Debug Object None. Causes a fatal error when used as a
source operand in any ASL statement.Integer, String, Buffer, Package, Field Unit,
Buffer Field
Device None None
Event None None
gion)Integer, Buffer, String, Debug Object Integer, Buffer, String
Integer Buffer, Buffer Field, Field Unit, String, De-
bug ObjectBuffer, String
Integer Constant Integer, Debug Object None. Also, storing any object to a constant
is a no-op, not an error.
Method None None
Mutex None None
Object Reference None None
Operation Region None None
Package Debug Object None
String Integer, Buffer, Debug Object Integer, Buffer
Power Resource None None
RawDataBuffer None None
Thermal Zone None None
19.3.5.7 Data Type Conversion Rules
The following table presents the detailed data conversion rules for each of the allowable data type conversions. These
conversion rules are implemented by the AML Interpreter and apply to all conversion types – explicit conversions,
implicit source conversions, and implicit result conversions.
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Table 19.7: Object Conversion Rules
To convert from
an object of this
Data TypeTo an object of
this Data TypeThis action is performed by the AML Interpreter
Buffer Buffer Field The contents of the buffer are copied to the Buffer Field. If the
buffer is smaller than the size of the buffer ﬁeld, it is zero extended.
If the buffer is larger than the size of the buffer ﬁeld, the upper
bits are truncated. Compatibility Note: This conversion was ﬁrst
introduced in ACPI 2.0. The behavior in ACPI 1.0 was undeﬁned.
Buffer Debug Object Each buffer byte is displayed as a hexadecimal integer, delimited by
spaces and/or commas.
Buffer Field Unit The entire contents of the buffer are copied to the Field Unit. If the
buffer is larger (in bits) than the size of the Field Unit, it is broken
into pieces and completely written to the Field Unit, lower chunks
ﬁrst. If the buffer (or the last piece of the buffer, if broken up) is
smaller than the size of the Field Unit, it is zero extended before
being written.
Buffer Integer If no integer object exists, a new integer is created. The contents of
the buffer are copied to the Integer, starting with the least-signiﬁcant
bit and continuing until the buffer has been completely copied — up
to the maximum number of bits in an Integer. The size of an Integer
is indicated by the Deﬁnition Block table header’s Revision ﬁeld. A
Revision ﬁeld value less than 2 indicates that the size of an Integer
is 32 bits. A value greater than or equal to 2 signiﬁes that the size
of an Integer is 64 bits. If the buffer is smaller than the size of an
integer, it is zero extended. If the buffer is larger than the size of
an integer, it is truncated. Conversion of a zero-length buffer to an
integer is not allowed.
Buffer String If no string object exists, a new string is created. If the string al-
ready exists, it is completely overwritten and truncated or extended
to accommodate the converted buffer exactly. The entire contents
of the buffer are converted to a string of two-character hexadecimal
numbers, each separated by a space. A zero-length buffer will be
converted to a null (zero-length) string.
Buffer Field [See the Integer and
Buffer Rules]If the Buffer Field is smaller than or equal to the size of an Integer
(in bits), it will be treated as an Integer. Otherwise, it will be treated
as a buffer. The size of an Integer is indicated by the Deﬁnition
Block table header’s Revision ﬁeld. A Revision ﬁeld value less than
2 indicates that the size of an Integer is 32 bits. A value greater than
or equal to 2 signiﬁes that the size of an Integer is 64 bits. (See the
conversion rules for the Integer and Buffer data types.)
Field Unit [See the Integer and
Buffer Rules]If the Field Unit is smaller than or equal to the size of an Integer (in
bits), it will be treated as an Integer. If the Field Unit is larger than

the size of an Integer, it will be treated as a Buffer. The size of an
Integer is indicated by the Deﬁnition Block table header’s Revision
ﬁeld. A Revision ﬁeld value less than 2 indicates that the size of an
Integer is 32 bits. A value greater than or equal to 2 signiﬁes that
the size of an Integer is 64 bits. (See the conversion rules for the
Integer and Buffer data types.)
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Table 19.7 – continued from previous page
Integer Buffer If no buffer object exists, a new buffer object is created based on the
size of the integer (4 bytes for 32-bit integers and 8 bytes for 64-bit
integers). If a buffer object already exists, the Integer overwrites the
entire Buffer object. If the integer requires more bits than the size of
the Buffer, then the integer is truncated before being copied to the
Buffer. If the integer contains fewer bits than the size of the buffer,
the Integer is zero-extended to ﬁll the entire buffer.
Integer Buffer Field The Integer overwrites the entire Buffer Field. If the integer is
smaller than the size of the buffer ﬁeld, it is zero-extended. If the
integer is larger than the size of the buffer ﬁeld, the upper bits are
truncated. Compatibility Note: This conversion was ﬁrst introduced
in ACPI 2.0. The behavior in ACPI 1.0 was undeﬁned.
Integer Debug Object The integer is displayed as a hexadecimal value.
Integer Field Unit The Integer overwrites the entire Field Unit. If the integer is smaller
than the size of the buffer ﬁeld, it is zero-extended. If the integer is
larger than the size of the buffer ﬁeld, the upper bits are truncated.
Integer String If no string object exists, a new string object is created based on the
size of the integer (8 characters for 32-bit integers and 16 characters
for 64-bit integers). If the string already exists, it is completely over-
written and truncated or extended to accommodate the converted
integer exactly. In either case, the entire integer is converted to a
string of hexadecimal ASCII characters.
Package Package If no package object exists, a new package object is created. If the
package already exists, it is completely overwritten and truncated
or extended to accommodate the source package exactly. Any and
all existing valid (non-null) package elements of the target package
are deleted, and the entire contents of the source package are copied
into the target package.
Package Debug Object Each element of the package is displayed based on its type.
String Buffer If no buffer object exists, a new buffer object is created. If a buffer
object already exists, it is completely overwritten. If the string is
longer than the buffer, the string is truncated before copying. If the
string is shorter than the buffer, the remaining buffer bytes are set
to zero. In either case, the string is treated as a buffer, with each
ASCII string character copied to one buffer byte, including the null
terminator. A null (zero-length) string will be converted to a zero-
length buffer.
String Buffer Field The string is treated as a buffer. If this buffer is smaller than the size
of the buffer ﬁeld, it is zero extended. If the buffer is larger than
the size of the buffer ﬁeld, the upper bits are truncated. Compati-
bility Note: This conversion was ﬁrst introduced in ACPI 2.0. The
behavior in ACPI 1.0 was undeﬁned.
String Debug Object Each string character is displayed as an ASCII character.
String Field Unit Each character of the string is written, starting with the ﬁrst, to the
Field Unit. If the Field Unit is less than eight bits, then the upper
bits of each character are lost. If the Field Unit is greater than eight
bits, then the additional bits are zeroed.
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String Integer If no integer object exists, a new integer is created. The integer is
initialized to the value zero and the ASCII string is interpreted as
a hexadecimal constant. Each string character is interpreted as a
hexadecimal value (‘0’-‘9’, ‘A’-‘F’, ‘a’-‘f’), starting with the ﬁrst
character as the most signiﬁcant digit, and ending with the ﬁrst non-
hexadecimal character, end-of-string, or when the size of an integer
is reached (8 characters for 32-bit integers and 16 characters for 64-
bit integers). Note: the ﬁrst non-hex character terminates the con-
version without error, and a “0x” preﬁx is not allowed. Conversion
of a null (zero-length) string to an integer is not allowed.
19.3.5.8 Rules for Storing and Copying Objects
The table below lists the actions performed when storing objects to different types of named targets. ASL provides the
following types of “store” operations:
• The Store operator is used to explicitly store an object to a location, with implicit conversion support of the
source object.
• Many of the ASL operators can store their result optionally into an object speciﬁed by the last parameter. In
these operators, if the destination is speciﬁed, the action is exactly as if a Store operator had been used to place
the result in the destination.
• The CopyObject operator is used to explicitly store a copy of an object to a location, with no implicit conversion
support.
Table 19.8: Object Storing and Copying Rules
When Storing anobject
of any datatype to this
type ofTarget locationThis action is performed by the
Store operator or any ASL oper-
ator with a Target operandThis action is performed by the
CopyObject operator
Method ArgX variable The object is copied to the destina-
tion with no conversion applied, with
one exception. If the ArgX con-
tains an Object Reference, an automatic
de-reference occurs and the object is
copied to the target of the Object Refer-
ence instead of overwriting the contents
of ArgX.The object is copied to the destina-
of ArgX.
Method LocalXvariable The object is copied to the destination
with no conversion applied. Even if Lo-
calX contains an Object Reference, it is
overwritten.The object is copied to the destination
overwritten.
Field Unit or BufferField The object is copied to the destination
after implicit result conversion is ap-
plied.Fields permanently retain their type and
cannot be changed. Therefore, Copy-
Object can only be used to copy an ob-
ject of type Integer or Buffer to ﬁelds.
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Table 19.8 – continued from previous page
Named data object The object is copied to the destination
plied to match the existing type of the
named location.The object and type are copied to the
named location.
19.3.5.8.1 ArgX Objects
1. Read from ArgX parameters
•ObjectReference - Automatic dereference, return the target of the reference. Use of DeRefOf returns the same.
•Buffer - Return the Buffer. Can create an Index, Field, or Reference to the buffer.
•Package - Return the Package. Can create an Index or Reference to the package.
•All other object types - Return the object.
Example method invocation for the table below:
MTHD (RefOf (Obj), Buf, Pkg, Obj)
Table 19.9: Reading from ArgX Objects
Parameter MTHD ArgX Type Read operation on ArgX Result of read
RefOf (Obj), Reference to object Obj Store (Arg0, . . . ) Obj
" " CopyObject (Arg0, . . . ) Obj
" " DeRefOf (Arg0) Obj
Buf, Buffer Store (Arg1, ..) Buf
" " CopyObject (Arg1, . . . ) Buf
" " Index (Arg1, . . . ) Index (Buf)
" " Field (Arg1, . . . ) Field (Buf)
Pkg Package Store (Arg2, . . . ) Pkg
" " CopyObject (Arg2, . . . ) Pkg
" " Index (Arg2, . . . ) Index (Pkg)
Obj All other object types Store (Arg3, . . . ) Obj
" " CopyObject (Arg3, . . . ) Obj
2. Store to ArgX parameters
•ObjectReference objects - Automatic dereference, copy the object and overwrite the ﬁnal target.
•All other object types - Copy the object and overwrite the ArgX variable. (Direct writes to buffer or
package ArgX parameters will also simply overwrite ArgX)
Table 19.10: Writing to ArgX Objects
Current type ofArgX Object to be written Write operation on
ArgXResult of write (in
ArgX)

ArgX)
RefOf (OldObj) Obj (any type) Store (. . . , ArgX) RefOf (copy of Obj)
" " CopyObject (. . . , ArgX) RefOf (copy of Obj)
All other object types Obj (Any type) Store (. . . , ArgX) Copy of Obj
" " CopyObject (. . . , ArgX) Copy of Obj
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Note: RefOf (ArgX) returns a reference to ArgX.
19.3.5.8.2 LocalX Objects
1. Read from LocalX variables
•ObjectReference - If performing a DeRefOf return the target of the reference. Otherwise, return the reference.
•All other object types - Return a the object
Table 19.11: Reading from LocalX Objects
Current LocalX Type Read operation on LocalX Result of read
RefOf (Obj) Store (LocalX, . . . ) RefOf (Obj)
" CopyObject (LocalX, . . . ) RefOf (Obj)
" DeRefOf (LocalX) Obj
Obj (All other types) Store (LocalX, . . . ) Obj
" CopyObject (LocalX, . . . ) Obj
2. Store to LocalX variables
•All object types - Delete any existing object in LocalX ﬁrst, then store a copy of the object.
Table 19.12: Writing to LocalX Objects
Current LocalX-
TypeObject to be writ-
tenWrite operation on LocalX Result of write (in LocalX)
All object types Obj (any type) Store (. . . , LocalX) Copy of Obj
" " CopyObject (. . . , LocalX) Copy of Obj
19.3.5.8.3 Named Objects
1. Read from Named object
•ObjectReference - If performing a DeRefOf return the target of the reference. Otherwise, return the
reference.
•All other object types - Return the object
Table 19.13: Reading from Named Objects
Current NAME Type Read operation on NAME Result of read
RefOf (Obj) Store (NAME, . . . ) RefOf (Obj)
" CopyObject (NAME, . . . )) RefOf (Obj)
" DeRefOf (NAME) Obj
Obj (All other types) Store (NAME, . . . ) Obj
" CopyObject (NAME, . . . ) Obj
2. Store to Named object
•All object types - Delete any existing object in NAME ﬁrst, then store a copy of the object. The Store
operator will perform an implicit conversion to the existing type in NAME. CopyObject does not perform
an implicit store.
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Table 19.14: Writing to Named Objects
Current NAME
tenWrite operation on NAME Result of write (in NAME)
Any (Any Type) Obj (Any type) Store (. . . , NAME) Copy of Obj (converted to
match existing type of NAME)
" " CopyObject (. . . , NAME) Copy of Obj (No conversion)
19.4 ASL Operators Summary
Table 19.15: ASL Operators Summary List
Operator Name Description
AccessAs Change Field Access
Acquire Acquire a mutex
Add Integer Add
Alias Deﬁne a name alias
And Integer Bitwise And
ArgX Method argument data objects
BankField Declare ﬁelds in a banked conﬁguration object
Break Continue following the innermost enclosing While
BreakPoint Used for debugging, stops execution in the debugger
Buffer Declare Buffer object
Case Expression for conditional execution
Concatenate Concatenate two strings, integers or buffers
ConcatenateResTemplate Concatenate two resource templates
CondRefOf Conditional reference to an object
Connection Declare Field Connection Attributes
Continue Continue innermost enclosing While loop
CopyObject Copy and existing object
CreateBitField Declare a bit ﬁeld object of a buffer object
CreateByteField Declare a byte ﬁeld object of a buffer object
CreateDWordField Declare a DWord ﬁeld object of a buffer object
CreateField Declare an arbitrary length bit ﬁeld of a buffer object
CreateQWordField Declare a QWord ﬁeld object of a buffer object
CreateWordField Declare a Word ﬁeld object of a buffer object
DataTableRegion Declare a Data Table Region
Debug Debugger output
Decrement Decrement an Integer
Default Default execution path in Switch()
DeﬁnitionBlock Declare a Deﬁnition Block
DerefOf Dereference an object reference
Device Declare a bus/device object
Divide Integer Divide
DMA DMA Resource Descriptor macro
DWordIO DWord IO Resource Descriptor macro
DWordMemory DWord Memory Resource Descriptor macro
DWordSpace DWord Space Resource Descriptor macro
EisaId EISA ID String to Integer conversion macro
Else Alternate conditional execution
ElseIf Conditional execution
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Table 19.15 – continued from previous page
EndDependentFn End Dependent Function
Event Resource Descriptor macro
ExtendedIO Declare an event synchronization object
ExtendedMemory Extended IO Resource Descriptor macro
ExtendedSpace Extended Space Resource Descriptor macro
External Declare external objects
Fatal Fatal error check
Field Declare ﬁelds of an operation region object
FindSetLeftBit Index of ﬁrst least signiﬁcant bit set
FindSetRightBit Index of ﬁrst most signiﬁcant bit set
FixedDMA Fixed DMA Resource Descriptor macro
FixedIO Fixed I/O Resource Descriptor macro
Fprintf Stores formatted string to a Named Object
FromBCD Convert from BCD to numeric
Function Declare control method
GpioInt GPIO Interrupt Connection Resource Descriptor macro
GpioIo GPIO I0 Connection Resource Descriptor macro
I2CSerialBusV2 I2C Serialbus Connection Resource Descriptor (Version 2) macro
If Conditional execution
Include Include another ASL ﬁle
Increment Increment a Integer
Index Indexed Reference to member object
IndexField Declare Index/Data Fields
Interrupt Interrupt Resource Descriptor macro
IO IO Resource Descriptor macro
IRQ Interrupt Resource Descriptor macro
IRQNoFlags Short Interrupt Resource Descriptor macro
LAnd Logical And
LEqual Logical Equal
LGreater Logical Greater
LGreaterEqual Logical Not less
LLess Logical Less
LLessEqual Logical Not greater
LNot Logical Not
LNotEqual Logical Not equal
Load Load differentiating deﬁnition block
LoadTable Load Table from RSDT/XSDT
LocalX Method local data objects
LOr Logical Or
Match Search for match in package array
Memory24 Memory Resource Descriptor macro
Memory32 Memory Resource Descriptor macro
Memory32Fixed Memory Resource Descriptor macro
Method Declare a control method
Mid Return a portion of buffer or string
Mod Integer Modulo
Multiply Integer Multiply
Mutex Declare a mutex synchronization object
Name Declare a Named object
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NAnd Integer Bitwise Nand
NoOp No operation
NOr Integer Bitwise Nor
Not Integer Bitwise Not
Notify Notify Object of event
ObjectType Type of object
Offset Set Field Offset within operation range
One Constant One Object (1)
Ones Constant Ones Object (-1)
OperationRegion Declare an operational region
Or Integer Bitwise Or
Package Declare a package object
PowerResource Declare a power resource object
Printf Stores formatted string to Debug Object
Processor Declare a processor package
QWordIO QWord IO Resource Descriptor macro
QWordMemory QWord Memory Resource Descriptor macro
QWordSpace Qword Space Resource Descriptor macro
RawDataBuffer Declare a RawDataBuffer
RefOf Create Reference to an object
Register Generic register Resource Descriptor macro
Release Release a synchronization object
Reset Reset a synchronization object
ResourceTemplate Resource to buffer conversion macro
Return Return from method execution
Revision Constant revision object
Scope Open named scope
ShiftLeft Integer shift value left
ShiftRight Integer shift value right
Signal Signal a synchronization object
SizeOf Get the size of a buffer, string, or package
Sleep Sleep n milliseconds (yields the processor)
SPISerialbusV2 SPI Serialbus Connection Resource Descritor (Version 2) macro
Stall Delay n microseconds (does not yield the processor)
StartDependentFn Start Dependent Function Resource Descriptor macro
StartDependentFnNoPri Start Dependent Function Resource Descriptor macro
Store Store object Integer
Subtract Subtract
Switch Select code to execute based on expression value
ThermalZone Declare a thermal zone package.
Timer Get 64-bit timer value
ToBCD Convert Integer to BCD
ToBuffer Convert data type to buffer
ToDecimalString Convert data type to decimal string
ToHexString Convert data type to hexadecimal string
ToInteger Convert data type to integer
ToPLD Converts a PLD Keyword List into a _PLD buffer
ToString Copy ASCII string from buffer
ToUUID Convert ASCII string to UUID
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Unicode String to Unicode conversion macro
UARTSerialBusV2 UART SerialBus Connection Resource Descriptor (version2) macro
VendorLong Vendor Resource Descriptor
VendorShort Vendor Resource Descriptor
Wait Wait on an Event
While Conditional loop
WordBusNumber Word Bus number Resource Descriptor macro
WordIO Word IO Resource Descriptor macro
WordSpace Word Space Resource Descriptor macro
Xor Integer Bitwise Xor
Zero Constant Zero object 0
19.5 ASL Operator Summary by Type

Table 19.16: ASL compiler controls
Table 19.17: ACPI table management
DeﬁnitionBlock Load deﬁnition block
Declare a Deﬁnition Block LoadTable
Load Load Table from RSDT/XSDT
Table 19.18: Miscellaneous named object creation
Function Declare a control method
ThermalZone Declare a thermal zone package
Table 19.19: Operation Regions and Fields
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Table 19.19 – continued from previous page
Offset Set Field offset within operation region
Table 19.20: Buffer Fields
Table 19.21: Synchronization
Event Declare an event synchronization object
Table 19.22: Object references
Table 19.23: Integer arithmetic
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Table 19.23 – continued from previous page
ShiftRight Integer shift value right I
Subtract Integer Subtract
Table 19.24: Logical operators
Table 19.25: Method execution control
Sleep Sleep in milliseconds (yields the processor)
Stall Delay in microseconds (does not yield the processor)
Table 19.26: Data type conversion and manipulation
Concatenate Concatenate two strings,integers or buffers
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Table 19.26 – continued from previous page
Store Store object
Table 19.27: Resource Descriptor macros
EndDependentFn End Dependent Function Resource Descriptor macro
ExtendedIO Extended I/O Resource Descriptor macro
ExtendedMemory Extended Memory Resource Descriptor macro
FixedDMA Fixed DMA resource Descriptor macro
GpioIO GPIO IO Connection Resource Descriptor macro
I2CSerialBusV2 I2C SerialBus Connection Resource Descriptor (Version 2) macro
SPISerialBusV2 SPI SerialBus Connection Resource Descriptor (Version 2) macro
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Table 19.27 – continued from previous page
StartDependentFn Start-
DependentFnNoPriStart Dependent Function Resource Descriptor macro
UARTSerialBusV2 UART SerialBus Connection Resource Descriptor (Version 2) macro
Table 19.28: Constants
Zero Constant Zero object (0)
Table 19.29: Control method objects
19.6 ASL Operator Reference
This section describes each of the ASL operators. The syntax for each operator is given, with a description of each
argument and an overall description of the operator behavior. Example ASL code is provided for the more complex
operators.
ASL operators can be categorized as follows:
• Named Object creation
• Method execution control (If, Else, While, etc.)
• Integer math
• Logical operators
• Resource Descriptor macros
• Object conversion
• Utility/Miscellaneous
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19.6.1 AccessAs (Change Field Unit Access)
Syntax :
AccessAs (AccessType, AccessAttribute)
AccessAs (AccessType, AccessAttribute (AccessLength))
Arguments
AccessType is an AccessTypeKeyword that speciﬁes the type of access desired ( ByteAcc ,WordAcc , etc.). AccessAt-
tribute is an optional argument of type AccessAttributeKeyword that speciﬁes additional protocols to be used, such as
AttribQuick ,AttribSendReceive , etc. AccessLength is a required argument for some of the Access Attributes.
TheAccessAs operator is used within a FieldList to specify the Access Type, Access Attributes, and Access Length
for the remaining FieldUnits within the list (or until another AccessAs operator is encountered.) It allows FieldUnits
to have different access types within a single Field deﬁnition.
Supported AccessTypes :

Syntax :
Arguments
• AnyAcc
• ByteAcc
• WordAcc
• DwordAcc
• QWordAcc
• BufferAcc
Supported simple AccessAttributes (with SMBus synonyms):
• AttribQuick ( SMBQuick )
• AttribSendReceive ( SMBSendReceive )
• AttribByte ( SMBByte )
• AttribWord ( SMBWord )
• AttribBlock ( SMBBlock )
• AttribProcessCall ( SMBProcessCall )
• AttribBlockProcessCall ( SMBBlockProcessCall )
Access Attributes that require an AccessLength argument:
• AttribBytes ( AccessLength )
• AttribRawBytes ( AccessLength )
• AttribRawProcessBytes ( AccessLength )
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19.6.2 Acquire (Acquire a Mutex)
Syntax :
Acquire (SyncObject, TimeoutValue) => Boolean
Arguments
SynchObject must be a mutex synchronization object. TimeoutValue is evaluated as an Integer.
Ownership of the Mutex is obtained. If the Mutex is already owned by a different invocation, the current execution
thread is suspended until the owner of the Mutex releases it or until at least TimeoutValue milliseconds have elapsed.
A Mutex can be acquired more than once by the same invocation.
Note: For Mutex objects referenced by a _DLM object, the host OS may also contend for ownership.
This operation returns True if a timeout occurred and the mutex ownership was not acquired. A TimeoutValue of
0xFFFF (or greater) indicates that there is no timeout and the operation will wait indeﬁnitely.
19.6.3 Add (Integer Add)
Syntax :
Add (Addend1, Addend2, Result) => Integer
Result = Addend1 + Addend2 => Integer
Result += Addend => Integer
Arguments
Addend1 andAddend2 are evaluated as Integers.
The operands are added and the result is optionally stored into Result. Overﬂow conditions are ignored and the result
of overﬂows simply loses the most signiﬁcant bits.
19.6.4 Alias (Declare Name Alias)
Syntax :
Alias (SourceObject, AliasObject)
Arguments
SourceObject is any named object. AliasObject is a NameString.
Creates a new object named AliasObject that refers to and acts exactly the same as SourceObject .
AliasObject is created as an alias of SourceObject in the namespace. The SourceObject name must already exist in the
namespace. If the alias is to a name within the same deﬁnition block, the SourceObject name must be logically ahead
of this deﬁnition in the block.
Example :
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The following example shows the use of an Alias term:
Alias (\SUS.SET.EVEN, SSE)
19.6.5 And (Integer Bitwise And)
Syntax :
And (Source1, Source2, Result) => Integer
Result = Source1 & Source2 => Integer
Result &= Source => Integer
Arguments
Source1 andSource2 are evaluated as Integers.
A bitwise AND is performed and the result is optionally stored into Result.
19.6.6 Argx (Method Argument Data Objects)
Syntax :
Arg0 | Arg1 | Arg2 | Arg3 | Arg4 | Arg5 | Arg6
Up to 7 argument-object references can be passed to a control method. On entry to a control method, only the argument
objects that are passed are usable.
19.6.7 BankField (Declare Bank/Data Field)
Syntax :
BankField (RegionName, BankName, BankValue, AccessType, LockRule,
UpdateRule) {FieldUnitList}
Arguments
RegionName is evaluated as a Namestring, and is the name of the host Operation Region.
BankName is evaluated as a Namestring, and is the name of the bank selection register.
BankValue is the bank selection ID (Integer) that is written to the BankName register before the FieldUnitList is
accessed.
TheAccessType, LockRule, UpdateRule , and FieldUnitList are the same format as the Field operator.
Accessing the contents of a banked ﬁeld data object will occur automatically through the proper bank setting, with
synchronization occurring on the operation region that contains the BankName data variable, and on the Global Lock
if speciﬁed by the LockRule.
This operator creates data ﬁeld objects. The contents of the created objects are obtained by a reference to a bank
selection register.
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This encoding is used to deﬁne named data ﬁeld objects whose data values are ﬁelds within a larger object selected by
a bank-selected register.
Example
The following is a block of ASL sample code using BankField:
• Creates a 4-bit bank-selected register in system I/O space.
• Creates overlapping ﬁelds in the same system I/O space that are selected via the bank register.
//
// Define a 256-byte operational region in SystemIO space
// and name it GIO0
OperationRegion (GIO0, SystemIO, 0x125, 0x100)
// Create some fields in GIO including a 4-bit bank select register
Field (GIO0, ByteAcc, NoLock, Preserve) {
GLB1, 1,
GLB2, 1,
Offset (1), // Move to offset for byte 1
BNK1, 4
}
// Create FET0 & FET1 in bank 0 at byte offset 0x30
BankField (GIO0, BNK1, 0, ByteAcc, NoLock, Preserve) {
Offset (0x30),
FET0, 1,
FET1, 1
}
// Create BLVL & BAC in bank 1 at the same offset
BankField (GIO0, BNK1, 1, ByteAcc, NoLock, Preserve) {
BLVL, 7,
BAC, 1
}
19.6.8 Break (Break from While)
Syntax :
Break
Break causes execution to continue immediately following the innermost enclosing While orSwitch scope, in the
current Method. If there is no enclosing While orSwitch within the current Method, a fatal error is generated.
Compatibility Note: In ACPI 1.0, the Break operator continued immediately following the innermost “code package.”
Starting in ACPI 2.0, the Break operator was changed to exit the innermost “While” or “Switch” package. This should
have no impact on existing code, since the ACPI 1.0 deﬁnition was, in practice, useless.
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19.6.9 BreakPoint (Execution Break Point)
Syntax :
BreakPoint
Used for debugging, the Breakpoint opcode stops the execution and enters the AML debugger. In the non-debug
version of the AML interpreter, BreakPoint is equivalent to Noop .
19.6.10 Buffer (Declare Buffer Object)
Syntax :
Buffer (BufferSize) {Initializer} => Buffer
Arguments
Declares a Buffer of optional size BufferSize and an optional initial value of Initializer. The Initializer is must be either
a ByteList or a String.
The optional BufferSize argument speciﬁes the size of the buffer and an optional initial value of the buffer is speciﬁed
via the Initializer . The initial value can be either an ASCII String or a list of byte values separated by commas. Strings
are automatically null terminated with a single zero byte.
The relationship between the BufferSize and the Initializer is summarized by the rules below.
In the typical case, the BufferSize is identical to the length of the Initializer:
Name (BUF0, Buffer(4) {0x01,0x02,0x03,0x04}) // Length = 4
If the BufferSize is not speciﬁed, the length of the Initializer is used as the buffer size:
Name (BUF1, Buffer() {0,1,2,3,4,5}) // Length = 6
Name (BUF2, Buffer() {"abcde"}) // Length = 6
If the BufferSize is larger than the length of the Initializer, the BufferSize is used as the ﬁnal buffer size. At runtime,
the AML interpreter will automatically pad zeros to the Initializer to match the BufferSize:
Name (BUF3, Buffer(1024) {4,5,6,7,8}) // Length = 1024
Name (BUF4, Buffer(1024) {"abcde"}) // Length = 1024
If the BufferSize is smaller than the length of the Initializer, the length of the Initializer is used as the buffer size:
Name (BUF5, Buffer(1) {5,4,3,2,1}) // Length = 5
If the Initializer is not speciﬁed, the AML interpreter creates a buffer containing all zeros, the length of which matches
the BufferSize:
Name (BUF6, Buffer(32} {}) // Length = 32
If neither the BufferSize nor the Initializer are speciﬁed, a buffer of zero length is created:
Name (BUF7, Buffer() {}) // Length = 0
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19.6.11 Case (Expression for Conditional Execution)
Syntax :
Case ( Value ) {TermList}
Arguments
Value speciﬁes an Integer, Buffer, String or Package object. TermList is a sequence of executable ASL expressions.
Execute code based upon the value of a Switch statement.
If the Case Value is an Integer, Buffer or String, then control passes to the statement that matches the value of the
enclosing Switch (Value). If the Case value is a Package, then control passes if any member of the package matches
the Switch (Value). The Switch CaseTermList can include any number of Case instances, but no two Case Values (or
members of a Value, if Value is a Package) within the same Switch statement can contain the same value.
Execution of the statement body begins at the start of the TermList and proceeds until the end of the TermList body or
until a Break or Continue operator transfers control out of the body.
19.6.12 Concatenate (Concatenate Data)
Syntax :
Concatenate ( Source1, Source2, Result ) => Buffer or String
Arguments

Syntax :
Arguments
Syntax :
Arguments
Source1 and Source2 must each evaluate to any valid ACPI object. For the basic data object types (Integer, String, or
Buffer), the value of the object is used in the concatenation. For all other object types (see table below), a string object
is created that contains the name (type) of the object. This string object is then concatenated according to the rules in
Concatenate Data Types .
The data type of Source1 dictates the required type of Source2 and the type of the result object. Source2 is implicitly
converted if necessary (and possible) to match the type of Source1 .
Source2 is concatenated to Source1 and the result data is optionally stored into Result.
Table 19.30: Concatenate Data Types
Source1 Data
TypeSource2 Data Type (Converted Type) Result Data Type
Integer Integer/String/Buffer →Integer Buffer
String Integer/String/Buffer /All other types →String String
Buffer Integer/String/Buffer /All other types →Buffer Buffer
All other types→
StringInteger/String/Buffer /All other types →String String
For the Source1 /Integer case, a String or Buffer that cannot be implicitly converted to an Integer will generate a fatal
error.
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Table 19.31: Concatenate Object Types
Data Object Type Name Resolved to Value
1 Integer Integer value of the object
2 String String value of the object
3 Buffer Buffer value of the object
Other Object Types Name Resolved to String
0 Uninitialized “[Uninitialized Object]”
4 Package “[Package]”
5 Field Unit “[Field]”
6 Device “[Device]”
7 Event “[Event]”
8 Control Method “[Control Method]”
9 Mutex “[Mutex]”
10 Operation Region “[Operation Region]”
11 Power Resource “[Power Resource]”
12 Processor “[Processor]”
13 Thermal Zone “[Thermal Zone]”
14 Buffer Field “[Buffer Field]”
15 Reserved
16 Debug Object “[Debug Object]”
Examples :
Device (DEVX) {}
Name (PKGX, Package () {1,2,3,"Battery1"})
Method (MTHX, 2)
{
Concatenate ("My Object: ", DEVX, Debug) // MyObject: Device
Printf ("PKGX %o contains %o elements\n", PKGX, SizeOf (PKGX))
Printf ("Arg0: %o\n", Arg0)
}
19.6.13 ConcatenateResTemplate (Concatenate Resource Templates)
Syntax :
ConcatenateResTemplate (Source1, Source2, Result) => Buffer
Arguments
Source1 andSource2 are evaluated as Resource Template buffers.
The resource descriptors from Source2 are appended to the resource descriptors from Source1. Then a new end tag
and checksum are appended and the result is stored in Result, if speciﬁed. If either Source1 or Source2 is exactly 1
byte in length, a run-time error occurs. An empty buffer is treated as a resource template with only an end tag.
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19.6.14 CondRefOf (Create Object Reference Conditionally)
Syntax :
CondRefOf (Source, Result) => Boolean
Arguments
Attempts to create a reference to the Source object. The Source of this operation can be any object type (for example,
data package, device object, and so on), and the result data is optionally stored into Result.
On success, the Destination object is set to refer to Source and the execution result of this operation is the value True.
On failure, Destination is unchanged and the execution result of this operation is the value False. This can be used
to reference items in the namespace that may appear dynamically (for example, from a dynamically loaded deﬁnition
block).
CondRefOf is equivalent to RefOf except that if the Source object does not exist, it is fatal for RefOf but not for
CondRefOf.
19.6.15 Connection (Declare Field Connection Attributes)
Syntax :
Arguments
ConnectionResourceObj is a GPIO or Serial Bus Connection Descriptor depending on the Operation Region type, or
a named object containing the Descriptor.
See Section 6.4.3.8.2 and Field (Declare Field Objects) for more information.
Examples :
// GenericSerialBus device at command
˓→value offset zero
Name (I2C, ResourceTemplate(){
I2CSerialBusV2(0x5a,,100000,, "\_SB.I2C",,,,,RawDataBuffer(){1,6})
})
{
Connection(I2C) // Specify connection resource
AccessAs(BufferAcc, AttribWord) // Use the GenericSerialBus
// Read/Write Word protocol
{
Connection(I2CSerialBusV2(0x5b,,100000,, "\_SB.I2C",,,,,RawDataBuffer(){3,9}))
AccessAs(BufferAcc, AttribBytes (16))
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}
Name(BUFF, Buffer(34){}) // Create GenericSerialBus data buffer
˓→as BUFF
The Connection macro declares the connection attributes for subsequent ﬁelds deﬁned within the Field declaration.
19.6.16 Continue (Continue Innermost Enclosing While)
Syntax :
Continue
Continue causes execution to continue at the start of the innermost enclosing While scope, in the currently executing
Control Method, at the point where the condition is evaluated. If there is no enclosing While within the current
Method, a fatal error is generated.
19.6.17 CopyObject (Copy and Store Object)
Syntax :
CopyObject (Source, Destination) => DataRefObject
Arguments
Converts the contents of the Source to a DataRefObject using the conversion rules in Section 19.3.5 and then copies
the results without conversion to the object referred to by Destination.
If Destination is already an initialized object of type DataRefObject, the original contents of Destination are discarded
and replaced with Source. Otherwise, a fatal error is generated.
Note: Compatibility Note: The CopyObject operator was ﬁrst introduced new in ACPI 2.0.
19.6.18 CreateBitField (Create 1-Bit Buffer Field)
Syntax :
CreateBitField (SourceBuffer, BitIndex, BitFieldName)
Arguments
SourceBuffer is evaluated as a buffer. BitIndex is evaluated as an integer. BitFieldName is a NameString.
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A new buffer ﬁeld object named BitFieldName is created for the bit of SourceBuffer at the bit index of BitIndex. The
bit-deﬁned ﬁeld within SourceBuffer must exist.BitFieldName is created for the bit of SourceBuffer at the bit index of
BitIndex. The bit-deﬁned ﬁeld within SourceBuffer must exist.
19.6.19 CreateByteField (Create 8-Bit Buffer Field)
Syntax :
CreateByteField ( SourceBuffer, ByteIndex, ByteFieldName )
Arguments
SourceBuffer is evaluated as a buffer. ByteIndex is evaluated as an integer. ByteFieldName is a NameString.
A new buffer ﬁeld object named ByteFieldName is created for the byte of SourceBuffer at the byte index of ByteIndex.
The byte-deﬁned ﬁeld within SourceBuffer must exist.
19.6.20 CreateDWordField (Create 32-Bit Buffer Field)
Syntax :
CreateDWordField ( SourceBuffer, ByteIndex, DWordFieldName )
Arguments
SourceBuffer is evaluated as a buffer. ByteIndex is evaluated as an integer. DWordFieldName is a NameString.
A new buffer ﬁeld object named DWordFieldName is created for the DWord of SourceBuffer at the byte index of
ByteIndex. The DWord-deﬁned ﬁeld within SourceBuffer must exist.
19.6.21 CreateField (Create Arbitrary Length Buffer Field)
Syntax :
CreateField ( SourceBuffer, BitIndex, NumBits, FieldName )
Arguments
SourceBuffer is evaluated as a buffer. BitIndex and NumBits are evaluated as integers. FieldName is a NameString.
A new buffer ﬁeld object named FieldName is created for the bits of SourceBuffer at BitIndex for NumBits. The
entire bit range of the deﬁned ﬁeld within SourceBuffer must exist. If NumBits evaluates to zero, a fatal exception is
generated.
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19.6.22 CreateQWordField (Create 64-Bit Buffer Field)
Syntax :
CreateQWordField ( SourceBuffer, ByteIndex, QWordFieldName )
Arguments
SourceBuffer is evaluated as a buffer. ByteIndex is evaluated as an integer. QWordFieldName is a NameString.
A new buffer ﬁeld object named QWordFieldName is created for the QWord of SourceBuffer at the byte index of
ByteIndex. The QWord-deﬁned ﬁeld within SourceBuffer must exist.
19.6.23 CreateWordField (Create 16-Bit Buffer Field)
Syntax :
CreateWordField ( SourceBuffer, ByteIndex, WordFieldName )
Arguments
SourceBuffer is evaluated as a buffer. ByteIndex is evaluated as an integer. WordFieldName is a NameString.

Syntax :
Arguments
Syntax :
Arguments
A new bufferﬁeld object named WordFieldName is created for the word of SourceBuffer at the byte index of ByteIn-
dex. The word-deﬁned ﬁeld within SourceBuffer must exist.
19.6.24 CSI2Bus (CSI-2 Serial Bus Connection Resource Descriptor Macro)
Syntax
CSI2Bus (SlaveMode, PhyType, LocalPort, ResourceSource, ResourceSourceIndex, ResourceUsage, Descriptor-
Name, VendorData )
Arguments
SlaveMode is an optional argument and can be either ControllerInitiated or DeviceInitiated. ControllerInitiated is the
default. The bit ﬁeld name _SLV is automatically created to refer to this portion of the resource descriptor.
PhyType is an integer ranging from 0 to 3 specifying the value for the PHY Type. This value describes the PHY
type used to connect this device to its receiver. _PHY is automatically created to refer to this portion of the resource
LocalPort is an optional integer argument, that identiﬁes the index of the local Port for this connection. The ﬁrst Port
instance is 0.
ResourceSource is a string which uniquely identiﬁes the remote CSI-2 receiver referred to by this descriptor. Re-
sourceSource can be a fully-qualiﬁed name, a relative name or a name segment that utilizes the namespace search
rules.
ResourceSourceIndex is an integer specifying the Port index of the Device speciﬁed by ResourceSource. Port index
values begin at 0.
ResourceUsage is an optional argument and is assumed to be ResourceConsumer for this revision.
DescriptorName is an optional argument that speciﬁes a name for an integer constant that will be created in the current
scope that contains the offset of this resource descriptor within the current resource template buffer. The predeﬁned
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descriptor ﬁeld names may be appended to this name to access individual ﬁelds within the descriptor via the Buffer
Field operators.
VendorData is an optional argument that speciﬁes an object to be decoded by the OS driver. It is a RawDataBuffer.
The bit ﬁeld name _VEN is automatically created to refer to this portion of the resource descriptor.
The CSI2Bus macro evaluates to a buffer that contains a CSI-2 resource descriptor. The macro is designed to be used
inside of a ResourceTemplate (see Section 19.3.4).
19.6.25 DataTableRegion (Create Data Table Operation Region)
Syntax :
DataTableRegion ( RegionName, SignatureString, OemIDString, OemTableIDString )
Arguments
Creates a new region named RegionName. SignatureString, OemIDString and OemTableIDString are evaluated as
strings.
A Data Table Region is a special Operation Region whose RegionSpace is SystemMemory. Any table referenced by a
Data Table Region must be in memory marked by AddressRangeReserved or AddressRangeNVS.
The memory referred to by the Data Table Region is the memory that is occupied by the table referenced in XSDT that
is identiﬁed by SignatureString, OemIDString and OemTableIDString. Any Field object can reference RegionName
The base address of a Data Table region is the address of the ﬁrst byte of the header of the table identiﬁed by Signa-
tureString, OemIDString and OemTableIDString. The length of the region is the length of the table.
19.6.26 Debug (Debugger Output)
Syntax :
Debug
The debug data object is a virtual data object. Writes to this object provide debugging information. On at least
debug versions of the interpreter, any writes into this object are appropriately displayed on the system’s native kernel
debugger. All writes to the debug object are otherwise benign. If the system is in use without a kernel debugger, then
writes to the debug object are ignored. The following table relates the ASL term types that can be written to the Debug
object to the format of the information on the kernel debugger display.
Table 19.32: Debug Object Display Formats
ASL Term Type Display Format
Numeric data object All digits displayed in hexadecimal format.
String data object String is displayed.
Object reference Information about the object is displayed (for example, object type and object name),
but the object is not evaluated.
The Debug object is a write-only object; attempting to read from the debug object is not supported.
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19.6.27 Decrement (Integer Decrement)
Syntax :
Decrement (Minuend) => Integer
Minuend -- => Integer
Arguments
Minuend is evaluated as an Integer.
This operation decrements the Minuend by one and the result is stored back to Minuend. Equivalent to Subtract
(Minuend, 1, Minuend). Underﬂow conditions are ignored and the result is Ones.
19.6.28 Default (Default Execution Path in Switch)
Syntax :
Default {TermList}
Arguments
TermList is a sequence of executable ASL expressions.
Within the body of a Switch (Select Code To Execute Based On Expression) statement, the statements speciﬁed by
TermList will be executed if no Case (Expression for Conditional Execution) statement value matches the Switch
statement value. If Default is omitted and no Case match is found, none of the statements in the Switch body are
executed. There can be at most one Default statement in the immediate scope of the parent Switch statement. The
Default statement can appear anywhere in the body of the Switch statement.
19.6.29 DeﬁnitionBlock (Declare Deﬁnition Block)
Syntax :
DefinitionBlock ( AMLFileName, TableSignature, ComplianceRevision, OEMID, TableID,
˓→OEMRevision) {TermList}
Arguments
AMLFileName is a string that speciﬁes the desired name of the translated output AML ﬁle. If the AMLFileName is a
NULL (zero length) string, the ASL compiler will automatically create the ﬁlename (typically generated from the input
ﬁlename/pathname).TableSignature is a string that contains the 4-character ACPI signature. ComplianceRevision is
an 8-bit value. OEMID is a 6-character string, TableId is an 8-character string, and OEMRevision is a 32-bit value.
If multiple DeﬁnitionBlocks are deﬁned in the same ASL ﬁle, the ﬁrst DeﬁnitionBlock deﬁnes the output AMLFile-
Name as per the rule above.
The DeﬁnitionBlock term speciﬁes the unit of data and/or AML code that the OS will load as part of the Differentiated
Deﬁnition Block or as part of an additional Deﬁnition Block.
This unit of data and/or AML code describes either the base system or some large extension (such as a docking station).
The entire DeﬁnitionBlock will be loaded and compiled by the OS as a single unit.
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System software loads a deﬁnition block by referencing the objects in the TermList package in order. The object list
is encoded as TermList, so that rather than describing a static object list, it is possible to describe a dynamic object list
according to the system settings. See Section 5.4.2.
Note: For compatibility with ACPI versions before ACPI 2.0, the bit width of Integer objects is dependent on the
ComplianceRevision of the DSDT. If the ComplianceRevision is less than 2, all integers are restricted to 32 bits.
Otherwise, full 64-bit integers are used. The version of the DSDT sets the global integer width for all integers,
including integers in SSDTs.
19.6.30 DerefOf (Dereference an Object Reference)
Syntax :
DerefOf (Source) => Object
Arguments
Returns the object referred by the Source object reference.
If the Source evaluates to an object reference, the actual contents of the object referred to are returned. If the Source
evaluates to a string, the string is evaluated as an ASL name (relative to the current scope) and the contents of that
object are returned. If the object speciﬁed by Source does not exist then a fatal error is generated. If the object speciﬁed
is a reference generated by the Index() operator and refers to an uninitialized package element, then a fatal error is
Note: Compatibility Note: The use of a String with DerefOf was ﬁrst introduced in ACPI 2.0*.
19.6.31 Device (Declare Device Package)
Syntax :
Device (DeviceName) {TermList}
Arguments
Creates a Device object of name DeviceName, which represents a processor, a bus or a device, or any other similar
hardware. Device opens a name scope.
A Device Package is one of the basic ways the Differentiated Deﬁnition Block describes the hardware devices in
the system to the operating software. Each Device Package is deﬁned somewhere in the hierarchical namespace
corresponding to that device’s location in the system. Within the namespace of the device are other names that provide
information and control of the device, along with any sub-devices that in turn describe sub-devices, and so on.
For any device, the platform runtime ﬁrmware provides only information that is added to the device in a non-hardware
standard manner. This type of value-added function is expressible in the ACPI Deﬁnition Block such that operating

Syntax :
Arguments
software can use the function.
The platform runtime ﬁrmware supplies Device Objects only for devices that are obtaining some system-added func-
tion outside the device’s normal capabilities and for any Device Object required to ﬁll in the tree for such a device. For
example, if the system includes a PCI device (integrated or otherwise) with no additional functions such as power man-
agement, the platform runtime ﬁrmware would not report such a device; however, if the system included an integrated
ISA device below the integrated PCI device (device is an IS bridge), then the system would include a Device Package
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for the ISA device with the minimum feature being added being the ISA device’s ID and conﬁguration information
and the parent PCI device, because it is required to get the ISA Device Package placement in the namespace correct.
The device object list is encoded as TermList , so that rather than describing a static device object list, it is possible to
describe a dynamic device object list according to the system settings. see Section 5.4.2.
Example
The following block of ASL sample code shows a nested use of Device objects to describe an IDE controller connected
to the root PCI bus:
Device (IDE0) { // primary controller
Name (_ADR, 0) // put PCI Address (device/function) here
// define region for IDE mode register
OperationRegion (PCIC, PCI_Config, 0x50, 0x10)
Field (PCIC, AnyAcc, NoLock, Preserve) {
...
}
Device (PRIM) { // Primary adapter
Name (_ADR, 0) // Primary adapter = 0
...
Method (_STM, 2) {
...
}
Method (_GTM) {
...
}
Device (MSTR) { // master channel
Name (_PR0, Package () {0, PIDE})
Name (_GTF) {
...
}
}
Device (SLAV) {
...
}
}
}
}
19.6.32 Divide (Integer Divide)
Syntax :
Divide (Dividend, Divisor, Remainder, Result) => Integer
Result = Dividend / Divisor=> Integer
Result /= Divisor => Integer
Arguments
Dividend andDivisor are evaluated as Integers.
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Dividend is divided by Divisor, then the resulting remainder is optionally stored into Remainder and the resulting
quotient is optionally stored into Result. Divide-by-zero exceptions are fatal.
The function return value is the Result (quotient).
19.6.33 DMA (DMA Resource Descriptor Macro)
Syntax :
DMA ( DmaType , IsBusMaster , DmaTransferSize, DescriptorName )
{ DmaChannelList } => Buffer
Arguments
DmaType speciﬁes the type of DMA cycle: ISA compatible (Compatibility), EISA Type A (TypeA), EISA Type B
(TypeB) or EISA Type F (TypeF). The 2-bit ﬁeld DescriptorName._TYP is automatically created to refer to this portion
of the resource descriptor, where ‘0’ is Compatibility, ‘1’ is TypeA, ‘2’ is TypeB and ‘3’ is TypeF.
IsBusMaster speciﬁes whether this device can generate DMA bus master cycles (BusMaster) or not (NotBusMaster).
If nothing is speciﬁed, then BusMaster is assumed. The 1-bit ﬁeld DescriptorName._BM is automatically created to
refer to this portion of the resource descriptor, where ‘0’ is NotBusMaster and ‘1’ is BusMaster.
DmaTransferSize speciﬁes the size of DMA cycles the device is capable of generating: 8-bit (Transfer8), 16-bit (Trans-
fer16) or both 8 and 16-bit (Transfer8_16). The 2-bit ﬁeld DescriptorName._SIZ is automatically created to refer to
this portion of the resource descriptor, where ‘0’ is Transfer8, ‘1’ is Transfer8_16 and ‘2’ is Transfer16.
DmaChannelList is a comma-delimited list of integers in the range 0 through 7 that specify the DMA channels used
by the device. There may be no duplicates in the list.
The DMA macro evaluates to a buffer that contains a DMA resource descriptor. The format of this resource descriptor
can be found in DMA Descriptor . This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer
Conversion Macro) .
19.6.34 DWordIO (DWord IO Resource Descriptor Macro)
Syntax :
DWordIO ( ResourceUsage, IsMinFixed, IsMaxFixed, Decode, ISARanges,
AddressGranularity, AddressMinimum, AddressMaximum, AddressTranslation,
RangeLength, ResourceSourceIndex, ResourceSource, DescriptorName,
TranslationType, TranslationDensity)
Arguments
ResourceUsage speciﬁes whether the I/O range is consumed by this device (ResourceConsumer) or passed on to child
devices (ResourceProducer). If nothing is speciﬁed, then ResourceConsumer is assumed.
IsMinFixed speciﬁes whether the minimum address of this I/O range is ﬁxed (MinFixed) or can be changed (MinNot-
Fixed). If nothing is speciﬁed, then MinNotFixed is assumed. The 1-bit ﬁeld DescriptorName._MIF is automatically
created to refer to this portion of the resource descriptor, where ‘1’ is MinFixed and ‘0’ is MinNotFixed.
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IsMaxFixed speciﬁes whether the maximum address of this I/O range is ﬁxed (MaxFixed) or can be changed (MaxNot-
Fixed). If nothing is speciﬁed, then MaxNotFixed is assumed. The 1-bit ﬁeld DescriptorName ._MAF is automatically
created to refer to this portion of the resource descriptor, where ‘1’ is MaxFixed and ‘0’ is MaxNotFixed.
Decode speciﬁes whether or not the device decodes the I/O range using positive (PosDecode) or subtractive (SubDe-
code) decode. If nothing is speciﬁed, then PosDecode is assumed. The 1-bit ﬁeld DescriptorName._DEC is automati-
cally created to refer to this portion of the resource descriptor, where ‘1’ is SubDecode and ‘0’ is PosDecode.
ISARanges speciﬁes whether the I/O ranges speciﬁes are limited to valid ISA I/O ranges (ISAOnly), valid non-ISA
I/O ranges (NonISAOnly) or encompass the whole range without limitation (EntireRange). The 2-bit ﬁeld Descriptor-
Name._RNG is automatically created to refer to this portion of the resource descriptor, where ‘1’ is NonISAOnly, ‘2’
is ISAOnly and ‘0’ is EntireRange.
AddressGranularity evaluates to a 32-bit integer that speciﬁes the power-of-two boundary (- 1) on which the I/O range
must be aligned. The 32-bit ﬁeld DescriptorName._GRA is automatically created to refer to this portion of the resource
AddressMinimum evaluates to a 32-bit integer that speciﬁes the lowest possible base address of the I/O range. The
value must have ‘0’ in all bits where the corresponding bit in AddressGranularity is ‘1’. For bridge devices which
translate addresses, this is the address on the secondary bus. The 32-bit ﬁeld DescriptorName._MIN is automatically
created to refer to this portion of the resource descriptor.
AddressMaximum evaluates to a 32-bit integer that speciﬁes the highest possible base address of the I/O range. The
translate addresses, this is the address on the secondary bus. The 32-bit ﬁeld DescriptorName._MAX is automatically
AddressTranslation evaluates to a 32-bit integer that speciﬁes the offset to be added to a secondary bus I/O address
which results in the corresponding primary bus I/O address. For all non-bridge devices or bridges which do not
perform translation, this must be ‘0’. The 32-bit ﬁeld DescriptorName._TRA is automatically created to refer to this
portion of the resource descriptor.
RangeLength evaluates to a 32-bit integer that speciﬁes the total number of bytes decoded in the I/O range. The 32-bit
ﬁeld DescriptorName._LEN is automatically created to refer to this portion of the resource descriptor.
ResourceSourceIndex is an optional argument which evaluates to an 8-bit integer that speciﬁes the resource descriptor
within the object speciﬁed by ResourceSource. If this argument is speciﬁed, the ResourceSource argument must also
be speciﬁed.
ResourceSource is an optional argument which evaluates to a string containing the path of a device which produces the
pool of resources from which this I/O range is allocated. If this argument is speciﬁed, but the ResourceSourceIndex
argument is not speciﬁed, a value of zero is assumed.

TranslationType is an optional argument that speciﬁes whether the resource type on the secondary side of the bus is
different (TypeTranslation) from that on the primary side of the bus or the same (TypeStatic). If TypeTranslation is
speciﬁed, then the primary side of the bus is Memory. If TypeStatic is speciﬁed, then the primary side of the bus is
I/O. If nothing is speciﬁed, then TypeStatic is assumed. The 1-bit ﬁeld DescriptorName._TTP is automatically created
to refer to this portion of the resource descriptor, where ‘1’ is TypeTranslation and ‘0’ is TypeStatic. see Table 6.49
TranslationDensity is an optional argument that speciﬁes whether or not the translation from the primary to secondary
bus is sparse (SparseTranslation) or dense (DenseTranslation). It is only used when TranslationType is TypeTransla-
tion. If nothing is speciﬁed, then DenseTranslation is assumed. The 1-bit ﬁeld DescriptorName._TRS is automatically
created to refer to this portion of the resource descriptor, where ‘1’ is SparseTranslation and ‘0’ is DenseTranslation .
see Table 6.50 for more information.
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The DWordIO macro evaluates to a buffer that contains a 32-bit I/O range resource descriptor. The format of the
32-bit I/O range resource descriptor can be found in Table 6.46. This macro is designed to be used inside of a
ResourceTemplate (Resource To Buffer Conversion Macro) .
19.6.35 DWordMemory (DWord Memory Resource Descriptor Macro)
Syntax :
DWordMemory (ResourceUsage, Decode, IsMinFixed, IsMaxFixed, Cacheable,
ReadAndWrite, AddressGranularity, AddressMinimum, AddressMaximum,
AddressTranslation, RangeLength, ResourceSourceIndex, ResourceSource,
DescriptorName, MemoryRangeType, TranslationType)
Arguments
ResourceUsage speciﬁes whether the Memory range is consumed by this device (ResourceConsumer) or passed on to
child devices (ResourceProducer). If nothing is speciﬁed, then ResourceConsumer is assumed.
Decode speciﬁes whether or not the device decodes the Memory range using positive (PosDecode) or subtractive
(SubDecode) decode. If nothing is speciﬁed, then PosDecode is assumed. The 1-bit ﬁeld DescriptorName._DEC is
automatically created to refer to this portion of the resource descriptor, where ‘1’ is SubDecode and ‘0’ is PosDecode.
IsMinFixed speciﬁes whether the minimum address of this Memory range is ﬁxed (MinFixed) or can be changed
(MinNotFixed). If nothing is speciﬁed, then MinNotFixed is assumed. The 1-bit ﬁeld DescriptorName._MIF is
automatically created to refer to this portion of the resource descriptor, where ‘1’ is MinFixed and ‘0’ is MinNotFixed.
IsMaxFixed speciﬁes whether the maximum address of this Memory range is ﬁxed (MaxFixed) or can be changed
(MaxNotFixed). If nothing is speciﬁed, then MaxNotFixed is assumed. The 1-bit ﬁeld DescriptorName._MAF is
automatically created to refer to this portion of the resource descriptor, where ‘1’ is MaxFixed and ‘0’ is MaxNotFixed.
Cacheable speciﬁes whether or not the memory region is cacheable (Cacheable), cacheable and write-combining
(WriteCombining), cacheable and prefetchable (Prefetchable) or uncacheable (NonCacheable). If nothing is speciﬁed,
then NonCacheable is assumed. The 2-bit ﬁeld DescriptorName._MEM is automatically created to refer to this portion
of the resource descriptor, where ‘1’ is Cacheable, ‘2’ is WriteCombining, ‘3’ is Prefetchable and ‘0’ is NonCacheable.
ReadAndWrite speciﬁes whether or not the memory region is read-only (ReadOnly) or read/write (ReadWrite). If
nothing is speciﬁed, then ReadWrite is assumed. The 1-bit ﬁeld DescriptorName._RW is automatically created to
refer to this portion of the resource descriptor, where ‘1’ is ReadWrite and ‘0’ is ReadOnly.
AddressGranularity evaluates to a 32-bit integer that speciﬁes the power-of-two boundary (- 1) on which the Memory
range must be aligned. The 32-bit ﬁeld DescriptorName._GRA is automatically created to refer to this portion of the
resource descriptor.
AddressMinimum evaluates to a 32-bit integer that speciﬁes the lowest possible base address of the Memory range.
The value must have ‘0’ in all bits where the corresponding bit in AddressGranularity is ‘1’. For bridge devices which
AddressMaximum evaluates to a 32-bit integer that speciﬁes the highest possible base address of the Memory range.
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RangeLength evaluates to a 32-bit integer that speciﬁes the total number of bytes decoded in the Memory range. The
32-bit ﬁeld DescriptorName._LEN is automatically created to refer to this portion of the resource descriptor.
ResourceSource is an optional argument which evaluates to a string containing the path of a device which produces
the pool of resources from which this Memory range is allocated. If this argument is speciﬁed, but the ResourceSour-
ceIndex argument is not speciﬁed, a zero value is assumed.
MemoryRangeType is an optional argument that speciﬁes the memory usage. The memory can be marked as normal
(AddressRangeMemory), used as ACPI NVS space (AddressRangeNVS), used as ACPI reclaimable space (Address-
RangeACPI) or as system reserved (AddressRangeReserved). If nothing is speciﬁed, then AddressRangeMemory is
assumed. The 2-bit ﬁeld DescriptorName._MTP is automatically created in order to refer to this portion of the re-
source descriptor, where ‘0’ is AddressRangeMemory, ‘1’ is AddressRangeReserved, ‘2’ is AddressRangeACPI and
‘3’ is AddressRangeNVS.
speciﬁed, then the primary side of the bus is I/O. If TypeStatic is speciﬁed, then the primary side of the bus is Memory.
If nothing is speciﬁed, then TypeStatic is assumed. The 1-bit ﬁeld DescriptorName._TTP is automatically created to
refer to this portion of the resource descriptor, where ‘1’ is TypeTranslation and-‘0’-is-TypeStatic. see Table 6.50 for
The DWordMemory macro evaluates to a buffer which contains a 32-bit memory resource descriptor. The format of
the 32-bit memory resource descriptor can be found in DWORD Address Space Descriptor Deﬁnition . This macro is
designed to be used inside of a ResourceTemplate (Resource To Buffer Conversion Macro) .
19.6.36 DWordSpace (DWord Space Resource Descriptor Macro)
Syntax :
DWordSpace (ResourceType, ResourceUsage, Decode, IsMinFixed, IsMaxFixed,
TypeSpecificFlags, AddressGranularity, AddressMinimum, AddressMaximum,
DescriptorName)
Arguments
ResourceType evaluates to an 8-bit integer that speciﬁes the type of this resource. Acceptable values are 0xC0 through
0xFF.

Syntax :
Arguments
0xFF.
19.6. ASL Operator Reference 903Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
TypeSpeciﬁcFlags evaluates to an 8-bit integer. The ﬂags are speciﬁc to the ResourceType.
The DWordSpace macro evaluates to a buffer which contains a 32-bit Address Space resource descriptor. The format
of this resource descriptor can be found in DWORD Address Space Descriptor . This macro is designed to be used
inside of a ResourceTemplate (Resource To Buffer Conversion Macro) .
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19.6.37 EISAID (EISA ID String To Integer Conversion Macro)
Syntax :
EISAID ( EisaIdString ) => DWordConst
Arguments
The EisaIdString must be a String object of the form “UUUNNNN”, where “U” is an uppercase letter and “N” is a
hexadecimal digit. No asterisks or other characters are allowed in the string.
Converts EisaIdString, a 7-character text string argument, into its corresponding 4-byte numeric EISA ID encoding. It
can be used when declaring IDs for devices that have EISA IDs.
Example
EISAID ("PNP0C09") // This is a valid invocation of the macro.
19.6.38 Else (Alternate Execution)
Syntax :
Else {TermList}
Arguments
TermList is a sequence of executable ASL statements.
If Predicate evaluates to 0 in an If statement, then control is transferred to the Else portion, which can consist of zero
or more ElseIf statements followed by zero or one Else statements. If the Predicate of any ElseIf statement evaluates
to non-zero, the statements in its term list are executed and then control is transferred past the end of the ﬁnal Else
term. If no Predicate evaluates to non-zero, then the statements in the Else term list are executed.
Example
The following example checks Local0 to be zero or non-zero. On non-zero, CNT is incremented; otherwise, CNT is
decremented:
If (LGreater (Local0, 5)
{
Increment (CNT)
}
Else If (Local0) {
Add (CNT, 5, CNT)
}
Else
{
Decrement (CNT)
}
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19.6.39 ElseIf (Alternate/Conditional Execution)
Syntax :
ElseIf ( Predicate ) {TermList}
Arguments
Predicate is evaluated as an Integer.
If the Predicate of any ElseIf statement evaluates to non-zero, the statements in its term list are executed and then
control is transferred past the end of the ﬁnal Else. If no Predicate evaluates to non-zero, then the statements in the
Else term list are executed.
Note: Compatibility Note: The ElseIf operator was ﬁrst introduced in ACPI 2.0, but is backward compatible with
the ACPI 1.0 speciﬁcation. An ACPI 2.0 and later ASL compiler must synthesize ElseIf from the If and Else opcodes
available in 1.0. For example:
If (predicate1)
{
...statements1...
}
ElseIf (predicate2)
{
...statements2...
}
Else
{
...statements3...
}
is translated to the following:
{
}
Else
{
If (predicate2)
{
}
Else
{
}
}
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19.6.40 EndDependentFn (End Dependent Function Resource Descriptor Macro)
Syntax :
EndDependentFn () => Buffer
The EndDependentFn macro generates an end-of-dependent-function resource descriptor buffer inside of a Re-
sourceTemplate (Resource To Buffer Conversion Macro) . This descriptor must be matched with a StartDependentFn
(Start Dependent Function Resource Descriptor Macro) or aStartDependentFnNoPri (Start Dependent Function Re-
source Descriptor Macro) .
19.6.41 Event (Declare Event Synchronization Object)
Syntax :
Event ( EventName )
Arguments
Creates an event synchronization object named EventName.
For more information about the uses of an event synchronization object, see the ASL deﬁnitions for the Wait, Signal,
and Reset function operators.
19.6.42 ExtendedIO (Extended IO Resource Descriptor Macro)
Syntax :
ExtendedIO ( ResourceUsage, IsMinFixed , IsMaxFixed , Decode ,
ISARanges , AddressGranularity, AddressMinimum, AddressMaximum ,
AddressTranslation , RangeLength , TypeSpecificAttributes,
DescriptorName, TranslationType, TranslationDensity)
Arguments
Fixed). If nothing is speciﬁed, then MaxNotFixed is assumed. The 1-bit ﬁeld DescriptorName._MAF is automatically

19.6. ASL Operator Reference 907Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
AddressGranularity evaluates to a 64-bit integer that speciﬁes the power-of-two boundary (- 1) on which the I/O range
must be aligned. The 64-bit ﬁeld DescriptorName._GRA is automatically created to refer to this portion of the resource
AddressMinimum evaluates to a 64-bit integer that speciﬁes the lowest possible base address of the I/O range. The
translate addresses, this is the address on the secondary bus. The 64-bit ﬁeld DescriptorName._MIN is automatically
AddressMaximum evaluates to a 64-bit integer that speciﬁes the highest possible base address of the I/O range. The
translate addresses, this is the address on the secondary bus. The 64-bit ﬁeld DescriptorName._MAX is automatically
AddressTranslation evaluates to a 64-bit integer that speciﬁes the offset to be added to a secondary bus I/O address
perform translation, this must be ‘0’. The 64-bit ﬁeld DescriptorName._TRA is automatically created to refer to this
RangeLength evaluates to a 64-bit integer that speciﬁes the total number of bytes decoded in the I/O range. The 64-bit
Type Speciﬁc Attributes is an optional argument that speciﬁes attributes speciﬁc to this resource type.
Field operatorsDescription
The ExtendedIO macro evaluates to a buffer that contains a 64-bit I/O resource descriptor, which describes a range of
I/O addresses. The format of this resource descriptor can be found in Section 6.4.3.5.4. This macro is designed to be
used inside of a ResourceTemplate (Resource To Buffer Conversion Macro) .
speciﬁed, then the primary side of the bus is Memory. If TypeStatic is speciﬁed, then the primary side of the bus is I/O.
If nothing is speciﬁed, then TypeStatic is assumed. The 1-bit ﬁeld DescriptorName. _TTP is automatically created to
refer to this portion of the resource descriptor, where ‘1’ is TypeTranslation and -‘0’-is-TypeStatic. See Section 5.6.8
created to refer to this portion of the resource descriptor, where ‘1’ is SparseTranslation and ‘0’ is DenseTranslation.
See Section 5.6.8 for more information.
19.6.43 ExtendedMemory (Extended Memory Resource Descriptor Macro)
Syntax :
ExtendedMemory ( ResourceUsage, Decode, IsMinFixed, IsMaxFixed,
Cacheable, ReadAndWrite, AddressGranularity, AddressMinimum,
AddressMaximum, AddressTranslation, RangeLength, TypeSpecificAttributes,
Arguments
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(MinNotFixed). If nothing is speciﬁed, then MinNotFixed is assumed. The 1-bit ﬁeld DescriptorName . _MIF is
(MaxNotFixed). If nothing is speciﬁed, then MaxNotFixed is assumed. The 1-bit ﬁeld DescriptorName. _MAF is
AddressGranularity evaluates to a 64-bit integer that speciﬁes the power-of-two boundary (- 1) on which the Memory
range must be aligned. The 64-bit ﬁeld DescriptorName._GRA is automatically created to refer to this portion of the
AddressMinimum evaluates to a 64-bit integer that speciﬁes the lowest possible base address of the Memory range.
translate addresses, this is the address on the secondary bus. The 64-bit ﬁeld DescriptorName ._MIN is automatically
AddressMaximum evaluates to a 64-bit integer that speciﬁes the highest possible base address of the Memory range.
translate addresses, this is the address on the secondary bus. The 64-bit ﬁeld DescriptorName ._MAX is automatically
perform translation, this must be ‘0’. The 64-bit ﬁeld DescriptorName. _TRA is automatically created to refer to this
RangeLength evaluates to a 64-bit integer that speciﬁes the total number of bytes decoded in the Memory range. The
64-bit ﬁeld DescriptorName. _LEN is automatically created to refer to this portion of the resource descriptor.
assumed. The 2-bit ﬁeld DescriptorName. _MTP is automatically created in order to refer to this portion of the re-

19.6. ASL Operator Reference 909Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
refer to this portion of the resource descriptor, where ‘1’ is TypeTranslation and-‘0’-is-TypeStatic. See Section 5.6.8
The ExtendedMemory macro evaluates to a buffer that contains a 64-bit memory resource descriptor, which describes
a range of memory addresses. The format of this resource descriptor can be found in Section 6.4.3.5.4. This macro is
19.6.44 ExtendedSpace (Extended Address Space Resource Descriptor Macro)
Syntax :
ExtendedSpace (ResourceType, ResourceUsage, Decode, IsMinFixed,
IsMaxFixed, TypeSpecificFlags, AddressGranularity, AddressMinimum,
Arguments
0xFF.
(SubDecode) decode. If nothing is speciﬁed, then PosDecode is assumed. The 1-bit ﬁeld DescriptorName. _DEC is
(MinNotFixed). If nothing is speciﬁed, then MinNotFixed is assumed. The 1-bit ﬁeld DescriptorName. _MIF is
range must be aligned. The 64-bit ﬁeld DescriptorName. _GRA is automatically created to refer to this portion of the
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The ExtendedSpace macro evaluates to a buffer that contains a 64-bit Address Space resource descriptor, which de-
scribes a range of addresses. The format of the 64-bit AddressSpace descriptor can be found in Section 6.4.3.5.4. This
macro is designed to be used inside of a ResourceTemplate (Resource To Buffer Conversion Macro) .
19.6.45 External (Declare External Objects)
Syntax :
External ( ObjectName, ObjectType, ReturnType, ParameterTypes )
Arguments
ObjectName is a NameString.
ObjectType is an optional ObjectTypeKeyword (e.g. IntObj, PkgObj, etc.). If not speciﬁed, “UnknownObj” type is
assumed.
ReturnType is optional. If the speciﬁed ObjectType is MethodObj, then this speciﬁes the type or types of object
returned by the method. If the method does not return an object, then nothing is speciﬁed or UnknownObj is speciﬁed.
To specify a single return type, simply use the ObjectTypeKeyword. To specify multiple possible return types, enclose
the comma-separated ObjectTypeKeywords with braces. For example: {IntObj, BuffObj}.
ParameterTypes is optional. If the speciﬁed ObjectType is MethodObj, this speciﬁes both the number and type of the
method parameters. It is a comma-separated, variable-length list of the expected object type or types for each of the
method parameters, enclosed in braces. For each parameter, the parameter type consists of either an ObjectTypeKey-
word or a comma-separated sub-list of ObjectTypeKeywords enclosed in braces. There can be no more than seven
parameters in total.Description
The External directive informs the ASL compiler that the object is declared external to this table so that no errors will
be generated for an undeclared object. The ASL compiler will create the external object at the speciﬁed place in the
namespace (if a full path of the object is speciﬁed), or the object will be created at the current scope of the External
term.
For external control methods, the ASL compiler can emit an External AML opcode that contains the name of the
method and the number of required arguments. This information may be used by AML disassemblers to properly
disassemble the AML to the correct ASL code.
External is especially useful for use in secondary SSDTs, when the required scopes and objects are declared in the
main DSDT.
Example
This example shows the use of External in conjunction with Scope within an SSDT:
DefinitionBlock ("ssdt.aml", "SSDT", 2, "X", "Y", 0x00000001)
{
External (\_SB.PCI0, DeviceObj)
19.6. ASL Operator Reference 911Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Scope (\_SB.PCI0)
{
}
}
19.6.46 Fatal (Fatal Error Check)
Syntax :
Fatal ( Type, Code, Arg )
Arguments
This operation is used to inform the OS that there has been an OEM-deﬁned fatal error.
In response, the OS must log the fatal event and perform a controlled OS shutdown in a timely fashion.
19.6.47 Field (Declare Field Objects)
Syntax :
Field ( RegionName, AccessType, LockRule, UpdateRule ) {FieldUnitList}
Arguments
RegionName is evaluated as a Namestring that refers to the host operation region.
AccessType is optional and deﬁnes the default access width of the ﬁeld deﬁnition and is any one of the following:
AnyAcc, ByteAcc, WordAcc, DWordAcc, or QWordAcc. In general, accesses within the parent object are performed
naturally aligned. If desired, AccessType set to a value other than AnyAcc can be used to force minimum access
width. Notice that the parent object must be able to accommodate the AccessType width. For example, an access type
of WordAcc cannot read the last byte of an odd-length operation region. The exceptions to natural alignment are the
access types used for a non-linear SMBus device. These will be discussed in detail below. Not all access types are
meaningful for every type of operational region. If not speciﬁed, the default is AnyAcc.
LockRule is optional and indicates whether the Global Lock is to be used when accessing this ﬁeld and is one of the

Arguments
following: Lock or NoLock. If LockRule is set to Lock, accesses to modify the component data objects will acquire
and release the Global Lock. If both types of locking occur, the Global Lock is acquired after the parent object Mutex.
On Hardware-reduced ACPI platforms, Lock is not supported. If not speciﬁed, the default is NoLock.
UpdateRule is optional and speciﬁeas how the unmodiﬁed bits of a ﬁeld are treated, and can be any one of the fol-
lowing: Preserve, WriteAsOnes, or WriteAsZeros. For example, if a ﬁeld deﬁnes a component data object of 4 bits
in the middle of a WordAcc region, when those 4 bits are modiﬁed the UpdateRule speciﬁes how the other 12 bits are
treated. If not speciﬁed, the default is Preserve.
FieldUnitList is a variable-length list of individual ﬁeld unit deﬁnitions, separated by commas. Each entry in the ﬁeld
unit list is one of the following:
Table 19.33: Field Unit List Entries
FieldUnitName (BitLength)
Offset ( ByteOffset )
AccessAs ( AccessType, AccessAttribute )
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Table 19.33 – continued from previous page
Connection ( ConnectionResourceObj )
FieldUnitName is the ACPI name for the ﬁeld unit (1 to 4 characters), and BitLength is the length of the ﬁeld unit in
bits. Offset is used to specify the byte offset of the next deﬁned ﬁeld unit. This can be used instead of deﬁning the
bit lengths that need to be skipped. AccessAs is used to deﬁne the access type and attributes for the remaining ﬁeld
units within the list. Connection is used to identify the connection resource of the ﬁeld access. This is necessary for
GenericSerialBus and GeneralPurposeIO operation region address spaces only.
Declares a series of named data objects whose data values are ﬁelds within a larger object. The ﬁelds are parts of the
object named by RegionName, but their names appear in the same scope as the Field term.
For example, the ﬁeld operator allows a larger operation region that represents a hardware register to be broken down
into individual bit ﬁelds that can then be accessed by the bit ﬁeld names. Extracting and combining the component
ﬁeld from its parent is done automatically when the ﬁeld is accessed.
When reading from a FieldUnit, returned values are normalized (shifted and masked to the proper length.) The data
type of an individual FieldUnit can be either a Buffer or an Integer, depending on the bit length of the FieldUnit. If the
FieldUnit is smaller than or equal to the size of an Integer (in bits), it will be treated as an Integer. If the FieldUnit is
larger than the size of an Integer, it will be treated as a Buffer. The size of an Integer is indicated by the DSDT header’s
Revision ﬁeld. A revision less than 2 indicates that the size of an Integer is 32 bits. A value greater than or equal to
2 signiﬁes that the size of an Integer is 64 bits. For more information about data types and FieldUnit type conversion
rules, see Section 19.3.5.7 .
Accessing the contents of a ﬁeld data object provides access to the corresponding ﬁeld within the parent object. If the
parent object supports Mutex synchronization, accesses to modify the component data objects will acquire and release
ownership of the parent object around the modiﬁcation.
The following table relates region types declared with an OperationRegion term to the different access types supported
for each region.
Table 19.34: OperationRegion Address Spaces and Access Types
Address Space Permitted Access Type(s) Description
SystemMemory ByteAcc, WordAcc, DWor-
dAcc, QWordAcc, or AnyAccAll access allowed
SystemIO ByteAcc, WordAcc, DWor-
PCI_Conﬁg ByteAcc, WordAcc, DWor-
EmbeddedControl ByteAcc Byte access only
SMBus BufferAcc Reads and writes to this operation region involve the use
of a region speciﬁc data buffer. (See below.)
SystemCMOS ByteAcc Byte access only
PciBarTarget ByteAcc, WordAcc, DWor-
IPMI BufferAcc Reads and writes to this operation region involve the use
GeneralPurposeIO ByteAcc Byte access only
GenericSerialBus BufferAcc Reads and writes to this operation region involve the use
of a region-speciﬁc data buffer. (See below.)
PCC ByteAcc Reads and writes to this operation region are performed
in units of bytes.
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The named FieldUnit data objects are provided in the FieldList as a series of names and bit widths. Bits assigned no
name (or NULL) are skipped. The ASL compiler supports the Offset (ByteOffset) macro within a FieldList to skip to
the bit position of the supplied byte offset, and the AccessAs macro to change access within the ﬁeld list.
GenericSerialBus, SMBus and IPMI regions are inherently non-linear, where each offset within the respective address
space represents a variable sized (0 to 32 bytes) ﬁeld. Given this uniqueness, these operation regions include restric-
tions on their ﬁeld deﬁnitions and require the use of a region-speciﬁc data buffer when initiating transactions. For
more information on the SMBus data buffer format see Section 13.2.5. For more information on the IPMI data buffer
format, see Section 5.5.2.4.5. For more information on the GenericSerialBus data buffer format, see Section 5.5.2.4.7.
For restrictions on the use of Fields with GeneralPurposeIO OpRegions, see Section 5.5.2.4.6.
Example :
OperationRegion (MIOC, PCI_Config, Zero, 0xFF)
Field (MIOC, AnyAcc, NoLock, Preserve)
{
Offset (0x58),
HXGB, 32,
HXGT, 32,
GAPE, 8,
MR0A, 4,
MR0B, 4
}
19.6.48 FindSetLeftBit (Find First Set Left Bit)
Syntax :
FindSetLeftBit ( Source, Result ) => Integer
Arguments
Source is evaluated as an Integer.
The one-based bit location of the ﬁrst MSb (most signiﬁcant set bit) is optionally stored into Result. The result of 0
means no bit was set, 1 means the left-most bit set is the ﬁrst bit, 2 means the left-most bit set is the second bit, and so
on.
19.6.49 FindSetRightBit (Find First Set Right Bit)
Syntax :
FindSetRightBit ( Source, Result ) => Integer
Arguments
The one-based bit location of the most LSb (least signiﬁcant set bit) is optionally stored in Result. The result of 0
means no bit was set, 32 means the ﬁrst bit set is the thirty-second bit, 31 means the ﬁrst bit set is the thirty-ﬁrst bit,
and so on.
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19.6.50 FixedDMA (DMA Resource Descriptor Macro)
Syntax :
FixedDMA ( DmaRequestLine, Channel, DmaTransferWidth, DescriptorName ) => Buffer
Arguments
DmaRequestLine is a system-relative number uniquely identifying the request line statically assigned to the device..
The bit ﬁeld name _DMA is automatically created to refer to this portion of the resource descriptor.
Channel is a controller-relative number uniquely identifying the channel statically assigned to this DMARequestLine.
Channels can be shared by reusing Channel numbers across descriptors. The bit ﬁeld name _TYP is automatically
DmaTransferWidth is an optional argument specifying the width of data transfer for which the device is conﬁgured.
Valid values are Width8Bit, Width16Bit, Width32Bit,Width64Bit, Width 128Bit or Width256Bit. If not speciﬁed,
Width32Bit is assumed. The bit ﬁeld name _SIZ is automatically created to refer to this portion of the resource
The FixedDMA macro evaluates to a buffer that contains a Fixed DMA Descriptor . This macro is designed to be used
19.6.51 FixedIO (Fixed IO Resource Descriptor Macro)
Syntax :
FixedIO ( AddressBase, RangeLength, DescriptorName ) => Buffer
Arguments
AddressBase evaluates to a 16-bit integer. It describes the starting address of the ﬁxed I/O range. The ﬁeld Descrip-
torName. _BAS is automatically created to refer to this portion of the resource descriptor.
RangeLength evaluates to an 8-bit integer. It describes the length of the ﬁxed I/O range. The ﬁeld DescriptorName.
_LEN is automatically created to refer to this portion of the resource descriptor.
DescriptorName evaluates to a name string which refers to the entire resource descriptor.

Syntax :
Arguments
The FixedIO macro evaluates to a buffer that contains a ﬁxed I/O resource descriptor. The format of this resource
descriptor can be found in Section 6.4.2.6. This macro is designed to be used inside of a ResourceTemplate (Resource
To Buffer Conversion Macro) .
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19.6.52 For (Conditional Loop)
Syntax :
For ( Initialize, Predicate, Update ) {TermList}
Arguments
Initialize . This optional expression is evaluated once before the loop is entered. If not speciﬁed, no initialization takes
place.
Predicate . The list of terms within the TermList are executed until the predicate evaluates to zero (FALSE). If this
argument is not speciﬁed, the For macro is equivalent to While(1) .
Update . This optional expression is evaluated once per execution of the loop, after all other terms within the TermList
have been executed.
Foris a macro that creates a loop by converting the input arguments to the equivalent ASL While loop.
Note: Creation of a named object more than once in a given scope is not allowed. As such, unconditionally creating
named objects within a For loop must be avoided. A fatal error will be generated on the second iteration of the loop,
during the attempt to create the same named object a second time.
Example
The following example shows the use of the Formacro to create a loop, followed by the equivalent While loop that is
actually emitted by the ASL compiler:
for (local0 = 0, local0 < 8, local0++)
{
}
Local0 = 0
While (Local0 < 8)
{
Local0++
}
19.6.53 Fprintf (Create and Store formatted string)
Syntax :
Fprintf ( Destination, FormatString, FormatArgs ) => String
Arguments
Fprintf is a macro that converts the evaluated FormatString into a series of string Concatenate operations, storing the
result in Destination .
FormatString is a string literal which may contain one or more uses of the format speciﬁer, %o, to indicate locations
in the string where an object may be inserted. %o is the only format speciﬁer supported since the resulting object is a
string and type conversion is handled automatically by Concatenate.
FormatArgs is a comma separated list of Named Objects, Locals, or Args that can be evaluated to a string. Each
argument is added to the FormatString using the Concatenate operation at the location speciﬁed by %o in order of
appearance.
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result in Destination
Example
The following ASL example uses Fprintf to write a formatted string of Arg0 and Arg1 to the Named Object STR1:
Fprintf (STR1, "%o: %o Successful", Arg1, Arg0)
This Fprintf macro expression evaluates to the following ASL operation.
Store (Concatenate (Concatenate (Concatenate (Concatenate ("", Arg1), ": "), Arg0), "
˓→Successful"), STR1)
19.6.54 FromBCD (Convert BCD To Integer)
Syntax :
FromBCD ( BCDValue, Result ) => Integer
Arguments
BCDValue is evaluated as an Integer in Binary Coded Decimal format.
The FromBCD operation converts BCDValue to a numeric format, and optionally stores the numeric value into Result.
19.6.55 Function (Declare Control Method)
Syntax :
Function ( FunctionName, ReturnType, ParameterTypes ) {TermList}
Arguments
ReturnType is optional and speciﬁes the type(s) of the object(s) returned by the method. If the method does not
return an object, then nothing is speciﬁed or UnknownObj is speciﬁed. To specify a single return type, simply use
the ObjectTypeKeyword (e.g. IntObj, PkgObj, etc.). To specify multiple possible return types, enclose the comma-
separated ObjectTypeKeywords with braces. For example:
{IntObj, BuffObj}.
ParameterTypes is optional and speciﬁes both the number and type of the method parameters. It is a comma-separated,
variable-length list of the expected object type or types for each of the method parameters, enclosed in braces. For
each parameter, the parameter type consists of either an ObjectTypeKeyword or a comma-separated sub-list of Object-
TypeKeywords enclosed in braces. There can be no more than seven parameters in total.
Function declares a named package containing a series of terms that collectively represent a control method. A control
method is a procedure that can be invoked to perform computation. Function opens a name scope.
System software executes a control method by executing the terms in the package in order. For more information on
method execution, see Section 5.5.2.
The current namespace location used during name creation is adjusted to be the current location on the namespace
tree. Any names created within this scope are “below” the name of this package. The current namespace location
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is assigned to the method package, and all namespace references that occur during control method execution for this
package are relative to that location.
Functions are equivalent to a Method that speciﬁes NotSerialized. As such, a function should not create any named
objects, since a second thread that might re-enter the function will cause a fatal error if an attempt is made to create
the same named object twice.
Note: Compatibility Note: New for ACPI 3.0
Example
The following block of ASL sample code shows the use of Function for deﬁning a control method:
Function (EXAM, IntObj, {StrObj, {IntObj, StrObj}})
{
Name (Temp,"")
Store (Arg0, Temp) // could have used Arg1
Return (SizeOf (Concatenate (Arg1, Temp)))
}
This declaration is equivalent to:
Method (EXAM, 2, NotSerialized, 0, IntObj, {StrObj, {IntObj, StrObj}})
{
...
}
19.6.56 GpioInt (GPIO Interrupt Connection Resource Descriptor Macro)
Syntax :
GpioInt (EdgeLevel, ActiveLevel, Shared, PinConfig, DebounceTimeout,
ResourceSource, ResourceSourceIndex, ResourceUsage, DescriptorName,
VendorData) {PinList}
Arguments
EdgeLevel can be either Edge or Level. The bit ﬁeld name _MOD is automatically created to refer to this portion of
the resource descriptor.
ActiveLevel can be one of ActiveHigh, ActiveLow or ActiveBoth. ActiveBoth can be speciﬁed only if EdgeLevel is
Edge. The bit ﬁeld name _POL is automatically created to refer to this portion of the resource descriptor.
Shared is an optional argument and can be one of Shared, Exclusive, SharedAndWake or ExclusiveAndWake. If not
speciﬁed, Exclusive is assumed. The “Wake” designation indicates that the interrupt is capable of waking the system
from a low-power idle state or a system sleep state. The bit ﬁeld name _SHR is automatically created to refer to this
PinConﬁg can be one of PullDefault, PullUp, PullDown, PullNone or a vendor-supplied value in the range 128-255.
The bit ﬁeld name _PPI is automatically created to refer to this portion of the resource descriptor.
DebounceTimeout is an optional argument specifying the debounce wait time, in hundredths of milliseconds. The bit
ﬁeld name _DBT is automatically created to refer to this portion of the resource descriptor.
ResourceSource is a string which uniquely identiﬁes the GPIO controller referred to by this descriptor. ResourceSource
can be a fully-qualiﬁed name, a relative name or a name segment that utilizes the namespace search rules.
ResourceSourceIndex is an optional argument and is assumed to be 0 for this revision.
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VendorData is an optional argument that speciﬁes a RawDataBuffer containing vendor-deﬁned byte data to be decoded
by the OS driver. The bit ﬁeld name _VEN is automatically created to refer to this portion of the resource descriptor.
PinList is a list of (zero-based) pin numbers on the ResourceSource that are described by this descriptor. For interrupt
pin descriptors, only one pin is allowed. The bit ﬁeld name _PIN is automatically created to refer to this portion of the
TheGpioInt macro evaluates to a buffer that contains a GPIO Interrupt Connection resource descriptor. The format of
this resource descriptor can be found in Section 6.4.3.8.1. This macro is designed to be used inside of a ResourceTem-
plate (Resource To Buffer Conversion Macro) .
19.6.57 GpioIo (GPIO Connection IO Resource Descriptor Macro)
Syntax :

Syntax :
GpioIo (Shared, PinConfig, DebounceTimeout, DriveStrength,
IORestriction, ResourceSource, ResourceSourceIndex, ResourceUsage,
DescriptorName, VendorData) {PinList}
Arguments
Shared is an optional argument and can be either Shared or Exclusive. If not speciﬁed, Exclusive is assumed. The bit
ﬁeld name _SHR is automatically created to refer to this portion of the resource descriptor.
DebounceTimeout is an optional argument specifying the hardware debounce wait time, in hundredths of milliseconds.
The bit ﬁeld name _DBT is automatically created to refer to this portion of the resource descriptor.
DriveStrength is an optional argument specifying the output drive capability of the pin, in hundredths of milliamperes.
The bit ﬁeld name _DRS is automatically created to refer to this portion of the resource descriptor.
IORestriction is an optional argument and can be IoRestrictionInputOnly, IoRestrictionOutputOnly, IoRestriction-
None, or IORestrictionNoneAndPreserve. IORestrictions limit the mode in which the pin can be accessed (Input or
Output). They also ensure that the pin conﬁguration is preserved during periods when the driver is unloaded or the
resource has been disconnected by the driver. If not speciﬁed, IoRestrictionNone is assumed. The bit ﬁeld name _IOR
is automatically created to refer to this portion of the resource descriptor.
ResourceSourceIndex is an optional argument and is always 0 for this revision.
ResourceUsage is an optional argument and is always ResourceConsumer for this revision.
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PinList is a list of pin numbers on the ResourceSource that are described by this descriptor. The bit ﬁeld name _PIN
The GpioIo macro evaluates to a buffer that contains a GPIO IO Connection resource descriptor. The format of this
resource descriptor can be found in GPIO Connection Descriptor . This macro is designed to be used inside of a
ResourceTemplate (Resource To Buffer Conversion Macro)
19.6.58 I2CSerialBusV2 (I2C Serial Bus Connection Resource Descriptor (Version
2) Macro)
Syntax :
I2CSerialBusV2 (SlaveAddress, SlaveMode, ConnectionSpeed,
AddressingMode, ResourceSource, ResourceSourceIndex, ResourceUsage,
DescriptorName, Shared, VendorData)
Arguments
SlaveAddress is the I2C bus address for this connection. The bit ﬁeld name _ADR is automatically created to refer to
this portion of the resource descriptor.
ConnectionSpeed is the maximum connection speed supported by this connection, in hertz. The bit ﬁeld name _SPE
AddressingMode is an optional argument and can be either AddressingMode7Bit or AddressingMode10Bit. Address-
ingMode7Bit is the default. The bit ﬁeld name _MOD is automatically created to refer to this portion of the resource
ResourceSource is a string which uniquely identiﬁes the I2C bus controller referred to by this descriptor. Resource-
Source can be a fully-qualiﬁed name, a relative name or a name segment that utilizes the namespace search rules.
Shared is an optional argument and can be either Shared orExclusive . If not speciﬁed, Exclusive is assumed. The bit
ﬁeld name _SHR is automatically created to refer to this portion of the resource descriptor. This was added in ACPI
6.1, and changed I2CSerialBus to I2CSerialBusV2.
The I2CSerialBusV2 macro evaluates to a buffer that contains an I2C Serial Bus Connection Resource Descriptor .
This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer Conversion Macro) .
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19.6.59 If (Conditional Execution)
Syntax :
If ( Predicate ) {TermList}
Arguments
If the Predicate is non-zero, the term list of the If term is executed.
Example
The following examples all check for bit 3 in Local0 being set, and clear it if set:
// example 1
If (And (Local0, 4))
{
XOr (Local0, 4, Local0)
}
// example 2
Store (4, Local2)
If (And (Local0, Local2))
{
XOr (Local0, Local2, Local0)
}
19.6.60 Include (Include Additional ASL File)
Syntax :
Include (FilePathName)
Arguments
FilePathname is a StringData data type that contains the full OS ﬁle system path.
Include another ﬁle that contains ASL terms to be inserted in the current ﬁle of ASL terms. The ﬁle must contain
elements that are grammatically correct in the current scope.
Example :
Include ("dataobj.asl")
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19.6.61 Increment (Integer Increment)
Syntax :
Increment (Addend) => Integer
Destination = Source [Index] => ObjectReference
Addend ++ => Integer
Arguments
Addend is evaluated as an Integer.
Add one to the Addend and place the result back in Addend. Equivalent to Add (Addend, 1, Addend). Overﬂow
conditions are ignored and the result of an overﬂow is zero.
19.6.62 Index (Indexed Reference To Member Object)
Syntax :
Index (Source, Index, Destination) => ObjectReference
Destination =Source [Index ] => ObjectReference
Arguments
Source is evaluated to a buffer, string, or package data type. Index is evaluated to an integer. The reference to the nth
object (where n = Index) within Source is optionally stored as a reference into Destination.
When Source evaluates to a Buffer, Index returns a reference to a Buffer Field containing the nth byte in the buffer.
When Source evaluates to a String, Index returns a reference to a Buffer Field containing the nth character in the string.
When Source evaluates to a Package, Index returns a reference to the nth object in the package.
19.6.62.1 Index with Packages
The following example ASL code shows a way to use the Index term to store into a local variable the sixth element of
the ﬁrst package of a set of nested packages:
Name (IO0D, Package () {
0x01, 0x03F8, 0x03F8, 0x01, 0x08, 0x01, 0x25, 0xFF, 0xFE, 0x00, 0x00
},
0x01, 0x02F8, 0x02F8, 0x01, 0x08, 0x01, 0x25, 0xFF, 0xBE, 0x00, 0x00
},
0x01, 0x03E8, 0x03E8, 0x01, 0x08, 0x01, 0x25, 0xFF, 0xFA, 0x00, 0x00
},
x01, 0x02E8, 0x02E8, 0x01, 0x08, 0x01, 0x25, 0xFF, 0xBA, 0x00, 0x00
},
0x01, 0x0100, 0x03F8, 0x08, 0x08, 0x02, 0x25, 0x20, 0x7F, 0x00, 0x00
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}
})
// Get the 6th element of the first package
Store (DeRefOf (Index (DeRefOf (Index (IO0D, 0)), 5)), Local0)
Note: DeRefOf is necessary in the ﬁrst operand of the Store operator in order to get the actual object, rather than

},
},
},
},
}
})
just a reference to the object. If DeRefOf were not used, then Local0 would contain an object reference to the sixth
element in the ﬁrst package rather than the number 1.*
19.6.62.2 Index with Buffers
The following example ASL code shows a way to store into the third byte of a buffer:
Name (BUFF, Buffer () {0x01, 0x02, 0x03, 0x04, 0x05})
// Store 0x55 into the third byte of the buffer
Store (0x55, Index (BUFF, 2))
The Index operator returns a reference to an 8-bit Buffer Field (similar to that created using CreateByteField).
If Source is evaluated to a buffer data type, the ObjectReference refers to the byte at Index within Source. If Source is
evaluated to a buffer data type, a Store operation will only change the byte at Index within Source.
The following example ASL code shows the results of a series of Store operations:
Name (SRCB, Buffer () {0x10, 0x20, 0x30, 0x40})
Name (BUFF, Buffer () {0x1, 0x2, 0x3, 0x4})
The following will store 0x78 into the 3rd byte of the destination buffer:
Store (0x12345678, Index (BUFF, 2))
The following will store 0x10 into the 2nd byte of the destination buffer:
Store (SRCB, Index (BUFF, 1))
The following will store 0x41 (an ‘A’) into the 4th byte of the destination buffer:
Store ("ABCDEFGH", Index (BUFF, 3))
Note: Compatibility Note: First introduced in ACPI 2.0. In ACPI 1.0, the behavior of storing data larger than 8-bits
into a buffer using Index was undeﬁned.
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19.6.62.3 Index with Strings
The following example ASL code shows a way to store into the 3rd character in a string:
Name (STR, "ABCDEFGHIJKL")
// Store 'H' (0x48) into the third character to the string
Store ("H", Index (STR, 2))
Note: Compatibility Note: First introduced in ACPI 2.0.
19.6.63 IndexField (Declare Index/Data Fields)
Syntax :
IndexField (IndexName, DataName, AccessType, LockRule, UpdateRule) {FieldUnitList}
Arguments
IndexName is evaluated as a Namestring and refers to a Field Unit object.
DataName is evaluated as a Namestring and refers to a Field Unit object.
AccessType , LockRule, UpdateRule, and FieldList are the same format as the Field term.
Creates a series of named data objects whose data values are ﬁelds within a larger object accessed by an index/data-
style reference to IndexName and DataName.
This encoding is used to deﬁne named data objects whose data values are ﬁelds within an index/data register pair. This
provides a simple way to declare register variables that occur behind a typical index and data register pair.
Accessing the contents of an indexed ﬁeld data object will automatically occur through the DataName object by using
an IndexName object aligned on an AccessType boundary, with synchronization occurring on the operation region that
contains the index data variable, and on the Global Lock if speciﬁed by LockRule.
The value written to the IndexName register is deﬁned to be a byte offset that is aligned on an AccessType boundary.
For example, if AccessType is DWordAcc, valid index values are 0, 4, 8, etc. This value is always a byte offset and is
independent of the width or access type of the DataName register.
Example
The following example contains a block of ASL sample code using IndexField, that:
(a) Creates an index/data register in system I/O space made up of 8-bit registers.
(b) Creates a FET0 ﬁeld within the indexed range.
Method (EX1) {
OperationRegion (GIO0, 1, 0x125, 0x100)
// Create a field named Preserve structured as a sequence
// of index and data bytes
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Field (GIO0, ByteAcc, NoLock, WriteAsZeros) {
IDX0, 8,
DAT0, 8,
.
.
.
}
// Create an IndexField within IDX0 & DAT0 which has
// FETs in the first two bits of indexed offset 0,
// and another 2 FETs in the high bit on indexed
// 2F and the low bit of indexed offset 30
IndexField (IDX0, DAT0, ByteAcc, NoLock, Preserve) {
FET0, 1,
FET1, 1,
Offset (0x2f), // skip to byte offset 2f
, 7, // skip another 7 bits
FET3, 1,
FET4, 1
}
// Clear FET3 (index 2F, bit 7)
Store (Zero, FET3)
} // End EX1
19.6.64 Interrupt (Interrupt Resource Descriptor Macro)
Syntax :
Interrupt ( ResourceUsage, EdgeLevel, ActiveLevel, Shared,
ResourceSourceIndex, ResourceSource, DescriptorName ) { InterruptList
} => Buffer
Arguments
ResourceUsage describes whether the device consumes the speciﬁed interrupt (ResourceConsumer) or produces it for
use by a child device (ResourceProducer). If nothing is speciﬁed, then ResourceConsumer is assumed.
EdgeLevel describes whether the interrupt is edge triggered (Edge) or level triggered (Level). The ﬁeld Descriptor-
Name ._HE is automatically created to refer to this portion of the resource descriptor, where ‘1’ is Edge and ‘0’ is
Level.
ActiveLevel describes whether the interrupt is active-high (ActiveHigh) or active-low (ActiveLow). The ﬁeld Descrip-
torName ._LL is automatically created to refer to this portion of the resource descriptor, where ‘1’ is ActiveLow and
‘0’ is ActiveHigh.
Shared describes whether the interrupt can be shared with other devices (Shared) or not (Exclusive), and whether it is
capable of waking the system from a low-power idle or system sleep state (SharedAndWake or ExclusiveAndWake).
The ﬁeld DescriptorName ._SHR is automatically created to refer to this portion of the resource descriptor, where ‘1’
is Shared and ‘0’ is Exclusive. If nothing is speciﬁed, then Exclusive is assumed.
ResourceSourceIndex evaluates to an integer between 0x00 and 0xFF and describes the resource source index. If it
is not speciﬁed, then it is not generated. If this argument is speciﬁed, the ResourceSource argument must also be
speciﬁed.
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ResourceSource evaluates to a string which uniquely identiﬁes the resource source. If it is not speciﬁed, it is not
generated. If this argument is speciﬁed, but the ResourceSourceIndex argument is not speciﬁed, a zero value is
assumed.
InterruptList is a comma-delimited list on integers, at least one value is required. Each integer represents a 32-
bit interrupt number. At least one interrupt must be deﬁned, and there may be no duplicates in the list. The ﬁeld
“DescriptorName. _INT” is automatically created to refer to this portion of the resource descriptor.
The Interrupt macro evaluates to a buffer that contains an interrupt resource descriptor. The format of this descriptor
can be found in Section 6.4.3.6. This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer
The interrupt macro uses the ResourceUsage ﬁeld to distinguish two types of devices, a ResourceProducer and a
ResourceConsumer .
AResourceProducer represents a device that can forward interrupts from one or more devices to processors under the
OSPM. Usage of ResourceProducer within interrupt macros is undeﬁned and will be ignored by the OSPM. Declaring
interrupt macros as ResourceProducer is not recommended.
AResourceConsumer is a device that consumes the interrupts declared in the InterruptList. Most devices fall under
this category and use this method to declare the interrupts that can be generated by that device. The interrupt descriptors
declared as ResourceConsumer, are generated by either the main interrupt controller described in the MADT or by
a device that acts as an “interrupt producer”. The ResourceSource ﬁeld is used to make this distinction. If this is
omitted, the interrupt numbers in the InterruptList identify global system interrupts, GSIVs, and these interrupts target
the main interrupt controller described in the MADT (see Section 5.2.12). The ResourceSource ﬁeld may also provide
the name of a device that is an “interrupt producer”. In this case the interrupt numbers in the InterruptList refer to the
private interrupt number space of the indicated an interrupt set of the “interrupt producer” device.
TheResourceSourceIndex parameter is reserved. If a platform speciﬁes “Interrupt ResourceSource support” in the
Platform-Wide _OSC (bit 13 in Table 6.13), the ResourceSourceIndex parameter must be zero.
The following example illustrates how to specify consumption of a “secondary interrupt”. In this example, the device
SDC0 consumes a secondary interrupt from MUX0, which multiplexes a group of secondary interrupts lines and
generates a single summary interrupt (also referred to as an “interrupt producer”). The device driver for MUX0 is

expected to generate a speciﬁc software based secondary interrupt based on implementation deﬁned details of that
device:
Device(MUX0){
Name(_HID, "ACME0F0F") // vendor specific interrupt combiner
Name(_CRS, ResourceTemplate () {
//Register Interface
MEMORY32FIXED(ReadWrite, 0x30000000, 0x200, )
//Summary Interrupt line (GSIV 51)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {51}
})
}
Device(SDC0){
Name(_HID, EISAID("PNP0D40")) // SDA Standard Compliant SD Host Controller
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MEMORY32FIXED(ReadWrite, 0xFF000000, 0x200, )
// Secondary Interrupt 10 from interrupt combiner MUX0
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, “\\_SB.MUX0”){10}
}
)
}
}
19.6.65 IO (IO Resource Descriptor Macro)
Syntax :
IO (Decode , AddressMin, AddressMax, AddressAlignment, RangeLength, DescriptorName) =>
˓→Buffer
Argument
Decode describes whether the I/O range uses 10-bit decode (Decode10) or 16-bit decode (Decode16). The ﬁeld De-
scriptorName. _DEC is automatically created to refer to this portion of the resource descriptor, where ‘1’ is Decode16
and ‘0’ is Decode10.
AddressMin evaluates to a 16-bit integer that speciﬁes the minimum acceptable starting address for the I/O range. It
must be an even multiple of AddressAlignment. The ﬁeld DescriptorName._MIN is automatically created to refer to
AddressMax evaluates to a 16-bit integer that speciﬁes the maximum acceptable starting address for the I/O range. It
must be an even multiple of AddressAlignment. The ﬁeld DescriptorName._MAX is automatically created to refer to
AddressAlignment evaluates to an 8-bit integer that speciﬁes the alignment granularity for the I/O address assigned.
The ﬁeld DescriptorName. _ALN is automatically created to refer to this portion of the resource descriptor.
RangeLength evaluates to an 8-bit integer that speciﬁes the number of bytes in the I/O range. The ﬁeld Descriptor-
Name. _LEN is automatically created to refer to this portion of the resource descriptor.
The IO macro evaluates to a buffer that contains an IO resource descriptor. The format of the IO descriptor can
be found in Section 6.4.2.5. This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer
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19.6.66 IRQ (Interrupt Resource Descriptor Macro)
Syntax :
IRQ ( EdgeLevel, ActiveLevel, Shared, DescriptorName ) {InterruptList} => Buffer
Arguments
Name._HE is automatically created to refer to this portion of the resource descriptor, where ‘1’ is Edge and ‘0’ is
Level.
torName._LL is automatically created to refer to this portion of the resource descriptor, where ‘1’ is ActiveLow and
The ﬁeld DescriptorName._SHR is automatically created to refer to this portion of the resource descriptor, where ‘1’
InterruptList is a comma-delimited list of integers in the range 0 through 15, at least one value is required. There may
be no duplicates in the list.
The IRQ macro evaluates to a buffer that contains an IRQ resource descriptor. The format of the IRQ descriptor can
be found in Section 6.4.2.1. This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer
19.6.67 IRQNoFlags (Interrupt Resource Descriptor Macro)
Syntax :
IRQNoFlags ( DescriptorName ) { InterruptList } => Buffer
Arguments
scope that contains the offset of this resource descriptor within the current resource template buffer.
be no duplicates in the list Description
The IRQNoFlags macro evaluates to a buffer that contains an active-high, edge-triggered IRQ resource descriptor.
The format of the IRQ descriptor can be found in Section 6.4.2.1. This macro is designed to be used inside of a
19.6. ASL Operator Reference 928Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.68 LAnd (Logical And)
Syntax :
LAnd ( Source1, Source2 ) => Boolean
Source1 &&Source2 => Boolean
Arguments
Source1 andSource2 are evaluated as integers.
If both values are non-zero, True is returned: otherwise, False is returned.
19.6.69 LEqual (Logical Equal)
Syntax :
LEqual (Source1, Source2) => Boolean
Source1 ==Source2 => Boolean
Arguments
Source1 andSource2 must each evaluate to an integer, a string, or a buffer. The data type of Source1 dictates the
required type of Source2. Source2 is implicitly converted if necessary to match the type of Source1.
If the values are equal, True is returned; otherwise, False is returned. For integers, a numeric compare is performed.
For strings and buffers, True is returned only if both lengths are the same and the result of a byte-wise compare
indicates exact equality.
19.6.70 LGreater (Logical Greater)
Syntax :
LGreater (Source1, Source2) => Boolean
Source1 >Source2 => Boolean
Arguments
If Source1 is greater than Source2, True is returned; otherwise, False is returned. For integers, a numeric comparison
is performed. For strings and buffers, a lexicographic comparison is performed. True is returned if a byte-wise
(unsigned) compare discovers at least one byte in Source1 that is numerically greater than the corresponding byte in
Source2. False is returned if at least one byte in Source1 is numerically less than the corresponding byte in Source2.
In the case of byte-wise equality, True is returned if the length of Source1 is greater than Source2, False is returned if
the length of Source1 is less than or equal to Source2.
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19.6.71 LGreaterEqual (Logical Greater Than Or Equal)
Syntax :
LGreaterEqual (Source1, Source2) => Boolean
Source1 >=Source2 => Boolean
Arguments
If Source1 is greater than or equal to Source2, True is returned; otherwise, False is returned. Equivalent to
LNot(LLess()). See the description of the LLess operator.
19.6.72 LLess (Logical Less)
Syntax :
LLess (Source1, Source2) => Boolean
Source1 < source2 => Boolean
Arguments
If Source1 is less than Source2, True is returned; otherwise, False is returned. For integers, a numeric comparison is
performed. For strings and buffers, a lexicographic comparison is performed. True is returned if a byte-wise (unsigned)
compare discovers at least one byte in Source1 that is numerically less than the corresponding byte in Source2. False
is returned if at least one byte in Source1 is numerically greater than the corresponding byte in Source2. In the case

Syntax :
Arguments
of byte-wise equality, True is returned if the length of Source1 is less than Source2, False is returned if the length of
Source1 is greater than or equal to Source2.
19.6.73 LLessEqual (Logical Less Than Or Equal)
Syntax :
LLessEqual (Source1, Source2) => Boolean
Source1 <= source2 => Boolean
Arguments
If Source1 is less than or equal to Source2, True is returned; otherwise False is returned. Equivalent to
LNot(LGreater()). See the description of the LGreater operator.
19.6. ASL Operator Reference 930Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.74 LNot (Logical Not)
Syntax :
LNot (Source) => Boolean
!Source => Boolean
Arguments
Source is evaluated as an integer.
If the value is zero True is returned; otherwise, False is returned.
19.6.75 LNotEqual (Logical Not Equal)
Syntax :
LNotEqual ( Source1, Source2 ) => Boolean
Source1 != Source2 => Boolean
Arguments
Source1 and Source2 must each evaluate to an integer, a string, or a buffer. The data type of Source1 dictates the
If Source1 is not equal to Source2, True is returned; otherwise False is returned. Equivalent to LNot(LEqual()).See
the description of the LEqual operator.
19.6.76 Load (Load Deﬁnition Block)
Syntax :
Load (Object, Result) => Boolean
Arguments
The Object parameter can refer to one of the following object types:
1. An operation region ﬁeld
2. An operation region directly
3. An ASL Buffer object
If the object is an operation region, the operation region must be in SystemMemory space. The Deﬁnition Block
should contain an ACPI DESCRIPTION_HEADER of type SSDT. The Deﬁnition Block must be totally contained
within the supplied operation region, operation region ﬁeld, or Buffer object. OSPM reads this table into memory, the
checksum is veriﬁed, and then it is loaded into the ACPI namespace.
Result is optional and is a Boolean indicating the status of the operation. A value of zero (false) means the operation
failed. Any other value means that the operation was successful. Also, this value is always returned as the function
return value
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Performs a run-time load of a Deﬁnition Block. Any table loaded via an operation region must be in memory marked
as AddressRangeReserved or AddressRangeNVS. The OS can also check the OEM Table ID and Revision ID against
a database for a newer revision Deﬁnition Block of the same OEM Table ID and load it instead.
The default namespace location to load the Deﬁnition Block is relative to the root of the namespace. The new Deﬁ-
nition Block can override this by specifying absolute names or by adjusting the namespace location using the Scope
operator.
Loading a Deﬁnition Block is a synchronous operation. Upon completion of the operation, the Deﬁnition Block has
been loaded. The control methods deﬁned in the Deﬁnition Block are not executed during load time.
19.6.77 LoadTable (Load Deﬁnition Block From XSDT)
Syntax :
LoadTable ( SignatureString, OEMIDString, OEMTableIDString,
RootPathString, ParameterPathString, ParameterData ) => Boolean
Arguments
The XSDT is searched for a table where the Signature ﬁeld matches SignatureString, the OEM ID ﬁeld matches
OEMIDString, and the OEM Table ID matches OEMTableIDString. All comparisons are case sensitive. If the Sig-
natureString is greater than four characters, the OEMIDString is greater than six characters, or the OEMTableID is
greater than eight characters, a run-time error is generated. The OS can also check the OEM Table ID and Revision
ID against a database for a newer revision Deﬁnition Block of the same OEM Table ID and load it instead.
The RootPathString speciﬁes the root of the Deﬁnition Block. It is evaluated using normal scoping rules, assuming that
the scope of the LoadTable instruction is the current scope. The new Deﬁnition Block can override this by specifying
absolute names or by adjusting the namespace location using the Scope operator. If RootPathString is not speciﬁed,
“" is assumed
If ParameterPathString and ParameterData are speciﬁed, the data object speciﬁed by ParameterData is stored into the
object speciﬁed by ParameterPathString after the table has been added into the namespace. If the ﬁrst character of
ParameterPathString is a backslash (‘') or caret (‘^’) character, then the path of the object is ParameterPathString. Oth-
erwise, it is RootPathString.ParameterPathString. If the speciﬁed object does not exist, a run-time error is generated.
The status of the operation is returned as a Boolean. A value of zero (false) means the operation failed. Any other
value means that the operation was successful.
Performs a run-time load of a Deﬁnition Block from the XSDT. Any table referenced by LoadTable must be in memory
marked by AddressRangeReserved or AddressRangeNVS.
Note: OSPM loads the DSDT and all SSDTs during initialization. As such, Deﬁnition Blocks to be conditionally
loaded via LoadTable must contain signatures other than “SSDT” .
Example :
Store (LoadTable ("OEM1", "MYOEM", "TABLE1", "\\_SB.PCI0","MYD", Package () {0,"\\_SB.
˓→PCI0"}), Local0)
This operation would search through the RSDT or XSDT for a table with the signature “OEM1,” the OEM ID of
“MYOEM,” and the table ID of “TABLE1.” If not found, it would store Zero in Local0. Otherwise, it will store a
package containing 0 and “\_SB.PCI0” into the variable at \_SB.PCI0.MYD.
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19.6.78 Localx (Method Local Data Objects)
Syntax :
Local0 | Local1 | Local2 | Local3 | Local4 | Local5 | Local6 | Local7
Up to 8 local objects can be referenced in a control method. On entry to a control method, these objects are uninitialized
and cannot be used until some value or reference is stored into the object. Once initialized, these objects are preserved
in the scope of execution for that control method.
19.6.79 LOr (Logical Or)
Syntax :
LOr ( Source1, Source2 ) => Boolean
Source1 || Source2 => Boolean
Arguments
If either value is non-zero, True is returned; otherwise, False is returned.
19.6.80 Match (Find Object Match)
Syntax :
Match ( SearchPackage, Op1, MatchObject1, Op2, MatchObject2, StartIndex ) => Ones \|
˓→Integer
Arguments
SearchPackage is evaluated to a package object and is treated as a one-dimension array. Each package element must
evaluate to either an integer, a string, or a buffer. Uninitialized package elements and elements that do not evaluate to
integers, strings, or buffers are ignored. Op1 and Op2 are match operators. MatchObject1 and MatchObject2 are the
objects to be matched and must each evaluate to either an integer, a string, or a buffer. StartIndex is the starting index
within the SearchPackage.
A comparison is performed for each element of the package, starting with the index value indicated by StartIndex (0
is the ﬁrst element). If the element of SearchPackage being compared against is called P[i], then the comparison is:
If (P[i] Op1 MatchObject1) and (P[i] Op2 MatchObject2) then Match => i is returned.
If the comparison succeeds, the index of the element that succeeded is returned; otherwise, the constant object Ones
is returned. The data type of the MatchObject dictates the required type of the package element. If necessary, the
package element is implicitly converted to match the type of the MatchObject. If the implicit conversion fails for any
reason, the package element is ignored (no match.)
Op1 and Op2 have the values and meanings listed in the following table.
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Table 19.35: Match Term Operator Meanings
Operator Encoding Macro
TRUE - A don’t care, always returns TRUE 0 MTR
EQ - Returns TRUE if P[i] == MatchObject 1 MEQ
LE - Returns TRUE if P[i] <= MatchObject 2 MLE
LT - Returns TRUE if P[i] < MatchObject 3 MLT
GE - Returns TRUE if P[i] >= MatchObject 4 MGE
GT - Returns TRUE if P[i] > MatchObject 5 MGT
Example
Following are some example uses of Match:
Name (P1,
Package () {1981, 1983, 1985, 1987, 1989, 1990, 1991, 1993, 1995, 1997, 1999, 2001}
)
// match 1993 == P1[i]
Match (P1, MEQ, 1993, MTR, 0, 0) // -> 7, since P1[7] == 1993
// match 1984 == P1[i]

Example
Name (P1,
)
Match (P1, MEQ, 1984, MTR, 0, 0) // -> ONES (not found)
// match P1[i] > 1984 and P1[i] <= 2000
Match (P1, MGT, 1984, MLE, 2000, 0) // -> 2, since P1[2]>1984 and P1[2]<=2000
// match P1[i] > 1984 and P1[i] <= 2000, starting with 3rd element
Match (P1, MGT, 1984, MLE, 2000, 3) // -> 3, first match at or past Start
19.6.81 Memory24 (Memory Resource Descriptor Macro)
Syntax :
Memory24 (ReadAndWrite, AddressMinimu, AddressMaximum, AddressAlignment, RangeLength,
˓→DescriptorName)
Arguments
AddressMinimum evaluates to a 16-bit integer that speciﬁes bits [8:23] of the lowest possible base address of the
memory range. All other bits are assumed to be zero. The value must be an even multiple of AddressAlignment. The
16-bit ﬁeld DescriptorName._MIN is automatically created to refer to this portion of the resource descriptor.
AddressMaximum evaluates to a 16-bit integer that speciﬁes bits [8:23] of the highest possible base address of the
16-bit ﬁeld DescriptorName._MAX is automatically created to refer to this portion of the resource descriptor.
AddressAlignment evaluates to a 16-bit integer that speciﬁes bits [0:15] of the required alignment for the memory
range. All other bits are assumed to be zero. The address selected must be an even multiple of this value. The 16-bit
ﬁeld DescriptorName. _ALN is automatically created to refer to this portion of the resource descriptor.
RangeLength evaluates to a 16-bit integer that speciﬁes the total number of bytes decoded in the memory range. The
16-bit ﬁeld DescriptorName. _LEN is automatically created to refer to this portion of the resource descriptor. The
range length provides the length of the memory range in 256 byte blocks.
19.6. ASL Operator Reference 934Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The Memory24 macro evaluates to a buffer that contains an 24-bit memory descriptor. The format of this descriptor
can be found in Table 6.40. This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer
Note: The use of Memory24 is deprecated and should not be used in new designs*.
19.6.82 Memory32 (Memory Resource Descriptor Macro)
Syntax :
Memory32 (ReadAndWrite, AddressMinimum, AddressMaximum, AddressAlignment, RangeLength,
Arguments
AddressMinimum evaluates to a 32-bit integer that speciﬁes the lowest possible base address of the memory range.
The value must be an even multiple of AddressAlignment. The 32-bit ﬁeld DescriptorName._MIN is automatically
AddressMaximum evaluates to a 32-bit integer that speciﬁes the highest possible base address of the memory range.
The value must be an even multiple of AddressAlignment. The 32-bit ﬁeld DescriptorName._MAX is automatically
AddressAlignment evaluates to a 32-bit integer that speciﬁes the required alignment for the memory range. The address
selected must be an even multiple of this value. The 32-bit ﬁeld DescriptorName. _ALN is automatically created to
refer to this portion of the resource descriptor.
RangeLength evaluates to a 32-bit integer that speciﬁes the total number of bytes decoded in the memory range. The
32-bit ﬁeld DescriptorName. _LEN is automatically created to refer to this portion of the resource descriptor. The
range length provides the length of the memory range in 1 byte blocks.
The Memory32 macro evaluates to a buffer that contains a 32-bit memory descriptor, which describes a memory range
with a minimum, a maximum and an alignment. The format of this descriptor can be found in Section 6.4.3.3. This
19.6. ASL Operator Reference 935Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.83 Memory32Fixed (Memory Resource Descriptor Macro)
Syntax :
Memory32Fixed (ReadAndWrite, AddressBase, RangeLength, DescriptorName)
Arguments
AddressBase evaluates to a 32-bit integer that speciﬁes the base address of the memory range. The 32-bit ﬁeld De-
scriptorName. _BAS is automatically created to refer to this portion of the resource descriptor.
32-bit ﬁeld DescriptorName. _LEN is automatically created to refer to this portion of the resource descriptor.
The Memory32Fixed macro evaluates to a buffer that contains a 32-bit memory descriptor, which describes a ﬁxed
range of memory addresses. The format of this memory descriptor can be found in Section 6.4.3.4. This macro is
19.6.84 Method (Declare Control Method)
Syntax :
Method ( MethodName, NumArgs, SerializeRule, SyncLevel, ReturnType, ParameterTypes )
˓→{TermList}
Arguments
MethodName is evaluated as a Namestring data type.
NumArgs is optional and is the required number of arguments to be passed to the method, evaluated as an Integer data
type. If not speciﬁed, the default value is zero arguments. Up to 7 arguments may be passed to a method. These
arguments may be referenced from within the method as Arg0 through Arg6.
SerializeRule is optional and is a ﬂag that deﬁnes whether the method is serialized or not and is one of the following:
Serialized or NotSerialized. A method that is serialized cannot be reentered by additional threads. If not speciﬁed, the
default is NotSerialized.
SyncLevel is optional and speciﬁes the synchronization level for the method (0 - 15). If not speciﬁed, the default sync
level is zero.
separated ObjectTypeKeywords with braces. For example: {IntObj, BuffObj}.
ParameterTypes is optional and speciﬁes the type of the method parameters. It is a comma-separated, variable-length
list of the expected object type or types for each of the method parameters, enclosed in braces. For each parameter,
the parameter type consists of either an ObjectTypeKeyword or a comma-separated sub-list of ObjectTypeKeywords
enclosed in braces. If ParameterTypes is speciﬁed, the number of parameters must match NumArgs.
19.6. ASL Operator Reference 936Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
TermList is a variable-length list of executable ASL statements representing the body of the control method.

Creates a new control method of name MethodName. This is a named package containing a series of object references
that collectively represent a control method, which is a procedure that can be invoked to perform computation. Method
opens a name scope.
System software executes a control method by referencing the objects in the package in order. For more information
on method execution, see Section 5.5.2
If a method is declared as Serialized, an implicit mutex associated with the method object is acquired at the speciﬁed
SyncLevel. If no SyncLevel is speciﬁed, SyncLevel 0 is assumed. The serialize rule can be used to prevent reenter-
ing of a method. This is especially useful if the method creates namespace objects. Without the serialize rule, the
reentering of a method will fail when it attempts to create the same namespace object.
There are eight local variables automatically available for each method, referenced as Local0 through Local7. These
locals may be used to store any type of ASL object.
Also notice that all namespace objects created by a method have temporary lifetime. When method execution exits,
the created objects will be destroyed.
Examples
The following block of ASL sample code shows a use of Method for deﬁning a control method that turns on a power
resource.
Method (_ON) {
Store (One, GIO.IDEP) // assert power
Store (One, GIO.IDER) // de-assert reset#
Store (Zero, GIO.IDEI) // de-assert isolation
}
This method is an implementation of _SRS (Set Resources). It shows the use of a method argument and two method
locals:
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, One, IRQW)
Store (\_SB.PCI0.PID1.IENA, Local1)
Or (IRQW, Local1, Local1)
Store (Local1, \\_SB.PCI0.PID1.IENA)
FindSetRightBit (IRQW, Local0)
If (Local0)
{
Decrement (Local0)
Store (Local0, \\_SB.PCI0.PID1.IN01)
}
}
19.6. ASL Operator Reference 937Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.85 Mid (Extract Portion of Buffer or String)
Syntax :
Mid ( Source, Index, Length, Result ) => Buffer or String
Arguments
Source is evaluated as either a Buffer or String. Index and Length are evaluated as Integers.
If Source is a buffer, then Length bytes, starting with the Indexth byte (zero-based) are optionally copied into Result.
If Index is greater than or equal to the length of the buffer, then the result is an empty buffer. Otherwise, if Index +
Length is greater than or equal to the length of the buffer, then only bytes up to and including the last byte are included
in the result.
If Source is a string, then Length characters, starting with the Indexth character (zero-based) are optionally copied into
Result. If Index is greater than or equal to the length of the buffer, then the result is an empty string. Otherwise, if
Index + Length is greater than or equal to the length of the string, then only bytes up to an including the last character
are included in the result.
19.6.86 Mod (Integer Modulo)
Syntax :
Mod ( Dividend, Divisor, Result ) => Integer
Result = Dividend % Divisor => Integer
Result %= Divisor => Integer
Arguments
The Dividend is divided by Divisor, and then the resulting remainder is optionally stored into Result. If Divisor
evaluates to zero, a fatal exception is generated.
19.6.87 Multiply (Integer Multiply)
Syntax :
Multiply ( Multiplicand, Multiplier, Result ) => Integer
Result = Multiplicand \ Multiplier => Integer
Result \= Multiplier => Integer
Arguments
Multiplicand andMultiplier are evaluated as Integers.
The Multiplicand is multiplied by Multiplier and the result is optionally stored into Result. Overﬂow conditions are
ignored and results are undeﬁned.
19.6. ASL Operator Reference 938Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.88 Mutex (Declare Synchronization/Mutex Object)
Syntax :
Mutex ( MutexName, SyncLevel )
Arguments
The MutexName is evaluated as a Namestring data type.
The SyncLevel is optional and speciﬁes the logical nesting level of the Mutex synchronization object. The current
sync level is maintained internally for a thread, and represents the greatest SyncLevel among mutex objects that are
currently acquired by the thread. The SyncLevel of a thread, before acquiring any mutexes, is zero. The SyncLevel of
the Global Lock (_GL) is zero. If not speciﬁed, the default sync level value is zero.
Creates a data mutex synchronization object named MutexName, with a synchronization level from 0 to 15 as speciﬁed
by the Integer SyncLevel.
A mutex synchronization object provides a control method with a mechanism for waiting for certain events. To prevent
deadlocks, wherever more than one synchronization object must be owned, the synchronization objects must always
be released in the order opposite the order in which they were acquired.
The SyncLevel parameter declares the logical nesting level of the synchronization object. The current sync level
is maintained internally for a thread, and represents the greatest SyncLevel among mutex objects that are currently
acquired by the thread. The SyncLevel of a thread before acquiring any mutexes is zero. The SyncLevel of the Global
Lock (_GL) is zero.
All Acquire terms must refer to a synchronization object with a SyncLevel that is equal or greater than the current
level, and all Release terms must refer to a synchronization object with a SyncLevel that is equal to the current level.
Mutex synchronization provides the means for mutually exclusive ownership. Ownership is acquired using an Acquire
term and is released using a Release term. Ownership of a Mutex must be relinquished before completion of any
invocation. For example, the top-level control method cannot exit while still holding ownership of a Mutex. Acquiring
ownership of a Mutex can be nested (can be acquired multiple times by the same thread).
19.6.89 Name (Declare Named Object)
Syntax :
Name ( ObjectName, Object )
Arguments
Creates a new object named ObjectName. Attaches Object to ObjectName in the Global ACPI namespace.
Creates ObjectName in the namespace, which references the Object.
Example
The following example creates the name PTTX in the root of the namespace that references a package.
Name (\PTTX, // Port to Port Translate Table
Package () {Package () {0x43, 0x59}, Package) {0x90, 0xFF}}
)
The following example creates the name CNT in the root of the namespace that references an integer data object with
the value 5:
19.6. ASL Operator Reference 939Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Name (\CNT, 5)
19.6.90 NAnd (Integer Bitwise Nand)
Syntax :
NAnd (Source1, Source2, Result) => Integer
Arguments
A bitwise NAND is performed and the result is optionally stored in Result.
19.6.91 NoOp Code (No Operation)
Syntax :
NoOp
This operation has no effect.
19.6.92 NOr (Integer Bitwise Nor)
Syntax :
NOr (Source1, Source2, Result) => Integer
Arguments
A bitwise NOR is performed and the result is optionally stored in Result.
19.6.93 Not (Integer Bitwise Not)
Syntax :
Not (Source, Result) => Integer
Result = ~Source => Integer
Arguments
Source is evaluated as an integer data type.
A bitwise NOT is performed and the result is optionally stored in Result.
19.6. ASL Operator Reference 940Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.94 Notify (Notify Object of Event)
Syntax :
Notify (Object, NotificationValue)
Arguments
Notiﬁes the OS that the NotiﬁcationValue for the Object has occurred. Object must be a reference to a device, proces-
sor, or thermal zone object.
Object type determines the notiﬁcation values. For example, the notiﬁcation values for a thermal zone object are
different from the notiﬁcation values used for a device object. Undeﬁned notiﬁcation values are treated as reserved
and are ignored by the OS.
For lists of deﬁned Notiﬁcation values, see Section 5.6.6
19.6.95 Offset (Change Current Field Unit Offset)
Syntax :
Offset (ByteOffset)
Arguments
ByteOffset is the new offset (in bytes) for the next FieldUnit within a FieldList.
The Offset operator is used within a FieldList to specify the byteOffset of the next deﬁned ﬁeld within its parent
operation region. This can be used instead of deﬁning the bit lengths that need to be skipped. All offsets are deﬁned
starting from zero, based at the starting address of the parent region.

Arguments
Syntax :
Arguments
19.6.96 ObjectType (Get Object Type)
Syntax :
ObjectType (Object) => Integer
Arguments
Object is any valid object.
The execution result of this operation is an integer that has the numeric value of the object type for Object.
The object type codes are listed in the following table. Note that if this operation is performed on an object reference
such as one produced by the Alias, Index, or RefOf statements, the object type of the base object is returned. For
typeless objects such as predeﬁned scope names (in other words, \_SB, \_GPE, etc.), the type value 0 (Uninitialized)
Table 19.36: Values Returned By the ObjectType Operator
Value Object
0 Uninitialized
19.6. ASL Operator Reference 941Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 19.36 – continued from previous page
1 Integer
2 String
3 Buffer
4 Package
5 Field Unit
6 Device
7 Event
8 Method
9 Mutex
10 Operation Region
11 Power Resource
12 Reserved
13 Thermal Zone
14 Buffer Field
16 Debug Object
>16 Reserved
19.6.97 One (Constant One Integer)
Syntax :
One => Integer
The One operator returns an Integer with the value 1. Writes to this object are not allowed. The use of this operator
can reduce AML code size, since it is represented by a one-byte AML opcode.
19.6.98 Ones (Constant Ones Integer)
Syntax :
Ones => Integer
The Ones operator returns an Integer with all bits set to 1. Writes to this object are not allowed. The use of this
operator can reduce AML code size, since it is represented by a one-byte AML opcode.
Note: The actual value of the integer returned by the Ones operator depends on the integer width of the DSDT. If the
revision of the DSDT is 1 or less, the integer width is 32 bits and Ones returns 0xFFFFFFFF . If the revision of the
DSDT is 2 or greater, the integer width is 64 bits and Ones returns 0xFFFFFFFFFFFFFFFF . This difference must be
considered when performing comparisons against the Ones Integer.
19.6. ASL Operator Reference 942Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.99 OperationRegion (Declare Operation Region)
Syntax :
OperationRegion (RegionName, RegionSpace, Offset, Length)
Arguments
Declares an operation region named RegionName. Offset is the offset within the selected RegionSpace at which the
region starts (byte-granular), and Length is the length of the region in bytes.
An Operation Region is a type of data object where read or write operations to the data object are performed in some
hardware space. For example, the Deﬁnition Block can deﬁne an Operation Region within a bus, or system I/O space.
Any reads or writes to the named object will result in accesses to the I/O space.
Operation regions are regions in some space that contain hardware registers for exclusive use by ACPI control methods.
In general, no hardware register (at least byte-granular) within the operation region accessed by an ACPI control
method can be shared with any accesses from any other source, with the exception of using the Global Lock to share
a region with the ﬁrmware. The entire Operation Region can be allocated for exclusive use to the ACPI subsystem in
the host OS.
Operation Regions that are deﬁned within the scope of a method are the exception to this rule. These Operation
Regions are known as “Dynamic” since the OS has no idea that they exist or what registers they use until the control
method is executed. Using a Dynamic SystemIO or SystemMemory Operation Region is not recommended since the
OS cannot guarantee exclusive access. All other types of Operation Regions may be Dynamic.
Operation Regions deﬁne the overall base address and length of a hardware region, but they cannot be accessed directly
by AML code. A Field object containing one or more FieldUnits is used to overlay the Operation Region in order to
access individual areas of the Region. An individual FieldUnit within an Operation Region may be as small as one
bit, or as large as the length of the entire Region. FieldUnit values are normalized (shifted and masked to the proper
length.) The data type of a FieldUnit can be either a Buffer or an Integer, depending on the bit length of the FieldUnit.
If the FieldUnit is smaller than or equal to the size of an Integer (in bits), it will be treated as an Integer. If the FieldUnit
is larger than the size of an Integer, it will be treated as a Buffer. The size of an Integer is indicated by the DSDT
header’s Revision ﬁeld. A revision less than 2 indicates that the size of an Integer is 32 bits. A value greater than or
equal to 2 signiﬁes that the size of an Integer is 64 bits. For more information about data types and FieldUnit type
conversion rules, see Section 19.3.5.7 .
An Operation Region object implicitly supports Mutex synchronization. Updates to the object, or a Field data object
for the region, will automatically synchronize on the Operation Region object; however, a control method may also
explicitly synchronize to a region to prevent other accesses to the region (from other control methods). Notice that
according to the control method execution model, control method execution is non-preemptive. Because of this,
explicit synchronization to an Operation Region needs to be done only in cases where a control method blocks or
yields execution and where the type of register usage requires such synchronization.
The predeﬁned Operation Region types speciﬁed in ACPI are shown in Table 5.182
Example
The following example ASL code shows the use of OperationRegion combined with Field to describe IDE 0 and 1
controlled through general I/O space, using one FET:
OperationRegion (GIO, SystemIO, 0x125, 0x1)
Field (GIO, ByteAcc, NoLock, Preserve) {
IDEI, 1, // IDEISO_EN - isolation buffer
IDEP, 1, // IDE_PWR_EN - power
IDER, 1 // IDERST#_EN - reset#
}
19.6. ASL Operator Reference 943Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.100 Or (Integer Bitwise Or)
Syntax :
Or (Source1, Source2, Result) => Integer
*Result*=*Source1*\|*Source2*=> Integer
*Result*\|=*Source1*=> Integer
Arguments
A bitwise OR is performed and the result is optionally stored in Result.
19.6.101 Package (Declare Package Object)
Syntax :
Package (NumElements) {PackageList} => Package
Arguments
NumElements is evaluated as an Integer. PackageList is an initializer list of objects.
Declares an unnamed aggregation of named data items, constants, and/or references to non-data namespace objects.
The size of the package is NumElements . The PackageList contains the data items, constants, and/or object references
used to initialize the package.
IfNumElements is absent, it is automatically set by the ASL compiler to match the number of elements in the Package-
List. If NumElements is present and greater than the number of elements in the PackageList , the default entry of type
Uninitialized (see ObjectType) is used to initialize the package elements beyond those initialized from the PackageList
.
There are three types of package elements allowed in the PackageList: ConstantData Objects(Integers, Strings,
Buffers, and Packages), named references that resolve to Data Objects (Integers, Strings, Buffers, and Packages),
and named references to objects other than Data Objects.
These constant terms are resolved at ASL compile time:
• Integer Constant
• String Constant
• Buffer Constant
• Package Constant
These Named References to Data Objects are resolved to actual data by the AML Interpreter at runtime:
• Integer reference
• String reference
• Buffer reference
• Buffer Field reference
• Field Unit reference
• Package reference
19.6. ASL Operator Reference 944Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
These Named References to non-Data Objects cannot be resolved to values. They are instead returned in the package
as references:
• Device reference
• Event reference
• Method reference
• Mutex reference
• Operation Region reference
• Power Resource reference
• Processor reference
• Thermal Zone reference
Note: For Package elements of type Package (deﬁning a subpackage), individual elements of the subpackage are
resolved according to the rules above, both compile-time and runtime.*
Evaluating an uninitialized element will yield a runtime error, but elements can be assigned values at runtime to deﬁne
them (via the Index operator). It is a compile time error for NumElements to be less than the number of elements
deﬁned in the PackageList .
The ASL compiler can emit two different AML opcodes for a Package declaration, either PackageOp orVarPacka-
geOp . For small, ﬁxed-length packages, the PackageOp is used and this opcode is compatible with ACPI 1.0. A
VarPackageOp will be emitted if any of the following conditions are true:
• The NumElements argument is a TermArg that can only be resolved at runtime.

• At compile time, NumElements resolves to a constant that is larger than 255.
• The PackageList contains more than 255 initializer elements.
Example :
Name (INT1, 0x1234)
Processor (CPU0, 0, 0x1010, 6) {}
PowerResource (PWR1, 0, 0) {}
Name (PKG1, Package () {
0x3400, // Integer Constant, resolved at compile time
"Processor " // String Constant, resolved at compile time
\INT1 // Integer Reference, resolved to value at
// runtime
\CPU0 // Object Reference, returned as a reference
// object
Package () { // Package Constant. Elements are resolved at
// both compile time and runtime
0x4321, // Integer Constant, resolved at compile time
\INT1, // Integer Reference, resolved to value at
// runtime
\PWR1
})
The runtime values of the parent package and subpackages are:
19.6. ASL Operator Reference 945Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Package [Contains 0x05 Elements] {
(00) Integer 0x0000000000003400
(01) String [0x09] "Processor"
(02) Integer 0x0000000000001234
(03) Reference [Named Object] [CPU0] Processor
(04) Package [Contains 0x03 Elements]
(00) Integer 0x0000000000004321
(01) Integer 0x0000000000001234
(02) Reference [Named Object] [PWR1] Power
}
19.6.102 PinConﬁg (Pin Conﬁguration Descriptor Macro)
Syntax :
Macro:
PinConfig (Shared/Exclusive, PinConfigType, PinConfigValue, ResourceSource,
ResourceSourceIndex, ResourceUsage, DescriptorName, VendorData) {Pin List}
Arguments
•Shared is an optional argument and can be either Shared or Exclusive. If not speciﬁed, Exclusive is assumed.
The bit ﬁeld name _SHR is automatically created to refer to this portion of the resource descriptor.
•PinConﬁgType can be one of the conﬁguration types described below in Pin Conﬁguration Types and Values .
The bit ﬁeld _TYP is automatically created to refer to this portion of the resource descriptor.
•PinConﬁgValue is one of the conﬁgurations values described below in Pin Conﬁguration Types and Values . The
bit ﬁeld _V AL is automatically created to refer to this portion of the resource descriptor.
•ResourceSource is a string which uniquely identiﬁes the pin controller referred to by this descriptor. Resource-
Source can be a fully-qualiﬁed name, a relative name or a name segment that utilizes the namespace search
rules.
•ResourceSourceIndex is an optional argument and is assumed to be 0 for this revision.
•ResourceUsage is an optional argument and is assumed to be ResourceConsumer for this revision.
•DescriptorName is an optional argument that speciﬁes a name for an integer constant that will be created in the
current scope that contains the offset of this resource descriptor within the current resource template buffer. The
predeﬁned descriptor ﬁeld names may be appended to this name to access individual ﬁelds within the descriptor
via the Buffer Field operators.
•VendorData is an optional argument that speciﬁes a RawDataBuffer containing vendor-deﬁned byte data to be
decoded by the OS driver. The bit ﬁeld name _VEN is automatically created to refer to this portion of the
•PinList is a list of pin numbers on the ResourceSource that are described by this descriptor. The bit ﬁeld name
_PIN is automatically created to refer to this portion of the resource descriptor.
Table 19.37: Pin Conﬁguration Types and Values
Pin Conﬁguration
TypePin Conﬁguration
ValueDescription
0x00 = Default N/A Default conﬁguration. No conﬁguration is applied.
19.6. ASL Operator Reference 946Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 19.37 – continued from previous page
0x01 = Bias Pull-Up Pull up resistance, in
Ohms.This means the pin is pulled up with a certain number
of Ohms to an implicitly supplied VDD rail.
0x02 = Bias Pull-down Pull down resistance, in
Ohms.This means the pin is pulled down with a certain number
of Ohms, toward the GND rail.
0x03 = Bias Default N/A If the silicon has a default biasing mode, reset the pin to
this mode.
0x04 = Bias Disable N/A Any software-selectable bias settings on the pin will be
disabled.
0x05 = Bias High
ImpedanceN/A This means that the pin is conﬁgured into a high
impedance mode and essentially shut off from the out-
side world. It will not inﬂuence the signal state if a rail
is connected to the pin, hence a good default mode.
0x06 = Bias Bus Hold N/A This will make the pin in a weak latch state where it
weakly drives the last value on a tristate bus.
0x07 = Drive Open Drain N/A This will conﬁgure the pin into open drain (open collec-
tor) state.
0x08 = Drive Open
SourceN/A This will conﬁgure the pin into open source (open emit-
ter) state.
0x09 = Drive Push Pull N/A This will conﬁgure the pin into explicit push-pull state.
This is useful if the power-on default state is e.g. open
drain or high impedance state.
0x0A = Drive Strength Drive strength in mil-
liamperesThis will set the output driver of the pin to supply a cer-
tain number of milliamperes, usually by activating sev-
eral driver stages.
0x0B = Slew Rate Custom format This controls the slew rate of the pin, affecting speed but
also sharpness of edges and thus noisiness on the board.
The hardware-speciﬁc argument tells what slew rate to
conﬁgure
0x0C = Input Debounce Debounce time in mi-
croseconds.This will enable debouncing (for e.g. key inputs) of the
pin signal.
0x0D = Input Schmitt
TriggerEnabled = 1, Disabled = 0 This will enable Schmitt trigger support for the line.
0x0E - 0x7F = Reserved Reserved Reserved
0x80 - 0xFF = Vendor de-
ﬁned valuesCustom base From this point, vendor and Hardware-speciﬁc conﬁgu-
rations are listed.
The PinConﬁg macro evaluates to a buffer that contains a Pin Conﬁguration resource descriptor, as described in Section
6.4.3.10. This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer Conversion Macro) .
Note : There is some overlap between the properties set by GpioIo/GpioInt/ PinFunction and PinConﬁg descriptors.
For example, both are setting properties such as pull-ups. If the same property is speciﬁed by multiple descriptors
for the same pins, the order in which these properties are applied is undetermined. To avoid any conﬂicts, Gpi-
oInt/GpioIo/PinFunction should provide a default value for these properties when PinConﬁg is used. If PinConﬁg is
used to set pin bias, PullDefault should be used for GpioIo/GpioInt/ PinFunction. If PinConﬁg is used to set debounce
timeout, 0 should be used for GpioIo/GpioInt. If PinConﬁg is used to set drive strength, 0 should be used for GpioIo.*
Example :
//
19.6. ASL Operator Reference 947Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
// Description: GPIO
//
Device (GPI0)
{
Name (_HID, "PNPFFFE")
Name (_UID, 0x0)
{
Return(0xf)
}
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0x4FE00000, 0x20)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {0x54}
})
Return(RBUF)
}
}
//
// Description: I2C controller 1
//
Device (I2C1)
{
Name (_HID, "PNPFFFF")
{
}
{
{
Memory32Fixed(ReadWrite, 0x4F800000, 0x20)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {0x55}
PinFunction(Exclusive, PullDefault, 0x5, "\\_SB.GPI0", 0, ResourceConsumer,
˓→) {2, 3}
// Configure 10k Pull up for I2C SDA/SCL pins
PinConfig(Exclusive, 0x01, 10000, "\\_SB.GPI0", 0, ResourceConsumer, ) {2, 3}
})
}
}
//
// Description: Physical display panel
//
Device (SDIO)
{
Name (_HID, "PNPFFFD")
{
19.6. ASL Operator Reference 948Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
}
{
{
Memory32Fixed(ReadWrite, 0x4F900000, 0x20)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {0x57}
GpioIo(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPI0",) {2, 3}
// Configure 20k Pull down
PinConfig(Exclusive, 0x02, 20000, "\\_SB.GPI0", 0, ResourceConsumer, ) {2, 3}
// Enable Schmitt-trigger
PinConfig(Exclusive, 0x0D, 1, "\\_SB.GPI0", 0, ResourceConsumer, ) {2, 3}
// Set slew rate to custom value 3
PinConfig(Exclusive, 0x0B, 3, "\\_SB.GPI0", 0, ResourceConsumer, ) {2, 3}
})
}
}
19.6.103 PinFunction (Pin Function Descriptor Macro)
Syntax :
Macro:
PinFunction (Shared/Exclusive, PinPullConfiguration, FunctionNumber, ResourceSource,
Arguments
•Shared is an optional argument and can be one of Shared, Exclusive. If not speciﬁed, Exclusive is assumed. The
bit ﬁeld name _SHR is automatically created to refer to this portion of the resource descriptor.

{
{
})
}
}
Syntax :
Macro:
Arguments
•PinPullConﬁguration can be one of PullDefault, PullUp, PullDown, PullNone or a vendor-supplied value in the
range 128-255.
•FunctionNumber is a provider-speciﬁc integer that designates which function is being described.
•ResourceSource is a string which uniquely identiﬁes the GPIO controller referred to by this descriptor. Re-
sourceSource can be a fully-qualiﬁed name, a relative name or a name segment that utilizes the namespace
search rules.
•PinList is a non-empty list of (zero-based) pin numbers on the ResourceSource that are described by this de-
scriptor. The bit ﬁeld name _PIN is automatically created to refer to this portion of the resource descriptor.
19.6. ASL Operator Reference 949Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The PinFunction macro evaluates to a buffer that contains a Pin Function resource descriptor, as described in this
section. This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer Conversion Macro) .
Note: PinFunction macro allows for maximum ﬂexibility to deﬁne the desired function of each pin individually. It is
the responsibility of the ﬁrmware writer to take into account any platform-level restrictions where pin function must be
applied at a coarser granularity. Thus, if the platform design requires the functions for a set of pins to be conﬁgured
as group, the ﬁrmware writer must ensure this is done in the corresponding PinFunction description by specifying all
relevant pins in a single PinFunction. In the multi-pin scenario, the OSPM must honor the PinFunction requirements
for all of the speciﬁed pins on an “all-or-nothing” basis.
Note: The Pin Function descriptor is intended for scenarios where non-GPIO functions are desired. For GPIO-based
functionalities, the ﬁrmware should always specify the appropriate GpioIo or Gpioint descriptor.
Example :
//
//
{
{
}
{
{
})
}
//
//
{
{
}
{
{
PinFunction(Exclusive, PullUp, 0x5, "\\_SB.GPI0", 0, ResourceConsumer,) {2,
˓→3}
19.6. ASL Operator Reference 950Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
})
}
}
//
// Description: I2C controller 2
//
Device (I2C2)
{
Name (_UID, 0x1)
{
}
{
{
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {0x56}
PinFunction(Exclusive, PullUp, 0x0, 0x4, "\\_SB.GPI0", 0, ResourceConsumer,
˓→) {2, 3}
})
}
}
//
//
Device (DISP)
{
{
}
{
{
})
}
}
19.6. ASL Operator Reference 951Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.104 PinGroup (Pin Group Descriptor Macro)
Syntax :
Macro:
PinGroup (ResourceLabel, ResourceUsage, DescriptorName, VendorData) {Pin List }
Arguments
•ResourceUsage is an optional argument and is assumed to be ResourceProducer for this revision.
•ResourceLabel is an arbitrary, non-empty string that uniquely identiﬁes this particular PinGroup resource from
others within a resource template buffer. This label is used by resource consumers to refer to this resource.
The PinGroup macro evaluates to a buffer that contains a Pin Group Conﬁguration resource descriptor. The format of
the Pin Group Conﬁguration resource descriptor can be found in Section 6.4.3.13. This macro is designed to be used
PinGroup resource descriptors must be declared within the scope of the pin controller device to which the pins belong.
19.6.105 PinGroupConﬁg (Pin Group Conﬁguration Descriptor Macro)
Syntax :
Macro:
PinGroupConfig (Shared/Exclusive, PinConfigType, PinConfigValue, ResourceSource,
ResourceSourceIndex, ResourceSourceLabel, ResourceUsage, DesriptorName, VendorData)
•PinConﬁgType can be one of the conﬁguration types described below in Pin Group Conﬁguration Types and
Values . The bit ﬁeld name _TYP is automatically created to refer to this portion of the resource descriptor.
•PinConﬁgValue is one of the conﬁgurations values described below in Pin Group Conﬁguration Types and
Values . The bit ﬁeld name _V AL is automatically created to refer to this portion of the resource descriptor.
•ResourceSource is a string that uniquely identiﬁes the GPIO controller which includes the PinGroup resource
referenced by this descriptor. ResourceSource can be a fully-qualiﬁed name, a relative name or a name segment
•ResourceSourceLabel is a non-empty string argument that matches ResourceLabel of the PinGroup resource in
the current resource template buffer of the GPIO controller referenced in ResourceSource.
19.6. ASL Operator Reference 952Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 19.38: Pin Group Conﬁguration Types and Values
0x00 = Default N/A Default conﬁguration. No conﬁguration is applied).
this mode.

this mode.
disabled.
conﬁgure
19.6. ASL Operator Reference 953Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The PinGroupConﬁg macro evaluates to a buffer that contains a Pin Group Conﬁguration resource descriptor. The
format of the Pin Group Conﬁguration resource descriptor can be found in Section 6.4.3.13. This macro is designed
to be used inside of a ResourceTemplate (Resource To Buffer Conversion Macro) .
Example :
//
//
{
{
}
{
{
PinGroup("group1", ResourceProducer) {2, 3}
})
}
//
//
{
{
}
{
{
// Set function I2C1 for SDA/SCL pins
PinGroupFunction(Exclusive, 0x5, "\\_SB.GPI0, 0, "group1", ResourceConsumer,
˓→)
// Configure 10k Pull up for SDA/SCL pins
PinGroupConfig(Exclusive, 0x01, 10000, "\\_SB.GPI0 ", 0, "group1",
˓→ResourceConsumer, )
})
}
}
19.6. ASL Operator Reference 954Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
//
//
{
{
}
{
{
// Set function I2C2 for SDA/SCL pins
PinGroupFunction(Exclusive, 0x4, "\\_SB.GPI0 ", 0, "group1",
˓→ResourceConsumer,)
})
}
}
//
//
{
{
}
{
{
// Set function GPIO for pin group group1
PinGroupFunction(Exclusive, 0x1, "\\_SB.GPI0 ", 0, "group1",
PinGroupConfig (Exclusive, 0x02, 20000, "\\_SB.GPI0 ", 0, "group1",
//Enable Schmitt-trigger
PinGroupConfig (Exclusive, 0x0D, 1, "\\_SB.GPI0 ", 0, "group1",
//Set slew rate to custom value 3
19.6. ASL Operator Reference 955Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
PinGroupConfig (Exclusive, 0x0B, 3, "\\_SB.GPI0 ", 0, "group1",
})
Return(RBUF)}
}
}
19.6.106 PinGroupFunction (Pin Group Function Conﬁguration Descriptor Macro)
Syntax :
Macro:
PinGroupFunction (Shared/Exclusive, FunctionNumber, ResourceSource,
˓→ResourceSourceIndex,
ResourceSourceLabel, ResourceUsage, DescriptorName, VendorData)
Arguments
•FunctionNumber is a provider-speciﬁc integer which designates which function is being described. The bit ﬁeld
name _FUN is automatically created to refere to this portion of the resource descriptor.
•ResourceSourceLabel is a non-empty string argument that matches ResourceLabel of a PinGroup resource in
• DescriptorName is an optional argument that speciﬁes a name for an integer constant that will be created in the
• ResourceUsage is an optional argument and is assumed to be ResourceConsumer for this revision.
The PinGroupFunction macro evaluates to a buffer that contains a Pin Function resource descriptor. The format of the
Pin Function resource descriptor can be found in Pin Function Descriptor . This macro is designed to be used inside
of aResourceTemplate (Resource To Buffer Conversion Macro) .
19.6. ASL Operator Reference 956Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.107 PowerResource (Declare Power Resource)
Syntax :
PowerResource (ResourceName, SystemLevel, ResourceOrder) {TermList}
Arguments
Declares a power resource named ResourceName. PowerResource opens a name scope.
For a deﬁnition of the PowerResource term, see Section 7.2
“Deﬁnition Block Loading :
19.6.108 Printf (Create and Store formatted string)
Syntax :
Printf (FormatString, FormatArgs) => String
Arguments
Printf is a macro that converts the evaluated FormatString into a series of string Concatenate operations, storing the
result in the Debug object.
string and type conversion is handled automatically by Concatenate .
The Printf macro converts a format string into a series of cascading string Concatenate operations, and stores the
result in the Debug object
Example
The following ASL example uses Printf to write a formatted string with the values of Arg0, Arg1, Arg2, and Arg3 to
the Debug Object:
Printf ("%o: Unexpected value for %o, %o at line %o", Arg0, Arg1, Arg2, Arg3)
This Printf macro expression evaluates to the following ASL operation:
Store (Concatenate (Concatenate (Concatenate (Concatenate
(Concatenate (Concatenate (Concatenate ("", Arg0),
": Unexpected value for "), Arg1), ", "), Arg2),
" at line "), Arg3), Debug)

Example
19.6. ASL Operator Reference 957Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.109 QWordIO (QWord IO Resource Descriptor Macro)
Syntax :
QWordIO ( ResourceUsage, IsMinFixed, IsMaxFixed, Decode, ISARanges,
˓→AddressGranularity, AddressMinimum, AddressMaximum,
AddressTranslation, RangeLength, ResourceSourceIndex, ResourceSource, DescriptorName,
˓→TranslationType, TranslationDensity)
Arguments
Fixed). If nothing is speciﬁed, then MinNotFixed is assumed. The 1-bit ﬁeld DescriptorName. _MIF is automatically
Fixed). If nothing is speciﬁed, then MaxNotFixed is assumed. The 1-bit ﬁeld DescriptorName. _MAF is automatically
Decode speciﬁes whether or not the device decodes the I/O range using positive (PosDecode) or subtractive (Sub-
Decode) decode. If nothing is speciﬁed, then PosDecode is assumed. The 1-bit ﬁeld DescriptorName. _DEC is
must be aligned. The 64-bit ﬁeld DescriptorName. _GRA is automatically created to refer to this portion of the
ﬁeld DescriptorName. _LEN is automatically created to refer to this portion of the resource descriptor.
argument is not speciﬁed, a zero value is assumed.
19.6. ASL Operator Reference 958Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
refer to this portion of the resource descriptor, where ‘1’ is TypeTranslation and ‘0’ is TypeStatic. See _TTP for more
tion. If nothing is speciﬁed, then DenseTranslation is assumed. The 1-bit ﬁeld DescriptorName. _TRS is automatically
See _TRS for more information.
The QWordIO macro evaluates to a buffer that contains a 64-bit I/O resource descriptor, which describes a range of I/O
addresses. The format of the 64-bit I/O resource descriptor can be found in Section 6.4.3.5.1. This macro is designed
19.6.110 QWordMemory (QWord Memory Resource Descriptor Macro)
Syntax :
QWordMemory (ResourceUsage, Decode, IsMinFixed, IsMaxFixed, Cacheable, ReadAndWrite,
˓→AddressGranularity, AddressMinimum,
AddressMaximum, AddressTranslation, RangeLength, ResourceSourceIndex, ResourceSource,
˓→DescriptorName, MemoryRangeType, TranslationType)
Arguments
then NonCacheable is assumed. The 2-bit ﬁeld DescriptorName. _MEM is automatically created to refer to this portion
19.6. ASL Operator Reference 959Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5

The QWordMemory macro evaluates to a buffer that contains a 64-bit memory resource descriptor, which describes a
range of memory addresses. The format of the 64-bit memory resource descriptor can be found in Table 6.45. This
19.6. ASL Operator Reference 960Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.111 QWordSpace (QWord Space Resource Descriptor Macro)
Syntax :
QWordSpace (ResourceType, ResourceUsage, Decode, IsMinFixed, IsMaxFixed,
˓→TypeSpecificFlags, AddressGranularity, AddressMinimum,
˓→DescriptorName) *
Arguments
0xFF.
19.6. ASL Operator Reference 961Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The QWordSpace macro evaluates to a buffer which contains a 64-bit Address Space resource descriptor, which
describes a range of addresses. The format of the 64-bit AddressSpace descriptor can be found in Table 6.45. This
19.6.112 RawDataBuffer (Raw Data Buffer)
Syntax :
RawDataBuffer (RDBufferSize) {ByteList} => RawDataBuffer
Arguments
Declares a RawDataBuffer of size RDBufferSize and optional initial value of ByteList.
The optional RDBufferSize parameter speciﬁes the size of the buffer and must be a word constant. The initial value
is speciﬁed in Initializer ByteList. If RDBufferSize is not speciﬁed, it defaults to the size of initializer. If the count is
too small to hold the value speciﬁed by initializer, the initializer size is used.

Syntax :
Arguments
Note that a RawDataBuffer is not encoded as a Buffer (Opcode, Package length bytes, etc), but rather contains only
the raw bytes speciﬁed.
19.6.113 RefOf (Create Object Reference)
Syntax :
RefOf (Object) => ObjectReference
Arguments
Object can be any object type (for example, a package, a device object, and so on).
Returns an object reference to Object. If the Object does not exist, the result of a RefOf operation is fatal. Use the
CondRefOf term in cases where the Object might not exist.
The primary purpose of RefOf() is to allow an object to be passed to a method as an argument to the method without
the object being evaluated at the time the method was loaded.
19.6. ASL Operator Reference 962Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.114 Register (Generic Register Resource Descriptor Macro)
Syntax :
Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress,
˓→AccessSize, DescriptorName)
Arguments
AddressSpaceKeyword speciﬁes the address space where the register exists. The register can be one of the following:
• I/O space (SystemIO)
• System Memory (SystemMemory)
• PCI conﬁguration space (PCI_Conﬁg)
• Embedded controller space (EmbeddedControl)
• SMBus (SMBus)
• CMOS (SystemCMOS)
• PCI Bar target (PciBarTarget)
• IPMI (IPMI)
• General purpose I/O (GeneralPurposeIO)
• Generic serial bus (GenericSerialBus)
• Platform Communications Channel (PCC)
• Fixed-feature hardware (FFixedHW)
The 8-bit ﬁeld DescriptorName . _ASI is automatically created in order to refer to this portion of the resource de-
scriptor. See the Address Space ID deﬁnition in Table: Generic Register Descriptor Deﬁnition for more information,
including a list of valid values and their meanings.
RegisterBitWidth evaluates to an 8-bit integer that speciﬁes the number of bits in the register. The 8-bit ﬁeld Descrip-
torName. _RBW is automatically created in order to refer to this portion of the resource descriptor. See the _RBW
deﬁnition in Table: Generic Register Descriptor Deﬁnition for more information.
RegisterBitOffset evaluates to an 8-bit integer that speciﬁes the offset in bits from the start of the register indicated by
RegisterAddress. The 8-bit ﬁeld DescriptorName. _RBO is automatically created in order to refer to this portion of the
resource descriptor. See the _RBO deﬁnition in Table: Generic Register Descriptor Deﬁnition for more information.
RegisterAddress evaluates to a 64-bit integer that speciﬁes the register address. The 64-bit ﬁeld DescriptorName.
_ADR is automatically created in order to refer to this portion of the resource descriptor. See the _ADR deﬁnition in
Table: Generic Register Descriptor Deﬁnition for more information.
AccessSize evaluates to an 8-bit integer that speciﬁes the size of data values used when accessing the address space as
follows:
0 - Undefined (legacy)
3 - DWord access
The 8-bit ﬁeld DescriptorName. _ASZ is automatically created in order to refer to this portion of the resource de-
scriptor. See the _ASZ deﬁnition in the Generic Register Resource Descriptor for more information. For backwards
compatibility, the AccesSize parameter is optional when invoking the Register macro. If the AccessSize parameter is
not supplied then the AccessSize ﬁeld will be set to zero. In this case, OSPM will assume the access size.
19.6. ASL Operator Reference 963Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The Register macro evaluates to a buffer that contains a generic register resource descriptor. For the format of the
buffer see Section 19.6.114. This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer
19.6.115 Release (Release a Mutex Synchronization Object)
Syntax :
Release (SyncObject)
Arguments
SynchObject must be a mutex synchronization object.
If the mutex object is owned by the current invocation, ownership for the Mutex is released once. It is fatal to release
ownership on a Mutex unless it is currently owned. A Mutex must be totally released before an invocation completes.
19.6.116 Reset (Reset an Event Synchronization Object)
Syntax :
Reset (SyncObject)
Arguments
SynchObject must be an Event synchronization object.
This operator is used to reset an event synchronization object to a non-signaled state. See also the Wait and Signal
function operator deﬁnitions.
19.6.117 ResourceTemplate (Resource To Buffer Conversion Macro)
Syntax :
ResourceTemplate() {ResourceMacroList} => Buffer
For a full deﬁnition of the ResourceTemplateTerm macro, see Section 19.3.3.
19.6. ASL Operator Reference 964Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.118 Return (Return from Method Execution)
Syntax :
Return
Return ()
Return (Arg)
Arguments
Arg is optional and can be any valid object or reference.
Returns control to the invoking control method, optionally returning a copy of the object named in Arg. If no Arg
object is speciﬁed, a Return(Zero) is generated by the ASL compiler.
Note: In the absence of an explicit Return () statement, the return value to the caller is undeﬁned.
19.6.119 Revision (Constant Revision Integer)
Syntax :
Revision => Integer
The Revision operator returns an Integer containing the current revision of the AML interpreter. Writes to this object
are not allowed.
19.6.120 Scope (Open Named Scope)
Syntax :
Scope (Location) {ObjectList}
Arguments
Opens and assigns a base namespace scope to a collection of objects. All object names deﬁned within the scope are
created relative to Location. Note that Location does not have to be below the surrounding scope, but can refer to
any location within the namespace. The Scope term itself does not create objects, but only locates objects within the
namespace; the actual objects are created by other ASL terms.
The object referred to by Location must already exist in the namespace and be one of the following object types that
has a namespace scope associated with it:
• A predeﬁned scope such as: (root), _SB, GPE, _PR, _TZ, etc.
• Device
• Thermal Zone
• Power Resource
19.6. ASL Operator Reference 965Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The Scope term alters the current namespace location to the existing Location. This causes the deﬁned objects within
TermList to be created relative to this new location in the namespace.
The object list is encoded as TermList, so that rather than describing a static object list, it is possible to describe a
dynamic object list according to the system settings. See “ Deﬁnition Block Loading .
Note: When creating secondary SSDTs, it is often required to use the Scope operator to change the namespace
location in order create objects within some part of the namespace that has been deﬁned by the main DSDT. Use
the External operator to declare the scope location so that the ASL compiler will not issue an error for an undeﬁned
Location.*
Examples
The following example ASL code uses the Scope operator and creates several objects:
Scope (\PCI0)
{
Name (X, 3)
Scope (\)
{
Method (RQ) {Return (0)}
}
Name (^Y, 4)
}
The created objects are placed in the ACPI namespace as shown:
\\PCI0.X
\\RQ
\\Y
The following example shows the use of External in conjunction with Scope within an SSDT:
{
{
}
}
19.6.121 ShiftLeft (Integer Shift Left)
Syntax :
ShiftLeft (Source, ShiftCount, Result) => Integer
Result = Source << shiftcount => Integer
Result <<= shiftcount => Integer
Arguments
Source andShiftCount are evaluated as Integers.
Source is shifted left with the least signiﬁcant bit zeroed ShiftCount times. The result is optionally stored into Result.
19.6. ASL Operator Reference 966Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.122 ShiftRight (Integer Shift Right)
Syntax :
ShiftRight (Source, ShiftCount, Result) => Integer
Result = Source >> ShiftCount => Integer
Result >>= ShiftCount => Integer
Arguments
Source is shifted right with the most signiﬁcant bit zeroed ShiftCount times. The result is optionally stored into Result.
19.6.123 Signal (Signal a Synchronization Event)
Syntax :
Signal (SyncObject)
Arguments
The Event object is signaled once, allowing one invocation to acquire the event.
19.6.124 SizeOf (Get Data Object Size)
Syntax :
SizeOf (ObjectName) => Integer
Arguments

Arguments
Syntax :
Arguments
Syntax :
Arguments
Syntax :
Arguments
ObjectName must be a buffer, string or package object.
Returns the size of a buffer, string, or package data object.
For a buffer, it returns the size in bytes of the data. For a string, it returns the size in bytes of the string, not counting
the trailing NULL. For a package, it returns the number of elements. For an object reference, the size of the referenced
object is returned. Other data types cause a fatal run-time error.
19.6. ASL Operator Reference 967Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.125 Sleep (Milliseconds Sleep)
Syntax :
Sleep (MilliSeconds)
Arguments
The Sleep term is used to implement long-term timing requirements. Execution is delayed for at least the required
number of milliseconds.
The implementation of Sleep is to round the request up to the closest sleep time supported by the OS and relinquish
19.6.126 SPISerialBusV2 (SPI Serial Bus Connection Resource Descriptor (Version
2) Macro)
Syntax :
SPISerialBusV2 (DeviceSelection, DeviceSelectionPolarity, WireMode, DataBitLength,
˓→SlaveMode, ConnectionSpeed,
ClockPolarity, ClockPhase, ResourceSource, ResourceSourceIndex, ResourceUsage,
˓→DescriptorName, Shared, VendorData)
Arguments
DeviceSelection is the device selection value. This value may refer to a chip-select line, GPIO line or other line
selection mechanism. _ADR is automatically created to refer to this portion of the resource descriptor.
DeviceSelectionPolarity is an optional argument and can be either PolarityHigh or PolarityLow to indicate that the
device is active. PolarityLow is the default. The bit ﬁeld _DPL is automatically created to refer to this portion of the
WireMode is an optional argument and can be either ThreeWireMode or FourWireMode. FourWireMode is the default.
The bit ﬁeld name _MOD is automatically created to refer to this portion of the resource descriptor.
DataBitLength is the size, in bits, of the smallest transfer unit for this connection. _LEN is automatically created to
ClockPolarity can be either ClockPolarityLow or ClockPolarityHigh. _POL is automatically created to refer to this
ClockPhase can be either ClockPhaseFirst or ClockPhaseSecond. _PHA is automatically created to refer to this portion
of the resource descriptor.
ResourceSource is a string which uniquely identiﬁes the SPI bus controller referred to by this descriptor. Resource-
ResourceUsage is an optional argument and is assumed to be ResourceConsumer for this revision.DescriptorName is
an optional argument that speciﬁes a name for an integer constant that will be created in the current scope that contains
19.6. ASL Operator Reference 968Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
the offset of this resource descriptor within the current resource template buffer. The predeﬁned descriptor ﬁeld names
may be appended to this name to access individual ﬁelds within the descriptor via the Buffer Field operators.
The SPISerialBusV2 macro evaluates to a buffer that contains an SPI Serial Bus Connection Resource Descriptor .
19.6.127 Stall (Stall for a Short Time)
Syntax :
Stall (MicroSeconds)
Arguments
The Stall term is used to implement short-term timing requirements. Execution is delayed for at least the required
number of microseconds.
The implementation of Stall is OS-speciﬁc, but must not relinquish control of the processor. Because of this, delays
longer than 100 microseconds must use Sleep instead of Stall.
19.6.128 StartDependentFn (Start Dependent Function Resource Descriptor
Macro)
Syntax :
StartDependentFn (CompatibilityPriority, PerformancePriority) {ResourceList}
Arguments
CompatibilityPriority indicates the relative compatibility of the conﬁguration speciﬁed by ResourceList relative to the
PC/AT. 0 = Good, 1 = Acceptable, 2 = Sub-optimal.
PerformancePriority indicates the relative performance of the conﬁguration speciﬁed by ResourceList relative to the
other conﬁgurations. 0 = Good, 1 = Acceptable, 2 = Sub-optimal.
ResourceList is a list of resources descriptors which must be selected together for this conﬁguration.
The StartDependentFn macro evaluates to a buffer that contains a start dependent function resource descriptor, which
describes a group of resources which must be selected together. Each subsequent StartDependentFn or StartDepen-
dentFnNoPri resource descriptor introduces a new choice of resources for conﬁguring the device, with the last choice
terminated with an EndDependentFn resource descriptor. The format of the start dependent function resource descrip-
tor can be found in Section 6.4.2.3. This macro generates the two-byte form of the resource descriptor, and is designed
19.6. ASL Operator Reference 969Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.129 StartDependentFnNoPri (Start Dependent Function Resource Descriptor
Macro)
Syntax :
StartDependentFnNoPri() {ResourceList}
The StartDependentFnNoPri macro evaluates to a buffer that contains a start dependent function resource descriptor,
which describes a group of resources which must be selected together. Each subsequent StartDependentFn or Start-
DependentFnNoPri resource descriptor introduces a new choice of resources for conﬁguring the device, with the last
choice terminated with an EndDependentFn resource descriptor. The format of the start dependent function resource
descriptor can be found in Section 6.4.2.3. This macro generates the one-byte form of the resource descriptor, and is
This is similar to StartDependentFn with both CompatibilityPriority and PerformancePriority set to 1, but is one byte
shorter.
19.6.130 Store (Store an Object)
Syntax :
Store (Source, Destination) => DataRefObject Destination = Source => DataRefObject
Arguments
This operation evaluates Source, converts it to the data type of Destination, and writes the result into Destination. For
information on automatic data-type conversion, see Section 19.3.5
Stores to OperationRegion Field data types may relinquish the processor depending on the address space.
All stores (of any type) to the constant Zero, constant One, or constant Ones object are not allowed. Stores to read-only
objects are fatal. The execution result of the operation depends on the type of Destination. For any type other than an
operation region ﬁeld, the execution result is the same as the data written to Destination. For operation region ﬁelds
with an AccessType of ByteAcc, WordAcc, DWordAcc, QWordAcc or AnyAcc, the execution result is the same as the
data written to Destination as in the normal case, but when the AccessType is BufferAcc, the operation region handler
may modify the data when it is written to the Destination so that the execution result contains modiﬁed data.
Example
The following example creates the name CNT that references an integer data object with the value 5 and then stores
CNT to Local0. After the Store operation, Local0 is an integer object with the value 5:
Name (CNT, 5)
Store (CNT, Local0)
19.6. ASL Operator Reference 970Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.131 Subtract (Integer Subtract)
Syntax :
Subtract ( Minuend, Subtrahend, Result ) => Integer
Result = Minuend - Subtrahend => Integer
Result -= Subtrahend => Integer
Arguments
Minuend and Subtrahend are evaluated as Integers.
Subtrahend is subtracted from Minuend, and the result is optionally stored into Result. Underﬂow conditions are

Example
Syntax :
Arguments
ignored and the result simply loses the most signiﬁcant bits.
19.6.132 Switch (Select Code To Execute Based On Expression)
Syntax :
Switch (Expression) {CaseTermList}
Arguments
Expression is an ASL expression that evaluates to an Integer, String or Buffer.
The Switch, Case and Default statements help simplify the creation of conditional and branching code. The Switch
statement transfers control to a statement within the enclosed body of executable ASL code
If the Case Value is an Integer, Buffer or String, then control passes to the statement that matches the value of Switch
(Expression). If the Case value is a Package, then control passes if any member of the package matches the Switch
(Value) The Switch CaseTermList can include any number of Case instances, but no two Case Values (or members of
a Value, if Value is a Package) within the same Switch statement can have the same value.
Execution of the statement body begins at the selected TermList and proceeds until the TermList end of body or until
a Break or Continue statement transfers control out of the body.
The Default statement is executed if no Case Value matches the value of Switch (expression). If the Default statement
is omitted, and no Case match is found, none of the statements in the Switch body are executed. There can be at most
one Default statement. The Default statement can appear anywhere in the body of the Switch statement.
A Case or Default term can only appear inside a Switch statement. Switch statements can be nested. (Compatibility
Note) The Switch, Case, and Default terms were ﬁrst introduced in ACPI 2.0. However, their implementation is
backward compatible with ACPI 1.0 AML interpreters.
Example
Use of the Switch statement usually looks something like this:
Switch (expression)
{
Case (value) {
Statements executed if Lequal (expression, value)
}
Case (Package () {value, value, value}) {
Statements executed if Lequal (expression, any value in package)
}
19.6. ASL Operator Reference 971Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Default {
Statements executed if expression does not equal any case constant-expression
}
}
Note: Compiler Note: The following example demonstrates how the Switch statement should be translated into
ACPI 1.0-compatible AML:
Switch (Add (ABCD( ),1)
{
Case (1) {
}
Case (Package () {4,5,6}) {
}
Default {
}
}
is translated as:
Name (_T_I, 0) // Create Integer temporary variable for result
While (One)
{
Store (Add (ABCD (), 1), \_T_I)
If (LEqual (_T_I, 1)) {
}
Else {
If (LNotEqual (Match (Package () {4, 5, 6}, MEQ, \_T_I, MTR, 0, 0), Ones)) {
}
Else {
}
Break
}
The While (One) is emitted to enable the use of Break and Continue within the Switch statement. Temporary names
emitted by the ASL compiler should appear at the top level of the method, since the Switch statement could appear
within a loop and thus attempt to create the name more than once.
Note: If the ASL compiler is unable to determine the type of the expression, then it will generate a warning and assume
a type of Integer. The warning will indicate that the code should use one of the type conversion operators (Such as
ToInteger, ToBuffer, ToDecimalString or ToHexString). Caution: Some of these operators are deﬁned starting with
ACPI 2.0 and as such may not be supported by ACPI 1.0b compatible interpreters.
Switch (ABCD ()) // Cannot determine the type because methods can return anything.
{
...case statements...
}
19.6. ASL Operator Reference 972Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
will generate a warning and the following code:
Name (_T_I, 0)
Store (ABCD (), \_T_I)
To remove the warning, the code should be:
Switch (ToInteger (ABCD ()))
{
}
19.6.133 ThermalZone (Declare Thermal Zone)
Syntax :
ThermalZone (ThermalZoneName) {TermList}
Arguments
Declares a Thermal Zone object named ThermalZoneName. ThermalZone opens a name scope.
Each use of a ThermalZone term declares one thermal zone in the system. Each thermal zone in a system is required
to have a unique ThermalZoneName.
A thermal zone may be declared in the namespace anywhere within the \_SB scope. For compatibility with operating
systems implementing ACPI 1.0, a thermal zone may also be declared under the \_TZ scope. An ACPI-compatible
namespace may deﬁne Thermal Zone objects in either the \_SB or \_TZ scope but not both.
For example ASL code that uses a ThermalZone statement, see Section 11
The thermal object list is encoded as TermList, so that rather than describing a static thermal object list, it is possible
to describe a dynamic thermal object list according to the system settings. See “ Deﬁnition Block Loading ”.
19.6.134 Timer (Get 64-Bit Timer Value)
Syntax :
Timer => Integer
The timer opcode returns a monotonically increasing value that can be used by ACPI methods to measure time passing,
this enables speed optimization by allowing AML code to mark the passage of time independent of OS ACPI interpreter
The Sleep opcode can only indicate waiting for longer than the time speciﬁed.
The value resulting from this opcode is 64 bits. It is monotonically increasing, but it is not guaranteed that every result
will be unique, i.e. two subsequent instructions may return the same value. The only guarantee is that each subsequent
evaluation will be greater-than or equal to the previous ones.
The period of this timer is 100 nanoseconds. While the underlying hardware may not support this granularity, the
interpreter will do the conversion from the actual timer hardware frequency into 100 nanosecond units.
Users of this opcode should realize that a value returned only represents the time at which the opcode itself executed.
There is no guarantee that the next opcode in the instruction stream will execute in any particular time bound.
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The OSPM can implement this using the ACPI Timer and keep track of overrun. Other implementations are possible.
This provides abstraction away from chipset differences
Note: Compatibility Note New for ACPI 3.0
19.6.135 ToBCD (Convert Integer to BCD)
Syntax :
ToBCD (Value, Result) => Integer
Arguments
Value is evaluated as an integer
The ToBCD operator is used to convert Value from a numeric (Integer) format to a BCD format and optionally store
the numeric value into Result.
19.6.136 ToBuffer (Convert Data to Buffer)
Syntax :
ToBuffer (Data, Result) => Buffer
Arguments
Data must be an Integer, String, or Buffer data type.
Data is converted to buffer type and the result is optionally stored into Result. If Data is an integer, it is converted
into n bytes of buffer (where n is 4 if the deﬁnition block has deﬁned integers as 32 bits or 8 if the deﬁnition block
has deﬁned integers as 64 bits as indicated by the Deﬁnition Block table header’s Revision ﬁeld), taking the least
signiﬁcant byte of integer as the ﬁrst byte of buffer. If Data is a buffer, no conversion is performed. If Data is a string,
each ASCII string character is copied to one buffer byte, including the string null terminator. A null (zero-length)
string will be converted to a zero-length buffer.
19.6.137 ToDecimalString (Convert Data to Decimal String)
Syntax :
ToDecimalString (Data, Result) => String
Arguments
Data is converted to a decimal string, and the result is optionally stored into Result. If Data is already a string, no
action is performed. If Data is a buffer, it is converted to a string of decimal values separated by commas. (Each byte
of the buffer is converted to a single decimal value.) A zero-length buffer will be converted to a null (zero-length)
string.
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19.6.138 ToHexString (Convert Data to Hexadecimal String)
Syntax :
ToHexString (Data, Result) => String
Arguments
Data is converted to a hexadecimal string, and the result is optionally stored into Result. If Data is already a string,
no action is performed. If Data is a buffer, it is converted to a string of hexadecimal values separated by commas. A
zero-length buffer will be converted to a null (zero-length) string.
19.6.139 ToInteger (Convert Data to Integer)
Syntax :
ToInteger (Data, Result) => Integer
Arguments
Data is converted to integer type and the result is optionally stored into Result. If Data is a string, it must be either a
decimal or hexadecimal numeric string (in other words, preﬁxed by “0x”) and the value must not exceed the maximum

Syntax :
Arguments
Syntax :
Arguments
of an integer value. If the value is exceeding the maximum, the result of the conversion is unpredictable. A null
(zero-length) string is illegal. If Data is a Buffer, the ﬁrst 8 bytes of the buffer are converted to an integer, taking the
ﬁrst byte as the least signiﬁcant byte of the integer. A zero-length buffer is illegal. If Data is an integer, no action is
19.6.140 ToPLD (Creates a _PLD Buffer Object)
Syntax :
ToPLD (PLDKeywordList) => \_PLD Buffer Object
Arguments
PLDKeywordList is a list of PLDKeyword types that describe elements of a Physical Layer Description (_PLD) buffer
that can be assigned values. The table below shows the available PLDKeyword types and their assignable types. Refer
to the _PLD section for a description of the _PLD method object.
Table 19.39: PLD Keywords and Assignment Types
PLDKeyword Assignment Type
PLD_Revision Integer
PLD_IgnoreColor Integer
PLD_Red Integer
PLD_Green Integer
PLD_Blue Integer
PLD_Width Integer
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Table 19.39 – continued from previous page
PLD_Height Integer
PLD_UserVisible Integer
PLD_Dock Integer
PLD_Lid Integer
PLD_Panel Integer or String
PLD_VerticalPosition Integer or String
PLD_HorizontalPosition Integer or String
PLD_Shape Integer or String
PLD_GroupOrientation Integer
PLD_GroupToken Integer
PLD_GroupPosition Integer
PLD_Bay Integer
PLD_Ejectable Integer
PLD_EjectRequired Integer
PLD_CabinetNumber Integer
PLD_CardCageNumber Integer
PLD_Reference Integer
PLD_Rotation Integer
PLD_Order Integer
PLD_VeriticalOffset Integer
PLD_HorizontalOffset Integer
A subset of PLDKeyword types can be assigned string values for improved readability. Those types and their
assignable values are shown in the table below.
Table 19.40: PLD Keywords and assignable String Values
PLDKeyword Assignable String Values
PLD_Panel “TOP”, “BOTTOM”,”LEFT”, “RIGHT”,”FRONT”,”BACK”,”UNKNOWN”
PLD_VerticalPosition “UPPER”,”CENTER”,”LOWER”
PLD_HorizontalPosition “LEFT”,”CENTER”,”RIGHT”
PLD_Shape “ROUND”,”OV AL”,”SQUARE”, “VERTICALRECTANGLE”, “HORIZONTAL-
RECTANGLE”, “VERTICALTRAPEZOID”, “HORIZONTALTRAPEZOID”, “UN-
KNOWN”
The ToPLD macro converts a list of PLDKeyword types into a _PLD buffer object.
Example
The following ASL shows an example using ToPLDto construct a _PLD buffer/package object:
Name (_PLD, Package (0x01) // \_PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x37,
PLD_Green = 0x44,
PLD_Blue = 0xFF,
PLD_Width = 0x4,
PLD_Height = 0x19,
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PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x1,
PLD_Panel = "TOP",
PLD_Shape = "VERTICALRECTANGLE",
PLD_GroupOrientation = 0x1,
PLD_GroupToken = 0xA,
PLD_GroupPosition = 0x21,
PLD_Bay = 0x1,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x1,
PLD_CabinetNumber = 0x1E,
PLD_CardCageNumber = 0x17,
PLD_Reference = 0x0,
PLD_Rotation = 0x7,
PLD_Order = 0x3,
PLD_VerticalOffset = 0x141,
PLD_HorizontalOffset = 0x2C
)
}
)
19.6.141 ToString (Convert Buffer To String)
Syntax :
ToString (Source, Length, *Result) => String
Arguments
Source is evaluated as a buffer. Length is evaluated as an integer data type.
Starting with the ﬁrst byte, the contents of the buffer are copied into the string until the number of characters speciﬁed
by Length is reached or a null (0) character is found. If Length is not speciﬁed or is Ones, then the contents of the
buffer are copied until a null (0) character is found. If the source buffer has a length of zero, a zero length (null
terminator only) string will be created. The result is copied into the Result.
19.6.142 ToUUID (Convert String to UUID Macro)
Syntax :
ToUUID (AsciiString) => Buffer
Arguments
AsciiString is evaluated as a String data type.
This macro will convert an ASCII string to a 128-bit buffer. The string must have the following format:
19.6. ASL Operator Reference 977Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
aabbccdd-eeff-gghh-iijj-kkllmmnnoopp
where aa - pp are one byte hexadecimal numbers, made up of hexadecimal digits. The resulting buffer has the format
shown in the following table:
Table 19.41: UUID Buffer Format
String Offset In Buffer
aa 3
bb 2
cc 1
dd 0
ee 5
ff 4
gg 7
hh 6
ii 8
jj 9
kk 10
ll 11
mm 12
nn 13
oo 14
pp 15
19.6.143 UARTSerialBusV2 (UART Serial Bus Connection Resource Descriptor Ver-
sion 2 Macro)
Syntax :
UARTSerialBusV2 (InitialBaudRate, BitsPerByte, StopBits, LinesInUse, IsBigEndian,
˓→Parity, FlowControl, ReceiveBufferSize,
TransmitBufferSize, ResourceSource, ResourceSourceIndex, ResourceUsage,
Arguments
InitialBaudRate evaluates to a 32-bit integer that speciﬁes the default or initial connection speed in bytes per second
that the device supports. The bit ﬁeld _SPE is automatically created to refer to this portion of the resource descriptor.
BitsPerByte is an optional argument that speciﬁes whether ﬁve bits (DataBitsFive), six bits (DataBitsSix), seven bits
(DataBitsSeven), eight bits (DataBitsEight) or nine bits (DataBitsNine) contain data during transfer of a single packet
or character. DataBitsEight is the default. The bit ﬁeld DescriptorName._LEN is automatically created to refer to this
StopBits is an optional argument that speciﬁes whether there are two bits (StopBitsTwo), one and a half bits (Stop-
BitsOnePlusHalf), one bit (StopBitsOne) or no bits (StopBitsZero) used to signal the end of a packet or character.
StopBitsOne is the default. The bit ﬁeld _STB is automatically created to refer to this portion of the resource descrip-
tor.
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LinesInUse evaluates to an integer representing 8 1-bit ﬂags representing the presence (‘1’) or absence (‘0’) of a
particular line. The bit ﬁeld _LIN is automatically created to refer to this portion of the resource descriptor.
Table 19.42: UART Serial Bus Connection Resource Descriptor - Ver-
sion 2 Macro
Bit Mask UART Line
Bit 7 (0x80) Request To Send (RTS)
Bit 6 (0x40) Clear To Send (CTS)
Bit 5 (0x20) Data Terminal Ready (DTR)
Bit 4 (0x10) Data Set Ready (DSR)
Bit 3 (0x08) Ring Indicator (RI)
Bit 2 (0x04) Data Carrier Detect (DTD)
Bit 1 (0x02) Reserved. Must be 0.
Bit 0 (0x01) Reserved. Must be 0.
IsBigEndian is an optional argument that speciﬁes whether the device is expecting big endian (BigEndian) or little
endian (LittleEndian) data formats. LittleEndian is the default. The bit ﬁeld _END is automatically created to refer to
Parity is an optional argument that speciﬁes whether the type of parity bits included after the data in a packet are to be
interpreted as space parity (ParityTypeSpace), mark parity (ParityTypeMark), odd parity (ParityTypeOdd), even parity
(ParityTypeEven) or no parity (ParityTypeNone). ParityTypeNone is the default. The bit ﬁeld PAR is automatically
FlowControl is an optional argument that speciﬁes whether there is hardware-based ﬂow control (FlowControlHard-
ware), software-based ﬂow control (FlowControlXON) or no ﬂow control (FlowControlNone) used when communi-
cating with the device. FlowControlNone is the default. The bit ﬁeld_FLC is automatically created to refer to this
ReceiveBufferSize evaluates to a 16-bit integer that speciﬁes the upper limit in bytes of the receive buffer that can be
optimally utilized while communicating with this device. The bit ﬁeld_RXL is automatically created to refer to this
TransmitBufferSize evaluates to a 16-bit integer that speciﬁes the upper limit in bytes of the transmit buffer that can be
optimally utilized while communicating with this device. The bit ﬁeld _TXL is automatically created to refer to this
ResourceSource is a string which uniquely identiﬁes the UART bus controller referred to by this descriptor. Resource-

The UARTSerialBusV2 macro evaluates to a buffer that contains a UART Serial Bus Connection Resource Descriptor
- Version 2 Macro . This macro is designed to be used inside of a ResourceTemplate (Resource To Buffer Conversion
19.6. ASL Operator Reference 979Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Macro) .
19.6.144 Unicode (String To Unicode Conversion Macro)
Syntax :
Unicode (String) => Buffer
Arguments
This macro will convert a string to a Unicode (UTF-16) string contained in a buffer. The format of the Unicode string
is 16 bits per character, with a 16-bit null terminator.
19.6.145 VendorLong (Long Vendor Resource Descriptor)
Syntax :
VendorLong (DescriptorName) {VendorByteList}
Arguments
VendorByteList evaluates to a comma-separated list of 8-bit integer constants, where each byte is added verbatim to
the body of the VendorLong resource descriptor. A maximum of n bytes can be speciﬁed. UUID and UUID speciﬁc
descriptor subtype are part of the VendorByteList.
The VendorLong macro evaluates to a buffer that contains a vendor-deﬁned resource descriptor. The long form of
the vendor-deﬁned resource descriptor can be found in Section 6.4.3.2. This macro is designed to be used inside of a
This is similar to VendorShort , except that the number of allowed bytes in VendorByteList is 65,533 (instead of 7).
19.6.146 VendorShort (Short Vendor Resource Descriptor)
Syntax :
VendorShort (DescriptorName) {VendorByteList}
Arguments
The VendorShort macro evaluates to a buffer that contains a vendor-deﬁned resource descriptor. The short form of
the vendor-deﬁned resource descriptor can be found in Section 6.4.2.8. This macro is designed to be used inside of a
This is similar to VendorLong , except that the number of allowed bytes in VendorByteList is 7 (instead of 65,533).
19.6. ASL Operator Reference 980Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.147 Wait (Wait for a Synchronization Event)
Syntax :
Wait (SyncObject, TimeoutValue) => Boolean
Arguments
SynchObject must be an event synchronization object. TimeoutValue is evaluated as an Integer. The calling method
blocks while waiting for the event to be signaled.
The pending signal count is decremented. If there is no pending signal count, the processor is relinquished until a
signal count is posted to the Event or until at least TimeoutValue milliseconds have elapsed.
This operation returns a non-zero value if a timeout occurred and a signal was not acquired. A TimeoutValue of
0xFFFF (or greater) indicates that there is no time out and the operation will wait indeﬁnitely.
19.6.148 While (Conditional Loop)
Syntax :
While (Predicate) {TermList}
Arguments
Predicate is evaluated as an integer.
If the Predicate is non-zero, the list of terms in TermList is executed. The operation repeats until the Predicate evaluates
to zero.
named objects within a While loop must be avoided. A fatal error will be generated on the second iteration of the loop,
19.6.149 WordBusNumber (Word Bus Number Resource Descriptor Macro)
Syntax :
WordBusNumber (ResourceUsage, IsMinFixed, IsMaxFixed, Decode, AddressGranularity,
˓→AddressMinimum, AddressMaximum,
AddressTranslation, RangeLength, ResourceSourceIndex, ResourceSource, DescriptorName)
Arguments
ResourceUsage speciﬁes whether the bus range is consumed by this device (ResourceConsumer) or passed on to child
IsMinFixed speciﬁes whether the minimum address of this bus number range is ﬁxed (MinFixed) or can be changed
IsMaxFixed speciﬁes whether the maximum address of this bus number range is ﬁxed (MaxFixed) or can be changed
19.6. ASL Operator Reference 981Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Decode speciﬁes whether or not the device decodes the bus number range using positive (PosDecode) or subtractive
AddressGranularity evaluates to a 16-bit integer that speciﬁes the power-of-two boundary (- 1) on which the bus
number range must be aligned. The 16-bit ﬁeld DescriptorName. _GRA is automatically created to refer to this
AddressMinimum evaluates to a 16-bit integer that speciﬁes the lowest possible bus number for the bus number range.
translate addresses, this is the address on the secondary bus. The 16-bit ﬁeld DescriptorName._MIN is automatically
AddressMaximum evaluates to a 16-bit integer that speciﬁes the highest possible bus number for the bus number range.
translate addresses, this is the address on the secondary bus. The 16-bit ﬁeld DescriptorName._MAX is automatically
AddressTranslation evaluates to a 16-bit integer that speciﬁes the offset to be added to a secondary bus bus number
which results in the corresponding primary bus bus number. For all non-bridge devices or bridges which do not
perform translation, this must be ‘0’. The 16-bit ﬁeld DescriptorName._TRA is automatically created to refer to this
RangeLength evaluates to a 16-bit integer that speciﬁes the total number of bus numbers decoded in the bus num-
ber range. The 16-bit ﬁeld DescriptorName. _LEN is automatically created to refer to this portion of the resource
The WordBusNumber macro evaluates to a buffer that contains a 16-bit bus-number resource descriptor. The format
of the 16-bit bus number resource descriptor can be found in Section 6.4.3.5.3. This macro is designed to be used
19.6.150 WordIO (Word IO Resource Descriptor Macro)
Syntax :
WordIO (ResourceUsage, IsMinFixed, IsMaxFixed, Decode, ISARanges, AddressGranularity,

Syntax :
Arguments
19.6. ASL Operator Reference 982Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
AddressGranularity evaluates to a 16-bit integer that speciﬁes the power-of-two boundary (- 1) on which the I/O range
must be aligned. The 16-bit ﬁeld DescriptorName. _GRA is automatically created to refer to this portion of the
AddressMinimum evaluates to a 16-bit integer that speciﬁes the lowest possible base address of the I/O range. The
AddressMaximum evaluates to a 16-bit integer that speciﬁes the highest possible base address of the I/O range. The
AddressTranslation evaluates to a 16-bit integer that speciﬁes the offset to be added to a secondary bus I/O address
RangeLength evaluates to a 16-bit integer that speciﬁes the total number of bytes decoded in the I/O range. The 16-bit
19.6. ASL Operator Reference 983Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The WordIO macro evaluates to a buffer that contains a 16-bit I/O range resource descriptor. The format of the 16-
bit I/O range resource descriptor can be found in Section 6.4.3.5.3. This macro is designed to be used inside of a
19.6.151 WordSpace (Word Space Resource Descriptor Macro)
Syntax :
WordSpace (ResourceType, ResourceUsage, Decode, IsMinFixed, IsMaxFixed,
Arguments
0xFF.

19.6. ASL Operator Reference 984Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The WordSpace macro evaluates to a buffer that contains a 16-bit Address Space resource descriptor. The format of
the 16-bit Address Space resource descriptor can be found in Section 6.4.3.5.3. This macro is designed to be used
19.6.152 XOr (Integer Bitwise Xor)
Syntax :
XOr ( Source1, Source2, Result ) => Integer
Result = Source1 ^ Source2 => Integer
Result ^= Source => Integer
Arguments
Source1 and Source2 are evaluated as Integers.
A bitwise XOR is performed and the result is optionally stored into Result.
19.6.153 Zero (Constant Zero Integer)
Syntax :
Zero => Integer
The Zero operator returns an Integer with the value 0. Writes to this object are not allowed. The use of this operator
19.6. ASL Operator Reference 985Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
19.6.154 ClockInput (Clock Input Resource Descriptor Macro)
Syntax :
ClockInput (FrequencyNumerator, FrequencyDivisor, Scale, FixedMode, ResourceSource,
˓→ResourceSourceIndex)
Arguments
FrequencyNumerator is an integer argument describing the numerator of the input frequency of the clock. This argu-
ment is required. If FixedMode isVariable this value describes the initial/default input clock frequency. The unit type
for the value in this argument is conveyed in Scale . The bit ﬁeld name _SPE is automatically created to refer to this
FrequencyDivisor is an integer argument describing the denominator of the input frequency of the clock. If FixedMode
isVariable this value describes the initial/default input clock frequency.
Scale is one of Hz | kHz | MHz. This required argument conveys the unit of the frequency value determined by
(FrequencyNumerator /FrequencyDivisor ).
FixedMode is one of Fixed | Variable. Fixed denotes that the clock frequency cannot be adjusted. Variable denotes
that the clock frequency is variable, and is controllable through the Device referenced by ResourceSource .
ResourceSource is a string which uniquely identiﬁes the Device which is the source of the clock signal described by
this Resource. If FixedMode isVariable , this argument is required. ResourceSource can be a fully-qualiﬁed name, a
relative name or a name segment that utilizes the namespace search rules.
ResourceSourceIndex is an integer specifying the clock output of the Device speciﬁed by ResourceSource . Clock
output index values begin at 0. If FixedMode isVariable , this argument is required. If ResourceSource is not supplied,
this argument is ignored. If the clock source referenced by ResourceSource has only one clock output, this argument
shall be 0.
Examples
The following examples show the use of the ClockInput macro for two different cases.
Case 1: Simple clock input descriptor, with a ﬁxed frequency of 33 1/3 MHz and no Device shown as a clock source.
ClockInput (100, 3, MHz, Fixed,,)
Case 2: Clock input descriptor referencing a variable clock input of 19.2 kHz, with a source device and index.
ClockInput (19200, 1, Hz, Variable, “\\_SB.PCI0.CLK4”, 3)
19.6. ASL Operator Reference 986CHAPTER
TWENTY
ACPI MACHINE LANGUAGE (AML) SPECIFICATION
This chapter formally deﬁnes the ACPI Machine Language (AML), which is the virtual machine language for ACPI
control methods on an ACPI-compatible OS. ACPI control methods can be written directly in AML, but people usually
write them in ASL and then compile to AML.
AML is the language processed by the ACPI AML interpreter. It is primarily a declarative language. It’s best not to
think of it as a stream of code, but rather as a set of declarations that the ACPI AML interpreter will compile into
the ACPI Namespace at deﬁnition block load time. For example, notice that DefByte allocates an anonymous integer
variable with a byte-size initial value in ACPI namespace, and passes in an initial value. The byte in the AML stream
that deﬁnes the initial value is not the address of the variable’s storage location.
An OEM or platform ﬁrmware vendor needs to write ASL and be able to single-step AML for debugging. (Debug-
gers and other ACPI control method language tools are expected to be AML-level tools, not source-level tools.) An
ASL translator implementer must understand how to read ASL and generate AML. An AML interpreter author must
understand how to execute AML.
AML and ASL are different languages, though they are closely related.
All ACPI-compatible operating systems must support AML. A given user can deﬁne some arbitrary source language
(to replace ASL) and write a tool to translate it to AML. However, the ACPI group will support a single translator for
a single language, ASL.
20.1 Notation Conventions
The notation conventions in the table below help the reader to interpret the AML formal grammar.
Table 20.1: AML Grammar Notation Conventions
0xdd Refers to a byte value ex-
pressed as 2 hexadecimal
digits.0x21
Number in bold. Denotes the encoding of
the AML term.
Term => Evaluated Type Shows the resulting type
of the evaluation of Term.
Single quotes (‘ ‘) Indicate constant charac-
ters.‘A’ => 0x41
Term := Term Term . . . The term to the left of :=
can be expanded into the
sequence of terms on the
right.aterm := bterm cterm means that aterm can be expanded
into the two-term sequence of bterm followed by cterm.
987Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 20.1 – continued from previous page
Term Term Term . . . Terms separated from
each other by spaces form
an ordered list.
aterm := bterm | [cterm dterm] means the following
constructs are possible:
bterm cterm dterm
aterm := [bterm | cterm] dterm means the following
bterm dterm cterm dterm
Dash character ( - ) Indicates a range. 1-9 means a single digit in the range 1 to 9 inclusive.
Parenthesized term fol-
lowing another term.The parenthesized term is
the repeat count of the
previous term.aterm(3) means aterm aterm aterm. bterm(n) means n
number of bterms.
20.2 AML Grammar Deﬁnition
This section deﬁnes the byte values that make up an AML byte stream.
The AML encoding can be categorized into the following groups:
• Table and Table Header encoding
• Name objects encoding
• Data objects encoding
• Package length encoding
• Term objects encoding
• Miscellaneous objects encoding
20.2.1 Table and Table Header Encoding
AMLCode :=DefBlockHeader TermList
DefBlockHeader := TableSignature TableLength SpecCompliance CheckSum OemID OemTableID
OemRevision CreatorID CreatorRevision
TableSignature := DWordData // As deﬁned in section 5.2.3.
TableLength := DWordData // Length of the table in bytes including the block header.
SpecCompliance := ByteData // The revision of the structure.
CheckSum := ByteData // Byte checksum of the entire table.
OemID :=
ByteData(6) // OEM ID of up to 6 characters. If the OEM ID is shorter than 6 characters,
it can be terminated with a NULL character.
OemTableID :=
20.2. AML Grammar Deﬁnition 988Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ByteData(8) // OEM Table ID of up to 8 characters. If the OEM Table ID is shorter than 8
characters,
OemRevision := DWordData // OEM Table Revision.
CreatorID := DWordData // Vendor ID of the ASL compiler.

OemID :=
CreatorRevision := DWordData // Revision of the ASL compiler.
20.2.2 Name Objects Encoding
LeadNameChar := ‘A’-‘Z’ | ‘_’
DigitChar := ‘0’ - ‘9’
‘A’-‘Z’ := 0x41 - 0x5A
‘_’ := 0x5F
‘0’-‘9’ := 0x30 - 0x39
‘' := 0x5C
‘^’ := 0x5E
NameSeg :=
<leadnamechar namechar namechar namechar >
// Notice that NameSegs shorter than 4 characters are ﬁlled with trailing underscores (‘_’s).
NameString := < rootchar namepath > | <preﬁxpath namepath >
PreﬁxPath := Nothing | <’^’ preﬁxpath >
NamePath := NameSeg | DualNamePath |MultiNamePath |NullName
DualNamePath := DualNamePreﬁx NameSeg NameSeg
DualNamePreﬁx := 0x2E
MultiNamePath := MultiNamePreﬁx SegCount NameSeg(SegCount)
MultiNamePreﬁx := 0x2F
SegCount := ByteData
// SegCount can be from 1 to 255. For example: MultiNamePreﬁx(35) is
// encoded as 0x2f 0x23 and followed by 35 NameSegs. So, the total
// encoding length will be 1 + 1 + 35*4 = 142. Notice that:
// DualNamePreﬁx NameSeg NameSeg has a smaller encoding than the
// encoding of: MultiNamePreﬁx(2) NameSeg NameSeg
SimpleName := NameString |ArgObj |LocalObj
SuperName := SimpleName |DebugObj |ReferenceTypeOpcode
NullName := 0x00
Target := SuperName |NullName
20.2. AML Grammar Deﬁnition 989Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
20.2.3 Data Objects Encoding
ComputationalData := ByteConst |WordConst |DWordConst |QWordConst |String |ConstObj |Revi-
sionOp |DefBuffer
DataObject := ComputationalData |DefPackage |DefVarPackage
ByteConst := BytePreﬁx ByteData
BytePreﬁx := 0x0A
WordConst := WordPreﬁx WordData
WordPreﬁx := 0x0B
DWordConst := DWordPreﬁx DWordData
DWordPreﬁx := 0x0C
QWordConst := QWordPreﬁx QWordData
QWordPreﬁx := 0x0E
String := StringPreﬁx AsciiCharList NullChar
StringPreﬁx := 0x0D
ConstObj := ZeroOp |OneOp |OnesOp
ByteList := Nothing | < bytedata bytelist >
ByteData := 0x00 - 0xFF
WordData := ByteData[0:7] ByteData[8:15] // 0x0000-0xFFFF
DWordData := WordData[0:15] WordData[16:31] // 0x00000000-0xFFFFFFFF
QWordData := DWordData[0:31] DWordData[32:63] // 0x0000000000000000-
0xFFFFFFFFFFFFFFFF
AsciiCharList := Nothing | < asciichar asciicharlist >
AsciiChar := 0x01 - 0x7F
ZeroOp := 0x00
OneOp := 0x01
OnesOp := 0xFF
RevisionOp := ExtOpPreﬁx 0x30
ExtOpPreﬁx := 0x5B
20.2. AML Grammar Deﬁnition 990Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
20.2.4 Package Length Encoding
PkgLength :=
PkgLeadByte |
<pkgleadbyte bytedata > |
<pkgleadbyte bytedata bytedata> |
<pkgleadbyte bytedata bytedata bytedata>
PkgLeadByte :=
<bit 7-6: bytedata count that follows (0-3)>
<bit 5-4: only used if pkglength < 63>
<bit 3-0: least signiﬁcant package length nybble>
Note: The high 2 bits of the ﬁrst byte reveal how many follow bytes are in the PkgLength. If the PkgLength has only
one byte, bit 0 through 5 are used to encode the package length (in other words, values 0-63). If the package length
value is more than 63, more than one byte must be used for the encoding in which case bit 4 and 5 of the PkgLeadByte
are reserved and must be zero. If the multiple bytes encoding is used, bits 0-3 of the PkgLeadByte become the least
signiﬁcant 4 bits of the resulting package length value. The next ByteData will become the next least signiﬁcant 8 bits
of the resulting value and so on, up to 3 ByteData bytes. Thus, the maximum package length is 2*28.
20.2.5 Term Objects Encoding
Object := NameSpaceModiﬁerObj |NamedObj
TermObj := Object |StatementOpcode |ExpressionOpcode
TermList := Nothing | < termobj termlist >
TermArg := ExpressionOpcode |DataObject |ArgObj |LocalObj
MethodInvocation := NameString TermArgList
TermArgList := Nothing | < termarg termarglist >
20.2.5.1 Namespace Modiﬁer Objects Encoding
NameSpaceModiﬁerObj := DefAlias |DefName |DefScope
DefAlias := AliasOp NameString NameString
AliasOp := 0x06
DefName := NameOp NameString DataRefObject
NameOp := 0x08
DefScope := ScopeOp PkgLength NameString TermList
ScopeOp := 0x10
20.2. AML Grammar Deﬁnition 991Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
20.2.5.2 Named Objects Encoding
NamedObj := DefBankField |DefCreateBitField |DefCreateByteField |DefCreateDWordField |DefCre-
ateField |DefCreateQWordField |DefCreateWordField |DefDataRegion |DefExternal |DefOpRe-
gion |DefPowerRes |DefThermalZone
DefBankField := BankFieldOp PkgLength NameString NameString BankValue FieldFlags FieldList
BankFieldOp := ExtOpPreﬁx 0x87
BankValue := TermArg => Integer
FieldFlags :=
ByteData // bit 0-3: AccessType
// 0 AnyAcc
// 1 ByteAcc
// 2 WordAcc
// 3 DWordAcc
// 4 QWordAcc
// 5 BufferAcc
// 6 Reserved
// 7-15 Reserved
// bit 4: LockRule
// 0 NoLock
// 1 Lock
// bit 5-6: UpdateRule
// 0 Preserve
// 1 WriteAsOnes
// 2 WriteAsZeros
// bit 7: Reserved (must be 0)
FieldList := Nothing | < ﬁeldelement ﬁeldlist >
NamedField := NameSeg PkgLength
ReservedField := 0x00 PkgLength
AccessField := 0x01 AccessType AccessAttrib
AccessType :=
ByteData // Bits 0:3 - Same as AccessType bits of FieldFlags.
// Bits 4:5 - Reserved
// Bits 7:6 - 0 = AccessAttrib = Normal Access Attributes
// 1 = AccessAttrib = AttribBytes (x)
// 2 = AccessAttrib = AttribRawBytes (x)
// 3 = AccessAttrib = AttribRawProcessBytes (x)
//
// x’ is encoded as bits 0:7 of the AccessAttrib byte.
AccessAttrib :=
ByteData // If AccessType is BufferAcc for the SMB or
// GPIO OpRegions, AccessAttrib can be one of
// the following values:
20.2. AML Grammar Deﬁnition 992Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
// 0x02 AttribQuick
// 0x04 AttribSendReceive
// 0x06 AttribByte
// 0x08 AttribWord
// 0x0A AttribBlock
// 0x0C Attrib ProcessCall
// 0x0D AttribBlockProcessCall
ConnectField := <0x02 NameString > | <0x02 BufferData
DefCreateBitField := CreateBitFieldOp SourceBuff BitIndex NameString
CreateBitFieldOp := 0x8D
SourceBuff := TermArg =>Buffer
BitIndex := TermArg => Integer
DefCreateByteField := CreateByteFieldOp SourceBuff ByteIndex NameString
CreateByteFieldOp := 0x8C
ByteIndex := TermArg => Integer
DefCreateDWordField := CreateDWordFieldOp SourceBuff ByteIndex NameString
CreateDWordFieldOp := 0x8A
DefCreateField := CreateFieldOp SourceBuff BitIndex NumBits NameString
CreateFieldOp := ExtOpPreﬁx 0x13
NumBits := TermArg => Integer
DefCreateQWordField := CreateQWordFieldOp SourceBuff ByteIndex NameString
CreateQWordFieldOp := 0x8F
DefCreateWordField := CreateWordFieldOp SourceBuff ByteIndex NameString
CreateWordFieldOp := 0x8B
DefDataRegion := DataRegionOp NameString TermArg TermArg TermArg
DataRegionOp := ExOpPreﬁx 0x88
DefDevice := DeviceOp PkgLength NameString TermList
DeviceOp := ExtOpPreﬁx 0x82
DefEvent := EventOp NameString
EventOp := ExtOpPreﬁx 0x02
DefExternal := ExternalOp NameString ObjectType ArgumentCount
ExternalOp := 0x15
ObjectType := ByteData
ArgumentCount := ByteData (0 - 7)
DefField := FieldOp PkgLength NameString FieldFlags FieldList
FieldOp := ExtOpPreﬁx 0x81
DefIndexField := IndexFieldOp PkgLength NameString NameString FieldFlags FieldList
20.2. AML Grammar Deﬁnition 993Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
IndexFieldOp := ExtOpPreﬁx 0x86
DefMethod := MethodOp PkgLength NameString MethodFlags TermList
MethodOp := 0x14
MethodFlags :=
ByteData // bit 0-2: ArgCount (0-7)
// bit 3: SerializeFlag
// 0 NotSerialized
// 1 Serialized
// bit 4-7: SyncLevel (0x00-0x0f)
DefMutex := MutexOp NameString SyncFlags
MutexOp := ExtOpPreﬁx 0x01
SyncFlags := ByteData // bits 0-3: SyncLevel (0x00-0x0f), bits 4-7: Reserved (must be 0)
DefOpRegion := OpRegionOp NameString RegionSpace RegionOffset RegionLen
OpRegionOp := ExtOpPreﬁx 0x80
RegionSpace :=
ByteData // 0x00 SystemMemory
// 0x01 SystemIO
// 0x02 PCI_Conﬁg
// 0x03 EmbeddedControl
// 0x04 SMBus
// 0x05 System CMOS
// 0x06 PciBarTarget
// 0x07 IPMI
// 0x08 GeneralPurposeIO
// 0x09 GenericSerialBus
// 0x0A PCC
// 0x80-0xFF: OEM Deﬁned
RegionOffset := TermArg => Integer
RegionLen := TermArg => Integer
DefPowerRes := PowerResOp PkgLength NameString SystemLevel ResourceOrder TermList
PowerResOp := ExtOpPreﬁx 0x84
SystemLevel := ByteData
ResourceOrder := WordData
ProcID := ByteData
PblkAddr := DWordData
PblkLen := ByteData
DefThermalZone := ThermalZoneOp PkgLength NameString TermList
ThermalZoneOp := ExtOpPreﬁx 0x85
ExtendedAccessField := 0x03 AccessType ExtendedAccessAttrib AccessLength
20.2. AML Grammar Deﬁnition 994Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ExtendedAccessAttrib := ByteData // 0x0B AttribBytes, 0x0E AttribRawBytes, 0x0F AttribRawPro-
cess
FieldElement := NamedField |ReservedField |AccessField |ExtendedAccessField |ConnectField
20.2.5.3 Statement Opcodes Encoding
StatementOpcode := DefBreak |DefBreakPoint |DefContinue |DefFatal |DefIfElse |DefNoop |DefNo-
tify|DefRelease |DefReset |DefReturn |DefSignal |DefSleep |DefStall |DefWhile
DefBreak := BreakOp
BreakOp := 0xA5
DefBreakPoint := BreakPointOp
BreakPointOp := 0xCC

cess
DefContinue := ContinueOp
ContinueOp := 0x9F
DefElse := Nothing | < elseop pkglength termlist >
ElseOp := 0xA1
DefFatal := FatalOp FatalType FatalCode FatalArg
FatalOp := ExtOpPreﬁx 0x32
FatalType := ByteData
FatalCode := DWordData
FatalArg := TermArg => Integer
DefIfElse := IfOp PkgLength Predicate TermList DefElse
IfOp := 0xA0
Predicate := TermArg => Integer
DefNoop := NoopOp
NoopOp := 0xA3
DefNotify := NotifyOp NotifyObject NotifyValue
NotifyOp := 0x86
NotifyObject := SuperName => ThermalZone | Processor | Device
NotifyValue := TermArg => Integer
DefRelease := ReleaseOp MutexObject
ReleaseOp := ExtOpPreﬁx 0x27
MutexObject := SuperName
DefReset := ResetOp EventObject
ResetOp := ExtOpPreﬁx 0x26
EventObject := SuperName
DefReturn := ReturnOp ArgObject
ReturnOp := 0xA4
20.2. AML Grammar Deﬁnition 995Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ArgObject := TermArg =>DataRefObject
DefSignal := SignalOp EventObject
SignalOp := ExtOpPreﬁx 0x24
DefSleep := SleepOp MsecTime
SleepOp := ExtOpPreﬁx 0x22
MsecTime := TermArg => Integer
DefStall := StallOp UsecTime
StallOp := ExtOpPreﬁx 0x21
UsecTime := TermArg =>ByteData
DefWhile := WhileOp PkgLength Predicate TermList
WhileOp := 0xA2
20.2.5.4 Expression Opcodes Encoding
ExpressionOpcode := DefAcquire |DefAdd |DefAnd |DefBuffer |DefConcat |DefConcatRes |DefCon-
dRefOf |DefCopyObject |DefDecrement |DefDerefOf |DefDivide |DefFindSetLeftBit |DefFind-
SetRightBit |DefFromBCD |DefIncrement |DefIndex |DefLAnd |DefLEqual |DefLGreater |De-
fLGreaterEqual |DefLLess |DefLLessEqual |DefMid |DefLNot |DefLNotEqual |DefLoadTable |
DefLOr |DefMatch |DefMod |DefMultiply |DefNAnd |DefNOr |DefNot |DefObjectType |DefOr |
DefPackage |DefVarPackage |DefRefOf |DefShiftLeft |DefShiftRight |DefSizeOf |DefStore |Def-
Subtract |DefTimer |DefToBCD |DefToBuffer |DefToDecimalString |DefToHexString | DefToInte-
ger | DefToString |DefWait |DefXOr |MethodInvocation
ReferenceTypeOpcode := DefRefOf |DefDerefOf |DefIndex | UserTermObj
DefAcquire := AcquireOp MutexObject Timeout
AcquireOp := ExtOpPreﬁx 0x23
Timeout := WordData
DefAdd := AddOp Operand Operand Target
AddOp := 0x72
Operand := TermArg => Integer
DefAnd := AndOp Operand Operand Target
AndOp := 0x7B
DefBuffer := BufferOp PkgLength BufferSize ByteList
BufferOp := 0x11
BufferSize := TermArg => Integer
DefConcat := ConcatOp Data Data Target
ConcatOp := 0x73
Data := TermArg => ComputationalData
DefConcatRes := ConcatResOp BufData BufData Target
ConcatResOp := 0x84
20.2. AML Grammar Deﬁnition 996Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
BufData := TermArg =>Buffer
DefCondRefOf := CondRefOfOp SuperName Target
CondRefOfOp := ExtOpPreﬁx 0x12
DefCopyObject := CopyObjectOp TermArg SimpleName
CopyObjectOp := 0x9D
DefDecrement := DecrementOp SuperName
DecrementOp := 0x76
DefDerefOf := DerefOfOp ObjReference
DerefOfOp := 0x83
ObjReference := TermArg =>ObjectReference | String
DefDivide := DivideOp Dividend Divisor Remainder Quotient
DivideOp := 0x78
Dividend := TermArg => Integer
Divisor := TermArg => Integer
Remainder := Target
Quotient := Target
DefFindSetLeftBit := FindSetLeftBitOp Operand Target
FindSetLeftBitOp := 0x81
DefFindSetRightBit := FindSetRightBitOp Operand Target
FindSetRightBitOp := 0x82
DefFromBCD := FromBCDOp BCDValue Target
FromBCDOp := ExtOpPreﬁx 0x28
BCDValue := TermArg => Integer
DefIncrement := IncrementOp SuperName
IncrementOp := 0x75
DefIndex := IndexOp BuffPkgStrObj IndexValue Target
IndexOp := 0x88
BuffPkgStrObj := TermArg =>Buffer , Package, or String
IndexValue := TermArg => Integer
DefLAnd := LandOp Operand Operand
LandOp := 0x90
DefLEqual := LequalOp Operand Operand
LequalOp := 0x93
DefLGreater := LgreaterOp Operand Operand
LgreaterOp := 0x94
DefLGreaterEqual := LgreaterEqualOp Operand Operand
20.2. AML Grammar Deﬁnition 997Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
LgreaterEqualOp := LnotOp LlessOp
DefLLess := LlessOp Operand Operand
LlessOp := 0x95
DefLLessEqual := LlessEqualOp Operand Operand
LlessEqualOp := LnotOp LgreaterOp
DefLNot := LnotOp Operand
LnotOp := 0x92
DefLNotEqual := LnotEqualOp Operand Operand
LnotEqualOp := LnotOp LequalOp
DefLoad := LoadOp NameString Target
LoadOp := ExtOpPreﬁx 0x20
DefLoadTable := LoadTableOp TermArg TermArg TermArg TermArg TermArg TermArg
LoadTableOp := ExtOpPreﬁx 0x1F
DefLOr := LorOp Operand Operand
LorOp := 0x91
DefMatch := MatchOp SearchPkg MatchOpcode Operand MatchOpcode Operand StartIndex
MatchOp := 0x89
SearchPkg := TermArg => Package
MatchOpcode :=
ByteData // 0 MTR
// 1 MEQ
// 2 MLE
// 3 MLT
// 4 MGE
// 5 MGT
StartIndex := TermArg => Integer
DefMid := MidOp MidObj TermArg TermArg Target
MidOp := 0x9E
MidObj := TermArg =>Buffer | String
DefMod := ModOp Dividend Divisor Target
ModOp := 0x85
DefMultiply := MultiplyOp Operand Operand Target
MultiplyOp := 0x77
DefNAnd := NandOp Operand Operand Target
NandOp := 0x7C
DefNOr := NorOp Operand Operand Target
NorOp := 0x7E
20.2. AML Grammar Deﬁnition 998Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
DefNot := NotOp Operand Target
NotOp := 0x80
DefObjectType := ObjectTypeOp <SimpleName |DebugObj |DefRefOf |DefDerefOf |DefIndex >
ObjectTypeOp := 0x8E
DefOr := OrOp Operand Operand Target
OrOp := 0x7D
DefPackage := PackageOp PkgLength NumElements PackageElementList
PackageOp := 0x12
DefVarPackage := VarPackageOp PkgLength VarNumElements PackageElementList
VarPackageOp := 0x13
NumElements := ByteData
VarNumElements := TermArg => Integer
PackageElementList := Nothing | < packageelement packageelementlist >
PackageElement := DataRefObject |NameString
DefRefOf := RefOfOp SuperName
RefOfOp := 0x71
DefShiftLeft := ShiftLeftOp Operand ShiftCount Target
ShiftLeftOp := 0x79
ShiftCount := TermArg => Integer
DefShiftRight := ShiftRightOp Operand ShiftCount Target
ShiftRightOp := 0x7A
DefSizeOf := SizeOfOp SuperName
SizeOfOp := 0x87
DefStore := StoreOp TermArg SuperName
StoreOp := 0x70
DefSubtract := SubtractOp Operand Operand Target
SubtractOp := 0x74
DefTimer := TimerOp
TimerOp := 0x5B 0x33
DefToBCD := ToBCDOp Operand Target
ToBCDOp := ExtOpPreﬁx 0x29
DefToBuffer := ToBufferOp Operand Target
ToBufferOp := 0x96
DefToDecimalString := ToDecimalStringOp Operand Target
ToDecimalStringOp := 0x97
DefToHexString := ToHexStringOp Operand Target
20.2. AML Grammar Deﬁnition 999Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
ToHexStringOp := 0x98
DefToInteger := ToIntegerOp Operand Target
ToIntegerOp := 0x99
DefToString := ToStringOp TermArg LengthArg Target
LengthArg := TermArg => Integer
ToStringOp := 0x9C
DefWait := WaitOp EventObject Operand
WaitOp := ExtOpPreﬁx 0x25
DefXOr := XorOp Operand Operand Target
XorOp := 0x7F
20.2.6 Miscellaneous Objects Encoding
Miscellaneous objects include:
• Arg objects
• Local objects
• Debug objects
20.2.6.1 Arg Objects Encoding
ArgObj := Arg0Op | Arg1Op | Arg2Op | Arg3Op | Arg4Op | Arg5Op | Arg6Op
Arg0Op := 0x68
Arg1Op := 0x69
Arg2Op := 0x6A
Arg3Op := 0x6B
Arg4Op := 0x6C
Arg5Op := 0x6D
Arg6Op := 0x6E
20.2.6.2 Local Objects Encoding
LocalObj := Local0Op | Local1Op | Local2Op | Local3Op | Local4Op | Local5Op | Local6Op | Local7Op
Local0Op := 0x60
Local1Op := 0x61
Local2Op := 0x62
Local3Op := 0x63
Local4Op := 0x64
Local5Op := 0x65
Local6Op := 0x66
20.2. AML Grammar Deﬁnition 1000Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Local7Op := 0x67
20.2.6.3 Debug Objects Encoding
DebugObj := DebugOp
DebugOp := ExtOpPreﬁx 0x31
20.3 AML Byte Stream Byte Values
The following table lists all byte values that can be found in an AML byte stream, and the meaning of each byte value.
This table is useful for debugging AML code.
Table 20.2: AML Byte Stream Byte Values
Encoding
ValueEncoding Name Encoding
GroupFixed List Arguments Variable
List Argu-
ments
0x00 ZeroOp Data Object — —
0x01 OneOp Data Object — —
0x02-0x05 — — — —
0x06 AliasOp Term Object NameString NameString —
0x07 — — — —
0x08 NameOp Term Object NameString DataRefObject —
0x09 — — — —
0x0A BytePreﬁx Data Object ByteData —
0x0B WordPreﬁx Data Object WordData —
0x0C DWordPreﬁx Data Object DWordData —
0x0D StringPreﬁx Data Object AsciiCharList NullChar —
0x0E QWordPreﬁx Data Object QWordData —
0x0F — — — —
0x10 ScopeOp Term Object NameString TermList
0x11 BufferOp Term Object TermArg ByteList
0x12 PackageOp Term Object ByteData Package
TermList
0x13 VarPackageOp Term Object TermArg Package
TermList
0x14 MethodOp Term Object NameString ByteData TermList
0x15 ExternalOp Name Object NameString ByteData ByteData —
0x16-0x2D — — — —
0x2E (‘.’) DualNamePreﬁx Name Object NameSeg NameSeg —
0x2F (‘/’) MultiNamePreﬁx Name Object ByteData NameSeg(N) —
0x30-0x39
(‘0’-‘9’)DigitChar Name Object — —
0x3A-0x40 — — — —
0x41-0x5A
(‘A’-‘Z’)NameChar Name Object — —
0x5B (‘[‘) ExtOpPreﬁx — ByteData —
0x5B 0x00 — — — —
0x5B 0x01 MutexOp Term Object NameString ByteData —
0x5B 0x02 EventOp Term Object NameString —

0x09 — — — —
0x0F — — — —
TermList
TermList
0x30-0x39
0x41-0x5A
20.3. AML Byte Stream Byte Values 1001Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table 20.2 – continued from previous page
Encoding
List Argu-
ments
0x5B 0x12 CondRefOfOp Term Object SuperName SuperName —
0x5B 0x13 CreateFieldOp Term Object TermArg TermArg TermArg
NameString—
0x5B 0x1F LoadTableOp Term Object TermArg TermArg TermArg
TermArg TermArg TermArg—
0x5B 0x20 LoadOp Term Object NameString SuperName —
0x5B 0x21 StallOp Term Object TermArg —
0x5B 0x22 SleepOp Term Object TermArg —
0x5B 0x23 AcquireOp Term Object SuperName WordData —
0x5B 0x24 SignalOp Term Object SuperName —
0x5B 0x25 WaitOp Term Object SuperName TermArg —
0x5B 0x26 ResetOp Term Object SuperName —
0x5B 0x27 ReleaseOp Term Object SuperName —
0x5B 0x28 FromBCDOp Term Object TermArg Target —
0x5B 0x29 ToBCD Term Object TermArg Target —
0x5B 0x2A Reserved — — —
0x5B 0x30 RevisionOp Data Object — —
0x5B 0x31 DebugOp Debug Object — —
0x5B 0x32 FatalOp Term Object ByteData DWordData TermArg —
0x5B 0x33 TimerOp Term Object — —
0x5B 0x80 OpRegionOp Term Object NameString ByteData TermArg
TermArg—
0x5B 0x81 FieldOp Term Object NameString ByteData FieldList
0x5B 0x82 DeviceOp Term Object NameString TermList
0x5B 0x83 Permanently Reserved — Use of this opcode for Proces-
sorOp was deprecated in ACPI
6.4, and is not to be reused.—
0x5B 0x84 PowerResOp Term Object NameString ByteData Word-
DataTermList
0x5B 0x85 ThermalZoneOp Term Object NameString TermList
0x5B 0x86 IndexFieldOp Term Object NameString NameString Byte-
DataFieldList
0x5B 0x87 BankFieldOp Term Object NameString NameString Ter-
mArg ByteDataFieldList
0x5B 0x88 DataRegionOp Term Object NameString TermArg TermArg
TermArg—
0x5B 0x80 -
0x5B 0xFF— — — —
0x5C (‘\’) RootChar Name Object — —
0x5D — — — —
0x5E (‘^’) ParentPreﬁxChar Name Object — —
0x5F(‘_’) NameChar— Name Object — —
0x60 (‘ `’) Local0Op Local Object — —
0x61 (‘a’) Local1Op Local Object — —
0x62 (‘b’) Local2Op Local Object — —
0x63 (‘c’) Local3Op Local Object — —
0x64 (‘d’) Local4Op Local Object — —
0x65 (‘e’) Local5Op Local Object — —
20.3. AML Byte Stream Byte Values 1002Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Encoding
List Argu-
ments
0x66 (‘f’) Local6Op Local Object — —
0x67 (‘g’) Local7Op Local Object — —
0x68 (‘h’) Arg0Op Arg Object — —
0x69 (‘i’) Arg1Op Arg Object — —
0x6A (‘j’) Arg2Op Arg Object — —
0x6B (‘k’) Arg3Op Arg Object — —
0x6C (‘l’) Arg4Op Arg Object — —
0x6D (‘m’) Arg5Op Arg Object — —
0x6E (‘n’) Arg6Op Arg Object — —
0x6F — — — —
0x70 StoreOp Term Object TermArg SuperName —
0x71 RefOfOp Term Object SuperName —
0x72 AddOp Term Object TermArg TermArg Target —
0x73 ConcatOp Term Object TermArg TermArg Target —
0x74 SubtractOp Term Object TermArg TermArg Target —
0x75 IncrementOp Term Object SuperName —
0x76 DecrementOp Term Object SuperName —
0x77 MultiplyOp Term Object TermArg TermArg Target —
0x78 DivideOp Term Object TermArg TermArg Target Tar-
get—
0x79 ShiftLeftOp Term Object TermArg TermArg Target —
0x7A ShiftRightOp Term Object TermArg TermArg Target —
0x7B AndOp Term Object TermArg TermArg Target —
0x7C NandOp Term Object TermArg TermArg Target —
0x7D OrOp Term Object TermArg TermArg Target —
0x7E NorOp Term Object TermArg TermArg Target —
0x7F XorOp Term Object TermArg TermArg Target —
0x80 NotOp Term Object TermArg Target —
0x81 FindSetLeftBitOp Term Object TermArg Target —
0x82 FindSetRightBitOp Term Object TermArg Target —
0x83 DerefOfOp Term Object TermArg —
0x84 ConcatResOp Term Object TermArg TermArg Target —
0x85 ModOp Term Object TermArg TermArg Target —
0x86 NotifyOp Term Object SuperName TermArg —
0x87 SizeOfOp Term Object SuperName —
0x88 IndexOp Term Object TermArg TermArg Target —
0x89 MatchOp Term Object TermArg ByteData TermArg
ByteData TermArg TermArg—
0x8A CreateDWordFieldOp Term Object TermArg TermArg NameString —
0x8B CreateWordFieldOp Term Object TermArg TermArg NameString —
0x8C CreateByteFieldOp Term Object TermArg TermArg NameString —
0x8D CreateBitFieldOp Term Object TermArg TermArg NameString —
0x8E ObjectTypeOp Term Object SuperName —
0x8F CreateQWordFieldOp Term Object TermArg TermArg NameString —
0x90 LandOp Term Object TermArg TermArg —
0x91 LorOp Term Object TermArg TermArg —
0x92 LnotOp Term Object TermArg —
20.3. AML Byte Stream Byte Values 1003Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Encoding
List Argu-
ments
0x92 0x93 LNotEqualOp Term Object TermArg TermArg —
0x92 0x94 LLessEqualOp Term Object TermArg TermArg —
0x92 0x95 LGreaterEqualOp Term Object TermArg TermArg —
0x93 LEqualOp Term Object TermArg TermArg —
0x94 LGreaterOp Term Object TermArg TermArg —
0x95 LLessOp Term Object TermArg TermArg —
0x96 ToBufferOp Term Object TermArg Target —
0x97 ToDecimalStringOp Term Object TermArg Target —
0x98 ToHexStringOp Term Object TermArg Target —
0x99 ToIntegerOp Term Object TermArg Target —
0x9A-0x9B — — — —
0x9C ToStringOp Term Object TermArg TermArg Target —
0x9D CopyObjectOp Term Object TermArg SimpleName —
0x9E MidOp Term Object TermArg TermArg TermArg
Target—
0x9F ContinueOp Term Object — —
0xA0 IfOp Term Object TermArg TermList
0xA1 ElseOp Term Object — TermList
0xA2 WhileOp Term Object TermArg TermList
0xA3 NoopOp Term Object — —
0xA4 ReturnOp Term Object TermArg —
0xA5 BreakOp Term Object — —
0xA6-0xCB — — — —
0xCC BreakPointOp Term Object — —
0xCD-0xFE — — — —
0xFF OnesOp Data Object — —
20.4 AML Encoding of Names in the Namespace
Assume the following namespace exists:
\\
S0
MEM
SET
GET
S1
MEM
SET
GET
CPU
SET
GET
Assume further that a deﬁnition block is loaded that creates a node \S0.CPU.SET, and loads a block using it as a root.
Assume the loaded block contains the following names:
20.4. AML Encoding of Names in the Namespace 1004Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
STP1
^GET
^^PCI0
^^PCI0.SBS
\\S2
\\S2.ISA.COM1
^^^S3
^^^S2.MEM
^^^S2.MEM.SET
Scope(\S0.CPU.SET.STP1) {
XYZ
^ABC
^ABC.DEF
}
This will be encoded in AML as:
'STP1'
ParentPrefixChar 'GET_'
ParentPrefixChar ParentPrefixChar 'PCI0'
ParentPrefixChar ParentPrefixChar DualNamePrefix 'PCI0' 'SBS_'
RootChar 'S2__'
RootChar MultiNamePrefix 3 'S2__' 'ISA_' 'COM1'
ParentPrefixChar ParentPrefixChar ParentPrefixChar 'S3__'
ParentPrefixChar ParentPrefixChar ParentPrefixChar DualNamePrefix 'S2__' 'MEM_'
ParentPrefixChar ParentPrefixChar ParentPrefixChar MultiNamePrefix 3 'S2__' 'MEM_'
˓→'SET_'
After the block is loaded, the namespace will look like this (names added to the namespace by the loading operation
are shown in bold):
\\
S0
MEM
SET
GET
CPU
SET
STP1
XYZ
ABC
DEF
GET
PCI0
SBS
S1
MEM
SET
GET
CPU
SET
GET
S2
ISA
COM1
MEM
SET
S3
20.4. AML Encoding of Names in the Namespace 1005CHAPTER
TWENTYONE
ACPI DATA TABLES AND TABLE DEFINITION LANGUAGE
There are two fundamental types of ACPI tables:
• Tables that contain AML code produced from the ACPI Source Language (ASL). These include the DSDT, any
SSDTs, and sometimes OEM-speciﬁc tables (OEMx).
• Tables that contain simple data and no AML byte code. These types of tables are known as ACPI Data Tables.
They include tables such as the FADT, MADT, ECDT, SRAT, etc. - essentially any table other than a DSDT or
SSDT.
• The ﬁrst type of table is generated using an ASL compiler and this language is speciﬁed in section 18.
The second type of table, the ACPI Data Table, is addressed by this section.
This section describes a simple language (the Table Deﬁnition Language or TDL) that can be used to generate any
ACPI data table. It simpliﬁes the table generation for platform ﬁrmware vendors and can automatically generate ﬁelds
such as table lengths, subtable lengths, checksums, ﬂag ﬁelds, etc.
21.1 Types of ACPI Data Tables
In the context of a compiler for the Table Deﬁnition Language (TDL), there are two types of ACPI Data Tables:
• ACPI tables that are “known” to the compiler. These would typically include all of the basic ACPI tables deﬁned
in the ACPI speciﬁcation such as the FADT, MADT, ECDT, etc. Since these tables are fully speciﬁed (usually
via the ACPI speciﬁcation, but from other sources as well), the TDL compiler knows all details of these tables
– including all required data types, optional or required sub-tables, etc.
• ACPI tables that are unknown to the compiler. These may include tables that are not deﬁned in the ACPI
speciﬁcation such as MCFG, DBGP, etc., or simply new ACPI tables that have not yet been implemented in the
compiler.
One of the goals of the ACPI Table Deﬁnition Language is to support both cases above. Most ACPI tables will be
known to the compiler (and will be the easiest to specify in TDL), but the language is general enough to allow the

compiler.
deﬁnition of new ACPI tables that are unknown or unimplemented in the compiler.
An additional goal of TDL is to support the output of a disassembler that formats an existing table into TDL. This
enables disassembler/change/compile operations.
1006Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
21.2 ACPI Table Deﬁnition Language Speciﬁcation
The following section deﬁnes the ACPI Table Deﬁnition Language (TDL). The grammar notation follows the same
rules as the ASL source language (See Section 19.2.1). Full deﬁnition of the various data types follows the ASL
grammar speciﬁcation.
21.2.1 Overview of the Table Deﬁnition Language (TDL)
Most ACPI tables share the following structure (all except FACS):
• A common, 36 byte header containing the table signature, length, checksum, revision, and other data.
• A table body which contains the speciﬁc table data.
The Table Deﬁnition Language allows the deﬁnition of an ACPI table via a collection of ﬁelds. Each line of TDL
source code is a ﬁeld, and corresponds to a single data item in the deﬁnition of the table.
For example, the C deﬁnition of the common ACPI table header is as follows:
typedef struct acpi_table_header
{
char Signature[4];
char OemId[6];
char OemTableId[8];
char AslCompilerId[4];
UINT32 AslCompilerRevision;
} ACPI_TABLE_HEADER;
In the Table Deﬁnition Language, an ACPI table header can be described as follows:
: "ECDT"
: 00000000
: 01
: 00
: "OEM "
: "MACHINE1"
: 00000001
: ""
: 00000000
Additionally and optionally, it can also be described with accompanying ﬁeld names:
Signature : "ECDT" [Embedded Controller Boot Resources Table]
Table Length : 00000000
Revision : 01
Checksum : 00
Oem ID : "OEM "
Oem Table ID : "MACHINE1"
Oem Revision : 00000001
Asl Compiler ID : ""
Asl Compiler Revision : 00000000
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1007Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Note: In the ACPI table header, the TableLength, Checksum, AslCompilerId, and the AslCompilerRevision ﬁelds
are all output ﬁelds that are ﬁlled in automatically by the compiler during table generation. Also, the ﬁeld names are
output by a disassembler that formats existing tables into TDL code.
21.2.2 TDL Grammar Speciﬁcation
// Root Term
DataTable := FieldList
// Field Terms
FieldList := Field | < ﬁeld ﬁeldlist >
Field := <ﬁelddeﬁnition optionalﬁeldcomment > |CommentField
FieldDeﬁnition :=
// Fields for predeﬁned (known) ACPI tables
<OptionalFieldName ‘:’FieldValue > |
// Generic data types (used for custom or undeﬁned ACPI tables)
<’uint8’ ‘:’ integerexpression > // 8-bit unsigned integer
<’uint16’ ‘:’ integerexpression> // 16-bit unsigned integer
<’uint24’ ‘:’ integerexpression> // 24-bit unsigned integer
<’uint32’ ‘:’ integerexpression> // 32-bit unsigned integer
<’uint40’ ‘:’ integerexpression> // 40-bit unsigned integer
<’uint48’ ‘:’ integerexpression> // 48-bit unsigned integer
<’uint56’ ‘:’ integerexpression> // 56-bit unsigned integer
<’uint64’ ‘:’ integerexpression> // 64-bit unsigned integer
<’string’ ‘:’ String > // Quoted ASCII string
<’unicode’ ‘:’ String > // quoted ascii string -> Unicode string
<’buffer’ ‘:’ byteconstlist > // Raw buffer of 8-bit unsigned integers
<’guid’ ‘:’ guid> // In GUID format
<’label’ ‘:’ label > // ASCII label - unquoted string
OptionalFieldName := Nothing | AsciiCharList // Optional ﬁeld name/description
FieldValue := IntegerExpression |String |Buffer |Flags |Label
OptionalFieldComment := Nothing | <’[‘ asciicharlist ‘]’>
CommentField := <’//’ asciicharlist newline > | <’/ ’ asciicharlist ‘ /’> | <’[‘ asciicharlist ‘]’>
// Data Expressions
IntegerExpression := Integer | < integerexpression integeroperator integerexpression > | <’(‘ integerex-
pression ‘)’>
// Operators below are shown in precedence order. The precedence rules are the same as the C language.
Parentheses have precedence over all operators.
IntegerOperator :=
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1008Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
‘!’ | ‘~’ | ‘*’ | ‘/’ | ‘%’ | ‘+’ | ‘-‘ | ‘<<’ | ‘>>’ | ‘<’ | ‘>’ | ‘<=’ | ‘>=’ | ‘==’ | ‘!=’ | ‘&’ | ‘^’ | ‘|’ | ‘&&’ |
‘||’
// Data Types
String := <’”’ asciicharlist ‘”’>
Buffer := ByteConstList
Guid := <dwordconst ‘-‘wordconst ‘-‘wordconst ‘-‘wordconst ‘-‘const48 >
Label := AsciiCharList
Integer := // duplicate deﬁnition - see previous chapter ByteConst |WordConst |Const24 |DWord-
Const |Const40 |Const48 |Const56 |QWordConst |LabelReference
LabelReference := <’$’ label >
Flags := OneBit | TwoBits
ByteConstList := ByteConst | <byteconst ‘ ‘byteconstlist >
AsciiCharList := Nothing | PrintableAsciiChar | <printableasciichar asciicharlist >
// Terminals
ByteConst := 0x00-0xFF
WordConst := 0x0000 - 0xFFFF
Const24 := 0x000000 - 0xFFFFFF
DWordConst := 0x00000000 - 0xFFFFFFFF
Const40 := 0x0000000000 - 0xFFFFFFFFFF
Const48 := 0x000000000000 - 0xFFFFFFFFFFFF
Const56 := 0x00000000000000 - 0xFFFFFFFFFFFFFF
QWordConst :- 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF
OneBit := 0 - 1
TwoBits := 0 - 3
PrintableAsciiChar := 0x20 - 0x7E
NewLine := ‘n’
21.2.3 Data Types
21.2.3.1 Integers
All integers in ACPI are unsigned. Four major types of unsigned integers are supported by the compiler: Bytes, Words,
DWords and QWords. In addition, for special cases, there are some odd sized integers such as 24-bit and 56-bit. The
actual required width of an integer is deﬁned by the ACPI table. If an integer is speciﬁed that is numerically larger
than the width of the target ﬁeld within the input source, an error is issued by the compiler. Integers are expected by
the data table compiler to be entered in hexadecimal with no “hex” preﬁx.
Examples :
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1009Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
[001] Revision : 04 // Byte (8-bit)
[002] C2 Latency : 0000 // Word (16-bit)
[004] DSDT Address : 00000001 // DWord (32-bit)
[008] Address : 0000000000000001 // QWord (64-bit)
Length of non-power-of-two examples:
[003] Reserved : 000000 // 24 bits
[007] Capabilities : 00000000000000 // 56 bits
21.2.3.2 Integer Expressions
Expressions are supported in all ﬁelds that require an integer value.
Supported operators (Standard C meanings, in precedence order):
() Parentheses
! Logical NOT
~ Bitwise ones compliment (NOT)
*Multiply
/ Divide
% Modulo
+ Add
- Subtract
<< Shift left
>> Shift right
< Less than
> Greater than
<= Less than or equal
>= Greater than or equal
== Equal
!= Not Equal
& Bitwise AND
^ bitwise Exclusive OR
| Bitwise OR
&& Logical AND
|| Logical OR
Examples :
[001] Revision : 04 \ *(4 + 7) // Byte (8-bit)
[002] C2 Latency : 0032 + 8 // Word (16-bit)
21.2.3.3 Flags
Many ACPI tables contain ﬂag ﬁelds. For these ﬁelds, only the individual ﬂag bits need to be speciﬁed to the compiler.
The individual bits are aggregated into a single integer of the proper size by the compiler.
Examples :
[002] Flags (decoded below) : 0005
Polarity : 1
Trigger Mode : 1
In this example, only the Polarity and Trigger Mode ﬁelds need to be speciﬁed to the compiler (as either zero or one).
The compiler then creates the ﬁnal 16-bit Flags ﬁeld for the ACPI table.
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1010Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
21.2.3.4 Strings
Strings must always be surrounded by quotes. The actual string that is generated by the compiler may or may not
be null-terminated, depending on the table deﬁnition in the ACPI speciﬁcation. For example, the OEM ID and OEM
Table ID in the common ACPI table header (shown above) are ﬁxed at six and eight characters, respectively. They
are not necessarily null terminated. Most other strings, however, are of variable-length and are automatically null
terminated by the compiler. If a string is speciﬁed that is too long for a ﬁxed-length string ﬁeld, an error is issued.
String lengths are speciﬁed in the deﬁnition for each relevant ACPI table.
Escape sequences within a quoted string are not allowed. The backslash character ‘' refers to the root of the ACPI
Examples :
[008] Oem Table ID : "TEMPLATE" // Fixed length
[006] Processor UID String : "\CPU0 " // Variable length
21.2.3.5 Buffers
A buffer is typically used whenever the required binary data is larger than a QWord, or the data does not ﬁt exactly
into one of the standard integer widths. Examples include UUIDs and byte data deﬁned by the SLIT table.
Examples :
// SLIT entry
[032] Locality 0 [0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 \] 24 25 26 27 28 29 2A 2B 2C
2D 2E 2F 30 31 32 33
// DMAR entry
[002] PCI Path : 1F 07
Each hexadecimal byte should be entered separately, separated by a space. The continuation character (backslash)
may be used to continue the buffer data to more than one line.
21.2.4 Fields Set Automatically by the Compiler

Examples :
Examples :
There are several types of ACPI table ﬁelds that are set automatically by the compiler. This simpliﬁes the process of
ACPI table development by relieving the programmer from these tasks.
Checksums: All ACPI table checksums are computed and inserted automatically. This includes the main checksum
that appears in the standard ACPI table header, as well as any additional checksum ﬁelds hsuch as the extended
checksum that appears in the ACPI 2.0 RSDP.
Table and Subtable Lengths: All ACPI table lengths are computed and inserted automatically. This includes the
master table length that appears in the common ACPI table header, and the length of any internal subtables as
applicable.
Examples :
[004] Table Length : 000000F4
[001] Subtable Type : 08 <platform interrupt sources>
[001] Length : 10
[001] Subtable Type : 01 <memory affinity>
[001] Length : 28
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1011Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Flags: As described in the previous section, individual ﬂags are aggregated automatically by the compiler and inserted
into the ACPI table as the correctly sized and valued integer.
Compiler IDs: The data table compiler automatically inserts the ID and current revision for iASL into the common
ACPI table header for each table during compilation.
21.2.5 Special Fields
Reserved Fields: All ﬁelds that are declared as Reserved by the table deﬁnition within the ACPI (or other) speciﬁca-
tion should be set to zero.
Table Revision: This ﬁeld in the common ACPI table header is often very important and deﬁnes the structure of the
remaining table. The developer should take care to ensure that this value is correct and current. This ﬁeld is not
set automatically by the compiler. It is instead used to indicate which version of the table is being compiled.
Table Signature: There are several table signatures within ACPI that are either different from the table name, or have
unusual length:
FADT - signature is “FACP”.
MADT - signature is “APIC”.
RSDP - signature is “RSD PTR ” (with trailing space)
21.2.6 TDL Generic Data Types
The following data types are used to construct ACPI tables that are not predeﬁned (known) by the TDL compiler:
UINT8 Generates an 8-bit unsigned integer UINT16 Generates a 16-bit unsigned integer UINT24 Gener-
ates a 24-bit unsigned integer UINT32 Generates a 32-bit unsigned integer UINT40 Generates a 40-bit un-
signed integer UINT48 Generates a 48-bit unsigned integer UINT56 Generates a 56-bit unsigned integer
UINT64 Generates a 64-bit unsigned integer String Generates a null-terminated ASCII string (ASCIIZ)
Unicode Generates a null terminated Unicode (UTF-16) string Buffer Generates a buffer of 8-bit unsigned
integers GUID Generates an encoded GUID in a 16-byte buffer Label Generates a Label at the current
location (offset) within the table. This label can be referenced within integer expressions by prepending
the label with a ‘$’ sign.
21.2.7 Deﬁning a Known ACPI Table in TDL
It is expected that most ACPI tables that will be created via the TDL compiler are ACPI tables that are known to the
compiler. This means that the compiler contains the required structure and deﬁnition of the table, as per the ACPI
speciﬁcation or other speciﬁcation for that table.
For these known ACPI tables, specifying the data for the table involves simply deﬁning the value for each ﬁeld in the
table. The compiler automatically types the data, performs range and any value checks, and generates the appropriate
output.
The starting point for any of the known ACPI tables is the document that speciﬁes the format of the table (usually the
ACPI speciﬁcation), or a table template ﬁle generated by an ASL compiler, or even the output of an AML disassembler.
Writing the TDL code involves implementing one line of code for each data item speciﬁed in the table deﬁnition itself.
For example, the table header for an ACPI table can be deﬁned as simply a sequence of strings and integers. The TDL
compiler will format these data items into a 36-byte ACPI header:
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1012Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
: "ECDT"
: 00000000
: 01
: 00
: "OEM "
: 00000001
: ""
: 00000000
21.2.8 Deﬁning an Unknown or New ACPI table in TDL
For ACPI tables that are new or whose formats are otherwise unknown to the compiler, “generic” data types are
introduced to allow the deﬁnition of these tables using explicit data types.
Examples of Generic Data Types :
Label : StartRecord
UINT8 : 11
UINT16 : $EndRecord - $StartRecord // Record length
UINT24 : 112233
UINT32 : 11223344
UINT56 : 11223344556677
UINT64 : 1122334455667788
String : "This is a string"
DevicePath : "\PciRoot(0)\Pci(0x1f,1)\Usb(0,0)"
Unicode : "This string will be encoded to Unicode"
Buffer : AA 01 32 4C 77
GUID : 11223344-5566-7788-99aa-bbccddeeff00
Label : EndRecord
21.2.9 Table Deﬁnition Language Examples
21.2.9.1 ECDT Disassembler Output
The output of the iASL disassembler may be used as direct input to the TDL compiler:
[000h 0000 4] Signature : "ECDT" [Embedded Controller Data Table]
[004h 0004 4] Table Length : 0000004E
[008h 0008 1] Revision : 01
[009h 0009 1] Checksum : F4
[00Ah 0010 6] Oem ID : "INTEL "
[010h 0016 8] Oem Table ID : "TEMPLATE"
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "INTL"
[020h 0032 4] Asl Compiler Revision : 20110316
[024h 0036 12] Command/Status Register : [Generic Address Structure]
[024h 0036 1] Space ID : 01 [SystemIO]
[025h 0037 1] Bit Width : 08
[026h 0038 1] Bit Offset : 00
[027h 0039 1] Encoded Access Width : 00 [Undefined/Legacy]
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1013Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
[028h 0040 8] Address : 0000000000000066
[030h 0048 12] Data Register : [Generic Address Structure]
[030h 0048 1] Space ID : 01 [SystemIO]
[031h 0049 1] Bit Width : 08
[032h 0050 1] Bit Offset : 00
[033h 0051 1] Encoded Access Width : 00 [Undefined/Legacy]
[034h 0052 8] Address : 0000000000000062
[03Ch 0060 4] UID : 00000000
[040h 0064 1] GPE Number : 09
[041h 0065 13] Namepath : "\_SB.PCI0.EC"
Raw Table Data: Length 78 (0x4E)
0000: 45 43 44 54 4E 00 00 00 01 F4 49 4E 54 45 4C 20 ECDTN.....INTEL
0010: 54 45 4D 50 4C 41 54 45 01 00 00 00 49 4E 54 4C TEMPLATE....INTL
0020: 16 03 11 20 01 08 00 00 66 00 00 00 00 00 00 00 ... ....f.......
0030: 01 08 00 00 62 00 00 00 00 00 00 00 00 00 00 00 ....b...........
0040: 09 5C 5F 53 42 2E 50 43 49 30 2E 45 43 00 .\_SB.PCI0.EC.
21.2.9.2 ECDT Deﬁnition with Field Comments
Similar to the disassembler output but simpler:
Signature : "ECDT" [Embedded Controller Data Table]
Table Length : 0000004E
Checksum : F4
Oem ID : "INTEL "
Oem Table ID : "TEMPLATE"
Asl Compiler ID : "INTL"
Asl Compiler Revision : 20110316
Command/Status Register : [Generic Address Structure]
Space ID : 01 [SystemIO]
Bit Width : 08
Bit Offset : 00
Encoded Access Width : 00 [Undefined/Legacy]
Address : 0000000000000066
Data Register : [Generic Address Structure]
Address : 0000000000000062
UID : 00000000
GPE Number : 09
Namepath : "\_SB.PCI0.EC"
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1014Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
21.2.10 Minimal ECDT Deﬁnition
An example of a minimal ECDT deﬁnition with no Field Names:
: "ECDT" [Embedded Controller Boot Resources Table]
: 0000004E
: 01
: F4
: "INTEL "
: "TEMPLATE"
: 00000001
: "INTL"
: 20110316
: [Generic Address Structure]
: 01 [SystemIO]
: 08
: 00
: 00 [Undefined/Legacy]
: 0000000000000066
: 08
: 00
: 0000000000000062
: 00000000
: 09
: "\_SB.PCI0.EC"
21.2.10.1 Generic ACPI Table Deﬁnition
Tables that are not known to the TDL compiler can be deﬁned by using the generic data types. All ACPI tables are
assumed to have the common ACPI header, however:
Signature : "OEMZ"
Table Length : 00000052
Checksum : 6C
Oem ID : "TEST"
Oem Table ID : "CUSTOM "
Asl Compiler ID : "INTL
Asl Compiler Revision : 00000001
UINT8 : 01
UINT8 : 08
UINT8 : 00
UINT8 : 00
UINT64 : 0000000000000066
UINT32 : 00000000
UINT8 : 12
String : "Hello World!"
21.2. ACPI Table Deﬁnition Language Speciﬁcation 1015APPENDIX
A
APPENDIX A: DEVICE CLASS SPECIFICATIONS
This section deﬁnes the behavior of devices as that behavior relates to power management and, speciﬁcally, to the four
device power states deﬁned by ACPI. The goal is enabling device vendors to design power-manageable products that
meet the basic needs of OSPM and can be utilized by any ACPI-compatible operating system.
A.1 Overview
The power management of individual devices is the responsibility of a policy owner in the operating system. This

UINT8 : 01
UINT8 : 08
UINT8 : 00
UINT8 : 00
UINT8 : 12
A
software element will implement a power management policy that is appropriate for the type (or class) of device being
managed. Device power management policy typically operates in conjunction with a global system power policy
implemented in the operating system.
In general, the device-class power management policy strives to reduce power consumption while the system is work-
ing by transitioning among various available power states according to device usage. The challenge facing policy
owners is to minimize power consumption without adversely impacting the system’s usability. This balanced approach
provides the user with both power savings and good performance.
Because the policy owner has very speciﬁc knowledge about when a device is in use or potentially in use, there is no
need for hardware timers or such to determine when to make these transitions. Similarly, this level of understanding
of device usage makes it possible to use fewer device power states. Generally, intermediate states attempt to draw a
compromise between latency and consumption because of the uncertainty of actual device usage. With the increased
knowledge in the OS, good decisions can be made about whether the device is needed at all. With this ability to turn
devices off more frequently, the beneﬁt of having intermediate states diminishes.
The policy owner also determines what class-speciﬁc events can cause the system to transition from sleeping to work-
ing states, and enables this functionality based on application or user requests. Notice that the deﬁnition of the wake
events that each class supports will inﬂuence the system’s global power policy in terms of the level of power man-
agement a system sleeping state can attain while still meeting wake latency requirements set by applications or the
user.
A.2 Device Power States
The following deﬁnitions apply to devices of all classes:
•D0. State in which device is on and running. It is receiving full power from the system and is delivering full
functionality to the user.
•D1. Class-speciﬁc low-power state (deﬁned in the following section) in which device context may or may not
be lost. Buses in D1 cannot do anything to the bus that would force devices on that bus to lose context.
•D2. Class-speciﬁc low-power state (deﬁned in the following section) in which device context may or may not
be lost. Attains greater power savings than D1. Buses in D2 can cause devices on that bus to lose some context
1016Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
(for example, the bus reduces power supplied to the bus). Devices in D2 must be prepared for the bus to be in
D2 or higher.
•D3. State in which device is off and not running. Device context is lost. Power can be removed from the device.
Device power-state transitions are typically invoked through bus-speciﬁc mechanisms (for example, ATA Standby,
USB Suspend, and so on). In some cases, bus-speciﬁc mechanisms are not available and device-speciﬁc mechanisms
must be used. Notice that the explicit command for entering the D3 state might be the removal of power.
It is the responsibility of the policy owner (or other software) to restore any lost device context when returning to the
D0 state.
A.2.1 Bus Power Management
Policy owners for bus devices (for example, PCI, USB, Small Computer System Interface [SCSI]) have the additional
responsibility of tracking the power states of all devices on the bus and for transitioning the bus itself to only those
power states that are consistent with those of its devices. This means that the bus state can be no lower than the highest
state of one of its devices. However, enabled wake events can affect this as well. For example, if a particular device is
in the D2 state and set to wake the system and the bus can only forward wake requests while in the D1 state, then the
bus must remain in the D1 state even if all devices are in a lower state.
Below are summaries of relevant bus power management speciﬁcations with references to the sources.
A.2.2 Display Power Management
Refer to the Display Power Management Signaling Speciﬁcation (DPMS), available from:
Video Electronics Standards Association (VESA)
2150 North First Street
Suite 440
San Jose, CA 95131-2029
A DPMS-compliant video controller and DPMS-compliant monitor use the horizontal and vertical sync signals to
control the power mode of the monitor. There are 4 modes of operation: normal, standby, suspend and off. DPMS-
compliant video controllers toggle the sync lines on or off to select the power mode.
A.2.3 PCMCIA/PCCARD/CardBus Power Management
PCMCIA and PCCARD devices do not have device power states deﬁned. The only power states available are on
and off, controlled by the host bus controller. The CardBus speciﬁcation is a superset of the PCCARD speciﬁcation,
incorporating the power management speciﬁcation for PCI bus. Power management capabilities query, state transition
commands and wake event reporting are identical.
A.2. Device Power States 1017Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.2.4 PCI Power Management
For information on PCI Power Management, see the PCI Special Interest Group (PCI-SIG) website. You can ﬁnd a
link to this site at http://ueﬁ.org/acpi, under the heading “PCI Sig”.
•PCI Bus Power Management Capabilities Query . PCI Bus device capabilities are reported via the optional
Capabilities List registers, which are accessed via the Cap_Ptr.
•PCI Bus Power Management State Transition Commands . PCI Bus device power states are controlled and
queried via the standard Power Management Status/Control Register (PMCSR).
•PCI Bus Wakeup Event Reporting . PCI wake events are reported on the optional PME# signal, with setting of
the Wake_Int bit in the PMCSR. Wake event reporting is controlled by the Wake_En bit in the PMCSR register.
A.2.5 USB Power Management
See the Universal Serial Bus Implementers Forum (USB-IF ) Web site, as listed at http://ueﬁ.org/acpi under the heading
“Universal Serial Bus Power Management”.
•USB Power Management Capabilities Query . USB device capabilities are reported to the USB Host via the
standard Power Descriptors. These address power consumption, latency time, wake support, and battery support
and status notiﬁcation.
•USB Power Management State Transition Commands . USB device power states are controlled by the USB
Host via the standard SET_FEATURE command. USB device power states are queried via the standard USB
GET_STATUS command.
•USB Wakeup Event Reporting . USB wake event reporting is controlled using the SET_FEATURE command,
with value DEVICE_REMOTE_WAKEUP. USB wake events are reported by sending remote wake resume
signaling.
A.2.6 Device Classes
Below is a list of the class-speciﬁc device power management deﬁnitions available in this speciﬁcation. Notice that
there exists a default device class deﬁnition that applies to all devices, even if there is a separate, class-speciﬁc section
that adds additional requirements.
•Audio Device Class . Applies to audio devices.
•COM Port Device Class . Applies to COM ports devices.
•Display Device Class . Applies to CRT monitors, LCD panels, and video controllers for those devices.
•Input Device Class . Applies to standard types of input devices such as keyboards, keypads, mice, pointing
devices, joysticks, and game pads, plus new types of input devices such as virtual reality devices.
•Modem Device Class . Applies to modem and modem-like (for example, ISDN terminal adapters) devices.
•Network Device Class . Applies speciﬁcally to Ethernet and token ring adapters. ATM and ISDN adapters are
not supported by this speciﬁcation.
•PC Card Controller Device Class . Applies to PC Card controllers and slots.
•Storage Device Class . Applies speciﬁcally to ATA hard disks, ﬂoppy disks, ATAPI and SCSI CD-ROMs, and
the IDE channel.
A.2. Device Power States 1018Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.3 Default Device Class
The requirements expressed in this section apply to all devices, even if there is a separate, class-speciﬁc power man-
agement deﬁnition that identiﬁes additional requirements.
Table A-1: Default Power State Deﬁnitions
State Deﬁnition
D0 Device is on and running. It is receiving full power from the system, and is delivering full func-
tionality to the user.
D1 This state is not deﬁned and not used by the default device class.
D2 This state is not deﬁned and not used by the default device class.
D3 Device is off and not running. Device context is assumed lost, and there is no need for any of it
to be preserved in hardware. This state should consume the minimum power possible. Its only
requirement is to recognize a bus-speciﬁc command to re-enter D0. Power can be removed from
the device while in D3. If power is removed, the device will receive a bus-speciﬁc hardware reset
upon reapplication of power, and should initialize itself as in a normal power on.
A.3.1 Default Power Management Policy
Table A-2: Default Power Management Policy
Present
StateNext
StateCause

Present
StateNext
D0 D3 Device determined by the OS to not be needed by any applications or the user. System
enters a sleeping state.
D3 D0 Device determined by the OS to be needed by some application or the user.
A.3.2 Default Wake Events
There are no default wake events, because knowledge of the device is implicit in servicing such events. Devices can
expose wake capabilities to OSPM, and device-speciﬁc software can enable these, but there is no generic application-
level or OS-wide support for undeﬁned wake events.
A.3.3 Default Minimum Power Capabilities
All devices must support the D0 and D3 states. Functionality available in D0 must be available after returning to D0
from D3 without requiring a system reboot or any user intervention. This requirement applies whether or not power is
removed from the device during D3.
A.3. Default Device Class 1019Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.4 Audio Device Class
The requirements expressed in this section apply to audio devices
A.4.1 Audio Device Power State Deﬁnitions
Table A-3: Audio Device Power State Deﬁnitions
State Status Deﬁnition
D0 Required Power is on. Device is operating.
D1 Optional Power consumption is less than D0 state. Device must be able to transition between
D0 and D1 states within 100 ms. No audio samples may be lost by entering and
leaving this state.
D2 Required Power consumption is less than D0 state. Device must be able to transition between
D0 and D2 states within 100 ms. Audio samples may be lost by entering and leaving
D3 Required The device is completely off or drawing minimal power. For example, a stereo will
be off, but a light-emitting diode (LED) may be on and the stereo may be listening to
IR commands.
If a device is in the D1 or D2 state it must resume within 100 ms. A device in the D3 state may take as long as it needs
to power up. It is the responsibility of the policy owner to advertise to the system how long a device requires to power
up.
All audio devices must be capable of D0, D2 and D3 states. It is desirable that an audio device be capable of D1 state.
The difference between D1 and D2 is that a device capable of D1 can maintain complete state information in reduced
power mode. The policy owner or other software must save all states for D2-capable devices. Some audio samples
may be lost in transitioning into and out of the D2 state.
Notice that the D1 state was added to allow digital signal processor (DSP)-equipped audio hardware to exploit low-
power modes in the DSP. For example, a DSP may be used to implement Dolby AC-3 Decode. When paused it stops
playing audio, but the DSP may contain thousands of bytes worth of state information. If the DSP supports a low-
power state, it can shut down and later resume from exactly the audio sample where it paused without losing state
A.4.2 Audio Device Power Management Policy
For the purpose of the following state transition policy, the following device-speciﬁc operational states are deﬁned:
•Playing . Audio is playing.
•Recording :
•Foreground . Normal application is recording. Recording is considered foreground unless speciﬁcally desig-
nated low priority.
•Background . Speech recognition or speech activity detection is running. Recording may be preempted by
foreground recording or playing. Any audio recording may be designated as background.
•Full Duplex . Device is simultaneously playing and recording.
•Paused . File handle is open. Only devices that are playing, foreground recording or in full duplex operation
may be paused. Background recording may not be paused. State is static and never lost. The paused state
assumes that a device must transition to the resumed state rapidly. Playing or recording must be resumed within
100 ms. No audio samples may be lost between the device is paused and later resumed.
A.4. Audio Device Class 1020Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
•Closed . No ﬁle handle is open.
Table A-4: Audio Device Power Management Policy
Present
StateNext
D3 D0 Audio device moves from closed to open state or paused when the device receives the
resume command.
D0 D1 Audio device receives pause command. If device is D1 capable, this state is preferred. If
not, the device driver will preserve context, and the device will be set to D2.
D2/D1 D0 Audio device receives a resume command.
D0 D2 Audio device is closed. Audio inactivity timer started.
D2 D3 Audio inactivity timer expires.
D0 D3 Audio device is in background record mode and receives power-down command.
When an audio device is in the D0 state it will refuse system requests to transition to D3 state unless it is in background
record mode. When an audio device is paused (D1 or D2) and it receives a request to transition to the D3 state, it will
save the state of the audio device and transition to the D3 state.
Since multimedia applications often open and close audio ﬁles in rapid succession, it is recommended that an inactivity
timer be employed by the policy owner to prevent needless shutdowns (D3 transitions) of the audio hardware. For
example, frequent power cycling may damage audio devices powered by vacuum tubes.
A.4.3 Audio Device Wake Events
An audio device may be a wake device. For example, a USB microphone designed for security applications might use
the USB wake mechanism to signal an alarm condition.
A.4.4 Audio Device Minimum Power Capabilities
All audio devices must be capable of D0, D2 and D3 power states. If the device is capable of maintaining context
while in a low-power state it should advertise support for D1. Transitional latency for the D2 or D3 states must be less
than 100 ms. There are no latency restrictions for D3 transitions, but the policy owner should advertise the amount of
time required.
A.5 COM Port Device Class
The requirements expressed in this section apply to Universal Asynchronous Receiver/Transmitters (UARTs) such as
the common NS16550 buffered serial port and equivalents.
The two required states for any power-managed COM Port are full on (D0) and full off (D3). This in turn requires that
the COM port hardware be power-manageable by ACPI control methods for COM ports that are on system boards, or
by standard bus power management controls for COM ports that are on add-in cards (for example, PCI). Because of
this, ISA-based COM port add-in cards will not be able to meet this requirement, and therefore cannot be compliant
A.5. COM Port Device Class 1021Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.5.1 COM Port Power State Deﬁnitions
Table A-5: COM Port Device Power State Deﬁnitions
D0 Required Line drivers are on. UART context is preserved.
D1 N/A This state is not deﬁned for COM Ports. Use the D3 state instead.
D2 N/A This state is not deﬁned for COM Ports. Use the D3 state instead.
D3 Required Line drivers are off (unpowered; outputs isolated from devices attached to the port).
UART context is lost. Latency to return to D0 is less than 1 second.
A.5.2 COM Power Power Management Policy
Table A-6: COM Port Device Power Management Policy
Present
StateNext
D3 D0 Power-on reset COM port opened by an application
D0 D3 COM port closed System enters sleeping state while wake is disabled on this device. System
enters sleeping state while wake is enabled on this device and the device is capable of
generating wake to the system from state D3.
A.5.3 COM Port Wake Events
If the COM port is capable of generating wake events, asserting the “ring indicator” line (V .24 circuit 125) will cause
the COM port to assert a wake event. There are two common mechanisms that may be employed (either one or both)
for performing machine wake using COM ports.
The ﬁrst provides a solution that is capable of waking the PC whether the UART is powered (D0) or not (D3). Here, the
“ring indicator” line (from V .24 circuit 125) is commonly connected directly to the system wake device in addition to
being connected to the UART. While this implementation is normative for COM ports located on system motherboards
(see the ACPI speciﬁcation), it could also be done by add-in cards with COM ports that reside on buses supporting
system wake from devices in D3 (for example, PME# signal on PCI).
The second mechanism requires that the UART be powered (D0) to use the UART’s interrupt output pin to generate
the wake event instead. When using this method, the OS COM port policy owner or power management control
methods are expected to conﬁgure the UART. Although any UART interrupt source (for example, ‘data ready’) could
theoretically be used to wake the system, these methods are beyond the scope of this document.
A.5.4 COM Port Minimum Power Capabilities
A COM port conforming to this speciﬁcation must support the D0 and D3 states.
A.5. COM Port Device Class 1022Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.6 Display Device Class

The requirements expressed in this section apply to all devices engaged in the display of program content, which
includes full screen display devices, display controllers, and graphics adapters. This class does not include video
capture devices unless they are children of the graphics adapter. This class does not include edge displays or hardware
indicators for device states.
While saving power from the display and adapter are primary goals of Display Device Class power management
deﬁnitions, the deﬁnitions are also intended to ensure that the user perceives the system as “off” during system sleeping
states, as required above. When the system enters a lower power state, the screen must go black so the user knows the
system is idle. This is important because devices that cannot actually save power (standard televisions, for example)
can still support the user notice of system idle by going black.
A.6.1 Display Device Power State Deﬁnitions
Table A-7: CRT Monitors Power State Deﬁnitions
D0 Required This state is equivalent to the “On” state deﬁned in the VESA DPMS speciﬁcation
(see Related Documents) and is signaled to the display using the DPMS method.
Display is fully on Video image is active
D1 Optional This state is equivalent to the “Standby” state deﬁned in the VESA DPMS and is
signaled to the display using the DPMS method. Display is functional but may be
conserving energy Video image is blank Latency to return to D0 must be less than 5
seconds
D2 Required This state is equivalent to the “Suspend” state deﬁned in the VESA DPMS speciﬁ-
cation and is signaled to the display using the DPMS method. Display is functional
and conserving energy Video image is blank Latency to return to D0 is less than 10
seconds
D3 Required This state is equivalent to the “Off” state deﬁned in the VESA DPMS speciﬁcation
and is signaled to the display using the DPMS method. Display is non-functional
Video image is blank
CRT Monitors are a special case in power management. On the one hand, they support a common deﬁned method
(DPMS) for changing power states. On the other hand, that procedure and the CRT support is extremely slow and out
of keeping with other faster power control methods used by other forms of display. This deﬁnition should not preclude
the use of faster and more effective methods of transitioning the CRT if they are available and known to the controller.
DPMS is not recommended as solution for new display devices in the future.
Table A-8: Internal Flat Panel Displays Power State Deﬁnitions
A.6. Display Device Class 1023Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
D0 Required This state is equivalent to the “On” state for a DPMS device, but is signaled to the
panel by the correct application of power and/or controller speciﬁc signaling. Display
is fully on Backlight (if present) is fully on(subject to performance state requirements
- see below) Video image is active
D1 Optional This state is not required to be physically different than a D3 state if the device is able
to meet the resume requirement and the driver is able to restore state. Display retains
internal state but may be conserving energy Backlight(if present) is fully off Video
image is blank Latency to return to D0 must be less than 500 milliseconds
D2 Optional This state is not required to be physically different than a D3 state if the device is able
state but is conserving energy Backlight (if present) is fully off; Video image is blank
Latency to return to D0 is less than 500 milliseconds
D3 Required This state is equivalent to the “Off” state deﬁned in the VESA DPMS speciﬁcation.
It is signaled by the removal of power or possibly by controller-speciﬁc signaling.
Display is non-functional Backlight (if present) is fully off. Video image is blank
Internal ﬂat panels (also known as local ﬂat panels or sometimes as LCDs) do not normally support or require DPMS
signaling to change power states. Instead, controllers capable of managing such panels tend to provide vendor-speciﬁc
methods to control internal ﬂat panels, often involving special sequencing of power signals to the panel. Some may be
managed only by the application or removal of power.
Backlight control for power management states is likewise controller and even platform speciﬁc. Note that on-off
backlight control for power management states is often unrelated to backlight intensity or brightness control that is
used while in the D0 state.
The 500 milliseconds is only to allow some existing hardware to function . The target for new devices should be 100
milliseconds.
Table A-9: External Digital Displays Power State Deﬁnitions
D0 Required This state is equivalent to the “On” state for a DPMS device, but is signaled to the dis-
play by the correct application of power and/or controller speciﬁc signaling. Display
is fully on. Video image is active.
to meet the resume requirement and the driver is able to restore state. It is signaled
by the removal of display output and time expiring. The physical state entered is no
different than D2. Display retains internal state but may be conserving energy Video
image is blank Latency to return to D0 must be less than 250 milliseconds*.
by the removal of display output and time expiring The physical state entered is no
different than D1. Display retains state but is conserving energy. Video image is
blank. Latency to return to D0 is less than 250 milliseconds*.
It is signaled by the removal of display output and time expiring. Display is non-
functional. Video image is blank. Latency to return to D0 is less than 250 millisec-
onds*.
Note: * Although a latency of 250 milliseconds is shown here, because not all devices in this group are faster, the
A.6. Display Device Class 1024Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
target resume time for a new device should be less than 100 milliseconds.
Table A-10: Standard TV Devices and Analog HDTVs Power State Deﬁnitions
D0 Required This state is equivalent to the “On” state for a DPMS device. Display is fully on Video
image is active
D1 Optional Video image is blank Latency to return to D0 must be less than 100 milliseconds
D2 Optional Video image is blank Latency to return to D0 must be less than 100 milliseconds
D3 Required This state is not equivalent to the “Off” state deﬁned in the VESA DPMS speciﬁcation
because not power is actually saved. Video image is blank Latency to return to D0 is
less than 100 milliseconds
Table A-11: Other (new) Full Screen Display Devices Power State Deﬁnitions
Some devices not speciﬁcally deﬁned above already exist, such as projectors that emulate CRTs or HDTVs. Others
may be coming. It is important for any device used for full screen display to support power transitions and power
management states, but the primary requirement for the method should be low overhead.
panel by the correct application of power and/or device speciﬁc signaling known to
the controller. Display is fully on Video image is active
to meet the resume requirement and the driver is able to restore state. It is signaled to
the panel by the correct application of power and/or device speciﬁc signaling known
to the controller. Display retains internal state but may be conserving energy Video
image is blank Latency to return to D0 must be less than 100 milliseconds
to the controller. Display retains state but is conserving energy Video image is blank
Latency to return to D0 is less than 100 milliseconds
It is signaled by the removal of display output and/or device speciﬁc methods known
to the controller. Display is non-functional Video image is blank Latency to return to
D0 is less than 250 milliseconds

Table A-12: Video Controllers (Graphics Adapters) Power State Deﬁnitions
A.6. Display Device Class 1025Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
D0 Required Back-end is on Video controller context is preserved Video memory contents are pre-
served
D1 Optional Back-end is off, except for CRT control signaling (DPMS) Video controller context
is preserved Video memory contents is preserved Latency to return to D0 is less than
100 milliseconds
D2 Optional Back-end is off, except for CRT control signaling (DPMS) Video controller context is
lost Video memory contents is lost Latency to return to D0 is less than 200 millisec-
onds
D3 Required Back-end is off Video controller context is lost (power removed) Video memory con-
tents is lost (power removed) Latency to return to D0 is less than 200 milliseconds
A.6.1.1 Display Codecs
Like the displays they control, display codecs are children of the adapter and cannot be in a higher state than the adapter
or a lower state than the displays they control . It is generally not helpful to deal with codecs entirely separately from
the adapter or the displays they control. While it may vary from device to device, a codec will either be safely powered
down when its display is powered down or it may require power as long as the adapter receives power.
A.6.2 Display Device Power Management Policy
Table A-13: Display Device Power Management Policy
Present
StateNext
D0 D1 User inactivity for a period of time (T1)
D1 D2 User inactivity for a period of time (T2 > T1)
D2 D3 User inactivity for a period of time (T3 > T2)
D1/D2/D3 D0 User activity or application UI change (for example, dialog pop-up)
These state transition deﬁnitions apply to both the full screen display and the video controller. However, the control
of the two devices is independent, except that a video controller will never be put into a lower power state than its full
screen display. Also, while full screen displays can transition directly from D1 to D3 or from D2 to D3, the adapters
require a transition to D0 from D1 or D2 before entering D3.
Transitions for the video controller are commanded via the bus-speciﬁc control mechanism for device states. Mon-
itor/LCD transitions are commanded by signaling from the video controller and are only generated as a result of
explicit commands from the policy-owner. Full screen display power control is functionally independent from any
other interface the monitor may provide (such as USB). For instance, Hubs and HID devices in the monitor enclosure
may be power-managed by their driver over the USB bus, but the Monitor/LCD device itself may not; it must be
power-managed from the video controller using the methods above.
A.6. Display Device Class 1026Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.6.3 Display Device Wake Events
Display devices incorporating a system power switch should generate a wake event when the switch is pressed while
the system is sleeping.
A.6.4 Display Device Minimum Power Capabilities
A CRT monitor conforming to this speciﬁcation must support the D0, D2, and D3 states. Other full screen displays
only need to support D0 and D3. Support for the D1 state is optional in all cases. Transitional latencies for the D1 or
D2 state must meet the requirements above.
A video controller conforming to this speciﬁcation must support the D0 and D3 states. Support for the D1 and D2
states is optional. Transitional latencies for the D1 must be less than 100 milliseconds while D2 and D3 must transition
to D0 in less than 200 milliseconds.
A.6.5 Display Device Performance States
Performance states for display devices and adapters have one clear difference from deﬁned power management states.
There is no display in any power management state higher than D0. However, performance states are all applied within
D0, which means they save power while continuing to display. Not all display class devices will support performance
states, but in all cases, they must allow continued display where they exist.
A.6.5.1 Common Requirements for Display Class Performance States
The deﬁnition of each state (up the line toward the OSPM) must include maximum latency information on transitions
into the state and transitions out of the state. (For states other than DPS1, it may be necessary to indicate whether the
latency is the time from DPS0 to DPSx or only from DPSx-1 to DPSx.)
Each state has to have a relative weight indicator or a relative power savings indicator (i.e., it can make a difference in
OSPM policies whether DPS1 saves 2% power and DPS2 save 75% power even if latency is longer.)
While ASL NameSpace structures may provide some of this information, it is recommended that display class perfor-
mance states be entered and exited by driver and not by control method wherever possible.
A.6.5.2 Performance states for Full Screen Displays
A.6.5.2.1 CRT Performance States
Some CRTs (in theory) have the capability for “reduced on” – a mode which displays but uses less power than full
performance. Even without this capability, a CRT may be able to use reduced refresh or other methods to reduce the
total power of displaying.
A.6. Display Device Class 1027Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.6.5.2.2 Internal Flat Panel
In general, panels consume a ﬁxed amount of power. However, some panels are also capable of supporting reduced
refresh. More important, the amount of backlight brightness is a major factor in system power. This clearly needs to be
coordinated with direct ASL control methods for brightness and with ambient light sensing when present. However,
a performance state may be achieved by offsetting the brightness value computed by other methods, either by a ﬁxed
amount or a ﬁxed percentage.
A.6.5.2.3 DVI Full Screen Devices
DVI Devices are normally capable of frequency control and may be able to beneﬁt by frequency control. However,
because of sensitivity to signal loss, DVI devices may have limitations on other types of performance control.
A.6.5.2.4 Standard TV and Analog HDTVs
Standard TV and Analog HDTVs do not appear capable of performance states. Codecs controlling them may be
capable of power saving, however.
A.6.5.2.5 New Devices
The ability to reduce power while continuing to display will be increasingly important.
A.6.5.3 Performance States for Video Controllers/Display Adapters
Adapters are somewhat limited during performance states because they have to continue to support display on one or
more full screen devices. However, they can still do a number of things to support performance states, including
• Changes to basic display and render capabilities, including speed or frequency range supported.
• Feature/Capability/Quality Control - limiting speciﬁc hardware features, limiting refresh rates, limiting resolu-
tions.
The limiting factor on what can be supported may sometimes be in the OSPM. If the OSPM support dynamic changes
in these features during a performance state change (even if no other time), more opportunities arise.
Once again, the latency on transitions and the power saved by speciﬁc states have to be made available to the OSPM
in order to use these options effectively.
A.7 Input Device Class
The requirements expressed in this section apply to standard types of input devices such as keyboards, keypads, mice,
pointing devices, joysticks, game pads, to devices that combine these kinds of input functionality (composite devices,
and so on), and to new types of input devices such as virtual reality devices, simulation devices, and so on.
A.7. Input Device Class 1028Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.7.1 Input Device Power State Deﬁnitions
Table A-14: Input Device Power State Deﬁnitions
D0 Required Device is receiving full power from its power source, delivering full functional-
ity to the user, and preserving applicable context and state information.
D1 Optional Input device power consumption is greatly reduced. In general, device is in
a power management state and is not delivering any functionality to the user
except wake functionality if applicable. Device status, state, or other infor-
mation indicators (for example, LEDs, LCD displays, and so on) are turned
off to save power. The following device context and state information should
be preserved by the policy owner or other software: Keyboard. Num, caps,
scroll lock states (and Compose and Kana states if applicable) and associated
LED/indicator states, repeat delay, and repeat rate. Joystick. Forced feedback
effects (if applicable). Any input device. All context and state information that
cannot be preserved by the device when it’s conserving power.
D2 N/A This state is not deﬁned for input devices, use D1 as the power management
state instead.

D3 Required Input device is off and not running. In general, the device is not delivering any
functionality to the user except wake functionality if applicable. Device context
and state information is lost.
A.7.2 Input Device Power Management Policy
Table A-15: Input Device Power Management Policy
Present
StateNext State Cause
D3 D0 Requested by the system
D0 D1/D3* Requested by the system (for example, system goes to sleep with wake enabled)
D0/D1 D3 Requested by the system (for example, system goes to sleep with wake disabled)
Power is removed
D1/D3 D0 Device with enabled wake capability requests transition by generating a wake
event Requested by the system
Note: This depends on whether the device features D1 or D3 wake capability or not; device will be put in the state
with the lowest possible power consumption.
A.7.3 Input Device Wake Events
It is recommended, but not required, that input devices implement and support bus-speciﬁc wake mechanisms if these
are deﬁned for their bus type. This is recommended because a user typically uses an input device of some kind to wake
the system when it is in a power management state (for example, when the system is sleeping).
The actual input data (particular button or key pressed) that’s associated with a wake event should never be discarded
by the device itself, but should always be passed along to the policy owner or other software for further interpretation.
This software implements a policy for how this input data should be interpreted, and decides what should be passed
along to higher-level software, and so on.
A.7. Input Device Class 1029Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
It is recommended that the device button(s) or key(s) used for power management purposes are clearly labeled with
text and/or icons. This is recommended for keyboards and other input devices on which all buttons or keys are typically
labeled with text and/or icons that identify their usage.
For example, a keyboard could include a special-purpose power management button (for example, “Power”) that,
when pressed during a system sleeping state, generates a wake event. Alternatively, the button(s) on mice and other
pointing devices could be used to trigger a wake event.
Examples of more advanced wake events include keyboard wake signaling when any key is pressed, mouse wake
signaling on detection of X/Y motion, joystick wake signaling on X/Y motion, and so on. However, in order to avoid
accidental or unintentional wake of the system, and to give the user some control over which input events will result in
a system wake, it’s suggested that more advanced types of wake events are implemented as features that can be turned
on or off by the user (for example, as part of the OSPM user interface).
A.7.4 Input Device Minimum Power Capabilities
An input device conforming to this speciﬁcation must support the D0 and D3 states. Support for the D1 state is
optional.
A.8 Modem Device Class
• The requirements expressed in this section apply to modems and similar devices, such as USB controlled ISDN
Terminal Adapters (“digital modems”) and computer-connected telephone devices (“CT phones”). This speciﬁ-
cation will refer to these devices as “modems; the same considerations apply to digital modems and CT phones
unless explicitly stated otherwise.
• The scope of this section is further restricted to modems that support power management using methods deﬁned
by the relevant PC-modem connection bus. These include PCI, USB, PCCARD (PCMCIA), CardBus, and
modems on the system motherboard described by ACPI system ﬁrmware control methods. The scope does not
include bus-speciﬁc means for devices to alert the host PC (for example, how to deliver a “ringing”’ message),
nor does it address how those alerting operations are controlled.
A.8.1 Technology Overview
Modems are traditionally serial devices, but today modems may be attached to a PC by many different means. Fur-
ther, many new modems expose a software serial interface, where the modem controller function is implemented in
software. This speciﬁcation addresses three different connection types:
• Traditional connections without power-managed connections (for example, COM, LPT, ISA)
• Power managed connections (for example, PCCARD, CardBus, PCI, USB)
• Motherboard modems
For some of the above modem connection types mentioned, there are three different modem architectures possible:
• Traditional modem (DAA, DSP, and controller in hardware)
• Controller-less design (DAA and DSP in hardware)
• “Soft modem” design (DAA and CODEC only in hardware)
The hardware components of the modem shall be controlled by the relevant bus commands, where applicable (USB,
PCI, CardBus). The software components are dependent on the power state of the CPU.
A.8. Modem Device Class 1030Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.8.1.1 Traditional Connections
In older methods (COM, LPT, ISA) the modem is controlled primarily by serialized ASCII command strings (for
example, V .25ter) and traditional V .24 (RS-232) out-of-band leads. In these legacy devices, there are no common
means for power management other than the power switch for the device, or the entire system unit.
An external modem connected to a COM port or LPT port typically has its own power supply. An LPT port modem
might run from the current on the LPT port +5V supply. For COM or LPT port modems, power is typically controlled
by a user switch.
The most common modem type is an ISA card with an embedded COM port. From a software standpoint, they are
logically identical to external modems, but the modems are powered by the PC system unit. Power is drawn from the
ISA bus without independent power switching.
A.8.1.2 Power-Managed Connections
PCMCIA, PCCARD and CardBus slots are powered and power-managed by the system, using means deﬁned in the
relevant bus speciﬁcations. For PCMCIA and PCCARD devices, only D0 and D3 states are available, via Socket
Services in the OS and/or ACPI system ﬁrmware. CardBus adds intermediate states, using the same mechanisms
deﬁned for PCI Bus.
PCI bus slots are powered and power-managed by the system, using means deﬁned in the PCI speciﬁcation.
USB devices may be powered by the USB itself (100mA or 500mA), or have their own external power supply. All
USB devices are power-managed by the USB bus master, using means deﬁned in the USB speciﬁcation.
A.8.1.3 Motherboard Modems
A modem embedded in the motherboard is powered by controls on the motherboard. It should be power-managed by
using control methods exposed via ACPI system ﬁrmware tables.
A.8.2 Modem Device Power State Deﬁnitions
Table A-16: Modem Device Power State Deﬁnitions
D0 Required Phone interface is on (may be on or off hook) Speaker is on Controller Context
is preserved
D1 N/A Not deﬁned (do not use)
D2 Optional Phone interface is not powered by the host (on hook) Speaker is off Controller
context is preserved 2 seconds maximum restore time
D3 Required Phone interface is not powered by host (on hook) Speaker is off Controller
context may be lost 5 seconds maximum restore time
A.8. Modem Device Class 1031Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.8.3 Modem Device Power Management Policy
Table A-17: Modem Device Power Management Policy
Present
D2/D3 D0 System issues a bus command to enter the D0 state (for example, an application
is answering or originating a call).
D0 D2 System issues a bus command to enter the D2 state. (for example, an application
is listening for an incoming call).
D0 D3 System issues a bus command to enter the D3 state (for example, all applications
have closed the Modem device).
A.8.4 Modem Device Wake Events
For any type of modem device, wake events (if supported and enabled) are only generated in response to detected
“ringing” from an incoming call. All other events associated with modems (V .8bis messages, and so on) require that
the PC be in the “working” state to capture them. The methods and signals used to generate the wake may vary as a
function of the modem connection (bus) type and modem architecture.
Machine wake is allowed from any modem power state (D0, D2, and D3), and is accomplished by methods described
in the appropriate bus power management speciﬁcation (PCI, USB, PCCARD), or by ACPI system board control
methods (for Modem on Motherboard implementations).
If the speciﬁc modem implementation or connection type does not enable it to assert system wake signaling, these
modems will not be able to wake the machine. The OS modem policy owner will have to retain the PC in the
“working” state to perform all types of event detection (including ringing).
A.8.5 Modem Device Minimum Power Capabilities
A modem or similar device conforming to this speciﬁcation must support the D0 and D3 states. Support of the D2
state is optional.
A.9 Network Device Class

The requirements expressed in this section apply to Ethernet and token ring adapters. ATM and ISDN adapters are not
supported by this speciﬁcation.
A.9.1 Network Device Power State Deﬁnitions
For the purpose of the following state deﬁnitions “no bus transmission” means that transmit requests from the host
processor are not honored, and “no bus reception” means that received data are not transferred to host memory.
Table A-18: Network Device Power State Deﬁnitions
A.9. Network Device Class 1032Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
D0 Required Device is on and running and is delivering full functionality and performance to
the user Device is fully compliant with the requirements of the attached network
D1 Optional No bus transmission allowed No bus reception allowed No interrupts can occur
Device context may be lost
D2 Optional No bus transmission allowed No bus reception allowed No interrupts can occur
D3 Required Device context is assumed to be lost No bus transmission allowed No bus re-
ception allowed No interrupts can occur
This document does not specify maximum power and maximum latency requirements for the sleeping states because
these numbers are very different for different network technologies. The device must meet the requirements of the bus
that it attaches to.
Although the descriptions of states D1 and D2 are the same, the choice of whether to implement D1 or D2 or both
may depend on bus services required, power requirements, or time required to restore the physical layer. For example,
a device designed for a particular bus might include state D1 because it needs a bus service such as a bus clock to
support Magic Packet™ wake, and that service is available in the bus device’s D1 power state but not in D2. Also, a
device might include both state D1 and state D2 to provide a choice between lower power and lower latency.
A.9.2 Network Device Power Management Policy
Table A-19: Network Device Power Management Policy
Present
D0 Dx System enters sleep state. If wake is enabled, Dx is the lowest power state (for
example, D1, D2, D3) from which the network device supports system wake.
An appropriate time-out has elapsed after a “link down” condition was detected.
Dx is the lowest power state in which the network device can detect “link up.”
D0 D3 System initiated network shutdown. System enters sleep state and wake is either
not enabled or the network device is capable of waking from D3.
D1/D2/D3 D0 System wake (transition to S0), including a wake caused by a network wake
event.
A.9.3 Network Device Wake Events
Network wake events are generally the result of either a change in the link status or the reception of a wake frame from
the network.
A.9.3.1 Link Status Events
Link status wake events are useful to indicate a change in the network’s availability, particularly when this change may
impact the level at which the system should re-enter the sleeping state. For example, a transition from “link off” to
“link on” may trigger the system to re-enter sleep at a higher level (for example, S2 versus S3) so that wake frames can
be detected. Conversely, a transition from “link on” to “link off” may trigger the system to re-enter sleep at a deeper
level (for example, S3 versus S2) since the network is not currently available. The network device should implement
an internal delay to avoid unnecessary transitions when the link status toggles on or off momentarily.
A.9. Network Device Class 1033Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.9.3.2 Wake Frame Events
Wake frame events are used to wake the system whenever meaningful data is presented to the system over the net-
work. Examples of meaningful data include the reception of a Magic Packet™, a management request from a remote
administrator, or simply network trafﬁc directly targeted to the local system. In all of these cases the network device
was pre-programmed by the policy owner or other software with information on how to identify wake frames from
other network trafﬁc. The details of how this information is passed between software and network device depend on
the OS and therefore are not described in this speciﬁcation.
A.9.4 Network Device Minimum Power Capabilities
A network device conforming to this speciﬁcation must support the D0 and D3 states. Support for the D1 and D2
states is optional.
A.10 PC Card Controller Device Class
The requirements expressed in this section apply to PC Card controller devices and the PC Card slots.
Power management of PC Cards is not deﬁned by this speciﬁcation. PC Card power management is deﬁned by the
relevant power management speciﬁcation for the card’s device class (for example, network, modem, and so on), in
conjunction with the PC Card standard (for 16-bit cards) or the PCI Power Management Speciﬁcation (for CardBus
cards).
A.10.1 PC Card Controller Device Power State Deﬁnitions
Table A-20: PC Card Controller Device Power State Deﬁnitions
A.10. PC Card Controller Device Class 1034Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
D0 Required Card status change interrupts are fully functional. Card functional interrupts
are fully functional. Controller context (for example, memory, I/O windows) is
fully functional. Controller interface is fully functional (processor can access
cards). Power to cards (slots) is available (may be on or off under software con-
trol). The controller is at its highest power consumption level. Bus command
response time is at its fastest level. PC Cards can be in any Dx power state (D0-
D3). Note: In D0 state, CSTSCHG interrupts can be passed to a system from
a powered down PC Card (for more detail, refer to section 5.2.11.2 of PC Card
Standard, Electrical Speciﬁcation).
D1 Optional Card status change interrupts are disabled. CSTSCHG interrupt events are still
detectable by the controller and cause the bus-speciﬁc wake signal to be as-
serted if wake is enabled on the controller. Card functional interrupts are dis-
abled. Controller context is preserved (all register contents must be maintained
but memory and I/O windows need not be functional). Controller interface is
non-functional (processor cannot access cards). Power to cards (slots) is avail-
able (may be on or off; retains power setting it had at time of entry to D1).
Power-level consumption for the controller is high but less than D0. The time
required to restore the function from the D1 state to the D0 state is quicker than
resumption from D3. Bus command response time is equal to or slower than in
D0. PC Cards can be in the D1, D2, or D3 power states (not D0). Note: In D1
state, CSTSCHG interrupts can be passed to a system from a powered-down PC
Card (for more detail, refer to section 5.2.11.2 of PC Card Standard, Electrical
Speciﬁcation).
D2 Optional Functionally the same as D1 (may be implemented instead of D1 in order to
allow bus and/or system to enter a lower-power state).
D3 Required Card status change interrupt: Disabled and need not be detected. Card func-
tional interrupt: Disabled and need not be detected. Controller context (for
example, memory, I/O windows): Lost. Controller interface: Non-functional
(processor can not access cards). Clock to controller: Off. Power to cards
(slots): Off (card context lost). Note: If Vcc is removed (for example, PCI Bus
B3) while the device is in the D3 state, a bus-speciﬁc reset (for example, PCI
RST#) must be asserted when power is restored and functions will then return
to the D0 state with a full power-on reset sequence. Whenever the transition
from D3 to D0 is initiated through assertion of a bus-speciﬁc reset, the power-
on defaults will be restored to the function by hardware just as at initial power
up. The function must then be fully initialized and reconﬁgured by software.
A.10.2 PC Card Controller Device Power Management Policy
The PC Card controller is a bus controller. As such, its power state is dependent on the devices plugged into the bus
(child devices). OSPM will track the state of all devices on the bus and will put the bus into the best possible power
state based on the current device requirements on that bus. For example, if the PC Card cards are all in the D1 state,
OSPM will put the PC Card controller in the D1 state.
Table A-21: PC Card Controller Device Power Management Policy
A.10. PC Card Controller Device Class 1035Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Present
D2/D3 D0 Any card in any slot needing to transition to state D0 due to a wake event or
because of system usage.
D0 D1 No card in any slot is in state D0.
D0 D2 No card in any slot is in state D0 or D1.
D0 D3 All cards in all slots are in state D3.
A.10.3 PC Card Controller Wake Events
A wake event is any event that would normally assert the controller’s status change interrupt (for example, card

Present
insertion, card battery state change, card ReqAttn event, and so on) or ring-indicate signal.
A.10.4 PC Card Controller Minimum Power Capabilities
A PC Card controller device conforming to this speciﬁcation must support the D0 and D3 states. Support for the D1
or D2 states is optional.
A.11 Storage Device Class
The requirements expressed in this section apply to ATA hard disks, ﬂoppy disks, ATAPI and SCSI CD-ROMs, and
A.11.1 Storage Device Power State Deﬁnitions
Table A-22: Hard Disk, CD-ROM and IDE/ATAPI Removable Storage Devices Power State Deﬁnitions
D0 Required Drive controller (for example, interface and control electronics) is functional.
Interface mode context (for example, communications timings) is programmed.
D1 Optional Drive controller (for example, interface and control electronics) is functional.
Interface mode context (for example, communications timings) is preserved.
Drive motor (for example, spindle) is stopped, with fast-start mode enabled, if
available. Laser (if any) is off. Recommended latency to return to D0 is less
than 5 seconds. Power consumption in D1 should be no more than 80% of
power consumed in D0. Note: For ATA devices, this state is invoked by the
Standby Immediate command.
D2 N/A This state is not deﬁned for storage devices.
D3 Required Drive controller (for example, interface and control electronics) is not func-
tional; context is lost. Interface mode (for example, communications timings)
is not preserved. Drive motor (for example, spindle) is stopped. Laser (if any)
is off. Power consumption in D3 is no more than 10% of power consumed in
D0. Note: For ATA devices, this state is invoked by the “sleep” command.
Table A-23: Floppy Disk Devices Power State Deﬁnitions
A.11. Storage Device Class 1036Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Drive motor (for example, spindle) is turning.
D1 N/A This state is not deﬁned for ﬂoppy disk drives.
D2 N/A This state is not deﬁned for ﬂoppy disk drives.
tional; context is lost. Drive motor (for example, spindle) is stopped.
Table A-24: IDE Channel Devices Power State Deﬁnitions
D0 Required Adapter is functional. Adapter interface mode (for example, communications
timings) is programmed. Power is applied to the bus (and all devices connected
to it).
D1 N/A This state is not deﬁned for the IDE Channel.
D2 N/A This state is not deﬁned for the IDE Channel.
D3 Required Adapter is non-functional. Adapter interface mode (for example, communica-
tions timings) is not preserved. Power to the bus (and all devices connected to
it) may be off.
A.11.2 Storage Device Power Management Policy
Table A-25: Hard Disk, Floppy Disk, CD-ROM and IDE/ATAPI Removable Storage Devices Power Manage-
ment Policy
Present
D3 D0 Device usage (high-priority I/O).
D0 D1* Device inactivity (no high-priority I/O) for some period of time (T1).
D0 D3 Device inactivity (no high-priority I/O) for a period of time (T2=>T1). System
enters sleeping state.
D1 (if sup-
ported)D0 Device usage (High-priority I/O).
Note: For ATA, the D3-to-D0 transition requires a reset of the IDE channel. This means that both devices on a
channel must be placed into D3 at the same time.
Table A-26: IDE Channel Devices Power Management Policy
Present
D3 D0 Any device on the channel needing to transition to a state other than state D3.
D0 D3 All devices on the channel in state D3.
A.11. Storage Device Class 1037Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A.11.3 Storage Device Wake Events
Storage devices with removable media can, optionally, signal wake upon insertion of media using their bus-speciﬁc
notiﬁcation mechanism. There are no other wake events deﬁned for Storage devices.
A.11.4 Storage Device Minimum Power Capabilities
A hard disk, CD-ROM or IDE/ATAPI removable storage device conforming to this speciﬁcation must support the D0
and D3 states. Support for the D1 state is optional.
A ﬂoppy disk and IDE channel device conforming to this speciﬁcation must support the D0 and D3 states.
A.11. Storage Device Class 1038APPENDIX
B
APPENDIX B: VIDEO EXTENSIONS
B.1 ACPI Extensions for Display Adapters: Introduction
This section of the document describes a number of specialized ACPI methods to support motherboard graphics
devices.
In many cases, system manufacturers need to add special support to handle multiple output devices such as panels and
TV-out capabilities, as well as special power management features. This is particularly true for notebook manufac-
turers. The methods described here have been designed to enable interaction between the platform ﬁrmware, video
driver, and OS to smoothly support these features.
Systems containing a built-in display adapter are required to implement the ACPI Extensions for Display Adapters.
Table B-1: Video Extension Object Requirements
Method Description Requirement
_DOS Enable/Disable output switch-
ingRequired if system supports display switching or LCD brightness
levels
_DOD Enumerate all devices attached
to display adapterRequired if integrated controller supports output switching
_ROM Get ROM Data Required if ROM image is stored in proprietary format
_GPD Get POST Device Required if _VPO is implemented
_SPD Set POST Device Required if _VPO is implemented
_VPO Video POST Options Required if system supports changing post VGA device
_ADR Return the unique ID for this de-
viceRequired
_BCL Query list of brightness control
levels supportedRequired if embedded LCD supports brightness control
_BCM Set the brightness level Required if _BCL is implemented
_DDC Return the EDID for this device Required if embedded LCD does not support return of EDID via
standard interface
_DCS Return status of output device Required if the system supports display switching (via hotkey)
_DGS Query graphics state Required if the system supports display switching (via hotkey
_DSS Device state set Required if the system supports display switching (via hotkey).
1039Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
B.2 Video Extension Deﬁnitions
Built-in display adapter This is a graphics chip that is built into the motherboard and cannot be replaced. ACPI
information is valid for such built-in devices.
Add-in display adapter This is a graphics chip or board that can be added to or removed from the computer. Because
the platform ﬁrmware cannot have speciﬁc knowledge of add-in boards, ACPI information is not available for
Boot-up display adapter This is the display adapter programmed by the platform boot ﬁrmware during machine
power-on self-test (POST). It is the device upon which the machine will show the initial operating system boot
screen, as well as any platform boot ﬁrmware messages.
The system can change the boot-up display adapter, and it can switch between the built-in adapter and the add-in
adapter.
Display device This is a synonym for the term display adapter discussed above.
Output device This is a device, which is a recipient of the output of a display device. For example, a CRT or a TV is
an output device.
B.3 ACPI Namespace
This is an example of the display-related namespace on an ACPI system:
GPE // ACPI General-purpose HW event
_L0x // Notify(VGA, 0x80) to tell OSPM of the event, when user presses
// the hot key to switch the output status of the monitor.
// Notify(VGA, 0x81) to tell the event to OSPM, when there are any
// changes on the sub-devices for the VGA controller
SB
|- PCI
|- VGA // Define the VGA controller in the namespace
|- \_PS0 / PR0
|- \_PS1 / PR1
|- \_PS3
|- \_DOS // Method to control display output switching
|- \_DOD // Method to retrieve information about child output devices
|- \_ROM // Method to retrieve the ROM image for this device
|- \_GPD // Method for determining which VGA device will post
|- \_SPD // Method for controlling which VGA device will post
|- \_VPO // Method for determining the post options
|- CRT // Child device CRT
|- \_ADR // Hardware ID for this device
|- \_DDC // Get EDID information from the monitor device
|- \_DCS // Get current hardware status
|- \_DGS // Query desired hardware active \ inactive state
|- \_DSS // Set hardware active \ inactive state
|- \_PS0 \
|- \_PS1 - Power methods
|- \_PS2 - for the output device
|- \_PS3 /
|- LCD // Child device LCD
B.2. Video Extension Deﬁnitions 1040Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
|- \_BCL // Brightness control levels
|- \_BCM // Brightness control method

|- \_PS0 \
|- \_PS3 /
|- \_BQC // Brightness Query Current Level
|- \_PS0 \
|- \_PS3 /
|- TV // Child Device TV
The LCD device represents the built-in output device. Mobile PCs will always have a built-in LCD display, but desktop
systems that have a built-in graphics adapter generally don’t have a built-in output device.
B.4 Display-speciﬁc Methods
The methods described in this section are all associated with speciﬁc display devices. This device-speciﬁc association
is represented in the namespace example in the previous section by the positioning of these methods in a device tree.
B.4.1 _DOS (Enable/Disable Output Switching)
Many ACPI machines currently reprogram the active display output automatically when the user presses the display
toggle switch on the keyboard. This is done because most video device drivers are currently not capable of being
notiﬁed synchronously of such state changes. However, this behavior violates the ACPI speciﬁcation, because the
system modiﬁes some graphics device registers.
The existence of the _DOS method indicates that the platform runtime ﬁrmware is capable of automatically switching
the active display output or controlling the brightness of the LCD. If it exists at all, the _DOS method must be present
for all display output devices. This method is required if the system supports display switching or LCD brightness
control.
Arg0 - An Integer containing the encoded switching controls (see below)
None
Additional Argument Information:
Bits [1:0]:
0 - The platform runtime firmware should not automatically switch
(toggle) the active display output, but instead just save the desired
state change for the display output devices in variables associated with
each display output, and generate the display switch event. OSPM can
query these state changes by calling the \_DGS method.
B.4. Display-speciﬁc Methods 1041Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
1 - The platform runtime firmware should automatically switch (toggle)
the active display output, with no interaction required on the OS part.
The display switch event should not be generated in this case.
2 - The \_DGS values should be locked. It's highly recommended that the
platform runtime firmware do nothing when hotkey pressed. No switch, no
notification.
3 - The platform runtime firmware should not automatically switch
(toggle) the active display output, but instead generate the display
switch event notify codes 0x82, 0x83, or 0x84. OSPM will determine what
display output state should be set, and change the display output state
without further involvement from the platform runtime firmware.
Bit [2]:
0 - The platform runtime firmware should automatically control the
brightness level of the LCD when the power changes from AC to DC.
1 - The platform runtime firmware should not automatically control the
The _DOS method controls this automatic switching behavior. This method should do so by saving the parameter
passed to this method in a global variable somewhere in the platform runtime ﬁrmware data segment. The platform
runtime ﬁrmware then checks the value of this variable when doing display switching. This method is also used to
control the generation of the display switching Notify (VGA, 0x80/0x81) .
The platform runtime ﬁrmware, when doing switching of the active display, must verify the state of the variable set by
the _DOS method. The default value of this variable must be 1.
B.4.2 _DOD (Enumerate All Devices Attached to the Display Adapter)
This method is used to enumerate devices attached to the display adapter. This method is required if integrated
controller supports output switching.
On many laptops today, a number of devices can be connected to the graphics adapter in the machine. These devices
are on the motherboard and generally are not directly enumerable by the video driver; for this reason, all motherboard
VGA attached devices are listed in the ACPI namespace.
These devices fall into two categories:
•Video output devices . For example, a machine with a single display device on the motherboard can have three
possible output devices attached to it, such as a TV , a CRT, or a panel.
•Non-video output devices . For example, TV Tuner, DVD decoder, Video Capture. They just attach to VGA
and their power management closely relates to VGA.
Both ACPI and the video driver have the ability to program and conﬁgure output devices. This means that both
ACPI and the video driver must enumerate the devices using the same IDs. To solve this problem, the _DOD method
returns a list of devices attached to the graphics adapter, along with device-speciﬁc conﬁguration information. This
information will allow the cooperation between ACPI components and the video driver.
Every child device enumerated in the ACPI namespace under the graphics adapter must be speciﬁed in this list of
devices. Each display device must have its own ID, which is unique with respect to any other attachable devices
enumerated.
B.4. Display-speciﬁc Methods 1042Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
None
APackage containing a variable-length list of Integers , each of which contains the 32-bit device attribute
of a child device (See Table B-2 below).
Example
Method (_DOD, 0) {
Return (
Package()
{
0x00000110, // Primary LCD panel, not detectable by firmware
0x80000100, // CRT type display, not detectable by firmware
0x80000220, // TV type display, not detectable by the firmware
0x80000411, // Secondary LCD panel, not detectable by firmware
}
)
}
Table B-2: Video Output Device Attributes
15:0
Device ID . The device ID must match the ID’s speciﬁed by Video Chip Vendors. They must also
be unique under VGA namespace:
Bits [3:0] Display Index : A zero-based instance of the Display, when multiple displays of the
same type are attached, regardless of where it is associated. Starting from the ﬁrst adapter and its
ﬁrst display of the type on the ﬁrst integrated internal device and then incrementing per
device-function according to its relative port number.
Bits [7:4] Display Port Attachment : This ﬁeld differentiates displays of the same type attached
at different points of one adapter. The zero-based number scheme is speciﬁc to each Video Chip
Vendors’ implementation.
Bits [11:8] Display Type : Decribes the speciﬁc type of Display Technology in use.
0 – Other
1 – VGA* CRT or VESA* Compatible Analog Monitor
2 – TV/HDTV or other Analog-Video Monitor
3 – External Digital Monitor (see note 1)
4 – Internal/Integrated Digital Flat Panel (see note 2)
5-15 – Reserved for future use
Bits [15:12] Chipset-vendor speciﬁc
16 Platform boot ﬁrmware can detect the device.
17 Non-VGA output device whose power is related to the VGA device. This can be used when
specifying devices like TV Tuner, DVD decoder, Video Capture . . . etc.
20:18 For VGA multiple-head devices, this speciﬁes head or pipe ID e.g. for Dual-Pipe*, Dual-
Display*, Duo-View*, TwinView*, Triple-View* . . . etc, beginning with 0 for head 0 or single-
head device and increasing for each additional head.
30:21 Reserved (must be 0)
B.4. Display-speciﬁc Methods 1043Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
31
Device ID Scheme:
1 - Uses the bit-ﬁeld deﬁnitions above (bits 15:0)
0 - Other scheme, contact the Video Chip Vendor
Note: 1: An “External Digital Monitor” is an external display device attachable via a user-accessible connector
standard (e.g. DFP* or DVI* Compatible Monitors).
2: An “Internal Flat Panel” is a non-detachable ﬁxed pixel display device, including a backlight, and is internally
associated, without user-accessible connectors, to the Video Chip (e.g. TFT LCD via TMDS*, LVDS* interface).
As mentioned in the above table, a “Pipe” or “Head” refers to a unique display content stream e.g. at a particular
color-depth, resolution, and refresh-rate. The “Port” refers to the display output device attachment and may include a
DAC, encoder or other mechanism required to support a given display end-point. The “Display Type” describes the
generalized class of display output technology, and the means of integration. The “Display Index” is then an index
that assists in creating a unique identiﬁer display end-points in scenarios where other attributes are the same.
Fig. B-1: Example Display Architecture
B.4. Display-speciﬁc Methods 1044Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Table B-3: Example Device IDs

0x000xyyyy Bit [31] = 0. Other proprietary scheme - 0x110 Device ID is an exception (see note 3)
0x00000110 Integrated LCD Panel #1 using a common, backwards compatible ID
0x80000100 Integrated VGA CRT or VESA compatible Monitor #1 on Port0
0x80000240 Integrated TV #1 on Port4
0x80000410 Integrated Internal LCD Panel #1 on Port1
0x80000421 LVDS Panel #2 Dual-Link using Port2 & 3 (see note 4)
0x80000131 VGA CRT or VESA compatible Monitor #2 on Port3
0x80000121 Dual-Link VGA CRT or VESA compatible Monitor #2 using Port2 & 3 (see note 4)
0x80000320 DVI Monitor #1 on Port2 (shares Port2 with a Dual-Function DVI/TV Encoder) (see note
5)
0x80000331 DVI Monitor #2 on Port3
0x80000330 Dual-Link DVI Monitor #1 using Port2 & 3
0x80000231 TV #2 on Port2 (shares Port2 with a Dual-Function DVI/TV Encoder) (see note 5)
Note: 3: When Bit [31] is 0, no assumptions can be made on which ID will be used for any particular display type.
Contact the Video Chip vendor for details of the ID scheme employed.
4: In certain cases multiple Displays Ports may be combined to increase bandwidth for a particular Display in higher-
resolution modes. In this situation, the Display Type and Port Number should remain the same in order to retain a
consistent ID for the same device, regardless of the selected display mode.
5: In certain cases, more than one type of display (and connector) may be supportable on a single Port (e.g. DVI +
TV + CRT on a single Display Encoder device), while only one display is selectable at any time. In this case, the Port
Number ﬁeld of the ID may be the same as other Display IDs, however the other ﬁelds (e.g. Display Type) provide
uniqueness.
B.4.3 _ROM (Get ROM Data)
This method is used to get a copy of the display devices’ ROM data. This method is required when the ROM image is
stored in a proprietary format such as stored in the platform ﬁrmware ROM. This method is not necessary if the ROM
image can be read through a standard PCI interface (using ROM BAR). If _ROM is present, it is preferred over the
image read through the standard PCI interface, in order to allow platform runtime ﬁrmware to provide re-conﬁgured
ROM data via the method.
The video driver can use the data returned by this method to program the device. The format of the data returned by
this function is a large linear buffer limited to 4 KB. The content of the buffer is deﬁned by the graphics independent
hardware vendor (IHV) that builds this device. The format of this ROM data will traditionally be compatible with the
ROM format of the normal PCI video card, which will allow the video driver to program its device, independently of
motherboard versus add-in card issues.
The data returned by the _ROM method is implementation-speciﬁc data that the video driver needs to program the
device. This method is deﬁned to provide this data as motherboard devices typically don’t have a dedicated option
ROM. This method will allow a video driver to get the key implementation speciﬁc data it needs so that it can fully
control and program the device without platform runtime ﬁrmware support.
Arg0 - An Integer containing the offset of the display device ROM data
Arg1 - An Integer containing the size of the buffer to ﬁll in (up to 4K).
B.4. Display-speciﬁc Methods 1045Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
A Buffer containing the requested ROM data
B.4.4 _GPD (Get POST Device)
This method is required if the _VPO method is implemented.
This method is used as a mechanism for the OS to query a CMOS value that determines which VGA device will be
posted at boot. A zero return value indicates the motherboard VGA will be posted on the next boot, a 1 indicates a
PCI VGA device will be posted, and a 2 indicates an AGP VGA device will be posted.
None
AnInteger containing encoded post information (32 bits valid):
Bits [1:0]
00 - Post the motherboard VGA device
01 - Post an add-in PCI VGA device
10 - Post an add-in AGP VGA device
11 - Post an add-in PCI-Express VGA device
Bits [31:2] - Reserved (must be 0)
B.4.5 _SPD (Set POST Device)
This method is used as a mechanism for the OS to update a CMOS value that determines which video device will be
posted at boot. A zero argument will cause the “motherboard” to be posted on the next boot, a 1 will cause an add-in
PCI device to be posted, and a 2 will cause an add-in AGP device to be posted.
Arg0 - An Integer containing encode post information (32 bits valid):
Bits [1:0]
AnInteger containing the status of the operation:
0 - Operation was successful
Non-zero - Operation failed
Example :
Method (_SPD, 1) { // Make the motherboard device the device to post }
B.4. Display-speciﬁc Methods 1046Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
B.4.6 _VPO (Video POST Options)
This method is required for systems with video devices built onto the motherboard and support changing post-VGA
device.
This method is used as a mechanism for the OS to determine what options are implemented. This method will be used
in conjunction with _GPD and _SPD.
None
AnInteger containing the options that are implemented and available:
Bit [0] - Posting the motherboard VGA device is an option.
(Bit [0] should always be set)
Bit [1] - Posting a PCI VGA device is an option.
Bit [2] - Posting an AGP VGA device is an option.
Bit [3] - Posting a PCI-Express VGA device is an option.
Bits [31:4] - Reserved (must be zero)
B.5 Notiﬁcations for Display Devices
Display devices may need to know about external, asynchronous events. In order to accommodate that, the following
notiﬁcations are deﬁned.
The event number is standardized because the event will be handled by the OS directly under certain circumstances
(see _DOS method in this speciﬁcation).
These notiﬁcations are valid for Display Devices
Table B-4: Notiﬁcations for Display Devices
0x80 Cycle Output Device. Used to notify OSPM whenever the state of one of the output devices
attached to the VGA controller has been switched or toggled. This event will, for example, be
generated when the user presses a hotkey to switch the active display output from the LCD panel
to the CRT.
0x81 Output Device Status Change. Used to notify OSPM whenever the state of any output devices
attached to the VGA controller has been changed. This event will, for example, be generated when
the user plugs-in or remove a CRT from the VGA port. In this case, OSPM will re-enumerate all
devices attached to VGA
0x82 Cycle Display Output Hotkey Pressed. Used to notify OSPM whenever the user has pressed the
Cycle display hotkey.
0x83 Next Display Output Hotkey Pressed. Used to notify OSPM whenever the user has pressed the
Next display hotkey.
0x84 Previous Display Output Hotkey Pressed. Used to notify OSPM whenever the user has pressed
the Previous display hotkey.
B.5. Notiﬁcations for Display Devices 1047Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
B.6 Output Device-speciﬁc Methods
The methods in this section are methods associated with the display output device.
B.6.1 _ADR (Return the Unique ID for this Device)
This method returns a unique ID representing the display output device. All output devices must have a unique
hardware ID. This method is required for all The IDs returned by this method will appear in the list of hardware IDs
returned by the _DOD method.
None
An Integer containing the device ID (32 bits)
Example :
Method (_ADR, 0) {
return(0x0100) // device ID for this CRT
}
This method is required for all output display devices.
B.6.2 _BCL (Query List of Brightness Control Levels Supported)
This method allows the OS to query a list of brightness level supported by built-in display output devices. (This
method in not allowed for externally connected displays.) This method is required if an integrated LCD is present and
supports brightness levels.
Each brightness level is represented by a number between 0 and 100, and can be thought of as a percentage. For
example, 50 can be 50% power consumption or 50% brightness, as deﬁned by the OEM.
The OEM may deﬁne the number 0 as “Zero brightness” that can mean to turn off the lighting (e.g. LCD panel
backlight) in the device. This may be useful in the case of an output device that can still be viewed using only ambient
light, for example, a transﬂective LCD. If Notify(Output Device, 0x85) for “Zero brightness” is issued, OSPM may be
able to turn off the lighting by calling _BCM(0).
None
A variable-length Package containing a list of Integers representing the the supported brightness levels.

None
Each integer has 8 bits of signiﬁcant data.
Example :
Method (_BCL, 0) {
// List of supported brightness levels
Return (Package(7){
80, // level when machine has full power
50, // level when machine is on batteries
// other supported levels:
20, 40, 60, 80, 100}
}
B.6. Output Device-speciﬁc Methods 1048Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
The ﬁrst number in the package is the level of the panel when full power is connected to the machine. The second
number in the package is the level of the panel when the machine is on batteries. All other numbers are treated as a
list of levels OSPM will cycle through when the user toggles (via a keystroke) the brightness level of the display.
These levels will be set using the _BCM method described in the following section.
B.6.3 _BCM (Set the Brightness Level)
This method allows OSPM to set the brightness level of a built-in display output device.
The OS will only set levels that were reported via the _BCL method. This method is required if _BCL is implemented.
Arg0 - An Integer containing the new brightness level
None
Example :
Method (_BCM, 1) { // Set the requested level }
The method will be called in response to a power source change or at the speciﬁc request of the end user, for example,
when the user presses a function key that represents brightness control.
B.6.4 _BQC (Brightness Query Current level)
This optional method returns the current brightness level of a built-in display output device. If present, it must be set
by the platform for initial brightness.
None
AnInteger containing the current brightness level (must be one of the values returned from the _BCL
method)
B.6.5 _DDC (Return the EDID for this Device)
This method returns an EDID (Extended Display Identiﬁcation Data) structure that represents the display output
device. This method is required for integrated LCDs that do not have another standard mechanism for returning EDID
data.
Arg0 - An Integer containing a code for the return data length:
1 - Return 128 bytes of data
2 - Return 256 bytes of data
3 - Return 384 bytes of data
4 - Return 512 bytes of data
B.6. Output Device-speciﬁc Methods 1049Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Either a Buffer containing the requested data (of the length speciﬁed in Arg0), or an Integer (value 0) if
Arg0 was invalid
Example :
Method (_DDC, 2) {
(LEqual (Arg0, 1)) { Return (Buffer(128){ ,,,, }) }
If (LEqual (Arg0, 2)) { Return (Buffer(256){ ,,,, }) }
Return (0)
}
The buffer will later be interpreted as an EDID data block. The format of this data is deﬁned by the VESA EDID
B.6.6 _DCS (Return the Status of Output Device)
This method is required if hotkey display switching is supported.
None
AnInteger containing the device status (32 bits) (see Table B-5 below).
Table B-5: Output Device Status
0 Output connector exists in the system now
1 Output is activated
2 Output is ready to switch
3 Output is not defective (it is functioning properly)
4 Device is attached (this is optional)
31:5 Reserved (must be zero)
Example:
• If the output signal is activated by _DSS, _DCS returns 0x1F or 0x0F.
• If the output signal is inactivated by _DSS, _DCS returns 0x1D or 0x0D.
• If the device is not attached or cannot be detected, _DCS returns 0x0xxxx and should return 0x1xxxx if it is
attached.
• If the output signal cannot be activated, _ DCS returns 0x1B or 0x0B.
• If the output connector does not exist (when undocked), _DCS returns 0x00.
B.6. Output Device-speciﬁc Methods 1050Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
B.6.7 _DGS (Query Graphics State)
This method is used to query the state (active or inactive) of the output device. This method is required if hotkey
display switching is supported.
None
AnInteger containing the device state (32 bits) (see Table B-6 below)
Table B-6: Device State for _DGS
0 0 - Next desired state is inactive / 1 - Next desired state is active
31:1 Reserved (must be zero)
The desired state represents what the user wants to activate or deactivate, based on the special function keys the user
pressed. OSPM will query the desired state when it receives the display toggle event (described earlier).
B.6.8 _DSS (Device Set State)
OSPM will call this method when it determines the outputs can be activated or deactivated. OSPM will manage this
to avoid ﬂickering as much as possible. This method is required if hotkey display switching is supported.
Arg0 - An Integer containing the new device state (32 bits) (see Table B-7 below)
None
Table B-7: Device State for _DSS
0 0 - Set output device to inactive state 1 - Set output device to active state
30 0 - Do whatever Bit [31] requires 1 - Don’t do actual switching, but need to change _DGS
to next state
31 0 - Don’t do actual switching, just cache the change
1 - If Bit [30] = 0, commit actual switching, including any _DSS with MSB=0 called before
If Bit [30] = 1, don’t do actual switching, change _DGS to next state
29:1 Reserved (must be zero)
Example Usage:
OS may call in such an order to turn off CRT, and turn on LCD:
CRT._DSS(0);
LCD._DSS(80000001L);
or:
LCD._DSS(1);
CRT._DSS(80000000L);
B.6. Output Device-speciﬁc Methods 1051Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
OS may call in such an order to force platform runtime ﬁrmware to make _DGS jump to next state without actual CRT,
LCD switching:
CRT._DSS(40000000L);
LCD._DSS(C0000001L);
B.7 Notiﬁcations Speciﬁc to Output Devices
Output devices may need to know about external, asynchronous events. In order, each of these events corresponds to
accommodate that, pressing a key or button on the following machine. Using these notiﬁcations is not appropriate if
no physical device exists that is associated with them. OSPM may ignore any of these notiﬁcations if, for example the
current user does not have permission to change the state of the output device. These notiﬁcations are only valid for
Output Devices.
Table B-8: Notiﬁcation Values for Output Devices
0x85 Cycle Brightness. Used to notify OSPM that the output device brightness should be increased
by one level. Used to notify OSPM that the user pressed a button or key that is associated with
cycling brightness. A useful response by OSPM would be to increase output device brightness
by one or more levels. (Levels are deﬁned in _BCL.) If the brightness level is currently at the
maximum value, it should be set to the minimum level.
0x86 Increase Brightness. Used to notify OSPM that the output device brightness should be increased
by one or more levels as deﬁned by the _BCL object. Used to notify OSPM that the user pressed
a button or key that is associated with increasing brightness. If the brightness level is currently at
the maximum value, OSPM may should ignore the notiﬁcation.
0x87 Decrease Brightness. Used to notify OSPM that the output device brightness should be decreased
a button or key that is associated with decreasing device brightness. If the brightness level is
currently at the minimum value, OSPM may should ignore the notiﬁcation.
0x88 Zero Brightness. Used to notify OSPM that the output device brightness should be zeroed, effec-
tively turning off any lighting that is associated with the device. Used to notify OSPM that the
user pressed a button or key associated with zeroing device brightness. This is not to be confused
with putting the device in a D3 state. While the brightness may be decreased to zero, the device
may still be displaying, using only ambient light.
0x89 Display Device Off. Used to notify OSPM that the device should be put in an off state, one that
is not active or visible to the user, usually D3, but possibly D1 or D2. Used to notify OSPM
that the user pressed a low power button or key associated with putting the device in an off state.
There is no need for a corresponding “device on” notiﬁcation, for two reasons. First, OSPM may
choose to toggle device state when this event is pressed multiple times. Second, OSPM may (and
probably will) choose to turn the monitor on whenever the user types on the keyboard, moves the
mouse, or otherwise indicates that he or she is attempting to interact with the machine.
B.7. Notiﬁcations Speciﬁc to Output Devices 1052Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
B.8 Notes on State Changes
It is possible to have any number of simultaneous active output devices. It is possible to have 0, 1, 2 . . . and so on active
output devices. For example, it is possible for both the LCD device and the CRT device to be active simultaneously.

It is also possible for all display outputs devices to be inactive (this could happen in a system where multiple graphics
cards are present).
The state of the output device is separate from the power state of the device. The “active” state represents whether the
image being generated by the graphics adapter would be sent to this particular output device. A device can be powered
off or in a low-power mode but still be the active output device. A device can also be in an off state but still be powered
on.
Example of the display-switching mechanism:
The laptop has three output devices on the VGA adapter. At this moment in time, the panel and the TV are both
active, while the CRT is inactive. The automatic display-switching capability has been disabled by OSPM by calling
_DOS(0), represented by global variable display_switching = 0.
The platform runtime ﬁrmware, in order to track the state of these devices, will have three global variable to track the
state of these devices. There are currently initialized to:
crt_active - 0 panel_active - 1 tv_active - 1
The user now presses the display toggle switch, which would switch the TV output to the CRT.
The platform runtime ﬁrmware ﬁrst updates three temporary variables representing the desired state of output devices:
want_crt_active - 1 want_panel_active - 1 want_tv_active - 0
Then the platform runtime ﬁrmware checks the display_switching variable. Because this variable is set to zero, the
platform runtime ﬁrmware does not do any device reprogramming, but instead generates a Notify (VGA, 0x80/0x81)
event for the display. This event will be sent to OSPM.
OSPM will call the _DGS method for each enumerated output device to determine which devices should now be
active. OSPM will determine whether this is possible, and will reconﬁgure the internal data structure of the OS to
represent this state change. The graphics modes will be recomputed and reset.
Finally, OSPM will call the _DSS method for each output device it has reconﬁgured.
Note: OSPM may not have called the _DSS routines with the same values and the _DGS routines returned, because
the user may be overriding the default behavior of the hardware-switching driver or operating system-provided UI.
The data returned by the _DGS method (the want_XXX values) are only a hint to the OS as to what should happen
with the output devices.
If the display-switching variable is set to 1, then the platform runtime ﬁrmware would not send the event, but instead
would automatically reprogram the devices to switch outputs. Any legacy display notiﬁcation mechanism could also
be performed at this time.
B.8. Notes on State Changes 1053APPENDIX
C
APPENDIX C: DEPRECATED CONTENT
This section lists content (if any) that is being deprecated from the ACPI speciﬁcation in this release.
Section 8.4: Declaring Processors
In the ﬁrst paragraph of this section, removed the following text:
Declaration of processors in the \_PR scope was only required for platforms desiring compatibility with ACPI 1.0-
based OSPM implementations. It is deprecated for all other uses. Processors are declared via the ASL Device state-
ment. Declarations via the ASL Processor statement are deprecated.
Section 9.4: Battery Device
A battery device is required to either have an ACPI Smart Battery Table or a Control Method Battery interface. In the
case of an ACPI Smart Battery Table, the Deﬁnition Block needs to include a Bus/Device Package for the SMBus host
controller. This will install an OS speciﬁc driver for the SMBus, which in turn will locate the Smart Battery System
Manager or Smart Battery Selector and Smart Battery Charger SMBus devices.
The Control Method Battery interface is deﬁned in Section 10.2.
Section 9.7: Embedded Controller Device
Operation of the embedded controller host controller register interface requires that the embedded controller driver has
ACPI-speciﬁc knowledge. Speciﬁcally, the driver needs to provide an “operational region” of its embedded controller
address space, and needs to use an ACPI event to service the host controller interface. For more information, see
Section 12.
The embedded controller device object provides the _HID of an ACPI-integrated embedded controller device of
PNP0C09 and the host controller register locations using the device standard methods. In addition, the embedded
controller must be declared as a named device object that includes a set of control methods. For more information, see
Section 12.11.
Section 8.4.1 _PDC (Processor Driver Capabilities)
The use of _PDC is deprecated in ACPI 3.0 in favor of _OSC. For backwards compatibility, _PDC may be implemented
using _OSC as follows:
1054Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Method(_PDC,1)
{
CreateDWordField (Arg0, 0, REVS)
CreateDWordField (Arg0, 4, SIZE)
//
// Local0 = Number of bytes forArg0
//
Store (SizeOf (Arg0), Local0)
//
// Local1 = Number of Capabilities bytes inArg0
//
Store (Subtract (Local0, 8), Local1)
//
// TEMP = Temporary field holding Capability DWORDs
//
CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)
//
// Create the Status (STS0) buffer withthe first DWORD = 0
// This isrequired to returnerrors defined by \_OSC.
//
Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})
//
// Concatenate the \_PDC capabilities bytes to the STS0 Buffer
//andstore them ina local variable forcalling OSC
//
Concatenate (STS0, TEMP, Local2)
//
// Note: The UUID passed into \_OSC isCPU vendor specific. Consult CPU
// vendor documentation forUUID andCapabilities Buffer bit
definitions
//
\_OSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE,
Local2)
}
_OSC (Operating System Capabilities) describes the _OSC object that can be used to convey processor related OSPM
capabilities to the platform. Consult vendor-speciﬁc CPU documentation for the UUID and Capabilities Buffer bit
deﬁnitions used by _OSC for a speciﬁc processor.
DESCRIPTION_HEADER Signatures for tables reserved by ACPI
• –“CDIT”
– Component Distance Information Table . See Links to ACPI-Related Documents under the heading
“Component Distance Information Table”.
• –“CRAT”
– Component Resource Attribute Table . See Links to ACPI-Related Documents under the heading “Com-
ponent Resource Attribute Table”.
1055INDEX
A
ACPI Hardware ,15
ACPI Machine Language (AML ),15
ACPI Namespace ,15
ACPI Non-Volatile-Sleeping Memory
(NVS). ,773
ACPI Reclaim Memory. ,773
ACPI registers. ,771
ACPI Source Language (ASL),15
Add-in Card ,15
Add-in display adapter ,1040
Address Range Scrub (ARS),16
Advanced Configuration and Power
Interface (ACPI ),15
Advanced Programmable Interrupt
Controller (APIC ),15
Appliance PC ,119
B
Battery management ,26
BIOS ,16
Boot Firmware ,16
Boot-up display adapter ,1040
Built-in display adapter ,1040
C
C0 Processor Power State ,25
C1 Processor Power State ,25
C2 Processor Power State ,25
C3 Processor Power State ,25
Cache memory configuration. ,771
Central Processing Unit (CPU) or
Processor ,16
Component ,16
Configuration / Plug and Play ,26
Control Method ,16
CPU configuration. ,771
D
D0(Fully-On ),23
D1,23
D2,23D3(Off),23
D3hot ,23
Desktop ,118
Device ,16
Device and processor performance
management ,26
Device Context ,16
Device Firmware ,16
Device Physical Address (DPA),16
Device power management ,26
Differentiated System Description
Table (DSDT ),16
Display device ,1040
E
Embedded Controller ,17
Embedded Controller Interface ,17
Emulation mode ,559
Enterprise Server ,119
Expansion ROM Firmware ,17
eXtended Root System Description Table
(XSDT ),21
F
Firmware ,17
Firmware ACPI Control Structure (FACS ),
17
Firmware Storage Device ,17
Fixed ACPI Description Table (FADT ),17
Fixed Feature Events ,17
Fixed Feature Registers ,17
Fixed Features ,17
Functional device configuration. ,771
G
G0 Working ,22
G1 Sleeping ,22
G2/S5 Soft Off ,21
G3 Mechanical Off ,21
General-Purpose Event Registers ,17
Generic Feature ,17
Generic Interrupt Controller (GIC),17
1056Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
Global System Status ,18
H
HBA,558
Host Processor ,18
Host Processor Boot Firmware ,18
Host Processor Runtime Firmware ,18
Hybrid Device ,559
I
I/O APIC ,18
I/O SAPIC ,18
Ignored Bits ,18
Intel Architecture-Personal Computer
(IA-PC ),18
L
Label Storage Area ,18
Legacy ,18
Legacy BIOS ,18
Legacy Hardware ,18
Legacy OS ,18
Local APIC ,18
Local SAPIC ,18
M
Management Firmware ,18
Memory controller configuration. ,771
Mobile ,118
Multiple APIC Description Table (MADT ),
19
N
Namespace ,19
Native mode ,559
Native SATA aware ,558
Non-Host Processor ,19
Non-native SATA aware ,558
NVDIMM ,19
O
Object ,19
Object name ,19
Operating System-directed Power
Management (OSPM ),19
Option ROM Firmware ,19
Output device ,1040
P
P0 Performance State ,25
P1 Performance State ,25
Package ,19
Performance Server ,119
Peripheral ,19Persistent Memory (pmem ),19
Platform ,19
Platform Boot Firmware ,19
Platform Firmware ,19
Platform Runtime Firmware ,19
Pn Performance State ,25
Power Button ,19
Power Management ,19

H
HBA,558
I
L
Legacy ,18
M
19
N
NVDIMM ,19
O
Object ,19
P
Power Resources ,20
Power Sources ,20
Processor power management ,26
R
Register Grouping ,20
Reserved Bits ,20
Root System Description Pointer (RSDP ),
20
Root System Description Table (RSDT ),20
Runtime Firmware ,20
S
S1 Sleeping State ,24
S2 Sleeping State ,24
S3 Sleeping State ,24
S4 Non-Volatile Sleep ,22
S4 Sleeping State ,24
S5 Soft Off State ,25
Secondary System Description Table
(SSDT ),20
Sleep Button ,20
Smart Battery Subsystem ,20
Smart Battery Table ,20
SMBus Controller ,27
SMBus Interface ,20
Software ,20
SOHO Server ,119
Streamlined Advanced Programmable
Interrupt Controller (SAPIC ),20
System ,20
System BIOS ,20
System Context ,20
System Control Interrupt (SCI),21
System Events ,26
System Management Bus (SMBus ),21
System Management Interrupt (SMI),21
System Physical Address (SPA),20
System power management ,26
T
Tablet ,119
Thermal management ,26
Thermal States ,21
Index 1057Advanced Conﬁguration and Power Interface (ACPI) Speciﬁcation, Release 6.5
U
UEFI ,21
UEFI Drivers ,21
W
Workstation ,118
Index 1058Advanced Micro Devices
Publication No. Revision Date
24593 3.41 June 2023AMD64 Technology
AMD64 Architecture
Programmer’s Manual 
Volume 2: 
System Programming
24593 3.41 June 2023
[AMD Public Use]© 2013 – 2023 Advanced Micro Devices Inc.  All rights reserved.
The information contained herein is for informational purposes only, and is subject to change without notice.
While every precaution has been taken in the preparation of this document, it may contain technicalinaccuracies, omissions and typographical errors, and AMD is under no obligation to update or otherwisecorrect this information. Advanced Micro Devices, Inc. makes no representations or warranties with respect tothe accuracy or completeness of the contents of this document, and assumes no liability of any kind, includingthe implied warranties of noninfringement, merchantability or fitness for particular purposes, with respect to theoperation or use of AMD hardware, software or other products described herein. No license, including impliedor arising by estoppel, to any intellectual property rights is granted by this document. Terms and limitationsapplicable to the purchase or use of AMD products are as set forth in a signed agreement between the parties orin AMD Standard Terms and Conditions of Sale. Any unauthorized copying, alteration, distribution,transmission, performance, display or other use of this material is prohibited. 
Trademarks
AMD, the AMD arrow logo, and combinations thereof, AMD Virtualization and 3DNow! are 
trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
MMX is a trademark and Pentium is a registered trademark of Intel Corporation. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
[AMD Public Use]Contents iii24593—Rev. 3.41—June 2023 AMD64 Technology
Contents
Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  xx
Tables  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  xxx
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  xxxv
Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  xlvii
About This Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlvii
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlvii
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlviiConventions and Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xlviii
Notational Conventions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlix
Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lRegisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lviEndian Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lix
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lix
1 System-Programming Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Memory Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Memory Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Canonical Address Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Paging  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Mixing Segmentation and Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Real Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Long Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Compatibility Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Legacy Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14System Management Mode (SMM)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151.5 System-Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.7 Additional System-Programming Facilities  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hardware Multitasking  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Machine Check  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Software Debugging  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2 x86 and AMD64 Architecture Differences  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Long Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
[AMD Public Use]iv ContentsAMD64 Technology 24593—Rev. 3.41—June 2023
System-Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2 Memory Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Page Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3 Protection Checks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4 Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
General-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28YMM/XMM Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Flags Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Extended Feature Register (EFER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory Type Range Registers (MTRRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Other Model-Specific Registers (MSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Segment-Override Prefixes in 64-Bit Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operands and Results  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Address Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Instructions that Reference RSP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Branches  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32NOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Single-Byte INC and DEC Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MOVSXD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Invalid Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reassigned Opcodes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FXSA VE and FXRSTOR Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6 Interrupts and Exceptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Stack Frame Pushes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Stack Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37IRET Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Task-Priority Register (CR8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
New Exception Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.7 Hardware Task Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.8 Long-Mode vs. Legacy-Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3 System Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.1 System-Control Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CR2 and CR3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44CR4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Additional Control Registers in 64-Bit-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CR8 (Task Priority Register, TPR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51RFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
[AMD Public Use]Contents v24593—Rev. 3.41—June 2023 AMD64 Technology
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Extended Control Registers (XCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2 Model-Specific Registers (MSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
System Configuration Register (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60System-Linkage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Memory-Typing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Debug-Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Performance-Monitoring Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Machine-Check Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Shadow Stack Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Extended State Save MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Speculation Control MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Hardware Configuration Register (HWCR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3 Processor Feature Identification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4 Segmented Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.1 Real Mode Segmentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734.2 Virtual-8086 Mode Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3 Protected Mode Segmented-Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Multi-Segmented Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Flat-Memory Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Segmentation in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4 Segmentation Data Structures and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5 Segment Selectors and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Segment Selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Segment Registers in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.6 Descriptor Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Global Descriptor Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Global Descriptor-Table Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Local Descriptor Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Local Descriptor-Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Interrupt Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Interrupt Descriptor-Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.7 Legacy Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Code-Segment Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Data-Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92System Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Gate Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.8 Long-Mode Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Code-Segment Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Data-Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98System Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Gate Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Long Mode Descriptor Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.9 Segment-Protection Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Privilege-Level Concept  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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Privilege-Level Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.10 Data-Access Privilege Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Accessing Data Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Accessing Stack Segments  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.11 Control-Transfer Privilege Checks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Direct Control Transfers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Control Transfers Through Call Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Return Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.12 Limit Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Determining Limit Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Data Limit Checks in 64-bit Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.13 Type Checks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Type Checks in Legacy and Compatibility Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Long Mode Type Check Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5 Page Translation and Protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.1 Page Translation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Page-Translation Options  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Page-Translation Enable (PG) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Physical-Address Extensions (PAE) Bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Page-Size Extensions (PSE) Bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Page-Directory Page Size (PS) Bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.2 Legacy-Mode Page Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
CR3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Normal (Non-PAE) Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132PAE Paging  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3 Long-Mode Page Translation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Canonical Address Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
CR3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4-Kbyte Page Translation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412-Mbyte Page Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451-Gbyte Page Translation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.4 Page-Translation-Table Entry Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Field Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Notes on Accessed and Dirty Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.5 Translation-Lookaside Buffer (TLB)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Process Context Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Global Pages  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158TLB Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.6 Page-Protection Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

User/Supervisor (U/S) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Read/Write (R/W) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163No Execute (NX) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Write Protect (CR0.WP) Bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Supervisor-Mode Execution Prevention (CR4.SMEP) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . 163Supervisor-Mode Access Prevention(CR4.SMAP) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Memory Protection Keys (MPK) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.7 Shadow Stack Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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Shadow Stack Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Shadow Stack Pages  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165Shadow Stack Protection Checks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.8 Protection Across Paging Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Access to User Pages when CR0.WP=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.9 Effects of Segment Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685.10 Upper Address Ignore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Detecting and Enabling Upper Address Ignore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168Upper Address Ignore Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Address Tag Storage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Debug Breakpoint Behavior with Upper Address Ignore . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6 System Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
6.1 Fast System Call and Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SYSCALL and SYSRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174SYSENTER and SYSEXIT (Legacy Mode Only)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176SWAPGS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.2 System Status and Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Processor Feature Identification (CPUID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Accessing Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Accessing the RFLAGS Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Accessing Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Accessing Model-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3 Segment Register and Descriptor Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Accessing Segment Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179Accessing Segment Register Hidden State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179Accessing Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.4 Protection Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Checking Access Rights  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Checking Segment Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180Checking Read/Write Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180Adjusting Access Rights  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.5 Processor Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.6 Cache and TLB Management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Cache Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181TLB Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.7 Shadow Stack Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7 Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
7.1 Single-Processor Memory Access Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Read Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Write Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188Read/Write Barriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.2 Multiprocessor Memory Access Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897.3 Memory Coherency and Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Special Coherency Considerations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Access Atomicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Cacheable Locks and Bus Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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7.4 Memory Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Instruction Fetching from Uncacheable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Memory Barrier Interaction with Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.5 Buffering and Combining Memory Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Write Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201Write Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.6 Memory Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Cache Organization and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Cache Control Mechanisms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206Cache and Memory Management Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209Serializing Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210Cache and Processor Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
L3 Cache Range Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.7 Memory-Type Range Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

MTRR Type Fields  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216MTRRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Using MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MTRRs and Page Cache Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224MTRRs in Multi-Processing Environments  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
7.8 Page-Attribute Table Mechanism  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
PAT Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226PAT Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227Identifying PAT Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
PAT Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228Combined Effect of MTRRs and PAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229PATs in Multi-Processing Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230Changing Memory Type  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.9 Memory-Mapped I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Extended Fixed-Range MTRR Type-Field Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231IORRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233IORR Overlapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Top of Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
7.10 Secure Memory Encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Determining Support for Secure Memory Encryption  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Enabling Memory Encryption Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Supported Operating Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238Page Table Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238I/O Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Restrictions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239SMM Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239Encrypt-in-Place  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239Secure Multi-Key Memory Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
8 Exceptions and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Precision  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241Instruction Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242Types of Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
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Masking External Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Masking Floating-Point and Media Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Disabling Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
8.2 Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
#DE—Divide-by-Zero-Error Exception (Vector 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247#DB—Debug Exception (Vector 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247NMI—Non-Maskable-Interrupt Exception (Vector 2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248#BP—Breakpoint Exception (Vector 3)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248#OF—Overflow Exception (Vector 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249#BR—Bound-Range Exception (Vector 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
#UD—Invalid-Opcode Exception (Vector 6)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
#NM—Device-Not-Available Exception (Vector 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250#DF—Double-Fault Exception (Vector 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250Coprocessor-Segment-Overrun Exception (Vector 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
#TS—Invalid-TSS Exception (Vector 10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252#NP—Segment-Not-Present Exception (Vector 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
#SS—Stack Exception (Vector 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
#GP—General-Protection Exception (Vector 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254#PF—Page-Fault Exception (Vector 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255#MF—x87 Floating-Point Exception-Pending (Vector 16). . . . . . . . . . . . . . . . . . . . . . . . . . 256#AC—Alignment-Check Exception (Vector 17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257#MC—Machine-Check Exception (Vector 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258#XF—SIMD Floating-Point Exception (Vector 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
#CP—Control-Protection Exception (Vector 21)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259#HV—Hypervisor Injection Exception (Vector 28)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
#VC—VMM Communication Exception (Vector 29). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260#SX—Security Exception (Vector 30). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260User-Defined Interrupts (Vectors 32–255)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
8.3 Exceptions During a Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2618.4 Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Selector-Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Page-Fault Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Control-Protection Error Code  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
8.5 Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Floating-Point Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264External Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
8.6 Real-Mode Interrupt Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2678.7 Legacy Protected-Mode Interrupt Control Transfers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Locating the Interrupt Handler  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Interrupt To Same Privilege. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271Interrupt To Higher Privilege. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272Privilege Checks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273Returning From Interrupt Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276Shadow Stack Support for Interrupts and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
8.8 Virtual-8086 Mode Interrupt Control Transfers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Protected-Mode Handler Control Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278Virtual-8086 Handler Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
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8.9 Long-Mode Interrupt Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Interrupt Gates and Trap Gates  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Locating the Interrupt Handler  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Interrupt Stack Frame  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Interrupt-Stack Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284Returning From Interrupt Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
8.10 Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Virtual-8086 Mode Extensions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Protected Mode Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290Effect of Instructions that Modify EFLAGS.IF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
9 Machine Check Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Reliability, Availability, and Serviceability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Error Detection, Logging, and Reporting  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Error Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
9.2 Determining Machine-Check Architecture Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
9.3 Machine Check Architecture MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Global Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300Error-Reporting Register Banks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305Machine-Check Architecture Extension Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
9.4 Initializing the Machine-Check Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3189.5 Using MCA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Determining the Scope of Detected Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Handling Machine Check Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Reporting Corrected Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
10 System-Management Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
10.1 SMM Differences  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32310.2 SMM Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
SMRAM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324SMBASE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325SMRAM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326SMM-Revision Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330SMRAM Protected Areas  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
10.3 Using SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
System-Management Interrupt (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333SMM Operating-Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Exceptions and Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334Invalidating the Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Saving Additional Processor State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336Operating in Protected Mode and Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336Auto-Halt Restart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336I/O Instruction Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
SMM Page Configuration Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
10.4 Leaving SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
10.5 Multiprocessor Considerations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
11 SSE, MMX, and x87 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
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11.1 Overview of System-Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
11.2 Determining Media and x87 Feature Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34111.3 Enabling SSE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Enabling Legacy SSE Instruction Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343Enabling Extended SSE Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343SIMD Floating-Point Exception Handling  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
11.4 Media and x87 Processor State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
SSE Execution Unit State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344MMX Execution Unit State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345x87 Execution Unit State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346Saving Media and x87 Execution Unit State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
11.5 XSAVE/XRSTOR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
CPUID Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

XFEATURE_ENABLED_MASK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355Extended Save Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356Instruction Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356YMM States and Supported Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357Extended SSE Execution State Management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Saving Processor State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Restoring Processor State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358MXCSR State Management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Mode-Specific XSA VE/XRSTOR State Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
12 Task Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
12.1 Hardware Multitasking Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36512.2 Task-Management Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
TSS Selector  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368TSS Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369Legacy Task-State Segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37164-Bit Task State Segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Task Gate Descriptor (Legacy Mode Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
12.3 Hardware Task-Management in Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Task Memory-Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378Switching Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Task Switches Using Task Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Nesting Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
13 Software Debug and Performance Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
13.1 Software-Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Setting Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401Using Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403Single Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407Breakpoint Instruction (INT3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407Control-Transfer Breakpoint Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408Debug Breakpoint Address Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Last Branch Record Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
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13.2 Performance Monitoring Counters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Performance Counter MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Detecting Hardware Support for Performance Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 420Using Performance Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421Time-Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
13.3 Instruction-Based Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
IBS Fetch Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423IBS Fetch Sampling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424IBS Execution Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
IBS Execution Sampling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
IBS Filtering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
13.4 Lightweight Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437Events and Event Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Detecting LWP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450LWP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454LWP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456LWP Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460XSA VE/XRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470Implementation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
14 Processor Initialization and Long Mode Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .479
14.1 Processor Initialization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Built-In Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479Clock Multiplier Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Processor Initialization State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480Multiple Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482Fetching the First Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
14.2 Hardware Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Processor Implementation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483Enabling Internal Caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483Initializing Media and x87 Processor State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Model-Specific Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
14.3 Initializing Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
14.4 Initializing Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48614.5 Initializing Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48714.6 Enabling and Activating Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Activating Long Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Consistency Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490Updating System Descriptor Table References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490Relocating Page-Translation Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
14.7 Leaving Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49114.8 Long-Mode Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
15 Secure Virtual Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .497
15.1 The Virtual Machine Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49715.2 SVM Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Virtualization Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
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Guest Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
External Access Protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498Restartable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498Security Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
15.3 SVM Processor and Platform Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49915.4 Enabling SVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49915.5 VMRUN Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
VMSA VE and VMLOAD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
15.6 #VMEXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50615.7 Intercept Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
State Saved on Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507Intercepts During IDT Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
EXITINTINFO Pseudo-Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
15.8 Decode Assists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
MOV CRx/DRx Intercepts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510INTn Intercepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511INVLPG and INVLPGA Intercepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511Nested and intercepted #PF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
15.9 Instruction Intercepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51215.10 IOIO Intercepts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
I/O Permissions Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515IN and OUT Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516(REP) OUTS and INS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
15.11 MSR Intercepts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51715.12 Exception Intercepts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
#DE (Divide By Zero) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
#DB (Debug) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518Vector 2 (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519#BP (Breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519#OF (Overflow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
#BR (Bound-Range)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519#UD (Invalid Opcode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
#NM (Device-Not-Available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519#DF (Double Fault) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519Vector 9 (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519#TS (Invalid TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520#NP (Segment Not Present). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520#SS (Stack Fault) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520#GP (General Protection). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520#PF (Page Fault)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520#MF (X87 Floating Point) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
#AC (Alignment Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
#MC (Machine Check)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520#XF (SIMD Floating Point). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521#SX (Security Exception)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
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#CP (Control Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
15.13 Interrupt Intercepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
INTR Intercept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
NMI Intercept  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
SMI Intercept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521INIT Intercept  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Virtual Interrupt Intercept  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
15.14 Miscellaneous Intercepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

Task Switch Intercept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523Ferr_Freeze Intercept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523Shutdown Intercept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524Pause Intercept Filtering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
Bus Lock Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
15.15 VMCB State Caching  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
VMCB Clean Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525Guidelines for Clearing VMCB Clean Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
VMCB Clean Field  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
15.16 TLB Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
TLB Flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528Invalidate Page, Alternate ASID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
15.17 Global Interrupt Flag, STGI and CLGI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52915.18 VMMCALL Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53015.19 Paged Real Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53015.20 Event Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53015.21 Interrupt and Local APIC Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Physical (INTR) Interrupt Masking in EFLAGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532Virtualizing APIC.TPR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532TPR Access in 32-Bit Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532Injecting Virtual (INTR) Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Interrupt Shadows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533Virtual Interrupt Intercept  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534Interrupt Masking in Local APIC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534INIT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534NMI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535NMI Virtualization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
15.22 SMM Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Sources of SMI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536Response to SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537Containerizing Platform SMM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
15.23 Last Branch Record Virtualization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Hardware Acceleration for LBR Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539LBR Virtualization CPUID Feature Detection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
15.24 External Access Protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Device IDs and Protection Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540Device Exclusion Vector (DEV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540Access Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541DEV Capability Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
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DEV Register Access Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
DEV Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544Unauthorized Access Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546Secure Initialization Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
15.25 Nested Paging  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Traditional Paging versus Nested Paging  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Replicated State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Enabling Nested Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549Nested Paging and VMRUN/#VMEXIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549Nested Table Walk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549Nested versus Guest Page Faults, Fault Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550Combining Nested and Guest Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551Combining Memory Types, MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Page Splintering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Legacy PAE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554A20 Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554Detecting Nested Paging Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554Guest Mode Execute Trap Extension  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554Supervisor Shadow Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
15.26 Security  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
15.27 Secure Startup with SKINIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Secure Loader  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Secure Loader Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557Secure Loader Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557Trusted Platform Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558System Interface, Memory Controller and I/O Hub Logic . . . . . . . . . . . . . . . . . . . . . . . . . . 559SKINIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559SL Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560Secure Multiprocessor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

15.28 Security Exception (#SX)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56215.29 Advanced Virtual Interrupt Controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562Local APIC Register Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563A VIC Backing Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564VMCB Changes for A VIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
A VIC Memory Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Interrupt Delivery  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576A VIC CPUID Feature Flags  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578New Processor Mechanisms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578A VIC Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579x2A VIC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
15.30 SVM Related MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
VM_CR MSR (C001_0114h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583IGNNE MSR (C001_0115h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584SMM_CTL MSR (C001_0116h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
VM_HSA VE_PA MSR (C001_0117h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585TSC Ratio MSR (C000_0104h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
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15.31 SVM-Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
SVM_KEY MSR (C001_0118h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
15.32 SMM-Lock  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
SmmLock Bit — HWCR[0]  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
SMM_KEY MSR (C001_0119h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
15.33 Nested Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
VMSA VE and VMLOAD Virtualization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588Virtual GIF (VGIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
15.34 Secure Encrypted Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Determining Support for SEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589Key Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589Enabling SEV  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Supported Operating Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590SEV Encryption Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Page Table Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590Restrictions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591SEV Interaction with SME  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592Page Flush MSR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593SEV_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593Virtual Transparent Encryption (VTE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
15.35 Encrypted State (SEV-ES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
Determining Support for SEV-ES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595Enabling SEV-ES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595SEV-ES Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595Types of Exits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
#VC Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597VMGExit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599GHCB  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599VMRUN  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599Automatic Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Control Register Write Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601Interaction with SMI and #MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
15.36 Secure Nested Paging (SEV-SNP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Determining Support for SEV-SNP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602Enabling SEV-SNP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602Reverse Map Table  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602Initializing the RMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604Hypervisor RMP Management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604Page Validation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605Virtual Machine Privilege Levels  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606Virtual Top-of-Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607Reflect #VC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
RMP and VMPL Access Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Large Page Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610Running SNP-Active Virtual Machines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
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TLB management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Interrupt Injection Restrictions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Side-Channel Protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

Secure TSC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616SEV-SNP Instruction Virtualization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
15.37 SPEC_CTRL Virtualization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61715.38 Instruction-Based Sampling Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
16 Advanced Programmable Interrupt Controller (APIC) . . . . . . . . . . . . . . . . . . . . . . . . .620
16.1 Sources of Interrupts to the Local APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62116.2 Interrupt Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62116.3 Local APIC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Local APIC Enable  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622APIC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623Local APIC ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625APIC Version Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Extended APIC Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Extended APIC Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
16.4 Local Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
APIC Timer Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629Local Interrupts LINT0 and LINT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631Performance Monitor Counter Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Thermal Sensor Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Extended Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632APIC Error Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632Spurious Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
16.5 Interprocessor Interrupts (IPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63416.6 Local APIC Handling of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Receiving System and IPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Lowest Priority Messages and Arbitration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639Accepting System and IPI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Selecting and Handling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
16.7 SVM Support for Interrupts and the Local APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Specific End of Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
16.8 x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
x2APIC Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
16.9 Detecting and Enabling x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Enabling x2APIC Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
16.10 x2APIC Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65016.11 Accessing x2APIC Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
x2APIC Register Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
WRMSR / RDMSR serialization for x2APIC Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652Reserved Bit Checking in x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
16.12 x2APIC_ID  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65216.13 x2APIC Interrupt Command Register (ICR) Operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . 65316.14 Logical Destination Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65416.15 Self_IPI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
[AMD Public Use]xviii ContentsAMD64 Technology 24593—Rev. 3.41—June 2023
17 Hardware Performance Monitoring and Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .657
17.1 P-State Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
17.2 Core Performance Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
17.3 Determining Processor Effective Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Actual Performance Frequency Clock Count (APERF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Maximum Performance Frequency Clock Count (MPERF) . . . . . . . . . . . . . . . . . . . . . . . . . 661
APERF Read-only (AperfReadOnly)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662MPERF Read-only (MperfReadOnly). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
17.4 Processor Feedback Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66217.5 Processor Core Power Reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Processor Facilities  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663Software Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
17.6 Collaborative Processor Performance Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Detecting Support for CPPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664CPPC Model Specific Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664Enabling CPPC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664CPPC Performance Levels and Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665Using CPPC to Manage Processor Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
CPPC Feedback Mechanisms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
18 Shadow Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .671
18.1 Shadow Stack Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Detecting and Enabling Shadow Stack Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
18.2 The Shadow Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
18.3 Shadow Stack Operation for CALL (near) and RET (near)  . . . . . . . . . . . . . . . . . . . . . . . . . 67218.4 Shadow Stack Operation for Far Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

18.5 Far Transfer to the Same Privilege Level  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
18.6 Far Transfer to Different Privilege Level  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Shadow Stack Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673Handling CS, LIP and SSP on Privilege Transistions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675Supervisor Shadow Stack Token . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Shadow Stack Token Validation for Inter-privilege CALL (far) and Interrupts/Exceptions . 676
Shadow Stack Token Validation for Inter-privilege RET and IRET . . . . . . . . . . . . . . . . . . . 677
18.7 Shadow Stack Operation for SYSCALL and SYSRET  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
18.8 Shadow Stack Operation for Task Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67818.9 Restricting Speculative Execution of RET targets  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67918.10 Shadow Stack Switching Using RSTORSSP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
18.11 Shadow Stack Management Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68218.12 Shadow Stack MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68318.13 XSAVE/XRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
19 Platform Quality of Service (PQOS) Extension  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .685
19.1 PQOS Extension Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Detecting Support for PQOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686Identifying PQM and PQE Capabilities  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
19.2 PQOS Monitoring (PQM) Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Detecting PQM Monitoring Resources and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
19.3 L3 Cache Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
[AMD Public Use]Contents xix24593—Rev. 3.41—June 2023 AMD64 Technology
PQM MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Monitoring L3 Occupancy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Monitoring L3 Memory Bandwidth (MBM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
19.4 PQOS Enforcement (PQE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Identifying support for PQE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702L3 Cache Allocation Enforcement (CAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702Code and Data Prioritization (CDP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704AMD Bandwidth Enforcement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
L3 External Bandwidth Enforcement (L3BE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706L3 Slow Memory Bandwidth Enforcement (L3SMBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE)  . . . . . . . . . . . . . . . . . . 709
Appendix A MSR Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711
A.1 MSR Cross-Reference by MSR Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711A.2 System-Software MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719A.3 Memory-Typing MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720A.4 Machine-Check MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
A.5 Software-Debug MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723A.6 Performance-Monitoring MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724A.7 Secure Virtual Machine MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
A.8 System Management Mode MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
A.9 CPUID Name MSR Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727A.10 Shadow Stack MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728A.11 Speculation Control MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728A.12 Memory Cache MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728A.13 Quality of Service MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729A.14 Collaborative Processor Performance Control MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Appendix B Layout of VMCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .730
Appendix C SVM Intercept Exit Codes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .745Appendix D SMM Containerization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .748
D.1 SMM Containerization Pseudocode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Appendix E OS-Visible Workarounds  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .754
E.1 Erratum Process Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  757
[AMD Public Use]xx FiguresAMD64 Technology 24593—Rev. 3.41—June 2023
Figures
Figure 1 -1. Segmented-Memory Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 1 -2. Flat Memory Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 1 -3. Paged Memory Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1 -4. 64-Bit Flat, Paged-Memory Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 1 -5. Real-Address Memory Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 1 -6. Operating Modes of the AMD64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 1 -7. System Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 1 -8. System-Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3 -1. Control Register 0 (CR0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 3 -2. Control Register 2 (CR2)—Legacy-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3 -3. Control Register 2 (CR2)—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3 -4. Control Register 3 (CR3)—Legacy-Mode Non-PAE Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3 -5. Control Register 3 (CR3)—Legacy-Mode PAE Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3 -6. Control Register 3 (CR3)—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 3 -7. CR4 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 3 -8. RFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 3 -9. Extended Feature Enable Register (EFER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 3 -10. AMD64 Architecture Model-Specific Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 3 -11. System-Configuration Register (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 3 -12. XSS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 3 -13. SPEC_CTRL Register (MSR 048h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 3 -14. PRED_CMD Register (MSR 049h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 4 -1. Segmentation Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 4 -2. Segment and Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 4 -3. Segment Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 4 -4. Segment-Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 4 -5. FS and GS Segment-Register Format—64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 4 -6. Global and Local Descriptor-Table Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 4 -7. GDTR and IDTR Format—Legacy Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 4 -8. GDTR and IDTR Format—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 4 -9. Relationship between the LDT and GDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Figure 4 -10. LDTR Format—Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 4 -11. LDTR Format—Long Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 4 -12. Indexing an IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 4 -13. Generic Segment Descriptor—Legacy Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 4 -14. Code-Segment Descriptor—Legacy Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 4 -15. Data-Segment Descriptor—Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 4 -16. LDT and TSS Descriptor—Legacy/Compatibility Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 4 -17. Call-Gate Descriptor—Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 4 -18. Interrupt-Gate and Trap-Gate Descriptors—Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 4 -19. Task-Gate Descriptor—Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 4 -20. Code-Segment Descriptor—Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 4 -21. Data-Segment Descriptor—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 4 -22. System-Segment Descriptor—64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 4 -23. Call-Gate Descriptor—Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 4 -24. Interrupt-Gate and Trap-Gate Descriptors—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 4 -25. Privilege-Level Relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 4 -26. Data-Access Privilege-Check Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 4 -27. Stack-Access Privilege-Check Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 4 -28. Nonconforming Code-Segment Privilege-Check Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 4 -29. Conforming Code-Segment Privilege-Check Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 4 -30. Legacy-Mode Call-Gate Transfer Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 4 -31. Long-Mode Call-Gate Access Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 4 -32. Privilege-Check Examples for Call Gates  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 4 -33. Legacy-Mode 32-Bit Stack Switch, with Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 4 -34. 32-Bit Stack Switch, No Parameters—Legacy Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 4 -35. Stack Switch—Long Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 5 -1. Virtual to Physical Address Translation—Long Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 5 -2. Control Register 3 (CR3)—Non-PAE Paging Legacy-Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 5 -3. Control Register 3 (CR3)—PAE Paging Legacy-Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 5 -4. 4-Kbyte Non-PAE Page Translation—Legacy Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 5 -5. 4-Kbyte PDE—Non-PAE Paging Legacy-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 5 -6. 4-Kbyte PTE—Non-PAE Paging Legacy-Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 5 -7. 4-Mbyte Page Translation—Non-PAE Paging Legacy-Mode . . . . . . . . . . . . . . . . . . . . . . . . . 135
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Figure 5 -8. 4-Mbyte PDE—Non-PAE Paging Legacy-Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 5 -9. 4-Kbyte PAE Page Translation—Legacy Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 5 -10. 4-Kbyte PDPE—PAE Paging Legacy-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 5 -11. 4-Kbyte PDE—PAE Paging Legacy-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 5 -12. 4-Kbyte PTE—PAE Paging Legacy-Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 5 -13. 2-Mbyte PAE Page Translation—Legacy Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 5 -14. 2-Mbyte PDPE—PAE Paging Legacy-Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 5 -15. 2-Mbyte PDE—PAE Paging Legacy-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 5 -16. Control Register 3 (CR3)—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 5 -17. 4-Kbyte Page Translation—Long Mode 4-Level Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 5 -18. 4-Kbyte Page Translation—Long Mode 5-Level Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 5 -19. 4-Kbyte PML5E—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 5 -20. 4-Kbyte PML4E—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 5 -21. 4-Kbyte PDPE—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 5 -22. 4-Kbyte PDE—Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 5 -23. 4-Kbyte PTE—Long Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 5 -24. 2-Mbyte Page Translation—Long Mode 4-Level Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 5 -25. 2-Mbyte Page Translation—Long Mode 5-Level Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 5 -26. 2-Mbyte PML5E—Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 5 -27. 2-Mbyte PML4E—Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 5 -28. 2-Mbyte PDPE—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 5 -29. 2-Mbyte PDE—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 5 -30. 1-Gbyte Page Translation—Long Mode 4-Level Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 5 -31. 1-Gbyte Page Translation—Long Mode 5-Level Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 5 -32. 1-Gbyte PML5E—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 5 -33. 1-Gbyte PML4E—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 5 -34. 1-Gbyte PDPE—Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 5 -35. PKRU Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 6 -1. STAR, LSTAR, CSTAR, and MASK MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 6 -2. SYSENTER_CS, SYSENTER_ESP, SYSENTER_EIP MSRs . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 7 -1. Processor and Memory System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 7 -2. MOESI State Transitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 7 -3. Cache Organization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
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Figure 7 -4. L3 Range Reserve Base Address Register (L3RangeReserveBaseAddr). . . . . . . . . . . . . . . . . 213
Figure 7 -5. L3 Range Reserve Maximum Address Register (L3RangeReserveMaxAddr)  . . . . . . . . . . . . 213
Figure 7 -6. L3 Range Reserve Way Mask Register (L3RangeReserveWayMask). . . . . . . . . . . . . . . . . . . 214
Figure 7 -7. MTRR Mapping of Physical Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 7 -8. Fixed-Range MTRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 7 -9. MTRRphysBase n Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 7 -10. MTRRphysMaskn Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 7 -11. MTRRdefType Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 7 -12. MTRR Capability Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 7 -13. PAT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 7 -14. Extended MTRR Type-Field Format (Fixed-Range MTRRs) . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 7 -15. IORRBasen  Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 7 -16. IORRMask n Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 7 -17. Memory Organization Using Top-of-Memory Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 7 -18. Top-of-Memory Registers (TOP_MEM, TOP_MEM2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 7 -19. Encrypted Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 8 -1. Control Register 2 (CR2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 8 -2. Selector Error Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 8 -3. Page-Fault Error Code  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 8 -4. Control-Protection Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 8 -5. Task Priority Register (CR8)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 8 -6. Real-Mode Interrupt Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 8 -7. Stack After Interrupt in Real Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 8 -8. Protected-Mode Interrupt Control Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 8 -9. Stack After Interrupt to Same Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 8 -10. Stack After Interrupt to Higher Privilege . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 8 -11. Privilege-Check Examples for Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 8 -12. Stack After Virtual-8086 Mode Interrupt to Protected Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 8 -13. Long-Mode Interrupt Control Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 8 -14. Long-Mode Stack After Interrupt—Same Privilege. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 8 -15. Long-Mode Stack After Interrupt—Higher Privilege. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 8 -16. Long-Mode IST Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 9 -1. MCG_CAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
[AMD Public Use]xxiv FiguresAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 9 -2. MCG_STATUS Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 9 -3. MCG_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 9 -4. MCA_INTR_CFG Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 9 -5. CPU Watchdog Timer Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Figure 9 -6. MCi_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 9 -7. MC i_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 9 -8. MCi_MISC1 Addressing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 9 -9. Miscellaneous Information Register (Thresholding Register Format) . . . . . . . . . . . . . . . . . . . 312
Figure 9 -10. Address Mapping of Registers in MCAX Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 9 -11. MCA_IPID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 9 -12. MCA_DESTAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 10 -1. Default SMRAM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 10 -2. SMBASE Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 10 -3. SMM-Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 10 -4. SMM_ADDR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 10 -5. SMM_MASK Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 10 -6. I/O Instruction Restart Dword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 11 -1. SSE Execution Unit State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 11 -2. MMX Execution Unit State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 11 -3. x87 Execution Unit State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 11 -4. FSAVE/FNSAVE Image (32-Bit, Protected Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 11 -5. FSAVE/FNSAVE Image (32-Bit, Real/Virtual-8086 Modes) . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 11 -6. FSAVE/FNSAVE Image (16-Bit, Protected Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 11 -7. FSAVE/FNSAVE Image (16-Bit, Real/Virtual-8086 Modes) . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 11 -8. XFEATURE_ENABLED_MASK Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 11 -9. FXSAVE and FXRSTOR Image (64-bit Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 11 -10. FXSAVE and FXRSTOR Image (Non-64-bit Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 12 -1. Task-Management Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Figure 12 -2. Task-Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Figure 12 -3. TR Format, Legacy Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Figure 12 -4. TR Format, Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 12 -5. Relationship between the TSS and GDT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 12 -6. Legacy 32-bit TSS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
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Figure 12 -7. I/O-Permission Bitmap Example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 12 -8. Long Mode TSS Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Figure 12 -9. Task-Gate Descriptor, Legacy Mode Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Figure 12 -10. Privilege-Check Examples for Task Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Figure 13 -1. Address-Breakpoint Registers (DR0–DR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 13 -2. Debug-Status Register (DR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Figure 13 -3. Debug-Control Register (DR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Figure 13 -4. Debug-Control MSR (DebugCtl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Figure 13 -5. Control-Transfer Recording MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Figure 13 -6. Debug-Extension-Control MSR (DebugExtnCtl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Figure 13 -7. LastBranchStackFromIp MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Figure 13 -8. LastBranchStackToIp MSR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Figure 13 -9. LastBranchStackSelect MSR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 13 -10. Performance Counter Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Figure 13 -11. Core Performance Event-Select Register (PerfEvtSeln ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Figure 13 -12. Performance Counter Global Control (PerfCntGlobalCtl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 13 -13. Performance Counter Global Status Register (PerfCntGlobalStatus). . . . . . . . . . . . . . . . . . . . 416
Figure 13 -14. Performance Counter Global Status Set Register (PerfCntGlobalStatusSet) . . . . . . . . . . . . . . 417
Figure 13 -15. Performance Counter Global Status Clear Register (PerfCntGlobalStatusClr) . . . . . . . . . . . . 418
Figure 13 -16. Northbridge Performance Event-Select Register (NB_PerfEvtSeln ) . . . . . . . . . . . . . . . . . . . . 419
Figure 13 -17. L2 Cache Performance Event-Select Register (L2I_PerfEvtSel n) . . . . . . . . . . . . . . . . . . . . . . 420
Figure 13 -18. Time-Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Figure 13 -19. IBS Fetch Control Register(IbsFetchCtl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Figure 13 -20. IBS Fetch Linear Address Register (IbsFetchLinAd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Figure 13 -21. IBS Fetch Physical Address Register (IbsFetchPhysAd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Figure 13 -22. IBS Execution Control Register (IbsOpCtl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Figure 13 -23. IBS Op Linear Address Register (IbsOpRip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Figure 13 -24. IBS Op Data 1 Register (IbsOpData1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Figure 13 -25. IBS Op Data 3 Register (IbsOpData3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Figure 13 -26. IBS Data Cache Linear Address Register (IbsDcLinAd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 13 -27. IBS Data Cache Physical Address Register (IbsDcPhysAd) . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Figure 13 -28. IBS Branch Target Address Register (IbsBrTarget). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Figure 13 -29. Generic Event Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
[AMD Public Use]xxvi FiguresAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 13 -30. Programmed Value Sample Event Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Figure 13 -31. Instructions Retired Event Record  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Figure 13 -32. Branch Retired Event Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 13 -33. DCache Miss Event Record  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Figure 13 -34. CPU Clocks not Halted Event Record  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Figure 13 -35. CPU Reference Clocks not Halted Event Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 13 -36. Programmed Event Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Figure 13 -37. LWP_CFG—Lightweight Profiling Features MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 13 -38. LWPCB—Lightweight Profiling Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Figure 13 -39. LWPCB Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Figure 13 -40. LWPCB Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Figure 13 -41. XSAVE Area for LWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Figure 15 -1. EXITINTINFO for All Intercepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 15 -2. EXITINFO1 for IOIO Intercept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Figure 15 -3. EXITINFO1 for SMI Intercept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Figure 15 -4. Layout of VMCB Clean Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Figure 15 -5. EVENTINJ Field in the VMCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Figure 15 -6. Host Bridge DMA Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Figure 15 -7. Format of DEV_OP Register (in PCI Config Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Figure 15 -8. Format of DEV_CAP Register (in PCI Config Space). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 15 -9. Format of DEV_BASE_HI[n] Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 15 -10. Format of DEV_BASE_LO[n] Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 15 -11. Format of DEV_MAP[n] Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 15 -12. Address Translation with Traditional Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Figure 15 -13. Address Translation with Nested Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 15 -14. SLB Example Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Figure 15 -15. vAPIC Backing Page Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 15 -16. Virtual APIC Task Priority Register Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 15 -17. Physical APIC ID Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Figure 15 -18. Physical APIC Table in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Figure 15 -19. Logical APIC ID Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Figure 15 -20. Logical APIC ID Table Format, Flat Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Figure 15 -21. Logical APIC ID Table Format, Cluster Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
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Figure 15 -22. Doorbell Register, MSR C001_011Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Figure 15 -23. EXITINFO1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Figure 15 -24. EXITINFO2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Figure 15 -25. EXITINFO1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Figure 15 -26. EXITINFO2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Figure 15 -27. Layout of VM_CR MSR (C001_0114h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Figure 15 -28. Layout of SMM_CTL MSR (C001_0116h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Figure 15 -29. TSC Ratio MSR (C000_0104h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Figure 15 -30. Guest Data Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Figure 15 -31. EXAMPLE #VC FLOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Figure 16 -1. Block Diagram of a Typical APIC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Figure 16 -2. APIC Base Address Register (MSR 0000_001Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
Figure 16 -3. APIC ID Register (APIC Offset 20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Figure 16 -4. APIC Version Register (APIC Offset 30h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Figure 16 -5. Extended APIC Feature Register (APIC Offset 400h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Figure 16 -6. Extended APIC Control Register (APIC Offset 410h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Figure 16 -7. General Local Vector Table Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Figure 16 -8. APIC Timer Local Vector Table Register (APIC Offset 320h) . . . . . . . . . . . . . . . . . . . . . . . . 629
Figure 16 -9. Timer Current Count Register (APIC Offset 390h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Figure 16 -10. Timer Initial Count Register (APIC Offset 380h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Figure 16 -11. Divide Configuration Register (APIC Offset 3E0h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Figure 16 -12. Local Interrupt 0/1 (LINT0/1) Local Vector Table Register
(APIC Offset 350h/360h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 16 -13. Performance Monitor Counter Local Vector Table Register
(APIC Offset 340h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 16 -14. Thermal Sensor Local Vector Table Register (APIC Offset 330h) . . . . . . . . . . . . . . . . . . . . . 632
Figure 16 -15. APIC Error Local Vector Table Register (APIC Offset 370h). . . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 16 -16. APIC Error Status Register (APIC Offset 280h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Figure 16 -17. Spurious Interrupt Register (APIC Offset F0h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Figure 16 -18. Interrupt Command Register (APIC Offset 300h–310h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Figure 16 -19. Remote Read Register (APIC Offset C0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Figure 16 -20. Logical Destination Register (APIC Offset D0h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Figure 16 -21. Destination Format Register (APIC Offset E0h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
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Figure 16 -22. Arbitration Priority Register (APIC Offset 90h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 16 -23. Interrupt Request Register (APIC Offset 200h–270h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 16 -24. In Service Register (APIC Offset 100h–170h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 16 -25. Trigger Mode Register (APIC Offset 180h–1F0h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 16 -26. Task Priority Register (APIC Offset 80h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Figure 16 -27. Processor Priority Register (APIC Offset A0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 16 -28. End of Interrupt (APIC Offset B0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 16 -29. Specific End of Interrupt (APIC Offset 420h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Figure 16 -30. Interrupt Enable Register (APIC Offset 480h–4F0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Figure 16 -31. APIC Base Address Register (MSR 01Bh) support for x2APIC . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 16 -32. Valid APIC State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Figure 16 -33. x2APIC_ID Register (MSR 802h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Figure 16 -34. Interrupt Command Register (MSR 830h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

Figure 16 -35. Logical Destination (MSR 80Dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 16 -36. Self_IPI Register (MSR 83Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 17 -1. P-State Current Limit Register (MSR C001_0061h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Figure 17 -2. P-State Control Register (MSR C001_0062h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Figure 17 -3. P-State Status Register (MSR C001_0063h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Figure 17 -4. Core Performance Boost (MSR C001_0015h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Figure 17 -5. Actual Performance Frequency Count (MSR0000_00E8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Figure 17 -6. Max Performance Frequency Count (MSR0000_00E7h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Figure 17 -7. APREF Read Only (MSR C000_00E8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Figure 17 -8. MPERF Read Only (MSR C000_00E7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Figure 17 -9. CPPC_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Figure 17 -10. CPPC_CAPABILITY_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 17 -11. CPPC_CAPABILITY_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Figure 17 -12. CPPC_REQUEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Figure 17 -13. CPPC_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Figure 18 -1. Interrupt Shadow Stack Table (ISST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Figure 18 -2. Shadow Stacks and Supervisor Shadow Stack Tokens. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Figure 18 -3. Supervisor Shadow Stack Token  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Figure 18 -4. Shadow Stack Restore Token . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Figure 18 -5. Previous SSP Token . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
[AMD Public Use]Figures xxix24593—Rev. 3.41—June 2023 AMD64 Technology
Figure 18 -6. RSTORSSP and SAVEPREVSSP Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Figure 19 -1. PQR_ASSOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Figure 19 -2. QM_EVTSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Figure 19 -3. QM_CTR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Figure 19 -4. QOS_EVT_CFG_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Figure 19 -5. L3_QOS_ABMC_CFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Figure 19 -6. L3_QOS_ABMC_DSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Figure 19 -7. L3_QOS_EXT_CFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Figure 19 -8. L3_MASK_n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Figure 19 -9. L3_QOS_CFG1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Figure 19 -10. L3QOS_BW_CONTROL_n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Figure 19 -11. L3QOS_SMBW_CONTROL_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
[AMD Public Use]xxx TablesAMD64 Technology 24593—Rev. 3.41—June 2023
Tables
Table 1 -1. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 1 -2. Interrupts and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 2 -1. Instructions That Reference RSP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 2 -2. 64-Bit Mode Near Branches, Default 64-Bit Operand Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 2 -3. Invalid Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 2 -4. Invalid Instructions in Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 2 -5. Opcodes Reassigned in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 2 -6. Differences Between Long Mode and Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3 -1. Speculation Control MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 4 -1. Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 4 -2. Descriptor Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 4 -3. Code-Segment Descriptor Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 4 -4. Data-Segment Descriptor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 4 -5. System-Segment Descriptor Types (S=0)—Legacy Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 4 -6. System-Segment Descriptor Types—Long Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 4 -7. Descriptor-Entry Field Changes in Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 4 -8. Segment Limit Checks in 64-Bit Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 5 -1. Supported Paging Alternatives (CR0.PG=1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 5 -2. Physical-Page Protection, CR0.WP=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 5 -3. Effect of CR0.WP=1 on Supervisor Page Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 6 -1. System Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 7 -1. Atomic Read-Modify-Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 7 -2. Memory Access by Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 7 -3. Caching Policy by Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 7 -4. Memory Access Ordering Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 7 -5. AMD64 Architecture Cache-Operating Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 7 -6. MTRR Type Field Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 7 -7. Fixed-Range MTRR Address Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 7 -8. Combined MTRR and Page-Level Memory Type with Unmodified PAT MSR . . . . . . . . . . . 225
Table 7 -9. PAT Type Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 7 -10. PAT-Register PA-Field Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 7 -11. Combined Effect of MTRR and PAT Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 7 -12. Serialization Requirements for Changing Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 7 -13. Extended Fixed-Range MTRR Type Encodings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
[AMD Public Use]Tables xxxi24593—Rev. 3.41—June 2023 AMD64 Technology
Table 8 -1. Interrupt Vector Source and Cause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 8 -2. Interrupt Vector Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 8 -3. Double-Fault Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 8 -4. Invalid-TSS Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 8 -5. Stack Exception Error Codes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 8 -6. General-Protection Exception Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 8 -7. Data-Type Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 8 -8. Control-Protection Error Codes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 8 -9. Simultaneous Interrupt Priorities  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 8 -10. Simultaneous Floating-Point Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 8 -11. Virtual-8086 Mode Interrupt Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 8 -12. Effect of Instructions that Modify the IF Bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 9 -1. CPU Watchdog Timer Time Base  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 9 -2. CPU Watchdog Timer Count Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 9 -3. Error Logging Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 9 -4. Error Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 10 -1. AMD64 Architecture SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Table 10 -2. Legacy SMM State-Save Area (Not used by AMD64 Architecture) . . . . . . . . . . . . . . . . . . . . 329
Table 10 -3. SMM Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Table 11 -5. SSE Subsets – CPUID Feature Identifiers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Table 11 -6. Extended Save Area Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Table 11 -7. XRSTOR Hardware-Specified Initial Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Table 11 -8. Deriving FSAVE Tag Field from FXSAVE Tag Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Table 12 -1. Effects of Task Nesting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Table 13 -1. Breakpoint-Setting Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Table 13 -2. Breakpoint Location by Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Table 13 -3. Types of Branch Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Table 13 -4. Host/Guest Only Bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Table 13 -5. Count Control Using CNT_MASK and INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Table 13 -6. Operating-System Mode and User Mode Bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Table 13 -7. Supported IBS Filtering Criteria. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Table 13 -8. EventId Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Table 13 -9. Lightweight Profiling CPUID Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Table 13 -10. LWPCB—Lightweight Profiling Control Block Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Table 13 -11. LWPCB Filters Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Table 13 -12. XSAVE Area for LWP Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
[AMD Public Use]xxxii TablesAMD64 Technology 24593—Rev. 3.41—June 2023
Table 14 -1. Initial Processor State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Table 14 -2. Initial State of Segment-Register Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Table 14 -3. x87 Floating-Point State Initialization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Table 14 -4. Processor Operating Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Table 14 -5. Long-Mode Consistency Checks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Table 15 -1. Guest Exception or Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Table 15 -2. EXITINFO1 for MOV CR x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Table 15 -3. EXITINFO1 for MOV DR x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Table 15 -4. EXITINFO1 for INTn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Table 15 -5. EXITINFO1 for INVLPG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Table 15 -6. Guest Instruction Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Table 15 -7. Instruction Intercepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Table 15 -8. MSR Ranges Covered by MSRPM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Table 15 -9. TLB Control Byte Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Table 15 -10. Effect of the GIF on Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Table 15 -11. Guest Exception or Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Table 15 -12. INIT Handling in Different Operating Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Table 15 -13. NMI Handling in Different Operating Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Table 15 -14. SMI Handling in Different Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Table 15 -15. DEV Capability Block, Overall Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Table 15 -16. DEV Capability Header (DEV_HDR) (in PCI Config Space) . . . . . . . . . . . . . . . . . . . . . . . . . 543
Table 15 -17. Encoding of Function Field in DEV_OP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Table 15 -18. DEV_CR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Table 15 -19. Combining Guest and Host PAT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Table 15 -20. Combining PAT and MTRR Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Table 15 -21. GMET Page Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Table 15 -22. Guest vAPIC Register Access Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Table 15 -23. Virtual Interrupt Control (VMCB offset 60h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Table 15 -24. New VMCB Fields Defined by AVIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Table 15 -25. Physical APIC ID Table Entry Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Table 15 -26. Logical APIC ID Table Entry Fields  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Table 15 -27. EXITINFO1 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Table 15 -28. EXITINFO2 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Table 15 -29. ID Field—IPI Delivery Failure Cause  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Table 15 -30. EXITINFO1 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Table 15 -31. EXITINFO2 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
[AMD Public Use]Tables xxxiii24593—Rev. 3.41—June 2023 AMD64 Technology
Table 15 -32. Encryption Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Table 15 -33. SEV/SME Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Table 15 -34. SEV_STATUS MSR Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Table 15 -35. AE Exitcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Table 15 -36. Fields of an RMP Entry  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Table 15 -37. RMP Page Assignment Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Table 15 -38. VMPL Permission Mask Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Table 15 -39. RMP Memory Access Checks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Table 15 -40. PVALIDATE/RMPADJUST Page Size Mismatch Combinations. . . . . . . . . . . . . . . . . . . . . . 611
Table 15 -41. VMRUN Page Checks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Table 15 -42. Non-Coherent Memory Type Conversion  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Table 16 -1. Interrupt Sources for Local APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Table 16 -2. APIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Table 16 -3. Divide Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Table 16 -4. Valid ICR Field Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Table 16 -5. Local APIC Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Table 16 -6. x2APIC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Table 17 -1. CPPC-related MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Table 18 -1. Shadow Stack Operations for Far Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Table 18 -2. Shadow Stack Management Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Table 19 -1. CPUID Fn000_0007_EBX_x0 Extended Feature Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 686
Table 19 -2. PQOS Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Table 19 -3. CPUID Fn0000_000F_x0 PQM Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Table 19 -4. CPUID Fn0000_000F_EDX_x1 PQM Event Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Table 19 -5. Fn8000_0020_EBX_x0 PQM Extended Feature Identifiers  . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Table 19 -6. QM_EVTSEL.EvtID Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Table 19 -7. Counter Size when Fn0000_000F_EAX_x1[CounterSize] = 0 . . . . . . . . . . . . . . . . . . . . . . . . 693
Table 19 -8. Transaction Types and EvtIDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Table 19 -9. BMEC Events and Corresponding Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Table 19 -10. CPUID Fn0000_00010_EDX_x0 PQE Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Table 19 -11. CAT vs. CDP L3 Mask Register Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Table A -1. MSRs of the AMD64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Table A -2. System-Software MSR Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Table A -3. Memory-Typing MSR Cross-Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Table A -4. Machine-Check MSR Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Table A -5. Software-Debug MSR Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
[AMD Public Use]xxxiv TablesAMD64 Technology 24593—Rev. 3.41—June 2023
Table A -6. Performance-Monitoring MSR Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Table A -7. Secure Virtual Machine MSR Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Table A -8. System Management Mode MSR Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Table A -9. CPUID Namestring MSR Cross Reference  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Table A -10. Shadow Stack MSR Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Table A -11. Speculation Control MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Table A -12. Memory Cache MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Table A -13. Quality of Service MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Table A -14. Collaborative Processor Performance Control MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Table B -1. VMCB Layout, Control Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Table B -2. VMCB Layout, State Save Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Table B -3. Swap Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Table B -4. VMSA Layout, State Save Area for SEV-ES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Table C -1. SVM Intercept Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
[AMD Public Use]xxxv24593—Rev. 3.41—June 2023 AMD64 Technology
Date RevisionDescription
June 2023 3.41Added the following corrections/clarifications:
Section 2.5.2, Added that an exception exists when Upper Address

Section 2.5.2, Added that an exception exists when Upper Address 
Ignore (UAI) is enabled.
Section 15.30.4: Removed statement that "software must not attempt 
to read or write the host save-state area directly."
Added AE Exitcode A5h, VMEXIT_BUSLOCK, to Table 15-35
Section 15.36.13: Removed sentence: "Note that the DR6 and DR7 
registers are always swapped as type ‘A’ state for any SEV guest."
Added new MSRs to Table A-1.
Added new features:
Bus Lock: Section 7.3.3, section 8.2.2, Figure 13.2, Figure 13.4, section 13.1.3.6, section 15.14.5, Tables B-1 and C-1.Collaborative Processor Performance Control (CPPC): Section 17.6 and Section A.14.Platform Quality of Service: Chapter 19 and Section A.13.
January 2023 3.40Added the following corrections/clarifications:
Replaced figure 5-17 with correct drawingAdded paragraph at end of section 7.3.2 Corrected description for the “Valid” field in the LastBranchStackToIpMSR documentation in section 13.1.1.9Corrected heading text for first and second columns of table 13-3Corrected heading level of section 13.3.5, IBS FilteringRemoved a duplicate paragraph from section 15.34.10
[AMD Public Use]xxxviAMD64 Technology 24593—Rev. 3.41—June 2023
November 2022 3.39Added corrections/clarifications to:
Write combining memory type in section 7.4
5-level paging in section 5.3
Automatic IBRS in section 3.1.7Section 7.10.9 Secure Multi-Key Memory EncryptionCPUID disable for non-privileged software in section 3.2.10Section 7.6.6 L3 Cache Range ReservationLast Branch Record Stack in section 13.1.1.8Core Performance Global Control Register in section 13.2.1Core Performance Counter Status Registers in section 13.2.1Section 13.3.4.1 IBS FilteringSection 15.21.10 NMI VirtualizationRead Only Guest Page Tables in section 15.25.5Section 15.29.10 x2AVICVMGEXIT Parameter in section 15.35.6VMPL Supervisor Shadow Stack in section 15.36.7Virtual TOM MSR in section 15.36.8SMT Protection for SEV-SNP VMs in section 15.36.17Section 15.36.19 SEV-SNP Instruction VirtualizationSection 15.38 Instruction-Based Sampling Virtualization 
November 2021 3.38Added corrections/clarifications to:  Address generation in Section 4.5.3.  PCID behavior in Section 5.5.  Machine Check Exception in Section 8.2.18.  SEV Status MSR in Section 15.34.10.  SEV_SNP in Sections 15.36.7, .10, .17.  VMCB and VMSA contents in Appendix B.  SVM Intercepts in Appendix C.Added new features:Chapter 5: Upper Address Ignore.Chapter 9, Section 3.2.6 and Appendix A: Machine Check Architecture Extension.Section 15.36: VMSA Register Protection, SEV-SNP VMSA Register Protection and Secure TSC.Date RevisionDescription
[AMD Public Use]xxxvii24593—Rev. 3.41—June 2023 AMD64 Technology
March 2021 3.37Added SPEC_CTRL and PRED_CMD support. 
Added x2APIC support.Added SMM Page Configuration Lock.Corrected the AMD64 Architecture SMM State-Save Area table. Add new section: APERF Read-only (AperfReadOnly).Updated the MSRs of the AMD64 Architecture table.Updated the Machine-Check MSR Cross-Reference table.Updated the Performance-Monitoring MSR Cross-Reference table.Updated the Secure Virtual Machine MSR Cross-Reference table.Added new section: Speculation Control MSRs.
August 2020 3.36 Added Shadow Stack support.Chapter 3: Section 3.1: Added content. Section 3.1.3: Added bit 23 and new content. Section 3.2.7: Added Shadow Stack Registers as new section 3.2.7. Chapter 5: Section 5.6: Updated content. Chapter 6: Added content to Table 6-1. Added section 6.7. Chapter 7: Table 7-3. Updated.Chapter 8: Table 8-1 and Table 8-2: Added content. Section 8.4: Updated content. Section 8.4.2: Added content. Added #CP as new section 8.2.20. Table 8-8: Added content. Added new Shadow Stack section 8.7.6. Section 8.9: Added bullet. Added new 8.9.4.1 section. Chapter 10: Updated Table 10-1. Section 10.4: Added bullet. Chapter 11: Section 11.5.2 and Figure 11-8: Updated table and figure. Section 11.5.8: Updated Table 11-3. Chapter 12: Section 12.2.2: Updated. Section 12.2.4: Updated Figure 12-6. Section 12.3.2: Updated content and added bullets. Chapter 15: Section 15.5.1: Updates. Section 15.15.3: Updated Figure 15-4. Section 15.25.6: Added bullet. Section 15.29.1. Updates. Section 15.29.4.1: Added content. Section 15.29.8.2: Added content.Added Chapter 18.Appendix A: Table A-1: Added content. Added new section A.10. Appendix B: Table B-1, Table B-2, and Table 4: Added content. 
May 2020 3.35Sections 5.6.1 and 5.6.6: Minor updates. Figure 5-16: Updated figure. Date RevisionDescription
[AMD Public Use]xxxviiiAMD64 Technology 24593—Rev. 3.41—June 2023
April 2020 3.34Section 3.1.3: Updated register information. Added PCIDE and PKE 
registers. Updated (TCE) content. Section 5.3.2: Added Process Context Identifier register information and register figure.Section 5.3.3: Updated figure.Section 5.3.4: Updated figure.Section 5.3.5: Updated figure.Section 5.4.1: Added (MPK) register information.Section 5.5.1: Inserted Process Context Identifiers as Section 5.5.1.
Section 5.5.3: Added bullets to Implicit Invalidations list.Section 5.6: Updated content.Section 8.2.15: Added bullet.Section 8.4.2: Updated register figure and added PK register information.Section 11.5.2: Updated register figure and table.Section 14.1.3: Updated table.Section 15.9: Updated table.Appendix B: Updated table.Appendix C: Updated table.Date RevisionDescription
[AMD Public Use]xxxix24593—Rev. 3.41—June 2023 AMD64 Technology
April 2020 3.33Section 1.1.2: Clarification on address size support.
Section 3.2.1: New feature enable bits in SYSCFG MSR.Section 7.6.5: Updated terminology.Section 7.10.6: Clarification to encrypted memory operation.Section 8.1.4: Clarification to IRET and NMI behavior.Tables 8-1 and 8-2: Added #HV exception.Inserted new 8.2.20 section for #HV exception. Section 8.4.2: Changes for SEV-SNP extension.Table 8-8: Added SEV-related exceptions.Figure 10-6: Updated I/O Restart DWORD.Section 15 and 15.1: General updates. Section 15.5.2: Relocated VMLOAD/VMSAVE documentation. Section 15.2.4 and 15.2.6: Updated content. Section 15.6: Added content. Table 15-7: Added content.Section 15.25.6: Clarification. Section 15.25.13: General clarifications. Section 15.33.1 and 15.33.2: General clarifications. Section 15.34.3, 15.34.7, and 15.34.10: Clarifications, and additions for SEV-SNP. Table 15-35: Added content.Section 15.35.8: Corrected terminology.Section 15.36: Added SEV-SNP extension documentation. Table A-1 and Table A-7: Added SEV-SNP related MSRs.Appendix B: Updates for SEV-SNP extension.Table C-1: Added exit code for SEV-SNP extension.
October 2019 3.32 Added UMIP, XSS, GMET, VTE, MCOMMIT, and RDPRU. 
July 2019 3.31Added CLWB and WBNOINVD details.Clarified FP error pointer save/restore behavior.Corrected description of APIC Software Enable functionality.Clarified canonical address checking behavior.Clarified fault generation. June 2023n for instructions that cross page or 
segment boundaries.Date RevisionDescription
[AMD Public Use]xlAMD64 Technology 24593—Rev. 3.41—June 2023
September 2018 3.30Modified Section 7.4 
Modified Section 7.6.4Modified Section 8.5.2Modified Section 9.2Corrected Figure 9-4Corrected Table 9-1Modified Section 9.3.2Corrected Figure 9-6Corrected Table 9-4Modified Section 14.2.3Modified Section 14.4Modified Section 15.6 Modified Section 15.7Modified Section 15.34.9Modified Section 15.34.10Modified Section 15.35.2Corrected Table B-4 in Appendix B
December 2017 3.29Modified Sections 7.10.1 and 7.10.4.Modified Sections 15.34.1, 15.34.7.Added new Section 15.34.10.Modified Section 15.35.10.Modified Appendix A, Table A-7.
March 2017 3.28Modified CR4 Register, Section 3.1.3.Removed UD2 in Table 6-1.Added new bullet in Section 7.1.1.Modified Note in Table 7-1.Added new Section 7.4.1.Clarified Self Modifying Code in Section 7.6.1.Added UD0 and UD1 instructions in Section 8.2.7.Added Instructions Retired Performance counter in Section 13.1.1.Modified Table in Section 15.34.9.Date RevisionDescription
[AMD Public Use]xli24593—Rev. 3.41—June 2023 AMD64 Technology
December 2016 3.27Added Resume Flag (RF) Bit in Section 3.1.6, ”RFLAGS Register,” on page 
51.Added Tom2ForceMemTypeWB in Section 3.2.1, ”System Configuration Register (SYSCFG),” on page 60.
Clarified 
SYSCALL and SYSRET in Section 6.1.1, ”SYSCALL and 
SYSRET,” on page 174.
Added Section 7.3.2, ”Access Atomicity,” on page 195.
Updated Note b in Table 7-12 on page 231.Modified Table 8-1, “Interrupt Vector Source and Cause”‚ on page 245.Modified Table 8-2, “Interrupt Vector Classification”‚ on page 246.Added Section 8.2.22, ”#VC—VMM Communication Exception (Vector 29),” on page 260.
Added a Note in Chapter 10, "System-Management Mode," on page 323.
Added Section 10.5, ”Multiprocessor Considerations,” on page 340.
Updated 
CPUID 8000_001F[EAX] and added CPUID 
8000_001F[EDX] in Section 15.34.1, ”Determining Support for 
SEV ,” on page 589.
Added new Section 15.35, ”Encrypted State (SEV-ES),” on page 595.
Clarified TSC Ratio MSR in Section 15.30.5 ”TSC Ratio MSR (C000_0104h)” on page 585.

Clarified 
Updated 
Modified Appendix B, ”Layout of VMCB” on page 730.Added Table B-3, “Swap Types”‚ on page 739.Added Codes 8Fh, 90h-9Fh, and 403h in Table C-1, “SVM Intercept 
Codes”‚ on page 745.
April 2016 3.26Clarification on loading a null selector into FS or GS added in Section 4.5.3, ”Segment Registers in 64-Bit Mode,” on page 80 Translation table diagrams corrected for definition of bit 8 in Section 5.5, ”Translation-Lookaside Buffer (TLB),” on page 157CR0.CD implementation-dependent behavior noted in Section 7.6.2, ”Cache Control Mechanisms,” on page 206Added clarification on IST usage in Section 8.9.4, ”Interrupt-Stack Table,” on page 284.Added new Section 7.10, ”Secure Memory Encryption,” on page 237.Added guideline for secure AP startup in Section 15.27.8, ”Secure Multiprocessor Initialization,” on page 560
Added TLB maintenance requirement for multiprocessor VM's in Section 
15.29.4, ”VMCB Changes for AVIC,” on page 569.
Added new Section 15.34, ”Secure Encrypted Virtualization,” on page 
588Date RevisionDescription
[AMD Public Use]xliiAMD64 Technology 24593—Rev. 3.41—June 2023
June 2015 3.25Added new section 15.33 Nested Virtualization for coverage of VMSAVE 
and VMLOAD Virtualization and Virtual GIF.
Various minor edits.
October 2013 3.24Added description of Supervisor-Mode Execution Prevention. See Section 
5.6.5 ”Supervisor-Mode Execution Prevention (CR4.SMEP) Bit” on page 163.
Indicated the deprecation of the Processor Feedback Interface. See 
Section 17.4, ”Processor Feedback Interface,” on page 662.
Added Section 17.5, ”Processor Core Power Reporting,” on page 662.
May 2013 3.23Clarified guidelines for implementing cross-modifying code in the sub-section ”Cross-Modifying Code” on page 205.
Added AVIC description. See Section 15.29, ”Advanced Virtual Interrupt Controller,” on page 562.
Added L2I PMC architecture definition. See Section 13.2, ”Performance 
Monitoring Counters,” on page 410.
September 2012 3.22Clarified processor behavior on write of EFER[LMA] bit in Section 3.1.7 
”Extended Feature Enable Register (EFER)” on page 55.
Clarified difference between cold reset and warm reset in Section 9.3, 
”Machine Check Architecture MSRs,” on page 300.
Added information on FFXSR feature bit to Table 11 -5 on page 342. 
Clarified SMM code responsibility to manage VMCB clean bits. See 
Section 15.15.2, ”Guidelines for Clearing VMCB Clean Bits,” on page 525.
Added a note to Table 15 -9 on page 528 to indicate that all encodings of 
TLB_CONTROL not defined are reserved.
Corrected information concerning the assignment of logical APIC IDs in 
Section 16.6.1, ”Receiving System and IPI Interrupts,” on page 638.
March 2012 3.21Added definition of processor feedback interface—frequency sensitivity monitor (See Section 17.4, ”Processor Feedback Interface,” on page 662)
Added Instruction-Based Sampling in a new section of Chapter 13 (See Section 13.3, ”Instruction-Based Sampling,” on page 423.) 
Reworked Introduction and first section of Chapter 9, "Machine Check Architecture," on page 295 and added deferred error handling.
Added description of CR4[FSGSBASE] bit. (See Section 3.1.3, ”CR4 
Register,” on page 46.)
Added references to the RDFSBASE, RDGSBASE, WRFSBASE, and 
WRGSBASE instructions in discussion of FS and GS segment descriptors. (See ”FS and GS Registers in 64-Bit Mode” on page 80)
Added Section 6.3.2, ”Accessing Segment Register Hidden State,” on 
page 179. Date RevisionDescription
[AMD Public Use]xliii24593—Rev. 3.41—June 2023 AMD64 Technology
December 2011 3.20Clarified description of the Cache Disable (CD) memory type in Section 
7.4 ”Memory Types” on page 198.
Added caveat: an overflow of either APERF or MPERF can invalidate the 
effective frequency calculation. See Section 17.3, ”Determining Processor Effective Frequency,” on page 660. 
Other minor editorial changes.
September 2011 3.19Added XSAVEOPT to discussions on XSAVE.
Corrections to discussion on multiprocessor memory access ordering in 
Chapter 7. 
Added discussion of extended core and northbridge performance 
counters and feature indicators to Chapter 13.
Added Lightweight Profiling (LWP) to Chapter 13.Added Global Timestamp Counter, Continuous Mode to LWP descriptionClarification: Function of pin A20M# is only defined in real mode. 
Statement added to Section 1.2.4, ”Real Addressing,” on page 10. 
Eliminated hardware P-state references 
May 2011 3.18Added information for OSXSAVE and XSAVE features.Added Cache Topology, Pause Filter Threshold, and XSETBV information.Updated TSC ratio information.Corrected description of FXSAVE/FXRSTOR exception behavior when 
CR0.EM=1
June 2010 3.17Replaced missing figures in Chapter 8, "Exceptions and Interrupts," on page 241.
June 2010 3.16Updated information on performance monitoring counters in ”Performance-Monitoring Counter Enable (PCE)” on page 49 and 6.2.5, 
”Accessing Model-Specific Registers” on page 178.
Revised Table 4-1, ”Segment Registers” on page 79.Add flush by ASID information to section 15.16, ”TLB Control” on page 
527.
Added information on VMCB clean field to Chapter15, ”Secure Virtual 
Machine” on page 497 and Appendix B, ”Layout of VMCB” on page 730.
Added section 15.10, ”IOIO Intercepts” on page 515.
Added section 15.30.5, ”TSC Ratio MSR (C000_0104h)” on page 585.
Added section 17.2, ”Core Performance Boost” on page 659.Date RevisionDescription
[AMD Public Use]xlivAMD64 Technology 24593—Rev. 3.41—June 2023
November 2009 3.15Added section 7.5, ”Buffering and Combining Memory Writes” on page 
201
Added MFENCE to list of ”Serializing Instructions” on page 210.Updated section 7.6.1, ”Cache Organization and Operation” on page 203.
Updated Table 7-4, “Memory Access Ordering Rules”‚ on page 200 and 
notes.Updated 7.4, ”Memory Types” on page 198.Clarified 5.5.3, ”TLB Management” on page 159.Added ”Invalidation of Table Entry Upgrades.” on page 160.Updated ”Speculative Caching of Address Translations” on page 160.
Update ”Handling of D-Bit Updates” on page 161.Revised and updated section 7.2, ”Multiprocessor Memory Access 
Ordering” on page 189 ff.
Added information on long mode segment-limit checks in ”Extended Feature Enable Register (EFER)” on page 56table on page 56 and ”Long Mode Segment Limit Enable (LMSLE) bit” on page 57 on page 57.
Added discussion of ”Data Limit Checks in 64-bit Mode” on page 123on 
page 123.Updated Table 6-1, “System Management Instructions”‚ on page 170.
Updated ”Canonicalization and Consistency Checks” on page 503on page 
503.
Added information about the next sequential instruction pointer (nRIP) in 
15.7.1, ”State Saved on Exit” on page 507.
Updated priority definition of PAUSE instruction intercept in Table 15 -7, 
“Instruction Intercepts”‚ on page 512.Added nRIP field to Table B-1, “VMCB Layout, Control Area”‚ on 
page 730.
Clarified information on ICEBP event injection, on page 530.
Deleted erroneous statement concerning the operation of the General 
Local Vector Table register Mask bit in section 16.4.
Clarified the description of the Interrupt Command Register Delivery 
Status bit in section ”Interprocessor Interrupts (IPI)” on page 634on page 634.Date RevisionDescription
[AMD Public Use]xlv24593—Rev. 3.41—June 2023 AMD64 Technology
September
20073.14Added information on ”Speculative Caching of Address Translations,” 
”Caching of Upper Level Translation Table Entries,” ”Use of Cached Entries When Reporting a Page Fault Exception,” ”Use of Cached Entries When Reporting a Page Fault Exception,” ”Handling of D-Bit Updates,” ”Invalidation of Cached Upper-level Entries by INVLPG” on page 161 and 
”Handling of PDPT Entries in PAE Mode” on page 161to section 5.5.3, 
”TLB Management” on page 159.
Added 15.21.7, ”Interrupt Masking in Local APIC” on page 534.
Added 16.3.6, ”Extended APIC Control Register” on page 626; clarified 
the use of the ICR DS bit in 16.5, ”Interprocessor Interrupts (IPI)” on page 634.
Added minor clarifications and corrected typographical and formatting 
errors.
July 2007 3.13Added 5.3.5, ”1-Gbyte Page Translation” on page 149.
Added 7.2, ”Multiprocessor Memory Access Ordering” on page 189Added divide-by-zero exception to Table 8-9, “Simultaneous Interrupt 
Priorities”‚ on page 263.Added information on ”CPU Watchdog Timer Register” on page 303and 
”Machine-Check Miscellaneous-Error Information Register 0 (MCi_MISC0)” on page 310to Chapter 9.
Added SSE4A support to Chapter 11, ”SSE, MMX, and x87 Programming” 
on page 341.
Added Monitor and MWAIT intercept information to section 15.9, 
”Instruction Intercepts” on page 512 and reorganized intercept 
information; clarified 15.16.1, ”TLB Flush” on page 528.
Added Monitor and MWAIT intercepts to tables B-1, ”VMCB Layout, Control Area” on page 730 and C-1, ”SVM Intercept Codes” on page 745.
Added Chapter 16, ”Advanced Programmable Interrupt Controller 
(APIC)” on page 620, Chapter 17, ”OS-Visible Workaround Information” on page 515, Chapter 17, ”Hardware Performance Monitoring and 
Control” on page 657.

Added Table A-7, “Secure Virtual Machine MSR Cross-Reference”‚ on 
page 726.
errors.
September
20063.12 Added numerous minor clarifications.
December 2005 3.11Added Chapter 15, Secure Virtual Machine. Incorporated numerous factual corrections and updates.
February 2005 3.10Corrected Table 8-6, “General-Protection Exception Conditions”‚ on page 254. Added SSE3 information. Clarified and corrected information on the CPUID instruction and feature identification. Added information on the RDTSCP instruction. Clarified information about MTRRs and PATs in multiprocessing systems.Date RevisionDescription
[AMD Public Use]xlviAMD64 Technology 24593—Rev. 3.41—June 2023
September
20033.09 Corrected numerous minor typographical errors.
April 2003 3.08Clarified terms in section on FXSAVE/FXSTOR. Corrected several minor 
errors of omission. Documentation of CR0.NW bit has been corrected. Several register diagrams and figure labels have been corrected. Description of shared cache lines has been clarified in 7.3, ”Memory Coherency and Protocol” on page 192.
September
20023.07Made numerous small grammatical changes and factual clarifications. Added Revision History.Date RevisionDescription
[AMD Public Use]xlvii24593—Rev. 3.41—June 2023 AMD64 Technology
Preface
About This Book
This book is part of a multivolume work entitled the AMD64 Architecture Programmer’s Manual. This 
table lists each volume and its order number. 
Audience
This volume (V olume 2) is intended for programmers writing operating systems, loaders, linkers, device drivers, or system utilities. It assumes an understanding of AMD64 architecture application-level programming as described in V olume 1.
This volume describes the AMD64 architecture’s resources and functions that are managed by system 
software, including operating-mode control, memory management, interrupts and exceptions, task and state-change management, system-management mode (including power management), multi-processor support, debugging, and processor initialization.
Application-programming topics are described in V olume 1. Details about each instruction are 
described in V olumes 3, 4, and 5.
Organization
This volume begins with an overview of system programming and differences between the x86 and AMD64 architectures. This is followed by chapters that describe the following details of system programming:
•System Resources —The system registers and processor ID (CPUID) functions. 
•Segmented Virtual Memory —The segmented-memory models supported by the architecture and
their associated data structures and protection checks. 
•Page Translation and Protection —The page-translation functions supported by the architecture
and their associated data structures and protection checks. Title Order No.
Volume 1: Application Programming 24592
Volume 2: System Programming 24593
Volume 3: General-Purpose and System Instructions 24594
Volume 4: 128-Bit and 256-Bit Media Instructions 26568
Volume 5: 64-Bit Media and x87 Floating-Point Instructions 26569
[AMD Public Use]xlviiiAMD64 Technology 24593—Rev. 3.41—June 2023
•System Instructions —The instructions used to manage system functions. 
•Memory System —The memory-system hierarchy and its resources and protocols, including
memory-characterization, caching, and buffering functions. 
•Exceptions and Interrupts—Details about the types and causes of exceptions and interrupts, and
the methods of transferring control during these events. 
•Machine-Check Mechanism —The resources and functions that support detection and handling of
machine-check errors. 
•System-Management Mode—The resources and functions that support system-management mode(SMM), including power-management functions. 
•SSE, MMX, and x87 Programming —The resources and functions that support use (by application
software) and state-saving (by the operation system) of the 256-bit media, 128-bit media, 64-bitmedia, and x87 floating-point instructions. 
•Multiple-Processor Management —The features of the instruction set and the system resources and
functions that support multiprocessing environments. 
•Debug and Performance Resources —The system resources and functions that support software
debugging and performance monitoring. 
•Legacy Task Management—Support for the legacy hardware multitasking functions, includingregister resources and data structures. 
•Processor Initialization and Long-Mode Activation—The methods by which system softwareinitializes and changes operating modes. 
•Mixing Code Across Operating Modes —Things to remember when running programs in different
operating modes. 
•Secure Virtual Machine —The system resources that support machine virtualization. 
•Advanced Programmable Interrupt Controller (APIC) operation . 
There are appendices describing details of model-specific registers (MSRs) and machine-check implementations. Definitions assumed throughout this volume are listed below. The index at the end of this volume cross-references topics within the volume. For other topics relating to the AMD64 architecture, see the tables of contents and indexes of the other volumes. 
Conventions and Definitions
The section which follows, Notational Conventions,  describes notational conventions used in this 
volume. The next section, Definitions,  lists a number of terms used in this volume along with their 
technical definitions. Some of these definitions assume knowledge of the legacy x86 architecture. See “Related Documents” on page lix for further information about the legacy x86 architecture. Finally, the Registers  section lists the registers which are a part of the system programming model.
[AMD Public Use]xlix24593—Rev. 3.41—June 2023 AMD64 Technology
Notational Conventions
#GP(0)
An instruction exception—in this example, a general-protection exception with error code of 0. 
1011b
A binary value—in this example, a 4-bit value. 
F0EA_0B02h
A hexadecimal value. Underscore characters may be inserted to improve readability. 
128
Numbers without an alpha suffix are decimal unless the context indicates otherwise.
7:4
A bit range, from bit 7 to 4, inclusive. The high-order bit is shown first. Commas may be inserted
to indicate gaps.
CPUID Fn XXXX_XXXX_RRR [FieldName ]
Support for optional features or the value of an implementation-specific parameter of a processorcan be discovered by executing the CPUID instruction on that processor. To obtain this value,software must execute the CPUID instruction with the function code XXXX_XXXX h in EAX and
then examine the field FieldName  returned in register RRR. If the “ _RRR ” notation is followed by
“_xYYY”, register ECX must be set to the value YYYh before executing CPUID. When FieldName
is not given, the entire contents of register RRR  contains the desired value. When determining
optional feature support, if the bit identified by FieldName  is set to a one, the feature is supported
on that processor.
CR0–CR4
A register range, from register CR0 through CR4, inclusive, with the low-order register first. 
CR0[PE], CR0.PE
Notation for referring to a field within a register—in this case, the PE field of the CR0 register.
CR0[PE] = 1, CR0.PE = 1
The PE field of the CR0 register is set (contains the value 1).
EFER[LME] = 0, EFER.LME = 0
The LME field of the EFER register is cleared (contains a value of 0).
DS:SI
A far pointer or logical address. The real address or segment descriptor specified by the segmentregister (DS in this example) is combined with the offset contained in the second register (SI in thisexample) to form a real or virtual address.
[AMD Public Use]lAMD64 Technology 24593—Rev. 3.41—June 2023
RFLAGS[13:12]
A field within a register identified by its bit range. In this example, corresponding to the IOPL
field.
16-bit mode
Legacy mode or compatibility mode in which a 16-bit address size is active. See legacy mode  and
compatibility mode .
32-bit mode
Legacy mode or compatibility mode in which a 32-bit address size is active. See legacy mode  and
64-bit mode
A submode of long mode. In 64-bit mode, the default address size is 64 bits and new features, such
as register extensions, are supported for system and application software. 
absolute
Said of a displacement that references the base of a code segment rather than an instruction pointer.
Contrast with relative .
ASID
Address space identifier.
byte
Eight bits. 
clear
To write a bit value of 0. Compare set. 
compatibility mode
A submode of long mode. In compatibility mode, the default address size is 32 bits, and legacy 16-
bit and 32-bit applications run without modification. 
commit
To irreversibly write, in program order, an instruction’s result to software-visible storage, such as aregister (including flags), the data cache, an internal write buffer, or memory.
CPL
Current privilege level.
direct

absolute
ASID
byte
clear
commit
CPL
direct
Referencing a memory location whose address is included in the instruction’s syntax as animmediate operand. The address may be an absolute or relative address. Compare indirect .
[AMD Public Use]li24593—Rev. 3.41—June 2023 AMD64 Technology
dirty data
Data held in the processor’s caches or internal buffers that is more recent than the copy held in
main memory.
displacement
A signed value that is added to the base of a segment (absolute addressing) or an instruction pointer(relative addressing). Same as offset .
doubleword
Two words, or four bytes, or 32 bits. 
double quadword
Eight words, or 16 bytes, or 128 bits. Also called octword . 
effective address size
The address size for the current instruction after accounting for the default address size and anyaddress-size override prefix. 
effective operand size
The operand size for the current instruction after accounting for the default operand size and anyoperand-size override prefix. 
exception
An abnormal condition that occurs as the result of executing an instruction. The processor’sresponse to an exception depends on the type of the exception. For all exceptions except 128-bitmedia SIMD floating-point exceptions and x87 floating-point exceptions, control is transferred tothe handler (or service routine) for that exception, as defined by the exception’s vector. Forfloating-point exceptions defined by the IEEE 754 standard, there are both masked and unmaskedresponses. When unmasked, the exception handler is called, and when masked, a default responseis provided instead of calling the handler. 
flush
An often ambiguous term meaning (1) writeback, if modified, and invalidate, as in “flush the cacheline,” or (2) invalidate, as in “flush the pipeline,” or (3) change a value, as in “flush to zero.”
GDT
Global descriptor table.
GIF
Global interrupt flag.
GPA
Guest physical address. In a virtualized environment, the page tables maintained by the guestoperating system provide the translation from the linear (virtual) address to the guest physical
[AMD Public Use]liiAMD64 Technology 24593—Rev. 3.41—June 2023
address. Nested page tables define the translation of the GPA to the host physical address (HPA).
See SP A and HP A.
HPA
Host physical address. The address space owned by the virtual machine monitor. In a virtualizedenvironment, nested page translation tables controlled by the VMM provide the translation fromthe guest physical address to the host physical address. See GP A.
IDT
Interrupt descriptor table.
IGN
Ignored. Value written is ignored by hardware. Value returned on a read is indeterminate. Seereserved .
indirect
Referencing a memory location whose address is in a register or other memory location. Theaddress may be an absolute or relative address. Compare direct .
IRB
The virtual-8086 mode interrupt-redirection bitmap.
IST
The long-mode interrupt-stack table.
IVT
The real-address mode interrupt vector table.
LDT
Local descriptor table.
legacy x86
The legacy x86 architecture. See “Related Documents” on page lix for descriptions of the legacyx86 architecture. 
legacy mode
An operating mode of the AMD64 architecture in which existing 16-bit and 32-bit applications andoperating systems run without modification. A processor implementation of the AMD64architecture can run in either long mode  or legacy mode . Legacy mode has three submodes, real
mode , protected mode , and virtual-8086 mode . 
LIP
Linear Instruction Pointer. LIP = (CS.base + rIP).
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long mode
An operating mode unique to the AMD64 architecture. A processor implementation of the
AMD64 architecture can run in either long mode or legacy mode . Long mode has two submodes,
64-bit mode  and compatibility mode . 
lsb
Least-significant bit.
LSB
Least-significant byte.
main memory
Physical memory, such as RAM and ROM (but not cache memory) that is installed in a particularcomputer system. 
mask
(1) A control bit that prevents the occurrence of a floating-point exception from invoking anexception-handling routine. (2) A field of bits used for a control purpose. 
MBZ
Must be zero. If software attempts to set an MBZ bit to 1 in a system register, a general-protectionexception (#GP) occurs; if in a translation table entry, a reserved-bit page fault exception (#PF)will occur if the hardware attempts to use the entry for address translation. See reserved .
memory
Unless otherwise specified, main memory . 
ModRM
A byte following an instruction opcode that specifies address calculation based on mode (Mod),register (R), and memory (M) variables. 
moffset
A 16, 32, or 64-bit offset that specifies a memory operand directly, without using a ModRM or SIBbyte.
msb
Most-significant bit.
MSB
Most-significant byte.
octword
Same as double quadword. 
offset
Same as displacement .
[AMD Public Use]livAMD64 Technology 24593—Rev. 3.41—June 2023
overflow
The condition in which a floating-point number is larger in magnitude than the largest, finite,
positive or negative number that can be represented in the data-type format being used.
PAE
Physical-address extensions.
physical memory
Actual memory, consisting of main memory  and cache. 
probe
A check for an address in a processor’s caches or internal buffers. External probes  originate
outside the processor, and internal probes originate within the processor.
procedure stack
A portion of a stack segment in memory that is used to link procedures. Also known as a program
stack.
program stack
See procedure stack.
protected mode
A submode of legacy mode . 
quadword
Four words, or eight bytes, or 64 bits. 
RAZ
Value returned on a read is always zero (0) regardless of what was previously written. See
reserved .
RA1
Value returned on a read is always one (1) regardless of what was previously written. See reserved .
real-address mode
See real mode . 
real mode
A short name for real-address mode,  a submode of legacy mode .
relative
Referencing with a displacement (also called offset) from an instruction pointer rather than thebase of a code segment. Contrast with absolute .
[AMD Public Use]lv24593—Rev. 3.41—June 2023 AMD64 Technology
reserved
Fields marked as reserved may be used at some future time.
To preserve compatibility with future processors, reserved fields require special handling when
read or written by software. Software must not depend on the state of a reserved field (unlessqualified as RAZ), nor upon the ability of such fields to return a previously written state.
If a field is marked reserved without qualification, software must not change the state of that field;
it must reload that field with the same value returned from a prior read.
Reserved fields may be qualified as IGN, MBZ, RAZ, or SBZ (see definitions).
REX
An instruction prefix that specifies a 64 -bit operand size and provides access to additional
registers. 
RIP-relative addressing
Addressing relative to the 64 -bit RIP instruction pointer.
SBZ
Should be zero. An attempt by software to set an SBZ bit to 1 results in undefined behavior. See
reserved .
shadow stack
A shadow stack is a separate, protected stack that is conceptually parallel to the procedure stack
and used only by the shadow stack feature.
set
To write a bit value of 1. Compare clear. 
SIB
A byte following an instruction opcode that specifies address calculation based on scale (S), index
(I), and base (B). 
SPA
System physical address. The address directly used to address system memory. Under SVM, alsoknown as the host physical address. See HP A.
sticky bit
A bit that is set or cleared by hardware and that remains in that state until explicitly changed bysoftware. 
SVM
Secure virtual machine. AMD’s virtualization architecture. SVM is defined in Chapter 15 onpage 497.
[AMD Public Use]lviAMD64 Technology 24593—Rev. 3.41—June 2023
System software
Privileged software that owns and manages the hardware resources of a system after initialization
by system firmware  and controls access to these resources. In a non-virtualized environment,
system software is provided by the operating system. In a virtualized environment, systemsoftware is largely equivalent to the virtual machine monitor (VMM), also commonly known asthe hypervisor .
TOP
The x87 top-of-stack pointer. 
TSS
Task-state segment.
underflow
The condition in which a floating-point number is smaller in magnitude than the smallest nonzero,positive or negative number that can be represented in the data-type format being used.
vector
(1) A set of integer or floating-point values, called elements , that are packed into a single data
object. Most of the SSE and 64-bit media instructions use vectors as operands.
(2) An index into an interrupt descriptor table (IDT), used to access exception handlers. Compareexception. 
virtual-8086 mode
VMCB
Virtual machine control block.
VMM
Virtual machine monitor.
word
Two bytes, or 16 bits. 
x86
See legacy x86 . 
Registers

TOP
TSS
underflow
vector
VMCB
VMM
word
x86
Registers
In the following list of registers, the names are used to refer either to a given register or to the contents 
of that register:
AH–DH
The high 8-bit AH, BH, CH, and DH registers. Compare AL–DL. 
[AMD Public Use]lvii24593—Rev. 3.41—June 2023 AMD64 Technology
AL–DL
The low 8-bit AL, BL, CL, and DL registers. Compare AH–DH. 
AL–r15B
The low 8-bit AL, BL, CL, DL, SIL, DIL, BPL, SPL, and R8B–R15B registers, available in 64-bit
mode.
BP
Base pointer register.
CRn
Control register number n.
CS
Code segment register.
eAX–eSP
The 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers. Compare rAX–rSP . 
EFER
Extended features enable register.
eFLAGS
16-bit or 32-bit flags register. Compare rFLAGS . 
EFLAGS
32-bit (extended) flags register.
eIP
16-bit or 32-bit instruction-pointer register. Compare rIP. 
EIP
32-bit (extended) instruction-pointer register.
FLAGS
16-bit flags register.
GDTR
Global descriptor table register.
GPRs
General-purpose registers. For the 16-bit data size, these are AX, BX, CX, DX, DI, SI, BP, and SP.For the 32-bit data size, these are EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP. For the 64-bitdata size, these include RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, and R8–R15. 
[AMD Public Use]lviiiAMD64 Technology 24593—Rev. 3.41—June 2023
IDTR
Interrupt descriptor table register.
IP
16-bit instruction-pointer register.
LDTR
Local descriptor table register.
MSR
Model-specific register. 
r8–r15
The 8-bit R8B–R15B registers, or the 16-bit R8W–R15W registers, or the 32-bit R8D–R15D
registers, or the 64-bit R8–R15 registers. 
rAX–rSP
The 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers, or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers, or the 64-bit RAX, RBX, RCX, RDX, RDI, RSI, RBP, and RSPregisters. Replace the placeholder r with nothing for 16-bit size, “E” for 32-bit size, or “R” for 64-
bit size. 
RAX
64-bit version of the EAX register.
RBP
64-bit version of the EBP register.
RBX
64-bit version of the EBX register.
RCX
64-bit version of the ECX register.
RDI
64-bit version of the EDI register.
RDX
64-bit version of the EDX register.
rFLAGS
16-bit, 32-bit, or 64-bit flags register. Compare RFLAGS . 
RFLAGS
64-bit flags register. Compare rFLAGS . 
[AMD Public Use]lix24593—Rev. 3.41—June 2023 AMD64 Technology
rIP
16-bit, 32-bit, or 64-bit instruction-pointer register. Compare RIP. 
RIP
64-bit instruction-pointer register. 
RSI
64-bit version of the ESI register.
RSP
64-bit version of the ESP register.
SP
Stack pointer register.
SS
Stack segment register.
SSP
Shadow-stack pointer register.
TPR
Task priority register (CR8), a new register introduced in the AMD64 architecture to speed
interrupt management. 
TR
Task register.
YMM/XMM
Set of sixteen (eight accessible in legacy and compatibility modes) 256-bit wide registers that holdscalar and vector operands used by the SSE instructions.
Endian Order
The x86 and AMD64 architectures address memory using little-endian byte-ordering. Multibyte 
values are stored with their least-significant byte at the lowest byte address, and they are illustrated with their least significant byte at the right side. Strings are illustrated in reverse order, because the addresses of their bytes increase from right to left. 
Related Documents
•Peter Abel, IBM PC Assembly Language and Programming , Prentice-Hall, Englewood Cliffs, NJ,
1995. 
•Rakesh Agarwal, 80x86 Architecture & Programming: Volume II, Prentice-Hall, Englewood
Cliffs, NJ, 1991. 
[AMD Public Use]lxAMD64 Technology 24593—Rev. 3.41—June 2023
•AMD, BIOS and Kernel Developer’s Guide  (BKDG) for particular hardware implementations of
older families of the AMD64 architecture. 
•AMD, Processor Programming Reference (PPR) for particular hardware implementations of
newer families of the AMD64 architecture. 
•AMD, AMD I/O Virtualization Technology (IOMMU) Specification , Revision 2.2 or later; order
number 48882.
•AMD, Software Optimization Guide for AMD Family 15h Processors, order number 47414.
•Don Anderson and Tom Shanley, Pentium  Processor System Architecture , Addison-Wesley, New
York, 1995. 
•Nabajyoti Barkakati and Randall Hyde, Microsoft Macro Assembler Bible , Sams, Carmel, Indiana,
1992. 
•Barry B. Brey, 8086/8088, 80286, 80386, and 80486 Assembly Language Programming ,
Macmillan Publishing Co., New York, 1994. 
•Barry B. Brey, Programming the 80286, 80386, 80486, and Pentium Based Personal Computer ,
Prentice-Hall, Englewood Cliffs, NJ, 1995. 
•Ralf Brown and Jim Kyle, PC Interrupts, Addison-Wesley, New York, 1994. 
•Penn Brumm and Don Brumm, 80386/80486 Assembly Language Programming, Windcrest
McGraw-Hill, 1993. 
•Geoff Chappell, DOS Internals, Addison-Wesley, New York, 1994. 
•Chips and Technologies, Inc. Super386 DX Programmer’s Reference Manual, Chips and
Technologies, Inc., San Jose, 1992. 
•John Crawford and Patrick Gelsinger, Programming the 80386 , Sybex, San Francisco, 1987. 
•Cyrix Corporation, 5x86 Processor BIOS Writer's Guide , Cyrix Corporation, Richardson, TX,
1995. 
•Cyrix Corporation, M1 Processor Data Book , Cyrix Corporation, Richardson, TX, 1996. 
•Cyrix Corporation, MX Processor MMX Extension Opcode Table , Cyrix Corporation, Richardson,
TX, 1996. 
•Cyrix Corporation, MX Processor Data Book , Cyrix Corporation, Richardson, TX, 1997. 
•Ray Duncan, Extending DOS: A Programmer's Guide to Protected-Mode DOS, Addison Wesley,
NY , 1991.
•William B. Giles, Assembly Language Programming for the Intel 80xxx Family , Macmillan, New
York, 1991. 
•Frank van Gilluwe, The Undocumented PC, Addison-Wesley, New York, 1994. 
•John L. Hennessy and David A. Patterson, Computer Architecture, Morgan Kaufmann Publishers,
San Mateo, CA, 1996. 
•Thom Hogan, The Programmer’s PC Sourcebook , Microsoft Press, Redmond, WA, 1991. 
•Hal Katircioglu, Inside the 486, Pentium, and Pentium Pro, Peer-to-Peer Communications, Menlo
Park, CA, 1997. 
[AMD Public Use]lxi24593—Rev. 3.41—June 2023 AMD64 Technology
•IBM Corporation, 486SLC Microprocessor Data Sheet , IBM Corporation, Essex Junction, VT,
1993.
•IBM Corporation, 486SLC2 Microprocessor Data Sheet , IBM Corporation, Essex Junction, VT,
1993. 
•IBM Corporation, 80486DX2 Processor Floating Point Instructions, IBM Corporation, Essex
Junction, VT, 1995. 
•IBM Corporation, 80486DX2 Processor BIOS Writer's Guide , IBM Corporation, Essex Junction,
VT, 1995. 
•IBM Corporation, Blue Lightning 486DX2 Data Book, IBM Corporation, Essex Junction, VT,
1994.
•Institute of Electrical and Electronics Engineers,  IEEE Standard for Binary Floating-Point
Arithmetic , ANSI/IEEE Std 754-1985. 
•Institute of Electrical and Electronics Engineers,  IEEE Standard for Radix-Independent Floating-
Point Arithmetic, ANSI/IEEE Std 854-1987. 
•Muhammad Ali Mazidi and Janice Gillispie Mazidi, 80X86 IBM PC and Compatible Computers,
Prentice-Hall, Englewood Cliffs, NJ, 1997.
•Hans-Peter Messmer, The Indispensable Pentium Book, Addison-Wesley, New York, 1995. 
•Karen Miller, An Assembly Language Introduction to Computer Architecture: Using the Intel
Pentium , Oxford University Press, New York, 1999. 
•Stephen Morse, Eric Isaacson, and Douglas Albert, The 80386/387 Architecture, John Wiley &
Sons, New York, 1987. 
•NexGen Inc. , Nx586TM Processor Data Book , NexGen Inc., Milpitas, CA, 1993.
•NexGen Inc. , Nx686TM Processor Data Book , NexGen Inc., Milpitas, CA, 1994.
•Bipin Patwardhan, Introduction to the Streaming SIMD Extensions in the Pentium® III ,
www.x86.org/articles/sse_pt1/ simd1.htm, June, 2000. 
•Peter Norton, Peter Aitken, and Richard Wilton, PC Programmer’s Bible, Microsoft Press,
Redmond, WA, 1993. 
•PharLap 386|ASM Reference Manual , Pharlap, Cambridge MA, 1993.
•PharLap TNT DOS-Extender Reference Manual , Pharlap, Cambridge MA, 1995.
•Sen-Cuo Ro and Sheau-Chuen Her, i386/i486 Advanced Programming, Van Nostrand Reinhold,
New York, 1993. 
•Jeffrey P. Royer, Introduction to Protected Mode Programming, course materials for an onsite
class, 1992. 
•Tom Shanley, Protected Mode System Architecture , Addison Wesley, NY , 1996. 
•SGS-Thomson Corporation, 80486DX Processor SMM Programming Manual , SGS-Thomson
Corporation, 1995. 
•Walter A. Triebel, The 80386DX Microprocessor , Prentice-Hall, Englewood Cliffs, NJ, 1992. 
•John Wharton, The Complete x86 , MicroDesign Resources, Sebastopol, California, 1994. 
[AMD Public Use]1 System-Programming OverviewAMD64 Technology 24593—Rev. 3.41—June 2023
1 System-Programming Overview
This entire volume is intended for system-software developers—programmers writing operating 
systems, loaders, linkers, device drivers, or utilities that require access to system resources. These system resources are generally available only to software running at the highest-privilege level (CPL=0), also referred to as privileged software. Privilege levels and their interactions are fully 
described in “Segment-Protection Overview” on page 104.
This chapter introduces the basic features and capabilities of the AMD64 architecture that are 
available to system-software developers. The concepts include:

•The supported address forms and how memory is organized. 
•How memory-management hardware makes use of the various address forms to access memory. 
•The processor operating modes, and how the memory-management hardware supports each of 
those modes.
•The system-control registers used to manage system resources.
•The interrupt and exception mechanism, and how it is used to interrupt program execution and to report errors.
•Additional, miscellaneous features available to system software, including support for hardware multitasking, reporting machine-check exceptions, debugging software problems, and optimizing software performance.
Many of the legacy features and capabilities are enhanced by the AMD64 architecture to support 64-bit operating systems and applications, while providing backward-compatibility with existing software.
1.1 Memory Model
The AMD64 architecture memory model is designed to allow system software to manage application software and associated data in a secure fashion. The memory model is backward-compatible with the legacy memory model. Hardware-translation mechanisms are provided to map addresses between virtual-memory space and physical-memory space. The translation mechanisms allow system software to relocate applications and data transparently, either anywhere in physical-memory space, or in areas on the system hard drive managed by the operating system. 
In long mode, the AMD64 architecture implements a flat-memory model. In legacy mode, the 
architecture implements all legacy memory models.
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1.1.1  Memory Addressing
The AMD64 architecture supports address relocation. To do this, several types of addresses are needed 
to completely describe memory organization. Specifically, four types of addresses are defined by the AMD64 architecture:
•Logical addresses
•Effective addresses, or segment offsets, which are a portion of the logical address.
•Linear (virtual) addresses
•Physical addresses
Logical Addresses.  A logical address  is a reference into a segmented-address space. It is comprised 
of the segment selector and the effective address. Notationally, a logical address is represented as
Logical Address = Segment Selector : Offset
The segment selector specifies an entry in either the global or local descriptor table. The specified 
descriptor-table entry describes the segment location in virtual-address space, its size, and other characteristics. The effective address is used as an offset into the segment specified by the selector.
Logical addresses are often referred to as far pointers . Far pointers are used in software addressing 
when the segment reference must be explicit (i.e., a reference to a segment outside the current 
segment). 
Effective Addresses.  The offset into a memory segment is referred to as an effective address (see 
“Segmentation” on page 5 for a description of segmented memory). Effective addresses are formed by adding together elements comprising a base value, a scaled-index value, and a displacement value. The effective-address computation is represented by the equation
Effective Address = Base + (Scale x Index) + Displacement
The elements of an effective-address computation are defined as follows:
•Base —A value stored in any general-purpose register.
•Scale —A positive value of 1, 2, 4, or 8.
•Index —A two’s-complement value stored in any general-purpose register.
•Displacement —An 8-bit, 16-bit, or 32-bit two’s-complement value encoded as part of the 
Effective addresses are often referred to as near pointers . A near pointer is used when the segment 
selector is known implicitly or when the flat-memory model is used.
Long mode defines a 64-bit effective-address length. If a processor implementation does not support 
the full 64-bit virtual-address space, the effective address must be in canonical form (see “Canonical 
Address Form” on page 4).
[AMD Public Use]3 System-Programming OverviewAMD64 Technology 24593—Rev. 3.41—June 2023
Linear (Virtual) Addresses.  The segment-selector portion of a logical address specifies a segment-
descriptor entry in either the global or local descriptor table. The specified segment-descriptor entry 
contains the segment-base address, which is the starting location of the segment in linear-address space. A linear address  is formed by adding the segment-base address to the effective address 
(segment offset), which creates a reference to any byte location within the supported linear-address space. Linear addresses are often referred to as virtual addresses , and both terms are used 
interchangeably throughout this document.
Linear Address = Segment Base Address + Effective Address
When the flat-memory model is used—as in 64-bit mode—a segment-base address is treated as 0. In this case, the linear address is identical to the effective address. In long mode, linear addresses must be in canonical address form, as described in “Canonical Address Form” on page 4.
Physical Addresses.  A physical address is a reference into the physical-address space, typically 
main memory. Physical addresses are translated from virtual addresses using page-translation mechanisms. See “Paging” on page 7 for information on how the paging mechanism is used for virtual-address to physical-address translation. When the paging mechanism is not enabled, the virtual (linear) address is used as the physical address.
1.1.2  Memory Organization
The AMD64 architecture organizes memory into virtual memory  and physical memory . Virtual-
memory and physical-memory spaces can be (and usually are) different in size. Generally, the virtual-
address space is much larger than physical-address memory. System software relocates applications and data between physical memory and the system hard disk to make it appear that much more memory is available than really exists. System software then uses the hardware memory-management mechanisms to map the larger virtual-address space into the smaller physical-address space.
Virtual Memory.  Software uses virtual addresses to access locations within the virtual-memory 
space. System software is responsible for managing the relocation of applications and data in virtual-memory space using segment-memory management. System software is also responsible for mapping virtual memory to physical memory through the use of page translation. The AMD64 architecture supports different virtual-memory sizes using the following address-translation modes:
•Protected Mode —This mode supports 4 gigabytes of virtual-address space using 32-bit virtual 
•Long Mode —This mode supports 16 exabytes of virtual-address space using 64-bit virtual 
addresses. A given implementation may however support less than this, as reported by the CPUID 
feature identification facility.
[AMD Public Use]System-Programming Overview 424593—Rev. 3.41—June 2023 AMD64 Technology
Physical Memory.  Physical addresses are used to directly access main memory. For a particular 
computer system, the size of the available  physical-address space is equal to the amount of main 
memory installed in the system. The maximum amount of physical memory accessible depends on the 
processor implementation and on the address-translation mode. The AMD64 architecture supports varying physical-memory sizes using the following address-translation modes:
•Real-Address Mode—This mode, also called real mode , supports 1 megabyte of physical-address 
space using 20-bit physical addresses. This address-translation mode is described in “Real 
Addressing” on page 10. Real mode is available only from legacy mode (see “Legacy Modes” on 
page 14). 
•Legacy Protected Mode —This mode supports several different address-space sizes, depending on 
the translation mechanism used and whether extensions to those mechanisms are enabled.
Legacy protected mode supports 4 gigabytes of physical-address space using 32-bit physical
addresses. Both segment translation (see “Segmentation” on page 5) and page translation (see
“Paging” on page 7) can be used to access the physical address space, when the processor is
running in legacy protected mode.
When the physical-address size extensions are enabled (see “Physical-Address Extensions (PAE)
Bit” on page 129), the page-translation mechanism can be extended to support 52-bit physicaladdresses. 52-bit physical addresses allow up to 4 petabytes of physical-address space to besupported. (Currently, the AMD64 architecture supports 40-bit addresses in this mode, allowing
up to 1 terabyte of physical-address space to be supported.
•Long Mode —This mode is unique to the AMD64 architecture. This mode supports up to 4 
petabytes of physical-address space using 52-bit physical addresses. Long mode requires the use of page-translation and the physical-address size extensions (PAE).
1.1.3  Canonical Address Form
Long mode defines 64 bits of virtual-address space, but processor implementations can support less.

Long mode defines 64 bits of virtual-address space, but processor implementations can support less. 
Although some processor implementations do not use all 64 bits of the virtual address, they all check bits 63 through the most-significant implemented bit to see if those bits are all zeros or all ones. An address that complies with this property is in canonical address form . In most cases, a virtual-memory 
reference that is not in canonical form (in either the linear or effective form of the address) causes a 
general-protection exception (#GP) to occur. However, implied stack references where the stack address is not in canonical form causes a stack exception (#SS) to occur. Implied stack references include all push and pop instructions, and any instruction using RSP or RBP as a base register.
By checking canonical-address form, the AMD64 architecture prevents software from exploiting 
unused high bits of pointers for other purposes. Software complying with canonical-address form on a specific processor implementation can run unchanged on long-mode implementations supporting larger virtual-address spaces.
[AMD Public Use]5 System-Programming OverviewAMD64 Technology 24593—Rev. 3.41—June 2023
1.2 Memory Management
Memory management consists of the methods by which addresses generated by software are translated 
by segmentation and/or paging into addresses in physical memory. Memory management is not visible to application software. It is handled by the system software and processor hardware.
1.2.1  Segmentation
Segmentation was originally created as a method by which system software could isolate software 
processes (tasks), and the data used by those processes, from one another in an effort to increase the reliability of systems running multiple processes simultaneously. 
The AMD64 architecture is designed to support all forms of legacy segmentation. However, most 
modern system software does not use the segmentation features available in the legacy x86 architecture. Instead, system software typically handles program and data isolation using page-level protection. For this reason, the AMD64 architecture dispenses with multiple segments in 64-bit mode and, instead, uses a flat-memory model. The elimination of segmentation allows new 64-bit system software to be coded more simply, and it supports more efficient management of multi-processing than is possible in the legacy x86 architecture.
Segmentation is, however, used in compatibility mode and legacy mode. Here, segmentation is a form 
of base memory-addressing that allows software and data to be relocated in virtual-address space off of an arbitrary base address. Software and data can be relocated in virtual-address space using one or more variable-sized memory segments.  The legacy x86 architecture provides several methods of 
restricting access to segments from other segments so that software and data can be protected from interfering with each other.
In compatibility and legacy modes, up to 16,383 unique segments can be defined. The base-address 
value, segment size (called a limit), protection, and other attributes for each segment are contained in a 
data structure called a segment descriptor. Collections of segment descriptors are held in descriptor 
tables . Specific segment descriptors are referenced or selected from the descriptor table using a 
segment selector register . Six segment-selector registers are available, providing access to as many as 
six segments at a time.
Figure 1-1 on page 6 shows an example of segmented memory. Segmentation is described in 
Chapter 4, “Segmented Virtual Memory.”
[AMD Public Use]System-Programming Overview 624593—Rev. 3.41—June 2023 AMD64 Technology
 
Figure 1-1. Segmented-Memory Model
Flat Segmentation.  One special case of segmented memory is the flat-memory model. In the legacy 
flat-memory model, all segment-base addresses have a value of 0, and the segment limits are fixed at 
4 Gbytes. Segmentation cannot be disabled but use of the flat-memory model effectively disables segment translation. The result is a virtual address that equals the effective address. Figure 1-2 on page 7 shows an example of the flat-memory model.
Software running in 64-bit mode automatically uses the flat-memory model. In 64-bit mode, the 
segment base is treated as if it were 0, and the segment limit is ignored. This allows an effective addresses to access the full virtual-address space supported by the processor.513-201.epsEffective Address
Selectors
BaseLimit
BaseLimitDescriptor TableVirtual Address
Space
Virtual Address
Segment
SegmentDS
ES
FS
GSCS
SS
[AMD Public Use]7 System-Programming OverviewAMD64 Technology 24593—Rev. 3.41—June 2023
 
Figure 1-2. Flat Memory Model
1.2.2  Paging
Paging allows software and data to be relocated in physical-address space using fixed-size blocks 
called physical pages . The legacy x86 architecture supports three different physical-page sizes of 
4 Kbytes, 2 Mbytes, and 4 Mbytes. As with segment translation, access to physical pages by lesser-
privileged software can be restricted.
Page translation uses a hierarchical data structure called a page-translation table to translate virtual 
pages into physical-pages. The number of levels in the translation-table hierarchy can be as few as one or as many as four, depending on the physical-page size and processor operating mode. Translation tables are aligned on 4-Kbyte boundaries. Physical pages must be aligned on 4-Kbyte, 2-Mbyte, or 4-Mbyte boundaries, depending on the physical-page size.
Each table in the translation hierarchy is indexed by a portion of the virtual-address bits. The entry 
referenced by the table index contains a pointer to the base address of the next-lower-level table in the translation hierarchy. In the case of the lowest-level table, its entry points to the physical-page base address. The physical page is then indexed by the least-significant bits of the virtual address to yield the physical address.
Figure 1-3 on page 8 shows an example of paged memory with three levels in the translation-table 
hierarchy. Paging is described in Chapter 5, “Page Translation and Protection.”513-202.epsEffective AddressVirtual Address
Space
Flat Segment
[AMD Public Use]System-Programming Overview 824593—Rev. 3.41—June 2023 AMD64 Technology
 
Figure 1-3. Paged Memory Model
Software running in long mode is required to have page translation enabled.
1.2.3  Mixing Segmentation and Paging
Memory-management software can combine the use of segmented memory and paged memory. 
Because segmentation cannot be disabled, paged-memory management requires some minimum initialization of the segmentation resources. Paging can be completely disabled, so segmented-memory management does not require initialization of the paging resources.
Segments can range in size from a single byte to 4 Gbytes in length. It is therefore possible to map 
multiple segments to a single physical page and to map multiple physical pages to a single segment. Alignment between segment and physical-page boundaries is not required, but memory-management software is simplified when segment and physical-page boundaries are aligned.513-203.epsPage Translation TablesPhysical Address
Space
Page Table Base AddressVirtual Address
Physical PageTable 3 Table 2 Table 1
[AMD Public Use]9 System-Programming OverviewAMD64 Technology 24593—Rev. 3.41—June 2023
The simplest, most efficient method of memory management is the flat-memory model. In the flat-
memory model, all segment base addresses have a value of 0 and the segment limits are fixed at 4 Gbytes. The segmentation mechanism is still used each time a memory reference is made, but because virtual addresses are identical to effective addresses in this model, the segmentation mechanism is effectively ignored. Translation of virtual (or effective) addresses to physical addresses takes place using the paging mechanism only.
Because 64-bit mode disables segmentation, it uses a flat, paged-memory model for memory 
management. The 4 Gbyte segment limit is ignored in 64-bit mode. Figure 1-4 shows an example of this model.
 
Figure 1-4. 64-Bit Flat, Paged-Memory Model513-204.epsPhysical Address
Space
Page FramePhysical Address
Page Translation Tables
Page Table Base AddressEffective AddressVirtual Address
Space
[AMD Public Use]System-Programming Overview 1024593—Rev. 3.41—June 2023 AMD64 Technology
1.2.4  Real Addressing
Real addressing is a legacy-mode form of address translation used in real mode. This simplified form 
of address translation is backward compatible with 8086-processor effective-to-physical address translation. In this mode, 16-bit effective addresses are mapped to 20-bit physical addresses, providing a 1-Mbyte physical-address space.
Segment selectors are used in real-address translation, but not as an index into a descriptor table.

Space
Space
Segment selectors are used in real-address translation, but not as an index into a descriptor table. 
Instead, the 16-bit segment-selector value is shifted left by 4 bits to form a 20-bit segment-base address. The 16-bit effective address is added to this 20-bit segment base address to yield a 20-bit physical address. If the sum of the segment base and effective address carries over into bit 20, that bit can be optionally truncated to mimic the 20-bit address wrapping of the 8086 processor by using the A20M# input signal to mask the A20 address bit.
A20 address bit masking should only be used in real mode (see next section for information on real 
mode). Use in other modes may result in address translation errors.
Real-address translation supports a 1-Mbyte physical-address space using up to 64K segments aligned 
on 16-byte boundaries. Each segment is exactly 64 Kbytes long. Figure 1-5 shows an example of real-address translation.
 
Figure 1-5. Real-Address Memory Model513-205.epsEffective AddressSelectors
+0000 Effective Address 0000 Selector
Physical Address0 19 0 19
0 190 15DS
ES
FS
GSCS
SS
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1.3 Operating Modes
The legacy x86 architecture provides four operating modes or environments that support varying 
forms of memory management, virtual-memory and physical-memory sizes, and protection:
•Real Mode.
•Protected Mode.
•Virtual-8086 Mode.
•System Management Mode.
The AMD64 architecture supports all these legacy modes, and it adds a new operating mode called 
long mode . Table 1-1 shows the differences between long mode and legacy mode. Software can move 
between all supported operating modes as shown in Figure 1-6 on page 12. Each operating mode is 
Table 1-1. Operating Modes
ModeSystem 
Software 
RequiredApplication 
Recompile 
RequiredDefaults1
Register 
Extensions2Maximum
GPR
Width
(bits) Address
Size 
(bits)Operand 
Size 
(bits)
Long 
Mode364-BitMode New 
64-bit OSyes 6432yes 64
CompatibilityModeno32no 3216 16
Legacy ModeProtected ModeLegacy 
32-bit OSno32 32
no3216 16
Virtual-8086 Mode16 16 32
Real ModeLegacy 
16-bit OS
Note:
1. Defaults can be overridden in most modes using an instruction prefix or system control bit. 
2. Register extensions include access to the upper eight general-purpose and YMM/XMM registers, uniform access to lower 8
bits of all GPRs, and access to the upper 32 bits of the GPRs.
3. Long mode supports only x86 protected mode. It does not support x86 real mode or virtual-8086 mode.
[AMD Public Use]System-Programming Overview 1224593—Rev. 3.41—June 2023 AMD64 Technology
 
Figure 1-6. Operating Modes of the AMD64 Architecture
1.3.1  Long Mode
Long mode consists of two submodes: 64-bit mode  and compatibility mode . 64-bit mode supports 
several new features, including the ability to address 64-bit virtual-address space. Compatibility mode 
provides binary compatibility with existing 16-bit and 32-bit applications when running on 64-bit system software. 
Throughout this document, references to long mode  refer collectively to both 64-bit mode  and 
compatibility mode . If a function is specific to either 64-bit mode or compatibility mode, then those 
specific names are used instead of the name long mode . 
Before enabling and activating long mode, system software must first enable protected mode. The 
process of enabling and activating long mode is described in Chapter 14, “Processor Initialization and 513-206.epsSystem
ModeReal
ModeVirtual
8086
ModeProtected
ModeLong Mode
64-bit
ModeCompatibility
Mode
EFER.LME=1, CR4.PAE=1
then CR0.PG=1
CR0.PE=1CR0.PG=0then EFER.LME=0CS.L=0CS.L=1
CS.L=0
CR0.PE=0EFLAGS.VM=1EFLAGS.VM=0
RSM SMI#
RSMSMI#SMI#SMI#
RSMRSM
SMI# RSM
Reset
Reset
Reset
Reset
[AMD Public Use]13 System-Programming OverviewAMD64 Technology 24593—Rev. 3.41—June 2023
Long Mode Activation.” Long mode features are described throughout this document, where 
1.3.2  64-Bit Mode
64-bit mode, a submode of long mode, provides support for 64-bit system software and applications by 
adding the following features:
•64-bit virtual addresses (processor implementations can have fewer).
•Access to General Purpose Register bits 63:32
•Access to additional registers through the REX, VEX, and XOP instruction prefixes:
- eight additional GPRs (R8–R15)- eight additional Streaming SIMD Extension (SSE) registers (YMM/XMM8–15)
•64-bit instruction pointer (RIP). 
•New RIP-relative data-addressing mode. 
•Flat-segment address space with single code, data, and stack space. 
The mode is enabled by the system software on an individual code-segment basis. Although code 
segments are used to enable and disable 64-bit mode, the legacy segmentation mechanism is largely disabled. Page translation is required for memory management purposes. Because 64-bit mode supports a 64-bit virtual-address space, it requires 64-bit system software and development tools. 
In 64-bit mode, the default address size is 64 bits, and the default operand size is 32 bits. The defaults 
can be overridden on an instruction-by-instruction basis using instruction prefixes. A new REX prefix is introduced for specifying a 64-bit operand size and the new registers. 
1.3.3  Compatibility Mode
Compatibility mode, a submode of long mode, allows system software to implement binary 
compatibility with existing 16-bit and 32-bit x86 applications. It allows these applications to run, without recompilation, under 64-bit system software in long mode, as shown in Table 1-1 on page 11. 
In compatibility mode, applications can only access the first 4 Gbytes of virtual-address space. 
Standard x86 instruction prefixes toggle between 16-bit and 32-bit address and operand sizes.
Compatibility mode, like 64-bit mode, is enabled by system software on an individual code-segment 
basis. Unlike 64-bit mode, however, segmentation functions the same as in the legacy-x86 architecture, using 16-bit or 32-bit protected-mode semantics. From an application viewpoint, compatibility mode looks like a legacy protected-mode environment. From a system-software viewpoint, the long-mode mechanisms are used for address translation, interrupt and exception handling, and system data-structures. 
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1.3.4  Legacy Modes
Legacy mode  consists of three submodes: real mode, protected mode, and virtual-8086 mode. 
Protected mode can be either paged or unpaged. L egacy mode  preserves binary compatibility not only 
with existing x86 16-bit and 32-bit applications but also with existing x86 16-bit and 32-bit system 
software.
Real Mode.  In this mode, also called real-address mode, the processor supports a physical-memory 
space of 1 Mbyte and operand sizes of 16 bits (default) or 32 bits (with instruction prefixes). Interrupt handling and address generation are nearly identical to the 80286 processor's real mode. Paging is not supported. All software runs at privilege level 0. 
Real mode is entered after reset or processor power-up. The mode is not supported when the processor 
is operating in long mode because long mode requires that paged protected mode be enabled. 
Protected Mode.  In this mode, the processor supports virtual-memory and physical-memory spaces 
of 4 Gbytes and operand sizes of 16 or 32 bits. All segment translation, segment protection, and hardware multitasking functions are available. System software can use segmentation to relocate effective addresses in virtual-address space. If paging is not enabled, virtual addresses are equal to physical addresses. Paging can be optionally enabled to allow translation of virtual addresses to physical addresses and to use the page-based memory-protection mechanisms.
In protected mode, software runs at privilege levels 0, 1, 2, or 3. Typically, application software runs at 
privilege level 3, the system software runs at privilege levels 0 and 1, and privilege level 2 is available to system software for other uses. The 16-bit version of this mode was first introduced in the 80286 processor.
Virtual-8086 Mode.  Virtual-8086 mode allows system software to run 16-bit real-mode software on a 
virtualized-8086 processor. In this mode, software written for the 8086, 8088, 80186, or 80188 processor can run as a privilege-level-3 task under protected mode. The processor supports a virtual-memory space of 1 Mbytes and operand sizes of 16 bits (default) or 32 bits (with instruction prefixes), and it uses real-mode address translation. 
Virtual-8086 mode is enabled by setting the virtual-machine bit in the EFLAGS register 
(EFLAGS.VM). EFLAGS.VM can only be set or cleared when the EFLAGS register is loaded from the TSS as a result of a task switch, or by executing an IRET instruction from privileged software. The POPF instruction cannot be used to set or clear the EFLAGS.VM bit.
Virtual-8086 mode is not supported when the processor is operating in long mode. When long mode is 
enabled, any attempt to enable virtual-8086 mode is silently ignored.

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1.3.5  System Management Mode (SMM)
System management mode (SMM) is an operating mode designed for system-control activities that are 
typically transparent to conventional system software. Power management is one popular use for system management mode. SMM is primarily targeted for use by platform firmware and specialized low-level device drivers. The code and data for SMM are stored in the SMM memory area, which is isolated from main memory by the SMM output signal.
SMM is entered by way of a system management interrupt (SMI). Upon recognizing an SMI, the 
processor enters SMM and switches to a separate address space where the SMM handler is located and executes. In SMM, the processor supports real-mode addressing with 4 Gbyte segment limits and default operand, address, and stack sizes of 16 bits (prefixes can be used to override these defaults).
1.4 System Registers
Figure 1-7 on page 16 shows the system registers defined for the AMD64 architecture. System 
software uses these registers to, among other things, manage the processor operating environment, define system resource characteristics, and to monitor software execution. With the exception of the RFLAGS register, system registers can be read and written only from privileged software. 
Except for the descriptor-table registers and task register, the AMD64 architecture defines all system 
registers to be 64 bits wide. The descriptor table and task registers are defined by the AMD64 architecture to include 64-bit base-address fields, in addition to their other fields.
As shown in Figure 1-7 on page 16, the system registers include:
•Control Registers—These registers are used to control system operation and some system features. 
See “System-Control Registers” on page 40 for details.
•System-Flags Register —The RFLAGS register contains system-status flags and masks. It is also 
used to enable virtual-8086 mode and to control application access to I/O devices and interrupts. See “RFLAGS Register” on page 51 for details.
•Descriptor-Table Registers —These registers contain the location and size of descriptor tables 
stored in memory. Descriptor tables hold segmentation data structures used in protected mode. See “Descriptor Tables” on page 82 for details.
•Task Register —The task register contains the location and size in memory of the task-state 
segment. The hardware-multitasking mechanism uses the task-state segment to hold state information for a given task. The TSS also holds other data, such as the inner-level stack pointers used when changing to a higher privilege level. See “Task Register” on page 369 for details.
•Debug Registers—Debug registers are used to control the software-debug mechanism, and to report information back to a debug utility or application. See “Debug Registers” on page 391 for details.
[AMD Public Use]System-Programming Overview 1624593—Rev. 3.41—June 2023 AMD64 Technology
Figure 1-7. System Registers
Also defined as system registers are a number of model-specific registers  included in the AMD64 
architectural definition, and shown in Figure 1-7:
•Extended-Feature-Enable Register—The EFER register is used to enable and report status on 
special features not controlled by the CRn control registers. In particular, EFER is used to control activation of long mode. See “Extended Feature Enable Register (EFER)” on page 55 for more information.Control Registers
CR0
CR2
CR3
CR4
CR8
System-Flags Register
RFLAGS
Debug Registers
DR0
DR1
DR2
DR3
DR6
DR7
System_Registers_Diag.epsMemory-Typing Registers
MTRRcap
MTRRdefType
MTRRphysBasen
MTRRphysMaskn
MTRRfixn
PAT
TOP_MEM
TOP_MEM2
Machine-Check Registers
MCG_CAP
MCG_STAT
MCG_CTL
MCi_CTL
MCi_STATUS
MCi_ADDR
MCi_MISC
Model-Specific RegistersDescriptor-Table Registers
GDTR
IDTR
LDTR
Task Register
TRExtended-Feature-Enable Register
EFER
Debug-Extension Registers
DebugCtl
LastBranchFromIP
LastBranchToIP
LastIntFromIP
LastIntToIPSystem-Configuration Register
SYSCFG
System-Linkage Registers
STAR
LSTAR
CSTAR
FS.base
GS.base
KernelGSbase
SYSENTER_CS
SYSENTER_ESP
SYSENTER_EIPSFMASKPerformance-Monitoring Registers
TSC
PerfEvtSeln
PerfCtrn
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•System-Configuration Register—The SYSCFG register is used to enable and configure system-
bus features. See “System Configuration Register (SYSCFG)” on page 60 for more information.
•System-Linkage Registers—These registers are used by system-linkage instructions to specify operating-system entry points, stack locations, and pointers into system-data structures. See “Fast System Call and Return” on page 173 for details.
•Memory-Typing Registers —Memory-typing registers can be used to characterize (type) system 
memory. Typing memory gives system software control over how instructions and data are cached, and how memory reads and writes are ordered. See “MTRRs” on page 217 for details.
•Debug-Extension Registers —These registers control additional software-debug reporting features. 
See “Debug Registers” on page 391 for details.
•Performance-Monitoring Registers—Performance-monitoring registers are used to count processor and system events, or the duration of events. See “Performance Monitoring Counters” on page 410 for more information.
•Machine-Check Registers —The machine-check registers control the response of the processor to 
non-recoverable failures. They are also used to report information on such failures back to system utilities designed to respond to such failures. See “Machine Check Architecture MSRs” on 
page 300 for more information.
1.5 System-Data Structures
Figure 1-8 on page 18 shows the system-data structures defined for the AMD64 architecture. System-
data structures are created and maintained by system software for use by the processor when running in protected mode. A processor running in protected mode uses these data structures to manage memory and protection, and to store program-state information when an interrupt or task switch occurs.
[AMD Public Use]System-Programming Overview 1824593—Rev. 3.41—June 2023 AMD64 Technology
Figure 1-8. System-Data Structures
As shown in Figure 1-8, the system-data structures include:
•Descriptors—A descriptor provides information about a segment to the processor, such as its 
location, size and privilege level. A special type of descriptor, called a gate, is used to provide a 
code selector and entry point for a software routine. Any number of descriptors can be defined, but system software must at a minimum create a descriptor for the currently executing code segment and stack segment. See “Legacy Segment Descriptors” on page 88, and “Long-Mode Segment Descriptors” on page 97 for complete information on descriptors.
•Descriptor Tables —As the name implies, descriptor tables hold descriptors. The global-descriptor 
table holds descriptors available to all programs, while a local-descriptor table holds descriptors used by a single program. The interrupt-descriptor table holds only gate descriptors used by 513-261.epsSegment Descriptors (Contained in Descriptor Tables)
Code
Stack
DataGate
Task-State Segment
Local-Descriptor TableTask-State Segment
Page-Translation Tables
Page-Map Level-4 Page Table Page Directory Page-Directory PointerGlobal-Descriptor Table
. . .
DescriptorInterrupt-Descriptor Table
Gate Descriptor
. . .
Gate DescriptorLocal-Descriptor Table
. . .
DescriptorDescriptor Tables
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interrupt handlers. System software must initialize the global-descriptor and interrupt-descriptor 
tables, while use of the local-descriptor table is optional. See “Descriptor Tables” on page 82 for more information.
•Task-State Segment —The task-state segment is a special segment for holding processor-state 
information for a specific program, or task. It also contains the stack pointers used when switching to more-privileged programs. The hardware multitasking mechanism uses the state information in the segment when suspending and resuming a task. Calls and interrupts that switch stacks cause the stack pointers to be read from the task-state segment. System software must create at least one task-state segment, even if hardware multitasking is not used. See “Legacy Task-State Segment” on page 371, and “64-Bit Task State Segment” on page 375 for details.
•Page-Translation Tables —Use of page translation is optional in protected mode, but it is required 
in long mode. A four-level page-translation data structure is provided to allow long-mode operating systems to translate a 64-bit virtual-address space into a 52-bit physical-address space. Legacy protected mode can use two- or three-level page-translation data structures. See “Page Translation Overview” on page 127 for more information on page translation.
1.6 Interrupts

The AMD64 architecture provides a mechanism for the processor to automatically suspend (interrupt) software execution and transfer control to an interrupt handler when an interrupt or exception occurs. An interrupt handler is privileged software designed to identify and respond to the cause of an interrupt or exception, and return control back to the interrupted software. Interrupts  can be caused 
when system hardware signals an interrupt condition using one of the external-interrupt signals on the processor. Interrupts can also be caused by software that executes an interrupt instruction. Exceptions  
occur when the processor detects an abnormal condition as a result of executing an instruction. The term “interrupts” as used throughout this volume includes both interrupts and exceptions when the distinction is unnecessary.
System software not only sets up the interrupt handlers, but it must also create and initialize the data 
structures the processor uses to execute an interrupt handler when an interrupt occurs. The data structures include the code-segment descriptors for the interrupt-handler software and any data-segment descriptors for data and stack accesses. Interrupt-gate descriptors must also be supplied. Interrupt gates point to interrupt-handler code-segment descriptors, and the entry point in an interrupt handler. Interrupt gates are stored in the interrupt-descriptor table. The code-segment and data-segment descriptors are stored in the global-descriptor table and, optionally, the local-descriptor table. 
When an interrupt occurs, the processor uses the interrupt vector to find the appropriate interrupt gate 
in the interrupt-descriptor table. The gate points to the interrupt-handler code segment and entry point, and the processor transfers control to that location. Before invoking the interrupt handler, the processor saves information required to return to the interrupted program. For details on how the processor transfers control to interrupt handlers, see “Legacy Protected-Mode Interrupt Control Transfers” on page 269, and “Long-Mode Interrupt Control Transfers” on page 280. 
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Table 1-2 shows the supported interrupts and exceptions, ordered by their vector number. Refer to 
“Vectors” on page 244 for a complete description of each interrupt, and a description of the interrupt mechanism.
1.7 Additional System-Programming Facilities
1.7.1  Hardware Multitasking
A task is any program that the processor can execute, suspend, and later resume executing at the point 
of suspension. During the time a task is suspended, other tasks are allowed to execute. Each task has its own execution space, consisting of a code segment, data segments, and a stack segment for each privilege level. Tasks can also have their own virtual-memory environment managed by the page-translation mechanism. The state information defining this execution space is stored in the task-state segment (TSS) maintained for each task.Table 1-2. Interrupts and Exceptions
Vector Description
0 Integer Divide-by-Zero Exception
1 Debug Exception2 Non-Maskable-Interrupt3 Breakpoint Exception (INT 3)4 Overflow Exception (INTO instruction)5 Bound-Range Exception (BOUND instruction)6 Invalid-Opcode Exception7 Device-Not-Available Exception8 Double-Fault Exception9 Coprocessor-Segment-Overrun Exception (reserved in AMD64)
10 Invalid-TSS Exception
11 Segment-Not-Present Exception
12 Stack Exception13 General-Protection Exception14 Page-Fault Exception15 (Reserved)16 x87 Floating-Point Exception17 Alignment-Check Exception18 Machine-Check Exception19 SIMD Floating-Point Exception21 Control-Protection Exception 
0–255 Interrupt Instructions0–255 Hardware Maskable Interrupts
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Support for hardware multitasking is provided by implementations of the AMD64 architecture when 
software is running in legacy mode. Hardware multitasking provides automated mechanisms for switching tasks, saving the execution state of the suspended task, and restoring the execution state of the resumed task. When hardware multitasking is used to switch tasks, the processor takes the following actions:
•The processor automatically suspends execution of the task, allowing any executing instructions to 
complete and save their results.
•The execution state of a task is saved in the task TSS.
•The execution state of a new task is loaded into the processor from its TSS.
•The processor begins executing the new task at the location specified in the new task TSS.
Use of hardware-multitasking features is optional in legacy mode. Generally, modern operating systems do not use the hardware-multitasking features, and instead perform task management entirely in software. Long mode does not support hardware multitasking at all. 
Whether hardware multitasking is used or not, system software must create and initialize at least one 
task-state segment data-structure. This requirement holds for both long-mode and legacy-mode software. The single task-state segment holds critical pieces of the task execution environment and is referenced during certain control transfers.
Detailed information on hardware multitasking is available in Chapter 12, “Task Management,” along 
with a full description of the requirements that must be met in initializing a task-state segment when hardware multitasking is not used.
1.7.2  Machine Check
Implementations of the AMD64 architecture support the machine-check exception. This exception is 
useful in system applications with stringent requirements for reliability, availability, and serviceability. The exception allows specialized system-software utilities to report hardware errors that are generally severe and non-recoverable. Providing the capability to report such errors can allow complex system problems to be pinpointed rapidly.
The machine-check exception is described in Chapter 9, “Machine Check Architecture.” Much of the 
error-reporting capabilities is implementation dependent. For more information, developers of 
machine-check error-reporting software should refer to the BIOS and Kernel Developer’s Guide 
(BKDG) or Processor Programming Reference Manual (PPR)   or applicable to your product.
1.7.3  Software Debugging
A software-debugging mechanism is provided in hardware to help software developers quickly isolate 
programming errors. This capability can be used to debug system software and application software alike. Only privileged software can access the debugging facilities. Generally, software-debug support is provided by a privileged application program rather than by the operating system itself.
The facilities supported by the AMD64 architecture allow debugging software to perform the 
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•Set breakpoints on specific instructions within a program.
•Set breakpoints on an instruction-address match.
•Set breakpoints on a data-address match.
•Set breakpoints on specific I/O-port addresses.
•Set breakpoints to occur on task switches when hardware multitasking is used.
•Single step an application instruction-by-instruction.
•Single step only branches and interrupts.
•Record a history of branches and interrupts taken by a program.
The debugging facilities are fully described in “Software-Debug Resources” on page 390. Some 
processors provide additional, implementation-specific debug support. For more information, refer to the BIOS and Kernel Developer’s Guide (BKDG) or Processor Programming Reference Manual 
(PPR)  applicable to your product.
1.7.4  Performance Monitoring
For many software developers, the ability to identify and eliminate performance bottlenecks from a 
program is nearly as important as quickly isolating programming errors. Implementations of the AMD64 architecture provide hardware performance-monitoring resources that can be used by special software applications to identify such bottlenecks. Non-privileged software can access the performance monitoring facilities, but only if privileged software grants that access. 
The performance-monitoring facilities allow the counting of events, or the duration of events. 
Performance-analysis software can use the data to calculate the frequency of certain events, or the time spent performing specific activities. That information can be used to suggest areas for improvement and the types of optimizations that are helpful.
The performance-monitoring facilities are fully described in “Performance Monitoring Counters” on 
page 410. The specific events that can be monitored are generally implementation specific. For more information, refer to the BIOS and Kernel Developer’s Guide (BKDG) or Processor Programming 
Reference Manual (PPR)  applicable to your product.
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2 x86 and AMD64 Architecture Differences
The AMD64 architecture is designed to provide full binary compatibility with all previous AMD

The AMD64 architecture is designed to provide full binary compatibility with all previous AMD 
implementations of the x86 architecture. This chapter summarizes the new features and architectural enhancements introduced by the AMD64 architecture, and compares those features and enhancements with previous AMD x86 processors. Most of the new capabilities introduced by the AMD64 architecture are available only in long mode (64-bit mode, compatibility mode, or both). However, some of the new capabilities are also available in legacy mode, and are mentioned where appropriate.
The material throughout this chapter assumes the reader has a solid understanding of the x86 
architecture. For those who are unfamiliar with the x86 architecture, please read the remainder of this volume before reading this chapter.
2.1 Operating Modes
See “Operating Modes” on page 11 for a complete description of the operating modes supported by the AMD64 architecture.
2.1.1  Long Mode
The AMD64 architecture introduces long mode and its two sub-modes: 64-bit mode and compatibility 
mode. 
64-Bit Mode.  64-bit mode provides full support for 64-bit system software and applications. The new 
features introduced in support of 64-bit mode are summarized throughout this chapter. To use 64-bit mode, a 64-bit operating system and tool chain are required.
Compatibility Mode.  Compatibility mode allows 64-bit operating systems to implement binary 
compatibility with existing 16-bit and 32-bit x86 applications. It allows these applications to run, without recompilation, under control of a 64-bit operating system in long mode. The architectural enhancements introduced by the AMD64 architecture that support compatibility mode are summarized throughout this chapter.
Unsupported Modes.  Long mode does not support the following two operating modes:
•Virtual-8086 Mode —The virtual-8086 mode bit (EFLAGS.VM) is ignored when the processor is
running in long mode. When long mode is enabled, any attempt to enable virtual-8086 mode issilently ignored. System software must leave long mode in order to use virtual-8086 mode. 
•Real Mode—Real mode is not supported when the processor is operating in long mode becauselong mode requires that protected mode be enabled.
2.1.2  Legacy Mode
The AMD64 architecture supports a pure x86 legacy mode, which preserves binary compatibility not 
only with existing 16-bit and 32-bit applications but also with existing 16-bit and 32-bit operating 
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systems. Legacy mode  supports real mode, protected mode, and virtual-8086 mode. A reset always 
places the processor in legacy mode (real mode), and the processor continues to run in legacy mode 
until system software activates long mode. New features added by the AMD64 architecture that are supported in legacy mode are summarized in this chapter.
2.1.3  System-Management Mode
The AMD64 architecture supports system-management mode (SMM). SMM can be entered from both 
long mode and legacy mode, and SMM can return directly to either mode. The following differences 
exist between the support of SMM in the AMD64 architecture and the SMM support found in previous processor generations:
•The SMRAM state-save area format is changed to hold the 64-bit processor state. This state-save
area format is used regardless of whether SMM is entered from long mode or legacy mode.
•The auto-halt restart and I/O-instruction restart entries in the SMRAM state-save area are one byteinstead of two bytes.
•The initial processor state upon entering SMM is expanded to reflect the 64-bit nature of theprocessor.
•New conditions exist that can cause a processor shutdown while exiting SMM.
•SMRAM caching considerations are modified because the legacy FLUSH# external signal(writeback, if modified, and invalidate) is not supported on implementations of the AMD64architecture.
See Chapter 10, “System-Management Mode,” for more information on the SMM differences.
2.2 Memory Model
The AMD64 architecture provides enhancements to the legacy memory model to support very large physical-memory and virtual-memory spaces while in long mode. Some of this expanded support for physical memory is available in legacy mode.
2.2.1  Memory Addressing
Virtual-Memory Addressing.  Virtual-memory support is expanded to 64 address bits in long mode. 
This allows up to 16 exabytes of virtual-address space to be accessed. The virtual-address space 
supported in legacy mode is unchanged.
Physical-Memory Addressing.  Physical-memory support is expanded to 52 address bits in long 
mode and legacy mode. This allows up to 4 petabytes of physical memory to be accessed. The expanded physical-memory support is achieved by using paging and the page-size extensions.
Note that given processor may implement less than the architecturally-defined physical address size of 
52 bits.
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Effective Addressing.  The effective-address length is expanded to 64 bits in long mode. An 
effective-address calculation uses 64-bit base and index registers, and sign-extends 8-bit and 32-bit 
displacements to 64 bits. In legacy mode, effective addresses remain 32 bits long.
2.2.2  Page Translation
The AMD64 architecture defines an expanded page-translation mechanism supporting translation of a 
64-bit virtual address to a 52-bit physical address. See “Long-Mode Page Translation” on page 139 for detailed information on the enhancements to page translation in the AMD64 architecture. The enhancements are summarized below.
Physical-Address Extensions (PAE).  The AMD64 architecture requires physical-address 
extensions to be enabled (CR4.PAE=1) before long mode is entered. When PAE is enabled, all paging data-structures are 64 bits, allowing references into the full 52-bit physical-address space supported by the architecture.
Page-Size Extensions (PSE).  Page-size extensions (CR4.PSE) are ignored in long mode. Long 
mode does not support the 4-Mbyte page size enabled by page-size extensions. Long mode does, however, support 4-Kbyte and 2-Mbyte page sizes.
Paging Data Structures.  The AMD64 architecture extends the page-translation data structures in 
support of long mode. The extensions are:
•Page-map level-5 (PML5)—Long mode with 5-Level paging support defines a new page
translation data structure, the PML5 table. The PML5 table is at the top of the page translation
hierarchy and references PML4 tables.
•Page-map level-4 (PML4) —Long mode defines a new page-translation data structure, the PML4
table. Without 5-Level paging, the PML4 table is at the top of the page-translation hierarchy andreferences PDP tables.
•Page-directory pointer (PDP) —The PDP tables in long mode are expanded from 4 entries to 512
entries each.
•Page-directory pointer entry (PDPE) —Previously undefined fields within the legacy-mode PDPE
are defined by the AMD64 architecture. 
CR3 Register.  The CR3 register is expanded to 64 bits for use in long-mode page translation. When 
long mode is active, the CR3 register references the base address of either the PML5 or PML4 table. The PML5 table is referenced when 5-Level paging is active (CR4.LA57=1). Otherwise, the PML4 table is referenced. In legacy mode, the upper 32 bits of CR3 are masked by the processor to support legacy page translation. CR3 references the PDP base-address when physical-address extensions are enabled, or the page-directory table base-address when physical-address extensions are disabled. 
Legacy-Mode Enhancements.  Legacy-mode software can take advantage of the enhancements 
made to the physical-address extension (PAE) support and page-size extension (PSE) support. The four-level page translation mechanism introduced by long mode is not available to legacy-mode software.
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•P AE—When physical-address extensions are enabled (CR4.PAE=1), the AMD64 architecture
allows legacy-mode software to load up to 52-bit (maximum size) physical addresses into the PDE
and PTE. Note that addresses are expanded to the maximum physical address size supported by theimplementation.
•PSE—The use of page-size extensions allows legacy mode software to define 4-Mbyte pagesusing the 32-bit page-translation tables. When page-size extensions are enabled (CR4.PSE=1), theAMD64 architecture enhances the 4-Mbyte PDE to support 40 physical-address bits.
See “Legacy-Mode Page Translation” on page 131 for more information on these enhancements.
2.2.3  Segmentation
In long mode, the effects of segmentation depend on whether the processor is running in compatibility 
mode or 64-bit mode:
•In compatibility mode, segmentation functions just as it does in legacy mode, using legacy 16-bit
or 32-bit protected mode semantics. 
•64-bit mode requires a flat-memory model for creating a flat 64-bit virtual-address space. Much ofthe segmentation capability present in legacy mode and compatibility mode is disabled when theprocessor is running in 64-bit mode.

The differences in the segmentation model as defined by the AMD64 architecture are summarized in the following sections. See Chapter 4, “Segmented Virtual Memory,” for a thorough description of these differences.
Descriptor-Table Registers.  In long mode, the base-address portion of the descriptor-table registers 
(GDTR, IDTR, LDTR, and TR) are expanded to 64 bits. The full 64-bit base address can only be loaded by software when the processor is running in 64-bit mode (using the LGDT, LIDT, LLDT, and LTR instructions, respectively). However, the full 64-bit base address is used by a processor running in 
compatibility mode (in addition to 64-bit mode) when making a reference into a descriptor table. 
A processor running in legacy mode can only load the low 32 bits of the base address, and the high 32 
bits are ignored when references are made to the descriptor tables.
Code-Segment Descriptors.  The AMD64 architecture defines a new code-segment descriptor 
attribute, L (long). In compatibility mode, the processor treats code-segment descriptors as it does in legacy mode, with the exception that the processor recognizes the L attribute. If a code descriptor with L=1 is loaded in compatibility mode, the processor leaves compatibility mode and enters 64-bit mode. In legacy mode, the L attribute is reserved.
The following differences exist for code-segment descriptors in 64-bit mode only:
•The CS base-address field is ignored by the processor.
•The CS limit field is ignored by the processor.
•Only the L (long), D (default size), and DPL (descriptor-privilege level) fields are used by the
processor in 64-bit mode. All remaining attributes are ignored.
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Data-Segment Descriptors.  The following differences exist for data-segment descriptors in 64-bit 
mode only:
•The DS, ES, and SS descriptor base-address fields are ignored by the processor.
•The FS and GS descriptor base-address fields are expanded to 64 bits and used in effective-address
calculations. The 64 bits of base address are mapped to model-specific registers (MSRs), and canonly be loaded using the WRMSR instruction.
•The limit fields and attribute fields of all data-segment descriptors (DS, ES, FS, GS, and SS) areignored by the processor.
In compatibility mode, the processor treats data-segment descriptors as it does in legacy mode. Compatibility mode ignores the high 32 bits of base address in the FS and GS segment descriptors when calculating an effective address.
System-Segment Descriptors.  In 64-bit mode only, The LDT and TSS system-segment descriptor 
formats are expanded by 64 bits, allowing them to hold 64-bit base addresses. LLDT and LTR instructions can be used to load these descriptors into the LDTR and TR registers, respectively, from 64-bit mode. 
In compatibility mode and legacy mode, the formats  of the LDT and TSS system-segment descriptors 
are unchanged. Also, unlike code-segment and data-segment descriptors, system-segment descriptor 
limits are checked  by the processor in long mode.
Some legacy mode LDT and TSS type-field encodings are illegal in long mode (both compatibility mode and 64-bit mode), and others are redefined to new types. See “System Descriptors” on page 99 
for additional information.
Gate Descriptors.  The following differences exist between gate descriptors in long mode (both 
compatibility mode and 64-bit mode) and in legacy mode:
•In long mode, all 32-bit gate descriptors are redefined as 64-bit gate descriptors, and are expanded
to hold 64-bit offsets. The length of a gate descriptor in long mode is therefore 128 bits (16 bytes),versus the 64 bits (8 bytes) in legacy mode.
•Some type-field encodings are illegal in long mode, and others are redefined to new types. See“Gate Descriptors” on page 101 for additional information.
•The interrupt-gate and trap-gate descriptors define a new field, called the interrupt-stack table(IST) field.
2.3 Protection Checks
The AMD64 architecture makes the following changes to the protection mechanism in long mode:
•The page-protection-check mechanism is expanded in long mode to include the U/S and R/W
protection bits stored in the PML5, PML4 and PDP entries.
•Several system-segment types and gate-descriptor types that are legal in legacy mode are illegal inlong mode (compatibility mode and 64-bit mode) and fail type checks when used in long mode.
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•Segment-limit checks are disabled in 64-bit mode for the CS, DS, ES, FS, GS, and SS segments.
Segment-limit checks remain enabled for the LDT, GDT, IDT and TSS system segments.
All segment-limit checks are performed in compatibility mode.
•Code and data segments used in 64-bit mode are treated as both readable and writable.
See “Page-Protection Checks” on page 161 and “Segment-Protection Overview” on page 104 for 
detailed information on the protection-check changes.
2.4 Registers
The AMD64 architecture adds additional registers to the architecture, and in many cases expands the size of existing registers to 64 bits. The 80-bit floating-point stack registers and their overlaid 64-bit MMX™ registers are not modified by the AMD64 architecture.
2.4.1  General-Purpose Registers
In 64-bit mode, the general-purpose registers (GPRs) are 64 bits wide, and eight additional GPRs are 
available. The GPRs are: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, and the new R8–R15 registers. To access the full 64-bit operand size, or the new R8–R15 registers, an instruction must include a new REX instruction-prefix byte (see “REX Prefixes” on page 30 for a summary of this prefix).
In compatibility and legacy modes, the GPRs consist only of the eight legacy 32-bit registers. All 
legacy rules apply for determining operand size.
2.4.2  YMM/XMM Registers 
In 64-bit mode, eight additional YMM/XMM registers are available, YMM/XMM8–15. A REX 
instruction prefix is used to access these registers. In compatibility and legacy modes, only registers YMM/XMM0–7 are accessible.
2.4.3  Flags Register
The flags register is expanded to 64 bits, and is called RFLAGS. All 64 bits can be accessed in 64-bit 
mode, but the upper 32 bits are reserved and always read back as zeros. Compatibility mode and legacy mode can read and write only the lower-32 bits of RFLAGS (the legacy EFLAGS). 
2.4.4  Instruction Pointer
In long mode, the instruction pointer is extended to 64 bits, to support 64-bit code offsets. This 64-bit 
instruction pointer is called RIP.
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2.4.5  Stack Pointer
In 64-bit mode, the size of the stack pointer, RSP, is always 64 bits. The stack size is not controlled by 
a bit in the SS descriptor, as it is in compatibility or legacy mode, nor can it be overridden by an instruction prefix. Address-size overrides are ignored for implicit stack references. 
2.4.6  Control Registers
The AMD64 architecture defines several enhancements to the control registers (CR n). In long mode, 
all control registers are expanded to 64 bits, although the entire 64 bits can be read and written only 
from 64-bit mode. A new control register, the task-priority register (CR8 or TPR) is added, and can be read and written from 64-bit mode. Last, the function of the page-enable bit (CR0.PG) is expanded. When long mode is enabled, the PG bit is used to activate and deactivate long mode.
2.4.7  Debug Registers
In long mode, all debug registers are expanded to 64 bits, although the entire 64 bits can be read and 
written only from 64-bit mode. Expanded register encodings for the decode registers allow up to eight new registers to be defined (DR8–DR15), although presently those registers are not supported by the AMD64 architecture.
2.4.8  Extended Feature Register (EFER)
The EFER is expanded by the AMD64 architecture to include a long-mode-enable bit (LME), and a 
long-mode-active bit (LMA). These new bits can be accessed from legacy mode and long mode.
2.4.9  Memory Type Range Registers (MTRRs)
The legacy MTRRs are architecturally defined as 64 bits, and can accommodate the maximum 52-bit 
physical address allowed by the AMD64 architecture. From both long mode and legacy mode, implementations of the AMD64 architecture reference the entire 52-bit physical-address value stored in the MTRRs. Long mode and legacy mode system software can update all 64 bits of the MTRRs to manage the expanded physical-address space.
2.4.10  Other Model-Specific Registers (MSRs)
Several other MSRs have fields holding physical addresses. Examples include the APIC-base register

Several other MSRs have fields holding physical addresses. Examples include the APIC-base register 
and top-of-memory register. Generally, any model-specific register that contains a physical address is defined architecturally to be 64 bits wide, and can accommodate the maximum physical-address size defined by the AMD64 architecture. When physical addresses are read from MSRs by the processor, the entire value is read regardless of the operating mode. In legacy implementations, the high-order MSR bits are reserved, and software must write those values with zeros. In legacy mode on AMD64 architecture implementations, software can read and write all supported high-order MSR bits.
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2.5 Instruction Set
2.5.1  REX Prefixes
REX prefixes are used in 64-bit mode to:
•Specify the new GPRs and YMM/XMM registers. 
•Specify a 64-bit operand size. 
•Specify additional control registers. One additional control register, CR8, is defined in 64-bit
mode. 
•Specify additional debug registers (although none are currently defined).
Not all instructions require a REX prefix. The prefix is necessary only if an instruction references one of the extended registers or uses a 64-bit operand. If a REX prefix is used when it has no meaning, it is ignored.
Default 64-Bit Operand Size.  In 64-bit mode, two groups of instructions have a default operand size 
of 64 bits and thus do not need a REX prefix for this operand size:
•Near branches.
•All instructions, except far branches, that implicitly reference the RSP. See “Instructions that
Reference RSP” on page 31 for additional information.
2.5.2  Segment-Override Prefixes in 64-Bit Mode
In 64-bit mode, the DS, ES, SS, and CS segment-override prefixes have no effect. These four prefixes 
are no longer treated as segment-override prefixes in the context of multiple-prefix rules. Instead, they are treated as null prefixes. An exception exists when Upper Address Ignore (UAI) is enabled. When UAI is enabled, these prefixes may control if the canonical check for a memory pointer is modified by UAI.
The FS and GS segment-override prefixes are treated as segment-override prefixes in 64-bit mode. 
Use of the FS and GS prefixes cause their respective segment bases to be added to the effective address calculation. See “FS and GS Registers in 64-Bit Mode” on page 80 for additional information on using 
these segment registers.
2.5.3  Operands and Results
The AMD64 architecture provides support for using 64-bit operands and generating 64-bit results 
when operating in 64-bit mode.
Operand-Size Overrides.  In 64-bit mode, the default operand size is 32 bits. A REX prefix can be 
used to specify a 64-bit operand size. Software uses a legacy operand-size (66h) prefix to toggle to 16-bit operand size. The REX prefix takes precedence over the legacy operand-size prefix. 
Zero Extension of Results.  In 64-bit mode, when performing 32-bit operations with a GPR 
destination, the processor zero-extends the 32-bit result into the full 64-bit destination. Both 8-bit and 
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16-bit operations on GPRs preserve all unwritten upper bits of the destination GPR. This is consistent 
with legacy 16-bit and 32-bit semantics for partial-width results. 
2.5.4  Address Calculations
The AMD64 architecture modifies aspects of effective-address calculation to support 64-bit mode. 
These changes are summarized in the following sections. See “Memory Addressing” in V olume 1 for details.
Address-Size Overrides.  In 64-bit mode, the default-address size is 64 bits. The address size can be 
overridden to 32 bits by using the address-size prefix (67h). 16-bit addresses are not supported in 64-bit mode. In compatibility mode and legacy mode, address-size overrides function the same as in x86 legacy architecture. 
Displacements and Immediates.  Generally, displacement and immediate values in 64-bit mode are 
not extended to 64 bits. They are still limited to 32 bits and are sign extended during effective-address calculations. In 64-bit mode, however, support is provided for some 64-bit displacement and immediate forms of the MOV instruction.
Zero Extending 16-Bit and 32-Bit Addresses.  All 16-bit and 32-bit address calculations are zero-
extended in long mode to form 64-bit addresses. Address calculations are first truncated to the effective-address size of the current mode (64-bit mode or compatibility mode), as overridden by any address-size prefix. The result is then zero-extended to the full 64-bit address width.
RIP-Relative Addressing.  A new addressing form, RIP-relative (instruction-pointer relative) 
addressing, is implemented in 64-bit mode. The effective address is formed by adding the displacement to the 64-bit RIP of the next instruction. 
2.5.5  Instructions that Reference RSP
With the exception of far branches, all instructions that implicitly reference the 64-bit stack pointer, 
RSP, default to a 64-bit operand size in 64-bit mode (see Table 2-1 for a listing). Pushes and pops of 
32-bit stack values are not possible in 64-bit mode with these instructions, but they can be overridden to 16 bits.
Table 2-1. Instructions That Reference RSP
MnemonicOpcode 
(hex)Description
ENTER C8 Create Procedure Stack Frame
LEA VE C9 Delete Procedure Stack Frame
POP reg/mem 8F/0 Pop Stack (register or memory)
POP reg 58-5F Pop Stack (register)
POP FS 0F A1 Pop Stack into FS Segment Register
POP GS 0F A9 Pop Stack into GS Segment Register
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2.5.6  Branches
The AMD64 architecture expands two branching mechanisms to accommodate branches in the full 
64-bit virtual-address space:
•In 64-bit mode, near-branch semantics are redefined.
•In both 64-bit and compatibility modes, a 64-bit call-gate descriptor is defined for far calls. 
In addition, enhancements are made to the legacy SYSCALL and SYSRET instructions.
Near Branches.  In 64-bit mode, the operand size for all near branches defaults to 64 bits (see 
Table 2-2 for a listing). Therefore, these instructions update the full 64-bit RIP without the need for a 
REX operand-size prefix. The following aspects of near branches default to 64 bits:
•Truncation of the instruction pointer.
•Size of a stack pop or stack push, resulting from a CALL or RET.
•Size of a stack-pointer increment or decrement, resulting from a CALL or RET.
•Size of operand fetched by indirect-branch operand size.
The operand size for near branches can be overridden to 16 bits in 64-bit mode. POPF, POPFD, POPFQ 9D Pop to rFLAGS Word, Doubleword, or Quadword
PUSH imm32 68 Push onto Stack (sign-extended doubleword)
PUSH imm8 6A Push onto Stack (sign-extended byte)
PUSH reg/mem FF/6 Push onto Stack (register or memory)
PUSH reg 50-57 Push onto Stack (register)
PUSH FS 0F A0 Push FS Segment Register onto Stack
PUSH GS 0F A8 Push GS Segment Register onto Stack
PUSHF, PUSHFD, PUSHFQ 9C Push rFLAGS Word, Doubleword, or Quadword onto Stack
Table 2-2. 64-Bit Mode Near Branches, Default 64-Bit Operand Size
CALL E8, FF/2 Call Procedure Near
Jcc many Jump Conditional Near
JMP E9, EB, FF/4 Jump Near
LOOP E2 Loop
LOOPcc E0, E1 Loop Conditional
RET C3, C2 Return From Call (near)Table 2-1. Instructions That Reference RSP (continued)
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The address size of near branches is not forced in 64-bit mode. Such addresses are 64 bits by default, 
but they can be overridden to 32 bits by a prefix. 
The size of the displacement field for relative branches is still limited to 32 bits.
Far Branches Through Long-Mode Call Gates.  Long mode redefines the 32-bit call-gate 
descriptor type as a 64-bit call-gate descriptor and expands the call-gate descriptor size to hold a 64-bit 
offset. The long-mode call-gate descriptor allows far branches to reference any location in the supported virtual-address space. In long mode, the call-gate mechanism is changed as follows:
•In long mode, CALL and JMP instructions that reference call-gates must reference 64-bit call
gates.
•A 64-bit call-gate descriptor must reference a 64-bit code-segment.
•When a control transfer is made through a 64-bit call gate, the 64-bit target address is read from the64-bit call-gate descriptor. The base address in the target code-segment descriptor is ignored.
Stack Switching.  Automatic stack switching is also modified when a control transfer occurs through 
a call gate in long mode:
•The target-stack pointer read from the TSS is a 64-bit RSP value.
•The SS register is loaded with a null selector. Setting the new SS selector to null allows nested
control transfers in 64-bit mode to be handled properly. The SS.RPL value is updated to remainconsistent with the newly loaded CPL value.
•The size of pushes onto the new stack is modified to accommodate the 64-bit RIP and RSP values.
•Automatic parameter copying is not supported in long mode.

gates.
Far Returns.  In long mode, far returns can load a null SS selector from the stack under the following 
conditions: 
•The target operating mode is 64-bit mode.
•The target CPL<3.
Allowing RET to load SS with a null selector under these conditions makes it possible for the 
processor to unnest far CALLs (and interrupts) in long mode.
Task Gates.  Control transfers through task gates are not supported in long mode.
Branches to 64-Bit Offsets.  Because immediate values are generally limited to 32 bits, the only way 
a full 64-bit absolute RIP can be specified in 64-bit mode is with an indirect branch. For this reason, direct forms of far branches are eliminated from the instruction set in 64-bit mode. 
SYSCALL and SYSRET Instructions.  The AMD64 architecture expands the function of the legacy 
SYSCALL and SYSRET instructions in long mode. In addition, two new STAR registers, LSTAR and CSTAR, are provided to hold the 64-bit target RIP for the instructions when they are executed in long mode. The legacy STAR register is not expanded in long mode. See “SYSCALL and SYSRET” on page 174 for additional information.
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SWAPGS Instruction.  The AMD64 architecture provides the SWAPGS instruction as a fast method 
for system software to load a pointer to system data-structures. SWAPGS is valid only in 64-bit mode. 
An undefined-opcode exception (#UD) occurs if software attempts to execute SWAPGS in legacy mode or compatibility mode. See “SWAPGS Instruction” on page 176 for additional information.
SYSENTER and SYSEXIT Instructions.  The SYSENTER and SYSEXIT instructions are invalid in 
long mode, and result in an invalid opcode exception (#UD) if software attempts to use them. Software should use the SYSCALL and SYSRET instructions when running in long mode. See “SYSENTER and SYSEXIT (Legacy Mode Only)” on page 176 for additional information.
2.5.7  NOP Instruction
The legacy x86 architecture commonly uses opcode 90h as a one-byte NOP. In 64-bit mode, the 
processor treats opcode 90h specially in order to preserve this NOP definition. This is necessary because opcode 90h is actually the XCHG EAX, EAX instruction in the legacy architecture. Without special handling in 64-bit mode, the instruction would not be a true no-operation. Therefore, in 64-bit mode the processor treats opcode 90h (the legacy XCHG EAX, EAX instruction) as a true NOP, regardless of a REX operand-size prefix. 
This special handling does not apply to the two-byte ModRM form of the XCHG instruction. Unless a 
64-bit operand size is specified using a REX prefix byte, using the two-byte form of XCHG to exchange a register with itself does not result in a no-operation, because the default operation size is 32 bits in 64-bit mode. 
2.5.8  Single-Byte INC and DEC Instructions
In 64-bit mode, the legacy encodings for the 16 single-byte INC and DEC instructions (one for each of 
the eight GPRs) are used to encode the REX prefix values. The functionality of these INC and DEC instructions is still available, however, using the ModRM forms of those instructions (opcodes FF /0 and FF /1). See “Single-Byte INC and DEC Instructions in 64-Bit Mode” in V olume 3 for additional information.
2.5.9  MOVSXD Instruction
MOVSXD is a new instruction in 64-bit mode (the legacy ARPL instruction opcode, 63h, is 
reassigned as the MOVSXD opcode). It reads a fixed-size 32-bit source operand from a register or memory and (if a REX prefix is used with the instruction) sign-extends the value to 64 bits. MOVSXD is analogous to the MOVSX instruction, which sign-extends a byte to a word or a word to a doubleword, depending on the effective operand size. See the instruction reference page for the MOVSXD instruction in V olume 3 for additional information.
2.5.10  Invalid Instructions
Table 2-3 lists instructions that are illegal in 64-bit mode. Table 2-4 on page 35 lists instructions that 
are invalid in long mode (both compatibility mode and 64-bit mode). Attempted use of these instructions causes an invalid-opcode exception (#UD) to occur. 
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Table 2-3. Invalid Instructions in 64-Bit Mode
Mnemonic Opcode (hex) Description
AAA 37 ASCII Adjust After Addition
AAD D5 ASCII Adjust Before Division
AAM D4 ASCII Adjust After Multiply
AAS 3F ASCII Adjust After Subtraction
BOUND 62 Check Array Bounds
CALL (far) 9A Procedure Call Far (absolute)
DAA 27 Decimal Adjust after Addition
DAS 2F Decimal Adjust after Subtraction
INTO CE Interrupt to Overflow Vector
JMP (far) EA Jump Far (absolute)
LDS C5 Load DS Segment Register
LES C4 Load ES Segment Register
POP DS 1F Pop Stack into DS Segment
POP ES 07 Pop Stack into ES Segment 
POP SS 17 Pop Stack into SS Segment 
POPA, POPAD 61 Pop All to GPR Words or Doublewords
PUSH CS 0E Push CS Segment Selector onto Stack
PUSH DS 1E Push DS Segment Selector onto Stack
PUSH ES 06 Push ES Segment Selector onto Stack
PUSH SS 16 Push SS Segment Selector onto Stack
PUSHA, PUSHAD 60 Push All GPR Words or Doublewords onto StackRedundant Grp1
(undocumented)82 Redundant encoding of group1 Eb,Ib opcodes
SALC(undocumented)D6 Set AL According to CF
Table 2-4. Invalid Instructions in Long Mode
SYSENTER 0F 34 System Call
SYSEXIT 0F 35 System Return
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2.5.11  Reassigned Opcodes
Table 2-5 below lists opcodes that are assigned functions in 64-bit mode that differ from their legacy 
2.5.12  FXSAVE and FXRSTOR Instructions
The FXSA VE and FXRSTOR instructions are used to save and restore the entire 128-bit media 
(XMM), 64-bit media, and x87 instruction-set environment during a context switch. The AMD64 
architecture modifies the memory format used by these instructions in order to save and restore the full 64-bit instruction and data pointers, as well as the XMM8–15 registers. Selection of the 32-bit legacy format or the expanded 64-bit format is accomplished by using the corresponding operand size with the FXSA VE and FXRSTOR instructions. When 64-bit software executes an FXSA VE and FXRSTOR with a 32-bit operand size (no operand-size override) the 32-bit legacy format is used. When 64-bit software executes an FXSA VE and FXRSTOR with a 64-bit operand size, the 64-bit format is used. 
For more information on the save area formats, see Section 11.4.4, “Saving Media and x87 Execution 
Unit State,” on page 348
If the fast-FXSA VE/FXRSTOR (FFXSR) feature is enabled in EFER, FXSA VE and FXRSTOR do not save or restore the XMM0–15 registers when executed in 64-bit mode at CPL 0. The x87 environment and MXCSR are saved whether fast-FXSA VE/FXRSTOR is enabled or not. The fast-FXSA VE/FXRSTOR feature has no effect on FXSA VE/FXRSTOR in non 64-bit mode or when CPL > 0. 
Software can use the CPUID instruction to determine whether the fast-FXSA VE/FXRSTOR feature is 
available (CPUID Fn8000_0001h_EDX[FFXSR]). For information on using the CPUID instruction to obtain processor feature information, see Section 3.3, “Processor Feature Identification,” on page 71.
2.6 Interrupts and Exceptions
When a processor is running in long mode, an interrupt or exception causes the processor to enter 64-bit mode. All long-mode interrupt handlers must be implemented as 64-bit code. The AMD64 
architecture expands the legacy interrupt-processing and exception-processing mechanism to support Table 2-5. Opcodes Reassigned in 64-Bit Mode
Opcode (hex)Compatibility and Legacy 
Modes64-Bit Mode
63ARPL—Adjust Requestor 
Privilege LevelMOVSXD—Move Doubleword with Sign Extension
40–4FDEC—Decrement by 1INC—Increment by 1REX Prefix
Note : Two-byte versions of DEC and INC are still available in 64-bit mode.
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handling of interrupts by 64-bit operating systems and applications. The changes are summarized in 
the following sections. See “Long-Mode Interrupt Control Transfers” on page 280 for detailed information on these changes.
2.6.1  Interrupt Descriptor Table
The long-mode interrupt-descriptor table (IDT) must contain 64-bit mode interrupt-gate or trap-gate 
descriptors for all interrupts or exceptions that can occur while the processor is running in long mode. Task gates cannot be used in the long-mode IDT, because control transfers through task gates are not supported in long mode. In long mode, the IDT index is formed by scaling the interrupt vector by 16. In legacy protected mode, the IDT is indexed by scaling the interrupt vector by eight.
2.6.2  Stack Frame Pushes
In legacy mode, the size of an IDT entry (16 bits or 32 bits) determines the size of 
interrupt -stack -frame pushes, and SS:eSP is pushed only on a CPL change. In long mode, the size of

interrupt -stack -frame pushes, and SS:eSP is pushed only on a CPL change. In long mode, the size of 
interrupt stack-frame pushes is fixed at eight bytes, because interrupts are handled in 64-bit mode. Long mode interrupts also cause SS:RSP to be pushed unconditionally, rather than pushing only on a CPL change.
2.6.3  Stack Switching
Legacy mode provides a mechanism to automatically switch stack frames in response to an interrupt. 
In long mode, a slightly modified version of the legacy stack-switching mechanism is implemented, and an alternative stack-switching mechanism—called the interrupt stack table (IST)—is supported.
Long-Mode Stack Switches.  When stacks are switched as part of a long-mode privilege-level 
change resulting from an interrupt, the following occurs:
control transfers in 64-bit mode to be handled properly. The SS.RPL value is cleared to 0.
•The old SS and RSP are saved on the new stack.
Interrupt Stack Table.  In long mode, a new interrupt stack table (IST) mechanism is available as an 
alternative to the modified legacy stack-switching mechanism. The IST mechanism unconditionally switches stacks when it is enabled. It can be enabled for individual interrupt vectors using a field in the IDT entry. This allows mixing interrupt vectors that use the modified legacy mechanism with vectors that use the IST mechanism. The IST pointers are stored in the long-mode TSS. The IST mechanism is only available when long mode is enabled.
2.6.4  IRET Instruction
In compatibility mode, IRET pops SS:eSP off the stack only if there is a CPL change. This allows 
legacy applications to run properly in compatibility mode when using the IRET instruction.
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In 64-bit mode, IRET unconditionally pops SS:eSP off of the interrupt stack frame, even if the CPL 
does not change. This is done because the original interrupt always pushes SS:RSP. Because interrupt stack-frame pushes are always eight bytes in long mode, an IRET from a long-mode interrupt handler (64-bit code) must pop eight-byte items off the stack. This is accomplished by preceding the IRET with a 64-bit REX operand-size prefix. 
In long mode, an IRET can load a null SS selector from the stack under the following conditions: 
•The target CPL< 3.
Allowing IRET to load SS with a null selector under these conditions makes it possible for the 
processor to unnest interrupts (and far CALLs) in long mode.
2.6.5  Task-Priority Register (CR8)
The AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority 
classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. 
A new control register (CR8) is introduced by the AMD64 architecture for managing priority classes. 
This register, also called the task-priority register (TPR), uses the four low-order bits for specifying a 
task priority. How external interrupts are organized into these priority classes is implementation dependent. See “External Interrupt Priorities” on page 266 for information on this feature.
2.6.6  New Exception Conditions
The AMD64 architecture defines a number of new conditions that can cause an exception to occur 
when the processor is running in long mode. Many of the conditions occur when software attempts to use an address that is not in canonical form. See “Vectors” on page 244 for information on the new exception conditions that can occur in long mode.
2.7 Hardware Task Switching
The legacy hardware task-switch mechanism is disabled when the processor is running in long mode. However, long mode requires system software to create data structures for a single task—the long-mode task.
•TSS Descriptors —A new TSS-descriptor type, the 64-bit TSS type, is defined for use in long
mode. It is the only valid TSS type that can be used in long mode, and it must be loaded into the TR
by executing the LTR instruction in 64-bit mode. See “TSS Descriptor” on page 368 for additional
•Task Gates —Because the legacy task-switch mechanism is not supported in long mode, software
cannot use task gates in long mode . Any attempt to transfer control to another task through a task
gate causes a general-protection exception (#GP) to occur.
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•Task-State Segment—A 64-bit task state segment (TSS) is defined for use in long mode. This new
TSS format contains 64-bit stack pointers (RSP) for privilege levels 0–2, interrupt-stack-table(IST) pointers, and the I/O-map base address. See “64-Bit Task State Segment” on page 375 foradditional information.
2.8 Long-Mode vs. Legacy-Mode Differences
Table 2-6 on page 39 summarizes several major system-programming differences between 64-bit 
mode and legacy protected mode. The third column indicates whether the difference also applies to compatibility mode. “Differences Between Long Mode and Legacy Mode” in V olume 3 summarizes the application-programming model differences.
Table 2-6. Differences Between Long Mode and Legacy Mode
Subject 64-Bit Mode DifferenceApplies To 
Compatibility 
Mode?
x86 Modes Real and virtual-8086 modes not supported Yes
Task Switching Task switching not supported Yes
Addressing64-bit virtual addresses No
4-level paging structuresYesPAE must always be enabled
Loaded Segment (Usage 
during memory reference)CS, DS, ES, SS segment bases are ignored
NoCS, DS, ES, FS, GS, SS segment limits are ignored
DS, ES, FS, GS attribute are ignoredCS, DS, ES, SS Segment prefixes are ignored
Exception and Interrupt 
HandlingAll pushes are 8 bytes
YesIDT entries are expanded to 16 bytes
SS is not changed for stack switchSS:RSP is pushed unconditionally
Call GatesAll pushes are 8 bytes
Yes16-bit call gates are illegal32-bit call gate type is redefined as 64-bit call gate and is 
expanded to 16 bytes
SS is not changed for stack switch
System-Descriptor Registers GDT, IDT, LDT, TR base registers expanded to 64 bits
Yes
System-Descriptor Table 
Entries and Pseudo-DescriptorsLGDT and LIDT use expanded 10-byte pseudo-descriptors
NoLLDT and LTR use expanded 16-byte table entries
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3 System Resources
The operating system manages the software-execution environment and general system operation 
through the use of system resources. These resources consist of system registers (control registers and model-specific registers) and system-data structures (memory-management and protection tables). The system-control registers are described in detail in this chapter; many of the features they control are described elsewhere in this volume. The model-specific registers supported by the AMD64 architecture are introduced in this chapter. 
Because of their complexity, system-data structures are described in separate chapters. Refer to the 
following chapters for detailed information on these data structures:
•Descriptors and descriptor tables are described in Section 4.4 “Segmentation Data Structures and
Registers,” on page 75.
•Page-translation tables are described in Section 5.2 “Legacy-Mode Page Translation,” on page 131
and Section 5.3 “Long-Mode Page Translation,” on page 139.
•The task-state segment is described in Section 12.2.4 “Legacy Task-State Segment,” on page 371and Section 12.2.5 “64-Bit Task State Segment,” on page 375.
Not all processor implementations are required to support all possible features. The last section in this chapter addresses processor-feature identification. System software uses the capabilities described in that section to determine which features are supported so that the appropriate service routines are loaded.
3.1 System-Control Registers
The registers that control the AMD64 architecture operating environment include:
•CR0—Provides operating-mode controls and some processor-feature controls.
•CR2—This register is used by the page-translation mechanism. It is loaded by the processor with
the page-fault virtual address when a page-fault exception occurs.
•CR3—This register is also used by the page-translation mechanism. It contains the base address of
the highest-level page-translation table, and also contains cache controls for the specified table.
•CR4—This register contains additional controls for various operating-mode features.
•CR8—This new register, accessible in 64-bit mode using the REX prefix, is introduced by the
AMD64 architecture. CR8 is used to prioritize external interrupts and is referred to as the task-
priority register  (TPR).
•RFLAGS —This register contains processor-status and processor-control fields. The status and
control fields are used primarily in the management of virtual-8086 mode, hardware multitasking,
and interrupts. 
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•EFER —This model-specific register contains status and controls for additional features not
managed by the CR0 and CR4 registers. Included in this register are the long-mode enable and
activation controls introduced by the AMD64 architecture.
Control registers CR1, CR5–CR7, and CR9–CR15 are reserved.
In legacy mode, all control registers and RFLAGS are 32 bits. The EFER register is 64 bits in all 
modes. The AMD64 architecture expands all 32-bit system-control registers to 64 bits. In 64-bit mode, 
the MOV CR n instructions read or write all 64 bits of these registers (operand-size prefixes are 
ignored). In compatibility and legacy modes, control-register writes fill the low 32 bits with data and the high 32 bits with zeros, and control-register reads return only the low 32 bits. 
In 64-bit mode, the high 32 bits of CR0 and CR4 are reserved and must be written with zeros. Writing 
a 1 to any of the high 32 bits results in a general-protection exception, #GP(0). All 64 bits of CR2 are writable. However, the MOV CR n instructions do not  check that addresses written to CR2 are within 
the virtual-address limitations of the processor implementation.
All CR3 bits are writable, except for unimplemented physical address bits, which must be cleared to 0. The upper 32 bits of RFLAGS are always read as zero by the processor. Attempts to load the upper 32 
bits of RFLAGS with anything other than zero are ignored by the processor.
3.1.1  CR0 Register
The CR0 register is shown in Figure 3-1 on page 42. The legacy CR0 register is identical to the low 32 
bits of this register (CR0 bits 31:0).
63 32
Reserved
31 30 29 28 19 18 17 16 15 6 5 4 3 2 1 0PG
CD
NWReservedA
MRW
PReserved
NE
ET
TS
EM
MP
PE
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Figure 3-1. Control Register 0 (CR0)
The functions of the CR0 control bits are (unless otherwise noted, all bits are read/write):
Protected-Mode Enable (PE) Bit.  Bit 0. Software enables protected mode by setting PE to 1, and 
disables protected mode by clearing PE to 0. When the processor is running in protected mode, 
segment-protection mechanisms are enabled.
See Section 4.9 “Segment-Protection Overview,” on page 104 for information on the segment-
protection mechanisms.
Monitor Coprocessor (MP) Bit.  Bit 1. Software uses the MP bit with the task-switched control bit 
(CR0.TS) to control whether execution of the WAIT/FWAIT instruction causes a device-not-available 
exception (#NM) to occur, as follows:
•If both the monitor-coprocessor and task-switched bits are set (CR0.MP=1 and CR0.TS=1), then
executing the WAIT/FWAIT instruction causes a device-not-available exception (#NM).
•If either the monitor-coprocessor or task-switched bits are clear (CR0.MP=0 or CR0.TS=0), then
executing the WAIT/FWAIT instruction proceeds normally.
Software typically should set MP to 1 if the processor implementation supports x87 instructions. This 
allows the CR0.TS bit to completely control when the x87-instruction context is saved as a result of a task switch.
Emulate Coprocessor (EM) Bit.  Bit 2. Software forces all x87 instructions to cause a device-not-
available exception (#NM) by setting EM to 1. Likewise, setting EM to 1 forces an invalid-opcode exception (#UD) when an attempt is made to execute any of the 64-bit or 128-bit media instructions Bits Mnemonic Description Access type
63:32 Reserved MBZ
31 PG Paging R/W
30 CD Cache Disable R/W
29 NW Not Writethrough R/W
28:19 Reserved do not change
18 AM Alignment Mask R/W
17 Reserved  do not change
16 WP Write Protect R/W1
15:6 Reserved do not change
5 NE Numeric Error R/W
4 ET Extension Type R
3 TS Task Switched R/W
2 EM Emulation R/W
1 MP Monitor Coprocessor R/W
0 PE Protection Enabled R/W1. Conditionally -- see description below.
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set results in an #NM exception instead.The exception handlers can emulate these instruction types if 
desired. Setting the EM bit to 1 does not cause an #NM exception when the WAIT/FWAIT instruction is executed.
Task Switched (TS) Bit.  Bit 3. When an attempt is made to execute an x87 or media instruction 
while TS=1, a device-not-available exception (#NM) occurs. Software can use this mechanism—sometimes referred to as “lazy context-switching”—to save the unit contexts before executing the next instruction of those types. As a result, the x87 and media instruction-unit contexts are saved only when necessary as a result of a task switch. 
When a hardware task switch occurs, TS is automatically set to 1. System software that implements 
software task-switching rather than using the hardware task-switch mechanism can still use the TS bit to control x87 and media instruction-unit context saves. In this case, the task-management software uses a MOV CR0 instruction to explicitly set the TS bit to 1 during a task switch. Software can clear the TS bit by either executing the CLTS instruction or by writing to the CR0 register directly. Long-mode system software can use this approach even though the hardware task-switch mechanism is not supported in long mode.
The CR0.MP bit controls whether the WAIT/FWAIT instruction causes an #NM exception when 
TS=1.
Extension Type (ET) Bit.  Bit 4, read-only. In some early x86 processors, software set ET to 1 to 
indicate support of the 387DX math-coprocessor instruction set. This bit is now reserved and forced to 1 by the processor. Software cannot clear this bit to 0.
Numeric Error (NE) Bit.  Bit 5. Clearing the NE bit to 0 disables internal control of x87 floating-point 
exceptions and enables external control. When NE is cleared to 0, the IGNNE# input signal controls whether x87 floating-point exceptions are ignored:
•When IGNNE# is 1, x87 floating-point exceptions are ignored.
•When IGNNE# is 0, x87 floating-point exceptions are reported by setting the FERR# input signal
to 1. External logic can use the FERR# signal as an external interrupt.
When NE is set to 1, internal control over x87 floating-point exception reporting is enabled and the external reporting mechanism is disabled. It is recommended that software set NE to 1. This enables optimal performance in handling x87 floating-point exceptions.
Write Protect (WP) Bit.  Bit 16. Read-only pages are protected from supervisor-level writes when the 
WP bit is set to 1. When WP is cleared to 0, supervisor software can write into read-only pages.
See Section 5.6 “Page-Protection Checks,” on page 161 for information on the page-protection 
mechanism. If the shadow stack feature has been enabled (CR4.CET=1), attempting to clear WP to 0 causes a general-protection exception (#GP).
Alignment Mask (AM) Bit.  Bit 18. Software enables automatic alignment checking by setting the 
AM bit to 1 when RFLAGS.AC=1. Alignment checking can be disabled by clearing either AM or 
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RFLAGS.AC to 0. When automatic alignment checking is enabled and CPL=3, a memory reference to 
an unaligned operand causes an alignment-check exception (#AC).
Not Writethrough (NW) Bit.  Bit 29. Ignored. This bit can be set to 1 or cleared to 0, but its value is 
ignored. The NW bit exists only for legacy purposes.
Cache Disable (CD) Bit.  Bit 30. When CD is cleared to 0, the internal caches are enabled. When CD 
is set to 1, no new data or instructions are brought into the internal caches. However, the processor still accesses the internal caches when CD = 1 under the following situations:
•Reads that hit in an internal cache cause the data to be read from the internal cache that reported the
hit.
•Writes that hit in an internal cache cause the cache line that reported the hit to be written back tomemory and invalidated in the cache. 
Cache misses do not affect the internal caches when CD = 1. Software can prevent cache access by setting CD to 1 and invalidating the caches.
Setting CD to 1 also causes the processor to ignore the page-level cache-control bits (PWT and PCD) 
when paging is enabled. These bits are located in the page-translation tables and CR3 register. See Section  “Page-Level Writethrough (PWT) Bit,” on page 155 and Section  “Page-Level Cache Disable (PCD) Bit,” on page 155 for information on page-level cache control.
See Section 7.6 “Memory Caches,” on page 203 for information on the internal caches.
Paging Enable (PG) Bit.  Bit 31. Software enables page translation by setting PG to 1, and disables 
page translation by clearing PG to 0. Page translation cannot be enabled unless the processor is in 
protected mode (CR0.PE=1). If software attempts to set PG to 1 when PE is cleared to 0, the processor causes a general-protection exception (#GP). 
See Section 5.1 “Page Translation Overview,” on page 127 for information on the page-translation 
Reserved Bits.  Bits 28:19, 17, 15:6, and 63:32. When writing the CR0 register, software should set

Reserved Bits.  Bits 28:19, 17, 15:6, and 63:32. When writing the CR0 register, software should set 
the values of reserved bits to the values found during the previous CR0 read. No attempt should be made to change reserved bits, and software should never rely on the values of reserved bits. In long mode, bits 63:32 are reserved and must be written with zero, otherwise a #GP occurs.
3.1.2  CR2 and CR3 Registers
The CR2 (page-fault linear address) register, shown in Figure 3-2 on page 45 and Figure 3-3 on 
page 45, and the CR3 (page-translation-table base address) register, shown in Figure 3-4 and 
Figure 3-5 on page 45, and Figure 3-6 on page 46, are used only by the page-translation mechanism. 
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Figure 3-2. Control Register 2 (CR2)—Legacy-Mode
 
Figure 3-3. Control Register 2 (CR2)—Long Mode
See Section  “CR2 Register,” on page 255 for a description of the CR2 register. 
The CR3 register is used to point to the base address of the highest-level page-translation table.
Figure 3-4. Control Register 3 (CR3)—Legacy-Mode Non-PAE Paging
Figure 3-5. Control Register 3 (CR3)—Legacy-Mode PAE Paging31 0
Page-Fault Virtual Address
63 32
31 0
31 12 11 5 4 3 2 0
Page-Directory-Table Base Address Reserved
PCD
PWTReserved
31 5 4 3 2 0
Page-Directory-Pointer-Table Base Address
PCD
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Figure 3-6. Control Register 3 (CR3)—Long Mode
The legacy CR3 register is described in Section 5.2.1 “CR3 Register,” on page 131, and the long-mode 
CR3 register is described in Section 5.3.2 “CR3,” on page 140.
3.1.3  CR4 Register
The CR4 register is shown in Figure 3-7. In legacy mode, the CR4 register is identical to the low 32 
bits of the register (CR4 bits 31:0). The features controlled by the bits in the CR4 register are model-specific extensions. Except for the performance-counter extensions (PCE) feature, software can use the CPUID instruction to verify that each feature is supported before using that feature. See Section 3.3 “Processor Feature Identification,” on page 71 for information on using the CPUID instruction.63 52 51 32
Reserved, MBZPage-Map Level-4 Table Base Address
(This is an architectural limit. A given implementation may support fewer bits.)
Page-Map Level-4 Table Base AddressUsage depends on state of Processor Context ID 
enablement (CR4.PCIDE). See below.
11 5 4 3 2  0
CR4.PCIDE=0 Reserved 
PCD
CR4.PCIDE=1Processor Context Identifier (See Section 5.5.1 
“Process Context Identifier,” on page 158 for more 
information.) 
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Figure 3-7. CR4 Register
The function of the CR4 control bits are (all bits are read/write):
Virtual-8086 Mode Extensions (VME).  Bit 0. Setting VME to 1 enables hardware-supported 
performance enhancements for software running in virtual-8086 mode. Clearing VME to 0 disables 
this support. The enhancements enabled when VME=1 include:63 32
Reserved
31 24 23 22 21 20 19 18 17 16 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CET 
PKE 
SMAP
SMEP
Reserved
OSXSA VE
PCIDE
FSGSBASEReserved
LA57
UMIP
OSXMMEXCPT
OSFXSR
PCE
PGE
MCE
PAE
PSE
DE
TSD
PVI
VME
Bits Mnemonic Description Access Type
63:24 Reserved MBZ
23 CET Control-flow Enforcement Technology R/W
22 PKE Protection Key Enable R/W
21 SMAP Supervisor Mode Access Protection R/W
20 SMEP Supervisor Mode Execution Prevention R/W
19 Reserved MBZ
18 OSXSA VE XSA VE and Processor Extended States Enable Bit R/W
17 PCIDE Process Context Identifier Enable R/W
16 FSGSBASEEnable RDFSBASE, RDGSBASE, WRFSBASE, and 
WRGSBASE instructionsR/W
15:13 Reserved MBZ
12 LA57 5-Level Paging Enable R/W
11 UMIP User Mode Instruction Prevention R/W
10 OSXMMEXCPT Operating System Unmasked Exception Support R/W
9 OSFXSR Operating System FXSA VE/FXRSTOR Support R/W
8 PCE Performance-Monitoring Counter Enable R/W
7 PGE Page-Global Enable R/W
6 MCE Machine Check Enable R/W
5 PAE Physical-Address Extension R/W
4 PSE Page Size Extensions R/W
3 DE Debugging Extensions R/W
2 TSD Time Stamp Disable R/W
1 PVI Protected-Mode Virtual Interrupts R/W
0 VME Virtual-8086 Mode Extensions R/W
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•Virtualized, maskable, external-interrupt control and notification using the VIF and VIP bits in the
RFLAGS register. Virtualizing affects the operation of several instructions that manipulate theRFLAGS.IF bit. 
•Selective intercept of software interrupts (INT n instructions) using the interrupt-redirection
bitmap in the TSS. 
Protected-Mode Virtual Interrupts (PVI).  Bit 1. Setting PVI to 1 enables support for protected-
mode virtual interrupts. Clearing PVI to 0 disables this support. When PVI=1, hardware support of two bits in the RFLAGS register, VIF and VIP, is enabled. 
Only the STI and CLI instructions are affected by enabling PVI. Unlike the case when CR0.VME=1, 
the interrupt-redirection bitmap in the TSS cannot be used for selective INT n interception.
PVI enhancements are also supported in long mode. See Section 8.10 “Virtual Interrupts,” on page 287 for more information on using PVI.
Time-Stamp Disable (TSD).  Bit 2. The TSD bit allows software to control the privilege level at 
which the time-stamp counter can be read. When TSD is cleared to 0, software running at any privilege level can read the time-stamp counter using the RDTSC or RDTSCP instructions. When TSD is set to 
1, only software running at privilege-level 0 can execute the RDTSC or RDTSCP instructions.
Debugging Extensions (DE).  Bit 3. Setting the DE bit to 1 enables the I/O breakpoint capability and 
enforces treatment of the DR4 and DR5 registers as reserved. Software that accesses DR4 or DR5 when DE=1 causes a invalid opcode exception (#UD).
When the DE bit is cleared to 0, I/O breakpoint capabilities are disabled. Software references to the 
DR4 and DR5 registers are aliased to the DR6 and DR7 registers, respectively.
Page-Size Extensions (PSE).  Bit 4. Setting PSE to 1 enables the use of 4-Mbyte physical pages. 
With PSE=1, the physical-page size is selected between 4 Kbytes and 4 Mbytes using the page-directory entry page-size field (PS). Clearing PSE to 0 disables the use of 4-Mbyte physical pages and restricts all physical pages to 4 Kbytes.
The PSE bit has no effect when physical-address extensions are enabled (CR4.PAE=1). Because long 
mode requires CR4.PAE=1, the PSE bit is ignored when the processor is running in long mode.
See Section  “4-Mbyte Page Translation,” on page 134 for more information on 4-Mbyte page 
translation.
Physical-Address Extension (PAE).  Bit 5. Setting PAE to 1 enables the use of physical-address 
extensions and 2-Mbyte physical pages. Clearing PAE to 0 disables these features.
With PAE=1, the page-translation data structures are expanded from 32 bits to 64 bits, allowing the 
translation of up to 52-bit physical addresses. Also, the physical-page size is selectable between 4 Kbytes and 2 Mbytes using the page-directory-entry page-size field (PS). Long mode requires PAE to be enabled in order to use the 64-bit page-translation data structures to translate 64-bit virtual addresses to 52-bit physical addresses.
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See Section 5.2.3 “PAE Paging,” on page 135 for more information on physical-address extensions.
Machine-Check Enable (MCE).  Bit 6. Setting MCE to 1 enables the machine-check exception 
mechanism. Clearing this bit to 0 disables the mechanism. When enabled, a machine-check exception 
(#MC) occurs when an uncorrectable machine-check error is encountered. 
Regardless of whether machine-check exceptions are enabled, the processor records enabled-errors 
when they occur. Error-reporting is performed by the machine-check error-reporting register banks. Each bank includes a control register for enabling error reporting and a status register for capturing errors. Correctable machine-check errors are also reported, but they do not cause a machine-check exception.
See Chapter 9, “Machine Check Architecture,” for a description of the machine-check mechanism, the 
registers used, and the types of errors captured by the mechanism.
Page-Global Enable (PGE).  Bit 7. When page translation is enabled, system-software performance 
can often be improved by making some page translations global  to all tasks and procedures. Setting 
PGE to 1 enables the global-page mechanism. Clearing this bit to 0 disables the mechanism. When PGE is enabled, system software can set the global-page (G) bit in the lowest level of the page-

translation hierarchy to 1, indicating that the page translation is global. Page translations marked as global are not invalidated in the TLB when the page-translation-table base address (CR3) is updated. When the G bit is cleared, the page translation is not global. All supported physical-page sizes also support the global-page mechanism. See Section 5.5.2 “Global Pages,” on page 158 for information on using the global-page mechanism.
Performance-Monitoring Counter Enable (PCE).  Bit 8. Setting PCE to 1 allows software running 
at any privilege level to use the RDPMC instruction. Software uses the RDPMC instruction to read the performance-monitoring counter MSRs, *PerfCtr n. Clearing PCE to 0 allows only the most-privileged 
software (CPL=0) to use the RDPMC instruction.
FXSAVE/FXRSTOR Support (OSFXSR).  Bit 9. System software must set the OSFXSR bit to 1 to 
enable use of the legacy SSE instructions. When this bit is set to 1, it also indicates that system software uses the FXSA VE and FXRSTOR instructions to save and restore the processor state for the x87, 64-bit media, and 128-bit media instructions.
Clearing the OSFXSR bit to 0 indicates that legacy SSE instructions cannot be used. Attempts to use 
those instructions while this bit is clear result in an invalid-opcode exception (#UD). Software can continue to use the FXSA VE/FXRSTOR instructions for saving and restoring the processor state for the x87 and 64-bit media instructions.
Unmasked Exception Support (OSXMMEXCPT).  Bit 10. System software must set the 
OSXMMEXCPT bit to 1 when it supports the SIMD floating-point exception (#XF) for handling of unmasked 256-bit and 128-bit media floating-point errors. Clearing the OSXMMEXCPT bit to 0 indicates the #XF handler is not supported. When OSXMMEXCPT=0, unmasked 128-bit media floating-point exceptions cause an invalid-opcode exception (#UD). See “SIMD Floating-Point Exception Causes” in V olume 1 for more information on unmasked SSE floating-point exceptions.
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User Mode Instruction Prevention (UMIP).  Bit 11. Setting UMIP to 1 enables a security mode to 
restrict certain instructions executing at CPL>0 so that they do not reveal information about structures 
that are controlled by the processor when it is at CPL=0. When UMIP is enabled, execution of SGDT, SIDT, SLDT, SMSW and STR instructions become available only at CPL=0 and any attempt to execute them with CPL>0 results in a #GP fault with error code 0. See Section 6 “System Instructions,” on page 170 for more information about UMIP.
5-Level Paging Enable (LA57)  .  Bit 12. Setting this bit to 1 while EFER[LMA]=1 enables 5-Level 
paging. 5-Level paging allows for the translation of up to 57 virtual address bits. See Section Section 5.3 “Long-Mode Page Translation,” on page 139 for a description of 4-Level and 5-Level paging. 
FSGSBASE.  Bit 16. System software must set this bit to 1 to enable the execution of the 
RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE instructions when supported. When enabled, these instructions allow software running in 64-bit mode at any privilege level to read and write the FS.base and GS.base hidden segment register state. See the discussion of segment registers in 64-bit mode in Section 4.5.3 “Segment Registers in 64-Bit Mode,” on page 80. Also see descriptions of the RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE instructions in V olume 3. 
Processor Context Identifier Enable (PCIDE).  Bit 17. Enable support for Process Context 
Identifiers (PCIDs). System software must set this bit to 1 to enable execution of the INVPCID instruction when supported. Can only be set in long mode (EFER.LMA = 1). See Chapter 5.5.1, “Process Context Identifier,” for more information on Process Context Identifiers. 
XSAVE and Extended States (OSXSAVE).  Bit 18. After verifying hardware support for the 
extended processor state management instructions, operating system software sets this bit to indicate support for the XGETBV , XSA VE and XRSTOR instructions.
Setting this bit also:
•allows the execution of the XGETBV and XSETBV instructions, and
•enables the XSA VE and XRSTOR instructions to save and restore the x87 FPU state (including
MMX registers), along with other processor extended states enabled in XCR0.
After initializing the XSA VE/XRSTOR save area, XSA VEOPT (if supported) may be used to save x87 FPU and other enabled extended processor state. For more information on XSA VEOPT, see individual instruction listing in Chapter 2 of V olume 4.
Note that legacy SSE instruction execution must be enabled prior to enabling extended processor state 
Supervisor Mode Execution Prevention (SMEP).  Bit 20. Setting this bit enables the supervisor 
mode execution prevention feature, if supported. This feature prevents the execution of instructions that reside in pages accessible by user-mode software when the processor is in supervisor-mode. See Section 5.6 “Page-Protection Checks,” on page 161 for more information. 
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Supervisor Mode Access Prevention (SMAP).  Bit 21. Setting this bit enables the supervisor mode 
access prevention feature, if supported. This feature prevents certain data accesses to pages accessible 
by user-mode software when the processor is in supervisor mode. See Section 5.6.6 “Supervisor-Mode Access Prevention(CR4.SMAP) Bit,” on page 164 for more information. 
Protection Key Enable (PKE).  Bit 22. Enable support for memory Protection Keys. Also enables 
support for the RDPKRU and WRPKRU instructions. A MOV to CR4 that changes CR4.PKE from 0 to 1 causes all cached entries in the TLB for the logical processor to be invalidated. (See Section 5.6.7 
“Memory Protection Keys (MPK) Bit,” on page 164 for more information on memory protection 
keys.)
Control-flow Enforcement Technology (CET).  Bit 23. Setting this bit enables the shadow stack 
feature. This feature ensures that return addresses read from the stack by RET and IRET instructions originated from a CALL instruction or similar control transfer. 
See Section 18 “Shadow Stacks,” on page 671 for more information. Before setting this bit, CR0.WP 
must be set to 1, otherwise a #GP fault is generated.
CR1 and CR5–CR7 Registers.  Control registers CR1, CR5–CR7, and CR9–CR15 are reserved. 
Attempts by software to use these registers result in an undefined-opcode exception (#UD).
3.1.4  Additional Control Registers in 64-Bit-Mode
In 64-bit mode, additional encodings are available to address up to eight additional control registers. 
The REX.R bit, in a REX prefix, is used to modify the ModRM reg field when that field encodes a 
control register, as shown in “REX Prefixes” in V olume 3. These additional encodings enable the processor to address CR8–CR15. 
One additional control register, CR8, is defined in 64-bit mode for all hardware implementations, as 
described in “CR8 (Task Priority Register, TPR),” below. Access to the CR9–CR15 registers is implementation-dependent. Any attempt to access an unimplemented register results in an invalid-opcode exception (#UD).
3.1.5  CR8 (Task Priority Register, TPR)
The AMD64 architecture introduces a new control register, CR8, defined as the task priority register 
(TPR). The register is accessible in 64-bit mode using the REX prefix. See Section 8.5.2 “External Interrupt Priorities,” on page 266 for a description of the TPR and how system software can use the TPR for controlling external interrupts.
3.1.6  RFLAGS Register
The RFLAGS register contains two different types of information:
•Control bits provide system-software controls and directional information for string operations.
Some of these bits can have privilege-level restrictions.
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•Status bits  provide information resulting from logical and arithmetic operations. These are written
by the processor and can be read by software running at any privilege level.
Figure 3-8 on page 52 shows the format of the RFLAGS register. The legacy EFLAGS register is 
identical to the low 32 bits of the register shown in Figure 3-8 (RFLAGS bits 31:0). The term rFLAGS  
is used to refer to the 16-bit, 32-bit, or 64-bit flags register, depending on context.
Figure 3-8. RFLAGS Register
The functions of the RFLAGS control and status bits used by application software are described in 
“Flags Register” in V olume 1. The functions of RFLAGS system bits are (unless otherwise noted, all bits are read/write):63 32
Reserved
31 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ID
VIP
VIF
AC
VM
RF
Reserved
NT
IOPL
OF
DF
IF
TF
SF
ZF
Reserved
AF
Reserved
PF
Reserved
CF
Bits Mnemonic Description Access type
63:22 Reserved RAZ
21 ID ID Flag R/W
20 VIP Virtual Interrupt Pending R/W
19 VIF Virtual Interrupt Flag R/W
18 AC Alignment Check R/W
17 VM Virtual-8086 Mode R/W
16 RF Resume Flag R/W
15 Reserved RAZ

Reserved
Reserved
ID
VIP
VIF
AC
VM
RF
Reserved
NT
IOPL
OF
DF
IF
TF
SF
ZF
Reserved
AF
Reserved
PF
Reserved
CF
14 NT Nested Task R/W
13:12 IOPL I/O Privilege Level R/W
11 OF Overflow Flag R/W
10 DF Direction Flag R/W
9 IF Interrupt Flag R/W
8 TF Trap Flag R/W
7 SF Sign Flag R/W
6 ZF Zero Flag R/W
5 Reserved RAZ
4 AF Auxiliary Flag R/W
3 Reserved RAZ
2 PF Parity Flag R/W
1 Reserved RA1
0 CF Carry Flag R/W
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Trap Flag (TF) Bit.  Bit 8. Software sets the TF bit to 1 to enable single-step mode during software 
debug. Clearing this bit to 0 disables single-step mode. 
When single-step mode is enabled at the start of an instruction's execution, a debug exception (#DB) 
occurs immediately after the instruction completes execution. Single stepping is automatically disabled (TF is set to 0) when the #DB exception occurs or when any exception or interrupt occurs.
See Section 13.1.4 “Single Stepping,” on page 407 for information on using the single-step mode 
during debugging.
Interrupt Flag (IF) Bit.  Bit 9. Software sets the IF bit to 1 to enable maskable interrupts. Clearing this 
bit to 0 causes the processor to ignore maskable interrupts. The state of the IF bit does not affect the response of a processor to non-maskable interrupts, software-interrupt instructions, or exceptions.
The ability to modify the IF bit depends on several factors:
•The current privilege-level (CPL)
•The I/O privilege level (RFLAGS.IOPL)
•Whether or not virtual-8086 mode extensions are enabled (CR4.VME=1)
•Whether or not protected-mode virtual interrupts are enabled (CR4.PVI=1)
See Section 8.1.4 “Masking External Interrupts,” on page 243 for information on interrupt masking. 
See Section 6.2.3 “Accessing the RFLAGS Register,” on page 178 for information on the specific 
instructions used to modify the IF bit.
I/O Privilege Level Field (IOPL) Field.  Bits 13:12. The IOPL field specifies the privilege level 
required to execute I/O address-space instructions (i.e., instructions that address the I/O space rather 
than memory-mapped I/O, such as IN, OUT, INS, OUTS, etc.). For software to execute these instructions, the current privilege-level (CPL) must be equal to or higher than (lower numerical value than) the privilege specified by IOPL (CPL <= IOPL). If the CPL is lower than (higher numerical value than) that specified by the IOPL (CPL > IOPL), the processor causes a general-protection exception (#GP) when software attempts to execute an I/O instruction. See “Protected-Mode I/O” in V olume 1 for information on how IOPL controls access to address-space I/O.
Virtual-8086 mode uses IOPL to control virtual interrupts and the IF bit when virtual-8086 mode 
extensions are enabled (CR4.VME=1). The protected-mode virtual-interrupt mechanism (PVI) also uses IOPL to control virtual interrupts and the IF bit when PVI is enabled (CR4.PVI=1). See Section 8.10 “Virtual Interrupts,” on page 287 for information on how IOPL is used by the virtual interrupt mechanism.
Nested Task (NT) Bit.  Bit 14, IRET reads the NT bit to determine whether the current task is nested 
within another task. When NT is set to 1, the current task is nested within another task. When NT is cleared to 0, the current task is at the top level (not nested).
The processor sets the NT bit during a task switch resulting from a CALL, interrupt, or exception 
through a task gate. When an IRET is executed from legacy mode while the NT bit is set, a task switch occurs. See Section 12.3.3 “Task Switches Using Task Gates,” on page 384 for information on 
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switching tasks using task gates, and Section 12.3.4 “Nesting Tasks,” on page 386 for information on 
task nesting.
Resume Flag (RF) Bit.  Bit 16. The RF bit, when set to 1, temporarily disables instruction breakpoint 
reporting to prevent repeated debug exceptions (#DB) from occurring. This allows an instruction which had been inhibited by an instruction-breakpoint debug exception to be restarted by the debug exception handler.
The processor clears the RF bit after every instruction is successfully executed, except when theinstruction is:
•An IRET that sets the RF bit.
•JMP, CALL, or INT n through a task gate.
In both of the above cases, RF is not cleared to 0 until the next instruction successfully executes.
When an exception occurs (or when a string instruction is interrupted), the processor normally sets 
RF=1 in the RFLAGS image saved on the interrupt stack. However, when a #DB exception occurs as a result of an instruction breakpoint, the processor clears the RF bit to 0 in the interrupt-stack RFLAGS image.
For instruction restart to work properly following an instruction breakpoint, the #DB exception 
handler must set RF to 1 in the interrupt-stack RFLAGS image. When an IRET is later executed to return to the instruction that caused the instruction-breakpoint #DB exception, the set RF bit (RF=1) is loaded from the interrupt-stack RFLAGS image. RF is not cleared by the processor until the instruction causing the #DB exception successfully executes.
Virtual-8086 Mode (VM) Bit.  Bit 17. Software sets the VM bit to 1 to enable virtual-8086 mode. 
Software clears the VM bit to 0 to disable virtual-8086 mode. System software can only change this bit using a task switch or an IRET. It cannot modify the bit using the POPFD instruction.
Alignment Check (AC) Bit.  Bit 18. Software enables automatic alignment checking by setting the 
AC bit to 1 when CR0.AM=1. Alignment checking can be disabled by clearing either AC or CR0.AM to 0. When automatic alignment checking is enabled and the current privilege-level (CPL) is 3 (least privileged), a memory reference to an unaligned operand causes an alignment-check exception (#AC).
When the supervisor mode access prevention feature is enabled (CR4.SMAP=1), certain supervisor-
mode data accesses to pages accessible by user mode are allowed only if RFLAGS.AC=1. See Section 5.6.6 “Supervisor-Mode Access Prevention(CR4.SMAP) Bit,” on page 164 for more 
Virtual Interrupt (VIF) Bit.  Bit 19. The VIF bit is a virtual image of the RFLAGS.IF bit. It is enabled 
when either virtual-8086 mode extensions are enabled (CR4.VME=1) or protected-mode virtual interrupts are enabled (CR4.PVI=1), and the RFLAGS.IOPL field is less than 3. When enabled, instructions that ordinarily would modify the IF bit actually modify the VIF bit with no effect on the RFLAGS.IF bit.
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System software that supports virtual-8086 mode should enable the VIF bit using CR4.VME. This 
allows 8086 software to execute instructions that can set and clear the RFLAGS.IF bit without causing an exception. With VIF enabled in virtual-8086 mode, those instructions set and clear the VIF bit instead, giving the appearance to the 8086 software that it is modifying the RFLAGS.IF bit. System software reads the VIF bit to determine whether or not to take the action desired by the 8086 software (enabling or disabling interrupts by setting or clearing the RFLAGS.IF bit).
In long mode, the use of the VIF bit is supported when CR4.PVI=1. See Section 8.10 “Virtual 
Interrupts,” on page 287 for more information on virtual interrupts.
Virtual Interrupt Pending (VIP) Bit.  Bit 20. The VIP bit is provided as an extension to both virtual-
8086 mode and protected mode. It is used by system software to indicate that an external, maskable interrupt is pending (awaiting) execution by either a virtual-8086 mode or protected-mode interrupt-service routine. Software must enable virtual-8086 mode extensions (CR4.VME=1) or protected-mode virtual interrupts (CR4.PVI=1) before using VIP. 
VIP is normally set to 1 by a protected-mode interrupt-service routine that was entered from virtual-
8086 mode as a result of an external, maskable interrupt. Before returning to the virtual-8086 mode application, the service routine sets VIP to 1 if EFLAGS.VIF=1. When the virtual-8086 mode application attempts to enable interrupts by clearing EFLAGS.VIF to 0 while VIP=1, a general-protection exception (#GP) occurs. The #GP service routine can then decide whether to allow the virtual-8086 mode service routine to handle the pending external, maskable interrupt. (EFLAGS is specifically referred to in this case because virtual-8086 mode is supported only from legacy mode.)
In long mode, the use of the VIP bit is supported when CR4.PVI=1. See Section 8.10 “Virtual 
Interrupts,” on page 287 for more information on virtual-8086 mode interrupts and the VIP bit.
Processor Feature Identification (ID) Bit.  Bit 21. The ability of software to modify this bit 
indicates that the processor implementation supports the CPUID instruction. See Section 3.3 
“Processor Feature Identification,” on page 71 for more information on the CPUID instruction.
3.1.7  Extended Feature Enable Register (EFER)
The extended-feature-enable register (EFER) contains control bits that enable additional processor

The extended-feature-enable register (EFER) contains control bits that enable additional processor 
features not controlled by the legacy control registers. The EFER is a model-specific register (MSR) with an address of C000_0080h (see Section 3.2 “Model-Specific Registers (MSRs),” on page 59 for more information on MSRs). It can be read and written only by privileged software. Figure 3-9 on page 56 shows the format of the EFER register.
Note: Attempting to set an enable bit for a feature that is not supported by the processor will result in 
a #GP(0) exception.
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Figure 3-9. Extended Feature Enable Register (EFER)
The defined EFER bits shown in Figure 3-9 above are described below:
System-Call Extension (SCE) Bit.  Bit 0, read/write. Setting this bit to 1 enables the SYSCALL and 
SYSRET instructions. Application software can use these instructions for low-latency system calls 
and returns in a non-segmented (flat) address space. See Section 6.1 “Fast System Call and Return,” on page 173 for additional information.
Long Mode Enable (LME) Bit.  Bit 8, read/write. Setting this bit to 1 enables the processor to activate 
long mode. Long mode is not activated until software enables paging some time later. When paging is enabled after LME is set to 1, the processor sets the EFER.LMA bit to 1, indicating that long mode is not only enabled but also active. See Chapter 14, “Processor Initialization and Long Mode Activation,” for more information on activating long mode.
Long Mode Active (LMA) Bit.  Bit 10, read/write. This bit indicates that long mode is active. The 
processor sets LMA to 1 when both long mode and paging have been enabled by system software. See 63 32
Reserved
31 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 1 0
Reserved
AIBRSE
UAIE Reserved
INTWB
MCOMMIT
Reserved
TCE
FFXSR
LMSLE
SVME
NXE
LMA
MBZ
LMEReserved
SCE
63:22 Reserved MBZ
21 AIBRSE Automatic IBRS Enable R/W
20 UAIE Upper Address Ignore Enable R/W 
18 INTWB Interruptible WBINVD/WBNOINVD enable R/W
17 MCOMMIT Enable MCOMMIT instruction R/W
16 Reserved MBZ
15 TCE Translation Cache Extension R/W
14 FFXSR Fast FXSA VE/FXRSTOR R/W
13 LMSLE Long Mode Segment Limit Enable R/W
12 SVME Secure Virtual Machine Enable R/W
11 NXE No-Execute Enable R/W
10 LMA Long Mode Active R/W
9 Reserved MBZ
8 LME Long Mode Enable R/W
7:1 Reserved RAZ
0 SCE System Call Extensions R/W
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Chapter 14, “Processor Initialization and Long Mode Activation,” for more information on activating 
long mode.
When LMA=1, the processor is running either in compatibility mode or 64-bit mode, depending on the 
value of the L bit in a code-segment descriptor, as shown in Figure 1-6 on page 12. 
When LMA=0, the processor is running in legacy mode. In this mode, the processor behaves like a standard 32-bit x86 processor, with none of the new 64-bit features enabled. When writing the EFER register the value of this bit must be preserved. Software must read the EFER register to determine the value of LMA, change any other bits as required and then write the EFER register. An attempt to write a value that differs from the state determined by hardware results in a #GP fault.
No-Execute Enable (NXE) Bit.  Bit 11, read/write. Setting this bit to 1 enables the no-execute page-
protection feature. The feature is disabled when this bit is cleared to 0. See Section  “No Execute (NX) 
Bit,” on page 156 for more information.
Before setting NXE, system software should verify the processor supports the feature by examining 
the feature flag CPUID Fn8000_0001_EDX[NX]. See Section 3.3 “Processor Feature Identification,” on page 71 for information on using the CPUID instruction.
Secure Virtual Machine Enable (SVME) Bit.  Bit 12, read/write. Enables the SVM extensions. 
When this bit is zero, the SVM instructions cause #UD exceptions. EFER.SVME defaults to a reset value of zero. The effect of turning off EFER.SVME while a guest is running is undefined; therefore, the VMM should always prevent guests from writing EFER. SVM extensions can be disabled by setting VM_CR.SVME_DISABLE. For more information, see descriptions of LOCK and SMVE_DISABLE bits in Section 15.30.1 “VM_CR MSR (C001_0114h),” on page 583.
Long Mode Segment Limit Enable (LMSLE) bit.  Bit 13, read/write. Setting this bit to 1 enables 
certain limit checks in 64-bit mode. This feature has been deprecated and is not supported by all processor implementations. If CPUID Fn8000_0008_EBX[EferLmlseUnsupported](bit 20)=1, 64-bit mode segment limit checking is not supported and attempting to set EFER.LMSLE =1 causes a #GP exception. See Section 4.12.2 “Data Limit Checks in 64-bit Mode,” on page 123, for more information on these limit checks.
Fast FXSAVE/FXRSTOR (FFXSR) Bit.  Bit 14, read/write. Setting this bit to 1 enables the FXSA VE 
and FXRSTOR instructions to execute faster in 64-bit mode at CPL 0. This is accomplished by not saving or restoring the XMM registers (XMM0-XMM15). The FFXSR bit has no effect when the FXSA VE/FXRSTOR instructions are executed in non 64-bit mode, or when CPL is > 0. The FFXSR bit does not affect the save/restore of the legacy x87 floating-point state, or the save/restore of MXCSR.
Before setting FFXSR, system software should verify whether this feature is supported by examining 
the feature flag CPUID Fn8000_0001_EDX[FFXSR]. See Section 3.3 “Processor Feature Identification,” on page 71 for information on using the CPUID instruction.
Translation Cache Extension (TCE) Bit.  Bit 15, read/write. Setting this bit to 1 changes how the 
INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these 
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instructions remove the target PTE from the TLB as well as all upper-level table entries that are cached 
in the TLB, whether or not they are associated with the target PTE. When this bit is set, these 
instructions will remove the target PTE and only those upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. This may provide a performance benefit.
Page table management software must be written in a way that takes this behavior into account. 
Software that was written for a processor that does not cache upper-level table entries may result in stale entries being incorrectly used for translations when TCE is enabled. Software that is compatible with TCE mode will operate in either mode.
For software using INVLPGB to broadcast TLB invalidations, the invalidations are controlled by the 
EFER.TCE value on the processor executing the INVLPGB instruction.
Before setting TCE, system software should verify that this feature is supported by examining the 
feature flag CPUID Fn8000_0001_ECX[TCE]. See Section 3.3 “Processor Feature Identification,” on page 71 for information on using the CPUID instruction.
Mcommit Enable (MCOMMIT) Bit.  Bit 17, read/write. Setting this bit to 1 enables the MCOMMIT 
instruction. When clear, attempting to execute MCOMMIT causes a #UD exception.
Interruptible Wbinvd (INTWB) Bit.  Bit 18. Setting this bit to 1 allows the WBINVD and 
WBNOINVD instructions to be interruptible. See WBINVD and WBNOINVD in V olume 3.
Upper Address Ignore Enable (UAIE) Bit.  Bit 20. Setting this bit to 1 excludes bits 63:57 of an 
address from the canonical check for some memory references. Section 5.10 “Upper Address Ignore,” 
on page 168.
Automatic IBRS Enable (AIBRSE) Bit.  Bit 21, read/write. Setting this bit to 1 enables Automatic 
IBRS (Indirect Branch Restricted Speculation). When Automatic IBRS is enabled, the following processes have IBRS protection even when SPEC_CTRL[IBRS] is not set:
•Processes running at CPL=0
•Processes running as host when Secure Nested Paging (SEV-SNP) is enabled
When Automatic IBRS is enabled, the internal return address stack used for return address predictions 
is cleared on VMEXIT. More information about IBRS protection can be found in Section 3.2.9 “Speculation Control MSRs,” on page 66. 
3.1.8  Extended Control Registers (XCRn)
Extended control registers (XCRn) form a new register space that is available for managing processor 
architectural features and capabilities. Currently only XCR0 is defined. All other XCR registers are reserved. For more details on the Extended Control Registers, see “Extended Control Registers” in V olume 4, Chapter 1. 
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3.2 Model-Specific Registers (MSRs)
Processor implementations provide model-specific registers (MSRs) for software control over the 
unique features supported by that implementation. Software reads and writes MSRs using the privileged RDMSR and WRMSR instructions. Implementations of the AMD64 architecture can contain a mixture of two basic MSR types:
•Legacy MSRs . The AMD family of processors often share model-specific features with other x86
processor implementations. Where possible, AMD implementations use the same MSRs for the
same functions. For example, the memory-typing and debug-extension MSRs are implemented onmany AMD and non-AMD processors.

•AMD model-specific MSRs. There are many MSRs common to the AMD family of processors butnot to legacy x86 processors. Where possible, AMD implementations use the same AMD-specificMSRs for the same functions.
Every model-specific register, as the name implies, is not necessarily implemented by all members of the AMD family of processors. Appendix A, “MSR Cross-Reference,” lists MSR-address ranges 
currently used by various AMD and other x86 processors.
The AMD64 architecture includes a number of features that are controlled using MSRs. Those MSRs 
are shown in Figure 3-10. The EFER register—described in Section 3.1.7 “Extended Feature Enable Register (EFER),” on page 55—is also an MSR.
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Figure 3-10. AMD64 Architecture Model-Specific Registers
The following sections briefly describe the MSRs in the AMD64 architecture.
3.2.1  System Configuration Register (SYSCFG)
The system-configuration register (SYSCFG) contains control bits for enabling and configuring 
system bus features. SYSCFG is a model-specific register (MSR) with an address of C001_0010h. Figure 3-11 on page 61 shows the format of the SYSCFG register. Some features are implementation 
specific, and are described in the BIOS and Kernel Developer’s Guide (BKDG) or Processor 
Programming Reference Manual   applicable to your product. Implementation-specific features are not 
shown in Figure 3-11.
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Figure 3-11. System-Configuration Register (SYSCFG)
The function of the SYSCFG bits are (all bits are read/write unless otherwise noted):
MtrrFixDramEn Bit.  Bit 18. Setting this bit to 1 enables use of the RdMem and WrMem attributes in 
the fixed-range MTRR registers. When cleared, these attributes are disabled. The RdMem and 
WrMem attributes allow system software to define fixed-range IORRs using the fixed-range MTRRs. See Section 7.9.1 “Extended Fixed-Range MTRR Type-Field Encodings,” on page 231 for information on using this feature.
MtrrFixDramModEn Bit.  Bit 19. Setting this bit to 1 allows software to read and write the RdMem 
and WrMem bits. When cleared, writes do not modify the RdMem and WrMem bits, and reads return 0. See Section 7.9.1 “Extended Fixed-Range MTRR Type-Field Encodings,” on page 231 for 
information on using this feature.
MtrrVarDramEn Bit.  Bit 20. Setting this bit to 1 enables the TOP_MEM register and the variable-
range IORRs. These registers are disabled when the bit is cleared to 0. See Section 7.9.2 “IORRs,” on 
page 233 and Section 7.9.4 “Top of Memory,” on page 235 for information on using these features.
MtrrTom2En Bit.  Bit 21. Setting this bit to 1 enables the TOP_MEM2 register. The register is 
disabled when this bit is cleared to 0. See Section 7.9.4 “Top of Memory,” on page 235 for information 
on using this feature.
Tom2ForceMemTypeWB.  Bit 22. Setting this bit to 1 forces the default memory type for memory 
between 4GB and the address specified by TOP_MEM2 to be write back instead of the memory type defined by MTRRdefType[Type]. For this bit to have any effect, MTRRdefType[E] must be 1. MTRR variable-range settings and PAT can be used to override this memory type.31  27 26 25 24 23 22 21 20 19 18 17 0
Reserved
HMKE
VMPLE
SNPE
MEME
FWB
TOM2
MVDM
MFDM
MFDE Reserved
31:27 Reserved MBZ
26 HMKE HostMultiKeyMemEncrModeEn R/W
25 VMPLE VMPLEn R/W
24 SNPE SecureNestedPagingEn R/W
23 MEME MemEncryptionModeEn R/W
22 FWB Tom2ForceMemTypeWB R/W
21 TOM2 MtrrTom2En R/W
20 MVDM MtrrVarDramEn R/W
19 MFDM MtrrFixDramModEn R/W
18 MFDE MtrrFixDramEn R/W
17:0 Reserved MBZ
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MemEncryptionModeEn.  Bit 23. Setting this bit to 1 enables the SME (Section 7.10 “Secure 
Memory Encryption,” on page 237) and SEV (Section 15.34 “Secure Encrypted Virtualization,” on 
page 588) memory encryption features. When cleared, these features are disabled. Once this bit or 
HostMultiKeyMemEncrModeEn is set to 1, it cannot be changed.
SecureNestedPagingEn. Bit 24. Setting this bit to 1 enables SEV-SNP (Section 15.36 “Secure Nested 
Paging (SEV-SNP),” on page 601). When cleared, this feature is disabled. Once this bit is set to 1, it cannot be changed. This bit can only be set if MemEncryptionModeEn is already set or is simultaneously also set to 1. After SecureNestedPagingEn is set to 1, certain MSRs may no longer be written. See Section 15.36.2 “Enabling SEV-SNP,” on page 602 for details.
VMPLEn . Bit 25. Setting this bit to 1 enables the VMPL feature (Section 15.36.7 “Virtual Machine 
Privilege Levels,” on page 606). Software should set this bit to 1 when SecureNestedPagingEn is 
being set to 1. Once SecureNestedPagingEn is set to 1, VMPLEn cannot be changed. 
HostMultiKeyMemEncrModeEn.  Bit 26. Setting this bit to 1 enables the SME-MK memory 
encryption feature (See Section 7.10 “Secure Memory Encryption,” on page 237). When cleared, this 
feature is disabled. Once this bit or MemEncryptionModeEn is set to 1, it cannot be changed.
3.2.2  System-Linkage Registers
System-linkage MSRs are used by system software to allow fast control transfers between applications 
and the operating system. The functions of these registers are:
STAR, LSTAR, CSTAR, and SFMASK Registers.  These registers are used to provide mode-
dependent linkage information for the SYSCALL and SYSRET instructions. STAR is used in legacy modes, LSTAR in 64-bit mode, and CSTAR in compatibility mode. SFMASK is used by the SYSCALL instruction for RFLAGS in long mode.
FS.base and GS.base Registers.  These registers allow 64-bit base-address values to be specified 
for the FS and GS segments, for use in 64-bit mode. See Section  “FS and GS Registers in 64-Bit Mode,” on page 80 for a description of the special treatment the FS and GS segments receive.
KernelGSbase Register.  This register is used by the SWAPGS instruction. This instruction 
exchanges the value located in KernelGSbase with the value located in GS.base.
SYSENTER x Registers.  The SYSENTER_CS, SYSENTER_ESP, and SYSENTER_EIP registers 
are used to provide linkage information for the SYSENTER and SYSEXIT instructions. These instructions are only used in legacy mode.
The system-linkage instructions and their use of MSRs are described in Section 6.1 “Fast System Call 
and Return,” on page 173. 
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3.2.3  Memory-Typing Registers
Memory-typing MSRs are used to characterize, or type, memory. Memory typing allows software to 
control the cacheability of memory, and determine how accesses to memory are ordered. The memory-typing registers perform the following functions:
MTRRcap Register.  This register contains information describing the level of MTRR support 
provided by the processor.
MTRRdefType Register.  This register establishes the default memory type to be used for physical 
memory that is not specifically characterized using the fixed-range and variable-range MTRRs.
MTRRphysBasen and MTRRphysMaskn Registers.  These registers form a register pair that can 
be used to characterize any address range within the physical-memory space, including all of physical memory. Up to eight address ranges of varying sizes can be characterized using these registers.
MTRRfixn Registers.  These registers are used to characterize fixed-size memory ranges in the first 1 
Mbytes of physical-memory space.
PAT Register.  This register allows memory-type characterization based on the virtual (linear) 
address. It is an extension to the PCD and PWT memory types supported by the legacy paging mechanism. The PAT mechanism provides the same memory-typing capabilities as the MTRRs, but with the added flexibility provided by the paging mechanism.
TOP_MEM and TOP_MEM2 Registers.  These top-of-memory registers allow system software to 
specify physical addresses ranges as memory-mapped I/O locations.
Refer to Section 7.7 “Memory-Type Range Registers,” on page 216 for more information on using 
these registers.
3.2.4  Debug-Extension Registers
The debug-extension MSRs provide software-debug capability not available in the legacy debug 
registers (DR0–DR7). These MSRs allow single stepping and recording of control transfers to take place. The debug-extension registers perform the following functions:
DebugCtl Register.  This MSR register provides control over control-transfer recording and single 
stepping, and external-breakpoint reporting and trace messages.
LastBranch x and LastInt x Registers.  The four registers, LastBranchToIP, LastBranchFromIP, 
LastIntToIP, and LastIntFromIP, are all used to record the source and target of control transfers when branch recording is enabled.
Refer to Section 13.1.6 “Control-Transfer Breakpoint Features,” on page 408 for more information on 
using these debug registers.
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3.2.5  Performance-Monitoring Registers
The time-stamp counter and performance-monitoring registers are useful in identifying performance 
bottlenecks. The number of performance counters can vary based on the implementation. These registers perform the following functions:
TSC Register.  This register is used to count processor-clock cycles. It can be read using the RDMSR 
instruction, or it can be read using the either of the read time-stamp counter  instructions, RDTSC or 
RDTSCP. System software can make RDTSC or RDTSCP available for use by non-privileged software by clearing the time-stamp disable bit (CR4.TSD) to 0.
*PerfEvtSel n Registers.  These registers are used to specify the events counted by the corresponding 
performance counter, and to control other aspects of its operation.
*PerfCtr n Registers.  These registers are performance counters that hold a count of processor, 
northbridge, or L2 cache events or the duration of events, under the control of the corresponding *PerfEvtSel n register. Each *PerfCtr n register can be read using the RDMSR instruction, or they can 
be read using the read performance-monitor counter  instruction, RDPMC. System software can make 
RDPMC available for use by non-privileged software by setting the performance-monitor counter enable bit (CR4.PCE) to 1.
Refer to Section 13.2.3 “Using Performance Counters,” on page 421 for more information on using 
3.2.6  Machine-Check Registers
The machine-check registers control the detection and reporting of hardware machine-check errors. 
The types of errors that can be reported include cache-access errors, load-data and store-data errors, bus-parity errors, and ECC errors. Three types of machine-check MSRs are shown in Figure 3-10 on 
page 60.
The first type is global machine-check registers, which perform the following functions:
MCG_CAP Register.  This register identifies the machine-check capabilities supported by the 
processor.
MCG_CTL Register.  This register provides global control over machine-check-error reporting.
MCG_STATUS Register.  This register reports global status on detected machine-check errors.
The second type is error-reporting register banks, which report on machine-check errors associated 
with a specific processor unit (or group of processor units). There can be different numbers of register banks for each processor implementation, and each bank is numbered from 0 to i. The registers in each 
bank perform the following functions:
MCi_CTL Registers.  These registers control error-reporting.
MCi_STATUS Registers.  These registers report machine-check errors.
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MCi_ADDR Registers.  These registers report the machine-check error address.
MCi_MISC Registers.  These registers report miscellaneous-error information.
The third type is MCA Extension (MCAX) register banks, which report on machine-check errors 
associated with a specific processor unit (or group of processor units). There can be different numbers of register banks for each processor implementation, and each bank is numbered from 0 to i. Legacy MCA supports up to 32 banks. MCAX bank 0 will alias to Legacy bank 0 registers. Similarly, MCAX bank n will alias to Legacy bank n registers. The registers in each bank perform the following functions:
MCA_CTL Register.  This register is an alias to MCi_CTL for banks 0 to 31. For banks 32 and above, 
this register controls error-reporting.
MCA_STATUS Register.  This register is an alias to MCi_Status.
MCA_ADDR Register.  This register is an alias to MCi_ADDR.
MCA_MISC0 Register.  This register is an alias to MCi_MISC0.
MCA_CONFIG Register.  This register holds configuration information for the MCA bank.
MCA_IPID Register.  This register holds information which identifies the specific MCA bank.
MCA_SYND Register.  This register stores information associated with the error in MCA_STATUS 
or MCA_DESTAT.
MCA_DESTAT Register.  This register reports deferred machine check errors. 
MCA_DEADDR Register.  This register provides the address associated with the deferred machine 
check error.
MCA_MISC[4:1] Registers.  Extended miscellaneous error-information registers.
MCA_SYND[2:1] Registers.  This register contains information associated with the error in 
MCA_STATUS or MCA_DESTAT.
Refer to Section 9.5 “Using MCA Features,” on page 319 for more information on using these 
3.2.7  Shadow Stack Registers
These registers are defined if the shadow stack feature is supported as indicated by 
CPUID Fn0000_0007_0 ECX[CET_SS] (bit 7) = 1. 
PL0_SSP, PL1_SSP, PL2_SSP Registers.  These registers specify the linear address to be loaded 
into SSP on the next transition to CPLn, where n=0, 1, 2. The linear address must be in canonical format and aligned to 4 bytes.
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PL3_SSP Register.  The user mode SSP is saved to and restored from this register. The linear address 
must be in canonical format and aligned to 4 bytes.
ISST_ADDR Register.  This register specifies the linear address of the Interrupt SSP Table (ISST). 
The linear address must be in canonical format.
U_CET Register.  This register specifies the user mode shadow stack controls.
S_CET Register.  This register specifies the supervisor mode shadow stack controls.
3.2.8  Extended State Save MSRs 
XSS Register.  This register contains a bitmap of supervisor-level state components. System software 
sets bits in the XSS register bitmap to enable management of corresponding state component by the 
XSA VES/XRSTORS instructions.   XSS register support is indicated by CPUID Fn0000_000D_EAX[XSA VES]_x1 = 1.
The XSS bitmap is defined as follows: 
Figure 3-12. XSS Register
3.2.9  Speculation Control MSRs 
Modern processors implement hardware techniques such as branch prediction, speculative execution 
and out-of-order processing to significantly improve performance. If the processor incorrectly predicts or speculates on an outcome, this is detected and any speculative results are discarded. The processor then supplies the architecturally correct, in-order response to the program's instructions. Even though the speculative results are discarded, microarchitectural side effects may remain which can be detected by software, and which in some cases may lead to side-channel vulnerabilities.
The two speculation control MSRs, SPEC_CTRL (MSR 048h) and PRED_CMD (MSR 049h), enable 
hardware features that are designed to limit certain types of speculation. Support for these features is 63 32
Reserved
31 13 12 11 10 0
Reserved
CET_S
CET_UReserved
63:13 Reserved MBZ
12 CET_S Enables the CET_U state component. R/W
11 CET_U Enables the CET_S state component. R/W
10:0 Reserved  MBZ
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indicated by CPUID Fn8000_0008_EBX as described in Table 3-1 below. The presence of a given 
speculation control feature also implies support for its associated MSR.
See ‘Additional CPUID Functions’ at the end of this subsection and APM volume 3 Appendix E.4 
‘CPUID Fn8000_0008_EBX’ for more information on CPUID functions related to speculation control. 
SPEC_CTRL (MSR 048h)SPEC_CTRL (MSR 48h) is a read-write register. Attempts to write a 1 into any reserved bit cause a 
#GP(0) fault. Unlike most MSRs, a WRMSR to SPEC_CTRL does not serialize memory operations. However, a write to this register is dispatch serializing and prevents execution of younger instructions until the WRMSR has completed. The format of SPEC_CTRL is shown in Figure 3-12.
 
Figure 3-13. SPEC_CTRL Register (MSR 048h) 
The SPEC_CTRL bits defined in Figure 3-13 and are described below:
Indirect Branch Restricted Speculation (IBRS). Bit 0. Setting this bit to 1 prevents indirect 
branches that occurred in a less privileged prediction mode before this bit was set from influencing the 
predictions of future indirect branches in a more privileged prediction mode that occur after this bit is set. A lesser privileged prediction mode is defined as CPL 3 or Guest mode, and a more privileged prediction mode is defined as CPL 0-2 or Host mode.
After setting IBRS to 1, if software subsequentlyTable 3-1. Speculation Control MSRs  
Feature Indicated by CPUID Function MSR 
IBRS Fn8000_0008 EBX[14]=1 SPEC_CTRL (MSR 048h) 
STIBP Fn8000_0008 EBX[15]=1 SPEC_CTRL (MSR 048h) 
SSBD Fn8000_0008 EBX[24]=1 SPEC_CTRL (MSR 048h) 
PSFD Fn8000_0008 EBX[28]=1 SPEC_CTRL (MSR 048h) 
IBPB Fn8000_0008 EBX[12]=1 PRED_CMD (MSR 049h) 
31 8 7 6 3 2 1 0 
Reserved
PSFDReserved
SSBD
STIBP
IBRS
31:8 Reserved MBZ 
7 PSFD Predicted Store Forward Disable. R/W 
6:3 Reserved MBZ
2 SSBD Speculative Store Bypass Disable. R/W 
1 STIBP Single-Thread Indirect Branch Prediction Mode. R/W 
0 IBRS Indirect Branch Restricted Speculation. R/W 
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31 8 7 6 3 2 1 0 
Reserved
SSBD
STIBP
IBRS
•clears IBRS to 0: The processor may allow older indirect branches that occurred when IBRS was
previously 0 to influence future indirect branch predictions.
•writes another 1 to IBRS: The processor starts a new window where older indirect branches do notinfluence future indirect branch predictions.
Only indirect branches that occurred prior to setting IBRS are prevented from influencing future indirect branches. Therefore, if IBRS were already set on a transition to a more privileged mode from a lesser privileged mode, software at the more privileged mode must write a 1 to IBRS if it requires indirect branch predictions in the new mode to not be influenced by those from the previous mode.
On processors with a shared indirect branch predictor, setting IBRS also prevents indirect branch 
predictions of one thread from influencing the predictions of its sibling threads, as if SPEC_CTRL[STIBP] was also set. For more information on STIBP, see Single Thread Indirect Branch Predictor below.
Some processors, identified by CPUID Fn8000_0008_EBX[IbrsSameMode] (bit 19) = 1, provide 
additional speculation limits. For these processors, when IBRS is set, indirect branch predictions are not influenced by any prior indirect branches, regardless of mode (CPL and guest/host) and regardless of whether the prior indirect branches occurred before or after the setting of IBRS. This is referred to as Same Mode IBRS.
Although return instructions can be considered a type of indirect branch, IBRS does not affect them. 
Software requiring IBRS-style indirect branch speculation limits for RET instructions should clear out any return address predictions by executing 32 CALL instructions having a non-zero displacement. Processors implementing more than 32 return predictions include hardware to clear the additional entries when software writes a 1 to IBRS. If the kernel and user virtual address spaces are disjoint with at least one unmapped 4K page separating them, and SMEP is enabled, then there is no need to clear out the return address predictions.
Some processors, identified by CPUID Fn8000_0021_EAX[AutomaticIBRS] (bit 8) = 1, support 
Automatic IBRS. Refer to the description of EFER[AIBRSE] on page 58 for more details.
Single Thread Indirect Branch Prediction mode (STIBP). Bit 1. Setting this bit to 1 prevents 
indirect branch predictions of one thread from influencing the predictions of any sibling threads, on processors where branch prediction resources are shared. RET (return) instructions are not influenced by sibling threads. Therefore, setting STIBP is not required to prevent one thread’s RET predictions from influencing the predictions of a sibling thread.
Note that STIBP mode is automatically enabled when SPEC_CTRL[IBRS] is set, regardless of value 
of SPEC_CTRL[STIBP].
Speculative Store Bypass Disable (SSBD). Bit 2. Setting this bit to 1 prevents load-type instructions 
from speculatively bypassing older store instructions whose final address have not yet been resolved.As specified in Section 7.1.1 “Read Ordering,” on page 187, loads from memory marked with the 
proper memory type can read memory out-of-order, speculatively and before older stores have 
completed. This means it is possible for a load to read and pass forward, in a speculative manner, 
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previous values of the memory location. The processor has logic to correct this occurrence and provide 
the proper in-order load response to the program. However, this mis-speculation may have resulted in microarchitectural side effects. When SSBD is set to 1, the processor can return speculative load data only if there are no older stores with unknown addresses.
Some legacy processors implement SSBD in a different MSR. On these processors, indicated by 
CPUID function 8000_0008, EBX[25]=1, SSBD is enabled by setting VIRT_SPEC_CTRL (MSR C001_011F) bit 2. On processors that support both SPEC_CTRL and VIRT_SPEC_CTRL, if SSBD is enabled in either MSR, the processor prevents loads from speculating around older stores. However, it is preferred that software uses SPEC_CTRL[SSBD] in this scenario.
On some processor models, setting SSBD is not needed to prevent speculative loads from bypassing 
older stores. This is indicated by CPUID Fn8000_0008_EBX[SsbdNotRequired] (bit 26) = 1.
Predicted Store Forward Disable (PSFD).  Bit 7. Setting this bit disables Predictive Store 
Forwarding (PSF).
As specified in Section 7.1.1 “Read Ordering,” on page 187, write data for cacheable memory types 
can be forwarded to read instructions before that data is actually written to memory, via a mechanism 
called store-to-load forwarding. PSF expands on store-to-load forwarding via a mechanism that predicts the relationship between loads and stores based on past behavior, without waiting for their address calculations to complete. Like other forms of speculative store bypass, an incorrect prediction may result in microarchitectural side effects. PSF speculation can be disabled by setting PFSD.
The PSF feature is also disabled when SPEC_CTRL[SSBD] is set. However, SSBD disables both PSF 
and speculative store bypass, while PSFD only disables PSF. PSFD may be desirable for software which is concerned with the speculative behavior of PSF but desires a smaller performance impact than setting SSBD.
PRED_CMD (MSR 049h)PRED_CMD is a write-only register. Attempts to read this register or to write a 1 into any reserved bit 
cause a #GP(0) fault. Unlike most MSRs, a WRMSR to PRED_CMD does not serialize memory operations. However, a write to this register is dispatch serializing and prevents execution of younger instructions until the WRMSR has completed. The format of the PRED_CMD register is shown in Figure 3-13 below.
 
Figure 3-14. PRED_CMD Register (MSR 049h) 31 1 0 
Reserved
IBPB
31:1 Reserved MBZ
0 IBPB Indirect Branch Prediction Barrier. W 
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Indirect Branch Prediction Barrier (IBPB).  Bit 0, write only. Setting this bit to 1 prevents the 
processor from using older indirect branch predictions to influence future indirect branches. This 
applies to JMP indirect, CALL indirect and to RET (return) instructions. In some implementations, setting IBPB causes the processor to flush all previous indirect branch predictions. As this restricts the processor from using any previous indirect branch information, IBPB is intended to be used by software when switching between contexts that do not trust each other. Examples of such contexts include switching from one user context to another, or from one guest to another. In some implementations, IBPB will only flush the indirect predictions that are accessible to the current thread.
Additional CPUID FunctionsThe following CPUID functions provide more information on the speculation control features to aid 
system software in optimizing processor performance:
•CPUID Function 8000_0008_EBX[16] (IBRS always on). When set, indicates that the processor
prefers that IBRS is only set once during boot and not changed. If IBRS is set on a processorsupporting IBRS always on mode, indirect branches executed in a less privileged prediction modewill not influence branch predictions for indirect branches in a more privileged prediction mode.This eliminates the need for WRMSR instructions to manage speculation effects at elevated-privilege entry and exit points.
•CPUID Function 8000_0008_EBX[17] (STIBP always on). When set, indicates that the processorprefers that STIBP is only set once during boot and not changed. This eliminates the need for aWRMSR at the necessary transition points.
•CPUID Function 8000_0008_EBX[18] (IBRS preferred). When set, indicates that the processorprefers using the IBRS feature instead of other software mitigations such as retpoline. This allowssoftware to remove the software mitigation and utilize the more performant IBRS mechanism.
3.2.10  Hardware Configuration Register (HWCR)
The HWCR register contains control bits that affect the functionality of other features. Some HWCR 
bits are implementation specific, and are described in the BIOS and Kernel Developer’s Guide (BKDG) or Processor Programming Reference Manual applicable to your product. Implementation specific HWCR bits are not listed below. 
SmmLock.  Bit 0. Enables SMM code lock. When set to 1, SMM code in the ASeg and TSeg memory 
ranges, and the SMM registers, become read-only and SMI interrupts are not intercepted in SVM. See Section 15.32 “SMM-Lock,” on page 587 for information on using this feature. 
CpbDis.  Bit 25. Core performance boost disable. When set to 1, core performance boost is disabled. 
See Section 17.2 “Core Performance Boost,” on page 659 for further details on this feature. 
IRPerfEn.  Bit 30. Setting this bit to 1 enables the instructions retired counter. See Section 13.2.1 
“Performance Counter MSRs,” on page 410 for information on using this feature.
SmmPgCfgLock.  Bit 33. Setting this bit to 1 locks the paging configuration while in SMM. See

SmmPgCfgLock.  Bit 33. Setting this bit to 1 locks the paging configuration while in SMM. See 
Section 10.3.9 “SMM Page Configuration Lock,” on page 338 for information on using this feature. 
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CpuidUserDis.  Bit 35. Setting this bit to 1 causes #GP(0) when the CPUID instruction is executed by 
non-privileged software (CPL is > 0) outside SMM. Support for the CPUID User Disable feature is 
indicated by CPUID Fn80000021_EAX[CpuidUserDis]=1.
3.3 Processor Feature Identification
The CPUID instruction provides information about the processor implementation and its capabilities. 
Software operating at any privilege level can execute the CPUID instruction to collect this information. Software can utilize this information to optimize performance.
The CPUID instruction supports multiple functions, each providing specific information about the 
processor implementation, including the vendor, model number, revision (stepping), features, cache organization, and name. The multifunction approach allows the CPUID instruction to return a detailed picture of the processor implementation and its capabilities—more detailed information than could be 
returned by a single function. This flexibility also allows for the addition of new CPUID functions in future processor generations.
The desired function number is loaded into the EAX register before executing the CPUID instruction. 
CPUID functions are divided into two types:
•Standard functions  return information about features common to all x86 implementations,
including the earliest features offered in the x86 architecture, as well as information about the
presence of features such as support for the A VX and FMA instruction subsets. Standard functionnumbers are in the range 0000_0000h–0000_FFFFh.
•Extended functions  return information about AMD-specific features such as long mode and the
presence of features such as support for the FMA4 and XOP instruction subsets. Extended functionnumbers are in the range 8000_0000h–8000_FFFFh.
Feature information is returned in the EAX, EBX, ECX, and EDX registers. Some functions accept a second input parameter passed to the instruction in the ECX register. 
In this and the other three volumes of this Programmer’s Manual , the notation CPUID 
FnXXXX_XXXX_RRR[FieldName]_ xYY is used to represent the input parameters and return value that 
corresponds to a particular processor capability or feature.In this notation, XXXX_XXXX represents the 32-bit value to be placed in the EAX register prior to 
executing the CPUID instruction. This value is the function number. RRR is either EAX, EBX, ECX, 
or EDX and represents the register to be examined after the execution of the instruction. If the contents 
of the entire 32-bit register provides the capability information, the notation [FieldName] is omitted, 
otherwise this provides the name of the field within the return value that represents the capability or feature.
When the field is a single bit, this is called a feature flag. Normally, if a feature flag bit is set, the 
corresponding processor feature is supported and if it is cleared, the feature is not supported. The optional input parameter passed to the CPUID instruction in the ECX register is represented by the 
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notation _xYY appended after the return value notation. If a CPUID function does not accept this 
optional input parameter, this notation is omitted.
For more specific information on the CPUID instruction, see the instruction reference page in V olume 
3. For a description of all feature flags related to instruction subset support, see V olume 3, Appendix D, “Instruction Subsets and CPUID Feature Flags.” For a comprehensive list of all processor capabilities and feature flags, see V olume 3, Appendix E, “Obtaining Processor Information Via the CPUID Instruction.”
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4 Segmented Virtual Memory
The legacy x86 architecture supports a segment-translation mechanism that allows system software to 
relocate and isolate instructions and data anywhere in the virtual-memory space. A segment is a contiguous block of memory within the linear address space. The size and location of a segment within the linear address space is arbitrary. Instructions and data can be assigned to one or more memory segments, each with its own protection characteristics. The processor hardware enforces the rules dictating whether one segment can access another segment.
The segmentation mechanism provides ten segment registers, each of which defines a single segment. 
Six of these registers (CS, DS, ES, FS, GS, and SS) define user segments. User segments hold software, data, and the stack and can be used by both application software and system software. The remaining four segment registers (GDT, LDT, IDT, and TR) define system segments. System segments contain data structures initialized and used only by system software. Segment registers contain a base address  pointing to the starting location of a segment, a limit defining the segment size, 
and attributes  defining the segment-protection characteristics.
Although segmentation provides a great deal of flexibility in relocating and protecting software and data, it is often more efficient to handle memory isolation and relocation with a combination of software and hardware paging support. For this reason, most modern system software bypasses the segmentation features. However, segmentation cannot be completely disabled, and an understanding of the segmentation mechanism is important to implementing long-mode system software.
•64-bit mode, segmentation is disabled, creating a flat 64-bit virtual-address space. As will be seen,certain functions of some segment registers, particularly the system-segment registers, continue tobe used in 64-bit mode.
4.1 Real Mode Segmentation
After reset or power-up, the processor always initially enters real mode. Protected modes are entered from real mode.
As noted in “Real Addressing” on page 10, real mode (real-address mode), provides a physical-
memory space of 1 Mbyte. In this mode, a 20-bit physical address is determined by shifting a 16-bit 
segment selector to the left four bits and adding the 16-bit effective address. 
Each 64K segment (CS, DS, ES, FS, GS, SS) is aligned on 16-byte boundaries. The segment  base is 
the lowest address in a given segment, and is equal to the segment selector * 16. The POP and MOV 
instructions can be used to load a (possibly) new segment selector into one of the segment registers. 
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When this occurs, the selector is updated and the segment base is set to selector * 16. The segment 
limit and segment attributes are unchanged, but are normally 64K (the maximum allowable limit) and read/write data, respectively.
On FAR transfers, CS (code segment) selector is updated to the new value, and the CS segment base is 
set to selector * 16. The CS segment limit and attributes are unchanged, but are usually 64K and read/write, respectively.
If the interrupt descriptor table (IDT) is used to find the real mode IDT see “Real-Mode Interrupt 
Control Transfers” on page 267.
The GDT, LDT, and TSS (see below) are not used in real mode.
4.2 Virtual-8086 Mode Segmentation
Virtual-8086 mode supports 16-bit real mode programs running under protected mode (see below). It 
uses a simple form of memory segmentation, optional paging, and limited protection checking. Programs running in virtual-8086 mode can access up to 1MB of memory space.
As with real mode segmentation, each 64K segment (CS, DS, ES, FS, GS, SS) is aligned on 16-byte 
boundaries. The segment  base is the lowest address in a given segment, and is equal to the segment 
selector * 16. The POP and MOV instructions work exactly as in real mode and can be used to load a (possibly) new segment selector into one of the segment registers. When this occurs, the selector is updated and the segment base is set to selector * 16. The segment limit and segment attributes are unchanged, but are normally 64K (the maximum allowable limit) and read/write data, respectively.
FAR transfers, with the exception of interrupts and exceptions, operate as in real mode. On FAR 
transfers, the CS (code segment) selector is updated to the new value, and the CS segment base is set to selector * 16. The CS segment limit and attributes are unchanged, but are usually 64K and read/write, respectively. Interrupts and exceptions switch the processor to protected mode. (See Chapter 8, “Exceptions and Interrupts” for more information.)
4.3 Protected Mode Segmented-Memory Models

System software can use the segmentation mechanism to support one of two basic segmented-memory models: a flat-memory model or a multi-segmented model. These segmentation models are supported in legacy mode and in compatibility mode. Each type of model is described in the following sections.
4.3.1  Multi-Segmented Model
In the multi-segmented memory model, each segment register can reference a unique base address 
with a unique segment size. Segments can be as small as a single byte or as large as 4 Gbytes. When page translation is used, multiple segments can be mapped to a single page and multiple pages can be mapped to a single segment. Figure 1-1 on page 6 shows an example of the multi-segmented model. 
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The multi-segmented memory model provides the greatest level of flexibility for system software 
using the segmentation mechanism.
Compatibility mode allows the multi-segmented model to be used in support of legacy software. 
However, in compatibility mode, the multi-segmented memory model is restricted to the first 4 Gbytes of virtual-memory space. Access to virtual memory above 4 Gbytes requires the use of 64-bit mode, which does not support segmentation.
4.3.2  Flat-Memory Model
The flat-memory model is the simplest form of segmentation to implement. Although segmentation 
cannot be disabled, the flat-memory model allows system software to bypass most of the segmentation mechanism. In the flat-memory model, all segment-base addresses have a value of 0 and the segment limits are fixed at 4 Gbytes. Clearing the segment-base value to 0 effectively disables segment translation, resulting in a single segment spanning the entire virtual-address space. All segment descriptors reference this single, flat segment. Figure 1-2 on page 7 shows an example of the flat-
memory model.
4.3.3  Segmentation in 64-Bit Mode
In 64-bit mode, segmentation is disabled. The segment-base value is ignored and treated as 0 by the 
segmentation hardware. Likewise, segment limits and most attributes are ignored. There are a few exceptions. The CS-segment DPL, D, and L attributes are used (respectively) to establish the privilege level for a program, the default operand size, and whether the program is running in 64-bit mode or compatibility mode. The FS and GS segments can be used as additional base registers in address calculations, and those segments can have non-zero base-address values. This facilitates addressing thread-local data and certain system-software data structures. See “FS and GS Registers in 64-Bit Mode” on page 80 for details about the FS and GS segments in 64-bit mode. The system-segment registers are always used in 64-bit mode.
4.4 Segmentation Data Structures and Registers
Figure 4-1 on page 76 shows the following data structures used by the segmentation mechanism:
•Segment Descriptors —As the name implies, a segment descriptor describes  a segment, including
its location in virtual-address space, its size, protection characteristics, and other attributes.
•Descriptor Tables—Segment descriptors are stored in memory in one of three tables. The global-descriptor table (GDT) holds segment descriptors that can be shared among all tasks. Multiplelocal-descriptor tables (LDT) can be defined to hold descriptors that are used by specific tasks andare not shared globally. The interrupt-descriptor table (IDT) holds gate descriptors that are used toaccess the segments where interrupt handlers are located.
•Task-State Segment —A task-state segment (TSS) is a special type of system segment that contains
task-state information and data structures for each task. For example, a TSS holds a copy of theGPRs and EFLAGS register when a task is suspended. A TSS also holds the pointers to privileged-
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software stacks. The TSS and task-switch mechanism are described in Chapter 12, “Task
Management.”
•Segment Selectors —Descriptors are selected for use from the descriptor tables using a segment
selector. A segment selector contains an index into either the GDT or LDT. The IDT is indexedusing an interrupt vector, as described in “Legacy Protected-Mode Interrupt Control Transfers” onpage 269, and in “Long-Mode Interrupt Control Transfers” on page 280. 
Figure 4-1. Segmentation Data Structures
Figure 4-2 on page 77 shows the registers used by the segmentation mechanism. The registers have the 
following relationship to the data structures:
•Segment Registers —The six segment registers (CS, DS, ES, FS, GS, and SS) are used to point to
the user segments. A segment selector selects a descriptor when it is loaded into one of the segment
registers. This causes the processor to automatically load the selected descriptor into a software-invisible portion of the segment register.
•Descriptor-Table Registers —The three descriptor-table registers (GDTR, LDTR, and IDTR) are
used to point to the system segments. The descriptor-table registers identify the virtual-memorylocation and size of the descriptor tables.
•Task Register (TR) —Describes the location and limit of the current task state segment (TSS).513-263.epsSegment Descriptors
Code
Stack
Data
Gate
Local-Descriptor TableGlobal-Descriptor Table (GDT)
. . .
Local-Descriptor Table (LDT)
. . .
DescriptorSegment Selectors
Selector 1
Selector 2
. . .
Selector n
Interrupt-Descriptor Table (IDT)
. . .
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Figure 4-2. Segment and Descriptor-Table Registers
A fourth system-segment register, the TR, points to the TSS. The data structures and registers 
associated with task-state segments are described in “Task-Management Resources” on page 366.
4.5 Segment Selectors and Registers
4.5.1  Segment Selectors
Segment selectors are pointers to specific entries in the global and local descriptor tables. Figure 4-3 
shows the segment selector format.
Figure 4-3. Segment Selector15 3 2 1 0
SI TI RPL
Bits Mnemonic Description
15:3 SI Selector Index2 TI Table Indicator1:0 RPL Requestor Privilege Level513-264.epsDS
ES
FS
GSData Segment RegistersCSCode Segment Register
SSStack Segment RegisterIDTRInterrupt-Descriptor-Table RegisterGDTRGlobal-Descriptor-Table Register
LDTRLocal-Descriptor-Table Register
TRTask Register
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The selector format consists of the following fields:
Selector Index Field.  Bits 15:3. The selector-index field specifies an entry in the descriptor table. 
Descriptor-table entries are eight bytes long, so the selector index is scaled by 8 to form a byte offset 
into the descriptor table. The offset is then added to either the global or local descriptor-table base address (as indicated by the table-index bit) to form the descriptor-entry address in virtual-address space.
Some descriptor entries in long mode are 16 bytes long rather than 8 bytes (see “Legacy Segment 
Descriptors” on page 88 for more information on long-mode descriptor-table entries). These expanded 
descriptors consume two entries in the descriptor table. Long mode, however, continues to scale the selector index by eight to form the descriptor-table offset. It is the responsibility of system software to assign selectors such that they correctly point to the start of an expanded entry.
Table Indicator (TI) Bit.  Bit 2. The TI bit indicates which table holds the descriptor referenced by the 
selector index. When TI=0 the GDT is used and when TI=1 the LDT is used. The descriptor-table base address is read from the appropriate descriptor-table register and added to the scaled selector index as described above.
Requestor Privilege-Level (RPL) Field.  Bits 1:0. The RPL represents the privilege level (CPL) the 
processor is operating under at the time the selector is created.
RPL is used in segment privilege-checks to prevent software running at lesser privilege levels from 
accessing privileged data. See “Data-Access Privilege Checks” on page 106 and “Control-Transfer Privilege Checks” on page 109 for more information on segment privilege-checks.
Null Selector.  Null selectors have a selector index of 0 and TI=0, corresponding to the first entry in 
the GDT. However, null selectors do not reference the first GDT entry but are instead used to invalidate unused segment registers. A general-protection exception (#GP) occurs if a reference is made to use a segment register containing a null selector in non-64-bit mode. By initializing unused segment registers with null selectors software can trap references to unused segments.
Null selectors can only be loaded into the DS, ES, FS and GS data-segment registers, and into the

Null selectors can only be loaded into the DS, ES, FS and GS data-segment registers, and into the 
LDTR descriptor-table register. A #GP occurs if software attempts to load the CS register with a null selector or if software attempts to load the SS register with a null selector in non 64-bit mode or at CPL 3. 
If CPUID Fn8000_0021_EAX[NullSelectorClearsBase] (bit 6) = 1, loading a segment register with a 
null selector clears the base address and limit of the segment register in all cases except a load of DS, ES, FS, or GS by an IRET, IRETD, IRETQ, or RETF instruction that changes the current privilege level, in which case these fields are left untouched. If CPUID Fn8000_0021_EAX[NullSelectorClearsBase] (bit 6) = 0, loading a segment register with a null selector makes the base address and limit of the segment register undefined. Because references to segment registers containing a null selector cause a #GP exception, the segment base and limit values have no effect. However, OS management of segment state may be simplified for processors supporting this clearing functionality. 
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4.5.2  Segment Registers
Six 16-bit segment registers are provided for referencing up to six segments at one time. All software 
tasks require segment selectors to be loaded in the CS and SS registers. Use of the DS, ES, FS, and GS segments is optional, but nearly all software accesses data and therefore requires a selector in the DS register. Table 4-1 on page 79 lists the supported segment registers and their functions.
The processor maintains a hidden portion  of the segment register in addition to the selector value 
loaded by software. This hidden portion contains the values found in the descriptor-table entry referenced by the segment selector. The processor loads the descriptor-table entry into the hidden portion when the segment register is loaded. By keeping the corresponding descriptor-table entry in hardware, performance is optimized for the majority of memory references.
Figure 4-4 shows the format of the visible and hidden portions of the segment register. Except for the 
FS and GS segment base, software cannot directly read or write the hidden portion (shown as gray-shaded boxes in Figure 4-4).
Figure 4-4. Segment-Register Format
CS Register.  The CS register contains the segment selector referencing the current code-segment 
descriptor entry. All instruction fetches reference the CS descriptor. When a new selector is loaded into the CS register, the current-privilege level (CPL) of the processor is set to that of the CS-segment descriptor-privilege level (DPL). Table 4-1. Segment Registers
Segment
RegisterEncoding Segment Register Function
ES /0 References optional data-segment descriptor entry
CS /1 References code-segment descriptor entry
SS /2 References stack segment descriptor entry
DS /3 References default data-segment descriptor entry
FS /4 References optional data-segment descriptor entry
GS /5 References optional data-segment descriptor entry
Hidden From Software513-221.eps32-Bit Segment Limit
32-Bit Segment Base AddressSegment AttributesSelector
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Data-Segment Registers.  The DS register contains the segment selector referencing the default 
data-segment descriptor entry. The SS register contains the stack-segment selector. The ES, FS, and 
GS registers are optionally loaded with segment selectors referencing other data segments. Data accesses default to referencing the DS descriptor except in the following two cases:
•The ES descriptor is referenced for string-instruction destinations.
•The SS descriptor is referenced for stack operations.
4.5.3  Segment Registers in 64-Bit Mode
CS Register in 64-Bit Mode.  In 64-bit mode, most of the hidden portion of the CS register is 
ignored. Only the L (long), D (default operation size), and DPL (descriptor privilege-level) attributes 
are recognized by 64-bit mode. Address calculations assume a CS.base value of 0. CS references do not check the CS.limit value, but instead check that the effective address is in canonical form.
DS, ES, and SS Registers in 64-Bit Mode.  In 64-bit mode, the contents of the ES, DS, and SS 
segment registers are ignored. All fields (base, limit, and attribute) in the hidden portion of the segment registers are ignored. 
Address calculations in 64-bit mode that reference the ES, DS, or SS segments are treated as if the 
segment base is 0. Instead of performing limit checks, the processor checks that all virtual-address references are in canonical form.
Neither enabling and activating long mode nor switching between 64-bit and compatibility modes 
changes the contents of the visible or hidden portions of the segment registers. These registers remain unchanged during 64-bit mode execution unless explicit segment loads are performed.
FS and GS Registers in 64-Bit Mode.  Unlike the CS, DS, ES, and SS segments, the FS and GS 
segment overrides can be used in 64-bit mode. When FS and GS segment overrides are used in 64-bit mode, their respective base addresses are used in the effective-address (EA) calculation. The complete EA calculation then becomes (FS or GS).base  base  (scale  index)  displacement. The FS.base 
and GS.base values are also expanded to the full 64-bit virtual-address size, as shown in Figure 4-5. Any overflow in the 64-bit linear address calculation is ignored and the resulting address instead wraps around to the other end of the address space.
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Figure 4-5. FS and GS Segment-Register Format—64-Bit Mode
In 64-bit mode, FS-segment and GS-segment overrides are not checked for limit or attributes. Instead, 
the processor checks that all virtual-address references are in canonical form.
Segment register-load instructions (MOV to Sreg and POP Sreg) load only a 32-bit base-address value 
into the hidden portion of the FS and GS segment registers. The base-address bits above the low 32 bits are cleared to 0 as a result of a segment-register load. When a null selector is loaded into FS or GS, the contents of the corresponding hidden descriptor register are not altered.
There are two methods to update the contents of the FS.base and GS.base hidden descriptor fields. The 
first is available exclusively to privileged software (CPL = 0). The FS.base and GS.base hidden descriptor-register fields are mapped to MSRs. Privileged software can load a 64-bit base address in canonical form into FS.base or GS.base using a single WRMSR instruction. The FS.base MSR address is C000_0100h while the GS.base MSR address is C000_0101h. 
The second method of updating the FS and GS base fields is available to software running at any 
privilege level (when supported by the implementation and enabled by setting CR4[FSGSBASE]). The WRFSBASE and WRGSBASE instructions copy the contents of a GPR to the FS.base and GS.base fields respectively. When the operand size is 32 bits, the upper doubleword of the base is cleared. WRFSBASE and WRGSBASE are only supported in 64-bit mode.
The addresses written into the expanded FS.base and GS.base registers must be in canonical form. Any 
instruction that attempts to write a non-canonical address to these registers causes a general-protection exception (#GP) to occur.
When in compatibility mode, the FS and GS overrides operate as defined by the legacy x86 
architecture regardless of the value loaded into the high 32 bits of the hidden descriptor-register base-address field. Compatibility mode ignores the high 32 bits when calculating an effective address.Hidden from Software and Unused in 64-bit Mode513-267.eps64-Bit Segment Base Address32-Bit  Segment LimitSegment AttributesSelector
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4.6 Descriptor Tables
Descriptor tables are used by the segmentation mechanism when protected mode is enabled 
(CR0.PE=1). These tables hold descriptor entries that describe the location, size, and privilege attributes of a segment. All memory references in protected mode access a descriptor-table entry.
As previously mentioned, there are three types of descriptor tables supported by the x86 segmentation 
mechanism:
•Global descriptor table (GDT)
•Local descriptor table (LDT)
•Interrupt descriptor table (IDT)
Software establishes the location of a descriptor table in memory by initializing its corresponding 
descriptor-table register. The descriptor-table registers and the descriptor tables are described in the following sections.
4.6.1  Global Descriptor Table
Protected-mode system software must create a global descriptor table (GDT). The GDT contains code-

segment and data-segment descriptor entries (user segments) for segments that can be shared by all tasks. In addition to the user segments, the GDT can also hold gate descriptors and other system-segment descriptors. System software can store the GDT anywhere in memory and should protect the segment containing the GDT from non-privileged software.
Segment selectors point to the GDT when the table-index (TI) bit in the selector is cleared to 0. The 
selector index portion of the segment selector references a specific entry in the GDT. Figure 4-6 on 
page 83 shows how the segment selector indexes into the GDT. One special form of a segment selector is the null selector. A null selector points to the first entry in the GDT (the selector index is 0 and 
TI=0). However, null selectors do not reference memory, so the first GDT entry cannot be used to describe a segment (see “Null Selector” on page 78 for information on using the null selector). The first usable GDT entry is referenced with a selector index of 1.
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Figure 4-6. Global and Local Descriptor-Table Access
4.6.2  Global Descriptor-Table Register
The global descriptor-table register (GDTR) points to the location of the GDT in memory and defines 
its size. This register is loaded from memory using the LGDT instruction (see “LGDT and LIDT Instructions” on page 179). Figure 4-7 shows the format of the GDTR in legacy mode and compatibility mode.
Figure 4-7. GDTR and IDTR Format—Legacy Modes
Figure 4-8 on page 84 shows the format of the GDTR in 64-bit mode.513-209.epsDescriptor Table Base Address Descriptor Table LimitGlobal (TI=0)
Local (TI=1)
Descriptor Table
++
Global or Local Descriptor-Table RegisterSelector Index 000Selector IndexTI Segment Selector
Unused in GDT
513-220.eps16-Bit Descriptor-Table Limit
32-Bit Descriptor-Table Base Address
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Figure 4-8. GDTR and IDTR Format—Long Mode
The GDTR contains two fields:
Limit.  2 bytes. These bits define the 16-bit limit, or size, of the GDT in bytes. The limit value is added 
to the base address to yield the ending byte address of the GDT. A general-protection exception (#GP) 
occurs if software attempts to access a descriptor beyond the GDT limit.
The offsets into the descriptor tables are not extended by the AMD64 architecture in support of long 
mode. Therefore, the GDTR and IDTR limit-field sizes are unchanged from the legacy sizes. The processor does check the limits in long mode during GDT and IDT accesses.
Base Address.  8 bytes. The base-address field holds the starting byte address of the GDT in virtual-
memory space. The GDT can be located at any byte address in virtual memory, but system software should align the GDT on a quadword boundary to avoid the potential performance penalties associated with accessing unaligned data. 
The AMD64 architecture increases the base-address field of the GDTR to 64 bits so that system 
software running in long mode can locate the GDT anywhere in the 64-bit virtual-address space. The processor ignores the high-order 4 bytes of base address when running in legacy mode.
4.6.3  Local Descriptor Table
Protected-mode system software can optionally create a local descriptor table  (LDT) to hold segment 
descriptors belonging to a single task or even multiple tasks. The LDT typically contains code-
segment and data-segment descriptors as well as gate descriptors referenced by the specified task. Like the GDT, system software can store the LDT anywhere in memory and should protect the segment containing the LDT from non-privileged software.
Segment selectors point to the LDT when the table-index bit (TI) in the selector is set to 1. The selector 
index portion of the segment selector references a specific entry in the LDT (see Figure 4-6 on 
page 83). Unlike the GDT, however, a selector index of 0 references the first entry in the LDT (when TI=1, the selector is not a null selector).
LDTs are described by system-segment descriptor entries located in the GDT, and a GDT can contain 
multiple LDT descriptors. The LDT system-segment descriptor defines the location, size, and privilege rights for the LDT. Figure 4-9 on page 85 shows the relationship between the LDT and GDT 
data structures.513-266.eps16-Bit Descriptor-Table Limit
64-Bit Descriptor-Table Base Address
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Loading a null selector into the LDTR is useful if software does not use an LDT. This causes a #GP if 
an erroneous reference is made to the LDT.
Figure 4-9. Relationship between the LDT and GDT
4.6.4  Local Descriptor-Table Register
The local descriptor-table register (LDTR) points to the location of the LDT in memory, defines its 
size, and specifies its attributes. The LDTR has two portions. A visible  portion holds the LDT selector, 
and a hidden  portion holds the LDT descriptor. When the LDT selector is loaded into the LDTR, the 
processor automatically loads the LDT descriptor from the GDT into the hidden portion of the LDTR. The LDTR is loaded in one of two ways:
•Using the LLDT instruction (see “LLDT and LTR Instructions” on page 180).
•Performing a task switch (see “Switching Tasks” on page 379).
Figure 4-10 on page 86 shows the format of the LDTR in legacy mode.513-208.epsGlobal
Table
GDT Limit
GDT Base AddressLDT Selector
LDT Attributes
LDT Limit
LDT Base AddressLocal
Table
Global Descriptor Table Register Local Descriptor Table Register
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Figure 4-10. LDTR Format—Legacy Mode
Figure 4-11 shows the format of the LDTR in long mode (both compatibility mode and 64-bit mode).
Figure 4-11. LDTR Format—Long Mode
The LDTR contains four fields:
LDT Selector.  2 bytes. These bits are loaded explicitly from the TSS during a task switch, or by using 
the LLDT instruction. The LDT selector must point to an LDT system-segment descriptor entry in the 
GDT. If it does not, a general-protection exception (#GP) occurs.
The following three fields are loaded automatically from the LDT descriptor in the GDT as a result of 
loading the LDT selector. The register fields are shown as shaded boxes in Figure 4-10 and Figure 4-11.
Base Address.  The base-address field holds the starting byte address of the LDT in virtual-memory 
space. Like the GDT, the LDT can be located anywhere in system memory, but software should align the LDT on a quadword boundary to avoid performance penalties associated with accessing unaligned data.Hidden From Software513-221.eps32-Bit Descriptor-Table Limit
32-Bit Descriptor-Table Base AddressDescriptor AttributesSelector
Hidden From Software513-267.eps64-Bit Descriptor-Table Base Address32-Bit Descriptor-Table LimitDescriptor AttributesSelector
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The AMD64 architecture expands the base-address field of the LDTR to 64 bits so that system 
software running in long mode can locate an LDT anywhere in the 64-bit virtual-address space. The processor ignores the high-order 32 base-address bits when running in legacy mode. Because the LDTR is loaded from the GDT, the system-segment descriptor format (LDTs are system segments) has been expanded by the AMD64 architecture in support of 64-bit mode. See “Long Mode Descriptor 
Summary” on page 103 for more information on this expanded format. The high-order base-address bits are only loaded from 64-bit mode using the LLDT instruction (see “LLDT and LTR Instructions” on page 180 for more information on this instruction).
Limit.  This field defines the limit, or size, of the LDT in bytes. The LDT limit as stored in the LDTR 
is 32 bits. When the LDT limit is loaded from the GDT descriptor entry, the 20-bit limit field in the descriptor is expanded to 32 bits and scaled based on the value of the descriptor granularity (G) bit. For details on the limit biasing and granularity, see “Granularity (G) Bit” on page 90. 
If an attempt is made to access a descriptor beyond the LDT limit, a general-protection exception (#GP) occurs.
mode. Therefore, the LDTR limit-field size is unchanged from the legacy size. The processor does check the LDT limit in long mode during LDT accesses.
Attributes.  This field holds the descriptor attributes, such as privilege rights, segment presence and 
segment granularity.
4.6.5  Interrupt Descriptor Table
The final type of descriptor table is the interrupt descriptor table (IDT). Multiple IDTs can be 
maintained by system software. System software selects a specific IDT by loading the interrupt

maintained by system software. System software selects a specific IDT by loading the interrupt 
descriptor table register (IDTR) with a pointer to the IDT. As with the GDT and LDT, system software can store the IDT anywhere in memory and should protect the segment containing the IDT from non-privileged software. 
The IDT can contain only the following types of gate descriptors:
•Interrupt gates
•Trap gates
•Task gates.
The use of gate descriptors by the interrupt mechanism is described in Chapter 8, “Exceptions and 
Interrupts.” A general-protection exception (#GP) occurs if the IDT descriptor referenced by an interrupt or exception is not one of the types listed above.
IDT entries are selected using the interrupt vector number rather than a selector value. The interrupt 
vector number is scaled by the interrupt-descriptor entry size to form an offset into the IDT. The interrupt-descriptor entry size depends on the processor operating mode as follows:
•In long mode, interrupt descriptor-table entries are 16 bytes.
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•In legacy mode, interrupt descriptor-table entries are eight bytes.
Figure 4-12 shows how the interrupt vector number indexes the IDT.
Figure 4-12. Indexing an IDT
4.6.6  Interrupt Descriptor-Table Register
The interrupt descriptor-table register (IDTR) points to the IDT in memory and defines its size. This 
register is loaded from memory using the LIDT instruction (see “LGDT and LIDT Instructions” on page 179). The format of the IDTR is identical to that of the GDTR in all modes. Figure 4-7 on page 83 shows the format of the IDTR in legacy mode. Figure 4-8 on page 84 shows the format of the 
IDTR in long mode.
mode. Therefore, the IDTR limit-field size is unchanged from the legacy size. The processor does check the IDT limit in long mode during IDT accesses.
4.7 Legacy Segment Descriptors
4.7.1  Descriptor Format
Segment descriptors define, protect, and isolate segments from each other. There are two basic types of 
descriptors, each of which are used to describe different segment (or gate) types:
•User Segments—These include code segments and data segments. Stack segments are a type of
data segment.513-207.epsIDT Base Address IDT LimitInterrupt
*Interrupt Vector
Descriptor Entry
Size++
Interrupt Descriptor Table Register
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•System Segments —System segments consist of LDT segments and task-state segments (TSS).
Gate descriptors are another type of system-segment descriptor. Rather than describing segments,
gate descriptors point to program entry points.
Figure 4-13 shows the generic format for user-segment and system-segment descriptors. User and system segments are differentiated using the S bit. S=1 indicates a user segment, and S=0 indicates a system segment. Gray shading indicates the field or bit is reserved. The format for a gate descriptor differs from the generic segment descriptor, and is described separately in “Gate Descriptors” on page 95.
Figure 4-13. Generic Segment Descriptor—Legacy Mode
Figure 4-13 shows the fields in a generic, legacy-mode, 8-byte (two doubleword) segment descriptor. In this figure, the upper doubleword (located at byte offset +4) is shown on top and the lower doubleword (located at byte offset +0) is shown on the bottom. The fields are defined as follows:
Segment Limit.  The 20-bit segment limit is formed by concatenating bits 19:16 of the upper 
doubleword with bits 15:0 of lower doubleword. The segment limit defines the segment size, in bytes. The granularity (G) bit controls how the segment-limit field is scaled (see “Granularity (G) Bit” on 
page 90). For data segments, the expand-down (E) bit determines whether the segment limit defines the lower or upper segment-boundary (see “Expand-Down (E) Bit” on page 93).
If software references a segment descriptor with an address beyond the segment limit, a general-
protection exception (#GP) occurs. The #GP occurs if any part of the memory reference falls outside the segment limit. For example, a doubleword (4 -byte) address reference causes a #GP if one or more 
bytes are located beyond the segment limit.
Base Address.  The 32-bit base address is formed by concatenating bits 31:24 of the upper 
doubleword with bits 7:0 of the same doubleword and bits 15:0 of the lower doubleword. The segment-base address field locates the start of a segment in virtual-address space.31 24 23 22 21 20 19 16 15 14 13 12 11 8 7 0
Base Address[31:24]
G
D/B
A VLSegment Limit 
[19:16]
PDPL
S Type Base Address[23:16] +4
Base Address[15:0] Segment Limit[15:0] +0
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S Bit and Type Field.  Bit 12 and bits 11:8 of the upper doubleword. The S and Type fields, together, 
specify the descriptor type and its access characteristics. Table 4-2 summarizes the descriptor types by 
S-field encoding and gives a cross reference to descriptions of the Type-field encodings.
Descriptor Privilege-Level (DPL) Field.  Bits 14:13 of the upper doubleword. The DPL field 
indicates the descriptor-privilege level of the segment. DPL can be set to any value from 0 to 3, with 0 specifying the most privilege and 3 the least privilege. See “Data-Access Privilege Checks” on page 106 and “Control-Transfer Privilege Checks” on page 109 for more information on how the DPL is used during segment privilege-checks.
Present (P) Bit.  Bit 15 of the upper doubleword. The segment-present bit indicates that the segment 
referenced by the descriptor is loaded in memory. If a reference is made to a descriptor entry when P = 0, a segment-not-present exception (#NP) occurs. This bit is set and cleared by system software 
and is never altered by the processor.
Available To Software (AVL) Bit.  Bit 20 of the upper doubleword. This field is available to software, 
which can write any value to it. The processor does not set or clear this field.
Default Operand Size (D/B) Bit.  Bit 22 of the upper doubleword. The default operand-size bit is 
found in code-segment and data-segment descriptors but not in system-segment descriptors. Setting this bit to 1 indicates a 32-bit default operand size, and clearing it to 0 indicates a 16-bit default size. The effect this bit has on a segment depends on the segment-descriptor type. See “Code-Segment Default-Operand Size (D) Bit” on page 92 for a description of the D bit in code-segment descriptors. “Data-Segment Default Operand Size (D/B) Bit” on page 94 describes the D bit in data-segment descriptors, including stack segments, where the bit is referred to as the “B” bit.
Granularity (G) Bit.  Bit 23 of the upper doubleword. The granularity bit specifies how the segment-
limit field is scaled. Clearing the G bit to 0 indicates that the limit field is not scaled. In this case, the limit equals the number of bytes available in the segment. Setting the G bit to 1 indicates that the limit field is scaled by 4 Kbytes (4096 bytes). Here, the limit field equals the number of 4-Kbyte  blocks 
available in the segment.
Setting a limit of 0 indicates a 1-byte segment limit when G = 0. Setting the same limit of 0 when G = 
1 indicates a segment limit of 4095.Table 4-2. Descriptor Types
S FieldDescriptor 
TypeType-Field Encoding
0 (System)LDT
See Table 4-5 on page 94 TSS
Gate
1 (User)Code See Table 4-3 on page 92
Data See Table 4-4 on page 93
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Reserved Bits.  Generally, software should clear all reserved bits to 0, so they can be defined in future 
revisions to the AMD64 architecture.
4.7.2  Code-Segment Descriptors
Figure 4-14 shows the code-segment descriptor format (gray shading indicates the bit is reserved). All 
software tasks require that a segment selector, referencing a valid code-segment descriptor, is loaded into the CS register. Code segments establish the processor operating mode and execution privilege-level. The segments generally contain only instructions and are execute-only, or execute and read-only. Software cannot write into a segment whose selector references a code-segment descriptor.
Figure 4-14. Code-Segment Descriptor—Legacy Mode
Code-segment descriptors have the S bit set to 1, identifying the segments as user segments. Type-field bit 11 differentiates code-segment descriptors (bit 11 set to 1) from data-segment descriptors (bit 11 cleared to 0). The remaining type-field bits (10:8) define the access characteristics for the code-segment, as follows:
Conforming (C) Bit.  Bit 10 of the upper doubleword. Setting this bit to 1 identifies the code segment 
as conforming . When control is transferred to a higher-privilege conforming code-segment (C=1) from 
a lower-privilege code segment, the processor CPL does not change. Transfers to non-conforming code-segments (C = 0) with a higher privilege-level than the CPL can occur only through gate 
descriptors. See “Control-Transfer Privilege Checks” on page 109 for more information on 
conforming and non-conforming code-segments.
Readable (R) Bit.  Bit 9 of the upper doubleword. Setting this bit to 1 indicates the code segment is

Readable (R) Bit.  Bit 9 of the upper doubleword. Setting this bit to 1 indicates the code segment is 
both executable and readable as data. When this bit is cleared to 0, the code segment is executable, but attempts to read data from the code segment cause a general-protection exception (#GP) to occur.
Accessed (A) Bit.  Bit 8 of the upper doubleword. The accessed bit is set to 1 by the processor when 
the descriptor is copied from the GDT or LDT into the CS register. This bit is only cleared by software.
Table 4-3 on page 92 summarizes the code-segment type-field encodings.31 24 23 22 21 20 19 16 15 14 13 12 11 10 9 8 7 0
G
D
A VLSegment 
Limit[19:16]
PDPL
11
CR
ABase Address[23:16] +4
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Code-Segment Default-Operand Size (D) Bit.  Bit 22 of byte +4. In code-segment descriptors, the 
D bit selects the default operand size and address sizes. In legacy mode, when D=0 the default operand 
size and address size is 16 bits and when D=1 the default operand size and address size is 32 bits. Instruction prefixes can be used to override the operand size or address size, or both.
4.7.3  Data-Segment Descriptors
Figure 4-15 shows the data-segment descriptor format. Data segments contain non-executable 
information and can be accessed as read-only or read/write. They are referenced using the DS, ES, FS, GS, or SS data-segment registers. The DS data-segment register holds the segment selector for the default data segment. The ES, FS and GS data-segment registers hold segment selectors for additional data segments usable by the current software task. 
The stack segment is a special form of data-segment register. It is referenced using the SS segment 
register and must be read/write. When loading the SS register, the processor requires that the selector reference a valid, writable data-segment descriptor.
Figure 4-15. Data-Segment Descriptor—Legacy ModeTable 4-3. Code-Segment Descriptor Types
Hex
ValueType Field
Description Bit 11
(Code/Data)Bit 10 Bit 9 Bit 8
Conforming
(C)Readable
(R)Accessed
(A)
8
10 0 0 Execute-Only
9 0 0 1 Execute-Only — Accessed
A 0 1 0 Execute/Readable
B 0 1 1 Execute/Readable — Accessed
C 1 0 0 Conforming, Execute-Only
D 1 0 1 Conforming, Execute-Only — Accessed
E 1 1 0 Conforming, Execute/Readable
F 1 1 1Conforming, Execute/Readable — 
Accessed
31 24 23 22 21 20 19 16 15 14 13 12 11 10 9 8 7 0
G
D/B
[19:16]
PDPL
1
0
E
W
A Base Address[23:16] +4
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Data-segment descriptors have the S bit set to 1, identifying them as user segments. Type-field bit 11 
differentiates data-segment descriptors (bit 11 cleared to 0) from code-segment descriptors (bit 11 set to 1). The remaining type-field bits (10:8) define the data-segment access characteristics, as follows:
Expand-Down (E) Bit.  Bit 10 of the upper doubleword. Setting this bit to 1 identifies the data 
segment as expand-down. In expand-down segments, the segment limit defines the lower  segment 
boundary while the base is the upper boundary. Valid segment offsets in expand-down segments lie in the byte range limit+1 to FFFFh or FFFF_FFFFh, depending on the value of the data segment default operand size (D/B) bit. 
Expand-down segments are useful for stacks, which grow in the downward direction as elements are 
pushed onto the stack. The stack pointer, ESP, is decremented  by an amount equal to the operand size 
as a result of executing a PUSH instruction.
Clearing the E bit to 0 identifies the data segment as expand-up. Valid segment offsets in expand-up 
segments lie in the byte range 0 to segment limit.
Writable (W) Bit.  Bit 9 of the upper doubleword. Setting this bit to 1 identifies the data segment as 
read/write. When this bit is cleared to 0, the segment is read-only. A general-protection exception (#GP) occurs if software attempts to write into a data segment when W=0.
the descriptor is copied from the GDT or LDT into one of the data-segment registers or the stack-segment register. This bit is only cleared by software.
Table 4-4 summarizes the data-segment type-field encodings.
Table 4-4. Data-Segment Descriptor Types
Hex
Expand-
Down
(E)Writable
(W)Accessed
(A)
0
00 0 0 Read-Only
1 0 0 1 Read-Only — Accessed
2 0 1 0 Read/Write
3 0 1 1 Read/Write — Accessed
4 1 0 0 Expand-down, Read-Only
5 1 0 1 Expand-down, Read-Only — Accessed
6 1 1 0 Expand-down, Read/Write
7 1 1 1 Expand-down, Read/Write — Accessed
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Data-Segment Default Operand Size (D/B) Bit.  Bit 22 of the upper doubleword. For expand-down 
data segments (E=1), setting D=1 sets the upper bound of the segment at 0_FFFF_FFFFh. Clearing 
D=0 sets the upper bound of the segment at 0_FFFFh.
In the case where a data segment is referenced by the stack selector (SS), the D bit is referred to as the 
B bit. For stack segments, the B bit sets the default stack size. Setting B=1 establishes a 32-bit stack referenced by the 32-bit ESP register. Clearing B=0 establishes a 16-bit stack referenced by the 16-bit SP register.
4.7.4  System Descriptors
There are two general types of system descriptors: system-segment descriptors and gate descriptors. 
System-segment descriptors are used to describe the LDT and TSS segments. Gate descriptors do not describe segments, but instead hold pointers to code-segment descriptors. Gate descriptors are used for protected-mode control transfers between less-privileged and more-privileged software.
System-segment descriptors have the S bit cleared to 0. The type field is used to differentiate the 
various LDT, TSS, and gate descriptors from one another. Table 4-5 summarizes the system-segment type-field encodings.
Table 4-5. System-Segment Descriptor Types (S=0)—Legacy Mode
Hex
ValueType Field 
(Bits 11:8)Description
0 0000 Reserved (Illegal)
1 0001 Available 16-bit TSS
2 0010 LDT
3 0011 Busy 16-bit TSS
4 0100 16-bit Call Gate
5 0101 Task Gate
6 0110 16-bit Interrupt Gate
7 0111 16-bit Trap Gate
8 1000 Reserved (Illegal)
9 1001 Available 32-bit TSS
A 1010 Reserved (Illegal)
B 1011 Busy 32-bit TSS
C 1100 32-bit Call Gate
D 1101 Reserved (Illegal)
E 1110 32-bit Interrupt Gate
F 1111 32-bit Trap Gate
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Figure 4-16 shows the legacy-mode system-segment descriptor format used for referencing LDT and 
TSS segments (gray shading indicates the bit is reserved). This format is also used in compatibility mode. The system-segments are used as follows:
•The LDT typically holds segment descriptors belonging to a single task (see “Local Descriptor
Table” on page 84). 
•The TSS is a data structure for holding processor-state information. Processor state is saved in aTSS when a task is suspended, and state is restored from the TSS when a task is restarted. Systemsoftware must create at least one TSS referenced by the task register, TR. See “Legacy Task-StateSegment” on page 371 for more information on the TSS.
Figure 4-16. LDT and TSS Descriptor—Legacy/Compatibility Modes
4.7.5  Gate Descriptors
Gate descriptors hold pointers to code segments and are used to control access between code segments 
with different privilege levels. There are four types of gate descriptors:
•Call Gates—These gates (Figure 4-17 on page 96) are located in the GDT or LDT and are used to
control access between code segments in the same task or in different tasks. See “Control Transfers
Through Call Gates” on page 113 for information on how call gates are used to control accessbetween code segments operating in the same task. The format of a call-gate descriptor is shown inFigure 4-17 on page 96.
•Interrupt Gates and Trap Gates—These gates (Figure 4-18 on page 96) are located in the IDT and
are used to control access to interrupt-service routines. “Legacy Protected-Mode Interrupt ControlTransfers” on page 269 contains information on using these gates for interrupt-control transfers.
The format of interrupt-gate and trap-gate descriptors is shown in Figure 4-17 on page 96.
•Task Gates—These gates (Figure 4-19 on page 96) are used to control access between different
tasks. They are also used to transfer control to interrupt-service routines if those routines arethemselves a separate task. See “Task-Management Resources” on page 366 for more information
on task gates and their use.31 24 23 22 21 20 19 16 15 14 13 12 11 8 7 0
GIGN
PDPL
0 Type Base Address[23:16] +4
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Figure 4-17. Call-Gate Descriptor—Legacy Mode

GIGN
PDPL
Figure 4-18. Interrupt-Gate and Trap-Gate Descriptors—Legacy Mode
Figure 4-19. Task-Gate Descriptor—Legacy Mode
There are several differences between the gate-descriptor format and the system-segment descriptor 
format. These differences are described as follows, from least-significant to most-significant bit positions:
Target Code-Segment Offset.  The 32-bit segment offset is formed by concatenating bits 31:16 of 
byte +4 with bits 15:0 of byte +0. The segment-offset field specifies the target-procedure entry point (offset) into the segment. This field is loaded into the EIP register as a result of a control transfer using the gate descriptor. 
Target Code-Segment Selector.  Bits 31:16 of byte +0. The segment-selector field identifies the 
target-procedure segment descriptor, located in either the GDT or LDT. The segment selector is loaded into the CS segment register as a result of a control transfer using the gate descriptor.
TSS Selector.  Bits 31:16 of byte +0 (task gates only). This field identifies the target-task TSS 
descriptor, located in any of the three descriptor tables (GDT, LDT, and IDT).31 16 15 14 13 12 11 8 7 6 5 4 0
Target Code-Segment Offset[31:16]
PDPL
0 TypeReserved
IGNParameter Count +4
Target Code-Segment Selector Target Code-Segment Offset[15:0] +0
31 16 15 14 13 12 11 8 7 0
PDPL
0 Type Reserved, IGN +4
Reserved, IGN
PDPL
TSS Selector Reserved, IGN +0
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Parameter Count (Call Gates Only).  Bits 4:0 of byte +4. Legacy-mode call-gate descriptors contain 
a 5-bit parameter-count field. This field specifies the number of parameters to be copied from the 
currently-executing program stack to the target program stack during an automatic stack switch. 
Automatic stack switches are performed by the processor during a control transfer through a call gate to a greater privilege-level. The parameter size depends on the call-gate size as specified in the type field. 32-bit call gates copy 4-byte parameters, and 16-bit call gates copy 2-byte parameters. See “Stack Switching” on page 117 for more information on call-gate parameter copying.
4.8 Long-Mode Segment Descriptors
The interpretation of descriptor fields is changed in long mode, and in some cases the format is expanded. The changes depend on the operating mode (compatibility mode or 64-bit mode) and on the descriptor type. The following sections describe the changes.
4.8.1  Code-Segment Descriptors
Code segments continue to exist in long mode. Code segments and their associated descriptors and 
selectors are needed to establish the processor operating mode as well as execution privilege-level. The new L attribute specifies whether the processor is running in compatibility mode or 64-bit mode (see “Long (L) Attribute Bit” on page 98). Figure 4-20 shows the long-mode code-segment descriptor 
format. In compatibility mode, the code-segment descriptor is interpreted and behaves just as it does in legacy mode as described in “Code-Segment Descriptors” on page 91.
In Figure 4-20, gray shading indicates the code-segment descriptor fields that are  ignored in 64-bit 
mode  when the descriptor is used during a memory reference. However, the fields are loaded whenever 
the segment register is loaded in 64-bit mode.
Figure 4-20. Code-Segment Descriptor—Long Mode
Fields Ignored in 64-Bit Mode.  Segmentation is disabled in 64-bit mode, and code segments span 
all of virtual memory. In this mode, code-segment base addresses are ignored. For the purpose of 
virtual-address calculations, the base address is treated as if it has a value of zero. 
Segment-limit checking is not performed, and both the segment-limit field and granularity (G) bit are 
ignored. Instead, the virtual address is checked to see if it is in canonical-address form.
The readable (R) and accessed (A) attributes in the type field are also ignored.31 24 23 22 21 20 19 16 15 14 13 12 11 10 9 8 7 0
G
D
L
PDPL
1
1
C
R
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Long (L) Attribute Bit.  Bit 21 of byte +4. Long mode introduces a new attribute, the long (L) bit, in 
code-segment descriptors. This bit specifies that the processor is running in 64-bit mode (L=1) or 
compatibility mode (L=0). When the processor is running in legacy mode, this bit is reserved.
Compatibility mode maintains binary compatibility with legacy 16-bit and 32-bit applications. 
Compatibility mode is selected on a code-segment basis, and it allows legacy applications to coexist under the same 64-bit system software along with 64-bit applications running in 64-bit mode. System software running in long mode can execute existing 16-bit and 32-bit applications by clearing the L bit of the code-segment descriptor to 0. 
When L=0, the legacy meaning of the code-segment D bit (see “Code-Segment Default-Operand Size 
(D) Bit” on page 92)—and the address-size and operand-size prefixes—are observed. Segmentation is 
enabled when L=0. From an application viewpoint, the processor is in a legacy 16-bit or 32-bit operating environment (depending on the D bit), even though long mode is activated.
If the processor is running in 64-bit mode (L=1), the only valid setting of the D bit is 0. This setting 
produces a default operand size of 32 bits and a default address size of 64 bits. The combination L=1 and D=1 is reserved for future use.
“Instruction Prefixes” in V olume 3 describes the effect of the code-segment L and D bits on default 
operand and address sizes when long mode is activated. These default sizes can be overridden with operand size, address size, and REX prefixes.
4.8.2  Data-Segment Descriptors
Data segments continue to exist in long mode. Figure 4-21 shows the long-mode data-segment 
descriptor format. In compatibility mode, data-segment descriptors are interpreted and behave just as they do in legacy mode.
In Figure 4-21, gray shading indicates the fields that are ignored in 64-bit mode  when the descriptor is 
used during a memory reference. However, the fields are loaded whenever the segment register is 
loaded in 64-bit mode.
Figure 4-21. Data-Segment Descriptor—Long Mode
Fields Ignored in 64-Bit Mode.  Segmentation is disabled in 64-bit mode. The interpretation of the 
segment-base address depends on the segment register used:31 24 23 22 21 20 19 16 15 14 13 12 11 10 9 8 7 0
G
D/B
PDPL
1
0
E
W
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•In data-segment descriptors referenced by the DS, ES and SS segment registers, the base-address
field is ignored. For the purpose of virtual-address calculations, the base address is treated as if ithas a value of zero. 
•Data segments referenced by the FS and GS segment registers receive special treatment in 64-bitmode. For these segments, the base address field is not ignored, and a non-zero value can be usedin virtual-address calculations. A 64-bit segment-base address can be specified using model-specific registers. See “FS and GS Registers in 64-Bit Mode” on page 80 for more information.
Segment-limit checking is not performed on any data segments in 64-bit mode, and both the segment-limit field and granularity (G) bit are ignored. The D/B bit is unused in 64-bit mode.
The expand-down (E), writable (W), and accessed (A) type-field attributes are ignored.A data-segment-descriptor DPL field is ignored in 64-bit mode, and segment-privilege checks are not 
performed on data segments. System software can use the page-protection mechanisms to isolate and protect data from unauthorized access.
4.8.3  System Descriptors
In long mode, the allowable system-descriptor types encoded by the type field are changed. Some 
descriptor types are modified, and others are illegal. The changes are summarized in Table 4-6. An attempt to use an illegal descriptor type causes a general-protection exception (#GP).
Table 4-6. System-Segment Descriptor Types—Long Mode
Hex
ValueType FieldDescriptionBit 11 Bit 10 Bit 9 Bit 8
0 0 0 0 0Reserved (Illegal)1 0 0 0 1
2 0 0 1 0 64-bit LDT1
3 0 0 1 1
Reserved (Illegal)4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1 Available 64-bit TSS
A 1 0 1 0 Reserved (Illegal)
B 1 0 1 1 Busy 64-bit TSS
C 1 1 0 0 64-bit Call Gate
Note(s):
1. In 64-bit mode only. In compatibility mode, the type specifies a 32-bit LDT.
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In long mode, the modified system-segment descriptor types are:
•The 32-bit LDT (02h), which is redefined as the 64-bit LDT.

Hex
3 0 0 1 1
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
Note(s):
•The available 32-bit TSS (09h), which is redefined as the available 64-bit TSS.
•The busy 32-bit TSS (0Bh), which is redefined as the busy 64-bit TSS.
In 64-bit mode, the LDT and TSS system-segment descriptors are expanded by 64 bits, as shown in 
Figure 4-22. In this figure, gray shading indicates the fields that are  ignored in 64-bit mode . Expanding 
the descriptors allows them to hold 64-bit base addresses, so their segments can be located anywhere in the virtual-address space. The expanded descriptor can be loaded into the corresponding descriptor-table register (LDTR or TR) only from 64-bit mode. In compatibility mode, the legacy system-segment descriptor format, shown in Figure 4-16 on page 95, is used. See “LLDT and LTR 
Instructions” on page 180 for more information.
Figure 4-22. System-Segment Descriptor—64-Bit Mode
The 64-bit system-segment base address must be in canonical form. Otherwise, a general-protection exception occurs with a selector error-code, #GP(selector), when the system segment is loaded. System-segment limit values are checked by the processor in both 64-bit and compatibility modes, under the control of the granularity (G) bit.
Figure 4-22 shows that bits 12:8 of doubleword +12 must be cleared to 0. These bits correspond to the 
S and Type fields in a legacy descriptor. Clearing these bits to 0 corresponds to an illegal type in legacy D 1 1 0 1 Reserved (Illegal)
E 1 1 1 0 64-bit Interrupt Gate
F 1 1 1 1 64-bit Trap Gate
31 23 20 19 16 15 14 13 12 11 10 9 8 7 0
0
0000Reserved, IGN +12
Base Address[63:32] +8
G
PDPL
Base Address[15:0] Segment Limit[15:0] +0Table 4-6. System-Segment Descriptor Types—Long Mode (continued)
Hex
Note(s):
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mode and causes a #GP if an attempt is made to access the upper half of a 64-bit mode system-segment 
descriptor as a legacy descriptor or as the lower half of a 64-bit mode system-segment descriptor. 
4.8.4  Gate Descriptors
As shown in Table 4-6 on page 99, the allowable gate-descriptor types are changed in long mode. 
Some gate-descriptor types are modified and others are illegal. The modified gate-descriptor types in 
long mode are:
•The 32-bit call gate (0Ch), which is redefined as the 64-bit call gate.
•The 32-bit interrupt gate (0Eh), which is redefined as the 64-bit interrupt gate.
•The 32-bit trap gate (0Fh), which is redefined as the 64-bit trap gate.
In long mode, several gate-descriptor types are illegal. An attempt to use these gates causes a general-
protection exception (#GP) to occur. The illegal gate types are:
•The 16-bit call gate (04h).
•The task gate (05h).
•The 16-bit interrupt gate (06h).
•The 16-bit trap gate (07h).
In long mode, gate descriptors are expanded by 64 bits, allowing them to hold 64-bit offsets. The 64-
bit call-gate descriptor is shown in Figure 4-23 and the 64-bit interrupt gate and trap gate are shown in 
Figure 4-24 on page 102. In these figures, gray shading indicates the fields that are  ignored in long 
mode . The interrupt and trap gates contain an additional field, the IST, that is not present in the call 
gate—see “IST Field (Interrupt and Trap Gates)” on page 102.
Figure 4-23. Call-Gate Descriptor—Long Mode31 16 15 14 13 12 11 10 9 8 7 0
0
Target Offset[63:32] +8
Target Offset[31:16]
PDPL
Target Selector Target Offset[15:0] +0
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Figure 4-24. Interrupt-Gate and Trap-Gate Descriptors—Long Mode
The target code segment referenced by a long-mode gate descriptor must be a 64-bit code segment 
(CS.L=1, CS.D=0). If the target is not a 64-bit code segment, a general-protection exception, #GP(error), occurs. The error code reported depends on the gate type:
•Call gates report the target code-segment selector as the error code.
•Interrupt and trap gates report the interrupt vector number as the error code.
A general-protection exception, #GP(0), occurs if software attempts to reference a long-mode gate 
descriptor with a target-segment offset that is not in canonical form. 
It is possible for software to store legacy and long mode gate descriptors in the same descriptor table. 
Figure 4-23 on page 101 shows that bits 12:8 of byte +12 in a long-mode call gate must be cleared to 0. 
These bits correspond to the S and Type fields in a legacy call gate. Clearing these bits to 0 corresponds to an illegal type in legacy mode and causes a #GP if an attempt is made to access the upper half of a 64-bit mode call-gate descriptor as a legacy call-gate descriptor. 
It is not necessary to clear these same bits in a long-mode interrupt gate or trap gate. In long mode, the 
interrupt-descriptor table (IDT) must contain 64-bit interrupt gates or trap gates. The processor automatically indexes the IDT by scaling the interrupt vector by 16. This makes it impossible to access the upper half of a long-mode interrupt gate, or trap gate, as a legacy gate when the processor is running in long mode.
IST Field (Interrupt and Trap Gates).  Bits 2:0 of byte +4. Long-mode interrupt gate and trap gate 
descriptors contain a new, 3-bit interrupt-stack-table (IST) field not present in legacy gate descriptors. The IST field is used as an index into the IST portion of a long-mode TSS. If the IST field is not 0, the index references an IST pointer in the TSS, which the processor loads into the RSP register when an interrupt occurs. If the IST index is 0, the processor uses the legacy stack-switching mechanism (with some modifications) when an interrupt occurs. See “Interrupt-Stack Table” on page 284 for more information.31 16 15 14 13 12 11 8 7 3 2 0
Reserved, IGN +12
PDPL
0 Type Reserved, IGN IST +4
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Count Field (Call Gates).  The count field found in legacy call-gate descriptors is not supported in 
long-mode call gates. In long mode, the field is reserved and should be cleared to zero.
4.8.5  Long Mode Descriptor Summary
System descriptors and gate descriptors are expanded by 64 bits to handle 64-bit base addresses in 
long mode or 64-bit mode. The mode in which the expansion occurs depends on the purpose served by the descriptor, as follows: 
•Expansion Only In 64-Bit Mode —The system descriptors and pseudo-descriptors that are loaded
into the GDTR, IDTR, LDTR, and TR registers are expanded only in 64-bit mode. They are not
expanded in compatibility mode. 
•Expansion In Long Mode —Gate descriptors (call gates, interrupt gates, and trap gates) are
expanded in long mode (both 64-bit mode and compatibility mode). Task gates and 16-bit gatedescriptors are illegal in long mode.
The AMD64 architecture redefines several of the descriptor-entry fields in support of long mode. The specific change depends on whether the processor is in 64-bit mode or compatibility mode. Table 4-7 summarizes the changes in the descriptor entry field when the descriptor entry is loaded into a segment register (as opposed to when the segment register is subsequently used to access memory).
Table 4-7. Descriptor-Entry Field Changes in Long Mode
Descriptor 
FieldDescriptor 
TypeLong Mode
Compatibility Mode 64-Bit Mode
LimitCode
Same as legacy x86 Same as legacy x86 Data
System
Offset Gate Expanded to 64 bits Expanded to 64 bits
BaseCode
Same as legacy x86Same as legacy x86DataSystem
Selector Gate
Same as legacy x86
IST1 Gate Interrupt and trap gates only. (New for long mode.)
S and TypeCode
Same as legacy x86 Same as legacy x86Data
SystemTypes 02h, 09h, and 0Bh redefined
Types 01h and 03h are illegal
GateTypes 0Ch, 0Eh, and 0Fh redefinedTypes 04h–07h are illegal
Note(s):
1. Not available (reserved) in legacy mode.
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4.9 Segment-Protection Overview
The AMD64 architecture is designed to fully support the legacy segment-protection mechanism. The 
segment-protection mechanism provides system software with the ability to restrict program access into other software routines and data. 
Segment-level protection remains enabled in compatibility mode. 64-bit mode eliminates most type 
checking, and limit checking is not performed, except on accesses to system-descriptor tables.
The preferred method of implementing memory protection in a long-mode operating system is to rely 
on the page-protection mechanism as described in “Page-Protection Checks” on page 161. System

Note(s):
on the page-protection mechanism as described in “Page-Protection Checks” on page 161. System 
software still needs to create basic segment-protection data structures for 64-bit mode. These structures are simplified, however, by the use of the flat-memory model in 64-bit mode, and the limited segmentation checks performed when executing in 64-bit mode.DPLCode
SystemGate
PresentCode
Same as legacy x86 Same as legacy x86DataSystemGate
Default SizeCode
Same as legacy x86D=0 Indicates 64-bit address, 32-bit data
D=1 Reserved
Data Same as legacy x86
Long1 Code Specifies compatibility mode Specifies 64-bit mode
GranularityCode
System
AvailableCode
Same as legacy x86 Same as legacy x86 DataSystemTable 4-7. Descriptor-Entry Field Changes in Long Mode (continued)
Note(s):
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4.9.1  Privilege-Level Concept
Segment protection is used to isolate and protect programs and data from each other. The segment-
protection mechanism supports four privilege levels in protected mode. The privilege levels are designated with a numerical value from 0 to 3, with 0 being the most privileged and 3 being the least privileged. System software typically assigns the privilege levels in the following manner:
•Privilege-level 0 (most privilege) —This level is used by critical system-software components that
require direct access to, and control over, all processor and system resources. This can include
platform firmware, memory-management functions, and interrupt handlers.
•Privilege-levels 1 and 2 (moderate privilege) —These levels are used by less-critical system-
software services that can access and control a limited scope of processor and system resources.Software running at these privilege levels might include some device drivers and library routines.These software routines can call more-privileged system-software services to perform functionssuch as memory garbage-collection and file allocation. 
•Privilege-level 3 (least privilege) —This level is used by application software. Software running at
privilege-level 3 is normally prevented from directly accessing most processor and systemresources. Instead, applications request access to the protected processor and system resources bycalling more-privileged service routines to perform the accesses.
Figure 4-25 shows the relationship of the four privilege levels to each other.
Figure 4-25. Privilege-Level Relationships
4.9.2  Privilege-Level Types
There are three types of privilege levels the processor uses to control access to segments. These are 
CPL, DPL, and RPL.
Current Privilege-Level.  The current privilege-level (CPL) is the privilege level at which the 
processor is currently executing. The CPL is stored in an internal processor register that is invisible to 513-236.eps Application ProgramsMemory Management
File AllocationInterrupt Handling
Device-Drivers
Library Routines Privilege
0
Privilege 1
Privilege 2
Privilege 3
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software. Software changes the CPL by performing a control transfer to a different code segment with 
a new privilege level.
Descriptor Privilege-Level.  The descriptor privilege-level (DPL) is the privilege level that system 
software assigns to individual segments. The DPL is used in privilege checks to determine whether software can access the segment referenced by the descriptor. In the case of gate descriptors, the DPL determines whether software can access the descriptor reference by the gate. The DPL is stored in the segment (or gate) descriptor.
Requestor Privilege-Level.  The requestor privilege-level (RPL) reflects the privilege level of the 
program that created the selector. The RPL can be used to let a called program know the privilege level of the program that initiated the call. The RPL is stored in the selector used to reference the segment (or gate) descriptor.
The following sections describe how the CPL, DPL, and RPL are used by the processor in performing 
privilege checks on data accesses and control transfers. Failure to pass a protection check generally causes an exception to occur.
4.10 Data-Access Privilege Checks
4.10.1  Accessing Data Segments
Before loading a data-segment register (DS, ES, FS, or GS) with a segment selector, the processor 
checks the privilege levels as follows to see if access is allowed:
1. The processor compares the CPL with the RPL in the data-segment selector and determines the
effective privilege level for the data access. The processor sets the effective privilege level to the
lowest privilege (numerically-higher value) indicated by the comparison.
2. The processor compares the effective privilege level with the DPL in the descriptor-table entry
referenced by the segment selector. If the effective privilege level is greater than or equal to(numerically lower-than or equal-to) the DPL, then the processor loads the segment register withthe data-segment selector. The processor automatically loads the corresponding descriptor-tableentry into the hidden portion of the segment register. 
If the effective privilege level is lower than (numerically greater-than) the DPL, a general-
protection exception (#GP) occurs and the segment register is not loaded.
Figure 4-26 on page 107 shows two examples of data-access privilege checks.
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Figure 4-26. Data-Access Privilege-Check Examples
Example 1 in Figure 4-26 shows a failing data-access privilege check. The effective privilege level is 3 
because CPL=3. This value is greater than the descriptor DPL, so access to the data segment is denied.
Example 2 in Figure 4-26 shows a passing data-access privilege check. Here, the effective privilege 
level is 0 because both the CPL and RPL have values of 0. This value is less than the descriptor DPL, so access to the data segment is allowed, and the data-segment register is successfully loaded.
4.10.2  Accessing Stack Segments
Before loading the stack segment register (SS) with a segment selector, the processor checks the 
privilege levels as follows to see if access is allowed:513-229.epsDPL=2Effective
Privilege
3
£MaxCPL=3
RPL=0Access DeniedData
Segment
DescriptorCS
Data
Selector
Example 1: Privilege Check Fails
DPL=2Effective
Privilege
0
£MaxCPL=0
RPL=0Access AllowedData
SegmentCS
Example 2: Privilege Check PassesData
Selector
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1. The processor checks that the CPL and the stack-selector RPL are equal . If they are not equal, a
general-protection exception (#GP) occurs and the SS register is not loaded.
2. The processor compares the CPL with the DPL in the descriptor-table entry referenced by the
segment selector. The two values must be equal . If they are not equal, a #GP occurs and the SS
register is not loaded.
Figure 4-27 shows two examples of stack-access privilege checks. In Example 1 the CPL, stack-
selector RPL, and stack segment-descriptor DPL are all equal, so access to the stack segment using the SS register is allowed. In Example 2, the stack-selector RPL and stack segment-descriptor DPL are both equal. However, the CPL is not equal to the stack segment-descriptor DPL, and access to the stack segment through the SS register is denied.
Figure 4-27. Stack-Access Privilege-Check Examples
513-235.epsDPL=3=CPL=3
RPL=3Access AllowedStack
Segment
Stack
Selector
Example 1: Privilege Check Passes
DPL=3=CPL=2
RPL=3Access DeniedStack
SegmentCS
Example 2: Privilege Check FailsStack
Selector
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4.11 Control-Transfer Privilege Checks
Control transfers between code segments (also called far control transfers ) cause the processor to 
perform privilege checks to determine whether the source program is allowed to transfer control to the 
target program. If the privilege checks pass, access to the target code-segment is granted. When access is granted, the target code-segment selector is loaded into the CS register. The rIP register is updated with the target CS offset taken from either the far-pointer operand or the gate descriptor. Privilege checks are not performed during near control transfers because such transfers do not change 
segments.
The following mechanisms can be used by software to perform far control transfers:
•System-software control transfers using the system-call  and system-return  instructions. See
“SYSCALL and SYSRET” on page 174 and “SYSENTER and SYSEXIT (Legacy Mode Only)”
on page 176 for more information on these instructions. SYSCALL and SYSRET are the preferred
method of performing control transfers in long mode. SYSENTER and SYSEXIT are not supported
in long mode.

segments.
•Direct control transfers using CALL and JMP instructions. These are discussed in the next section,“Direct Control Transfers.”
•Call-gate control transfers using CALL and JMP instructions. These are discussed in “ControlTransfers Through Call Gates” on page 113.
•Return control transfers using the RET instruction. These are discussed in “Return ControlTransfers” on page 120.
•Interrupts and exceptions, including the INT n and IRET instructions. These are discussed in
Chapter 8, “Exceptions and Interrupts.”
•Task switches initiated by CALL and JMP instructions. Task switches are discussed in Chapter 12,“Task Management.” The hardware task-switch mechanism is not supported in long mode.
4.11.1  Direct Control Transfers
A direct control transfer  occurs when software executes a far-CALL or a far-JMP instruction without 
using a call gate. The privilege checks and type of access allowed as a result of a direct control transfer 
depends on whether the target code segment is conforming or nonconforming. The code-segment-descriptor conforming (C) bit indicates whether or not the target code-segment is conforming (see “Conforming (C) Bit” on page 91 for more information on the conforming bit).
Privilege levels are not changed as a result of a direct control transfer. Program stacks are not automatically switched by the processor as they are with privilege-changing control transfers through call gates (see “Stack Switching” on page 117 for more information on automatic stack switching during privilege-changing control transfers).
Nonconforming Code Segments.  Software can perform a direct control transfer to a 
nonconforming code segment only if the target code-segment descriptor DPL and the CPL are equal and the RPL is less than or equal to the CPL. Software must use a call gate to transfer control to a 
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more-privileged, nonconforming code segment (see “Control Transfers Through Call Gates” on 
page 113 for more information).
In far calls and jumps, the far pointer (CS:rIP) references the target code-segment descriptor. Before 
loading the CS register with a nonconforming code-segment selector, the processor checks as follows to see if access is allowed:
1.DPL = CPL Check —The processor compares the target code-segment descriptor DPL with the
currently executing program CPL. If they are equal, the processor performs the next check. If they
are not equal, a general-protection exception (#GP) occurs.
2.RPL  CPL Check —The processor compares the target code-segment selector RPL with the
currently executing program CPL. If the RPL is less than or equal to the CPL, access is allowed. Ifthe RPL is greater than the CPL, a #GP exception occurs.
If access is allowed, the processor loads the CS and rIP registers with their new values and begins executing from the target location. The CPL is not changed —the target-CS selector RPL value is 
disregarded when the selector is loaded into the CS register.
Figure 4-28 on page 111 shows three examples of privilege checks performed as a result of a far 
control transfer to a nonconforming code-segment. In Example 1, access is allowed because CPL = DPL and RPL CPL. In Example 2, access is denied because CPL 
DPL. In Example 3, access is 
denied because RPL  CPL.
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Figure 4-28. Nonconforming Code-Segment Privilege-Check Examples
Conforming Code Segments.  On a direct control transfer to a conforming code segment, the target 
code-segment descriptor DPL can be lower than (at a greater privilege) the CPL. Before loading the 513-230.epsAccess Allowed
Code
Segment
Example 1: Privilege Check PassesCS CPL=2
=
DPL=2
DescriptorRPL=0Code
Selector
£
?Access
Allowed
Access
Allowed
Access Denied
Code
Segment
Example 2: Privilege Check FailsCS CPL=2
=
DPL=3
Selector
£
?Access
Allowed
Access
Denied
Code
Segment
Example 3: Privilege Check FailsCS CPL=2
=
DPL=2
DescriptorRPL=3Code
Selector
£
?Access
Denied
Access
Allowed
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CS register with a conforming code-segment selector, the processor compares the target code-segment 
descriptor DPL with the currently-executing program CPL. If the DPL is less than or equal to the CPL, access is allowed. If the DPL is greater than the CPL, a #GP exception occurs.
On an access to a conforming code segment, the RPL is ignored and not involved in the privilege 
check.
When access is allowed, the processor loads the CS and rIP registers with their new values and begins 
executing from the target location. The CPL is not changed —the target CS-descriptor DPL value is 
disregarded when the selector is loaded into the CS register. The target program runs at the same privilege as the program that called it.
Figure 4-29 shows two examples of privilege checks performed as a result of a direct control transfer 
to a conforming code segment. In Example 1, access is allowed because the CPL of 3 is greater than the DPL of 0. As the target code selector is loaded into the CS register, the old CPL value of 3 replaces the target-code selector RPL value, and the target program executes with CPL=3. In Example 2, access is denied because CPL  DPL.
Figure 4-29. Conforming Code-Segment Privilege-Check Examples
513-231.epsAccess AllowedCode
Segment
Example 1: Privilege Check PassesCS CPL=3
³
DPL=0
DescriptorCode
Selector
Access DeniedCode
Segment
Example 2: Privilege Check FailsCS CPL=0
³
DPL=3
Selector
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4.11.2  Control Transfers Through Call Gates
Control transfers to more-privileged code segments are accomplished through the use of call gates. 
Call gates are a type of descriptor that contain pointers to code-segment descriptors and control access 
to those descriptors. System software uses call gates to establish protected entry points into system-service routines.
Transfer Mechanism.  The pointer operand of a far-CALL or far-JMP instruction consists of two 
pieces: a code-segment selector (CS) and a code-segment offset (rIP). In a call-gate transfer, the CS selector points to a call-gate descriptor rather than a code-segment descriptor, and the rIP is ignored (but required by the instruction).
Figure 4-30 shows a call-gate control transfer in legacy mode. The call-gate descriptor contains 
segment-selector and segment-offset fields (see “Gate Descriptors” on page 95 for a detailed 
description of the call-gate format and fields). These two fields perform the same function as the pointer operand in a direct control-transfer instruction. The segment-selector field points to the target code-segment descriptor, and the segment-offset field is the instruction-pointer offset into the target code-segment. The code-segment base taken from the code-segment descriptor is added to the offset field in the call-gate descriptor to create the target virtual address (linear address).
Figure 4-30. Legacy-Mode Call-Gate Transfer Mechanism
513-233.epsVirtual-Address
Space
Code SegmentFar Pointer
DPL Code-Segment Limit
Code-Segment BaseDPL Code-Segment Selector
Code-Segment OffsetSegment Selector Instruction Offset
+Call-Gate
Code-Segment
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Figure 4-31 shows a call-gate control transfer in long mode. The long-mode call-gate descriptor 
format is expanded by 64 bits to hold a full 64-bit offset into the virtual-address space. Only long-mode call gates can be referenced in long mode (64-bit mode and compatibility mode). The legacy-mode 32-bit call-gate types are redefined in long mode as 64-bit types, and 16-bit call-gate types are illegal.
Figure 4-31. Long-Mode Call-Gate Access Mechanism
A long-mode call gate must reference a 64-bit code-segment descriptor. In 64-bit mode, the code-segment descriptor base-address and limit fields are ignored. The target virtual-address is the 64-bit offset field in the expanded call-gate descriptor.
Privilege Checks.  Before loading the CS register with the code-segment selector located in the call 
gate, the processor performs three privilege checks. The following checks are performed when either conforming or nonconforming code segments are referenced:
1. The processor compares the CPL with the call-gate DPL from the call-gate descriptor (DPL
G).
The CPL must be numerically less than or equal to DPLG for this check to pass. In other words,
the following expression must be true: CPL DPLG.513-234.epsVirtual-Address
Space
Flat Code-SegmentDPL Code-Segment Limit
Code-Segment Offset (31:0)Far Pointer
Segment Selector
UnusedInstruction Offset
Code-Segment Offset (63:32)Call-Gate

G).
Space
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2. The processor compares the RPL in the call-gate selector with DPLG. The RPL must be
numerically less than or equal to  DPLG for this check to pass. In other words, the following
expression must be true: RPL DPLG.
3. The processor compares the CPL with the target code-segment DPL from the code-segment
descriptor (DPLS). The type of comparison varies depending on the type of control transfer.
- When a call—or a jump to a conforming  code segment—is used to transfer control through a 
call gate, the CPL must be numerically greater than or equal to  DPLS for this check to pass. 
(This check prevents control transfers to less-privileged programs.) In other words, the 
following expression must be true: CPL DPLS.
- When a JMP instruction is used to transfer control through a call gate to a nonconforming  code 
segment, the CPL must be numerically equal to  DPLS for this check to pass. (JMP instructions 
cannot change CPL.) In other words, the following expression must be true: CPL = DPLS.
Figure 4-32 on page 116 shows two examples of call-gate privilege checks. In Example 1, all privilege 
checks pass as follows: 
•The call-gate DPL (DPLG) is at the lowest privilege (3), specifying that software running at any
privilege level (CPL) can access the gate.
•The selector referencing the call gate passes its privilege check because the RPL is numerically
less than or equal to DPLG.
•The target code segment is at the highest privilege level (DPLS= 0). This means software running
at any privilege level can access the target code segment through the call gate.
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Figure 4-32. Privilege-Check Examples for Call Gates
In Example 2, all privilege checks fail as follows:
•The call-gate DPL (DPLG) specifies that only software at privilege-level 0 can access the gate. The
current program does not have enough privilege to access the call gate because its CPL is 2.
•The selector referencing the call-gate descriptor does not have enough privilege to complete the
reference. Its RPL is numerically greater than DPLG.513-232.epsExample 1: Privilege Check PassesDPL G=3
Call-Gate DescriptorCode
SegmentCS CPL=2
DPL S=0
Code-Segment DescriptorCall-Gate
SelectorRPL=3
Example 2: Privilege Check FailsDPL G=0
DPL S=3
SelectorRPL=3Access Allowed
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•The target code segment is at a lower privilege (DPLS= 3) than the currently running software
(CPL = 2). Transitions from more-privileged software to less-privileged software are not allowed,
so this privilege check fails as well.
Although all three privilege checks failed in Example 2, failing only one check is sufficient to deny 
access into the target code segment.
Stack Switching.  The processor performs an automatic stack switch when a control transfer causes a 
change in privilege levels to occur. Switching stacks isolates more-privileged software stacks from less-privileged software stacks and provides a mechanism for saving the return pointer back to the program that initiated the call.
When switching to more-privileged software, as is done when transferring control using a call gate, the 
processor uses the corresponding stack pointer (privilege-level 0, 1, or 2) stored in the task-state segment (TSS). The format of the stack pointer stored in the TSS depends on the system-software operating mode:
•Legacy-mode system software stores a 32-bit ESP value (stack offset) and 16-bit SS selector
register value in the TSS for each of three privilege levels 0, 1, and 2. 
•Long-mode system software stores a 64-bit RSP value in the TSS for privilege levels 0, 1, and 2.No SS register value is stored in the TSS because in long mode a call gate must reference a 64-bit
code-segment descriptor. 64-bit mode does not use segmentation, and the stack pointer consistssolely of the 64-bit RSP. Any value loaded in the SS register is ignored.
See “Task-Management Resources” on page 366 for more information on the legacy-mode and long-mode TSS formats.
Figure 4-33 on page 118 shows a 32-bit stack in legacy mode before and after the automatic stack 
switch. This particular example assumes that parameters are passed from the current program to the 
target program. The process followed by legacy mode in switching stacks and copying parameters is:
1. The target code-segment DPL is read by the processor and used as an index into the TSS for
selecting the new stack pointer (SS:ESP). For example, if DPL=1 the processor selects the
SS:ESP for privilege-level 1 from the TSS.
2. The SS and ESP registers are loaded with the new SS:ESP values read from the TSS.
3. The old values of the SS and ESP registers are pushed onto the stack pointed to by the new
SS:ESP.
4. The 5-bit count field is read from the call-gate descriptor. 5. The number of parameters specified in the count field (up to 31) are copied from the old stack to
the new stack. The size of the parameters copied by the processor depends on the call-gate size:
32-bit call gates copy 4-byte parameters and 16-bit call gates copy 2-byte parameters.
6. The return pointer is pushed onto the stack. The return pointer consists of the current CS-register
value and the EIP of the instruction following the calling instruction.
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7. The CS register is loaded from the segment-selector field in the call-gate descriptor, and the EIP is
loaded from the offset field in the call-gate descriptor.
8. The target program begins executing with the instruction referenced by new CS:EIP.
Figure 4-33. Legacy-Mode 32-Bit Stack Switch, with Parameters
Figure 4-34 shows a 32-bit stack in legacy mode before and after the automatic stack switch when no 
parameters are passed (count=0). Most software does not use the call-gate descriptor count-field to pass parameters. System software typically defines linkage mechanisms that do not rely on automatic parameter copying.
Figure 4-34. 32-Bit Stack Switch, No Parameters—Legacy Mode
Figure 4-35 on page 119 shows a long-mode stack switch. In long mode, all call gates must reference 
64-bit code-segment descriptors, so a long-mode stack switch uses a 64-bit stack. The process of 513-224.epsParameter n. . .Parameter 1
Parameter 2 +(n-2)*4+(n-1)*4
Old SS:ESPOld
32-Bit Stack
Before CALLNew
After CALL
Old SS
Old ESP
Old EIPParameter n. . .Parameter 1
Parameter 2
Old CS +4+8+(n*4)+8+(n*4)+12
+(n*4)+(n*4)+4
New SS:ESP
Stack Switch
513-225.epsOld SS:ESPOld
After CALL
Old EIPOld ESPOld SS
Old CS +4+8+12
New SS:ESP
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switching stacks in long mode is similar to switching in legacy mode when no parameters are passed. 
The process is as follows:
1. The target code-segment DPL is read by the processor and used as an index into the 64-bit TSS
for selecting the new stack pointer (RSP). 
2. The RSP register is loaded with the new RSP value read from the TSS. The SS register is loaded
with a null selector (SS 0). Setting the new SS selector to null allows proper handling of nested
control transfers in 64-bit mode. See “Nested Returns to 64-Bit Mode Procedures” on page 121
As in legacy mode, it is desirable to keep the stack-segment requestor privilege-level (SS.RPL)
equal to the current privilege-level (CPL). When using a call gate to change privilege levels, theSS.RPL is updated to reflect the new CPL. The SS.RPL is restored from the return-target CS.RPLon the subsequent privilege-level-changing far return.
3. The old values of the SS and RSP registers are pushed onto the stack pointed to by the new RSP.
The old SS value is popped on a subsequent far return. This allows system software to set up theSS selector for a compatibility-mode process by executing a RET (or IRET) that changes theprivilege level.
4. The return pointer is pushed onto the stack. The return pointer consists of the current CS-register
value and the RIP of the instruction following the calling instruction.
5. The CS register is loaded from the segment-selector field in the long-mode call-gate descriptor,
and the RIP is loaded from the offset field in the long-mode call-gate descriptor.
The target program begins execution with the instruction referenced by the new RIP.
Figure 4-35. Stack Switch—Long Mode
All long-mode stack pushes resulting from a privilege-level-changing far call are eight-bytes wide and increment the RSP by eight. Long mode ignores the call-gate count field and does not support the automatic parameter-copy feature found in legacy mode. Software can access parameters on the old stack, if necessary, by referencing the old stack segment selector and stack pointer saved on the new process stack.513-226.epsOld SS:RSPOld
64-Bit Stack
After CALL
Old RIPOld RSPOld SS

After CALL
Old CS +8+16+24
New RSP
Stack Switch(SS=0 + new_CPL)
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4.11.3  Return Control Transfers
Returns to calling programs can be performed by using the RET instruction. The following types of 
returns are possible:
•Near Return —Near returns perform control transfers within the same code segment, so the CS
register is unchanged. The new offset is popped off the stack and into the rIP register. No privilege
checks are performed.
•Far Return, Same Privilege —A far return transfers control from one code segment to another.
When the original code segment is at the same privilege level as the target code segment, a farpointer (CS:rIP) is popped off the stack and the RPL of the new code segment (CS) is checked. Ifthe requested privilege level (RPL) matches the current privilege level (CPL), then a return is madeto the same privilege level. This prevents software from changing the CS value on the stack in anattempt to return to higher-privilege software.
•Far Return, Less Privilege —Far returns can change privilege levels, but only to a lower -privilege
level. In this case a stack switch is performed between the current, higher-privilege program andthe lower-privilege return program. The CS-register and rIP-register values are popped off thestack. The lower-privilege stack pointer is also popped off the stack and into the SS register andrSP register. The processor checks both the CS and SS privilege levels to ensure they are equal andat a lesser privilege than the current CS.
In the case of nested returns to 64-bit mode, a null selector can be popped into the SS register. See
“Nested Returns to 64-Bit Mode Procedures” on page 121.
Far returns also check the privilege levels of the DS, ES, FS and GS selector registers. If any of
these segment registers have a selector with a higher privilege than the return program, thesegment register is loaded with the null selector.
Stack Switching.  The stack switch performed by a far return to a lower-privilege level reverses the 
stack switch of a call gate to a higher-privilege level, except that parameters are never automatically copied as part of a return. The process followed by a far-return stack switch in long mode and legacy mode is:
1. The return code-segment RPL is read by the processor from the CS value stored on the stack to
determine that a lower-privilege control transfer is occurring.
2. The return-program instruction pointer is popped off the current-program (higher privilege) stack
and loaded into the CS and rIP registers.
3. The return instruction can include an immediate operand that specifies the number of additional
bytes to be popped off of the stack. These bytes may correspond to the parameters pushed onto the
stack previously by a call through a call gate containing a non-zero parameter-count field. If thereturn includes the immediate operand, then the stack pointer is adjusted upward by adding thespecified number of bytes to the rSP.
4. The return-program stack pointer is popped off the current-program (higher privilege) stack and
loaded into the SS and rSP registers. In the case of nested returns to 64-bit mode, a null selectorcan be popped into the SS register.
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The operand size of a far return determines the size of stack pops when switching stacks. If a far return 
is used in 64-bit mode to return from a prior call through a long-mode call gate, the far return must use a 64-bit operand size. The 64-bit operand size allows the far return to properly read the stack established previously by the far call.
Nested Returns to 64-Bit Mode Procedures.  In long mode, a far call that changes privilege levels 
causes the SS register to be loaded with a null selector (this is the same action taken by an interrupt in long mode). If the called procedure performs another far call to a higher-privileged procedure, or is interrupted, the null SS selector is pushed onto the stack frame, and another null selector is loaded into the SS register. Using a null selector in this way allows the processor to properly handle returns nested within 64-bit-mode procedures and interrupt handlers. 
Normally, a RET that pops a null selector into the SS register causes a general-protection exception 
(#GP) to occur. However, in long mode, the null selector acts as a flag indicating the existence of nested interrupt handlers or other privileged software in 64-bit mode. Long mode allows RET to pop a null selector into SS from the stack under the following conditions: 
•The target mode is 64-bit mode.
•The target CPL is less than 3.
In this case, the processor does not load an SS descriptor, and the null selector is loaded into SS 
without causing a #GP exception.
4.12 Limit Checks
Except in 64-bit mode, limit checks are performed by all instructions that reference memory. Limit checks detect attempts to access memory outside the current segment boundary, attempts at executing instructions outside the current code segment, and indexing outside the current descriptor table. If an instruction fails a limit check, either (1) a general-protection exception occurs for all other segment-limit violations or (2) a stack-fault exception occurs for stack-segment limit violations.
In 64-bit mode, segment limits are not checked during accesses to any segment referenced by the CS, 
DS, ES, FS, GS, and SS selector registers. Instead, the processor checks that the virtual addresses used 
to reference memory are in canonical-address form. In 64-bit mode, as with legacy mode and compatibility mode, descriptor-table limits are checked .
4.12.1  Determining Limit Violations
To determine segment-limit violations, the processor checks a virtual (linear) address to see if it falls 
outside the valid range of segment offsets determined by the segment-limit field in the descriptor. If any part of an operand or instruction falls outside the segment-offset range, a limit violation occurs. For example, a doubleword access, two bytes from an upper segment boundary, causes a segment violation because half of the doubleword is outside the segment.
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Three bits from the descriptor entry are used to control how the segment-limit field is interpreted: the 
granularity (G) bit, the default operand-size (D) bit, and for data segments, the expand-down (E) bit. See “Legacy Segment Descriptors” on page 88 for a detailed description of each bit.
For all segments other than expand-down segments, the minimum segment-offset is 0. The maximum segment-offset depends on the value of the G bit:
•If G=0 (byte granularity), the maximum allowable segment-offset is equal to the value of the
segment-limit field.
•If G=1 (4096-byte granularity), the segment-limit field is first scaled by 4096 (1000h). Then 4095(0FFFh) is added to the scaled value to arrive at the maximum allowable segment-offset, as shownin the following equation:
maximum segment-offset  (limit  1000h)  0FFFh
For example, if the segment-limit field is 0100h, then the maximum allowable segment-offset is(0100h1000h)0FFFh10_1FFFh.
In both cases, the maximum segment-size is specified when the descriptor segment-limit field is 
0F_FFFFh.
Expand-Down Segments.   Expand-down data segments are supported in legacy mode and 
compatibility mode but not in 64-bit mode. With expand-down data segments, the maximum segment offset depends on the value of the D bit in the data-segment descriptor:
•If D=0 the maximum segment-offset is 0_FFFFh.
•If D=1 the maximum segment-offset is 0_FFFF_FFFFh.
The minimum allowable segment offset in expand-down segments depends on the value of the G bit: •If G=0 (byte granularity), the minimum allowable segment offset is the segment-limit value plus 1.
For example, if the segment-limit field is 0100h, then the minimum allowable segment-offset is
0101h.
•If G=1 (4096-byte granularity), the segment-limit value in the descriptor is first scaled by 4096(1000h), and then 4095 (0FFFh) is added to the scaled value to arrive at a scaled segment-limitvalue. The minimum allowable segment-offset is this scaled segment-limit value plus 1, as shownin the following equation:
minimum segment-offset  (limit  1000)  0FFFh  1
For example, if the segment-limit field is 0100h, then the minimum allowable segment-offset is(0100h1000h)0FFFh 1 10_1000h.
For expand-down segments, the maximum segment size is specified when the segment-limit value is 
0.
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4.12.2  Data Limit Checks in 64-bit Mode
In 64-bit mode, data reads and writes are not normally checked for segment-limit violations. When 
EFER.LMSLE = 1, reads and writes in 64-bit mode at CPL > 0, using the DS, ES, FS, or SS segments, have a segment-limit check applied.

0101h.
0.
This limit-check uses the 32-bit segment-limit to find the maximum allowable address in the top 4GB 
of the 64-bit virtual (linear) address space.
This segment-limit check does not apply to accesses through the GS segment, or to code reads. If the 
DS, ES, FS, or SS segment is null or expand-down, the effect of the limit check is undefined. Data segment limit checking in 64-bit mode is not supported by all processor implementations and has been deprecated. If CPUID Fn8000_0008_EBX[EferLmlseUnsupported](bit 20) = 1, 64-bit mode segment limit checking is not supported and attempting to enable this feature by setting EFER.LMSLE =1 will result in a #GP exception.
4.13 Type Checks
Type checks prevent software from using descriptors in invalid ways. Failing a type check results in an exception. Type checks are performed using five bits from the descriptor entry: the S bit and the 4-bit Type field. Together, these five bits are used to specify the descriptor type (code, data, segment, or gate) and its access characteristics. See “Legacy Segment Descriptors” on page 88 for a detailed 
description of the S bit and Type-field encodings. Type checks are performed by the processor in compatibility mode as well as legacy mode. Limited type checks are performed in 64-bit mode.
4.13.1  Type Checks in Legacy and Compatibility Modes
The type checks performed in legacy mode and compatibility mode are listed in the following sections.
Descriptor-Table Register Loads.  Loads into the LDTR and TR descriptor-table registers are 
checked for the appropriate system-segment type. The LDTR can only be loaded with an LDT 
descriptor, and the TR only with a TSS descriptor. The checks are performed during any action that causes these registers to be loaded. This includes execution of the LLDT and LTR instructions and during task switches.
Segment Register Loads.  The following restrictions are placed on the segment-descriptor types that 
can be loaded into the six user segment registers:
•Only code segments can be loaded into the CS register.
•Only writable data segments can be loaded into the SS register.Table 4-8. Segment Limit Checks in 64-Bit Mode
Memory Address Effect of Limit Check
Linear Address £ (0FFFFFFFF_00000000h + 32-bit Limit) Access OK.
Linear Address > (0FFFFFFFF_00000000h + 32-bit Limit) Exception (#GP or #SS)
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•Only the following segment types can be loaded into the DS, ES, FS, or GS registers:
- Read-only or read/write data segments.- Readable code segments.
These checks are performed during any action that causes the segment registers to be loaded. This 
includes execution of the MOV segment-register instructions, control transfers, and task switches.
Control Transfers.  Control transfers (branches and interrupts) place additional restrictions on the 
segment types that can be referenced during the transfer:
•The segment-descriptor type referenced by far CALLs and far JMPs must be one of the following:
- A code segment- A call gate or a task gate- An available TSS (only allowed in legacy mode)- A task gate (only allowed in legacy mode)
•Only code-segment descriptors can be referenced by call-gate, interrupt-gate, and trap-gate
descriptors.
•Only TSS descriptors can be referenced by task-gate descriptors.
•The link field (selector) in the TSS can only point to a TSS descriptor. This is checked during anIRET control transfer to a task.
•The far RET and far IRET instructions can only reference code-segment descriptors.
•The interrupt-descriptor table (IDT), which is referenced during interrupt control transfers, canonly contain interrupt gates, trap gates, and task gates.
Segment Access.  After a segment descriptor is successfully loaded into one of the segment 
registers, reads and writes into the segments are restricted in the following ways:
•Writes are not allowed into read-only data-segment types.
•Writes are not allowed into code-segment types (executable segments).
•Reads from code-segment types are not allowed if the readable (R) type bit is cleared to 0.
These checks are generally performed during execution of instructions that access memory.
4.13.2  Long Mode Type Check Differences
Compatibility Mode and 64-Bit Mode.  The following type checks differ in long mode (64-bit mode 
and compatibility mode) as compared to legacy mode:
•System Segments—System-segment types are checked, but the following types that are valid in
legacy mode are illegal in long mode:
- 16-bit available TSS.- 16-bit busy TSS.
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- Type-field encoding of 00h in the upper half of a system-segment descriptor to indicate an 
illegal type and prevent access as a legacy descriptor. 
•Gates —Gate-descriptor types are checked, but the following types that are valid in legacy mode
are illegal in long mode: 
- 16-bit call gate.- 16-bit interrupt gate.- 16-bit trap gate.- Task gate.
64-Bit Mode.  64-bit mode disables segmentation, and most of the segment-descriptor fields are 
ignored. The following list identifies situations where type checks in 64-bit mode differ from those in 
compatibility mode and legacy mode:
•Code Segments —The readable (R) type bit is ignored in 64-bit mode. None of the legacy type-
checks that prevent reads from or writes into code segments are performed in 64-bit mode.
•Data Segments —Data-segment type attributes are ignored in 64-bit mode. The writable (W) and
expand-down (E) type bits are ignored. All data segments are treated as writable.
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5 Page Translation and Protection
The x86 page-translation mechanism (or simply paging  mechanism) enables system software to create 
separate address spaces for each process or application. These address spaces are known as virtual-
address  spaces. System software uses the paging mechanism to selectively map individual pages of 
physical memory into the virtual-address space using a set of hierarchical address-translation tables 
known collectively as page tables .
The paging mechanism and the page tables are used to provide each process with its own private region of physical memory for storing its code and data. Processes can be protected from each other by isolating them within the virtual-address space. A process cannot access physical memory that is not mapped into its virtual-address space by system software.
System software can use the paging mechanism to selectively map physical-memory pages into 
multiple virtual-address spaces. Mapping physical pages in this manner allows them to be shared by multiple processes and applications. The physical pages can be configured by the page tables to allow read-only access. This prevents applications from altering the pages and ensures their integrity for use by all applications. 
Shared mapping is typically used to allow access of shared-library routines by multiple applications. A 
read-only copy of the library routine is mapped to each application virtual-address space, but only a single copy of the library routine is present in physical memory. This capability also allows a copy of the operating-system kernel and various device drivers to reside within the application address space. Applications are provided with efficient access to system services without requiring costly address-space switches. 
The system-software portion of the address space necessarily includes system-only data areas that 
must be protected from accesses by applications. System software uses the page tables to protect this memory by designating the pages as supervisor  pages. Such pages are only accessible by system 
software.
When the supervisor mode execution prevention (SMEP) feature is supported and enabled, attempted 
instruction fetches from user-mode accessible pages while in supervisor-mode triggers a page fault (#PF). This protects the integrity of system software by preventing the execution of instructions at a supervisor privilege level (CPL < 3) when these instructions could have been written or modified by user-mode code. 
When the supervisor mode access prevention (SMAP) feature is supported and enabled and 
RFLAGS.AC=0, some attempted explicit data accesses from user-mode accessible pages while in supervisor-mode trigger a page fault (#PF). This protects the integrity of system software by preventing the use of data at a supervisor privilege level (CPL < 3) that could have been modified by user-mode code. Supervisor software that requires access to data which is marked as user-mode accessible may temporarily suppress SMAP checks by modifying RFLAGS.AC, such as with the CLAC/STAC instructions.
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Finally, system software can use the paging mechanism to map multiple, large virtual-address spaces

Finally, system software can use the paging mechanism to map multiple, large virtual-address spaces 
into a much smaller amount of physical memory. Each application can use the entire 32-bit or 64-bit virtual-address space. System software actively maps the most-frequently-used virtual-memory pages into the available pool of physical-memory pages. The least-frequently-used virtual-memory pages are swapped out to the hard drive. This process is known as demand-paged virtual memory.
5.1 Page Translation Overview
The legacy x86 architecture provides support for translating 32-bit virtual addresses into 32-bit physical addresses (larger physical addresses, such as 36-bit or 40-bit addresses, are supported as a special mode). The AMD64 architecture enhances this support to allow translation of 64-bit virtual addresses into 52-bit physical addresses, although processor implementations can support smaller virtual-address and physical-address spaces.
Virtual addresses are translated to physical addresses through hierarchical translation tables created 
and managed by system software. Each table contains a set of entries that point to the next-lower table in the translation hierarchy. A single table at one level of the hierarchy can have hundreds of entries, each of which points to a unique table at the next-lower hierarchical level. Each lower-level table can in turn have hundreds of entries pointing to tables further down the hierarchy. The lowest-level table in the hierarchy points to the translated physical page. 
Figure 5-1 on page 128 shows an overview of the page-translation hierarchy used in long mode. 
Legacy mode paging uses a subset of this translation hierarchy (the page-map level-4 table does not 
exist in legacy mode and the PDP table may or may not be used, depending on which paging mode is enabled). The 5th level of translation, Page Map Level 5, only exists when 5-Level paging is enabled. As this figure shows, a virtual address is divided into fields, each of which is used as an offset into a translation table. The complete translation chain is made up of all table entries referenced by the virtual-address fields. The lowest-order virtual-address bits are used as the byte offset into the physical page.
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Figure 5-1. Virtual to Physical Address Translation—Long Mode
The following physical-page sizes are supported: 4 Kbytes, 2 Mbytes, 4 Mbytes, and 1 Gbytes. In long 
mode 4-Kbyte, 2-MByte, and 1-GByte sizes are available. In legacy mode 4-Kbyte, 2-MByte, and 4-MByte sizes are available.
Virtual addresses are 32 bits long, and physical addresses up to the supported physical-address size can 
be used. The AMD64 architecture enhances the legacy translation support by allowing virtual addresses of up to 64 bits long to be translated into physical addresses of up to 52 bits long. PML4E
PML5E
513-333.epsPDE
Physical
AddressPDPE
PTEPhysical Page
OffsetSign
Extension63 0
Page Directory
OffsetPage Map
Level-4 OffsetPage Map
Level-4 OffsetPage Directory
Pointer OffsetPage Table
Offset
Page Map Base Register CR364-Bit Virtual Address
Page Directory Pointer
TablePage Directory
TablePhysical Page
FramePage
TablePage Map
Level 4
Level-5 Offset
Page Map
Level 5
Table
(when 5-Level 
paging is enabled)
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Currently, the AMD64 architecture defines a mechanism for translating 48-bit virtual addresses to 52-
bit physical addresses. The mechanism used to translate a full 64-bit virtual address is reserved and will be described in a future AMD64 architectural specification.
5.1.1  Page-Translation Options
The form of page-translation support available to software depends on which paging features are 
enabled. Four controls are available for selecting the various paging alternatives:
•Page-Translation Enable (CR0.PG)
•Physical-Address Extensions (CR4.PAE)
•Page-Size Extensions (CR4.PSE)
•Long-Mode Active (EFER.LMA)
Not all paging alternatives are available in all modes. Table 5-1 summarizes the paging support 
available in each mode.
5.1.2  Page-Translation Enable (PG) Bit
Page translation is controlled by the PG bit in CR0 (bit 31). When CR0.PG is set to 1, page translation 
is enabled. When CR0.PG is cleared to 0, page translation is disabled.
The AMD64 architecture uses CR0.PG to activate and deactivate long mode when long mode is 
enabled. See “Enabling and Activating Long Mode” on page 488 for more information.
5.1.3  Physical-Address Extensions (PAE) Bit
Physical-address extensions are controlled by the PAE bit in CR4 (bit 5). When CR4.PAE is set to 1, 
physical-address extensions are enabled. When CR4.PAE is cleared to 0, physical-address extensions are disabled.Table 5-1. Supported Paging Alternatives (CR0.PG=1)
ModePhysical-
Address 
Extensions
(CR4.PAE)Page-Size 
(CR4.PSE)Page-
Directory 
Pointer OffsetPage-
Directory 
Page SizeResulting 
Physical-
Page SizeMaximum 
Virtual 
AddressMaximum 
Physical 
Address
Long Mode 
(64-bit and compatibility modes) Enabled –PDPE.PS=0PDE.PS=0 4 Kbyte
64-bit 52-bit PDE.PS=1 2 Mbyte
PDPE.PS=1 – 1 Gbyte
Legacy ModeEnabled –
PDPE.PS=0PDE.PS=0 4 Kbyte
32-bit52-bit
PDE.PS=1 2 Mbyte 52-bit
DisabledDisabled – 4 Kbyte 32-bit
EnabledPDE.PS=0 4 Kbyte 32-bit
PDE.PS=1 4 Mbyte 40-bit
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Setting CR4.PAE = 1 enables virtual addresses to be translated into physical addresses up to 52 bits 
long. This is accomplished by doubling the size of paging data-structure entries from 32 bits to 64 bits to accommodate the larger physical base-addresses for physical-pages.
PAE must be enabled before activating long mode. See “Enabling and Activating Long Mode” on 
page 488.
5.1.4  Page-Size Extensions (PSE) Bit
Page-size extensions are controlled by the PSE bit in CR4 (bit 4). Setting CR4.PSE to 1 allows 
operating-system software to use 4-Mbyte physical pages in the translation process. The 4-Mbyte physical pages can be mixed with standard 4 -Kbyte physical pages or replace them entirely. The 
selection of physical-page size is made on a page-directory-entry basis. See “Page Size (PS) Bit” on page 155 for more information on physical-page size selection. When CR4.PSE is cleared to 0, page-size extensions are disabled.
The choice of 2 Mbyte or 4 Mbyte as the large physical-page size depends on the value of CR4.PSE 
and CR4.PAE, as follows:
•If physical-address extensions are enabled (CR4.PAE=1), the large physical-page size is 2 Mbytes,
regardless of the value of CR4.PSE. 
•If physical-address extensions are disabled (CR4.PAE=0) and CR4.PSE=1, the large physical-
page size is 4 Mbytes. 
•If both CR4.PAE=0 and CR4.PSE=0, the only available page size is 4 Kbytes.
The value of CR4.PSE is ignored when long mode is active. This is because physical-address extensions must be enabled in long mode, and the only available page sizes are 4 Kbytes and 2 Mbytes.
In legacy mode, physical addresses up to 40 bits long can be translated from 32-bit virtual addresses 
using 32-bit paging data-structure entries when 4-Mbyte physical-page sizes are selected. In this special case, CR4.PSE=1 and CR4.PAE=0. See “4-Mbyte Page Translation” on page 134 for a 
description of the 4-Mbyte PDE that supports 40-bit physical-address translation. The 40-bit physical-address capability is an AMD64 architecture enhancement over the similar capability available in the legacy x86 architecture.
5.1.5  Page-Directory Page Size (PS) Bit
The page directory offset entry (PDE) and page directory pointer offset entry (PDPE) are data 
structures used in page translation (see Figure 5-1 on page 128). The page-size (PS) bit in the PDE (bit 
7, referred to as PDE.PS) selects between standard 4 -Kbyte physical-page sizes and larger (2-Mbyte or 
4-Mbyte) physical-page sizes. The page-size (also PS) bit in the PDPE (bit 7, referred to as PDPE.PS) selects between 2-Mbyte and 1-Gbyte physical-page sizes in long mode.
When PDE.PS is set to 1, large physical pages are used, and the PDE becomes the lowest level of the 
translation hierarchy. The size of the large page is determined by the values of CR4.PAE and 
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CR4.PSE, as shown in Figure 5-1 on page 129. When PDE.PS is cleared to 0, standard 4-Kbyte 
physical pages are used, and the PTE is the lowest level of the translation hierarchy.
When PDPE.PS is set to 1, 1-Gbyte physical pages are used, and the PDPE becomes the lowest level of 
the translation hierarchy. Neither the PDE nor PTE are used for 1-Gbyte paging.
5.2 Legacy-Mode Page Translation
Legacy mode supports two forms of translation:
•Normal (non-PAE) Paging —This is used when physical-address extensions are disabled
(CR4.PAE=0). Entries in the page translation table are 32 bits and are used to translate 32-bit
virtual addresses into physical addresses as large as 40 bits.
•P AE Paging —This is used when physical-address extensions are enabled (CR4.PAE=1). Entries in
the page translation table are 64 bits and are used to translate 32-bit virtual addresses into physicaladdresses as large as 52 bits.

Legacy paging uses up to three levels of page-translation tables, depending on the paging form used and the physical-page size. Entries within each table are selected using virtual-address bit fields. The legacy page-translation tables are:
•Page Table—Each page-table entry (PTE) points to a physical page. If 4-Kbyte pages are used, the
page table is the lowest level of the page-translation hierarchy. PTEs are not used when translating2-Mbyte or 4-Mbyte pages.
•Page Directory—If 4-Kbyte pages are used, each page-directory entry (PDE) points to a pagetable. If 2-Mbyte or 4 -Mbyte pages are used, a PDE is the lowest level of the page-translation
hierarchy and points to a physical page. In non-PAE paging, the page directory is the highest levelof the translation hierarchy.
•Page-Directory Pointer—Each page-directory pointer entry (PDPE) points to a page directory.Page-directory pointers are only used in PAE paging (CR4.PAE=1), and are the highest level in thelegacy page-translation hierarchy.
The translation-table-entry formats and how they are used in the various forms of legacy page translation are described beginning on page 132.
5.2.1  CR3 Register
The CR3 register is used to point to the base address of the highest-level page-translation table. The 
base address is either the page-directory pointer table or the page directory table. The CR3 register format depends on the form of paging being used. Figure 5-2 on page 132 shows the CR3 format when 
normal (non-PAE) paging is used (CR4.PAE=0). Figure 5-3 shows the CR3 format when PAE paging 
is used (CR4.PAE=1).
[AMD Public Use]Page Translation and Protection 13224593—Rev. 3.41—June 2023 AMD64 Technology
Figure 5-2. Control Register 3 (CR3)—Non-PAE Paging Legacy-Mode
Figure 5-3. Control Register 3 (CR3)—PAE Paging Legacy-Mode
The CR3 register fields for legacy-mode paging are:
Table Base Address Field.   This field points to the starting physical address of the highest-level 
page-translation table. The size of this field depends on the form of paging used:
•Normal (Non-P AE) Paging (CR4.P AE=0)—This 20-bit field occupies bits 31:12, and points to the
base address of the page-directory table. The page-directory table is aligned on a 4-Kbyteboundary, with the low-order 12 address bits 11:0 assumed to be 0. This yields a total base-addresssize of 32 bits.
•P AE Paging (CR4.P AE=1) —This field is 27 bits and occupies bits 31:5. The CR3 register points to
the base address of the page-directory-pointer table. The page-directory-pointer table is aligned ona 32-byte boundary, with the low 5 address bits 4:0 assumed to be 0.
Page-Level Writethrough (PWT) Bit.  Bit 3. Page-level writethrough indicates whether the highest-
level page-translation table has a writeback or writethrough caching policy. When PWT=0, the table has a writeback caching policy. When PWT=1, the table has a writethrough caching policy.
Page-Level Cache Disable (PCD) Bit.  Bit 4. Page-level cache disable indicates whether the highest-
level page-translation table is cacheable. When PCD=0, the table is cacheable. When PCD=1, the table is not cacheable.
Reserved Bits.  Reserved fields should be cleared to 0 by software when writing CR3.
5.2.2  Normal (Non-PAE) Paging
Non-PAE paging (CR4.PAE=0) supports 4-Kbyte and 4-Mbyte physical pages, as described in the 
following sections.
4-Kbyte Page Translation.  4-Kbyte physical-page translation is performed by dividing the 32-bit 
virtual address into three fields. Each of the upper two fields is used as an index into a two-level page-translation hierarchy. The virtual-address fields are used as follows, and are shown in Figure 5-4:
•Bits 31:22 index into the 1024-entry page-directory table.31 12 11 5 4 3 2 0
PCD
31 5 4 3 2 0
PCD
[AMD Public Use]133 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
•Bits 21:12 index into the 1024-entry page table.
•Bits 11:0 provide the byte offset into the physical page.
Figure 5-4. 4-Kbyte Non-PAE Page Translation—Legacy Mode
Figure 5-5 on page 133 shows the format of the PDE (page-directory entry), and Figure 5-6 on 
page 134 shows the format of the PTE (page-table entry). Each table occupies 4 Kbytes and can hold 
1024 of the 32-bit table entries. The fields within these table entries are described in “Page-Translation-Table Entry Fields” on page 153.
Figure 5-5 shows bit 7 cleared to 0. This bit is the page-size  bit (PS), and specifies a 4-Kbyte physical-
page translation.
Figure 5-5. 4-Kbyte PDE—Non-PAE Paging Legacy-Mode31 12 11 9 8 7 6 5 4 3 2 1 0
Page-Table Base Address A VL
IGN
0
IGN
A
PCD
PWT
U/S
R/W
PVirtual Address
Page OffsetPage-Directory
OffsetPage-Table
Offset0 11 12 21 22 31
Physical
AddressPTE
PDE10 10
3232
Page-Directory Base12 31
CR3Page-
Directory
TablePage
Table4 Kbyte
Physical 
Page12
[AMD Public Use]Page Translation and Protection 13424593—Rev. 3.41—June 2023 AMD64 Technology
Figure 5-6. 4-Kbyte PTE—Non-PAE Paging Legacy-Mode
4-Mbyte Page Translation.  4-Mbyte page translation is only supported when page-size extensions 
are enabled (CR4.PSE=1) and physical-address extensions are disabled (CR4.PAE=0).
PSE defines a page-size bit in the 32-bit PDE format (PDE.PS). This bit is used by the processor 
during page translation to support both 4-Mbyte and 4-Kbyte pages. 4-Mbyte pages are selected when PDE.PS is set to 1, and the PDE points directly to a 4-Mbyte physical page. PTEs are not used in a 4-Mbyte page translation. If PDE.PS is cleared to 0, or if 4-Mbyte page translation is disabled, the PDE points to a PTE.
4-Mbyte page translation is performed by dividing the 32-bit virtual address into two fields. Each field 
is used as an index into a single-level page-translation hierarchy. The virtual-address fields are used as follows, and are shown in Figure 5-7 on page 135:
•Bits 31:22 index into the 1024-entry page-directory table.
•Bits 21:0 provide the byte offset into the physical page.31 12 11 9 8 7 6 5 4 3 2 1 0
Physical-Page Base Address A VL
G
PA
D
A
PCD
PWT
U/S
R/W
P
[AMD Public Use]135 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 5-7. 4-Mbyte Page Translation—Non-PAE Paging Legacy-Mode
The AMD64 architecture modifies the legacy 32-bit PDE format in PSE mode to increase physical-
address size support to 40 bits. This increase in address size is accomplished by using bits 20:13 to hold eight additional high-order physical-address bits. Bit 21 is reserved and must be cleared to 0. 
Figure 5-8 shows the format of the PDE when PSE mode is enabled. The physical-page base-address 
bits are contained in a split field. The high-order, physical-page base-address bits 39:32 are located in PDE[20:13], and physical-page base-address bits 31:22 are located in PDE[31:22].
Figure 5-8. 4-Mbyte PDE—Non-PAE Paging Legacy-Mode
5.2.3  PAE Paging
PAE paging is used when physical-address extensions are enabled (CR4.PAE=1). PAE paging doubles 
the size of page-translation table entries to 64 bits so that the table entries can hold larger physical 31 22 21 20 13 12 11 9 8 7 6 5 4 3 2 1 0
Physical-Page Base Address [31:22]
0Physical-Page Base Address 
[39:32]
PATA VL
G
1
D
A
PCD
PWT
U/S
R/WPVirtual Address
Offset0 21 22 31
Physical
AddressPDE10
40
CR3Page-
Directory
Table4 Mbyte
Physical 
Page22
[AMD Public Use]Page Translation and Protection 13624593—Rev. 3.41—June 2023 AMD64 Technology
addresses (up to 52 bits). The size of each table remains 4 Kbytes, which means each table can hold 
512 of the 64-bit entries. PAE paging also introduces a third-level page-translation table, known as the page-directory-pointer table (PDPT).
The size of large pages in PAE-paging mode is 2 Mbytes rather than 4 Mbytes. PAE uses the page-
directory page-size bit (PDE.PS) to allow selection between 4-Kbyte and 2-Mbyte page sizes. PAE automatically uses the page-size bit, so the value of CR4.PSE is ignored by PAE paging. 
4-Kbyte Page Translation.  With PAE paging, 4-Kbyte physical-page translation is performed by 
dividing the 32-bit virtual address into four fields, each of the upper three fields is used as an index into a 3-level page-translation hierarchy. The virtual-address fields are described as follows and are shown in Figure 5-9:
•Bits 31:30 index into a 4-entry page-directory-pointer table.
•Bits 29:21 index into the 512-entry page-directory table.
•Bits 20:12 index into the 512-entry page table.
Figure 5-9. 4-Kbyte PAE Page Translation—Legacy Mode
Figures 5-10 through 5-12 show the legacy-mode 4 -Kbyte translation-table formats:Virtual Address
Offset0 11 12 20 21 29 30 31
Physical
PDEPDPE9 9 2
52*
52*52*
Page-Directory-Pointer Base5 31
CR3Page-
Directory-
Pointer
TablePage-
Directory
TablePage
Physical 
PagePage-Directory-
Pointer Offset
12
*This is an architectural limit. A given processor

Physical
52*
52*52*
CR3Page-
Pointer
Directory
TablePage
Physical 
12
implementation may support fewer bits.
[AMD Public Use]137 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
•Figure 5-10 shows the PDPE (page-directory-pointer entry) format.
•Figure 5-11 shows the PDE (page-directory entry) format.
•Figure 5-12 shows the PTE (page-table entry) format.
The fields within these table entries are described in “Page-Translation-Table Entry Fields” on 
page 153.
Figure 5-11 shows the PDE.PS bit cleared to 0 (bit 7), specifying a 4-Kbyte physical-page translation.
Figure 5-10. 4-Kbyte PDPE—PAE Paging Legacy-Mode 
Figure 5-11. 4-Kbyte PDE—PAE Paging Legacy-Mode 
Figure 5-12. 4-Kbyte PTE—PAE Paging Legacy-Mode 63 52 51 32
Reserved, MBZPage-Directory Base Address
31 12 11 9 8 5 4 3 2 1 0
Page-Directory Base Address A VL Reserved, MBZ
PCD
PWTMBZ
P
63 62 52 51 32NXReserved, MBZPage-Table Base Address
31 12 11 9 8 7 6 5 4 3 2 1 0
IGN
0
IGN
A
PCD
PWT
U/S
R/W
P
63 62 52 51 32NXReserved, MBZPhysical-Page Base Address
G
PAT
D
A
PCD
PWT
U/S
R/W
P
[AMD Public Use]Page Translation and Protection 13824593—Rev. 3.41—June 2023 AMD64 Technology
2-Mbyte Page Translation.  2-Mbyte page translation is performed by dividing the 32-bit virtual 
address into three fields. Each field is used as an index into a 2-level page-translation hierarchy. The 
virtual-address fields are described as follows and are shown in Figure 5-13 on page 138:
•Bits 31:30 index into the 4-entry page-directory-pointer table.
•Bits 20:0 provide the byte offset into the physical page.
Figure 5-13. 2-Mbyte PAE Page Translation—Legacy Mode
Figure 5-14 shows the format of the PDPE (page-directory-pointer entry) and Figure 5-15 on page 139 
shows the format of the PDE (page-directory entry). PTEs are not used in 2-Mbyte page translations.
Figure 5-15 on page 139 shows the PDE.PS bit set to 1 (bit 7), specifying a 2 -Mbyte physical-page 
translation.Virtual Address
Offset0 20 21 29 30 31
Physical
AddressPDEPDPE9 2
52*
52*
Page-Directory-Pointer Base Register5 31
CR3Page-
Pointer
Directory
Table2 Mbyte
Physical 
21
[AMD Public Use]139 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 5-14. 2-Mbyte PDPE—PAE Paging Legacy-Mode 
Figure 5-15. 2-Mbyte PDE—PAE Paging Legacy-Mode
5.3 Long-Mode Page Translation
Long-mode page translation requires the use of physical-address extensions (PAE). Before activating 
long mode, PAE must be enabled by setting CR4.PAE to 1. Activating long mode before enabling PAE causes a general-protection exception (#GP) to occur.
The PAE-paging data structures support mapping of 64-bit virtual addresses into 52-bit physical 
addresses. PAE expands the size of legacy page-directory entries (PDEs) and page-table entries (PTEs) from 32 bits to 64 bits, allowing physical-address sizes of greater than 32 bits. 
The AMD64 architecture enhances the page-directory-pointer entry (PDPE) by defining previously 
reserved bits for access and protection control. A new translation table is added to PAE paging, called the page-map level-4 (PML4). The PML4 table precedes the PDP table in the page-translation hierarchy. 
Because PAE is always enabled in long mode, the PS bit in the page directory entry (PDE.PS) selects 
between 4-Kbyte and 2-Mbyte page sizes, and the CR4.PSE bit is ignored. When 1-Gbyte pages are supported, the PDPE. PS bit selects the 1-Gbyte page size.
Some processors, identified by CPUID Fn0000_0007_ECX[LA57] (bit 16) = 1, support an additional 
translation table called page-map level-5 (PML5). The PML5 table precedes the PML4 table and allows translation of up to 57 bits of virtual address. 5-Level paging is enabled by setting 63 52 51 32
PCD
PWTMBZ
P
31 21 20 13 12 11 9 8 7 6 5 4 3 2 1 0
Physical-Page Base Address Reserved, MBZ
PATA VL
G
1
D
A
PCD
PWT
U/S
R/W
P
[AMD Public Use]Page Translation and Protection 14024593—Rev. 3.41—June 2023 AMD64 Technology
CR4[LA57]=1 when EFER[LMA]=1. CR4[LA57] is ignores when long mode is not active 
(EFER[LMA]=0). 
5.3.1  Canonical Address Form
The AMD64 architecture requires implementations supporting fewer than the full 64-bit virtual 
address to ensure that those addresses are in canonical form. An address is in canonical form if the address bits from the most-significant implemented bit up to bit 63 are all ones or all zeros. If the addresses of all bytes in a virtual-memory reference are not in canonical form, the processor generates a general-protection exception (#GP) or a stack fault (#SS) as appropriate. 
5.3.2  CR3
In long mode, the CR3 register is used to point to the PML4 base address when 5-Level paging is 
disabled (CR4[LA57]=0) or the PML5 base address when 5-Level paging is enabled (CR4[LA57]=1). CR3 is expanded to 64 bits in long mode, allowing the PML4 or PML5 table to be located anywhere in the 52-bit physical-address space. Figure 5-16 on page 140 shows the long-mode CR3 format.
 
Figure 5-16. Control Register 3 (CR3)—Long Mode
The CR3 register fields for long mode are:
Table Base Address Field.  Bits 51:12. When 5-Level paging is enabled (CR4.LA57=1) this 40-bit 
field points to the PML5 base address. Otherwise it points to the PML4 base address. The PML4 or PML5 table is aligned on a 4-Kbyte boundary with the low-order 12 address bits (11:0) assumed to be 0. This yields a total base-address size of 52 bits. System software running on processor implementations supporting less than the full 52-bit physical-address space must clear the unimplemented upper base-address bits to 0.63 52 51 32
Reserved, MBZPage-Map Level-4 or Level-5
Page-Map Level-4 or Level-5 Table Base AddressUsage depends on state of Processor Context ID 
11 5 4 3 2 0
PCD
PWTReserved 
CR4.PCIDE=1 Processor Context Identifier (See “Process Context 
Identifier” on page 158 for more information.) 
[AMD Public Use]141 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
level page-translation table has a writeback or writethrough caching policy. When PWT=0, the table 
has a writeback caching policy. When PWT=1, the table has a writethrough caching policy.
Process Context Identifier.  Bits 11:0. This 12-bit field determines the current Processor Context 
Identifier (PCID) when CR4.PCIDE=1.
5.3.3  4-Kbyte Page Translation
In long mode, 4-Kbyte physical-page translation is performed by dividing the virtual address into up to 
seven fields. Up to four of the fields are used as indices into the level page-translation hierarchy. The virtual-address fields are described as follows, and are shown in Figure 5-17 on page 142 (4-Kbyte 
Page Translation—Long Mode 4-Level Paging) and Figure 5-18 on page 143 (4-Kbyte Page 
Translation—Long Mode 5-Level Paging):
•Bits 63:57 are a sign extension of bit 56, as required for canonical-address forms.
•Bits 56:48 index into the 512-entry page-map level-5 table. (Only when 5-Level paging is
enabled).
•Bits 47:39 index into the 512-entry page-map level-4 table.
•Bits 38:30 index into the 512-entry page-directory pointer table.
Note: The sizes of the sign extension, PML5, and the PML4 fields depend on the number of virtualaddress bits supported by the implementation.
[AMD Public Use]Page Translation and Protection 14224593—Rev. 3.41—June 2023 AMD64 Technology
Figure 5-17. 4-Kbyte Page Translation—Long Mode 4-Level PagingVirt ual Address
0 2111 1202 0392 9383 4748 63
 Pag e- Map
Level-4 Offset
(PML4)P age-Directory
Pointer OffsetP age-Directory
OffsetP age-Table
OffsetPhysical-Page
Offset

enabled).
 Pag e- Map
Offset
9 9 9 12 9
PML4EPDPE
PDEPTE
Physical
AddressPag e
TablePag e
Directory
TablePag e
Directory
Pointer 
 Physical
Pag ePag e- Map
Level-4 
Table
52*52*52*
52*
CR3P age-Map Level-4 
Base Address12 51Sign Extend
* This is an architectural limit. A given processor
    implementation may support fewer bits.
[AMD Public Use]143 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 5-18. 4-Kbyte Page Translation—Long Mode 5-Level Paging
Figures 5-19 through 5-22 on page 144 and Figure 5-23 on page 145 show the long-mode 4 -Kbyte 
translation-table formats:
•Figure 5-19 on page 144 shows the PML5E (page-map level-5 entry) format.
•Figure 5-20 on page 144 shows the PML4E (page-map level-4 entry) format.
•Figure 5-21 on page 144 shows the PDPE (page-directory-pointer entry) format.
•Figure 5-22 on page 144 shows the PDE (page-directory entry) format.
•Figure 5-23 on page 145 shows the PTE (page-table entry) format.
page 153.
Figure 5-22 on page 144 shows the PDE.PS bit (bit 7) cleared to 0, indicating a 4-Kbyte physical-page 
S ign Ext endP age-Map
(PML5)P age-Map
OffsetPhysical-P age
Offset
9 9 9 9 1257 56
9
PML5E PML4EPDPE
PDEPTE
Physical
TablePag e
Directory
TablePag e
Directory
Pointer
 Physical
Pag eP age-Map
Level-4
TableP age-Map
Level-5
Table
52* 52*52*52*
52*
CR3P age-Map Level-5
Base Address12 51* This is an architectural limit. A given processor
    implementation may support fewer bits
[AMD Public Use]Page Translation and Protection 14424593—Rev. 3.41—June 2023 AMD64 Technology
Figure 5-19. 4-Kbyte PML5E—Long Mode
Figure 5-20. 4-Kbyte PML4E—Long Mode
Figure 5-21. 4-Kbyte PDPE—Long Mode
Figure 5-22. 4-Kbyte PDE—Long Mode63 62 52 51 32NXAvailablePage-Map Level-4 Base Address
Page-Map Level-4 Table Bse Address A VL
MBZ
MBZ
IGN
A
PCD
PWT
U/S
R/W
P
63 62 52 51 32NXAvailablePage-Directory-Pointer Base Address
Page-Directory-Pointer Base Address A VL
MBZ
MBZ
IGN
A
PCD
PWT
U/S
R/W
P
63 62 52 51 32NXAvailablePage-Directory Base Address
Page-Directory Base Address A VL
IGN
0
IGN
A
PCD
PWT
U/S
R/W
P
63 62 52 51 32NXAvailablePage-Table Base Address
IGN
0
IGN
A
PCD
PWT
U/S
R/W
P
[AMD Public Use]145 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 5-23. 4-Kbyte PTE—Long Mode
5.3.4  2-Mbyte Page Translation
In long mode, 2-Mbyte physical-page translation is performed by dividing the virtual address into up 
to six fields. Up to four of the fields are used as indices into the level page-translation hierarchy. The 
virtual-address fields are described as follows, and are shown in Figure 5-24 on page 146 (2-Mbyte 
PDE—Long Mode) and Figure 5-25 on page 147 (2-Mbyte Page Translation—Long Mode 5-Level Paging):
•Bits 63:57 are a sign extension of bit 56 as required for canonical address forms.
•Bits 56:48 index into the 512-entry page-map level-5 table (only when 5-Level paging is enabled).
•Bits 38:30 index into the 512-entry page-directory-pointer table.
•Bits 20:0 provide the byte offset into the physical page.63 62 59 58 52 51  32NX Usage depends 
on CR4.PKE 
(see below)AvailablePhysical-Page Base Address 
(This is an architectural limit. A given implementation may support fewer bits.) 
G
PAT
D
A
PCD
PWT
U/S
R/W
P
62 59 
CR4.PKE=0  Available
CR4.PKE=1Memory Protection Key (See “Memory Pro-
tection Keys (MPK) Bit” on page 164 for 
more information)
[AMD Public Use]Page Translation and Protection 14624593—Rev. 3.41—June 2023 AMD64 Technology
Figure 5-24. 2-Mbyte Page Translation—Long Mode 4-Level PagingVirtual Address
0 1202 0392 9383 4748 63
Sign ExtendPage-Map
Level-4 Table Offset
(PML4)Page-Directory
Pointer OffsetPage-Directory
OffsetPage Offset
9 9 21 9
PML4EPDPE
PDEPhysical
AddressPage
Directory
TablePage
Directory
Pointer 
 Physical
PagePage-Map
Level-4 
Table
52*52*
52*
CR3Page-Map Level-4 
[AMD Public Use]147 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 5-25. 2-Mbyte Page Translation—Long Mode 5-Level Paging
Figures 5-26 through 5-29 on page 149 show the long-mode 2 -Mbyte translation-table formats (the 
PML4 and PDPT formats are identical to those used for 4-Kbyte page translations and are repeated 
here for clarity):
•Figure 5-26 on page 148 shows the PML5E (page-map level-5 entry) format.
•Figure 5-27 on page 148 shows the PML4E (page-map level-4 entry) format.
•Figure 5-28 on page 148 shows the PDPE (page-directory-pointer entry) format.
•Figure 5-29 on page 149 shows the PDE (page-directory entry) format.
page 153. PTEs are not used in 2-Mbyte page translations.
Figure 5-29 shows the PDE.PS bit (bit 7) set to 1, indicating a 2 -Mbyte physical-page translation.Virtual Address
(PML5)Page-Map
9 9 9 2157 56
9
Directory
TablePage
Directory
Pointer 
 Physical
Level-4 
TablePage-Map
Level-5 
Table
52* 52*52*
52*
CR3Page-Map Level-5 
[AMD Public Use]Page Translation and Protection 14824593—Rev. 3.41—June 2023 AMD64 Technology
Figure 5-26. 2-Mbyte PML5E—Long Mode
Figure 5-27. 2-Mbyte PML4E—Long Mode
Figure 5-28. 2-Mbyte PDPE—Long Mode63 62 52 51 32NXAvailablePage-Map Level-4 Table Base Address
Page-Map Level-4 Table Base Address A VL
MBZ
MBZ
IGN
A
PCD
PWT
U/S
R/W
P
MBZ
MBZ
IGN
A
PCD
PWT
U/S
R/W
P
IGN
0
IGN
A
PCD
PWT
U/S
R/W
P
[AMD Public Use]149 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 5-29. 2-Mbyte PDE—Long Mode
5.3.5  1-Gbyte Page Translation
In long mode, 1-Gbyte physical-page translation is performed by dividing the virtual address into up to 
five fields. Up to three of the fields are used as indices into the level page-translation hierarchy. The virtual-address fields are described as follows, and are shown in Figure 5-30 on page 150 (1-Gbyte 
PDPE—Long Mode) and Figure 5-31 on page 151 (1-Gbyte Page Translation—Long Mode 5-Level Paging):
•Bits 56:48 index into the 512-entry page-map level-5 table. (Only when 5-Level paging is enabled)
•Bits 29:0 provide the byte offset into the physical page.63 52 51 32NX Usage depends 
on CR4.PKE 
PATA VL
G
1
D
A
PCD
PWT
U/S
R/W
P
62 59 
[AMD Public Use]Page Translation and Protection 15024593—Rev. 3.41—June 2023 AMD64 Technology
Figure 5-30. 1-Gbyte Page Translation—Long Mode 4-Level PagingVirtual Address
0 0392 933 8 4748 63
Pointer OffsetPage Offset
9 30 9
PML4EPDPE
Physical
Directory
Pointer 
Table1 Gbyte
 Physical
Level-4 
Table
52*52*
CR3Page-Map Level-4

on CR4.PKE 
PATA VL
G
1
D
A
PCD
PWT
U/S
R/W
P
62 59 
9 30 9
PML4EPDPE
Physical
Directory
Pointer 
 Physical
Level-4 
Table
52*52*
[AMD Public Use]151 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 5-31. 1-Gbyte Page Translation—Long Mode 5-Level Paging
Figure 5 -32 to Figure 5 -34 show the long mode 1 -Gbyte translation-table formats (the PML4 and 
PML5 formats are identical to the ones used for 4-Kbyte page translations and are repeated here for 
clarity):
•Figure 5-32 shows the PML5E (page-map level-5 entry) format.
•Figure 5-33 shows the PML4E (page-map level-4 entry) format.
•Figure 5-34 shows the PDPE (page-directory-pointer entry) format.
The fields within these table entries are described in Section 5.4 “Page-Translation-Table Entry 
Fields” on page 153 in the current volume. PTEs and PDEs are not used in 1-Gbyte page translations.
Figure 5-34 on page 153 shows the PDPE.PS bit (bit 7) set to 1, indicating a 1 -Gbyte physical-page 
0 0392 9383 4748 63
9 9 3057 56
9
Physical
Directory
Pointer 
 Physical
Level-4 
Level-5 
Table
52* 52*52*
[AMD Public Use]Page Translation and Protection 15224593—Rev. 3.41—June 2023 AMD64 Technology
Figure 5-32. 1-Gbyte PML5E—Long Mode
Figure 5-33. 1-Gbyte PML4E—Long Mode63 62 52 5132NXAvailablePage-Map Level-4 Table Base Address
MBZ
MBZ
IGN
A
PCD
PWT
U/S
R/W
P
63 62 52 5132NXAvailablePage Directory Pointer Base Address
MBZ
MBZ
IGN
A
PCD
PWT
US
R/W
P
[AMD Public Use]153 Page Translation and ProtectionAMD64 Technology 24593—Rev. 3.41—June 2023
Figure 5-34. 1-Gbyte PDPE—Long Mode
1-Gbyte Paging Feature Identification.  EDX bit 26 as returned by CPUID function 8000_0001h 
indicates 1-Gbyte page support. The EAX register as returned by CPUID function 8000_0019h reports 
the number of 1-Gbyte L1 TLB entries supported and EBX reports the number of 1-Gbyte L2 TLB entries. For more information using the CPUID instruction see Section 3.3 “Processor Feature Identification” on page 71.
5.4 Page-Translation-Table Entry Fields
The page-translation-table entries contain control and informational fields used in the management of the virtual-memory environment. Most fields are common across all translation table entries and modes and occupy the same bit locations. However, some fields are located in different bit positions depending on the page translation hierarchical level, and other fields have different sizes depending on which physical-page size, physical-address size, and operating mode are selected. Although these fields can differ in bit position or size, their meaning is consistent across all levels of the page translation hierarchy and in all operating modes.
5.4.1  Field Definitions
The following sections describe each field within the page-translation table entries.
Translation-Table Base Address Field.  The translation-table base-address field points to the 
physical base address of the next-lower-level table in the page-translation hierarchy. Page data-
structure tables are always aligned on 4-Kbyte boundaries, so only the address bits above bit 11 are 63 62 59 58 52 51 32NXUsage depends 
on CR4.PKE 
(see below) Available Physical Page Base Address 
31 30 12 11 9 8 7 6 5 4 3 2 1 0
Phy 
Page 
Base 
AddrReserved, MBZ
P A TA VL
G
1
D
A
PCD
PWT
U/S
R/W
P
62 59 
[AMD Public Use]Page Translation and Protection 15424593—Rev. 3.41—June 2023 AMD64 Technology
stored in the translation-table base-address field. Bits 11:0 are assumed to be 0. The size of the field 
depends on the mode:
•In normal (non-PAE) paging (CR4.PAE=0), this field specifies a 32-bit physical address.
•In PAE paging (CR4.PAE=1), this field specifies a 52-bit physical address.
52 bits correspond to the maximum physical-address size allowed by the AMD64 architecture. If a 
processor implementation supports fewer than the full 52-bit physical address, software must clear the unimplemented high-order translation-table base-address bits to 0. For example, if a processor implementation supports a 40-bit physical-address size, software must clear bits 51:40 when writing a translation-table base-address field in a page data-structure entry.
Physical-Page Base Address Field.  The physical-page base-address field points to the base 
address of the translated physical page. This field is found only in the lowest level of the page-translation hierarchy. The size of the field depends on the mode:
•In normal (non-PAE) paging (CR4.PAE=0), this field specifies a 32-bit base address for a physical
page.
•In PAE paging (CR4.PAE=1), this field specifies a 52-bit base address for a physical page.
Physical pages can be 4 Kbytes, 2 Mbytes, 4 Mbytes, or 1-Gbyte and they are always aligned on an 
address boundary corresponding to the physical-page length. For example, a 2-Mbyte physical page is always aligned on a 2-Mbyte address boundary. Because of this alignment, the low-order address bits are assumed to be 0, as follows:
•4-Kbyte pages, bits 11:0 are assumed 0.
•2-Mbyte pages, bits 20:0 are assumed 0.
•4-Mbyte pages, bits 21:0 are assumed 0.
•1-Gbyte pages, bits 29:0 are assumed 0.
Present (P) Bit.  Bit 0. This bit indicates whether the page-translation table or physical page is loaded 
in physical memory. When the P bit is cleared to 0, the table or physical page is not loaded in physical 
memory. When the P bit is set to 1, the table or physical page is loaded in physical memory. 
Software clears this bit to 0 to indicate a page table or physical page is not loaded in physical memory. 
A page-fault exception (#PF) occurs if an attempt is made to access a table or page when the P bit is 0. System software is responsible for loading the missing table or page into memory and setting the P bit to 1. 
When the P bit is 0, indicating a not-present page, all remaining bits in the page data-structure entry are 
available to software. 
Entries with P cleared to 0 are never cached in TLB nor will the processor set the Accessed or Dirty bit 
for the table entry.
Read/Write (R/W) Bit.  Bit 1. This bit controls read/write access to all physical pages mapped by the 
table entry. For example, a page-map level-4 R/W bit controls read/write access to all 128M 
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(512512512) physical pages it maps through the lower-level translation tables. When the R/W bit 
is cleared to 0, access is restricted to read-only. When the R/W bit is set to 1, both read and write access 
is allowed. See “Page-Protection Checks” on page 161 for a description of the paging read/write 
protection mechanism.
User/Supervisor (U/S) Bit.  Bit 2. This bit controls user (CPL 3) access to all physical pages mapped 
by the table entry. For example, a page-map level-4 U/S bit controls the access allowed to all 128M (512512512) physical pages it maps through the lower-level translation tables. When the U/S bit 
is cleared to 0, access is restricted to supervisor level (CPL 0, 1, 2). When the U/S bit is set to 1, both user and supervisor access is allowed. See “Page-Protection Checks” on page 161 for a description of the paging user/supervisor protection mechanism.
Page-Level Writethrough (PWT) Bit.  Bit 3. This bit indicates whether the page-translation table or 
physical page to which this entry points has a writeback or writethrough caching policy. When the PWT bit is cleared to 0, the table or physical page has a writeback caching policy. When the PWT bit is set to 1, the table or physical page has a writethrough caching policy. See “Memory Caches” on page 203 for additional information on caching.
Page-Level Cache Disable (PCD) Bit.  Bit 4. This bit indicates whether the page-translation table or 
physical page to which this entry points is cacheable. When the PCD bit is cleared to 0, the table or physical page is cacheable. When the PCD bit is set to 1, the table or physical page is not cacheable. See “Memory Caches” on page 203 for additional information on caching.
Accessed (A) Bit.  Bit 5. This bit indicates whether the page-translation table or physical page to

Accessed (A) Bit.  Bit 5. This bit indicates whether the page-translation table or physical page to 
which this entry points has been accessed. The A bit is set to 1 by the processor the first time the table or physical page is either read from or written to. The A bit is never cleared by the processor. Instead, software must clear this bit to 0 when it needs to track the frequency of table or physical-page accesses.
Dirty (D) Bit.  Bit 6. This bit is only present in the lowest level of the page-translation hierarchy. It 
indicates whether the physical page to which this entry points has been written. The D bit is set to 1 by the processor the first time there is a write to the physical page. The D bit is never cleared by the processor. Instead, software must clear this bit to 0 when it needs to track the frequency of physical-page writes.
Page Size (PS) Bit.  Bit 7. This bit is present in page-directory entries and long-mode page-directory-
pointer entries. When the PS bit is set in the page-directory-pointer entry (PDPE) or page-directory entry (PDE), that entry is the lowest level of the page-translation hierarchy. When the PS bit is cleared to 0 in all levels above PTE, the lowest level of the page-translation hierarchy is the page-table entry (PTE), and the physical-page size is 4 Kbytes. The physical-page size is determined as follows:
•If EFER.LMA=1 and PDPE.PS=1, the physical-page size is 1 Gbyte.
•If CR4.PAE=0 and PDE.PS=1, the physical-page size is 4 Mbytes. 
•If CR4.PAE=1 and PDE.PS=1, the physical-page size is 2 Mbytes.
See Table 5-1 on page 129 for a description of the relationship between the PS bit, PAE, physical-page 
sizes, and page-translation hierarchy.
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Global Page (G) Bit.  Bit 8. This bit is only present in the lowest level of the page-translation 
hierarchy. It indicates the physical page is a global page. The TLB entry for a global page (G=1) is not 
invalidated when CR3 is loaded either explicitly by a MOV CRn instruction or implicitly during a task switch. Use of the G bit requires the page-global enable bit in CR4 to be set to 1 (CR4.PGE=1). See “Global Pages” on page 158 for more information on the global-page mechanism.
Available to Software (AVL) Bit.  These bits are not interpreted by the processor and are available for 
use by system software.
Page-Attribute Table (PAT) Bit.  This bit is only present in the lowest level of the page-translation 
hierarchy, as follows:
•If the lowest level is a PTE (PDE.PS=0), PAT occupies bit 7. 
•If the lowest level is a PDE (PDE.PS=1) or PDPE (PDPE.PS=1), PAT occupies bit 12. 
The PAT bit is the high-order bit of a 3-bit index into the PAT register (Figure 7-13 on page 226). The 
other two bits involved in forming the index are the PCD and PWT bits. Not all processors support the PAT bit by implementing the PAT registers. See “Page-Attribute Table Mechanism” on page 226 for a description of the PAT mechanism and how it is used.
Memory Protection Key (MPK) Bits.  Bits 62:59. When Memory Protection Keys are enabled 
(CR4.PKE=1), this 4-bit field selects the memory protection key for the physical page mapped by this entry. Ignored if memory protection keys are disabled (CR4.PKE=0). (See “Memory Protection Keys (MPK) Bit” on page 164 for a description of this mechanism.) 
No Execute (NX) Bit.  Bit 63. This bit is present in the translation-table entries defined for PAE 
paging, with the exception that the legacy-mode PDPE does not contain this bit. This bit is not supported by non-PAE paging.
The NX bit can only be set when the no-execute page-protection feature is enabled by setting 
EFER.NXE to 1 (see “Extended Feature Enable Register (EFER)” on page 55). If EFER.NXE=0, the 
NX bit is treated as reserved. In this case, a page-fault exception (#PF) occurs if the NX bit is not cleared to 0.
This bit controls the ability to execute code from all physical pages mapped by the table entry. For 
example, a page-map level-4 NX bit controls the ability to execute code from all 128M (512512512) physical pages it maps through the lower-level translation tables. When the NX bit 
is cleared to 0, code can be executed from the mapped physical pages. When the NX bit is set to 1, code cannot be executed from the mapped physical pages. See “No Execute (NX) Bit” on page 156 for a description of the no-execute page-protection mechanism.
Reserved Bits.  Software should clear all reserved bits to 0. If the processor is in long mode, or if 
page-size and physical-address extensions are enabled in legacy mode, a page-fault exception (#PF) occurs if reserved bits are not cleared to 0. 
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5.4.2  Notes on Accessed and Dirty Bits
The processor never sets the Accessed bit or the Dirty bit for a not present page (P = 0). The ordering 
of Accessed and Dirty bit updates with respect to surrounding loads and stores is discussed below.
Accessed (A) Bit.  The Accessed bit can be set for instructions that are speculatively executed by the 
For example, the Accessed bit may be set by instructions in a mispredicted branch path even though 
those instructions are never retired. Thus, software must not assume that the TLB entry has not been cached in the TLB, just because no instruction that accessed the page was successfully retired. Nevertheless, a table entry is never cached in the TLB without its Accessed bit being set at the same time.
The processor does not order Accessed bit updates with respect to loads done by other instructions.
Dirty (D) Bit.  The Dirty bit is not updated speculatively. For instructions with multiple writes, the D 
bit may be set for any writes completed up to the point of a fault. In rare cases, the Dirty bit may be set 
even if a write was not actually performed, including MASKMOVQ with a mask of zero and certain x87 floating point instructions that cause an exception. Thus software can not assume that the page has actually been written even where PTE[D] is set to 1.
If PTE[D] is cleared to 0, software can rely on the fact that the page has not been written.In general, Dirty bit updates are ordered with respect to other loads and stores, although not 
necessarily with respect to accesses to WC memory; in particular, they may not cause WC buffers to be flushed. However, to ensure compatibility with future processors, a serializing operation should be inserted before reading the D bit.
5.5 Translation-Lookaside Buffer (TLB)
When paging is enabled, every memory access has its virtual address automatically translated into a physical address using the page-translation hierarchy. Translation-lookaside buffers  (TLBs), also 
known as page-translation caches , nearly eliminate the performance penalty associated with page 
translation. TLBs are special on-chip caches that hold the most-recently used virtual-to-physical address translations. Each memory reference (instruction and data) is checked by the TLB. If the translation is present in the TLB, it is immediately provided to the processor, thus avoiding external memory references for accessing page tables.
TLBs take advantage of the principle of locality. That is, if a memory address is referenced, it is likely 
that nearby memory addresses will be referenced in the near future. In the context of paging, the 
proximity of memory addresses required for locality can be broad—it is equal to the page size. Thus, it is possible for a large number of addresses to be translated by a small number of page translations. This high degree of locality means that almost all translations are performed using the on-chip TLBs.
System software is responsible for managing the TLBs when updates are made to the linear-to-
physical mapping of addresses. A change to any paging data-structure entry is not automatically 
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reflected in the TLB, and hardware snooping of TLBs during memory-reference cycles is not 
performed. Software must invalidate the TLB entry of a modified translation-table entry so that the change is reflected in subsequent address translations. TLB invalidation is described in “TLB Management” on page 159. Only privileged software running at CPL=0 can manage the TLBs. 
5.5.1  Process Context Identifier
The Process Context Identifier (PCID) feature allows a logical processor to cache TLB mappings 
concurrently for multiple virtual address spaces. When enabled (by setting CR4.PCIDE=1), the processor associates the current 12-bit PCID with each TLB mapping it creates. Only entries matching the current PCID are used when performing address translations. In this way, the processor may retain cached TLB mappings for multiple contexts.
The current PCID is the value in CR3[11:0]. When PCIDs are enabled the system software can store

The current PCID is the value in CR3[11:0]. When PCIDs are enabled the system software can store 
12-bit Process Context Identifiers in CR3 for different address spaces. Subsequently, when system software switches address spaces (by writing the page table base pointer in CR3[62:12]), the processor may use TLB mappings previously stored for that address space and PCID, providing that bit 63 of the source operand is set to 1. If bit 63 is set to 0, the legacy behavior of a move to CR3 is maintained, invalidating TLB entries but only non-global entries for the specified PCID. Note that this bit is not stored in the CR3 register itself. PCID-tagged TLB contents may also be managed using the INVPCID instruction; see the INVPCID description in volume 3 for details. A MOV to CR4 that clears CR4.PCIDE causes all cached entries in the TLB for the logical processor to be invalidated. When PCIDs are not enabled (CR4.PCIDE=0) the current PCID is always zero and all TLB mappings are associated with PCID=0.
 Attempting to set CR4.PCIDE with a MOV to CR4 if EFER.LMA = 0 or CR3[11:0] <> 0 causes a 
#GP exception. Attempting to clear CR0.PG with a MOV to CR0 if CR4.PCIDE is set also causes a #GP exception. The presence of PCID functionality is indicated by CPUID Function 1, ECX[PCID]=1.
5.5.2  Global Pages
The processor invalidates the TLB whenever CR3 is loaded either explicitly or implicitly. After the 
TLB is invalidated, subsequent address references can consume many clock cycles until their translations are cached as new entries in the TLB. Invalidation of TLB entries for frequently-used or critical pages can be avoided by specifying the translations for those pages as global. TLB entries for 
global pages are not invalidated as a result of a CR3 load. Global pages are invalidated using the INVLPG instruction.
Global-page extensions are controlled by setting and clearing the PGE bit in CR4 (bit 7). When 
CR4.PGE is set to 1, global-page extensions are enabled. When CR4.PGE is cleared to 0, global-page extensions are disabled. When CR4.PGE=1, setting the global (G) bit in the translation-table entry marks the page as global.
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The INVLPG instruction ignores the G bit and can be used to invalidate individual global-page entries 
in the TLB. To invalidate all entries, including global-page entries, disable global-page extensions (CR4.PGE=0).
5.5.3  TLB Management
Generally, unless system software modifies the linear-to-physical address mapping, the processor 
manages the TLB transparently to software. This includes allocating entries and replacing old entries with new entries. In general, software changes made to paging-data structures are not automatically reflected in the TLB. In these situations, it is necessary for software to invalidate TLB entries so that these changes will be propagated to the page-translation mechanism.
TLB entries can be explicitly invalidated using operations intended for that purpose or implicitly 
invalidated as a result of another operation. TLB invalidation has no effect on the associated page-translation tables in memory.
Explicit Invalidations.  Several mechanisms are provided to explicitly invalidate the TLB:
•The Invalidate TLB Entry instruction (INVLPG) can be used to invalidate a specific entry within
the TLB. This instruction invalidates an entry regardless of whether it is marked as global or not.
•The Invalidate TLB entry in a Specified ASID  instruction (INVLPGA) operates similarly, but
operates only on entries associated with the specified ASID. See “Invalidate Page, AlternateASID” on page 529.
•The Invalidate TLB with Broadcast instruction (INVLPGB) can be used to invalidate a specified
range of TLB entries on the local processor and broadcast the invalidation operation to remoteprocessors. See INVLPGB in V olume 3.
•The Invalidate TLB entries in Specified PCID  instruction (INVPCID) can be used to invalidate
TLB entries of the specified Processor Context ID. See INVPCID in V olume 3.
•Updates to the CR3 register cause the entire TLB to be invalidated except for global pages. The
CR3 register can be updated with the MOV CR3 instruction. CR3 is also updated during a taskswitch, with the updated CR3 value read from the TSS of the new task. This behavior for CR3 ismodified by the PCID extension; See “Process Context Identifier” on page 158 for details.
•The TLB_CONTROL field of a VMCB can request specific flushes of the TLB to occur when theVMRUN instruction is executed on that VMCB. See “TLB Flush” on page 528.
Implicit Invalidations.  The following operations cause the entire TLB to be invalidated, including 
global pages:
•Modifying the CR0.PG bit (paging enable).
•Modifying the CR4.PAE bit (physical-address extensions), the CR4.PSE bit (page-size
extensions), or the CR4.PGE bit (page-global enable).
•Entering SMM as a result of an SMI interrupt.
•Executing the RSM instruction to return from SMM.
•Updating a memory-type range register (MTRR) with the WRMSR instruction.
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•External initialization of the processor.
•External masking of the A20 address bit (asserting the A20M# input signal).
•Writes to certain model-specific registers with the WRMSR instruction; see the BIOS and Kernel
Developer’s Guide (BKDG) or Processor Programming Reference Manual  applicable to your
product for more information.
•A MOV to CR4 that changes CR4.PKE from 0 to 1.
•A MOV to CR4 that clears CR4.PCIDE from 1 to 0.
Invalidation of Table Entry Upgrades.  If a table entry is updated to remove a page access 
constraint, such as removing supervisor, read-only, and/or no-execute restrictions, an invalidation is 
not required because the hardware will automatically detect the changes. If a table entry is updated and does not remove a permission violation, it is unpredictable whether the old or updated entry will be used until an invalidation is performed.
Speculative Caching of Address Translations.  For performance reasons, AMD64 processors may 
speculatively load valid address translations into the TLB on false execution paths. Such translations are not based on references that a program makes from an “architectural state” perspective, but which the processor may make in speculatively following an instruction path which turns out to be mispredicted. In general, the processor may create a TLB entry for any linear address for which valid entries exist in the page table structure currently pointed to by CR3. This may occur for both instruction fetches and data references. Such entries remain cached in the TLBs and may be used in subsequent translations. Loading a translation speculatively will set the Accessed bit, if not already set. A translation will not be loaded speculatively if the Dirty bit needs to be set.
Caching of Upper Level Translation Table Entries.  Similarly, to improve the performance of table 
walks on TLB misses, AMD64 processors may save upper level translation table entries in special table walk caching structures which are kept coherent with the tables in memory via the same mechanisms as the TLBs—by means of the INVLPG instruction, moves to CR3, and modification of paging control bits in CR0 and CR4. Like address translations in the TLB, these upper level entries may also be cached speculatively and by false-path execution. These entries are never cached if their P (present) bits are set to 0. 
Under certain circumstances, an upper-level table entry that cannot ultimately lead to a valid 
translation (because there are no valid entries in the lower level table to which it points) may also be cached. This can happen while executing down a false path, when an in-progress table walk gets cancelled by the branch mispredict before the low level table entry that would cause a fault is encountered. Said another way, the fact that a page table has no valid entries does not guarantee that upper level table entries won't be accessed and cached in the processor, as long as those upper level entries are marked as present. For this reason, it is not safe to modify an upper level entry, even if no valid lower-level entries exist, without first clearing its present bit, followed by an INVLPG instruction. 
Use of Cached Entries When Reporting a Page Fault Exception.  On current AMD64 
processors, when any type of page fault exception is encountered by the MMU, any cached upper-
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level entries that lead to the faulting entry are flushed (along with the TLB entry, if already cached) and

level entries that lead to the faulting entry are flushed (along with the TLB entry, if already cached) and 
the table walk is repeated to confirm the page fault using the table entries in memory. This is done because a table entry is allowed to be upgraded (by marking it as present, or by removing its write, execute or supervisor restrictions) without explicitly maintaining TLB coherency. Such an upgrade will be found when the table is re-walked, which resolves the fault. If the fault is confirmed on the re-walk however, a page fault exception is reported, and upper level entries that may have been cached on the re-walk are flushed. 
Handling of D-Bit Updates.  When the processor needs to set the D bit in the PTE for a TLB entry 
that is already marked as writable at all cached TLB levels, the table walk that is performed to access the PTE in memory may use cached upper level table entries. This differs from the fault situation previously described, in which cached entries aren’t used to confirm the fault during the table walk. 
Invalidation of Cached Upper-level Entries by INVLPG.  The effect of INVLPG on TLB caching 
of upper-level page table entries is controlled by EFER[TCE] on processors that support the translation cache extension feature. If EFER[TCE] is 0, or if the processor does not support the translation cache extension feature, an INVLPG will flush all upper-level page table entries in the TLB as well as the target PTE. If EFER[TCE] is 1, INVLPG will flush only those upper-level entries that lead to the target PTE, along with the target PTE itself. INVLPGA may flush all upper-level entries regardless of the state of TCE. For further details, see Section 3.1.7 “Extended Feature Enable Register (EFER)” on page 55.
Handling of PDPT Entries in PAE Mode.  When 32-bit PAE mode is enabled on AMD64 processors 
(CR4.PAE is set to 1) a third level of the address translation table hierarchy, the page directory pointer table (PDPT), is enabled. This table contains four entries. On older AMD64 processors, in native mode, these four entries are unconditionally loaded into the table walk cache whenever CR3 is written with the PDPT base address, and remain locked in. At this point they are also checked for reserved bit violations, and if such violations are present a general-protection exception (#GP) occurs.
Under SVM, however, when the processor is in guest mode with PAE enabled, the guest PDPT entries 
are not cached or validated at this point, but instead are loaded and checked on demand in the normal course of address translation, just like page directory and page table entries. Any reserved bit violations are detected at the point of use, and result in a page-fault (#PF) exception rather than a 
general-protection (#GP) exception. The cached PDPT entries are subject to displacement from the table walk cache and reloading from the PDPT, hence software must assume that the PDPT entries may be read by the processor at any point while those tables are active. Modern AMD processors implement this same behavior in native mode as well, rather than pre-loading the PDPT entries. 
5.6 Page-Protection Checks
The AMD64 architecture provides the following forms of page-level memory protection: 
•Supervisor pages. This form of protection prevents non-privileged (user) code from accessing
privileged (supervisor) code and data.
•Read-only pages. This form of protection prevents writes into read-only address spaces.
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•Instruction fetch restrictions. Two forms of page-level memory protection prevent the processor
from fetching instructions from pages that are either known to contain non-executable data or thatare accessible by user-mode code. 
•Memory protection keys. This form of protection allows an application to manage page-based dataaccess protections from user mode.
•Shadow stack pages. The processor restricts the types of memory accesses that are allowed to reador write a shadow stack page and prohibits the shadow stack mechanism from accessing non-shadow stack pages. See “Shadow Stack Protection” on page 165.
Access protection checks are performed when a virtual address is translated into a physical address. For those checks, the processor examines the page-level memory-protection bits in the translation tables to determine if the access is allowed. The page table bits involved in these checks are:
•User/Supervisor (U/S)—See “User/Supervisor (U/S) Bit” on page 155.
•Read/Write (R/W)—See “Read/Write (R/W) Bit” on page 154.
•No-Execute (NX)—See “No Execute (NX) Bit” on page 156.
•Memory Protection Key (MPK)—See 
“Memory Protection Keys (MPK) Bit” on page 164.
Access protection actions taken by the processor are controlled by the following bits:•Write-Protect enable (CR0.WP)—See “Write Protect (WP) Bit” on page 43.
•No-Execute Enable (EFER.NXE)—See “No-Execute Enable (NXE) Bit” on page 57.
•Supervisor-mode Execution Prevention enable (CR4.SMEP)—See “Supervisor Mode Execution
Prevention (SMEP)” on page 50.
•Supervisor-mode Access Prevention enable (CR4.SMAP)—See “Supervisor-Mode AccessPrevention(CR4.SMAP) Bit” on page 164.
•Alignment Check Bit (RFLAGS.AC) – See ““Alignment Check (AC) Bit” on page 54.
•Protection Key Enable (CR4.PKE)—See “Protected-Mode Enable (PE) Bit” on page 42.
•Control-flow Enforcement Technology (CR4.CET) - See “CR4 Register” on page 46.
These protection checks are available at all levels of the page-translation hierarchy.
5.6.1  User/Supervisor (U/S) Bit
The U/S bit in the page-translation tables determines the privilege level required to access the page. If 
U/S=0 in any of the page table entries traversed during a table walk, the page is considered a supervisor page. If U/S=1 in all the page table entries traversed during a table walk, the page is considered a user page. Conceptually, user (non-privileged) pages correspond to a current privilege-level (CPL) of 3, or least-privileged. Supervisor (privileged) pages correspond to a CPL of 0, 1, or 2, all of which are jointly regarded as most-privileged.
When the processor is running at a CPL of 0, 1, or 2, it can access both user and supervisor pages 
unless restricted by SMEP or SMAP (See sections “Supervisor-Mode Execution Prevention (CR4.SMEP) Bit” on page 163 and “Supervisor-Mode Access Prevention(CR4.SMAP) Bit” on 
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page 164 for further details). However, when the processor is running at a CPL of 3, it can only access 
user pages. If an attempt is made to access a supervisor page while the processor is running at CPL = 3, a page-fault exception (#PF) occurs.
See “Privilege-Level Concept” on page 105 for more information on processor privilege levels.
5.6.2  Read/Write (R/W) Bit
The R/W bit in the page-translation tables specifies the access type allowed for the page. If R/W=0 in 
any of the page table entries traversed during a table walk, the page is read-only. If R/W=1 in all the page table entries traversed during a table walk, the page is read/write. A page-fault exception (#PF) occurs if an attempt is made by user software to write to a read-only page. If supervisor software attempts to write a read-only page, the outcome depends on the value of the CR0.WP bit (described below).
5.6.3  No Execute (NX) Bit
The NX bit provides the ability to mark a page as non-executable. If the NX bit is set at any level of the 
page-table hierarchy in the table entries traversed during a table walk, the page mapped by those entries is a no-execute page. When no-execute protection is enabled, any attempt to fetch an instruction from a no-execute page results in a page-fault exception (#PF).
The no-execute protection check applies to all privilege levels. It does not distinguish between 
supervisor and user-level accesses.
The no-execute protection feature is supported only in PAE-paging mode. In 32-bit PAE mode, the NX 
bit is not supported at the Page Directory Pointer table level. In this mode, the value of the NX bit at the PDP level defaults to 0. 
No-execute protection is enabled by setting the NXE bit in the EFER register to 1. Before setting this 
bit, system software must verify the processor supports the no-execute feature by checking the CPUID NX feature flag (CPUID Fn8000_0001_EDX[NX]). 
5.6.4  Write Protect (CR0.WP) Bit
The ability to write to read-only pages is governed by the processor mode and whether write protection 
is enabled. If write protection is not enabled, a processor running at CPL 0, 1, or 2 can write to any 
physical page, even if it is marked as read-only. Enabling write protection by setting the WP bit in CR0 prevents supervisor code from writing into read-only pages, including read-only user-level pages.
A page-fault exception (#PF) occurs if software attempts to write (at any privilege level) into a read-
only page while write protection is enabled.
5.6.5  Supervisor-Mode Execution Prevention (CR4.SMEP) Bit
When supported and enabled, a page-fault exception (#PF) is generated if the processor attempts to 
fetch an instruction from a user page while running at CPL 0, 1, or 2.
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Supervisor-mode execution prevention is enabled by setting the SMEP bit (bit 20) in the CR4 register 
to 1. Before setting this bit, system software must verify the processor supports the SMEP feature by checking the SMEP feature flag (CPUID Fn0000_0007_EBX[SMEP]_x0 = 1). 
For more information using the CPUID instruction see Section 3.3 “Processor Feature Identification” 
on page 71.

on page 71.
5.6.6  Supervisor-Mode Access Prevention(CR4.SMAP) Bit
When SMAP is supported and enabled, a page-fault exception (#PF) is generated if the processor 
attempts to read or write data from a user page and one of the following is true: 
•The access is an implicit supervisor-mode access OR 
•The access is made while running at CPL 0,1, or 2 and RFLAGS.AC=0. 
Some accesses are considered implicit supervisor-mode accesses. Implicit supervisor-mode accesses 
are subject to the SMAP check regardless of the value of RFLAGS.AC. An implicit supervisor-mode access is one that is considered a supervisor access regardless of the value of CPL.
Supervisor-mode access prevention is enabled by setting the SMAP bit (bit 21) in the CR4 register to 
1. Before setting this bit, system software must verify the processor supports the SMAP feature by checking the SMAP feature flag CPUID Fn0000_0007_EBX[SMAP]_x0 (bit 20) = 1.
Shadow stack accesses are not subject to the SMAP check. For more information on using the CPUID instruction see “Processor Feature Identification” on 
page 71.
5.6.7  Memory Protection Keys (MPK) Bit
The Memory Protection Key (MPK) feature provides a way for applications to impose page-based 
data access protections (read/write, read-only or no access), without requiring modification of page tables and subsequent TLB invalidations when the application changes protection domains.
When MPK is enabled (CR4.PKE=1), a protection key is located in bits 62:59 of final page table entry 
mapping each virtual address. This 4-bit protection key is used as an index (i) into the user-accessible PKRU register which contains 16 access-disable/write-disable (WDi/ADi) pairs. 
Figure 5-35. PKRU Register
The WDi/ADi pairs operate as follows:31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PK15 PK14 PK13 PK12 PK11 PK10 PK9 PK8 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0
W
DA
DW
DADW
DADW
DADW
DADW
DADW
DADW
DADW
DADW
DADW
DADW
DADW
DADW
DADW
DADW
DAD
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If ADi=0, data access is permitted
•If ADi=1, no data access is permitted (regardless of CPL)
•If WDi == 0, write access is allowed
•If WDi == 1: User-mode write access is not allowed. Supervisor access is controlled by CR0.WP:
•If CR0.WP=1, supervisor-mode writes are not allowed 
•If CR0.WP=0, supervisor-mode writes are allowed
Software can use the RDPKRU and WRPKRU instructions to read and write the PKRU register. These 
instructions are not privileged and can be used in user mode or in supervisor mode. 
The MPK mechanism is ignored in the following cases:
•if CR4.PKE=0 
•if long mode is disabled (EFER.LMA=0)
•for instruction fetches 
•for pages marked in the paging structures as supervisor addresses (U/S=0)
5.7 Shadow Stack Protection
When the shadow stack feature is enabled (CR4.CET=1), certain combinations of page-table 
protection bits are used to distinguish pages containing shadow stacks from ordinary pages. As described in the following sections, the processor restricts the types of memory accesses that can be made to shadow stack pages and prohibits the shadow stack mechanism from accessing non-shadow stack pages. (See “Shadow Stacks” on page 671 for details on the shadow stack feature).
5.7.1  Shadow Stack Accesses
The processor treats certain memory accesses as shadow stack accesses. Shadow stack accesses are 
generated only by the shadow stack instructions or by the shadow stack mechanism. As with ordinary data accesses, a shadow stack access can be either a supervisor access or a user access, depending on the CPL when the access is made. Shadow stack accesses made when the processor is at CPL 0, 1, or 2 are supervisor-shadow stack accesses, and accesses made at CPL 3 are user-shadow stack accesses. (An exception is the WRUSS instruction, whose accesses are always treated as user-shadow stack accesses).
5.7.2  Shadow Stack Pages
Shadow stack accesses are allowed only to linear addresses that are mapped to shadow stack pages. A 
shadow stack is described by the following combination of page-table protection bits:
•R/W(Read/Write)=0 and D(Dirty)=1 in the final page-table entry that maps the linear address. 
•R/W(Read/Write)=1 in all other page-mapping structures leading to the final page-table entry.
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The U/S (User/Supervisor) bit in the page-translation tables determines the privilege level required to 
access a given shadow stack page. If U/S=0, the page is considered a supervisor-shadow stack page and if U/S=1 the page is considered a user-shadow stack page.
5.7.3  Shadow Stack Protection Checks
The processor restricts the types of memory accesses that are allowed to read or write a shadow stack 
page. The page-level protection bits and the type of memory access are examined to determine if the access is allowed. The following section assumes the memory protection key field allows access to the given page, if memory protection keys are enabled, and that CR0.WP=1 (which is prerequisite for enabling the shadow stack feature).
The following memory accesses are allowed to shadow stack pages:
•User-shadow stack accesses can read or write user-shadow stack pages,
•Supervisor-shadow stack accesses can read or write supervisor-shadow stack pages. 
(Note : shadow stack write accesses are allowed to complete, even though the R/W bit is 0).
•Non-shadow stack reads can read any shadow stack page (subject to U/S page protections). 
The following memory accesses are not allowed:•User-shadow stack access to supervisor-shadow stack pages.
•Supervisor-shadow stack access to user-shadow stack pages.
•Any shadow stack access to a non-shadow stack page. 
•Non-shadow stack writes to a shadow stack page.
If the memory access is not allowed, a page-fault exception (#PF) is generated with the paging-
protection violation bits (user/supervisor, read/write, or both) set in the error code as appropriate. The SS bit is set in the #PF error code if the page-fault was caused by a shadow stack access. (See “Page-Fault Error Code” on page 262).
5.8 Protection Across Paging Hierarchy
The privilege level and access type specified at each level of the page-translation hierarchy have a combined effect on the protection of the translated physical page. Enabling and disabling write protection via CR0.WP further qualifies the protection effect on the physical page.
Table 5-2 shows the overall effect that privilege level and access type have on physical-page 
protection when write protection is disabled (CR0.WP=0). In this case, when any translation-table 
entry is specified as supervisor level, the physical page is a supervisor page and can only be accessed by software running at CPL 0, 1, or 2. Such a page allows read/write access even if all levels of the page-translation hierarchy specify read-only access.
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If all table entries in the translation hierarchy are specified as user level the physical page is a user 
page, and both supervisor and user software can access it. In this case the physical page is read-only if 
any table entry in the translation hierarchy specifies read-only access. All table entries in the translation hierarchy must specify read/write access for the physical page to be read/write.
Table 5-3 shows the overall effect that privilege level and access type have on physical-page access 
when write protection is enabled (CR0.WP=1). When any translation-table entry is specified as supervisor level, the physical page is a supervisor page and can only be accessed by supervisor software. In this case, the physical page is read-only if any table entry in the translation hierarchy specifies read-only access. All table entries in the translation hierarchy must specify read/write access for the supervisor page to be read/write.Table 5-2. Physical-Page Protection, CR0.WP=0
Page-Map Level-4 
EntryPage-Directory-
Pointer EntryPage-Directory 
EntryPage-Table EntryEffective Result on 
Physical Page
U/S R/W U/S R/W U/S R/W U/S R/W U/S R/W
S — — — — — — —
S R/W— — S — — — — —
— — — — S — — —— — — — — — S —
U R U — U — U —
U R
1U — U R U — U —U — U — U R U —U — U — U — U RU R/W U R/W U R/W U R/W U R/W
Note:
S = Supervisor Level (CPL=0, 1, or 2), U = User Level (CPL = 3), R = Read-Only Access, R/W = Read/Write Access, — = Don’t
Care.
Note:
1. Supervisor-level programs can access these pages as R/W.
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5.8.1  Access to User Pages when CR0.WP=1
As shown in Table 5-2 on page 167, read/write access to user-level pages behaves the same as when 
write protection is disabled (CR0.WP=0), with one critical difference. When write protection is enabled, supervisor programs cannot write into read-only user pages.
5.9 Effects of Segment Protection

S — — — — — — —
U R U — U — U —
U R
Note:
Care.
Note:
Segment-protection and page-protection checks are performed serially by the processor, with segment-privilege checks performed first, followed by page-protection checks. Page-protection checks are not performed if a segment-protection violation is found. If a violation is found during either segment-protection or page-protection checking, an exception occurs and no memory access is performed. Segment-protection violations cause either a general-protection exception (#GP) or a stack exception (#SS) to occur. Page-protection violations cause a page-fault exception (#PF) to occur.
5.10 Upper Address Ignore 
The Upper Address Ignore feature provides a way for software to use bits 63:57 of an address as an arbitrary software-assigned and software-interpreted tag. When this feature is enabled, these address bits are excluded from the canonicality check that’s done when the address is used for certain memory references.
5.10.1  Detecting and Enabling Upper Address Ignore
Support for the Upper Address Ignore feature is indicated by CPUID 
Fn8000_0021_EAX[UpperAddressIgnore](bit 7)=1. The Upper Address Ignore feature is enabled by setting EFER.UAIE (bit 20) in 64-bit mode (EFER.LMA=CS.L=1). EFER.UAIE is ignored outside of 64-bit mode. Table 5-3. Effect of CR0.WP=1 on Supervisor Page Access
Page-Map
Level-4
EntryPage
Pointer
EntryPage Directory 
EntryPage Table 
EntryPhysical Page
R/W R/W R/W R/W R/W
R — — —
R— R — —
— — R —
— — — R
W W W W W
Note:
R = Read-Only Access Type, W = Read/Write Access Type, — = Don’t Care.
Physical page is in supervisor mode, as determined by U/S settings in Table 5 -2.
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5.10.2  Upper Address Ignore Operation
When Upper Address Ignore is active the processor no longer performs a canonical address check on 
bits 63:57 of the logical address for memory references that use either the DS or ES segment, it checks only bits 56:48 of the logical address when 4-level paging is enabled. No canonical checks are performed for ES or DS segment memory references when 5-level paging is enabled. For a description of 4-level and 5-level paging see Section 5.3 “Long-Mode Page Translation” on page 139.
Any memory reference made using the segment registers CS, SS, FS or GS still performs the normal 
canonical address check. This includes indirect jump, call, and return target addresses since they are CS based. Canonical checks for implicit references to IDT, GDT, LDT and TSS are not suppressed when Upper Address Ignore is active. 
5.10.3  Address Tag Storage
The following registers, which hold virtual addresses for communication to software, are not 
guaranteed to hold the address tag in the upper 7 bits:
•CR2
•x87 DP
•IBS Data Cache Linear Address Register
5.10.4  Debug Breakpoint Behavior with Upper Address Ignore
The Debug Breakpoint Address Registers (DR0-3) hold full 64-bit addresses and Upper Address 
Ignore changes how the address match is performed for data address breakpoints. When Upper Address Ignore is active the value in DR0-3[63:57] is ignored and the linear address of the memory access is only compared against DR0-3[56:0]. 
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6 System Instructions
System instructions provide control over the resources used to manage the processor operating 
environment. This includes memory management, memory protection, task management, interrupt and exception handling, system-management mode, software debug and performance analysis, and model-specific features. Most instructions used to access these resources are privileged and can only be executed while the processor is running at CPL=0, although some instructions can be executed at any privilege level.
Table 6-1 summarizes the instructions used for system management. These include all privileged 
instructions, instructions whose privilege requirement is under the control of system software, non-privileged instructions that are used primarily by system software, and instructions used to transfer control to system software. Most of the instructions listed in Table 6-1 are summarized in this chapter, although a few are introduced elsewhere in this manual, as indicated in the Reference column of 
Table 6-1. 
For details on individual system instructions, see “System Instruction Reference” in V olume 3.
Table 6-1. System Management Instructions
Mnemonic NamePrivilege
ReferenceCPL=0 O/S1 Any
ARPL Adjust Requestor Privilege Level X“Adjusting Access Rights” on 
page 181
CLAC Clear Alignment Check Flag X“CLAC and STAC Instructions” on page 178 
CLGI Clear Global Interrupt Flag X“Global Interrupt Flag, STGI and CLGI Instructions” on page 529
CLI Clear Interrupt Flag X“CLI and STI Instructions” on page 178
CLRSSBSY Clear Shadow Stack Busy X “CLRSSBSY” on page 182
CLTS Clear Task-Switched Flag in CR0 X “CLTS Instruction” on page 178
HLT Halt X “Processor Halt” on page 181
INCSSP Increment SSP X “INCSSP” on page 182
INT3 Interrupt to Debug Vector X“Breakpoint Instruction (INT3)” on page 407
INVD Invalidate Caches X “Cache Management” on page 181
INVLPG Invalidate TLB Entry X “INVLPG Instruction” on page 182
INVLPGAInvalidate TLB Entry in a Specified ASIDX“Invalidate Page, Alternate ASID” on page 529
Note:
1. The operating system controls the privilege required to use the instruction.
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INVLPGBInvalidate TLB Entries with 
Broadcast X“INVLPGB Instruction” on page 182
INVPCID Invalidate TLB Entries in Specified Processor Context X  “INVPCID Instruction” on page 182
IRET x Interrupt Return (all forms) X“Returning From Interrupt Procedures” on page 276
LAR Load Access-Rights Byte X“Checking Access Rights” on page 180
LGDTLoad Global-Descriptor-Table RegisterX“LGDT and LIDT Instructions” on page 179LIDTLoad Interrupt-Descriptor-Table RegisterX
LLDTLoad Local-Descriptor-Table RegisterX“LLDT and LTR Instructions” on page 180
LMSW Load Machine-Status Word X“LMSW and SMSW Instructions” on page 177
LSL Load Segment Limit X“Checking Segment Limits” on page 180
LTR Load Task Register X“LLDT and LTR Instructions” on page 180
MONITOR Setup Monitor Address X --
MOV CR n Move to/from Control Registers X“MOV CRn Instructions” on page 177
MOV DR n Move to/from Debug Registers X“Accessing Debug Registers” on page 178
MWAIT Monitor Wait X --
RDFSBASE Read FS Base Address X “RDFSBASE, RDGSBASE, 
WRFSBASE, and WRGSBASE Instructions” on page 179RDGSBASE Read GS Base Address X
RDMSR Read Model-Specific Register X“RDMSR and WRMSR Instructions” on page 178
RDPMC Read Performance-Monitor Counter X “RDPMC Instruction” on page 178
RDSSP Read SSP X “RDSSP” on page 182
RDTSC Read Time-Stamp Counter X “RDTSC Instruction” on page 178
RDTSCPRead Time-Stamp Counter and Processor IDX “RDTSCP Instruction” on page 179
RSMReturn from System-Management ModeX “Leaving SMM” on page 339Table 6-1. System Management Instructions (continued)
Note:
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RSTORSSP Restore SSP X “RSTORSSP” on page 182
SA VEPREVSS
PSave Previous SSP X “SA VEPREVSSP” on page 182
SETSSBSY Set Shadow Stack Busy X “SETSSBSY” on page 182
SGDTStore Global-Descriptor-Table RegisterX“SGDT and SIDT Instructions” on page 180SIDTStore Interrupt-Descriptor-Table RegisterX
SKINITSecure Init and Jump with AttestationX “Security” on page 556
SLDTStore Local-Descriptor-Table RegisterX“SLDT and STR Instructions” on page 180
SMSW Store Machine-Status Word X“LMSW and SMSW Instructions” on page 177
STAC Set Alignment Check Flag X“CLAC and STAC Instructions” on page 178
STI Set Interrupt Flag X“CLI and STI Instructions” on page 178
STGI Set Global Interrupt Flag X“Global Interrupt Flag, STGI and CLGI Instructions” on page 529
STR Store Task Register X“SLDT and STR Instructions” on page 180
SWAPGSSwap GS and KernelGSbase RegistersX“SWAPGS Instruction” on page 176
SYSCALL Fast System Call X“SYSCALL and SYSRET” on page 174
SYSENTER System Call X “SYSENTER and SYSEXIT (Legacy Mode Only)” on page 176 SYSEXIT System Return X
SYSRET Fast System Return X“SYSCALL and SYSRET” on page 174 
VERR Verify Segment for Reads X “Checking Read/Write Rights” on page 180 VERW Verify Segment for Writes X
VMLOAD Load State from VMCB X“VMSA VE and VMLOAD Instructions” on page 505
VMMCALL Call VMM X“VMMCALL Instruction” on page 530
VMRUN Run Virtual Machine X “VMRUN Instruction” on page 500Table 6-1. System Management Instructions (continued)
Note:
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The following instructions are summarized in this chapter but are not categorized as system

Note:
The following instructions are summarized in this chapter but are not categorized as system 
instructions, because of their importance to application programming:
•The CPUID instruction returns information critical to system software in initializing the operating
environment. It is fully described in Section 3.3, “Processor Feature Identification,” on page 71.
•The PUSHF and POPF instructions set and clear certain rFLAGS bits depending on the processoroperating mode and privilege level. These dependencies are described in “POPF and PUSHFInstructions” on page 178.
The MOV , PUSH, and POP instructions can be used to load and store segment registers, as described in “MOV , POP, and PUSH Instructions” on page 179.
User Mode Instruction Prevention (UMIP)This security mode restricts certain instructions so that they do not reveal information about structures 
that are controlled by the processor when it is at CPL=0. The presence of the UMIP feature is indicated by CPUID Function 0000_0007, ECX[2]=1. This mode is enabled by setting CR4 bit 11 to a 1. Attempts to set CR4 bit 11 when the UMIP feature is not supported result in a #GP fault. Once CR4[11] is set to 1, the SGDT, SIDT, SLDT, SMSW and STR instructions become available only at CPL=0. Any attempt to execute them with CPL>0 results in a #GP fault with error code 0.
6.1 Fast System Call and Return
Operating systems can use both paging and segmentation to implement protected memory models. Segment descriptors provide the necessary memory protection and privilege checking for segment accesses. By setting segment-descriptor fields appropriately, operating systems can enforce access restrictions as needed. VMSA VE Save State to VMCB X“VMSA VE and VMLOAD 
Instructions” on page 505
WBINVD Writeback and Invalidate Caches X“Cache Management” on page 181WBNOINVD Writeback No Invalidate X
WRFSBASE Write FS Base Address X “RDFSBASE, RDGSBASE, 
WRFSBASE, and WRGSBASE Instructions” on page 179WRGSBASE Write GS Base Address X
WRMSR Write Model-Specific Register X“RDMSR and WRMSR Instructions” on page 178
WRSS Write to Shadow Stack X “WRSS” on page 183
WRUSS Write to User Shadow Stack X “WRUSS” on page 183Table 6-1. System Management Instructions (continued)
Note:
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A disadvantage of segment-based protection and privilege checking is the overhead associated with 
loading a new segment selector (and its corresponding descriptor) into a segment register. Even when using the flat-memory model, this overhead still occurs when switching between privilege levels because code segments (CS) and stack segments (SS) are reloaded with different segment descriptors.
To initiate a call to the operating system, an application transfers control to the operating system 
through a gate descriptor (call, interrupt, trap, or task gate). In the past, control was transferred using either a far CALL instruction or a software interrupt. Transferring control through one of these gates is slowed by the segmentation-related overhead, as is the later return using a far RET or IRET instruction. The following checks are performed when control is transferred in this manner:
•Selectors, gate descriptors, and segment descriptors are in the proper form.
•Descriptors lie within the bounds of the descriptor tables.
•Gate descriptors reference the appropriate segment descriptors.
•The caller, gate, and target privileges all allow the control transfer to take place.
•The stack created by the call has sufficient properties to allow the transfer to take place.
In addition to these call-gate checks, other checks are made involving the task-state segment when a 
task switch occurs.
6.1.1  SYSCALL and SYSRET
SYSCALL and SYSRET Instructions.  SYSCALL and SYSRET are low-latency system call and 
return instructions. These instructions assume the operating system implements a flat-memory model, 
which greatly simplifies calls to and returns from the operating system. This simplification comes from eliminating unneeded checks, and by loading pre-determined values into the CS and SS segment registers (both visible and hidden portions). As a result, SYSCALL and SYSRET can take fewer than one-fourth the number of internal clock cycles to complete than the legacy CALL and RET instructions. SYSCALL and SYSRET are particularly well-suited for use in 64-bit mode, which requires implementation of a paged, flat-memory model. 
SYSCALL and SYSRET require that the code-segment base, limit, and attributes (except for DPL) are 
consistent for all application and system processes. Only the DPL is allowed to vary. The processor assumes (but does not check) that the SYSCALL target CS segment descriptor entry has DPL=0 and 
the SYSRET target CS segment descriptor entry has DPL=3. 
For details on the SYSCALL and SYSRET instructions, see “System Instruction Reference” in V olume 3. 
Because SYSCALL and SYSRET do not use the program stack to store return addresses, the shadow 
stack mechanism is not used to validate their return addresses. However, when shadow stacks are enabled, SYSCALL and SYSRET save and restore the current SSP as follows:
•If the shadow stack feature is enabled at the current CPL (typically CPL=3), SYSCALL saves the
current SSP to the PL3_SSP MSR
•If shadow stacks are enabled at the target CPL (CPL=0), SYSCALL clears the SSP to 0.
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•If shadow stacks are enabled at CPL=3, SYSRET restores SSP from PL3_SSP.
SYSCALL and SYSRET MSRs.  The STAR, LSTAR, and CSTAR registers are model-specific 
registers (MSRs) used to specify the target address of a SYSCALL instruction as well as the CS and 
SS selectors of the called and returned procedures. The SFMASK register is used in long mode to specify how rFLAGS is handled by these instructions. Figure 6-1 shows the STAR, LSTAR, CSTAR, and SFMASK register formats.
Figure 6-1. STAR, LSTAR, CSTAR, and MASK MSRs
•STAR —The STAR register has the following fields (unless otherwise noted, all bits are
read/write):
-SYSRET CS and SS Selectors —Bits 63:48. This field is used to specify both the CS and SS 
selectors loaded into CS and SS during SYSRET. If SYSRET is returning to 32-bit mode 
(either legacy or compatibility), this field is copied directly into the CS selector field. If SYSRET is returning to 64-bit mode, the CS selector is set to this field + 16. SS.Sel is set to this field + 8, regardless of the target mode. Because SYSRET always returns to CPL 3, the RPL bits 49:48 should be initialized to 11b. 
-SYSCALL CS and SS Selectors—Bits 47:32. This field is used to specify both the CS and SS selectors loaded into CS and SS during SYSCALL. This field is copied directly into CS.Sel. SS.Sel is set to this field + 8. Because SYSCALL always switches to CPL 0, the RPL bits 33:32 should be initialized to 00b.
-32-bit SYSCALL Target EIP —Bits 31:0. This is the target EIP of the called procedure.
The legacy STAR register is not expanded in long mode to provide a 64-bit target RIP address.Instead, long mode provides two new STAR registers—long STAR (LSTAR) and compatibilitySTAR (CSTAR)—that hold a 64-bit target RIP.
•LSTAR and CSTAR —The LSTAR register holds the target RIP of the called procedure in long
mode when the calling software is in 64-bit mode. The CSTAR register holds the target RIP of thecalled procedure in long mode when the calling software is in compatibility mode. The WRMSRinstruction is used to load the target RIP into the LSTAR and CSTAR registers. If the RIP written63 48 47 32 31 0
STAR C000_0081h SYSRET CS and SS SYSCALL CS and SS 32-bit SYSCALL Target EIP
LSTAR C000_0082h Target RIP for 64-Bit-Mode Calling Software
CSTAR C000_0083h Target RIP for Compatibility-Mode Calling Software
SFMASK C000_0084h Reserved, RAZ SYSCALL Flag Mask
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to either of the MSRs is not in canonical form, a #GP fault is generated on the WRMSR
•SFMASK —The SFMASK register is used to specify which RFLAGS bits are cleared during a
SYSCALL. In long mode, SFMASK is used to specify which RFLAGS bits are cleared whenSYSCALL is executed. If a bit in SFMASK is set to 1 , the corresponding bit in RFLAGS is cleared
to 0. If a bit in SFMASK is cleared to 0, the corresponding RFLAGS bit is not modified.
6.1.2  SYSENTER and SYSEXIT (Legacy Mode Only)
SYSENTER and SYSEXIT Instructions.  Like SYSCALL and SYSRET, SYSENTER and 
SYSEXIT are low-latency system call and return instructions designed for use by system and application software implementing a flat-memory model. However, these instructions are illegal in 
long mode and result in an undefined opcode exception (#UD) if software attempts to use them . 
Software should use the SYSCALL and SYSRET instructions when running in long mode.
SYSENTER and SYSEXIT MSRs.  Three model-specific registers (MSRs) are used to specify the

SYSENTER and SYSEXIT MSRs.  Three model-specific registers (MSRs) are used to specify the 
target address and stack pointers for the SYSENTER instruction as well as the CS and SS selectors of the called and returned procedures. The register fields are: 
•SYSENTER Target CS —Holds the CS selector of the called procedure.
•SYSENTER Target ESP —Holds the called-procedure stack pointer. The SS selector is updated
automatically to point to the next descriptor entry after the SYSENTER Target CS, and ESP is the
offset into that stack segment.
•SYSENTER Target EIP —Holds the offset into the CS of the called procedure.
Figure 6-2 shows the register formats and their corresponding MSR IDs.
Figure 6-2. SYSENTER_CS, SYSENTER_ESP, SYSENTER_EIP MSRs
6.1.3  SWAPGS Instruction
The SWAPGS instruction provides a fast method for system software to load a pointer to system data 
structures. SWAPGS can be used upon entering system-software routines as a result of a SYSCALL instruction or as a result of an interrupt or exception. Before returning to application software, SWAPGS can restore an application data-structure pointer that was replaced by the system data-structure pointer.63 32 31 16 15 0
SYSENTER_CS 174h SYSENTER Target CS
SYSENTER_ESP 175h SYSENTER Target ESP
SYSENTER_EIP 176h SYSENTER Target EIP
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SWAPGS exchanges the base-address value located in the KernelGSbase model-specific register 
(MSR address C000_0102h) with the base-address value located in the hidden portion of the GS selector register (GS.base). This exchange allows the system-kernel software to quickly access kernel data structures by using the GS segment-override prefix during memory references. 
The need for SwapGS arises from the requirement that, upon entry to the OS kernel, the kernel needs 
to obtain a 64-bit pointer to its essential data structures. When using SYSCALL to implement system calls, no kernel stack exists at the OS entry point. Neither is there a straightforward method to obtain a pointer to kernel structures, from which the kernel stack pointer could be read. Thus, the kernel cannot save GPRs or reference memory. SwapGS does not require any GPR or memory operands, so no registers need to be saved before using it. Similarly, when the OS kernel is entered via an interrupt or exception (where the kernel stack is already set up), SwapGS can be used to quickly get a pointer to the kernel data structures. 
See “FS and GS Registers in 64-Bit Mode” on page 80 for more information on using the GS.base 
register in 64-bit mode.
6.2 System Status and Control
System-status and system-control instructions are used to determine the features supported by a processor, gather information about the current execution state, and control the processor operating modes.
6.2.1  Processor Feature Identification (CPUID)
CPUID Instruction.  The CPUID instruction provides complete information about the processor 
implementation and its capabilities. Software operating at any privilege level can execute the CPUID 
instruction to collect this information. System software normally uses the CPUID instruction to determine which optional features are available so the system can be configured appropriately. See Section 3.3, “Processor Feature Identification,” on page 71.
6.2.2  Accessing Control Registers
MOV CRn  Instructions.  The MOV CRn instructions can be used to copy data between the control 
registers and the general-purpose registers. These instructions are privileged and cause a general-
protection exception (#GP) if non-privileged software attempts to execute them.
LMSW and SMSW Instructions.  The machine status word is located in CR0 register bits 15:0. The 
load machine status word  (LMSW) instruction writes only the least-significant four status-word bits 
(CR0[3:0]). All remaining status-word bits (CR0[15:4]) are left unmodified by the instruction. The instruction is privileged and causes a #GP to occur if non-privileged software attempts to execute it.
The store machine status word  (SMSW) instruction stores all 16 status-word bits (CR0[15:0]) into the 
target GPR or memory location. The instruction is not privileged and can be executed by all software.
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CLTS Instruction.  The clear task-switched bit  instruction (CLTS) clears CR0.TS to 0. The CR0.TS 
bit is set to 1 by the processor every time a task switch takes place. The bit is useful to system software 
in determining when the x87 and multimedia register state should be saved or restored. See “Task Switched (TS) Bit” on page 43 for more information on using CR0.TS to manage x87-instruction state. The CLTS instruction is privileged and causes a #GP to occur if non-privileged software attempts to execute it.
6.2.3  Accessing the RFLAGS Register
The RFLAGS register contains both application and system bits. This section describes the 
instructions used to read and write system bits. Descriptions of instruction effects on application flags can be found in “Flags Register” in V olume 1 and “Instruction Effects on rFLAGS” in V olume 3.
POPF and PUSHF Instructions.  The pop and push rFLAGS instructions are used for moving data 
between the rFLAGS register and the stack. They are not strictly system instructions, but their 
behavior is mode-dependent. 
CLI and STI Instructions.  The clear interrupt  (CLI) and set interrupt  (STI) instructions modify only 
the RFLAGS.IF bit or RFLAGS.VIF bit. Clearing RFLAGS.IF to 0 causes the processor to ignore maskable interrupts. Setting RFLAGS.IF to 1 causes the processor to allow maskable interrupts.
See “Virtual Interrupts” on page 287 for more information on the operation of these instructions when 
virtual-8086 mode extensions are enabled (CR4.VME=1).
CLAC and STAC Instructions.  The clear alignment check flag (CLAC) and set alignment check flag 
(STAC) instructions modify only the RFLAGS.AC bit. 
6.2.4  Accessing Debug RegistersThe MOV DR n instructions are used to copy data between the debug registers and the general-purpose 
registers. These instructions are privileged and cause a general-protection exception (#GP) if non-
privileged software attempts to execute them. See “Debug Registers” on page 391 for a detailed description of the debug registers.
6.2.5  Accessing Model-Specific Registers
RDMSR and WRMSR Instructions.  The read/write model-specific register instructions (RDMSR 
and WRMSR) can be used by privileged software to access the 64 -bit MSRs. See “Model-Specific 
Registers (MSRs)” on page 59 for details about the MSRs. 
RDPMC Instruction.  The read performance-monitoring counter  instruction, RDPMC, is used to read 
the model-specific performance-monitoring counter registers.
RDTSC Instruction.  The read time-stamp counter  instruction, RDTSC, is used to read the model-
specific time-stamp counter (TSC) register. 
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RDTSCP Instruction.  The read time-stamp counter and processor ID instruction, RDTSCP, is used 
to read the model-specific time-stamp counter (TSC) register. as well as the low 32 bits of the 
TSC_AUX register (MSR C000_0103h).
6.3 Segment Register and Descriptor Register Access
The AMD64 architecture supports the legacy instructions that load and store segment registers and descriptor registers. In some cases the instruction capabilities are expanded to support long mode.
6.3.1  Accessing Segment Registers
MOV, POP, and PUSH Instructions.  The MOV and POP instructions can be used to load a selector 
into a segment register from a general-purpose register or memory (MOV) or from the stack (POP). 
Any segment register, except the CS register, can be loaded with the MOV and POP instructions. The CS register must be loaded with a far-transfer instruction.
All segment register selectors can be stored in a general-purpose register or memory using the MOV 
instruction or pushed onto the stack using the PUSH instruction.
When a selector is loaded into a segment register, the processor automatically loads the corresponding 
descriptor-table entry into the hidden portion of the selector register. The hidden portion contains the base address, limit, and segment attributes.
Segment-load and segment-store instructions work normally in 64-bit mode. The appropriate entry is 
read from the system descriptor table (GDT or LDT) and is loaded into the hidden portion of the segment descriptor register. However, the contents of data-segment and stack-segment descriptor registers are ignored, except in the case of the FS and GS segment-register base fields—see “FS and GS Registers in 64-Bit Mode” on page 80 for more information.
The ability to use segment-load instructions allows a 64-bit operating system to set up segment 
registers for a compatibility-mode application before switching to compatibility mode.
6.3.2  Accessing Segment Register Hidden State
WRMSR and RDMSR Instructions.  The base address field of the hidden state of the FS and GS

WRMSR and RDMSR Instructions.  The base address field of the hidden state of the FS and GS 
registers are mapped to MSRs and may be read and written by privileged software when running in 64-
bit mode.
RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE Instructions.  When supported and 
enabled, these instructions allow software running at any privilege level to read and write the base address field of the hidden state of the FS and GS segment registers. These instructions are only defined in 64-bit mode.
6.3.3  Accessing Descriptor-Table Registers
LGDT and LIDT Instructions.  The load GDTR (LGDT) and load IDTR  (LIDT) instructions load a 
pseudo-descriptor  from memory into the GDTR or IDTR registers, respectively. 
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LLDT and LTR Instructions.  The load LDTR  (LLDT) and load TR  (LTR) instructions load a system-
segment descriptor from the GDT into the LDTR and TR segment-descriptor registers (hidden 
portion), respectively.
SGDT and SIDT Instructions.  The store GDTR  (SGDT) and store IDTR  (SIDT) instructions reverse 
the operation of the LGDT and LIDT instructions. SGDT and SIDT store a pseudo-descriptor from the GDTR or IDTR register into memory. 
SLDT and STR Instructions.  In all modes, the store LDTR  (SLDT) and store TR (STR) instructions 
store the LDT or task selector from the visible portion of the LDTR or TR register into a general-purpose register or memory, respectively. The hidden portion of the LDTR or TR register is not stored.
6.4 Protection Checking
Several instructions are provided to allow software to determine the outcome of a protection check before performing a memory access that could result in a protection violation. By performing the checks before a memory access, software can avoid violations that result in a general-protection exception (#GP). 
6.4.1  Checking Access Rights
LAR Instruction.  The load access-rights  (LAR) instruction can be used to determine if access to a 
segment is allowed, based on privilege checks and type checks. The LAR instruction uses a segment-
selector in the source operand to reference a descriptor in the GDT or LDT. LAR performs a set of access-rights checks and, if successful, loads the segment-descriptor access rights into the destination register. Software can further examine the access-rights bits to determine if access into the segment is allowed.
6.4.2  Checking Segment Limits
LSL Instruction.  The load segment-limit (LSL) instruction uses a segment-selector in the source 
operand to reference a descriptor in the GDT or LDT. LSL performs a set of preliminary access-rights 
checks and, if successful, loads the segment-descriptor limit field into the destination register. Software can use the limit value in comparisons with pointer offsets to prevent segment limit violations.
6.4.3  Checking Read/Write Rights
VERR and VERW Instructions.  The verify read-rights  (VERR) and verify write-rights  (VERW) can 
be used to determine if a target code or data segment (not a system segment) can be read or written 
from the current privilege level (CPL). The source operand for these instructions is a pointer to the segment selector to be tested. If the tested segment (code or data) is readable from the current CPL, the VERR instruction sets RFLAGS.ZF to 1; otherwise, it is cleared to zero. Likewise, if the tested data segment is writable, the VERW instruction sets the RFLAGS.ZF to 1. A code segment cannot be tested for writability.
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6.4.4  Adjusting Access Rights
ARPL Instruction.  The adjust RPL-field (ARPL) instruction can be used by system software to 
prevent access into privileged-data segments by lower-privileged software. This can happen if an 
application passes a selector to system software and the selector RPL is less than (has greater privilege than) the calling-application CPL. To prevent this surrogate access, system software executes ARPL with the following operands:
•The destination operand is the data-segment selector passed to system software by the application.
•The source operand is the application code-segment selector (available on the system-software
stack as a result of the CALL into system software by the application).
ARPL is not supported in 64-bit mode. 
6.5 Processor Halt
The processor halt instruction (HLT) halts instruction execution, leaving the processor in the halt state. 
No registers or machine state are modified as a result of executing the HLT instruction. The processor remains in the halt state until one of the following occurs:
•A non-maskable interrupt (NMI).
•An enabled, maskable interrupt (INTR).
•Processor reset (RESET).
•Processor initialization (INIT).
•System-management interrupt (SMI).
6.6 Cache and TLB Management
Cache-management instructions are used by system software to maintain coherency within the 
memory hierarchy. Memory coherency and caches are discussed in Chapter 7, “Memory System.” 
Similarly, TLB-management instructions are used to maintain coherency between page translations cached in the TLB and the translation tables maintained by system software in memory. See “Translation-Lookaside Buffer (TLB)” on page 157 for more information.
6.6.1  Cache Management
WBINVD and WBNOINVD Instructions.  The writeback and invalidate (WBINVD) and writeback 
no invalidate (WBNOINVD) instructions are used to write all modified cache lines to memory so that memory contains the most recent copy of data. After the writes are complete, the WBINVD instruction invalidates all cache lines, whereas the WBNOINVD instruction may leave the lines in the cache hierarchy in a non-modified state. These instructions operate on all caches in the memory hierarchy, including caches that are external to the processor. See the instructions' description in V olume 3 for further operational details.
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INVD Instruction.  The invalidate  (INVD) instruction is used to invalidate all cache lines in all caches 
in the memory hierarchy. Unlike the WBINVD instruction, no modified cache lines are written to 
memory. The INVD instruction should only be used in situations where memory coherency is not required.
6.6.2  TLB Invalidation
INVLPG Instruction.  The invalidate TLB entry (INVLPG) instruction can be used to invalidate 
specific entries within the TLB. The source operand is a virtual-memory address that specifies the 
TLB entry to be invalidated. Invalidating a TLB entry does not remove the associated page-table entry from the data cache. See “Translation-Lookaside Buffer (TLB)” on page 157 for more information.
INVLPGA Instruction.  The invalidate TLB entry in a Specified ASID instruction (INVLPGA) can be 
used to invalidate TLB entries associated with the specified ASID. See “Invalidate Page, Alternate ASID” on page 529.
INVLPGB Instruction.  The invalidate TLB with Broadcast  instruction (INVLPGB) can be used to 
invalidate a specified range of TLB entries on the local processor and broadcast the invalidation to remote processors. See “INVLPGB” in V olume 3.
INVPCID Instruction.  The invalidate TLB entries in Specified PCID  instruction (INVPCID) can be 
used to invalidate TLB entries of the specified Processor Context ID. See “INVPCID” in V olume 3.
6.7 Shadow Stack Management 
The following instructions are available to software for use in managing shadow stacks if the shadow stack feature is present as indicated by CPUID Fn0000_0007_x0_ECX[CET_SS] (bit 7) =1. Except for RDSSP, attempting to execute these instructions when shadow stacks are disabled results in a #UD exception. For more information refer to the detailed instruction descriptions in APM volume 3.
CLRSSBSY.  Validates a shadow stack token and clears the tokens busy bit. This is a privileged 
INCSSP.  Increment SSP by ‘n’ stack frames. Used to pop unneeded items from a shadow stack.
RDSSP.  Read the SSP into a GPR. Treated as a NOP if shadow stacks are disabled.
RSTORSSP.  Used to switch shadow stacks. Expects a ‘shadow stack restore token’ at the top of the 
new shadow stack. Upon validating this token, sets the token’s busy bit and sets SSP to the top of the new shadow stack.
SAVEPREVSSP.  Copies a ‘previous SSP token’ from the current shadow stack back to the previous 
stack for later use by an RSTORSSP instruction.
SETSSBSY.  Validates the shadow stack token pointed to by the PL0_SSP MSR. If valid, sets the 
busy bit to 1 and sets SSP = PL0_SSP. This is a privileged instruction.
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WRSS.  Writes the source operand to a shadow stack. This instruction must be enabled in the U_CET 
and S_CET MSRs, otherwise a #UD is generated.
WRUSS.  Writes the source operand to a user shadow stack. This is a privileged instruction.
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7 Memory System
This chapter describes:
•Cache coherency mechanisms
•Cache control mechanisms
•Memory typing
•Memory mapped I/O

•Memory ordering rules
•Serializing instructions
Figure 7-1 on page 185 shows a conceptual picture of a processor and memory system, and how data 
and instructions flow between the various components. This diagram is not intended to represent a 
specific microarchitectural implementation but instead is used to illustrate the major memory-system components covered by this chapter.
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Figure 7-1. Processor and Memory System
The memory-system components described in this chapter are shown as unshaded  boxes in Figure 7-1. 
Those items are summarized in the following paragraphs.
Main memory is external to the processor chip and is the memory-hierarchy level farthest from the 
processor execution units.
Caches  are the memory-hierarchy levels closest to the processor execution units. They are much 
smaller and much faster than main memory, and can be either internal or external to the processor chip. 
Caches contain copies of the most frequently used instructions and data. By allowing fast access to frequently used data, software can run much faster than if it had to access that data from main memory. Figure 7-1 shows three caches, all internal to the processor:513-211.epsWrite-Combining
BuffersL1
Instruction Cache
Write BuffersL2 Cache
L1
Data CacheMain Memory
System Bus Interface
Load/Store Unit
Execution Units
Processor Chip
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•L1 Data Cache—The L1 (level-1) data cache holds the data most recently read or written by the
software running on the processor.
•L1 Instruction Cache—The L1 instruction cache is similar to the L1 data cache except that it holdsonly the instructions executed most frequently. In some processor implementations, the L1instruction cache can be combined with the L1 data cache to form a unified L1 cache.
•L2 Cache—The L2 (level-2) cache is usually several times larger than the L1 caches, but it is alsoslower. It is common for L2 caches to be implemented as a unified cache containing bothinstructions and data. Recently used instructions and data that do not fit within the L1 caches canreside in the L2 cache. The L2 cache can be exclusive, meaning it does not cache informationcontained in the L1 cache. Conversely, inclusive L2 caches contain a copy of the L1-cachedinformation.
Memory-read operations from cacheable memory first check the cache to see if the requested information is available. A read hit  occurs if the information is available in the cache, and a read miss  
occurs if the information is not available. Likewise, a write hit  occurs if the memory write can be 
stored in the cache, and a write miss  occurs if it cannot be stored in the cache.
Caches are divided into fixed-size blocks called cache lines . The cache allocates lines to correspond to 
regions in memory of the same size as the cache line, aligned on an address boundary equal to the cache-line size. For example, in a cache with 32-byte lines, the cache lines are aligned on 32-byte boundaries and byte addresses 0007h and 001Eh are both located in the same cache line. The size of a cache line is implementation dependent. Most implementations have either 32-byte or 64-byte cache lines. The implemented cache line size is reported by CPUID Fn8000_0005 and Fn8000_0006 for the various caches, as described in Appendix E of V olume 3.
The process of loading data into a cache is a cache-line fill . Even if only a single byte is requested, all 
bytes in a cache line are loaded from memory. Typically, a cache-line fill must remove (evict) an 
existing cache line to make room for the new line loaded from memory. This process is called cache-
line replacement. If the existing cache line was modified before the replacement, the processor performs a cache-line writeback  to main memory when it performs the cache-line fill.
Cache-line writebacks help maintain coherency  between the caches and main memory. Internally, the 
processor can also maintain cache coherency by internally probing (checking) the other caches and 
write buffers for a more recent version of the requested data. External devices can also check processor caches for more recent versions of data by externally probing the processor. Throughout this 
document, the term probe  is used to refer to external probes, while internal probes are always qualified 
with the word internal .
Write buffers  temporarily hold data writes when main memory or the caches are busy with other 
memory accesses. The existence of write buffers is implementation dependent.
Implementations of the architecture can use write-combining buffers if the order and size of non-
cacheable writes to main memory is not important to the operation of software. These buffers can 
combine multiple, individual writes to main memory and transfer the data in fewer bus transactions.
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7.1 Single-Processor Memory Access Ordering
The flexibility with which memory accesses can be ordered is closely related to the flexibility in which 
a processor implementation can execute  and retire  instructions. Instruction execution creates results 
and status and determines whether or not the instruction causes an exception. Instruction retirement commits  the results of instruction execution, in program order, to software-visible resources such as 
memory, caches, write-combining buffers, and registers, or it causes an exception to occur if instruction execution created one.
Implementations of the AMD64 architecture retire instructions in program order, but implementations 
can execute instructions in any order, subject only to data dependencies. Implementations can also speculatively execute  instructions—executing instructions before knowing they are needed. Internally, 
implementations manage data reads and writes so that instructions complete in order. However, because implementations can execute instructions out of order and speculatively, the sequence of memory accesses performed by the hardware can appear to be out of program order. The following sections describe the rules governing memory accesses to which processor implementations adhere. These rules may be further restricted, depending on the memory type being accessed. Further, these rules govern single processor operation; see “Multiprocessor Memory Access Ordering” on page 189 for multiprocessor ordering rules.
7.1.1  Read Ordering
Generally, reads do not affect program order because they do not affect the state of software-visible 
resources other than register contents. However, some system devices might be sensitive to reads. In such a situation software can map a read-sensitive device to a memory type that enforces strong read-ordering, or use read/write barrier instructions to force strong read-ordering. 
For cacheable memory types, the following rules govern read ordering:
•Out-of-order reads are allowed to the extent that they can be performed transparently to software,
such that the appearance of in-order execution is maintained. Out-of-order reads can occur as aresult of out-of-order instruction execution or speculative execution. The processor can readmemory and perform cache refills out-of-order to allow out-of-order execution to proceed.
•Speculative reads are allowed. A speculative read occurs when the processor begins executing amemory-read instruction before it knows the instruction will actually complete. For example, theprocessor can predict a branch will occur and begin executing instructions following the predictedbranch before it knows whether the prediction is valid. When one of the speculative instructionsreads data from memory, the read itself is speculative. Cache refills may also be performedspeculatively.
•Reads can be reordered ahead of writes. Reads are generally given a higher priority by theprocessor than writes because instruction execution stalls if the read data required by an instructionis not immediately available. Allowing reads ahead of writes usually maximizes softwareperformance.
•A read cannot  be reordered ahead of a prior write if the read is from the same location as the prior
write. In this case, the read instruction stalls until the write instruction completes execution. The
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read instruction requires the result of the write instruction for proper software operation. For
cacheable memory types, the write data can be forwarded to the read instruction before it isactually written to memory.
•Instruction fetching constitutes a parallel, asynchronous stream of reads that is independent fromand unordered with respect to the read accesses performed by loads in that instruction stream.
7.1.2  Write Ordering
Writes affect program order because they affect the state of software-visible resources. The following 
rules govern write ordering:

•Generally, out-of-order writes are not allowed. Write instructions executed out of order cannot
commit (write) their result to memory until all previous instructions have completed in program
order. The processor can, however, hold the result of an out-of-order write instruction in a privatebuffer (not visible to software) until that result can be committed to memory.
•It is possible for writes to write-combining  memory types to appear to complete out of order,
relative to writes into other memory types. See “Memory Types” on page 196 and “Write
Combining” on page 202 for additional information.
•Speculative writes are not allowed. As with out-of-order writes, speculative write instructions
cannot commit their result to memory until all previous instructions have completed in programorder. Processors can hold the result in a private buffer (not visible to software) until the result canbe committed.
•Write buffering is allowed. When a write instruction completes and commits its result, that resultcan be buffered until it is actually written to system memory in program order. Although the writebuffer itself is not directly accessible by software, the results in the buffer are accessible bysubsequent memory accesses to the locations that are buffered, including reads for which only asubset of bytes being accessed are in the buffer. For example, a doubleword read that overlaps asingle modified byte in the write buffer can return the buffered value for that byte before that writehas been committed to memory.
In general, any read from cacheable memory returns the net result of all prior globally and locally
visible writes to those bytes, as performed in program order. A given implementation may provide
bytes from the write buffer to satisfy this, or may stall the read until any overlapping bufferedwrites have been committed to memory. For cacheable memory types, the write buffer can be readout-of-order and speculatively, just like memory.
•Write combining is allowed. In some situations software can relax the write-ordering rules throughthe use of a Write Combining memory type or non-temporal store instructions, and allow severalwrites to be combined into fewer writes to memory. When write-combining is used, it is possiblefor writes to other memory types to proceed ahead of (out-of-order) memory-combining writes,unless the writes are to the same address. Write-combining should be used only when the order ofwrites does not affect program order (for example, writes to a graphics frame buffer).
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7.1.3  Read/Write Barriers
When the order of memory accesses must be strictly enforced, software can use read/write barrier 
instructions to force reads and writes to proceed in program order. Read/write barrier instructions force all prior reads or writes to complete before subsequent reads or writes are executed. The LFENCE, SFENCE, and MFENCE instructions are provided as dedicated read, write, and read/write barrier instructions (respectively). Serializing instructions, I/O instructions, and locked instructions (including the implicitly locked XCHG instruction) can also be used as read/write barriers. Barrier instructions are useful for controlling ordering between differing memory types as well as within one memory type; see Section 7.3.1, “Special Coherency Considerations,” on page 194 for details.
Table 7-2 on page 198 summarizes the memory-access ordering possible for each memory type supported by the AMD64 architecture.
7.2 Multiprocessor Memory Access Ordering
The term memory ordering refers to the sequence in which memory accesses are performed by the memory system, as observed by all processors or programs.
To improve performance of applications, AMD64 processors can speculatively execute instructions 
out of program order and temporarily hold out-of-order results. However, certain rules are followed with regard to normal cacheable accesses on naturally aligned boundaries to WB memory.
In the examples below, all memory values are initialized to zero.From the point of view of a program, in ascending order of priority:
•All loads, stores and I/O operations from a single processor appear to occur in program order to the
code running on that processor and all instructions appear to execute in program order.
•Successive stores from a single processor are committed to system memory and visible to otherprocessors in program order. A store by a processor cannot be committed to memory before a readappearing earlier in the program has captured its targeted data from memory. In other words, storesfrom a processor cannot be reordered to occur prior to a load preceding it in program order. 
In this context:
- Loads do not pass previous loads (loads are not reordered). Stores do not pass previous stores 
(stores are not reordered)
Load A cannot read 0 when Load B reads 1. (This rule may be violated in the case of loads as
part of a string operation, in which one iteration of the string reads 0 for Load A while anotheriteration reads 1 for Load B.)
- Stores do not pass loads Processor 0 Processor 1
Store A  1 Load B 
Store B  1 Load A
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Load A and Load B cannot both read 1.
•Stores from a processor appear to be committed to the memory system in program order; however,
stores can be delayed arbitrarily by store buffering while the processor continues operation.Therefore, stores from a processor may not appear to be sequentially consistent. 
Both Load A and Load B may read 1. Also, due to possible write combining one or bothprocessors may not actually store a 1 at the designated location.
•Non-overlapping Loads may pass stores. 
All combinations of values (00, 01, 10, and 11) may be observed by Processors 0 and 1. 
- Where sequential consistency is needed (for example in Dekker’s algorithm for mutual 
exclusion), an MFENCE instruction should be used between the store and the subsequent load, or a locked access, such as XCHG, should be used for the store.
Load A and Load B cannot both read 0.
- Loads that partially overlap prior stores may return the modified part of the load operand from 
the store buffer, combining globally visible bytes with bytes that are only locally visible. To 
ensure that such loads return only a globally visible value, an MFENCE or locked access must be used between the store and the dependent load, or the store or load must be performed with a locked operation such as XCHG.
- Stores to different locations in memory observed from two (or more) other processors will 
appear in the same order to all observers. Behavior such as that shown in this code example,Processor 0 Processor 1
Load A Load B 
Store B  1 Store A  1
Processor 0 Processor 1
Store A  1 Store B  1
… …
Store A  2 Store B  2
… …
Load B Load A
Store A  1 Store B  1 
MFENCE MFENCE
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in which processor X sees store A from processor 0 before store B from processor 1, while
processor Y sees store B from processor 1 before store A from processor 0, is not allowed.
•Dependent stores between different processors appear to occur in program order, as shown in thecode example below. 
If processor 1 reads a value from A (written by processor 0) before carrying out a store to B, and if
processor 2 reads the updated value from B, a subsequent read of A must also be the updated value. 
•The local visibility (within a processor) for a memory operation may differ from the globalvisibility (from another processor). Using a data bypass, a local load can read the result of a localstore in a store buffer, before the store becomes globally visible. Program order is still maintainedwhen using such bypasses.
Load A in processor 0 can read 1 using the data bypass, while Load A in processor 1 can read 0.
Similarly, Load B in processor 1 can read 1 while Load B in processor 0 can read 0. Therefore, theresult r1 = 1, r2 = 0, r3 = 1 and r4 = 0 may occur. There are no constraints on the relative order ofwhen the Store A of processor 0 is visible to processor 1 relative to when the Store B of processor1 is visible to processor 0.
If a very strong memory ordering model is required that does not allow local store-load bypasses,
an MFENCE instruction or a synchronizing instruction such as XCHG or a locked Read-modify-write should be used between the store and the subsequent load. This enforces a memory orderingstronger than total store ordering.Processor 0 Processor 1 Processor X Processor Y
Load A (1) Load B (1)
Load B (0) Load A (0)
Processor 0 Processor 1 Processor 2
Store A  1
Load A (1)
Store B  1
Load B (1)
Load A (1)
Load r1 A Load r3 B
Load r2 B Load r4 A
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Store A  1
Load A (1)
Store B  1
Load B (1)
Load A (1)
In this example, the MFENCE instruction ensures that any buffered stores are globally visible
before the loads are allowed to execute, so the result r1 = 1, r2 = 0, r3 = 1 and r4 = 0 will not occur.
7.3 Memory Coherency and Protocol
Implementations that support caching support a cache-coherency protocol for maintaining coherency between main memory and the caches. The cache-coherency protocol is also used to maintain coherency between all processors in a multiprocessor system. The cache-coherency protocol supported by the AMD64 architecture is the MOESI  (modified, owned, exclusive, shared, invalid) 
protocol. The states of the MOESI protocol are:
•Invalid —A cache line in the invalid state does not hold a valid copy of the data. Valid copies of the
data can be either in main memory or another processor cache.
•Exclusive —A cache line in the exclusive state holds the most recent, correct copy of the data. The
copy in main memory is also the most recent, correct copy of the data. No other processor holds a
copy of the data. 
•Shared—A cache line in the shared state holds the most recent, correct copy of the data. Otherprocessors in the system may hold copies of the data in the shared state, as well. If no otherprocessor holds it in the owned state, then the copy in main memory is also the most recent. 
•Modified —A cache line in the modified state holds the most recent, correct copy of the data. The
copy in main memory is stale (incorrect), and no other processor holds a copy.
•Owned —A cache line in the owned state holds the most recent, correct copy of the data. The
owned state is similar to the shared state in that other processors can hold a copy of the most recent,correct data. Unlike the shared state, however, the copy in main memory can be stale (incorrect).Only one processor can hold the data in the owned state—all other processors must hold the data inthe shared state. 
Figure 7-2 on page 193 shows the general MOESI state transitions possible with various types of 
memory accesses. This is a logical software view, not a hardware view, of how cache-line state transitions. Instruction-execution activity and external-bus transactions can both be used to modify the cache MOESI state in multiprocessing or multi-mastering systems. Load r1 A Load r3 B
Load r2 B Load r4 AProcessor 0 Processor 1
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Figure 7-2. MOESI State Transitions
To maintain memory coherency, external bus masters (typically other processors with their own 
internal caches) need to acquire the most recent copy of data before caching it internally. That copy can be in main memory or in the internal caches of other bus-mastering devices. When an external master has a cache read-miss or write-miss, it probes the other mastering devices to determine whether the 
most recent copy of data is held in any of their caches. If one of the other mastering devices holds the most recent copy, it provides it to the requesting device. Otherwise, the most recent copy is provided by main memory.
There are two general types of bus-master probes:513-212.epsReset
INVD, WBINVDRead Hit
Write Miss (WB memory)Probe Write Hit
Probe Read HitProbe Write Hit
Read Miss, Exclusive
Probe Read HitWrite Hit
Read Miss, Shared
Probe Write HitInvalid Exclusive
Read Hit
Write HitModified
Write HitOwned
Read Hit
Probe Read HitShared
Read Hit
Write Hit
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•Read probes indicate the external master is requesting the data for read purposes. 
•Write probes indicate the external master is requesting the data for the purpose of modifying it. 
Referring back to Figure 7-2 on page 193, the state transitions involving probes are initiated by other 
processors and external bus masters into the processor. Some read probes are initiated by devices that 
intend to cache the data. Others, such as those initiated by I/O devices, do not intend to cache the data. Some processor implementations do not change the data MOESI state if the read probe is initiated by a device that does not intend to cache the data.
State transitions involving read misses and write misses can cause the processor to generate probes 
into external bus masters and to read main memory.
Read hits do not cause a MOESI-state change. Write hits generally cause a MOESI-state change into 
the modified state. If the cache line is already in the modified state, a write hit does not change its state.
The specific operation of external-bus signals and transactions and how they influence a cache MOESI 
state are implementation dependent. For example, an implementation could convert a write miss to a WB memory type into two separate MOESI-state changes. The first would be a read-miss placing the cache line in the exclusive state. This would be followed by a write hit into the exclusive cache line, changing the cache-line state to modified.
7.3.1  Special Coherency Considerations
In some cases, data can be modified in a manner that is impossible for the memory-coherency protocol 
to handle due to the effects of instruction prefetching. In such situations software must use serializing instructions and/or cache-invalidation instructions to ensure subsequent data accesses are coherent.
An example of this type of a situation is a page-table update followed by accesses to the physical pages referenced by the updated page tables. The following sequence of events shows what can happen when software changes the translation of virtual-page A from physical-page M to physical-page N:
1. Software invalidates the TLB entry. The tables that translate virtual-page A to physical-page M
are now held only in main memory. They are not cached by the TLB.
2. Software changes the page-table entry for virtual-page A in main memory to point to physical-
page N rather than physical-page M.
3. Software accesses data in virtual-page A. 
During Step 3, software expects the processor to access the data from physical-page N. However, it is 
possible for the processor to prefetch the data from physical-page M before the page table for virtual-
page A is updated in Step 2. This is because the physical-memory references for the page tables  are 
different than the physical-memory references for the data. Because the physical-memory references 
are different, the processor does not recognize them as requiring coherency checking and believes it is 
safe to prefetch the data from virtual-page A, which is translated into a read from physical page M. Similar behavior can occur when instructions are prefetched from beyond the page table update instruction.
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To prevent this problem, software must use an INVLPG or MOV CR3 instruction immediately after 
the page-table update to ensure that subsequent instruction fetches and data accesses use the correct virtual-page-to-physical-page translation. It is not necessary to perform a TLB invalidation operation preceding the table update.
7.3.2  Access Atomicity 
Cacheable, naturally-aligned single loads or stores of up to a quadword are atomic on any processor 
model, as are misaligned loads or stores of less than a quadword that are contained entirely within a naturally-aligned quadword. Misaligned load or store accesses typically incur a small latency penalty. 
Model-specific relaxations of this quadword atomicity boundary, with respect to this latency penalty, may be found in a given processor's Software Optimization Guide. 
Misaligned accesses can be subject to interleaved accesses from other processors or cache-coherent 
devices which can result in unintended behavior. Atomicity for misaligned accesses can be achieved 
where necessary by using the XCHG instruction or any suitable LOCK-prefixed instruction. 
Processors that report CPUID Fn0000_0001_ECX[A VX](bit 28) = 1 extend the atomicity for 
cacheable, naturally-aligned single loads or stores from a quadword to a double quadword. 
7.3.3  Cacheable Locks and Bus Locks
The processor guarantees access atomicity for locked read-modify-write operations. WB memory 
type, aligned locked read-modify-write (RMW) instructions are referred to as "cacheable locks". Cacheable locks are handled within a single processor and incur minimal or no performance penalty.  Non-WB and misaligned locked RMW instructions are referred to as "bus locks" and require system-wide synchronization among all processors to guarantee atomicity.  Bus locks may incur significant performance penalties for all processors in the system when any processor performs a non-WB or misaligned locked RMW instruction.
The processor performs a bus lock for any locked read-modify-write operations with a memory type 
other than WB, regardless of alignment.
The processor performs a bus lock for any misaligned locked read-modify-write operations, regardless

The processor performs a bus lock for any misaligned locked read-modify-write operations, regardless 
of memory type.  The alignment boundary at which a processor considers an access to be misaligned, and thus performs a bus lock instead of a cacheable lock for a locked read-modify-write operation, is implementation-dependent.  A bus lock is always performed when an access spans an L1 data cache cacheline alignment boundary, but a processor may perform a bus lock at alignment boundaries smaller than the L1 data cache cacheline alignment boundary.  The L1 data cache cacheline size and alignment boundary is specified by CPUID Fn8000_0005_ECX [L1 Data Cache Identifiers] (bits 7:0).
Atomic read-modify-write operations are performed on behalf of the types of operations listed in 
Table 7-1.
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The processor provides several methods for reporting bus lock activity to system software and 
reducing its frequency and performance penalty.  Bus lock trap is described in section 8.2.2 on page 247 and section 13.1 on page 390, and SVM Bus Lock Threshold is described in section 15.14.5 
on page 524.
7.4 Memory Types
Memory type  is an attribute that can be associated with a specific region of virtual or physical memory. 
Memory type designates certain caching and ordering behaviors for loads and stores to addresses in that region. Most memory types are explicitly assigned, although some are inferred by the hardware from current processor state and instruction context.
The AMD64 architecture defines the following memory types:
•Uncacheable (UC) —Reads from, and writes to, UC memory are not cacheable. Reads from UC
memory cannot be speculative. Write-combining to UC memory is not allowed. Reads from or
writes to UC memory cause the write buffers to be written to memory and be invalidated prior tothe access to UC memory.
The UC memory type is useful for memory-mapped I/O devices where strict ordering of reads and
writes is important. Note that this strong ordering is with respect to UC accesses only; reads tomemory types which support speculative operation may bypass non-conflicting UC accesses.
•Cache Disable (CD) —The CD memory type is a form of uncacheable memory type that is inferred
when the L1 caches are disabled but not invalidated, or for certain conflicting memory typeassignments from the Page Attribute Table (PAT) and Memory Type Range Register (MTRR)mechanisms. The former case occurs when caches are disabled by setting CR0.CD to 1 withoutinvalidating the caches with either the INVD or WBINVD instruction for any reference to a regiondesignated as cacheable. The latter case occurs when a specific type has been assigned to a virtualpage via PAT, and a conflicting type has been assigned to the mapped physical page via an MTRRTable 7-1. Atomic Read-Modify-Write Operation
Category Operations Comments
Software atomic using a 
memory operand  XCHG, LOCK prefix + ADD, SUB, AND, OR, XOR, ADC, SBB, INC, DEC, NOT, NEG, BTC, BTR, BTS, XADD, CMPXCHG Atomic read-modify-write on the memory operand
Segmentation and system data structuresLSL, LAR, VERR, VERW, LDS, LES, LFS, LGS, LSS, LTR, MOV DS, MOV ES, MOV FS, MOV GS, MOV SS, POP DS, POP ES, POP FS, POP GS, POP SS, Task switch Setting Accessed bit in segment or task descriptor or TSS
Far control transfer  CALL (far), JMP (far), RET (far), IRET, INTn, INT3, INT0, INT1, exception or interrupt or trap gate  Setting Accessed bit in gate descriptor
Paging  Page table walk for instruction fetch or data access Setting Accessed or Dirty bit in page table entries
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(see “Combined Effect of MTRRs and PAT” on page 229 and “Combining Memory Types,
MTRRs” on page 552 for details).
For the L1 data cache and the L2 cache, reads from, and writes to, CD memory that hit the cache,
or any other caches in the system, cause the cache line(s) to be invalidated before accessing mainmemory. If a cache line is in the modified state, the line is written to main memory prior to beinginvalidated. The access is allowed to proceed after any invalidations are complete.
For the L1 instruction cache, instruction fetches from CD memory that hit the cache read the
cached instructions rather than access main memory. Instruction fetches that miss the cache accessmain memory and do not cause cache-line replacement. Writes to CD memory that hit in theinstruction cache cause the line to be invalidated.
•Write-Combining (WC) —Reads from, and writes to, WC memory are not cacheable. Reads from
WC memory can be speculative.
Writes to this memory type can be combined internally by the processor and written to memory as
a single write operation to reduce memory accesses. For example, four word writes to consecutiveaddresses can be combined by the processor into a single quadword write, resulting in one memoryaccess instead of four. Reads from this memory can also be combined internally by the processor ifthey are to the same cache line. WC reads are not combined across serializing or barrierinstructions.
The WC memory type is useful for graphics-display memory buffers where the order of writes is
not important.
•Write-Combining Plus (WC+) —WC+ is an uncacheable memory type, and combines writes in
write-combining buffers like WC. Unlike WC (but like the CD memory type), accesses to WC+memory probe the caches on all processors (including the caches of the processor issuing therequest) to maintain coherency. This ensures that cacheable writes are observed by WC+ accesses.
•Write-Protect (WP) —Reads from WP memory are cacheable and allocate cache lines on a read
miss. Reads from WP memory can be speculative.
Writes to WP memory that hit in the cache do not update the cache. Instead, all writes update
memory (write to memory), and writes that hit in the cache invalidate the cache line. Writebuffering of WP memory is allowed.
The WP memory type is useful for shadowed-ROM memory where updates must be immediately
visible to all devices that read the shadow locations.
•Writethrough (WT) —Reads from WT memory are cacheable and allocate cache lines on a read
miss. Reads from WT memory can be speculative.
All writes to WT memory update main memory, and writes that hit in the cache update the cache
line (cache lines remain in the same state after a write that hits a cache line). Writes that miss thecache do not allocate a cache line. Write buffering of WT memory is allowed.
•Writeback (WB) —Reads from WB memory are cacheable and allocate cache lines on a read miss.
Cache lines can be allocated in the shared, exclusive, or modified states. Reads from WB memorycan be speculative. 
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All writes that hit in the cache update the cache line and place the cache line in the modified state.
Writes that miss the cache allocate a new cache line and place the cache line in the modified state.Writes to main memory only take place during writeback operations. Write buffering of WBmemory is allowed.
The WB memory type provides the highest-possible performance and is useful for most software
and data stored in system memory (DRAM).
Table 7-2 shows the memory access ordering possible for each memory type supported by the AMD64 
architecture. Table 7-4 on page 200 shows the ordering behavior of various operations on various memory types in greater detail. Table 7-3 on page 198 shows the caching policy for the same memory types.
Table 7-2. Memory Access by Memory Type
Memory Access
AllowedMemory Type
UC/CD WC WP WT WB
ReadOut-of-Order no yes yes yes yes
Speculative no yes yes yes yes
Reorder Before Write no yes yes yes yes
WriteOut-of-Order no yes no no no
Speculative no no no no no
Buffering no yes yes yes yes
Combining1no yes no yes yes
Note:
1. Write-combining buffers are separate from write (store) buffers.
Table 7-3. Caching Policy by Memory Type
Caching PolicyMemory Type
UC CD WC WP WT WB
Read Cacheable no no no yes yes yes
Write Cacheable no no no no yes yes
Read Allocate no no no yes yes yes
Write Allocate no no no no no yes
Write Hits Update Memory yes2yes1yes2yes3yes no
Note:
1. For the L1 data cache and the L2 cache, if an access hits the cache, the cache line is invalidated. If the cache line is in the
modified state, the line is written to main memory and then invalidated. For the L1 instruction cache, read (instruction fetch)
hits access the cache rather than main memory.
2. The data is not cached, so a cache write hit cannot occur. However, memory is updated.
3. Write hits update memory and invalidate the cache line.
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7.4.1  Instruction Fetching from Uncacheable Memory
Instruction fetches from an uncacheable memory type (including those for the CD type which don't hit

Note:
Instruction fetches from an uncacheable memory type (including those for the CD type which don't hit 
in the instruction cache) may read a naturally-aligned block of memory no larger than an instruction cache line that contains multiple instructions, and may or may not repeat reads of a given block in the course of extracting instructions from it. In general, the exact sequence of read accesses is not deterministic, regardless of instruction stream contents, aside from the following constraints:
•instruction fetching of branch targets from uncacheable memory will only be done non-
speculatively
•sequential instruction fetching will not transition speculatively from a cacheable memory type toan uncacheable memory type
•sequential instruction fetching will not speculatively cross more than one 4KB page boundary
It is recommended that MMIO devices that have read side-effects be separated from memory that's subject to uncacheable instruction fetches by at least one 4KB page.
7.4.2  Memory Barrier Interaction with Memory Types
Memory types other than WB may allow weaker ordering in certain respects. When the ordering of 
memory accesses to differing memory types must be strictly enforced, software can use the LFENCE, MFENCE or SFENCE barrier instructions to force loads and stores to proceed in program order. Table 7-4 on page 200 summarizes the cases where a memory barrier must be inserted between two memory operations.
The table is read as follows: the ROW is the first memory operation in program order, followed by the 
COLUMN, which is the second memory operation in program order. Each cell represents the ordered combination of the two memory operations and the letters a, b, c, d, e, f, g, h, i, j, k, and l within the cell 
represent the applicable memory ordering rule for that combination. These symbols are described in the footnotes below the table. In the table and footnotes, the abbreviation nt stands for non-temporal 
(load or store), io stands for input / output, lf for LFENCE, sf for SFENCE, and mf for MFENCE.
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Table 7-4. Memory Access Ordering Rules
a — A load (wp, wt, wb) may not pass a previous load (wp, wt, wb, wc, wc+, uc).
b — A load (wc, wc+) may pass a previous load (wp, wt, wb, wc, wc+). To ensure memory order, an
LFENCE instruction must be inserted between the two loads.
c — A store (wp, wt, wb, uc, wc, wc+, nt) may not pass a previous load (wp, wt, wb, uc, wc, wc+, nt).
d — All previous loads and stores complete to memory or I/O space before a memory access for an I/O,
locked or serializing instruction is issued.
e — A load (wp, wt, wb, wc, wc+) may pass a previous non-conflicting store (wp, wt, wb, wc, wc+, nt).
To ensure memory order, an MFENCE instruction must be inserted between the store and the load.
f — A load or store (uc) does not pass a previous load or store (wp, wt, wb, uc, wc, wc+, nt).g — A store (wp, wt, wb, uc) does not pass a previous store (wp, wt, wb, uc).h — A store (wc, wc+, nt) may pass a previous store (wp, wt, wb) or non-conflicting store (wc, wc+, nt).
To ensure memory order, an SFENCE instruction must be inserted between these two stores. A store
(wc, wc+, nt) does not pass a previous conflicting store (wc, wc+, nt, uc).
i — A load (wp, wt, wb, wc, wc+) may pass a previous non-conflicting store (uc). To ensure memory
order, an MFENCE instruction must be inserted between the store and the load.
j — A store (wp, wt, wb) may pass a previous store (wc, wc+, nt). To ensure memory order, an SFENCE
instruction must be inserted between these two stores.
k — All loads and stores associated with the I/O and locked instructions complete to memory (no buffered
stores) before a load or store from a subsequent instruction is issued.Second Memory Operation
First Memory Operation
Load (wp, wt, wb)
Load (uc)
Load (wc, wc+)
Store (wp, wt, wb)
Store (uc)
  Store 
(wc, wc+, non-temporal) 
Load/Store (io)
Lock (atomic)
Serialize instructions/
Interrupts/Exceptions
Load (wp, wt, wb) a f b (lf) c c c d d d
Load (uc) a f b (lf) c c c d d d
Load (wc, wc+) a f b (lf) c c c d d d
Store (wp, wt, wb) e (mf) f e (mf) g g h (sf) d d d
Store (uc) i f i g g h (sf) d d d
Store (wc, wc+, non-temporal) e (mf) f e (mf) j (sf) g, m h (sf) d d d
Load/Store (io) k k k k k l d, k d, k d, k
Lock (atomic) k k k k k k d, k d, k d, k
Serialize instruction/ 
Interrupts/Exceptionsl l l l l l d, l d, l d, l
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l — All loads and stores complete to memory for the serializing instruction before the subsequent
instruction fetch is issued.
m — A store (uc) does not pass a previous store (wc, wc+).
7.5 Buffering and Combining Memory Writes
7.5.1  Write Buffering
Writes to memory (main memory and caches) can be stored internally by the processor in write buffers 
(also known as store buffers) before actually writing the data into a memory location. System 
performance can be improved by buffering writes, as shown in the following examples:
•When higher-priority memory transactions, such as reads, compete for memory access with writes,
writes can be delayed in favor of reads, which minimizes or eliminates an instruction-executionstall due to a memory-operand read.
•When the memory is busy, buffering writes while the memory is busy removes the writes from theinstruction-execution pipeline, which frees instruction-execution resources.
The processor manages the write buffer so that it is transparent to software. Memory accesses check the write buffer, and the processor completes writes into memory from the buffer in program order. Also, the processor completely empties the write buffer by writing the contents to memory as a result of performing any of the following operations:
•SFENCE Instruction—Executing a store-fence (SFENCE) instruction forces all memory writes
before the SFENCE (in program order) to be written into memory (or, for WB type, the cache)before memory writes that follow the SFENCE instruction. The memory-fence (MFENCE)instruction has a similar effect, but it forces the ordering of loads in addition to stores.
•Serializing Instructions —Executing a serializing instruction forces the processor to retire the
serializing instruction (complete both instruction execution and result writeback) before the nextinstruction is fetched from memory.
•I/O instructions —Before completing an I/O instruction, all previous reads and writes must be
written to memory, and the I/O instruction must complete before completing subsequent reads orwrites. Writes to I/O-address space (OUT instruction) are never buffered.
•Locked Instructions—A locked instruction (an instruction executed using the LOCK prefix) or anXCHG instruction (which is implicitly locked) must complete after all previous reads and writes
and before  subsequent reads and writes. Locked writes are never buffered, although locked reads
and writes are cacheable.
•Interrupts and Exceptions—Interrupts and exceptions, including virtualization intercepts(#VMEXIT), are serializing events that force the processor to write all results from the write bufferto memory before fetching the first instruction from the interrupt or exception service routine.
•UC Memory Reads —UC memory reads are not reordered ahead of writes.
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Write buffers can behave similarly to write-combining buffers because multiple writes may be 
collected internally before transferring the data to caches or main memory. See the following section 
for a description of write combining. 
7.5.2  Write Combining
Write-combining memory uses a different buffering scheme than write buffering described above. 
Writes to write-combining (WC) memory can be combined internally by the processor in a buffer for more efficient transfer to main memory at a later time. For example, 16 doubleword writes to consecutive memory addresses can be combined in the WC buffers and transferred to main memory as a single burst operation rather than as individual memory writes. 
The following instructions perform writes to WC memory:
•(V)MASKMOVDQU 
•MASKMOVQ
•(V)MOVNTDQ
•MOVNTI
•(V)MOVNTPD
•(V)MOVNTPS
•MOVNTQ
•MOVNTSD
•MOVNTSS
WC memory is not cacheable. A WC buffer writes its contents only to main memory.
The size and number of WC buffers available is implementation dependent. The processor assigns an 
address range to an empty WC buffer when a WC-memory write occurs. The size and alignment of this address range is equal to the buffer size. All subsequent writes to WC memory that fall within this address range can be stored by the processor in the WC-buffer entry until an event occurs that causes the processor to write the WC buffer to main memory. After the WC buffer is written to main memory, the processor can assign a new address range on a subsequent WC-memory write.
Writes to consecutive addresses in WC memory are not required for the processor to combine them.

•MASKMOVQ
•MOVNTI
•MOVNTQ
•MOVNTSD
•MOVNTSS
Writes to consecutive addresses in WC memory are not required for the processor to combine them. 
The processor combines any WC memory write that falls within the active-address range for a buffer. Multiple writes to the same address overwrite each other (in program order) until the WC buffer is written to main memory. 
It is possible for writes to proceed out of program order when WC memory is used. For example, a 
write to cacheable memory that follows a write to WC memory can be written into the cache before the WC buffer is written to main memory. For this reason, and the reasons listed in the previous paragraph, software that is sensitive to the order of memory writes should avoid using WC memory.
WC buffers are written to main memory under the same conditions as the write buffers, namely when:
•Executing a store-fence (SFENCE) instruction.
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•Executing a serializing instruction.
•Executing an I/O instruction. 
- Executing an MMIO access (load or store to UC memory type)
•Executing a locked instruction (an instruction executed using the LOCK prefix).
•Executing an XCHG instruction 
•An interrupt or exception occurs.
WC buffers are also written to main memory when:
•A subsequent non-write-combining operation has a write address that matches the WC-buffer
active-address range.
•A write to WC memory falls outside the WC-buffer active-address range. The existing buffercontents are written to main memory, and a new address range is established for the latest WCwrite.
7.6 Memory Caches
The AMD64 architecture supports the use of internal and external caches. The size, organization, coherency mechanism, and replacement algorithm for each cache is implementation dependent. Generally, the existence of the caches is transparent to both application and system software. In some cases, however, software can use cache-structure information to optimize memory accesses or manage memory coherency. Such software can use the extended-feature functions of the CPUID instruction to gather information on the caching subsystem supported by the processor. For more information, see Section 3.3, “Processor Feature Identification,” on page 71.
7.6.1  Cache Organization and Operation
Although the detailed organization of a processor cache depends on the implementation, the general 
constructs are similar. L1 caches—data and instruction, or unified—and L2 caches usually are implemented as n-way set-associative caches. Figure 7-3 on page 204 shows a typical logical  
organization of an n-way set-associative cache. The physical implementation of the cache can be quite different.
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Figure 7-3. Cache Organization Example
As shown in Figure 7-3, the cache is organized as an array of cache lines. Each cache line consists of 
three parts: a cache-data line (a fixed-size copy of a memory block), a tag, and other information. 
Rows of cache lines in the cache array are sets, and columns of cache lines are ways. In an n-way set-
associative cache, each set is a collection of n lines. For example, in a four-way set-associative cache, each set is a collection of four cache lines, one from each way.513-213.epsPhysical Address
Tag Field Index Field Offset Field= = =Tag Data Other
.  .  .Set 1
Set 2
Set 3Set 0
Set m-1Tag Data Other Tag Data Other.  .  .Way 1 Way 0 Way n-1
Line Data 0,2 Line Data 1,2 Line Data n-1,2
MUX n:1HitMiss Miss Miss
HitHit.  .  .
Data
Hit DataCache
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The cache is accessed using the physical address of the data or instruction being referenced. To access 
data within a cache line, the physical address is used to select the set, way, and byte from the cache. This is accomplished by dividing the physical address into the following three fields:
•Index— The index field  selects the cache set (row) to be examined for a hit. All cache lines within
the set (one from each way) are selected by the index field.
•Tag— The tag field is used to select a specific cache line from the cache set. The physical-address
tag field is compared with each cache-line tag in the set. If a match is found, a cache hit is signaled,
and the appropriate cache line is selected from the set. If a match is not found, a cache miss issignaled.
•Offset— The offset field  points to the first byte in the cache line corresponding to the memory
reference. The referenced data or instruction value is read from (or written to, in the case ofmemory writes) the selected cache line starting at the location selected by the offset field.
In Figure 7-3 on page 204, the physical-address index field is shown selecting Set 2 from the cache. 
The tag entry for each cache line in the set is compared with the physical-address tag field. The tag entry for Way 1 matches the physical-address tag field, so the cache-line data for Set 2, Way 1 is selected using the n:1 multiplexer. Finally, the physical-address offset field is used to point to the first 
byte of the referenced data (or instruction) in the selected cache line.
Cache lines can contain other information in addition to the data and tags, as shown in Figure 7-3 on 
page 204. MOESI state and the state bits associated with the cache-replacement algorithm are typical 
pieces of information kept with the cache line. Instruction caches can also contain pre-decode or branch-prediction information. The type of information stored with the cache line is implementation dependent.
Self-Modifying Code.  Software that stores into its own pending instruction stream with the intent of 
then executing the modified instructions is classified as self-modifying code. To support self-modifying code, AMD64 processors will flush any lines from the instruction cache that such stores hit, and will additionally check whether an instruction being modified is already in decode or execution behind the store instruction. If so, it will flush the pipeline and restart instruction fetch to acquire and re-decode the updated instruction bytes. No special action is needed by software for such updates to be immediately recognized. As with cache coherency, the check for instructions that are in flight is performed using physical addresses to avoid aliasing issues that could arise with virtual (linear) addresses.
When the modified bytes are in cacheable memory, the data cache may retain a copy of the modified 
cache line in a shared state, and the instruction cache refill may be satisfied from any suitable place in the memory hierarchy in a model-dependent manner that maintains cache coherency.
Cross-Modifying Code.  Software that stores into the active instruction stream of another executing 
thread with the intent that the other thread subsequently execute the modified instruction stream is classified as cross-modifying code. There are two approaches to consider: asynchronous modification and synchronous modification.
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Asynchronous modification.  This is done with a write to the target instruction stream with no 
particular coordination being done between the writing and receiving threads. The nature of the code 
being executed by the target thread is such that it is insensitive to the exact timing of the update, for example executing in a known loop until an update to a branch instruction's offset takes it down a new path (or an update to an immediate operand, or opcode, or other instruction field). Such modifications must be done via a single store to the target thread's instruction stream that is contained entirely within a naturally-aligned quadword, and is subject to the constraints given here. A key aspect is that, although the store is performed atomically, the affected quadword may be read more than once in the process of extracting instruction bytes from it. This can result in the following scenarios resulting from a single store:
1. An update to two successive instructions, A and B, to A' and B' may result in execution of an A-B'
sequence rather than A'-B'. However it will not result in an A'-B sequence since stores become
visible to instruction fetchers in program order, and instruction fetchers read memory sequentiallybetween taken branches.
2. A modification to one instruction A that changes it to two instructions A'-B will only result in
execution of A'-B. 
3. A modification to two instructions A-B that combines them into one instruction A' may result in a
sequence of A-X, where X starts at the point in A' where B previously started. 
Note that since stores to the instruction stream are observed by the instruction fetcher in program order, one can do multiple modifications to an area of the target thread's code that is beyond reach of the thread's current control flow, followed by a final asynchronous update that alters the control flow to expose the modified code to fetching and execution.
If the desired action cannot be achieved within these constraints, a synchronous modification approach 
must be used for reliable operation.

Synchronous modification.   This entails a producer-consumer approach to the modification, where 
the target thread waits on a signal from the modifying thread, such as changing the state of a shared variable, before executing the modified code. The modifying thread writes to the target instruction bytes in any desired manner, then writes the synchronizing variable to release the target thread. Upon release, the target thread must then execute a serializing instruction such as CPUID or MFENCE (a locked operation is not sufficient) before proceeding to the modified code to avoid executing a stale view of the instructions which may have been speculatively fetched. Note that such speculative fetching is a function of branch predictor operation which is completely beyond the control of software.
See V olume 1, Chapter 3, “Semaphores,” for a discussion of instructions that are useful for 
interprocessor synchronization.
7.6.2  Cache Control Mechanisms
The AMD64 architecture provides a number of mechanisms for controlling the cacheability of 
memory. These are described in the following sections.
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Cache Disable.  Bit 30 of the CR0 register is the cache-disable bit, CR0.CD. Caching is enabled 
when CR0.CD is cleared to 0, and caching is disabled when CR0.CD is set to 1. When caching is 
disabled, reads and writes access main memory.
Software can disable the cache while the cache still holds valid data (or instructions). If a read or write 
hits the L1 data cache or the L2 cache when CR0.CD=1, the processor does the following:
1. Writes the cache line back if it is in the modified or owned state.2. Invalidates the cache line.3. Performs a non-cacheable main-memory access to read or write the data.
If an instruction fetch hits the L1 instruction cache when CR0.CD=1, some processor models may read 
the cached instructions rather than access main memory. When CR0.CD=1, the exact behavior of L2 and L3 caches is model-dependent, and may vary for different types of memory accesses.
The processor also responds to cache probes when CR0.CD=1. Probes that hit the cache cause the 
processor to perform Step 1. Step 2 (cache-line invalidation) is performed only if the probe is performed on behalf of a memory write or an exclusive read.
Writethrough Disable.  Bit 29 of the CR0 register is the not writethrough disable bit, CR0.NW. In 
early x86 processors, CR0.NW is used to control cache writethrough behavior, and the combination of CR0.NW and CR0.CD determines the cache operating mode.
In early x86 processors , clearing CR0.NW to 0 enables writeback caching for main memory, 
effectively disabling writethrough caching for main memory. When CR0.NW=0, software can disable 
writeback caching for specific memory pages or regions by using other cache control mechanisms. When software sets CR0.NW to 1, writeback caching is disabled for main memory, while writethrough caching is enabled.
In implementations of the AMD64 architecture , CR0.NW is not used to qualify the cache operating 
mode established by CR0.CD. Table 7-5 shows the effects of CR0.NW and CR0.CD on the AMD64 
architecture cache-operating modes.
Page-Level Cache Disable.  Bit 4 of all paging data-structure entries controls page-level cache 
disable (PCD). When a data-structure-entry PCD bit is cleared to 0, the page table or physical page pointed to by that entry is cacheable, as determined by the CR0.CD bit. When the PCD bit is set to 1, the page table or physical page is not cacheable. The PCD bit in the paging data-structure base-register Table 7-5. AMD64 Architecture Cache-Operating Modes
CR0.CD CR0.NW Cache Operating Mode
0 0 Cache enabled with a writeback-caching policy.
0 1 Invalid setting—causes a general-protection exception (#GP).
1 0
Cache disabled. See “Cache Disable” on page 207 .1 1
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(bit 4 in CR3) controls the cacheability of the highest-level page table in the page-translation 
Page-Level Writethrough Enable.  Bit 3 of all paging data-structure entries is the page-level 
writethrough enable control (PWT). When a data-structure-entry PWT bit is cleared to 0, the page table or physical page pointed to by that entry has a writeback caching policy. When the PWT bit is set to 1, the page table or physical page has a writethrough caching policy. The PWT bit in the paging data-structure base-register (bit 3 in CR3) controls the caching policy of the highest-level page table in the page-translation hierarchy.
The corresponding PCD bit must be cleared to 0 (page caching enabled) for the PWT bit to have an 
effect.
Memory Typing.  Two mechanisms are provided for software to control access to and cacheability of 
specific memory regions: 
•The memory-type range registers (MTRRs) control cacheability based on physical addresses. See
“MTRRs” on page 217 for more information on the use of MTRRs.
•The page-attribute table (PAT) mechanism controls cacheability based on virtual addresses. PATextends the capabilities provided by the PCD and PWT page-level cache controls. See “Page-Attribute Table Mechanism” on page 226 for more information on the use of the PAT mechanism.
System software can combine the use of both the MTRRs and PAT mechanisms to maximize control over memory cacheability.
If the MTRRs are disabled in implementations that support the MTRR mechanism, the default 
memory type is set to uncacheable (UC). Memory accesses are not cached even if the caches are enabled by clearing CR0.CD to 0. Cacheable memory types must be established using the MTRRs in order for memory accesses to be cached.
Cache Control Precedence.  The cache-control mechanisms are used to define the memory type and 
cacheability of main memory and regions of main memory. Taken together, the most restrictive memory type takes precedence in defining the caching policy of memory. The order of precedence is:
1. Uncacheable (UC)2. Write-combining (WC)3. Write-protected (WP)4. Writethrough (WT)5. Writeback (WB)
For example, assume a large memory region is designated a writethrough type using the MTRRs. 
Individual pages within that region can have caching disabled by setting the appropriate page-table PCD bits. However, no pages within that region can have a writeback caching policy, regardless of the page-table PWT values.
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7.6.3  Cache and Memory Management Instructions
Data Prefetch.  The prefetch instructions are used by software as a hint to the processor that the 
referenced data is likely to be used in the near future. The processor can preload the cache line 
containing the data in anticipation of its use. PREFETCH provides a hint that the data is to be read. PREFETCHW provides a hint that the data is to be written. The processor can mark the line as modified if it is preloaded using PREFETCHW.
Memory Ordering.  Instructions are provided for software to enforce memory ordering (serialization) 
in weakly-ordered memory types. These instructions are:
•SFENCE (store fence) —forces all memory writes (stores) preceding the SFENCE (in program
order) to be written into memory before memory writes following the SFENCE.
•LFENCE (load fence) —forces all memory reads (loads) preceding the LFENCE (in program
order) to be read from memory before memory reads following the LFENCE. In some systems,
LFENCE may be configured to be dispatch serializing. In systems where CPUIDFn8000_0021_EAX[LFenceAlwaysSerializing] (bit 2) = 1, LFENCE is always dispatchserializing. 
•MFENCE (memory fence)—forces all memory accesses (reads and writes) preceding theMFENCE (in program order) to be written into or read from memory before memory accessesfollowing the MFENCE.
Cache Line Writeback and Flush.  The CLFLUSH instruction (writeback, if modified, and 
invalidate) takes the byte memory-address operand (a linear address), and checks to see if the address is cached. If the address is cached, the entire cache line containing the address is invalidated. If any portion of the cache line is dirty (in the modified or owned state), the entire line is written to main memory before it is invalidated. CLFLUSH affects all caches  in the memory hierarchy—internal and 
external to the processor, and across all cores. The CLWB instruction operates in the same manner except it does not invalidate the cache line. The checking and invalidation process continues until the address has been updated in memory and, for CLFLUSH, invalidated in all caches.
In most cases, the underlying memory type assigned to the address has no effect on the behavior of this

In most cases, the underlying memory type assigned to the address has no effect on the behavior of this 
instruction. However, when the underlying memory type for the address is UC or WC (as defined by the MTRRs), the processor does not proceed with checking all caches to see if the address is cached. In both cases, the address is uncacheable, and invalidation is unnecessary. Write-combining buffers are written back to memory if the corresponding physical address falls within the buffer active-address range.
Cache Writeback and Invalidate.  Unlike the CLFLUSH and CLWB instructions, the WBINVD and 
WBNOINVD instructions operate on the entire cache, rather than a single cache line. The WBINVD and WBNOINVD instructions first write back all cache lines that are dirty (in the modified or owned 
state) to main memory. After writeback is complete, the WBINVD instruction additionally invalidates 
all cache lines. The checking and invalidation process continues until all internal caches in the executing core's path to system memory are invalidated. In some implementations this may include caches in other branches of the system's cache hierarchy; see the description of these instructions in 
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volume 3 for more detail. For either instruction, a special bus cycle is transmitted to higher-level 
external caches directing them to perform a writeback-and-invalidate operation. 
Cache Invalidate.  The INVD instruction is used to invalidate all cache lines. Unlike the WBINVD 
instruction, dirty cache lines are not written to main memory. The process continues until all internal caches have been invalidated. A special bus cycle is transmitted to higher-level external caches directing them to perform an invalidation. 
The INVD instruction should only be used in situations where memory coherency is not required.
7.6.4  Serializing Instructions
Serializing instructions force the processor to retire the serializing instruction and all previous 
instructions before the next instruction is fetched. A serializing instruction is retired when the following operations are complete:
•The instruction has executed.
•All registers modified by the instruction are updated.
•All memory updates performed by the instruction are complete.
•All data held in the write buffers have been written to memory.
Serializing instructions can be used as a barrier between memory accesses to force strong ordering of 
memory operations. Care should be exercised in using serializing instructions because they modify processor state and may affect program flow. The instructions also force execution serialization, which can significantly degrade performance. When strongly-ordered memory accesses are required, but execution serialization is not, it is recommended that software use the memory-ordering instructions described on page 209. 
The following are serializing instructions:
•Non-Privileged Instructions
- CPUID- IRET- RSM- MFENCE
•Privileged Instructions- MOV CRn- MOV DRn- LGDT, LIDT, LLDT, LTR- WRMSR (see note 1) - WBINVD, WBNOINVD, INVD- INVLPG
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Note 1: Writes to the following MSRs are not serializing: SPEC_CTRL, PRED_CMD, all x2APIC 
MSRs.
A dispatch serializing instruction is a lighter form of ordering than a serializing instruction. A dispatch 
serializing instruction forces the processor to retire the serializing instruction and all previous instructions before the next instruction is executed. In some systems, LFENCE may be configured to be dispatch serializing. In systems where CPUID Fn8000_0021_EAX[LFenceAlwaysSerializing](bit 2) = 1, LFENCE is always dispatch serializing.
7.6.5  Cache and Processor Topology
Cache and processor topology information is useful in the optimal management of system and 
application resources. Exposing processor and cache topology information to the programmer allows software to make more efficient use of hardware multithreading resources delivering optimal performance. Shared resources in a specific cache and processor topology may require special consideration in the optimization of multiprocessing software performance.
The processor topology allows software to determine which cores or logical processors are siblings in 
a compute unit, node, and processor package. For example, a scheduler can then choose to either compact or scatter threads (or processes) to cores in compute units, nodes, or across the cores in the entire physical package in order to optimize for a power and performance profile.
Topology extensions define processor topology at both the node, compute unit and cache level. 
Topology extensions include cache properties with sharing and the processor topology identified. The result is a simplified extension to the CPUID instruction that describes the processors cache topology and leverages existing industry cache properties folded into AMD’s topology extension description.
Topology extensions definition supports existing and future processors with varying degrees of cache 
level sharing. Topology extensions also support the description of a simple compute unit with one core or packages where the number of cores in a node and/or compute unit are not an even power of two.
CPUID Function 8000_001D: Cache Topology Definition.  CPUID Function 8000_001D describes 
the hierarchical relationships of cache levels relative to the cores which share these resources. Function 8000_001D is defined to be called iteratively with the value 8000001Dh in EAX and an additional parameter in ECX. To gather information for all cache levels, software must execute the CPUID instruction with 8000001Dh in EAX and ECX set to increasing values beginning with 0 until a value of 0 is returned from EAX[4:0], which indicates no more cache descriptions.
If software dynamically manages cache configuration, it will need to update any stored cache 
properties for the processor.
CPUID Function 8000_001E: Processor Topology Definition.  CPUID Function 8000_001E 
describes processor topology with component identifiers. To read the processor topology, definition software calls the CPUID instruction with the value 8000001Eh in EAX. After execution, the APIC ID is represented in EAX. EBX contains the compute unit description in the processor, while ECX contains system unique node identification. Software may read this information once for each core.
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CPUID Function 8000_0026: Extended CPU Topology.  CPUID Fn8000_0026 reports extended 
topology level information, including heterogenous topology, for the cores within the system. The 
topology level is selected by the value passed to the instruction in ECX. To discover the topology of a system, software should execute the CPUID instruction with an EAX value of 80000026h and increasing values of ECX, starting with a value of zero, until CPUID Fn8000_0026_ECX[LevelType](bits 15:8) returns zero. More information about CPUID Fn8000_0026 can be found in Appendix E of V olume 3.
The following CPUID functions provide processor topology information:
•CPUID Fn8000_0001_ECX
•CPUID Fn8000_0008_ECX
•CPUID Fn8000_001D_EAX, EBX, ECX, EDX
•CPUID Fn8000_001E_EAX, EBX, ECX
•CPUID Fn8000_0026_EAX, EBX, ECX, EDX
For more information using the CPUID instruction, see Section 3.3, “Processor Feature 
Identification,” on page 71.
7.6.6  L3 Cache Range Reservation
The L3 Cache Range Reservation feature allows a portion of the L3 cache to be reserved for a specific 
system physical address range. This capability is intended to reduce access latency for a specified range of memory by keeping it in the L3 cache as much as possible, which may be useful in some latency-sensitive applications. However, it does not provide a guaranteed level of performance. Since many factors can affect the performance of a particular process, performance evaluation of specific configurations is critical to determining whether to enable the L3 Range Reservation feature. Further details are provided in the following subsections.
CPUID Feature Flag.  Support for the L3 Cache Range Reservation feature is indicated by CPUID 
Fn8000_0020_EBX[L3RR] (bit 4) = 1.
L3 Range Reservation Registers.  The following MSRs are used to program L3 Range Reservation:
•L3 Range Reserve Base Address Register (C001_1095h)
•L3 Range Reserve Maximum Address Register (C001_1096h)
•L3 Range Reserve Way Mask (C001_109Ah)
L3 Range Reservation MSR layouts are shown below. The MSR bit position numbering uses P and W, 
where:
•P is equal to the value of CPUID Fn8000_0008_EAX[PhysAddrSize].
•W is equal to the value of CPUID Fn8000_001D_EBX_x03[CacheNumWays].
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L3 Range Reserve Base Address  
Figure 7-4. L3 Range Reserve Base Address Register (L3RangeReserveBaseAddr)
L3 Range Reserve Maximum Address
 
Figure 7-5. L3 Range Reserve Maximum Address Register 
(L3RangeReserveMaxAddr)63 P P-1 32
Reserved BaseAddr[P-1:32]
31 12 11 0
Base[Addr31:12] Reserved
63:P Reserved MBZ

where:
 
31 12 11 0
P-1:12 BaseAddr[P-1:12] Base Address, 4KB aligned SPA R/W
11:0 Reserved MBZ
63 P P-1 32
Reserved MaxAddr[P-1:32]
31 12 11 0
MaxAddr[31:12] Reserved En
P-1:12 MaxAddr[P-1:12] Maximum Address, 4KB aligned SPA R/W
11:1 Reserved MBZ
0 En Enable R/W
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L3 Range Reserve Way Mask
Figure 7-6. L3 Range Reserve Way Mask Register (L3RangeReserveWayMask)
L3 Range Reservation Register Programming.  A system physical address A is in the reserved 
range if:
BaseAddr[P-1:12] <= A[P-1:12] < MaxAddr[P-1:12]
The L3 ways enabled for use by cache lines in the reserved range will be referred to as the reserved 
region of the cache.
To enable the L3 Range Reservation feature, software must follow the following sequence of MSR 
writes: 
1. Write MSR C001_109Ah to program the WayMask[W-1:0] field.2. Write MSR C001_1095h to program the BaseAddr[P-1:12] field.3. Write MSR C001_1096h to program the MaxAddr[P-1:12] field and set En to 1.
To disable the L3 Range Reservation feature, set En to zero.See “Programming Considerations” on page 215 for other requirements and considerations.
Range Reservation used as Range Lock.  The L3 Range Reservation feature can be used to lock 
the reserved range of addresses in the L3 cache in the reserved region. To accomplish this, software 
must calculate the size of the L3 cache using the following fields of CPUID information:
•CacheNumSets from CPUID Fn8000001D_ECX_x03.
•CacheLineSize from CPUID Fn8000001D_EBX_x03.
Using the above parameters, the L3 cache size per-way in bytes is calculated as:
L3SizePerWay = CacheNumSets * (CacheLineSize + 1).63 32
Reserved
31 0
Reserved WayMask[W-1:0]
63:W Reserved MBZ
W-1:0 WayMask[W-1:0]Way Mask, WayMask[n]=1 allocates L3 
way n to range reserved addresses.R/W
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Software can determine the size of the reserved range it wishes to lock in bytes and allocate as many 
L3-ways as needed by programming the WayMask field in MSR C001_109Ah. Software must set 
CR0.CD on all logical processors sharing the L3 cache and execute the WBINVD instruction to flush the L3 cache before enabling the Range Reservation feature. If the size of the reserved range is less than the number of bytes of L3 cache allocated by the WayMask field in MSR C001_109Ah, the 
reserved range will remain “locked” in cache. The reserved range follows coherency rules around evictions, probes, and cache flushes. If the size of the reserved range does not fit in the allocated L3 ways as programmed in the WayMask field in MSR C001_109Ah, the cache lines within the reserved 
range are replaced using normal L3 cache replacement policy, in those allocated L3 ways. However, the reserved region is only used by cache lines in the reserved range.
Range Reservation Operation.  The scope of L3 range reservation is limited to an L3 cache and the 
cores sharing that L3 cache. Setting up a reserved range reserves a portion of the corresponding cache for use by a range of system physical addresses but does not bring the data or instructions at those addresses into the cache. The cache is filled with the data or instructions from the reserved address region as those addresses are accessed by the associated logical processors, either through explicit references by software, by hardware-based prefetching or by speculative execution of instructions which may or may not eventually retire. After the L3 range reservation is enabled, the cache lines with addresses in the reserved range are cached in the reserved region of the L3 cache. The cache lines with addresses outside the reserved range are cached in the unreserved region of the L3 cache.
Whether L3 range reservation is enabled or disabled, a cache line in the reserved range will still 
behave coherently with respect to all coherent operations. Placing a cache line in a reserved location does not exempt it from the rules of coherency. In case where a cache line outside the reserved range is present in the reserved region at the time the L3 range reservation feature is enabled or where a cache line in the reserved range is present in unreserved regions of the cache, normal coherent accesses by any processor in the system will still read the correct, current data from these locations. 
Programming Considerations.  The Range Reservation configuration registers should not be 
modified while cacheable traffic is in flight. The recommended way to meet this requirement is to set the CR0.CD bit on all logical processors which are connected to the cache being configured. For the L3 cache, that includes all the logical processors sharing an L3 cache and for the L2 cache that includes the two logical processors which share a physical core and L2 cache.
If a given range is reserved in multiple L3 caches in a system, the cache lines can be cached in each of 
them as long as none of the logical processors accessing the data modify it. Modifying the cache lines will remove them from all other caches. However, once the modification is complete the cache lines can once again be re-cached in multiple caches if accessed by those processors. The cache lines thus accessed are again placed in the reserved region of the L3 cache upon access. It is not necessary to disable and re-enable the address range in order to re-establish the reserved region; the affected addresses will be brought into the reserved cache regions again as they are accessed, although the initial accesses to those ranges will incur the latency penalty associated with retrieving the data or instructions from memory or another cache.
Setting up a reserved range does not affect the cacheability rules of the addresses in that range. For 
example, if the page tables specify that the memory type for a page is UC, including that page within a 
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range reserved region will not cause the addresses on that page to become cacheable. Instead, a portion 
of the cache will become unusable by any address since the addresses for which that portion of cache is reserved cannot be installed in the cache and all other addresses are prevented from being installed there.
When Secure Memory Encryption (SME) or Secure Encrypted Virtualization (SEV) is enabled, the L3 
range reservation feature cannot be used on system physical addresses that are encrypted. See “Secure Memory Encryption” on page 237 and “Secure Encrypted Virtualization” on page 588 for details. 
Reserving a way of the L3 cache for range reservation exempts those ways from being used by the L3 QoS Allocation feature. The ways that overlap between any of the L3 QoS Allocation Mask MSRs 
(MSR 0x0000_0C90h through 0x0000_0C9Fh) will be unavailable for use by the L3 QoS Allocation feature and only available for use by the L3 Range Reservation feature.
7.7 Memory-Type Range Registers
The AMD64 architecture supports three mechanisms for software access-control and cacheability-control over memory regions. These mechanisms can be used in place of similar capabilities provided by external chipsets used with early x86 processors.
This section describes a control mechanism that uses a set of programmable model-specific registers 
(MSRs) called the memory-type-range registers  (MTRRs). The MTRR mechanism provides system 
software with the ability to manage hardware-device memory mapping. System software can characterize physical-memory regions by type (e.g., ROM, flash, memory-mapped I/O) and assign hardware devices to the appropriate physical-memory type. 
Another control mechanism is implemented as an extension to the page-translation capability and is 
called the page attribute table  (PAT). It is described in “Page-Attribute Table Mechanism” on 
page 226. Like the MTRRs, PAT provides system software with the ability to manage hardware-device memory mapping. With PAT, however, system software can characterize physical pages and assign virtually-mapped devices to those physical pages using the page-translation mechanism. PAT may be used in conjunction with the MTTR mechanism to maximize flexibility in memory control.
Finally, control mechanisms are provided for managing memory-mapped I/O. These mechanisms 
employ extensions to the MTRRs and a separate feature called the top-of-memory registers . The 
MTRR extensions include additional MTRR type-field encodings for fixed-range MTRRs and variable-range I/O range registers (IORRs). These mechanisms are described in “Memory-Mapped I/O” on page 231.
7.7.1  MTRR Type Fields
The MTRR mechanism provides a means for associating a physical-address range with a memory type 
(see “Memory Types” on page 196). The MTRRs contain a type field used to specify the memory type in effect for a given physical-address range. 
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There are two variants of the memory type-field encodings: standard and extended. Both the standard 
and extended encodings use type-field bits 2:0 to specify the memory type. For the standard encodings, bits 7:3 are reserved and must be zero. For the extended encodings, bits 7:5 are reserved, but bits 4:3 are defined as the RdMem and WrMem bits. “Extended Fixed-Range MTRR Type-Field Encodings” on page 231 describes the function of these extended bits and how software enables them. 
Only the fixed-range MTRRs support the extended type-field encodings. Variable-range MTRRs use the standard encodings.
Table 7-6 on page 217 shows the memory types supported by the MTRR mechanism and their 
encoding in the MTRR type fields referenced throughout this section. Unless the extended type-field encodings are explicitly enabled, the processor uses the type values shown in Table 7-6.
memory type is set to uncacheable (UC). Memory accesses are not cached even if the caches are 
enabled by clearing CR0.CD to 0.  Cacheable memory types must be established using the MTRRs to 
enable memory accesses to be cached.
7.7.2  MTRRs
Both fixed-size and variable-size address ranges are supported by the MTRR mechanism. The fixed-
size ranges are restricted to the lower 1 Mbyte of physical-address space, while the variable-size ranges can be located anywhere in the physical-address space.
Figure 7-7 on page 218 shows an example mapping of physical memory using the fixed-size and 
variable-size MTRRs. The areas shaded gray are not mapped by the MTRRs. Unmapped areas are set 
to the software-selected default memory type. Table 7-6. MTRR Type Field Encodings
Type Value Type Name Type Description
00h UC—UncacheableAll accesses are uncacheable. Write combining is not 
allowed. Speculative accesses are not allowed
01h WC—Write-CombiningAll accesses are uncacheable. Write combining is allowed. Speculative reads are allowed
04h WT—WritethroughReads allocate cache lines on a cache miss. Cache lines are not allocated on a write miss. Write hits update the cache and main memory.
05h WP—Write-ProtectReads allocate cache lines on a cache miss. All writes update main memory. Cache lines are not allocated on a write miss. Write hits invalidate the cache line and update main memory.
06h WB—WritebackReads allocate cache lines on a cache miss, and can allocate to either the shared, exclusive, or modified state. Writes allocate to the modified state on a cache miss.
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Figure 7-7. MTRR Mapping of Physical Memory
MTRRs are 64-bit model-specific registers (MSRs). They are read using the RDMSR instruction and 
written using the WRMSR instruction. See “Memory-Typing MSRs” on page 720 for a listing of the MTRR MSR numbers. The following sections describe the types of MTRRs and their function.
Fixed-Range MTRRs.  The fixed-range MTRRs are used to characterize the first 1 Mbyte of physical 
memory. Each fixed-range MTRR contains eight type fields for characterizing a total of eight memory ranges. Fixed-range MTRRs support extended type-field encodings as described in “Extended Fixed-Range MTRR Type-Field Encodings” on page 231. The extended type field allows a fixed-range MTRR to be used as a fixed-range IORR. Figure 7-8 on page 219 shows the format of a fixed-range 
MTRR.513-214.eps0F_FFFFh10_0000h0_FFFF_FFFF_FFFFh
256 Kbytes
256 Kbytes
512 KbytesPhysical Memory
Up to 8 Variable Ranges
64 4-Kbyte Ranges
16 16-Kbyte Ranges
8 64-Kbyte RangesDefault (Unmapped) Ranges
00_0000h
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Figure 7-8. Fixed-Range MTRR
For the purposes of memory characterization, the first 1 Mbyte of physical memory is segmented into 
a total of 88 non-overlapping memory ranges, as follows:
•The 512 Kbytes of memory spanning addresses 00_0000h to 07_FFFFh are segmented into eight
64-Kbyte ranges. A single MTRR is used to characterize this address space.
•The 256 Kbytes of memory spanning addresses 08_0000h to 0B_FFFFh are segmented into 16 16-Kbyte ranges. Two MTRRs are used to characterize this address space.
•The 256 Kbytes of memory spanning addresses 0C_0000h to 0F_FFFFh are segmented into 64 4-Kbyte ranges. Eight MTRRs are used to characterize this address space.
Table 7-7 shows the address ranges corresponding to the type fields within each fixed-range MTRR. The gray-shaded heading boxes represent the bit ranges for each type field in a fixed-range MTTR. See Table 7-6 on page 217 for the type-field encodings.63 56 55 48 47 40 39 32
Type Type Type Type
31 24 23 16 15 8 7 0
Table 7-7. Fixed-Range MTRR Address Ranges
Physical Address Range (in hexadecimal)Register Name63–56 55–48 47–40 39–32 31–24 23–16 15–8 7–0
70000–7
FFFF60000–6FFFF50000–5FFFF40000–4FFFF30000–3FFFF20000–2FFFF10000–1FFFF00000–0FFFFMTRRfix64K_00000
9C000–9FFFF98000–9BFFF94000–97FFF90000–93FFF8C000–8FFFF88000–8BFFF84000–87FFF80000–83FFFMTRRfix16K_80000
BC000–BFFFFB8000–BBFFFB4000–B7FFFB0000–B3FFFAC000–AFFFFA8000–ABFFFA4000–A7FFFA0000–A3FFFMTRRfix16K_A0000
C7000–C7FFFC6000–C6FFFC5000–C5FFFC4000–C4FFFC3000–C3FFFC2000–C2FFFC1000–C1FFFC0000–C0FFFMTRRfix4K_C0000
CF000–CFFFFCE000–CEFFFCD000–CDFFFCC000–CCFFFCB000–CBFFFCA000–CAFFFC9000–C9FFFC8000–C8FFFMTRRfix4K_C8000
D7000–D7FFFD6000–D6FFFD5000–D5FFFD4000–D4FFFD3000–D3FFFD2000–D2FFFD1000–D1FFFD0000–D0FFFMTRRfix4K_D0000
DF000–DFFFFDE000–DEFFFDD000–DDFFFDC000–DCFFFDB000–DBFFFDA000–DAFFFD9000–D9FFFD8000–D8FFFMTRRfix4K_D8000
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Variable-Range MTRRs.  The variable-range MTRRs can be used to characterize any address range 
within the physical-memory space, including all of physical memory. Up to eight address ranges of 
varying sizes can be characterized using the MTRR. Two variable-range MTRRs are used to characterize each address range: MTRRphysBase n and MTRRphysMask n (n is the address-range 
number from 0 to 7). For example, address-range 3 is characterized using the MTRRphysBase3 and MTRRphysMask3 register pair.
Figure 7-9 shows the format of the MTRRphysBase n register and Figure 7-10 on page 221 shows the 
format of the MTRRphysMaskn register. The fields within the register pair are read/write. 
MTRRphysBase n Registers.  The fields in these variable-range MTRRs, shown in Figure 7-9, are:
•Type—Bits 7:0. The memory type used to characterize the memory range. See Table 7-6 on
page 217 for the type-field encodings. Variable-range MTRRs do not support the extended type-field encodings.
•Range Physical Base-Address (PhysBase)—Bits 51:12. The memory-range base-address inphysical-address space. PhysBase is aligned on a 4-Kbyte (or greater) address in the 52-bitphysical-address space supported by the AMD64 architecture. PhysBase represents the most-significant 40-address bits of the physical address. Physical-address bits 11:0 are assumed to be 0. 
Note that a given processor may implement less than the architecturally-defined physical address size of 52 bits. E7000–E
7FFFE6000–E6FFFE5000–E5FFFE4000–E4FFFE3000–E3FFFE2000–E2FFFE1000–E1FFFE0000–E0FFFMTRRfix4K_E0000
EF000–EFFFFEE000–EEFFFED000–EDFFFEC000–ECFFFEB000–EBFFFEA000–EAFFFE9000–E9FFFE8000–E8FFFMTRRfix4K_E8000
F7000–F7FFFF6000–F6FFFF5000–F5FFFF4000–F4FFFF3000–F3FFFF2000–F2FFFF1000–F1FFFF0000–F0FFFMTRRfix4K_F0000
FF000–FFFFFFE000–FEFFFFD000–FDFFFFC000–FCFFFFB000–FBFFFFA000–FAFFFF9000–F9FFFF8000–F8FFFMTRRfix4K_F8000
Table 7-7. Fixed-Range MTRR Address Ranges (continued)
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Figure 7-9. MTRRphysBase n Register
MTRRphysMask n Registers.  The fields in these variable-range MTRRs, shown in Figure 7-10, are:
•Valid (V)—Bit 11. Indicates that the MTRR pair is valid (enabled) when set to 1. When the valid bit
is cleared to 0 the register pair is not used.
•Range Physical Mask (PhysMask) —Bits 51:12. The mask value used to specify the memory
range. Like PhysBase, PhysMask is aligned on a 4-Kbyte physical-address boundary. Bits 11:0 ofPhysMask are assumed to be 0.
Figure 7-10. MTRRphysMask n Register
PhysMask and PhysBase are used together to determine whether a target physical-address falls within the specified address range. PhysMask is logically ANDed with PhysBase and separately ANDed with 63 52 51 32
Reserved PhysBase[51:32]
31 12 11 8 7 0
PhysBase[31:12] Reserved Type
63:52 Reserved MBZ
51:12 PhysBase Range Physical Base Address R/W
11:8 Reserved MBZ
7:0 Type Default Memory Type R/W
63 52 51 32
Reserved PhysMask[51:32]
31 12 11 10 0
PhysMask[31:12] V Reserved
51:12 PhysMask Range Physical Mask R/W
11 V MTRR Pair Enable (Valid) R/W
10:0 Reserved MBZ
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the upper 40 bits of the target physical-address. If the results of the two operations are identical, the 
target physical-address falls within the specified memory range. The pseudo-code for the operation is:

31 12 11 8 7 0
63 52 51 32
31 12 11 10 0
MaskBase = PhysMask AND PhysBase
MaskTarget = PhysMask AND Target_Address[51:12]IF MaskBase == MaskTarget
target address is in range
ELSE 
target address is not in range
Variable Range Size and Alignment.  The size and alignment of variable memory-ranges (MTRRs) 
and I/O ranges (IORRs) are restricted as follows:
•The boundary on which a variable range is aligned must be equal to the range size. For example, a
memory range of 16 Mbytes must be aligned on a 16-Mbyte boundary. 
•The range size must be a power of 2 (2n, 52 > n > 11), with a minimum allowable size of 4 Kbytes.
For example, 4 Mbytes and 8 Mbytes are allowable memory range sizes, but 6 Mbytes is not
allowable.
PhysMask and PhysBase Values.  Software can calculate the PhysMask value using the following 
procedure:
1. Subtract the memory-range physical base-address from the upper physical-address of the memory
range.
2. Subtract the value calculated in Step 1 from the physical memory size.3. Truncate the lower 12 bits of the result in Step 2 to create the PhysMask value to be loaded into
the MTRRphysMask n register. Truncation is performed by right-shifting the value 12 bits.
For example, assume a 32-Mbyte memory range is specified within the 52-bit physical address space, 
starting at address 200_0000h. The upper address of the range is 3FF_FFFFh. Following the process outlined above yields:
1. 3FF_FFFFh–200_0000h = 1FF_FFFFh2. F_FFFF_FFFF_FFFF–1FF_FFFFh = F_FFFF_FE00_0000h3. Right shift (F_FFFF_FE00_0000h) by 12 = FF_FFFF_E000h
In this example, the 40-bit value loaded into the PhysMask field is FF_FFFF_E000h.Software must also truncate the lower 12 bits of the physical base-address before loading it into the 
PhysBase field. In the example above, the 40-bit PhysBase field is 00_0000_2000h.
Default-Range MTRRs.  Physical addresses that are not within ranges established by fixed-range and 
variable-range MTRRs are set to a default memory-type using the MTRRdefType register. The format of this register is shown in Figure 7-11.
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Figure 7-11. MTRRdefType Register Format
The fields within the MTRRdefType register are read/write. These fields are:
•Type—Bits 7:0. The default memory-type used to characterize physical-memory space. See
Table 7-6 on page 217 for the type-field encodings. The extended type-field encodings are notsupported by this register.
•Fixed-Range Enable (FE) —Bit 10. All fixed-range MTRRs are enabled when FE is set to 1.
Clearing FE to 0 disables all fixed-range MTRRs. Setting and clearing FE has no effect on thevariable-range MTRRs. The FE bit has no effect unless the E bit is set to 1 (see below).
•MTRR Enable (E) —Bit 11. This is the MTRR memory typing enable bit. The memory typing
capabilities of all fixed-range and variable-range MTRRs are enabled when E is set to 1. ClearingE to 0 disables the memory typing capabilities of all fixed-range and variable-range MTRRs andsets the default memory-type to uncacheable (UC) regardless of the value of the Type field. Thisbit does not affect the operation of the RdMem and WrMem fields.
7.7.3  Using MTRRs
Identifying MTRR Features.  Software determines whether a processor supports the MTRR 
mechanism by executing the CPUID instruction with either function 0000_0001h or function 8000_0001h. If MTRRs are supported, bit 12 in the EDX register is set to 1 by CPUID. See “Processor Feature Identification” on page 71 for more information on the CPUID instruction.
The MTRR capability register (MTRRcap) is a read-only register containing information describing the level of MTRR support provided by the processor. Figure 7-12 shows the format of this register. If MTRRs are supported, software can read MTRRcap using the RDMSR instruction. Attempting to write to the MTRRcap register causes a general-protection exception (#GP).63 32
Reserved
31 12 11 10 9 8 7 0
Reserved
E
FE
ReservedType
63:12 Reserved MBZ
11 E MTRR Enable R/W
10 FE Fixed Range Enable R/W
9:8 Reserved MBZ
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Figure 7-12. MTRR Capability Register Format
The MTRRcap register field are:
•Variable-Range Register Count (VCNT) —Bits 7:0. The VCNT field contains the number of
variable-range register pairs supported by the processor. For example, a processor supporting eight
register pairs returns a 08h in this field.
•Fixed-Range Registers (FIX) —Bit 8. The FIX bit indicates whether or not the fixed-range registers
are supported. If the processor returns a 1 in this bit, all fixed-range registers are supported. If the
processor returns a 0 in this bit, no fixed-range registers are supported.
•Write-Combining (WC) —Bit 10. The WC bit indicates whether or not the write-combining
memory type is supported. If the processor returns a 1 in this bit, WC memory is supported,otherwise it is not supported.
7.7.4  MTRRs and Page Cache Controls
When paging and the MTRRs are both enabled, the address ranges defined by the MTRR registers can 
span multiple pages, each of which can characterize memory with different types (using the PCD and PWT page bits). When caching is enabled (CR0.CD=0 and CR0.NW=0), the effective memory type is 
determined as follows:
1. If the page is defined as cacheable and writeback (PCD=0 and PWT=0), then the MTRR defines
the effective memory-type.
2. If the page is defined as not cacheable (PCD=1), then UC is the effective memory-type.3. If the page is defined as cacheable and writethrough (PCD=0 and PWT=1), then the MTRR
defines the effective memory-type unless the MTRR specifies WB memory, in which case WT is
the effective memory-type.63 32
Reserved
31 11 10 9 8 7 0
Reserved
WC
Reserved
FIXVCNT
63:11 Reserved R
10 WC Write Combining R
9 Reserved R
8 FIX Fixed-Range Registers R
7:0 VCNT Variable-Range Register Count R
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Table 7-8 lists the MTRR and page-level cache-control combinations and their combined effect on the 
final memory-type, if the PAT register holds the default settings.
Large Page Sizes.  When paging is enabled, software can use large page sizes (2 Mbytes and 
4 Mbytes) in addition to the more typical 4-Kbyte page size. When large page sizes are used, it is possible for multiple MTRRs to span the memory range within a single large page. Each MTRR can characterize the regions within the page with different memory types. If this occurs, the effective memory-type used by the processor within the large page is undefined.
Software can avoid the undefined behavior in one of the following ways:
•Avoid using multiple MTRRs to characterize a single large page.
•Use multiple 4-Kbyte pages rather than a single large page.
•If multiple MTRRs must be used within a single large page, software can set the MTRR type fields
to the same value.
•If the multiple MTRRs must have different type-field values, software can set the large page PCDand PWT bits to the most restrictive memory type defined by the multiple MTRRs.
Overlapping MTRR Registers.  If the address ranges of two or more MTRRs overlap, the following 
rules are applied to determine the memory type used to characterize the overlapping address range:
1. Fixed-range MTRRs, which characterize only the first 1 Mbyte of physical memory, have
precedence over variable-range MTRRs.Table 7-8. Combined MTRR and Page-Level Memory Type with 
Unmodified PAT MSR
MTRR
Memory TypePage
PCD BitPage
PWT BitEffective 
Memory-Type
UC — — UC
WC0 — WC
1 0 WC1
1 1 UC
WP0 — WP
1 — UC
WT0 — WT
1 — UC
WB0 0 WB
0 1 WT
1 — UC
Note:
1. The effective memory-type resulting from the combination of PCD=1, PWT=0, and an MTRR
WC memory type is implementation dependent.
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2. If two or more variable-range MTRRs overlap, the following rules apply:
a. If the memory types are identical, then that memory type is used.
b. If at least one of the memory types is UC, the UC memory type is used.c. If at least one of the memory types is WT, and the only other memory type is WB, then the
WT memory type is used.
d. If the combination of memory types is not listed Steps A through C immediately above, then
the memory type used is undefined.
7.7.5  MTRRs in Multi-Processing Environments
In multi-processing environments, the MTRRs located in all processors must characterize memory in 
the same way. Generally, this means that identical values are written to the MTRRs used by the processors. This also means that values CR0.CD and the PAT must be consistent across processors. Failure to do so may result in coherency violations or loss of atomicity. Processor implementations do 
not check the MTRR settings in other processors to ensure consistency. It is the responsibility of 
system software to initialize and maintain MTRR consistency across all processors.

7.8 Page-Attribute Table Mechanism
The page-attribute table (PAT) mechanism extends the page-table entry format and enhances the capabilities provided by the PCD and PWT page-level cache controls. PAT (and PCD, PWT) allow memory-type characterization based on the virtual (linear) address. The PAT mechanism provides the same memory-typing capabilities as the MTRRs but with the added flexibility of the paging mechanism. Software can use both the PAT and MTRR mechanisms to maximize flexibility in memory-type control.
7.8.1  PAT Register
Like the MTRRs, the PAT register is a 64-bit model-specific register (MSR). The format of the PAT 
registers is shown in Figure 7-13. See “Memory-Typing MSRs” on page 720 for more information on 
the PAT MSR number and reset value.
 
Figure 7-13. PAT Register63 59 58 56 55 51 50 48 47 43 42 40 41 35 34 32
Reserved PA7 Reserved PA6 Reserved PA5 Reserved PA4
31 27 26 24 23 19 18 16 15 11 10 8 7 3 2 0
Reserved PA3 Reserved PA2 Reserved PA1 Reserved PA0
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The PAT register contains eight page-attribute (PA) fields, numbered from PA0 to PA7. The PA fields 
hold the encoding of a memory type, as found in Table 7-9 on page 227. The PAT type-encodings match the MTRR type-encodings, with the exception that PAT adds the 07h encoding. The 07h encoding corresponds to a UC− type. The UC− type (07h) is identical to the UC type (00h) except it 
can be overridden by an MTRR type of WC.
Software can write any supported memory-type encoding into any of the eight PA fields. An attempt to 
write anything but zeros into the reserved fields causes a general-protection exception (#GP). An attempt to write an unsupported type encoding into a PA field also causes a #GP exception.
The PAT register fields are initiated at processor reset to the default values shown in Table 7-10 on 
page 228.
7.8.2  PAT Indexing
PA fields in the PAT register are selected using three bits from the page-table entries. These bits are:
•P AT (page attribute table) —The PAT bit is bit 7 in 4-Kbyte PTEs; it is bit 12 in 2-Mbyte and 4-
Mbyte PDEs. Page-table entries that don’t have a PAT bit (PML4 entries, for example) assume PAT
= 0.
•PCD (page cache disable)—The PCD bit is bit 4 in all page-table entries. The PCD from the PTEor PDE is selected depending on the paging mode.
•PWT (page writethrough)—The PWT bit is bit 3 in all page-table entries. The PWT from the PTEor PDE is selected depending on the paging mode.Table 7-9. PAT Type Encodings
00h UC—UncacheableAll accesses are uncacheable. Write combining is not allowed. Speculative 
accesses are not allowed.
01h WC—Write-CombiningAll accesses are uncacheable. Write combining is allowed. Speculative reads are allowed.
04h WT—WritethroughReads allocate cache lines on a cache miss, but only to the shared state. Cache lines are not allocated on a write miss. Write hits update the cache and main memory.
05h WP—Write-ProtectReads allocate cache lines on a cache miss, but only to the shared state. All writes update main memory. Cache lines are not allocated on a write miss. Write hits invalidate the cache line and update main memory.
06h WB—WritebackReads allocate cache lines on a cache miss, and can allocate to either the shared or exclusive state. Writes allocate to the modified state on a cache miss.
07hUC–
(UC minus)All accesses are uncacheable. Write combining is not allowed. Speculative accesses are not allowed. Can be overridden by an MTRR with the WC type.
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Table 7-10 on page 228 shows the various combinations of the PAT, PCD, and PWT bits used to select 
a PA field within the PAT register. Table 7-10 also shows the default memory-type values established 
in the PAT register by the processor after a reset. The default values correspond to the memory types 
established by the PCD and PWT bits alone in processor implementations that do not support the PAT mechanism. In such implementations, the PAT field in page-table entries is reserved and cleared to 0. See “Page-Translation-Table Entry Fields” on page 153 for more information on the page-table entries.
7.8.3  Identifying PAT Support
Software determines whether a processor supports the PAT mechanism by executing the CPUID 
instruction with either function 0000_0001h or function 8000_0001h. If PAT is supported, bit 16 in the EDX register is set to 1 by CPUID. See Section 3.3, “Processor Feature Identification,” on page 71 for more information on the CPUID instruction.
If PAT is supported by a processor implementation, it is always enabled . The PAT mechanism cannot 
be disabled by software. Software can effectively avoid using PAT by:
•Not setting PAT bits in page-table entries to 1.
•Not modifying the reset values of the PA fields in the PAT register.
In this case, memory is characterized using the same types that are used by implementations that do 
not support PAT.
7.8.4  PAT Accesses
In implementations that support the PAT mechanism, all memory accesses that are translated through 
the paging mechanism use the PAT index bits to specify a PA field in the PAT register. The memory type stored in the specified PA field is applied to the memory access. The process is summarized as:
1. A virtual address is calculated as a result of a memory access.Table 7-10. PAT-Register PA-Field Indexing
Page Table Entry BitsPAT Register Field Default Memory TypePAT PCD PWT
0 0 0 PA0 WB
0 0 1 PA1 WT
0 1 0 PA2 UC–1
0 1 1 PA3 UC
1 0 0 PA4 WB
1 0 1 PA5 WT
1 1 0 PA6 UC–1
1 1 1 PA7 UC
Note:
1. Can be overridden by WC memory type set by an MTRR.
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2. The virtual address is translated to a physical address using the page-translation mechanism.
3. The PAT, PCD and PWT bits are read from the corresponding page-table entry during the virtual-
address to physical-address translation.
4. The PAT, PCD and PWT bits are used to select a PA field from the PAT register.5. The memory type is read from the appropriate PA field.6. The memory type is applied to the physical-memory access using the translated physical address.
Page-Translation Table Access.  The PAT bit exists only in the PTE (4K paging) or PDEs (2/4 
Mbyte paging). In the remaining upper levels (PML5, PML4, PDP, and 4KB PDEs), only the PWT and 
PCD bits are used to index into the first 4 entries in the PAT register. The resulting memory type is used for the next lower paging level.
7.8.5  Combined Effect of MTRRs and PAT
The memory types established by the PAT mechanism can be combined with MTRR-established 
memory types to form an effective memory-type. The combined effect of MTRR and PAT memory types are shown in Figure 7-11. In the AMD64 architecture, reserved and undefined combinations of 
MTRR and PAT memory types result in undefined behavior. If the MTRRs are disabled in implementations that support the MTRR mechanism, the default memory type is set to uncacheable (UC).
Table 7-11. Combined Effect of MTRR and PAT Memory Types
PAT Memory Type MTRR Memory Type Effective Memory Type
UC UC UC
UC WC, WP, WT, WB CD
UC−UC UC
WC WC
WP, WT, WB CD
WC — WC
WPUC UC
WC CD
WP WP
WT CD
WB WP
WTUC UC
WC, WP CD
WT, WB WT
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7.8.6  PATs in Multi-Processing Environments
In multi-processing environments, values of CR0.CD and the PAT must be consistent across all 
processors and the MTRRs in all processors must characterize memory in the same way. In other words, matching address ranges and cachability types are written to the MTRRs for each processor.
Failure to do so may result in coherency violations or loss of atomicity. Processor implementations do 
not check the MTRR, CR0.CD and PAT values in other processors to ensure consistency. It is the 
responsibility of system software to initialize and maintain consistency across all processors.
7.8.7  Changing Memory Type
A physical page should not have differing cacheability types assigned to it through different virtual 
mappings; they should be either all of a cacheable type (WB, WT, WP) or all of a non-cacheable type (UC, WC). Otherwise, this may result in a loss of cache coherency, leading to stale data and unpredictable behavior. For this reason, certain precautions must be taken when changing the memory type of a page. In particular, when changing from a cachable memory type to an uncachable type the caches must be flushed, because speculative execution by the processor may have resulted in memory being cached even though it was not programmatically referenced. The following table summarizes the serialization requirements for safely changing memory types.WBUC UC
WC WC
WP WP
WT WT
WB WBTable 7-11. Combined Effect of MTRR and PAT Memory Types (continued)
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WC WC
WP WP
WT WT
Table 7-12. Serialization Requirements for Changing Memory Types
7.9 Memory-Mapped I/O
Processor implementations can independently direct reads and writes to either system memory or 
memory-mapped I/O. The method used for directing those memory accesses is implementation dependent. In some implementations, separate system-memory and memory-mapped I/O buses can be provided at the processor interface. In other implementations, system memory and memory-mapped I/O share common data and address buses, and system logic uses sideband signals from the processor to route accesses appropriately. Refer to AMD data sheets and application notes for more information about particular hardware implementations of the AMD64 architecture.
The I/O range registers (IORRs), and the top-of-memory registers allow system software to specify 
where memory accesses are directed for a given address range. The MTRR extensions are described in the following section. “IORRs” on page 233 describes the IORRs and “Top of Memory” on page 235 
describes the top-of-memory registers. In implementations that support these features, the default 
action taken when the features are disabled is to direct memory accesses to memory-mapped I/O. 
7.9.1  Extended Fixed-Range MTRR Type-Field Encodings
The fixed-range MTRRs support extensions to the type-field encodings that allow system software to 
direct memory accesses to system memory or memory-mapped I/O. The extended MTRR type-field encodings use previously reserved bits 4:3 to specify whether reads and writes to a physical-address range are to system memory or to memory-mapped I/O. The format for this encoding is shown in Figure 7-14 on page 232. The new bits are:
•WrMem —Bit 3. When set to 1, the processor directs write requests for this physical address range
to system memory. When cleared to 0, writes are directed to memory-mapped I/O.
•RdMem —Bit 4. When set to 1, the processor directs read requests for this physical address range to
system memory. When cleared to 0, reads are directed to memory-mapped I/O.New Type
WB WT WP UC WCOld TypeWB – a a b b
WT a – a b b
WP a a – b b
UC a a a – a
WC a a a a –
Note:
a. Remove the previous mapping (make it not present in the page tables); Flush the TLBs including the TLBs
of other processors that may have used the mapping, even speculatively; Create a new mapping in the
page tables using the new type.
b. In addition to the steps described in note a, software should flush the page from the caches of any processor
that may have used the previous mapping. This must be done after the TLB flushing in note a has beencompleted.
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The type subfield (bits 2:0) allows the encodings specified in Table 7-6 on page 217 to be used for 
memory characterization.
Figure 7-14. Extended MTRR Type-Field Format (Fixed-Range MTRRs)
These extensions are enabled using the following bits in the SYSCFG MSR:
•MtrrFixDramEn —Bit 18. When set to 1, RdMem and WrMem attributes are enabled. When
cleared to 0, these attributes are disabled. When disabled, accesses are directed to memory-mapped
I/O space.  
•MtrrFixDramModEn—Bit 19. When set to 1, software can read and write the RdMem and
WrMem bits. When cleared to 0, writes do not modify the RdMem and WrMem bits, and readsreturn 0.
To use the MTRR extensions, system software must first set MtrrFixDramModEn=1 to allow modification to the RdMem and WrMem bits. After the attribute bits are properly initialized in the fixed-range registers, the extensions can be enabled by setting MtrrFixDramEn=1.
RdMem and WrMem allow the processor to independently direct reads and writes to either system 
memory or memory-mapped I/O. The RdMem and WrMem controls are particularly useful when shadowing ROM devices located in memory-mapped I/O space. It is often useful to shadow such devices in RAM system memory to improve access performance, but writes into the RAM location can corrupt the shadowed ROM information. The MTRR extensions solve this problem. System software can create the shadow location by setting WrMem = 1 and RdMem = 0 for the specified memory range and then copy the ROM location into itself. Reads are directed to the memory-mapped ROM, but writes go to the same physical addresses in system memory. After the copy is complete, system software can change the bit values to WrMem = 0 and RdMem = 1. Now reads are directed to the faster copy located in system memory, and writes are directed to memory-mapped ROM. The ROM responds as it would normally to a write, which is to ignore it.
Not all combinations of RdMem and WrMem are supported for each memory type encoded by bits 2:0. 
Table 7-13 on page 233 shows the allowable combinations. The behavior of reserved encoding combinations (shown as gray-shaded cells) is undefined and results in unpredictable behavior.7 5 4 3 2 0
Reserved RdMem WrMem Type
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7.9.2  IORRs
The IORRs operate similarly to the variable-range MTRRs. The IORRs specify whether reads and 
writes in any physical-address range map to system memory or memory-mapped I/O. Up to two address ranges of varying sizes can be controlled using the IORRs. A pair of IORRs are used to control each address range: IORRBase n and IORRMask n (n is the address-range number from 0 to 1).
Figure 7-15 on page 234 shows the format of the IORRBasen registers and Figure 7-16 on page 235 
shows the format of the IORRMask n registers. The fields within the register pair are read/write.
The intersection of the IORR range with the equivalent effective MTRR range follows the same type encoding table (Table 7-13) as the fixed-range MTRR, where the RdMem/WrMem and memory type are directly tied together.
IORRBase n Registers.  The fields in these IORRs are:
to system memory. When cleared to 0, writes are directed to memory-mapped I/O.Table 7-13. Extended Fixed-Range MTRR Type Encodings
RdMem WrMem Type Implication or Potential Use
0 00 (UC) UC I/O
1 (WC) WC I/O
4 (WT) WT I/O
5 (WP) WP I/O
6 (WB) Reserved
0 10 (UC)Used while creating a shadowed ROM1 (WC)
4 (WT)
Reserved 5 (WP)
6 (WB)
1 00 (UC) Used to access a shadowed ROM
1 (WC)Reserved4 (WT)
5 (WP)WP Memory
(Can be used to access shadowed ROM)
1 10 (UC) UC Memory
1 (WC) WC Memory
4 (WT) WT Memory
5 (WP) Reserved
6 (WB) WB Memory
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system memory. When cleared to 0, reads are directed to memory-mapped I/O.
•Range Physical-Base-Address (PhysBase)—Bits 51:12. The memory-range base-address in
physical-address space. PhysBase is aligned on a 4-Kbyte (or greater) address in the 52-bitphysical-address space supported by the AMD64 architecture. PhysBase represents the most-significant 40-address bits of the physical address. Physical-address bits 11:0 are assumed to be 0.
Note that a given processor may implement less than the architecturally-defined physical address size of 52 bits. 
The format of these registers is shown in Figure 7-15.
 
Figure 7-15. IORRBase n Register
IORRMaskn  Registers.  The fields in these IORRs are:
•Valid (V)—Bit 11. Indicates that the IORR pair is valid (enabled) when set to 1. When the valid bit
is cleared to 0 the register pair is not used for memory-mapped I/O control (disabled).
•Range Physical-Mask (PhysMask) —Bits 51:12. The mask value used to specify the memory
The format of these registers is shown in Figure 7-16 on page 235.63 52 51 32
31 12 11 5 4 3 0
PhysBase[31:12] Reserved
Rd
WrReserved
63:52 Reserved IGN
11:5 Reserved IGN
4 Rd RdMem Enable R/W
3 Wr WrMem Enable R/W
2:0 Reserved IGN
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Figure 7-16. IORRMask n Register
The operation of the PhysMask and PhysBase fields is identical to that of the variable-range MTRRs. 
See page 221 for a description of this operation.
7.9.3  IORR Overlapping
The use of overlapping IORRs is not recommended. If overlapping IORRs are specified, the resulting 
behavior is implementation-dependent.
7.9.4  Top of Memory
The top-of-memory  registers, TOP_MEM and TOP_MEM2, allow system software to specify physical 
addresses ranges as memory-mapped I/O locations. Processor implementations can direct accesses to

Rd
addresses ranges as memory-mapped I/O locations. Processor implementations can direct accesses to 
memory-mapped I/O differently than system I/O, and the precise method depends on the implementation. System software specifies memory-mapped I/O regions by writing an address into each of the top-of-memory registers. The memory regions specified by the TOP_MEM registers are aligned on 8-Mbyte boundaries as follows:
•Memory accesses from physical address 0 to one less than the value in TOP_MEM are directed to
•Memory accesses from the physical address specified in TOP_MEM to FFFF_FFFFh are directedto memory-mapped I/O.
•Memory accesses from physical address 1_0000_0000h to one less than the value in TOP_MEM2are directed to system memory.
•Memory accesses from the physical address specified in TOP_MEM2 to the maximum physicaladdress supported by the system are directed to memory-mapped I/O.63 52 51 32
31 12 11 10 0
11 V I/O Register Pair Enable (Valid) R/W
10:0 Reserved IGN
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Figure 7-17 on page 236 shows how the top-of-memory registers organize memory into separate 
system-memory and memory-mapped I/O regions.
The intersection of the top-of-memory range with the equivalent effective MTRR range follows the 
same type encoding table (Table 7-13 on page 233) as the fixed-range MTRR, where the RdMem/WrMem and memory type are directly tied together.
Figure 7-17. Memory Organization Using Top-of-Memory Registers
Figure 7-18 shows the format of the TOP_MEM and TOP_MEM2 registers. Bits 51:23 specify an 8-Mbyte aligned physical address. All remaining bits are reserved and ignored by the processor. System software should clear those bits to zero to maintain compatibility with possible future extensions to the registers. The TOP_MEM registers are model-specific registers. See “Memory-Typing MSRs” on 
page 720 for information on the MSR address and reset values for these registers.
 
Figure 7-18. Top-of-Memory Registers (TOP_MEM, TOP_MEM2)63 52 51 32
Reserved, IGN Top-of-Memory Physical Address[51:32]
31 23 22 0
Top-of-Memory Physical 
Address[31:23]Reserved, IGN
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The TOP_MEM register is enabled by setting the MtrrVarDramEn bit in the SYSCFG MSR (bit 20) to 
1 (one). The TOP_MEM2 register is enabled by setting the MtrrTom2En bit in the SYSCFG MSR (bit 21) to 1 (one). The registers are disabled when their respective enable bits are cleared to 0. When the top-of-memory registers are disabled, memory accesses default to memory-mapped I/O space. 
Note that a given processor may implement fewer than the architecturally-defined number of physical 
address bits.
7.10 Secure Memory Encryption
Software running in non-virtualized (native) mode can utilize the Secure Memory Encryption (SME) feature to mark individual pages of memory as encrypted through the page tables. A page of memory 
marked encrypted will be automatically decrypted when read by software and automatically encrypted when written to DRAM. SME may therefore be used to protect the contents of DRAM from physical attacks on the system.
All memory encrypted using SME is encrypted with the same AES key which is created randomly 
each time a system is booted. The memory encryption key cannot be read or modified by software.
For details on using memory encryption in virtualized environments, please see Section 15.34, 
“Secure Encrypted Virtualization,” on page 588.
7.10.1  Determining Support for Secure Memory Encryption
Support for memory encryption features is reported in CPUID Fn8000_001F[EAX]. Bit 0 indicates 
support for Secure Memory Encryption. When this feature is present, CPUID Fn8000_001F[EBX] 
supplies additional information regarding the use of memory encryption such as which page table bit is used to mark pages as encrypted. 
Additionally, in some implementations, the physical address size of the processor may be reduced 
when memory encryption features are enabled, for example from 48 to 43 bits. In this case the upper physical address bits are treated as reserved when the feature is enabled except where otherwise indicated. When memory encryption is supported in an implementation, CPUID Fn8000_001F[EBX] reports any physical address size reduction present. Bits reserved in this mode are treated the same as other page table reserved bits, and will generate a page fault if found to be non-zero when used for address translation.
Complete CPUID details for encrypted memory features can be found in V olume 3, section E.4.17.
7.10.2  Enabling Memory Encryption Extensions
Prior to using SME, memory encryption features must be enabled by setting SYSCFG MSR bit 23 
(MemEncryptionModEn) to 1. In implementations where the physical address size of the processor is reduced when memory encryption features are enabled, software must ensure it is executing from addresses where these upper physical address bits are 0 prior to setting SYSCFG[MemEncryptionModEn].   Memory encryption is then further controlled via the page tables.
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Note that software should keep the value of SYSCFG[MemEncryptionModEn] consistent across all 
CPU cores in the system. Failure to do so may lead to unexpected results.
7.10.3  Supported Operating Modes
SME is supported in all CPU modes when CR4.PAE=1 and paging is enabled. This includes long 
mode as well as legacy PAE-enabled protected mode. 
7.10.4  Page Table Support
Software utilizes the page tables to indicate if a memory page is encrypted or unencrypted. The 
location of the specific attribute bit (C-bit, or enCrypted bit) used is implementation-specific but may be determined by referencing CPUID Fn8000_001F[EBX] (see V olume 3, section E.4.17 for details). In some implementations, the bit used may be a physical address bit (e.g., address bit 47), especially in cases where the physical address size is reduced by hardware when memory encryption features are enabled.
To mark a memory page for encryption when stored in DRAM, software sets the C-bit to 1 for the 
page. If the C-bit is 0, the page is not encrypted when stored in DRAM. The C bit can be applied to 
translation table entries for any size of page - 4KB, 2MB, or 1GB.
Note that it is possible for the page tables themselves to be located in encrypted memory. For instance, 
if the C-bit is set in a PML4 entry, the PDP table it points to (and thus all PDPEs in that table) will be loaded from encrypted memory.
Figure 7-19. Encrypted Memory Accesses
CPU
AES Decrypt
AES Encrypt
DataPTE C‐BitMemory Read
CPU
DataPTE C‐Bit
DRAM
DRAMMemory Write0
01
1
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7.10.5  I/O Accesses
In implementations where the physical address size is reduced when memory encryption features are 
enabled, memory range checks (e.g. MTRR/TOM/IORR/etc.) to determine memory types or DRAM/MMIO are performed using the reduced physical address size. In particular, the C-bit is not 
considered a physical address bit and is masked by hardware for purposes of these checks.
Additionally, any pages corresponding to MMIO addresses must be configured with the C-bit clear. 
Encrypted I/O pages are not allowed and accesses with the C-bit set will be ignored.
7.10.6  Restrictions
In some hardware implementations, coherency between the encrypted and unencrypted mappings of 
the same physical page are not enforced. In such a system, prior to changing the value of the C-bit for a page, software should flush the page from all CPU caches in the system. If a hardware implementation supports coherency across encryption domains as indicated by CPUID Fn8000_001F_EAX[10] then this flush is not required.
Simply changing the value of a C-bit on a page will not automatically encrypt the existing contents of 
a page, and any data in the page prior to the C-bit modification will become unintelligible. To set the C-bit on a page and cause its contents to become encrypted so the data remains accessible, see Section 7.10.8, “Encrypt-in-Place,” on page 239.
In legacy PAE mode, if the C-bit location is in the upper 32 bits of the page table entry, the first level 
page table (the PDP table) cannot be located in encrypted memory. This is because when the CPU is in 32-bit PAE mode, the CR3 value is only 32-bits in length.
7.10.7  SMM Interaction
SME is available when the processor is executing in SMM, once it has enabled paging. Any physical 
address bit restrictions that exist due to memory encryption features being enabled remain in place while in SMM.
7.10.8  Encrypt-in-Place
It is possible to perform an in-place encryption of data in physical memory. This technique is useful for

It is possible to perform an in-place encryption of data in physical memory. This technique is useful for 
setting the C-bit on a page while maintaining visibility to the page's contents such as during SME initialization. This is accomplished by creating two linear mappings of the same page where one mapping has the C-bit set to 0 and the other has the C-bit set to 1. To avoid possible data corruption, 
software should use the following algorithm for performing in-place encryption of memory:
1. Create two linear mappings X and Y that map to the same physical page. Mapping X has C-bit=0
and uses the WP (Write Protect) memory type. Mapping Y has C-bit=1 and uses the WB (Write-
Back) memory type.
2. Perform a WBINVD on all cores in the system.
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3. Copy N bytes from mapping X to a temporary buffer in conventionally-mapped memory (for
which the C bit may or may not be set, as desired). N must be equal to the L1 cache line size as
specified by CPUID Fn8000_0005[ECX].
4. Write N bytes from the temporary buffer to Y . Note that the initial cache refill of the line for this
step will cause it to be decrypted, which corrupts the contents since it is not yet encrypted. Thisstep restores the original contents. (If the line were evicted before this step was completed, theunwritten portion would get corrupted by the outgoing encryption, which is why the line can't becopied in-place, but rather must be copied from the temporary buffer.)
5. Repeat steps 3-4 until the entire page has been copied.
7.10.9  Secure Multi-Key Memory Encryption
The Multi-Key Secure Memory Encryption (SME-MK) feature is an extension of the Secure Memory 
Encryption (SME) feature. This feature allows software (OS or hypervisor) to load encryption keys into hardware memory controllers and to select which key is used to encrypt each page of memory. Encryption key loading also requires the use of the AMD Secure Processor (AMD-SP).
Support for SME-MK is reported by CPUID Fn8000_0023_EAX[MemHmk] (bit 0) = 1. When this 
feature is present, the number of simultaneously available host encryption key IDs (EncrKeyId) is reported by CPUID Fn8000_0023_EBX[MaxMemHmkEncrKeyID] (bits 15:0). 
The MEM-MK feature is enabled by setting SYSCFG MSR bit 26 (HostMultiKeyMemEncrModeEn) 
to 1 and bit 23 (MemEncryptionModEn) to 0. In implementations where the physical address size of 
the processor is reduced when memory encryption features are enabled, software must ensure it is executing from addresses where these upper physical address bits are 0 prior to enabling the MEM -MK feature. Memory encryption is then further controlled via the page tables. Software should 
keep the value of SYSCFG MSR bits HostMultiKeyMemEncrModeEn and MemEncryptionModEn consistent across all CPU cores in the system. Failure to do so may lead to unexpected results. 
When SME-MK is enabled, all system physical addresses have an EncrKeyID field defined as part of 
the system physical address (this includes CR3, the nested page table base, VMCB addresses, etc.). The EncrKeyID field specifies the index of the encryption key to use. An EncrKeyID value of zero indicates that encryption is not used for that access. The physical address space may be reduced and the upper physical address bits used to specify the EncrKeyID (the physical address size reduction is reported by CPUID Fn8000_001F_EBX[PhysAddrReduction]). EncrKeyID width (EncrKeyIdWidth) is equal to log2(CPUID Fn8000_0023_EBX[MaxMemHmkEncrKeyID] + 1). System physical address bits [CBitP:(CBitP-EncrKeyIdWidth + 1)] contain EncrKeyID, where CBitP is equal to CPUID Fn8000_001F_EBX[CbitPosition] (5:0).
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8 Exceptions and Interrupts
Exceptions and interrupts force control transfers from the currently-executing program to a system-
software service routine that handles the interrupting event. These routines are referred to as exception 
handlers and interrupt handlers , or collectively as event handlers . Typically, interrupt events can be 
handled by the service routine transparently to the interrupted program. During the control transfer to the service routine, the processor stops executing the interrupted program and saves its return pointer. The system-software service routine that handles the exception or interrupt is responsible for saving the state of the interrupted program. This allows the processor to restart the interrupted program after system software has handled the event.
When an exception or interrupt occurs, the processor uses the interrupt vector number as an index into 
the interrupt-descriptor table (IDT). An IDT is used in all processor operating modes, including real mode (also called real-address mode), protected mode, and long mode. 
Exceptions and interrupts come from three general sources:
•Exceptions  occur as a result of software execution errors or other internal-processor errors.
Exceptions also occur during non-error situations, such as program single stepping or address-
breakpoint detection. Exceptions are considered synchronous  events because they are a direct
result of executing the interrupted instruction.
•Software interrupts occur as a result of executing interrupt instructions. Unlike exceptions andexternal interrupts, software interrupts allow intentional triggering of the interrupt-handlingmechanism. Like exceptions, software interrupts are synchronous events.
•External interrupts  are generated by system logic in response to an error or some other event
outside the processor. They are reported over the processor bus using external signaling. Externalinterrupts are asynchronous events that occur independently of the interrupted instruction. 
Throughout this section, the term masking  can refer to either disabling or delaying an interrupt. For 
example, masking external interrupts delays the interrupt, with the processor holding the interrupt as 
pending until it is unmasked. With floating-point exceptions (SSE and x87), masking prevents an 
interrupt from occurring and causes the processor to perform a default operation on the exception condition.
8.1 General Characteristics
Exceptions and interrupts have several different characteristics that depend on how events are reported and the implications for program restart. 
8.1.1  Precision
Precision  describes how the exception is related to the interrupted program:
•Precise exceptions are reported on a predictable instruction boundary. This boundary is generally
the first instruction that has not completed when the event occurs. All previous instructions (in
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program order) are allowed to complete before transferring control to the event handler. The
pointer to the instruction boundary is saved automatically by the processor. When the eventhandler completes execution, it returns to the interrupted program and restarts execution at theinterrupted-instruction boundary.
•Imprecise exceptions are not guaranteed to be reported on a predictable instruction boundary. The
boundary can be any instruction that has not completed when the interrupt event occurs. Impreciseevents can be considered asynchronous, because the source of the interrupt is not necessarilyrelated to the interrupted instruction. Imprecise exception and interrupt handlers typically collectmachine-state information related to the interrupting event for reporting through system-diagnostic software. The interrupted program is not restartable. 
8.1.2  Instruction Restart
As mentioned above, precise exceptions are reported on an instruction boundary. The instruction 
boundary can be reported in one of two locations:
•Most exceptions report the boundary before  the instruction causing the exception. In this case, all
previous instructions (in program order) are allowed to complete, but the interrupted instruction is
not. No program state is updated as a result of partially executing an interrupted instruction.
•Some exceptions report the boundary after  the instruction causing the exception. In this case, all
previous instructions—including the one executing when the exception occurred—are allowed tocomplete.  
Program state can be updated when the reported boundary is after the instruction causing theexception. This is particularly true when the event occurs as a result of a task switch. In this case,the general registers, segment-selector registers, page-base address register, and LDTR are allupdated by the hardware task-switch mechanism. The event handler cannot rely on the state ofthose registers when it begins execution and must be careful in validating the state of the segment-selector registers before restarting the interrupted task. This is not an issue in long mode, however,because the hardware task-switch mechanism is disabled in long mode.
8.1.3  Types of Exceptions
There are three types of exceptions, depending on whether they are precise and how they affect 
program restart:

•Faults  are precise exceptions reported on the boundary before the instruction causing the
exception. Generally, faults are caused by an error condition involving the faulted instruction. Any
machine-state changes caused by the faulting instruction are discarded so that the instruction canbe restarted. The saved rIP points to the faulting instruction.
•Traps  are precise exceptions reported on the boundary following the instruction causing the
exception. The trapped instruction is completed by the processor and all state changes are saved.The saved rIP points to the instruction following the faulting instruction.
•Aborts  are imprecise exceptions. Because they are imprecise, aborts typically do not allow reliable
program restart.
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8.1.4  Masking External Interrupts
General Masking Capabilities.  Software can mask the occurrence of certain exceptions and 
interrupts. Masking can delay or even prevent triggering of the exception-handling or interrupt-
handling mechanism when an interrupt-event occurs. External interrupts are classified as maskable or nonmaskable:
•Maskable interrupts  trigger the interrupt-handling mechanism only when RFLAGS.IF=1.
Otherwise they are held pending for as long as the RFLAGS.IF bit is cleared to 0.
•Nonmaskable interrupts (NMI) are unaffected by the value of the RFLAGS.IF bit. However, the
occurrence of an NMI masks further NMIs until an IRET instruction is executed to completion or,in the event of a task switch, to the completion of the outgoing TSS update. An exception raisedduring execution of the IRET prior to these points will result in NMI continuing to be masked forthe duration of the exception handler, until the exception handler completes an IRET.
Masking During Stack Switches.  The processor delays recognition of maskable external interrupts 
and debug exceptions during certain instruction sequences that are often used by software to switch stacks. The typical programming sequence used to switch stacks is:
1. Load a stack selector into the SS register.2. Load a stack offset into the ESP register.
If an interrupting event occurs after the selector is loaded but before the stack offset is loaded, the 
interrupted-program stack pointer is invalid during execution of the interrupt handler. 
To prevent interrupts from causing stack-pointer problems, the processor does not allow external 
interrupts or debug exceptions to occur until the instruction immediately following the MOV SS or POP SS instruction completes execution.
The recommended method of performing this sequence is to use the LSS instruction. LSS loads both 
SS and ESP, and the instruction inhibits interrupts until both registers are updated successfully.
8.1.5  Masking Floating-Point and Media Instructions
Any x87 floating-point exceptions can be masked and reported later using bits in the x87 floating-
point status register (FSW) and the x87 floating-point control register (FCW). The floating-point exception-pending exception is used for unmasked x87 floating-point exceptions (see Section “#MF—x87 Floating-Point Exception-Pending (Vector 16)” on page 256).
The SIMD floating-point exception is used for unmasked SSE floating-point exceptions (see Section 
“#XF—SIMD Floating-Point Exception (Vector 19)” on page 258). SSE floating-point exceptions are masked using the MXCSR register. The exception mechanism is not triggered when these exceptions are masked. Instead, the processor handles the exceptions in a default manner.
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8.1.6  Disabling Exceptions
Disabling an exception prevents the exception condition from being recognized, unlike masking an 
exception which prevents triggering the exception mechanism after the exception is recognized. Some exceptions can be disabled by system software running at CPL=0, using bits in the CR0 register or CR4 register:
•Alignment-check exception (see Section “#AC—Alignment-Check Exception (Vector 17)” on 
page 257).
•Device-not-available exception (see Section “#NM—Device-Not-Available Exception (Vector 7)” 
on page 250).
•Machine-check exception (see Section “#MC—Machine-Check Exception (Vector 18)” on 
page 258).
The debug-exception mechanism provides control over when specific breakpoints are enabled and disabled. See Section “Setting Breakpoints” on page 401 for more information on how breakpoint controls are used for triggering the debug-exception mechanism.
8.2 Vectors
Specific exception and interrupt sources are assigned a fixed vector-identification number (also called an “interrupt vector” or simply “vector”). The interrupt vector is used by the interrupt-handling mechanism to locate the system-software service routine assigned to the exception or interrupt. Up to 256 unique interrupt vectors are available. The first 32 vectors are reserved for predefined exception and interrupt conditions. Software-interrupt sources can trigger an interrupt using any available interrupt vector. 
Table 8-1 on page 245 lists the supported interrupt vector numbers, the corresponding exception or 
interrupt name, the mnemonic, the source of the interrupt event, and a summary of the possible causes.
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Table 8-2 on page 246 shows how each interrupt vector is classified. Reserved interrupt vectors are 
indicated by the gray-shaded rows.Table 8-1. Interrupt Vector Source and Cause
Vector Exception/Interrupt Mnemonic Cause
0 Divide-by-Zero-Error #DE DIV , IDIV , AAM instructions
1 Debug #DB Instruction accesses and data accesses
2 Non-Maskable-Interrupt #NMI External NMI signal
3 Breakpoint #BP INT3 instruction
4 Overflow #OF INTO instruction
5 Bound-Range #BR BOUND instruction
6 Invalid-Opcode #UD Invalid instructions
7 Device-Not-Available #NM x87 instructions
8 Double-Fault #DFException during the handling of another exception or 
interrupt
9 Coprocessor-Segment-Overrun — Unsupported (Reserved)
10 Invalid-TSS #TS Task-state segment access and task switch
11 Segment-Not-Present #NP Segment register loads
12 Stack #SS SS register loads and stack references
13 General-Protection #GP Memory accesses and protection checks
14 Page-Fault #PF Memory accesses when paging enabled
15 Reserved —
16x87 Floating-Point Exception-Pending#MF x87 floating-point instructions
17 Alignment-Check #AC Misaligned memory accesses
18 Machine-Check #MC Model specific
19 SIMD Floating-Point #XF SSE floating-point instructions
20 Reserved —
21 Control-Protection Exception #CP RET/IRET or other control transfer
22–27 Reserved —
28 Hypervisor Injection Exception #HV Event injection
29 VMM Communication Exception #VC Virtualization event
30 Security Exception #SX Security-sensitive event in host
31 Reserved —
0–255 External Interrupts (Maskable) #INTR External interrupts
0–255 Software Interrupts — INT n instruction
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The following sections describe each interrupt in detail. The format of the error code reported by each 
interrupt is described in Section “Error Codes” on page 261.Table 8-2. Interrupt Vector Classification
Vector Interrupt (Exception) Type Precise Class2
0 Divide-by-Zero-Error FaultyesContributory
1 Debug Fault or Trap
Benign2 Non-Maskable-Interrupt — —
3 BreakpointTrap
yes4 Overflow
5 Bound-Range
Fault 6 Invalid-Opcode7 Device-Not-Available8 Double-Fault Abort no
9 Coprocessor-Segment-Overrun
10 Invalid-TSS
Fault yesContributory11 Segment-Not-Present
12 Stack13 General-Protection14 Page-Fault Benign or Contributory
16x87 Floating-Point Exception-
Pending Faultno
Benign 17 Alignment-Check yes
18 Machine-Check Abort no
19 SIMD Floating-Point Fault yes
20 Reserved
21 Control Protection Fault yes Contributory
22–27 Reserved
28 Hypervisor Injection Exception – – Benign
29 VMM Communication Exception Fault yes Contributory
30 Security Exception – yes Contributory 
31 Reserved
0–255 External Interrupts (Maskable)—1—1Benign0–255 Software Interrupts
Note:
1. External interrupts are not classified by type or whether or not they are precise.
2. See Section “#DF—Double-Fault Exception (Vector 8)” on page 250 for a definition of benign and contributory
classes.
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8.2.1  #DE—Divide-by-Zero-Error Exception (Vector 0)
A #DE exception occurs when the denominator of a DIV instruction or an IDIV instruction is 0. A 
#DE also occurs if the result is too large to be represented in the destination.
#DE cannot be disabled.
Error Code Returned.  None.
Program Restart.  #DE is a fault-type exception. The saved instruction pointer points to the 
instruction that caused the #DE.
8.2.2  #DB—Debug Exception (Vector 1)
When the debug-exception mechanism is enabled, a #DB exception can occur under any of the

Note:
classes.
When the debug-exception mechanism is enabled, a #DB exception can occur under any of the 
following circumstances:
•Instruction execution.
•Instruction single stepping.
•Data read.
•Data write.
•I/O read.
•I/O write.
•Task switch.
•Debug-register access, or general detect fault (debug register access when DR7.GD=1).
•Executing the INT1 instruction (opcode 0F1h).
#DB conditions are enabled and disabled using the debug-control register, DR7 and RFLAGS.TF. 
Each #DB condition is described in more detail in Section “Setting Breakpoints” on page 401.
The processor can be configured to generate a #DB exception as a trap following the successful 
execution of a bus lock when the processor is at privilege level > 0.  Section 13.1.3.6 on page 406 
describes the bus lock trap mechanism in further detail.
The conditions under which a bus lock occurs are described in Section 7.3.3 on page 195.
Error Code Returned.  None. #DB information is returned in the debug-status register, DR6.
Program Restart.  #DB can be either a fault-type or trap-type exception. In the following cases, the 
saved instruction pointer points to the instruction that caused the #DB:
•Invalid debug-register access, or general detect.
In all other cases, the instruction that caused the #DB is completed, and the saved instruction pointer 
points to the instruction after the one that caused the #DB.
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The RFLAGS.RF bit can be used to restart an instruction following an instruction breakpoint resulting 
in a #DB. In most cases, the processor clears RFLAGS.RF to 0 after every instruction is successfully executed. However, in the case of the IRET, JMP, CALL, and INT n (through a task gate) instructions, 
RFLAGS.RF is not cleared to 0 until the next instruction successfully executes.
When a non-debug exception occurs (or when a string instruction is interrupted), the processor normally sets RFLAGS.RF to 1 in the rFLAGS image  that is pushed on the interrupt stack. A 
subsequent IRET back to the interrupted program pops the rFLAGS image off the stack and into the RFLAGS register, with RFLAGS.RF=1. The interrupted instruction executes without causing an instruction breakpoint, after which the processor clears RFLAGS.RF to 0.
However, when a #DB exception occurs, the processor clears RFLAGS.RF to 0 in the rFLAGS image 
that is pushed on the interrupt stack. The #DB handler has two options:
•Disable the instruction breakpoint completely.
•Set RFLAGS.RF to 1 in the interrupt-stack rFLAGS image. The instruction breakpoint condition
is ignored immediately after the IRET, but reoccurs if the instruction address is accessed later, ascan occur in a program loop.
8.2.3  NMI—Non-Maskable-Interrupt Exception (Vector 2)
An NMI exception occurs as a result of system logic signaling a non-maskable interrupt to the 
Program Restart.  NMI is an interrupt. The processor recognizes an NMI at an instruction boundary. 
The saved instruction pointer points to the instruction immediately following the boundary where the NMI was recognized.
Masking.  NMI cannot be masked. However, when an NMI is recognized by the processor, 
recognition of subsequent NMIs are disabled until an IRET instruction is executed. 
8.2.4  #BP—Breakpoint Exception (Vector 3)
A #BP exception occurs when an INT3 instruction is executed. The INT3 is normally used by debug 
software to set instruction breakpoints by replacing instruction-opcode bytes with the INT3 opcode.
#BP cannot be disabled.
Program Restart.  #BP is a trap-type exception. The saved instruction pointer points to the byte after 
the INT3 instruction. This location can be the start of the next instruction. However, if the INT3 is used 
to replace the first opcode bytes of an instruction, the restart location is likely to be in the middle of an instruction. In the latter case, the debug software must replace the INT3 byte with the correct instruction byte. The saved RIP instruction pointer must then be decremented by one before returning 
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to the interrupted program. This allows the program to be restarted correctly on the interrupted-
instruction boundary.
8.2.5  #OF—Overflow Exception (Vector 4)
An #OF exception occurs as a result of executing an INTO instruction while the overflow bit in 
RFLAGS is set to 1 (RFLAGS.OF=1).
#OF cannot be disabled.
Program Restart.  #OF is a trap-type exception. The saved instruction pointer points to the 
instruction following the INTO instruction that caused the #OF.
8.2.6  #BR—Bound-Range Exception (Vector 5)
A #BR exception can occur as a result of executing the BOUND instruction. The BOUND instruction 
compares an array index (first operand) with the lower bounds and upper bounds of an array (second 
operand). If the array index is not within the array boundary, the #BR occurs.
#BR cannot be disabled.
Program Restart.  #BR is a fault-type exception. The saved instruction pointer points to the BOUND 
instruction that caused the #BR.
8.2.7  #UD—Invalid-Opcode Exception (Vector 6)
A #UD exception occurs when an attempt is made to execute an invalid or undefined opcode. The 
validity of an opcode often depends on the processor operating mode. A #UD occurs under the following conditions:
•Execution of any reserved or undefined opcode in any mode.
•Execution of the UD0, UD1 or UD2 instructions.
•Use of the LOCK prefix on an instruction that cannot be locked.
•Use of the LOCK prefix on a lockable instruction with a non-memory target location.
•Execution of an instruction with an invalid-operand type.
•Execution of the SYSENTER or SYSEXIT instructions in long mode.
•Execution of any of the following instructions in 64-bit mode: AAA, AAD, AAM, AAS, BOUND,
CALL (opcode 9A), DAA, DAS, DEC, INC, INTO, JMP (opcode EA), LDS, LES, POP (DS, ES,SS), POPA, PUSH (CS, DS, ES, SS), PUSHA, SALC.
•Execution of the ARPL, LAR, LLDT, LSL, LTR, SLDT, STR, VERR, or VERW instructions whenprotected mode is not enabled, or when virtual-8086 mode is enabled.
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•Execution of any legacy SSE instruction when CR4.OSFXSR is cleared to 0. (For further
information, see Section “FXSA VE/FXRSTOR Support (OSFXSR)” on page 49.
•Execution of any SSE instruction (uses YMM/XMM registers), or 64-bit media instruction (usesMMX™ registers) when CR0.EM = 1. 
•Execution of any SSE floating-point instruction (uses YMM/XMM registers) that causes anumeric exception when CR4.OSXMMEXCPT = 0.
•Use of the DR4 or DR5 debug registers when CR4.DE = 1.
•Execution of RSM when not in SMM mode.
See the specific instruction description (in the other volumes) for additional information on invalid conditions.
#UD cannot be disabled.
Program Restart.  #UD is a fault-type exception. The saved instruction pointer points to the 
instruction that caused the #UD.
8.2.8  #NM—Device-Not-Available Exception (Vector 7)
A #NM exception occurs under any of the following conditions:
•An FWAIT/WAIT instruction is executed when CR0.MP=1 and CR0.TS=1.
•Any x87 instruction other than FWAIT is executed when CR0.EM=1. 
•Any x87 instruction is executed when CR0.TS=1. The CR0.MP bit controls whether the
FWAIT/WAIT instruction causes an #NM exception when TS=1.
•Any 128-bit or 64-bit media instruction when CR0.TS=1.
#NM can be enabled or disabled under the control of the CR0.MP, CR0.EM, and CR0.TS bits as described above. See Section 3.1.1 for more information on the CR0 bits used to control the #NM exception.
Program Restart.  #NM is a fault-type exception. The saved instruction pointer points to the 
instruction that caused the #NM.
8.2.9  #DF—Double-Fault Exception (Vector 8)
A #DF exception can occur when a second exception occurs during the handling of a prior (first) 
exception or interrupt handler. 
Usually, the first and second exceptions can be handled sequentially without resulting in a #DF. In this 
case, the first exception is considered benign , as it does not harm the ability of the processor to handle 
the second exception. 
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In some cases, however, the first exception adversely affects the ability of the processor to handle the 
second exception. These exceptions contribute to the occurrence of a #DF, and are called contributory  
exceptions. If a contributory exception is followed by another contributory exception, a double-fault exception occurs. Likewise, if a page fault is followed by another page fault or a contributory exception, a double-fault exception occurs.
Table 8-3 shows the conditions under which a #DF occurs. Page faults are either benign or

Table 8-3 shows the conditions under which a #DF occurs. Page faults are either benign or 
contributory, and are listed separately. See the “Class” column in Table 8-2 on page 246 for information on whether an exception is benign or contributory. 
If a third interrupting event occurs while transferring control to the #DF handler, the processor shuts 
down. Only an NMI, RESET, or INIT can restart the processor in this case. However, if the processor shuts down as it is executing an NMI handler, the processor can only be restarted with RESET or INIT.
#DF cannot be disabled.
Error Code Returned.  Zero.
Program Restart.  #DF is an abort-type exception. The saved instruction pointer is undefined, and the 
program cannot be restarted.
8.2.10  Coprocessor-Segment-Overrun Exception (Vector 9)
This interrupt vector is reserved.  It is for a discontinued exception originally used by processors that 
supported external x87-instruction coprocessors. On those processors, the exception condition is 
caused by an invalid-segment or invalid-page access on an x87-instruction coprocessor-instruction operand. On current processors, this condition causes a general-protection exception to occur.
Error Code Returned.  Not applicable.
Program Restart.  Not applicable.Table 8-3. Double-Fault Exception Conditions
First Interrupting Event Second Interrupting Event
Contributory Exceptions
• Divide-by-Zero-Error Exception• Invalid-TSS Exception • Segment-Not-Present Exception• Stack Exception• General-Protection ExceptionInvalid-TSS Exception Segment-Not-Present ExceptionStack ExceptionGeneral-Protection Exception
Page Fault ExceptionPage Fault ExceptionInvalid-TSS Exception Segment-Not-Present ExceptionStack ExceptionGeneral-Protection Exception
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8.2.11  #TS—Invalid-TSS Exception (Vector 10)
A #TS exception occurs when an invalid reference is made to a segment selector as part of a task 
switch. A #TS also occurs during a privilege-changing control transfer (through a call gate or an interrupt gate), if a reference is made to an invalid stack-segment selector located in the TSS. Table 8-4 
lists the conditions under which a #TS occurs and the error code returned by the exception mechanism.
#TS cannot be disabled.
Error Code Returned.  See Table 8-4 for a list of error codes returned by the #TS exception.
Program Restart.  #TS is a fault-type exception. If the exception occurs before loading the segment 
selectors from the TSS, the saved instruction pointer points to the instruction that caused the #TS. 
However, most #TS conditions occur due to errors with the loaded segment selectors. When an error is found with a segment selector, the hardware task-switch mechanism completes loading the new task state from the TSS, and then triggers the #TS exception mechanism. In this case, the saved instruction pointer points to the first instruction in the new task.
In long mode, a #TS cannot be caused by a task switch, because the hardware task-switch mechanism 
is disabled. A #TS occurs only as a result of a control transfer through a gate descriptor that results in an invalid stack-segment reference using an SS selector in the TSS. In this case, the saved instruction pointer always points to the control-transfer instruction that caused the #TS.
Table 8-4. Invalid-TSS Exception Conditions
Selector 
ReferenceError Condition Error Code
Task-State 
SegmentTSS limit check on a task switchTSS Selector IndexTSS limit check on an inner-level stack pointer
LDT SegmentLDT does not point to GDT
LDT Selector IndexLDT reference outside GDT
GDT entry is not an LDT descriptorLDT descriptor is not present
Code SegmentCS reference outside GDT or LDT
CS Selector IndexPrivilege check (conforming DPL 
> CPL)
Privilege check (non-conforming DPL ¹ CPL)
Type check (CS not executable)
Data SegmentData segment reference outside GDT or LDTDS, ES, FS or GS Selector IndexType check (data segment not readable)
Stack SegmentSS reference outside GDT or LDT
SS Selector IndexPrivilege check (stack segment descriptor DPL ¹ CPL)
Privilege check (stack segment selector RPL ¹ CPL)
Type check (stack segment not writable)
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8.2.12  #NP—Segment-Not-Present Exception (Vector 11)
An #NP occurs when an attempt is made to load a segment or gate with a clear present bit, as described 
in the following situations:
•Using the MOV , POP, LDS, LES, LFS, or LGS instructions to load a segment selector (DS, ES, FS,
and GS) that references a segment descriptor containing a clear present bit (descriptor.P=0). 
•Far transfer to a CS that is not present.
•Referencing a gate descriptor containing a clear present bit.
•Referencing a TSS descriptor containing a clear present bit. This includes attempts to load the TSSdescriptor using the LTR instruction.
•Attempting to load a descriptor containing a clear present bit into the LDTR using the LLDTinstruction.
•Loading a segment selector (CS, DS, ES, FS, or GS) as part of a task switch, with the segmentdescriptor referenced by the segment selector having a clear present bit. In long mode, an #NPcannot be caused by a task switch, because the hardware task-switch mechanism is disabled.
When loading a stack-segment selector (SS) that references a descriptor with a clear present bit, a stack exception (#SS) occurs. For information on the #SS exception, see the next section, “#SS—Stack Exception (Vector 12).”
#NP cannot be disabled.
Error Code Returned.  The segment-selector index of the segment descriptor causing the #NP 
Program Restart.  #NP is a fault-type exception. In most cases, the saved instruction pointer points to 
the instruction that loaded the segment selector resulting in the #NP. See Section “Exceptions During a 
Task Switch” on page 261 for a description of the consequences when this exception occurs during a task switch.
8.2.13  #SS—Stack Exception (Vector 12)
An #SS exception can occur in the following situations:
•Implied stack references in which the stack address is not in canonical form. Implied stack
references include all push and pop instructions, and any instruction using RSP or RBP as a baseregister.
•Attempting to load a stack-segment selector that references a segment descriptor containing a clearpresent bit (descriptor.P=0).
•Any stack access that fails the stack-limit check.
#SS cannot be disabled.
Error Code Returned.  The error code depends on the cause of the #SS, as shown in Table 8-5 on 
page 254:
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Program Restart.  #SS is a fault-type exception. In most cases, the saved instruction pointer points to 
the instruction that caused the #SS. See Section “Exceptions During a Task Switch” on page 261 for a 
description of the consequences when this exception occurs during a task switch.
8.2.14  #GP—General-Protection Exception (Vector 13)
Table 8-6 describes the general situations that can cause a #GP exception. The table is not an 
exhaustive, detailed list of #GP conditions, but rather a guide to the situations that can cause a #GP. If 
an invalid use of an AMD64 architectural feature results in a #GP, the specific cause of the exception is described in detail in the section describing the architectural feature.
#GP cannot be disabled.
Error Code Returned.  As shown in Table 8-6, a selector index is reported as the error code if the 
#GP is due to a segment-descriptor access. In all other cases, an error code of 0 is returned.
Program Restart.  #GP is a fault-type exception. In most cases, the saved instruction pointer points to 
the instruction that caused the #GP. See Section “Exceptions During a Task Switch” on page 261 for a 
description of the consequences when this exception occurs during a task switch.Table 8-5. Stack Exception Error Codes
Stack Exception Cause Error Code
Stack-segment descriptor present bit is clear SS Selector Index
Stack-limit violation 0
Stack reference using a non-canonical address 0
Table 8-6. General-Protection Exception Conditions
Error Condition Error Code
Any segment privilege-check violation, while loading a segment register.
Selector IndexAny segment type-check violation, while loading a segment register.

Loading a null selector into the CS, SS, or TR register.Accessing a gate-descriptor containing a null segment selector.Referencing an LDT descriptor or TSS descriptor located in the LDT.Attempting a control transfer to a busy TSS (except IRET).In 64-bit mode, loading a non-canonical base address into the GDTR or IDTR.In long mode, accessing a system or call-gate descriptor whose extended type field is not 0.In long mode, accessing a system descriptor containing a non-canonical base address.In long mode, accessing a gate descriptor containing a non-canonical offset.In long mode, accessing a gate descriptor that does not point to a 64-bit code segment.In long mode, accessing a 16-bit gate descriptor.In long mode, attempting a control transfer to a TSS or task gate.
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8.2.15  #PF—Page-Fault Exception (Vector 14)
A #PF exception can occur during a memory access in any of the following situations:
•A page-translation-table entry or physical page involved in translating the memory access is not
present in physical memory. This is indicated by a cleared present bit (P=0) in the translation-tableentry.
•An attempt is made by the processor to load the instruction TLB with a translation for a non-executable page.
•The memory access fails the paging-protection checks (user/supervisor, read/write, or both).
•A reserved bit in one of the page-translation-table entries is set to 1. A #PF occurs for this reasononly when CR4.PSE=1 or CR4.PAE=1.
•A data access to a user-mode address caused a protection key violation.
#PF cannot be disabled.
CR2 Register.  The virtual (linear) address that caused the #PF is stored in the CR2 register. The 
legacy CR2 register is 32 bits long. The CR2 register in the AMD64 architecture is 64 bits long, as shown in Figure 8-1 on page 256. In AMD64 implementations, when either software or a page fault 
causes a write to the CR2 register, only the low-order 32 bits of CR2 are used in legacy mode; the processor clears the high-order 32 bits.Any segment limit-check or non-canonical address violation (except when using the SS register).
0Accessing memory using a null segment register.
Writing memory using a read-only segment register.Attempting to execute an SSE instruction specifying an unaligned memory operand.Attempting to execute code that is past the CS segment limit or at a non-canonical RIP.Executing a privileged instruction while CPL is > 0.Executing an instruction that is more than 15 bytes long.Writing a 1 into any register field that is reserved, must be zero (MBZ).Using WRMSR to write a read-only MSR.Using WRMSR to write a non-canonical value into an MSR that must be canonical.Using WRMSR to set an invalid type encoding in an MTRR or the PAT MSR.
0Enabling paging while protected mode is disabled.Setting CR0.NW=1 while CR0.CD=0.Any long-mode consistency-check violation.Table 8-6. General-Protection Exception Conditions (continued)
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Figure 8-1. Control Register 2 (CR2)
Error Code Returned.  The page-fault error code is pushed onto the page-fault exception-handler 
stack. See Section “Page-Fault Error Code” on page 262 for a description of this error code.
Program Restart.  #PF is a fault-type exception. In most cases, the saved instruction pointer points to 
the instruction that caused the #PF. See Section “Exceptions During a Task Switch” on page 261 for a 
description of what can happen if this exception occurs during a task switch.
8.2.16  #MF—x87 Floating-Point Exception-Pending (Vector 16)
The #MF exception is used to handle unmasked x87 floating-point exceptions. An #MF occurs when 
all of the following conditions are true:
•CR0.NE=1.
•An unmasked x87 floating-point exception is pending. This is indicated by an exception bit in thex87 floating-point status-word register being set to 1
•The corresponding mask bit in the x87 floating-point control-word register is cleared to 0. 
•The FWAIT/WAIT instruction or any waiting floating-point instruction is executed.
If there is an exception mask bit (in the FPU control word) set, the exception is not reported. Instead, the x87-instruction unit responds in a default manner and execution proceeds normally.
The x87 floating-point exceptions reported by the #MF exception are (including mnemonics):
•IE—Invalid-operation exception (also called #I), which is either:
- IE alone—Invalid arithmetic-operand exception (also called #IA), or- SF and IE together—x87 Stack-fault exception (also called #IS).
•DE—Denormalized-operand exception (also called #D).
•ZE—Zero-divide exception (also called #Z).
•OE—Overflow exception (also called #O).
•UE—Underflow exception (also called #U).
•PE—Precision exception (also called #P or inexact-result exception).
Error Code Returned.  None. Exception information is provided by the x87 status-word register. See 
“x87 Floating-Point Programming” in V olume 1 for more information on using this register.
Program Restart.  #MF is a fault-type exception. The #MF exception is not precise, because multiple 
instructions and exceptions can occur before the #MF handler is invoked. Also, the saved instruction 63 0
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pointer does not point to the instruction that caused the exception resulting in the #MF. Instead, the 
saved instruction pointer points to the x87 floating-point instruction or FWAIT/WAIT instruction that is about to be executed when the #MF occurs. The address of the last instruction  that caused an x87 
floating-point exception is in the x87 instruction-pointer register. See “x87 Floating-Point Programming” in V olume 1 for information on accessing this register.
Masking.  Each type of x87 floating-point exception can be masked by setting the appropriate bits in 
the x87 control-word register. See “x87 Floating-Point Programming” in V olume 1 for more information on using this register.
#MF can also be disabled by clearing the CR0.NE bit to 0. See Section “Numeric Error (NE) Bit” on 
page 43 for more information on using this bit.
8.2.17  #AC—Alignment-Check Exception (Vector 17)
An #AC exception occurs when an unaligned-memory data reference is performed while alignment 
checking is enabled.
After a processor reset, #AC exceptions are disabled. Software enables the #AC exception by setting 
the following register bits:
•CR0.AM=1.
•RFLAGS.AC=1.
When the above register bits are set, an #AC can occur only when CPL=3. #AC never occurs when 
CPL  3.
Table 8-7 lists the data types and the alignment boundary required to avoid an #AC exception when the mechanism is enabled.
Table 8-7. Data-Type Alignment
Supported Data TypeRequired Alignment
(Byte Boundary)
Word 2
Doubleword 4
Quadword 8
Bit string 2, 4 or 8 (depends on operand size)
256-bit media 16
128-bit media 16
64-bit media 8
Segment selector 2
32-bit near pointer 4
32-bit far pointer 2
48-bit far pointer 4
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Program Restart.  #AC is a fault-type exception. The saved instruction pointer points to the 
instruction that caused the #AC.
8.2.18  #MC—Machine-Check Exception (Vector 18)
The #MC exception is model specific. Processor implementations are not required to support the #MC 
exception, and those implementations that do support #MC can vary in how the #MC exception mechanism works.
The exception is enabled by setting CR4.MCE to 1. The machine-check architecture can include 
model-specific masking for controlling the reporting of some errors. Refer to Chapter 9, “Machine Check Architecture,” for more information.
Error Code Returned.  None. Error information is provided by model-specific registers (MSRs) 
defined by the machine-check architecture.
Program Restart.  #MC is an abort-type exception. If the RIPV flag (RIP valid) is set in the 
MCG_Status MSR, the saved CS and rIP point to the instruction at which the interrupted process thread can be restarted. If RIPV is clear, there is no reliable way to restart the program. If the EIPV flag (EIP valid) is set in the MCG_Status MSR, the saved CS and rIP point to the process thread that caused the error. If EIPV is clear, the CS:rIP of the instruction causing the failure is not known or the machine check is not related to a specific instruction.
8.2.19  #XF—SIMD Floating-Point Exception (Vector 19)
The #XF exception is used to handle unmasked SSE floating-point exceptions. A #XF exception 
occurs when all of the following conditions are true:
•A SSE floating-point exception occurs. The exception causes the processor to set the appropriate
exception-status bit in the MXCSR register to 1.
•The exception-mask bit in the MXCSR that corresponds to the SSE floating-point exception isclear (=0).

•CR4.OSXMMEXCPT=1, indicating that the operating system supports handling of SSE floating-point exceptions.x87 Floating-point single-precision 4
x87 Floating-point double-precision 8
x87 Floating-point extended-precision 8
x87 Floating-point save areas 2 or 4 (depends on operand size)Table 8-7. Data-Type Alignment (continued)
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The exception-mask bits are used by software to specify the handling of SSE floating-point 
exceptions. When the corresponding mask bit is cleared to 0, an exception occurs under the control of the CR4.OSXMMEXCPT bit. However, if the mask bit is set to 1, the SSE floating-point unit responds in a default manner and execution proceeds normally.
The CR4.OSXMMEXCPT bit specifies the interrupt vector to be taken when an unmasked SSE 
floating-point exception occurs. When CR4.OSXMMEXCPT=1, the #XF interrupt vector is taken when an exception occurs. When CR4.OSXMMEXCPT=0, the #UD (undefined opcode) interrupt vector is taken when an exception occurs.
The SSE floating-point exceptions reported by the #XF exception are (including mnemonics):
•IE—Invalid-operation exception (also called #I).
Each type of SSE floating-point exception can be masked by setting the appropriate bits in the 
MXCSR register. #XF can also be disabled by clearing the CR4.OSXMMEXCPT bit to 0. 
Error Code Returned.  None. Exception information is provided by the SSE floating-point MXCSR 
register. See “Instruction Reference” in V olume 4 for more information on using this register.
Program Restart.  #XF is a fault-type exception. Unlike the #MF exception, the #XF exception is 
precise. The saved instruction pointer points to the instruction that caused the #XF.
8.2.20  #CP—Control-Protection Exception (Vector 21)
A #CP exception is generated when shadow stacks are enabled (CR4.CET=1) and any of the following 
situations occur:
•For RET or IRET instructions, the return addresses on the shadow stack and the data stack do not
match.
•An invalid supervisor shadow stack token is encountered by the CALL, RET, IRET, SETSSBSYor RSTORSSP instructions or during the delivery of an interrupt or exception.
•For inter-privilege RET and IRET instructions, the SSP is not 8-byte aligned, or the previous SSPfrom shadow stack is not 4-byte aligned or, in legacy or compatibility mode, is not less than 4GB.
•A task switch initiated by IRET where the incoming SSP is not aligned to 4 bytes or is not less than4GB.
Error Code Returned. The #CP error code is pushed onto the control-protection exception-handler stack. See Section “Control-Protection Error Code” on page 262 for a description of this error code.
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Program Restart.  #CP is a fault-type exception. In most cases, the saved instruction pointer points to 
the instruction that caused the #CP. See Section “Exceptions During a Task Switch” on page 261 for a 
8.2.21  #HV—Hypervisor Injection Exception (Vector 28)
The #HV exception may be injected by the hypervisor into a secure guest VM to notify the VM of 
pending events. See Section 15.36.16 for details.
8.2.22  #VC—VMM Communication Exception (Vector 29)
The #VC exception is generated when certain events occur inside a secure guest VM. See 
Section 15.35.5 for more details.
8.2.23  #SX—Security Exception (Vector 30)
The #SX exception is generated by security-sensitive events under SVM. See Section 15.28 for 
details.
8.2.24  User-Defined Interrupts (Vectors 32–255)
User-defined interrupts can be initiated either by system logic or software. They occur when:
•System logic signals an external interrupt request to the processor. The signaling mechanism and
the method of communicating the interrupt vector to the processor are implementation dependent.
•Software executes an INTn instruction. The INT n instruction operand provides the interrupt vector
number.
Both methods can be used to initiate an interrupt into vectors 0 through 255. However, because vectors 0 through 31 are defined or reserved by the AMD64 architecture, software should not use vectors in 
this range for purposes other than their defined use.
Program Restart.  The saved instruction pointer depends on the interrupt source:
•External interrupts are recognized on instruction boundaries. The saved instruction pointer pointsto the instruction immediately following the boundary where the external interrupt wasrecognized.
•If the interrupt occurs as a result of executing the INT n instruction, the saved instruction pointer
points to the instruction after the INT n.
Masking.  The ability to mask user-defined interrupts depends on the interrupt source:
•External interrupts can be masked using the RFLAGS.IF bit. Setting RFLAGS.IF to 1 enablesexternal interrupts, while clearing RFLAGS.IF to 0 inhibits them.
•Software interrupts (initiated by the INT n instruction) cannot be disabled.
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8.3 Exceptions During a Task Switch
An exception can occur during a task switch while loading a segment selector. Page faults can also 
occur when accessing a TSS. In these cases, the hardware task-switch mechanism completes loading the new task state from the TSS, and then triggers the appropriate exception mechanism. No other checks are performed. When this happens, the saved instruction pointer points to the first instruction in the new task.
In long mode, an exception cannot occur during a task switch, because the hardware task-switch 
mechanism is disabled.
8.4 Error Codes
The processor exception-handling mechanism reports error and status information for some exceptions using an error code. The error code is pushed onto the stack by the exception mechanism during the control transfer into the exception handler. The error code formats are described in the 
8.4.1  Selector-Error Code
Figure 8-2 shows the format of the selector-error code. 
Figure 8-2. Selector Error Code
The information reported by the selector-error code includes:
•EXT—Bit 0. If this bit is set to 1, the exception source is external to the processor. If cleared to 0,
the exception source is internal to the processor.
•IDT—Bit 1. If this bit is set to 1, the error-code selector-index field references a gate descriptor
located in the interrupt-descriptor table (IDT). If cleared to 0, the selector-index field references a
descriptor in either the global-descriptor table (GDT) or local-descriptor table (LDT), as indicatedby the TI bit.
•TI—Bit 2. If this bit is set to 1, the error-code selector-index field references a descriptor in theLDT. If cleared to 0, the selector-index field references a descriptor in the GDT. The TI bit isrelevant only when the IDT bit is cleared to 0.
•Selector Index —Bits 15:3. The selector-index field specifies the index into either the GDT, LDT,
or IDT, as specified by the IDT and TI bits.
Some exceptions return a zero in the selector-error code.31 16 15 3 2 1 0
Reserved Selector Index
TI
IDT
EXT
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8.4.2  Page-Fault Error Code
Figure 8-4 shows the format of the page-fault error code. 
Figure 8-3. Page-Fault Error Code
The information reported by the page-fault error code includes:
•P—Bit 0. If this bit is cleared to 0, the page fault was caused by a not-present page. If this bit is set
to 1, the page fault was caused by a page-protection violation.
•R/W—Bit 1. If this bit is cleared to 0, the access that caused the page fault is a memory read. If this
bit is set to 1, the memory access that caused the page fault was a write. This bit does notnecessarily indicate the cause of the page fault was a read or write violation.
•U/S—Bit 2. If this bit is cleared to 0, an access in supervisor mode (CPL=0, 1, or 2) caused the
page fault. If this bit is set to 1, an access in user mode (CPL=3) caused the page fault. This bit doesnot necessarily indicate the cause of the page fault was a privilege violation.
•RSV—Bit 3. If this bit is set to 1, the page fault is a result of the processor reading a 1 from areserved field within a page-translation-table entry. This type of page fault occurs only whenCR4.PSE=1 or CR4.PAE=1. If this bit is cleared to 0, the page fault was not caused by theprocessor reading a 1 from a reserved field.
•I/D—Bit 4. If this bit is set to 1, it indicates that the access that caused the page fault was aninstruction fetch. Otherwise, this bit is cleared to 0. This bit is only defined if no-execute feature isenabled (EFER.NXE=1 && CR4.PAE=1).

•PK—Bit 5. If this bit is set to 1, it indicates that a data access to a user-mode address caused aprotection key violation. This fault only occurs if memory protection keys are enabled(CR4.PKE=1).
•SS—Bit 6. If this bit is set to 1, the page fault was caused by a shadow stack access. This bit is only
set when the shadow stack feature is enabled (CR4.CET=1).
•RMP —Bit 31. If this bit is set to 1, the page fault is a result of the processor encountering an RMP
violation. This type of page fault only occurs when SYSCFG[SecureNestedPagingEn]=1. If thisbit is cleared to 0, the page fault was not caused by an RMP violation. See section 15.36.10 foradditional information.
8.4.3  Control-Protection Error Code 
Figure 8-4 shows the format of the #CP error code. 31 30 7 6 5 4 3 2 1 0RMPReserved 
S S 
PK 
I/D
RSV
U/S
R/W
P
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Figure 8-4. Control-Protection Error Code 
The control-protection error codes are defined below:
8.5 Priorities
To allow for consistent handling of multiple-interrupt conditions, simultaneous interrupts are 
prioritized by the processor. The AMD64 architecture defines priorities between groups of interrupts, and interrupt prioritization within a group is implementation dependent. Table 8-9 shows the interrupt priorities defined by the AMD64 architecture.
When simultaneous interrupts occur, the processor transfers control to the highest-priority interrupt 
handler. Lower-priority interrupts from external sources are held pending by the processor, and they are handled after the higher-priority interrupt is handled. Lower-priority interrupts that result from internal sources are discarded. Those interrupts reoccur when the high-priority interrupt handler completes and transfers control back to the interrupted instruction. Software interrupts are discarded as well, and reoccur when the software-interrupt instruction is restarted.31 15 14  0
Reserved Control-protection error code 
Table 8-8. Control-Protection Error Codes  
Error Code Value Name Cause 
1 NEAR-RET A RET (near) instruction encountered a return address mismatch. 
2 FAR-RET/IRET A RET (far) or IRET instruction encountered a return address mismatch.
3 RSTORSSPAn RSTORSSP instruction encountered an invalid shadow stack restore 
token. 
4 SETSSBSYA SETSSBSY instruction encountered an invalid supervisor shadow stack token. 
Table 8-9. Simultaneous Interrupt Priorities
Interrupt 
PriorityInterrupt ConditionInterrupt 
Vector
(High)
0Processor Reset —
Machine-Check Exception 18
1External Processor Initialization (INIT)
— SMI Interrupt
External Clock Stop (Stpclk)
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8.5.1  Floating-Point Exception Priorities
Floating-point exceptions (SSE and x87 floating-point) can be handled in one of two ways:
•Unmasked exceptions are reported in the appropriate floating-point status register, and a software-
interrupt handler is invoked. See Section “#MF—x87 Floating-Point Exception-Pending (Vector16)” on page 256 and Section “#XF—SIMD Floating-Point Exception (Vector 19)” on page 258
for more information on the floating-point interrupts.2Data, and I/O Breakpoint (Debug Register)1Single-Step Execution Instruction Trap (RFLAGS.TF=1)
3 Non-Maskable Interrupt 2
4 Maskable External Interrupt (INTR) 32–255
5Instruction Breakpoint (Debug Register) 1
Code-Segment-Limit Violation1 13
Instruction-Fetch Page Fault1 14
6Invalid Opcode Exception1 6
Device-Not-Available Exception 7
Instruction-Length Violation (> 15 Bytes) 13
7Divide-by-zero Exception 0
Invalid-TSS Exception 10
Segment-Not-Present Exception 11
Stack Exception 12
General-Protection Exception 13
Data-Access Page Fault 14
Floating-Point Exception-Pending Exception 16
Alignment-Check Exception 17
SIMD Floating-Point Exception 19
Control-Protection Exception 21
Hypervisor Injection Exception 28
VMM Communication Exception 29
Note:
1. This reflects the relative priority for faults encountered when fetching the first byte of an instruction. In the fetching and decoding
of subsequent bytes of an instruction, if those bytes span the segment limit or cross into a non-executable or not-present page,
the fetch will result in a #GP(0) fault or #PF as appropriate, preventing those bytes from being accessed. However, if theinstruction can be determined to be invalid based just on the bytes preceding that boundary, a #UD fault may take priority. Thisbehavior is model-dependent.Table 8-9. Simultaneous Interrupt Priorities (continued)
Interrupt 
Vector
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•Masked exceptions are also reported in the appropriate floating-point status register. Instead of
transferring control to an interrupt handler, however, the processor handles the exception in adefault manner and execution proceeds.
If the processor detects more than one exception while executing a single floating-point instruction, it prioritizes the exceptions in a predictable manner. When responding in a default manner to masked exceptions, it is possible that the processor acts only on the high-priority exception and ignores lower-priority exceptions. In the case of vector (SIMD) floating-point instructions, priorities are set on sub-operations, not across all operations. For example, if the processor detects and acts on a QNaN operand in one sub-operation, the processor can still detect and act on a denormal operand in another sub-operation.
When reporting SSE floating-point exceptions before taking an interrupt or handling them in a default 
manner, the processor first classifies the exceptions as follows:
•Input exceptions  include SNaN operand (#I), invalid operation (#I), denormal operand (#D), or
zero-divide (#Z). Using a NaN operand with a maximum, minimum, compare, or convert
instruction is also considered an input exception.
•Output exceptions  include numeric overflow (#O), numeric underflow (#U), and precision (#P).
Using the above classification, the processor applies the following procedure to report the exceptions:
1. The exceptions for all sub-operations are prioritized.2. The exception conditions for all sub-operations are logically ORed together to form a single set of
exceptions covering all operations. For example, if two sub-operations produce a denormal result,
only one denormal exception is reported.
3. If the set of exceptions includes any unmasked  input exceptions, all input exceptions are reported
in MCXSR, and no output exceptions are reported. Otherwise, all input and output exceptions arereported in MCXSR.
4. If any exceptions are unmasked, control is transferred to the appropriate interrupt handler.
Table 8-10 on page 265 lists the priorities for simultaneous floating-point exceptions.
Table 8-10. Simultaneous Floating-Point Exception Priorities
Exception 
PriorityException Condition
(High)
0SNaN Operand
#INaN Operand of Maximum, Minimum, Compare, and Convert 
Instructions (Vector Floating-Point)
Stack Overflow (x87 Floating-Point)Stack Underflow (x87 Floating-Point)
1 QNaN Operand —
2Invalid Operation (Remaining Conditions) #I
Zero Divide #Z
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8.5.2  External Interrupt Priorities
classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. The organization of these priority classes is implementation dependent. A typical method is to use the upper four bits of the interrupt vector number to define the priority. Thus, interrupt vector 53h has a priority of 5 and interrupt vector 37h has a priority of 3.
This register, called the task-priority register (TPR), uses its four low-order bits to specify a task 
priority. The remaining 60 bits are reserved and must be written with zeros. Figure 8-5 shows the 
format of the TPR.
The TPR is available only in 64-bit mode.
Figure 8-5. Task Priority Register (CR8)
System software can use the TPR register to temporarily block low-priority interrupts from 
interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts. The TPR is cleared to 0 on reset. 
System software reads and writes the TPR using a MOV CR8 instruction. The MOV CR8 instruction 
requires a privilege level of 0. Programs running at any other privilege level cannot read or write the TPR, and an attempt to do so results in a general-protection exception (#GP).

A serializing instruction is not required after loading the TPR, because a new priority level is 
established when the MOV instruction completes execution. For example, assume two sequential TPR loads are performed, in which a low value is first loaded into TPR and immediately followed by a load 3 Denormal Operand #D
4Numeric Overflow #O
Numeric Underflow #U
5
(Low)Precision #P
63 4 3 0
Reserved, MBZTask Priority 
(TPR)Table 8-10. Simultaneous Floating-Point Exception Priorities (continued)
Exception 
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of a higher value. Any pending, lower-priority interrupt enabled by the first MOV CR8 is recognized 
between the two MOVs.
The TPR is an architectural abstraction of the interrupt controller (IC), which prioritizes and manages 
external interrupt delivery to the processor. The IC can be an external system device, or it can be integrated on the chip like the local advanced programmable interrupt controller (APIC). Typically, the IC contains a priority mechanism similar, if not identical to, the TPR. The IC, however, is implementation dependent, and the underlying priority mechanisms are subject to change. The TPR, by contrast, is part of the AMD64 architecture.
Effect of IC on TPR.  The features of the implementation-specific IC can impact the operation of the 
TPR. For example, the TPR might affect interrupt delivery only if the IC is enabled. Also, the mapping of an external interrupt to a specific interrupt priority is an implementation-specific behavior of the IC.
While the CR8 register provides the same functionality as the TPR at offset 80h of the local APIC, 
software should only use one mechanism to access the TPR. For example, updating the TPR with a write to the local APIC offset 0x80 but then reading it with a MOV CR8 is not guaranteed to return the same value that was written by the local APIC write.
8.6 Real-Mode Interrupt Control Transfers
In real mode, the IDT is a table of 4-byte entries, one entry for each of the 256 possible interrupts implemented by the system. The real mode IDT is often referred to as an interrupt vector table , or IVT. 
Table entries contain a far pointer (CS:IP pair) to an exception or interrupt handler. The base of the IDT is stored in the IDTR register, which is loaded with a value of 00h during a processor reset. Figure 8-6 on page 268 shows how the real-mode interrupt handler is located by the interrupt 
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Figure 8-6. Real-Mode Interrupt Control Transfer
When an exception or interrupt occurs in real mode, the processor performs the following:
1. Pushes the FLAGS register (EFLAGS[15:0]) onto the stack.2. Clears EFLAGS.IF to 0 and EFLAGS.TF to 0.3. Saves the CS register and IP register (RIP[15:0]) by pushing them onto the stack.4. Locates the interrupt-handler pointer (CS:IP) in the IDT by scaling the interrupt vector by four
and adding the result to the value in the IDTR.
5. Transfers control to the interrupt handler referenced by the CS:IP in the IDT.
Figure 8-7 on page 269 shows the stack after control is transferred to the interrupt handler in real 
mode.513-239.epsInterrupt-Descriptor
Table
4* +
IDT Base Address
Interrupt-Descriptor-Table RegisterInterrupt Vector CS
OffsetMemory
Interrupt Handler
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Figure 8-7. Stack After Interrupt in Real Mode
An IRET instruction is used to return to the interrupted program. When an IRET is executed, the 
processor performs the following:
1. Pops the saved CS value off the stack and into the CS register. The saved IP value is popped into
RIP[15:0].
2. Pops the FLAGS value off of the stack and into EFLAGS[15:0].3. Execution begins at the saved CS.IP location.
8.7 Legacy Protected-Mode Interrupt Control Transfers
In protected mode, the interrupt mechanism transfers control to an exception or interrupt handler 
through gate descriptors. In protected mode, the IDT is a table of 8-byte gate entries, one for each of the 256 possible interrupt vectors implemented by the system. Three gate types are allowed in the IDT:
•Task gates
If a reference is made to any other descriptor type in the IDT, a general-protection exception (#GP) 
occurs.
Interrupt-gate control transfers are similar to CALLs and JMPs through call gates. The interrupt 
mechanism uses gates (interrupt, trap, and task) to establish protected entry-points into the exception and interrupt handlers. 
The remainder of this chapter discusses control transfers through interrupt gates and trap gates. If the 
gate descriptor in the IDT is a task gate, a TSS-segment selector is referenced, and a task switch occurs. See Chapter 12, “Task Management,” for more information on the hardware task-switch mechanism.513-243.epsInterrupt-Handler and
Interrupted-Program
Stack
SS:SP+2+4
Return IPReturn CSReturn FLAGS
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8.7.1  Locating the Interrupt Handler
When an exception or interrupt occurs, the processor scales the interrupt vector number by eight and 
uses the result as an offset into the IDT. If the gate descriptor referenced by the IDT offset is an interrupt gate or a trap gate, it contains a segment-selector and segment-offset field (see Section “Legacy Segment Descriptors” on page 88 for a detailed description of the gate-descriptor format and fields). These two fields perform the same function as the pointer operand in a far control-transfer instruction. The gate-descriptor segment-selector field points to the target code-segment descriptor located in either the GDT or LDT. The gate-descriptor segment-offset field is the instruction-pointer offset into the interrupt-handler code segment. The code-segment base taken from the code-segment descriptor is added to the gate-descriptor segment-offset field to create the interrupt-handler virtual address (linear address).
Figure 8-8 on page 271 shows how the protected-mode interrupt handler is located by the interrupt 
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Figure 8-8. Protected-Mode Interrupt Control Transfer
8.7.2  Interrupt To Same Privilege
When a control transfer to an exception or interrupt handler at the same privilege level occurs (through 
an interrupt gate or a trap gate), the processor performs the following:
1. Pushes the EFLAGS register onto the stack.2. Clears the TF, NT, RF, and VM bits in EFLAGS to 0.3. The processor handles EFLAGS.IF based on the gate-descriptor type:*Interrupt Vector
+
513-240.epsVirtual-Address
Space
Code Segment+Interrupt
Code-Segment OffsetCS Selector DPL
Global or Local
Code-Segment BaseCS Limit DPLInterrupt-Descriptor-Table RegisterIDT Base Address IDT Limit8
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- If the gate descriptor is an interrupt gate, EFLAGS.IF is cleared to 0.
- If the gate descriptor is a trap gate, EFLAGS.IF is not modified.
4. Saves the return CS register and EIP register (RIP[31:0]) by pushing them onto the stack. The CS
value is padded with two bytes to form a doubleword.
5. If the interrupt has an associated error code, the error code is pushed onto the stack.
6. The CS register is loaded from the segment-selector field in the gate descriptor, and the EIP is
loaded from the offset field in the gate descriptor.
7. The interrupt handler begins executing with the instruction referenced by new CS:EIP.
Figure 8-9 shows the stack after control is transferred to the interrupt handler.
Figure 8-9. Stack After Interrupt to Same Privilege Level
8.7.3  Interrupt To Higher PrivilegeWhen a control transfer to an exception or interrupt handler running at a higher privilege occurs 
(numerically lower CPL value), the processor performs a stack switch using the following steps:
1. The target CPL is read by the processor from the target code-segment DPL and used as an index
into the TSS for selecting the new stack pointer (SS:ESP). For example, if the target CPL is 1, the
processor selects the SS:ESP for privilege-level 1 from the TSS.
2. Pushes the return stack pointer (old SS:ESP) onto the new stack. The SS value is padded with two
bytes to form a doubleword.
3. Pushes the EFLAGS register onto the new stack.
4. Clears the following EFLAGS bits to 0: TF, NT, RF, and VM.5. The processor handles the EFLAGS.IF bit based on the gate-descriptor type:Interrupt-Handler and
Interrupted Progr am
Stack
Return EI PReturn C SReturn EFL AGS
Error Code SS:ESP+4+8+12
513-242.epsReturn C SReturn EFL AGS
Return EI P SS:ESP+4+8With Error Code With No Error Code
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Stack
6. Saves the return-address pointer (CS:EIP) by pushing it onto the stack. The CS value is padded
with two bytes to form a doubleword.
7. If the interrupt vector number has an error code associated with it, the error code is pushed onto
the stack.
8. The CS register is loaded from the segment-selector field in the gate descriptor, and the EIP is
9. The interrupt handler begins executing with the instruction referenced by new CS:EIP.
Figure 8-10 shows the new stack after control is transferred to the interrupt handler.
Figure 8-10. Stack After Interrupt to Higher Privilege
8.7.4  Privilege ChecksBefore loading the CS register with the interrupt-handler code-segment selector (located in the gate 
descriptor), the processor performs privilege checks similar to those performed on call gates. The checks are performed when either conforming or nonconforming interrupt handlers are referenced: 
1. The processor reads the gate DPL from the interrupt-gate or trap-gate descriptor. The gate DPL is
the minimum privilege-level  (numerically-highest value) needed by a program to access the gate.
The processor compares the CPL with the gate DPL. The CPL must be numerically less-than or
equal-to  the gate DPL for this check to pass.Interrupt-Handler Stack
Return SS
Return EI PReturn C SReturn EFL AGSReturn E SP
Error Code New SS: ESP+4+8+12+16+20
513-241 .epsReturn SS
Return C SReturn EFL AGSReturn E SP
Return EI P New SS: ESP+4+8+12+16With Error Code With No Error Code
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2. The processor compares the CPL with the interrupt-handler code-segment DPL. For this check to
pass, the CPL must be numerically greater-than or equal-to  the code-segment DPL. This check
prevents control transfers to less-privileged interrupt handlers.
Unlike call gates, no RPL comparison takes place. This is because the gate descriptor is referenced in 
the IDT using the interrupt vector number rather than a selector, and no RPL field exists in the interrupt vector number.
Exception and interrupt handlers should be made reachable from software running at any privilege 
level that requires them. If the gate DPL value is too low (requiring more privilege), or the interrupt-handler code-segment DPL is too high (runs at lower privilege), the interrupt control transfer can fail the privilege checks. Setting the gate DPL=3 and interrupt-handler code-segment DPL=0 makes the exception handler or interrupt handler reachable from any privilege level.
Figure 8-11 on page 275 shows two examples of interrupt privilege checks. In Example 1, both 
privilege checks pass: 
•The interrupt-gate DPL is at the lowest privilege (3), which means that software running at any
privilege level (CPL) can access the interrupt gate. 
•The interrupt-handler code segment is at the highest-privilege level, as indicated by DPL=0. Thismeans software running at any privilege can enter the interrupt handler through the interrupt gate.
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Figure 8-11. Privilege-Check Examples for Interrupts
In Example 2, both privilege checks fail:
•The interrupt-gate DPL specifies that only software running at privilege-level 0 can access the
gate. The current program does not have a high enough privilege level to access the interrupt gate,since its CPL is set at 2.513-244.epsExample 2: Privilege Check FailsDPL=0
Gate DescriptorAccess Denied
Interrupt
HandlerCS CPL=2
≤
DPL=3
Code DescriptorInterrupt Vector
≥?Access
Denied
Access
DeniedExample 1: Privilege Check PassesDPL=3
Gate DescriptorAccess Allowed
Interrupt
≤
DPL=0
≥?Access
Allowed
Access
Allowed
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•The interrupt handler has a lower privilege (DPL=3) than the currently-running software (CPL=2).
Transitions from more-privileged software to less-privileged software are not allowed, so thisprivilege check fails as well. 
Although both privilege checks fail, only one such failure is required to deny access to the interrupt handler.
8.7.5  Returning From Interrupt Procedures
A return to an interrupted program should be performed using the IRET instruction. An IRET is a far 
return to a different code segment, with or without a change in privilege level. The actions of an IRET in both cases are described in the following sections.
IRET, Same Privilege.  Before performing the IRET, the stack pointer must point to the return EIP. If 
there was an error code pushed onto the stack as a result of the exception or interrupt, that error code should have been popped off the stack earlier by the handler. The IRET reverses the actions of the interrupt mechanism:
1. Pops the return pointer off of the stack, loading both the CS register and EIP register (RIP[31:0])
with the saved values. The return code-segment RPL is read by the processor from the CS value
stored on the stack to determine that an equal-privilege control transfer is occurring.
2. Pops the saved EFLAGS image off of the stack and into the EFLAGS register.
3. Transfers control to the return program at the target CS:EIP.
IRET, Less Privilege.  If an IRET changes privilege levels, the return program must be at a lower 
privilege than the interrupt handler. The IRET in this case causes a stack switch to occur:1. The return pointer is popped off of the stack, loading both the CS register and EIP register
(RIP[31:0]) with the saved values. The return code-segment RPL is read by the processor from
the CS value stored on the stack to determine that a lower-privilege control transfer is occurring.
2. The saved EFLAGS image is popped off of the stack and loaded into the EFLAGS register.
3. The return-program stack pointer is popped off of the stack, loading both the SS register and ESP
register (RSP[31:0]) with the saved values.
4. Control is transferred to the return program at the target CS:EIP.
8.7.6  Shadow Stack Support for Interrupts and Exceptions
The operation of the shadow stack for an interrupt control transfer depends whether or not the interrupt 
handler runs at the same privilege or at a higher privilege level than the CPL when the interrupt or exception occurred.
Interrupt Control Transfer to Same Privilege Level.  When a control transfer to a interrupt handler 
at the same privilege occurs, and the shadow stack feature is enabled for the current CPL, the processor pushes the interrupted procedure's CS and LIP (CS.base + EIP) onto the current shadow stack. 
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Interrupt Control Transfer to Higher Privilege Level.  When a control transfer to a interrupt 
handler at a higher privilege occurs, the actions taken by the processor depend on the CPL when the 
interrupt or exception occurred.
•If the CPL = 3:
- if shadow stacks are enabled in user-mode, the current SSP is saved to MSR PL3_SSP.- if shadow stacks are enabled in supervisor mode, a new SSP is loaded from MSR PLn_SSP 
(where n = the target CPL 0, 1 or 2).
- the shadow stack token located at the base of the new shadow stack is checked, and if valid, the 
token's busy bit is set to 1.
Note : the CS and LIP are not pushed onto the new shadow stack. 
•If the CPL =1 or 2, and shadow stacks are enabled in supervisor mode:- the new SSP is loaded from MSR PLn_SSP (where n = the target CPL 0 or 1).- the shadow stack token located at the base of the new shadow stack is checked, and if valid, the 
- the CS, LIP and old SSP are pushed onto the new shadow stack.
For a detailed description of shadow stack operations, see Section “Shadow Stacks” on page 671.
8.8 Virtual-8086 Mode Interrupt Control Transfers
This section describes interrupt control transfers as they relate to virtual-8086 mode. Virtual-8086 
mode is not supported by long mode. Therefore, the control-transfer mechanism described here is not applicable to long mode.
When a software interrupt occurs (not external interrupts, INT1, or INT3) while the processor is 
running in virtual-8086 mode (EFLAGS.VM=1), the control transfer that occurs depends on three system controls:
•EFLAGS.IOPL— This field controls interrupt handling based on the CPL. See Section “I/O
Privilege Level Field (IOPL) Field” on page 53 for more information on this field.
Setting IOPL 3 redirects the interrupt to the general-protection exception (#GP) handler.
•CR4.VME —This bit enables virtual-mode extensions. See Section “Virtual-8086 Mode
Extensions (VME)” on page 47 for more information on this bit.
•TSS Interrupt-Redirection Bitmap —The TSS interrupt-redirection bitmap contains 256 bits, one

for each possible INTn vector (software interrupt). When CR4.VME=1, the bitmap is used by the
processor to direct interrupts to the handler provided by the currently-running 8086 program(bitmap entry is 0), or to the protected-mode operating-system interrupt handler (bitmap entry is1). See Section “Legacy Task-State Segment” on page 371 for information on the location of this
field within the TSS.
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If IOPL<3, CR4.VME=1, and the corresponding interrupt redirection bitmap entry is 0, the processor 
uses the virtual-interrupt mechanism. See Section “Virtual Interrupts” on page 287 for more information on this mechanism.
Table 8-11 summarizes the actions of the above system controls on interrupts taken when the 
processor is running in virtual-8086 mode.
8.8.1  Protected-Mode Handler Control Transfer
Control transfers to protected-mode handlers from virtual-8086 mode differ from standard protected-
mode transfers in several ways. The processor follows these steps in making the control transfer:
1. Reads the CPL=0 stack pointer (SS:ESP) from the TSS.2. Pushes the GS, FS, DS, and ES selector registers onto the stack. Each push is padded with two
3. Clears the GS, FS, DS, and ES selector registers to 0. This places a null selector in each of the
four registers
4. Pushes the return stack pointer (old SS:ESP) onto the new stack. The SS value is padded with two
5. Pushes the EFLAGS register onto the new stack.6. Clears the following EFLAGS bits to 0: TF, NT, RF, and VM.7. Handles EFLAGS.IF based on the gate-descriptor type:
8. Pushes the return-address pointer (CS:EIP) onto the stack. The CS value is padded with two bytes
to form a doubleword.
9. If the interrupt has an associated error code, pushes the error code onto the stack.
10. Loads the segment-selector field from the gate descriptor into the CS register, and loads the offset
field from the gate descriptor into the EIP register.Table 8-11. Virtual-8086 Mode Interrupt Mechanisms
EFLAGS.IOPL CR4.VMETSS Interrupt 
Redirection 
Bitmap EntryInterrupt Mechanism
0, 1, or 20 —General-Protection Exception1 1
1 0 Virtual Interrupt
30 —Protected-Mode Handler1 1
1 0 Virtual 8086 Handler
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11. Begins execution of the interrupt handler with the instruction referenced by the new CS:EIP.
Figure 8-12 shows the new stack after control is transferred to the interrupt handler with an error code.
Figure 8-12. Stack After Virtual-8086 Mode Interrupt to Protected Mode
An IRET from privileged protected-mode software (CPL=0) to virtual-8086 mode reverses the stack-
build process. After the return pointer, EFLAGS, and return stack-pointer are restored, the processor restores the ES, DS, FS, and GS registers by popping their values off the stack.
8.8.2  Virtual-8086 Handler Control Transfer
When a control transfer to an 8086 handler occurs from virtual-8086 mode, the processor creates an 
interrupt-handler stack identical to that created when an interrupt occurs in real mode (see Figure 8-7 
on page 269). The processor performs the following actions during a control transfer:
1. Pushes the FLAGS register (EFLAGS[15:0]) onto the stack.2. Clears the EFLAGS.IF and EFLAGS.RF bits to 0.3. Saves the CS register and IP register (RIP[15:0]) by pushing them onto the stack.4. Locates the interrupt-handler pointer (CS:IP) in the 8086 IDT by scaling the interrupt vector by
four and adding the result to the virtual (linear) address 0. The value in the IDTR is not used.
An IRET from the 8086 handler back to virtual-8086 mode reverses the stack-build process.With Error Code
Return SS
Error Code New SS: ESP
(From T SS, CPL=0)+4+8+12+16+20Return E SReturn DSReturn F SReturn G S
+24+28+32+36
513-249.epsWith No Error Code
Return SS
Return EI P New SS: ESP+4+8+12+16+20Return E SReturn DSReturn F SReturn G S
+24+28+32Interrupt-Handler Stack
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8.9 Long-Mode Interrupt Control Transfers
The long-mode architecture expands the legacy interrupt-mechanism to support 64-bit operating 
systems and applications. These changes include:
•All interrupt handlers are 64-bit code and operate in 64-bit mode.
•The size of an interrupt-stack push is fixed at 64 bits (8 bytes).
•The interrupt-stack frame is aligned on a 16-byte boundary.
•The stack pointer, SS:RSP, is pushed unconditionally on interrupts, rather than conditionally based
on a change in CPL. 
•The SS selector register is loaded with a null selector as a result of an interrupt, if the CPL changes.
•The IRET instruction behavior changes, to unconditionally pop SS:RSP, allowing a null SS to bepopped.
•A new interrupt stack-switch mechanism, called the interrupt-stack table or IST, is introduced.
•When shadow stacks are enabled, a new shadow stack-switch mechanism, called the Interrupt SSPTable or ISST, is introduced.
8.9.1  Interrupt Gates and Trap Gates
Only long-mode interrupt and trap gates can be referenced in long mode (64-bit mode and 
compatibility mode). The legacy 32-bit interrupt-gate and 32-bit trap-gate types (0Eh and 0Fh, as described in Section “System Descriptors” on page 99) are redefined in long mode as 64-bit interrupt-gate and 64-bit trap-gate types. 32-bit and 16-bit interrupt-gate and trap-gate types do not exist in long mode, and software is prohibited from using task gates. If a reference is made to any gate other than a 64-bit interrupt gate or a 64-bit trap gate, a general-protection exception (#GP) occurs.
The long-mode gate types are 16 bytes (128 bits) long. They are an extension of the legacy-mode gate 
types, allowing a full 64-bit segment offset to be stored in the descriptor. See Section “Legacy Segment Descriptors” on page 88 for a detailed description of the gate-descriptor format and fields. 
8.9.2  Locating the Interrupt Handler
When an interrupt occurs in long mode, the processor multiplies the interrupt vector number by 16 and 
uses the result as an offset into the IDT. The gate descriptor referenced by the IDT offset contains a segment-selector and a 64-bit segment-offset field. The gate-descriptor segment-offset field contains the complete virtual address for the interrupt handler. The gate-descriptor segment-selector field points to the target code-segment descriptor located in either the GDT or LDT. The code-segment descriptor is only used for privilege-checking purposes and for placing the processor in 64-bit mode. The code segment-descriptor base field, limit field, and most attributes are ignored.
Figure 8-13 shows how the long-mode interrupt handler is located by the interrupt mechanism.
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Figure 8-13. Long-Mode Interrupt Control Transfer
8.9.3  Interrupt Stack Frame
In long mode, the return-program stack pointer (SS:RSP) is always pushed onto the interrupt-handler 
stack, regardless of whether or not a privilege change occurs. Although the SS register is not used in 64-bit mode, SS is pushed to allow returns into compatibility mode. Pushing SS:RSP unconditionally presents operating systems with a consistent interrupt-stack-frame size for all interrupts, except for error codes. Interrupt service-routine entry points that handle interrupts generated by non-error-code interrupts can push an error code on the stack for consistency.
In long mode, when a control transfer to an interrupt handler occurs, the processor performs the 
1. Aligns the new interrupt-stack frame by masking RSP with FFFF_FFFF_FFFF_FFF0h.*Interrupt Vector
+
513-245.epsVirtual-Address
Space
Interrupt HandlerInterrupt-Descriptor
Table
Code-Segment Offset
CS Selector DPL
Global- or Local-
Code-Segment BaseCS Limit DPLInterrupt-Descriptor-Table RegisterIDT Base Address IDT Limit16
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2. If IST field in interrupt gate is not 0, reads IST pointer into RSP. 
3. If a privilege change occurs, the target DPL is used as an index into the long-mode TSS to select a
new stack pointer (RSP). 
4. If a privilege change occurs, SS is cleared to zero indicating a null selector.5. Pushes the return stack pointer (old SS:RSP) onto the new stack. The SS value is padded with six
bytes to form a quadword.
6. Pushes the 64-bit RFLAGS register onto the stack. The upper 32 bits of the RFLAGS image on
the stack are written as zeros.

+
Space
Table
7. Clears the TF, NT, and RF bits in RFLAGS bits to 0.8. Handles the RFLAGS.IF bit according to the gate-descriptor type:
- If the gate descriptor is an interrupt gate, RFLAGS.IF is cleared to 0.
- If the gate descriptor is a trap gate, RFLAGS.IF is not modified.
9. Pushes the return CS register and RIP register onto the stack. The CS value is padded with six
10. If the interrupt vector number has an error code associated with it, pushes the error code onto the
stack. The error code is padded with four bytes to form a quadword.
11. Loads the segment-selector field from the gate descriptor into the CS register. The processor
checks that the target code-segment is a 64-bit mode code segment.
12. Loads the offset field from the gate descriptor into the target RIP. The interrupt handler begins
execution when control is transferred to the instruction referenced by the new RIP.
Figure 8-14 on page 283 shows the stack after control is transferred to the interrupt handler.
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Figure 8-14. Long-Mode Stack After Interrupt—Same Privilege
Interrupt-Stack Alignment.  In legacy mode, the interrupt-stack pointer can be aligned at any address 
boundary. Long mode, however, aligns the stack on a 16-byte boundary. This alignment is performed 
by the processor in hardware before pushing items onto the stack frame. The previous RSP is saved unconditionally on the new stack by the interrupt mechanism. A subsequent IRET instruction automatically restores the previous RSP.
Aligning the stack on a 16-byte boundary allows optimal performance for saving and restoring the 16-
byte XMM registers. The interrupt handler can save and restore the XMM registers using the faster 16-byte aligned loads and stores (MOV APS), rather than unaligned loads and stores (MOVUPS). Although the RSP alignment is always performed in long mode, it is only of consequence when the interrupted program is already running at CPL=0, and it is generally used only within the operating-system kernel. The operating system should put 16-byte aligned RSP values in the TSS for interrupts that change privilege levels.
Stack Switch.  In long mode, the stack-switch mechanism differs slightly from the legacy stack-
switch mechanism (see Section “Interrupt To Higher Privilege” on page 272). When stacks are switched during a long-mode privilege-level change resulting from an interrupt, a new SS descriptor is not loaded from the TSS. Long mode only loads an inner-level RSP from the TSS. However, the SS 
selector is loaded with a null selector, allowing nested control transfers, including interrupts, to be handled properly in 64-bit mode. The SS.RPL is set to the new CPL value. See Section “Nested IRETs 
to 64-Bit Mode Procedures” on page 286 for additional information.Return SS
Return CS
Error CodeWith Error Code
Return RIPReturn RFLAGSReturn RSP
RSP+8+16+24+32+40Return SS
Return CSWith No Error Code
RSP+8+16+24+32Interrupt-Handler Stack
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The interrupt-handler stack that results from a privilege change in long mode looks identical to a long-
mode stack when no privilege change occurs. Figure 8-15 shows the stack after the switch is performed and control is transferred to the interrupt handler.
Figure 8-15. Long-Mode Stack After Interrupt—Higher Privilege
8.9.4  Interrupt-Stack Table
In long mode, a new interrupt-stack table (IST) mechanism is introduced as an alternative to the 
modified legacy stack-switch mechanism described above. The IST mechanism provides a method for specific interrupts, such as NMI, double-fault, and machine-check, to always execute on a known-good stack. In legacy mode, interrupts can use the hardware task-switch mechanism to set up a known-good stack by accessing the interrupt service routine through a task gate located in the IDT. However, the hardware task-switch mechanism is not supported in long mode. 
When enabled, the IST mechanism unconditionally switches stacks. It can be enabled on an individual 
interrupt vector basis using a new field in the IDT gate-descriptor entry. This allows some interrupts to use the modified legacy mechanism, and others to use the IST mechanism. The IST mechanism is only available in long mode. 
The IST mechanism uses new fields in the 64-bit TSS format and the long-mode interrupt-gate and 
trap-gate descriptors:
•Figure 12 -8 on page 377 shows the format of the 64-bit TSS and the location of the seven IST
pointers. The 64-bit TSS offsets from 24h to 5Bh provide space for seven IST pointers, each of
which are 64 bits (8 bytes) long. Return SS
Return CS
New RSP
(from TSS)
SS=0
(if CPL changes)+8+16+24+32+40Return SS
Return CSWithout Error Code
New RSP
(from TSS)
SS=0
(if CPL changes)+8+16+24+32Interrupt-Handler Stack
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•The long-mode interrupt-gate and trap-gate descriptors define a 3-bit IST-index field in bits 2:0 of
byte +4. Figure 4-24 on page 102 shows the format of long-mode interrupt-gate and trap-gate
descriptors and the location of the IST-index field.
To enable the IST mechanism for a specific interrupt, system software stores a non-zero value in the interrupt gate-descriptor IST-index field. If the IST index is zero, the modified legacy stack-switching mechanism (described in the previous section) is used.
Figure 8-16 shows how the IST mechanism is used to create the interrupt-handler stack. When an 
interrupt occurs and the IST index is non-zero, the processor uses the index to select the corresponding IST pointer from the TSS. The IST pointer is loaded into the RSP to establish a new stack for the interrupt handler. The SS register is loaded with a null selector if the CPL changes and the SS.RPL is set to the new CPL value. After the stack is loaded, the processor pushes the old stack pointer, RFLAGS, the return pointer, and the error code (if applicable) onto the stack. Control is then transferred to the interrupt handler.
Figure 8-16. Long-Mode IST Mechanism
Software must make sure that an interrupt or exception handler using an IST pointer doesn't take another exception using the same IST pointer, as this will result in the first stack exception frame being overwritten. 
513-248.epsReturn SS
Return CS
Error Code64-Bit
Interrupt-Handler Stack
+8+16+24+32+40
ISTLong-Mode
Interrupt- or Trap-
Gate Descriptor64-Bit TSS
RSP0 : RSP2IST1 : IST7RSPSS=0
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Interrupt Shadow Stack Table. When the shadow stack feature is enabled in long mode 
(EFER.LMA=1), a mechanism similar to the IST is provided to switch shadow stacks. This 
mechanism, the Interrupt Shadow Stack Table (ISST) is described in Section “Shadow Stacks” on 
page 671. 
8.9.5  Returning From Interrupt Procedures
As with legacy mode, a return to an interrupted program in long mode should be performed using the 
IRET instruction. However, in long mode, the IRET semantics are different from legacy mode:
•In 64-bit mode , IRET pops the return-stack pointer unconditionally off the interrupt-stack frame
and into the SS:RSP registers. This reverses the action of the long-mode interrupt mechanism,
which saves the stack pointer whether or not a privilege change occurs. IRET also allows a nullselector to be popped off the stack and into the SS register. See Section “Nested IRETs to 64-Bit
Mode Procedures” on page 286 for additional information.
•In compatibility mode , IRET behaves as it does in legacy mode. The SS:ESP is popped off the
stack only if a control transfer to less privilege (numerically greater CPL) is performed. Otherwise,it is assumed that a stack pointer is not present on the interrupt-handler stack.
The long-mode interrupt mechanism always uses a 64-bit stack when saving values for the interrupt handler, and the interrupt handler is always entered in 64-bit mode. To work properly, an IRET used to exit the 64-bit mode interrupt-handler requires a series of eight-byte pops off the stack. This is accomplished by using a 64-bit operand-size prefix with the IRET instruction. The default stack size assumed by an IRET in 64-bit mode is 32 bits, so a 64-bit REX prefix is needed by 64-bit mode interrupt handlers.
Nested IRETs to 64-Bit Mode Procedures.  In long mode, an interrupt causes a null selector to be

Nested IRETs to 64-Bit Mode Procedures.  In long mode, an interrupt causes a null selector to be 
loaded into the SS register if the CPL changes (this is the same action taken by a far CALL in long mode). If the interrupt handler performs a far call, or is itself interrupted, the null SS selector is pushed onto the stack frame, and another null selector is loaded into the SS register. Using a null selector in this way allows the processor to properly handle returns nested within 64-bit-mode procedures and interrupt handlers. 
The null selector enables the processor to properly handle nested returns to 64-bit mode (which do not 
use the SS register), and returns to compatibility mode (which do use the SS register). Normally, an IRET that pops a null selector into the SS register causes a general-protection exception (#GP) to occur. However, in long mode, the null selector indicates the existence of nested interrupt handlers and/or privileged software in 64-bit mode. Long mode allows an IRET to pop a null selector into SS from the stack under the following conditions: 
•The target CPL 3.
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8.10 Virtual Interrupts
The term virtual interrupts  includes two classes of extensions to the interrupt-handling mechanism:
•Virtual-8086 Mode Extensions (VME) —These allow virtual interrupts and interrupt redirection in
virtual-8086 mode. VME has no effect on protected-mode programs. 
•Protected-Mode Virtual Interrupts (PVI) —These allow virtual interrupts in protected mode when
CPL=3. Interrupt redirection is not available in protected mode. PVI has no effect on virtual-8086-
mode programs. 
Because virtual-8086 mode is not supported in long mode, VME extensions are not supported in long mode. PVI extensions are, however, supported in long mode.
8.10.1  Virtual-8086 Mode Extensions
The virtual-8086-mode extensions (VME) enable performance enhancements for 8086 programs 
running as protected tasks in virtual-8086 mode. These extensions are enabled by setting CR4.VME (bit 0) to 1. The extensions enabled by CR4.VME are:
•Virtualizing control and notification of maskable external interrupts with the EFLAGS VIF (bit
19) and VIP (bit 20) bits. 
•Selective interception of software interrupts (INT n instructions) using the TSS interrupt
redirection bitmap (IRB). 
Background.  Legacy-8086 programs expect to have full access to the EFLAGS interrupt flag (IF) 
bit, allowing programs to enable and disable maskable external interrupts. When those programs run in virtual-8086 mode under a multitasking protected-mode environment, it can disrupt the operating system if programs enable or disable interrupts for their own purposes. This is particularly true if interrupts associated with one program can occur during execution of another program. For example, a program could request that an area of memory be copied to disk. System software could suspend the program before external hardware uses an interrupt to acknowledge that the block has been copied. System software could subsequently start a second program which enables interrupts. This second program could receive the external interrupt indicating that the memory block of the first program has been copied. If that were to happen, the second program would probably be unprepared to handle the interrupt properly.
Access to the IF bit must be managed by system software on a task-by-task basis to prevent corruption 
of system resources. In order to completely manage the IF bit, system software must be able to interrupt all instructions that can read or write the bit. These instructions include STI, CLI, PUSHF, POPF, INT n, and IRET. These instructions are part of an instruction class that is IOPL-sensitive . The 
processor takes a general-protection exception (#GP) whenever an IOPL-sensitive instruction is executed and the EFLAGS.IOPL field is less than the CPL. Because all virtual-8086 programs run at CPL=3, system software can interrupt all instructions that modify the IF bit by setting IOPL 3.
System software maintains a virtual image of the IF bit for each virtual-8086 program by emulating the actions of IOPL-sensitive instructions that modify the IF bit. When an external maskable-interrupt 
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occurs, system software checks the state of the IF image for the current virtual-8086 program to 
determine whether the program is masking interrupts. If the program is masking interrupts, system software saves the interrupt information until the virtual-8086 program attempts to re-enable interrupts. When the virtual-8086 program unmasks interrupts with an IOPL-sensitive instruction, system software traps the action with the #GP handler.
The performance of a processor can be significantly degraded by the overhead of trapping and 
emulating IOPL-sensitive instructions, and the overhead of maintaining images of the IF bit for each virtual-8086 program. This performance loss can be eliminated by running virtual-8086 programs with IOPL set to 3, thus allowing changes to the real IF flag from any privilege level. Unfortunately, this can leave critical system resources unprotected.
In addition to the performance problems caused by virtualizing the IF bit, software interrupts (INT n 
instructions) cannot be masked by the IF bit or virtual copies of the IF bit. The IF bit only affects 
maskable external interrupts. Software interrupts in virtual-8086 mode are normally directed to the real mode interrupt vector table (IVT), but it can be desirable to redirect certain interrupts to the protected-mode interrupt-descriptor table (IDT). 
The virtual-8086-mode extensions are designed to support both external interrupts and software 
interrupts, with mechanisms that preserve high performance without compromising protection. Virtualization of external interrupts is supported using two bits in the EFLAGS register: the virtual-interrupt flag (VIF) bit and the virtual-interrupt pending (VIP) bit. Redirection of software interrupts is supported using the interrupt-redirection bitmap (IRB) in the TSS. A separate TSS can be created for each virtual-8086 program, allowing system software to control interrupt redirection independently for each virtual-8086 program.
VIF and VIP Extensions for External Interrupts.  When VME extensions are enabled, the IF-
modifying instructions normally trapped by system software are allowed to execute. However, instead of modifying the IF bit, they modify the EFLAGS VIF bit. This leaves control over maskable interrupts to the system software. It can also be used as an indicator to system software that the virtual-8086 program is able to, or is expecting to, receive external interrupts. 
When an unmasked external interrupt occurs, the processor transfers control from the virtual-8086 
program to a protected-mode interrupt handler. If the interrupt handler determines that the interrupt is for the virtual-8086 program, it can check the state of the VIF bit in the EFLAGS value pushed on the stack for the virtual-8086 program. If the VIF bit is set (indicating the virtual-8086 program attempted to unmask interrupts), system software can allow the interrupt to be handled by the appropriate virtual-8086 interrupt handler.
If the VIF bit is clear (indicating the virtual-8086 program attempted to mask interrupts) and the 
interrupt is for the virtual-8086 program, system software can hold the interrupt pending. System software holds an interrupt pending by saving appropriate information about the interrupt, such as the interrupt vector, and setting the virtual-8086 program's VIP bit in the EFLAGS image on the stack. When the virtual-8086 program later attempts to set IF, the previously set VIP bit causes a general-protection exception (#GP) to occur. System software can then pass the saved interrupt information to the virtual-8086 interrupt handler.
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To summarize, when the VME extensions are enabled (CR4.VME=1), the VIF and VIP bits are set and 
cleared as follows: 
•VIF Bit—This bit is set and cleared by the processor in virtual-8086 mode in response to an
attempt by a virtual-8086 program to set and clear the EFLAGS.IF bit. VIF is used by systemsoftware to determine whether a maskable external interrupt should be passed on to the virtual-8086 program, emulated by system software, or held pending. VIF is also cleared during softwareinterrupts through interrupt gates, with the original VIF value preserved in the EFLAGS image onthe stack. 
•VIP Bit —System software sets and clears this bit in the EFLAGS image saved on the stack after an

interrupt. It can be set when an interrupt occurs for a virtual-8086 program that has a clear VIF bit.The processor examines the VIP bit when an attempt is made by the virtual-8086 program to setthe IF bit. If VIP is set when the program attempts to set IF, a general-protection exception (#GP)occurs before  execution of the IF-setting instruction. System software must clear VIP to avoid
repeated #GP exceptions when returning to the interrupted instruction.
The VIF and VIP bits can be used by system software to minimize the overhead associated with managing maskable external interrupts because virtual copies of the IF flag do not have to be maintained by system software. Instead, VIF and VIP are maintained during context switches along with the remaining EFLAGS bits.
Table 8-12 on page 291 shows how the behavior of instructions that modify the IF bit are affected by 
the VME extensions.
Interrupt Redirection of Software Interrupts.  In virtual-8086 mode, software interrupts (INT n 
instructions) are trapped using a #GP exception handler if the IOPL is less than 3 (the CPL for virtual-8086 mode). This allows system software to interrupt and emulate 8086-interrupt handlers. System software can set the IOPL to 3, in which case the INT n instruction is vectored through a gate descriptor 
in the protected-mode IDT. System software can use the gate to control access to the virtual-8086 mode interrupt vector table (IVT), or to redirect the interrupt to a protected-mode interrupt handler.
When VME extensions are enabled, for INT n instructions to execute normally, vectoring directly to a 
virtual-8086 interrupt handler through the virtual-8086 IVT (located at address 0 in the virtual-address 
space of the task). For security or performance reasons, however, it can be necessary to intercept INTn instructions on a vector-specific basis to allow servicing by protected-mode interrupt handlers. This is performed by using the interrupt-redirection bitmap (IRB), located in the TSS and enabled when CR4.VME=1. The IRB is available only in virtual-8086 mode.
Figure 12 -6 on page 372 shows the format of the TSS, with the interrupt redirection bitmap located 
near the top. The IRB contains 256 bits, one for each possible software-interrupt vector. The most-
significant bit of the IRB controls interrupt vector 255, and is located immediately before the IOPB base. The least-significant bit of the IRB controls interrupt vector 0. 
The bits in the IRB function as follows:
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•When set to 1, the INTn instruction behaves as if the VME extensions are not enabled. The
interrupt is directed through the IDT to a protected-mode interrupt handler if IOPL=3. If IOPL<3,the INTn causes a #GP exception.
•When cleared to 0, the INTn instruction is directed through the IVT for the virtual-8086 programto the corresponding virtual-8086 interrupt handler.
Only software interrupts can be redirected using the IRB mechanism. External interrupts are asynchronous events that occur outside the context of a virtual-8086 program. Therefore, external interrupts require system-software intervention to determine the appropriate context for the interrupt. The VME extensions described in Section “VIF and VIP Extensions for External Interrupts” on page 288 are provided to assist system software with external-interrupt intervention. 
8.10.2  Protected Mode Virtual Interrupts
The protected-mode virtual-interrupt (PVI) bit in CR4 enables support for interrupt virtualization in 
protected mode. When enabled, the processor maintains program-specific VIF and VIP bits similar to the manner defined by the virtual-8086 mode extensions (VME). However, unlike VME, only the STI and CLI instructions are affected by the PVI extension. When a program is running at CPL=3, it can use STI and CLI to set and clear its copy of the VIF flag without causing a general-protection exception. The last section of Table 8-12 on page 291 describes the behavior of instructions that modify the IF bit when PVI extensions are enabled.
The interrupt redirection bitmap (IRB) defined by the VME extensions is not supported by the PVI 
extensions.
8.10.3  Effect of Instructions that Modify EFLAGS.IF
the VME and PVI extensions. The table columns specify the following:
•Operating Mode—the processor mode in effect when the instruction is executed.
•Instruction —the IF-modifying instruction.
•IOPL—the value of the EFLAGS.IOPL field.
•VIP—the value of the EFLAGS.VIP bit.
•#GP—indicates whether the conditions in the first four columns cause a general-protection
exception (#GP) to occur.
•Effect on IF Bit —indicates the effect the conditions in the first four columns have on the
EFLAGS.IF bit and the image of EFLAGS.IF on the stack.
•Effect on VIF Bit —indicates the effect the conditions in the first four columns have on the
EFLAGS.VIF bit and the image of EFLAGS.VIF on the stack.
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Table 8-12. Effect of Instructions that Modify the IF Bit
Operating Mode Instruction IOPLVI
P#GP Effect on IF Bit Effect on VIF Bit
Real Mode
CR0.PE=0
EFLAGS.VM=0CR4.VME=0CR4.PVI=0CLI
noIF = 0
STI IF = 1
PUSHF EFLAGS.IF Stack Image = IF
POPF IF = EFLAGS.IF stack image
INTnEFLAGS.IF Stack Image = IF
IF = 0
IRET IF = EFLAGS.IF Stack Image
Protected Mode
CR0.PE=1
EFLAGS.VM=0CR4.VME=xCR4.PVI=0CLI³CPL
no IF = 0
<CPL yes —
STI³CPL no IF = 1
<CPL yes —
PUSHF x
noEFLAGS.IF Stack Image = IF
POPF³CPL IF = EFLAGS.IF Stack Image
<CPL No Change
INTn gate
xEFLAGS.IF Stack Image = IF
IF = 0
IRET
IF = EFLAGS.IF Stack Image
IRETD
Note:
Gray-shaded boxes indicate the bits are unsupported (ignored) in the specified operating mode.
“x” indicates the value of the bit is a “don’t care”.“—” indicates the instruction causes a general-protection exception (#GP).
Note:
1. If the EFLAGS.IF stack image is 0, no #GP exception occurs and the IRET instruction is executed.2. If the EFLAGS.IF stack image is 1, the IRET is not executed, and a #GP exception occurs.
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Virtual-8086 Mode
CR0.PE=1
EFLAGS.VM=1CR4.VME=0CR4.PVI=xCLI3
no IF = 0
< 3 yes —
STI3 no IF = 1
< 3 yes —
PUSHF3 no EFLAGS.IF Stack Image = IF
< 3 yes —
POPF3 no IF = EFLAGS.IF Stack Image
< 3 yes —
INTn gate3 noEFLAGS.IF Stack Image = IF
IF = 0
< 3 yes —
IRET3 no IF = EFLAGS.IF Stack Image
< 3 yes —
IRETD3 no IF = EFLAGS.IF Stack Image
< 3 yes —Table 8-12. Effect of Instructions that Modify the IF Bit (continued)
Note:
Note:
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Virtual-8086 Mode 
with VME Extensions
CR0.PE=1
EFLAGS.VM=1CR4.VME=1CR4.PVI=xCLI3
x noIF = 0 No Change
<3 No Change VIF = 0
STI3 x no IF = 1 No Change
<30 no No Change VIF = 1
1 yes —
PUSHF3
x noEFLAGS.IF Stack Image = IF Not Pushed
<3 Not Pushed EFLAGS.IF Stack Image = VIF
PUSHFD3
xno EFLAGS.IF Stack Image = IF EFLAGS.VIF Stack Image = VIF
<3 yes —
POPF3 x no IF = EFLAGS.IF Stack Image No Change
<30 no No Change VIF = EFLAGS.IF Stack Image
1 yes —
POPFD3
xno IF = EFLAGS.IF Stack Image No Change 
<3 yes —
INTn gate3
x noEFLAGS.IF Stack Image = IF
IF = 0No Change
<3 No ChangeEFLAGS.IF Stack Image = VIFVIF = 0
IRET3 x no IF = EFLAGS.IF Stack Image No Change
1no
1 No Change VIF = EFLAGS.IF Stack Image
yes2—
IRETD3
xno IF = EFLAGS.IF Stack Image VIF = EFLAGS.IF Stack Image
<3 yes —Table 8-12. Effect of Instructions that Modify the IF Bit (continued)
Note:
Note:
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Protected Mode 
with PVI Extensions
CR0.PE=1
EFLAGS.VM=0CR4.VME=xCR4.PVI=1CPL=3CLI3
1 yes —
PUSHF
x x noEFLAGS.IF Stack Image = IFNot Pushed
PUSHFD EFLAGS.VIF Stack Image = VIF
POPF
IF = EFLAGS.IF Stack ImageNo Change
POPFD VIF = 0
INTn gateEFLAGS.IF Stack Image = IF
IF = 0 (if interrupt gate)No Change
IRET

Note:
Note:
CR0.PE=1
1 yes —
PUSHF
POPF
IRET
IRETD VIF = EFLAGS.VIF Stack ImageTable 8-12. Effect of Instructions that Modify the IF Bit (continued)
Note:
Note:
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9 Machine Check Architecture
The AMD64 Machine Check Architecture (MCA) plays a vital role in the reliability, availability, and 
serviceability (RAS) of AMD processors, as well as the RAS of the computer systems in which they are embedded. MCA defines the facilities by which processor and system hardware errors are logged and reported to system software. This allows system software to serve a strategic role in recovery from and diagnosis of hardware errors.
Error checking hardware is configured and information about detected error conditions is conveyed 
via an architecturally-defined set of registers. The system programming interface of MCA is described below in Section 9.3 “Machine Check Architecture MSRs” on page 300.
9.1 Introduction
All computer systems are susceptible to errors—results that are contrary to the system design. Errors can be categorized as soft or hard. Soft errors are caused by transient interference and are not 
necessarily indicative of any damage to the computer circuitry. These external events include noise from electromagnetic radiation and the incursion of sub-atomic particles that cause bit cell storage capacitors to change state.
Hard errors are repeatable malfunctions that are generally attributable to physical damage to computer 
circuitry. Damage may be caused by external forces (for example, voltage surges) or wear processes inherent in the circuit technology. Damaged circuit elements can manifest symptoms similar to those that are caused by soft error processes. An increase in the frequency of errors attributable to one circuit element may indicate that the element has sustained damage or is wearing-out and may, in the future, cause a hard error.
9.1.1  Reliability, Availability, and Serviceability
This section describes the concepts of reliability, availability, and serviceability (RAS) and shows how 
they are interrelated.
The rate at which errors occur in a computer system is a measure of the system’s reliability . 
Availability is the percentage of time that the system is available to do useful work. Errors that prevent 
a computer system from continued operation result in down-time , that is, periods of unavailability. 
Down-time includes the amount of time required to restore the system to operation. This may include the time to diagnose a failure, determine the field replaceable unit (FRU) containing the faulty circuitry, carry out the repair action required to replace the identified FRU, and restart the system. This time directly impacts the system’s availability and is a measure of the system’s serviceability . 
The availability of a computer system can be increased without decreasing performance or significantly increasing cost through the judicious addition of data and control path redundancy in concert with dedicated error-checking hardware. Together, redundancy and error checking detect  and 
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often correct  hardware errors. When errors are corrected by hardware, system operation continues 
without any perceptible disruption or loss in performance. 
Another important technique that can prevent down-time is error containment . Error containment 
limits the propagation of an erroneous data. This enhances system availability by limiting the effects of 
errors to a subset of software or hardware resources. System software may either correct the error and resume the interrupted program or, if the error cannot be corrected, terminate software processes that cannot continue due to the error.
Error logging enhances serviceability by providing information that is used to identify the FRU that 
contains the failed circuitry. The mechanical design of the computer system can enhance serviceability (and thus availability) by making the task of physically replacing a failed FRU quicker and easier.
9.1.2  Error Detection, Logging, and Reporting
Error detection requires specific error-checking hardware that compares the actual result of some data 
transfer or transformation to the expected result. Any disparity indicates that an error has occurred. Error detection is controlled through implementation-specific means. Disabling detection is normally only appropriate when hardware is being debugged in the laboratory. 
When an error is detected, hardware autonomously acts to either correct the error or contain the 
propagation of the corrupting effects of an uncorrected error. For some error sources, hardware action can be disabled by software through the MCA interface.
As hardware acts to correct or contain a detected error, it gathers information about the error to aid in 
recovery, diagnosis, and repair. The architecture provides software control of error logging  and 
reporting . The following describes the characteristics of each:
•Logging
Logging involves saving information about the error in specific MCA registers. If the error 
reporting bank associated with the error source is enabled, logging occurs; if disabled, error information is generally discarded (there are implementation-specific exceptions). 
•Reporting
An uncorrected error may be reported to system software via a machine-check exception, if error 
reporting for the specific error source is enabled.
Reporting is the hardware-initiated action of interrupting the processor using a machine-check exception (#MC). Reporting for each specific error type can be enabled or disabled by system software though the MCA register interface. Even if reporting for an error type is disabled, logging may continue.
Disabling reporting can negatively impact both error containment and error recovery (see the next 
section) and should be avoided.
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Hardware categorizes errors into three classes. These are: 
•corrected
•uncorrected
•deferred
The following sections describe the characteristics of each of these error classes:
If an error can be corrected by hardware, no immediate action by software is required. In this case, 
information is logged, if enabled, to aid in later diagnosis and possible repair. 
If correction is not possible, the error is classified as uncorrected. The occurrence of an uncorrected 
error requires immediate action by system software to either correct the error and resume the interrupted program or, if software-based correction is not possible, to determine the extent of the impact of the uncorrected error to any executing instruction stream or the architectural state of the processor or system and take actions to contain the error condition by terminating corrupted software processes.
For errors that are not corrected, but have no immediate impact on the architectural state of the system, 
processor core, or any current thread of execution, the error may be classified by hardware as a deferred error. Information about deferred errors is logged, if enabled, but not reported via a machine-check exception. Instead hardware monitors the error and escalates the error classification to uncorrected at the point in time where the error condition is about to impact the execution of an instruction stream or cause the corruption of the processor core or system architectural state. 
This escalation results in a #MC exception, assuming that reporting for that error source is enabled. If 
software can correct the error, it may be possible to resume the affected program. If not, software can terminate the affected program rather than bringing down the entire system. This is referred to as error 
localization.
A common example of deferred error processing and localization is the conversion of globally 
uncorrected DRAM errors to process-specific consumed memory errors. In this example, uncorrected ECC-protected data that has not yet been consumed by any processor core is tagged as “poison.” Hardware reports the uncorrected data as a localized error via a #MC exception when it is about to be used (“consumed”) by an instruction execution stream.
In contrast, an error that cannot be contained and is of such severity that it has compromised the

In contrast, an error that cannot be contained and is of such severity that it has compromised the 
continued operation of a processor core requires immediate action to terminate system processing and may result in a hardware-enforced shutdown . In the shutdown state, the execution of instructions by 
that processor core is halted. See Section 8.2.9 “#DF—Double-Fault Exception (Vector 8)” on 
page 250 for a description of the shutdown processor state.
If supported, system software can chose to configure and enable hardware to generate an interrupt 
when a deferred error is first detected. Corrected errors may be counted as they are logged. If supported and enabled, exceeding a software-configured count threshold may be signalled via an interrupt. These notification mechanisms are independent of machine-check reporting. 
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Specific details on hardware error detection, logging, and reporting are implementation-dependent and 
are described in the BIOS and Kernel Developer’s Guide (BKDG) or Processor Programming 
Reference Manual applicable to your product.
9.1.3  Error Recovery
When errors cannot be corrected by hardware, error recovery  comes into play. Error recovery, as 
defined by MCA, always involves software intervention. Logged information about the uncorrected 
error condition that caused the exception allows system software to take actions to either correct the error and resume the interrupted execution stream or terminate software processes (or higher-level software constructs) that are known to be affected by the uncorrected error.
From a system perspective, all errors are either recoverable or unrecoverable. The following outlines 
the characteristics of each:
•Recoverable —Hardware has determined that the architectural state of the processor experiencing 
the uncorrected error has not been compromised. Software execution can continue if system 
software can determine the extent of the error and take actions to either:
-correct  the error and resume the interrupted stream of execution or, 
- if this is not possible, terminate  software processes that have incurred a loss of architectural 
state and continue  other software processes that are unaffected by the error.
•Unrecoverable —Hardware has determined that the architectural state of the processor 
experiencing the uncorrected error has been corrupted. Software execution cannot reliably 
continue. 
Software saves any diagnostic information that it may be able to gather and halts.
The fact that an error is recoverable does not mean that recovery software will be able to resume 
program execution. If it is unable to determine the extent of the corruption or if it determines that essential state information has been lost, it may only be able to save information about the error and halt processing.
System software has many options to recover from an uncorrected error. The following is a partial list 
of possible actions that system software might take:
•If it can be determined that the corruption caused by the uncorrected error is contained within a 
software process, software can kill the process.
•If the uncorrected error has corrupted the architectural state of a virtual machine, the VMM can rebuild the container (using only hardware resources that are known to be good) and reboot the guest operating system.
•If the uncorrected error is a part of a block of data being transferred to or from an I/O device, the data transfer can be flushed and retried or terminated with an error.
•If the uncorrected error is due to a hard link failure, software can reconfigure the network to route information around the failed link.
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•If the uncorrected error is in a cache and the cache line containing the uncorrected (known bad) 
data is in the shared state, software can invalidate the line so that it will be reloaded from memory or another cache that has the line in the owned state.
Many more error scenarios are recoverable depending on the effectiveness of hardware error containment, the logging capabilities of the system, and the sophistication of the recovery software that acts on the information conveyed through the MCA reporting structure.
If recovery software is unable to restore a valid system architectural state at some level of software 
abstraction (process, guest operating system, virtual machine, or virtual machine monitor), the uncorrected error is considered system fatal . In this situation, system software must halt the execution 
of instructions. A system reset is required to restore the system to a known-good architectural state.
9.2 Determining Machine-Check Architecture Support
Support for the machine-check architecture is implementation-dependent. System software executes the CPUID instruction to determine whether a processor implements the machine-check exception (#MC) and the global MCA MSRs. The CPUID Fn0000_0001_EDX[MCE] feature bit indicates support for the machine-check exception and the CPUID Fn0000_0001_EDX[MCA] feature bit indicates support for the base set of global machine-check MSRs.
Once system software determines that the base set of MCA MSRs is available, it determines the 
implemented number of machine-check reporting banks by reading the machine-check capabilities register (MCG_CAP), which is the first of the global MCA MSRs. 
For a processor implementation to provide an architecturally compliant MCA interface, it must 
provide support for the machine-check exception, the global machine-check MSRs, the watchdog timer (see “CPU Watchdog Timer Register” on page 303.), and at least one bank of the machine-check reporting registers.
Support for the deferred reporting and software-based containment of uncorrected data errors is 
indicated by the feature bit CPUID Fn8000_0007_EBX[SUCCOR]. See “Machine-Check Recovery” on page 306. 
Support for recoverable MCA overflow conditions is indicated by feature bit CPUID 
Fn8000_0007_EBX[McaOverflowRecov]. See the discussion of recoverable status overflow in Section 9.3.2.1 “MCA Overflow” on page 305.
Implementation-specific information concerning the machine-check mechanism can be found in the BIOS and Kernel Developer’s Guide (BKDG) or Processor Programming Reference Manual  
applicable to your product. For more information on using the CPUID instruction, see Section 3.3, “Processor Feature Identification,” on page 71.
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9.3 Machine Check Architecture MSRs
The AMD64 Machine-Check Architecture defines the set of model-specific registers (MCA MSRs) 
used to log and report hardware errors. These registers are:
•Global status and control registers:
- Machine-check global-capabilities register (MCG_CAP)- Machine-check global-status register (MCG_STATUS)- Machine-check global-control register (MCG_CTL)- Machine-check exception configuration register (MCA_INTR_CFG)
•One or more error-reporting register banks, each containing:- Machine-check control register (MCi_CTL)- Machine-check status register (MCi_STATUS)- Machine-check address register (MC i_ADDR)
- At least one machine-check miscellaneous error-information register (MCi_MISC0)Each error-reporting register bank is associated with a specific processor unit (or group of
processor units).
•CPU Watchdog Timer register (CPU_WATCHDOG_TIMER)
The error-reporting registers retain their values through a warm reset. (A warm reset occurs while power to the processor is stable. This in contrast to a cold reset, which occurs during the application of power after a period of power loss.) This preservation of error information allows the platform firmware or other system-boot software to recover and report information associated with the error when the processor is forced into a shutdown state.
The RDMSR and WRMSR instructions are used to read and write the machine-check MSRs. See 
“Machine-Check MSRs” on page 722 for a listing of the machine-check MSR numbers and their reset values. The following sections describe each MCA MSR and its function.
9.3.1  Global Status and Control Registers
The global status and control MSRs are the MCG_CAP, MCG_STATUS, MCG_CTL and 
MCA_INTR_CFG registers. 
9.3.1.1  Machine-Check Global-Capabilities Register
Figure 9-1 shows the format of the machine-check global-capabilities register (MCG_CAP). 
MCG_CAP is a read-only register that specifies the machine-check mechanism capabilities supported by the processor implementation. 
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Figure 9-1. MCG_CAP Register
The fields within the MCG_CAP register are:
•BANK_CNT (MCi Bank Count) —Bits 7:0. This field specifies how many error-reporting register 
banks are supported by the processor implementation.
•CTLP(MCG_CTL Register Present)—Bit 8. This bit specifies whether or not the Machine-Check

•CTLP(MCG_CTL Register Present)—Bit 8. This bit specifies whether or not the Machine-Check 
Global-Control (MCG_CTL) Register is supported by the processor. When the bit is set to 1, the register is supported. When the bit is cleared to 0, the register is unsupported. The MCG_CTL register is described on page 302.
All remaining bits in the MCG_CAP register are reserved. Writing values to the MCG_CAP register produces undefined results.
9.3.1.2  Machine-Check Global-Status Register
Figure 9-2 shows the format of the machine-check global-status register (MCG_STATUS). MCG_STATUS provides basic information about the processor state after the occurrence of a machine-check error.63 32
Reserved
31 9 8 7 0
Reserved
CTLPBANK_CNT
63:9 Reserved R
8 CTLP MCG_CTL register present R
7:0 BANK_CNT Number of reporting banks R
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Figure 9-2. MCG_STATUS Register
The fields within the MCG_STATUS register are:
•Restart-IP Valid (RIPV)—Bit 0. When this bit is set to 1, the interrupted program can be reliably 
restarted at the instruction addressed by the instruction pointer pushed onto the stack by the machine-check error mechanism. If this bit is cleared to 0, the interrupted program cannot be reliably restarted.
•Error-IP Valid (EIPV)—Bit 1. When this bit is set to 1, the process thread that was interrupted by the #MC is responsible for the machine-check error, which occurred at the privilege level indicated by the CS selector that was pushed on the stack by the exception. If this bit is cleared to 0, it is possible that the interrupted thread is not responsible for the machine-check error.
•Machine Check In-Progress (MCIP) —Bit 2. When this bit is set to 1, it indicates that a machine-
check error is in progress. If another machine-check error occurs while this bit is set, the processor enters the shutdown state. The processor sets this bit whenever a machine check exception is generated. Software is responsible for clearing it after the machine check exception is handled.
All remaining bits in the MCG_STATUS register are reserved.
9.3.1.3  Machine-Check Global-Control Register
Figure 9-3 shows the format of the machine-check global-control register (MCG_CTL). MCG_CTL is used by software to enable or disable the logging and reporting of machine-check errors from the implemented error-reporting banks. Depending on the implementation, detected errors from some error sources associated with a reporting bank that is disabled are still logged. Setting all bits to 1 in this register enables all implemented error-reporting register banks to log errors.63 32
Reserved
31 3 2 1 0
Reserved
MCIP
EIPV
RIPV
63:3 Reserved RAZ
2 MCIP Machine Check In-Progress R/W
1 EIPV Error IP Valid Flag R/W
0 RIPV Restart IP Valid Flag R/W
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Figure 9-3. MCG_CTL Register
9.3.1.4  Machine-Check Exception Configuration Register
In addition to the standard Machine Check exception (#MC) signaling, certain machine check events 
can raise an interrupt via the APIC LVT mechanism. Configuration of these interrupts are provided, in part, in register MCA_INTR_CFG located at MSR C000_0410, see Figure 9-4. See Section 16.4 
“Local Interrupts” on page 627 for details on configuring LVT entries.
Figure 9-4. MCA_INTR_CFG Register
9.3.1.5  CPU Watchdog Timer Register
The CPU watchdog timer is used to generate a machine check condition when an instruction does not complete within a time period specified by the CPU Watchdog Timer register. The timer restarts the count each time an instruction completes, when enabled by the CPU Watchdog Timer Enable bit. The 
time period is determined by the Count Select  and Time Base  fields. The timer does not count during 
halt or stop-grant. 
The format of the CPU watchdog timer is shown in Figure 9-5.63 2 1 0EN63… Error-Reporting Register-Bank Enable Bits …
EN2
EN1EN0
63 32
Reserved
31 16 15 12 11 8 7 4 3 0
ReservedThreshold
LvtOffsetReservedDeferredLvt
OffsetReserved
63:16 Reserved RAZ
15:12 ThresholdLvtOffsetFor error thresholding interrupts, specifies the 
address of the LVT entry in the APIC registers as follows: LVT address = (ThresholdLvtOffset < < 4) + 500h (see APIC[530:500]).R/W
11:8 Reserved RAZ
7:4 DeferredLvtOffsetFor deferred error interrupts, specifies the address of the LVT entry in the APIC registers as follows: LVT address = (DeferredLvtOffset < < 4) + 500h (see APIC[530:500]).R/W
3:0 Reserved RAZ
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Figure 9-5. CPU Watchdog Timer Register Format
CPU Watchdog Timer Enable (EN) -  Bit 0. This bit specifies whether the CPU Watchdog Timer is 
enabled. When the bit is set to 1, the timer increments and generates a machine check when the timer 
expires. When cleared to 0, the timer does not increment and no machine check is generated.
CPU Watchdog Timer  Time Base (TB)  - Bits 2:1. Specifies the time base for the time-out period 
indicated in the Count Select field. The allowable time base values are provided in Table 9-1.
.
CPU Watchdog Timer  Count Select (CS)  - Bits 6:3. Specifies the time period required for the CPU 
Watchdog Timer to expire. The time period is this value times the time base specified in the Time Base  
field. The allowable values are shown in Table 9-2.
 63 32
Reserved
31 7 6 3 2 1 0
Model dependent; see BKDG or PPR for desired processor. CS TB EN
63:7 Reserved SBZ
6:3 CS CPU Watchdog Timer Count Select R/W
2:1 TB CPU Watchdog Timer Time Base R/W
0 EN CPU Watchdog Timer Enable R/W
Table 9-1. CPU Watchdog Timer Time Base
TB[1:0] Time Base
00b 1 millisecond
01b 1 microsecond
10b Reserved
11b Reserved
Table 9-2. CPU Watchdog Timer Count Select
CS[3:0] Value
0000b 4095
0001b 2047
0010b 1023
0011b 511
0100b 255
0101b 127
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9.3.2  Error-Reporting Register Banks
Each error-reporting register bank contains the following registers:
•Machine-check control register (MCi_CTL).
•Machine-check status register (MCi_STATUS).
•Machine-check address register (MC i_ADDR).
•Machine-check miscellaneous error-information register 0 (MC i_MISC0).
The i in each register name corresponds to the number of a supported register bank. Each error-
reporting register bank is normally associated with a specific execution unit. The number of error-
reporting register banks is implementation-specific. For more information, see the BIOS and Kernel 
Developer’s Guide (BKDG) or Processor Programming Reference Manual  applicable to your product. 
Software reads the MCG_CAP register to determine the number of supported register banks. The first error-reporting register (MC0_CTL) always starts with MSR address 400h, followed by MC0_STATUS (401h), MC0_ADDR (402h), and MC0_MISC0 (403h). The addresses of any additional error-reporting MSRs are assigned sequentially starting at 404h through the remaining supported register banks.
9.3.2.1  MCA Overflow
If an error occurs within an error reporting bank while the status register for that bank contains valid data (MC i_STATUS[V AL] = 1), an MCA overflow condition results. In this situation, information 
about the new error will either be discarded or will replace the information about the prior error. 
Hardware sets the MC i_STATUS[OVER] bit to indicate this condition has occurred and follows a set 
of rules to determine whether to overwrite the previously logged error information or discard the new 
error information. These rules are shown in Table 9-3 below. 0110b 63
0111b 31
1000b 8191
1001b 16383
1010b–1111b ReservedTable 9-2. CPU Watchdog Timer Count Select (continued)
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If the V AL bit is not set, hardware writes the appropriate logging registers based on the type of error 
(writing the MCi_STATUS register last) and then sets the V AL bit to indicate to software that the information currently contained in the MCi_STATUS register is valid. Software clears the V AL bit after reading the contents of this register (after reading and saving valid information stored in any of the other logging registers) to indicate to hardware that it has saved the information, making the registers available to log the next error.
If survivable MCA overflow is supported by the implementation (as indicated by CPUID 
Fn8000_0007_EBX[McaOverflowRecov] = 1), the state of the MC i_STATUS[PCC] bit indicates

0111b 31
1000b 8191
Fn8000_0007_EBX[McaOverflowRecov] = 1), the state of the MC i_STATUS[PCC] bit indicates 
whether system execution can continue. If a particular processor does not support survivable MCA overflow and overflow occurs, software must halt instruction execution on that processor core regardless of the state of the PCC bit because critical information may have been lost as a result of the overflow. See the description of the Machine-Check Status registers below for more information on the PCC bit.
9.3.2.2  Machine-Check Recovery
Machine Check Recovery is a feature allowing recovery of the system when the hardware cannot correct an error. Machine Check Recovery is supported when CPUID Fn8000_0007_EBX[SUCCOR]=1.
When Machine Check Recovery is supported and an uncorrected error has been detected that the 
hardware can contain to the task or process to which the machine check has been delivered, it logs a context-synchronous uncorrectable error (MCi_STATUS[UC]=1, MCi_STATUS[PCC]=0). The rest of the system is unaffected and may continue running if supervisory software can terminate only the affected process context.
9.3.2.3  Machine-Check Control Registers
The machine-check control registers (MC i_CTL), as shown in Figure 9-6, contain an enable bit for 
each error source within an error-reporting register bank. Setting an enable bit to 1 enables error reporting for the specific feature controlled by the bit, and clearing the bit to 0 disables error reporting Table 9-3. Error Logging Priorities
Previous Error Type
Corrected Deferred Uncorrected
Current 
Error 
TypeCorrected Discard Current Discard Current Discard Current
Deferred Overwrite Previous Discard Current Discard Current
Uncorrected Overwrite Previous Overwrite Previous Discard Current
Note(s):
1. Logging a deferred error has priority over the retention of information concerning a prior corrected error.
2. Logging an uncorrected error has priority over the retention of information concerning either a prior deferred
or corrected error.
3. Valid Information concerning an uncorrected error is not overwritten by any subsequent errors.
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for the feature. It is recommended that the value FFFF_FFFF_FFFF_FFFFh be programmed into each 
MCi_CTL register.
Disabling the reporting of errors from error sources that are capable of detecting uncorrected errors can compromise future error recovery and is not recommended. Other implementation-specific values are documented in the product’s BIOS and Kernel Developer’s Guide (BKDG) or Processor 
Programming Reference Manual .
Figure 9-6. MC i_CTL Register
9.3.2.4  Machine-Check Status Registers
Each error-reporting register bank includes a machine-check status register (MC i_STATUS) that the 
processor uses to log error information. Hardware writes the status register bits when an error is detected, and sets the V AL bit of the register to 1, indicating that the status information is valid. Error reporting for the error source associated with the detected error does not  need to be enabled in the 
MCi_CTL Register for the processor to write the status register. Error reporting must be enabled for 
the error to be reported via a #MC exception. Software is responsible for clearing the status register after the exception has been handled. Attempting to write a value other than 0 to an MC i_STATUS 
register in an implemented MCA bank may raise a general-protection (#GP) exception. 
Figure 9-7 on page 308 shows the format of the MC i_STATUS register. 63 2 1 0EN63… Error-Reporting Register-Bank Enable Bits …
EN2
EN1EN0
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Figure 9-7. MC i_STATUS Register
The fields within the MC i_STATUS register are:
•MCA Error Code —Bits 15:0. This field encodes information about the error, including:
- The type of transaction that caused the error.
- The memory-hierarchy level involved in the error.- The type of request that caused the error.- Other information concerning the transaction type.See the BIOS and Kernel Developer’s Guide (BKDG) or Processor Programming Reference
Manual  applicable to your product for information on the format and encoding of the MCA error
code.
•Model-Specific Extended Error Code—Bits 31:16. This field encodes model-specific information 
about the error. For further information, see the documentation for particular implementations of the architecture.63 62 61 60 59 58 57 56 55 54 53 52 45 44 43 42 32V AL
OVER
UC
EN
MISCV
ADDRV
PCCImplementation-
specific information
TCCImplementation-
SYNDVImplementation-
Deferred
PoisonImplementation-specific 
31 16 15 0
Model-Specific Extended Error Code MCA Error Code
63 V AL Valid R/W*
62 OVER Status Register Overflow R/W*
61 UC Uncorrected Error R/W*
60 EN Error Condition Enabled R/W*
59 MISCV Miscellaneous-Error Register Valid R/W*
58 ADDRV Error-Address Register Valid R/W*
57 PCC Processor-Context Corrupt R/W*
56 Implementation-specific information R/W*
55 TCC Task-Context Corrupt R/W*
54 Implementation-specific information R/W*
53 SYNDV Syndrome Register Valid R/W*
52:45 Implementation-specific information R/W*
44 Deferred Deferred error R/W*
43 Poison Poisoned data consumed R/W*
42:32 Implementation-specific information R/W*
31:16 Model-Specific Extended Error Code R/W*
15:0 MCA Error Code R/W*
* System software can only clear this bit to 0.
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•Implementation-specific Information—Bits 56, 54:45, 42:32. These bit ranges hold model-specific 
error information. Software should not rely on the field definitions in these ranges being consistent between processor implementations. For details see the BIOS and Kernel Developer’s Guide  or 
Processor Programming Reference Manual  for desired implementations of the architecture. 
•Poison —Bit 43. When set to 1, this bit indicates that the uncorrected error condition being 
reported is due to the attempted use of data that was previous detected as in error (and could not be corrected) and marked as known-bad.
•Deferred —Bit 44. When set to 1, this bit indicates that hardware has determined that the error 
condition being logged has not affected the execution of any instruction stream and that action by system software to prevent or correct an error is not required. No machine-check exception is signaled. Hardware will monitor the error and log an uncorrected error when the execution of any thread of execution is impacted.
•SYNDV —Bit 53. When set to 1, this bit indicates that the contents of the corresponding syndrome 
register (MCA_SYND) are valid. When this bit is cleared, the contents of MCA_SYND are not valid.
•TCC —Bit 55. When set to 1, this bit indicates that the hardware context of the process thread to 
which the error was reported may have been corrupted. Continued operation of the thread may have unpredictable results. When this bit is cleared, the hardware context of the process thread to which the error was reported is not corrupted and recovery of the process thread is possible. This bit is only meaningful when MCA_STATUS[PCC]=0.
•PCC —Bit 57. When set to 1, this bit indicates that the processor state is likely to be corrupt due to 
an uncorrected error. In this case, it is possible that software cannot reliably continue execution. When this bit is cleared, the processor state is not corrupted and recovery is still possible. If the PCC bit is set in any error bank, the processor will clear RIPV and EIPV in the MCG_STATUS register.
•ADDRV —Bit 58. When set to 1, this bit indicates that the contents of the corresponding error-
reporting address register (MCi_ADDR) are valid. When this bit is cleared, the contents of MCi_ADDR are not valid.
•MISCV —Bit 59. When set to 1, this bit indicates that additional information about the error is 
saved in the corresponding error-reporting miscellaneous register (MC i_MISC0). When cleared, 
this bit indicates that the contents of the MCi_MISC0 register are not valid.
•EN—Bit 60. When set to 1, this bit indicates that the error condition is enabled in the corresponding error-reporting control register (MC i_CTL). Errors disabled by MC i_CTL do not 
cause a machine-check exception.
•UC—Bit 61. When set to 1, this bit indicates that the logged error status is for an uncorrected error. 
When cleared, the error class is determined by looking at the Deferred bit; the error is a Corrected error if the Deferred bit is clear or a Deferred error if the Deferred bit is set. (See Section 9.1.2, 
“Error Detection, Logging, and Reporting,” on page 296, for more detail on these error classes.)
•OVER —Bit 62. This bit is set to 1 by the processor if the V AL bit is already set to 1 as the 
processor attempts to write error information into MC i_STATUS. In this situation, the machine-
check mechanism handles the contents of MCi_STATUS as follows:

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- For processor implementations that log errors for disabled reporting banks, status for an 
enabled error replaces status for a disabled error.
- Status for a deferred error replaces status for a corrected error.
- Status for an uncorrected error replaces status for a corrected or deferred error.- Status for an enabled uncorrected error is never replaced.See Section 9.3.2.1 “MCA Overflow” on page 305 for more information on this field.
•VAL—Bit 63. This bit is set to 1 by the processor if the contents of MC i_STATUS are valid. 
Software should clear the V AL bit after reading the MC i_STATUS register, otherwise a subsequent 
machine-check error sets the OVER bit as described above.
When a machine-check error occurs, the processor writes an error code into the appropriate 
MCi_STATUS register MCA error-code field. The MC i_STATUS[V AL] bit is set to 1, indicating that 
the MC i_STATUS register contents are valid.
MCA error-codes are used to report errors in the memory hierarchy, the system bus, and the system-interconnection logic. Error-codes are divided into subfields that are used to describe the cause of an error. The information is implementation-specific. For further information, see the BIOS and Kernel 
Developer’s Guide (BKDG) or Processor Programming Reference Manual  applicable to your product.
9.3.2.5  Machine-Check Address Registers
Each error-reporting register bank includes a machine-check address register (MC i_ADDR) that the 
processor uses to report the address or location associated with the logged error. The address field can hold a virtual (linear) address, a physical address, or a value indicating an internal physical location, depending on the type of error. For further information, see the documentation for particular implementations of the architecture. The contents of this register are valid only if the ADDRV bit in the corresponding MC i_STATUS register is set to 1.
9.3.2.6  Machine-Check Miscellaneous-Error Information Register 0 (MCi_MISC0)
Each error-reporting register bank includes the Machine-Check Miscellaneous 0 register that the processor uses to report additional error information.
In some implementations, the MCi_MISC0 register is used for error thresholding. Thresholding is a 
mechanism provided by hardware to:
•count detected errors, and
•(optionally) generate an APIC-based interrupt when a programmed number of errors has been 
counted.
Processor hardware counts detected errors and ensures that multiple error sources do not share the same thresholding register. Software can use corrected error counts to help predict which components might soon fail (begin generating uncorrectable errors) and schedule their replacement. 
Threshold counters increment for error sources that are enabled for logging. 
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9.3.2.7  Additional Machine-Check Miscellaneous-Error Information Registers (MC i_MISC j)
The MC i_MISC0[BLKP] field is used to point to any additional MC i_MISC j registers, where j > 0. If 
this field is zero, no additional MC i_MISC registers are implemented. If this field is one, and CPUID 
Fn8000_0007_EBX[ScalableMca]=1, refer to Section 9.3.3, “Machine-Check Architecture Extension 
Registers,” on page 313 for addresses of additional MC i_MISC j registers. 
If the MCi_MISC0[BLKP] field is non-zero and CPUID Fn8000_0007_EBX[ScalableMca]=0, up to 8 additional MCi_MISC j registers can be implemented for the error-reporting bank i (for a total of 9). 
These registers are allocated in contiguous blocks of 8, with MC i_MISC1 addressed by:
             MC i_MISC1 address = C000_0400h + (MC i_MISC0[BLKP] << 3) 
This is illustrated in Figure 9-8 below.
Figure 9-8. MC i_MISC1 Addressing
The format of implemented MC i_MISC j registers depends upon their use and use can vary from one 
implementation to another. Figure 9-9 below illustrates the format of a miscellaneous error information register when used as an error thresholding register. 
All miscellaneous error information registers will contain the V AL field in bit position 63. 
MCi_MISC0 must contain the BLKP field in bits 31:24. MCi_CTL
MCi_ADDR
C000_0400h + (MCi_MISC0[BLKP] << 3)MCi_MISC1
MCi_MISC2
MCi_MISC3
. . .MCi_MISC0
MCi_MISC8
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Figure 9-9. Miscellaneous Information Register (Thresholding Register Format)
The fields within the MC i_MISC j register are:
•Valid (VAL)—Bit 63. When set to 1, indicates that the counter present (CNTP) and block pointer 
(BLKP) fields in this register are valid.
•Counter Present (CNTP)—Bit 62. When set to 1, indicates the presence of a threshold counter.
•Locked (LKD) —Bit 61. When set to 1, indicates that the threshold counter is not available for OS 
use. If this is the case, writes to bits 60:0 of this register are ignored and do not generate a fault. Software must check the Locked bit before writing into the thresholding register.
This field is write-enabled by MSR C001_0015h Hardware Configuration Register 
[MCSTATUSWrEn].
•IntP (Thresholding Interrupt Supported) —Bit 60. When set, this bit indicates that the reporting of 
threshold overflow via interrupt is supported. Interrupt type is determined by the setting of the INTT field.
•LVT Offset (LVTOFF) —Bits 55:52. This field specifies the address of the APIC LVT entry to 
deliver the threshold counter interrupt. Software must initialize the APIC LVT entry before enabling the threshold counter to generate the APIC interrupt; otherwise, undefined behavior may result. This field is aliased to MCA_INTR_CFG[ThresholdLvtOffest].63 62 61 60 59 56 55 52 51 50 49 48 47 32V AL
CNTP
LKD
IntPReserved LVTOFF
CNTEINTT
OFERRCT
31 24 23 0
BLKP Reserved
Bits Mnemonic Description Access type Reset
63 V AL Valid R 1b
62 CNTP Counter Present R 1b
61 LKD Locked R/W 0b
60 IntP Thresholding Interrupt Supported RImplementation 
Dependent
59:56 Reserved
55:52 LVTOFF LVT Offset R/W 0000b
51 CNTE Counter Enable R/W 0b
50:49 INTT Interrupt Type R/W 00b
48 OF Overflow R/W Undefined
47:32 ERRCT Error Counter R/W Undefined
31:24 BLKP Block pointer for additional MISC registers R Undefined
23:0 Reserved
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•Counter Enable (CNTE)—Bit 51. When set to 1, counting of implementation-dependent errors is 
enabled; otherwise, counting is disabled.
•Interrupt Type (INTT) —Bits 50:49. The value of this field specifies the type of interrupt signaled 
when the value of the overflow bit changes from 0 to 1. 
- 00b = No interrupt- 01b = APIC-based interrupt- 10b = Reserved - 11b = Reserved 
•Overflow (OF)—Bit 48. The value of this field is maintained through a warm reset. This bit is set 
by hardware when the error counter increments to its maximum implementation-supported value (from FFFEh to FFFFh for the maximum implementation-supported value). This is defined as the threshold level. When the overflow bit is set, the interrupt selected by the interrupt type field is generated. Software must reset this bit to zero in the interrupt handler routine when they update the error counter.
•Error Counter (ERRCT) —Bits 47:32. This field is maintained through a warm reset. The size of 
the threshold counter is implementation-dependent. Implementations with less than 16 bits fill the most significant unimplemented bits with zeros. 
Software enumerates the counter bits to discover the size of the counter and the threshold level 
(when counter increments to the maximum count implemented). Software sets the starting error count as follows:
Starting error count  = threshold level  – desired software error count to cause overflow
The error counter is incremented by hardware when errors for the associated error counter are 
logged. When this counter overflows, it stays at the maximum error count (with no rollover). MCA_MISCx[ErrCt] will not increment on errors that set MCA_STATUS[Poison].
•Block pointer for additional MISC registers (BLKP) —Bits 31:24. This field is only valid when 
valid (V AL) bit is set. When non-zero, this field is used to indicate the presence of additional MCi_MISC registers.
Other formats for miscellaneous information registers are implementation-dependent, see the BIOS 
and Kernel Developer’s Guide (BKDG) or Processor Programming Reference Manual  applicable to 
your product for more details.
9.3.3  Machine-Check Architecture Extension Registers
This section describes the Machine Check Architecture Extension (MCAX). MCAX is available on a 
processor when CPUID Fn8000_0007_EBX[ScalableMca] returns 1.
A processor that supports MCAX supports up to 64 MCA banks per thread, with 16 MCAX registers 
per bank, at MSRs C000_2[3FF:000]. MSRs C000_2[FFF:400] are reserved for future use.
Software can identify an MCA bank as MCAX-capable by checking for MCA_CONFIG[Mcax]=1.

Software can identify an MCA bank as MCAX-capable by checking for MCA_CONFIG[Mcax]=1. 
An MCAX bank contains the following MCAX registers: MCA_CTL, MCA_STATUS, 
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MCA_ADDR, MCA_MISC0, MCA_CONFIG, MCA_IPID, MCA_SYND, MCA_DESTAT, 
MCA_MISC[4:1], and MCA_SYND[2:1]. See Figure 9-10 for address mapping of registers in a MCAX bank.
MCAX bank registers MCA_CTL, MCA_STATUS, MCA_ADDR, and MCA_MISC0 are aliased to 
MCA bank registers MCi_CTL, MCi_STATUS, MCi_ADDR, and MCi_MISC0 in MCA banks 0 to 31. The format of MCA_CTL, MCA_STATUS, MCA_ADDR, and MCA_MISC0 is the same as the format of the corresponding MCA bank register.
Figure 9-10. Address Mapping of Registers in MCAX Bank
9.3.3.1  MCA Configuration Register
The MCA_CONFIG register holds configuration information for the MCA bank. MCA 
bank 
number 
(decimal)MCAX Bank registers 
(MSR C000_2xxx)MCAX Bank registers (MSR C000_2xxx)
MCA_
CTLMCA_
STAT
USMCA_
ADDRMCA_
MISC
0MCA
_CON
FIGMCA
_IPIDMCA
_SYN
DReser
vedMCA
_DES
TATMCA_
DEAD
DRMCA_
MISC 
[1:4]MCA_
SYND 
[1:2]
0 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h00Ah:0
0Dh00Eh:0
0Fh
n 000h 
+ 
n*10h001h
+ 
n*10h002h
+ 
n*10h003h
+ 
n*10h004h
+ 
n*10h005h
+ 
n*10h006h
+ 
n*10h007h
+ 
n*10h008h
+ 
n*10h009h
+ 
n*10h(00Ah:
00Dh) 
+ 
n*10h(00Eh:
00Fh) 
+ 
n*10h
63 41 40 39 38 37 36 35 34 33 32
Reserved
IntEn
Reserved
DeferredIntType
Reserved
Log DeferredEn
Reserved
MCAXEN
31 9 8 7 6 5 4 3 2 1 0
Reserved
FruTextInMCA
LsbInStatSupported
DeStatErrCodeSupported
FatalMaskSupported
DeferredIntTypeSupported
Reserved
DeferredLoggingSupported
Reserved
MCAX
63:41 Reserved
40 IntEn Interrupt Enable R/W
39 Reserved
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IntEn —Bits 40. When this bit is set to 0, an interrupt will not occur for corrected errors. When this bit 
is set to 1 and IntPresent=1, this bank will generate an interrupt on a corrected error to the interrupt 
vector configured in MCA_INTR_CFG[ThresholdLvtOffset].
DeferredIntType —Bits 38:37. When MCA_CONFIG[McaxEn]=1, specifies the type of interrupt to 
generate on a deferred error. 
LogDeferredEn —Bit 34. Enable logging of deferred errors in MCA_STATUS. 0=Log deferred errors 
only in MCA_DESTAT and MCA_DEADDR. 1=Log deferred errors in MCA_STATUS and 
MCA_ADDR in addition to MCA_DESTAT and MCA_DEADDR. This bit does not affect logging of deferred errors in MCA_SYND or MCA_MISCx.
McaxEn
—Bit 32. Enable MCAX feature set. 1=System software acknowledges support for the MCAX 
feature set. 0=System software has not acknowledged support for the MCAX feature set; all 
uncorrected errors and fatal errors cause a system fatal event.
FruTextInMca —Bit 9. 1=MCA_SYND1 and MCA_SYND2 contain an ASCII-formatted Field 
Replaceable Unit (FRU) identifier for the error logged in MCA_STATUS or MCA_DESTAT. 
0=MCA_SYND1 and MCA_SYND2 contain implementation-specific information.
LsbInStatSupported —Bit 8. 1=MCA_STATUS[29:24] and MCA_DESTAT[29:24] contain the least 
significant valid bit of the address logged in MCA_ADDR and MCA_DEADDR.DeStatErrCodeSupported
—Bit 7. 1=MCA_DESTAT contains an MCA Error Code and a Model-
specific Extended Error Code for the error logged in MCA_DESTAT.38:37 DeferredIntType Deferred Error Interrupt Type R/W
36:35 Reserved
34 LogDeferredEn Deferred Error Logging Enable R/W
33 Reserved
32 McaxEn MCAX Enable R/W
31:10 Reserved
9 FruTextInMCA MCA FruText Supported R/W
8 LsbInStatSupported Address LSB in MCA_STATUS Supported R
7 DeStatErrCodeSupported Deferred Error Status Error Code Supported R
6 FatalMaskSupported System fatal error event supported. R
5 DeferredIntTypeSupported Deferred Interrupt Type Supported R
4:3 Reserved
2 DeferredLoggingSupported Deferred Error Logging Supported R
1 Reserved
0 MCAX MCAX Capable R
00b No interrupt
01b APIC based interrupt 10b SMI11b ReservedBits Mnemonic Description Access Type
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DeferredIntTypeSupported —Bit 5. 1=MCA_CONFIG[DeferredIntType] controls the type of interrupt 
generated on a deferred error. Deferred errors are supported in this bank only if 
MCA_CONFIG[DeferredLoggingSupported]=1.
DeferredLoggingSupported —Bit 2. 1= MCA_CONFIG[LogDeferredEn] in this bank controls the 
logging behavior for deferred errors. 0= MCA_CONFIG[LogDeferredEn] is not supported.MCAX
—Bit 0. MCAX: Set by hardware. This MCA bank provides Machine Check Architecture 
Extensions.
9.3.3.2  MCA IP Identification
This register holds information which identifies the specific bank type: the McaType value, HWID, 
and the InstanceID. By providing those values as part of the MCA, the bank type information is available to the machine check handler for parsing and for diagnosis.
Figure 9-11. MCA_IPID Register 
McaType
—Bits 63:48. MCA bank type. This field is used to identify the MCA bank type in 
conjunction with MCA_IPID[Hwid]. For more information, see the Processor Programming Reference Manual applicable to your product.
InstanceIdHi
—Bits 47:44. The high bits of the Instance identification for the MCA bank. This field is 
used to identify the MCA bank instance in conjunction with MCA_IPID[InstanceId]. For more 
information, see the Processor Programming Reference Manual applicable to your product.
Hwid —Bits 43:32. MCA bank hardware identification. For more information, see the Processor 
Programming Reference Manual applicable to your product.InstanceId
—Bits 31:0. The Instance identification for the MCA bank. This field is used to identify the 
MCA bank instance.63 48 47 44 43 32
MCA Type InstanceldHi HWID 
31 0
Instanceld
63:48 McaType MCA bank type. R/W
47:44 InstanceIdHi The high bits of the Instance ID. R/W
43:32 Hwid Hardware ID value. R/W
31:0 InstanceID The low bits of the Instance ID. R/W
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9.3.3.3  MCA Syndrome Register
The MCA_SYND register stores a syndrome associated with the error logged in MCA_STATUS or 
MCA_DESTAT. The “syndrome” may include syndrome values associated with an error correcting code or other information about the error. The contents of this register are valid if MCA_STATUS[SYNDV] bit is set to 1 or MCA_DESTAT[SYNDV] bit is set to 1.
The format and contents of this register are implementation dependent. For more information, see the 
Processor Programming Reference Manual applicable to your product.
9.3.3.4  MCA Deferred Error Status Register
This register holds status information for deferred errors. This register ensures that software will see a deferred error, even when a later error of higher severity occurs. If the error being logged is a deferred error, then the error will be logged to MCA_DESTAT. See Section 9.3.2.4, “Machine-Check Status Registers,” on page 307 for more detailed descriptions of the register fields.
When the deferred error has been processed by the deferred error handler, MCA_DESTAT should be 
cleared. If MCA_STATUS also contains a deferred error, MCA_STATUS should be cleared.
Figure 9-12. MCA_DESTAT Register 63 62 61 59 58 57 54 53 52 45 44 43  32Valid
OverflowModel 
Dependent
AddrVModel 
Dependent
SyndVModel Dependent
DeferredModel Dependent
31  16 15 0
Model-specific Extended Error Code MCA Error Code
63 Valid  A valid error is contained in this register. R/W
62 Overflow One or more deferred errors was not logged. R/W
61:59 Model Dependent.
58 AddrV An address is contained in MCA_DEADDR. R/W
57:54  Model Dependent.
53 SyndV Syndrome valid. MCA_SYND contains error syn -
drome information associated with this deferred 
error.R/W
52:45 Model Dependent.
44 Deferred Error is a deferred error. R/W
43:32 Model Dependent.
31:16Model-Specific Extended Error CodeThis field encodes model-specific information about the error. Valid if MCA_CONFIG[DeSta -
tErrCodeSupported]=1, else Reserved.R/W
15:0 MCA Error CodeThis field encodes information about the error logged in MCA_DESTAT. Valid if MCA_CON -
FIG[DeStatErrCodeSupported]=1, else Reserved. R/W
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9.3.3.5  MCA Deferred Error Address Register
The MCA_DEADDR register provides the address associated with an error logged in MCA_DESTAT.
The format of this register is the same as MCA_ADDR.The register is only meaningful if MCA_DESTAT[Valid]=1 and MCA_DESTAT[ADDRV]=1. 
9.3.3.6  MCA Miscellaneous Registers 1 - 4
Set by hardware.The format of MCA_MISC[4-1] is the same as the format of MCA_MISC0.
9.3.3.7  MCA Syndrome Registers 1 - 2
The MCA_SYND[2-1] registers store information associated with the error in MCA_STATUS or 
MCA_DESTAT. The contents of these registers are valid if MCA_STATUS[SYNDV] is set or MCA_DESTAT[SYNDV] is set.
The format and contents of this register is implementation dependent. For more information, see the 
9.4 Initializing the Machine-Check Mechanism

Following a processor reset, all machine-check error-reporting enable bits are disabled. System software must enable these bits before machine-check errors can be reported. Generally, system software should initialize the machine-check mechanism using the following process:
•Execute the CPUID instruction and verify that the processor supports the machine-check 
exception (MCE) and machine-check registers (MCA). Software should not proceed with initializing the machine-check mechanism if the machine-check registers are not supported.
•If the machine-check registers are supported, system software should take the following steps:
- Check to see if the CTLP bit in the MCG_CAP register is set to 1. If it is, then the MCG_CTL 
register is supported by the processor. If the MCG_CTL register is supported, software should 
set its enable bits to 1 for the machine-check features it uses. Software can load MCG_CTL with all 1s to enable all available machine-check reporting banks.
- Read the COUNT field from the MCG_CAP register to determine the number of error-
reporting register banks supported by the processor. For each error-reporting register bank, software should set the enable bits to 1 in the MC i_CTL register for the error types it wants the 
processor to report. Software can write each MC i_CTL with all 1s to enable all error-reporting 
mechanisms.
Not enabling reporting banks that may be involved in the reporting of uncorrected errors can
lead to the loss of system reliability and error recoverability.
- Check the V AL bit on each implemented MCi_STATUS register. It is possible that valid error-
status information has already been logged in the MC i_STATUS registers at the time software 
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is attempting to initialize them. The status can reflect errors logged prior to a warm reset or 
errors recorded during the system power-up and boot process. Before clearing the MCi_STATUS registers, software should examine their contents and log any errors found.
- After saving any valid error information contained in the MCi_STATUS, MC i_ADDR, and 
any implemented miscellaneous error information registers for each implemented reporting bank, software should clear all status fields in the MCi_STATUS register for each bank by writing all 0s to the register.
•As a final step in the initialization process, system software should enable the machine-check exception by setting CR4[MCE] to 1.
A machine-check condition that occurs while CR4[MCE] is cleared will result in the processor core entering the shutdown state.
9.5 Using MCA Features
System software can detect and handle logged errors using three methods:
1. Polling
Software can periodically examine the machine-check status registers for errors, and save any
error information found. Uncorrected errors found during polling will require some type ofimmediate response to initiate recovery or shutdown.
2. Enabling machine-check reporting
When reporting is enabled, any uncorrected error that occurs causes control to be transferred to themachine-check exception handler. The exception handler can be designed for a specific processorimplementation or can be generalized to work on multiple implementations.
3. Setting up and enabling interrupts for deferred and corrected errors
In many implementations, MCA hardware can be configured to generate an interrupt hardware onthe detection of a deferred error or when a programmed corrected error threshold is reached.
These methods are not mutually exclusive.
9.5.1  Determining the Scope of Detected Errors
Table 9-4 details the actions that recovery software should take and the level of recovery possible 
based on status information returned in the MCi_STATUS and MCG_STATUS registers.
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9.5.2  Handling Machine Check Exceptions
The processor uses the interrupt control-transfer mechanism to invoke an exception handler after a 
machine-check exception occurs. This requires system software to initialize the interrupt-descriptor table (IDT) with either an interrupt gate or a trap gate that references the interrupt handler. See “Legacy Protected-Mode Interrupt Control Transfers” on page 269 and “Long-Mode Interrupt Control 
Transfers” on page 280 for more information on interrupt control transfers.
At a minimum, the machine-check exception handler must be capable of logging errors for later 
examination. This can be a sufficient implementation for some handlers. More thorough exception-handler implementations can analyze the error to determine if it is unrecoverable, and whether it can be recovered in software.
Machine-check exception handlers that attempt recovery must be thorough in their analysis and their 
corrective actions. The following guidelines should be used when writing such a handler:
•The status registers in all the enabled error-reporting register banks must be examined to identify 
the cause of the machine-check exception. Read the COUNT field from MCG_CAP to determine the number of status registers supported by the processor.
•Check the valid bit in each status register (MCi_STATUS[V AL]). The MC i_STATUS register does 
not need to be examined when its valid bit is clear.
•Check the valid MC i_STATUS registers to see if error recovery is possible. Error recovery is not 
possible when:
- The processor-context corrupt bit (MC i_STATUS[PCC]) is set to 1.
- The error-overflow status bit (MCi_STATUS[OVER]) is set and the processor does not support 
recoverable MCi_STATUS overflow (as indicated by feature bit CPUID 
Fn8000_0007_EBX[McaOverflowRecov] = 0).Table 9-4. Error Scope
MCi_STATUSError ScopePCC TCC UC Deferred
1 — 1 —System fatal error. Error has corrupted the processor core architectural state. 
System processing must be terminated.
0 0 1 —Recoverable error. If software can correct the error, the interrupted program can be resumed.
0 1 1 —Containable error. The interrupted instruction stream cannot be resumed. System-level recovery may be possible if software can localize the error and terminate any affected software processes. 
0 0 0 1Deferred error. Immediate software action is not required. A latent error has been discovered, but not yet consumed. Error handling software may attempt to correct this data error, or prevent access by processes which map the data, or make the physical resource containing the data inaccessible.
0 0 0 0Hardware corrected error. No software action is required. Error information should be saved for analysis.
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- The processor does not support Machine Check Recovery as indicated by feature bit CPUID 
Fn8000_0007_EBX[SUCCOR].
If error recovery is not possible, the handler should log the error information and return to the
system software responsible for shutting down the processor core.
•Check the MC i_STATUS[UC] bit to see if the processor corrected the error. If UC is set, the 
processor did not correct the error and the exception handler must correct the error before restarting the interrupted program. 
- If MCA Recovery is supported:
   • Check MCA_STATUS[TCC].   • If TCC is set, the context of the process executing on the interrupted thread may be corrupt
and the thread cannot be recovered. The rest of the system is unaffected; it is possible to
terminate only the affected process thread.
   • If TCC is clear, the context of the process thread executing on the interrupted logical core is
not corrupt. Recovery of the process thread may be possible, but only if the uncorrectederror condition is first corrected by software; otherwise, the interrupted process thread mustbe terminated.
If the handler cannot correct the error or the MCG_STATUS[RIPV] bit is cleared, it should not return control to the interrupted program, but should log the error information and terminate the software process that was about to consume the uncorrected data. If the error has compromised the state of a guest operating system, the guest should be restarted. If the state of the virtual machine has been corrupted, the virtual machine must be reinitialized.
•When identifying the error condition, portable exception handlers should examine only the architecturally defined fields of the MC i_STATUS register. 
•If the MCG_STATUS[RIPV] bit is set, the interrupted program can be restarted reliably at the instruction pointer address pushed onto the exception handler stack. If RIPV = 0, the interrupted program cannot be restarted reliably at that location, although it can be restarted at that location for debugging purposes.

•When logging errors, particularly those that are not recoverable, check the MCG_STATUS[EIPV] bit to see if the instruction-pointer address pushed onto the exception handler stack is related to the process thread interrupted by the machine-check exception. If EIPV = 0, the address is not guaranteed to be related to the interrupted process thread.
•Before exiting the machine-check handler, clear the MCG_STATUS[MCIP] bit. MCIP indicates a machine-check exception occurred. If this bit is set when another machine-check exception occurs, the processor enters the shutdown state.
•When an exception handler is able to, at a minimum, successfully log an error condition, the MCi_STATUS registers should be cleared before exiting the machine-check handler. Software is 
responsible for clearing at least the MCi_STATUS[V AL] bits.
•Additional machine-check exception-handler portability can be added by having the handler use the CPUID instruction to identify the processor and its capabilities. Implementation-specific 
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software can be added to the machine-check exception handler based on the processor information 
reported by CPUID.
9.5.3  Reporting Corrected Errors
Machine-check exceptions do not occur if the error is corrected by the processor. If system software 
wishes to detect and save information concerning corrected machine-check errors, a system-service routine must be provided to check the contents of the machine-check status registers for corrected errors. The service routine can be invoked by system software on a periodic basis, or by an error-thresholding interrupt.
A service routine that gathers error information for corrected errors should perform the following:
•Examine the status register (MC i_STATUS) in each of the enabled error-reporting register banks. 
For each MC i_STATUS register with a set valid bit (V AL=1), the service routine should:
- Save the contents of the MC i_STATUS register.
- Save the contents of the corresponding MCi_ADDR register if MC i_STATUS[ADDRV] = 1.
- Save the contents of the corresponding MCi_MISC register if MCi_STATUS[MISCV] = 1.
•Once the information found in the error-reporting register banks is saved, the MC i_STATUS 
register should be cleared. This allows the processor to properly report any subsequent errors in the 
MCi_STATUS registers.
•The service routine can save the time-stamp counter with each error logged. This can help in determining how frequently errors occur. For further information, see “Time-Stamp Counter” on page 422.
•In multiprocessor configurations, the service routine can save the processor-node identifier. This can help locate a failing multiprocessor-system component, which can then be isolated from the rest of the system. For further information, see the documentation for particular implementations of the architecture.
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10 System-Management Mode
System-management mode (SMM) is an operating mode designed for system-control activities like 
power management. Normally, these activities are transparent to conventional operating systems and applications. SMM is used by platform firmware and specialized low-level device drivers, rather than 
The SMM interrupt-handling mechanism differs substantially from the standard interrupt-handling 
mechanism described in Chapter 8, “Exceptions and Interrupts.” SMM is entered using a special external interrupt called the system-management interrupt (SMI). After an SMI is received by the 
processor, the processor saves the processor state in a separate address space, called SMRAM . The 
SMM-handler software and data structures are also located in the SMRAM space. Interrupts and exceptions that ordinarily cause control transfers to the operating system are disabled when SMM is entered. The processor exits SMM, restores the saved processor state, and resumes normal execution by using a special instruction, RSM.
In SMM, address translation is disabled and addressing is similar to real mode. SMM programs can address up to 4 Gbytes of physical memory. See “SMM Operating-Environment” on page 333 for additional information on memory addressing in SMM.
The following sections describe the components of the SMM mechanism:
•“SMM Resources” on page 324 —this section describes SMRAM, the SMRAM save-state area
used to hold the processor state, and special SMRAM save-state entries used in support of SMM.
•“Using SMM” on page 333 —this section describes the mechanism of entering and exiting SMM.
It also describes SMM memory allocation, addressing, and interrupts and exceptions.
Of these mechanisms, only the format of the SMRAM save-state area differs between the AMD64 
architecture and the legacy architecture.
Note: Model-independent aspects of SMM operation are described here; see the BIOS and Kernel 
Developer’s Guide (BKDG) or Processor Programming Reference Manual  of a given processor 
family for possible model-specific details.
10.1 SMM Differences
There are functional differences between the SMM support in the AMD64 architecture and the SMM support found in previous architectures. These are:
•The SMRAM state-save area layout is changed to hold the 64-bit processor state.
•The initial processor state upon entering SMM is expanded to reflect the 64-bit nature of the
•New conditions exist that can cause a processor shutdown while in SMM.
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•The auto-halt restart and I/O-instruction restart entries in the SMRAM state-save area are one byte
each instead of two bytes each.
•Some previous AMD x86 processors saved and restored the CR2 register in the SMRAM state-save area. This register is not saved by the SMM implementation in the AMD64 architecture.SMM handlers that save and restore CR2 must perform the operation in software.
10.2 SMM Resources
The SMM resources supported by the processor consist of SMRAM, the SMRAM state-save area, and special entries within the SMRAM state-save area. In addition to the save-state area, SMRAM includes space for the SMM handler.
10.2.1  SMRAM
SMRAM is the memory-address space accessed by the processor when in SMM. The default size of 
SMRAM is 64 Kbytes and can range in size between 32 Kbytes and 4 Gbytes. System logic can use physically separate SMRAM and main memory, directing memory transactions to SMRAM after recognizing SMM is entered, and redirecting memory transactions back to system memory after recognizing SMM is exited. When separate SMRAM and main memory are used, the system designer needs to provide a method of mapping SMRAM into main memory so that the SMI handler and data structures can be loaded.
Figure 10 -1 on page 325 shows the default SMRAM memory map. The default SMRAM code 
segment (CS) has a base address of 0003_0000h (the base address is automatically scaled by the 
processor using the CS-selector register, which is set to the value 3000h). This default SMRAM-base address is known as SMBASE . A 64-Kbyte memory region, addressed from 0003_0000h to 
0003_FFFFh, makes up the default SMRAM memory space. The top 32 Kbytes (0003_8000h to 0003_FFFFh) must be supported by system logic, with physical memory covering that entire address range. The top 512 bytes (0003_FE00h to 0003_FFFFh) of this address range are the default SMM 
state-save area . The default entry point for the SMM interrupt handler is located at 0003_8000h. 
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Figure 10-1. Default SMRAM Memory Map
10.2.2  SMBASE Register
The format of the SMBASE register is shown in Figure 10 -2. SMBASE is an internal processor 
register that holds the value of the SMRAM-base address. SMBASE is set to 30000h after a processor 
reset.
Figure 10-2. SMBASE Register
In some operating environments, relocation of SMRAM to a higher memory area can provide more low memory for legacy software. SMBASE relocation is supported when the SMM-base relocation bit in the SMM-revision identifier (bit 17) is set to 1. In processors implementing the AMD64 architecture, SMBASE relocation is always supported. 
Software can only modify SMBASE (relocate the SMRAM-base address) by entering SMM, 
modifying the SMBASE image stored in the SMRAM state-save area, and exiting SMM. The SMM-handler entry point must be loaded at the new memory location specified by SMBASE+8000h. The next time SMM is entered, the processor saves its state in the new state-save area at SMBASE+0FE00h, and begins executing the SMM handler at SMBASE+8000h. The new SMBASE address is used for every SMM until it is changed, or a hardware reset occurs. 513-250.epsSMM State-Save AreaSMRAM
0003_FFFFh
0003_FE00h
0003_8000h
0003_0000hSMM Handler

reset.
(SMBASE+8000h)
(SMBASE)(SMBASE+FFFFh)
0 31
SMRAM Base 
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When SMBASE is used to relocate SMRAM to an address above 1 Mbyte, 32-bit address-size 
override prefixes must be used to access this memory. This is because addressing in SMM behaves as it does in real mode, with a 16-bit default operand size and address size. The values in the 16-bit segment-selector registers are left-shifted four bits to form a 20-bit segment-base address. Without using address-size overrides, the maximum computable address is 10FFEFh.
Because SMM memory-addressing is similar to real-mode addressing, the SMBASE address must be 
less than 4 Gbytes.
10.2.3  SMRAM State-Save Area
When an SMI occurs, the processor saves its state in the 512-byte SMRAM state-save area during the 
control transfer into SMM. The format of the state-save area defined by the AMD64 architecture is shown in Table 10 -1. This table shows the offsets in the SMRAM state-save area relative to the 
SMRAM-base address. The state-save area is located between offset 0_FE00h (SMBASE+0_FE00h) and offset 0_FFFFh (SMBASE+0_FFFFh). Software should not modify offsets specified as read-only or reserved, otherwise unpredictable results can occur.
Table 10-1. AMD64 Architecture SMM State-Save Area
Offset (Hex) 
from SMBASEContents SizeAllowable 
Access
FE00h
ESSelector Word
Read-OnlyFE02h Attributes Word
FE04h Limit Doubleword
FE08h Base Quadword
FE10h
CSSelector Word
Read-OnlyFE12h Attributes Word
FE14h Limit Doubleword
FE18h Base Quadword
FE20h
SSSelector Word
Read-OnlyFE22h Attributes Word
FE24h Limit Doubleword
FE28h Base Quadword
FE30h
DSSelector Word
Read-OnlyFE32h Attributes Word
FE34h Limit Doubleword
FE38h Base Quadword
Note:
1. The offset for the SMM-revision identifier is compatible with previous implementations.
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FE40h
FSSelector Word
Read-OnlyFE42h Attributes Word
FE44h Limit Doubleword
FE48h Base Quadword
FE50h
GSSelector Word
Read-OnlyFE52h Attributes Word
FE54h Limit Doubleword
FE58h Base Quadword
FE60h–FE63h
GDTRReserved 4 Bytes
Read-OnlyFE64h Limit Word
FE66h–FE67h Reserved 2 Bytes
FE68h Base Quadword
FE70h
LDTRSelector Word
Read-OnlyFE72h Attributes Word
FE74h Limit Doubleword
FE78h Base Quadword
FE80h–FE83h
IDTRReserved 4 Bytes
Read-OnlyFE84h Limit Word
FE86h–FE87h Reserved 2 Bytes
FE88h Base Quadword
FE90h
TRSelector Word
Read-OnlyFE92h Attributes Word
FE94h Limit Doubleword
FE98h Base Quadword
FEA0h I/O Instruction Restart RIP Quadword Read-Only
FEA8h I/O Instruction Restart RCX Quadword Read-Only
FEB0h I/O Instruction Restart RSI Quadword Read-Only
FEB8h I/O Instruction Restart RDI Quadword Read-Only
FEC0h I/O Instruction Restart Dword Doubleword Read-Only
FEC4h–FEC7h Reserved 4 Bytes —
FEC8h I/O Instruction Restart ByteRead/WriteFEC9h Auto-Halt Restart Byte
FECAh—FECFh Reserved 6 Bytes —
FED0h EFER Quadword Read-OnlyTable 10-1. AMD64 Architecture SMM State-Save Area (continued)
Access
Note:
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FED8h SVM Guest Quadword
Read-Only FEE0h SVM Guest VMCB Physical Address Quadword
FEE8h SVM Guest Virtual Interrupt Quadword
FEF0h—FEFBh Reserved 12 Bytes —
FEFCh SMM-Revision Identifier1 Doubleword Read-Only
FF00h SMBASE Doubleword Read/Write
FF04h—FF17h Reserved 20 Bytes —
FF18h SSP Quadword Read/Write
FF20h SVM Guest PAT Quadword
Read-OnlyFF28h SVM Host EFER Quadword
FF30h SVM Host CR4 Quadword
FF38h SVM Host CR3 Quadword
FF40h SVM Host CR0 Quadword
FF48h CR4 Quadword
Read-Only FF50h CR3 Quadword
FF58h CR0 Quadword
FF60h DR7 QuadwordRead-OnlyFF68h DR6 Quadword
FF70h RFLAGS Quadword Read/Write
FF78h RIP Quadword
Read/WriteFF80h R15 Quadword
FF88h R14 Quadword
FF90h R13 Quadword
FF98h R12 Quadword
FFA0h R11 Quadword
FFA8h R10 Quadword
FFB0h R9 Quadword
FFB8h R8 QuadwordTable 10-1. AMD64 Architecture SMM State-Save Area (continued)
Access
Note:
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A number of other registers are not saved or restored automatically by the SMM mechanism. See 
“Saving Additional Processor State” on page 336 for information on using these registers in SMM.
As a reference for legacy processor implementations, the legacy SMM state-save area format is shown 
in Table 10 -2. Implementations of the AMD64 architecture do not use this format.FFC0h RDI Quadword
Read/WriteFFC8h RSI Quadword
FFD0h RBP Quadword
FFD8h RSP Quadword
FFE0h RBX Quadword
FFE8h RDX Quadword
FFF0h RCX Quadword
FFF8h RAX Quadword
Table 10 -2. Legacy SMM State-Save Area (Not used by AMD64 
Architecture)  
Offset (Hex)
from SMBASEContents SizeAllowable
Access
FE00h—FEF7h Reserved 248 Bytes —
FEF8h SMBASE Doubleword Read/Write
FEFCh SMM-Revision Identifier Doubleword Read-Only
FF00h I/O Instruction Restart WordRead/WriteFF02h Auto-Halt Restart Word
FF04h—FF87h Reserved 132 Bytes —
FF88h GDT Base Doubleword Read-Only
FF8Ch—FF93h Reserved Quadword —
FF94h IDT Base Doubleword Read-Only
FF98h—FFA7h Reserved 16 Bytes —
Note:
1. The offset for the SMM-revision identifier is compatible with previous implementations.Table 10-1. AMD64 Architecture SMM State-Save Area (continued)
Access
Note:
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10.2.4  SMM-Revision Identifier
The SMM-revision identifier specifies the SMM version and the available SMM extensions 
implemented by the processor. Software reads the SMM-revision identifier from offset FEFCh in the SMM state-save area of SMRAM. This offset location is compatible with earlier versions of SMM. Software must not write to this location. Doing so can produce undefined results. Figure 10 -3 on 
page 331 shows the format of the SMM-revision identifier.FFA8h ES Doubleword
Read-OnlyFFACh CS Doubleword
FFB0h SS Doubleword
FFB4h DS Doubleword
FFB8h FS Doubleword
FFBCh GS Doubleword
FFC0h LDT Base DoublewordRead-OnlyFFC4h TR Doubleword
FFC8h DR7 DoublewordRead-OnlyFFCCh DR6 Doubleword
FFD0h EAX Doubleword
Read/WriteFFD4h ECX Doubleword
FFD8h EDX Doubleword
FFDCh EBX Doubleword
FFE0h ESP Doubleword
FFE4h EBP Doubleword
FFE8h ESI Doubleword
FFECh EDI Doubleword
FFF0h EIP Doubleword Read/Write
FFF4h EFLAGS Doubleword Read/Write
FFF8h CR3 DoublewordRead-OnlyFFFCh CR0 DoublewordTable 10 -2. Legacy SMM State-Save Area (Not used by AMD64 
Architecture) (continued) 
Access
Note:
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Figure 10-3. SMM-Revision Identifier
The fields within the SMM-revision identifier are:
•SMM-revision Level—Bits 15:0. Specifies the version of SMM supported by the processor. The
SMM-revision level is of the form 0_xx64h, where xx starts with 00 and is incremented for later
revisions to the SMM mechanism. 
•I/O Instruction Restart —Bit 16. When set to 1, the processor supports restarting I/O instructions
that are interrupted by an SMI. This bit is always set to 1 by implementations of the AMD64architecture. See “I/O Instruction Restart” on page 337 for information on using this feature.
•SMM Base Relocation —Bit 17. When set to 1, the processor supports relocation of SMRAM. This
bit is always set to 1 by implementations of the AMD64 architecture. See “SMBASE Register” onpage 325 for information on using this feature.
All remaining bits in the SMM-revision identifier are reserved.
10.2.5  SMRAM Protected Areas
Two areas are provided as safe areas for SMM code and data that are not readily accessible by non-
SMM applications. The SMI handler can be located in one of these two ranges, or it can be located outside of these ranges. The handler is placed in the desired range by setting SMBASE accordingly.
The ASeg range is located at a fixed address from A_0000h to B_FFFFh. The TSeg range is located at 
a variable base specified by the SMM_ADDR MSR with a variable size specified by the SMM_MASK MSR. These ranges must never overlap.
Each CPU memory access is in the TSeg range if the following is true:Phys Addr[51:17] & SMM_MASK[51:17] = SMM_ADDR[51:17] & SMM_MASK[51:17].For example, if the TSeg range spans 256 Kbytes starting at address 10_0000h, then SMM_ADDR 
=0010_0000h and SMM_MASK=FFFC_0000h. This results in a TSeg address range from 0010_0000 513-251epsSMM-Revision Level0 15 16 17 31Reserved
Description Bits
SMM-Revision Level

I/O Instruction RestartSMM Base Relocation15:01617
18
11
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to 0013_FFFFh. The TSeg range must be aligned to a 128 Kbyte boundary and the minimum TSeg 
size is 128 Kbytes.
Figure 10-4. SMM_ADDR Register Format
•SMM TSeg Base Address (BASE)— Bits 51:17. Specifies the base address of the TSeg range of
protected addresses.
Figure 10-5. SMM_MASK Register Format
•ASeg Address Range Enable (AE) —Bit 0. Specifies whether the ASeg address range is enabled for
protection. When the bit is set to 1, the ASeg address range is enabled for protection. When clearedto 0, the ASeg address range is disabled for protection.63 52 51 32
Reserved BASE[51:32]
31 17 16 0
BASE[31:17] Reserved
63:52 Reserved RAZ
51:17 BASE SMM TSeg Base Address R/W
16:0 Reserved RAZ
63 52 51 32
Reserved MASK[51:32]
31 17 16 2 1 0
MASK[31:17] Reserved TE AE
51:17 MASK TSeg Mask R/W
16:2 Reserved RAZ
1 TE Tseg Address Range Enable R/W
0 AE Aseg Address Range Enable R/W
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•TSeg Address Range Enable (TE)—Bit 1. Specifies whether the TSeg address range is enabled for
protection. When the bit is set to 1, the TSeg address range is enabled for protection. When clearedto 0, the TSeg address range is disabled for protection.
•TSeg Mask (MASK)—Bits 51:17. Specifies the mask used to determine the TSeg range of protectedaddresses. The physical address is in the TSeg range if the following is true: 
Phys Addr[51:17] & SMM_MASK[51:17] = SMM_ADDR[51:17] & SMM_MASK[51:17].
Note that a processor is not required to implement all 52 bits of the physical address.
10.3 Using SMM
10.3.1  System-Management Interrupt (SMI)
SMM is entered using the system-management interrupt (SMI). SMI is an external non-maskable 
interrupt that operates differently from and independently of other interrupts. SMI has priority over all other external interrupts, including NMI (see “Priorities” on page 263 for a list of the interrupt priorities). SMIs are disabled when in SMM, which prevents reentrant calls to the SMM handler.
When an SMI is received by the processor, the processor stops fetching instructions and waits for 
currently-executing instructions to complete and write their results. The SMI also waits for all buffered memory writes to update the caches or system memory. When these activities are complete, the processor uses implementation-dependent external signaling to acknowledge back to the system that it has received the SMI.
10.3.2  SMM Operating-Environment
The SMM operating-environment is similar to real mode, except that the segment limits in SMM are 4 
Gbytes rather than 64 Kbytes. This allows an SMM handler to address memory in the range from 0h to 0FFFF_FFFFh. As with real mode, segment-base addresses are restricted to 20 bits in SMM, and the default operand-size and address-size is 16 bits. To address memory locations above 1 Mbyte, the SMM handler must use the 32-bit operand-size-override and address-size-override prefixes.
After saving the processor state in the SMRAM state-save area, a processor running in SMM sets the 
segment-selector registers and control registers into a state consistent with real mode. Other registers are also initialized upon entering SMM, as shown in Table 10 -3.
Table 10-3. SMM Register Initialization
Register Initial SMM Contents
CSSelector SMBASE right-shifted 4 bits
Base SMBASELimit FFFF_FFFFhAttr Read-Write-Execute
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10.3.3  Exceptions and Interrupts
All hardware interrupts are disabled upon entering SMM, but exceptions and software interrupts are 
not disabled. If necessary, the SMM handler can re-enable hardware interrupts. Software that handles interrupts in SMM should consider the following:
•SMI—If an SMI occurs while the processor is in SMM, it is latched by the processor. The latched
SMI occurs when the processor leaves SMM.
•NMI—If an NMI occurs while the processor is in SMM, it is latched by the processor, but the NMI
handler is not invoked until the processor leaves SMM with the execution of an RSM instruction.
A pending NMI causes the handler to be invoked immediately after the RSM completes and beforethe first instruction in the interrupted program is executed.
An SMM handler can unmask NMI interrupts by simply executing an IRET. Upon completion of
the IRET instruction, the processor recognizes the pending NMI, and transfers control to the NMIhandler. Once an NMI is recognized within SMM using this technique, subsequent NMIs arerecognized until SMM is exited. Later SMIs cause NMIs to be masked, until the SMM handlerunmasks them.
•Exceptions —Exceptions (internal processor interrupts) are not disabled and can occur while in
SMM. Therefore, the SMM-handler software should be written to avoid generating exceptions.
•Software Interrupts—The software-interrupt instructions (BOUND, INTn, INT3, and INTO) canbe executed while in SMM. However, it is not recommended that the SMM handler use theseinstructions.
•Maskable Interrupts —RFLAGS.IF is cleared to 0 by the processor when SMM is entered.
Software can re-enable maskable interrupts while in SMM, but it must follow the guidelines listedbelow for handling interrupts.DS, ES, FS, GS, SSSelector 0000h
Base 0000_0000_0000_0000hLimit FFFF_FFFFhAttr Read-Write
RIP 0000_0000_0000_8000h
RFLAGS 0000_0000_0000_0002h
CR0PE, EM, TS, PG bits cleared to 0.
All other bits are unmodified.
CR4 0000_0000_0000_0000h
DR7 0000_0000_0000_0400h
EFER 0000_0000_0000_0000hTable 10-3. SMM Register Initialization (continued)
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•Debug Interrupts —The processor disables the debug interrupts when SMM is entered by clearing
DR7 to 0 and clearing RFLAGS.TF to 0. The SMM handler can re-enable the debug facilities
while in SMM, but it must follow the guidelines listed below for handling interrupts.
•INIT— The processor does not recognize INIT while in SMM.
Because the RFLAGS.IF bit is cleared when entering SMM, the HLT instruction should not be executed in SMM without first setting the RFLAGS.IF bit to 1. Setting this bit to 1 allows the processor to exit the halt state by using an external maskable interrupt.
In the cases where an SMM handler must accept and handle interrupts and exceptions, several 
guidelines must be followed:
•Interrupt handlers must be loaded and accessible before enabling interrupts.
•A real-mode interrupt vector table located at virtual (linear) address 0 is required.
•Segments accessed by the interrupt handler cannot have a base address greater than 20 bits because
of the real-mode addressing used in SMM. In SMM, the 16-bit value stored in the segment-selectorregister is left-shifted four bits to form the 20-bit segment-base address, like real mode.
•Only the IP (rIP[15:0]) is pushed onto the stack as a result of an interrupt in SMM, because of thereal-mode addressing used in SMM. If the SMM handler is interrupted at a code-segment offsetabove 64 Kbytes, then the return address on the stack must be adjusted by the interrupt-handler,and a RET instruction with a 32-bit operand-size override must be used to return to the SMMhandler.
•If the interrupt-handler is located below 1 Mbyte, and the SMM handler is located above 1 Mbyte,a RET instruction cannot be used to return to the SMM handler. In this case, the interrupt handlercan adjust the return pointer on the stack, and use a far CALL to transfer control back to the SMMhandler.
10.3.4  Invalidating the Caches
The processor can cache SMRAM-memory locations. If the system implements physically separate 
SMRAM and system memory, it is possible for SMRAM and system memory locations to alias into identical cache locations. In some processor implementations, the cache contents must be written to memory and invalidated when SMM is entered and exited. This prevents the processor from using 
previously-cached main-memory locations as aliases for SMRAM-memory locations when SMM is entered, and vice-versa when SMM is exited. 
Implementations of the AMD64 architecture do not require cache invalidation  when entering and 
exiting SMM. Internally, the processor keeps track of SMRAM and system-memory accesses 
separately and properly handles situations where aliasing occurs. Cached system memory and SMRAM locations can persist across SMM mode changes. Removal of the requirement to writeback and invalidate the cache simplifies SMM entry and exit and allows SMM code to execute more rapidly. 
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10.3.5  Saving Additional Processor State
Several registers are not saved or restored automatically by the SMM mechanism. These are:
•The 128-bit media instruction registers.

•The 64-bit media instruction registers.
•The x87 floating-point registers.
•The page-fault linear-address register (CR2).
•The task-priority register (CR8).
•The debug registers, DR0, DR1, DR2, and DR3.
•The memory-type range registers (MTRRs).
•Model-specific registers (MSRs).
These registers are not saved because SMM handlers do not normally use or modify them. If an SMI 
results in a processor reset (due to powering down the processor, for example) or the SMM handler modifies the contents of the unsaved registers, the SMM handler should save and restore the original contents of those registers. The unsaved registers, along with those stored in the SMRAM state-save area, need to be saved in a non-volatile storage location if a processor reset occurs. The SMM handler should execute the CPUID instruction to determine the feature set available in the processor, and be able to save and restore the registers required by those features. For more information on using the CPUID instruction, see Section 3.3, “Processor Feature Identification,” on page 71.
The SMM handler can execute any of the 128-bit media, 64-bit media, or x87 instructions. A simple 
method for saving and restoring those registers is to use the FXSA VE and FXRSTOR instructions, respectively, if it is supported by the processor. See “Saving Media and x87 Execution Unit State” on page 348 for information on saving and restoring those registers.
Floating-point exceptions can occur when the SMM handler uses media or x87 floating-point 
instructions. If the SMM handler uses floating-point exception handlers, they must follow the usage guidelines established in “Exceptions and Interrupts” on page 334. A simple method for dealing with 
floating-point exceptions while in SMM is to simply mask all exception conditions using the appropriate floating-point control register. When the exceptions are masked, the processor handles floating-point exceptions internally in a default manner, and allows execution to continue uninterrupted.
10.3.6  Operating in Protected Mode and Long Mode
Software can enable protected mode from SMM and it can also enable and activate long mode. An 
SMM handler can use this capability to enter 64-bit mode and save additional processor state that cannot be accessed from outside 64-bit mode (for example, the most-significant 32 bits of CR2).
10.3.7  Auto-Halt Restart
The auto-halt restart entry is located at offset FEC9h in the SMM state-save area. The size of this field 
is one byte, as compared with two bytes in previous versions of SMM.
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When entering SMM, the processor loads the auto-halt restart entry to indicate whether SMM was 
entered from the halt state, as follows: 
•Bit 0 indicates the processor state upon entering SMM:
- When set to 1, the processor entered SMM from the halt state.- When cleared to 0, the processor did not enter SMM from the halt state.
•Bits 7:1 are cleared to 0.
The SMM handler can write the auto-halt restart entry to specify whether the return from SMM should 
take the processor back to the halt state or to the instruction-execution state specified by the SMM state-save area. The values written are:
•Clear to 00h —The processor returns to the state specified by the SMM state-save area.
•Set to any non-zero value —The processor returns to the halt state.
If the return from SMM takes the processor back to the halt state, the HLT instruction is not re-
executed. However, the halt special bus-cycle is driven on the processor bus after the RSM instruction executes.
The result of entering SMM from a non-halt state and returning to a halt state is not predictable.
10.3.8  I/O Instruction Restart
The I/O-instruction restart entry is located at offset FEC8h in the SMM state-save area. The size of this 
field is one byte, as compared with two bytes in previous versions of SMM. The I/O-instruction restart mechanism is supported when the I/O-instruction restart bit (bit 16) in the SMM-revision identifier is set to 1. This bit is always set to 1 in the AMD64 architecture. 
When an I/O instruction is interrupted by an SMI, the I/O-instruction restart entry specifies whether 
the interrupted I/O instruction should be re-executed following an RSM that returns from SMM. Re-executing a trapped I/O instruction is useful, for example, when an I/O write is performed to a powered-down disk drive. When this occurs, the system logic monitoring the access can issue an SMI to have the SMM handler power-up the disk drive and retry the I/O write. The SMM handler does this by querying system logic and detecting the failed I/O write, asking system logic to initiate the disk-drive power-up sequence, enabling the I/O instruction restart mechanism, and returning from SMM. Upon returning from SMM, the I/O write to the disk drive is restarted.
When an SMI occurs, the processor always clears the I/O-instruction restart entry to 0. If the SMI 
interrupted an I/O instruction, then the SMM handler can modify the I/O-instruction restart entry as follows:
•Clear to 00h (default value) —The I/O instruction is not restarted, and the instruction following the
interrupted I/O-instruction is executed. When a REP (repeat) prefix is used with an I/O instruction,
it is possible that the next instruction to be executed is the next I/O instruction in the repeat loop.
•Set to any non-zero value —The I/O instruction is restarted.
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While in SMM, the handler must determine the cause of the SMI and examine the processor state at the 
time the SMI occurred to determine whether or not an I/O instruction was interrupted. Implementations provide state information in the SMM save-state area to assist in this determination:
•I/O Instruction Restart DWORD—indicates whether the SMI interrupted an I/O instruction, and
saves extra information describing the I/O instruction.
•I/O Instruction Restart RIP—the RIP of the interrupted I/O instruction.
•I/O Instruction Restart RCX—the RCX of the interrupted I/O instruction.
•I/O Instruction Restart RSI—the RSI of the interrupted I/O instruction.
•I/O Instruction Restart RDI—the RDI of the interrupted I/O instruction.
Figure 10-6. I/O Instruction Restart Dword
The fields in the I/O Instruction Restart DWORD are as follows:
•B3—DR6.B3 status 
•B2—DR6.B2 status 
•B1—DR6.B1 status 
•B0 —DR6.B0 status 
•TF—The I/O instruction was interrupted with Single Stepping (EFLAGS.TF = 1)
•PORT—Intercepted I/O port
•A64—64-bit address
•A32—32-bit address
•A16—16-bit address 
•SZ32—32-bit I/O port size
•SZ16—16-bit I/O port size
•SZ8—8-bit I/O port size
•REP—Repeated port access
•STR—String based port access (INS, OUTS)
•V AL—Valid (SMI was detected during an I/O instruction.)
•TYPE—Access type (0 = OUT instruction, 1 = IN instruction).
10.3.9  SMM Page Configuration Lock
The SMM Page Configuration Lock feature allows the SMM handler to lock the paging configuration. 
The feature is enabled by setting HWCR.SMM_PGCFG_LOCK=1 (bit 33). Once locked, the paging 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT
B3
B2B1B0TF
PORT
A64A32A16
SZ32
SZ16
SZ8
REPSTR
V AL
TYPE
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configuration cannot be modified until SMM is exited using the RSM instruction. The processor clears 
HWCR.SMM_PGCFG_LOCK when completing the RSM instruction. If page configuration locking is needed when the processor enters SMM again in the future, HWCR.SMM_PGCFG_LOCK must be set again by the SMM handler. 
When SMM Page Configuration Lock is enabled, the following will result in a #GP exception: 
•Writing Extended Feature Register (EFER) using the WRMSR instruction.
•Writing CR0, CR3, or CR4 using the MOV CRn instruction.
Attempting to set HWCR.SMM_PGCFG_LOCK when not in SMM results in a #GP exception. 
Before setting HWCR.SMM_PGCFG_LOCK, system software must verify the processor supports the SMM Page Configuration Lock feature by checking that CPUID Fn8000_0021_EAX[SmmPgCfgLock] (bit 3) = 1. For more information on using the CPUID instruction see Section 3.3, “Processor Feature Identification,” on page 71.
10.4 Leaving SMM
Software leaves SMM and returns to the interrupted program by executing the RSM instruction. RSM causes the processor to load the interrupted state from the SMRAM state-save area and then transfer control back to the interrupted program. RSM cannot be executed in any mode other than SMM, otherwise an invalid-opcode exception (#UD) occurs.
An RSM causes a processor shutdown if an invalid-state condition is found in the SMRAM state-save 
area. Only an external reset, external processor-initialization, or non-maskable external interrupt (NMI) can cause the processor to leave the shutdown state. The invalid SMRAM state-save-area conditions that can cause a processor shutdown during an RSM are:
•CR0.PE=0 and CR0.PG=1.
•CR0.CD=0 and CR0.NW=1.
•Certain reserved bits are set to 1, including:

- Any CR0 bit in the range 63:32 is set to 1.- Any unsupported bit in CR3 is set to 1.- Any unsupported bit in CR4 is set to 1.- Any DR6 bit or DR7 bit in the range 63:32 is set to 1.- Any unsupported bit in EFER is set to 1.
•Invalid returns to long mode, including:- EFER.LME=1, CR0.PG=1, and CR4.PAE=0. - EFER.LME=1, CR0.PG=1, CR4.PAE=1, CS.L=1, and CS.D=1.
•The SSM revision identifier is modified.
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Some SMRAM state-save-area conditions are ignored, and the registers, or bits within the registers, 
are restored in a default manner by the processor. This avoids a processor shutdown when an invalid condition is stored in SMRAM. The default conditions restored by the processor are:
•The EFER.LMA register bit is set to the value obtained by logically ANDing the SMRAM values
of EFER.LME, CR0.PG, and CR4.PAE.
•The RFLAGS.VM register bit is set to the value obtained by logically ANDing the SMRAMvalues of RFLAGS.VM, CR0.PE, and the inverse of EFER.LMA.
•The base values of FS, GS, GDTR, IDTR, LDTR, and TR are restored in canonical form. Thosevalues are sign-extended to bit 63 using the most-significant implemented bit.
•Unimplemented segment-base bits in the CS, DS, ES, and SS registers are cleared to 0.
•SSP is canonicalized (i.e., sign-extended to bit 63). 
10.5 Multiprocessor Considerations
For multiprocessor operation, each logical processor must be given a separate SMBASE value so that the save-state areas do not overlap. For systems with fewer than 64 logical processors it is sufficient to 
stagger the SMBASE values by 512 bytes. Note that this also offsets the SMI entry point by the same amount for each processor. With 64 or more logical processors, the entry points will start to collide with the save-state areas. Staggering the SMBASE values by 1024 bytes results in 512-byte entry point areas interleaved with the 512-byte state-save areas, and so provides scaling beyond 63 logical processors. 
Further details on multiprocessor aspects of SMM may be found in the BIOS and Kernel Developer’s 
Guide (BKDG) or Processor Programming Reference Manual  for a given processor family.
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11 SSE, MMX, and x87 Programming
This chapter describes the system-software implications of supporting applications that use the 
Streaming SIMD Extensions (SSE), MMX™, and x87 instructions. Throughout this chapter, these instructions are collectively referred to as media and x87 (media/x87) instructions. A complete listing 
of the instructions that fall in this category—and the detailed operation of each instruction—can be found in volumes 4 and 5. Refer to V olume 1 for information on using these instructions in application software.
The SSE instruction set is comprised of the legacy SSE  instruction set which includes the SSE1, SSE2, 
SSE3, SSSE3, SSE4A, SSE4.1, and SSE4.2 subsets and the extended SSE  instruction set which 
includes the A VX, FMA4, and XOP subsets. Many of the extended SSE instructions support both 128-
bit and 256-bit data types.
11.1 Overview of System-Software Considerations
Processor implementations can support different combinations of the SSE, MMX, and x87 instruction sets. Two sets of registers—independent of the general-purpose registers—support these instructions. The SSE instructions operate on the YMM/XMM registers, and the 64-bit media and x87-instructions operate on the aliased MMX/x87 registers. The SSE and x87 floating-point instruction sets have distinct status registers, control registers, exception vectors, and system-software control bits for managing the operating environment. System software that supports use of these instructions must be able to manage these resources properly including:
•Detecting support for the instruction set, and enabling any optional features, as necessary.
•Saving and restoring the processor media or x87 state.
•Execution of floating-point instructions (media or x87) can produce exceptions. System software 
must supply exception handlers for all unmasked floating-point exceptions.
11.2 Determining Media and x87 Feature Support
Support for the architecturally defined subsets within the media and x87 instructions is implementation dependent. System software executes the CPUID instruction to determine whether a processor implements any of these features (see Section 3.3, “Processor Feature Identification,” on page 71 for more information on using the CPUID instruction). After CPUID is executed feature support can be determined by examining specific bit fields returned in the EAX, ECX, and EDX registers. 
The following table summarizes the architecturally defined SSE subsets and state management 
instructions and gives the feature bits returned by the CPUID function. If the indicated bit is set, the feature is supported by the processor.
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Some instructions may be listed in more than one subset. If software attempts to execute an instruction 
belonging to an unsupported instruction subset, an invalid-opcode exception (#UD) occurs. Refer to Appendix D, “Instruction Subsets and CPUID Feature Flags” in V olume 3 for specific information.Table 11-5. SSE Subsets – CPUID Feature Identifiers
CPUID Fn Field Name Field Bit Instruction Subset
Legacy SSE
0000_0001h EDX[SSE] EDX[25] Original Streaming SIMD Extensions (SSE1)
0000_0001h EDX[SSE2] EDX[26] SSE2
0000_0001h ECX[SSE3] ECX[0] SSE3
0000_0001h ECX[SSSE3] ECX[9] SSSE3
0000_0001h ECX[SSE41] ECX[19] SSE4.1
0000_0001h ECX[SSE42] ECX[20] SSE4.2
8000_0001h ECX[SSE4A] ECX[6]SSE4A: EXTRQ, INSERTQ, MOVNTSS, and 
MOVNTSD instructions
Extended SSE
0000_0001h ECX[A VX] ECX[28] A VX
8000_0001h ECX[XOP] ECX[11] AMD XOP
0000_0001h ECX[FMA] ECX[12] FMA
8000_0001h ECX[FMA4] ECX[16] AMD FMA4
MMX
0000_0001h or 
8000_0001hEDX[MMX] EDX[23] Original MMX™ Instructions
8000_0001h EDX[MmxExt] EDX[22] AMD Extensions to MMX
8000_0001h EDX[3DNow] EDX[31] AMD 3DNow!™
8000_0001h EDX[3DNowExt] EDX[30] AMD Extensions to 3DNow!
x87
8000_0001hEDX[FPU] EDX[0] x87 instruction set and facilities
Context Management Instructions
8000_0001hEDX[FXSR] EDX[24] FXSA VE / FXRSTOR instructions
8000_0001h EDX[FFXSR] EDX[25] Hardware optimizations for FXSA VE / FXRSTOR
0000_0001h ECX[XSA VE] ECX[26] XSA VE / XRSTOR instructions
0000_000Dh
ECX=01hEAX[XSA VEOPT] EAX[0] XSA VEOPT
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11.3 Enabling SSE Instructions
Use of the 256-bit and 128-bit media instructions by application software requires system software 
support. System software must determine which SSE subsets are supported, enable those that are to be used, and supply code to handle the various exceptions that may occur during the execution of these instructions. The legacy SSE instructions and the extended SSE instructions often require unique exception handling.
11.3.1  Enabling Legacy SSE Instruction Execution
When legacy SSE instructions are supported, system software must set CR4.OSFXSR to let the 
processor know that the software supports the FXSA VE/FXRSTOR instructions. When the processor detects CR4.OSFXSR = 1, it allows execution of the legacy SSE instructions. If system software does not set CR4.OSFXSR, any attempt to execute these instructions causes an invalid-opcode exception (#UD). System software must also clear the CR0.EM (emulate coprocessor) bit to 0, otherwise an 
attempt to execute a legacy SSE instruction causes a #UD exception. An attempt to execute either FXSA VE or FXRSTOR when CR0.EM is set results in a #NM exception.
System software should also set the CR0.MP (monitor coprocessor) bit to 1. When CR0.EM=0 and 
CR0.MP=1, all media instructions, x87 instructions, and the FWAIT/WAIT instructions cause a 
device-not-available exception (#NM) when the CR0.TS bit is set. System software can use the #NM exception to perform lazy context switching, saving and restoring media and x87 state only when necessary after a task switch. See “CR0 Register” on page 41 for more information.
11.3.2  Enabling Extended SSE Instruction Execution
After the steps specified above are completed to enable legacy SSE instruction execution, additional 
steps are required to enable the extended SSE instructions and state management. System software must carry out the following process:
•Confirm that the hardware supports the XSA VE, XRSTOR, XSETBV , and XGETBV instructions 
and the XCR0 register (XFEATURE_ENABLED_MASK) by executing the CPUID instruction function 0000_0001h. If CPUID Fn0000_0001_ECX[XSA VE] is set, hardware support is verified.
•Optionally confirm hardware support of the XSA VEOPT instruction by executing CPUID function 0000_000Dh, sub-function 1 (ECX = 1). If CPUID Fn0000_000D_EAX_x1[XSA VEOPT] is set, the processor supports the XSA VEOPT instruction. XSA VEOPT is a performance optimized version of XSA VE.

•Confirm that hardware supports the extended SSE instructions by verifying XFeatureSupportedMask[2:0] = 111b. XFeatureSupportedMask is accessed via the CPUID instruction function 0000_000Dh, sub-function 0 (ECX = 0). XFeatureSupportedMask[31:0] is returned in the EAX register. 
If CPUID Fn0000_000D_EAX_x0[2:0] = 111b, hardware supports x87, legacy SSE, and extended
SSE instructions. Bit 0 of EAX signifies x87 floating-point and MMX support, bit 1 signifieslegacy SSE support, and bit 2 signifies extended SSE support. Support for both x87 and legacySSE instructions are required for processors that support the extended SSE instructions.
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•Set CR4[OSXSA VE] (bit 18) to enable the use of the XSETBV and XGETBV instructions. 
XSETBV is a privileged instruction that writes the XCRn registers. XCR0 is the XFEATURE_ENABLED_MASK used to manage media and x87 processor state using the XSA VE, XSA VEOPT, and XRSTOR instructions.
•Enable the x87/MMX, legacy SSE, and extended SSE instructions and processor state management by setting the x87, SSE, and YMM bits of XCR0 (XFEATURE_ENABLED_MASK). This is done via the privileged instruction XSETBV . Enabling extended SSE capabilities without enabling legacy SSE capabilities is not allowed. The x87 flag (bit 0) of the XFEATURE_ENABLED_MASK must be set when writing XCR0.
•Determine the XSA VE/XRSTOR memory save area size requirement. The field XFeatureEnabledSizeMax specifies the size requirement in bytes based on the currently enabled extended features and is returned in the EBX register after execution of CPUID Function 0000_000Dh, sub-function 0 (ECX = 0).
•Allocate the save/restore area based on the information obtained in the previous step.
For a detailed description of the XSETBV and XGETBV instructions, see individual instruction reference pages in V olume 4. See the section entitled “XFEATURE_ENABLED_MASK” in V olume 4 for details on the field definitions for XFEATURE_ENABLED_MASK.
For more information on using the CPUID instruction to obtain processor feature information, see 
Section 3.3, “Processor Feature Identification,” on page 71.
11.3.3  SIMD Floating-Point Exception Handling
System software must supply an exception handler if unmasked SSE floating-point exceptions are 
allowed to occur. When an unmasked exception is detected, the processor transfers control to the SIMD floating-point exception (#XF) handler provided by the operating system. System software must let the processor know that the #XF handler is available by setting CR4.OSXMMEXCPT to 1. If this bit is set to 1, the processor transfers control to the #XF handler when it detects an unmasked exception, otherwise a #UD exception occurs. When the processor detects a masked exception, it handles it in a default manner regardless of the CR4.OSXMMEXCPT value.
11.4 Media and x87 Processor State
The media and x87 processor state includes the contents of the registers used by SSE, MMX, and x87 instructions. System software that supports such applications must be capable of saving and restoring these registers.
11.4.1  SSE Execution Unit State
Figure 11 -1 shows the registers whose contents are affected by execution of SSE instructions. These 
include:
•YMM/XMM0–15—Sixteen 256-bit/128-bit SSE registers. In legacy and compatibility modes, 
software access is limited to the first eight registers.
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•MXCSR—The 32-bit Media eXtensions Control and Status Register.
All of these registers are visible to application software. Refer to “Streaming SIMD Extensions Media 
and Scientific Programming” in V olume 1 for more information on these registers.
Figure 11-1. SSE Execution Unit State
11.4.2  MMX Execution Unit State
Figure 11 -2 on page 346 shows the register contents that are affected by execution of 64-bit media 
instructions. These registers include:
•mmx0–mmx7 —Eight 64-bit media registers.
•FSW—Two fields (TOP and ES) in the 16-bit x87 status word register.513-314 ymm.eps255 127 0
YMM0
YMM1YMM2YMM3YMM4YMM5YMM6YMM7YMM8YMM9
YMM10
YMM11
YMM12YMM13YMM14YMM15XMM0XMM1XMM2XMM3XMM4XMM5XMM6XMM7XMM8XMM9
XMM10
XMM11
XMM12XMM13XMM14XMM15
Available in all modes
Available only in 64-bit mode31 0MXCSR Media eXtension Control and Status Register
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•FTW —The 16-bit x87 tag word.
Figure 11-2. MMX Execution Unit State
The 64-bit media instructions and x87 floating-point instructions share the same physical data 
registers. Figure 11 -2 shows how the 64-bit registers (MMX0–MMX7) are aliased onto the low 64 bits 
of the 80-bit x87 floating-point physical data registers (FPR0–FPR7). Refer to “64-Bit Media Programming” in V olume 1 for more information on these registers.
Of the registers shown in Figure 11 -2, only the eight 64-bit MMX registers are visible to 64-bit media 
application software. The processor maintains the contents of the two fields of the x87 status word—
top-of-stack-pointer (TOP) and exception summary (ES)—and the 16-bit x87 tag word during execution of 64-bit media instructions, as described in “Actions Taken on Executing 64-Bit Media Instructions” in V olume 1. 
64-bit media instructions do not generate x87 floating-point exceptions, nor do they set any status 
flags. However, 64-bit media instructions can trigger an unmasked floating-point exception caused by a previously executed x87 instruction. 64-bit media instructions do this by reading the x87 FSW.ES bit to determine whether such an exception is pending. 
11.4.3  x87 Execution Unit State
Figure 11 -3 on page 348 shows the registers whose contents are affected by execution of x87 floating-
point instructions. These registers include:MMX Registers
79 0
MMX0
MMX1MMX2MMX3MMX4MMX5MMX6MMX7
0 1563 64
FPR0FPR1FPR2FPR3FPR4FPR5FPR6FPR7
FSW
ES TOP
FTW x87 Tag Wordx87 Status WordVisible to application 
software
Written by processor 
hardware
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•fpr0–fpr7 —Eight 80-bit floating-point physical registers.
•FCW —The 16-bit x87 control word register.
•FSW—The 16-bit x87 status word register.
•Last x87 Instruction Pointer —This value is a pointer (32-bit, 48-bit, or 64-bit, depending on 
effective operand size and mode) to the last non-control x87 floating-point instruction executed. 
•Last x87 Data Pointer —The pointer (32-bit, 48-bit, or 64-bit, depending on effective operand size 
and mode) to the data operand referenced by the last non-control x87 floating-point instruction 
executed, if that instruction referenced memory; if it did not, then this value is implementation dependent.
•Last x87 Opcode—An 11-bit permutation of the instruction opcode from the last non-control x87 floating-point instruction executed.
Of the registers shown in Figure 11 -3 on page 348, only FPR0–FPR7, FCW, and FSW are directly 
updated by x87 application software. The processor maintains the contents of the FTW, instruction and data pointers, and opcode registers during execution of x87 instructions. Refer to “Registers” in V olume 1 for more information on these registers. 
The 11-bit instruction opcode register holds a permutation of the two-byte instruction opcode from the 
last non-control x87 instruction executed by the processor. (For a definition of non-control x87 
instruction , see “Control” in Chapter 6 of V olume 1.) The opcode field is formed as follows:
•Opcode Register Field[10:8] = First x87 opcode byte[2:0].
•Opcode Register Field[7:0] = Second x87 opcode byte[7:0].
For example, the x87 opcode D9 F8h is stored in the opcode register as 001_1111_1000b. The low-order three bits of the first opcode byte, D9h (1101_1001b), are stored in opcode-register bits 10:8. The second opcode byte, F8h (1111_1000b), is stored in bits 7:0 of the opcode register. The high-order five bits of the first opcode byte (1101_1b) are not needed because they are identical for all x87 instructions. 
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Figure 11-3. x87 Execution Unit State
11.4.4  Saving Media and x87 Execution Unit State
In most cases, operating systems, exception handlers, and device drivers should save and restore the 
media and/or x87 processor state between task switches or other interventions in the execution of 128-bit, 64-bit, or x87 procedures. Application programs are also free to save and restore state at any time.
In general, system software should use the FXSA VE and FXRSTOR instructions to save and restore

In general, system software should use the FXSA VE and FXRSTOR instructions to save and restore 
the entire media and x87 processor state. The FSA VE/FNSA VE and FRSTOR instructions can be used for saving and restoring the x87 state. Because the 64-bit media registers are physically aliased onto the x87 registers, the FSA VE/FNSA VE and FRSTOR instructions can also be used to save and restore the 64-bit media state. However, FSA VE/FNSA VE and FRSTOR do not save or restore the 128-bit media state.Tag WordStatus WordControl Wordx87 Floating-Point Registers
79 0
FPR0
FPR1FPR2FPR3FPR4FPR5FPR6FPR7
0 15
63
0 10Last x87 Instruction Pointer
Last x87 Data Pointer
OpcodeFCW
FSW
FTW x87 Tag Wordx87 Status Wordx87 Control Word
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11.4.4.1  FSAVE/FNSAVE and FRSTOR Instructions
The FSA VE/FNSA VE and FRSTOR instructions save and restore the entire register state for 64-bit 
media instructions and x87 floating-point instructions. The FSA VE instruction stores the register state, but only after handling any pending unmasked-x87 floating-point exceptions. The FNSA VE instruction stores the register state but skips the reporting and handling of these exceptions. The state of all MMX/FPR registers is saved, as well as all other x87 state (the control word register, status word register, tag word, instruction pointer, data pointer, and last opcode). After saving this state, the tag state for all MMX/FPR registers is changed to empty  and is thus available for a new procedure. 
Starting on page 350, Figure 11 -4 through Figure 11 -7 show the memory formats used by the 
FSA VE/FNSA VE and FRSTOR instructions when storing the x87 state in various processor modes and using various effective-operand sizes. This state includes:
•x87 Data Registers
- FPR0–FPR7 80-bit physical data registers.
•x87 Environment- FCW: x87 control word register- FSW: x87 status word register- FTW: x87 tag word- Last x87 instruction pointer- Last x87 data pointer- Last x87 opcode
The eight data registers are stored in the 80 bytes following the environment information. Instead of 
storing these registers in their physical order (FPR0–FPR7), the processor stores the registers in the their stack order, ST(0)–ST(7), beginning with the top-of-stack, ST(0).
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Figure 11 -4. FSAVE/FNSAVE Image (32-Bit, Protected Mode)Bit Offset Byte
Offset 31 16 15 0
ST(7)[79:48] +68h
¼ ¼
ST(1)[15:0] ST(0)[79:64] ¼
ST(0)[63:32] ¼
ST(0)[31:0] +1Ch
Reserved, IGN Data DS Selector[15:0] +18h
Data Offset[31:0] +14h
00000b Instruction Opcode[10:0] Instruction CS Selector[15:0] +10h
Instruction Offset[31:0] +0Ch
Reserved, IGN x87 Tag Word (FTW) +08h
Reserved, IGN x87 Status Word (FSW) +04h
Reserved, IGN x87 Control Word (FCW) +00h
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Figure 11-5. FSAVE/FNSAVE Image (32-Bit, Real/Virtual-8086 Modes)Bit Offset Byte
¼ ¼
0000b Data Offset[3:16] 0000 0000 0000b +18h
Reserved, IGN Data Offset[15:0] +14h
0000b Instruction Offset[31:16] 0 Instruction Opcode[10:0] +10h
Reserved, IGN Instruction Offset[15:0] +0Ch
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Figure 11 -6. FSAVE/FNSAVE Image (16-Bit, Protected Mode)Bit Offset Byte
Not Part of x87 State ST(7)[79:64] +5Ch
¼ ¼
ST(0)[79:48] +14h
ST(0)[47:16] +10h
ST(0)[15:0] Data DS Selector[15:0] +0Ch
Data Offset[15:0] Instruction CS Selector[15:0] +08h
Instruction Offset[15:0] x87 Tag Word (FTW) +04h
x87 Status Word (FSW) x87 Control Word (FCW) +00h
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Figure 11-7. FSAVE/FNSAVE Image (16-Bit, Real/Virtual-8086 Modes)
11.4.4.2  FLDENV/FNLDENV and FSTENV Instructions
The FLDENV/FNLDENV and FSTENV instructions load and store only the x87 floating-point 
environment. These instructions, unlike the FSA VE/FNSA VE and FRSTOR instructions, do not save or restore the x87 data registers. The FLDENV/FSTENV instructions do not save the full 64-bit data and instruction pointers. 64-bit applications should use FXSA VE/FXRSTOR, rather than FLDENV/FSTENV . The format of the saved x87 environment images for protected mode and real/virtual mode are the same as those of the first 14-bytes of the FSA VE/FNSA VE images for 16-bit operands or 32/64-bit operands, respectively. See Figure 11 -4 on page 350, Figure 11 -5 on page 351, 
Figure 11 -6 on page 352, and Figure 11 -7.Bit Offset Byte
¼ ¼
ST(0)[15:0]Data
[19:16]0000 0000 0000b +0Ch
Data Offset [15:0]Instruction
[19:16]0 Instruction Opcode[10:0] +08h
Instruction Offset [15:0] x87 Tag Word (FTW) +04h
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11.4.4.3  FXSAVE and FXRSTOR Instructions
The FXSA VE and FXRSTOR instructions save and restore the entire 128-bit media, 64-bit media, and 
x87 state. These instructions usually execute faster than FSA VE/FNSA VE and FRSTOR because they do not normally save and restore the x87 exception pointers (last-instruction pointer, last data-operand pointer, and last opcode). The only case in which they do save the exception pointers is the relatively rare case in which the exception-summary bit in the x87 status word (FSW.ES) is set to 1, indicating that an unmasked exception has occurred. The FXSA VE and FXRSTOR memory format contains fields for storing these values.
Unlike FSA VE and FNSA VE, the FXSA VE instruction does not alter the x87 tag word. Therefore, the 
contents of the shared 64-bit MMX and 80-bit FPR registers can remain valid after an FXSA VE instruction (or any other value the tag bits indicated before the save). Also, FXSA VE (like FNSA VE) does not check for pending unmasked-x87 floating-point exceptions. 
Figure 11 -9 on page 360 shows the memory format of the media x87 state in long mode. If a 32-bit 
operand size is used in 64-bit mode, the memory format is the same, except that RIP and RDS are 
stored as sel:offset  pointers, as shown in Figure 11 -10 on page 361.
For more information on the FXSA VE and FXRSTOR instructions, see individual instruction listings in “64-Bit Media Instruction Reference” of V olume 5.
11.5 XSAVE/XRSTOR Instructions
The XSAVE, XSAVEOPT, XRSTOR, XGETBV, and XSETBV instructions and associated datastructures extend the FXSAVE/FXRSTOR memory image used to manage processor states andprovide additional functionality. These instructions do not obviate the FXSAVE/FXRSTORinstructions. For more information about FXSAVE/FXRSTOR, see “FXSAVE and FXRSTOR
Instructions” in Volume 2 . For detailed descriptions of FXSAVE and FXRSTOR, see individual
instruction listings in AMD64 Architecture Programmer’s Manual “Volume 5: 64-Bit Media and x87
Floating-Point Instructions.”
The CPUID instruction is used to identify features supported in processor hardware. Extended control
registers are used to enable and disable the handling of processor states associated with supportedhardware features and to communicate to an application whether an operating system supports aparticular feature that has a processor state specific to it.
11.5.1 CPUID Enhancements
•CPUID Fn0000_00001_ECX[XSA VE] indicates that the processor supports XSA VE/XRSTOR instructions and at least one XCR.
•CPUID Fn0000_00001_ECX[OSXSA VE] indicates whether the operating system has enabled extensible state management and supports processor extended state management.
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•CPUID Fn0000_0000D enumerates processor states (including legacy x87 FPU states, SSE states, 
and processor extended states), the offset, and the size of the save area for each processor extended state. Sub-functions (ECX > 0) provide details concerning features and support of processor states enumerated in the root function.
11.5.2 XFEATURE_ENABLED_MASK 
XFEATURE_ENABLED_MASK is set up by privileged software to enable the saving and restoring of extended processor architectural state information supported by a specific processor. Clearing defined bit fields in this mask inhibits the XSA VE instruction from saving (and XRSTOR from restoring) this state information. 
XFEATURE_ENABLED_MASK is addressed as XCR0 in the extended control register space and is 
accessed via the XSETBV and XGETBV instructions.
XFEATURE_ENABLED_MASK is defined as follows:
Figure 11-8. XFEATURE_ENABLED_MASK Format63 62 61  13 12 11 10 9 8 3 2 1 0X
LWP Reserved
CET_S
CET_U
RSVD
MPKReserved
YMM
SSE
x87
63 XReserved specifically for XCR0 bit vector 
expansion.MBZ
62 LWPWhen set, Lightweight Profiling (LWP) extensions are enabled and XSA VE/XRSTOR supports LWP state management.
R/W
61:13 Reserved   MBZ
12 CET_SWhen set, CET supervisor state is supported by XSA VE/XRSTORR/W
11 CET_UWhen set, CET user state is supported by XSA VE/XRSTOR R/W
10 Reserved MBZ
9 MPKWhen set, PKRU state management is supported by XSA VE/XRSTOR. R/W
8:3 Reserved ,MBZ

CET_S
CET_U
RSVD
YMM
SSE
x87
R/W
8:3 Reserved ,MBZ 
2 YMMWhen set, 256-bit SSE state management is supported by XSA VE/XRSTOR.Must be set to enable A VX extensions.
R/W
1 SSEWhen set, 128-bit SSE state management is supported by XSA VE/XRSTOR. This bit must be set if YMM is set.Must be set to enable A VX extensions.
R/W
0 x87x87 FPU state management is supported by XSA VE/XRSTOR. Must be set to 1.R/W
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Hardware initializes XCR0 to 0000_0000_0000_0001h. On writing this register, software must insure 
that XCR0[63:3] is clear, XCR0[0] is set, and that XCR0[2:1] is not equal to 10b. An attempt to write data that violates these rules results in a #GP.
11.5.3 Extended Save Area
The XSA VE/XRSTOR save area extends the legacy 512-byte FXSA VE/FXRSTOR memory image to provide a compatible register state management environment as well as an upward migration path. The save area is architecturally defined to be extendable and enumerated by the sub-functions of CPUID Fn 0000_000Dh. Figure 11 -6 shows the format of the XSA VE/XRSTOR area.
The register fields of the first 512 bytes of the XSA VE/XRSTOR area are the same as those of the FXSA VE/FXRSTOR area, but the 512-byte area is organized as x87 FPU states, MXCSR (including MXCSR_MASK), and XMM registers. The layout of the save area is fixed and may contain non-contiguous individual save areas because a processor does not support certain extended states or because system software does not support certain processor extended states. The save area is not compacted when features are not saved or are not supported by the processor or by system software.
For more information on using the CPUID instruction to obtain processor implementation 
information, see Section 3.3, “Processor Feature Identification,” on page 71.
11.5.4 Instruction Functions
CR4.OSXSA VE and XCR0 can be read at all privilege levels but written only at ring 0.
•XGETBV reads XCR0.
•XSETBV writes XCR0, ring 0 only.
•XRSTOR restores states specified by bitwise AND of a mask operand in EDX:EAX with XCR0.
•XSA VE (and XSA VEOPT) saves states specified by bitwise AND of a mask operand in 
EDX:EAX with XCR0.Table 11 -6. Extended Save Area Format
Save Area Offset (Byte) Size (Bytes)
FPU/SSE Save Area 0 512
Header 512 64
Reserved, (Ext_Save_Area_2) CPUID Fn 0000_000D_EBX_x02 CPUID Fn 0000_000D_EAX_x02
Reserved, (Ext_Save_Area_3) CPUID Fn 0000_000D_EBX_x03 CPUID Fn 0000_000D_EAX_x03Reserved, (Ext_Save_Area_4) CPUID Fn 0000_000D_EBX_x04 CPUID Fn 0000_000D_EAX_x04
Reserved, (…) … …
Note: Bytes 464–511 are available for software use. XRSTOR ignores bytes 464–511 of an XSAVE image.
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11.5.5 YMM States and Supported Operating Modes
Extended instructions operate on YMM states by means of extended (XOP/VEX) prefix encoding. 
When a processor supports YMM states, the states exist in all operating modes, but interfaces to access the YMM states may vary by mode. Processor support for extended prefix encoding is independent of processor support of YMM states.
Instructions that use extended prefix encoding are generally supported in long and protected modes, 
but are not supported in real or virtual 8086 modes, or when entering SMM mode. Bits 255:128 of the YMM register state are maintained across transitions into and out of these modes. The XSA VE/XRSTOR instructions function in all operating modes; XRSTOR can modify YMM register state in any operating mode, using state information from the XSA VE/XRSTOR area.
11.5.6 Extended SSE Execution State Management
Operating system software must use the XSA VE/XRSTOR instructions for extended SSE execution state management. XSA VEOPT, a performance optimized version of XSA VE, may be used instead of XSA VE once the XSA VE/XRSTOR save area is initialized. In the following discussion XSA VEOPT may be substituted for the instruction XSA VE. The instructions also provide an interface to manage XMM/MXCSR states and x87 FPU states in conjunction with processor extended states. An operating system must enable extended SSE execution state management prior to the execution of extended SSE instructions. Attempting to execute an extended SSE instruction without enabling execution state management causes a #UD exception.
11.5.6.1  Enabling Extended SSE Instruction Execution
To enable extended SSE instruction execution and state management, system software must carry out 
the following process:
•Optionally confirm hardware support of the XSA VEOPT instruction by executing CPUID function 0000_000Dh, sub-function 1 (ECX = 1). If CPUID Fn0000_000D_EAX_x1[XSA VEOPT] is set, the processor supports the XSA VEOPT instruction. XSA VEOPT is a performance optimized version of XSA VE. (SDCR-3580)
•Confirm that hardware supports the extended SSE instructions by verifying XFeatureSupportedMask[2:0] = 111b. XFeatureSupportedMask is accessed via the CPUID instruction function 0000_000Dh, sub-function 0 (ECX = 0).
•Set CR4[OSXSA VE] (bit 18) to enable the use of the XSETBV and XGETBV instructions. XSETBV is a privileged instruction that writes the XCRn registers. XCR0 is the 
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XFEATURE_ENABLED_MASK used to manage media and x87 processor state using the 
XSA VE, XSA VEOPT, and XRSTOR instructions.
•Enable the x87/MMX, legacy SSE, and extended SSE instructions and processor state management by setting the x87, SSE, and YMM bits of XCR0 (XFEATURE_ENABLED_MASK). Enabling extended SSE capabilities without enabling legacy SSE capabilities is not allowed. The x87 flag (bit 0) of the XFEATURE_ENABLED_MASK must be set when writing XCR0.
•Determine the XSA VE/XRSTOR memory save area size requirement. The field XFeatureEnabledSizeMax specifies the size requirement in bytes based on the currently enabled extended features and is returned in the EAX register after execution of CPUID Function 0000_000Dh, sub-function 0 (ECX = 0).
For more information on the XSETBV and XGETBV instructions, see individual instruction descriptions in V olume 4. XFEATURE_ENABLED_MASK fields are defined in Section 11.5.2 above.
11.5.7 Saving Processor State
The XSTATE header starts at byte offset 512 in the save area. XSTATE_BV is the first 64-bit field in the header. The order of bit vectors in XSTATE_BV matches the order of bit vectors in XCR0. The XSA VE instruction sets bits in the XSTATE_BV vector field when it writes the corresponding processor extended state to a save area in memory. XSA VE modifies only bits for processor states specified by bitwise AND of the XSA VE bit mask operand in EDX:EAX with XCR0. If software modifies the save area image of a particular processor state component directly, it must also set the corresponding bit of XSTATE_BV . If the bit is not set, directly modified state information in a save area image may be ignored by XRSTOR.
XSA VEOPT, a performance optimized version of the XSA VE instruction, may be used (if supported) 
in lieu of the XSA VE instruction once the XSA VE/XRSTOR save area has been initialized via the execution of the XSA VE instruction.
11.5.8 Restoring Processor State
When XRSTOR is executed, processor state components are updated only if the corresponding bits in the mask operand (EDX:EAX) and XCR0 are both set. For each updated component, when the corresponding bit in the XSTATE_BV field in the save area header is set, the component is loaded 
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from the save area in memory. When the XSTATE_BV bit is cleared, the state is set to the hardware-
specified initial values shown in Table 11 -7.
11.5.9 MXCSR State Management
The MXCSR has no hardware-specified initial state; it is read from the save area in memory whenever either XMM or YMM_HI are updated. 
11.5.10 Mode-Specific XSAVE/XRSTOR State Management
Some state is conditionally saved or updated, depending on processor state:
•On processors where CPUID Fn8000_0008_EBX[2] is 0, the x87 error pointers are not saved or

•On processors where CPUID Fn8000_0008_EBX[2] is 0, the x87 error pointers are not saved or 
restored if the state saved or loaded from memory doesn't have a pending #MF. On processors where CPUID Fn8000_0008_EBX[2] is 1, the error pointers are always restored from the save area (and if in 64-bit mode the CS and DS portions of the error pointer registers are zeroed), and the error pointer fields in the save area are zeroed if there is no pending #MF, else the error pointer offset registers are written to the save area. 
•XMM8–XMM15 are not saved or restored in non 64-bit mode.
•YMM_HI8–YMM_HI15 are not saved or restored in non 64-bit mode.Table 11-7. XRSTOR Hardware-Specified Initial Values
Component Initial Value
x87 FCW = 037Fh
FSW = 0000h
Empty/Full = 00h (FTW = FFFFh)
x87 Error Pointers = 0
ST0 - ST7 = 0
 XMM XMM0 - XMM15 = 0, if 64-bit mode
XMM0 - XMM7 = 0, if !64-bit mode
YMM_HI YMM_HI0 -Y MM_HI15 = 0, if 64-bit mode
YMM_HI0-YMM_HI7 = 0, if !64-bit mode
LWP LWP disabled
MPK PKRU = 0 
CET_S PL0_SSP = PL1_SSP = PL2_SSP = 0
CET_U U_CET = 0, PL3_SSP = 0
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Figure 11-9. FXSAVE and FXRSTOR Image (64-bit Mode)F E D C B A 9 8 7 6 5 4 3 2 1 0 Byte
Reserved, IGN +1F0h
¼ 
Reserved, IGN +1A0h
XMM15 +190h
XMM14 +180h
XMM13 +170h
XMM12 +160h
XMM11 +150h
XMM10 +140h
XMM9 +130h
XMM8 +120h
XMM7 +110h
XMM6 +100h
XMM5 +F0h
XMM4 +E0h
XMM3 +D0h
XMM2 +C0h
XMM1 +B0h
XMM0 +A0h
Reserved, IGN ST(7) +90h
Reserved, IGN ST(6) +80h
Reserved, IGN ST(5) +70h
Reserved, IGN ST(4) +60h
Reserved, IGN ST(3) +50h
Reserved, IGN ST(2) +40h
Res
erv
ed, 
IG
NST(1) +30h
Reserved, IGN ST(0) +20h
MXCSR_MASK MXCSR RDP1 +10h
RIP1 FOP 0 FTW FSW FCW +00h
1. Stored as sel:offset if operand size is 32 bits. 32bit sel:offset format of the pointers is shown in figure 11 -10.
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Figure 11-10. FXSAVE and FXRSTOR Image (Non-64-bit Mode)
Software can read and write all fields within the FXSA VE and FXRSTOR memory image. These 
fields include:
•FCW —Bytes 01h–00h. x87 control word.
•FSW—Bytes 03h–02h. x87 status word.
•FTW —Byte 04h. x87 tag word. See “FXSA VE Format for x87 Tag Word” on page 362 for 
additional information on the FTW format saved by the FXSA VE instruction. 
•(Byte 05h contains the value 00h.)
•FOP —Bytes 07h–06h. last x87 opcode.
•Last x87 Instruction Pointer —A pointer to the last non-control x87 floating-point instruction 
executed by the processor:F E D C B A 9 8 7 6 5 4 3 2 1 0 Byte
¼ 
Reserved, IGN +120h
XMM7 +110h
XMM6 +100h
XMM5 +F0h
XMM4 +E0h
XMM3 +D0h
XMM2 +C0h
XMM1 +B0h
XMM0 +A0h
Reserved, IGN ST(1) +30h
MXCSR_MASK MXCSR rsrvd, IGN DS DP +10h
rsrvd, IGN CS EIP FOP 0 FTW FSW FCW +00h
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-RIP (64-bit format) —Bytes 0Fh–08h. 64-bit offset into the code segment (used without a CS 
selector).
-EIP (32-bit format) —Bytes 0Bh–08h. 32-bit offset into the code segment. 
-CS (32-bit format) —Bytes 0Dh–0Ch. Segment selector portion of the pointer. 
•Last x87 Data Pointer —If the last non-control x87 floating point instruction referenced memory, 
this value is a pointer to the data operand referenced by the last non-control x87 floating-point 
instruction executed by the processor:
-RDP (64-bit format) —Bytes 17h–10h. 64-bit offset into the data segment (used without a DS 
-DP (32-bit format)—Bytes 13h–10h. 32-bit offset into the data segment.
-DS (32-bit format) —Bytes 15h–14h. Segment selector portion of the pointer.
If the last non-control x87 instruction did not reference memory, then the value in the pointer is
implementation dependent.
•MXCSR —Bytes 1Bh–18h. 128-bit media-instruction control and status register. This register is 
saved only if CR4.OSFXSR is set to 1.
•MXCSR_MASK —Bytes 1Fh–1Ch. Set bits in MXCSR_MASK indicate supported feature bits in 
MXCSR. For example, if bit 6 (the DAZ bit) in the returned MXCSR_MASK field is set to 1, the DAZ mode and the DAZ flag in MXCSR are supported. Cleared bits in MXCSR_MASK indicate 
reserved bits in MXCSR. If software attempts to set a reserved bit in the MXCSR register, a #GP exception will occur. To avoid this exception, after software clears the FXSA VE memory image and executes the FXSA VE instruction, software should use the value returned by the processor in the MXCSR_MASK field when writing a value to the MXCSR register, as follows:
-MXCSR_MASK = 0:  If the processor writes a zero value into the MXCSR_MASK field, the 
denormals-are-zeros (DAZ) mode and the DAZ flag in MXCSR are not supported. Software 
should use the default mask value, 0000_FFBFh (bit 6, the DAZ bit, and bits 31:16 cleared to 
0), to mask any value it writes to the MXCSR register to ensure that all reserved bits in MXCSR are written with 0, thus avoiding a #GP exception. 
-MXCSR_MASK  0: If the processor writes a non-zero value into the MXCSR_MASK field, 
software should AND this value with any value it writes to the MXCSR register.
•MMXn/FPRn—Bytes 9Fh–20h. Shared 64-bit media and x87 floating-point registers. As in the case of the x87 FSA VE instruction, these registers are stored in stack order ST(0)–ST(7). The upper six bytes in the memory image for each register are reserved.
•XMMn—Bytes 11Fh–A0h. 128-bit media registers. These registers are saved only if CR4.OSFXSR is set to 1.
11.5.10.1  FXSAVE Format for x87 Tag Word
Rather than saving the entire x87 tag word, FXSA VE saves a single-byte encoded version. FXSA VE encodes each of the eight two-bit fields in the x87 tag word as follows:
•Two-bit values of 00, 01, and 10 are encoded as a 1, indicating the corresponding x87 FPRn 
register holds a value.
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•A two-bit value of 11 is encoded as a 0, indicating the corresponding x87 FPR n is empty.
For example, assume an FSA VE instruction saves an x87 tag word with the value 83F1h. This tag-
word value describes the x87 FPRn contents as follows:
When an FXSA VE is used to write the x87 tag word to memory, it encodes the value as E3h. This 
encoded version describes the x87 FPRn contents as follows:
If necessary, software can decode the single-bit FXSA VE tag-word fields into the two-bit field FSA VE 
uses by examining the contents of the corresponding FPR registers saved by FXSA VE. Table 11 -8 on 
page 364 shows how the FPR contents are used to find the equivalent FSA VE tag-field value. The fraction column refers to fraction portion of the extended-precision significand (bits 62:0). The integer 
bit column refers to the integer-portion of the significand (bit 63). See Chapter 11, “SSE, MMX, and 
x87 Programming,” on page 341 for more information on floating-point numbering formats.x87 Register FPR7 FPR6 FPR5 FPR4 FPR3 FPR2 FPR1 FPR0
Tag Word Value (hex) 8 3 F 1
Tag Value (binary) 10 00 00 11 11 11 00 01
Meaning Special Valid Valid Empty Empty Empty Valid Zero
x87 Register FPR7 FPR6 FPR5 FPR4 FPR3 FPR2 FPR1 FPR0
Encoded Tag Byte (hex) E 3
Tag Value (binary) 1 1 1 0 0 0 1 1
Meaning Valid Valid Valid Empty Empty Empty Valid Valid
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11.5.10.2  Performance Considerations
When system software supports multi-tasking, it must be able to save the processor state for one task 
and load the state for another. For performance reasons, the media and/or x87 processor state is usually saved and loaded only when necessary. System software can save and load this state at the time a task switch occurs. However, if the new task does not use the state, loading the state is unnecessary and reduces performance.
The task-switch bit (CR0.TS) is provided as a lazy context-switch mechanism that allows system 
software to save and load the processor state only when necessary. When CR0.TS=1, a device-not-
available exception (#NM) occurs when an attempt is made to execute a 128-bit media, 64-bit media, or x87 instruction. System software can use the #NM exception handler to save the state of the previous task, and restore the state of the current task. Before returning from the exception handler to the media or x87 instruction, system software must clear CR0.TS to 0 to allow the instruction to be executed. Using this approach, the processor state is saved only when the registers are used.
In legacy mode, the hardware task-switch mechanism sets CR0.TS=1 during a task switch (see “Task

In legacy mode, the hardware task-switch mechanism sets CR0.TS=1 during a task switch (see “Task 
Switched (TS) Bit” on page 43 for more information). In long mode, the hardware task-switching is not supported, and the CR0.TS bit is not set by the processor. Instead, the architecture assumes that system software handles all task-switching and state-saving functions. If CR0.TS is to be used in long mode for controlling the save and restore of media or x87 state, system software must set and clear it explicitly.Table 11-8. Deriving FSAVE Tag Field from FXSAVE Tag Field
Encoded
FXSA VE 
Tag FieldExponent Integer Bit2Fraction1 Type of ValueEquivalent
FSA VE
Tag Field
1 (Valid)All 0s0 All 0s Zero 01 (Zero)
0 Not all 0s Denormal
10 (Special)1 All 0sPseudo Denormal1 Not all 0s
Neither 
all 0s 
nor all 1s0
don’t careUnnormal
1 Normal 00 (Valid)
All 1s0Pseudo Infinity
or Pseudo NaN
10 (Special)
1All 0s Infinity
Not all 0s NaN
0 (Empty) don’t care Empty 11 (Empty)
Note(s):
1. Bits 62:0 of the significand. Bit 62, the most-significant bit of the fraction, is also called the M bit.
2. Bit 63 of the significand, also called the J bit.
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12 Task Management
This chapter describes the hardware task-management features. All of the legacy x86 task-
management features are supported by the AMD64 architecture in legacy mode, but most features are not available in long mode. Long mode, however, requires system software to initialize and maintain certain task-management resources . The details of these resource-initialization requirements for long 
mode are discussed in “Task-Management Resources” on page 366.
12.1 Hardware Multitasking Overview
A task (also called a process ) is a program that the processor can execute, suspend, and later resume 
executing at the point of suspension. During the time a task is suspended, other tasks are allowed to execute. Each task has its own execution space, consisting of: 
•Code segment and instruction pointer.
•Data segments.
•Stack segments for each privilege level.
•General-purpose registers.
•rFLAGS register.
•Local-descriptor table.
•Task register, and a link to the previously-executed task.
•I/O-permission and interrupt-permission bitmaps.
•Pointer to the page-translation tables (CR3).
The state information defining this execution space is stored in the task-state segment (TSS) 
maintained for each task.
Support for hardware multitasking is provided in legacy mode. Hardware multitasking provides 
automated mechanisms for switching tasks, saving the execution state of the suspended task, and restoring the execution state of the resumed task. When hardware multitasking is used to switch tasks, the processor takes the following actions:
•Suspends execution of the task, allowing any executing instructions to complete and save their
results.
•Saves the task execution state in the task TSS.
•Loads the execution state for the new task from its TSS.
•Begins executing the new task at the location specified in the new task TSS.
Software can switch tasks by branching to a new task using the CALL or JMP instructions. Exceptions and interrupts can also switch tasks if the exception or interrupt handlers are themselves separate tasks. IRET can be used to return to an earlier task.
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12.2 Task-Management Resources
The hardware-multitasking features are available when protected mode is enabled (CR0.PE=1). 
Protected-mode software execution, by definition, occurs as part of a task. While system software is not required to use the hardware-multitasking features, it is required to initialize certain task-management resources for at least one task (the current task) when running in protected mode. This single task is needed to establish the protected-mode execution environment. The resources that must be initialized are:
•Task-State Segment (TSS)—A segment that holds the processor state associated with a task.
•TSS Descriptor —A segment descriptor that defines the task-state segment.
•TSS Selector —A segment selector that references the TSS descriptor located in the GDT.
•Task Register —A register that holds the TSS selector and TSS descriptor for the current task.
Figure 12 -1 on page 367 shows the relationship of these resources to each other in both 64-bit and 32-
bit operating environments.
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Figure 12-1. Task-Management Resources
A fifth resource is available in legacy mode for use by system software that uses the hardware-
multitasking mechanism to manage more than one task:
•Task-Gate Descriptor —This form of gate descriptor holds a reference to a TSS descriptor and is
used to control access between tasks.
The task-management resources are described in the following sections.513-254.eps32-Bit Limit 64-Bit or 32-Bit Base Address AttributesTask Register (Hidden From Software)
0 15
TSS SelectorTask Register (Visible)Global-Descriptor
Table
TSS Descriptor
I/O-Bitmap Base AddressI/O-Permission Bitmap
Interrupt-Redirection BitmapTask-State Segment+
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12.2.1  TSS Selector
TSS selectors are selectors that point to task-state segment descriptors in the GDT. Their format is 
identical to all other segment selectors, as shown in Figure 12 -2. 
Figure 12-2. Task-Segment Selector
Selector Index.  Bits 15:3. The selector-index field locates the TSS descriptor in the global-descriptor 
table. 
Table Indicator (TI) Bit.  Bit 2. The TI bit must be cleared to 0, which indicates that the GDT is used. 
TSS descriptors cannot be located in the LDT. If a reference is made to a TSS descriptor in the LDT, a general-protection exception (#GP) occurs.
Requestor Privilege-Level (RPL) Field.  Bits 1:0. RPL represents the privilege level (CPL) the 
processor is operating under at the time the TSS selector is loaded into the task register.
12.2.2  TSS Descriptor
The TSS descriptor is a system-segment descriptor, and it can be located only in the GDT. The format 
for an 8-byte, legacy-mode and compatibility-mode TSS descriptor can be found in “System Descriptors” on page 94. The format for a 16-byte, 64-bit mode TSS descriptor can be found in 
“System Descriptors” on page 99.
The fields within a TSS descriptor (all modes) are described in “Descriptor Format” on page 88. The following additional information applies to TSS descriptors:
•Segment Limit —When shadow stacks are not enabled (CR4.CET=0), a TSS descriptor must have a
segment limit value of at least 67h, which defines a minimum TSS size of 68h (104 decimal) bytes.
If shadow stacks are enabled (CR4.CET=1), the TSS segment limit must be at least 06Bh (for aminimum size of 108 decimal bytes), in order to accommodate the 32-bit shadow stack pointer(SSP). If the limit is less than the specified values, an invalid-TSS exception (#TS) occurs during
the task switch. When an I/O-permission bitmap, interrupt-redirection bitmap, or additional stateinformation is included in the TSS, the limit must be set to a value large enough to enclose thatinformation. In this case, if the TSS limit is not large enough to hold the additional information, a15 3 2 1 0
Selector Index TI RPL
15:3 Selector Index
2 TI Table Indicator 
1:0 RPL Requestor Privilege Level
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#GP exception occurs when an attempt is made to access beyond the TSS limit. No check for the
larger limit is performed during the task switch.
•Type—Four system-descriptor types are defined as TSS types, as shown in Table 4-5 on page 94.Bit 9 is used as the descriptor busy bit (B). This bit indicates that the task is busy when set to 1, andavailable when cleared to 0. Busy tasks are the currently running task and any previous (outer)tasks in a nested-task hierarchy. Task recursion is not supported, and a #GP exception occurs if anattempt is made to transfer control to a busy task. See “Nesting Tasks” on page 386 for additional
In long mode, the 32-bit TSS types (available and busy) are redefined as 64-bit TSS types, and
only 64-bit TSS descriptors can be used. Loading the task register with an available 64-bit TSScauses the processor to change the TSS descriptor type to indicate a busy 64-bit TSS. Because longmode does not support task switching, the TSS-descriptor busy bit is never cleared by theprocessor to indicate an available 64-bit TSS.
Sixteen-bit TSS types are illegal in long mode. A general-protection exception (#GP) occurs if a
reference is made to a 16-bit TSS.
12.2.3  Task Register
The task register  (TR) points to the TSS location in memory, defines its size, and specifies its 
attributes. As with the other descriptor-table registers, the TR has two portions. A visible  portion holds 
the TSS selector, and a hidden  portion holds the TSS descriptor. When the TSS selector is loaded into 
the TR, the processor automatically loads the TSS descriptor from the GDT into the hidden portion of 
the TR.

the TR. 
The TR is loaded with a new selector using the LTR instruction. The TR is also loaded during a task 
switch, as described in “Switching Tasks” on page 379.
Figure 12 -3 shows the format of the TR in legacy mode.
Figure 12-3. TR Format, Legacy Mode
Figure 12 -4 shows the format of the TR in long mode (both compatibility mode and 64-bit mode).Hidden From Software513-221.eps32-Bit Descriptor-Table Limit
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Figure 12-4. TR Format, Long Mode
The AMD64 architecture expands the TSS-descriptor base-address field to 64 bits so that system 
software running in long mode can access a TSS located anywhere in the 64-bit virtual-address space. The processor ignores the 32 high-order base-address bits when running in legacy mode. Because the TR is loaded from the GDT, the system-segment descriptor format has been expanded to 16 bytes by the AMD64 architecture in support of 64-bit mode. See “System Descriptors” on page 99 for more 
information on this expanded format. The high-order base-address bits are only loaded from 64-bit mode using the LTR instruction. Figure 12 -5 shows the relationship between the TSS and GDT.
Figure 12-5. Relationship between the TSS and GDT
Long mode requires the use of a 64-bit TSS type, and this type must be loaded into the TR by executing the LTR instruction in 64-bit mode . Executing the LTR instruction in 64-bit mode loads the 
TR with the full 64-bit TSS base address from the 16-byte TSS descriptor format (compatibility mode Hidden From Software513-267.eps64-Bit Descriptor-Table Base Address32-Bit Descriptor-Table LimitDescriptor AttributesSelector
513-210.epsGlobal
Table
GDT Limit
GDT Base AddressTask Selector
TSS Attributes
TSS Limit
TSS Base AddressTask
State
Segment
Global Descriptor Table Register Task Register
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can only load 8-byte system descriptors). A processor running in either compatibility mode or 64-bit 
mode uses the full 64-bit TR.base address.
12.2.4  Legacy Task-State Segment
The task-state segment (TSS) is a data structure in memory that the processor uses to save and restore 
the execution state for a task when a task switch occurs. Figure 12 -6 on page 372 shows the format of 
a legacy 32-bit TSS.
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Figure 12 -6. Legacy 32-bit TSSBit Offset Byte 
I/O-Permission Bitmap (IOPB) (Up to 8 Kbytes)IOPB
Base
Interrupt-Redirection Bitmap (IRB) (Eight 32-Bit Locations)
-
¯Operati
ng-System Data Structure-
¯
SSP +68h
I/O-P
ermission Bitmap Base Address Reserved, IGN T +64h
Reserved, IGN LDT Selector +60h
Reserved, IGN GS +5Ch
Reserved, IGN FS +58h
Reserved, IGN DS +54h
Reserved, IGN SS +50h
Reserved, IGN CS +4Ch
Reserved, IGN ES +48h
EDI +44h
ESI +40h
EBP +3Ch
ESP +38h
EBX +34h
EDX +30h
ECX +2Ch
EAX +28h
EFLAGS +24h
EIP +20h
CR3 +1Ch
Reserved, IGN SS2 +18h
ESP2 +14h
Reserved, IGN SS1 +10h
ESP1 +0Ch
Reserved, IGN SS0 +08h
ESP0 +04h
Reserved, IGN Link (Prior TSS Selector) +00h
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The 32-bit TSS contains three types of fields:
•Static fields are read by the processor during a task switch  when a new task is loaded, but are not
written by the processor when a task is suspended.
•Dynamic fields  are read by the processor during a task switch when a new task is loaded, and are
•Software-defined fields are read and written by software, but are not read or written by the
processor. All but the first 104 bytes of a TSS can be defined for software purposes, minus anyadditional space required for the optional I/O-permission bitmap and interrupt-redirection bitmap.
TSS fields are not read or written by the processor when the LTR instruction is executed. The LTR instruction loads the TSS descriptor into the TR and marks the task as busy, but it does not cause a task switch.
The TSS fields used by the processor in legacy mode are:
•Link—Bytes 01h–00h, dynamic field. Contains a copy of the task selector from the previously-
executed task. See “Nesting Tasks” on page 386 for additional information.
•Stack Pointers —Bytes 1Bh–04h, static field. Contains the privilege 0, 1, and 2 stack pointers for
the task. These consist of the stack-segment selector (SS n), and the stack-segment offset (ESP n).
•CR3—Bytes 1Fh–1Ch, static field. Contains the page-translation-table base-address (CR3)
register for the task.
•EIP—Bytes 23h–20h, dynamic field. Contains the instruction pointer (EIP) for the next instruction
to be executed when the task is restored.
•EFLAGS —Bytes 27h–24h, dynamic field. Contains a copy of the EFLAGS image at the point the
task is suspended.
•General-Purpose Registers—Bytes 47h–28h, dynamic field. Contains a copy of the EAX, ECX,
EDX, EBX, ESP, EBP, ESI, and EDI values at the point the task is suspended.
•Segment-Selector Registers —Bytes 59h–48h, dynamic field. Contains a copy of the ES, CS, SS,
DS, FS, and GS, values at the point the task is suspended.
•LDT Segment-Selector Register —Bytes 63h–60h, static field. Contains the local-descriptor-table
segment selector for the task.
•T (Trap) Bit —Bit 0 of byte 64h, static field. This bit, when set to 1, causes a debug exception
(#DB) to occur on a task switch. See “Breakpoint Instruction (INT3)” on page 407 for additionalinformation.
•Shadow Stack Pointer (SSP) —Bytes 6Bh-68h, static field. Contains the 32-bit SSP for the
incoming task. Note that the SSP of the outgoing task is not saved in this field.
•I/O-Permission Bitmap Base Address —Bytes 67h–66h, static field. This field represents a 16-bit
offset into the TSS. This offset points to the beginning of the I/O-permission bitmap, and the end ofthe interrupt-redirection bitmap.
•I/O-Permission Bitmap—Static field. This field specifies protection for I/O-port addresses (up tothe 64K ports supported by the processor), as follows:
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- Whether the port can be accessed at any privilege level.
- Whether the port can be accessed outside the privilege level established by EFLAGS.IOPL.- Whether the port can be accessed when the processor is running in virtual-8086 mode. Because one bit is used per 8-byte I/O-port, this bitmap can take up to 8 Kbytes of TSS space. The
bitmap can be located anywhere within the first 64 Kbytes of the TSS, as long as it is above byte103. The last byte of the bitmap must contain all ones (0FFh). See “I/O-Permission Bitmap” onpage 374 for more information.
•Interrupt-Redirection Bitmap —Static field. This field defines how each of the 256-possible
software interrupts is directed in a virtual-8086 environment. One bit is used for each interrupt, fora total bitmap size of 32 bytes. The bitmap can be located anywhere above byte 103 within the first64 Kbytes of the TSS. See “Interrupt Redirection of Software Interrupts” on page 289 for
information on using this field.
The TSS can be paged by system software. System software that uses the hardware task-switch mechanism must guarantee that a page fault does not occur during a task switch. Because the processor only reads and writes the first 104 TSS bytes during a task switch, this restriction only applies to those bytes. The simplest approach is to align the TSS on a page boundary so that all critical bytes are either present or not present. Then, if a page fault occurs when the TSS is accessed, it occurs before the first byte is read. If the page fault occurs after a portion of the TSS is read, the fault is unrecoverable.
I/O-Permission Bitmap.  The I/O-permission bitmap (IOPB) allows system software to grant less-
privileged programs access to individual I/O ports, overriding the effect of RFLAGS.IOPL for those devices. When an I/O instruction is executed, the processor checks the IOPB only if the processor is in virtual x86 mode or the CPL is greater than the RFLAGS.IOPL field. Each bit in the IOPB corresponds to a byte I/O port. A word I/O port corresponds to two consecutive IOPB bits, and a doubleword I/O port corresponds to four consecutive IOPB bits. Access is granted to an I/O port of a given size when all IOPB bits corresponding to that port are clear. If any bits are set, a #GP occurs. 
The IOPB is located in the TSS, as shown by the example in Figure 12 -7 on page 375. Each TSS can

The IOPB is located in the TSS, as shown by the example in Figure 12 -7 on page 375. Each TSS can 
have a different copy of the IOPB, so access to individual I/O devices can be granted on a task-by-task basis. The I/O-permission bitmap base-address field located at byte 66h in the TSS is an offset into the TSS locating the start of the IOPB. If all 64K I/O ports are supported, the IOPB base address must not be greater than 0DFFFh, otherwise accesses to the bitmap cause a #GP to occur. An extra byte must be present after the last IOPB byte. This byte must have all bits set to 1 (0FFh). This allows the processor to read two IOPB bytes each time an I/O port is accessed. By reading two IOPB bytes, the processor can check all bits when unaligned, multi-byte I/O ports are accessed. 
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Figure 12-7. I/O-Permission Bitmap Example
Bits in the IOPB sequentially correspond to I/O port addresses. The example in Figure 12 -7 shows bits 
12 through 15 in the second doubleword of the IOPB cleared to 0. Those bit positions correspond to 
byte I/O ports 44h through 47h, or alternatively, doubleword I/O port 44h. Because the bits are cleared to zero, software running at any privilege level can access those I/O ports. 
By adjusting the TSS limit, it may happen that some ports in the I/O-address space have no 
corresponding IOPB entry. Ports not represented by the IOPB will cause a #GP exception. Referring again to Figure 12 -7, the last IOPB entry is at bit 23 in the fourth IOPB doubleword, which 
corresponds to I/O port 77h. In this example, all ports from 78h and above will cause a #GP exception, as if their permission bit was set to 1.
12.2.5  64-Bit Task State Segment
Although the hardware task-switching mechanism is not supported in long mode, a 64-bit task state 
segment (TSS) must still exist. System software must create at least one 64-bit TSS for use after activating long mode, and it must execute the LTR instruction, in 64-bit mode , to load the TR register 
with a pointer to the 64-bit TSS that serves both 64-bit-mode programs and compatibility-mode programs.
The legacy TSS contains several fields used for saving and restoring processor-state information. The 
legacy fields include general-purpose register, EFLAGS, CR3 and segment-selector register state, among others. Those legacy fields are not supported by the 64-bit TSS. System software must save and restore the necessary processor-state information required by the software-multitasking implementation (if multitasking is supported). Figure 12 -8 on page 377 shows the format of a 64-bit 
TSS. 
The 64-bit TSS holds several pieces of information important to long mode that are not directly related 
to the task-switch mechanism:
•RSPn —Bytes 1Bh–04h . The full 64-bit canonical forms of the stack pointers (RSP) for privilege
levels 0 through 2. Bit Offset Byte
1111_1111 IOPB+Ch
IOPB+8h
0 0 0 0 IOPB+4h
IOPB
I/O-Permission Bitmap Base Address +64h
. . .
+00h
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•ISTn —Bytes 5Bh–24h . The full 64-bit canonical forms of the interrupt-stack-table (IST) pointers.
See “Interrupt-Stack Table” on page 284 for a description of the IST mechanism.
•I/O Map Base Address—Bytes 67h–66h . The 16-bit offset to the I/O-permission bit map from the
64-bit TSS base. The function of this field is identical to that in a legacy 32-bit TSS. See “I/O-
Permission Bitmap” on page 374 for more information.
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Figure 12-8. Long Mode TSS FormatBit Offset Byte
Base
-
¯-
¯
I/O Map
 Base Address Reserved, IGN +64h
Reserved, IGN+60h
+5Ch
IST7[63:32] +58h
IST7[31:0] +54h
IST6[63:32] +50h
IST6[31:0] +4Ch
IST5[63:32] +48h
IST5[31:0] +44h
IST4[63:32] +40h
IST4[31:0] +3Ch
IST3[63:32] +38h
IST3[31:0] +34h
IST2[63:32] +30h
IST2[31:0] +2Ch
IST1[63:32] +28h
IST1[31:0] +24h
Reserved, IGN+20h
+1Ch
RSP2[63:32] +18h
RSP2[31:0] +14h
RSP1[63:32] +10h
RSP1[31:0] +0Ch
RSP0[63:32] +08h
RSP0[31:0] +04h
Reserved, IGN +00h
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12.2.6  Task Gate Descriptor (Legacy Mode Only)
Task-gate descriptors hold a selector reference to a TSS and are used to control access between tasks. 
Unlike a TSS descriptor or other gate descriptors, a task gate can be located in any of the three descriptor tables (GDT, LDT, and IDT). Figure 12 -9 shows the format of a task-gate descriptor.
Figure 12-9. Task-Gate Descriptor, Legacy Mode Only
The task-gate descriptor fields are:
•System (S) and Type —Bits 12 and 11:8 (respectively) of byte +4. These bits are encoded by
software as 00101b to indicate a task-gate descriptor type.
•Present (P)—Bit 15 of byte +4. The segment-present bit indicates the segment referenced by the
gate descriptor is loaded in memory. If a reference is made to a segment when P=0, a segment-not-present exception (#NP) occurs. This bit is set and cleared by system software and is never alteredby the processor.
•Descriptor Privilege-Level (DPL) —Bits 14:13 of byte +4. The DPL field indicates the gate-
descriptor privilege level. DPL can be set to any value from 0 to 3, with 0 specifying the mostprivilege and 3 the least privilege.
12.3 Hardware Task-Management in Legacy Mode
This section describes the operation of the task-switch mechanism when the processor is running in legacy mode. None of these features are supported in long mode (either compatibility mode or 64-bit mode).
12.3.1  Task Memory-Mapping
The hardware task-switch mechanism gives system software a great deal of flexibility in managing the 
sharing and isolation of memory—both virtual (linear) and physical—between tasks.
Segmented Memory.  The segmented memory for a task consists of the segments that are loaded 
during a task switch and any segments that are later accessed by the task code. The hardware task-switch mechanism allows tasks to either share segments with other tasks, or to access segments in isolation from one another. Tasks that share segments actually share a virtual-address (linear-address) space, but they do not necessarily share a physical-address space. When paging is enabled, the virtual-to-physical mapping for each task can differ, as is described in the following section. Shared segments 31 16 15 14 13 12 11 8 7 0
Reserved, IGN P DPL S Type Reserved, IGN +4
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do share  physical memory when paging is disabled, because virtual addresses are used as physical 
A number of options are available to system software that shares segments between tasks:
•Sharing segment descriptors using the GDT. All tasks have access to the GDT, so it is possible for
segments loaded in the GDT to be shared among tasks.
•Sharing segment descriptors using a single LDT. Each task has its own LDT, and that LDT selectoris automatically saved and restored in the TSS by the processor during task switches. Tasks,however, can share LDTs simply by storing the same LDT selector in multiple TSSs. Using theLDT to manage segment sharing and segment isolation provides more flexibility to systemsoftware than using the GDT for the same purpose.
•Copying shared segment descriptors into multiple LDTs. Segment descriptors can be copied bysystem software into multiple LDTs that are otherwise not shared between tasks. Allowingsegment sharing at the segment-descriptor level, rather than the LDT level or GDT level, providesthe greatest flexibility to system software.
In all three cases listed above, the actual data and instructions are shared between tasks only when the tasks’ virtual-to-physical address mappings are identical.
Paged Memory.  Each task has its own page-translation table base-address (CR3) register, and that 
register is automatically saved and restored in the TSS by the processor during task switches. This allows each task to point to its own set of page-translation tables, so that each task can translate virtual addresses to physical addresses independently. Page translation must be enabled for changes in CR3 values to have an effect on virtual-to-physical address mapping. When page translation is disabled, the tables referenced by CR3 are ignored, and virtual addresses are equivalent to physical addresses.
12.3.2  Switching Tasks
The hardware task-switch mechanism transfers program control to a new task when any of the 
following occur:
•A CALL or JMP instruction with a selector operand that references a task gate is executed. The
task gate can be located in either the LDT or GDT.
•A CALL or JMP instruction with a selector operand that references a TSS descriptor is executed.The TSS descriptor must be located in the GDT.
•A software-interrupt instruction (INTn) is executed that references a task gate located in the IDT.
•An exception or external interrupt occurs, and the vector references a task gate located in the IDT.

•An IRET is executed while the EFLAGS.NT bit is set to 1, indicating that a return is beingperformed from an inner-level task to an outer-level task. The new task is referenced using theselector stored in the current-task link field. See “Nesting Tasks” on page 386 for additional
information. The RET instruction cannot  be used to switch tasks.
When a task switch occurs, the following operations are performed automatically by the processor:
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•The processor performs privilege-checking to determine whether the currently-executing program
is allowed to access the target task. If this check fails, the task switch is aborted without modifyingthe processor state, and a general-protection exception (#GP) occurs. The privilege checksperformed depend on the cause of the task switch:
- If the task switch is initiated by a CALL or JMP instruction through a TSS descriptor, the 
processor checks that both the currently-executing program CPL and the TSS-selector RPL are 
numerically less-than or equal-to the TSS-descriptor DPL. 
- If the task switch takes place through a task gate, the CPL and task-gate RPL are compared 
with the task-gate DPL, and no comparison is made using the TSS-descriptor DPL. See “Task Switches Using Task Gates” on page 384.
- Software interrupts, hardware interrupts, and exceptions all transfer control without checking 
the task-gate DPL.
- The IRET instruction transfers control without checking the TSS-descriptor DPL.
•The processor performs limit-checking on the target TSS descriptor to verify that the TSS limit isgreater than or equal to:
- 67h (at least 104 bytes), when shadow stacks are not enabled (CR4.CET=0).- 6Bh (at least 108 bytes), when shadow stacks are enabled (CR4.CET=1).If this check fails, the task switch is aborted without modifying the processor state, and an
invalid -TSS exception (#TS) occurs.
•If shadow stacks are enabled at the current CPL and the task switch was initiated by an IRETinstruction, the current SSP must be aligned to 8 bytes. If this check fails, the task switch is abortedwithout modifying the processor state, and an #TS(current task) exception is generated.
•The current-task state is saved in the TSS. This includes the next-instruction pointer (EIP),EFLAGS, the general-purpose registers, and the segment-selector registers.
Up to this point, any exception that occurs aborts the task switch without changing the processor
state. From this point forward, any exception that occurs does so in the context of the new task. Ifan exception occurs in the context of the new task during a task switch, the processor finishesloading the new-task state without performing additional checks. The processor transfers controlto the #TS handler after this state is loaded, but before the first instruction is executed in the newtask. When a #TS occurs, it is possible that some of the state loaded by the processor did notparticipate in segment access checks. The #TS handler must verify that all segments are accessiblebefore returning to the interrupted task.
•The task register (TR) is loaded with the new-task TSS selector, and the hidden portion of the TR isloaded with the new-task descriptor. The TSS now referenced by the processor is that of the newtask. 
•The current task is marked as busy. The previous task is marked as available or remains busy,based on the type of linkage. See “Nesting Tasks” on page 386 for more information.
•CR0.TS is set to 1. This bit can be used to save other processor state only when it becomesnecessary. For more information, see the next section, “Saving Other Processor State.”
•If shadow stacks are enabled (CR4.CET=1), the following shadow stack actions are performed:
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saveCsLipSsp = FALSE
checkCsLip   = FALSERead CS and EFLAGS from the incoming TSSnewCPL = (EFLAGS.VM == 1) ? 3 : CS.RPL
IF (task switch was initiated by CALL, interrupt or exception)
   {   IF (ShadowStacksEnabled at current CPL)
{IF ((current CPL == 3) && (newCPL < 3))
         PL3_SSP = SSP     // switching from user to supv            ELSE         {            saveCsLipSsp = TRUE  // all other priv changes         tempSSP = SSP         tempLIP = CS.base + EIP         tempCS = CS.sel         }      }   } //end task switch initated by CALL,int, or exception
ELSEIF (task switch was initiated by IRET)
   {    IF (ShadowStacksEnabled at current CPL)      {      // pop CS, LIP and SSP from shadow stack       IF ((newCPL == current CPL) || (newCPL < 3))         {               // no priv change, or supv to user/supv         tempCS  = SSTK_READ_MEM.d [SSP+16]         tempLIP = SSTK_READ_MEM.d [SSP+8]         tempSSP = SSTK_READ_MEM.d [SSP]         SSP = SSP + 24
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         checkCsLip = TRUE
         }      // check shadow stack token and clear busy bit
temp_Token = SSTK_READ_MEM.q [SSP] // read supervisor sstk tokenexpected_Token = SSP OR 0x01  // busy bit must be setIF (temp_token == expected token)
SSTK_WRITE_MEM.q [SSP] = SSP  // token OK, clear busy bit
      SSP = 0      }      // end shadow stacks enabled at current CPL   } //end task switch initiated by IRET
•The new-task state is loaded from the TSS. This includes the next-instruction pointer (EIP),
EFLAGS, the general-purpose registers, and the segment-selector registers. The processor clearsthe segment-descriptor present (P) bits (in the hidden portion of the segment registers) to preventaccess into the new segments, until the task switch completes successfully.
•The LDTR and CR3 registers are loaded from the TSS, changing the virtual-to-physical mappingfrom that of the old task to the new task. Because this is done in the middle of accessing the newTSS, system software must ensure that TSS addresses are translated identically in all tasks.
•The descriptors for all previously-loaded segment selectors are loaded into the hidden portion ofthe segment registers. This sets or clears the P bits for the segments as specified by the newdescriptor values.
IF (ShadowStacksEnabled at current CPL) 
   {   IF (EFLAGS.VM == 1)         EXCEPTION [#TSS(new task selector)]
   IF (task switch was initiated by a CALL, JMP, interrupt or exception)
      {      newSSP = SSTK_READ_MEM.d [TSS offset 0x68]  // read new SSP      IF (newSSP[2:0] != 0)                       // must be 8-byte aligned             EXCEPTION [#TSS(new task selector)]        // check token and set busy
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      temp_Token = SSTK_READ_MEM.q [newSSP]     // read sstk token
      expected_Token = SSP // busy bit must be clear
      IF (temp_token != expected_token) // token must be valid            EXCEPTION [#TSS(new task selector)]        SSTK_WRITE_MEM.q [SSP] = SSP OR 0x01 // valid token, set busy bit 
      SSP = newSSP            IF (saveCsLipSsP == TRUE) // push old CS,LIP,SSP onto new sstk         {               SSTK_WRITE_MEM.q [SSP-24] = tempCS         SSTK_WRITE_MEM.q [SSP-16] = tempLIP         SSTK_WRITE_MEM.q [SSP-8] = tempSSP         SSP = SSP - 24         }      } // end task switch initiated by CALL, JMP, interrupt or exception   } // end shadow stacks enabled at current CPL   ELSEIF (task switch was initiated by an IRET)   {   IF (checkCsLip == TRUE)      {                                 // check CS, LIP against shadow stack      IF (tempCS != CS)             EXCEPTION [#CP(RETF/IRET)]  // CS must match      IF (tempLIP != (CS.base + EIP))            EXCEPTION [#CP(RETF/IRET)]  // LIP must match      }               IF ShadowStackEnabled at newCPL      {      IF (!checkCsLip)
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         tempSSP = PL3_SSP; 
      IF (tempSSP[1:0] != 0)            // SSP must be 4-byte aligned                EXCEPTION [#CP(RETF/IRET)]      IF (tempSSP[63:32] != 0)          // and SSP must be <4 GB                EXCEPTION [#CP(RETF/IRET)]      SSP = tempSSP      }  // end shadow stacks enabled at new CPL   } // end task swtich initiated by IRET
If the above steps complete successfully, the processor begins executing instructions in the new task 
beginning with the instruction referenced by the CS:EIP far pointer loaded from the new TSS. The privilege level of the new task is taken from the new CS segment selector’s RPL.
Saving Other Processor State.  The processor does not automatically save the registers used by the 
media or x87 instructions. Instead, the processor sets CR0.TS to 1 during a task switch. Later, when an attempt is made to execute any of the media or x87 instructions while TS=1, a device-not-available exception (#NM) occurs. System software can then save the previous state of the media and x87 registers and clear the CR0.TS bit to 0 before executing the next media/x87 instruction. As a result, the media and x87 registers are saved only when necessary after a task switch. 
12.3.3  Task Switches Using Task Gates
When a control transfer to a new task occurs through a task gate, the processor reads the task-gate DPL 
(DPL

(DPL
G) from the task-gate descriptor. Two privilege checks, both of which must pass, are performed 
on DPLG before the task switch can occur successfully:
•The processor compares the CPL with DPLG. The CPL must be numerically less than or equal to
DPLG for this check to pass. In other words, the following expression must be true: CPL DPLG.
•The processor compares the RPL in the task-gate selector with DPLG. The RPL must be
Unlike call-gate control transfers, the processor does not read the DPL from the target TSS descriptor (DPL
S) and compare it with the CPL when a task gate is used.
Figure 12 -10 on page 386 shows two examples of task-gate privilege checks. In Example 1, the 
privilege checks pass:
•The task-gate DPL (DPLG) is at the lowest privilege (3), specifying that software running at any
•The selector referencing the task gate passes its privilege check because the RPL is numerically
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•The task-gate DPL (DPLG) specifies that only software at privilege-level 0 can access the gate.
The current program does not have enough privilege to access the task gate, because its CPL is 2.
•The selector referencing the task-gate descriptor does not have a high enough privilege to complete
the reference. Its RPL is numerically greater than DPLG.
Although both privilege checks failed in the example, if only one check fails, access into the target task is denied.
Because the legacy task-switch mechanism is not supported in long mode, software cannot use task 
gates in long mode. Any attempt to transfer control to another task using a task gate in long mode 
causes a general-protection exception (#GP) to occur.
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Figure 12-10. Privilege-Check Examples for Task Gates
12.3.4  Nesting Tasks
The hardware task-switch mechanism supports task nesting through the use of EFLAGS nested-task  
(NT) bit and the TSS link-field. The manner in which these fields are updated and used during a task 
switch depends on how the task switch is initiated:
•The JMP instruction does not update EFLAGS.NT or the TSS link-field. Task nesting is not
supported by the JMP instruction.513-255.epsExample 1: Privilege Check PassesDPL G=3
Task-Gate DescriptorTask-State
DPL S
TSS DescriptorTask-Gate
Task-Gate DescriptorCS CPL=2
DPL S
Task-State
SegmentAccess Allowed
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•The CALL instruction, INTn instructions, interrupts, and exceptions can only be performed from
outer-level tasks to inner-level tasks. All of these operations set the EFLAGS.NT bit for the newtask to 1 during a task switch, and copy the selector for the previous task into the new-task linkfield.
•An IRET instruction which returns to another task only occurs when the EFLAGS.NT bit for thecurrent task is set to 1, and only can be performed from an inner-level task to an outer-level task.When an IRET results in a task switch, the new task is referenced using the selector stored in thecurrent-TSS link field. The EFLAGS.NT bit for the current task is cleared to 0 during the taskswitch.
Table 12 -1 summarizes the effect various task-switch initiators have on EFLAGS.NT, the TSS link-
field, and the TSS-busy bit. (For more information on the busy bit, see the next section, “Preventing Recursion.”)
Programs running at any privilege level can set EFLAGS.NT to 1 and execute the IRET instruction to 
transfer control to another task. System software can keep control over improperly nested-task switches by initializing the link field of all TSSs that it creates. That way, improperly nested-task switches always transfer control to a known task.
Preventing Recursion.  Task recursion is not allowed by the hardware task-switch mechanism. If 
recursive-task switches were allowed, they would replace a previous task-state image with a newer image, discarding the previous information. To prevent recursion from occurring, the processor uses the busy bit located in the TSS-descriptor type field (bit 9 of byte +4). Use of this bit depends on how the task switch is initiated:
•The JMP instruction clears the busy bit in the old task to 0 and sets the busy bit in the new task to 1.
A general-protection exception (#GP) occurs if an attempt is made to JMP to a task with a set busybit.
•The CALL instruction, INT n instructions, interrupts, and exceptions set the busy bit in the new
task to 1. The busy bit in the old task remains set to 1, preventing recursion through task-nestingTable 12-1. Effects of Task Nesting
Task-Switch
InitiatorOld Task New Task
EFLAGS.NTLink 
(Selector)Busy EFLAGS.NTLink 
(Selector)Busy
JMP — —Clear to 0
(was 1)— — Set to 1
CALL
INTn
Interrupt
Exception——
(Was 1)Set to 1 Old Task Set to 1
IRETClear to 0
(was 1)—Clear to 0
(was 1)—
Note:
“—” indicates no change is made.
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levels. A general-protection exception (#GP) occurs if an attempt is made to switch to a task with a
set busy bit.
•An IRET to another task (EFLAGS.NT must be 1) clears the busy bit in the old task to 0. The busybit in the new task is not altered, because it was already set to 1.
Table 12 -1 on page 387 summarizes the effect various task-switch initiators have on the TSS-busy bit.
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13 Software Debug and Performance 
Resources
Testing, debug, and performance optimization consume a significant portion of the time needed to 
develop a new computer or software product and move it successfully into production. To stay competitive, product developers need tools that allow them to rapidly detect, isolate, and correct problems before a product is shipped. The goal of the debug and performance features incorporated into processor implementations of the AMD64 architecture is to support the tool chain solutions used in software and hardware product development.
The debug and performance resources that can be supported by AMD64 architecture implementations 
include:
•Software Debug —Software-debug facilities include the debug registers (DR0–DR7), debug 
exception, and breakpoint exception. Additional features are provided using model-specific 
registers (MSRs). These registers are used to set breakpoints on branches, interrupts, and exceptions and to single step from one branch to the next. The software-debug capability is described in the following section.
•Performance Monitoring Counters —Performance monitoring counters (PMCs) are provided to 
count specific processor hardware events. A set of control registers allow the selection of events to be monitored and a corresponding set of counter registers track the frequency of monitored events. These counters are described in Section 13.2 “Performance Monitoring Counters” on page 410.
•Instruction-Based Sampling — Instruction-based sampling is a hardware-based facility that 
enables system software to capture specific data concerning instruction fetch and instruction execution operation based on random sampling. This facility is described in Section 13.3 “Instruction-Based Sampling” on page 423.
•Lightweight Profiling—AMD64 architecture provides instructions that allow user-level programs to manage the gathering of instruction statistics using very little overhead. This facility is described in Section 13.4 “Lightweight Profiling” on page 437.
Although a subset of the facilities listed are available in all processor implementations, the remainder are optional. Support for optional facilities is indicated via CPUID feature bits. The means of determining support for each architected facility is described along with the facility in the sections that follow.
A given processor product may include additional debug and performance monitoring capabilities 
beyond those which are architecturally-defined. For details see the BIOS and Kernel Developer’s 
Guide (BKDG) or Processor Programming Reference Manual (PPR)  applicable to your product.
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13.1 Software-Debug Resources
Software can program breakpoints into the debug registers, causing a debug exception (#DB) when 
matches occur on instruction-memory addresses, data-memory addresses, or I/O addresses. The breakpoint exception (#BP) is also supported to allow software to set breakpoints by placing INT3 instructions in the instruction memory for a program. Program control is transferred to the breakpoint exception (#BP) handler when an INT3 instruction is executed.

In addition to the debug features supported by the debug registers (DR0–DR7), the processor also 
supports features supported by model-specific registers (MSRs). Together, these capabilities provide a rich set of breakpoint conditions, including:
•Breakpoint On Address Match —Breakpoints occur when the address stored in a address-
breakpoint register matches the address of an instruction or data reference. Up to four address-
match breakpoint conditions can be set by software.
•Single Step All Instructions —Breakpoints can be set to occur on every instruction, allowing a 
debugger to examine the contents of registers as a program executes.
•Single Step Control Transfers —Breakpoints can be set to occur on control transfers, such as calls, 
jumps, interrupts, and exceptions. This can allow a debugger to narrow a problem search to a specific section of code before enabling single stepping of all instructions.
•Breakpoint On Any Instruction —Breakpoints can be set on any specific instruction using either the 
address-match breakpoint condition or using the INT3 instruction to force a breakpoint when the instruction is executed.
•Breakpoint On Task Switch —Software forces a #DB exception to occur when a task switch is 
performed to a task with the T bit in the TSS set to 1. Debuggers can use this capability to enable or disable debug conditions for a specific task.
•Breakpoint On Bus Lock  —The processor generates a #DB exception as a trap following the 
successful execution of a locked read-modify-write operation that requires a bus lock and the current privilege level (CPL) was > 0. See Section 13.1.3.6  on page 406 for more information about Bus Lock traps. 
Problem areas can be identified rapidly using the information supplied by the debug registers when breakpoint conditions occur:
•Special conditions that cause a #DB exception are recorded in the DR6 debug-status register, 
including breakpoints due to task switches and single stepping. The DR6 register also identifies which address-breakpoint register (DR0–DR3) caused a #DB exception due to an address match. When combined with the DR7 debug-control register settings, the cause of a #DB exception can be identified.
•To assist in analyzing the instruction sequence a processor follows in reaching its current state, the source and destination addresses of control-transfer events are saved by the processor. These include branches (calls and jumps), interrupts, and exceptions. Debuggers can use this information to narrow a problem search to a specific section of code before single stepping all instructions.
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13.1.1  Debug Registers
The AMD64 architecture supports the legacy debug registers, DR0–DR7. These registers are 
expanded to 64 bits by the AMD64 architecture. In legacy mode and in compatibility mode, only the lower 32 bits are used. In these modes, writes to a debug register fill the upper 32 bits with zeros, and reads from a debug register return only the lower 32 bits. In 64-bit mode, all 64 bits of the debug registers are read and written. Operand-size prefixes are ignored. 
The debug registers can be read and written only when the current-protection level (CPL) is 0 (most 
privileged). Attempts to read or write the registers at a lower-privilege level (CPL>0) cause a general-protection exception (#GP).
Several debug registers described below are model-specific registers (MSRs). See “Software-Debug 
MSRs” on page 723 for a listing of the debug-MSR numbers and their reset values. Some processor implementations include additional MSRs used to support implementation-specific software debug features. For more information on these registers and their capabilities, see the BIOS and Kernel 
Developer’s Guide (BKDG) or Processor Programming Reference Manual (PPR)  applicable to your 
product.
13.1.1.1  Address-Breakpoint Registers (DR0-DR3)
Figure 13 -1 shows the format of the four address-breakpoint registers, DR0-DR3. Software can load a 
virtual (linear) address into any of the four registers, and enable breakpoints to occur when the address 
matches an instruction or data reference. The MOV DR n instructions do not  check that the virtual 
addresses loaded into DR0–DR3 are in canonical form. Breakpoint conditions are enabled using the debug-control register, DR7 (see “Debug-Control Register (DR7)” on page 393).
Figure 13-1. Address-Breakpoint Registers (DR0–DR3)63 0
Breakpoint 0 64-bit Virtual (linear) Address
63 0
Breakpoint 1 64-bit Virtual (linear) Address
63 0
Breakpoint 2 64-bit Virtual (linear) Address
63 0
Breakpoint 3 64-bit Virtual (linear) Address
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13.1.1.2  Reserved Debug Registers (DR4, DR5)
The DR4 and DR5 registers are reserved and should not be used by software. These registers are 
aliased to the DR6 and DR7 registers, respectively. When the debug extensions are enabled (CR4[DE] = 1) attempts to access these registers cause an invalid-opcode exception (#UD).
13.1.1.3  Debug-Status Register (DR6)
Figure 13 -2 on page 392 shows the format of the debug-status register, DR6. Debug status is loaded 
into DR6 when an enabled debug condition is encountered that causes a #DB exception. 
Figure 13-2. Debug-Status Register (DR6)
Bits 15:13 of the DR6 register are not cleared by the processor and must be cleared by software after 
the contents have been read. Register fields are:
•Breakpoint-Condition Detected (B3–B0) —Bits 3:0. The processor updates these four bits on every 
debug breakpoint or general-detect condition. A bit is set to 1 if the corresponding address-
breakpoint register detects an enabled breakpoint condition, as specified by the DR7 Ln, G n, R/W n 
and LEN n controls, and is cleared to 0 otherwise. For example, B1 (bit 1) is set to 1 if an address-
breakpoint condition is detected by DR1.
•Bus Lock Detected (BLD) —Bit 11. The processor clears this bit if #DB was generated due to a bus 
lock.  Other sources of #DB do not modify this bit.63 32
Reserved
31 16 15 14 13 12 11 10 4 3 2 1 0
Reserved
BT
BS
BD
Reserved
BLDReserved
B3
B2B1B0
31:16 Reserved RA1
15 BT Breakpoint Task Switch R/W
14 BS Breakpoint Single Step R/W
13 BD Breakpoint Debug Access Detected R/W
12 Reserved RAZ
11 BLD Bus Lock Detected R/W
10:4 Reserved RA1
3 B3 Breakpoint #3 Condition Detected R/W
2 B2 Breakpoint #2 Condition Detected R/W
1 B1 Breakpoint #1 Condition Detected R/W
0 B0 Breakpoint #0 Condition Detected R/W
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•Debug-Register-Access Detected (BD) —Bit 13. The processor sets this bit to 1 if software 
accesses any debug register (DR0–DR7) while the general-detect condition is enabled 
(DR7[GD] = 1).
•Single Step (BS) —Bit 14. The processor sets this bit to 1 if the #DB exception occurs as a result of 
single-step mode (rFLAGS[TF] = 1). Single-step mode has the highest-priority among debug 
exceptions. Other status bits within the DR6 register can be set by the processor along with the BS bit.
•Task-Switch (BT) —Bit 15. The processor sets this bit to 1 if the #DB exception occurred as a result 
of task switch to a task with a TSS T-bit set to 1. 
All remaining bits in the DR6 register are reserved. Reserved bits 31:16 and 11:4 must all be set to 1, while reserved bit 12 must be cleared to 0. In 64-bit mode, the upper 32 bits of DR6 are reserved and must be written with zeros. Writing a 1 to any of the upper 32 bits results in a general-protection exception, #GP(0).
13.1.1.4  Debug-Control Register (DR7)
Figure 13 -3 shows the format of the debug-control register, DR7. DR7 is used to establish the 
breakpoint conditions for the address-breakpoint registers (DR0–DR3) and to enable debug 
exceptions for each address-breakpoint register individually. DR7 is also used to enable the general-detect breakpoint condition.
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Figure 13-3. Debug-Control Register (DR7)
The fields within the DR7 register are all read/write. These fields are:
•Local-Breakpoint Enable (L3–L0) —Bits 6, 4, 2, and 0 (respectively). Software individually sets 
these bits to 1 to enable debug exceptions to occur when the corresponding address-breakpoint 
register (DR n) detects a breakpoint condition while executing the current  task. For example, if L1 
(bit 2) is set to 1 and an address-breakpoint condition is detected by DR1, a #DB exception occurs. These bits are cleared to 0 by the processor when a hardware task-switch occurs.
•Global-Breakpoint Enable (G3–G0) —Bits 7, 5, 3, and 1 (respectively). Software sets these bits to 
1 to enable debug exceptions to occur when the corresponding address-breakpoint register (DRn) detects a breakpoint condition while executing any task. For example, if G1 (bit 3) is set to 1 and an 63 32
Reserved

Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEN3 R/W3 LEN2 R/W2 LEN1 R/W1 LEN0 R/W0
Reserved
GD
Reserved
Reserved
GE
LE
G3
L3
G2
L2
G1
L1
G0
L0
31:30 LEN3 Length of Breakpoint #3 R/W
29:28 R/W3 Type of Transaction(s) to Trap R/W
27:26 LEN2 Length of Breakpoint #2 R/W
25:24 R/W2 Type of Transaction(s) to Trap R/W
23:22 LEN1 Length of Breakpoint #1 R/W
21:20 R/W1 Type of Transaction(s) to Trap R/W
19:18 LEN0 Length of Breakpoint #0 R/W
17:16 R/W0 Type of Transaction(s) to Trap R/W
15:14 Reserved RAZ
13 GD General Detect Enabled R/W
12:11 Reserved RAZ
10 Reserved RA1
9 GE Global Exact Breakpoint Enabled R/W
8 LE Local Exact Breakpoint Enabled R/W
7 G3 Global Exact Breakpoint #3 Enabled R/W
6 L3 Local Exact Breakpoint #3 Enabled R/W
5 G2 Global Exact Breakpoint #2 Enabled R/W
4 L2 Local Exact Breakpoint #2 Enabled R/W
3 G1 Global Exact Breakpoint #1 Enabled R/W
2 L1 Local Exact Breakpoint #1 Enabled R/W
1 G0 Global Exact Breakpoint #0 Enabled R/W
0 L0 Local Exact Breakpoint #0 Enabled R/W
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address-breakpoint condition is detected by DR1, a #DB exception occurs. These bits are never 
cleared to 0 by the processor.
•Local-Enable (LE)—Bit 8. Software sets this bit to 1 in legacy implementations to enable exact breakpoints while executing the current  task. This bit is ignored by implementations of the 
AMD64 architecture. All breakpoint conditions, except certain string operations preceded by a repeat prefix, are exact.
•Global-Enable (GE) —Bit 9. Software sets this bit to 1 in legacy implementations to enable exact 
breakpoints while executing any task. This bit is ignored by implementations of the AMD64 
architecture. All breakpoint conditions, except certain string operations preceded by a repeat prefix, are exact.
•General-Detect Enable (GD) —Bit 13. Software sets this bit to 1 to cause a debug exception to 
occur when an attempt is made to execute a MOV DR n instruction to any debug register 
(DR0–DR7). This bit is cleared to 0 by the processor when the #DB handler is entered, allowing the handler to read and write the DRn registers. The #DB exception occurs before executing the instruction, and DR6[BD] is set by the processor. Software debuggers can use this bit to prevent the currently-executing program from interfering with the debug operation.
•Read/Write (R/W3–R/W0)—Bits 29:28, 25:24, 21:20, and 17:16 (respectively). Software sets these fields to control the breakpoint conditions used by the corresponding address-breakpoint registers (DRn). For example, control-field R/W1 (bits 21:20) controls the breakpoint conditions for the 
DR1 register. The R/W n control-field encodings specify the following conditions for an address-
breakpoint to occur:
- 00—Only on instruction execution.- 01—Only on data write.- 10—This encoding is further qualified by CR4[DE] as follows:
. CR4[DE] = 0—Condition is undefined.
. CR4[DE] = 1—Only on I/O read or I/O write.
- 11—Only on data read or data write.
•Length (LEN3–LEN0) —Bits 31:30, 27:26, 23:22, and 19:18 (respectively). Software sets these 
fields to control the range used in comparing a memory address with the corresponding address-
breakpoint register (DR n). For example, control-field LEN1 (bits 23:22) controls the breakpoint-
comparison range for the DR1 register. 
The value in DR n defines the low-end of the address range used in the comparison. LEN n is used 
to mask the low-order address bits in the corresponding DR n register so that they are not used in 
the address comparison. To work properly, breakpoint boundaries must be aligned on an address 
corresponding to the range size specified by LENn. The LEN n control-field encodings specify the 
following address-breakpoint-comparison ranges:
- 00—1 byte.- 01—2 byte, must be aligned on a word boundary.- 10—8 byte, must be aligned on a quadword boundary. (Long mode only; otherwise undefined.)
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- 11—4 byte, must be aligned on a doubleword boundary.
If the R/W n field is used to specify instruction breakpoints (R/Wn=00), the corresponding LENn 
field must be set to 00. Setting LENn to any other value produces undefined results.
All remaining bits in the DR7 register are reserved. Reserved bits 15:14 and 12:11 must all be cleared 
to 0, while reserved bit 10 must be set to 1. In 64-bit mode, the upper 32 bits of DR7 are reserved and must be written with zeros. Writing a 1 to any of the upper 32 bits results in a general-protection #GP(0) exception.
13.1.1.5  64-Bit-Mode Extended Debug Registers
In 64-bit mode, additional encodings for debug registers are available. The R bit of the REX prefix is 
used to modify the ModRM reg field when that field encodes a control register. These additional 
encodings enable the processor to address DR8–DR15.
Access to the DR8–DR15 registers is implementation-dependent. The architecture does not require 
any of these extended debug registers to be implemented. Any attempt to access an unimplemented register results in an invalid-opcode exception (#UD).
13.1.1.6  Debug-Control MSR (DebugCtl)
Figure 13 -4 on page 397 shows the format of the debug-control MSR (DebugCtl). DebugCtl provides 
additional debug controls over control-transfer recording and single stepping, and external-breakpoint 
reporting and trace messages. DebugCtl is read and written using the RDMSR and WRMSR instructions.
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Figure 13-4. Debug-Control MSR (DebugCtl)
The fields within the DebugCtl register are:
•Last-Branch Record (LBR) —Bit 0, read/write. Software sets this bit to 1 to cause the processor to 
record the source and target addresses of the last control transfer taken before a debug exception 
occurs. The recorded control transfers include branch instructions, interrupts, and exceptions. See “Control-Transfer Breakpoint Features” on page 408 for more details on the registers. See Figure 13 -5 on page 398 for the format of the control-transfer recording MSRs.
•Branch Single Step (BTF) —Bit 1, read/write. Software uses this bit to change the behavior of the 
rFLAGS[TF] bit. When this bit is cleared to 0, the rFLAGS[TF] bit controls instruction single stepping, (normal behavior). When this bit is set to 1, the rFLAGS[TF] bit controls single stepping on control transfers. The single-stepped control transfers include branch instructions, interrupts, and exceptions. Control-transfer single stepping requires both BTF = 1 and rFLAGS[TF] = 1. See 
“Control-Transfer Breakpoint Features” on page 408 for more details on control-transfer single stepping.
•Bus Lock #DB Trap (BLCKDB) —Bit 2, read/write. Software sets this bit to enable generation of a 
#DB trap following successful exection of a bus lock when CPL is > 0. See Section 7.3.3  on 
page 195 for information on the conditions that cause a bus lock. Section 13.1.3.6  on page 406 describes bus lock #DB trap in more detail.
•Freeze LBR Stack on PMC Interrupt (FLBRI)—Bit 11, read/write. Software sets this bit to freeze the Last Branch Record (LBR) Stack when one of the Core Performance Counters overflows and is 63 32
Reserved
31 13 12 11 10 7 6 3 2 1 0
Reserved
FPMCI
FLBRIReserved Reserved
BLCKDB
BTF
LBR
63:13 Reserved RAZ
12 FPMCIFreeze Core Performance Monitor Counters on 
PMC interruptR/W
11 FLBRI Freeze LBR Stack on PMC interrupt R/W
10:7 Reserved RAZ
2 BLCKDB Bus Lock #DB trap enabled R/W
1 BTF Branch Single Step R/W
0 LBR Last-Branch Record R/W
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configured to signal a PMC overflow event. Support for this feature is indicated by 
CPUID Fn8000_0022_EAX[LbrAndPmcFreeze](bit 2) = 1.
•Freeze PMC on PMC interrupt (FPMCI) —Bit 12, read/write. Software sets this bit to freeze the 
Core Performance Counters when one of these counters overflows and is configured to signal a PMC overflow event. Support for this feature is indicated by CPUID Fn8000_0022_EAX[LbrAndPmcFreeze](bit 2) = 1.
All remaining bits in the DebugCtl register are reserved.
13.1.1.7  Control-Transfer Recording MSRs
Figure 13 -5 on page 398 shows the format of the 64-bit control-transfer recording MSRs: 
LastBranchToIP, LastBranchFromIP, LastIntToIP, and LastIntFromIP. These registers are loaded 
automatically by the processor when the DebugCtl[LBR] bit is set to 1. These MSRs are read-only.
Figure 13-5. Control-Transfer Recording MSRs
13.1.1.8  Debug-Extension-Control MSR (DebugExtnCtl)
Figure 13 -6 shows the format of the Debug-Extension-Control MSR (DebugExtnCtl). DebugExtnCtl 
is supported on processors that support Last Branch Record Stack (see Section 13.1.8, “Last Branch

is supported on processors that support Last Branch Record Stack (see Section 13.1.8, “Last Branch 
Record Stack,” on page 409) and provides control over enabling Last Branch Record Stack recording.63 0
LastBranchToIP - 64-bit Segment Offset (RIP)
63 0
LastBranchFromIP - 64-bit Segment Offset (RIP)
63 0
LastIntToIP - 64-bit Segment Offset (RIP)
63 0
LastIntFromIP - 64-bit Segment Offset (RIP)
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Figure 13-6. Debug-Extension-Control MSR (DebugExtnCtl)
The fields within the DebugExtnCtl register are:
•Last-Branch Record Stack Enable (LBRS) —Bit 6, read/write. Software sets this bit to 1 to cause 
the source and target address of control transfer instructions to be recorded on the LBR stack. The 
processor clears this bit when #DB exception occurs. Support for LBR Stack is indicated by CPUID Fn8000_0022_EAX[LbrStack](bit 1) = 1.
13.1.1.9  Last Branch Stack Registers
Figure 13 -7 and Figure 13 -8 show the format of the LastBranchStackFromIp and LastStackToIp 
MSRs. These MSRs provide access to the Last Branch Record Stack. These MSRs are supported on 
processors with CPUID Fn8000_0022_EAX[LbrStack] = 1. There are LBR_SIZE = CPUID Fn8000_0022_EBX[LbrStackSize] instances for each MSR. The Last Branch Record functionality is described in Section 13.1.8, “Last Branch Record Stack,” on page 409.
Figure 13 -7. LastBranchStackFromIp MSR63 32
Reserved
31 6 5 0
Reserved
LBRSReserved
63:7 Reserved MBZ
6 LBRS LBR Stack Enable R/W
5:0 Reserved MBZ
63 62 57 56 0
M Reserved BranchFromIp
63 M Mispredict R/W
62:57 Reserved
56:0 BranchFromIp  Segment offset of the recorded branch R/W
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The fields within LastBranchStackFromIp are:
•Mispredict —Bit 63, read/write. The processor sets this bit to 1 when the recorded branch was 
mispredicted.
•BranchFromIp —Bits 56:0, read/write. The processor records either the segment offset of the 
branch itself or the instruction preceding the branch. It can only record the segment offset of an 
instruction preceding the branch if that instruction is not a branch itself. Recording the IP of an instruction preceding the branch is the result of branch fusion. If it is desired that BranchFromIp only records the address of branches, Branch Fusion needs to be disabled by also enabling Legacy LBR via DbgCfg[LBR].
Figure 13-8. LastBranchStackToIp MSR
The fields within LastBranchStackToIp are:
•Valid—Bit 63, read/write. The processor sets this bit to 1 when the recorded branch entry is valid.
•Speculative —Bit 62, read/write. The processor sets this bit when the branch entry was recorded 
when a speculative performance feature was active.
•BranchToIp —Bits 56:0, read/write. The processor records the segment offset of the branch target.
Figure 13 -9 shows the format of the LastBranchStackSelect MSR. LastBranchStackSelect controls the 
recording of branches to the Last Branch Record Stack. This MSR is supported on processors with 
CPUID Fn8000_0022_EAX[LbrStack] = 1.63 62 61 57 56 0V
SPECReserved BranchToIp
63 V Valid R/W
62 SPEC Speculative R/W
61:57 Reserved
56:0 BranchToIp BranchToIp R/W
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Figure 13-9. LastBranchStackSelect MSR
The fields within LbrSelect are:
•CplEq0 —Bit 0, read/write. When set, the LBR Stack does not record branches ending in CPL = 0.
•CplGe0 —Bit 1, read/write. When set, the LBR Stack does not record branches ending in CPL > 0.
•Jcc—Bit 2, read/write. When set, the LBR Stack does not record conditional near branches.
•CallNearRel—Bit 3, read/write. When set, the LBR Stack does not record direct (relative) near 
calls.
•CallNearInd —Bit 4, read/write. When set, the LBR Stack does not record indirect near calls.
•RetNear —Bit 5, read/write. When set, the LBR Stack does not record near returns.
•JmpNearInd —Bit 6, read/write. When set, the LBR Stack does not record near indirect jumps.
•JmpNearRel —Bit 7, read/write. When set, the LBR Stack does not record near direct (relative) 
jumps.
•FarBranch —Bit 8, read/write. When set, the LBR Stack does not record far branches. 
13.1.2  Setting Breakpoints
Breakpoints can be set to occur on either instruction addresses or data addresses using the breakpoint-address registers, DR0–DR3 (DR n). The values loaded into these registers represent the breakpoint-
location virtual address. The debug-control register, DR7, is used to enable the breakpoint registers and to specify the type of access and the range of addresses that can trigger a breakpoint.63 9 8 7 6 5 4 3 2 1 0
Reserved
FarBranch
JmpNearRel
JmpNearInd
RetNear
CallNearInd
CallNearRel
Jcc
CplGe0
CplEq0
63:9 Reserved RAZ
8 FarBranch Suppress recording of far branches R/W
7 JmpNearRel Suppress recording of near relative jumps R/W
6 JumpNearInd Suppress recording of near indirect jumps R/W
5 RetNear Suppress recording of near returns R/W
4 CallNearInd Suppress recording of indirect near calls R/W
3 CallNearRel Suppress recording of relative near calls R/W
2 Jcc Suppress recording of conditional branches R/W
1 CplGe0 Suppress recording of branches ending in CPL > 0 R/W
0 CplEq0 Suppress recording of branches ending in CPL = 0 R/W
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Software enables the DR n registers using the corresponding local-breakpoint enable (L n) or global-
breakpoint enable (Gn) found in the DR7 register. L n is used to enable breakpoints only while the 
current task is active, and it is cleared by the processor when a task switch occurs. G n is used to enable 
breakpoints for all tasks, and it is never cleared by the processor.
The R/W n fields in DR7, along with the CR4[DE] bit, specify the type of access required to trigger a 
breakpoint when an address match occurs on the corresponding DRn register. Breakpoints can be set to 
occur on instruction execution, data reads and writes, and I/O reads and writes. The R/W n and 
CR4[DE] encodings used to specify the access type are described on page 395 of “Debug-Control Register (DR7).”
The LENn fields in DR7 specify the size of the address range used in comparison with data or 
instruction addresses. LEN n is used to mask the low-order address bits in the corresponding DR n 
register so that they are not used in the address comparison. Breakpoint boundaries must be aligned on an address corresponding to the range size specified by LENn. Assuming the access type matches the type specified by R/W n, a breakpoint occurs if any accessed byte falls within the range specified by 
LEN n. For instruction breakpoints, LENn must specify a single-byte range. The LEN n encodings used 
to specify the address range are described on page 395 of “Debug-Control Register (DR7).”
Table 13 -1 shows several examples of data accesses, and whether or not they cause a #DB exception to 
occur based on the breakpoint address in DR n and the breakpoint-address range specified by LEN n. In 
this table, R/W n always specifies read/write access.
Table 13 -1. Breakpoint-Setting Examples
Data-Access Address
(hexadecimal)Access Size 
(bytes)Byte-Addresses in Data-Access
(hexadecimal)Breakpoint-Address Range
(hexadecimal)Result
DRn=F000, LEN n=00 (1 Byte)
DRn=F005, LEN n=10 (8 Bytes)
EFFB 8EFFB, EFFC, EFFD, EFFE, 
EFFF, F000, F001
F000–F007#DB
EFFE2 EFFE, EFFF —
4 EFFE, EFFF, F000, F001
#DBF000 1 F000
F001 2 F001, F002
F005 4 F005, F006, F007, F008
Note:
“—” indicates no #DB occurs.
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13.1.3  Using Breakpoints
A debug exception (#DB) occurs when an enabled-breakpoint condition is encountered during 
program execution. The debug-handler must check the debug-status register (DR6), the conditions enabled by the debug-control register (DR7), and the debug-control MSR (DebugCtl), to determine the #DB cause. The #DB exception corresponds to interrupt vector 1. See “#DB—Debug Exception (Vector 1)” on page 247. 
Instruction breakpoints and general-detect conditions cause the #DB exception to occur before  the 
instruction is executed, while all other breakpoint and single-stepping conditions cause the #DB 
exception to occur after  the instruction is executed. Table 13 -2 summarizes where the #DB exception 
occurs based on the breakpoint condition. EFFB 8EFFB, EFFC, EFFD, EFFE, 
F000#DB
4 EFFE, EFFF, F000, F001#DBF000 1 F000
F001 2 F001, F002—F005 4 F005, F006, F007, F008
DRn=F004, LEN n=11 (4 Bytes)
EFFB 8EFFB, EFFC, EFFD, EFFE, EFFF, F000, F001
F004–F007— EFFE2 EFFE, EFFF
F000 1 F000
F005 4 F005, F006, F007, F008 #DBTable 13-1. Breakpoint-Setting Examples  (continued)
(hexadecimal)Access Size

F000#DB
F000 1 F000
Note:
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Instruction breakpoints and general-detect conditions have a lower interrupt-priority than the other 
breakpoint and single-stepping conditions (see “Priorities” on page 263). Data-breakpoint conditions 
on the previous  instruction occur before an instruction-breakpoint condition on the next instruction. 
However, if instruction and data breakpoints can occur as a result of executing a single  instruction, the 
instruction breakpoint occurs first (before the instruction is executed), followed by the data breakpoint (after the instruction is executed).
13.1.3.1  Instruction Breakpoints
Instruction breakpoints are set by loading a breakpoint-address register (DR n) with the desired 
instruction virtual-address, and then setting the corresponding DR7 fields as follows:
•Ln or G n is set to 1 to enable the breakpoint for either the local task or all tasks, respectively.
•R/W n is set to 00b to specify that the contents of DR n are to be compared only with the virtual 
address of the next instruction to be executed.
•LEN n must be set to 00b.
When a #DB exception occurs due to an instruction breakpoint-address in DRn, the corresponding B n 
field in DR6 is set to 1 to indicate that a breakpoint condition occurred. The breakpoint occurs before 
the instruction is executed, and the breakpoint-instruction address is pushed onto the debug-handler stack. If multiple instruction breakpoints are set, the debug handler can use the B n field to identify 
which register caused the breakpoint.
Returning from the debug handler causes the breakpoint instruction to be executed. Before returning 
from the debug handler, the rFLAGS[RF] bit should be set to 1 to prevent a re-occurrence of the #DB exception due to the instruction-breakpoint condition. The processor ignores instruction-breakpoint conditions when rFLAGS[RF] = 1, until after the next instruction (in this case, the breakpoint instruction) is executed. After the next instruction is executed, the processor clears rFLAGS[RF]. Table 13-2. Breakpoint Location by Condition
Breakpoint Condition Breakpoint Location
InstructionBefore Instruction is ExecutedGeneral Detect
Data Write Only
After Instruction is Executed1 Data Read or Data WriteI/O Read or I/O Write
Single Step
1
After Instruction is Executed
Task Switch
Note:
1. Repeated operations (REP prefix) can breakpoint between iterations.
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13.1.3.2  Data Breakpoints
Data breakpoints are set by loading a breakpoint-address register (DR n) with the desired data virtual-
address, and then setting the corresponding DR7 fields as follows:
•R/W n is set to 01b to specify that the data virtual-address is compared with the contents of DR n 
only during a memory-write. Setting this field to 11b specifies that the comparison takes place 
during both memory reads and memory writes.
•LEN n is set to 00b, 01b, 11b, or 10b to specify an address-match range of one, two, four, or eight 
bytes, respectively. Long mode must be active to set LEN n to 10b.
When a #DB exception occurs due to a data breakpoint address in DR n, the corresponding B n field in 
DR6 is set to 1 to indicate that a breakpoint condition occurred. The breakpoint occurs after the data-access instruction is executed, which means that the original data is overwritten by the data-access instruction. If the debug handler needs to report the previous data value, it must save that value before setting the breakpoint.
Because the breakpoint occurs after the data-access instruction is executed, the address of the 
instruction following the data-access instruction is pushed onto the debug-handler stack. Repeated string instructions, however, can trigger a breakpoint before all iterations of the repeat loop have completed. When this happens, the address of the string instruction is pushed onto the stack during a #DB exception if the repeat loop is not complete. A subsequent IRET from the #DB handler returns to the string instruction, causing the remaining iterations to be executed. Most implementations cannot report breakpoints exactly for repeated string instructions, but instead report the breakpoint on an iteration later than the iteration where the breakpoint occurred.
13.1.3.3  I/O Breakpoints
I/O breakpoints are set by loading a breakpoint-address register (DR n) with the I/O-port address to be 
trapped, and then setting the corresponding DR7 fields as follows:
•R/W n is set to 10b to specify that the I/O-port address is compared with the contents of DR n only 
during execution of an I/O instruction. This encoding of R/Wn is valid only when debug 
extensions are enabled (CR4[DE] = 1).
•LEN n is set to 00b, 01b, or 11b to specify the breakpoint occurs on a byte, word, or doubleword 
I/O operation, respectively.
The I/O-port address specified by the I/O instruction is zero extended by the processor to 64 bits before comparing it with the DRn registers.
When a #DB exception occurs due to an I/O breakpoint in DR n, the corresponding B n field in DR6 is 
set to 1 to indicate that a breakpoint condition occurred. The breakpoint occurs after the instruction is 
executed, which means that the original data is overwritten by the breakpoint instruction. If the debug handler needs to report the previous data value, it must save that value before setting the breakpoint.
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Because the breakpoint occurs after the instruction is executed, the address of the instruction following 
the I/O instruction is pushed onto the debug-handler stack, in most cases. In the case of INS and OUTS instructions that use the repeat prefix, however, the breakpoint occurs after the first iteration of the repeat loop. When this happens, the I/O-instruction address can be pushed onto the stack during a #DB exception if the repeat loop is not complete. A subsequent return from the debug handler causes the next I/O iteration to be executed. If the breakpoint condition is still set, the #DB exception reoccurs after that iteration is complete.
13.1.3.4  Task-Switch Breakpoints
Breakpoints can be set in a task TSS to raise a #DB exception after a task switch. Software enables a 
task breakpoint by setting the T bit in the TSS to 1. When a task switch occurs into a task with the T bit set, the processor completes loading the new task state. Before the first instruction is executed, the #DB exception occurs, and the processor sets DR6[BT] to 1, indicating that the #DB exception occurred as a result of task breakpoint.
The processor does not clear the T bit in the TSS to 0 when the #DB exception occurs. Software must 
explicitly clear this bit to disable the task breakpoint. Software should never set the T-bit in the debug-handler TSS if a separate task is used for #DB exception handling, otherwise the processor loops on the debug handler.
13.1.3.5  General-Detect Condition
General-detect is a special debug-exception condition that occurs when software running at any 
privilege level attempts to access any of the DR n registers while DR7[GD] is set to 1. When a #DB 
exception occurs due to the general-detect condition, the processor clears DR7[GD] and sets DR6[BD] to 1. Clearing DR7[GD] allows the debug handler to access the DR n registers without causing infinite 
#DB exceptions.
A debugger enables general detection to prevent other software from accessing and interfering with 
the debug registers while they are in use by the debugger. The exception is taken before executing the MOV DRn instruction so that the DRn contents are not altered.
13.1.3.6  Bus Lock Trap
The processor can be configured to generate a #DB exception when a bus lock occurs.  Software 
enables bus lock trap by setting DebugCtl MSR[BLCKDB] (bit 2) to 1.  When bus lock trap is enabled, the processor generates a #DB exception following the successful execution of a locked read-modify-write instruction that requires a bus lock when CPL is > 0.  The processor indicates that this #DB was caused by a bus lock by clearing DR6[BLD] (bit 11).  DR6[11] previously had been defined to be always 1, so DR6[11]=0 uniquely identifies the source of the #DB as a bus lock trap. All other #DB exceptions leave DR6[BLD] unmodified, so to maintain DR6[BLD]=0 as the unique identifier of a bus lock trap, system software should set DR6[BLD]=1 before returning to the interrupted task.
See Section 7.3.3  on page 195 for information on the conditions that cause a bus lock.

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Note that implicit supervisor-level accesses do not generate a bus lock trap, even when CPL is > 0.  An 
implicit supervisor-mode access is one that is considered a supervisor access regardless of the value of CPL. 
13.1.4  Single Stepping
Single-step breakpoints are enabled by setting the rFLAGS[TF] bit to 1. TF may be set by the IRET, POPF or SYSRET instructions, with an IRET executed by a debugger being the typical use case. When IRET sets TF, it causes a #DB exception to be taken immediately after  the target  of the IRET is 
executed, returning control to the debugger and thereby single-stepping the target instruction. Setting TF with a POPF instruction also causes a one-instruction delayed #DB exception. When TF is set by SYSRET however, a #DB exception is taken before  the target instruction executes, hence SYSRET 
does not provide the single-stepping behavior of IRET. 
When a #DB exception occurs due to single stepping, the processor clears rFLAGS[TF] before 
entering the debug handler, so that the debug handler itself is not single stepped. The processor also sets DR6[BS] to 1, which indicates that the #DB exception occurred as a result of single stepping. The rFLAGS image pushed onto the debug-handler stack has the TF bit set, and single stepping resumes when a subsequent IRET pops the stack image into the rFLAGS register.
Single-step breakpoints have a higher priority than external interrupts. If an external interrupt occurs 
during single stepping, control is transferred to the #DB handler first, causing the rFLAGS[TF] bit to be cleared. Next, before the first instruction in the debug handler is executed, the processor transfers control to the pending-interrupt handler. This allows external interrupts to be handled outside of single-step mode.
The INT n, INT3, and INTO instructions clear the rFLAGS[TF] bit when they are executed. If a 
debugger is used to single-step software that contains these instructions, it must emulate them instead 
of executing them.
The single-step mechanism can also be set to single step only control transfers, rather than single step 
every instruction. See “Single Stepping Control Transfers” on page 409 for additional information.
13.1.5  Breakpoint Instruction (INT3)
The INT3 instruction, or the INT n instruction with an operand of 3, can be used to set breakpoints that 
transfer control to the breakpoint-exception (#BP) handler rather than the debug-exception handler. When a debugger uses the breakpoint instructions to set breakpoints, it does so by replacing the first bytes of an instruction with the breakpoint instruction. The debugger replaces the breakpoint instructions with the original-instruction bytes to clear the breakpoint.
INT3 is a single-byte instruction while INT n with an operand of 3 is a two-byte instruction. The 
instructions have slightly different effects on the breakpoint exception-handler stack. See “#BP—
Breakpoint Exception (Vector 3)” on page 248 for additional information on this exception.
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13.1.6  Control-Transfer Breakpoint Features
A control transfers is accomplished by using one of following instructions:
•JMP, CALL, RET
•Jcc, JrCXZ, LOOP cc
•JMPF, CALLF, RETF
•INTn, INT 3, INTO, ICEBP
•Exceptions, IRET
•SYSCALL, SYSRET, SYSENTER, SYSEXIT
•INTR, NMI, SMI, RSM
13.1.6.1  Recording Control Transfers
Software enables control-transfer recording by setting DebugCtl[LBR] to 1. When this bit is set, the 
processor updates the recording MSRs automatically when control transfers occur:
•LastBranchFromIP  and LastBranchToIP Registers —On branch instructions, the 
LastBranchFromIP register is loaded with the segment offset of the branch instruction, and the 
LastBranchToIP register is loaded with the first instruction to be executed after the branch. On interrupts and exceptions, the LastBranchFromIP register is loaded with the segment offset of the interrupted instruction, and the LastBranchToIP register is loaded with the offset of the interrupt or exception handler.
•LastIntFromIP  and LastIntToIP Registers— The processor loads these from the LastBranchFromIP 
register and the LastBranchToIP register, respectively, when most interrupts and exceptions are taken. These two registers are not updated, however, when #DB or #MC exceptions are taken, or the ICEBP instruction is executed.
The processor automatically disables control-transfer recording when a debug exception (#DB) occurs by clearing DebugCtl[LBR] to 0. The contents of the control-transfer recording MSRs are not altered by the processor when the #DB occurs. Before exiting the debug-exception handler, software can set DebugCtl[LBR] to 1 to re-enable the recording mechanism.
Debuggers can trace a control transfer backward from a bug to its source using the recording MSRs 
and the breakpoint-address registers. The debug handler does this by updating the breakpoint registers from the recording MSRs after a #DB exception occurs, and restarting the program. The program takes a #DB exception on the previous control transfer, and this process can be repeated. The debug handler cannot simply copy the contents of the recording MSR into the breakpoint-address register. The recording MSRs hold segment offsets, while the debug registers hold virtual (linear) addresses. The debug handler must calculate the virtual address by reading the code-segment selector (CS) from the interrupt-handler stack, then reading the segment-base address from the CS descriptor, and adding that base address to the offset in the recording MSR. The calculated virtual-address can then be used as a breakpoint address.
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13.1.6.2  Single Stepping Control Transfers
Software can enable control-transfer single stepping by setting DebugCtl[BTF] to 1 and rFLAGS[TF] 
to 1. The processor automatically disables control-transfer single stepping when a debug exception (#DB) occurs by clearing DebugCtl[BTF]. rFLAGS[TF] is also cleared when a #DB exception occurs. Before exiting the debug-exception handler, software must set both DebugCtl[BTF] and rFLAGS[TF] to 1 to restart single stepping.
When enabled, this single-step mechanism causes a #DB exception to occur on every branch 
instruction, interrupt, or exception. Debuggers can use this capability to perform a “coarse” single step across blocks of code (bound by control transfers), and then, as the problem search is narrowed, switch into a “fine” single-step mode on every instruction (DebugCtl[BTF] = 0 and rFLAGS[TF] = 1).
Debuggers can use both the single-step mechanism and recording mechanism to support full backward 
and forward tracing of control transfers.
13.1.7  Debug Breakpoint Address Masking
The Breakpoint Address Extension feature extends the DR[0-3] breakpoint capabilities. Processors with this extension support address mask registers corresponding to each of the DR[0-3] breakpoint registers, in the form of DR[0-3]_ADDR_MASK MSRs. These masks may be used to increase the 
range of breakpoints by excluding address bits from the breakpoint match. Each bit set to one excludes the corresponding address bit from the breakpoint comparison. Mask bits 11:0 may be used to expand instruction fetch breakpoint ranges up to a 4KB page, while mask bits 31:12 have no effect on instruction breakpoints. For DR0 only, the full mask field (31:0) may be used to qualify data breakpoint matches. This extension is signified by CPUID Fn8000_0001_ECX[26]=1.
An additional extension expands the data breakpoint masking capability of DR0 to the other 
breakpoint registers, and extends instruction breakpoint masking to bits 31:0 for all registers. This is signified by CPUID Fn8000_0001_ECX[30]=1.
13.1.8  Last Branch Record Stack
Processors with CPUID Fn8000_0022_EAX[LbrStack] = 1 support Last Branch Record Stack (LBR Stack). The LBR Stack records the From and To IP for the LBR_ SIZE = CPUID Fn8000_0022_EBX[LbrStackSize] most recent control-transfer instructions. 
LBR Stack recording is enabled by setting DebugExtnCtl [LBRV2EN] = 1. LBR Stack recording is 
independent of Last Branch Record (LBR). DebugCtl[LBR] does not need to be set to 1 for the processor to start recording to the LBR Stack. 
Software can access the contents of the LBR stack using LastBranchStackFromIp and 
LastBranchStackToIp MSRs. The format of these MSRs is shown in Figure 13 -7 on page 399 and 
Figure 13 -8 on page 400.
Table 13 -3, “Types of Branch Records” shows the types of branch records based on the values of 
LastBranchStackToIp[SPEC] and LastBranchStackToIp[V].
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Software can use the LastBranchStackSelect MSR (Figure 13 -9 on page 401) to specify the branch 
types for which LBR Stack recording is suppressed. 
13.2 Performance Monitoring Counters

The AMD64 architecture supports a set of hardware-based performance-monitoring counters (PMCs) 
that can be utilized to measure the frequency or duration of certain hardware events. MSRs allow the selection of events to be monitored and include a set of corresponding counter registers that accumulate a count of monitored events. 
Software tools can use these counters to identify performance bottlenecks, such as sections of code 
that have high cache-miss rates or frequently mispredicted branches. This information can then be used as a guide for improving overall performance or eliminating performance problems through software optimizations or hardware-design improvements.
Software performance analysis tools often require a means to time-stamp an event or measure elapsed 
time between two events. The time-stamp counter provides this capability. See Section 13.2.4 “Time-Stamp Counter” on page 422.
The registers used in support of performance monitoring are model-specific registers (MSRs). See 
“Model-Specific Registers (MSRs)” on page 59 for a general discussion of MSRs and “Performance-Monitoring MSRs” on page 724 for a listing of the performance-monitoring MSR numbers and their reset values.
13.2.1  Performance Counter MSRs
The legacy architecture defines  four performance counters (PerfCtr n) and corresponding event-select 
registers (PerfEvtSel n). Extensions add Northbridge and L2 cache performance monitoring counters. 
Each *PerfCtr register counts events selected by the corresponding *PerfEvtSel register. Table 13-3. Types of Branch Records
LastBranchStackToIp[V] LastBranchStackToIp[SPEC] Description of LBR Stack entry
1 0 Normal recorded branch.
1 1 Branch was recorded when a speculative 
performance feature was active and successful.
0 1 Branch was recorded, but the speculative performance feature was not successful.
0 0 No branch has yet been recorded in this entry since SW last cleared the V and SPEC bits. 
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An architectural extension augments the number of performance and event-select registers by adding 
two more processor counter / event-select pairs. Further extensions add four counter / event-select pairs dedicated to counting Northbridge (NB) events and four counter / event-select pairs dedicated to counting L2 cache (L2I) events. 
Core logic includes instruction execution pipelines, execution units, and caches closest to the 
execution hardware. The NB includes logic that routes data traffic between caches, external I/O devices, and a system memory controller which reads and writes system memory (usually implemented as external DRAM). The L2 cache is a cache that is further away from the processor core than the L1 cache or caches. This cache is normally larger than the L1 cache(s) and requires more processor cycles to access. An L2 cache may be shared between physical processor cores.
All implementations support the base set of four performance counter / event-select pairs. Support for 
the extended performance monitoring registers and the performance-related events selectable via the *PerfEvtSel registers vary by implementation and are described in the BIOS and Kernel Developer’s 
Guide (BKDG) or Processor Programming Reference Manual (PPR)  for that processor. 
Core performance counters are used to count processor core events, such as data-cache misses, or the duration of events, such as the number of clocks it takes to return data from memory after a cache miss. During event counting, hardware increments a counter each time it detects an occurrence of a specified event. During duration measurement, hardware counts the number of processor clock cycles required to complete a specific hardware function. 
NB performance counters are used to count events that occur within the Northbridge. The L2I 
performance counters are used to count events associated with accessing the L2 cache.
Performance counters and event-select registers are implemented as machine-specific registers 
(MSRs). The base set of four PerfCtr and PerfEvtSel registers are accessed via a legacy set of MSRs and the extended set of six core PerfCtr / PerfEvtSel registers are accessed via a different set. Extended core PerfCtr / PerfEvtSel registers 0–3 alias the legacy set. 
Support for the extended set of core PerfCtr registers and associated PerfEvtSel registers, as well as the 
sets of Northbridge and L2 cache counter / event-select pairs are indicated by CPUID feature bits. See “Detecting Hardware Support for Performance Counters” on page 420. The MSR address assignments for the legacy and extended performance / event-select pairs are listed in Appendix A, Section A.6, “Performance-Monitoring MSRs” on page 724.
The length, in bits, of the performance counters is implementation-dependent, but the maximum 
length supported is 64 bits. Figure 13 -10 shows the format of the performance counter registers.
Figure 13 -10. Performance Counter Format
63 0
event or duration count
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For a given processor, all implemented performance counter registers can be read and written by 
system software running at CPL = 0 using the RDMSR and WRMSR instructions, respectively. The architecture also provides an instruction, RDPMC, which may be employed by user-mode software to read the architected core, Northbridge, and L2 performance counters.
The RDPMC instruction loads the contents of the architected performance counter register specified 
by the index value contained in the ECX register, into the EDX register and the EAX register. The high 32 bits are returned in EDX, and the low 32 bits are returned in EAX. RDPMC can be executed only at CPL = 0, unless system software enables use of the instruction at all privilege levels. RDPMC can be 
enabled for use at all privilege levels by setting CR4[PCE] (the performance-monitor counter-enable  
bit) to 1. When CR4[PCE] = 0 and CPL > 0, attempts to execute RDPMC result in a general-
protection exception (#GP). For more information on the RDPMC instruction, see the instruction reference page in V olume 3 of this manual.
Writing the performance counters can be useful if software wants to count a specific number of events, 
and then trigger an interrupt when that count is reached. An interrupt can be triggered when a performance counter overflows (see “Counter Overflow” on page 421 for additional information). Software should use the WRMSR instruction to load the count as a two’s-complement negative number into the performance counter. This causes the counter to overflow after counting the appropriate number of times.
The performance counters are not guaranteed to produce identical measurements each time they are 
used to measure a particular instruction sequence, and they should not be used to take measurements of very small instruction sequences. The RDPMC instruction is not serializing, and it can be executed out-of-order with respect to other instructions around it. Even when bound by serializing instructions, the system environment at the time the instruction is executed can cause events to be counted before the counter value is loaded into EDX:EAX. The following sections describe the core performance event-select and the Northbridge performance event-select registers.
Core Performance Event-Select Registers
The core performance event-select registers (PerfEvtSeln) are 64-bit registers used to specify the 
events counted by the core performance counters, and to control other aspects of their operation. Each performance counter supported by the implementation has a corresponding event-select register that controls its operation. Figure 13 -11 below shows the format of the core PerfEvtSel register.
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Figure 13-11. Core Performance Event-Select Register (PerfEvtSeln)
The fields shown in Figure 13 -11 above are further described below:
•HG_ONLY (Host/Guest Only)—Bits 41:40, read/write. This field qualifies events to be counted 
based on virtualization operating mode (guest or host). The following table defines how HG_ONLY qualifies the counting of events:63 42 41 40 39 36 35 32
ReservedHG_ 
ONLYReservedEVENT_
SELECT[11:8]
31 24 23 22 21 20 19 18 17 16 15 8 7 0
CNT_MASK
INV
EN
Reserved
INT
Reserved
ED G E
OS
USRUNIT_MASK EVENT_SELECT[7:0]
63:42 Reserved RAZ
41:40 HG_ONLY Host/Guest Only R/W
39:36 Reserved RAZ
35:32 EVENT_SELECT[11:8] Event select bits 11:8 R/W
31:24 CNT_MASK Counter Mask R/W
23 INV Invert Comparison R/W
22 EN Counter Enable R/W
21 Reserved RAZ
20 INT Interrupt Enable R/W
19 Reserved RAZ
18 EDGE Edge Detect R/W
17 OS Operating-System Mode R/W
16 USR User Mode R/W
15:8 UNIT_MASK Unit Mask R/W
7:0 EVENT_SELECT[7:0] Event select bits 7:0 R/W
Table 13-4. Host/Guest Only Bits
Host Mode
(Bit 41)Guest Mode
(Bit 40)Events Counted
0 0 All events, irrespective of guest or host mode

CNT_MASK
INV
EN
Reserved
INT
Reserved
ED G E
OS
Host Mode
0 1 Guest events, if EFER[SVME] = 1
1 0 Host events, if EFER[SVME] = 1
1 1 Guest and host events, if EFER[SVME] = 1
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•EVENT_SELECT[11:8] (Event Select) —Bits 35:32, read/write. This field extends the 
EVENT_SELECT field from 8 bits to 12 bits. See EVENT_SELECT[7:0] below.
•CNT_MASK (Counter Mask) —Bits 31:24, read/write. Used with INV bit to control the counting of 
multiple events that occur within one clock cycle. The table below describes this:
•INV (Invert Comparison), read/write. Used with CNT_MASK field to control the counting of 
multiple events within one clock cycle. See table above.
•EN (Counter Enable), read/write. Software sets this bit to 1 to enable the PerfEvtSeln register, and counting in the corresponding PerfCtr n register. Clearing this bit to 0 disables the register pair.
•INT (Interrupt Enable), read/write. Software sets this bit to 1 to enable an interrupt to occur when the performance counter overflows (see “Counter Overflow” on page 421 for additional information). Clearing this bit to 0 disables the triggering of the interrupt.
•EDGE (Edge Detect), read/write. Software sets this bit to 1 to count the number of edge transitions from the negated to asserted state. This feature is useful when coupled with event-duration monitoring, as it can be used to calculate the average time spent in an event. Clearing this bit to 0 disables edge detection.
•OS (Operating-System Mode) and USR (User Mode), read/write. Software uses these bits to control the privilege level at which event counting is performed according to Table 13 -6. 
•UNIT_MASK (Unit Mask)—Bits 15:8, read/write. This field further specifies or qualifies the event specified by the EVENT_SELECT field. Depending on implementation, it may be used to specify Table 13-5. Count Control Using CNT_MASK and INV
CNT_MASK INV Increment Value
00h –Corresponding PerfCtr[ n] register is incremented by the number of events occurring in a 
clock cycle. If the number of events is equal to or greater than 32, the count register is 
incremented by 32.
FFh:01h10Corresponding PerfCtr[n] register is incremented by 1, if the number of events occurring in a clock cycle is greater than or equal to the CNT_MASK value.
1Corresponding PerfCtr[n]register is incremented by 1, if the number of events occurring in a clock cycle is less than the CNT_MASK value.
Note 1: Maximum CNT_MASK value (in the range FFh:01h is implementation dependent. Consult applicable BIOS and Ker -
nel Developer’s Guide (BKDG) or Processor Programming Reference Manual (PPR) .
Table 13 -6. Operating-System Mode and User Mode Bits
OS
(Bit 17)USR
(Bit 16)Event Counting
0 0 No counting.
0 1 Only at CPL > 0.
1 0 Only at CPL = 0.
1 1 At all privilege levels.
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a sub-event within the class specified by the EVENT_SELECT field or it may act as bit mask and 
be used to specify a number of events within the class to be monitored simultaneously.
•EVENT_SELECT[7:0] (Event Select [7:0]) —Bits 7:0, read/write. This field concatenated with 
EVENT_SELECT[11:8] specifies the event or event duration to be counted by the corresponding PerfCtr[ n] register. The events that can be monitored are implementation dependent. In some 
implementations, support for a specific EVENT_SELECT value may restricted to a subset of the available performance counters. For more information, see the BIOS and Kernel Developer’s 
The core performance event-select registers can be read and written only by system software running at CPL = 0 using the RDMSR and WRMSR instructions, respectively. Any attempt to read or write these registers at CPL > 0 causes a general-protection exception to occur.
Core Performance Global Control Register
Core Performance Counter Global Control Register (PerfCntGlobalCtl) is a 64-bit register used to 
provide additional enable bits for each of the available core performance counters (PerfCnt n). The 
number of available core performance counters is reported by CPUID Fn8000_0022_EBX[NumCorePmc]. PerfCntGlobalCtl provides a way to simultaneously enable or disable multiple core performance counters with a single WRMSR instruction. To enable PerfCnt n, both bit n of PerfCntGlobalCtl and the EN field of the counter's PerfEvtSel register must be 
set to 1. Clearing either bit causes the corresponding count register to stop counting.
Figure 13 -12 shows the format of the core PerfCntGlobalCtl register.
Figure 13-12. Performance Counter Global Control (PerfCntGlobalCtl)
Core Performance Counter Status Registers
A set of three registers is provided to monitor and manage core performance counter status. The Core 
Performance Counter Status Register (PerfCntGlobalStatus) contains overflow bits for the Core Performance Counters and freeze status bits for the LBR stack and performance counters. Software can clear individual status bits by writing 1’s to corresponding bit positions in the PerfCntGlobalStatusClr register, and set individual status bits by writing 1’s to corresponding bit positions in the PerfCntGlobalStatusSet register. Hardware normally sets these bits; setting or clearing them with software may cause certain hardware actions as described below. 63 5 0
Reserved EN
63:6 Reserved RAZ
5:0 EN Global enable for PerfCnt[5:0] R/W
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Performance Counter Global Status Register
Figure 13-13. Performance Counter Global Status Register (PerfCntGlobalStatus)
The fields shown in Figure 13 -13 are further described below:
•Performance Counter Freeze (PMCF)—Bit 59, read-only. When set, this indicates that the Core 
Performance Counter registers have been frozen due to an overflow interrupt triggered for at least one of the core performance counters. This feature is enabled via DebugCtl[FPCI] as described in “Debug-Control MSR (DebugCtl)” on page 396. Software must use 
PerfCntGlobalStatusClr[C_PMCF] to clear this bit to allow the Core Performance Counters to resume counting.
•Last Branch Record Stack Freeze (LBRSF) —Bit 58, read-only. When set, this indicates that the 
Last Branch Record Stack has been frozen due to an overflow interrupt triggered for at least one of the core performance counters. This feature is enabled via DebugCtl[FLBRI] as described in “Debug-Control MSR (DebugCtl)” on page 396. Software must use 
PerfCntGlobalStatusClr[C_LBRSF] to clear this bit to allow the Last Branch Record Stack to resume recording branches.
•Core Performance Counter Overflow (CNT_OF)—Bits 5:0, read-only. Each available Core Performance Counter corresponds to one bit in this field. When set, it indicates that the corresponding performance counter has overflowed. The CNT_OF bit will be set for a counter even when the counter is not configured to trigger an interrupt on overflow. Software must use PerfCntGlobalStatusSet[C_CNT_OF] to clear these indications.
Software may use PerfCntGlobalStatusSet and PerfCntGlobalStatusClr registers to modify the contents of the PerfCntGlobalStatus register for context switching purposes.63 60 59 58 57 6 5 0
Reserved
PMCF
LBRSFReserved CNT_OF
63:60 Reserved RO
59 PMCF Performance Counter Freeze RO
58 LBRSF Last Branch Record Stack Freeze RO
57:6 Reserved RO
5:0 CNT_OF Counter overflow for PerfCnt[5:0] RO
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Performance Counter Global Status Set Register
Figure 13-14. Performance Counter Global Status Set Register 
(PerfCntGlobalStatusSet)
The fields shown in Figure 13 -14 are further described below:
•Set Core Performance Counter Freeze (S_PMCF) —Bit 59, write-only. When written as 1, 
PerfCntGlobalStatus[PMCF] is set to 1 and the Core Performance Monitor Counters are frozen.
•Set Last Branch Record Stack Freeze (S_LBRSF) —Bit 58, write-only. When written as 1, 
PerfCntGlobalStatus[LBRSF] is set to 1 and the Last Branch Record Stack is frozen.
•Set Core Performance Counter Overflow (S_CNT_OF)—Bits 5:0, write-only. For each bit written 
as 1, the corresponding bit in PerfCntGlobalStatus[CNT_OF] is set to 1. Setting a bit in PerfCntGlobalStatus[CNT_OF] through PerfCntGlobalStatusSet[CNT_OF] does not trigger an interrupt, freeze core performance counters, freeze the Last Branch Record stack or trigger any other action that the hardware may take when a core performance counter overflows.63 60 59 58 57 6 5 0
Reserved
S_PMCF
S_LBRSFReserved S_CNT_OF
63:60 Reserved WO
59 S_PMCF Set Performance Counter Freeze WO
58 S_LBRSF Set Last Branch Record Freeze WO
57:6 Reserved WO
5:0 S_CNT_OFSet selected bits of 
PerfCntGlobalStatus[CNT_OF]WO

Reserved
S_PMCF
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Performance Counter Global Status Clear Register
Figure 13-15. Performance Counter Global Status Clear Register 
(PerfCntGlobalStatusClr)
The fields shown in Figure 13 -15 are further described below:
•Clear Performance Counter Freeze (C_PMCF) —Bit 59, write-only. When written as 1, 
PerfCntGlobalStatus[PMCF] is cleared to 0 and core performance counters, that are enabled to 
count, continue counting.
•Clear Last Branch Record Stack Freeze (C_LBRSF)—Bit 58, write-only. When written as 1, PerfCntGlobalStatus[LBRSF] is cleared to 0 and the Last Branch Record Stack continues to record branches if enabled.
•Clear Core Performance Counter Overflow (C_CNT_OF) —Bits 5:0, write-only. For each bit 
written as 1, the corresponding bit in PerfCntGlobalStatus[CNT_OF] is cleared to 0. Software should clear the Performance Counter Overflow bits when:
- Handling a core performance counter overflow interrupt- Disabling a core performance counter- Resetting a core performance counter
Northbridge Performance Event-Select Registers
The Northbridge (NB) performance event-select registers (NB_PerfEvtSel n) are 64-bit registers used 
to specify the events counted by the Northbridge performance counters, and to control other aspects of 
their operation. Each performance counter supported by the implementation has a corresponding event-select register that controls its operation. Figure 13 -16 below shows the format of the 
NB_PerfEvtSel n register.63 60 59 58 57 6 5 0
Reserved
C_PMCF
C_LBRSFReserved C_CNT_OF
59 C_PMCF Clear Performance Counter Freeze WO
58 C_LBRSF Clear Last Branch Record Freeze WO
5:0 C_CNT_OFClear selected bits of 
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Figure 13-16. Northbridge Performance Event-Select Register (NB_PerfEvtSel n)
The Northbridge performance event-select registers can be read and written only by system software 
running at CPL = 0 using the RDMSR and WRMSR instructions, respectively. Any attempt to read or write these registers at CPL > 0 causes a general-protection exception to occur.
For more information on the defined fields within the NB_PerfEvtSel n registers, see the BIOS and 
Kernel Developer’s Guide (BKDG) or Processor Programming Reference Manual (PPR)  applicable 
to your product.
L2 Cache (L2I) Performance Event-Select Registers
The L2 cache performance event-select registers (L2I_PerfEvtSel n) are 64-bit registers used to specify 
the events counted by the L2 cache performance counters, and to control other aspects of their 
operation. Each performance counter supported by the implementation has a corresponding event-select register that controls its operation. Figure 13 -17 below shows the format of the L2I_PerfEvtSel n 
register.63 36 35 32
ReservedEVENT_ 
31 23 22 21 20 19 16 15 8 7 0
Reserved
EN
Reserved
INTReserved UNIT_MASK EVENT_SELECT[7:0]
63:36 Reserved RAZ
35:32 EVENT_SELECT[11:8] Event select bits [11:8] R/W
31:23 Reserved RAZ
19:16 Reserved RAZ
7:0 EVENT_SELECT[7:0] Event select bits [7:0] R/W
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Figure 13-17. L2 Cache Performance Event-Select Register (L2I_PerfEvtSel n)
The L2 cache performance event-select registers can be read and written only by system software 
For more information on the defined fields within the L2I_PerfEvtSel n registers, see the BIOS and 
Instructions Retired Performance counter
This is a dedicated counter that is always counting instructions retired. It exists at MSR address 
C000_00E9. It is enabled by setting a 1 to HWCR[30] and its support is indicated by CPUID Fn8000_0008_EBX[1].
13.2.2  Detecting Hardware Support for Performance Counters
Support for extended core, Northbridge, and L2 cache performance counters is implementation-dependent. Support on a given processor implementation can be verified using the CPUID instruction.
CPUID Fn8000_0001_ECX[PerfCtrExtCore] = 1 indicates support for the six architecturally defined 
extended core performance counters and their associated event-select registers. CPUID Fn8000_0001_ECX[PerfCtrExtNB] = 1 indicates support for the four architecturally defined Northbridge performance counter / event-select pairs and 63 36 35 32
Reserved
EN
Reserved
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CPUID Fn8000_0001_ECX[PerfCtrExtL2I] = 1 indicates support for the four architecturally defined 
L2 cache performance counter / event-select pairs. 
See Section 3.3, “Processor Feature Identification,” on page 71 for more information on using the 
CPUID instruction.
Processors that return a non-zero value in CPUID Fn8000_0022_EBX[NumPerfCtrCore] report the 
number of available core performance counters in CPUID Fn8000_0022_EBX[NumPerfCtrCore].
Processors that return a non-zero value in CPUID Fn8000_0022_EBX[NumPerfCtrNB] report the 
number of available Northbridge performance counters in CPUID Fn8000_0022_EBX[NumPerfCtrNB]. 
A given processor may implement other performance measurement MSRs with similar capabilities 
even if one or more of the optional architected facilities are not supported.
CPUID Fn8000_0022_EAX[PerfMonV2] = 1 indicates support for PerfCntGlobalCtl MSR, 
PerfCntGlobalStatus MSR, PerfCntGlobalStatusClr MSR and PerfCntGlobalStatusSet MSR. 
CPUID Fn8000_0022_EAX[LbrAndPmcFreeze] = 1 indicates support for LBR Stack and Core 
Performance Counter Freeze on PMC overflow.
13.2.3  Using Performance Counters
13.2.3.1  Starting and Stopping
Performance measurement using the PerfCtr n, NB_PerfCtrn, and L2I_PerfCtrn registers is initiated by 
setting the corresponding *PerfEvtSel n[EN] bit to 1. Counting is stopped by clearing the 
*PerfEvtSel n[EN] bit. Software must initialize the remaining *PerfEvtSeln fields with the appropriate 
setup information before or at the same time EN is set. Counting begins when the WRMSR instruction 
that sets *PerfEvtSeln[EN] to 1 completes execution. Counting stops when the WRMSR instruction that clears the EN bit completes execution.
13.2.3.2  Counter Overflow
Some processor implementations support an interrupt-on-overflow capability that allows an interrupt 
to occur when one of the *PerfCtr n registers overflows. The source and type of interrupt is 
implementation dependent. Some implementations cause a debug interrupt to occur, while others make use of the local APIC to specify the interrupt vector and trigger the interrupt when an overflow occurs. Software enables or disables the triggering of an interrupt on counter overflow by setting or clearing the *PerfEvtSel n[INT] bit.
If system software makes use of the interrupt-on-overflow capability, an interrupt handler must be provided that can record information relevant to the counter overflow. Before returning from the interrupt handler, the performance counter can be re-initialized to its previous state so that another interrupt occurs when the appropriate number of events are counted.
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13.2.4  Time-Stamp Counter
The time-stamp counter (TSC) is used to count processor-clock cycles. The TSC is cleared to 0 after a 
processor reset. After a reset, the TSC is incremented at a rate corresponding to the baseline frequency of the processor (which may differ from actual processor frequency in low power modes of operation). Each time the TSC is read, it returns a monotonically-larger value than the previous value read from the TSC. When the TSC contains all ones, it wraps to zero. The TSC in a 1-GHz processor counts for almost 600 years before it wraps. Figure 13 -18 shows the format of the 64-bit time-stamp counter 
(TSC). 
Figure 13-18. Time-Stamp Counter (TSC)
The TSC is a model-specific register that can also be read using one of the special read time-stamp

(TSC). 
The TSC is a model-specific register that can also be read using one of the special read time-stamp 
counter  instructions, RDTSC (Read Time-Stamp Counter) or RDTSCP (Read Time-Stamp Counter 
and Processor ID). The RDTSC and RDTSCP instructions load the contents of the TSC into the EDX register and the EAX register. The high 32 bits are loaded into EDX, and the low 32 bits are loaded into EAX. The RDTSC and RDTSCP instructions can be executed at any privilege level and from any processor mode. However, system software can disable the RDTSC or RDTSCP instructions for programs that run at CPL > 0 by setting CR4[TSD] (the time-stamp disable bit) to 1. When 
CR4[TSD] = 1 and CPL > 0, attempts to execute RDSTC or RDSTCP result in a general-protection 
exception (#GP).
The TSC register can be read and written using the RDMSR and WRMSR instructions, respectively. 
The programmer should use the CPUID instruction to determine whether these features are supported. If EDX bit 4 (as returned by CPUID function 1) is set, then the processor supports TSC, the RDTSC instruction and CR4[TSD]. If EDX bit 27 returned by CPUID function 8000_0001h is set, then the processor supports the RDTSCP instruction.
The TSC register can be used by performance-analysis applications, along with the performance-
monitoring registers, to help determine the relative frequency of an event or its duration. Software can also use the TSC to time software routines to help identify candidates for optimization. In general, the TSC should not be used to take very short time measurements, because the resulting measurement is not guaranteed to be identical each time it is made. The RDTSC instruction (unlike the RDTSCP instruction) is not serializing, and can be executed out-of-order with respect to other instructions around it. Even when bound by serializing instructions, the system environment at the time the instruction is executed can cause additional cycles to be counted before the TSC value is loaded into EDX:EAX.
When using the TSC to measure elapsed time, programmers must be aware that for some 
implementations, the rate at which the TSC is incremented varies based on the processor power management state (Pstate). For other implementations, the TSC increment rate is fixed and is not 63 0
TSC
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subject to power-management related changes in processor frequency. CPUID Fn 
8000_0007h_EDX[TscInvariant] = 1 indicates that the TSC increment rate is a constant.
13.3 Instruction-Based Sampling
Instruction-Based Sampling (IBS) is a hardware facility that can be used to gather specific metrics related to processor instruction fetch and instruction execution activity. Data capture is performed by hardware at a sampling interval specified by values programmed in IBS sampling control registers. The IBS facility can be utilized by software to perform code profiling based on statistical sampling. 
There are two independent data gathering components of IBS: instruction fetch sampling and 
instruction execution sampling. Instruction fetch sampling provides information about instruction address translation look-aside buffer (ITLB) and instruction cache behavior for a randomly selected fetch block, under the control of the IBS Fetch Control Register. Instruction execution sampling provides information about instruction execution behavior by tracking the execution of a single operation (op) that is randomly selected, under the control of the IBS Execution Control Register.
When the programmed interval for fetch sampling has expired, the fetch sampling component of IBS 
selects and tags the next fetch block. IBS hardware records specific performance information about the tagged fetch. In a similar manner, when the programmed interval for op sampling has expired, the op sampling component of IBS selects and tags the next op being dispatched for execution. 
When data collection for the tagged fetch or op is complete, the hardware signals an interrupt. An 
interrupt handler can then read the performance information that was captured for the fetch or op in IBS MSRs, save it, and re-enable the hardware to take the next sample.
More information about the IBS facility and how software can use it to perform code profiling can be 
found in the Software Optimization Guide for your specific product. The Software Optimization Guide 
for AMD Family 15h Processors  is order #47414. 
Support for the IBS feature is indicated by the CPUID Fn 8000_0001h_ECX[IBS]. For more information on using the CPUID instruction to obtain processor implementation information, see Section 3.3, “Processor Feature Identification,” on page 71.
13.3.1  IBS Fetch Sampling
When a processor fetches an instruction, it is actually reading a contiguous range of instruction bytes that contains the instruction from memory or from cache. This range of bytes loaded by the processor in one operation is called a fetch block . The size and address-alignment characteristics of the fetch 
block are implementation-dependent. In the following discussion, the term instruction fetch  or simply 
fetch  refers to this operation of reading a fetch block.
Instruction fetch sampling records the following performance information for each tagged fetch:
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•If the fetch completed or was aborted
•The number of core clock cycles spent on the fetch
•If the fetch hit or missed the instruction cache
•If the instruction fetch hit or missed the instruction TLBs
•The fetch address translation page size
•The linear and physical address associated with the fetch
IBS selects and tags a fetch at a programmable rate. When enabled by the IBS Fetch Control Register 
(IbsFetchEn = 1 and IbsFetchVal = 0), an internal 20-bit fetch interval counter increments for every attempted fetch operation. When the value in bits 19:4 of the fetch counter equal the value in the IbsFetchMaxCnt field of the IBS Fetch Control Register, the next fetch block is tagged for data collection.
When the tagged fetch completes or is aborted, the status of the fetch is written to the IBS Fetch 
Control Register and the associated linear address and physical address are written in the IBS Fetch Linear Address Register and IBS Fetch Physical Address Register, respectively. The IbsFetchVal bit is set in the IBS Fetch Control Register and an interrupt is generated as specified by the local APIC.
The interrupt service routine saves the performance information stored in the IBS fetch registers. 
Software can then initiate another sample by resetting the IbsFetchVal bit in the IBS Fetch Control Register. Hardware initializes bits 19:4 of the internal fetch interval counter with the value in the IbsFetchCnt field. If the IbsFetchCtl[IbsRandEn] bit is set, bits 3:0 of the fetch interval counter are re-initialized by hardware with a pseudo-random value; otherwise bits 3:0 are cleared.
13.3.2  IBS Fetch Sampling Registers
The IBS fetch sampling registers consist of the status and control register (IBS Fetch Control Register) and the associated fetch address registers (IBS Fetch Linear Address Register and IBS Fetch Physical Address Register). The IBS fetch sampling registers are accessed using the RDMSR and WRMSR instructions.
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IBS Fetch Control Register
Figure 13-19. IBS Fetch Control Register(IbsFetchCtl)
The fields shown in Figure 13 -19 are further described below:
•IbsFetchL3Miss (IBS Fetch L3 Cache Miss) —Bit 61, read/write. This bit is set when the tagged 
fetch missed in the L3 cache. This bit is supported when CPUID 
Fn8000_001B_EAX[IbsL3MissFiltering](bit 11) = 1.
•IbsFetchOcMiss (IBS Fetch Op Cache Miss) —Bit 60, read/write. This bit is set if the tagged fetch 
missed in the Op Cache. This bit is supported when CPUID Fn8000_001B_EAX[IbsL3MissFiltering](bit 11) = 1.
•IbsL3MissOnly (IBS Fetch L3 Miss Filtering) —Bit 59, read/write. This bit controls L3 Miss 
Filtering. When set, Fetch IBS only sends interrupts for samples with an L3 miss. See Section 13.3.5, “IBS Filtering,” on page 435 for a description of Fetch IBS Filtering.63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 32Reserved
IbsFetchL3Miss
IbsFetchOcMiss
IbsL3MissOnly
Reserved
IbsRandEn
Reserved
IbsL1TlbMiss
IbsL1TlbPgSz
IbsPhyAddrValid
IbsIcMiss
IbsFetchComp
IbsFetchVal
IbsFetchEnIbsFetchLat
31 16 15 0
IbsFetchCnt IbsFetchMaxCnt
63:62 Reserved RAZ
61 IbsFetchL3Miss IBS Fetch L3 Cache Miss R/W
60 IbsFetchOcMiss IBS Fetch Op Cache Miss R/W
59 IbsL3MissOnly IBS Fetch L3 Miss Filtering R/W
58 Reserved RAZ
57 IbsRandEn IBS Randomize Tagging Enable R/W
56 Reserved RAZ
55 IbsL1TlbMiss IBS Fetch L1 TLB Miss R/W
54:53 IbsL1TlbPgSz IBS Fetch L1 TLB Page Size R/W
52 IbsPhyAddrValid IBS Fetch Physical Address Valid R/W

Reserved
IbsRandEn
Reserved
IbsIcMiss
31 16 15 0
51 IbsIcMiss IBS Instruction Cache Miss R/W
50 IbsFetchComp IBS Fetch Complete R/W
49 IbsFetchVal IBS Fetch Valid R/W
48 IbsFetchEn IBS Fetch Enable R/W
47:32 IbsFetchLat IBS Fetch Latency R/W
31:16 IbsFetchCnt IBS Fetch Count R/W
15:0 IbsFetchMaxCnt IBS Fetch Maximum Count R/W
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•IbsRandEn (IBS Randomize Tagging Enable) —Bit 57, read/write. Software sets this bit to 1 to add 
variability to the interval at which fetch operations are selected for tagging. When set, bits 3:0 of 
the fetch interval counter are set to a pseudo-random value when the IbsFetchCtl register is written. Clearing this bit causes bits 3:0 of the fetch interval counter to be reset to zero.
•IbsL1TlbMiss (IBS Fetch L1 TLB Miss)—Bit 55, read/write. This bit is set if the tagged fetch missed in the L1 TLB.
•IbsL1TlbPgSz[1:0]
 (IBS Fetch L1 TLB Page Size) —Bits 54:53, read/write. This field indicates the 
page size of the translation in the L1 TLB for the tagged fetch. This field is valid only if IbsPhyAddrVal = 1. The table below defines the encoding of this two-bit field:
Some implementations might not support all page sizes. Note: The page size in the L1 TLB might 
not match the page size in the page table. 
•IbsPhyAddrValid (IBS Fetch Physical Address Valid)—Bit 52, read/write. This bit is set if the physical address of the tagged fetch is valid. When this bit is set, the IbsL1TlbPgSz field and the contents of the IBS Fetch Physical Address Register (see definition of this register below) are both valid.
•IbsIcMiss (IBS Instruction Cache Miss)—Bit 51, read/write. This bit is set if the tagged fetch missed in the instruction cache.
•IbsFetchComp (IBS Fetch Complete) —Bit 50, read/write. This bit is set if the tagged fetch 
completes and data is available for use by the instruction decoder.
•IbsFetchVal (IBS Fetch Valid)—Bit 49, read/write. This bit is set if the tagged fetch either completes or is aborted. When the bit is set, captured data for the tagged fetch is available and the fetch interval counter stops. An interrupt is generated as specified by the local APIC. The interrupt handler should read and save the captured performance data before clearing the bit.
•IbsFetchEn (IBS Fetch Enable)—Bit 48, read/write. Software sets this bit to enable fetch sampling. Clearing this bit to 0 disables fetch sampling.
•IbsFetchLat[15:0] (IBS Fetch Latency) —Bits 47:32, read/write. This 16-bit field indicates the 
number of core clock cycles from the initiation of the fetch to the delivery of the instruction bytes to the core. If the fetch is aborted before it completes, this field returns the number of clock cycles from the initiation of the fetch to its abortion.
•IbsFetchCnt[15:0] (IBS Fetch Count)—Bits 31:16, read/write. This 16-bit field returns the current value of bits 19:4 of the fetch interval counter on a read. Bits 19:4 of the fetch interval counter are set to this value on a write.
•IbsFetchMaxCnt[15:0] (IBS Fetch Maximum Count) —Bits 15:0, read/write. This 16-bit field 
specifies the maximum count value of bits 19:4 of the fetch interval counter. When the value in bits 19:4 of the fetch counter equals the value in this field, the next fetch block is tagged for profiling.Value Page Size
00b 4 Kbyte
01b 2 Mbyte10b 1 Gbyte
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IBS Fetch Linear Address Register
Figure 13-20. IBS Fetch Linear Address Register (IbsFetchLinAd)
This is a read-only register. Reading the IbsFetchLinAd MSR returns the 64-bit linear address of the 
tagged fetch. This address may correspond to the first byte of an AMD64 instruction or the start of the fetch block. The address is valid only if the IbsFetchCtl[IbsFetchVal]=1. The address is in canonical form.
IBS Fetch Physical Address Register
Figure 13 -21. IBS Fetch Physical Address Register (IbsFetchPhysAd)
This is a read-only register. Reading the IbsFetchPhysAd MSR returns the 52-bit physical address of 
the tagged fetch. This address may correspond to the first byte of an AMD64 instruction or the start of the fetch block. The address is valid only if both the IbsPhyAddrValid and the IbsFetchVal bits of the IbsFetchCtl register are set. Otherwise, the contents of this register are undefined. The indicated size of 52 bits is an architectural limit. Specific processors may implement fewer bits.63 32
IbsFetchLinAd[63:32]
31 0
IbsFetchLinAd[31:0]
63:0 IbsFetchLinAd IBS Fetch Linear Address RO
63 52 51 32
Reserved IbsFetchPhysAd[51:32]
31 0
IbsFetchPhysAd[31:0]
51:0 IbsFetchPhysAd IBS Fetch Physical Address RO
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13.3.3  IBS Execution Sampling
Instruction execution performance is measured by tagging an op associated with an instruction. The 
tagged op joins other ops in a queue waiting to be dispatched and executed. Instructions that decode to more than one op may return different performance data depending upon which op associated with the instruction is tagged. IBS returns the following performance information for each retired tagged op:
•Branch status for branch ops.
•For a load or store op:
- Whether the load or store missed in the data cache.- Whether the load or store address hit or missed in the TLBs.- The linear and physical address of the data operand associated with the load or store operation.- Source information for cache, DRAM, MMIO, or I/O accesses.
IBS selects and tags an op at a programmable rate. When enabled by the IBS Execution Control 
Register (IbsOpEn = 1 and IbsOpVal = 0), an internal 27-bit op interval counter increments either once for every core clock cycle, if IbsOpCntCtl is cleared, or once for every dispatched op, if IbsOpCntCtl is set.
When the value in bits 26:4 of the op counter equals the value in the IbsOpMaxCnt field of the IBS 
Execution Control Register, an op is tagged in the next cycle. When the op is retired, the execution status of the op is written to the IBS execution registers, and IbsOpVal bit of the IBS Execution Control Register is set. When this is complete, an interrupt is signaled to the local APIC. The local APIC should be programmed to deliver this interrupt to the processor core.
The interrupt service routine must save the performance information stored in IBS execution registers. 
Software can then initiate another sample by resetting the IbsOpVal bit in the IBS Execution Control Register.
Aborted ops do not produce an IBS execution sample. If the tagged op aborts (i.e., does not retire), 
hardware resets bits 26:7 of the op interval counter to zero, and bits 6:0 to a random value. The op counter continues to increment and another op is selected when the value in bits 26:4 of the op interval counter equals the value in the IbsOpMaxCnt field.
Randomization of sampling interval:  A degree of randomization of the sampling interval is 
necessary to ensure fairness in sampling, especially for loop-intensive code. For execution sampling 
this must be done by software. This is accomplished when writing the IbsOpCtl register to clear the IbsOpVal bit and initiate a new sampling interval. At that time software can provide a small random 
number (4-6 bits) in the IbsOpCurCnt field to offset the starting count, thereby randomizing the point at which the count reaches the IbsOpMaxCnt value and triggers a sample.
13.3.4  IBS Execution Sampling Registers
The IBS execution sampling registers consist of the control register (IBS Execution Control Register), the linear address register (IBS Op Linear Address Register), and three execution data registers (IBS 
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Op Data 1–3). The IBS execution sampling registers are accessed using the RDMSR and WRMSR 
IBS Execution Control Register (IbsOpCtl)
Figure 13-22. IBS Execution Control Register (IbsOpCtl)
The fields shown in Figure 13 -22 are further described below:
•IbsOpCurCnt[26:0] (IBS Op Current Count)—Bits 58:32, read/write. This field returns the 
current value of the op counter, and provides the starting value of the counter when software writes this register to clear the IbsOpVal bit and start another sampling interval.
•IbsOpMaxCnt[26:20] (IBS Op Maximum Count[26:20]) —Bits 26:20, read/write. This field is 
used to specify the most significant 7 bits of the IbsOpMaxCnt.
•IbsOpCntCtl (IBS Op Counter Control)—Bit 19, read/write. This bit controls op tagging. When this bit is zero, IBS counts core clock cycles in order to select an op for tagging. When this bit is one, IBS counts dispatched ops in order to select an op for tagging.
•IbsOpVal (IBS Op Sample Valid) —Bit 18, read/write. This bit is set when a tagged op retires and

•IbsOpVal (IBS Op Sample Valid) —Bit 18, read/write. This bit is set when a tagged op retires and 
indicates that new instruction execution data is available. The op counter stops counting. An interrupt is generated as specified by the local APIC. The software interrupt handler captures the performance data before clearing the bit to enable the hardware to take another sample.63 59 58 32
Reserved IbsOpCurCnt[26:0]
31 27 26 20 19 18 17 16 15 0
Reserved IbsOpMaxCnt[26:20]
IbsOpCntCtl
IbsOpVal
IbsOpEn
IbsOpL3MissOnlyIbsOpMaxCnt[19:4]
63:59 Reserved MBZ
58:32 IbsOpCurCnt[26:0] IBS Op Current Count, bits 26:0 R/W
26:20 IbsOpMaxCnt[26:20] IBS Op Maximum Count, bits 26:20 R/W
19 IbsOpCntCtl IBS Op Counter Control R/W
18 IbsOpVal IBS Op Sample Valid R/W
17 IbsOpEn IBS Op Sampling Enable R/W 
16 IbsOpL3MissOnly IBS Op L3 Miss Filtering R/W
15:0 IbsOpMaxCnt[19:4] IBS Op Maximum Count, bits 19:4 R/W
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•IbsOpEn (IBS Op Sample Enable) —Bit 17, read/write. Software sets this bit to enable IBS 
execution sampling. Clearing this bit disables IBS execution sampling.
•IbsOpL3MissOnly (IBS Op L3 Miss Filtering) —Bit 16, read/write. This bit controls L3 Miss 
Filtering. When set, Execution IBS only sends interrupts for samples with an L3 miss. See 
Section 13.3.5, “IBS Filtering,” on page 435 for a description of Execution IBS Filtering.
•IbsOpMaxCnt[19:4] (IBS Op Maximum Count[19:4])—read/write. This field specifies the maximum count value for bits 19:4 of the op interval counter. When the value in bits 26:4 of the op interval counter equal the value specified by the concatenation of the IbsOpMaxCnt[26:20] field with this field, the next op is tagged for profiling.
IBS Op Linear Address Register (IbsOpRip)
Figure 13-23. IBS Op Linear Address Register (IbsOpRip)
IbsOpRip[63:0] (IBS Op Linear Address)—Bits 63:0, read/write. Specifies the linear address for the instruction from which the tagged op was issued. The address is valid only if the IbsOpCtl[IbsOpVal] bit is set and the IbsOpData1[IbsRipInvalid] bit is cleared. The address is in canonical form.63 32
IbsOpRip[63:31]
31 0
IbsOpRip[31:0]
63:0 IbsOpRip IBS Op Linear Address R/W
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IBS Op Data 1 Register (IbsOpData1)
The IBS Op Data 1 Register provides core cycle counts for tagged ops and performance data for 
tagged ops which perform a branch.
Figure 13 -24. IBS Op Data 1 Register (IbsOpData1)
The fields shown in Figure 13 -24 are further described below:
•IbsRipInvalid (IbsOpRip Register Invalid) —Bit 38, read/write. If this bit is set, the contents of the 
IbsOpRip register are not valid.
•IbsOpBrnRet (IBS Op Branch Retired) —Bit 37, read/write. This bit is set if the tagged op performs 
a branch that retired.
•IbsOpBrnMisp (IBS Op Branch Mispredicted) —Bit 36, read/write. This bit is set if the tagged op 
performs a retired mispredicted branch.
•IbsOpBrnTaken (IBS Op Branch Taken) —Bit 35, read/write. This bit is set if the tagged op 
performs a retired taken branch.
•IbsOpReturn (IBS Op RET) —Bit 34, read/write. This bit is set if the tagged op performs a retired 
subroutine return (RET).63 39 38 37 36 35 34 33 32
Reserved
IbsRipInvalid
IbsOpBrnRet
IbsOpBrnMisp
IbsOpBrnTaken
IbsOpReturn
Reserved
31 0
Reserved
63:39 Reserved MBZ
38 IbsRipInvalid IbsOpRip Register Invalid R/W
37 IbsOpBrnRet IBS Op Branch Retired R/W
36 IbsOpBrnMisp IBS Op Branch Mispredicted R/W
35 IbsOpBrnTaken IBS Op Branch Taken R/W
34 IbsOpReturn IBS Op RET R/W
33:0 Reserved MBZ
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IBS Op Data 2 Register (IbsOpData2)
The IBS Op Data 2 Register captures Northbridge-related performance data. The information captured 
is implementation-dependent. See the BIOS and Kernel Developer’s Guide (BKDG) or Processor 
Programming Reference Manual (PPR)  applicable to your product for details.
IBS Op Data 3 Register (IbsOpData3)Data Cache (first-level cache) performance data is captured in IBS Op Data 3 Register. If a load or 
store operation crosses a 128-bit boundary, the data returned in this register is the data for the access to the data below the 128-bit boundary.
63 48 47 32
Reserved IbsDcMissLat[15:0]
31 19 18 17 16 15 14 13 12 9 8 7 6 5 4 3 2 1 0
Reserved
IbsDcPhyAddrValid
IbsDcLinAddrValid
Reserved
IbsDcLockedOp
IbsDcUcMemAcc
IbsDcWcMemAccReserved
IbsDcMisAcc
IbsDcMiss
Reserved
IbsDcL1tlbHit1G
IbsDcL1tlbHit2M
Reserved
IbsDcL1tlbMiss
IbsStOp
IbsLdOp
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Figure 13 -25. IBS Op Data 3 Register (IbsOpData3)
The fields shown in Figure 13 -25 are further described below:
•IbsDcMissLat[15:0] (IBS Data Cache Miss Latency) —Bits 47:32, read/write. This field indicates 
the number of core clock cycles from when a miss is detected in the data cache to when the data is 
delivered to the core. The value is not valid for data cache store operations.
•IbsDcPhyAddrValid (IBS Data Cache Physical Address Valid) —Bit 18, read/write. This bit is set if 
the physical address in the IBS DC Physical Address Register is valid for a load or store operation.
•IbsDcLinAddrValid (IBS Data Cache Linear Address Valid)—Bit 17, read/write. This bit is set if the linear address in the IBS DC Linear Address Register is valid for a load or store operation.
•IbsDcLockedOp (IBS Data Cache Locked Op) —Bit 15, read/write. This bit is set if the tagged load 
or store operation was a locked operation.
•IbsDcUcMemAcc (IBS Data Cache UC Memory Access) —Bit 14, read/write. This bit is set if the 
tagged load or store operation accessed uncacheable memory.
•IbsDcWcMemAcc (IBS Data Cache WC Memory Access)—Bit 13, read/write. This bit is set if the tagged load or store operation accessed write combining memory.
•IbsDcMisAcc (IBS Data Cache Misaligned Access Penalty) —Bit 8, read/write. This bit is set if a 
tagged load or store operation incurred a performance penalty due to a misaligned access.Bits Mnemonic Description Access type
63:48 Reserved MBZ
47:32 IbsDcMissLat[15:0] IBS Data Cache Miss Latency R/W
31:19 Reserved MBZ
18 IbsDcPhyAddrValid IBS Data Cache Physical Address Valid R/W
17 IbsDcLinAddrValid IBS Data Cache Linear Address Valid R/W
15 IbsDcLockedOp IBS Data Cache Locked Op R/W
14 IbsDcUcMemAcc IBS Data Cache UC Memory Access R/W
13 IbsDcWcMemAcc IBS Data Cache WC Memory Access R/W
12:9 Reserved MBZ
8 IbsDcMisAcc IBS Data Cache Misaligned Access Penalty R/W
7 IbsDcMiss IBS Data Cache Miss R/W
6 Reserved MBZ
5 IbsDcL1tlbHit1G IBS Data Cache L1 TLB Hit 1-Gbyte Page R/W 
4 IbsDcL1tlbHit2M IBS Data Cache L1 TLB Hit 2-Mbyte Page R/W 
3 Reserved MBZ
2 IbsDcL1tlbMiss IBS Data Cache L1 TLB Miss R/W 
1 IbsStOp IBS Store Operation R/W 
0 IbsLdOp IBS Load Operation R/W
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•IbsDcMiss (IBS Data Cache Miss)—Bit 7, read/write. This bit is set if the cache line used by the 
tagged load or store operation was not present in the data cache.
•IbsDcL1tlbHit1G (IBS Data Cache L1 TLB Hit 1-Gbyte Page) —Bit 5, read/write. This bit is set if 
the physical address for the tagged load or store operation was present in a 1-Gbyte page table entry in the data cache L1 TLB.
•IbsDcL1tlbHit2M (IBS Data Cache L1 TLB Hit 2-Mbyte Page) —Bit 4, read/write. This bit is set if 
the physical address for the tagged load or store operation was present in a 2-Mbyte page table entry in the data cache L1 TLB.
•IbsDcL1tlbMiss (IBS Data Cache L1 TLB Miss) —Bit 2, read/write. This bit is set if the physical 
address for the tagged load or store operation was not present in the data cache L1 TLB.
•IbsStOp (IBS Store Op)—Bit 1, read/write. This bit is set if the tagged op was a store.
•IbsLdOp (IBS Load Op)—Bit 0, read/write. This bit is set if the tagged op was a load.
IBS Data Cache Linear Address Register (IbsDcLinAd)
Figure 13-26. IBS Data Cache Linear Address Register (IbsDcLinAd)
IbsDcLinAd[63:0] (IBS Data Cache Linear Address) —Bits 63:0, read/write. Specifies the linear 
address of the tagged op's memory operand. The address is valid only if IbsOpData3[IbsDcLinAdVal] is set. The address is in canonical form. 63 32
IbsDcLinAd[63:32]
31 0
IbsDcLinAd[31:0]
Bit Mnemonic Description Access type
63:0 IbsDcLinAd IBS Data Cache Linear Address R/W
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IBS Data Cache Physical Address Register (IbsDcPhysAd)
Figure 13 -27. IBS Data Cache Physical Address Register (IbsDcPhysAd)
IbsDcPhysAd (IBS Data Cache Physical Address) —Bits 51:0, read/write. Specifies the physical 
address of the tagged op’s memory operand. The address is valid only if IbsOpData3[IbsDcPhyAdVal] 
is set.

31 0
is set.   
IBS Branch Target Address Register (IbsBrTarget)
Figure 13-28. IBS Branch Target Address Register (IbsBrTarget)
IbsBrTarget (IBS Branch Target) —Bits 63:0, read/write. Specifies the 64-bit linear address for the 
branch target. The address is in canonical form. For non-branch instructions, the value supplied in this 
register is invalid. For a conditional branch not taken, the value supplied in this register is the fall-through address.
13.3.5  IBS Filtering 
Processors that set CPUID Fn8000_001B_EAX[IbsL3MissFiltering](bit 11) = 1 support IBS Filtering for both IBS Fetch Sampling and IBS Execution Sampling. IBS Filtering changes the behavior of the 63 52 51 32
Reserved IbsDcPhysAd[51:32]
31 0
IbsDcPhysAd[31:0]
51:0 IbsDcPhysAd IBS Data Cache Physical Address R/W
63 32
IbsBrTarget[63:32]
31 0
IbsBrTarget[31:0]
63:0 IbsBrTarget IBS branch target linear address R/W
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IBS hardware such that interrupts are only generated for samples that match certain criteria. If the 
sample does not match the selected criteria the IBS hardware restarts and selects a new sample. This results in reduced interrupt overhead if software is only interested in samples with certain characteristics.
Fetch IBS Filtering
When Fetch IBS collects a sample that does not match the selected filter criteria it does not set 
IbsFetchCtl[IbsFetchVal] and instead clears IbsFetchCtl[IbsFetchCnt] and bits 19:8 of the internal fetch counter. Bits 7:0 of the internal fetch counter are loaded with a pseudo-random value if IbsFetchCtl[IbsRandEn] is set and cleared if IbsFetchCtl[IbsRandEn] is not set. It is recommended that software sets IbsFetchCtl[IbsRandEn] when IBS Filtering is active. After its reset, the internal fetch counter increments for every attempted fetch. When the internal fetch counter's bits [9:4] match IbsFetchCtl[IbsFetchMaxCnt] the next fetch is selected for profiling. When the selected fetch completes or is aborted, the IBS hardware evaluates it against the IBS Filtering criteria and either sets IbsFetchCtl[IbsFetchVal] and signals an interrupt or restarts Fetch IBS in the manner described above.
Execution IBS Filtering
When Execution IBS collects a sample that does not match the selected filter criteria it does not set 
IbsOpCtl[IbsOpVal] and instead clears IbsOpCtl[IbsOpCurCnt] and bits 26:0 of the internal op counter. Bits 6:0 of the internal op counter are loaded with a pseudo-random value. After its reset, the internal op counter increments for every cycle (IbsOpCtl[IbsOpCntCtl] = 0) or dispatched op (IbsOpCtl[IbsOpCntCtl] = 1). When the internal op counter's bits [26:4] match IbsOpCtl[IbsOpMaxCnt] the next op is selected for profiling. When profiling is complete, the IBS hardware evaluates it against the IBS Filtering criteria and either sets IbsOpCtl[IbsOpVal] and signals an interrupt or restarts Execution IBS in the manner described above.
Supported IBS Filter Criteria
Figure 13 -7 shows the supported filter criteria and how they are activated.
Table 13-7. Supported IBS Filtering Criteria
Filter criterion Active when Supported If
Fetch IBS only reports 
samples with L3 missIbsFetchCtl[IbsL3MissOnly] = 1CPUID Fn8000_001B_EAX[IbsL3MissFiltering](bit 11) = 1
Execution IBS only reports samples with L3 missIbsOpCtl[IbsOpL3MissOnly] = 1CPUID Fn8000_001B_EAX[IbsL3MissFiltering](bit 11) = 1
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13.4 Lightweight Profiling
Lightweight Profiling (LWP) is an AMD64 extension that allows user mode processes to gather 
performance data about themselves with very low overhead. LWP is supported in both long mode and legacy mode. Modules such as managed runtime environments and dynamic optimizers can use LWP to monitor the running program with high accuracy and high resolution. They can quickly discover performance problems and opportunities and immediately act on this information.
LWP allows a program to gather performance data and examine it either by polling or by taking an 
occasional interrupt. It introduces minimal additional state to the CPU and the process. LWP differs from the existing performance counters and from Instruction Based Sampling (IBS) because it collects large quantities of data before taking an interrupt. This substantially reduces the overhead of using performance feedback. An application can avoid the need to enable and process interrupts by polling the LWP data.
A program can control LWP data collection entirely in user mode. It can start, stop, and reconfigure 
profiling without calling the kernel.
LWP runs within the context of a thread, so it can be used by multiple processes in a system at the same 
time without interference. This also means that if one thread is using LWP and another is not, the latter thread incurs no profiling overhead.
LWP can be programmed to run in one of two modes: synchronized mode  or continuous mode . In 
synchronized mode the recording of events stops when the buffer set up to hold event records becomes 
full. In continuous mode, the storing of events wraps in the buffer overwriting older records.
13.4.1  Overview
When enabled, LWP hardware monitors one or more events during the execution of user-mode code and periodically inserts event records into a ring buffer in the address space of the running process. If performance timestamping is supported and enabled, each event record captured is timestamped using the value read from the performance timestamp counter (PTSC). Timestamping is enabled by setting the Flags.PTSC bit of the Lightweight Profiling Control Block (LWPCB). When the ring buffer is filled beyond a user-specified threshold, the hardware can cause an interrupt which the operating system (OS) uses to signal a process to empty the ring buffer. With proper OS support, the interrupt can even be delivered to a separate process or thread.
LWP only counts instructions that retire in user mode (CPL = 3). Instructions that change to CPL 3 
from some other level are not counted, since the instruction address is not an address in user mode space. LWP does not count hardware events while the processor is in system management mode (SMM) and while entering or leaving SMM.
Once LWP is enabled, each user-mode thread uses the LLWPCB and SLWPCB instructions to control 
LWP operation. These instructions refer to a data structure in application memory called the Lightweight Profiling Control Block, or LWPCB, to specify the profiling parameters and to interact 
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with the LWP hardware. The LWPCB in turn points to a buffer in memory in which LWP stores event 
records.
Each thread in a multi-threaded process must configure LWP separately. A thread has its own ring 
buffer and counters which are context switched with the rest of the thread state. However, a single monitor thread could collect and process LWP data from multiple other threads.
LWP may be set up to run in one of two modes: 
•Synchronized Mode
LWP runs in synchronized mode when it is started with LWPCB.Flags.CONT = 0. In this mode, 
LWP will not advance the ring buffer pointer when the event ring buffer is full. It simply increments LWPCB.MissedEvents to count the number of missed event records. In synchronized mode, a thread can remove event records from the ring buffer by advancing the ring buffer tail pointer without stopping LWP in the executing thread. If the buffer had been full, event records will again be written and the ring buffer pointer will be advanced.
•Continuous Mode
LWP runs in continuous mode when it is started with LWPCB.Flags.CONT = 1. In this mode, 
LWP will store an event record even when the event ring buffer is full, wrapping around in the ring buffer and overwriting the oldest event record. In continuous mode, LWPCB.MissedEvents counts the number of times that such wrapping has occurred. The only reliable way to read events from the ring buffer when LWP is in continuous mode is to stop LWP in the running thread before accessing the LWPCB and the ring buffer contents. Support for continuous mode is indicated by CPUID Fn8000_001C_EAX[LwpCont].
During profiling, the LWP hardware monitors and reports on one or more types of events. Following are the steps in this process:
1.Count—Each time an instruction is retired, LWP decrements its internal event counters for all of 
the events associated with the instruction. An instruction can cause zero, one, or multiple events. For instance, an indirect jump through a pointer in memory counts as an instruction retired, a branch retired, and may also cause up to two DCache misses (or more, if there is a TLB miss) and up to two ICache misses.
- Some events may have filters or conditions on them that regulate counting. For instance, the

- Some events may have filters or conditions on them that regulate counting. For instance, the 
application may configure LWP so that only cache miss events with latency greater than a 
specified minimum are eligible to be counted.
2.Gather— When an event counter becomes negative, the event should be reported. LWP gathers 
an event record and, if enabled, samples the value in the PTSC to be included in the record as the TimeStamp value. The event’s counter may continue to count below zero until the record is written to the event ring buffer.
For most events, such as instructions retired, LWP gathers an event record describing the 
instruction that caused the counter to become negative. However, it is valid for LWP to gather event record data for the next instruction that causes the event, or to take other measures to capture 
a record. Some of these options are described with the individual events.
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- An implementation can choose to gather event information on one or many events at any one 
time. If multiple event counters become negative, an advanced LWP implementation might 
gather one event record per event and write them sequentially. A basic LWP implementation may choose one of the eligible events. Other events continue counting but wait until the first event record is written. LWP picks the next eligible instructions for the waiting events. This situation should be extremely uncommon if software chooses large event interval values.
- LWP may discard an event occurrence. For instance, if the LWPCB or the event ring buffer 
needs to be paged in from disk, LWP might choose not to preserve the pending event data. If an event is discarded, LWP gathers an event record for the next instruction to cause the event.
- Similarly, if LWP needs to replay an instruction to gather a complete event record, the replay 
may abort instead of retiring. The event counter continues counting below zero and LWP gathers an event record for the next instruction to cause the event.
3.Store—When a complete event record is gathered, LWP stores it into the event ring buffer in the process’ address space and advances the ring buffer head pointer.
- LWP checks to see if the ring buffer is full, i.e., if advancing the ring buffer head pointer would 
make it equal to the tail pointer. If the buffer is full, LWP increments the 64-bit counter 
LWPCB.MissedEvents. If LWP is running in synchronized mode, it does not advance the head pointer. If LWP is running in continuous mode, it always advances the head pointer and LWPCB.MissedEvents counts the number of times that the buffer wrapped.
- If more than one event record reaches the Store stage simultaneously, only one need be stored. 
Though LWP might store all such event records, it may delay storing some event records or it may discard the information and proceed to choose the next eligible instruction for the discarded event type(s). This behavior is implementation dependent.
- The store need not complete synchronously with the instruction retiring. In other words, if 
LWP buffers the event record contents, the Store stage (and subsequent stages) may complete some number of cycles after the tagged instruction retires. The data about the event and the instruction are precise, but the Report and Reset steps (below) may complete later.
4.Report— If LWP threshold interrupts are enabled and the space used in the event ring buffer 
exceeds a user-defined threshold, LWP initiates an interrupt. The OS can use this to signal the process to empty the ring buffer. Note that the interrupt may occur significantly later than the event that caused the threshold to be reached.
5.Reset—For each event that was stored, the counter is reset to its programmed interval. If requested by the application, LWP applies randomization to the low order bits of the interval. Counting for that event continues. Reset happens if the ring buffer head pointer was advanced or if the missed event counter was incremented. If the event counter went below -1, indicating that additional events occurred between the selected event and the time it was reported, that overrun value reduces the reset value so as to preserve the statistical distribution of events.
For all events except the LWPV AL instruction, the hardware may impose a minimum on the reset 
value of an event counter. This prevents the system from spending too much time storing samples rather than making forward progress on the application. Any minimum imposed by the hardware can be detected by examining the EventInterval n fields in the LWPCB after enabling LWP.
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An application should periodically remove event records from the ring buffer and advance the tail 
pointer. (If the application does not process the event records quickly enough or often enough, the LWP hardware will detect that the ring buffer is full and will miss events.) There are two ways to process the gathered events: interrupts or polling.
The application can wait until a threshold interrupt occurs to process the event records in the ring 
buffer. This requires OS or driver support. (As a consequence, interrupts can only be enabled if a kernel mode routine allows it; see “LWP_CFG—LWP Configuration MSR” on page 454) One usage 
model is to associate the LWP interrupt with a semaphore or mutex. When the interrupt occurs, the OS or driver signals the associated object. A thread waiting on the object wakes up and empties the ring buffer. Other models are possible, of course.
Alternatively, the application can have a thread that periodically polls the ring buffer. The polling 
thread need not be part of the process that is using LWP. It can be in a separate process that shares the memory containing the LWP control block and ring buffer.
Access to the ring buffer uses a lockless protocol between the LWP hardware and the application. The 
hardware owns the head pointer and the area in the ring buffer from the head pointer up to (but not including) the tail pointer. The application must not modify the head pointer nor rely on any data in the area of the ring buffer owned by the hardware. If the application has a stale value for the head pointer, it may miss an existing event record but it will never read invalid data. When the application is done emptying the ring buffer, it should refresh its copy of the head pointer to see if the LWP hardware has added any new event records.
Similarly, the application owns the tail pointer and the area in the ring buffer from the tail pointer up to 
(but not including) the head pointer. The hardware will never modify the tail pointer or overwrite the data in that region of the ring buffer. If the hardware has a stale value for the tail pointer, it may consider that the ring buffer is full or at its threshold, but it will never overwrite valid data. Instead, it refreshes its copy of the tail pointer and rechecks to see if the full or threshold condition still applies.
When LWP is in continuous mode, this lockless protocol does not work, since the LWP hardware may 
overwrite the event records in the ring buffer when it advances the head pointer past the tail pointer. Because of this, the application must stop LWP before removing event records from the ring buffer. This prevents the hardware from wrapping through the ring buffer asynchronously from the application’s attempt to remove data from it. 
To use continuous mode properly, the application should set LWPCB.MissedEvents to 0 and set the 
head and tail pointers to the start of the ring buffer before starting LWP. To empty the ring buffer, the application should stop LWP. If LWPCB.MissedEvents is 0, the buffer did not wrap and there are event records starting at the tail pointer and continuing up to (but not including) the head pointer. If MissedEvents is not 0, the buffer wrapped and there are event records starting with the oldest one pointed to by the head pointer and continuing (possibly wrapping) all the way around to the newest one just before the head pointer.
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13.4.2  Events and Event Records
When a monitored event overflows its event counter, LWP puts an event record into the LWP event 
ring buffer. If event timestamping is supported and enabled, each event record will include a TimeStamp value. This value is a copy of the contents of Performance Timestamp Counter (PTSC) zero-extended if necessary to 64 bits.
The PTSC is a free-running counter that increments at a constant rate of 100MHz and is synchronized 
across all cores on a node to within +/-1. This counter starts when the processor is initialized and cannot be reset or modified. It is at least 40 bits wide. Privileged code can read the PTSC value via the RDMSR instruction. The size of the counter is indicated by the 2-bit field CPUID Fn8000_0008_ECX[PerfTscSize]. A value of 00b means that the PTSC is 40 bits wide; 01b means 48 bits, 10b means 56 bits, and 11b indicates a full 64 bits.
The PTSC can be correlated to the architectural TSC that runs at the P0 frequency. An application can

The PTSC can be correlated to the architectural TSC that runs at the P0 frequency. An application can 
read the TSC and PTSC, wait a 1000 clock periods or so, then read them again. The ratio of the differences is the scaling factor for the counters.
The event record size is fixed but may vary based on implementation. The event record size for a given 
processor is discovered by executing CPUID Fn8000_001C and extracting the value of the LwpEventSize field. (See “Detecting LWP Capabilities” on page 451). Current implementations fix the record size at 32 bytes and this size is used in the record format specifications below.
Reserved fields and fields that are not defined for a particular event are set to zero when LWP writes an 
event record.
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Figure 13-29. Generic Event Record
Table 13 -8 below lists the event identifiers for the events defined in version 1 of LWP. They are 
described in detail in the following sections.Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
(Event-specific data) Flags CoreId EventId 0
InstructionAddress 8
(Event-specific address or data) 16
TimeStamp 24
Bytes Field Description
0 EventIdEvent identifier specifying the event record type. Valid identifiers are 1 to 
255. 0 is an invalid identifier.
1 CoreIdCPU core identifier value from COREID field of LWP_CFG (see “LWP_CFG—LWP Configuration MSR” on page 454). For multicore 
systems, this typically identifies the core on which LWP is running. This allows software to aggregate event records from multiple threads into a single data structure without losing CPU information. It also allows software to detect when a thread has migrated from one core to another.
3–2 Flags Event-specific flags.
7–4 Event-specific data.
15–8 InstructionAddressThe Effective Address of the instruction that triggered this event record. This is the value before adding in the CS base address. If the base is non-zero, software must track it. (Modern operating systems use a CS base of zero, and CS is unused in long mode.)
23–16 Event-specific address or other data.
31–24 TimeStampPerformance Time Stamp Counter value if LWP was started with LWPCB.Flags.PTSC = 1, zero otherwise.
Table 13-8. EventId Values
EventId Description
0 Reserved – invalid event
1 Programmed value sample2 Instructions retired3 Branches retired4 DCache misses
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13.4.2.1  Programmed Value Sample
LWP decrements the event counter each time the program executes the LWPV AL instruction (see 
“LWPV AL—Insert Value Sample in LWP Ring Buffer” on page 458). When the counter becomes negative, it stores an event record with an EventId of 1. The data in the event record come from the operands to the instruction as detailed in the instruction description.
Figure 13-30. Programmed Value Sample Event Record
13.4.2.2  Instructions Retired
LWP decrements the event counter each time an instruction retires. When the counter becomes 
negative, it stores a generic event record with an EventId of 2.
Instructions are counted if they execute entirely in user mode (CPL = 3). Instructions that change to 
CPL 3 from some other level are not counted, since the instruction address is not an address in user mode space. All user mode instructions are counted, including LWPV AL and LWPINS.5 CPU clocks not halted
6 CPU reference clocks not halted
255 Programmed event
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Data1 Flags CoreId EventId=1 0
Data2 16
0 EventId Event identifier = 1
1 CoreId CPU core identifier from LWP_CFG
3–2 Flags Immediate value (bottom 16 bits)
7–4 Data1 Reg/mem value
15–8 InstructionAddress Instruction address of LWPV AL instruction
23–16 Data2 Reg value (zero extended if running in legacy mode)
31–24 TimeStampPerformance Time Stamp Counter value if LWP was started with 
LWPCB.Flags.PTSC = 1, zero otherwise.Table 13-8. EventId Values (continued)
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Figure 13-31. Instructions Retired Event Record
13.4.2.3  Branches Retired
LWP decrements the event counter each time a transfer of control retires, regardless of whether or not 
it is taken. When the counter becomes negative, it stores an event record with an EventId of 3.
Control transfer instructions that are counted are:
•JMP (near), Jcc, JCXZ, JEXCZ, and JRCXZ
•LOOP, LOOPE, and LOOPNE
•CALL (near) and RET (near)
LWP does not count JMP (far), CALL (far), RET (far), traps, or interrupts (whether synchronous or 
asynchronous), nor does it count operations that switch to or from ring 3, SMM, or SVM, such as SYSCALL, SYSENTER, SYSEXIT, SYSRET, VMMCALL, INT, or INTO.
Some implementations of the AMD64 architecture perform an optimization called “fusing” when a 
compare operation (or other operation that sets the condition codes) is followed immediately by a conditional branch. The processor fuses these into a single operation internally before they are executed. While this is invisible to the programmer, the address of the actual branch is not available for LWP to report when the (fused) instruction retires. In this case, LWP sets the FUS bit in the event record and reports the address of the operation that set the condition codes. If FUS is set, software can find the address of the actual branch by decoding the instruction at the reported InstructionAddress and Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Reserved Reserved CoreId EventId=2 0
Reserved 16
Bytes Bits Field Description
0 7:0 EventId Event identifier = 2
1 7:0 CoreId CPU identifier from LWP_CFG
7–2 Reserved
15–8 InstructionAddress Instruction address
23–16 Reserved
LWPCB.Flags.PTSC = 1, zero otherwise.
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adding its length to that address. (Note that fused instructions do count as 2 instructions for the 
Instructions Retired event, since there were 2 x86 instructions originally.)
Figure 13 -32. Branch Retired Event RecordByte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Reserved
TKN
PRD
PRV
FUSReserved CoreId EventId=3 0
TargetAddress 16
0 7:0 EventId Event identifier = 3
1 7:0 CoreId CPU core identifier from LWP_CFG
3–2 11:0 Reserved
3 4 FUS1—Fused operation. InstructionAddress points to a compare 
operation (or other operation that sets the condition codes) 
immediately preceding the branch.
0—InstructionAddress points to the branch instruction.
3 5 PRV1—PRD bit is valid
0—Prediction information is not availableSome implementations of LWP may be unable to capture branch 
prediction information on some or all branches.
3 6 PRD1—Branch was predicted correctly
0—MispredictedIf PRV = 0, the value of PRD is unpredictable and should be 
ignored.
For unconditional branches, PRD=1 if PRV=1.
3 7 TKN1—Branch was taken0—Branch not takenAlways 1 for unconditional branches.
7–4 Reserved
23–16 TargetAddressAddress of instruction executed after branch. This is the target if 
the branch was taken and the fall-through address if the branch was a not-taken conditional branch. TargetAddress is the Effective Address value before adding in the CS base address.
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13.4.2.4  DCache Misses
LWP decrements the event counter each time a load from memory causes a DCache miss whose 
latency exceeds the LwpCacheLatency threshold and/or whose data come from a level of the cache or memory hierarchy that is selected for counting. When the counter becomes negative, LWP stores an event record with an EventId of 4. 
A misaligned access that causes two misses on a single load decrements the event counter by 1 and, if 
it reports an event, the data are for the lowest address that missed. LWP only counts loads directly caused by the instruction. It does not count cache misses that are indirectly due to TLB walks, LDT or GDT references, TLB misses, etc. Cache misses caused by LWP itself accessing the LWPCB or the event ring buffer are not counted.
Measuring Latency
The x86 architecture allows multiple loads to be outstanding simultaneously. An implementation of 
LWP might not have a full latency counter for every load that is waiting for a cache miss to be resolved. Therefore, an implementation may apply any of the following simplifications. Software using LWP should be prepared for this.
•The implementation may round the latency to a multiple of 2^ j. This is a small power of 2, and the

•The implementation may round the latency to a multiple of 2^ j. This is a small power of 2, and the 
value of j must be 1 to 4. For example, in the rest of this section, assume that j= 4, so 2^ j= 16. The 
low 4 bits of latency reported in the event record will be 0. The actual latency counter is 
incremented by 16 every 16 cycles of waiting. The value of j is returned as LwpLatencyRnd (see 
“Detecting LWP Capabilities” on page 451).
•The implementation may do an approximation when starting to count latency. If counting is in increments of 16, the 16 cycles need not start when the load begins to wait. The implementation may bump the latency value from 0 to 16 any time during the first 16 cycles of waiting.
•The implementation may cap total latency to 2^ n-16 (where n>= 10). The latency counter is thus a 
saturating counter that stops counting when it reaches its maximum value. For example, if n= 10, 
the latency value will count from 0 to 1008 in steps of 16 and then stop at 1008. (If n= 10, each 
counter is only 6 bits wide.) The value of n is returned as LwpLatencyMax (see “Detecting LWP 
Capabilities” on page 451).
Note that the latency threshold used to filter events is a multiple of 16. This value is used in the comparison that decides whether a cache miss event is eligible to be counted.
Reporting the DCache Miss Data Address
The event record for a DCache miss reports the linear address of the data (after adding in the segment 
base address, if any). The way an implementation records the linear address affects the exact event that is reported and the amount of time it takes to report a cache miss event. The implementation may report the event immediately, report the next eligible event once the counter becomes negative, or replay the instruction.
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Figure 13-33. DCache Miss Event Record
13.4.2.5  CPU Clocks not Halted
LWP decrements the event counter each clock cycle that the CPU is not in a halted state (due to 
STPCLK or a HLT instruction). When the counter becomes negative, it stores a generic event record with an EventId of 5. This counter varies in real-time frequency as the core clock frequency changes.Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Latency SRC
DA VReserved CoreId EventId=4 0
DataAddress 16
0 7:0 EventId Event identifier = 4
2–3 11:0 Reserved
3 4 DA V1—DataAddress is valid
0—Address is unavailable
3 5:7 SRCData source for the requested data
7–4 Latency Total latency of cache miss (in cycles)
23–16 DataAddress Address of memory reference (if flag bit 28 = 1)
LWPCB.Flags.PTSC = 1, zero otherwise.0 No valid status
1 Local L3 cache2 Remote CPU or L3 cache3 DRAM4 Reserved (for Remote cache)5 Reserved6 Reserved7 Other (MMIO/Config/PCI/APIC)
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Figure 13-34. CPU Clocks not Halted Event Record
13.4.2.6  CPU Reference Clocks not Halted
LWP decrements the event counter each reference clock cycle that the CPU is not in a halted state (due 
to STPCLK or a HLT instruction). When the counter becomes negative, it stores a generic event record with an EventId of 6.
The reference clock runs at a constant frequency that is independent of the core frequency and of the 
performance state. The reference clock frequency is processor dependent. The processor may implement this event by subtracting the ratio of (reference clock frequency / core clock frequency) each core clock cycle.Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Reserved Reserved CoreId EventId=5 0
0 7:0 EventId Event identifier = 5
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Figure 13-35. CPU Reference Clocks not Halted Event Record
13.4.2.7  Programmed Event
When a program executes the LWPINS instruction (see “LWPINS—Insert User Event Record in LWP 
Ring Buffer” on page 459), the processor stores an event record with an event identifier of 255. The data in the event record come from the operands to the instruction as detailed in the instruction description.Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Reserved Reserved CoreId EventId=6 0
0 7:0 EventId Event identifier = 6
2–7 Reserved
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Figure 13-36. Programmed Event Record
13.4.2.8  Other Events
The overall design of LWP allows easy extension to the list of events that it can monitor. The following 
are possibilities for events that may be added in future versions of LWP:
•DTLB misses
•FPU operations
•ICache misses
•ITLB misses
13.4.3  Detecting LWP
An application uses the CPUID instruction to identify whether Lightweight Profiling is present and 
which of its capabilities are available for use. An operating system uses CPUID to determine whether LWP is supported on the hardware and to determine which features of LWP are supported and can be made available to applications.Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Data1 Flags CoreIdEventID =
2550
Data2 16
0 EventId Event identifier = 255
1 CoreId CPU identifier from LWP_CFG
3–2 Flags Imm16 value
15–8 InstructionAddress Instruction address of LWPINS instruction
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13.4.3.1  Detecting LWP Presence
LWP is supported on a processor if CPUID Fn8000_0001_ECX[LWP] (bit 15) is set. This bit is 
identical to the value of CPUID Fn0000_000D_EDX_x0[bit 30], which is bit 62 of the XFeatureSupportedMask and indicates XSA VE support for LWP. A system can check either of those bits to determine if LWP is supported. Since LWP requires XSA VE, software can assume that this bit being set implies that CPUID Fn0000_0001_ECX[XSA VE] (bit 26) is also set.
13.4.3.2  Detecting LWP XSAVE Area
The size of the LWP extended state save area used by XSA VE/XRSTOR is 128 bytes (080h). This 
value is returned by CPUID Fn0000_000D_ EAX_x3E (ECX=62).
The offset of the LWP save area from the beginning of the XSA VE/XRSTOR area is 832 bytes (340h). This value is returned by CPUID Fn0000_000D_ EBX_x3E (ECX=62).
The size of the LWP save area is included in the XFeatureSupportedSizeMax value returned by CPUID Fn0000_000D_ECX_x0 (ECX=0). 
If LWP is enabled in the XFEATURE_ENABLED_MASK, the size of the LWP save area is included 
in the XFeatureEnabledSizeMax value returned by CPUID Fn0000_000D_EBX_x0 (ECX=0).
13.4.3.3  Detecting LWP Capabilities
The values returned by CPUID Fn8000_001C indicate the capabilities of LWP. See Table 13 -9, 
“Lightweight Profiling CPUID Values” for a listing of the returned values.
Bit 0 of EAX is a copy of bit 62 from XFEATURE_ENABLED_MASK and indicates whether LWP is 
available for use by applications. If it is 1, the processor supports LWP and the operating system has enabled LWP for applications.
Bits 31:1 returned in EAX are taken from the LWP_CFG MSR and reflect the LWP features that are 
available for use. These are a subset of the bits returned in EDX, which reflect the full capabilities of LWP on current processor. The operating system can make a subset of LWP available if it cannot handle all supported features. For instance, if the OS cannot handle an LWP threshold interrupt, it can disable the feature. User-mode software must assume that the bits in EAX describe the features it can use. Operating systems should use the bits from EDX to determine the supported capabilities of LWP and make all or some of those features available.
Under SVM, if a VMM allows the migration of guests among processors that all support LWP, it must 
arrange for CPUID to report the logical AND of the supported feature bits over all processors in the migration pool. Other CPUID values must also be reported as the “least common denominator” among the processors.
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Table 13 -9. Lightweight Profiling CPUID Values
Reg Bits Field Description

EAX0 LwpAvail1—LWP is available to application programs. The hardware and the 
operating system support LWP.
0—LWP is not available.
This bit is a copy of bit 62 of the XFEATURE_ENABLED_MASK 
register (XCR0).
1 LwpV AL LWPV AL instruction (EventId = 1) is available.
2 LwpIRE Instructions retired event (EventId = 2) is available.
3 LwpBRE Branch retired event (EventId = 3) is available.
4 LwpDME DCache miss event (EventId = 4) is available.
5 LwpCNH CPU clocks not halted event (EventId = 5) is available.
6 LwpRNH CPU reference clocks not halted event (EventId = 6) is available.
28:7 Reserved
29 LwpCont Sampling in continuous mode is available.
30 LwpPTSC Performance Time Stamp Counter in event records is available. 
31 LwpInt Interrupt on threshold overflow is available.
EBX7:0 LwpCbSizeSize in quadwords of the LWPCB. This value is at least (LwpEventOffset / 8) + LwpMaxEvents but an implementation may require a larger control block.
15:8 LwpEventSizeSize in bytes of an event record in the LWP event ring buffer. (32 for LWP Version 1.)
23:16 LwpMaxEventsMaximum supported EventId value (not including EventId 255 used by the LWPINS instruction). Not all events between 1 and LwpMaxEvents are necessarily supported.
31:24 LwpEventOffsetOffset from the start of the LWPCB to the EventInterval1 field. Software uses this value to locate the area of the LWPCB that describes events to be sampled. This permits expansion of the initial fixed region of the LWPCB. LwpEventOffset is always a multiple of 8.
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ECX4:0 LwpLatencyMaxNumber of bits in cache latency counters (10 to 31).
0 if DCache miss event is not supported (EDX[LwpDME] = 0).
5 LwpDataAddress1—Cache miss event records report the data address of the reference.0—Data address is not reported.0 if DCache miss event is not supported (EDX[LwpDME] = 0).
8:6 LwpLatencyRndThe amount by which cache latency is rounded. The bottom 
LwpLatencyRnd bits of latency information will be zero. The actual number of bits implemented for the counter is (LwpLatencyMax – LwpLatencyRnd).
Must be 0 to 4.0 if DCache miss event is not supported (EDX[LwpDME] = 0).
15:9 LwpVersion Version of LWP implementation. (1 for LWP Version 1.)
23:16 LwpMinBufferSizeMinimum size of the LWP event ring buffer, in units of 32 event records. 
At least 32*LwpMinBufferSize records must be allocated for the LWP event ring buffer, and hence the size of the ring buffer must be at least 32 
* LwpMinBufferSize * LwpEventSize bytes. If 0, there is no minimum.
27:24 Reserved
28 LwpBranchPrediction1—Branches Retired events can be filtered based on whether the branch 
was predicted properly. The values of NMB and NPB in the LWPCB enable filtering based on prediction.
0—NMB and NPB fields of the LWPCB are ignored.
0 if Branches Retired event is not supported (EDX[LwpBRE] = 0).
29 LwpIpFiltering1—IP filtering is supported.0—IP filtering is not supported. The IPI, IPF, BaseIP, and LimitIP fields 
of the LWPCB are ignored.
30 LwpCacheLevels1—Cache-related events can be filtered by the cache level that returned 
the data. The value of CLF in the LWPCB enables cache level 
filtering.
0—CLF is ignored.
An implementation must support filtering either by latency or by cache 
level. It may support both.
31 LwpCacheLatency1—Cache-related events can be filtered by latency. The value of 
MinLatency in the LWPCB controls filtering.
0—MinLatency is ignored.An implementation must support filtering either by latency or by cache 
EDX 0 LwpAvailLWP is supported. If 0, the remainder of the data returned by CPUID 
should be ignored.
This bit is a copy of CPUID Fn8000_0001_ECX[LWP] (bit 15).
1 LwpV AL LWPV AL instruction (EventId = 1) is supported.Table 13 -9. Lightweight Profiling CPUID Values
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For more information on using the CPUID instruction, refer to Section 3.3, “Processor Feature 
13.4.4  LWP Registers
The XFEATURE_ENABLED_MASK register (extended control register XCR0) and the LWP model-specific registers describe and control the LWP hardware. The MSRs are available if CPUID Fn8000_0001_ECX[LWP] (bit 15) is set. LWP can only be used if the system has made support for 
LWP state management available in XFEATURE_ENABLED_MASK.
13.4.4.1  XFEATURE_ENABLED_MASK Support
LWP requires that the processor support the XSA VE/XRSTOR instructions to manage LWP state, 
along with the XSETBV/XGETBV instructions that manage the enabled state mask. An operating system uses XSETBV to set bit 62 of XFEATURE_ENABLED_MASK to indicate that it supports management of LWP state and allows applications to use LWP. When the system makes LWP available by setting bit 62 of XFEATURE_ENABLED_MASK, LWP is initially disabled (LWP_CBADDR is zero).
See “Guidelines for Operating Systems” on page 477 for details on how to implement LWP support in 
an operating system.
13.4.4.2  LWP_CFG—LWP Configuration MSR
LWP_CFG (MSR C000_0105h) controls which features of LWP are available on the processor. The 
operating system loads LWP_CFG at start-up time (or at the time an LWP driver is loaded) to indicate its level of support for LWP. Only bits for supported features (those that are set in CPUID Fn8000_001C_EDX) can be turned on in LWP_CFG. Attempting to set other bits causes a #GP fault.
User code can examine LWP_CFG bits 31:1 by reading CPUID Fn8000_001C_EAX.2 LwpIRE Instructions retired event (EventId = 2) is supported.
3 LwpBRE Branch retired event (EventId = 3) is supported.
4 LwpDME DCache miss event (EventId = 4) is supported.
5 LwpCNH CPU clocks not halted event (EventId = 5) is supported.
6 LwpRNH CPU reference clocks not halted event (EventId = 6) is supported.
29 LwpCont Sampling in continuous mode is supported.
30 LwpPTSC Performance Time Stamp Counter in event records is supported. 
31 LwpInt Interrupt on threshold overflow is supported.Table 13 -9. Lightweight Profiling CPUID Values
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Bits 39:32 of LWP_CFG contains the COREID value that LWP will store into the CoreId field of 
every event record written by this core. The operating system should initialize this value to be the local APIC number, obtained from CPUID Fn0000_0001_EBX[LocalApicId] (bits 31:24). COREID is present so that when LWP is used in a virtualized environment, it has access to the core number without needing to enter the hypervisor. On systems that support x2APIC, local APIC numbers may be more than 8 bits wide. The operating system may then assign LWP COREID values that are small and identify the core within a cluster. If the system has more than 256 cores, there will be unavoidable duplication of COREID values.
Bits 47:40 of LWP_CFG specify the vector number that LWP will use when it signals a ring buffer 
threshold interrupt.
The reset value of LWP_CFG is 0.
Figure 13-37. LWP_CFG—Lightweight Profiling Features MSR
13.4.4.3  LWP_CBADDR—LWPCB Address MSR
LWP_CBADDR (MSR C000_0106h) provides access to the internal copy of the LWPCB linear 
address.6
36261605958575655545352515049484746454443424140393837363534333231302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
Reserved VECTOR COREID
INT
PTSC
CONTReserved
RNH
CNH
DME
BRE
IRE
V AL
Bits Field Description
0 Reserved
1 V AL Allow the LWPV AL instruction.
2 IRE Allow LWP to count instructions retired.3 BRE Allow LWP to count branches retired.4 DME Allow LWP to count DCache misses.5 CNH Allow LWP to count CPU clocks not halted.6 RNH Allow LWP to count CPU reference clocks not halted.
29 CONT Enable continuous mode. If 0, LWP will always use synchronized mode.
30 PTSCEnable storing Performance Time Stamp Counter (PTSC) in the TimeStamp field of 
event records, if PTSC is available.
31 INT Allow LWP to generate an interrupt when threshold is exceeded.
39:32 COREID Value to store in CoreId field when writing an event record.
47:40 VECTORInterrupt vector number to use for LWP Threshold interrupts. Must be provided if 
INT=1.
63:48 Reserved
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RDMSR from this register returns the current LWPCB address without performing any of the 
operations described for the SLWPCB instruction.
WRMSR to this register with a non-zero value generates a #GP fault; use LLWPCB or XRSTOR to 
load an LWPCB address. 
Writing a zero to LWP_CBADDR immediately disables LWP, discarding any internal state. For 
instance, an operating system can write a zero to stop LWP when it terminates a thread.
Note that LWP_CBADDR contains the linear address of the control block. All references to the 
LWPCB that are made by microcode during the normal operation of LWP ignore the DS segment register.
The reset value of LWP_CBADDR is 0. This means that when the system sets bit 62 of 
XFEATURE_ENABLED_MASK to make LWP available, it is initially disabled.
13.4.5  LWP Instructions

INT=1.
This section describes the instructions included in the AMD64 architecture to support LWP. These instructions raise #UD if LWP is not supported or if bit 62 of XFEATURE_ENABLED_MASK is 0 indicating that LWP is not available.
The LLWPCB instruction enables or disables Lightweight Profiling and controls the events being 
profiled. The SLWPCB instruction queries the current state of Lightweight Profiling.
LWP provides two instructions for inserting user data into the event ring buffer. The LWPINS 
instruction unconditionally stores an event record into the ring buffer, while the LWPV AL instruction uses an LWP event counter to sample program values at defined intervals.
The instructions LLWPCB, SLWPCB, LWPINS, and LWPV AL are also described in the chapter 
“General-Purpose Instruction Reference” of V olume 3. Refer to reference pages for the individual instruction for information on instruction encoding, flags affected, and exception behavior.
13.4.5.1  LLWPCB—Load LWPCB Address
Parses the Lightweight Profiling Control Block at the address contained in the specified register. If the 
LWPCB is valid, writes the address into the LWP_CBADDR MSR and enables Lightweight Profiling.
The LWPCB must be in memory that is readable and writable in user mode. For better performance, it 
should be aligned on a 64-byte boundary in memory and placed so that it does not cross a page boundary, though neither of these suggestions is required.
Action
1. If LWP is not available or if the machine is not in protected mode, LLWPCB immediately causes 
a #UD exception.
2. If LWP is already enabled, the processor flushes the LWP state to memory in the old LWPCB. See 
“SLWPCB—Store LWPCB Address” on page 458 for details on saving the active LWP state.
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If the flush causes a #PF exception, LWP remains enabled with the old LWPCB still active. Note 
that the flush is done before LWP attempts to access the new LWPCB.
3. If the specified LWPCB address is 0, LWP is disabled and the execution of LLWPCB is complete.
4. The LWPCB address is non-zero. LLWPCB validates it as follows:
- If any part of the LWPCB or the ring buffer is beyond the data segment limit, LLWPCB causes 
a #GP exception.
- If the ring buffer size is below the implementation’s minimum ring buffer size, LLWPCB 
causes a #GP exception. 
- While doing these checks, LWP reads and writes the LWPCB, which may cause a #PF 
exception. 
If any of these exceptions occurs, LLWPCB aborts and LWP is left disabled. Usually, the operating 
system will handle a #PF exception by making the memory available and returning to retry the LLWPCB instruction. The #GP exceptions indicate application programming errors.
5. LWP converts the LWPCB address and the ring buffer address to linear address form by adding 
the DS base address and stores the addresses internally. 
6. LWP examines the LWPCB.Flags field to determine which events should be enabled and whether 
threshold interrupts should be taken. It clears the bits for any features that are not available and stores the result back to LWPCB.Flags to inform the application of the actual LWP state.
7. For each event being enabled, LWP examines the EventInterval n value and, if necessary, sets it to 
an implementation-defined minimum. (The minimum event interval for LWPV AL is zero.) It loads its internal counter for the event from the value in EventCounter n. A zero or negative value 
in EventCounter n means that the next event of that type will cause an event record to be stored. To 
count every j
th event, a program should set EventInterval n to j-1 and EventCounter n to some 
starting value (where j-1 is a good initial count). If the counter value is larger than the interval, the 
first event record will be stored after a larger number of events than subsequent records.
8. LWP is started. The execution of LLWPCB is complete.
Notes
If none of the bits in the LWPCB.Flags specifies an available event, LLWPCB still enables LWP to 
allow the use of the LWPINS instruction. However, no other event records will be stored.
A program can temporarily disable LWP by executing SLWPCB to obtain the current LWPCB 
address, saving that value, and then executing LLWPCB with a register containing 0. It can later re-enable LWP by executing LLWPCB with a register containing the saved address.
When LWP is enabled, it is typically an error to execute LLWPCB with the address of the active 
LWPCB. When the hardware flushes the existing LWP state into the LWPCB, it may overwrite fields that the application may have set to new LWP parameter values. The flushed values will then be loaded as LWP is restarted. To reuse an LWPCB, an application should stop LWP by passing a zero to LLWPCB, then prepare the LWPCB with new parameters and execute LLWPCB again to restart LWP.
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Internally, LWP keeps the linear address of the LWPCB and the ring buffer. If the application changes 
the value of DS, LWP will continue to collect samples even if the new DS value would no longer allows it to access the LWPCB or the ring buffer. However, a #GP fault will occur if the application uses XRSTOR to restore LWP state saved by XSA VE. Programs should avoid using XSA VE/XRSTOR on LWP state if DS has changed. This only applies when the CPL ≠ 0; kernel mode operation of XRSTOR is unaffected by changes to DS. See “XSA VE/XRSTOR” on page 470 for details.
Operating system and hypervisor code that runs when the CPL ≠ 3 should use XSA VE and XRSTOR 
to control LWP rather than using LLWPCB (see below). Use WRMSR to write 0 to LWP_CBADDR to immediately stop LWP without saving its current state (see “LWP_CBADDR—LWPCB Address 
MSR” on page 455).
It is possible to execute LLWPCB when the CPL ≠ 3 or when SMM is active, but the system software 
must ensure that the LWPCB and the entire ring buffer are properly mapped into writable memory in order to avoid a #PF or #GP fault. Furthermore, if LWP is enabled when a kernel executes LLWPCB, both the old and new control blocks and ring buffers must be accessible. Using LLWPCB in these situations is not recommended. 
13.4.5.2  SLWPCB—Store LWPCB Address
Flushes LWP state to memory and returns the current effective address of the LWPCB in the specified 
register. 
If LWP is not currently enabled, SLWPCB sets the specified register to zero.The flush operation stores the internal event counters for active events and the current ring buffer head 
pointer into the LWPCB. If there is an unwritten event record pending, it is written to the event ring buffer.
If LWP_CBADDR is not zero, the value returned is an effective address that is calculated by 
subtracting the current DS.Base address from the linear address kept in LWP_CBADDR. Note that if DS has changed between the time LLWPCB was executed and the time SLWPCB is executed, this might result in an address that is not currently accessible by the application.
SLWPCB generates an invalid opcode exception (#UD) if the machine is not in protected mode or if 
LWP is not available.
It is possible to execute SLWPCB when the CPL ≠ 3 or when SMM is active, but if the LWPCB 
pointer is not zero, the system software must ensure that the LWPCB and the entire ring buffer are properly mapped into writable memory in order to avoid a #PF fault. Using SLWPCB in these situations is not recommended.
13.4.5.3  LWPVAL—Insert Value Sample in LWP Ring Buffer
Decrements the event counter associated with the Programmed Value Sample event (see “Programmed 
Value Sample” on page 443). If the resulting counter value is negative, inserts an event record into the 
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LWP event ring buffer in memory and advances the ring buffer pointer. If the counter is not negative 
and the ModRM operand specifies a memory location, that location is not accessed.
The event record has an EventId of 1. The value in the register specified by vvvv (first operand) is 
stored in the Data2 field at bytes 23–16 (zero extended if the operand size is 32). The value in a register or memory location (second operand) is stored in the Data1 field at bytes 7–4. The immediate value (third operand) is truncated to 16 bits and stored in the Flags field at bytes 3–2. See Figure 13 -30 on 
page 443.
If the ring buffer is not full or if LWP is running in continuous mode, the head pointer is advanced and 
the event counter is reset to the interval for the event (subject to randomization). If the ring buffer threshold is exceeded and threshold interrupts are enabled, an interrupt is signaled. If LWP is in continuous mode and the new head pointer equals the tail pointer, the MissedEvents counter is incremented to indicate that the buffer wrapped.
If the ring buffer is full and LWP is running in synchronized mode, the event record overwrites the last

page 443.
If the ring buffer is full and LWP is running in synchronized mode, the event record overwrites the last 
record in the buffer, the MissedEvents counter in the LWPCB is incremented, and the head pointer is not advanced.
LWPV AL generates an invalid opcode exception (#UD) if the machine is not in protected mode or if 
LWPV AL does nothing if LWP is not enabled or if the Programmed Value Sample event is not enabled 
in LWPCB.Flags. This allows LWPV AL instructions to be harmlessly ignored if profiling is turned off.
It is possible to execute LWPV AL when the CPL ≠ 3 or when SMM is active, but the system software 
must ensure that the memory operand (if present), the LWPCB, and the entire ring buffer are properly mapped into writable memory in order to avoid a #PF or #GP fault. Using LWPV AL in these situations is not recommended.
LWPV AL can be used by a program to perform value profiling. This is the technique of sampling the 
value of some program variable at a predetermined frequency. For example, a managed runtime might use LWPV AL to sample the value of the divisor for a frequently executed divide instruction in order to determine whether to generate specialized code for a common division. It might sample the target location of an indirect branch or call to see if one destination is more frequent than others. Since LWPV AL does not modify any registers or condition codes, it can be inserted harmlessly between any instructions.
Note
When LWPV AL completes (whether or not it stored an event record in the event ring buffer), it counts 
as an instruction retired. If the Instructions Retired event is active, this might cause that counter to become negative and immediately store an event record. If LWPV AL also stored an event record, the buffer will contain two records with the same instruction address (but different EventId values).
13.4.5.4  LWPINS—Insert User Event Record in LWP Ring Buffer
Inserts a record into the LWP event ring buffer in memory and advances the ring buffer pointer.
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The record has an EventId of 255. The value in the register specified by vvvv (first operand) is stored 
in the Data2 field at bytes 23–16 (zero extended if the operand size is 32). The value in a register or memory location (second operand) is stored in the Data1 field at bytes 7–4. The immediate value (third operand) is truncated to 16 bits and stored in the Flags field at bytes 3–2. See Figure 13 -36 on 
page 450.
the CF flag is cleared. If the ring buffer threshold is exceeded and threshold interrupts are enabled, an interrupt is signaled. If LWP is in continuous mode and the new head pointer equals the tail pointer, the MissedEvents counter is incremented to indicate that the buffer wrapped.
record in the buffer, the MissedEvents counter in the LWPCB is incremented, the head pointer is not advanced, and the CF flag is set.
LWPINS generates an invalid opcode exception (#UD) if the machine is not in protected mode or if 
LWPINS simply clears CF if LWP is not enabled. This allows LWPINS instructions to be harmlessly 
ignored if profiling is turned off.
It is possible to execute LWPINS when the CPL ≠ 3 or when SMM is active, but the system software 
must ensure that the memory operand (if present), the LWPCB, and the entire ring buffer are properly mapped into writable memory in order to avoid a #PF or #GP fault. Using LWPINS in these situations is not recommended.
LWPINS can be used by a program to mark significant events in the ring buffer as they occur. For 
instance, a program might capture information on changes in the process’ address space such as library loads and unloads, or changes in the execution environment such as a change in the state of a user-mode thread of control.
Note that when the LWPINS instruction finishes writing a event record in the event ring buffer, it 
counts as an instruction retired. If the Instructions Retired event is active, this might cause that counter to become negative and immediately store another event record with the same instruction address (but different EventId values).
13.4.6  LWP Control Block
An application uses the LWP Control Block (LWPCB) to specify the details of Lightweight Profiling operation. It is an interactive region of memory in which some fields are controlled and modified by the LWP hardware and others are controlled and modified by the software that processes the LWP event records.
Most of the fields in the LWPCB are constant for the duration of a LWP session (the time between 
enabling LWP and disabling it). This means that they are loaded into the LWP hardware when it is enabled, and may be periodically reloaded from the same location as needed. The contents of the 
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constant fields must not be changed during a LWP run or results will be unpredictable. Changing the 
LWPCB memory to read-only or unmapped will cause an exception the next time LWP attempts to access it. To change values in the LWPCB, disable LWP, change the LWPCB (or create a new one), and re-enable LWP.
A few fields are modified by the LWP hardware to communicate progress to the software that is 
emptying the event ring buffer. Software may read them but should never modify them during an LWP session. Other fields are for software to modify to indicate that progress has been made in emptying the ring buffer. Software writes these fields and the LWP hardware reads them as needed.
For efficiency, some of the LWPCB fields may be shadowed internally in the LWP hardware unit when 
profiling is enabled. LWP refreshes these fields from (or flushes them to) memory as needed to allow software to make progress. For more information, refer to “LWPCB Access” on page 476.
The BufferTailOffset field is at offset 64 in the LWPCB in order to place it in a separate cache line on 
most implementations, assuming that the LWPCB itself is aligned properly. This allows the software thread that is emptying the ring buffer to retain write ownership of that cache line without colliding with the changes made by LWP when writing BufferHeadOffset. In addition, most implementations will use a value of 128 as the offset to the EventInterval1 field, since that places the event information in a separate cache line.
All fields in the LWPCB (as shown in Figure 13 -38) that are marked as “Reserved” (or “Rsvd”) should 
be zero.
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Figure 13 -38. LWPCB—Lightweight Profiling Control Block
The R/W column in Table 13 -10 below indicates how a field is used while LWP is enabled:Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Random BufferSize Flags 0
BufferBase 8
Reserved BufferHeadOffset 16
MissedEvents 24
Filters Threshold 32
BaseIP 40
LimitIP 48
Reserved 56
Reserved BufferTailOffset 64
Reserved for software 72
Reserved for software 80
.
.
Reserved
..88
7 2
Rsvd25 0
EventCounter17 2
Rsvd25 0
EventInterval1
E = LwpEventOffsetE
7 2
Rsvd25 0
EventCounter27 2
Rsvd25 0
EventInterval2E 
+8
. . .
7 2
Rsvd25 0
EventCounter N7 2
Rsvd25 0
EventInterval N
N = LwpMaxEvents...
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•LWP—hardware modifies the field; software may read it, but must not change it
•Init—hardware reads and modifies the field while executing LLWPCB; the field must then remain 
unchanged as long as the LWPCB is in use
•SW—software may modify the field; hardware may read it, but does not change it
•No—field must remain unchanged as long as the LWPCB is in use
Table 13-10. LWPCB —Lightweight Profiling Control Block Fields
Bytes Bits Field Description R/W
3–0 FlagsFlags indicating which events should be or are being counted (see 
Figure 13-39, “LWPCB Flags”) and whether threshold interrupts should be enabled.
Before executing LLWPCB, the application sets Flags to a bit mask of 
the events (and interrupt) that should be enabled. LLWPCB does a logical “and” of this mask with the available feature bits in LWP_CFG and rewrites Flags with the mask of features actually enabled.Init
7–4 27:0 BufferSizeTotal size of the event ring buffer (in bytes). Must be a multiple of the event record size LwpEventSize (the value used internally will be rounded down if not). BufferSize must be at least (32 * LwpMinBufferSize * LwpEventSize).No
7 7:4 RandomNumber of bits of randomness to use in counters. Each time a counter is loaded from an interval to start counting down to the next event to record, the bottom Random bits are set to a random value. This avoids fixed patterns in events.No

15–8 BufferBaseThe Effective Address of the event ring buffer. Should be aligned on a 64-byte boundary for reasonable performance. Software is encouraged to align the ring buffer to a page boundary for best performance. If the default address size is less than 64 bits, the upper bits of BufferBase must be zero.
LLWPCB converts BufferBase to a linear address and stores it 
internally. LWPCB.BufferBase is not modified.No
19–16 BufferHeadOffsetUnsigned offset from BufferBase specifying where the LWP hardware will store the next event record. When BufferHeadOffset == BufferTailOffset, the ring buffer is empty. BufferHeadOffset must always be less than BufferSize; LWP will use a value of 0 if BufferHeadOffset is too large. Also, it must always be a multiple of LwpEventSize; LWP will round it down if not.LWP
23–20 Reserved
31–24 MissedEventsThe 64-bit count of the number of events that were missed. A missed event occurs when LWP stores an event record, attempts to advance BufferHeadOffset, and discovers that it would be equal to BufferTailOffset. In this case, LWP leaves BufferHeadOffset unchanged and instead increments the MissedEvents counter. Thus, when the ring buffer is full, the last event record is overwritten.LWP
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35–32 ThresholdThreshold for signaling an interrupt to indicate that the ring buffer is 
filling up. If threshold interrupts are enabled in Flags, then when LWP advances BufferHeadOffset, it computes the space used as ((BufferHeadOffset – BufferTailOffset) % BufferSize). If the space used equals or exceeds Threshold, LWP causes an interrupt. 
If Threshold is greater than BufferSize, no interrupt will ever be taken. 
If Threshold is zero, an interrupt will be taken every time an event record is stored in the ring buffer.
Threshold is an unsigned integer multiple of LwpEventSize (the value 
used internally will be rounded down if not).
Ignored if threshold interrupts are not available in LWP_CFG or if they 
are not enabled in FlagsNo
39–36 FiltersFilters to qualify which events are eligible to be counted. This field includes bits to filter branch events by type and prediction status, and bits and values to filter cache events by type and latency. See Figure 13-40, “LWPCB Filters” for details.
47–40 BaseIPLow limit of the IP filtering range. An instruction must start at a location greater than or equal to BaseIP to be in range.
Ignored if IPF is zero or if the CPUID LwpIpFiltering bit is 0 to indicate 
that IP filtering is not supported.No
55–48 LimitIPHigh limit of the IP filtering range. An instruction must start at a location less than or equal to LimitIP to be in range.
63–56 Reserved
67–64 BufferTailOffsetUnsigned offset from BufferBase to the oldest event record in the ring buffer. BufferTailOffset is maintained by software and must always be less than BufferSize and a multiple of LwpEventSize. If software stores a value of BufferTailOffset into the LWPCB that violates these rules, the LWP hardware might not detect ring buffer overflow or threshold conditions properly.SW
71–68 Reserved
72–87Reserved for software use. These bytes are never read or written by the LWP hardwareSW
(E-1) – 
88Reserved area between the fixed portion of the LWPCB and the event specifiers. Should be zero. The EventInterval1 field is at offset E = 
LwpEventOffset.Table 13-10. LWPCB —Lightweight Profiling Control Block Fields (continued)
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The LLWPCB instruction reads the Flags word from the LWPCB to determine which events to profile 
and whether threshold interrupts should be enabled. LLWPCB writes the Flags word after turning off bits corresponding to features which are not currently available.(E+3)–
E25:0 EventInterval1Reset value for counting events of type EventId = 1 (Programmed Value 
Sample). A value of n specifies that after n+1 (modified by Random) 
LWPV AL instructions, LWP will store an event record in the ring buffer.
EventInterval1 is a signed value. If it is negative, LLWPCB will use 
zero and will store zero into EventInterval1 in the LWPCB.
The Programmed Value Sample event is the only one which allows an 
interval to be below the implementation minimum interval value.Init
E+3 7:2 Reserved
(E+7)– 
(E+4)25:0 EventCounter1Starting (LLWPCB) or current (SLWPCB) value of counter. This is a signed number. LLWPCB treats a negative value as zero.LWP
E+7 7:2 Reserved
(E+11)
– 
(E+8 )25:0 EventInterval2Reset value for counting events of type EventId = 2 (Instructions Retired). A value of n specifies that after n+1 (modified by Random) 
instructions are retired, LWP will store an event record in the ring buffer.
EventInterval2 is a signed value. If it is negative or is below the 
implementation minimum, LLWPCB will use the minimum and will store that value into EventInterval2 in the LWPCB.Init
E+11 7:2 Reserved
(E+15) 
– 
(E+12)57:32 EventCounter2Starting (LLWPCB) or current (SLWPCB) value of counter. This is a signed number. LLWPCB treats a negative value as zero.LWP
E+15 7:2 Reserved
Event3…Repeat event configuration similar to EventInterval2 and EventCounter2 for EventId values from 3 to LwpMaxEvents.Table 13-10. LWPCB —Lightweight Profiling Control Block Fields (continued)
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Figure 13-39. LWPCB Flags
Event counting can be filtered by a number of conditions which are specified in the Filters word of the 
LLWPCB. The IP filtering applies to all events. Cache level filtering applies to all events that interact with the caches. Branch filtering applies to the Branches Retired event.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0INT
PTSC
RNH
CNH
DME
BRE
IRE
V AL
Bit Field Input to LLWPCB Value after LLWPCB
0 Reserved
1 V AL Enable LWPV AL instruction LWPV AL instruction enabled
2 IRE Enable Instructions Retired event Instructions Retired event enabled
3 BRE Enable Branches Retired event Branches Retired event enabled
4 DME Enable DCache miss event DCache Miss event enabled
5 CNH Enable CPU clocks not halted event CPU Clocks Not Halted event enabled
6 RNH Enable CPU reference clocks not halted eventCPU Reference Clocks Not Halted event 
enabled
29 CONT1—Use continuous mode. If the ring buffer 
overflows, LWP continues to store events and advance BufferHead. Software must stop LWP in order to empty the ring buffer.
0—Use synchronized mode.LWP operates in continuous mode if input bit is set and continuous mode is available. Otherwise, LWP operates in synchronous mode.
30 PTSC1—Store the Performance Time Stamp 
Counter (PTSC) in the TimeStamp field of 
each event record, if PTSC is available.
0—Store 0 in the TimeStamp field.Performance Time Stamp Counter value will 
be stored if input bit is set and PTSC feature is available. Otherwise 0 is stored.
31 INT Enable threshold interrupts. Threshold interrupts are enabled.
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Figure 13-40. LWPCB Filters
The following table provides detailed descriptions of the fields in the Filters word.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0IPF
IPI
NRB
NCB
NAB
NPB
NMBReserved
OTH
RAM
RDC
NBC
CLFMinLatency
7:0 MinLatency Minimum latency for a cache-related event8 CLF Cache level filtering9 NBC Northbridge cache events10 RDC Remote data cache events11 RAM DRAM cache events12 OTH Other cache events
24:13 Reserved
25 NMB No mispredicted branches26 NPB No predicted branches27 NAB No absolute branches28 NCB No conditional branches29 NRB No unconditional relative branches30 IPI IP filtering invert
31 IPF IP filtering
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Table 13-11. LWPCB Filters Fields
7:0 MinLatencyMinimum latency for a cache-related event to be eligible for LWP counting. Applies 
to all cache-related events being monitored. MinLatency is multiplied by 16 to get the actual latency in cycles, providing less resolution but a larger range for filtering. An implementation may have a maximum for the latency value. If MinLatency*16 exceeds this maximum value, the maximum is used instead. A value of 0 disables filtering by latency. 
Ignored if no cache latency event is enabled or if the CPUID LwpCacheLatency bit 
is 0 to indicate that the implementation does not filter by latency (use the CLF bits to get a similar effect). At least one of these mechanisms is supported if any cache miss events are supported.
8 CLFCache level filtering.

1—Enables filtering cache-related events by the cache level or memory level that 
returned the data. It enables the next 4 bits. Cache-related events are only 
eligible for counting if the bit describing the memory level is on.
0—Disables cache level filtering. The next 4 bits are ignored, and any cache or 
memory level is eligible. 
Ignored if no cache latency event is enabled or if the CPUID LwpCacheLevels bit is 0 to indicate that the implementation does not filter by cache level (use the MinLatency field to get a similar effect). At least one of these mechanisms is supported if any cache miss events are supported.
9 NBCNorthbridge cache events.
1—Count cache-related events that are satisfied from data held in a cache that 
resides on the Northbridge.
0—Ignore Northbridge cache eventsIgnored if CLF is 0.
10 RDCRemote data cache events.1—Count cache-related events that are satisfied from data held in a remote data 
cache.
0—Ignore remote cache events.Ignored if CLF is 0.
11 RAMDRAM cache events.1—Count cache-related events that are satisfied from DRAM.0—Ignore DRAM cache events.Ignored if CLF is 0.
12 OTHOther cache events.1—Count cache-related events that are satisfied from other sources, such as MMIO, 
Config space, PCI space, or APIC.
0—Ignore such cache eventsIgnored if CLF is 0.
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25 NMBNo mispredicted branches.
1—Mispredicted branches will not be counted.0—Mispredicted branches will be counted if not suppressed by other filter 
Caution: If NMB and NPB are both set, no branches will be counted.Ignored if the Branches Retired event is not enabled or if the CPUID 
LwpBranchPrediction bit is 0 to indicate that the implementation does not filter by prediction.
26 NPBNo predicted branches.
1—Correctly predicted branches will not be counted. Note that since direct branches 
are always predicted correctly, this is a superset of the NDB filter.
0—Correctly predicted branches will be counted if not suppressed by other filter 
27 NABNo absolute branches.
1—Absolute branches will not be counted. This only applies to jumps through a 
register or memory (JMP opcode FF /4) and calls through a register or memory 
(CALL opcode FF /2). Relative branches (both conditional and unconditional) are counted normally if not disabled via the NRB or NCB bits.
0—Absolute branches will be counted if not suppressed by other filter conditions.
Caution: If NRB, NCB, and NAB are all set, no branches will be counted.Ignored if the Branches Retired event is not enabled.
28 NCBNo conditional branches.1—Conditional branches will not be counted. This only applies to conditional jumps 
(Jcc) and loops (LOOPcc). Unconditional relative branches, indirect jumps 
through a register or memory, and returns are counted normally if not disabled via the NRB or NAB bits.
0—Conditional branches will be counted if not suppressed by other filter conditions.
Caution: If NRB, NCB, and NAB are all set, no branches will be counted.Ignored if the Branches Retired event is not enabled.Table 13 -11. LWPCB Filters Fields (continued)
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13.4.7  XSAVE/XRSTOR
LWP requires that the processor support the XSA VE/XRSTOR instructions for managing extended 
processor state components.
13.4.7.1  Configuration
The processor uses bit 62 of XFEATURE_ENABLED_MASK (register XCR0) to indicate whether 
LWP state can be saved and restored, and thus whether LWP is available to applications. The LWP XSA VE area length and offset from the beginning of the XSA VE area are available from the CPUID instruction (see “Detecting LWP XSA VE Area” on page 451). In Version 1 of LWP, the LWP XSA VE 
area is 128 (080h) bytes long and the offset is 832 (340h) bytes.
13.4.7.2  XSAVE Area
Figure 13 -41 below shows the layout of the XSA VE area for LWP. It is large enough to allow for future 
expansion of the number of event counters. Details of the fields are in Table 13 -12.
All fields in the XSA VE area that are marked as “Reserved” (or “Rsvd”) must be zero.29 NRBNo unconditional relative branches.
1—Unconditional relative branches will not be counted. This applies to 
unconditional jumps (JMP), calls (CALL), and returns (RET). Conditional 
branches and indirect jumps or calls through a register or memory are counted normally if not disabled via the NCB or NAB bits.
0—Direct branches will be counted if not suppressed by other filter conditions.
30 IPIIP filtering invert.1—IP filtering inverted. Only instructions outside the range from BaseIP to LimitIP 
are eligible for LWP counting.
0—IP filtering normal. Only instructions inside the range from BaseIP to LimitIP 
Ignored if IPF is zero or if the CPUID LwpIpFiltering bit is 0 to indicate that IP 
filtering is not supported.
31 IPFIP filtering.
1—IP filtering enabled. The values of the BaseIP and LimitIP fields specify a range 
of instruction addresses that are eligible for LWP event counting and reporting. 
The range is inclusive if IPI is 0 and exclusive if IPI is 1.
0—IP filtering disabled; instructions at every address are eligible for LWP counting.
Ignored if the CPUID LwpIpFiltering bit is 0 to indicate that IP filtering is not 
supported.Table 13 -11. LWPCB Filters Fields (continued)
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Figure 13-41. XSAVE Area for LWPByte 7 Byte 06 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
LWPCBAddress 0
BufferHeadOffset Counter Flags (Reserved) Cntr Flags 8
BufferBase 16
Filters31 28
Rsvd27 0
BufferSize 24
Saved Event Record32
404856
EventCounter2 EventCounter1 64
EventCounter4 EventCounter3 72
EventCounter6 EventCounter5 80
Reserved for EventCounter8 Reserved for EventCounter7 88
Reserved for EventCounter10 Reserved for EventCounter9 96
Reserved for EventCounter12 Reserved for EventCounter11 104
Reserved for EventCounter14 Reserved for EventCounter13 112
Reserved for EventCounter16 Reserved for EventCounter15 120
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13.4.7.3  XSAVE operation
If LWP is not currently enabled (i.e., if LWP_CBADDR = 0), no state needs to be stored. XSA VE sets 
bit 62 in XSA VE.HEADER.XSTATE_BV to 0 so that an attempt to restore state from this save area 
will use the processor supplied values. See “Processor supplied values” on page 474.
If LWP is enabled, XSA VE stores the various internal LWP values into the XSA VE area with no 
checking or conversion and sets bit 62 in XSA VE.HEADER.XSTATE_BV to 1.
13.4.7.4  XRSTOR operation
If bit 62 in XFEATURE_ENABLED_MASK (XCR0) is 0 or if bit 62 of EDX:EAX (EDX[30]) is 0, 
XRSTOR does not alter the LWP state.
If the above bits are 1 but bit 62 in XSA VE.HEADER.XSTATE_BV is 0, XRSTOR writes the LWP 
state using the processor supplied values, disabling LWP. See “Processor supplied values” on 
page 474.
If all of the above bits are 1, XRSTOR loads LWP state from the XSA VE area as follows:
1. The internal pointers and sizes are loaded. Table 13 -12. XSAVE Area for LWP Fields
7–0 LWPCBAddressAddress of LWPCB. 0 if LWP is disabled, in which case the rest of the save 
area is ignored. This is a linear address.
9–8 0 — Reserved
9–8 1 CntrFlags.Counter11—Event with EventId 1 is active. XRSTOR will make the event active 
and restore its counter from EventCounter1.
0—Event 1 is not active. XRSTOR will make the event inactive.
9–8 6:2 CntrFlags.Countern Bit flags defined as above for EventCounter2–6.
9–8 15:7 — Reserved for counter flags
11–10 15:0 — Reserved for counter flags
15–12 BufferHeadOffset BufferHeadOffset value
23–16 BufferBase Address of the event ring buffer. This is a linear address.
27–24 27:0 BufferSize Size of the event ring buffer
27–24 31:28 — Reserved
31–28 Filters Profiling filters (same as the Filters field in the LWPCB)
63–32 SavedEventRecordIf an event record is pending, the data to write. May be sparse. Zero in the 
EventId field means no record pending.
67–64 EventCounter1 Counter for event 1 (valid if CntrFlags.Counter1 bit is set)
87–68 EventCounter n Counters for events 2–6 (valid if the respective Countern bit is set)
127–88 — Reserved for future event counters
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- If BufferSize is below the implementation minimum, LWP is disabled and XRSTOR of LWP 
state terminates.

- If BufferSize is not a multiple of the event record size, it is rounded down.
- If BufferHeadOffset is greater than (BufferSize - LwpEventSize), a value of 0 is used instead.- If BufferHeadOffset is not a multiple of the event record size, it is rounded down.
2. For each bit that is set in the Flags field that corresponds to an available event (as currently set in 
the LWP_CFG MSR), the corresponding event is enabled and the event counter is loaded from the 
EventCounter n field. All other events are disabled. 
3. If the EventId field in the SavedEventRecord is non-zero, there was a pending event when 
XSA VE was executed. XRSTOR loads the event record into hardware. LWP will store it into the event ring buffer as soon as possible once the CPL is 3. 
Software should not alter the SavedEventRecord field. An implementation may ignore a saved 
event record if it was not constructed by XSA VE. Storing an event into SavedEventRecord and then executing XRSTOR is not a reliable way of injecting an event into the ring buffer. 
Note that if LWP is already enabled when executing XRSTOR, the old LWP state is overwritten without being saved.
No interrupt is generated by XRSTOR if the restored value of BufferHeadOffset results in a buffer that 
is filled beyond the threshold. The interrupt will occur the next time an event record is stored.
XRSTOR may not restore all of the state necessary for LWP to operate. The LWP hardware will read 
additional state from the LWPCB when it stores then next event record.
If the CPL = 0, XRSTOR simply reloads the LWPCB address and the ring buffer address from the 
XSA VE area. Kernel software is trusted not to alter the area in such a way as to allow access to memory that the application could not otherwise read or write. The linear addresses in the XSA VE area were validated when the application executed LLWPCB.
If the CPL ≠ 0, XRSTOR first validates the LWPCB and ring buffer pointers. This prevents an 
application from altering the XSA VE area in order to gain access to memory that it could not otherwise read or write (based on the current values in the DS segment register). Note that if a program’s DS value changes after doing a successful LLWPCB, it might be incapable of doing an XSA VE and then an XRSTOR of LWP state. The XRSTOR will fail if the new DS value no longer allows access to the linear addresses corresponding to the LWPCB or the ring buffer. Programs should avoid this behavior.
If XRSTOR is executed when the CPL ≠ 0, the system performs additional checks on the LWPCB and 
ring buffer addresses according to the pseudo-code below. A “Store-type Segment_check” fails if the limit check fails (address is beyond the segment limit) or if the segment is read-only.
bool Check(uint64 addr, uint32 size) { // Utility function
if (!64bit_Mode)
addr = truncate32(addr - DS.BASE)
uint64 top = addr + size - 1;
if (! Store-type Segment_check on DS:[addr] || // Check lower bound
! Store-type Segment_check on DS:[top]) // and upper bound
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return false;
return true;
}
if (! Check(XSAVE.LWPCBAddress, sizeof(LWPCB)) ||
! Check(XSAVE.BufferAddress, XSAVE.BufferSize))
Disable LWP
If any of the address checks fails, LWP is disabled. No fault is generated. A program that executes 
XRSTOR when the CPL ≠ 0 and DS has changed can use SLWPCB to check whether LWP is running.
As with all features that use XSA VE and XRSTOR, if bit 62 of XFEATURE_ENABLED_MASK 
(XCR0) is 0 but bit 62 of XSA VE.HEADER.XSTATE_BV is 1, XRSTOR will cause a #GP(0) exception.
13.4.7.5  Processor supplied values
If XRSTOR is executed when bit 62 of XFEATURE_ENABLED_MASK (XCR0) and EDX:EAX are 
both 1, but the corresponding bit in XSA VE.HEADER.XSTATE_BV is 0, it indicates that there is no 
LWP state to restore. In this case, LWP_CBADDR is set to 0 and LWP is disabled. Other processor internal state for LWP is set to 0 as necessary to avoid security issues.
13.4.8  Implementation Notes
The following subsections describe other LWP considerations.
13.4.8.1  Multiple Simultaneous Events
Multiple events are possible when an instruction retires. For instance, an indirect jump through a 
pointer in memory can trigger the instructions retired, branches retired, and DCache miss events simultaneously. LWP counts all events that apply to the instruction, but might not store event records for all events whose event counters became negative. It is implementation dependent as to how many event records are stored when multiple event counters simultaneously become negative. If not all events cause event records to be stored, the choice of which event(s) to report is implementation dependent and may vary from run to run on the same processor.
13.4.8.2  Processor State for Context Switch, SVM, and SMM
Implementations of LWP have internal state to hold information such as the current values of the 
counters for the various events, a pointer into the event ring buffer, and a copy of the tail pointer for quick detection of threshold and overflow states.
There are times when the system must preserve the volatile LWP state. When the operating system 
context switches from one user thread to another, the old user state must be saved with the thread’s context and the new state must be loaded. When a hypervisor decides to switch from one guest OS to another, the same must be done for the guest systems’ states. Finally, state must be stored and reloaded when the system enters and exits SMM, since the SMM code may decide to shut off power to the core.
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Hardware does not maintain the LWP state in the active LWPCB. This is because the counters change 
with every event (not just every reported event), so keeping them in memory would generate a large amount of unnecessary memory traffic. Also, the LWPCB is in user memory and may be paged out to disk at any time, so the memory may not be available when needed. 
Saving State at Thread Context Switches
LWP requires that an operating system use the XSA VE and XRSTOR instructions to save and restore 
LWP state across context switches.
XRSTOR restores the LWP volatile state when restoring other system state. Some additional LWP 
state will be restored from the LWPCB when operations in ring 3 require that information.
LWP does not support the “lazy” state save and restore that is possible for floating point and SSE state. 
It does not interact with the CR0[TS] bit. Operating systems that support LWP must always do an XSA VE to preserve the old thread’s LWP context and an XRSTOR to set up the new LWP context. The OS can continue to do a lazy switch of the FP and SSE state by ensuring that the corresponding bits in EDX:EAX are clear when it executes the XSA VE and XRSTOR to handle the LWP context.
Saving State at SVM Worldswitch to a Different Guest
Hypervisors that allow guests to use LWP must save and restore LWP state when the guest OS 
changes. In addition to the usual information in the VMCB, the hypervisor must use XSA VE/XRSTOR to maintain the volatile LWP state and must also save and restore LWP_CFG. When switching between a guest that uses LWP and one that does not, the hypervisor changes the value of XFEATURE_ENABLED_MASK (XCR0), which ensures that LWP is only enabled in the appropriate guest.
A hypervisor need not modify the LWP state if the guest OS is not changed.
Enabling SVM Live Migration
Some hypervisors support live migration of a guest virtual machine. Live migration is when a 
hypervisor preserves the entire state of the guest running on one physical machine, copies that state to another physical machine, and then resumes execution of the guest on the new hardware.
To allow live migration among machines which may have different internal implementations of LWP, 
the hypervisor must present the common subset of features among all the hosts in the pool of machines that can be used. Furthermore, since the hypervisor may XSA VE LWP state on one machine and XRSTOR it on another machine, the contents of the XSA VE area must be consistent across all implementations.
This means that an implementation of LWP keeps all event counters internally, not in the LWPCB. If 
implementations were permitted to differ in this detail, a counter might not get properly restored after migrating the guest machine.
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Saving State at SMM Entry and Exit
SMM entry and exit must save and restore LWP state when the processor is going to change power 
state. SMM must use XSA VE/XRSTOR and must also save and restore LWP_CFG. Since LWP is ring 3 only and is inactive in System Management Mode, its state should not need to be saved and restored otherwise.
Notes on Restoring LWP State

The LWPCB may not be in memory at all times. Therefore, the LWP hardware does not attempt to 
access it while still in the OS kernel/VMM/SMM, since that access might fault. Some LWP state is restored once the processor is in ring 3 and can take a #PF exception without crashing. This usually happens the next time LWP needs to store an event record into the ring buffer.
13.4.8.3  LWPCB Access
Several LWPCB fields are written asynchronously by the LWP hardware and by the user software. 
This section discusses techniques for reducing the associated memory traffic. This is interesting to software because it influences what state is kept internally in LWP, and it explains the protocol between the hardware filling the event ring buffer and the software emptying it.
The hardware keeps an internal copy of the event ring buffer head pointer. It need not flush the head 
pointer to the LWPCB every time it stores an event record. The flush can be done periodically or it can be deferred until a threshold or buffer full condition happens or until the application executes LLWPCB or SLWPCB. Exceeding the buffer threshold always forces the head pointer to memory so that the interrupt handler emptying the ring buffer sees the threshold condition.
The hardware may keep an internal copy of the event ring buffer tail pointer. It need not read the 
software-maintained tail pointer unless it detects a threshold or buffer full condition. At that point, it rereads the tail pointer to see if software has emptied some records from the ring buffer. If so, it recomputes the condition and acts accordingly. This implies that software polling the ring buffer should begin processing event records when it detects a threshold condition itself. To avoid a race condition with software, the hardware rereads the tail pointer every time it stores an event record while the threshold condition appears to be true. (An implementation can relax this to “every n
th time” for 
some small value of n.) It also rereads it whenever the ring buffer appears to be full.
The interval values used to reset the counters can be cached in the hardware when the LLWPCB 
instruction is executed, or they can be read from the LWPCB each time the counter overflows. 
The ring buffer base and size are cached in the hardware.The MissedEvents value is a counter for an exceptional condition and is kept in memory.The cached LWP state is refreshed from the LWPCB when LWP is enabled either explicitly via 
LLWPCB or implicitly when needed in ring 3 after LWP state is restored via XRSTOR.
Caching implies that software cannot reliably change sampling intervals or other cached state by 
modifying the LWPCB. The change might not be noticed by the LWP hardware. On the other hand, changing state in the LWPCB while LWP is running may change the operation at an unpredictable 
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moment in the future if LWP context is saved and restored due to context switching. Software must 
stop and restart LWP to ensure that any changes reliably take effect.
13.4.8.4  Security
The operating system must ensure that information does not leak from one process to another or from 
the kernel to a user process. Hence, if it supports LWP at all, the operating system must ensure that the state of the LWP hardware is set appropriately when a context switch occurs and when a new process or thread is created. LWP state for a new thread can be initialized by executing XRSTOR with bit 62 of XSA VE.HEADER.XSTATE_BV set to 0 and the corresponding bit in EDX:EAX set to 1.
13.4.8.5  Interrupts
The LWP threshold interrupt vector number is specified in the LWP_CFG MSR. The operating system 
must assign a vector for LWP threshold interrupts and fill in the corresponding entry in the interrupt-descriptor table. Note that the LWP interrupt is not shared with the performance counter interrupt, since the system allows concurrent and independent use of those two mechanisms.
13.4.8.6  Memory Access During LWP Operation
When LWP needs to save an event record in the event ring buffer, it accesses the user memory 
containing the ring buffer and sometimes the memory containing the LWPCB. This causes a Page Fault (#PF) exception if those pages are not in memory.
A particular implementation of LWP has several ways to deal with page faults when storing an event 
record. These may include saving the event record in the XSA VE area and retrying the store later, re-executing the instruction, or discarding the event and reporting the next event of the appropriate type.
Note that this reinforces the notion that LWP is a sampling mechanism. Programs cannot rely on it to 
precisely capture every n
th instance of an event. It captures approximately  every nth instance.
13.4.8.7  Guidelines for Operating Systems
To support LWP, an operating system should follow the following guidelines. Most of these operations 
should be done on each core of a multi-core system.
System initialization
1. Use CPUID Fn0000_0000 to ensure that the system is running on an “Authentic AMD” 
processor, and then check CPUID Fn8000_0001_ECX[LWP] to ensure that the processor 
supports LWP.
Alternatively, check CPUID Fn0000_000D_EDX_x0[30] to ensure that the system supports the 
LWP XSA VE area, indicating that the processor supports LWP.
2. Enable XSA VE operations by setting CR4[OSXSA VE].
3. Enable LWP by executing XSETBV to set bit 62 of XCR0.
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4. Assign a unique interrupt vector number for LWP threshold interrupts and load the corresponding 
entry in the interrupt-descriptor table with the address of the interrupt handler. This handler 
should use some system-specific method to forward any threshold interrupts to the application.
5. Make LWP available by setting LWP_CFG. To enable all supported LWP features, set 
LWP_CFG[31:0] to the value returned by CPUID Fn8000_001C_EDX. Set 
LWP_CFG[COREID] to the APIC core number (or some other value unique to the core) and LWP_CFG[VECTOR] to the assigned interrupt vector number.
Thread support•For each thread, allocate an XSA VE area that is at least as big as the XFeatureEnabledSizeMax value returned by CPUID Fn0000_000D_EBX_x0 (ECX=0). This is good practice for any system that supports XSA VE.
•When creating a new process or thread, execute XRSTOR with bit 62 of EDX:EAX set to 1 and bit 
62 of XSA VE.HEADER.XSTATE_BV set to 0. This ensures that LWP is turned off for any new thread. Alternatively, use WRMSR to write 0 into LWP_CBADDR before starting the thread.
•When saving a running thread’s context, execute XSA VE with bit 62 of EDX:EAX set to 1 to save 
the thread’s LWP state. It takes almost no time or resources if the thread is not using LWP.
•When restoring a thread’s context, execute XRSTOR with bit 62 of EDX:EAX set to 1. This 
restores the LWP state for the thread or disables LWP if the thread is not using it.
•When a thread exits or aborts, use WRMSR to store 0 into LWP_CBADDR. This ensures that LWP is turned off.
13.4.8.8  Summary of LWP State
LWP adds the following visible state to the AMD64 architecture:
•CPUID Fn8000_0001_ECX[LWP] (bit 15) to indicate LWP support.
•CPUID Fn8000_001C to indicate LWP features.
•Two new MSRs: LWP_CFG, LWP_CBADDR,.
•Four new instructions: LLWPCB, SLWPCB, LWPINS, and LWPV AL.
•Bit 62 in XCR0 (XFEATURE_ENABLED_MASK)
•A new XSA VE area for LWP state.
•New fields for LWP state in the SVM and SMM context, whether in the VMCB and SMM save 
area or elsewhere.
See Section 3.3, “Processor Feature Identification,” on page 71 for information on using the CPUID instruction to obtain information about processor capabilities.
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14 Processor Initialization and Long Mode 
Activation
This chapter describes the hardware actions taken following a processor reset and the steps that must 
be taken to initialize processor resources and activate long mode. In some cases the actions required are implementation-specific with references made to the appropriate implementation-specific documentation.
14.1 Processor Initialization
System logic can initialize the processor in either of two ways. One method, called RESET, is usually initiated by the assertion of an external signal (typically designated RESET#). The other method, called INIT, is typically initiated by another processor by means of an INIT interprocessor interrupt (IPI). See “Interprocessor Interrupts (IPI)” on page 634 for more information.
Both initialization techniques place the processor in real mode and initialize processor resources to a 
known, consistent state from which software can begin execution. The processor begins execution when the RESET# pin is deasserted or the INIT state is exited.
The RESET method places the processor in a known state and prepares it to begin execution in real 
mode. The INIT method is similar except it does not modify the state of certain registers. See Section 14.1.3 on page 480 for a comparison of these initialization methods.

System logic ensures that the processor transitions through the RESET state whenever power is 
reapplied after a planned or unplanned interruption. A RESET can also be performed when power is stable. An INIT can be performed at any time after the processor is powered up.
14.1.1  Built-In Self Test (BIST)
An optional built-in self-test can be performed after the processor is reset. The mechanism for 
triggering the BIST is implementation-specific, and can be found in the hardware documentation  for 
the implementation. The number of processor cycles BIST can consume before completing is also 
implementation-specific but typically consumes several million cycles.
BIST can be used by system implementations to assist in verifying system integrity, thereby improving 
system reliability, availability, and serviceability. The internal BIST hardware generally tests all internal array structures for errors. These structures can include (but are not limited to):
•All internal caches, including the tag arrays as well as the data arrays.
•All TLBs.
•Internal ROMs, such as the microcode ROM and floating-point constant ROM.
•Branch-prediction structures.
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EAX is loaded with zero if BIST completes without detecting errors. If any hardware faults are 
detected during BIST, a non-zero value is loaded into EAX.
14.1.2  Clock Multiplier Selection
The internal processor clock runs at some multiple of the system clock. The processor-to-system clock 
multiple does not have to be fixed by a processor implementation but instead can be programmable through hardware or software, or some combination of the two. For information on selecting the processor-clock multiplier, see the BIOS and Kernel Developer’s Guide (BKDG) or Processor 
Programming Reference Manual  applicable to your product.
14.1.3  Processor Initialization State
Table 14 -1 shows the initial processor state following either RESET or INIT. Except as indicated, 
processor resources generally are set to the same value after either RESET or INIT.
Table 14-1. Initial Processor State
Processor Resource Value After RESET Value After INIT
CR0 0000_0000_6000_0010hCD and NW are unchanged
Bit 4 (reserved) = 1All others = 0
CR2, CR3, CR4 0
CR8 0 0 
EFER 0
RIP 0000_0000_0000_FFF0h
CSSelector = F000hBase = 0000_0000_FFFF_0000hLimit = FFFFhAttributes = See Table 14 -2 on page 482
DS, ES, FS, GS, SSSelector
 = 0000h
Base = 0
Limit = FFFFh
Attributes = See Table 14 -2 on page 482
GDTR, IDTRBase = 0Limit
 = FFFFh
LDTR, TRSelector = 0000h
Base = 0
RAX0
(non-zero if BIST is run and fails)0
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Table 14 -2 on page 482 shows the initial state of the segment-register attributes (located in the hidden 
portion of the segment registers) following either RESET or INIT. RDXFamily/Model/Stepping, including extended family and extended model—see 
“Processor Implementation Information” on page 483
RBX, RCX, RBP, RSP, RDI, RSI,
R8, R9, R10, R11, R12, R13, R14, 
R150
x87 Floating-Point StateFPR0–FPR7  = 0
Control Word = 0040h
Status Word = 0000hTag Word = 5555hInstruction CS = 0000hInstruction Offset = 0x87 Instruction Opcode = 0Data-Operand DS = 0000hData-Operand Offset = 0Not modified
64-Bit Media State MMX0–MMX7 = 0 Not modified
SSE StateXMM0–XMM15 = 0MXCSR = 1F80hNot modified
Memory-Type Range RegistersSee “Memory-Typing MSRs” on 
page 720Not modified
Machine-Check RegistersSee “Machine-Check MSRs” on page 722Not modified
DR0, DR1, DR2, DR3 0
DR6 0000_0000_FFFF_0FF0h
Time-Stamp Counter 0 Not modified
Performance-Monitor ResourcesSee “Performance-Monitoring MSRs” on page 724Not modified
Other Model-Specific RegistersSee “MSR Cross-Reference” on page 711Not modified
Instruction and Data CachesInvalidated Not modifiedInstruction and Data TLBs
APIC Disabled, see Table 16 -2 on page 624. Enabled, see Table 16 -2 on page 624.
SMRAM Base Address (SMBASE) 0003_0000h Not modified
XCR0 0000_0000_0000_0001h Not modified
PKRU 0000_0000h Not modifiedTable 14-1. Initial Processor State (continued)
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14.1.4  Multiple Processor Initialization
Following reset in multiprocessor configurations, the processors use a multiple-processor 
initialization protocol to negotiate which processor becomes the bootstrap  processor. This bootstrap 
processor then executes the system initialization code while the remaining processors wait for software initialization to complete. For further information, see the documentation for particular implementations of the architecture. 
14.1.5  Fetching the First Instruction
After a RESET or INIT, the processor is operating in 16-bit real mode. Normally within real mode, the 
code-segment base-address is formed by shifting the CS-selector value left four bits. The base address is then added to the value in EIP to form the physical address into memory. As a result, the processor can only address the first 1 Mbyte of memory when in real mode. 
However, immediately following RESET or INIT, the CS-selector register is loaded with F000h, but 
the CS base-address is not formed by left-shifting the selector. Instead, the CS base-address is 
initialized to FFFF_0000h. EIP is initialized to FFF0h. Therefore, the first instruction fetched from memory is located at physical-address FFFF_FFF0h (FFFF_0000h + 0000_FFF0h).
The CS base-address remains at this initial value until the CS-selector register is loaded by software. 
This can occur as a result of executing a far jump instruction or call instruction, for example. When CS is loaded by software, the new base-address value is established as defined for real mode (by left shifting the selector value four bits).Table 14-2. Initial State of Segment-Register Attributes
Attribute Value (Binary) Description
G 0 Byte Granularity
D/B 0 16-Bit Segment
L (CS Only) 0 Legacy-Mode Segment
P 1 Segment is Present
DPL 00 Privilege-Level 0
S and TypeCode 
SegmentS = 1Type = 1010Executable/Readable Code Segment
Data SegmentS = 1Type = 0010Read/Write Data Segment
LDTRS = 0Type = 0010LDT
TRS = 0Type = 0011Busy 16-Bit TSS
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14.2 Hardware Configuration
14.2.1  Processor Implementation Information
Software can read processor-identification information from the EDX register immediately following 
RESET or INIT. This information can be used to initialize software to perform processor-specific functions. The information stored in EDX is defined as follows:
•Stepping ID (bits 3:0) —This field identifies the processor-revision level.
•Extended Model (bits 19:16) and Model (bits 7:4) —These fields combine to differentiate
processor models within a instruction family. For example, two processors may share the same
microarchitecture but differ in their feature set. Such processors are considered different modelswithin the same instruction family. This is a split field, comprising an extended-model portion inbits 19:16 with a legacy portion in bits 7:4
•Extended Family (bits 27:20) and Family (bits 11:8) —These fields combine to differentiate
processors by their microarchitecture. 
The CPUID instruction can be used to obtain the same information. This is done by executing CPUID with either function 1 or function 8000_0001h. Additional information about the processor and the features supported can be gathered using CPUID with other feature codes. See Section 3.3, “Processor Feature Identification,” on page 71 for additional information.
14.2.2  Enabling Internal Caches
Following a RESET (but not an INIT), all instruction and data caches are disabled, and their contents 
are invalidated (the MOESI state is set to the invalid state). Software can enable these caches by clearing the cache-disable bit (CR0.CD) to zero (RESET sets this bit to 1). Software can further refine caching based on individual pages and memory regions. Refer to “Cache Control Mechanisms” on page 206 for more information on cache control.
Memory-Type Range Registers (MTRRs).  Following a RESET (but not an INIT), the 
MTRRdefType register is cleared to 0, which disables the MTRR mechanism. The variable-range and fixed-range MTRR registers are not initialized and are therefore in an undefined state. Before enabling the MTRR mechanism, the initialization software (usually platform firmware) must load these registers with a known value to prevent unexpected results. Clearing these registers, for example, sets memory to the uncacheable (UC) type. 
14.2.3  Initializing Media and x87 Processor State
Some resources used by x87 floating-point instructions and media instructions must be initialized by

Some resources used by x87 floating-point instructions and media instructions must be initialized by 
software before being used. Initialization software can use the CPUID instruction to determine whether the processor supports these instructions, and then initialize their resources as appropriate.
x87 Floating-Point State Initialization.  Table 14 -3 on page 484 shows the differences between the 
initial x87 floating-point state following a RESET and the state established by the FINIT/FNINIT instruction. An INIT does not modify the x87 floating-point state. The initialization software can 
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execute an FINIT or FNINIT instruction to prepare the x87 floating-point unit for use by application 
software. The FINIT and FNINIT instructions have no effect on the 64-bit media state.
Initialization software should also load the MP, EM, and NE bits in the CR0 register as appropriate for 
the operating system. The recommended settings are:
•MP=1 —Setting MP to 1 causes a device-not-available exception (#NM) to occur when the
FWAIT/WAIT instruction is executed and the task-switched bit (CR0.TS) is set to 1. This supports
operating systems that perform lazy context-switching of x87 floating-point state.
•EM=0 —Clearing EM to 0 allows the x87 floating-point unit to execute instructions rather than
causing a #NM exception (CR0.EM=1). System software sets EM to 1 only when softwareemulation of x87 instructions is desired.
•NE=1 —Setting NE to 1 causes x87 floating-point exceptions to be handled by the floating-point
exception-pending exception (#MF) handler. Clearing this bit causes the processor to externallyindicate the exception occurred, and an external device can then cause an external interrupt tooccur in response.
Refer to “CR0 Register” on page 41 for additional information on these control bits.
64-Bit Media State Initialization.  There are no special requirements placed on software to initialize 
the processor state used by 64-bit media instructions. This state is initialized completely by the processor following a RESET. System software should leave CR0.EM cleared to 0 to allow execution of the 64-bit media instructions. If CR0.EM is set to 1, attempted execution of the 64-bit media instructions causes an invalid-opcode exception (#UD).
The 64-bit media state is not modified by an INIT.Table 14-3. x87 Floating-Point State Initialization
x87 Floating-Point 
ResourceRESETFINIT/FNINIT
Instructions
FPR0–FPR7 0 Not modified
Control Word0040h 
• Round to nearest• Single precision• Unmask all exceptions037Fh• Round to nearest• Extended precision• Mask all exceptions
Status Word 0000h
Tag Word 5555h (FPR n contain zero) FFFFh (FPRn are empty)
Instruction CS 0000h
Instruction Offset 0x87 Instruction Opcode 0Data-Operand DS 0000hData-Operand Offset 0
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SSE State Initialization.  Platform firmware or system software must also prepare the processor to 
allow execution of SSE instructions. The required preparations include:
•Leaving CR0.EM cleared to 0 to allow execution of the SSE instructions. If CR0.EM is set to 1,
attempted execution of the SSE instructions except FXSA VE/FXRSTOR causes an invalid-opcode
exception (#UD). An attempt to execute either of these instructions when CR0.EM is set results ina #NM exception.
•Enabling the SSE instructions by setting CR4.OSFXSR to 1. Software cannot execute the SSEinstructions unless this bit is set. Setting this bit also indicates that system software uses theFXSA VE and FXRSTOR instructions to save and restore, respectively, the SSE state. Theseinstructions also save and restore the 64-bit media state and x87 floating-point state.
•Indicating that system software uses the SIMD floating-point exception (#XF) for handling SSEfloating-point exceptions. This is done by setting CR4.OSXMMEXCPT to 1. 
•Setting (optionally) the MXCSR mask bits to mask or unmask SSE floating-point exceptions asdesired. Because this register can be read and written by application software, it is not absolutelynecessary for system software to initialize it.
Refer to “CR4 Register” on page 46 for additional information on these CR4 control bits.
14.2.4  Model-Specific Initialization
Implementations of the AMD64 architecture can contain model-specific features and registers that are 
not initialized by the processor and therefore require system-software initialization. System software must use the CPUID instruction to determine which features are supported. Model-specific features are generally configured using model-specific registers (MSRs), which can be read and written using the RDMSR and WRMSR instructions, respectively.
Some of the model-specific features are pervasive across many processor implementations of the 
AMD64 architecture and are therefore described within this volume. These include:
•System-call extensions, which must be enabled in the EFER register before using the SYSCALL
and SYSRET instructions. See “System-Call Extension (SCE) Bit” on page 56 for information onenabling these instructions.
•Memory-typing MSRs. See “Memory-Type Range Registers (MTRRs)” on page 483 for
information on initializing and using these registers.
•The machine-check mechanism. See “Initializing the Machine-Check Mechanism” on page 318
for information on enabling and using this capability.
•Extensions to the debug mechanism. See “Software-Debug Resources” on page 390 forinformation on initializing and using these extensions.
•The performance-monitoring resources. See “Performance Monitoring Counters” on page 410 forinformation on initializing and using these resources.
Initialization of other model-specific features used by the page-translation mechanism and long mode are described throughout the remainder of this section.
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Some model-specific features are not pervasive across processor implementations and are therefore 
not described in this volume. For more information on these features and their initialization requirements, see the BIOS and Kernel Developer’s Guide (BKDG) or Processor Programming 
Reference Manual  applicable to your product.
14.3 Initializing Real Mode
A basic real-mode (real-address-mode) operating environment must be initialized so that system software can initialize the protected-mode operating environment. This real-mode environment must include:
•A real-mode IDT for vectoring interrupts and exceptions to the appropriate handlers while in real
mode. The IDT base-address value in the IDTR initialized by the processor can be used, or systemsoftware can relocate the IDT by loading a new base-address into the IDTR.
•The real-mode interrupt and exception handlers. These must be loaded before enabling externalinterrupts.
Because the processor can always accept a non-maskable interrupt (NMI), it is possible an NMI
can occur before initializing the IDT or the NMI handler. System hardware must provide amechanism for disabling NMIs to allow time for the IDT and NMI handler to be properlyinitialized. Alternatively, the IDT and NMI handler can be stored in non-volatile memory that isreferenced by the initial values loaded into the IDTR.
Maskable interrupts can be enabled by setting EFLAGS.IF after the real-mode IDT and interrupt
handlers are initialized.
•A valid stack pointer (SS:SP) to be used by the interrupt mechanism should interrupts orexceptions occur. The values of SS:SP initialized by the processor can be used.
•One or more data-segment selectors for storing the protected-mode data structures that are createdin real mode.
Once the real-mode environment is established, software can begin initializing the protected-mode environment.
14.4 Initializing Protected Mode
Protected mode must be entered before activating long mode. A minimal protected-mode environment must be established to allow long-mode initialization to take place. This environment must include the following:
•A protected-mode IDT for vectoring interrupts and exceptions to the appropriate handlers while in
protected mode. 
•The protected-mode interrupt and exception handlers referenced by the IDT. Gate descriptors foreach handler must be loaded in the IDT.
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•A GDT which contains:
- A code descriptor for the code segment that is executed in protected mode.- A read/write data segment that can be used as a protected-mode stack. This stack can be used
by the interrupt mechanism if interrupts or exceptions occur.
Software can optionally load the GDT with one or more data segment descriptors, a TSS descriptor, 
and an LDT descriptor for use by long-mode initialization software.
After the protected-mode data structures are initialized, system software must load the IDTR and 
GDTR with pointers to those data structures. Once these registers are initialized, protected mode can be enabled by setting CR0.PE to 1.
If legacy paging is used during the long-mode initialization process, the page-translation tables must

If legacy paging is used during the long-mode initialization process, the page-translation tables must 
be initialized before enabling paging. At a minimum, one page directory and one page table are required to support page translation. The CR3 register must be loaded with the starting physical address of the highest-level table supported in the page-translation hierarchy. After these structures are initialized and protected mode is enabled, paging can be enabled by setting CR0.PG to 1.
14.5 Initializing Long Mode
From protected mode, system software can initialize the data structures required by long mode and store them anywhere in the first 4 Gbytes of physical memory. These data structures can be relocated above 4 Gbytes once long mode is activated. The data structures required by long mode include the following:
•An IDT with 64-bit interrupt-gate descriptors. Long-mode interrupts are always taken in 64-bit
mode, and the 64-bit gate descriptors are used to transfer control to interrupt handlers running in64-bit mode. See “Long-Mode Interrupt Control Transfers” on page 280 for more information.
•The 64-bit mode interrupt and exception handlers to be used in 64-bit mode. Gate descriptors foreach handler must be loaded in the 64-bit IDT.
•A GDT containing segment descriptors for software running in 64-bit mode and compatibilitymode, including:
- Any LDT descriptors required by the operating system or application software.- A TSS descriptor for the single 64-bit TSS required by long mode. - Code descriptors for the code segments that are executed in long mode. The code-segment
descriptors are used to specify whether the processor is operating in 64-bit mode or
compatibility mode. See “Code-Segment Descriptors” on page 97, “Long (L) Attribute Bit” on
page 98, and “CS Register” on page 79 for more information.
- Data-segment descriptors for software running in compatibility mode. The DS, ES, and SS
segments are ignored in 64-bit mode. See “Data-Segment Descriptors” on page 98 for more
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- FS and GS data-segment descriptors for 64-bit mode, if required by the operating system. If
these segments are used in 64-bit mode, system software can also initialize the full 64-bit base
addresses using the WRMSR instruction. See “FS and GS Registers in 64-Bit Mode” onpage 80 for more information.
The existing protected-mode GDT can be used to hold the long-mode descriptors described above.
•A single 64-bit TSS for holding the privilege-level 0, 1, and 2 stack pointers, the interrupt-stack-table pointers, and the I/O-redirection-bitmap base address (if required). This is the only TSSrequired, because hardware task-switching is not supported in long mode. See “64-Bit Task StateSegment” on page 375 for more information.
•The 4-level page-translation tables required by long mode. Long mode also requires the use ofphysical-address extensions (PAE) to support physical-address sizes greater than 32 bits. See“Long-Mode Page Translation” on page 139 for more information.
If paging is enabled during the initialization process, it must be disabled before enabling long mode. 
After the long-mode data structures are initialized, and paging is disabled, software can enable and activate long mode. 
14.6 Enabling and Activating Long Mode
Long mode is enabled  by setting the long-mode enable control bit (EFER.LME) to 1. However, long 
mode is not activated  until software also enables paging. When software enables paging while long 
mode is enabled, the processor activates long mode, which the processor indicates by setting the long-mode-active status bit (EFER.LMA) to 1. The processor behaves as a 32-bit x86 processor in all respects until long mode is activated, even if long mode is enabled. None of the new 64-bit data sizes, addressing, or system aspects available in long mode can be used until EFER.LMA=1.
Table 14 -4 shows the control-bit settings for enabling and activating the various operating modes of 
the AMD64 architecture. The default address and data sizes are shown for each mode. For the methods 
of overriding these default address and data sizes, see “Instruction Prefixes” in V olume 1.
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Long mode uses two code-segment-descriptor bits, CS.L and CS.D, to control the operating 
submodes. If long mode is active, CS.L = 1, and CS.D = 0, the processor is running in 64-bit mode, as shown in Table 14 -4 on page 489. With this encoding (CS.L=1, CS.D=0), default operand size is 32 
bits and default address size is 64 bits. Using instruction prefixes, the default operand size can be overridden to 64 bits or 16 bits, and the default address size can be overridden to 32 bits. 
The final encoding of CS.L and CS.D in long mode (CS.L=1, CS.D=1) is reserved for future use. When long mode is active and CS.L is cleared to 0, the processor is in compatibility mode, as shown in 
Table 14 -4 on page 489. In compatibility mode, CS.D controls default operand and address sizes 
exactly as it does in the legacy x86 architecture. Setting CS.D to 1 specifies default operand and address sizes as 32 bits. Clearing CS.D to 0 specifies default operand and address sizes as 16 bits. 
14.6.1  Activating Long Mode
Switching the processor to long mode requires several steps. In general, the sequence involves 
disabling paging (CR0.PG=0), enabling physical-address extensions (CR4.PAE=1), loading CR3, enabling long mode (EFER.LME=1), and finally enabling paging (CR0.PG=1). 
Specifically, software must follow this sequence to activate long mode:
1. If starting from page-enabled protected mode, disable paging by clearing CR0.PG to 0. This
requires that the MOV CR0 instruction used to disable paging be located in an identity-mapped
page (virtual address equals physical address).Table 14-4. Processor Operating Modes
ModeEncoding
Default 
Address Size 
(bits)2Default
Data 
Size
(bits)2EFER.LMA1
CS.L
CS.D
Long Mode64-Bit
Mode11 0 64 32
CompatibilityMode01 32 32
0 16 16
Legacy Mode 0 x1 32 32
0 16 16
Note:
1. EFER.LMA is set by the processor when software sets EFER.LME and CR0.PG according
to the sequence described in “Activating Long Mode” on page 489. 
2. See “Instruction Prefixes” in Volume 1 for overrides to default sizes. 
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2. In any order:
- Enable physical-address extensions by setting CR4.PAE to 1. Long mode requires the use of
physical-address extensions (PAE) in order to support physical-address sizes greater than 32
bits. Physical-address extensions must be enabled before enabling paging.
- Load CR3 with the physical base-address of the level-4 page-map-table (PML4) or level-5
page-map-table (PML5). See “Long-Mode Page Translation” on page 139 for details oncreating the 4-level or 5-level page translation tables required by long mode.
- Enable long mode by setting EFER.LME to 1.
3. Enable paging by setting CR0.PG to 1. This causes the processor to set the EFER.LMA bit to 1.
The instruction following the MOV CR0 that enables paging must be a branch, and both the MOVCR0 and the following branch instruction must be located in an identity-mapped page.
14.6.2  Consistency Checks
The processor performs long-mode consistency checks whenever software attempts to modify any of 
the control bits directly involved in activating long mode (EFER.LME, CR0.PG, and CR4.PAE). A general-protection exception (#GP) occurs when a consistency check fails. Long-mode consistency checks ensure that the processor does not enter an undefined mode or state that results in unpredictable behavior.
Long-mode consistency checks cause a general-protection exception (#GP) to occur if:
•An attempt is made to enable or disable long mode while paging is enabled.
•Long mode is enabled, and an attempt is made to enable paging before enabling physical-address
extensions (PAE).
•Long mode is enabled, and an attempt is made to enable paging while CS.L=1.
•Long mode is active and an attempt is made to disable physical-address extensions (PAE).
Table 14 -5 summarizes the long-mode consistency checks made during control-bit transitions.
14.6.3  Updating System Descriptor Table References
Immediately after activating long mode, the system-descriptor-table registers (GDTR, LDTR, IDTR, 
TR) continue to reference legacy descriptor tables. The tables referenced by these descriptors all reside in the lower 4 Gbytes of virtual-address space. After activating long mode, 64-bit operating-system Table 14-5. Long-Mode Consistency Checks
Control Bit Transition Check
EFER.LME0 ® 1 If (CR0.PG=1) then #GP(0)
1 ® 0 If (CR0.PG=1) then #GP(0)
CR0.PG 0 ® 1If ((EFER.LME=1) & (CR4.PAE=0) then #GP(0)
If ((EFER.LME=1) & (CS.L=1)) then #GP(0)
CR4.PAE 1 ® 0 If (EFER.LMA=1) then #GP(0)
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software should use the LGDT, LLDT, LIDT, and LTR instructions to load the system descriptor-table

software should use the LGDT, LLDT, LIDT, and LTR instructions to load the system descriptor-table 
registers with references to the 64-bit versions of the descriptor tables. See “Descriptor Tables” on 
page 82 for details on descriptor tables in long mode. 
Long mode requires 64-bit interrupt-gate descriptors to be stored in the interrupt-descriptor table 
(IDT). Software must not allow exceptions or interrupts to occur between the time long mode is activated and the subsequent update of the interrupt-descriptor-table register (IDTR) that establishes a reference to the 64-bit IDT. This is because the IDTR continues to reference a 32-bit IDT immediately after long mode is activated. If an interrupt or exception occurred before updating the IDTR, a legacy 32-bit interrupt gate would be referenced and interpreted as a 64-bit interrupt gate, with unpredictable results. 
External interrupts can be disabled using the CLI instruction. Non-maskable interrupts (NMI) and 
system-management interrupts (SMI) must be disabled using external hardware. See “Long-Mode Interrupt Control Transfers” on page 280 for more information on long mode interrupts.
14.6.4  Relocating Page-Translation Tables
The long-mode page-translation tables must be located in the first 4 Gbytes of physical-address space 
before activating long mode. This is necessary because the MOV CR3 instruction used to initialize the page-map level-4 base address must be executed in legacy mode before activating long mode. Because the MOV CR3 is executed in legacy mode, only the low 32 bits of the register are written, which limits the location of the page-map level-4 translation table to the low 4 Gbytes of memory. Software can relocate the page tables anywhere in physical memory, and re-initialize the CR3 register, after long mode is activated.
14.7 Leaving Long Mode
To return from long mode to legacy protected mode with paging enabled, software must deactivate and disable long mode using the following sequence:
1. Switch to compatibility mode and place the processor at the highest privilege level (CPL=0).2. Deactivate long mode by clearing CR0.PG to 0. This causes the processor to clear the LMA bit to
0. The MOV CR0 instruction used to disable paging must be located in an identity-mapped page.
Once paging is disabled, the processor behaves as a standard 32-bit x86 processor.
3. Load CR3 with the physical base-address of the legacy page tables.
4. Disable long mode by clearing EFER.LME to 0.5. Enable legacy page-translation by setting CR0.PG to 1. The instruction following the MOV CR0
that enables paging must be a branch, and both the MOV CR0 and the following branch
instruction must be located in an identity-mapped page.
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14.8 Long-Mode Initialization Example
Following is sample code that outlines the steps required to place the processor in long mode. 
mydata  segment para 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; This generic data-segment holds pseudo-descriptors used; by the LGDT and LIDT instructions.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Establish a temporary 32-bit GDT and IDT.; pGDT32  label   fword                  ; Used by LGDT.                dw      gdt32_limit    ; GDT limit ...                dd      gdt32_base     ; and 32-bit GDT basepIDT32  label   fword                  ; Used by LIDT.                dw      idt32_limit    ; IDT limit ...                dd      idt32_base     ; and 32-bit IDT base;; Establish a 64-bit GDT and IDT (64-bit linear base-; address);pGDT64  label   tbyte                  ; Used by LGDT.                dw      gdt64_limit    ; GDT limit ...                dq      gdt64_base     ; and 64-bit GDT basepIDT64  label   tbyte                  ; Used by LIDT.                dw      idt64_limit    ; IDT limit ...                dq      idt64_base     ; and 64-bit IDT basemydata  ends ; end of data segment
code16  segment para use16 ; 16-bit code segment;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 16-bit code, real mode;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Initialize DS to point to the data segment containing; pGDT32 and PIDT32. Set up a real-mode stack pointer, SS:SP,; in case of interrupts and exceptions.;
climov ax, seg mydatamov ds, axmov ax, seg mystackmov ss, axmov sp, esp0
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;
; Use CPUID to determine if the processor supports long mode. ;
mov eax, 80000000h ; Extended-function 8000000h.cpuid                ; Is largest extended functioncmp eax, 80000000h ; any function > 80000000h?jbe no_long_mode   ; If not, no long mode.mov eax, 80000001h ; Extended-function 8000001h.cpuid                ; Now EDX = extended-features flags.bt edx, 29        ; Test if long mode is supported.jnc no_long_mode   ; Exit if not supported.
;; Load the 32-bit GDT before entering protected mode. ; This GDT must contain, at a minimum, the following ; descriptors:; 1) a CPL=0 16-bit code descriptor for this code segment.; 2) a CPL=0 32/64-bit code descriptor for the 64-bit code.; 3) a CPL=0 read/write data segment, usable as a stack ; (referenced by SS).;; Load the 32-bit IDT, in case any interrupts or exceptions; occur after entering protected mode, but before enabling; long mode).;; Initialize the GDTR and IDTR to point to the temporary ; 32-bit GDT and IDT, respectively.;
lgdt ds:[pGDT32]lidt ds:[pIDT32]
;; Enable protected mode (CR0.PE=1).;
mov eax, 000000011hmov cr0, eax
;; Execute a far jump to turn protected mode on.; code16_sel must point to the previously-established 16-bit ; code descriptor located in the GDT (for the code currently ; being executed).;
db 0eah ;Far jump...
dw offset now_in_prot;to offset...dw code16_sel ;in current code segment.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; At this point we are in 16-bit protected mode, but long; mode is still disabled.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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now_in_prot:
;; Set up the protected-mode stack pointer, SS:ESP.; Stack_sel must point to the previously-established stack; descriptor (read/write data segment), located in the GDT.; Skip setting DS/ES/FS/GS, because we are jumping right to ; 64-bit code.;
mov ax, stack_selmov ss, axmov esp, esp0
;; Enable the 64-bit page-translation-table entries by ; setting CR4.PAE=1 (this is _required_ before activating ; long mode). Paging is not enabled until after long mode ; is enabled.;
mov eax, cr4bts eax, 5mov cr4, eax
;; Create the long-mode page tables, and initialize the ; 64-bit CR3 (page-table base address) to point to the base ; of the PML4 page table. The PML4 page table must be located ; below 4 Gbytes because only 32 bits of CR3 are loaded when ; the processor is not in 64-bit mode.;
mov eax, pml4_base ; Pointer to PML4 table (<4GB).mov cr3, eax       ; Initialize CR3 with PML4 base.
;; Enable long mode (set EFER.LME=1).;
mov ecx, 0c0000080h ; EFER MSR number.rdmsr ; Read EFER.
bts eax, 8 ; Set LME=1.
wrmsr ; Write EFER.
;; Enable paging to activate long mode (set CR0.PG=1);
mov eax, cr0 ; Read CR0.
bts eax, 31 ; Set PE=1.
mov cr0, eax ; Write CR0.
;; At this point, we are in 16-bit compatibility mode; ( LMA=1, CS.L=0, CS.D=0 ).; Now, jump to the 64-bit code segment. The offset must be ; equal to the linear address of the 64-bit entry point, ; because 64-bit code is in an unsegmented address space.; The selector points to the 32/64-bit code selector in the; current GDT.;
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db 066h
db 0eahdd start64_lineardw code64_sel
code16ends ; End of the 16-bit code segment;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;   ;;;    Start of 64-bit code ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;code64  para use64start64: ; At this point, we're using 64-bit code;; Point the 64-bit RSP register to the stack’s _linear_; address. There is no need to set SS here, because the SS ; register is not used in 64-bit mode.;
mov rsp, stack0_linear
;; This LGDT is only needed if the long-mode GDT is to be; located at a linear address above 4 Gbytes.  If the long; mode GDT is located at a 32-bit linear address, putting ; 64-bit descriptors in the GDT pointed to by [pGDT32] is; just fine. pGDT64_linear is the _linear_ address of the ; 10-byte GDT pseudo-descriptor.;; The new GDT should have a valid CPL0 64-bit code segment; descriptor at the entry-point corresponding to the current; CS selector. Alternatively, a far transfer to a valid CPL0; 64-bit code segment descriptor in the new GDT must be done; before enabling interrupts.;
lgdt [pGDT64_linear]

;; Load the 64-bit IDT. This is _required_, because the 64-bit ; IDT uses 64-bit interrupt descriptors, while the 32-bit ; IDT used 32-bit interrupt descriptors. pIDT64_linear is; the _linear_ address of the 10-byte IDT pseudo-descriptor.;
lidt [pIDT64_linear]
;; Set the current TSS. tss_sel should point to a 64-bit TSS; descriptor in the current GDT. The TSS is used for ; inner-level stack pointers and the IO bit-map.;
mov ax, tss_selltr ax
;; Set the current LDT. ldt_sel should point to a 64-bit LDT; descriptor in the current GDT.
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;
mov ax, ldt_sel
lldt ax
;; Using fs: and gs: prefixes on memory accesses still uses ; the 32-bit fs.base and gs.base.  Reload these 2 registers ; before using the fs: and gs: prefixes. FS and GS can be ; loaded from the GDT using a normal “mov fs,foo” type ; instructions, which loads a 32-bit base into FS or GS.; Alternatively, use WRMSR to assign 64-bit base values to; MSR_FS_base or MSR_GS_base.;
mov ecx, MSR_FS_basemov eax, FsbaseLowmov edx, FsbaseHiwrmsr
;; Reload CR3 if long-mode page tables are to be located above ; 4 Gbytes. Because the original CR3 load was done in 32-bit ; legacy mode, it could only load 32 bits into CR3. Thus, the; current page tables are located in the lower 4 Gbytes of ; physical memory. This MOV to CR3 is only needed if the; actual long-mode page tables should be located at a linear; address above 4 Gbytes.; 
mov rax, final_pml4_base  ; Point to PML4mov cr3, rax              ; Load 64-bit CR3
;; Enable interrupts.;
sti           ; Enabled INTR
<insert 64-bit code here>
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15 Secure Virtual Machine
The AMD Virtualization™ (AMD-V™) architecture is designed to support enterprise-class server 
virtualization software technology and facilitate virtualization development and deployment on any 
type of system, through the Secure Virtual Machine (SVM) extension. An SVM-enabled virtual machine architecture provides hardware resources that allow a single physical machine to run multiple operating systems efficiently, while maintaining secure, hardware-enforced isolation.
15.1 The Virtual Machine Monitor
A virtual machine monitor (VMM), also known as a hypervisor , consists of software that controls the 
execution of multiple guest  operating systems on a single physical machine. The VMM provides each 
guest the appearance of full control over a complete computer system (memory, CPU, and all peripheral devices). The use of the term host refers to the execution context of the VMM. World switch  
refers to the operation of switching between the host and guest. A guest may have one or more virtual CPUs (vCPUs) managed by the guest OS, just as on a non-virtualized system, and a VMM may run any mix of vCPUs from the same or different guests on different logical processors simultaneously with no hardware-imposed constraints.
Fundamentally, VMMs work by intercepting  and emulating in a safe manner sensitive operations in 
the guest (such as changing the page tables, which could give a guest access to memory it is not 
allowed to access, or accessing peripheral devices that are shared among multiple guests). The AMD SVM architecture provides hardware assists to improve performance and facilitate implementation of 
virtualization.
15.2 SVM Hardware Overview
SVM processor support provides a set of hardware extensions designed to enable economical and efficient implementation of virtual machine systems. Generally speaking, hardware support falls into two complementary categories: virtualization  support and security support.
15.2.1  Virtualization Support
The AMD virtual machine architecture is designed to provide:
•A guest/host tagged TLB to reduce virtualization overhead
•External (DMA) access protection for memory
•Assists for interrupt handling, virtual interrupt support, and enhanced pause filter
•The ability to intercept selected instructions or events in the guest
•Mechanisms for fast world switch between VMM and guest
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15.2.2  Guest Mode
This new processor mode is entered through the VMRUN instruction. When in guest mode, the 
behavior of some x86 instructions changes to facilitate virtualization.
The CPUID function numbers 4000_0000h–4000_00FFh have been reserved for software use. 
Hypervisors can use these function numbers to provide an interface to pass information from the hypervisor to the guest. This is similar to extracting information about a physical CPU by using CPUID. Hypervisors use the CPUID Fn 400000[FF:00] bit to denote a virtual platform.
Feature bit CPUID Fn0000_0001_ECX[31] has been reserved for use by hypervisors to indicate the 
presence of a hypervisor. Hypervisors set this bit to 1 and physical CPU's set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine.
15.2.3  External Access Protection
Guests may be granted direct access to selected I/O devices. Hardware support is designed to prevent 
devices owned by one guest from accessing memory owned by another guest (or the VMM).
15.2.4  Interrupt Support
To facilitate efficient virtualization of interrupts, the following support is provided under control of 
VMCB flags:
Intercepting physical interrupt delivery.  The VMM can request that physical interrupts cause a 
running guest to exit, allowing the VMM to process the interrupt.
Virtual interrupts.  The VMM can inject virtual interrupts into the guest. Under control of the VMM, 
a virtual copy of the EFLAGS.IF interrupt mask bit, and a virtual copy of the APIC's task priority register are used transparently by the guest instead of the physical resources.
Sharing a physical APIC.  SVM allows multiple guests to share a physical APIC with isolation of 
each guest's manipulation of APIC state from the other guests' views of their own APIC state, so that no guest can interfere with delivery of interrupts to another guest.
Direct interrupt delivery.  On models that support it, the Advanced Virtual Interrupt Controller 
(A VIC) extension virtualizes the APIC's interrupt delivery functions. This provides for delivery of device or inter-processor interrupts directly to a target vCPU or vCPUs, which avoids the overhead of having the VMM determine interrupt routing and speeds up interrupt delivery. (see Section 15.29).
15.2.5  Restartable Instructions
SVM is designed to safely restart, with the exception of task switches, any intercepted instruction 
(either atomic or idempotent) after the intercept.
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15.2.6  Security Support
To further support secure initialization and execution, SVM provides additional system support 
through a variety of extensions. 
Attestation.  The SKINIT instruction and associated system support (the Trusted Platform Module, or 
TPM) allow for verifiable startup of trusted software (such as a hypervisor, or a native operating system), based on secure hash comparison. (Section 15.27).
Encrypted memory. On models that support it, the Secure Encrypted Virtualization (SEV) and SEV 
Encrypted State (SEV-ES) extensions guard against inspection of guest memory and (for SEV-ES) guest register state by malicious hypervisor code, memory bus tracing or memory device removal through encryption of guest memory and register contents (Section 15.34 and Section 15.35).
Secure Nested Paging. On models that support it, the SEV-SNP extension provides additional 
protection for guest memory against malicious manipulation of address translation mechanisms by 
hypervisor code. (Section 15.36).
15.3 SVM Processor and Platform Extensions
SVM hardware extensions can be grouped into the following categories:
•State switch—VMRUN, VMSA VE, VMLOAD instructions, global interrupt flag (GIF), and
instructions to manipulate the latter (STGI, CLGI). (Section 15.5, Section 15.5.2, Section 15.17)
•Intercepts—allow the VMM to intercept sensitive operations in the guest. (Section 15.7 throughSection 15.14)
•Interrupt and APIC assists—physical interrupt intercepts, virtual interrupt support, APIC.TPRvirtualization. (Section 15.17 and Section 15.21)
•SMM intercepts and assists (Section 15.22)
•External (DMA) access protection (Section 15.24)
•Nested paging support for two levels of address translation. (Section 15.25)
•Security—SKINIT instruction. (Section 15.27)
15.4 Enabling SVM
The VMRUN, VMLOAD, VMSA VE, CLGI, VMMCALL, and INVLPGA instructions can be used when the EFER.SVME is set to 1; otherwise, these instructions generate a #UD exception. The SKINIT and STGI instructions can be used when either the EFER.SVME bit is set to 1 or the feature flag CPUID Fn8000_0001_ECX[SKINIT] is set to 1; otherwise, these instructions generate a #UD exception.
Before enabling SVM, software should detect whether SVM can be enabled using the following 
algorithm: 
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if (CPUID Fn8000_0001_ECX[SVM] == 0)
  return SVM_NOT_AVAIL;
if (VM_CR.SVMDIS == 0)
  return SVM_ALLOWED;
if (CPUID Fn8000_000A_EDX[SVML]==0)

  return SVM_DISABLED_AT_BIOS_NOT_UNLOCKABLE  // the user must change a platform firmware setting to enable SVMelse return SVM_DISABLED_WITH_KEY;  // SVMLock may be unlockable; consult platform firmware or TPM to obtain the key.
For more information on using the CPUID instruction to obtain processor capability information, see 
15.5 VMRUN Instruction
The VMRUN instruction is the cornerstone of SVM. VMRUN takes, as a single argument, the physical address of a 4KB-aligned page, the virtual machine control block  (VMCB), which describes a 
virtual machine (guest) to be executed. The VMCB contains:
•a list of instructions or events in the guest (e.g., write to CR3) to intercept,
•various control bits that specify the execution environment of the guest or that indicate special
actions to be taken before running guest code, and
•guest processor state (such as control registers, etc.).
Note that VMRUN is not supported inside the SMM handler and the behavior is undefined.
15.5.1  Basic Operation
The VMRUN instruction has an implicit addressing mode of [rAX]. Software must load RAX (EAX 
in 32-bit mode) with the physical address of the VMCB, a 4-Kbyte-aligned page that describes a virtual machine to be executed. The portion of RAX used in forming the address is determined by the current effective address size.
The VMCB is accessed by physical address and should be mapped as writeback (WB) memory.VMRUN is available only at CPL 0. A #GP(0) exception is raised if the CPL is greater than 0. 
Furthermore, the processor must be in protected mode and EFER.SVME must be set to 1, otherwise, a #UD exception is raised.
The VMRUN instruction saves some host processor state information in the host state-save area in 
main memory at the physical address specified in the VM_HSA VE_PA MSR; it then loads corresponding guest state from the VMCB state-save area. VMRUN also reads additional control bits from the VMCB that allow the VMM to flush the guest TLB, inject virtual interrupts into the guest, etc.
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The VMRUN instruction then checks the guest state just loaded. If an illegal state has been loaded, the 
processor exits back to the host (Section 15.6).
Otherwise, the processor now runs the guest code until an intercept event occurs, at which point the 
processor suspends guest execution and resumes host execution at the instruction following the VMRUN. This is called a #VMEXIT and is described in detail in (Section 15.6). 
VMRUN saves or restores a minimal amount of state information to allow the VMM to resume execution after a guest has exited. This allows the VMM to handle simple intercept conditions quickly. If additional guest state information must be saved or restored (e.g., to handle more complex intercepts or to switch to a different guest), the VMM must use the VMLOAD and VMSA VE instructions to handle the additional guest state (Section 15.5.2). 
Saving Host State.  To ensure that the host can resume operation after #VMEXIT, VMRUN saves at 
least the following host state information:
•CS.SEL, NEXT_RIP—The CS selector and rIP of the instruction following the VMRUN. On
#VMEXIT the host resumes running at this address.
•RFLAGS, RAX—Host processor mode and the register used by VMRUN to address the VMCB.
•SS.SEL, RSP—Stack pointer for host.
•CR0, CR3, CR4, EFER—Paging/operating mode for host.
•IDTR, GDTR—The pseudo-descriptors. VMRUN does not save or restore the host LDTR.
•ES.SEL and DS.SEL.
Processor implementations may store only part or none of host state in the memory area pointed to by VM_HSA VE_PA MSR and may store some or all host state in hidden on-chip memory. Different implementations may choose to save the hidden parts of the host’s segment registers as well as the selectors. For these reasons, software must not rely on the format or contents of the host state save area, nor attempt to change host state by modifying the contents of the host save area.
Loading Guest State.  After saving host state, VMRUN loads the following guest state from the 
VMCB:
•CS, rIP—Guest begins execution at this address. The hidden state of the CS segment register is
also loaded from the VMCB.
•RFLAGS, RAX.
•SS, RSP—Includes the hidden state of the SS segment register.
•CR0, CR2, CR3, CR4, EFER—Guest paging mode. Writing paging-related control registers withVMRUN does not flush the TLB since address spaces are switched. (Section 15.16.)
•INTERRUPT_SHADOW—This flag indicates whether the guest is currently in an interruptlockout shadow; (Section 15.21.5).
•IDTR, GDTR.
•ES and DS—Includes the hidden state of the segment registers.
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•DR6 and DR7—The guest’s breakpoint state.
•V_TPR—The guest’s virtual TPR.
•V_IRQ—The flag indicating whether a virtual interrupt is pending in the guest.
•CPL—If the guest is in real mode, the CPL is forced to 0; if the guest is in v86 mode, the CPL is
forced to 3. Otherwise, the CPL saved in the VMCB is used.
The processor checks the loaded guest state for consistency. If a consistency check fails while loading guest state, the processor performs a #VMEXIT. For additional information, see “Canonicalization and Consistency Checks” on page 503.
If the guest is in PAE paging mode according to the registers just loaded and nested paging is not 
enabled, the processor will also read the four PDPEs pointed to by the newly loaded CR3 value; setting any reserved bits in the PDPEs also causes a #VMEXIT.
It is possible for the VMRUN instruction to load a guest rIP that is outside the limit of the guest code 
segment or that is non-canonical (if running in long mode). If this occurs, a #GP fault is delivered inside the guest; the rIP falling outside the limit of the guest code segment is not considered illegal guest state.
After all guest state is loaded, and intercepts and other control bits are set up, the processor reenables 
interrupts by setting GIF to 1. It is assumed that VMM software cleared GIF some time before executing the VMRUN instruction, to ensure an atomic state switch.
Some processor models allow the VMM to designate certain guest VMCB fields as “clean,” meaning 
that they haven't been modified relative to the current state of hardware. This allows the hardware to optimize execution of VMRUN. See Section 15.15 for details on which fields may be affected by this. The descriptions below assume all fields are loaded.
Control Bits.  Besides loading guest state, the VMRUN instruction reads various control fields from 
the VMCB; most of these fields are not written back to the VMCB on #VMEXIT, since they cannot change during guest execution:
•TSC_OFFSET—an offset to add when the guest reads the TSC (time stamp counter). Guest writes
to the TSC can be intercepted and emulated by changing the offset (without writing the physicalTSC). This offset is cleared when the guest exits back to the host.
•V_INTR_PRIO, V_INTR_VECTOR, V_IGN_TPR—fields used to describe a virtual interrupt forthe guest (see “Injecting Virtual (INTR) Interrupts” on page 533).
•V_INTR_MASKING—controls whether masking of interrupts (in EFLAGS.IF and TPR) is to bevirtualized (Section 15.21).
•The address space ID (ASID) to use while running the guest.
•A field to control flushing of the TLB during a VMRUN (see Section 15.16).
•The intercept vectors describing the active intercepts for the guest. On exit from the guest, theinternal intercept registers are cleared so no host operations will be intercepted.
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The maximum ASID value supported by a processor is implementation specific. The value returned in 
EBX after executing CPUID Fn8000_000A is the number of ASIDs supported by the processor.
Segment State in the VMCB.  The segment registers are stored in the VMCB in a format similar to 
that for SMM: both base and limit are fully expanded; segment attributes are stored as 12-bit values formed by the concatenation of bits 55:52 and 47:40 from the original 64-bit (in-memory) segment descriptors; the descriptor “P” bit is used to signal NULL segments (P=0) where permissible and/or relevant. The loading of segment attributes from the VMCB (which may have been overwritten by software) may result in attribute bit values that are otherwise not allowed. However, only some of the attribute bits are actually observed by hardware, depending on the segment register in question:
•CS—D, L, P, and R. 
•SS—B, P, E, W, and Code/Data
•DS, ES, FS, GS —D, P, DPL, E, W, and Code/Data.
•LDTR—P, S, and Type (LDT) 
•TR—P, S, and Type (32- or 16-bit TSS) 
NOTE: For the Stack Segment attributes, P is observed in legacy and compatibility mode. In 64-bit 
mode, P is ignored because all stack segments are treated as present.

The VMM should follow these rules when storing segment attributes into the VMCB:
•For NULL segments, set all attribute bits to zero; otherwise, write the concatenation of bits 55:52
and 47:40 from the original 64-bit (in-memory) segment descriptors.
•The processor reads the current privilege level from the CPL field in the VMCB. The CS.DPL willmatch the CPL field.
•When in virtual x86 or real mode, the processor ignores the CPL field in the VMCB and forces thevalues of 3 and 0, respectively.
When examining segment attributes after a #VMEXIT:
•Test the Present (P) bit to check whether a segment is NULL; note that CS and TR never contain
NULL segments and so their P bit is ignored;
•Retrieve the CPL from the CPL field in the VMCB, not from any segment DPL.
Canonicalization and Consistency Checks.  The VMRUN instruction performs consistency 
checks on guest state and #VMEXIT performs the appropriate subset of these consistency checks on host state. Illegal guest state combinations cause a #VMEXIT with error code VMEXIT_INV ALID. The following conditions are considered illegal state combinations (note that some checks may be subject to VMCB Clean field settings, see below):
•EFER.SVME is zero.
•CR0.CD is zero and CR0.NW is set.
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•CR0[63:32] are not zero.
•Any MBZ bit of CR3 is set.
•Any MBZ bit of CR4 is set.
•DR6[63:32] are not zero.
•DR7[63:32] are not zero.
•Any MBZ bit of EFER is set.
•EFER.LMA or EFER.LME is non-zero and this processor does not support long mode.
•EFER.LME and CR0.PG are both set and CR4.PAE is zero.
•EFER.LME and CR0.PG are both non-zero and CR0.PE is zero.
•EFER.LME, CR0.PG, CR4.PAE, CS.L, and CS.D are all non-zero.
•The VMRUN intercept bit is clear.
•The MSR or IOIO intercept tables extend to a physical address that is greater than or equal to the
maximum supported physical address.
•Illegal event injection (Section 15.20).
•ASID is equal to zero.
•Any reserved bit is set in S_CET
•CR4.CET=1 when CR0.WP=0
•CR4.CET=1 and U_CET.SS=1 when EFLAGS.VM=1
•Any reserved bit set in U_CET (SEV_ES only):
- VMRUN results in VMEXIT(INV ALID)- VMEXIT forces reserved bits to 0
VMRUN can load a guest value of CR0 with PE = 0 but PG = 1, a combination that is otherwise illegal 
(see Section 15.19).
In addition to consistency checks, VMRUN and #VMEXIT canonicalize (i.e., sign-extend to bit 63): 
•All base addresses in the segment registers that have been loaded.
•SSP
•ISST_ADDR
•PL0_SSP, PL1_SSP, PL2_SSP, PL3_SSP
VMCB Clean field behavior: On processor models that support designation of clean fields, the final 
merged hardware state is used for consistency checks. This may include state from fields marked as 
clean, if the processor chooses to ignore the indication.
VMRUN and TF/RF Bits in EFLAGS.  When considering interactions of VMRUN with the TF and 
RF bits in EFLAGS, one must distinguish between the behavior of host as opposed to that of the guest.
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From the host point of view, VMRUN acts like a single instruction, even though an arbitrary number 
of guest instructions may execute before a #VMEXIT effectively completes the VMRUN. As a single host instruction, VMRUN interacts with EFLAGS.RF and EFLAGS.TF like ordinary instructions. EFLAGS.RF suppresses any potential instruction breakpoint match on the VMRUN, and EFLAGS.TF causes a #DB trap after the VMRUN completes on the host side (i.e., after the #VMEXIT from the guest). As with any normal instruction, completion of the VMRUN instruction clears the host EFLAGS.RF bit. 
The value of EFLAGS.RF from the VMCB affects the first guest instruction. When VMRUN loads a 
guest value of 1 for EFLAGS.RF, that value takes effect and suppresses any potential (guest) instruction breakpoint on the first guest instruction. When VMRUN loads a guest value of 1 in EFLAGS.TF, that value does not cause a trace trap between the VMRUN and the first guest 
instruction, but rather after  completion of the first guest instruction.
Host values of EFLAGS have no effect on the guest and guest values of EFLAGS have no effect on the host.
See also Section 15.7.1 regarding the value of EFLAGS.RF saved on #VMEXIT.
15.5.2  VMSAVE and VMLOAD Instructions
These instructions transfer additional guest register context, including hidden context that is not 
otherwise accessible, between the processor and a guest's VMCB for a more complete context switch than VMRUN and #VMEXIT perform. The system physical address of the VMCB is specified in rAX. When these operations are needed, VMLOAD would be executed as desired prior to executing a VMRUN, and VMSA VE at any desired point after a #VMEXIT.
The VMSA VE and VMLOAD instructions take the physical address of a VMCB in rAX. These 
instructions complement the state save/restore abilities of VMRUN instruction and #VMEXIT. They provide access to hidden processor state that software cannot otherwise access, as well as additional privileged state.
These instructions handle the following register state:•      FS, GS, TR, LDTR (including all hidden state) •      KernelGsBase •      STAR, LSTAR, CSTAR, SFMASK •      SYSENTER_CS, SYSENTER_ESP, SYSENTER_EIPLike VMRUN, these instructions are only available at CPL0 (otherwise causing a #GP(0) exception) 
and are only valid in protected mode with SVM enabled via EFER.SVME (otherwise causing a #UD exception).
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15.6 #VMEXIT
When an intercept triggers, the processor performs a #VMEXIT (i.e., an exit from the guest to the host 
context).
On #VMEXIT, the processor:
•Disables interrupts by clearing the GIF, so that after the #VMEXIT, VMM software can complete
the state switch atomically.
•Writes back to the VMCB the current guest state—the same subset of processor state as is loadedby the VMRUN instruction, including the V_IRQ, V_TPR, and the INTERRUPT_SHADOW bits.
•Saves the reason for exiting the guest in the VMCB’s EXITCODE field; additional informationmay be saved in the EXITINFO1 or EXITINFO2 fields, depending on the intercept. Note that thecontents of the EXITINFO1 and EXITINFO2 fields are undefined for intercepts where their use isnot indicated.
•Clears all intercepts.
•Resets the current ASID register to zero (host ASID).
•Clears the V_IRQ and V_INTR_MASKING bits inside the processor.
•Clears the TSC_OFFSET inside the processor.
•Reloads the host state previously saved by the VMRUN instruction. The processor reloads thehost’s CS, SS, DS, and ES segment registers and, if required, re-reads the descriptors from thehost’s segment descriptor tables, depending on the implementation. The segment descriptor tablesmust be mapped as present and writable by the host's page tables. Software should keep the host’ssegment descriptor tables consistent with the segment registers when executing VMRUNinstructions. Immediately after #VMEXIT, the processor still contains the guest value for LDTR.So for CS, SS, DS, and ES, the VMM must only use segment descriptors from the global descriptortable. (The VMSA VE instruction can be used for a more complete context switch, allowing theVMM to then load LDTR and other registers not saved by #VMEXIT with desired values; seeSection 15.5.2 for details.) Any exception encountered while reloading the host segments causes ashutdown.
•If the host is in PAE mode, the processor reloads the host's PDPEs from the page table indicated bythe host's CR3. If the PDPEs contain illegal state, the processor causes a shutdown.
•Forces CR0.PE = 1, RFLAGS.VM = 0.
•Sets the host CPL to zero.
•Disables all breakpoints in the host DR7 register.
•Checks the reloaded host state for consistency; any error causes the processor to shutdown. If thehost’s rIP reloaded by #VMEXIT is outside the limit of the host’s code segment or non-canonical(in the case of long mode), a #GP fault is delivered inside the host. 
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15.7 Intercept Operation
Various instructions and events (such as exceptions) in the guest can be intercepted by means of 
control bits in the VMCB “Layout of VMCB” on page 730. The two primary classes of intercepts supported by SVM are instruction and exception intercepts.
Exception intercepts.  Exception intercepts are checked when normal instruction processing must 
raise an exception before resolving possible double-fault conditions and before attempting delivery of the exception (which includes pushing an exception frame, accessing the IDT, etc.).
For some exceptions, the processor still writes certain exception-specific registers even if the 
exception is intercepted. (See the descriptions in Section 15.12 and following for details.) When an external or virtual interrupt is intercepted, the interrupt is left pending.
When an intercept occurs while the guest is in the process of delivering a non-intercepted interrupt or

When an intercept occurs while the guest is in the process of delivering a non-intercepted interrupt or 
exception using the IDT, SVM provides additional information on #VMEXIT (See Section 15.7.2).
Instruction intercepts.  These occur at well-defined points in instruction execution—before the 
results of the instruction are committed, but ordered in an intercept-specific priority relative to the instruction’s exception checks. Generally, instruction intercepts are checked after simple exceptions (such as #GP—when CPL is incorrect—or #UD) have been checked, but before exceptions related to memory accesses (such as page faults) and exceptions based on specific operand values. There are several exceptions to this guideline, e.g., the RSM instruction. Instruction breakpoints for the current instruction and pending data breakpoint traps from the previous instruction are designed to be checked before instruction intercepts.
15.7.1  State Saved on Exit
When triggered, intercepts write an EXITCODE into the VMCB identifying the cause of the intercept. 
The EXITINTINFO field signals whether the intercept occurred while the guest was attempting to deliver an interrupt or exception through the IDT; a VMM can use this information to transparently complete the delivery (Section 15.20). Some intercepts provide additional information in the EXITINFO1 and EXITINFO2 fields in the VMCB; see the individual intercept descriptions for details. 
The guest state saved in the VMCB is the processor state as of the moment the intercept triggers. In the 
x86 architecture, traps (as opposed to faults) are detected and delivered after the instruction that triggered them has completed execution. Accordingly, a trap intercept takes place after the execution of the instruction that triggered the trap in the first place. The saved guest state thus includes the effects of executing that instruction.
Example: Assume a guest instruction triggers a data breakpoint (#DB) trap which is in turn 
intercepted. The VMCB records the guest state after execution of that instruction, so that the saved 
CS:rIP points to the following instruction, and the saved DR7 includes the effects of matching the data breakpoint.
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The next sequential instruction pointer (nRIP) is saved in the guest VMCB control area at location C8h 
on all #VMEXITs that are due to instruction intercepts, as defined in Section 15.9, as well as MSR and IOIO intercepts and exceptions caused by the INT3, INTO, and BOUND instructions. For all other intercepts, nRIP is reset to zero.
The nRIP is the RIP that would be pushed on the stack if the current instruction were subject to a trap-
style debug exception, if the intercepted instruction were to cause no change in control flow. If the intercepted instruction would have caused a change in control flow, the nRIP points to the next sequential instruction rather than the target instruction.
Some exceptions write special registers even when they are intercepted; see the individual descriptions 
in Section 15.12 for details.
Support for the NRIP save on #VMEXIT is indicated by CPUID Fn8000_000A_EDX[NRIPS]. See 
Section 3.3, “Processor Feature Identification,” on page 71 for more information on using the CPUID instruction.
15.7.2  Intercepts During IDT Interrupt Delivery
It is possible for an intercept to occur while the guest is attempting to deliver an exception or interrupt 
through the IDT (e.g., #PF because the VMM has paged out the guest’s exception stack). In some cases, such an intercept can result in the loss of information necessary for transparent resumption of the guest. In the case of an external interrupt, for example, the processor will already have performed an interrupt acknowledge cycle with the PIC or APIC to obtain the interrupt type and vector, and the 
interrupt is thus no longer pending. 
To recover from such situations, all intercepts indicate (in the EXITINTINFO field in the VMCB) 
whether they occurred during exception or interrupt delivery though the IDT. This mechanism allows the VMM to complete the intercepted interrupt delivery, even when it is no longer possible to recreate the event in question.
Figure 15-1. EXITINTINFO for All Intercepts63 32 31 30 12 11 10 8 7 0
ERRORCODE V Reserved, MBZ EV TYPE VECTOR
63:32 ERRORCODE Error Code
31 V Valid
30:12 — Reserved, MBZ
11 EV Error Code Valid
10:8 TYPE Qualifies the guest exception or interrupt. Table 15 -1 shows 
possible values returned and their corresponding interrupt or 
exception types. Values not indicated are unused and reserved.
7:0 VECTOR 8-bit IDT vector of the interrupt or exception.
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Despite the instruction name, the events raised by the INT1 (also known as ICEBP), INT3 and INTO 
instructions (opcodes F1h, CCh and CEh) are considered exceptions for the purposes of EXITINTINFO, not software interrupts. Only events raised by the INT n instruction (opcode CDh) are 
considered software interrupts.
•Error Code Valid—Bit 11. Set to 1 if the guest exception would have pushed an error code;
otherwise cleared to zero.
•Valid—Bit 31. Set to 1 if the intercept occurred while the guest attempted to deliver an exceptionthrough the IDT; otherwise cleared to zero.
•Errorcode—Bits 63:32. If EV is set to 1, holds the error code that the guest exception would havepushed; otherwise is undefined.
In the case of multiple exceptions, EXITINTINFO records the aggregate information on all exceptions but the last (intercepted) one.
Example: A guest raises a #GP during delivery of which a #NP is raised (a scenario that, according to 
x86 rules, resolves to a #DF), and an intercepted #PF occurs during the attempt to deliver the #DF. 
Upon intercept of the #PF, EXITINTINFO indicates that the guest was in the process of delivering a #DF when the #PF occurred. The information about the intercepted page fault itself is encoded in the EXITCODE, EXITINFO1 and EXITINFO2 fields. If the VMM decides to repair and dismiss the #PF, it can resume guest execution by re-injecting (see Section 15.20) the fault recorded in EXITINTINFO. If the VMM decides that the #PF should be reflected back to the guest, it must combine the event in EXITINTINFO with the intercepted exception according to x86 rules. In this case, a #DF plus a #PF would result in a triple fault or shutdown.
15.7.3  EXITINTINFO Pseudo-Code
When delivering exceptions or interrupts in a guest, the processor checks for exception intercepts and 
updates the value of EXITINTINFO should an intercept occur during exception delivery. The following pseudo-code outlines how the processor delivers an event (exception or interrupt) E.
if E is an exception and is intercepted: 
    #VMEXIT(E)E = (result of combining E with any prior events)
if (result was #DF and #DF is intercepted):
    #VMEXIT(#DF)if (result was shutdown and shutdown is intercepted):Table 15-1. Guest Exception or Interrupt Types
Value Type
0 External or virtual interrupt (INTR)
2 NMI3 Exception (fault or trap)4 Software interrupt (caused by INT n instruction)
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    #VMEXIT(#shutdown)
EXITINTINFO = E // Record the event the guest is delivering.
Attempt delivery of E through the IDT
Note that this may cause secondary exceptions
Once an exception has been successfully taken in the guest:EXITINTINFO.V = 0 // Delivery succeeded; no #VMEXIT.
Dispatch to first instruction of handler
When an exception triggers an intercept, the EXITCODE, and optionally EXITINFO1 and 
EXITINFO2, fields always reflect the intercepted exception, while EXITINTINFO, if marked valid, indicates the prior exception the guest was attempting to deliver when the intercept occurred. 
15.8 Decode Assists
Decode assists are provided to allow hypervisors to decode guest instructions more efficiently. CPUID Fn8000_000A_EDX[DecodeAssists] = 1 indicates support for this feature. See Section 3.3, “Processor Feature Identification,” on page 71 for more information on using the CPUID instruction.
15.8.1  MOV CR x/DR x Intercepts
The EXITINFO1 field holds a flag indicating whether the instruction was a MOV CRx and the number 
of the GPR operand. MOV-to-CR instructions always set bit 63 and provide the GPR number, except for CR0 as specified below.
MOV-to-CR0 Special Case.  If the instruction is MOV-to-CR, the GPR number is provided; if the 
instruction is LMSW or CLTS, no additional information is provided and bit 63 is not set. Table 15-2. EXITINFO1 for MOV CR x 
Bit Offsets Field Contents
3:0 GPR number
62:4 0
63Instruction was MOV CR x—set to1 if the instruction was 
a MOV CRx instruction; cleared to 0 otherwise.
Table 15-3. EXITINFO1 for MOV DR x 
63:4 0
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MOV-from-CR0 Special Case.  If the instruction is MOV-from-CR, the GPR number is provided and

62:4 0
63:4 0
MOV-from-CR0 Special Case.  If the instruction is MOV-from-CR, the GPR number is provided and 
bit 63 is set; if the instruction is SMSW, no information is provided and bit 63 is not set.
15.8.2  INT n Intercepts
EXITINFO1 records the immediate value of the interrupt number for INT n instructions. See Table 
15-4.
15.8.3  INVLPG and INVLPGA Intercepts
For an INVLPG intercept, EXITINFO1 provides the linear address after segment base addition and 
address size masking produce the effective address size. See Table 15-5. For an INVLPGA intercept, the linear address is available directly from the guest rAX register and is not provided in EXITINFO1.
15.8.4  Nested and intercepted #PF 
In the case of a Nested Page Fault or intercepted #PF, guest instruction bytes at guest CS:RIP are 
stored into the 16-byte wide field Guest Instruction Bytes located at offset 0D0h in the VMCB. The format of this field is summarized in Table 15 -6 below. Up to 15 bytes are recorded, read from guest 
CS:RIP. If a faulting condition occurs, such as not-present page or exceeding the CS limit, then the Guest Instruction Bytes field records as many bytes as could be fetched. The number of bytes fetched is put into the first byte of this field. Zero indicates that no bytes were fetched. The default number of bytes is always 15. Fewer bytes are returned only if a fault occurs while fetching. 
This field is filled in only during data page faults. Instruction-fetch page faults provide no additional 
All other intercepts clear bits 0:7 in this field to zero (to indicate an invalid condition); 
implementations may leave the other bytes untouched. Table 15-4. EXITINFO1 for INT n
7:0 Software interrupt number
63:8 0
Table 15-5. EXITINFO1 for INVLPG
63:0 Linear address
Table 15-6. Guest Instruction Bytes
3:0 Number of bytes fetched
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15.9 Instruction Intercepts
Table 15 -7 specifies the instructions that check a given intercept and, where relevant, how the 
intercept is prioritized relative to exceptions.4:7 0
127:8 Instruction bytes
Table 15-7. Instruction Intercepts
Instruction Intercept Checked By Priority
Read/Write of CR0MOV TO/FROM CR0, LMSW, 
SMSW, CLTSChecks non-memory exceptions (CPL, illegal bit combinations, etc.) before the intercept. For LMSW and SMSW, checks SVM intercepts before checking memory exceptions.
Read/Write of CR3 (excluding task switch)MOV TO/FROM CR3 (not checked by task switch operations)Checks non-memory exceptions first, then the intercept. If the intercept triggers on a write, the intercept happens before  the TLB is flushed. If PAE is 
enabled, the loading of the four PDPEs can cause a #GP; that exception is checked after  the intercept 
check, so the VMM handling a CR3 intercept cannot rely on the PDPEs being legal; it must examine them in software if necessary.
The reads and writes of CR3 that occur in VMRUN, 
#VMEXIT or task switches are not subject to this 
intercept check.
Read/Write of other CRsMOV TO/FROM CR nAll normal exception checks take precedence over the SVM intercepts.
Read/Write of Debug Registers, DR nMOV TO/FROM DR n. (Not checked 
by implicit DR6/DR7 writes.)All normal exception checks take precedence over the SVM intercepts.Table 15-6. Guest Instruction Bytes (continued)
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Selective CR0 Write 
InterceptMOV TO CR0, LMSWChecks non-memory exceptions (CPL, illegal bit combinations, etc.) before the intercept. For LMSW and SMSW, checks SVM intercepts before checking memory exceptions. 
The selective write intercept on CR0 triggers only if a 
bit other than CR0.TS or CR0.MP is being changed by the write. In particular, this means that CLTS does not check this intercept.
When both selective and non-selective CR0-write 
intercepts are active at the same time, the non-selective intercept takes priority. With respect to exceptions, the priority of this intercept is the same as the generic CR0-write intercept.
The LMSW instruction treats the selective CR0-write 
intercept as a non-selective intercept (i.e., it intercepts regardless of the value being written).
Reading or Writing IDTR, GDTR, LDTR, TRLIDT, SIDT, LGDT, SGDT, LLDT, SLDT, LTR, STRThe SVM intercept is checked after #UD and #GP exception checks, but before any memory access is performed.
RDTSC RDTSC Checks all exceptions before the SVM intercept.
RDPMC RDPMC Checks all exceptions before the SVM intercept.
PUSHF PUSHF Takes priority over any exceptions.
POPF POPF Takes priority over any exceptions.
CPUID CPUID No exceptions to check.
RSM RSM The intercept takes priority over any exceptions.
IRET IRET The intercept takes priority over any exceptions.
Software Interrupt INT nThe intercept occurs before any exceptions are checked. The CS:rIP reported on #VMEXIT are those of the intercepted INTn instruction.
Though the INT n instruction may dispatch through IDT 
vectors in the range of 0–31, those events cannot be 
intercepted by means of exception intercepts (see “Exception Intercepts” on page 518).
INVD INVD Exceptions (#GP) are checked before the intercept.Table 15-7. Instruction Intercepts (continued)
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PAUSE PAUSENo exceptions to check. 
VMRUN copies the VMCB.PauseFilterCount into an 
internal counter. Each PAUSE instruction decrements the counter, and the PAUSE intercept only occurs if the counter goes below zero while the PAUSE intercept is enabled. The VMCB.PauseFilterCount field is not written by the processor. Certain events, including SMI, can cause the internal count to be reloaded from the VMCB.
VMCB.PauseFilterCount support is indicated by 
EDX[10] as returned by CPUID extended function 8000_000A. If This feature is not supported or VMCB.PauseFilterCount = 0, then the first PAUSE instruction can be intercepted.
HLT HLTChecks all exceptions before checking for this intercept.
INVLPG INVLPG Checks all exceptions (#GP) before the intercept.
INVLPGA INVLPGA Checks all exceptions (#GP) before the intercept.
VMRUN VMRUNChecks exceptions (#GP) before the intercept.
The current implementation requires that the VMRUN
intercept always be set in the VMCB.
VMLOAD VMLOAD Checks exceptions (#GP) before the intercept.
VMSA VE VMSA VE Checks exceptions (#GP) before the intercept.
VMMCALL VMMCALLThe intercept takes priority over exceptions. VMMCALL causes #UD in the guest if it is not intercepted.
STGI STGI Checks exceptions (#GP) before the intercept.
CLGI CLGI Checks exceptions (#GP) before the intercept.
SKINIT SKINIT Checks exceptions (#GP) before the intercept.
RDTSCP RDTSCP Checks all exceptions before the SVM intercept.
ICEBP ICEBP(opcode F1h).Although the ICEBP instruction dispatches through IDT vector 1, that event is not interceptable by means of the #DB exception intercept.
WBINVD WBINVD, WBNOINVD Checks exceptions (#GP) before the intercept.
MONITOR MONITOR, MONITORX Checks all exceptions before the intercept.Table 15-7. Instruction Intercepts (continued)
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15.10 IOIO Intercepts
The VMM can intercept IOIO instructions (IN, OUT, INS, OUTS) on a port-by-port basis by means of 
the SVM I/O permissions map. 
15.10.1  I/O Permissions Map
The I/O Permissions Map (IOPM) occupies 12 Kbytes of contiguous physical memory. The map is 
structured as a linear array of 64K+3 bits (two 4-Kbyte pages, and the first three bits of a third 4-Kbyte page) and must be aligned on a 4-Kbyte boundary; the physical base address of the IOPM is specified in the IOPM_BASE_PA field in the VMCB and loaded into the processor by the VMRUN instruction. The VMRUN instruction ignores the lower 12 bits of the address specified in the VMCB. If the address of the last byte in the IOPM is greater than or equal to the maximum supported physical address, this is treated as illegal VMCB state and causes a #VMEXIT(VMEXIT_INV ALID).
Each bit in the IOPM corresponds to an 8-bit I/O port. Bit 0 in the table corresponds to I/O port 0, bit 1 
to I/O port 1 and so on. A bit set to 1 indicates that accesses to the corresponding port should be intercepted. The IOPM is accessed by physical address, and should reside in memory that is mapped as writeback (WB).MWAIT MWAIT, MWAITXChecks all exceptions before the intercept. There are 
conditional and unconditional MWAIT intercepts. The conditional MWAIT intercept is checked before the unconditional MWAIT intercept.
When both conditional and unconditional MWAIT

When both conditional and unconditional MWAIT 
intercepts are active, the conditional intercept is checked first. A hypervisor that sets both intercepts will receive the conditional MWAIT intercept exit code for a guest MWAIT instruction that would have entered a low-power state, and will receive the unconditional MWAIT intercept exit code for a guest MWAIT instruction that would not have entered the low-power state. These checks also apply to MWAITX.
XSETBV XSETBV Checks intercept before exceptions (#GP).
RDPRU RDPRU Check all exceptions before the intercept.
INVLPGB INVLPGB Intercept takes priority over all exceptions except #GP for CPL<>0.
INVLPGB_ILLEGAL INVLPGB exception casesIntercept takes priority over all exceptions except #GP for CPL<>0.
INVPCID INVPCIDIntercept takes priority over all exceptions except #GP for CPL<>0.
TLBSYNC TLBSYNC Checks exceptions (#GP) before the intercept.Table 15-7. Instruction Intercepts (continued)
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15.10.2  IN and OUT Behavior
If the IOIO_PROT intercept bit is set, the IOPM controls port access. For IN/OUT instructions that 
access more than a single byte, the permission bits for all bytes are checked; if any bit is set to 1, the I/O operation is intercepted.
Exceptions related to virtual x86 mode, IOPL, or the TSS-bitmap are checked before  the SVM 
intercept check. All other exceptions are checked after  the SVM intercept check.
I/O Intercept Information.  When an IOIO intercept triggers, the following information (describing 
the intercepted operation in order to facilitate emulation) is saved in the VMCB’s EXITINFO1 field:
Figure 15-2. EXITINFO1 for IOIO Intercept
The rIP of the instruction following  the IN/OUT is saved in EXITINFO2, so that the VMM can easily 
resume the guest after I/O emulation.
15.10.3  (REP) OUTS and INS
Bits 12:10 of the EXITINFO1 field provide the effective segment number (the default segment is DS). 
(For segment register encodings, see Table A -32, “16-Bit Register and Memory References” on 
page 478 , in AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System 
Instructions.)
INS provides the effective segment (always ES, encoded as 0).31 16 15 13 12 10 9 8 7 6 5 4 3 2 1 0
PORT Reserved SEG
A64
A32A16
SZ32
SZ16
SZ8
REPSTR
R SD
TYPE
31:16 PORT Intercepted I/O port
15-13 — Reserved
12:10 SEG Effective segment number
9 A64 64-bit address
8 A32 32-bit address
7 A16 16-bit address
6 SZ32 32-bit operand size
5 SZ16 16-bit operand size
4 SZ8 8-bit operand size
3 REP Repeated port access
2 STR String based port access (INS, OUTS)
1 — Reserved
0 TYPE Access Type  (0 = OUT instruction, 1 = IN instruction)
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On intercepted SMI-on-I/O, bits 12:10 of EXITINFO1 encode the segment. For definitions of the 
remaining bits of this field, (Section 15.13.3).
15.11 MSR Intercepts
The VMM can intercept RDMSR and WRMSR instructions by means of the SVM MSR permissions 
map (MSRPM) on a per-MSR basis.
MSR Permissions Map.  The MSR permissions bitmap consists of four separate bit vectors of 16 
Kbits (2 Kbytes) each. Each 16 Kbit vector controls guest access to a defined range of 8K MSRs. Each MSR is covered by two bits defining the guest read and write access permissions. The lsb of the two bits controls read access to the MSR and the msb controls write access. A value of 1 indicates that the operation is intercepted. The four separate bit vectors must be packed together and located in two contiguous physical pages of memory. If the MSR_PROT intercept is active, any attempt to read or write an MSR not covered by the MSRPM will automatically cause an intercept.
The following table defines the ranges of MSRs covered by the MSR permissions map. Note that the 
MSR ranges are not contiguous.
The MSRPM is accessed by physical address and should reside in memory that is mapped as 
writeback (WB). The MSRPM must be aligned on a 4KB boundary. The physical base address of the MSRPM is specified in MSRPM_BASE_PA field in the VMCB and is loaded into the processor by the VMRUN instruction. The VMRUN instruction ignores the lower 12 bits of the address specified in the VMCB, and if the address of the last byte in the table is greater than or equal to the maximum supported physical address, this is treated as illegal VMCB state and causes a #VMEXIT(VMEXIT_INV ALID).
RDMSR and WRMSR Behavior.  If the MSR_PROT bit in the VMCB’s intercept vector is clear, 
RDMSR/WRMSR instructions are not intercepted.
RDMSR and WRMSR instructions check for exceptions and intercepts in the following order:
•Exceptions common to all MSRs (e.g., #GP if not at CPL 0)
•Check SVM intercepts in the MSR permission map, if the MSR_PROT intercept is requested.
•Exceptions specific to a given MSR (including password protection, unimplemented MSRs,
reserved bits, etc.)Table 15-8. MSR Ranges Covered by MSRPM
MSRPM Byte Offset MSR Range
000h–7FFh 0000_0000h–0000_1FFFh
800h–FFFh C000_0000h–C000_1FFFh
1000h–17FFh C001_0000h–C001_1FFFh
1800h–1FFFh Reserved
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MSR Intercept Information.  On #VMEXIT, the processor indicates in the VMCB’s EXITINFO1 
whether a RDMSR (EXITINFO1 = 0) or WRMSR (EXITINFO1 = 1) was intercepted.
15.12 Exception Intercepts
When intercepting exceptions that define an error code (normally pushed onto the exception stack), 
the SVM hardware delivers that error code in the VMCB’s EXITINFO1 field; the exception vector number can be derived from the EXITCODE. The CS.SEL and rIP saved in the VMCB on an exception-intercept match those that would otherwise have been pushed onto the exception stack frame, except that when an interrupt-based instruction causes an intercept, the rIP of the instruction is stored in the VMCB, rather than the rIP of the next instruction. The interrupt-based instructions are INT3 (opcode CC), INTO, and BOUND.
Unless otherwise noted below, no special registers are written before an exception is intercepted. For 
details on guest state saved in the VMCB, see Section 15.7.1.
External interrupts and software interrupts (INT n instruction) do not check the exception intercepts, 
even when they use a vector in the range 0 to 31.Exceptions that occur during the handling of a prior exception are checked for intercepts before  being 
combined with the prior exception (e.g., into a double-fault). If the result of combining exceptions is a 
double-fault or shutdown, the processor checks whether those are intercepted before attempting delivery.
Example:  Assume that the VMM intercepts #GP and #DF exceptions, and the guest raises a (non-
intercepted) #NP, during the delivery of which it also gets a #GP (e.g., due to an illegal IDT entry)—a situation that, according to x86 semantics, results in a #DF. In this case, #VMEXIT signals an intercepted #GP, not an intercepted #DF and fills EXITINTINFO with the #NP fault. On the other 
hand, if only the #DF intercept were active in this scenario, #VMEXIT would signal an intercepted #DF.
The following subsections detail the individual intercepts.
15.12.1  #DE (Divide By Zero)
The EXITINFO1 and EXITINFO2 fields are undefined.
15.12.2  #DB (Debug)
The #DB exception can have fault-type (e.g., instruction breakpoint) or trap-type (e.g., data 
breakpoint) behavior; accordingly the intercept differs in what state is saved in the VMCB (see Section 15.7.1). In either case, however, the value saved for DR6 and DR7 matches what would be visible to a #DB exception handler (i.e., both #DB faults and traps are permitted to write DR6 and DR7 before the intercept). The EXITINFO1 and EXITINFO2 fields are undefined. 
Fault-type #DB exceptions, whether indicated in EXITCODE or EXITINTINFO, cause the CS:rIP 
saved in the VMCB to indicate the instruction that caused the #DB exception. Trap-type #DB 
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exceptions cause the VMCB’s CS:rIP to indicate the instruction following the instruction that caused 
the exception. A vector 1 exception generated by the single byte INT1 instruction (also known as ICEBP) does not trigger the #DB intercept. Software should use the dedicated ICEBP intercept to intercept ICEBP (see Section 15.9).
15.12.3  Vector 2 (Reserved)
This intercept bit is not implemented; use the NMI intercept (Section 15.13.2) instead. The effect of 
setting this bit is undefined.
15.12.4  #BP (Breakpoint)
This intercept applies to the trap raised by the single byte INT3 (opcode CCh) instruction. The 
EXITINFO1 and EXITINFO2 fields are undefined. The CS:rIP reported on #VMEXIT are those of the INT3 instruction.
15.12.5  #OF (Overflow)
This intercept applies to the trap raised by the INTO (opcode CEh) instruction. The EXITINFO1 and 
EXITINFO2 fields are undefined.
15.12.6  #BR (Bound-Range)
This intercept applies to the fault raised by the BOUND instruction. The EXITINFO1 and 
15.12.7  #UD (Invalid Opcode)
15.12.8  #NM (Device-Not-Available)
15.12.9  #DF (Double Fault)
The EXITINFO1 and EXITINFO2 fields are undefined. The rIP value saved in the VMCB is

The EXITINFO1 and EXITINFO2 fields are undefined. The rIP value saved in the VMCB is 
undefined (as is the case for the rIP value pushed on the stack for #DF exceptions). If a double fault is intercepted, the exceptions leading up to the double fault will have written any status registers normally written by those exceptions.
15.12.10  Vector 9 (Reserved)
This intercept is not implemented. The effect of setting this bit is undefined.
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15.12.11  #TS (Invalid TSS)
The EXITINFO1 and EXITINFO2 fields are undefined. The rIP value saved in the VMCB may point 
to either the instruction causing the task switch, or to the first instruction of the incoming task. See Section 15.14.1 for information on the EXITINFO1 and EXITINFO2 fields.
15.12.12  #NP (Segment Not Present)
The EXITINFO1 field contains the error code that would be pushed on the stack by a #NP exception. 
The EXITINFO2 field is undefined.
15.12.13  #SS (Stack Fault)
The EXITINFO1 field contains the error code that would be pushed on the stack by a #SS exception. 
15.12.14  #GP (General Protection)
The EXITINFO1 field contains the error code that would be pushed on the stack by a #GP exception.
15.12.15  #PF (Page Fault)
This intercept is tested before  CR2 is written by the exception. The error code saved in EXITINFO1 is 
the same as would be pushed onto the stack by a non-intercepted #PF exception in protected mode. 
The faulting address is saved in the EXITINFO2 field in the VMCB. Even when the guest is running in paged real mode, the processor will deliver the (protected-mode) page-fault error code in EXITINFO1, for the VMM to use in analyzing the intercepted #PF. The processor may provide additional instruction decode assist information. (See Section 15.8.4.)
15.12.16  #MF (X87 Floating Point)
This intercept is tested after  the floating point status word has been written, as is the case for a normal 
FP exception. The EXITINFO1 and EXITINFO2 fields are undefined.
15.12.17  #AC (Alignment Check)
The EXITINFO1 field contains the error code that would be pushed on the stack by an #AC exception. 
15.12.18  #MC (Machine Check)
The SVM intercept is checked after all #MC-specific registers have been written, but before other 
guest state is modified. When #MC is being intercepted, a machine-check exits to the VMM, whenever possible, and shuts down the processor only when this is not a reasonable option. The EXITINFO1 and EXITINFO2 fields are undefined.
Note that in some processors, if the guest VM has disabled machine check handling (CR4.MCE=0) 
then all machine check errors that occur in the guest will result in a shutdown event. However in 
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processors where CPUID Fn8000_000A_EDX[HOST_MCE_OVERRIDE] (bit 23) = 1 the VMM 
may override this behavior by setting CR4.MCE=1 in the host. In this scenario, machine check errors that occur in the guest and which can be contained by the processor will always result in a #VMEXIT(MC).
15.12.19  #XF (SIMD Floating Point)
This intercept is tested after the SIMD status word (MXCSR) has been written, as is the case for a 
normal FP exception. The EXITINFO1 and EXITINFO2 fields are undefined.
15.12.20  #SX (Security Exception)
The EXITINFO1 field contains the error code that would be pushed on the stack by a #SX exception. 
The EXITINFO2 field is undefined. 
15.12.21  #CP (Control Protection)
The EXITINFO1 field contains the error code that would be pushed on the stack by a #CP exception. 
15.13 Interrupt Intercepts
External interrupts, when intercepted, cause a #VMEXIT; the interrupt is held pending so that the interrupt can eventually be taken in the VMM. Exception intercepts do not apply to external or software interrupts, so it is not possible to intercept an interrupt by means of the exception intercepts, even if the interrupt should happen to use a vector in the range from 0 to 31.
15.13.1  INTR Intercept
This intercept affects physical, as opposed to virtual, maskable interrupts. See “Virtual Interrupt 
Intercept” on page 534 for virtualization of maskable interrupts.
15.13.2  NMI Intercept
This intercept affects non-maskable interrupts. NMI interrupts (and SMIs) may be blocked for one 
instruction following an STI.
15.13.3  SMI Intercept
This intercept affects System Management Mode Interrupts (SMIs); see “SMM Support” on page 536 
for details on SMI handling. 
When this intercept triggers, bit 0 of the EXITINFO1 field distinguishes whether the SMI was caused 
internally by I/O Trapping (bit 0 = 0), or asserted externally (bit 0 = 1).
If the SMI was asserted while the guest was executing an I/O instruction, extra information (describing 
the I/O instruction) is saved in the upper 32 bits of EXITINFO1, and the rIP of the I/O instruction is 
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saved in EXITINFO2. EXITINFO1 indicates that SMI was asserted during an I/O instruction when the 
V ALID bit is set.
If the SMI wasn't asserted during an I/O instruction, the extra EXITINFO1 and EXITINFO2 bits are 
undefined.
The SMI intercept is ignored when HWCR[SMMLOCK] is set.
Figure 15-3. EXITINFO1 for SMI Intercept
15.13.4  INIT InterceptThe INIT intercept allows the VMM to intercept the assertion of INIT while a guest is running. An 
intercepted INIT remains pending until the VMM sets GIF (see “Global Interrupt Flag, STGI and CLGI Instructions” on page 529), at which point it either takes effect or is redirected. See Section 15.21.8 for a discussion of the INIT redirection feature.63 48 47 44 43 42 41 40 39 38 37 36 35 34 33 32
PORT BRP
TF
RAZ
A64
A32A16
SZ32
SZ16
SZ8
REPSTR
V AL
TYPE
31 12 10 9 2 1 0
Reserved, RAZ SEG Reserved, RAZ
MCREDIR
SMISRC
63:48 PORT Intercepted I/O port
47:44 BRP I/O breakpoint matches
43 TF EFLAGS TF value
42 — Reserved, RAZ
41 A64 64-bit address
40 A32 32-bit address
39 A16 16-bit address
38 SZ32 32-bit operand size
37 SZ16 16-bit operand size
36 SZ8 8-bit operand size
35 REP Repeated port access
34 STR String based port access (INS, OUTS)
33 V AL Valid (SMI was detected during an I/O instruction)
32 TYPE Access Type  (0 = OUT instruction, 1 = IN instruction)
31:13 — Reserved, RAZ
12:10 SEG Effective segment number (see Section 15.9)
9:2 — Reserved, RAZ
1 MCREDIRSMI was due to a redirect machine check error (See “Inter -
action with SMI and #MC” on page 601) 
0 SMISRC SMI source (0 = internal, 1 = external)
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15.13.5  Virtual Interrupt Intercept
This intercept is taken just before a guest takes a virtual interrupt. When the intercept triggers, the 
virtual interrupt has not been taken, and remains pending in the guest's VMCB V_IRQ field. This intercept is not required for handling fixed local APIC interrupts, but may be used for emulating ExtINT interrupt delivery mode (which is not masked by the TPR), or legacy PICs in auto-EOI mode.
15.14 Miscellaneous Intercepts
The SVM architecture includes intercepts to handle task switches, processor freezes due to FERR, and shutdown operations.
15.14.1  Task Switch Intercept
Checked by—Any instruction or event that causes a task switch (e.g., JMP, CALL, exceptions, 
interrupts, software interrupts).
Priority— The intercept is checked before the task switch takes place but after  the incoming TSS and 
task gate (if one was involved) have been checked for correctness.Task switches can modify several resources that a VMM may want to protect (CR3, EFLAGS, LDT). 
However, instead of checking various intercepts (e.g., CR3 Write, LDTR Write) individually, task switches check only a single intercept bit.
On #VMEXIT, the following information is delivered in the VMCB:
•EXITINFO1[15:0] holds the segment selector identifying the incoming TSS.
•EXITINFO2[31:0] holds the error code to push in the new task, if applicable; otherwise, this field
is undefined.
•EXITINFO2[63:32] holds auxiliary information for the VMM:
- EXITINFO2[36]—Set to 1 if the task switch was caused by an IRET; else cleared to 0.- EXITINFO2[38]—Set to 1 if the task switch was caused by a far jump; else cleared to 0.- EXITINFO2[44]—Set to 1 if the task switch has an error code; else cleared to 0.- EXITINFO2[48]—The value of EFLAGS.RF that would be saved in the outgoing TSS if the 
task switch were not intercepted.
15.14.2  Ferr_Freeze Intercept
Checked when the processor freezes due to assertion of FERR (while IGNNE is deasserted, and legacy 
handling of FERR is selected in CR0.NE), i.e., while the processor is waiting to be unfrozen by an external interrupt.
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15.14.3  Shutdown Intercept
When this intercept occurs, any condition that normally causes a shutdown causes a #VMEXIT to the

When this intercept occurs, any condition that normally causes a shutdown causes a #VMEXIT to the 
VMM instead. After an intercepted shutdown, the state saved in the VMCB is undefined.
15.14.4  Pause Intercept Filtering
On processors that support Pause filtering (indicated by CPUID Fn8000_000A_EDX[PauseFilter] = 
1), the VMCB provides a 16 bit PAUSE Filter Count value. On VMRUN this value is loaded into an internal counter. Each time a PAUSE instruction is executed, this counter is decremented until it reaches zero at which time a #VMEXIT is generated if PAUSE intercept is enabled. If the PAUSE Filter Count is set to zero and PAUSE Intercept is enabled, every PAUSE instruction will cause a #VMEXIT.
In addition, some processor families support Advanced Pause Filtering (indicated by CPUID 
Fn8000_000A_EDX[PauseFilterThreshold] = 1). In this mode, a 16-bit PAUSE Filter Threshold field is added in the VMCB. The threshold value is a cycle count that is used to reset the pause counter. 
As with simple Pause filtering, VMRUN loads the PAUSE count VMCB value into an internal 
counter. Then, on each PAUSE instruction the processor checks the elapsed number of cycles since the most recent PAUSE instruction against the PAUSE Filter Threshold. If the elapsed cycle count is greater than the PAUSE Filter Threshold, then the internal pause count is reloaded from the VMCB and execution continues. If the elapsed cycle count is less than the PAUSE Filter Threshold, then the internal pause count is decremented. If the count value is less than zero and PAUSE intercept is enabled, a #VMEXIT is triggered. 
If Advanced Pause Filtering is supported and PAUSE Filter Threshold field is set to zero, the filter will 
operate in the simpler, count only mode.
15.14.5  Bus Lock Threshold
On processors that support Bus Lock Threshold (indicated by CPUID Fn8000_000A_EDX[29] 
BusLockThreshold=1), the VMCB provides a Bus Lock Threshold enable bit and an unsigned 16-bit Bus Lock Threshold count.  On VMRUN, this value is loaded into an internal count register.  Before the processor executes a bus lock in the guest, it checks the value of this register.  If the value is greater than 0, the processor executes the bus lock successfully and decrements the count.  If the value is 0, the bus lock is not executed and a #VMEXIT to the VMM is taken.  A Bus Lock Threshold #VMEXIT is reported to the VMM with VMEXIT code A5h, VMEXIT_BUSLOCK.  EXITINFO1 and EXITINFO2 are set to 0 on a VMEXIT_BUSLOCK.
On a #VMEXIT, the processor writes the current value of the Bus Lock Threshold Counter to the 
VMCB.
Section 7.3.3 on page 195 describes the conditions under which a bus lock is executed.
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The bus lock threshold #VMEXIT may occur due to a tablewalk A/D bit update if a page table 
memory type is not WB. In this case, the bus lock threshold #VMEXIT is still reported as a VMEXIT_BUSLOCK, not a Nested Page Fault.
15.15 VMCB State Caching
VMCB state caching allows the processor to cache certain guest register values in hardware between a #VMEXIT and subsequent VMRUN instructions and use the cached values to improve context-switch performance. Depending on the particular processor implementation, VMRUN loads each guest register value either from the VMCB or from the VMCB state cache, as specified by the value of the VMCB Clean field in the VMCB. Support for VMCB state caching is indicated by CPUID Fn8000_000A_EDX[VmcbClean] = 1.
The SVM architecture uses the physical address of the VMCB as a unique identifier for the guest 
virtual CPU for the purposes of deciding whether the cached copy belongs to the guest. For the purposes of VMCB state caching, the ASID is not a unique identifier for a guest virtual CPU.
15.15.1  VMCB Clean Bits
The VMCB Clean field (VMCB offset 0C0h, bits 31:0) controls which guest register values are loaded 
from the VMCB state cache on VMRUN. Each set bit in the VMCB Clean field allows the processor to load one guest register or group of registers from the hardware cache; each clear bit requires that the processor load the guest register from the VMCB. The clean bits are a hint, since any given processor implementation may ignore bits that are set to 1 on any given VMRUN, unconditionally loading the associated register value(s) from the VMCB. Clean bits that are set to zero are always honored.
This field is backward-compatible to CPUs that do not support VMCB state caching; older CPUs 
neither cache VMCB state nor read the VMCB Clean field. 
Older hypervisors that are not aware of VMCB state caching and respect the SBZ property of 
undefined VMCB fields will not enable VMCB state caching.
15.15.2  Guidelines for Clearing VMCB Clean Bits
The hypervisor must clear specific bits in the VMCB Clean field every time it explicitly modifies the 
associated guest state in the VMCB. The guest's execution can cause cached state to be updated, but the hypervisor is not responsible for setting VMCB Clean bits corresponding to any state changes caused by guest execution.
The hypervisor must clear the entire VMCB field to 0 for a guest, under the following circumstances: 
•This is the first time a particular guest is run. 
•The hypervisor executes the guest on a different CPU core than one used the last time that guest
was executed.
•The hypervisor has moved the guest's VMCB to a different physical page since the last time thatguest was executed. 
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Failure to clear the VMCB Clean bits to zero in these cases may result in undefined behavior. 
The CPU automatically treats the VMCB Clean field as zero on the current VMRUN when the 
hypervisor executes a guest that is not currently cached. The CPU compares the VMCB physical address against all cached VMCB physical addresses and treats the VMCB Clean field as zero, if no cached VMCB address matches.
SMM software (or any other agent external to the hypervisor that has access to VMCBs) that changes 
the contents of a VMCB needs to comprehend the clean bits and adjust them accordingly; otherwise the guest may not operate as intended. 
15.15.3  VMCB Clean Field
The layout of the VMCB Clean field is illustrated in Figure 15 -4 below.
Figure 15-4. Layout of VMCB Clean Field
Bits 31:12 are reserved for future implementations. For forward compatibility, if the hypervisor has 
not modified the VMCB, the hypervisor may write FFFF_FFFFh to the VMCB Clean Field to indicate that it has not changed any VMCB contents other than the fields described below as explicitly uncached. The hypervisor should write 0h to indicate that the VMCB is new or potentially inconsistent with the CPU's cached copy, as occurs when the hypervisor has allocated a new location for an existing VMCB from a list of free pages and does not track whether that page had recently been used as a 31 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
C ET 
A VIC
LBR
CR2
SEG
DT
DRx
CRx
NP
TPR
ASID
IOPM
I
31:13 — Reserved
12 CET S_CET, SSP, ISST_ADDR
11 A VIC A VIC APIC_BAR; A VIC APIC_BACKING_PAGE, A VIC 
PHYSICAL_TABLE and A VIC LOGICAL_TABLE Point -
ers
10 LBR DbgCtlMsr, br_from/to, lastint_from/to
9 CR2 CR2
8 SEG CS/DS/SS/ES Sel/Base/Limit/Attr, CPL
7 DT GDT/IDT Limit and Base
6 DRx DR6, DR7
5 CR x CR0, CR3, CR4, EFER
4 NP Nested Paging: NCR3, G_PAT
3 TPR V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_IN -
TR_MASKING, V_INTR_VECTOR (Offset 60h–67h)
2 ASID ASID
1 IOPM IOMSRPM: IOPM_BASE, MSRPM_BASE
0 IIntercepts: all the intercept vectors, TSC offset, Pause Filter Count
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VMCB for another guest. If any VMCB fields (excluding explicitly uncached fields) have been 
modified, all clean bits that are undefined (within the scope of the hypervisor) must be cleared to zero.
Bit 31 is a special bit reserved for the host that the CPU will never use for a clean bit. The following are explicitly not cached and not represented by Clean bits: 
•TLB_Control 
•Interrupt shadow 
•VMCB status fields (Exitcode, EXITINFO1, EXITINFO2, EXITINTINFO, Decode Assist, etc.) 
•Event injection 
•RFLAGS, RIP, RSP, RAX
15.16 TLB Control
TLB entries are tagged with Address Space Identifier  (ASID) bits to distinguish different guest virtual 
address spaces when shadow page tables are used, or different guest physical address spaces when 
nested page tables are used. The VMM can choose a software strategy in which it keeps multiple shadow page tables, and/or multiple nested page tables in processors that support nested paging, up-to-date; the VMM can allocate a different ASID for each shadow or nested page table. This allows 
switching to a new process in a guest under shadow paging (changing CR3 contents), or to a new guest under nested paging (changing nCR3 contents), without flushing the TLBs. (See Section 15.25 for a complete explanation of nested paging operation.)

With shadow paging, the VMM is responsible for setting up a shadow page table for each guest linear 
address space that maps it to system physical addresses. These are used as the active page tables in place of the guest OS's page tables. The VMM sets the CR3 field in the guest VMCB to point to the system physical address of the desired shadow page table. The VMM is responsible for updating the shadow page table when the guest changes its page table or paging control state, and the VMM updates the access and dirty bits of the guest page table.
The VMRUN instruction and #VMEXIT write the CR0, CR3, CR4 and EFER registers, but these 
writes do not flush the TLB. The VMM is responsible for explicitly invalidating any guest translations 
that may be affected by its actions. There are two mechanisms available for this described in the next two sections.
When running with SVM enabled, global page table entries (PTEs) are global only within an ASID, 
not across ASIDs.
Software Rule.  When the VMM changes a guest’s paging mode by changing entries in the guest’s 
VMCB, the VMM must ensure that the guest’s TLB entries are flushed from the TLB. The relevant 
VMCB state includes:
•CR0—PG, WP, CD, NW.
•CR3—Any bit.
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•CR4—PGE, PAE, PSE.
•EFER—NXE, LMA, LME.
15.16.1  TLB Flush
TLB flush operations function identically whether or not SVM is enabled (e.g., MOV-TO-CR3 flushes 
non-global mappings, whereas MOV-TO-CR4 flushes global and non-global mappings). TLB flush operations must not be assumed to affect all ASIDs. If a VMM sets the intercept bit for any guest action that would have flushed the TLB, the #VMEXIT intercept occurs and the TLB is not flushed; it is the VMM's responsibility to flush the TLB appropriately. In implementations that do not provide a way to selectively flush all translations of a single specified ASID, software may effectively flush the guest's TLB entries by allocating a new ASID for the guest and not reusing the old ASID until the entire TLB has been flushed at least once.
The TLB_CONTROL field in the VMCB provides the commands specified by the control byte 
encodings shown in Table 15-9. The first two commands are available on all processors that support SVM; support for the other commands is optional and is indicated by CPUID Fn8000_000A_EDX[FlushByAsid] = 1.
When the VMM sets the TLB_CONTROL field to 1, the VMRUN instruction flushes the TLB for all 
ASIDs, for both global and non-global pages. The VMRUN instruction reads, but does not change, the value of the TLB_CONTROL field.
A MOV-to-CR3, a task switch that changes CR3, or clearing or setting CR0.PG or bits PGE, PAE, PSE 
of CR4 affects only the TLB entries belonging to the current ASID, regardless of whether the operation occurred in host or guest mode. The current ASID is 0 when the CPU is not inside a guest context.
All TLB entries belonging to all ASIDs are flushed by SMI, RSM, MTRR modifications, IORR 
modifications, and access to other system MSRs that affect address translation.
If a hypervisor modifies a nested page table by decreasing permission levels, clearing present bits, or 
changing address translations and intends to return to the same ASID, it should use either TLB command 011b or 001b.Table 15-9. TLB Control Byte Encodings
Encoding Function Definition
00h Do not flush
01h Flush entire TLB (Should be used only on legacy hardware.)
03h Flush this guest's TLB entries
07h Flush this guest's non-global TLB entries
Note: All encodings not defined in this table are reserved.
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15.16.2  Invalidate Page, Alternate ASID
The INVLPGA instruction allows the VMM to selectively invalidate the TLB mapping for a given 
guest virtual page within a given ASID. The linear address is specified in the implicit register operand rAX; the ASID is specified in ECX. The input address is always interpreted as a guest virtual address, so INVLPGA is typically meaningful only when used with shadow page tables; it does not provide a means to invalidate a nested translation by guest physical address. 
15.17 Global Interrupt Flag, STGI and CLGI Instructions
The global interrupt flag (GIF) is a bit that controls whether interrupts and other events can be taken by the processor. The STGI and CLGI instructions set and clear, respectively, the GIF. Table 15 -10 shows 
how the value of the GIF affects how interrupts and exceptions are handled. Implementations may provide hardware support for virtualizing the GIF in nested virtualization scenarios; see Section 15.33, for details.
Table 15-10. Effect of the GIF on Interrupt Handling 
Interrupt source GIF==0 GIF ==1
Debug exception or trap, due 
to breakpoint register matchIgnored and discarded Normal operation
Debug trace trap due to EFLAGS.TFNormal operation Normal operation
RESET Normal operation Normal operation
INIT Held pending until GIF==1 Normal operation, see Table 15 -12
NMI Held pending until GIF==1 Normal operation, see Table 15 -13
External SMI Held pending until GIF==1 Normal operation, see Table 15 -14
Internal SMI (I/O Trapping) Ignored and discarded Normal operation, see Table 15 -14
INTR and vINTR Held pending until GIF==1 Normal operation
#SX (Security Exception) n/a
1 Normal operation
Machine CheckIf possible (implementation-dependent), held pending until GIF==1, otherwise shutdown. Normal operation
A20MNormal operation Normal operation
 (VM_CR.DIS_A20M controls A20 masking)
Other implementation-specific but non-architecturally-visible interrupts (STPCLK, IGNNE toggle, ECC scrub)Normal operation Normal operation
Note:
1. #SX is caused only by an INIT signal that has been “redirected” (i.e., converted to an #SX; see Section 15.28); the conversion
only happens when GIF==1, as the INIT is simply held pending otherwise.
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15.18 VMMCALL Instruction
This instruction is meant as a way for a guest to explicitly call the VMM. No CPL checks are 
performed, so the VMM can decide whether to make this instruction legal at the user-level or not.
If VMMCALL instruction is not intercepted, the instruction raises a #UD exception.
15.19 Paged Real Mode
To facilitate virtualization of real mode, the VMRUN instruction may legally load a guest CR0 value 
with PE = 0 but PG = 1. Likewise, the RSM instruction is permitted to return to paged real mode. This processor mode behaves in every way like real mode, with the exception that paging is applied. The intent is that the VMM run the guest in paged-real mode at CPL0, and with page faults intercepted. The VMM is responsible for setting up a shadow page table that maps guest physical  memory to the 
appropriate system physical addresses.
The behavior of running a guest in paged real mode without intercepting page faults to the VMM is 
15.20 Event Injection
The VMM can inject exceptions or interrupts (collectively referred to as events) into the guest by setting bits in the VMCB’s EVENTINJ field prior to executing the VMRUN instruction. The format of the field is shown in Table 15-5. The encoding matches that of the EXITINTINFO field. When an event is injected by means of this mechanism, the VMRUN instruction causes the guest to take the specified exception or interrupt unconditionally before executing the first guest instruction.
Injected events are treated in every way as though they had occurred normally in the guest (in 
particular, they are recorded in EXITINTINFO) with the following exceptions:
•Injected events are not subject to intercept checks. (Note, however, that if secondary exceptions
occur during delivery of an injected event, those exceptions are subject to exception intercepts.)
•An injected NMI does not block delivery of further NMIs.
•If the VMM attempts to inject an event that is impossible for the guest mode (e.g., a #BR exceptionwhen the guest is in 64-bit mode), the event injection will fail and no guest state instructions willbe executed; VMRUN will immediately exit with an error code of VMEXIT_INV ALID.
•Injecting an exception (TYPE = 3) with vectors 3 or 4 behaves like a trap raised by INT3 and INTOinstructions, respectively, in which case the processor checks the DPL of the IDT descriptor beforedispatching to the handler.
•Software interrupts cannot be properly injected if the processor does not support the NextRIP field.Support is indicated by CPUID Fn8000_000A_EDX[NRIPS] = 1. Hypervisor software shouldemulate the event injection of software interrupts if NextRIP is not supported. 
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•Event injection does not support injection of intercepted #DB faults that are the result of a guest
ICEBP instruction. ICEBP does not perform DPL checks, as does INT n injection. Hypervisor
software should emulate the injection of ICEBP.
Figure 15-5. EVENTINJ Field in the VMCB
The fields in EVENTINJ are as follows:

•VECTOR —Bits 7:0. The 8-bit IDT vector of the interrupt or exception. If TYPE is 2 (NMI), the
VECTOR field is ignored.
•TYPE —Bits 10:8. Qualifies the guest exception or interrupt to generate. Table 15 -11 shows
possible values and their corresponding interrupt or exception types. Values not indicated are
unused and reserved.
•EV (Error Code Valid) —Bit 11. Set to 1 if the exception should push an error code onto the stack;
clear to 0 otherwise.
•V (Valid)—Bit 31. Set to 1 if an event is to be injected into the guest; clear to 0 otherwise.
•ERRORCODE —Bits 63:32. If EV is set to 1, the error code to be pushed onto the stack, ignored
otherwise. 
VMRUN exits with VMEXIT_INV ALID error code if either:
•Reserved values of TYPE have been specified, or
•TYPE = 3 (exception) has been specified with a vector that does not correspond to an exception(this includes vector 2, which is an NMI, not an exception).
15.21 Interrupt and Local APIC Support 
SVM hardware support is designed to ensure efficient virtualization of interrupts. 63 32 31 30 12 11 10 8 7 0
ERRORCODE V Reserved, SBZ EV TYPE VECTOR
Table 15-11. Guest Exception or Interrupt Types
Value Type
2 NMI
3 Exception (fault or trap)
4 Software interrupt (INT n instruction)
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15.21.1  Physical (INTR) Interrupt Masking in EFLAGS 
To prevent the guest from blocking maskable interrupts (INTR), SVM provides a VMCB control bit, 
V_INTR_MASKING, which changes the operation of EFLAGS.IF and accesses to the TPR by means of the CR8 register. While running a guest with V_INTR_MASKING cleared to zero: 
•EFLAGS.IF controls both virtual and physical interrupts.
While running a guest with V_INTR_MASKING set to 1:•The host EFLAGS.IF at the time of the VMRUN is saved and controls physical interrupts while
the guest is running. 
•The guest value of EFLAGS.IF controls virtual interrupts only. 
15.21.2  Virtualizing APIC.TPR 
SVM provides a virtual TPR register, V_TPR, for use by the guest; its value is loaded from the VMCB 
by VMRUN and written back to the VMCB by #VMEXIT. The APIC's TPR always controls the task priority for physical interrupts, and the V_TPR always controls virtual interrupts. 
While running a guest with V_INTR_MASKING cleared to 0: 
•Writes to CR8 affect both the APIC's TPR and the V_TPR register. 
•Reads from CR8 operate as they would without SVM. 
While running a guest with V_INTR_MASKING set to 1: •Writes to CR8 affect only the V_TPR register. 
•Reads from CR8 return V_TPR. 
15.21.3  TPR Access in 32-Bit Mode
The mechanism for TPR virtualization described in Section 15.21.2 applies only to accesses that are 
performed using the CR8 register. However, in 32-bit mode, the TPR is traditionally accessible only 
by using a memory-mapped register. Typically, a VMM virtualizes such TPR accesses by not mapping the APIC page addresses in the guest. A guest access to that region then causes a #PF intercept to the VMM, which inspects the guest page tables to determine the physical address and, after recognizing the physical address as belonging to the APIC, finally invokes software emulation code.
To improve the efficiency of TPR accesses in 32-bit mode, SVM makes CR8 available to 32-bit code 
by means of an alternate encoding of MOV TO/FROM CR8 (namely, MOV TO/FROM CR0 with a LOCK prefix). To achieve better performance, 32-bit guests should be modified to use this access method, instead of the memory-mapped TPR. (For details, see “MOV CRn” on page 377 of the AMD64 Programmer’s Reference Volume 3: General Purpose and System Instructions, order# 24594.)
The alternate encodings of the MOV TO/FROM CR8 instructions are available even if SVM is 
disabled in EFER.SVME. They are available in both 64-bit and 32-bit mode.
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15.21.4  Injecting Virtual (INTR) Interrupts
Virtual Interrupts allow the host to pass an interrupt (#INTR) to a guest. While inside a guest, the 
virtual interrupt follows the same rules that a real interrupt follows (virtual #INTR is not taken until EFLAGS.IF is 1, the guest's TPR has enabled interrupts at the same priority as that of the pending virtual interrupt).
SVM provides an efficient mechanism by which the VMM can inject virtual interrupts into a guest:
•As described in Section 15.13.1, the VMM can intercept physical interrupts that arrive while a
guest is running, by activating the INTR intercept in the VMCB.
•As described in Section 15.21.4, the VMM can virtualize the interrupt masking logic by setting the
V_INTR_MASKING bit in the VMCB.
•The three VMCB fields V_IRQ, V_INTR_PRIO, and V_INTR_VECTOR indicate whether thereis a virtual interrupt pending, and, if so, what its vector number and priority are. The VMRUNinstruction loads this information into corresponding on-chip registers.
•The processor takes a virtual INTR interrupt if:
- V_IRQ and V_INTR_PRIO indicate that there is a virtual interrupt pending whose priority is 
greater than the value in V_TPR,
- interrupts are enabled in EFLAGS.IF,- interrupts are enabled using GIF, and- the processor is not in an interrupt shadow (see Section 15.21.5).The only other difference between virtual INTR handling and normal interrupt handling is that, in
the latter case, the interrupt vector is obtained from the V_INTR_VECTOR register (as opposed torunning an INTACK cycle to the local APIC).
•The V_IGN_TPR field in the VMCB can be set to indicate that the currently pending virtualinterrupt is not subject to masking by TPR. The priority comparison against V_TPR is omitted inthis case. This mechanism can be used to inject ExtINT-type interrupts into the guest. 
•When the processor dispatches a virtual interrupt (through the IDT), V_IRQ is cleared afterchecking for intercepts of virtual interrupts and before the IDT is accessed.
•On #VMEXIT, V_IRQ is written back to the VMCB, allowing the VMM to track whether a virtualinterrupt has been taken.
•Physical interrupts take priority over virtual interrupts, whether they are taken directly or through a#VMEXIT.
•On #VMEXIT, the processor clears its internal copies of V_IRQ and V_INTR_MASKING, sovirtual interrupts do not remain pending in the VMM, and interrupt control reverts to normal.
15.21.5  Interrupt Shadows
The x86 architecture defines the notion of an interrupt shadow —a single-instruction window during 
which interrupts are not recognized. For example, the instruction after an STI instruction that sets 
EFLAGS.IF (from zero to one) does not recognize interrupts or certain debug traps. The VMCB 
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INTERRUPT_SHADOW field indicates whether the guest is currently in an interrupt shadow. This 
information is saved on #VMEXIT and loaded on VMRUN.
15.21.6  Virtual Interrupt Intercept
When virtualizing interrupt handling, a VMM typically needs only gain control when new interrupts 
for a guest arrive or are generated, and when the guest issues an EOI (end-of-interrupt). In some circumstances, it may also be necessary for the VMM to gain control at the moment interrupts become enabled in the guest (i.e., just before the guest takes a virtual interrupt). The VMM can do so by enabling the VINTR intercept.
15.21.7  Interrupt Masking in Local APIC
When guests have direct access to devices, interrupts arriving at the local APIC can usually be 
dismissed only by the guest that owns the device causing the interrupt. To prevent one guest from blocking other guests’ interrupts (by never processing their own), the VMM can mask pending interrupts in the local APIC, so they do not participate in the prioritization of other interrupts. 
SVM introduces the following APIC features:
•A 256-bit IER (interrupt enable) register is added to the local APIC. This register resets to all ones
(enabling all 256 vectors). Software can read and write the IER by means of the memory-mappedAPIC page.
•Only vectors that are enabled in the IER participate in the APIC computation of the highest-priority pending interrupt.
•The VMM can issue specific end-of-interrupt (EOI) commands to the local APIC, allowing theVMM to clear pending interrupts in any order, rather than always targeting the interrupt withhighest-priority.
15.21.8  INIT Support
The INIT signal interrupts the processor at the next instruction boundary and causes an unconditional 
control transfer. INIT reinitializes the control registers, segment registers and GP registers in a manner similar to RESET, but does not alter the contents of most MSRs, caches or numeric coprocessor (x87 or SSE) state, and then transfers control to the same instruction address as RESET (physical address FFFFFFF0h). Unlike RESET, INIT is not expected to be visible to the memory controller, and hence will not trigger automatic clearing of trusted memory pages by memory controller hardware. 
To maintain the security of such pages, the VMM can request that INITs be redirected and turned into

To maintain the security of such pages, the VMM can request that INITs be redirected and turned into 
#SX exceptions by setting the R_INIT bit in the VM_CR MSR (see Section 15.30.1). This allows the 
VMM to gain control when an INIT is requested and scrub any sensitive context. The VMM may then disable the redirection of INIT and cause the platform to reassert INIT (see the relevant BIOS and 
Kernel Developer’s Guide  or Processor Programming Reference Manual  for details), at which point 
the processor will respond in the normal manner. The actions initiated by the INIT pin may also be initiated by an incoming APIC INIT interrupt; the mechanisms described here apply in either case. Table 15 -12 summarizes the handling of INITs.
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If redirection is enabled without the INIT intercept being enabled, an INIT that asserts during guest 
execution will result in #SX being asserted within the guest, with the INIT being cleared. The VMM may intercept the assertion of #SX as described in “Intercept Operation” on page 507. Note that when 
a VMM has intercepted an INIT assertion, it may modify R_INIT any time before setting GIF to control the behavior when GIF is ultimately set, or the VMM may instead return to a guest VM with the intercept disabled and redirection enabled to effectively hand off the INIT to the guest as a #SX exception.
15.21.9  NMI Support
The VMM can intercept non-maskable interrupts (NMI) using a VMCB control bit (see Table 15 -13). 
When intercepted, NMIs cause an exit from the guest and are held pending.
15.21.10  NMI Virtualization
NMI Virtualization allows the host to inject an NMI (#NMI) into a guest. While inside a guest, the 
virtual NMI follows the same rules as a physical NMI. With NMI Virtualization, the processor virtualizes the masking state of NMIs which prevents a guest from taking a second virtual NMI until the execution of an IRET instruction.
NMI Virtualization support is indicated by CPUID Fn8000_000A_EDX[VNMI] = 1.NMI Virtualization is enabled by setting V_NMI_ENABLE (bit 26 in offset 60h of the VMCB). 
Enabling NMI Virtualization requires the NMI intercept bit to be set. An attempt to run a guest with V_NMI_ENABLE without the NMI intercept bit set results in #VMEXIT(INV ALID). When NMI Virtualization is enabled, NMI intercepts only apply to physical NMIs, not virtual NMIs. 
Three new bits are added to the VMCB field at offset 60h to provide NMI virtualization hardware 
support:Table 15-12. INIT Handling in Different Operating Modes
GIF INIT Intercept INIT Redirect Processor Response to INIT
0 X X Hold pending until GIF = 1.
11 X #VMEXIT(INIT), INIT is still pending.
00 Taken normally.
1 #SX, INIT is no longer pending.
Table 15-13. NMI Handling in Different Operating Modes
GIF NMI Intercept Processor Response to NMI
0 X Hold pending until GIF=1.
11 #VMEXIT(NMI), NMI is still pending.0 Taken normally.
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V_NMI : Indicates whether a virtual NMI is pending in the guest. The processor will clear V_NMI 
once it takes the virtual NMI.
V_NMI_MASK: Indicates whether virtual NMIs are masked. The processor will set V_NMI_MASK 
once it takes the virtual NMI. V_NMI_MASK is cleared when the guest successfully completes an IRET instruction or #VMEXIT occurs while delivering the virtual NMI.
V_NMI_ENABLE : Enables NMI virtualization.
SVM provides an efficient mechanism by which the VMM can inject virtual NMI into a guest:
•The VMM can inject NMI into the guest by setting V_NMI_ENABLE and V_NMI in the VMCB.
•When V_NMI_ENABLE is set, VMRUN loads V_NMI and V_NMI_MASK from the VMCB
into internal registers.
•The processor takes a virtual NMI if:
- virtual NMIs are not masked, - interrupts are enabled with GIF, - virtual interrupts are enabled with VGIF, and- the processor is not in an interrupt shadow.
•When the processor recognizes a virtual NMI, V_NMI is cleared and V_NMI_MASK is set before
the IDT is accessed.
•On #VMEXIT, V_NMI and V_NMI_MASK are written back to the VMCB.
•If a #VMEXIT occurs during the virtual NMI delivery, EXITINTINFO is set appropriately andV_NMI_MASK is saved as 0.
•If Event Injection is used to inject an NMI when NMI Virtualization is enabled, VMRUN setsV_NMI_MASK in the guest state.
•Physical NMI takes priority over virtual NMI.
15.22 SMM Support
This section describes SVM support for virtualization of System Management Mode (SMM).
15.22.1  Sources of SMI
Various events can cause an assertion of a system management interrupt (SMI); these are classified 
into three categories
•Internal, synchronous (also known as I/O Trapping)—implementation-specific IOIO or config
space trapping in the CPU itself; always synchronous in response to an IN or OUT instruction. I/OTrapping is set up by means of MSRs and can be brought under the control of the VMM byintercepting guest access to those MSRs.
•External, synchronous—IOIO trapping in response to (and synchronous with) IN or OUTinstructions, but generated by an external agent (typically the Southbridge).
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•External, asynchronous—generated externally in response to an external, physical event, e.g.,
closing a laptop lid, temperature sensor triggering, etc.
15.22.2  Response to SMI
How hardware responds to SMIs is a function of whether SMM interrupts are being intercepted and 
whether interrupts are enabled globally, as shown in Table 15 -14.
 
By intercepting SMIs, the VMM can gain control before the processor enters SMM.
15.22.3  Containerizing Platform SMM
In some usage scenarios, the VMM may not trust the existing platform SMM code, or may otherwise 
want to ensure that the SMM does not operate in the context of certain guests or the hypervisor. To address these cases, SVM provides the ability to containerize  SMM code, i.e., run it inside a guest, 
with the full protection mechanisms of the VMM in place. In other scenarios, the VMM may not want to exert control over SMM.
There are three solutions for the VMM to control SMM handlers:
•The simplest solution is to not intercept SMI signals. SMIs encountered while in a guest context
are taken from within the guest context. In this case, the SMM handler is not subject to anyintercepts set up by the VMM and consequently runs outside of the virtualization controls. Thestate saved in the SMM State-Save area as seen by the SMM handler reflects the state of the guestthat had been running at the time the SMI was encountered. When the SMM handler executes theRSM instruction, the processor returns to executing in the guest context, and any modifications tothe SMM State-Save area made by the SMM handler are reflected in the guest state.
•A hypervisor may want to emulate all SMI-based I/O interceptions for a guest and to take SMIsignals only in the hypervisor context. The hypervisor should set all IOIO intercept bits and theSMI intercept bit for the guest to ensure that there is no possibility of encountering synchronous(internal or external) SMI signals while running the guest. Any #VMEXIT(SMI) encountered isthen known to be due to an external, asynchronous SMI. The hypervisor may respond to the#VMEXIT(SMI) by executing the STGI instruction, which causes the pending SMI to be takenimmediately. When an SMI due to an I/O instruction is pending, the effect of executing STGI inthe hypervisor is undefined. To handle a pending SMI due to an I/O instruction, the hypervisormust either containerize SMM or not intercept SMI.Table 15 -14. SMI Handling in Different Operating Modes
GIFIntercept
SMIInternal SMI External SMI
0 x Lost. Hold pending until GIF=1.
11Exit guest,
code #VMEXIT(SMI), SMI is not pending.#VMEXIT(SMI), SMI is still pending.
0 Taken normally. Taken normally.
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•The most involved solution is to containerize SMM by placing it in a guest. Containerizing gives
the VMM full control over the state that the SMM handler can access.
Containerizing Platform SMM.  A VMM can containerize SMM by creating its own trusted SMM 
hypervisor and use that handler to run the platform SMM code in a container. The SMM hypervisor may be the same code as the VMM itself, or may be an entirely different set of code. The trusted SMM hypervisor sets up a guest context to run the platform SMM as a guest. The guest context consists of a VMCB and related state and the guest's (real or virtual) SMM save area. The SMM hypervisor emulates SMM entry, including setup of the SMM save area, and emulates RSM at the end of SMM operation.   The guest executes the platform SMM code in paged real mode with appropriate SVM intercepts in place, thus ensuring security.
For this approach to work, the VMM may need to write the SMM_BASE MSR, as well as related 
SMM control registers. As part of the emulation of SMM entry and RSM, the VMM needs to access the SMM_CTL MSR (see Section 15.30.3). However, these actions conflict with any platform 
firmware that locks SMM control registers.

A VMM can determine if it is running with a compatible firmware setup by checking the SMMLOCK 
bit in the HWCR MSR (described in the BIOS and Kernel Developer’s Guide (BKDG) or Processor 
Programming Reference Manual  applicable to your product). If the bit is 1, firmware has locked the 
SMM control registers and the VMM is unable to move them or insert its own SMM hypervisor. 
As the processor physically enters SMM, the SMRAM regions are remapped. The VMM design must 
ensure that none of its code or data disappears when the SMRAM areas are mapped or unmapped. Also note that the ASEG region of the SMRAM overlaps with a portion of video memory, so the SMM hypervisor should not attempt to write diagnostic messages to the screen. Any attempt by guests to relocate any of the SMRAM areas (by means of certain MSR writes) must also be intercepted to prevent malicious SMM code from interfering with VMM operation.
Writes to the SMM_CTL MSR cause a #GP if firmware has locked the SMM control registers.
15.23 Last Branch Record Virtualization
The debug control MSR (DebugCtl) provides control of control-transfer recording and other debug 
facilities. (See Chapter 13, “Software Debug and Performance Resources,” on page 389, for more information on using the debug control MSR.) Software sets the last-branch record (DebugCtl[LBR]) bit to 1 to cause the processor to record the source and target addresses of the last control transfer taken before a debug exception. These control transfers include branch instructions, interrupts, and exceptions. Recorded information is stored in four MSRs:
•LastBranchFromIP
•LastBranchToIP
•LastIntFromIP 
•LastIntToIP
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Under SVM, to virtualize the function of these MSRs, the VMM must save the contents of the control-
transfer recording MSRs on #VMEXIT and restore them prior to the VMRUN for each guest. If control-transfer recording is to be used in host state as well the values of these registers must be exchanged between values tracked by host and guest. 
15.23.1  Hardware Acceleration for LBR Virtualization
Processors optionally support hardware acceleration for LBR virtualization. The following fields are 
allocated in the VMCB state save area to hold the contents of the DebugCtl and control-transfer recording MSRs: 
•DBGCTL—Holds the guest value of the DebugCtl MSR.
•BR_FROM—Holds the guest value of the LastBranchFromIP MSR.
•BR_TO—Holds the guest value of the LastBranchToIP MSR.
•LASTEXCPFROM—Holds the guest value of the LastIntFromIP MSR.
•LASTEXCPTO—Holds the guest value of the LastIntToIPLastIntToIP MSR.
When VMCB.LBR_VIRTUALIZATION_ENABLE is set, VMRUN saves all five host control-
transfer MSRs in the host save area, and then loads the same five MSRs for the guest from the VMCB save area. Similarly, #VMEXIT saves the guest's MSRs and loads the host's MSRs to and from their respective save areas.
On processors supporting LBR Stack, VMCB.LBR_ VIRTUALIZATION_ENABLE also controls 
save and restore of the following fields in the VMCB state save area:
•DBGEXNTCTL - Holds the guest value of the DebugExtnCtl MSR.
•LBR_STACK_FROM - Holds the guest value of the LastBranchStackFromIp MSRs 
•LBR_STACK_TO - Holds the guest value of the LastBranchStackToIp MSRs 
•LBR_SELECT - Holds the guest value of the LastBranchStackSelect MSR.
VMRUN saves the host state and restores the guest state and #VMEXIT saves the guest state and 
restores the host state of the DebugExtnCtl MSR. VMRUN only restores the guest state and #VMEXIT only saves the guest state of the LastBranchStackFromIp, LastBranchStackToIp and LastBranchStackSelect MSRs. For SEV-ES guests #VMEXIT clears the contents of the LastBranchStackFromIp, LastBranchStackToIp and LastBranchStackSelect MSRs after saving the guest state. 
15.23.2  LBR Virtualization CPUID Feature Detection
CPUID Fn8000_000A_EDX[LbrVirt] = 1 indicates support for the LBR virtualization acceleration 
feature on AMD64 processors. See Section 3.3, “Processor Feature Identification,” on page 71 for more information on using the CPUID instruction.
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15.24 External Access Protection
By securing the virtual address translation mechanism, the VMM can restrict guest CPU accesses to 
memory. However, should the guest have direct access to DMA-capable devices, an additional protection mechanism is required. SVM provides multiple protection domains which can restrict device access to physical memory on a per-page basis. This is accomplished via control logic in the Northbridge’s host bridge which governs any external access port (e.g., PCI or HyperTransport™ technology interfaces).
15.24.1  Device IDs and Protection Domains
The Northbridge’s host bridge provides a number of protection domains. Each protection domain has 
associated with it a device exclusion vector (DEV) that specifies the per-page access rights of devices in that domain. Devices are identified by a HyperTransport™ bus/unitID (device ID) and the host bridge contains a lookup table of fixed size that maps device IDs to a protection domain. 
15.24.2  Device Exclusion Vector (DEV)
A DEV is a contiguous array of bits in physical memory; each bit in the DEV (in little-endian order) 
corresponds to one 4-Kbyte page in physical memory.
The physical address of the base of a DEV must be 4-Kbyte-aligned and stored in one of the 
DEVBASE registers, which are accessed through an indirection mechanism in the DEVCTL PCI Configuration Space function block in the host bridge (see “DEV Control and Status Registers” on page 544). The DEV protection hardware is not operational until enabled by setting a control bit in the DEV Control Register, also in the DEVCTL function block.
The DEV may have to cover part of MMIO space beyond the DRAM. Especially in 64-bit systems, the 
operating system should map MMIO space starting immediately after the DRAM area and building up, as opposed to starting down from the maximum physical address.
Host Bridge and Processor DEV Caching.  For improved performance, the host bridge may cache 
portions of the DEV . Any such cached information can be invalidated by setting the DEV_FLUSH flag in the DEV control register to 1. Software must set this flag after modifying DEV contents to ensure that the protection logic uses the updated values. The host bridge automatically clears this flag when the flush operation completes. After setting this flag, software should monitor it until it has cleared, in order to synchronize DEV updates with subsequent activity. 
By default, the host bridge probes the processor caches for the latest data when it accesses the DEV in 
DRAM. However, it is possible to disable probing by means of the DEV_CR register (“DEV_CR Register” on page 544); this is recommended in the case of unified memory architecture (UMA) graphics systems. If cache probing is disabled, host bridge reads of the DEV will not check processor caches for more recent copies. This requires software on the CPU to map the memory containing the DEV as uncacheable (UC) or write-through (WT). Alternatively, software must perform a CLFLUSH before it can expect a change to the DEV to be visible by the Northbridge (and before software flushes the DEV cache in the host controller).
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Multiprocessor Issues.  Device-originated memory requests are checked against the DEV at the 
point of entry to the system—the Northbridge to which the device is physically attached. Each 
Northbridge can have its own set of domains, device-to-domain mappings, and DEV tables (e.g., domain #2 on one node can encompass different devices, and can have different access rights than domain #2 on another node). Thus, the number of protection domains available to software can scale with the number of Northbridges in the system.
15.24.3  Access Checking
Memory Space Accesses.  When a memory-space read or write request is received on an external 
host bridge port, the host bridge maps the HyperTransport bus device ID to a protection domain 
number, which in turn selects the DEV defining the access permissions for the device (see 
Figure 15 -6). The host bridge then checks the memory address against the DEV contents by indexing 
into the DEV with the PFN portion of the address (bits 39:12). The PFN is used as a bit index within the DEV . If the bit read from the DEV is set to 1, the host bridge inhibits the access by returning all ones for the data for a read request, or suppressing the store operation on a write request. A Master Abort error response will be returned to the requesting device.
Peer-to-peer memory accesses routed up to the host bridge are also subjected to checks against the 
DEV . Peer-to-peer transfers that may be occurring behind bridges are not checked.
DEV checks are applied before addresses are translated by the GART. The DEV table is never

DEV checks are applied before addresses are translated by the GART. The DEV table is never 
consulted by accesses originating in the CPU.
I/O Space Accesses.  The host bridge can be configured to reject all I/O space accesses from 
devices, by setting the IOSPE bit in the DEV_CR control register (see “DEV_CR Register” on page 544). I/O space peer-to-peer transfers behind bridges are not checked.
Config Space Accesses.  Major aspects of host bridge functionality are configured by means of 
control registers that are accessed through PCI configuration space. Because this is potentially accessible by means of device peer-to-peer transfers, the host bridge always blocks access to this space from anything other than the CPU.
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Figure 15-6. Host Bridge DMA Checking
15.24.4  DEV Capability Block
The presence of DEV support is indicated through a new PCI capability block. The capability block 
also provides access to the registers that control operation of the DEV feature.
The DEV capability block in PCI space contains three 32-bit words: the capability header 
(DEV_HDR), and two registers (DEV_OP and DEV_DATA) which serve as an indirection mechanism for accessing the actual DEV control and status registers.
DEV Capability Header.  The DEV capability header (DEV_HDR) is defined in Table 15 -16.Table 15-15. DEV Capability Block, Overall Layout
Byte Offset Register Comments
0 DEV_HDR Capability block header
4 DEV_OP Selects control/status register to access
8 DEV_DATA Read/write to access register selected in DEV_OPDEV Cache
with
 Domain#Tagged
DEV Table
WalkerHyperTransport
to
Domain#
(Zero if No Match)Bus/Dev IDPhysical Address
DEV_BASE/LIMIT[0]
DEV_BASE/LIMIT[1]
DEV_BASE/LIMIT[2]
DEV_BASE/LIMIT[3]Domain#Bus/Dev IDTM
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15.24.5  DEV Register Access Mechanism
The Northbridge’s DEV control and status registers are accessed through an indirection mechanism: 
writing the DEV_OP register selects which internal register is to be accessed, and the DEV_DATA register can be read or written to access the selected register.
Figure 15 -7 shows the format of the DEV_OP register. The DEV_DATA register reflects the format of 
the DEV register selected in DEV_OP.
Figure 15 -7. Format of DEV_OP Register (in PCI Config Space)
The FUNCTION field in the DEV_OP register selects the function/register to read or write according 
to the encoding in Table 15 -17; for blocks of registers that have multiple instances (e.g., multiple 
DEV_BASE_HI/LO registers), the INDEX field selects the instance; otherwise it is ignored.Table 15-16. DEV Capability Header (DEV_HDR) (in PCI Config Space)
31:22 Reserved, MBZ
21 Interrupt Reporting Capability
20 Machine Check Exception Reporting Capability
19 Reserved, MBZ
18:16 DEV Capability Block Type; hardwired to 000b.
15:8 PCI Capability pointer; points to next capability in list
7:0 PCI Capability ID; hardwired to 0x0F
31 16 15 8 7 0
Reserved, MBZ FUNCTION INDEX
Table 15-17. Encoding of Function Field in DEV_OP Register
Function Code Register Type Number of Instances
0 DEV_BASE_LO multiple
1 DEV_BASE_HI multiple
2 DEV_MAP multiple
3 DEV_CAP single
4 DEV_CR single
5 DEV_ERR_STATUS single
6 DEV_ERR_ADDR_LO single
7 DEV_ERR_ADDR_HI single
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For example, to write the DEV_BASE_HI register for protection domain number 2, software sets 
DEV_OP.FUNCTION to 1, and DEV_OP.INDEX to 2, and then writes the desired 32-bit value into DEV_DATA. As the DEV_OP and DEV_DATA registers are accessed through PCI config space (ports 0CF8h–0CFFh), they may be secured from unauthorized access by software executing on the processor by appropriate settings in the SVM I/O protection bitmap. These registers are also protected by the host bridge from external access as described in “Config Space Accesses” on page 541.
15.24.6  DEV Control and Status Registers
The DEV control and status registers are accessible by means of the indirection mechanism; these 
registers are not directly visible in PCI config space.
DEV_CAP Register.  Read-only register; holds implementation specific information: the number of 
protection domains supported, the number of DEV_MAP registers (which map device/unit IDs to domain numbers), and the revision ID. 
Figure 15-8. Format of DEV_CAP Register (in PCI Config Space)
The initial implementation provide four domains and three map registers.
DEV_CR Register.  This is the main control register for the DEV mechanism; it is cleared to zero by 
RESET.31 24 23 16 15 8 7 0
Reserved, RAZ N_MAPS N_DOMAINS REVISION
Table 15-18. DEV_CR Control Register
31:7 Reserved, MBZ
6DEV table walk probe disable.
0 = Use probe on DEV walk; 1 = Do not use probe
5SL_DEV_EN. Enable bit for limited memory protection, see Section 15.24.8 on 
page 546. Set to “1” by SKINIT instruction, can be cleared by software.
4Invalidate DEV cache. Software must set this bit to 1 to invalidate the DEV cache; cleared by hardware when invalidation is complete.
3Enable MCE reporting.
0 = Do not generate MCE; 1 = Generate MCE on errors.
2I/O space protection enable (IOSPEN)0 = Allow upstream I/O cycles; 1 = Block.
1Memory clear disable. If non-zero, memory-clearing on reset is disabled. This bit is not writable until the memory is enabled.
0 DEV global enable bit. If zero, DEV protection is turned off. 
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DEV_BASE Address/Limit Registers.  The DEV base address registers (one set per domain) each 
point to the physical address of a DEV table corresponding to a protection domain. The address and 
size are encoded in a pair (high/low) of 32-bit registers. The N_DOMAINS field in DEV_CAP indicates how many (pairs of) DEV_BASE registers are implemented. The register format is as shown in Figures 15 -9 and 15 -10.
Figure 15-9. Format of DEV_BASE_HI[n] Registers
Figure 15-10. Format of DEV_BASE_LO[n] Registers
Fields of the DEV_BASE_HI and DEV_BASE_LO registers are defined as follows:
•Valid (V) —Bit 0. Indicates whether a DEV table has been defined for the given protection domain;
if this bit is clear, software can leave the other fields undefined, and no protection checks are
performed for memory references in this domain.
•Protect (P) —Bit 1. Indicates whether accesses to addresses beyond the address range covered by
the DEV are legal (P=0) or illegal (P=1).
•SIZE —Bits 6:2. Specifies how much memory the DEV covers, expressed increments of 4GB *
2
size. In other words, a DEV table covers a minimum of 4GB, and can expand by powers of two.
DEV_MAP Registers.  The DEV_MAP registers assign protection domain numbers to device-
originated requests by matching the device ID (HT bus and unit number) associated with the request against bus and unit numbers in the registers. If no match is found in any of the registers, a domain number of zero is returned. The number of DEV_MAP registers implemented by the chip is indicated by the N_MAPS field in DEV_CAP.
The format of the DEV_MAP registers is shown in Figure 15 -11.
 
Figure 15-11. Format of DEV_MAP[n] Registers31 8 7 0
Reserved, MBZ BASEADDRESS[39:32]
31 12 11 7 6 2 1 0
BASEADDRESS[31:12] Reserved, MBZ SIZE P V
31 26 25 20 19 12 11 10 6 5 4 0
DOM1 DOM0 BUSNO V1 UNIT1 V0 UNIT0
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The fields of the DEV_MAP[ n] registers are defined as follows:
•UNIT0—Bits 4:0. Specifies the first of two HyperTransport link unit numbers on the bus number
specified by the BUSNO field.
•V0—Bit 5. Indicates whether UNIT0 is valid (no matches occur on invalid entries).
•UNIT1—Bits 10:6. Specifies the second of two HyperTransport link unit numbers on the bus
number specified by the BUSNO field.
•V1—Bit 11. Indicates whether UNIT1 is valid (no matches occur on invalid entries).
•BUSNO—Bits 19:12. Specifies a HyperTransport link bus number.
•DOM0—Bits 25:20. Specifies the protection domain for the first HyperTransport link unit.
•DOM1—Bits 31:26. Specifies the protection domain for the second HyperTransport link unit.
15.24.7  Unauthorized Access Logging 
Any attempted unauthorized access by devices to DEV-protected memory is logged by the host bridge 
in the DEV_Error_Status and DEV_Error_Address registers for possible inspection by the VMM.
15.24.8  Secure Initialization Support 
The host bridge contains additional logic that operates in conjunction with the SKINIT instruction to 
provide a limited form of memory protection during the secure startup protocol. This provides protection for a Secure Loader image in memory, allowing it to, among other things, set up full DEV protection. (See Section 15.27 for detailed operation of SKINIT.)
The host bridge logic includes a hidden (not accessible to software) SL_DEV_BASE address register.

The host bridge logic includes a hidden (not accessible to software) SL_DEV_BASE address register. 
SL_DEV_BASE points to a 64KB-aligned 64KB region of physical memory. When SL_DEV_EN is 1, the 64KB region defined by SL_DEV_BASE is protected from external access (as if it were protected by the DEV), as well as from any access (both CPU and external accesses) via GART-translated addresses. Additionally, the SL_DEV mechanism, when enabled, blocks all device accesses to PCI Configuration space.
15.25 Nested Paging
The optional SVM nested paging feature provides for two levels of address translation, thus eliminating the need for the VMM to maintain shadow page tables.
15.25.1  Traditional Paging versus Nested Paging
Figure 15 -12 shows how a page in the linear address space is mapped to a page in the physical address 
space in traditional (single-level) address translation. Control register CR3 contains the physical 
address of the base of the page tables (PT, represented by the shaded box in the figure), which governs the address translation.
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Figure 15-12. Address Translation with Traditional Paging
With nested paging enabled, two levels of address translation are applied; refer to Figure 15 -13 below.
•Both guest and host levels have their own copy of CR3, referred to as gCR3 and nCR3,
•Guest page tables (gPT) map guest linear addresses to guest physical addresses. The guest pagetables are in guest physical memory, and are pointed to by gCR3.
•Nested page tables (nPT) map guest physical addresses to system physical addresses. The nestedpage tables are in system physical memory, and are pointed to by nCR3.
•The most-recently used translations from guest linear to system physical address are cached in theTLB and used on subsequent guest accesses.
It is important to note that gCR3 and the guest page table entries contain guest physical addresses, not system physical addresses. Hence, before accessing a guest page table entry, the table walker first translates that entry’s guest physical address into a system physical address.Linear Space
PT0
0CR3
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Figure 15-13. Address Translation with Nested Paging
The VMM can give each guest a different ASID, so that TLB entries from different guests can coexist 
in the TLB. The ASID value of zero is reserved for the host; if the VMM attempts to execute VMRUN with a guest ASID of zero, the result is #VMEXIT(VMEXIT_INV ALID). Note that because an ASID is associated with the guest's physical address space, it is common across all of the guest's virtual address spaces within a processor. This differs from shadow page tables where ASIDs tag individual guest virtual address spaces. Note also that the same ASID may or may not be associated with the same address space across all processors in a multiprocessor system, for either nested tables or shadow tables; this depends on how the VMM manages ASID assignment.
15.25.2  Replicated State
Most processor state affecting paging is replicated for host and guest. This includes the paging 
registers  CR0, CR3, CR4, EFER and PAT. CR2 is not replicated but is loaded by VMRUN. The 
MTRRs are not replicated.
While nested paging is enabled, all (guest) references to the state of the paging registers by x86 code 
(MOV to/from CR n, etc.) read and write the guest copy of the registers; the VMM's versions of the 
registers are untouched and continue to control the second level translations from guest physical to system physical addresses. In contrast, when nested paging is disabled, the VMM's paging control registers are stored in the host state save area and the paging control registers from the guest VMCB are the only active versions of those registers.Guest Linear
gPT0
0
Host Linear0
nPT0Guest Physicalpaged bygCR3gCR3
nCR3
PTCR3 (used by VMM)
System Physicalpaged by
the VMM’s CR3
paged bynCR3
TLB EntryVMM
gPT
paged by
nCR3
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15.25.3  Enabling Nested Paging
The VMRUN instruction enables nested paging when the NP_ENABLE bit in the VMCB is set to 1. 
The VMCB contains the hCR3 value for the page tables for the extra translation. The extra translation uses the same paging mode as the VMM used when it executed the most recent VMRUN.
Nested paging is automatically disabled by #VMEXIT.Nested paging is allowed only if the host has paging enabled. Support for nested paging is indicated by 
CPUID Fn8000_000A_EDX[NP] = 1. If VMRUN is executed with hCR0.PG cleared to zero and NP_ENABLE set to 1, VMRUN terminates with #VMEXIT(VMEXIT_INV ALID). See Section 3.3, 
“Processor Feature Identification,” on page 71 for more information on using the CPUID instruction.
15.25.4  Nested Paging and VMRUN/#VMEXIT
When VMRUN is executed with nested paging enabled (NP_ENABLE = 1), the paging registers are 
affected as follows:
•VMRUN saves the VMM’s CR3 in the host save area. 
•VMRUN loads the guest paging state from the guest VMCB into the guest registers (i.e., VMRUN
loads CR3 with the VMCB CR3 field, etc.). The guest PAT register is loaded from G_PAT field inthe VMCB.
•VMRUN loads nCR3, the version of CR3 to be used while the nested-paging guest is running,from the N_CR3 field in the VMCB. The other host paging-control bits (hCR4.PAE, etc.) remainthe same as they were in the VMM at the time VMRUN was executed.
When VMRUN is executed with nested paging enabled (NP_ENABLE = 1), the following conditions are considered illegal state combinations, in addition to those mentioned in “Canonicalization and Consistency Checks” on page 503:
•Any MBZ bit of nCR3 is set.
•Any G_PAT.PA field has an unsupported type encoding or any reserved field in G_PAT has a non-zero value. (See Section 7.8.1, “PAT Register,” on page 226.)
When #VMEXIT occurs with nested paging enabled:
•#VMEXIT writes the guest paging state (gCR3, gCR0, etc.) back into the VMCB. nCR3 is not
saved back into the VMCB.
•#VMEXIT need not reload any host paging state other than CR3 from the host save area, though animplementation is free to do so.
15.25.5  Nested Table Walk
When the guest is running with nested paging enabled, a TLB miss causes several nested table walks:
•Guest Page Tables—the gCR3 register specifies a guest physical address, as do the entries in the
guest's page tables. These guest physical addresses must be translated to system physical addresses
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using the nested page tables. Nested page table level faults can occur on these accesses, including
write faults due to setting of accessed and dirty bits in the guest page table.
•Final Guest-Physical Page—once a guest linear to guest physical mapping is known, guestpermissions can be checked. If the guest page tables allow the access, the guest physical address iswalked in the nested page tables to find the system physical address.
Unless Read Only Guest Page Tables is enabled for a guest, table walks for guest page tables are always treated as user writes at the nested page table level. For this reason,
•the page must be writable by user at the nested page table level, or else a #VMEXIT(NPF) is
raised, and
•the dirty and accessed bits are always set in the nested page table entries that were touched duringnested page table walks for guest page table entries.
A table walk for the guest page itself is always treated as a user access at the nested page table level, but is treated as a data read, data write, or code read, depending on the guest access.
CPUID Fn8000000A_EDX[ROGPT] (bit 21) = 1 indicates support for Read Only Guest Page Tables. 
Read Only Guest Page Tables is enabled for a guest by setting VMCB bit 6 at offset 90h. When Read Only Guest Page Tables is enabled, guest page table accesses are treated as writes at the nested page table level only when an access or dirty bit update in a guest page table is required, thus allowing a hypervisor to map guest page tables into read-only nested pages. 
If the guest has paging disabled (gCR0.PG = 0), there are no guest page table entries to be translated in 
the nested page tables. In this case, the final guest-physical address is equal to the guest-linear address, and is still translated in the nested page tables.
15.25.6  Nested versus Guest Page Faults, Fault Ordering
In nested paging, page faults can be raised at either the guest or nested page table level. Nested walks 
proceed in the following order; faults are generated in the same order:
1. Walk the guest page table entries in the nested page table. Dirty/Accessed bits are set as needed in
the nested page table. Any nested page table faults result in #VMEXIT(NPF).
2. As the guest page table walk proceeds from the top of the page table to the last entry, any not-
present entries or reserved bits in the guest page table entries at each level of the guest walk cause

#PF in the guest. Guest dirty and accessed bits are set as needed in the guest page tables during thewalk. Steps 1 and 2 are repeated for each level of the guest page table that is traversed.
3. Once the guest physical address for the guest access has been determined, check the guest
permissions; any fault at this point causes a #PF in the guest.
4. Perform the final translation from guest physical to system physical using the nested page table;
any fault during this translation results in a #VMEXIT(NPF).
Nested page faults are entirely a function of the nested page table and VMM processor mode. Nested faults cause a #VMEXIT(NPF) to the VMM. The faulting guest physical address is saved in the VMCB's EXITINFO2 field; EXITINFO1 delivers an error code similar to a #PF error code:
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•Bit 0 (P)—cleared to 0 if the nested page was not present, 1 otherwise
•Bit 1 (RW)—set to 1 if the nested page table level access was a write. Note that host table walks for
guest page tables are always treated as data writes.
•Bit 2 (US)—set to 1 if the nested page table level access was a user access. Note that nested pagetable accesses performed by the MMU are treated as user accesses unless there are featuresenabled that override this.
•Bit 3 (RSV)—set to 1 if reserved bits were set in the corresponding nested page table entry
•Bit 4 (ID)—set to 1 if the nested page table level access was a code read. Note that nested tablewalks for guest page tables are always treated as data writes, even if the access itself is a code read
•Bit 6 (SS) - set to 1 if the fault was caused by a shadow stack access. 
In addition, the VMCB contents for nested page faults indicate whether the page fault was encountered during the nested page table walk for a guest page TLB entry, or for the final nested walk for the guest physical address, as indicated by EXITINFO1[33:32]:
•Bit 32—set to 1 if nested page fault occurred while translating the guest’s final physical address
•Bit 33—set to 1 if nested page fault occurred while translating the guest page tables
•Bit 37—set to 1 if the page was marked as a supervisor shadow stack page in the leaf node of the
nested page table and the shadow stack check feature is enabled in VMCB offset 90h.
Guest faults are entirely a function of the guest page tables and processor mode; they are delivered to the guest as normal #PF exceptions without any VMM intervention, unless the VMM is intercepting guest #PF exceptions. Bits 32 and 33 of EXITINFO1 are written during nested page faults to indicate whether the page fault was encountered during the nested page table walk for a guest page table's table entries, or if the fault was encountered during the nested page table walk for the translation of the final guest physical address.
See Section 15.36.10, “RMP and VMPL Access Checks,” on page 608 for additional 
#VMEXIT(NPF) EXITINFO1 field definitions.
The processor may provide additional instruction decode assist information. See Section 15.10.
15.25.7  Combining Nested and Guest Attributes
Any access to guest physical memory is subjected to a permission check by examining the mapping of 
the guest physical address in the nested page table.
A page is considered writable by the guest only if it is marked writable at both the guest and nested 
page table levels. Note that the guest’s gCR0.WP affects only the interpretation of the guest page table entry; setting gCR0.WP cannot make a page writable at any CPL in the guest, if the page is marked read-only in the nested page table. The host hCR0.WP bit is ignored under nested paging.
A page is considered executable by the guest only if it is marked executable at both the guest and 
nested page table levels. If the EFER.NXE bit is cleared for the guest, all guest pages are executable at 
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the guest level. Similarly, if the EFER.NXE bit is cleared for the host, all nested page table mappings 
are executable at the underlying nested level.
Some attributes are taken from the guest page tables and operating modes only. A page is considered 
global within the guest only if is marked global in the guest page tables; the nested page table entry and host hCR4.PGE are irrelevant. Global pages are only global within their ASID.
A page is considered user in the guest only if it is marked as user at the guest level. The page must be 
marked user in the nested page table to allow any guest access at all.
15.25.8  Combining Memory Types, MTRRs
When nested paging is disabled, the processor behaves as though there is no gPAT register. The host PAT MSR determines memory type attributes for the current VM, and guest writes to the PAT 
MSR that aren't intercepted by the VMM will alter the host PAT MSR. The hypervisor is responsible for context-switching the PAT MSR contents on world switches between VMs.
When nested paging is enabled, the processor combines guest and nested page table memory types. 
Registers that affect memory types include:
•The PCD/PWT/PAT i bits in the nested and guest page table entries.
•The PCD/PWT bits in the nested CR3 and guest CR3 registers.
•The guest PAT type (obtained by appropriately indexing the gPAT register).
•The host PAT type (obtained by appropriately indexing the host’s PAT register).
•The MTRRs (which are referenced based only on system physical address).
•gCR0.CD and hCR0.CD.
Note that there is no hardware support for guest MTRRs; the VMM can simulate their effect by 
altering the memory types in the nested page tables. Note that the MTRRs are only applied to system physical addresses.
The rules for combining memory types when constructing a guest TLB entry are:
•Nested and guest PAT types are combined according to Table 15 -19, producing a “combined PAT
type.”
•Combined PAT type is further combined with the MTRR type according to Table 15 -20, where the
relevant MTRRs are determined by the system physical address.
•Either gCR0.CD or hCR0.CD can disable caching.
Memory Consistency Issues.  Because the guest uses extra fields to determine the memory type, the 
VMM may use a different memory type to access a given piece of memory than does the guest. If one 
access is cacheable and the other is not, the VMM and guest could observe different memory images, which is undesirable. (MP systems are particularly sensitive to this problem when the VMM desires to migrate a virtual processor from one physical processor to another.)
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To address this issue, the following mechanisms are provided:
•VMRUN and #VMEXIT flush the write combiners. This ensures that all writes to WC memory by
the guest are visible to the host (or vice-versa) regardless of memory type. (It does not ensure thatcacheable writes by one agent are properly observed by WC reads or writes by the other agent.)
•A new memory type  WC+  is introduced. WC+ is an uncacheable memory type, and combines
writes in write-combining buffers like WC. Unlike WC (but like the CD memory type), accesses toWC+ memory also snoop the caches on all processors (including self-snooping the caches of theprocessor issuing the request) to maintain coherency. This ensures that cacheable writes areobserved by WC+ accesses.
•When combining nested and guest memory types that are incompatible with respect to caching, theWC+ memory type is used instead of WC (and Table 15-20 ensures that the snooping behavior isretained regardless of the host MTRR settings). Refer to Table 15-19 or details.
Table 15 -19 shows how guest and host PAT types are combined into an effective PAT type. When 
interpreting this table, recall (a) that guest and host PAT types are not combined when nested paging is disabled and (b) that the intent is for the VMM to use its PAT type to simulate guest MTRRs.
The existing AMD64 table that defines how PAT types are combined with the physical MTRRs is 
extended to handle CD and WC+ PAT types as shown in Table 15 -20.Table 15-19. Combining Guest and Host PAT Types
Host PAT Type
UC UC– WC WP WT WBGuest PAT TypeUC UC UC UC UC UC UC
UC– UC UC– WC UC UC UC
WC WC WC WC WC+ WC+ WC+
WP UC UC UC WP UC WP
WT UC UC UC UC WT WT
WB UC UC WC WP WT WB
Table 15-20. Combining PAT and MTRR Types
MTRR Type
UC WC WP WT WBEffective PAT TypeUC UC CD CD CD CD
UC– UC WC CD CD CD
WC WC WC WC WC WC
WC+ WC WC WC+ WC+ WC+
WP UC CD WP CD WP
WT UC CD CD WT WT
WB UC WC WP WT WB
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15.25.9  Page Splintering
When an address is mapped by guest and nested page table entries with different page sizes, the TLB 
entry that is created matches the size of the smaller page. 
15.25.10  Legacy PAE Mode
The behavior of PAE mode in a nested-paging guest differs slightly from the behavior of (host-only)

MTRR Type
The behavior of PAE mode in a nested-paging guest differs slightly from the behavior of (host-only) 
legacy PAE mode, in that the guest’s four PDPEs are not loaded into the processor at the time CR3 is written. Instead, the PDPEs are accessed on demand as part of a table walk. This has the side-effect that illegal bit combinations in the PDPEs are not signaled at the time that CR3 is written, but instead when the faulty PDPE is accessed as part of a table walk. 
This means that an operating system cannot rely on the behavior when the in-memory PDPEs are 
different than the in-processor copy.
15.25.11  A20 Masking
There is no provision for applying A20 masking to guest physical addresses; the VMM can emulate 
A20 masking by changing the nested page mappings accordingly.
15.25.12  Detecting Nested Paging Support
Nested Paging is an optional feature of SVM and is not available in all implementations of SVM-
capable processors. The CPUID instruction should be used to detect nested paging support on a particular processor. See Section 3.3, “Processor Feature Identification,” on page 71 for more information on using the CPUID instruction.
15.25.13  Guest Mode Execute Trap Extension
The Guest Mode Execute Trap (GMET) extension allows a hypervisor to cause nested page faults on 
attempts by a guest to execute code at CPL0, 1 or 2 from pages designated by the hypervisor. The presence of the GMET extension is indicated by CPUID Fn8000_000A EDX[17]=1. The GMET mode is selected for a targeted guest by setting bit 3 of VMCB offset 090h to 1. For processors that don’t support GMET this bit is ignored.
On GMET capable processors, when this bit is set to 1 on a VMRUN, the processor changes how the 
U/S bit in the nested page table is interpreted. The NX bit still prohibits execution of code at any privilege level when set to 1. However, with GMET enabled and the effective NX bit =0, if the effective U/S bit =1 and the page is being accessed for execution at CPL0, 1 or 2, a nested page fault #VMEXIT(NPF) is generated. If the effective NX bit =0 and the effective U/S bit =0 then the 
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translation is allowed for the code page. The following table summarizes the behavior when GMET is 
enabled.
The EXITINFO1 field for the nested page fault contains the page fault error code describing attributes 
of the attempted translation that caused the fault. A GMET violation is not explicitly indicated with a separate bit. It is up to software to determine if it was NX based or GMET based by inspecting this error code along with the faulting page’s effective NX and U/S settings.
1
15.25.14  Supervisor Shadow Stacks
The Supervisor Shadow Stack (SSS) feature is an extension to nested paging which allows a 
hypervisor to restrict which guest physical addresses may be used for a guest supervisor shadow stack. Supervisor shadow stack accesses made by the guest to pages not designated as SSS pages in the nested page tables result in a #VMEXIT(NPF).
Determining Support for SSS.  Support for the SSS feature is indicated by CPUID 
Fn8000_000A_EDX[19](SupervisorShadowStack)=1. 
Enabling SSS.  The SSS feature is enabled by setting bit 4 in VMCB offset 90h (See Table B-1. 
VMCB Layout, Control Area). The SSS feature can be enabled only if nested paging is enabled in the VMCB and the PAE and No Execute paging modes (EFER.NXE=1) are enabled in the host.
Attempting to execute a VMRUN with SSS enabled and nested paging disable result in a 
VMEXIT(INV ALID). If the host is not legacy non-PAE mode or EFER.NXE=0, attempts to enable the SSS feature are silently ignored.
The SSS feature can be enabled regardless of whether the guest has enabled shadow stacks or not.
Designating SSS Pages.  When the SSS feature is enabled, the hypervisor indicates a page may be 
used for a supervisor shadow stack using following combination of nested page table bits:
•NX=1 and U/S=0 in the final nested page table entry used to translate the address.
•R/W=1 in all other nested non-leaf page table entries leading to the final nested page table entry.
Although is not enforced by the SSS feature, R/W should be 0 in the final nested page table entry in 
order to achieve the desired security functionality.Table 15-21. GMET Page Configuration 
nPT NX Bit nPT U/S BitGuest
User-Mode CodeGuest
Supervisor-Mode Code
1 X No Execute No Execute
0 1 Execute No Execute
0 0 Execute Execute
1 The guest user/supervisor indication is normally provided in ExitInfo1, however on some im -
plementations a GMET erratum may require CPL to be read from the guest VMCB.
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SSS Access Checking.  When the SSS feature is enabled, guest supervisor shadow stack accesses 
are allowed only to physical pages designated   as SSS pages in the nested page tables. Note that 
supervisor shadow stack writes to SSS pages are allowed to complete even though R/W=0 in the final nested page table entry.
The following accesses to SSS pages are not allowed:
•Supervisor shadow accesses made to non-SSS pages. These result in a #VMEXIT(NPF) with the
SS bit set in the EXITINFO1 error code. 
•Attempting to execute code from an SSS page. This results in a VMEXIT(#NPF) the same as anypage with NX=1.
See Chapter 15.25.6, “Nested versus Guest Page Faults, Fault Ordering,” on page 550 for more information on EXITINFO1 error codes for nested page faults.
15.26 Security
SVM provides additional hardware support that is designed to facilitate the construction of trusted software systems. While the security features described in this section are orthogonal to SVM’s virtualization support (and are not required for processor virtualization), the two form building blocks for trusted systems.
SKINIT Instruction.  The SKINIT instruction and associated system support (the Trusted Platform 
Module or TPM) are designed to allow for verifiable startup of trusted software (such as a VMM), based on secure hash comparison.
Security Exception.  A security exception (#SX) is used to signal certain security-critical events.
15.27 Secure Startup with SKINIT
The SKINIT instruction is one of the keys to creating a “root of trust” starting with an initially untrusted operating mode. SKINIT reinitializes the processor to establish a secure execution environment for a software component called the secure loader (SL) and starts execution of the SL in a way that cannot be tampered with. SKINIT also copies the secure loader executable image to an external device, such as a Trusted Platform Module (TPM) for verification using unique bus transactions that preclude SKINIT operation from being emulated by software in a way that the TPM could not readily detect. (Detailed operation is described in Section 15.27.4.)
15.27.1  Secure Loader
A secure loader (SL) typically initializes SVM hardware mechanisms and related data structures, and 
initiates execution of a trusted piece of software such as a VMM (referred to as a Security Kernel, or SK, in this document), after first having validated the identity of that software.
SKINIT allows SVM protections to be reliably enabled after the system is already up and running in a 
non-trusted mode — there is no requirement to change the typical x86 platform boot process. 
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Exact details of the hand-off from the SL to an SK are dependent on characteristics of the SL, SK and 
the initial untrusted operating environment. However, there are specific requirements for the SL image, as described in Section 15.27.2. 
15.27.2  Secure Loader Image
The secure loader (SL) image contains all code and initialized data sections of a secure loader. This 
code and initial data are used to initialize and start a security kernel in a completely safe manner, including setting up DEV protection for memory allocated for use by SL and SK. The SL image is loaded into a region of memory called the secure loader block (SLB) and can be no larger than 64Kbyte (see Section 15.27.3). The SL image is defined to start at byte offset 0 in the SLB.
The first word (16 bits) of the SL image must specify the SL entry point as an unsigned offset into the SL image. The second word must contain the length of the image in bytes; the maximum length allowed is 65535 bytes. These two values are used by the SKINIT instruction. The layout of the rest of the image is determined by software conventions. The image typically includes a digital signature for validation purposes. The digital signature hash must include the entry point and length fields. SKINIT transfers the SL image to the TPM for validation prior to starting SL execution (see Section 15.27.6 for further details of this transfer). The SL image for which the hash is computed must be ready to execute without prior manipulation.
15.27.3  Secure Loader Block
The secure loader block is a 64Kbyte range of physical memory which may be located at any 64Kbyte-

aligned address below 4Gbyte. The SL image must have been loaded into the SLB starting at offset 0 before executing SKINIT. The physical address of the SLB is provided as an input operand (in the EAX register) to SKINIT, which sets up special protection for the SLB against device accesses (i.e., the DEV need not be activated yet).
The SL must be written to execute initially in flat 32-bit protected mode with paging disabled. A base 
address can be derived from the value in EAX to access data areas within the SL image using base+displacement addressing, to make the SL code position-independent.
Memory between the end of the SL image and the end of the SLB may be used immediately upon entry 
by the SL as secure scratch space, such as for an initial stack, before DEV protections are set up for the rest of memory. The amount of space required for this will limit the maximum size of the SL image, and will depend on SL implementation. SKINIT sets the ESP register to the appropriate top-of-stack value (EAX + 10000h).
Figure 15 -14 illustrates the layout of the SLB, showing where EAX and ESP point after SKINIT 
execution. Labels in italics indicate suggested uses; other labels reflect required items.
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Figure 15-14. SLB Example Layout
15.27.4  Trusted Platform Module
The trusted platform module, or TPM, is an essential part of full trusted system initialization. This 
device is attached to an LPC link off the system I/O hub. It recognizes special SKINIT transactions, receives the SL image sent by SKINIT and verifies the signature. Based on the outcome, the device decides whether or not to cooperate with the SL or subsequent SK. The TPM typically contains sealed storage containing cryptographic keys and other high-security information that may be specific to the platform.SL Stack
SL Code
and
Static Data
SL Entry Point
SL Header
Length EP Offset
31 16 15 064 KBSL Runtime
Data Area
SL Image
(Hash Area)Post SKINIT ESP
Post SKINIT EAX
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15.27.5  System Interface, Memory Controller and I/O Hub Logic
SKINIT uses special support logic in the processor’s system interface unit, the internal controller and 
the I/O hub to which the TPM is attached. SKINIT uses special transactions that are unique to SKINIT, along with this support logic, designed to securely transmit the SL Image to the TPM for validation.
The use of this special protocol is intended to allow the TPM to detect true execution, as opposed to 
emulation, of a trusted Secure Loader, which in turn provides a means for verifying the subsequent loading and startup of a trusted Security Kernel.
15.27.6  SKINIT Operation
The SKINIT instruction is intended to be used primarily in normal mode prior to the VMM taking 
control.
SKINIT takes the physical base address of the SLB as its only input operand in EAX, and performs the 
following steps:
1. Reinitialize processor state in the same manner as for the INIT signal, then enter flat 32-bit
protected mode with paging off. The CS selector is set to 8h and CS is read only. The SS selector
is set to 10h and SS is read/write and expand-up. The CS and SS bases are cleared to 0 and limitsare set to 4G. DS, ES, FS and GS are left as 16-bit real mode segments and the SL must reloadthese with protected mode selectors having appropriate GDT entries before using them. Initializeddata in the SLB may be referenced using the SS segment override prefix until DS is reloaded. Thegeneral purpose registers are cleared except for EAX, which points to the start of the secureloader, EDX, which contains model, family and stepping information, and ESP, which containsthe initial stack pointer for the secure loader. Cache contents remain intact, as do the x87 and SSEcontrol registers. Most MSRs also retain their values, except those which might compromiseSVM protections. The EFER MSR, however, is cleared. The DPD, R_INIT and DIS_A20M flagsin the VM_CR register are unconditionally set to 1.
2. Form the SLB base address by clearing bits 15:0 of EAX (EAX is updated), and enable the
SL_DEV protection mechanism (see Section 15.24.8) to protect the 64-Kbyte region of physicalmemory starting at the SLB base address from any device access. 
3. In multiprocessor operation, perform an interprocessor handshake as described in
Section 15.27.8.
4. Read the SL image from memory and transmit it to the TPM in a manner that cannot be emulated
by software. 
5. Signal the TPM to complete the hash and verify the signature. If any failures have occurred along
the way, the TPM will conclude that no valid SL was started.
6. Clear the Global Interrupt Flag. This disables all interrupts, including NMI, SMI and INIT and
ensures that the subsequent code can execute atomically. If the processor enters the shutdownstate (due to a triple fault for instance) while GIF is clear, it can only be restarted by means of aRESET.
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7. Update the ESP register to point to the first byte beyond the end of the SLB (SLB base + 65536),
so that the first item pushed onto the stack by the SL will be at the top of the SLB.
8. Add the unsigned 16-bit entry point offset value from the SLB to the SLB base address to form
the SL entry point address, and jump to it.
The validation of the SL image by the TPM is a one-way transaction as far as SKINIT is concerned. It 
does not depend on any response from the TPM after transferring the SL image before jumping to the SL entry point, and initiates execution of the Secure Loader unconditionally. Because of the processor initialization performed, SKINIT does not honor instruction or data breakpoint traps, or trace traps due to EFLAGS.TF.
Pending interrupts.  Device interrupts that may be pending prior to SKINIT execution due to 
EFLAGS.IF being clear, or that assert during the execution of SKINIT, will be held pending until software subsequently sets GIF to 1. Similarly, SMI, INIT and NMI interrupts that assert after the start of SKINIT execution will also be held pending until GIF is set to 1.
Debug Considerations.  SKINIT automatically disables various implementation-specific hardware 
debug features. A debug version of the SL can reenable those features by clearing the VM_CR.DPD flag immediately upon entry.
15.27.7  SL Abort
If the SL determines that it cannot properly initialize a valid SK, it must cause GIF to be set to 1 and 
clear the VM_CR MSR to re-enable normal processor operation. 
15.27.8  Secure Multiprocessor Initialization
The following standard APIC features are used for secure MP initialization:
•The concept of a single Bootstrap Processor (BSP) and multiple Application Processors (APs).
•The INIT interprocessor interrupt (IPI), which puts the target processors into a halted state (INIT
state) which is responsive only to a subsequent Startup IPI. 
•The Startup IPI causes target processors to begin execution at a location in memory that isspecified by the Boot Processor and conveyed along with the Startup IPI. The operation of theprocessor in response to a Startup IPI is slightly modified to support secure initialization, asdescribed below.
A Startup IPI normally causes an AP to start execution at a location provided by the IPI. To support secure MP startup, each AP responds to a startup IPI by additionally clearing its GIF and setting the DPD, R_INIT and DIS_A20M flags in the VM_CR register
 if, and only if, the BSP has indicated that 
it has executed an SKINIT. All other aspects of Startup IPI behavior remain unchanged.
Software Requirements for Secure MP initialization.  The driver that starts the SL must execute on 
the BSP. Prior to executing the SKINIT instruction, the driver must save any processor-specific system register contents to memory for restoration after reinitialization of the APs. The driver should also put all APs in an idle state. The driver must first confirmed that all APs are idle and then it must issue an 
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INIT IPI to all APs and wait for its local APIC busy indication to clear. This places the APs into a 
halted state which is responsive only to a subsequent Startup IPI. APs will still respond to snoops for cache coherency. The driver may execute SKINIT at any time after this point. Depending on processor implementation, a fixed delay of no more than 1000 processor cycles may be necessary before executing SKINIT to ensure reliable sensing of APIC INIT state by the SKINIT.
AP Startup Sequence.  While the SL starts executing on the BSP, the APs remain halted in APIC

AP Startup Sequence.  While the SL starts executing on the BSP, the APs remain halted in APIC 
INIT state. Either the SL or the SK may issue the Startup IPI for the APs at whatever point is deemed appropriate. The Startup IPI conveys an 8-bit vector specified by the software that issues the IPI to the APs. This vector provides the upper 8 bits of a 20-bit physical address. Therefore, the AP startup code must reside in the lower 1Mbyte of physical memory—with the entry point at offset 0 on that particular page. 
In response to the Startup IPI, the APs start executing at the specified location in 16-bit real mode. This 
AP startup code must set up protections on each processor as determined by the SL or SK. It must also set GIF to re-enable interrupts, and restore the pre-SKINIT system context (as directed by the SL or SK executing on the BSP), before resuming normal system operation.
The SL must ensure the integrity of the AP startup sequence, for example by including the startup code 
in the hashed SL image and setting up DEV protection for it before copying it to the desired area. The AP startup code does not need to (and should not) execute SKINIT. Care must also be taken to avoid issuing another INIT IPI from any processor after the BSP executes SKINIT and before all APs have received a Startup IPI, as this could compromise the integrity of AP initialization. 
Pending interrupts.  Device interrupts that may be pending on an AP prior to the APIC INIT IPI due 
to EFLAGS.IF being clear, or that assert any time after the processor has accepted the INIT IPI, will be held pending through the subsequent Startup IPI, and remain pending until software sets GIF to 1 on that AP. Similarly, SMI, INIT, and NMI interrupts that assert after the processor has accepted the INIT IPI will also be held pending until GIF is set to 1.
Aborting MP initialization.  In the event that the SL or SK on the BSP decides to abort SVM system 
initialization for any reason, the following clean-up actions must be performed by SL code executing on each processor before returning control to the original operating environment:
•The BSP and all APs that responded to the Startup IPI must restore GIF and clear VM_CR on each
processor for normal operation. 
•For each processor that has a distinct memory controller associated with it, the SL_DEV_EN flagin the DEV control register must be cleared in order to restore normal device accessibility to the64KB SL memory range.
Any secure context created by the SL that should not be exposed to untrusted code should be cleaned up as appropriate before these steps are taken.
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15.28 Security Exception (#SX)
The Security Exception fault signals security-sensitive events that occur while executing the VMM, in 
the form of an exception so that the VMM may take appropriate action. (A VMM would typically intercept comparable sensitive events in the guest.) Currently, the only use of the #SX is to redirect external INITs into an exception so that the VMM may — among other possibilities — destroy sensitive information before re-issuing the INIT, this time without redirection. The INIT redirection is controlled by the VM_CR.R_INIT bit. (See “INIT Support” on page 534 for more details on INIT and #SX behavior). Note that INIT is gated by the Global Interrupt Flag (GIF), and so will be held pending if asserted while GIF is 0. When GIF transitions to 1, INIT will either take effect or be redirected to 
#SX, depending on the state of R_INIT.
The #SX exception dispatches to vector 30, and behaves like other fault-class exceptions such as 
General Protection Fault (#GP). The #SX exception pushes an error code. The only error code currently defined is 1, and indicates redirection of INIT has occurred.
The #SX exception is a contributory fault.
15.29 Advanced Virtual Interrupt Controller
The AMD Advanced Virtual Interrupt Controller (A VIC) is an important enhancement to AMD 
Virtualization™ Technology (AMD-V). In a virtualized environment, A VIC presents to each guest a virtual interrupt controller that is compliant with the local Advanced Programmable Interrupt Controller (APIC) architecture. See Chapter 16, “Advanced Programmable Interrupt Controller (APIC),” on page 620 for a detailed description of APIC.
15.29.1  Introduction
In a virtualized computer system, each guest operating system needs access to an interrupt controller to 
send and receive device and interprocessor interrupts. When there is no hardware acceleration, it falls to the virtual machine monitor (VMM) to intercept guest-initiated attempts to access the interrupt controller registers and provide direct emulation of the controller system programming interface allowing the guest to initiate and process interrupts. The VMM uses the underlying physical and virtual interrupt delivery mechanisms of the system to deliver interrupts from I/O devices and virtual processors to the target guest virtual processor and to handle any required end of interrupt processing. 
Given the high rate of device and interprocessor interrupt generation in certain scenarios, in particular 
on server-class systems, the emulation of a local APIC can be a significant burden for the VMM. The A VIC architecture addresses the overhead of guest interrupt processing in a virtualized environment by applying hardware acceleration to the following components of interrupt processing:
•Providing a guest operating system access to performance-critical interrupt controller registers
•Initiating intra- and inter-processor interrupts (IPIs) in and between virtual processors in a guest
Software-initiated Interrupts.  Modern operating systems use software interrupts (self-IPIs) to 
implement software event signaling, inter-process communication and the scheduling of deferred 
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processing. System software sets up and initiates these interrupts by writing to control registers of the 
local APIC. A VIC hardware reduces VMM overhead by providing hardware assist for many of these operations.
Inter-processor Interrupts.  Inter-processor interrupts (IPIs) are used extensively by modern 
operating systems to handle communication between processor cores within a machine (or, in a virtualized environment, between virtual processors within a virtual machine). IPIs are also employed to provide signaling and synchronization for operations such as cross-processor TLB invalidations (also known as TLB shootdowns). A VIC provides hardware mechanisms that deliver the interrupt to the virtual interrupt controller of the target virtual processor without VMM intervention.
Device Interrupts. Acceleration of the delivery of virtual interrupts from I/O devices to virtual 
processors is not addressed directly by A VIC hardware. This acceleration would be provided by an I/O 
memory management unit (IOMMU). The A VIC architecture is compatible with the AMD I/O Memory Management Unit (IOMMU). For more information on the IOMMU architecture, see AMD 
I/O Virtualization Technology (IOMMU) Specification (order #48882). See “Device Interrupts” on page 577 for further details of device interrupt handling under the A VIC extension.
The following subsections describe the A VIC architecture in detail. 
15.29.2  Local APIC Register Virtualization
The system programming interface for the local APIC comprises a set of memory-mapped registers. In 
a non-virtualized environment, system software directly reads and writes these registers to configure 
the interrupt controller and initiate and process interrupts. In a virtualized environment, each guest operating system still requires access to this system programming interface but does not own the underlying interrupt processing hardware. To provide this facility to the guest operating system, VMM-level software emulates the local APIC for each guest virtual processor.
The A VIC architecture provides an image of the local APIC called the guest virtual APIC (guest 
vAPIC) in the guest physical address (GPA) space of each virtual processor when the virtual machine for the guest is instantiated. This image is backed by a page in the system physical address (SPA) space called a vAPIC backing page. The backing page remains pinned in system memory as long as the virtual machine persists, even when the specific virtual processor associated with the backing page is not running. Accesses to the memory-mapped register set by the guest are redirected by A VIC hardware to this backing page.
The VMM reads configuration, control, and command information written by the guest from the

The VMM reads configuration, control, and command information written by the guest from the 
backing page and writes status information to this page for the guest to read. The guest is allowed to read most registers directly without the need for VMM intervention. Most writes are intercepted allowing the VMM to process and act on the configuration, control, and command data from the guest. However, for certain frequently used command and control operations, specific hardware support allows the guest to directly initiate interrupts and complete end of interrupt processing, eliminating the need for VMM intervention in the execution of performance-critical operations.
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15.29.3  AVIC Backing Page
A VIC hardware detects attempted accesses by the guest to its local APIC register set and redirects 
these accesses to the vAPIC backing page. This is illustrated in the figure below.
Figure 15-15. vAPIC Backing Page Access
To correctly redirect guest accesses of the guest vAPIC registers to the vAPIC backing page, the hard -
ware needs two addresses. These are:
•vAPIC backing page address in the SPA space
•Guest vAPIC base address (APIC BAR) in the GPA space
System software is responsible for setting up a translation in the nested page table granting guest read 
and write permissions for accesses to the vAPIC Backing Page in SPA space. A VIC hardware walks the nested page table to check permissions, but does not use the SPA address specified in the leaf page table entry. Instead, A VIC hardware finds this address in the A VIC_BACKING_PAGE pointer field of the VMCB.v2_AVIC_diagram2.epsAVIC_BACKING_PAGE ptr
V_APIC_BARVMCBSystem Physical 
Address SpaceMemory Mapped Image
Guest 
vAPIC 
RegistersvAPIC Backing Page
Emulated 
vAPIC 
Registers
GPA to SPA 
MappingRegister-level 
Permissions FilterBacking 
Page SPAGuest vAPIC 
Page GPA
Guest vAPIC Page GPA Backing Page SPAallow* trap
faultGuest Physical 
Address Space
AVIC Hardware
*Writes to specific registers can initiate AVIC hardware actions
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The VMM initializes the backing page with appropriate default APIC register values including items 
such as APIC version number. The vAPIC backing page address and the guest vAPIC base address are stored in the VMCB fields A VIC_BACKING_PAGE pointer and V_APIC_BAR respectively.
System firmware initializes the value of guest vAPIC base address (and VMCB.V_APIC_BAR) to 
FEE0_0000h. This is the address where the guest operating system expects to find the local APIC register set when it boots. If the guest attempts to relocate the local APIC register base address in GPA space by writing to the APIC Base Address Register (MSR 0000_001Bh), the VMM should intercept the write to update the V_APIC_BAR field of the guest’s VMCB(s) and the GPA part of translation in the virtual machine’s nested page tables.
The vAPIC backing page must be present in system physical memory for the life of the guest VM 
because some fields are updated even when the guest is not running.
15.29.3.1  Virtual APIC Register Accesses
A VIC hardware detects attempted guest accesses to the vAPIC registers in the backing page. These 
attempted accesses are handled by the register-level permissions filter in one of three ways:
•Allow—The access to the backing page is allowed to complete. Writes update the backing page 
value, while reads return the current value. In certain cases, a write results in specific hardware-based acceleration actions (summarized in Table 15 -22 and described below).
•Fault—The processor performs an SVM intercept before the access. Causes a #VMEXIT.
•Trap— The processor performs an SVM intercept immediately after the access completes. Causes a #VMEXIT.
The details of this behavior for each of these registers are summarized in the following table.
Table 15-22. Guest vAPIC Register Access Behavior
xAPIC 
Register 
Offsetx2APIC MSR 
AddressRegister NameA VIC and x2A VIC Register Access 
Behavior
20h 802h APIC ID RegisterRead: Allowed
Write: #VMEXIT (trap)
30h 803h APIC Version RegisterRead: AllowedWrite: #VMEXIT (fault)
80h 808h Task Priority Register (TPR)Read: AllowedWrite: Accelerated by A VIC
90h 809h Arbitration Priority Register (APR)Read: #VMEXIT (fault)Write: #VMEXIT (fault)
A0h 80Ah Processor Priority Register (PPR)Read: AllowedWrite: #VMEXIT (fault)
B0h 80Bh End of Interrupt Register (EOI)Read: AllowedWrite: Accelerated by A VIC for edge-triggered interrupts or #VMEXIT (trap) for level triggered interrupts
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C0h - Remote Read RegisterRead: Allowed
D0h 80Dh Logical Destination RegisterRead: AllowedWrite: #VMEXIT (trap)
E0h - Destination Format RegisterRead: AllowedWrite: #VMEXIT (trap)
F0h 80Fh Spurious Interrupt Vector RegisterRead: AllowedWrite: #VMEXIT (trap)
100h–170h 810h-817h In-Service Register (ISR)Read: AllowedWrite: #VMEXIT (fault)
180h–1F0h 818h-81Fh Trigger Mode Register (TMR)Read: AllowedWrite: #VMEXIT (fault)
200h–270h 820h-827h Interrupt Request Register (IRR)Read: AllowedWrite: #VMEXIT (fault)
280h 828h Error Status Register (ESR)Read: AllowedWrite: #VMEXIT (trap)
300h 830hInterrupt Command Register (APIC: low bits [31:0], x2APIC all bits [63:0])Read: AllowedWrite: Accelerated by A VIC or #VMEXIT (trap) for advanced functions.
310h -Interrupt Command Register High (APIC only: high bits [63:32])Read: Allowed (A VIC)
Write: Allowed (A VIC)
320h 832h Timer Local Vector Table EntryRead: Allowed
330h 833h Thermal Local Vector Table EntryRead: AllowedWrite: #VMEXIT (trap)
340h 834hPerformance Counter Local Vector Table EntryRead: AllowedWrite: #VMEXIT (trap)
350h 835h Local Interrupt 0 Vector Table EntryRead: AllowedWrite: #VMEXIT (trap)
360h 836h Local Interrupt 1 Vector Table EntryRead: AllowedWrite: #VMEXIT (trap)
370h 837h Error Vector Table EntryRead: AllowedWrite: #VMEXIT (trap)
380h 838h Timer Initial Count RegisterRead: AllowedWrite: #VMEXIT (trap)
390h 839h Timer Current Count RegisterRead: #VMEXIT (fault)Write: #VMEXIT (fault)
3E0h 83Eh Timer Divide Configuration RegisterRead: AllowedWrite: #VMEXIT (trap)Table 15-22. Guest vAPIC Register Access Behavior (continued)
xAPIC 
Register 
Behavior
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Accesses to any other register locations not explicitly defined in this table are allowed to read and 
write the backing page.
All vAPIC registers are 32-bits wide and are located at 16-byte aligned offsets. The results of an 
attempted read or write of any bytes in the range [register_offset + 4:register_offset + 15] are undefined.
Guest writes to the Task Priority Register (TPR) and specific usage cases of writes to the End of 
Interrupt (EOI) Register and the Interrupt Command Register Low (ICRL) cause specific hardware actions. A VIC hardware allows guest writes to the Interrupt Command Register High (ICRH) since the writing of this register has no immediate hardware side-effect. A VIC hardware maintains and uses the value in the Processor Priority Register (PPR) to control the delivery of interrupts to guest virtual processors. The following sections discuss the handling of accesses by the guest to these registers in the vAPIC backing page.
Task Priority Register (TPR).  When the guest operating system writes to the TPR, the value is 
updated in the backing page and the upper 4 bits of the value are automatically copied by the hardware 
to the V_TPR value in the VMCB. All reads from the TPR location return the value from the vAPIC backing page. Also, any TPR accesses using the MOV CR8 semantics update the backing page and V_TPR values.- 83Fh Self IPI Register (x2APIC only)Read: #GP in guest (x2A VIC)
Write: Allowed (x2A VIC)
400h 840h Extended APIC Feature RegisterRead: #VMEXIT (fault)Write: #VMEXIT (fault)
410h 841h Extended APIC Control RegisterRead: #VMEXIT (fault)Write: #VMEXIT (fault)
420h 842hSpecific End of Interrupt Register(SEOI)Read: #VMEXIT (fault)Write: #VMEXIT (fault)
480h–4F0h 848h-84Fh Interrupt Enable Registers (IER)Read: #VMEXIT (fault)Write: #VMEXIT (fault)
500h-530h 850h-853hExtended Interrupt [3:0] Local Vector 
Table RegistersCPUID Fn8000_000A_EDX[27]=1:
Read: AllowedWrite: #VMEXIT (trap)CPUID Fn8000_000A_EDX[27]=0:Read: #VMEXIT (fault)Write: #VMEXIT(fault)
540h-FFFh - Extended RegistersRead: #VMEXIT (fault)
Write: #VMEXIT (fault)Table 15-22. Guest vAPIC Register Access Behavior (continued)
xAPIC 
Register 
Behavior
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The priority value stored in CR8 and V_TPR are not the same format as the APIC TPR register. Only 
the Task Priority bits of are maintained in the lower 4 bits of CR8 and V_TPR. The Task Priority Sub-class value is not stored. Writes to the memory-mapped TPR register update bits 3:0 of CR8 and 
V_TPR and writes to CR8 update the TPR backing page value bits 7:4 while bits 3:0 are set to zero.
Figure 15-16. Virtual APIC Task Priority Register Synchronization

xAPIC 
Register 
Behavior
The synchronization between the Task Priority field of the TPR and the Task Priority field of CR8 is normal local APIC behavior which is emulated by A VIC. For more information on the APIC, see Chapter 16, “Advanced Programmable Interrupt Controller (APIC),” on page 620.
Processor Priority Register (PPR).  Writes to the processor priority register by the guest cause a 
#VMEXIT without updating the value in the backing page. A VIC hardware maintains the PPR value in the backing page. A VIC hardware updates the PPR value in the backing page when either the TPR value or the highest in-service interrupt changes. This value is used to control the delivery of virtual interrupts to the guest. PPR reads by the guest are allowed.
End of Interrupt (EOI) Register.  When the guest writes to the EOI register address, A VIC 
hardware clears the highest priority in-service interrupt (ISR) bit in the backing page and re-evaluates the interrupt state to determine if another pending interrupt should be delivered. If the highest priority in-service interrupt is set to level mode (in the corresponding TMR bit), the EOI write causes a #VMEXIT to allow the VMM to emulate the level-triggered behavior.
Interrupt Command Register Low (ICRL).  Writes to the ICRL register have the side-effect of 
initiating the generation of an interprocessor interrupt (IPI) based on the values written to the fields in both the ICRL and ICRH registers. A VIC hardware handles the generation of IPIs when the specified Message Type is Fixed (also known as fixed delivery mode) and the Trigger Mode is edge-triggered. The hardware also supports self and broadcast delivery modes specified via the Destination Shorthand (DSH) field of the ICRL. Logical and physical APIC ID formats are supported. All other IPI types cause a #VMEXIT. For more information on A VIC’s handling of IPI commands, see “Inter-processor Interrupts” on page 563.Task PriorityTask Priority 
Subclass
Reserved Task PriorityTPR
CR8 / V_TPR74 0 3
74 0 3
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15.29.4  VMCB Changes for AVIC
The following paragraphs provide an overview of new VMCB fields defined as part of the A VIC 
15.29.4.1  VMCB Virtual Interrupt Control Word
A VIC adds the A VIC Enable bit to the VMCB virtual interrupt control word at offset 60h. x2A VIC 
mode, described in Section 15.29.10 on page 582, adds x2A VIC Mode Enable.
A VIC Enable—Virtual Interrupt Control, Bit 31.  The A VIC hardware support may be enabled on 
a per virtual processor basis. This bit determines whether or not A VIC is enabled for a particular virtual processor. Any guest configured to use A VIC must also enable nested paging. Enabling A VIC implicitly disables the V_IRQ, V_INTR_PRIO, V_IGN_TPR, and V_INTR_VECTOR fields in the VMCB Control Word. Enabling A VIC also affects CR8 behavior independent of V_INTR_MASKING enable (bit 24): writes to CR8 affect the V_TPR and update the backing page and reads from CR8 return V_TPR.
x2A VIC Mode Enable—Virtual Interrupt Control, Bit 30 . The x2APIC MSR interface 
virtualization enable. When this bit is set to 1 on a VMRUN, A VIC Enable also has to be set to 1. If not 
the VMRUN fails with a VMEXIT_INV ALID error code.
When A VIC is enabled (bit 31 set to 1), x2A VIC Mode Enable (bit 30) determines A VIC mode. If the 
x2A VIC bit is cleared to 0, xA VIC virtualization mode is enabled (used for MMIO local APIC register Table 15-23. Virtual Interrupt Control (VMCB offset 60h)
VMCB 
offsetBit(s) Field Name Description
060h 7:0 V_TPR Virtual TPR for the guest 1 2
8 V_IRQ If nonzero; virtual INTR is pending 2 3
15:9 Reserved, SBZ —
19:16 V_INTR_PRIO Priority for virtual interrupt3
20 V_IGN_TPR If nonzero, the current virtual interrupt ignores the virtual TPR3
23:21 Reserved, SBZ —
24 V_INTR_MASKING Virtualized masking of INTR interrupts
25 Reserved, SBZ —
30 x2 A VIC Mode Enable If set, selects x2A VIC mode.
31 A VIC Enable If set, enables A VIC
39:32 V_INTR_VECTOR Vector to use for this interrupt3
63:40 Reserved, SBZ —
Note(s):
1.  Bits 3:0 are used for the 4-bit virtual TPR value; bits 7:4 are Reserved, SBZ.2.  This value is written back to the VMCB at #VMEXIT.3.  This field is ignored on VMRUN when AVIC is enabled.
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interface). If the x2A VIC bit is set to 1, x2A VIC virtualization mode is enabled (used for MSR local 
APIC register interface).
15.29.4.2  AVIC VMCB Fields
A VIC utilizes a number of formerly reserved locations in the VMCB. Table 15 -24 below lists the new 
fields defined by the architecture.
These fields are discussed further in the following paragraphs:
V_APIC_BAR—VMCB, Offset 098h.  This entry is used to hold a copy of guest physical base 
address of its local APIC register block. The guest can change the GPA of its local APIC register block by writing to the guest version of the APIC Base Address Register (MSR 0000_001Bh). Writes to this MSR are intercepted by the VMM and the value is used to update the GPA in the nested page table entry for the vAPIC backing page and the value to be saved in this field of the VMCB.
APIC_BACKING_Page Pointer—VMCB, Offset 0E0h.  This is a 52-bit HPA pointer to the vAPIC 
backing page for this virtual processor. The vAPIC backing page is described in more detail in the following section.
Logical APIC Table Pointer—VMCB, Offset 0F0h.  This is a 52-bit HPA pointer to the Logical 
APIC ID Table for the virtual machine containing this virtual processor. This table is described in more detail in the following section. Table 15-24. New VMCB Fields Defined by AVIC
VMCB 
OffsetBit(s) Field Name Description
098h63:52 Reserved, SBZ —
51:12 V_APIC_BAR Bits 51:12 of the GPA of the guest vAPIC register bank
11:0 Reserved, SBZ —
0E0h63:52 Reserved, SBZ —
51:12 A VIC_BACKING_PAGE Pointer Bits 51:12 of HPA of the vAPIC backing page
0F0h63:52 Reserved, SBZ —
51:12 A VIC_LOGICAL_TABLE Pointer Bits 51:12 of HPA of the Logical APIC Table11:0 Reserved, SBZ —
0F8h63:52 Reserved, SBZ —
51:12A VIC_PHYSICAL_TABLE 
PointerBits 51:12 of HPA for the Physical APIC Table
11:8 Reserved, SBZ —
7:0 A VIC_PHYSICAL_MAX_INDEX Index of the last guest physical core ID for this guest
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Physical APIC Table Pointer—VMCB, Offset 0F8h.  This is a 52-bit HPA pointer to the Physical 
APIC ID Table for the virtual machine containing this virtual processor. This table is described in more detail in the following section.
A VIC_PHYSICAL_MAX_INDEX—VMCB, Offset 0F8h.  Bits 7:0. This 8-bit value provides the 
index of the last guest physical core ID for this guest.
15.29.4.3  Physical Address Pointer Restrictions
All of the physical addresses in the previous sections must point to legal, implementation-supported 
physical address ranges. These pointers are evaluated on VMRUN and cause a #VMEXIT if they are outside of the legal range. These memory ranges must be mapped as write-back cacheable memory type. 
All the addresses point to 4-Kbyte aligned data structures. Bits 11:0 are reserved (except for offset 
0F8h) and should be set to zero. The lower 8 bits of offset 0F8h are used for the field A VIC_PHYSICAL_MAX_INDEX. VMRUN fails with #VMEXIT(VMEXIT_INV ALID) if A VIC_PHYSICAL_MAX_INDEX is greater than 255 in xA VIC mode or greater than 511 in x2A VIC mode.
Multiprocessor VM requirements. When running a VM which has multiple virtual CPUs, and the 
VMM runs a virtual CPU on a core which had last run a different virtual CPU from the same VM, 
regardless of the respective ASID values, care must be taken to flush the TLB on the VMRUN using a TLB_CONTROL value of 3h. Failure to do so may result in stale mappings misdirecting virtual APIC accesses to the previous virtual CPU's APIC backing page.
15.29.5  AVIC Memory Data Structures
The A VIC architecture defines three new memory-resident data structures. Each of these structures is 
defined to fit exactly in one 4-Kbyte page. Future implementations may expand the size.
15.29.5.1  Virtual APIC Backing Page
Each virtual processor in the system is assigned a virtual APIC backing page (vAPIC backing page). 
Accesses by the guest to the local APIC register block in the guest physical address space are redirected to the vAPIC backing page in system memory. The vAPIC backing page is used by A VIC hardware and the VMM to emulate the local APIC. See “Virtual APIC Register Accesses” on page 565 for a detailed description.
15.29.5.2  Physical APIC ID Table
The physical APIC ID table is set up and maintained by the VMM and is used by the hardware to 
locate the proper vAPIC backing page to be used to deliver interrupts based on the guest physical APIC ID. One physical APIC ID table must be provided per virtual machine.
The guest physical APIC ID is used as an index into this table. Each entry contains a pointer to the

The guest physical APIC ID is used as an index into this table. Each entry contains a pointer to the 
virtual processor’s vAPIC backing page, a bit to indicate whether the virtual processor is currently scheduled on a physical core, and if so, the physical APIC ID of that core.
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The length of this table is fixed at 4 Kbytes allowing a maximum of 512 virtual processors per virtual 
machine. However, in this version of the architecture the maximum number of virtual processors per guest is limited to 256. The physical ID table can be populated in a sparse manner using the valid bit to indicate assigned IDs. The index of the last valid entry is stored in the VMCB A VIC_PHYSICAL_MAX_INDEX field.
A pointer to this table is maintained in the VMCB. Because there is a single Physical APIC ID Table 
per virtual machine, the value of this pointer is the same for every virtual processor within the virtual machine.
Each entry in the table has the following format:
Figure 15-17. Physical APIC ID Table Entry
Note that the IR bit, when set, indicates that the VMM has assigned a physical core to host this virtual 
processor. The bit does not differentiate between a physical processor running in guest mode (actively executing guest software) or in host mode (having suspended the execution of guest software). 63 62 61 52 51 32
V IR Reserved Backing Page Pointer[51:32]
31 1211 0
Backing Page Pointer[31:12] Host Physical APIC ID
Table 15-25. Physical APIC ID Table Entry Fields
Bit(s) Field Name Description
63 VValid bit. When set, indicates that this entry contains a valid vAPIC backing page pointer. 
If cleared, this table entry contains no information.
62 IRIsRunning. This bit indicates that the corresponding guest virtual processor is currently scheduled by the VMM to run on a physical core.
61:52 —  Reserved, SBZ. Should always be set to zero.
51:12 Backing Page Pointer 4-Kbyte aligned HPA of the vAPIC backing page for this virtual processor.
11:0 Host Physical APIC IDPhysical APIC ID of the physical core allocated by the VMM to host the guest virtual processor. This field is not valid unless the IsRunning bit is set.
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The Physical APIC ID Table occupies the lower half of a single 4-Kbyte memory page, formatted as 
follows:
Figure 15-18. Physical APIC Table in Memory
Since a destination of FFh is used to specify a broadcast, physical APIC ID FFh is reserved. The upper 2048 bytes of the table are reserved and should be set to zero.
15.29.5.3  Logical APIC ID Table
In addition to the Physical APIC ID Table, each guest VM is assigned a Logical APIC ID Table. This 
table is used to lookup the guest physical APIC ID for logically addressed interrupt requests. Each entry of this table provides the guest physical APIC ID corresponding to a single logically addressed APIC. Note that this implies that the logical ID of each vAPIC must be unique. The entries of this table are selected using the logical ID and interpreted differently depending upon logical APIC addressing mode of the guest.
If the guest attempts to change the logical ID of its APIC, the VMM must reflect this change in the 
Logical APIC ID Table. A VIC hardware supports the fixed interrupt message type targeting one or more logical destinations. The hardware also supports self and broadcast delivery modes specified via the Destination Shorthand (DSH) field of the ICRL. Any other message types must be supported through emulation by the VMM. 2CPhysical APIC Entry 254
Physical APIC Entry 253
Physical APIC Entry 252
Physical APIC Entry 1
Physical APIC Entry 0 08162032204020484088
2024
2016
2008 Physical APIC Entry 251
Physical APIC Entry 2Reserved
Reserved
02251252253254255
1Guest 
Physical 
APIC ID
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A pointer to this table is maintained in the VMCB. Because there is a single Logical APIC ID Table 
For all logical destination modes, the table entries have the following format:
Figure 15-19. Logical APIC ID Table Entry
Logical APIC ID Table Format for Flat Mode. When running in flat mode, A VIC expects the 
logical APIC ID table to be formatted as shown in Figure 15 -20 below. This mode uses only the first 8 
entries of the table. Although the logical APIC ID is an eight bit value, supported encodings must be of 
the form 2
i, where i = 0 to 7. In the figure the value i is used and represents the index into the table. The 
actual byte offset into the table for a given logical APIC ID l_apic_id  is 4 * log2(l_apic_id). 
The Logical APIC ID Table is not used by A VIC hardware in x2A VIC mode. Instead, the destination logical ID is derived from the target x2APIC ID as follows: Logical x2APICID = (X2APICID[19:4] << 16) | (1 << x2APICID[3:0]).31 30 8 7 0
V Reserved Guest Physical APIC ID
Table 15-26. Logical APIC ID Table Entry Fields
31 VValid Bit. When set, indicates that this table entry contains a valid physical APIC ID. If 
cleared, this table entry contains no information.
30:8 — Reserved, SBZ. Should always be set to zero.
7:0 Guest Physical APIC IDGuest physical APIC ID corresponding to the local APIC selected when logically addressed.
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Figure 15-20. Logical APIC ID Table Format, Flat Mode
Logical APIC ID Table Format for Cluster Mode.  In cluster mode, bits 7:4 of the logical APIC ID 
represent the cluster number and bits 3:0 represent the APIC index (bit encoded). The cluster number Fh (15) is reserved. Since the APIC index field is four bits, four encodings are supported for the APIC index value.
The actual byte offset into the table for a given cluster c and an APIC index apic_ix  is (16 * c) + 4 * 
log
2(apic_ix).
When running in cluster mode, A VIC expects the logical APIC ID table to be formatted as shown in 
Figure 15 -21 below. 0 02
1 4812162024284092
Entry for Logical APIC 3
Entry for Logical APIC 2
Entry for Logical APIC 1
Entry for Logical APIC 0Entry for Logical APIC 7
Entry for Logical APIC 6
Entry for Logical APIC 5
Entry for Logical APIC 4Reserved
32
34567 Logical 
APIC ID Index
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Figure 15-21. Logical APIC ID Table Format, Cluster Mode
15.29.6  Interrupt Delivery
There are two fundamental types of virtual interrupts—interprocessor interrupts (IPIs) and I/O device 
interrupts (device interrupts). An IPI is initiated when guest system software writes the ICRL register. A device interrupt is initiated by a I/O device that has been programmed by guest system software (usually a device driver) to send a message signaling an event to a specific guest physical processor. This message usually includes an interrupt vector number indicating the nature of the event.
The following sections discuss the actions taken by A VIC hardware when a virtual processor signals 
an IPI and the actions taken by I/O virtualization hardware when a device signals a virtual interrupt.
15.29.6.1  Interprocessor Interrupts
To process an IPI, A VIC hardware executes the following steps:
1. If the destination-shorthand coded in the command is 01b (i.e. self), update the IRR in the backing 
page, signal doorbell to self and skip remaining steps.
2. If destination-shorthand is non-zero, or if the destination field is FFh (i.e. broadcast), jump to 
step 4.
3. If the destination(s) is (are) logically addressed, lookup the guest physical APIC IDs for each 
logical ID using the Logical APIC ID table.
If the entry is not valid (V bit is cleared), cause a #VMEXIT.04812162024284092
Entry for Cluster 0, Logical APIC 3
Entry for Cluster 0, Logical APIC 2
Entry for Cluster 0, Logical APIC 1
Entry for Cluster 0, Logical APIC 0Entry for Cluster 1, Logical APIC 3Entry for Cluster 14, Logical APIC 1
Entry for Cluster 14, Logical APIC 0Entry for Cluster 14, Logical APIC 2Entry for Cluster 14, Logical APIC 3
Entry for Cluster 1, Logical APIC 2
Entry for Cluster 1, Logical APIC 1
Entry for Cluster 1, Logical APIC 0224236240Reserved
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If the entry is valid, but the Guest Physical APIC ID is greater than 255, cause a #VMEXIT 
(xA VIC).
If the entry is valid, but contains an invalid backing page pointer, cause a #VMEXIT.
4. Lookup the vAPIC backing page address in the Physical APIC table using the guest physical 
APIC ID as an index into the table.For directed interrupts, if the selected table entry is not valid, cause a #VMEXIT. For broadcast 
IPIs, invalid entries are ignored.
5. For every valid destination:
- Atomically set the appropriate IRR bit in each of the destinations’ vAPIC backing page.
- Check the IsRunning status of each destination.- If the destination IsRunning bit is set, send a doorbell message using the host physical core

(xA VIC).
- Check the IsRunning status of each destination.- If the destination IsRunning bit is set, send a doorbell message using the host physical core 
number from the Physical APIC ID table.
6. If any destinations are identified as not currently scheduled on a physical core (i.e., the IsRunning 
bit for that virtual processor is not set), cause a #VMEXIT.
Refer to Section 15.29.9.1, “A VIC IPI Delivery Not Completed,” on page 580 for new exit codes 
associated with the #VMEXIT exceptions listed above.
15.29.6.2  Device Interrupts
The delivery of a I/O device interrupt to a virtual processor is handled by an IOMMU with virtual 
interrupt capability. To deliver a virtual interrupt, I/O virtualization hardware executes the following steps:
1. An interrupt message arrives from the I/O device identifying the source device and interrupt 
vector number. 
2. I/O virtualization hardware uses the device ID to determine the guest physical APIC ID of the 
core that is the target of the device interrupt.
3. I/O virtualization hardware uses the guest physical APID ID to index into the Physical APIC ID 
Table to find the SPA of the vAPIC backing page. If the I/O virtualization hardware accesses an 
entry in the Physical APIC ID Table that is not valid (V bit is cleared), the I/O virtualization hardware aborts the virtual interrupt delivery and logs an error.
4. I/O virtualization hardware performs any required vector number translation.
5. I/O virtualization hardware atomically sets the bit in the IRR in the vAPIC backing page that 
corresponds to the vector.
6. If the virtual processor that is the target of the interrupt is not currently running on its assigned 
physical core, the virtual interrupt will be presented when the virtual processor is made active 
again. I/O virtualization hardware may provide additional information to the VMM about the device interrupt to aid in virtual processor scheduling decisions.
If the virtual processor that is the target of the interrupt is scheduled on a physical processor 
(indicated by the IsRunning bit of the Physical APIC ID table entry being set), I/O virtualization 
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hardware uses the host physical APIC ID in the table entry to send a doorbell signal to the 
corresponding processor core to signal that an interrupt needs to be processed.
15.29.7  AVIC CPUID Feature Flags
A CPUID feature bit is used indicate support for A VIC on a specific hardware implementation. CPUID 
Fn8000_000A_EDX[A VIC] (bit 13) = 1 indicates support for the A VIC architecture on that hardware. Additionally, CPUID Fn8000_000A_EDX[x2A VIC] (bit 18) = 1 indicates support for the A VIC architecture when the guest is using x2APIC MSR interface. 
15.29.8  New Processor Mechanisms
In order to support the direct injection of interrupts into the guest and to accelerate critical vAPIC 
functions, new hardware mechanisms are implemented in the processor.
15.29.8.1  Special Trap/Fault Handling for vAPIC Accesses
To virtualize the local APIC utilized by the guest to generate and process interrupts, all read and write 
accesses by the guest virtual processor to its local APIC registers are redirected to the vAPIC backing page. Most reads and many writes to this guest physical address range read or write the contents of memory locations within the vAPIC backing page at the corresponding offset. 
To support proper handling and emulation of the guest local APIC, the processor provides permissions 
filtering hardware (Refer to Figure 15 -15.) that detects and intercepts accesses to specific offsets 
(representing APIC registers) within the vAPIC backing page. This hardware either allows the access, blocks the access and causes a #VMEXIT (fault behavior), or allows the access and then causes a #VMEXIT (trap behavior).
Hardware directly handles the side effects of guest writes to the TPR and EOI registers. Writes to the 
ICRL register with simple functional side effects such as the generation of a directed IPI or a self-IPI request are handled directly. Values written to the ICRL defined to initiate more complex behavior cause a #VMEXIT to allow the VMM to emulate the function. A guest write to the ICRH register has no immediate hardware side effect and is allowed.
Most other write access attempts within the vAPIC register bank address range cause a #VMEXIT 
with trap or fault behavior allowing the VMM to emulate the function of that register. See Table 15 -22 
for more detail.
Reads and writes to locations within the vAPIC backing page, but outside the offset range of defined 
vAPIC registers are allowed to complete.
15.29.8.2  Doorbell Mechanism
Each core provides a doorbell mechanism that is used by other cores (for IPIs) and the IOMMU (for 
device interrupts) to signal to the VMM of the target physical core that a virtual interrupt requires 
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processing. The exact mechanism is implementation-specific, but must be protected from access from 
non-privileged software running on other cores and from direct access by an external device.
When the doorbell is received in guest mode, hardware on the receiving core evaluates the vAPIC state 
in the vAPIC backing page for the currently running virtual processor and injects the interrupt into the guest as appropriate.
Doorbell Register.  The system programming interface to the doorbell mechanism is provided via an 
MSR. Sending a doorbell signal to a another core is initiated by writing the physical APIC ID corresponding to that core to the Doorbell Register (MSR C001_011Bh). The format of this register is shown in Figure 15 -22 below.
Figure 15-22. Doorbell Register, MSR C001_011Bh
Writing to this register causes a doorbell signal to be sent to the specified physical core. The serializing semantics of WRMSR are relaxed when writing to the Doorbell Register. Any attempt to read from this register results in a #GP.
Processing of Doorbell Signals.  A doorbell signal delivered to a running guest is recognized by the 
hardware regardless of whether it can be immediately injected into the guest as a virtual interrupt. On the next VMRUN, the virtual interrupt delivery mechanism evaluates the state of the IRR register of the guest’s vAPIC backing page to find the highest priority pending interrupt and injects it if interrupt masking and priority allow.
15.29.8.3  Additional VMRUN Handling
In addition to the normal VMRUN operations, the core re-evaluates the APIC state in the vAPIC 
backing page upon entry into the guest and processes pending interrupts as necessary. Specifically:
•On VMRUN the interrupt state is evaluated and the highest priority pending interrupt indicated in 
the IRR is delivered if interrupt masking and priority allow
•Any doorbell signals received during VMRUN processing are recognized immediately after entering the guest
•When A VIC mode is enabled for a virtual processor, the V_IRQ, V_INTR_PRIO, V_INTR_VECTOR, and V_IGN_TPR fields in the VMCB are ignored.
15.29.9  AVIC Exit Codes
The A VIC architecture defines two new A VIC-related #VMEXIT events. These cases are described in 
the following sections. Assigned EXITCODE values are given in Table C-1 on page 745.63 8 7 0
Reserved, MBZ Physical APIC ID
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15.29.9.1  AVIC IPI Delivery Not Completed
An IPI could not be delivered to all targeted guest virtual processors because at least one guest virtual 
processor was not allocated to a physical core at the time. This results in a #VMEXIT with an exit code of A VIC_INCOMPLETE_IPI. Additional data associated with this #VMEXIT event is returned in the EXITINFO1 and EXITINFO2 fields.
EXITINFO1.  This field contains the values written to the vAPIC ICRH and ICRL registers.
Figure 15-23. EXITINFO1
EXITINFO2.  This field contains information describing the specific reason for the IPI delivery 
failure.
Figure 15-24. EXITINFO2
The ID field identifies the reason for the IPI delivery failure:63 32 31 0
ICRH ICRL
Table 15-27. EXITINFO1 Fields
63:32 ICRH Value written to the vAPIC ICRH register.
31:0 ICRL Value written to the vAPIC ICRL register.
63 32 31 8 7 0
ID Reserved Index
Table 15-28. EXITINFO2 Fields
63:32 ID Specific reason for the delivery failure. See Table 15 -29 for defined values.
31:8 — Reserved
7:0 IndexFor ID = 1 – 3, this field provides the index of a logical or physical table entry. 
Reserved for all other ID values.
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15.29.9.2  AVIC Access to Un-accelerated vAPIC register
A guest access to an APIC register that is not accelerated by A VIC results in a #VMEXIT with the exit

failure.
ICRH ICRL
63 32 31 8 7 0
A guest access to an APIC register that is not accelerated by A VIC results in a #VMEXIT with the exit 
code of A VIC_NOACCEL. This fault is also generated if an EOI is attempted when the highest priority in-service interrupt is set for level-triggered mode. Additional data associated with this #VMEXIT event is returned in the EXITINFO1 and EXITINFO2 fields.Table 15-29. ID Field—IPI Delivery Failure Cause
ID Cause Description Index
0 Invalid Interrupt typeThe trigger mode for the specified IPI was set to 
level or the destination type is unsupported.Reserved.
1IPI Target Not RunningIsRunning bit of the target for a Singlecast/Broadcast/Multicast IPI is not set in the physical APIC ID table.Index of the physical or logical APIC ID table entry for the target virtual processor that was not scheduled on a physical core.
2 Invalid Target in IPITarget ID invalid. This is due to one the following reasons:
•In logical mode:
cluster > max_cluster (64)cluster_id > 31 (x2A VIC)guest_physical_apic_id > 255 (xA VIC)
•In physical mode:target > max_physical (512)
•address is not present in the physical or logical ID tablesIndex of the physical or logical table 
entry for the invalid target.
3Invalid Backing Page PointerThe vAPIC Backing Page Pointer field of the Physical APIC ID Table contained an invalid physical address.For shorthand or broadcast delivery modes, index of the physical APIC ID Table containing the invalid address. For directed IPIs, index of the logical or physical APIC ID table depending on the destination mode.
4Invalid IPI VectorThe vector for the specified IPI was set to an illegal value (VEC < 16).Reserved
> 4 Reserved — Reserved
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EXITINFO1.  This field contains the offset of the un-accelerated virtual APIC register and a bit 
indicating whether a read or write operation was attempted.
Figure 15-25. EXITINFO1
EXITINFO2.  This field contains extra information for the un-accelerated operation. If the EXITINFO1 fields indicate a write to the vAPIC EOI register (offset = B0h), bits 7:0 of this value contain the number of the highest in-service vector found in the virtual APIC ISR. 
Figure 15-26. EXITINFO2
15.29.10  x2AVIC
The x2A VIC virtualization feature provides hardware acceleration for performance-sensitive APIC 
accesses when the x2APIC MSR interface is used by the guest operating system. x2A VIC support is reported by Fn8000000A_EDX[X2A VIC] (bit 14) = 1.63 33 32 31 12 11 4 3 0
Reserved
R/WReserved APIC Offset[11:4] Reserved
Table 15-30. EXITINFO1 Fields
Bits Field Name Description
63:33 — Reserved.
32 R/W If set, write was attempted. If clear, read was attempted.
31:12 — Reserved.
11:4 APIC_Offset[11:4]Offset within virtual vAPIC backing page at which read or write was attempted. 
APIC_Offset[3:0] = 0, since all registers are aligned on 16-byte boundaries.
3:0 — Reserved.
63 8 7 0
Reserved Vector
Table 15-31. EXITINFO2 Fields
63:8 — Reserved
7:0 Vector Vector for attempted EOI; otherwise undefined.
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x2A VIC mode is enabled by setting A VIC Enable (bit 31) and x2A VIC Mode Enable (bit 30) in VMCB 
offset 60h to 1. When x2A VIC mode is enabled, x2APIC MSR accesses are virtualized in a similar manner to MMIO accesses in xA VIC mode. x2APIC MSR intercept checks and access checks have higher priority than A VIC access permission checks. See Section 15.29.3.1 for x2APIC register access behavior when x2A VIC is enabled.
In x2APIC mode Interrupt Command Register Low (ICRL) and Interrupt Command Register High 
(ICRH) registers are combined into a 64-bit register and accessed through the ICR MSR (830h). In x2A VIC mode ICR MSR bits 31:0 and 63: 32 are mapped to ICRL (offset 300h) and ICRH (offset 310h) in the backing page. SELF_IPI MSR (83Fh) acceleration is handled the same way as ICR MSR acceleration.
V_APIC_BAR and Logical Destination Table are not used in x2A VIC mode.New x2A VIC mode error conditions are documented in Section 15.29.4.1, Section 15.29.4.3 and 
Table 15-30.
15.30 SVM Related MSRs
SVM uses the following MSRs for various control purposes. These MSRs are available regardless of whether SVM is enabled in EFER.SVME. For details on implementation-specific features, see the BIOS and Kernel Developer’s Guide (BKDG) or Processor Programming Reference Manual  
applicable to your product.
15.30.1  VM_CR MSR (C001_0114h)
The VM_CR MSR controls certain global aspects of SVM. The layout of the MSR is shown in 
Figure 15 -27.
Figure 15-27. Layout of VM_CR MSR (C001_0114h)
The individual fields are as follows:
•DPD—Bit 0. If set, disables the external hardware debug port and certain internal debug features.
•R_INIT—Bit 1. If set, non-intercepted INIT signals are converted into an #SX exception. 
•DIS_A20M—Bit 2. If set, disables A20 masking.
•LOCK—Bit 3. When this bit is set, writes to LOCK and SVMDIS are silently ignored. When this
bit is clear, VM_CR bits 3 and 4 can be written. Once set, LOCK can only be cleared using theSVM_KEY MSR (See Section 15.31.) This bit is not affected by INIT or SKINIT.63 5 4 3 2 1 0
Reserved, MBZ SVMDIS LOCK DIS_A20M R_INIT DPD
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•SVMDIS—Bit 4. When this bit is set, writes to EFER treat the SVME bit as MBZ. When this bit is
clear, EFER.SVME can be written normally. This bit does not prevent CPUID from reporting thatSVM is available. Setting SVMDIS while EFER.SVME is 1 generates a #GP fault, regardless ofthe current state of VM_CR.LOCK. This bit is not affected by SKINIT. It is cleared by INIT whenLOCK is cleared to 0; otherwise, it is not affected.
15.30.2  IGNNE MSR (C001_0115h)
The read/write IGNNE MSR is used to set the state of the processor-internal IGNNE signal directly. 
This is only useful if IGNNE emulation has been enabled in the HW_CR MSR (and thus the external signal is being ignored). Bit 0 specifies the current value of IGNNE; all other bits are MBZ.
15.30.3  SMM_CTL MSR (C001_0116h)
The write-only SMM_CTL MSR provides software control over SMM signals. SMM_CTL MSR is 
not supported when CPUID Fn8000_0021[NoSmmCtlMSR] is set.
Figure 15-28. Layout of SMM_CTL MSR (C001_0116h)
Writing individual bits causes the following actions:
•DISMISS—Bit 0. Clear the processor-internal “SMI pending” flag.
•ENTER—Bit 1. Enter SMM: map the SMRAM memory areas, record whether NMI was currently
blocked and block further NMI and SMI interrupts.
•SMI_CYCLE—Bit 2. Send SMI special cycle.
•EXIT—Bit 3. Exit SMM: unmap the SMRAM memory areas, restore the previous masking statusof NMI and unconditionally reenable SMI.
•RSM_CYCLE—Bit 4. Send RSM special cycle.
Writes to the SMM_CTL MSR cause a #GP if platform firmware has locked the SMM control registers by setting HWCR[SMMLOCK].
Conceptually, the bits are processed in the order of ENTER, SMI_CYCLE, DISMISS, RSM_CYCLE, 
EXIT, though only the following bit combinations may be set together in a single write (for all other combinations of more than one bit, behavior is undefined):
•ENTER + SMI_CYCLE
•DISMISS + ENTER
•DISMISS + ENTER + SMI_CYCLE
•EXIT + RSM_CYCLE63 5 4 3 2 1 0
Reserved, MBZ RSM_CYCLE EXIT SMI_CYCLE ENTER DISMISS
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The VMM must ensure that ENTER and EXIT operations are properly matched, and not nested, 
otherwise processor behavior is undefined. Also undefined are ENTER when the processor is already 
in SMM, and EXIT when the processor is not in SMM.
15.30.4  VM_HSAVE_PA MSR (C001_0117h)
The 64-bit read/write VM_HSA VE_PA MSR holds the physical address of a 4KB block of memory 
where VMRUN saves host state, and from which #VMEXIT reloads host state. The VMM software is expected to set up this register before issuing the first VMRUN instruction. 
Writing this MSR causes a #GP if:
•any of the low 12 bits of the address written are nonzero, or
•the address written is greater than or equal to the maximum supported physical address for this
15.30.5  TSC Ratio MSR (C000_0104h)
Writing to the TSC Ratio MSR allows the hypervisor to control the guest's view of the Time Stamp 
Counter. The contents of TSC Ratio MSR sets the value of the TSCRatio. This constant scales the timestamp value returned when the TSC is read by a guest via the RDTSC or RDTSCP instructions or when the TSC, MPERF, or MPerfReadOnly MSRs are read via the RDMSR instruction by a guest running under virtualization.
This facility allows the hypervisor to provide a consistent TSC, MPERF, and MPerfReadOnly rate for

This facility allows the hypervisor to provide a consistent TSC, MPERF, and MPerfReadOnly rate for 
a guest process when moving that process between cores that have a differing P0 rate. The TSCRatio does not affect the value read from the TSC, MPERF, and MPerfReadOnly MSRs when in host mode or when virtualization is disabled. System Management Mode (SMM) code sees unscaled TSC, MPERF and MPerfReadOnly values unless the SMM code is executed within a guest container. The TSCRatio value does not affect the rate of the underlying TSC, MPERF, and MPerfReadOnly counters, nor the value that gets written to the TSC, MPERF, and MPerfReadOnly MSRs counters on a write by either the host or the guest. 
The TSC Ratio MSR specifies the TSCRatio value as a fixed-point binary number in 8.32 format, 
which is composed of 8 bits of integer and 32 bits of fraction. This number is the ratio of the desired P0 frequency to be presented to the guest relative to the P0 frequency of the core (See Section 17.1, “P-State Control,” on page 657). The reset value of the TSCRatio is 1.0, which sets the guest P0 frequency to match the core P0 frequency.
Note that:
TSCFreq = Core P0 frequency * TSCRatio, so TSCRatio = (Desired TSCFreq) / Core P0 frequency.
The TSC value read by the guest is computed using the TSC Ratio MSR along with the TSC_OFFSET 
field from the VMCB so that the actual value returned is:
TSC Value (in guest) = (P0 frequency * TSCRatio * t) + VMCB.TSC_OFFSET + (Last Value Written to TSC) * TSCRatio
Where t is time since the TSC was last written via the TSC MSR (or since reset if not written)
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The layout of the TSC Ratio MSR is illustrated in the figure below.
Figure 15-29. TSC Ratio MSR (C000_0104h)
INT.  Integer Part. Bits 39:32. Integer part of TSCRatio.
FRAC.  Fractional Part. Bits 39:32. Fractional part of TSCRatio. 
TSCRatio = INT + FRAC  2-32
CPUID Fn8000_000A_EDX[TscRateMsr] =1 indicates support for the TSC Ratio MSR. See 
15.31 SVM-Lock
The SVM-Lock feature allows software to prevent EFER.SVME from being set, either unconditionally or with a 64-bit key to re-enable SVM functionality. 
Support for SVM-Lock is indicated by CPUID Fn8000_000A_EDX[SVML] = 1. On processors that 
support the SVM-Lock feature, SKINIT and STGI can be executed even if EFER.SVME=0. See descriptions of LOCK and SVMDIS bits in Section 15.30.1. When the SVM-Lock feature is not 
available, hypervisors can use the read-only VM_CR.SVMDIS bit to detect SVM (see Section 15.4).
15.31.1  SVM_KEY MSR (C001_0118h)
The write-only SVM_KEY MSR is used to create a password-protected mechanism to clear 
VM_CR.LOCK. 
When VM_CR.LOCK is zero, writes to SVM_KEY MSR set the 64-bit SVM Key value. When VM_CR.LOCK is one, writes to SVM_KEY MSR compare the written value to the SVM Key 
value; if the values match and are non-zero, the VM_CR.LOCK bit is cleared. If the values mismatch or the SVM Key value is zero, the write to SVM_KEY is ignored, and VM_CR.LOCK is unmodified. Software should read VM_CR.LOCK after writing SVM_KEY to determine whether the unlock succeeded.63 40 39 32 31 0
Reserved INT FRAC
63:40 Reserved MBZ
39:32 INT Integer Part R/W
31:0 FRAC Fractional Part R/W
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If SVM Key is zero when VM_CR.LOCK is one, VM_CR.LOCK can only be cleared by a processor 
reset.
To preserve the security of the SVM key, reading the SVM_KEY MSR always returns zero.
15.32 SMM-Lock
The SMM-Lock feature allows platform firmware to prevent System Management Interrupts (SMI) 
from being intercepted in SVM. The SmmLock bit is located in the HWCR MSR register.
15.32.1  SmmLock Bit — HWCR[0]
The SmmLock bit (bit 0) is located in the HWCR MSR (C001_0015h ). When SmmLock is clear, it can 
be set to one. Once set, the bit cannot be cleared by software and writes to it are ignored. SmmLock can 
only be cleared using the SMM_KEY MSR (see Section 15.32.2), or by a processor reset. This bit is 
not affected by INIT or SKINIT. When SmmLock is set, other SMM configuration registers cannot be written. For complete information on the HWCR register, see the BIOS and Kernel Developer’s Guide 
(BKDG) or Processor Programming Reference Manual  applicable to your product.
15.32.2  SMM_KEY MSR (C001_0119h) 
The write-only SMM_KEY MSR is used to create a password-protected mechanism to clear 
SmmLock. 
When SmmLock is zero, writes to SMM_KEY MSR set the 64-bit SMM Key value. When SmmLock is one, writes to SMM_KEY MSR compare the written value to the SMM Key value; 
if the values match and are non-zero, the SmmLock bit is cleared. If the values mismatch or the SMM Key value is zero, the write to SMM_KEY is ignored, and SmmLock is unmodified. Software should read SmmLock after writing SMM_KEY to determine whether the unlock succeeded.
If SMM_Key MSR is equal to zero when SmmLock is one, SmmLock can only be cleared by a 
processor reset.
To preserve the security of the SMM key, reading SMM_KEY MSR always returns zero.
15.33 Nested Virtualization
Hardware support for improved performance of nested virtualization, which is the act of running a 
hypervisor as a guest under a higher-level hypervisor, is provided through the features described here. These relieve the top-level hypervisor from performing certain common, high-overhead operations that can occur with nested virtualization. 
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15.33.1  VMSAVE and VMLOAD Virtualization
This feature allows the VMSA VE and VMLOAD instructions to execute in guest mode without 
causing a #VMEXIT. The VMCB address in RAX is treated as a guest physical address and is translated to a host physical address. Any page fault in attempting that translation will result in a normal #VMEXIT with a nested page fault exit code. If the translation is successful, the register state transfer to or from the VMCB will then be performed.
Support for virtualized VMSA VE and VMLOAD is indicated by CPUID Fn8000_000A_EDX[15]=1. 
When this feature is available, it must be explicitly enabled by setting bit 1 of VMCB offset 0B8h to 1. This enable bit is only recognized when the hypervisor is in 64 bit mode, nested paging is enabled and Secure Encrypted Virtualization is disabled, otherwise attempted execution of a VMLOAD or VMSA VE in the guest will result in a #VMEXIT with a VMSA VE/VMLOAD exit code.
15.33.2  Virtual GIF (VGIF)
This feature allows STGI and CLGI to execute in guest mode and control virtual interrupts in guest 
mode while still allowing physical interrupts to be intercepted by the hypervisor. The presence of the VGIF feature is indicated by CPUID Fn8000_000A_EDX[16]=1.
In order to provide this ability, two new bits are added to the VMCB field at offset 60h:
When a VMRUN is executed and VGIF is enabled, the processor uses bit 9 as the starting value of the 
virtual GIF. It then provides masking capability for when virtual interrupts are taken. STGI executed in the guest sets bit 9 of VMCB offset 60h and allows a virtual interrupt to be taken. CLGI executed in the guest clears bit 9 of VMCB offset 60h and causes the virtual interrupt to be masked. Bit 9 in the VMCB is also writeable by the hypervisor, and loaded on VMRUN and is saved on #VMEXIT.
The hypervisor can still use the STGI and CLGI intercept controls in the VMCB to intercept execution of these in the guest regardless of VGIF enablement.
15.34 Secure Encrypted Virtualization
Secure Encrypted Virtualization (SEV) is available when the CPU is running in guest mode utilizing AMD-V virtualization features. SEV enables running encrypted virtual machines (VMs) in which the code and data of the virtual machine are secured so that the decrypted version is available only within the VM itself. Each virtual machine may be associated with a unique encryption key so if data is accessed by a different entity using a different key, the SEV encrypted VM's data will be decrypted with an incorrect key, leading to unintelligible data.
It is important to note that SEV mode therefore represents a departure from the standard x86 
virtualization security model, as the hypervisor is no longer able to inspect or alter all guest code or Offset Bit Description
60h 9 VGIF value (0 – Virtual interrupts are masked, 1 – Virtual Interrupts are unmasked) 
60h 25 Virtual GIF enable for this guest (0 - Disabled, 1 - Enabled) 
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data. The guest page tables, managed by the guest, may mark data memory pages as either private or 
shared, thus allowing selected pages to be shared outside the guest. Private memory is encrypted using a guest-specific key, while shared memory is accessible to the hypervisor.
15.34.1  Determining Support for SEV
Support for memory encryption features is reported in CPUID 8000_001F[EAX] as described in

Support for memory encryption features is reported in CPUID 8000_001F[EAX] as described in 
Section 7.10.1, “Determining Support for Secure Memory Encryption,” on page 237. Bit 1 indicates 
support for Secure Encrypted Virtualization. 
When memory encryption features are present, CPUID 8000_001F[EBX] and 8000_001F[ECX] 
supply additional information regarding the use of memory encryption, such as the number of keys supported simultaneously and which page table bit is used to mark pages as encrypted. Additionally, in some implementations, the physical address size of the processor may be reduced when memory encryption features are enabled, for example from 48 to 43 bits. In this example, physical address bits 47:43 would be treated as reserved except where otherwise indicated. When memory encryption is supported in an implementation, CPUID 8000_001F[EBX] reports any physical address size reduction present. Bits reserved in this mode are treated the same as other page table reserved bits, and will generate a page fault if found to be non-zero when used for address translation.
Full CPUID details for memory encryption features may be found in V olume 3, section E.4.17.
15.34.2  Key Management
Under the memory encryption extensions defined here, each SEV-enabled guest virtual machine is 
associated with a memory encryption key, and the SME mode (if used, see Section 7.10 on page 237) is associated with a separate key. Key management for the SEV feature is not handled by the CPU but rather by a separate processor known as the AMD Secure Processor (AMD-SP) which is present on AMD SOCs. A detailed discussion of AMD-SP operation is beyond the scope of this manual. 
CPU software is not aware of the values of these keys but the hypervisor should coordinate the loading 
of virtual machine keys through the AMD-SP driver. This coordination will also determine which ASID the hypervisor should use for a particular guest. Under SEV , the ASID is used as the key index that identifies which encryption key is used to encrypt/decrypt memory traffic associated with that SEV-enabled guest. Encryption keys themselves are never visible to CPU software and are never stored off-chip in the clear.
15.34.3  Enabling SEV
Prior to starting an encrypted VM, software must enable MemEncryptionModEn through MSR 
C001_0010 (SYSCFG) as described in Section 7.10.2, “Enabling Memory Encryption Extensions,” 
on page 237. SEV may then be enabled on a specific virtual machine during the VMRUN instruction if the hypervisor sets the SEV enable (bit 1) in VMCB offset 090h.
When SEV is enabled in a guest, the following additional consistency checks are performed during 
VMRUN:
•Nested paging (VMCB offset 090h, bit 0) must be enabled
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•MSR C001_0015 (HWCR) [SmmLock] must be set
•ASID (VMCB offset 058h) must be within the allowed range for SEV
The allowed ASIDs for SEV operation may be a subset of the overall number of hardware supported 
ASIDs. In this scenario, SEV-enabled guests must use ASIDs in the defined subset, while non-SEV enabled guests can use the remaining ASID range. The range of ASIDs allowed for SEV-enabled guests is from 1 to a maximum value defined via CPUID 8000_001F[ECX]. 
Note that on systems where CPUID Fn8000_001F_EAX[11] is set to 1, the hypervisor must be in 64-
bit mode in order to execute a VMRUN to an SEV-enabled guest. If not, the VMRUN fails with a VMEXIT_INV ALID error code.
If any of the above consistency checks fail when SEV is enabled on a guest, the VMRUN instruction 
will terminate with a VMEXIT_INV ALID error code. If MemEncryptionModEn is 0, SEV cannot be enabled and the VMCB control bit for SEV is ignored.
15.34.4  Supported Operating Modes
Secure Encrypted Virtualization may be enabled on guests running in any operating mode. However 
the guest is only able to control memory encryption when operating in long mode or legacy PAE mode. In all other modes, all guest memory accesses are unconditionally considered private and are encrypted with the guest-specific key.
15.34.5  SEV Encryption Behavior
When a guest is executed with SEV enabled, the guest page tables are used to determine the C-bit for a 
memory page and hence the encryption status of that memory page. This allows a guest to determine which pages are private or shared, but this control is available only for data pages. Memory accesses on behalf of instruction fetches and guest page table walks are always treated as private, regardless of the software value of the C-bit. This behavior ensures non-guest entities (such as the hypervisor) cannot inject their own code or data into an SEV-enabled guest. If a guest does wish to make data in instruction pages or page tables accessible to code outside of the guest, this data must be explicitly copied into a shared data page.
Note that while the guest may choose to set the C-bit explicitly on instruction pages and page table 
addresses, the value of this bit is a don't-care in such situations as hardware always performs these as private accesses. 
15.34.6  Page Table Support
An SEV-enabled guest controls encryption in its own guest page tables using the C-bit defined by 
CPUID 8000_001F[EBX]. This location is the same C-bit location as defined under SME (Section 7.10, “Secure Memory Encryption,” on page 237) in non-virtualized mode. If the C-bit is an 
address bit, this bit is masked from the guest physical address when it is translated through the nested page tables. Consequently, the hypervisor does not need to be aware of which pages the guest has chosen to mark private.
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For example if the C-bit is address bit 47, when a guest accesses virtual address 0x54321, it might be 
translated to guest physical address 0x8000_00AB_C321, indicating the page should be encrypted with the private guest key. When this guest physical address is translated through the nested page tables, host virtual address 0xAB_C321 is used for translation. The C-bit value from the guest physical address is saved and used on the final system physical address after the nested table translation as shown in Figure 15 -30.
Note that because guest physical addresses are always translated through the nested page tables, the size of the guest physical address space is not impacted by any physical address space reduction indicated in CPUID 8000_001F[EBX]. If the C-bit is a physical address bit however, the guest physical address space is effectively reduced by 1 bit.
Figure 15-30. Guest Data Request
15.34.7  Restrictions
As with SME, some hardware implementations may not enforce coherency between mappings of the 
same physical page with different encryption enablement or keys. In such a system, when the encryption enablement or key for a particular memory page is to be changed, software must first ensure the page is flushed from all CPU caches. Certain conventional cache flushing techniques may not work however; see Section 15.34.9 for further details.
Note that if the hardware implementation enforces coherency across encryption domains as indicated 
by CPUID Fn8000_001F_EAX[10] then this flush is not required.
Guest Page Tables
Address
Nested Page Tables
Address
Guest Physical Address
 C‐bit
System Physical Address
 C‐bitGuest Data Request
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15.34.8  SEV Interaction with SME
SEV may be used in conjunction with SME mode. In this scenario, the guest page tables control 
encryption for guest memory, and the host (nested) page tables control encryption for shared memory. This behavior is summarized in Table 15 -32. SEV is considered active when the CPU is in guest mode 
and the guest has SEV enabled in the VMCB.
Note that during a nested page table walk, it is possible for both the guest page tables to be encrypted 
and the nested page tables to be encrypted. In this scenario, the guest page tables are decrypted using the guest private encryption key, and the nested page tables are decrypted using the host (SME) encryption key. 
Guest data accesses that are marked shared (C=0) by the guest may still be optionally encrypted using 
the host (SME) key if the pages are marked encrypted in the nested tables. If a page is marked encrypted in both the guest and nested tables, the guest tables have priority and the page will be encrypted using the guest key. This behavior is summarized in Table 15 -33.Table 15 -32. Encryption Control
Type of 
AccessMemEncrypt
ionModEnGuest 
ModeSEV 
Mode 
ActiveEncryptedEncryption 
KeyNotes
Legacy Mode (memory encryption disabled)
All 0 X X No N/A
Secure Memory Encryption Mode
All 1 0 X Optional Host Key Determined by page tables (CR3)
All 1 1 0 Optional Host KeyDetermined by nested page tables 
(hCR3)
Secure Encrypted Virtualization Mode
Instruction 
Fetch1 1 1 Yes Guest Key
Guest Page 
Table 
Access1 1 1 Yes Guest Key
Nested Page 
Table 
Access1 1 1 Optional Host KeyDetermined by nested page tables (hCR3)
Data Access 1 1 1 Optional
1See Table 
15-33: 
SEV/SME

Type of 
ModeSEV 
Mode 
KeyNotes
(hCR3)
Guest Page 
Table 
Table 
1See Table 
15-33: 
SEV/SME 
InteractionDetermined by guest page tables (gCR3) and nested page tables (hCR3)
Note: 
1. Encryption is guest-controlled in long mode and legacy P AE mode only. In all other modes, these accesses are always considered
private and are encrypted with the guest key
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15.34.9  Page Flush MSR
If coherency across encryption domains is not supported (see “Restrictions” on page 591), and the 
hypervisor wishes to read an encrypted page, it must first flush the guest view of that page from all CPU caches to ensure it is able to view the most recent copy of that data. This may be accomplished by issuing a WBINVD instruction on all cores on which the guest has run, or by using the VMPAGE_FLUSH MSR (C001_011E). Support for the VMPAGE_FLUSH MSR is indicated in CPUID 8000_001F[EAX] bit 2.
The VMPAGE_FLUSH MSR is a write-only register that may be used to flush 4KB of data on behalf 
of a guest. The hypervisor writes the host linear address of the page and guest ASID to the MSR, and hardware will then perform a write-back invalidation of the page causing any dirty data present in any CPU caches throughout the system to be encrypted and written to DRAM. Note that the VMPAGE_FLUSH MSR uses the standard host page tables to perform the page translation. The Page Flush MSR operation will hit on and evict guest-cached instances of the memory, whereas CLFLUSH instructions using this same translation will not.
The VMPAGE_FLUSH MSR will only flush memory pages marked private by the guest. If the 
hypervisor does not know if the memory page was marked private but wishes to evict the page from the cache, it should perform a standard CLFLUSH in addition to using the VMPAGE_FLUSH MSR.
Attempts to flush a host virtual address that is not mapped into a physical address or use of an ASID=0 
will cause a #GP(0) fault. If SMAP is enabled, the input address needs to be mapped in page tables as a supervisor address.
If coherency across encryption domains is supported, the CLFLUSH instruction may be used to evict 
guest pages from the cache regardless of whether they are marked private or not by the guest.
15.34.10  SEV_STATUS MSR
Guests can determine what SEV features are currently active by reading the SEV_STATUS MSR 
(C001_0131). This MSR indicates which SEV features were enabled by the hypervisor in the last VMRUN for that guest as shown in Table 15 -34. The SEV_STATUS MSR is read-only and accesses to Table 15-33. SEV/SME Interaction
Nested Page Table
C=0 C=1
Guest 
Page TableC=0 Unencrypted Encrypted with host key
C=1Encrypted with guest keyEncrypted with guest key
Bit[s] Description
63:12  VirtualAddr:  Write-only. Host virtual address of page to flush 
11:0  ASID: Write-only. Guest ASID to use for the flush
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the SEV_STATUS MSR cannot be intercepted by the hypervisor. The SEV_STATUS MSR is 
available on processors that support SEV . 
15.34.11  Virtual Transparent Encryption (VTE)
The Virtual Transparent Encryption feature can be enabled to force all memory accesses within an 
SEV guest to be encrypted with the guest’s key. Support for this feature is indicated in CPUID Fn8000_001F[EAX] bit 16.
To enable this feature, the hypervisor must set VMCB offset 90h bit 5. Bit 5 is only observed when 
SEV (bit 1) is also set to 1 and SEV-ES (bit 2) is cleared to 0. In all other configurations of these bits (namely SEV disabled or SEV-ES enabled), bit 5 is ignored by hardware.Table 15-34. SEV_STATUS MSR Fields
63:18 Reserved  
17SmtProtection_Enabled: The guest was run with the SMT Protection feature enabled in
SEV_FEATURES[15]
16 VmsaRegProt_Enabled: The guest was run with the VMSA Register Protection feature enabled in SEV_FEA -
TURES[14] 
15 Reserved  
14 The guest was run with Instruction-Based Sampling Virtualization enabled. SEV_FEATURES[12]
13 Reserved  
12VmgexitParameter_Enabled: The guest was run with the VMGEXIT Parameter feature enabled in
SEV_FEATURES[10]
11 SecureTsc_Enabled:  The guest was run with the Secure TSC feature enabled in SEV_FEATURES[9]
10 VmplSSS_Enabled:  The guest was run with the VMPL SSS feature enabled in
SEV_FEATURES[8]
9SNPBTBIsolation_Enabled: The guest was run with the BTB isolation feature enabled in 
SEV_FEATURES[7]
8PreventHostIBS_Enabled: This guest was run with the PreventHostIBS feature enabled in SEV_FEATURES[6].
7DebugSwap_Enabled:  This guest was run with debug register swapping enabled in 
SEV_FEATURES[5].
6AlternateInjection_Enabled: The guest was run with the Alternate Injection feature enabled in SEV_FEATURES[4]
5RestrictedInjection_Enabled: The guest was run with the Restricted Injection feature enabled in SEV_FEATURES[3]
4 ReflectVC_Enabled: The guest was run with the ReflectVC feature enabled in SEV_FEATURES[2]
3 vTOM_Enabled:  The guest was run with the Virtual TOM feature enabled in SEV_FEATURES[1]
2 SNP_Active: The guest was run in SNP-Active mode as selected by SEV_FEATURES[0]
1 SEV_ES_Enabled: The guest was run with the SEV-ES feature enabled in VMCB offset 90h
0 SEV_Enabled: The guest was run with the SEV feature enabled in VMCB offset 90h
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When this feature is enabled, CPU hardware treats the guest C-bit as 1 for all guest memory 
references. The actual C-bit in the guest page tables is ignored by hardware. 
Guest address translation is unchanged, so the guest physical address (without the C-bit) is used for 
translation in the nested page tables. 
15.35 Encrypted State (SEV-ES)
Encrypted VMs that use the SEV feature described in Section 15.34 may additionally use the SEV-ES feature to protect guest register state from the hypervisor. An SEV-ES VM's CPU register state is encrypted during world switches and cannot be directly accessed or modified by the hypervisor. This is designed to protect against attacks such as exfiltration (unauthorized reading of VM state) and control flow attacks (modifying VM state) including rollback attacks (restoring an earlier VM register state).
SEV-ES includes architectural support for notifying a VM's operating system when certain types of 
world switches are about to occur, allowing the VM to selectively share information with the hypervisor when needed for functionality.
15.35.1  Determining Support for SEV-ES
SEV-ES support can be determined by reading CPUID Fn8000_001F[EAX] as described in 
Section 15.34.1. Bit 3 of EAX indicates support for SEV-ES.
15.35.2  Enabling SEV-ES
SEV-ES may be enabled on a per-VM basis by setting bit 2 in offset 90h of the VMCB. When enabling 
SEV-ES, the hypervisor must also enable SEV (offset 90h bit 1) and LBR virtualization (offset B8h bit 0). Additionally, all other programming requirements related to enabling SEV (see Section 15.34.3) must be satisfied when running an SEV-ES guest.
On some systems, there is a limitation on which ASID values can be used on SEV guests that are run 
with SEV-ES disabled. While SEV-ES may be enabled on any valid SEV ASID (as defined by CPUID Fn8000_001F[ECX]), there are restrictions on which ASIDs may be used for SEV guests with SEV-ES disabled. CPUID Fn8000_001F[EDX] indicates the minimum ASID value that must be used for an SEV-enabled, SEV-ES-disabled guest. For example, if CPUID Fn8000_001F[EDX] returns the value 5, then any VMs which use ASIDs 1-4 and which enable SEV must also enable SEV-ES.
Note that prior to running an SEV-ES VM for the first time, the hypervisor must coordinate with the 
AMD Secure Processor to create the initial encrypted state image for the guest VM.
15.35.3  SEV-ES Overview
The SEV-ES architecture is designed to protect guest VM register state by default, and only allow the 
guest VM itself to grant selective access as required. This additional security protection functionality is accomplished in two ways. First, all VM register state is saved and encrypted when a VM exit event (#VMEXIT) occurs. This state is decrypted and restored on a VMRUN only. Second, certain types of #VMEXIT events cause a new exception to be taken within the guest VM. This new exception (#VC, 
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see Section 15.35.5) indicates that the guest VM performed some action which requires hypervisor 
involvement, an example of which would be an I/O access by the VM. The guest #VC handler is 
responsible for determining what register state is necessary to expose to the hypervisor for the purpose of emulating this operation. The #VC handler also inspects the returned values from the hypervisor and updates the guest state if the output is deemed acceptable.
Register state that needs to be exposed utilizes a new structure called the Guest-Hypervisor

Register state that needs to be exposed utilizes a new structure called the Guest-Hypervisor 
Communication Block (GHCB). The GHCB location is chosen by the guest who maps the page as a shared memory page, thus allowing direct hypervisor access. Only state located in the GHCB can be read by the hypervisor as all state stored in the traditional VMCB save state structure is encrypted using the guest memory encryption key and integrity protected.
In the #VC handler, the guest may utilize a new instruction (Section 15.35.6) to perform a world 
switch and invoke the hypervisor. In response to this, the hypervisor can inspect the GHCB and determine the services requested by the guest.
15.35.4  Types of Exits
When SEV-ES is enabled, all #VMEXIT events are classified as either Automatic Exits (AE) or Non-
Automatic Exits (NAE). AE events are generally events that occur asynchronously with respect to the guest execution (e.g. interrupts) or events that need not involve exposing any guest register state. All other #VMEXIT events are classified as NAE events, and with NAE events the guest is allowed to determine what register state (if any) to expose in the GHCB. During guest execution, #VMEXIT events (both AE and NAE) are only taken if the corresponding intercept bit in the VMCB control area is set.
The hypervisor is informed of specific AE events exclusively via the #VMEXIT codes within the 
EXITCODE field of the VMCB control area. NAE events result in a #VC exception which is handled by the guest. Table 15-35 lists the possible AE events, all other events are considered NAE events.
Table 15-35. AE Exitcodes
Code Name Notes HW Advances RIP
52h VMEXIT_MC Machine check exception No
60h VMEXIT_INTR Physical INTR No
61h VMEXIT_NMI Physical NMI No
62h VMEXIT_SMI Physical SMI No
63h VMEXIT_INIT Physical INIT No
64h VMEXIT_VINTR Virtual INTR No
77h VMEXIT_PAUSE PAUSE instruction Yes
78h VMEXIT_HLT HLT instruction Yes
7Fh VMEXIT_SHUTDOWN Shutdown No
8Fh VMEXIT_EFER_WRITE_TRAP See Section 15.35.10 Yes
90h -9Fh VMEXIT_CR[0-15]_WRITE_TRAP See Section 15.35.10 Yes
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In the case of exits due to specific instructions, the CPU will automatically advance the guest RIP in 
response to the AE so that execution will resume at the next instruction on a subsequent VMRUN.
In the case of nested page faults, these are treated as AEs only if there was no reserved bit error. This is 
intended to be used to help distinguish nested page faults due to demand misses (hypervisor needs to allocate a page) vs MMIO emulation (hypervisor needs to emulate a device). Consequently, the hypervisor should set a reserved page table bit, such as a reserved address bit, on all MMIO pages that it intends to emulate. (This can include address bits that may become reserved when SEV is enabled; see Section 15.34.1.) This will ensure that MMIO page faults become NAE events, which is critical so 
the guest #VC handler can be invoked to assist in the MMIO emulation. Nested page faults that are AE events do not invoke any guest handler and the hypervisor is intended to allocate memory as needed and then resume the guest.
Note that when a guest is running with SEV-ES enabled, instruction bytes (VMCB offset D0h) are 
never saved to the VMCB on a nested page fault.
15.35.5  #VC Exception
The VMM Communication Exception (#VC) is always generated by hardware when an SEV-ES 
enabled guest is running and an NAE event occurs. The #VC exception is a precise, contributory, fault-
type exception utilizing exception vector 29. This exception cannot be masked. The error code of the #VC exception is equal to the #VMEXIT code (see Appendix C) of the event that caused the NAE.
In response to a #VC exception, a typical flow would involve the guest handler inspecting the error 
code to determine the cause of the exception and deciding what register state must be copied to the GHCB for the event to be handled. The handler should then execute the VMGEXIT instruction to create an AE and invoke the hypervisor. After a later VMRUN, guest execution will resume after the VMGEXIT instruction where the handler can view the results from the hypervisor and copy state from the GHCB back to its internal state as needed. This flow is shown in Figure 15 -31.
Note that it is inadvisable for the hypervisor to set the VMCB intercept bit for the #VC exception as this would prevent proper handling of NAEs by the guest. Similarly, the hypervisor should avoid setting intercept bits for events that would occur in the #VC handler (such as IRET).A5h VMEXIT_BUSLOCK Bus Lock Threshold No
400h VMEXIT_NPFOnly if PFCODE[3]=0 (no reserved bit 
error)No
403h VMEXIT_VMGEXIT VMGEXIT instruction Yes
–1 VMEXIT_INV ALID Invalid guest state –
–2 VMEXIT_BUSYBusy bit was set in guest state (see Section 15.36.16)–Table 15 -35. AE Exitcodes (continued)
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Figure 15-31. EXAMPLE #VC FLOW
Guest triggers 
VMEXIT condition
Send #VC exception 
to the guest
Hypervisor handles 
exit
#VC handler copies 
state to GHCB as 
needed
VMGEXIT
Save guest state to 
protected memory 
and load HV state
VMRUN
Load guest state 
from protecte d 
memory
Returns to #VC 
handler
Handler modifies 
state as needed
IRETGuest AMD64 Hardware Hypervisor
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15.35.6  VMGExit
The VMGEXIT instruction creates an AE and is intended to allow a guest #VC handler to invoke the 
hypervisor when needed. VMGEXIT causes an AE with the VMEXIT_VMGEXIT code and behaves like a trap so that upon a subsequent VMRUN, execution resumes following the VMGEXIT. There is no hypervisor intercept bit for VMGEXIT as the instruction unconditionally causes an AE when executed in an SEV-ES guest.
The VMGEXIT opcode is only valid within a guest when run with SEV-ES mode active. If the guest is 
not run with SEV-ES mode active, the VMGEXIT opcode will be treated as a VMMCALL opcode and will behave exactly like a VMMCALL.
The VMGEXIT Parameter feature may be used by a guest #VC handler to atomically pass one 
parameter to the hypervisor. Support for the VMGEXIT Parameter feature is indicated by CPUID Fn8000_001F_EAX[VmgexitParameter] (bit 17) = 1. The VMGEXIT Parameter feature is enabled by setting SEV_FEATURES bit 10 (VmgexitParameter) in VMSA. When this feature is enabled, the RAX and the CPL values are written to the VMCB control area on VMGEXIT at offsets 110h (VMGEXIT_RAX) and 118h (VMGEXIT_CPL).
15.35.7  GHCB
The GHCB is an unencrypted memory page used to communicate register state between the SEV-ES 
guest and the hypervisor. The guest VM is able to set the location of the GHCB via the GHCB MSR (C001_0130). This value is also included in the VMCB and is saved/restored on VMRUN/#VMEXIT respectively.
The GHCB MSR is used to set up the location of the GHCB memory page. The format of this MSR is 
defined below:
The value of this MSR is saved/restored from the VMCB offset 0A0h. It is recommended software 
write this MSR with a page-aligned address. The GHCB MSR can be read/written only in guest mode, attempts to access this MSR in host mode will result in a #GP.
Hardware never accesses the GHCB directly, and as a result the format of the GHCB is not fixed. 
15.35.8  VMRUN
When SEV-ES is enabled, the VM save state area does not reside at offset 400h in the VMCB page. 
Instead it resides starting at offset 0h in a separate page called the VM Save Area (VMSA) as indicated by the VMSA Pointer at offset 108h. The VMSA Pointer value is stored as a host physical address. 
Hardware always accesses the VMSA save state area using encrypted memory accesses utilizing the guest's memory encryption key.
When hardware executes a VMRUN instruction and the VMCB indicates SEV-ES is enabled for the 
guest, the hardware loads guest state from the encrypted save state area indicated by the VMSA Bit Function
63:0 Guest physical address of GHCB
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Pointer. Also, the VMRUN instruction will perform the following actions in addition to the standard 
VMRUN behavior: 
•Calculate a checksum over guest state to verify integrity
•Perform a VMLOAD to load additional guest register state
•Load guest GPR state
•Load guest FPU state
When a guest has SEV-ES enabled, the encrypted VM state save area definition is expanded to include 
all GPR and FPU state (see Appendix B). If any part of the VMRUN flow faults or if the integrity checksum fails to match, a #VMEXIT(VMEXIT_INV ALID) is generated.
Note that if SEV-ES is enabled, the VMRUN instruction ignores bits 10:5 of the VMCB clean bits and always reloads the full guest state. 
Also note that for SEV-ES guests, while the full guest state is loaded on VMRUN only the minimal 
hypervisor state defined by the legacy VMRUN instruction (see Section 15.5.1) is saved to the host save area. The hypervisor itself should save its desired additional segment state and GPR values to the host save area since these values will be restored by hardware on a subsequent VMEXIT. Hardware does not automatically save host state such as FS, STAR, or GPR values from the hypervisor on a VMRUN. See Appendix B for a detailed breakdown of each piece of VMCB state.

Finally, note that event injection for SEV-ES guests is restricted. Software interrupts and exception 
vectors 3 and 4 may not be injected. If this is attempted, the VMRUN will fail with a VMEXIT_INV ALID error code.
15.35.9  Automatic Exits
When an automatic exit event occurs while an SEV-ES enabled guest is executing, hardware 
automatically saves guest state to the encrypted save state area and restores hypervisor state from the host save area. Specifically, in addition to the standard state saved/restored by the VMEXIT flow, hardware will also perform the following steps:
•Perform a VMSA VE to save additional guest register state
•Save guest GPR state
•Save guest FPU state
•Calculate and store a checksum over the guest state for use in a subsequent VMRUN
•Perform a VMLOAD to load additional host register state
•Load host GPR state
•Re-initialize FPU state to their reset values
The loading of host GPR state from the host save area is done using the format of the expanded VMCB 
described in Appendix B. All register state is either loaded from this location or re-initialized to default values so no guest register state is visible to the hypervisor.
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15.35.10  Control Register Write Traps
The use of CR[0-15]_WRITE intercepts are discouraged for guests that are run with SEV-ES. These 
intercepts occur prior to the control register being modified, and the hypervisor is not able to modify the control register itself since the register is located in the encrypted state image. Hypervisors are encouraged to use the new CR[0-15]_WRITE_TRAP and EFER_WRITE_TRAP intercept bits instead which cause an AE after a control register has been modified. These intercepts enable the hypervisor to track the guest mode and verify if desired features are being enabled. When these traps are taken, the new value of the control register is saved in EXITINFO1. CR write traps are only supported for SEV-ES guests.
Note that writes by SEV-ES guests to EFER.SVME are always ignored by hardware.
15.35.11  Interaction with SMI and #MC 
If an SMI occurs while an SEV-ES guest is executing, the platform SMI handler is not immediately 
executed. Instead, the SMI will remain pending and a #VMEXIT(SMI) is generated. The SMI will then be taken in hypervisor context after STGI is executed. Note that this behavior occurs regardless of the value of the SMI intercept bit in the VMCB.
In some systems, machine check errors are first delivered as an SMI. If this occurs while an SEV-ES 
guest is executing, #VMEXIT(SMI) will be generated and EXITINFO1[MCREDIR] will be set to 1 (“SMI Intercept” on page 521). As described above, the SMI will be held pending until STGI is 
executed. After the platform SMI handler executes following STGI, the hypervisor should check the MCREDIR bit to determine if the #VMEXIT(SMI) was due to a machine check error in the guest and handle it appropriately.
15.36 Secure Nested Paging (SEV-SNP) 
The SEV-SNP features enable additional protection for encrypted VMs designed to achieve stronger isolation from the hypervisor. SEV-SNP is used with the SEV and SEV-ES features described in Section 15.34 and Section 15.35 respectively and requires the enablement and use of these features.
Primarily, SEV-SNP provides integrity protection of VM memory to help prevent hypervisor-based 
attacks that rely on guest data corruption, aliasing, replay, and various other attack vectors. To achieve this, a new system-wide data structure called the Reverse Map Table (RMP) is used to perform additional security checks on memory access as described in Section 15.36.3.
In addition to memory protection, SEV-SNP also includes several security features including a new 
Virtual Machine Privilege Level (VMPL) architecture, interrupt injection restrictions, and side-channel protection. These features are designed to enable additional use models and enhanced security protections.
While this chapter describes the CPU hardware behavior of SEV-SNP, the technology also requires the 
use of the AMD Secure Processor (AMD-SP) SEV-SNP Application Binary Interface (ABI) to 
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manage the lifecycle events of SEV-SNP VMs. See the SEV-SNP ABI specification (PID#56860) on 
AMD’s website for more details.
15.36.1  Determining Support for SEV-SNP 
Support for SEV-SNP can be determined by reading CPUID Fn8000_001F[EAX] as described in 
Section 15.34.1. Bit 4 indicates support for SEV-SNP, while bit 5 indicates support for VMPLs. The 
number of VMPLs available in an implementation is indicated in bits 15:12 of CPUID Fn8000_001F[EBX].
CPUID Fn8000_001F[EAX] also indicates support for additional security features used with SEV-
SNP guests, which are described in the following sections.
15.36.2  Enabling SEV-SNP 
SEV-SNP depends on SEV for confidentiality protection. Before enabling SEV-SNP, the 
MemEncryptionModEn bit in MSR C001_0010 (SYSCFG) must be set, and all programming requirements described in Section 15.34.3 must be satisfied. After SecureNestedPagingEn is set to 1 in MSR C001_0010, certain MSRs may no longer be modified. This includes the fixed range MTRR registers (see Section 7.7.2), the IORR registers (see Section 7.9.2), the TOP_MEM and TOP_MEM2 
registers (see Section 7.9.4), as well as the SYS_CFG MSR. Attempts to write the SYS_CFG MSR after SecureNestedPagingEn is set to 1 will be ignored while attempts to write the other MSRs mentioned will result in #GP(0).
Enabling SEV-SNP requires a two-step initialization procedure:
1. Construct the Reverse Map Table (RMP) as described in Section 15.36.4.
2. Set VMPLEn and SecureNestedPagingEn in MSR C001_0010 (SYSCFG) on every core in the
system.
After the SEV-SNP feature has been globally enabled, SEV-SNP can be activated on a per-VM basis 
by setting bit 0 of the SEV_FEATURES field at offset 3B0h of the VMSA during VM creation. SEV-SNP activated VMs must also enable SEV-ES as described in Section 15.35.2 and SEV as described in 
Section 15.34.3. 
In this chapter, the term SNP-enabled  indicates that SEV-SNP is globally enabled in the SYSCFG 
MSR. The term SNP-active  indicates that SEV-SNP is enabled for a specific VM in the 
SEV_FEATURES field of its VMSA. While SNP-enabled systems support both SNP-active and non-SNP-active VMs, SNP-active VMs can only run on SNP-enabled systems.
15.36.3  Reverse Map Table 
The Reverse Map Table (RMP) is a structure shared globally by all logical processors that resides in 
system memory and is used to ensure a one-to-one mapping between system physical addresses and guest physical addresses. Each page of physical memory that is potentially assignable to guests has one entry within the RMP. RMP entries contain the security attributes of the system physical page as described in Table 15-36.
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The integrity of the RMP is maintained by restricting software manipulation of it to the following 
special-purpose instructions:
•RMPUPDATE: Available to the hypervisor to alter the Guest_Physical_Address, Assigned,
Page_Size, Immutable, and ASID fields of an RMP entry. See Section 15.36.5 for details.
•PSMASH: Allows the hypervisor to split a 2MB entry in the RMP into 512 4KB entries in theRMP. See Section 15.36.11 for details.
•RMPADJUST: Allows a guest to alter the VMPL permission masks of the RMP entry. See Section15.36.7 for details.
•PV ALIDATE: Allows a guest to write to the Validated flag in the RMP entry. See Section 15.36.6
When SEV-SNP is globally enabled, it adds more restrictions to page access controls. The hypervisor and the guests use the above instructions to enforce these restrictions on memory accesses. A violation Table 15-36. Fields of an RMP Entry
Name Notes
AssignedFlag indicating that the system physical page is assigned to a guest or to the 
AMD-SP. 
0: Owned by the hypervisor 1: Owned by a guest or the AMD-SP 
Page_Size Encoding of the page size. 0: 4KB page 1: 2MB page 
Immutable Flag indicating that software can alter the entry via x86 RMP manipulation 
instructions. 
0: RMP entry can be altered by software 1: RMP entry cannot be altered by software 
Guest_Physical_Address Guest physical address associated with the page
ASID ASID of guest to which page is assigned 
VMSA Flag indicating that the page is a VMSA page. 0: Non-VMSA page 1: VMSA page 
Validated Flag indicating that the guest has validated the page. See Section 15.36.6 for details.
0: The guest has not yet validated the page 1: The guest validated the page with PV ALIDATE 
Permissions[0] 
VMPL permission masks for the page. See section 15.36.7.
 for details.  ...
Permissions[n-1] 
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of memory access restrictions indicated by the RMP will result in an exception. See Section 15.36.10 

15.36.4  Initializing the RMP
MSR C001_0132 (RMP_BASE) defines the system physical address of the first byte of the RMP. The 
MSR C001_0133 (RMP_END) defines the system physical address of last byte of the RMP. Software must program RMP_BASE and RMP_END identically for each core in the system and before enabling SEV-SNP globally.
RMP_BASE and (RMP_END+1) must be 8KB aligned. The AMD-SP may place further alignment 
requirements on these registers. Refer to the latest AMD-SP specifications to determine the required alignment.
The region of memory between RMP_BASE and RMP_END contains a 16KB region used for 
processor bookkeeping followed by the RMP entries, which are each 16B in size. The size of the RMP determines the range of physical memory that the hypervisor can assign to SNP-active virtual machines at runtime. The RMP covers the system physical address space from address 0h to the address calculated by:
((RMP_END + 1 – RMP_BASE – 16KB) / 16B) x 4KBFor example, if the RMP_BASE is equal to 10_0000h, then to cover the first 4GB of physical memory, 
RMP_END must be set to 110_3FFFh, which makes the RMP just over 16MB.
Once SEV-SNP is globally enabled, memory accesses are restricted by RMP checks. To ensure that the 
RMP starts in a known and non-restrictive state, software should write zeros to all memory from RMP_BASE to RMP_END before setting the SecureNestedPagingEn bit in the SYSCFG MSR. The hypervisor then requests the AMD-SP to finalize the initialization of the RMP. The AMD-SP initializes the RMP to prevent all software from directly writing to the memory between RMP_BASE and RMP_END. All subsequent RMP entry manipulation must occur either via the x86 RMP manipulation instructions or through interactions with the AMD-SP.
15.36.5  Hypervisor RMP Management 
The hypervisor manages the SEV-SNP security attributes of pages assigned to SNP-active guests by 
altering the RMP entries of those pages. Because the RMP is initialized by the AMD-SP to prevent direct access to the RMP, the hypervisor must use the RMPUPDATE instruction to alter the entries of the RMP. RMPUPDATE allows the hypervisor to alter the Guest_Physical_Address, Assigned, Page_Size, Immutable, and ASID fields of an RMP entry. 
SEV-SNP associates an owner with each system physical page through settings of the Assigned, 
ASID, and Immutable fields of the page’s RMP entry according to Table 15-37. A page can be owned 
by the hypervisor, a guest, or the AMD-SP. 
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When the hypervisor assigns a page to a guest, it must also set the Guest_Physical_Address and 
Page_Size to match the nested page table mapping for the guest. If not, access to the page by the guest will result in a fault. See Section 15.36.10 for details on the RMP access checks.
The hypervisor may transition any page that has Immutable set to 0 into a hypervisor-owned page by 
using RMPUPDATE to set Assigned to 0 and ASID to 0. To transition a page that has Immutable set to 1, the hypervisor must request the AMD-SP to transition the page.
The RMP initialization requirement to write zeros to the RMP (see Section 15.36.4) results in all pages 
in the system initially belonging to the hypervisor. Any memory pages which are not covered by the RMP are considered permanent hypervisor pages. For example, if the RMP is configured to only cover the first 4GB of memory then all memory above 4GB is considered hypervisor memory for the purpose of RMP access checks.
15.36.6  Page Validation 
Each page assigned to a VM is either validated or unvalidated, as indicated by the Validated flag in the 
page’s RMP entry. Memory accesses by the VM to private pages that are unvalidated generate a #VC. All pages are initially assigned as unvalidated.
The VM may use the PV ALIDATE instruction to either set or clear the Validated flag of a page. It is 
expected that VMs would use PV ALIDATE to set the Validated flag during VM startup to gain access to the memory the hypervisor has assigned. The VM may later use PV ALIDATE to clear the Validated flag if its memory space is being reduced, such as after a memory hot-plug event.
Page validation allows a VM to detect an unexpected remapping of its pages by the hypervisor. Before 
accessing a page, the VM must validate the page. Once validated, any use of RMPUPDATE by the hypervisor to unassign, reassign, or remap the page will cause the page to become unvalidated. The VM can then detect tampering with the page mapping via the #VC that occurs from accessing unvalidated pages.
PV ALIDATE takes a page size as an input parameter indicating that either a 4KB or 2MB page should 
be validated. If the VM attempts to use PV ALIDATE on a 4KB page that is mapped to a 2MB or 1GB page in the nested page table, PV ALIDATE generates an #VMEXIT(NPF). In this case, the hypervisor can smash the larger page into 4KB pages using the PSMASH instruction as described in Section 15.36.11. If the VM attempts to use PV ALIDATE on a 2MB guest page that is mapped to 4KB nested pages, PV ALIDATE returns an error indication to the VM. The VM can instead attempt to execute PV ALIDATE for each of the 4KB pages individually.Table 15 -37. RMP Page Assignment Settings
Owner Assigned ASID Immutable
Hypervisor 0 0 -
Guest 1 ASID of the guest -
AMD-SP 1 0 1
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15.36.7  Virtual Machine Privilege Levels
A typical guest VM may consist of multiple vCPUs. SEV-SNP expands on this capability by enabling 
the vCPUs to run at distinct Virtual Machine Privilege Levels (VMPLs). Within a vCPU, the different VMPLs are represented by unique VMSAs and are expected to be run in a mutually exclusive manner. Each VMSA is assigned a VMPL as indicated by the VMPL field in the VMSA. 
VMPLs are identified numerically starting at 0 with VMPL0 being the most privileged. The number of 
VMPLs available in an implementation is indicated in bits 15:12 of CPUID Fn8000_001F[EBX]. The VMPL feature enables a guest to sub-divide its address space and implement vCPU-specific access controls on a page-by-page basis. 
The processor restricts guest memory accesses based on VMPL permission masks in RMP entries. 
Each RMP entry contains a set of permission masks, one mask for each implemented VMPL. On memory accesses, the processor checks the current VMPL permission mask of the page to determine whether the access is allowed. The permission mask bits are defined in Table 15-38.
When a guest access results in a #VMEXIT(NPF) due to a VMPL permission violation, an error code bit in EXITINFO1 is set as described in Section 15.36.10. It is illegal to configure a page with VMPL write permissions but not read permissions. A data access to such a page will result in a #VMEXIT(NPF).
When the hypervisor assigns a page to a guest using RMPUPDATE, full permissions are enabled for 
VMPL0 and are disabled for all other VMPLs. A VM can then use the RMPADJUST instruction to modify the permissions of VMPLs numerically higher than its own. For example, a vCPU executing at VMPL0 could use RMPADJUST to restrict a page of memory to be only read-write but not executable at VMPL1. However, the vCPU executing at VMPL1 could not alter its own permissions or the permissions of VMPL0. Table 15-38. VMPL Permission Mask Definition
Bit Name Settings
0 Read0: Reads cause #VMEXIT(NPF)
1: Reads are allowed
1 Write 0: Writes cause #VMEXIT(NPF)1: Writes are allowed
2 Execute-User0: Execution at CPL 3 causes #VMEXIT(NPF)1: Execution at CPL 3 is allowed
3 Execute-Supervisor 0: Execution at CPL < 3 causes #VMEXIT(NPF)1: Execution at CPL < 3 is allowed
4Supervisor-Shadow-
Stack0: SSS accesses cause #VMEXIT(NPF)
1: SSS accesses are allowed
5-7 Reserved SBZ 
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Further, RMPADJUST cannot be used to grant greater permissions than what is allowed by the 
permission mask for the current VMPL. For example, if VMPL1 attempts to grant write permission to a page to VMPL2, but VMPL1 does not have write permission to the page, RMPADJUST will fail.
VMPL Supervisor Shadow Stack. The VMPL Supervisor Shadow Stack (VMPL SSS) feature 
allows an SNP-active guest instead of the hypervisor (see Section 15.25.14) to restrict which guest 
physical addresses may be used for a guest supervisor shadow stack by designating SSS pages with VMPL SSS permission bit. Supervisor shadow stack accesses made by the guest to pages not designated as SSS pages in the VMPL Permissions result in a #VMEXIT(NPF).
Support for the VMPL SSS feature is indicated by CPUID Fn8000_001F_EAX[VmplSSS] (bit 7) = 1. 
The VMPL SSS feature is enabled by setting SEV_FEATURES bit 8 (VmplSSS) in VMSA. VMPL SSS and nested page controlled SSS feature are mutually exclusive. If SEV_FEATURES[VmplSSS] = 1 and VMCB[SSS] = 1, VMRUN fails with #VMEXIT(VMEXIT_INV ALID).
If the VMPL SSS feature is enabled, than both supervisor and user shadow stack accesses must be to

If the VMPL SSS feature is enabled, than both supervisor and user shadow stack accesses must be to 
private memory pages. If not, a #PF exception with the reserved (RSV) error code bit set is generated in the guest.
15.36.8  Virtual Top-of-Memory 
In the VMSA of an SNP-active guest, the VIRTUAL_TOM field designates a 2MB aligned guest 
physical address called the virtual top of memory. When bit 1 (vTOM) of SEV_FEATURES is set in the VMSA of an SNP-active VM, the VIRTUAL_TOM field is used to determine the C-bit for data accesses instead of the guest page table contents. All data accesses below VIRTUAL_TOM are accessed with an effective C-bit of 1 and all addresses at or above VIRTUAL_TOM are accessed with an effective C-bit of 0. Note that page table accesses and instruction fetches always have an effective C-bit of 1, regardless of the value of VIRTUAL_TOM or whether the feature is enabled.
The Virtual TOM MSR (C001_0135) may be used to change the VIRTUAL_TOM value. CPUID 
Fn8000_001F_EAX[VirtualTom] (bit 18) = 1 indicates support for the Virtual TOM MSR. This MSR register is read-write when Virtual TOM is active, and an attempt to access it when Virtual TOM is not active will result in a #GP(0) exception. Virtual TOM MSR bits 63:52 and 20:0 are Reserved, RAZ. A WRMSR to this register flushes TLB entries belonging to the current ASID.
When virtual top of memory is enabled in SEV_FEATURES, the C-bit in the guest page table entries 
must be zero for all accesses. Any guest memory accesses with the C-bit set to 1 in the guest page tables will result in a #PF due to a reserved bit error.
15.36.9  Reflect #VC 
When running an SEV-SNP VM, the CPU generates #VC exceptions in response to events that may 
require hypervisor interaction. #VC exceptions and the events that may lead to them are discussed in Section 15.35.5. SEV-SNP VMs may either chose to handle #VC exceptions directly in their current 
guest context or turn #VC exceptions into Automatic Exits. This behavior is controlled by bit 2 (ReflectVC) of SEV_FEATURES. If this bit is set to 1, then any event that would otherwise lead to a #VC exception is instead turned into an Automatic Exit.
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When a #VC is turned into an Automatic Exit, the guest VM terminates with an exit code of 
VMEXIT_VC. The error code for the #VC, which reflects the event which led to the #VC (e.g., VMEXIT_CPUID), is saved to the GUEST_EXITCODE field in the VMSA. Additional information about the event that caused the #VC is saved to the GUEST_EXITINFO1, GUEST_EXITINFO2, GUEST_EXITINTINFO, and GUEST_NRIP fields in the VMSA. The information saved to these fields is the same as the standard exit information provided for the event that occurred. For example, if the VM performs a port I/O instruction which is marked for interception, the GUEST_EXITCODE field will be set to VMEXIT_IOIO and the GUEST_EXITINFO1 field will contain information about the I/O port access, as defined in Section 15.10.2.
The Reflect #VC feature enables #VC events to be handled by a vCPU at a VMPL other than the one 
that initiated them. For example, a guest may contain a vCPU which consists of two different VMSAs. One VMSA is defined to execute at VMPL0, while the other has ReflectVC enabled and is defined to execute at VMPL3. When the vCPU running at VMPL3 encounters a #VC condition, the information is saved to its VMSA and control is returned to the hypervisor. The hypervisor may then run the vCPU at VMPL0 which can read the exit information saved to the VMPL3 VMSA, interact with the hypervisor as required, write appropriate response data back into the VMPL3 VMSA, and instruct the hypervisor to resume execution of the vCPU at VMPL3. 
If the #VC event occurred during the processing of an interrupt or exception, the 
GUEST_EXITINTINFO.V bit will be set. If the Alternate Injection feature is enabled (see Section 15.36.15), hardware will automatically set the VINTR_CTL[BUSY] bit in the VMSA. This enables a higher privileged VMPL to re-inject the event that caused the #VC.
The GUEST_EXITCODE, GUEST_EXITINFO1, GUEST_EXITINFO2, GUEST_EXITINTINFO, 
and GUEST_NRIP fields are populated by hardware on every Automatic Exit, regardless of the ReflectVC feature. For Automatic Exits other than reflected #VCs, these fields are set to the same values that are set in the unencrypted VMCB.
15.36.10  RMP and VMPL Access Checks
When SEV-SNP is enabled globally, the processor places restrictions on all memory accesses based on 
the contents of the RMP, whether the accesses are performed by the hypervisor, a legacy guest VM, a non-SNP guest VM or an SNP-active guest VM. The processor may perform one or more of the following checks depending on the context of the access:
•RMP-Covered: Checks that the target page is covered by the RMP. A page is covered by the RMP
if its corresponding RMP entry is below RMP_END. Any page not covered by the RMP isconsidered a Hypervisor-Owned page.
•Hypervisor-Owned: Checks that if the target page is covered by the RMP then the Assigned bit ofthe target page is 0. If the page table entry that specifies the sPA indicates that the target page sizeis 2MB, then all RMP entries for the 4KB constituent pages of the target page must have theAssigned bit set to 0. Accesses to 1GB pages only install 2MB TLB entries when SEV-SNP isenabled, therefore this check treats 1GB accesses as 2MB accesses for purposes of this check.
•Guest-Owned: Checks that the ASID field of the RMP entry of the target page matches the ASIDof the current VM.
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•Reverse-Map: Checks that the Guest_Physical_Address of the RMP entry of the target page
matches the guest physical address of the translation.
•Validated: Checks that the Validated field of the RMP entry of the target page is 1.
•Mutable: Checks that the Immutable field of the RMP entry of the target page is 0.
•Page-Size: Checks that the following conditions are met:
- If the nested page table indicates a 2MB or 1GB page size, the Page_Size field of the RMP 
entry of the target page is 1.
- If the nested page table indicates a 4KB page size, the Page_Size field of the RMP entry of 
the target page is 0.
•VMPL: Checks that the VMPL permission mask allows access. See Section 15.36.7 for details.
Table 15-39 describes under which conditions each check is performed and what fault is produced on 
failure.
In addition, any memory access that results in an RMP check may result in an RMP violation (#PF or 
#VMEXIT(NPF)) if the accessed RMP entries are in use by other logical processors. In this case, software should retry the access.Table 15-39. RMP Memory Access Checks
Host/GuestSNP-
ActiveType of Access C-Bit Check Fault
Host -Data write,
Page Table Access- Hypervisor-Owned #PF
Guest NoData write,Page Table Access- Hypervisor-Owned #VMEXIT(NPF)
Guest Yes Instruction Fetch,Page Table Access -RMP-Covered,Guest-Owned,Reverse-Map,Mutable,Page-Size#VMEXIT(NPF)
Validated #VC
VMPL #VMEXIT(NPF)
Guest Yes Data write 0 Hypervisor-Owned #VMEXIT(NPF)
Guest Yes Data write, Data read 1RMP-Covered,Guest-Owned,Reverse-Map,Mutable,Page-Size#VMEXIT(NPF)
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If a memory access results in a modification of the Accessed or Dirty bits in a page table entry, this 
page table modification is treated similarly to data write accesses by SEV-SNP. For any such page table modification access, the page size of the access is inherently 4KB.
If the virtual TOM feature (see Section 15.36.8) is enabled, then the Virtual TOM setting is used to 
determine the C-bit for a given guest access. Guest physical addresses below Virtual TOM are 
considered to have a C-bit set to 1.
The following page-fault error bits are set on an RMP check related #PF:
•Bit 31 (RMP): Set to 1 if the fault was caused due to an RMP check or a VMPL check failure, 0
otherwise. All RMP violations described in this section will set this bit to 1.
Additionally, the following page-fault error bits may be set on a #VMEXIT(NPF) in EXITINFO1:
•Bit 34 (ENC): Set to 1 if the guest’s effective C-bit was 1, 0 otherwise.
•Bit 35 (SIZEM): Set to 1 if the fault was caused by a size mismatch between PV ALIDATE or
RMPADJUST and the RMP, 0 otherwise.
•Bit 36 (VMPL): Set to 1 if the fault was caused by a VMPL permission check failure, 0 otherwise.
•Bit 37 (SSS): Set to VMPL permission mask SSS (bit 4) value if VmplSSS is enabled.
The effective C-bit is always a 1 on any guest instruction fetch, page table access, or data write to private (C=1) memory.
All RMP checks described in this section occur after page table and nested page table access checks 
and have lower priority than existing paging checks. Table 15-39 reflects the relative priority of RMP

and have lower priority than existing paging checks. Table 15-39 reflects the relative priority of RMP 
checks. Namely, VMPL checks have the lowest priority, preceded by page validation checks. For example, if a guest access fails the Page-Size check and the Validated check, a #VMEXIT(NPF) will occur instead of a #VC since the Page-Size check has priority over the page validation check.
A failure of the page validation check results in a #VC with error code PAGE_NOT_V ALIDATED 
(0x404). The faulting guest virtual address is saved to CR2 when this error occurs.
15.36.11  Large Page Management 
The hypervisor may need to convert a 2MB page assigned to a guest into 4KB pages. This conversion 
is called page smashing and requires the hypervisor to alter the RMP. The hypervisor can use RMPUPDATE to alter the size of the page in the RMP, but this will clear the validated bit. 
To convert a 2MB page into 4KB pages without altering the validated status of the region, the 
hypervisor may use the PSMASH instruction. PSMASH takes a 2MB aligned system physical address and smashes the page while preserving the Validated bit in the RMP. After PSMASH successfully completes, the RMP entries of the resulting 4KB pages have the following contents:
•Consecutive values in the Guest_Physical_Address fields
•Page_Size set to 0 indicating 4KB pages
•All other RMP fields copied from the original 2MB page RMP entry
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One reason the hypervisor may need to smash a 2MB page is if the guest executes PV ALIDATE or 
RMPADJUST on a 4KB page that is backed by a 2MB page. In that case, the instructions generate a #VMEXIT(NPF) with the SIZEM bit set in EXITINFO1. To resolve this, the hypervisor can smash the page and then have the guest restart the instruction. 
If the guest wishes to validate a 2MB aligned region, the guest should first attempt to execute 
PV ALIDATE with a size of 2MB. If the page is backed by 4KB pages, PV ALIDATE terminates with a FAIL_SIZEMISMATCH error. In this case, the guest should then execute PV ALIDATE on each 4KB page individually. This allows the guest to take advantage of the more efficient 2MB mappings and avoid having the hypervisor unnecessarily smash the page. 
Table 15-40 summarizes the potential page size mismatches and how to resolve them.
The reverse operation of converting a set of consecutive 4KB pages into a single 2MB page requires 
assistance from either the guest or the AMD-SP to ensure that the operation is safe to perform.
15.36.12  Running SNP-Active Virtual Machines 
As with SEV-ES guests, SNP-active guests are described by a hypervisor controlled VMCB and a 
guest encrypted VMSA. The initial VMSA for an SNP-active guest must be set up through coordination with the AMD-SP, the details of which are beyond the scope of this manual. This includes the initial configuration of the SEV_FEATURES field in the VMSA which indicates which guest security features are enabled for that particular VM instance. VMRUN to an SNP-active guest will fail with a VMEXIT_INV ALID error code if SEV-SNP is not globally enabled.
VMRUN Checks. When SEV-SNP is globally enabled on a system, the VMRUN instruction performs 
additional security checks on various memory pages. These checks are similar to the ones described in 
Section 15.36.10. Note that where a check depends on page size, a page size of 4KB is used. In addition to the checks described in that section, an additional check exists:
•VMSA: Checks that the VMSA field in the RMP entry equals 1.
The VMSA field in an RMP entry may be set by the AMD-SP, or by a vCPU running at VMPL0 using 
the RMPADJUST instruction.Table 15-40. PVALIDATE/RMPADJUST Page Size Mismatch Combinations
Requested 
Page SizePage Size in 
RMPError Condition Recommended Handling
4KB 2MB #VMEXIT(NPF) PSMASH
2MB 4KB FAIL_SIZEMISMATCH Guest retries on each 4KB constituent page
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The checks performed on VMRUN are as follows:
The A VIC Logical Table, A VIC Physical Table, IOPM_BASE_PA, MSRPM_BASE_PA, and nCR3 
are not checked by VMRUN as these structures are only read by the hardware.
After a successful VMRUN, the VMCB page, as well as any A VIC Backing Page and VMSA Page are 
marked as in-use by hardware, and any attempt to modify the RMP entries for these pages via instructions like RMPUPDATE will result in a FAIL_INUSE response. The in-use marking is automatically cleared by hardware after a #VMEXIT event.
Other Checks. In addition to the RMP checks performed by VMRUN, a few other VM-related 
operations perform special RMP checks. 
The address written to the VM_HSA VE_PA MSR, which holds the address of the page used to save 
the host state on a VMRUN, must point to a hypervisor-owned page. If this check fails, the WRMSR will fail with a #GP(0) exception. Note that a value of 0 is not considered valid for the VM_HSA VE_PA MSR and a VMRUN that is attempted while the HSA VE_PA is 0 will fail with a #GP(0) exception.
The VMSA VE instruction also performs checks to ensure that the target page is hypervisor-owned. 
The VMSA VE instruction is not expected to be used with SEV-ES and SNP-active guests, as described in Section 15.36.8, but may be used with other guests. 
If VMSA VE is executed in host mode and the target page fails the RMP check, a #GP(0) exception is generated. If VMSA VE is executed in a guest when the VMSA VE instruction is virtualized (see Section 15.33.1) and the target page fails the RMP check, then a #VMEXIT(NPF) is generated 
indicating an RMP permission error. In processors that support SEV-SNP, the execution of the VMSA VE instruction inside an SEV-ES or SNP-active guest is not supported and will result in a #VMEXIT(VMSA VE). 
Intercept Behavior.  All port I/O (IN, INS, OUT, OUTS) and CPUID instructions executed by an 
SNP-Active guest are treated as intercepted regardless of the intercept bits set in the VMCB and 
IOPM. Execution of these instructions in an SNP-Active guest will unconditionally generate a Non-Automatic Exit. Table 15-41. VMRUN Page Checks
Page Type SNP-Active Check Fault
VMCB - Hypervisor-Owned #GP(0)
A VIC Backing Page - Hypervisor-Owned #VMEXIT(VMEXIT_INV ALID)
VMSA No Hypervisor-Owned #VMEXIT(VMEXIT_INV ALID)
VMSA YesRMP-Covered
Guest-OwnedReverse-MapMutableVMSA#VMEXIT(VMEXIT_INV ALID)
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15.36.13  Debug Registers 
SEV-ES and SNP-active guests may choose to enable full virtualization of CPU debug registers 
through SEV_FEATURES bit 5 (DebugSwap). 
When enabled, the DR[0-3] registers and DR[0-3]_ADDR_MASK registers are swapped as type ‘B’ 
state (see Appendix B). 
15.36.14  Memory Types 
When an SNP-active guest accesses memory, the hardware forces the use of coherent memory types. 
This prevents the hypervisor from attempting to corrupt guest memory by the use of non-coherent memory types for accesses by the guest. 
If a guest memory access is determined to be non-coherent after the memory type determination logic 
described in Section 15.25.8, the hardware forces a coherent type as described in Table 15-42.
15.36.15  TLB management 
For non-SNP-active guests, when a hypervisor moves a VMSA to a new logical processor it must 
ensure that the VMSA cannot use any stale (incorrect) TLB translations to prevent corruption of the 
guest. For SNP-active guests, to avoid any dependency on the hypervisor for correctly managing guest TLB contents, the hardware detects when the VMSA is moved and manages the TLB for that guest automatically. The hardware uses two VMSA fields to track this information: the TLB_ID (byte offset 3D0h) and the PCPU_ID (byte offset 3D8h). 
During guest creation, software should initialize the TLB_ID and PCPU_ID by setting both to zero. 
The hardware subsequently manages the values in both fields throughout the lifetime of that VMSA. During operation, software may explicitly write PCPU_ID to 0 to force a TLB flush on the next VMRUN to that VMSA if desired. If this occurs, the hardware will set the PCPU_ID field to a non-zero value when it flushes the TLB.
For example, when guest software performs an RMPADJUST to alter the permissions of a VMPL, it 
may need to ensure that the existing TLB entries of all vCPUs executing at the targeted VMPL are not used anymore. The guest software can do this by writing zero to PCPU_ID of the affected VMSAs. When these VMSAs are re-entered with VMRUN, the hardware will ensure existing TLB entries are no longer used and set PCPU_ID to a non-zero value. This value can be checked for non-zero by the guest software to ensure the operation has completed before proceeding.
As with any guest, the hypervisor may use the TLB_CONTROL field in the VMCB to force TLB 
flushes when desired. When the hypervisor writes 3h or 7h to TLB_CONTROL, both global and non-global TLB entries of the guest are invalidated.Table 15 -42. Non-Coherent Memory Type Conversion
Non-Coherent Memory Type Forced Coherent Memory Type
UC CD
WC WC+

UC CD
WC WC+
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15.36.16  Interrupt Injection Restrictions 
SNP-active guests may choose to enable the Restricted Injection or Alternate Injection features 
through SEV_FEATURES bits 3 and 4 respectively. These features enforce additional interrupt and event injection security protections designed to help protect against malicious injection attacks. The two are mutually exclusive for a specific VMSA and an attempt to enable both will result in a #VMEXIT(VMEXIT_INV ALID) when the VMRUN instruction is executed.
Restricted Injection Operation.  This feature disables all hypervisor-based interrupt queuing and 
event injection of all vectors except a new exception vector, #HV (28), which is reserved for SNP 
guest use, but never generated by hardware. #HV is only allowed to be injected into VMSAs that 
execute with Restricted Injection. #HV is a benign exception and can only be injected as an exception (VMCB.EVENTINJ[Type]=3) and without an error code. Guests running with Restricted Injection are expected to communicate with the hypervisor about events via a software-managed para-virtualization interface. This interface can use #HV injection as a doorbell to inform the guest that new events have been added.
The VMRUN instruction with Restricted Injection enabled will fail with a VMEXIT_INV ALID error 
code if the hypervisor attempts the injection of any unsupported event or attempts to run the guest with A VIC enabled. 
Alternate Injection Operation.  This feature replaces all hypervisor-based interrupt queuing and 
event injection with guest-controlled queuing and injection. When this is enabled on a VMSA, event 
injection information on VMRUN is read from the EventInjCtrl field in the VMSA (offset 3E0h) and interrupt queuing information is read from the VIntrCtrl field in the VMSA (offset 3B8h). This feature is intended to be used in a multi-VMPL architecture where a high privilege VMSA injects events and 
interrupts directly into a low privilege VMSA by writing to its encrypted VMSA. 
When Alternate Injection is enabled, the EventInjCtlr field in the unencrypted VMCB (offset A8h) is ignored on VMRUN. The VIntrCtrl field in the unencrypted VMCB (offset 70h) is processed, but only the V_INTR_MASKING, Virtual GIF Mode, and A VIC Enable bits are used. The A VIC Enable bit must be 0 if the guest is running with Alternate Injection enabled, otherwise the VMRUN will fail with a VMEXIT_INV ALID error code.
The remaining fields of VIntrCtrl (V_TPR, V_IRQ, VGIF, V_INTR_PRIO, V_IGN_TPR, 
V_INTR_VECTOR, V_NMI, V_NMI_MASK, V_NMI_EN) are read exclusively from the encrypted version in the VMSA. Additionally, bit 10 of the encrypted VIntrCtrl field is defined as the INT_SHADOW bit and the unencrypted INT_SHADOW bit in VMCB offset 68h bit 0 is ignored. On a VMEXIT, the V_TPR, V_IRQ, V_NMI, V_NMI_MASK, and INT_SHADOW values are written back to the encrypted VIntrCtrl only.
In guests that run with Alternate Injection, bit 63 of the encrypted VIntrCtrl field is defined as a BUSY 
bit. On VMRUN, if VIntrCtrl[BUSY] is set to 1, then the VMRUN fails with a VMEXIT_BUSY error code. The BUSY bit enables a VMSA to be temporarily marked non-runnable while software modifications are in progress.
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Additional Intercept Behavior.  Additional hardware-forced intercept behavior exists in guests that 
run with either of these features enabled:
•For either feature, hardware treats physical INTR, NMI, INIT, and #MC events as intercepted
regardless of the intercept bit set in the VMCB. 
•Under Alternate Injection, any MSR access to the x2APIC MSR range (MSR 0x800-0x8FF) by theguest is intercepted regardless of the MSR_PROT intercept and MSR protection bitmap. In thiscase, the interception behavior is the same as what would occur if the MSR bitmap indicated aninterception of the corresponding MSR.
15.36.17  Side-Channel Protection 
SEV-SNP provides optional protections against certain side channel attacks. Branch Target Buffer Isolation SNP-active guests may choose to enable the Branch Target Buffer Isolation mode through 
SEV_FEATURES bit 7 (BTBIsolation). The Branch Target Buffer (BTB) is an internal CPU structure that is used when predicting indirect branches, and SNP-active guests may choose to impose additional restrictions on it in order to help prevent certain types of speculative execution-based side channels.
When executing an SNP-active guest when BTB Isolation is enabled, CPU hardware will ensure that 
no code outside of that guest context is able to influence the BTB-based predictions performed by hardware within the guest. Hardware tracks the source of prediction information in the BTB and may flush BTB contents when required to maintain this isolation.
In hardware that supports BTB Isolation, new BTB prediction information is never written if 
SPEC_CTRL[IBRS] is enabled in the current context. Therefore, it is recommended that non-guest software that executes temporarily (e.g., hypervisor exit handling code) run with SPEC_CTRL[IBRS] set to 1. This ensures that indirect branch information from that context is not stored in the BTB and may avoid the need for a BTB flush when guest execution is resumed.
Instruction Based Sampling SEV-ES and SNP-active guests may choose to disallow the use of Instruction Based Sampling (IBS) 
by the hypervisor in order to limit the information that may be gathered about their execution. Guests may enable this restriction through SEV_FEATURES bit 6 (PreventHostIBS). When a VMRUN is executed on a guest that has enabled this protection, the IbsFetchCtl[IbsFetchEn] and IbsOpCtl[IbsOpEn] MSR bits must be 0. If either of these bits are not 0 then the VMRUN will fail with a VMEXIT_INV ALID error code.
VMSA Register ProtectionSNP-active guests may choose to enable the VMSA Register Protection feature through 
SEV_FEATURES bit 14 (VmsaRegProt). When an Automatic Exit occurs and this feature is enabled, CPU hardware will obfuscate the values of certain registers before they are written to the VMSA. The 
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hardware will then deobfuscate these values on a subsequent VMRUN. This obfuscation may help 
prevent certain types of side channel attacks on the encrypted VMSA ciphertext.
The obfuscation is performed with a bit-wise XOR operation between the register value and an 8B 
nonce. The nonce value is stored in the VMSA and is updated in a pseudo-random manner by the CPU hardware on every Automatic Exit. When initializing a new VMSA, it is recommended that the nonce is set to a random value.
The specific VMSA fields which are obfuscated when this feature is enabled may vary by 
implementation. More information about this may be found in the AMD-SP SEV-SNP ABI specification. 
SMT ProtectionThe SMT Protection feature allows SEV-SNP VMs to require the sibling thread to be idle while the 
VM is being run. This ensures that malicious code is not executed by the sibling thread and therefore provides mitigation for potential side channel attacks related to shared core resources. The hypervisor 
must execute the HLT instruction or request an I/O C-state on the sibling thread prior to executing the 
VMRUN instruction to run an SEV-SNP vCPU with the SMT Protection feature enabled.
SNP-active guests may choose to enable the SMT Protection feature through SEV_FEATURES bit 15 
(SmtProtection). Support for the SMT Protection feature is indicated by CPUID Fn8000_001F_EAX[25](SmtProtection)=1.
When the hypervisor executes VMRUN to run an SNP-active guest with SMT Protection enabled, the 
processor checks if the sibling thread is in an idle state and in host mode. If not, the VMRUN fails with a VMEXIT_IDLE_REQUIRED error code.
When a thread is in the idle state and the sibling thread is in guest mode with SMT Protection active, 
the thread in the idle state does not immediately exit the idle state upon receiving a wake up event, 
such as an interrupt. Instead, the processor writes the APIC ICR register with the IDLE_WAKEUP_ICR MSR value and remains in the idle state until the sibling thread enters host mode. The write is done once and only if x2APIC mode is enabled. It is recommended that hypervisor software program the HLT_WAKEUP_ICR value to send an IPI to the sibling thread in order to force it to enter host mode.
The IDLE_WAKEUP_ICR MSR (C001_0137h) has the same layout and access properties as the 
x2APIC Interrupt Command Register (ICR) MSR (see Section 16.13).
15.36.18  Secure TSC
SNP-active guests may choose to enable the Secure TSC feature through SEV_FEATURES bit 9 
(SecureTscEn). When enabled, Secure TSC changes the guest view of the Time Stamp Counter when

(SecureTscEn). When enabled, Secure TSC changes the guest view of the Time Stamp Counter when 
read by the guest via either the TSC MSR, RDTSC, or RDTSCP instructions. The TSC value is first scaled with the GUEST_TSC_SCALE value from the VMSA and then is added to the VMSA GUEST_TSC_OFFSET value. The P0 frequency, TSC_RATIO (C001_0104h) and TSC_OFFSET (VMCB offset 50h) values are not used in the calculation.
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The GUEST_TSC_SCALE is an 8.32 fixed point binary number which is composed of 8 bits of 
integer and 32 bits of fraction. The AMD-SP SEV-SNP ABI specification provides additional information about the Secure TSC feature and initialization of GUEST_TSC_SCALE.
Guests that run with Secure TSC enabled may read the GUEST_TSC_FREQ MSR (C001_0134h) 
which returns the effective frequency in MHz of the guest view of TSC. This MSR is read-only and attempting to write the MSR or read it when outside of a guest with Secure TSC enabled causes a #GP(0) exception.
Guests that run with Secure TSC enabled are not expected to perform writes to the TSC MSR (10h). If 
such a write occurs, subsequent TSC values read are undefined.
15.36.19  SEV-SNP Instruction Virtualization
The hypervisor uses RMPUPDATE and PSMASH instructions to modify the RMP table when 
SEV-SNP is enabled. In a nested virtualization use case, when the hypervisor is running as a guest, 
these instructions should be replaced with WRMSR  VIRT_RMPUPDATE MSR (C001_F001h) and WRMSR VIRT_PSMASH MSR (C001_F002h), respectively.  The VIRT_RMPUPDATE MSR, VIRT_PSMASH MSR and CPUID Fn8000_001F_EAX[NestedVirtSnpMsr] (bit 29), which reports VIRT_RMPUPDATE and VIRT_PSMASH MSR support, are not implemented in the processor and are expected to be emulated by the top-level hypervisor.
VIRT_RMPUPDATE MSR input convention:
RAX: 4KB aligned GPA
RDX: New RMP entry, bytes 7:0R8: New RMP entry, bytes 15:8
VIRT_RMPUPDATE MSR output convention:
RAX: RMPUPDATE return code
VIRT_PSMASH MSR input convention:
RAX: 2MB aligned GPA
VIRT_PSMASH MSR output convention:
RAX: PSMASH return code
15.37 SPEC_CTRL Virtualization 
A hypervisor may wish to impose speculation controls on guest execution or a guest may want to 
impose its own speculation controls. Therefore, the processor implements both host and guest versions of SPEC_CTRL. The presence of this feature is indicated by CPUID Fn8000_000A_EDX[20]=1.
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When in host mode, the host SPEC_CTRL value is in effect and writes update only the host version of 
SPEC_CTRL. On a VMRUN, the processor loads the guest version of SPEC_CTRL from the VMCB. For most guests, processor behavior is controlled by the logical OR of the two registers. When the guest writes SPEC_CTRL, only the guest version is updated. On a VMEXIT, the guest version is saved into the VMCB and the processor returns to only using the host SPEC_CTRL for speculation control. 
SNP-active guests with BTB isolation enabled behave differently (see section 15.36.17). For these 
guests the host value of IBRS does not override the guest value.
15.38 Instruction-Based Sampling Virtualization
Hardware support for Instruction-Based Sampling (IBS) virtualization is reported by CPUID Fn8000_000A_EDX[IbsVirt] (bit 26) = 1. IBS virtualization is enabled when bit 2 at offset B8h in the VMCB is set to 1 for non SEV-ES guests and when bit 12 in SEV_FEATURES in VMSA is set to 1 for SEV-ES guests.
When a VMRUN is executed to an SEV-ES guest with IBS virtualization enabled, the 
IbsFetchCtl[IbsFetchEn] and IbsOpCtl[IbsOpEn] MSR bits must be 0. If either of these bits are not 0, the VMRUN will fail with a VMEXIT_INV ALID error code.
The following fields are allocated in the VMCB and VMSA state save area to hold the guest values of 
the fetch and op IBS registers:
•IBS_FETCH_CTL — IbsFetchCtl MSR
•IBS_FETCH_LINADDR — IbsFetchLinAd MSR
•IBS_OP_CTL — IbsOpCtl MSR
•IBS_OP_RIP — IbsOpRip MSR
•IBS_OP_DATA — IbsOpData1 MSR
•IBS_OP_DATA2 — IbsOpData2 MSR
•IBS_OP_DATA3 — IbsOpData3 MSR
•IBS_DC_LINADDR — IbsDcLinAd MSR
•BP_IBSTGT_RIP — IbsBrTarget MSR
•IC_IBS_EXTD_CTL — IbsFetchExtdCtl MSR
With IBS virtualization enabled, a guest is not able to read a physical address from either 
IbsFetchPhysAd MSR or IbsDcPhysAd MSR. Both registers return zero when read by the guest and the associated valid bits IbsFetchCtl[IbsPhyAddrValid] and IbsOpData3[IbsDcPhyAddrValid] respectively, return zero. Writes to IbsFetchPhysAd MSR and IbsDcPhysAd MSR within the guest are ignored.
IBS virtualization requires the use of A VIC (see section Section 15.29, “Advanced Virtual Interrupt 
Controller,” on page 562) or NMI virtualization (see Section 15.21.10, “NMI Virtualization,” on 
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page 535) for delivery of a virtualized interrupt from the IBS hardware in the guest. Without 
virtualized interrupt delivery an IBS interrupt occurring in the guest will not be delivered to either the guest or the hypervisor. When A VIC is enabled, the IBS LVT entry (Extended Interrupt 0 LVT) message type should be programmed to INTR or NMI. 
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16 Advanced Programmable Interrupt 
Controller (APIC)
The Advanced Programmable Interrupt Controller (APIC) provides interrupt support on AMD64 
architecture processors. The local APIC accepts interrupts from the system and delivers them to the local CPU core interrupt handler. 
Support for APIC is indicated by CPUID Fn0000_0001_EDX[APIC] = 1. For information on using 
the CPUID instruction to obtain processor implementation information, see Section 3.3, “Processor 
Feature Identification,” on page 71.
The APIC block diagram is provided in Figure 16 -1. 
Figure 16-1. Block Diagram of a Typical APIC ImplementationLocal
APICLocal
APICLocal
APICCPU#1
Interrupt
HandlerCPU#2
CPU
CoreCPU#N
 Interrupt Messages
IOAPIC PIC I/O Interrupts Interrupt Messages
Legacy
InterruptsAPIC Timer
PerfMonCntr
ThermalSensor
Extended Intr
SignaledMessage
InterruptsAPIC ErrorCPU
CoreCPU
Core
Interrupt
HandlerInterrupt
Handler
APIC Timer
APIC ErrorAPIC Timer
APIC Error
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16.1 Sources of Interrupts to the Local APIC
Each CPU core has an associated local APIC which receives interrupts from the following sources:
•I/O interrupts from the IOAPIC interrupt controller (including LINT0 and LINT1)
•Legacy interrupts (INTR and NMI) from the legacy interrupt controller
•Message Signalled Interrupts 
•Interprocessor Interrupts (IPIs) from other local APICs. Interprocessor Interrupts are used to send
interrupts or to execute system wide functions between CPU cores in the system, including theoriginating CPU core (self-interrupt).
•Locally generated interrupts within the local APIC. The local APIC receives local interrupts fromthe APIC timer, Performance Monitor Counters, thermal sensors, APIC errors and extendedinterrupts from implementation specific sources.
The sources of interrupts for the local APIC are provided in Table 16 -1.
Table 16-1. Interrupt Sources for Local APIC
16.2 Interrupt Control
I/O, legacy, and interprocessor interrupts are sent via interrupt messages. The interrupt messages contain the following information:Source DescriptionMessage Type to 
Local APIC
I/O interruptsSystem interrupts from I/O devices or system hardware 
received through the I/O APIC and sent to the local APIC as interrupt messages. They may be edge-triggered or level-sensitive.Fixed, Lowest Priority, SMI, 
NMI, INIT, STARTUP, Exter -
nal interrupt, LINT0, LINT1
Legacy InterruptsLegacy interrupts (INT and NMI) from the PIC and sent to the local APIC as interrupt messages.NMI, INT
Interprocessor (IPI)Interprocessor interrupts. Used for interrupt forwarding, system-wide functions, or software self-interrupts.Fixed, lowest priority, SMI, 
read request, NMI, INIT, 
STARTUP, External interrupt
APIC TimerLocal interrupt from the programmed APIC timer reaches zero, under control of TIMER_LVT.Fixed
Performance Monitor CounterLocal interrupt from the performance monitoring counter when it overflows, under control of PERF_CNT_LVT.Fixed, SMI, or NMI
Thermal SensorLocal interrupt from internal thermal sensors when it has tripped, under control of THERMAL_LVT.Fixed, SMI, or NMI
Extended Interrupt[3:0]Local Interrupts from programmable internal CPU core sources, under the control of the EXTENDED_INTERRUPT[3:0]_LVT.Fixed, SMI, NMI, or 
External interrupt
APIC Internal ErrorLocal interrupt when an error is detected within the local APIC, under control of ERROR_LVT.Fixed, SMI, or NMI

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•Destination address of the local APIC.
•VECTOR[7:0] indicating interrupt priority of up to 256 interrupt vectors. This information is
captured in the IRR register for Fixed and Lowest Priority interrupt message types. 
•Trigger Mode indicating edge triggered or level-sensitive (which requires an EOI response to thesource).
•Message Type[3:0] indicating the type of interrupt to be presented to the local APIC. For Fixed andLowest Priority message types, the interrupt is processed through the target local APIC. For allother message types, the interrupt is sent directly to the destination CPU core. There is a 5-lineinterrupt interface to the CPU core for INTR, SMI, NMI, INIT and STARTUP interrupts. Forlocally-generated interrupts, control is provided by local vector tables or LVTs. Separate LVTs areprovided for each interrupt source, allowing for a unique entry point for each source. The LVTcontains the VECTOR[7:0], trigger mode and message type as well as other fields associated withthe specific interrupt. The message type may be Fixed, SMI, NMI, or External interrupt. A Maskbit is also provided to mask the interrupt.
16.3 Local APIC
16.3.1  Local APIC Enable
The local APIC is controlled by the APIC enable bit (AE) in the APIC Base Address Register 
(MSR 0000_001Bh). See Figure 16 -2 on page 623.
When AE is set to 1, the local APIC is enabled and all interrupt types are accepted. When AE is cleared to 0, the local APIC is disabled, including all local vector table interrupts. 
Software can disable the local APIC, using the APIC_SW_EN bit in the Spurious Interrupt Vector 
Register (APIC_F0). When this bit is cleared to zero, the local APIC is temporarily disabled:
•SMI, NMI, INIT, Startup, and Remote Read interrupts may be accepted.
•Pending interrupts in the ISR and IRR are held.
•Further fixed, lowest-priority, and ExtInt interrupts are not accepted.
•All LVT entry mask bits are set and cannot be cleared.
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Figure 16-2. APIC Base Address Register (MSR 0000_001Bh)
The fields within the APIC Base Address register are as follows:
•Boot Strap CPU Core (BSC) —Bit 8. The BSC bit indicates that this CPU core is the boot core of
the BSP. Each CPU core that is not the boot core of the boot processor is an AP (Application
Processor). 
•APIC Enable (AE) —Bit 11. This is the APIC enable bit. The local APIC is enabled and all
interruption types are accepted when AE is set to 1. Clearing AE to 0 disables the local APIC, andno local vector table interrupts are supported.
•APIC Base Address (ABA) —Bits 51:12. Specifies the base physical address for the APIC register
set. The address is extended by 12 bits at the least-significant end to form the 52-bit physical baseaddress. The reset value of the APIC base address is 0_0000_FEE0_0000h. This address is notaffected by INIT.
Note that a given processor may implement a physical address less than 52 bits in length.
16.3.2  APIC Registers
The system programming interface of the local APIC is made up of the registers listed in Table 16 -2 
below. All APIC registers are memory-mapped into the 4-Kbyte APIC register space, and are accessed 
with memory reads and writes. The memory address is indicated as:
APIC Register address = APIC Base Address + Offset
where the APIC Base Address must point to an uncacheable memory region, and is located in APIC Base Address Register, MSR 0000_001Bh. See Figure 16 -2.63 52 51 32
Reserved ABA[51:32]
ABA[31:12]
AE
EXTD
Reserved
BSCReserved
51:12 ABA APIC Base Address R/W
11 AE APIC Enable R/W
10 EXTD x2APIC Mode Enable R/W
8 BSC Boot Strap CPU Core RO
7:0 Reserved MBZ
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APIC registers are aligned to 16-byte offsets and must be accessed using naturally-aligned DWORD 
size read and writes. All other accesses cause undefined behavior. 
The table includes the value of each register after reset and INIT. 
Table 16-2. APIC Registers
Offset Name Reset
20h APIC ID Register  ??000000h
30h APIC Version Register 80??0010h
80h Task Priority Register (TPR) 00000000h
90h Arbitration Priority Register (APR) 00000000h
A0h Processor Priority Register (PPR) 00000000h
B0h End of Interrupt Register (EOI) –
C0h Remote Read Register 00000000h
D0h Logical Destination Register (LDR) 00000000h
E0h Destination Format Register (DFR) FFFFFFFF
F0h Spurious Interrupt Vector Register 000000FFh
100-170h In-Service Register (ISR) 00000000h
180-1F0h Trigger Mode Register (TMR) 00000000h
200-270h Interrupt Request Register (IRR) 00000000h
280h Error Status Register (ESR) 00000000h
300h Interrupt Command Register Low (bits 31:0) 00000000h
310h Interrupt Command Register High (bits 63:32) 00000000h
320h Timer Local Vector Table Entry 00010000h
330h Thermal Local Vector Table Entry 00010000h
340h Performance Counter Local Vector Table Entry 00010000h
350h Local Interrupt 0 Vector Table Entry 00010000h
360h Local Interrupt 1 Vector Table Entry 00010000h
370h Error Vector Table Entry 00010000h
380h Timer Initial Count Register 00000000h
390h Timer Current Count Register 00000000h
3E0h Timer Divide Configuration Register 00000000h
400h Extended APIC Feature Register 00040007h
410h Extended APIC Control Register 00000000h
420h Specific End of Interrupt Register (SEOI) –
480-4F0h Interrupt Enable Registers (IER) FFFFFFFFh
500-530h Extended Interrupt [3:0] Local Vector Table Registers 00000000h
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16.3.3  Local APIC ID
Unique local APIC IDs are assigned to each CPU core in the system. The value is determined by 
hardware, based on the number of CPU cores on the processor and the node ID of the processor. 
The APIC ID is located in the APIC ID register at APIC offset 20h. See Figure 16 -3. It is model 
dependent, whether software can modify the APIC ID Register. The initial value of the APIC ID (after 
a reset) is the value returned in CPUID function 0000_0001h_EBX[31:24].
Figure 16-3. APIC ID Register (APIC Offset 20h) 
•APIC ID (AID) —Bits 31:24. The APIC ID field contains the unique APIC ID value assigned to
this specific CPU core. A given implementation may use some bits to represent the CPU core andother bits represent the processor.
16.3.4  APIC Version Register
A version register is provided to allow software to identify which APIC version is used. Bits 7:0 of the 
APIC Version Register indicate the version number of the APIC implementation. 
The number of entries in the local vector table are specified in bits 23:16 of the register as the 
maximum number minus one.
Bit 31 indicates the presence of extended APIC registers which have an offset starting at 400h.
 
Figure 16 -4. APIC Version Register (APIC Offset 30h)31 24 23 0
AID Reserved
31:24 AID APIC ID R/W
23:0 Reserved MBZ
31 30 24 23 16 15 8 7 0EASReserved MLE Reserved VER
31 EAS Extended APIC Register Space Present RO
30:24 Reserved MBZ
23:16 MLE Max LVT Entries RO
15:8 Reserved MBZ
7:0 VER Version RO
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The fields within the APIC Version register are as follows:
•Version (VER) —Bits 7:0. The VER field indicates the version number of the APIC
implementation. The local APIC implementation is identified with a value=1Xh (20h-FFh are
reserved).
•Max LVT Entries (MLE) —Bits 23:16. The MLE field specifies the number of entries in the local
vector table minus one.
•Extended APIC Register Space Present (EAS) —Bit 31. The EAS bit when set to 1 indicates the
presence of an extended APIC register space, starting at offset 400h.
16.3.5  Extended APIC Feature Register
The Extended APIC Feature Register indicates the number of extended Local Vector Table registers in 
the local APIC, whether the Interrupt Enable Registers are present, and whether the 8-bit Extended APIC ID and Specific End Of Interrupt (SEOI) Register are supported.
Figure 16-5. Extended APIC Feature Register (APIC Offset 400h)
•Extended LVT Count (XLC)—(Bits 23:16) Specifies the number of extended local vector tableregisters in the local APIC.
•Extended APIC ID Capability (XAIDC)—(Bit 2) Indicates that the processor is capable ofsupporting an 8-bit APIC ID.
•Specific End of Interrupt Capable—(Bit 1) Indicates that the Specific End Of Interrupt Register ispresent.
•Interrupt Enable Register Capable—(Bit 0) Read-only. Indicates that the Interrupt EnableRegisters are present. 
16.3.6  Extended APIC Control Register
This bit enables writes to the interrupt enable registers.31 24 23 16 15 3 2 1 0
Reserved XLC Reserved
XAIDC
SNIC
INC
31:24 Reserved MBZ

XAIDC
SNIC
INC
23:16 XLC Extended LVT Count RO
15:3 Reserved MBZ
2 XAIDC Extended APIC ID Capable RO
1 SNIC Specific End of Interrupt Capable RO
0 INC Interrupt Enable Register Capable RO
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Figure 16-6. Extended APIC Control Register (APIC Offset 410h)
•Extended APIC ID Enable (XAIDN)—Bit 2. Setting XAIDN to 1 enables the upper four bits of the
APIC ID field described in “APIC ID Register (APIC Offset 20h)” on page 625. Clearing this bit,specifies a 4-bit APIC ID using only the lower four bits of the APIC ID field of the APIC IDregister.
•Enable SEOI Generation (SN)—Bit 1. Read-write. This bit enables Specific End of Interrupt(SEOI) generation when a write to the specific end of interrupt register is received.
•Enable Interrupt Enable Registers (IERN)—Bit 0. This bit enables writes to the interrupt enableregisters.
16.4 Local Interrupts
The local APIC handles the following local interrupts:
•APIC Timer
•Local Interrupt 0 (LINT0) 
•Local Interrupt 1 (LINT1) 
•Performance Monitor Counters
•Thermal Sensors
•APIC internal error 
•Extended (Implementation dependent)
A separate entry in the local vector table is provided for each interrupt to allow software to specify:•Whether the interrupt is masked or not.
•The delivery status of the interrupt.
•The message type.
•The unique address vector. 
•For LINT0 and LINT1 interrupts, the trigger mode, remote IRR, and input pin polarity.31 3 2 1 0
Reserved
XAIDN
SN
IERN
31:3 Reserved MBZ
2 XAIDN Extended APIC ID Enable. R/W
1 SN Enable SEOI Generation R/W
0 IERN Enable Interrupt Enable Registers R/W
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•For the APIC timer interrupt, the timer mode.
The general format of a Local Vector Table Register is shown in Figure 16 -7.
Figure 16 -7. General Local Vector Table Register Format
The fields within the General Local Vector Table register are as follows:
•Vector (VEC) —Bits 7:0. The VEC field contains the vector that is sent for this interrupt source
when the message type is fixed. It is ignored when the message type is NMI and is set to 00h when
the message type is SMI. Valid values for the vector field are from 16 to 255. A value of 0 to 15when the message type is fixed results in an illegal vector APIC error.
•Message Type (MT) —Bits 10:8. The MT field specifies the delivery mode sent to the CPU core
interrupt handler. The legal values are:
- 000b = Fixed - The vector field specifies the interrupt delivered.- 010b = SMI - An SMI interrupt is delivered. In this case, the vector field should be set to 00h.- 100b = NMI - A NMI interrupt is delivered with the vector field being ignored.- 111b = External interrupt is delivered.
•Delivery Status (DS) —Bit 12. The DS bit indicates the interrupt delivery status. The DS bit is set to
1 when the interrupt is pending at the CPU core interrupt handler. After a successful delivery of the
interrupt, the associated bit in the IRR is set and this bit is cleared to zero. See Section 16.6.2,“Lowest Priority Messages and Arbitration,” on page 639 for details. The bit is cleared to 0 whenthe interrupt is idle.
•Remote IRR (RIR) —Bit 14. The RIR bit is set to 1 when the local APIC accepts an LINT0 or
LINT1 interrupt with the trigger mode=1 (level sensitive). The bit is cleared to 0 when the interruptcompletes, as indicated when an EOI is received.31 18 17 16 15 14 13 12 11 10 8 7 0
Reserved
TMM
M
TGM
RIR
Reserved
DS
ReservedMT VEC
31:18 Reserved  MBZ
17 TMM Timer Mode R/W
16 M Mask R/W
15 TGM Trigger Mode R/W
14 RIR Remote IRR RO
13 Reserved MBZ
12 DS Delivery Status RO
11 Reserved MBZ
10:8 MT Message Type R/W
7:0 VEC Vector R/W
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•Trigger Mode (TGM) —Bit 15. Specifies how interrupts to the local APIC are triggered. The TGM
bit is set to 1 when the interrupt is level-sensitive. It is cleared to 0 when the interrupt is edge-
triggered. When the message type is SMI or NMI, the trigger mode is edge triggered.
•Mask (M) —Bit 16. When the M bit is set to 1, reception of the interrupt is disabled. When the M
bit is cleared to 0, reception of the interrupt is enabled.
•Timer Mode (TMM) —Bit 17. Specifies the timer mode for the APIC Timer interrupt. The TMM bit
set to 1 indicates periodic timer interrupts. The TMM bit cleared to 0 indicates one-shot operation.
16.4.1  APIC Timer Interrupt
The APIC timer is a programmable 32-bit counter used by software to time operations or events. The 
timer can operate in two modes, periodic and one-shot, under the control of bit 17 (Timer Mode) in APIC Timer Local Vector Table Register (see Figure 16 -8). In both modes, the APIC timer is set to a 
programmable initial value and starts to decrement at a programmable clock rate. When the Initial Count Register is written to a non-zero value, the APIC timer is initialized to the value just written and starts decrementing. When the Initial Count Register is written to zero, the APIC timer is initialized to zero and stops decrementing. In one-shot mode, the APIC timer stops counting when the timer reaches zero. In periodic mode, the APIC timer is initialized again when it reaches zero, and it starts to decrement again. Whenever the timer value is decremented to zero, an APIC timer interrupt is generated under the control of bit 16 (Mask) in the APIC Timer Local Vector Table Register.
To avoid race conditions, software should initialize the Divide Configuration Register and the Timer 
Local Vector Table Register prior to writing the Initial Count Register to start the timer.
Figure 16-8. APIC Timer Local Vector Table Register (APIC Offset 320h)
Three APIC registers are defined for the APIC timer function:
•Current Count Register (CCR) is the actual APIC timer. Whenever the ICR is written to a non-zero
value, or when the CCR reaches zero while in periodic mode, it is initialized to a start count loadedfrom the ICR and then decrements. The APIC timer interrupt is generated when the CCR valuereaches zero. The counting rate is controlled by the DCR. See Figure 16 -9. 
•Initial Count Register (ICR) provides the initial value for the APIC timer. See Table 16 -10.
•Divide Configuration Register (DCR) controls the counting rate of the APIC timer by dividing theCPU core clock by a programmable amount. See Figure 16 -11. For the specific details on the
implementation of the APIC timer base clock rate, see the BIOS and Kernel Developer’s Guide
(BKDG) or Processor Programming Reference Manual applicable to your product.31 18 17 16 15 13 12 11 8 7 0
Reserved
TMM
MReserved
DSReserved VEC
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Figure 16-9. Timer Current Count Register (APIC Offset 390h)
•APIC Timer Current Count (APICTCC) —Bits 31:0. The APICTCC field contains the current
value of the APIC timer.
Figure 16-10. Timer Initial Count Register (APIC Offset 380h)
•APIC Timer Initial Count (APICTIC)—Bits 31:0. The APICTIC field contains the value that is
loaded into the APIC Timer Current Count Register when the APIC timer is initialized.
Figure 16 -11. Divide Configuration Register (APIC Offset 3E0h)
•Divide Value (DV) —Bits 3, 1:0. The DV field specifies the value of the CPU core clock divisor.
Table 16 -3 lists the allowable values.31 0
APICTCC
31:0 APICTCC APIC Timer Current Count RO
31 0
APICTIC
31:0 APICTIC APIC Timer Initial Count R/W
31 4 3 2 1 0
Reserved
DV[2]
ReservedDV[1:0]
31:4 Reserved MBZ
3 DV[2] Divide Value[2] R/W
2 Reserved , MBZ
1:0 DV[1:0] Divide Value[1:0] R/W
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Table 16-3. Divide Values 
16.4.2  Local Interrupts LINT0 and LINT1
When the target local APIC receives an interrupt message from an IOAPIC with the LINT0 or LINT1 
message type, the appropriate local interrupt is generated under the control of bit 16 (Mask) in the APIC LINT0 or LINT1 Local Vector Table Register. See Figure 16 -12. 
Figure 16-12. Local Interrupt 0/1 (LINT0/1) Local Vector Table Register
(APIC Offset 350h/360h)
In addition to the normal LVT control bits (mask, delivery status and vector offset), the LINT0/LINT1 interrupts provide the following controls:
•Trigger Mode - indicates whether the interrupt pin is edge triggered or level sensitive when the
message type is fixed.
•Remote IRR - When the trigger mode indicates level, this flag is set when the local APIC acceptsthe interrupt, and is reset when the local APIC receives an EOI. When the flag is set, no additionallocal interrupt requests are sent to the local APIC, and they remain pending. 
16.4.3  Performance Monitor Counter Interrupts

When a performance monitor counter overflows, an APIC interrupt is generated under the control of 
bit 16 (Mask) in the APIC Performance Monitor Counter Local Vector Table Register. See Figure 16 -13 on page 631. 
(APIC Offset 340h)Bits 3, 1:0 Resulting Timer Divide
000b Divide by 2
001b Divide by 4010b Divide by 8011b Divide by 16100b Divide by 32101b Divide by 64110b Divide by 128111b Divide by 1
31 17 16 15 14 13 12 11 10 8 7 0
Reserved
M
TGM
RIR
Reserved
DS
31 17 16 15 13 12 11 10 8 7 0
Reserved
MReserved
DS
[AMD Public Use]Advanced Programmable Interrupt Controller (APIC) 63224593—Rev. 3.41—June 2023 AMD64 Technology
16.4.4  Thermal Sensor Interrupts
When a thermal event occurs, an APIC interrupt is generated under the control of bit 16 (Mask) in the 
APIC Thermal Sensor Local Vector Table Register. See Figure 16 -14. See the BIOS and Kernel 
Developer’s Guide (BKDG) or Processor Programming Reference Manual  applicable to your product 
for more information on thermal events. This interrupt may not be supported in all implementations.
Figure 16-14. Thermal Sensor Local Vector Table Register (APIC Offset 330h)
16.4.5  Extended Interrupts
The local interrupts are extended to include more LVT registers, to allow additional interrupt sources. 
The additional sources are model dependent and can include:
•Counter overflow from the Machine Check Miscellaneous Threshold Register. See “Machine-
Check Miscellaneous-Error Information Register 0 (MCi_MISC0)” on page 310 for details.
•ECC Error Count Threshold in memory system.
•Instruction Sampling.
The LVT register used for each interrupt source is specified by the control register associated with the source.
The Extended LVT Count field (bits 23:16) of the Extended APIC Feature Register specifies the 
number of extended LVT registers. Currently there are four additional LVT registers defined, Extended Interrupt [3:0], Local Vector Table Register, located at APIC offsets 500h–530h. (See Section 16.7.1, “Specific End of Interrupt Register,” on page 645 and Figure 16 -5 on page 626.)
16.4.6  APIC Error Interrupts
Errors that are detected while handling interrupts cause an APIC error interrupt to be generated under 
the control of bit 16 (Mask) in the APIC Error Local Vector Table Register. See Figure 16 -15 on 
page 632.
Figure 16 -15. APIC Error Local Vector Table Register (APIC Offset 370h)
The error information is recorded in the APIC Error Status Registers. The APIC Error Status Register is a read-write register. Writes to the register cause the internal error state to be recorded in the register, clearing the original error. See Figure 16 -16.31 17 16 15 13 12 11 10 8 7 0
Reserved
M Res
DS
Reserved
MReserved
DS
[AMD Public Use]633 Advanced Programmable Interrupt Controller (APIC)AMD64 Technology 24593—Rev. 3.41—June 2023
Figure 16-16. APIC Error Status Register (APIC Offset 280h)
The fields within the APIC Error Status register are as follows:
•Sent Accept Error (SAE) —Bit 2. The SAE bit when set to 1 indicates that a message sent by the
local APIC was not accepted by any other APIC.
•Receive Accept Error (RAE) —Bit 3. The RAE bit when set to 1 indicates that a message received
by the local APIC was not accepted by this or any other APIC
•Sent Illegal Vector (SIV) —Bit 5. The SIV bit when set to 1 indicates that the local APIC attempted
to send a message with an illegal vector value.
•Receive Illegal Vector (RIV) —Bit 6. The RIV bit when set to 1 indicates that the local APIC has
received a message with an illegal vector value.
•Illegal Register Address (IRA) —Bit 7. The IRA bit when set to 1 indicates that an access to an
unimplemented register location within the local APIC register range (APIC Base Address + 4
Kbytes) was attempted.
16.4.7  Spurious Interrupts
A timing issue exists between software and hardware that, though rare, results in spurious interrupts. 
In the event that the task priority is set to or above the level of the interrupt to be serviced while the interrupt is being acknowledged, the local APIC delivers a spurious interrupt to the CPU core instead, with the vector number specified by the Vector field of the Spurious Interrupt Register. The ISR is unaffected by the spurious interrupt, so the interrupt handler completes without sending an EOI back to the issuing local APIC.31 8 7 6 5 4 3 2 1 0
Reserved
IRA
RIV
SIV
Reserved
RAE
SAE
Reserved
31:8 Reserved MBZ
7 IRA Illegal Register Address R/W
6 RIV Received Illegal Vector R/W
5 SIV Sent Illegal Vector R/W
4 Reserved MBZ
3 RAE Receive Accept Error R/W
2 SAE Sent Accept Error R/W
1:0 Reserved MBZ
[AMD Public Use]Advanced Programmable Interrupt Controller (APIC) 63424593—Rev. 3.41—June 2023 AMD64 Technology
Figure 16-17. Spurious Interrupt Register (APIC Offset F0h)
The fields within the Spurious Interrupt register are as follows:
•Vector (VEC) —Bits 7:0. The VEC field contains the vector that is sent to the CPU core in the event
of a spurious interrupt.
•APIC Software Enable (ASE) —Bit 8. The ASE bit when set to 0 disables the local APIC
temporarily. When the local APIC is disabled, SMI, NMI, INIT, Startup, and Remote Read may be
accepted; pending interrupts in the ISR and IRR are held, but further fixed, lowest-priority, andExtInt interrupts are not accepted. All LVT entry mask bits are set and cannot be cleared. Settingthe ASE bit to 1, enables the local APIC.
•Focus CPU Core Checking (FCC) —Bit 9. The FCC bit when set to 1 disables focus CPU core
checking when the lowest-priority message type is used. A CPU core is the focus of an interrupt ifit is already servicing that interrupt (ISR=1) or if it has a pending request for that interrupt(IRR=1). Clearing the FCC bit to 0 disables focus CPU core checking.
16.5 Interprocessor Interrupts (IPI)
A local APIC can send interrupts to other local APICs (or itself) using software-initiated Interprocessor Interrupts (IPIs) using the Interrupt Command Register (ICR). Writing into the low order doubleword of the ICR causes the IPI to be sent.
The ICR can issue the following types of interrupt messages:
•basic interrupt message to another local APIC, including forwarding an interrupt that was received
but not serviced
•basic interrupt message to the same local APIC (self-interrupt)
•system management interrupt (SMI) 
•remote read message to another local APIC to read one of its APIC registers. 
•non-maskable interrupt (NMI) delivered to another local APIC31 10 9 8 7 0
Reserved
FCC
ASEVEC
31:10 Reserved MBZ
9 FCC Focus CPU Core Checking R/W
8 ASE APIC Software Enable R/W
[AMD Public Use]635 Advanced Programmable Interrupt Controller (APIC)AMD64 Technology 24593—Rev. 3.41—June 2023
•initialization message (INIT) to a target local APIC to be reset to their INIT state and await a
STARTUP IPI.
•startup message (SIPI) to the target local APICs, pointing to a start-up routine.
The format of the Interrupt Command Register is shown in Figure 16 -18.
Figure 16-18. Interrupt Command Register (APIC Offset 300h–310h)
The fields within the Interrupt Command register are as follows:
•Vector (VEC) —Bits 7:0. The function of this field varies with the Message Type field. The VEC
field contains the vector that is sent for this interrupt source for fixed and lowest priority message
types.
•Message Type (MT) —Bits 10:8. The MT field specifies the message type sent to the CPU core
- 000b = Fixed - The IPI delivers an interrupt to the target local APIC specified in Destination 
field.
- 001b = Lowest Priority - The IPI delivers an interrupt to the local APIC executing at the lowest 
priority of all local APICs that match the destination logical ID specified in the Destination 
field. See Section 16.6.1, “Receiving System and IPI Interrupts,” on page 638.
- 010b = SMI - The IPI delivers an SMI interrupt to target local APIC(s). The trigger mode is 
edge-triggered and the Vector field must = 00h.63 56 55 32
DES Reserved
31 20 19 18 17 16 15 14 13 12 11 10 8 7 0
Reserved DSH RRS
TGM
L
Reserved
DS
DMMT VEC
63:56 DES Destination R/W
55:20 Reserved MBZ
19:18 DSH Destination Shorthand R/W
17:16 RRS Remote Read Status RO
14 L Level R/W
11 DM Destination Mode R/W
[AMD Public Use]Advanced Programmable Interrupt Controller (APIC) 63624593—Rev. 3.41—June 2023 AMD64 Technology
- 011b = Remote read - The IPI delivers a read request to read an APIC register in the target local 
APIC specified in Destination field. The trigger mode is edge triggered and the Vector field

TGM
L
Reserved
DS
DMMT VEC
APIC specified in Destination field. The trigger mode is edge triggered and the Vector field 
specifies the APIC offset of the APIC register to be read. The Remote Status field provides the current status of the remote read access after it has been issued. Data is returned from the target local APIC and captured in the Remote Read Register of the issuing local APIC. See Figure 16 -19 on page 637.
- 100b = NMI - The IPI delivers a non-maskable interrupt to the target local APIC specified in 
the Destination field. The Vector field is ignored.
- 101b = INIT - The IPI delivers an INIT request to the target local APIC(s) specified in the 
Destination field, causing the CPU core to assume the INIT state. The trigger mode is edge-triggered, and the Vector field must =00h. In the INIT state, the target APIC is responsive only to the STARTUP IPI. All other interrupts (including SMI and NMI) are held pending until the STARTUP IPI has been accepted.
- 110b = STARTUP - The IPI delivers a start-up request (SIPI) to the target local APIC(s) 
specified in Destination field, causing the CPU core to start processing the platform firmware boot-strap routine whose address is specified by the Vector field. 
- 111b = External interrupt - The IPI delivers an external interrupt to the target local APIC 
specified in Destination field. The interrupt can be delivered even if the APIC is disabled.
•Destination Mode (DM) —Bit 11. The DM bit when set to 1 specifies a logical destination which
may be one or more local APICs with a common destination logical ID. When cleared to 0, the DMbit specifies a physical destination which indicates a single local APIC ID.
1 when the local APIC has sent the IPI and is waiting for it to be accepted by another local APIC(the ICR is not idle). Clearing the DS bit indicates that the target local APIC is idle. Code mayrepeatedly write ICRL without polling the DS bit; all requested IPIs will be delivered.
•Level (L)—Bit 14. The L bit when set to 1 indicates assert. Clearing the L bit to 0 indicatesdeassert.
•Trigger Mode (TGM)—Bit 15. Specifies how IPIs to the local APIC are triggered. The TGM bit isset to 1 when the interrupt is level-sensitive. It is cleared to 0 when the interrupt is edge-triggered. 
•Remote Read Status (RRS) —Bits 17:16. The RRS field indicates the current read status of a
Remote Read from another local APIC. The encoding for this field is as follows:
- 00b = Read was invalid- 01b = Delivery pending- 10b = Delivery done and access was valid. Data available in Remote Read Register.- 11b = Reserved
•Destination Shorthand (DSH) —Bits 19:18. The DSH field indicates whether a shorthand notation
is used, and provides a quick way to specify a destination for a message. It replaces the Destination
field, when the destination field is not required (DSH > 00b), allowing software to use a singlewrite to the low order ICR. The encoding are as follows:
[AMD Public Use]637 Advanced Programmable Interrupt Controller (APIC)AMD64 Technology 24593—Rev. 3.41—June 2023
- 00b = Destination - The Destination field is required to specify the destination.
- 01b = Self - The issuing APIC is the only destination.- 10b = All including self - The IPI is sent to all local APICs including itself (destination 
field=FFh).
- 11b = All excluding self - The IPI is sent to all local APICs except itself (destination 
field=FFh). Note that if the lowest priority is used, the message could end up being reflected back to this
local APIC. If DS=1xb, the destination mode is ignored and physical is automatically used.
•Destination (DES) —Bits 63:56. The DES field identifies the target local APIC(s) for the IPI and
contains the destination encoding used when the Destination Shorthand field=00b. The fieldindicates the target local APIC when the destination mode=0 (physical), and the destination logicalID (as indicated by LDR and DFR) when the destination mode=1 (logical).
Figure 16-19. Remote Read Register (APIC Offset C0h)
•Remote Read Data (RRD) —Bits 31:0. The RRD field contains the data resulting from a valid
completion of a remote read interprocessor interrupt.
Not all combinations of ICR fields are valid. Only the combinations indicated in Table 16 -4 are valid.
Table 16-4. Valid ICR Field Combinations31 0
RRD
31:0 RRD Remote Read Data RO
Message Type Trigger Mode Level Destination Shorthand
FixedEdge x x
Level Assert x
Lowest Priority, SMI, NMI, INITEdge x Destination or all excluding self.
Level Assert Destination or all excluding self
Startup x x Destination or all excluding self
Note: x indicates a don’t care.
[AMD Public Use]Advanced Programmable Interrupt Controller (APIC) 63824593—Rev. 3.41—June 2023 AMD64 Technology
16.6 Local APIC Handling of Interrupts
16.6.1  Receiving System and IPI Interrupts
Each local APIC verifies the destination ID, the destination mode and the message type of an APIC 
interrupt to determine if it is the target of the interrupt.
The destination mode is either physical or logical. In physical destination mode, the value of the 
interrupt message destination field is compared with the unique APIC ID value of each local APIC to select the target local APIC. If the destination field of the Interrupt Command Register is set to FFh, the interrupt is broadcasted and accepted by all local APICs. In physical destination mode, the lowest priority message type is not supported.
In logical destination mode, all local APICs use the Logical Destination Register and the Destination 
Format Register to determine if the interrupt is directed to them. The value of the interrupt message destination field is compared with the value in the Logical Destination Register (see Figure 16 -20) of 
all local APICs. 
The logical APIC ID must be unique. Since the comparison with the interrupt message destination 
field is on a bit-basis, there are only 8 unique logical IDs (01h, 02h, 04h, 08h, 10h, 20h, 40h, and 80h). For flat mode, the logical ID must be one of these values (for a total of eight local APICs supported). In cluster mode, the value of the logical ID is constrained to be xyh, where 0 ≤ x ≤ Eh and y = either 1,2,4, 
or 8, for a total of (15 × 4) possible unique logical IDs.
Figure 16-20. Logical Destination Register (APIC Offset D0h)
•Destination Logical ID (DLID) —Bits 31:24. The DLID field contains the logical APIC ID
assigned to this specific CPU core. The logical APIC ID must be unique.
Two interrupt models are defined for the logical destination mode, the flat model and the cluster model, under the control of the Destination Format Register. See Figure 16 -21.31 24 23 0
DLID Reserved
31:24 DLID Destination Logical ID R/W
[AMD Public Use]639 Advanced Programmable Interrupt Controller (APIC)AMD64 Technology 24593—Rev. 3.41—June 2023
Figure 16-21. Destination Format Register (APIC Offset E0h)
•Model (MOD) —Bits 31:28. The MOD field controls which format to use when accepting
interrupts in logical destination mode. The allowable values are 0h = cluster model and
Fh = flat model.
With the flat model, up to eight unique logical APIC ID values can be provided by software by setting a different bit in the LDR. When the logical ID of the destination is compared with the LDR, if any bit position is set in both fields, this local APIC is a valid destination. A broadcast to all local APICs occurs when the LDR is set to all ones.
In the cluster model, bits 31:28 of the logical ID of the destination are compared with bits 31:28 of the 
LDR. If there is a match, then bits 27:24 are tested for matching ones, similar to the flat model. If bits 31:28 match, and any of bits 27:24 are set in both fields, this local APIC is a valid destination. The cluster model allows for 15 unique clusters to be defined, with each cluster having four unique logical APIC values to be addressed. In cluster logical destination mode, lowest priority message type is not supported.
In both the flat model and the cluster model, if the destination field = FFh, the interrupt is accepted by 
all local APICs.
16.6.2  Lowest Priority Messages and Arbitration
In the case where the interrupt is valid for several local APICs in logical destination mode with a 
lowest priority message type, the interrupt is accepted by the local APIC with the lowest arbitration priority, as indicated by the Arbitration Priority field in the Arbitration Priority Register (APR). The 
value in the Arbitration Priority  field indicates the current priority for a pending interrupt or task, or an 
interrupt being serviced by the CPU core. See Figure 16 -22.31 28 27 0
MOD Reserved
31:28 MOD Model R/W
27:0 Reserved All ones RO
[AMD Public Use]Advanced Programmable Interrupt Controller (APIC) 64024593—Rev. 3.41—June 2023 AMD64 Technology
Figure 16-22. Arbitration Priority Register (APIC Offset 90h)
The fields within the Arbitration Priority register are as follows:

•Arbitration Priority Sub-class (APS)—Bits 3:0. The APS field indicates the current sub-priority to
handle arbitrated interrupts to be serviced by the CPU core.
•Arbitration Priority (AP)—Bits 7:4. The AP field indicates the current priority to handle arbitratedinterrupts to be serviced by the CPU core. The priority is used to arbitrate between CPU cores todetermine which core accepts a lowest-priority interrupt request. 
The value in the Arbitration Priority field is equal to the highest priority of the Task Priority field of the Task Priority Register (TPR), the highest bit set in the In-Service Register (ISR) vector, or the highest bit set in the Interrupt Request Register (IRR) vector. The value in the Arbitration Priority Sub-class field is equal to the Task Priority Sub-class if the APR is equal to the TPR, and zero otherwise.
If focus CPU core checking is enabled (Spurious Interrupt Register bit 9=0), the focus CPU core for an 
interrupt can always accept the interrupt. A CPU core is the focus of an interrupt if it is already servicing that interrupt (corresponding ISR bit is set) or if it already has a pending request for that interrupt (corresponding IRR bit is set). If there is no focus CPU core for an interrupt or if focus CPU core checking is disabled (Spurious Interrupt Register bit 9=1), all target local APICs identified as candidates for the interrupt arbitrate to determine which is executing with the lowest arbitration priority. If there is a tie for lowest priority, the local APIC with the highest APIC ID is selected. 
16.6.3  Accepting System and IPI Interrupts
If the local APIC accepting the interrupt determines that the message type for the interrupt request 
indicates SMI, NMI, INIT, STARTUP or ExtINT, it sends the interrupt directly to the CPU core for handling. If the message type is fixed or lowest priority, the accepting local APIC places the interrupt into an open slot in either the IRR or ISR registers. If there is no free slot, the interrupt is rejected and sent back to the sender with a retry request.
Three 256-bit acceptance registers support interrupts accepted by the local APIC. Bits 255:16 
correspond to interrupt vectors 255:16 with 255 being the highest priority; bits 15:0 are reserved. 
•Interrupt Request Register (IRR), which contains interrupt requests that have been accepted but
have not been sent to the CPU core for interrupt handling. When a system interrupt is accepted, theassociated bit corresponding to the interrupt vector is set in the IRR. When the CPU core requests a31 8 7 4 3 0
Reserved AP APS
7:4 AP Arbitration Priority RO
3:0 APS Arbitration Priority Sub-class RO
[AMD Public Use]641 Advanced Programmable Interrupt Controller (APIC)AMD64 Technology 24593—Rev. 3.41—June 2023
new interrupt, the local APIC selects the highest priority IRR interrupt and sends it to the CPU
core. The local APIC then sets the corresponding bit in the ISR and resets the associated IRR bit.See Figure 16 -23 on page 641.
•In-Service Register (ISR) contains the bit map of the interrupts that have been sent to the CPU coreand are still being serviced. When the CPU core writes to the EOI register indicating completion ofthe interrupt processing, the associated ISR bit is reset and a new interrupt is selected from the IRRregister. If a higher priority interrupt is accepted by the local APIC while the CPU core is servicinganother interrupt, the higher priority interrupt is sent directly to the CPU core (before the currentinterrupt finishes processing) and the associated IRR bit is set. The CPU core interrupts the currentinterrupt handler to service the higher priority interrupt. When the interrupt handler for the higherpriority interrupt completes, the associated IRR bit is reset and the interrupt handler returns tocomplete the previous interrupt handler routine. If a second interrupt with the same interrupt vectornumber is received by the local APIC while the ISR bit is set, the local APIC sets the IRR bit. Nomore than two interrupts can be pending for the same interrupt vector number. Subsequentinterrupt requests to the same interrupt vector number will be rejected. See Figure 16 -24 on
page 642.
•Trigger Mode Register (TMR) indicates the trigger mode of the interrupt and determines whetheran EOI message is sent to the I/O APIC for level-sensitive interrupts. When the interrupt isaccepted by the local APIC and the IRR bit is set, the associated TMR bit is set for level-sensitiveinterrupts or reset for edge-triggered interrupts. At the end of the interrupt handler routine, whenthe EOI is received at the local APIC, an EOI message is sent to the I/O APIC if the associatedTMR bit is set for a system interrupt. See Figure 16 -25 on page 642.
Figure 16-23. Interrupt Request Register (APIC Offset 200h–270h)
•Interrupt Request bits (IR) —Bits 255:16. The corresponding request bit is set when an interrupt is
accepted by the local APIC. The interrupt request registers provide a bit per interrupt to indicatethat the corresponding interrupt has been accepted by the local APIC. Interrupts are mapped asfollows:
255 16 15 0
IR Reserved
255:16 IR Interrupt Request bits RO
15:0 Reserved MBZ
Register Interrupt Number
IRR (APIC offset 200h) 31–16
IRR (APIC offset 210h) 63–32
IRR (APIC offset 220h) 95–64
IRR (APIC offset 230h) 127–96
[AMD Public Use]Advanced Programmable Interrupt Controller (APIC) 64224593—Rev. 3.41—June 2023 AMD64 Technology
Figure 16-24. In Service Register (APIC Offset 100h–170h)
•In Service bits (IS) —Bits 255:16. These bits are set when the corresponding interrupt is being
serviced by the CPU core. The in-service registers provide a bit per interrupt to indicate that the
corresponding interrupt is being serviced by the CPU core. Interrupts are mapped as follows:
Figure 16-25. Trigger Mode Register (APIC Offset 180h–1F0h)IRR (APIC offset 240h) 159–128
IRR (APIC offset 250h) 191–160
IRR (APIC offset 260h) 223–192
IRR (APIC offset 270h) 255–224
255 16 15 0
IS Reserved
255:16 IS In Service bits RO
ISR (APIC offset 100h) 31–16
ISR (APIC offset 110h) 63–32
ISR (APIC offset 120h) 95–64
ISR (APIC offset 130h) 127–96
ISR (APIC offset 140h) 159–128
ISR (APIC offset 150h) 191–160
ISR (APIC offset 160h) 223–192
ISR (APIC offset 170h) 255–224
255 16 15 0
TM Reserved
255:16 TM Trigger Mode bits RO
15:0 Reserved MBZRegister Interrupt Number
[AMD Public Use]643 Advanced Programmable Interrupt Controller (APIC)AMD64 Technology 24593—Rev. 3.41—June 2023
•Trigger Mode bits (TM) —Bits 255 :16. These bits provide a bit per interrupt to indicate the
assertion mode of each interrupt. Interrupts are mapped as follows:
16.6.4  Selecting and Handling Interrupts
Interrupts are selected by the local APIC for delivery to the CPU core interrupt handler on a priority 
determined by the interrupt vector number. Of the 15 priority levels, 15 is the highest and 1 is the lowest. The priority level for an interrupt is equal to the interrupt vector number divided by 16, rounded down to the nearest integer, with vectors 0Fh–00h reserved. Therefore, interrupt vectors 79h and 70h have the same priority level. The high-order hex digit indicates the priority level while the low-order hex digit indicates the priority within the same priority level.
Two registers are used to determine the priority threshold for selecting interrupts to be delivered to the 
CPU core, the Task Priority Register (TPR) and the Processor Priority Register (PPR). Software uses the TPR to set a priority threshold for interrupts to the CPU core, allowing the OS to block specific interrupts. See Figure 16 -26 on page 643 for more details on the TPR.
The value in the Task Priority  field is set by software to set a threshold priority at which the processor 
is to be interrupted. The value varies from 0 (all interrupts are allowed) to 15 (all interrupts with fixed delivery mode are inhibited). See Figure 16 -26.
Figure 16 -26. Task Priority Register (APIC Offset 80h)
The fields within the Task Priority register are as follows:Register Interrupt Number
TMR (APIC offset 180h) 31–16
TMR (APIC offset 190h) 63–32
TMR (APIC offset 1A0h) 95–64
TMR (APIC offset 1B0h) 127–96
TMR (APIC offset 1C0h) 159–128
TMR (APIC offset 1D0h) 191–160
TMR (APIC offset 1E0h) 223–192
TMR (APIC offset 1F0h) 255–224
31 8 7 4 3 0
Reserved TP TPS
7:4 TP Task Priority R/W
3:0 TPS Task Priority Sub-class R/W
[AMD Public Use]Advanced Programmable Interrupt Controller (APIC) 64424593—Rev. 3.41—June 2023 AMD64 Technology
•Task Priority Sub-class (TPS) —Bits 3 :0. The TPS field indicates the current sub-priority to be used
when arbitrating lowest-priority messages. This field is written with zero when TPR is written
using the architectural CR8 register.

31 8 7 4 3 0
•Task Priority (TP) —Bits 7 :4. The TP field indicates the current priority to be used when a core is
deciding when to handle interrupts. A value of zero allows all interrupts; a value of Fh disables allinterrupts. TP is also used to arbitrate between CPU cores to determine which core accepts alowest-priority interrupt request. This field can also be written using the architectural CR8 register.
The PPR is set by the CPU core and represents the current priority level at which the CPU core is executing. The PPR determines whether a pending interrupt in the local APIC can be selected for interrupt handling in the CPU core. The value set by hardware is either the interrupt priority level of the highest priority ISR bit set or the value in the TPR, whichever is higher. The PPR is equal to the TPR when the CPU core is not servicing a higher priority interrupt. See Figure 16 -27 on page 644.
Figure 16-27. Processor Priority Register (APIC Offset A0h)
The fields within the Processor Priority register are as follows:
•Processor Priority Sub-class (PPS) —Bits 3:0. The PPS field is set to the Task Priority sub-class
field of the Task Priority Register (TPR) if the PP field is equal to the Task Priority field of the
TPR.
•Processor Priority (PP) —Bits 7:4. The PP field indicates the CPU core’s current priority for
servicing a task or interrupt, and is used to determine if any pending interrupts should be serviced.It is the higher value of either the interrupt priority level of the highest priority ISR bit set or thevalue in the TPR.
Pending interrupts must have a higher priority level than the value in the PPR to be selected by the local APIC for interrupt handling in the core; otherwise, they remain pending in the IRR until the PPR is lowered below the pending interrupt priority level. No pending interrupts are selected by the local APIC when the TPR=15. 
The local APIC selects the highest priority pending interrupt (highest priority IRR) when the CPU core 
is ready, and sends the interrupt (with the IRR vector) to the CPU core. The local APIC resets the highest priority IRR bit and sets the associated ISR bit.31 8 7 4 3 0
Reserved PP PPS
7:4 PP Processor Priority RO
3:0 PPS Processor Priority Sub-class RO
[AMD Public Use]645 Advanced Programmable Interrupt Controller (APIC)AMD64 Technology 24593—Rev. 3.41—June 2023
As part of the completion of the interrupt handling routine, software writes a value of zero to the End-
of-Interrupt Register (EOI) in the local APIC, which causes the local APIC to reset the associated ISR bit. The EOI register is a write-only register.
If a higher priority interrupt is accepted by the local APIC while the CPU core is servicing another 
interrupt, the higher priority interrupt is sent directly to the CPU core (before the current interrupt finishes processing) and the associated ISR bit is set. The CPU core interrupts the current interrupt handler to service the higher priority interrupt. When the interrupt handler for the higher priority interrupt completes, the associated ISR bit is reset and the interrupt handler returns to complete the previous interrupt handler routine. 
Figure 16-28. End of Interrupt (APIC Offset B0h)
•End of Interrupt (EOI) —Bits 31:0. Write-only operation signals end of interrupt processing to
source of interrupt.
16.7 SVM Support for Interrupts and the Local APIC
The SVM hypervisor uses the Extended APIC Feature Register, Extended APIC Control Register, Specific End of Interrupt Register (SEOI), and Interrupt Enable Register (IER) to control virtualized interrupts. When guests have direct access to devices, interrupts arriving at the local APIC can usually be dismissed only by the guest that owns the device causing the interrupt. To prevent one guest from blocking other guests’ interrupts (by never processing their own), the VMM can mask pending interrupts in the local APIC, so they do not participate in the prioritization of other interrupts. 
16.7.1  Specific End of Interrupt Register
Software issues a specific EOI (SEOI) by writing the vector number of the interrupt to the SEOI 
register in the local APIC. The SEOI register is located at offset 420h in the APIC space. The SEOI register format is shown in Figure 16 -29.31 0
EOI
31:0 EOI End of Interrupt WO
31 8 7 0
Reserved VECTOR
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Figure 16-29. Specific End of Interrupt (APIC Offset 420h)
16.7.2  Interrupt Enable Register
The IER is made available to software by means of eight 32-bit registers in the local APIC; bit i of the 
256-bit IER is located at bit position ( i mod 32) in the local APIC register IER[i / 32]. The eight IER 
registers are located at offsets 480h, 490h, ...,4F0h in APIC space. The IER format is shown in Figure 
16-30.
Figure 16-30. Interrupt Enable Register (APIC Offset 480h–4F0h)
Interrupt Enable (IE) —Bits 255 :16. Interrupts are mapped as follows:
The IER and SEOI registers are located in the APIC Extended Space area. The presence of the APIC Extended Space area is indicated by bit 31 of the APIC Version Register (at offset 30h in APIC space). 
The presence of the IER and SEOI functionality is identified by bits 0 and 1, respectively, of the APIC 
Extended Feature Register (located at offset 400h in APIC space). IER and SEOI are enabled by setting bits 0 and 1, respectively, of the APIC Extended Control Register (located at offset 410h).Bits Mnemonic Description Access type
7:0 VECTOR Vector Number of Interrupt R/W
255 16 15 0
IE Reserved
255:16 IE Interrupt Enable R/W
IER (APIC offset 480h) 31–16
IER (APIC offset 490h) 63–32
IER (APIC offset 4A0h) 95–64
IER (APIC offset 4B0h) 127–96
IER (APIC offset 4C0h) 159–128
IER (APIC offset 4D0h) 191–160
IER (APIC offset 4E0h) 223–192
IER (APIC offset 4F0h) 255–224
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Only vectors that are enabled in IER participate in APIC's computation of the highest-priority pending 
interrupt. The reset value of IER is all ones.
16.8 x2APIC Mode
x2APIC mode is an extension to the local APIC architecture designed to support larger CPU topologies and to enhance delivery of interrupts. When enabled, x2APIC mode adds the following features:
•All APIC and x2APIC registers are accessed via an MSR-based interface.
•The Local APIC ID and Logical APIC ID registers are expanded to 32 bits.
•Logical and physical destinations are extended to 32 bits.
•A new self-IPI register simplifies sending IPIs to self.
In general, x2APIC mode maintains backwards compatibility with the key elements of the local APIC 
functionality previously described in Section 16. However, the following local APIC functionality is changed in x2APIC mode:
•The Destination Format Register (DFR) is no longer needed and is not supported.
•The two 32-bit Interrupt Command Registers (ICRs) are merged into a single 64-bit ICR.
•Local APIC Base (MSR 01Bh) bit 10, previously reserved, is used to enable x2APIC mode.
16.8.1  x2APIC Terminology
Although x2APIC is an operational mode of the local APIC, the following sections use the term 
‘x2APIC’ as a qualifier to more conveniently identify a given aspect of the local APIC when that mode is enabled. For example, the term ‘x2APIC programming interface’ may be used instead of ‘the programming interface when the local APIC is in x2APIC mode’.
16.9 Detecting and Enabling x2APIC Mode
System software can detect the presence of the x2APIC feature by executing the CPUID instruction. Support for x2APIC mode is indicated by CPUID Fn0000_0001_ECX[x2APIC] (bit 21) = 1.
If the feature is present, the local APIC is placed into x2APIC mode by setting bit 10 in the Local 
APIC Base register (MSR 01Bh). Before entering x2APIC mode, the local APIC must first be enabled (AE=1, EXTD=0). System software can then place the local APIC into x2APIC mode by executing a WRMSR with both AE=1 and EXTD=1. The format of the Local APIC Base register for x2APIC-capable processors is shown in Figure 16 -31.
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Figure 16-31. APIC Base Address Register (MSR 01Bh) support for x2APIC
Not all combinations of the local APIC mode bits are valid. See Table 16 -5. Attempting to set the 
combination of AE=0 and EXTD=1 is invalid and causes the WRMSR instruction to generate a 
#GP(0) exception.
Table 16-5. Local APIC Operating Modes
Similarly, not all transitions between local APIC states are valid. The valid state transitions are 
illustrated in Figure 16 -2. Once the local APIC has been placed into x2APIC mode, the only valid

illustrated in Figure 16 -2. Once the local APIC has been placed into x2APIC mode, the only valid 
transition (other than reset) is to “APIC Disabled” mode by simultaneously clearing AE and EXTD to zero. Executing a WRMSR instruction to attempt a transition other than those specified in Figure 16-32 results in a #GP(0) exception.63 52 51 32
AE
EXTD
Reserved
11 AE APIC Enable (xAPIC mode) R/W
10 EXTD X2APIC Mode Enable R/W
[7:0] Reserved MBZ
AE (bit 11) EXTD (bit 10) Local APIC Mode
0 0 local APIC disabled 
0 1 Invalid
1 0 local APIC enabled in xAPIC mode
1 1 local APIC enabled in x2APIC mode
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Figure 16 -32. Valid APIC State Transitions
16.9.1  Enabling x2APIC Mode
Starting from APIC Disabled mode, enabling x2APIC mode is a two-step process. First, a transition is 
made to APIC_Enabled mode by setting APIC_Base bit 11 (AE) to 1 with bit 10 (EXTD) left as zero. Next, the transition to x2APIC mode is made by setting both AE and EXTD to 1 simultaneously.
Most APIC registers previously written by software while in APIC_Enabled mode are not affected by 
the transition to x2APIC mode. The exceptions are:
•The Logical Destination Register (LDR) is not preserved.
•The upper half of the Interrupt Command Register (ICR_High) is not preserved.
•A value previously written by software to the 8-bit APIC_ID register (MMIO offset 30h) is
converted by hardware into the appropriate format and reflected into the 32-bit x2APIC_IDregister (MSR 802h).
Leaving x2APIC mode.  Once in x2APIC mode, the only valid mode transition (other than a reset) is 
to APIC_Disabled mode by using WRMSR to clear APIC_Base bit 11 (AE) bit 10 (EXTD) to 0 at the same time.
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16.10 x2APIC Initialization 
A RESET clears the APIC Base Address Register AE bit and EXTD bit, disabling the local APIC. All 
local APIC registers are initialized to their reset values as described in section 16.3.2 “APIC Registers”.
An INIT does not modify the APIC Base Address Register AE and EXTD bits, thus the local APIC 
mode is not changed. All other APIC registers are initialized to their values as described in “Reset in x2APIC mode” above.
16.11 Accessing x2APIC Register
The x2APIC system programming interface consists of the Model Specific Registers listed in Table 16 -6 below. All APIC registers except the APIC Base Address Register are mapped into the 
architecturally dedicated MSR range 800h to 8FFh, and accessed using WRMSR and RDMSR instructions.
The RDMSR/WRMSR instructions read and write the MSR specified in the ECX register using the 
EDX:EAX register pair as the destination and source operand. Bits 31:0 of the APIC register are mapped into EAX[31:0]. For 64-bit x2APIC registers, the high-order bits (bits 63:32) are mapped to EDX[31:0]. A #GP(0) exception is generated if an unimplemented APIC register is specified in ECX. When not in x2APIC mode, attempts to access the APIC register set using the MSR interface results in the WRMSR or RDMSR instruction generating a #GP(0) exception. See APM volume 3 for more information on the WRMSR and RDMSR instructions.
In x2APIC mode, the legacy MMIO access to the APIC register set is disabled. Attempts to use the 
legacy MMIO access mechanism may result in an unintended memory access or a memory-related exception such as #GP or #PF.
16.11.1  x2APIC Register Address Space
The x2APIC registers are mapped into the MSR address range 800h through 8FFh. This address range 
is reserved for accessing the APIC register set in x2APIC mode.
The legacy APIC registers are mapped to this MSR address space using on the following formula:x2APIC MSR address = 800h + ((APIC MMIO offset) >> 4)The following registers are exceptions to the above formula:
•The two 32-bit Interrupt Command Registers in APIC mode (MMIO offsets 300h and 310h) are
merged into a single 64-bit x2APIC register at MSR address 830h.
•The x2APIC Self_IPI register is added at MSR address 83Fh
•The Destination Format Register (DFR) at MMIO offset E0h and the Remote Read Register(RRR) at MMIO offset C0h are not supported in x2APIC mode. Accordingly, MSR addresses80Eh and 80Ch are not used and are reserved.
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The system programming interface of the local APIC in x2APIC mode is made up of the MSRs listed 
in Table 16 -6 below.
Table 16-6. x2APIC Register
MSR Address 
(x2APIC mode)MMIO Offset 
(xAPIC mode)Register Name Read/
WriteNotes 
802h 20h x2APIC ID Register [31:0] RO Expanded to 32-bits in x2APIC mode
803h 30h APIC Version Register RO
808h 80h Task Priority Register (TPR) R/W  
809h 90h Arbitration Priority Register (APR) RO  
80Ah A0h Processor Priority Register (PPR) RO  
80Bh B0h End of Interrupt Register (EOI) WO #GP(0) if non-zero value is written
- C0h Remote Read Register - Eliminated in x2APIC mode
80Dh D0h Logical Destination Register (LDR) RO Expanded to 32-bits in x2APIC mode
- E0h Destination Format Register - Eliminated in x2APIC mode
80Fh F0h Spurious Interrupt Vector Register R/W 
800-817h 100-170h In-Service Register (ISR) RO 
818-81Fh 180-1F0h Trigger Mode Register (TMR) RO  
820-827h 200-270h Interrupt Request Register (IRR) RO  
828h 280h Error Status Register (ESR) R/W #GP(0) if non-zero value is written
830h 300h Interrupt Command Register (bits 
63:0)R/W  
832h 320h Timer Local Vector Table Entry R/W 
833h 330h Thermal Local Vector Table Entry R/W 
834h 340h Perf Counter Local Vector Table Entry R/W
835h 350h Local Interrupt 0 Vector Table Entry R/W
836h 360h Local Interrupt 1 Vector Table Entry R/W
837h 370h Error Vector Table Entry R/W
838h 380h Timer Initial Count Register R/W
839h 390h Timer Current Count Register RO
83Eh 3E0h Timer Divide Configuration Register R/W
83Fh —Self IPI Register WO See Figure 16 -6
840h 400h Extended APIC Feature Register RO
841h 410h  Extended APIC Control Register R/W
842h 420hSpecific End of Interrupt Register 
(SEOI)R/W
848-84Fh 480-4F0h Interrupt Enable Registers (IER) R/W
850-853h 500-530h Extended Interrupt [3:0] Local Vector 
Table RegistersR/W
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MSR addresses in the range 800h through 8FFh that are not listed in Table 16-2 are unimplemented 
and reserved. A #GP(0) exception is generated if a WRMSR or an RDMSR instruction attempts to access an unimplemented MSR in the x2APIC address range.
16.11.2  WRMSR / RDMSR serialization for x2APIC Register
The WRMSR instruction is used to write the APIC register set in x2APIC mode. Normally WRMSR is 
a serializing instruction, however when accessing x2APIC registers, the serializing aspect of WRMSR is relaxed to allow for more efficient access to those registers. Consequently, a WRMSR write to an x2APIC register may complete before older store operations are complete and have become globally visible. When strong ordering of an x2APIC write access is required with respect to preceding memory operations, software can insert a serializing instruction (such as MFENCE) before the WRMSR instruction.
The RDMSR instruction is not a serializing instruction and remains non-serializing when reading 
x2APIC MSRs. However, WRMSR and RDMSR instructions targeting the x2APIC MSRs are always executed in program order with respect to each other.
16.11.3  Reserved Bit Checking in x2APIC Mode
When writing x2APIC MSRs, the WRMSR instruction checks for reserved bits. Attempting to write a 
‘1’ to a reserved bit causes a #GP(0) exception. For x2APIC MSRs, WRMSR reserved bit checks are summarized as follows:
Legacy APIC registers.  Reserved bit checks for existing APIC registers are the same as described for 
each register in non-x2APIC mode. For details, see the APIC register descriptions in sections 16.3 
through section 16.6 above. Except for the Interrupt Command Register, attempting to write a ‘1’ into bits 63:32 of the legacy APIC registers causes a #GP(0) exception.
Interrupt Command Register (ICR). See the description of the 64-bit ICR register in section 16.13.
Error Status Register (ESR). A WRMSR of a non-zero value causes a #GP(0) exception.
SELF IPI register. See the description of the 32-bit SELF IPI register in Section 16.15 on page 655.The RDMSR instruction returns a zero for any reserved bit.
16.12 x2APIC_ID
Unique local APIC IDs are assigned to each logical processor in the system. In x2APIC mode, the 
APIC ID is expanded to 32 bits and is referred to as the ‘x2APIC_ID’. It is assigned by hardware at reset time based on the processor topology of the system. The x2APIC_ID is a concatenation of several fields such as socket ID, core ID and thread ID.

Because the number of sockets, cores and threads may differ for each SOC, the format of x2APIC ID is 
model-dependent. Some fields may not be present, depending on the processor model and the 
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processor topology. The presence, size and position of each field is discoverable using the CPUID 
instruction (see “Cache and Processor Topology” on page 211).
Figure 16-33. x2APIC_ID Register (MSR 802h)
System software can read x2APIC_ID using either of the following mechanisms:
RDMSR.  An RDMSR of MSR 0802h returns the x2APIC_ID in EAX[31:0]. The x2APIC_ID is a 
read-only register. Attempting to write MSR 802h or attempting to read this MSR when not in x2APIC 
mode causes a #GP(0) exception. See 16.11 “Accessing x2APIC Registers”.
CPUID.  The x2APIC ID is reported by CPUID functions Fn0000_000B (Extended Topology 
Enumeration) and CPUID Fn8000_001E (Extended APIC ID) as follows:
•Fn0000_000B_EDX[31:0]_x0 reports the full 32-bit ID, independent of APIC mode (i.e. even
with APIC disabled)
•Fn8000_001E_EAX[31:0] conditionally reports APIC ID. There are 3 cases:
- 32-bit x2APIC_ID, in x2APIC mode.- 8-bit APIC ID (upper 24 bits are 0), in xAPIC mode.- 0, if the APIC is disabled.
The above CPUID functions also report the presence, width and location of the sub-fields comprising 
the x2APIC ID. See APM V olume 3 Appendix E, “Obtaining Processor Information Via the CPUID Instruction” for detailed information.
16.13 x2APIC Interrupt Command Register (ICR) Operations
In legacy APIC mode, two 32-bit registers (ICR Low and ICR High) are used by system software to send Inter-Processor Interrupts (IPIs) to other local APICs. The x2APIC architecture combines these two registers into a single 64-bit Interrupt Command Register located at MSR address 830h. Thus in x2APIC mode sending an IPI requires only a single WRMSR to the ICR as opposed to two MMIO accesses in xAPIC mode.
The upper half of the x2APIC ICR (bits 63:32) contains the Destination ID (DEST) field, which is 
expanded to 32 bits in x2APIC mode. A DEST value of FFFF_FFFFh is used to broadcast IPIs to all local APICs.31 0
x2APIC_ID
31:0 x2APIC_ID x2APIC ID RO
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The lower half of the x2APIC ICR (bits 31:0) is identical to the APIC Interrupt Command Register 
Low[31:0] (see Fig 16-18 on page 582), with the following exceptions:
•The Remote Read Status field (bits 17:16) is eliminated and must be zero.
•Message Type field (bits 10:8). Encodings 1, 3 and 7 are eliminated and the encodings are
reserved.
•The Delivery Status field (bit 12) is eliminated and must be zero.
The format of the x2APIC ICR register is shown in Figure 16 -34.
Figure 16-34. Interrupt Command Register (MSR 830h)
16.14 Logical Destination Register
When an IPI is sent using logical destination mode, all local APICs in the system use the Logical Destination Register to determine if the interrupt message is directed to them (see 16.6.1 Receiving System and IPI Interrupts). In x2APIC mode, the Logical Destination Register (LDR) is expanded to 32 bits and contains the ‘logical x2APIC_ID’. System hardware initializes LDR with the 32-bit logical x2APIC_ID whenever x2APIC mode is enabled. The LDR is a read-only register located at MSR address 080Dh. The format of the Logical Destination Registers is shown in Figure 16 -35.63 0
DEST
Reserved
DSH
Reserved
TGM
L
Reserved
DMMT VEC
63:32 DEST Destination R/W
55:20 Reserved  MBZ
17:16 Reserved MBZ
15 TMG Trigger Mode R/W
13:12 Reserved MBZ
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Figure 16-35. Logical Destination (MSR 80Dh)
The logical x2APIC_ID consists of two 16-bit sub-fields: cluster_ID and logical_ID.
•LDR[31:16] cluster_ id. Identifies the cluster of which this processor is a member.
•LDR[15:0] logical_id. A bit vector uniquely identifying this processor within the cluster.
In logical destination mode, a given logical processor is addressed by its unique cluster ID and 
logical_ID combination. The use of a bit vector for logical_ID allows an interrupt message to be routed to multiple processors within the addressed cluster.
The partitioning of logical x2APIC_ID provides for a possible 65,535 (216-1) clusters, with each 
cluster having up to 16 logical processors. The legacy “flat logical” addressing is not supported in x2APIC mode.
Upon receiving an interrupt message in logical destination format, each x2APIC compares bits 31:16 
of the message destination with LDR[31:16] (cluster_id). If there is a match, then bits 15:0 of the destination and LDR[15:0] are tested for matching ones. If bits[31:16] (cluster_id) match and any bit in 15:0 (logical_id) match, this x2APIC is a valid destination.
A DEST value of FFFF_FFFFh in the ICR is used to broadcast IPIs to all local APICs.The two sub-fields comprising logical x2APIC_ID are derived from the value of local x2APIC_ID. 
The 16-bit logical_ID sub-field is initialized by setting a single bit, ‘n’, where n= the 4 least significant bits of local x2APIC_ID. The 16-bit cluster_id is derived from the remaining bits of the x2APIC_ID. Specifically, logical_id[15:0] = 1 << x2APIC_ID[3:0] and cluster_id[15:0] = x2APIC_ID[19:4].
16.15 Self_IPI Register
The Self_IPI register (MSR 83Fh) provides a performance-optimized interface for system software to send interrupt messages to the local APIC. This register is write-only and attempts to read it cause a #GP(0) exception. The format of the Self_IPI registers is shown in Figure 16 -36.31 0
Logical x2APIC_ID
31:0 x2Logical_ID Logical x2APICID Identifier RO
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Figure 16-36. Self_IPI Register (MSR 83Fh)
The Self_IPI register contains a single field: an interrupt vector. Writing to this register causes a to-self 
IPI to be generated, equivalent to a to-self IPI generated by writing the Interrupt Command Register (ICR, MSR 830h) with the following settings:
•Destination shorthand = self
•Trigger Mode = edge-triggered
•Message Type = fixed
•Vector = interrupt vector as specified in the Self_IPI register
The x2APIC’s response to a self-IPI sent via the Self_IPI register is architecturally identical to one 
sent via the ICR. In particular, the operation of the Interrupt Response Register (IRR), In-Service Register (ISR) and Trigger Mode Register (TMR) is the same. See “Accepting System and IPI Interrupts” on page 640 for IRR, ISR and TMR details.
The Interrupt Request Register (IRR) contains interrupt requests that have been accepted by the 
processor core. Completion of the WRMSR to the Self_IPI register ensures that the resulting IPI has been entered into the IRR, and that the associated TMR bit is cleared (as expected for edge-triggered interrupts).31 8 7 0
Reserved VEC
7:0 VEC Interrupt Vector WO
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17 Hardware Performance Monitoring and 
Control
The AMD64 architecture provides several mechanisms by which software can monitor and control 
processor performance to optimize power use. The following lists the facilities that are described in the sections that follow:
•The P-state control interface allows dynamic control of performance states. See Section 17.1 
which follows immediately below.
•Core performance boost (CPB) dynamically increases core clock rate beyond that defined for the P0 power state to achieve higher performance while maintaining power consumption below a preset level. See Section 17.2 on page 659.
•The effective frequency interface provides a measure of the actual core clock rate over a specified period of time. See Section 17.3 on page 660.
•The processor power reporting interface allows system software to measure average processor core power over a given time period. See Section 17.5 on page 662.
•Collaborative Processor Performance Control (CPPC) provides a mechanism for improving performance and power efficiency in collaboration with Operating System Power Management software. See Section 17.6 on page 664.
17.1 P-State Control

P-states are operational performance states (states in which the processor is executing instructions, that is, running software) characterized by a unique frequency of operation for a CPU core. The P-state control interface supports dynamic P-state changes in up to 16 P-states, called P-states 0 through 15 or P0 though P15. P0 is the highest power, highest performance P-state; each ascending P-state number represents a lower-power, lower-performance state.
Core P-states are controlled by software. Each CPU core contains one set of P-state control registers. 
Software controls the P-states of each CPU core independently; however, hardware may include interdependencies that affect the P-state achieved by each core. 
Hardware provides the highest P-state value in the PstateMaxVal field of the P-State Current Limit 
Register. P-states may be limited to a lower performance value under certain conditions. The current P-state limit is dynamic and is specified in the CurPstateLimit field of the P-State Current Limit Register.
Software requests a core P-state change by writing a 4-bit index corresponding to the desired core P-
state number to the P-State Control Register of the appropriate core. For example, to request the P3 state for core 0, software writes 3h to the core 0’s PstateCmd field in MSR C001_0062h. If the P-state value is greater than the value in PstateMaxVal, the value written is clipped to that value. 
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As the current P-state limit changes, the P-state for the CPU core is either set to the software-requested 
P-state value or the new current P-state limit, whichever is the higher P-state value.
The current P-state value can be read using the P-State Status Register. The P-State Current Limit 
Register and the P-State Status Register are read-only registers. Writes to these registers cause a #GP exception. Support for hardware P-state control is indicated by CPUID Fn8000_0007_EDX[HwPstate] = 1. Figure 17 -1 below shows the format of the P-State 
Current Limit register.
Figure 17-1. P-State Current Limit Register (MSR C001_0061h)
The fields within the P-State Current Limit register are:
•Current P-State Limit (CurPstateLimit) —Bits 3:0. Provides the current P-state limit, which is the 
lowest P-state value (highest-performance state) that is currently supported by the hardware. This 
is a dynamic value controlled by hardware. Reset value is implementation specific.
•P-State Maximum Value (PstateMaxVal)—Bits 7:4. Specifies the highest P-state value (lowest performance state) supported by the hardware. Attempts to change the current P-state number to a higher value by writes to the P-State Control Register are clipped to the value of this field. Reset value is implementation specific. 
Figure 17-2. P-State Control Register (MSR C001_0062h)
P-State Change Command (PstateCmd)—Bits 3:0. Writes to this field cause the CPU core to change to the indicated P-state number, which may be clipped by the PstateMaxVal field of the P-State Cur -
rent Limit Register. Reset value is implementation specific.63 8 7 4 3 0
Reserved PstateMaxVal CurPstateLimit
63:8 Reserved MBZ
7:4 PstateMaxVal P-state maximum value RO
3:0 CurPstateLimit Current P-state limit RO
63 4 3 0
Reserved PstateCmd
63:4 Reserved MBZ
3:0 PstateCmd P-state change command R/W
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Figure 17-3. P-State Status Register (MSR C001_0063h)
Current P-State (CurPstate) —Bits 3:0. This field provides the current P-state of the CPU core regard -
less of the source of the P-state change, including writes to the P-State Control Register: 0 = P-state 0, 
1 = P-state 1, etc. The value of this field is updated when the frequency transitions to a new value 
associated with the P-state. Reset value is implementation specific.
17.2 Core Performance Boost
Core performance boost (CPB) dynamically monitors processor activity to create an estimate of power consumption. If the estimated processor consumption is below an internally defined power limit and software has requested P0 on a given core, hardware may transition the core to a frequency and voltage beyond those defined for P0. If the estimated power consumption exceeds the defined power limit, some or all cores are limited to the frequency and voltage defined by P0. CPB ensures that average power consumption over a thermally significant time period remains at or below the defined power limit.
CPB can be disabled using the CPBDis field of the Hardware Configuration Register (HWCR MSR) 
on the appropriate core. When CPB is disabled, hardware limits the frequency and voltage of the core to those defined by P0.
Support for core performance boost is indicated by CPUID Fn8000_0007_EDX[CPB] = 1. See 
Section 3.3, “Processor Feature Identification,” on page 71 for more information on using the CPUID instruction.63 4 3 0
Reserved CurPstate
3:0 CurPstate Current P-state RO
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Figure 17-4. Core Performance Boost (MSR C001_0015h)
Core Performance Boost Disable (CpbDis) —Bit 25. Specifies whether core performance boost is 
enabled or disabled. 0 = Enabled. 1 = Disabled.
17.3 Determining Processor Effective Frequency
The Max Performance Frequency Clock Count (MPERF) and the Actual Performance Frequency 
Clock Count (APERF) registers constitute the effective frequency interface. This interface provides a means for software to calculate an average, or effective, frequency of a core over a known window of time. This provides software a measure of actual performance rather than forcing software to assume that the current frequency of the core is the frequency of the last P-state requested. 
To calculate an effective clock frequency of a given processor core, on that processor do the following:
1. Read both MPERF and APERF and save their initial values.
- MPERF_INIT = MPERF and APERF_INIT = APERF
2. Wait an appropriate amount of time.3. Read both MPERF and APERF again.4. Effective frequency = {(APERF − APERF_INIT) / (MPERF − MPERF_INIT)} * P0 frequency.
The amount of time that elapses between steps 1 and 3 is determined by software. This allows software 
to define the time window over which the processor frequency is averaged. Software should disable interrupts or any other events that may occur between the read of MPERF and the read of APERF in step 1 and again when the two MSRs are read in step 3. Step 4 provides the equation for the calculation of the effective frequency value. Software determines the P0 frequency using ACPI defined data structures.
The effective frequency interface only counts clock cycles while the core is in the ACPI defined C0 
state.
Only the ratio between MPERF and APERF is architecturally defined. Software should not assume 
any specific definition of the MPERF or APERF registers. If an overflow of either the MPERF or 63 25 0
Reserved
CPBDisReserved
63:26 Reserved MBZ
25 CPBDis Core Performance Boost Disable R/W
24:0 Reserved MBZ
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APERF register occurs between the read of MPERF in step 1 and the read of APERF in step 3, the 
effective frequency calculated in step 4 is invalid.
Hardware support for the effective frequency interface is indicated by 
CPUID Fn0000_0006_ECX[EffFreq]. See Section 3.3, “Processor Feature Identification,” on page 71 
for more information on using the CPUID instruction.
17.3.1  Actual Performance Frequency Clock Count (APERF)
Specifies the numerator of the effective frequency ratio.
Figure 17-5. Actual Performance Frequency Count (MSR0000_00E8h)
17.3.2  Maximum Performance Frequency Clock Count (MPERF)
Specifies the denominator of the effective frequency ratio. The value read is scaled by the TSCRatio value (MSR C000_0104h) for guest reads, but the underlying counters are not affected. Reads in host mode or writes to MPERF are not affected.
Figure 17-6. Max Performance Frequency Count (MSR0000_00E7h)63 0
APERF
63:0 APERF Actual Performance Frequency Clock Count R/W
63 0
MPERF
63:0 MPERF Max Performance Frequency Clock Count R/W
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17.3.3  APERF Read-only (AperfReadOnly)
Figure 17 -7. APREF Read Only (MSR C000_00E8h)
17.3.4  MPERF Read-only (MperfReadOnly)
Read-only version of MPERF. The value read is scaled by the TSCRatio value (MSR C000_0104h) 
for guest reads.
Figure 17 -8. MPERF Read Only (MSR C000_00E7h)
17.4 Processor Feedback Interface

APERF
63 0
MPERF
The Processor Feedback Interface is deprecated. Some processor products may support this feature. To determine support on a given processor, software can test the feature bit CPUID Fn8000_0007_EDX[ProcFeedbackInterface]. For more information, consult the BIOS and Kernel 
Developer’s Guide (BKDG) or Processor Programming Reference Manual  applicable to your 
product. 
17.5 Processor Core Power Reporting
The processor power reporting interface allows system software to estimate the average power consumed by a processor core over a software-determined time period. Computing the average power involves reading a “core power accumulator” register at the beginning and end of the measurement interval, taking the difference and then dividing by the length of the time interval.
Support for the processor power reporting interface is indicated by
CPUID Fn8000_0007_EDX[ProcPowerReporting] = 1.63 0
APERF_RD_ONLY
63:0 APERF_RD_ONLY APREF Read Only RO
63 0
MPERF_RD_ONLY
63:0 MPERF_RD_ONLY MPERF Read Only RO
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17.5.1  Processor Facilities
Estimating core average power involves the use of several processor facilities. Processors that support 
the processor power reporting interface define the following three facilities:
•CpuSwPwrAcc MSR
•MaxCpuSwPwrAcc MSR
•CpuPwrSampleTimeRatio (CPUID Fn8000_0007_ECX)
A fourth facility, available on all processors, is the time-stamp counter (TSC). The TSC is a free-running counter that increments on every processor clock cycle. The current value o f this counter is read using the RDTSC instruction.
The contents of the CpuSwPwrAcc register represents the cumulative energy consumed by the core. 
Each hardware-determined sample period (Tsample) a value that represents the energy consumed 
since the previous sample is added to the contents of this register. Tsample is on the order of a few microseconds. The exact value is immaterial because the CpuPwrSampleTimeRatio register provides the ratio of Tsample to the TSC period.
CpuSwPwrAcc is cleared to zero at power-on and is never reset. Therefore, it is possible for this 
counter to overflow and roll over to zero. To account for this, the interface provides the MaxCpuSwPwrAcc register. When read, this register provides a value that represents the maximum energy that the CpuSwPwrAcc register can report.
17.5.2  Software Algorithm
The following algorithm should be used to calculate the average power consumed by a processor core during the measurement interval T
M. To obtain a stable average power value, TM should be on the 
order of several milliseconds.
•Determine the value of the ratio of Tsample to the TSC period (CpuPwrSampleTimeRatio) by 
executing CPUID Fn8000_0007. Call this value N.
N = CPUID Fn8000_0007_ECX[31:0].
•Read the full range of the cumulative energy value from the register MaxCpuSwPwrAcc. 
Jmax = value returned from RDMSR MaxCpuSwPwrAcc.
•At time x, read CpuSwPwrAcc and the TSC
Jx = value returned by RDMSR CpuSwPwrAcc 
Tx = value returned by RDTSC
•At time y, read CpuSwPwrAcc and the TSC again
Jy = value returned by RDMSR CpuSwPwrAcc
Ty = value returned by RDTSC
Calculate the average power consumption for the processor core over the measurement interval TM = 
(Ty – Tx). 
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•If (Jy < Jx), rollover has occurred; set Jdelta  = (Jy + Jmax) – Jx
else Jdelta  = Jy – Jx 
•PwrCPUave = N * Jdelta  / (Ty - Tx) 
Units of result is milliwatts. 
17.6 Collaborative Processor Performance Control
AMD’s Collaborative Processor Performance Control (CPPC) feature is an implementation of the 
Collaborative Processor Performance Control standard, first introduced in the Advanced Configuration and Power Interface (ACPI) Specification Revision 5.0. CPPC provides a framework for managing the performance and power efficiency of SOCs in collaboration with Operating System Power Management (OSPM) software.
The CPPC feature provides a mechanism for the OSPM to manage the performance of a logical 
processor utilizing a continuous and abstract performance scale. CPPC implements a set of MSRs to enumerate the abstract performance scale, to request processor performance levels using that scale, and to provide feedback to the OSPM.
17.6.1  Detecting Support for CPPC
Support for CPPC is indicated by CPUID Fn8000_0008_EBX[CPPC](bit 27)=1. 
17.6.2  CPPC Model Specific Registers
Various aspects of the CPPC are managed though the model-specific registers listed in Table 17 -1 
below. These MSRs are used by the OSPM to obtain CPPC capabilities, control CPPC operations and 
obtain feedback on delivered performance.
17.6.3  Enabling CPPC
Software may enable Collaborative Processor Performance Control by setting CPPC_ENABLE[CPPC_En] (bit 0) = 1. Enabling CPPC on any one logical processor in a package enables it for all processors within that package.Table 17-1. CPPC-related MSRs
Register Name MSR Address Reference Description
CPPC_CAPABILITY_1 C001_02B0h Figure 17 -10 Specifies the CPPC performance ranges and thresholds.
CPPC_ENABLE C001_02B1h Figure 17 -9 Enables CPPC.
CPPC_CAPABILITY_2 C001_02B2h Figure 17 -11 Reports the constrained maximum performance level.
CPPC_REQUEST C001_02B3h Figure 17 -12 Conveys OSPM requests and hints to the CPPC hardware.
CPPC_STATUS C001_02B4h Figure 17 -13 Reports excursions to the minimum performance level.
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When CPPC is enabled, the hardware calculates the processor’s performance capabilities and 
initializes the performance level fields in the CPPC capability registers.
The processor ignores the P-state control interface (described in “P-State Control” on page 657) when 
CPPC is enabled.
17.6.3.1  CPPC_ENABLE
Figure 17-9. CPPC_ENABLE
The CPPC_ENABLE register fields are further described below:
•CPPC_En (CPPC Enable) —Bit 0, read/write once. Software sets this bit to enable Collaborative 
Processor Performance Control. Once CPPC is enabled the processor ignores further writes to this 
register. CPPC_En can only be cleared by reset.
17.6.4  CPPC Performance Levels and Capabilities
The OSPM can read the CPPC_CAPABILITY_1 and CPPC_CAPABILITY_2 MSRs to determine the 
performance levels and thresholds supported by the processor. These values are reported on a 
continuous scale of abstract values ranging from 00h (minimum) to FFh (maximum).
Prior to enabling CPPC, the CPPC_CAPABILTY_1 and CPPC_CAPABILITY_2 registers are 
initialized to zero. When CPPC is enabled, the hardware calculates the processors’ performance capabilities and stores the appropriate values in both CPPC capability registers.
The reported performance levels directly map to processor frequency; however, this mapping is 
specific to a processor family and implementation.The CPPC_CAPABILITY_1 and CPPC_CAPABILITY_2 registers are implemented on a per-logical 
processor basis. Each logical processor contains an independent set of CPPC capability registers.
17.6.4.1  CPPC_CAPABILITY_1
The CPPC_CAPABILITY_1 register reports the processor performance levels and thresholds.63 1 0
Reserved
CPPC_En
63:1 Reserved MBZ
0 CPPC_En CPPC enable R/W1
63 32
Reserved
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Figure 17-10. CPPC_CAPABILITY_1
The CPPC_CAPABILITY_1 register fields are further described below:
•HighestPerf[7:0] (Highest Performance)— Bits 31:24. Reports the maximum performance an 
individual processor can reach under ideal conditions. This performance level is not guaranteed 
due to system thermal and power constraints and may not be sustainable for long durations. The 
Highest Performance level may require that other processors be in a lower performance state.
•NominalPerf[7:0] (Nominal Performance)—Bits 23:16. Reports the maximum sustained performance level of the processor, assuming ideal operating conditions. In the absence of an unexpected system power or thermal constraint, the processor can maintain the nominal performance level continuously. All processors can sustain the Nominal Performance state simultaneously.
•LowNonLinPerf[7:0] (Lowest Non-Linear Performance)—Bits 15:8. Reports the most energy efficient performance level (in terms of performance per watt). Above this threshold, lower performance levels generally result in increased energy efficiency. Reducing performance below this threshold does not result in total energy savings for a given computation, although it reduces instantaneous power consumption.
•LowestPerf[7:0] (Lowest Performance)—Bits 7:0. Reports the lowest performance level of the 
processor.31 24 23 16 15 8 7 0
HighestPerf NominalPerf LowNonLinPerf LowestPerf

63:32 Reserved RAZ
31:24 HighestPerfHighest Performance - The absolute maximum perfor-
mance an individual processor may reach.RO
23:16 NominalPerfNominal (Guaranteed) Performance - The maximum sustained performance level of the processor.RO
15:8 LowNonLinPerfLowest Non-Linear Performance is the lowest perfor -
mance level at which nonlinear power savings are achieved.RO
7:0 LowestPerfLowest performance is the absolute lowest performance level of the processor.RO
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17.6.4.2  CPPC_CAPABILITY_2
The CPPC_CAPABILITY_2 register reports the constrained maximum performance level of the 
Figure 17-11. CPPC_CAPABILITY_2
The CPPC_CAPABILITY_2 register fields are further described below:
•MaxPerf[7:0] (Constrained Maximum Performance)— Bits 7:0. Reports the current maximum 
performance level considering all known external constraints (i.e., power limits, thermal limits, 
AC/DC power source, etc.).
17.6.5  Using CPPC to Manage Processor Performance
The OSPM controls CPPC operation by specifying processor performance goals and hints using the 
CPPC_REQUEST register. The values written to CPPC_REQUEST use the abstract, continuous performance scale described in Section 17.6.4 on page 665.
CPPC supports two modes of operation – directed and autonomous . In the directed mode of operation, 
the OSPM requests explicit performance targets by writing the CPPC_REQUEST[DesPerf] field. The 
CPPC hardware translates these requests into actual performance and power states (core frequency, 
data fabric and memory clocks, etc). DesPerf may be set to any performance value between CPPC_REQUEST[MinPerf,MaxPerf], inclusive.
The effective performance delivered by the CPPC hardware is guided by hints provided by the OSPM. 
These hints include minimum and maximum performance limits, plus a preference towards energy 
efficiency or performance. The OSPM programs these hints into the MinPerf, MaxPerf, and EnergyPerfPref fields of the CPPC_REQUEST register.
Autonomous mode is selected by writing zero to CPPC_REQUEST[DesPerf]. In autonomous mode, 
the hardware independently selects a performance level appropriate to the current workload. As with the directed mode, the OSPM provides hints to guide the hardware’s performance level selection, 63 32
Reserved
31 8 7 0
Reserved MaxPerf
63:8 Reserved RAZ
7:0 MaxPerf Constrained Maximum Performance RO
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including minimum and maximum performance limits and a preference for optimizing for energy 
efficiency versus performance.
17.6.5.1  CPPC_REQUEST
The CPPC_REQUEST register is used by the OSPM to convey performance requests and hints to the 
CPPC hardware.
Figure 17 -12. CPPC_REQUEST
The CPPC_REQUEST register fields are further described below:
•EnergyPerfPref[7:0] (Energy Performance Preference hint)— Bits 31:24. Provides a hint to the 
hardware if software wants to bias the processor towards performance (00h) or towards energy 
efficiency (FFh).
•DesPerf[7:0] (Desired Performance hint)—Bits 23:16. The OSPM programs this field with a non-zero value to convey a desired performance level to the hardware. The Desired Performance hint may be set to any performance value in the range [MinPerf, MaxPerf], inclusive. When programmed to zero, autonomous mode is selected, and hardware autonomously determines the 
performance level appropriate for the current workload.
•MinPerf[7:0] (Minimum Performance hint)— Bits 15:8. The OSPM programs this field to limit the 
minimum performance that is expected to be supplied by the hardware. Excursions below the minimum are possible due to unexpected system thermal or power constraints. MinPerf may be set to any performance value in the range CPPC_CAPABILITY_1[LowestPerf, HighestPerf], inclusive but must be set to a value less than or equal to MaxPerf.
•MaxPerf[7:0] (Maximum Performance hint)— Bits 7:0. The OSPM programs this field to limit the 
maximum performance for the purpose of energy efficiency or thermal control. Excursions above the maximum are possible due to hardware coordination between processor cores and other 63 32
Reserved
EnergyPerfPref DesPerf MinPerf MaxPerf
31:24 EnergyPerfPref Energy Performance Preference RW
23:16 DesPerf Desired Performance RW
15:8 MinPerf Minimum Performance RW
7:0 MaxPerf Maximum Performance RW
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components in the package. Maximum performance may be set to any performance value in the 
range CPPC_CAPABILITY_1[LowestPerf, HighestPerf] inclusive.
17.6.6  CPPC Feedback Mechanisms
The CPPC hardware provides performance feedback to the OSPM via the CPPC_STATUS MSR. The bits within the CPPC_STATUS register are sticky, and when set will remain set until software clears 
them. Software must clear these bits to enable notifications for subsequent events.
The processor sets CPPC_STATUS[MinEx] to signal that an excursion to less than minimum 
performance has occurred. This indicates that an unpredicted power or thermal event has occurred, and 
the processor has limited delivered performance to less than CPPC_REQUEST[MinPerf].
17.6.6.1  CPPC_STATUS
The CPPC_STATUS register conveys performance feedback to the OSPM.
Figure 17-13. CPPC_STATUS
The CPPC_STATUS register fields are further described below:
•MinEx (Minimum Excursion)— Bit 1. The processor sets this bit when Delivered Performance has 
been constrained to less than CPPC_REQUEST[MinPerf]. Software must clear this bit to enable 
further notifications of minimum performance excursions.
17.6.6.2  Frequency Metrics
The AMD64 architecture provides a mechanism by which the OSPM can determine the effective 
frequency of a logical processor.
The Maximum Performance Frequency Clock Count (MPERF) and the Actual Performance 
Frequency Clock Count (APERF) registers constitute the effective frequency interface. This interface 
provides a means for software to calculate an average, or effective, frequency of a core over a known 63 32
Reserved
31 2 1 0
Reserved
MinEx
Reserved
63:2 Reserved MBZ
1 MinEx Minimum Excursion has occurred R/W
0 Reserved MBZ
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window of time. See Section 17.3, “Determining Processor Effective Frequency,” on page 660 for 
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18 Shadow Stacks
The shadow stack mechanism facilitates protection against a common form of computer exploit 
known as Return Oriented Programming (ROP). ROP exploits utilize intentionally corrupted stack frames to divert normal processor control flow into short fragments of existing executable code, which ultimately end with a RET instruction. These fragments are then chained together using return addresses previously written to the stack by the attacker.
The shadow stack mechanism protects against ROP exploits by ensuring that return addresses read 
from the stack by RET and IRET instructions originated from a CALL instruction or similar control transfer.
In the following sections, the term ‘program stack’ is used to distinguish the stack pointed to by the SP 
register and manipulated by instructions (such as PUSH, POP, ENTER, LEA VE) from the shadow stack.
18.1 Shadow Stack Overview
A shadow stack is a separate, protected stack that is conceptually parallel to the program stack and used only by control-transfer and return instructions. When shadow stacks are enabled, most control transfers that save a return address (such as CALL, INTn, exceptions and interrupts) write the return address to the shadow stack in addition to the program stack. Upon the subsequent RET or IRET operation, the processor reads the return address from both stacks and checks that they match. A control-protection exception (#CP) is raised if the return addresses do not match.
The shadow stack is implemented in regions of memory marked with the “shadow stack” attribute in 
the page tables (see “Page-Protection Checks” on page 161). Pages with the shadow stack attribute are writeable only by control transfer operations that save a return address and by the shadow stack management instructions. Shadow stack pages are not writeable by ordinary data-access instructions and thus protected from tampering. 
18.1.1  Detecting and Enabling Shadow Stack Support
Support for the shadow stack feature is indicated by CPUID Fn0000_0007_ECX_x0[CET_SS](bit 
7)=1. This bit also indicates the shadow stack MSRs are present.
The shadow stack feature is enabled by setting CR4.CET (bit 23) = 1 (see “CR4 Register” on page 46).

The shadow stack feature is enabled by setting CR4.CET (bit 23) = 1 (see “CR4 Register” on page 46). 
The shadow stack feature is operational when in protected mode (CR0.PE=1) with paging enabled (CR0.PG=1). Shadow stacks are disabled in virtual x86 mode (rFLAGS.VM=1).
Once the feature is enabled, shadow stack operation can be separately enabled in user mode and in 
supervisor mode using control bits in the S_CET and U_CET MSRs (see “Shadow Stack MSRs” on page 683).
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18.2 The Shadow Stack Pointer
On processors implementing the shadow stack feature, the Shadow Stack Pointer (SSP) register 
contains the address of the current top of the shadow stack. The width of the shadow stack is 64 bits in 64-bit mode and 32 bits in legacy and compatibility modes. The address size of SSP is 64 bits in 64-bit mode and 32 bits in legacy and compatibility modes.
The SSP register cannot be encoded as a source or destination register by regular instructions and thus 
is not directly accessible to software as a general operand, nor as an address operand. The SSP register is directly accessible only by using the shadow stack management instructions (see “Shadow Stack Management Instructions” on page 682).
18.3 Shadow Stack Operation for CALL (near) and RET 
(near)
When shadow stacks are enabled, the CALL (near) instruction pushes the return address onto the 
shadow stack, in addition to pushing it onto the program stack. On the subsequent near RET/RETn instruction, the return addresses are read from both stacks and compared. If the return addresses do not match, a control-protection (#CP) exception is generated.
A CALL (near) with a displacement of 0 (CALL +0) does not push the return address onto the shadow 
stack since the “CALL +0” idiom does not actually branch to another code sequence, and is typically 
not followed by a return instruction. 
One form of the return instruction, RETn, pops ‘n’ additional parameters from the program stack 
before returning to the caller. Since the shadow stack does not store any data items, RETn does not pop additional parameters from the shadow stack. 
18.4 Shadow Stack Operation for Far Transfers
The term ‘far transfer’ in the following discussion encompasses the following types of control transfers:
•Explicit CALL (far) to a procedure in another code segment
•Exceptions and interrupts that transfer to a handler in another code segment
•RET (far) and IRET instructions
A far transfer may also change the CPL. The exact operation of the shadow stack depends on the type 
of far transfer involved, the associated CPL change (if any) and whether the shadow stack capability is enabled for the target CPL. Shadow stack operations for far transfers are described in the following sections and summarized in Table 18-1. (See AMD Architecture Programmers Manual V olume 3 for detailed instruction algorithms for CALL (far), RET (far), IRET and INTn.)
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18.5 Far Transfer to the Same Privilege Level
When shadow stacks are enabled, a far transfer to the same privilege level pushes the CS and LIP 
(linear address of the return IP) onto the current shadow stack in addition to pushing the return IP onto the program stack. Upon the subsequent RET (far) or IRET operation, the return addresses are popped from both stacks and the linear forms of the two addresses are compared. If the return addresses do not match, a control-protection (#CP) exception is generated.
18.6 Far Transfer to Different Privilege Level
In addition to changing code segments, far transfers can also be used to change to a different privilege level (CPL). When changing the CPL, inter-privilege far transfers switch to a new program stack. In a similar manner, inter-privilege far transfers also switch to a new shadow stack, providing that shadow stacks are enabled for the new privilege level.
18.6.1  Shadow Stack Switching
When an inter-privilege far transfer switches to a new program stack, the new program stack pointer is selected from the either the inner-level stack pointers in the TSS or the Interrupt Stack Table (IST), depending on the type of far transfer. (See “Interrupt To Higher Privilege” on page 272). Similarly, when shadow stacks are enabled, inter-privilege far transfers also switch to a new shadow stack. The new shadow stack pointer is selected from shadow stack pointer MSRs (PLn_SSP) or the Interrupt Shadow Stack Table (ISST) as described in the following sections. 
18.6.1.1  Shadow Stack Switching for Inter-Privilege CALL (far)
When a CALL (far) changes privilege level, a shadow stack switch occurs to an inner-level shadow 
stack. The new SSP is loaded from one of the following MSRs:
•PL2_SSP for transitions to CPL 2. 
•PL1_SSP for transitions to CPL 1. 
•PL0_SSP for transitions to CPL 0. Table 18-1. Shadow Stack Operations for Far Transfers
CALLF/int/excp 
From CPL To CPLStack 
switch?New SSP loaded 
from: (where 
n=new CPL)CS, LIP saved to 
and restored from:SSP saved to and 
restored from:RETF/IRET 
checks returns 
address?
0,1,2,3 Same No Uses current SSPCurrent Shadow 
StackCurrent Shadow StackYes
3 0,1,2 Yes PLn_SSP <not saved/restored> PL3_SSP No
2 0,1 Yes PLn_SSP New shadow stack New shadow stack Yes
1 0 Yes PLn_SSP New shadow stack New shadow stack Yes
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When switching shadow stacks, the processor validates the new shadow stack using a special value 
called a shadow stack token as described in Section 18.6.3 “Supervisor Shadow Stack Token” on 
page 675.
18.6.1.2  Shadow Stack Switching for Interrupts and Exceptions
In long mode (EFER.LMA=1), the processor provides an additional mechanism, the Interrupt Stack 
Table (IST) to switch program stacks for interrupts and exceptions. The IST mechanism uses the IST field in the Interrupt Descriptor Table (IDT) entry as an index into a table of inner-level program stack pointers (see “Interrupt-Stack Table” on page 284). The shadow stack feature provides a similar mechanism, the Interrupt Shadow Stack Table (ISST), for switching shadow stacks. 
The ISST is an 8-entry table containing supervisor shadow stack pointers. The base of the ISST is 
specified by the INTERRUPT_SSP_TABLE MSR. If the IST field in the IDT entry is non-zero, it is used as an index into the ISST to select a new SSP as shown in Figure  “” on page 674.
If the IST field is zero or if the processor is not in long mode, the ISST mechanism is not used and the 
new inner-level SSP is selected from the PLn_SSP MSRs as previously described in Section 18.6.4 
“Shadow Stack Switching for Inter-Privilege CALL (far)” on page 673.
Figure 18-1. Interrupt Shadow Stack Table (ISST)
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18.6.2  Handling CS, LIP and SSP on Privilege Transistions
When changing to a new code segment, the shadow stack behavior for saving and restoring CS, LIP 
and SSP depends on the CPL of the originating far transfer.
Transitions from CPL=3Inter-privilege far transfers originating at CPL=3 save the current user-level SSP to PL3_SSP rather 
than to the supervisor shadow stack. Upon the subsequent RETF/IRET back to CPL=3, the user-level SSP is restored from PL3_SSP and the return CS and LIP are not verified. 
Transitions from CPL=1 and CPL=2Far transfers originating at CPL=1 or CPL=2 to an inner (more privileged) level save the current CS, 
LIP and SSP to the inner level shadow stack after switching shadow stacks as described in section Section 18.6.1, “Shadow Stack Switching,” on page 673. Upon the subsequent RET(far)/IRET, the 
SSP is restored (Section 18.6.1, “Shadow Stack Switching,” on page 673) from the inner-level shadow 
stack and the CS and LIP popped from the shadow stack are verified against the values read from the program stack. If the return addresses do not match, a control-protection (#CP) exception is generated.
18.6.3  Supervisor Shadow Stack Token
When switching shadow stacks, the processor validates the new shadow stack by checking a supervisor  shadow stack token  located at the base of the stack. 
When initially creating a shadow stack for use at privilege levels 0, 1 and 2, system software must place a supervisor shadow stack token at the base of each stack. System software must also store a pointer to each shadow stack in the appropriate shadow stack base register, PLn_SSP (n=0,1,2,3) using the WRMSR instruction.
The relationship of the shadow stacks, supervisor shadow stack tokens, and the PLn_SSP registers are 
shown in Figure 18.6.3 “Shadow Stacks and Supervisor Shadow Stack Tokens” on page 676. The three supervisor shadow stacks (PL0, PL1 and PL2) have shadow stack tokens stored at the base of the stack. Tokens are not used for PL3 shadow stacks.
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Figure 18-2. Shadow Stacks and Supervisor Shadow Stack Tokens
The supervisor shadow stack token is a 64-bit value and is formatted as shown in Figure 18 -3: 
Figure 18-3. Supervisor Shadow Stack Token
The supervisor shadow stack token fields are defined as follows:
Linear Address. Bits 63:3 of the linear address of this token. The linear address is required to be 8-
byte aligned.

Rsvd.  Reserved, must be zero.
Busy Bit.  If 0, this indicates this supervisor shadow stack is not in use by any logical processor. If 1, it 
indicates this supervisor shadow stack is currently in use by one of the logical processors. The 
processor sets the busy bit when switching to a supervisor shadow stack and clears it when switching away from that stack. 
18.6.4  Shadow Stack Token Validation for Inter-privilege CALL (far) and 
Before switching shadow stacks, a CALL (far) or an interrupt/exception that changes to a more 
privileged level validates the supervisor shadow stack token located at the base of the new stack. If the validation checks pass, the supervisor shadow stack token is marked busy. The following steps are performed to validate the supervisor shadow stack token and set the busy bit:63 3 2 1 0
Linear Address Rsvd Busy
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1. Check that the incoming SSP is 8-byte aligned, otherwise a #GP exception is generated. The
incoming SSP is located in PLn_SSP (where ‘n’ is the new privilege level: 0, 1, 2), or the ISST
for interrupts/exceptions (see Section 18.6.1, “Shadow Stack Switching,” on page 673).
<Steps 2-6 are performed atomically.>
2. Fetch the 8-byte shadow stack token using the address specified by the incoming SSP (using a
locked load with shadow stack access rights).
3. Check that the shadow stack token reserved bits and the busy bit are 0.4. Check that the address specified in the shadow stack token matches the incoming SSP.5. If checks 3 and 4 pass, set the supervisor shadow stack token busy bit (using a store, unlock).6. If checks 3 or 4 fail, the shadow stack token is not modified and a #GP exception is generated. 
18.6.5  Shadow Stack Token Validation for Inter-privilege RET and IRET
RET (far) and IRET to lower privilege levels validate the shadow stack token located on the current 
supervisor shadow stack before switching shadow stacks. If the token is valid, the token’s busy bit is cleared. The processor performs the following steps to validate the token: 
1. Check that the return SSP (located on the current shadow stack) is 4-byte aligned, else a #CP
exception is generated.
<Steps 2-7 are performed atomically.>2. Fetch the 8-byte shadow stack token from the current shadow stack at SSP+24 (using a locked
load with shadow stack access rights).
3. Check that the busy bit is 1.4. Check that the reserved bits are 0.5. Check that the address specified in the shadow stack token matches the SSP.6. If checks 3 through 5 pass, the shadow stack token busy bit is cleared.7. If any of checks 3 through 5 fail, the shadow stack token is not modified. A fault is not generated.
18.7 Shadow Stack Operation for SYSCALL and SYSRET
SYSCALL and SYSRET are low-latency system call and return instructions designed for use by 
system and application software implementing a flat-memory model. These instructions do not use the program stack to store return addresses, and therefore do not use the shadow stack to validate return addresses. However, SYSCALL and SYSRET modify SSP as described below. The Shadow stack operations described for SYSCALL and SYSRET also apply to SYSENTER and SYSEXIT respectively, although the latter are available only in legacy mode.
The SYSCALL instruction is used by application software executing at CPL=3. When shadow stacks 
are enabled at CPL=3, SYSCALL saves the current SSP to PL3_SSP. SYSCALL changes to CPL=0 
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before entering the operating system and if shadow stacks are enabled at CPL=0, then SSP is cleared to 
0. 
Unlike other inter-privilege far transfers, SYSCALL does not automatically perform a switch to a 
supervisor shadow stack. If shadow stacks are enabled at CPL=0, prior to executing a CALL instruction or similar transfer of control that pushes a return address to the shadow stack, software at the OS entry point must ensure that a supervisor shadow stack is available for use. System software can use SETSSBSY to set up a supervisor shadow stack.
The operating system uses the SYSRET instruction to return to the application running at CPL=3. If 
shadow stacks are enabled at CPL=3, SYSRET restores SSP from PL3_SSP. Prior to using SYSRET to return to the application, system software can use the CLRSSBSY to tear down the supervisor shadow stack. Because CLRSSYBSY clears the SSP to 0, system software must ensure that any subsequent interrupt or exception that may occur in CPL=0 prior to the SYSRET is configured to use the ISST stack-switching mechanism. Otherwise taking an interrupt or exception with SSP=0 will likely result in a fault due to SSP wrap-around. 
18.8 Shadow Stack Operation for Task Switches
The legacy x86 task-switch mechanism transfers program control to a new task when any of the following control transfers occur:
•A CALL or JMP instruction references a task gate or TSS descriptor.
•A software-interrupt instruction (INTn), exception or external interrupt references a task gate. 
•An IRET is executed when the EFLAGS.NT bit is set to 1.
Shadow stack operations for legacy x86 task switches are summarized in this section. Because the x86 
task management feature is supported by the AMD64 architecture only in legacy mode (EFER.LMA=0), the shadow stack operations described below only apply to legacy mode. (See “Switching Tasks” on page 379 for more information on task switching). 
When switching to a new task with shadow stacks enabled, the new task must use a 32-bit TSS. The 
SSP for the new task is located at TSS offset 104. Since the SSP is 4 bytes in legacy mode, the TSS must be at least 108 bytes in size. The SSP must be aligned to an 8-byte boundary and point to a supervisor shadow stack token.
If the task switch is initiated by a CALL/JMP/INTn instruction, or an interrupt or exception:
•For task switches originating at CPL=3, and if shadow stacks are enabled at that CPL, the current 
SSP is saved to PL3_SSP. Otherwise, for task switches originating at supervisor-level (CPL=0,1,2) the current SSP is saved onto the new shadow stack along with current CS and LIP. If shadow stacks are enabled at the CPL of the new task, the busy bit is set in the supervisor shadow stack token pointed to by the SSP of the incoming task.
If the task switch is initiated by an IRET instruction:
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•For task switches originating at supervisor-level (CPL=0,1,2) and returning to CPL=3, the SSP is 
restored from PL3_SSP, otherwise the SSP is restored from the current shadow stack. The return CS and LIP are read from the current shadow stack and compared to the CS and linear form of the EIP in the TSS of the incoming task. A control-protection (#CP) exception is generated if the return addresses do not match.
18.9 Restricting Speculative Execution of RET targets
When shadow stacks are enabled, the processor will not speculatively execute instructions from a RET address on the program stack unless the address matches the corresponding address on the shadow stack, or the target of the RET is predicted by a return address branch prediction mechanism. 
18.10 Shadow Stack Switching Using RSTORSSP
As previously described in Section 18.6.1, “Shadow Stack Switching,” on page 673, the processor 
automatically switches shadow stacks as part of the inter-privilege far transfer mechanism. In order to allow programs to switch stacks at other times (when performing operations such as initializing a shadow stack or recovering from a #CP fault) the RSTORSSP and SA VEPREVSSP instructions are provided. 
The RSTORSSP instruction is used to switch shadow stacks. The instruction expects to find a shadow 
stack restore token at the top of the proposed new shadow stack. Upon validating this token, RSTORSSP points the SSP to the top of the new shadow stack and sets the token’s busy bit, making the new shadow stack ready for use.
Upon successful completion, the RSTORSSP instruction modifies the restore token by saving the old 
SSP into the token’s SSP Restore Value field in order to facilitate a later return to the old shadow stack.
The shadow stack restore token used by RSTORSSP is formatted as follows:
Figure 18-4. Shadow Stack Restore Token
The shadow stack restore token fields are defined as follows:SSP Restore value. Bits 63:2 of the linear address of this token. Replaced by the previous SSP upon 
successful completion of the RSTORSSP instruction.
Busy. Initially must be 0. Set to 1 upon successful completion of the RSTORSSP instruction.
Mode. If 0, this indicates the shadow stack restore token is for use in legacy or compatibility mode. If 
1, this indicates the restore token is for use in 64-bit mode.63 2 1 0
SSP Restore Value / Token Address Busy Mode
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After RSTORSSP switches to the new stack the modified shadow stack token is at the top of the new

After RSTORSSP switches to the new stack the modified shadow stack token is at the top of the new 
in-use shadow stack. If a return to the old stack is not required, the modified token (to which the previous SSP has been saved) can be popped from the stack using the INCSSP instruction. 
If a return to the old stack is desired, the SA VEPREVSSP instruction can be used to copy the token 
back to the previous stack for later use by an RSTORSSP instruction. The SA VEPREVSSP expects to find a previous SSP token on the top of the current shadow stack. After moving this token to the 
previous stack, SA VEPREVSSP pops it off the new stack by incrementing SSP.
The previous SSP token used by SA VEPREVSSP is formatted as follows:
Figure 18-5. Previous SSP Token
The previous SSP token fields are defined as follows:Previous SSP. Bits 63:2 of the previous SSP. Upon successful completion, the SA VEPREVSSP 
instruction copies the token to this address.Busy. Must be set to 1 initially. Cleared to 0 upon successful completion of the SA VEPREVSSP 
instruction.Mode. If 0, this indicates the previous SSP token is for use in legacy or compatibility mode. If 1, this 
indicates the token is for use in 64-bit mode.Figure 18 -6 “RSTORSSP and SA VEPREVSSP Operation” on page 681 illustrates the operation of the 
RSTORSSP instruction when switching to a new shadow stack, followed by a SA VEPREVSSP 
instruction to save a previous token back to the original stack.63 2 1 0
Previous SSP Busy Mode
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Figure 18-6. RSTORSSP and SAVEPREVSSP Operation
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In this example (Figure 18 -6 “RSTORSSP and SA VEPREVSSP Operation” on page 681), 
RSTORSSP is used to switch from shadow stack A to shadow stack B. Subsequently, a 
SA VEPREVSSP instruction is used to save a shadow stack restore token.
Initially, shadow stack A is in-use, and the proposed shadow stack B contains a shadow stack restore 
token at address B - 8. An RSTORSSP instruction is then executed with the operand pointing to the restore token.
The RSTORSSP instruction checks the restore token for validity, copies the previous SSP to the token, 
sets bit 1 of the token and sets the new value of SSP to address B. Shadow stack B is now ready for use.
Next, a SA VEPREVSSP instruction is executed to facilitate a later return to shadow stack A (using a 
subsequent RSTORSSP instruction, not shown). The SA VEPREVSSP instruction copies the token to address A - 8 and clears token bit 1, then pops the old token from shadow stack B.
For detailed RSTORSSP and SA VEPREVSSP algorithms refer to the instruction descriptions in APM 
V olume 3.
18.11 Shadow Stack Management Instructions
When shadow stacks are enabled, the following instructions are available to software for use in managing shadow stacks. Except for RDSSP, attempting to execute these instructions when shadow stacks are disabled results in a #UD exception. RDSSP is treated as a NOP when shadow stacks are disabled. For more information refer to the detailed instruction descriptions in APM volume 3.
Table 18 -2. Shadow Stack Management Instructions
Mnemonic Name Description 
CLRSSBSYClear Shadow Stack 
BusyValidates a shadow stack token and clears its busy bit. This is a privileged instruction.
INCSSPIncrement Shadow Stack PointerIncrement SSP by ‘n’ stack frames. Used to pop unneeded items from a shadow stack.
RDSSPRead Shadow Stack PointerRead the SSP into a GPR. Treated as a NOP if shadow stacks are disabled.
RSTORSSPRestore Shadow Stack PointerUsed to switch shadow stacks. Expects a ‘shadow stack restore token’ at the top of the new shadow stack. Upon validating this token, sets the token’s busy bit and sets SSP to the top of the new shadow stack.
SA VEPREVSSPSave Previous Shadow Stack PointerCopies a ‘previous SSP token’ from the current shadow stack back to the previous stack for later use by an RSTORSSP instruction. 
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18.12 Shadow Stack MSRs
The following MSRs are defined if the shadow stack feature is supported as indicated by CPUID Fn 
0000_0007_0 ECX[CET_SS] (bit 7) = 1:
U_CET . MSR 0x6A0. Specifies the user mode shadow stack controls. The individual fields are as 
follows:
•Bit 0 - SH_STK_EN. When set to 1, enables the shadow stacks in user mode.
•Bit 1 - WR_SHSTK_EN. When set to 1, enables the WRSS instruction is user mode.
•Bits 63:2 – reserved, MBZ
S_CET.  MSR 0x6A2. Specifies the supervisor mode shadow stack controls.
•Bit 0 - SH_STK_EN. When set to 1, enables the shadow stacks in supervisor mode.
•Bit 1 - WR_SHSTK_EN. When set to 1, enables the WRSS instruction is supervisor mode.
PL0_SSP.  MSR 0x6A4. Specifies the linear address to be loaded into SSP on the next transition to 
CPL=0. The linear address must be in canonical format and aligned to 4 bytes when initializing this 
register.
PL1_SSP . MSR 0x6A5. Specifies the linear address to be loaded into SSP on the next transition to 
CPL=1. The linear address must be in canonical format and aligned to 4 bytes when initializing this 
register.
PL2_SSP.  MSR 0x6A6. Specifies the linear address to be loaded into SSP on the next transition to 
CPL=2. The linear address must be in canonical format and aligned to 4 bytes when initializing this 
register.
PL3_SSP.  MSR 0x6A7. The user mode SSP is saved to and restored from this register. The linear 
address must be in canonical format and aligned to 4 bytes when initializing this register.ISST_ADDR.  MSR 0x6A8. This register specifies the linear address of the Interrupt Shadow Stack 
Table (ISST). The linear address must be in canonical format.SETSSBSYSet Shadow Stack 
BusyValidates the shadow stack token pointed to by the PL0_SSP MSR. If valid, clears the busy bit and sets SSP = PL0_SSP. This is a privileged instruction.
WRSS Write Shadow StackWrites the source operand to a shadow stack. This instruction has associated enable bits in the U_CET and S_CET MSRs
WRUSSWrite User Shadow StackWrites the source operand to a user shadow stack. This is a privileged instruction.Table 18 -2. Shadow Stack Management Instructions (continued)
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18.13 XSAVE/XRSTOR
The XSA VE/XRSTOR instructions can be used to manage the shadow stack registers as processor 
extended state components 11 (CET_U state) and 12 (CET_S state) as described below:
• CET_U state.  The shadow stack user controls are identified as state component 11 in 
XFEATURE_ENABLED_MASK and consist of the two 64-bit MSRs U_CET and PL3_SSP. 
Bytes 7:0 in the XSA VE area are used for U_CET and bytes 15:8 are used for PL3_SSP. The XSA VE area size and offset for the CET_U state are available using CPUID Fn0000_000D_ECX_x0B (ECX=11).
• CET_S state. The shadow stack supervisor controls are identified as state component 12 in 
XFEATURE_ENABLED_MASK and consist of the three 64-bit MSRs PL0_SSP, PL1_SSP and PL2_SSP. Bytes 7:0 in the XSA VE area are used for PL0_SSP, bytes 15:8 are used for PL2_SSP and bytes 23:16 are used for PL3_SSP. The XSA VE area size and offset for the CET_S state are available using CPUID Fn0000_000D_ECX_x0C (ECX=12). 
The CET_U and CET_S state components are managed by XSA VE/XRSTOR by setting bits 11 and 12 respectively in XFEATURE_ENABLE_MASK. See Section 11.5.2, 
“XFEATURE_ENABLED_MASK,” on page 355 for more details. When restoring CET_U and CET_S state, XRSTOR checks for reserved bits and canonicality as described in Section 18.11 “Shadow Stack Management Instructions” on page 682. 
System software can enable XSA VES/XRSTORS management of the CET_U and CET_S state 
components by setting bits 11 and 12 respectively in the XSS MSR.
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19 Platform Quality of Service (PQOS) 
Extension
The AMD PQOS Extension provides system software (operating system, hypervisor, or similar 
software) with mechanisms to monitor usage of shared platform resources such as L3 cache by a logical processor, thread, application, or guest OS. The PQOS extension also provides system software with the ability to set and enforce limits on usage of certain shared platform resources.
In shared environments, such as those found in cloud computing installations, multiple threads, or 
applications contending for a shared resource can cause significant impact to collocated workloads. For example, contention for a resource such as the last-level cache may cause violation of service-level objectives. Contention for shared resources may also cause latency spikes that violate runtime objectives of latency-sensitive tasks. The PQOS extension can be used to minimize the effects of contention for shared resources from co-located workloads.
19.1 PQOS Extension Overview
The PQOS extension provides for the monitoring  of the usage of certain shared resources and, 
separately, for the enforcement  of limits on the use of shared resources.

separately, for the enforcement  of limits on the use of shared resources. 
The monitoring and enforcement functions of PQOS are not necessarily applied across the entire system, but in general apply to a QOS Domain, which corresponds to a level in the processor hardware hierarchy containing a shared resource. In some implementations, the QOS Domain is a Core-Complex and the shared resource whose usage is monitored or regulated by PQOS is the last-level cache. 
Platform QOS features are implemented on a logical processor basis. Therefore, multiple threads 
(logical processors) in a single CPU core have independent PQOS resource monitoring and enforcement configurations.
The set of resources that may be monitored, and the set for which limits can be enforced, are 
implementation-dependent and enumerated by a CPUID function on a feature and sub-feature basis, as described in the following sections.
The PQOS extension consists of two separate but related features—PQOS Monitoring (PQM) and  
PQOS Enforcement (PQE) . 
The PQM feature provides mechanisms for monitoring the usage of shared resources. The set of 
resources that can be monitored and the specific usage metrics that may be tracked for those resources are implementation-dependent and enumerated by CPUID (see Section 19.2.1).   
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PQM can be used to monitor usage of the following resources:
•L3 cache occupancy (see Section 19.3.2)
•L3 cache bandwidth (see Section 19.3.3)
The ability to set and enforce limits on usage of shared resources is provided by the PQE feature. The 
set of resources for which limits can be enforced is implementation-dependent and enumerated by CPUID (see Section 19.4.1). PQE can be used to enforce limits on the usage of the following resources: 
•L3 cache allocation (see Section 19.4.2 and Section 19.4.3)
•L3 cache bandwidth (see Section 19.4.4, Section 19.4.5, Section 19.4.6, and Section 19.4.7)
19.1.1  Detecting Support for PQOS
Overall support for the PQOS extension is indicated by CPUID Fn0000_0007_EBX[PQE, PQM] as 
described in Table 19 -1.
•PQM, EBX bit 12. This bit also indicates the PQM-related MSRs are present. (See “PQM MSRs” on page 689).
•PQE, EBX bit 15. This bit also indicates that certain PQE-related MSRs are present. (See “PQOS Enforcement (PQE)” on page 701).
19.1.1.1  PQOS Versions
Identifying the attributes and capabilities of the PQOS extension is generally performed using CPUID 
functions. However, some early implementations also use a PQOS version  number in addition to 
CPUID. Table 19 -2 identifies the PQOS Version associated with a product of a specific 
Family/Model.Table 19-1. CPUID Fn000_0007_EBX_x0 Extended Feature Identifiers
EBX Bit Name Description
12 PQM PQOS Monitoring Feature
15 PQE PQOS Enforcement Feature
Table 19-2. PQOS Versions
Family Model Version
17h 30h–90h V1.0
19h 00h–0Fh V2.0
19h 20h–5Fh V2.0
All othersIn later implementations, only CPUID is needed to identify PQOS capabilities and PQOS Version is not used.
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19.1.2  Identifying PQM and PQE Capabilities
The PQM and PQE features operate on specific shared platform resources, such as the L3 cache. The 
set of shared resources supported by PQM and PQE are implementation-dependent and identified by CPUID functions Fn0000_000F and Fn0000_0010 respectively. Each of these CPUID functions provide a base leaf (ECX=0) which identifies the shared resource types supported by PQM and PQE and one or more sub-leaves (ECX=1,2,3…) that report additional attributes and capabilities for each shared resource as described in Section 19.2.1 and Section 19.4.1. A complete description of these CPUID functions can be found in Appendix E of APM volume 3. 
19.2 PQOS Monitoring (PQM) Overview 
The ability to monitor resource usage of shared resources is provided by the PQM feature. Monitoring is accomplished by assigning a software-defined Resource Management Identifier (RMID) to a logical processor and at some later time reading the usage metrics of a particular monitored resource by that RMID.
19.2.1  Detecting PQM Monitoring Resources and Capabilities
Once overall support for PQM has been established, support for specific PQM sub-features may be 
determined using CPUID functions Fn00000_000F and Fn8000_0020.
The PQM feature operates on specific shared platform resources, such as the L3 cache. The set of 
shared resources supported by PQM is implementation dependent and identified by CPUID functions Fn0000_000F. The base leaf (ECX=0) identifies the overall resource types supported by PQM. Each supported resource is identified by a bit in EDX as shown in Table 19 -3. This CPUID leaf also reports 
the largest RMID supported for any resource monitored by PQM.
Additional PQM capabilities associated with each resource are returned by executing CPUID 
Fn0000_000F with ECX equal to that resource’s bit number. For example, CPUID Fn0000_000F_x1 (ECX=1) returns L3-specific monitoring capabilities. See Table 19 -4 for details.
CPUID Fn0000_000F_x1 returns the following information about the L3 Cache Monitoring feature:Table 19-3. CPUID Fn0000_000F_x0 PQM Capabilities
EDX Bits
0 – Reserved
1 L3CacheMon L3 monitoring capability
31:2 – Reserved
EBX Bits
31:0 Max_RMID Largest RMID supported for any PQM resource
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•If EAX is non-zero, it indicates the size of the L3 monitoring counter, offset from 24 bits. If EAX is 
0, the counter size is determined by the PQOS version number as described in Table 19 -7 on 
page 693.
•EBX identifies the counter scaling factor. The QM_CTR value must be multiplied by this scaling 
factor to obtain the cache occupancy or bandwidth used in bytes.
•ECX identifies the largest RMID for L3 monitoring. Writing a larger value to the RMID field in the QM_EVTSEL register results in a #GP(0) exception.
•EDX identifies the specific L3 usage events that can be monitored. See Table 19 -4. This bit vector 
also identifies the valid EvtID selections for use in the QM_EVTSEL registers.
Extended L3 Cache Monitoring capabilities are enumerated by Fn8000_0020_EBX_x0 as described in Table 19 -5.Table 19-4. CPUID Fn0000_000F_EDX_x1 PQM Event Identifiers
EDX bits PQM event identifier Description
0 L3 Occupancy L3 cache occupancy
1 L3 total bandwidthL3 Cache Bandwidth Monitoring Event 0
At reset, this event tracks Total L3 Bandwidth. However, if BMEC is supported, the specific types of L3 bandwidth sources to be tracked are configurable. See Section 19.3.3.2 below.
2 L3 local bandwidthL3 Cache Bandwidth Monitoring Event 1At reset, this event tracks Local L3 Bandwidth. However, if BMEC is supported, the specific types of L3 bandwidth sources to be tracked are configurable. See Section 19.3.3.2 below.
31:3 – Reserved
Table 19-5. Fn8000_0020_EBX_x0 PQM Extended Feature Identifiers
EBX Bits Name Description
1 L3MBE Memory Bandwidth Enforcement. See Section 19.4.5.
2 L3SMBE Slow Memory Bandwidth Enforcement. See Section 19.4.6.
3 BMECBandwidth Monitor Event Configuration (BMEC).See Section 19.3.3.2.
5 ABMCAssignable Bandwidth Monitoring Counters (ABMC). See Section 19.3.3.3.
6 SDCIAE SDCI Allocation Enforcement. See Section 19.4.7.
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19.3 L3 Cache Monitoring
System software obtains the usage metrics for a particular resource by writing the RMID and Event 
Identifier (EvtID) to the QM_EVTSEL register and then reading the usage count from the QM_CTR register. See Section 19.3.1 for details on the PQM MSRs. 
Each PQM usage metric is assigned an EvtID. The EvtID selects which of the monitored metrics is 
reported for the specified RMID. The EvtID is one more than the event identifier as reported in EDX by CPUID Fn0000_000F_x1. For example, the event identifier for L3 Cache Occupancy Monitoring is bit 0, thus its EvtID is 1.
The association of an RMID with a processor is performed by writing an RMID to the PQR_ASSOC 
MSR. Each logical processor can be assigned a unique RMID, or the same RMID can be assigned to multiple logical processors to track a multi-threaded application’s shared resource usage. The monitoring hardware tracks and reports usage of shared resources (such as the L3 cache occupancy) on a per-RMID basis.
Software may associate multiple processors with the same RMID at the same time. If the processors 
are located within the same QOS Domain, the resource usage by all these processors is accumulated and the total is reported by the monitoring hardware.
For PQOS Version 1.0 and 2.0, as identified by Family/Model, the QM_EVTSEL register is shared by 
all the processors in a QOS Domain. It is software’s responsibility to ensure that no other process changes the QM_EVTSEL register between the time it is written and the time the QM_CTR read occurs. For later implementations, each processor in the QOS Domain has a private QM_EVTSEL and QM_CTR register pair, therefore software does not require synchronization between processors in the QOS Domain to use the register pair.

Writing a value larger than the MAX_RMID (CPUID Fn0000_000F_EBX_x0[MAX_RMID] to the 
QM_EVTSEL register will result in a #GP(0) exception. Writing to the QM_EVTSEL register an undefined EvtID or an RMID value greater than the largest RMID supported for that specific resource will cause the subsequent read of the QM_CTR to return 1 in the E (error) field.
19.3.1  PQM MSRs
The following MSRs are used by the PQM feature:
•PQR_ASSOC, MSR C8Fh. This MSR is used to assign an RMID to a logical processor.
•QM_EVTSEL, MSR C8Dh. This MSR is used to request a selected usage metric for a given 
RMID be returned to the QM_CTR MSR.
• QM_CTR, MSR C8Eh. This MSR is used to report the requested usage metric.
Each of these MSRs are described in detail below.
19.3.1.1  PQR_ASSOC
This MSR is used by system software to assign an RMID or a COS to a logical processor. 
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Figure 19-1. PQR_ASSOC
•COS[4:0] (Class of Service) – bits 35:32, read/write. System software uses the COS field to assign 
an arbitrary, numeric Class of Service value to this logical processor. Based on the COS, the PQOS hardware can enforce limits on usage of shared resources. At reset, the COS value is cleared to 0. The size of the COS field is implementation dependent. Software must use CPUID Fn0000_0010_EDX_x1[Max_COS](bits 15:0) to determine the largest COS value supported by the processor. An attempt to write a larger value than Max_COS results in a #GP(0) exception. 
•RMID[11:0] (Resource Monitoring Identifier) – bits 11:0, read/write. The RMID field specifies an identifier that the PQOS hardware will use to tag usage of monitored events. Software subsequently uses the RMID value to retrieve the usage data for a particular monitored event. At reset, the RMID value is cleared to 0.
The size of the RMID field is implementation dependent. Software must use CPUID 
Fn0000_000F_EBX_x0[Max_RMID](bits 31:0) to determine the maximum RMID value supported by the processor. An attempt to write a larger value than Max_RMID results in a #GP(0) exception. 
19.3.1.2  QM_EVTSEL
This MSR is used to request a selected usage metric for a given RMID be returned to the QM_CTR 
MSR.63 36 35 32
Reserved COS
31 12 11 0
Reserved RMID
Bits Mnemonic DescriptionAccess 
type
63:36 – Reserved MBZ
35:32 COS Class of Service R/W
31:12 – Reserved MBZ
11:0 RMID Resource Monitor Identifier R/W
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Figure 19-2. QM_EVTSEL
The fields within the QM_EVTSEL register are:
•RMID[11:0] (Resource Monitoring Identifier) – bits 43:32, read/write. To read the usage of a 
particular monitored resource/event by an RMID, the corresponding EvtID and RMID are written to the QM_EVTSEL register, and the resulting usage is then read from the QM_CTR register. The width of the RMID field matches the width of the QM_ASSOC.RMID field.
•ExtEvtID (Extended Event Identifier) – bit 31. When set, the EvtID field refers to Extended Event Identifiers as shown in Table 19 -6.
Note: This bit is MBZ unless L3_QOS_EXT_CFG.ABMC_En is set. 
•EvtID[7:0] (Event Identifier) – bits 7:0, read/write. This field specifies the PQM resource or event for which usage will be returned in the QM_CTR register. EvtID encodings are defined in Table 19 -6.63 44 43 32
31 30 8 7 0ExtEvtID Reserved EvtID
63:44 – Reserved MBZ
43:32 RMID Resource Monitoring Identifier R/W
31 ExtEvtID Extended Event Identifier R/W ( see note)
30:8 – Reserved MBZ
7:0 EvtID Event Identifier R/W
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19.3.1.3  QM_CTR
QM_CTR is used to report the usage metric selected by the QM_EVTSEL register.
 
Figure 19 -3. QM_CTR
The fields within the QM_CTR register are:
• E (Error) – bit 63, read only. The E bit is set if an error occurs upon access to the counter, such as 
an illegal EvtID or RMID.
• U (Undefined) – bit 62, read only. The U bit is set if the count for this EvtID is not currently avail-
able. The monitoring hardware may set the U bit at any time to indicate that the requested event 
count for the specified RMID is not currently available. This is generally a temporary condition and subsequent reads may succeed.
• CNT (Count) – bits CNT_LEN-1:0, read only. The CNT field reports the usage data for moni-
tored resources and events. To read the usage of a particular monitored resource/event by an RMID, the corresponding EvtID and RMID are written to the QM_EVTSEL register, and the resulting usage data is then read from the QM_CTR register. The value in the count field must be Table 19-6. QM_EVTSEL.EvtID Encodings
ExtendedEvtID Value Name Description
01 L3OccMon L3 cache monitoring event.
2 L3BWMonEVT0L3 cache bandwidth monitoring event 0. At reset, this 
event tracks TOTAL L3 memory bandwidth. However, if BMEC is supported the types of bandwidth tracked by this event can be configured.
3 L3BWMonEVT1L3 cache bandwidth monitoring event 1. At reset, this event tracks LOCAL L3 memory bandwidth. However, if BMEC is supported, the types of bandwidth tracked by this event can be configured.
1 1 L3CacheABMCAssignable Bandwidth Monitoring Counter (ABMC) access.
63 62 CNT_LEN CNT_LEN-1 0
E U Reserved COUNT
63 E Error on access to counter RO
62 U Count for this event is currently unavailable RO
61:CNT_LEN – Reserved, read as zero RAZ
CNT_LEN-1:0 CNT Count of monitored resource or event RO
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scaled by multiplying by the scale factor reported by CPUID Fn0000_000F_EBX_x1[Scaling -
Factor]. 
•The size of the CNT field (CNT_LEN) is implementation-dependent and is identified by
CPUID Fn0000_000F_EAX_x1[CounterSize]. If CounterSize is non-zero, the width of theCNT field in bits is (CounterSize + 24). For example, if the value of CounterSize is 20, then theCNT field is 44 bits wide. If CounterSize is 0, use the PQOS Version (see Table 19 -2 on
page 686) and the following table to identify the counter size.
19.3.2  Monitoring L3 Occupancy
Monitoring L3 cache occupancy is accomplished by first assigning a RMID to a given logical 
processor or group of processors. Then, at some later time, the L3 cache occupancy metric may be read by writing the RMID and the L3 Occupancy identifier (EvtID =1) to the QM_EVTSEL register and reading the resulting value from the QM_CTR register. The monitoring hardware may not keep a precise count of the L3 cache occupancy associated with a given RMID; the L3 cache occupancy value returned is an approximation.
The value returned in QM_CTR must be multiplied by the L3 Cache Scaling Factor to obtain the 
approximate number of bytes in the L3 cache currently associated with the supplied RMID. The L3 Cache Scaling Factor is returned by CPUID Fn0000_000F_EBX_x1[ScalingFactor](bits 31:0).
The QOS Domain for L3 occupancy monitoring is an L3 cache and all the processors which share 
that cache. When using L3 occupancy monitoring, L3 cache lines are tagged with the current RMID value in the PQR_ASSOC register of the processor which installed the cache line. When the QM_CTR is read for that RMID, the monitoring hardware reports an approximation of the amount of the L3 cache contents currently associated with that RMID in the L3 QOS Domain of the processor performing the read. 
If two processors in the same L3 QOS Domain are running with different RMIDs and both processors 
access a given cache line, that line may be associated with either of the RMIDs. Subsequently, the line may remain associated with the RMID with which it was first associated, or its RMID association may change over time, depending on cache access patterns.
Similarly, if the RMID of a processor is changed but that processor continues to access cache lines 
which have been associated with the previous RMID, those cache lines may continue to be reported as belonging to the first RMID for an indefinite period.
If software changes the of association of RMIDs with processors such that an RMID is no longer in 
use by any processor, the L3 occupancy count for that unused RMID will not immediately drop to zero. Lines which were installed in the L3 cache and associated with that RMID may remain in the cache until they are replaced through normal cache replacement mechanisms or software explicitly Table 19-7. Counter Size when Fn0000_000F_EAX_x1[CounterSize] = 0
PQOS Version Counter Size (Bits)
V1.0 62
V2.0 44
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flushes the lines using CLFLUSH, WBINVD, or INVD instructions.
Note: L3 cache occupancy as reported by the monitoring hardware is an approximation. Software

V1.0 62
V2.0 44
must not assume that an L3 occupancy measurement of zero is an indication that no linesremain in the cache which were installed by processors running for a given RMID. The L3cache occupancy monitor should never be used to determine whether cache flushing may beskipped in situations which would ordinarily require cache flushing for functionalcorrectness.
After writing the corresponding EvtID and RMID into the QM_EVTSEL register, L3 occupancy data 
is reported via the QM_CTR register. The QM_CTR E bit will be set if system software has specified an illegal RMID or an undefined or unsupported EvtID in QM_EVTSEL. If the E bit is set, the rest of the QM_CTR value should be ignored.
The U bit may be set on any QM_CTR read. Subsequent reads issued to the same RMID and EvtID 
may have the U bit cleared. The U bit is set when the monitoring hardware does not have an accurate count for the selected event.
19.3.3  Monitoring L3 Memory Bandwidth (MBM)
The L3 MB) mechanism counts requests made by the L3 cache to the lower-level caches and memory 
(not including I/O). Processors supporting L3 memory bandwidth monitoring are identified by Fn0000_000F_EDX_x1 bit 1 [L3BWMonEvt0] and bit 2 [L3BWMonEvt1] being set. The corresponding Event IDs are EvtID=2 and EvtID=3 respectively.
By default, L3BWMonEvt0 (EvtID 2) tracks total L3 memory bandwidth and L3BWMonEvt1 (EvtId 
3) tracks local L3 memory bandwidth.  If Bandwidth Monitoring Event Configuration (BMEC) is not implemented, the types of L3 transactions counted for EvtID2 and EvtID3 are fixed. See Section 19.3.3.1. However, if BMEC is supported, the type of bandwidth transactions tracked by these events is configurable. See Section 19.3.3.2.
If Assignable Bandwidth Monitoring Counters (ABMC) are implemented, software can specify 
which RMIDs are tracked by the implemented MBM hardware counters. See Section 19.3.3.3.
System software reads MBM bandwidth counters using the QM_EVTSEL and QM_CTR registers as 
For all bandwidth monitoring modes, the value returned in QM_CTR must be multiplied by the 
scaling factor, CPUID Fn0000_000F_EBX_x1[ScalingFactor](bits 31:0), to obtain the number of bytes used by the selected bandwidth source. 
To obtain a bandwidth, software should read the Time Stamp Counter (TSC) and the L3 Cache 
Bandwidth count, wait some period of time, and then read the TSC and the L3 Cache Bandwidth count again. To obtain the rate, software should then divide the difference between the count values by the sampling period.
In PQOS Version 2.0 or higher, the MBM hardware will set the U bit on the first QM_CTR read 
when it begins tracking an RMID that it was not previously tracking. The U bit will be zero for all subsequent reads from that RMID while it is still tracked by the hardware. Therefore, a QM_CTR 
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read with the U bit set when that RMID is in use by a processor can be considered 0 when calculating 
the difference with a subsequent read. The U bit will not be set when a counter rolls over. For these implementations, if the U bit is clear on QM_CTR read for a given RMID and event, the MBM hardware has been counting the event for that RMID continuously without interruption since the previous QM_CTR read for that RMID and that event.
A given implementation may have insufficient hardware to simultaneously track the bandwidth for all 
RMID values that the hardware supports. If an attempt is made to read a Bandwidth Count for an RMID that has been impacted by these hardware limitations, the U bit of the QM_CTR will be set when the counter is read. Subsequent QM_CTR reads for that RMID and Event may return a value with the U bit clear. Potential causes of the U bit being set include (but are not limited to):
•RMID is not currently tracked by the hardware.
•RMID was not tracked by the hardware at some time since it was last read.
•RMID has not been read since it started being tracked by the hardware.
For bandwidth monitoring events which continually increment the counter, when the maximum count 
is reached the counter will roll over and continue counting. It is the software’s responsibility to read the count often enough to avoid having the count roll over twice between reads. The initial counter size is 24 bits and retrieving the value at 1Hz or faster is sufficient to ensure at most one rollover per sampling period.
19.3.3.1  Legacy L3 Cache Bandwidth Monitoring
In early implementations where BMEC is not supported, the types of L3 transactions counted by the 
hardware for EvtID 2  and EvtID 3 are fixed. EvtID 2 tracks total L3 memory bandwidth and EvtID 3 tracks local L3 memory bandwidth. The precise transactions counted by each EvtID depends on the PQOS version. Table 19 -8specifies which transactions are counted by a given EvtID for implementations that do 
not support BMEC. These implementations are identified by the PQOS Version as determined by the Family/Model of the product (see Table 19 -2 on page 686).
System software reads the total and local bandwidth using the QM_EVTSEL and QM_CTR registers. 
The bandwidth metric can be read by setting the following fields in QM_EVTSEL: [ExtendedEvtID]=0, [EvtID]={2,3}, and setting [RMID] to the desired RMID. Reading QM_CTR will then return the contents of the specified event. The E bit will be set if an illegal RMID was specified in QM_EVTSEL.Table 19-8. Transaction Types and EvtIDs
Transaction Type V1.0 EvtIDs V2.0 EvtIDs
Read to Local NUMA Domain 2,3 2,3
Read to Non-Local NUMA Domain 2 2
Non-Temporal Write to Local NUMA Domain N/A 2,3
Non-Temporal Write to Non-Local NUMA Domain N/A 2
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19.3.3.2  Bandwidth Monitoring Event Configuration (BMEC)
The BMEC feature allows software to configure the specific types of L3 transactions that are counted 
for L3 bandwidth monitoring. 
The BMEC feature implements a set of n MSRs (QOS_EVT_CFG_n) which specify the transaction 
types to be counted for each L3 bandwidth monitoring event. QOS_EVT_CFG_n configures the 
L3CacheBwMonEvt<n> encoding of QM_EVTSEL.EvtID. For example, L3BWMonEVT1 (corresponding to EvtID=3) may be configured using the QOS_EVT_CFG_1 register. The format of the QOS_EVT_CFG_n MSRs is shown in Figure 19 -4 on page 697.
Table 19 -9 summarizes the BMEC Events and their associated names, EvtIDs, configuration MSRs, 
and default settings.
Detecting Support for BMEC
Support for BMEC is indicated by CPUID Fn8000_0020_EBX_x0[BMEC] (bit 3) =1.
The number of BMEC configuration registers and the types of transactions that can be counted are 
implementation dependent and identified by CPUID. 
•CPUID Fn8000_0020_EBX_x3[EVT_NUM](bits 7:0) identifies the number of 
QOS_EVT_CFG_n registers available for BMEC use.
•CPUID Fn8000_0020_ECX_x3 identifies the types of L3 transactions that can be counted. 
For implementations that support at least two BMEC configuration registers (EVT_NUM >= 2), 
QOS_EVT_CFG_0 is reset to a value such that L3CacheBwMonEvt0 reports Total L3 System Memory Bandwidth and QOS_EVT_CFG_1 is reset to a value such that L3CacheBwMonEvt1 reports L3 System Memory Bandwidth to the Local NUMA domain. See Figure 19 -4 for the specific 
reset values.
BMEC MSRs
The BMEC feature implements a set of n configuration registers, QOS_EVT_CFG_n, where <n> is 
the BMEC event number (EvtID). The BMEC configuration registers are used to specify the Bandwidth Types to be counted for each BMEC EvtID. The MSR address of QOS_EVT_CFG_n is C000_0400h + n. 
The BMEC configuration registers contain a bit for each Bandwidth (BW) Type that can be used to 
configure the BMEC EvtID (see Figure 19 -4). The Bandwidth Types that can be tracked are 
implementation dependent and enumerated by CPUID Fn8000_0020_ECX_x3. Bit locations that are Table 19 -9. BMEC Events and Corresponding Attributes
BMEC event        BMEC name EvtID Configuration MSR Default (reset) Configuration
L3BWMonEVT0 L3BW Total 2QOS_EVT_CFG_0
MSR C000_0400hTracks Total L3 Bandwidth
L3BWMonEVT1 L3BWLocal 3QOS_EVT_CFG_1
MSR C000_0401hTracks Local L3 Bandwidth
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0 in the CPUID field indicate that the corresponding bit positions in QOS_EVT_CFG_n are reserved 
and MBZ.
 
Notes: 
   QOS_EVT_CFG_0 is reset to a value such that L3CacheBwMonEvt0 (EvtID=2) reports Total L3 memory bandwidth.   QOS_EVT_CFG_1 is reset to a value such that L3CacheBwMonEvt1 (EvtID=3) reports Local L3 memory bandwidth.
Figure 19-4. QOS_EVT_CFG_n
The fields in the QOS_EVT_CFG_n registers are further described below:
• BwType (Bandwidth Types) – bits 6:0, read/write. This field is a bit map specifying the types of 
L3 bandwidth events to be tracked. The Bandwidth Types that can be tracked are implementation

and MBZ.
 
Notes: 
L3 bandwidth events to be tracked. The Bandwidth Types that can be tracked are implementation 
dependent and software must use CPUID Fn8000_0020_ECX_x3 to determine if a particular Bandwidth Type is supported. Bit locations that are 0 in the CPUID field indicate that the corre -
sponding bit positions in QOS_EVT_CFG_n are reserved and MBZ.
19.3.3.3  Assignable Bandwidth Monitoring (ABMC)
The ABMC feature implements a set of n counters to monitor L3 bandwidth in the QOS Domain. 
Each of these counters can be assigned by system software to a particular source RMID (or COS, if 
supported) to track the memory bandwidth used by that source.
ABMC gives system software full control over the bandwidth monitoring resources in the QOS 
Domain. When enabled, the bandwidth monitoring hardware will only track memory bandwidth used by the sources and Bandwidth Types configured through the L3_QOS_ABMC_CFG_n MSRs. Bandwidth data may still be accessed by specifying an RMID and EvtID, but may also be accessed by specifying an ABMC CtrId. (See “Reading the ABMC Counters” on page 701 for more details)
Detecting Support for ABMC
Support for ABMC is identified by CPUID Fn8000_0020_EBX_x0[ABMC] (bit 5) being set. If 63 7 6 0
ReservedBW Types (as 
defined below)
type
63:7 – Reserved MBZ
6 VictimBW Dirty victim writes to all types of memory RW
5 RmtSlowFill Reads issued to remote memory the system identi -
fies as “Slow Memory”RW
4 LclSlowFill Reads issued to local memory the system identi -
3 RmtNTWr Non-temporal writes issued to remote memory RW
2 LclNTWr Non-temporal writes issued to local memory RW
1 RmtFill Reads issued to remote DRAM memory RW
0 LclFill Reads issued to local DRAM memory RW
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ABMC is supported, the feature’s attributes and capabilities are enumerated by CPUID 
Fn8000_0020_x5 as detailed in Appendix E of APM volume 3, and summarized below:
•EAX returns the size of the assignable counters and the presence of a counter overflow bit.
•EBX returns the number of ABMC counters supported.
•ECX identifies the capability to associate individual assignable counters with a COS (Class of 
Service) rather than an RMID.
The types of L3 transactions that ABMC can track are configurable and identified by CPUID 
Fn8000_0020_ECX_x3. See “QOS_EVT_CFG_n” on page 697 for a list of transaction types and corresponding encodings.
AMBC MSRs
The ABMC feature implements a pair of MSRs, L3_QOS_ABMC_CFG (MSR C000_03FDh) and L3_QOS_ABMC_DSC (MSR C000_3FEh). Each logical processor implements a separate copy of these registers. 
Attempts to read or write these MSRs when ABMC is not enabled will result in a #GP(0) exception.Individual assignable bandwidth counters are configured by writing to L3_QOS_ABMC_CFG MSR 
and specifying the Counter ID, Bandwidth Source, and Bandwidth Types.
Reading L3_QOS_ABMC_DSC returns the configuration of the counter specified by 
L3_QOS_ABMC_CFG [CtrID].
Figure 19-5. L3_QOS_ABMC_CFG63 62 6 1 53 52 48 47 46 4 4 4 3 32CfgEn
CtrEnReserved CtrID
IsCOSReserved BwSrc (RMID or COS)
31 0
BwType
TypeReset Value
63 CfgEn Configuration Enable R/W 0
62 CtrEn Counter Enable R/W 0
61:53 – Reserved MBZ 0
52:48 CtrID Counter Identifier R/W 0
47 IsCOS BwSrc field is a COS (not an RMID) R/W 0
46:44 – Reserved MBZ 0
43:32 BwSrc Bandwidth Source (RMID or COS) R/W 0
31:0 BwType Bandwidth types to track for this counter R/WSee BwType below
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The fields shown in Figure 19 -5 are further described below:
•CfgEn (Configuration Enable) – bit 63. When set, indicates a WRMSR to this register should 
configure the assignable counter selected by the CtrID field. If this bit is not set on a write, no configuration is performed.
•CtrEn (Counter Enable) – bit 62. When set, the selected counter will begin tracking the bandwidth types specified in the BwType field. 
•CtrID (Counter ID) – bits 52:48. Identifies the assignable counter to configure. 
•IsCOS (BwSrc is a COS) – bit 47. When set, indicates that the BwSrc field is a COS (Class of Service) as opposed to an RMID.
•BwSrc (Bandwidth Source) – bits 43:32. Specifies an RMID (or COS if IsCOS=1) to monitor with this counter. The size of this field is LOG2(CPUID Fn0000_000F_EBX_x0[MAX_RMID]+1).
•BwType (Bandwidth Types – bits 31:0. This field is a bit map specifying the types of L3 bandwidth events to be tracked by this assignable counter. This field uses the Bandwidth Type encodings used in CPUID Fn8000_0020_ECX_x3[BandwidthTypes]. Upon reset, the bit for each supported Bandwidth Type enumerated by the above CPUID function is set to 1.
Figure 19-6. L3_QOS_ABMC_DSC
The fields shown in Figure 19 -6 are further described below:
•CfgErr (Configuration Error) – bit 63. When set, indicates that the last configuration specified in L3_QOS_ABMC_CFG was invalid and consequently the specified counter was not enabled.63 62 6 1 53 52 48 47 46 4 4 4 3 32CfgErr
IsCOSReserved Bw Src (RMID or COS)
31 0
BwType
63 CfgErr Configuration Error R 0
62 CtrEn Counter Enable R 0
61:53 – Reserved R 0
52:48 CtrID Counter Identifier R 0
47 IsCOS BwSrc field is a COS (not an RMID) R 0
46:44 – Reserved R 0
43:32 BwSrc Bandwidth Source (RMID or COS) R 0
31:0 BwType Bandwidth types to track for this counter RSee BwType below
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•CtrEn (Counter Enable) – bit 62. When set, indicates the selected counter is actively tracking the 
bandwidth types specified in the BwType field. When cleared, the selected counter is also zero.
•CtrID (Counter ID) – bits 52:48. Identifies the assignable counter for which configuration is reported. 
•BwSrc (Bandwidth Source) – bits 43:32. Returns the RMID (or COS if IsCOS=1) being monitored with this counter. The size of this field is LOG2(CPUID Fn0000_000F_EBX_x0[MAX_RMID]+1).
•BwType (Bandwidth Types – bits 31:0. This field is a bit map which identifies the types of L3 bandwidth events to be tracked by the specified counter. The BwType field uses the same event encodings used in CPUID Fn8000_0020_ECX_x3[BandwidthMonitoringEvents].
L3 _QOS_EXT_CFG MSR
If support for ABMC is identified (CPUID Fn8000_0020_EBX_x0[ABMC](bit 5)=1), then the 
L3_QOS_EXT_CFG MSR, (MSR address C000_03FFh) is also supported. The format of this register is shown in Figure 19 -7.
Figure 19-7. L3_QOS_EXT_CFG
Enabling ABMC
ABMC is enabled by setting L3_QOS_EXT_CFG.ABMC_En=1 (see Figure 19 -7). When the state of 
ABMC_En is changed, it must be changed to the updated value on all logical processors in the QOS Domain.
Upon transitions of the ABMC_En the following actions take place:•All ABMC assignable bandwidth counters are reset to 0.
•The L3 default mode bandwidth counters are reset to 0.
•The L3_QOS_ABMC_CFG MSR is reset to 0.63 2 1 0
Reserved
SDCIAE_En
ABMC_En
Type
63:2 – Reserved RAZ
1 SDCIAE_En SDCI Allocation Enforcement Enable R/W
0 ABMC_En ABMC Enable R/W
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Configuring ABMC
After enabling ABMC, system software can configure a counter by writing the QOS_ABMC_CFG 
register and specifying the Counter ID, Bandwidth Source, and Bandwidth Types fields and setting the Configuration Enable bit. The value of the specified Counter ID is cleared to zero upon configuration. Writing QOS_ABMC_CFG with CfgEn clear will not change the configuration of the counter. Reading QOS_ABMC_CFG will return the last value written (see Figure 19 -5 on page 698).
Each logical processor has a separate copy of QOS_ABMC_CFG. The contents of this register are not persistent through PC6 events and will be reset in that case. Attempts to access L3_QOS_ABMC_CFG when ABMC is not enabled (L3_QOS_EXT_CFG.ABMC_En == 0) result in a #GP(0) exception. 
Reading L3_QOS_ABMC_DSC will return the configuration of the counter specified by 
QOS_ABMC_CFG[CtrID] (see Figure 19 -6 on page 699).
Reading the ABMC Counters
System software reads the assignable counters using the QM_EVTSEL and QM_CTR registers.
The contents of a specific counter can be read by setting the following fields in QM_EVTSEL: 
[ExtendedEvtID]=1, [EvtID]=L3CacheABMC and setting [RMID] to the desired counter ID. Reading QM_CTR will then return the contents of the specified counter. The E bit will be set if the counter configuration was invalid, or if an invalid counter ID was set in the QM_EVTSEL[RMID] field.
Alternatively, the contents of a counter may be read by specifying an RMID and setting the [EvtID] to 
L3BWMonEvt n where n= {0,1}. If an assignable bandwidth counter is monitoring that RMID with a

L3BWMonEvt n where n= {0,1}. If an assignable bandwidth counter is monitoring that RMID with a 
BwType bitmask that matches a QOS_EVT_CFG_n, that counter’s value will be returned when reading QM_CTR. However, if multiple counters have the same configuration, QM_CTR will return the value of the counter with the lowest CtrID.
The value returned in QM_CTR must be multiplied by the scaling factor, 
Fn0000_000F_EBX_x1[ScalingFactor](31:0), to obtain the number of bytes used by the selected bandwidth source. 
19.4 PQOS Enforcement (PQE)
The PQE feature provides the ability to set and enforce limits on the usage of shared resources by a thread or a group of threads. For example, PQE can be used to specify the amount of L3 cache that is available to a thread.
Enforcement is accomplished by assigning a numerical Class of Service (COS) to a thread and 
specifying allocations or limits on the usage of a shared resource for that COS. The current COS for a given processor is specified in PQR_ASSOC register, MSR C8Fh (see Figure 19 -1 on page 690). If 
multiple threads share the same COS, those threads will competitively share the controlled resource.
PQE implements several sub-features which are described in detail in the following sections:
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•CAT – L3 Cache allocation.
•CDP – L3 Cache allocation, based on code vs. data access.
•L3 bandwidth allocation.
•L3 slow memory bandwidth allocation.
•SDCI allocation enforcement.
For each resource controlled by PQE, a set of Model-Specific Registers is defined which system 
software can use to specify the allocation limits for each COS.
19.4.1  Identifying support for PQE 
Support for PQE is identified by CPUID Fn0000_0007_EBX_x0[PQE]=1. If PQE is supported, the 
set of resources for which limits can be set and enforced is reported by CPUID function Fn0000_0010. Each supported resource is identified by a bit in EBX, as shown in Table 19 -10.
Once support for a PQE resource has been determined as above, CPUID Fn0000_0010 with ECX = {resource bit number} may be used to determine the PQE enforcement capabilities for that resource. For example, Fn0000_00010_x1 (ECX=1) returns the following information about the L3 Cache Monitoring feature:
•EAX identifies CBM_LEN, the length of the L3 cache capacity bitmasks (CBMs).
•EBX identifies the L3 Cache Allocation Sharing Mask.
•ECX identifies the presence of specific L3 Cache Enforcement features, such as Code-Data 
Prioritization (CDP) support.
•EDX identifies COS_MAX, the maximum COS supported for L3 Cache Allocation Enforcement. 
A complete description of these CPUID functions can be found in Appendix E of APM volume 3.
19.4.2  L3 Cache Allocation Enforcement (CAT)
The L3 CAT feature enables system software to limit the fractional portion of the L3 cache used by 
threads for each COS.
Limits for L3 cache allocation are specified by a set of L3_MASK_n registers, where n is the COS 
associated with that MSR. There is one L3_MASK register for each COS implemented for the L3 
cache resource. This set of registers starts at MSR address C90h and continues through address C90h + (n-1). The maximum COS value supported by the L3 resource is reported by CPUID Fn0000_0010_EDX_x1[MAX_COS](bits 15:0). COS values are zero-based, thus the number of Table 19-10. CPUID Fn0000_00010_EDX_x0 PQE Resources
EDX Bits Name Description
1 L3Alloc L3 Cache Allocation Enforcement
31:2 – Reserved 
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classes supported is (MAX_COS+1).
Each of the L3_MASK_n registers contain a bitmask where each bit represents a fixed portion of the 
L3 cache into which COS <n> is allowed to allocate. The length of the bit mask is implementation-dependent and returned by CPUID Fn0000_0010_EAX_x1[CBM_LEN](bits 4:0). The length is zero based, thus CBM_LEN=15 would indicate that the cache is partitioned into 16 sections for L3 allocation purposes.
Once the L3_MASK_n registers are configured with the desired L3 cache allocations, threads can be 
assigned a COS using the PQR_ASSOC register as described in Section 19.3.1 “PQM MSRs” on 
page 689.
19.4.2.1  L3_MASK_n MSRs
The format of the L3_MASK_n registers is shown in Figure 19 -8 below.
Figure 19-8. L3_MASK_n
19.4.2.2  Using L3 CAT
System software sets bits in the L3_MASK_n registers to indicate the portions of the L3 cache that may be used by a given COS <n>. For example, if CBM_LEN for a given implementation is 15, then each set bit in the L3_MASK_n represents 1/16 of the cache which may be used by processors running with COS = <n>. 
If two or more different Classes of Service have set bits in the same position in their respective 
L3_MASK_n registers, that portion of the cache is competitively shared by logical processors running with those COS values.
After configuring the L3_Mask_n registers with the desired L3 allocations, system software can set 
PQR_ASSOC[COS] to specify the Class of Service for the currently active thread. If the value written to PQR_ASSOC[COS] exceeds CPUID Fn0000_00010_EDX_x1[MAX_COS], a #GP(0) exception is signaled.
Some products may implement L3 Cache Allocation Enforcement by allocating some number of 
ways of the L3 cache for each set bit in the L3_MASK register, but this will not necessarily be true for all implementations and software should not rely on that interpretation. However, because this is one possible implementation, it is possible that use of CAT will reduce the effective associativity available to processes running using an L3_MASK which does not have all the bits set. 63 CMB_LEN+1 CMB_LEN 0
Reserved MASK
Type
63:CBM_LEN+1 – Reserved, read as zero RAZ
CBM_LEN:0 MASK L3 Cache Allocation Mask R/W
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The bits which are set in the various L3_MASK_n registers do not have to be contiguous and may 
overlap in any desired combination. If an L3_MASK_n register is programmed with all bits clear, that COS will be prevented from allocating any lines in the L3 cache. At reset, the L3_MASK register bitmap bits are all set, allowing all processors to use the entire L3 cache accessible to them.
The L3 Cache Allocation mechanism controls only the allocations into the L3 cache. Once a line is 
installed into the cache, any COS is allowed to “hit” on that line.
When a given cache line is accessed by processors running with different COS values in the same 
QOS Domain, only a single copy of the line will be allocated in the shared cache at a given time. Depending on the access pattern, this line may be installed in the L3 cache partition belonging to either COS. Depending on subsequent access patterns, that cache line may later be evicted and then installed into the partition belonging to the other COS. Software should not assume that the line will always be associated with the last COS that accessed the line.
Depending on the implementation, some portions of the L3 Cache may be shared by other system 
functions or used for some other purpose not under the control of the PQOS feature set. The L3 Cache Allocation Sharing Mask returned by CPUID Fn0000_0010_EBX_x1[L3ShareAllocMask] is a bitmask that represents portions of the L3 that may be shared by those functions. When software sets a bit in an L3_MASK_n register at the same position as a bit in the L3ShareAllocMask, processors executing with the corresponding COS will competitively share that portion of the cache with the other function. An L3ShareAllocMask with all bits cleared indicates that no other entity in the system is competing with the processors for use of the L3 cache.
19.4.3  Code and Data Prioritization (CDP)
The L3 CDP feature is an extension of the previously-described L3 CAT feature (See Section 19.4.2). 
When enabled, CDP allows system software to specify different L3 cache allocations for instructions versus data.
19.4.3.1  Detecting Support for CDP
Presence of the L3 CDP feature is indicated by CPUID Fn0000_0010_ECX_x1[CDP](bit 2) being set. The L3 CAT information returned by Fn0000_0010_{EAX, EBX, EDX}_x1 also applies to the L3 CDP feature, except for MAX_COS. When CDP is enabled, the maximum COS value is half the value given by CPUID Fn0000_0010_EDX_x1[MAX_COS] + 1.
19.4.3.2  CDP Model-Specific Registers
If CDP is supported, software can enable the CDP feature by setting the CDP_En bit in L3_QOS_CFG1 (MSR C81h). See Figure 19 -9.
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Figure 19-9. L3_QOS_CFG1
When CDP is enabled, the L3_MASK_n registers operate in pairs, and each pair is associated with a 
single COS. The lower-numbered register in the pair is used to specify the cache allocation mask for data accesses and the upper register of the pair is used to specify the mask for instruction fetches. 
For 
a given COS, the data allocation mask will be specified in MSR C90 + (2*COS) while the instruction 
allocation mask will be specified by MSR C90 + (2*COS+1). See Table 19 -11 below.

For 
Note that enabling CDP reduces the effective number of unique COS values by half. Specifying a 
COS outside of the valid range will result in undefined behavior.
The interpretation of the L3_MASK registers is the same with CAT; the difference is that with CDP 
enabled, the mask to be applied is selected based on whether the line is accessed as an instruction or data fetch. Similar to the behavior with CDP disabled, if a line is accessed as both code and data, then the line may be allocated using either mask register and be counted against that allocation limit. Also similar to the case with CDP disabled, software may not assume that cache lines will necessarily be associated with the code or data mask register with which they were most recently accessed.
Software should observe the following sequence when enabling or disabling CDP mode: 
1. Ensure that all bits of the QOS Allocation mask for each COS (L3_MASK_<COS>[MASK] are
set. 
2. Ensure that the QOS Bandwidth enforcement limit for each COS is set to “No Limit”.
(L3QOS_BW_CONTROL_<COS>[U] = 1) 63 0
Reserved
CDP_En
Type
63:1 – Reserved, read as zero RAZ
0 CDP_En CDP Enable R/W
Table 19-11. CAT vs. CDP L3 Mask Register Usage
Mask Register MSR Address CAT Usage CDP Usage
L3_Mask_0 C90h COS 0
COS 0data
L3_Mask_1 C91h COS 1 code
L3_Mask_2 C92h COS 2
COS 1data
L3_Mask_3 C93h COS 3 code
. . . . .
. . . . .
L3_Mask_n C90+n COS n
COS n/2data
L3_Mask_n+1 C90+n+1 COS n+1 code
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3. Ensure that all logical processors in the QOS Domain are associated (PQR_ASSOC[COS] with
valid COS numbers for when CDP is enabled. Specifically, the COS number must be less than
half of COS_MAX. Using COS numbers outside that range will result in undefined behavior.
4. Write the desired state of CDP_En to the L3_QOS_CFG1 MSR on each logical processor in the
QOS Domain. In some implementations, a single L3_QOS_CFG1 MSR may be shared betweenmultiple logical processors.
For optimal QOS behavior in the new operating mode, software should flush the caches in the QOS 
Domain once the new configuration has been enabled to clear out any residual allocations from the previous configuration. 
19.4.4  AMD Bandwidth Enforcement
The AMD Bandwidth Enforcement feature provides a set of sub-features to control threads which 
may be over-utilizing bandwidth relative to their priority with respect to other workloads co-located in the QOS Domain. When support for PQE is identified (see Section 19.4.1 “Identifying support for PQE” on page 702) CPUID Fn8000_0008_EBX_x0[BE](bit 6) returns an indication that AMD Bandwidth Enforcement is supported.
The sub-features supported under AMD Bandwidth Enforcement are further enumerated by CPUID 
function 0x8000_0020_EBX_x0. The supported sub-features include:
•L3 BE - L3 External Bandwidth Allocation Enforcement (see Section 19.4.5 “L3 External 
Bandwidth Enforcement (L3BE)” on page 706)
•L3 SMBE - L3 External Slow Memory Bandwidth Allocation Enforcement (see Section 19.4.6 “L3 Slow Memory Bandwidth Enforcement (L3SMBE)” on page 708)
•L3 SDCIAE – L3 Smart Data Cache Injection Allocation Enforcement (see Section 19.4.7 “L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE)” on page 709)
19.4.5  L3 External Bandwidth Enforcement (L3BE)
L3BE allows system software to specify memory bandwidth limits used by a thread (or a group of 
threads) assigned to a given Class of Service.
Support for L3BE is indicated by CPUID Fn8000_0020_EBX_x0[L3BE](bit 1)=1. If L3BE is 
supported, the feature’s attributes and capabilities are enumerated by ID Fn8000_0020_x1 as summarized below:
•EAX[31:0](BW_LEN) returns the size of the bandwidth specifier field in the 
L3QOS_BW_Control_n MSRs.
•EDX[31:0](COS_MAX) returns the maximum COS number supported by the L3BE feature.
19.4.5.1  L3BE MSRs
Bandwidth limits are specified using the L3QOS_BW_CONTROL_n, MSRs, where <n> is the 
corresponding COS number. This set of registers starts at MSR address C000_0200h and continues through C000_0200h + n. The format of the L3QOS_BW_CONTROL_n registers is shown in Figure 
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19-10.
.
Figure 19-10. L3QOS_BW_CONTROL_n
The fields within a L3QOS_BW_CONTROL_n register are:
•U (Unlimited) – bit <BW_LEN>. When set, indicates that threads belonging to this COS are 
unlimited in bandwidth and the contents of the BW field are ignored. At reset, the U bit for all L3QOS_BW_CONTROL_n MSRs are set.
•BW (Bandwidth) – bits BW_LEN-1:0. Specifies a limit on the total L3 external bandwidth, expressed in 1/8 GB/s increments, for all threads running under COS <n>.
19.4.5.2  Using L3BE
System software can control usage of L3 external bandwidth using the L3QOS_BW_CONTROL 
MSRs to specify bandwidth limits for a given COS. There is one L3QOS_BW_CONTROL for each COS as identified by CPUID Fn8000_0020_EDX_x1[COS_MAX](bits 31:0).
At reset, the “U” (Unlimited) bit of all L3QOS_BW_CONTROL registers is set, allowing maximum 
bandwidth usage by all processors.
The value programmed in the L3QOS_BW_CONTROL_n register specifies a limit on the total L3 
external bandwidth consumed by all threads running with COS=<n> within the L3 cache QOS Domain. Software may program a bandwidth limit for COS <n> in L3QOS_BW_CONTROL[BW]_n, or it may specify “no limit” by setting the “U” bit. Unlike cache allocation (which specifies a fraction of the cache), this limit is not a relative bandwidth, but an absolute number expressed in 1/8 GB/s increments. The format of the L3QOS_BW_CONTROL_n registers are described in Figure 19 -10 on page 707.
Bandwidth limits are upper bounds on the bandwidth the processors in a given domain and COS may consume, but do not ensure that the specified bandwidth will necessarily be available to those processors. Cases where the processors in a given COS may not be able to reach their allocated bandwidth include (but are not limited to): 
1. The specified limit may be greater than the maximum system bandwidth.63 BW_LEN BW_LEN-1 0
Reserved U BW
Type
63:BW_LEN+1 – Reserved, read as zero RAZ
BW-LEN U Unlimited bandwidth R/W
BW-LEN-1:0 BW L3 cache external bandwidth limit R/W
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2. The sum of the limits applied to all classes of service in the domain may exceed the maximum
bandwidth the system can deliver to that COS domain. 
3. Multiple COS domains which share the same memory channels may demand more total
bandwidth than the shared memory can supply. 
4. I/O or other system entities may consume a large fraction of system bandwidth and result in less
bandwidth being available to the various processor COS domains. 
5. Large amounts of write traffic may affect the memory system’s ability to deliver read bandwidth. 
In the case where total available L3 external bandwidth has been over-subscribed (that is, not all 
classes of service can reach their bandwidth limits), the hardware makes no attempt to allocate the available L3 bandwidth in proportion to the limits specified for each COS domain or the limits specified for each COS within a given domain. That is (in case 2 above), if COS x has limit A, and 
COS y has limit 2*A, and the total bandwidth which the system can deliver to that COS is only 2*A, 
the system will only limit COS x to A; it will not attempt to give (2/3)*A to COS x and (4/3)*A to 
COS y (maintaining the ratio of their limits).
19.4.5.3  CDP Interaction with L3BE
When CDP is enabled, the mapping of COS to its associated L3QOS_BW_CONTROL register is changed.  For a given COS, the bandwidth limits are specified by MSR  C000_0200h + (2*COS).  For example, if CDP is enabled, the L3 bandwidth limit for threads associated with COS 3 are specified in L3QOS_BW_CONTROL_6.
Note that enabling CDP reduces the effective number of unique COS values by half.  Specifying a 
19.4.6  L3 Slow Memory Bandwidth Enforcement (L3SMBE)
L3SMBE allows the system software to limit bandwidth to slow memory available to threads inside 
the QOS Domain. Support for L3SMBE is indicated by CPUID Fn8000_0020_EBX_x0[L3SMBE](bit 2)=1. If L3SMBE is supported, the feature’s attributes and capabilities are enumerated by ID Fn8000_0020_x2 as summarized below:
L3QOS_SMBW_Control_n MSRs.
•EDX[31:0](COS_MAX) returns the maximum COS number for the L3SMBE feature.
19.4.6.1  L3SMBE MSRs
Similar to the L3BE feature (see Section 19.4.5), L3SMBE bandwidth limits are specified in the 
L3QOS_SMBW_CONTROL_n, MSRs, where <n> is the corresponding COS number. This set of registers starts at MSR address C000_0280h and continues through C000_0280h + n. The format of the L3QOS_SMBW_CONTROL_n registers is shown in Figure 19 -11.
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Figure 19-11. L3QOS_SMBW_CONTROL_n

The fields within an L3QOS_SMBW_CONTROL_n register are:
•U (Unlimited) – bit <SMBW_LEN>. When set, indicates that threads belonging to this COS are 
unlimited in bandwidth and the contents of the SMBW field are ignored. At reset, the U bit for all L3QOS_SMBW_CONTROL_n MSRs are set.
•SMBW (Bandwidth) – bits SMBW_LEN-131. Specifies a limit on the slow memory bandwidth, expressed in 1/8 GB/s increments, for all threads running under COS <n>.
19.4.6.2  Using L3SMBE
System software can control usage of L3 slow memory bandwidth using the 
L3QOS_SMBW_CONTROL MSRs to specify bandwidth limits for a given COS. There is one such register for each COS as identified by CPUID Fn8000_0020_EDX_x2[COS_MAX](bits 31:0). L3SMBE usage details and operation are the same as L3BE, except that it controls a subset of bandwidth resources related to slow memory. See Section 19.4.5.2 “Using L3BE” on page 707 for usage notes.
19.4.6.3  CDP Interaction with L3SMBE
Similar to the L3BE feature, the mapping of a COS to its associated L3QOS_SMBW_CONTROL 
register is changed if CDP is enabled.  For a given COS, the slow memory bandwidth limits are specified by MSR  C000_0280h + (2*COS). For example, if CDP is enabled, the slow memory bandwidth limit for threads associated with COS 3 are specified in L3QOS_SMBW_CONTROL_6. Note that enabling CDP reduces the effective number of unique COS values by half. Specifying a COS outside of the valid range will result in undefined behavior.
19.4.7  L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE)
Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O 
devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data.
The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to limit the 63 SMBW_LEN SMBW_LEN-1 0
Reserved U SMBW
Type
63:SMBW_LEN+1 – Reserved, read as zero RAZ
SMBW_LEN U Unlimited bandwidth R/W
SWBW_LEN-1:0 SMBW L3 cache slow memory bandwidth limit R/W
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portion of the L3 cache used for SDCI. 
When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by 
the highest-supported L3_MASK_n register as reported by CPUID Fn0000_0010_EDX_x1[MAX_COS](bits 15:0). For example, if MAX_COS=15, SDCI lines will be allocated into the L3 cache partitions determined by the bitmask in the L3_MASK_15 register.
Support for SDCIAE is indicated by CPUID Fn8000_0020_EBX_x0[SDCIAE](bit 6)=1. SDCIAE is enabled by setting L3_QOS_EXT_CFG.SDCIAE_En=1 (see Figure 19 -7 on page 700). 
When the state of SDCIAE_En is changed, it must be changed to the updated value on all logical 
processors in the QOS Domain.
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Appendix A MSR Cross-Reference
This appendix lists the MSRs that are defined in the AMD64 architecture. The AMD64 architecture 
supports some of the same MSRs as previous versions of the x86 architecture and implementations thereof. Where possible, the AMD64 architecture supports the same MSRs, for the same functions, as these previous architectures and implementations.
The first section lists the MSRs according to their MSR address, and it gives a cross reference for 
additional information. The remaining sections list the MSRs by their functional group. Those sections also give a brief description of the register and specify the register reset value.
Some MSRs are implementation-specific For information about these MSRs, see the documentation 
for specific implementations of the AMD64 architecture. 
A.1 MSR Cross-Reference by MSR Address
Table A -1 lists the MSRs in the AMD64 architecture in order of MSR address.
Table A -1. MSRs of the AMD64 Architecture
MSR Address MSR NameFunctional 
GroupCross-Reference
0010h TSC Performance “Time-Stamp Counter” on page 422
001Bh APIC_BASE System Software “Local APIC Enable” on page 622
0048h SPEC_CTRLSpeculation 
Control“Speculation Control MSRs” on page 66 
0049h PRED_CMDSpeculation Control“Speculation Control MSRs” on page 66 
00E7h MPERF Performance“Determining Processor Effective Frequency” on page 660
00E8h APERF Performance“Determining Processor Effective Frequency” on page 660
00FEh MTRRcap Memory Typing “Identifying MTRR Features” on page 223
0174h SYSENTER_CS
System Software“SYSENTER and SYSEXIT MSRs” on page 1760175h SYSENTER_ESP
0176h SYSENTER_EIP
0179h MCG_CAP
Machine Check“Machine-Check Global-Capabilities Register” 
on page 300
017Ah MCG_STATUS“Machine-Check Global-Status Register” on page 301
017Bh MCG_CTL“Machine-Check Global-Control Register” on page 302
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01D9h DebugCtl Software Debug “Debug-Control MSR (DebugCtl)” on page 396
01DBh LastBranchFromIP
Software Debug“Control-Transfer Recording MSRs” on 
page 39801DCh LastBranchToIP
01DDh LastIntFromIP
01DEh LastIntToIP
0200h MTRRphysBase0
Memory Typing “Variable-Range MTRRs” on page 2200201h MTRRphysMask0
0202h MTRRphysBase10203h MTRRphysMask10204h MTRRphysBase20205h MTRRphysMask20206h MTRRphysBase30207h MTRRphysMask30208h MTRRphysBase40209h MTRRphysMask4
020Ah MTRRphysBase5
020Bh MTRRphysMask5020Ch MTRRphysBase6
020Dh MTRRphysMask6
020Eh MTRRphysBase7
020Fh MTRRphysMask7
0250h MTRRfix64K_00000
Memory Typing “Fixed-Range MTRRs” on page 2180258h MTRRfix16K_800000259h MTRRfix16K_A00000268h MTRRfix4K_C00000269h MTRRfix4K_C8000
026Ah MTRRfix4K_D0000
026Bh MTRRfix4K_D8000026Ch MTRRfix4K_E0000
026Dh MTRRfix4K_E8000
026Eh MTRRfix4K_F0000
026Fh MTRRfix4K_F8000
0277h PATMemory Typing“PAT Register” on page 226
02FFh MTRRdefType “Default-Range MTRRs” on page 222Table A -1. MSRs of the AMD64 Architecture (continued)
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0400h MC0_CTL
Machine CheckSee the documentation for particular 
implementations of the architecture. 0404h MC1_CTL
0408h MC2_CTL
040Ch MC3_CTL
0410h MC4_CTL0414h MC5_CTL0401h MC0_STATUS
Machine Check “Machine-Check Status Registers” on page 3070405h MC1_STATUS0409h MC2_STATUS
040Dh MC3_STATUS
0411h MC4_STATUS
0415h MC5_STATUS0402h MC0_ADDR
Machine Check“Machine-Check Address Registers” on 
page 3100406h MC1_ADDR
040Ah MC2_ADDR
040Eh MC3_ADDR
0412h MC4_ADDR
0416h MC5_ADDR0403h MC0_MISC
Machine Check“Machine-Check Miscellaneous-Error 
Information Register 0 (MCi_MISC0)” on page 3100407h MC1_MISC
040Bh MC2_MISC
040Fh MC3_MISC
0413h MC4_MISC
0417h MC5_MISC
06A0h U_CET 
Shadow Stack “Shadow Stack MSRs” on page 72806A2h S_CET 06A4h PL0_SSP 06A5h PL1_SSP06A6h PL2_SSP 06A7h PL3_SSP 06A8h ISST_ADDR Table A -1. MSRs of the AMD64 Architecture (continued)
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0C81h L3_QOS_CFG1 Quality of Service
“Platform Quality of Service (PQOS) 
Extension” on page 6850C8Dh QM_EVTSEL Quality of Service
0C8Eh QM_CTR Quality of Service
0C8Fh PQR_ASSOC Quality of Service
0C90h L3_MASK_0 Quality of Service
0C90+n L3_MASK+n Quality of Service
0DA0h XSS -XSA VES and XSTRORS instructions in APM volume 4
C000_0080h EFER System Software“Extended Feature Enable Register (EFER)” on page 55
C000_0081h STAR System Software
“SYSCALL and SYSRET MSRs” on page 175C000_0082h LSTAR System Software
C000_0083h CSTAR System Software
C000_0084h SF_MASK System Software
C000_00E7h MPerfReadOnly Performance“MPERF Read-only (MperfReadOnly)” on page 662
C000_00E8h APerfReadOnly Performance“APERF Read-only (AperfReadOnly)” on page 662
C000_00E9h IRPerfCount Performance“Instructions Retired Performance counter” on page 420
C000_0100h FS.Base System Software “FS and GS Registers in 64-Bit Mode” on page 80 C000_0101h GS.Base System Software
C000_0102h KernelGSbase System Software “SWAPGS Instruction” on page 176
C000_0103h TSC_AUX System Software “RDTSCP Instruction” on page 179
C000_0104h TSC Ratio SVM “TSC Ratio MSR (C000_0104h)” on page 585
C000_0108h PrefetchControl 
—Controls enabling / disabling hardware prefetchers. See the appropriate BIOS and 
Kernel Developer’s Guide or Processor 
Programming Reference Manual  for details.
C000_010Eh LastBranchStackSelect Software Debug “Last Branch Record Stack” on page 409
C000_010Fh DebugExtnCtl Software Debug“Debug-Extension-Control MSR (DebugExtnCtl)” on page 398
C000_0200h L3QOS_BW_CONTROL_0 Quality of Service
“Platform Quality of Service (PQOS) Extension” on page 685C000_0200h+n L3QOS_BW_CONTROL_n Quality of Service
C000_0280h L3QOS_SMBW_CONTROL_0 Quality of Service
C000_0280h+n L3QOS_SMBW_CONTROL_n Quality of Service

C000_0300h PerfCntrGlobalStatus Performance“Core Performance Counter Status Registers” on page 415Table A -1. MSRs of the AMD64 Architecture (continued)
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C000_0301h PerfCntrGobalCtl Performance“Core Performance Global Control Register” on 
page 415
C000_0302h PerfCntrGlobalStatusClr Performance“Performance Counter Global Status Clear Register” on page 418
C000_0303h PerfCntrGlobalStatusSet Performance“Performance Counter Global Status Set Register” on page 417
C000_03FDh L3_QOS_ABMC_CFG Quality of Service
“Platform Quality of Service (PQOS) Extension” on page 685C000_03FEh L3_QOS_ABMC_DSC Quality of Service
C000_03FEh L3_QOS_EXT_CFG Quality of Service
C000_0400h L3_EVT_CFG_0 Quality of Service
C000_0401h L3_EVT_CFG_1 Quality of Service
C000_0408h MC4_MISC1
Machine Check“Machine-Check Miscellaneous-Error Information Register 0 (MCi_MISC0)” on page 310C000_0409h MC4_MISC2
C000_040Ah MC4_MISC3
C000_0410h MCA_INTR_CFG MCA related interrupt configuration. See the appropriate BIOS and Kernel Developer’s Guide  
or Processor Programming Reference Manual  
C000_2000h + 
i*10hMCA_CTLSee the documentation for particular 
implementations of the architecture. 
C000_2001h + 
i*10hMCA_STATUS “Machine-Check Status Registers” on page 307
C000_2002h + 
i*10hMCA_ADDR“Machine-Check Address Registers” on 
page 310 
C000_2003h + 
i*10hMCA_MISC0“Machine-Check Miscellaneous-Error 
Information Register 0 (MCi_MISC0)” on page 310
C000_2004h + 
i*10hMCA_CONFIG “MCA Configuration Register” on page 314 
C000_2005h + 
i*10hMCA_IPID“MCA IP Identification” on page 316 
C000_2006h + 
i*10hMCA_SYND “MCA Syndrome Register” on page 317 Table A -1. MSRs of the AMD64 Architecture (continued)
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C000_2008h + 
i*10hMCA_DESTAT
Machine Check“MCA Deferred Error Status Register” on 
page 317 
C000_2009h + 
i*10hMCA_DEADDR“MCA Deferred Error Address Register” on page 318 
(C000_200Ah : 
C000_200Dh) 
+ i*10hMCA_MISC[4-1]“MCA Miscellaneous Registers 1 - 4” on page 318 
(C000_200Eh : 
C000_200Fh)+ 
i*10hMCA_SYND[2-1] “MCA Syndrome Registers 1 - 2” on page 318 
C001_0000h PerfEvtSel0
Performance“Core Performance Event-Select Registers” on page 412C001_0001h PerfEvtSel1
C001_0002h PerfEvtSel2C001_0003h PerfEvtSel3C001_0004h PerfCtr0
Performance “Performance Counter MSRs” on page 410C001_0005h PerfCtr1C001_0006h PerfCtr2C001_0007h PerfCtr3
C001_0010h SYSCFG Memory Typing“System Configuration Register (SYSCFG)” on 
page 60
C001_0015h HWCR System Software “Hardware Configuration Register (HWCR)” on page 70
C001_0016h IORRBase0
Memory Typing “IORRs” on page 233C001_0017h IORRMask0
C001_0018h IORRBase1C001_0019h IORRMask1
C001_001Ah TOP_MEMMemory Typing “Top of Memory” on page 235C001_001Dh TOP_MEM2
C001_0030h
Processor_Name_String CPUID NameSee the appropriate BIOS and Kernel 
Developer’s Guide  or Processor Programming 
Reference Manual  for details.C001_0031h
C001_0032hC001_0033hC001_0034hC001_0035h
C001_0056h SMI_Trigger_IO_Cycle SMMSee the appropriate BIOS and Kernel 
Reference Manual  for details.Table A -1. MSRs of the AMD64 Architecture (continued)
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C001_0061h P-State Current Limit
SMM“Hardware Performance Monitoring and 
Control” on page 657C001_0062h P-State Control
C001_0063h P-State StatusC001_0074h CPU_Watchdog_Timer Machine Check “CPU Watchdog Timer Register” on page 303
C001_0104h TSC Ratio SVM “TSC Ratio MSR (C000_0104h)” on page 585
C001_0111h SMBASE 
SMM“SMBASE Register” on page 325
C001_0112h SMM_ADDR“SMRAM Protected Areas” on page 331C001_0113h SMM_MASK C001_0114h VM_CR SVM “SVM Related MSRs” on page 583
C001_0115h IGNNE SVM “SVM Related MSRs” on page 583
C001_0116h SMM_CTL SVM “SVM Related MSRs” on page 583
C001_0117h VM_HSA VE_PA SVM “SVM Related MSRs” on page 583
C001_0118h SVM_KEY_MSR SVM “SVM-Lock” on page 586
C001_0119h SMM_KEY_MSR SMM “SMM-Lock” on page 587
C001_011Ah Local_SMI_Status SMM See the appropriate BIOS and Kernel 
Reference Manual  for details.
C001_011Bh Doorbell Register SVM “Doorbell Register” on page 579
C001_011Eh VMPAGE_FLUSH SVM “Secure Encrypted Virtualization” on page 588
C001_011Fh VIRT_SPEC_CTRLSpeculation Control“Speculation Control MSRs” on page 66 
C001_0130h GHCB SVM  “GHCB” on page 599 
C001_0131h SEV_STATUS SVM  “SEV_STATUS MSR” on page 593 
C001_0132h RMP_BASE SVM “Initializing the RMP” on page 604 
C001_0133h RMP_END SVM  “Initializing the RMP” on page 604
C001_0134h GUEST_TSC_FREQ SVM  “Secure TSC” on page 616
C001_0135h VIRTUAL_TOM SVM “Virtual Top-of-Memory” on page 607
C001_0137h IDLE_WAKEUP_ICR SVM “Side-Channel Protection” on page 615
C001_0140h OSVW_ID_LengthOSVW “OS-Visible Workarounds” on page 754C001_0141h OSVW StatusTable A -1. MSRs of the AMD64 Architecture (continued)
[AMD Public Use]MSR Cross-Reference 71824593—Rev. 3.41—June 2023 AMD64 Technology
C001_0200h PerfEvtSel0 
Performance“Core Performance Event-Select Registers” on 
page 412C001_0202h PerfEvtSel1 
C001_0204h PerfEvtSel2 C001_0206h PerfEvtSel3 C001_0208h PerfEvtSel4 
C001_020Ah PerfEvtSel5 
C001_0201h PerfCtr0 
“Performance Counter MSRs” on page 410C001_0203h PerfCtr1 C001_0205h PerfCtr2 C001_0207h PerfCtr3 C001_0209h PerfCtr4 
C001_020Bh PerfCtr5 
C001_0230h L2I_PerfEvtSel0 
“Performance-Monitoring MSRs” on page 724C001_0232h L2I_PerfEvtSel1 C001_0234h L2I_PerfEvtSel2 C001_0236h L2I_PerfEvtSel3 C001_0231h L2I_PerfCtr0 C001_0233h L2I_PerfCtr1 C001_0235h L2I_PerfCtr2 C001_0237h L2I_PerfCtr3 C001_0240h NB_PerfEvtSel0 C001_0242h NB_PerfEvtSel1 C001_0244h NB_PerfEvtSel2 C001_0246h NB_PerfEvtSel3 C001_0241h NB_PerfCtr0 C001_0243h NB_PerfCtr1 C001_0245h NB_PerfCtr2 C001_0247h NB_PerfCtr3 
C001_02B0h CPPC_CAPABILITY_1 CPPC
“Collaborative Processor Performance Control” 
on page 664C001_02B1h CPPC_ENABLE CPPC
C001_02B2h CPPC_CAPABILITY_2 CPPC
C001_02B3h CPPC_REQUEST CPPC
C001_02B4h CPPC_STATUS CPPCTable A -1. MSRs of the AMD64 Architecture (continued)
[AMD Public Use]719 MSR Cross-ReferenceAMD64 Technology 24593—Rev. 3.41—June 2023
A.2 System-Software MSRs
Table A -2 lists the MSRs defined for general use by system software in controlling long mode and in 
allowing fast control transfers between applications and the operating system.(C001_0300 + 
i*2h LastBranchStackFromIp
page 398 (C001_0301 + 
i*2hLastBranchStackToIp
C001_1019h DR1_ADDR_MASK 
Software Debug“Debug Breakpoint Address Masking” on page 409C001_101Ah DR2_ADDR_MASK 
C001_101Bh DR3_ADDR_MASK 
C001_1027h DR0_ADDR_MASK 
 C001_1095h L3RangeReserveBaseAddr
Memory Caches “L3 Cache Range Reservation” on page 212 C001_1096h L3RangeReserveMaxAddr
C001_109Ah L3RangeReserveWayMask
Table A -2. System-Software MSR Cross-Reference
MSR Address MSR Name Description Reset Value
0000_001Bh APIC_BASESee the appropriate BIOS and Kernel Developer’s 
Guide  or Processor Programming Reference 
Manual  for details.0000_0000_FEE0_0x00h
C000_0080h EFERContains control bits that enable extended features supported by the processor, including long mode.0000_0000_0000_0000h
C000_0081h STARIn legacy mode, used to specify the target address of a SYSCALL instruction, as well as the CS and SS selectors of the called and returned procedures.undefined
C000_0082h LSTARIn 64-bit mode, used to specify the target RIP of a SYSCALL instruction.undefined
C000_0083h CSTARIn compatibility mode, used to specify the target RIP of a SYSCALL instruction.undefined
C000_0084h SF_MASK SYSCALL Flags Mask undefined
C000_0100h FS.BaseContains the 64-bit base address in the hidden portion of the FS register (the base address from the FS descriptor).0000_0000_0000_0000h
C000_0101h GS.BaseContains the 64-bit base address in the hidden portion of the GS register (the base address from the GS descriptor).0000_0000_0000_0000hTable A -1. MSRs of the AMD64 Architecture (continued)
[AMD Public Use]MSR Cross-Reference 72024593—Rev. 3.41—June 2023 AMD64 Technology
A.3 Memory-Typing MSRs
Table A -3 lists the MSRs used to control memory-typing and the page-attribute-table mechanism.C000_0102h KernelGSbaseThe SWAPGS instruction exchanges the value in 
KernelGSbase with the value in GS.base, providing a fast method for system software to load a pointer to system data-structures.undefined
C000_0103h TSC_AUXThe RDTSCP instruction copies the value of this MSR into the ECX register.0000_0000_0000_0000h

C000_0104h TSC_RATIOSpecifies the TSCRatio value which is used to scale the TSC value read by a Guest.0000_0001_0000_0000h
0174h SYSENTER_CSIn legacy mode, used to specify the CS selector of the procedure called by SYSENTER.undefined
0175h SYSENTER_ESPIn legacy mode, used to specify the stack pointer for the procedure called by SYSENTER.undefined
0176h SYSENTER_EIPIn legacy mode, used to specify the EIP of the procedure called by SYSENTER.undefined
Table A -3. Memory-Typing MSR Cross-Reference
00FEh MTRRcapA read-only  register containing information 
describing the level of MTRR support provided by the processor.0000_0000_0000_0508h
Specifies the memory-range base address in physical-address space of a variable-range memory region. These registers also specify the memory type used for the memory region.undefined0202h MTRRphysBase1
0204h MTRRphysBase20206h MTRRphysBase30208h MTRRphysBase4
020Ch MTRRphysBase6
020Eh MTRRphysBase7Table A -2. System-Software MSR Cross-Reference (continued)
[AMD Public Use]721 MSR Cross-ReferenceAMD64 Technology 24593—Rev. 3.41—June 2023
0201h MTRRphysMask0
Specifies the size of a variable-range memory 
region.Valid (bit 11) = 0
All Other Bits Undefined0203h MTRRphysMask1
0205h MTRRphysMask20207h MTRRphysMask30209h MTRRphysMask4
020Bh MTRRphysMask5
Fixed-range MTRRs used to characterize the 
first 1 Mbyte of physical memory. Each 64-bit register contains eight type fields for characterizing a total of eight memory ranges.
• MTRRfix64K_n characterizes 64 Kbyte 
ranges.
• MTRRfix16K_n characterizes 16 Kbyte 
ranges.
• MTRRfix4K_n characterizes 4 Kbyte 
ranges.undefined0258h MTRRfix16K_80000
0259h MTRRfix16K_A00000268h MTRRfix4K_C00000269h MTRRfix4K_C8000
0277h PATUsed to extend the page-table entry format, 
allowing memory-type characterization on a physical-page basis.0007_0406_0007_0406h
02FFh MTRRdefTypeSets the default memory-type for physical addresses not within ranges established by fixed-range and variable-range MTRRs.0000_0000_0000_0000h
C001_0010h SYSCFGContains control bits for enabling and configuring system bus features.0000_0000_0002_0601h
C001_0016h IORRBase0 Specifies the memory-range base address in physical-address space of a variable-range I/O region.undefinedC001_0018h IORRBase1
C001_0017h IORRMask0 Specifies the size of a variable-range I/O 
All Other Bits Undefined C001_0019h IORRMask1
C001_001Ah TOP_MEMSets the boundary between system memory and memory-mapped I/O for addresses below 4 Gbytes.0000_0000_0400_0000h
C001_001Dh TOP_MEM2Sets the boundary between system memory and memory-mapped I/O for addresses above 4 Gbytes.undefinedTable A -3. Memory-Typing MSR Cross-Reference (continued)
[AMD Public Use]MSR Cross-Reference 72224593—Rev. 3.41—June 2023 AMD64 Technology
A.4 Machine-Check MSRs
Table A -4 lists the MSRs used in support of the machine-check mechanism.
Table A -4. Machine-Check MSR Cross-Reference
0179h MCG_CAPA read-only register that specifies the 
machine-check mechanism capabilities supported by the processor.0000_0000_0000_010xh
017Ah MCG_STATUSProvides basic information about the processor state immediately after the occurrence of a machine-check error.undefined
017Bh MCG_CTLControls global reporting of machine-check errors from various sources. 0000_0000_0000_0000h
0400h + 4i for 
0 <=i <=31MCi_CTLControl for error reporting banks, per implementation.0000_0000_0000_0000h
0401h + 4i MCi_STATUS[5:0]Status registers for each error-reporting register bank, used to report machine-check error information for the specified register bank.undefined
0402h + 4i MCi_ADDR[5:0]Reports the instruction memory-address or data memory-address responsible for the machine-check error for the specified register bank.undefined
0403h + 4i MCi_MISC[5:0]Reports miscellaneous information about the machine-check error for the specified register bank.c00x_xxxx_xx00_0000
c00x_xxxx_0000_0000 C000_0409h MC4_MISC2
C000_0410h MCA_INTR_CFG MCA interrupt configuration. 0000_0000_0000_0000h
i*10h MCA_CTL Control for error reporting banks per implementation.0000_0000_0000_0000h
i*10hMCA_STATUS Status registers for each error-reporting register bank, used to report machine-check error information for the specified register bank.undefined
i*10hMCA_ADDR Reports the instruction memory-address or data memory-address responsible for the machine-check error for the specified register bank.undefined
i*10hMCA_MISC0 Reports miscellaneous information about the machine-check error for the specified register bank.c00x_xxxx_xx00_0000
[AMD Public Use]723 MSR Cross-ReferenceAMD64 Technology 24593—Rev. 3.41—June 2023
A.5 Software-Debug MSRs
Table A -5 lists the MSRs used in support of the software-debug architecture.C000_2004h + 
i*10hMCA_CONFIG Controls configuration information of each 
MCA bank.See the appropriate BIOS and 
Kernel Developer’s Guide or Processor Programming Reference Manual .
i*10hMCA_IPID Holds information to identify the MCA bank type.See the appropriate BIOS and 
i*10hMCA_SYND Holds syndrome associated with the error. See the appropriate BIOS and 
i*10hMCA_DESTAT Holds status information for deferred errors.See the appropriate BIOS and 
i*10hMCA_DEADDR Provides the address associated with the deferred error.See the appropriate BIOS and 
(C000_200Ah:
+ i*10hMCA_MISC[4:1] Reports miscellaneous-error information.See the appropriate BIOS and 
(C000_200Eh:
C000_200Fh) 
+ i*10hMCA_SYND[2:1] Stores information associated with the error in MCA_STATUS or MCA_DESTAT.See the appropriate BIOS and 
i - indicates the register bank numberTable A -4. Machine-Check MSR Cross-Reference (continued)
[AMD Public Use]MSR Cross-Reference 72424593—Rev. 3.41—June 2023 AMD64 Technology
A.6 Performance-Monitoring MSRs
Table A -6 lists the MSRs used in support of performance monitoring, including the time-stamp 
counter.Table A -5. Software-Debug MSR Cross-Reference
01D9h DebugCtlProvides debug controls for control-transfer 
recording and control-transfer single stepping, and external-breakpoint reporting and trace messages.0000_0000_0000_0000h
01DBh LastBranchFromIPDuring control-transfer recording, this register is loaded with the segment offset of the control-transfer source.undefined
01DCh LastBranchToIPDuring control-transfer recording, this register is loaded with the segment offset of the control-transfer target.undefined
01DDh LastIntFromIPWhen an interrupt occurs during control-transfer recording, this register is loaded with LastBranchFromIP before LastBranchFromIP is updated.undefined
01DEh LastIntToIPWhen an interrupt occurs during control-transfer recording, this register is loaded with LastBranchToIP before LastBranchToIP is updated.undefined
C000_1027h DR0_ADDR_MASK Address mask for DR0 breakpoint [31:0] 0000_0000_0000_0000h
C000_1019h DR1_ADDR_MASK Address mask for DR1 breakpoint [31:0] 0000_0000_0000_0000h
C000_101Ah DR2_ADDR_MASK Address mask for DR2 breakpoint [31:0] 0000_0000_0000_0000h
C000_101Bh DR3_ADDR_MASK Address mask for DR3 breakpoint [31:0] 0000_0000_0000_0000h
Table A -6. Performance-Monitoring MSR Cross-Reference
0010h TSCCounts processor-clock cycles. It is 
incremented once for each processor-clock cycle.0000_0000_0000_0000h
00E7h MPERF Denominator of effective frequency ratio. 0000_0000_0000_0000h
00E8h APERF Numerator of effective frequency ratio. 0000_0000_0000_0000h
C000_00E7h MPerfReadOnly Read only version of MPERF.
0000_0000_0000_0000hC000_00E8h APerfReadOnly Read only version of APERF.
C000_00E9h IRPerfCount Dedicated instructions retired performance 
counter.
[AMD Public Use]725 MSR Cross-ReferenceAMD64 Technology 24593—Rev. 3.41—June 2023
For the corresponding performance counter, 
this register specifies the events counted, and controls other aspects of counter operation.0000_0000_0000_0000hC001_0001h PerfEvtSel1

counter.
Used to count specific processor events, or the 
duration of events, as specified by the corresponding PerfEvtSeln register.undefinedC001_0005h PerfCtr1
C001_0006h PerfCtr2C001_0007h PerfCtr3C001_0200h PerfEvtSel0
These MSR addresses are aliases for the base 
set of performance event-select registers PerfEvtSel[3:0].
0000_0000_0000_0000hC001_0202h PerfEvtSel1
C001_0204h PerfEvtSel2C001_0206h PerfEvtSel3C001_0208h PerfEvtSel4 Extended core performance event-select 
registers. Support for these MSRs is indicated by CPUID Fn8000_0001_ECX[PerfCtrExtCore] = 1.C001_020Ah PerfEvtSel5
C001_0201h PerfCtr0
These MSR addresses are aliases for the base set of performance-monitoring counter registers PerfCtr[3:0].undefinedC001_0203h PerfCtr1
C001_0205h PerfCtr2C001_0207h PerfCtr3C001_0209h PerfCtr4 Extended core performance counter registers. 
Support for these MSRs is indicated by CPUID Fn8000_0001_ECX[PerfCtrExtCore] = 1.C001_020Bh PerfCtr5
C001_0230h L2I_PerfEvtSel0Specifies the L2 cache events to be counted and controls other aspects of counter operation.Support for these MSRs is indicated by CPUID Fn8000_0001_ECX[PerfCtrExtL2I] = 1.0000_0000_0000_0000hC001_0232h L2I_PerfEvtSel1
C001_0234h L2I_PerfEvtSel2C001_0236h L2I_PerfEvtSel3C001_0231h L2I_PerfCtr0 Counts specific L2 cache events as specified 
by the corresponding L2I_PerfEvtSel n 
Register.Support for these MSRs is indicated by CPUID Fn8000_0001_ECX[PerfCtrExtL2I] = 1.undefinedC001_0233h L2I_PerfCtr1
C001_0235h L2I_PerfCtr2C001_0237h L2I_PerfCtr3C001_0240h NB_PerfEvtSel0 Specifies Northbridge events to be counted and 
controls other aspects of counter operation.
Support for these MSRs is indicated by CPUID Fn8000_0001_ECX[PerfCtrExtNB] = 1.0000_0000_0000_0000hC001_0242h NB_PerfEvtSel1
C001_0244h NB_PerfEvtSel2
C001_0246h NB_PerfEvtSel3Table A -6. Performance-Monitoring MSR Cross-Reference (continued)
[AMD Public Use]MSR Cross-Reference 72624593—Rev. 3.41—June 2023 AMD64 Technology
A.7 Secure Virtual Machine MSRs
Table A -7 lists the MSRs used in support of SVM functions.C001_0241h NB_PerfCtr0 Counts specific Northbridge events as 
specified by the corresponding NB_PerfEvtSel n Register.
Support for these MSRs is indicated by CPUID Fn8000_0001_ECX[PerfCtrExtNB] = 1.undefinedC001_0243h NB_PerfCtr1
C001_0245h NB_PerfCtr2C001_0247h NB_PerfCtr3
Table A -7. Secure Virtual Machine MSR Cross-Reference
C000_0104h TSC Ratio Ratio for scaling TSC, MPERF, and 
MPerfReadOnly values read by guest.
C001_0114h VM_CR Controls certain global aspects of SVM. undefined
C001_0115h IGNNESets the state of the processor-internal IGNNE signal.
C001_0116h SMM_CTLProvides software control over SMM signals.
C001_0117h VM_HSA VE_PAHolds the physical address of a block of memory where VMRUN saves host state, and from which #VMEXIT reloads host state.
C001_0118h SVM_KEYCreates a password-protected mechanism to clear VM_CR.LOCK.
C001_011Bh Doorbell RegisterSends a doorbell signal to the specified physical APIC.
C001_011Eh VMPAGE_FLUSH“Secure Encrypted Virtualization” on page 588
C001_0130h GHCBGuest-HV Communication Block address (see section 15.35.7)
C001_0131h SEV_STATUSSEV active features indication (see section 15.35.10)
C001_0132h RMP_BASE Base address of RMP (see 15.36.4) 0000_0000_0000_0000h
C001_0133h RMP_END Ending address of RMP (see 15.36.4) 0000_0000_0000_0000h
C001_0134h GUEST_TSC_FREQ Guest TSC Frequency (see 15.36.18) 0000_0000_0000_0000h Table A -6. Performance-Monitoring MSR Cross-Reference (continued)
[AMD Public Use]727 MSR Cross-ReferenceAMD64 Technology 24593—Rev. 3.41—June 2023
A.8 System Management Mode MSRs
Table A -8 lists the MSRs used in support of SMM functions.
A.9 CPUID Name MSR Cross-Reference
Table A -9 lists the MSRs used to support CPUID namestring.Table A -8. System Management Mode MSR Cross-Reference
C001_0056h SMI_Trigger_IO_CycleSpecifies an I/O cycle that may be generated 
when a local SMI trigger event occurs. See the appropriate See the appropriate BIOS 
and Kernel Developer’s Guide or Processor 
Programming Reference Manual  for details.0000_0000_0000_0000h
C001_0061h P-State Current Limit 
C001_0062h P-State Control C001_0063h P-State Status C001_0111h SMBASE Contains the SMRAM base address. 0000_0000_0003_0000h
C001_0112h SMM_ADDRContains the base address of protected 
memory for the SMM Handler.0000_0000_0000_0000h
C001_0113h SMM_MASKContains a mask which determines the size of the protected area for the SMM handler.0000_0000_0000_0000h
C001_0119h SMM_KEY_MSR 
C001_011Ah Local_SMI_StatusContains status associated with SMI sources local to the CPU core. See the appropriate BIOS and Kernel Developer’s Guide or Processor Programming Reference Manual  
for details.0000_0000_0000_0000h
Table A -9. CPUID Namestring MSR Cross Reference
Processor_Name_StringSee appropriate BIOS and Kernel 
Developer’s Guide (BKDG) or Processor 
Programming Reference Manual  and 
Processor Revision Guide .0000_0000_0000_0000hC001_0031h
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A.10 Shadow Stack MSRs 
Table A -10 lists the MSRs that support the shadow stack feature. These registers are defined if the 
shadow stack feature is present as indicated by CPUID Fn0000_0007_x0_ECX[CET_SS] (bit 7) =1. 
A.11 Speculation Control MSRs 
Table A -11 lists the MSRs that support speculation control. See “Speculation Control MSRs” on 
page 66 for further details, including how to determine whether these registers are defined. 
A.12 Memory Cache MSRs Table A -10. Shadow Stack MSR Cross Reference 
MSR Address MSR Name Description Reset Value 
06A0h U_CET User-mode shadow stack controls 
0000_0000_0000_0000h 06A2h S_CET Supervisor-mode shadow stack controls 
06A4h PL0_SSP CPL 0 shadow stack pointer 
06A5h PL1_SSP CPL 1 shadow stack pointer 
06A6h PL2_SSP CPL 2 shadow stack pointer 
06A7h PL3_SSP CPL 3 shadow stack pointer 
06A8h ISST_ADDRContains the base address of the Interrupt 
SSP Table 
Table A -11. Speculation Control MSRs 
0048h SPEC_CTRL Speculation Control 0000_0000_0000_0000h 0049h PRED_CMD Prediction Control 
C001_011Fh VIRT_SPEC_CTRL Virtual Speculation Control 
Table A -12. Memory Cache MSRs 
 C001_1095h L3RangeReserveBaseAddr L3 Range Reserve Base Address Register
C001_1096h L3RangeReserveMaxAddrL3 Range Reserve Maximum Address Register
C001_109Ah L3RangeReserveWayMask L3 Range Reserve Way Mask
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A.13 Quality of Service MSRs 
A.14 Collaborative Processor Performance Control MSRs Table A -13. Quality of Service MSRs
0C81h L3_QOS_CFG1 CDP enable 0
0C8Dh QM_EVTSEL QOS event selection 0
0C8Eh QM_CTR QOS counter 0
0C8Fh PQR_ASSOC RMID association 0
0C90h+n L3_MASK_n L3 allocation mask Bits CBM_LEN:0 are set, 
all others cleared
C000_0200+n L3QOS_BW_CONTROL_n L3 bandwidth control U bit set, all other bits 
cleared
C000_0280+n L3QOS_SMBW_CONTROL_n L3 slow memory bandwidth control U bit set, all other bits 
cleared
C000_03FDh L3_QOS_ABMC_CFG ABMC configuration See 19.3.3.3
C000_03FEh L3_QOS_ABMC_DSC ABMC discovery 0
C000_03FFh L3_QOS_EXT_CFG ABMC, SDCI enables 0
C000_0400h QOS_EVT_CFG_0 BMEC configuration See 19.3.3.2
C000_0401h QOS_EVT_CFG_1 BMEC configuration See 19.3.3.2
Table A -14. Collaborative Processor Performance Control MSRs
C001_02B0h  CPPC_CAPABILITY_1 CPPC performance ranges 0
C001_02B1h  CPPC_ENABLE CPPC enable 0
C001_02B2h  CPPC_CAPABILITY_2 CPPC constrained max performance level 0
C001_02B3h  CPPC_REQUEST CPPC request 0
C001_02B4h  CPPC_STATUS CPPC status 0
[AMD Public Use]Layout of VMCB 73024593—Rev. 3.41—June 2023 AMD64 Technology
Appendix B Layout of VMCB
The VMCB is divided into two areas—the first one contains various control bits including the 
intercept vectors and the second one contains saved guest state.
Table B-1 describes the layout of the control area of the VMCB, which starts at offset zero within the 
VMCB page. The control area is padded to a size of 1024 bytes. All unused bytes must be zero, as they are reserved for future expansion. It is recommended that software zero out any newly allocated VMCB.
Table B-1. VMCB Layout, Control Area
Byte Offset Bit(s) Function
000h (vector 0)15:0 Intercept reads of CR0–15, respectively
31:16 Intercept writes of CR0–15, respectively
004h (vector 1)15:0 Intercept reads of DR0–15, respectively
31:16 Intercept writes of DR0–15, respectively.
008h (vector 2) 31:0 Intercept exception vectors 0–31, respectively
00Ch (vector 3)0 Intercept INTR (physical maskable interrupt)

1 Intercept NMI
2 Intercept SMI
3 Intercept INIT
4 Intercept VINTR (virtual maskable interrupt)
5Intercept CR0 writes that change bits other than CR0.TS or 
CR0.MP
6 Intercept reads of IDTR
7 Intercept reads of GDTR
8 Intercept reads of LDTR
9 Intercept reads of TR
10 Intercept writes of IDTR
11 Intercept writes of GDTR
12 Intercept writes of LDTR
13 Intercept writes of TR
14 Intercept RDTSC instruction
15 Intercept RDPMC instruction
[AMD Public Use]731 Layout of VMCBAMD64 Technology 24593—Rev. 3.41—June 2023
00Ch (continued)16 Intercept PUSHF instruction
17 Intercept POPF instruction
18 Intercept CPUID instruction
19 Intercept RSM instruction
20 Intercept IRET instruction
21 Intercept INT n instruction
22 Intercept INVD instruction
23 Intercept PAUSE instruction
24 Intercept HLT instruction
25 Intercept INVLPG instruction
26 Intercept INVLPGA instruction
27 IOIO_PROT—Intercept IN/OUT accesses to selected ports
28MSR_PROT—intercept RDMSR or WRMSR accesses to 
selected MSRs
29 Intercept task switches
30FERR_FREEZE: intercept processor “freezing” during legacy FERR handling
31 Intercept shutdown eventsTable B-1. VMCB Layout, Control Area (continued)
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010h (vector 4)0 Intercept VMRUN instruction
1 Intercept VMMCALL instruction
2 Intercept VMLOAD instruction
3 Intercept VMSA VE instruction
4 Intercept STGI instruction
5 Intercept CLGI instruction
6 Intercept SKINIT instruction
7 Intercept RDTSCP instruction
8 Intercept ICEBP instruction
9 Intercept WBINVD and WBNOINVD instructions
10 Intercept MONITOR/MONITORX instruction
11 Intercept MWAIT/MWAITX instruction unconditionally
12Intercept MWAIT/MWAITX instruction if monitor hardware 
is armed
13 Intercept XSETBV instruction
14 Intercept RDPRU instruction
15Intercept writes of EFER (occurs after guest instruction finishes)
31:16Intercept writes of CR0-15 (occurs after guest instruction finishes)
014h (vector 5)0 Intercept all INVLPGB instructions
1 Intercept only illegally specified INVLPGB instructions
2 Intercept INVPCID instruction
3 Intercept MCOMMIT instruction
4 Intercept TLBSYNC instruction. Presence of this bit is indicated by CPUID Fn8000_000A, EDX[24] = 1.
5Intercept bus lock operations when Bus Lock Threshold Counter is 0 (occurs before guest instruction executes).
31:6 RESERVED, SBZ
018h–03Bh RESERVED, SBZ
03Ch 15:0 PAUSE Filter Threshold
03Eh 15:0 PAUSE Filter Count
040h 63:0IOPM_BASE_PA—Physical base address of IOPM (bits 11:0 are ignored)
048h 63:0MSRPM_BASE_PA—Physical base address of MSRPM (bits 11:0 are ignored)
050h 63:0 TSC_OFFSET—To be added in RDTSC and RDTSCPTable B-1. VMCB Layout, Control Area (continued)
[AMD Public Use]733 Layout of VMCBAMD64 Technology 24593—Rev. 3.41—June 2023
058h31:0 Guest ASID
39:32TLB_CONTROL
00h—Do nothing01h—Flush entire TLB (all entries, all ASIDs) on VMRUN 
Should only be used by legacy hypervisors
03h—Flush this guest’s TLB entries07h—Flush this guest’s non-global TLB entries
NOTE: All other encodings are reserved.
63:40 RESERVED, SBZ
060h7:0V_TPR—The virtual TPR for the guest. Bits 3:0 are used for 
a 4-bit virtual TPR value; bits 7:4 are SBZ.
NOTE : This value is written back to the VMCB at #VMEXIT.
8V_IRQ—If nonzero, virtual INTR is pending
NOTE: This value is written back to the VMCB at #VMEXIT.
This field is ignored on VMRUN when AVIC is enabled.
9VGIF value (0 – Virtual interrupts are masked, 1 – Virtual 
Interrupts are unmasked)
11 V_NMI - If nonzero, virtual NMI is pending
12 V_NMI_MASK - if nonzero, virtual NMI is masked
15:13 RESERVED, SBZ
19:16V_INTR_PRIO—Priority for virtual interrupt
NOTE: This field is ignored on VMRUN when AVIC is enabled..
20V_IGN_TPR—If nonzero, the current virtual interrupt ignores the (virtual) TPR
23:21 RESERVED, SBZ
24V_INTR_MASKING—Virtualize masking of INTR interrupts ( “Virtualizing APIC.TPR” on page 532)
25AMD Virtual GIF enabled for this guest (0  - Disabled, 1  -Enabled)
26V_NMI_ENABLE - NMI Virtualization Enable (see  “NMI Virtualization” on page 535)
29:27 Reserved, SBZ
30 x2A VIC Enable (see “x2A VIC” on page 582)
31 A VIC Enable
39:32V_INTR_VECTOR—Vector to use for this interrupt
63:40 RESERVED, SBZTable B-1. VMCB Layout, Control Area (continued)
[AMD Public Use]Layout of VMCB 73424593—Rev. 3.41—June 2023 AMD64 Technology
068h0 INTERRUPT_SHADOW - Guest is in an interrupt shadow
1GUEST_INTERRUPT_MASK - Value of the RFLAGS.IF 
bit for the guest
Note: This value is written back to the VMCB on #VMEXIT. It is not 
used during VMRUN.
63:2 RESERVED, SBZ
070h 63:0 EXITCODE
078h 63:0 EXITINFO1
080h 63:0 EXITINFO2
088h 63:0 EXITINTINFO
090h0 NP_ENABLE—Enable nested paging.
1 Enable Secure Encrypted Virtualization
2 Enable Encrypted State for Secure Encrypted Virtualization
3 Guest Mode Execute Trap
4SSSCheckEn - Enable supervisor shadow stack restrictions in nested page tables. Support for this feature is indicated by CPUID Fn8000_000A_EDX[19] (SSSCheck)
5 Virtual Transparent Encryption.
6Enable Read Only Guest Page Tables. See  “Nested Table Walk” on page 549
7 Enable INVLPGB/TLBSYNC.
0 - INVLPGB and TLBSYNC will result in #UD.1 - INVLPGB and TLBSYNC can be executed in guest.Presence of this bit is indicated by CPUID bit 8000_000A, 
EDX[24] = 1. When in SEV-ES guest or this bit is not present, INVLPGB/TLBSYNC is always enabled in guest if supported by processor. 
63:8 RESERVED, SBZ
098h63:52 RESERVED, SBZ
51:0 A VIC APIC_BAR
0A0h 63:0 Guest physical address of GHCB
0A8h 63:0EVENTINJ—Event injection ( “Event Injection” on 
page 530 for details)
0B0h 63:0N_CR3—Nested page table CR3 to use for nested 
pagingTable B-1. VMCB Layout, Control Area (continued)
[AMD Public Use]735 Layout of VMCBAMD64 Technology 24593—Rev. 3.41—June 2023
When SEV-ES is not enabled, the state-save area within the VMCB starts at offset 400h into the 
VMCB page; Table B-2 describes the fields within the state-save area; note that the table lists offsets relative to the state-save area  (not the VMCB as a whole). 0B8h0LBR_VIRTUALIZATION_ENABLE
0—Do nothing1—Enable LBR virtualization hardware acceleration
1 Virtualized VMSA VE/VMLOAD (Enable)
2Virtualized Instruction-Based Sampling (Enable). See 
“Instruction-Based Sampling Virtualization” on page 618 for details.
63:3 RESERVED, SBZ
0C0h31:0VMCB Clean Bits. See “Layout of VMCB Clean Field” on page 526
63:32 RESERVED, SBZ
0C8h 63:0 nRIP—Next sequential instruction pointer
0D0h7:0 Number of bytes fetched
127:8 Guest instruction bytes
0E0h63:52 RESERVED, SBZ
51:0 A VIC APIC_BACKING_PAGE Pointer
0E8h–0EFh RESERVED, SBZ
0F0h63:52 RESERVED, SBZ
51:12 A VIC LOGICAL_TABLE Pointer
11:0 Reserved, SBZ
0F8h63:52 RESERVED, SBZ
51:12 A VIC PHYSICAL_TABLE Pointer[51:12]
11:8 RESERVED, SBZ
7:0 A VIC_PHYSICAL_MAX_INDEX
100h – 107h RESERVED, SBZ
108h63:52 RESERVED, SBZ
51:12 VMSA Pointer[51:12]
11:0 RESERVED, SBZ
110h 63:0 VMGEXIT_RAX
118h 7:0 VMGEXIT_CPL
120h 15:0 Bus Lock Threshold Counter
All other fields up to 3DFh RESERVED, SBZ
3E0h – 3FFh Reserved for Host usageTable B-1. VMCB Layout, Control Area (continued)
[AMD Public Use]Layout of VMCB 73624593—Rev. 3.41—June 2023 AMD64 Technology
Table B-2. VMCB Layout, State Save Area 
Offset Size Contents Notes
000h word
ESselector
002h word attrib
004h dword limit
008h qword base Only lower 32 bits are implemented
010h word
CSselector
012h word attrib
014h dword limit
018h qword base Only lower 32 bits are implemented
020h word
SSselector
022h word attrib
024h dword limit
028h qword base Only lower 32 bits are implemented
030h word
DSselector
032h word attrib
034h dword limit
038h qword base Only lower 32 bits are implemented
040h word
FSselector
042h word attrib
044h dword limit
048h qword base
050h word
GSselector
052h word attrib
054h dword limit
058h qword base
060h word
GDTRselector RESERVED
062h word attrib RESERVED
064h dword limit Only lower 16 bits are implemented
068h qword base
070h word
LDTRselector
072h word attrib
074h dword limit
078h qword base
[AMD Public Use]737 Layout of VMCBAMD64 Technology 24593—Rev. 3.41—June 2023
080h word
IDTRselector RESERVED
082h word attrib RESERVED
084h dword limit Only lower 16 bits are implemented
088h qword base
090h word
TRselector
092h word attrib
094h dword limit
098h qword base
0A0h–0CAh RESERVED
0CBh byte CPLIf the guest is real-mode then the CPL is forced 
to 0; if the guest is virtual-mode then the CPL is forced to 3
0CCh dword RESERVED
0D0h qword EFER
0D8h–147h RESERVED
148h qword CR4
150h qword CR3
158h qword CR0
160h qword DR7
168h qword DR6
170h qword RFLAGS
178h qword RIP
180h–1D7h RESERVED
1D8h qword RSP
1E0h qword S_CET 
1E8h qword SSP 
1F0h qword ISST_ADDR 
1F8h qword RAX
200h qword STAR
208h qword LSTAR
210h qword CSTAR
218h qword SFMASK
220h qword KernelGsBase

060h word
070h word
080h word
090h word
228h qword SYSENTER_CS
230h qword SYSENTER_ESP
238h qword SYSENTER_EIP
240h qword CR2Table B-2. VMCB Layout, State Save Area  (continued)
[AMD Public Use]Layout of VMCB 73824593—Rev. 3.41—June 2023 AMD64 Technology
248h–267h RESERVED
268h qword G_PAT Guest PAT—only used if nested paging enabled
270h qword DBGCTLGuest DebugCtl MSR—only used if hardware 
acceleration of LBR virtualization is supported and enabled by setting the LBR_VIRTUALIZATION_ENABLE bit of the VMCB control area.
278h qword BR_FROMGuest LastBranchFromIP MSR—only used if hardware acceleration of LBR virtualization is supported and enabled.
280h qword BR_TOGuest LastBranchToIP MSR—only used if hardware acceleration of LBR virtualization is supported and enabled.
288h qword LASTEXCPFROMGuest LastIntFromIP MSR—Only used if hardware acceleration of LBR virtualization is supported and enabled.
298h qword DBGEXTNCFGGuest DebugExtnCtl MSR—only used if hardware acceleration of LBR Stack virtualization is supported and enabled by setting the LBR_VIRTUALIZATION_ENABLE bit of the VMCB control area.
299h–2DFh 72 bytes RESERVED 
2E0h qword SPEC_CTRL 
2E8h–66Fh904 bytesRESERVED
670h–76Fh256 bytesLBR_STACK_FROM
LBR_STACK_TOGuest LastBranchStackFromIp and 
LastBranchStackToIp MSRs in MSR address order — only used if hardware acceleration of LBR Stack virtualization is supported and enabled by setting the LBR_VIRTUALIZATION_ENABLE bit of the VMCB control area.
770h qword LBR_SELECTGuest LastBranchStackSelect MSR - only used if hardware acceleration of LBR Stack virtualization is supported and enabled by setting the LBR_VIRTUALIZATION_ENABLE bit of the VMCB control area.Table B-2. VMCB Layout, State Save Area  (continued)
[AMD Public Use]739 Layout of VMCBAMD64 Technology 24593—Rev. 3.41—June 2023
When SEV-ES is enabled (Section 15.35  “Encrypted State (SEV-ES)” on page 595), the VMSA 
structure starts at offset 0h in the page indicated by the VMSA Pointer. The format of the VM save 
state for SEV-ES guests is described in the table below.
All state is categorized into 3 swap types based on how it is handled by hardware during a world 
switch:
The format of the host save area is identical to the guest save area described in the table below, except 
that it begins at offset 400h in the host save page (e.g., the host TR value is stored at offset 490h relative to the start of the host save page).778h qword IBS_FETCH_CTL
IBS Virtualization state (swap type C).780h qwordIBS_FETCH_
LINADDR
788h qword IBS_OP_CTL
790h qword IBS_OP_RIP
798h qword IBS_OP_DATA
7A0h qword IBS_OP_DATA2
7A8h qword IBS_OP_DATA3
7B0h qword IBS_DC_LINADDR
7B8h qword BP_IBSTGT_RIP
7C0h qword IC_IBS_EXTD_CTL
7C8h to ends of VMCB RESERVED
Table B-3. Swap Types
Swap Type Behavior in VMRUN Behavior in AE VMEXIT
AHost state saved to host save area
Guest state loaded from VMSA Guest state saved to VMSAHost state loaded from host save area
BGuest state loaded from VMSA(Host state not  saved to host save area)Guest state saved to VMSAHost state loaded from host save area
CGuest state loaded from VMSA(Host state not  saved to host save area)Guest state saved to VMSAHost state initialized to default (reset) valuesTable B-2. VMCB Layout, State Save Area  (continued)
[AMD Public Use]Layout of VMCB 74024593—Rev. 3.41—June 2023 AMD64 Technology
Table B-4. VMSA Layout, State Save Area for SEV-ES
Offset Size Content Swap Type Notes
000h 16 bytes ES A
010h 16 bytes CS A
020h 16 bytes SS A
030h 16 bytes DS A
040h 16 bytes FS B
050h 16 bytes GS B
060h 16 bytes GDTR A
070h 16 bytes LDTR B
080h 16 bytes IDTR A
090h 16 bytes TR B
0A0h qword PL0_SSP B
0A8h qword PL1_SSP B
0B0h qword PL2_SSP B
0B8h qword PL3_SSP B
0C0h qword U_CET B
0C8h dword RESERVED –
0CAh byte VMPL –Swapped for guest. Not used in 
host mode.
0CBh byte CPL A
0CCh dword RESERVED –
0D0h qword EFER A
0D8h-13Fh 104 bytes RESERVED –
140h qword XSS B
148h qword CR4 A
150h qword CR3 A
158h qword CR0 A
160h qword DR7 C
168h qword DR6 C
170h qword RFLAGS A
178h qword RIP A
180h qword DR0 B
188h qword DR1 B
190h qword DR2 B
198h qword DR3 B
1A0h qword DR0_ADDR_MASK B
[AMD Public Use]741 Layout of VMCBAMD64 Technology 24593—Rev. 3.41—June 2023
1A8h qword DR1_ADDR_MASK B
1B0h qword DR2_ADDR_MASK B
1B8h qword DR3_ADDR_MASK B
1C0h-1D7h 24 bytes RESERVED –
1D8h qword RSP A
1E0h qword S_CET A
1E8h qword SSP A
1F0h qword ISST_ADDR A
1F8h qword RAX A
200h qword STAR B
208h qword LSTAR B
210h qword CSTAR B
218h qword SFMASK B
220h qword KernelGsBase B
228h qword SYSENTER_CS B
230h qword SYSENTER_ESP B
238h qword SYSENTER_EIP B
240h qword CR2 C
248h-267h 32 bytes RESERVED –
268h qword G_PAT –Swapped for guest, not used in 
host mode.
270h qword DBGCTL A
278h qword BR_FROM A
280h qword BR_TO A
288h qword LASTEXCPFROM A
290h qword LASTEXCPTO A
298h-2DFh 72 bytes RESERVED –
2E0h qword RESERVED –
2E8h dword PKRU B
2ECh dword TSC_AUX B
2F0h qword GUEST_TSC_SCALE –
2F8h qword GUEST_TSC_OFFSET –
300h qword REG_PROT_NONCE –
308h qword RCX B
310h qword RDX B
318h qword RBX BTable B-4. VMSA Layout, State Save Area for SEV-ES (continued)
[AMD Public Use]Layout of VMCB 74224593—Rev. 3.41—June 2023 AMD64 Technology
320h qword RESERVED –
328h qword RBP B
330h qword RSI B
338h qword RDI B
340h qword R8 B
348h qword R9 B
350h qword R10 B
358h qword R11 B
360h qword R12 B
368h qword R13 B
370h qword R14 B
378h qword R15 B
380h 16 bytes RESERVED –
390h qword GUEST_EXITINFO1 – EXITINFO1 for AE exits
398h qword GUEST_EXITINFO2 – EXITINFO2 for AE exits
3A0h qword GUEST_EXITINTINFO – EXITINTINFO for AE exits
3A8h qword GUEST_NRIP –Next sequential instruction pointer 
for AE exits
3B0h qword SEV_FEATURES –Guest-controlled SEV feature selection
• Bit 0: SNPActive• Bit 1: vTOM• Bit 2: ReflectVC• Bit 3: RestrictedInjection• Bit 4: AlternateInjection• Bit 5: DebugSwap• Bit 6: PreventHostIBS• Bit 7: BTBIsolation• Bit 8: VmplSSS • Bit 9: SecureTSC• Bit 10: VmgexitParameter• Bit 11: Reserved, SBZ• Bit 12: IbsVirtualization• Bit 13: Reserved, SBZ
• Bit 14: VmsaRegProt• Bit 15: SmtProtection
• Bits 63:16: Reserved, SBZTable B-4. VMSA Layout, State Save Area for SEV-ES (continued)
[AMD Public Use]743 Layout of VMCBAMD64 Technology 24593—Rev. 3.41—June 2023
3B8h qword VINTR_CTRL –Guest-controlled injection control
• Bits 7:0: V_TPR• Bit 8: V_IRQ• Bit 9: VGIF• Bit 10: INT_SHADOW• Bit 11: V_NMI• Bit 12: V_NMI_MASK• Bits 15:13: Reserved, SBZ• Bits 19:16: V_INTR_PRIO• Bit 20: V_IGN_TPR• Bits 25:21: Reserved, SBZ• Bit 26: V_NMI_ENABLE• Bits 31:27: Reserved, SBZ• Bits 39:32: V_INTR_VECTOR• Bits 62:40: Reserved, SBZ• Bit 63: BUSY
3C0h qword GUEST_EXITCODE – EXITCODE for AE exits
3C8h qword VIRTUAL_TOM –Swapped for guest, not used in 
host mode. Only bits 51:21 are observed.
3D0h qword TLB_ID –
3D8h qword PCPU_ID –
3E0h qword EVENTINJ –Same as the EVENTINJ field in the VMCB (Table B-1) at offset 0A8h.
3E8h qword XCR0 B
3F0h-3FFh 16 bytes Reserved –
400h qword X87_DP C FP x87 data pointer
408h dword MXCSR C FP MXCSR
40Ch word X87_FTW C FP x87 tag word
40Eh word X87_FSW C FP x87 status word
410h word X87_FCW C FP control word
412h word X87_FOP C FP x87 opcode
414h word X87_DS C FP x87 DS
416h word X87_CS C FP x87 CS
418h qword X87_RIP C FP x87 RIP
420h-46Fh 80 bytes FPREG_X87 C X87 register state (stack order)
470h-56Fh 256 bytes FPREG_XMM C XMM register state
570h-66Fh 256 bytes FPREG_YMM C YMM_HI register stateTable B-4. VMSA Layout, State Save Area for SEV-ES (continued)
[AMD Public Use]Layout of VMCB 74424593—Rev. 3.41—June 2023 AMD64 Technology
670h-76Fh  256 bytesLBR_STACK_FROM 
LBR_STACK_TOC LBR Stack state
770h qword LBR_SELECT C LastBranchStackSelect state
778h qword IBS_FETCH_CTL C
IBS Virtualization state780h qword IBS_FETCH_LINADDR C
788h qword IBS_OP_CTL C
790h qword IBS_OP_RIP C
798h qword IBS_OP_DATA C
7A0h qword IBS_OP_DATA2 C
7A8h qword IBS_OP_DATA3 C
7B0h qword IBS_DC_LINADDR C
7B8h qword BP_IBSTGT_RIP C
7C0h qword IC_IBS_EXTD_CTL CTable B-4. VMSA Layout, State Save Area for SEV-ES (continued)
[AMD Public Use]745 SVM Intercept Exit CodesAMD64 Technology 24593—Rev. 3.41—June 2023
Appendix C SVM Intercept Exit Codes
When the VMRUN instruction exits (back to the host), an exit/reason code is stored in the EXIT -
CODE field in the VMCB. The exit codes are defined in Table C-1. Intercept exit codes 0h–8Dh 
equal the bit position of the corresponding flag in the VMCB’s intercept vector. 
Table C-1. SVM Intercept Codes
Code Name Cause
0h–Fh VMEXIT_CR[0–15]_READ Read of CR 0 through 15, respectively.
10h–1Fh VMEXIT_CR[0–15]_WRITE Write of CR 0 through 15, respectively.
20h–2Fh VMEXIT_DR[0–15]_READ Read of DR 0 through 15, respectively.
30h–3Fh VMEXIT_DR[0–15]_WRITE Write of DR 0 through 15, respectively.
40h–5Fh VMEXIT_EXCP[0–31] Exception vector 0–31, respectively.

60h VMEXIT_INTR Physical INTR (maskable interrupt).
61h VMEXIT_NMI Physical NMI.
62h VMEXIT_SMIPhysical SMI (the EXITINFO1 field provides more 
information) .
63h VMEXIT_INIT Physical INIT.
64h VMEXIT_VINTR Virtual INTR.
65h VMEXIT_CR0_SEL_WRITEWrite of CR0 that change.d any bits other than CR0.TS or CR0.MP
66h VMEXIT_IDTR_READ Read of IDTR.
67h VMEXIT_GDTR_READ Read of GDTR.
68h VMEXIT_LDTR_READ Read of LDTR.
69h VMEXIT_TR_READ Read of TR.
6Ah VMEXIT_IDTR_WRITE Write of IDTR.
6Bh VMEXIT_GDTR_WRITE Write of GDTR.
6Ch VMEXIT_LDTR_WRITE Write of LDTR.
6Dh VMEXIT_TR_WRITE Write of TR.
6Eh VMEXIT_RDTSC RDTSC instruction.
6Fh VMEXIT_RDPMC RDPMC instruction.
70h VMEXIT_PUSHF PUSHF instruction.
71h VMEXIT_POPF POPF instruction.
72h VMEXIT_CPUID CPUID instruction.
73h VMEXIT_RSM RSM instruction.
74h VMEXIT_IRET IRET instruction.
75h VMEXIT_SWINT Software interrupt (INT n instructions).
76h VMEXIT_INVD INVD instruction.
77h VMEXIT_PAUSE PAUSE instruction.
78h VMEXIT_HLT HLT instruction.
[AMD Public Use]SVM Intercept Exit Codes 74624593—Rev. 3.41—June 2023 AMD64 Technology
79h VMEXIT_INVLPG INVLPG instructions.
7Ah VMEXIT_INVLPGA INVLPGA instruction.
7Bh VMEXIT_IOIOIN or OUT accessing protected port (the EXITINFO1 field 
provides more information).
7Ch VMEXIT_MSR RDMSR or WRMSR access to protected MSR.
7Dh VMEXIT_TASK_SWITCH Task switch.
7Eh VMEXIT_FERR_FREEZEFP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt.
7Fh VMEXIT_SHUTDOWN Shutdown
80h VMEXIT_VMRUN VMRUN instruction.
81h VMEXIT_VMMCALL VMMCALL instruction.
82h VMEXIT_VMLOAD VMLOAD instruction.
83h VMEXIT_VMSA VE VMSA VE instruction.
84h VMEXIT_STGI STGI instruction.
85h VMEXIT_CLGI CLGI instruction.
86h VMEXIT_SKINIT SKINIT instruction.
87h VMEXIT_RDTSCP RDTSCP instruction.
88h VMEXIT_ICEBP ICEBP instruction.
89h VMEXIT_WBINVD WBINVD or WBNOINVD instruction.
8Ah VMEXIT_MONITOR MONITOR or MONITORX instruction.
8Bh VMEXIT_MWAIT MWAIT or MWAITX instruction.
8Ch VMEXIT_MWAIT_CONDITIONALMWAIT or MWAITX instruction, if monitor hardware is armed.
8Eh VMEXIT_RDPRU RDPRU instruction.
8Dh VMEXIT_XSETBV XSETBV instruction.
8Fh VMEXIT_EFER_WRITE_TRAP Write of EFER MSR (occurs after guest instruction finishes).
90h-9Fh VMEXIT_CR[0-15]_WRITE_TRAPWrite of CR0-15, respectively (occurs after guest instruction finishes).
A0h VMEXIT_INVLPGB INVLPGB instruction.
A1h VMEXIT_INVLPGB_ILLEGAL Illegal INVLPGB instruction.
A2h VMEXIT_INVPCID INVPCID instruction.
A3h VMEXIT_MCOMMIT MCOMMIT instruction.
A4h VMEXIT_TLBSYNC TLBSYNC instruction.
A5h VMEXIT_BUSLOCK Bus lock while Bus Lock Threshold Counter value is 0.
400h VMEXIT_NPFNested paging: host-level page fault occurred (EXITINFO1 
contains fault error code; EXITINFO2 contains the guest physical address causing the fault).Table C-1. SVM Intercept Codes (continued)
[AMD Public Use]747 SVM Intercept Exit CodesAMD64 Technology 24593—Rev. 3.41—June 2023
401h A VIC_INCOMPLETE_IPIA VIC—Virtual IPI delivery not completed. See "A VIC IPI 
Delivery Not Completed" on page 580 for EXITINFO1–2 definitions.
402h A VIC_NOACCELA VIC—Attempted access by guest to vAPIC register not handled by A VIC hardware. See "A VIC Access to Un-accelerated vAPIC register" on page 581 for EXITINFO1–2 definitions.
403h VMEXIT_VMGEXIT VMGEXIT instruction.
F000_000h Unused Reserved for Host.
–1 VMEXIT_INV ALID Invalid guest state in VMCB.
–2 VMEXIT_BUSYBUSY bit was set in the encrypted VMSA (see "Interrupt Injection Restrictions" on page 614).
–3 VMEXIT_IDLE_REQUIREDThe sibling thread is not in an idle state (see "Side-Channel Protection" on page 615).Table C-1. SVM Intercept Codes (continued)
[AMD Public Use]SMM Containerization 74824593—Rev. 3.41—June 2023 AMD64 Technology
Appendix D SMM Containerization
To minimally participate in SMM activity, the VMM can implement simple containerization. This 
appendix provides example pseudocode to perform this simple containerization. VMMs that do not trust SMM code should implement secure containerization, which requires further extension of the code provided here.
D.1 SMM Containerization Pseudocode
This code emulates transitions to and from SMM:
• The process of entering SMM mode as a result of a system management interrupt (SMI)
• The RSM instruction, which returns the processor from SMM.
A hypervisor that containerizes SMM must set the SMM intercept bit in all guest VMCBs. When the 
hypervisor encounters a #VMEXIT(SMI), it should then emulate SMM entry and execute the SMM handler by means of VMRUN with the RSM intercept bit set. When the RSM instruction is intercepted, the hypervisor should emulate the RSM instruction and then resume normal execution.
In this code, the hypervisor sets up the 
smm_vmcb  from scratch and assigns it the supplied address 
space identifier (ASID).This example code sets up a container VMCB for the SMM handler and copies appropriate state 
information into the SMM save area. After calling 
emulate_smm() , the hypervisor should repeatedly 
VMRUN the SMM handler VMCB until the hypervisor encounters a #VMEXIT(RSM). Finally, the hypervisor should call 
emulate_rsm() .
//emulate_smm( ):
// Inputs://   smm_vmcb:   the _virtual address_ of a VMCB that will be configured //               as an SMM container//   asid:       the asid to use for the SMM handler; the hypervisor should//               ensure that no TLB entries for this ASID are present in the TLB//   smm_regs:   an array of 64-bit values that will be filled with the //               GPRs (except RSP and RAX) for the SMM handler//   guest_vmcb:  the _virtual address_ of the VMCB of the guest//                that was running when the intercepted SMI occurred//   guest_regs: an array of 64-bit values that contains the GPRs (except RSP//               and RAX) for the guest that was running when the intercepted//               SMI occurred
void
emulate_smm(VMCB *smm_vmcb, uint32 asid, uint64 smm_regs[16], 
         VMCB *guest_vmcb, uint64 guest_regs[16])
{
setup_smm_container(*smm_vmcb, asid, smm_regs, *guest_vmcb, guest_regs)
[AMD Public Use]749 SMM ContainerizationAMD64 Technology 24593—Rev. 3.41—June 2023
//Enter SMM mode:
wrmsr(SMM_CTL_MSR, ENTER+DISMISS+SMI_CYCLE)setup_smm_save_state(*guest_vmcb, guest_regs)
do { VMRUN(smm_vmcb) } until we see #VMEXIT(RSM). 
       Shadow EFER reads and writes to protect the SVME bit.
    
   //Emulate RSM:
copy_smm_save_to_guest_vmcb(guest_vmcb, guest_regs)
//Leave SMM mode:wrmsr(SMM_CTL_MSR, EXIT+RSM_CYCLE)
}
void
setup_smm_container(VMCB &smm_vmcb, uint32 asid, uint64 smm_regs[16],
                 VMCB &g_vmcb, uint64 guest_regs[16])
{
clear smm_vmcb to all zerosset intercepts in smm_vmcb:
RSMVMRUNMSR
smm_vmcb.msrpm = (physical address of msr protection map with 
                     efer read and efer write set)
// Note that the hypervisor should shadow the SVME bit of EFER and 
   // return EFER.SVME=0 on reads of EFER.
//// Note also that the IOPM (unused in this example code) and MSRPM for the SMM // container can be statically set up and reused on subsequent SMM entries, // and can be shared between multiple cores' SMM container VMCBs. Each core // must have a separate VMCB for the SMM container, but those cores’ VMCBs may // be statically or dynamically allocated.
smm_vmcb.asid = asidsmmbase = rdmsr(smmbase_msr) // Note: smmbase is a 32 bit valueSet up the smm handler's segment information: {Selector, Attrib, Limit, Base}smm_vmcb.CS = {(smmbase & 0x00ffff00) >> 4, 0x089B, 0xffff_ffff, smmbase}
smm_vmcb.{ES, SS, DS, FS, GS} = {0x0000, 0x0893, 0xffff_ffff, 0x0000_0000}smm_vmcb.GDTR = {unused, unused, g_vmcb.gdtr_limit, g_vmcb.gdtr_base}smm_vmcb.LDTR = (copy all from g_vmcb.LDTR)smm_vmcb.IDTR = {unused, unused, g_vmcb.idtr_limit, g_vmcb.idtr_base}smm_vmcb.TR = (copy all from g_vmcb.TR)
smm_vmcb.CPL = 0
smm_vmcb.EFER = 0x1000 (SVME = 1)
[AMD Public Use]SMM Containerization 75024593—Rev. 3.41—June 2023 AMD64 Technology
smm_vmcb.CR4 = 0
smm_vmcb.DR7 = 0x0000_0400smm_vmcb.RFLAGS = 0x0000_0002smm_vmcb.RIP = 0x0000_8000
Copy the following values from g_vmcb to smm_vmcb
CR3 DR6RSPRAXSTARLSTARCSTARSFMASKKERNELGSBASESYSENTER_CSSYSENTER_ESPSYSENTER_EIP CR2CR0: clear bits 0, 2, 3, 31
copy 14 guest GPRs from guest_regs (all except RAX, RSP) to smm_regs
}
void
setup_smm_save_state(struct VMCB &g_vmcb, uint64 guest_regs[16]){
smmbase = rdmsr(smmbase_msr) // Note: smmbase is a 32 bit value
 smmsave_physical_addr = smmbase + 0xfe00 
// smmsave is the physical address of the SMM save area;
   // the hypervisor will need to map this into its virtual memory space.
smmsave = virtual_to_physical_map(smmsave_physical_addr)
Copy the following values from g_vmcb to smmsave:
all defined portions of ES, CS, SS, DS, FS, GS, GDTR, LDTR, IDTR, TR
        (all bytes of each 16-byte segment save area)
CPLEFERCR4CR3CR0DR7DR6RFLAGSRIPRSPRAX
copy 14 guest GPRs (other than RAX and RSP) from guest_regs

}
void
copy 14 guest GPRs (other than RAX and RSP) from guest_regs 
[AMD Public Use]751 SMM ContainerizationAMD64 Technology 24593—Rev. 3.41—June 2023
                                               to GPR entries in smmsave
iorestart_dword[31:0] = g_vmcb.exitinfo1[63:32] 
if ((iorestart_dword & IO_RESTART_VALID) != 0){
Copy iorestart_dword to smmsave.iorestart_dword, 
            masking out address size bits
Copy g_vmcb.exitinfo2 to smmsave.iorestart_rip
uint64 *guest_indexreg // Point to the index register in the guest context
                             // that is changed by the string instruction...
uint64 *smm_indexreg   // ...similarly, for the smm save area
if (iorestart_dword & IO_RESTART_IN != 0) {
guest_indexreg = &guest_regs[RDI] // type=IN, indexreg=RDIsmm_indexreg = &smmsave.iorestart_rdismmsave.iorestart_rsi = guest_regs[RSI]
} else {
guest_indexreg = &guest_regs[RSI] // type=OUT, indexreg=RSIsmm_indexreg = &smmsave.iorestart_rsismmsave.iorestart_rdi = guest_regs[RDI]
}
// Reconstruct the IORestart values
if (iorstart_dword & IO_RESTART_STR != 0){    uint64 mask    uint64 ecxfix
    operand_size = (iorestart_dword >> 4) & 0x7)    address_size = (iorestart_dword >> 7) & 0x7)
    if (address_size == 0) // Some SVM implementations do not provide 
                                 // these bits; we must decode on those CPUs
    address_size = decode_io_size(guest_vmcb)
    mask = (1<<address_size) - 1    if (g->RFLAGS D-bit is set)
    operand_size = -operand_size
    if (iorestart_dword & IO_RESTART_RIP != 0) 
    ecxfix = 1
    else ecxfix = 0
    *smm_indexreg = *guest_indexreg & ~mask  |  (*guest_indexreg -
                                                               operand_size) & mask
    smmsave.iorestart_rcx = mask & (guest_regs[RCX] + ecxfix)
} else { // not string    *smm_indexreg = *guest_indexreg    smmsave.iorestart_rcx = guest_regs[RCX]}
} else { // iorestart isn't valid: Put the same values into the restart values.
[AMD Public Use]SMM Containerization 75224593—Rev. 3.41—June 2023 AMD64 Technology
smmsave.iorestart_dword = 0
smmsave.iorestart_rip = g.ripsmmsave.iorestart_rcx = guest_regs[RCX]smmsave.iorestart_rsi = guest_regs[RSI]smmsave.iorestart_rdi= guest_regs[RDI]
}
smmsave.iorestart = 0
smmsave.hltrestart = 0smmsave.nmimask = 0smmsave.smm_revision = 0x30064smmsave.smm_base = smmbase
}
void
copy_smm_save_to_guest_vmcb(struct VMCB &g_vmcb, uint64 guest_regs[16]){
Copy the following values from smmsave to g_vmcb
all defined portions of ES, CS, SS, DS, FS, GS, GDTR, LDTR, IDTR, TRCPLEFERCR4CR3CR0DR7DR6RFLAGSRSPRAX
Copy the other 14 GPRs from smmsave into guest_regs. 
 
   If smmsave.iorestart is set, copy RDI,
RSI, RCX from the smmsave.iorestart_{RDI, RSI, RCX} fields 
                instead of the regular {RDI, RSI, RCX} fields.
if (smmsave.iorestart is zero and smmsave.iorestart_dword is valid){
modify g_vmcb.DR6:
clear g_vmcb.DR6[3:0] and copy BRP bits from
                smmsave.iorestart_dword[15:12] into g_vmcb.DR6[3:0]
// this preserves AMD's behavior that dr6[3:0] is not sticky,
         // but the other bits are sticky
g_vmcb.DR6.BS |= smmsave.iorestart_dword.TF
if any bit of smmsave.iorestart_dword.{BRP[3:0], TF} is nonzero, 
[AMD Public Use]753 SMM ContainerizationAMD64 Technology 24593—Rev. 3.41—June 2023
         we have a pending #DB exception,
         so set up a #DB event injection for the guest.
}
if (smmsave.iorestart is set) {
set g_vmcb.RIP = smmsave.iorestart_rip
} else if (smmsave.hltrestart is set) {
// (In the event that the guest is allowed to execute HLT and 
      // the SMM code wants to use the auto-halt restart function, 
      // we need to re-execute the HLT instruction in the guest context.      // Even if the HLT has prefixes (all of which would be ignored),      // we know that RIP-1 is the F4 opcode itself.)
Subtract 1 from the guest RIP under a mask that masks out bits 
             above the current default address size:
mask = (1 << current_address_size) - 1g_vmcb.RIP = mask & (g_vmcb.RIP-1)
} else {
set g_vmcb.RIP = smmsave.RIP
}
// Note that it is undefined to have both iorestart and hltrestart set at// the same time.
// Perform the RSM consistency checks listed in volume 3 of the 
// AMD64 Architecture Programmer's manual, except the check that // disallows CR0.PG = 1 when CR0.PE = 0.  Note that the expected// value for the SMM revision field is 0x0003_0064.  If any of the// checks fail, the native RSM instruction would have caused a // processor shutdown (which commonly results in a reboot// triggered by the chipset). The hypervisor may wish to destroy// the guest or cause its own shutdown.}
D.1.1 Converting Simple Containerization into Secure Containerization
To convert this simple containerization example into secure containerization, the hypervisor must limit 
the SMM handler's access to I/O ports, MSRs, and memory. Based on security policy decisions, the hypervisor should set appropriate bits in the I/O Protection Map and the MSR Protection map and emulate any accesses the SMM handler makes to those protected resources. The hypervisor should run the SMM handler in paged real mode, with a page table that appropriately limits memory accessible to SMM code. Additionally, the hypervisor may wish to conceal some or all of the contents of a guest's general purpose and floating-point registers from the SMM handler.
[AMD Public Use]OS-Visible Workarounds 75424593—Rev. 3.41—June 2023 AMD64 Technology
Appendix E OS-Visible Workarounds
Operating system software may provide a workaround for a hardware erratum. These operating 
system-visible workarounds are provisional and should be removed or disabled when the erratum is corrected in a subsequent hardware release.
The OS-Visible Workaround (OSVW) architecture provides a means by which operating system 
software may determining the status of a known erratum for the hardware on which the software is running. Support for the OSVW mechanism is indicated by CPUID Fn8000_0001_ECX[OSVW] = 1.
See Section 3.3, "Processor Feature Identification," on page 71 for information on using the CPUID 
Each hardware erratum is assigned a unique OSVW ID number. OSVW ID numbers start at 0 and are 
assigned sequentially up to the most recently identified erratum which is assigned the number m
−1. 
The OSVW mechanism encodes the status of each erratum for a given hardware system in a bit vector of length m accessed through OSVM MSRs 1–N. The state of bit n of the vector indicates the status of 
the erratum with the OSVW ID number n. The OSVW ID number for the erratum and the bit position 
within the erratum status bit vector, once assigned, are global across all AMD processors; the OSVW ID and bit position will not be re-used. 
The OSVW MSRs are defined as follows: 
•OSVW MSR0 contains the OSVW_ID_Length field, used to indicate the total number of valid 
OSVW ID bits ( m). The format of this MSR is shown in Figure E-1 below.
•OSVW MSR 1 and following contain the erratum status bit vector of length m. Each bit n of this 
vector encodes the status of erratum n (OSVW ID = n). The format of these MSRs is shown in 
Figure E-2 on page 755.
The bank of OSVW MSRs is located at address C001_0140h, starting with OSVW MSR0.
The OSVW MSRs should be treated as read-only registers for the OS. The OS should never write into 
these registers. Hardware allows platform firmware writes to these registers.
Figure E-1. OSVW MSR0: OSVW_ID_Length63 16 15 0
Reserved OSVW_ID_Length
Bits Mnemonic Description Access type1
63:16 Reserved
15:0 OSVW_ID_Length Total length of the status vector OSVW_E in bits. R/W
Note 1: MSR should be treated as read-only by operating system software.
[AMD Public Use]755 OS-Visible WorkaroundsAMD64 Technology 24593—Rev. 3.41—June 2023
OSVW_ID_Length—Bits [15:0].  The number of valid bits in the OSVW erratum status vector 
OSVW_E. If a specific erratum has an OSVW ID that is greater than or equal to the 
OSVW_ID_Length, the erratum is unknown to the latest release. Otherwise, the erratum status bit in the appropriate OSVW MSR can be checked to see if a workaround is required.
The erratum status bit vector (OSVW_E) is accessed through OSVW MSR 1 and following. For MSR 
N, the 64-bit MSR holds erratum status bits ( N
−1)*64+63:( N−1)*64. To access the erratum status for 
OSVW ID number n (E[n] in the diagram), read MSR N, where N = n/64 + 1, and test bit i, where i = n 
modulo 64.
Figure E-2 below gives the format of the OSVW MSRs 1–N.
Figure E-2. OSVW MSRs 1–N: OSVW Erratum Status Registers
OS-Visible Workaround Erratum Status (OSVW_E[n]) —Bits 63:0. Each bit indicates whether 
platform hardware is affected by OS-visible erratum n and whether the OS needs to apply a 
workaround.For the status bit:

modulo 64.
workaround.For the status bit: 
1 = Hardware contains the erratum; an OS software workaround is required.
0 = Hardware has corrected the erratum; an OS software workaround is unnecessary. If one is 
installed, it must be disabled. 
The location of an OSVW ID status bit within a bank of OSVW MSRs is determined as follows:
•MSR address = OSVW_MSR0 + 1 + floor (OSVW_ID /64)
•Bit offset in MSR = OSVW_ID modulo 64
If a specific erratum has an OSVW_ID that is greater than or equal to the OSVW_ID_LENGTH, 
hardware does not know about the erratum and the processor model must be used to determine whether the workaround must be applied. 
OSVW MSR bits beyond the end of the OSVW_E bit vector are reserved.63 62 1 0
E[n] E[ n] ... E[n]E[n]
Bit Mnemonic Description Access type1
i OSVW_E[ n] OS-visible workaround status bit n R/W
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E.1 Erratum Process Overview
Following is an overview of the AMD erratum process:
1. When an OS-visible erratum is discovered, AMD assigns a unique OSVW ID to the erratum and
publishes to OS vendors the starting range of affected processor models and suggested
workarounds. 
2. AMD works with platform firmware vendors and OEMs in parallel to develop a firmware update
to add the new erratum status bit to the OSVW_E erratum status bit vector for affected siliconrevisions to report the new OSVW ID as requiring a workaround. The OSVW_ID_Length field inOSVW MSR0 is incremented by one.
3. OS vendors schedule the workaround into their release schedules and eventually release it.
4. The OS detection logic for the workaround first checks whether the processor OSVW MSRs 1–N
record the erratum by comparing the OSVW ID of the erratum with the OSVW_ID_Length field
in OSVW MSR0. 
5. If the erratum OSVW ID is greater than or equal to the OSVW_ID_Length, the current firmware
does not know about this erratum. In this case, the OS software compares the processor model IDwith the starting model ID that AMD supplied with the erratum to determine if the workaroundshould be applied.
6. If the erratum OSVW ID is less than the OSVW_ID_Length, the firmare is aware of the erratum.
In this case, the OS uses the state of the associated OSVW_E status bit to conditionally apply theworkaround. If the associated status bit is set, the workaround is applied.
7. Once AMD fixes the erratum in a future release, updated firmware ensures that the OSVW_E
status bit associated with the erratum is cleared. When OS workaround detection logic runs on thenew hardware, it will see that the bit corresponding to the OSVW ID is cleared and not apply theOS workaround for that erratum.
[AMD Public Use]Index 75724593—Rev. 3.41—June 2023 AMD64 Technology
Symbols
#AC...................................................................... 257
#BP...................................................................... 248
#BR...................................................................... 249
#D................................................................. 256, 259
#DB...................................................................... 247
#DE...................................................................... 247
#DF...................................................................... 250
#GP...................................................................... 254
#I................................................................... 256, 259
#IA....................................................................... 256
#IS........................................................................ 256
#MC ..................................................................... 258
#MF ..................................................................... 256
#NM ..................................................................... 250
#NP...................................................................... 253
#O................................................................. 256, 259
#OF...................................................................... 249
#P.................................................................. 256, 259
#PF....................................................................... 255
#SS....................................................................... 253
#SX...................................................................... 562
#TS...................................................................... 252
#U................................................................. 256, 259
#UD ..................................................................... 249
#VMEXIT ...................................................... 501, 502
#XF............................................................... 258, 259
#Z.................................................................. 256, 259
Numerics
13-7LastBranchStackFromIp MSR .......................... 399
16-bit mode ................................................................ l
1-Gbyte page ......................................................... 149
1-Gbyte page translation ......................................... 149
long mode 4-level paging .................................... 150
long mode 5-level paging .................................... 151
2-Mbyte page translation—long mode 5-level paging 145
32-bit mode ................................................................ l
4-Kbyte page translation ......................................... 141
5-Level paging ...................................................... 127
5-Level Paging Enable (LA57) ................................. 50
64-bit media instructions
causing #MF exception ....................................... 346
initializing ................................................... 484, 485
MMX registers ................................................... 345
saving state ........................................................ 348
64-bit mode .......................................................... l, 13A
A bit........................................................... 91, 93, 155
A20 Masking ......................................................... 554
abort ..................................................................... 242
AC bit ..................................................................... 54
access checking ..................................................... 541
accessed (A)
code segment ........................................................ 91
data segment ........................................................ 93
page-translation tables ......................................... 155
address space identifier (ASID) ............................... 527
address-breakpoint registers (DR0-DR3) .................. 391
addressing
RIP-relative ........................................................... lv
address-size prefix ................................................... 31
ADDRV bit ........................................................... 309
Advanced Programmable Interrupt Controller (APIC) ......
620
AIBRSE bit ............................................................. 58
alignment check (rFLAGS.AC) ......................... 54, 257
alignment mask (CR0.AM) ............................... 43, 257
alignment-check exception (#AC) ................ 44, 54, 257
AM bit .................................................................... 43
AP startup sequence ............................................... 561
APIC ..................................................................... 620
base address ....................................................... 623
enable ................................................................ 623
error interrupts .................................................... 632
internal error ...................................................... 621
registers ............................................................. 623
timer interrupt .................................................... 629
version register ................................................... 625
APIC.TPR ............................................................. 532
APIC.TPR virtualization ......................................... 499
Application Processors (APs) .................................. 560
Arbitration ............................................................. 639
architecture differences ............................................. 23
ARPL instruction ................................................... 181
ASID .................................................................... 527
attributes ................................................................. 87
available to software (A VL)
descriptor ............................................................. 90
page-translation tables ......................................... 156
A VL bit ........................................................... 90, 156
B

B
base address ........................... 84, 86, 89, 132, 153, 154
benign exception .................................................... 250Index
[AMD Public Use]758 IndexAMD64 Technology 24593—Rev. 3.41—June 2023
BIST ..................................................................... 479
bootstrap CPU core (BSC) ...................................... 623
bootstrap processor (BSP) ............................... 482, 560
BOUND instruction ............................................... 249
bound-range exception (#BR) ................................. 249
BR_FROM ............................................................ 539
BR_TO ................................................................. 539
branches .................................................................. 32
Breakpoint
on bus lock ......................................................... 390
breakpoint
determining cause ............................................... 403
on address match ......................................... 390, 405
on any instruction ............................................... 390
on I/O ................................................................ 405
on instruction ..................................................... 404
on task switch ............................................. 390, 407
setting address .................................................... 401
specifying address-match length .......................... 402
breakpoint exception (#BP) .................................... 248
breakpoints ............................................................ 401
built-in self test (BIST) .......................................... 479
C
C bit ....................................................................... 91
cache
control mechanisms ............................................ 206
control precedence .............................................. 208
enabling ............................................................. 483
index ................................................................. 205
invalidate ........................................................... 210
line.................................................................... 186
offset ................................................................. 205
organization ....................................................... 203
self-modifying code ............................................ 205
set..................................................................... 204
tag..................................................................... 205
way................................................................... 204
writeback and invalidate ...................................... 209
cache disable (CD) bit ....................................... 44, 207
cache disable (CD), memory type ............................ 196
cache-coherency protocol ....................................... 192
losing coherency ................................................. 194
CALL
See call gate and control transfer.
call gate ........................................................... 95, 113
count field ............................................................ 97
count field, long mode ........................................ 103
descriptor, long mode ............................................ 33
jump through ...................................................... 115
parameters ......................................................... 117
privilege checks .................................................. 114
stack switch ....................................................... 117
stack switch, long mode ................................. 33, 118canonical address form ....................................... 4, 140
CD bit ............................................................. 44, 207
CD memory type .................................................... 196
CLFLUSH ..................................................... 209, 540
CLGI ............................................................ 514, 529
CLI instruction ...................................................... 178
clock multiplier ...................................................... 480
CLTS ............................................................ 178, 512
code segment ............................................... 26, 79, 91
64-bit mode .......................................................... 80
accessed (A) ......................................................... 91
conforming (C) ..................................................... 91
default-operand size (D) ........................................ 92
ignored fields in 64-bit mode ................................. 97
long bit (L) ..................................................... 26, 98
long mode ............................................................ 97
readable (R) ......................................................... 91
type field .............................................................. 91
coherency, across encryption domains ..................... 593
coherency, cache .................................................... 186
Combining Memory Types and MTRRs ................... 552
commit ...................................................................... l
commit, instruction results ...................................... 187
compatibility mode ............................................... l, 13
config space accesses ............................................. 541
conforming (C), code segment .................................. 91
consistency checks, long mode ................................ 490
containerized SMM code ........................................ 537
contributory exception ............................................ 251
control registers ................................................. 29, 40
control transfer ...................................................... 109
See also call gate and interrupt.
call gate ............................................................. 113
direct ................................................................. 109
far, conforming code segment .............................. 111
far, nonconforming code segment ......................... 109
interrupt to higher privilege ................................. 272
interrupt to same privilege ................................... 271
parameters .......................................................... 117
stack switch ........................................................ 117
control-transfer recording MSRs ............................. 398
coprocessor-segment-overrun exception ................... 251
core performance counter global control register ...... 415
core performance counter status registers ................. 415
count field ............................................................. 103
CPL.............................................................. 105, 502
definition ........................................................... 105
in call gate protection .......................................... 114
in data segment protection ........................... 106, 319
in interrupt to higher privilege ............................. 273
in protecting conforming CS ................................ 111
in protecting nonconforming CS .......................... 110
in stack segment protection .................................. 108
[AMD Public Use]Index 75924593—Rev. 3.41—June 2023 AMD64 Technology
privileged instructions ......................................... 170
SYSCALL, SYSRET assumptions ....................... 174
CPU watchdog timer register .................................. 303
CPUID ............................................... 55, 71, 177, 513
nested paging ..................................................... 554
CR0................................................................. 41, 501
alignment mask (AM) .................................... 43, 257
cache disable (CD) ........................................ 44, 207
emulate coprocessor (EM) ..................................... 42
emulate coprocessor (EM) bit .............................. 343
extension type (ET) .............................................. 43
monitor coprocessor (MP) ..................................... 42
not write-through (NW) ................................. 44, 207
numeric error (NE) ........................................ 43, 257
paging enable (PG) ........................................ 44, 129
protection enable (PE) ................................ 42, 74, 82
task switched (TS) ......................................... 43, 178
write protect (WP) ................................................ 43
CR1........................................................................ 51
CR2......................................................... 44, 255, 501
CR3....................... 25, 44, 45, 131, 140, 373, 501, 546
non-PAE paging ................................................. 131

PAE paging ................................................... 45, 131
PAE paging, long mode ....................................... 140
page-level cache disable (PCD) .................... 132, 141
page-level write-through (PWT) ................... 132, 141
table-base address ........................................ 132, 140
CR4................................................................. 46, 501
debugging extensions (DE) ................................... 48
machine-check enable (MCE) ......................... 49, 258
OS #XF support (OSXMMEXCPT) ...... 258, 343, 344
OS FXSA VE/FXRSTOR support (OSFXSR) .169, 343
page-global enable (PGE) .............................. 49, 158
page-size extensions (PSE) ..................... 48, 130, 134
performance counter enable (PCE) .......... 49, 178, 412
physical-address extensions (PAE) .... 48, 51, 129, 139
protected-mode virtual interrupts (PVI) .................. 48
time-stamp disable (TSD) ...................... 48, 178, 422
virtual-8086 mode extensions (VME) .............. 47, 287
CR5–CR7 ............................................................... 51
CR8................................................................. 51, 266
CR9–CR15 .............................................................. 51
CS register ....................................................... 79, 501
selector .............................................................. 501
CSTAR register ...................................... 175, 714, 719
D
D bit .......................................................... 92, 98, 155
D/B bit .............................................................. 90, 94
Data Limit Checks ................................................. 123
Data limit checks ................................................... 123
data prefetch, cache ................................................ 209
data segment ................................................ 27, 80, 92
64-bit mode .......................................................... 80accessed (A) ......................................................... 93
default operand size (D) ........................................ 94
expand down (E) .................................................. 93
FS and GS ...................................................... 27, 80
ignored fields in 64-bit mode ................................. 98
long mode ............................................................ 98
privilege checks .................................................. 106
type field .............................................................. 93
writable (W) ......................................................... 93
DAZ bit ................................................................. 362
DBGCTL .............................................................. 539
DE bit ..................................................................... 48
DE exception ................................................. 256, 259
debug .............................................................. 21, 560
See breakpoint and single-step.
debug exception (#DB) ................................... 247, 403
debug registers ................................................. 29, 391
address-breakpoint registers (DR0-DR3) .............. 391
control-transfer recording MSRs .......................... 398
debug-control MSR (DebugCtl) ........................... 396
debug-control register (DR7) ............................... 393
debug-extension-control (DebugExtnCtl) .............. 398
last branch stack registers .................................... 399
reserved (DR4, DR5) .......................................... 392
debug-control MSR (DebugCtl) .............................. 396
debug-control register (DR7) .................................. 393
DebugCtl register ........................................... 712, 724
debug-extension-control register
last-branch record stack enable ............................ 399
debug-extension-control register (DebugExtnCtl) ..... 398
DebugExtnCtl register ............................................ 398
debugging extensions (CR4.DE) ............................... 48
DEC instruction ....................................................... 34
default operand size
B bit, stack segment .............................................. 94
D bit, code segment .............................................. 92
D bit, data segment ....................................... 94, 121
D/B bit, descriptor ................................................ 90
with expand down ............................................... 122
denormalized-operand exception (DE) ............. 256, 259
denormals-are-zeros (DAZ) mode ........................... 362
descriptor .......................................................... 75, 88
available to software (A VL) ................................... 90
code segment ........................................................ 26
data segment ........................................................ 27
default operand size (D/B) ..................................... 90
DPL...................................................... 90, 106, 378
gate..................................................................... 27
granularity (G) ...................................................... 90
present (P) .................................................... 90, 378
S field .......................................................... 90, 378
segment base ........................................................ 89
segment limit ........................................................ 89
[AMD Public Use]760 IndexAMD64 Technology 24593—Rev. 3.41—June 2023
system segment .................................................... 27
TSS................................................................... 368
type field ...................................................... 90, 378
descriptor table .................................................. 75, 82
global-descriptor table (GDT) ................................ 77
interrupt-descriptor table (IDT) .............................. 37
local-descriptor table (LDT) .................................. 77
descriptor-table registers ..................................... 26, 76
64-bit mode ........................................................ 103
GDTR ................................................................. 83
IDTR ................................................................... 88
LDTR .................................................................. 85
DEV base address registers ..................................... 545
DEV caching ......................................................... 540
DEV capability block ............................................. 542
DEV register access ............................................... 543
DEV_BASE_HI/LO registers ................................. 543
DEV_CAP register ................................................ 544
DEV_CR register ................................................... 544
DEV_DATA .......................................................... 542
DEV_HDR ............................................................ 542
DEV_MAP Registers ............................................. 545
DEV_OP ........................................................ 542, 543
DEVBASE registers ............................................... 540
device exclusion vector (DEV) ............................... 540
device ID .............................................................. 540
device-not-available exception (#NM) ................ 42, 250
differences (architectural) ......................................... 23
direct referencing ........................................................ l
dirty (D), page-translation tables ............................. 155
displacement ........................................................... 31
displacements ............................................................ li
divide-by-zero-error exception (#DE) ...................... 247
double quadword ....................................................... li
double-fault exception (#DF) .................................. 250
doubleword ............................................................... li
DP field ................................................................ 362
DPL...................................................................... 106
data segment, 64-bit mode ..................................... 99
definition ........................................................... 106
in data segment protection ............................ 106, 319
in interrupt stack switch ...................................... 272

in stack segment protection ................................. 108
in stack switching ............................................... 117
DPL field ......................................................... 90, 378
DR0-DR3 registers ................................................ 391
DR4, DR5 registers ................................................ 392
DR6 register ................................................... 392, 502
DR7 register .......................................................... 502DS field ................................................................. 362
DS register ...................................................... 80, 501
DS.SEL ................................................................. 501
E
E bit........................................................................ 93
eAX–eSP register .................................................... lvii
EFER register ........... 29, 55, 67, 69, 501, 713, 714, 719
fast FXSA VE/FXRSTOR (FFXSR) ........................ 57
long mode active (LMA) ............................... 56, 488
long mode enable (LME) ............................... 56, 488
no-execute enable (NXE) ...................................... 57
system-call extension (SCE) .................................. 56
EFER.SVME ......................................................... 499
effective address .................................................. 2, 25
effective address size ................................................. li
effective memory type ............................................ 224
effective operand size ................................................ li
EFLAGS
See rFLAGS.
eFLAGS register ..................................................... lvii
EIP
See rIP.
eIP register ............................................................. lvii
EIPV bit ................................................................ 302
EM bit ............................................................. 42, 484
emulate coprocessor (CR0.EM) ................................. 42
EN bit ................................................................... 309
enabling SVM ....................................................... 499
endian byte-ordering ................................................ lix
End-of-Interrupt Register (EOI) .............................. 645
environment .......................................................... 349
error code
page fault ........................................................... 262
selector .............................................................. 261
ES register ....................................................... 80, 501
ES.SEL ................................................................. 501
ESP
See rSP.
ET bit ...................................................................... 43
event handler, definition ......................................... 241
event injection ....................................................... 530
EVENTINJ ............................................................ 530
exception handler, definition ................................... 241
exception intercept
#AC................................................................... 520
#BP................................................................... 519
#BR................................................................... 519
#DB................................................................... 518
#DE................................................................... 518
#DF................................................................... 519
#GP................................................................... 520
#MC .......................................................... 520, 521
[AMD Public Use]Index 76124593—Rev. 3.41—June 2023 AMD64 Technology
#MF .................................................................. 520
#NM .................................................................. 519
#NP................................................................... 520
#OF................................................................... 519
#PF................................................................... 520
#SS................................................................... 520
#TS................................................................... 520
#UD .................................................................. 519
#XF................................................................... 521
vector 2 ............................................................. 519
vector 9 ............................................................. 519
Exception Intercepts ............................................... 518
exceptions ................................................................. li
abort .................................................................. 242
benign ............................................................... 250
contributory ....................................................... 251
definition of ....................................................... 241
definition of vector ............................................. 244
differences in long mode ....................................... 36
error code, page fault .......................................... 262
error code, selector ............................................. 261
fault................................................................... 242
floating-point priorities ....................................... 264
imprecise ........................................................... 242
maskable SSE floating point ................................ 243
maskable x87 floating point ................................. 243
masking during stack switches ............................. 243
precise ............................................................... 241
priorities ............................................................ 263
trap.................................................................... 242
while in SMM .................................................... 334
exclusive state, MOESI .......................................... 192
EXITINFO1 .......................................................... 516
expand down (E)
stack segment ................................................ 93, 122
extended family field ............................................. 483
Extended Interrupts ................................................ 632
extended model field .............................................. 483
extended save area ................................................. 356
extended state management .................................... 354
extended topology .................................................. 212
extensible state management ................................... 354
extension type (CR0.ET) .......................................... 43
F
family field ........................................................... 483
far control transfer ................................................. 109
far return .......................................................... 33, 120
fast FXSA VE/FXRSTOR ......................................... 57
fault...................................................................... 242
FCW register .......................................... 347, 349, 361
feature identification ................................................ 71
FENCE ................................................................. 189FFXSR bit ............................................................... 57
fill, cache-line ........................................................ 186
first instruction ...................................................... 482
flat segmentation .............................................. 6, 9, 75
FLDENV , FSTENV instructions .............................. 353
floating-point exception pending (#MF) ................... 256
caused by 64-bit media instructions ...................... 346
floating-point exception priorities ............................ 264
flush......................................................................... li
FOP register .......................................................... 361
FPR registers ................................................. 347, 349
FS and GS ......................................................... 27, 80
FS register ............................................................... 80
FS.Base register ............................................. 714, 719
FSA VE, FRSTOR instructions ................................ 349
FSW register .................................... 345, 347, 349, 361
FTW register ................................... 346, 347, 349, 361
FXSA VE, FXRSTOR instructions ................ 36, 49, 354
32-bit memory image .......................................... 361
64-bit memory image .......................................... 360

x87 tag word format ............................................ 362
G
G bit ............................................................... 90, 156
gate descriptors ........................................................ 27
call gate ............................................................... 95
DPL................................................................... 106
ignored fields in long mode ................................. 101
illegal types in long mode .................................... 101
interrupt gate ........................................................ 95
long mode .................................................. 101, 103
redefined types in long mode ............................... 101
target-segment offset ............................................. 96
target-segment selector .......................................... 96
task gate ............................................................... 95
trap gate ............................................................... 95
GDT ....................................................................... 82
GDTR ...................................................... 83, 501, 513
general detect fault ......................................... 247, 406
general-protection exception (#GP) ......................... 254
general-purpose registers (GPRs) .............................. 28
GIF....................................................................... 529
global descriptor table (GDT) ............................. 77, 82
base address, 64-bit mode ...................................... 84
first entry ............................................................. 82
limit check, long mode .......................................... 84
global descriptor-table register (GDTR) ..................... 83
base address ......................................................... 84
limit..................................................................... 84
loading ............................................................... 179
storing ............................................................... 180
global interrupt flag (GIF) ....................................... 529
global page (G), page-translation tables ................... 156
[AMD Public Use]762 IndexAMD64 Technology 24593—Rev. 3.41—June 2023
global pages ..................................................... 49, 158
granularity (G), descriptor ................................. 90, 121
GS register .............................................................. 80
GS.Base register ............................................. 714, 719
guest mode ............................................................ 498
Guest page tables (gPT) ......................................... 547
H
halt....................................................................... 181
Hardware errata ..................................................... 754
HLT............................................................... 181, 514
host...................................................................... 497
HostMultiKeyMemEncrModeEn bit .......................... 62
HWCR .................................................................... 70
HWCR register
CpbDis bit ........................................................... 70
CpuidUserDis ...................................................... 71
IRPerfEn bit ......................................................... 70
SmmLock bit ....................................................... 70
hypervisor ............................................................. 497
I
I/O interrupts ......................................................... 621
I/O Permissions Map .............................................. 515
I/O privilege level field (rFLAGS.IOPL) ................... 53
I/O space accesses ................................................. 541
I/O, memory-mapped ............................................. 231
I/O-permission bitmap
in 32-bit TSS ...................................................... 373
in 64-bit TSS ...................................................... 376
I/O-permission bitmap (IOPB) ................................ 374
IBS
virtualization ...................................................... 618
IBS filtering .......................................................... 435
ICEBP .................................................................. 514
ID bit ...................................................................... 55
IDT......................................................................... 87
IDTR ....................................................... 88, 501, 513
IE exception ................................................... 256, 259
IF bit ................................................................ 53, 291
IGN......................................................................... lii
illegal state ............................................................ 501
immediate operand ................................................... 31
imprecise exceptions and interrupts ......................... 242
IN/OUT ................................................................ 516
INC instruction ........................................................ 34
indirect .................................................................... lii
inexact-result exception ................................... 256, 259
INIT ..................................................................... 534
initialization .......................................................... 479
initialization (INIT)
processor state .................................................... 480In-Service Register ................................................. 641
instruction-based sampling virtualization ................. 618
instructions (system-management) ........................... 170
INT3 instruction ............................................ 248, 407
integer bit .............................................................. 363
intercept ................................................................ 499
Ferr_Freeze ................................................ 522, 523
shutdown ........................................................... 524
task switch ......................................................... 522
Intercept Exit Codes ............................................... 745
Interprocessor interrupt (IPI) ........................... 560, 634
INIT .................................................................. 560
Startup ............................................................... 560
Interrupt Control .................................................... 621
interrupt descriptor table (IDT) ................................. 87
limit check, long mode .......................................... 88
interrupt descriptor-table register (IDTR) ................... 88
interrupt flag (rFLAGS.IF) ............................... 53, 178
interrupt gate ................................................... 95, 280
IST field ............................................................. 102
interrupt handler, definition ..................................... 241
interrupt intercept ................................................... 521
INIT .................................................................. 522
INTR ................................................................. 521
NMI .................................................................. 521
SMI................................................................... 521
virtual ................................................................ 522
interrupt redirection ........................................ 278, 289
Interrupt Request Register ...................................... 640
interrupt shadow stack table .................................... 286
interrupt shadows ................................................... 533
INTERRUPT_SHADOW ....................................... 501
interrupt-descriptor table (IDT)
index .................................................. 241, 270, 280
protected mode ................................................... 269
real-address mode ............................................... 267
interrupt-redirection bitmap .................................... 374
interrupts
definition of external ........................................... 241
definition of software .......................................... 241
external .............................................................. 260
external maskable ............................................... 243
external nonmaskable .......................................... 243
external-interrupt priorities .................................. 266

long mode summary ............................................ 280
returning from 64-bit mode .................................. 286
[AMD Public Use]Index 76324593—Rev. 3.41—June 2023 AMD64 Technology
returns ............................................................... 276
software ............................................................. 260
stack alignment, long mode ................................. 283
stack pointer push, long mode .............................. 281
stack switch, long mode ................................. 37, 283
to higher privilege .............................................. 272
to same privilege ................................................ 271
interrupt-stack table (IST) .......................... 37, 102, 284
interrupt-vector table .............................................. 267
INTn ..................................................................... 513
INTn instruction ............................................. 260, 407
INTO instruction ................................................... 249
INTWB bit .............................................................. 58
invalid arithmetic-operand exception ....................... 256
invalid state, MOESI .............................................. 192
invalidate page ...................................................... 529
invalid-opcode exception (#UD) ........................ 34, 249
invalid-operation exception (IE) ....................... 256, 259
invalid-TSS exception (#TS) ................................... 252
INVD .................................................... 182, 210, 513
INVLPG ............................................................... 514
INVLPG instruction ................................ 158, 182, 183
INVLPGA ...................................................... 514, 529
IOPB ............................................................. 373, 374
IOPL .................................................................... 516
IOPL field ........................................................ 53, 277
IOPL-sensitive instruction ...................................... 287
IOPM ................................................................... 515
IOPM_BASE_PA .................................................. 515
IORRBasen registers ............................... 233, 716, 721
IORRMaskn registers ...................................... 234, 721
IORRs, variable-range ............................................ 233
IOSPE .................................................................. 541
IRET .................................................................... 513
less privilege ............................................... 276, 277
long mode ..................................................... 37, 286
same privilege .................................................... 276
IST field ................................................................ 102
J
J bit...................................................................... 364
jump
K
KernelGSbase register ............................. 177, 714, 720
L
L bit........................................................................ 98
L1 data cache ........................................................ 186L1 instruction cache ............................................... 186
L2 cache ................................................................ 186
L2I_PerfEvtSel registers ......................................... 419
L3 cache range reservation ...................................... 212
registers ............................................................. 212
L3 range reservation
operation ............................................................ 215
programming considerations ................................ 215
register programming .......................................... 214
used as range lock ............................................... 214
L3 range reserve
maximum address ............................................... 213
way mask ........................................................... 214
LAR instruction ..................................................... 180
last branch record virtualization .............................. 538
last branch stack registers ....................................... 399
LastBranchFromIP ................................................. 538
LastBranchFromIP register ............................. 712, 724
LastBranchStackFromIp register ............................. 399
LastBranchStackSelect register ............................... 401
LastBranchToIP ..................................................... 538
LastBranchToIP register ................................. 712, 724
LASTEXCPFROM ................................................ 539
LASTEXCPTO ...................................................... 539
LastIntFromIP ....................................................... 538
LastIntFromIP register .................................... 712, 724
LastIntToIP ........................................................... 538
LastIntToIP register ........................................ 712, 724
LastStackToIp register ............................................ 399
LDT........................................................................ 84
selector field ....................................................... 373
LDTR ............................................................. 85, 513
Legacy Interrupts ................................................... 621
legacy mode ................................................. lii, 14, 23
legacy PAE mode ................................................... 554
legacy x86 ............................................................... lii
LFENCE ............................................................... 189
LFENCE instruction ............................................... 209
LGDT ........................................................... 179, 513
LIDT ............................................................. 179, 513
limit..................................................... 84, 87, 89, 368
linear address ............................................................. 3
Link field .............................................................. 373
LINT0 ................................................................... 631
LINT1 ................................................................... 631
LLDT ............................................................ 180, 513
LMA bit .................................................................. 56
LME bit .................................................................. 56
LMSLE ................................................................... 57
LMSW ................................................... 177, 512, 513
load ordering ......................................................... 209
Local APIC ............................................................ 622
[AMD Public Use]764 IndexAMD64 Technology 24593—Rev. 3.41—June 2023
ID..................................................................... 625
interrupt masking ......................................... 534, 645
local descriptor table (LDT) ................................ 77, 84
base address, 64-bit mode ..................................... 87
limit check, long mode .......................................... 87
local descriptor-table register (LDTR) ....................... 85
attributes .............................................................. 87
base address ......................................................... 86
hidden portion ...................................................... 85
LDT selector ........................................................ 86
limit .................................................................... 87
loading .............................................................. 180
Local Interrupts ..................................................... 627
locality .................................................................. 157
logging
unauthorized access ............................................ 546
logical address ........................................................... 2
long attribute (L)
code segment ....................................................... 98
effect on D bit ...................................................... 98
long mode ................................................... liii, 12, 23
2-Mbyte physical-page translation ....................... 145
activating ........................................................... 489

logging
consistency checks ............................................. 490
CR3 register ....................................................... 140
differences from legacy mode ................................ 39
enabling ............................................................. 488
enabling versus activating ................................... 488
GDT requirements .............................................. 487
IDT requirements ............................................... 487
leaving ............................................................... 491
page translation-table requirements ...................... 488
relocating descriptor tables .................................. 490
relocating page tables .......................................... 491
TSS requirements ............................................... 488
use of CS.L and CS.D ......................................... 489
virtual to physical address translation ................... 128
long mode active (EFER.LMA) ......................... 56, 488
long mode enable (EFER.LME) ......................... 56, 488
long-mode
4-Kbyte translation-table formats ......................... 143
LSB........................................................................ liii
lsb.......................................................................... liii
LSTAR register ....................................... 175, 714, 719
LTR............................................................... 180, 513
M
M bit ..................................................................... 364
machine check
error codes ......................................................... 310
error-reporting address register (MCi_ADDR) ...... 310
error-reporting control register (MCi_CTL) .......... 306
error-reporting miscellaneous register (MCi_MISC) ......310
error-reporting register banks ....................... 305, 313
error-reporting status register (MCi_STATUS) ...... 307
global-capabilities register (MCG_CAP) .............. 300
global-control register (MCG_CTL) ..................... 302
global-status register (MCG_STATUS) ................. 301
initialization ....................................................... 318
machine check registers .......................................... 300
machine-check enable (CR4.MCE) .................... 49, 258
machine-check exception (#MC) ............................. 258
mask ...................................................................... liii
masking
definition of interrupt .......................................... 241
MBZ ...................................................................... liii
MCA error code field ............................................. 308
MCE bit .................................................................. 49
MCG_CAP register ................................. 300, 711, 722
MCG_CTL register ................................. 302, 711, 722
MCG_CTL Register Present bit ............................... 301
MCG_STATUS register ........................... 301, 711, 722
MCi Bank Count field ............................................ 301
MCi_ADDR registers .............................. 310, 713, 722
MCi_CTL registers ................................. 306, 307, 713
MCi_MISC registers ...................................... 713, 722
MCi_STATUS registers ........................... 307, 713, 722
MCIP bit ............................................................... 302
MCOMMIT bit ........................................................ 58
Media Extension Control and Status Register (MXCSR) ..
344
MemEncryptionModeEn bit ...................................... 62
memory ................................................................. 184
memory addressing
canonical address form ............................................ 4
effective address ..................................................... 2
linear address ......................................................... 3
logical address ........................................................ 2
near pointers ........................................................... 2
physical address ...................................................... 3
real address .......................................................... 10
RIP-relative address .............................................. 31
segment offset ........................................................ 2
virtual address ........................................................ 3
memory consistency ............................................... 552
memory management ................................................. 5
memory serialization .............................................. 209
memory system ...................................................... 184
memory type .......................................................... 196
determining effective .......................................... 224
uncacheable (UC) ............................................... 196
write-combining (WC) ........................................ 197
write-combining plus (WC+) ............................... 197
write-protect (WP) .............................................. 197
memory-access ordering
[AMD Public Use]Index 76524593—Rev. 3.41—June 2023 AMD64 Technology
description ......................................................... 187
read ordering ...................................................... 187
write ordering ..................................................... 188
memory-mapped I/O
directing reads and writes to ......................... 231, 235
memory-type range register (MTRR) ........................ 29
combined with PAT ............................................. 229
effect of paging cache controls ............................ 224
effects with large page sizes ................................ 225
fixed range ......................................................... 218
identifying features ............................................. 223
initial value ........................................................ 483
IORRBase .......................................................... 233
IORRMask ......................................................... 234
MTRRcap .......................................................... 223
MTRRdefType ................................................... 223
MTRRfix16K ..................................................... 219
MTRRfix4K ...................................................... 219
MTRRfix64K ..................................................... 219
MTRRphysBase ................................................. 220
MTRRphysMask ................................................ 221
overlapping ranges ............................................. 225
type field, default ................................................ 217
type field, extended ............................................ 231
variable range ..................................................... 220
variable range size and alignment ........................ 222
MFENCE instruction ............................................. 209
MISCV bit ............................................................ 309
MMX registers ...................................................... 345
model field ............................................................ 483
model-specific error code field ................................ 308
model-specific registers (MSRs) .................. 29, 59, 178
control-transfer recording .................................... 398
debug extensions .................................................. 63
initializing .......................................................... 485
machine check .............................. 64, 65, 66, 67, 300
memory typing .............................................. 63, 217
PAT................................................................... 226
performance monitoring ................................. 64, 411
SYSCFG .............................................................. 60
system linkage ............................................... 62, 175
time-stamp counter ........................................ 64, 422
TOP_MEM ........................................................ 235
TOP_MEM2 ...................................................... 235
modes ..................................................................... 11
64-bit ................................................................... 13
compatibility ..................................................... l, 13
legacy ............................................................. lii, 14
long............................................................... liii, 12
protected ........................................................ liv, 14
real............................................................ liv, 4, 14
virtual-8086 ................................................... lvi, 14
modified state, MOESI ........................................... 192

MOESI ................................................................. 192moffset ................................................................... liii
monitor coprocessor (CR0.MP) ................................. 42
MOV CRn instruction ............................................ 177
MOV DRn instruction ............................................ 178
MOV TO CR0 ....................................................... 513
MOV TO/FROM CR0 ............................................ 512
MOV TO/FROM CRn .................................... 512, 673
MOV TO/FROM DRn .................................... 512, 673
MOVSXD instruction ............................................... 34
MP bit ............................................................. 42, 484
MSB ...................................................................... liii
msb........................................................................ liii
MSR ..................................................................... lviii
MSR permissions map (MSRPM) ........................... 517
MSR_PROT .......................................................... 517
MSRs ...................................................................... 59
MTRRcap register ................................... 223, 711, 720
MTRRdefType register ............................ 223, 712, 721
MTRRfix16K_n registers ....................................... 219
MTRRfix4K_n registers ......................................... 219
MTRRfix64K_n registers ........................ 219, 712, 721
MtrrFixDramEn bit .......................................... 61, 232
MtrrFixDramModEn bit ................................... 61, 232
MTRRphysBasen registers ...................... 220, 712, 720
MTRRphysMaskn registers ............................ 221, 721
MTRRs ......................................................... 217, 552
MtrrTom2En bit ............................................... 61, 237
MtrrVarDramEn bit .......................................... 61, 237
multiprocessor issues .............................................. 541
MXCSR register .................................................... 345
field................................................................... 362
MXCSR_MASK field ......................................... 362
N
NB_PerfEvtSel registers ......................................... 418
NE bit ............................................................. 43, 484
near branch
operand size, 64-bit mode ...................................... 32
near control transfer ............................................... 109
near pointers .............................................................. 2
near return ............................................................. 120
Nested page tables (hPT) ........................................ 547
nested paging ......................................................... 546
nested task (rFLAGS.NT) ................................. 53, 386
nestedtable walk .................................................... 549
NEXT_RIP ............................................................ 501
NMI...................................................................... 248
NMI support .......................................................... 535
NMI virtualization ................................................. 535
no-execute (NX)
page-translation tables, bit in ............................... 156
nonmaskable interrupt exception (NMI) ................... 248
[AMD Public Use]766 IndexAMD64 Technology 24593—Rev. 3.41—June 2023
non-PAE paging ..................................................... 131
CR3 format ........................................................ 131
NOP instruction ....................................................... 34
not write-through (CR0.NW) ............................. 44, 207
NP_ENABLE ........................................................ 549
NT bit ..................................................................... 53
null selector ............................................................. 78
64-bit mode far return ......................................... 121
interrupt return from 64-bit mode ......................... 286
long mode interrupts .................................... 283, 285
long mode stack switch ....................................... 119
numeric error (CR0.NE) .................................... 43, 257
NW bit .................................................................... 44
NX bit ................................................................... 156
NXE bit .................................................................. 57
O
octword ................................................................... liii
OE exception .................................................. 256, 259
offset ................................................................ liii, 96
operand-size prefix .................................................. 30
operating modes ...................................................... 11
OS FXSA VE/FXRSTOR support (CR4.OSFXSR) ...169, 
343
OS unmasked exception support (CR4.OSXMMEXCPT) .
258, 343, 344
OSFXSR bit ............................................................ 49
OS-visible workarounds (OSVW) ........................... 754
OSVW ID .......................................................... 754
OSVW status ..................................................... 756
OSVW_ID_Length ............................................. 756
OSXMMEXCPT bit ........................................... 49, 50
OVER bit .............................................................. 309
overflow ................................................................. liv
overflow exception (#OF) ....................................... 249
overflow exception (OE) ................................. 256, 259
owned state, MOESI .............................................. 192
P
P bit......................................................... 90, 154, 378
packed .................................................................... liv
PAE...................................................................... 502
PAE bit ...................................................... 48, 51, 129
PAE paging ...................................................... 25, 131
CR3 format ................................................... 45, 131
CR3 format, long mode ....................................... 140
legacy mode ....................................................... 135
long mode .......................................................... 141
page directory ........................................................ 131
page size (PS) ..................................... 130, 134, 136
page directory pointer ..................................... 131, 136page faults
guest level .......................................................... 550
page size (PS), page-translation tables ..................... 155
page splintering ..................................................... 554
page table .............................................................. 131
page translation ...................................................... 126
page-attribute table (PAT) ....................................... 226
combined with MTRR ......................................... 229
effect on memory access ...................................... 228
identifying support .............................................. 228
indexing ............................................................. 227
Paged Real Mode ................................................... 530
page-fault exception (#PF) .............................. 154, 255
page-fault virtual address ........................................ 255
page-global enable (CR4.PGE) ......................... 49, 158
page-level cache disable (PCD) ............................... 207
CR3, bit in ......................................................... 132
page-translation tables, bit in ............................... 155
page-level write-through (PWT) .............................. 208
page-map level-4 ................................................... 139
page-map level-5 ................................................... 139
page-size extensions (CR4.PSE) ...... 25, 26, 48, 130, 134
40-bit physical address support .................... 130, 135
unsupported in long mode ................................... 130
page-translation cache ............................................ 157
page-translation options .......................................... 129
page-translation tables .............................................. 25
accessed (A) ....................................................... 155

available to software (A VL) ................................. 156
dirty (D) ............................................................. 155
global page (G) ................................................... 156
hierarchy ............................................................ 128
no-execute .......................................................... 156
page directory entry (PDE) .................................. 131
page size (PS) ..................................................... 155
page table entry (PTE) ........................................ 131
page-attribute table (PAT) .................................... 156
page-directory pointer entry (PDPE) ....... 25, 131, 136
page-level cache disable (PCD) ............................ 155
page-level write-through (PWT) .......................... 155
page-map level-4 entry (PML4E) ................... 25, 139
page-map level-4 entry (PML5E) ......................... 139
physical-page base address .................................. 154
present (P) .......................................................... 154
read/write (R/W) ................................................. 154
translation-table base address ............................... 153
user/supervisor (U/S) .......................................... 155
paging ......................................................... 7, 25, 126
See also PAE paging and non-PAE paging.
effect of segment protection ................................. 168
protection across translation hierarchy .................. 166
[AMD Public Use]Index 76724593—Rev. 3.41—June 2023 AMD64 Technology
protection checks ................................................ 161
supported translations ......................................... 128
paging enable (CR0.PG) .................................... 44, 129
activating long mode .................................... 129, 490
parameter count field ............................................... 97
PAT...................................................................... 553
See page-attribute table (PAT).
PAT bit .................................................................. 156
PAT register ............................................ 226, 712, 721
PAUSE ................................................................. 514
PCC bit ................................................................. 309
PCD bit .................................................. 132, 141, 155
PCE bit ................................................................... 49
PDE...................................................................... 131
PDPE ..................................................... 131, 502, 554
PE bit ...................................................................... 42
PE exception .................................................. 256, 259
PerfCntGlobalCtl ................................................... 415
PerfCtr registers ........ 410, 415, 417, 418, 716, 725, 726
PerfEvtSel registers .......................... 410, 716, 724, 725
performance counter .............................................. 178
performance counter enable (CR4.PCE) ..... 49, 178, 412
performance counter hardware support-detecting ...... 420
performance monitor counter interrupts ................... 631
performance optimization .................................. 22, 410
performance-monitoring counters
L2I_PerfEvtSeln ................................................. 419
NB_PerfEvtSeln ................................................. 418
overflow ............................................................ 421
PerfCntGlobalStatus ........................................... 415
PerfCtrn ............................................................. 411
PerfEvtSeln ........................................................ 412
starting and stopping ........................................... 421
PG bit .............................................................. 44, 129
PGE bit ................................................................... 49
physical address ................................................... 3, 24
as index into cache ............................................. 205
physical memory ....................................................... 4
physical-address extensions (CR4.PAE) ...25, 26, 48, 51, 
129, 139
See also PAE paging.
POP instruction ...................................................... 178
POPF .................................................................... 513
precise exceptions and interrupts ............................. 241
precision exception (PE) .................................. 256, 259
PREFETCH instruction .......................................... 209
present (P)
descriptor ...................................................... 90, 378
page-translation tables ........................................ 154
principle of locality ................................................ 157
priorities, interrupt ................................................. 263
privilege level ........................................................ 105probe, cache .................................................. 186, 193
during cache disable ............................................ 207
processor feature identification (rFLAGS.ID) ............. 55
processor halt ........................................................ 181
processor modes
16-bit ..................................................................... l
32-bit ..................................................................... l
64-bit ..................................................................... l
processor state ....................................................... 480
processor states ...................................................... 355
protected mode .......................................... liv, 14, 500
initial operating environment ............................... 486
protected-mode virtual interrupts (CR4.PVI) .............. 48
protection checks
adjusting RPL ..................................................... 181
call gate ............................................................. 114
checking access rights ......................................... 180
data segment ...................................................... 106
direct call, conforming ........................................ 111
direct call, nonconforming ................................... 109
enabling ............................................................... 74
far return ............................................................ 120
interrupt return ........................................... 276, 277
interrupt to higher privilege ................................. 273
limit check, 64-bit mode ...................................... 121
long mode changes ............................................... 27
long mode interrupt ............................................. 283
long mode interrupt return ................................... 286
stack segment ..................................................... 107
type check .......................................................... 123
verifying read/write access .................................. 180
protection domains ................................................. 540
protection enable (CR0.PE) .......................... 42, 74, 82
PS bit ............................................................ 130, 155
PSE bit .................................................................... 48
PSE paging .............................................................. 25
P-State .......................................................... 657, 671
control ....................................................... 657, 671
current limit register ............................................ 658
status register ..................................................... 659
PTE...................................................................... 131
PUSH instruction ................................................... 178
PUSHF ................................................................. 513
PVI bit .................................................................... 48
PWT bit ................................................. 132, 141, 155
Q
quadword ................................................................ liv
R
R bit........................................................................ 91
R/W bit ................................................................. 154
r8–r15 ................................................................... lviii
[AMD Public Use]768 IndexAMD64 Technology 24593—Rev. 3.41—June 2023
RA1........................................................................ liv
RAX ..................................................................... 501
rAX–rSP ............................................................... lviii
RAZ ....................................................................... liv

Q
R
RdMem, MTRR type field ................................. 61, 231
RDMSR ................................................... 59, 178, 517
RDP field .............................................................. 362
RDPMC ........................................................... 49, 513
RDPMC instruction ............................................... 178
RDTSC ....................................... 48, 64, 178, 422, 513
RDTSCP ..................................... 48, 64, 179, 422, 514
read hit .................................................................. 186
read miss ............................................................... 186
read only guest page tables ..................................... 550
read ordering ......................................................... 209
read/write (R/W)
page-translation tables, bit in ............................... 154
readable (R), code segment ....................................... 91
real address ............................................................. 10
real address mode. See real mode
real mode ...................................................... liv, 4, 14
registers
See also entries for individual registers.
control registers .............................................. 29, 40
CR0..................................................................... 41
CR2................................................................... 255
CR3................................................ 25, 45, 131, 140
CR4..................................................................... 46
CSTAR .............................................................. 175
debug registers .............................................. 29, 391
debug-extension MSRs ......................................... 63
descriptor-table registers ................................. 26, 76
eAX–eSP ............................................................ lvii
EFER ................................................. 29, 55, 67, 69
eFLAGS ............................................................. lvii
eIP..................................................................... lvii
FPR............................................................ 347, 349
FS and GS ............................................................ 80
GPRs ................................................................... 28
HWCR ................................................................ 70
IBS fetch control ................................................ 425
IbsBrTarget ........................................................ 435
IbsDcLinAd ....................................................... 434
IbsDcPhysAd ..................................................... 435
IbsFetchCtl ........................................................ 425
IbsFetchLinAd ................................................... 427
IbsFetchPhysAd ................................................. 427
IbsOpCtl ............................................................ 429IbsOpData1 ........................................................ 431
IbsOpData2 ........................................................ 432
IbsOpData3 ........................................................ 432
IbsOpRip ........................................................... 430
last x87 data pointer ............................. 347, 349, 362
last x87 instruction pointer ................... 347, 349, 361
LSTAR .............................................................. 175
machine-check MSRs .......................... 64, 65, 66, 67
MCG_CAP ........................................................ 300
MCG_CTL ......................................................... 302
MCG_STATUS .................................................. 301
MCi_ADDR ....................................................... 310
MCi_CTL .......................................................... 306
MCi_MISC ........................................................ 310
MCi_STATUS .................................................... 307
memory-type range register (MTRR) ........ 29, 63, 217
MMX ................................................................ 345
model-specific registers (MSRs) ............................ 29
MTRR, fixed range ............................................. 218
MTRR, variable range ......................................... 220
MTRRfix4K ....................................................... 219
MXCSR ............................................................. 345
PerfCntGlobalCtl ................................................ 415
PerfCntGlobalStatus ........................................... 416
PerfCntGlobalStatusClr ....................................... 418
PerfCntGlobalStatusSet ....................................... 417
performance-monitoring MSRs .............................. 64
r8–r15 ................................................................ lviii
rAX–rSP ............................................................ lviii
rFLAGS ................................................. lviii, 28, 51
rIP....................................................................... lix
rSP...................................................................... 29
segment registers .................................................. 79
SSE registers ........................................................ 28
STAR ................................................................. 175
SYSENTER_CS ................................................. 176
SYSENTER_EIP ................................................ 176
SYSENTER_ESP ............................................... 176
system-linkage MSRs ........................................... 62
task-priority register (CR8) ....................... 38, 51, 266
[AMD Public Use]Index 76924593—Rev. 3.41—June 2023 AMD64 Technology
TOP_MEM ................................................... 61, 235
TOP_MEM2 ................................................. 61, 235
x87 FCW ............................................ 347, 349, 361
x87 floating-point processor state ........................ 346
x87 FSW ..................................... 345, 347, 349, 361
x87 FTW ..................................... 346, 347, 349, 361
x87 opcode ......................................... 347, 349, 361
XMM registers ................................................... 344
relative .................................................................... liv
replacement, cache-line .......................................... 186
replicated state ....................................................... 548
reserved ................................................................... lv
reset...................................................................... 479
processor state .................................................... 480
RESET# signal ...................................................... 479
resume flag (rFLAGS.RF) ......................... 54, 248, 407
RET instruction ..................................................... 120
from 64-bit mode ................................................ 121
long mode ..................................................... 33, 120
popping null selector, 64-bit mode ....................... 121
stack switch ....................................................... 120
retire, instruction ................................................... 187
revision history .................................................... xxxv

REX prefix .............................................................. 30
RF bit ..................................................................... 54
RFLAGS ............................................................... 501
rFLAGS ............................................................ 28, 51
alignment check (AC) .................................... 54, 257
I/O privilege level field (IOPL) .............................. 53
interrupt flag (IF) ........................................... 53, 178
nested task (NT) ............................................ 53, 386
processor feature identification (ID) ....................... 55
resume flag (RF) ................................... 54, 248, 407
trap flag (TF) ....................................................... 53
virtual interrupt (VIF) .................................... 54, 288
virtual interrupt pending (VIP) ........................ 55, 288
virtual-8086 mode (VM) ....................................... 54
rFLAGS register .................................................... lviii
RIP....................................................................... 501
rIP.......................................................................... 28
rIP register .............................................................. lix
RIP-relative address ................................................. 31
RIP-relative addressing ............................................. lv
RIPV bit ................................................................ 302
RPL......................................................... 78, 106, 368
adjusting ............................................................ 181
in call gate protection .......................................... 115
in far return ........................................................ 120
in IRET instruction ............................................. 276
in protecting conforming CS ................................ 112
in protecting nonconforming CS .......................... 110in stack segment protection .................................. 108
RSM ...................................................... 323, 339, 513
RSP...................................................................... 501
rSP.......................................................................... 29
call gate stack switch ........................................... 117
implicit reference .................................................. 31
S
S bit................................................................ 90, 378
SBZ......................................................................... lv
SCE bit ................................................................... 56
secure initialization ................................................ 546
secure loader (SL) .................................................. 556
secure loader (SL) image ........................................ 557
secure loader block ................................................. 557
secure MP initialization .......................................... 560
secure multi-key memory encryption ....................... 240
EncrKeyID ......................................................... 240
SecureNestedPagingEn bit ........................................ 62
security exception (#SX) ................................ 556, 562
segment base ........................................................... 89
segment limit ........................................................... 89
segment offset ............................................................ 2
segment registers ............................................... 76, 79
accessing ............................................................ 179
hidden portion ...................................................... 79
initializing unused registers ................................... 78
segmentation ....................................................... 5, 26
64-bit mode .......................................................... 75
combining with paging ............................................ 8
flat segmentation .......................................... 6, 9, 75
multi-segmented model ......................................... 74
segment-not-present exception (#NP) ...................... 253
segment-override prefix ............................................ 30
selector ..................................... 76, 77, 78, 86, 96, 368
selector index .......................................................... 78
self-modifying code ............................................... 205
SEOI Register ................................................ 626, 646
serializing instructions ............................................ 210
set............................................................................ lv
SEV-SNP instruction virtualization .......................... 617
SF exception .......................................................... 256
SFENCE ............................................................... 189
SFENCE instruction ............................................... 209
SGDT ........................................................... 180, 513
shadow page tables (SPTs) ...................................... 527
shadow stack registers .............................................. 65
shared state, MOESI ............................................... 192
shut down .............................................................. 251
SIDT ............................................................. 180, 513
SIMD floating-point exception (#XF) .49, 258, 343, 344
[AMD Public Use]770 IndexAMD64 Technology 24593—Rev. 3.41—June 2023
single-step
all instructions ............................................. 390, 407
control-transfers .......................................... 390, 409
SKINIT .................................................. 514, 546, 556
SL abort ................................................................ 560
SLDT ............................................................ 180, 513
SMBASE register .................................................. 325
SMI...................................................................... 323
external, synchronous ......................................... 536
internal, synchronous .......................................... 536
xternal, asynchronous ......................................... 537
SMM .................................................................... 323
SMM interrupts ..................................................... 334
SMM revision identifier ......................................... 330
SMM state-save area .............................................. 326
SMM_CTL MSR ................................................... 584
SMRAM ............................................................... 324
SMRAM state-save area ......................................... 326
SMSW .................................................................. 512
SMSW instruction ................................................. 177
SMT protection ..................................................... 616
specific EOI (SEOI) ................. 645, 647, 649, 650, 652
speculative execution ............................................. 187
Spurious Interrupts ................................................. 633
SS register ........................................................ 80, 501
SS.SEL ................................................................. 501
SSE Instructions
subset support .................................................... 341
SSE instructions
enabling ...................................................... 169, 343
YMM/XMM registers .................................... 28, 344
SSM Containerization ............................................ 748
stack exception (#SS) ............................................. 253
stack pointers
in 64-bit TSS ...................................................... 375
stack segment .................................................... 80, 92
privilege checks .................................................. 107
stack switch
call gate ............................................................. 117
call gate, long mode ....................................... 33, 118
interrupt ............................................................. 272
interrupt return ............................................ 276, 277

interrupt, long mode ............................................. 37
stack-fault exception (SF) ....................................... 256
STAR register ......................................... 175, 714, 719
state switch ........................................................... 499
status word ............................................................ 177stepping ID field .................................................... 483
STGI ............................................................. 514, 529
STI instruction ....................................................... 178
sticky bits ................................................................. lv
store ordering ........................................................ 209
STR...................................................................... 513
STR instruction ...................................................... 180
SVM ..................................................................... 536
SVM support ......................................................... 536
SVME bit ................................................................ 57
SWAPGS instruction .............................................. 176
SYSCALL Flag Mask register ................................. 175
SYSCALL, SYSRET instructions ..................... 56, 174
SYSCFG register ...................................... 60, 716, 721
HostMultiKeyMemEncrModeEn ........................... 62
HostMultiKeyMemEncrModeEn bit ..................... 240
MtrrFixDramEn ............................................ 61, 232
MtrrFixDramModEn ..................................... 61, 232
MtrrTom2En ...................................................... 237
MtrrVarDramEn ........................................... 61, 237
SecureNestedPagingEn ......................................... 62
Tom2ForceMemTypeWB ...................................... 61
SYSENTER_CS register ......................... 176, 711, 720
SYSENTER_EIP register ........................ 176, 711, 720
SYSENTER_ESP register ........................ 176, 711, 720
SYSENTER, SYSEXIT instructions ........................ 176
illegal in long mode ............................................ 176
SYSGFG register
MemEncryptionModeEn ....................................... 62
system call and return ............................................. 173
system data structures ............................................... 17
system management interrupt (SMI) ......... 323, 333, 536
system management mode (SMM) ............... 15, 24, 536
leaving ............................................................... 339
long mode differences ......................................... 323
operating environment ........................................ 333
revision identifier ................................................ 330
saving processor state .......................................... 336
SMBASE register ............................................... 325
SMRAM ............................................................ 324
state-save area, AMD64 architecture .................... 326
state-save area, legacy ......................................... 329
system registers ....................................................... 15
system segment ............................................ 27, 89, 94
ignored fields in 64-bit mode ............................... 100
illegal types in long mode ...................................... 99
long mode ............................................................ 99
type field .............................................................. 94
system-call extension (EFER.SCE) ............................ 56
system-linkage MSRs ....................................... 62, 175
[AMD Public Use]Index 77124593—Rev. 3.41—June 2023 AMD64 Technology
T
T bit...................................................................... 373
table indicator, selector ............................................. 78
tagged TLB ........................................................... 498
task gate .................................................................. 95
in task switching ................................................. 384
long mode .......................................................... 103
Task Register (TR) ................................................... 76
task register (TR) ................................................... 369
selector .............................................................. 368
task switch ..................................................... 365, 379
disabled in long mode ........................................... 38
lazy context switch ........................................ 43, 364
nesting tasks ....................................................... 386
preventing recursion ........................................... 387
task switched (CR0.TS) ..................................... 43, 178
task, execution space .............................................. 365
task-priority register (CR8) .......................... 38, 51, 266
task-state segment (TSS)
descriptor ........................................................... 368
dynamic fields .................................................... 373
I/O-permission bitmap ................................. 373, 376
interrupt-redirection bitmap ................................. 374
interrupt-stack table ............................................ 376
legacy 32-bit ...................................................... 371
link field ............................................................ 386
software-defined fields ........................................ 373
stack pointers .............................................. 373, 375
static fields ......................................................... 373
TCE bit ................................................................... 57
TF bit ...................................................................... 53
Thermal Sensor ..................................................... 621
Thermal Sensor Interrupts ...................................... 632
TI bit ............................................................... 78, 368
time-stamp counter ......................................... 178, 422
time-stamp disable (CR4.TSD) .................. 48, 178, 422
TLB................................................ 156, 157, 500, 501
explicit invalidation ............................. 159, 182, 183
implicit invalidation ............................................ 159
TLB Control .......................................................... 527
TLB entry upgrades ............................................... 160
TLB flush .............................................................. 528
TLB_CONTROL ................................................... 528
Tom2ForceMemTypeWB bit .................................... 61
top of memory ....................................................... 235
top of memory, virtual ............................................ 607
TOP_MEM register ........................... 61, 235, 716, 721
TOP_MEM2 register .......................... 61, 235, 716, 721
TPM ..................................................................... 558
TPR register ............................................... 38, 51, 266TR register ............................................. 366, 369, 513
translation lookaside buffer (TLB) ........................... 157
trap....................................................................... 242
trap flag (rFLAGS.TF) ............................................. 53
trap gate .......................................................... 95, 280
Trigger Mode Register ............................................ 641
Trusted Platform Module (TPM) ............................. 556
trusted software ..................................................... 556
TS bit ...................................................................... 43
TSC register ........................................... 422, 711, 724
TSD bit ................................................................... 48
TSS.......................................................... lvi, 366, 371
TSS descriptor ....................................................... 366
TSS selector .................................................... 96, 366
type check ............................................................. 123
Type field ................................................. 90, 369, 378
U
U/S bit .................................................................. 155
UAIE bit ................................................................. 58
UC bit ................................................................... 309
UC memory type .................................................... 196

U
UD2 instruction ..................................................... 249
UE exception ................................................. 256, 259
uncacheable (UC-), memory type ............................ 227
underflow ................................................................ lvi
underflow exception (UE) ............................... 256, 259
user segment ............................................................ 88
user/supervisor (U/S)
V
V_IGN_TPR ......................................................... 533
V_INTR_MASKING ............................................. 532
V_INTR_PRIO ...................................................... 533
V_INTR_VECTOR ................................................ 533
V_IRQ .......................................................... 502, 533
V_TPR ................................................... 502, 532, 533
V AL bit ................................................................. 310
Variable-range IORRs ............................................ 233
vector ...................................................................... lvi
vector, interrupt ...................................................... 244
VERR instruction ................................................... 180
VERW instruction .................................................. 180
VIF bit .................................................................... 54
VIP bit .................................................................... 55
virtual #INTR ........................................................ 533
virtual address ..................................................... 3, 24
virtual APIC register access behavior ....................... 565
virtual APIC register accesses ................................. 565
virtual interrupt (rFLAGS.VIF) ......................... 54, 288
[AMD Public Use]772 IndexAMD64 Technology 24593—Rev. 3.41—June 2023
virtual interrupt pending (rFLAGS.VIP) ............. 55, 288
virtual interrupts ............. 53, 54, 55, 287, 288, 498, 535
virtual interrupts, protected mode ............................ 290
virtual machine control block (VMCB) .................... 500
virtual machine monitor ......................................... 497
virtual memory .......................................................... 3
virtual-8086 mode .............................................. lvi, 14
interrupt to protected mode .................................. 278
interrupts ........................................................... 277
virtual-8086 mode (rFLAGS.VM) ............................. 54
virtual-8086 mode extensions (CR4.VME) ......... 47, 287
VM bit .................................................................... 54
VM_HSA VE_AREA ............................................. 501
VM_SA VE_PA MSR ............................................. 585
VMCB .................................................................. 500
A VIC fields ........................................................ 570
NMI virtualization .............................................. 535
virtual interrupt control word ............................... 569
VME .................................................................... 287
VME bit ........................................................... 47, 277
VMLOAD ............................................................. 514
VMM ................................................................... 497
VMMCALL ................................................... 514, 530
VMPL
permission mask ................................................. 606
VMPL supervisor shadow stack .............................. 607
VMPLEn bit ............................................................ 62
VMRUN ................................................ 498, 500, 514
VMSA VE .............................................................. 514
W
W bit ...................................................................... 93
WAIT/FWAIT instruction ......................................... 42
WB memory type .................................................. 197
WBINVD ........................................ 181, 182, 209, 514
WC memory type .................................................. 197
WC+ ..................................................................... 553
world switch .......................................................... 497
WP bit .................................................................... 43
WP memory type ................................................... 197
writable (W), data segment ....................................... 93
write buffer .................................................... 186, 201
emptying ............................................................ 201
write hit ................................................................ 186
write miss .............................................................. 186
write ordering ................................................. 188, 209
write protect (CR0.WP) ............................................ 43
write-back (WB), memory type ............................... 197
writeback, cache line .............................................. 186
write-combining buffer .................................... 186, 202
emptying ............................................................ 202
write-combining plus memory type ......................... 197write-though (WT)
memory type ...................................................... 197
WrMem, MTRR type field ................................ 61, 231
WRMSR .................................................. 59, 178, 517
WT memory type ................................................... 197
X
x2A VIC ................................................................. 582
x87 control word ..................................... 347, 349, 361
x87 data pointer register .......................... 347, 349, 362
x87 environment .................................................... 349
x87 floating-point instructions
initializing .......................................................... 483
processor state .................................................... 346
x87 instruction pointer register ................. 347, 349, 361
x87 opcode register ................................. 347, 349, 361
x87 status word ................................ 345, 347, 349, 361
x87 tag word .................................... 346, 347, 349, 361
FXSA VE format ................................................. 362
XMM registers ...................................................... 344
XSS Register ........................................................... 66
Y
YMM states ........................................................... 357
Z
ZE exception ................................................. 256, 259
zero extension .................................................... 30, 31
zero-divide exception (ZE) ............................. 256, 259
[AMD Public Use] 
Copyright © 2023 Intel Corporation. All rights reserved.   
 
Linux* Stacks for Intel® T rust Domain 
Extension 1.0 
 
v0. 11 
August 2023  
 
Document Number: 355388 -001  
  
2       Document Number: 355388 -001  
 
Contents  
1 Introduction  ................................ ................................ ................................ ..............................  8 
1.1 Overview  ................................ ................................ ................................ .............................  8 
1.2 Terminology  ................................ ................................ ................................ ......................  11 
2 Install ................................ ................................ ................................ ................................ ..........  13 
2.1 Hardware  ................................ ................................ ................................ ...........................  13 
2.2 BIOS  ................................ ................................ ................................ ................................ .... 14 
2.3 Components  ................................ ................................ ................................ .....................  16 
2.4 Building Stacks  ................................ ................................ ................................ ................  18 
2.4.1  Build Packages  ................................ ................................ ................................ .........  18 
2.4.2  Create Guest Image  ................................ ................................ .............................  20 
2.5 Install IaaS Host  ................................ ................................ ................................ ..............  22

2.5 Install IaaS Host  ................................ ................................ ................................ ..............  22 
2.5.1  Install Packages by Manual  ................................ ................................ ..................  23 
2.5.2  Deploy via Ansible  ................................ ................................ ................................ ..24 
2.5.3  Reboot with the Intel TDX kernel  ................................ ................................ ......  26 
3 Manage the TD guest  ................................ ................................ ................................ ..........  27 
3.1 Overview  ................................ ................................ ................................ ...........................  27 
3.2 Boot TD Guest  ................................ ................................ ................................ .................  31 
3.2.1  Launch via QEMU  ................................ ................................ ................................ .... 31 
3.2.2  Launch via  Libvirt  ................................ ................................ ................................ ... 33 
3.3 Secure Boot  ................................ ................................ ................................ ....................  34 
3.4 Use VirtIO Device  ................................ ................................ ................................ ..........  37 
3.5 Full  Disk Encryption  ................................ ................................ ................................ ......  39 
3.5.1  Workflow  ................................ ................................ ................................ ...................  39 
3.5.2  Prepare Encryption Image ................................ ................................ ....................  41 
4 Measurement & Attestation  ................................ ................................ .............................. 42 
4.1 TEE, TCB, Quote ................................ ................................ ................................ ............ 42 
4.2 TDX Measurement  ................................ ................................ ................................ .......  43    
3       Document Number: 355388 -001  
 
4.2.1  TD Report  ................................ ................................ ................................ ................  43 
4.2.2  MRTD and RTMR  ................................ ................................ ................................ .. 43 
4.2.3  Pre -Boot Measurement  ................................ ................................ .......................  44 
4.2.4  PyTdxMeasure Tool  ................................ ................................ .............................  45 
4.2.5  Linux Runtime Measurement  ................................ ................................ ............  46 
4.3 Attestation  ................................ ................................ ................................ .......................  47 
4.3.1  Overview  ................................ ................................ ................................ ...................  47 
4.3.2  Set Up DCAP Repository on Host  ................................ ................................ ... 49 
4.3.3  Set Up PCCS on Hos t ................................ ................................ ..........................  50 
4.3.4  Set Up Quote Generation Service on Host  ................................ ....................  52 
4.3.5  Generate Quote in TD  ................................ ................................ ..........................  54 
4.3.6  Verify TD Quote on Host  ................................ ................................ .....................  56 
4.4  Use Intel Project Amber  ................................ ................................ .............................. 58 
4.4.1  Overview  ................................ ................................ ................................ ................... 58 
4.4.2  Installation  ................................ ................................ ................................ ................ 58 
4.4.3  Example Usage  ................................ ................................ ................................ .......  59 
5 Validation  ................................ ................................ ................................ ................................ . 61 
5.1 Overview  ................................ ................................ ................................ ............................  61 
5.2 PyCloudStack  ................................ ................................ ................................ .................  62 
5.2.1  Overview  ................................ ................................ ................................ ...................  62 
5.2.2  Installation  ................................ ................................ ................................ ...............  64 
5.2.3  Example ................................ ................................ ................................ ....................  64 
5.3 Intel TDX Tests  ................................ ................................ ................................ ...............  66 
5.3.1  Overview  ................................ ................................ ................................ ...................  66 
5.3.2  Prerequisites ................................ ................................ ................................ ............ 68 
5.3.3  Setup Environment  ................................ ................................ ...............................  69 
5.3.4  Run Tests  ................................ ................................ ................................ ..................  70 
6 Develop & Debug  ................................ ................................ ................................ ..................  72 
6.1 Override the Intel TDX module  ................................ ................................ ..................  72    
4       Document Number: 355388 -001  
 
6.2 Off -TD Debug via GDB from the Host  ................................ ................................ .... 74 
6.3 Check Memory Encryption  ................................ ................................ .........................  76 
6.4 Run Intel A MX workload within TDX Guest  ................................ ...........................  77 
7 Disclaimer  ................................ ................................ ................................ ..............................  80 
8 References ................................ ................................ ................................ .............................. 82 
 
5       Document Number: 355388 -001  
 
Figures  
FIGURE 1: INTEL® TDX ................................ ................................ ................................ ................................ .................  8 
FIGURE 2:  INTEL TDX  COMPONENT INTERFACES  ................................ ................................ ................................ ................  9 
FIGURE 3: LINUX STACK FOR INTEL TDX ................................ ................................ ................................ .........................  10 
FIGURE 4: 8+0  DIMM  POPULATION FOR INTEL TDX................................ ................................ ................................ .........  13 
FIGURE 5: 16+0  DIMM  POPULATION FOR INTEL TDX ................................ ................................ ................................ .......  14 
FIGURE 6: BIOS  SETTINGS FOR INTEL TDX ................................ ................................ ................................ ......................  15 
FIGURE 7: LINUX STACK FOR INTEL TDX  OVERVIEW  ................................ ................................ ................................ ...........  16 
FIGURE 8: END-TO-END HOST AND GUEST STACK FOR LINUX AND INTEL TDX ................................ ................................ ..........  18 
FIGURE 9:  BUILD PROCESS FOR INTEL TDX  PACKAGES  ................................ ................................ ................................ ........  19 
FIGURE 11: CREATE INTEL TDX  UBUNTU GUEST IMAGE  ................................ ................................ ................................ ..... 21 
FIGURE 10:  CREATE INTEL TDX  RHEL  GUEST IMAGE  ................................ ................................ ................................ .........  22 
FIGURE 12: DEPLOY TDX  HOST STACK VIA ANSIBLE  ................................ ................................ ................................ ...........  25 
FIGURE 13: TD GUEST BOOT PROCESS  ................................ ................................ ................................ ...........................  27

FIGURE 13: TD GUEST BOOT PROCESS  ................................ ................................ ................................ ...........................  27 
FIGURE 14: DETAILED BOOT FLOW FOR DIFFERENT TD BOOT  ................................ ................................ ................................  29 
FIGURE 15: ENABLE SECURE BOOT ................................ ................................ ................................ ................................  34 
FIGURE 16: TDX  GUEST ATTACK SURFACE  ................................ ................................ ................................ ......................  38 
FIGURE 17: FULL DISK ENCRYPTION IN TDX  GUEST ................................ ................................ ................................ ...........  39 
FIGURE 18: MEASUREMENT AND ATTESTATION FOR TEE ................................ ................................ ................................ .... 42 
FIGURE 19: INTEL TDX  MEASUREMENT  ................................ ................................ ................................ .........................  43 
FIGURE 20: TD MEASUREMENT PROCESS  ................................ ................................ ................................ .......................  45 
FIGURE 21: ENABLE IMA  EXTEND HASH TO RTMR  ................................ ................................ ................................ ...........  46 
FIGURE 22: INTEL TDX  ATTESTATION FLOW ................................ ................................ ................................ ....................  49 
FIGURE 23: SETUP PCCS  ................................ ................................ ................................ ................................ ............  51 
FIGURE 24: SET UP DCAP  SOFTWARE ON THE TDX  HOST ................................ ................................ ................................ .... 53 
FIGURE 25: QUOTE GENERATION ................................ ................................ ................................ ................................ .. 54 
FIGURE 26: APPROACHES TO GENERATE INTEL TDX  QUOTE  ................................ ................................ ................................  55 
FIGURE 27: VERIFY QUOTE ................................ ................................ ................................ ................................ ..........  57 
FIGURE 28: INTEL TDX  E2E  FULL STACK VALIDATION  ................................ ................................ ................................ ........  61 
FIGURE 29: PYCLOUD STACK FRAMEWORK  ................................ ................................ ................................ ......................  62 
FIGURE 30: VALIDATION SCENARIOS FOR VMM  AND LIBVIRT  ................................ ................................ ..............................  63 
FIGURE 31: ABSTRACT COMMON OPERATIONS FOR CLOUD STACK  ................................ ................................ ........................  63 
FIGURE 32: BIOS  SEARCH TDX  MODULE FROM ESP ................................ ................................ ................................ .........  72 
FIGURE 33: OFF-TD DEBUG VIA GDB ................................ ................................ ................................ ............................  74 
 
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TABLES  
TABLE 1:  INTEL TDX  BIOS  CONFIGURATIONS  ................................ ................................ ................................ ..................  15 
TABLE 2: LINUX STACK FOR INTEL TDX  COMPONENTS  ................................ ................................ ................................ ........  16 
TABLE 3: BOOT TYPES FOR TD GUEST ................................ ................................ ................................ ............................  28 
TABLE 4: START -QEMU .SH PARAMETERS  ................................ ................................ ................................ .........................  31 
TABLE 5: RTMR  DEFINITIONS  ................................ ................................ ................................ ................................ ...... 44 
TABLE 6: LINUX STACK FOR INTEL TDX  VALIDATIONS  ................................ ................................ ................................ .........  61 
TABLE 7: TDX  STACK TESTS ................................ ................................ ................................ ................................ .........  66 
 
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Revision H istory  
Revision 
Number  Description  Date  
0.8 Initial Release  1st May  
2023  
0.9  • Add  the reference tool of check -tdx -host.sh  
• Add chapter 4.2.5 Linu x Runtime Measurement via 
IMA (Linux Integrit y Measurement Architecture)  
• Add chapter 3.5 Full Disk Encryption  
• Add chapter 4.4 Use Intel Project Amber  
• Complete  the incomplete steps for  Secure boot  
• Add chapter 6.3 Check Memory Encryption  27th May  
2023  
0.10  • Use $ for all command code  
• Normalize the “sud o” usage, use “sudo s u” and 
simple root access used  in multiple steps  
• Add more ter minology like TCG, PCR, VMM, etc  
• Refine the build step for individual package build and 
full repo build  
• Update the new “Ubuntu Guest Image ” tool  
• Add ansible deployment tool  27th June 
2023  
0.11  • Update BIOS settings  
• Add a note about Amber client packages installation  
• Adjust manual installation section  to include grub 
config and default kernel setting  
• Update guest image tool section  
• Update description o f Remote attestation  
• Add more terminology  like QVL, QvE  
• Fix typo  11 th 
August 
2023  
     
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1.1 Overview  
Intel® Trust Domain Extension (Intel® TDX)  refers to an Intel technology that 
extends virtual machine extensions ( VMX) and Intel® Total Memory E ncryption – 
Multi -Key ( Intel® TME -MK) with a new kind of virtual machine guest called a trust 
domain (TD).  A TD runs in a CPU mode that is designed to protect the 
confidentiality of its memory contents and its CPU state from any other software, 
including t he hosting virtual machine monitor  (VMM ) [1] 
  
Figure 1: Intel® TDX  
The white paper or specifications for Intel TDX can be found at Intel® Trust Domain 
Extensions , the major components  interfaces are defined in t he specifications in 
Figure 2: : Intel TDX Component Interfaces . 
   
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Figure 2:  Intel TDX Component Interfaces  
 
Linux * Stack s for Intel® TDX is  an e nd-to-end hypervisor cloud stack including the 
Infrastructure as a Service ( IaaS ) and Platform as a Service ( PaaS ) components to 
produce the following minimal use cases:  
• Launch Intel® TDX g uest  VM  to run general computing  work loads . 
• Do l aunch -time measurement  within the  Intel® TDX guest  VM . 
• Do runtime attestation  with the quote generated by Intel® Software Guard 
Extensions (Intel® SGX) -based quote generation service (QGS) on the IaaS 
host . 
   
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Figure 3: Linux Stack for Intel TDX  
The open -source code for Linux Stack for Intel TDX  can be found at : 
https://github.com/intel/tdx -tools .  
NOTE : tdx -tools has multiple release tags . Please make sure to use  the cor rect 
release tag which matche s the  release  version . The Release tag and kernel version   
mapping ca n be  found in  tdx -tools  wiki. 
This document introduces : 
• The deployment, cloud stack test , and other common use s for those  who 
want to validate confidential workload s or tune performance.  
• The d ebug an d development methods for those  who want to integr ate stack 
in their IaaS/PaaS framework . 
The OS supported in the document are Ubuntu 22.04 and RHEL 8.7.   
   
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1.2 Terminology  
TERM  DESCRIPTION  
ACM  Authenticated Code  Module  
CFV  Configuration Firmware Volume  
CMR  Convertible Memory Ranges  
CPLD  Complex Progra mmable L ogic  Device  
CRB  Customer  Reference Board  
DCAP  Data Center Attestation Primitives  
DIMM  Dual In-line Memory Module  
ECC  Error Correction Code memory  
ESP  EFI System Partition  
FV  Firmware Volume  
GPA  Guest Physical Address  
GVA  Guest Virtual Address  
HVC  Hypervisor Virtual Console  
IFWI  Integrated Firmware Image  
IBV  Independent BIOS Vendor  
Intel SGX  Intel® Software Guard Extension s (Intel® SGX)  
Intel TDX  Intel® Trust Domain Extension  (Intel® TDX)  
LIV server  Live server is used for attestation with 
produc tion CPU SKUs  
LUKS  Linux Unified Key Setup  
MOK Machine Owner Key  
MRTD  Measurement of Trust Domain  Firmware  
OVMF  Open -source Virtual Machine Firmware  
PCR  Platform Configuration Register  
PCS  Provisioning Certification Service  
PCCS  Provisioning Certifi cate Caching Service  
PK/ KEK/DB  Platform Key/Key Exchange Key/Database Key  
QGS  Quote Generation Service  
QMP  QEMU  Monitor Protocol  
QVE  Quote Verification Enclave

QVE  Quote Verification Enclave  
QVL  Quote Verification Library  
RTMR  Runtime Measurement Register  
SBX server  Sandbox s erver is used for attestation with pre -
production CPU SKUs  
SEAM  Secure  Arbitration Mode  
SVN  Security Version Number     
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TCB  Trusted -Computing Base  
TCG  Trust ed Computing Group  
TDVF  Trusted Domain Virtual Firmware  
TDVM  A TD guest VM  
TDX -CI TDX Crypto Inte grity  
TDX -LI TDX Logical Integrity  
VMM  Virtual Machine Monitor  
     
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2 Install  
2.1 Hardware  
Linux Stack s for Intel TDX  needs the following hardware  support  that enables Intel 
TDX : 
• CPU Processor SKU . Contact  Intel sales represent ative  for details.  
• Board  configurations via hardware jumper or CPLD  (complex program mable 
logic  device ). Contact your ODM/OEM vendor.   
• DDR5 DIMM with  the type of 10 × 4 ECC  (error correction code memory )  
• DDR5 RDIMMs  with integrity protection . 
• DIMM  (Dual in-line memory module ) population : It is  recommended  that all 
channel 0 slots  have at least 1 DIMM populated. There are a total of 8 DIMMs 
per socket . DIMM population must be symmetric across the integrated 
memory controllers.  
 
Figure 4: 8+0 DIMM Population  for Intel TDX  
Intel TDX  also supports  the full DIMM  population 16+0 as follows:  
   
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Figure 5: 16+0 DIMM Population for Intel TDX  
 
2.2  BIOS  
BIOS configuration s are needed to support Intel TDX. Contact  an Intel sal es 
represent ative  or IBV ( independ ent BIOS vendor)  for details.  The following settings 
are examples for reference . 
 
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NOTE: Below diagram is jus t an example . The configuration or the menus might be 
different on your BIOS. Contact the IBV or OEM/ODM f or the correct settings.  
 
Figure 6: BIOS settings for Intel TDX  
  Table 1:  Intel TDX BIOS Configurations  
BIOS Setting  Notes  
Vol atile Memory = 1LM  Intel TDX and CMR  (Convertible Memory Ranges)  logical 
integr ity, isolation, and cryptographic  integrity are only 
available with directly attached DDR5 memory.  
NOTE: Please skip this setting  if it doesn’t exist  in BIOS 
menu . 
Total Memory Encryption 
(Intel TME) = Enable  Intel TDX technology depends on Intel® Total M emory 
Encryption  (Intel® TME) . 
(Intel TME) By pass = 
Auto  4th generation Intel Xeon Scalable processors  introduce 
an Intel TME bypass mode to allow memory  outside of 
Intel TME multi -tenant virtual machines, Intel SGX 
enclaves, and I ntel TDX trust domains to be unencrypted 
to improve the performance of nonconfidential software.  
Multi -Tenant (TME -MT) = 
Enable  128 Intel TME – Multi -Tenant encryption  keys.  
TDX Secure Arbitration 
Mode  Loader (SEAM 
Loader)  Loadin g Intel TDX module  from BIOS when it’s enabled.  
Memory Integrity  = Disable  4th generation Intel Xeon Scalable processor  E-stepping 
does not support Intel TDX -CI, but only support s Intel  
TDX -LI. 
Intel TDX = Enable  Intel TDX should be enabled . 
   
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TDX Key Spl it = <Non -zero 
Value)  Keys split between Intel TME multi -tenant and Intel TDX . 
Software Guard Extension  = 
Enable  Intel TDX depends on Intel SGX technology for hardware 
TCB and remote attestation . 
 
2.3  Components  
Linux Stack for Intel TDX  is a vertical end -to-end stack including  a series of 
components  which are  listed in Table 2: Linux Stack for Intel TDX  Components  
Table 2: Linux Stack for Intel TDX  Components . 
 
Figure 7: Linux Stack for Intel TDX overview  
There are multiple components in t he Linux stack for both the host and guest.  
Table 2: Linux Stack for Intel TDX  Components  
   
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Components  Description  Source  
Intel  TDX 
Module  An attested software module 
running in SEAM Root Mode . Intel Trust Domain Extensions  
TDX  Loader  A SEAM module intended 
to install an Intel TDX 
module int o SEAM range . Intel  Trust Domain Extensions  
Intel TDX Host 
Kernel  The host kernel with Intel TDX 
patches being upstreamed . https://github.com/intel/tdx/tree/kv
m 
Intel TDX  QEMU  QEMU  with Intel TDX patches 
being upstreamed . https://github.com/intel/ qemu -tdx  
 
Intel TDX  Libvirt  Libvirt with Intel TDX patches 
being upstreamed . https://github. com/intel/libvirt -
tdx/tree/for_ QEMU _upstream  
TDVF  Virtual firmware (aka OVMF) 
with Intel TDX features  already 
upstreamed . https://github.com/tianocore/edk2  
 
DCAP  Intel SGX -based DCAP ( data 
center attestation primitives) 
for the platform certificate 
after registration . https://github.com/intel/SGXDataC
enterAttestationPrimitives  
QGS  QGS provides the functionality 
of Intel TDX quo te generation 
within an Intel SGX -based 
quote enclave. It is part of the 
DCAP running on the IaaS host 
or legacy VM.  https://github.com/intel/SGXDataC
enterAttestationPrimitive s 
 
Intel TDX Guest 
Kernel  The guest kernel with  Intel  
TDX patches being 
upstreamed . https://github.com/intel/tdx/tree/g
uest -upstream  
Grub2  The bootloader grub2 with 
Intel TDX patches already 
upstr eamed . https://github.com/intel/grub -
tdx/tree/2.06 -upstream -v4 
 
Shim  The bootloader shim with Intel 
TDX patches already 
upstreamed . http s://github.com/intel/shim -tdx  
 
Intel TDX 
Attestation 
Agent  A sample  Intel  TDX attestation 
agent to call 
TDVMCALL.getQuote(). It is 
part of DCAP.  
 https://github.com/intel/SGXDataC
 
PyTdxMeasure  A Python measurement library 
that  dumps RTMR, the CCEL 
ACPI table , and verif ies the https://github.com/intel/tdx -tools  
    
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RTMR via replaying the TD 
event log.  
 
NOTE:  Some of the components have completed patch upstreaming such as Grub , 
Shim , and TDVF , while others are still in progress.   
2.4  Build ing  Stacks  
For an end -to-end stack setup and validation, tdx -tools  provides downstream 
patches and a build tool to construct t he whole stack in a few simple steps.   
The supported distro s’ version s are  as follows for both host and guest packages:  
• RHEL 8. x (Latest Version ) 
• Ubuntu 22.04  
 
Figure 8: End -to-End Host and Guest Stack for Linux  and  Intel TDX  
The en d-to-end stack building includes two steps  on any Linux development 
machine : 
• Step 1: Build  packages  
• Step 2: Create guest image  
 
2.4.1  Build Packages  
A build.sh  script  is provided by tdx -tools  to download the upstream source, apply 
Intel TDX patches from the dire ctory <build>/common , and do package build ing . 
   
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Note: When obtaining tdx -tools, p lease make sure to use the correct tag which 
matches the release version.   
 
Figure 9:  Build process for Intel TDX packages  
The kernel config  is provided  in the kernel package directory with Intel TDX 
configurations . For example, RHEL -8 will use the path  build/rhel -8/intel-mvp-
tdx-kernel/tdx -kernel.spec . All kernel config uration s have been optimized  for 
TDX  performance.  
Below is an example using Ubuntu 22.04 to build the entire repo with  all the  
packages.  
NOTE: The building process may take more than 1 hour or longer depending on the 
resource of building server.  
$ # Follow https://docs.docker.com/engine/install/  to setup Docker.  
$ # Add curre nt user into docker group  
$ sudo usermod -G docker -a $USER 
$ # Restart docker service  
$ sudo systemctl restart docker  
 
$ # Make sure you get the correct tag. Here is an example of getting 2023ww33 tag  
$ git clone git@github.com:intel/tdx -tools.git --branch 2023ww33  
$ cd build/ubuntu -22.04/ 
$ 
$ # Build the all packages via buil d-repo.sh, and running it within pkg -builder 
$ # container to avoid any issues of build environment  
$ ./pkg-builder build -repo.sh 
 
Below is an example of how to build individual packages on Ubuntu 22.04.  
   
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$ # If want to build individual package  like intel -mvp-tdx-kernel 
$ ./pkg-builder intel-mvp-tdx-kernel/build.sh   
 
After the packages have been built successfully, two repositories are generated.  
1. build/ubuntu -22.04/host_repo : includ es the  Intel TDX host kernel, Intel 
TDX QEMU , Intel TDX Libvirt , and TDVF.  
2. build/ubuntu -22.04/guest_repo  : includes  the Intel  TDX guest kernel, 
grub2 , and shim.  
2.4.2  Cre ate Gu est Image  
The Intel  TDX virtual machine requires guest images to be booted with an Intel TDX 
guest kernel ,  Intel TDX grub2 and shim packages for both  grub boot and secure 
boot.   
The  image creation process is a little different for the different distr os: 
• Ubuntu 22.04 guest image  
Ubuntu provides EFI enabled guest/cloud images at https://cloud -
images.ubuntu.com/  .  Use <tdx-tools>/build/ ubuntu-22.04/guest-

boot.   
image/create -ubuntu-image.sh  as follows:  
$ # Prerequisite: build the Ubuntu packages via build -repo.sh 
$ # Install dependencies  
$ sudo apt install libguestfs -tools 
 
$ cd build/ubuntu -22.04/guest -image 
$ 
$ # Install guest repo  packages in to guest image . Please provide guest repo  
$ # directory which is generated  in the Build Packages  chapter 
$ ./create-ubuntu-image.sh  -r $GUEST_REPO   
The $GUEST_REPO  is the path to guest repo, which has the following file hierarchy . 
  guest_repo/  
  |- all/ 
  |- amd64/ 
   
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Figure 10: Create Intel TDX Ubuntu Guest Image  
NOTE: The guest image can be further customized at <tdx-
tools>/build/ubuntu22. 04/guest -image : 
Usage: create -ubuntu-image.sh [OPTION]...  
Required  
-r <guest repo>           Specify the directory including guest packages, 
generated by build -repo.sh or remote repo  
Test suite  
-t                        Install test suite  
Optional  
-v <kernel version>       Specify the version of the guest kernel, like 5.19.17-
mvp29v4+4-generic of  
                          linux-image-unsigned -5.19.17-mvp29v4+4 -generic. If the 
guest repo is remote,  
                          the option is necessary.  
-a                        Auth file that will be placed in /etc/apt/auth.conf.d  
-h                        Show this help  
-f                        Force to recreate the output image  
-n                        Guest host name, default is "tdx -guest" 
-u                        Guest user name, default is "tdx"  
-p                        Guest password, default  is "123456"  
-s                        Specify the size of guest image  
-o <output file>          Specify the output file, default is tdx -guest-ubuntu-
22.04.qcow2. 
   
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                          Please make sure the suffix is qcow2. Due to permission 
considerati on, 
                          the output file will be put into /tmp/<output file>.  
-b                        Debug Mode  
                          - enable root login  
 
• RHEL  8.x  guest image  
The default  distro cloud image does not support an EFI schema . The  tdx-
tools  repository  provides <tdx-tools>/build/rhel -8/guest-
image/create -efi-img.sh to create a RHEL EFI guest image via the 
kickstart1 tool.  
Use  tdx-guest-stack.sh  to install  the  Intel TDX guest packages into the 
image  using the follow ing workflow . 
 
Fig ure 11:  Create Intel TDX RHEL guest i mage  
 
2.5 Install IaaS Host   
Perform t he following steps to deploy  the packages  on IaaS host.  
NOTE : Please d isable Intel TDX in  the BIOS  to install  the  Intel TDX packages . 
Before installing  the  Intel TDX host kernel , the distro default kernel may 
unintentionally cleanup  MTRR  (memory type range register)  for the  Intel TDX 
memory range . This will cause an MCHECK error . Once the Intel  TDX packages 
 
1 https://linuxhint.com/beginners -kickstart/   
   
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have been installed , set  the Intel TDX kernel as the default in grub, reboot, and 
enable Intel TDX in the BIOS.  
2.5.1  Install Packages  by Manual  
For Ubuntu 22.04 host  
• Install all Debian packages .  
$ # Build the DEB packages via the above  steps, the DEB packages will be generated  
$ # to <tdx -tools>/build/ubuntu -22.04/host_repo/  
$ cd host_repo  
$ sudo apt -y --allow-downgrades install ./*.deb  
• Add numa_balancing=disable  into grub menu.  
$ vi /etc/default/grub  
 
# Add "numa_balancing=disable " in GRUB_CMDLINE_LINUX_DEFAULT  
GRUB_CMDLINE_LINUX_DEFAULT=". . .  numa_balancing=disable"  
 
$ sudo update -grub 
• Set TDX kernel as default kernel . 
$ grep -A100 submenu /boot/grub/grub.cfg | grep menuentry | grep  <TDX kernel 
version>  
 
$ # Use the string in above o utput, such as " gnulinux -6.2.0-mvp4v1+2 - 
$ # generic-advanced -34db9317 -bf73-44c3-8425-2fa83446e8d5 " in  
$ # /etc/default/grub file as value of “GRUB_DEFAULT"  
 
# Below value is just an exmaple. Please do Not use it directly. Please us e the 
string from output of last command.  
GRUB_DEFAULT=" gnulinux -6.2.0-mvp4v1+2 -generic-advanced -34db9317 -bf73-44c3-8425-
2fa83446e8d5 " 
 
NOTE: Change the default string according to your TDX kernel version.  
 
For  RHEL 8. x host  
• Move the gen erated host repo to a directory that will be used in the repo file.  
$ sudo mkdir -p /srv/ 
$ 
$ # Build the RPM packages via above steps, the RPM package will be generated  
$ # in <tdx-tools>/build/ rhel-8/host_repo/  
$ sudo mv build/rhel -8/host_repo/  /srv/tdx -host 
   
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• Set  up the  host repository . Generate  the file /etc/yum.repos.d/tdx -host -
local.repo  and add the following content.  
$ cat /etc/yum.repos.d/tdx -host-local.repo  
[tdx-host-local] 
name=tdx -host-local  
baseurl=file:///srv/tdx -host 
enabled=1  
gpgcheck=0  
module_hotfixes=true  
• Add  the EPEL  repo . It provides the packages of capstone  and libcapstone  
required by Intel TDX QEMU .  
$ sudo dnf install https://dl.fedoraproject.org/pub/epel/epel -release-latest-
8.noarch.rpm  
• Install the host packages . 
$ sudo dnf install intel -mvp-tdx-kernel intel -mvp-tdx-qemu-kvm intel -mvp-ovmf 
intel-mvp-tdx-libvirt 
• If you get  an error about qemu -kvm  conflicts, remo ve the existing qemu -kvm  
package with the following command,  and then re -run the command above to 
install host  packages . 
$ sudo dnf remove qemu-kvm 
 
# Add "numa_balancing=disable " in GRUB_CMDLINE_LINUX  
GRUB_CMDLINE_LINUX=". . .  numa_balancing=disable"  
 
$ sudo grub2-mkconfig -o /boot/efi/EFI/redhat/grub.cfg  
$ ls /boot/vmlinuz* | grep <kernel -version>  
 
$ # Use output of above command, such as  
$ # "/boot/vmlinuz -6.2.0-tdx.v1.5.mvp7.el8.x86_64 " in the  
$ # below command  
 
$ sudo g rubby --set-default=/boot/vmlinuz -<kernel version>  
 
2.5.2  Deploy via Ansible  
Use the ansible  based “TDX Deployment Tool” to deploy the host stack  to multiple 
server node s or guest stack  to multiple TD VM s.    
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Figure 12: Deploy TDX host stack vi a Ansible  
NOTE: Current  Ansible script  only  support deployment on Ubuntu22.04.   
Before using the script there are a couple pre -requisites.  
1. Build the host *.deb repositories . Refer to section 2.4.1  Build Packages . The  
final built files will be at  <tdx-tools>/build/ubuntu -22.04/host_repo . 
2. Copy all *.deb packages to <tdx-tools>/deploy/tdx_stack/tdx_repo/  
$ cp build/ubuntu -22.04/host_repo/*.deb deploy/tdx_stack/tdx_repo/  
3. Prepare ansible inventory host file  and enable password -less login on all 
managed nodes , please refer tutorial .  
$ # The content of an example inventory file  
$ cat deploy/tdx_stack/ hosts 
tdx@10.0. 0.2 
tdx@10.0.0.3  
tdx@10.0.0.4  
 
$ # Enable the SSH password less login  
$  
$ ssh-copy-id tdx@10.0.0.2  
... 
$ ssh-copy-id tdx@10.0.0.3  
... 
$ ssh-copy-id tdx@10.0.0.4  
4. Setup  ansible docker  to create the build image  
$ ./docker -playbook.sh rebuild  
5. Run playbook in docker for auto deployment process on all managed nodes  
$ ./docker -playbook.sh -i hosts tdx_stack /tdx_host_install.yml -K 
   
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2.5.3  Reboot with the Intel TDX kernel  
After install ing  the  Intel  TDX kernel and host packages successful ly, reboot the 
system into the BIOS  menu  and enable Intel TDX. Refer to Section 2.2  on the BIOS 
settings . To verify that Intel TDX is enabled by using  the script  check -tdx -host.sh  
after  the system is booted. Alternatively, the below steps can also be used to 
determine that Intel TDX has been successfu lly enabled.  
• Check whether TDX Module is initial ized . The expected output is “TDX 
module initialized”.  
$ sudo dmesg | grep -i tdx 
... 
tdx: TDX module initialized.  
• Check Intel TME enable status ; expect a return code of 1. 
$ sudo rdmsr -f 1:1 0x982  
1 
• Check Intel TME max keys . 
$ sudo rdmsr -f 50:36 0x981  
• Check the  Intel SGX and MCHECK status , expect ing a code of 0. 
$ sudo rdmsr 0xa0  
0 
• Check the  Intel TDX Status , expect ing a code of 1. 
$ sudo rdmsr -f 11:11 0x1401  
1 
NOTE: All the above  checking  steps should be successful with expected result 
returned befor e moving forward to the next steps.  
• Check the number of  Intel  TDX keys . 
$ sudo rdmsr -f 63:32 0x87  
1 
• Check the information for the Intel TDX module . 
$ cat /sys/firmware/tdx/ tdx_module/*   
   
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3 Manage  the TD guest  
Like a normal virtual machine, a TD guest c an be launched  by QEMU  via command 
line or orchestrated  by Libvirt via XML  templates. This chapter introduce s how to

... 
1 
0 
1 
1 
   
line or orchestrated  by Libvirt via XML  templates. This chapter introduce s how to 
manage the lifecycle of a TD guest  for diverse boot s such as secure boot, direct 
boot, and grub boot.  
NOTE : Please make sure to use the  correct tag  of tdx -tools  which matches the 
release version.  
3.1 Overview  
You  can boot a TD guest either by using the  QEMU  command line or by using a 
Libvirt XML  template and virsh  commands. Libvirt translate s the  XML  template to 
QEMU  commands and cal ls qemu -kvm to complete the  VM boot. Similarly, you  can 
call qemu -kvm directly with parameters to boot a VM.  
The following diagram illustrates the  TD gues t boot type and boot process.  
 
Figure 13: TD Guest Boot Process  
The following table expla ins different boot types:  
   
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Table 3: Boot Type s for TD Guest  
Boot Type  Description  Differen ce from a non -
confidential VM  
Direct Boot  Boot the guest by explicitly specifying 
kernel binary via QEMU  launch ing  
parameter "-kernel ", specifying the 
initrd binary via QEMU  launching 
parameter  "-initrd ", specifying the  
kernel command via  QEMU  launching 
parameter  “-append ".  
Bootloaders, such as shim/grub are 
not involved in direct boot . No differences on QEM U 
launch parameters  for 
confidential VM , but 
requires TDVF/OVMF to do 
measured boot and record 
the measurement into 
RTMR (Runtime 
Measurement Register)  
register  
Grub Boot  Boot the guest without "-kernel " and 
"-append " in QEMU  launching 
params . The OVMF /TDVF search es 
for and start s the bootloader from 
ESP  No differ ences on QEMU  
launch parameters for 
confidential VM, but 
requires Intel TDX Grub2  to 
do measured boot and 
record the measurement 
into RTMR register  
Measured Boot  It is the process of measu ring and 
storing securely (i.e. using a TPM) the 
next stage object in the boot process 
by the UEFI BIOS, bootloader, kernel, 
etc.  The se cure register is a PCR 
register in a trusted 
computing group (TCG) -
defined trusted platform 
module (TPM) , while is 
RTMR in Intel TDX module  
Secure Boot  Secure boot is  a security standard 
developed by members of the PC 
industry to help make sure that a 
device boot  using only software that 
is trusted by the original equipment 
manufac turer (OEM) . The Secure 
boot certific ate should be protected  
by measured boot . The secure boot certificate 
can be enrolled  in runtime of 
guest VM for non -
confidential VM, while the 
secure boot must be 
enrolled in TDVF offline  for 
the consistent 
measurement  on MRTD  
(measurement of trust 
domain ) 
The detail boot flow for different TD boot methods can be found in Figure 14: 
Detailed  boot flow for different  TD boot     
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Figure 14: Detailed  boot flow for different  TD boot  
In Figure 14: Detailed  boot flow for different  TD boot : 
Measured Boot  
1. In OVMF, the image handler  DxeTpmMeasureBootHandler  will be triggered 
when loading EFI image via CoreLoadImageCommon() . 
2. In OVMF, DxeTpmMeasureBootHandler  will measure the object s like FV, 
QEMU  CFG, VMM Hob, Variable into TCG PCR Register . In TD guest, the 
measurement will also be extended  to RTMR register if vTPM does not exi st. 
3. In boot loader Shim X64.efi , TpmMeasureVariable () will measure the 
secure boot’s certificates into TCG PCR or TDX RTMR  register.  
4. Boot loader Grub X64.efi  measures kernel binary and cmdline, initrd binary 
and grub’s module into TCG PCR or TDX RTMR register.  
The mapping between TCG PCR register and RTMR is  
➢ PCR #1 , #7   RTMR #0 
➢ PCR #2~#6  RTMR #1  
➢ PCR #8~#15  RTMR #2  
Secure Boot  
1. In OVMF, the image handler DxeImage VerificationHandler  will be 
triggered when loading EFI image via CoreLoadImageCommon()  
   
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2. In OVMF, DxeImageVer ificationHandler  will use UEFI secure boot’s DB 
key verify the cert ificate from each of load EFI image.  
3. ShimX64.efi and GrubX64.efi will use UEFI secure boot’s DB key or Linux 
secure boot’s MoK (Machine Owner Key) to verify the certificate of kernel, 
kernel module etc.  
4. All certific ates , including UEFI secure boot and Linu x secure boot , are 
measured into TDX RTMR register.  
Direct Boot  
1. In direct boot path, the kernel binary is started and measured by 
TryRunning QEMUKernel() . 
2. In direct boot path, the kernel command and initrd are measured by the EFI 
stub of Linux kernel . 
Refer to the measure log for direct boot  for a sample of what the output should 
look like . 
Grub Boot  
1. In grub boot, ShimX64.efi will help bring the UEFI secure boot  to Linux secure 
boot . Normally UEFI secure boot will use MSFT UEFI certificat es3. But here it 
needs  a new key to sign customized kernel/grub/shim, please refer 3.3  
2. In grub boot, GrubX64.ef i will measure kernel binary/ command and initrd 
binary.  
Refer the measure log for grub boot . 
  
3 https://learn.microsoft.com/en -us/windows -hardware/manufacture/desktop/windows -secure -
boot -key -creation -and -man agement -guidance?view=windows -11     
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3.2  Boot TD Guest  
3.2.1   Launch via QEMU  
Since the QEMU  parameter li st is quite long and complicated, tdx -tools  provides  the  
start -qemu .sh script to handl e some parameters by default. It supports both direct 
boot and grub boot of TD guest . It also provides a few interactive parameters to 
meet customization requirement s.  
Note : The parameters in “ start -qemu .sh” may vary along with different Intel TDX 
kernel and Intel TDX QEMU  version s. Please make sure to use the correct tag of tdx -
tools wh ich matches the release . 
The start -qemu .sh script offers  several parameters to boot TD guest s on demand. 
The parameters are listed in Table 4: start -qemu qemu .sh para meters : 
Table 4: start -qemu .sh para meters  
Parameter  Description  
-i <guest image file>  Guest image file name and location  
-k <kernel file>       Kernel binary name and location  
-t [legacy | efi | td]   VM type  supported;  default is "td" 
-b [direct | grub]  Boot type, default  value is " direct " which requires 
kernel binary specified via "-k" 
-p <Monitor port>     Monitor port via telnet . Refer to the usage of QEMU  
Monitor  
-f <SSH Forward port>    Host port used for  guest VM SSH forwarding . Refer 
to QEMU  SSH port forwarding  
-o <OVMF file>       BIOS firmware device file . OVMF /TDVF  is used for 
"td" and  "efi" VM type. "efi" is used for non -
confidential VM, while "td" is used for TD VM guest  
-m <11:22:33:44:55:66>  MAC address  of VM. If MAC address changes for a 
TD guest, RTMR value will change and Intel TDX 
measurement will fail  
-q [tdvmcall | vsock]  TD quote  generation supports using tdvmcall or 
vsock.  Choose the corresponding value to boot TD 
guest.  
-c <number>  Number of vCPU. Default value is 1.  
-r <root partition>    Root partition for direct boot, default is /dev/vda3  
-e <extra kernel command > Extra kernel command needed in VM boot  
-v Flag to en able vsock  
-d Flag to enable "debug=on " for GDB guest . Refer to 
chapter 6 Develop & Debug     
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-s Flag to use serial console instead of hypervisor virtual 
console  (HVC ). 
-h Show usage help  
 
• Direct boot TD guest via QEMU  command  
This is an example of direct boot using start -qemu .sh. You  need to provide 
the guest image and kernel image as shown . Direct boot is used by default , so 
it's not required to use “-b direct”. 
$ ./start-qemu.sh -i <guest  image> -k <kernel binary>  
 
• Grub boot TD guest via QEMU  command  
This is an example of grub boot using start -qemu .sh. You  need to provide  the  
guest image and specify to use gr ub boot via “-b grub”.  
$ ./start-qemu.sh -i <guest image> -b grub 
 
• Direct boot non -confidential  guest via QEMU  command  
This is an example of how to direct boot a non -TD guest . Provide the guest 
image and kernel image as shown . It requires using "-t efi" to boot no n-
confidential  guest via OVMF /TDVF  or "-t legacy " to boo t non -confidential  
guest via legacy SeaBIOS . 
$ ./start-qemu.sh -i <guest image > -k <kernel image> -t efi 
$ ./start-qemu.sh -i <guest image> -k <kernel image> -t legacy  
  
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3.2.2   Launch  via Libvirt  
Libvi rt is a popular orchestrator to manage the VM guest via the virsh  command.  
Tdx -tools  provides both direct boot and grub boot XML  templates for TD guest  at 
tdx -tools /doc/ . 
Template  Description  
tdx_libvirt_direct.xml.template  TD guest direct boot  
tdx_lib virt_grub.xml.template  TD guest grub boot  
 
NOTE: T he templates may vary with a different kernel version or QEMU  version. 
Please make sure to use the correct tag of tdx -tools which matches the release 
version.  
To create the final VM’s XML from the tem plate , update the XML  template to refer 
to the guest image, kernel image , and OVMF binary : 
• Update OVMF binary

version.  
• Update OVMF binary  
<loader>/path/to/OVMF.fd </loader>  
• Update guest image  
<source file="/path/to/guest -image.qcow2"/>  
• Update kernel image (This is not needed when usi ng grub boot template)  
<kernel>/path/to/vmlinuz -jammy</kernel>  
 
Unlike QEMU , Libvirt uses the concept of a domain to manage the VM lifecycle 
across reboot  cycle.  Libvirt distinguishes between two different types of domains: 
transient and persisten t4. 
• Transient domains only exist until the domain is shut  down or when the host 
server is restarted.  
• Persistent d omains last indefinitely.  
This example uses a Transient domain to start a TD guest:  
$ virsh create tdx_libvirt_direct.xml  
Check  whether a TD  guest is running with the following command. It's expected to 
see  a TD guest running.  
 
4 https://wiki.libvirt.org/VM_lifecycle.html      
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$ virsh list  
 Id   Name                                      State 
--------------------------------------------------------------  
 2    td-guest                                  running 
 
Enter the  TD guest  console  with the following command.  
$ virsh console  <TD guest name>  
  
3.3  Secure Boot  
Secure boot for a TD guest is almost the same as a traditional non -confidential VM.  
The major difference is the OMVF.fd/ TDVF.fd need s to be  measured into  MRTD 
statically. Since the EFI variable is read -only in runtime with TDX guest VM,  i t does 
not permit  enroll ing  the secure boot key into the EFI variable FV  (firmware volume)  
via a tool such as EnrollDefaultKey  at runtime . Instead, a new tool ovmfkeyenroll  
from  tdx -tools  is developed to help enrol l the secure boot certificate offline  before 
measurement.  
 
Figure 15: Enable Secure Boot  
The steps of enrolling the secure boot key are as follows:  
• Step 1: Generate customized secure boot keys and certificates, instead of 
using a Microsoft certificate.  
#!/bin/bash  
NAME="Test"  
openssl req -new -x509 -newkey rsa:2048 -subj "/CN=$NAME PK/" -keyout PK.key \ 
-out PK.crt -days 3650 -nodes -sha256 
openssl req -new -x509 -newkey rsa:2048 -subj "/CN=$NAME KEK/" -keyout KEK.key \ 
-out KEK.crt -days 3650 -nodes -sha256 
   
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openssl req -new -x509 -newkey rsa:2048 -subj "/CN=$NAME DB/" -keyout DB.key \ 
-out DB.crt -days 3650 -nodes -sha256 
openssl x509 -in PK.crt -out PK.cer -outform DER  
openssl x509 -in KEK.crt -out KEK.cer -outform DER  
openssl x509 -in DB.crt -out DB.cer -outform DER  
GUID=$(py thon3 -c 'import uuid; print(str(uuid.uuid1()))')  
echo $GUID > myGUID.txt  
chmod 0600 *.key  
Refer to the following to learn more about t he different types of digital 
certificates.   
o Managing EFI Boot Loaders for Linux: Controlling Secure Boot  
o UEFI Specification  
• Step 2: Build and install ovmfkeyenroll tool, Refer to sourc e 
• Step 3: Enroll key into OVMF.fd  (aka TDVF.fd)  
$ ovmfkeyenroll -fd <absolute -path-to-OVMF.fd> \ 
                -pk <pk-key-guid> <absolute -path-to>/PK.cer \ 
                -kek <kek -guid> <absolute -path-to>/KEK.cer \ 
                -db <db-key-guid> <absolute -path-to>/DB.cer  
NOTE:  Replace GUID  with  the  content of myGUID.txt generated above . 
• Step 4: Install signing tool  
o Option 1: Bui ld from source : sbsigntools  
o Option 2: Use RPM  or DEB  packages built by  a third -party .  
$ wget https://download -
ib01.fedoraproject.org/pub/fedora/linux/releases/33/Everything/ 
x86_64/os/Packages/s/sbsigntools -0.9.4-2.fc33.x86_64.r pm 
$ sudo rpm -ihvf sbsigntools -0.9.4-2.fc33.x86_64.rpm   
• Step 5: Extract  the  following components from the guest’s packag es 
o shimx64.efi  
o mmx64.efi  
o grubx64.efi  
o fbx64.efi  
o guest kernel binary file  like vmlinuz  
• Step 6: Sign Shim/Grub/Kernel with customized secu re boot key  
$ sbsign --key <path -to>/DB.key --cert <path -to>/DB.crt --output shimx64 -
signed.efi  shimx64.efi  
$ sbsign --key <path -to>/DB.key --cert <path -to>/DB.crt --output mmx64 -signed.efi 
mmx64.efi   
$ sbsign --key <path -to>/DB.key --cert <path -to>/DB.crt --output grubx64 -
signed.efi  grubx64.efi  
$ sbsign --key <path -to>/DB.key --cert <path -to>/DB.crt --output fbx64-signed.efi 
fbx64.efi  
$ sbsign --key <path -to>/DB.key --cert <path -to>/DB.crt --output vmlinuz -signed 
vmlinuz-<guest-kernel-version>  
   
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NOTE: if the DB.key or DB.crt file to be signed is not in the same directory  
then a relative address needs to be used.  
 The following files  are created : 
o shimx64 -signed.efi  
o mmx64 -signed.efi  
o grubx64 -signed.efi  
o fbx64 -signed.efi  
o vmlinuz -signed  
• Step 7: Customize g uest QCOW2 Image  
o Create the directories for mounting ESP and rootfs p artitions:  
$ mkdir -p workspace/efi  
$ mkdir -p workspace/rootfs  
o Connect the QCOW2 image to /dev/nbdx : 
$ sudo modprobe nbd max_part=8  
$ sudo qemu-nbd --connect=/dev/nbd0 /path/of/td -guest.qcow2  
o Mount ESP and rootfs  
For RHEL 8.x:  
$ sudo mount /dev/nbd0p2 workspace/efi  
$ sudo mount /dev/nbd0p3 workspace/rootfs  
For Ubuntu 22.04:  
$ sudo mount /dev/nbd0p15 workspace/efi  
$ sudo mount /dev/nbd0p1 workspace/rootfs  
o Replace the files  
For RHEL 8.x : 
$ sudo su 
$ cp /path/to/shimx64 -signed.efi workspace/efi/EFI/BOOT/BOOTX64.EFI  
$ cp /path/to/shimx64 -signed.efi workspace/efi/EFI/redhat/shimx64.efi  
$ cp /path/to/fbx64 -signed.efi workspace/efi/EFI/BOOT/fbx64.efi  
$ cp /path/to/mmx64 -signed.efi workspace/efi/EFI/BOOT/mmx64.efi  
$ cp /path/to/mmx64 -signed.efi workspace/efi/EFI/redhat/mmx64.efi  
$ cp /path/to/grubx64 -signed.efi workspace/efi/EFI/redhat/grubx64.efi  
 
$ # please pay attention to replace the cor rect version of the  kernel  
$ cp /path/to/vmlinuz -signed workspace/rootfs/boot/vmlinuz -<kernel-version>  
$ sudo su  
$ cp /path/to/shimx64 -signed.efi workspace/efi/EFI/ubuntu/ shimx64.efi  
$ cp /path/to/mmx64 -signed.efi workspace /efi/EFI/BOOT/mmx64.efi  
   
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$ cp /path/to/mmx64 -signed.efi workspace/efi/EFI/ubuntu/mmx64.efi  
$ cp /path/to/grubx64 -signed.e fi workspace/efi/EFI/ubuntu/grubx64.efi  
$ 
$ # please pay attention to replace the correct version of the kernel  
• Step 8:  Unmount  the ESP and rootfs partitions:  
• Step 9: Disconnect the QCOW2 image  
$ sudo qemu-nbd --disconnect /dev/nbd 0 
Use  the modified OVMF.sb.fd and tdx -guest.sb.qcow2 to start  a TDVM and verify 
whether the secure boot is enabled  via the  dmesg log:  
$ dmesg | grep -i "Secure Boot" 
It is expected  to show  "Secure Boot Enabled " 
3.4 Use VirtIO Device  
Within the Intel TDX guest,  the drivers  are  the largest threat attack surface by far .  
They access the host -controlled PCI config space  to perform MMIO and port IO . 
Refer to Figure 16: TDX Guest Attack Surface  or detail threat analysis at [2] .     
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Figure 16: TDX Guest Attack Surface  
To mitigate this risk there is a curated list of drivers that are enabled in the runtime 
for the TD guest kernel. By default, all PCI and ACPI bus drivers are blocked unless 
they are in the allow -list. The current default allow -list for the PCI bus is limited to the 
following VirtIO  drivers:  
• virtio_net  
• virtio_console  
• virtio_blk  
• 9pnet_virtio  
• virtio_vsock  
Since most of the ACPI tables are not needed for a n Intel  TDX guest, the  
implemented ACPI table allow -list limits them to  a small, predefined list with a 
possibility to pass additional tables via a command line option. The current allow -list 
is limited to the following tables : 
• XSDT  
• FACP  
• DSDT  
• FACS  
• APIC  
• SVKL  
   
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• CCEL  
3.5  Full Disk E ncryption  
FDE ( Full disk encryption) is a security method for protecting sensitive data by 
encrypting all data on a disk partition . In non -confidential VM, FDE is using LUKS 
(Linux Unified Key Setup) with  a user input disk encryption key . In confidential 
environment s like Intel TDX, to achieve zer o trust, the encryption key should be 
retrieved  from  the  replying party via remote attestation . 
  
Figure 17: Full Disk Encryption in TDX Guest  
The FDE can be done in OVMF at  the  pre -boot s tage or initrd at  the  Linux early boot 
stage like . To learn more,  refer to the presentation “ Secure Boot loader for 
Confidential Computing ”.  
3.5.1  Workflow  
This section introduce s a solution /implementation  integrating  FDE with Intel TDX.

• XSDT  
• FACP  
• DSDT  
• FACS  
• APIC  
• SVKL  
   
• CCEL  
  
This section introduce s a solution /implementation  integrating  FDE with Intel TDX.  
The workflow can be divided into 5 steps . 
1. Register  key and keyid from the Key Broker Service ( KBS ). 
   
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2. Create an encrypted guest i mage with key retrieved in Step 1  
3. Install FDE components in the encrypted guest image  
4. Enroll necessary variables into OVMF  
5. Launch  a TDX guest based on the encrypted guest image an d the OVMF  
In the  above  step 1 , the key and key id pair should be register ed in the KBS. Typically, 
the key will be used to encrypt  the guest image , and the keyid is the  iden tifier  of the 
key in the KBS , which will be used in the decryption process . Given that KBS  
providers  have different design s for their key s and keyids, it is recommended to 
register the  pair of the key and the keyid after consulting the  KBS provider.   
In the  above  step 2 , it create s an encrypted guest image . 
In the  above  step 3 , FDE components will be installed in the encrypted guest image . 
The tdx -tools provides a n integrated  script “tdx-tools/attestation/full -
disk-encryption/tools/image/fde -image.sh ” to complete the task . The key 
and the keyid is retrieved in Step 1 , and the tdx -repo is built from the tdx -tools.  
$ cd attestation/full -disk-encryption/tools/image  
$ ./fde-image.sh -k ${key} -i ${keyid} -d ${tdx-repo} 
In Step 4, several variables are enrolled in the OVMF. These variables, such as keyid, 
are retrieved by the fde -agent from the OVMF to help remote attestat ion retrieve 
the key from the KBS.  For example, assume that the keyid is saved in a JSON file.  
The python script “tdx-tools/attestation/full -disk-
encryption/tools/image/enroll_vars.py ” helps enroll the data.  
$ cd attestation/full -disk-encryption/tool s/image 
$ # Enroll user data  
$ cat userdata.txt  
{ 
 "keyid":"sth" 
} 
$ NAME="KBSUserData"  
$ GUID="732284dd -70c4-472a-aa45-1ffda02caf74"  
$ DATA="userdata.txt"  
$ python3 tools/image/enroll_vars.py -i OVMF.fd -o OVMF.fd -n $NAME -g $GUID -d 
$DATA 
$ # Enroll KBS URL 
$ NAME="KBSURL"  
$ GUID="0d9b4a60 -e0bf-4a66-b9b1-db1b98f87770"  
$ DATA="url.txt"  
$DATA 
$ # Enroll KBS Certificate  
$ NAME="KBSCert"  
$ GUID="d2bf05a0 -f7f8-41b6-b0ff-ad1a31c34d37" 
$ DATA="cert.cer"  
   
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$DATA 
 
In Step 5 , a TDX g uest is launched from the encrypted guest image. The script “tdx -
tools/start -qemu .sh” can launch it . Please use the encrypted guest image and 
OVMF mentioned in step 3 and step 4.  
$ OVMF_PATH=/path/to/OVMF  
$ IMAGE_PATH=/path/to/image  
$ start-qemu.sh \ 
 -b grub \ 
 -q tdvmcall \ 
 -o ${OVMF_PATH} \ 
 -i ${IMAGE_PATH}  
The detail steps are described in tdx-tools/doc/ full_disk_encryption.md . 
3.5.2  Prepare Encryption Image  
It is complicated to create an  encrypted guest  image in Step 2 and Step 3. In Step 2, 
an em pty image is created first . The image will be partitioned into several volumes , 
and the root filesystem partition is encrypted with the key in actual. Then the rootfs 
is copied  to the root filesystem partition.  
In the Step 3, a binary named by the fde -age nt and its related configuration need to 
be installed into the initrd . The  parameter “cryptdevice =${root -enc }”,  which 
specifies  the  encrypted root partition,  is appended in the kernel  cmdline to enable 
the FDE .  
More details are  described in the tdx-tools/attestation/full -disk-
encryption/README.md .     
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4  Measurement  & Attestation  
4.1  TEE , TCB , Quote  
Typically , a TEE provide s the  evidence or measurements of its origin and current 
state  so that the evidence can be verified by another party either  programmatic ally 
or manually . It can decide whether to trust code running in the TEE. It is typically 
important that such evidence is signed by hardware that can be vouched for by a 
manufac turer, so that the party checking the evidence has strong assurances that it 
was not generated by malware or other unauthorized parties.  [3]  The remote party 
allow s sending  the secret or key to the TEE environment after successfully verif ying  
the evidence . 
 
Figure 18: Measurement a nd Attestation for TEE  
The trusted computing base (TCB) refers to all of a system's hardware, firmware, 
and software components that provide a secur e environment.   For a confidential 
VM , it includes hardware information such as CPU, SEAM firmware , and gues t 
components such as OVMF, bootloader (shim/grub), and kernel.  The  other host 
software such as QEMU  VMM  and  Orchestrator Libvirt are out of TCB.  
The hash -chained measurement on TCB will be extend ed to some secure register s 
such as TPM PCR ( platform configuration register) . The value s from several secure 
registers are constructed  to a report and  are finally sign ed to be a quote  by an 
attestation key.  
   
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4.2  TDX Measurement  
4.2.1  TD Report  
 
Figure 19: Intel TDX Measurement  
The API TDG.MR.REPORT  in the Intel  TDX module creates a 
TDREPORT_STRUCT  structure5 containing the TD measurements, initial 
configuration of the TD that was locked at finalization ( TDH.MR.FINALIZE ), the 
Intel TDX module measurements, and t he REPORTDATA  value  [1]: 
• The measurement of TDX module is recorded  in the field MRSEAM . 
• The measurement of  TDVF/OVMF  is record in the field MRTD . 
• The measurement of TD -Hob , ACPI  is record in the RTMR [ 0]. 
• The measurement o f bootloaders like grub/shim is record ed in the field 
RTMR [ 1]. 
• The measurement of kernel  and  initrd is recorded in the field RTMR [ 2]. 
NOTE : for direct boot, there is no bootloader , so the measurement of kernel is 
recorded in the field RTMR [ 1]. 
4.2.2  MRTD and RTMR  
There are two types of measurement registers – MRTD  and RTMR  for Intel TDX : 
 
5 https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Tdx.h  
   
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• MRTD  (TD measurement register) provides static measurement of TD build 
process and the initial contents of TD  
• RTMR  (runtime measurement register ) is an array of general -purp ose 
measurement registers to Intel TDX software to enable measuring additional 
logic and  data loaded into the TD at runtime . As designed, RTMR can be used 
by the guest TD software to measure boot process.  
There are 4 RTMR registers : 
Table 5: RTMR Definitions  
Register  Content  Measured by  
RTMR [0] Static configuration (CFV); Dynamic 
Configuration (TD HOB, ACPI)  TDVF  
RTMR [1] PCI option ROM, O S loader, OS kernel, 
initrd, GPT, boot variable, bo ot 
parameter  TDVF  
RTMR [2] TD OS App  OS  applications  
RTMR [3] Reserved   
 
4.2.3  Pre -Boot  Measurement  
The pre -boot environment before  the  kernel includes  the TDVF/OVMF phase of  the 
bootloader phase ( shim and grub ). The whole boot chain will be measured into 
RTMR  via EFI_CC_MEASUREMENT _PROTOCOL6. 
 
6 https://github.com/tianocore/edk2/blob/master/MdePkg/Include/Protocol/CcMeasurement.h      
45       Document Number: 355388 -001  
 
Figure 20: TD Measurement Process  
Similar to TCG event log  [4] , EFI_CC_MEASUREMENT_PROTOCOL  log s the event s into 
ACPI table CCEL 7 and the measurement hash is extended to the corresponding 
RTMR register.  The event logs in CCEL table can be replayed within a TD guest to 
verify the RTMR value . 
4.2.4  PyTdxMeasure Tool  
PyTdxMeasure  in tdx -tool s provi des a Python library and utilities for TD 
measurement  that can be used by tenant workload, attestation agent , or validation 
tools : 
• Get RTMR value from TDREPORT via Linux attestation driver.  
• Get the full TD event log from CCEL ACPI table.  
• Verify value of RTMR by replaying event logs.  
Here  are the step -by-step  instructions to use  PyTdxMeasure : 
• Install  
$ python3 -m pip install pytdxmeasure  
• Run  
o Get Event Log . 
$ ./tdx_eventlogs  
 
7 https://uefi.org/specs /ACPI/6.5/05_ACPI_Software_Programming_Model.html#cc -event -log -
acpi -table   
   
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Refer to the example output s at measurement log for grub 
boot  and  measurement log for direct boot  
o Get TDREPORT , which includes value of RTMR . 
$ ./tdx_tdreport  
o Verify RTMR . 
$ ./tdx_verify_rtmr  
The to ol will compare RTMR  value from TDREPORT  and RTMR  value 
replayed via event log . The two values are expected to be identical , 
which means the measured contents are not tampered  with . 
4.2.5  Linux Runtime Measurement  
Inte grity Measurement Architecture  (IMA) is the Linux kernel inte grity sub system  
to detect if files  have been accidentally or maliciously altered, both remotely and 
locally. Currently IMA maintains the runtime measurement list if anchored in a 
hardware Trusted Platform Module  (TPM) to make the measured hashes of files

• Run  
 
hardware Trusted Platform Module  (TPM) to make the measured hashes of files 
immutable. It also supports the app raise mechanism to enforce local file integrity by 
appraising the measurement against a “good” value stored as an extended attribute.  
Extra kernel changes have been introduced to enable  IMA in  TD  guest  and  maintain 
the runtime measurement list inside RTMR [2]. 
 
Figure 21: Enable IMA extend hash to RTMR  
Different configuration s (built -in kernel command line ) can be appli ed to define the 
scope  to be measured. Available options include:  
   
47       Document Number: 355388 -001  
 
• “ima_hash=sh a384”: Enable  measurement against  boot aggregates , which 
covers firmware , boot loader, kernel command line and etc . 
• “ima_hash=sha384  ima_policy=critical_data ”: Enable measurement s 
against  boot aggregates and kernel integrity critical data.  
• “ima_hash=sha384 ima_policy= tcb”: Enable measurement s against  all 
programs executed, files mmap ’d for exec ution , and all files opened with the 
read mode bit set by either the effective uid (euid=0) or  uid=0.  
Custom policies can be set by user to d efin e the sco pe to be measured . For more 
details, please refe r to the IMA documentations.  
Below  are  some  sample  instructions to enable and verify  this feature in a TD guest:  
• Sample configuration to start up the T D VM  
$ ./start-qemu.sh -k <path-to-kernel> -i <path-to-image> -e 
"ima_hash=sha384 ima_policy= critical _data" 
• Run  
o Get IMA measurement count.  
$ cat /sys/kernel/security/ integrity/ima/runtime_measurements_count  
o Get full IMA measurement list  stored inside  the  kernel securityfs.  
$ cat /sys/kernel/security/integrity/ima/ascii_runtime_measurements  
o Verify RTMR  wit hin TDREPORT  by using the PyTdxMeasure Tool . 
$ cd tdx-tools/attestation/pytdxmeasure  
$ sudo ./tdx_tdreport  
User can find the measurements extended in RTMR [ 2] inside the 
TDREPORT . TPM PCR Calculator (available in Microsoft Store) can be 
used to replay the result with the ASCII measurements that fetched 
inside kernel security  FS. 
4.3  Attestation  
4.3.1  Overview  
Remote attestation helps an off -platform party (also known as Relying Party) to 
have increased confidence that the software is running inside a TD, on a g enuine, 
Intel -TDX system, and at a given security level (also referenced as the TCB version).  
On a hig h level, the Relying Party requests attestation  proof – a TD Quote – and then 
verifies this TD Quote. Among other information, the TD Quote contains: TD    
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measurements (static and runtime), data that the TD associates with itself, SVNs of 
elements in the TDX  TCB. Intel TDX attestation requires Intel SGX, because an 
SGX -based TD -Quoting Enclave is used in the process. In the following, we provide 
some more det ails of the Intel SGX attestation flow. See Section E of Intel® Trust 
Domain Extension – White Paper  for more details about Intel TDX remote 
attestation.  
Intel TDX Attestation flow ( see  Figure 22): 
• (1): Relying Party sends an attestation request to TD.  
• (2) : TD request s a TD Report from th e Intel TDX Module  
• (3, 4) : Intel  TDX Module invoke s the CPU instr uction SEAMREPORT, which 
triggers the hardware -based generation of a TD Report including, among 
other information, TD measurements (static and runtime), data that the TD 
associates with itself, SVNs of elements in the TDX TCB. The 
SEAMREPORT instr uction pr otects the integrity of the TD Report with a 
MAC for which the key is only known  to hardware.  
• (5): Intel TDX Module passes back the TD Report to the TD.  
• (6): TD forwards the TD Report to the VMM requesting the conversion to a 
TD Quote.  
• (7, 8): VM  forwards  the TD Report to the TD Quoting Enclave for conversion. 
TD  Quoting Enclave uses the CPU instruction EVERIFYREPORT2  to verify 
the MAC of the TD Report. On success, the TD  Quoting Enclave  converts the 
TD Report to a TD Quote by signing the TD Repor t with it s Attestation Key. 
The Attestation Key is signed with the Provisioning Certificate Key (PCK) by 
the Provisioning Certification Enclave (PCE) and the Intel publishes 
certificates and certificate revocation lists for PCKs. As a result, the trust of 
TD Quotes  is rooted in Intel CAs.  
• (9, 10): VMM passed back TD Quote to TD, and TD forwards it to the 
challenger.  
• (11, 12 ): Relying Party performs attestation verification by verifying the TD 
Quote. The attestation verification can be done by the Relying Pa rty itsel f or 
using a dedicated attestation service, e.g., Project Amber.  
 
Intel TDX r emote attestation demonstrates applications that are running securely 
on a given trusted environment (TD guest) to a relying party. This increases the 
confidence of  a rem ote party  that the software is running inside a TD on a genuine 
Intel  TDX system at a given security level, which is also referenced as the TCB    
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version. The TDX attestation reuses Intel SGX  infrastructure to provide attestation 
to a given measurement. It is based o n TD Quote , which is the signed TD Report in 
TD Quoting Enclave  [1].  
 
Figure 22: Intel TDX Attestation Flow  
Linux Stack for Intel TDX provides end -to-end Intel TDX attestation capability by 
integrating the Intel ® Software Guard Extensions Data Center Attestation 
Primitives8 (Intel® SGX DCAP ). In this section, it will introduce how to run Intel TDX 
remote at testation.  
4.3.2  Set  Up DCAP Repo sitory  on Host  
In the following, we show  how to s et up Intel SGX DCAP  on an Intel TDX host with 
either Ubuntu 22.04 or RHEL 8.x. For more details about installation and self -
building  https://download.01.org/intel -sgx/sgx -dcap/1.17/linux/docs/  or 
https://github.com/intel/SGXDataCenterAttestationPrimitives  
Before running  the steps, download  SGX DCAP archive  1.17 from 
https://download.01.org/intel -sgx/sgx -dcap/1.17/linux/  according to your OS distro. 
The relevant archive is named sgx_*_local_repo.tgz.  
1. Ubuntu 22.04  
$ # Switch to root user  
$ sudo su 
$ 
$ tar zxvf <sgx_debian_local_repo file name >.tar.gz 
$ mv sgx_debian_local_repo /srv/sgx_debian_local_repo  
 
8 https://github.com/intel/SGXDataCenterAttestationPrimitives   
   
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$ 
$ # Set up local Debian repository  
$ cat <<EOF >> /etc/apt/sources.list.d/s gx_debian_local_repo.list  
deb [trusted=yes arch=amd64] file:/srv/sgx_debian_local_repo jammy main  
EOF 
$ 
$ apt update 
$ apt install -y gcc make tar  
 
 # Install latest nodejs, version 18 shown below is an example  
$ curl -sL https://deb.nodesourc e.com/setup_18.x -o nodesource_setup.sh  
$ bash nodesource_setup.sh sudo apt -get install -y nodejs  
2. RHEL 8.x  
$ sudo su 
$ 
$ cd /srv/  
$ tar zxvf <sgx_rpm_local_repo  file name> .tar.gz  
$ mv sgx_rpm_local_repo /srv/sgx_rpm_local_rep o 
$ 
$ # Set up local RPM repository  
$ cat <<EOF >> /etc/yum.repos.d/tdx -attestation.repo  
[tdx-attestation -local] 
name=tdx -attestation -local 
baseurl=file:///srv/sgx_rpm_local_repo  
enabled=1  
EOF 
$ 
$ dnf check -update 
$ dnf install -y gcc make tar  
 
$ sudo dnf module reset nodejs  
$ 
$ # Install latest nodejs, version 18 shown below is an example  
$ dnf module install nodejs:1 8 
 
4.3.3  Set  Up PCCS  on Host  
Intel provides a reference  implementation of the  Provisioning Certification Cachin g 
Service (PCCS) . This cache can store collateral (e.g., Provisioning Certificate Key 
certificates and TCB levels) necessary for TD quote generation and TD quote 
verif ication, without the need to access the Intel® Software Guard Extensions 
Provisioning Cer tification Service (Intel® SGX PCS ). 
In the following example, we assume you use Intel’s PCCS implementation for 
remote attestation purposes.     
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Figure 23: Setup PCCS  
1. If you do not have an API key for the Intel SGX PCS service , obtain a key : 
Go  to https://api.portal.trustedservices.intel.com/provisioning -certification  
logi n (or create an account) , and click 'Subscribe' . Two API key s are 
generated (for key rollover). Copy one of the API keys for the following steps.   
2. Install  PCCS with following steps. During installation, answer “Y” when asked 
if the PCCS should be installed now, “Y” when asked if PCCS should be 
configured now, and enter API key generated in step 1 when asked for “ Intel 
PCS API key ”. Answer the rema ining ques tions according to your needs.  
o For Ubuntu 22.04  
$ # Switch to root user for installation  
$ sudo su  
$ 
$ apt update  
$ apt install -y --no-install-recommends sgx -dcap-pccs 
$ cd /opt/intel/sgx -dcap-pccs 
$ sudo -u pccs ./install.sh  
 
o For RHEL 8. x 
   
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$ sudo su  
$ 
$ dnf install -y sgx-dcap-pccs  
$ sudo -u pccs ./install.sh

$ sudo su  
$ 
 
$ sudo su  
$ 
 
3. After the installation is complete s successfully, make sure the PCCS is 
configured to use  the v4 API. Look for “uri” in  the  configuration file 
/opt/intel/sgx -dcap -pccs/config/default.json:  
"uri": "https://api.trustedservices.intel.com/sgx/certification/v4/"  
4. If present, delete the old  PCCS database. Afterwards, restart PCCS . 
$ $ [Optional] Remove old PCCS datase  
$ sudo rm -rf /opt/intel/sgx -dcap-pccs/pckcac he.db  
$ 
$ Restart PCCS and check status  
$ sudo systemctl restart pccs  
$ sudo systemctl status pccs  
You can check the service log of the PCCS service with the following command:  
$ sudo journalctl -u pccs -f 
4.3.4  Set  Up Quote Generation Service on Host  
This s ection introduces how to install  Quote Generation Service  (QGS)  and how to 
perform  Intel SGX platform registration . 
 
53       Document Number: 355388 -001  
 
Figure 24: Set  up DCAP software on the TDX host  
1. Download the Intel® Software Guard Ex tensions SDK for Linux* OS (Intel® 
SGX SDK for Linux* OS)  from https://download.01.org/intel -sgx/sgx -
dcap/1.17/linux/distro/  according to your OS distro. The relevant archive is 
named sgx_linux_x64_sdk_*.bin . 
2. Install the Intel® Software Guard Extensions SDK for Linux* OS (Intel® SGX 
SDK for Linux* OS)  to the folder /opt/intel / 
$ sudo ./sgx_linux_x64_sdk_2. 20.100.4.bin 
o For RHEL 8.x 
$ sudo ./sgx_li nux_x64_sdk_2. 20.100.4.bin  
2. Install QGS  and QPL  packages on the host . 
o For Ubuntu 22.04   
$ sudo apt install -y –no-install-recommends tdx -qgs libsgx -dcap-default-qpl 
libsgx-dcap-default-qpl-dev 
o For RHEL 8.x  
$ sudo dnf install -y tdx-qgs libsgx -dcap-default-qpl libsgx-dcap-default-qpl-
devel 
Modify the configuration file: /etc/sgx_default_qcnl.conf  to add the 
following . Replace <PCCS_IP>  with the IP of your PCCS.  
// PCCS server address  
“pccs_url ”: “https://<PCCS_IP>:8081/sgx/certification/v4/ ”,  
// To accept insecure HTTPS certificate  depends on PCCS Ser ver’s configuration,  
// set below option to false  
“use_secure_cert ”: false 
3. Install PCKIDRetrievalTool  
$ sudo apt install -y sgx-pck-id-retrieval -tool 
o For RHEL 8 .x 
$ sudo dnf install -y sgx-pck-id-retrieval -tool 
NOTE: the reported version of the PCKIDRetrievalTool may  be different.  
4. Modify the configuration file /opt/intel/sgx -pck-id-retrieva l-
tool/network_setting.conf  with the followin g content.  
PCCS_URL=https://<PCCS_IP>:8081/sgx/certification/v4/platforms  
# if using localhost as pccs  
   
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# PCCS_URL=https://localhost:8081/sgx/certification/v4/platforms 
USE_SECURE_CERT=FALSE  
5. Perform SGX platform Registration via PCKIDRetrievalTool  
$ cd /opt/intel/ sgx-pck-id-retrieval -tool 
$ sudo sh -c ./PCKIDRetrievalTool  
The expected response  is as follows . The reported version may be different . 
Intel® Software Guard Extensions PCK Cert ID Retrieval Tool Version 1.1 7.100.4 
Registration status has bee n set to completed status. Pckid_retrieval.csv has been 
generated successfully!  
NOTE: If it returns  a message li ke “Platform Manifest not availa ble”, you may need to 
perform SGX Factory Reset in BIOS and run PCKIDRetrievalTool again.  
4.3.5  Generate Quote  in TD  
This section introduces the generation of a TD quote inside a TD including the 
launch of a TD with quote generation.  
 
Figure 25: Quote Generation  
   
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4.3.5.1  Launch TD with Quote Generation Support  
There are two  ways to run quote generation : 
 
Figure 26: Approaches to Generate Intel TDX Quote  
• App roach 1: Get quote via vsock  call from the user space within TD guest to 
QGS directly . 
o If launch ed via QEMU , add the following parameter.  
-device vhost -vsock-pci,guest -cid=3 
o If using start -qemu.sh  to indicate getting quote via vsock.  
$ ./start-qemu.sh -i <guest image> -k <guest kernel>  -q vsock 
o If launch ed via libvirt, add the following fields in XML  
<vsock model='virtio'>  
  <cid auto='yes' address='3'/>  
  <address type='pci' domain='0x0000' bus='0x05' slot='0x00' function='0x0'/> 
</vsock>  
 
• Approach 2 : Get quote via TDG.VP.VMCALL.GETQUOTE   
o If launch ed via QEMU , add “quote-generation -
service=vsock:2:4050 ” in parameter -object  
-object tdx -guest,sept -ve-disable,id=tdx,quote -generation -service=vsock:2:4050  
o If using start -qemu.sh  to indicate getting q uote via tdvmcall . 
$ ./start-qemu.sh -i <guest image> -k <guest kernel> -q tdvmcall  
   
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o If launch ed via Libvirt, add following fields in XML  
<launchSecurity type='tdx'>  
  ...... 
  <Quote-Generation -Service>vsock:2:4050</Quote -Generation -Service> 
</launchSecur ity> 
o Within a TD guest, create a  file at /etc/tdx -attest.conf  with the 
following content:  
port=4050  
4.3.5.2  Generate Quote within Intel TDX Guest  
1. Set  up the package repository in TD  guest . Refer to Section  4.3. 2: Set  Up 
DCAP . 
- Install libtdx -attest, libtdx -attest -dev  
$ sudo apt install -y libtdx -attest libtdx -attest-dev 
$ sudo dnf install -y libtdx -attest libtdx -attest-devel 
2. Build quote generation sample  
$ sudo apt  install -y gcc make   
$ cd /opt/intel/tdx -quote-generation -sample/  
$ make clean  
$ make 
$ sudo dnf install -y gcc make  
$ make 
 
3. Use test_tdx_attest  to generate  TD quote which will be w ritten in to file  
quote.dat .  
$ sudo ./test_tdx_attest  
 
4.3.6  Verify TD Quot e on Host  
    
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Figure 27: Verify Quote  
After the Q uote is generated, you can use  a sample Quote verification application to 
verify the Quote.  
1. Install the Quote veri fication libraries:  
$ sudo apt install -y libsgx -dcap-quote-verify  
$ sudo apt install -y libsgx -dcap-quote-verify-dev  
$ sudo apt install -y libsgx -ae-qve 
$ sudo dnf install -y libsgx -dcap-quote-verify  
$ sudo dnf install -y libsgx-dcap-quote-verify-devel  
$ sudo dnf install -y libsgx -ae-qve 
2. Copy quote.dat  from  TDVM  
Use scp  or virt_copy_out  to copy the quote from the TDVM . 
$ # use scp to copy the quote from TDVM to host  
$ scp <TDVM -user>@<TDVM -IP>:<path -to>/quote.dat <host_di rectory>/.  
$ # use virt -copy-out to copy the quote from TDVM to host  
$ virt-copy-out -a <image_name> <directory_in_TDVM_contains_quote.dat> 
<a_host_directory>  
NOTE: Terminate  the  TDVM before using virt_copy_out  to copy out the 
quote.dat.  
   
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3. Build and run sa mple application verifying the generated quote located at 
<PATH>:  
$ git clone https://github.com/intel/SGXDataCenterAttestationPrimitives.git  
$ cd SGXDataCenterAttestationPrimitives/SampleCode/ QuoteVerificationSample  
$ make SGX_DEBUG=1 
$ ./app -quote <PATH>/quote.da t 
  
4.4  Use Intel Project Amber  
Intel Project Amber is Intel’s first step in creating a new multi -cloud, multi -TEE 
service for third -party attestation to help  drive forward adoption of co nfidential 
computing for the broader industry.  Please ref er to Project Amber  for more details. 
This section introduce s how to install the Amber client to access services.  
4.4.1  Ov erview  
Intel ® Project  Amber  Go  Client  Library9  is a Go library  for integrating with  the  Intel ® 
Project Amber V1 API. A beta version  Intel ® Project  Amber  Go  TDX CLI10  (amber -cli) 
is also provided in this library repository . This amber -cli provides basic 
functionalit ies:  
• Creat e RSA key pair  
• Get an Amber signed token  
• Get a TD Quote with nonce and user data  
• Decrypt ing  an encrypted blob  
This section introduce s the installation and example usages.  
4.4.2   Ins tallat ion  
A build script is provided by tdx -tools . Refer to 2.4.1  Build Packages  to build 
packages and  2.5  Install IaaS Host  to set up the repository.  
NOTE : This package is only for TD guest’s attestation environment . The packages 
will be installe d by default if the guest image is created using guest image tool in 
2.4.2  Cre ate Gu est Image . 
• In case the packages are not installed  by default , install the Amber Client 
package and its dependency.  
 
9 https://github.com/intel/amber -client  
10 https://github.com/intel/amber -client/tree/main/amber -cli-tdx     
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$ sudo apt install -y libtdx-attest amber -cli 
$ sudo dnf install libtdx -attest intel -mvp-amber-cli 
4.4.3  Example  Usage  
To get the TD Quote, a nonce and user data can be used as input parameter.  
• Get a TD Quote  
$ amber-cli quote  
• The nonce is a value con structed to be unique to a particular message to 
prevent replay attacks, user can get  a nonce  from Amber attestation service

prevent replay attacks, user can get  a nonce  from Amber attestation service 
or create random data  as a nonce . To get a TD Quote with the nonce  by 
following step, the hash of the nonce will be put into TD rep ort in the TD 
Quote.  
$ amber-cli quote  --nonce <base64 encoded nonce > 
$ amber-cli quote --nonce <base64 encoded nonce> --user-data <base64 encoded 
userdata>  
 
To get an Amber signed token , the AMBER_URL  and AMBER_API_KEY  is need ed, 
please contact Intel ® Project Amber team to get them . 
• Export environment variables  
$ export AMBER_URL=<amber api url>  
$ export AMBER_API_KEY=<amber attestation api key>  
• Create RSA key pair  
$ amber-cli create -key-pair --key-path <private key file path>  
$ amber-cli token  
• Get an Amber signed token with user data and policy -ids 
$ amber-cli token --user-data <base64 encoded userdata> --policy-ids <comma 
separated amber attestation policy ids > 
    
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The amber -cli provides a feature to decrypt an encrypted blob . The encrypted blob 
should be encoded by base64.  
$ amber-cli decrypt --key-path <private key file path> --in <base64 encoded 
encrypted blob> --out <output file path>  
    
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5 Validation  
The Linux Stack for Intel TDX provides end to end TDX capability across diverse 
infrastructures  like hypervisor and Kubernetes within hypervisor.  
 
Figure 28: Intel  TDX E2E Full Stack Validation  
The end -to-end validation of Linux Stack  for Intel TDX cover s the following scopes.  
Table 6: Linux Stack for Intel TDX Validations  
Validation  Scope  Description  
System Status  IaaS  Verify the hardware and BIOS status like Intel SGX, Inte l 
TME -MK , Intel TDX, Intel TDX mo dule , etc . 
IaaS Host  IaaS  Verify the functionality of IaaS components like 
platform registration, QGS service, libvirt  and QEMU  
configurations  
VM Lifecycle  PaaS  Diverse boot types for TD VM guest, pre -boot 
environment measurement, etc . 
   
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VM Environmen t PaaS  CPUID, TSC, VirtIO devices , etc . 
Workload  PaaS  Container workloads run in TD guest or the Kubernetes 
cluster within TD guest  
 
To support complex validation and automation scenarios, the pyCloudStack 
framework is designed to support the scopes ment ioned in Table 6: Linux Stack for 
Intel TDX Validations . 
5.2 PyCloudStack  
5.2.1  Overview  
PyCloudStack abstracts the common objects , operations , and  resources for diverse 
cloud architectures . It supports h ypervisor stack s based on libvirt or  direct QEMU  
command s, container stacks  orchestrated by Kubernetes or directly by docker , and  
supports  running  on local or remote IaaS host s. It can be used to create an advance d 
deployment CI/CD operator via  a Python plugin for ansible, end -to-end val idation , 
framework with customized componen ts and configurations in a full vertical stack . 
The overall architecture diagram is illustrated as below : 
 
Figure 29: PyCloudStack Framework  
The framework supports  scenarios for VM manageme nt: via QEMU  direct or via 
libvirt : 
   
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Figure 30: Validation Scenarios  for VMM and Libvirt  
• Scenario 1: QEMU  manage d VM direct ly via QMP  (QEMU  monitor  protocol )11 
• Scenario 2: Libvirt manage d VM  via VirtAPI12 
The framework abstracts the common operations for host, virtua l machine, 
kubernetes , and container : 
 
Figure 31: Abstract Common Operations for Cloud Stack  
 Below are additional details for the VM use case.  
• VMGuestFactory  is designed to communicate  and handle VM configurations 
with test case s. For example, the size of a virtual machine can be specified by 
indicating how many CPU s and how much memory are required.  
VMGuestFactory  usually works with VMParam  and VMImage . 
o VMParam  operator provid es predefined VM parameters for typical 
configuration. It also provides the capability for you  to customize VM 
parameters.  
 
11 https://wiki. QEMU .org/Documentation/QMP   
12 https://github.com/virtapi/virtapi   
   
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o VMImage  is designed to manage guest images for guest VMs so that 
multiple guest distros can be supported. You  can customize guest 
images based on test requirement.  
• VMM  operators are responsible for VM lifecycle management using given 
configuration. VMM operator includes VMMLibvirt  and VMMQEMU . 
VMMLibvirt  needs to work together with “virtXML ” operator.  
• virtXML  is respo nsible for  Libvirt XML  template management.  It helps you  to 
customize XML  template for VMs.  
For  Kubernetes use case : 
• cluster  operator is designed to implement Kubernetes object manageme nt.  
Registry  is used to manage container images. With them worki ng together, 
you  can create Kubernetes objects, such as deployment and service. Then 
cloud workload can run in a Kubernetes cluster.  
There are also some other common operators for Device m anagement  at the 
bottom of the diagram.  
• CMDRunner  is designed t o run commands on local host or remote targets via 
ssh connection.  
• DUT  is designed to manage devices under test, such as CPU  frequency of 
host.  
• MSR  operator provides methods to read and write register.  
Finally, with the  PyCloudStack framework, functio nality, stability, performance, and 
interoperability tests are well supported.  
5.2.2  Installation  
PyCloudStack has been uploaded to PyPI . Install PyCloudStack to the host via the 
following command.  
$ pip3 install pycloudstack  
5.2.3  Example  
Most of automation tests  in the  tdx -tools  repo are based on  the  PyCloudStack 
framework . Below  are  several examples:  
• Example 1: Operate VM via Libvirt  
from pycloudstack.vmguest import VMGuestFactory  
   
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from pycloudstack.vmparam impor t VM_STATE_SHUTDOWN, VM_STATE_RUNNING, 
VM_STATE_PAUSE, VM_TYPE_TD  
 
vm_factory = VMGuestFactory(vm_image, vm_kernel)  
 
LOG.info("Create TD guest")  
inst = vm_factory.new_vm(VM_TYPE_TD, auto_start=True)  
inst.wait_for_ssh_ready()  
 
LOG.info("Suspend TD guest")  
inst.suspend()  
ret = inst.wait_for_state(VM_STATE_PAUSE)  
assert ret, "Suspend tim eout" 
 
LOG.info("Resume TD guest")  
inst.resume()  
ret = inst.wait_for_state(VM_STATE_RUNNING)  
assert ret, "Resume timeout"  
• Example 2: Customize the VM  
import logging  
import psut il 
# Get host total cores and sockets, assign 80% vcpu and 80% memory to vm  
total_core = psutil.cpu_count()  
cores = int(total_core * 0.4)  
memsize = int(psutil.virtual_memory().available / 1000 * 0.8)  
vmspec = VMSpec(sockets=2, cores=cores, memsize=memsize)  
inst = vm_factory.new_vm(VM_TYPE_TD, vmspec=vmspec, auto_start=True)  
• Example 3:  Run Tensor Flow AI microbench boosted by AMX within TDVM  
LOG.info("Create TD guest to test tensorflow")  
td_inst = vm_factory.new_vm(vm_type, vmspec=VMSpec.model_large())  
 
# customize the VM image  
td_inst.image.inject_root_ssh_key(vm_ssh_pubkey)  
 
# create and start VM instance  
td_inst.create()  
td_inst.start()  
td_inst.wait_for_ssh_ready()  
 
# It may take up to 30 minutes to complete the test  
LOG.info("====== The test running may ta ke up to 30 minutes!  ======")  
 
command = '''  
cd /root/models -2.5.0 && DNNL_MAX_CPU_ISA=AVX512_CORE_AMX OMP_NUM_THREADS=16 
KMP_AFFINITY=granularity=fine,verbose,compact 
python3 ./benchmarks/launch_benchmark.py  
    --model-name dien  --mode inference  --precision bfloat16  
    --framework tensorflow --data-location /root/dien  
    --exact-max-length=100 --num-inter-threads 1  --num-intra-threads 16  
    --batch-size 8 --graph-type=static  
    --in-graph /root/dien_fp32_static_rnn_graph.pb  
    --benchmark -only --verbose -- 
     ''' 
   
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runner = td_inst.ssh_run(command.split(), vm_ssh_key)  
assert runner.retcode == 0, "Failed to execute remote command"  
 
# throughput should not be 0  
patt_ok = r'Approximate accelerator performance in recommendations/second is 
(\d*.\d*)' 
match = re.search(patt _ok, '\n'.join(runner.stdout))  
assert match is not None  
images_per_s = match.group(1)  
LOG.info('Throughput: %s recommendations/s', images_per_s)  
assert float(images_per_s) > 0  
 
5.3  Intel TDX Tests  
Intel TDX tests  from tdx -tools  are designe d to cover basic acceptance tests, 
functionality, workload , and  environment tests for Intel TDX. It also provides 
interoperability tests by using AMX in  an Intel TDX  guest VM . 
NOTE : The tests implementation depends o n the  PyCloudStack framework. The 
test execution must be on  an Intel TDX -enabled Linux platform with  an Intel TDX -
enabled kernel  with  QEMU  and  Libvirt installed.  
NOTE: Please make sure to use  the correct tag  of tdx -tools  which matches the 
release version  so that the tests  can work with di fferent Intel TDX kernel and Intel 
TDX QEMU  versions.  
5.3.1  Overview

5.3.1  Overview  
The tests can be classified  into  4 categories – Lifecycle, Environment, Workload and 
Interoperability. Refer to the test  list i n the table  below.  Some of the tests require a 
customize d gues t image before running the test . The required prerequisites are in 
the next section.  
Table 7: TDX  Stack Tests  
Category  Test case  Description  
Lifecycle  test_tdvm_lifecycle.py  TD lifecycle management  
test_multiple_tdvms.py  Co -existe nce of multiple TD s 
test_vm_coexists.py  Co-existence  0f TD and legacy VM  
test_max_cpu.py  Boot TD with high  CPU utilization  
test_vm_shutdown_mode.py  Different  shutdown mode s of Libvirt  
test_acpi_reboot.py  TD ACPI reboot  
test_acpi_shutdown.py  TD  ACPI shutdown  
test_vm_shutdown_qga.py  VM shutdown via QEMU  guest agent     
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test_vm_reboot_qga.py  VM reboot via QEMU  guest agent  
Environment  test_tdvm_tsc.py  TD  TSC clock source and frequency  
test_tdx_guest_status.py  TDX initialization in TD guest  
test _tdx_host_status.py  Check TDX host status  
test_tdvm_network.py  Check network functions in TD  
Workload  test_workload_redis.py  Redis workload running in TD  
test_workload_nginx.py  Nginx workload running in TD  
Interoperability  test_amx_docker_tf.py  Run A I model with AMX in docker 
container on TD  
test_amx_vm_tf.py  Run AI model with AMX in TD  
 
A full example for a redis workload test case  is as follows . 
def test_tdvm_redis(vm_factory, vm_ssh_pubkey, vm_ssh_key):  
    """ 
    Run redis benchmark test  
    Ref: https://redis.io/topics/benchmarks  
    Use official docker images redis:latest  
    Test Steps:  
    1. start VM  
    2. Run remote command "systemctl status docker" to check docker service's 
status 
    3. Run remote command "systemctl start docker" to force start docker service  
    4. Run rem ote command "/root/bat -script/redis -bench.sh"  
       to launch redis container and  benchmark testing  
    """ 
    LOG.info("Create TD guest to run redis benchmark")  
    td_inst = vm_factory.new_vm(VM_TYPE_TD)  
 
    # customize the VM image  
    td_inst.image .inject_root_ssh_key(vm_ssh_pubkey)  
    td_inst.image.copy_in(  
        os.path.join(CURR_DIR, "redis -bench.sh"), "/root/")  
 
    # create and start VM instance  
    td_inst.create()  
    td_inst.start()  
    td_inst.wait_for_ssh_ready()  
 
    command_list = [  
        'systemctl start docker',  
        '/root/redis -bench.sh -t get,set'  
    ] 
    for cmd in command_list:  
        LOG.debug(cmd)  
        runner = td_inst.ssh_run(cmd.split(), vm_ssh_key)  
        assert runner.retcode == 0, "Failed to execute remote command"  
    
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5.3.2  Prerequisite s 
A g uest image is require d for all the tests. Refer  to “Chapter 2.4.2 Create Guest 
Image” to generate  a basic guest image. Additional prerequisites  are  required  for 
some of the tests.  The first step is to s tart a VM using the guest image built above 
and  go through  corr esponding items required by tests . The  next step is to  shut  
down the VM and use the guest image for further tests.  
1. Instal l QEMU  guest agent in guest image . 
For Ubuntu 22.04 guest image : 
$ sudo apt-get install qemu-guest-agent 
For RHEL 8.x guest ima ge: 
$ sudo dnf install  qemu-guest-agent 
2. Install docker in guest image .  
For Ubuntu 22.04 guest image:  
$ sudo apt-get install docker.io 
For RHEL 8.x guest image:  
$ sudo dnf install docker  
3. For workload tests, make sure the latest docker image is in the guest image . It 
needs  both the  docker image “nginx:latest ”  and  “redis:latest ”.  
$ docker pull nginx:latest  
$ docker pull redis:latest  
4. Install intel-tensorflow -avx512  in guest image. Download the DIEN_bf16 
model and put it under /root in  the  guest image.  
For ubuntu 22.04 guest image : 
$ pip3 install intel-tensorflow -avx512==2.11.0  
$ wget https://storage.googleapis.com/intel -optimized -
tensorflow/models/v2_5_0/dien_bf16_pretrained_opt_model.pb  
For RHEL 8 .x guest image , upgrade python to python 3.8 first  and then run 
the following command s:    
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$ pip3 instal l intel-tensorflow -avx512==2.11.0  
 
5.3.3  Setup Environment  
1. Install required packages:  
If your host dist ro is Ubuntu 22.04:  
$ sudo apt install python3-virtualenv python3 -libvirt libguestfs -dev libvirt -dev 
python3-dev net-tools 
If your host distro is RHEL 8 .x: 
$ sudo dnf install python3 -virtualenv python3 -libvirt libguestfs -devel libvirt -
devel python3 -devel gcc gcc-c++ 
2. Make sure  the  libvirt service is started. If not, start libvirt service.  If the  host is 
Ubuntu 22.04 and AppArmor is enabled, set security_driver = "none"  
in /etc/libvirt/ QEMU .conf and restart the libvirt  service . 
$ sudo systemctl status libvirtd  
$ sudo systemctl restart libvirtd  
3. Setup environment . Run  the  below command to setup the python 
environment . 
$ cd tdx-tools/tests/  
$ source setupenv.sh  
4. Create  artifacts.yaml  from template  
Refer  template <tdx-tools>/tests/artifacts.yaml.template  to 
create  <tdx-tools>/tests/artifacts.yaml . Update  
the  source  and  sha256sum  to indicate the lo cation of guest image and guest 
kernel.  See following example:  
latest-guest-image-rhel: 
  source: http://cpss -devops.sh.intel.com/download/tdx -guest/latest/td -guest-
rhel8.7.qcow2.tar.xz  
  sha256sum: http://css -devops.sh.intel.com/download/tdx -guest/lates t/td-guest-
rhel8.7.qcow2.tar.xz.sha256sum  
 
latest-guest-kernel-rhel: 
  source: http://css -devops.sh.intel.com/download/tdx -guest/latest/vmlinuz -rhel8.7 
  sha256sum: http://css -devops.sh.intel.com/download/tdx -guest/latest/vmlinuz -
rhel8.7.sha256sum  
   
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latest-guest-image-ubuntu: 
  source: http://css -devops.sh.intel.com/download/tdx -guest/latest/td -guest-
ubuntu-22.04-test.qcow2.tar.xz  
  sha256sum: http://css -devops.sh.intel.com/download/tdx -guest/latest/td -guest-
ubuntu-22.04-test.qcow2.tar.xz.sha256sum  
 
latest-guest-kernel-ubuntu: 
  source: http://css -devops.sh.intel.com/download/tdx -guest/latest/vml inuz-jammy 
jammy.sha256sum  
5. Generate keys  
Generate a pair of keys that will be used in te st running.  
$ ssh-keygen 
The keys should be named "vm_ssh_test_key" and "vm_ssh_test_key.pub" 
and located under tdx -tools/tests/tests/  
5.3.4  Run Tes ts 
1. Run all tests:  
$ sudo ./run.sh -s all 
$ # NOTE:  
$ # “sudo” is required  since some tests need root permission . 
$ # The user need s to be added into  the libvirt group. e.g., for user "root " 
$ # please run  
$ sudo usermod -aG libvirt root  
2. Run some case modules : 
$ ./run.sh -c <test_module1> -c <test_module2>  
For example,  run  the  whole test mo dule “ test_tdvm_lifecycle.py ”. 
$ ./run.sh -c tests/test_tdvm_lifecycle.py  
 
3. Run specific  test  cases:   
$ ./run.sh -c <test_module1> -c <test_module1>::<test_name>  
For example,  run  the  test case “test_tdvm_lifecycle_virsh_start_shutdown ” in 
“tests/test_tdvm_lifecyc le.py” 
$ ./run.sh -c tests/test_tdvm_li fecycle.py :: 
test_tdvm_lifecycle_virsh_start_shutdown  
    
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4. User can specify guest image OS type with  “-g”. Currently “rhel” and  “ubuntu” 
are supported .  Ubuntu 22.04  guest image will be  used by default if  “-g” is not 
specified . 
For example,  run all the tests using an RHEL 8.x guest image.  
$ sudo ./run.sh -g rhel -s all 
 
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6 Develop & Debug  
6.1 Override  the Intel TDX module  
Secure arbitration mode (SEAM) is an extension to the virtual machines extension 
(VMX) architecture to define a new VMX root operation called SEAM VMX root and 
a new VMX non -root operation called SEAM VMX non -root. Collectively, the SEAM 
VMX root and SEAM VMX non -root execution modes are called operation s in 
SEAM. SEAM VMX roo t operation is designed to host a CPU -attested , software 
module called the Intel® Trust -Domain  Extensions (Intel® TDX) module to manage 
virtual machine (VM) guests called Trust Domains (TD).  Currently, the Intel TDX 
Module is the only SEAM module that the  Intel P -SEAM LDR installs  [1]. 
By default, BIOS load s the built -in version of TDX Loader and TDX module from the 
IFWI  during the server booting . For  development or upgrading purpose  without re -
flashing the BIO S, a debug or new  version SEAMLDR and TDX module could be  
placed into the ESP partition . The BIOS load s the new or debug version from ESP 
on the next boot.   
   
Figure 32: BIOS Search TDX Module from ESP  
The naming rule is:  
   
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• <ESP>/EFI/TDX/TDX -SEAM_SEAMLDR.bin  
• <ESP>/EFI/TDX/TDX -SEAM.so

• <ESP>/EFI/TDX/TDX -SEAM.so  
• <ESP>/EFI/TDX/TDX -SEAM.so.sigstruct  
 
Check the updated TDX module information . 
# It will display a string including version information of tdx module, such as 
major version, monir version , build date, etc. 
 
$ sudo cat /sys/firmware/tdx/tdx _module/* 
0x00000000202302060x000001c90x000000010x00000000initialized0x00008086  
     
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6.2 Off -TD Debug via GDB from the Host  
QEMU  supports working with gdb via gdb’s remote -connection facility (the 
“gdbstub”). Thi s allows you  to debug guest code in the same way that you  might do 
with a low -level debug facility like JTAG on real hardware. You  can stop and start the 
virtual machine, e xamine state s like registers and memory, and set breakpoints and 
watchpoints.  Refer to https://www. QEMU .org/docs/master/system/gdb.html  for 
detail ed gdb usage.  
To support gdb  the  Intel TDX module expose s the following  API s: 
• TDH.VP.RD/WR to allow QEMU  emulator to read/ write guest’s CPU states . 
• TDH.MEM.RD/WR to allow QEMU  emulator to read/write gue st memory.  
 
Figure 33: Off -TD Debug via GDB  
Steps to debug TD guest are as follows:  
• Step 1: Start TD guest in debug mode  
o Append “ debug=on ” to “ -object”. For example:  
-object tdx -guest,id=tdx,debug=on  
o Add -s -S parameter to qemu -kvm . For example:  
$ qemu-kvm -s –S 
o Disable kernel address randomization  by append “nokaslr” 
   
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o If booting TD via start -qemu.sh , please refer to below command  to set 
“debug=on” : 
$ ./start-qemu.sh -i <guest image> -k <guest kernel> -d 
• Step 2: Install the guest kernel’s debug symbol into the host.  
$ sudo dnf install intel-mvp-tdx-guest-kernel-debuginfo  
• Step 3: Run the script start_gdb.sh with  the  following content . 
#!/bin/b ash 
GDB=gdb 
MOD_DIR=/usr/lib/debug/usr/lib/modules/<guest kernel>/  
$GDB \ 
-ex "add-auto-load-safe-path $MOD_DIR" \ 
-ex "file $MOD_DIR/vmlinux" \ 
-ex "set arch i386:x86 -64:intel" \ 
-ex "set remotetimeout 360" \ 
-ex "target remote 127.0.0.1:1234“  
• Step 4: In the GDB console, use command “hb” to set the first break point.  
gdb> hb start_kernel  
The software breakpoint is available after the kernel is loaded into Guest Physical 
Address ( GPA ) space by QEMU . 
     
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6.3 Check Memory Encryption  
There are lots of approa ches t o check whether TDX memory is encrypted or not. 
This section introduce s how to do this check via a GDB debug approach.  
1. Install the kernel development package on the host for debug symbol s (using 
RHEL distro as example):  
$ sudo dnf install intel-mvp-tdx-kernel-devel 
2. Get the GVA  (guest virtual  address ) of the .text  code section of guest 
kernel . 
$ # Extract the guest kernel binary  
$ /usr/src/kernels/$(uname -r)/scripts/extract -vmlinux <path -to-guest-kernel-
file > vmlinux  
$ objdump -d vmlinux >  disassem bled-vmlinux.asm && head -n 20 disassembled -
vmlinux.asm  
... 
ffffffff81000000 <.text>:  
ffffffff81000000:   48 8d 25 51 3f c0 01    lea   0x1c03f51(%rip),%rsp  
ffffffff81000007:   48 8d 3d f2 ff ff ff    lea   -0xe(%rip),%rdi  
ffffffff8100000e:   56                      push %rsi  
ffffffff8100000f:   e8 dc 06 00 00          callq 0xffffffff810006f0  
... 
 The result shows that the virtual address of .text  section start s from 
0xffffffff81000000 . 
3. Verify the instructions /memory  at the guest physical address of the  .text 
code section in a non -confidential VM guest.  
➢ Launch a non -confidential guest , nokaslr  should be appended for kernel 
command like below  to turn off the Kernel Address Space  Layout  
Randomization (KASLR).  
-append "root=/dev/vda1 console=hvc0  nokaslr"  
➢ Ent er QEMU  monitor shell  
If using start -qemu.sh, just “ telnet 127.0.0.1 9001 ” 
➢ Disassemble the virtual address of  the  .text section  
(QEMU) stop 
(QEMU) x /10i 0xffffffff81000000  
0x01000000:  48 8d 25 51 3f c0 01     leaq     0x1c03f51(%rip), % rsp 
0x01000007:  48 8d 3d f2 ff ff ff     leaq     -0xe(%rip), %rdi  
0x0100000e:  56                       pushq    %rsi  
0x0100000f:  e8 dc 06 00 00           callq    0x100 06f0 
    
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4. Verify the instructions/memory at guest physical address of .text code 
section  in a TD  guest . 
➢ Launch a TD guest  
o debug=on should be append ed for QEMU  command line  
o nokaslr  should be appended for kernel command line  
-append "root=/dev/vda1 console=hvc0 nokaslr"  
➢ Enter QEMU  monitor shell  
If using  start -QEMU.sh, just “ telnet 127.0.0.1 9001 ” 
➢ Disassemble the virtual address of .text section  
0xffffffff81000000:  98                       cwtl  
0xffffffff81000001:  f8                       clc  
0xffffffff81000002:  49 5e                    popq     %r14  
0xffffffff81000004:  5a                       popq     %rdx  
0xffffffff810 00005:  55                       pushq    %rbp  
... 
The disassembled instructions should be differ ent  from  a non -confidential  guest 
and should look  meaningless  (all zero)  since the memory is encrypted.  
6.4 Run Intel AMX workload within TDX Guest  
Intel AMX is a new built -in accelerator that improves the performance of deep -
learning training and inference on the CPU . This  is ideal for workloads like natural -
language processing, recommendation systems , and image recognit ion.13 It is 
available on the 4th Gen Intel® Xeon® Scalable processors . Use the following 
approach to check its capability on the host server and TD guest . 
$ grep -o amx /proc/cpuinfo  
Expect to see output of several  "amx". Empty results mean Intel AMX is not enabled.  
This section introduces how to run AI workload boosted by Intel AMX within  an Intel 
TDX gues t. This offers another layer of security over traditional VM’s to p rotect the  
model data while it is being used.  
• Install the Intel® Optimization for TensorFlow * version 2.8.0 via pip. Python 
versions supported are 3.7, 3.8, 3.9, 3.10. For TensorFlow versions 1.13, 1.14 
 
13 Intel® Advanced Matrix Extensions Overview     
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and 1.15 with pip > 20.0, if you get an  “invalid whee l error”, try to downgrade 
the pip version to < 20.0  
$ dnf install  python3 
$ python -m pip3 install intel -tensorflow -avx512==2.8.0  
• Download a pre -trained model . 
$ wget https://storage.googleapis.com/intel -optimized -tensorflow/models/v1_8/  
mobilenet_ v1_1.0_224_frozen.pb  
• Clone the intelai/models repo and then navigate to the benchmark  directory . 
$ dnf install git  
$ git clone https://github.com/IntelAI/models.git cd models/ benchmarks  
• Intel ® Optimization for TensorFlow  use s Intel ® oneAPI Deep Neural Netw ork 
Library (oneDNN)  and OpenMP  library . The DNNL_MAX_CPU_ISA 
environment variable can be used to limit processor features for oneDNN , it 
should be set to AVX512_CORE_AMX  to use AMX features.   The 
OMP_NUM_THREADS and KMP_AFFINITY  environment variable s set the 
number of threads and thread affinity  for OpenMP library . Set these  
environment variables . 
$ export DNNL_MAX_CPU_ISA=AVX512_CORE_AMX  
$ export OMP_NUM_THREADS=16  
$ export KMP_AFFINITY=granularity=fine,verbose,compact  
• Run online inference. Replace <PA TH>  to the absolute path where  the  pre -
trained model is located . 
$ python3 launch_benchmark.py \ 
--benchmark -only --framework tensorflow --model-name mobilenet_v1 \ 
--mode inference --precision bfloat16 --batch-size 1 \ 
--in-graph /opt/mobilenet_v1_1.0_2 24_frozen.pb \ 
--num-intra-threads 16 --num-inter-threads 1 --verbose --\ input_height=224 
input_width=224 warmup_steps=20 steps=20 \ input_layer='input' 
output_layer='MobilenetV1/Predictions/Reshape_1'  
• The result will look like the following.   
[Running wa rmup steps...]  
steps = 10, 360.33539518900346 images/sec steps = 20, 349.292471685543 images/sec 
[Running benchmark steps...]  
steps = 10, 364.1521097412745 images/sec steps = 20, 369.8028566390407 images/sec  
Average Throughput: 364.37 images/s on 20 iterat ions 
If running same workload without “ export 
DNNL_MAX_CPU_ISA=AVX512_CORE_AMX ”, the result wil l be  a 
noticeably  smaller (images/sec)  because AMX is not being used to 
accelerate .    
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NOTE: If you fail to run above comman ds and see a message like "If you cannot  
immediately regenerate your protos, some other possible workarounds are: 1. 
Downgrade the protobuf package to 3.20.x or lower. 2. Set 
PROTOCOL_BUFFERS_PYTHON_IMPLEMENTATION=python (but this will use 
pure -Python pars ing and will be much slower)." you have two options.  Option 1 is to 
upgrade the protobuf version to 3.20.0 as following:  
$ pip3.8 install --upgrade protobuf==3.20.0  
Option 2 is to  set  the  environment variable as following  
$ export PROTOCOL_BUFFERS_PYTHON_IMPLEMENTATION=python  
Then re -run above online inference command.

Then re -run above online inference command.  
 
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7 Disclaimer  
The released components of the Linux Reference Stack for Intel TDX: Virtual 
Firmware (edk2/TDVF), bootloader (grub2), and the Linux kernel, are fully en abled 
to be run from within the Linux -based Intel TDX Guest VM t o take advantage of the 
Intel TDX security technology for cryptographically isolating Trusted VMs from the 
rest of the system.  
While Intel TDX removes the need for a Guest VM to trust the host  and virtual 
machine manager (VMM), it cannot by itself protect the guest VM from host/VMM 
attacks that leverage existing paravirt -based communication interfaces between 
the host/VMM and the guest (such as MMIO, portIO, etc .). To achieve the full 
protectio n against such attacks, the Guest VM SW stack needs to be harden ed to 
securely handle a untrusted and potentially malicious input from a host/VMM via the 
above -mentioned interfaces. This hardening effort is not specific to Intel TDX as a 
technology, but co mmon for all confidential cloud computing solutions and the 
comp onents of the VM guest SW stack. It should be an industry -wide effort 
together with the open -source  maintainers to perform the security analysis and 
hardening of these components fo r the confidential computing threat model.  
The Linux Reference S tack for Intel TDX team has invested a significant effort in 
hardening the Linux kernel that is released as part of the Linux Reference Stack for 
Intel TDX , the  threat model for the Linux guest kernel , as well as the i mplemented 
mitigation mechanisms ar e explained in the  Intel TDE Linux guest kernel security 
specification. The overall hardening methodology, as well as documentation on the 
tools that have been used can be found in Inte l TDE guest Linux kernel hardening 
strategy. As a result , the Linux Ref erence Stack for Intel TDX kernel tree contains 
numerous patches that either implement these hardening mechanisms or fix the 
security issues that were discovered during the hardening pr ocess. It is strongly 
recommended that all these patches are manually c arried forward to the intended 
production kernels, until they are merged into the mainline Linux kernel and will 
become part of the upstream base kernel tree. In particular, the followi ng two 
patches that are critical for the security of the Intel TDX Linu x guest kernel must be 
included in any production guest kernel:  
Commit ID:  
• c942fc241d4e6c215731b6f03740b1a8bfc42018 from patches -tdx -
kernelMVP -KERNEL -5.19 -v2.4.tar.gz     
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• Commit ID: c289330c56c61508a1008d74fc65b7bc24a4a7d5 from 
patches -tdx -kernelMVP -KERNEL -5.19 -v2.4.tar.gz  
It is important to note that the hardening of the Linux guest kernel has not been 
finalized for this release and other components, such as virtual firmware 
(edk2/TDVF) and the bootloader (grub2), still need more attention. In particular , 
the existing interfaces that edk2/TDVF or grub2 expose towards the host/VMM 
have not yet been analyzed for potential security implications against the 
con fidential cloud computing threat model. It is strongly recommended that  this 
analysis be done, and any issues uncovered are mitigated before these components 
are used in productio n. 
 
82       Document Number: 355388 -001  
 
8 References  
 
[1]  Intel, "Intel® TDX White Papers," February 2023. [Online]. Available: 
https://www.intel.com/content/www/us /en/developer/articles/technical/intel -
trust -domain -extensions.html.  
[2]  Intel, "TDX Guest Hardening," [Online]. Available: https://intel.github.io/ccc -
linux -guest -hardening -docs/tdx -guest -hardening.html.  
[3]  Confidential Computing Consortium, "A Techn ical Analysis of Confidential 
Computing," 2022.  
[4]  Trust Computing Group, TCG Guidance on Integrity Measurements and Event 
Log, 2021.  
 
Intel® Trust Domain Extensions (Intel® TDX) Module 
Application Binary Interface (ABI) Incompatibilities 
between TDX 1.0 and TDX  1.5 
 
354808 -003US 
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Intel TDX ABI 1.5 -1.0 Incompatibilities  Notices and Disclaimers  
   Intel TDX ABI 1.5 -1.0 Incompatibilities  354808 -003US  
November 2023  . Page 3 of 10 
Intel TDX ABI 1.5 -1.0 Incompatibilities  Table of Contents  
1. About this Document  ................................ ................................ ................................ ................................ ............  4 
1.1. Scope of this Document  ................................ ................................ ................................ ................................ ........  4 
1.2. Glossary ................................ ................................ ................................ ................................ ................................ . 4 
1.3. Notation  ................................ ................................ ................................ ................................ ................................  4 5 
1.4. References  ................................ ................................ ................................ ................................ .............................  4 
2. TDX Module Enumeration  ................................ ................................ ................................ ................................ ..... 5 
2.1. Host -Side TDX Module Enumeration  ................................ ................................ ................................ .....................  5 
2.2. Guest -Side TDX Environment Enumeration  ................................ ................................ ................................ ...........  5 
3. TD Configuration  ................................ ................................ ................................ ................................ ...................  6 10 
3.1. CPUID Configuration  ................................ ................................ ................................ ................................ .............  6 
4. SEAMCALL and TDCALL Completion Status  ................................ ................................ ................................ ...........  7 
4.1. Background  ................................ ................................ ................................ ................................ ...........................  7 
4.2. TD Operation State (OP_STATE)  ................................ ................................ ................................ ............................  8 
4.3. Secure EPT Entry State  ................................ ................................ ................................ ................................ ..........  8 15 
4.4. TDH.VP.ENTER Completion Status  ................................ ................................ ................................ ........................  8

4.4. TDH.VP.ENTER Completion Status  ................................ ................................ ................................ ........................  8 
4.5. Other Completion Status Incompatibilities  ................................ ................................ ................................ ...........  8 
5. TD Entry and Exit ................................ ................................ ................................ ................................ ...................  9 
5.1. TD Exits without VMX Exit Information  ................................ ................................ ................................ .................  9 
5.2. Host Recoverability Hint  ................................ ................................ ................................ ................................ ........  9 20 
6. Concurrency Enforcement  ................................ ................................ ................................ ................................ .... 10 
6.1. Host -Priority Locks  ................................ ................................ ................................ ................................ ..............  10 
6.1.1.  Background  ................................ ................................ ................................ ................................ .................  10 
6.1.2.  Host -Side Operation ................................ ................................ ................................ ................................ .... 10 
6.1.3.  Guest -Side Operation ................................ ................................ ................................ ................................ .. 10 25 
6.1.4.  Backward Compatibility Impact  ................................ ................................ ................................ ..................  10 
  Intel TDX ABI 1.5 -1.0 Incompatibilities  354808 -003US  
November 2023  . Page 4 of 10 
Intel TDX ABI 1.5 -1.0 Incompatibilities  1. About this Document  
This document describes incompatibilities between the Application Binary I nterface (ABI) of the Intel ® Trust Domain 
Extensions  (Intel ® TDX) module , as defined for TDX 1.0 and for TDX 1.5 .  Such incompatibilities may require the host VMM 
s/w and/or guest TD s/w that has been written for TDX 1.0 to be updated for use with TDX 1.5.  5 
 TDX Module  
 TDX Module  
 TDX Module  
 TDX Module  
→ TDX Module ABI Incompatibilities  [TDX Module ABI 
Incompatibilities ] Description of the incompatibilities 
 
occur.  
1.2. Glossary  15 
See the [ TDX Module Base Spec ]. 
1.3. Notation  
1.4. References  
See the [ TDX Module Base Spec ]. 20  Intel TDX ABI 1.5 -1.0 Incompatibilities  354808 -003US  
November 2023  . Page 5 of 10 
Intel TDX ABI 1.5 -1.0 Incompatibilities  2. TDX Module Enumeration  
TDX Module 1.5 feature enumeration is forward compatible with TDX Module 1.0.  
2.1. Host -Side TDX Module Enumeration  
In TDX 1.0, once the TDX module has been initialized by TDH.SYS.INIT and at least one LP has been initialized by 
TDH.SYS.LP.INIT, TDH.SYS.INFO could be called to return a fixed -format TDSYSINFO_STRUCT, which enumerated various 5 
TDX module features and configuration.  
A host VMM that is not aware of TDX 1.5 can still use the above enumeration method with TDX module version 1.5 or 
later.  
However, In TDX 1.5, the fixed format of TDSYSINFO_STRUCT prevented adding all the new  information  required for TDX 
1.5 features .  Thus, a host VMM that is aware of TDX 1.5 should use the  new interface functions TDH.SYS.RD and 10 
TDH.SYS.RDALL.  These functions use the metadata interface convention and can be used to read one or more global 
metadata fields.  A single field has been added to TDSYSINFO_STRUCT to indicate the availability of the new functions.  
a host VMM that is aware of TDX 1.5 can use the following method to enumerate the TDX module:  
1. Execute TDH.SYS.INIT  
2. Execute TDH.SYS.LP.INIT  15 
3. If the host VMM suspect s that the TDX module version may be 1.0:  
3.1. Execute TDH.SYS.INFO to read the TDSYSINFO_STRUCT.  
3.2. If TDSYSINFO_STRUCT.SYS_RD is 0, this is a TDX 1.0 module.  Else, it’s a TDX 1.5 or newer module.  
4. If the TDX module version is 1.5  or newer : 
4.1. Execute TDH.SYS.RD or TDH.SYS.RDALL to read the TDX module’s functionality and configuration.  20 
The host VMM should not rely on the TDX module version information provided in TDSYSINFO_STRUCT.  Any update to 
the TDX module from the TDX 1.0 baseline is enumerated by the global fields read by TDH.SYS.RD*.  
For further details, see the [TDX Module Base Spec] section on TDX module enumeration.  
2.2. Guest -Side TDX Environment  Enumeration  
In TDX 1.0, a TD could call TDG.VP.INFO to enumerate a few configuration variables that were not available via the 25 
architectural means (CPUID, MSRs).  
A guest TD that is not aware of TDX 1.5 can still use the above enumeration method with TDX module version 1.5 or later.  
However, In TDX 1.5, the fixed format of TDG.VP.INFO prevented adding all the required information.  Instead, new 
interface functions TDG.SYS.RD and TDG.SYS.RDALL have been added.  These functions use the metadata interface 
convention and can be used to read one or  more global metadata fields.  A single field has been added to TDG.VP.INFO’s 30 
return values to indicate the availability of the new functions.  
a guest TD that is aware of TDX 1.5 can use the following method to enumerate its run time environment : 
1. Execute TDG.VP.INFO  
1.1. If R10.SYS_RD (bit 0) is 0, the TD is running in a TDX 1.0 environment.  Else, the TD is running in a TDX 1.5 or 
newer environment.  35 
2. If the TD is running in a TDX 1.5 or newer environment:  
2.1. Execute TDG.SYS.RD or TDG.SYS.RDALL to read the TDX module’s functionality and configuration.  
Any update from the TDX 1.0 baseline is enumerated by the global fields read by TDG.SYS.RD*.  
Examples of new guest -side features that can be enumerated:  
• A Migration TD uses the Service TD guest -side API.  It should also determine if TD migration is supported.  40 
• Guest TD should understand if CPU ID virtualization guest control is available if  it wants to use that feature.  
• Guest TD should understand if TD partitioning is supported if  it wants to use that feature.  
• Guest TD should understand if local attestation is supported if  it wants to use that feature.  
For further details, see the [TDX Module Base Spec] section on guest TD run time environment enumeration.   Intel TDX ABI 1.5 -1.0 Incompatibilities  354808 -003US  
November 2023  . Page 6 of 10 
Intel TDX ABI 1.5 -1.0 Incompatibilities  3. TD Configuration  
3.1. CPUID Configuration  
TDX 1.0 Background  
In TDX 1.0, the virtualization of CPUID fields was configurable based on the TD configuration, as provided to 
TDH.MNG.INIT in the TD_PARAMS structure.  CPUID field could be configured based on the TD’s ATTRIBUTES and XFAM 5 
setting, or it could be based on direct configuration provided by the host VMM in TD_PARAMS.CPUID_CONFIG.  
The list of directly configurable CPUID bits is enumerated to the host VMM in TDX 1.0 in the TDSYSINFO_STRUCT output 
of TDH.SYS.INFO.  Even with TDX 1.0 the host VMM is required to consult this list in order to properly configure a TD  – 
this list is subject to change and  will change between TDX 1.0 minor releases.  
TDX 1.5 Updates  10

TDX 1.5 Updates  10 
To support TD migration, TDX 1.5 added the option for some CPUID bit fields to be configurable based on both 
CPUID_CONFIG and either XFAM or ATTRIBUTES sections of TD_PARAMS.  This is intended to support fine-grained 
virtualization of sub -features of extended features .  For example:  
• The host VMM can configure the TDX module to virtualize some AVX512 as available, but to virtualize other  AVX512 
instructions as unavailable.  15 
• The host VMM can configure the TDX module to virtualize the Perfmon architectural events support.  
This is useful for TD migration, as it allows the host VMM to configure a common subset of supported sub -features.  
From the host VMM’s perspective, the update means there are more configurable CPUID bits.  The list returned by 
TDH.DYD.INFO, or the equivalent CPUID_CONFIG_LEAVES and CPUID_CONFIG_VALUES read by TDH.SYS.RD*, 
enumerates those bits.  20 
For details, see the [TDX Module Base Spec] section on CPUID configuration by the host VMM.  
Backward Compatibility Impact  
A properly written VMM should be able to handle the fact that more CPUID bits become configurable . 
The host VMM should always consult the list of directly configurable CPUID leaves and sub -leaves, as enumerated by 
TDH.SYS.RD/RDALL or TDH .SYS.INFO.   If a CPUID bit is enumerated as configurable, and the VMM was not designed to 25 
configure that bit, the VMM should set the configuration for that bit to 1.  
If the host VMM neglects to configure CPUID bits that are configurable, their virtual value (as seen by guest TDs) will be 
0.  Intel TDX ABI 1.5 -1.0 Incompatibilities  354808 -003US  
November 2023  . Page 7 of 10 
Intel TDX ABI 1.5 -1.0 Incompatibilities  4. SEAMCALL and TDCALL Completion Status  
4.1. Background  
Completion status codes are returned in RAX by all SEAMCALL and TDCALL functions.  
The TDX 1.0 spec specifies the structure of status codes as follows:  5 
Table 4.1:  TDX 1.0 Interface Functions Completion Status (Returned in RAX)  
63 ERROR  Instruction aborted due to error . 
0: Indicates that the function  completed successfully – possibly with some 
warnings . 
1: Indicates that the function aborted due to some error . 
62 NON_RECOVERABLE  Recoverability hint – applicable only when ERROR  is 1.  
0: Indicates that the function  may possibly be retried after some conditions 
have been corrected.  
1: Indicates that the error is probably not recoverable.  
61:48  RESERVED  Reserved  – set to 0  
47:40  CLASS  Class of the function completion status  
39:32  DETAILS_L1  Details of the function completion status  
31:0  DETAILS_L2  Additional details of the function completion status – e.g., includes:  
• Implicit or explicit operand identifier  
• CPUID leaf or sub -leaf 
• MSR index  
• VMCS field code  
• VM exit reason  
• CMR index  
• TDMR index  
 
Properly written host VMMs and guest TDs should use the ERROR and NON_RECOVERABLE indications bits and the 
CLASS/DETAILS_L1/DETAILS_L2 fields.  They should ignore the RESERVED bits.  
TDX 1.4/ 1.5 Updates  10 
Two of the previously reserved bits are now used, as follows:  
Table 4.2:  New Bits in TDX 1.5 Interface Functions Completion Status (Returned in RAX)  
61 FATAL  Fatality hint – applicable only for SEAMCALL.  
0: Indicates that the TD can continue its normal lifecycle.  
1: Indicates that the TD entered a state where it can only be torn 
down.  E.g., when an import has failed and the TD’s OP_STATE is 
FAILED_IMPORT.   Intel TDX ABI 1.5 -1.0 Incompatibilities  354808 -003US  
November 2023  . Page 8 of 10 
Intel TDX ABI 1.5 -1.0 Incompatibilities  Bits Name  Description  
60 HOST_RECOVERABILITY_HINT  As a TDH.VP.ENTER output, indicates a TDCALL that resulted in a trap -
like TD exit for which the host VMM needs to provide a recoverability 
hint in the following TD entry.  
On the following TDH.VP.ENTER, the host VMM provides a hint to the 
guest TD, which is the output of the TDCALL:  
0: The host VMM hints that the guest -side function may possibly be 
retried (e.g., the host may have corrected some conditions).  
1: The host VMM hints that the error is probably not recoverable.  
 
There are many new status codes (CLASS/DETAILS_L1/DETAILS_L2 combinations).  
Properly written host VMMs and guest TDs should ignore the reserved bit; thus, they should not be confused by the 
newly defined bits 61 and 60.  5 
There could be compatibility issues in cases where interface functions return different status 
(CLASS/DETAILS_L1/DETAILS_L2 combinations) in TDX 1.5 than in TDX 1.0.  These are discussed below.  
4.2. TD Operation State (OP_STATE)  
To support TD migration, the operation state (OP_STATE) of the TD in TDX 1.5 is much more complicated than it was in 
TDX 1.0.  As a result, we no longer implement specific state check logic for most SEAMCALL interface functions, and do 10 
not provide a specific error code for most failure cases.  Instead, we have a generic table -driven check, and provide a 
generic TDX_OP_STATE_INCORRECT  status in case of failure.  
We expect the host VMM to not care about the failure reason.  For debug, it is possible to query the TD’s OP_STATE using 
TDH.MNG.RD.  
4.3. Secure EPT Entry State  15 
To support TD migration, the Secure EPT entry state in TDX 1.5 is much more complicated than it was in TDX 1.0.  As a 
result, we no longer implement specific state check logic for most interface functions, and do not provide a specific error 
code for most failure cases.  Instead, we have a generic table -driven check, and provide a generic 
TDX_EPT_ENTRY_STATE_INCORRECT  status in case of failure.  
As in TDX 1.0, TDX 1.5 also provides extended error information, which includes the Secure EPT entry architectural 20 
content, Secure EPT level and entry state of the Secure EPT entry where the error was detected.  
4.4. TDH.VP.ENTER Completion Status  
TDH.VP.ENTER has some new TD exit cases.  See  Ch. 5 for details.  
4.5. Other Completion Status Incompatibilities  
There are few other cases where error codes returned by TDX module interface functions have been enhanced or 25 
modified.  There error codes are not expected in normal operation.  They are only used in error cases and are intended 
for (human) debuggability.  
Specifically, TDX 1.4/1.5 support of TD metadata access has been greatly enhanced over TDX 1.0.  One size effect is that 
some error codes returned by TDH.MNG.RD/WR and TDH.VP.RD/WR have been modified and became more elaborate.  
 30 
November 2023  . Page 9 of 10 
Intel TDX ABI 1.5 -1.0 Incompatibilities  5. TD Entry and Exit  
5.1. TD Exits without VMX Exit Information  
In TDX 1.0, all TD exits (termination of TDH.VP.ENTER) returned an architectural  VM Exit Reason in the lower 32 bits of 
RAX.   In most cases except synchronous TD exits, other GPRs returned additional VM exit information.  5 
TDX 1.4/ 1.5 Updates  
TDX 1.4/1.5 adds multiple cases where TD exit (i.e., completion of TDH.VP.ENTER) does not return a  VM Exit Reason or 
any other VMX exit information.   
Table 5.1:  TD Exits without VMX Exit Information  
TDH.VP.ENTER Completion Status (in RAX)   
TDX_NON_RECOVERABLE_TD_CORRUPTED_MD  This error code is only expected if TD -preserving update 
(which is only used with VMMs that are aware of TDX 1.5) is 
used.   
TDX_HOST_PRIORITY_BUSY_TIMEOUT  See the discussion in 6.1. 
TDX_CROSS_TD_FAULT  Applicable to Service TDs.  A VMM that is not aware of TDX 
1.5 will not bind service TDs.  
TDX_CROSS_TD_ TRAP  Applicable to Service TDs.  A VMM that is not aware of TDX 
 10 
The specific cases are details in the [ TDX Module ABI Spec  Spec] TDH.VP.ENTER sections.  
5.2. Host Recoverability Hint  
TDX 1.4/1.5 adds the option of trap -like TD exits to set bit 60 of the TDH.VP.ENTER completion status in RAX as a host -
recoverability indicator.  This is used in cases where a TDCALL would return some error status to the guest TD, e.g., 
TDX_HOST_PRIORITY_BUSY_TIME OUT.  The host VMM can impact the value of this bit, as will be seen by the guest TD, 15 
by setting RCX bit 52 on the next call to TDH.VP.ENTER . 
Host recoverability is applicable for the following TDH.VP.ENTER completion status values:  
• TDX_CROSS_TD_TRAP :  Not expected to happen, see above.  
• TDX_HOST_PRIORITY_BUSY_TIMEOUT :  See the discussion in 6.1. 
 20  Intel TDX ABI 1.5 -1.0 Incompatibilities  354808 -003US  
November 2023  . Page 10 of 10 
Intel TDX ABI 1.5 -1.0 Incompatibilities  6. Concurrency Enforcement  
6.1. Host -Priority Locks  
6.1.1.  Background  
TDX 1.4/1.5 added a new host -priority locks mechanism to prevent DOS by guest TDs.  This is a variant on explicit 
concurrency restrictions, where the host VMM side is given priority over guest TD side.  A  new HOST_PRIORITY flag is 5

concurrency restrictions, where the host VMM side is given priority over guest TD side.  A  new HOST_PRIORITY flag is 5 
added to locks protecting resources that may be accessed by the host VMM and a guest TD.  Both mutexes and 
shared/exclusive locks can be enhanced with host priority.  
For details, see the [TDX Module Base Spec] section on concurrency restrictions with host priority.  
6.1.2.  Host -Side Operation  
The host VMM is expected to recognize the TDX_OPERAND_BUSY status returned by SEAMCALL operations; the VMM 10 
should retry the operation until succe ssful .  Failing to do so will prevent the guest TD from acquiring access to the busy 
resource, since it remains marked as “host priority”.  
As a bug detection mechanism, if the guest TD tries to acquire a resource that has been held as “host priority” for more 
than a pre -configured time, a TD exit will happen.  The returned status in this case is 
TDX_HOST_PRIORITY_BUSY_TIMEOUT . 15 
6.1.3.  Guest -Side Operation  
The guest TD is expected to recognize the TDX_OPERAND_BUSY status returned by TDCALL operations; the TD should 
retry the operation until successful.  
6.1.4.  Backward Compatibility Impact  
• The host VMM may not recognize TD exit with TDX_HOST_PRIORITY_BUSY_TIMEOUT . 20 Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Combined Volumes:
1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4
NOTE:  This document contains all four volumes of the Intel 64 and IA-32 Architectures Software
Developer's Manual: Basic Architecture , Order Number 253665; Instruction Set Reference A-Z , Order
Number 325383; System Programming Guide , Order Number 325384; Model-Specific Registers, Order
Number 335592. Refer to all four volumes when evaluating your design needs.
Order Number:  325462-082US
December 2023
Notices & Disclaimers
No product or component can be absolutely secure. Your costs and results may vary. 
You may not use or facilitate the use of this document in conn ection with any infringement or other legal analysis concerning 
the sole exception that a) you may publish an unmodified copy and b) code included in this document is licensed subject to 
the Zero-Clause BSD open source license (0BSD), https://opensource.org/licenses/0BSD . You may create software 
implementations based on this document and in compliance with the foregoing that are intended to execute on the Intel 
product(s) referenced in this document. No rights are granted to create mo difications or derivatives of this document.
names and brands may be claimed as the property of others.Intel® 64 and IA-32 Architectures Software
Developer’s Manual
Volume 1: Basic Architecture
NOTE:  The Intel 64 and IA-32 Architectures Software Developer's Manual cons ists of four volumes:
Basic Architecture , Order Number 253665; Instruction Set Reference A-Z , Order Number 325383;
System Programming Guide , Order Number 325384; Model-Specific Registers,  Order Number
335592. Refer to all four volumes wh en evaluating your design needs.
Order Number:  253665-082US
names and brands may be claimed as the property of others.Vol. 1 iiiCONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL
1.1 INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .  1-1
1.2 OVERVIEW OF VOLUME 1: BASIC ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-4
1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-6
1.3.1 Bit and Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.2 Reserved Bits and Software Compatibility  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.2.1 Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.3.3 Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.3.4 Segmented Addressing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.3.5 A New Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.3.6 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.4 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-9
CHAPTER 2
INTEL® 64 AND IA-32 ARCHITECTURES2.1 BRIEF HISTORY OF INTEL® 64 AND IA-32 ARCHITECTURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-1
2.1.1 16-Bit Processors and Segmentation (1978) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

CHAPTER 2
2.1.2 The Intel® 286 Processor (1982) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.3 The Intel386™ Processor (1985). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.4 The Intel486™ Processor (1989). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.5 The Intel® Pentium® Processor (1993). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .2-2
2.1.6 The P6 Family of Processors (1995—1999). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.1.7 The Intel® Pentium® 4 Processor Family (2000—2006). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.8 The Intel® Xeon® Processor (2001—2007)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .2-3
2.1.9 The Intel® Pentium® M Processor (2003—2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .2-3
2.1.10 The Intel® Pentium® Processor Extreme Edition (2005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.1.11 The Intel® Core™ Duo and Intel® Core™ Solo Processors (2006—2007). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.1.12 The Intel® Xeon® Processor 5100, 5300 Series, and Intel® Core™ 2 Processor Family (2006)  . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.1.13 The Intel® Xeon® Processor 5200, 5400, 7400 Series, and Intel® Core™ 2 Processor Family (2007) . . . . . . . . . . . . . . . . . . .2-4
2.1.14 The Intel Atom® Processor Family (2008)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .2-5
2.1.15 The Intel Atom® Processor Family Based on Silvermont Microarchitecture (2013)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . .2-5
2.1.16 The Intel® Core™ i7 Processor Family (2008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .2-5
2.1.17 The Intel® Xeon® Processor 7500 Series (2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
2.1.18 2010 Intel® Core™ Processor Family (2010)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.19 The Intel® Xeon® Processor 5600 Series (2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.20 The Second Generation Intel® Core™ Processor Family (2011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . .2-6
2.1.21 The Third Generation Intel® Core™ Processor Family (2012) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .2-6
2.1.22 The Fourth Generation Intel® Core™ Processor Family (2013). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
2.2 MORE ON SPECIFIC ADVANCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-7
2.2.1 P6 Family Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
2.2.2 Intel NetBurst® Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.2.1 The Front End Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
2.2.2.2 Out-Of-Order Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.2.3 Retirement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.3 Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.3.1 The Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.3.2 Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.4 Intel Atom® Microarchitecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.5 Nehalem Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.2.6 Sandy Bridge Microarchitecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.2.7 SIMD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.2.8 Intel® Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.2.8.1 Some Implementation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.2.9 Multi-Core Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18CONTENTS
ivVol. 1PAGE
2.2.10 Intel® 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.2.11 Intel® Virtualization Technology (Intel® VT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3 INTEL® 64 AND IA-32 PROCESSOR GENERATIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4 PLANNED REMOVAL OF INTEL® INSTRUCTION SET ARCHITECTURE  AND FEATURES FROM UPCOMI NG PRODUCTS. . . . . . 2-28
2.5 INTEL® INSTRUCTION SET ARCHITECTURE AND FEATURES REMOVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 2-28
CHAPTER 3
BASIC EXECUTION ENVIRONMENT
3.1 MODES OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-1
3.1.1 Intel® 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.2 OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-2
3.2.1 64-Bit Mode Execution Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

CHAPTER 3
3.3 MEMORY ORGANIZATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-6
3.3.1 IA-32 Memory Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.3.2 Paging and Virtual Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.3.3 Memory Organization in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.3.4 Modes of Operation vs. Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.3.5 32-Bit and 16-Bit Address and Operand Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.3.6 Extended Physical Addressing in Protected Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.3.7 Address Calculations in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.3.7.1 Canonical Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4 BASIC PROGRAM EXECUTION REGISTERS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.1 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.1.1 General-Purpose Registers in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.2 Segment Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.4.2.1 Segment Registers in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.3 EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.3.1 Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.4.3.2 DF Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.4.3.3 System Flags and IOPL Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.4.3.4 RFLAGS Register in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.5 INSTRUCTION POINTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.5.1 Instruction Pointer in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.6 OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.6.1 Operand Size and Address Size in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.7 OPERAND ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.7.1 Immediate Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.7.2 Register Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.7.2.1 Register Operands in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.7.3 Memory Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.7.3.1 Memory Operands in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.7.4 Specifying a Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.7.4.1 Segmentation in 64-Bit Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.7.5 Specifying an Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.7.5.1 Specifying an Offset in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.7.6 Assembler and Compiler Addressing Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.7.7 I/O Port Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
CHAPTER 4
DATA TYPES
4.1 FUNDAMENTAL DATA TYPES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-1
4.1.1 Alignment of Words, Doublewords, Quadwords, and Double Quadwords  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .4-2
4.2 NUMERIC DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-2
4.2.1 Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2.1.1 Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2.1.2 Signed Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.2.2 Floating-Point Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3 POINTER DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-6
4.3.1 Pointer Data Types in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7Vol. 1 vCONTENTS
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PAGE
4.4 BIT FIELD DATA TYPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-7
4.5 STRING DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-8
4.6 PACKED SIMD DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-8
4.6.1 64-Bit SIMD Packed Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.6.2 128-Bit Packed SIMD Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.7 BCD AND PACKED BCD INTEGERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-9
4.8 REAL NUMBERS AND FLOATING-POINT FORMATS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  4-11
4.8.1 Real Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.8.2 Floating-Point Format  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.8.2.1 Normalized Numbers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.8.2.2 Biased Exponent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.8.3 Real Number and Non-number Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.8.3.1 Signed Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.8.3.2 Normalized and Denormalized Finite Numbers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.8.3.3 Signed Infinities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.8.3.4 NaNs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.8.3.5 Operating on SNaNs and QNaNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.8.3.6 Using SNaNs and QNaNs in Applications  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.8.3.7 QNaN Floating-Point Indefinite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.8.3.8 Half Precision Floating-Point Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.8.4 Rounding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.8.4.1 Rounding Control (RC) Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.8.4.2 Truncation with Intel® SSE, SSE2, and AVX Conversion Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.9 OVERVIEW OF FLOATING-POINT EXCEPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .  4-19
4.9.1 Floating-Point Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.9.1.1 Invalid Operation Exception (#I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.9.1.2 Denormal Operand Exception (#D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.9.1.3 Divide-By-Zero Exception (#Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.9.1.4 Numeric Overflow Exception (#O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.9.1.5 Numeric Underflow Exception (#U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
4.9.1.6 Inexact-Result (Precision) Exception (#P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
4.9.2 Floating-Point Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4.9.3 Typical Actions of a Floating-Point Exception Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
CHAPTER 5
INSTRUCTION SET SUMMARY
5.1 GENERAL-PURPOSE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-5
5.1.1 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.1.2 Binary Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.1.3 Decimal Arithmetic Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.4 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.5 Shift and Rotate Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.6 Bit and Byte Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.7 Control Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.1.8 String Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.1.9 I/O Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.1.10 Enter and Leave Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.1.11 Flag Control (EFLAG) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.1.12 Segment Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.1.13 Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.1.14 User Mode Extended State Save/Restore Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.1.15 Random Number Generator Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.1.16 BMI1 and BMI2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.1.16.1 Detection of VEX-Encoded GPR Instructions, LZCNT, TZCNT, and PREFETCHW . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 5-11
5.2 X87 FPU INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-12
5.2.1 X87 FPU Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.2.2 X87 FPU Basic Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.2.3 X87 FPU Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.2.4 X87 FPU Transcendental Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13CONTENTS
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5.2.5 X87 FPU Load Constants Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.2.6 X87 FPU Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.3 X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.4 MMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.1 MMX Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.2 MMX Conversion Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.3 MMX Packed Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.4 MMX Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.4.5 MMX Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.4.6 MMX Shift and Rotate Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.4.7 MMX State Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.5 INTEL® SSE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.5.1 Intel® SSE SIMD Single Precision Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.5.1.1 Intel® SSE Data Transfer Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.5.1.2 Intel® SSE Packed Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.5.1.3 Intel® SSE Comparison Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.5.1.4 Intel® SSE Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.5.1.5 Intel® SSE Shuffle and Unpack Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.5.1.6 Intel® SSE Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.5.2 Intel® SSE MXCSR State Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.5.3 Intel® SSE 64-Bit SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.5.4 Intel® SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.6 INTEL® SSE2 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.6.1 Intel® SSE2 Packed and Scalar Double Precision Floating-Point Instructions  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-20
5.6.1.1 Intel® SSE2 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.6.1.2 Intel® SSE2 Packed Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.6.1.3 Intel® SSE2 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.6.1.4 Intel® SSE2 Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.6.1.5 Intel® SSE2 Shuffle and Unpack Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.6.1.6 Intel® SSE2 Conversion Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.6.2 Intel® SSE2 Packed Single Precision Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 5-22
5.6.3 Intel® SSE2 128-Bit SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.6.4 Intel® SSE2 Cacheability Control and Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.7 INTEL® SSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.7.1 Intel® SSE3 x87-FP Integer Conversion Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.7.2 Intel® SSE3 Specialized 128-Bit Unaligned Data Load Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.7.3 Intel® SSE3 SIMD Floating-Point Packed ADD/SUB Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 5-23
5.7.4 Intel® SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.7.5 Intel® SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-24
5.7.6 Intel® SSE3 Agent Synchronization Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.8 SUPPLEMENTAL STREAMING SIMD EXTENSIONS 3 (SSSE3) INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.8.1 Horizontal Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.8.2 Packed Absolute Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.8.3 Multiply and Add Packed Signed and Unsigned Bytes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.8.4 Packed Multiply High with Round and Scale  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.8.5 Packed Shuffle Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.8.6 Packed Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.8.7 Packed Align Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.9 INTEL® SSE4 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.10 INTEL® SSE4.1 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.10.1 Dword Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.10.2 Floating-Point Dot Product Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.10.3 Streaming Load Hint Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.10.4 Packed Blending Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.10.5 Packed Integer MIN/MAX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.10.6 Floating-Point Round Instructions with Selectable Rounding Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.10.7 Insertion and Extractions from XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.10.8 Packed Integer Format Conversions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28Vol. 1 viiCONTENTS
PAGE
5.10.10 Horizontal Search  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.10.11 Packed Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.10.12 Packed Qword Equality Comparisons  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.10.13 Dword Packing With Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.11 INTEL® SSE4.2 INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-29
5.11.1 String and Text Processing Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.11.2 Packed Comparison SIMD Integer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.12 INTEL® AES-NI AND PCLMULQDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-29
5.13 INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .  5-30
5.14 16-BIT FLOATING-POINT CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-30
5.15 FUSED-MULTIPLY-ADD (FMA)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-30
5.16 INTEL® ADVANCED VECTOR EXTENSIONS 2 (INTEL® AVX2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  5-31
5.17 INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS (INTEL® TSX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-31
5.18 INTEL® SHA EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-31
5.19 INTEL® ADVANCED VECTOR EXTENSIONS 512 (INTEL® AVX-512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-31
5.20 SYSTEM INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-36
5.21 64-BIT MODE INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-37
5.22 VIRTUAL-MACHINE EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-38
5.23 SAFER MODE EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-38
5.24 INTEL® MEMORY PROTECTION EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-39
5.25 INTEL® SOFTWARE GUARD EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-39

5.26 SHADOW STACK MANAGEMENT INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  5-40
5.27 CONTROL TRANSFER TERMINATING INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-40
5.28 INTEL® AMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-40
5.29 USER INTERRUPT INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-40
5.30 ENQUEUE STORE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-41
CHAPTER 6
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS6.1 PROCEDURE CALL TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-1
6.2 STACKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-1
6.2.1 Setting Up a Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.2 Stack Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.3 Address-Size Attributes for Stack Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4 Procedure Linking Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4.1 Stack-Frame Base Pointer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4.2 Return Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.5 Stack Behavior in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3 SHADOW STACKS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-4
6.4 CALLING PROCEDURES USING CALL AND RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-4
6.4.1 Near CALL and RET Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4.2 Far CALL and RET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.4.3 Parameter Passing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4.3.1 Passing Parameters Through the General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 6-7
6.4.3.2 Passing Parameters on the Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4.3.3 Passing Parameters in an Argument List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4.4 Saving Procedure State Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4.5 Calls to Other Privilege Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4.6 CALL and RET Operation Between Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.4.7 Branch Functions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.5 INTERRUPTS AND EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-12
6.5.1 Call and Return Operation for Interrupt or Exception Handling Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.5.2 Calls to Interrupt or Exception Handler Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.5.3 Interrupt and Exception Handling in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.5.4 INT n, INTO, INT3, INT1, and BOUND Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.5.5 Handling Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.5.6 Interrupt and Exception Behavior in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.6 PROCEDURE CALLS FOR BLOCK-STRUCTURED LANGUAGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-20
6.6.1 ENTER Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20CONTENTS
viii Vol. 1PAGE
6.6.2 LEAVE Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
CHAPTER 7
PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
7.1 PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  7-1
7.2 PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS IN 64-BIT MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7-1
7.3 SUMMARY OF GP INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7-2
7.3.1 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2
7.3.1.1 General Data Movement Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
7.3.1.2 Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.3.1.3 Exchange Instructions in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
7.3.1.4 Stack Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
7.3.1.5 Stack Manipulation Instructions in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7

7.3.1.6 Type Conversion Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
7.3.1.7 Type Conversion Instructions in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2 Binary Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.1 Addition and Subtraction Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.2 Increment and Decrement Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.3 Increment and Decrement Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.4 Comparison and Sign Change Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.3.2.5 Multiplication and Division Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.3.3 Decimal Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.3.3.1 Packed BCD Adjustment Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.3.3.2 Unpacked BCD Adjustment Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.3.4 Decimal Arithmetic Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.5 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.6 Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.6.1 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.6.2 Double-Shift Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.3.6.3 Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.3.7 Bit and Byte Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.3.7.1 Bit Test and Modify Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.7.2 Bit Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.7.3 Byte Set on Condition Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.7.4 Test Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.8 Control Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.8.1 Unconditional Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.8.2 Conditional Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.3.8.3 Control Transfer Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.3.8.4 Software Interrupt Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.3.8.5 Software Interrupt Instructions in 64-Bit Mode and Compatibility Mode. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 7-18
7.3.9 String Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.3.9.1 String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.3.9.2 Repeated String Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.3.9.3 Fast-String Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.3.9.4 String Operations in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.3.10 I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.3.11 I/O Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.3.12 Enter and Leave Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.3.13 Flag Control (EFLAG) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.3.13.1 Carry and Direction Flag Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.3.13.2 EFLAGS Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.3.13.3 Interrupt Flag Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.14 Flag Control (RFLAG) Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.15 Segment Register Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.15.1 Segment-Register Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.3.15.2 Far Control Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22

7.3.15.3 Software Interrupt Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.15.4 Load Far Pointer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23Vol. 1 ixCONTENTS
PAGE
7.3.16 Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16.1 Address Computation Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16.2 Table Lookup Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16.3 Processor Identification Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.16.4 No-Operation and Undefined Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.3.17 Random Number Generator Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
7.3.17.1 RDRAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
7.3.17.2 RDSEED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
CHAPTER 8
PROGRAMMING WITH THE X87 FPU 8.1 X87 FPU EXECUTION ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8-1
8.1.1 x87 FPU in 64-Bit Mode and Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2 x87 FPU Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2.1 Parameter Passing With the x87 FPU Register Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.3 x87 FPU Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.3.1 Top of Stack (TOP) Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.3.2 Condition Code Flags  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.3.3 x87 FPU Floating-Point Exception Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.3.4 Stack Fault Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.1.4 Branching and Conditional Moves on Condition Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.1.5 x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.5.1 x87 FPU Floating-Point Exception Mask Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.5.2 Precision Control Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.5.3 Rounding Control Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.6 Infinity Control Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.7 x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.8 x87 FPU Instruction and Data (Operand) Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.1.9 Last Instruction Opcode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.1.9.1 Fopcode Compatibility Sub-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.1.10 Saving the x87 FPU State with FSTENV/FNSTENV and FSAVE/FNSAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 8-11
8.1.11 Saving the x87 FPU State with FXSAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.2 X87 FPU DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8-13
8.2.1 Indefinites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.2.2 Unsupported Double Extended Precision Floating-Point Encodings and Pseudo-Denormals  . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.3 X87 FPU INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8-15
8.3.1 Escape (ESC) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.3.2 x87 FPU Instruction Operands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.3.3 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.3.4 Load Constant Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.3.5 Basic Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.3.6 Comparison and Classification Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.3.6.1 Branching on the x87 FPU Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.3.7 Trigonometric Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.3.8 Approximation of Pi  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

8.3.9 Logarithmic, Exponential, and Scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.3.10 Transcendental Instruction Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.3.11 x87 FPU Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
8.3.12 Waiting vs. Non-waiting Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.3.13 Unsupported x87 FPU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.4 X87 FPU FLOATING-POINT EXCEPTION HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8-24
8.4.1 Arithmetic vs. Non-arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8.5 X87 FPU FLOATING-POINT EXCEPTION CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8-26
8.5.1 Invalid Operation Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
8.5.1.1 Stack Overflow or Underflow Exception (#IS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
8.5.1.2 Invalid Arithmetic Operand Exception (#IA)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
8.5.2 Denormal Operand Exception (#D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8.5.3 Divide-By-Zero Exception (#Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8.5.4 Numeric Overflow Exception (#O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28CONTENTS
xVol. 1PAGE
8.5.5 Numeric Underflow Exception (#U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
8.5.6 Inexact-Result (Precision) Exception (#P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
8.6 X87 FPU EXCEPTION SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
8.7 HANDLING X87 FPU EXCEPTIONS IN SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
8.7.1 Native Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
8.7.2 MS-DOS* Compatibility Sub-mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
8.7.3 Handling x87 FPU Exceptions in Software  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
CHAPTER 9 
PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
9.1 OVERVIEW OF MMX TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-1
9.2 THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-1
9.2.1 MMX Technology in 64-Bit Mode and Compatibility Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .9-2
9.2.2 MMX Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
9.2.3 MMX Data Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
9.2.4 Memory Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
9.2.5 Single Instruction, Multiple Data (SIMD) Execution Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
9.3 SATURATION AND WRAPAROUND MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-4
9.4 MMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-5
9.4.1 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
9.4.2 Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
9.4.3 Comparison Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.4.4 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.4.5 Unpack Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.4.6 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.4.7 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.4.8 EMMS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.5 COMPATIBILITY WITH X87 FPU ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-8
9.5.1 MMX Instructions and the x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.6 WRITING APPLICATIONS WITH MMX CODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-8
9.6.1 Checking for MMX Technology Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.6.2 Transitions Between x87 FPU and MMX Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
9.6.3 Using the EMMS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
9.6.4 Mixing MMX and x87 FPU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

9.6.5 Interfacing with MMX Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.6.6 Using MMX Code in a Multitasking Operating System Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 9-10
9.6.7 Exception Handling in MMX Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.6.8 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.6.9 Effect of Instruction Prefixes on MMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
CHAPTER 10
PROGRAMMING WITH INTEL® STREAMIN G SIMD EXTENSIONS (INTEL® SSE)
10.1 OVERVIEW OF INTEL® SSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 INTEL® SSE PROGRAMMING ENVIRONMENT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2.1 Intel® SSE in 64-Bit Mode and Compatibility Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.2 XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.3 MXCSR Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.3.1 SIMD Floating-Point Mask and Flag Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3.2 SIMD Floating-Point Rounding Control Field  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3.3 Flush-To-Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3.4 Denormals-Are-Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.4 Compatibility of Intel® SSE with Intel® SSE2 and SSE3, MMX, and the x87 FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3 INTEL® SSE DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.4 INTEL® SSE INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4.1 Intel® SSE Packed and Scalar Floating-Point Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4.1.1 Intel® SSE Data Movement Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.4.1.2 Intel® SSE Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.4.2 Intel® SSE Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.2.1 Intel® SSE Comparison Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9Vol. 1 xiCONTENTS
PAGE
10.4.2.2 Intel® SSE Shuffle and Unpack Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.3 Intel® SSE Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.4 Intel® SSE 64-Bit SIMD Integer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.5 MXCSR State Management Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.6 Cacheability Control, Prefetch, and Memory Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 10-12
10.4.6.1 Cacheability Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.6.2 Caching of Temporal vs. Non-Temporal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.6.3 PREFETCHh Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.4.6.4 SFENCE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5 FXSAVE AND FXRSTOR INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5.1 FXSAVE Area  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5.1.1 x87 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.5.1.2 SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.5.2 Operation of FXSAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.5.3 Operation of FXRSTOR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.6 HANDLING INTEL® SSE INSTRUCTION EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.7 WRITING APPLICATIONS WITH INTEL® SSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
CHAPTER 11
PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
11.1 OVERVIEW OF INTEL® SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-1
11.2 INTEL® SSE2 PROGRAMMING ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-2
11.2.1 Intel® SSE2 in 64-Bit Mode and Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.2 Compatibility of Intel® SSE2 with Intel® SSE, MMX Technology, and x87 FPU Programming Environment . . . . . . . . . . . . 11-3
11.2.3 Denormals-Are-Zeros Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.3 INTEL® SSE2 DATA TYPES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-3
11.4 INTEL® SSE2 INSTRUCTIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-4
11.4.1 Packed and Scalar Double Precision Floating-Point Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.4.1.1 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.4.1.2 Intel® SSE2 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4.1.3 Intel® SSE2 Logical Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.1.4 Intel® SSE2 Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.1.5 Intel® SSE2 Shuffle and Unpack Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.1.6 Intel® SSE2 Conversion Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.4.2 Intel® SSE2 64-Bit and 128-Bit SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.4.3 128-Bit SIMD Integer Instruction Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.4.4 Cacheability Control and Memory Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.4.1 FLUSH Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.4.2 Cacheability Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.4.3 Memory Ordering Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.4.4 Pause. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4.5 Branch Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.5 INTEL® SSE, SSE2, AND SSE3 EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.5.1 SIMD Floating-Point Exceptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.5.2 SIMD Floating-Point Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.5.2.1 Invalid Operation Exception (#I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.5.2.2 Denormal-Operand Exception (#D)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.5.2.3 Divide-By-Zero Exception (#Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.5.2.4 Numeric Overflow Exception (#O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.5.2.5 Numeric Underflow Exception (#U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5.2.6 Inexact-Result (Precision) Exception (#P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5.3 Generating SIMD Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5.3.1 Handling Masked Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.5.3.2 Handling Unmasked Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.5.3.3 Handling Combinations of Masked and Unmasked Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 11-18
11.5.4 Handling SIMD Floating-Point Exceptions in Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.5.5 Interaction of SIMD and x87 FPU Floating-Point Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.6 WRITING APPLICATIONS WITH INTEL® SSE AND SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.6.1 General Guidelines for Using Intel® SSE and SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19CONTENTS
xiiVol. 1PAGE
11.6.2 Checking for Intel® SSE and SSE2 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.6.3 Checking for the DAZ Flag in the MXCSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11.6.4 Initialization of Intel® SSE and SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11.6.5 Saving and Restoring the SSE/SSE2 State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
11.6.6 Guidelines for Writing to the MXCSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
11.6.7 Interaction of Intel® SSE and SSE2 Instructions with x87 FPU and MMX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
11.6.8 Compatibility of SIMD and x87 FPU Floating-Point Data Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 11-22
11.6.9 Mixing Packed and Scalar Floating-Point and 128-Bit SIMD Integer Instructions and Data . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
11.6.10 Interfacing with Intel® SSE and SSE2 Procedures and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
11.6.10.1 Passing Parameters in XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
11.6.10.2 Saving XMM Register State on a Procedure or Function Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 11-23
11.6.10.3 Caller-Save Recommendation for Procedure and Function Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 11-24
11.6.11 Updating Existing MMX Technology Routines Using 128-Bit SIMD Integer Instructions. . . . . . . . . . . . . . . . . . . .  . . . . . . . . 11-24

11.6.12 Branching on Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
11.6.13 Cacheability Hint Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.6.14 Effect of Instruction Prefixes on Intel® SSE and SSE2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
CHAPTER 12
PROGRAMMING WITH INTEL® SSE3, SSSE 3, INTEL® SSE4, AND INTEL® AES-NI
12.1 PROGRAMMING ENVIRONMENT AND DATA TYPES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.1 Intel® SSE3, SSSE3, and Intel® SSE4 in 64-Bit Mode and Compatibility Mode  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 12-1
12.1.2 Compatibility of Intel® SSE3 and SSSE3 with MMX Technology, the x87 FPU Environment, and Intel® SSE and SSE2 . 12-1
12.1.3 Horizontal and Asymmetric Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 OVERVIEW OF INTEL® SSE3 INSTRUCTIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3 INTEL® SSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3.1 x87 FPU Instruction for Integer Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.2 SIMD Integer Instruction for Specialized 128-Bit Unaligned Data Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.3 SIMD Floating-Point Instructions That Enhance LOAD/MOVE/DUPLICATE Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.4 SIMD Floating-Point Instructions Provide Packed Addition/Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 12-4
12.3.5 SIMD Floating-Point Instructions Provide Horizontal Addition/Subtraction. . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 12-4
12.3.6 Two Thread Synchronization Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4 WRITING APPLICATIONS WITH INTEL® SSE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4.1 Guidelines for Using Intel® SSE3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4.2 Checking for Intel® SSE3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4.3 Enable FTZ and DAZ for SIMD Floating-Point Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.4.4 Programming Intel® SSE3 with Intel® SSE and SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5 OVERVIEW OF SSSE3 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.6 SSSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.6.1 Horizontal Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.6.2 Packed Absolute Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.6.3 Multiply and Add Packed Signed and Unsigned Bytes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.4 Packed Multiply High with Round and Scale  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.5 Packed Shuffle Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.6 Packed Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.7 Packed Align Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.7 WRITING APPLICATIONS WITH SSSE3 EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.7.1 Guidelines for Using SSSE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.7.2 Checking for SSSE3 Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.8 INTEL® SSE3, SSSE3, AND INTEL® SSE4 EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.8.1 Device Not Available (DNA) Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.8.2 Numeric Error Flag and IGNNE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.8.3 Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.8.4 IEEE 754 Compliance of Intel® SSE4.1 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 12-10
12.9 INTEL® SSE4 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12-10
12.10 INTEL® SSE4.1 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12-11
12.10.1 Dword Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.10.2 Floating-Point Dot Product Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.10.3 Streaming Load Hint Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.10.4 Packed Blending Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14Vol. 1 xiiiCONTENTS
PAGE
12.10.5 Packed Integer MIN/MAX Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.10.6 Floating-Point Round Instructions with Selectable Rounding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.10.7 Insertion and Extractions from XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15

PAGE
12.10.8 Packed Integer Format Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 12-16
12.10.10 Horizontal Search  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
12.10.11 Packed Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.10.12 Packed Qword Equality Comparisons  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.10.13 Dword Packing With Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.11 INTEL® SSE4.2 INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.11.1 String and Text Processing Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.11.1.1 Memory Operand Alignment  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.11.2 Packed Comparison SIMD Integer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.12 WRITING APPLICATIONS WITH INTEL® SSE4 EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.12.1 Guidelines for Using Intel® SSE4 Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.12.2 Checking for Intel® SSE4.1 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.12.3 Checking for Intel® SSE4.2 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.13 INTEL® AES-NI OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.13.1 Little-Endian Architecture and Big-Endian Specification (FIPS 197) . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 12-19
12.13.1.1 AES Data Structure in Intel® 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12.13.2 AES Transformations and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12.13.3 PCLMULQDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12.13.4 Checking for Intel® AES-NI Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
CHAPTER 13
MANAGING STATE USING THE XSAVE FEATURE SET13.1 XSAVE-SUPPORTED FEATURES AND STATE-COMPONENT BITMAPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .  13-1
13.2 ENUMERATION OF CPU SUPPORT FOR XSAVE INSTRUCTIONS AND XSAVE-SUPPORTED FEATURES  . . . . . . . . . . . . . . . . . .  13-3
13.3 ENABLING THE XSAVE FEATURE SET AND XSAVE-ENABLED FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13-5
13.4 XSAVE AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13-7
13.4.1 Legacy Region of an XSAVE Area  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.2 XSAVE Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.4.3 Extended Region of an XSAVE Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.5 XSAVE-MANAGED STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.5.1 x87 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.5.2 SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.5.3 AVX State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.5.4 MPX State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.5.5 AVX-512 State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.5.6 PT State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.5.7 PKRU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.5.8 PASID State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.5.9 CET State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.5.10 HDC State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.5.11 UINTR State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.5.12 LBR State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.5.13 HWP State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.5.14 AMX State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.6 PROCESSOR TRACKING OF XSAVE-MANAGED STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18

13.7 OPERATION OF XSAVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.8 OPERATION OF XRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
13.8.1 Standard Form of XRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
13.8.2 Compacted Form of XRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
13.8.3 XRSTOR and the Init and Modified Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
13.9 OPERATION OF XSAVEOPT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
13.10 OPERATION OF XSAVEC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
13.11 OPERATION OF XSAVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24
13.12 OPERATION OF XRSTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
13.13 MEMORY ACCESSES BY THE XSAVE FEATURE SET  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 13-27CONTENTS
xiv Vol. 1PAGE
13.14 EXTENDED FEATURE DISABLE (XFD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13-27
CHAPTER 14
PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
14.1 INTEL® AVX OVERVIEW  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.1 256-Bit Wide SIMD Register Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.2 Instruction Syntax Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.1.3 VEX Prefix Instruction Encoding Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2 FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.2.1 256-Bit Floating-Point Arithmetic Processing Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.2 256-Bit Non-Arithmetic Instruction Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.3 Arithmetic Primitives for 128-Bit Vector and Scalar processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 14-11
14.2.4 Non-Arithmetic Primitives for 128-Bit Vector and Scalar Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 14-13
14.3 DETECTION OF INTEL® AVX INSTRUCTIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-15
14.3.1 Detection of VEX-Encoded AES and VPCLMULQDQ  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 14-17
14.4 HALF PRECISION FLOATING-POINT CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  14-18
14.4.1 Detection of F16C Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20
14.5 FUSED-MULTIPLY-ADD (FMA) EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-21
14.5.1 FMA Instruction Operand Order and Arithmetic Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.5.2 Fused-Multiply-ADD (FMA) Numeric Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.5.3 Detection of FMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
14.6 OVERVIEW OF INTEL® ADVANCED VECTOR EXTENSIONS 2 (INTEL® AVX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .  14-25
14.6.1 Intel® AVX2 and 256-Bit Vector Integer Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
14.7 PROMOTED VECTOR INTEGER INSTRUCTIONS IN INTEL® AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-26
14.7.1 Detection of Intel® AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
14.8 ACCESSING YMM REGISTERS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-32
14.9 MEMORY ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-32
14.10 SIMD FLOATING-POINT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-34
14.11 EMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-34
14.12 WRITING INTEL® AVX FLOATING-POINT EXCEPTION HANDLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .  14-34
14.13 GENERAL PURPOSE INSTRUCTION SET ENHANCEMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-35
CHAPTER 15
PROGRAMMING WITH INTEL® AVX-512
15.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.1 512-Bit Wide SIMD Register Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.2 32 SIMD Register Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.3 Eight Opmask Register Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.4 Instruction Syntax Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.5 EVEX Instruction Encoding Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.2 DETECTION OF AVX-512 FOUNDATION INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 15-3
15.2.1 Additional 512-Bit Instruction Extensions of the Intel® AVX-512 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2.2 Detection of AVX512-FP16 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3 DETECTION OF 512-BIT INSTRUCTION GROUPS OF THE INTEL® AVX-512 FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 15-6
15.4 DETECTION OF INTEL® AVX-512 INSTRUCT ION GROUPS OPERATING AT 256 AND 128-BIT VECTOR LENGTHS. . . . . . . . . 15-7
15.5 ACCESSING XMM, YMM, AND ZMM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.6 ENHANCED VECTOR PROGRAMMING ENVIRONMENT USING EVEX ENCODING  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 15-8
15.6.1 OPMASK Register to Predicate Vector Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.6.1.1 Opmask Register K0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.6.1.2 Example of Opmask Usages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.6.2 OpMask Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.6.3 Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.6.4 Static Rounding Mode and Suppress All Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.6.5 Compressed Disp8*N Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.7 MEMORY ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-13
15.8 SIMD FLOATING-POINT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-14
15.9 INSTRUCTION EXCEPTION SPECIFICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-15
15.10 EMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-15
15.11 WRITING FLOATING-POINT EXCEPTION HAND LERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-15Vol. 1 xvCONTENTS
PAGE
CHAPTER 16
PROGRAMMING WITH INTEL® TRANSACT IONAL SYNCHRONIZ ATION EXTENSIONS
16.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-1
16.2 INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-1
16.2.1 HLE Software Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.2.2 RTM Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3 INTEL® TSX APPLICATION PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  16-3
16.3.1 Detection of Transactional Synchronization Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.1.1 Detection of HLE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.1.2 Detection of RTM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.1.3 Detection of XTEST Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.1.4 Detection of Intel® TSX Suspend Load Address Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.2 Querying Transactional Execution Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.3 Requirements for HLE Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.4 Transactional Nesting  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.4.1 HLE Nesting and Elision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.4.2 RTM Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.4.3 Nesting HLE and RTM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.5 RTM Abort Status Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.6 RTM Memory Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.7 RTM-Enabled Debugger Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.8 Intel® TSX Suspend/Resume Load Address Tracking Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.9 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.9.1 Instruction Based Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.3.9.2 Runtime Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
CHAPTER 17
CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
17.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-1
17.1.1 Shadow Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.2 Indirect Branch Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.3 Speculative Behavior when CET is Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

CHAPTER 17
17.2 SHADOW STACKS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-2
17.2.1 Shadow Stack Pointer and its Operand and Address Size Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 17-2
17.2.2 Terminology  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.3 Supervisor Shadow Stack Token  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.4 Shadow Stack Usage on Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.2.5 Switching Shadow Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.2.6 Constraining Execution at Targets of RET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17.3 INDIRECT BRANCH TRACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-7
17.3.1 No-track Prefix for Near Indirect CALL/JMP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.3.2 Terminology  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.3.3 Indirect Branch Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.3.3.1 Control Transfers between CPL 3 and CPL < 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.3.3.2 Control Transfers within CPL 3 or CPL < 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.3.4 Indirect Branch Tracking State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.3.5 INT3 Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.3.6 Legacy Compatibility Treatment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.3.6.1 Legacy Code Page Bitmap Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.3.7 Other Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.3.7.1 Intel® Transactional Synchronization Extensions (Intel® TSX) Interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.3.7.2 #CP(ENDBRANCH) Priority w.r.t #NM and #UD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.3.7.3 #CP(ENDBRANCH) Priority w.r.t #BP and #DB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.3.8 Constraining Speculation after Missing ENDBRANCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 17-14
17.4 INTEL® TRUSTED EXECUTION TECHNOLOGY (INTEL® TXT) INTERACTIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 17-14
CHAPTER 18
PROGRAMMING WITH INTEL® AD VANCED MATRIX EXTENSIONS
18.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-1CONTENTS
xvi Vol. 1PAGE
18.1.1 Tile Architecture Details  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.1.2 TMUL Architecture Details  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.1.3 Handling of Tile Row and Column Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.1.4 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.2 RECOMMENDATIONS FOR SYSTEM SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3 IMPLEMENTATION PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.4 HELPER FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
CHAPTER 19
INPUT/OUTPUT
19.1 I/O PORT ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2 I/O PORT HARDWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.3 I/O ADDRESS SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.3.1 Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.4 I/O INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.5 PROTECTED-MODE I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.5.1 I/O Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.5.2 I/O Permission Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.6 ORDERING I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
CHAPTER 20 
PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION
20.1 USING THE CPUID INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.1 Notes on Where to Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.2 Identification of Earlier IA-32 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
APPENDIX A

CHAPTER 20 
APPENDIX A
EFLAGS CROSS-REFERENCEA.1 EFLAGS AND INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-1
APPENDIX B
EFLAGS CONDITION CODESB.1 CONDITION CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-1
APPENDIX C
FLOATING-POINT EXCEPTIONS SUMMARYC.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-1
C.2 X87 FPU INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-1
C.3 INTEL® SSE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-3
C.4 INTEL® SSE2 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-5
C.5 INTEL® SSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-7
C.6 SSSE3 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-7
C.7 INTEL® SSE4 INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-7
APPENDIX D
GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
D.1 TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .  D-1
D.2 SOFTWARE EXCEPTION HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  D-1
D.3 EXCEPTION SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  D-3
D.4 SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .  D-3
D.4.1 Floating-Point Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-3
D.4.2 Intel® SSE, SSE2, and SSE3 Response To Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-4
D.4.2.1 Numeric Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-5
D.4.2.2 Results of Operations with NaN Operands or a NaN Result  for Intel® SSE, SSE2, and SSE3 Numeric Instructions. . . .D-5
D.4.2.3 Condition Codes, Exception Flags, and Response for Masked and Unmasked Numeric Exceptions . . . . . . . . . . . . . . . .  . .D-9
D.4.3 Example SIMD Floating-Point Emulation Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . D-15Vol. 1 xviiCONTENTS
PAGE
APPENDIX E
INTEL® MEMORY PROT ECTION EXTENSIONS
E.1 INTEL® MEMORY PROTECTION EXTENSIONS (INTEL® MPX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  E-1
E.2 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  E-1
E.3 INTEL MPX PROGRAMMING ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  E-2
E.3.1 Detection and Enumeration of Intel MPX Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
E.3.2 Bounds Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
E.3.3 Configuration and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
E.3.4 Read and Write of IA32_BNDCFGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4
E.4 INTEL MPX INSTRUCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  E-4
E.4.1 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
E.4.2 Usage and Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
E.4.3 Loading and Storing Bounds in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6
E.4.3.1 BNDLDX and BNDSTX in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7
E.4.3.2 BNDLDX and BNDSTX Outside 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . E-8
E.5 INTERACTIONS WITH INTEL MPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  E-9
E.5.1 Intel MPX and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9
E.5.2 Intel® MPX Support for Pointer Operations with Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-10
E.5.3 CALL, RET, JMP, and All Jcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-10
E.5.4 BOUND Instruction and Intel MPX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-11
E.5.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-11
E.5.6 Intel MPX and System Management Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-11
E.5.7 Support of Intel MPX in VMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-11
E.5.8 Support of Intel MPX in Intel TSX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-12CONTENTS
xviii Vol. 1PAGE
FIGURES
Figure 1-1. Bit and Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Figure 2-1. The P6 Processor Microarchitecture with Advanced Transfer Cache Enhancement . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 2-7

FIGURES
Figure 2-2. The Intel NetBurst® Microarchitecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 2-3. The Intel® Core™ Microarchitecture Pipeline Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Figure 2-4. SIMD Extensions, Register Layouts, and Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Figure 2-5. Comparison of an IA-32 Proce ssor Supporting Intel® Hyper-Threading Technology and a Traditional Dual Processor 
System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Figure 2-6. Intel 64 and IA-32 Processors that Support Dual-Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Figure 2-7. Intel® 64 Processors that Support Quad-Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Figure 2-8. Intel® Core™ i7 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Figure 3-1. IA-32 Basic Execution Environment for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 3-3
Figure 3-2. 64-Bit Mode Execution Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-3. Three Memory Management Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-4. General System and Application Programming Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Figure 3-5. Alternate General-Purpose Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Figure 3-6. Use of Segment Registers for Flat Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Figure 3-7. Use of Segment Registers in Segmented Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Figure 3-8. EFLAGS Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Figure 3-9. Memory Operand Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Figure 3-10. Memory Operand Address in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Figure 3-11. Offset (or Effective Address) Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Figure 4-1. Fundamental Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Figure 4-2. Bytes, Words, Doublewords, Quadwords, and Double Quadwords in Memory . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 4-2
Figure 4-3. Numeric Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-4. Pointer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Figure 4-5. Pointers in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Figure 4-6. Bit Field Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Figure 4-7. 64-Bit Packed SIMD Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Figure 4-8. 128-Bit Packed SIMD Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Figure 4-9. BCD Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Figure 4-10. Binary Real Number System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Figure 4-11. Binary Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Figure 4-12. Real Numbers and NaNs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Figure 6-1. Stack Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Figure 6-2. Stack on Near and Far Calls  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Figure 6-3. Shadow Stack on Near and Far Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Figure 6-4. Protection Rings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Figure 6-5. Stack Switch on a Call to a Different Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Figure 6-6. Shadow Stack Switch on a Call to a Different Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Figure 6-7. Stack Usage on Transfers to Interrupt and Exception Handling Routines. . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 6-15
Figure 6-8. Shadow Stack Usage on Transfers to Interrupt and Exception Handling Routines  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 6-16
Figure 6-9. Nested Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Figure 6-10. Stack Frame After Entering the MAIN Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Figure 6-11. Stack Frame After Entering Procedure A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Figure 6-12. Stack Frame After Entering Procedure B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Figure 6-13. Stack Frame After Entering Procedure C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Figure 7-1. Operation of the PUSH Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Figure 7-2. Operation of the PUSHA Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

Figure 7-3. Operation of the POP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Figure 7-4. Operation of the POPA Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-5. Sign Extension  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-6. SHL/SAL Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Figure 7-7. SHR Instruction Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Figure 7-8. SAR Instruction Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Figure 7-9. SHLD and SHRD Instruction Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Figure 7-10. ROL, ROR, RCL, and RCR Instruction Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13Vol. 1 xixCONTENTS
PAGE
Figure 7-11. Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD Instructions . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 7-21
Figure 8-1. x87 FPU Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Figure 8-2. x87 FPU Data Register Stack  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Figure 8-3. Example x87 FPU Dot Product Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Figure 8-4. x87 FPU Status Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Figure 8-5. Moving the Condition Codes to the EFLAGS Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Figure 8-6. x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Figure 8-7. x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Figure 8-8. Contents of x87 FPU Opcode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Figure 8-9. Protected Mode x87 FPU State Image in Memory, 32-Bit Format  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 8-11
Figure 8-10. Real Mode x87 FPU State Image in Memory, 32-Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Figure 8-11. Protected Mode x87 FPU State Image in Memory, 16-Bit Format  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Figure 8-12. Real Mode x87 FPU State Image in Memory, 16-Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Figure 8-13. x87 FPU Data Type Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Figure 9-1. MMX Technology Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Figure 9-2. MMX Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Figure 9-3. Data Types Introduced with the MMX Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Figure 9-4. SIMD Execution Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Figure 10-1. Intel® SSE Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Figure 10-2. XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Figure 10-3. MXCSR Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Figure 10-4. 128-Bit Packed Single Precision Floating-Point Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Figure 10-5. Packed Single Precision Floating-Point Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Figure 10-6. Scalar Single Precision Floating-Point Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Figure 10-7. SHUFPS Instruction, Packed Shuffle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .10-10
Figure 10-8. UNPCKHPS Instruction, High Unpack and Interleave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .10-10
Figure 10-9. UNPCKLPS Instruction, Low Unpack and Interleave Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10
Figure 11-1. Intel® Steaming SIMD Extensions 2 Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 11-2
Figure 11-2. Data Types Introduced with Intel® SSE2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Figure 11-3. Packed Double Precision Floating-Point Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Figure 11-4. Scalar Double Precision Floating-Point Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Figure 11-5. SHUFPD Instruction, Packed Shuffle Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Figure 11-6. UNPCKHPD Instruction, High Unpack, and Interleave Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 11-8
Figure 11-7. UNPCKLPD Instruction, Low Unpack, and Interleave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 11-8
Figure 11-8. Intel® SSE and SSE2 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Figure 11-9. Example Masked Response for Packed Operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .11-17
Figure 12-1. Asymmetric Processing in ADDSUBPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Figure 12-2. Horizontal Data Movement in HADDPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

Figure 12-3. Horizontal Data Movement in PHADDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Figure 12-4. MPSADBW Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16
Figure 12-5. AES State Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-19
Figure 14-1. 256-Bit Wide SIMD Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Figure 14-2. General Procedural Flow of Application Detection of Intel® AVX . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .14-15
Figure 14-3. General Procedural Flow of Application Detection of Float-16. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .14-20
Figure 15-1. 512-Bit Wide Vectors and SIMD Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
Figure 15-2. Procedural Flow for Application Detection of AVX-512 Foundation Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Figure 15-3. Procedural Flow for Application Detection of 512-Bit Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
Figure 15-4. Procedural Flow for Application Detection of 512-Bit Instruction Groups . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 15-6
Figure 15-5. Procedural Flow for Detection of  Intel® AVX-512 Instructions Operating at Vector Lengths < 512 . . . . . . . . . . .  . . . 15-7
Figure 17-1. Supervisor Shadow Stack with a Supervisor Shadow Stack Token. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 17-4
Figure 17-2. RSTORSSP to Switch to New Shadow Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Figure 17-3. SAVEPREVSSP to Save a Restore Point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Figure 17-4. Priority of Control Protection Exception on Missing ENDBRANCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
Figure 18-1. Intel® AMX Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
Figure 18-2. The TMUL Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Figure 18-3. Matrix Multiply C+= A*B  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
Figure 19-1. Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Figure 19-2. I/O Permission Bit Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
Figure D-1. Control Flow for Handling Unmasked Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4CONTENTS
xx Vol. 1PAGE
Figure E-1. Layout of the Bounds Registers BND0-BND3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
Figure E-2. Common Layout of the Bound Configuration Registers BNDCFGU and BNDCFGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
Figure E-3. Layout of the Bound Status Registers BNDSTATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . E-4
Figure E-4. Bound Paging Structure and Address Translation in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . E-7
Figure E-5. Bound Paging Structure and Address Translation Outside 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . E-9Vol. 1 xxiCONTENTS
PAGE
TABLES
Table 2-1. Key Features of Most Recent IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Table 2-2. Key Features of Most Recent Intel® 64 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Table 2-3. Key Features of Previous Generations of IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 2-27
Table 2-4. Planned Intel® ISA and Features Removal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Table 2-5. Intel® ISA and Features Removal List  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Table 3-1. Instruction Pointer Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Table 3-2. Addressable General Purpose Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Table 3-3. Effective Operand- and Address-Size Attributes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Table 3-4. Effective Operand- and Address-Size Attributes in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Table 3-5. Default Segment Selection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Table 4-1. Signed Integer Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-2. Length, Precision, and Range of Floating-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-3. Floating-Point Number and NaN Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-4. Packed Decimal Integer Encodings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Table 4-5. Real and Floating-Point Number Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Table 4-6. Denormalization Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Table 4-7. Rules for Handling NaNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Table 4-8. Rounding Modes and Encoding of Rounding Control (RC) Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 4-18
Table 4-9. Numeric Overflow Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Table 4-10. Masked Responses to Numeric Overflow  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Table 4-11. Numeric Underflow (Normalized) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

Table 5-2. Instruction Set Extensions Introduction in Intel® 64 and IA-32 Processors . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 5-2
Table 5-1. Instruction Groups in Intel® 64 and IA-32 Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Table 5-3. Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1  . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
Table 6-1. Exceptions and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Table 7-1. Move Instruction Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Table 7-2. Conditional Move Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-3. Bit Test and Modify Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Table 7-4. Conditional Jump Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Table 8-1. Condition Code Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Table 8-2. Precision Control Field (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Table 8-3. Unsupported Double Extended Precision Floating-Point Encodings and Pseudo-Denormals  . . . . . . . . . . . . . . . . .  . . . . 8-14
Table 8-4. Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
Table 8-5. Floating-Point Conditional Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
Table 8-6. Setting of x87 FPU Condition Code Flags for Floating-Point Number Comparisons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Table 8-7. Setting of EFLAGS Status Flags for Floating-Point Number Comparisons. . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 8-19
Table 8-8. TEST Instruction Constants for Conditional Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Table 8-9. Arithmetic and Non-arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Table 8-10. Invalid Arithmetic Operations and the Masked Responses to Them  . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 8-27
Table 8-11. Divide-By-Zero Conditions and the Masked Responses to Them . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Table 9-1. Data Range Limits for Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Table 9-2. MMX Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Table 9-3. Effect of Prefixes on MMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
Table 10-1. PREFETCHh Instructions Caching Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Table 10-2. Format of an FXSAVE Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Table 11-1. Masked Responses of Intel® SSE, SSE2, and SSE3 Instructions to Invalid Arithmetic Operations . . . . . . . . . . . . . . . . 11-14
Table 11-2. SSE and SSE2 State Following a Power-up/Reset or INIT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Table 11-3. Effect of Prefixes on the Intel® SSE, SSE2, and SSE3 Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
Table 12-1. SIMD Numeric Exceptions Signaled by SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Table 12-2. Enhanced 32-Bit SIMD Multiply Supported by Intel® SSE4.1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 12-11
Table 12-3. Blend Field Size and Control Modes Supported by Intel® SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Table 12-4. Enhanced SIMD Integer MIN/MAX Instructions Supported by Intel® SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 12-14
Table 12-5. New SIMD Integer Conversions Supported by Intel® SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
Table 12-6. New SIMD Integer Conversions Supported by Intel® SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
Table 12-7. Enhanced SIMD Pack Support by Intel® SSE4.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
Table 12-8. Byte and 32-Bit Word Representation of a 128-Bit State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
Table 12-9. Matrix Representation of a 128-Bit State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20CONTENTS
xxii Vol. 1PAGE
Table 12-10. Little Endian Representation of a 128-Bit State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
Table 12-11. Little Endian Represen tation of a 4x4 Byte Matrix  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
Table 12-12. The ShiftRows Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
Table 12-13. Look-up Table Associated with S-Box Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
Table 12-14. The InvShiftRows Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
Table 12-15. Look-up Table Associated with InvS-Box Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 12-24
Table 13-1. Format of the Legacy Region of an XSAVE Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Table 14-1. Promoted SSSE3 and Intel® SSE, SSE2, SSE3, and SSE4 Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 14-3
Table 14-2. Promoted 256-Bit and 128-Bit Arithmetic Intel® AVX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 14-9
Table 14-3. Promoted 256-Bit and 128-Bit Data Movement Intel® AVX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Table 14-4. 256-Bit Intel® AVX Instruction Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Table 14-6. 128-Bit Intel® AVX Instruction Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 14-14
Table 14-8. Immediate Byte Encoding for 16-Bit Floating-Point Co nversion Instructions. . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 14-18
Table 14-9. Non-Numerical Behavior for VCVTPH2PS and VCVTPS2PH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Table 14-10. Invalid Operation for VCVTPH2PS and VCVTPS2PH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Table 14-12. Underflow Condition for VCVTPS2PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Table 14-13. Overflow Condition for VCVTPS2PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Table 14-14. Inexact Condition for VCVTPS2PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Table 14-11. Denormal Condition Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Table 14-15. FMA Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Table 14-16. Rounding Behavior of Zero Result in FMA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
Table 14-17. FMA Numeric Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
Table 14-18. Promoted Vector Integer SIMD In structions in Intel® AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 14-26
Table 14-19.  VEX-Only SIMD Instructions in Intel® AVX and AVX2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
Table 14-20. New Primitive in Intel® AVX2 Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Table 14-21. Alignment Faulting Conditions when Memory Access is Not Aligned . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 14-33
Table 14-22. Instructions Requiring Explicitly Aligned Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
Table 14-23. Instructions Not Requiring Explicit Memory Alignmen t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 14-34
Table 15-1. 512-Bit Instruction Groups in the Intel® AVX-512 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 15-6
Table 15-2. Feature Flag Collection Required of 256/128 Bit Vector Lengths for Each Instruction Group. . . . . . . . . . . . . .  . . . . . . 15-7
Table 15-3. Instruction Mnemonics That Do Not Support EVEX.128 Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 15-8
Table 15-4. Characteristics of Three Rounding Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
Table 15-5. Static Rounding Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
Table 15-6.  SIMD Instructions Requiring Explicitly Aligned Memo ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 15-14
Table 15-7. Instructions Not Requir ing Explicit Memory Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Table 16-1. RTM Abort Status Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Table 17-1. Indirect Branch Tracking State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
Table 19-1. I/O Instruction Serialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
Table A-1. Codes Describing Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
Table A-2. EFLAGS Cross-Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
Table B-1. EFLAGS Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
Table C-1. x87 FPU and SIMD Floating-Point Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1
Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .C-1
Table C-3. Exceptions Generated with Intel® SSE Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-3
Table C-4. Exceptions Generated with Intel® SSE2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-5
Table C-5. Exceptions Generated with Intel® SSE3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-7
Table C-6. Exceptions Generated with Intel® SSE4 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-8
Table D-1. ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVP S, DIVSS, ADDPD, ADDSD, SUBPD, SUBSD, MULPD, MULSD, 
DIVPD, DIVSD, ADDSUBPS, ADDSUBPD, HADDPS, HADDPD, HSUBPS, and HSUBPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .D-5
Table D-2. CMPPS.EQ, CMPSS.EQ, CMPPS.ORD, CMPSS.ORD, CMPPD.EQ, CMPSD.EQ, CMPPD.ORD, and CMPSD.ORD . . . . . . . . . . . . .D-6
Table D-3. CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CM PSS.UNORD, CMPPD.NEQ, CMPSD.NEQ, CMPPD.UNORD, and 
CMPSD.UNORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-6
Table D-4. CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE, CMPPD.LT, CMPSD.LT, CMPPD.LE, and CMPSD.LE . . . . . . . . . . . . . . . . . .  . . . .D-6
Table D-5. CMPPS.NLT, CMPSS.NLT, CMPPS.NLE,  CMPSS.NLE, CMPPD.NLT, CMPSD.NLT, CMPPD.NLE, and CMPSD.NLE . . . . . . . . . .D-7
Table D-6. COMISS and COMISD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-7
Table D-7. UCOMISS and UCOMISD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-7
Table D-8. CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, CVTPD2PI, CVTSD2SI, CVTTPD2PI, CVTTSD2SI, CVTPS2DQ, Vol. 1 xxiiiCONTENTS
PAGE
CVTTPS2DQ, CVTPD2DQ, and CVTTPD2DQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-7
Table D-9. MAXPS, MAXSS, MINPS, MINSS, MAXPD, MAXSD, MINPD, and MINSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .D-8
Table D-10. SQRTPS, SQRTSS, SQRTPD, and SQRTSD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-8
Table D-11. CVTPS2PD and CVTSS2SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-8

PAGE
Table D-12. CVTPD2PS and CVTSD2SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-8
Table D-13. #I - Invalid Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-9
Table D-14. #Z - Divide-by-Zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11
Table D-15. #D - Denormal Operand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12
Table D-16. #O - Numeric Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-13
Table D-17. #U - Numeric Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-14
Table D-18. #P - Inexact Result (Precision)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-15
Table E-1.  Error Code Definition of BNDSTATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4
Table E-2.  Intel MPX Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
Table E-3.  Effective Address Size of Intel® MPX Instructions with 67H Prefix. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .E-10
Table E-4.  Bounds Register INIT Behavior Due to BND Prefix with Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-11CONTENTS
xxiv Vol. 1PAGEVol. 1 1-1CHAPTER 1
The Intel® 64 and IA-32 Architectures Software Developer’s Ma nual, Volume 1: Basic Architecture (order number 
253665) is part of a set that describes the ar chitecture and programming environment of Intel® 64 and IA-32 
architecture processors. Other volumes in this set are:
•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D: Instruction Set 
Reference (order numbers 253666, 253667, 326018, and 334569).
•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D: System 
Programming Guide (order numbers 253668, 253669, 326019, and 332831).
•The Intel® 64 and IA-32 Architectures Software Developer’s Ma nual, Volume 4: Model-Specific Registers (order 
number 335592).
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture 
and programming environment of Intel 64 and IA-32 processors. The Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, describe the instruction set of the processor and the opcode struc-
ture. These volumes apply to application programmers an d to programmers who write operating systems or exec-
utives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C, & 3D, describe 
the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operating-
system and BIOS designers. In addition, the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 3B, addresses the programming environment for cl asses of software that host operating systems. The 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, describes the model-specific registers 
of Intel 64 and IA-32 processors.
1.1 INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL
This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which 
include: 
•Pentium® processors
•P6 family processors
•Pentium® 4 processors
•Pentium® M processors
•Intel® Xeon® processors
•Pentium® D processors
•Pentium® processor Extreme Editions
•64-bit Intel® Xeon® processors
•Intel® Core™ Duo processor
•Intel® Core™ Solo processor
•Dual-Core Intel® Xeon® processor LV
•Intel® Core™ 2 Duo processor
•Intel® Core™ 2 Quad processor Q6000 series
•Intel® Xeon® processor 3000, 3200 series
•Intel® Xeon® processor 5000 series
•Intel® Xeon® processor 5100, 5300 series
•Intel® Core™ 2 Extreme processor X7000 and X6800 series
•Intel® Core™ 2 Extreme processor QX6000 series
•Intel® Xeon® processor 7100 series1-2 Vol. 1ABOUT THIS MANUAL
•Intel® Pentium® Dual-Core processor
•Intel® Xeon® processor 7200, 7300 series
•Intel® Xeon® processor 5200, 5400, 7400 series
•Intel® Core™ 2 Extreme processor QX9000 and X9000 series
•Intel® Core™ 2 Quad processor Q9000 series
•Intel® Core™ 2 Duo processor E8000, T9000 series
•Intel Atom® processor family
•Intel Atom® processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000, 
C1000 series are built from 45 nm and 32 nm processes
•Intel® Core™ i7 processor
•Intel® Core™  i5 processor
•Intel® Xeon® processor E7-8800/4800/2800 product families 
•Intel® Core™ i7-3930K processor
•2nd generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series
•Intel® Xeon® processor E3-1200 product family
•Intel® Xeon® processor E5-2400/1400 product family
•Intel® Xeon® processor E5-4600/2600/1600 product family
•3rd generation Intel® Core™ processors
•Intel® Xeon® processor E3-1200 v2 product family
•Intel® Xeon® processor E5-2400/1400 v2 product families
•Intel® Xeon® processor E5-4600/2600/1600 v2 product families
•Intel® Xeon® processor E7-8800/4800/2800 v2 product families
•4th generation Intel® Core™ processors
•The Intel® Core™ M processor family 
•Intel® Core™ i7-59xx Processor Extreme Edition
•Intel® Core™ i7-49xx Processor Extreme Edition
•Intel® Xeon® processor E3-1200 v3 product family
•Intel® Xeon® processor E5-2600/1600 v3 product families
•5th generation Intel® Core™ processors
•Intel® Xeon® processor D-1500 product family
•Intel® Xeon® processor E5 v4 family
•Intel Atom® processor X7-Z8000 and X5-Z8000 series
•Intel Atom® processor Z3400 series
•Intel Atom® processor Z3500 series
•6th generation Intel® Core™ processors
•Intel® Xeon® processor E3-1500m v5 product family
•7th generation Intel® Core™ processors
•Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series 
•Intel® Xeon® Scalable Processor Family 
•8th generation Intel® Core™ processors
•Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
•Intel® Xeon® E processors
•9th generation Intel® Core™ processors
•2nd generation Intel® Xeon® Scalable Processor Family Vol. 1 1-3ABOUT THIS MANUAL
•10th generation Intel® Core™ processors
•11th generation Intel® Core™ processors
•3rd generation Intel® Xeon® Scalable Processor Family
•12th generation Intel® Core™ processors
•13th generation Intel® Core™ processors
•4th generation Intel® Xeon® Scalable Processor Family
•5th generation Intel® Xeon® Scalable Processor Family
•Intel® Core™ Ultra 7 processors
P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium® 
Pro, Pentium® II, Pentium® III, and Pentium® III Xeon® processors.
The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are based on the Intel NetBurst® microar-
chitecture. Most early Intel® Xeon® processors are based on the Intel NetBurst® microarchitecture. Intel Xeon 
processor 5000, 7100 series are based on the Intel NetBurst® microarchitecture.
The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LV are based on an improved 
Pentium® M processor microarchitecture. 
The Intel® Xeon® processor 3000, 3200, 5100, 5300, 7200, and 7300 series, Intel® Pentium® dual-core, Intel® 
Core™ 2 Duo, Intel® Core™ 2 Quad, and Intel® Core™ 2 Extreme processors are based on Intel® Core™ microar-
chitecture.
The Intel® Xeon® processor 5200, 5400, 7400 series, Intel® Core™ 2 Quad processor Q9000 series, and Intel® 
Core™ 2 Extreme processors QX9000, X9000 series, Intel® Core™ 2 processor E8000 series are based on 
Enhanced Intel® Core™ microarchitecture.
The Intel Atom® processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000, 
C1000 series are based on the Intel Atom® microarchitecture and supports Intel 64 architecture.
P6 family, Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-core Intel® Xeon® processor LV, 
and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel® AtomTM 
processor Z5xx series support IA-32 architecture.
The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel®

The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel® 
Core™ 2 Duo, Intel® Core™ 2 Extreme, Intel® Core™ 2 Quad processors, Pentium® D processors, Pentium® Dual-
Core processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel® 64 architecture.
The Intel® Core™ i7 processor and Intel® Xeon® processor 3400, 5500, 7500 series are based on 45 nm Nehalem 
microarchitecture. Westmere microarchitecture is a 32 nm version of the Nehalem microarchitecture. Intel® 
Xeon® processor 5600 series, Intel Xeon processor E7 and various Intel Core i7, i5, i3 processors are based on the 
Westmere microarchitecture. These processors support Intel 64 architecture.
The Intel® Xeon® processor E5 family, Intel® Xeon® processor E3-1200 family, Intel® Xeon® processor E7-
8800/4800/2800 product families, Intel® Core™ i7-3930K processor, and 2nd generation Intel® Core™ i7-2xxx, 
Intel® CoreTM i5-2xxx, Intel® Core™ i3-2xxx processor series are based on the Sandy Bridge microarchitecture and 
support Intel 64 architecture.
The Intel® Xeon® processor E7-8800/4800/2800 v2 product families, Intel® Xeon® processor E3-1200 v2 product 
family and 3rd generation Intel® Core™ processors are based on the Ivy Bridge microarchitecture and support 
Intel 64 architecture.
The Intel® Xeon® processor E5-4600/2600/1600 v2 product families, Intel® Xeon® processor E5-2400/1400 v2 
product families and Intel® Core™ i7-49xx Processor Extreme Edition are based on the Ivy Bridge-E microarchitec-
ture and support Intel 64 architecture.
The Intel® Xeon® processor E3-1200 v3 product family and 4th Generation Intel® Core™ processors are based on 
the Haswell microarchitecture and support Intel 64 architecture.
The Intel® Xeon® processor E5-2600/1600 v3 product families and the Intel® Core™ i7-59xx Processor Extreme 
Edition are based on the Haswell-E microarchitecture and support Intel 64 architecture.
The Intel Atom® processor Z8000 series is based on the Airmont microarchitecture.1-4 Vol. 1ABOUT THIS MANUAL
The Intel Atom® processor Z3400 series and the Intel Atom® processor Z3500 series are based on the Silvermont 
microarchitecture.
The Intel® Core™ M processor family, 5th generation Intel® Core™ processors, Intel® Xeon® processor D-1500 
product family and the Intel® Xeon® processor E5 v4 family are based on the Broadwell microarchitecture and 
support Intel 64 architecture. 
The Intel® Xeon® Scalable Processor Family, Intel® Xeon® processor E3-1500m v5 product family and 6th gener-
ation Intel® Core™ processors are based on the Skylake microarchitecture and support Intel 64 architecture.
The 7th generation Intel® Core™ processors are based on the Kaby Lake microarchitecture and support Intel 64 
The Intel Atom® processor C series, the Intel Atom® processor X series, the Intel® Pentium® processor J series, 
the Intel® Celeron® processor J series, and the Intel® Celeron® processor N series are based on the Goldmont 
The Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series is based on the Knights Landing microarchitecture and 
supports Intel 64 architecture.
The Intel® Pentium® Silver processor series, the Intel® Celeron® processor J series, and the Intel® Celeron® 
processor N series are based on the Goldmont Plus microarchitecture.
The 8th generation Intel® Core™ processors, 9th generation Intel® Core™ processors, and Intel® Xeon® E proces-
sors are based on the Coffee Lake microarchitecture and support Intel 64 architecture.
The Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series is based on the Knights Mill microarchitecture and 
The 2nd generation Intel® Xeon® Scalable Processor Family is based on the Cascade Lake product and supports 
Some 10th generation Intel® Core™ processors are based on the Ice Lake microarchitecture, and some are based 
on the Comet Lake microarchitecture; both support Intel 64 architecture.
Some 11th generation Intel® Core™ processors are based on the Tiger Lake microarchitecture, and some are 
based on the Rocket Lake microarchitecture; both support Intel 64 architecture.
Some 3rd generation Intel® Xeon® Scalable Processor Family processors are based on the Cooper Lake product, 
and some are based on the Ice Lake microarchitecture; both support Intel 64 architecture.
The 12th generation Intel® Core™ processors are based on the Alder Lake performance hybrid architecture and 
The 13th generation Intel® Core™ processors are based on the Raptor Lake performance hybrid architecture and 
The 4th generation Intel® Xeon® Scalable Processor Family is based on  Sapphire Rapids microarchitecture and 
The 5th generation Intel® Xeon® Scalable Processor Family is based on Emerald Rapids microarchitecture and 
The Intel® Core™ Ultra 7 processor is based on Meteor Lake hy brid architecture and supp orts Intel 64 architecture.
IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microproces-
sors. Intel® 64 architecture is the instruction set architecture and programming environment which is the superset 
of Intel’s 32-bit and 64-bit architectures. It  is compatible with the IA-32 architecture.
1.2 OVERVIEW OF VOLUME 1: BASIC ARCHITECTURE
A description of this manual’s content follows:
Chapter 1 — About This Manual.  Gives an overview of all volumes of th e Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual. It also describes the notation al conventions in these manuals and lists related Intel 
manuals and documentation of interest to programmers and hardware designers.Vol. 1 1-5ABOUT THIS MANUAL
Chapter 2 — Intel® 64 and IA-32 Architectures.  Introduces the Intel 64 and IA-32 architectures along with 
the families of Intel processors that are based on these architectures. It also gives an overview of the common 
features found in these processors and brief history of the Intel 64 and IA-32 architectures.
Chapter 3 — Basic Execution Environment . Introduces the models of memory organization and describes the 
register set used by applications.
Chapter 4 — Data Types.  Describes the data types and addressing mo des recognized by the processor; provides 
an overview of real numbers and floating-poi nt formats and of floating-point exceptions.
Chapter 5 — Instruction Set Summary.  Lists all Intel 64 and IA-32 instructions, divided into technology groups.
Chapter 6 — Procedure Calls, Interrupts, and Exceptions. Describes the procedure stack and mechanisms 
provided for making procedure calls and for servicing interrupts and exceptions.
Chapter 7 — Programming with General-Purpose Instructions.  Describes basic load and store, program 
control, arithmetic, and string instructions that operat e on basic data types, general-purpose and segment regis-
ters; also describes system instructions that are executed in protected mode.
Chapter 8 — Programmin g with the x87 FPU.  Describes the x87 floating-point unit (FPU), including floating-
point registers and data types; gives an  overview of the floating-point instruction set and describes the processor's 
floating-point exception conditions.
Chapter 9 — Progra mming with Intel® MMX™ Technology. Describes Intel MMX technology, including MMX 
registers and data types; also provides an overview of the MMX instruction set. 
Chapter 10 — Programming with Intel® Streaming SIMD Extensions (Intel® SSE). Describes SSE exten-
sions, including XMM registers, the MXCSR register, and pack ed single precision floating-point data types; provides 
an overview of the SSE instruction set and gives guidelines for writing code that accesses the SSE extensions. 
Chapter 11 — Programming with Intel® Streaming SIMD Extensions 2 (Intel® SSE2).  Describes SSE2 
extensions, including XMM registers and packed double prec ision floating-point data ty pes; provides an overview 
of the SSE2 instruction set and gives gu idelines for writing code that accesses SSE2 extensions. This chapter also 
describes SIMD floating-point exceptions that can be generated with SSE and SSE2 instructions. It also provides general guidelines for incorporating support for SSE and SS E2 extensions into operating system and applications 
code.
Chapter 12 — Programming with Intel
® Streaming SIMD Extensions 3 (Intel® SSE3), Supplemental 
Streaming SIMD Extensions 3 (SSSE3), Intel® Streaming SIMD Extensions 4 (Intel® SSE4) and Intel® 
AES New Instructions (Intel® AES-NI).  Provides an overview of the SSE3 instruction set, Supplemental SSE3, 
SSE4, AESNI instructions, and guidelines for writing code that access these extensions.
Chapter 13 — Managing State Using the XSAVE Feature Set. Describes the XSAVE feature set instructions 
and explains how software can enable the XSAVE feature set and XSAVE-enabled features.
Chapter 14 — Programming with Intel® AVX, FMA, and Intel® AVX2. Provides an overview of the Intel® AVX

code.
Chapter 14 — Programming with Intel® AVX, FMA, and Intel® AVX2. Provides an overview of the Intel® AVX 
instruction set, FMA, and Intel® AVX2 extensions and gives guidelines for writing code that access these exten-
sions.
Chapter 15 — Programming with Intel® AVX-512. Provides an overview of the Intel® AVX-512 instruction set 
extensions and gives guidelines for writing code that access these extensions.
Chapter 16 — Programming with Intel® Transactional Synchronization Extensions. Describes the instruc-
tion extensions that support lock elision techniques to improve the performance of multi-threaded software with 
contended locks.
Chapter 17 — Control-flow Enforcement Technology. Provides an overview of the Control-flow Enforcement 
Technology (CET) and gives guidelines for writing code that access these extensions.
Chapter 18 — Programming with Intel® Advanced Matrix Extensions. Provides an overview of the Intel® 
Advanced Matrix Extensions and gives guidelines  for writing code that access these extensions.
Chapter 19 — Input/Output. Describes the processor’s I/O mechanism, including I/O port addressing, I/O 
instructions, and I/O protection mechanisms.
Chapter 20 — Processor Identifica tion and Feature Determination. Describes how to determine the CPU 
type and features available in the processor.1-6 Vol. 1ABOUT THIS MANUAL
Appendix A — EFLA GS Cross-Reference.  Summarizes how the IA-32 instructions affect the flags in the EFLAGS 
register.
Appendix B — EFLAGS Condition Codes. Summarizes how conditional jump, move, and ‘byte set on condition 
code’ instructions use condition code flags (OF, CF, ZF, SF, and PF) in the EFLAGS register.
Appendix C — Floating-Point Exceptions Summary. Summarizes exceptions raised by the x87 FPU floating-
point and SSE/SSE2/SSE3 floating-point instructions.
Appendix D — Guidelines for Writing SI MD Floating-Point Exception Handlers.  Gives guidelines for writing 
exception handlers for exceptions generated by SSE/SSE2/SSE3 floating-point instructions.
Appendix E — Intel® Memory Protection Extensions. Provides an overview of the Intel® Memory Protection 
Extensions, a feature that has been deprecated an d will not be available on future processors.
1.3 NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure form ats, for symbolic representation of instructions, and for 
hexadecimal and binary numbers. Th is notation is described below.
1.3.1 Bit and Byte Order
In illustrations of data structures in memory, smaller ad dresses appear toward the bottom of the figure; addresses 
increase toward the top. Bit positions are numbered from ri ght to left. The numerical value of a set bit is equal to 
two raised to the power of the bit position. Intel 64 and IA-32 processors are “little endian” machines; this means 
the bytes of a word are numbered starting fr om the least significant byte. See Figure 1-1.
1.3.2 Reserved Bits and Software Compatibility
In many register and memory layout descriptions, certain bits are marked as reserved . When bits are marked as 
reserved, it is essential for compatibility with future proce ssors that software treat these bits as having a future, 
though unknown, effect. The behavior of reserved bits sh ould be regarded as not only undefined, but unpredict-
able. 
Software should follow these guidelin es in dealing with reserved bits:
•Do not depend on the states of any reserved bits when testing the values of registers that contain such bits. 
Mask out the reserved bits before testing.
•Do not depend on the states of any reserved bi ts when storing to memory or to a register.
•Do not depend on the ability to retain in formation written into any reserved bits.Figure 1-1.  Bit and Byte OrderByte 3Data Structure 
Byte 1 Byte 2 Byte 031 2423 1615 87 0
LowestBit offset
28
24
20
16
12
8
40Address
Byte OffsetHighest
AddressVol. 1 1-7ABOUT THIS MANUAL
•When loading a register, always load the reserved bits wi th the values indicated in the documentation, if any, 
or reload them with values previously read from the same register.
NOTE
Avoid any software dependence upon the state of reserved bits in Intel 64 and IA-32 registers. Depending upon the values of reserved register  bits will make software dependent upon the 
unspecified manner in which the processor hand les these bits. Programs that depend upon 
reserved values risk incompatibility with future processors.
1.3.2.1  Instruction Operands
When instructions are represented symbolically, a subset of  the IA-32 assembly language is used. In this subset, 
an instruction has the following format:
label: mnemonic argument 1, argument2, argument3
where:
•A label  is an identifier which is followed by a colon.
•A mnemonic  is a reserved name for a class of instruction opcodes which have the same function.
•The operands argument1 , argument2 , and argument3  are optional. There may be from zero to three 
operands, depending on the opcode. When present, they take  the form of either literals or identifiers for data 
items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items 
declared in another part of the program (which may not be shown in the example).
When two operands are present in an ar ithmetic or logical instruction, the ri ght operand is the source and the left 
operand is the destination. 
LOADREG: MOV EAX, SUBTOTAL
In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand, 
and SUBTOTAL is the source operand. Some assembly la nguages put the source and destination in reverse order.
1.3.3 Hexadecimal an d Binary Numbers
Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for 
example, 0F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.
Base 2 (binary) numbers are represented by a string of  1s and 0s, sometimes followed by the character B (for 
example, 1010B). The “B” designation is only used in situ ations where confusion as to the type of number might 
arise.
1.3.4 Segmented Addressing
The processor uses byte addressing. This means memory  is organized and accessed as a sequence of bytes. 
Whether one or more bytes are being accessed, a byte addr ess is used to locate the byte or bytes memory. The 
range of memory that can be addressed is called an address space .
The processor also supports segmented addressing. This is  a form of addressing where a program may have many 
independent address spaces, called  segments . For example, a program can keep its code (instructions) and stack 
in separate segments. Code addresses would always refe r to the code space, and stack addresses would always 
refer to the stack space. The following notation is used to specify a byte ad dress within a segment: 
Segment-register:Byte-address
For example, the following segment address identifies the byte at address FF79H in th e segment pointed by the DS 
register:1-8 Vol. 1ABOUT THIS MANUAL
DS:FF79H
The following segment address identifies an instruction addr ess in the code segment. The CS register points to the 
code segment and the EIP register contains the address of the instruction.
CS:EIP
1.3.5 A New Syntax for CPUID, CR, and MSR Values
Obtain feature flags, status, and system information by us ing the CPUID instruction, by checking control register 
bits, and by reading model-specific registers. We are movi ng toward a new syntax to represent this information. 
See Figure 1-2.
1.3.6 Exceptions
An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to 
divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other condi-Figure 1-2.  Syntax for CPUID,  CR, and MSR Data PresentationInput value for EAX register
Output register and feature flag or field 
name with bit position(s)
Value (or range) of outputCPUID.01H:EDX.SSE[bit 25] = 1
CR4.OSFXSR[bit 9] = 1
IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1CPUID Input and Output
Control Register Values
Model-Specific Register ValuesExample CR name
Feature flag or field name 
with bit position(s)
Value (or range) of output
Example MSR name
Feature flag or field name with bit position(s)
SDM29002Vol. 1 1-9ABOUT THIS MANUAL
tions. Some types of exceptions may provide error codes.  An error code reports additional information about the 
error. An example of the notation used to sh ow an exception and error code is shown below:
#PF(fault code)
This example refers to a page-fault exception under conditions where an error code naming a type of fault is 
reported. Under some conditions, exceptions that produce e rror codes may not be able to report an accurate code. 
In this case, the error code is zero, as shown below for a general-protection exception:
#GP(0)
1.4 RELATED LITERATURE
Literature related to Intel 64 and IA-32 proc essors is listed and viewable on-line at: 
https://software.intel.com/en-us/articles/intel-sdm
See also: 
•The latest security information on Intel® products:

#GP(0)
See also: 
https://www.intel.com/content/www/us/en/security-center/default.html
•Software developer resources, guidance, and insights for security advisories:https://software.intel.com/security-software-guidance/
•The data sheet for a particular Intel 64 or IA-32 processor
•The specification update for a particular Intel 64 or IA-32 processor
•Intel® C++ Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
•Intel® Fortran Compiler documentation and online help:
•Intel® Software Development Tools:
https://software.intel.com/en-us/intel-sdp-home
•Intel® 64 and IA-32 Architectures Software Developer’s Manual (in one, four or ten volumes):
•Intel® 64 and IA-32 Architectures Optimization Reference Manual: 
https://software.intel.com/en-us/articles/intel-sdm#optimization
•Intel® Trusted Execution Technology Measured Launched Environment Programming Guide:
http://www.intel.com/content/www/us/ en/software-developers/intel-txt-software-development-guide.html
•Intel® Software Guard Extensions (Intel® SGX) Information:
https://software.intel.com/en-us/isa-extensions/intel-sgx
•Developing Multi-threaded Applicatio ns: A Platform Consistent Approach:
https://software.intel.com/sites/default/files/arti cle/147714/51534-developing-multithreaded-applica-
tions.pdf
•Using Spin-Loops on Intel® Pentium® 4 Processor and Intel® Xeon® Processor:
https://software.intel.com/sites/default/files/22/30/25602
•Performance Monitoring Unit Sharing Guide:
http://software.intel.com/file/30388
Literature related to select features in future Intel processors are available at:
•Intel® Architecture Instruction Set Extensions Programming Reference:
https://software.intel.com/en-us/isa-extensions
More relevant links are:
•Intel® Developer Zone:
https://software.intel.com/en-us1-10 Vol. 1ABOUT THIS MANUAL
•Developer centers:
http://www.intel.com/content/www/us/en/har dware-developers/developer-centers.html
•Processor support general link:
http://www.intel.com/support/processors/
•Intel® Hyper-Threading Technology (Intel® HT Technology):
http://www.intel.com/technology/platform-technology/hyper-threading/index.htmVol. 1 2-1CHAPTER 2
INTEL® 64 AND IA-32 ARCHITECTURES
2.1 BRIEF HISTORY OF INTEL® 64 AND IA-32 ARCHITECTURES
The following sections provide a summary of the major technical evolutions from IA-32 to Intel 64 architecture: 
starting from the Intel 8086 processor to the latest In tel® Core® 2 Duo, Core 2 Quad and Intel Xeon processor 
5300 and 7300 series. Object code created for processors released as early as 1978 still executes on the latest processors in the Intel 64 and IA-32 architecture families.
2.1.1 16-Bit Processors and Segmentation (1978)
The IA-32 architecture family was preceded by 16-bit processors, the 8086 and 8088. The 8086 has 16-bit regis-
ters and a 16-bit external data bus, with 20-bit addressing giving a 1-MByte address space. The 8088 is similar to 
the 8086 except it has an 8-bit external data bus. 
The 8086/8088 introduced segmentation to the IA-32 arch itecture. With segmentation, a 16-bit segment register 
contains a pointer to a memory segment of up to 64 KB ytes. Using four segment registers at a time, 8086/8088 
processors are able to address up to 256 KBytes withou t switching between segments. The 20-bit addresses that 
can be formed using a segment register and an additional  16-bit pointer provide a total address range of 1 MByte.
2.1.2 The Intel® 286 Processor (1982)
The Intel 286 processor introduced protected mode operatio n into the IA-32 architecture. Protected mode uses the 
segment register content as selectors or pointers into descriptor tables. Descriptors provide 24-bit base addresses 
with a physical memory size of up to 16 MBytes, suppo rt for virtual memory management on a segment swapping 
basis, and a number of protection mechanisms. These mechanisms include: 
•Segment limit checking.
•Read-only and execute-only segment options.
•Four privilege levels.
2.1.3 The Intel386™ Processor (1985)
The Intel386 processor was the first 32-bit processor in the IA-32 architecture family. It introduced 32-bit registers for use both to hold operands and for addressing. The lowe r half of each 32-bit Intel386 register retains the prop-
erties of the 16-bit registers of earlier generations, permitting backward compatibility. The processor also provides 
a virtual-8086 mode that allows for even greater effi ciency when executing programs created for 8086/8088 
processors. 
In addition, the Intel386 processor has support for:
•A 32-bit address bus that supports up to 4-GBytes of physical memory.
•A segmented-memory model and a flat memory model.
•Paging, with a fixed 4-KByte page size providing a method for virtual memory management.
•Support for parallel stages.
2.1.4 The Intel486™ Processor (1989)
The Intel486™ processor added more parallel execution capability  by expanding the Intel386 processor’s instruc-
tion decode and execution units into five pipelined stages. Ea ch stage operates in parallel with the others on up to 
five instructions in different stages of execution. 2-2 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
In addition, the processor added:
•An 8-KByte on-chip first-level cache that increased the pe rcent of instructions that could execute at the scalar 
rate of one per clock.
•An integrated x87 FPU.
•Power saving and system management capabilities.
2.1.5 The Intel® Pentium® Processor (1993)
The introduction of the Intel Pentium processor added a second execution pipeline to achieve superscalar perfor-
mance (two pipelines, known as u and v, together can ex ecute two instructions per clock). The on-chip first-level 
cache doubled, with 8 KBytes devoted to code and another 8 KBytes devoted to data. The data cache uses the MESI 
protocol to support more efficient write-back cache in ad dition to the write-through cache previously used by the 
Intel486 processor. Branch prediction with an on-chip br anch table was added to increase performance in looping 
constructs. 
•Extensions to make the virtual-8086 mode more efficient and allow for 4-MByte as well as 4-KByte pages.
•Internal data paths of 128 and 256 bits  add speed to internal data transfers.
•Burstable external data bus was increased to 64 bits.
•An APIC to support systems with multiple processors.
•A dual processor mode to support glueless two processor systems.
A subsequent stepping of the Pentium family introduced Intel MMX technolo gy (the Pentium Processor with MMX 
technology). Intel MMX technology uses  the single-instruction, multiple-dat a (SIMD) execution model to perform 
parallel computations on packed integer data contained in 64-bit registers. 
See Section 2.2.7, “SIMD Instructions.”
2.1.6 The P6 Family of Processors (1995—1999)
The P6 family of processors was based on a superscalar microarchitecture that set new performance standards; see 
also Section 2.2.1, “P6 Family Microarchitecture.” One of th e goals in the design of the P6 family microarchitecture 
was to exceed the performance of the Pentium  processor significantly while using the same 0.6-micrometer, four-
layer, metal BICMOS manufacturing process. Me mbers of this family include the following: 
•The Intel Pentium Pro processor  is three-way superscalar. Using parallel processing techniques, the 
processor is able on average to decode, dispatch, and complete execution of (retire) three instructions per 
clock cycle. The Pentium Pro introduced the dynamic execution (micro-data flow analysis, out-of-order 
execution, superior branch prediction, and speculative execution) in a superscalar implementation. The 
processor was further enhanced by its caches. It has the same two on-chip 8-KByte 1st-Level caches as the Pentium processor and an additional 256-KByte Leve l 2 cache in the same package as the processor.
•The Intel Pentium II processor  added Intel MMX technology to the P6  family processors along with new 
packaging and several hardware enhancements. The proce ssor core is packaged in the single edge contact 
cartridge (SECC). The Level l data and instruction caches  were enlarged to 16 KBytes each, and Level 2 cache 
sizes of 256 KBytes, 512 KBytes, and 1 MBytes are supp orted. A half-frequency backside bus connects the 
Level 2 cache to the processor. Multiple low-power states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep 
are supported to conserve power when idling.
•The Pentium II Xeon processor combined the premium characteristics of previous generations of Intel 
processors. This includes: 4-way, 8-way (and up) scalability and a 2 MBytes 2nd-Level cache running on a full-
frequency backside bus.
•The Intel Celeron processor  family focused on the value PC market segment. Its introduction offers an 
integrated 128 KBytes of Level 2 cache and a plastic pin grid array (P.P.G.A.) form factor to lower system design cost.

•The Intel Pentium III processor  introduced the Streaming SIMD Extens ions (SSE) to the IA-32 architecture. 
SSE extensions expand the SIMD execution model introd uced with the Intel MMX technology by providing a Vol. 1 2-3INTEL® 64 AND IA-32 ARCHITECTURES
new set of 128-bit registers and the ability to perform SIMD operations on packed single precision floating-
point values. See Section 2.2.7, “SIMD Instructions.”
•The Pentium III Xeon processor  extended the performance levels of the IA-32 processors with the 
enhancement of a full-speed, on-die, and Advanced Transfer Cache.
2.1.7 The Intel® Pentium® 4 Processor Family (2000—2006) 
The Intel Pentium 4 processor family is based on Intel NetBurst microarchitecture; see Section 2.2.2, “Intel 
NetBurst® Microarchitecture.”
The Intel Pentium 4 processor introduced Streaming SIMD Extensions 2 (SSE2); see Section 2.2.7, “SIMD Instruc-
tions.” The Intel Pentium 4 processor 3.40 GHz, suppor ting Hyper-Threading Technology introduced Streaming 
SIMD Extensions 3 (SSE3); see Se ction 2.2.7, “SIMD Instructions.”
Intel 64 architecture was introduced in the Intel Pentiu m 4 Processor Extreme Edition supporting Hyper-Threading 
Technology and in the Intel Pentiu m 4 Processor 6xx and 5xx sequences.
Intel® Virtualization Technology (Intel® VT) was introduced in the Intel Pentium 4 processor 672 and 662.
2.1.8 The Intel® Xeon® Processor (2001—2007)
Intel Xeon processors (with exception for dual-core Intel Xeon processor LV, Intel Xeon processor 5100 series) are 
based on the Intel NetBurst microarchitecture; see Section 2.2.2, “Intel NetBurst® Microarchitecture.” As a family, 
this group of IA-32 processors (more recently Intel 64 processors) is designed for use in multi-processor server 
systems and high-performance workstations. 
The Intel Xeon processor MP introduced support for Intel® Hyper-Threading Technology; see Section 2.2.8, “Intel® 
Hyper-Threading Technology.”
The 64-bit Intel Xeon processor 3.60 GHz (with an 800 MHz System Bus) was used to introduce Intel 64 architec-
ture. The Dual-Core Intel Xeon processor includes dual core technology. The Intel Xeon processor 70xx series 
includes Intel Virtualization Technology.
The Intel Xeon processor 5100 series introduces  power-efficient, high performance Intel Core  microarchitecture. 
This processor is based on Intel 64 architecture; it incl udes Intel Virtualization Te chnology and dual-core tech-
nology. The Intel Xeon processor 3000 series are also based on Intel Core microarchitecture. The Intel Xeon 
processor 5300 series introduces four processor cores in a physical package, they are also based on Intel Core microarchitecture. 
2.1.9 The Intel® Pentium® M Processor (2003—2006)
The Intel Pentium M processor family is a high performanc e, low power mobile processor family with microarchitec-
tural enhancements over previous generations of IA-32 Intel mobile processors. This family is designed for 
extending battery life and seamless integration with platfo rm innovations that enable new usage models (such as 
extended mobility, ultra thin form-facto rs, and integrated wireless networking).
Its enhanced microarchitecture includes:
•Support for Intel Architecture with Dynamic Execution.
•A high performance, low-power core manufactured usin g Intel’s advanced process technology with copper 
interconnect.
•On-die, primary 32-KByte instruction cache and 32-KByte write-back data cache.
•On-die, second-level cache (up to 2 MByte) with Advanced Transfer Cache Architecture.
•Advanced Branch Prediction and Data Prefetch Logic.
•Support for MMX technology, Streaming SIMD instructions, and the SSE2 instruction set.
•A 400 or 533 MHz, Source-Synchronous Processor System Bus.
•Advanced power management using Enhanced Intel SpeedStep® technology.2-4 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
2.1.10 The Intel® Pentium® Processor Extreme Edition (2005) 
The Intel Pentium processor Extreme Edition introduced du al-core technology. This technology provides advanced 
hardware multi-threading support. The processor is based on Intel NetBurst microarchitecture and supports Intel 
SSE, SSE2, SSE3, Intel Hyper-Threading Technology, and Intel 64 architecture.
See also:
•Section 2.2.2, “Intel NetBurst® Microarchitecture.”
•Section 2.2.3, “Intel® Core™ Microarchitecture.”
•Section 2.2.7, “SIMD Instructions.”
•Section 2.2.8, “Intel® Hyper-Threading Technology.”
•Section 2.2.9, “Multi-Core Technology.”
•Section 2.2.10, “Intel® 64 Architecture.”
2.1.11 The Intel® Core™ Duo and Intel® Core™ Solo Processors (2006—2007)
The Intel Core Duo processor offers power-efficient, dual -core performance with a low-power design that extends 
battery life. This family and the single-core Intel Core Solo processor offer microarchitectural enhancements over 
Pentium M processor family.
•Intel® Smart Cache which allows for efficient data sharing between two processor cores.
•Improved decoding and SIMD execution.
•Intel® Dynamic Power Coordination and Enhanced Intel® Deeper Sleep to reduce power consumption.
•Intel® Advanced Thermal Manager which features digital thermal sensor interfaces.
•Support for power-optimized 667 MHz bus.
The dual-core Intel Xeon processor LV is based on the same microarchitecture as Intel Core Duo processor, and 
supports IA-32 architecture.
2.1.12 The Intel® Xeon® Processor 5100, 5300 Series, and Inte l® Core™ 2 Processor Family 
(2006)
The Intel Xeon processor 3000, 3200, 5100, 5300, and 7300 series, Intel Pentium Dual-Core, Intel Core 2 Extreme, 
Intel Core 2 Quad processors, and Intel Core 2 Duo proce ssor family support Intel 64 architecture; they are based 
on the high-performance, power-efficient Intel® Core microarchitecture built on 65 nm process technology. The 
Intel Core microarchitecture includes the following innovative features:
•Intel® Wide Dynamic Execution to increase performance and execution throughput.
•Intel® Intelligent Power Capability to reduce power consumption.
•Intel® Advanced Smart Cache which allows for efficient data sharing between two processor cores.
•Intel® Smart Memory Access to increase data bandwidth and hide latency of memory accesses.
•Intel® Advanced Digital Media Boost which improves app lication performance using multiple generations of 
Streaming SIMD extensions.
The Intel Xeon processor 5300 series, Intel Core 2 Ex treme processor QX6800 series, and Intel Core 2 Quad 
processors support Intel quad-core technology.
2.1.13 The Intel® Xeon® Processor 5200, 5400, 7400 Series, and Intel® Core™ 2 Processor 
Family (2007)
The Intel Xeon processor 5200, 5400, and 7400 series, Inte l Core 2 Quad processor Q9000 Series, Intel Core 2 Duo 
processor E8000 series support Intel 64 archit ecture; they are based on the Enhanced Intel® Core microarchitec-Vol. 1 2-5INTEL® 64 AND IA-32 ARCHITECTURES
ture using 45 nm process technology. The Enhanced Intel Core microarchitecture provides the following improved 
features:
•A radix-16 divider, faster OS primitives further increases the performance of Intel® Wide Dynamic Execution. 
•Improves Intel® Advanced Smart Cache with Up to 50% larger level-two cache and up to 50% increase in way-
set associativity. 
•A 128-bit shuffler engine significantl y improves the performance of Intel® Advanced Digital Media Boost and 
SSE4.
The Intel Xeon processor 5400 series and the Intel Core 2 Quad processor Q9000 Series support Intel quad-core 
technology. The Intel Xeon processor 7400 series offers up to six processor cores and an L3 cache up to 16 MBytes.
2.1.14 The Intel Atom® Processor Family (2008)
The first generation of Intel Atom® processors are built on 45 nm proce ss technology. They are based on a new 
microarchitecture, Intel Atom® microarchitecture, which is optimized for ultra low power devices. The Intel Atom® 
microarchitecture features two in-order execution pipelines that minimize power consumption, increase battery 
life, and enable ultra-small form factors. The initial Intel Atom Processor family and subsequent generations 
including Intel Atom processor D2000, N2000, E2000, Z2 000, C1000 series provide the following features:
•Enhanced Intel® SpeedStep® Technology.
•Intel® Hyper-Threading Technology.
•Deep Power Down Technology with Dynamic Cache Sizing.
•Support for instruction set extensions up to and including Supplemental Streaming SIMD Extensions 3 
(SSSE3).
•Support for Intel® Virtualization Technology.
•Support for Intel® 64 Architecture (excluding Intel Atom processor Z5xx Series).
2.1.15 The Intel Atom® Processor Family Based on Silvermont Microarchitecture (2013)
Intel Atom Processor C2xxx, E3xxx, S1xxx series are base d on the Silvermont microarchitecture. Processors based 
on the Silvermont microarchitecture support instruction set extensions up to and in cluding SSE4.2, AESNI, and 
PCLMULQDQ.
2.1.16 The Intel® Core™ i7 Processor Family (2008)
The Intel Core i7 processor 900 series supports Intel 64 architecture, and is based on Nehalem microarchitecture

(SSSE3).
The Intel Core i7 processor 900 series supports Intel 64 architecture, and is based on Nehalem microarchitecture 
using 45 nm process technology. The Intel Core i7 proc essor and Intel Xeon processor 5500 series include the 
•Intel® Turbo Boost Technology converts therma l headroom into higher performance. 
•Intel® HyperThreading Technology in conjunction with Qu adcore to provide four cores and eight threads. 
•Dedicated power control unit to reduce active and idle power consumption.
•Integrated memory controller on the processo r supporting three channels of DDR3 memory.
•8 MB inclusive Intel® Smart Cache.
•Intel® QuickPath interconnect (QPI) providing point-to-point link to chipset.
•Support for SSE4.2 and SSE4.1 instruction sets.
•Second generation Intel Virtualization Technology.
2.1.17 The Intel® Xeon® Processor 7500 Series (2010)
The Intel Xeon processor 7500 and 6500 series are based on Nehalem microarchitecture using 45 nm process tech-
nology. These processors support the same features descr ibed in Section 2.1.16, plus the following features:2-6 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
•Up to eight cores per physical processor package.
•Up to 24 MB inclusive Intel® Smart Cache.
•Provides Intel® Scalable Memory Interconnect (Intel® SMI) channels with Intel® 7500 Scalable Memory Buffer 
to connect to system memory. 
•Advanced RAS supporting software recoverable machine check architecture.
2.1.18 2010 Intel® Core™ Processor Family (2010)
The 2010 Intel Core processor family sp ans Intel Core i7, i5, and i3 processors. These processors are based on 
Westmere microarchitecture using 32 nm process technology. The features can include:
•Deliver smart performance using Intel Hyper-Threadin g Technology plus Intel Turbo Boost Technology. 
•Enhanced Intel Smart Cache and integrated memory controller.
•Intelligent power gating.
•Repartitioned platform with on-die inte gration of 45 nm integrated graphics.
•Range of instruction set support up to AESNI, PCLMULQDQ, SSE4.2 and SSE4.1.
2.1.19 The Intel® Xeon® Processor 5600 Series (2010)
The Intel Xeon processor 5600 series are based on Westmere microarchitecture using 32 nm process technology. 
They support the same features described in Section 2.1.16, plus the following features:
•Up to six cores per physical processor package.
•Up to 12 MB enhanced Intel® Smart Cache.
•Support for AESNI, PCLMULQDQ, SSE4.2 and SSE4.1 instruction sets.
•Flexible Intel Virtualization Technologies across processor and I/O.
2.1.20 The Second Generation Intel® Core™ Processor Family (2011)
The Second Generation Intel Core processor family spans Intel Core i7, i5, and i3 processors based on the Sandy 
Bridge microarchitecture. These processors are built from  32 nm process technology and have features including:
•Intel Turbo Boost Technology for Intel Core i5 and i7 processors.
•Intel Hyper-Threading Technology. 
•Processor graphics and built-in visual features like Intel® Quick Sync Video, Intel® InsiderTM, etc.
•Range of instruction set support up to AV X, AESNI, PCLMULQDQ, SSE4.2 and SSE4.1.
The Intel Xeon processor E3-1200 product family is also based on the Sandy Bridge microarchitecture.The Intel Xeon processor E5-2400/1400 product families are based on the Sandy Bridge-EP microarchitecture.
The Intel Xeon processor E5-4600/2600/1600 product fami lies are based on the Sandy Bridge-EP microarchitec-
ture and provide support for multiple sockets.
2.1.21 The Third Generation Intel® Core™ Processor Family (2012)
The Third Generation Intel Core processor family spans Inte l Core i7, i5, and i3 processors based on the Ivy Bridge 
microarchitecture. The Intel Xeon processor E7-8800/4800/2800 v2 product families and Intel Xeon processor E3-1200 v2 product family are also based on the Ivy Bridge microarchitecture.
The Intel Xeon processor E5-2400/1400 v2 product famili es are based on the Ivy Bridge-EP microarchitecture.
The Intel Xeon processor E5-4600/2600/1600 v2 product fa milies are based on the Ivy Bridge-EP microarchitec-
ture and provide support for multiple sockets.Vol. 1 2-7INTEL® 64 AND IA-32 ARCHITECTURES
2.1.22 The Fourth Generation Intel® Core™ Processor Family (2013)
The Fourth Generation Intel Core processor family spans In tel Core i7, i5, and i3 processors based on the Haswell 
microarchitecture. Intel Xeon processor E3-1200 v3 product family is also based on the Haswell microarchitecture.
2.2 MORE ON SPECIFIC ADVANCES
The following sections provide more  information on major innovations.
2.2.1 P6 Family Microarchitecture
The Pentium Pro processor introduced a new microarchite cture commonly referred to as P6 processor microarchi-
tecture. The P6 processor microarchitecture was later e nhanced with an on-die, Level 2 cache, called Advanced 
Transfer Cache.
The microarchitecture is a three-way superscalar, pipelined architecture. Three-way superscalar means that by 
using parallel processing techniques, the processor is able  on average to decode, dispatch, and complete execution 
of (retire) three instructions per clock cycle. To handle th is level of instruction throughput, the P6 processor family 
uses a decoupled, 12-stage superpipeline that supports out-of-order instruction execution. 
Figure 2-1 shows a conceptual view of the P6 processor microarchitecture pipeline with the Advanced Transfer 
Cache enhancement. 
To ensure a steady supply of instructions and data for the instruction execution pipeline, the P6 processor microar-
chitecture incorporates two cache levels. The Level 1 cache provides an 8-KByte instruction cache and an 8-KByte 
data cache, both closely coupled to the pipeline. The Level 2 cache provides 256-KBy te, 512-KByte, or 1-MByte 
static RAM that is coupled to the core processor through a full clock-speed 64-bit cache bus.
The centerpiece of the P6 processor microarchitecture is an out-of-order execution mechanism called dynamic 
execution. Dynamic execution incorporates three data-processing concepts:Figure 2-1.  The P6 Processor Microarchitect ure with Advanced Transfer Cache EnhancementBus Unit
2nd Level Cache
On-die, 8-way1st  Level  Cache
4-way, low latency
Fetch/
DecodeExecution
Cache
Microcode
ROMExecution
Out-of-Order
CoreRetirement
BTSs/Branch PredictionSystem Bus
Branch  History  UpdateFrequently  used
Less  frequently  used
Front End
OM165202-8 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
•Deep branch prediction allows the processor to decode instructions beyond branches to keep the instruction 
pipeline full. The P6 processor family  implements highly optimized branch prediction algorithms to predict the 
direction of the instruction.
•Dynamic data flow analysis  requires real-time analysis of the flow of data through the processor to 
determine dependencies and to detect opportunities for out-of-order instruction execution. The out-of-order 
execution core can monitor many instructions and execute these instructions in the order that best optimizes the use of the processor’s multiple execution units, while maintaining the data integrity.
•Speculative execution refers to the processor’s ability to execute instructions that lie beyond a conditional 
branch that has not yet been resolved, and ultimately to commit the results in the order of the original 
instruction stream. To make speculative execution possible, the P6 processor microarchitecture decouples the dispatch and execution of instructions from the commitm ent of results. The processor’s out-of-order execution 
core uses data-flow analysis to execute all available instructions in the instruction pool and store the results in 
temporary registers. The retirement unit then linearly searches the instruction pool for completed instructions that no longer have data dependencies with other in structions or unresolved branch predictions. When 
completed instructions are found, the retirement unit commits the results of these instructions to memory 
and/or the IA-32 registers (the processor’s eight general-purpose registers and eight x87 FPU data registers) 
in the order they were originally issued and retires the instructions from the instruction pool.
2.2.2 Intel NetBurst® Microarchitecture
The Intel NetBurst microarchitecture provides:
•The Rapid Execution Engine.
— Arithmetic Logic Units (ALUs) run at twice the processor frequency.
— Basic integer operations can dispatch in 1/2 processor clock tick.
•Hyper-Pipelined Technology.— Deep pipeline to enable industry-leading clock rates for desktop PCs and servers.
— Frequency headroom and scalability to continue leadership into the future.
•Advanced Dynamic Execution.
— Deep, out-of-order, speculative execution engine.
•Up to 126 instructions in flight.
•Up to 48 loads and 24 stores in pipeline1.
— Enhanced branch prediction capability.
•Reduces the misprediction penalty associated with deeper pipelines.
•Advanced branch prediction algorithm.
•4K-entry branch target array.
•New cache subsystem.— First level caches.
•Advanced Execution Trace Cache stores decoded instructions.

•Execution Trace Cache removes decoder latency from main execution loops.
•Execution Trace Cache integrates path of program execution flow into a single line.
•Low latency data cache.
— Second level cache.
•Full-speed, unified 8-way Level 2 on-die Advance Transfer Cache.
•Bandwidth and performance increases with processor frequency.
1. Intel 64 and IA-32 processors based on the Intel NetBurst microarchitecture at 90 nm process can handle more than 24 stores i n 
flight.Vol. 1 2-9INTEL® 64 AND IA-32 ARCHITECTURES
•High-performance, quad-pumped bus interface to th e Intel NetBurst microarchitecture system bus.
— Supports quad-pumped, scalable bus clock to achieve up to 4X effective speed.
— Capable of delivering up to 8. 5 GBytes of bandwidth per second.
•Superscalar issue to enable parallelism.
•Expanded hardware registers with renaming to avoid register name space limitations.
•64-byte cache line size (transfers data up to two lines per sector).
Figure 2-2 is an overview of the Intel NetBurst microarc hitecture. This microarchitecture pipeline is made up of 
three sections: (1) the front end pipeline, (2) the out-of-order execution core, and (3) the retirement unit. 
2.2.2.1  The Front End Pipeline
The front end supplies instructions in program order to the out-of-order execution core. It performs a number of functions:
•Prefetches instructions that are likely to be executed.
•Fetches instructions that have not already been prefetched.
•Decodes instructions into micro-operations.
•Generates microcode for complex instructions and special-purpose code.
•Delivers decoded instructions from the execution trace cache.
•Predicts branches using highly advanced algorithm.
The pipeline is designed to address common problems in  high-speed, pipelined microprocessors. Two of these 
problems contribute to major sources of delays:
•Time to decode instructions fetched from the target.Figure 2-2.  The Intel NetBurst ® MicroarchitectureFetch/DecodeTrace Cache
Microcode ROMExecution
Out-Of-Order
CoreRetirement1st Level Cache
4-way2nd Level Cache
 8-Way
BTBs/Branch PredictionBus UnitSystem Bus
Frequently used paths
Less frequently used
paths
Front End3rd Level  Cache
Optional
Branch History Update
OM165212-10 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
•Wasted decode bandwidth due to branches or branch target in the middle of cache lines.
The operation of the pipeline’s trace cache addresses these issues. Instructions are constantly being fetched and 
decoded by the translation engine (part of the fetch/deco de logic) and built into sequences of micro-ops called 
traces. At any time, multiple traces (representing prefet ched branches) are being stored in the trace cache. The 
trace cache is searched for the instruction that follows the active branch. If the instruction also appears as the first 
instruction in a pre-fetched branch, the fetch and decode of instructions from the memory hierarchy ceases and the 
pre-fetched branch becomes the new source of instructions (see Figure 2-2).
The trace cache and the translation engine have cooper ating branch prediction hardware. Branch targets are 
predicted based on their linear addresses using branch target buffers (BTBs) and fetched as soon as possible.
2.2.2.2  Out-Of-Order Execution Core
The out-of-order execution core’s ability to execute instructio ns out of order is a key factor in enabling parallelism. 
This feature enables the processor to reorder instructions so that if one micro-op is delayed, other micro-ops may 
proceed around it. The processor employs several buffers to smooth the flow of micro-ops.
The core is designed to facilitate parallel execution. It can dispatch up to six micro-ops per cycle (this exceeds trace 
cache and retirement micro-op bandwidth). Most pipelines can start executing a new micro-op every cycle, so 
several instructions can be in flight at a time for each pipeline. A number of arithmetic logical unit (ALU) instruc-
tions can start at two per cycle; many floating-point instructions can start once every two cycles. 
2.2.2.3  Retirement Unit
The retirement unit receives the results of the executed  micro-ops from the out-of-order execution core and 
processes the results so that the architectural state updates according to the original program order. 
When a micro-op completes and writes its result, it is reti red. Up to three micro-ops may be retired per cycle. The 
Reorder Buffer (ROB) is the unit in the processor which buffers completed micro-ops, updates the architectural 
state in order, and manages the ordering of exceptions. The retirement section also keeps track of branches and 
sends updated branch target information to the BTB. The BTB then purges pre-fetched traces that are no longer 
needed.
2.2.3 Intel® Core™ Microarchitecture
Intel Core microarchitecture introduces the following feat ures that enable high performance and power-efficient 
performance for single-threaded as well as multi-threaded workloads:
•Intel® Wide Dynamic Execution  enable each processor core to fetch, dispatch, execute in high bandwidths 
to support retirement of up to four instructions per cycle.
— Fourteen-stage efficient pipeline.— Three arithmetic logical units.
— Four decoders to decode up to five instruction per cycle.
— Macro-fusion and micro-fusion to improve front-end throughput.— Peak issue rate of dispatching up to six micro-ops per cycle.
— Peak retirement bandwidth of up to 4 micro-ops per cycle.
— Advanced branch prediction.— Stack pointer tracker to improve efficiency of executing function/procedure entries and exits.
•Intel® Advanced Smart Cache  delivers higher bandwidth from the second level cache to the core, and 
optimal performance and flexibility for single -threaded and multi-threaded applications.
— Large second level cache up to 4 MB and 16-way associativity.
— Optimized for multicor e and single-threaded execution environments.
— 256-bit internal data path to improve band width from L2 to first-level data cache.Vol. 1 2-11INTEL® 64 AND IA-32 ARCHITECTURES
•Intel® Smart Memory Access  prefetches data from memory in response to data access patterns and reduces 
cache-miss exposure of out-of-order execution.
— Hardware prefetchers to reduce effective latency of second-level cache misses.
— Hardware prefetchers to reduce effective latency of first-level data cache misses.
— Memory disambiguation to improve efficiency of speculative execution engine.
•Intel® Advanced Digital Media Boost  improves most 128-bit SIMD instructions with single-cycle 
throughput and floating-point operations.
— Single-cycle throughput of most 128-bit SIMD instructions.— Up to eight floating-point operations per cycle.
— Three issue ports available to dispatching SIMD instructions for execution.
Intel Core 2 Extreme, Intel Core 2 Duo processors and Intel Xeon processor 5100 series implement two processor 
cores based on the Intel Core microarchitecture, the functi onality of the subsystems in each core are depicted in 
Figure 2-3. 
2.2.3.1  The Front End
The front end of Intel Core microarchitecture provides several enhancements to feed the Intel Wide Dynamic 
Execution engine:
•Instruction fetch unit prefetches instructions into an in struction queue to maintain steady supply of instruction 
to the decode units.
•Four-wide decode unit can decode 4 instructions per cycle or 5 instructions per cycle with Macrofusion.
•Macrofusion fuses common sequence of two instructions as one decoded instruction (micro-ops) to increase decoding throughput.
•Microfusion fuses common sequence of two micro-ops as one micro-ops to improve retirement throughput.Figure 2-3.  The Intel® Core™ Micr oarchitecture Pipeline FunctionalityDecode
ALU
Branch
MMX/SSE/FP
MoveLoadShared L2 Cache
Up to 10.7 GB/s 
FSB
Retirement Unit 
(Re-Order Buffer)
L1D Cache and DTLBInstruction Fetch and PreDecode
Instruction Queue
Rename/Alloc
ALU
FAdd
MMX/SSEALU
FMul
MMX/SSESchedulerMicro-
code 
ROM
Store2-12 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
•Instruction queue provides caching of short loops to improve efficiency.
•Stack pointer tracker improves efficiency of executing procedure/function entries and exits.
•Branch prediction unit employs dedicated hardware to ha ndle different types of bran ches for improved branch 
prediction.
•Advanced branch prediction algorithm directs instruction fetch unit to fetch instructions likely in the architec-tural code path for decoding.
2.2.3.2  Execution Core 
The execution core of the Intel Core microarchitecture is superscalar and can process instructions out of order to increase the overall rate of instructions executed per cy cle (IPC). The execution core employs the following feature 
to improve execution throughput and efficiency:
•Up to six micro-ops can be dispatched to execute per cycle.
•Up to four instructions can be retired per cycle.
•Three full arithmetic logical units.
•SIMD instructions can be dispatched through three issue ports.

•Most SIMD instructions have 1-cycle throughput (including 128-bit SIMD instructions).
•Up to eight floating-point operation per cycle.
•Many long-latency computation operation are pipelined in hardware to increase overall throughput.
•Reduced exposure to data access delays using Intel Smart Memory Access.
2.2.4 Intel Atom® Microarchitecture
Intel Atom microarchitecture maximizes power-efficient performance for single-threaded and multi-threaded workloads by providing:
•Advanced Micro-Ops Execution  
— Single-micro-op instruction execution from decode to retirement, including instructions with register-only, 
load, and store semantics.
— Sixteen-stage, in-order pipeline optimized for throughput and reduced power consumption.
— Dual pipelines to enable decode, issue, executio n, and retirement of two instructions per cycle.
— Advanced stack pointer to improve efficien cy of executing function entry/returns.
•Intel® Smart Cache
— Second level cache is 512 KB and 8-way associativity.
— Optimized for multi-thre aded and single-threaded execution environments
— 256-bit internal data path between L2 and L1 data caches improves high bandwidth.
•Efficient Memory Access— Efficient hardware prefetchers to L1 and L2, speculativ ely loading data likely to be requested by processor 
to reduce cache miss impact.
•Intel® Digital Media Boost
— Two issue ports for dispatching SIMD instructions to execution units.
— Single-cycle throughput for most 128-bit integer SIMD instructions.
— Up to six floating-point operations per cycle.— Up to two 128-bit SIMD integer operations per cycle.
— Safe Instruction Recognition (SIR) to allow long-latency floating-point operations to retire out of order with 
respect to integer instructions.Vol. 1 2-13INTEL® 64 AND IA-32 ARCHITECTURES
2.2.5 Nehalem Microarchitecture
Nehalem microarchitecture provides the foundation for many fe atures of Intel Core i7 processors. It builds on the 
success of 45 nm Intel Core microarchitecture and provides the following feature enhancements:
•Enhanced processor core
— Improved branch prediction and recovery from misprediction.
— Enhanced loop streaming to improve front end performance and reduce power consumption.— Deeper buffering in out-of-order  engine to extract parallelism.
— Enhanced execution units to provide acceleration in CRC, string/text processing and data shuffling.
•Smart Memory Access
— Integrated memory controller provides low-latency access to system memory and scalable memory 
bandwidth.
— New cache hierarchy organization with shared, inclusive L3 to reduce snoop traffic.— Two level TLBs and increased TLB size.— Fast unaligned memory access.
•HyperThreading Technology
— Provides two hardware threads (logical processors) per core.
— Takes advantage of 4-wide execution engi ne, large L3, and massive memory bandwidth.
•Dedicated Power management Innovations
— Integrated microcontroller with optimized embe dded firmware to manage power consumption.
— Embedded real-time sensors for temperature, current, and power.
— Integrated power gate to turn off/on per-core power consumption— Versatility to reduce power consumption of memory, link subsystems.
2.2.6 Sandy Bridge Microarchitecture
Sandy Bridge microarchitecture builds on the successes of Intel® Core™ microarchitecture and Nehalem microar-
chitecture. It offers the following features:
•Intel Advanced Vector Extensions (Intel AVX).
— 256-bit floating-point instruction set extensions to the 128-bit Intel Streaming SIMD Extensions, providing 
up to 2X performance benefits relative to 128-bit code.
— Non-destructive destination encoding offers more flexible coding techniques.
— Supports flexible migration and co-existence between 256-bit AVX code, 128-bit AVX code and legacy 128-
bit SSE code.
•Enhanced front-end and execution engine.
— New decoded Icache component that improves fron t-end bandwidth and reduces branch misprediction 
penalty.
— Advanced branch prediction.
— Additional macro-fusion support.— Larger dynamic execution window.
— Multi-precision integer arithmetic enhancements (ADC/SBB, MUL/IMUL).
— LEA bandwidth improvement.— Reduction of general execution stalls (read ports, writeback conflicts, bypass latency, partial stalls).
— Fast floating-point exception handling.2-14 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
— XSAVE/XRSTORE performance improvements and XSAVEOPT new instruction.
•Cache hierarchy improvements for wider data path.
— Doubling of bandwidth enabled by two symmetric ports for memory operation.
— Simultaneous handling of more in-flight load s and stores enabled by increased buffers.
— Internal bandwidth of two loads and one store each cycle.
— Improved prefetching.
— High bandwidth low latency LLC architecture.— High bandwidth ring architecture of on-die interconnect.
For additional information on Intel
® Advanced Vector Extensions (AVX), see Section 5.13, “Intel® Advanced Vector 
Extensions (Intel® AVX)” and Chapter 14, “Programming wi th Intel® AVX, FMA, and Intel® AVX2” in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 1.
2.2.7 SIMD Instructions
Beginning with the Pentium II and Pentium with Intel MMX te chnology processor families, six extensions have been 
introduced into the Intel 64 and IA-32 architectures to pe rform single-instruction multiple-data (SIMD) operations. 
These extensions include the MMX technology, SSE extens ions, SSE2 extensions, SSE3 extensions, Supplemental 
Streaming SIMD Extensions 3, and SSE4. Each of these ex tensions provides a group of instructions that perform 
SIMD operations on packed integer and/or packed floating-point data elements. 
SIMD integer operations can use the 64-bit MMX or the 128-bit XMM registers. SIMD floating-point operations use 
128-bit XMM registers. Figure 2-4 shows a summary of the various SIMD extensions (M MX technology, Intel SSE, 
Intel SSE2, Intel SSE3, SSSE3, and Intel SSE4), the data ty pes they operate on, and how the data types are packed 
into MMX and XMM registers.
The Intel MMX technology was introduced in the Pentium II and Pentium with MMX technology processor families. 
MMX instructions perform SIMD operations on packed byte, word, or doubleword integers located in MMX registers. 
These instructions are useful in applications that operate on integer arrays and streams of integer data that lend 
themselves to SIMD processing.
Intel SSE was introduced in the Pentium III processor family. Intel SSE instructions operate on packed single preci-
sion floating-point values contained in XMM registers and on packed integers contained in MMX registers. Several 
Intel SSE instructions provide state management, cache control, and memory ordering operations. Other Intel SSE 
instructions are targeted at applications that operate on ar rays of single precision floating-point data elements (3-
D geometry, 3-D rendering, and video encoding and decoding applications).
Intel SSE2 was introduced in the Pentium 4 and Intel Xeon processors. Intel SSE2 instructions operate on packed 
double precision floating-poi nt values contained in XMM registers and on packed integers contained in MMX and 
XMM registers. Intel SSE2 integer instructions extend IA -32 SIMD operations by adding new 128-bit SIMD integer 
operations and by expanding existing 64-bit SIMD integer operations to 128-bi t XMM capability. Intel SSE2 instruc-
tions also provide new cache control and memory ordering operations.
Intel SSE3 was introduced with the Pentium 4 processor su pporting Hyper-Threading Technology (built on 90 nm 
process technology). Intel SSE3 offers 13 instructions that accelerate performance of Streaming SIMD Extensions technology, Streaming SIMD Extensions 2 technology, and x87-FP math capabilities.
SSSE3 was introduced with the Intel Xeon processor 5100 series and Intel Core 2 processor family. SSSE3 offer 32 
instructions to accelerate processing of SIMD integer data.
Intel SSE4 offers 54 instructions. 47 of them are referre d to as Intel SSE4.1 instructions. Intel SSE4.1 was intro-
duced with the Intel Xeon processor 54 00 series and Intel Core 2 Extreme processor QX9650. The other seven Intel 
SSE4 instructions are referred to as Intel SSE4.2 instructions.
Intel AES-NI and PCLMULQDQ introduced seven new instructions. Six of them are primitives for accelerating algo-
rithms based on AES encryption /decryption standard, and are referred to as Intel AES-NI.
The PCLMULQDQ instruction accelerates general-purpose bl ock encryption, which can perform carry-less multipli-
cation for two binary numbers up to 64-bit wide.Vol. 1 2-15INTEL® 64 AND IA-32 ARCHITECTURES
Intel 64 architecture allows four generations of 128-bit SIMD extensions to access up to 16 XMM registers. IA-32 
architecture provides eight XMM registers.
Intel® Advanced Vector Extensions offers comprehensive arch itectural enhancements over previous generations of 
Streaming SIMD Extensions. Intel AVX introduces the following architectural enhancements:
•Support for 256-bit wide vectors and SIMD register set.

•256-bit floating-point instruction set enhancement with  up to 2X performance gain relative to 128-bit 
•Instruction syntax support for generalized three-operand syntax to improve instruction programming flexibility 
and efficient encoding of new instruction extensions.
•Enhancement of legacy 128-bit SIMD instruction extensio ns to support three operand syntax and to simplify 
compiler vectorization of high-level language expressions.
•Support flexible deployment of 256-bit AVX code, 128- bit AVX code, legacy 128-bit code and scalar code.
In addition to performance considerations, programmers should also be cognizant of the implications of VEX-
encoded AVX instructions with the expectations of system software components that manage the processor state 
components enabled by XCR0. For additional information see Section 2.3.10.1, “Vector Length Transition and 
Programming Considerations” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
See also: 
•Section 5.4, “MMX Instructions,” and Chapter 9, “Programming with Intel® MMX™ Technology.”
•Section 5.5, “Intel® SSE Instructions,” and Chapter 10, “Programming with Intel® Streaming SIMD Extensions 
(Intel® SSE).”
•Section 5.6, “Intel® SSE2 Instructions,” and Chap ter 11, “Programming with Intel® Streaming SIMD 
Extensions 2 (Intel® SSE2).”
•Section 5.7, “Intel® SSE3 Instructions,” Section 5.8,  “Supplemental Streaming SIMD Extensions 3 (SSSE3) 
Instructions,” Section 5.9, “Intel® SSE4 Instructions ,” and Chapter 12, “Programming with Intel® SSE3, 
SSSE3, Intel® SSE4, and Intel® AES-NI.”2-16 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
2.2.8 Intel® Hyper-Threading Technology
Intel Hyper-Threading Technology (Intel HT Technology) was developed to improve the performance of IA-32 
processors when executing multi-threaded operating system  and application code or single-threaded applications 
under multi-tasking environments. The technology enables a single physical processor to execute two or more 
separate code streams (threads) concurrently using shared execution resources. 
Intel HT Technology is one form of hardware multi-threading capability in IA-32 processor families. It differs from 
multi-processor capability using separate physically distinct packages with each physical processor package mated 
with a physical socket. Intel HT Technology provides hard ware multi-threading capability with a single physical 
package by using shared execution resources in a processor core.
Architecturally, an IA-32 processor that supports Intel HT Technology consists of two or more logical processors, 
each of which has its own IA-32 architectural state. Each logical processor consists of a full set of IA-32 data regis-ters, segment registers, control registers, debug registers,  and most of the MSRs. Each also has its own advanced 
programmable interrupt controller (APIC). 
Figure 2-5 shows a comparison of a processor that suppor ts Intel HT Technology (implemented with two logical 
processors) and a traditional dual processor system. Figure 2-4.  SIMD Extensions, Re gister Layouts, and Data Types4 Packed Word Integers8 Packed Byte Integers
2 Packed Doubleword IntegersMMX Registers
QuadwordMMX Technology - SSSE3Data Type Register Layout SIMD Extension
SSE - AVX
4 Packed Single Precision
Floating-Point Values
2 Packed Double Precision
8 Packed Word Integers16 Packed Byte Integers
4 Packed Doubleword
2 Quadword Integers
Double QuadwordIntegersXMM Registers
8 Packed SP FP Values
4 Packed DP FP ValuesYMM RegistersAVX
2 128-bit DataVol. 1 2-17INTEL® 64 AND IA-32 ARCHITECTURES
Unlike a traditional MP system configurat ion that uses two or more separate physical IA-32 processors, the logical 
processors in an IA-32 processor supporting Intel HT Technology share the core resources of the physical 
processor. This includes the execution engine and the syst em bus interface. After power up and initialization, each 
logical processor can be independently directed to execute a specified thread, interrupted, or halted.
Intel HT Technology leverages the process and thread-level parallelism found in contemporary operating systems 
and high-performance applications by providing two or more  logical processors on a single chip. This configuration 
allows two or more threads1 to be executed simultaneously on each a physical processor. Each logical processor 
executes instructions from an application thread using the resources in the processor core. The core executes 
these threads concurrently, using out-of-order instruction scheduling to maximize the use of execution units during each clock cycle.
2.2.8.1  Some Implementation Notes
All Intel HT Technology configurations require:
•A processor that supports Intel HT Technology.
•A chipset and BIOS that utilize the technology.
•Operating system optimizations.
See http://www.intel.com/products/ht/hyperthreading_more.htm  for information.
At the firmware (BIOS) level, the basic procedures to initialize the logical processors in a processor supporting Intel 
HT Technology are the same as those for a traditional DP or MP platform. The mechanisms that are described in the 
Multiprocessor Specification, Version 1.4, to power-up and in itialize physical processors in an MP system also apply 
to logical processors in a processor that supports Intel HT Technology. 
An operating system designed to run on a traditional DP or MP platform may use CPUID to determine the presence 
of hardware multi-threading support feature and the number of logical processors they provide.
Although existing operating system and application code sh ould run correctly on a processor that supports Intel HT 
Technology, some code modifications are recommended to get the optimum benefit. These modifications are discussed in Chapter 7, “Multiple-Processor Management,” Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A.Figure 2-5.  Comparison of an  IA-32 Processor Supporting In tel® Hyper-Threading Technology
and a Traditional Dual Processor System
1. In the remainder of this document, the term “thread” will be  used as a general term for th e terms “process” and “thread.”Processor Core Processor Core Processor CoreAS AS AS ASTraditional Multiple Processor (MP) SystemIA-32 Processor Supporting
Hyper-Threading Technology
AS = IA-32 Architectural StateIA-32 processor IA-32 processor
Two logical 
processors that share a single coreEach processor is a 
separate physical packageIA-32 processor
OM165222-18 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
2.2.9 Multi-Core Technology
Multi-core technology is another form of hardware multi- threading capability in IA-32 processor families. Multi-core 
technology enhances hardware multi-threading capability by providing two or more execution cores in a physical 
package.
The Intel Pentium processor Extreme Edition is the first me mber in the IA-32 processor family to introduce multi-
core technology. The processor provides  hardware multi-threading support with both two processor cores and Intel 
Hyper-Threading Technology. This means that the Intel Pe ntium processor Extreme Edition provides four logical 
processors in a physical package (two logical processors for each processor core). The Dual-Core Intel Xeon 
processor features multi-core, Intel Hyper-Threading Technology and supports multi-processor platforms. 
The Intel Pentium D processor also features multi-core technology. This processor provides hardware multi-
threading support with two processor cores but does not offer Intel Hyper-Threading Te chnology. This means that 
the Intel Pentium D processor provides two logical processors in a physical package, with each logical processor 
owning the complete execution resources of a processor core.
The Intel Core 2 processor family, Intel Xeon processor 3000 series, Intel Xeon processor 5100 series, and Intel 
Core Duo processor offer power-efficient multi-core tec hnology. The processor contains two cores that share a 
smart second level cache. The Level 2 cache enables efficient data sharing between two cores to reduce memory 
traffic to the system bus.
The Pentium® dual-core processor is based on the same technology as the Intel Core 2 Duo processor family.
The Intel Xeon processor 7300, 5300, and 3200 series, Inte l Core 2 Extreme Quad-Core processor, and Intel Core 
2 Quad processors support Intel quad-core technology. The Quad-core Intel Xeon processors and the Quad-Core 
Intel Core 2 processor family are also in Figure 2-7. Figure 2-6.  Intel 64 and IA-32 Processors that Support Dual-Core Architectual 
State
System BusExecution Engine
Local APIC Local APICExecution EngineArchitectual 
State
Bus Interface Bus InterfaceLocal APIC Local APICArchitectual 
StateArchitectual 
StatePentium Processor Extreme EditionSystem BusArchitectual State
Execution Engine
Local APIC Local APICExecution EngineArchitectual State
Bus InterfaceIntel Core Duo Processor
Intel Core 2 Duo Processor
Intel Pentium dual-core Processor
Second Level CacheArchitectual State

State
State
Bus Interface Bus InterfacePentium D Processor
OM19809Vol. 1 2-19INTEL® 64 AND IA-32 ARCHITECTURES
Intel Core i7 processors support Intel quad-core techno logy, Intel HyperThreading Technology, provides Intel 
QuickPath interconnect link to the chipset and have integr ated memory controller supporting three channels to 
DDR3 memory.Figure 2-7.  Intel® 64 Proc essors that Support Quad-Core 
Figure 2-8.  Intel®  Core™ i7 Processor System BusIntel Core 2 Extreme Quad-core Processor
Intel Core 2 Quad Processor
Intel Xeon Processor 3200 SeriesIntel Xeon Processor 5300 Series
Architectual State
Bus InterfaceSecond Level CacheArchitectual State
Bus InterfaceSecond Level Cache
OM19810
ChipsetIntel Core i7  Processor
QPILogical 
Proces
sor
L1 and L2
Execution Engine Execution EngineL1 and L2 L1 and L2
Execution Engine Execution EngineL1 and L2
QuickPath Interconnect (QPI) Interface, Integrated Memory ControllerThird Level Cache
OM19810bLogical 
Proces
sorLogical 
Proces
Proces
Proces
Proces
Proces
Proces
sor
DDR3IMC2-20 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
2.2.10 Intel® 64 Architecture
Intel 64 architecture increases the linear address space for software to 64 bits and supports physical address space 
up to 52 bits. The technology also introduces a new operating mode referre d to as IA-32e mode.
IA-32e mode operates in one of two sub-modes: (1) comp atibility mode enables a 64-bit operating system to run 
most legacy 32-bit software unmodified, (2) 64-bit mode  enables a 64-bit operating system to run applications 
written to access 64-bit address space. 
In the 64-bit mode, applications may access:
•64-bit flat linear addressing.
•8 additional general-purpose registers (GPRs).
•8 additional registers for streaming SIMD extens ions (Intel SSE, SSE2, and SSE3, and SSSE3).
•64-bit-wide GPRs and instruction pointers.
•Uniform byte-register addressing.
•Fast interrupt-prioritization mechanism.
•A new instruction-pointer relative-addressing mode.
An Intel 64 architecture processor supports existing IA-32 software because it is able to run all non-64-bit legacy 
modes supported by IA-32 architecture. Most existing IA-32 applications also run in compatibility mode.
2.2.11 Intel® Virtualization  Technology (Intel® VT)
Intel® Virtualization Technology for Intel 64 and IA-32 archit ectures provide extensions that support virtualization. 
The extensions are referred to as Virtual Machine Extensio ns (VMX). An Intel 64 or IA-32 platform with VMX can 
function as multiple virtual systems (or virtual machin es). Each virtual machine can run operating systems and 
applications in separate partitions. 
VMX also provides programming interface for a new layer of system software (called the Virtual Machine Monitor 
(VMM)) used to manage the operation of virtual machines . Information on VMX and on the programming of VMMs 
is in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3C .
Intel Core i7 processor provides the following enhancements to Intel Virtualization Technology:
•Virtual processor ID (VPID) to reduce the cost of VMM managing transitions.
•Extended page table (EPT) to reduce the number of transitions for VMM to manage memory virtualization.
•Reduced latency of VM transitions.
2.3 INTEL® 64 AND IA-32 PROCESSOR GENERATIONS
In the mid-1960s, Intel co-founder and Chairman Emeritus Gordon Moore had this observation: “... the number of 
transistors that would be incorporated on a silicon die wo uld double every 18 months for the next several years.” 
Over the past three and half decades, this prediction known as “Moore's Law” has continued to hold true.
The computing power and the complexity (or roughly, the num ber of transistors per processor) of Intel architecture 
processors has grown in close relation to Moore's law. By taking advantage of new process technology and new 
microarchitecture designs, each new generation of IA-3 2 processors has demonstrated frequency-scaling head-
room and new performance levels over the previous generation processors.Vol. 1 2-21INTEL® 64 AND IA-32 ARCHITECTURES
The key features of the Intel Pentium 4 processor, In tel Xeon processor, Intel Xeon processor MP, Pentium III 
processor, and Pentium III Xeon processor with advanced transfer cache are shown in Table 2-1. Older generation  
IA-32 processors, which do not employ on-die Level 2 cache, are shown in Table 2-2. 
Table 2-1.  Key Features of Most Recent IA-32 Processors 
Intel 
ProcessorDate 
Intro-
ducedMicroarchitecture Top-Bin Clock 
Fre-quency at 
Intro-
ductionTran-
sistorsRegister 
Sizes1
NOTES:
1. The register size and external data bus size are given in bits.System 
Bus Band-
widthMax. 
Extern. 
Addr. 
SpaceOn-Die 
Caches2
2. First level cache is denoted us ing the abbreviation L1, 2nd level cache is denoted as L2. The size
of L1 includes the first-level data cache an d the instruction cache where applicable, but 
does not include the trace cache.Intel Pentium 
MProcessor 
755
3
3. Intel processor numbers are not a measure of performance. Processor numbers differentiate 
features within each processor family, not across different processor families. 
See http://www.intel.com/products/processor_number  for details.2004 Intel Pentium M 
Processor2.00 GHz 140 M GP: 32 
FPU: 80 MMX: 64
XMM: 1283.2 GB/s 4 GB L1: 64 KB
L2: 2 MB
Intel Core Duo
Processor 
T2600
32006 Improved Intel 
Pentium M 
Processor Microarchitecture; 
Dual Core;
Intel Smart Cache, 
Advanced Thermal 
Manager2.16 GHz  152 M GP: 32 
FPU: 80 
MMX: 64XMM: 1285.3 GB/s 4 GB L1: 64 KB
L2: 2 MB (2 
MB Total)
Intel Atom
Processor Z5xx series2008 Intel Atom 
Microarchitecture; 
Intel Virtualization 
Technology.1.86 GHz - 
800 MHz 47 M GP: 32 
XMM: 128Up to 4.2 
GB/s4 GB L1: 56 KB
4
L2: 512 KB 
4. In Intel Atom Processor, the si ze of L1 instruction cache is 32 KB ytes, L1 data cache is 24 KBytes.
Table 2-2.  Key Features of Mo st Recent Intel® 64 Processors
Intel 
Intro-
ducedMicro-architec-
tureHighest 
Processor 
Base Fre-quency at 
Intro-
SizesSystem 
Bus/QPI 
Link SpeedMax. 
Extern. 
Addr. SpaceOn-Die 
Caches
64-bit Intel 
XeonProcessor 
with 800 MHz 
System Bus2004 Intel NetBurst 
Microarchitecture; Intel Hyper-
Threading 
Technology; Intel 64 Architecture3.60 GHz 125 M GP: 32, 64
XMM: 1286.4 GB/s 64 GB 12K µop 
Execution Trace Cache;
16 KB L1;
1 MB L2
Xeon
Processor MP 
with 8MB L32005 Intel NetBurst 
Intel Hyper-
Threading Technology; Intel 
64 Architecture 3.33 GHz 675 M GP: 32, 64
FPU: 80 
MMX: 64
XMM: 1285.3 GB/s
 11024 GB 
(1 TB)12K µop 
Execution 
Trace Cache;
16 KB L1;1 MB L2,
8 MB L32-22 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
Intel Pentium 
4
Processor Extreme 
Edition 
Supporting Hyper-
Threading 
Technology2005 Intel NetBurst 
Intel Hyper-Threading 
Technology; Intel 
64 Architecture 3.73 GHz 164 M GP: 32, 64
FPU: 80 
MMX: 64XMM: 1288.5 GB/s 64 GB 12K µop 
Execution 
Trace Cache;16 KB L1;
2 MB L2
Processor 
Extreme 
Edition 8402005 Intel NetBurst 
64 Architecture;
Dual-core 
23.20 GHz 230 M GP: 32, 64
FPU: 80 
MMX: 64
Execution 
16 KB L1;1 MB L2 (2 
MB Total)
Dual-Core Intel 
Xeon Processor 
70412005 Intel NetBurst 
Threading 
Technology; Intel 64 Architecture;
Dual-core 
33.00 GHz  321 M GP: 32, 64
16 KB L1;
2 MB L2 (4 MB Total)
4
Processor 6722005 Intel NetBurst 
Technology.3.80 GHz 164 M GP: 32, 64
FPU: 80 
MMX: 64XMM: 1286.4 GB/s 64 GB 12K µop 
Execution 
2 MB L2 
Processor 
Extreme Edition 9552006 Intel NetBurst 
Intel 64 Architecture; Dual 
Core;
Technology.3.46 GHz  376 M GP: 32, 64
FPU: 80 
Execution 
2 MB L2 
(4 MB Total)
Intel Core 2 
Extreme 
Processor 
X68002006 Intel Core 
Dual Core; 
Intel 64 
Architecture;
Technology.2.93 GHz  291 M GP: 32, 64 
FPU: 80 
MMX: 64
XMM: 1288.5 GB/s 64 GB L1: 64 KB
L2: 4 MB (4 
MB Total)Table 2-2.  Key Features of Most Re cent Intel® 64 Processors (Contd.)
Intel 
Intro-ducedMicro-architec-
Processor Base Fre-
quency at 
Intro-ductionTran-
Bus/QPI Link 
SpeedMax. 
Extern. Addr. 
CachesVol. 1 2-23INTEL® 64 AND IA-32 ARCHITECTURES
Intel Xeon
Processor 
51602006 Intel Core

FPU: 80 
Execution 
2 MB L2 
Processor 
Core;
FPU: 80 
Execution 
2 MB L2 
Extreme 
Processor 
Dual Core; 
Intel 64 
FPU: 80 
MMX: 64
L2: 4 MB (4 
Intel 
quency at 
SpeedMax. 
Intel Xeon
Processor 
51602006 Intel Core 
Dual Core; 
Intel 64 
Technology.3.00 GHz  291 M GP: 32, 64
FPU: 80 
MMX: 64XMM: 12810.6 GB/s 64 GB L1: 64 KB
L2: 4 MB (4 
MB Total)
Intel Xeon
Processor 
71402006 Intel NetBurst 
Dual Core; 
Intel 64 
Technology.3.40 GHz  1.3 B GP: 32, 64
FPU: 80 
MMX: 64
XMM: 12812.8 GB/s 64 GB L1: 64 KB
L2: 1 MB (2 
MB Total)
L3: 16 MB 
(16 MB 
Total)
Extreme 
Processor 
QX67002006 Intel Core 
Quad Core; 
Intel 64 
Technology.2.66 GHz 582 M GP: 32, 64 
FPU: 80 
MMX: 64
L2: 4 MB (4 
MB Total)
Quad-core 
Intel XeonProcessor 
53552006 Intel Core 
Microarchitecture; Quad Core; 
Intel 64 
Technology.2.66 GHz 582 M GP: 32, 64
XMM: 12810.6 GB/s 256 GB L1: 64 KB
L2: 4 MB (8 MB Total)
Duo Processor 
E68502007 Intel Core 
Dual Core; 
Intel 64 
Technology;
Intel Trusted 
Execution Technology3.00 GHz 291 M GP: 32, 64
FPU: 80 
L2: 4 MB (4 
MB Total)
Intel Xeon
Processor 
73502007 Intel Core 
Quad Core; 
Intel 64 
Technology.2.93 GHz  582 M GP: 32, 64
FPU: 80 
MMX: 64
XMM: 128
8.5 GB/s 1024 GB L1: 64 KB
L2: 4 MB (8 
Intel 
quency at 
SpeedMax. 
Caches2-24 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
Intel Xeon
Processor 
54722007 Enhanced Intel 
Core 
Intel 64 
Technology.3.00 GHz  820 M GP: 32, 64
FPU: 80 
MMX: 64XMM: 12812.8 GB/s 256 GB L1: 64 KB
L2: 6 MB (12 
MB Total)
Intel Atom
Processor2008 Intel Atom 
Intel 64 
Technology.2.0 - 1.60 
GHz47 M GP: 32, 64
FPU: 80 
MMX: 64
GB/sUp to 
64GBL1: 56 KB
4
L2: 512 KB 
Intel Xeon
Processor 
74602008 Enhanced Intel 
Core 
Six Cores; 
Intel 64 
Technology.2.67 GHz  1.9 B GP: 32, 64
FPU: 80 
MMX: 64
XMM: 1288.5 GB/s 1024 GB L1: 64 KB
L2: 3 MB (9 
MB Total)
L3: 16 MB
Intel Atom
Processor 3302008 Intel Atom 
Intel 64 
Dual core;
Technology.1.60 GHz 94 M GP: 32, 64
FPU: 80 
MMX: 64
GB/sUp to 
64GBL1: 56 KB5
L2: 512 KB 
(1 MB Total)
Intel Core i7-
965Processor 
Extreme 
Edition2008 Nehalem 
microarchitecture; Quadcore; 
HyperThreading 
Technology; Intel QPI; Intel 64 
Technology.3.20 GHz  731 M GP: 32, 64
XMM: 128QPI: 6.4 
GT/s; Memory: 
25 GB/s 64 GB L1: 64 KB
L2: 256 KB 
L3: 8 MBTable 2-2.  Key Features of Most Re cent Intel® 64 Processors (Contd.)
Intel 
quency at 
SpeedMax. 
CachesVol. 1 2-25INTEL® 64 AND IA-32 ARCHITECTURES
620M
Processor 2010 Intel Turbo Boost 
Technology, 
Westmere microarchitecture; 
Dual-core; 
HyperThreading Technology; Intel 
Technology., 
Integrated graphics2.66 GHz  383 M GP: 32, 64
FPU: 80 
MMX: 64XMM: 12864 GB L1: 64 KB
L2: 256 KB 
L3: 4 MB
Intel Xeon-
Processor 56802010 Intel Turbo Boost 
Technology, Westmere 
microarchitecture; 
Six core; HyperThreading 
Technology.3.33 GHz 1.1 B GP: 32, 64
GT/s; 32 GB/s1 TB L1: 64 KB
L2: 256 KB 
L3: 12 MB
Processor 
75602010 Intel Turbo Boost 
Nehalem microarchitecture; 
Eight core; 
Technology.2.26 GHz 2.3 B GP: 32, 64
FPU: 80 
MMX: 64XMM: 128QPI: 6.4 
GT/s; 
Memory: 76 GB/s 16 TB L1: 64 KB
L2: 256 KB 
L3: 24 MB
2600K
Processor 2011 Intel Turbo Boost 
Technology, Sandy 
Bridge 
microarchitecture; Four core; 
Technology., Processor graphics, 
Quicksync Video3.40 GHz  995 M GP: 32, 64
FPU: 80 
MMX: 64
XMM: 128
YMM: 256DMI: 5 
GT/s; 
Memory: 
21 GB/s64 GB L1: 64 KB
L2: 256 KB 
Intel 
quency at 
SpeedMax. 
Caches2-26 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
Processor E3-
12802011 Intel Turbo Boost 
Bridge microarchitecture; 
Four core; 
Technology.3.50 GHz GP: 32, 64
FPU: 80 
MMX: 64XMM: 128
GT/s; 
Memory: 21 GB/s1 TB L1: 64 KB
L2: 256 KB 
L3: 8 MB
Processor E7-
88702011 Intel Turbo Boost 
Ten core; 
Technology.2.40 GHz 2.2 B GP: 32, 64
FPU: 80 
GT/s; 
Memory: 102 GB/s 16 TB L1: 64 KB
L2: 256 KB 
L3: 30 MB
NOTES:
1. The 64-bit Intel Xeon Processor MP with an  8-MByte L3 supports a multi-processor plat form with a dual system bus; this creat es a 
platform bandwidth with 10.6 GBytes.
2. In Intel Pentium Processor Extreme Edition 840, the size of on-die cache is listed for each core. The total size of L2 in th e physical
package in 2 MBytes.
3. In Dual-Core Intel Xeon Processor 7041, the size of on-die cache is listed for each core. The total size of L2 in the physic al package in
4 MBytes.
4. In Intel Atom Processor, the si ze of L1 instruction ca che is 32 KBytes, L1 data cache is 24 KBytes.
5. In Intel Atom Processor, the si ze of L1 instruction ca che is 32 KBytes, L1 data cache is 24 KBytes.Table 2-2.  Key Features of Most Re cent Intel® 64 Processors (Contd.)
Intel 
quency at 
SpeedMax. 
CachesVol. 1 2-27INTEL® 64 AND IA-32 ARCHITECTURES
Table 2-3.  Key Features of Previo us Generations of IA-32 Processors
Intel 
Intro-ducedMax. Clock 
Frequency/Technology at 
IntroductionTran-
Sizes
1Ext. Data Bus Size2Max. Extern. Addr. 
SpaceCaches 
8086 1978 8 MHz 29 K 16 GP 16 1 MB None
Intel 286 1982 12.5 MHz 134 K 16 GP 16 16 MB Note 3
Intel386 DX 
Processor1985 20 MHz 275 K 32 GP 32 4 GB Note 3
Intel486 DX 
Processor1989 25 MHz 1.2 M 32 GP
80 FPU32 4 GB L1: 8 KB
Pentium Processor 1993 60 MHz 3.1 M 32 GP
80 FPU64 4 GB L1: 16 KB
Pentium Pro 
Processor1995 200 MHz 5.5 M 32 GP
80 FPU64 64 GB L1: 16 KB
L2: 256 KB or 
512 KB 
Pentium II Processor 1997 266 MHz 7 M 32 GP
80 FPU
64 MMX64 64 GB L1: 32 KB
512 KB
Pentium III Processor 1999 500 MHz 8.2 M 32 GP
80 FPU
64 MMX128 XMM64 64 GB L1: 32 KB
L2: 512 KB
Pentium III and 
Pentium III Xeon 
Processors1999 700 MHz 28 M 32 GP
80 FPU
64 MMX
128 XMM64 64 GB L1: 32 KB
L2: 256 KB
Pentium 4 Processor 2000 1.50 GHz, Intel 
NetBurst Microarchitecture42 M 32 GP
80 FPU64 MMX
128 XMM64 64 GB 12K µop 
Execution Trace Cache; 
L1: 8 KB
L2: 256 KB
Intel Xeon Processor 2001 1.70 GHz, Intel 
L1: 8 KB
L2: 512 KB
Intel Xeon Processor 2002 2.20 GHz, Intel 
NetBurst Microarchitecture, 
Technology55 M 32 GP
L1: 8 KB
L2: 512 KB
Pentium M Processor 2003 1.60 GHz, Intel 
NetBurst Microarchitecture77 M 32 GP
128 XMM64 4 GB L1: 64 KB
L2: 1 MB2-28 Vol. 1INTEL® 64 AND IA-32 ARCHITECTURES
NOTE:
1. The register size and external data bus size are given in bits . Note also that each 32-bit ge neral-purpose (GP) registers can  be 
addressed as an 8- or a 16-bit data  registers in all of the processors.
2. Internal data paths are 2 to 4 times wider than th e external data bus for each processor.
2.4 PLANNED REMOVAL OF INTEL® IN STRUCTION SET ARCHITECTURE AND 
FEATURES FROM UPCOMING PRODUCTS
This section lists Intel Instruction Set Architecture (ISA) and features that Intel plans to remove from select prod-
ucts starting from a specific year.
2.5 INTEL® INSTRUCTION SET ARCH ITECTURE AND FEATURES REMOVED
This section lists Intel ISA and features that Intel has already removed for select upcoming products. All sections

L1: 8 KB
L2: 512 KB
NOTE:
This section lists Intel ISA and features that Intel has already removed for select upcoming products. All sections 
relevant to the removed features will be identified as su ch and may be moved to an archived section in future 
Intel® 64 and IA-32 Architectures Software Developer's Manual releases.Intel Pentium 4
Processor 
Supporting Hyper-Threading 
Technology at 90 nm 
process2004 3.40 GHz, Intel 
NetBurst 
Microarchitecture, HyperThreading 
Technology125 M 32 GP
80 FPU
64 MMX128 XMM64 64 GB 12K µop 
Execution 
Trace Cache; L1: 16 KB
L2: 1 MB
Table 2-4.  Planned Intel® IS A and Features Removal List 
Intel ISA/Feature Year of Removal
xAPIC mode 2025 onwards
Table 2-5.  Intel® ISA and Features Removal List 
Intel® Memory Protection Extensions (Intel® MPX) 2019 onwards
MSR_TEST_CTRL, bit 31 (MSR address 33H) 2019 onwards
Hardware Lock Elision (HLE) 2019 onwardsTable 2-3.  Key Features of Previous Generations of  IA-32 Processors (Contd.)Vol. 1 3-1CHAPTER 3
This chapter describes the basic execution environment of an Intel 64 or IA-32 processor as seen by assembly-
language programmers. It describes how the processor executes instructions and how it stores and manipulates data. The execution environment described here includes  memory (the address space), general-purpose data 
registers, segment registers, the flag register, and the instruction pointer register.
3.1 MODES OF OPERATION
The IA-32 architecture supports three basic operating modes: protected mode, real-address mode, and system 
management mode. The operating mode determines which instructions and architectural features are accessible:
•Protected mode  — This mode is the native state of the proce ssor. Among the capabilities of protected mode 
is the ability to directly execute “real-address mode” 8 086 software in a protected, multi-tasking environment. 
This feature is called virtual-8086 mode , although it is not actually a processor mode. Virtual-8086 mode is 
actually a protected mode attribute that can be enabled for any task. 
•Real-address mode  — This mode implements the programming en vironment of the Intel 8086 processor with 
extensions (such as the ability to switch to protected or  system management mode). The processor is placed in 
real-address mode following power-up or a reset.
•System management mode (SMM)  — This mode provides an operating system or executive with a 
transparent mechanism for implementing platform-speci fic functions such as power management and system 
security. The processor enters SMM when the external SMM interrupt pin (SMI#) is activated or an SMI is 
received from the advanced programm able interrupt controller (APIC). 
In SMM, the processor switches to a separate address space while saving the basic context of the currently 
running program or task. SMM-specific code may then be  executed transparently. Upon returning from SMM, 
the processor is placed back into its state prior to th e system management interrupt. SMM was introduced with 
the Intel386™ SL and Intel486™ SL processors and became a standard IA-32 feature with the Pentium 
processor family. 
3.1.1 Intel® 64 Architecture
Intel 64 architecture adds IA-32e mode. IA-32e mode has two sub-modes.These are:
•Compatibility mode (sub -mode of IA-32e mode) — Compatibility mode permits most legacy 16-bit and 
32-bit applications to run without re-c ompilation under a 64-bit operating system. For brevity, the compatibility 
sub-mode is referred to as compatib ility mode in IA-32 architecture. The execution environment of compati-
bility mode is the same as described in Section 3.2. Co mpatibility mode also supports all of the privilege levels 
that are supported in 64-bit and protected modes. Lega cy applications that run in Virtual 8086 mode or use 
hardware task management will not work in this mode. 
Compatibility mode is enabled by the operating system (OS)  on a code segment basis. This means that a single 
64-bit OS can support 64-bit applications running in 64- bit mode and support legacy 32-bit applications (not 
recompiled for 64-bits) running in compatibility mode.
Compatibility mode is similar to 32-bit protected mode. Applications access only the first 4 GByte of linear-
address space. Compatibility mode uses 16-bit and 32-bit address and operand sizes. Like protected mode, this 
mode allows applications to access physical memory greater than 4 GByte using PAE (Physical Address Exten-
sions). 
•64-bit mode  (sub-mode of IA-32e mode) — This mode enables a 64-bit operating system to run applica-
tions written to access 64-bit linear address space. For brevity, the 64-bit sub-mode is referred to as 64-bit mode in IA-32 architecture.3-2 Vol. 1BASIC EXECUTION ENVIRONMENT
64-bit mode extends the number of general purpose re gisters and SIMD extension registers from 8 to 16. 
General purpose registers are widened to 64 bits. The mode also introduces a new opcode prefix (REX) to 
access the register extensions. See Section 3.2.1 for a detailed description.
64-bit mode is enabled by the operating system on a code -segment basis. Its default address size is 64 bits and 
its default operand size is 32 bits. The default operand size can be overridden on an instruction-by-instruction 
basis using a REX opcode prefix in conjuncti on with an operand size override prefix. 
REX prefixes allow a 64-bit operand to be specified when  operating in 64-bit mode. By using this mechanism, 
many existing instructions have been promoted to allow the use of 64-bit registers and 64-bit addresses.
3.2 OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT
Any program or task running on an IA-32 processor is gi ven a set of resources for executing instructions and for 
storing code, data, and state information. These resource s (described briefly in the following paragraphs and 
shown in Figure 3-1) make up the basic execution environment for an IA-32 processor. 
An Intel 64 processor supports the basic execution enviro nment of an IA-32 processor, and a similar environment 
under IA-32e mode that can execute 64-bit programs (64-bit sub-mode) and 32-bit programs (compatibility sub-mode). 
The basic execution environment is used jointly by the ap plication programs and the operating system or executive 
running on the processor.
•Address space  — Any task or program running on an IA-32 processor can address a linear address space of 
up to 4 GBytes (232 bytes) and a physical address space of up to 64 GBytes (236 bytes). See Section 3.3.6, 
“Extended Physical Addressing in Protected Mode,” fo r more information about addressing an address space 
greater than 4 GBytes.
•Basic program execution registers  — The eight general-purpose registers, the six segment registers, the 
EFLAGS register, and the EIP (instruction pointer) register comprise a basic execution environment in which to 
execute a set of general-purpose instructions. These instructions perform basic integer arithmetic on byte, word, and doubleword integers, handle program flow co ntrol, operate on bit and byte strings, and address 
memory. See Section 3.4, “Basic Program Execution Re gisters,” for more information about these registers.
•x87 FPU registers  — The eight x87 FPU data registers, the x87 FPU control register, the status register, the 
x87 FPU instruction pointer register, the x87 FPU operand (data) pointer register, the x87 FPU tag register, and 
the x87 FPU opcode register provide an execution envi ronment for operating on single precision, double 
precision, and double extended precision floating-point  values, word integers, doubleword integers, quadword 
integers, and binary coded decimal (B CD) values. See Section 8.1, “x87 FPU Execution Environment,” for more 
information about these registers.
•MMX registers  — The eight MMX registers support execution of single-instruction, multiple-data (SIMD) 
operations on 64-bit packed byte, word, and doublewo rd integers. See Section 9.2, “The MMX Technology 
Programming Environment,” for more information about these registers.
•XMM registers  — The eight XMM data registers and the MXCSR register support execution of SIMD operations 
on 128-bit packed single precision and double precision floating-point values and on 128-bit packed byte, word, 
doubleword, and quadword integers. See Section 10.2 , “Intel® SSE Programming Environment,” for more 
•YMM registers  — The YMM data registers support execution of 256-bit SIMD operations on 256-bit packed 
single precision and double precision floating-point values and on 256-bit packed byte, word, doubleword, and 
quadword integers. 
•Bounds registers  — Each of the BND0-BND3 register stores the lower and upper bounds  (64 bits each) 
associated with the pointer to a memory buffer. They support execution of the Intel MPX instructions. 
•BNDCFGU and BNDSTATUS — BNDCFGU configures user mode MPX operations on bounds checking. 
BNDSTATUS provides additional information on the #BR caused by an MPX operation.Vol. 1 3-3BASIC EXECUTION ENVIRONMENT

Figure 3-1.  IA-32 Basic Execution Environment for Non-64-Bit Modes02^32 -1
Eight 32-bit
32-bits32-bitsGeneral-Purpose Registers
Segment Registers
EFLAGS Register
EIP (Instruction Pointer Register)Address Space*
*The address space can beSix 16-bit
RegistersRegisters
Eight 80-bit
RegistersFloating-Point
Data Registers
Eight 64-bit
Registers MMX Registersflat or segmented. Using
XMM RegistersEight 128-bit
Registers16 bits Control Register
16 bits Status Register
48 bits FPU Instruction Pointer Register
48 bits FPU Data (Operand) Pointer RegisterFPU Registers
MMX Registers
XMM Registers
32-bits MXCSR RegisterOpcode Register (11-bits)Basic Program Execution Registers
16 bits Tag Registerthe physical address
extension mechanism, a
physical address space of
2^36 - 1 can be addressed.
YMM RegistersEight 256-bit
RegistersYMM RegistersFour 128-bit RegistersBounds Registers
BNDCFGU BNDSTATUS3-4 Vol. 1BASIC EXECUTION ENVIRONMENT
•Stack  — To support procedure or subroutine calls and the passing of parameters between procedures or 
subroutines, a stack and stack management resources ar e included in the execution environment. The stack 
(not shown in Figure 3-1) is located in memory. See Se ction 6.2, “Stacks,” for more information about stack 
In addition to the resources provided in the basic exec ution environment, the IA-32 architecture provides the 
following resources as part of its system-level architec ture. They provide extensive support for operating-system 
and system-development software. Except for the I/O ports,  the system resources are described in detail in the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D.
•I/O ports  — The IA-32 architecture supports a transfers of data to and from input/output (I/O) ports. See 
Chapter 19, “Input/Output,” in this volume.
•Control registers  — The five control registers (CR0 through CR4) determine the operating mode of the 
processor and the characteristics of the currently executing task. See Chapter 2, “System Architecture Overview,” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
•Memory management registers  — The GDTR, IDTR, task register, and LDTR specify the locations of data 
structures used in protected mode memory management . See Chapter 2, “System Architecture Overview,” in 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
•Debug registers  — The debug registers (DR0 through DR7) control and allow monitoring of the processor’s 
debugging operations. See in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
•Memory type range registers (MTRRs)  — The MTRRs are used to assign memory types to regions of 
memory. See the sections on MTRRs in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volumes 3A, 3B, 3C & 3D.
•Model-specific registers (MSRs)  — The processor provides a variety of model-specific registers that are 
used to control and report on processor performance. Virtually all MSRs handle sy stem related functions and 
are not accessible to an application program. One except ion to this rule is the time-stamp counter. The MSRs 
are described in Chapter 2, “Model-Spe cific Registers (MSRs),” of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 4.
•Machine check registers  — The machine check registers consist of a set of control, status, and error-
reporting MSRs that are used to detect and report on  hardware (machine) errors. See Chapter 16, “Machine-
Check Architecture,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
•Performance monitoring counters  — The performance monitoring counters allow processor performance 
events to be monitored. See Chapter 20, “Performance Monitoring,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3B.
The remainder of this chapter describes the organization  of memory and the address space, the basic program 
execution registers, and addressing modes. Refer to the fo llowing chapters in this volume for descriptions of the 
other program execution resources shown in Figure 3-1:
•X87 FPU registers  — See Chapter 8, “Programming with the x87 FPU.”
•MMX Registers — See Chapter 9, “Programming with Intel® MMX™ Technology.”
•XMM registers  — See Chapter 10, “Programming  with Intel® Streaming SIMD Extensions (Intel® SSE),” 
Chapter 11, “Programming with Intel® Streaming SI MD Extensions 2 (Intel® SSE2),” and Chapter 12, 
“Programming with Intel® SSE3, SSSE 3, Intel® SSE4, and Intel® AES-NI.”
•YMM registers  — See Chapter 14, “Programming with Intel® AVX, FMA, and Intel® AVX2.”
•BND registers, BNDCFGU, BNDSTATUS — See Chapter 13, “Managing Stat e Using the XSAVE Feature Set,” 
and Appendix E, “Intel® Memory Protection Extensions.”
•Stack implementation and procedure calls  — See Chapter 6, “Procedure Ca lls, Interrupts, and Exceptions.”Vol. 1 3-5BASIC EXECUTION ENVIRONMENT
3.2.1 64-Bit Mode Execution Environment
The execution environment for 64-bit mode is similar to that described in Section 3.2. The following paragraphs 
describe the differences that apply. 
•Address space  — A task or program running in 64-bit mode on an IA-32 processor can address linear address 
space of up to 264 bytes (subject to the canonical addressing requirement described in Section 3.3.7.1) and 
physical address space of up to 252 bytes. Software can query CPUID for the physical address size supported 
by a processor.
•Basic program execution registers  — The number of general-purpose registers (GPRs) available is 16. 
GPRs are 64-bits wide and they support operations on byte, word, doubleword, and quadword integers. 
Accessing byte registers is done uniformly to the lowest 8 bits. The instruction pointer register becomes 64 bits. 
The EFLAGS register is extended to 64 bits wide, and is  referred to as the RFLAGS register. The upper 32 bits 
of RFLAGS is reserved. The lower 32 bits of RFLAGS is the same as EFLAGS. See Figure 3-2.
•XMM registers  — There are 16 XMM data registers for SIMD operations. See Section 10.2, “Intel® SSE 
•YMM registers  — There are 16 YMM data registers for SIMD operations. See Chapter 14, “Programming with 
Intel® AVX, FMA, and Intel® AVX2,” for more information about these registers.
•BND registers, BNDCFGU, BNDSTATUS — See Chapter 13, “Managing State Using the XSAVE Feature Set,” 
and Appendix E, “Intel® Memo ry Protection Extensions.”
•Stack  — The stack pointer size is 64 bits. Stack size is not controlled by a bit in the SS descriptor (as it is in 
non-64-bit modes) nor can the pointer size be overridden by an instruction prefix.
•Control registers  — Control registers expand to 64 bits. A new control register (the task priority register: CR8 
or TPR) has been added. See Chapter 2, “Intel® 64 and IA-32 Architectures‚” in this volume.
•Debug registers  — Debug registers expand to 64 bits. See Chapter 18, “Debug, Branch Profile, TSC, and 
Intel® Resource Director Technology (Intel® RDT) Features,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3B.3-6 Vol. 1BASIC EXECUTION ENVIRONMENT
•Descriptor table registers  — The global descriptor table register (GDTR) and interrupt descriptor table 
register (IDTR) expand to 10 bytes so that they can hold a full 64-bit base address. The local descriptor table register (LDTR) and the task register (TR) also expand to hold a full 64-bit base address.
3.3 MEMORY ORGANIZATION
The memory that the processor addresses on its bus is called physical memory . Physical memory is organized as 
a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address . The physical 
address space  ranges from zero to a maximum of 236 − 1 (64 GBytes) if the processor does not support Intel 
64 architecture. Intel 64 architecture introduces a set of changes in physical and linear address space; these 
are described in Section 3.3.3, Section 3.3.4, and Section 3.3.7.Figure 3-2.  64-Bit Mode Execution Environment02^64 -1Sixteen 64-bit
64-bits64-bitsGeneral-Purpose Registers
RFLAGS Register
RIP (Instruction Pointer Register)Address Space
Six 16-bit
Registers MMX Registers
XMM RegistersSixteen 128-bit
64 bits FPU Instruction Pointer Register
64 bits FPU Data (Operand) Pointer RegisterFPU Registers
16 bits Tag Register
Four 128-bit RegistersBounds Registers
BNDCFGU BNDSTATUS
YMM RegistersSixteen 256-bit
RegistersYMM RegistersVol. 1 3-7BASIC EXECUTION ENVIRONMENT
Virtually any operating system or executive designed to work with an IA-32 or Intel 64 processor will use the

Six 16-bit
Virtually any operating system or executive designed to work with an IA-32 or Intel 64 processor will use the 
processor’s memory management facilities to access memory. These facilities provide features such as segmenta-tion and paging, which allow memory to  be managed efficiently and reliably. Memory management is described in 
detail in Chapter 3, “Protected-Mode Memory Management,” in the Intel
® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3A. The following paragraphs describe the basic methods of addressing memory when 
memory management is used.
3.3.1 IA-32 Memory Models
When employing the processor’s memory management fac ilities, programs do not directly address physical 
memory. Instead, they access memory using one of three memory models: flat, segmented, or real address mode:
•Flat memory model  — Memory appears to a program as a single, continuous address space (Figure 3-3). This 
space is called a linear address space . Code, data, and stacks are all contained in this address space. Linear 
address space is byte addressable, with ad dresses running contiguously from 0 to 232 - 1 (if not in 64-bit 
mode). An address for any byte in linear address space is called a linear address .
•Segmented memory model  — Memory appears to a program as a group of independent address spaces 
called segments. Code, data, and stacks are typically contained in separate segments. To address a byte in a 
segment, a program issues a logical address. This cons ists of a segment selector and an offset (logical 
addresses are often referred to as far pointers). The segment selector iden tifies the segment to be accessed 
and the offset identifies a byte in the address space of  the segment. Programs running on an IA-32 processor 
can address up to 16,383 segments of different sizes and types, and each segment can be as large as 232 
bytes.
Internally, all the segments that are defined for a system are mapped into the processor’s linear address space. 
To access a memory location, the processor thus translat es each logical address into a linear address. This 
translation is transparent to the application program.
The primary reason for using segmented memory is to in crease the reliability of programs and systems. For 
example, placing a program’s stack in a separate segmen t prevents the stack from growing into the code or 
data space and overwriting instructions or data, respectively.
•Real-address mode memory model  — This is the memory model for the Intel 8086 processor. It is 
supported to provide compatibility with existing programs  written to run on the Intel 8086 processor. The real-
address mode uses a specific implementation of segmen ted memory in which the linear address space for the 
program and the operating system/executive consists of an array of segments of up to 64 KBytes in size each. 
The maximum size of the linear address space in real-address mode is 220 bytes. 
See also: Chapter 21, “8086 Emulation,” in the Intel® 64 and IA-32 Architectu res Software Developer’s 
Manual, Volume 3B.3-8 Vol. 1BASIC EXECUTION ENVIRONMENT
3.3.2 Paging and Virtual Memory
With the flat or the segmented memory model, linear address space is mapped into the processor’s physical 
address space either directly or thro ugh paging. When using direct mapping (paging disabled), each linear address 
has a one-to-one correspondence with a physical address. Linear addresses are sent out on the processor’s address 
lines without translation. 
When using the IA-32 architecture’s paging mechanism (paging enabled), linear address space is divided into 
pages which are mapped to virtual memory. The pages of vi rtual memory are then mapped as needed into physical 
memory. When an operating system or executive uses paging, the paging mechanism is transparent to an applica-
tion program. All that the applic ation sees is linear address space.
In addition, IA-32 architecture’s paging me chanism includes extensions that support:
•Physical Address Extensions (PAE) to address physical address space greater than 4 GBytes.
•Page Size Extensions (PSE) to map linear addr ess to physical address in 4-MBytes pages.
See also: Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3A.
3.3.3 Memory Organization in 64-Bit Mode
Intel 64 architecture supports physical address space greate r than 64 GBytes; the actual physical address size of 
IA-32 processors is implementation specific. In 64-bit mo de, there is architectural support for 64-bit linear address 
space. However, processors supporting Intel 64 arch itecture may implement less than 64-bits (see Section 
3.3.7.1). The linear address space is mapped into the processor physical address space through the PAE paging 
mechanism.Figure 3-3.  Three Memory Management ModelsLinear AddressFlat Model
Linear
Address
Space*
Offset
Segment SelectorSegmented Model
Real-Address Mode Model
Linear Address
LogicalOffset (effective address)
Space Divided
Into Equal
Sized Segments
AddressLogical
AddressLinear
Address
Space*Segments
* The linear address space
can be paged when using the 
flat or segmented model.Vol. 1 3-9BASIC EXECUTION ENVIRONMENT
3.3.4 Modes of Operation vs. Memory Model
When writing code for an IA-32 or Intel 64 processor,  a programmer needs to know the operating mode the 
processor is going to be in when executing the code an d the memory model being used. The relationship between 
operating modes and memory models is as follows:
•Protected mode — When in protected mode, the processor can use any of the memory models described in 
this section. (The real-addressing mode memory model is  ordinarily used only when the processor is in the 
virtual-8086 mode.) The memory model used depends on the design of the operating system or executive. 
When multitasking is implemented, individual tasks can use different memory models.
•Real-address mode  — When in real-address mode, the proce ssor only supports the real-address mode 
•System management mode  — When in SMM, the processor switches to a separate address space, called the 
system management RAM (SMRAM). The memory model used to address bytes in this address space is similar 
to the real-address mode model. See Chapter 32, “System Management Mode,” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 3C, for more information on the memory model used in 
SMM.
•Compatibility mode — Software that needs to run in compatibility mode should observe the same memory 
model as those targeted to run in 32-bit protected mode. The effect of segmentation is the same as it is in 32-
bit protected mode semantics.
•64-bit mode — Segmentation is generally (but not completely) disabled, creating a flat 64-bit linear-address 
space. Specifically, the processor treats the segment base  of CS, DS, ES, and SS as zero in 64-bit mode (this 
makes a linear address equal an effective address). Segm ented and real address modes are not available in 64-
bit mode.
3.3.5 32-Bit and 16-Bit Ad dress and Operand Sizes
IA-32 processors in protected mode can be configured fo r 32-bit or 16-bit address and operand sizes. With 32-bit 
address and operand sizes, the maximum line ar address or segment offset is FFFFFFFFH (232-1); operand sizes are 
typically 8 bits or 32 bits. With 16-bit address and operan d sizes, the maximum linear address or segment offset is 
FFFFH (216-1); operand sizes are typically 8 bits or 16 bits. 
When using 32-bit addressing, a logical address (or far poin ter) consists of a 16-bit segment selector and a 32-bit 
offset; when using 16-bit addressing, an address consis ts of a 16-bit segment selector and a 16-bit offset. 
Instruction prefixes allow temporary overrides of the defa ult address and/or operand sizes from within a program.
When operating in protected mode, the segment descripto r for the currently executing code segment defines the 
default address and operand size. A segment descriptor is a system data structure not normally visible to applica-
tion code. Assembler directives allow the default addressi ng and operand size to be chosen for a program. The 
assembler and other tools then set up the segmen t descriptor for the code segment appropriately.
When operating in real-address mode, the default addressing  and operand size is 16 bits. An address-size override 
can be used in real-address mode to enable 32-bit ad dressing. However, the maximum allowable 32-bit linear 
address is still 000FFFFFH (220-1).
3.3.6 Extended Physical Addressing in Protected Mode
Beginning with P6 family processors, the IA-32 archit ecture supports addressing of up to 64 GBytes (236 bytes) of 
physical memory. A program or task could not address locations in this address space directly. Instead, it 
addresses individual linear address spaces of up to 4 G Bytes that mapped to 64-GBy te physical address space 
through a virtual memory management mechanism. Using this mechanism, an operating system can enable a 
program to switch 4-GByte linear address spac es within 64-GByte physical address space.

The use of extended physical addressing requires the pr ocessor to operate in protected mode and the operating 
system to provide a virtual memory management system. See “36-Bit Physical Addressing Using the PAE Paging 
Mechanism” in Chapter 3, “Protected-M ode Memory Management,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3A.3-10 Vol. 1BASIC EXECUTION ENVIRONMENT
3.3.7 Address Calculations in 64-Bit Mode
In most cases, 64-bit mode uses flat address space for code, data, and stacks. In 64-bit mode (if there is no 
address-size override), the size of effective address calculations is 64 bits. An effective-address calculation uses a 
64-bit base and index registers and sign-extend displacements to 64 bits.
In the flat address space of 64-bit mode, linear addr esses are equal to effective addresses because the base 
address is zero. In the event that FS or GS segments are used with a non-zero base, this rule does not hold. In 64-bit mode, the effective address components are added and the effective address is truncated (See for example the 
instruction LEA) before adding the full 64-bit segment base . The base is never truncated, regardless of addressing 
mode in 64-bit mode.
The instruction pointer is extended to 64 bits to support 64-bit code offsets. The 64-bit instruction pointer is called 
the RIP. Table 3-1 shows the relationship between RIP, EIP, and IP.
Table 3-1.  Instruction Pointer Sizes
Generally, displacements and immediates in 64-bit mode are not extended to 64 bits. They are still limited to 32 
bits and sign-extended during effective-address calculations . In 64-bit mode, however, support is provided for 64-
bit displacement and immediate forms of the MOV instruction. 
All 16-bit and 32-bit address calculations are zero-exten ded in IA-32e mode to form 64-bit addresses. Address 
calculations are first truncated to the effective address size of the current mode (64-bit mode or compatibility mode), as overridden by any address-size prefix. The result  is then zero-extended to the full 64-bit address width. 
Because of this, 16-bit and 32-bit applications running in compatibility mode can access only the low 4 GBytes of 
the 64-bit mode effective addresses. Likewise, a 32-bit ad dress generated in 64-bit mode can access only the low 
4 GBytes of the 64-bit mode effective addresses.
3.3.7.1  Canonical Addressing
In 64-bit mode, an address is considered to be in canonica l form if address bits 63 through to the most-significant 
implemented bit by the microarchitecture are set to either all ones or all zeros.
Intel 64 architecture defines a 64-bit linear address. Implementations can support less. The first implementation of 
IA-32 processors with Intel 64 architecture supports a 48-b it linear address. This means a canonical address must 
have bits 63 through 48 set to zeros or ones (depending on whether bit 47 is a zero or one).
Although implementations may not use all 64 bits of the li near address, they should check bits 63 through the 
most-significant implemented bit to see if the address is in canonical form. If a linear-memory reference is not in 
canonical form, the implementation should generate an exception. In most cases, a general-protection exception 
(#GP) is generated. However, in the case of explicit or implied stack references, a stack fault (#SS) is generated. 
Instructions that have implied stack references, by defa ult, use the SS segment register. These include PUSH/POP-
related instructions and instructions us ing RSP/RBP as base registers. In these cases, the canonical fault is #SS. 
If an instruction uses base registers RSP/RBP and uses a segment override prefix to specify a non-SS segment, a 
canonical fault generates a #GP (instead of an #SS). In 64-bit mode, only FS and GS segment-overrides are appli-
cable in this situation. Other segment override prefixes (C S, DS, ES, and SS) are ignored. Note that this also means 
that an SS segment-override applied to a “non-stack” regist er reference is ignored. Such a sequence still produces 
a #GP for a canonical fault (and not an #SS).
3.4 BASIC PROGRAM EXECUTION REGISTERS
IA-32 architecture provides 16 basic program execution registers for use in general system and application programing (see Figure 3-4). These registers can be grouped as follows:Bits 63:32 Bits 31:16 Bits 15:0
16-bit instruction pointer Not Modified IP
32-bit instruction pointer Zero Extension EIP64-bit instruction pointer RIPVol. 1 3-11BASIC EXECUTION ENVIRONMENT
•General-purpose registers . These eight registers are available for storing operands and pointers.
•Segment registers . These registers hold up to six segment selectors.
•EFLAGS (program status  and control) register . The EFLAGS register report on the status of the program 
being executed and allows limited (application-program level) control of the processor. 
•EIP (instruction pointer) register . The EIP register contains a 32-bit pointer to the next instruction to be 
executed. 
3.4.1 General-Purpose Registers
The 32-bit general-purpose registers EAX, EBX, ECX, EDX,  ESI, EDI, EBP, and ESP are provided for holding the 
following items:
•Operands for logical and arithmetic operations.
•Operands for address calculations.
•Memory pointers.
Although all of these registers are available for general st orage of operands, results, and pointers, caution should 
be used when referencing the ESP register. The ESP regist er holds the stack pointer and as a general rule should 
not be used for another purpose. 
Many instructions assign specific registers to hold operands. For example, string instructions use the contents of 
the ECX, ESI, and EDI registers as operands. When usin g a segmented memory model, some instructions assume 
that pointers in certain registers are relative to specific segments. For instance, some instructions assume that a 
pointer in the EBX register points to a memory location in the DS segment. 
Figure 3-4.  General System and Application Progra mming Registers0 31
EAX
EBX
ECX
EDX
ESI
EDI
EBP
ESP
CS
DS
SS
ES
FS
GS0 15
0 31
EFLAGS
EIP31 0General-Purpose Registers
Program Status and Control Register
Instruction Pointer3-12 Vol. 1BASIC EXECUTION ENVIRONMENT
The special uses of general-purpose registers by instru ctions are described in Chapter 5, “Instruction Set 
Summary,” in this volume. See also: Chapter 3, Ch apter 4, Chapter 5, and Chapter 6 of the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D. The following is a summary of special uses:
•EAX — Accumulator for operands and results data.
•EBX — Pointer to data in the DS segment.
•ECX — Counter for string and loop operations.
•EDX — I/O pointer.
•ESI — Pointer to data in the segment pointed to by the DS register; source pointer for string operations.
•EDI — Pointer to data (or destination) in the segment po inted to by the ES register; destination pointer for 
string operations.
•ESP — Stack pointer (in the SS segment).
•EBP — Pointer to data on the stack (in the SS segment).
As shown in Figure 3-5, the lower 16 bits of the general-pu rpose registers map directly to the register set found in 
the 8086 and Intel 286 processors and can be referenced wi th the names AX, BX, CX, DX, BP, SI, DI, and SP. Each 
of the lower two bytes of the EAX, EB X, ECX, and EDX registers can be refe renced by the names AH, BH, CH, and 
DH (high bytes) and AL, BL, CL, and DL (low bytes).
3.4.1.1  General-Purpose Registers in 64-Bit Mode
In 64-bit mode, there are 16 general purpose registers and the default operand size is 32 bits. However, general-
purpose registers are able to work with either 32-bit or 64- bit operands. If a 32-bit operand size is specified: EAX, 
EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D - R15D are availabl e. If a 64-bit operand size is specified: RAX, RBX, RCX, 
RDX, RDI, RSI, RBP, RSP, R8-R15 are available. R8D-R1 5D/R8-R15 represent eight new general-purpose registers. 
All of these registers can be accessed at the byte, word, dw ord, and qword level. REX prefixes are used to generate 
64-bit operand sizes or to reference registers R8-R15.
Registers only available in 64-bit mode (R8-R15 and X MM8-XMM15) are preserved across transitions from 64-bit 
mode into compatibility mode then back into 64-bit mo de. However, values of R8-R15 and XMM8-XMM15 are unde-
fined after transitions from 64-bit mode through compatibi lity mode to legacy or real mode and then back through 
compatibility mode to 64-bit mode.Figure 3-5.  Alternate General-Purpose Register Names0 7 15 31 16 8
AH AL
BH BL
CH CL
DH DL
BP
SI
DI
SP16-bit
AX
DXCXBX32-bit
EAX
EBX
ECXEDX
EBP
ESI
ESPGeneral-Purpose Registers
EDIVol. 1 3-13BASIC EXECUTION ENVIRONMENT
In 64-bit mode, there are limitations on accessing byte registers. An instruction cannot reference legacy high-
bytes (for example: AH, BH, CH, DH) an d one of the new byte registers at the same time (for example: the low

AH AL
BH BL
CH CL
DH DL
BP
SI
DI
SP16-bit
AX
EAX
EBX
ECXEDX
EBP
ESI
bytes (for example: AH, BH, CH, DH) an d one of the new byte registers at the same time (for example: the low 
byte of the RAX register). However, instructions may refe rence legacy low-bytes (for example: AL, BL, CL, or DL) 
and new byte registers at the same time (for example: th e low byte of the R8 register, or RBP). The architecture 
enforces this limitation by changing high-byte references (AH, BH, CH, DH) to low byte references (BPL, SPL, DIL, 
SIL: the low 8 bits for RBP, RSP, RDI, an d RSI) for instructions using a REX prefix.
When in 64-bit mode, operand size determines the num ber of valid bits in the destination general-purpose 
register: 
•64-bit operands generate a 64-bit result in the destination general-purpose register.
•32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination general-purpose 
register.
•8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56 bits or 48 bits (respectively) of the 
destination general-purpose register are not modified by the operation. If the result of an 8-bit or 16-bit 
operation is intended for 64-bit address calculation, ex plicitly sign-extend the register to the full 64-bits. 
Because the upper 32 bits of 64-bit general-purpose regist ers are undefined in 32-bit modes, the upper 32 bits of 
any general-purpose register are not preserved when swit ching from 64-bit mode to a 32-bit mode (to protected 
mode or compatibility mode). Software must not depend on  these bits to maintain a value after a 64-bit to 32-bit 
mode switch.
3.4.2 Segment Registers
The segment registers (CS, DS, SS, ES, FS, and GS) hold 16- bit segment selectors. A segment selector is a special 
pointer that identifies a segment in memory. To access a particular segment in memory, the segment selector for 
that segment must be present in the appropriate segment register.
When writing application code, programmers generally create segment selectors with assembler directives and 
symbols. The assembler and other tools then create the actual segment selector values associated with these 
directives and symbols. If writing system code, programm ers may need to create segment selectors directly. See 
Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A.
How segment registers are used depends on the type of memory management model that the operating system or 
executive is using. When using the flat (unsegmented) me mory model, segment registers are loaded with segment 
selectors that point to overlapping segments, each of which begins at address 0 of the linear address space (see 
Figure 3-6). These overlapping segments then comprise the linear address space for the program. Typically, two 
overlapping segments are defined: one for code and anothe r for data and stacks. The CS segment register points 
to the code segment and all the other segment registers point to the data and stack segment.
When using the segmented memory model, each segment re gister is ordinarily loaded with a different segment 
selector so that each segment register points to a different segment within the linear address space (see 
Figure 3-7). At any time, a program can thus access up to  six segments in the linear address space. To access a 
segment not pointed to by one of the segment registers, a program must firs t load the segment selector for the 
segment to be accessed into a segment register.Table 3-2.  Addressable General Purpose Registers
Register Type Without REX With REX
Byte Registers AL, BL, CL, DL, AH, BH, CH, DH AL, BL, CL, DL, DIL, SIL, BPL, SPL, R8B - R15BWord Registers AX, BX, CX, DX, DI, SI, BP, SP AX, BX, CX, DX, DI, SI, BP, SP, R8W - R15WDoubleword Registers EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D - R15D
Quadword Registers N.A. RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8 - R153-14 Vol. 1BASIC EXECUTION ENVIRONMENT
Each of the segment registers is associated with one of th ree types of storage: code, data, or stack. For example, 
the CS register contains the segment selector for the code segment , where the instructions being executed are 
stored. The processor fetches instructions from the code segment, using a logical address that consists of the 
segment selector in the CS register and the contents of th e EIP register. The EIP register contains the offset within 
the code segment of the next instruction to be executed. Th e CS register cannot be load ed explicitly by an applica-
tion program. Instead, it is loaded implicitly by instruct ions or internal processor operations that change program 
control (such as procedure calls, interrupt handling, or task switching).
The DS, ES, FS, and GS registers point to four data segments . The availability of four data segments permits effi-
cient and secure access to different types of data structures. For example, four separate data segments might be 
created: one for the data structures of the current modu le, another for the data exported from a higher-level 
module, a third for a dynamically created data structure, and a fourth for data shared with another program. To 
access additional data segments, the application program mu st load segment selectors for these segments into the 
DS, ES, FS, and GS registers, as needed.
The SS register contains the segment selector for the stack segment , where the procedure stack is stored for the 
program, task, or handler currently being executed. All st ack operations use the SS register to find the stack Figure 3-6.  Use of Segment Re gisters for Flat Memory Model
Figure 3-7.  Use of Segment Regi sters in Segmented Memory ModelSegment Registers
CS
SSDS
ES
FSGSLinear Address
Space for Program
The segment selector in
each segment register
points to an overlapping Overlapping
Segments
of up to
4 GBytes
segment in the linear
address space.Beginning at
Address 0
CS
DS
SS
ES
FS
GSCode
Segment
Data
Segment
Stack
Segment
Data
Segment
Data
SegmentData
SegmentAll segments
are mappedto the samelinear-addressspaceVol. 1 3-15BASIC EXECUTION ENVIRONMENT
segment. Unlike the CS register, the SS register can be lo aded explicitly, which permits application programs to set 
up multiple stacks an d switch among them.
See Section 3.3, “Memory Organization,” for an overview  of how the segment registers are used in real-address 
mode.
The four segment registers CS, DS, SS, and ES are the sa me as the segment registers found in the Intel 8086 and 
Intel 286 processors and the FS and GS registers were in troduced into the IA-32 Architecture with the Intel386™ 
family of processors.
3.4.2.1  Segment Registers in 64-Bit Mode
In 64-bit mode: CS, DS, ES, SS are treated as if each segm ent base is 0, regardless of the value of the associated 
segment descriptor base. This creates a flat address spac e for code, data, and stack. FS and GS are exceptions. 
Both segment registers may be used as additional base re gisters in linear address calculations (in the addressing 
of local data and certain operating system data structures). 
Even though segmentation is generally disabled, segm ent register loads may cause the processor to perform 
segment access assists. During these activities, enabled proc essors will still perform most of the legacy checks on 
loaded values (even if the checks are not applicable in  64-bit mode). Such checks are needed because a segment 
register loaded in 64-bit mode may be used by  an application running in compatibility mode. 
Limit checks for CS, DS, ES, SS, FS, and GS are disabled in 64-bit mode.
3.4.3 EFLAGS Register
The 32-bit EFLAGS register contains a group of status flag s, a control flag, and a group of system flags. Figure 3-8 
defines the flags within this register. Following initializati on of the processor (either by asserting the RESET pin or 
the INIT pin), the state of the EFLAGS register is 00000002H . Bits 1, 3, 5, 15, and 22 through 31 of this register 
are reserved. Software should not use or depend on the states of any of these bits.
Some of the flags in the EFLAGS register can be modified directly, using special-purpose instructions (described in 
the following sections). There are no instructions that allo w the whole register to be examined or modified directly. 
The following instructions can be used to move groups of flags to and from the procedure stack or the EAX register: 
LAHF, SAHF, PUSHF, PUSHFD, POPF, and POPFD. After the cont ents of the EFLAGS register have been transferred to 
the procedure stack or EAX register, the flags can be exam ined and modified using the processor’s bit manipulation 
instructions (BT, BTS, BTR, and BTC).
When suspending a task (using the processor’s multitaski ng facilities), the processor automatically saves the state 
of the EFLAGS register in the task state segment (TSS) fo r the task being suspended. When binding itself to a new 
task, the processor loads the EFLAGS register with data from the new task’s TSS.

When a call is made to an interrupt or exception handle r procedure, the processor automatically saves the state of 
the EFLAGS registers on the procedure stack. When an in terrupt or exception is handled with a task switch, the 
state of the EFLAGS register is saved in the TSS for the task being suspended.3-16 Vol. 1BASIC EXECUTION ENVIRONMENT
As the IA-32 Architecture has evolved, flags have been added to the EFLAGS register, but the function and place-
ment of existing flags have remained the same from one family of the IA-32 processors to the next. As a result, 
code that accesses or modifies these flags for one family of IA-32 processors works as expected when run on later 
families of processors.
3.4.3.1  Status Flags
The status flags (bits 0, 2, 4, 6, 7, and 11) of the EFLAGS  register indicate the results of arithmetic instructions, 
such as the ADD, SUB, MUL, and DIV instructions. The status flag functions are:
CF (bit 0) Carry flag  — Set if an arithmetic operation genera tes a carry or a borrow out of the most-
significant bit of the result; cleared otherwise. This flag indicates an overflow condition for 
unsigned-integer arithmetic. It is also used in multiple-precision arithmetic.
PF (bit 2) Parity flag  — Set if the least-significant byte of the result contains an even number of 1 bits; 
cleared otherwise.
AF (bit 4) Auxiliary Carry flag  — Set if an arithmetic operation generates a carry or a borrow out of bit 
3 of the result; cleared otherwise. This flag is  used in binary-coded decimal (BCD) arithmetic.
ZF (bit 6) Zero flag  — Set if the result is zero; cleared otherwise.
SF (bit 7) Sign flag  — Set equal to the most-significant bit of the result, which is the sign bit of a signed 
integer. (0 indicates a positive value and 1 indicates a negative value.)
OF (bit 11) Overflow flag  — Set if the integer result is too large a positive number or too small a negative 
number (excluding the sign-bit) to fit in the de stination operand; cleared otherwise. This flag 
indicates an overflow condition for signed-integer (two’s complement) arithmetic.
Of these status flags, only the CF flag can be modified directly, using the STC, CLC, and CMC instructions. Also the 
bit instructions (BT, BTS, BTR, and BTC)  copy a specified bit into the CF flag.Figure 3-8.  EFLAGS Register31 2930 28 2726 25 24232221 20 19 181716
0R
FI
DA
CV
M
X  Virtual-8086 Mode (VM)
X Resume Flag (RF)X Nested Task (NT)X  I/O Privilege Level (IOPL)
S Overflow Flag (OF)
C Direction Flag (DF)X  Interrupt Enable Flag (IF)X  Alignment Check / Access Control (AC)X ID Flag (ID)
X Virtual Interrupt Pending (VIP)15 1314 12 1110 9 876543 210
0C
FA
FP
F1D
FI
FT
FS
FZ
FN
T0 0 00 0000000V
I
PV
I
FO
FI
O
P
L
X  Virtual Interrupt Flag (VIF)
X  Trap Flag (TF)
S  Sign Flag (SF)S  Zero Flag (ZF)S  Auxiliary Carry Flag (AF)S  Parity Flag (PF)
S  Carry Flag (CF)
S  Indicates a Status Flag
C  Indicates a Control FlagX  Indicates a System Flag
Reserved bit positions. DO NOT USE.
Always set to values previously read.Vol. 1 3-17BASIC EXECUTION ENVIRONMENT
The status flags allow a single arithmetic operation to produce results for three different data types: unsigned inte-
gers, signed integers, and BCD integers. If the result of an  arithmetic operation is treated as an unsigned integer, 
the CF flag indicates an out-of-range condition (carry or a borrow); if treated as a signed integer (two’s comple-
ment number), the OF flag indicates a carry or borrow; and if treated as a BCD digit, the AF flag indicates a carry 
or borrow. The SF flag indicates the sign of a signed inte ger. The ZF flag indicates either a signed- or an unsigned-
integer zero.
When performing multiple-precision arithmetic on integers , the CF flag is used in conjunction with the add with 
carry (ADC) and subtract with borrow (SBB) instructions to propagate a carry or borrow from one computation to 
the next. 
The condition instructions J cc (jump on condition code cc), SET cc (byte set on condition code cc), LOOP cc, and 
CMOV cc (conditional move) use one or more of the status flags as condition codes and test them for branch, set-
byte, or end-loop conditions.
3.4.3.2  DF Flag
The direction flag (DF, located in bit 10 of the EFLAGS register) controls string instructions (MOVS, CMPS, SCAS, 
LODS, and STOS). Setting the DF flag causes the string instructions to auto-decrement (to process strings from 
high addresses to low addresses). Clearing the DF flag causes the string instructions to auto-increment 
(process strings from low addresses to high addresses).
The STD and CLD instructions set an d clear the DF flag, respectively.
3.4.3.3  System Flags and IOPL Field
The system flags and IOPL field in the EFLAGS regist er control operating-system or executive operations. They 
should not be modified by application programs . The functions of the system flags are as follows:
TF (bit 8) Trap flag  — Set to enable single-step mode for debu gging; clear to disable single-step mode.
IF (bit 9) Interrupt enable flag  — Controls the response of the processor to maskable interrupt 
requests. Set to respond to maskable interru pts; cleared to inhibit maskable interrupts.
IOPL (bits 12 and 13)
I/O privilege level field  — Indicates the I/O privilege level of the currently running program 
or task. The current privilege le vel (CPL) of the currently running program or task must be less 
than or equal to the I/O privilege level to a ccess the I/O address space. The POPF and IRET 
instructions can modify this field only when operating at a CPL of 0.
NT (bit 14) Nested task flag  — Controls the chaining of interrupted and called tasks. Set when the 
current task is linked to the previously execut ed task; cleared when the current task is not 
linked to another task.
RF (bit 16) Resume flag  — Controls the processor’s response to debug exceptions.
VM (bit 17) Virtual-8086 mode flag  — Set to enable virtual-8086 mode; clear to return to protected 
mode without virtual-8086 mode semantics.
AC (bit 18) Alignment check (or access control) flag  — If the AM bit is set in the CR0 register, align-
ment checking of user-mode data accesses is  enabled if and only if this flag is 1.
If the SMAP bit is set in the CR4 register, explicit supervisor-mode data accesses to user-mode 
pages are allowed if and only if this bit is 1.  See Section 4.6, “Access Rights,” in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 3A.
VIF (bit 19) Virtual interrupt flag  — Virtual image of the IF flag. Used in conjunction with the VIP flag. 
(To use this flag and the VIP flag the virtual mode extensions are enabled by setting the VME flag in control register CR4.)
VIP (bit 20) Virtual interrupt pending flag  — Set to indicate that an interrupt is pending; clear when no 
interrupt is pending. (Software sets and clears th is flag; the processor only reads it.) Used in 
conjunction with the VIF flag.
ID (bit 21) Identification flag  — The ability of a program to set or clear this flag indicates support for 
the CPUID instruction.3-18 Vol. 1BASIC EXECUTION ENVIRONMENT
For a detailed description of these flags: see Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 3A. 
3.4.3.4  RFLAGS Register in 64-Bit Mode
In 64-bit mode, EFLAGS is extended to 64 bits and called RFLAGS. The upper 32 bits of RFLAGS register is 
reserved. The lower 32 bits of RFLAGS is the same as EFLAGS.
3.5 INSTRUCTION POINTER
The instruction pointer (EIP) register contains the offset in  the current code segment for the next instruction to be 
executed. It is advanced from one instruction boundary to the next in straight-line code or it is moved ahead or 
backwards by a number of instructions when executing JMP, J cc, CALL, RET, and IRET instructions. 
The EIP register cannot be accessed directly by software; it is controlled implicitly by control-transfer instructions 
(such as JMP, J cc, CALL, and RET), interrupts, and exceptions. The only way to read the EIP register is to execute a 
CALL instruction and then read the value of the return  instruction pointer from the procedure stack. The EIP 
register can be loaded indirectly by modifying the value of a return instruction pointer on the procedure stack and 
executing a return instruction (RET or IRET). Se e Section 6.2.4.2, “Return Instruction Pointer.”
All IA-32 processors prefetch instructions. Because of inst ruction prefetching, an instruction address read from the 
bus during an instruction load does not match the value in  the EIP register. Even though different processor gener-
ations use different prefetchin g mechanisms, the function of the EIP register to direct program flow remains fully 
compatible with all software written to run on IA-32 processors.
3.5.1 Instruction Pointer in 64-Bit Mode

In 64-bit mode, the RIP register becomes the instruction pointer. This register holds the 64-bit offset of the next instruction to be executed. 64-bit mode also supports a te chnique called RIP-relative addressing. Using this tech-
nique, the effective address is determined by adding  a displacement to the RIP of the next instruction.
3.6 OPERAND-SIZE AND A DDRESS-SIZE ATTRIBUTES
When the processor is executing in protected mode, ever y code segment has a default operand-size attribute and 
address-size attribute. These attributes are selected with the D (default size) flag in the segment descriptor for the 
code segment (see Chapter 3, “Protected-M ode Memory Management,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3A). When the D flag is set, the 32-bit operand-size and address-size attri-
butes are selected; when the flag is clear, the 16-bit size  attributes are selected. When the processor is executing 
in real-address mode, virtual-8086 mode, or SMM, the default operand-size and address-size attributes are always 16 bits.
The operand-size attribute selects the size of operands. Wh en the 16-bit operand-size attribute is in force, oper-
ands can generally be either 8 bits or 16 bits, and when th e 32-bit operand-size attribute is in force, operands can 
generally be 8 bits or 32 bits.
The address-size attribute selects the sizes of addresses used to address memory: 16 bits or 32 bits. When the 16-
bit address-size attribute is in force, segment offsets and displacements are 16 bits. This restriction limits the size 
of a segment to 64 KBytes. When the 32-bit address-size attribute is in force, segment offsets and displacements 
are 32 bits, allowing up to 4 GBytes to be addressed.
The default operand-size attribute and/or address-size attr ibute can be overridden for a particular instruction by 
adding an operand-size and/or address- size prefix to an instruction. See Ch apter 2, “Instruction Format,” in the 
Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. The effect of this prefix applies only to 
the targeted instruction.
Table 3-4 shows effective operand size and address size (w hen executing in protected mode or compatibility mode) 
depending on the settings of the D flag and th e operand-size and address-size prefixes.Vol. 1 3-19BASIC EXECUTION ENVIRONMENT
3.6.1 Operand Size and Address Size in 64-Bit Mode
In 64-bit mode, the default address size is 64 bits and the default operand size is 32 bits. Defaults can be over-
ridden using prefixes. Address-size and operand-size prefixes allow mixi ng of 32/64-bit data and 32/64-bit 
addresses on an instruction-by-instruction basis. Table 3- 4 shows valid combinations of the 66H instruction prefix 
and the REX.W prefix that may be us ed to specify operand-size overrides in 64-bit mode. Note that 16-bit 
addresses are not supported in 64-bit mode.
REX prefixes consist of 4-bit fields that form 16 different values. The W-bit field in the REX prefixes is referred to as 
REX.W. If the REX.W field is properly set, the prefix specif ies an operand size override to  64 bits. Note that software 
can still use the operand-size 66H prefix to toggle to a 16-bit operand size. However, setting REX.W takes prece-
dence over the operand-size pref ix (66H) when both are used.
In the case of SSE/SSE2/SSE3/SSSE3 SIMD instructions : the 66H, F2H, and F3H prefixes are mandatory for 
opcode extensions. In such a case, there is no interact ion between a valid REX.W prefix and a 66H opcode exten-
sion prefix.
See Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A.
3.7 OPERAND ADDRESSING
IA-32 machine-instructions act on zero or more operands . Some operands are specifie d explicitly and others are 
implicit. The data for a source operand can be located in:
•The instruction itself (an immediate operand).
•A register.
•A memory location.
•An I/O port.Table 3-3.  Effective Operand- and Address-Size Attributes
D  F l a g  i n  C o d e  S e g m e n t  D e s c r i p t o r 00001111  
Operand-Size Prefix 66H N N Y Y N N Y Y A d d r e s s - S i z e  P r e f i x  6 7 H NYNYNYNY  Effective Operand Size 16 16 32 32 32 32 16 16 Effective Address Size 16 32 16 32 32 16 32 16NOTES:
Y: Yes - this instruction prefix is present.
N: No - this instruction prefix is not present.
Table 3-4.  Effective Operand- and A ddress-Size Attributes in 64-Bit Mode
L Flag in Code Segment Descriptor
111 1  111 1  
R E X . W  P r e f i x  000 0  111 1  
Operand-Size Prefix 66H N N Y Y N N Y Y 
Address-Size Prefix 67H N Y N Y N Y N Y Effective Operand Size 32 32 16 16 64 64 64 64
Effective Address Size 64 32 64 32 64 32 64 32
NOTES:
N: No - this instruction prefix is not present.3-20 Vol. 1BASIC EXECUTION ENVIRONMENT
When an instruction returns data to a destination operand, it can be returned to:
•An I/O port.
3.7.1 Immediate Operands
Some instructions use data encoded in the instruction itself as a source operand. These operands are called imme-
diate  operands (or simply immediates). For example, the fo llowing ADD instruction adds an immediate value of 14 
to the contents of the EAX register:
ADD EAX, 14
All arithmetic instructions (except the DIV and IDIV inst ructions) allow the source operand to be an immediate 
value. The maximum value allowed for an immediate operand varies among instructions, but can never be greater 
than the maximum value of an unsigned doubleword integer (232).
3.7.2 Register Operands
Source and destination operands can be any of the following registers, depending on the instruction being 
executed:
•32-bit general-purpose registers (EAX, EBX,  ECX, EDX, ESI, EDI, ESP, or EBP).
•16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, or BP).
•8-bit general-purpose registers (AH, BH, CH, DH, AL, BL, CL, or DL).
•Segment registers (CS, DS, SS, ES, FS, and GS).
•EFLAGS register.
•X87 FPU registers (ST0 through ST7, status word, contro l word, tag word, data operand pointer, and instruction 
pointer).
•MMX registers (MM0 through MM7).
•XMM registers (XMM0 through XMM7) and the MXCSR register.
•Control registers (CR0, CR2, CR3, and CR4) and system  table pointer registers (GDTR, LDTR, IDTR, and task 
register).
•Debug registers (DR0, DR1, DR2, DR3, DR6, and DR7).
•MSR registers.
Some instructions (such as the DIV and MUL instructions) use quadword operands contained in a pair of 32-bit 
registers. Register pairs are represented with a colon sepa rating them. For example, in the register pair EDX:EAX, 
EDX contains the high order bits and EAX contai ns the low order bits of a quadword operand. 
Several instructions (such as the PUSHFD and POPFD instructions) are provided to load and store the contents of 
the EFLAGS register or to set or clear individual flags in this register. Other instructions (such as the J cc instruc-
tions) use the state of the status flags in the EFLAGS re gister as condition codes for branching or other decision 
making operations.
The processor contains a selection of system registers th at are used to control memory management, interrupt and 
exception handling, task management, processor management, and debugging activities. Some of these system 
registers are accessible by an application program, the op erating system, or the executive through a set of system 
instructions. When accessing a system register with a sy stem instruction, the register is generally an implied 
operand of the instruction.Vol. 1 3-21BASIC EXECUTION ENVIRONMENT
3.7.2.1  Register Operands in 64-Bit Mode
Register operands in 64-bit mode can be any of the following:
•64-bit general-purpose registers (RAX, RBX, RC X, RDX, RSI, RDI, RSP, RBP, or R8-R15).
•32-bit general-purpose registers (EAX, EBX, EC X, EDX, ESI, EDI, ESP, EBP, or R8D-R15D).
•16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, BP, or R8W-R15W).
•8-bit general-purpose registers: AL, BL, CL, DL, SIL, DIL, SPL, BPL, and R8B-R15B are available using REX 
prefixes; AL, BL, CL, DL, AH, BH, CH, DH are available without using REX prefixes.
•RFLAGS register.
•X87 FPU registers (ST0 through ST7, status word, contro l word, tag word, data operan d pointer, and instruction 
pointer).
•XMM registers (XMM0 through XMM15) and the MXCSR register.
•Control registers (CR0, CR2, CR3, CR4, and CR8) and system table pointer registers (GDTR, LDTR, IDTR, and 
task register).
•RDX:RAX register pair representing a 128-bit operand.
3.7.3 Memory Operands
Source and destination operands in memory are referenced  by means of a segment selector and an offset (see 
Figure 3-9). Segment selectors specify the segment containi ng the operand. Offsets specify the linear or effective 
address of the operand. Offsets can be 32 bits (represented by the notation m16:32) or 16 bits (represented by the

pointer).
address of the operand. Offsets can be 32 bits (represented by the notation m16:32) or 16 bits (represented by the 
notation m16:16).
3.7.3.1  Memory Operands in 64-Bit Mode
In 64-bit mode, a memory operand can be referenced by a segment selector and an offset. The offset can be 16 
bits, 32 bits or 64 bits (see Figure 3-10).
3.7.4 Specifying a Segment Selector
The segment selector can be specified either implicitly or explicitly. The most common method of specifying a 
segment selector is to load it in a segment register and then allow the processor to select the register implicitly, 
depending on the type of operation being performed. Th e processor automatically chooses a segment according to 
the rules given in Table 3-5. Figure 3-9.  Memory Operand Address
Figure 3-10.  Memory Operand Address in 64-Bit ModeOffset (or Linear Address)0 15
Segment310
Selector
Offset (or Linear Address)0 15
Segment630
Selector3-22 Vol. 1BASIC EXECUTION ENVIRONMENT
When storing data in memory or loading data from memo ry, the DS segment default can be overridden to allow 
other segments to be accessed. Within an assembler, th e segment override is generally handled with a colon “:” 
operator. For example, the following MOV instruction moves a value from register EAX into the segment pointed to 
by the ES register. The offset into the segment is contained in the EBX register:
MOV ES:[EBX], EAX
At the machine level, a segment override is specified with a segment-override prefix, which is a byte placed at the 
beginning of an instruction. The following de fault segment selections cannot be overridden:
•Instruction fetches must be made from the code segment.
•Destination strings in string instructions must be stored in the data segment pointed to by the ES register.
•Push and pop operations must always reference the SS segment.
Some instructions require a segment selector to be specifie d explicitly. In these cases, the 16-bit segment selector 
can be located in a memory location or in a 16-bit regi ster. For example, the following MOV instruction moves a 
segment selector located in register BX into segment register DS:
MOV DS, BX
Segment selectors can also be specified explicitly as part of a 48-bit far pointer in memory. Here, the first double-
word in memory contains the offset and the next word contains the segment selector.
3.7.4.1  Segmentation in 64-Bit Mode
In IA-32e mode, the effects of segmentation depend on wh ether the processor is running in compatibility mode or 
64-bit mode. In compatibility mode, segmentation functions ju st as it does in legacy IA-32 mode, using the 16-bit 
or 32-bit protected mode semantics described above.
In 64-bit mode, segmentation is generally (but not co mpletely) disabled, creating a flat 64-bit linear-address 
space. The processor treats the segment base of CS, DS, ES, SS as zero, creating a linear address that is equal to 
the effective address. The exceptions are the FS and GS segments, whose segment registers (which hold the 
segment base) can be used as additional base registers in some linear address calculations.
3.7.5 Specifying an Offset
The offset part of a memory address can be sp ecified directly as a static value (called a displacement ) or through 
an address computation made up of one or more of the following components:
•Displacement  — An 8-, 16-, or 32-bit value.
•Base  — The value in a general-purpose register.
•Index  — The value in a general-purpose register.
•Scale factor — A value of 2, 4, or 8 that is multiplied by the index value.Table 3-5.  Default Segment Selection Rules
Reference Type Register Used Segment Used Default Selection Rule
Instructions CS Code Segment All instruction fetches.
Stack SS Stack Segment All stack pushes and pops.
Any memory reference which uses the ESP or EBP register as a base 
register.
Local Data DS Data Segment All data references, except when relative to stack or string destination.
Destination Strings ES Data Segment 
pointed to with the 
ES registerDestination of string instructions.Vol. 1 3-23BASIC EXECUTION ENVIRONMENT
The offset which results from adding these components is called an effective address . Each of these components 
can have either a positive or negative (2s complement) va lue, with the exception of the scaling factor. Figure 3-11 
shows all the possible ways that these components can be co mbined to create an effective address in the selected 
segment.
The uses of general-purpose registers as base or in dex components are restricted in the following manner:
•The ESP register cannot be used as an index register.
•When the ESP or EBP register is used as the base, the SS segment is the default segment. In all other cases, 
the DS segment is the default segment.
The base, index, and displacement components can be used  in any combination, and any of these components can 
be NULL. A scale factor may be used only when an index al so is used. Each possible combination is useful for data 
structures commonly used by programmers in high-level languages and assembly language. 
The following addressing modes suggest uses fo r common combinations of address components.
•Displacement  ⎯ A displacement alone represents a direct (unc omputed) offset to the operand. Because the 
displacement is encoded in the instruction, this form of  an address is sometimes called an absolute or static 
address. It is commonly used to access a statically allocated scalar operand.
•Base ⎯ A base alone represents an indirect offset to th e operand. Since the value in the base register can 
change, it can be used for dynamic storage of variables and data structures.
•Base + Displacement  ⎯ A base register and a displacement can be used together for two distinct purposes:
— As an index into an array when the element size is  not 2, 4, or 8 bytes—The displacement component 
encodes the static offset to the beginning of the array. The base register holds the results of a calculation 
to determine the offset to a specific element within the array.
— To access a field of a record: the base register hold s the address of the beginning of the record, while the 
displacement is a static offset to the field.
An important special case of this combination is acce ss to parameters in a procedure activation record. A 
procedure activation record is the stack frame created when a procedure is entered. Here, the EBP register is the best choice for the base register, because it automatically selects the stack segment. This is a compact 
encoding for this common function.
•(Index ∗ Scale) + Displacement ⎯ This address mode offers an efficient way to index into a static array 
when the element size is 2, 4, or 8 bytes. The disp lacement locates the beginning of the array, the index 
register holds the subscript of the desired array element, and the processor automatically converts the 
subscript into an index by applying the scaling factor.
•Base + Index + Displacement  ⎯ Using two registers together supports either a two-dimensional array (the 
displacement holds the address of the be ginning of the array) or one of seve ral instances of an array of records 
(the displacement is an offset to a field within the record).
•Base + (Index ∗ Scale) + Displacement ⎯ Using all the addressing compon ents together allows efficient 
indexing of a two-dimensional array when the elemen ts of the array are 2, 4, or 8 bytes in size.Figure 3-11.  Offset (or E ffective Address) ComputationOffset = Base + (Index * Scale) + DisplacementBase
EAX
EBX
ECXEDXESPEBP
ESIEDIEAX
EBXECXEDX
EBP
ESIEDI1 None
2
4
88-bit
16-bit
32-bitIndex Scale Displacement
*++3-24 Vol. 1BASIC EXECUTION ENVIRONMENT
3.7.5.1  Specifying an Offset in 64-Bit Mode
The offset part of a memory address in 64-bit mode can be specified directly as a static value or through an address 
computation made up of one or more of the following components:
•Displacement — An 8-bit, 16-bit, or 32-bit value.
•Base — The value in a 64-bit general-purpose register.
•Index — The value in a 64-bit general-purpose register.
•Scale factor —  A value of 2, 4, or 8 that is multiplied by the index value.
The base and index value can be specified in one of sixteen  available general-purpose registers in most cases. See 
Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 2A.
The following unique combination of address components is also available.
•RIP + Displacement ⎯ In 64-bit mode, RIP-relative addressing uses a signed 32-bit displacement to 
calculate the effective address of the next instruction by sign-extend the 32-bit value and add to the 64-bit 
value in RIP.
3.7.6 Assembler and Compiler Addressing Modes
At the machine-code level, the selected combination of di splacement, base register, index register, and scale factor 
is encoded in an instruction. All assemblers permit a pr ogrammer to use any of the allowable combinations of these 
addressing components to address operands. High-level la nguage compilers will select an appropriate combination 
of these components based on the language construct a programmer defines.

3.7.7 I/O Port Addressing
The processor supports an I/O address space that contains  up to 65,536 8-bit I/O ports. Ports that are 16-bit and 
32-bit may also be defined in the I/O address space. An  I/O port can be addressed with either an immediate 
operand or a value in the DX register. See Chapter 19,  “Input/Output,” for more information about I/O port 
addressing.Vol. 1 4-1CHAPTER 4
DATA TYPES
This chapter introduces data types defined for the Intel 64 and IA-32 architectures. A section at the end of this 
chapter describes the real-number and floating-point conc epts used in x87 FPU and Intel SSE, SSE2, SSE3, SSSE3, 
SSE4, and AVX extensions.
4.1 FUNDAMENTAL DATA TYPES
The fundamental data types are bytes,  words, doublewords, quadwords, an d double quadwords (see Figure 4-1). 
A byte is eight bits, a word is 2 bytes (16 bits), a doublewo rd is 4 bytes (32 bits), a quadword is 8 bytes (64 bits), 
and a double quadword is 16 bytes (128 bits). A subset of  the IA-32 architecture instructions operates on these 
fundamental data types without any additional operand typing.
The quadword data type was introduced into the IA-32 arch itecture in the Intel486 proc essor; the double quadword 
data type was introduced in the Pentium III processor with the Intel SSE extensions.
Figure 4-2 shows the byte order of each of the fundamenta l data types when referenced as operands in memory. 
The low byte (bits 0 through 7) of each data type occupies  the lowest address in memory and that address is also 
the address of the operand.Figure 4-1.  Fundamental Data Types0
63
Double 0
Word
310
Doubleword15
0Byte7
78
Low Word High Word
Low Doubleword High Doubleword1516
3132N+1
N+2
N+4Low
ByteHigh
ByteN
Low Quadword High QuadwordQuadwordN
NN
N
N+80Quadword
127 63 644-2 Vol. 1DATA TYPES
4.1.1 Alignment of Words, Doublewords,  Quadwords, and Double Quadwords
Words, doublewords, and quadwords do not need to be aligned in memory on natural boundaries. The natural 
boundaries for words, doublewords, and quadwords are ev en-numbered addresses, addresses evenly divisible by 
four, and addresses evenly divisible by eight, respectively . However, to improve the performance of programs, data 
structures (especially stacks) should be aligned on natural boundaries whenever possible. The reason for this is 
that the processor requires two memory accesses to make  an unaligned memory access; aligned accesses require 
only one memory access. A word or doubleword operand that crosses a 4-byte boundary or a quadword operand 
that crosses an 8-byte boundary is considered unaligned  and requires two separate memory bus cycles for access.
Some instructions that operate on double quadwords require memory operands to be aligned on a natural 
boundary. These instructions generate a general-protection exception (#GP) if an unalign ed operand is specified. A 
natural boundary for a double quadword is any address even ly divisible by 16. Other instructions that operate on 
double quadwords permit unaligned access (without genera ting a general-protection exception). However, addi-
tional memory bus cycles are required to access unaligned data from memory.
4.2 NUMERIC DATA TYPES
Although bytes, words, and doubleword s are fundamental data types, some instructions support additional inter-
pretations of these data types to allow operations to be performed on numeric data types (signed and unsigned 
integers, and floating-point numbers). Single precision (32-bit) floating-point and double precision (64-bit) 
floating-point data types are supported across all genera tions of Intel SSE extensions and Intel AVX extensions. 
The half precision (16-bit) floating-point data type wa s supported only with F16C extensions (VCVTPH2PS and 
VCVTPS2PH) beginning with th e third generation of Intel® Core™ processors based on Ivy Bridge microarchitec-
ture. Starting with the 4th generation Intel® Xeon® Scalable Processor Family, an Intel® AVX-512 instruction set 
architecture (ISA) for FP16 was added, supporting a wide range of general-purpose numeric operations for 16-bit half precision floating-point values (binary16 in IEEE Standard 754-2019 for Floating-Point Arithmetic, aka half 
precision or FP16), which complements the existing 32-bit  and 64-bit floating-point instructions already available 
in the Intel Xeon processor-based products. This ISA also  provides complex-valued native hardware support for 
half precision floating-point. See Figure 4-3. Figure 4-2.  Bytes, Words, Doublewords, Quadwords, and Double  Quadwords in MemoryEH
DH 7AH
CH FEH
BH 06H
AH 36H
9H 1FH
8H A4H
7H 23H
6H 0BH
5H
4H
3H 74H
2H CBH
1H 31H
0HQuadword at Address 6H
Contains Doubleword at Address AHContains 7AFE0636HWord at Address BH
Contains FE06H
Byte at Address 9H
Contains 1FH
Word at Address 6H
Contains 230BH
Word at Address 1H
Contains CB31HWord at Address 2H
Contains 74CBH
Double quadword at Address 0H45H
67H
12HContains12H
7AFE06361FA4230BH
4E127AFE06361FA4230B456774CB31124EH FHVol. 1 4-3DATA TYPES
4.2.1 Integers
The Intel 64 and IA-32 architectures define two types of in tegers: unsigned and signed. Unsigned integers are ordi-
nary binary values ranging from 0 to the maximum positi ve number that can be encoded in the selected operand 
size. Signed integers are two’s complement binary values th at can be used to represent both positive and negative 
integer values.
Some integer instructions (such as the ADD, SUB, PADDB,  and PSUBB instructions) operate on either unsigned or 
signed integer operands. Other integer instructions (such as IMUL, MUL, IDIV, DIV, FIADD, and FISUB) operate on 
only one integer type.
The following sections describe the encodings and ranges of the two types of integers.
4.2.1.1  Unsigned Integers
Unsigned integers are unsigned bina ry numbers contained in a byte, wo rd, doubleword, and quadword. Their 
values range from 0 to 255 for an unsigned byte integer, from 0 to 65,535 for an unsigned word integer, from 0 Figure 4-3.  Numeric Data Types15
SDM10024Doubleword 
Unsigned IntegerByte Unsigned Integer
Word Unsigned 
Integer
Quadword 
Unsigned Integer0
0
0
07
15
31
63
Byte Signed 
Integer
Word Signed 
Integer
Quadword Signed 
Integer0
0
0
07 6
31
63Doubleword Signed 
IntegerSign
Sign
SignSign
623014
Half Precision 
Floating Point
Single Precision 
Floating Point0
0
52 51Double Precision 
Floating PointSign
Sign
Sign
Double Extended 
Precision Floating Point0
0Integer Bit Sign
64 63 6263 6223 22 31 3015 14 9
79 784-4 Vol. 1DATA TYPES
to 232 – 1 for an unsigned doubleword integer, and from 0 to 264 – 1 for an unsigned quadword integer. Unsigned 
integers are sometimes referred to as ordinals .
4.2.1.2  Signed Integers
Signed integers are signed binary numbers held in a byte , word, doubleword, or quadword. All operations on signed 
integers assume a two's complement representation. The sign  bit is located in bit 7 in a byte integer, bit 15 in a 
word integer, bit 31 in a doubleword integer, and bit 63 in  a quadword integer (see the signed integer encodings in 
Table 4-1).
The sign bit is set for negative integers and cleared for positive integers and zero. Integer values range from –128 
to +127 for a byte integer, from –32,768 to +32,767 for a word integer, from –231 to +231 – 1 for a doubleword 
integer, and from –263 to +263 – 1 for a quadword integer.
When storing integer values in memory, word integers are stored in 2 consecutive bytes; doubleword integers are 
stored in 4 consecutive bytes; and quadword integers are stored in 8 consecutive bytes.
The integer indefinite is a special value that is someti mes returned by the x87 FPU when operating on integer 
values. For more information, see Section 8.2.1, “Indefinites.”
4.2.2 Floating-Point Data Types
The IA-32 architecture defines and operates on four floating -point data types: half precision floating-point, single 
precision floating-point, double precision floating-poi nt, and double-extended precision floating-point (see 
Figure 4-3). The data formats for these data types correspond directly to formats specified in the IEEE Standard 754 for Floating-Point Arithmetic. 
VCVTPS2PH) beginning with th e third generation of Intel Core processors based on Ivy Bridge microarchitecture. 
Starting with the 4th generation Intel
 Xeon Scalable Processor Family, an Inte l AVX-512 instruction set architecture 
(ISA) for FP16 was added, supporting a wide range of gene ral-purpose numeric operations for 16-bit half precision 
floating-point values (binary16 in the IEEE Standard 754-2 019 for Floating-Point Arithmetic, aka half precision or 
FP16), which complements the existing 32-bit and 64-bit fl oating-point instructions already available in the Intel 
Xeon processor-based products.Table 4-1.  Signed Integer Encodings
Class Two’s Complement Encoding
Sign
Positive Largest 0 11..11
..
..
Smallest 0 00..01
Zero 0 00..00
Negative Smallest 1 11..11
....
Largest 1 00..00
Integer indefinite 1 00..00
Signed Byte Integer:

Sign
..
..
....
Signed Word Integer:Signed Doubleword Integer:
Signed Quadword Integer:← 7 bits →
← 15 bits →
← 31 bits →
← 63 bits →Vol. 1 4-5DATA TYPES
Table 4-2 gives the length, precision, and approximate normalized range that can be represented by each of these 
data types. Denormal values are also  supported in each of these types.
NOTE
Section 4.8, “Real Numbers and Floating-Point Form ats,” gives an overview of the IEEE Standard 
754 floating-point formats and defines the terms integer bit, QNaN, SNaN, and denormal value.
Table 4-3 shows the floating-point encodings for zeros, denormalized finite numbers, normalized finite numbers, 
infinites, and NaNs for each of the three floating-point da ta types. It also gives the format for the QNaN floating-
point indefinite value. (See Section 4.8.3.7, “QNaN Floati ng-Point Indefinite,” for a discussion of the use of the 
QNaN floating-point indefinite value.)
For the half precision, single precision, and double precis ion formats, only the fraction part of the significand is 
encoded. The integer is assumed to be 1 for all numbers except 0 and denormalized finite numbers. For the double 
extended precision format, the integer is contained in bit 63, and the most-significant fr action bit is bit 62. Here, 
the integer is explicitly set to 1 for normalized numbers, infinities, and NaNs, and to 0 for zero and denormalized 
numbers.Table 4-2.  Length, Precision, and Range of Floating-Point Data Types
Data Type Length 
(Bits)Precision
(Bits)Approximate Normalized Range
Binary Decimal
Half Precision 16 11 2–14 to 2166.10 × 10–5 to 6.55 × 104
Single Precision 32 24 2–126 to 21281.18 × 10–38 to 3.40 × 1038
Double Precision 64 53 2–1022 to 210242.23 × 10–308 to 1.80 × 10308
Double-Extended 
Precision80 64 2–16382 to 2163843.36 × 10–4932 to 1.19 × 104932
Table 4-3.  Floating-Point  Number and NaN Encodings
Class Sign Biased ExponentSignificand
Integer1Fraction
Positive + ∞ 0 11..11 1 00..00
+Normals 0
.
.
011..10
    .
    .
00..011
.
.
111..11
    .
    .
00..00
+Denormals 0
..
000..00
    .    .
00..000
..
011.11
    .    .
00..01
+Zero 0 00..00 0 00..00
Negative −Zero 1 00..00 0 00..00
−Denormals 1
..
100..00
    .    .
00..000
..
000..01
    .    .
11..11
−Normals 1
.
.
100..01
    .
    .
11..101
.
.
100..00
    .
    .
11..11
-∞ 1 11..11 1 00..004-6 Vol. 1DATA TYPES
The exponent of each floating-point data type is encoded in biased format; see Section 4.8.2.2, “Biased Exponent.” 
The biasing constant is 15 for the half precision format, 127 for the single precision format, 1023 for the double 
precision format, and 16,383 for the double extended precision format.
When storing floating-point values in memory, half precis ion values are stored in 2 consecutive bytes in memory; 
single precision values are stored in 4 consecutive bytes in  memory; double precision values are stored in 8 consec-
utive bytes; and double extended precision values are stored in 10 consecutive bytes.
The single precision and double precision floating-point data types are operated on by x87 FPU, and Intel 
SSE/SSE2/SSE3/SSE4.1/AVX instructions. The double extended  precision floating-point format is only operated on 
by the x87 FPU. See Section 11.6.8, “Compatibility of SI MD and x87 FPU Floating-Point Data Types,” for a discus-
sion of the compatibility of single pr ecision and double precision floating-poi nt data types between the x87 FPU and 
Intel SSE/SSE2/SSE3 extensions.
4.3 POINTER DATA TYPES
Pointers are addresses of locations in memory. 
In non-64-bit modes, the architecture defines two types of pointers: a near pointer  and a far pointer . A near 
pointer is a 32-bit (or 16-bit) offset (also called an effective address ) within a segment. Near pointers are used 
for all memory references in a flat memory model or for references in a segmented model where the identity of the 
segment being accessed is implied. 
A far pointer is a logical address, consisting of a 16-bit se gment selector and a 32-bit (or 16-bit) offset. Far pointers 
are used for memory references in a segmented memory  model where the identity of a segment being accessed 
must be specified explicitly. Near and far poin ters with 32-bit offsets are shown in Figure 4-4.NaNs SNaN X 11..11 1 0X..XX2
QNaN X 11..11 1 1X..XX
QNaN Floating-
Point Indefinite1 11..11 1 10..00
Half Precision
Single Precision:
Double Precision:
Double Extended Precision:← 5 Bits →
← 8 Bits →
← 11 Bits →
← 15 Bits →← 10 Bits →
← 23 Bits →
← 52 Bits →
← 63 Bits →
NOTES:
1. Integer bit is implied and not stored for half precis ion, single precision, and double precision formats.
2. The fraction for SNaN encodings must be non-zero with the most-significant bit 0.
Figure 4-4.  Pointer Data TypesTable 4-3.  Floating-Point Nu mber and NaN Encodings (Contd.)
0 47Far Pointer or Logical Address
32 31OffsetNear Pointer
0 31OffsetVol. 1 4-7DATA TYPES
4.3.1 Pointer Data Types in 64-Bit Mode
In 64-bit mode (a sub-mode of IA-32e mode), a near pointer  is 64 bits. This equates to an effective address. Far 
pointers  in 64-bit mode can be one of three forms: 
•16-bit segment selector, 16-bit offset if the operand size is 32 bits.
•16-bit segment selector, 32-bit offset if the operand size is 32 bits.
•16-bit segment selector, 64-bit offset if the operand size is 64 bits.
See Figure 4-5.
4.4 BIT FIELD DATA TYPE
A bit field  (see Figure 4-6) is a contiguous sequence of bits. It  can begin at any bit positi on of any byte in memory 
and can contain up to 32 bits.Figure 4-5.  Pointe rs in 64-Bit Mode
Figure 4-6.  Bit Field Data Type16-bit Segment Selector 16-bit Offset
0 16 15 3116-bit Segment Selector 32-bit Offset
0 32 31 4716-bit Segment Selector 64-bit Offset
0 64 63 7964-bit Offset
0 63Near Pointer
Far Pointer with 64-bit Operand Size
Far Pointer with 32-bit Operand Size
Bit Field
Least
BitSignificant4-8 Vol. 1DATA TYPES
4.5 STRING DATA TYPES
Strings are continuous sequences of bits, bytes, words, or doublewords. A bit string  can begin at any bit position 
of any byte and can contain up to 232 – 1 bits. A byte string  can contain bytes, words, or doublewords and can 
range from zero to 232 – 1 bytes (4 GBytes).
4.6 PACKED SIMD DATA TYPES
Intel 64 and IA-32 architectures define and operate on a se t of 64-bit and 128-bit packed data type for use in SIMD 
operations. These data types consist of fundamental data  types (packed bytes, words, doublewords, and quad-
words) and numeric interpretations of fundamental types fo r use in packed integer and packed floating-point oper-
ations.
4.6.1 64-Bit SIMD Packed Data Types
The 64-bit packed SIMD data types were introduced into the IA-32 architecture in the Intel MMX technology. They 
are operated on in MMX registers. The fundamental 64-bit packed data types are packed bytes, packed words, and 
packed doublewords (see Figure 4-7). When performing numer ic SIMD operations on these data types, these data 
types are interpreted as containing byte , word, or doubleword integer values.
4.6.2 128-Bit Packed SIMD Data Types
The 128-bit packed SIMD data types were introduced into the IA-32 architecture in the Intel SSE extensions and 
used with Intel SSE2, SSE3, SSSE3, SSE4.1, and AVX extensions. They are operated on primarily in the 128-bit 
XMM registers and memory. The fundamental 128-bit packed data types are packed bytes, packed words, packed 
doublewords, and packed quadwords (see Figure 4-8). Wh en performing SIMD operations on these fundamental 
data types in XMM registers, these data types are interprete d as containing packed or scalar half precision floating-
point, single precision floating-point or  double precision floating-point values, or as containing packed byte, word, 
doubleword, or quadword integer values.Figure 4-7.  64-Bit Packed SIMD Data TypesPacked WordsPacked Bytes
Packed Doublewords0 63
0 630 63
Packed Word IntegersPacked Byte Integers
Packed Doubleword Integers0 63
0 630 63Fundamental 64-Bit Packed SIMD Data Types
64-Bit Packed Integer Data TypesVol. 1 4-9DATA TYPES
4.7 BCD AND PACKED BCD INTEGERS
Binary-coded decimal integers (BCD integers) are unsigned 4- bit integers with valid values  ranging from 0 to 9. IA-
32 architecture defines operations on BCD integers located in one or more general-purpose registers or in one or 
more x87 FPU registers (see Figure 4-9).Figure 4-8.  128-Bit Packed SIMD Data TypesFundamental 128-bit Packed SIMD Data Types
128-bit Packed Floating-Point and Integer Data TypesPacked Bytes
0 127
Packed Doublewords
0 127
0 127Packed Quadwords
Packed Single Precision 
Floating-Point
0 127
0 127Packed Double Precision 
Packed Byte Integers
0 127
Packed Word Integers
0 127
Packed Doubleword 
Integers
0 127
0 127Packed Quadword 
IntegersPacked Words
0 127
Packed Half Precision 
0 1274-10 Vol. 1DATA TYPES

0 630 63
0 127
0 127
0 127
0 127
0 127
Integers
0 127
0 127
When operating on BCD integers in general-purpose regist ers, the BCD values can be unpacked (one BCD digit per 
byte) or packed (two BCD digits per byte). The value of an  unpacked BCD integer is the binary value of the low half-
byte (bits 0 through 3). The high half-byte (bits 4 through 7) can be any value during addition and subtraction, but 
must be zero during multiplication and division. Packed BCD integers allow tw o BCD digits to be contained in one 
byte. Here, the digit in the high half-byte is more  significant than the digit in the low half-byte.
When operating on BCD integers in x87 FPU data registers,  BCD values are packed in an 80-bit format and referred 
to as decimal integers. In this format, the first 9 bytes ho ld 18 BCD digits, 2 digits per byte. The least-significant 
digit is contained in the lower half-byt e of byte 0 and the most-significant di git is contained in the upper half-byte 
of byte 9. The most significant bit of byte 10 contains th e sign bit (0 = positive and 1 = negative; bits 0 through 6 
of byte 10 are don’t care bits). Negative decimal integers are not stored in two's complement form; they are distin-
guished from positive decimal integers only by the sign bit. The range of de cimal integers that can be encoded in 
this format is –1018 + 1 to 1018 – 1. 
The decimal integer format exists in memory only. When a de cimal integer is loaded in an x87 FPU data register, it 
is automatically converted to the double extended precisio n floating-point format. All decimal integers are exactly 
representable in double extended precision format.
Table 4-4 gives the possible encodings of value in the decimal integer data type.Figure 4-9.  BCD Data Types
Table 4-4.  Packed Decimal Integer Encodings
Class SignMagnitude
digit digit digit digit ... digit
Positive
 Largest0 0000000 1001 1001 1001 1001 ... 1001
.. .
.. .
 Smallest 0 0000000 0000 0000 0000 0000 ... 0001 Zero 0 0000000 0000 0000 0000 0000 ... 0000
Negative
 Zero1 0000000 0000 0000 0000 0000 ... 0000
 Smallest 1 0000000 0000 0000 0000 0000 ... 0001
.. ... .
 Largest 1 0000000 1001 1001 1001 1001 ... 1001Packed BCD Integers
BCD BCD0BCD Integers
7BCD X
34
080-Bit Packed BCD Decimal Integers
79D0
4 Bits = 1 BCD DigitSign
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
78 72 71X0 73 4Vol. 1 4-11DATA TYPES
The packed BCD integer indefinite encoding (FFFFC00 0000000000000H) is stored by the FBSTP instruction in 
response to a masked floating-point invalid-operation ex ception. Attempting to load this value with the FBLD 
instruction produces an undefined result.
4.8 REAL NUMBERS AND FLOATING-POINT FORMATS
This section describes how real numbers are repres ented in floating-point format in x87 FPU and 
SSE/SSE2/SSE3/SSE4.1 and Intel AVX floating-point instructions. It also introduces terms such as normalized 
numbers, denormalized numbers, biased exponents, sign ed zeros, and NaNs. Readers who are already familiar 
with floating-point processing techniques and the IEEE Stan dard 754 for Floating-Point Arithmetic may wish to skip 
4.8.1 Real Number System
As shown in Figure 4-10, the real-number system comprise s the continuum of real numbers from minus infinity ( −
∞) to plus infinity (+ ∞).
Because the size and number of registers that any computer  can have is limited, only a subset of the real-number 
continuum can be used in real-number (floating-point) calculations. As shown at the bottom of Figure 4-10, the subset of real numbers that the IA-32 architecture su pports represents an approximation of the real number 
system. The range and precision of this real-number subset  is determined by the IEEE Standard 754 floating-point 
formats. 
4.8.2 Floating-Point Format
To increase the speed and efficiency of real-number co mputations, computers and microprocessors typically repre-
sent real numbers in a binary floating-point format. In th is format, a real number has three parts: a sign, a signif-
icand, and an exponent (see Figure 4-11).
The sign is a binary value that indicates whether the number is positive (0) or negative (1). The significand has 
two parts: a 1-bit binary integer (also referred to as the J-bit) and a binary fraction. The integer-bit is often not 
represented, but instead is an implied value. The exponent is a binary integer that represents the base-2 power by 
which the significand is multiplied.
Table 4-5 shows how the real number 178.125 (in ordinary de cimal format) is stored in IEEE Standard 754 floating-
point format. The table lists a progression of real number notations that leads to the single precision, 32-bit 
floating-point format. In this format, the significand is  normalized (see Section 4.8.2.1, “Normalized Numbers”) 
and the exponent is biased (see Section 4.8.2.2, “Biased Exponent”). For the single precision floating-point format, 
the biasing constant is +127.Packed BCD 
Integer Indefinite1 1111111 1111 1111 1100 0000 ... 0000
← 1 byte →←  9 bytes →Table 4-4.  Packed Decima l Integer Encodings (Contd.)
digit digit digit digit ... digit4-12 Vol. 1DATA TYPES
Figure 4-10.  Binary Real Number System
Figure 4-11.  Binary Floating-Point Format
Table 4-5.  Real and Floating-Point Number Notation
Notation Value
Ordinary Decimal 178.125
Scientific Decimal 1 .78125E10 2
Scientific Binary 1 .0110010001E2111
Scientific Binary
(Biased Exponent) 1.0110010001E210000110
IEEE Single Precision Format Sign Biased Exponent Normalized Significand
0 10000110 01100100010000000000000
          1. (Implied)Binary Real Number System
Subset of binary real numbers that can be represented with
IEEE single precision (32-bit) floating-point format
+10
10.0000000000000000000000
1.11111111111111111111111
Precision 24 Binary Digits
Numbers within this range
cannot be represented.ςς ςς-100 -10 -10 1 10 100
ςς ςς-100 -10 -1 0 1 10 100
Sign
Integer or J-BitExponent Significand
FractionVol. 1 4-13DATA TYPES
4.8.2.1  Normalized Numbers
In most cases, floating-point numbers are encoded in norm alized form. This means that except for zero, the signif-
icand is always made up of an integer of 1 and the following fraction:
1.fff...ff
For values less than 1, leading zeros are eliminated. (For  each leading zero eliminat ed, the exponent is decre-
mented by one.)
Representing numbers in normalized form maximizes the number of significant digits that can be accommodated 
in a significand of a given width. To summarize, a normaliz ed real number consists of a normalized significand that 
represents a real number between 1 and 2 and an ex ponent that specifies the number’s binary point.
4.8.2.2  Biased Exponent
In the IA-32 architecture, the exponents of floating-point  numbers are encoded in a bi ased form. This means that 
a constant is added to the actual exponent so that the bi ased exponent is always a positive number. The value of 
the biasing constant depends on the number of bits ava ilable for representing exponents in the floating-point 
format being used. The biasing constant is chosen so that the smallest normalized number can be reciprocated 
without overflow.
See Section 4.2.2, “Floating-Point Data Types,” for a list of  the biasing constants that the IA-32 architecture uses 
for the various sizes of floating-point data-types.
4.8.3 Real Number and Non-number Encodings
A variety of real numbers and special values can be enco ded in the IEEE Standard 754 floating-point format. These 
numbers and values are generally divided into the following classes:
•Signed zeros
•Denormalized finite numbers
•Normalized finite numbers
•Signed infinities
•NaNs
•Indefinite numbers
(The term NaN stands for “Not a Number.”)
Figure 4-12 shows how the encodings for these numbers and non-numbers fit into the real number continuum. The 
encodings shown here are for the IEEE single precision floa ting-point format. The term “S” indicates the sign bit, 
“E” the biased exponent, and “Sig” the significand. The ex ponent values are given in decimal. The integer bit is 
shown for the significands, even though the integer bit is implied in single precision floating-point format.4-14 Vol. 1DATA TYPES
An IA-32 processor can operate on and/or return any of these values, depending on th e type of computation being 
performed. The following sections descr ibe these number and non-number classes.
4.8.3.1  Signed Zeros
Zero can be represented as a +0 or a −0 depending on the sign bit. Both enco dings are equal in value. The sign of 
a zero result depends on the operation being performe d and the rounding mode being used. Signed zeros have 
been provided to aid in implementing interval arithmetic. The sign of a zero may indicate the direction from which 
underflow occurred, or it may indicate the sign of an ∞ that has been reciprocated.
4.8.3.2  Normalized and Denormalized Finite Numbers
Non-zero, finite numbers are divided into two classes:  normalized and denormalized. The normalized finite

Non-zero, finite numbers are divided into two classes:  normalized and denormalized. The normalized finite 
numbers comprise all the non-zero finite values that ca n be encoded in a normalized real number format between 
zero and ∞. In the single precision floating-point format show n in Figure 4-12, this group of numbers includes all 
the numbers with biased exponents ranging from 1 to 25410 (unbiased, the exponent range is from −12610 to 
+12710).
When floating-point numbers become very close to zero, the normalized-number format can no longer be used to 
represent the numbers. This is because the range of the ex ponent is not large enough to compensate for shifting 
the binary point to the right to eliminate leading zeros.
When the biased exponent is zero, smaller numbers can only be represented by making the integer bit (and 
perhaps other leading bits) of the significand zero. The numbers in this range are called denormalized  numbers. 
The use of leading zeros with denormalized numbers allo ws smaller numbers to be represented. However, this 
denormalization may cause a loss of precision (the number of significant bits is reduced by the leading zeros).
When performing normalized floating-point computations , an IA-32 processor normally operates on normalized 
numbers and produces normalized numbers as results. Denormalized numbers represent an underflow  condition. 
The exact conditions are specified in Section 4.9.1.5, “Numeric Underflow Exception (#U).”
A denormalized number is computed through a technique ca lled gradual underflow. Table 4-6 gives an example of 
gradual underflow in the denormalization process. Here th e single precision format is being used, so the minimum 
exponent (unbiased) is −12610. The true result in this example requires an exponent of −12910 in order to have a Figure 4-12.  Real Numbers and NaNs1 0S ES i g1
−0
1 0−Denormalized
FiniteNaN
11...254−Normalized
Finite
1255 −∞
255 SNaN
255 QNaN
NOTES:
3. Sign bit ignored.2. Fraction must be non-zero.0 0S E Sig1
0 0NaN
01...254
0255
X3255 1.0XX ...2
255 1.1XX ...+0
+Denormalized
Finite
+Normalized
Finite
+∞
SNaN
QNaN X3X3
X3Real Number and NaN Encodings For 32-Bit Floating-Point Format−Denormalized Finite
−Normalized Finite −0 − ∞ +∞+ Denormalized Finite
+ Normalized Finite +0
0.XXX ...20.000 ...
1.000 ...1.XXX ...
1.000 ...0.000 ...
0.XXX ...2
1.XXX ...
1.0XX ...2
1.1XX ...
1. Integer bit of fraction implied for
single precision float ing-point format.Vol. 1 4-15DATA TYPES
normalized number.   Since  −12910 is beyond the allowable exponent range, the result is denormalized by inserting 
leading zeros until the minimum exponent of −12610 is reached.
In the extreme case, all the significant bits are shifted out to the right by leading zeros, creating a zero result. 
The Intel 64 and IA-32 architectures deal with denormal values in the following ways:
•It avoids creating denormals by no rmalizing numbers whenever possible.
•It provides the floating-point underflow exception to permit programmers to detect cases when denormals are 
created.
•It provides the floating-point denormal-operand exceptio n to permit procedures or programs to detect when 
denormals are being used as source operands for computations.
4.8.3.3  Signed Infinities
The two infinities, + ∞ and −∞, represent the maximum positive and negative real numbers, respectively, that can 
be represented in the floating-point format. Infinity is al ways represented by a significand of 1.00...00 (the integer 
bit may be implied) and the maximum biased exponent allowed in the specified fo rmat (for example, 25510 for the 
single precision format).
The signs of infinities are observed, and comparisons are po ssible. Infinities are always interpreted in the affine 
sense; that is, – ∞ is less than any finite number and + ∞ is greater than any finite number. Arithmetic on infinities 
is always exact. Exceptions are generated only when the use of an infinity as a source operand constitutes an 
invalid operation.
Whereas denormalized numbers may represent an underflow condition, the two ∞ numbers may represent the 
result of an overflow condition. Here, the normalized re sult of a computation has a biased exponent greater than 
the largest allowable exponent for the selected result format.
4.8.3.4  NaNs
Since NaNs are non-numbers, they are not part of the real number line. In Figure 4-12, the encoding space for 
NaNs in the floating-point formats is shown above the ends  of the real number line. This space includes any value 
with the maximum allowable biased exponent and a non- zero fraction (the sign bit is ignored for NaNs).
The IA-32 architecture defines two classes of NaNs: quiet NaNs (QNaNs) and signaling NaNs (SNaNs). A QNaN is a 
NaN with the most significant fraction bit set; an SNaN is a NaN with the most significant fraction bit clear. QNaNs are allowed to propagate through most arithmetic operat ions without signaling an exception. SNaNs generally 
signal a floating-point invalid-operation exception whenever they appear as operands in arithmetic operations.
SNaNs are typically used to trap or invoke an exception handler. They must be inserted by software; that is, the 
processor never generates an SNaN as a result of a floating-point operation.Table 4-6.  Denormalization Process
Operation Sign Exponent* Significand
True Result 0 −129 1.01011100000...00
Denormalize 0 −128 0.10101110000...00
Denormalize 0 −127 0.01010111000...00
Denormalize 0 −126 0.00101011100...00
Denormal Result 0 −126 0.00101011100...00
* Expressed as an unbiased, decimal number.4-16 Vol. 1DATA TYPES
4.8.3.5  Operating on SNaNs and QNaNs
When a floating-point operation is performed on an SNaN and/or a QNaN, the result of the operation is either a 
QNaN delivered to the destination operand or the genera tion of a floating-point invalid operation exception, 
depending on the following rules:
•If one of the source operands is an SNaN and the floating-point invalid-operation exception is not masked (see 
Section 4.9.1.1, “Invalid Operation Exception (#I)”), then a floating-point invalid-operation exception is 
signaled and no result is stored in the destination oper and. If one of the source operands is a QNaN and the 
floating-point invalid-operation exception is not masked  and the operation is one that generates an invalid-
operation exception for QNaN operands as described in Section 8.5.1.2, “Invalid Arithmetic Operand Exception 
(#IA),” or Section 11.5.2.1, “Invalid Operation Except ion (#I),” then a floating-point invalid-operation 
exception is signaled and no result is stored in the destination operand.
•If either or both of the source operands are NaNs and floating-point invalid-operation exception is masked, the 
result is as shown in Table 4-7. When an SNaN is conv erted to a QNaN, the conversion is handled by setting the 
most-significant fraction bit of the SNaN to 1. Also, when one of the source operands is an SNaN, or when it is a QNaN and the operation is one that generates an invalid-operation exception for QNaN operands as described 
in Section 8.5.1.2, “Invalid Arithmetic Operand Exce ption (#IA),” or Section 11.5.2.1, “Invalid Operation 
Exception (#I),” then the floating-point invalid-operation exception flag is set. Note that for some combinations 
of source operands, the result is different for x8 7 FPU operations and for Intel SSE/SSE2/SSE3/SSE4.1 
operations. Intel AVX follows the same behavior as Intel SSE/SSE2/SSE3/SSE4.1 in this respect.
•When neither of the source operands is a NaN, but th e operation generates a floating-point invalid-operation 
exception (see Tables 8-10 and 11-1), the result is commonly a QNaN FP Indefinite (Section 4.8.3.7).
Any exceptions to the behavior described in Table 4-7 are described in Section 8.5.1.2, “Invalid Arithmetic Operand 
Exception (#IA),” and Section 11.5.2.1, “Invalid Operation Exception (#I).”
4.8.3.6  Using SNaNs and QNaNs in Applications
Except for the rules given at the beginn ing of Section 4.8.3.4, “NaNs,” for encoding SNaNs and QNaNs, software is 
free to use the bits in the significand of a NaN for any purpose. Both SNaNs and QNaNs can be encoded to carry and 
store data, such as diagnostic information.Table 4-7.  Rules for Handling NaNs 
Source Operands Result1
SNaN and QNaN X87 FPU — QNaN source operand.
SSE/SSE2/SSE3/SSE4.1/AVX — First source operand (if this operand is an 
SNaN, it is converted to a QNaN).
Two SNaNs X87 FPU — SNaN source operand with the larger significand, converted into a 
QNaN.
SSE/SSE2/SSE3/SSE4.1/AVX — First source operand converted to a QNaN.
Two QNaNs X87 FPU — QNaN source operand with the larger significand.
SSE/SSE2/SSE3/SSE4.1/AVX — First source operand.
SNaN and a floating-point value SNaN source operand, converted into a QNaN.QNaN and a floating-point value QNaN source operand.
SNaN (for instructions that take  only one operand) SNaN source operand, converted into a QNaN.
QNaN (for instructions that take only one operand) QNaN source operand.NOTE:
1. For SSE/SSE2/SSE3/SSE4.1 instructions, the first operand is generally a source operand that becomes the destination operand. For

QNaN.
1. For SSE/SSE2/SSE3/SSE4.1 instructions, the first operand is generally a source operand that becomes the destination operand. For 
AVX instructions, the first source operand is usually the 2nd operand in a non-destructive source syntax. Within the Result  column, 
the x87 FPU notation also applies to the FISTTP instruction in SSE3; the SSE3 notation applies to the SI MD floating-point instr uc-
tions.Vol. 1 4-17DATA TYPES
By unmasking the invalid operation exception, the progra mmer can use signaling NaNs to trap to the exception 
handler. The generality of this approa ch and the large number of NaN values that are available provide the sophis-
ticated programmer with a tool that can be applied to a variety of special situations.
For example, a compiler can use signaling NaNs as referenc es to uninitialized (real) array elements. The compiler 
can preinitialize each array element with a signaling NaN wh ose significand contains the index (relative position) of 
the element. Then, if an application program attempts to ac cess an element that it has not initialized, it can use the 
NaN placed there by the compiler. If th e invalid operation exception is unmask ed, an interrupt will occur, and the 
exception handler will be invoked. The exception handle r can determine which element has been accessed, since 
the operand address field of the exception pointer will po int to the NaN, and the NaN will contain the index number 
of the array element.
Quiet NaNs are often used to speed up debugging. In it s early testing phase, a program often contains multiple 
errors. An exception handler can be written to save diagnost ic information in memory whenever it is invoked. After 
storing the diagnostic data, it can supply a quiet NaN as the result of the erroneous instruction, and that NaN can 
point to its associated diagnostic area in memory. The program will then continue, creating a different NaN for each 
error. When the program ends, the NaN results can be used  to access the diagnostic data saved at the time the 
errors occurred. Many errors can thus be diagnosed and corrected in one test run.
In embedded applications that use comp uted results in further computations, an undetected QNaN can invalidate 
all subsequent results. Such applications should theref ore periodically check for QNaNs and provide a recovery 
mechanism to be used if a QNaN result is detected. 
4.8.3.7  QNaN Floating-Point Indefinite
For the floating-point data type encodings (single precisio n, double precision, and doub le extended precision), one 
unique encoding (a QNaN) is reserved for representing the special value QNaN floating-point indefinite. The x87 
FPU and the Intel SSE/SSE2/SSE3/SSE4.1/AVX extensions re turn these indefinite values as responses to some 
masked floating-point exceptions. Table 4-3 shows the en coding used for the QNaN floating-point indefinite.
4.8.3.8  Half Precision Floating-Point Operation
Two instructions, VCVTPH2PS and VCVTPS2PH, which provid e conversion only between half precision and single 
precision floating-point values, were introduced with the F16C extensions beginning with the third generation of 
Intel Core processors based on Ivy Bridge microarc hitecture. Starting with the 4th generation Intel Xeon Scalable 
Processor Family, an Intel AVX-512 instruction set architec ture (ISA) for FP16 was added, supporting a wide range 
of general-purpose numeric operations for 16-bit half prec ision floating-point values (binary16 in the IEEE Stan-
dard 754-2019 for Floating-Point Arithmetic, aka half prec ision or FP16). These additions complement the existing 
32-bit and 64-bit floating-point instructions already available in the Intel Xeon processor-based products.
The SIMD floating-point exception behavior of the VCVTPH2PS and VCVTPS2PH instructions, as well as of the other 
half precision instructions, are described in Section 14.4.1.
4.8.4 Rounding
When performing floating-point operations, the processor prod uces an infinitely precise floating-point result in the 
destination format (half precision, single precision, double  precision, or double extended precision floating-point) 
whenever possible. However, because only a subset of the numbers in the real number continuum can be repre-
sented in IEEE Standard 754 floating-point formats, it is often the case that an infinitely precise result cannot be 
encoded exactly in the format of the destination operand.
For example, the following value ( a) has a 24-bit fraction. The least-significant bit of this fraction (the underlined 
bit) cannot be encoded exactly in the single prec ision format (which has only a 23-bit fraction):
(a) 1.0001 0000 1000 0011 1001 0111 E2 101
To round this result ( a), the processor first selects two representable fractions b and c that most closely bracket a 
in value ( b < a < c).
(b) 1.0001 0000 1000 0011 1001 011E2 101
(c) 1.0001 0000 1000 0011 1001 100E2 1014-18 Vol. 1DATA TYPES
The processor then sets the result to b or to c according to the selected rounding mode. Rounding introduces an 
error in a result that is less than one unit in the last place (the least significant bit position of the floating-point value) to which the result is rounded.
The IEEE Standard 754 defines four rounding modes (see Table 4-8): round to nearest,  round up, round down, and 
round toward zero. The default rounding mode (for the Inte l 64 and IA-32 architectures) is round to nearest. This 
mode provides the most accurate and statistically unbiased estimate of the true result and is suitable for most 
applications. 
The round up and round down modes are termed directed rounding  and can be used to implement interval arith-
metic. Interval arithmetic is used to determine upper an d lower bounds for the true result of a multistep computa-
tion, when the intermediate results of the computation are subject to rounding. 
The round toward zero mode (sometimes called the “cho p” mode) is commonly used when performing integer 
arithmetic with the x87 FPU.
The rounded result is called the inexact result. When the processor produces an inexact result, the floating-point 
precision (inexact) flag (PE) is set (see Section 4. 9.1.6, “Inexact-Result (Precision) Exception (#P)”).
The rounding modes have no effect on comparison operations , operations that produce exact results, or operations 
that produce NaN results.
4.8.4.1  Rounding Control (RC) Fields
In the Intel 64 and IA-32 architectures, the rounding mo de is controlled by a 2-bit rounding-control (RC) field 
(Table 4-8 shows the encoding of this field). The RC  field is implemented in two different locations: 
•X87 FPU control register (bits 10 and 11).
•The MXCSR register (bits 13 and 14).
Although these two RC fields perform the same function , they control rounding for different execution environ-
ments within the processor. The RC field in the x87 FPU control register controls rounding for computations 
performed with the x87 FPU instructions; the RC field in the MXCSR register controls rounding for SIMD floating-
point computations performed with the Inte l SSE/SSE2/SSE3/SSE4.1/AVX instructions.
4.8.4.2  Truncation with Intel® SSE, SSE2, and AVX Conversion Instructions
The following Intel SSE/SSE2 instructions automatically truncate the results of conversions from floating-point 
values to integers when the result it inexact: CVTTPD 2DQ, CVTTPS2DQ, CVTTPD2PI, CVTTPS2PI, CVTTSD2SI, and 
CVTTSS2SI. Here, truncation means the round toward zero mode described in Table 4-8. There are also several 
Intel AVX2 and AVX-512 instructions which use truncation (VCVTT*).Table 4-8.  Rounding Modes and Encoding of Rounding Control (RC) Field
Rounding Mode RC Field 
SettingDescription
Round to 
nearest (even)00B Rounded result is the closest to the infinitely precise result. If two values are equally close, the 
result is the even value (that is, the one with the least-significant bit of zero). Default
Round down 
(toward −∞)01B Rounded result is closest to but no gr eater than the infinitely precise result.
Round up 
(toward +∞)10B Rounded result is closest to but no less than the infinitely precise result.
Round toward 
zero (Truncate)11B Rounded result is closest to bu t no greater in absolu te value than the infi nitely precise result.Vol. 1 4-19DATA TYPES
4.9 OVERVIEW OF FLOATING-POINT EXCEPTIONS
The following section provides an overvi ew of floating-point exceptions and their handling in the IA-32 architec-
ture. For information specific to the x87 FPU and to the Intel SSE/SSE2/SSE3/SSE4.1/AVX extensions, refer to the 
following sections:
•Section 4.9, “Overview of Floating-Point Exceptions.”
•Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions.” 
•Section 12.8.4, “IEEE 754 Compliance of Inte l® SSE4.1 Floating-Point Instructions.”
•Section 14.10, “SIMD Floating-Point Exceptions.”
When operating on floating-point operands, the IA-32 architecture recognizes and detects six classes of exception 
conditions:
•Invalid operation (#I).
•Divide-by-zero (#Z).
•Denormalized operand (#D).
•Numeric overflow (#O).
•Numeric underflow (#U).
•Inexact result (precision) (#P).

The nomenclature of “#” symbol followed by one or two letters  (for example, #P) is used in this manual to indicate 
exception conditions. It is merely a short-hand form and is not related to assembler mnemonics.
NOTE
All of the exceptions listed above except the denormal-operand exception (#D) are defined in IEEE 
Standard 754.
The invalid-operation, divide-by-zero and denormal-operand  exceptions are pre-computation exceptions (that is, 
they are detected before any arithmetic operation occu rs). The numeric-underflow, numeric-overflow and precision 
exceptions are post-computation exceptions.
Each of the six exception classes has a corresponding flag bit (IE, ZE, OE, UE, DE, or PE ) and mask bit (IM, ZM, OM, 
UM, DM, or PM). When one or more fl oating-point exception conditions are detected, the processor sets the appro-
priate flag bits, then takes one of two possible courses of action, depending on the settings of the corresponding 
mask bits:
•Mask bit set. Handles the exception automatically, pr oducing a predefined (and often times usable) result, 
while allowing program execution to continue undisturbed.
•Mask bit clear. Invokes a software exception handler to handle the exception.
The masked (default) responses to exceptions have been chosen to deliver a reasonable result for each exception 
condition and are generally satisfactory for most floating -point applications. By masking or unmasking specific 
floating-point exceptions, programmer s can delegate responsibility for most exceptions to the processor and 
reserve the most severe exception conditions for software exception handlers. 
Because the exception flags are “sticky,” they provide a cu mulative record of the exceptions that have occurred 
since they were last cleared. A programmer can thus mask all exceptions, run a calculation, and then inspect the 
exception flags to see if any exceptions were detected during the calculation.
In the IA-32 architecture, floating-point exception flag an d mask bits are implemented in two different locations: 
•X87 FPU status word and control word. The flag bits are located at bits 0 through 5 of the x87 FPU status word 
and the mask bits are located at bits 0 through 5 of  the x87 FPU control word (see Figures 8-4 and 8-6).
•MXCSR register. The flag bits are located at bits 0 th rough 5 of the MXCSR register and the mask bits are 
located at bits 7 through 12 of the register (see Figure 10-3).
Although these two sets of flag and mask bits perform the same function, they report on and control exceptions for 
different execution environments within the processor. Th e flag and mask bits in the x87 FPU status and control 
words control exception reporting and masking for comput ations performed with the x87 FPU instructions; the 4-20 Vol. 1DATA TYPES
companion bits in the MXCSR register control exception reporting and masking for SIMD floating-point computa-
tions performed with the Intel SSE/SSE2/SSE3/SSE4.1/AVX instructions.
Note that when exceptions are masked, the processor may detect multiple exceptions in a single instruction, 
because it continues executing the instruction after performing its masked response. For example, the processor can detect a denormalized operand, perform its masked response to this exception, and then detect numeric 
underflow.
See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules for exception precedence when 
more than one floating-point exception condition is detected for an instruction.
4.9.1 Floating-Point Exception Conditions
The following sections describe the various conditions that cause a floating-point exception to be generated and the 
masked response of the processor when these conditions are detected. The Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volumes 3A, 3B, 3C, & 3D, lists th e floating-point exceptions that can be signaled for 
each floating-point instruction.
4.9.1.1  Invalid Operation Exception (#I)
The processor reports an invalid operation exception in response to one or more invalid arithmetic operands. If the invalid operation exception is masked, the processor sets the IE flag and returns an indefinite value or a QNaN. This 
value overwrites the destination register specified by th e instruction. If the invalid operation exception is not 
masked, the IE flag is set, a software exception ha ndler is invoked, and the operands remain unaltered.
See Section 4.8.3.6, “Using SNaNs and QNaNs in Applicatio ns,” for information about the result returned when an 
exception is caused by an SNaN.
The processor can detect a variety of invalid arithmetic operations that can be coded in a program. These opera-
tions generally indicate a programming error, such as dividing ∞by∞. See the following sections for information 
regarding the invalid-operation exception when  detected while executing x87 FPU or Intel 
SSE/SSE2/SSE3/SSE4.1/AVX instructions:
•X87 FPU; Section 8.5.1, “Invalid Operation Exception.”
•SIMD floating-point exceptions; Section 11 .5.2.1, “Invalid Operation Exception (#I).”
•Section 12.8.4, “IEEE 754 Compliance of Intel® SSE4.1 Floating-Point Instructions.”
4.9.1.2  Denormal Operand Exception (#D)
The processor reports the denormal-operand exception if an arithmetic instruction attempts to operate on a 
denormal operand (see Section 4.8.3.2, “Normalized and De normalized Finite Numbers”). When the exception is 
masked, the processor sets the DE flag and proceeds wi th the instruction. Operating on denormal numbers will 
produce results at least as good as, and often better th an, what can be obtained when denormal numbers are 
flushed to zero. Programmers can mask this exception so that a computation may proceed, then analyze any loss 
of accuracy when the final result is delivered.
When a denormal-operand exception is not masked, the DE fl ag is set, a software exception handler is invoked, and 
the operands remain unaltered. When denormal operands ha ve reduced significance due to loss of low-order bits, 
it may be advisable to not operate on them. Precluding  denormal operands from computations can be accom-
plished by an exception handler that respon ds to unmasked denormal-operand exceptions.
See the following sections for information regarding the denormal-operand exception when detected while 
executing x87 FPU or Intel SSE/SSE2/SSE3/SSE4.1/AVX instructions:
•X87 FPU; Section 8.5.2, “Denormal Operand Exception (#D).”
•SIMD floating-point exceptions; Section 11 .5.2.2, “Denormal-Operand Exception (#D).”
•Section 14.10, “SIMD Floating-Point Exceptions.”Vol. 1 4-21DATA TYPES
4.9.1.3  Divide-By-Zero Exception (#Z)
The processor reports the floating-point divide-by-zero exception whenever an instruction attempts to divide a 
finite non-zero operand by 0. The masked response for the divide-by-zero exception is to set the ZE flag and return 
an infinity signed with the exclusive OR of the sign of the operands. If the divide-by-zero exception is not masked, 
the ZE flag is set, a software exception handler is invoked, and the operands remain unaltered.
See the following sections for information regarding the divide-by-zero exception when detected while executing 
x87 FPU or Intel SSE/SSE2/AVX instructions:
•X87 FPU; Section 8.5.3, “Divide-By-Zero Exception (#Z).”
•SIMD floating-point exceptions; Section 11.5.2.3, “Divide-By-Zero Exception (#Z).”
4.9.1.4  Numeric Overflow Exception (#O)
The processor reports a floating-point numeric overflow ex ception whenever the rounded result of an instruction 
exceeds the largest allowable finite value that will fit in to the destination operand. Table 4-9 shows the threshold 
range for numeric overflow for each of the floating-point fo rmats; overflow occurs when a rounded result falls at or 
outside this threshold range.
When a numeric-overflow exception occurs and the exception is masked, the processor sets the OE flag and 
returns one of the values shown in Table 4-10, accord ing to the current rounding mode. See Section 4.8.4, 
“Rounding.”
When numeric overflow occurs and the numeric-overflow exception is not masked, the OE flag is set, a software 
exception handler is invoked, and the so urce and destination operands either remain unchanged or a biased result 
is stored in the destination operand (depending whethe r the overflow exception was generated during an Intel 
SSE/SSE2/SSE3/SSE4.1/AVX floating-point  operation or an x87 FPU operation).
See the following sections for information regarding the num eric overflow exception when detected while executing 
x87 FPU instructions or while executing Intel SSE/SSE2/SSE3/SSE4.1/AVX instructions:

•X87 FPU; Section 8.5.4, “Numeric Overflow Exception (#O).”Table 4-9.  Numeric Overflow Thresholds
Floating-Point Format Overflow Thresholds
Half Precision | x | ≥ 1.0 ∗ 216
Single Precision | x | ≥ 1.0 ∗ 2128
Double Precision | x | ≥ 1.0 ∗ 21024
Double Extended Precision | x | ≥ 1.0 ∗ 216384
Table 4-10.  Masked Responses to Numeric Overflow
Rounding Mode Sign of True Result Result
To nearest + + ∞
–– ∞
Toward – ∞ + Largest finite positive number
–– ∞
Toward + ∞ ++ ∞
– Largest finite negative number
Toward zero + Largest finite positive number
– Largest finite negative number4-22 Vol. 1DATA TYPES
•SIMD floating-point exceptions; Section 11 .5.2.4, “Numeric Overflow Exception (#O).”
4.9.1.5  Numeric Underflow Exception (#U)
The processor detects a potential floating-point numeric und erflow condition whenever the result of rounding with 
unbounded exponent (taking into account precision control for x87) is non-zero and tiny; that is, non-zero and less 
than the smallest possible normalized, finite value that will fit into the destination operand. Table 4-11 shows the 
threshold range for numeric underflow for each of the floa ting-point formats (assuming normalized results); under-
flow occurs when a rounded result falls strictly within the threshold range. The ability to detect and handle under-
flow is provided to prevent a very small result from propagating through a computation and causing another 
exception (such as overflow during di vision) to be generated at a later ti me. Results which trigger underflow are 
also potentially less accurate.
How the processor handles an underflow cond ition, depends on two related conditions:
•Creation of a tiny, non-zero result.
•Creation of an inexact result; that is, a result that cannot be represented exactly in the destination format.
Which of these events causes an underflow exception to be reported and how the processor responds to the excep-
tion condition depends on whether the underflow exception is masked:
•Underflow exception masked —  The underflow exception is reported (the UE flag is set) only when the result 
is both tiny and inexact. The processor returns a correct ly signed result whose magnitude is less than or equal 
to the smallest positive normal floating-point number to the destination operand, regardless of inexactness.
•Underflow exception not masked —  The underflow exception is reported when the result is non-zero tiny, 
regardless of inexactness. The processor leaves the so urce and destination operands unaltered or stores a 
biased result in the destination operand (depending wh ether the underflow exception was generated during an 
Intel SSE/SSE2/SSE3/AVX floating-point operation or an  x87 FPU operation) and invokes a software exception 
handler.
See the following sections for information regarding the numeric underflow exception when detected while 
executing x87 FPU instructions or while executin g Intel SSE/SSE2/SSE3/SSE4.1/AVX instructions:
•X87 FPU; Section 8.5.5, “Numeric Underflow Exception (#U).”
•SIMD floating-point exceptions; Section 11 .5.2.5, “Numeric Underflow Exception (#U).”
4.9.1.6  Inexact-Result (Precision) Exception (#P)
The inexact-result exception (also called the precision exceptio n) occurs if the result of an operation is not exactly 
representable in the destination format. For example, the fraction 1/3 cannot be precisely represented in binary 
floating-point form. This exception occurs frequently and indicates that some (normally acceptable) accuracy will 
be lost due to rounding. The exception is supported for a pplications that need to perform exact arithmetic only. 
Because the rounded result is generally satisfactory fo r most applications, this exception is commonly masked.Table 4-11.  Numeric Underflow (Normalized) Thresholds
Floating-Point Format Underflow Thresholds1
NOTES:
1. Where ‘x’ is the result rounded to destinat ion precision with an unbounded exponent range.Half Precision | x | < 1.0 ∗ 2−14
Single Precision | x | < 1.0 ∗ 2−126
Double Precision | x | < 1.0 ∗ 2−1022
Double Extended Precision | x | < 1.0 ∗ 2−16382Vol. 1 4-23DATA TYPES
If the inexact-result exception is masked when an inexac t-result condition occurs and a numeric overflow or under-
flow condition has not occurred, the processor sets the PE flag and stores the rounded result in the destination operand. The current rounding mode determines the me thod used to round the result. See Section 4.8.4, 
If the inexact-result exception is not masked when an in exact result occurs and numeric overflow or underflow has 
not occurred, the PE flag is set, the rounded result is st ored in the destination operand, and a software exception 
handler is invoked.
If an inexact result occurs in conjunction with numeric ov erflow or underflow, one of the following operations is 
carried out:
•If an inexact result occurs along with masked overflow or  underflow, the OE flag or UE flag and the PE flag are 
set and the result is stored as described for the ov erflow or underflow exceptions; see Section 4.9.1.4, 
“Numeric Overflow Exception (#O),” or Section 4.9.1.5,  “Numeric Underflow Exception (#U).” If the inexact 
result exception is unmasked, the processor also invokes a software exception handler.
•If an inexact result occurs along with unmasked overflow  or underflow and the destination operand is a register, 
the OE or UE flag and the PE flag are set, the result  is stored as described for the overflow or underflow 
exceptions, and a software exception handler is invoked.
If an unmasked numeric overflow or underflow exception occurs and the destination operand is a memory location 
(which can happen only for a floating-point store), the inex act-result condition is not reported and the C1 flag is 
cleared.
See the following sections for information regarding the inexact-result exception when detected while executing 
x87 FPU or Intel SSE/SSE2/SSE3/SSE4.1/AVX instructions:
•X87 FPU; Section 8.5.6, “Inexact-Result (Precision) Exception (#P).”
4.9.2 Floating-Point Exception Priority
The processor handles exceptions according to a predeter mined precedence. When an instruction generates two or 
more exception conditions, the exception precedence so metimes results in the high er-priority exception being 
handled and the lower-priority exceptions being ignored. For example, dividing an SNaN by zero can potentially 
signal an invalid-operation exception (due to the SNaN operand) and a divide-by-zero exception. Here, if both 
exceptions are masked, the processor handles the higher-pri ority exception only (the invalid-operation exception), 
returning a QNaN to the destination. Alternately, a deno rmal-operand or inexact-result exception can accompany 
a numeric underflow or overflow exception with both exceptions being handled.
The precedence for floating-point exceptions is as follows:1. Invalid-operation exception, subdivided as follows:
a. Stack underflow (occurs with x87 FPU only).
b. Stack overflow (occurs with x87 FPU only).c. Operand of unsupported format (occurs with x87 FP U only when using the do uble extended precision 
floating-point format).
d. SNaN operand.
2. QNaN operand. Though this is not an exception, the handling of a QNaN operand has precedence over lower-
priority exceptions. For example, a QNaN divided by zero results in a QNaN, not a zero-divide exception.
3. Any other invalid-operation exception not mentioned above or a divide-by-zero exception.
4. Denormal-operand exception. If masked, then instruct ion execution continues, and a lower-priority exception 
can occur as well.
5. Numeric overflow and underflow exceptions; possibly in conjunction with the inexact-result exception.6. Inexact-result exception.4-24 Vol. 1DATA TYPES
Invalid operation, zero divide, and denormal operand exce ptions are detected before a floating-point operation 
begins. Overflow, underflow, and precision exceptions ar e not detected until a true result has been computed. 
When an unmasked pre-operation exception is detected, the destination operand has not yet been updated, and 
appears as if the offending instruction has not been executed. When an unmasked post-operation exception is 
detected, the destination operand may be updated with a re sult, depending on the nature of the exception (except 
for Intel SSE/SSE2/SSE3/AVX instructions, which do not update their destination operands in such cases).
4.9.3 Typical Actions of a Floating-Point Exception Handler

After the floating-point exception handler is invoked, the processor handles the exception in the same manner that 
it handles non-floating-point exceptions. The floating-poi nt exception handler is normally part of the operating 
system or executive software, and it usually invokes a user-registered floating-point exception handle. 
A typical action of the exception handler is to store st ate information in memory. Other typical exception handler 
actions include:
•Examining the stored state information to determine the nature of the error.
•Taking actions to correct the condition that caused the error.
•Clearing the exception flags.
•Returning to the interrupted program and resuming normal execution.
In lieu of writing recovery procedures, the exception handler can do the following:
•Increment in software an exception counter for later display or printing.
•Print or display diagnostic information (such as the state information).
•Halt further program execution.Vol. 1 5-1CHAPTER 5
This chapter provides an abridged overview of Intel 64 an d IA-32 instructions. Instructions are divided into the 
following groups:
•Section 5.1, “General-Purpose Instructions.”
•Section 5.2, “x87 FPU Instructions.”
•Section 5.3, “x87 FPU AND SIMD State Management Instructions.”
•Section 5.4, “MMX Instructions.”
•Section 5.5, “Intel® SSE Instructions.”
•Section 5.6, “Intel® SSE2 Instructions.”
•Section 5.7, “Intel® SSE3 Instructions.”
•Section 5.8, “Supplemental Streaming SIMD Extensions 3 (SSSE3) Instructions.”
•Section 5.9, “Intel® SSE4 Instructions.”
•Section 5.10, “Intel® SSE4.1 Instructions.”
•Section 5.11, “Intel® SSE4.2 Instruction Set.”
•Section 5.12, “Intel® AES-NI and PCLMULQDQ.”
•Section 5.13, “Intel® Advanced Vector Extensions (Intel® AVX).”
•Section 5.14, “16-bit Floating-Point Conversion.”
•Section 5.15, “Fused-Multiply-ADD (FMA).”
•Section 5.16, “Intel® Advanced Vector Extensions 2 (Intel® AVX2).”
•Section 5.17, “Intel® Transactional Synchronization Extensions (Intel® TSX).”
•Section 5.18, “Intel® SHA Extensions.”
•Section 5.19, “Intel® Advanced Vector Extensions 512 (Intel® AVX-512).”
•Section 5.20, “System Instructions.”
•Section 5.21, “64-Bit Mode Instructions.”
•Section 5.22, “Virtual-Machine Extensions.”
•Section 5.23, “Safer Mode Extensions.”
•Section 5.24, “Intel® Memory Protection Extensions.”
•Section 5.25, “Intel® Software Guard Extensions.”
•Section 5.26, “Shadow Stack Management Instructions.”
•Section 5.27, “Control Transfer Terminating Instructions.”
•Section 5.28, “Intel® AMX Instructions.”
•Section 5.29, “User Interrupt Instructions.”
•Section 5.30, “Enqueue Store Instructions.”
Table 5-1 lists the groups and IA-32 processors that support each group. More recent instruction set extensions are 
listed in Table 5-2. Within these groups, most inst ructions are collected into functional subgroups.5-2 Vol. 1INSTRUCTION SET SUMMARY
Table 5-1.  Instruction Groups in  Intel® 64 and IA-32 Processors 
Instruction Set 
Architecture Intel 64 and IA-32 Processor Support
General Purpose All Intel 64  and IA-32 processors.
 X87 FPU Intel486, Pentium, Pentium with MM X Technology, Celeron, Pentium Pro, Pentium II, Pentium II Xeon, 
Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon proc essors, Pentium M, Intel Co re Solo, Intel Core Duo, 
Intel Core 2 Duo processors, Intel Atom processors.
X87 FPU and SIMD State 
ManagementPentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Pentium 4, Intel Xe on processors, Pentium M, 
Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors, Intel Atom processors.
MMX Technology Pentium with MMX Technology , Celeron, Pentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Pentium 
4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors, Intel Atom 
SSE Extensions Pentium III, Pentiu m III Xeon, Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, 
SSE2 Extensions Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors, 
Intel Atom processors.
SSE3 Extensions Pentium 4 supporting HT Technology (built on 90 nm process technology), Intel Core Solo, Intel Core Duo, 
Intel Core 2 Duo processors, Intel Xeon processo r 3xxxx, 5xxx, 7xxx Series, Intel Atom processors.
SSSE3 Extensions Intel Xeon processor 3 xxx, 5100, 5200, 5300, 5400, 5500, 5600, 7300, 7400, 7500 series, Intel Core 2 
Extreme processors QX6000 series, Intel Core 2 Duo, Intel Core 2 Quad processors, Intel Pentium Dual-Core 
processors, Intel Atom processors.
IA-32e mode: 64-bit 
mode instructionsIntel 64 processors.
System Instructions Intel 64 and IA-32 processors.
VMX Instructions Intel 64  and IA-32 processors supporting Intel Virtualizati on Technology.
SMX Instructions Intel Core 2 Duo processor E6x5 0, E8xxx; Intel Core 2 Quad processor Q9xxx.
Table 5-2.  Instruction Set Extensions Intr oduction in Intel® 64 and IA-32 Processors
Instruction Set Architecture Proc essor Generation Introduction
SSE4.1 Extensions Intel® Xeon® processor 3100, 3300, 5200, 5400, 7400, 7500 series, Intel® Core™ 2 Extreme 
processors QX9000 series, Intel® Core™ 2 Quad processor Q9000 series, Intel® Core™ 2 Duo processors 8000 series and T9000 series, Intel Atom® proc essor based on Silvermont microarchitecture.
SSE4.2 Extensions, CRC32, 
POPCNTIntel® Core™ i7 965 processor, Intel® Xeon® proc essors X3400, X3500, X5500, X6500, X7500 series, 
Intel Atom processor based on Silvermont microarchitecture.
Intel® AES-NI, PCLMULQDQ Intel® Xeon® proce ssor E7 series, Intel® Xeon® processors X3600 and X5600, Intel® Core™ i7 980X 
processor, Intel Atom processor based on Silvermont microarchitecture. Use CPUID to verify presence 
of Intel AES-NI and PC LMULQDQ across Intel® Cor e™ processor families.
Intel® AVX Intel® Xeon® processor E3 and E5 families, 2n d Generation Intel® Core™ i7, i5, i3 processor 2xxx 
families.
F16C 3rd Generation Intel® Core™ processors, Intel® Xeon® processor E3-1200 v2 product family, Intel® 
Xeon® processor E5 v2 and E7 v2 families.
RDRAND 3rd Generation Intel Core processors, Intel Xeon processor E3-1200 v2 product family, Intel Xeon 
processor E5 v2 and E7 v2 families, Intel Atom processor based on Silvermont microarchitecture.
FS/GS base access 3rd Generation Intel Core processors, Intel Xeon processor E3-1200 v2 product family, Intel Xeon 
processor E5 v2 and E7 v2 families, Intel Atom® processor based on Goldmont microarchitecture.Vol. 1 5-3INSTRUCTION SET SUMMARY
FMA, AVX2, BMI1, BMI2, 
INVPCID, LZCNT, Intel® TSXIntel® Xeon® processor E3/E5/E7 v3 product families, 4th Generation Intel® Core™ processor family.
MOVBE Intel Xeon processor E3/E5/E7 v3 product families, 4th Generation Intel Core processor family, Intel 
Atom processors.
PREFETCHW Intel® Core™ M processor family; 5th Generation  Intel® Core™ processor fa mily, Intel Atom processor 
based on Silvermont microarchitecture.
ADX Intel Core M processor family, 5th Generation Intel Core processor family.RDSEED, CLAC, STAC Intel Core M processor family, 5th Generati on Intel Core processor family, Intel Atom processor based 
on Goldmont microarchitecture.
AVX512ER, AVX512PF, 
PREFETCHWT1Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series.
AVX512F, AVX512CD Intel Xeon Phi Processor 3200, 5200, 7200 Se ries, Intel® Xeon® Scalable Pr ocessor Family, Intel® Core™ 
i3-8121U processor.
CLFLUSHOPT, XSAVEC, 
XSAVES, Intel® MPXIntel Xeon Scalable Processor Fa mily, 6th Generation Intel® Core ™ processor family, Intel Atom 
processor based on Goldmont microarchitecture.
SGX1 6th Generation Intel Core processor family, Intel Atom® processor based on Goldmont Plus 
AVX512DQ, AVX512BW, 
AVX512VLIntel Xeon Scalable Processor Family, Intel Core i3-8121U processor based on Cannon Lake 
CLWB Intel Xeon Scalable Processor Fa mily, Intel Atom® processor based on  Tremont microarchitecture, 11th 
Generation Intel Core processor family based on Tiger Lake microarchitecture.
PKU Intel Xeon Scalable Processor Family, 10th genera tion Intel® Core™ processors based on Comet Lake 
AVX512_IFMA, 
AVX512_VBMIIntel Core i3-8121U processor based on Cannon Lake microarchitecture.
Intel® SHA Extensions Inte l Core i3-8121U processor based on Cannon Lake  microarchitecture, Inte l Atom processor based 
on Goldmont microarchitecture, 3rd Generation Intel® Xeon® Scalable Processor Family based on Ice 
Lake microarchitecture.
UMIP Intel Core i3-8121U processor based on Cannon Lake microarchitecture, In tel Atom processor based 
on Goldmont Plus microarchitecture.
PTWRITE Intel Atom processor based on Goldmont Plus  microarchitecture, 12th generation Intel® Core™ 
processor based on Alder Lake performance hybrid ar chitecture, 4th generation  Intel® Xeon® Scalable 
Processor Family based on Sapphire Rapids microarchitecture.
RDPID 10th Generation Intel® Core™ processor family based on Ice Lake microa rchitecture, Intel Atom

RDPID 10th Generation Intel® Core™ processor family based on Ice Lake microa rchitecture, Intel Atom 
processor based on Goldmont Plus microarchitecture.
AVX512_4FMAPS, 
AVX512_4VNNIWIntel® Xeon Phi™ Processor 7215, 7285, 7295 Series.
AVX512_VNNI 2nd Generation Intel® Xeon® Scalable Processo r Family, 10th Generation Intel Core processor family 
based on Ice Lake microarchitecture.
AVX512_VPOPCNTDQ Intel Xeon Phi Processor 7215, 7285, 7295 Series, 10th Generation Intel Core processor family based 
on Ice Lake microarchitecture.
Fast Short REP MOV 10th Generation Intel Core processor family based on Ice Lake microarchitecture.
GFNI (SSE) 10th Generation Intel Core processor family base d on Ice Lake microarchitecture, Intel Atom processor 
based on Tremont microarchitecture.Table 5-2.  Instruction Set Extensions Introducti on in Intel® 64 and IA -32 Processors (Contd.)
Instruction Set Architecture Proc essor Generation Introduction5-4 Vol. 1INSTRUCTION SET SUMMARY
VAES, GFNI (AVX/AVX512), 
AVX512_VBMI2, 
VPCLMULQDQ, 
AVX512_BITALG10th Generation Intel Core processor family based on Ice Lake microarchitecture.
ENCLV Future processors.
Split Lock Detection 10th Generation Intel Core processor family  based on Ice Lake microarchitecture, Intel Atom processor 
based on Tremont microarchitecture.
CLDEMOTE Intel Atom processor based on Tremont microarchitecture, 4th generation Intel® Xeon® Scalable 
Direct stores: MOVDIRI, 
MOVDIR64B Intel Atom processor based on Tremont microarchitecture, 11th Generation Intel Core processor 
family based on Tiger Lake microarchitecture, 4th generation Intel® Xeon® Scalable Processor Family 
based on Sapphire Rapids microarchitecture.
User wait: TPAUSE, 
UMONITOR, UMWAITIntel Atom processor based on Tremont microarchitect ure, 12th generation Intel Core processor based 
on Alder Lake performance hybrid architecture, 4th generation Intel® Xeon® Scalable Processor Family 
AVX512_BF16 3rd Generation Intel® Xeon® Scalable Processor Family based on Cooper Lake product, 4th generation 
Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture.
AVX512_VP2INTERSECT 11th Generation Intel Core proce ssor family based on Tiger Lake microarchitecture.
Key Locker111th Generation Intel Core proce ssor family based on Tiger Lake microarchitecture, 12th generation 
Intel Core processor based on Alder La ke performance hybrid architecture.
Control-flow Enforcement 
Technology (CET)11th Generation Intel Core proce ssor family based on Tiger Lake microarchitecture, 4th generation 
TME-MK2, PCONFIG 3rd Generation Intel® Xeon® Scalable Proc essor Family based on Ice Lake microarchitecture.
WBNOINVD 3rd Generation Intel® Xeon® Scalable Processor Family based on Ice Lake microarchitecture.
LBRs (architectural) 12th generation Intel Core processor based on Alder Lake performance hybrid architecture, 4th 
generation Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture.
Intel® Virtualization 
Technology - Redirect 
Protection (Intel® VT-rp) and HLAT12th generation Intel Core processor based on Alder Lake performance hybrid architecture, 4th 
AVX-VNNI 12th generation Intel Core processor based on Alder Lake performance hybrid architecture
3, 4th 
SERIALIZE 12th generation Intel Core processor based on Alder Lake performance hybrid architecture, 4th 
Intel® Thread Director and 
HRESET12th generation Intel Core processor based on Alder Lake performance hybrid architecture.
Fast zero-length REP MOVSB, 
fast short REP STOSB12th generation Intel Core processor based on Alder Lake performance hybrid architecture, 4th 
Fast Short REP CMPSB, fast 
short REP SCASB4th generation Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture.
Supervisor Memory 
Protection Keys (PKS)12th generation Intel Core processor based on Alder Lake performance hybrid architecture, 4th 
Attestation Services for 
Intel® SGX3rd Generation Intel® Xeon® Scalable Processor Family based on Ice Lake microarchitecture.
Enqueue Stores: ENQCMD 
and ENQCMDS4th generation Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture.Table 5-2.  Instruction Set Extensions Introducti on in Intel® 64 and IA -32 Processors (Contd.)
Instruction Set Architecture Proc essor Generation IntroductionVol. 1 5-5INSTRUCTION SET SUMMARY
The following sections list instructions in each major group and subgroup. Given for each instruction is its 
mnemonic and descriptive names. When two or more mn emonics are given (for exam ple, CMOVA/CMOVNBE), they 
represent different mnemonics for the same instructio n opcode. Assemblers support redundant mnemonics for 
some instructions to make it easier to read code listi ngs. For instance, CMOVA (Conditional move if above) and 
CMOVNBE (Conditional move if not below or equal) repres ent the same condition. For detailed information about 
specific instructions, see the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, 
&2 D .
5.1 GENERAL-PURPOSE INSTRUCTIONS
The general-purpose instructions perform basic data move ment, arithmetic, logic, program flow, and string opera-
tions that programmers commonly use to write application and system software to run on Intel 64 and IA-32 processors. They operate on data contained in memory, in the general-purpose regist ers (EAX, EBX, ECX, EDX, 
EDI, ESI, EBP, and ESP) and in the EFLAGS register. They also operate on address information contained in 
memory, the general-purpose registers, and the segment registers (CS, DS, SS, ES, FS, and GS). 
This group of instructions includes the data transfer, bina ry integer arithmetic, decimal arithmetic, logic operations, 
shift and rotate, bit and byte operations, program control,  string, flag control, segment register operations, and 
miscellaneous subgroups. The sections that follow introduce each subgroup. 
For more detailed information on general purpose-inst ructions, see Chapter 7, “Programming With General-
Purpose Instructions.”
5.1.1 Data Transfer Instructions
The data transfer instructions move data between memo ry and the general-purpose and segment registers. They 
also perform specific operations such as conditional moves, stack access, and data conversion.Intel® TSX Suspend Load 
Address Tracking 
(TSXLDTRK)4th generation Intel® Xeon® Scalable Processor Fa mily based on Sapphire Rapids microarchitecture.
Intel® Advanced Matrix 
Extensions (Intel® AMX)
Includes CPUID Leaf 1EH, 
“TMUL Information Main 
Leaf”, and CPUID bits AMX-
BF16, AMX-TILE, and AMX-INT8.4th generation Intel® Xeon® Scalable Processor Fa mily based on Sapphire Rapids microarchitecture.
User Interrupts (UINTR) 4th generation In tel® Xeon® Scalable Processor Family base d on Sapphire Rapids microarchitecture.
IPI Virtualization 4th generation Intel® Xeon® Scalable Proc essor Family based on Sapphire Rapids microarchitecture.
AVX512-FP16, for the FP16 
Data Type4th generation Intel® Xeon® Scalable Processor Fa mily based on Sapphire Rapids microarchitecture.
NOTES:
1. Details on Key Locker can be found in the Intel Key Locker Specification here:
 https://software.intel.c om/content/www/us/en/develop/download/intel-key-locker-specification.html. 
2. Further details on TME-MK usage can be found here: 
https://software.intel.com /sites/default/files/manag ed/a5/16/Multi-Key-Total-Me mory-Encryption-Spec.pdf.
3. Alder Lake performance hybrid architecture does not support Intel® AVX-512. ISA features such as Intel® AVX, AVX-VNNI, Intel ® AVX2, 
and UMONITOR/UMWAIT/TPAUSE are supported.Table 5-2.  Instruction Set Extensions Introducti on in Intel® 64 and IA -32 Processors (Contd.)
Instruction Set Architecture Proc essor Generation Introduction5-6 Vol. 1INSTRUCTION SET SUMMARY
MOV Move data between general-purpose register s; move data between memory and general-
purpose or segment registers; move immediates to general-purpose registers.
CMOVE/CMOVZ Conditional move if equal/Conditional move if zero.
CMOVNE/CMOVNZ Conditional move if not equal/Conditional move if not zero.
CMOVA/CMOVNBE Conditional move if above/ Conditional move if not below or equal.
CMOVAE/CMOVNB Conditional move if above or equal/Conditional move if not below.
CMOVB/CMOVNAE Conditional move if below/ Conditional move if not above or equal.
CMOVBE/CMOVNA Conditional move if below or equal/Conditional move if not above.

CMOVG/CMOVNLE Conditional move if greate r/Conditional move if not less or equal.
CMOVGE/CMOVNL Conditional move if greate r or equal/Conditional move if not less.
CMOVL/CMOVNGE Conditional move if less/Co nditional move if not greater or equal.
CMOVLE/CMOVNG Conditional move if less or  equal/Conditional move if not greater.
CMOVC Conditional move if carry.
CMOVNC Conditional move if not carry.
CMOVO Conditional move if overflow.
CMOVNO Conditional move if not overflow.CMOVS Conditional move if sign (negative).
CMOVNS Conditional move if not sign (non-negative).
CMOVP/CMOVPE Conditional move if parity /Conditional move if parity even.
CMOVNP/CMOVPO Conditional move if not pa rity/Conditional move if parity odd.
XCHG Exchange.
BSWAP Byte swap.XADD Exchange and add.
CMPXCHG Compare and exchange.
CMPXCHG8B Compare and exchange 8 bytes.PUSH Push onto stack.
POP Pop off of stack.
PUSHA/PUSHAD Push general-purpose registers onto stack.POPA/POPAD Pop general-purpose registers from stack.
CWD/CDQ Convert word to doubleword/Convert doubleword to quadword.
CBW/CWDE Convert byte to word/Convert word to doubleword in EAX register.
MOVSX Move and sign extend.
MOVZX Move and zero extend.
5.1.2 Binary Arithmetic Instructions
The binary arithmetic instructions perform basic binary integer computations on byte , word, and doubleword inte-
gers located in memory and/or the general purpose registers.
ADCX Unsigned integer add with carry.
ADOX Unsigned integer add with overflow.
ADD Integer add.ADC Add with carry.
SUB Subtract.
SBB Subtract with borrow.IMUL Signed multiply.
MUL Unsigned multiply.
IDIV Signed divide.Vol. 1 5-7INSTRUCTION SET SUMMARY
DIV Unsigned divide.
INC Increment.DEC Decrement.
NEG Negate.
CMP Compare.
5.1.3 Decimal Arithmetic Instructions
The decimal arithmetic instructions perform decima l arithmetic on binary coded decimal (BCD) data.
DAA Decimal adjust after addition.
DAS Decimal adjust after subtraction.
AAA ASCII adjust after addition.AAS ASCII adjust after subtraction.
AAM ASCII adjust after multiplication.
AAD ASCII adjust before division.
5.1.4 Logical Instructions
The logical instructions perform basic AND, OR, XOR, and NOT logical operations on byte, word, and doubleword 
values.
AND Perform bitwise logical AND.OR Perform bitwise logical OR.
XOR Perform bitwise logical exclusive OR.
NOT Perform bitwise logical NOT.
5.1.5 Shift and Rotate Instructions
The shift and rotate instructions shift and rotate the bits in word and doubleword operands.SAR Shift arithmetic right.
SHR Shift logical right.
SAL/SHL Shift arithmetic left/Shift logical left.SHRD Shift right double.
SHLD Shift left double.
ROR Rotate right.ROL Rotate left.
RCR Rotate through carry right.
RCL Rotate through carry left.
5.1.6 Bit and Byte Instructions
Bit instructions test and modify individual bits in word and doubleword operands. Byte instructions set the value of 
a byte operand to indicate the status of flags in the EFLAGS register.
BT Bit test.
BTS Bit test and set.BTR Bit test and reset.
BTC Bit test and complement.
BSF Bit scan forward.5-8 Vol. 1INSTRUCTION SET SUMMARY
BSR Bit scan reverse.
SETE/SETZ Set byte if eq ual/Set byte if zero.
SETNE/SETNZ Set byte if not equal/Set byte if not zero.
SETA/SETNBE Set byte if above/Se t byte if not below or equal.
SETAE/SETNB/SETNC Set byte if above or equal/ Set byte if not below/Set byte if not carry.
SETB/SETNAE/SETC Set byte if below/Set byte if not above or equal/Set byte if carry.
SETBE/SETNA Set byte if below or  equal/Set byte if not above.
SETG/SETNLE Set byte if greater/ Set byte if not less or equal.
SETGE/SETNL Set byte if greater or equal/Set byte if not less.
SETL/SETNGE Set byte if less/Set byte if not greater or equal.
SETLE/SETNG Set byte if less or equal/Set byte if not greater.
SETS Set byte if sign (negative).
SETNS Set byte if not sign (non-negative).
SETO Set byte if overflow.
SETNO Set byte if not overflow.
SETPE/SETP Set byte if parity even/Set byte if parity.SETPO/SETNP Set byte if parity  odd/Set byte if not parity.
TEST Logical compare.
CRC32
1Provides hardware acceleration to calculate cyclic redundancy checks for fast and efficient 
implementation of data integrity protocols.
POPCNT2Calculates of number of bits set to 1 in the second operand (source) and returns the count 
in the first operand (a destination register).
5.1.7 Control Transfer Instructions
The control transfer instructions provide jump, conditiona l jump, loop, and call and return operations to control 
program flow.
JMP Jump.
JE/JZ Jump if equal/Jump if zero.JNE/JNZ Jump if not equal/Jump if not zero.
JA/JNBE Jump if above/Jump if not below or equal.
JAE/JNB Jump if above or equal/Jump if not below.JB/JNAE Jump if below/Jump if not above or equal.
JBE/JNA Jump if below or equal/Jump if not above.
JG/JNLE Jump if greater/Jump if not less or equal.JGE/JNL Jump if greater or equal/Jump if not less.
JL/JNGE Jump if less/Jump if not greater or equal.
JLE/JNG Jump if less or equal/Jump if not greater.JC Jump if carry.
JNC Jump if not carry.
JO Jump if overflow.JNO Jump if not overflow.
JS Jump if sign (negative).
JNS Jump if not sign (non-negative).
1. Processor support of CRC32 is enumerated by CPUID.01:ECX[SSE4.2] = 12. Processor support of PO PCNT is enumerated by CPUID.01:ECX[POPCNT] = 1Vol. 1 5-9INSTRUCTION SET SUMMARY
JPO/JNP Jump if parity odd/Jump if not parity.
JPE/JP Jump if parity even/Jump if parity.JCXZ/JECXZ Jump register CX zero/Jump register ECX zero.
LOOP Loop with ECX counter.
LOOPZ/LOOPE Loop with ECX and zero/Loop with ECX and equal.LOOPNZ/LOOPNE Loop with ECX and not zero/Loop with ECX and not equal.
CALL Call procedure.
RET Return.IRET Return from interrupt.
INT Software interrupt.
INTO Interrupt on overflow.BOUND Detect value out of range.
ENTER High-level procedure entry.
LEAVE High-level procedure exit.
5.1.8 String Instructions
The string instructions operate on strings of bytes,  allowing them to be moved to and from memory.
MOVS/MOVSB Move string/Move byte string.
MOVS/MOVSW Move string/Move word string.MOVS/MOVSD Move string/Move doubleword string.
CMPS/CMPSB Compare string/Compare byte string.
CMPS/CMPSW Compare string /Compare word string.
CMPS/CMPSD Compare string/Com pare doubleword string.
SCAS/SCASB Scan string/Scan byte string.
SCAS/SCASW Scan string/Scan word string.SCAS/SCASD Scan string/Scan doubleword string.
LODS/LODSB Load string/Load byte string.
LODS/LODSW Load string/Load word string.LODS/LODSD Load string/Load doubleword string.
STOS/STOSB Store string/Store byte string.
STOS/STOSW Store string/Store word string.STOS/STOSD Store string/Store doubleword string.
REP Repeat while ECX not zero.
REPE/REPZ Repeat while equal/Repeat while zero.REPNE/REPNZ Repeat while not equal/Repeat while not zero.
5.1.9 I/O Instructions
These instructions move data between the processor’s I/O ports and a register or memory.
IN Read from a port.
OUT Write to a port.INS/INSB Input string from port/Input byte string from port.
INS/INSW Input string from port/Input word string from port.
INS/INSD Input string from port/Input doubleword string from port.OUTS/OUTSB Output string to port/Output byte string to port.
OUTS/OUTSW Output string to port/Output word string to port.5-10 Vol. 1INSTRUCTION SET SUMMARY
OUTS/OUTSD Output string to port/Output doubleword string to port.
5.1.10 Enter and Leave Instructions
These instructions provide machine-language support for procedure calls in block-structured languages.
ENTER High-level procedure entry.LEAVE High-level procedure exit.
5.1.11 Flag Control (EFLAG) Instructions
The flag control instructions operate on the flags in the EFLAGS register.
STC Set carry flag.
CLC Clear the carry flag.CMC Complement the carry flag.
CLD Clear the direction flag.
STD Set direction flag.
LAHF Load flags into AH register.
SAHF Store AH register into flags.PUSHF/PUSHFD Push EFLAGS onto stack.
POPF/POPFD Pop EFLAGS from stack.
STI Set interrupt flag.CLI Clear the interrupt flag.
5.1.12 Segment Register Instructions
The segment register instructions allow far pointers (segme nt addresses) to be loaded into the segment registers.
LDS Load far pointer using DS.
LES Load far pointer using ES.LFS Load far pointer using FS.
LGS Load far pointer using GS.
LSS Load far pointer using SS.
5.1.13 Miscellaneous Instructions
The miscellaneous instructions provide such functions as lo ading an effective address, executing a “no-operation,” 
and retrieving processor identification information.
LEA Load effective address.
NOP No operation.UD Undefined instruction.
XLAT/XLATB Table lookup translation.
CPUID Processor identification.MOVBE
1Move data after swapping data bytes.
PREFETCHW Prefetch data into cache in anticipation of write.
PREFETCHWT1 Prefetch hint T1 with intent to write.
1. Processor support of MOVBE is enumerated by CPUID.01:ECX.MOVBE[bit 22] = 1.Vol. 1 5-11INSTRUCTION SET SUMMARY
CLFLUSH Flushes and invalidates a memory operand and its associated cache line from all levels of

CLFLUSH Flushes and invalidates a memory operand and its associated cache line from all levels of 
the processor’s cache hierarchy.
CLFLUSHOPT Flushes and invalidates a memory operand and its associated cache line from all levels of 
the processor’s cache hierarchy with optimized memory system throughput.
5.1.14 User Mode Extended St ate Save/Restore Instructions
XSAVE Save processor extended states to memory.
XSAVEC Save processor extended states with compaction to memory.
XSAVEOPT Save processor extended states to memory, optimized.XRSTOR Restore processor extended states from memory.
XGETBV Reads the state of an extended control register.
5.1.15 Random Number Generator Instructions
RDRAND Retrieves a random number generated from hardware.
RDSEED Retrieves a random number generated from hardware.
5.1.16 BMI1 and BMI2 Instructions
ANDN Bitwise AND of first source with inverted second source operands.BEXTR Contiguous bitwise extract.BLSI Extract lowest set bit.
BLSMSK Set all lower bits below first set bit to 1.
BLSR Reset lowest set bit.BZHI Zero high bits starting from specified bit position.
LZCNT Count the number of leading zero bits.
MULX Unsigned multiply withou t affecting arithmetic flags.
PDEP Parallel deposit of bits using a mask.
PEXT Parallel extraction of bits using a mask.
RORX Rotate right without affecting arithmetic flags.SARX Shift arithmetic right.
SHLX Shift logic left.
SHRX Shift logic right.TZCNT Count the number of trailing zero bits.
5.1.16.1  Detection of VEX-Encoded GPR In structions, LZCNT, TZCNT, and PREFETCHW
VEX-encoded general-purpose instructions do not operate on any vector registers. 
There are separate feature flags for the following subsets of  instructions that operate on general purpose registers, 
and the detection requirements for hardware support are:
CPUID.(EAX=07H, ECX=0H):EBX.B MI1[bit 3]: if 1 indicates the processor supports the first group of advanced bit 
manipulation extensions (ANDN, BE XTR, BLSI, BLSMSK, BLSR, TZCNT);
CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8 ]: if 1 indicates the processor supports the second group of advanced 
bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX);
CPUID.EAX=80000001H:ECX.LZCNT[bit 5]: if 1 indicate s the processor supports the LZCNT instruction.
CPUID.EAX=80000001H:ECX.PREFTEHCHW[bit 8]: if 1 indica tes the processor supports the PREFTEHCHW instruc-
tion. CPUID.(EAX=07H, ECX= 0H):ECX.PREFTEHCHWT1[bit 0]: if 1 indi cates the processor supports the PREFT-
EHCHWT1 instruction.5-12 Vol. 1INSTRUCTION SET SUMMARY
5.2 X87 FPU INSTRUCTIONS
The x87 FPU instructions are executed by the processor’s x87 FPU. These instructions operate on floating-point, 
integer, and binary-coded decimal (BCD) operands. For more detail on x87 FPU instructions, see Chapter 8, 
“Programming with the x87 FPU.”
These instructions are divided into the following subgroups: data transfer, lo ad constants, and FPU control instruc-
tions. The sections that follow introduce each subgroup.
5.2.1 X87 FPU Data Transfer Instructions
The data transfer instructions move floating-point, in teger, and BCD values betw een memory and the x87 FPU 
registers. They also perform conditional move operations on floating-point operands.
FLD Load floating-point value.
FST Store floating-point value.FSTP Store floating-point value and pop.
FILD Load integer.
FIST Store integer.
FISTP
1Store integer and pop.
FBLD Load BCD.FBSTP Store BCD and pop.
FXCH Exchange registers.
FCMOVE Floating-point conditional move if equal.FCMOVNE Floating-point conditional move if not equal.
FCMOVB Floating-point conditional move if below.
FCMOVBE Floating-point conditional move if below or equal.FCMOVNB Floating-point conditional move if not below.
FCMOVNBE Floating-point conditional move if not below or equal.
FCMOVU Floating-point conditional move if unordered.FCMOVNU Floating-point conditional move if not unordered.
5.2.2 X87 FPU Basic Arithmetic Instructions
The basic arithmetic instructions perform basic arithmetic operations on floating-point and integer operands.
FADD Add floating-point.
FADDP Add floating-point and pop.FIADD Add integer.
FSUB Subtract floating-point.
FSUBP Subtract floating-point and pop.FISUB Subtract integer.
FSUBR Subtract floating-point reverse.
FSUBRP Subtract floating-point reverse and pop.FISUBR Subtract integer reverse.
FMUL Multiply floating-point.
FMULP Multiply floating-point and pop.FIMUL Multiply integer.
FDIV Divide floating-point.
1. SSE3 provides an instruction FISTTP for integer conversion.Vol. 1 5-13INSTRUCTION SET SUMMARY
FDIVP Divide floating-point and pop.
FIDIV Divide integer.FDIVR Divide floating-point reverse.
FDIVRP Divide floating-point reverse and pop.
FIDIVR Divide integer reverse.FPREM Partial remainder.
FPREM1 IEEE partial remainder.
FABS Absolute value.FCHS Change sign.
FRNDINT Round to integer.
FSCALE Scale by power of two.FSQRT Square root.
FXTRACT Extract exponent and significand.
5.2.3 X87 FPU Comparison Instructions
The compare instructions examine or compare floating-point or integer operands.
FCOM Compare floating-point.
FCOMP Compare floating-point and pop.
FCOMPP Compare floating-point and pop twice.FUCOM Unordered compare floating-point.
FUCOMP Unordered compare floating-point and pop.
FUCOMPP Unordered compare floating-point and pop twice.FICOM Compare integer.
FICOMP Compare integer and pop.
FCOMI Compare floating-point and set EFLAGS.FUCOMI Unordered compare floating-point and set EFLAGS.
FCOMIP Compare floating-point, set EFLAGS, and pop.
FUCOMIP Unordered compare floating-point, set EFLAGS, and pop.FTST Test floating-point (compare with 0.0).
FXAM Examine floating-point.
5.2.4 X87 FPU Transcendental Instructions
The transcendental instructions perform basic trigonometri c and logarithmic operations on floating-point oper-
ands.
FSIN Sine.
FCOS Cosine.
FSINCOS Sine and cosine.FPTAN Partial tangent.
FPATAN Partial arctangent.
F2XM1 2
x − 1.
FYL2X y ∗log2x.
FYL2XP1 y ∗log2(x+1).5-14 Vol. 1INSTRUCTION SET SUMMARY
5.2.5 X87 FPU Load Co nstants Instructions
The load constants instructions load common constants, such as π, into the x87 floating-point registers.
FLD1 Load +1.0.
FLDZ Load +0.0.FLDPI Load π.
FLDL2E Load log
2e.
FLDLN2 Load loge2.
FLDL2T Load log210.
FLDLG2 Load log102.
5.2.6 X87 FPU Control Instructions
The x87 FPU control instructions operate on the x87 FPU register stack and save and restore the x87 FPU state.
FINCSTP Increment FPU register stack pointer.
FDECSTP Decrement FPU register stack pointer.FFREE Free floating-point register.
FINIT Initialize FPU after checking error conditions.
FNINIT Initialize FPU without checking error conditions.FCLEX Clear floating-point exception flags after checking for error conditions.
FNCLEX Clear floating-point exception flags without checking for error conditions.
FSTCW Store FPU control word after checking error conditions.FNSTCW Store FPU control word without checking error conditions.
FLDCW Load FPU control word.
FSTENV Store FPU environment after checking error conditions.FNSTENV Store FPU environment with out checking error conditions.
FLDENV Load FPU environment.
FSAVE Save FPU state after checking error conditions.FNSAVE Save FPU state without checking error conditions.
FRSTOR Restore FPU state.
FSTSW Store FPU status word after checking error conditions.FNSTSW Store FPU status word with out checking error conditions.
WAIT/FWAIT Wait for FPU.
FNOP FPU no operation.
5.3 X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS
Two state management instructions were introduced into the IA-32 architecture with the Pentium II processor 
family:
FXSAVE Save x87 FPU and SIMD state.
FXRSTOR Restore x87 FPU and SIMD state.
Initially, these instructions operated only on the x87 FPU (and MMX) registers to perform a fast save and restore, 
respectively, of the x87 FPU and MMX state. With th e introduction of SSE extensions in the Pentium III processor 
family, these instructions were expanded to also save an d restore the state of the XMM and MXCSR registers. Intel 
64 architecture also supports these instructions.
See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for more detail.Vol. 1 5-15INSTRUCTION SET SUMMARY
5.4 MMX INSTRUCTIONS
Four extensions have been introduced into the IA-32 arch itecture to permit IA-32 processors to perform single-
instruction multiple-data (SIMD) operations. These extens ions include the MMX technology, SSE extensions, SSE2 
extensions, and SSE3 extensions. For a discussion that puts SIMD instructions in their historical context, see Section 2.2.7, “SIMD Instructions.”
MMX instructions operate on packed byte, word, doublewo rd, or quadword integer operands contained in memory, 
in MMX registers, and/or in general-purpose registers.  For more detail on these instructions, see Chapter 9, 
“Programming with Intel® MMX™ Technology.” 
MMX instructions can only be executed on Intel 64 and IA-32 processors that support the MMX technology. Support 
for these instructions can be detected with the CPUID inst ruction. See the description of the CPUID instruction in

for these instructions can be detected with the CPUID inst ruction. See the description of the CPUID instruction in 
Chapter 3, “Instruction Set Reference, A-L,” of the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A.
MMX instructions are divided into the following subgroups: data transfer, conversion, packed arithmetic, compar-
ison, logical, shift and rotate, and state management instructions. The sections that follow introduce each 
subgroup.
5.4.1 MMX Data Transfer Instructions
The data transfer instructions move doubleword and quadword operands between MMX registers and between 
MMX registers and memory.
MOVD Move doubleword.
MOVQ Move quadword.
5.4.2 MMX Conversion Instructions
The conversion instructions pack and unpack bytes, words, and doublewords
PACKSSWB Pack words into bytes with signed saturation.
PACKSSDW Pack doublewords into words with signed saturation.PACKUSWB Pack words into bytes with unsigned saturation.
PUNPCKHBW Unpack high-order bytes.
PUNPCKHWD Unpack high-order words.PUNPCKHDQ Unpack high-order doublewords.
PUNPCKLBW Unpack low-order bytes.
PUNPCKLWD Unpack low-order words.PUNPCKLDQ Unpack low-order doublewords.
5.4.3 MMX Packed Arithmetic Instructions
The packed arithmetic instructions perform packed intege r arithmetic on packed byte, word, and doubleword inte-
gers.
PADDB Add packed byte integers.
PADDW Add packed word integers.
PADDD Add packed doubleword integers.
PADDSB Add packed signed byte in tegers with signed saturation.
PADDSW Add packed signed word integers with signed saturation.
PADDUSB Add packed unsigned byte integers with unsigned saturation.
PADDUSW Add packed unsigned word integers with unsigned saturation.PSUBB Subtract packed byte integers.
PSUBW Subtract packed word integers.5-16 Vol. 1INSTRUCTION SET SUMMARY
PSUBD Subtract packed doubleword integers.
PSUBSB Subtract packed signed byte integers with signed saturation.
PSUBSW Subtract packed signed word integers with signed saturation.
PSUBUSB Subtract packed unsigned byte integers with unsigned saturation.
PSUBUSW Subtract packed unsigned word integers with unsigned saturation.
PMULHW Multiply packed signed word  integers and store high result.
PMULLW Multiply packed signed word  integers and store low result.
PMADDWD Multiply and add packed word integers.
5.4.4 MMX Comparison Instructions
The compare instructions compare pack ed bytes, words, or doublewords.
PCMPEQB Compare packed bytes for equal.
PCMPEQW Compare packed words for equal.
PCMPEQD Compare packed doublewords for equal.PCMPGTB Compare packed signed byte integers for greater than.PCMPGTW Compare packed signed word integers for greater than.
PCMPGTD Compare packed signed doub leword integers for greater than.
5.4.5 MMX Logical Instructions
The logical instructions perform AND, AND NOT, OR, and XOR operations on quadword operands.
PAND Bitwise logical AND.
PANDN Bitwise logical AND NOT.
POR Bitwise logical OR.PXOR Bitwise logical exclusive OR.
5.4.6 MMX Shift and Rotate Instructions
The shift and rotate instructions shift and rotate packed bytes, words, or doublewords, or quadwords in 64-bit 
operands.
PSLLW Shift packed words left logical.
PSLLD Shift packed doublewords left logical.
PSLLQ Shift packed quadword left logical.PSRLW Shift packed words right logical.
PSRLD Shift packed doublewords right logical.
PSRLQ Shift packed quadword right logical.PSRAW Shift packed words right arithmetic.
PSRAD Shift packed doublewords right arithmetic.
5.4.7 MMX State Management Instructions
The EMMS instruction clears the MMX state from the MMX registers.
EMMS Empty MMX state.Vol. 1 5-17INSTRUCTION SET SUMMARY
5.5 INTEL® SSE INSTRUCTIONS
Intel SSE instructions represent an extension of the SI MD execution model introduced with the MMX technology. 
For more detail on these instructions, see Chapter 10, “Programming with Intel® Streaming SIMD Extensions 
Intel SSE instructions can only be executed on Intel 64 and IA-32 processors that support Intel SSE extensions. 
Support for these instructions can be detected with th e CPUID instruction. See the description of the CPUID 
instruction in Chapter 3, “Instruction  Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 2A.
Intel SSE instructions are divided into four subgroups (n ote that the first subgroup has subordinate subgroups of 
its own):
•SIMD single precision floating-point instru ctions that operate on the XMM registers.
•MXCSR state management instructions.
•64-bit SIMD integer instructions that operate on the MMX registers.
•Cacheability control, prefetch, and instruction ordering instructions.
The following sections provide an overview of these groups.
5.5.1 Intel® SSE SIMD Single Prec ision Floating-Point Instructions
These instructions operate on packed and scalar single precision floating-point values located in XMM registers 
and/or memory. This subgroup is further divided into th e following subordinate subgroups: data transfer, packed 
arithmetic, comparison, logical, shuffle and unpack, and conversion instructions.
5.5.1.1  Intel® SSE Data Transfer Instructions
Intel SSE data transfer instructions move packed and sca lar single precision floating-point operands between XMM 
registers and between XMM registers and memory.
MOVAPS Move four aligned packed single precisio n floating-point values between XMM registers or 
between an XMM register and memory.
MOVUPS Move four unaligned packed single precision floating-point values between XMM registers 
or between an XMM register and memory.
MOVHPS Move two packed single precision floating-point values to and from the high quadword of 
an XMM register and memory.
MOVHLPS Move two packed single precision floating-p oint values from the high quadword of an XMM 
register to the low quadword of another XMM register.
MOVLPS Move two packed single precision floating-p oint values to and from the low quadword of an 
XMM register and memory.
MOVLHPS Move two packed single precision floating-p oint values from the low quadword of an XMM 
register to the high quadwo rd of another XMM register.
MOVMSKPS Extract sign mask from four packed single precision floating-point values.
MOVSS Move scalar single precision floating-poi nt value between XMM registers or between an 
5.5.1.2  Intel® SSE Packed Arithmetic Instructions
Intel SSE packed arithmetic instructions perform packed  and scalar arithmetic operations on packed and scalar 
single precision floating-point operands.
ADDPS Add packed single precision floating-point values.ADDSS Add scalar single precision floating-point values.
SUBPS Subtract packed single pr ecision floating-point values.
SUBSS Subtract scalar single precision floating-point values.5-18 Vol. 1INSTRUCTION SET SUMMARY
MULPS Multiply packed single precision floating-point values.
MULSS Multiply scalar single precision floating-point values.DIVPS Divide packed single precision floating-point values.
DIVSS Divide scalar single precision floating-point values.
RCPPS Compute reciprocals of packed single precision floating-point values.RCPSS Compute reciprocal of scalar single precision floating-point values.
SQRTPS Compute square roots of packed single precision floating-point values.
SQRTSS Compute square root of scalar single precision floating-point values.RSQRTPS Compute reciprocals of square roots of packed single precision floating-point values.
RSQRTSS Compute reciprocal of square root of scalar single precision floating-point values.
MAXPS Return maximum packed single precision floating-point values.MAXSS Return maximum scalar single precision floating-point values.
MINPS Return minimum packed single precision floating-point values.
MINSS Return minimum scalar single precision floating-point values.
5.5.1.3  Intel® SSE Comparison Instructions
Intel SSE compare instructions co mpare packed and scalar single precision floating-point operands.
CMPPS Compare packed single precision floating-point values.CMPSS Compare scalar single precision floating-point values.
COMISS Perform ordered comparison of scalar single precision floating-point values and set flags in 
EFLAGS register.
UCOMISS Perform unordered comparison of scalar sing le precision floating-point values and set flags 
in EFLAGS register.
5.5.1.4  Intel® SSE Logical Instructions
Intel SSE logical instructions perform bitwise AND, AND NOT, OR, and XOR operations on packed single precision 
floating-point operands.
ANDPS Perform bitwise logical AND of packed single precision floating-point values.
ANDNPS Perform bitwise logical AND NOT of pack ed single precision floating-point values.
ORPS Perform bitwise logical OR of packed  single precision floating-point values.
XORPS Perform bitwise logical XOR of packed single precision floating-point values.
5.5.1.5  Intel® SSE Shuffle and Unpack Instructions
Intel SSE shuffle and unpack instructions shuffle or interleave  single precision floating-point values in packed single 
precision floating-point operands.

SHUFPS Shuffles values in packed single precision floating-point operands.
UNPCKHPS Unpacks and interleaves th e two high-order values from two single precision floating-point 
operands.
UNPCKLPS Unpacks and interleaves the two low-order values from two single precision floating-point 
operands.
5.5.1.6  Intel® SSE Conversion Instructions
Intel SSE conversion instructions convert packed and individual doubleword integers into packed and scalar single 
precision floating-point values and vice versa.
CVTPI2PS Convert packed doubleword integers to packed single precision floating-point values.
CVTSI2SS Convert doubleword integer to scalar single precision floating-point value.Vol. 1 5-19INSTRUCTION SET SUMMARY
CVTPS2PI Convert packed single precision floating -point values to packed doubleword integers.
CVTTPS2PI Convert with truncation packed single pr ecision floating-point values to packed double-
word integers.
CVTSS2SI Convert a scalar single precision fl oating-point value to a doubleword integer.
CVTTSS2SI Convert with truncation a scalar single precision floating-point value to a scalar double-
word integer.
5.5.2 Intel® SSE MXCSR State Management Instructions
MXCSR state management instructions allow saving and restoring the state of the MXCSR control and status 
register.
LDMXCSR Load MXCSR register.STMXCSR Save MXCSR register state.
5.5.3 Intel® SSE 64-Bit SIMD Integer Instructions
These Intel SSE 64-bit SIMD integer instructions perform addi tional operations on packed bytes, words, or double-
words contained in MMX registers. They represent enhanc ements to the MMX instruction set described in Section 
5.4, “MMX Instructions.”
PAVGB Compute a verage of packed unsigned byte integers.
PAVGW Compute a verage of packed unsigned word integers.
PEXTRW Extract word.PINSRW Insert word.
PMAXUB Maximum of packed unsigned byte integers.PMAXSW Maximum of packed signed word integers.
PMINUB Minimum of packed unsigned byte integers.
PMINSW Minimum of packed signed word integers.PMOVMSKB Move byte mask.
PMULHUW Multiply packed unsigned integers and store high result.
PSADBW Compute sum of absolute differences.PSHUFW Shuffle packed integer word in MMX register.
5.5.4 Intel® SSE Cacheability Control, Pr efetch, and Instruction Ordering Instructions
The cacheability control instructions provide control over the caching of non-temporal data when storing data from 
the MMX and XMM registers to memory. The PREFETCH h allows data to be prefetched to a selected cache level. The 
SFENCE instruction controls instruction ordering on store operations.
MASKMOVQ Non-temporal store of se lected bytes from an MMX register into memory.
MOVNTQ Non-temporal store of quadword  from an MMX register into memory.
MOVNTPS Non-temporal store of four packed single  precision floating-point values from an XMM 
register into memory.
PREFETCH h Load 32 or more of bytes from memory to a selected level of the processor’s cache hier-
archy.
SFENCE Serializes store operations.
5.6 INTEL® SSE2 INSTRUCTIONS
Intel SSE2 extensions represent an extension of the SI MD execution model introduced with MMX technology and 
the Intel SSE extensions. Intel SSE2 instructions operate on packed double precision floating-point operands and 5-20 Vol. 1INSTRUCTION SET SUMMARY
on packed byte, word, doubleword, and quadword operands located in the XMM registers. For more detail on these 
instructions, see Chapter 11, “Programming with Intel® Streaming SIMD Extensions 2 (Intel® SSE2).”
Intel SSE2 instructions can only be executed on Intel 64 and IA-32 processors that support the Intel SSE2 exten-
sions. Support for these instructions can be detected with the CPUID instruction. See the description of the CPUID instruction in Chapter 3, “Instruction Set Reference, A-L,” of the Intel
® 64 and IA-32 Architectures Software Devel-
These instructions are divided into four  subgroups (note that the first subgrou p is further divided into subordinate 
subgroups):
•Packed and scalar double precision floating-point instructions.
•Packed single precision floating-point conversion instructions.
•128-bit SIMD integer instructions.
•Cacheability-control and instruction ordering instructions.
The following sections give an overview of each subgroup.
5.6.1 Intel® SSE2 Packed an d Scalar Double Precision Floating-Point Instructions
Intel SSE2 packed and scalar double precision floating-point  instructions are divided into the following subordinate 
subgroups: data movement, arithmetic, comparison, conversi on, logical, and shuffle operations on double preci-
sion floating-point operands. These are introduced in the sections that follow.
5.6.1.1  Intel® SSE2 Data Movement Instructions
Intel SSE2 data movement instructions move double pr ecision floating-point data between XMM registers and 
between XMM registers and memory.
MOVAPD Move two aligned packed double precision floating-point values between XMM registers or 
MOVUPD Move two unaligned packed double precis ion floating-point values between XMM registers 
MOVHPD Move high packed double precision floating -point value to and from the high quadword of 
MOVLPD Move low packed single precision floating-p oint value to and from the low quadword of an 
MOVMSKPD Extract sign mask from two packed  double precision floating-point values.
MOVSD Move scalar double precision floating-point value between XMM registers or between an 
5.6.1.2  Intel® SSE2 Packed Arithmetic Instructions
The arithmetic instructions perform addition, subtraction, multiply, divide, square root, and maximum/minimum 
operations on packed and scalar double precision floating-point operands.
ADDPD Add packed double precision floating-point values.
ADDSD Add scalar double precision floating-point values.SUBPD Subtract packed double precision floating-point values.
SUBSD Subtract scalar double precision floating-point values.
MULPD Multiply packed double precision floating-point values.MULSD Multiply scalar double precision floating-point values.
DIVPD Divide packed double precision floating-point values.
DIVSD Divide scalar double precision floating-point values.SQRTPD Compute packed square roots of packed  double precision floating-point values.
SQRTSD Compute scalar square root of scalar double precision floating-point values.Vol. 1 5-21INSTRUCTION SET SUMMARY
MAXPD Return maximum packed double precision floating-point values.
MAXSD Return maximum scalar double precision floating-point values.MINPD Return minimum packed double precision floating-point values.
MINSD Return minimum scalar double precision floating-point values.
5.6.1.3  Intel® SSE2 Logical Instructions
Intel SSE2 logical instructions perform AND, AND NOT,  OR, and XOR operations on packed double precision 
floating-point values.
ANDPD Perform bitwise logical AND of packed  double precision floating-point values.
ANDNPD Perform bitwise logical AND NOT of pack ed double precision floating-point values.
ORPD Perform bitwise logical OR of packed double precision floating-point values.
XORPD Perform bitwise logical XOR of packed double precision floating-point values.
5.6.1.4  Intel® SSE2 Compare Instructions
Intel SSE2 compare instructions compare packed and scalar double precision floating-point values and return the 
results of the comparison either to the destination operand or to the EFLAGS register.
CMPPD Compare packed double precision floating-point values.CMPSD Compare scalar double precision floating-point values.
COMISD Perform ordered comparison of scalar double  precision floating-point values and set flags 
UCOMISD Perform unordered comparison of scalar do uble precision floating-point values and set 
flags in EFLAGS register.
5.6.1.5  Intel® SSE2 Shuffle and Unpack Instructions
Intel SSE2 shuffle and unpack instructions shuffle or interl eave double precision floating-point values in packed 
double precision floating-point operands.
SHUFPD Shuffles values in packed double precision floating-point operands.
UNPCKHPD Unpacks and interleaves th e high values from two packed double precision floating-point 
operands.
UNPCKLPD Unpacks and interleaves the low values fr om two packed double precision floating-point 
operands.
5.6.1.6  Intel® SSE2 Conversion Instructions
Intel SSE2 conversion instructions convert packed and individual doubleword integers into packed and scalar 
double precision floating-point values and vice versa. Th ey also convert between packed and scalar single precision 
and double precision floating-point values.
CVTPD2PI Convert packed double precision floating-point values to packed doubleword integers.
CVTTPD2PI Convert with truncation packed double precision floating-point values to packed double-
CVTPI2PD Convert packed doubleword integers to packed double precision floating-point values.

operands.
operands.
CVTPD2DQ Convert packed double precision floating-point values to packed doubleword integers.
CVTTPD2DQ Convert with truncation packed double precision floating-point values to packed double-
CVTDQ2PD Convert packed doubleword integers to packed double precision floating-point values.
CVTPS2PD Convert packed single precision floating-poi nt values to packed double precision floating-
point values.5-22 Vol. 1INSTRUCTION SET SUMMARY
CVTPD2PS Convert packed double precision floating-point values to packed single precision floating-
point values.
CVTSS2SD Convert scalar single precision floating-point values to scalar double precision floating-
CVTSD2SS Convert scalar double precision floating-point values to scalar single precision floating-
CVTSD2SI Convert scalar double precision floa ting-point values to a doubleword integer.
CVTTSD2SI Convert with truncation scalar double precision floating-point values to scalar doubleword 
integers.
CVTSI2SD Convert doubleword integer to scala r double precision floating-point value.
5.6.2 Intel® SSE2 Packed Single Precision Floating-Point Instructions
Intel SSE2 packed single precision floating-point instruct ions perform conversion operations on single precision 
floating-point and integer operands. These instructions re present enhancements to the Intel SSE single precision 
floating-point instructions.
CVTDQ2PS Convert packed doubleword integers to packed single precision floating-point values.
CVTPS2DQ Convert packed single precision floating -point values to packed doubleword integers.
CVTTPS2DQ Convert with truncation packed single prec ision floating-point values to packed doubleword 
integers.
5.6.3 Intel® SSE2 128-Bit SIMD Integer Instructions
Intel SSE2 SIMD integer instructions perform additional operations on packed words,  doublewords, and quadwords 
contained in XMM and MMX registers.
MOVDQA Move aligned double quadword.
MOVDQU Move unaligned double quadword.MOVQ2DQ Move quadword integer from MMX to XMM registers.
MOVDQ2Q Move quadword integer from XMM to MMX registers.
PMULUDQ Multiply packed unsigned doubleword integers.PADDQ Add packed quadword integers.
PSUBQ Subtract packed quadword integers.
PSHUFLW Shuffle packed low words.PSHUFHW Shuffle packed high words.
PSHUFD Shuffle packed doublewords.
PSLLDQ Shift double quadword left logical.PSRLDQ Shift double quadword right logical.
PUNPCKHQDQ Unpack high quadwords.
PUNPCKLQDQ Unpack low quadwords.
5.6.4 Intel® SSE2 Cacheability Control and Ordering Instructions
Intel SSE2 cacheability control instructions provide additi onal operations for caching of non-temporal data when 
storing data from XMM registers to memory. LFENCE and MF ENCE provide additional control of instruction ordering 
on store operations.
CLFLUSH See Section 5.1.13.LFENCE Serializes load operations.
MFENCE Serializes load and store operations.
PAUSE Improves the performance of “spin-wait loops”.Vol. 1 5-23INSTRUCTION SET SUMMARY
MASKMOVDQU Non-temporal store of selected bytes from an XMM register into memory.
MOVNTPD Non-temporal store of two packed double precision floating-point values from an XMM 
MOVNTDQ Non-temporal store of double quadword from an XMM register into memory.
MOVNTI Non-temporal store of a doubleword fr om a general-purpose register into memory.
5.7 INTEL® SSE3 INSTRUCTIONS
The Intel SSE3 extensions offers 13 instructions that a ccelerate performance of Streaming SIMD Extensions tech-
nology, Streaming SIMD Extensions 2 te chnology, and x87-FP math capabilities.  These instructions can be grouped 
into the following categories:
•One x87 FPU instruction used  in integer conversion.
•One SIMD integer instruction that addresses unaligned data loads.
•Two SIMD floating-point packed ADD/SUB instructions.
•Four SIMD floating-point horizontal ADD/SUB instructions.
•Three SIMD floating-point LOAD /MOVE/DUPLICATE instructions.
•Two thread synchronization instructions.
Intel SSE3 instructions can only be executed on Intel 64  and IA-32 processors that support Intel SSE3 extensions. 
The sections that follow describe each subgroup.
5.7.1 Intel® SSE3 x87-FP Integer Conversion Instruction
FISTTP Behaves like the FISTP instruction but uses truncation, irrespective of the rounding mode 
specified in the floating-point control word (FCW).
5.7.2 Intel® SSE3 Specialized 128-Bi t Unaligned Data Load Instruction
LDDQU Special 128-bit unaligned load designed to avoid cache line splits.
5.7.3 Intel® SSE3 SIMD Floating-Point Packed ADD/SUB Instructions
ADDSUBPS Performs single precision addition on the second and fourth pairs of 32-bit data elements 
within the operands; single precision subtraction on the first and third pairs.
ADDSUBPD Performs double precision addition on the second pair of quadwords, and double precision 
subtraction on the first pair.
5.7.4 Intel® SSE3 SIMD Floating-Poi nt Horizontal ADD/SUB Instructions
HADDPS Performs a single precision addition on co ntiguous data elements. The first data element of 
the result is obtained by adding the first and second elements of the first operand; the 
second element by adding the third and fourth elements of the first operand; the third by 
adding the first and second elements of the se cond operand; and the fourth by adding the 
third and fourth elements of the second operand.
HSUBPS Performs a single precision subtraction on contiguous data elements. The first data 
element of the result is obtained by subtra cting the second element of the first operand 
from the first element of the first operand; the second element by subtracting the fourth 
element of the first operand from the third element of the first operand; the third by 5-24 Vol. 1INSTRUCTION SET SUMMARY
subtracting the second element of the second operand from the first element of the second 
operand; and the fourth by subtracting the fo urth element of the second operand from the 
third element of the second operand.
HADDPD Performs a double precision addition on contiguous data elements. The first data element 
of the result is obtained by adding the first and second elements of the first operand; the 
second element by adding the first and second elements of the second operand.
HSUBPD Performs a double precision subtraction on contiguous data elements. The first data 
from the first element of the first operand; the second element by subtracting the second 
element of the second operand from th e first element of the second operand.
5.7.5 Intel® SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions
MOVSHDUP Loads/moves 128 bits; duplicating th e second and fourth 32-bit data elements.
MOVSLDUP Loads/moves 128 bits; duplicating the first and third 32-bit data elements.
MOVDDUP Loads/moves 64 bits (bits[63:0] if the source  is a register) and returns the same 64 bits in 
both the lower and upper halves of the 128-bit result register; duplicates the 64 bits from 
the source.
5.7.6 Intel® SSE3 Agent Sy nchronization Instructions
MONITOR Sets up an address range used to monitor write-back stores.
MWAIT Enables a logical processor to enter into an optimized state while waiting for a write-back 
store to the address range set up by the MONITOR instruction.
5.8 SUPPLEMENTAL STREAMING SIMD EXTENSIONS 3 (SSSE3) INSTRUCTIONS
SSSE3 provide 32 instructions (represented by 14 mnemonics) to accelerate computations on packed integers. 
These include:
•Twelve instructions that perform horizontal addition or subtraction operations.
•Six instructions that evaluate absolute values.
•Two instructions that perform multiply and add operat ions and speed up the evaluation of dot products.
•Two instructions that accelerate packed-integer multip ly operations and produce integer values with scaling.
•Two instructions that perform a byte-wise, in-place s huffle according to the second shuffle control operand.
•Six instructions that negate packed integers in the destination operand if the signs of the corresponding 
element in the source operand is less than zero.
•Two instructions that align data from the composite of two operands.
SSSE3 instructions can only be executed on Intel 64 an d IA-32 processors that support SSSE3 extensions. Support 
Chapter 3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A.
5.8.1 Horizontal Addition/Subtraction
PHADDW Adds two adjacent, signed 16-bit integers  horizontally from the source and destination

Volume 2A.
PHADDW Adds two adjacent, signed 16-bit integers  horizontally from the source and destination 
operands and packs the signed 16-bit results to the destination operand.
PHADDSW Adds two adjacent, signed 16-bit integers  horizontally from the source and destination 
operands and packs the signed, saturated 16-bit results to the destination operand.Vol. 1 5-25INSTRUCTION SET SUMMARY
PHADDD Adds two adjacent, signed 32-bit integers  horizontally from the source and destination 
operands and packs the signed 32-bit results to the destination operand.
PHSUBW Performs horizontal subtraction on each adjacent pair of 16-bit signed integers by 
subtracting the most significant word from the least significant word of each pair in the 
source and destination operands. The signed 16-bit results are packed and written to the destination operand.
PHSUBSW Performs horizontal subtraction on each adjacent pair of 16-bit signed integers by 
source and destination operands. The signed, saturated 16-bit results are packed and 
written to the destination operand.
PHSUBD Performs horizontal subtraction on each adjacent pair of 32-bit signed integers by 
subtracting the most significant doubleword from  the least significant double word of each 
pair in the source and destination operands. The signed 32-bit results are packed and 
5.8.2 Packed Absolute Values
PABSB Computes the absolute value of each signed byte data element.
PABSW Computes the absolute value of each signed 16-bit data element.
PABSD Computes the absolute value of each signed 32-bit data element. 
5.8.3 Multiply and Add Packed Signed and Unsigned Bytes
PMADDUBSW Multiplies each unsigned byte value with  the corresponding signed byte value to produce 
an intermediate, 16-bit signed integer. Each adjacent pair of 16-bit signed values are 
added horizontally. The signed, saturated 16-bit results are packed to the destination operand.
5.8.4 Packed Multiply High with Round and Scale
PMULHRSW Multiplies vertically each signed 16-b it integer from the destination operand with the 
corresponding signed 16-bit integer of the so urce operand, producing intermediate, signed 
32-bit integers. Each intermediate 32-bit integer is truncated to the 18 most significant 
bits. Rounding is always performed by adding 1 to the least significant bit of the 18-bit 
intermediate result. The final result is obtained by selecting the 16 bits immediately to the 
right of the most significant bit of each 18-bit  intermediate result and packed to the desti-
nation operand.
5.8.5 Packed Shuffle Bytes
PSHUFB Permutes each byte in place, according to a shuffle control mask. The least significant 
three or four bits of each shuffle control byte of the control mask form the shuffle index. The shuffle mask is unaffected. If the most signif icant bit (bit 7) of a shuffle control byte is 
set, the constant zero is written in the result byte.
5.8.6 Packed Sign
PSIGNB/W/D Negates each signed integer element of the destination operand if the sign of the corre-
sponding data element in the source operand is less than zero.5-26 Vol. 1INSTRUCTION SET SUMMARY
5.8.7 Packed Align Right
PALIGNR Source operand is appended after the de stination operand forming an intermediate value 
of twice the width of an operand. The result is extracted from the intermediate value into 
the destination operand by selecting the 128-bit  or 64-bit value that are right-aligned to 
the byte offset specified by the immediate value.
5.9 INTEL® SSE4 INSTRUCTIONS
Intel Streaming SIMD Extensions 4 (Intel SSE4) introduces  54 new instructions. 47 of the Intel SSE4 instructions 
are referred to as Intel SSE4.1 in this document, and 7 new Intel SSE4 instructions are re ferred to as Intel SSE4.2. 
Intel SSE4.1 is targeted to improve the performance of media, imaging, and 3D workloads. Intel SSE4.1 adds 
instructions that improve compiler vectorization and signif icantly increase support for packed dword computation. 
The technology also provides a hint that can improve memory throughput when reading from uncacheable WC 
memory type.
The 47 Intel SSE4.1 instructions include:
•Two instructions perform packed dword multiplies.
•Two instructions perform floating-point dot products with input/output selects.
•One instruction performs a load with a streaming hint.
•Six instructions simplify packed blending.
•Eight instructions expand support for packed integer MIN/MAX.
•Four instructions support floating-point round with se lectable rounding mode and precision exception override.
•Seven instructions improve data insertion and extractions from XMM registers
•Twelve instructions improve packed integer format conversions (sign and zero extensions).
•One instruction improves SAD (sum absolute difference) generation for small block sizes.
•One instruction aids horizontal searching operations.
•One instruction improves masked comparisons.
•One instruction adds qword packed equality comparisons.
•One instruction adds dword packing with unsigned saturation.
The Intel SSE4.2 instructions operating on XMM registers include:
•String and text processing that can take advantage of single-instruction multiple-data programming 
techniques.
•A SIMD integer instruction that enhances the capabilit y of the 128-bit integer SIMD capability in SSE4.1.
5.10 INTEL® SSE4.1 INSTRUCTIONS
Intel SSE4.1 instructions can use an XMM register as a so urce or destination. Programming Intel SSE4.1 is similar 
to programming 128-bit Integer SIMD and floating-point SIMD instructions in Intel SSE/SSE2/SSE3/SSSE3. Intel 
SSE4.1 does not provide any 64-bit integer SIMD instructio ns operating on MMX registers. The sections that follow 
describe each subgroup.
5.10.1 Dword Multiply Instructions 
PMULLD Returns four lower 32-bits of the 64-b it results of signed 32-bit integer multiplies.
PMULDQ Returns two 64-bit signed result  of signed 32-bit integer multiplies.Vol. 1 5-27INSTRUCTION SET SUMMARY
5.10.2 Floating-Point Dot Product Instructions
DPPD Perform double precision dot product for up to 2 elements and broadcast.
DPPS Perform single precision dot products for up to 4 elements and broadcast.
5.10.3 Streaming Load Hint Instruction
MOVNTDQA Provides a non-temporal hint that can cause adjacent 16-byte items within an aligned 64-
byte region (a streaming line) to be fetched and held in a small set of temporary buffers 
(“streaming load buffers”). Subsequent stream ing loads to other aligned 16-byte items in 
the same streaming line may be supplied from  the streaming load buffer and can improve 
throughput.
5.10.4 Packed Blending Instructions
BLENDPD Conditionally copies specified double precis ion floating-point data elements in the source 
operand to the corresponding data elements in  the destination, using an immediate byte 
control. 
BLENDPS Conditionally copies specified single precis ion floating-point data elements in the source 
control.
BLENDVPD Conditionally copies specified double precis ion floating-point data elements in the source 
operand to the corresponding data elements in the destination, using an implied mask. 
BLENDVPS Conditionally copies specified single precision floating-point data elements in the source 
PBLENDVB Conditionally copies spec ified byte elements in the source operand to the corresponding 
elements in the destination, using an implied mask.
PBLENDW Conditionally copies spec ified word elements in the source operand to the corresponding 
elements in the destination, using an immediate byte control.
5.10.5 Packed Integer MIN/MAX Instructions 
PMINUW Compare packed unsigned word integers.
PMINUD Compare packed unsigned dword integers.
PMINSB Compare packed signed byte integers.PMINSD Compare packed signed dword integers.
PMAXUW Compare packed unsigned word integers.
PMAXUD Compare packed unsigned dword integers.PMAXSB Compare packed signed byte integers.
PMAXSD Compare packed signed dword integers.
5.10.6 Floating-Point Round Instructions with Selectable Rounding Mode
ROUNDPS Round packed single precision floating-point  values into integer values and return rounded 
ROUNDPD Round packed double precision floating-p oint values into integer values and return 
rounded floating-point values. 
ROUNDSS Round the low packed single precision floating-point value into an integer value and return 
a rounded floating-point value.
ROUNDSD Round the low packed double precision fl oating-point value into an integer value and 
return a rounded floating-point value.5-28 Vol. 1INSTRUCTION SET SUMMARY
5.10.7 Insertion and Extractions from XMM Registers
EXTRACTPS Extracts a single precision floating-point value from a specified offset in an XMM register 
and stores the result to memory or a general-purpose register.

INSERTPS Inserts a single precision floating-point value from either a 32-bit memory location or 
selected from a specified offset in an XMM register to a specified offset in the destination XMM register. In addition, INSERTPS allows zero ing out selected data elements in the desti-
nation, using a mask.
PINSRB Insert a byte value from a regist er or memory into an XMM register.
PINSRD Insert a dword value from 32-bit re gister or memory into an XMM register.
PINSRQ Insert a qword value from 64-bit re gister or memory into an XMM register.
PEXTRB Extract a byte from an XMM register and inse rt the value into a general-purpose register or 
memory.
PEXTRW Extract a word from an XMM register and insert the value into a general-purpose register 
or memory.
PEXTRD Extract a dword from an XMM register and insert the value into a general-purpose register 
or memory.
PEXTRQ Extract a qword from an XMM register and insert the value into a general-purpose register 
or memory.
5.10.8 Packed Integer Format Conversions
PMOVSXBW Sign extend the lower 8-bi t integer of each packed word element into packed signed word 
integers. 
PMOVZXBW Zero extend the lower 8-bi t integer of each packed word el ement into packed signed word 
integers.
PMOVSXBD Sign extend the lower 8-bit integer of each packed dword element into packed signed 
dword integers.
PMOVZXBD Zero extend the lower 8-bit integer of each packed dword element into packed signed 
PMOVSXWD Sign extend the lower 16-bit integer of each packed dword element into packed signed 
PMOVZXWD Zero extend the lower 16-bit integer of each packed dword element into packed signed 
PMOVSXBQ Sign extend the lower 8-bit integer of each packed qword element into packed signed 
qword integers.
PMOVZXBQ Zero extend the lower 8-bit integer of each packed qword element into packed signed 
PMOVSXWQ Sign extend the lower 16-bit integer of each packed qword element into packed signed 
PMOVZXWQ Zero extend the lower 16-bit integer of each packed qword element into packed signed 
PMOVSXDQ Sign extend the lower 32-bit integer of each packed qword element into packed signed 
PMOVZXDQ Zero extend the lower 32-bit integer of each packed qword element into packed signed 
5.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks
MPSADBW Performs eight 4-byte wide Sum of Absolute  Differences operations to produce eight word 
integers. Vol. 1 5-29INSTRUCTION SET SUMMARY
5.10.10 Horizontal Search
PHMINPOSUW Finds the value and loca tion of the minimum unsigned word from one of 8 horizontally 
packed unsigned words. The resulting value and location (offset within the source) are 
packed into the low dword of the destination XMM register.
5.10.11 Packed Test
PTEST Performs a logical AND between the destination with this mask and sets the ZF flag if the 
result is zero. The CF flag (zero for TEST) is set if the inverted mask AND’d with the desti-
nation is all zeroes.
5.10.12 Packed Qword Eq uality Comparisons
PCMPEQQ 128-bit packed qword equality test.
5.10.13 Dword Packing With Unsigned Saturation
PACKUSDW Packs dword to word with unsigned saturation.
5.11 INTEL® SSE4.2 INSTRUCTION SET
Five of the Intel SSE4.2 instructions operate on XMM re gister as a source or destination. These include four 
text/string processing instructions and one packed quadword compare SIMD instruction. Programming these five Intel SSE4.2 instructions is similar to programming 128- bit Integer SIMD in Intel SSE2/SSSE3. Intel SSE4.2 does 
not provide any 64-bit integer SIMD instructions. 
CRC32 operates on general-purpose registers and is summari zed in Section 5.1.6. The sections that follow summa-
rize each subgroup.
5.11.1 String and Text Processing Instructions
PCMPESTRI Packed compare explicit-lengt h strings, return index in ECX/RCX.
PCMPESTRM Packed compare explicit-lengt h strings, return mask in XMM0.
PCMPISTRI Packed compare implicit-lengt h strings, return index in ECX/RCX.
PCMPISTRM Packed compare implicit-lengt h strings, return mask in XMM0.
5.11.2 Packed Comparison SIMD Integer Instruction
PCMPGTQ Performs logical compare of grea ter-than on packed integer quadwords.
5.12 INTEL® AES-NI AND PCLMULQDQ
Six Intel® AES-NI instructions operate on XMM registers to  provide accelerated primitives for block encryp-
tion/decryption using Advanced Encryption Standard (F IPS-197). The PCLMULQDQ instruction performs carry-less 
multiplication for two binary numbers up to 64-bit wide. 
AESDEC Perform an AES decryption round using an 128-bit state and a round key.
AESDECLAST Perform the last AES decryption round using an 128-bit state and a round key.
AESENC Perform an AES encr yption round using an 128-bit state and a round key.
AESENCLAST Perform the last AES encryption ro und using an 128-bit state and a round key.
AESIMC Perform an inverse mix column transformation primitive.5-30 Vol. 1INSTRUCTION SET SUMMARY
AESKEYGENASSIST Assist the creation of ro und keys with a key expansion schedule.
PCLMULQDQ Perform carryless multiplication of two 64-bit numbers.
5.13 INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX)
Intel® Advanced Vector Extensions (AVX) promote legacy 128- bit SIMD instruction sets that operate on the XMM 
register set to use a “vector extension” (VEX) prefix and operates on 256-bit vector registers (YMM). Almost all 
prior generations of 128-bit SIMD instructions that oper ate on XMM (but not on MMX registers) are promoted to 
support three-operand syntax with VEX-128 encoding.
VEX-prefix encoded Intel AVX instructio ns support 256-bit and 128-bit floating-point operations by extending the 
legacy 128-bit SIMD floating-point instru ctions to support three-operand syntax. 
Additional functional enhancements are also provided with VEX-encoded Intel AVX instructions.
The list of Intel AVX instructions is  included in the following tables:
•Table 14-2 lists 256-bit and 128-bit floating-point arithm etic instructions promoted from legacy 128-bit SIMD 
instruction sets.
•Table 14-3 lists 256-bit and 128-bit data movement and pr ocessing instructions promoted from legacy 128-bit 
SIMD instruction sets.
•Table 14-4 lists functional enhancements of 256-bit Inte l AVX instructions not available from legacy 128-bit 
•Table 14-5 lists 128-bit integer and floating-point instructions promoted from legacy 128-bit SIMD instruction 
sets.
•Table 14-6 lists functional enhancements of 128-bit Inte l AVX instructions not available from legacy 128-bit 
•Table 14-7 lists 128-bit data movement and processing instructions promoted from legacy instruction sets.
5.14 16-BIT FLOATI NG-POINT CONVERSION
Conversions between single precision floating-point (32-bi t) and half precision floating-point (16-bit) data are 
provided by the VCVTPS2PH and VCVTPH2P S instructions, introduced beginning with the third generation of Intel 
Core processors based on Ivy Bridge microarchitecture: 
VCVTPH2PS Convert eight/four data elements contai ning 16-bit floating-point data into eight/four 
single precision floating-point data.
VCVTPS2PH Convert eight/four data elements containing single precision floating-point data into 
eight/four 16-bit floating-point data.
Starting with the 4th generation Intel Xeon Scalable Processor Family based on Sapphire Rapids microarchitecture, 
Intel® AVX-512 instruction set architecture for FP16 was added, supporting a wide range of general-purpose 
numeric operations for 16-bit half precision floating-p oint values (binary16 in IEEE Standard 754-2019 for 
Floating-Point Arithmetic, aka half precision or FP16).  Section 5.19 includes a list of these instructions.
5.15 FUSED-MULTIPLY-ADD (FMA)
FMA extensions enhances Intel AVX with high-throughput,  arithmetic capabilities covering fused multiply-add, 
fused multiply-subtract, fused multiply  add/subtract interleave, signed-reversed multiply on fused multiply-add 
and multiply-subtract. FMA extensions provide 36 256-bit floating-point instructions to perform computation on 
256-bit vectors and additional 128-bit and scalar FMA instructions.
•Table 14-15 lists FMA instruction sets.Vol. 1 5-31INSTRUCTION SET SUMMARY
5.16 INTEL® ADVANCED VECTOR  EXTENSIONS 2 (INTEL® AVX2)
Intel® AVX2 extends Intel AVX by promoting most of the 12 8-bit SIMD integer instructions with 256-bit numeric 
processing capabilities. Intel AVX2 instructions fo llow the same programming model as AVX instructions. 
In addition, AVX2 provide enhanced functionalities for broadcast/permute operations on data elements, vector 
shift instructions with variable-shift count per data el ement, and instructions to fetch non-contiguous data 
elements from memory.
•Table 14-18 lists promoted vector integer instructions in AVX2.
•Table 14-19 lists new instructions in AVX2 that complements AVX.
5.17 INTEL® TRANSACTIONAL SYNCHR ONIZATION EXTENSIONS (INTEL® TSX)

XABORT Abort an RTM transaction execution.
XACQUIRE Prefix hint to the beginning of an HLE transaction region.
XRELEASE Prefix hint to the end of an HLE transaction region.
XBEGIN Transaction begin of an RTM transaction region.XEND Transaction end of an RTM transaction region.
XTEST Test if executing in a transactional region.
XRESLDTRK Resume tracking load addresses.XSUSLDTRK Suspend tracking load addresses.
5.18 INTEL® SHA EXTENSIONS 
Intel® SHA extensions provide a set of instructions that ta rget the acceleration of the Secure Hash Algorithm 
(SHA), specifically the SHA-1 and SHA-256 variants. 
SHA1MSG1 Perform an intermediate calculation for the next four SHA1 message dwords from the 
previous message dwords.
SHA1MSG2 Perform the final calculation for the next four SHA1 message dwords from the intermediate 
message dwords.
SHA1NEXTE Calculate SHA1 state E after four rounds.
SHA1RNDS4 Perform four rounds of SHA1 operations.
SHA256MSG1 Perform an intermediate calculation for the next four SHA256 message dwords.SHA256MSG2 Perform the final calculation for the next four SHA256 message dwords.
SHA256RNDS2 Perform two rounds of SHA256 operations.
5.19 INTEL® ADVANCED VECTOR EXTENSIONS 512 (INTEL® AVX-512)
The Intel® AVX-512 family comprises a collection of 512-bit SIMD instruction sets to accelerate a diverse range of 
applications. Intel AVX-512 instructions provide a wide ra nge of functionality that support programming in 512-bit, 
256 and 128-bit vector register, plus support for opmask re gisters and instructions operating on opmask registers. 
The collection of 512-bit SIMD instruction sets in Intel AVX-512 include new functionality not available in Intel AVX 
and Intel AVX2, and promoted instructions similar to equi valent ones in Intel AVX/Intel AVX2 but with enhance-
ment provided by opmask registers not available to  VEX-encoded Intel AVX/Intel AVX2. Some instruction 
mnemonics in Intel AVX/Intel AVX2 that are promoted in to Intel AVX-512 can be replaced by new instruction 
mnemonics that are available only with EVEX encoding , e.g., VBROADCASTF128 into VBROADCASTF32X4. Details 
of EVEX instruction encoding are discussed in Sect ion 2.7, “Intel® AVX-512 Encoding,” of the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 2A. St arting with the 4th generation Intel Xeon Scalable 
Processor Family, an Intel AVX-512 instruction set architec ture for FP16 was added, supporting a wide range of 5-32 Vol. 1INSTRUCTION SET SUMMARY
general-purpose numeric operations for 16-bit half precis ion floating-point values, which complements the existing 
512-bit instruction mnemonics in AVX-512F instructions that are not Intel AVX or AVX2 promotions include:
VALIGND/Q Perform dword/qword alignment of two concatenated source vectors.VBLENDMPD/PS Replace the VBLENDVPD/PS instruct ions (using opmask as select control).
VCOMPRESSPD/PS Compress packed DP or SP elements of a vector.
VCVT(T)PD2UDQ Convert packed DP FP elements of a vector to packed unsigned 32-bit integers.
VCVT(T)PS2UDQ Convert packed SP FP elements of a vector to packed unsigned 32-bit integers.
VCVTQQ2PD/PS Convert packed signed 64-bit integers to packed DP/SP FP elements.
VCVT(T)SD2USI Convert the low DP FP elemen t of a vector to an unsigned integer.
VCVT(T)SS2USI Convert the low SP FP element of a vector to an unsigned integer.
VCVTUDQ2PD/PS Convert packed unsigned 32-bit integers to packed DP/SP FP elements.
VCVTUSI2USD/S Convert an unsigned integer to th e low DP/SP FP element and merge to a vector.
VEXPANDPD/PS Expand packed DP or SP elements of a vector.
VEXTRACTF32X4/64X4 Extract a vector from a full-l ength vector with 32/64-bit granular update.
VEXTRACTI32X4/64X4 Extract a vector from a full-le ngth vector with 32/64-bit granular update.
VFIXUPIMMPD/PS Perform fix-up to special values in DP/SP FP vectors.
VFIXUPIMMSD/SS Perform fix-up to specia l values of the low DP/SP FP element.
VGETEXPPD/PS Convert the exponent of DP/SP FP  elements of a vector into FP values.
VGETEXPSD/SS Convert the exponent of the low DP /SP FP element in a vector into FP value.
VGETMANTPD/PS Convert the manti ssa of DP/SP FP elements of a vector into FP values.
VGETMANTSD/SS Convert the mantissa of the low DP/SP FP element of a vector into FP value.
VINSERTF32X4/64X4 Insert a 128/256-bit vector into a full-length vector with 32/64-bit granular update.
VMOVDQA32/64 VMOVDQA with 32/64-bit  granular conditional update.
VMOVDQU32/64 VMOVDQU with 32/64-bit granular conditional update.
VPBLENDMD/Q Blend dword/qword elements  using opmask as select control.
VPBROADCASTD/Q Broadcast from general-pu rpose register to vector register.
VPCMPD/UD Compare packed signed/unsig ned dwords using specified primitive.
VPCMPQ/UQ Compare packed signed/unsigne d quadwords using specified primitive.
VPCOMPRESSQ/D Compress packed 64/32-bit elements of a vector.VPERMI2D/Q Full permute of two tables of dwor d/qword elements overwriting the index vector.
VPERMI2PD/PS Full permute of two tables of DP/SP elements overwriting the index vector.
VPERMT2D/Q Full permute of two tables of dwor d/qword elements overwriting one source table.
VPERMT2PD/PS Full permute of two tables of DP/SP elements overwriting one source table.
VPEXPANDD/Q Expand packed dword/qword elements of a vector.
VPMAXSQ Compute maximum of packed signed 64-bit integer elements.VPMAXUD/UQ Compute maximum of packed unsigned 32/64-bit integer elements.
VPMINSQ Compute minimum of packed signed 64-bit integer elements.
VPMINUD/UQ Compute minimum of packed unsigned 32/64-bit integer elements.VPMOV(S|US)QB Down convert qword elem ents in a vector to byte elements using truncation (saturation | 
unsigned saturation).
VPMOV(S|US)QW Down convert qword elements in a vector  to word elements using truncation (saturation | 
VPMOV(S|US)QD Down convert qword elements in a vector to dword elements using truncation (saturation | 
VPMOV(S|US)DB Down convert dword elements in a vector  to byte elements using truncation (saturation | 
unsigned saturation).Vol. 1 5-33INSTRUCTION SET SUMMARY
VPMOV(S|US)DW Down convert dword elements in a vector  to word elements using truncation (saturation | 
VPROLD/Q Rotate dword/qword element left by a constant shift count with conditional update.
VPROLVD/Q Rotate dword/qword element left by shif t counts specified in a vector with conditional 
update.
VPRORD/Q Rotate dword/qword element right by a constant shift count with conditional update.
VPRORRD/Q Rotate dword/qword element right by shif t counts specified in a vector with conditional 
update.
VPSCATTERDD/DQ Scatter dword/qword elements in  a vector to memory using dword indices.
VPSCATTERQD/QQ Scatter dword/qword elements in  a vector to memory using qword indices.
VPSRAQ Shift qwords right by a constant shift count and shifting in sign bits.VPSRAVQ Shift qwords right by shift counts in a vector and shifting in sign bits.
VPTESTNMD/Q Perform bitwise NAND of dword/qword elements of two vectors and write results to 
opmask.
VPTERLOGD/Q Perform bitwise ternary logic operation of  three vectors with 32/64 bit granular conditional 
update.
VPTESTMD/Q Perform bitwise AND of dword/qword elements of two vect ors and write results to opmask.
VRCP14PD/PS Compute approximate reciprocals of  packed DP/SP FP elements of a vector.
VRCP14SD/SS Compute the approximate reciprocal of the low DP/SP FP element of a vector.VRNDSCALEPD/PS Round packed DP/SP FP elements of a vector to specified number of fraction bits.
VRNDSCALESD/SS Round the low DP/SP FP element of a vector to specified number of fraction bits.
VRSQRT14PD/PS Compute approximate reciprocals of square  roots of packed DP/SP FP elements of a vector.
VRSQRT14SD/SS Compute the approximate reciprocal of square root of the low DP/SP FP element of a 
vector.
VSCALEPD/PS Multiply packed DP/SP FP elements of a vector by powers of two with exponents specified 
in a second vector.
VSCALESD/SS Multiply the low DP/SP FP element of a vect or by powers of two with  exponent specified in 
the corresponding element of a second vector.
VSCATTERDD/DQ Scatter SP/DP FP elements in a vector to memory using dword indices.
VSCATTERQD/QQ Scatter SP/DP FP elements in a vector to memory using qword indices.
VSHUFF32X4/64X2 Shuffle 128-bit lanes of a vector with 32/64 bit granular conditional update.VSHUFI32X4/64X2 Shuffle 128-bit lanes of a vector with 32/64 bit granular conditional update.
512-bit instruction mnemonics in AVX-512DQ that are not Intel AVX or AVX2 promotions include:
VCVT(T)PD2QQ Convert packed DP FP elements of a vector to packed signed 64-bit integers.
VCVT(T)PD2UQQ Convert packed DP FP elements of a vector to packed unsigned 64-bit integers.VCVT(T)PS2QQ Convert packed SP FP elements of a vector to packed signed 64-bit integers.

vector.
VCVT(T)PS2UQQ Convert packed SP FP elements of a vector to packed unsigned 64-bit integers.
VCVTUQQ2PD/PS Convert packed unsigned 64-bit integers to packed DP/SP FP elements.VEXTRACTF64X2 Extract a vector from a full-length vector with 64-bit granular update.
VEXTRACTI64X2 Extract a vector from a full-length vector with 64-bit granular update.
VFPCLASSPD/PS Test packed DP/SP FP elements in a vector by numeric/special-value category.VFPCLASSSD/SS Test the low DP/SP FP element by numeric/special-value category.
VINSERTF64X2 Insert a 128-bit vector into a fu ll-length vector with 64-bit granular update.
VINSERTI64X2 Insert a 128-bit vector into a full-length vector with 64-bit granular update.VPMOVM2D/Q Convert opmask register to vector register in 32/64-bit granularity.
VPMOVB2D/Q2M Convert a vector register in 32/ 64-bit granularity to an opmask register.5-34 Vol. 1INSTRUCTION SET SUMMARY
VPMULLQ Multiply packed signed 64-bit integer elem ents of two vectors and store low 64-bit signed 
result.
VRANGEPD/PS Perform RANGE operation on each pair of  DP/SP FP elements of two vectors using specified 
range primitive in imm8.
VRANGESD/SS Perform RANGE operation on the pair of  low DP/SP FP element of two vectors using speci-
fied range primitive in imm8.
VREDUCEPD/PS Perform Reduction operation on packed DP/SP FP elements of a vector using specified 
reduction primitive in imm8.
VREDUCESD/SS Perform Reduction operation on the lo w DP/SP FP element of a vector using specified 
512-bit instruction mnemonics in AVX-512BW that are not Intel AVX or AVX2 promotions include:
VDBPSADBW Double block packed Sum-Absolute-Differences on unsigned bytes.VMOVDQU8/16 VMOVDQU with 8/16-bit granular conditional update.
VPBLENDMB Replaces the VPBLENDVB instruction (using opmask as select control).
VPBLENDMW Blend word elements us ing opmask as select control.
VPBROADCASTB/W Broadcast from general-pu rpose register to vector register.
VPCMPB/UB Compare packed signed/unsigned bytes using specified primitive.VPCMPW/UW Compare packed signed/unsig ned words using specified primitive.
VPERMW Permute packed word elements.
VPERMI2B/W Full permute from two tables of byte/word elements overwriting the index vector.VPMOVM2B/W Convert opmask register to vector register in 8/16-bit granularity.
VPMOVB2M/W2M Convert a vector register in 8/16-bit granularity to an opmask register.
VPMOV(S|US)WB Down convert word elements in a vector to byte elements using truncation (saturation | 
VPSLLVW Shift word elements in a vector left by shift counts in a vector.
VPSRAVW Shift words right by shift counts in  a vector and shifting in sign bits.
VPSRLVW Shift word elements in a vector right by shift counts in a vector.
VPTESTNMB/W Perform bitwise NAND of byte/word elem ents of two vectors and write results to opmask.
VPTESTMB/W Perform bitwise AND of byte/word elements of two vectors and write results to opmask.
512-bit instruction mnemonics in AVX-512CD that are not Intel AVX or AVX2 promotions include:
VPBROADCASTM Broadcast from opmask register to vector register.
VPCONFLICTD/Q Detect conflicts within a vector of packed 32/64-bit integers.
VPLZCNTD/Q Count the number of leading zero  bits of packed dword/qword elements.
Opmask instructions include:
KADDB/W/D/Q Add two 8/16/32/64-bit opmasks.
KANDB/W/D/Q Logical AND two 8/16/32/64-bit opmasks.KANDNB/W/D/Q Logical AND NOT two 8/16/32/64-bit opmasks.
KMOVB/W/D/Q Move from or move to opma sk register of 8/16/32/64-bit data.
KNOTB/W/D/Q Bitwise NOT of two 8/16/32/64-bit opmasks.KORB/W/D/Q Logical OR two 8/16/32/64-bit opmasks.
KORTESTB/W/D/Q Update EFLAGS according to the resu lt of bitwise OR of two 8/16/32/64-bit opmasks.
KSHIFTLB/W/D/Q Shift left 8/16/32/64-bit opmask by specified count.KSHIFTRB/W/D/Q Shift right 8/16/32/64-bit opmask by specified count.
KTESTB/W/D/Q Update EFLAGS according to the result  of bitwise TEST of two 8/16/32/64-bit opmasks.Vol. 1 5-35INSTRUCTION SET SUMMARY
KUNPCKBW/WD/DQ Unpack and interleave two 8/ 16/32-bit opmasks into 16/32/64-bit mask.
KXNORB/W/D/Q Bitwise logical XNOR of two 8/16/32/64-bit opmasks.KXORB/W/D/Q Logical XOR of two 8/16/32/64-bit opmasks.
512-bit instruction mnemonics in AVX-512ER include:
VEXP2PD/PS Compute approximate base-2 exponentia l of packed DP/SP FP elements of a vector.
VEXP2SD/SS Compute approximate base-2 exponentia l of the low DP/SP FP element of a vector.
VRCP28PD/PS Compute approximate reciprocals to 28 bi ts of packed DP/SP FP elements of a vector. 
VRCP28SD/SS Compute the approximate reciprocal to 28  bits of the low DP/SP FP element of a vector. 
VRSQRT28PD/PS Compute approximate reciprocals of square  roots to 28 bits of packed DP/SP FP elements 
of a vector.
VRSQRT28SD/SS Compute the approximate reciprocal of sq uare root to 28 bits of the low DP/SP FP element 
512-bit instruction mnemonics in AVX-512PF include:
VGATHERPF0DPD/PS Sparse prefetch of packed DP/S P FP vector with T0 hint using dword indices.
VGATHERPF0QPD/PS Sparse prefetch of packed DP/S P FP vector with T0 hint using qword indices.
VGATHERPF1DPD/PS Sparse prefetch of packed DP/S P FP vector with T1 hint using dword indices.
VGATHERPF1QPD/PS Sparse prefetch of packed DP/S P FP vector with T1 hint using qword indices.
VSCATTERPF0DPD/PS Sparse prefetch of packed DP/SP FP  vector with T0 hint to write using dword indices.
VSCATTERPF0QPD/PS Sparse prefetch of packed DP/SP FP  vector with T0 hint to write using qword indices.
VSCATTERPF1DPD/PS Sparse prefetch of packed DP/SP FP  vector with T1 hint to write using dword indices.
VSCATTERPF1QPD/PS Sparse prefetch of packed DP/SP FP  vector with T1 hint to write using qword indices.
512-bit instruction mnemonics in AVX512-FP16 include:
VADDPH/SH Add packed/scalar FP16 values.
VCMPPH/SH Compare packed/scalar FP16 values.
VCOMISH Compare scalar ordered FP16 values and set EFLAGS.VCVTDQ2PH Convert packed signed doubleword integers to packed FP16 values.
VCVTPD2PH Convert packed double precision FP values to packed FP16 values.
VCVTPH2DQ/QQ Convert packed FP16 values to  signed doubleword/quadword integers.
VCVTPH2PD Convert packed FP16 values to FP64 values.
VCVTPH2PS[X] Convert packed FP16 values to single precision floating-point values.
VCVTPH2QQ Convert packed FP16 values to signed quadword integer values.VCVTPH2UDQ/QQ Convert packed FP16 values to unsigned doubleword/quadword integers.
VCVTPH2UW/W Convert packed FP16 values to unsigned/signed word integers.
VCVTPS2PH[X] Convert packed single precision floating-point values to packed FP16 values.VCVTQQ2PH Convert packed signed quadword integers to packed FP16 values.
VCVTSD2SH Convert low FP64 value to an FP16 value.
VCVTSH2SD/SS Convert low FP16 value to an FP64/FP32 value.VCVTSH2SI/USI Convert low FP16 value to signed/unsigned integer.
VCVTSI2SH Convert a signed doubleword/quadword integer to an FP16 value.
VCVTSS2SH Convert low FP32 value to an FP16 value.VCVTTPH2DQ/QQ Convert with truncation packed FP16 values to signed doubleword/quadword integers.
VCVTTPH2UDQ/QQ Convert with truncation packed FP16 values to unsigned doubleword/quadword integers.
VCVTTPH2UW/W Convert packed FP16 values to unsigned/signed word integers.5-36 Vol. 1INSTRUCTION SET SUMMARY
VCVTTSH2SI/USI Convert with truncation low FP16 value to a signed/unsigned integer.
VCVTUDQ2PH Convert packed unsigned doublewo rd integers to packed FP16 values.
VCVTUQQ2PH Convert packed unsigned quadwo rd integers to packed FP16 values.
VCVTUSI2SH Convert unsigned double word integer to an FP16 value.
VCVTUW2PH Convert packed unsigned word integers to FP16 values.
VCVTW2PH Convert packed signed word integers to FP16 values.
VDIVPH/SH Divide packed/scalar FP16 values.
VF[C]MADDCPH Complex multiply and accumulate FP16 values.VF[C]MADDCSH Complex multiply and accumulate scalar FP16 values.
VF[C]MULCPH Complex multiply FP16 values.
VF[C]MULCSH Complex multiply scalar FP16 values.VF[,N]MADD[132,213,231]PH Fused multiply-add of packed FP16 values.
VF[,N]MADD[132,213,231]SH Fused mult iply-add of scalar FP16 values.
VFMADDSUB[132,213,231]PH Fused multiply-alternating add/subtract of packed FP16 values.
VFMSUBADD[132,213,231]PH Fused multiply-alternating subtract/add of packed FP16 values.
VF[,N]MSUB[132,213,231]PH Fused multiply-subtract of packed FP16 values.VF[,N]MSUB[132,213,231]SH Fused multiply-subtract of scalar FP16 values.
VFPCLASSPH/SH Test types of packed/scalar FP16 values.
VGETEXPPH/SH Convert exponents of packed /scalar FP16 values to FP16 values.
VGETMANTPH/SH Extract FP16 vector of norm alized mantissas from FP16 vector/scalar.
VMAXPH/PS Return maximum of packed/scalar FP16 values.
VMINPH/PS Return minimum of packed/scalar FP16 values.VMOVSH Move scalar FP16 value.
VMOVW Move word.
VMULPH/SH Multiply packed/scalar FP16 values.VRCPPH/SH Compute reciprocals of packed/scalar FP16 values.
VREDUCEPH/SH Perform reduction transfor mation on packed/scalar FP16 values.

VRNDSCALEPH/SH Round packed/scalar FP16 values to include a given number of fraction bits.VRSQRTPH/SH Compute reciprocals of square roots of packed/scalar FP16 values.
VSCALEPH/SH Scale packed/scalar FP16 values with FP16 values.
VSQRTPH/SH Compute square root of packed/scalar FP16 values.VSUBPH/SH Subtract packed/scalar FP16 values.
VUCOMISH Unordered compare scalar FP16 values and set EFLAGS.
5.20 SYSTEM INSTRUCTIONS
The following system instructions are used to control thos e functions of the processor that are provided to support 
for operating systems and executives.
CLAC Clear AC Flag in EFLAGS register.STAC Set AC Flag in EFLAGS register.
LGDT Load global descriptor table (GDT) register.
SGDT Store global descriptor table (GDT) register.LLDT Load local descriptor table (LDT) register.
SLDT Store local descriptor table (LDT) register.
LTR Load task register.STR Store task register.Vol. 1 5-37INSTRUCTION SET SUMMARY
LIDT Load interrupt descriptor table (IDT) register.
SIDT Store interrupt descriptor table (IDT) register.MOV Load and store control registers.
LMSW Load machine status word.
SMSW Store machine status word.CLTS Clear the task-switched flag.
ARPL Adjust requested privilege level.
LAR Load access rights.LSL Load segment limit.
VERR Verify segment for reading
VERW Verify segment for writing.MOV Load and store debug registers.
INVD Invalidate cache, no writeback.
WBINVD Invalidate cache, with writeback.
INVLPG Invalidate TLB Entry.
INVPCID Invalidate Process-Context Identifier.LOCK (prefix) Perform atomic access to memory (can be applied to a number of general purpose instruc-
tions that provide memory source/destination access).
HLT Halt processor.RSM Return from system management mode (SMM).
RDMSR Read model-specific register.
WRMSR Write model-specific register.RDPMC Read performance monitoring counters.
RDTSC Read time stamp counter.
RDTSCP Read time stamp counter and processor ID.SYSENTER Fast System Call, transfers to a flat protected mode kernel at CPL = 0.
SYSEXIT Fast System Call, transfers to a flat protected mode kernel at CPL = 3.
XSAVE Save processor extended states to memory.XSAVEC Save processor extended states with compaction to memory.
XSAVEOPT Save processor extended states to memory, optimized.
XSAVES Save processor supervisor-mode extended states to memory.XRSTOR Restore processor extended states from memory.
XRSTORS Restore processor supervisor-m ode extended states from memory.
XGETBV Reads the state of an extended control register.XSETBV Writes the state of an extended control register.
RDFSBASE Reads from FS base address at any privilege level.
RDGSBASE Reads from GS base ad dress at any privilege level.
WRFSBASE Writes to FS base ad dress at any privilege level.
WRGSBASE Writes to GS base ad dress at any privilege level.
5.21 64-BIT MODE INSTRUCTIONS
The following instructions are introduced in 64-bit  mode. This mode is a sub-mode of IA-32e mode.
CDQE Convert doubleword to quadword.
CMPSQ Compare string operands.CMPXCHG16B Compare RDX:RAX with m128.5-38 Vol. 1INSTRUCTION SET SUMMARY
LODSQ Load qword at a ddress (R)SI into RAX.
MOVSQ Move qword from address (R)SI to (R)DI.MOVZX (64-bits) Move bytes/words to do ublewords/quadwords, zero-extension.
STOSQ Store RAX at address RDI.
SWAPGS Exchanges current GS base register  value with value in MSR address C0000102H.
SYSCALL Fast call to privilege level 0 system procedures.
SYSRET Return from fast system call.
5.22 VIRTUAL-MACHINE EXTENSIONS
The behavior of the VMCS-maintenance  instructions is summarized below:
VMPTRLD Takes a single 64-bit source operand in memory. It makes the referenced VMCS active and 
current.
VMPTRST Takes a single 64-bit destination operan d that is in memory. Current-VMCS pointer is 
stored into the destination operand.
VMCLEAR Takes a single 64-bit operand in memory. The instruction sets the launch state of the VMCS 
referenced by the operand to “clear”, render s that VMCS inactive, and ensures that data 
for the VMCS have been writte n to the VMCS-data area in the referenced VMCS region.
VMREAD Reads a component from the VMCS (the enco ding of that field is given in a register 
operand) and stores it into a destination operand.
VMWRITE Writes a component to the VMCS (the encoding  of that field is given in a register operand) 
from a source operand.
The behavior of the VMX management instructions is summarized below:
VMLAUNCH Launches a virtual machine managed by th e VMCS. A VM entry occurs, transferring control 
to the VM.
VMRESUME Resumes a virtual machine managed by th e VMCS. A VM entry occurs, transferring control 
to the VM.
VMXOFF Causes the processor to leave VMX operation.
VMXON Takes a single 64-bit source operand in memory. It causes a logical processor to enter VMX 
root operation and to use the memory refere nced by the operand to support VMX opera-
tion.
The behavior of the VMX-specific TLB-management instructions is summarized below:
INVEPT Invalidate cached Extended Page Table  (EPT) mappings in the processor to synchronize 
address translation in virtual machines with memory-resident EPT pages.
INVVPID Invalidate cached mappings of address translation based on the Virtual Processor ID 
(VPID).
None of the instructions above can be executed in compat ibility mode; they generate invalid-opcode exceptions if 
executed in compatibility mode.
The behavior of the guest-available instructions is summarized below:
VMCALL Allows a guest in VMX non-root operation to call the VMM for service. A VM exit occurs, 
transferring control to the VMM.
VMFUNC Allows software in VMX non-root operatio n to invoke a VM function, which is processor 
functionality enabled and configured by software  in VMX root operation. No VM exit occurs.
5.23 SAFER MODE EXTENSIONS
The behavior of the GETSEC instruction leaves of th e Safer Mode Extensions (SMX) are summarized below:
GETSEC[CAPABILITIES]Returns the available le af functions of the GETSEC instruction.Vol. 1 5-39INSTRUCTION SET SUMMARY
GETSEC[ENTERACCS] Loads an authenticated code chipse t module and enters authenticated code execution 
mode.
GETSEC[EXITAC] Exits authenticated code execution mode.
GETSEC[SENTER] Establishes a Measured Launched Environment (MLE) which has its dynamic root of trust 
anchored to a chipset supporting Intel Trusted Execution Technology.
GETSEC[SEXIT] Exits the MLE.
GETSEC[PARAMETERS] Returns SMX related parameter information.
GETSEC[SMCRTL] SMX mode control.GETSEC[WAKEUP] Wakes up sleeping logical processors inside an MLE.
5.24 INTEL® MEMORY PROTECTION EXTENSIONS
Intel Memory Protection Extensions (Int el MPX) provides a set of instructions to enable software to add robust 
bounds checking capability to memory references. Detail s of Intel MPX are described in Appendix E, “Intel® 
Memory Protection Extensions.”
BNDMK Create a LowerBound and an UpperBound in a register.
BNDCL Check the address of a memory reference against a LowerBound.
BNDCU Check the address of a memory reference against an UpperBound in 1’s compliment form.
BNDCN Check the address of a memory reference against an UpperBound not in 1’s compliment 
form.
BNDMOV Copy or load from memory of the LowerBound and UpperBound to a register.
BNDMOV Store to memory of the LowerB ound and UpperBound from a register.
BNDLDX Load bounds using address translation.
BNDSTX Store bounds using address translation.
5.25 INTEL® SOFTWARE GUARD EXTENSIONS
Intel Software Guard Extensions (Intel SGX) provide two se ts of instruction leaf functions to enable application 
software to instantiate a protected container, referred to as an enclave. The enclave instructions are organized as leaf functions under two instruction mnemonics: ENCLS (ring 0) and ENCLU (ring 3). Details of Intel SGX are 
described in Chapter 34 thro ugh Chapter 40 of the Intel
Volume 3D.
The first implementation of Intel SGX is also referred to as SGX1, it is introduced with the 6th Generation Intel 
Core Processors. The leaf functions supp orted in SGX1 are shown in Table 5-3.
Table 5-3.  Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1
Supervisor Instruction Descripti on User Instruction Description
ENCLS[EADD] Add a page ENCLU[ EENTER] Enter an Enclave 
ENCLS[EBLOCK] Block an EPC page ENCLU[EEXIT] Exit an EnclaveENCLS[ECREATE] Create an enclave ENCLU[EGETKEY] Create a cryptographic keyENCLS[EDBGRD] Read data by debugger ENCL U[EREPORT] Create a cryptographic report
ENCLS[EDBGWR] Write data by debugger ENCLU[ERESUME] Re-enter an Enclave
ENCLS[EEXTEND] Extend EPC page measurementENCLS[EINIT] Initialize an enclaveENCLS[ELDB] Load an EPC page as blockedENCLS[ELDU] Load an EPC page as unblockedENCLS[EPA] Add version array5-40 Vol. 1INSTRUCTION SET SUMMARY
5.26 SHADOW STACK MANAGEMENT INSTRUCTIONS
Shadow stack management instructions allow the program and run-time to perform operations like recovering

Shadow stack management instructions allow the program and run-time to perform operations like recovering 
from control protection faults, shadow stack switch ing, etc. The following instructions are provided.
CLRSSBSY Clear busy bit in a su pervisor shadow stack token.
INCSSP Increment the shadow stack pointer (SSP).
RDSSP Read shadow stack point (SSP).
RSTORSSP Restore a shadow stack pointer (SSP).
SAVEPREVSSP Save previous shadow stack pointer (SSP).
SETSSBSY Set busy bit in a supervisor shadow stack token.WRSS Write to a shadow stack.
WRUSS Write to a user mode shadow stack.
5.27 CONTROL TRANSFER TERMINATING INSTRUCTIONS
ENDBR32 Terminate an Indirect Branch in 32-bit and Compatibility Mode.
ENDBR64 Terminate an Indirect Branch in 64-bit Mode.
5.28 INTEL® AMX INSTRUCTIONS
LDTILECFG Load tile configuration.STTILECFG Store tile configuration.TDPBF16PS Dot product of BF16 tiles accumu lated into packed single precision tile.
TDPBSSD Dot product of signed bytes with dword accumulation.
TDPBSUD Dot product of signed/unsig ned bytes with dword accumulation.
TDPBUSD Dot product of unsigned/sign ed bytes with dword accumulation.
TDPBUUD Dot product of unsigned bytes with dword accumulation.
TILELOADD Load data into tile.TILELOADDT1 Load data into tile with hint to optimize data caching.
TILERELEASE Release tile.
TILESTORED Store tile.TILEZERO Zero tile.
5.29 USER INTERRUPT INSTRUCTIONS
CLUI Clear user interrupt flag.SENDUIPI Send user interprocessor interrupt.STUI Set user interrupt flag.
TESTUI Determine user interrupt flag.ENCLS[EREMOVE] Remove a page from EPC
ENCLS[ETRACK] Activate EBLOCK checksENCLS[EWB] Write back/invalidate an EPC pageTable 5-3.  Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1
Supervisor Instruction Descripti on User Instruction DescriptionVol. 1 5-41INSTRUCTION SET SUMMARY
UIRET User-interrupt return.
5.30 ENQUEUE STORE INSTRUCTIONS
ENQCMD Enqueue command.
ENQCMDS Enqueue command supervisor.5-42 Vol. 1INSTRUCTION SET SUMMARYVol. 1 6-1CHAPTER 6
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
This chapter describes the facilities in the Intel 64 and IA-32 architectures for executing calls to procedures or 
subroutines. It also describes how interrupts and exceptio ns are handled from the perspective of an application 
programmer.
6.1 PROCEDURE CALL TYPES
The processor supports procedure calls in the following two different ways:
•CALL and RET instructions.
•ENTER and LEAVE instructions, in conjunct ion with the CALL and RET instructions.
Both of these procedure call mechanisms use the procedure st ack, commonly referred to simply as “the stack,” to 
save the state of the calling procedure, pass parameters to  the called procedure, and store local variables for the 
currently executing procedure.
The processor’s facilities for handling interrupts and exceptions are similar to those used by the CALL and RET 
Processors that support Control-Flow Enforcement Technology  (CET) support an additional stack referred to as “the 
shadow stack”. The CALL instruction, when shadow stacks  are enabled, additionally saves the state of the calling 
procedure on the shadow stack; and the RET instruction rest ores the state of the calling procedure if the state on 
the stack and the shadow stack match.
6.2 STACKS
The stack (see Figure 6-1) is a contiguous array of memory locations. It is contained in a segment and identified by 
the segment selector in the SS register. When using the fl at memory model, the stack can be located anywhere in 
the linear address space for the program. A stack can be  up to 4 GBytes long, the maximum size of a segment.
Items are placed on the stack using the PUSH instructio n and removed from the stack using the POP instruction. 
When an item is pushed onto the stack, the processor decr ements the ESP register, then writes the item at the new 
top of stack. When an item is popped off the stack, the processor reads the item from the top of stack, then incre-
ments the ESP register. In this manner, the stack grows down  in memory (towards lesser addresses) when items 
are pushed on the stack and shrinks up (towards greater addresses) when the items are popped from the stack.
A program or operating system/executive can set up many st acks. For example, in multitasking systems, each task 
can be given its own stack. The number of stacks in a sy stem is limited by the maximum number of segments and 
the available physical memory. 
When a system sets up many stacks, only one stack—the current stack —is available at a time. The current stack 
is the one contained in the segment referenced by the SS register.6-2 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
The processor references the SS register automatically for all stack operations. For example, when the ESP register 
is used as a memory address, it automatically points to an address in the current stack. Also, the CALL, RET, PUSH, 
POP, ENTER, and LEAVE instructions all perform operations on the current stack.
6.2.1 Setting Up a Stack
To set a stack and establish it as the current stack, the program or operating system/executive must do the 
1. Establish a stack segment.2. Load the segment selector for the stack segment into the SS register using a MOV, POP, or LSS instruction.
3. Load the stack pointer for the stack into the ESP regi ster using a MOV, POP, or LSS instruction. The LSS 
instruction can be used to load the SS and ESP registers in one operation.
See “Segment Descriptors” in Chapter 3, “Prote cted-Mode Memory Management,” of the Intel
® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 3A, for information on how to set up a segment descriptor and 
segment limits for a stack segment.
6.2.2 Stack Alignment
The stack pointer for a stack segment should be aligned on 16-bit (word) or 32-bit (double-word) boundaries, depending on the width of the stack segment. The D flag  in the segment descriptor for the current code segment 
sets the stack-segment width (see “Segment Descriptors” in  Chapter 3, “Protected-Mode Memory Management,” of 
the Intel
® 64 and IA-32 Architectures Software Developer’s Ma nual, Volume 3A). The PUSH and POP instructions 
use the D flag to determine how much to decrement or in crement the stack pointer on a push or pop operation, 
respectively. When the stack width is 16 bits, the stack pointer is incremente d or decremented in 16-bit increments; 
when the width is 32 bits, the stack pointer is incremente d or decremented in 32-bit increments. Pushing a 16-bit 
value onto a 32-bit wide stack can result in stack misalign ed (that is, the stack pointer is not aligned on a double-Figure 6-1.  Stack StructureBottom of Stack
(Initial ESP Value)
Local Variables
for Calling
Procedure
Passed to
Called
Procedure
Frame Boundary
EBP Register
ESP RegisterReturn Instruction
Top of StackStack Segment
Pushes Move the
Top Of Stack to
Lower AddressesPops Move the 
Top Of Stack toHigher AddressesThe EBP register isThe Stack Can Be
16 or 32 Bits Wide
typically set to point
to the returninstruction pointer.
PointerVol. 1 6-3PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
word boundary). One exception to this rule is when the co ntents of a segment register (a 16-bit segment selector) 
are pushed onto a 32-bit wide stack. Here, the processor automatically aligns the stack pointer to the next 32-bit 
boundary.
The processor does not check stack pointer alignment. It is the responsibility of the programs, tasks, and system 
procedures running on the processor to maintain proper alignment of stack pointers. Misaligning a stack pointer 
can cause serious performance degradation and in some instances program failures.
6.2.3 Address-Size Attributes for Stack Accesses
Instructions that use the stack implicitly (such as the PU SH and POP instructions) have two address-size attributes 
each of either 16 or 32 bits. This is because they always have the implicit address of the top of the stack, and they 
may also have an explicit memory address (for example, PUSH Array1[EBX]). The attrib ute of the explicit address 
is determined by the D flag of the current code segmen t and the presence or absence of the 67H address-size 
prefix.
The address-size attribute of the top of the stack determin es whether SP or ESP is used for the stack access. Stack 
operations with an address-size attribute of 16 use th e 16-bit SP stack pointer register and can use a maximum 
stack address of FFFFH; stack operations with an address-size attribute of 32 bits use the 32-bit ESP register and 
can use a maximum address of FFFFFFFFH. The default address-size attribute for data segments used as stacks is controlled by the B flag of the segment’s descriptor. When this flag is clear, the default address-size attribute is 16; 
when the flag is set, the address-size attribute is 32.
6.2.4 Procedure Linking Information
The processor provides two pointers for linking of procedures: the stack-frame base pointer and the return instruc-
tion pointer. When used in conjunction with a standard software procedure-call technique, these pointers permit

prefix.
tion pointer. When used in conjunction with a standard software procedure-call technique, these pointers permit 
reliable and coherent linking of procedures.
6.2.4.1  Stack-Frame Base Pointer
The stack is typically divided into fr ames. Each stack frame can then contain local variables, parameters to be 
passed to another procedure, and proced ure linking information. The stack-frame base pointer (contained in the 
EBP register) identifies a fixed reference point within the stack frame for the called procedure. To use the stack-
frame base pointer, the called procedure typically copies the contents of the ESP register into the EBP register prior 
to pushing any local variables on the stack. The stack-frame base pointer then permits easy access to data struc-tures passed on the stack, to the return instruction pointe r, and to local variables added to the stack by the called 
procedure.
Like the ESP register, the EBP register automatically points  to an address in the current stack segment (that is, the 
segment specified by the current contents of the SS register). 
6.2.4.2  Return Instruction Pointer
Prior to branching to the first instruction of the called proc edure, the CALL instruction pushes the address in the EIP 
register onto the current stack. This address is then ca lled the return-instruction pointer and it points to the 
instruction where execution of the calling procedure should  resume following a return from the called procedure. 
Upon returning from a called procedure,  the RET instruction pops the return-instruction pointer from the stack back 
into the EIP register. Execution of the calling procedure then resumes.
The processor does not keep track of the location of the retu rn-instruction pointer. It is thus up to the programmer 
to ensure that stack pointer is pointing to the return-instr uction pointer on the stack, prior to issuing a RET instruc-
tion. A common way to reset the stack pointer to the point to the return-instruction pointer is to move the contents 
of the EBP register into the ESP regist er. If the EBP register is loaded with  the stack pointer immediately following 
a procedure call, it should point to the return instruction pointer on the stack.
The processor does not require that the return instructio n pointer point back to the calling procedure. Prior to 
executing the RET instruction, the return  instruction pointer can be manipulated in software to point to any address 6-4 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
in the current code segment (near return) or another code  segment (far return). Performing such an operation, 
however, should be undertaken very cautiously , using only well defined code entry points.
6.2.5 Stack Behavior in 64-Bit Mode
In 64-bit mode, address calculations that reference SS segm ents are treated as if the segment base is zero. Fields 
(base, limit, and attribute) in segment descriptor registers are ignored. SS DPL is modified such that it is always 
equal to CPL. This will be true even if it is th e only field in the SS descriptor that is modified. 
Registers E(SP), E(IP) and E(BP) are promoted to 64-bits and are re-named RSP, RIP, and RBP respectively. Some 
forms of segment load instructions ar e invalid (for example, LDS, POP ES).
PUSH/POP instructions increment/decrement the stack us ing a 64-bit width. When the contents of a segment 
register is pushed onto 64-bit stack, the pointer is auto matically aligned to 64 bits (as with a stack that has a 32-
bit width).
6.3 SHADOW STACKS
A shadow stack is a second stack used exclusively for control transfer operations. This stack is separate from the procedure stack. The shadow stack is not used to store data, hence is not explicitly writeable by software. Writes 
to the shadow stack are restricted to control transfer instructions and shadow stack management instructions. 
Shadow stacks can be enabled separately for privilege le vel 3 (user mode) or privilege levels less than 3 (super-
visor mode).
Shadow stacks are active only in protected mode with paging enabled. Shadow stacks cannot be enabled for a 
program executing in virtual 8086 mode.
Processors that support shadow stacks have an architectu ral register called the shadow stack pointer (SSP) that 
points to the current top of the shadow stack. The SSP ca nnot be directly encoded as a source, destination, or 
memory operand in instructions. The width of the shadow stack is 32-bit in 32-bit/compatibility mode, and is 64-
bit in 64-bit mode. The address-size attribute of the shad ow stack is likewise 32-bit in 32-bit/compatibility mode, 
and 64-bit in 64-bit mode.
The size of the shadow stack pushes and pops for far CALL  and call to interrupt/exception handlers is fixed at 64 
bits, and the processor uses 8-byte, zero padded stor es for these pushes in 32-bit/compatibility modes.
6.4 CALLING PROCEDURES USING CALL AND RET
The CALL instruction allows control transfers to  procedures within the current code segment ( near call ) and in a 
different code segment ( far call ). Near calls usually provide access to local procedures within the currently running 
program or task. Far calls are usually used to access operat ing system procedures or procedures in a different task. 
See “CALL—Call Procedure” in Chapter 3, “Ins truction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 2A, for a detailed description of the CALL instruction.
The RET instruction also allows near and far returns to matc h the near and far versions of the CALL instruction. In 
addition, the RET instruction allows a program to increment the stack pointer on a return to release parameters 
from the stack. The number of bytes released from the stack is determined by an optional argument ( n) to the RET 
instruction. See “RET—Return from Procedure” in Chapte r 4, “Instruction Set Reference, M-U,” of the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 2B, for a detailed description of the RET instruction.
6.4.1 Near CALL and RET Operation
When executing a near call, the processor does the following (see Figure 6-2):
1. Pushes the current value of the EIP register on the stack.
If shadow stack is enabled and the displacement value is not 0, pushes the current value of the EIP register on 
the shadow stack.Vol. 1 6-5PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
2. Loads the offset of the called procedure in the EIP register.
3. Begins execution of the called procedure.
When executing a near return, the processor performs these actions:
1. Pops the top-of-stack value (the return instruction pointer) into the EIP register.
If shadow stack is enabled, pops the top-of-stack (the return instruction pointer) value from the shadow stack 
and if it’s not the same as the return instruction pointer popped from the stack, then the processor causes a 
control protection exception with e rror code NEAR-RET (#CP(NEAR-RET)).
2. If the RET instruction has an optional n argument, increments the stack pointer by the number of bytes 
specified with the n operand to release parameters from the stack.
3. Resumes execution of the calling procedure.
6.4.2 Far CALL and RET Operation
When executing a far call, the processor performs these actions (see Figure 6-2):
1. Pushes the current value of the CS register on the stack.
If shadow stack is enabled:
a. Temporarily saves the current value of the SSP register  internally and aligns the SSP to the next 8 byte 
boundary.
b. Pushes the current value of the CS register on the shadow stack.
c. Pushes the current value of LIP (CS.base + EIP) on the shadow stack.d. Pushes the internally saved value of the SSP register on the shadow stack.
2. Pushes the current value of the EIP register on the stack.
3. Loads the segment selector of the segment that contains the called procedure in the CS register.
4. Loads the offset of the called procedure in the EIP register.
5. Begins execution of the called procedure.
When executing a far return, the processor does the following:1. Pops the top-of-stack value (the return instruction pointer) into the EIP register.
2. Pops the top-of-stack value (the segment selector for th e code segment being returned to) into the CS register.
a. Causes a control protection exception (#CP(FAR-R ET/IRET)) if the SSP is not aligned to 8 bytes. 
b. Compares the values on the shadow stack at addre ss SSP+8 (the LIP) and SSP+16 (the CS) to the CS and 
(CS.base + EIP) popped from the stack, and causes a control protection exception (#CP(FAR-RET/IRET)) if 
they do not match. 
c. Pops the top-of-stack value (the SSP of the procedure being returned to) from shadow stack into the SSP 
register.
3. If the RET instruction has an optional n argument, increments the stack pointer by the number of bytes 
4. Resumes execution of the calling procedure.6-6 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
Figure 6-2.  Stack on Near and Far Calls
Figure 6-3.  Shadow Stack on Near and Far CallsStack 
Frame After CallStack During 
Near Call
Param 2Param 1
Calling EIPParam 3 ESP Before Call

register.
Near Call
ESP After CallStack 
Frame 
Before 
CallStack During 
Far Call
Calling EIPCalling CSParam 3
ESP After CallESP Before Call
Stack 
Frame 
After 
Call
Note: On a near or far return, parameters are released from the stack based on the optional n operand in the RET n instruction.Stack During 
Near Return
Calling EIPParam 3
ESP Before ReturnESP After ReturnStack During 
Far Return
Calling EIPCalling CSParam 3ESP After Return
ESP Before Return
Calling EIPSSP After Return
Calling LIPCalling CS
Calling SSPSSP After Return
SSP Before Return
SSP Before ReturnShadow Stack 
During Near Call
Calling EIPShadow Stack 
During Far Call
Calling SSPSSP Before Call
SSP After CallSSP Before Call
SSP After Call
Note: There are no parameters on the shadow stack. RET and RET n operate identically on 
the shadow stack.Vol. 1 6-7PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
6.4.3 Parameter Passing
Parameters can be passed between procedures in any of three ways: through general-purpose registers, in an 
argument list, or on the stack.
6.4.3.1  Passing Parameters Thro ugh the General-Purpose Registers
The processor does not save the state of the general-purp ose registers on procedure calls. A calling procedure can 
thus pass up to six parameters to the called procedure by copying the parameters into any of these registers 
(except the ESP and EBP registers) prior to executing the CALL instruction. The called procedure can likewise pass 
parameters back to the calling procedure through general-purpose registers.
6.4.3.2  Passing Parameters on the Stack
To pass a large number of parameters to the called proced ure, the parameters can be placed on the stack, in the 
stack frame for the calling procedure. Here, it is useful to use the stack-frame base pointer (in the EBP register) to 
make a frame boundary for easy access to the parameters.
The stack can also be used to pass parameters back  from the called procedure to the calling procedure.
6.4.3.3  Passing Paramete rs in an Argument List
An alternate method of passing a larger number of paramete rs (or a data structure) to the called procedure is to 
place the parameters in an argument list in one of the data  segments in memory. A pointer to the argument list can 
then be passed to the called procedure through a general- purpose register or the stack. Parameters can also be 
passed back to the calling procedure in this same manner.
6.4.4 Saving Procedure State Information
The processor does not save the contents of the genera l-purpose registers, segment registers, or the EFLAGS 
register on a procedure call. A calling procedure should ex plicitly save the values in any of the general-purpose 
registers that it will need when it resumes execution afte r a return. These values can be saved on the stack or in 
memory in one of the data segments.
The PUSHA and POPA instructions facilitate saving and re storing the contents of the general-purpose registers. 
PUSHA pushes the values in all the gene ral-purpose registers on the stack in the following order: EAX, ECX, EDX, 
EBX, ESP (the value prior to executing the PUSHA instructio n), EBP, ESI, and EDI. The POPA instruction pops all the 
register values saved with a PUSHA instruction (except the ESP value) from the stack to their respective registers.
If a called procedure changes the state of any of the segm ent registers explicitly, it should restore them to their 
former values before executing a return to the calling procedure.
If a calling procedure needs to maintain the state of the EF LAGS register, it can save and restore all or part of the 
register using the PUSHF/PUSHFD and POPF/POPFD instruct ions. The PUSHF instruction pushes the lower word of 
the EFLAGS register on the stack, while the PUSHFD inst ruction pushes the entire register. The POPF instruction 
pops a word from the stack into the lower word of the EF LAGS register, while the POPFD instruction pops a double 
word from the stack into the register.
6.4.5 Calls to Other Privilege Levels
The IA-32 architecture’s protection mechanism recognizes  four privilege levels, numbered from 0 to 3, where a 
greater number mean less privilege. The re ason to use privilege levels is to improve the reliabili ty of operating 
systems. For example, Figure 6-4 shows how privilege levels can be interpreted as rings of protection. 6-8 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
In this example, the highest privilege level 0 (at the center  of the diagram) is used for segments that contain the 
most critical code modules in the system, usually the kernel of an operating system. The outer rings (with progres-
sively lower privileges) are used for segments that contain code modules for less critical software. 
Code modules in lower privilege segments can only acce ss modules operating at higher privilege segments by 
means of a tightly controlled and protected interface called a gate. Attempts to access higher privilege segments 
without going through a protection gate and without having  sufficient access rights causes a general-protection 
exception (#GP) to be generated.
If an operating system or executive uses this multilevel protection mechanism, a call to a procedure that is in a 
more privileged protection level than the calling procedure is handled in a similar manner as a far call (see Section 
6.4.2, “Far CALL and RET Operation” ). The differences are as follows:
•The segment selector provided in the CALL instruct ion references a special data structure called a call gate 
descriptor . Among other things, the call gate descriptor provides the following:
— Access rights information.— The segment selector for the code segment of the called procedure.
— An offset into the code segment (that is, the instruction pointer for the called procedure).
•The processor switches to a new stack to execute the ca lled procedure. Each privilege level has its own stack. 
The segment selector and stack pointer for the privilege level 3 stack are stored in the SS and ESP registers, 
respectively, and are automatically saved when a call to  a more privileged level occurs. The segment selectors 
and stack pointers for the privilege level 2, 1, and 0 stac ks are stored in a system segment called the task state 
segment (TSS). 
The use of a call gate and the TSS during a stack switch are transparent to the calling procedure, except when a 
general-protection exception is raised.
6.4.6 CALL and RET Operation Between Privilege Levels
When making a call to a more privileged protection level, the processor does the following (see Figure 6-5):
1. Performs an access rights check (privilege check).
2. Temporarily saves (internally) the current contents of the SS, ESP, CS, and EIP registers.Figure 6-4.  Protection RingsLevel 0
Level 1
Level 2
Level 3Protection Rings
Operating
Operating System
Services (Device
Drivers, Etc.)
0 12 3Highest Lowest
Privilege LevelsSystem
KernelVol. 1 6-9PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
Figure 6-5.  Stack Switch on a Call to a Different Privilege LevelStack for Calling 
Procedure
Param 1
Param 3Param 2
ESP Before CallStack for Called 
Procedure
Param 1Calling ESPCalling SS
Calling CSParam 3Param 2
Calling EIPStack 
Frame 
Before CallStack 
Frame 
After Call
ESP After Call
Note: On a return, parameters are released on both stacks based on the optional n 
operand in the RET n instruction.Param 1
Param 3Param 2ESP After Return
Calling EIP ESP Before Return6-10 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
3. Loads the segment selector and stack pointer for the ne w stack (that is, the stack for the privilege level being 
called) from the TSS into the SS and ESP registers and switches to the new stack.
4. Pushes the temporarily saved SS and ESP values fo r the calling procedure’s stack onto the new stack.
5. Copies the parameters from the calling procedure’s stack to the new stack. A value in the call gate descriptor 
determines how many parameters to copy to the new stack.
6. Pushes the temporarily saved CS and EIP values for the calling procedure to the new stack.
If shadow stack is enabled at the privilege level of th e calling procedure, then the processor temporarily saves 
the SSP of the calling procedure internally. If the calling procedure is at privilege level 3, the SSP of the calling 
procedure is also saved into the IA32_PL3_SSP MSR.Figure 6-6.  Shadow Stac k Switch on a Call to a Different Privilege LevelCalling to Procedure at Higher Privilege Level from Privilege Level 3
Shadow Stack for 
Calling ProcedureHandler’s Shadow 
Stack
SSP Before Call 
and After ReturnSupervisor 
Shadow Stack 
TokenSSP After Call and 
Before Return
Note: There are no parameters on the shadow stack. RET and RET n operate identically on the shadow stack.SSP Before Call and After Return
LIPCS
SSPSSP After Call and 
Before ReturnCalling to Procedure at Higher Privilege Level from Privilege Level 2 or 1
Interrupted Procedure’s

Stack
LIPCS
Interrupted Procedure’s 
Shadow StackHandler’s Shadow 
Stack
Supervisor 
TokenVol. 1 6-11PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
If shadow stack is enabled at the privilege level of th e called procedure, then the SSP for the called procedure 
is obtained from one of the MSRs liste d below, depending on the target privilege level. The SSP obtained is then 
verified to ensure it points to a valid supervisor sh adow stack that is not currently active by verifying a 
supervisor shadow stack token at the address pointed to  by the SSP. The operations  performed to verify and 
acquire the supervisor shadow stack token by making it busy are as described in Section 17.2.3 of the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
— IA32_PL2_SSP if transitioning to ring 2.— IA32_PL1_SSP if transitioning to ring 1.
— IA32_PL0_SSP if transitioning to ring 0.
If shadow stack is enabled at the privilege level of the called procedure and the calling procedure was not at 
privilege level 3, then the processor pushes the temp orarily saved CS, LIP (CS.base + EIP), and SSP of the 
calling procedure to the new shadow stack.
1
7. Loads the segment selector for the new code segment and the new instruction pointer from the call gate into 
the CS and EIP registers, respectively.
8. Begins execution of the called pr ocedure at the new privilege level.
When executing a return from the privileged pr ocedure, the processor performs these actions:
1. Performs a privilege check.
2. Restores the CS and EIP registers to their values prior to the call.
If shadow stack is enabled at the current privilege level:
— Causes a control protection exception (#CP(FAR -RET/IRET)) if SSP is not aligned to 8 bytes.
— If the privilege level of the procedure being returned  to is less than 3 (returning to supervisor mode):
•Compares the values on shadow stack at address SS P+8 (the LIP) and SSP+16 (the CS) to the CS and 
(CS.base + EIP) popped from the stack and causes a control protection exception (#CP(FAR-
RET/IRET)) if they do not match. 
•Temporarily saves the top-of-stack value (the SSP of the procedure being returned to) internally.
— If a busy supervisor shadow stack token is present at address SSP+24, then marks the token free using 
operations described in Section 17.2.3 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1.
— If the privilege level of the procedure being returned to  is less than 3 (returning to supervisor mode), re-
stores the SSP register from the internally saved value.
— If the privilege level of the procedure being returned to  is 3 (returning to user mode) and shadow stack is 
enabled at privilege level 3, then restores th e SSP register with value of IA32_PL3_SSP MSR.
specified with the n operand to release parameters from the stack. If the call gate descriptor specifies that one 
or more parameters be copied from one stack to the other, a RET n instruction must be used to release the 
parameters from both stacks. Here, the n operand specifies the number of by tes occupied on each stack by the 
parameters. On a return, the processor increments ESP by n for each stack to step over (effectively remove) 
these parameters from the stacks.
4. Restores the SS and ESP registers to their values prior to the call, which causes a switch back to the stack of 
the calling procedure.
5. If the RET instruction has an optional n argument, increments the stack pointer by the number of bytes 
specified with the n operand to release parameters from the stack (see explanation in step 3).
6. Resumes execution of the calling procedure.
See Chapter 5, “Prote ction,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for 
detailed information on calls to privilege d levels and the call gate descriptor.
1. If any of these pushes leads to an exception or a VM  exit, the supervisor shadow -stack token remains busy.6-12 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
6.4.7 Branch Functions in 64-Bit Mode
The 64-bit extensions expand branching mechanisms to accommodate branches in 64-bit linear-address space. 
These are:
•Near-branch semantics are redefined in 64-bit mode.
•In 64-bit mode and compatibility mode, 64-bit call-gate descriptors for far calls are available.
In 64-bit mode, the operand size for all near branches (CAL L, RET, JCC, JCXZ, JMP, and LOOP) is forced to 64 bits. 
These instructions update the 64-bit RIP without the need for a REX operand-size prefix. 
The following aspects of near branches ar e controlled by the effective operand size:
•Truncation of the size of the instruction pointer.
•Size of a stack pop or push, due to a CALL or RET.
•Size of a stack-pointer increment or  decrement, due to a CALL or RET.
•Indirect-branch operand size.
In 64-bit mode, all of the above actions are forced to 64  bits regardless of operand size prefixes (operand size 
prefixes are silently ignored). However, the displacement field for relative branches is still limited to 32 bits and the 
address size for near branches is not forced in 64-bit mode. 
Address sizes affect the size of RCX used for JCXZ and L OOP; they also impact the address calculation for memory 
indirect branches. Such addresses are 64 bits by default; but they can be overridden to 32 bits by an address size 
prefix.
Software typically uses far branches to change privilege levels. The legacy IA-32 architecture provides the call-gate 
mechanism to allow software to branch from one privilege level to another, although call gates can also be used for 
branches that do not change privilege levels. When call gate s are used, the selector portion of the direct or indirect 
pointer references a gate descr iptor (the offset in the instruction is ignored). The offset to the destination’s code 
segment is taken from the call-gate descriptor. 
64-bit mode redefines the type value of a 32-bit call-gat e descriptor type to a 64-bit call gate descriptor and 
expands the size of the 64-bit descriptor to hold a 64-bi t offset. The 64-bit mode call-gate descriptor allows far 
branches that reference any location in  the supported linear-address space. These call gates also hold the target 
code selector (CS), allowing changes to privilege level and default size as a result of the gate transition.
Because immediates are generally specified up to 32 bits, the only way to specify a full 64-bit absolute RIP in 64-
bit mode is with an indirect branch. For this reason, dire ct far branches are eliminated from the instruction set in 
64-bit mode.
64-bit mode also expands the semantics of the SYSENTER and SYSEXIT instructions so that the instructions 
operate within a 64-bit memory space. The mode also  introduces two new instructions: SYSCALL and SYSRET 
(which are valid only in 64-bit mode). For details, see “SYSENTER—Fast System Call,” “SYSEXIT—Fast Return from 
Fast System Call,” “SYSCALL—Fast Syst em Call,” and “SYSRET—Return From Fast System Call” in Chapter 4, 
“Instruction Set Reference, M-U,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2B.
6.5 INTERRUPTS AND EXCEPTIONS
The processor provides two mechanisms for interrupt ing program execution, interrupts, and exceptions:
•An interrupt is an asynchronous event that is ty pically triggered by an I/O device.
•An exception  is a synchronous event that is generated when  the processor detects one or more predefined 
conditions while executing an instruction. The IA-32 arch itecture specifies three classes of exceptions: faults, 
traps, and aborts. 
The processor responds to interrupts and exceptions in essentially the same way. When an interrupt or exception 
is signaled, the processor halts execution of the current pr ogram or task and switches to a handler procedure that 
has been written specifically to handle the interrupt or  exception condition. The processor accesses the handler 
procedure through an entry in the interrupt descriptor ta ble (IDT). When the handler has completed handling the 
interrupt or exception, program control is re turned to the interrupted program or task.Vol. 1 6-13PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
The operating system, executive, and/or device drivers normally handle interrupts and exceptions independently 
from application programs or tasks. Application prog rams can, however, access the interrupt and exception 
handlers incorporated in an operating system or executiv e through assembly-language calls. The remainder of this 
section gives a brief overview of the processor’s interru pt and exception handling mechanism. See Chapter 6, 
“Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
3A, for a description of this mechanism.
The IA-32 Architecture defines 18 predefined interrupts and exceptions and 224 user defined interrupts, which are

The IA-32 Architecture defines 18 predefined interrupts and exceptions and 224 user defined interrupts, which are 
associated with entries in the IDT. Each interrupt and ex ception in the IDT is identified with a number, called a 
vector . Table 6-1 lists the interrupts and exceptions with entr ies in the IDT and their respective vectors. Vectors 0 
through 8, 10 through 14, and 16 through 19 are the predef ined interrupts and exceptions; vectors 32 through 255 
are for software-defined interrupts, which are for either software interrupts  or maskable hardware inter-
rupts .
Note that the processor defines several additional interrup ts that do not point to entries in the IDT; the most 
notable of these interrupts is the SMI interrupt. See Chap ter 6, “Interrupt and Exception Handling,” in the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information about the interrupts 
and exceptions.
When the processor detects an interrupt or exception, it does one of the following things:
•Executes an implicit call to a handler procedure.
•Executes an implicit call to a handler task.
6.5.1 Call and Return Operation for Inte rrupt or Exception Handling Procedures
A call to an interrupt or exception handler procedure is si milar to a procedure call to another protection level (see 
Section 6.4.6, “CALL and RET Operation Between Privilege Levels”). Here, the vector re ferences one of two kinds 
of gates in the IDT: an interrupt gate or a trap gate . Interrupt and trap gates are similar to call gates in that they 
provide the following information:
•Access rights information
•The segment selector for the code segment that contains the handler procedure
•An offset into the code segment to the first instruction of the handler procedure
The difference between an interrupt gate and a trap gate is as follows. If an interrupt or exception handler is called 
through an interrupt gate, the processor clears the interrupt  enable (IF) flag in the EFLAGS register to prevent 
subsequent interrupts from interfering wi th the execution of the handler. When a handler is called through a trap 
gate, the state of the IF flag is not changed.
Table 6-1.  Exceptions and Interrupts
Vector Mnemonic Description Source
 0 #DE Divide Error DIV and IDIV instructions.
 1 #DB Debug Any code or data reference. 2 NMI Interrupt Non-maskab le external interrupt.
 3 #BP Breakpoint INT3 instruction. 4 #OF Overflow INTO instruction. 5 #BR BOUND Range Exceeded BOUND instruction. 6 #UD Invalid Opcode (Undefined Opco de) UD instruction or reserved opcode.
 7 #NM Device Not Available (No Math Coprocesso r) Floating-point or WA IT/FWAIT instruction.
 8 #DF Double Fault Any instruction that can generate an exception, an NMI, or 
an INTR.
 9 #MF CoProcessor Segment Overrun (reserved) Floating-point instruction.
1
10 #TS Invalid TSS Task switch or TSS access.11 #NP Segment Not Present Loading segment registers or accessing  system segments.6-14 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
If the code segment for the handler procedure has the same  privilege level as the currently executing program or 
task, the handler procedure uses the current stack; if the ha ndler executes at a more privileged level, the processor 
switches to the stack for the handler’s privilege level. 
If no stack switch occurs, the processor does the follow ing when calling an interrupt or exception handler (see 
Figure 6-7):
1. Pushes the current contents of the EFLAGS, CS, and EIP registers (in that order) on the stack.
a. Temporarily saves the current value of the SSP register internally.
c. Pushes the current value of LIP (CS.base + EIP) on the shadow stack.
d. Pushes the temporarily saved SSP value on the shadow stack.
2. Pushes an error code (if appropriate) on the stack.3. Loads the segment selector for the new code segment an d the new instruction pointer (from the interrupt gate 
or trap gate) into the CS and EIP registers, respectively.
4. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.
5. Begins execution of the handler procedure.12 #SS Stack Segment Fault Stack operations and SS register loads.
13 #GP General Protection Any memory reference and other protection checks.14 #PF Page Fault Any memory reference.15 Reserved16 #MF Floating-Point Error (Math Fault) Floa ting-point or WAIT/FWAIT instruction.
17 #AC Alignment Check Any data reference in memory.
2
18 #MC Machine Check Error codes (if any) and source are model dependent.3
19 #XM SIMD Floating-Point Exception SIMD Floating-Point Instruction4
20 #VE Virtualization Exception EPT violations5
21 #CP Control Protection Exception The RET, IRET, RSTORSSP, and SETSSBSY instructions can 
generate this exception. When CET indirect branch tracking 
is enabled, this exception can be generated due to a 
missing ENDBRANCH instruction at the target of an indirect 
call or jump.
22-31 Reserved
32-255 Maskable Interrupt s External interrupt from INTR pin or INT n instruction.
NOTES:
1. IA-32 processors after th e Intel386 processor do no t generate this exception.
2. This exception was introduced  in the Intel486 processor.
3. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.
4. This exception was introduced  in the Pentium III processor.
5. This exception ca n occur only on processors that su pport the 1-setting of the “EPT-vio lation #VE” VM-execution control.Table 6-1.  Exceptions and Interrupts (Contd.)
Vector Mnemonic Description SourceVol. 1 6-15PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
Figure 6-7.  Stack Usage on Transfers to  Interrupt and Exception Handling RoutinesInterrupted Procedure’s
and Handler’s Stack
ESP Before
Transfer to HandlerStack Usage with No Privilege-Level Change
CSEFLAGS
Error CodeEIP
ESP AfterTransfer to Handler
Error CodeHandler’s Stack
ESPSS
EIPCSEFLAGSStack Usage with Privilege-Level Change
Stack
ESP Before
Transfer to Handler
ESP After
Transfer to Handler6-16 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
Figure 6-8.  Shadow Stack Usage on Transfers to Interrupt and Exception Handling RoutinesInterrupted Procedure’s
and Handler’s Shadow Stack
SSP Before
LIPCS
SSP SSP After
Transfer to HandlerShadow Stack Usage with No Privilege-Level Change
Shadow Stack Usage with Privilege-Level Change from Level 3
Handler’s Shadow StackInterrupted Procedure’s
Shadow Stack
SSP Before
SSP After
Transfer to HandlerSupervisor 
Token
Shadow Stack Usage with Privilege-Level Change from Level 2 or 1
Handler’s Shadow Stack
CSInterrupted Procedure’s
SSP Before
SSP After
Token
SSPLIPVol. 1 6-17PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
If a stack switch does occur, the processor does the following:
1. Temporarily saves (internally) the current contents of the SS, ESP, EFLAGS, CS, and EIP registers.
2. Loads the segment selector and stack pointer for the new stack (that is, the stack for the privilege level being 
3. Pushes the temporarily saved SS, ESP, EFLAGS, CS, and EIP values for the interrupted procedure’s stack onto 
the new stack.
If shadow stack is enabled at the privilege level of th e interrupted procedure, then the processor temporarily 
saves the SSP of the interrupted proced ure internally. If the interrupted proc edure is at privilege level 3, the 
SSP of the interrupted procedure is also saved into the IA32_PL3_SSP MSR.
If shadow stack is enabled at the privilege level being called, then the SSP for the called privilege level is 
obtained from one of the MSRs listed below, depending on  the target privilege level. The SSP obtained is then 
— IA32_PL2_SSP if transitioning to ring 2.
— IA32_PL1_SSP if transitioning to ring 1.
If shadow stack is enabled at the privilege level being called and the interrupted procedure was not at privilege 
level 3, then the processor pushes the temporarily save d CS, LIP (CS.base + EIP), and SSP of the interrupted 
procedure to the new shadow stack.1
4. Pushes an error code on the new stack (if appropriate).
5. Loads the segment selector for the new code segment an d the new instruction pointer (from the interrupt gate 
6. If the call is through an interrupt gate, cl ears the IF flag in the EFLAGS register.
7. Begins execution of the handler procedure at the new privilege level.

A return from an interrupt or exception handler is initiated with the IRET instruction. The IRET instruction is similar 
to the far RET instruction, except that it also restores th e contents of the EFLAGS register for the interrupted proce-
dure. When executing a return from an interrupt or exce ption handler from the same privilege level as the inter-
rupted procedure, the processor performs these actions:
1. Restores the CS and EIP registers to their values prior to the interrupt or exception.
a. Compares the values on the shadow stack at addre ss SSP+8 (the LIP) and SSP+16 (the CS) to the CS and 
b. Pops the top-of-stack value (the SSP prior to the interrupt or exception) from the shadow stack into the SSP 
register.
2. Restores the EFLAGS register.3. Increments the stack pointer appropriately.
4. Resumes execution of the interrupted procedure.
When executing a return from an interrupt or exception ha ndler from a different privilege level than the interrupted 
procedure, the processor performs these actions:
1. Performs a privilege check.2. Restores the CS and EIP registers to their values prior to the interrupt or exception.
3. Restores the EFLAGS register.
1. If any of these pushes leads to an exception or a VM  exit, the supervisor shadow -stack token remains busy.6-18 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
If shadow stack is enabled at  the current privilege level:
— If SSP is not aligned to 8 bytes, then causes a control protection exception (#CP(FAR-RET/IRET)).
•Compares the values on the shadow stack at addre ss SSP+8 (the LIP) and SSP+16 (the CS) to the CS 
and (CS.base + EIP) popped from the stack, and causes a control protection exception (#CP(FAR-
— If the privilege level of the procedure being returned to is less than 3 (returning to supervisor mode), 
restores the SSP register from the internally saved value.
enabled at privilege level 3, then restores the SS P register with the value of the IA32_PL3_SSP MSR.
4. Restores the SS and ESP registers to their values prior to  the interrupt or exception, resulting in a stack switch 
back to the stack of the interrupted procedure.
5. Resumes execution of the interrupted procedure.
6.5.2 Calls to Interrupt or Exception Handler Tasks
Interrupt and exception handler routines can also be executed in a separate task. Here, an interrupt or exception 
causes a task switch to a handler task. The handler task is given its own address space and (optionally) can execute 
at a higher protection level than application programs or tasks. 
The switch to the handler task is accomplished with an implicit task call that references a task gate descriptor . 
The task gate provides access to the address space for the handler task. As part of the task switch, the processor 
saves complete state information for the interrupted program or task. Upon returning from the handler task, the 
state of the interrupted program or task is restored and execution continues. See Chapter 6, “Interrupt and Excep-
tion Handling,” in the Intel® 64 and IA-32 Architectures Software Develo per’s Manual, Volume 3A, for more infor-
mation on handling interrupts and exceptions through handler tasks.
6.5.3 Interrupt and Exception Handling in Real-Address Mode
When operating in real-address mode, the processor responds to an interrupt or exception with an implicit far call 
to an interrupt or exception handler. The processor uses th e interrupt or exception vector as an index into an inter-
rupt table. The interrupt table contains instruction pointers to the interrupt and exception handler procedures.
The processor saves the state of the EFLAGS register, the EI P register, the CS register, and an optional error code 
on the stack before switching to the handler procedure.
A return from the interrupt or exception handle r is carried out with the IRET instruction. 
See Chapter 21, “8086 Emulation,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
3B, for more information on handling inte rrupts and exceptions in real-address mode.
6.5.4 INT n, INTO, INT3, INT1, and BOUND Instructions
The INT n, INTO, INT3, and BOUND instructions allow a program or task to explicitly call an interrupt or exception 
handler. The INT n instruction (opcode CD) uses a vector as an argument, which allows a program to call any inter-
rupt handler.
The INTO instruction (opcode CE) explicitly calls the overfl ow exception (#OF) handler if the overflow flag (OF) in 
the EFLAGS register is set. The OF flag indicates overflow  on arithmetic instructions, but it does not automatically 
raise an overflow exception. An overflow exception can only  be raised explicitly in either of the following ways:Vol. 1 6-19PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
•Execute the INTO instruction.
•Test the OF flag and execute the INT n instruction with an argument of 4 (the vector of the overflow exception) 
if the flag is set.
Both the methods of dealing with overflow conditions allow a program to test for overflow at specific places in the 
instruction stream.
The INT3 instruction (opcode CC) explicitly calls the br eakpoint exception (#BP) handler. Similarly, the INT1 
instruction (opcode F1) explicitly calls the debug exception (#DB) handler.1
The BOUND instruction explicitly calls the BOUND-range ex ceeded exception (#BR) handler if an operand is found 
to be not within predefined boundaries in memory. This in struction is provided for checking references to arrays 
and other data structures. Like the overflow exception, the BOUND-range exceeded exception can only be raised 
explicitly with the BOUND instruction or the INT n instruction with an argument of 5 (the vector of the bounds-
check exception). The processor does not implicitly pe rform bounds checks and raise the BOUND-range exceeded 
6.5.5 Handling Floating-Point Exceptions
When operating on individual or packed floating-point valu es, the IA-32 architecture supports a set of six floating-
point exceptions. These exceptions can be generated during  operations performed by the x87 FPU instructions or 
by SSE/SSE2/SSE3 instructions. When an x87 FPU instruction (including the FISTTP instruction in SSE3) generates 
one or more of these exceptions, it in turn gene rates floating-point error exception (#MF); when an 
SSE/SSE2/SSE3 instruction generates a floating-point exception, it in turn generates SIMD floating-point excep-tion (#XM). 
See the following sections for further descriptions of the floating-point exceptions, how they are generated, and 
how they are handled:
•Section 4.9.1, “Floating-Point Exception Conditions,” an d Section 4.9.3, “Typical Actions of a Floating-Point 
Exception Handler.”
•Section 8.4, “x87 FPU Floating-Point Exception Handling ,” and Section 8.5, “x87 FPU Floating-Point Exception 
Conditions.”
•Section 11.5.1, “SIMD Floating-Point Exceptions.”
•Interrupt Behavior.
6.5.6 Interrupt and Exception Behavior in 64-Bit Mode
64-bit extensions expand the legacy IA-32 interrupt-pro cessing and exception-processing mechanism to allow 
support for 64-bit operating systems and applications. Changes include:
•All interrupt handlers pointed to by the IDT are 64-bit code (does not appl y to the SMI handler).
•The size of interrupt-stack pushes is fixed at 64 bi ts. The processor uses 8-byte, zero extended stores.
•The stack pointer (SS:RSP) is pushed unconditionally on  interrupts. In legacy environments, this push is 
conditional and based on a change in current privilege level (CPL).
•The new SS is set to NULL if there is a change in CPL.
•IRET behavior changes.
•There is a new interrupt stack-switch mechanism an d a new interrupt shadow stack-switch mechanism.
•The alignment of interrupt stack frame is different.
1. Hardware vendors may use the INT1 instru ction for hardware debug. For that reason, Intel recommends software vendors instead 
use the INT3 instruction for software breakpoints.6-20 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
6.6 PROCEDURE CALLS FOR BL OCK-STRUCTURED LANGUAGES
The IA-32 architecture supports an alternate method of performing procedure calls with the ENTER (enter proce-
dure) and LEAVE (leave procedure) instructions. These instructions automatically create and release, respectively,

dure) and LEAVE (leave procedure) instructions. These instructions automatically create and release, respectively, 
stack frames for called procedures. The stack frames have predefined spaces for local variables and the necessary pointers to allow coherent returns from called procedures. They also allow scope rules to be implemented so that 
procedures can access their own local variables and some number of other variables located in other stack frames.
ENTER and LEAVE offer two benefits:
•They provide machine-langua ge support for implementing block-struct ured languages, such as C and Pascal. 
•They simplify procedure entry and exit in compiler-generated code.
6.6.1 ENTER Instruction
The ENTER instruction creates a stack frame compatible with the scope rules typically used in block-structured 
languages. In block-structured languages, the scope of a procedure is the set of variables to which it has access. 
The rules for scope vary among language s. They may be based on the nesting of procedures, the division of the 
program into separately compiled files,  or some other modularization scheme.
ENTER has two operands. The first specifies the number of bytes to be reserved on the stack for dynamic storage 
for the procedure being called. Dynamic storage is the me mory allocated for variables created when the procedure 
is called, also known as automatic variables. The second pa rameter is the lexical nesting level (from 0 to 31) of the 
procedure. The nesting level is the depth of a procedure in  a hierarchy of procedure calls. The lexical level is unre-
lated to either the protection privilege level or to the I/ O privilege level of the currently running program or task.
ENTER, in the following example, allocates 2 Kbytes of dy namic storage on the stack and sets up pointers to two 
previous stack frames in the stack frame for this procedure:
ENTER 2048,3
The lexical nesting level determines the number of stack fr ame pointers to copy into the new stack frame from the 
preceding frame. A stack frame pointer is a doubleword us ed to access the variables of a procedure. The set of 
stack frame pointers used by a procedure to access the variab les of other procedures is called the display. The first 
doubleword in the display is a pointer to the previous stac k frame. This pointer is used by a LEAVE instruction to 
undo the effect of an ENTER instruction by discarding the current stack frame.
After the ENTER instruction creates the display for a procedure, it allocates the dynamic local variables for the 
procedure by decrementing the contents of the ESP register  by the number of bytes specif ied in the first parameter. 
This new value in the ESP register serves as the initial top-of-stack for all PUSH and POP operations within the 
To allow a procedure to address its display, the ENTER in struction leaves the EBP register pointing to the first 
doubleword in the display. Because stacks grow down, this is actually the doubleword with the highest address in 
the display. Data manipulation instructions that specify the EBP register as a base register automatically address 
locations within the stack segment instead of the data segment.
The ENTER instruction can be used in two ways: nested and non-nested. If the lexical level is 0, the non-nested 
form is used. The non-nested form pushes the contents of the EBP register on the stack, copies the contents of the 
ESP register into the EBP register, and subtracts the first op erand from the contents of the ESP register to allocate 
dynamic storage. The non-nested form di ffers from the nested form in that no  stack frame pointers are copied. The 
nested form of the ENTER instruction occurs when the second parameter (lexical level) is not zero.
The following pseudo code shows the fo rmal definition of the ENTER instruction. STORAGE is the number of bytes 
of dynamic storage to allocate for local vari ables, and LEVEL is th e lexical nesting level.Vol. 1 6-21PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
PUSH EBP;
FRAME_PTR := ESP;IF LEVEL > 0 
THEN
DO (LEVEL − 1) times
EBP := EBP − 4;
PUSH Pointer(EBP); (* doubleword pointed to by EBP *)
OD;
PUSH FRAME_PTR;
FI;EBP := FRAME_PTR;ESP := ESP − STORAGE;
The main procedure (in which all other procedures are nest ed) operates at the highest lexical level, level 1. The 
first procedure it calls operates at the next deeper lexical level, level 2. A level 2 procedure can access the variables 
of the main program, which are at fixed locations specif ied by the compiler. In the case of level 1, the ENTER 
instruction allocates only the requested dynamic storage on the stack because there is no previous display to copy.
A procedure that calls another procedure at a lower lexica l level gives the called procedure access to the variables 
of the caller. The ENTER instruction provides this access by  placing a pointer to the calling procedure's stack frame 
in the display.
A procedure that calls another procedure at the same lexica l level should not give access to its variables. In this 
case, the ENTER instruction copies only that part of the display from the calling procedure which refers to previ-
ously nested procedures operating at higher lexical levels. The new stack frame does not include the pointer for 
addressing the calling procedure’s stack frame.
The ENTER instruction treats a re-entrant procedure as a call  to a procedure at the same lexical level. In this case, 
each succeeding iteration of the re-entrant procedure can address only its own variables and the variables of the 
procedures within which it is nested. A re-entrant proc edure always can address its own variables; it does not 
require pointers to the stack frames of previous iterations.
By copying only the stack frame pointers of procedures  at higher lexical levels, the ENTER instruction makes 
certain that procedures access only those variables of higher lexical levels, not those at parallel lexical levels (see 
Figure 6-9).
Block-structured languages can use the lexical levels define d by ENTER to control access to the variables of nested 
procedures. In Figure 6-9, for example, if procedure A ca lls procedure B which, in turn, calls procedure C, then 
procedure C will have access to the variables of the MAIN  procedure and procedure A, but not those of procedure 
B because they are at the same lexical level. The following definition describes the access to variables for the nested procedures in Figure 6-9.
1. MAIN has variables at fixed locations.2. Procedure A can access only the variables of MAIN.Figure 6-9.  Nested ProceduresMain (Lexical Level 1)  
Procedure A (Lexical Level 2)  
Procedure B (Lexical Level 3)  
Procedure C (Lexical Level 3)
Procedure D (Lexical Level 4)  6-22 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
3. Procedure B can access only the variables of procedur e A and MAIN. Procedure B cannot access the variables of 
procedure C or procedure D.
4. Procedure C can access only the variables of procedur e A and MAIN. Procedure C cannot access the variables of 
procedure B or procedure D.
5. Procedure D can access the variables of procedure C, procedure A, and MAIN. Procedure D cannot access the 
variables of procedure B.
In Figure 6-10, an ENTER instruction at the beginning of the MAIN procedure creates three doublewords of dynamic 
storage for MAIN, but copies no pointers from other stack frames. The first doubleword in the display holds a copy 
of the last value in the EBP register before the ENTER instruction was executed. The second doubleword holds a 
copy of the contents of the EBP register following the EN TER instruction. After the instruction is executed, the EBP 
register points to the first doubleword pushed on the stac k, and the ESP register points to the last doubleword in 
the stack frame.
When MAIN calls procedure A, the ENTER instruction create s a new display (see Figure 6-11). The first doubleword 
is the last value held in MAIN's EBP register. The second  doubleword is a pointer to MAIN's stack frame which is 
copied from the second doubleword in MAIN's display. This  happens to be another copy of the last value held in 
MAIN’s EBP register. Procedure A can access variables in MAIN because MAIN is at level 1. 
Therefore the base address for the dyna mic storage used in MAIN is the current address in the EBP register, plus 
four bytes to account for the saved contents of MAIN’s EB P register. All dynamic variab les for MAIN are at fixed, 
positive offsets from this value. 
Figure 6-10.  Stack Frame Afte r Entering the MAIN Procedure
Figure 6-11.  Stack Frame After Entering Procedure AEBP
DisplayOld EBP
ESPMain’s EBP
Dynamic
Storage
EBPDisplayOld EBP
Dynamic
StorageProcedure A’s EBPMain’s EBP
Main’s EBPVol. 1 6-23PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
When procedure A calls procedure B, the ENTER instruction creates a new display (see Figure 6-12). The first 
doubleword holds a copy of the last value in procedur e A’s EBP register. The second and third doublewords are 
copies of the two stack frame pointers in procedure A’s display. Procedure B can access variables in procedure A

Dynamic
Storage
Dynamic
copies of the two stack frame pointers in procedure A’s display. Procedure B can access variables in procedure A 
and MAIN by using the stack frame pointers in its display.
When procedure B calls procedure C, the ENTER inst ruction creates a new display for procedure C (see 
Figure 6-13). The first doubleword holds a copy of the last value in procedure B’s EBP register. This is used by the 
LEAVE instruction to restore procedure B’s stack frame. The second and third doublewords are copies of the two 
stack frame pointers in procedure A’s display. If procedur e C were at the next deeper lexical level from procedure 
B, a fourth doubleword would be copied, which would be the stack frame pointer to procedure B’s local variables. 
Note that procedure B and procedure C are at the same le vel, so procedure C is not intended to access procedure 
B’s variables. This does not mean that procedure C is co mpletely isolated from procedure B; procedure C is called 
by procedure B, so the pointer to the returning stack fram e is a pointer to procedure B’s stack frame. In addition, 
procedure B can pass parameters to procedure C either on th e stack or through variables global to both procedures 
(that is, variables in the scope of both procedures).
Figure 6-12.  Stack Frame After Entering Procedure BEBP
Dynamic
Main’s EBP
Procedure A’s EBP
Procedure B’s EBPMain’s EBP
Procedure A’s EBP6-24 Vol. 1PROCEDURE CALLS, INTERRU PTS, AND EXCEPTIONS
6.6.2 LEAVE Instruction
The LEAVE instruction, which does not have any operands, reverses the action of the previous ENTER instruction. 
The LEAVE instruction copies the contents of the EBP regist er into the ESP register to release all stack space allo-
cated to the procedure. Then it restores the old value of  the EBP register from the stack. This simultaneously 
restores the ESP register to its original value. A subsequent RET instruction then can remove any arguments and the return address pushed on the stack by the calling program for use by the procedure.Figure 6-13.  Stack Frame After Entering Procedure CEBP
Dynamic
Main’s EBP
Procedure B’s EBP
Procedure C’s EBPMain’s EBP
Procedure A’s EBPVol. 1 7-1CHAPTER 7
PROGRAMMING WITH
GENERAL-PURPOSE INSTRUCTIONS
General-purpose (GP) instructions are a subset of the IA- 32 instructions that represent the fundamental instruction 
set for the Intel IA-32 processors. These instructions were introduced into the IA-32 architecture with the first IA-
32 processors (the Intel 8086 and 8088). Additional instru ctions were added to the general-purpose instruction set 
in subsequent families of IA-32 processors (the Intel 28 6, Intel386, Intel486, Pentium, Pentium Pro, and Pentium 
II processors). 
Intel 64 architecture further extends the capability of most general-purpose instructions so that they are able to 
handle 64-bit data in 64-bit mode. A small number of gene ral-purpose instructions (still supported in non-64-bit 
modes) are not supported in 64-bit mode.
General-purpose instructions perform basic data movement , memory addressing, arithmetic and logical, program 
flow control, input/output, and string operations on a se t of integer, pointer, and BCD data types. This chapter 
provides an overview of the general-purpose instructions. See the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, for detailed descriptions of individual instructions.
7.1 PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS
The programming environment for the general-purpose instru ctions consists of the set of registers and address 
space. The environment includes the following items:
•General-purpose registers —  Eight 32-bit general-purpose registers (see Section 3.4.1, “General-Purpose 
Registers”) are used in non-64-bit modes to address op erands in memory. These registers are referenced by 
the names EAX, EBX, ECX, EDX, EBP, ESI EDI, and ESP. 
•Segment registers —  The six 16-bit segment registers contain segment pointers for use in accessing memory 
(see Section 3.4.2, “Segment Registers”). These register s are referenced by the names CS, DS, SS, ES, FS, and 
GS.
•EFLAGS register —  This 32-bit register (see Section 3.4.3, “EFLAGS Register”) is used to provide status and 
control for basic arithmetic, compare, and system operations. 
•EIP register —  This 32-bit register contains the current instruction pointer (see Section 3.5, “Instruction 
Pointer”). 
General-purpose instructions operate on  the following data types. The width of valid data types is dependent on 
processor mode (see Chapter 4):
•Bytes, words, doublewords.
•Signed and unsigned byte, word, doubleword integers.
•Near and far pointers.
•Bit fields.
•BCD integers.
7.2 PROGRAMMING ENVIRONMENT FOR GP  INSTRUCTIONS IN 64-BIT MODE
The programming environment for the general-purpose instruct ions in 64-bit mode is similar to that described in 
Section 7.1.
•General-purpose registers —  In 64-bit mode, sixteen general-purpose registers available. These include the 
eight GPRs described in Section 7.1 and eight new GPRs  (R8D-R15D). R8D-R15D are available by using a REX 
prefix. All sixteen GPRs can be promoted to 64 bits. The 64-bit registers are referenced as RAX, RBX, RCX, RDX, 
RBP, RSI, RDI, RSP, and R8-R15 (see Section 3.4.1.1, “General-Purpose Registers in 64-Bit Mode”). Promotion 
to 64-bit operand requires REX prefix encodings.7-2 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
•Segment registers —  In 64-bit mode, segmentation is available but it is set up uniquely (see Section 3.4.2.1, 
“Segment Registers in 64-Bit Mode”).
•Flags and Status register —  When the processor is running in 64 -bit mode, EFLAGS becomes the 64-bit 
RFLAGS register (see Section 3.4.3, “EFLAGS Register”).
•Instruction Pointer register —  In 64-bit mode, the EIP register becomes the 64-bit RIP register (see Section 
3.5.1, “Instruction Pointer in 64-Bit Mode”).
General-purpose instructions operate on the following data types in 64-bit mode. The width of valid data types is 
dependent on default operand size, address size, or a prefix that overrides the default size:
•Bytes, words, doublewords, quadwords.
•Signed and unsigned byte, word, doubleword, quadword integers.
See also: 
•Chapter 3, “Basic Execution Environment,” for more information about IA-32e modes.
•Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2A, for more detailed information about REX prefixes.
•Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, for a complete 
listing of all instructions. This information documents the behavior of individual instructions in the 64-bit mode 
context.
7.3 SUMMARY OF GP INSTRUCTIONS
General purpose instructions are divi ded into the following subgroups: 
•Data transfer.
•Binary arithmetic.
•Decimal arithmetic.
•Logical.
•Shift and rotate.
•Bit and byte.
•Control transfer.
•String.
•I/O.
•Enter and Leave.
•Flag control.
•Segment register.
•Miscellaneous.
Each sub-group of general-purpose instructions is discusse d in the context of non-64-bit mode operation first. 
Changes in 64-bit mode beyond those affected by the use of the REX prefixes are discussed in separate sub-
sections within each subgroup. For a simple list of general-purpose instructions by subgroup, see Chapter 5.
7.3.1 Data Transfer Instructions
The data transfer instructions move  bytes, words, doublewords, or qu adwords both between memory and the 
processor’s registers and between registers. For the purpos e of this discussion, these instructions are divided into 
subordinate subgroups that provide for:
•General data movement.Vol. 1 7-3PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
•Exchange.
•Stack manipulation.
•Type conversion.
7.3.1.1  General Data Movement Instructions
Move instructions —  The MOV (move) and CMOVcc (conditional mo ve) instructions transfer data between 
memory and registers or between registers.
The MOV instruction performs basic load data and stor e data operations between memory and the processor’s 
registers and data movement operations between registers. It handles data transfers along the paths listed in Table 
7-1. (See “MOV—Move to/from Control Registers” and “MOV—Move to/from Debug Registers” in Chapter 4, 
2A, for information on moving data to and from the control and debug registers.) 
The MOV instruction cannot move data from one memory lo cation to another or from one segment register to 
another segment register. Memory-to-memory moves are pe rformed with the MOVS (string move) instruction (see 
Section 7.3.9, “String Operations”). 
Conditional move instructions —  The CMOVcc instructions are a group of instructions that check the state of the

Conditional move instructions —  The CMOVcc instructions are a group of instructions that check the state of the 
status flags in the EFLAGS register an d perform a move operation if the flags are in a specified state. These instruc-
tions can be used to move a 16-bit or 32-bit value from me mory to a general-purpose register or from one general-
purpose register to another. The flag state being tested is  specified with a condition code (cc) associated with the 
instruction. If the condition is not satisfied, a move is  not performed and execution continues with the instruction 
following the CMOVcc instruction.
Table 7-2 shows mnemonics for CMOVcc instructions and th e conditions being tested for each instruction. The 
condition code mnemonics are appended to the letters “CMOV” to form the mnemonics for CMOVcc instructions. 
The instructions listed in Table 7-2 as pairs (for exam ple, CMOVA/CMOVNBE) are alternate names for the same 
instruction. The assembler provides these alternate names to make it easier to read program listings.
CMOVcc instructions are useful for optimizing small IF cons tructions. They also help eliminate branching overhead 
for IF statements and the possibility of branch mispredictions by the processor. 
These conditional move instructions are supported in the P6 family, Pentium 4, and Intel Xeon processors. Software 
can check if CMOVcc instructions are supported by checki ng the processor’s feature information with the CPUID 
instruction.Table 7-1.  Move Instruction Operations
Type of Data Movement Source → Destination
From memory to a register Memory location → General-purpose register
Memory location → Segment register
From a register to memory General-purpose register → Memory location
Segment register → Memory location
Between registers General-purpose register → General-purpose register
General-purpose register → Segment register
Segment register → General-purpose register
General-purpose register → Control register
Control register → General-purpose register
General-purpose register → Debug register
Debug register → General-purpose register
Immediate data to a register Immediate → General-purpose register
Immediate data to memory Immediate → Memory location7-4 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
7.3.1.2  Exchange Instructions 
The exchange instructions swap the cont ents of one or more operands and, in  some cases, perform additional oper-
ations such as asserting the LOCK signal or modifying flags in the EFLAGS register.
The XCHG (exchange) instruction swaps the contents of two operands. This instruction takes the place of three 
MOV instructions and does not require a temporary location to save the contents of one operand location while the other is being loaded. When a memory operand is used with  the XCHG instruction, the processor’s LOCK signal is 
automatically asserted. This instruction is thus useful for implementing semaphores or similar data structures for 
process synchronization. See “Bus Locking” in Chap ter 9, “Multiple-Processor Management,”of the Intel
® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on bus locking.
The BSWAP (byte swap) instruction reverses the byte order in a 32-bit register operand. Bit positions 0 through 7 
are exchanged with 24 through 31, and bit positions 8 th rough 15 are exchanged with  16 through 23. Executing 
this instruction twice in a row leaves the register with th e same value as before. The BSWAP instruction is useful for 
converting between “big-endian” and “li ttle-endian” data formats. This instruction also speeds execution of decimal 
arithmetic. (The XCHG instruction can be used to swap the bytes in a word.)
The XADD (exchange and add) instruction swaps two operands  and then stores the sum of the two operands in the 
destination operand. The status flags in the EFLAGS register  indicate the result of the addition. This instruction can 
be combined with the LOCK prefix (s ee “LOCK—Assert LOCK# Signal Prefix” in  Chapter 3, “Instruction Set Refer-
ence, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A) in a multiprocessing 
system to allow multiple processors to execute one DO loop.
The CMPXCHG (compare and exchange) and CMPXCHG8B (com pare and exchange 8 bytes) instructions are used 
to synchronize operations in systems that use multiple processors. The CMPXCHG instruction requires three oper-
ands: a source operand in a register, another source oper and in the EAX register, and a destination operand. If 
the values contained in the destination operand and the EAX register are equal, the destination operand is 
replaced with the value of the other source operand (the value not in the EAX register). Otherwise, the original Table 7-2.  Conditio nal Move Instructions
Instruction Mnemonic Status Flag  States Condition Description
Unsigned Conditional Moves  CMOVA/CMOVNBE (CF or ZF) =
 0 Above/not below or equal
  CMOVAE/CMOVNB CF = 0 Above or equal/not below
  CMOVNC CF = 0 Not carry  CMOVB/CMOVNAE CF = 1 Below/not above or equal
  CMOVC CF = 1 Carry
  CMOVBE/CMOVNA (CF or ZF) = 1 Below or equal/not above  CMOVE/CMOVZ ZF = 1 Equal/zero
  CMOVNE/CMOVNZ ZF = 0 Not equal/not zero
  CMOVP/CMOVPE PF = 1 Parity/parity even  CMOVNP/CMOVPO PF = 0 Not parity/parity odd
Signed Conditional Moves
  CMOVGE/CMOVNL (SF xor OF) = 0 Greater or equal/not less
  CMOVL/CMOVNGE (SF xor OF) = 1 Less/not greater or equal
  CMOVLE/CMOVNG ((SF xor OF) or ZF) = 1 Less or equal/not greater
  CMOVO OF = 1 Overflow  CMOVNO OF = 0 Not overflow
  CMOVS SF = 1 Sign (negative)
  CMOVNS SF = 0 Not sign (non-negative)Vol. 1 7-5PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
value of the destination operand is loaded in the EAX register. The status flags in the EFLAGS register reflect the 
result that would have been obtained by subtracting th e destination operand from the value in the EAX register.
The CMPXCHG instruction is commonly used for testing and modifying semaphores. It checks to see if a semaphore 
is free. If the semaphore is free, it is marked allocated; otherwise it gets the ID of the current owner. This is all done in one uninterruptible operation. In a single-processor system, the CMPXCHG instructio n eliminates the need to 
switch to protection level 0 (to disable interrupts) before executing multiple instructions to test and modify a sema-
phore. 
For multiple processor systems, CMPX CHG can be combined with the LOCK prefix to perform the compare and 
exchange operation atomically. (See “Locked Atomic Oper ations” in Chapter 9, “Multiple-Processor Management,” 
of the Intel
® 64 and IA-32 Architectures Software Developer’s Ma nual, Volume 3A, for more information on atomic 
operations.)
The CMPXCHG8B instruction also requires three operands: a 64-bit value in EDX:EAX, a 64-bit value in ECX:EBX, 
and a destination operand in memory. The instruction comp ares the 64-bit value in the EDX:EAX registers with the 
destination operand. If they are equal, the 64-bit valu e in the ECX:EBX registers is stored in the destination 
operand. If the EDX:EAX registers and the destination ar e not equal, the destination is loaded in the EDX:EAX 
registers. The CMPXCHG8B instruction can be combined with  the LOCK prefix to perform the operation atomically.
7.3.1.3  Exchange Instructions in 64-Bit Mode 
The CMPXCHG16B instruction is available in 64-bit mode on ly. It is an extension of the functionality provided by 
CMPXCHG8B that operates on 128-bits of data.
7.3.1.4  Stack Manipulation Instructions
The PUSH, POP, PUSHA (push all registers), and POPA (pop all registers) instructions move data to and from the 
stack. The PUSH instruction decrements the stack pointer (c ontained in the ESP register), then copies the source 
operand to the top of stack (see Figure 7-1). It operates  on memory operands, immediate operands, and register 
operands (including segment registers). The PUSH instruct ion is commonly used to place parameters on the stack 
before calling a procedure. It can also be used to reserve space on the stack for temporary variables.
The PUSHA instruction saves the contents of the eight general-purpose registers on the stack (see Figure 7-2). 
This instruction simplifies procedure calls by reducing the number of instructions required to save the contents of 
the general-purpose registers. The registers are pushed on the stack in the following order: EAX, ECX, EDX, EBX, 
the initial value of ESP before EA X was pushed, EBP, ESI, and EDI. Figure 7-1.  Operation of the PUSH Instruction0Stack
31Before Pushing Doubleword
Growth
ESP
n − 4
n − 8nStack
0 31After Pushing Doubleword
ESP Doubleword Value7-6 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
The POP instruction copies the word or doubleword at the cu rrent top of stack (indicated by the ESP register) to the 
location specified with the destination operand. It then in crements the ESP register to point to the new top of stack 
(see Figure 7-3). The destination operand may specify a gene ral-purpose register, a segment register, or a memory 
location.

Growth
ESP
n − 4
n − 8nStack
location. 
The POPA instruction reverses the effect of the PUSHA inst ruction. It pops the top eight words or doublewords from 
the top of the stack into the general-purpose registers, ex cept for the ESP register (see  Figure 7-4). If the operand-
size attribute is 32, the doublewords on the stack are transf erred to the registers in the following order: EDI, ESI, 
EBP, ignore doubleword, EBX, EDX, ECX,  and EAX. The ESP register is restored  by the action of popping the stack. 
If the operand-size attribute is 16, the words on the stack are transferred to the registers in the following order: DI, 
SI, BP, ignore word, BX, DX, CX, and AX.Figure 7-2.  Operation of the PUSHA Instruction
Figure 7-3.  Operation of the POP Instruction0Stack31Before Pushing Registers
Growth
ESP n - 4
n - 8nStack
0 31After Pushing Registers
ESPEAX
EDIEBX
EBPECX
EDX
Old ESP
ESI
n - 36n - 20
n - 28n - 12
n - 16
n - 24
n - 32
0 31StackAfter Popping Doubleword
Growth
ESP n - 4
n - 8nStack
Before Popping Doubleword
ESP Doubleword Value0 31Vol. 1 7-7PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
7.3.1.5  Stack Manipulation Instructions in 64-Bit Mode
In 64-bit mode, the stack pointer size is 64 bits and cannot be overridden by an instruction prefix. In implicit stack 
references, address-size overrides are ignored. Pushes an d pops of 32-bit values on the stack are not possible in 
64-bit mode. 16-bit pushes and pops are supported by us ing the 66H operand-size pr efix. PUSHA, PUSHAD, POPA, 
and POPAD are not supported.
7.3.1.6  Type Conversion Instructions
The type conversion instructions convert bytes into word s, words into doublewords, and doublewords into quad-
words. These instructions are especially useful for conver ting integers to larger integer formats, because they 
perform sign extension (see Figure 7-5).
Two kinds of type conversion instructions are provided: simple conversion and move and convert.
Simple conversion —  The CBW (convert byte to word), CWDE (c onvert word to doubleword extended), CWD 
(convert word to doubleword), and CDQ (convert doublewo rd to quadword) instructions perform sign extension to 
double the size of the source operand.
The CBW instruction copies the sign (bit 7) of the byte in th e AL register into every bit position of the upper byte of 
the AX register. The CWDE instruction copies the sign (bit 15)  of the word in the AX register into every bit position 
of the high word of the EAX register.
The CWD instruction copies the sign (bit 15) of the word in the AX register into every bit position in the DX register. 
The CDQ instruction copies the sign (bit 31) of the doublewo rd in the EAX register into every bit position in the EDX 
register. The CWD instruction can be used to produce a do ubleword dividend from a word before a word division, 
and the CDQ instruction can be used to produce a quadword  dividend from a doubleword before doubleword divi-
sion.Figure 7-4.  Operation of the POPA Instruction
Figure 7-5.  Sign ExtensionStackAfter Popping Registers
Growth
ESP n - 4
n - 8nStack
Before Popping Registers
ESPEAX
EDIEBX
EBPECX
EDX
Ignored
ESI
n - 36n - 20
n - 28n - 12
n - 16
n - 24
n - 3203 1 03 1
31
After Sign15 0
SNNNNNNNNN N NN N N N SSSSSSSSSSS SSSSSExtensionBefore Sign15 0
SNNNNNNNNN N NN N N NExtension7-8 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
Move with sign or zero extension —  The MOVSX (move with sign extens ion) and MOVZX (move with zero 
extension) instructions move the source operand into a register then perform the sign extension.
The MOVSX instruction extends an 8-bit value to a 16-bit valu e or an 8-bit or 16-bit value to a 32-bit value by sign 
extending the source operand, as shown in Figure 7-5. The MOVZX instruction extends an 8-bit value to a 16-bit 
value or an 8-bit or 16-bit value to a 32-bit value by zero extending the source operand.
7.3.1.7  Type Conversion Instructions in 64-Bit Mode
The MOVSXD instruction operates on 64-bit data. It sign-ext ends a 32-bit value to 64 bits. This instruction is not 
encodable in non-64-bit modes.
7.3.2 Binary Arithmetic Instructions
Binary arithmetic instructions operate on 8-, 16-, and 32- bit numeric data encoded as signed or unsigned binary 
integers. The binary arithmetic  instructions may also be used in algori thms that operate on decimal (BCD) values.
For the purpose of this discussion, these instructions are divided into subordinate subgroups of instructions that:
•Add and subtract.
•Increment and decrement.
•Compare and change signs.
•Multiply and divide.
7.3.2.1  Addition and Subtraction Instructions
The ADD (add integers), ADC (add integers with carry), SU B (subtract integers), and SBB (subtract integers with 
borrow) instructions perform addition and subtraction operations on signed or unsigned integer operands.
The ADD instruction computes the sum of two integer operands. 
The ADC instruction computes the sum of two integer operands, plus 1 if the CF flag is se t. This instruction is used 
to propagate a carry when adding numbers in stages. 
The SUB instruction computes the difference of two integer operands. 
The SBB instruction computes the difference of two integer op erands, minus 1 if the CF flag is set. This instruction 
is used to propagate a borrow when subtracting numbers in stages.
7.3.2.2  Increment and Decrement Instructions
The INC (increment) and DEC (decrement) instructions add 1 to or subtract 1 from an unsigned integer operand, 
respectively. A primary use of these instructions is for implementing counters.
7.3.2.3  Increment and Decrement Instructions in 64-Bit Mode
The INC and DEC instructions are supported in 64-bit mo de. However, some forms of INC and DEC (the register 
operand being encoded using register extension field in  the MOD R/M byte) are not encodable in 64-bit mode 
because the opcodes are treated as REX prefixes.
7.3.2.4  Comparison and Sign Change Instructions
The CMP (compare) instruction computes the difference be tween two integer operands and updates the OF, SF, ZF, 
AF, PF, and CF flags according to the result. The source operands are not modified, nor is the result saved. The CMP 
instruction is commonly used in conjunction with a J cc (jump) or SET cc (byte set on condition) instruction, with the 
latter instructions performing an action based on the result of a CMP instruction.
The NEG (negate) instruction subtracts a signed integer operand from zero. The effect of the NEG instruction is to 
change the sign of a two's complement operand while keeping its magnitude.Vol. 1 7-9PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
7.3.2.5  Multiplication and Division Instructions
The processor provides two multiply instructions, MUL ( unsigned multiply) and IMUL (signed multiply), and two 
divide instructions, DIV (unsigned divide) and IDIV (signed divide).
The MUL instruction multiplies two unsigned integer operands . The result is computed to twice the size of the 
source operands (for example, if word operands are being multiplied, the result is a doubleword).
The IMUL instruction multiplies two sign ed integer operands. The result is computed to twice the size of the source 
operands; however, in some cases the result is truncated to the size of the source operands (see “IMUL—Signed 
Multiply” in Chapter 3, “Instruction  Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 2A).
The DIV instruction divides one unsi gned operand by another unsigned op erand and returns a quotient and a 
remainder.
The IDIV instruction is identical to the DIV instruct ion, except that IDIV performs a signed division.
7.3.3 Decimal Arithmetic Instructions
Decimal arithmetic can be performed by combining the bi nary arithmetic instructions ADD, SUB, MUL, and DIV 
(discussed in Section 7.3.2, “Binary Arit hmetic Instructions”) with the decimal arithmetic instructions. The decimal 
arithmetic instructions are provided to carry out the following operations:
•To adjust the results of a previous binary arit hmetic operation to produce a valid BCD result.
•To adjust the operands of a subsequent binary arithmet ic operation so that the operation will produce a valid 
BCD result. 
These instructions operate on both packed and unpacke d BCD values. For the purpose of this discussion, the 
decimal arithmetic instructions are divided into su bordinate subgroups of in structions that provide:
•Packed BCD adjustments.
•Unpacked BCD adjustments.
7.3.3.1  Packed BCD Adjustment Instructions
The DAA (decimal adjust after addition) and DAS (decimal ad just after subtraction) instructions adjust the results 
of operations performed on packed BCD integers (see Section 4.7, “BCD and Packed BCD Integers”). Adding two 
packed BCD values requires two instructions: an ADD in struction followed by a DAA in struction. The ADD instruc-
tion adds (binary addition) the two values and stores the re sult in the AL register. The DAA instruction then adjusts

tion adds (binary addition) the two values and stores the re sult in the AL register. The DAA instruction then adjusts 
the value in the AL register to obtain a valid, 2-digit, packed BCD value and sets the CF flag if a decimal carry 
occurred as the result of the addition.
Likewise, subtracting one packed BCD value from another re quires a SUB instruction followed by a DAS instruction. 
The SUB instruction subtracts (binary subtraction) one BC D value from another and stores the result in the AL 
register. The DAS instruction then adjusts the value in the AL register to obtain a valid, 2-digit, packed BCD value 
and sets the CF flag if a decimal borrow o ccurred as the result of the subtraction. 
7.3.3.2  Unpacked BCD Adjustment Instructions
The AAA (ASCII adjust after addition),  AAS (ASCII adjust after subtraction), AAM (ASCII adjust after multiplica-
tion), and AAD (ASCII adjust before division) instructions adjust the results of arithmetic operations performed on unpacked BCD values (see Section 4.7, “BCD and Pack ed BCD Integers”). All these instructions assume that 
the value to be adjusted is stored in the AL regi ster or, in one instance, the AL and AH registers. 
The AAA instruction adjusts the contents of the AL regist er following the addition of two unpacked BCD values. It 
converts the binary value in the AL register into a decimal value and stores the result in the AL register in unpacked 
BCD format (the decimal number is stored in the lower 4 bits  of the register and the upper 4 bits are cleared). If a 
decimal carry occurred as a result of the addition, the CF fl ag is set and the contents of the AH register are incre-
mented by 1.7-10 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
The AAS instruction adjusts the contents of the AL regist er following the subtraction of two unpacked BCD values. 
Here again, a binary value is converted into an unpacke d BCD value. If a borrow was required to complete the 
decimal subtract, the CF flag is set and the contents of the AH register are decremented by 1.
The AAM instruction adjusts the contents of the AL regist er following a multiplication of two unpacked BCD values. 
It converts the binary value in the AL register into a decimal value and stores the least significant digit of the result 
in the AL register (in unpacked BCD format) and the most sign ificant digit, if there is one, in the AH register (also 
in unpacked BCD format).
The AAD instruction adjusts a two-digit BCD value so that when the value is divided with the DIV instruction, a valid 
unpacked BCD result is obtained. The instruction converts the BCD value in registers AH (most significant digit) and 
AL (least significant digit) into a binary  value and stores the result in register AL. When the value in AL is divided by 
an unpacked BCD value, the quotient and remainder wi ll be automatically encoded in unpacked BCD format.
7.3.4 Decimal Arithmetic Instructions in 64-Bit Mode
Decimal arithmetic instructions are not supported in 64 -bit mode, they are either invalid or not encodable.
7.3.5 Logical Instructions
The logical instructions AND, OR, XOR (exclusive or), and NOT perform the standard Boolean operations for which 
they are named. The AND, OR, and XOR instructions re quire two operands; the NOT instruction operates on a 
single operand.
7.3.6 Shift and Rotate Instructions
The shift and rotate instructions rearrange the bits with in an operand. For the purpose of this discussion, these 
instructions are further divided into subordinate subgroups of instructions that:
•Shift bits
•Double-shift bits (move them between operands)
•Rotate bits
7.3.6.1  Shift Instructions
The SAL (shift arithmetic left), SHL (shift logical left), SA R (shift arithmetic right), SHR (shift logical right) instruc-
tions perform an arithmetic or logical shift of the bits in a byte, word, or doubleword. 
The SAL and SHL instructions perform the same operation (s ee Figure 7-6). They shift the source operand left by 
from 1 to 31 bit positions. Empty bit positions are cleared. The CF flag is loaded with the last bit shifted out of the 
operand.Vol. 1 7-11PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
The SHR instruction shifts the source operand right by fr om 1 to 31 bit positions (see Figure 7-7). As with the 
SHL/SAL instruction, the empty bit positions are cleared and th e CF flag is loaded with the last bit shifted out of the 
operand.
The SAR instruction shifts the source operand right by fr om 1 to 31 bit positions (see Figure 7-8). This instruction 
differs from the SHR instruction in that it preserves the si gn of the source operand by clearing empty bit positions 
if the operand is positive or setting the empty bits if the operand is negative. Again, the CF flag is loaded with the 
last bit shifted out of the operand.
The SAR and SHR instructions can also be used to perfor m division by powers of 2 (see “SAL/SAR/SHL/SHR—Shift 
Instructions” in Chapter 4, “Instruction Set Reference, M-U,” of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2B).Figure 7-6.  SHL/SAL Instruction Operation
Figure 7-7.  SHR Instruction Operation1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1  1  1 XInitial State
CF00  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1  1  1  0 1After 1-bit SHL/SAL Instruction00  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1  1  1  0  0  0  0  0  0  0  0  0  0 0After 10-bit SHL/SAL InstructionOperand
1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1  1  1 XInitial StateCF00  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1  1 1After 1-bit SHR Instruction00  0  0  0  0  0  0  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0 0After 10-bit SHR InstructionOperand7-12 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
7.3.6.2  Double-Shift Instructions
The SHLD (shift left double) and SHRD (shift right double ) instructions shift a specified number of bits from one 
operand to another (see Figure 7-9). They are provided to facilitate operations on unaligned bit strings. They can 
also be used to implement a variety of bit string move operations. 
The SHLD instruction shifts the bits in the destination op erand to the left and fills the empty bit positions (in the 
destination operand) with bits shifted out of the source operand. The destination and so urce operands must be the 
same length (either words or doubleword s). The shift count can range from 0 to 31 bits. The result of this shift 
operation is stored in the destination operand, and the sour ce operand is not modified. The CF flag is loaded with 
the last bit shifted out of the destination operand.
The SHRD instruction operates the same as the SHLD instru ction except bits are shifted to the right in the destina-
tion operand, with the empty bit positions filled  with bits shifted out of the source operand.Figure 7-8.  SAR In struction Operation
Figure 7-9.  SHLD and SHRD Instruction Operations0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1  1 XInitial State (Positive Operand)CF
0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1 1After 1-bit SAR Instruction
1  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1  1 XInitial State (Negative Operand)Operand
1  1  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  0  0  0  1  1 1After 1-bit SAR InstructionCF
Destination (Memory or Register) CF31 0
Source (Register)31 0
Source (Register)
31 0SHRD InstructionSHLD InstructionVol. 1 7-13PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
7.3.6.3  Rotate Instructions
The ROL (rotate left), ROR (rotate right), RCL (rotate through carry left) and RCR (rotate through carry right) 
instructions rotate the bits in the destination operan d out of one end and back through the other end (see 
Figure 7-10). Unlike a shift, no bits are lost during a rotation. The rotate count can range from 0 to 31.
The ROL instruction rotates the bits in the operand to th e left (toward more significant bit locations). The ROR 
instruction rotates the operand right (toward less significant bit locations).
The RCL instruction rotates the bits in the operand to the left , through the CF flag. This instruction treats the CF flag 
as a one-bit extension on the upper end of the operand. Each  bit that exits from the most significant bit location of 
the operand moves into the CF flag. At the same time, the bit in the CF flag enters the least significant bit location of the operand.
The RCR instruction rotates the bits in the operand to the right through the CF flag. For all the rotate instructions, the CF flag always contains the value of the last bit rotated out of the operand, even 
if the instruction does not use the CF flag as an extension of the operand. The value of this flag can then be tested

if the instruction does not use the CF flag as an extension of the operand. The value of this flag can then be tested 
by a conditional jump instruction (JC or JNC).
7.3.7 Bit and Byte Instructions
These instructions operate on bit or byte strings. For th e purpose of this discussion, they are further divided into 
subordinate subgroups that:
•Test and modify a single bit.
•Scan a bit string.
•Set a byte given conditions.
•Test operands and report results.Figure 7-10.  ROL, ROR, RCL, and RCR Instruction OperationsDestination (Memory or Register) CF31 0
Destination (Memory or Register) CF0 31
Destination (Memory or Register) CF31 0ROL Instruction
RCL Instruction
RCR InstructionROR Instruction7-14 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
7.3.7.1  Bit Test and Modify Instructions
The bit test and modify instructions (see Table 7-3) operat e on a single bit, which can be in an operand. The loca-
tion of the bit is specified as an offset from the least si gnificant bit of the operand. When the processor identifies 
the bit to be tested and modified, it first loads the CF flag  with the current value of the bit. Then it assigns a new 
value to the selected bit, as determined by the modify operation for the instruction. 
7.3.7.2  Bit Scan Instructions
The BSF (bit scan forward) and BSR (bit scan reverse) instructions scan a bit string in a source operand for a set bit 
and store the bit index of the first set bit found in a destin ation register. The bit index is the offset from the least 
significant bit (bit 0) in the bit string to the first set bit. The BSF instruction scans the source operand low-to-high 
(from bit 0 of the source operand toward the most significant bit); the BSR instruction scans high-to-low (from the most significant bit toward the least significant bit).
7.3.7.3  Byte Set on Condition Instructions
The SET cc (set byte on condition) instructions set a destinatio n-operand byte to 0 or 1, depending on the state of 
selected status flags (CF, OF, SF, ZF, and PF) in the EFLAGS register. The suffix ( cc) added to the SET mnemonic 
determines the condition being tested for. 
For example, the SETO instruction tests for overflow. If the OF flag is set, the destination byte is set to 1; if OF is 
clear, the destination byte is cleared to 0. Appendix B, “EFLAGS Condition Codes,” lists the conditions it is possible 
to test for with this instruction.
7.3.7.4  Test Instruction
The TEST instruction performs a logical AND of two operands and sets the SF, ZF, and PF flags according to the 
results. The flags can then be tested by the co nditional jump or loop instructions or the SET cc instructions. The 
TEST instruction differs from the AND instruction in  that it does not alter either of the operands.
7.3.8 Control Transfer Instructions
The processor provides both conditional and unconditional control transfer instructions to direct the flow of 
program execution. Conditional transfers are taken only fo r specified states of the status flags in the EFLAGS 
register. Unconditional control transfers are always executed.
For the purpose of this discussion, these instructions are further divided into subordinate subgroups that process:
•Unconditional transfers.
•Conditional transfers.
•Software interrupts.
7.3.8.1  Unconditional Transfer Instructions
The JMP, CALL, RET, INT, and IRET inst ructions transfer program control to another location (destination address) 
in the instruction stream. The destination can be within the same code segment (near transfer) or in a different 
code segment (far transfer).Table 7-3.  Bit Test and Modify Instructions
Instruction Effect on CF Flag Effect on Selected Bit
BT (Bit Test) CF flag ← Selected Bit No effect
BTS (Bit Test and Set) CF flag ← Selected Bit Selected Bit ← 1
BTR (Bit Test and Reset) CF flag ← Selected Bit Selected Bit ← 0
BTC (Bit Test and Complement) CF flag ← Selected Bit Selected Bit ← NOT (Selected Bit)Vol. 1 7-15PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
Jump instruction —  The JMP (jump) instruction unconditionally transfers program control to a destination 
instruction. The transfer is one-way; that is, a return address is not saved. A destination operand specifies the 
address (the instruction pointer) of the destination instruction. The address can be a relative address  or an 
absolute address .
A relative address  is a displacement (offset) with respect to the address in the EIP register. The destination 
address (a near pointer) is formed by adding the displace ment to the address in the EIP register. The displacement 
is specified with a signed integer, allowing jumps either forward or backward in the instruction stream.
An absolute address  is a offset from address 0 of a segment. It ca n be specified in either of the following ways:
•An address in a general-purpose register —  This address is treated as a near pointer, which is copied into 
the EIP register. Program execution then continues at  the new address within the current code segment.
•An address specified using the standard  addressing modes of the processor —  Here, the address can 
be a near pointer or a far pointer. If the address is for a near pointer, the address is translated into an offset and 
copied into the EIP register. If the address is for a far po inter, the address is translated into a segment selector 
(which is copied into the CS register) and an offset (which is copied into the EIP register).
In protected mode, the JMP instruction also allows jumps to a call gate, a task gate, and a task-state segment.
Call and return instructions —  The CALL (call procedure) and RET (return from procedure) instructions allow a 
jump from one procedure (or subroutine) to another and a subsequent jump back (return) to the calling procedure.
The CALL instruction transfers program control from the current (or calling) procedure to another procedure (the 
called procedure). To allow a subsequent return to the calling procedure, the CALL in struction saves the current 
contents of the EIP register on the stack before jumping to the called procedure. The EIP register (prior to trans-
ferring program control) contains the address of the instru ction following the CALL instruction. When this address 
is pushed on the stack, it is referred to as the return instruction pointer  or return address .
The address of the called procedure (the address of the fi rst instruction in the procedure being jumped to) is spec-
ified in a CALL instruction the same way as it is in a JM P instruction (see “Jump instruction” on page 7-15). The 
address can be specified as a relative address or an absolute  address. If an absolute addr ess is specified, it can be 
either a near or a far pointer.
The RET instruction transfers program control from the pr ocedure currently being executed (the called procedure) 
back to the procedure that called it (the calling procedur e). Transfer of control is accomplished by copying the 
return instruction pointer from the stack into the EIP register. Program execution then continues with the instruc-tion pointed to by the EIP register.
The RET instruction has an optional operand, the value of wh ich is added to the contents of the ESP register as part 
of the return operation. This operand allows the stack po inter to be incremented to remove parameters from the 
stack that were pushed on the stack by the calling procedure.
See Section 6.4, “Calling Procedures Using CALL and RET, ” for more information on the mechanics of making proce-
dure calls with the CALL  and RET instructions.
Return from interrupt instruction —  When the processor services an interrupt, it performs an implicit call to an 
interrupt-handling procedure. The IRET (return from interrupt) instruction returns program control from an inter-
rupt handler to the interrupted procedure (that is, the pr ocedure that was executing when the interrupt occurred). 
The IRET instruction performs a similar operation to the RE T instruction (see “Call and return instructions” on page 
7-15) except that it also restores the EFLAGS register from the stack. The contents of the EFLAGS register are 
automatically stored on the stack along with the return instruction pointer when the processor services an inter-
rupt.
7.3.8.2  Conditional Transfer Instructions
The conditional transfer instructions execute jumps or loops that transfer program control to another instruction in 
the instruction stream if specified conditions are met. The conditions for control transfer are specified with a set of 
condition codes that define various states of the status  flags (CF, ZF, OF, PF, and SF) in the EFLAGS register.
Conditional jump instructions —  The J cc (conditional) jump instructions transfer program control to a destina-
tion instruction if the conditions specified with the condition code ( cc) associated with the instruction are satisfied 
(see Table 7-4). If the condition is not satisfied, ex ecution continues with the instruction following the J cc instruc-
tion. As with the JMP instruction, the transfer is one-way; that is, a return address is not saved.7-16 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS

rupt.
The destination operand specifies a relative address (a signed  offset with respect to the address in the EIP register) 
that points to an instruction in the current code segment. The J cc instructions do not support far transfers; 
however, far transfers can be accomplished with a combination of a J cc and a JMP instruction (see “J cc—Jump if 
Condition Is Met” in Chapter 3, “Instruc tion Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2A).
Table 7-4 shows the mnemonics for the J cc instructions and the conditions being tested for each instruction. The 
condition code mnemonics are appended to th e letter “J” to form the mnemonic for a J cc instruction. The instruc-
tions are divided into two groups: unsigned and signed co nditional jumps. These groups correspond to the results 
of operations performed on unsigned and signed integers  respectively. Those instructions listed as pairs (for 
example, JA/JNBE) are alternate names for the same instru ction. Assemblers provide alternate names to make it 
easier to read program listings.
The JCXZ and JECXZ instructions test the CX and ECX register s, respectively, instead of one or more status flags. 
See “Jump if zero instructions” on page 7-17 for more information about these instructions.
Loop instructions —  The LOOP, LOOPE (loop while equal), LOOPZ (loop while zero), LOOPNE (loop while not 
equal), and LOOPNZ (loop while not zero) instructions are conditional jump instructions that use the value of the 
ECX register as a count for the number of times to execute a loop. All the loop instructions decrement the count in the ECX register each time they are executed and termin ate a loop when zero is reached. The LOOPE, LOOPZ, 
LOOPNE, and LOOPNZ instructions also accept the ZF flag as a condition for terminating the loop before the count 
reaches zero.
The LOOP instruction decrements the contents of the ECX re gister (or the CX register, if the address-size attribute 
is 16), then tests the register for the loop-termination condition. If the count in the ECX register is non-zero, 
program control is transferred to the instruction addre ss specified by the destination operand. The destination Table 7-4.  Conditiona l Jump Instructions 
Instruction Mnemonic Conditio n (Flag States) Description
Unsigned Conditional Jumps  JA/JNBE (CF or ZF) = 0 Above/not below or equal  JAE/JNB CF = 0 Above or equal/not below  JB/JNAE CF = 1 Below/not above or equal  JBE/JNA (CF or ZF) = 1 Below or equal/not above  JC CF = 1 Carry  JE/JZ ZF = 1 Equal/zero  JNC CF = 0 Not carry  JNE/JNZ ZF = 0 Not equal/not zero  JNP/JPO PF = 0 Not parity/parity odd  JP/JPE PF = 1 Parity/parity even  JCXZ CX = 0 Register CX is zero  JECXZ ECX = 0 Register ECX is zeroSigned Conditional Jumps  JG/JNLE ((SF xor OF) or ZF) = 0 Greater/not less or equal  JGE/JNL (SF xor OF) = 0 Greater or equal/not less  JL/JNGE (SF xor OF) = 1 Less/not greater or equal  JLE/JNG ((SF xor OF) or ZF) = 1 Less or equal/not greater  JNO OF = 0 Not overflow  JNS SF = 0 Not sign (non-negative)  JO OF = 1 Overflow  JS SF = 1 Sign (negative)Vol. 1 7-17PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
operand is a relative address (that is, an offset relative to  the contents of the EIP register), and it generally points 
to the first instruction in the block of code that is to be  executed in the loop. When the count in the ECX register 
reaches zero, program control is transferred to the instruction immediately following the LOOP instruction, 
which terminates the loop. If the count in the ECX register is zero when the LOOP instruction is first executed, the 
register is pre-decremented to FFFFFFFFH, causing the loop to be executed 232 times.
The LOOPE and LOOPZ instructions perform the same oper ation (they are mnemonics for the same instruction). 
These instructions operate the same as the LOOP instruction, except that they also test the ZF flag. 
If the count in the ECX register is not zero and the ZF flag  is set, program control is transferred to the destination 
operand. When the count reaches zero or the ZF flag is clea r, the loop is terminated by transferring program control 
to the instruction immediately following the LOOPE/LOOPZ instruction.
The LOOPNE and LOOPNZ instructions (mnemonics for the same instruction) operate the same as the 
LOOPE/LOOPZ instructions, except that they te rminate the loop if the ZF flag is set. 
Jump if zero instructions —  The JECXZ (jump if ECX zero) instruction ju mps to the location specified in the desti-
nation operand if the ECX register contains the value zero. This instruction can be used in combination with a loop 
instruction (LOOP, LOOPE, LOOPZ, LOOPNE, or LOOPNZ) to test the ECX register prior to beginning a loop. As 
described in “Loop instructions” on page 7-16, the loop instructions decrement the contents of the ECX register 
before testing for zero. If the value in the ECX register is zero initially, it will be decremented to FFFFFFFFH on the 
first loop instruction, causing the loop to be executed 232 times. To prevent this problem, a JECXZ instruction can 
be inserted at the beginning of the code block for the loop , causing a jump out of the loop if the ECX register count 
is initially zero. When used with repeated string scan  and compare instructions, the JECXZ instruction can deter-
mine whether the loop terminated because the count reache d zero or because the scan or compare conditions were 
satisfied.
The JCXZ (jump if CX is zero) instruction operates the sa me as the JECXZ instruction when the 16-bit address-size 
attribute is used. Here, the CX register is tested for zero.
7.3.8.3  Control Transfer Instructions in 64-Bit Mode
The listed instructions update the 64-bit RIP without need for a REX operand-size prefix. 
Near branches in the following operations are forced  to 64-bits (regardless of operand size prefixes):
•Size of a stack pop or push, due to CALL or RET.
•Size of a stack-pointer increment or  decrement, due to CALL or RET.
Note that the displacement field for relative branches is still limited to 32 bits and the address size for near 
branches is not forced.
Address size determines the register size (CX/ECX/RCX)  used for JCXZ and LOOP. It also impacts the address 
calculation for memory indirect branches. Addresses size is 64 bits by default, although it can be over-ridden to 32 
bits (using a prefix).
7.3.8.4  Software Interrupt Instructions
The INT n (software interrupt), INTO (interrupt on overflow),  and BOUND (detect value out of range) instructions 
allow a program to explicitly raise a specified interrupt or  exception, which in turn causes the handler routine for 
the interrupt or exception to be called.
The INT n instruction can raise any of the processor’s interrupts or exceptions by encoding the vector of the inter-
rupt or exception in the instruction. This instruction can be  used to support software generated interrupts or to test 
the operation of interrupt and exception handlers.
The IRET (return from interrupt) instruction returns program control from an interrupt handler to the interrupted 
procedure. The IRET instruction performs a similar operation to the RET instruction. 7-18 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
The CALL (call procedure) and RET (r eturn from procedure) instructions allow a jump from one procedure to 
another and a subsequent return to the calling procedure.  EFLAGS register contents are automatically stored on 
the stack along with the return instruction poin ter when the processor services an interrupt.
The INTO instruction raises the overflow exception if the OF  flag is set. If the flag is clear, execution continues 
without raising the exception. This instruction allows softwa re to access the overflow exception handler explicitly to 
check for overflow conditions.
The BOUND instruction compares a signed value against upper and lower bounds, and raises the “BOUND range 
exceeded” exception if the value is less than the lower bound  or greater than the upper bound. This instruction is 
useful for operations such as checking an array index to make sure it falls within the range defined for the array.
7.3.8.5  Software Interrupt Instructions  in 64-Bit Mode and Compatibility Mode
In 64-bit mode, the stack size is 8 bytes wide. IRET must  pop 8-byte items off the stack. SS:RSP pops uncondition-
ally. BOUND is not supported.
In compatibility mode, SS:RSP is popped only if the CPL changes.
7.3.9 String Operations
The GP instructions includes a set of string instructions  that are designed to access large data structures; these 
are introduced in Section 7.3.9.1. Section 7.3.9.2 describes  how REP prefixes can be used with these instructions 
to perform more complex repeated string operations . Certain processors optimize repeated string operations

to perform more complex repeated string operations . Certain processors optimize repeated string operations 
with fast-string operation , as described in Section 7.3.9.3. Section 7.3.9.4 explains how string operations can be 
used in 64-bit mode.
7.3.9.1  String Instructions
The MOVS (Move String), CMPS (Compa re string), SCAS (Scan string), LODS  (Load string), and STOS (Store 
string) instructions permit large data structures, such as  alphanumeric character strings, to be moved and exam-
ined in memory. These instructions operate on individual  elements in a string, which can be a byte, word, or 
doubleword. The string elements to be operated on are identified with the ESI (source string element) and EDI 
(destination string element) registers.  Both of these registers contain absolute addresses (offsets into a segment) 
that point to a string element. 
By default, the ESI register addresse s the segment identified with the DS segment register. A segment-override 
prefix allows the ESI register to be associated with th e CS, SS, ES, FS, or GS segment register. The EDI register 
addresses the segment identified with th e ES segment register; no segment override is allowed for the EDI register. 
The use of two different segment registers in the string in structions permits operations to be performed on strings 
located in different segments. Or by associating the ESI re gister with the ES segment register, both the source and 
destination strings can be located in the same segment. (T his latter condition can also be achieved by loading the 
DS and ES segment registers with the same segment select or and allowing the ESI register to default to the DS 
register.)
The MOVS instruction moves the string element addressed by  the ESI register to the location addressed by the EDI 
register. The assembler recognizes three “short forms” of this  instruction, which specify the size of the string to be 
moved: MOVSB (move byte string), MOVSW (move wo rd string), and MOVSD (move doubleword string).
The CMPS instruction subtracts the destination string el ement from the source string element and updates the 
status flags (CF, ZF, OF, SF, PF, and AF) in the EFLAGS register according to the results. Neither string element is 
written back to memory. The assembler recognizes three “s hort forms” of the CMPS instruction: CMPSB (compare 
byte strings), CMPSW (compare word strings) , and CMPSD (compare doubleword strings).
The SCAS instruction subtracts the destination string elem ent from the contents of the EAX, AX, or AL register 
(depending on operand length) and up dates the status flags according to the results. The string element and 
register contents are not modified. The following “short fo rms” of the SCAS instruction specify the operand length: 
SCASB (scan byte string), SCASW (scan word string), and SCASD (scan doubleword string).
The LODS instruction loads the source string element identi fied by the ESI register into the EAX register (for a 
doubleword string), the AX register (for a word string), or the AL register (for  a byte string). The “short forms” for Vol. 1 7-19PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
this instruction are LODSB (load byte string), LODSW (load word string), and LODSD (load doubleword string). This 
instruction is usually used in a loop, where other instructions process each element of the string after they are loaded into the target register.
The STOS instruction stores the source string element from  the EAX (doubleword string), AX (word string), or AL 
(byte string) register into the memory location identified wi th the EDI register. The “short forms” for this instruction 
are STOSB (store byte string), STOSW (store word string),  and STOSD (store doubleword string). This instruction 
is also normally used in a loop. Here a string is commonly  loaded into the register with a LODS instruction, oper-
ated on by other instructions, and then stored again in memory with a STOS instruction.
The I/O instructions (see Section 7.3.10, “I/O Instructions”) also perform operations on strings in memory.
7.3.9.2  Repeated String Operations
Each of the string instructions described in Section 7.3.9. 1 perform one iteration of a string operation. To operate 
on strings longer than a doubleword, the string instructions  can be combined with a repeat prefix (REP) to create a 
repeating instruction or be placed in a loop.
When used in string instructions, the ESI and EDI regi sters are automatically incremented or decremented after 
each iteration of an instruction to point to the next elem ent (byte, word, or doubleword) in the string. String oper-
ations can thus begin at higher addresses and work towa rd lower ones, or they can begin at lower addresses and 
work toward higher ones. The DF flag in the EFLAGS regi ster controls whether the registers are incremented (DF = 
0) or decremented (DF = 1). The STD and CLD inst ructions set and clear this flag, respectively.
The following repeat prefixes can be used in conjunction with a count in the ECX register to cause a string instruc-
tion to repeat:
•REP — Repeat while the ECX register not zero.
•REPE/REPZ — Repeat while the ECX register not zero and the ZF flag is set.
•REPNE/REPNZ  — Repeat while the ECX register not zero and the ZF flag is clear.
When a string instruction has a repeat prefix, the operatio n executes until one of the termination conditions spec-
ified by the prefix is satisfied. Th e REPE/REPZ and REPNE/REPNZ prefixes ar e used only with the CMPS and SCAS 
instructions. Also, note that a REP STOS instruction is the fastest way to initialize a large block of memory.
7.3.9.3  Fast-String Operation
To improve performance, more recent processors support modifications to the processor’s operation during the 
string store operations initiated with the MOVS, MOVSB, STOS, and STOSB instructions. This optimized operation, 
called fast-string operation , is used when the execution of one of those instructions meets certain initial condi-
tions (see below). Instructions using fast-string operation effectively operate on the string in groups that may 
include multiple elements of the native data size (byte,  word, doubleword, or quadword). With fast-string opera-
tion, the processor recognizes interrupts and data brea kpoints only on boundaries between these groups. Fast-
string operation is used only if the source and destinat ion addresses both use either the WB or WC memory types.
The initial conditions for fast-string operation are implemen tation-specific and may vary with the native string size. 
Examples of parameters that may impact the us e of fast-string operation include the following:
•The alignment indicated in the EDI and ESI alignment registers.
•The address order of the string operation.
•The value of the initial operation counter (ECX).
•The difference between the source and destination addresses.
NOTE
Initial conditions for fast-string operation in future Intel 64 or IA-32 processor families may differ 
from above. The Intel® 64 and IA-32 Architectu res Optimization Reference Manual may contain 
model-specific information.7-20 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
Software can disable fast-string operation by clearing the fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR. 
However, Intel recommends that system software always enable fast-string operation. 
When fast-string operation is enabled (because IA 32_MISC_ENABLE[0] = 1), some processors may further 
enhance the operation of the REP MOVSB and REP STOSB in structions. A processor supports these enhancements 
if CPUID.(EAX=07H, ECX=0H):EBX[bit 9]  is 1. The Intel® 64 and IA-32 Architectures Optimization Reference 
Manual may include model-specific recommen dations for use of these enhancements.
The stores produced by fast-string operation may appear  to execute out of order. Software dependent upon 
sequential store ordering should not use string operations for the entire data structure to be stored. Data and 
semaphores should be separated. Order-dependent code should write to a discrete semaphore variable after any string operations to allow correctly ordered data to be seen  by all processors. Atomicity of load and store operations 
is guaranteed only for native data elements of the string with native data size, and only if they are included in a 
single cache line. See Section 9.2.4, “Fast-String Operation and Out-of-Order Stores,” of the Intel
® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 3A.
7.3.9.4  String Operations in 64-Bit Mode
The behavior of MOVS (Move String), CMPS (Compare stri ng), SCAS (Scan string), LO DS (Load string), and STOS 
(Store string) instructions in 64-bit mode is similar to th eir behavior in non-64-bit modes, with the following differ-
ences:
•The source operand is specified by RSI or DS:ESI, depe nding on the address size attribute of the operation. 
•The destination operand is specified by RDI or DS:E DI, depending on the address size attribute of the 

ences:
operation. 
•Operation on 64-bit data is supported by using the REX.W prefix.
When using REP prefixes for string operations in 64-b it mode, the repeat count is specified by RCX or ECX 
(depending on the address size attribute of the operation). The default address size is 64 bits.
7.3.10 I/O Instructions
The IN (input from port to register), INS (input from port to string), OUT (output from register to port), and OUTS 
(output string to port) instructions move data between the processor’s I/O ports and either a register or memory.
The register I/O instructions (IN and OUT) move data be tween an I/O port and the EAX register (32-bit I/O), the 
AX register (16-bit I/O), or the AL (8-bit I/O) register. Th e I/O port being read or wri tten to is specified with an 
immediate operand or an address in the DX register. 
The block I/O instructions (INS and OUTS) instructions mo ve blocks of data (strings) between an I/O port and 
memory. These instructions operate similar to the string in structions (see Section 7.3.9, “String Operations”). The 
ESI and EDI registers are used to specify string elements in  memory and the repeat prefix (REP) is used to repeat 
the instructions to implement block moves. The assemble r recognizes the following alternate mnemonics for these 
instructions: INSB (input byte), INSW (input word), and INSD (input doubleword), and OUTSB (output byte), 
OUTSW (output word), and OUTSD (output doubleword).
The INS and OUTS instructions use an a ddress in the DX register to specify the I/O port to be read or written to.
7.3.11 I/O Instructions in 64-Bit Mode
For I/O instructions to and from memory, the differences in 64-bit mode are:
•Operation on 64-bit data is not encodable and REX prefixes are silently ignored.Vol. 1 7-21PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
7.3.12 Enter and Leave Instructions
The ENTER and LEAVE instructions provide machine-langua ge support for procedure calls in block-structured 
languages, such as C and Pascal. These instructions an d the call and return mechanism that they support are 
described in detail in Section 6.6, “Procedu re Calls for Block-Structured Languages.”
7.3.13 Flag Control (EFLAG) Instructions
The Flag Control (EFLAG) instructions allow the state of sele cted flags in the EFLAGS register to be read or modi-
fied. For the purpose of this discussion, these instructions are further divided into subordinate subgroups of 
instructions that manipulate:
•Carry and direction flags.
•The EFLAGS register.
•Interrupt flags.
7.3.13.1  Carry and Direction Flag Instructions
The STC (set carry flag), CLC (clear carry flag), and CMC (complement carry flag) instructions allow the CF flag in 
the EFLAGS register to be modified directly. They are typica lly used to initialize the CF flag to a known state before 
an instruction that uses the flag in an operation is execut ed. They are also used in conjunction with the rotate-with-
carry instructions (RCL and RCR).
The STD (set direction flag) and CLD (clear direction flag) in structions allow the DF flag in the EFLAGS register to 
be modified directly. The DF flag determines the direct ion in which index registers ESI and EDI are stepped when 
executing string processing instructions. If the DF flag is clear, the index registers are incremented after each iter-
ation of a string instruction; if the DF flag is set, the registers are decremented.
7.3.13.2  EFLAGS Transfer Instructions
The EFLAGS transfer instructions allow gr oups of flags in the EFLAGS register to be copied to a register or memory 
or be loaded from a register or memory. 
The LAHF (load AH from flags) and SAHF (store AH into fl ags) instructions operate on five of the EFLAGS status 
flags (SF, ZF, AF, PF, and CF). The LAHF instruction copies the status flags to bits 7, 6, 4, 2, and 0 of the AH register, 
respectively. The contents of the remaining bits in the regi ster (bits 5, 3, and 1) are unaffected, and the contents 
of the EFLAGS register remain unchanged. The SAHF instructio n copies bits 7, 6, 4, 2, and 0 from the AH register 
into the SF, ZF, AF, PF, and CF flags, respectively in the EFLAGS register.
The PUSHF (push flags), PUSHFD (push flags double), POPF (pop flags), and POPFD (pop flags double) instructions 
copy the flags in the EFLAGS register to and from the st ack. The PUSHF instruction pushes the lower word of the 
EFLAGS register onto the stack (see Fi gure 7-11). The PUSHFD instruction push es the entire EFLAGS register onto 
the stack (with the RF and VM flags read as clear).
The POPF instruction pops a word from the stack into the EFLA GS register. Only bits 11, 10, 8, 7, 6, 4, 2, and 0 of 
the EFLAGS register are affected with all uses of this inst ruction. If the current privil ege level (CPL) of the current Figure 7-11.  Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD InstructionsPUSHFD/POPFD
PUSHF/POPF
31 2930 28 2726 25 24232221 20 19 181716
0R
FI
DA
CV
M15 1314 12 1110 9 876 543 210
0C
FA
FP
F1D
FI
FT
FS
FZ
FN
I
PV
I
FO
FI
O
P
L7-22 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
code segment is 0 (most privileged), the IOPL bits (bits 13 and 12) also are affected. If the I/O privilege level 
(IOPL) is greater than or equal to the CPL, numerically, the IF flag (bit 9) also is affected. 
The POPFD instruction pops a doubleword into the EFLAGS re gister. This instruction can change the state of the AC 
bit (bit 18) and the ID bit (bit 21), as well as the bits af fected by a POPF instruction. The restrictions for changing 
the IOPL bits and the IF flag that were given for th e POPF instruction also apply to the POPFD instruction.
7.3.13.3  Interrupt Flag Instructions
The STI (set interrupt flag) and CLI (clear interrupt flag) instructions allow the interrupt IF flag in the EFLAGS 
register to be modified directly. The IF flag controls th e servicing of hardware-generat ed interrupts (those received 
at the processor’s INTR pin). If the IF flag is set, the proc essor services hardware interrupts; if the IF flag is clear, 
hardware interrupts are masked.
The ability to execute these instructions depends on the operating mode of the processor and the current privilege 
level (CPL) of the program or task atte mpting to execute these instructions.
7.3.14 Flag Control (RFLAG) Instructions in 64-Bit Mode
In 64-bit mode, the LAHF and SAHF instructions are supported if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.
PUSHF and POPF behave the same in 64-bit mode as in  non-64-bit mode. PUSHFD al ways pushes 64-bit RFLAGS 
onto the stack (with the RF and VM flags read as clear). PO PFD always pops a 64-bit value from the top of the stack 
and loads the lower 32 bits into RFLAGS. It then zero extends the upper bits of RFLAGS.
7.3.15 Segment Register Instructions
The processor provides a variety of instructions that addr ess the segment registers of the processor directly. These 
instructions are only used when an operating system or executive is using the segmented or the real-address mode 
memory model. 
For the purpose of this discussion, these instructions are divided into subordinate subgroups of instructions that 
allow:
•Segment-register load and store.
•Far control transfers.
•Software interrupt calls.
•Handling of far pointers.
7.3.15.1  Segment-Register Load and Store Instructions
The MOV instruction (introduced in Section 7.3.1.1, “Gener al Data Movement Instructions”) and the PUSH and POP 
instructions (introduced in Section 7.3.1.4, “Stack Manipu lation Instructions”) can transfer 16-bit segment selec-
tors to and from segment registers (DS, ES, FS, GS, and SS). The transfers are always made to or from a segment register and a general-purpose register or memory. Transfers between segment registers are not supported.
The POP and MOV instructions cannot place a value in the CS register. Only the far control-transfer versions of the 
JMP, CALL, and RET instructions (see Section 7.3.15.2, “Far  Control Transfer Instructions”) affect the CS register 
directly. 
7.3.15.2  Far Control Transfer Instructions
The JMP and CALL instructions (see Section 7.3.8, “Control Transfer Instructions”) both accept a far pointer as a 
destination to transfer program control to a segment othe r than the segment currently being pointed to by the CS 
register. When a far call is made with the CALL instructio n, the current values of the EIP and CS registers are both 
pushed on the stack.
The RET instruction (see “Call and return instructions” on page 7-15) can be used to execute a far return. Here, 
program control is transferred from a code segment that co ntains a called procedure back to the code segment that Vol. 1 7-23PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
contained the calling procedure. The RET instruction restores  the values of the CS and EIP registers for the calling 
procedure from the stack.
7.3.15.3  Software Interrupt Instructions

directly. 
The software interrupt instructions INT, INTO, and IRET (see Section 7.3.8.4, “Software Interrupt Instructions”) 
can also call and return from interrupt and exception hand ler procedures that are located in a code segment other 
than the current code segment. With these instructions, ho wever, the switching of code segments is handled trans-
parently from the application program.
7.3.15.4  Load Far Pointer Instructions
The load far pointer instructions LDS (load far pointer using DS), LES (load far pointer using ES), LFS (load far pointer using FS), LGS (load far pointer using GS), and LSS (load far pointer using SS) load a far pointer from 
memory into a segment register and a general-purpose general register. The segment selector part of the far 
pointer is loaded into the selected segment register and the offset is loaded into the selected general-purpose 
register.
7.3.16 Miscellaneous Instructions
The following instructions perform operations that are of interest to applications programmers. For the purpose of 
this discussion, these instructions are further divided into  subordinate subgroups of instructions that provide for:
•Address computations.
•Table lookup.
•Processor identification.
•NOP and undefined instruction entry.
7.3.16.1  Address Computation Instruction
The LEA (load effective address) instruction computes the effective address in memory (offset within a segment) 
of a source operand and places it in a general-purpose regi ster. This instruction can interpret any of the processor’s 
addressing modes and can perform any indexing or scaling th at may be needed. It is especially useful for initial-
izing the ESI or EDI registers before the execution of string instructions or for initializing the EBX register before an 
XLAT instruction. 
7.3.16.2  Table Lookup Instructions
The XLAT and XLATB (table lookup) instructions replace the contents of the AL register with a byte read from a 
translation table in memory. The initial value in the AL regi ster is interpreted as an unsigned index into the trans-
lation table. This index is added to the contents of the EB X register (which contains the base address of the table) 
to calculate the address of the table entry. These instructions are used for applications such as converting character 
codes from one alphabet into another (for example, an ASC II code could be used to look up its EBCDIC equivalent 
in a table).
7.3.16.3  Processor Identification Instruction
The CPUID (processor identification) instruction returns in formation about the processor on which the instruction 
is executed. 
7.3.16.4  No-Operation and Undefined Instructions
The NOP (no operation) instruction increments the EIP regist er to point at the next instruction, but affects nothing 
else.7-24 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
The UD (undefined) instruction generates an invalid opcode exception. Intel reserves the opcode for this instruction 
for this function. The instruction is provided to allow software to test an invalid opcode exception handler.
7.3.17 Random Number Generator Instructions
The instructions for generating random numbers to co mply with NIST SP800-90A, SP800-90B, and SP800-90C 
standards are described in this section.
7.3.17.1  RDRAND
The RDRAND instruction returns a random number. All Inte l processors that support the RDRAND instruction indi-
cate the availability of the RDRAND instruction via reporting CPUID.01H: ECX.RDRAND[bit 30] = 1.
RDRAND returns random numbers that are supplied by a cr yptographically secure, deterministic random bit gener-
ator DRBG. The DRBG is designed to meet the NIST SP 800-90A standard. The DRBG is re-seeded frequently from 
an on-chip non-deterministic entropy source to guarantee data returned by RDRAND is statistically uniform, non-
periodic and non-deterministic.
In order for the hardware design to meet its security goal s, the random number generator continuously tests itself 
and the random data it is generating. Runtime failures in the random number generator circuitry or statistically anomalous data occurring by chance will be detected by th e self test hardware and flag the resulting data as being 
bad. In such extremely rare cases, the RDRAND in struction will return no data instead of bad data.
Under heavy load, with multiple cores ex ecuting RDRAND in parallel, it is possible, though unlikely, for the demand 
of random numbers by software processes/threads to exceed the rate at which the random number generator 
hardware can supply them. This will lead to the RDRAND instruction return ing no data transitorily. The RDRAND 
instruction indicates the occurrence of this rare situation by clearing the CF flag.
The RDRAND instruction returns with the carry flag set (CF = 1) to indicate valid data is returned. It is recom-
mended that software using the RDRAND instruction to get random numbers retry for a limited number of itera-
tions while RDRAND returns CF=0 and complete when valid data is returned, indicated with CF=1. This will deal 
with transitory underflows. A retry limit should be employ ed to prevent a hard failure in the RNG (expected to be 
extremely rare) leading to a busy loop in software.
The intrinsic primitive for RDRAND is defined to address software’s need for the common cases (CF = 1) and the 
rare situations (CF = 0). The intrinsic primitive returns a va lue that reflects the value of the carry flag returned by 
the underlying RDRAND instruction. The example below illu strates the recommended usage of an RDRAND intrinsic 
in a utility function, a loop to fetch a 64 bit random value with a retry count limit of 10. A C implementation might be written as follows:
----------------------------------------------------------------------------------------
#define SUCCESS 1
#define RETRY_LIMIT_EXCEEDED 0#define RETRY_LIMIT 10
int get_random_64( unsigned __int 64 * arand)
{int i ; 
for ( i = 0; i < RETRY_LIMIT; i ++) {
if(_rdrand64_step(arand) ) return SUCCESS;
}return RETRY_LIMIT_EXCEEDED;
}
-------------------------------------------------------------------------------
7.3.17.2  RDSEED
The RDSEED instruction returns a random number. All Inte l processors that support the RDSEED instruction indi-
cate the availability of the RDSEED instruction via re porting CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 1.Vol. 1 7-25PROGRAMMING WITH GENERAL -PURPOSE INSTRUCTIONS
RDSEED returns random numbers that are supplied by a cryptographically secure, enhanced non-deterministic 
random bit generator (Enhanced NRBG). The NRBG is desi gned to meet the NIST SP 800-90B and NIST SP800-90C 
standards. 
In order for the hardware design to meet its security go als, the random number generator continuously tests itself 
and the random data it is generating. Runtime failures in the random number generator circuitry or statistically 
anomalous data occurring by chance will be detected by th e self test hardware and flag the resulting data as being 
bad. In such extremely rare case s, the RDSEED instruction will retu rn no data instead of bad data.
Under heavy load, with multiple cores executing RDSEED in parallel, it is possible for the demand of random 
numbers by software processes/threads to exceed the ra te at which the random number generator hardware can 
supply them. This will lead to the RDSEED instruction retu rning no data transitorily. The RDSEED instruction indi-
cates the occurrence of this situation by clearing the CF flag.
The RDSEED instruction returns with the carry flag set (CF = 1) to indicate valid data is returned. It is recom-
mended that software using the RDSEED instruction to get random numbers retry for a limited number of iterations 
while RDSEED returns CF=0 and complete when valid data is returned, indicated with CF=1. This will deal with 
transitory underflows. A retry limit should be employed to prevent a hard failure in the NRBG (expected to be 
The intrinsic primitive for RDSEED is defined to address software’s need for the common cases (CF = 1) and the 
the underlying RDSEED instruction.7-26 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSVol. 1 8-1CHAPTER 8
PROGRAMMING WITH THE X87 FPU
The x87 Floating-Point Unit (FPU) provides high-performan ce floating-point processing capabilities for use in 
graphics processing, scientific, engineering, and business a pplications. It supports the floating-point, integer, and 
packed BCD integer data types and the floating-point pr ocessing algorithms and exception handling architecture 
defined in the IEEE Standard 754 for Floating-Point Arithmetic.
This chapter describes the x87 FPU execution environment and instruction set. It also provides exception handling 
information that is specific to the x87 FPU. Refer to the following chapters or sections of chapters for additional 
information about x87 FPU instructions and floating-point operations:

•The Intel® 64 and IA-32 Architectures Software Developer’ s Manual, Volumes 2A, 2B, 2C, & 2D, provides 
detailed descriptions of x87 FPU instructions.
•Section 4.2.2, “Floating-Point Data Types,” Section 4. 2.1.2, “Signed Integers,” and Section 4.7, “BCD and 
Packed BCD Integers,” describe the floati ng-point, integer, and BCD data types.
•Section 4.9, “Overview of Floating-Point Exceptions,” Se ction 4.9.1, “Floating-Point Exception Conditions,” and 
Section 4.9.2, “Floating-Point Exception Priority,” give an overview of the fl oating-point exceptions that the x87 
FPU can detect and report.
8.1 X87 FPU EXECUTION ENVIRONMENT
The x87 FPU represents a separate execution environment within the IA-32 architecture (see Figure 8-1). This execution environment consists of eight data registers (called the x87 FPU data registers) and the following 
special-purpose registers: 
•Status register.
•Control register.
•Tag word register.
•Last instruction pointer register.
•Last data (operand) pointer register.
•Opcode register.
These registers are described in the following sections.
The x87 FPU executes instructions from the processor’s norm al instruction stream. The state of the x87 FPU is inde-
pendent from the state of the basic execution environm ent and from the state of SSE/SSE2/SSE3 extensions. 
However, the x87 FPU and Intel MMX technology share stat e because the MMX registers are aliased to the x87 FPU 
data registers. Therefore, when writing code that us es x87 FPU and MMX instructions, the programmer must 
explicitly manage the x87 FPU and MMX state (see Sect ion 9.5, “Compatibility with x87 FPU Architecture”).
8.1.1 x87 FPU in 64-Bit Mode and Compatibility Mode
In compatibility mode and 64-bit mode, x87 FPU instructio ns function like they do in protected mode. Memory 
operands are specified using the ModR/M, SIB encoding that  is described in Section 3.7.5, “Specifying an Offset.”
8.1.2 x87 FPU Data Registers
The x87 FPU data registers (shown in Figure 8-1) consist of  eight 80-bit registers. Values are stored in these regis-
ters in the double extended precision floating-point form at shown in Figure 4-3. When floating-point, integer, or 
packed BCD integer values are loaded from memory into any of the x87 FPU data registers, the values are auto-
matically converted into double extended precision floating -point format (if they are not already in that format). 
When computation results are subsequently transferred back  into memory from any of the x87 FPU registers, the 8-2 Vol. 1PROGRAMMING WITH THE X87 FPU
results can be left in the double extended precision floati ng-point format or converted back into a shorter floating-
point format, an integer format, or the packed BCD inte ger format. (See Section 8.2, “x87 FPU Data Types,” for a 
description of the data types operated on by the x87 FPU.)
The x87 FPU instructions treat the eight x87 FPU data regist ers as a register stack (see Figure 8-2). All addressing of 
the data registers is relative to the register on the top of  the stack. The register number of the current top-of-stack 
register is stored in the TOP (stack TOP) field in the x87 FPU status word. Load operations decrement TOP by one 
and load a value into the new top-of-stack register, an d store operations store the value from the current TOP 
register in memory and then increment TOP by one. (For th e x87 FPU, a load operation is equivalent to a push and 
a store operation is equivalent to a pop.) Note that load and store operations are also available that do not push and 
pop the stack.
If a load operation is performed when TOP is at 0, register  wraparound occurs and the new value of TOP is set to 7. 
The floating-point stack-overflow exception indicates when wraparound might cause an unsaved value to be over-
written (see Section 8.5.1.1, “Stack Overflow or Underflow Exception (#IS)”).
Many floating-point instructions have several addressing  modes that permit the programmer to implicitly operate 
on the top of the stack, or to explicitly operate on specif ic registers relative to the TOP. Assemblers support these Figure 8-1.  x87 FPU Execution Environment
Figure 8-2.  x87 FPU Data Register Stack0 79
R7
R6
R5
R4
R3
R2
R1
R0Data Registers
Exponent Significand78 6463
15
Control
Register0
Status
Register
Tag
Register0 47
Last Instruction Pointer (FCS:FIP)
Last Data (Operand) Pointer (FDS:FDP)
10
Opcode0Sign
7
6
5
4
3
2
1
0FPU Data Register Stack
ST(2)
ST(1)
ST(0)Top
011BGrowth
StackVol. 1 8-3PROGRAMMING WITH THE X87 FPU
register addressing modes, using the expression ST(0), or  simply ST, to represent the current stack top and ST(i) 
to specify the ith register from TOP in the stack (0 ≤ i ≤ 7). For example, if TOP contains 011B (register 3 is the top 
of the stack), the following instruction would add the cont ents of two registers in the stack (registers 3 and 5):
FADD ST, ST(2);
Figure 8-3 shows an example of how the stack structure of the x87 FPU registers and instructions are typically used 
to perform a series of computat ions. Here, a two-dimensional dot product is computed, as follows:
1. The first instruction (FLD value1) decrements the stack register pointer (TOP) and loads the value 5.6 from 
memory into ST(0). The result of this  operation is shown in snap-shot (a). 
2. The second instruction multiplies the value in ST(0) by  the value 2.4 from memory and stores the result in 
ST(0), shown in snap-shot (b).
3. The third instruction decrements TOP and loads the value 3.8 in ST(0).
4. The fourth instruction multiplies the value in ST(0) by  the value 10.3 from memory and stores the result in 
ST(0), shown in snap-shot (c).
5. The fifth instruction adds the value and the value in ST (1) and stores the result in ST(0), shown in snap-shot 
(d).
The style of programming demonstrated in this example is supported by the floating-point instruction set. In cases 
where the stack structure causes computation bottlenec ks, the FXCH (exchange x87 FPU register contents) 
instruction can be used to streamline a computation.
8.1.2.1  Parameter Passing With the x87 FPU Register Stack
Like the general-purpose registers, the contents of the x8 7 FPU data registers are unaffected by procedure calls, or 
in other words, the values are maintained across proced ure boundaries. A calling procedure can thus use the x87 
FPU data registers (as well as the procedure stack) fo r passing parameter between procedures. The called proce-
dure can reference parameters passed through the register  stack using the current stack register pointer (TOP) 
and the ST(0) and ST(i) nomenclature. It is also common pr actice for a called procedure to leave a return value or 
result in register ST(0) when returning ex ecution to the calling procedure or program.Figure 8-3.  Example x87 FPU Dot Product Computation(a)
R7
R6
R5
R4
R3
R2
R1
R0Computation
ST(0) 5.6(b)
R7
R6
R5
R4
R3
R2
R1
R0ST(0) 13.44(c)
R7
R6
R5
R4
R3
R2
R1
R0ST(1)
ST(0)13.44(d)
R7
R6
R5
R4
R3
R2
R1
R0ST(1)
ST(0) 39.1413.44
52.58Dot Product = (5.6 x 2.4) + (3.8 x 10.3)
Code:
FLD  value1 ;(a) value1 = 5.6
FMUL value2 ;(b) value2 = 2.4FLD  value3 ; value3 = 3.8
FMUL value4 ;(c)value4 = 10.3
FADD ST(1)  ;(d)8-4 Vol. 1PROGRAMMING WITH THE X87 FPU
When mixing MMX and x87 FPU instructions in the procedur es or code sequences, the programmer is responsible 
for maintaining the integrity of parameters being passed in  the x87 FPU data registers.  If an MMX instruction is 
executed before the parameters in the x87 FPU data regi sters have been passed to another procedure, the param-
eters may be lost (see Section 9.5, “Compatibility with x87 FPU Architecture”).
8.1.3 x87 FPU Status Register
The 16-bit x87 FPU status register (see Figure 8-4) indica tes the current state of the x87 FPU. The flags in the x87 
FPU status register include the FPU busy flag, top-of-stack (TOP) pointer, condition code flags, exception summary status flag, stack fault flag, and exception flags. The x87 FP U sets the flags in this register to show the results of 
operations. 
 
The contents of the x87 FPU status register (referred to as  the x87 FPU status word) can be stored in memory using 
the FSTSW/FNSTSW, FSTENV/FNSTENV, FSAVE/FNSAVE, and FXSA VE instructions. It can also be stored in the AX 
register of the integer unit, using the FSTSW/FNSTSW instructions.
8.1.3.1  Top of Stack (TOP) Pointer
A pointer to the x87 FPU data register that is currently at the top of the x87 FPU register stack is contained in bits 
11 through 13 of the x87 FPU status word. This pointer, which is commonly referred to as TOP (for top-of-stack), 
is a binary value from 0 to 7. See Section 8.1.2, “x87 FPU Data Registers,” for more information about the TOP 
pointer.
8.1.3.2  Condition Code Flags
The four condition code flags (C0 through C3) indicate the results of floating-point comparison and arithmetic oper-
ations. Table 8-1 summarizes the manner in which the floa ting-point instructions set the condition code flags.

pointer.
ations. Table 8-1 summarizes the manner in which the floa ting-point instructions set the condition code flags. 
These condition code bits are used principally for condit ional branching and for storage of information used in 
exception handling (see Section 8.1.4, “Branchi ng and Conditional Moves on Condition Codes”).
As shown in Table 8-1, the C1 condition code flag is used for a variety of functions. When both the IE and SF flags 
in the x87 FPU status word are set, indicating a stack ov erflow or underflow exception (#IS), the C1 flag distin-
guishes between overflow (C1 = 1) and un derflow (C1 = 0). When the PE flag in the status word is set, indicating 
an inexact (rounded) result, the C1 flag  is set to 1 if the last rounding by the instruction was upward. The FXAM 
instruction sets C1 to the sign of the value being examined.Figure 8-4.  x87 FPU Status WordFPU Busy
15 1314 1110 9 876543 210
BI
EP
EO
EU
EZ
ED
ETOPTop of Stack Pointer
Exception Flags
   Precision   Underflow   Overflow   Zero Divide   Denormalized Operand   Invalid OperationStack FaultException Summary StatusCondition
   CodeC
2C
1C
0E
SS
FC
3Vol. 1 8-5PROGRAMMING WITH THE X87 FPU
The C2 condition code flag is used by  the FPREM and FPREM1 instructions to indicate an incomplete reduction (or 
partial remainder). When a successful reduction has been completed, the C0, C3, and C1 condition code flags are 
set to the three least-significant bits of the quotient  (Q2, Q1, and Q0, respectively). See “FPREM1—Partial 
Remainder” in Chapter 3, “Instruction  Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2A, for mo re information on how these instructions use the condition code flags.
The FPTAN, FSIN, FCOS, and FSINCOS instructions set the C2  flag to 1 to indicate that the source operand is 
beyond the allowable range of ±263 and clear the C2 flag if the source operand is within the allowable range.
Where the state of the condition code flags are listed as unde fined in Table 8-1, do not rely on any specific value in 
these flags.
8.1.3.3  x87 FPU Floating-Point Exception Flags
The six x87 FPU floating-point exception flags (bits 0 throug h 5) of the x87 FPU status word indicate that one or 
more floating-point exceptions have been detected since th e bits were last cleared. The individual exception flags 
(IE, DE, ZE, OE, UE, and PE) are described in detail in Se ction 8.4, “x87 FPU Floating-Point Exception Handling.” 
Each of the exception flags can be masked by an exception mask bit in the x87 FPU control word (see Section 8.1.5, 
“x87 FPU Control Word”). The exception summary status flag (ES, bit 7) is set when any of the unmasked exception 
flags are set. When the ES flag is set, the x87 FPU exception handler is invoked, using one of the techniques 
described in Section 8.7, “Handling x87 FPU Exceptions in So ftware.” (Note that if an exception flag is masked, the 
x87 FPU will still set the appropriate flag if the associated exception occurs, but it will not set the ES flag.) 
The exception flags are “sticky” bits (once set, they rema in set until explicitly cleared). They can be cleared by 
executing the FCLEX/FNCLEX (clear exceptions) instructions, by reinitializing the x87 FPU with the FINIT/FNINIT or 
FSAVE/FNSAVE instructions, or by overwriting the flags with an FRSTOR or FLDENV instruction.
The B-bit (bit 15) is included for 8087 compatibility only. It reflects the contents of the ES flag.
Table 8-1.  Condition Code Interpretation
Instruction C0 C3 C2 C1
FCOM, FCOMP, FCOMPP, FICOM, FICOMP, FTST, 
FUCOM, FUCOMP, FUCOMPP Result of Comparison Operands 
are not 
Comparable0 or #IS
FCOMI, FCOMIP, FUCOMI, FUCOMIP Undefined. (These instructions set the 
status flags in the EFLAGS register.)#IS
FXAM  Operand class Sign
FPREM, FPREM1 Q2 Q1 0 = reduction 
complete
1 = reduction 
incompleteQ0 or #IS
F2XM1, FADD, FADDP, FBSTP, FCMOVcc, 
FIADD, FDIV, FDIVP, FD IVR, FDIVRP, FIDIV, 
FIDIVR, FIMUL, FIST, FISTP, FISUB, FISUBR, 
FMUL, FMULP, FPATAN, FRNDINT, FSCALE, FST, FSTP, FSUB, FSUBP, FSUBR, FSUBRP, FSQRT, 
FYL2X, FYL2XP1Undefined Roundup or #IS
FCOS, FSIN, FSINCOS, FP TAN Undefined 0 = source 
operand within 
range1 = source 
operand out of 
rangeRoundup or #IS 
(Undefined if C2 = 
1)
FABS, FBLD, FCHS, FDECSTP, FILD, FINCSTP, 
FLD, Load Constants, FS TP (ext. prec.), FXCH, 
FXTRACT Undefined 0 or #IS8-6 Vol. 1PROGRAMMING WITH THE X87 FPU
8.1.3.4  Stack Fault Flag
The stack fault flag (bit 6 of the x87 FPU status word) indicates that stack overflow or stack underflow has occurred 
with data in the x87 FPU data register stack. The x87 FPU ex plicitly sets the SF flag when it detects a stack overflow 
or underflow condition, but it does not explicitly clear th e flag when it detects an invalid-arithmetic-operand condi-
tion. 
When this flag is set, the condition code flag C1 indica tes the nature of the fault: overflow (C1 = 1) and under-
flow (C1 = 0). The SF flag is a “sticky” flag, meaning that after it is set, the processor does not clear it until it is 
explicitly instructed to do so (for example, by an FINIT/FNINIT, FCLEX/FNCLEX, or FSAVE/FNSAVE instruction). 
See Section 8.1.7, “x87 FPU Tag Word,” for more information on x87 FPU stack faults.
8.1.4 Branching and Conditional Moves on Condition Codes
The x87 FPU (beginning with the P6 family processors ) supports two mechanisms fo r branching and performing 
conditional moves according to comparisons of two floating -point values. These mechanis m are referred to here as 
the “old mechanism” and the “new mechanism.” 
The old mechanism is available in the x87 FPU prior to the P6 family processors and in P6 family processors. This 
mechanism uses the floating-point compare instructions  (FCOM, FCOMP, FCOMPP, FTST, FUCOMPP, FICOM, and 
FICOMP) to compare two floating-point values and set th e condition code flags (C0 through C3) according to the 
results. The contents of the condition code flags are then copied into the status flags of the EFLAGS register using 
a two step process (see Figure 8-5):
1. The FSTSW AX instruction moves the x87 FPU status word into the AX register.
2. The SAHF instruction copies the upper 8 bits of the AX register, which includes the condition code flags, into the 
lower 8 bits of the EFLAGS register.
When the condition code flags have been loaded into th e EFLAGS register, conditional jumps or conditional moves 
can be performed based on the new settings of  the status flags in the EFLAGS register.FLDENV, FRSTOR Each bit loaded from memory
FFREE, FLDCW, FCLEX/FNCLEX, FNOP, 
FSTCW/FNSTCW, FSTENV/FNSTENV, 
FSTSW/FNSTSW, Undefined
FINIT/FNINIT, FSAVE/FNSAVE 0 0 0 0
Figure 8-5.  Moving the Condit ion Codes to the EFLAGS RegisterTable 8-1.  Condition Code Interpretation (Contd.)
0Condition
CodeStatus
Flag
C0
C1
C2C3CF
(none)
PF
ZF
C
F1P
FZ
F7 31 EFLAGS Register0
C
2C
1C
3AX Register
0C150
C
2C
1C
3x87 FPU Status Word
0C15
FSTSW AX Instruction
SAHF InstructionVol. 1 8-7PROGRAMMING WITH THE X87 FPU
The new mechanism is available beginning with the P6 fami ly processors. Using this mechanism, the new floating-
point compare and set EFLAGS instructions (FCOMI, FCOM IP, FUCOMI, and FUCOMIP) compare two floating-point 
values and set the ZF, PF, and CF flags in the EFLAGS register directly. A single instruction thus replaces the three 
instructions required by the old mechanism.
Note also that the FCMOV cc instructions (also new in the P6 family processors) allow conditional moves of floating-
point values (values in the x87 FPU data registers) based on  the setting of the status flags (ZF, PF, and CF) in the 
EFLAGS register. These instructions eliminate the need for an IF statement to perform conditional moves of 
8.1.5 x87 FPU Control Word
The 16-bit x87 FPU control word (see Figure 8-6) controls the precision of the x87 FPU and rounding method used. 
It also contains the x87 FPU floating-point exception mask  bits. The control word is cached in the x87 FPU control 
register. The contents of this register can be loaded wi th the FLDCW instruction and stored in memory with the 
FSTCW/FNSTCW instructions.
When the x87 FPU is initialized with either an FINIT/ FNINIT or FSAVE/FNSAVE instruction, the x87 FPU control 
word is set to 037FH, which masks all floating-point ex ceptions, sets rounding to nearest, and sets the x87 FPU 
precision to 64 bits.
8.1.5.1  x87 FPU Floating-Point Exception Mask Bits
The exception-flag mask bits (bits 0 through 5 of the x 87 FPU control word) mask the 6 floating-point exception 
flags in the x87 FPU status word. When one of these mask  bits is set, its corresponding x87 FPU floating-point 
exception is blocked from being generated.
8.1.5.2  Precision Control Field
The precision-control (PC) field (bits 8 and 9 of the x87 FP U control word) determines the precision (64, 53, or 24 
bits) of floating-point calculations made by the x87 FPU (see Table 8-2). The default precision is double extended 
precision, which uses the full 64-bit significand available with the double extended precision floating-point format

precision, which uses the full 64-bit significand available with the double extended precision floating-point format 
of the x87 FPU data registers. This setting is best suited fo r most applications, because it allows applications to take 
full advantage of the maximum precision available with the x87 FPU data registers.Figure 8-6.  x87 FPU Control Word15 1314 12 1110 9 876543 210
XI
MP
MO
MU
MZ
MD
MRC PCInfinity Control
Rounding Control
Precision Control
Exception Masks   Precision   Underflow
   Overflow
   Zero Divide   Denormal Operand   Invalid Operation
Reserved8-8 Vol. 1PROGRAMMING WITH THE X87 FPU
The double precision and single precision settings reduce th e size of the significand to 53 bits and 24 bits, respec-
tively. These settings are provided to support IEEE Standa rd 754 and to provide compatibility with the specifica-
tions of certain existing programming languages. Using these settings nullifies the advantages of the double 
extended precision floating-point form at's 64-bit significand length. When reduced precision is specified, the 
rounding of the significand value clears the unused bits on the right to zeros. 
The precision-control bits only affect the results of the following floating-point instructions: FADD, FADDP, FIADD, 
FSUB, FSUBP, FISUB, FSUBR, FSUBRP, FISUBR, FMUL, FMULP, FIMU L, FDIV, FDIVP, FIDIV, FDIVR, FDIVRP, FIDIVR, 
and FSQRT.
8.1.5.3  Rounding Control Field
The rounding-control (RC) field of the x87 FPU control regist er (bits 10 and 11) controls how the results of x87 FPU 
floating-point instructions are rounded. See Section 4.8. 4, “Rounding,” for a discussion of rounding of floating-
point values; See Section 4.8.4.1, “Rounding Control (RC) Fields,” for the encodings of the RC field.
8.1.6 Infinity Control Flag
The infinity control flag (bit 12 of the x87 FPU control wo rd) is provided for compatibility with the Intel 287 Math 
Coprocessor; it is not meaningful for later version x87 FP U coprocessors or IA-32 processors. See Section 4.8.3.3, 
“Signed Infinities,” for information on how the x87 FPUs handle infinity values.
8.1.7 x87 FPU Tag Word
The 16-bit tag word (see Figure 8-7) indicates the contents  of each the 8 registers in the x87 FPU data-register 
stack (one 2-bit tag per register). The tag codes indicate whether a register contains a valid number, zero, or a 
special floating-point number (NaN, infinity, denormal, or unsupported format), or whether it is empty. The x87 
FPU tag word is cached in the x87 FPU in the x87 FPU tag wo rd register. When the x87 FPU is initialized with either 
an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87 FP U tag word is set to FFFFH, which marks all the x87 FPU 
data registers as empty.
.
Each tag in the x87 FPU tag word corresponds to a physic al register (numbers 0 through 7). The current top-of-
stack (TOP) pointer stored in the x87 FPU status word can be used to associate tags with registers relative to ST(0).Table 8-2.  Precision Control Field (PC)
Precision PC Field
Single Precision (24 bits) 00BReserved 01BDouble Precision (53 bits) 10BDouble Extended Precision (64 bits) 11B
Figure 8-7.  x87 FPU Tag Word0 15
TAG ValuesTAG(7) TAG(5) TAG(6) TAG(4) TAG(3) TAG(2) TAG(1) TAG(0)
00 — Valid
01 — Zero10 — Special: invalid (NaN, unsup ported), infinity, or denormal
11 — EmptyVol. 1 8-9PROGRAMMING WITH THE X87 FPU
The x87 FPU uses the tag values to detect stack overflow  and underflow conditions (s ee Section 8.5.1.1, “Stack 
Overflow or Underflow Exception (#IS)”).
Application programs and exception handlers can use this tag information to check the contents of an x87 FPU data 
register without performing complex decoding of the actual da ta in the register. To read the tag register, it must be 
stored in memory using either the FS TENV/FNSTENV or FSAVE/FNSAVE instructions. The location of the tag word 
in memory after being saved with one of these in structions is shown in Figures 8-9 through 8-12.
Software cannot directly load or modify the tags in the tag register. The FLDENV and FRSTOR instructions load an 
image of the tag register into the x87 FPU; however, the x87 FPU uses those tag values only to determine if the 
data registers are empty (11B) or non-empty (00B, 01B, or 10B). 
If the tag register image indicates that a data register is em pty, the tag in the tag register for that data register is 
marked empty (11B); if the tag register image indicates that  the data register is non-empty, the x87 FPU reads the 
actual value in the data register and sets the tag for the register accordingly. This action prevents a program from 
setting the values in the tag register to incorrectly re present the actual contents of non-empty data registers.
8.1.8 x87 FPU Instruction an d Data (Operand) Pointers
The x87 FPU stores pointers to the instruction and data (operand) for the last non-control instruction executed. 
These are the x87 FPU instruction pointer and x87 FPU data  (operand) pointers; software can save these pointers 
to provide state information for exception handlers. The poin ters are illustrated in Figure 8-1 (the figure illustrates 
the pointers as used outside 64-bit mode; see below).
Note that the value in the x87 FPU data pointer is always a pointer to a memory operand. If the last non-control 
instruction that was executed did not have a memory operand, the value in the data pointer is undefined 
(reserved). If CPUID.(EAX=07H, ECX=0H ):EBX[bit 6] = 1, the data pointer is updated only for x87 non-control 
instructions that incur unmasked x87 exceptions.
The contents of the x87 FPU instruction and data pointers remain unchanged when any of the following instructions 
are executed: FCLEX/FNCLEX, FLDCW, FSTCW/FNSTC W, FSTSW/FNSTSW, FSTENV /FNSTENV, FLDENV, and 
WAIT/FWAIT.
For all the x87 FPUs and Numeric Processor Extensions (N PXs) except the 8087, the x87 FPU instruction pointer 
points to any prefixes that preceded the instruction. Fo r the 8087, the x87 FPU instruction pointer points only to 
the actual opcode.
The x87 FPU instruction and data pointers each consists of an offset and a segment selector:
•The x87 FPU Instruction Pointer Offset (FIP) comprises 64 bits on processors that support IA-32e mode; on 
other processors, it offset comprises 32 bits.
•The x87 FPU Instruction Pointer Selector (FCS) comprises 16 bits.
•The x87 FPU Data Pointer Offset (FDP) comprises 64 bits  on processors that support IA-32e mode; on other 
processors, it offset comprises 32 bits.
•The x87 FPU Data Pointer Selector (FDS) comprises 16 bits.
The pointers are accessed by the FINIT/FNINIT, FLDE NV, FRSTOR, FSAVE/FNSAVE, FSTENV/FNSTENV, FXRSTOR, 
FXSAVE, XRSTOR, XSAVE, and XSAVEOPT instructions as follows:
•FINIT/FNINIT. Each instruction clears FIP, FCS, FDP, and FDS.
•FLDENV, FRSTOR. These instructions use the memory formats given in Figures 8-9 through 8-12:
— For each of FIP and FDP, each instruction loads the lo wer 32 bits from memory and clears the upper 32 bits.
— If CR0.PE = 1, each instruction loads FCS and FDS from memory; otherwise, it clears them.
•FSAVE/FNSAVE, FSTENV/FNSTENV. These instructions use the memory formats given in Figures 8-9 through 
8-12.
— Each instruction saves the lower 32 bits of each FIP and FDP into memory. the up per 32 bits are not saved.
— If CR0.PE = 1, each instruction saves FCS and FDS into memory. If 
CPUID.(EAX=07H, ECX=0H):EBX[bit 13] = 1, the processor deprecates FCS and FDS; it saves each as 
0000H.8-10 Vol. 1PROGRAMMING WITH THE X87 FPU
— After saving these data into memory, FSAVE/FNSAVE clears FIP, FCS, FDP, and FDS.
•FXRSTOR, XRSTOR. These instructions load data from  a memory image whose format depend on operating 
mode and the REX prefix. The memory formats are gi ven in Tables 3-43, 3-46, and 3-47 in Chapter 3, 
“Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A.
— Outside of 64-bit mode or if REX.W = 0, the instructions operate as follows:
•For each of FIP and FDP, each instruction loads the lower 32 bits from memory and clears the upper 32 
bits.
•Each instruction loads FCS and FDS from memory.
— In 64-bit mode with REX.W = 1, the instructions operate as follows:
•Each instruction loads FIP and FDP from memory.
•Each instruction clears FCS and FDS.
•FXSAVE, XSAVE, and XSAVEOPT. These instructions store data into a memory image whose format depend on 
operating mode and the REX prefix. The memory formats are given in Tabl es 3-43, 3-46, and 3-47 in Chapter 
3, “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A.
•Each instruction saves the lower 32 bits of each of FIP and FDP into memory. The upper 32 bits are not 
saved.
•Each instruction saves FCS and FDS into memory. If CPUID.(EAX=07H, ECX=0H):EBX[bit 13] = 1, the 
processor deprecates FCS and FDS; it saves each as 0000H.
— In 64-bit mode with REX.W = 1, each instruction saves FIP and FDP into memory. FCS and FDS are not 
saved.
8.1.9 Last Instruction Opcode

Volume 2A.
saved.
saved.
The x87 FPU stores in the 11-bit x87 FPU opcode register (FOP) the opcode of the last x87 non-control instruction 
executed that incurred an unmasked x87 exception. (Thi s information provides state information for exception 
handlers.) Only the first and second opcode bytes (after all prefixes) are stored in the x87 FPU opcode register. 
Figure 8-8 shows the encoding of these tw o bytes. Since the upper 5 bits of th e first opcode byte are the same for 
all floating-point opcodes (11011B), only the lower 3 bi ts of this byte are stored in the opcode register.
8.1.9.1  Fopcode Compatibility Sub-mode
Some Pentium 4 and Intel Xeon processors provide program control over the value stored into FOP. Here, bit 2 of 
the IA32_MISC_ENABLE MSR enables (set) or disables (clear) the fopcode compatibility mode. 
If fopcode compatibility mode is enabled, FOP is defined as  it had been in previous IA-32 implementations, as the 
opcode of the last x87 non-control instruction executed (even if that instruction did not incur an unmasked x87 
exception).Vol. 1 8-11PROGRAMMING WITH THE X87 FPU
The fopcode compatibility mode should be enabled only  when x87 FPU floating-point exception handlers are 
designed to use the fopcode to analyze program performa nce or restart a program after an exception has been 
handled.
More recent Intel 64 processors do not support fopcode compatibility mode and do not allow software to set bit 2 
of the IA32_MISC_ENABLE MSR.
8.1.10 Saving the x87 FPU State wi th FSTENV/FNSTENV and FSAVE/FNSAVE
The FSTENV/FNSTENV and FSAVE/FNSAVE instructions stor e x87 FPU state information in memory for use by 
exception handlers and other system and application software. The FSTENV/FNSTE NV instruction saves the 
contents of the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer, and opcode registers. The 
FSAVE/FNSAVE instruction stores that information plus the contents of the x87 FPU data registers. Note that the 
FSAVE/FNSAVE instruction also initializes the x87 FPU to de fault values (just as the FINIT/FNINIT instruction does) 
after it has saved the original state of the x87 FPU.
The manner in which this information is stored in me mory depends on the operating mode of the processor 
(protected mode or real-address mode) and on the operand- size attribute in effect (32-bit or 16-bit). See Figures 
8-9 through 8-12. In virtual-8086 mode or SMM, the real -address mode formats shown in Figure 8-12 is used. See 
Chapter 32, “System Management Mode,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 3C, for information on using the x87 FPU while in SMM.
The FLDENV and FRSTOR instructions allow x87 FPU state in formation to be loaded from memory into the x87 FPU. 
Here, the FLDENV instruction loads only the status, control,  tag, x87 FPU instruction pointer, x87 FPU data pointer, 
and opcode registers, and the FRSTOR instruction loads all the x87 FPU registers, including the x87 FPU stack 
registers. Figure 8-8.  Contents of  x87 FPU Opcode Registers
Figure 8-9.  Protected Mode x87 FP U State Image in Memory, 32-Bit Format0
x87 FPU Opcode Register1002nd Instruction Byte
701st Instruction Byte
7 2
78
0 31
0
4
8
12
16
20
2432-Bit Protected Mode Format
Control Word
Bits 10:0 of opcodeStatus Word
Tag Word
FPU Instruction Pointer Selector
FPU Data Pointer Selector (FDS)FPU Data Pointer Offset (FDP)0 0 0 0 0FPU Instruction Pointer Offset (FIP)16 15
For instructions that also store x87 FPU data  registers, the eight 
80-bit registers (R0-R7) follow th e above structure in sequence.8-12 Vol. 1PROGRAMMING WITH THE X87 FPU
8.1.11 Saving the x87 FPU State with FXSAVE
The FXSAVE and FXRSTOR instructions save and restore, re spectively, the x87 FPU state along with the state of the 
XMM registers and the MXCSR register. Using the FXSAVE in struction to save the x87 FPU state has two benefits: 
(1) FXSAVE executes faster than FSAVE, and (2) FXSAVE  saves the entire x87 FPU, MMX, and XMM state in one 
operation. See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for additional information about these instruc-
tions.Figure 8-10.  Real Mode x87 FPU State Image in Memory, 32-Bit Format
Figure 8-11.  Protected Mode x87 FP U State Image in Memory, 16-Bit Format
Figure 8-12.  Real Mode x87 FPU State Image in Memory, 16-Bit Format0 31
0
4
8
12
16
20
2432-Bit Real-Address Mode Format
FDP[31:16]FIP[31:16]Status Word
Tag Word
FOP[10:0]
0 0 0 0 0 0 0 0 0 0 0 0FDP[15:0]0 0 0 0FIP[15:0]
0 0 0 016 15
For instructions that also store x87 FPU data registers, the eight 
80-bit registers (R0-R7) follow th e above structure in sequence.
0
0
2
4
6
8
10
1216-Bit Protected Mode Format
Control Word15
Status Word
Tag Word
FCS
FDSFDPFIP
0
0
2
4
6
8
10
1216-Bit Real-Address Mode and
Tag WordVirtual-8086 Mode Format
0 0 0 0 0 0 0 0 0 0 0 0Bits 10:0 of opcode0FIP[15:0]
FIP[19:16]
FDP[19:16]FDP[15:0]Vol. 1 8-13PROGRAMMING WITH THE X87 FPU
8.2 X87 FPU DATA TYPES
The x87 FPU recognizes and operates on the following seven data types (see Figures 8-13): single precision 
floating-point, double precision floating-point, double ex tended precision floating-point, signed word integer, 
signed doubleword integer, signed quadword  integer, and packed BCD decimal integers. 
For detailed information about these data types, see Sectio n 4.2.2, “Floating-Point Data Types,” Section 4.2.1.2, 
“Signed Integers,” and Section 4.7, “BCD and Packed BCD Integers.”
With the exception of the 80-bit double extended precisio n floating-point format, all of these data types exist in 
memory only. When they are loaded into x87 FPU data registers, they are converted into double extended precision floating-point format and operated on in that format.
Denormal values are also supported in each of the floating -point types, as required by IEEE Standard 754. When a 
denormal number in single precision or double precision fl oating-point format is used as a source operand and the 
denormal exception is masked, the x87 FPU automatically normalizes  the number when it is converted to double 
extended precision format.
When stored in memory, the least significant byte of an x87 FPU data-type value is stored at the initial address 
specified for the value. Successive bytes from the value are then stored in successively higher addresses in 
memory. The floating-point instructions load and store memory operands using only the initial address of the 
operand. 
As a general rule, values should be stored in memory in double precision format. This format provides sufficient 
range and precision to return correct results with a mini mum of programmer attention. The single precision format 
is useful for debugging algorithms, because rounding prob lems will manifest themselves more quickly in this 
format. The double extended precision format is normally reserved for holding intermediate results in the x87 FPU 
registers and constants. Its extra length is designed to shield final results from the effects of rounding and over-
flow/underflow in intermediate calculations. However, wh en an application requires the maximum range and preci-
sion of the x87 FPU (for data storage, computations, an d results), values can be stored in memory in double 
extended precision format.Figure 8-13.  x87 FPU Data Type Formats0Packed BCD Integers
79D00Quadword Integer
63
4 Bits = 1 BCD Digit0Doubleword Integer
310Word Integer
15
Sign
78 72 71X6214
300Double Extended Precision Floating-Point
79Sign
78 64630Double Precision Floating-Point
63620Single Precision Floating-Point
3130 23 22Fraction Exp. Sign
Implied Integer
Implied IntegerSign Exponent Fraction
52 51
Fraction Exponent
62Integer
Sign
Sign
Sign8-14 Vol. 1PROGRAMMING WITH THE X87 FPU
8.2.1 Indefinites
For each x87 FPU data type, one unique encoding is reserved for representing the special value indefinite . The x87 
FPU produces indefinite values as responses to some masked floating-point invalid-operation exceptions. See 
Tables 4-1, 4-3, and 4-4 for the encoding of the integer indefinite, QNaN floating-point indefinite, and packed BCD 
integer indefinite, respectively. 
The binary integer encoding 100..00B represents either of two things, depending on the circumstances of its use:
•The largest negative number supported by the format (–215, –231, or –263).
•The integer indefinite  value.
If this encoding is used as a source operand (as in an integer load or integer arithmetic instruction), the x87 FPU 
interprets it as the largest negative number representabl e in the format being used. If the x87 FPU detects an 
invalid operation when storing an integer value in memory with an FIST/FISTP instruction and the invalid-operation 
exception is masked, the x87 FPU stores the integer indefi nite encoding in the destination operand as a masked 
response to the exception. In situations where the origin  of a value with this encoding may be ambiguous, the

response to the exception. In situations where the origin  of a value with this encoding may be ambiguous, the 
invalid-operation exception flag can be examined to see if the value was produced as a response to an exception.
8.2.2 Unsupported Double Ex tended Precision Floating-P oint Encodings and Pseudo-
Denormals
The double extended precision floating-point format permit s many encodings that do not fall into any of the cate-
gories shown in Table 4-3. Table 8-3 shows these unsuppor ted encodings. Some of these encodings were supported 
by the Intel 287 math coprocessor; however, most of th em are not supported by the Intel 387 math coprocessor 
and later IA-32 processors. These encodings are no longer supported due to changes made in the final version of 
IEEE Standard 754 that eliminated these encodings.
Specifically, the categories of encodings formerly kn own as pseudo-NaNs, pseudo-infinities, and un-normal 
numbers are not supported and should not be used as op erand values. The Intel 387 math coprocessor and later 
IA-32 processors generate an invalid-operation except ion when these encodings are encountered as operands.
Beginning with the Intel 387 math coprocessor, the en codings formerly known as pseudo-denormal numbers are 
not generated by IA-32 processors. When encountered as operands, however, they are handled correctly, consid-
ering the biased exponent as 1 (and the unbiased exponent  as -16382); that is, they are treated as denormals and 
a denormal exception is generated. Pseudo-denormal numb ers should not be used as operand values. They are 
supported by current IA-32 processors (as described here) to support legacy code.
Table 8-3.  Unsupported Double Extended Precision Floating-Point  Encodings and Pseudo-Denormals
Integer Fraction
Positive 
Pseudo-NaNsQuiet0
.
011..11
.
11..1101 1 . . 1 1
.
10..00
Signaling0
.
011..11
.
11..110  01..11
.
00..01
Positive Floating-Point Pseudo-infinity 0 11..11 0 00..00
Unnormals0
.
011..10
.
00..0101 1 . . 1 1
.
00..00
Pseudo-denormals 0
.
000..00
.
00..0011 1 . . 1 1
.
00..00Vol. 1 8-15PROGRAMMING WITH THE X87 FPU
8.3 X87 FPU INSTRUCTION SET
The floating-point instructions that the x87 FPU supports can be grouped into six functional categories:
•Data transfer instructions.
•Basic arithmetic instructions.
•Comparison instructions.
•Transcendental instructions.
•Load constant instructions.
•x87 FPU control instructions.
See Section 5.2, “x87 FPU Instructions,” for a list  of the floating-point instructions by category.
The following section briefly describes the instructions in each category. Detailed descriptions of the floating-point 
instructions are given in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, 
&2 D .  
8.3.1 Escape (ESC) Instructions
All of the instructions in the x87 FPU instruction set fall in to a class of instructions known as escape (ESC) instruc-
tions. All of these instructions have a common opcode fo rmat, where the first byte of  the opcode is one of the 
numbers from D8H through DFH.
8.3.2 x87 FPU Instruction Operands
Most floating-point instructions require one or two oper ands, located on the x87 FPU data-register stack or in 
memory. (None of the floating-point inst ructions accept immediate operands.) 
When an operand is located in a data register, it is referenc ed relative to the ST(0) register (the register at the top 
of the register stack), rather than by a physical regist er number. Often the ST(0) register is an implied operand.
Operands in memory can be referenced using the same operand addressing methods described in Section 3.7, 
“Operand Addressing.”
8.3.3 Data Transfer Instructions
The data transfer instructions (see Tabl e 8-4) perform the following operations:Negative Floating-Point Pseudo-denormals 1
.
100..00
.
00..001 11..11
.
00..00
Unnormals1
.
111..10
.
00..010 11..01
.
00..00
Pseudo-infinity 1 11..11 0 00..00
Negative Pseudo-NaNs
Signaling1
.
111..11
.
11..110 01..11
.
00..01
Quiet1
.
111..11
.
11..110 11..11
.
10..00
← 15 bits →←  63 bits →Table 8-3.  Unsupported Double Exte nded Precision Floating-Point Enco dings and Pseudo-D enormals (Contd.)8-16 Vol. 1PROGRAMMING WITH THE X87 FPU
•Load a floating-point, integer, or packed BCD operand from memory into the ST(0) register.
•Store the value in an ST(0) register to memory in floating-point, integer, or packed BCD format.
•Move values between registers in the x87 FPU register stack.
The FLD (load floating-point) instruction pushes a floating -point operand from memory onto the top of the x87 FPU 
data-register stack. If the operand is in single precision or  double precision floating-point format, it is automatically 
converted to double extended precision floating-point format . This instruction can also be used to push the value in 
a selected x87 FPU data register onto the top of the register stack.
The FILD (load integer) instruction converts an integer op erand in memory into double extended precision floating-
point format and pushes the value onto the top of the regi ster stack. The FBLD (load packed decimal) instruction 
performs the same load operation for a packed BCD operand in memory.
The FST (store floating-point) and FIST (store integer) inst ructions store the value in register ST(0) in memory in 
the destination format (floating-point or integer, respecti vely). Again, the format conversion is carried out auto-
matically.
The FSTP (store floating-point and pop), FISTP (store in teger and pop), and FBSTP (store packed decimal and pop) 
instructions store the value in the ST(0) registers into memo ry in the destination format (floating-point, integer, or 
packed BCD), then performs a pop operation on the register stack. A pop operation causes the ST(0) register to be 
marked empty and the stack pointer (TOP) in the x87 FPU co ntrol work to be incremented by 1. The FSTP instruc-
tion can also be used to copy the value in the ST(0) register to another x87 FPU register [ST(i)].
The FXCH (exchange register contents) instruction exchange s the value in a selected register in the stack [ST(i)] 
with the value in ST(0).
The FCMOV cc (conditional move) instructions move the value in a selected register in the stack [ST(i)] to register 
ST(0) if a condition specified with a condition code ( cc) is satisfied (see Table 8-5). The condition being tested for 
is represented by the status flags in the EFLAGS regi ster. The condition code mnemonics are appended to the 
letters “FCMOV” to form the mnemonic for a FCMOV cc instruction.Table 8-4.  Data Transfer Instructions
Floating-Point Integer Packed Decimal
FLD Load Floating-Point FILD Load Integer FBLD Load Packed
Decimal
FST Store Floating-Point FIST Store IntegerFSTP Store Floating-Point and 
PopFISTP Store Integer
and PopFBSTP Store Packed
Decimal and Pop
FXCH Exchange Register 
Contents
FCMOV cc Conditional Move
Table 8-5.  Floating-Point Conditional Move Instructions
FCMOVB CF =1B e l o w
FCMOVNB CF =0N o t  b e l o w
FCMOVE ZF =1E q u a l
FCMOVNE ZF =0N o t  e q u a lVol. 1 8-17PROGRAMMING WITH THE X87 FPU
Like the CMOV cc instructions, the FCMOV cc instructions are useful for optimizing small IF constructions. They also 
help eliminate branching overhead for IF operations and th e possibility of branch mispredictions by the processor. 
Software can check if the FCMOV cc instructions are supported by checking the processor’s feature information with 
the CPUID instruction.
8.3.4 Load Constant Instructions
The following instructions push commonly used constants onto the top [ST(0)] of the x87 FPU register stack:
FLDZ Load +0.0.
FLDPI Load π.
FLDL2T Load log2 10.
FLDL2E Load log2e.
The constant values have full double extended precision floating-point precision (64 bits) and are accurate to 
approximately 19 decimal digits. They are stored internally in a format more precise than double extended preci-
sion floating-point. When loading the constant, the x87 FP U rounds the more precise internal constant according 
to the RC (rounding control) field of the x87 FPU control word. The inexact-result exception (#P) is not generated 
as a result of this rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up. See 
Section 8.3.8, “Approximation of Pi,” for information on the π constant.
8.3.5 Basic Arithmetic Instructions
The following floating-point instructions perform basic arithmetic operations on floating-point numbers. Where 
applicable, these instructions match IEEE Standard 754:
FADD/FADDP Add floating-point.
FIADD Add integer to floating-point.
FSUB/FSUBP Subtract floating-point.FISUB Subtract integer from floating-point.
FSUBR/FSUBRP Reverse subtract floating-point.
FISUBR Reverse subtract floating-point from integer.FMUL/FMULP Multiply floating-point.
FIMUL Multiply integer by floating-point.
FDIV/FDIVP Divide floating-point.FIDIV Divide floating-point by integer.
FDIVR/FDIVRP Reverse divide.

FIDIVR Reverse divide integer by floating-point.FABS Absolute value.
FCHS Change sign.Instruction Mnemonic Status Flag States Condition Description
FCMOVBE CF =1 or ZF =1 Below or equal
FCMOVNBE CF =0 or ZF =0N o t  b e l o w  n o r  e q u a l
FCMOVU PF =1 Unordered
FCMOVNU PF =0 Not unorderedTable 8-5.  Floating-Point Condit ional Move Instructions (Contd.)8-18 Vol. 1PROGRAMMING WITH THE X87 FPU
FSQRT Square root.
FPREM Partial remainder.
FPREM1 IEEE partial remainder.FRNDINT Round to integral value.
The add, subtract, multiply, and divide instructio ns operate on the following types of operands:
•Two x87 FPU data registers.
•An x87 FPU data register and a floating-point or integer value in memory.
See Section 8.1.2, “x87 FPU Data Registers,” for a descripti on of how operands are referenced on the data register 
stack.
Operands in memory can be in single precision floating -point, double precision floating-point, word-integer, or 
doubleword-integer format. They are converted to double extended precision floating-point format automatically.
Reverse versions of the subtract (FSUBR) and divide (FDIVR ) instructions enable effici ent coding. For example, the 
following options are available with the FSUB and FSUBR inst ructions for operating on values in a specified x87 FPU 
data register ST( i) and the ST(0) register:
FSUB:
ST(0) := ST(0) − ST(i)
ST(i) := ST( i) − ST(0)
FSUBR:
ST(0) := ST( i) − ST(0)
ST(i) := ST(0) − ST(i)
These instructions eliminate the need to exchange values  between the ST(0) register and another x87 FPU register 
to perform a subtraction or division.
The pop versions of the add, subtract , multiply, and divide instructions of fer the option of popping the x87 FPU 
register stack following the arithmetic operation. These instructions operate on values in the ST( i) and ST(0) regis-
ters, store the result in the ST( i) register, and pop the ST(0) register.
The FPREM instruction computes the remainder from the divi sion of two operands in the manner used by the Intel 
8087 and Intel 287 math coprocessors; the FPREM1 instruct ion computes the remainder in the manner specified in 
IEEE Standard 754.
The FSQRT instruction computes the square root of the source operand.
The FRNDINT instruction returns a floating-point value that is the integral value closest to the source value in the 
direction of the rounding mode specified in  the RC field of the x87 FPU control word.
The FABS, FCHS, and FXTRACT instructions perform conv enient arithmetic operations. The FABS instruction 
produces the absolute value of the source operand. The FC HS instruction changes the sign of the source operand. 
The FXTRACT instruction separates the source operand into its exponent and fraction and stores each value in a 
register in floating-point format.
8.3.6 Comparison and Classification Instructions
The following instructions compare or classify floating-point values:
FCOM/FCOMP/FCOMPP Compare floating-point  and set x87 FPU condition code flags.
FUCOM/FUCOMP/FUCOMPP Unordered compare floating -point and set x87 FPU condition code flags.
FICOM/FICOMP Compare integer and set x87 FPU condition code flags.FCOMI/FCOMIP Compare floating-point and set EFLAGS status flags.
FUCOMI/FUCOMIP Unordered compare floating -point and set EFLAGS status flags.
FTST Test (compare floating-point with 0.0).Vol. 1 8-19PROGRAMMING WITH THE X87 FPU
FXAM Examine.
Comparison of floating-point values differ from comparison  of integers because floating-point values have four 
(rather than three) mutually exclusive relationsh ips: less than, equal, greater than, and unordered.
The unordered relationship is true when at least one of the two values being compared is a NaN or in an unsup-
ported format. This additional relationship is required  because, by definition, NaNs are not numbers, so they 
cannot have less than, equal, or greater than relationships with other floating-point values.
The FCOM, FCOMP, and FCOMPP instructions compare the va lue in register ST(0) with a floating-point source 
operand and set the condition code flags (C0, C2, and C3) in the x87 FPU status word according to the results (see 
Table 8-6). 
If an unordered condition is detected (one or both of th e values are NaNs or in an undefined format), a floating-
point invalid-operation exception is generated.
The pop versions of the instruction pop the x87 FPU register  stack once or twice after the comparison operation is 
complete.
The FUCOM, FUCOMP, and FUCOMPP instructions operate th e same as the FCOM, FCOMP, and FCOMPP instructions. 
The only difference is that with the FUCOM, FUCOMP, an d FUCOMPP instructions, if an unordered condition is 
detected because one or both of the operands are QNaNs,  the floating-point invalid-operation exception is not 
The FICOM and FICOMP instructions also operate the same  as the FCOM and FCOMP instructions, except that the 
source operand is an integer value in memory. The inte ger value is automatically converted into an double 
extended precision floating-point value prior to making the comparison. The FICOMP instruction pops the x87 FPU 
register stack following the comparison operation.
The FTST instruction performs the same operation as the FC OM instruction, except that the value in register ST(0) 
is always compared with the value 0.0.
The FCOMI and FCOMIP instructions were introduced into th e IA-32 architecture in the P6 family processors. They 
perform the same comparison as the FCOM and FCOMP instructions, except that they set the status flags (ZF, PF, and CF) in the EFLAGS register to indicate the results of the comparison (see Table 8-7) instead of the x87 FPU 
condition code flags. The FCOMI and FCOMIP instructions allow condition branch instructions (J cc) to be executed 
directly from the results of their comparison.
Software can check if the FCOMI and FCOMIP instructions are supported by checking the processor’s feature infor-
mation with the CPUID instruction.
The FUCOMI and FUCOMIP instructions operate the same as  the FCOMI and FCOMIP instructions, except that they 
do not generate a floating-point invalid-operation exception if the unordered condition is the result of one or both 
of the operands being a QNaN. The FCOMIP and FUCOMIP in structions pop the x87 FPU register stack following the 
comparison operation.Table 8-6.  Setting of x87 FP U Condition Code Flags for Floating-Point Number Comparisons
Condition C3 C2 C0
ST(0) > Source Operand 0 0 0ST(0) < Source Operand 0 0 1ST(0) = Source Operand 1 0 0Unordered 1 1 1
Table 8-7.  Setting of EFLAGS Status Fl ags for Floating-Point Number Comparisons
Comparison Results ZF PF CF
ST0 > ST(i)0 0 0
ST0 < ST(i)0 0 1
ST0 = ST(i)1 0 0
Unordered 1 1 18-20 Vol. 1PROGRAMMING WITH THE X87 FPU
The FXAM instruction determines the classification of the fl oating-point value in the ST(0) register (that is, whether 
the value is zero, a denormal number, a normal finite number, ∞, a NaN, or an unsupported format) or that the 
register is empty. It sets the x87 FPU condition code fl ags to indicate the classification (see “FXAM—Examine” in 
Volume 2A). It also sets the C1 flag  to indicate the sign of the value.
8.3.6.1  Branching on the x87 FPU Condition Codes
The processor does not offer any control-flow instructions that branch on the setting of the condition code flags 
(C0, C2, and C3) in the x87 FPU status word. To branch on  the state of these flags, the x87 FPU status word must 
first be moved to the AX register in the integer unit. The FSTSW AX (store status word) instruction can be used for 
this purpose. When these flags are in the AX register, the TEST instruction can be used to control conditional 
branching as follows:
1. Check for an unordered result. Use the TEST instruction to compare the contents of the AX register with the 
constant 0400H (see Table 8-8). This operation will clear the ZF flag in the EFLAGS register if the condition code 
flags indicate an unordered result; otherwise, the ZF flag  will be set. The JNZ instruction can then be used to 
transfer control (if necessary) to a procedure for handling unordered operands.
2. Check ordered comparison result. Use the constants given in Table 8-8 in the TEST instruction to test for a less 
than, equal to, or greater than result, then use the co rresponding conditional branch instruction to transfer 
program control to the appropriate procedure or section of code.
If a program or procedure has been thorou ghly tested and it incorporates periodic checks for QNaN results, then it 
is not necessary to check for the unordered result every time a comparison is made.
See Section 8.1.4, “Branching and Conditional Moves on Condition Codes,” for another technique for branching on 
x87 FPU condition codes.
Some non-comparison x87 FPU instructions update the cond ition code flags in the x87 FPU status word. To ensure

Some non-comparison x87 FPU instructions update the cond ition code flags in the x87 FPU status word. To ensure 
that the status word is not altered inadvertently, store it immediately following a comparison operation.
8.3.7 Trigonometric Instructions
The following instructions perform four common trigonometric functions:
FSIN Sine.
FCOS Cosine.FSINCOS Sine and cosine.
FPTAN Tangent.
FPATAN Arctangent.
These instructions operate on the top one or two register s of the x87 FPU register stack and they return their 
results to the stack. The source operands for the FSIN, FCOS, FSINCOS, and FPTAN instructions must be given in 
radians; the source operand for the FPATAN instruction is given in rectangular coordinate units.
The FSINCOS instruction returns both the sine and the cosine of a source operand value. It operates faster than 
executing the FSIN and FCOS instructions in succession.Table 8-8.  TEST Instruction Constants for Conditional Branching
Order Constant Branch
ST(0) > Source Operand 4500H JZ
ST(0) < Source Operand 0100H JNZ
ST(0) = Source Operand 4000H JNZ
Unordered 0400H JNZVol. 1 8-21PROGRAMMING WITH THE X87 FPU
The FPATAN instruction computes the arctangent of ST(1) di vided by ST(0), returning a result in radians. It is 
useful for converting rectangular coordinates to polar coordinates.
See Section 8.3.8, “Approximation of Pi,” and Section 8. 3.10, “Transcendental Instruction Accuracy,” for informa-
tion regarding the accuracy of these instructions. 
8.3.8 Approximation of Pi
When the argument (source operand) of a trigonometric function is within the domain of the function, the argu-ment is automatically reduced by the appropriate multiple of 2 π through the same reduction mechanism used by 
the FPREM and FPREM1 instructions. The internal value of π (3.1415926…) that the x87 FPU uses for argument 
reduction and other computations, denoted as Pi in the expr ession below. The numerical value of Pi can be written 
as:
Pi = 0.f ∗ 2
2
where the fraction f is expr essed in binary form as:
f = C90FDAA2  2168C234  C
(The spaces in the fraction above indicate 32-bit boundaries.)
The internal approximation Pi of the value π has a 66 significant bits. Since the exact value of π represented in 
binary has the next 3 bits equal to 0,  it means that Pi is the value of π rounded to nearest-even to 68 bits, and also 
the value of π rounded toward zero (truncated) to 69 bits.
However, accuracy problems may arise because this relatively short finite approximation Pi of the number π is used 
for calculating the reduced argument of  the trigonometric function approximations in the implementations of FSIN, 
FCOS, FSINCOS, and FPTAN. Alternately,  this means that FSIN (x), FCOS (x ), and FPTAN (x) are really approxi-
mating the mathematical functions sin (x * π /Pi), cos (x * π / Pi), and tan (x * π / Pi), and not exactly sin (x), cos 
(x), and tan (x). (Note that FSINCOS is the equivalent of FSIN and FCOS combined together). The period of sin (x 
* π /Pi) for example is 2* Pi, and not 2π. 
See also Section 8.3.10, “Transcendental Instruction Accu racy,” for more information on the accuracy of these 
8.3.9 Logarithmic, Exponential, and Scale
The following instructions provide two different logarithmic functions, an exponential function and a scale function:
FYL2X Logarithm.
FYL2XP1 Logarithm epsilon.
F2XM1 Exponential.
FSCALE Scale.
The FYL2X and FYL2XP1 instructions pe rform two different base 2 logarithmi c operations. The FYL2X instruction 
computes (y ∗ log2x). This operation permits the calculation of th e log of any base using the following equation:
logb x = (1/log2 b) ∗ log2 x
The FYL2XP1 instruction computes (y ∗ log2(x + 1)). This operation provides optimum accuracy for values of x that 
are close to 0.
The F2XM1 instruction computes (2x − 1). This instruction only operates on source values in the range −1.0 to +1.0.
The FSCALE instruction multiplies the source operand by a power of 2.
8.3.10 Transcendental Instruction Accuracy
New transcendental instruction algorithms were incorpor ated into the IA-32 archit ecture beginning with the 
Pentium processors. These new algorithms (used in tran scendental instructions FSIN, FCOS, FSINCOS, FPTAN, 
FPATAN, F2XM1, FYL2X, and FYL2XP1) allow a higher level of  accuracy than was possible in earlier IA-32 processors 8-22 Vol. 1PROGRAMMING WITH THE X87 FPU
and x87 math coprocessors. The accuracy of these instructions is measured in terms of units in the last place  
(ulp). For a given argument x, let f(x) and F(x) be the correct and computed (approximate) function values, 
respectively. The error in ulps is defined to be:
where k is an integer such that:
With the Pentium processor and later IA-32 processors, the worst case error on transcendental functions is less 
than 1 ulp when rounding to the nearest (even) and less than 1.5 ulps when rounding in other modes. The func-
tions are guaranteed to be monotonic, with respect to th e input operands, throughout the domain supported by the 
However, for FSIN, FCOS, FSINCOS, and FPTAN which approx imate periodic trigonometric functions, the previous 
statement about maximum ulp errors is true only when th ese instructions are applied to reduced argument (see 
Section 8.3.8, “Approximation of Pi”). This  is due to the fact that only 66 significant bits are retained in the finite 
approximation Pi of the number π (3.1415926…), used internally for calculating the reduced argument in FSIN, 
FCOS, FSINCOS, and FPTAN. This approximation of π is not always sufficiently accurate for good argument reduc-
tion. 
For single precision, the argument of FSIN, FCOS, FSIN COS, and FPTAN must exceed 200,000 radians in order for 
the error of the result to exceed 1 ulp when rounding to  the nearest (even), or 1.5 ulps when rounding in other 
(directed) rounding modes.
For double and double-extended precision, the ulp errors  will grow above these thresholds for arguments much 
smaller in magnitude. The ulp errors increase significantly when the argument approaches the value of π (or Pi) for 
FSIN, and when it approaches π/2(or Pi/2) for FCOS, FSINCOS, and FPTAN.
For all three IEEE precisions supported (32-bit single pr ecision, 64-bit double precision, and 80-bit double-
extended precision), applying FSIN, FCOS, FSINCOS, or FP TAN to arguments larger than a certain value can lead 
to reduced arguments (calculated internally) that are inaccurate or even very inaccurate in some cases. This leads 
to equally inaccurate approximations of the corresponding  mathematical functions. In particular, arguments that 
are close to certain values will lose significance when reduced, leading to increased relative (and ulp) errors in the 
results of FSIN, FCOS, FSINCOS, and FPTAN. These values are: 
•Any non-zero multiple of π for FSIN.
•Any multiple of π, plus π/2 for FCOS.
•Any non-zero multiple of π/2 for FSINCOS and FPTAN. 
If the arguments passed to FSIN, FCOS, FSINCOS, and FPTA N are not close to these values then even the finite 
approximation Pi of π used internally for argument reduction will allow for results that have good accuracy.
Therefore, in order to avoid such errors it is recommended to perform accurate argument reduction in software, 
and to apply FSIN, FCOS, FSINCOS, and FPTAN to reduce d arguments only. Regardless of the target precision 
(single, double, or double-extended), it is safe to reduce  the argument to a value smaller in absolute value than 
about 3 π/4 for FSIN, and smaller than about 3 π/8 for FCOS, FSINCOS, and FPTAN. 
The thresholds shown above are not ex act. For example, accuracy measurem ents show that the double-extended 
precision result of FSIN will not have errors larger than 0.72 ulp for |x| < 2.82 (so |x| < 3 π/4 will ensure good accu-
racy, as 3 π/4 < 2.82). On the same interval, double precision re sults from FSIN will have errors at most slightly 
larger than 0.5 ulp, and single precision results will  be correctly rounded in the vast majority of cases.
Likewise, the double-extended precision result of FCOS will not have errors larger than 0.82 ulp for |x| < 1.31 (so 
|x| < 3 π/8 will ensure good accuracy, as 3 π/8 < 1.31). On the same interval, do uble precision results from FCOS 
will have errors at most slightly larger than 0.5 ulp, and si ngle precision results will be correctly rounded in the vast 
majority of cases.
FSINCOS behaves similarly to FSIN and FCOS, combined as a pair.errorfx() Fx()–
2k6 3–-------------------------- - =
12k–fx() 2.< ≤Vol. 1 8-23PROGRAMMING WITH THE X87 FPU
Finally, the double-extended precision result of FPTAN will not have errors larger than 0.78 ulp for |x| < 1.25 (so 
|x| < 3 π/8 will ensure good accuracy, as 3 π/8 < 1.25). On the same interval, double precision results from FPTAN 
will have errors at most slightly larger than 0.5 ulp, and single precision results will be correctly rounded in the vast 
A recommended alternative in order to avoid the accuracy issues that might be caused by FSIN, FCOS, FSINCOS,

A recommended alternative in order to avoid the accuracy issues that might be caused by FSIN, FCOS, FSINCOS, 
and FPTAN, is to use good quality mathematical library im plementations of the sin, cos, sincos, and tan functions, 
for example those from the Intel® Math Library available in the Intel® Compiler.
The instructions FYL2X and FYL2XP1 are two operand instruct ions and are guaranteed to be within 1 ulp only when 
y equals 1. When y is not equal to 1, the maximum ulp error is always within 1.35 ulps in round to nearest mode. (For the two operand functions, monotonicity was proved by holding one of the operands constant.)
8.3.11 x87 FPU Control Instructions
The following instructions control the state and modes of oper ation of the x87 FPU. They also allow the status of the 
x87 FPU to be examined:
FINIT/FNINIT Initialize x87 FPU.
FLDCW Load x87 FPU control word.
FSTCW/FNSTCW Store x87 FPU control word.FSTSW/FNSTSW Store x87 FPU status word.
FCLEX/FNCLEX Clear x87 FPU exception flags.
FLDENV Load x87 FPU environment.FSTENV/FNSTENV Store x87 FPU environment.
FRSTOR Restore x87 FPU state.
FSAVE/FNSAVE Save x87 FPU state.FINCSTP Increment x87 FPU register stack pointer.
FDECSTP Decrement x87 FPU register stack pointer.
FFREE Free x87 FPU register.FNOP No operation.
WAIT/FWAIT Check for and handle pending unmasked x87 FPU exceptions.
The FINIT/FNINIT instructions initialize the x87 FP U and its internal registers to default values.
The FLDCW instructions loads the x87 FPU control word register with a value from memory. The FSTCW/FNSTCW 
and FSTSW/FNSTSW instructions store the x87 FPU control an d status words, respectively, in memory (or for an 
FSTSW/FNSTSW instruction in a general-purpose register).
The FSTENV/FNSTENV and FSAVE/FNSAVE instructions save the x87 FPU environment and state, respectively, in 
memory. The x87 FPU environment includes all the x87 FP U’s control and status registers; the x87 FPU state 
includes the x87 FPU environment and the data registers in the x87 FPU register stack. (The FSAVE/FNSAVE 
instruction also initializes the x87 FPU to default values, lik e the FINIT/FNINIT instruction, after it saves the original 
state of the x87 FPU.) 
The FLDENV and FRSTOR instructions load the x87 FPU envi ronment and state, respectively, from memory into the 
x87 FPU. These instructions are commonly used when switching tasks or contexts.
The WAIT/FWAIT instructions are synchronization instructions. (They are actually mnemonics for the same 
opcode.) These instructions check the x87 FPU status word for pending unmasked x87 FPU exceptions. If any 
pending unmasked x87 FPU exceptions are found, they are handled before the processor resumes execution of the 
instructions (integer, floating-point, or system instruction) in the instruction stream. The WAIT/FWAIT instructions 
are provided to allow synchronization of instruction ex ecution between the x87 FPU and the processor’s integer 
unit. See Section 8.6, “x87 FPU Exception Synchronization, ” for more information on the use of the WAIT/FWAIT 
instructions.8-24 Vol. 1PROGRAMMING WITH THE X87 FPU
8.3.12 Waiting vs. Non-waiting Instructions
All of the x87 FPU instructions except a few special cont rol instructions perform a wait operation (similar to the 
WAIT/FWAIT instructions), to check for and handle pend ing unmasked x87 FPU floating-point exceptions, before 
they perform their primary operation (such as adding tw o floating-point numbers). These instructions are called 
waiting  instructions. Some of the x87 FPU control instructions, such as FSTSW/FNSTSW, have both a waiting and 
a non-waiting version. The waiting version (with the “F” pr efix) executes a wait operation before it performs its 
primary operation; whereas, the non-waiting version (wit h the “FN” prefix) ignores pending unmasked exceptions. 
Non-waiting instructions allow software to save the curre nt x87 FPU state without first handling pending exceptions 
or to reset or reinitialize the x87 FPU without regard for pending exceptions.
NOTES
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible 
(under unusual circumstances) for a non-waiting instruction to be interrupted prior to being executed to handle a pending x87 FPU exception. 
When operating a P6 family, Pentium 4, or Inte l Xeon processor in MS-DOS compatibility mode, 
non-waiting instructions can not be interrupted in this way.
8.3.13 Unsupported x87 FPU Instructions
The Intel 8087 instructions FENI and FDISI and the Inte l 287 math coprocessor instruction FSETPM perform no 
function in the Intel 387 math coprocessor and later IA-32 processors. If these opcodes are detected in the instruc-
tion stream, the x87 FPU performs no specific oper ation and no internal x87 FPU states are affected.
8.4 X87 FPU FLOATING-POINT EXCEPTION HANDLING
The x87 FPU detects the six classes of exception conditions  described in Section 4.9, “Overview of Floating-Point 
Exceptions”:
•Invalid operation (#I), with two subclasses:
— Stack overflow or underflow (#IS).
— Invalid arithmetic operation (#IA).
Each of the six exception classes has a corresponding flag bit in the x87 FPU status word and a mask bit in the x87 
FPU control word (see Section 8.1.3, “x87 FPU Status Regi ster,” and Section 8.1.5, “x87 FPU Control Word,” respec-
tively). In addition, the exception summary (ES) flag in  the status word indicates when one or more unmasked 
exceptions has been detected. The stack fault (SF) flag (also in the status word) distinguishes between the two types of invalid-operation exceptions.
The mask bits can be set with FLDCW, FRSTOR, or FX RSTOR; they can be read with either FSTCW/FNSTCW, 
FSAVE/FNSAVE, or FXSAVE. The flag bits can be read wi th the FSTSW/FNSTSW, FSAVE/FNSAVE, or FXSAVE instruc-
tion.
NOTE
Section 4.9.1, “Floating-Point Exception Conditions ,” provides a general overview of how the IA-32 
processor detects and handles the various classes of floating-point exceptions. This information 
pertains to the x87 FPU as well as the Intel SSE, SSE2, and SSE3 instructions. Vol. 1 8-25PROGRAMMING WITH THE X87 FPU
The following sections give specific information about ho w the x87 FPU handles floating-point exceptions that are 
unique to the x87 FPU.
8.4.1 Arithmetic vs. Non- arithmetic Instructions
When dealing with floating-point exceptio ns, it is useful to distinguish between arithmetic instructions  and non-
arithmetic instructions . Non-arithmetic instructions have no operands or do not make substantial changes to 
their operands. Arithmetic instructions do make signific ant changes to their operands; in particular, they make 
changes that could result in floating-point exceptions be ing signaled. Table 8-9 lists the non-arithmetic and arith-
metic instructions. It should be noted that some non-arithmetic instructions can signal a floating-point stack (fault) 
exception, but this exception is not the result of an operation on an operand.
Table 8-9.  Arithmetic and Non-arithmetic Instructions
Non-arithmetic Instructio ns Arithmetic Instructions
FABS F2XM1FCHS FADD/FADDPFCLEX FBLD
FDECSTP FBSTP
FFREE FCOM/FCOMP/FCOMPPFINCSTP FCOS
FINIT/FNINIT FDIV/F DIVP/FDIVR/FDIVRP
FLD (register-to-register) FIADDFLD (extended format from memory) FICOM/FICOMP
FLD constant FIDIV/FIDIVR
FLDCW FILDFLDENV FIMUL
FNOP FIST/FISTP
1
FRSTOR FISUB/FISUBR
FSAVE/FNSAVE FLD (single and double)
FST/FSTP (register-to-register) FMUL/FMULP
FSTP (extended format to memory) FPATANFSTCW/FNSTCW FPREM/FPREM1
FSTENV/FNSTENV FPTAN
FSTSW/FNSTSW FRNDINTWAIT/FWAIT FSCALE
FXAM FSIN
FXCH FSINCOS
FSQRT
FST/FSTP (single and double)
FSUB/FSUBP/FSUBR/FSUBRPFTST
FUCOM/FUCOMP/FUCOMPP
FXTRACTFYL2X/FYL2XP18-26 Vol. 1PROGRAMMING WITH THE X87 FPU
8.5 X87 FPU FLOATING-POINT EXCEPTION CONDITIONS
The following sections describe the various conditions that cause a floating-point exception to be generated by the 
x87 FPU and the masked response of the x87 FPU when these conditions are detected. The Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, lists the floating-point exceptions that can be signaled for each floating-point instruction.
8.5.1 Invalid Operation Exception
The floating-point invalid-operation exception occurs in response to two sub-classes of operations:
•Stack overflow or underflow (#IS).
•Invalid arithmetic operand (#IA).
The flag for this exception (IE) is bit 0 of the x87 FPU st atus word, and the mask bit (IM) is bit 0 of the x87 FPU 
control word. The stack fault flag (SF) of the x87 FPU stat us word indicates the type of operation that caused the 
exception. When the SF flag is set to 1, a stack operation has resulted in stack overflow or underflow; when the flag is cleared to 0, an arithmetic instruction has encountered an invalid operand. Note that the x87 FPU explicitly sets

exception. When the SF flag is set to 1, a stack operation has resulted in stack overflow or underflow; when the flag is cleared to 0, an arithmetic instruction has encountered an invalid operand. Note that the x87 FPU explicitly sets 
the SF flag when it detects a stack overflow or underflow co ndition, but it does not explic itly clear the flag when it 
detects an invalid-arithmetic-operand condition. As a result , the state of the SF flag can be 1 following an invalid-
arithmetic-operation exception, if it was not cleared from  the last time a stack overflow or underflow condition 
occurred. See Section 8.1.3.4, “Stack Fault Fl ag,” for more information about the SF flag.
8.5.1.1  Stack Overflow or  Underflow Exception (#IS)
The x87 FPU tag word keeps track of the contents of the re gisters in the x87 FPU register stack (see Section 8.1.7, 
“x87 FPU Tag Word”). It then uses this information to detect two different types of stack faults:
•Stack overflow  — An instruction attempts to load a non-em pty x87 FPU register from memory. A non-empty 
register is defined as a register containing a zero (tag va lue of 01), a valid value (tag  value of 00), or a special 
value (tag value of 10).
•Stack underflow  — An instruction references an empty x87 FPU register as a source operand, including 
attempting to write the contents of an empty register  to memory. An empty register has a tag value of 11.
NOTES
The term stack overflow originates from the situ ation where the program has loaded (pushed) eight 
values from memory onto the x87 FPU register stac k and the next value pushed on the stack causes 
a stack wraparound to a register that already contains a value.
The term stack underflow originates from the op posite situation. Here, a program has stored 
(popped) eight values from the x87 FPU register stack to memory and the next value popped from 
the stack causes stack wraparound to an empty register.
When the x87 FPU detects stack overflow or underflow, it sets the IE flag (bit 0) and the SF flag (bit 6) in the x87 
FPU status word to 1. It then sets condition-code flag C1 (bit 9) in the x87 FPU status word to 1 if stack overflow 
occurred or to 0 if stack underflow occurred. NOTE:
1. The FISTTP instruction in SSE3 is an arithmetic x87 FPU instruction.Table 8-9.  Arithmetic and Non- arithmetic Instru ctions (Contd.)
Non-arithmetic Instructions Arithmetic InstructionsVol. 1 8-27PROGRAMMING WITH THE X87 FPU
If the invalid-operation exception is masked, the x87 FPU returns the floating-point, integer, or packed decimal 
integer indefinite value to the destination operand, depe nding on the instruction being executed. This value over-
writes the destination register or memory location specified by the instruction.
If the invalid-operation exception is not masked, a software exception handler is invoked (see Section 8.7, 
“Handling x87 FPU Exceptions in Software”) and the to p-of-stack pointer (TOP) and source operands remain 
unchanged.
8.5.1.2  Invalid Arithmetic Operand Exception (#IA)
The x87 FPU is able to detect a variety of invalid arithmet ic operations that can be coded in a program. These oper-
ations are listed in Table 8-10. (This list includes  the invalid operations defined in IEEE Standard 754.)
When the x87 FPU detects an invalid arithmetic operand, it se ts the IE flag (bit 0) in the x87 FPU status word to 1. 
If the invalid-operation exception is masked, the x87 FPU th en returns an indefinite value or QNaN to the destina-
tion operand and/or sets the floating-point condition code s as shown in Table 8-10. If the invalid-operation excep-
tion is not masked, a software exception handler is invo ked (see Section 8.7, “Handling x87 FPU Exceptions in 
Software”) and the top-of-stack pointer (TOP) and source operands remain unchanged.
Normally, when one or both of the source operands is a QNaN (and neither is an SNaN or in an unsupported 
format), an invalid-operand exception is not generated. An exception to this rule is most of the compare instruc-
tions (such as the FCOM and FCOMI instructions) and the floating-point to integer conversion instructions Table 8-10.  Invalid Arithmetic Operat ions and the Masked Responses to Them
Condition Masked Response
Any arithmetic operation on an operand that is in an unsupported 
format.Return the QNaN floating-poi nt indefinite value to the 
destination operand.
Any arithmetic operation on a SNaN. Return a QNaN to the destination operand (see Table 4-7).Ordered compare and test operations: one or both operands are 
NaNs.Set the condition code flags (C0, C2, and C3) in the x87 FPU 
status word or the CF, PF, and ZF flags in the EFLAGS register to 111B (not comparable).
Addition: operands are opposite-signed infinities.
Subtraction: operands are like-signed infinities.Return the QNaN floating-poi nt indefinite value to the 
Multiplication: ∞ by 0; 0 by ∞. Return the QNaN floating-point indefinite value to the 
Division: ∞ by  ∞; 0 by 0. Return the QNaN floating -point indefinite  value to the 
Remainder instructions FPREM, FPREM1: modulus (divisor) is 0 or 
dividend is ∞.Return the QNaN floating-point indefinite; clear condition code 
flag C2 to 0.
Trigonometric instructions FCOS, FPTAN, FSIN, FSINCOS: source 
operand is ∞.Return the QNaN floating-point indefinite; clear condition code 
FSQRT: negative operand (except FSQRT (–0) = –0); FYL2X: negative 
operand (except FYL2X (–0) = – ∞); FYL2XP1: operand more 
negative than –1.Return the QNaN floating-poi nt indefinite value to the 
FBSTP: Converted value cannot be represented in 18 decimal digits, 
or source value is an SNaN, QNaN, ±∞, or in an unsupported 
format.Store packed BCD integer indefinite value in the destination 
operand.
FIST/FISTP: Converted value exceeds representable integer range 
of the destination operand, or source value is an SNaN, QNaN, ±∞, 
or in an unsupported format.Store integer indefinite valu e in the destination operand.
FXCH: one or both registers are tagged empty. Load empty registers with the QNaN floating-point indefinite 
value, then perform the exchange.8-28 Vol. 1PROGRAMMING WITH THE X87 FPU
(FIST/FISTP and FBSTP). With these instructions, a QNaN source operand will generate an invalid-operand excep-
tion.
8.5.2 Denormal Operand Exception (#D)
The x87 FPU signals the denormal-operand exception under the following conditions:
•If an arithmetic instruction attempts to operate on a denormal operand (see Section 4.8.3.2, “Normalized and 
Denormalized Finite Numbers”).
•If an attempt is made to load a denormal single precis ion or double precision floating-point value into an x87 
FPU register. (If the denormal value being loaded is a double extended precision floating-point value, the 
denormal-operand except ion is not reported.)
The flag (DE) for this exception is bit 1 of the x87 FPU st atus word, and the mask bit (D M) is bit 1 of the x87 FPU 
control word.
When a denormal-operand exception oc curs and the exception is masked, the x87 FPU sets the DE flag, then 
proceeds with the instruction. The denormal operand in single- or double precision floating-point format is auto-
matically normalized when converted to the double exte nded precision floating-point format. Subsequent opera-
tions will benefit from the additional precision of the internal double extended precision floating-point format.
When a denormal-operand exception occurs and the exception is not masked, the DE flag is set and a software 
exception handler is invoked (see Section 8.7, “Handlin g x87 FPU Exceptions in Software”). The top-of-stack 
pointer (TOP) and source operands remain unchanged.
For additional information about the denormal-operation  exception, see Section 4.9.1.2, “Denormal Operand 
Exception (#D).”
8.5.3 Divide-By-Zero Exception (#Z)
The x87 FPU reports a floating-point divide-by-zero exceptio n whenever an instruction attempts to divide a finite 
non-zero operand by 0. The flag (ZE) for this exception is  bit 2 of the x87 FPU status word, and the mask bit (ZM) 
is bit 2 of the x87 FPU control word. The FDIV, FDIVP, FDIV R, FDIVRP, FIDIV, and FIDIVR instructions and the other 
instructions that perform division internally (FYL2X and FXTRACT) can report the divide-by-zero exception. 
When a divide-by-zero exception occurs and the exception is masked, the x87 FPU sets the ZE flag and returns the 
values shown in Table 8-10. If the divide-by-zero exception is not masked, the ZE flag is set, a software exception 
handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions in Software”), and the top-of-stack pointer 
(TOP) and source operands remain unchanged.
8.5.4 Numeric Overflow Exception (#O)
The x87 FPU reports a floating-point numeric overflow ex ception (#O) whenever the rounded result of an arith-
metic instruction exceeds the largest allowable finite value th at will fit into the floating-point format of the destina-
tion operand. (See Section 4.9.1.4, “Numeric Overflow  Exception (#O),” for additional information about the 
numeric overflow exception.)
When using the x87 FPU, numeric overflow can occur on arit hmetic operations where the result is stored in an x87

When using the x87 FPU, numeric overflow can occur on arit hmetic operations where the result is stored in an x87 
FPU data register. It can also occur on store floating-point operations (using the FST and FSTP instructions), where 
a within-range value in a data register is stored in memory  in a single precision or double precision floating-point Table 8-11.  Divide-By-Zero Conditions and the Masked Responses to Them
Divide or reverse divide operation with a 
0 divisor.Returns an ∞ signed with the exclusive OR of the sign of the two operands to the 
FYL2X instruction. Returns an ∞ signed with the opposite  sign of the non-zero operand to the destination 
operand.
FXTRACT instruction. ST(1) is set to – ∞; ST(0) is set to 0 with the sa me sign as the source operand.Vol. 1 8-29PROGRAMMING WITH THE X87 FPU
format. The numeric overflow exception cannot occur when storing values in an integer or BCD integer format. 
Instead, the invalid-arithmetic-operand exception is signaled.
The flag (OE) for the numeric-overflow exception is bit 3 of the x87 FPU status word, and the mask bit (OM) is bit 
3 of the x87 FPU control word. 
When a numeric-overflow exception occurs and the exceptio n is masked, the x87 FPU sets  the OE flag and returns 
one of the values shown in Table 4-10. The value returned  depends on the current rounding mode of the x87 FPU 
(see Section 8.1.5.3, “Rounding Control Field”).
The action that the x87 FPU takes when numeric overfl ow occurs and the numeric-overflow exception is not 
masked, depends on whether the instruction is supposed to store the result in memory or on the register stack.
•Destination is a memory location —  The OE flag is set and a software exception handler is invoked (see 
Section 8.7, “Handling x87 FPU Exce ptions in Software”). The top-of-stack pointer (TOP) and source and 
destination operands remain unchanged. Because the data in the stack is in double extended precision format, 
the exception handler has the option either of re-executi ng the store instruction after proper adjustment of the 
operand or of rounding the significand on the stack to th e destination's precision as the standard requires. The 
exception handler should ultimately store a value into th e destination location in memory if the program is to 
continue.
•Destination is the register stack —  The significand of the result is rounded according to current settings of 
the precision and rounding control bits in the x87 FPU co ntrol word and the exponent of the result is adjusted 
by dividing it by 224576. (For instructions not affected by the prec ision field, the significand is rounded to 
double-extended precision.) The resultin g value is stored in the destination operand. Condition code bit C1 in 
the x87 FPU status word (called in this situation the “ro und-up bit”) is set if the significand was rounded upward 
and cleared if the result was rounded toward 0. After the result is stored , the OE flag is set and a software 
exception handler is invoked. The scali ng bias value 24,576 is equal to 3 ∗ 213. Biasing the exponent by 24,576 
normally translates the number as nearly as possible to  the middle of the double extended precision floating-
point exponent range so that, if desired, it can be used in subsequent scaled operations with less risk of causing 
further exceptions.
When using the FSCALE instruction, massive overflow ca n occur, where the result is too large to be repre-
sented, even with a bias-adjusted exponent. Here, if over flow occurs again, after the result has been biased, a 
properly signed ∞ is stored in the destination operand.
8.5.5 Numeric Underflow Exception (#U)
The x87 FPU detects a potential floating -point numeric underflow condition whenever the result of an arithmetic 
instruction is non-zero and tiny; that is, the magnitude of the rounded result with unbounded exponent is non-zero 
and less than the smallest possible normalized, finite value that will fit into the floating-point format of the desti-
nation operand. See Section 4.9.1.5, “Numeric Underflo w Exception (#U),” for additional information about the 
numeric underflow exception.
Like numeric overflow, numeric underflow can occur on arithmetic operations where the result is stored in an x87 
FPU data register. It can also occur on store floating-poi nt operations (with the FST and FSTP instructions), where 
a within-range value in a data register is stored in me mory in the smaller single precision or double precision 
floating-point formats. A numeric underflow exception cannot occur when storing values in an integer or BCD 
integer format, because a value with magnitude less than 1 is always rounded to an integral value of 0 or 1, 
depending on the rounding mode in effect.
The flag (UE) for the numeric-underflow exception is bit 4 of the x87 FPU status word, and the mask bit (UM) is bit 
4 of the x87 FPU control word.
When a numeric-underflow condition occurs and the exce ption is masked, the x87 FPU performs the operation 
described in Section 4.9.1.5, “Numeric Underflow Exception (#U).”
When the exception is not masked, the action of the x87 FPU depends on whether the instruction is supposed to 
store the result in a memory location  or on the x87 FPU resister stack.
•Destination is a memory location —  (Can occur only with a store instruction.) The UE flag is set and a 
software exception handler is invoked; see Section 8.2,  “x87 FPU Data Types.” The top-of-stack pointer (TOP) 
and source and destination operands remain unch anged, and no result is stored in memory. 
Because the data in the stack is in double extended precision format, the exception handler has the option 8-30 Vol. 1PROGRAMMING WITH THE X87 FPU
either of re-exchanges the store instruction after pr oper adjustment of the operand or of rounding the 
significand on the stack to the destination's precision as the standard requires. Th e exception handler should 
ultimately store a value into the destination location in memory if the program is to continue.
by multiplying it by 224576. (For instructions not affected by the prec ision field, the significand is rounded to 
double extended precision.) The resulting value is stored  in the destination operand. Condition code bit C1 in 
the x87 FPU status register (acting here as a “round-up bit”) is set if the significand was rounded upward and 
cleared if the result was rounded toward  0. After the result is stored, the UE  flag is set and a software exception 
handler is invoked. The scaling bias value 24,576 is the same as is used for the overflow exception and has the 
same effect, which is to translate the result as nearly as possible to the middle of the double extended precision 
floating-point exponent range.
When using the FSCALE instruction, massive underflow can occur, where the magnitude of the result is too 
small to be represented, even with a bias-adjusted expo nent. Here, if underflow occurs again after the result 
has been biased, a properly signed 0 is stored in the destination operand.
8.5.6 Inexact-Result (Precision) Exception (#P)
representable in the destination format. (See Section 4. 9.1.6, “Inexact-Result (Precision) Exception (#P),” for 
additional information about the numeric overflow except ion.) Note that the transcendental instructions (FSIN, 
FCOS, FSINCOS, FPTAN, FPATAN, F2XM1, FYL2X, an d FYL2XP1) by nature produce inexact results.
The inexact-result exception flag (PE) is bit 5 of the x87 FPU status word, and the mask bit (PM) is bit 5 of the x87 
FPU control word. 
If the inexact-result exception is masked when an inexact-result condition occurs and a numeric overflow or under-
flow condition has not occurred, the x87 FPU handles the ex ception as describe in Section 4.9.1.6, “Inexact-Result 
(Precision) Exception (#P),” with one additional action. The C1 (round-up) bit in the x87 FPU status word is set to 
indicate whether the inexact result was rounded up (C1 is set) or “not rounded up” (C1 is cleared). In the “not 
rounded up” case, the least-significant bits of the inexact result are truncated so that the result fits in the destina-tion format.
If the inexact-result exception is not masked when an inexact result occurs and numeric overflow or underflow has 
not occurred, the x87 FPU handles the exception as described  in the previous paragraph and, in addition, invokes 
a software exception handler.
If an inexact result occurs in conjunction with numeric overflow or underflow, the x87 FPU carries out one of the 
following operations:
•If an inexact result occurs in conjunction with masked overflow or underflow, the OE or UE flag and the PE flag 
are set and the result is stored as described for the overflow or underflow exceptions (see Section 8.5.4,

are set and the result is stored as described for the overflow or underflow exceptions (see Section 8.5.4, 
“Numeric Overflow Exception (#O),” or Section 8.5.5,  “Numeric Underflow Exception (#U)”). If the inexact 
result exception is unmasked, the x87 FPU also invokes a software exception handler.
•If an inexact result occurs in conjunction with unmasked overflow or underflow and the destination operand is 
a register, the OE or UE flag and the PE flag are set, the result is stored as described for the overflow or 
underflow exceptions (see Section 8.5.4, “Numeric Ov erflow Exception (#O),” or Section 8.5.5, “Numeric 
Underflow Exception (#U)”) and a software exception handler is invoked.
cleared.
8.6 X87 FPU EXCEPTION SYNCHRONIZATION
Because the integer unit and x87 FPU are separate execution units, it is possible for the processor to execute floating-point, integer, and system instructions concurre ntly. No special programming techniques are required to 
gain the advantages of concurrent execution. (Floating-point instructions are placed in the instruction stream along Vol. 1 8-31PROGRAMMING WITH THE X87 FPU
with the integer and system instructions.) However, conc urrent execution can cause problems for floating-point 
exception handlers. 
This problem is related to the way the x87 FPU signals the existence of unmasked floating-point exceptions. 
(Special exception synchronization is not required for masked floating-point exceptions, because the x87 FPU 
always returns a masked result to the destination operand.) 
When a floating-point exception is unmasked and the exception condition occurs, the x87 FPU stops further execu-
tion of the floating-point instruction and signals the exce ption event. On the next occurrence of a floating-point 
instruction or a WAIT/FWAIT instruction in the instruction stream, the processor checks the ES flag in the x87 FPU 
status word for pending floating-point exceptions. If floa ting-point exceptions are pending, the x87 FPU makes an 
implicit call (traps) to the floating-point software ex ception handler. The exception handler can then execute 
recovery procedures for selected or all floating-point exceptions.
Synchronization problems occur in the time between the mo ment when the exception is signaled and when it is 
actually handled. Because of concurrent execution, intege r or system instructions can be executed during this 
time. It is thus possible for the source or destination operands for a floating-point instruction that faulted to be overwritten in memory, making it impossible for the exce ption handler to analyze or recover from the exception.
To solve this problem, an exception synchronizing instruct ion (either a floating-point instruction or a WAIT/FWAIT 
instruction) can be placed immediately after any floating -point instruction that might present a situation where 
state information pertaining to a floating-point exception might be lost or corrupted. Floating-point instructions 
that store data in memory are prime candidates for synchr onization. For example, the fo llowing three lines of code 
have the potential for exception synchronization problems:
FILD COUNT ;Floating-point instruction
INC COUNT ;Integer instructionFSQRT ;Subsequent floating-point instruction
In this example, the INC instruction modifies the source operand of the floating-point instruction, FILD. If an 
exception is signaled during the execution of the FILD in struction, the INC instruction would be allowed to over-
write the value stored in the COUNT memory location before  the floating-point exception handler is called. With the 
COUNT variable modified, the floating-point exception handler would not be able to recover from the error.
Rearranging the instructions, as follows, so that the FSQR T instruction follows the FILD  instruction, synchronizes 
floating-point exception handling and eliminates the possibi lity of the COUNT variable being overwritten before the 
floating-point exception handler is invoked.
FSQRT      ;Subsequent floating-point instruction synchronizes
           ;any exceptions  generated by the FILD instruction.
INC COUNT  ;Integer instruction
The FSQRT instruction does not require any synchronization,  because the results of this instruction are stored in 
the x87 FPU data registers and will remain there, undisturb ed, until the next floating-point or WAIT/FWAIT instruc-
tion is executed. To absolutely ensure that any exceptio ns emanating from the FSQRT instruction are handled (for 
example, prior to a procedure call), a WAIT instruction can be placed directly after the FSQRT instruction.
Note that some floating-point instructions (non-waiting instructions) do not check for pending unmasked excep-
tions (see Section 8.3.11, “x87 FPU Control Instructions ”). They include the FNINIT, FNSTENV, FNSAVE, FNSTSW, 
FNSTCW, and FNCLEX instructions. When an FNINIT, FNSTE NV, FNSAVE, or FNCLEX instruction is executed, all 
pending exceptions are essentially lost (either the x87 FPU st atus register is cleared or all exceptions are masked). 
The FNSTSW and FNSTCW instructions do not check for pe nding interrupts, but they do not modify the x87 FPU 
status and control registers. A subsequent “waiting” floa ting-point instruction can then handle any pending excep-
tions.
8.7 HANDLING X87 FPU EX CEPTIONS IN SOFTWARE
The x87 FPU in Pentium and later IA-32 processors provides  two different modes of operation for invoking a soft-
ware exception handler for floating-point exceptions: na tive mode and MS-DOS compatibility mode. The mode of 
operation is selected by CR0.NE[bit 5]. See Chapter 2, “System Architecture Overview,” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume  3A, for more information about the NE flag.8-32 Vol. 1PROGRAMMING WITH THE X87 FPU
8.7.1 Native Mode
The native mode for handling floating-point exceptions is selected by setting CR0.NE[bit 5] to 1. In this mode, if the 
x87 FPU detects an exception condition while executing a floating-point instruction and the exception is unmasked 
(the mask bit for the exception is cleared), the x87 FPU se ts the flag for the exception and the ES flag in the x87 
FPU status word. It then invokes the software exception handler through the floating-point-error exception (#MF, 
exception vector 16), immediately before execution of any of the following instructions in the processor’s instruc-
tion stream:
•The next floating-point instruction, unless it is one of  the non-waiting instructions (FNINIT, FNCLEX, FNSTSW, 
FNSTCW, FNSTENV, and FNSAVE). 
•The next WAIT/FWAIT instruction.
•The next MMX instruction.
If the next floating-point instruction in the instruction st ream is a non-waiting instruct ion, the x87 FPU executes the 
instruction without invoking the software exception handler.
8.7.2 MS-DOS* Comp atibility Sub-mode
If CR0.NE[bit 5] is 0, the MS-DOS compatibility mode for handling floating-point exceptions is selected. In this 
mode, the software exception handler for floating-point exceptions is invoked externally using the processor’s 
FERR#, INTR, and IGNNE# pins. This method of reporting fl oating-point errors and invoking an exception handler 
is provided to support the floating-point exception hand ling mechanism used in PC systems that are running the 
MS-DOS or Windows* 95 operating system.
Using FERR# and IGNNE# to handle floating-point exceptio n is deprecated by modern operating systems, this 
approach also limits newer processors to operate with one logical processor active.
The MS-DOS compatibility mode is typically used as fo llows to invoke the floating-point exception handler:
1. If the x87 FPU detects an unmasked floating-point exceptio n, it sets the flag for the exception and the ES flag 
in the x87 FPU status word.
2. If the IGNNE# pin is deasserted, the x87 FPU then asse rts the FERR# pin either immediately, or else delayed 
(deferred) until just before the execution of the next waiting floating-point instruction or MMX instruction. 
Whether the FERR# pin is asserted immediately or delaye d depends on the type of processor, the instruction, 
and the type of exception.
3. If a preceding floating-point instruction has set the exception flag for an unmasked x87 FPU exception, the 
processor freezes just before executing the next WAIT instruction, waiting floating-point instruction, or MMX 
instruction. Whether the FERR# pin was asserted at the preceding floating-point instruction or is just now being 
asserted, the freezing of the processor assures that th e x87 FPU exception handler will be invoked before the 
new floating-point (or MMX) instruction gets executed.
4. The FERR# pin is connected through external hardwa re to IRQ13 of a cascaded, programmable interrupt

4. The FERR# pin is connected through external hardwa re to IRQ13 of a cascaded, programmable interrupt 
controller (PIC). When the FERR# pin is asserted, th e PIC is programmed to generate an interrupt 75H.
5. The PIC asserts the INTR pin on the processor to signal the interrupt 75H.6. The BIOS for the PC system handles the interrupt 75 H by branching to the inte rrupt 02H (NMI) interrupt 
handler.
7. The interrupt 02H handler determines if the interrupt is  the result of an NMI interrupt or a floating-point 
8. If a floating-point exception is detected, the interrupt  02H handler branches to the floating-point exception 
handler.
If the IGNNE# pin is asserted, the processor ignores floating -point error conditions. This pin is provided to inhibit 
floating-point exceptions from being generated while the fl oating-point exception handler is servicing a previously 
signaled floating-point exception.
Appendix D, “Guidelines for Writing SIMD Floating-Point Exception Handlers,” describes the MS-DOS compatibility 
mode in much greater detail. This mode is somewhat more complicated in the Intel486 and Pentium processor 
implementations, as described in Appendix D.Vol. 1 8-33PROGRAMMING WITH THE X87 FPU
8.7.3 Handling x87 FPU Exceptions in Software
Section 4.9.3, “Typical Actions of a Floating-Point Except ion Handler,” shows actions that may be carried out by a 
floating-point exception handler. The state of the x87 FPU can be saved with  the FSTENV/FNSTENV or 
FSAVE/FNSAVE instructions; see Section 8.1.10, “Sav ing the x87 FPU State wi th FSTENV/FNSTENV and 
FSAVE/FNSAVE.” 
If the faulting floating-point instruction is followed by on e or more non-floating-point instructions, it may not be 
useful to re-execute the faulting instruction. See Sectio n 8.6, “x87 FPU Exception Synchronization,” for more infor-
mation on synchronizing floating-point exceptions.
In cases where the handler needs to restart program execution with the faulting instruction, the IRET instruction 
cannot be used directly. The reason for this is that beca use the exception is not generated until the next floating-
point or WAIT/FWAIT instruction following the faulting floa ting-point instruction, the return instruction pointer on 
the stack may not point to the faulting instruction. To restart program execution at the faulting instruction, the 
exception handler must obtain a pointer to the instruction from the saved x87 FPU state information, load it into 
the return instruction pointer location on the stack, and then execute the IRET instruction.8-34 Vol. 1PROGRAMMING WITH THE X87 FPUVol. 1 9-1CHAPTER 9
The Intel MMX technology was introduced into the IA- 32 architecture in the Pentium II processor family and 
Pentium  processor with MMX technology. The extensions introd uced in MMX technology support a single-instruc-
tion, multiple-data (SIMD) execution model that is design ed to accelerate the performance of advanced media and 
communications applications.
This chapter describes MMX technology.
9.1 OVERVIEW OF MMX TECHNOLOGY
MMX technology defines a simple and flexible SIMD execut ion model to handle 64-bit packed integer data. This 
model adds the following features to the IA-32 architectu re, while maintaining backwards compatibility with all IA-
32 applications and operating-system code:
•Eight new 64-bit data registers, called MMX registers.
•Three new packed data types:
— 64-bit packed byte integers (signed and unsigned).
— 64-bit packed word integers (signed and unsigned).
— 64-bit packed doubleword integers (signed and unsigned).
•Instructions that support the new data types and to handle MMX state management.
•Extensions to the CPUID instruction.
MMX technology is accessible from all the IA32-architectu re execution modes (protected mode, real address mode, 
and virtual 8086 mode). It does not add any new modes to the architecture.
The following sections of this chapter describe MMX technology’s programming en vironment, including MMX 
register set, data types, and instruction set. Additional instructions that operate on MMX registers have been added 
to the IA-32 architecture by the SSE/SSE2 extensions.
For more information, see:
•Section 10.4.4, “Intel® SSE 64-Bit SIMD Integer Instructions,” describes MMX instructions added to the IA-32 
architecture with the SSE extensions.
•Section 11.4.2, “Intel® SSE2 64-Bit and 128-Bit SIMD In teger Instructions,” describes MMX instructions added 
to the IA-32 architecture with SSE2 extensions.
•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, gives detailed 
descriptions of MMX instructions.
•Chapter 13, “Intel® MMX™ Technology System Programming,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3B, describes the ma nner in which MMX technology is integrated into the 
IA-32 system programming model.
9.2 THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT 
Figure 9-1 shows the execution environment for MMX technology. All MMX instructions operate on MMX registers, the general-purpose registers, and/or memory as follows: 
•MMX registers —  These eight registers (see Figure 9-1) are used to perform operations on 64-bit packed 
integer data. They are named MM0 through MM7.9-2 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
•General-purpose  registers —  The eight general-purpose registers (see Figure 3-5) are used with existing IA-
32 addressing modes to address operands in memory. (MMX registers cannot be used to address memory). 
General-purpose registers are also used to hold operan ds for some MMX technology operations. They are EAX, 
EBX, ECX, EDX, EBP, ESI, EDI, and ESP.
9.2.1 MMX Technology in 64-Bi t Mode and Compatibility Mode
In compatibility mode and 64-bit mode, MMX instructions function like they do in pr otected mode. Memory oper-
ands are specified using the ModR/M, SI B encoding described in Section 3.7.5.
9.2.2 MMX Registers
The MMX register set consists of eight 64-bit registers (s ee Figure 9-2), that are used to perform calculations on 
the MMX packed integer data types. Values in MMX register s have the same format as a 64-bit quantity in memory. 
The MMX registers have two data access modes: 64-bit access mode and 32-bit access mode. The 64-bit access 
mode is used for:
•64-bit memory accesses.
•64-bit transfers between MMX registers.
•All pack, logical, and arithmetic instructions.
•Some unpack instructions.
The 32-bit access mode is used for:
•32-bit memory accesses.
•32-bit transfer between general-purpose registers and MMX registers.
•Some unpack instructions.Figure 9-1.  MMX Technology Execution Environment0232 -1
Eight 32-BitAddress Space
General-PurposeEight 64-BitMMX Registers
RegistersVol. 1 9-3PROGRAMMING WITH INTE L® MMX™ TECHNOLOGY
Although MMX registers are defined in the IA-32 architecture as separate registers, they are aliased to the registers 
in the FPU data register stack (R0 through R7). 
See also Section 9.5, “Compatibi lity with x87 FPU Architecture.”
9.2.3 MMX Data Types
MMX technology introduced the follo wing 64-bit data types to the IA-32 architecture (see Figure 9-3):
•64-bit packed byte integers — eight packed bytes.
•64-bit packed word integers — four packed words.
•64-bit packed doubleword inte gers — two packed doublewords.
MMX instructions move 64-bit packed data types (packed bytes, packed words, or packed doublewords) and the 
quadword data type between MMX registers and memory or between MMX registers in  64-bit blocks. However, 
when performing arithmetic or logical operations on the pa cked data types, MMX instructions operate in parallel on 
the individual bytes, words, or doublewords contained in  MMX registers; see Section 9.2.5, “Single Instruction, 
Multiple Data (SIMD) Execution Model.”
9.2.4 Memory Data Formats
When stored in memory: bytes, words, and doublewords in the packed data types are stored in consecutive 
addresses. The least significant byte, word, or doubleword is stored at the lowest address and the most significant 
byte, word, or doubleword is stored at the high address. The ordering of bytes, words, or doublewords in memory 
is always little endian. That is, the bytes with the low addresses are less significant than the bytes with high 
addresses.Figure 9-2.  MMX Register Set
Figure 9-3.  Data Types Intr oduced with the MMX TechnologyMM7
MM6
MM5
MM4
MM3
MM2MM1MM063 0
0 630 639-4 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
9.2.5 Single Instruction, Multiple Data (SIMD) Execution Model
MMX technology uses the single instruction, multiple data  (SIMD) technique for performing arithmetic and logical 
operations on bytes, words, or doublewords packed into MMX registers (see Figure 9-4). For example, the PADDSW 
instruction adds 4 signed word integers from one source operand to 4 signed word integers in a second source 
operand and stores 4 word integer results in a destinat ion operand. This SIMD technique speeds up software

MM6
MM5
MM4
MM3
operand and stores 4 word integer results in a destinat ion operand. This SIMD technique speeds up software 
performance by allowing the same operation to be carried  out on multiple data elements in parallel. MMX tech-
nology supports parallel operations on byte, word, and do ubleword data elements when contained in MMX regis-
ters.
The SIMD execution model supported in the MMX technolo gy directly addresses the needs of modern media, 
communications, and graphics applications, which often use sophisticated algorithms that perform the same oper-
ations on a large number of small data types (bytes, word s, and doublewords). For example, most audio data is 
represented in 16-bit (word) quantities. The MMX instruct ions can operate on 4 words simultaneously with one 
instruction. Video and graphics information is commonly represented as palletized 8-bit (byte) quantities. In 
Figure 9-4, one MMX instruction oper ates on 8 bytes simultaneously.
9.3 SATURATION AND WRAPAROUND MODES
When performing integer arithmetic, an operation may result  in an out-of-range condition, where the true result 
cannot be represented in the destinatio n format. For example, when performing arithmetic on signed word inte-
gers, positive overflow can occur when the true signed result is larger than 16 bits.
The MMX technology provides three ways of handling out-of-range conditions:
•Wraparound arithmetic —  With wraparound arithmetic, a true out-of-range result is truncated (that is, the 
carry or overflow bit is ignored and only the least signific ant bits of the result are returned to the destination). 
Wraparound arithmetic is suitable for applications that  control the range of operands to prevent out-of-range 
results. If the range of operands is not controlled, howe ver, wraparound arithmetic can lead to large errors. For 
example, adding two large signed numbers can cause positive overflow and produce a negative result.
•Signed saturation arithmetic —  With signed saturation arithmetic, out-of-range results are limited to the 
representable range of signed integers for the integer si ze being operated on (see Table 9-1). For example, if 
positive overflow occurs when operating on signed word  integers, the result is “saturated” to 7FFFH, which is 
the largest positive integer that can be represented in 16 bits; if negative overflow occurs, the result is 
saturated to 8000H.
•Unsigned saturation arithmetic —  With unsigned saturation arithmetic, out-of-range results are limited to 
the representable range of unsigned integers for the in teger size. So, positive overflow when operating on 
unsigned byte integers results in FFH being returned and negative overflow results in 00H being returned.
.Figure 9-4.  SIMD Execution ModelX3 X2 X1 X0
Y3 Y2 Y1 Y0
X3 OP Y3 X2 OP Y2 X1 OP Y1 X0 OP Y0OP OP OP OPSource 1
Source 2
DestinationVol. 1 9-5PROGRAMMING WITH INTE L® MMX™ TECHNOLOGY
Saturation arithmetic provides an answer for many overflow situations. For example, in color calculations, satura-
tion causes a color to remain pure black or pure white with out allowing inversion. It also prevents wraparound arti-
facts from entering into computations when range checking of source operands it not used.
MMX instructions do not indicate overflow or underflow o ccurrence by generating exceptions or setting flags in the 
9.4 MMX INSTRUCTIONS
The MMX instruction set consists of 47 instruct ions, grouped into the following categories:
•Data transfer
•Arithmetic
•Comparison
•Conversion
•Unpacking
•Logical
•Shift
•Empty MMX state instruction (EMMS)
Table 9-2 gives a summary of the instructions in the MMX instruction set. The following sections give a brief over-
view of the instructions within each group.
NOTES
The MMX instructions described in this chapter are those instructions that are available in an IA-32 
processor when CPUID.01H:EDX.MMX[bit 23] = 1. 
Section 10.4.4, “Intel® SSE 64-Bit SIMD Integer Instructions,” and Section 11.4.2, “Intel® SSE2 
64-Bit and 128-Bit SIMD Integer Instructions,” list additional instructions included with the Intel 
SSE/SSE2 extensions that operate on MMX registers but are not considered part of the MMX 
instruction set.Table 9-1.  Data Range Limits for Saturation
Data Type Lower Limit Upper Limit
Hexadecimal Decimal Hexadecimal Decimal
Signed Byte     80H     -128     7FH      127
Signed Word 8000H -32,768 7FFFH 32,767
Unsigned Byte     00H           0     FFH      255
Unsigned Word 0000H           0 FFFFH 65,5359-6 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
9.4.1 Data Transfer Instructions
The MOVD (Move 32 Bits) instruction transfers 32 bits of packed data from memory to  an MMX register and vice 
versa; or from a general-purpose register to an MMX register and vice versa.
The MOVQ (Move 64 Bits) instruction transfers 64 bits of packed data from memory to an MMX register and vice 
versa; or transfers data between MMX registers.
9.4.2 Arithmetic Instructions
The arithmetic instructions perform addition, subtraction,  multiplication, and multiply/add operations on packed 
data types.
The PADDB/PADDW/PADDD (add packed integers) instruct ions and the PSUBB/PSUBW/ PSUBD (subtract packed 
integers) instructions add or subtract the corresponding si gned or unsigned data elements of the source and desti-Table 9-2.  MMX Instruction Set Summary
Category Wraparound Signed Saturation Unsigned Saturation
Arithmetic Addition
Subtraction
Multiplication
Multiply and AddPADDB, PADDW, PADDD
PSUBB, PSUB W, PSUBD
PMULL, PMULH
PMADDPADDSB, PADDSW
PSUBSB, PSUBSWPADDUSB, PADDUSW
PSUBUSB, PSUBUSW
Comparison Compare for Equal
Compare for Greater 
ThanPCMPEQB, PCMPEQW, 
PCMPEQD
PCMPGTPB, PCMPGTPW, 
PCMPGTPD
Conversion Pack PACKSSWB,
PACKSSDWPACKUSWB
Unpack Unpack High
Unpack LowPUNPCKHBW, 
PUNPCKHWD, PUNPCKHDQ
PUNPCKLBW, 
PUNPCKLWD, PUNPCKLDQ
Packed Full Quadword
Logical And
And NotOr
Exclusive ORPAND
PANDNPOR
PXOR
Shift Shift Left Logical
Shift Right Logical
Shift Right ArithmeticPSLLW, PSLLD
PSRLW, PSRLD
PSRAW, PSRADPSLLQ
PSRLQ
Doubleword Transfers Quadword Transfers
Data Transfer Register to Register
Load from Memory
Store to MemoryMOVD
MOVD
MOVDMOVQ
MOVQ
MOVQ
Empty MMX State EMMSVol. 1 9-7PROGRAMMING WITH INTE L® MMX™ TECHNOLOGY
nation operands in wraparound mode. These instructions  operate on packed byte, word, and doubleword data 
types.
The PADDSB/PADDSW (add packed signed integers with signed saturation) instructions and the PSUBSB/PSUBSW 
(subtract packed signed integers with signed saturation) instructions add or subtract the corresponding signed data elements of the source and destination operands and sa turate the result to the limits of the signed data-type 
range. These instructions operate on  packed byte and word data types.
The PADDUSB/PADDUSW (add packed unsigned integers with unsigned saturation) instructions and the 
PSUBUSB/PSUBUSW (subtract packed unsigned integers with unsigned saturation) instructions add or subtract the 
corresponding unsigned data elements of the source and de stination operands and saturate the result to the limits 
of the unsigned data-type range. These instructions  operate on packed byte and word data types.
The PMULHW (multiply packed signed integers and store hi gh result) and PMULLW (multiply packed signed integers 
and store low result) instructions perform a signed multip ly of the corresponding words of the source and destina-
tion operands and write the high-order or low-order 16 bits of each of the results, respectively, to the destination 
operand.
The PMADDWD (multiply and add packed integers) instructio n computes the products of the corresponding signed 
words of the source and destination operands. The four intermediate 32-bit doubleword products are summed in 
pairs (high-order pair and low-order pair) to produce two 32-bit doubleword results. 
9.4.3 Comparison Instructions
The PCMPEQB/PCMPEQW/PCMPEQD (compare packed  data for equal) instructions and the 
PCMPGTB/PCMPGTW/PCMPGTD (compare packed signed intege rs for greater than) instructions compare the corre-
sponding signed data elements (bytes, words, or doublewo rds) in the source and destination operands for equal to 
or greater than, respectively. 
These instructions generate a mask of ones or zeros wh ich are written to the destination operand. Logical opera-
tions can use the mask to select packed elements. This ca n be used to implement a packed conditional move oper-
ation without a branch or a set of branch instructio ns. No flags in the EFLAGS register are affected. 
9.4.4 Conversion Instructions
The PACKSSWB (pack words into bytes with signed satura tion) and PACKSSDW (pack doublewords into words with 
signed saturation) instructions convert signed words into signed bytes and signed doublewords into signed words, 
respectively, using signed saturation.
PACKUSWB (pack words into bytes with unsigned saturati on) converts signed words into unsigned bytes, using 
unsigned saturation.
9.4.5 Unpack Instructions
The PUNPCKHBW/PUNPCKHWD/ PUNPCKHDQ (unpack high-order data elements) instructions and the

The PUNPCKHBW/PUNPCKHWD/ PUNPCKHDQ (unpack high-order data elements) instructions and the 
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ (unpack low-order data  elements) instructions unpack bytes, words, or 
doublewords from the high- or low-order data elements of the source and destination operands and interleave 
them in the destination operand. By placing all 0s in the source operand, these instructions can be used to convert 
byte integers to word integers, word integers to double word integers, or doubleword integers to quadword inte-
gers. 
9.4.6 Logical Instructions
PAND (bitwise logical AND), PANDN (bitwise logical AND NO T), POR (bitwise logical OR), and PXOR (bitwise logical 
exclusive OR) perform bitwise logical operations on the quadword source and destination operands.9-8 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
9.4.7 Shift Instructions
The logical shift left, logical shift right and arithmetic sh ift right instructions shift each element by a specified 
number of bit positions.
The PSLLW/PSLLD/PSLLQ (shift packed da ta left logical) instructions and the PSRLW/PSRLD/PSRLQ (shift packed 
data right logical) instructions perform a logical left or ri ght shift of the data elements and fill the empty high or low 
order bit positions with zeros. These instructions op erate on packed words, doublewords, and quadwords.
The PSRAW/PSRAD (shift packed data right arithmetic) inst ructions perform an arithmetic right shift, copying the 
sign bit for each data element into empty bit positions on the upper end of each data element. This instruction operates on packed words and doublewords. 
9.4.8 EMMS Instruction
The EMMS instruction empties the MMX state by setting th e tags in x87 FPU tag word to 11B, indicating empty 
registers. This instruction must be executed at the end of an MMX routine before calling other routines that can 
execute floating-point instructions. See Section 9.6.3, “U sing the EMMS Instruction,” for more information on the 
use of this instruction.
9.5 COMPATIBILITY WITH X87 FPU ARCHITECTURE
The MMX state is aliased to the x87 FPU state. No new states or modes have been added to IA-32 architecture to support the MMX technology. The same floating-point inst ructions that save and restore the x87 FPU state also 
handle the MMX state (for example, during context switching).
MMX technology uses the same interface techniques betw een the x87 FPU and the operating system (primarily for 
task switching purposes). For more details, see Chapter 13, “Intel® MMX™ Te chnology System Programming,” in 
the Intel
9.5.1 MMX Instructions and the x87 FPU Tag Word
After each MMX instruction, the entire x87 FPU tag word is set to valid (00B). The EMMS instruction (empty MMX 
state) sets the entire x87 FPU tag word to empty (11B). 
Chapter 13, “Intel® MMX™ Technology System Programming,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3A, provides additional inform ation about the effects of x87 FPU and MMX instructions 
on the x87 FPU tag word. For a de scription of the tag word, see Section 8.1.7, “x87 FPU Tag Word.”
9.6 WRITING APPLICAT IONS WITH MMX CODE
The following sections give guidelines for writ ing application code that uses MMX technology.
9.6.1 Checking for MMX Technology Support
Before an application attempts to use the MMX technology, it  should check that it is present on the processor. Check 
by following these steps:
1. Check that the processor supports th e CPUID instruction by attempting to execute the CPUID instruction. If the 
processor does not support the CPUID instruction, th is will generate an invalid-opcode exception (#UD).
2. Check that the processor supports the MMX technology 
(if CPUID.01H:EDX.MMX[bit 23] = 1).
3. Check that emulation of the x87 FPU is disabled (if CR0.EM[bit 2] = 0).
If the processor attempts to execute an unsupported MMX instruction or attempts to execute an MMX instruction 
with CR0.EM[bit 2] set, this generate s an invalid-opcode exception (#UD).Vol. 1 9-9PROGRAMMING WITH INTE L® MMX™ TECHNOLOGY
Example 9-1 illustrates how to use the CPUID instruction to detect the MMX technolo gy. This example does not 
represent the entire CPUID sequence, but shows th e portion used for detection of MMX technology.
Example 9-1.  Partial Routin e for Detecting MMX Technology with the CPUID Instruction
... ; identify existence of CPUID instruction
... ; identify Intel processormov EAX, 1 ; request for feature flagsCPUID ; 0FH, 0A2H CPUID instructiontest EDX, 00800000H ; Is IA MMX technology bit (Bit 23 of EDX) set?jnz ; MMX_Technology_Found
9.6.2 Transitions Between x87 FPU and MMX Code
Applications can contain both x87 FPU floating-point an d MMX instructions. However, because the MMX registers 
are aliased to the x87 FPU register stack, care must be  taken when making transitions between x87 FPU instruc-
tions and MMX instructions to prevent incoherent or unexpected results.
When an MMX instruction (other than the EMMS instructio n) is executed, the processor changes the x87 FPU state 
•The TOS (top of stack) value of the x87 FPU status word is set to 0.
•The entire x87 FPU tag word is set to the valid state (00B in all tag fields). 
•When an MMX instruction writes to an MMX register, it writes ones (11B) to the exponent part of the corre-
sponding floating-point regi ster (bits 64 through 79).
The net result of these actions is that any x87 FPU state pr ior to the execution of the MMX instruction is essentially 
lost.
When an x87 FPU instruction is executed, the processor assumes that the current state of the x87 FPU register 
stack and control registers is valid and executes the instruction without any preparatory modifications to the x87 
FPU state.
If the application contains both x87 FPU floating-point and MMX instructions, the following guidelines are recom-
mended:
•When transitioning between x87 FPU and MMX code, save the state of any x87 FPU data or control registers 
that need to be preserved for future use. The FSAVE and FXSAVE instructions save the entire x87 FPU state.
•When transitioning between MMX an d x87 FPU code, do the following:
— Save any data in the MMX registers that needs to be preserved for future use. FSAVE and FXSAVE also save 
the state of MMX registers.
— Execute the EMMS instruction to clear the MMX state from the x87 data and control registers.
The following sections describe the use of the EMMS instru ction and give additional guidelines for mixing x87 FPU 
and MMX code.
9.6.3 Using the EMMS Instruction
As described in Section 9.6.2, “Transitions Between x 87 FPU and MMX Code,” when an MMX instruction executes, 
the x87 FPU tag word is marked valid (00B). In this stat e, the execution of subsequent x87 FPU instructions may 
produce unexpected x87 FPU floating-point exceptions and/ or incorrect results because the x87 FPU register stack 
appears to contain valid data. The EMMS instruction is pr ovided to prevent this problem by marking the x87 FPU 
tag word as empty.
The EMMS instruction should be used in each of the following cases: 
•When an application using the x87 FPU instructions calls an MMX technology library/DLL (use the EMMS 
instruction at the end of the MMX code).9-10 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
•When an application using MMX instructions calls a x87 FPU floating-point library/DLL (use the EMMS 
instruction before calling the x87 FPU code).
•When a switch is made between MMX code in a task or thread and other tasks or threads in cooperative 
operating systems, unless it is certain that more MMX instructions will be executed before any x87 FPU code.
EMMS is not required when mixing MMX technology in structions with Intel SSE/SSE2/SSE3 instructions; see 
Section 11.6.7, “Interaction of Intel® SSE and SSE2 Instructions with x87 FPU and MMX Instructions.”
9.6.4 Mixing MMX and x87 FPU Instructions
An application can contain both x87 FPU floating-point and MMX instructions. However, frequent transitions 
between MMX and x87 FPU instructions are not recommen ded, because they can degrade performance in some 
processor implementations. When mixing MMX code with x87 FPU code, follow these guidelines:
•Keep the code in separate modules, procedures, or routines.
•Do not rely on register contents across transitions between x87 FPU and MMX code modules.
•When transitioning between MMX code and x87 FPU code, sa ve the MMX register state (if it will be needed in 
the future) and execute an EMMS in struction to empty the MMX state.
•When transitioning between x87 FPU code and MMX code, sa ve the x87 FPU state if it will be needed in the 
future.
9.6.5 Interfacing with MMX Code
MMX technology enables direct access to all the MMX regist ers. This means that all existing interface conventions 
that apply to the use of the processor’s general-purpose registers (EAX, EBX, etc.) also apply to the use of MMX 
An efficient interface to MMX routines might pass parame ters and return values through the MMX registers or

future.
An efficient interface to MMX routines might pass parame ters and return values through the MMX registers or 
through a combination of memory locations (via the stack)  and MMX registers. Do not use the EMMS instruction or 
mix MMX and x87 FPU code when using to the MMX registers to pass parameters.
If a high-level language that does not support the MMX data types directly is used, the MMX data types can be 
defined as a 64-bit structure containing packed data types.
When implementing MMX instructions in high-level languages, other approaches can be taken, such as: 
•Passing parameters to an MMX routine by passing a pointer to a structure via the stack.
•Returning a value from a function by returning a pointer to a structure.
9.6.6 Using MMX Code in a Multitas king Operating Sy stem Environment
An application needs to identify the nature of the multitas king operating system on which it runs. Each task retains 
its own state which must be saved when a task switch occurs. The processor state (context) consists of the 
general-purpose registers and the floating-point and MMX registers.
Operating systems can be classified into two types:
•Cooperative multitasking operating system.
•Preemptive multitasking operating system.
Cooperative multitasking operating systems do not save the FPU or MMX state when performing a context switch. 
Therefore, the application needs to save the relevant stat e before relinquishing direct or indirect control to the 
Preemptive multitasking operating systems are responsibl e for saving and restoring the FPU and MMX state when 
performing a context switch. Therefore, the application does not have to save or restore the FPU and MMX state.Vol. 1 9-11PROGRAMMING WITH INTE L® MMX™ TECHNOLOGY
9.6.7 Exception Handling in MMX Code
MMX instructions generate the same type of memory-acce ss exceptions as other IA-32 instructions (page fault, 
segment not present, and limit violations). Existing exceptio n handlers do not have to be modified to handle these 
types of exceptions for MMX code.
Unless there is a pending floating-point exception, MMX instructions do not generate numeric exceptions. There-
fore, there is no need to modify existing exception ha ndlers or add new ones to handle numeric exceptions. 
If a floating-point exception is pending, the subseque nt MMX instruction generates a numeric error exception 
(interrupt 16 and/or assertion of the FERR# pin). The MMX instruction resumes execution upon return from the 
exception handler.
9.6.8 Register Mapping
MMX registers and their tags are mapped to physical loca tions of the floating-point registers and their tags. 
Register aliasing and mapping is described in more detail in Chapter 13, “Intel® MMX™ Technology System 
Programming,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
9.6.9 Effect of Instruction Prefixes on MMX Instructions
Table 9-3 describes the effect of instruction prefixes on  MMX instructions. Unpredictable behavior can range from 
being treated as a reserved operation on one generation of IA-32 processors to generating an invalid opcode 
exception on another generation of processors.
See “Instruction Prefixes” in Chapter 2, “Instruction Format,” of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2A, for a de scription of the instruction prefixes.Table 9-3.  Effect of Pref ixes on MMX Instructions 
Prefix Type Effect on MMX Instructions 
Address Size Prefix (67H) Affects in structions with a memory operand.
Reserved for instructions without a memory operand and may result in 
unpredictable behavior.
Operand Size (66H) Reserved and may result in unpredictable behavior.Segment Override (2EH, 36H, 3EH, 26H, 64H, 
65H)Affects instructions with a memory operand.
Repeat Prefix (F3H) Reserved and may result in unpredictable behavior.
Repeat NE Prefix(F2H) Reserved and may result in unpredictable behavior.Lock Prefix (F0H) Reserved; genera tes invalid opcode exception (#UD).
Branch Hint Prefixes (2EH and 3EH) Reserved and may result in unpredictable behavior.9-12 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGYVol. 1 10-1CHAPTER 10
PROGRAMMING WITH INTEL®
STREAMING SIMD EXTENSIONS (INTEL® SSE)
The Intel® Streaming SIMD Extensions (Intel® SSE) were introduced into the IA-32 architecture in the Pentium III 
processor family. These extensions enhance the perfor mance of IA-32 processors for advanced 2-D and 3-D 
graphics, motion video, image processing, speech recognitio n, audio synthesis, telephon y, and video conferencing. 
This chapter describes SSE. Chapter 11, “Programming wi th Intel® Streaming SIMD Extensions 2 (Intel® SSE2),” 
provides information to assist in writing application prog rams that use Intel SSE2. Chapter 12, “Programming with 
Intel® SSE3, SSSE3, Intel® SSE4, and Intel® AES- NI,” provides this information for Intel SSE3.
10.1 OVERVIEW OF INTEL® SSE
Intel MMX technology introduced single-instruction multip le-data (SIMD) capability into the IA-32 architecture, 
with the 64-bit MMX registers, 64-bit packed integer data ty pes, and instructions that allowed SIMD operations to 
be performed on packed integers. Intel SSE expanded the SIMD execution model by adding facilities for handling 
packed and scalar single precision floating-point values contained in 128-bit registers.
If CPUID.01H:EDX.SSE[bit 25] = 1, Intel SSE is available.
Intel SSE adds the following features to the IA-32 archit ecture, while maintaining back ward compatibility with all 
existing IA-32 processors, applications, and operating systems:
•Eight 128-bit data registers (called XMM registers) in no n-64-bit modes; 16 XMM registers are available in 64-
bit mode.
•The 32-bit MXCSR register, which provides control and st atus bits for operations performed on XMM registers.
•The 128-bit packed single precision floating-point data type (four IEEE single precision floating-point values 
packed into a double quadword).
•Instructions that perform SIMD operations on single precision floating-point values and that extend SIMD 
operations that can be performed on integers:
— 128-bit Packed and scalar single precision floating-point instructions that operate on data located in MMX 
— 64-bit SIMD integer instructions that support addition al operations on packed integer operands located in 
MMX registers.
•Instructions that save and restore the state of the MXCSR register.
•Instructions that support explicit pr efetching of data, control of the cacheability of data, and control the 
ordering of store operations.
•Extensions to the CPUID instruction. 
These features extend the IA-32 architecture’s SIMD programming model in four important ways: 
•The ability to perform SIMD operations on four packed  single precision floating-point values enhances the 
performance of IA-32 processors for advanced media and communications applications that use computation-
intensive algorithms to perform repetitive operations  on large arrays of simple, native data elements. 
•The ability to perform SIMD single precision floating -point operations in XMM registers and SIMD integer 
operations in MMX registers provides greater flexibility and throughput for executing applications that operate 
on large arrays of floating-point and integer data.
•Cache control instructions provide the ability to stream data in and out of XMM registers without polluting the 
caches and the ability to prefetch data to selected cach e levels before it is actually used. Applications that 
require regular access to large amounts of data benefit from these prefetching and st reaming store capabilities. 
•The SFENCE (store fence) instruction provides greater co ntrol over the ordering of store operations when using 
weakly-ordered memory types.10-2 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
Intel SSE is fully compatible with all software written fo r IA-32 processors. All existing software continues to run 
correctly, without modification, on processors that incorp orate Intel SSE. Enhancements to CPUID permit detection 
of Intel SSE. Intel SSE is accessible from all IA-32 ex ecution modes: protected mode, real address mode, and 
virtual-8086 mode.
The following sections of this chapter describe the prog ramming environment for Intel SSE, including: XMM regis-
ters, the packed single precision floating-point data type, and Intel SSE instructions. For additional information, 
see:
•Section 11.6, “Writing Applicatio ns with Intel® SSE and SSE2.”
•Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,” describes the exceptions that can be generated with 
Intel SSE/SSE2/SSE3 instructions.
•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, provides a 
detailed description of these instructions.
•Chapter 14, “System Programming for Instruction Set Exte nsions and Processor Extended States,” in the Intel® 
64 and IA-32 Architectures Software Developer’s Manual,  Volume 3A, gives guidelines for integrating these 
extensions into an operating-system environment.

see:
10.2 INTEL® SSE PROGRAMMING ENVIRONMENT
Figure 10-1 shows the execution environment for Intel SSE.  All Intel SSE instructions operate on the XMM regis-
ters, MMX registers, and/or memory as follows: 
•XMM registers —  These eight registers (see Figure 10-2 and Sect ion 10.2.2, “XMM Registers”) are used to 
operate on packed or scalar single precision floating-poi nt data. Scalar operations are operations performed on 
individual (unpacked) single precision floating-point va lues stored in the low doub leword of an XMM register. 
XMM registers are referenced by  the names XMM0 through XMM7.
•MXCSR register —  This 32-bit register (see Figure 10-3 and Section 10.2.3, “MXCSR Control and Status 
Register”) provides status and control bits used in SIMD floating-point operations.
•MMX registers —  These eight registers (see Figure 9-2) are used to perform operations on 64-bit packed 
integer data. They are also used to hold operands for some operations performed between the MMX and XMM 
registers. MMX registers are referenced by the names MM0 through MM7.
•General-purpose registers —  The eight general-purpose registers (see Figure 3-5) are used along with the 
existing IA-32 addressing modes to address operands in memory. (MMX and XMM registers cannot be used to Figure 10-1.  Intel® SSE Execution Environment0232 -1
Eight 32-Bit
32 Bits EFLAGS RegisterAddress Space
General-PurposeEight 64-BitMMX RegistersEight 128-BitXMM Registers
32 Bits MXCSR Register
RegistersVol. 1 10-3PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
address memory). The general-purpose registers are also used to hold operands for some SSE instructions and 
are referenced as EAX, EBX, ECX,  EDX, EBP, ESI, EDI, and ESP.
•EFLAGS register —  This 32-bit register (see Figure 3-8) is used to record result of some compare operations.
10.2.1 Intel® SSE in 64-Bit Mode and Compatibility Mode
In compatibility mode, Intel SSE functions like it does in  protected mode. In 64-bit mode, eight additional XMM 
registers are accessible. Registers XM M8-XMM15 are accessed by using REX prefixes. Memory operands are spec-
ified using the ModR/M, SIB encodi ng described in Section 3.7.5.
Some Intel SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access 
64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.
10.2.2 XMM Registers
Eight 128-bit XMM data registers were introduced into the IA-32 architecture  with Intel SSE (see Figure 10-2). 
These registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently 
from the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased to any other 
of the processor’s registers). 
Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands. 
SSE2 extensions expand the functions of the XMM regist ers to operand on packed or scalar double precision 
floating-point operands and packed integer operands; s ee Section 11.2, “Intel® SSE2 Programming Environment,” 
and Section 12.1, “Programming Environment and Data types.”
XMM registers can only be used to perform calculations on data; they cannot be used to address memory. 
Addressing memory is a ccomplished by using the general-purpose registers.
Data can be loaded into XMM registers or written from th e registers to memory in 32-bit, 64-bit, and 128-bit incre-
ments. When storing the entire contents of an XMM register in memory (128-bit store), the data is stored in 16 
consecutive bytes, with the low-order byte of the re gister being stored in the first byte in memory.
10.2.3 MXCSR Control and Status Register
The 32-bit MXCSR register (see Figure 10-3) contains cont rol and status information for Intel SSE, SSE2, and SSE3 
SIMD floating-point operations. This register contains: 
•Flag and mask bits for SIMD  floating-point exceptions.
•Rounding control field for SIMD  floating-point operations.Figure 10-2.  XMM RegistersXMM7
XMM6
XMM5
XMM4
XMM3
XMM2XMM1XMM0127 010-4 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
•Flush-to-zero flag that provides a means of controlling underflow conditions on SIMD floating-point operations.
•Denormals-are-zeros flag that controls how SIMD floating-point instructions handle denormal source operands.
The contents of this register can be loaded from memo ry with the LDMXCSR and FXRS TOR instructions and stored 
in memory with STMXCSR and FXSAVE.
Bits 16 through 31 of the MXCSR register are reserved an d are cleared on a power-up or reset of the processor; 
attempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCS R instructions, will result 
in a general-protection exception (#GP) being generated.
10.2.3.1  SIMD Floating-Point Mask and Flag Bits
Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They 
are “sticky” flags. That is, after a flag is set, it remain s set until explicitly cleared. To clear these flags, use the 
LDMXCSR or the FXRSTOR instruct ion to write zeroes to them.
Bits 7 through 12 provide individual mask bits for the SIMD  floating-point exceptions. An exception type is masked 
if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up 
or reset. This causes all SIMD floating-point exceptions to be initially masked.
If LDMXCSR or FXRSTOR clears a mask bit and sets the co rresponding exception flag bit, a SIMD floating-point 
exception will not be generated as a result of this change. The unmasked exception will be generated only upon the 
execution of the next SSE/SSE2/SSE3 instruction that detects the unmasked exception condition. 
For more information about the use of the SIMD floating -point exception mask and flag bits, see Section 11.5, 
“Intel® SSE, SSE2, and SSE3 Exceptions,” and Section 12.8, “Intel® SSE3, SSSE3, And Intel® SSE4 Exceptions.”
10.2.3.2  SIMD Floating-Point Rounding Control Field
Bits 13 and 14 of the MXCSR register (the rounding control [R C] field) control how the results of SIMD floating-point 
instructions are rounded. See Section 4.8.4, “Rounding,” for a description of the function and encoding of the 
rounding control bits.
10.2.3.3  Flush-To-Zero
Bit 15 (FTZ) of the MXCSR register en ables the flush-to-zero mode, which controls the masked response to a SIMD 
floating-point underflow condition. When the underflo w exception is masked and the flush-to-zero mode is 
enabled, the processor performs the fo llowing operations when it detects a floating-point underflow condition.Figure 10-3.  MXCSR Control/Status Register 31 16
Overflow Mask
Divide-by-Zero MaskDenormal Operation MaskInvalid Operation MaskDenormals Are Zeros*Precision FlagUnderflow FlagUnderflow MaskFlush to Zero
Rounding Control15 1314 12 11 10 9 876543 210
Precision Mask
Overflow Flag
Divide-by-Zero FlagDenormal FlagInvalid Operation FlagF
TR
CP
MZ
EO
EU
EP
EI
MD
MZ
MO
MU
M ReservedD
EEID
A
Z
* The denormals-are-zeros flag was introduced in the Pentium 4 and Intel Xeon processor.ZVol. 1 10-5PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
•Returns a zero result with the sign of the true result.
•Sets the precision and underflow exception flags.
If the underflow exception is not masked, the flush-to-zero bit is ignored.
The flush-to-zero mode is not compatible with IEEE St andard 754. The IEEE-mandated masked response to under-
flow is to deliver the denormalized result (see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”). 
The flush-to-zero mode is provided primarily for performance reasons. At the cost of a slight precision loss, faster 
execution can be achieved for applications where underflows are common and rounding the underflow result to zero can be tolerated.
The flush-to-zero bit is cleared upon a power-up or re set of the processor, disabling the flush-to-zero mode.
10.2.3.4  Denormals-Are-Zeros
Bit 6 (DAZ) of the MXCSR register enables the denormals- are-zeros mode, which controls the processor’s response 
to a SIMD floating-point denormal operand condition. Wh en the denormals-are-zeros flag is set, the processor 
converts all denormal source operands to a zero with the sign of the original op erand before performing any 
computations on them. The processor does not set the de normal-operand exception fl ag (DE), regardless of the 
setting of the denormal-operand exception mask bit (DM); and it does not generate a denormal-operand exception 
if the exception is unmasked.
The denormals-are-zeros mode is not compatible with I EEE Standard 754 (see Sectio n 4.8.3.2, “Normalized and 
Denormalized Finite Numbers”). The denormals-are-zeros mode is provided to improve processor performance for 
applications such as streaming media processing, wher e rounding a denormal operand to zero does not appre-

ciably affect the quality of the processed data.
The denormals-are-zeros flag is cleared upon a power-up or reset of the processor, disabling the denormals-are-
zeros mode.
The denormals-are-zeros mode was introduced in the Pe ntium 4 and Intel Xeon processor with the SSE2 exten-
sions; however, it is fully compatible with the SSE SIMD floating-point instructions (that is, the denormals-are-zeros flag affects the operation of the SSE SIMD floating-p oint instructions). In earlier IA-32 processors and in 
some models of the Pentium 4 processor, this flag (bit 6) is reserved. See Section 11.6.3, “Checking for the DAZ 
Flag in the MXCSR Register,” for instructions for detecting the availability of this feature.
Attempting to set bit 6 of the MXCSR register on processo rs that do not support the DAZ flag will cause a general-
protection exception (#GP). See Section 11.6.6, “Guidelines for Writing to the MXCSR Register,” for instructions for 
preventing such general-protection exceptions by usin g the MXCSR_MASK value returned by the FXSAVE instruc-
tion.
10.2.4 Compatibility of Intel® SSE with In tel® SSE2 and SSE3, MMX, and the x87 FPU
The state (XMM registers and MXCSR register) introduced into the IA-32 execution environment with Intel SSE is 
shared with Intel SSE2 and SSE3. Intel SSE, SSE2, and SSE3 instructions are fully compatible; they can be 
executed together in the same instruction stream with no  need to save state when switching between instruction 
sets.
XMM registers are independent of the x87 FPU and MMX re gisters, so Intel SSE, SSE2, and SSE3 operations 
performed on the XMM registers can be performed in para llel with operations on the x87 FPU and MMX registers; 
see Section 11.6.7, “Interaction of Intel® SSE and SSE2 Instructions with x87 FPU and MMX Instructions.”
The FXSAVE and FXRSTOR instructions save and restore the SSE/SSE2/SSE3 states along with the x87 FPU and 
MMX state.
10.3 INTEL® SSE DATA TYPES
Intel SSE introduced one data type, the 128-bit packed sing le precision floating-point data type, to the IA-32 archi-
tecture (see Figure 10-4). This data type consists of four  IEEE 32-bit single precision floating-point values packed 10-6 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
into a double quadword. See Figure 4-3 for the layout of a single precision floating-point value; refer to Section 
4.2.2, “Floating-Point Data Types,” for a detailed descr iption of the single precision floating-point format.
This 128-bit packed single precision floating-point data type is operated on in the XMM registers or in memory. 
Conversion instructions are provided to convert two packed  single precision floating-point values into two packed 
doubleword integers or a scalar single precision floating -point value into a doubleword integer (see Figure 11-8).
Intel SSE provides conversion instructions between XMM registers and MMX registers, and between XMM registers 
and general-purpose bit registers. See Figure 11-8.
The address of a 128-bit packed memory operand must be aligned on a 16-byte boundary, except in the following 
cases: 
•The MOVUPS instruction supports unaligned accesses.
•Scalar instructions that use a 4-byte memory oper and that is not subject to alignment requirements.
Figure 4-2 shows the byte order of 128-bit (double quadword) data types in memory.
10.4 INTEL® SSE INSTRUCTION SET
Intel SSE instructions are divide d into four functional groups:
•Packed and scalar single precision floating-point instructions.
•64-bit SIMD integer instructions.
•State management instructions.
•Cacheability control, prefetch, an d memory ordering instructions.
The following sections give an overview of each of the instructions in these groups.
10.4.1 Intel® SSE Packed and Scal ar Floating-Point Instructions
The packed and scalar single precision floating-point instructions are divided into the following subgroups:
•Data movement instructions.
•Arithmetic instructions.
•Logical instructions.
•Shuffle instructions.
•Conversion instructions.
The packed single precision floating-point instructions  perform SIMD operations on packed single precision 
floating-point operands (see Figure 10-5). Each source oper and contains four single precision floating-point values, 
and the destination operand contains the results of the op eration (OP) performed in pa rallel on the corresponding 
values (X0 and Y0, X1 and Y1, X2 and Y2, and X3 and Y3) in each operand.Figure 10-4.  128-Bit Packed Single Precision Floating-Point Data Type0 127Contains 4 Single Precision 
64 63 3132 9596Vol. 1 10-7PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
The scalar single precision floating-point instructions oper ate on the low (least significant) doublewords of the two 
source operands (X0 and Y0); see Figure 10-6. The three most  significant doublewords (X1, X2, and X3) of the first 
source operand are passed through to the destination. The scalar operations are similar to the floating-point oper-
ations performed in the x87 FPU data re gisters with the precision control field in the x87 FPU control word set for 
single precision (24-bit significand), except that x87 st ack operations use a 15-bit exponent range for the result, 
while SSE operations use an 8-bit exponent range.
10.4.1.1  Intel® SSE Da ta Movement Instructions
Intel SSE data movement instructions move single pr ecision floating-point data between XMM registers and 
The MOVAPS (move aligned packed single precision floating -point values) instruction transfers a double quadword 
operand containing four packed single precision floating-p oint values from memory to an XMM register and vice 
versa, or between XMM registers. The memory address must be aligned to a 16-byte boundary; otherwise, a 
general-protection exception (#GP) is generated.
The MOVUPS (move unaligned packed single precision, floa ting-point) instruction performs the same operations as 
the MOVAPS instruction, except that 16-byte a lignment of a memory address is not required.
The MOVSS (move scalar single precision floating-point) instruction transfers a 32-bit single precision floating-
point operand from memory to the low doubleword of an XMM register and vice versa, or between XMM registers.
The MOVLPS (move low packed single precision floating-point) instruction moves two packed single precision 
floating-point values from memory to the low quadword of an XMM register and vice versa. The high quadword of 
the register is left unchanged.Figure 10-5.  Packed Single Precision Floating-Point Operation
Figure 10-6.  Scalar Single Precision Floating-Point OperationX3 X2 X1 X0
Y3 Y2 Y1 Y0
X3 OP Y3 X2 OP Y2 X1 OP Y1 X0 OP Y0OP OP OP OP
X3 X2 X1 X0
Y3 Y2 Y1 Y0
X3 X2 X1 X0 OP Y0OP10-8 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
The MOVHPS (move high packed single precision floating -point) instruction moves two packed single precision 
floating-point values from memory to the high quadword of an XMM register and vice versa. The low quadword of 
the register is left unchanged.
The MOVLHPS (move packed single precision floating-point low to high) instruction moves two packed single preci-
sion floating-point values from the low quadword of the source XMM register into the high quadword of the desti-
nation XMM register. The low quadword of th e destination register is left unchanged.
The MOVHLPS (move packed single precision floating-point high to low) instruction moves two packed single preci-
sion floating-point values from the high quadword of th e source XMM register into the low quadword of the desti-
nation XMM register. The high quadword of the destination register is left unchanged.
The MOVMSKPS (move packed single precision floating-point  mask) instruction transfers the most significant bit of 
each of the four packed single precision floating-point numbers in an XMM register to a general-purpose register. 
This 4-bit value can then be used as a condition to perform branching.
10.4.1.2  Intel® SSE Arithmetic Instructions
Intel SSE arithmetic instructions perform addition, subtract ion, multiply, divide, reciprocal, square root, reciprocal 
of square root, and maximum/minimum operations on pack ed and scalar single precision floating-point values.
The ADDPS (add packed single precision floating-point  values) and SUBPS (subtrac t packed single precision 
floating-point values) instructions add and subtract, respec tively, two packed single precision floating-point oper-
ands.
The ADDSS (add scalar single precision floating-point valu es) and SUBSS (subtract scalar single precision floating-
point values) instructions add and subtract, respectively, th e low single precision floating -point values of two oper-
ands and store the result in the low doubleword of the destination operand.
The MULPS (multiply packed single precision floating-point  values) instruction multiplies two packed single preci-
sion floating-point operands.

ands.
The MULSS (multiply scalar single precision floating-point values) instruction multiplies the low single precision 
floating-point values of two operands and stores the re sult in the low doubleword of the destination operand.
The DIVPS (divide packed, single precision floating-point values) instruction divides two packed single precision 
The DIVSS (divide scalar single precision floating-point valu es) instruction divides the low single precision floating-
point values of two operands and stores the result in the low doubleword of the destination operand.
The RCPPS (compute reciprocals of packed single precisio n floating-point values) instruction computes the approx-
imate reciprocals of values in a packed single precision floating-point operand.
The RCPSS (compute reciprocal of scalar single precision floating-point values) instruction computes the approxi-
mate reciprocal of the low single precision floating-point value in the source operand and stores the result in the 
low doubleword of the destination operand.
The SQRTPS (compute square roots of packed single pr ecision floating-point values) instruction computes the 
square roots of the values in a packed single precision floating-point operand.
The SQRTSS (compute square root of scalar single precision floating-point values) instruction computes the square 
root of the low single precision floating-point value in th e source operand and stores the result in the low double-
word of the destination operand.
The RSQRTPS (compute reciprocals of square roots of pack ed single precision floating-point values) instruction 
computes the approximate reciprocals of the square roots of  the values in a packed single precision floating-point 
operand.
The RSQRTSS (reciprocal of square root of scalar single precision floating-point value) instruction computes the 
approximate reciprocal of the square root of the low single  precision floating-point value in the source operand and 
stores the result in the low doubleword of the destination operand.
The MAXPS (return maximum of packed single precision floating-point values) instruction compares the corre-
sponding values from two packed single precision floa ting-point operands and returns the numerically greater 
value from each comparison to the destination operand.Vol. 1 10-9PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
The MAXSS (return maximum of scalar single precision floating-point values) instruction compares the low values 
from two packed single precision floating-point operan ds and returns the numerically greater value from the 
comparison to the low doubleword of the destination operand.
The MINPS (return minimum of packed single precision floating-point values) instruction compares the corre-
sponding values from two packed single precision floati ng-point operands and returns the numerically lesser value 
from each comparison to the destination operand.
The MINSS (return minimum of scalar single precision floa ting-point values) instruction compares the low values 
from two packed single precision floating-point oper ands and returns the numerically lesser value from the 
10.4.2 Intel® SSE Logical Instructions
Intel SSE logical instructions perform AND, AND NOT, OR, and XOR operations on packed single precision floating-
point values. 
The ANDPS (bitwise logical AND of packed single precision floating-point values) instruction returns the logical AND 
of two packed single precision floating-point operands.
The ANDNPS (bitwise logical AND NOT of packed single pr ecision, floating-point values) instruction returns the 
logical AND NOT of two packed single precision floating-point operands.
The ORPS (bitwise logical OR of packed single precision, floating-point values) instruction returns the logical OR of 
two packed single precision floating-point operands.
The XORPS (bitwise logical XOR of packed single precisio n, floating-point values) instruction returns the logical 
XOR of two packed single precision floating-point operands.
10.4.2.1  Intel® SSE Comparison Instructions
The compare instructions compare packed  and scalar single precision floating-p oint values and return the results 
of the comparison either to the destination operand or to the EFLAGS register.
The CMPPS (compare packed single precision floating-point values) instruction compares the corresponding values 
from two packed single precision floating-point operands , using an immediate operand as a predicate, and returns 
a 32-bit mask result of all 1s or all 0s for each compar ison to the destination operand. The value of the immediate 
operand allows the selection of any of 8 compare condit ions: equal, less than, less than equal, unordered, not 
equal, not less than, not less than or equal, or ordered.
The CMPSS (compare scalar single precision, floating-point  values) instruction compares the low values from two 
packed single precision floating-point operands, using an  immediate operand as a predicate, and returns a 32-bit 
mask result of all 1s or all 0s for the comparison to th e low doubleword of the destination operand. The immediate 
operand selects the compare conditio ns as with the CMPPS instruction.
The COMISS (compare scalar single precision floating-p oint values and set EFLAGS) and UCOMISS (unordered 
compare scalar single precision floating-point values and set EFLAGS) instructions compare the low values of two 
packed single precision floating-point operands and set the ZF, PF, and CF flags in the EFLAGS register to show the 
result (greater than, less than, equal, or unordered). Th ese two instructions differ as follows: the COMISS instruc-
tion signals a floating-point invalid-operation (#I) except ion when a source operand is either a QNaN or an SNaN; 
the UCOMISS instruction only signals an invalid-operation exception when a source operand is an SNaN.
10.4.2.2  Intel® SSE Shuffle and Unpack Instructions
Intel SSE shuffle and unpack instructions shuffle or interlea ve the contents of two packed single precision floating-
point values and store the results in the destination operand.
The SHUFPS (shuffle packed single precision floating-point  values) instruction places any two of the four packed 
single precision floating-point values from the destinatio n operand into the two low-order doublewords of the desti-
nation operand, and places any two of  the four packed single precision floating-point values from the source 
operand in the two high-order doublewords of the dest ination operand (see Figure 10-7). By using the same 
register for the source and destination operands, the SHUFPS instruction can shuffle four single precision floating-point values into any order. 10-10 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
The UNPCKHPS (unpack and interleave high packed single precision floating-point values) instruction performs an 
interleaved unpack of the high-order single precision floa ting-point values from the source and destination oper-
ands and stores the result in the destination operand (see Figure 10-8).
The UNPCKLPS (unpack and interleave low packed single precision floating-point values) instruction performs an 
interleaved unpack of the low-order sing le precision floating-point values from the source and destination operands 
and stores the result in the destination operand (see Figure 10-9).Figure 10-7.  SHUFPS Instruct ion, Packed Shuffle Operation
Figure 10-8.  UNPCKHPS Instruction, High Unpack and Interleave Operation
Figure 10-9.  UNPCKLPS Instruction, Low Unpack and Interleave OperationX3 X2 X1 X0
Y3 Y2 Y1 Y0
Y3 ... Y0 Y3 ... Y0 X3 ... X0 X3 ... X0DEST
SRC
DEST
X3 X2 X1 X0
Y3 Y2 Y1 Y0
Y3 X3 Y2 X2DEST
SRC
DEST
X3 X2 X1 X0
Y3 Y2 Y1 Y0
Y1 X1 Y0 X0DEST
SRC
DESTVol. 1 10-11PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
10.4.3 Intel® SSE Conversion Instructions
Intel SSE conversion instructions (see Figure 11-8) supp ort packed and scalar conversions between single preci-
sion floating-point and doubleword integer formats.
The CVTPI2PS (convert packed doubleword integers to pa cked single precision floating-point values) instruction 
converts two packed signed doubleword integers into two packed single precision floating-point values. When the 
conversion is inexact, the result is rounded according to the rounding mode selected in the MXCSR register. 
The CVTSI2SS (convert doubleword integer to scalar single  precision floating-point value) instruction converts a 
signed doubleword integer into a single precision floating-point value. When the conversion is inexact, the result is 
rounded according to the rounding mode selected in the MXCSR register. 
The CVTPS2PI (convert packed single precision floating-point values to packed doubleword integers) instruction 
converts two packed single precision floating-point values  into two packed signed doubleword integers. When the

converts two packed single precision floating-point values  into two packed signed doubleword integers. When the 
conversion is inexact, the result is rounded according to the rounding mode selected in the MXCSR register. The 
CVTTPS2PI (convert with truncation packed single precisio n floating-point values to packed doubleword integers) 
instruction is similar to the CVTPS2PI instruction, except that truncation is used to round a source value to an 
integer value; see Section 4.8.4.2, “Truncation with Intel® SSE, SSE2, and AVX Conversion Instructions.”
The CVTSS2SI (convert scalar single precision floating-poi nt value to doubleword integer) instruction converts a 
single precision floating-point value into a signed doubleword  integer. When the conversion is inexact, the result is 
rounded according to the rounding mode selected in the MXCSR register. The CVTTSS2SI (convert with truncation 
scalar single precision floating-point value to doubleword integer) instruction is similar to the CVTSS2SI instruc-
tion, except that truncation is used to round the source value to an integer value; see Section 4.8.4.2, “Truncation 
with Intel® SSE, SSE2, and AVX Conversion Instructions.”
10.4.4 Intel® SSE 64-Bit SIMD Integer Instructions
Intel SSE adds the following 64-bit packed integer inst ructions to the IA-32 architecture. These instructions 
operate on data in MMX registers and 64-bit memory locations. 
NOTE
When Intel SSE2 is present in an IA-32 processor,  these instructions are extended to operate on 
128-bit operands in XMM register s and 128-bit memory locations.
The PAVGB (compute average of packed unsigned byte  integers) and PAVGW (compute average of packed 
unsigned word integers) instructions compute a SIMD aver age of two packed unsigned by te or word integer oper-
ands, respectively. For each corresponding pair of data el ements in the packed source operands, the elements are 
added together, a 1 is added to the temporary sum, and that result is shifted right one bit position.
The PEXTRW (extract word) instruction copies a selected  word from an MMX regist er into a general-purpose 
register.
The PINSRW (insert word) instruction copies a word from  a general-purpose register or from memory into a 
selected word location in an MMX register.
The PMAXUB (maximum of packed unsi gned byte integers) instruction compares the corresponding unsigned byte 
integers in two packed operands and returns the grea ter of each comparison to the destination operand.
The PMINUB (minimum of packed unsigned byte integers ) instruction compares the corresponding unsigned byte 
integers in two packed operands and returns the le sser of each comparison to the destination operand.
The PMAXSW (maximum of packed signed word integers ) instruction compares the corresponding signed word 
The PMINSW (minimum of packed signed word integers) in struction compares the corresponding signed word inte-
gers in two packed operands and returns the lesser  of each comparison to the destination operand.
The PMOVMSKB (move byte mask) instruction creates an 8- bit mask from the packed byte integers in an MMX 
register and stores the result in the low byte of a genera l-purpose register. The mask contains the most significant 
bit of each byte in the MMX register. (When operat ing on 128-bit operands, a 16-bit mask is created.)10-12 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
The PMULHUW (multiply packed unsigned word integers and store high result) instruction performs a SIMD 
unsigned multiply of the words in the two source operands and returns the high word of each result to an MMX 
register.
The PSADBW (compute sum of absolute differences) inst ruction computes the SIMD absolute differences of the 
corresponding unsigned byte integers in two source oper ands, sums the differences, and stores the sum in the low 
The PSHUFW (shuffle packed word integers) instruction shuf fles the words in the source operand according to the 
order specified by an 8-bit immediate operand an d returns the result to the destination operand.
10.4.5 MXCSR State Management Instructions
The MXCSR state management instructions (LDMXCSR an d STMXCSR) load and save the state of the MXCSR 
register, respectively. The LDMXCSR instruction loads the MXCSR register  from memory, while the STMXCSR 
instruction stores the contents of the register to memory.
10.4.6 Cacheability Control, Prefet ch, and Memory Ordering Instructions
Intel SSE introduced several new instructions to give programs more control over the caching of data. They also 
introduces the PREFETCH h instructions, which provide the ability to pref etch data to a specified cache level, and the 
SFENCE instruction, which enforces pr ogram ordering on stores. These instru ctions are described in the following 
sections.
10.4.6.1  Cacheability Control Instructions
The following three instructions enable data from the MMX  and XMM registers to be stored to memory using a non-
temporal hint. The non-temporal hint directs the processor to store the data to memory without writing the data 
into the cache hierarchy. See Section 10.4.6.2, “Caching of Temporal vs. Non-Temporal Data,” for information 
about non-temporal stores and hints.
The MOVNTQ (store quadword using non-temporal hint) instruction stores packed integer data from an MMX 
register to memory, using a non-temporal hint.
The MOVNTPS (store packed single precision floating-poi nt values using non-temporal hint) instruction stores 
packed floating-point data from an XMM register to memory, using a non-temporal hint.
The MASKMOVQ (store selected bytes of quadword) instructio n stores selected byte integers from an MMX register 
to memory, using a byte mask to selectively write the individual bytes. This instruction also uses a non-temporal hint.
10.4.6.2  Caching of Temp oral vs. Non-Temporal Data
Data referenced by a program can be te mporal (data will be used again) or non-temporal (data will be referenced 
once and not reused in the immediate future). For exampl e, program code is generally temporal, whereas, multi-
media data, such as the display list in a 3-D graphics appl ication, is often non-temporal. To make efficient use of 
the processor’s caches, it is generally desirable to cache temporal data and not cache non-temporal data. Over-
loading the processor’s caches with non-temporal data is sometimes referred to as “polluting the caches.” The Intel 
SSE and SSE2 cacheability control instructions enable a program to write non-temporal data to memory in a 
manner that minimizes pollution of caches. 
These Intel SSE and SSE2 non-temporal store instructions minimize cache pollutions by treating the memory being 
accessed as the write combining (WC) type. If a program sp ecifies a non-temporal store with one of these instruc-
tions and the memory type of the destination region is write back (WB), write through (WT), or write combining 
(WC), the processor will do the following:
•If the memory location being written to is present in the cache hierarchy, the data in the caches is evicted.1
1. Some older CPU implementations (e.g., Pentium M) allowed addre sses being written with a non-temp oral store instruction to be 
updated in-place if the memo ry type was not WC and line  was already in the cache.Vol. 1 10-13PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
•The non-temporal data is written to memory with WC semantics.
See also: Chapter 12, “Memory Cache Control,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Using the WC semantics, the store transaction will be weak ly ordered, meaning that the data may not be written to 
memory in program order, and the store will not write allocate (that is, the processor will not fetch the corre-
sponding cache line into the cache hierarchy, prior to pe rforming the store). Also, different processor implementa-
tions may choose to collapse and combine these stores.
The memory type of the region being written to can ove rride the non-temporal hint, if the memory address speci-
fied for the non-temporal store is in uncacheable memory . Uncacheable as referred to here means that the region 
being written to has been mapped with either an unc acheable (UC) or write pr otected (WP) memory type.
In general, WC semantics require software to ensure cohe rence, with respect to other processors and other system 
agents (such as graphics cards). Appropriate use of sync hronization and fencing must be performed for producer-
consumer usage models. Fencing ensures that all system agents have global visibility of the stored data; for instance, failure to fence may result in a written cache line staying within a processor and not being visible to other 
agents. 
The memory type visible on the bus in the presence of me mory type aliasing is implementation specific. As one 
possible example, the memory type written to the bus may re flect the memory type for the first store to this line,

agents. 
possible example, the memory type written to the bus may re flect the memory type for the first store to this line, 
as seen in program order; other alternatives are possibl e. This behavior should be considered reserved, and 
dependence on the behavior of any particular  implementation risks future incompatibility.
NOTE
Some older CPU implementations (e.g., Pentium M) may implement non-temporal stores by 
updating in place data that already reside in the cache hierarchy. For such processors, the 
destination region should also be mapped as WC. If mapped as WB or WT, there is the potential for 
speculative processor reads to bring the data into  the caches; in this case, non-temporal stores 
would then update in place, and data would not be flushed from the processor by a subsequent 
fencing operation.
10.4.6.3  PREFETCH h Instructions
The PREFETCH h instructions permit programs to load data into the processor at a suggested cache level, so that 
the data is closer to the processor’s load and store unit wh en it is needed. These instructions fetch 32 aligned bytes 
(or more, depending on the implementation) containing th e addressed byte to a location in the cache hierarchy 
specified by the temporal locality hint (see Table 10-1). In th is table, the first-level cache is closest to the processor 
and second-level cache is farther away from the processor than the first-level cache. The hints specify a prefetch 
of either temporal or non-temporal data (see Section 10.4.6.2, “Caching of Temporal vs. Non-Temporal Data”). Subsequent accesses to temporal data are treated like no rmal accesses, while those to non-temporal data will 
continue to minimize cache pollution. If the data is already present at a level of the cache hierarchy that is closer 
to the processor, the PREFETCH h instruction will not result in any data movement. The PREFETCH h instructions do 
not affect functional behavior of the program.
See Section 11.6.13, “Cacheability Hint Instructions ,” for additional information about the PREFETCH h instructions.
Table 10-1.  PREFETCH h Instructions Caching Hints
PREFETCH h Instruction 
Mnemonic Actions
PREFETCHT0 Temporal data—fetch data in to all levels of cache hierarchy:
• Pentium III processor—1st-le vel cache or 2nd-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache
PREFETCHT1 Temporal data—fetch data into level 2 cache and higher
• Pentium III processor—2nd-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache10-14 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
10.4.6.4  SFENCE Instruction
The SFENCE (Store Fence) instruction controls write orderi ng by creating a fence for me mory store operations. This 
instruction guarantees that the result of every store inst ruction that precedes the store fence in program order is 
globally visible before any store instruction that follows th e fence. The SFENCE instruction provides an efficient way 
of ensuring ordering between procedures that produce weakly-ordered data and procedures that consume that 
data.
10.5 FXSAVE AND FXRSTOR INSTRUCTIONS
The FXSAVE and FXRSTOR instructions were introduced in to the IA-32 architecture in the Pentium II processor 
family (prior to the introduction of the SSE extensions). Th e original versions of these instructions performed a fast 
save and restore, respectively, of the x87 execution environment ( x87 state ). (By saving the state of the x87 FPU 
data registers, the FXSAVE and FXRSTOR instructions impl icitly save and restore the state of the MMX registers.) 
The SSE extensions expanded the scope of these instructio ns to save and restore the states of the XMM registers 
and the MXCSR register ( SSE state ), along with x87 state. 
The FXSAVE and FXRSTOR instructions can be used in  place of the FSAVE/FNSAVE and FRSTOR instructions; 
however, the operation of the FXSAVE and FXRSTOR in structions are not identical to the operation of 
FSAVE/FNSAVE and FRSTOR.
NOTE
The FXSAVE and FXRSTOR instructions are not considered part of the SSE instruction group. They have a separate CPUID feature bit to indicate whether they are present (if 
CPUID.01H:EDX.FXSR[bit 24] = 1). 
The CPUID feature bit for SSE extensions does not indicate the presence of FXSAVE and FXRSTOR.
The FXSAVE and FXRSTOR instructions organize x87 st ate and SSE state in a region of memory called the FXSAVE 
area. Section 10.5.1 provides details of the FXSAVE area and its format. Section 10.5.2 describes operation of 
FXSAVE, and Section 10.5.3 describes the operation of FXRSTOR.
10.5.1 FXSAVE Area
area. Each of the instructions takes a memory operand th at specifies the 16-byte aligned base address of the 
FXSAVE area on which it operates.PREFETCHT2 Temporal data—fetch data into level 2 cache and higher
PREFETCHNTA Non-temporal data—fetch data into location  close to the processor, minimizing cache pollution 
• Pentium III processor—1st-level cache • Pentium 4 and Intel Xeon processor—2nd-level cacheTable 10-1.  PREFETCH h Instructions Caching Hints (Contd.)
Mnemonic ActionsVol. 1 10-15PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
Every FXSAVE area comprises the 512 bytes starting at th e area’s base address. Table 10-2 illustrates the format 
of the first 416 bytes of the legacy region of an FXSAVE area.
The x87 state component comprises bytes 23:0 and bytes 159:32. The SSE state component comprises 
bytes 31:24 and bytes 415:160. FXSAVE and FXRSTOR do  not use bytes 511:416; bytes 463:416 are reserved.
Section 10.5.2 and Section 10.5.3 provide details of  how FXSAVE and FXRSTOR use an FXSAVE area.
10.5.1.1  x87 State
Table 10-2 illustrates how FXSAVE and FXRSTOR organize x87 state and SSE state; the x87 state is listed below, 
along with details of its interactions with FXSAVE and FXRSTOR:
•Bytes 1:0, 3:2, and 7:6 are used for x87 FPU Control Word (FCW), x87 FPU Status Word (FSW), and x87 FPU 
Opcode (FOP), respectively.Table 10-2.  Format of an FXSAVE Area
15 14 13  12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CS or FPU 
IP bits 63:32FPU IP bits 31:0 FOP Rsvd. FTW FSW FCW 0
MXCSR_MASK MXCSR Reserved DS or
FPU DP 
bits 63:32 FPU DP bits 31:0 16
Reserved ST0/MM0 32
Reserved ST1/MM1 48
Reserved ST2/MM2 64
Reserved ST3/MM3 80
Reserved ST4/MM4 96
Reserved ST5/MM5 112
Reserved ST6/MM6 128
Reserved ST7/MM7 144
XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
XMM15 40010-16 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
•Byte 4 is used for an abridged version of the x87 FPU Tag Word (FTW). The following items describe its usage:
—F o r  e a c h  j, 0≤ j≤ 7, FXSAVE saves a 0 into bit j of byte 4 if x87 FPU data register ST j has a empty tag; 
otherwise, FXSAVE saves a 1 into bit j of byte 4.
—F o r  e a c h  j, 0≤ j≤ 7, FXRSTOR establishes the tag value for x87 FPU data register ST j as follows. If bit j of 
byte 4 is 0, the tag for ST j in the tag register for that data regist er is marked empty (11B); otherwise, the 
x87 FPU sets the tag for ST j based on the value being loaded into that register (see below).
•Bytes 15:8 are used as follows:
— If the instruction has no REX prefix, or if REX.W = 0:
•Bytes 11:8 are used for bits 31:0 of the x87 FPU Instruction Pointer Offset (FIP).
•If CPUID.(EAX=07H, ECX=0H):EBX[bit 13] = 0, byte s 13:12 are used for x87 FPU Instruction Pointer 
Selector (FPU CS). Otherwise, the processor deprec ates the FPU CS value: FXSAVE saves it as 0000H.
•Bytes 15:14 are not used.
— If the instruction has a REX prefix with REX.W = 1,  bytes 15:8 are used for the full 64 bits of FIP.
•Bytes 23:16 are used as follows:
•Bytes 19:16 are used for bits 31:0 of the x87 FPU Data Pointer Offset (FDP).
•If CPUID.(EAX=07H, ECX=0H):EBX[bit 13] = 0, bytes 21:20 are used for x87 FPU Data Pointer Selector 
(FPU DS). Otherwise, the processor deprecates the FPU DS value: FXSAVE saves it as 0000H.
•Bytes 23:22 are not used.
— If the instruction has a REX prefix with REX.W = 1,  bytes 23:16 are used for the full 64 bits of FDP.
•Bytes 31:24 are used for SSE state (see Section 10.5.1.2).
•Bytes 159:32 are used for the registers ST0–ST7 (MM0–MM7 ). Each of the 8 registers is allocated a 128-bit 
region, with the low 80 bits used for the register and the upper 48 bits unused.
10.5.1.2  SSE State
Table 10-2 illustrates how FXSAVE and FXRSTOR organize x8 7 state and SSE state; the SSE state is listed below, 
•Bytes 23:0 are used for x87 state (see Section 10.5.1.1).
•Bytes 27:24 are used for the MXCSR register. FXRSTOR ge nerates a general-protection fault (#GP) in response 
to an attempt to set any of the reserved bits in the MXCSR register.
•Bytes 31:28 are used for the MXCSR_MASK value. FXRSTOR ignores this field.
•Bytes 159:32 are used for x87 state.

•Bytes 287:160 are used for the registers XMM0–XMM7. 
•Bytes 415:288 are used for the registers XMM8–XMM15. Thes e fields are used only in 64-bit mode. Executions 
of FXSAVE outside 64-bit mode do not write to these byte s; executions of FXRSTOR outside 64-bit mode do not 
read these bytes and do not update XMM8–XMM15.
If CR4.OSFXSR = 0, FXSAVE an d FXRSTOR may or may not operate on SSE state; this behavior is implementation 
dependent. Moreover, SSE instructions cannot be used unless CR4.OSFXSR = 1.
10.5.2 Operation of FXSAVE
The FXSAVE instruction takes a single memory operand, wh ich is an FXSAVE area. The instruction stores x87 state 
and SSE state to the FXSAVE area. See Section 10.5.1.1 an d Section 10.5.1.2 for details regarding mode-specific 
operation and operation determined by instruction prefixes.Vol. 1 10-17PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)
10.5.3 Operation of FXRSTOR
The FXRSTOR instruction takes a single memory operand, wh ich is an FXSAVE area. If the value at bytes 27:24 of 
the FXSAVE area is not a legal value for the MXCSR regist er (e.g., the value sets reserved bits), execution of 
FXRSTOR results in a general-protection fault (#GP). Othe rwise, the instruction loads x87 state and SSE state from 
the FXSAVE area. See Section 10.5.1.1 and Section 10.5 .1.2 for details regarding mode-specific operation and 
operation determined by instruction prefixes.
10.6 HANDLING INTEL® SS E INSTRUCTION EXCEPTIONS
See Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,” for a detailed discussion of the general and SIMD 
floating-point exceptions that can be generated with the Intel SSE instructions and for guidelines for handling these 
exceptions when they occur.
10.7 WRITING APPLICATIONS WITH INTEL® SSE
See Section 11.6, “Writing Applications with Intel® SSE and SSE2,” for additional information about writing appli-
cations and operating-system code using Intel SSE.10-18 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)Vol. 1 11-1CHAPTER 11
STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
The streaming SIMD extensions 2 (SSE2) were introduced into the IA-32 architecture in the Pentium 4 and Intel 
Xeon processors. These extensions enhance the performanc e of IA-32 processors for advanced 3-D graphics, video 
decoding/encoding, speech recognition, E-commerce, Internet, scientific, and engineering applications. 
This chapter describes the SSE2 extensions and provides in formation to assist in writing application programs that 
use these and the SSE extensions. 
11.1 OVERVIEW OF INTEL® SSE2
Intel SSE2 uses the single instruction multiple data (SIM D) execution model that is used with MMX technology and 
Intel SSE. They extend this model with  support for packed double precision floating-point values and for 128-bit 
packed integers.
If CPUID.01H:EDX.SSE2[bit 26] = 1, Intel SSE2 is present.
Intel SSE2 adds the following features to the IA-32 archit ecture, while maintaining backward compatibility with all 
existing IA-32 processors, applications, and operating systems.
•Six data types: 
— 128-bit packed double precision floating-point (two  IEEE Standard 754 double precision floating-point 
values packed into a double quadword).
— 128-bit packed byte integers.
— 128-bit packed word integers.
— 128-bit packed doubleword integers.— 128-bit packed quadword integers.
•Instructions to support the additional data type s and extend existing SIMD integer operations:
— Packed and scalar double precision floating-point instructions.
— Additional 64-bit and 128-bit SIMD integer instructions.— 128-bit versions of SIMD integer instructions introduced with the MMX technology and Intel SSE.
— Additional cacheability-control and instruction-ordering instructions.
•Modifications to existing IA-32 instructions to support Intel SSE2 features:
— Extensions and modifications to the CPUID instruction.— Modifications to the RDPMC instruction.
These new features extend the IA-32 architecture’s  SIMD programming model in three important ways:
•They provide the ability to perform SI MD operations on pairs of packed double precision floating-point values. 
This permits higher precision computations to be carried out in XMM registers, which enhances processor 
performance in scientific and engineer ing applications and in applications that use advanced 3-D geometry 
techniques (such as ray tracing). Additional flexibility is provided with instructions that operate on single 
(scalar) double precision floating-point values located in the low quadword of an XMM register. 
•They provide the ability to operate on 128-bit packed integers (bytes, words, doublewords, and quadwords) in 
XMM registers. This provides greater flexibility and gr eater throughput when performing SIMD operations on 
packed integers. The capability is pa rticularly useful for applications such as RSA authentication and RC5 
encryption. Using the full set of SIMD registers, data ty pes, and instructions provided with the MMX technology 
and Intel SSE/SSE2, programmers can develop algorithms that finely mix packed single- and double precision 
floating-point data and 64- and 128-bit packed integer data. 
•Intel SSE2 enhances the support introduced with Intel SSE for controlling the cacheability of SIMD data. Intel SSE2 cache control instructions provide the ability to stream data in and out of the XMM registers without 
polluting the caches and the ability to prefetch data before it is actually used.11-2 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
Intel SSE2 is fully compatible with all software written for IA-32 processors. All existing software continues to run 
correctly, without modification, on processors that incorporate Intel SSE2, as well as in the presence of applications that incorporate these extensions. Enhancements to the CPUID instruction permit detection of Intel SSE2. Also, 
because Intel SSE2 uses the same registers as Intel SSE, no new operating-system support is required for saving 
and restoring program state during a context switch beyond that provided for Intel SSE.
Intel SSE2 is accessible from all IA-32 execution modes: protected mode, real address mode, and virtual 8086 
mode.
The following sections in this chapter describe the progra mming environment for Intel SSE2, including: the 128-bit 
XMM floating-point register set, data types, and Intel SSE2  instructions. The chapter also describes exceptions that 
can be generated with the Intel SSE and SSE2 instructions and gives guidelines for writing applications with Intel 
SSE and SSE2.
For additional information about Intel SSE2, see:
detailed description of individual Intel SSE2 instructions.
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating Intel SSE 
and SSE2 into an operating-system environment.
11.2 INTEL® SSE2 PROGRAMMING ENVIRONMENT
Figure 11-1 shows the programming environment for Intel SSE2. No new registers or other instruction execution 
state are defined with Intel SSE2. Intel SSE2 instructions use XMM registers, MMX registers, and/or IA-32 general-
purpose registers, as follows: 
•XMM registers —  These eight registers (see Figure 10-2) are used to operate on packed or scalar double 
precision floating-point data. Scalar operations are operations performed on individual (unpacked) double 
precision floating-point values stored in the low quadwo rd of an XMM register. XMM registers are also used to 
perform operations on 128-bit packed integer data. Th ey are referenced by the names XMM0 through XMM7.
•MXCSR register —  This 32-bit register (see Figure 10-3) provides st atus and control bits used in floating-point 
operations. The denormals-are-zeros and flush-to-zero flags in this register provide a higher performance 
alternative for the handling of denormal source op erands and denormal (underflow) results. For more Figure 11-1.  Intel® Steaming SIMD Extensions 2 Execution Environment0232 -1
RegistersVol. 1 11-3PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
information on the functions of these flags see Section 10.2.3.4, “Denormals-Are-Zeros,” and Section 10.2.3.3, 
“Flush-To-Zero.”
integer data. They are also used to hold operands  for some operations performed between MMX and XMM 
•General-purpose registers —  The eight general-purpose registers (see Figure 3-5) are used along with the

existing IA-32 addressing modes to address operands in memory. MMX and XMM registers cannot be used to 
address memory. The general-purpose registers are also used to hold operands for some SSE2 instructions. 
These registers are referenced by the names EA X, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.
•EFLAGS register —  This 32-bit register (see Figure 3-8) is used to record the results of some compare 
11.2.1 Intel® SSE2 in 64-Bit Mode and Compatibility Mode
In compatibility mode, Intel SSE2 functions like it does in protected mode. In 64-bit mode, eight additional XMM 
registers are accessible. Registers XMM8-X MM15 are accessed by using REX prefixes. 
Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5.
Some Intel SSE2 instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access 
11.2.2 Compatibility of Intel® SSE2 with In tel® SSE, MMX Technology, and x87 FPU 
Programming Environment
Intel SSE2 does not introduce any new state to the IA-32 execution environment beyond that of Intel SSE. Intel 
SSE2 represents an enhancement of Intel SSE; they are fully compatible and share the same state information. 
Intel SSE and SSE2 instructions can be executed together in the same instruction stream without the need to save 
state when switching between instruction sets.
XMM registers are independent of the x87 FPU and MMX regi sters; so Intel SSE and SSE2 operations performed on 
XMM registers can be performed in parallel with x87 FPU or  MMX technology operations; see Section 11.6.7, “Inter-
action of Intel® SSE and SSE2 Instructions with x87 FPU and MMX Instructions.”
The FXSAVE and FXRSTOR instructions save and restore the SSE and SSE2 states along with the x87 FPU and MMX 
states.
11.2.3 Denormals-Are-Zeros Flag
The denormals-are-zeros flag (bit 6 in the MXCSR register ) was introduced into the IA-32 architecture with Intel 
SSE2. See Section 10.2.3.4, “Denormals-Are-Zeros,” for a description of this flag.
11.3 INTEL® SSE2 DATA TYPES
Intel SSE2 introduced one 128-bit packed floating-point da ta type and four 128-bit SIMD integer data types to the 
IA-32 architecture (see Figure 11-2). 
•Packed double precision floating-point —  This 128-bit data type consists of two IEEE 64-bit double 
precision floating-point values packed into a double quadword. See Figure 4-3 for the layout of a 64-bit double 
precision floating-point value; refer to Section 4.2.2, “F loating-Point Data Types,” for a detailed description of 
double precision floating-point values.
•128-bit packed integers —  The four 128-bit packed integer data ty pes can contain 16 byte integers, 8 word 
integers, 4 doubleword integers, or 2 quadword integers. Refer to Section 4.6.2, “128-Bit Packed SIMD Data 
Types,” for a detailed description of the 128-bit packed integers.11-4 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
All of these data types are operated on  in XMM registers or memory. Instruct ions are provided to convert between 
these 128-bit data types and th e 64-bit and 32-bit data types.
cases: 
•A MOVUPD instruction that supports unaligned accesses.
•Scalar instructions that use an 8-byte memory operand that is not subject to alignment requirements.
Figure 4-2 shows the byte order of 128-bit (double quad word) and 64-bit (quadword) data types in memory.
11.4 INTEL® SSE2 INSTRUCTIONS
The Intel SSE2 instructions are divi ded into four functional groups:
•64-bit and 128-bit SIMD integer instructions.
•128-bit extensions of SIMD integer instructions introduced with the MMX technology and Intel SSE.
•Cacheability-control and instruction-ordering instructions.
The following sections provide mo re information about each group.
11.4.1 Packed and Scalar Double Precision Floating-Point Instructions
The packed and scalar double precision floating-point in structions are divided into the following sub-groups:
The packed double precision floating-point instructions perform SIMD operations similarly to the packed single 
precision floating-point instructions (see Figure 11-3). Each  source operand contains two double precision floating-Figure 11-2.  Data Types Introduced with Intel® SSE2128-Bit Packed Word Integers128-Bit Packed Byte Integers
128-Bit Packed Doubleword
Integers0 1270 127
0 1270 1270 127
128-Bit Packed Quadword 
Integers128-Bit Packed Double- 
Precision Floating-Point
64 63Vol. 1 11-5PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
point values, and the destination operand contains the resu lts of the operation (OP) performed in parallel on the 
corresponding values (X0 and Y0, and X1 and Y1) in each operand.
The scalar double precision floating-point instructions op erate on the low (least significant) quadwords of two 
source operands (X0 and Y0), as shown in Figure 11-4. Th e high quadword (X1) of the first source operand is 
passed through to the destination. The scalar operations ar e similar to the floating-point operations performed in 
x87 FPU data registers with the precision control field in the x87 FPU control word set for double precision (53-bit 
significand), except that x87 stack operations use a 15-b it exponent range for the result while Intel SSE2 opera-
tions use an 11-bit exponent range. 
See Section 11.6.8, “Compatibility of SIMD and x87 FPU Fl oating-Point Data Types,” for more information about 
obtaining compatible results when performing both scalar double precision floating-point operations in XMM regis-
ters and in x87 FPU data registers.
11.4.1.1  Data Movement Instructions
Data movement instructions move double precision floa ting-point data between XMM registers and between XMM 
registers and memory.
The MOVAPD (move aligned packed double precision floati ng-point) instruction transfers a 128-bit packed double 
precision floating-point operand from memory to an XMM register or vice versa, or between XMM registers. The 
memory address must be aligned to a 16-byte boundary; if not, a general-protection exception (GP#) is gener-
ated.Figure 11-3.  Packed Double Precision Floating-Point Operations
Figure 11-4.  Scalar Double Pr ecision Floating-Point OperationsX1 X0
     X1 OP Y1 X0 OP Y0OPY1 Y0
OP
X1 X0
      X1 X0 OP Y0OPY1 Y011-6 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
The MOVUPD (move unaligned packed double precision fl oating-point) instruction transfers a 128-bit packed 
double precision floating-point operand from memory to an  XMM register or vice versa, or between XMM registers. 
Alignment of the memory address is not required.
The MOVSD (move scalar double precision floating-point) in struction transfers a 64-bit double precision floating-
point operand from memory to the low quadword of an X MM register or vice versa, or between XMM registers. 
Alignment of the memory address is not requ ired, unless alignment checking is enabled.
The MOVHPD (move high packed double precision floating -point) instruction transfers a 64-bit double precision 
floating-point operand from memory to the high quadword of an XMM register or vice versa. The low quadword of 
the register is left unchanged. Alignment of the memory  address is not required, unless alignment checking is 
enabled.
The MOVLPD (move low packed double precision floating-p oint) instruction transfers a 64-bit double precision 
floating-point operand from memory to the low quadword of an XMM register or vice versa. The high quadword of 
enabled.
The MOVMSKPD (move packed double precision floating-point mask) instruction extracts the sign bit of each of the 
two packed double precision floating-point numbers in an XMM register and saves them in a general-purpose 
register. This 2-bit value can then be us ed as a condition to perform branching.
11.4.1.2  Intel® SSE2 Arithmetic Instructions
Intel SSE2 arithmetic instructions perform addition , subtraction, multiply, divide, square root, and 
maximum/minimum operations on packed and scalar double precision floating-point values.
The ADDPD (add packed double precision floating-point  values) and SUBPD (subtract packed double precision 
floating-point values) instructions add and subtract, respec tively, two packed double precision floating-point oper-
ands.
The ADDSD (add scalar double precision floating-point values) and SUBSD (subtract scalar double precision 
floating-point values) instructions add and subtract, respec tively, the low double precision floating-point values of

ands.
floating-point values) instructions add and subtract, respec tively, the low double precision floating-point values of 
two operands and stores the result in the low quadword of the destination operand.
The MULPD (multiply packed double precision floating-point  values) instruction multiplies two packed double preci-
The MULSD (multiply scalar double precision floating-point values) instruction multiplies the low double precision 
floating-point values of two operands and stores the result in the low quadword of the destination operand.
The DIVPD (divide packed double precision floating-point values) instruction divides two packed double precision 
The DIVSD (divide scalar double precision floating-point  values) instruction divides the low double precision 
The SQRTPD (compute square roots of packed double pr ecision floating-point values) instruction computes the 
square roots of the values in a packed double precision floating-point operand.
The SQRTSD (compute square root of scalar double prec ision floating-point values) instruction computes the 
square root of the low double precision floating-point valu e in the source operand and stores the result in the low 
quadword of the destination operand.
The MAXPD (return maximum of packed double precision floating-point values) instruction compares the corre-
sponding values in two packed double precision floating -point operands and returns the numerically greater value 
The MAXSD (return maximum of scalar doub le precision floating-point values) instruction compares the low double 
precision floating-point values from two packed double precision floating-point operands and returns the numeri-
cally higher value from the comparison to the low quadword of the destination operand.
The MINPD (return minimum of packed double precision floating-point values) instruction compares the corre-
sponding values from two packed double precision floati ng-point operands and returns the numerically lesser value 
from each comparison to the destination operand.Vol. 1 11-7PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
The MINSD (return minimum of scalar double precision floating-point values) instruction compares the low values 
from two packed double precision floating-point oper ands and returns the numerically lesser value from the 
comparison to the low quadword of the destination operand.
11.4.1.3  Intel® SSE2 Logical Instructions
intel SSE2 logical instructions perform AND, AND NOT, OR, and XOR operations on packed double precision floating-point values. 
The ANDPD (bitwise logical AND of packed double precision floating-point values) instruction returns the logical 
AND of two packed double precision floating-point operands.
The ANDNPD (bitwise logical AND NOT of packed double precision floating-point values) instruction returns the 
logical AND NOT of two packed double precision floating-point operands.
The ORPD (bitwise logical OR of packed double precision fl oating-point values) instruction returns the logical OR of 
two packed double precision floating-point operands.
The XORPD (bitwise logical XOR of pack ed double precision floating-point values) instruction returns the logical 
XOR of two packed double precision floating-point operands.
11.4.1.4  Intel® SSE2 Comparison Instructions
Intel SSE2 compare instructions compare packed and scalar double precision floating-point values and return the results of the comparison either to the destination operand or to the EFLAGS register.
The CMPPD (compare packed double precision floating-p oint values) instruction compares the corresponding 
values from two packed double precision floating-point operands, using an immediate operand as a predicate, and 
returns a 64-bit mask result of all 1s or all 0s for each  comparison to the destinatio n operand. The value of the 
immediate operand allows the selection of any of eight co mpare conditions: equal, less than, less than equal, unor-
dered, not equal, not less than, not less than or equal, or ordered.
The CMPSD (compare scalar double precision floating-point  values) instruction compares the low values from two 
packed double precision floating-point operands, using an  immediate operand as a predicate, and returns a 64-bit 
mask result of all 1s or all 0s for the comparison to the low quadword of the destination operand. The immediate 
operand selects the compare condition as with the CMPPD instruction.
The COMISD (compare scalar double precision floating-p oint values and set EFLAGS) and UCOMISD (unordered 
compare scalar double precision floating-point values and set EFLAGS) instructions compare the low values of two 
packed double precision floating-point operands and set the ZF, PF, and CF flags in the EFLAGS register to show the 
result (greater than, less than, equal, or unordered). Th ese two instructions differ as follows: the COMISD instruc-
the UCOMISD instruction only signals an invalid-operation exception when a source operand is an SNaN.
11.4.1.5  Intel® SSE2 Shuffle and Unpack Instructions
Intel SSE2 shuffle instructions shuffle the contents of tw o packed double precision floating-point values and store 
the results in the destination operand.
The SHUFPD (shuffle packed double precision floating-point  values) instruction places either of the two packed 
double precision floating-point values from the destin ation operand in the low quadword of the destination 
operand, and places either of the two packed double prec ision floating-point values from source operand in the 
high quadword of the destination operand (see Figure 11-5 ). By using the same register for the source and desti-
nation operands, the SHUFPD instruction can swap two packed double precision floating-point values. 11-8 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
The UNPCKHPD (unpack and interleave hi gh packed double precision floating-point values) instruction performs an 
interleaved unpack of the high values from the source and destination operands and stores the result in the desti-nation operand (see Figure 11-6).
The UNPCKLPD (unpack and interleave low packed double pr ecision floating-point values) instruction performs an 
interleaved unpack of the low values from the source and destination operands and stores the result in the desti-
nation operand (see Figure 11-7).Figure 11-5.  SHUFPD Instruct ion, Packed Shuffle Operation
Figure 11-6.  UNPCKHPD Instruction, High Unpack, and Interleave Operation
Figure 11-7.  UNPCKLPD Instruction, Low Unpack, and Interleave OperationX1 X0
Y1 Y0
Y1 or Y0 X1 or X0DEST
SRC
DEST
X1 X0
Y1 Y0
Y1 X1DEST
SRC
DEST
X1 X0
Y1 Y0
Y0 X0DEST
SRC
DESTVol. 1 11-9PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
11.4.1.6  Intel® SSE2 Conversion Instructions
Intel SSE2 conversion instructions (see Figure 11-8) support packed and scalar conversions between:
•Double precision and single precision floating-point formats.
•Double precision floating-point and doubleword integer formats.
•Single precision floating-point and doubleword integer formats.
Conversion between double precision and si ngle precision floating-points values —  The following instruc-
tions convert operands between double precision and single  precision floating-point formats. The operands being 
operated on are contained in XMM registers or memory (at most, one operand can reside in memory; the destina-tion is always an MMX register).
The CVTPS2PD (convert packed single precision floating-p oint values to packed double precision floating-point 
values) instruction converts two packed single precision floa ting-point values to two double precision floating-point 
values.
The CVTPD2PS (convert packed double precision floating-p oint values to packed single precision floating-point 
values) instruction converts two packed double-
precision floating-point values to two single precision floati ng-point values. When a conversion is inexact, the result 
is rounded according to the rounding mo de selected in the MXCSR register.
The CVTSS2SD (convert scalar single precision floating-point  value to scalar double precision floating-point value) 
instruction converts a single precision floating-point  value to a double precision floating-point value.
The CVTSD2SS (convert scalar double precision floating-point  value to scalar single precision floating-point value) 
instruction converts a double precision floating-point value to a single precision floating-point value. When the 
conversion is inexact, the result is rounded according to the rounding mode selected in the MXCSR register.
Conversion between double pr ecision floating-point values  and doubleword integers —  The following

Conversion between double pr ecision floating-point values  and doubleword integers —  The following 
instructions convert operands between double precision fl oating-point and doubleword integer formats. Operands Figure 11-8.  Intel® SSE an d SSE2 Conversion InstructionsCVTPS2PICVTTPS2DQCVTDQ2PS
CVTPI2PSCVTPD2PSCVTPS2PD
CVTPD2DQ CVTDQ2PD
CVTTPD2PICVTP
I2PDCVTSS2SI
CVTSI2SS
CVTSI2SDCVTTSD2SI
CVTSD2SSCVTSS2SDCVTPS2DQ
4 Doubleword
Integer
Floating-PointDoubleword
Integer 2 Doubleword
Integer Single Precision
CVTS
D2SICVTPD2PICVTTPD2DQCVTTPS2PICVTTSS2SI
2 Doubleword
Integer (r32/mem) (MMX/mem)
(XMM/mem)Double Precision (XMM/mem)
(XMM/mem)(XMM/mem)11-10 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
are housed in XMM registers, MMX registers, general re gisters or memory (at most one operand can reside in 
memory; the destination is always an XMM, MMX, or general register).
The CVTPD2PI (convert packed double precision floating-p oint values to packed doubleword integers) instruction 
converts two packed double precision floating-point numb ers to two packed signed doubleword integers, with the 
result stored in an MMX register. When rounding to an in teger value, the source value is rounded according to the 
rounding mode in the MXCSR register. The CVTTPD2PI (conve rt with truncation packed double precision floating-
point values to packed doubleword integers) instruction is  similar to the CVTPD2PI instruction except that trunca-
tion is used to round a source value to an integer value;  see Section 4.8.4.2, “Truncation with Intel® SSE, SSE2, 
and AVX Conversion Instructions.”
The CVTPI2PD (convert packed doubleword integers to pa cked double precision floating-point values) instruction 
converts two packed signed doubleword integers to two double precision floating-point values. 
The CVTPD2DQ (convert packed double precision floating-p oint values to packed doubleword integers) instruction 
result stored in the low quadword of an XMM register. Wh en rounding an integer value, the source value is rounded 
according to the rounding mode selected in the MXCSR register. The CVTTPD2DQ (convert with truncation packed 
double precision floating-point values to packed double word integers) instruction is similar to the CVTPD2DQ 
instruction except that truncation is used to round a sour ce value to an integer value; see Section 4.8.4.2, “Trun-
cation with Intel® SSE, SSE2, and AVX Conversion Instructions.”
The CVTDQ2PD (convert packed doublewo rd integers to packed double precision floating-point values) instruction 
converts two packed signed doubleword integers located in the low-order doublewords of an XMM register to two 
double precision floating-point values. 
The CVTSD2SI (convert scalar double precision floating-poi nt value to doubleword integer) instruction converts a 
double precision floating-point value to a doubleword inte ger, and stores the result in a general-purpose register. 
When rounding an integer value, the source value is ro unded according to the rounding mode selected in the 
MXCSR register. The CVTTSD2SI (convert with truncation sca lar double precision floating-point value to double-
word integer) instruction is similar to the CVTSD2SI instruction except that truncation is used to round the source value to an integer value; see Section 4.8.4.2, “Truncation with Intel® SSE, SSE2, and AVX Conversion Instruc-
tions.”
The CVTSI2SD (convert doubleword integer to scalar double  precision floating-point value) instruction converts a 
signed doubleword integer in a general-purpose register to  a double precision floating-point number, and stores the 
result in an XMM register. 
Conversion between single pr ecision floating-point and do ubleword integer formats —  These instruc-
tions convert between packed single precision floating-poi nt and packed doubleword integer formats. Operands are 
housed in XMM registers, MMX registers, general registers,  or memory (the latter for at most one source operand). 
The destination is always an XMM, MMX, or general register. These SSE2 instructions supplement conversion 
instructions (CVTPI2PS, CVTPS2PI, CVTTPS2PI, CVTSI2SS,  CVTSS2SI, and CVTTSS2SI) introduced with Intel SSE 
The CVTPS2DQ (convert packed single precision floating-p oint values to packed doubleword integers) instruction 
converts four packed single precision floating-point valu es to four packed signed doubleword integers, with the 
source and destination operands in XMM registers or memory (the latter for at most one source operand). When 
the conversion is inexact, the rounde d value according to the rounding mode selected in the MXCSR register is 
returned. The CVTTPS2DQ (convert with truncation packed si ngle precision floating-point values to packed double-
word integers) instruction is similar to the CVTPS2DQ instruction except that truncation is used to round a source 
value to an integer value; see Section 4.8.4.2, “Truncation with Intel® SSE, SSE2, and AVX Conversion Instruc-tions.”
The CVTDQ2PS (convert packed doubleword integers to pa cked single precision floating-point values) instruction 
converts four packed signed doubleword integers to four packed single precision floating-point numbers, with the 
returned. Vol. 1 11-11PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
11.4.2 Intel® SSE2 64-Bit and 128-Bit SIMD Integer Instructions
Intel SSE2 adds several 128-bit packed integer instructio ns to the IA-32 architecture. Where appropriate, a 64-bit 
version of each of these instructions is also provided. Th e 128-bit versions of instructions operate on data in XMM 
registers; 64-bit versions operate on data in MMX registers. The instructions follow.
The MOVDQA (move aligned double quadword) instruction transfers a double quadword operand from memory to 
an XMM register or vice versa; or between XMM registers. The memory address must be aligned to a 16-byte 
boundary; otherwise, a general-protec tion exception (#GP) is generated.
The MOVDQU (move unaligned double quadword) instruct ion performs the same operations as the MOVDQA 
instruction, except that 16-byte alignment of a memory address is not required.
The PADDQ (packed quadword add) instruction adds two pa cked quadword integer operands or two single quad-
word integer operands, and stores the results in an XMM or MMX register, respectively. This instruction can operate 
on either unsigned or signed (two’s complement notation) integer operands.
The PSUBQ (packed quadword subtract) instruction subtract s two packed quadword integer operands or two single 
quadword integer operands, and stores the results in an XMM or MMX register, respectively. Like the PADDQ 
instruction, PSUBQ can operate on either unsigned or signed (two’s complement notation) integer operands.
The PMULUDQ (multiply packed unsigned doubleword inte gers) instruction performs an unsigned multiply of 
unsigned doubleword integers and returns a quadword result . Both 64-bit and 128-bit versions of this instruction 
are available. The 64-bit version operates on two doubleword  integers stored in the low doubleword of each source 
operand, and the quadword result is returned to an MMX  register. The 128-bit version performs a packed multiply 
of two pairs of doubleword integers. Here, the doublewords are packed in th e first and third doublewords of the 
source operands, and the quadword results are stored in the low and high quadwords of an XMM register.
The PSHUFLW (shuffle packed low words) instruction shuffles  the word integers packed into the low quadword of 
the source operand and stores the shuffled result in the low quadword of the destinat ion operand. An 8-bit imme-
diate operand specifies the shuffle order.
The PSHUFHW (shuffle packed high words) instruction shuffles  the word integers packed into the high quadword of 
the source operand and stores the shuffled result in the high quadword of the destination operand. An 8-bit imme-
The PSHUFD (shuffle packed doubleword integers) instruct ion shuffles the doubleword integers packed into the 
source operand and stores the shuffled result in the dest ination operand. An 8-bit immediate operand specifies the 
shuffle order.
The PSLLDQ (shift double quadword left logical) instruction shifts the contents of the source operand to the left by 
the amount of bytes specified by an  immediate operand. The empty low-order bytes are cleared (set to 0).
The PSRLDQ (shift double quadword right logical) instructio n shifts the contents of the source operand to the right 
by the amount of bytes specified by an immediate operan d. The empty high-order bytes are cleared (set to 0).
The PUNPCKHQDQ (Unpack high quadwords) instruction inte rleaves the high quadword of the source operand and

The PUNPCKHQDQ (Unpack high quadwords) instruction inte rleaves the high quadword of the source operand and 
the high quadword of the destination operand and writes them to the destination register.
The PUNPCKLQDQ (Unpack low quadwords) instruction inte rleaves the low quadwords of the source operand and 
the low quadwords of the destination operand and writes them to the destination register.
Two additional SSE instructions enable data moveme nt from the MMX register s to the XMM registers. 
The MOVQ2DQ (move quadword integer from MMX to XMM re gisters) instruction moves the quadword integer from 
an MMX source register to an XMM destination register.
The MOVDQ2Q (move quadword integer fr om XMM to MMX registers) instruction moves the low quadword integer 
from an XMM source register to an MMX destination register. 
11.4.3 128-Bit SIMD Intege r Instruction Extensions
All of 64-bit SIMD integer instructions introduced with  MMX technology and Intel SSE (with the exception of the 
PSHUFW instruction) have been extended  by Intel SSE2 to operate on 128-bi t packed integer operands located in 
XMM registers. The 128-bit versions of these instructio ns follow the same SIMD conventions regarding packed 11-12 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
operands as the 64-bit versions. For example, where the 64-bit version of the PADDB instruction operates on 8 
packed bytes, the 128-bit version operates on 16 packed bytes. 
11.4.4 Cacheability Control and Memory Ordering Instructions
Intel SSE2 instructions that give programs more contro l over the caching, loading, and storing of data. are 
11.4.4.1  FLUSH Cache Line
The CLFLUSH (flush cache line) instruction writes and inva lidates the cache line associated with a specified linear 
address. The invalidation is for all levels of the processo r’s cache hierarchy, and it is broadcast throughout the 
cache coherency domain.
NOTE
CLFLUSH was introduced with Intel SSE2. However,  the instruction can be implemented in IA-32 
processors that do not implement Intel SSE2. Detect CLFLUSH using the feature bit (if 
CPUID.01H:EDX.CLFSH[bit 19] = 1).
11.4.4.2  Cacheability Control Instructions
The following four instructions enable data from XMM and general-purpose registers to be stored to memory using 
a non-temporal hint. The non-temporal hint directs the processor to store data to memory without writing the data 
into the cache hierarchy. See Section 10.4.6.2, “Caching of  Temporal vs. Non-Temporal Data,” for more information 
The MOVNTDQ (store double quadword using non-temporal hint) instruction stores packed integer data from an 
XMM register to memory, using a non-temporal hint.
The MOVNTPD (store packed double precision floating-point values using non-temporal hint) instruction stores 
packed double precision floating-point data from an  XMM register to memory, using a non-temporal hint.
The MOVNTI (store doubleword using non-temporal hint) instruction stores integer data from a general-purpose 
The MASKMOVDQU (store selected bytes of double quadword ) instruction stores selected byte integers from an 
XMM register to memory, using a byte mask to selectively write the individual bytes. The memory location does not 
need to be aligned on a natural boundary. This instruction also uses a non-temporal hint. 
11.4.4.3  Memory Or dering Instructions
Intel SSE2 introduced two fence instructions (LFENCE and MFENCE) as companions to the SFENCE instruction 
introduced with Intel SSE. 
The LFENCE instruction establishes a memory fence for loads. It guarantees ordering between two loads and 
prevents speculative loads from passing the load fence (t hat is, no speculative loads are allowed until all loads 
specified before the load fence have been carried out).
The MFENCE instruction establishes a memory fence for both  loads and stores. The processor ensures that no load 
or store after MFENCE will become globally visible until a ll loads and stores before MFENCE are globally visible.1 
Note that the sequences LFENCE;SFENCE and SFENCE;LFE NCE are not equivalent to MFENCE because neither 
ensures that older stores are globally observed prior to younger loads.
11.4.4.4  Pause
The PAUSE instruction is provided to improve the performanc e of “spin-wait loops” executed on a Pentium 4 or Intel 
Xeon processor. On a Pentium 4 processor, it also provides the added benefit of reducing processor power 
1. A load is considered to become  globally visible when the value to be loaded is determined.Vol. 1 11-13PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
consumption while executing a spin-wait loop. It is recomme nded that a PAUSE instruction always be included in 
the code sequence for a spin-wait loop.
11.4.5 Branch Hints
Intel SSE2 designates two instruction prefixes (2EH an d 3EH) to provide branch hints to the processor (see 
“Instruction Prefixes” in Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2A). These prefixes can only be used with the Jcc instruct ion and only at the machine code level (that is, there are 
no mnemonics for the branch hints).
11.5 INTEL® SSE, SSE2,  AND SSE3 EXCEPTIONS
Intel SSE, SSE2, and SSE3 instructions ge nerate two general types of exceptions:
•Non-numeric exceptions.
•SIMD floating-point exceptions.1
Intel SSE, SSE2, and SSE3 instructions can generate the same type of memory-access and non-numeric excep-
tions as other IA-32 architecture instructions. Existing exception handlers can generally handle these exceptions 
without any code modification. See “Providing Non-Numeri c Exception Handlers for Exceptions Generated by the 
SSE, SSE2, and SSE3 Instructions ” in Chapter 14 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A, for a list of the non-numeric exceptio ns that can be generated by the Intel SSE, SSE2, SSE3 
instructions and for guidelines for handling these exceptions.
Intel SSE, SSE2, and SSE3 instructions do not genera te numeric exceptions on packed integer operations; 
however, they can generate numeric (SIMD floating-point) exceptions on packed single precision and double preci-
sion floating-point operations. These SIMD floating-poi nt exceptions are defined in the IEEE Standard 754 for 
Floating-Point Arithmetic and are the same exceptions that are generated for x87 FPU instructions. See Section 
11.5.1, “SIMD Floating-Point Exceptions,” for a description of these exceptions.
11.5.1 SIMD Floating-Point Exceptions
SIMD floating-point exceptions are those exceptions that can be generated by Intel SSE, SSE2, and SSE3 instruc-
tions that operate on packed or scalar floating-point operands.
Six classes of SIMD floating-point exceptions can be generated:
•Denormal operand (#D).
•Inexact result (Precision) (#P).
All of these exceptions (except the denormal operand exce ption) are defined in IEEE Standard 754, and they are 
the same exceptions that are generated with the x87 fl oating-point instructions. Section 4.9, “Overview of 
Floating-Point Exceptions,” gives a detailed description of  these exceptions and of how and when they are gener-
ated. The following sections discuss the implementation of these exceptions in the Intel SSE/SSE2/SSE3 exten-sions.
All SIMD floating-point exceptions are precise and occur as soon as the instruction completes execution.
1. The FISTTP instruction in Intel SSE3 does not generate SIMD floating-point exceptions, but it can generate x87 FPU floating-p oint 
exceptions.11-14 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
Each of the six exception conditions has a corresponding flag (IE, DE, ZE, OE, UE, and PE) and mask bit (IM, DM, 
ZM, OM, UM, and PM) in the MXCSR register (see Figure 10- 3). The mask bits can be set with the LDMXCSR or 
FXRSTOR instruction; the mask and flag bits can be read with the STMXCSR or FXSAVE instruction.
The OSXMMEXCEPT flag (bit 10) of control register CR4 provides additional control over generation of SIMD 
floating-point exceptions by allowing the operating system to indicate whether or not it supports software excep-
tion handlers for SIMD floating-point exceptions. If an  unmasked SIMD floating-point exception is generated and 
the OSXMMEXCEPT flag is set, the processor invokes a soft ware exception handler by generating a SIMD floating-
point exception (#XM). If the OSXMMEXCEPT bit is clear,  the processor generates an invalid-opcode exception 
(#UD) on the first Intel SSE or SSE2 instruction that dete cts a SIMD floating-point exception condition. See Section 
11.6.2, “Checking for Intel® SSE and SSE2 Support.”
11.5.2 SIMD Floating-Point Exception Conditions
The following sections describe the conditions that cause a SIMD floating-point except ion to be generated and the 
masked response of the processor wh en these conditions are detected.

masked response of the processor wh en these conditions are detected. 
11.5.2.1  Invalid Op eration Exception (#I)
The floating-point invalid-operation exception (#I) occurs in response to an invalid arithmetic operand. The flag 
(IE) and mask (IM) bits for the invalid operation exception are bits 0 and 7, respectively, in the MXCSR register.
If the invalid-operation exception is masked, the processor returns a QNaN, QNaN floating-point indefinite, integer 
indefinite, one of the source operands to the destination op erand, or it sets the EFLAGS , depending on the operation 
being performed. When a value is returned to the destination operand, it overwrites the destination register specified 
by the instruction. Table 11-1 lists the invalid-arithmetic operations that the processor detects for instructions and the masked responses to these operations.
Table 11-1.  Masked Responses of Intel® SSE, SSE2, an d SSE3 Instructions to Inva lid Arithmetic Operations
ADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD, 
MULPS, MULSS, MULPD, MULSD, DIVPS, DIVSS, DIVPD, DIVSD, ADDSUBPD, ADDSUBPD, HADDPD, HADDPS, HSUBPD or HSUBPS 
instruction with an SNaN operandReturn the SNaN converted to a QNaN; Refer to Table 4-7 for 
SQRTPS, SQRTSS, SQRTPD, or SQRTSD with SNaN operands Return the SNaN converted to a QNaN.
SQRTPS, SQRTSS, SQRTPD, or SQRTSD with negative operands 
(except zero)Return the QNaN floati ng-point Indefinite.
MAXPS, MAXSS, MAXPD, MAXSD, MINPS, MINSS, MINPD, or 
MINSD instruction with QNaN or SNaN operandsReturn the source 2 operand value.
CMPPS, CMPSS, CMPPD or CMPSD in struction with QNaN or SNaN 
operandsReturn a mask of all 0s (except for the predicates “not-equal,” 
“unordered,” “not-less-than,” or “not-less-than-or-equal,” which 
returns a mask of all 1s).
CVTPD2PS, CVTSD2SS, CVTPS2PD, CVTSS2SD with SNaN 
operandsReturn the SNaN converted to a QNaN.
COMISS or COMISD with QNaN or SNaN operand(s) Set EFLAGS values to “not comparable.”
Addition of opposite signed infinities or subtraction of like-signed 
infinitiesReturn the QNaN floati ng-point Indefinite.
Multiplication of  infinity by zero Return the QN aN floating-point Indefinite.
Divide of (0/0) or (
∞/∞) Return the QNaN floating-point Indefinite.Vol. 1 11-15PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
If the invalid operation exception is not masked, a softwa re exception handler is invoked and the operands remain 
unchanged. See Section 11.5.4, “Handling SIMD  Floating-Point Exceptions in Software.”
Normally, when one or more of the source operands are QNaNs (and neither is an SNaN or in an unsupported 
format), an invalid-operation exception is not generated. Th e following instructions are exceptions to this rule: the 
COMISS and COMISD instructions; and the CMPPS, CMPSS,  CMPPD, and CMPSD instructions (when the predicate 
is less than, less-than or equal, not less-than, or not less-than or equal). With these instructions, a QNaN source 
operand will generate an invalid-operation exception.
The invalid-operation exception is not affected by the flush-to-zero mode or by the denormals-are-zeros mode.
11.5.2.2  Denormal-Operand Exception (#D)
The processor signals the denormal-operand exception if an arithmetic instruction attempts to operate on a 
denormal operand. The flag (DE) and ma sk (DM) bits for the denormal-operand exception are bits 1 and 8, respec-
tively, in the MXCSR register.
The CVTPI2PD, CVTPD2PI, CVTTPD2PI, CVTDQ2PD, CVTPD2DQ, CVTTPD2DQ, CVTSI2SD, CVTSD2SI, CVTTSD2SI, 
CVTPI2PS, CVTPS2PI, CVTTPS2PI, CVTSS2SI, CVTTSS2SI, CVTSI2SS, CVTDQ2PS, CVTPS2DQ, and CVTTPS2DQ conversion instructions do not signal denormal except ions. The RCPSS, RCPPS, RSQRTSS, and RSQRTPS instruc-
tions do not signal any kind of floating-point exception.
The denormals-are-zero flag (bit 6) of the MXCSR regist er provides an additional option for handling denormal-
operand exceptions. When this flag is set, denormal sour ce operands are automatically converted to zeros with the 
sign of the source operand (see Section 10.2.3.4, “Denor mals-Are-Zeros”). The denormal operand exception is not 
affected by the flush-to-zero mode.
See Section 4.9.1.2, “Denormal Operand Exception (#D),”  for more information about the denormal exception. 
See Section 11.5.4, “Handling SIMD Floating-Point Exceptio ns in Software,” for information on handling unmasked 
11.5.2.3  Divide-By- Zero Exception (#Z)
The processor reports a divide-by-zero exception when a DIVPS, DIVSS, DIVPD or DIVSD instruction attempts to 
divide a finite non-zero operand by 0. The flag (ZE) and mask (ZM) bits for the divide-by-zero exception are bits 2 
and 9, respectively, in the MXCSR register.
See Section 4.9.1.3, “Divide-By-Zero Exception (#Z),” fo r more information about the divide-by-zero exception. 
The divide-by-zero exception is not affected by the flush-to-zero mode at a single-instruction boundary.
While DAZ does not affect the rules for signaling IEEE ex ceptions, operations on denormal inputs might have 
different results when DAZ=1. As a consequence, DAZ can have an effect on the floating-point exceptions - 
including the divide-by-zero exception - when observ ed for a given operation involving denormal inputs.
11.5.2.4  Numeric Ov erflow Exception (#O)
The processor reports a numeric overflow exception whenev er the rounded result of an arithmetic instruction 
exceeds the largest allowable finite value that fits in the destination operand. This exception can be generated with 
the ADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD, MULPS, MULSS, MULPD, MULSD, DIVPS, DIVSS, DIVPD, DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS, HADDPD, HADDPS, HSUBPD, and Conversion to integer when the valu e in the source register is a 
NaN, 
∞, or exceeds the representable range for CVTPS2PI, 
CVTTPS2PI, CVTSS2SI, CVTTSS2SI, CVTPD2PI, CVTSD2SI, 
CVTPD2DQ, CVTTPD2PI, CVTTS D2SI, CVTTPD2DQ, CVTPS2DQ, 
or CVTTPS2DQReturn the inte ger Indefinite.Table 11-1.  Masked Responses of Inte l® SSE, SSE2, and SSE3 Instru ctions to Invalid Arithm etic Operations (Contd.)
Condition Masked Response11-16 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
HSUBPS instructions. The flag (OE) and mask (OM) bits  for the numeric overflow exception are bits 3 and 10, 
respectively, in the MXCSR register.
See Section 4.9.1.4, “Numeric Overflow Exception (#O),”  for more information about the numeric-overflow excep-
tion. See Section 11.5.4, “Handling SIMD Floating-Point Exceptions in Software,” for information on handling 
unmasked exceptions.
The numeric overflow exception is not affected by the flush-to-zero mode or by the denormals-are-zeros mode.
11.5.2.5  Numeric Underflow Exception (#U)
The processor reports a numeric underflow exception whenev er the magnitude of the rounded result of an arith-
metic instruction, with unbounded exponent, is less than th e smallest possible normalized, finite value that will fit 
in the destination operand and the numeric-underflow exception is not masked. If the numeric underflow exception is masked, both underflow and the inexact-result condition must be detected before numeric underflow is reported. 
This exception can be generated with the ADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD, 
MULPS, MULSS, MULPD, MULSD, DIVPS, DIVSS, DIVPD, DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS, HADDPD, HADDPS, HSUBPD, and HSUBPS instructions. The fl ag (UE) and mask (UM) bits for the numeric under-
flow exception are bits 4 and 11, respectively, in the MXCSR register.
The flush-to-zero flag (bit 15) of the MXCSR register prov ides an additional option for handling numeric underflow 
exceptions. When this flag is set and the numeric underflow exception is masked, tiny results are returned as a zero 
with the sign of the true result; see Section 10.2.3.3, “Flush-To-Zero.”
Underflow will occur when a tiny non-zero result is detect ed (the result has to be also inexact if underflow excep-
tions are masked), as described in th e IEEE Standard 754-2008. While DAZ does not affect the rules for signaling 
IEEE exceptions, operations on denormal inputs might ha ve different results when DAZ=1. As a consequence, DAZ 
can have an effect on the floating-point exceptions - in cluding the underflow exception - when observed for a given 
operation involving denormal inputs.
See Section 4.9.1.5, “Numeric Underflow Exception (#U) ,” for more information about the numeric underflow 
exception. See Section 11.5.4, “Handling SIMD Floating-Point  Exceptions in Software,” for information on handling 
11.5.2.6  Inexact-Result (Precision) Exception (#P)

form. This exception occurs frequently and indicates that some (normally acceptable) accuracy has been lost. The 
exception is supported for applications that need to perf orm exact arithmetic only. Because the rounded result is 
generally satisfactory for most applications, this exception is commonly masked.
The flag (PE) and mask (PM) bits for the inexact-result  exception are bits 5 and 12, respectively, in the MXCSR 
register.
See Section 4.9.1.6, “Inexact-Result (Precision) Exceptio n (#P),” for more information about the inexact-result 
In flush-to-zero mode, the inexact result exception is reported. 
11.5.3 Generating SIMD Floating-Point Exceptions
When the processor executes a packed or scalar floating-point instruction, it looks for and reports on SIMD 
floating-point exception conditions using two sequential steps:
1. Looks for, reports on, and handles pre-computation exce ption conditions (invalid-operand, divide-by-zero, and 
denormal operand)
2. Looks for, reports on, and handles post-computation exception conditions (numeric overflow, numeric 
underflow, and inexact result)Vol. 1 11-17PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
If both pre- and post-computational exceptions are unmask ed, it is possible for the processor to generate a SIMD 
floating-point exception (#XM) twice during the execution of an SSE, SSE2 or SSE3 instruction: once when it 
detects and handles a pre-computational exception an d when it detects a post-computational exception.
11.5.3.1  Handling Masked Exceptions
If all exceptions are masked, the processor handles the exceptions it detects by placing the masked result (or 
results for packed operands) in a destination operand and continuing program execution. The masked result may be a rounded normalized value, signed infinity, a denormal finite number, zero, a QNaN floating-point indefinite, or 
a QNaN depending on the exception condition detected. In  most cases, the corresponding exception flag bit in 
MXCSR is also set. The one situation where an exception flag is not set is when an underflow condition is detected and it is not accompanied by an inexact result.
When operating on packed floating-point operands, the processor returns a masked result for each of the sub-
operand computations and sets a separate set of internal exception flags for each computation. It then performs a 
logical-OR on the internal exception flag settings and sets  the exception flags in the MXCSR register according to 
the results of OR operations.
For example, Figure 11-9 shows the results of an MULPS inst ruction. In the example, all SIMD floating-point excep-
tions are masked. Assume that a denormal exception conditio n is detected prior to the multiplication of sub-oper-
ands X0 and Y0, no exception condition is detected fo r the multiplication of X1 and Y1, a numeric overflow 
exception condition is detected for the multiplication of  X2 and Y2, and another denormal exception is detected 
prior to the multiplication of sub-operands X3 and Y3 . Because denormal exceptions are masked, the processor 
uses the denormal source values in the multiplications of  (X0 and Y0) and of (X3 and Y3) passing the results of the 
multiplications through to the destination operand. With th e denormal operand, the result of the X0 and Y0 compu-
tation is a normalized finite value, with no exceptions  detected. However, the X3 and Y3 computation produces a 
tiny and inexact result. This causes the corresponding internal numeric underflow an d inexact-result exception 
flags to be set.
For the multiplication of X2 and Y2, the processor stores the floating-point ∞ in the destination operand, and sets 
the corresponding internal sub-operand numeric overflow flag. The result of the X1 and Y1 multiplication is passed 
through to the destination operand, with no internal su b-operand exception flags being set. Following the compu-
tations, the individual sub-operand exceptions flags for denormal operand, numeric underflow, inexact result, and 
numeric overflow are OR’d and the corresponding flags are set in the MXCSR register.
The net result of this computation is that:
•Multiplication of X0 and Y0 produces a normalized finite result
•Multiplication of X1 and Y1 produces a normalized finite result
•Multiplication of X2 and Y2 produces a floating-point ∞ result
•Multiplication of X3 and Y3 produces a tiny, inexact, finite resultFigure 11-9.  Example Masked Response for Packed OperationsX3 X2 X1 X0 (Denormal)
Y3 (Denormal) Y2 Y1 Y0 
Tiny, Inexact, Finite Normalized FiniteMULPS MULPS MULPS MULPS
∞ Normalized Finite11-18 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
•Denormal operand, numeric underflow, numeric underfl ow, and inexact result flags are set in the MXCSR 
register
11.5.3.2  Handling Unmasked Exceptions
If all exceptions are unmasked, the processor:
1. First detects any pre-computation exceptions: it ORs those exceptions, sets the appropriate exception flags, 
leaves the source and destination operands unaltered, and goes to step 2. If it does not detect any pre-
computation exceptions, it goes to step 5.
2. Checks CR4.OSXMMEXCPT[bit 10]. If this flag is set, the processor goes to step 3; if the flag is clear, it 
generates an invalid-opcode exception (#UD) and makes an implicit call to the invalid-opcode exception 
handler.
3. Generates a SIMD floating-point exception (#XM) and makes an implicit call to the SIMD floating-point 
4. If the exception handler is able to fix the source op erands that generated the pre-computation exceptions or 
mask the condition in such a way as to allow the processor to continue executing the instruction, the processor 
resumes instruction execution as described in step 5.
5. Upon returning from the exception handler (or if no pr e-computation exceptions were detected), the processor 
checks for post-computation exceptions. If the processor detects any post-computation exceptions: it ORs 
those exceptions, sets the appropriate exception flags, leaves the source and destination operands unaltered, 
and repeats steps 2, 3, and 4.
6. Upon returning from the exceptions handler in step 4 (o r if no post-computation exceptions were detected), the 
processor completes the execution of the instruction.
The implication of this procedure is that for unmasked exceptions, the processor can generate a SIMD floating-
point exception (#XM) twice: once if it detects pre-computat ion exception conditions and a second time if it detects 
post-computation exception conditions. For example, if SIMD floating-point exceptions are unmasked for the 
computation shown in Figure 11-9, the processor would gene rate one SIMD floating-point exception for denormal 
operand conditions and a second SIMD floating-point ex ception for overflow and underflow (no inexact result 
exception would be generated because the multiplicatio ns of X0 and Y0 and of X1 and Y1 are exact).
11.5.3.3  Handling Combinations of Masked and Unmasked Exceptions
In situations where both masked and unmasked exceptions  are detected, the processor will set exception flags for 
the masked and the unmasked exceptions. However, it will not return masked results until after the processor has 
detected and handled unmasked post-computation exceptions  and returned from the exception handler (as in step 
6 above) to finish executing the instruction.
11.5.4 Handling SIMD Floating-P oint Exceptions in Software
Section 4.9.3, “Typical Actions of a Fl oating-Point Exception Handler,” shows actions that may be carried out by a 
SIMD floating-point exception handler. The SSE/SSE2/SSE3 state is saved with the FXSAVE instruction; see Section 
11.6.5, “Saving and Restoring the SSE/SSE2 State.”
11.5.5 Interaction of SIMD and x87 FPU Floating-Point Exceptions
SIMD floating-point exceptions are generated independently from x87 FPU floating-point exceptions. SIMD 
floating-point exceptions do not cause assertion of the FERR# pin (independent of the value of CR0.NE[bit 5]). 
They ignore the assertion and deassertion of the IGNNE# pin.
If applications use Intel SSE/SSE2/SSE3 instructions al ong with x87 FPU instructions (in the same task or 
program), consider the following:
•SIMD floating-point exceptions are reported independen tly from the x87 FPU floating-point exceptions. SIMD 
and x87 FPU floating-point exceptions can be unmasked independently. Separate x87 FPU and SIMD floating-Vol. 1 11-19PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)

point exception handlers must be provided if the same exception is unmasked for x87 FPU and for Intel 
SSE/SSE2/SSE3 operations.
•The rounding mode specified in the MXCSR register does not affect x87 FPU instructions. Likewise, the rounding mode specified in the x87 FPU control word does  not affect the Intel SSE/SSE2/SSE3 instructions. To 
use the same rounding mode, the rounding control bits in  the MXCSR register and in the x87 FPU control word 
must be set explicitly to the same value.
•The flush-to-zero mode set in the MXCSR register for Intel SSE/SSE2/SSE3 instructions has no counterpart in the x87 FPU. For compatibility with the x87 FPU, set the flush-to-zero bit to 0.
•The denormals-are-zeros mode set in the MXCSR register for Intel SSE/SSE2/SSE3 instructions has no 
counterpart in the x87 FPU. For compatibility with the x87 FPU, set the denormals-are-zeros bit to 0.
•An application that expects to detect x87 FPU exceptio ns that occur during the execution of x87 FPU instruc-
tions will not be notified if exceptions occurs during the execution of corresponding Intel SSE/SSE2/SSE31 
instructions, unless the exception masks that are enabled in the x87 FPU control word have also been enabled 
in the MXCSR register and the application is capabl e of handling SIMD floating -point exceptions (#XM).
— Masked exceptions that occur during an SSE/SSE2/SSE 3 library call cannot be detected by unmasking the 
exceptions after the call (in an attempt to generate the fault based on the fact that an exception flag is set). 
A SIMD floating-point exception flag that is set when the corresponding exception is unmasked will not 
generate a fault; only the next occurrence of that unmasked exception will generate a fault.
— An application which checks the x87 FPU status word to determine if any masked exception flags were set 
during an x87 FPU library call will also need to check the MXCSR register to detect a similar occurrence of a 
masked exception flag being set during an SSE/SSE2/SSE3 library call.
11.6 WRITING APPLICATIONS WITH INTEL® SSE AND SSE2 
The following sections give some guidelines for writing a pplication programs and operating-system code that uses 
Intel SSE and SSE2. Because Intel SSE and SSE2 share th e same state and perform companion operations, these 
guidelines apply to both sets of extensions.
Chapter 14 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, discusses the inter-
face to the processor for context switching as well as othe r operating system considerations when writing code that 
uses Intel SSE, SSE2, and SSE3.
11.6.1 General Guidelines for  Using Intel® SSE and SSE2
The following guidelines describe how to take full advant age of the performance gains available with Intel SSE and 
SSE2:
•Ensure that the processor su pports Intel SSE and SSE2.
•Ensure that your operating system supports Intel SSE and SSE2. (Operating system support for Intel SSE 
implies support for Intel SSE2, and vice versa.)
•Use stack and data alignment techniques to keep data properly aligned for efficient memory use.
•Use the non-temporal store instructions offered with Intel SSE and SSE2.
•Employ the optimization and scheduling techniques describ ed in the Intel® 64 and IA-32 Architectures Optimi-
zation Reference Manual; see Section 1.4, “Related Literature,” for the order number for this manual.
11.6.2 Checking for Intel® SSE and SSE2 Support
Before an application attempts to use Intel SSE and/or In tel SSE2, it should check that they are present on the 
processor:
1. Intel SSE3 refers to ADDSUBPD, ADDSUBPS, HADDPD, HADDPS, HS UBPD, and HSUBPS. The only othe r Intel SSE3 instruction that 
can raise floating-point exceptions is FISTTP; it can genera te x87 FPU invalid operation and inexact result exceptions.11-20 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
1. Check that the processor supports the CPUID instruction.  Bit 21 of the EFLAGS register can be used to check 
processor’s support the CPUID instruction. 
2. Check that the processor supports Intel SSE and/or SSE2 (true if CPUID.01H:EDX.SSE[bit 25] = 1 and/or 
CPUID.01H:EDX.SSE2[bit 26] = 1).
The operating system must provide system level support fo r handling SSE state, exceptions before an application 
can use Intel SSE and/or Intel SS E2; see Chapter 14 in the Intel® 64 and IA-32 Architectures Software Developer’s 
If the processor attempts to execute an unsupported Intel SSE or SSE2 instruction, the processor will generate an 
invalid-opcode exception (#UD). If an operating system did not provide adequate system level support for Intel 
SSE, executing an Intel SSE or SSE2 instructions can also generate #UD.
11.6.3 Checking for the DAZ Flag in the MXCSR Register
The denormals-are-zero flag in the MXCSR register is availa ble in most of the Pentium 4 processors and in the Intel 
Xeon processor, with the exception of some early steppings.  To check for the presence of the DAZ flag in the MXCSR 
register, do the following:
1. Establish a 512-byte FXSAVE area in memory.
2. Clear the FXSAVE area to all 0s.3. Execute the FXSAVE instruction, using the address of th e first byte of the cleared FXSAVE area as a source 
operand. See “FXSAVE—Save x87 FPU, MMX, SSE, and SSE2 State” in Chapter 3 of the Intel
Architectures Software Developer’s Manual, Volume 2A, for a description of the FXSAVE instruction and the 
layout of the FXSAVE image.
4. Check the value in the MXCSR_MASK field in the FXSAVE image (bytes 28 through 31).
— If the value of the MXCSR_MASK field is 00000000H, the DAZ flag and denormals-are-zero mode are not 
— If the value of the MXCSR_MASK field is non-zero an d bit 6 is set, the DAZ flag and denormals-are-zero 
mode are supported.
If the DAZ flag is not supported, then  it is a reserved bit and attempting to write a 1 to it will cause a general-
protection exception (#GP). See Section 11.6.6, “Guidelines for Writing to the MXCSR Register,” for general guide-
lines for preventing general-protection exce ptions when writing to the MXCSR register.
11.6.4 Initialization of Intel® SSE and SSE2
The SSE and SSE2 state is contained in the XMM and MXCSR re gisters. Upon a hardware reset of the processor, this 
state is initialized as follows (see Table 11-2):
•All SIMD floating-point exceptions are masked (bits 7 through 12 of the MXCSR register is set to 1).
•All SIMD floating-point exception flags are cleared (b its 0 through 5 of the MXCSR register is set to 0).
•The rounding control is set to round-nearest (bits 13 and 14 of the MXCSR register are set to 00B).
•The flush-to-zero mode is disabled (bit 15 of the MXCSR register is set to 0).
•The denormals-are-zeros mode is disabled (bit 6 of the MXCSR register is set to 0). If the denormals-are-zeros 
mode is not supported, this bit is reserved and will be set to 0 on initialization.
•Each of the XMM registers is cleared (set to all zeros).
If the processor is reset by asserting the INIT # pin, the SSE and SSE2 state is not changed.Table 11-2.  SSE and SSE2 State Fo llowing a Power-up/Reset or INIT
Registers Power-Up or Reset INIT
XMM0 through XMM7 +0.0 Unchanged
MXCSR 1F80H UnchangedVol. 1 11-21PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
11.6.5 Saving and Restoring the SSE/SSE2 State
The FXSAVE instruction saves the x87 FPU, MMX, SSE, and SSE2 states (which includes the contents of eight XMM 
registers and the MXCSR registers) in a 512-byte block of memory. The FXRSTOR instruction restores the saved 
SSE and SSE2 state from memory. See the FXSAVE instruction in Chapter 3 of the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 2A, for the layout of the 512-byte state block.
In addition to saving and restoring the SSE and SSE2 st ate, FXSAVE and FXRSTOR also save and restore the x87 
FPU state (because MMX registers are aliased to the x87 FP U data registers this includes saving and restoring the 
MMX state). For greater code efficiency, it is suggested that FXSAVE and FXRSTOR be substituted for the FSAVE, 
FNSAVE, and FRSTOR instructions in the following situations:
•When a context switch is being made in a multitasking environment
•During calls and returns from interrupt and exception handlers
In situations where the code is swit ching between x87 FPU and MMX technology computations (without a context 
switch or a call to an interrupt or exception), the FSAVE/FNSAVE and FRSTOR instructions are more efficient than the FXSAVE and FXRSTOR instructions.
11.6.6 Guidelines for Writing to the MXCSR Register
The MXCSR has several reserved bits, and attempting to writ e a 1 to any of these bits will cause a general-protec-
tion exception (#GP) to be generated. To allow software to identify these reserved bi ts, the MXCSR_MASK value is 
provided. Software can determine this mask value as follows:
1. Establish a 512-byte FXSAVE area in memory.2. Clear the FXSAVE area to all 0s.

3. Execute the FXSAVE instruction, using the address of th e first byte of the cleared FXSAVE area as a source 
Architectures Software Developer’s Ma nual, Volume 2A, for a description of FXSAVE and the layout of the 
FXSAVE image.
— If the value of the MXCSR_MASK field is 00000000H, th en the MXCSR_MASK value is the default value of 
0000FFBFH. Note that this value indicates that bit 6 of the MXCSR register is reserved; this setting indicates 
that the denormals-are-zero mode is not supported on the processor.
— If the value of the MXCSR_MASK field is non-zero , the MXCSR_MASK value should be used as the 
MXCSR_MASK.
All bits set to 0 in the MXCSR_MASK value indicate reserv ed bits in the MXCSR register. Thus, if the MXCSR_MASK 
value is AND’d with a value to be written into the MXCSR register, the resulting value will be assured of having all 
its reserved bits set to 0, preventing the possibility of  a general-protection exception being generated when the 
value is written to the MXCSR register. 
For example, the default MXCSR_MASK value when 00000000H  is returned in the FXSAVE image is 0000FFBFH. If 
software AND’s a value to be written to MXCSR register wi th 0000FFBFH, bit 6 of the result (the DAZ flag) will be 
ensured of being set to 0, which is the required setting to  prevent general-protection exceptions on processors that 
do not support the denormals-are-zero mode.
To prevent general-protection exceptions, the MXCSR_MASK  value should be AND’d with the value to be written 
into the MXCSR register in the following situations:
•Operating system routines that receive a parameter from  an application program and then write that value to 
the MXCSR register (either with an  FXRSTOR or LDMXCSR instruction)
•Any application program that writes to the MXCSR register  and that needs to run robustly on several different 
IA-32 processors
Note that all bits in the MXCSR_MASK value that are set to 1 indicate features that  are supported by the MXCSR 
register; they can be treated as feature flags for identifying processor capabilities.11-22 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
11.6.7 Interaction of Intel® SSE and SSE2 Inst ructions with x87 FPU and MMX Instructions
The XMM registers and the x87 FPU and MMX registers re present separate execution environments, which has 
certain ramifications when executing Intel SSE, SSE2, MMX,  and x87 FPU instructions in the same code module or 
when mixing code modules that contain these instructions:
•Those Intel SSE and SSE2 instructions that operate on ly on XMM registers (such as the packed and scalar 
floating-point instructions and the 128-bit SIMD integer instructions) in the same instruction stream with 64-
bit SIMD integer or x87 FPU instructions without any re strictions. For example, an application can perform the 
majority of its floating-point computations in the X MM registers, using the packed  and scalar floating-point 
instructions, and at the same time use the x87 FPU to perfor m trigonometric and other transcendental compu-
tations. Likewise, an application can perform packed 64-bit and 128-bit SIMD integer operations together 
without restrictions.
•Those Intel SSE and SSE2 instructions that operate on MMX registers (such as the CVTPS2PI, CVTTPS2PI, 
CVTPI2PS, CVTPD2PI, CVTTPD2PI, CVTPI2PD, MOVDQ2Q, MOVQ2DQ, PADDQ, and PSUBQ instructions) can 
also be executed in the same instruction stream as 64-bit SIMD integer or x87 FPU instructions, however, here 
they are subject to the restrictions on the simultaneous use of MMX technology and x87 FPU instructions, which include:
— Transition from x87 FPU to MMX technology instructions or to Intel SSE or SSE2 instructions that operate on 
MMX registers should be preceded by  saving the state of the x87 FPU.
— Transition from MMX technology instructions or from Intel SSE or SSE2 instructions that operate on MMX 
registers to x87 FPU instructions should be pr eceded by execution of the EMMS instruction.
11.6.8 Compatibility of SIMD and x 87 FPU Floating-Point Data Types
Intel SSE and SSE2 instructions operate on the same single  precision and double precision floating-point data types 
that the x87 FPU operates on. However, when operating on  these data types, Intel SSE and SSE2 operate on them 
in their native format (single precision or double precision), in contrast to the x87 FPU which extends them to 
double extended precision floating-point format to perf orm computations and then rounds the result back to a 
single precision or double precision format before writ ing results to memory. Because the x87 FPU operates on a 
higher precision format and then rounds the result to a lower precision format, it may return a slightly different 
result when performing the same operation on the same si ngle precision or double precision floating-point values 
than is returned by Intel SSE and SSE2. The difference occu rs only in the least-significant bits of the significand.
11.6.9 Mixing Packed and Scalar Floating-Point  and 128-Bit SIMD Integer Instructions and 
Data
Intel SSE and SSE2 define typed operations on packed an d scalar floating-point data types and on 128-bit SIMD 
integer data types, but IA-32 processors do not enforce this  typing at the architectural level. They only enforce it 
at the microarchitectural level. Therefore, when a Pentium 4 or Intel Xeon processor loads a packed or scalar floating-point operand or a 128-bit packed integer operan d from memory into an XMM register, it does not check 
that the actual data being loaded matches the data type specified in the instruction. Likewise, when the processor 
performs an arithmetic operation on the data in an XMM re gister, it does not check that the data being operated on 
matches the data type specified in the instruction.
As a general rule, because data typing of SIMD floating-p oint and integer data types is not enforced at the archi-
tectural level, it is the responsibility of the programmer, a ssembler, or compiler to ensure that code enforces data 
typing. Failure to enforce correct data typing can le ad to computations that return unexpected results.
For example, in the following code sa mple, two packed single precision floating-point operands are moved from 
memory into XMM registers (using MOVAPS instructions); th en a double precision packed add operation (using the 
ADDPD instruction) is performed on the operands:
movaps xmm0, [eax] ; EAX register contains pointer to packed 
; single precision floating-point operand
movaps xmm1, [ebx]addpd xmm0, xmm1Vol. 1 11-23PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
Pentium 4 and Intel Xeon processors execute these instructions without generating an invalid-operand exception 
(#UD) and will produce the expected results in register XMM0  (that is, the high and low 64-bits of each register will 
be treated as a double precision floating-point value and the processor will operate on them accordingly). Because 
the data types operated on and the data  type expected by the ADDPD instruction were inconsistent, the instruction 
may result in a SIMD floating-point exception (such as numeric overflow [#O] or invalid operation [#I]) being 
generated, but the actual source of the proble m (inconsistent data types) is not detected.
The ability to operate on an operand that contains a data ty pe that is inconsistent with the typing of the instruction 
being executed, permits some valid operations to be perf ormed. For example, the following instructions load a 
packed double precision floating-point operand from memory  to register XMM0, and a mask to register XMM1; then 
they use XORPD to toggle the sign bits of  the two packed values in register XMM0.
movapd xmm0, [eax] ; EAX register  contains pointer to packed 
; double precision floating-point operand
movaps xmm1, [ebx] ; EBX register contains pointer to packed
; double precision floating-point mask
xorpd xmm0, xmm1 ; XOR operation toggles sign bits using 
; the mask in xmm1
In this example: XORPS or PXOR can be used in place of XORPD and yield the same correct result. However, 
because of the type mismatch between the operand data type and the instruction data type, a latency penalty will 
be incurred due to implementations of the instructions at the microarchitecture level. 
Latency penalties can also be incurred by using move in structions of the wrong type . For example, MOVAPS and 
MOVAPD can both be used to move a packed single prec ision operand from memory to an XMM register. However, 
if MOVAPD is used, a latency penalty will be incurred when a correctly typed instruction attempts to use the data in 
the register.
Note that these latency penalties are not incurred when moving data from XMM registers to memory.

11.6.10 Interfacing with Intel® SSE and SSE2 Procedures and Functions
Intel SSE and SSE2 allow direct access to XMM registers.  This means that all existing interface conventions 
between procedures and functions that apply to the use of the general-purpose registers (EAX, EBX, etc.) also 
apply to XMM register usage.
11.6.10.1  Passing Parameters in XMM Registers
The state of XMM registers is preserved across procedure (o r function) boundaries. Parameters can be passed from 
one procedure to another using XMM registers.
11.6.10.2  Saving XMM Register State on a Procedure or Function Call
The state of XMM registers can be saved in two ways: usin g an FXSAVE instruction or a move instruction. FXSAVE 
saves the state of all XMM registers (along with the state of MXCSR and the x87 FPU registers). This instruction is 
typically used for major changes in the context of the execution environment, such as a task switch. FXRSTOR 
restores the XMM, MXCSR, and x87 FPU registers stored with FXSAVE.
In cases where only XMM registers must be saved, or where selected XMM registers need to be saved, move 
instructions (MOVAPS, MOVUPS, MOVSS, MOVAPD, MO VUPD, MOVSD, MOVDQA, and MOVDQU) can be used. 
These instructions can also be used to restore the contents of XMM registers. To avoid performance degradation when saving XMM registers to memory or when loading X MM registers from memory, be sure to use the appropri-
ately typed move instructions.
The move instructions can also be used to save the contents of XMM registers on the stack. Here, the stack pointer 
(in the ESP register) can be used as the memory address to the next available byte in the stack. Note that the stack 
pointer is not automatically incremented when us ing a move instruction (as it is with PUSH). 11-24 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
A move-instruction procedure that saves the contents of an XMM register to the stack is responsible for decre-
menting the value in the ESP register by 16. Likewise, a move-instruction procedure that loads an XMM register 
from the stack needs also to increment the ESP register by 16. To avoid performance degradation when moving the 
contents of XMM registers, use the appropriately typed move instructions.
Use the LDMXCSR and STMXCSR instructions  to save and restore, respectively, the contents of the MXCSR register 
on a procedure call and return.
11.6.10.3  Caller-Save Recommendation for Procedure and Function Calls
When making procedure (or function) calls from SSE or SSE2 code, a caller-save convention is recommended for 
saving the state of the calling procedure. Using this co nvention, any register whose content must survive intact 
across a procedure call must be stored in memory by  the calling procedure prior to executing the call. 
The primary reason for using the caller-save convention is  to prevent performance degradation. XMM registers can 
contain packed or scalar double precision floating-point, pa cked single precision floating-point, and 128-bit packed 
integer data types. The called procedure has no way of knowing the data types in XMM registers following a call; so it is unlikely to use the correctly typed move instruction to store the contents of XMM registers in memory or to 
restore the contents of XMM registers from memory. 
As described in Section 11.6.9, “Mixing Packed and Scalar  Floating-Point and 128-Bit SIMD Integer Instructions 
and Data,” executing a move instruction that does not match the type for the data being moved to/from XMM regis-ters will be carried out correctly, but can lead to a greater instruction latency.
11.6.11 Updating Existing MMX Technology Ro utines Using 128-Bit SIM D Integer Instructions
Intel SSE2 extends all 64-bit MMX SIMD integer instructio ns to operate on 128-bit SIMD integers using XMM regis-
ters. The extended 128-bit SIMD integer instructions operat e like the 64-bit SIMD integer instructions; this simpli-
fies the porting of MMX technology applications. However, there are considerations:
•To take advantage of wider 128-bit SIMD integer inst ructions, MMX technology code must be recompiled to 
reference the XMM registers instead of MMX registers.
•Computation instructions that reference memory operan ds that are not aligned on 16-byte boundaries should 
be replaced with an unaligned 128-bit load (MOVUD Q instruction) followed by a version of the same 
computation operation that uses register instead of  memory operands. Use of 128-bit packed integer 
computation instructions with memory operands that ar e not 16-byte aligned results in a general protection 
•Extension of the PSHUFW instruction (shuffle word acro ss 64-bit integer operand) across a full 128-bit operand 
is emulated by a combination of the followin g instructions: PSHUFHW, PSHUFLW, and PSHUFD.
•Use of the 64-bit shift by bit instructions (PSRLQ, PSLL Q) can be extended to 128 bits in either of two ways:
— Use of PSRLQ and PSLLQ, along with masking logic operations. 
— Rewriting the code sequence to use PSRLDQ and PSLLDQ (shift double quadword operand by bytes)
•Loop counters need to be updated, since each 128-bit SIMD integer instruction operates on twice the amount 
of data as its 64-bit SIMD integer counterpart.
11.6.12 Branching on Arithmetic Operations
There are no condition codes in SSE or SSE2 states. A packed-data comparison instruction generates a mask which 
can then be transferred to an integer register. The follow ing code sequence provides an  example of how to perform 
a conditional branch, based on the result of an Intel SSE2 arithmetic operation. 
cmppd XMM0, XMM1 ; generates a mask in XMM0
movmskpd EAX, XMM0 ; moves a 2 bit mask to eaxtest EAX, 0 ; compare with desired resultjne BRANCH TARGETVol. 1 11-25PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
The COMISD and UCOMISD instructions update the EFLAGS  as the result of a scalar comparison. A conditional 
branch can then be scheduled immediately following COMISD/UCOMISD.
11.6.13 Cacheability Hint Instructions
Intel SSE and SSE2 cacheability control instructions enab le the programmer to control prefetching, caching, 
loading, and storing of data. When correctly used, these instructions improve application performance. 
To make efficient use of the processor’s super-scalar microarchitecture, a program needs to provide a steady 
stream of data to the executing program to avoid stalling the processor. PREFETCH h instructions minimize the 
latency of data accesses in performance-critical sections of application code by allowing data to be fetched into the 
processor cache hierarchy in advance of actual usage. 
PREFETCH h instructions do not change the user-visible semant ics of a program, although they may affect perfor-
mance. The operation of these instructions is implementa tion-dependent. Programmers may need to tune code for 
each IA-32 processor implementation. Excessive usage of PREFETCH h instructions may waste memory bandwidth 
and reduce performance. For more deta iled information on the use of prefetch hints, refer to Chapter 7, “Opti-
mizing Cache Usage,” in the Intel® 64 and IA -32 Architectures Optimization Reference Manual.
The non-temporal store instructions (MOVNTI, MO VNTPD, MOVNTPS, MOVNTDQ, MOVNTQ, MASKMOVQ, and 
MASKMOVDQU) minimize cache pollution when writing non-temporal data to memory (see Section 10.4.6.1, 
“Cacheability Control Instructions,” an d Section 10.4.6.2, “Caching of Temporal vs. Non-Temporal Data”). They 
prevent non-temporal data from being written into processor caches on a store operation.
Besides reducing cache pollution, the use of weakly-order ed memory types can be important under certain data 
sharing relationships, such as a producer-consumer relati onship. The use of weakly ordered memory can make the 
assembling of data more efficient; but care must be take n to ensure that the consumer obtains the data that the 
producer intended. Some common usage models that may be affected in this way by weakly-ordered stores are: 
•Library functions that use weakly ordered memory to write results.
•Compiler-generated code that writes weakly-ordered results.
•Hand-crafted code.
The degree to which a consumer of data knows that the data is weakly ordered can vary for these cases. As a 
result, the SFENCE or MFENCE instruction should be us ed to ensure ordering between routines that produce 
weakly-ordered data and routines that consume the da ta. SFENCE and MFENCE provide a performance-efficient 
way to ensure ordering by guaranteeing that every st ore instruction that precedes SFENCE/MFENCE in program 
order is globally visible before a stor e instruction that follows the fence. 
11.6.14 Effect of Instruction Prefixes on  Intel® SSE and SSE2 Instructions
Table 11-3 describes the effects of instruction prefixes on  Intel SSE and SSE2 instructions. (Table 11-3 also applies

Table 11-3 describes the effects of instruction prefixes on  Intel SSE and SSE2 instructions. (Table 11-3 also applies 
to SIMD integer and SIMD floating-point instructions in Intel SSE3.) Unpredictable behavior can range from 
prefixes being treated as a reserved operation on one ge neration of IA-32 processors to generating an invalid 
opcode exception on another generation of processors.
See also “Instruction Prefixes” in Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A, for complete descrip tion of instruction prefixes.
NOTE
Some Intel SSE, SSE2, and SSE3 instructions have  two-byte opcodes that are either 2 bytes or 3 
bytes in length. Two-byte opcodes that are 3 byte s in length consist of: a mandatory prefix (F2H, 
F3H, or 66H), 0FH, and an opcode byte. See Table 11-3.11-26 Vol. 1PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
Table 11-3.  Effect of Prefixes on the Intel® SSE, SSE2, and SSE3 Instructions
Prefix Type Effect on the Intel® SSE, SSE2, and SSE3 Instructions 
Reserved for instructions without a memory operand and may result in unpredictable 
behavior.
Operand Size (66H) Reserved and may result in unpredictable behavior.
Segment Override 
(2EH,36H,3EH,26H,64H,65H)Affects instructions with a memory operand.
behavior.
Repeat Prefixes (F2H and F3H) Reserved and may result in unpredictable behavior.Lock Prefix (F0H) Reserved; generates invalid opcode exception (#UD).
Branch Hint Prefixes(E2H and E3H) Reserved and may result in unpredictable behavior.Vol. 1 12-1CHAPTER 12
PROGRAMMING WITH INTEL® SSE3, SSSE3,
INTEL® SSE4, AND INTEL® AES-NI
This chapter describes the Intel SSE3, SSSE3, and Intel SSE4  instructions, and provides information to assist in 
writing application programs that use these extensions. 
Intel AES-NI and PCLMLQDQ are instruction extensions ta rgeted to accelerate high-speed block encryption and 
cryptographic processing. Section 12.13 covers these instru ctions and their relationship to the Advanced Encryp-
tion Standard (AES).
12.1 PROGRAMMING ENVIRONMENT AND DATA TYPES
The programming environment for using Intel SSE3, SSSE3, and Intel SSE4 is unchanged from those shown in 
Figure 3-1 and Figure 3-2. These  extensions  do not introduce new data types. XMM registers are used to operate 
on packed integer data, single precision floating-poi nt data, or double precision floating-point data. 
One Intel SSE3 instruction uses the x87 FPU for x87-style programming. There are two Intel SSE3 instructions that 
use the general registers for thread synchronization. The MXCSR register governs SIMD floating-point operations. 
Note, however, that the x87 FPU control word does not affect  the Intel SSE3 instruction that is executed by the x87 
FPU (FISTTP), other than by unmasking an invalid operand or inexact result exception.
Intel SSE4 instructions do not use MMX registers. The majority of Intel SSE4.21 and SSE4.1 instructions operate on 
XMM registers.
12.1.1 Intel® SSE3, SSSE3, and Intel® SSE4  in 64-Bit Mode and Compatibility Mode
In compatibility mode, Intel SSE3, SSSE3, and Intel SSE4 fu nction like they do in protected mode. In 64-bit mode, 
eight additional XMM registers are accessible. Regi sters XMM8-XMM15 are accessed by using REX prefixes. 
Some Intel SSE3, SSSE3, and Intel SSE4 instructions may be used to operate on general-purpose registers. Use 
the REX.W prefix to access 64-bit general-purpose registers.  Note that if a REX prefix is used when it has no 
meaning, the prefix is ignored.
12.1.2 Compatibility of Intel® SSE3 and SSSE3 with MMX Tech nology, the x87 FPU 
Environment, and Intel® SSE and SSE2 
Intel SSE3, SSSE3, and Intel SSE4 do not introduce any new state to the Intel 64 and IA-32 execution environ-
ments. 
For SIMD and x87 programming, the FXSAVE and FXRSTOR instructions save and restore the architectural states 
of XMM, MXCSR, x87 FPU, and MMX registers. The MONITO R and MWAIT instructions use general purpose registers 
on input, they do not modify the content of those registers.
12.1.3 Horizontal and Asymmetric Processing
Many of the Intel SSE/SSE2/SSE3 and SSSE3 instructions accelerate SIMD data processing using a model referred 
to as vertical computation. Using this model, data flow is  vertical between the data elements of the inputs and the 
output. 
1. Although the presence of CRC32 support is enumerated by CPUI D.01:ECX[SSE4.2] = 1, CRC32 operates on general purpose regis-
ters.12-2 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
Figure 12-1 illustrates the asymmetric processing of the Intel SSE3 instruction ADDSUBPD. Figure 12-2 illustrates 
the horizontal data movement of the Intel SSE3 instruction HADDPD. 
12.2 OVERVIEW OF IN TEL® SSE3 INSTRUCTIONS
Intel SSE3 extensions include 13 instructions. See:
•Section 12.3, “Intel® SSE3 Instructions,” provides an introduction to individual Intel SSE3 instructions. 
•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, provides 
detailed information on individual instructions.
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating Intel 
SSE/SSE2/SSE3 extensions into an operating-system environment.
12.3 INTEL® SSE3 INSTRUCTIONS
Intel SSE3 instructions are grouped as follows:
•x87 FPU instruction:
— One instruction that improves x87 FPU floating-point to integer conversion.Figure 12-1.  Asymmetric Processing in ADDSUBPD 
Figure 12-2.  Horizontal Data Movement in HADDPDX1 X0
 X1 + Y1 X0 -Y0SUBY1 Y0
ADD
X1 X0
 Y0 + Y1 X0 + X1ADDY1 Y0
ADDVol. 1 12-3PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
•SIMD integer instruction:
— One instruction that provides a specialized 128-bit unaligned data load.
•SIMD floating-point instructions:
— Three instructions that enhance LOAD/MOVE/DUPLICATE performance.— Two instructions that provide packed addition/subtraction.
— Four instructions that provide horizontal addition/subtraction.
•Thread synchronization instructions:
— Two instructions that improve synchronization between multi-threaded agents.
The instructions are discussed in more detail in the following paragraphs.
12.3.1 x87 FPU Instruction for Integer Conversion
The FISTTP instruction (x87 FPU Store Integer and Pop with Truncation) behaves like FISTP, but uses truncation 
regardless of what rounding mode is specified in the x87 FPU control word. The instruction converts the top of stack 
(ST0) to integer with rounding to and pops the stack. 
The FISTTP instruction is available in three precisions: short integer (word or 16-bit), integer (double word or 32-
bit), and long integer (64-bit). With FISTTP, applications no longer need to change the FCW when truncation is 
required.
12.3.2 SIMD Integer Instruction for Sp ecialized 128-Bit Unaligned Data Load
The LDDQU instruction is a special 128-bit unaligned load de signed to avoid cache line sp lits. If the address of a 16-
byte load is on a 16-byte boundary, LDQQU loads the bytes requested. If the address of the load is not aligned on 
a 16-byte boundary, LDDQU loads a 32-byte block starting  at the 16-byte aligned address immediately below the 
load request. It then extr acts the requested 16 bytes.
The instruction provides significant performance improvem ent on 128-bit unaligned memory accesses at the cost 
of some usage model restrictions.
12.3.3 SIMD Floating-Point Instructions That  Enhance LOAD/MOVE/DUPLICATE Performance
The MOVSHDUP instruction loads/moves 128-bits, duplic ating the second and fourth 32-bit data elements.
•MOVSHDUP OperandA, OperandB
— OperandA (128 bits, four data elements): 3a, 2a, 1a, 0a
— OperandB (128 bits, four data elements): 3b, 2b, 1b, 0b
— Result (stored in OperandA): 3b, 3b, 1b, 1b
The MOVSLDUP instruction loads/moves 128-bits, dupl icating the first and third 32-bit data elements.
•MOVSLDUP OperandA, OperandB
— Result (stored in OperandA): 2b, 2b, 0b, 0b
The MOVDDUP instruction loads/moves 64-bits; duplicating the 64 bits from the source.
•MOVDDUP OperandA, OperandB
— OperandA (128 bits, two data elements): 1a, 0a
— OperandB (64 bits, one data element): 0b
— Result (stored in OperandA): 0b, 0b12-4 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.3.4 SIMD Floating-Point Instructions  Provide Packed Addition/Subtraction
The ADDSUBPS instruction has two 128-bit operands. The in struction performs single precision addition on the 
second and fourth pairs of 32-bit data elements within th e operands; and single precision subtraction on the first 
and third pairs.
•ADDSUBPS OperandA, OperandB

— Result (stored in OperandA): 3a+3b, 2a-2b, 1a+1b, 0a-0b
The ADDSUBPD instruction has two 128-bit operands. The in struction performs double precision addition on the 
second pair of quadwords, and double precision subtraction on the first pair.
•ADDSUBPD OperandA, OperandB
— OperandB (128 bits, two data elements): 1b, 0b
— Result (stored in OperandA): 1a+1b, 0a-0b
12.3.5 SIMD Floating-Point Instructions Provide Horizontal Addition/Subtraction
Most SIMD instructions operate vertically. This means that th e result in position i is a function of the elements in 
position i of both operands. Horizontal addition/subtraction operates horizontally. This means that contiguous data 
elements in the same source operand are used to produce a result.
The HADDPS instruction performs a single precision additi on on contiguous data elements. The first data element 
of the result is obtained by adding the first and second el ements of the first operand; the second element by adding 
the third and fourth elements of the first operand; the thir d by adding the first and seco nd elements of the second 
operand; and the fourth by adding the third and fourth elements of the second operand.
•HADDPS OperandA, OperandB
— Result (Stored in OperandA): 3b+2b, 1b+0b, 3a+2a, 1a+0a
The HSUBPS instruction performs a single precision subt raction on contiguous data elements. The first data 
element of the result is obtained by subtracting the seco nd element of the first operand from the first element of 
the first operand; the second element by subtracting the fo urth element of the first operand from the third element 
of the first operand; the third by subtracting the second element of the second operand from the first element of 
the second operand; and the fourth by subtracting the fourth element of the seco nd operand from the third 
element of the second operand.
•HSUBPS OperandA, OperandB
— Result (Stored in OperandA): 2b-3b, 0b-1b, 2a-3a, 0a-1a
The HADDPD instruction performs a double precision additi on on contiguous data elements. The first data element 
the first and second elements of the second operand.
•HADDPD OperandA, OperandB
— Result (Stored in OperandA): 1b+0b, 1a+0aVol. 1 12-5PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
The HSUBPD instruction performs a do uble precision subtraction on contiguous data elements. The first data 
the first operand; the second element by subtracting the second element of the second operand from the first 
•HSUBPD OperandA OperandB
— Result (Stored in OperandA): 0b-1b, 0a-1a
12.3.6 Two Thread Synchronization Instructions
The MONITOR instruction sets up an address range that is used to monitor write-back-stores. MWAIT enables a logical processor to enter into an optimized state while waiting for a write-back-store to the 
address range set up by MONITOR. MONITOR and MWAIT requ ire the use of general purpose registers for its input. 
The registers used by MONITOR and MWAIT must be initializ ed properly; register content is not modified by these 
12.4 WRITING APPLICATIONS WITH INTEL® SSE3
The following sections give guidelines  for writing application programs and operating-system code that use Intel 
SSE3 instructions. 
12.4.1 Guidelines for Using Intel® SSE3
The following guidelines describe how to maximize the benefits of using Intel SSE3:
•Check that the processor supports Intel SSE3.
— Applications may need to ensure that the target op erating system supports Intel SSE3. (Operating system 
support for the Intel SSE implies sufficient support for Intel SSE2 and SSE3.) 
•Ensure your operating system supports MONITOR and MWAIT.
zation Reference Manual (see Section 1.4, “Related Literature”).
12.4.2 Checking for Intel® SSE3 Support
Before an application attempts to use the SIMD subset of Intel SSE3 instructions, the application should follow the 
steps illustrated in Section 11.6.2, “Checking for Intel®  SSE and SSE2 Support.” Next, use the additional step 
provided below:
•Check that the processor supports the SIMD and x87 Inte l SSE3 extensions (if CPUID.01H:ECX.SSE3[bit 0] = 
1). 
An operating system that provides application support for Intel SSE and SSE2 also provides sufficient application 
support for Intel SSE3. To use FISTTP, software only needs to check support for Intel SSE3.
In the initial implementation of MONITOR and MWAIT, thes e two instructions are available to ring 0 and condition-
ally available at ring level greater than 0. Before an application attempts to use the MONITOR and MWAIT instruc-
tions, the application should use the following steps:
1. Check that the processor supports MONITOR and MWAIT. If CPUID.01H:ECX.MONITOR[bit 3] = 1, MONITOR 
and MWAIT are available at ring 0. 
2. Query the smallest and largest line size that MONITOR uses. Use CPUID.05H:EAX.smallest[bits 
15:0];EBX.largest[bits15:0]. Values ar e returned in bytes in EAX and EBX.12-6 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
3. Ensure the memory address range(s) that will be supplied to MONITOR meets memory type requirements.
MONITOR and MWAIT are targeted for system software that  supports efficient thread synchronization, see Chapter 
14 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A for details.
12.4.3 Enable FTZ and DAZ for SIMD Floating-Point Computation
Enabling the FTZ and DAZ flags in the MX CSR register is likely to accelerate SIMD floating-point computation where 
strict compliance to the IEEE standard 754-1985 is not re quired. The FTZ flag is available to Intel 64 and IA-32 
processors that support Intel SSE; DAZ is available to Intel 64 processors and to most IA-32 processors that 
support Intel SSE, SSE2, and SSE3. 
Software can detect the presence of DAZ, modify the MX CSR register, and save and restore state information by 
following the techniques discussed in Section 11.6.3 through Section 11.6.6.
12.4.4 Programming Intel® SSE 3 with Intel® SSE and SSE2
SIMD instructions in Intel SSE3 are intended to complement the use of Intel SSE and SSE2 in programming SIMD 
applications. Application software that intends to use Intel SSE3 instructions should also check for the availability 
of Intel SSE and SSE2 instructions.
The FISTTP instruction in Intel SSE3 is intended to acce lerate x87 style programming where performance is limited 
by frequent floating-point conversion to integers; th is happens when the x87 FPU control word is modified 
frequently. Use of the FISTTP instruction can elim inate the need to access the x87 FPU control word.
12.5 OVERVIEW OF  SSSE3 INSTRUCTIONS
SSSE3 provides 32 instructions to accelerate a variety of  multimedia and signal processing applications employing 
SIMD integer data. See:
•Section 12.6, “SSSE3 Instructions,” provides an introduction to individual SSSE3 instructions. 
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating SSSE3 
and Intel SSE, SSE2, and SSE3 into an operating-system environment.
12.6 SSSE3 INSTRUCTIONS
SSSE3 instructions include:
•Six instructions that evaluate the absolute values.

The operands of these instructions are packed integers of byte, word, or double word sizes. The operands are 
stored as 64 or 128 bit data in MMX registers, XMM registers, or memory.
The instructions are discussed in more detail in the following paragraphs.Vol. 1 12-7PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.6.1 Horizontal Addition/Subtraction
In analogy to the packed, floating-point horizontal add and subtract instructions in Intel SSE3, SSSE3 offers similar 
capabilities on packed integer data. Data elements of si gned words, doublewords are supported. Saturated version 
for horizontal add and subtract on signed words are also  supported. The horizontal data movement of PHADD is 
shown in Figure 12-3. 
There are six horizontal add instructions (represented by three mnemonics); three operate on 128-bit operands 
and three operate on 64-bit operands. The width of each da ta element is either 16 bits or 32 bits. The mnemonics 
are listed below.
•PHADDW adds two adjacent, signed 16- bit integers horizontally from the source and destination operands and 
packs the signed 16-bit results to the destination operand.
•PHADDSW adds two adjacent, signed 16-bit integers hori zontally from the source and destination operands 
and packs the signed, saturated 16-bit results to the destination operand.
•PHADDD adds two adjacent, signed 32- bit integers horizontally from the source and destination operands and 
packs the signed 32-bit results to the destination operand.
There are six horizontal subtract instructions (represent ed by three mnemonics); three operate on 128-bit oper-
ands and three operate on 64-bit operands. The width of each  data element is either 16 bits or 32 bits. These are 
listed below.
•PHSUBW performs horizontal subtraction on each adjace nt pair of 16-bit signed in tegers by subtracting the 
most significant word from the least significant word of  each pair in the source and destination operands. The 
signed 16-bit results are packed and written to the destination operand.
•PHSUBSW performs horizontal subtraction on each adjacent  pair of 16-bit signed in tegers by subtracting the 
signed, saturated 16-bit results are packed and written to the destination operand.
•PHSUBD performs horizontal subtraction on each adjace nt pair of 32-bit signed integers by subtracting the 
most significant doubleword from the least significant double word of each pair in the source and destination 
operands. The signed 32-bit results are packed and written to the destination operand.
12.6.2 Packed Absolute Values
There are six packed-absolute-value instructions (repre sented by three mnemonics). Three operate on 128-bit 
operands and three operate on 64-bit operands. The widths  of data elements are 8 bits, 16 bits or 32 bits. The 
absolute value of each data element of the source operan d is stored as an UNSIGNED result in the destination 
operand.
•PABSB computes the absolute value of  each signed byte data element.Figure 12-3.  Horizontal Data Movement in PHADDDX0 + X1 X2 + X3 Y0 + Y1 Y2 + Y3X2 X0
ADDY1 Y0
ADDY2 Y3X1 X3
ADD ADD12-8 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
•PABSW computes the absolute value of each signed 16-bit data element.
•PABSD computes the absolute value of each signed 32-bit data element. 
12.6.3 Multiply and Add Packed Signed and Unsigned Bytes
There are two multiply-and-add-packed-s igned-unsigned-byte instructions (represented by one mnemonic). One 
operates on 128-bit operands and the other operates on 64-bit operands. Multiplications are performed on each 
vertical pair of data elements. The data elements in th e source operand are signed byte values, the input data 
elements of the destination oper and are unsigned byte values.
•PMADDUBSW multiplies each unsigned byte value with th e corresponding signed byte value to produce an 
intermediate, 16-bit signed integer. Each adjacent pair of 16-bit signed  values are added horizontally. The 
signed, saturated 16-bit results are packed to the destination operand.
12.6.4 Packed Multiply High  with Round and Scale
There are two packed-multiply-high-with-round-and-scale in structions (represented by one mnemonic). One oper-
ates on 128-bit operands and the other operates on 64-bit operands.
•PMULHRSW multiplies vertically each signed 16-bit integer from the destination operand with the corre-
sponding signed 16-bit integer of the source operand,  producing intermediate, sign ed 32-bit integers. Each 
intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is always performed by adding 
1 to the least significant bit of the 18-bit intermediate re sult. The final result is obtained by selecting the 16 bits 
immediately to the right of the most significant bit of  each 18-bit intermediate result and packed to the 
12.6.5 Packed Shuffle Bytes
There are two packed-shuffle-bytes instructions (represent ed by one mnemonic). One operates on 128-bit oper-
ands and the other operates on 64-bit operands. The shuffl e operations are performed bytewise on the destination 
operand using the source operand as a control mask.
•PSHUFB permutes each byte in place, according to a shuf fle control mask. The least significant three or four bits 
of each shuffle control byte of the control mask form th e shuffle index. The shuffle mask is unaffected. If the 
most significant bit (bit 7) of a shuffle control byte is  set, the constant zero is written in the result byte.
12.6.6 Packed Sign
There are six packed-sign instructions (represented by three mnemonics). Three operate on 128-bit operands and 
three operate on 64-bit operands. The widths of each data element for these instructions are 8 bit, 16 bit or 32 bit 
signed integers.
•PSIGNB/W/D negates each signed integer element of the destination operand if the sign of the corresponding 
data element in the source operand is less than zero.
12.6.7 Packed Align Right
There are two packed-align-right instructions (represented  by one mnemonic). One operates on 128-bit operands 
and the other operates on 64-bit operands. These instructions concatenate the destination and source operand into 
a composite, and extract the result from the composite according to an immediate constant.
•PALIGNR’s source operand is appended after the destin ation operand forming an intermediate value of twice 
the width of an operand. The result is extracted from the intermediate value into the destination operand by 
selecting the 128-bit or 64-bit value that are right-aligne d to the byte offset specified by the immediate value. Vol. 1 12-9PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.7 WRITING APPLICATIO NS WITH SSSE3 EXTENSIONS
The following sections give guidelines for writing applic ation programs and operating-system code that use SSSE3 
12.7.1 Guidelines for Using SSSE3 
The following guidelines describe how to maximize the benefits of using SSSE3:
•Check that the processor supports SSSE3.
•Ensure that your operating system supports SSSE3 and Intel SSE, SSE2, and SSE3. (Operating system support 
for Intel SSE implies suffic ient support for SSSE3 and Intel SSE2 and SSE3.) 
12.7.2 Checking for SSSE3 Support
Before an application attempts to use SSSE3, the applicat ion should follow the steps illustrated in Section 11.6.2, 
“Checking for Intel® SSE and SSE2 Support.” Next, use the additional step provided below:
•Check that the processor supports SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1). 
12.8 INTEL® SSE3, SSSE3, AND INTEL® SSE4 EXCEPTIONS
Intel SSE3, SSSE3, and Intel SSE4 instructions can gene rate the same type of memory-access and non-numeric 
exceptions as other Intel 64 or IA-32 instructions. Existing exception handlers generally handle these exceptions without code modification. 
FISTTP can generate floating-point exceptions. Some Intel SSE3 instructions can also generate SIMD floating-point 
exceptions. 
Intel SSE3 additions and changes are noted in the follow ing sections. See also: Section 11.5, “Intel® SSE, SSE2, 
and SSE3 Exceptions”.
12.8.1 Device Not Available (DNA) Exceptions
Intel SSE3, SSSE3, and Intel SSE4 will cause a DNA Exceptio n (#NM) if the processor attempts to execute an Intel 
SSE3 instruction while CR0.TS[bit 3] = 1. If CPUID.01H:E CX.SSE3[bit 0] = 0, execution of an Intel SSE3 instruc-
tion will cause an invalid opcode fault regardless of the state of CR0.TS[bit 3].
Similarly, an attempt to execute an SSSE3 instruction on a processor that reports CPUID.01H:ECX.SSSE3[bit 9] =

Similarly, an attempt to execute an SSSE3 instruction on a processor that reports CPUID.01H:ECX.SSSE3[bit 9] = 
0 will cause an invalid opcode fault regardless of the state of CR0.TS[bit 3]. An attempt to execute an Intel SSE4.1 instruction on a processor that reports CPUID.01H:ECX.SSE4_1[bit 19] = 0 will cause an invalid opcode fault 
regardless of the state of CR0.TS[bit 3].
An attempt to execute PCMPGTQ or any one of the four string processing instructions in Intel SSE4.2 on a 
processor that reports CPUID.01H:ECX.SSE4_2[bit 20] = 0 will cause an invalid opcode fault regardless of the 
state of CR0.TS[bit 3]. CRC32 and POPCNT do not cause #NM.
12.8.2 Numeric Error Flag and IGNNE#
Most Intel SSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and the IGNNE# pin. With one exception, all use the exception 19 (#XM) software exception for error reporting. The exception is FISTTP; it 
behaves like other x87-FP instructions.
SSSE3 instructions ignore CR0.NE[bit 5] (treats it  as if it were always set) and the IGNNE# pin. 12-10 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
SSSE3 instructions do not cause floating-point errors. Floa ting-point numeric errors for Intel SSE4.1 are described 
in Section 12.8.4. Intel SSE4.2 instructions do not cause floating-point errors.
12.8.3 Emulation
CR0.EM is used by some software to emulate x87 floating -point instructions. CR0.EM[bit 2] cannot be used for 
emulation of SSSE3 and Intel SSE, SSE2, SSE3, and SSE4. If an Intel SSE3, SSSE3, or Intel SSE4 instruction 
execute with CR0.EM[bit 2] set, an invalid opcode exception (INT 6) is generated instead of a device not available 
exception (INT 7).
12.8.4 IEEE 754 Compliance of Intel® SS E4.1 Floating-Point Instructions
The six Intel SSE4.1 instructions that perform floating-point arithmetic are:
•DPPS
•DPPD
•ROUNDPS
•ROUNDPD
•ROUNDSS
•ROUNDSD
Dot Product operations are not specified in IEEE-754. When neither FTZ nor DAZ are enabled, the dot product 
instructions resemble sequences of IEEE-754 multiplies and adds (with rounding at each stage), except that the 
treatment of input NaN’s is implementation  specific (there will be at least on e NaN in the output). The input select 
fields (bits imm8[4:7]) force input elements to +0.0f prio r to the first multiply and will suppress input exceptions 
that would otherwise have been be generated.
As a convenience to the exception handler, any exceptio ns signaled from DPPS or DPPD leave the destination 
unmodified. 
Round operations signal invalid and precision only.
The other Intel SSE4.1 instructions with floating-poi nt arguments (BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, 
INSERTPS, EXTRACTPS) do not signal any SIMD numeric exceptions.
12.9 INTEL® SSE4 OVERVIEW
Intel SSE4 comprises two sets of extensions: Intel SSE4.1  and SSE4.2. Intel SSE4.1 is targeted to improve the 
performance of media, imaging, and 3D workloads. Intel SSE4.1 adds instructions th at improve compiler vectoriza-Table 12-1.  SIMD Numeric Exceptions Signaled by SSE4.1
DPPS DPPD ROUNDPS
ROUNDSSROUNDPD
ROUNDSD
Overflow X XUnderflow X X
I n v a l i dXXX  
(1)X (1)
I n e x a c t  P r e c i s i o n XXX  (2)X (2)
Denormal X XNOTE:
1. Invalid is signaled  only if Src = SNaN.
2. Precision is ignored (regardless of the MXCSR precision mask) if if imm8[3] = ‘1’.Vol. 1 12-11PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
tion and significantly increase support for packed dword computation. The technology also provides a hint that can 
improve memory throughput when reading from uncacheable WC memory type.
•Four instructions support floating-point round with sele ctable rounding mode and precision exception override.
The Intel SSE4.2 instructions operating on XMM regi sters improve performance in the following areas:
•String and text processing that can take advantag e of single-instruction multiple-data programming 
•A SIMD integer instruction that enhances the capability of the 128-bit integer SIMD capability in Intel SSE4.1.
12.10 INTEL® SSE4.1 INSTRUCTION SET
12.10.1 Dword Multiply Instructions 
Intel SSE4.1 adds two dword multiply inst ructions that aid vectorization. They allow four simultaneous 32 bit by 32 
bit multiplies. PMULLD returns a low 32-bits of the result  and PMULDQ returns a 64-bit signed result. These repre-
sent the most common integer mult iply operation. See Table 12-2.
12.10.2 Floating-Point Dot Product Instructions
Intel SSE4.1 adds two instructions for double precision (f or up to 2 elements; DPPD) and single precision dot prod-
ucts (for up to 4 elements; DPPS).
These dot-product instructions include source select and destination broadcast which generally improves the flex-
ibility. For example, a single DPPS instruction ca n be used for a 2, 3, or 4 element dot product.Table 12-2.  Enhanced 32-Bit SIMD Multiply Supported by Intel® SSE4.1
32-Bit Integer Operation
Unsigned x Unsigned Signed x SignedResultLow 32-bit (not available) PMULLD
High 32-bit (not available) (not available)
64-bit PMULUDQ* PMULDQ
NOTE:
* Available prior to Intel SSE4.1.12-12 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.10.3 Streaming Load Hint Instruction
Historically, CPU read accesses of WC memory type region s have significantly lower throughput than accesses to 
cacheable memory. 
The streaming load instruction in SSE4.1, MOVNTDQA, prov ides a non-temporal hint that can cause adjacent 16-
byte items within an aligned 64-byte region of WC memory type (a streaming line) to be  fetched and held in a small 
set of temporary buffers (“streaming load buffers”). Subseq uent streaming loads to other aligned 16-byte items in 
the same streaming line may be satisfied from the streaming load buffer and can improve throughput.
Programmers are advised to use the following practices to improve the efficiency of MOVNTDQA streaming loads 
from WC memory:
•Streaming loads must be 16-byte aligned.
•Temporally group streaming loads of the same streaming cache line for effective use of the small number of 
streaming load buffers. If loads to the same streaming line are excessively spaced apart, it may cause the 
streaming line to be re-fetched from memory.
•Temporally group streaming loads from at most a few streaming lines together. The number of streaming load 
buffers is small; grouping a modest number of streams will avoid running out of streaming load buffers and the 
resultant re-fetching of streaming lines from memory.
•Avoid writing to a streaming line until all 16-byte-aligned reads from the streaming line have occurred. Reading a 16-byte item from a streaming line that has been wr itten, may cause the streaming line to be re-fetched.
•Avoid reading a given 16-byte item within a streaming li ne more than once; repeated loads of a particular 16-
byte item are likely to cause the streaming line to be re-fetched.
•The streaming load buffers, reflecting the WC memory ty pe characteristics, are not required to be snooped by 
operations from other agents. Software should not re ly upon such coherency actions to provide any data 
coherency with respect to other logical processors or bu s agents. Rather, software must ensure the consistency 
of WC memory accesses between producers and consumers.
•Streaming loads may be weakly ordered and may appear to  software to execute out of order with respect to 
other memory operations. Software must explicitly use MFENCE if it needs to preserve order among streaming 
loads or between streaming loads and other memory operations.
•Streaming loads must not be used to reference memory addresses that are mapped to I/O devices having side 
effects or when reads to these devices are destructive.  This is because MOVNTDQA is speculative in nature.
Example 12-1 provides a sketch of the basic assembly sequ ences that illustrate the principles of using MOVNTDQA 
in a situation with a producer-consumer accessing a WC memory region.Vol. 1 12-13PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
Example 12-1.  Sketch of MOVNTDQA Us age of a Consumer and a PCI Producer 
// P0: producer is a PCI device writing into the WC space
# the PCI device updates status th rough a UC flag, "u_dev_status" .

# the PCI device updates status th rough a UC flag, "u_dev_status" . 
# the protocol for "u_dev_status" : 0:  produce; 1: consume; 2: all done
mov eax, $0
mov [u_dev_status], eax
producerStart:
mov eax, [u_dev_status]     # poll status flag to see if consumer is requestion data
cmp eax, $0                           # jne done                                # I no longer need to produce                       
commence PCI writes  to WC region..
mov eax, $1  # producer ready to notify the consumer via status flag
mov  [u_dev_status], eax     
# now wait for consumer to signal its status
spinloop:
cmp [u_dev_status], $1      # did I get a signal from the consumer ?
jne producerStart                  # yes I did jmp spinloop                         # check again
done:// producer is finish ed at this point 
// P1: consumer check PCI stat us flag to consume WC data
mov eax, $0  # request to the producer mov [u_dev_status], eax
consumerStart:
mov; eax, [u_dev_status]  # reads the value of the PCI status cmp eax, $1                                 # has producer writtenjne consumerStart                       # tight loop; make it more efficient with pause, etc. 
mfence # producer finished device writes  to WC, ensure WC region is coherent
ntread:
movntdqa xmm0, [addr]movntdqa xmm1, [addr + 16]movntdqa xmm2, [addr + 32]movntdqa xmm3, [addr + 48]…  # do any more NT reads as neededmfence  # ensure PCI device reads the correct value of [u_dev_status]  
# now decide whether we are done or we need the producer to produce more data# if we are done write a 2 into the variable, otherwise write a 0 into the variable
mov eax, $0/$2            # end or continue producing
# if I want to consume again I will jump back  to consumerStart after storing a 0 into eax
# otherwise I am done12-14 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.10.4 Packed Blending Instructions
Intel SSE4.1 adds 6 instructions used for blending (BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, PBLENDVB, 
PBLENDW).
Blending conditionally copies a data element in a source operand to the same element in the destination. Intel 
SSE4.1 instructions improve blending operations for most  field sizes. A single new Intel SSE4.1 instruction can 
generally replace a sequence of 2 to 4 operations using previous architectures.
The variable blend instructions (BLEND VPS, BLENDVPD, PBLENDW) introduce the use of control bits stored in an 
implicit XMM register (XMM0). The most significant bit in each field (the sign bit, for 2’s complement integer or 
floating-point) is used as a selector. See Table 12-3.
12.10.5 Packed Integer MIN/MAX Instructions 
Intel SSE4.1 adds 8 packed integer MIN and MAX in structions: PMINUW, PMINUD, PMINSB, PMINSD; PMAXUW, 
PMAXUD, PMAXSB, and PMAXSD. 
Four 32-bit integer packed MIN and MAX instructions oper ate on unsigned and signed dwords. Two instructions 
operate on signed bytes. Two instructions  operate on unsigned words. See Table 12-4.
12.10.6 Floating-Point Round Instruct ions with Selectable Rounding Mode
High level languages and libraries often expose rounding  operations having a variety of numeric rounding and 
exception behaviors. Using Intel SSE, SSE2, and SSE3 inst ructions to mitigate the rounding-mode-related problem 
is sometimes not straight forward.
Intel SSE4.1 introduces four rounding instructions (ROUNDPS, ROUNDPD, ROUNDSS, and ROUNDSD) that cover 
scalar and packed single- and double precision floating-p oint operands. The rounding mode can be selected using 
an immediate from one of the IEEE-754 modes (Nearest, -I nf, +Inf, and Truncate) without changing the current Table 12-3.  Blend Field Size and Control Modes Supported by Intel® SSE4.1 
InstructionsPacked 
Double FPPacked 
Single FPPacked 
QWordPacked 
DWordPacked 
Word Packed Byte Blend Control
BLENDPS X Imm8
BLENDPD X Imm8
BLENDVPS X X(1)XMM0
BLENDVPD X X(1)XMM0
PBLENDVB(2) (2) (2)XX M M 0
P B L E N D W XXX I m m 8
NOTE:
1. Use of floating-point SIMD instructions on integer data types may incur performance penalties. 
2. Byte variable blend can be used for larger sized fi elds by reformatting (or shuffling) the blend control.
Table 12-4.  Enhanced SIMD Integer MIN/MAX Instructions Supporte d by Intel® SSE4.1
Integer Width
Byte Word DWord
Integer 
Format UnsignedPMINUB*
PMAXUB*PMINUW
PMAXUWPMINUD
PMAXUD
SignedPMINSB
PMAXSBPMINSW*
PMAXSW*PMINSD
PMAXSD
NOTE:
* Available prior to Intel SSE4.1.Vol. 1 12-15PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
rounding mode; or the instruction can be forced to use the current rounding mode. Another bit in the immediate is 
used to suppress inexact precision exceptions.
Rounding instructions in Intel SSE4.1 generally permit sing le-instruction solutions to C99 functions ceil(), floor(), 
trunc(), rint(), nearbyint(). These instructions simplif y the implementations of half-way-away-from-zero rounding 
modes as used by C99 round() and F90’s nint().
12.10.7 Insertion and Extractions from XMM Registers
Intel SSE4.1 adds 7 instructions (corresponding to 9 asse mbly instruction mnemonics) that simplify data insertion 
and extraction between general-purpose register (GPR ) and XMM registers: EXTRACTPS, INSERTPS, PINSRB, 
PINSRD, PINSRQ, PEXTRB, PEXTRW, PEXTRD, and PEXTRQ. Wh en accessing memory, no alignment is required for 
any of these instructions (unless alignment checking is enabled).
EXTRACTPS extracts a single precision fl oating-point value from any dword offset in an XMM register and stores the 
result to memory or a general-purpose register. INSERTPS inserts a single floa ting-point value from either a 32-bit 
memory location or from specified element in an XMM register to a selected element in the destination XMM 
register. In addition, INSERTPS allows the insertion of +0.0f into any destination elements using a mask.
PINSRB, PINSRD, and PINSRQ insert byte, dword, or qword integer values from a register or memory into an XMM 
register. Insertion of integer word values we re already supported by Intel SSE2 (PINSRW). 
PEXTRB, PEXTRW, PEXTRD, and PEXTRQ extract byte, word, dw ord, and qword from an XMM register and insert the 
values into a general-purpose register or memory.
12.10.8 Packed Integer Format Conversions
A common type of operation on packed integers is the co nversion by zero- or sign-extension of packed integers 
into wider data types. Intel SSE4.1 adds 12 instructions th at convert from a smaller packed integer type to a larger 
integer type: PMOVSXBW, PMOVZXBW, PMOVSXBD , PMOVZXBD, PMOVSXWD, PMOVZXWD, PMOVSXBQ, 
PMOVZXBQ, PMOVSXWQ, PMOVZXWQ, PMOVSXDQ, and PMOVZXDQ.
The source operand is from either an XMM register or memory; the destination is an XMM register. See Table 12-5.
When accessing memory, no alignment is required for any of  the instructions unless alignment checking is enabled. 
In which case, all conversions must be aligned to the width of the memory reference. The number of elements converted (and width of memory reference) is illustrate d in Table 12-6. The alignment requirement is shown in 
parenthesis.
Table 12-5.  New SIMD Integer Conversions Supported by Intel® SSE4.1 
Source Type
Byte Word DwordDestination
TypeSigned Word
Unsigned WordPMOVSXBW
PMOVZXBW
Signed Dword
Unsigned DwordPMOVSXBD
PMOVZXBDPMOVSXWD
PMOVZXWD
Signed Qword
Unsigned QwordPMOVSXBQ
PMOVZXBQPMOVSXWQ
PMOVZXWQPMOVSXDQ
PMOVZXDQ12-16 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks
Intel SSE4.1 adds an instruction (MPSADBW) that performs  eight 4-byte wide SAD operations per instruction to 
produce eight results. Compared to PSADBW, MPSADBW op erates on smaller chunks (4-byte instead of 8-byte 
chunks); this makes the instruction better suited to vi deo coding standards such as VC.1 and H.264. MPSADBW 
performs four times the number of absolute difference operat ions than that of PSADBW (per instruction). This can 
improve performance for dense motion searches.
MPSADBW uses a 4-byte wide field from a source operand; the offset of the 4-byte fi eld within the 128-bit source 
operand is specified by two immediate control bits. MPSADB W produces eight 16-bit SAD results. Each 16-bit SAD 
result is formed from overlapping pairs of 4 bytes in the destination with the 4-byte field from the source operand. 
MPSADBW uses eleven consecutive bytes in the destination op erand, its offset is specified by a control bit in the 
immediate byte (i.e., the offset can be from byte 0 or  from byte 4). Figure 12-4  illustrates the operation of 
MPSADBW. MPSADBW can simplify coding of dense motion es timation by providing sour ce and destination offset 
control, higher throughput of SAD operations, and the smaller chunk size.
12.10.10 Horizontal Search
Intel SSE4.1 adds a search instruction (PHMINPOSUW) th at finds the value and location of the minimum unsigned 
word from one of 8 horizontally packed unsigned words. The resulting value and location (offset within the source)

word from one of 8 horizontally packed unsigned words. The resulting value and location (offset within the source) 
are packed into the low dword of  the destination XMM register.
Rapid search is often a significant component of moti on estimation. MPSADBW and PHMINPOSUW can be used 
together to improve video encode.Table 12-6.  New SIMD Integer Conver sions Supported by Intel® SSE4.1 
TypeWord 8 (64 bits)
Dword 4 (32 bits) 4 (64 bits)
Qword 2 (16 bits) 2 (32 bits) 2 (64 bits)
Figure 12-4.  MPSADBW OperationAbs. Diff.
SumImm[1:0]*32
Imm[2]*32Source
0 127 160 127 96 64Vol. 1 12-17PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.10.11 Packed Test
The packed test instruction PTEST is similar to a 128-bit eq uivalent to the legacy instruction TEST. With PTEST, the 
source argument is typically used like a bit mask. 
PTEST performs a logical AND between the destination with this  mask and sets the ZF flag if the result is zero. The 
CF flag (zero for TEST) is set if the inverted mask AND’d with the destination is all zero. Because the destination is 
not modified, PTEST simplifies branching operations (such as  branching on signs of packed floating-point numbers, 
or branching on zero fields).
12.10.12 Packed Qword Eq uality Comparisons
Intel SSE4.1 adds a 128-bit packed qword equality test. Th e new instruction (PCMPEQQ) is identical to PCMPEQD, 
but has qword granularity.
12.10.13 Dword Packing With Unsigned Saturation
Intel SSE4.1 adds a new instruction PACKUSDW to complete the set of small integer pack instructions in the family 
of SIMD instruction extensions. PACKUSDW packs dword to  word with unsigned saturation. See Table 12-7 for the 
complete set of packing instructions for small integers.
12.11 INTEL® SSE4.2 INSTRUCTION SET
Five of the seven Intel SSE4.2 instructions can use an XMM register as a source or destination. These include four text/string processing instructions and one packed quadword compare SIMD instruction. Programming these five 
Intel SSE4.2 instructions is similar to programming 128-b it Integer SIMD in Intel SSE2 or SSSE3. Intel SSE4.2 
does not provide any 64-bit integer SIMD instructions. 
12.11.1 String and Text Processing Instructions
String and text processing instructions in Intel SSE4.2 allo cates four opcodes to provide a rich set of string and text 
processing capabilities that traditionally required many more opcodes. These four instructions use XMM registers 
to process string or text elements of up to 128-bits (16 bytes or 8 words). Each instruction uses an immediate byte 
to support a rich set of programmable controls. A string-p rocessing Intel SSE4.2 instruction returns the result of 
processing each pair of string elements using either an index or a mask. 
The capabilities of the string/text processing instructions include:
•Handling string/text fragments consisting of bytes or words, either  signed or unsigned.
•Support for partial string or fragments less than 16 bytes in  length, using either explicit length or implicit null-
termination.
•Four types of string compare operations on word/byte elements.
•Up to 256 compare operations performed in a single instruction on all string/text element pairs.
•Built-in aggregation of intermediate results from comparisons.Table 12-7.  Enhanced SIMD Pack Support by Intel® SSE4.1
Pack Type
DWord -> Word Word -> ByteSaturation 
TypeUnsigned PACKUSDW (new!) PACKUSWB
Signed PACKSSDW PACKSSWB12-18 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
•Programmable control of processing on intermediate results.
•Programmable control of output formats in terms of an index or mask.
•Bi-directional support for the index format.
•Support for two mask formats: bit or natural element width.
•Not requiring 16-byte alignment for memory operand.
The four Intel SSE4.2 instructions that process text/string fragments are:
•PCMPESTRI  — Packed compare explicit-length strings, return index in ECX/RCX.
•PCMPESTRM  — Packed compare explicit-length strings, return mask in XMM0.
•PCMPISTRI  — Packed compare implicit-length strings, return index in ECX/RCX.
•PCMPISTRM  — Packed compare implicit-length strings, return mask in XMM0.
All four of these instructions require the use of an imme diate byte to control operation. The two source operands 
can be XMM registers or a combination of XMM register  and memory address. The immediate byte provides 
programmable control with the following attributes:
•Input data format.
•Compare operation mode.
•Intermediate result processing.
•Output selection.
Depending on the output format associated with the instru ction, the text/string processing instructions implicitly 
uses either a general-purpose register (ECX/RCX) or an XMM register (XMM0) to  return the final result.
Two of the four text-string processing instructions specif y string length explicitly. They use two general-purpose 
registers (EDX, EAX) to specify the number of valid data el ements (either word or byte) in the source operands. The 
other two instructions specify valid stri ng elements using null termination. A data element is considered valid only 
if it has a lower index than the least significant null data element.
12.11.1.1  Memory Operand Alignment
The text and string processing instructions in Intel SSE4.2 do not perform alignment checking on memory oper-
ands. This is different from most other 128-bit SIMD inst ructions accessing the XMM registers. The absence of an 
alignment check for these four instructions does not imply any modification to the existing definitions of other 
12.11.2 Packed Comparison SIMD Integer Instruction
Intel SSE4.2 also provides a 128-bit integer SIMD instru ction PCMPGTQ that performs logical compare of greater-
than on packed integer quadwords.
12.12 WRITING APPLICATIONS WITH INTEL® SSE4 EXTENSIONS
12.12.1 Guidelines for Using Intel® SSE4 Extensions
The following guidelines describe how to maximize  the benefits of using Intel SSE4 extensions:
•Check that the processor supports Intel SSE4 extensions.
•Ensure that the operating system supports SSSE3 and Intel SSE, SSE2, and SSE3. (Operating system support 
for Intel SSE implies sufficient support fo r SSSE3 and Intel SSE2, SSE3, and SSE4.) 
•Employ the optimization and schedulin g techniques described in the Intel®  64 and IA-32 Architectures Optimi-
zation Reference Manual (see Section 1.4, “Related Literature”).Vol. 1 12-19PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.12.2 Checking for Intel® SSE4.1 Support
Before an application attempts to use Intel SSE4.1 instru ctions, the application should follow the steps illustrated 
in Section 11.6.2, “Checking for Intel® SSE and SSE2 Su pport.” Next, use the additional step provided below:
Check that the processor supports Intel SSE4.1 (if CPUID.01H:ECX.SSE4_1[bit 19] = 1), Intel SSE3 (if 
CPUID.01H:ECX.SSE3[bit 0] = 1), and SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1). 
12.12.3 Checking for Intel® SSE4.2 Support
Before an application attempts to use the following Intel SSE4.2 instructions: PCMPESTRI/PCMPESTRM/PCMP-
ISTRI/PCMPISTRM, PCMPGTQ; the applic ation should follow the steps illustrate d in Section 11.6.2, “Checking for 
Intel® SSE and SSE2 Support.” Next, use the additional steps provided below:
•Check that the processor supports Intel SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1), Intel SSE4.1 (if 
CPUID.01H:ECX.SSE4_1[bit 19] = 1), and SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1). 
•Before an application attempts to use the CRC32 instruct ion, it must check that the processor supports Intel 
SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1).
•Before an application attempts to use the POPCNT instru ction, it must check that the processor supports Intel 
SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1) and POPCNT (if CPUID.01H:ECX.POPCNT[bit 23] = 1).
12.13 INTEL® AES-NI OVERVIEW
Intel AES-NI provides six instructions to accelerate sy mmetric block encryption/decryption of 128-bit data blocks 
using the Advanced Encryption Standard (AES) specified by the NIST publication FI PS 197. Specifically, two 
instructions (AESENC and AESENCLAST) target the AES encryption rounds; and two instructions (AESDEC and 
AESDECLAST) target AES decryption rounds using the Equi valent Inverse Cipher. One instruction (AESIMC) targets 
the Inverse MixColumn transformation primitive, and on e instruction (AESKEYGEN) targets generation of round 
keys from the cipher key for the AES encryption/decryption rounds.
AES supports encryption/decryption using cipher key length s of 128, 192, and 256 bits by processing the data 
block in 10, 12, and 14 rounds of predefined transformation s. Figure 12-5 depicts the cryptographic processing of 
a block of 128-bit plain text into cipher text. 
The predefined AES transformation primitives are described in the next few sections, they are also referenced in 
the operation flow of instruction reference page of these instructions.
12.13.1 Little-Endian Architecture an d Big-Endian Specification (FIPS 197)
FIPS 197 document defines the Advanced Encryption Standa rd (AES) and includes a set of test vectors for testing

FIPS 197 document defines the Advanced Encryption Standa rd (AES) and includes a set of test vectors for testing 
all of the steps in the algorithm, and can be used for testing and debugging. Figure 12-5.  AES State FlowPlain text AES StateRK(0)
XOR Rounds 2.. n-2
Round 1Last RK(1) RK(n-1)
AES State AES State Cipher text
AES-128: n = 10
AES-192: n = 12AES-256: n = 14Round 
n-112-20 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
The following observation is important for using the AES in structions offered in Intel 64 Architecture: FIPS 197 text 
convention is to write hex strings with the low-memory by te on the left and the high -memory byte on the right. 
Intel’s convention is the reverse. It is similar to the difference between Big Endian and Little Endian notations. 
In other words, a 128 bits vector in the FIPS document, wh en read from left to right, is encoded as [7:0, 15:8, 
23:16, 31:24, …127:120]. Note that inside the byte, the encodi ng is [7:0], so the first bit from the left is the most 
significant bit. In practice, the test vectors are written in hexadecimal notation, where pairs of hexadecimal digits 
define the different bytes. To translate the FIPS 197 notation  to an Intel 64 architecture compatible (“Little Endian”) 
format, each test vector needs to be byte-refle cted to [127:120,… 31:24, 23:16, 15:8, 7:0]. 
Example A: FIPS Test vector: 000102030405060708090a0b0c0d0e0fHIntel AES Hardware: 0f0e0d0c0b0a09080706050403020100H
It should be pointed out that the only thing at issue is a textual convention, and programmers do not need to 
perform byte-reversal in their code , when using the AES instructions.
12.13.1.1  AES Data Structure in Intel® 64 Architecture
The AES instructions that are defined in this document operate on one or on two 128 bits source operands: State 
and Round Key. From the architectural point of view, the state is input in an xmm register and the Round key is 
input either in an xmm register or a 128-bit memory location. 
In AES algorithm, the state (128 bits) can be viewed as four 32-bit doublewords (“Words” in AES terminology): X3, 
X2, X1, and X0. 
The state may also be viewed as a set of 16 bytes. The 16 bytes can also be viewed as a 4x4 matrix of bytes where 
S(i, j) with i, j = 0, 1, 2, 3 compose the 32-bit “words” as follows:
X0 = S (3, 0) S (2, 0) S (1, 0) S (0, 0)X1 = S (3, 1) S (2, 1) S (1, 1) S (0, 1)X2 = S (3, 2) S (2, 2) S (1, 2) S (0, 2)X3 = S (3, 3) S (2, 3) S (1, 3) S (0, 3)The following tables, Table 12-8 through Table 12-11, i llustrate various representations of a 128-bit state.
Example: 
FIPS vector: d4 bf 5d 30 e0 b4 52 ae b8 41 11 f1 1e 27 98 e5Table 12-8.  Byte and 32-Bit Word Representation of  a 128-Bit State
B y t e  # 1 5 1 4 1 3 1 2 1 1 1 0 9876543210
Bit Position 127-
120119-
112111-
103103-
9695-
8887-
8079-
7271-
6463-
5655-
4847-
4039-
3231-
2423-
1615-
87- 
0
127 - 96 95 - 64 64 - 32 31 - 0
State Word X3 X2 X1 X0
State Byte P O N M L K J I H G F E D C B A
Table 12-9.  Matrix Represen tation of a 128-Bit State
A E I M S(0, 0) S(0, 1) S(0, 2) S(0, 3)
B F J N S(1, 0) S(1, 1) S(1, 2) S(1, 3)
C G K O S(2, 0) S(2, 1) S(2, 2) S(2, 3)
D H L P S(3, 0) S(3, 1) S(3, 2) S(3, 3)Vol. 1 12-21PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
This vector has the “least significant” byte d4 and the sign ificant byte e5 (written in Big Endian format in the FIPS 
document). When it is translated to IA notations, the encoding is:
12.13.2 AES Transformations and Functions
The following functions and transformations are used in the algorithmic descriptions of AES instruction extensions AESDEC, AESDECLAST, AESENC, AESENCLAST, AESIMC, and AESKEYGENASSIST.
Note that these transformations are expressed here in a Little Endian format (and not as in the FIPS 197 docu-
ment).
•MixColumns(): A byte-oriented 4x4 matrix transformation on the matrix representation of a 128-bit AES state. 
A FIPS-197 defined 4x4 matrix is multiplied to each 4x1 column vector of the AES state. The columns are 
considered polynomials with coefficients in the Finite Field that is used in the definition of FIPS 197, the 
operations (“multiplication” and “addition”) are in that Finite Field, and the polynomials are reduced modulo 
x4+1. 
The MixColumns() transformation defines the relationship between each byte of the result state, represented
as S’(i, j) of a 4x4 matrix (see Section 12.13.1), as  a function of input state bytes, S(i, j), as follows
S’(0, j) := FF_MUL( 02H, S(0, j) ) XOR FF_M UL(03H, S(1, j) ) XOR S(2, j) XOR S(3, j)
S’(1, j) := S(0, j) XOR FF_MUL( 02H, S(1, j) ) XOR FF_MUL(03H, S(2, j) ) XOR S(3, j) 
S’(2, j) := S(0, j) XOR S(1, j) XOR FF_MUL( 02H, S(2, j) ) XOR FF_MUL(03H, S(3, j) ) S’(3, j) := FF_MUL(03H, S(0, j) ) XOR S(1, j) XOR S(2, j) XOR FF_MUL( 02H, S(3, j) ) where j = 0, 1, 2, 3. FF_MUL(Byte1, Byte2) denotes th e result of multiplying two elements (represented by
Byte1 and byte2) in the Finite Field representation  t h a t  d e f i n e s  A E S .  T h e  r e s u l t  o f  p r o d u c e d  b y e
FF_MUL(Byte1, Byte2) is an element in the Finite Field (represented as a byte). A Finite Field is a field with afinite number of elements, and when this number can be  represented as a power of 2 (2n), its elements can
be represented as the set of 2n binary strings of le ngth n. AES uses a finite field with n=8 (having 256
elements). With this representation, “addition” of two el ements in that field is a bit-wise XOR of their binary-
string representation, producing another element in the fi eld. Multiplication of two elements in that field is
defined using an irreducible polynomial (for AES, this polynomial is m(x) = x
8 + x4 + x3 + x + 1). In this
Finite Field representation, the bit value of bit position k of a byte represents the coefficient of a polynomial of
order k, e.g., 1010_1101B (ADH) is represented by the polynomial (x7 + x5 + x3 + x2 + 1). The byte value
result of multiplication of two elements is obtained  by a carry-less multiplication of the two corresponding
polynomials, followed by reductio n modulo the polynomial, where the remainder is calculated using
operations defined in the field. For example, FF_MUL(57H, 83H) = C1H, because the carry-less polynomial
multiplication of the polynomials re presented by 57H and 83H produces (x13 + x11 + x9 + x8 + x6 + x5 + x4
+ x3 + 1), and the remainder modulo m(x) is (x7 + x6 + 1).
•RotWord(): performs a byte-wise cyclic permutation (rotate right in little-endian byte order) on a 32-bit AES 
word.Table 12-10.  Little Endian Re presentation of a 128-Bit State
S t a t e  V a l u e e 59 82 71 ef 11 14 1b 8a e5 2b 4e 03 05 d b f d 4
Table 12-11.  Little Endian Repr esentation of a 4x4 Byte Matrix
A E I M d4 e0 b8 1e
B F J N bf b4 41 27
C G K O 5d 52 11 98
DHLP 3 0 a e f 1 e 512-22 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
The output word X’[j] of RotWord(X[j]) where X[j] repres ent the four bytes of column j, S(i, j), in descending
order X[j] = ( S(3, j), S(2, j), S(1, j), S(0, j) ); X’[j] = ( S’(3, j), S’(2, j), S’(1, j), S’(0, j) ) := ( S(0, j), S(3,
j), S(2, j), S(1, j) )
•ShiftRows(): A byte-oriented matrix transformation that processes the matrix representation of a 16-byte AES 
state by cyclically shifting the last three rows of th e state by different offset to the left, see Table 12-12.
•SubBytes(): A byte-oriented transformation that processes the 128-bit AES state by applying a non-linear 
substitution table (S-BOX) on each byte of the state.
The SubBytes() function defines the rela tionship between each byte of the result state S’(i, j) as a function of
input state byte S(i, j), by 
S’(i, j) := S-Box (S(i, j)[7:4], S(i, j)[3:0])
where S-BOX (S[7:4], S[3:0]) represents a look-up oper ation on a 16x16 table to return a byte value, see 
Table 12-13. 
•SubWord(): produces an output AES word (four bytes) fr om the four bytes of an input word using a non-linear 
substitution table (S-BOX).Table 12-12.  The ShiftRows Transformation
Matrix Representation of In put State Output of ShiftRows
AE IM A E I M
BF JN F J N B
CGKO K O C G
DHLP P D H L
Table 12-13.  Look-up Table Asso ciated with S-Box Transformation
S[3:0]
0123456789abcde f
S[7:4]0 63 7c 77 7b f2 6b 6f c5 30 01 67 2b fe d7 ab 76
1 ca 82 c9 7d fa 59 47 f0 ad d4 a2 af 9c a4 72 c0
2 b7 fd 93 26 36 3f f7 cc 34 a5 e5 f1 71 d8 31 15
3 04 c7 23 c3 18 96 05 9a 07 12 80 e2 eb 27 b2 75
4 09 83 2c 1a 1b 6e 5a a0 52 3b d6 b3 29 e3 2f 84
5 53 d1 00 ed 20 fc b1 5b 6a cb be 39 4a 4c 58 cf
6 d0 ef aa fb 43 4d 33 85 45 f9 02 7f 50 3c 9f a8
7 51 a3 40 8f 92 9d 38 f5 bc b6 da 21 10 ff f3 d2
8 cd 0c 13 ec 5f 97 44 17 c4 a7 7e 3d 64 5d 19 73
9 60 81 4f dc 22 2a 90 88 46 ee b8 14 de 5e 0b db
a e0 32 3a 0a 49 06 24 5c c2 d3 ac 62 91 95 e4 79
b e7 c8 37 6d 8d d5 4e a9 6c 56 f4 ea 65 7a ae 08
c ba 78 25 2e 1c a6 b4 c6 e8 dd 74 1f 4b bd 8b 8a
d 70 3e b5 66 48 03 f6 0e 61 35 57 b9 86 c1 1d 9e
e e1 f8 98 11 69 d9 8e 94 9b 1e 87 e9 ce 55 28 df

AE IM A E I M
BF JN F J N B
CGKO K O C G
DHLP P D H L
S[3:0]
f 8c a1 89 0d bf e6 42 68 41 99 2d 0f b0 54 bb 16Vol. 1 12-23PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
X’[j] = ( S’(3, j), S’(2, j), S’(1, j), S’(0, j) ) := ( S-Box (S(3, j)), S-Box( S(2, j) ), S-Box( S(1, j) ), S-Box(
S(0, j) ))
•InvMixColumns(): The inverse transformation of MixColumns().
The InvMixColumns() transformation defines the relationsh ip between each byte of the result state S’(i, j) as
a function of input state bytes, S(i, j), by 
S’(0, j) := FF_MUL( 0eH, S(0, j) ) XOR FF_MUL(0bH, S(1, j) ) XOR FF_MUL(0dH, S(2, j) ) XOR FF_MUL( 09H,
S(3, j) )
S’(1, j) := FF_MUL(09H, S(0, j) ) XOR FF_MUL( 0eH, S(1, j) ) XOR FF_MUL(0bH, S(2, j) ) XOR FF_MUL( 0dH,
S(3, j) )
S’(2, j) := FF_MUL(0dH, S(0, j) ) XOR FF_MUL( 09H, S(1, j) ) XOR FF_MUL( 0eH, S(2, j) ) XOR FF_MUL(0bH,
S(3, j) ) 
S’(3, j) := FF_MUL(0bH, S(0, j) ) XOR FF_MUL(0dH, S(1, j) ) XOR FF_MUL( 09H, S(2, j) ) XOR FF_MUL( 0eH,
S(3, j) ), where j = 0, 1, 2, 3.
•InvShiftRows(): The inverse transformation of InvShi ftRows(). The InvShiftRows() transforms the matrix 
representation of a 16-byte AES state by cyclically shifting  the last three rows of the state by different offset to 
the right, see Table 12-14.
•InvSubBytes(): The inverse transformation of SubBytes().
The InvSubBytes() transformation defines the relationship between each byte of the result state S’(i, j) as a
function of input state byte S(i, j), by 
S’(i, j) := InvS-Box (S(i, j)[7:4], S(i, j)[3:0])
where InvS-BOX (S[7:4], S[3:0]) represents a look-up operation on a 16x16 table to return a byte value, see 
Table 12-15. Table 12-14.  The InvShiftRows Transformation
AE IM A E I M
BF JN N B F J
CGKO K O C G
DHLP H L P D12-24 Vol. 1PROGRAMMING WITH INTEL® SSE3, SSSE3, INTEL® SSE4, AND INTEL® AES-NI
12.13.3 PCLMULQDQ
The PCLMULQDQ instruction performs carry-less multiplicati on of two 64-bit data into a 128-bit result. Carry-less 
multiplication of two 128-bit data into a 256-bi t result can use PCLMULQDQ as building blocks.
Carry-less multiplication is a component of many cryptograp hic systems. It is an important piece of implementing 
Galois Counter Mode (GCM) operation of block ciphers. GC M operation can be used in conjunction with AES algo-
rithms to add authentication capability. GCM usage mode ls also include IPsec, storage standard, and security 
protocols over fiber channel. Additiona lly, PCLMULQDQ can be used in calculat ions of hash functions and CRC using 
arbitrary polynomials.
12.13.4 Checking for Intel® AES-NI Support
Before an application attempts to use AESNI instructions  or PCLMULQDQ, the application should follow the steps 
illustrated in Section 11.6.2, “Checking for Intel® SSE an d SSE2 Support.” Next, use the additional step provided 
below:
Check that the processor supports Intel AES-NI (if CPUI D.01H:ECX.AESNI[bit 25] = 1); check that the processor 
supports PCLMULQDQ (if CPUID.01H:ECX.PCLMULQDQ[bit 1] = 1).Table 12-15.  Look-up Table Associ ated with InvS-Box Transformation
S[3:0]
S[7:4]0 52 09 6a d5 30 36 a5 38 bf 40 a3 9e 81 f3 d7 fb
1 7c e3 39 82 9b 2f ff 87 34 8e 43 44 c4 de e9 cb
2 54 7b 94 32 a6 c2 23 3d ee 4c 95 0b 42 fa c3 4e
3 08 2e a1 66 28 d9 24 b2 76 5b a2 49 6d 8b d1 25
4 72 f8 f6 64 86 68 98 16 d4 a4 5c cc 5d 65 b6 92
5 6c 70 48 50 fd ed b9 da 5e 15 46 57 a7 8d 9d 84
6 90 d8 ab 00 8c bc d3 0a f7 e4 58 05 b8 b3 45 06
7 d0 2c 1e 8f ca 3f 0f 02 c1 af bd 03 01 13 8a 6b
8 3a 91 11 41 4f 67 dc ea 97 f2 cf ce f0 b4 e6 73
9 96 ac 74 22 e7 ad 35 85 e2 f9 37 e8 1c 75 df 6e
a 47 f1 1a 71 1d 29 c5 89 6f b7 62 0e aa 18 be 1b
b fc 56 3e 4b c6 d2 79 20 9a db c0 fe 78 cd 5a f4
c 1f dd a8 33 88 07 c7 31 b1 12 10 59 27 80 ec 5f
d 60 51 7f a9 19 b5 4a 0d 2d e5 7a 9f 93 c9 9c ef
e a0 e0 3b 4d ae 2a f5 b0 c8 eb bb 3c 83 53 99 61
f 17 2b 04 7e ba 77 d6 26 e1 69 14 63 55 21 0c 7dVol. 1 13-1CHAPTER 13
MANAGING STATE USING THE XSAVE FEATURE SET
The XSAVE feature set extends the functionality of th e FXSAVE and FXRSTOR instructions (see Section 10.5, 
“FXSAVE and FXRSTOR Instructions”) by supporting the savi ng and restoring of processor state in addition to the 
x87 execution environment ( x87 state ) and the registers used by the streaming SIMD extensions ( SSE state ). 
The XSAVE feature set  comprises eight instructions. XGETBV and XS ETBV allow software to read and write the 
extended control register XCR0, which controls the operation of the XSAVE feature set. XSAVE, XSAVEOPT, 
XSAVEC, and XSAVES are four instructions that save processor state to memory; XRSTOR and XRSTORS are corre-
sponding instructions that load processor state from  memory. XGETBV, XSAVE, XSAVEOPT, XSAVEC, and XRSTOR 
can be executed at any privilege level; XSETBV, XSAVES, and XRSTORS can be executed only if CPL = 0. In addition 
to XCR0, the XSAVES and XRSTORS instructions are controlled also by the IA32_XSS MSR (index DA0H).
The XSAVE feature set organizes the state that manages into state components . Operation of the instructions is 
based on state-component bitmaps  that have the same format as XCR0 and as the IA32_XSS MSR: each bit 
corresponds to a state component. Section 13.1 discusses these state components and bitmaps in more detail.
Section 13.2 describes how the processor enumerates support for the XSAVE feature set and for XSAVE-enabled 
features  (those features that require the use of the XSAVE feature set for their enabling). Section 13.3 explains 
how software can enable the XSAVE feature set and XSAVE-enabled features.
The XSAVE feature set allows saving and loading pr ocessor state from a region of memory called an XSAVE area . 
Section 13.4 presents details of the XSAVE area and its organization. Each XSAVE-managed state component is 
associated with a section of the XSAVE area. Section 13. 5 describes in detail each of the XSAVE-managed state 
Section 13.7 through Section 13.12 describe the operatio n of XSAVE, XRSTOR, XSAVEOPT, XSAVEC, XSAVES, and 
XRSTORS, respectively.
Section 13.13 provides some details about memory accesse s performed by instructions in the XSAVE feature set, 
and Section 13.14 describes a facility called extended feature disable  (XFD). 
13.1 XSAVE-SUPPORTED FEATURES  AND STATE-COMPONENT BITMAPS
The XSAVE feature set supports the saving and restoring of state components , each of which is a discrete set of 
processor registers (or parts of registers). In general, ea ch such state component corresponds to a particular CPU 
feature. Such a feature is XSAVE-supported . Some XSAVE-supported features use registers in multiple XSAVE-
managed state components.
The XSAVE feature set organizes the state compon ents of the XSAVE-supported features using state-component 
bitmaps . A state-component bitmap comprises 64 bits; each bit in such a bitmap corresponds to a single state 
component. The following bits are defined in state-compon ent bitmaps (details on individual state components are 
provided in subsections of Section 13.5):
•Bit 0 corresponds to the state component us ed for the x87 FPU execution environment ( x87 state ).
•Bit 1 corresponds to the state component used for registers used by the streaming SIMD extensions ( SSE 
state ).
•Bit 2 corresponds to the state component used for the additional register state used by the Intel® Advanced 
Vector Extensions ( AVX state ).
•Bits 4:3 correspond to the two state components used for the additional register state used by Intel® Memory 
Protection Extensions ( MPX state ):
— State component 3 is used for the 4 128-bit bounds registers BND0–BND3 ( BNDREGS state ).
— State component 4 is used for the 64-bit user-mod e MPX configuration register BNDCFGU and the 64-bit 
MPX status register BNDSTATUS ( BNDCSR state ).
•Bits 7:5 correspond to the three state components used  for the additional register state used by Intel® 
Advanced Vector Extensions 512 ( AVX-512 state ):13-2 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
— State component 5 is used for the 8 64-bit opmask registers k0–k7 ( opmask state ).
— State component 6 is used for the upper 256 bits of  the registers ZMM0–ZMM15. These 16 256-bit values 
are denoted ZMM0_H–ZMM15_H ( ZMM_Hi256 state ).
— State component 7 is used for the 16 512-bit registers ZMM16–ZMM31 ( Hi16_ZMM state ).
•Bit 8 corresponds to the state component used for the Intel Processor Trace MSRs ( PT state ).
•Bit 9 corresponds to the state component used for the protection-key feature’s register PKRU ( PKRU state ).
•Bit 10 corresponds to the state component used for th e IA32_PASID MSR used by the ENQCMD instruction for 
a process address space identifiers ( PASID state ).
•Bits 12:11 correspond to the two state components used fo r the additional register state used by Control-Flow 
Enforcement Technology ( CET state ):
— State component 11 is used for the 2 MSRs controlling user-mode functionality for CET ( CET_U state ).
— State component 12 is used for the 3 MSRs containi ng shadow-stack pointers for privilege levels 0–2

— State component 12 is used for the 3 MSRs containi ng shadow-stack pointers for privilege levels 0–2 
(CET_S state ).
•Bit 13 corresponds to the state component used for an MSR used to control hardware duty cycling ( HDC 
state ).
•Bit 14 corresponds to the state component used for user interrupts ( UINTR state ).
•Bit 15 corresponds to the state component used for last-branch record configuration ( LBR state ).
•Bit 16 corresponds to the state component used for an MSR used to control hardware P-states ( HWP state ).
•Bits 18:17 correspond to the two state components used  for the additional register state used by Intel® 
Advanced Matrix Extensions ( AMX state ):
— State component 17 is used for the 64-byte TILECFG register ( TILECFG state ).
— State component 18 is used for the 8192 bytes of tile data ( TILEDATA state ).
Bits in the range 62:19 are not currently defined in st ate-component bitmaps and are reserved for future expan-
sion. As individual state components are defined using thos e bits, additional sub-sections will be updated within 
Section 13.5 over time. Bit 63 is used for special functi onality in some bitmaps and does not correspond to any 
state component.
The state component corresponding to bit i of state-component bitmaps is called state component i. Thus, x87 
state is state component 0; SSE state is state component 1; AVX state is state component 2; MPX state comprises 
state components 3–4; AVX-512 state comprises state comp onents 5–7; PT state is state component 8; PKRU state 
is state component 9; PASID state is state component 10; CET state comprises state components 11–12; HDC 
state is state component 13; UINTR state is state compon ent 14; LBR state is state component 15; HWP state is 
state component 16; AMX state comprises state components 17–18.
The XSAVE feature set uses state-component bitmaps in mult iple ways. Most of the instructions use an implicit 
operand (in EDX:EAX), called the instruction mask , which is the state-component bitmap that specifies the state 
components on which the instruction operates.
Some state components are user state components , and they can be managed by the entire XSAVE feature set. 
Other state components are supervisor state components , and they can be managed only by XSAVES and 
XRSTORS. The state components corresponding to bit 9, to bi ts 18:17, and to bits in the range 7:0 are user state 
components; those corresponding to bit 8, to bits in th e range 13:10, and to bits 16:14 are supervisor state 
Extended control register XCR0 contains a state-componen t bitmap that specifies the user state components that 
software has enabled the XSAVE feature set to manage. If the bit corresponding to a state component is clear in 
XCR0, instructions in the XSAVE feature set will not operate on that state comp onent, regardless of the value of the 
instruction mask.
The IA32_XSS MSR (index DA0H) contains a state-compon ent bitmap that specifies the supervisor state compo-
nents that software has enabled XSAVES and XRSTORS to manage (XSAVE, XSAVEC, XSAVEOPT, and XRSTOR cannot manage supervisor state components). If the bi t corresponding to a state component is clear in the 
IA32_XSS MSR, XSAVES and XRSTORS will not operate on that state component, regardless of the value of the 
instruction mask.Vol. 1 13-3MANAGING STATE USING THE XSAVE FEATURE SET
Some XSAVE-supported features can be used only if XCR0 has been configured so that the features’ state compo-
nents can be managed by the XSAVE feature set. (This applie s only to features with user state components.) Such 
state components and features are XSAVE-enabled . In general, the processor will not modify (or allow modifica-
tion of) the registers of a state component of an XSAVE- enabled feature if the bit corresponding to that state 
component is clear in XCR0. (If software clears such a bit in XCR0, the processor preserves the corresponding state component.) If an XSAVE-enabled feature has not been fully  enabled in XCR0, execution of any instruction defined 
for that feature causes an in valid-opcode exception (#UD).
As will be explained in Section 13.3, the XSAVE featur e set is enabled only if CR4.OSXSAVE[bit 18] = 1. If 
CR4.OSXSAVE = 0, the processor treats XSAVE-enabled state features and their state components as if all bits in 
XCR0 were clear; the state components cannot be modified and the features’ instructions cannot be executed.
The state components for x87 state, for SSE state, for PT st ate, for PKRU state, for PASID state, for CET state, for 
HDC state, for UINTR state, for LBR state, and for HWP state are XSAVE-managed but the corresponding features 
are not XSAVE-enabled. Processors allow modification of this state, as well as execution of x87 FPU instructions 
and SSE instructions and use of Intel Processor Trac e, protection keys, the ENQCMD instruction and the 
IA32_PASID MSR, CET, hardware duty cycling, user inte rrupts, LBRs, and hardware P-states, regardless of the 
value of CR4.OSXSAVE and XCR0.
13.2 ENUMERATION OF CPU SUPPORT FOR XSAVE INSTRUCTIONS AND XSAVE-
SUPPORTED FEATURES
A processor enumerates support for the XSAVE feature set an d for features supported by that feature set using the 
CPUID instruction. The following items provide specific details:
•CPUID.1:ECX.XSAVE[bit 26] enumerates general support for the XSAVE feature set:
— If this bit is 0, the processor does not support any of the following instructions: XGETBV, XRSTOR, 
XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, an d XSETBV; the processor provides no further 
enumeration through CPUID function 0DH (see below).
— If this bit is 1, the processor supports the follow ing instructions: XGETBV, XR STOR, XSAVE, and XSETBV.1 
Further enumeration is provided  through CPUID function 0DH.
CR4.OSXSAVE can be set to 1 if and only if CPUID.1:ECX.XSAVE[bit 26] is enumerated as 1.
•CPUID function 0DH enumerates details of CPU support through a set of sub-functions. Software selects a 
specific sub-function by the value placed in the ECX register. The following item s provide specific details:
— CPUID function 0DH, sub-function 0.
•EDX:EAX is a bitmap of all the user state components that can be managed using the XSAVE feature 
set. A bit can be set in XCR0 if and only if the co rresponding bit is set in this bitmap. Every processor 
that supports the XSAVE feature set will set EA X[0] (x87 state) and EAX[1] (SSE state).
If EAX[ i]=  1  ( f o r  1<  i < 32) or EDX[ i–32] = 1 (for 32 ≤ i< 63), sub-function i enumerates details for 
state component i (see below).
•ECX enumerates the size (in bytes) required by the XSAVE instruction for an XSAVE area containing all 
the user state components supported by this processor.
•EBX enumerates the size (in bytes) required by the XSAVE instruction for an XSAVE area containing all 
the user state components corresponding to bits currently set in XCR0.
— CPUID function 0DH, sub-function 1.
•EAX[0] enumerates support for the XSAVEOPT instruct ion. The instruction is supported if and only if 
this bit is 1. If EAX[0] = 0, execution of XSAVEOPT causes an invalid-opcode exception (#UD).
•EAX[1] enumerates support for compaction extensions  to the XSAVE feature set. The following are 
supported if this bit is 1:
1. If CPUID.1:ECX.XSAVE[bit 26] = 1, XGETBV and XSETBV may be ex ecuted with ECX = 0 (to read an d write XCR0). Any support for 
execution of these instructions with other values of ECX is enumerated separately.13-4 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
—The compacted format of the extended region of XSAVE areas (see Section 13.4.3). 
—The XSAVEC instruction. If EAX[1] = 0,  execution of XSAVEC causes a #UD.
—Execution of the compacted form of XRSTOR (see Section 13.8).
•EAX[2] enumerates support for execution of XGETBV with ECX = 1. This allows software to determine 
the state of the init optimization. See Section 13.6.
•EAX[3] enumerates support for XSAVES, XRSTORS, and the IA32_XSS MSR. If EAX[3] = 0, execution of XSAVES or XRSTORS causes a #UD; an atte mpt to access the IA32_XSS MSR using RDMSR or 
WRMSR causes a general-protection exception (#GP). Every processor that supports a supervisor state 
component sets EAX[3]. Every processor that sets EA X[3] (XSAVES, XRSTORS, IA32_XSS) will also set 
EAX[1] (the compaction extensions).
•EAX[4] enumerates general support for extended fe ature disable (XFD). See Section 13.14 for details.
•EAX[31:5] are reserved.
•EBX enumerates the size (in bytes) defined as follows:
—If EAX[3] is enumerated as 1, EBX enumerates th e size required by the XSAVES instruction for an 
XSAVE area containing all the state components corresponding to bits currently set in XCR0 | 
IA32_XSS.
—If EAX[3] is enumerated as 0 and EAX[1] is enumer ated as 1, EBX enumerates the size required by 
the XSAVEC instruction for an XSAVE area containing all the state components corresponding to bits 
currently set in XCR0.
—If EAX[1] and EAX[3] are both enum erated as 0, EBX enumerates zero.
•EDX:ECX is a bitmap of all the supervisor state components that can be managed by XSAVES and

IA32_XSS.
•EDX:ECX is a bitmap of all the supervisor state components that can be managed by XSAVES and 
XRSTORS. A bit can be set in the IA32_XSS MSR if and only if the corresponding bit is set in this bitmap.
NOTE
In summary, the XSAVE feature set supports state component i (0≤ i< 63) if one of the following 
is true: (1) i< 32 and CPUID.(EAX=0DH,ECX=0):EAX[ i]=  1 ;  ( 2 ) i≥ 32 and 
CPUID.(EAX=0DH,ECX=0):EAX[ i–32] = 1; (3) i< 32 and CPUID.(EAX=0DH,ECX=1):ECX[ i]=  1 ;  
or (4) i≥ 32 and CPUID.(EAX=0DH,ECX=1):EDX[ i–32] = 1. The XSAVE feature set supports user 
state component i if (1) or (2) holds; if (3) or (4) holds, state component i is a supervisor state 
component and support is limited to XSAVES and XRSTORS.
— CPUID function 0DH, sub-function i (i > 1). This sub-function enumerates details for state component i. If 
the XSAVE feature set supports state component i (see note above), the foll owing items provide specific 
details:
•EAX enumerates the size (in bytes) required for state component i.
•If state component i is a user state component, EBX enumerates the offset (in bytes, from the base of 
the XSAVE area) of the section used for state component i. (This offset applies only when the standard 
format for the extended region of the XSAV E area is being used; see Section 13.4.3.)
•If state component i is a supervisor state component, EBX returns 0.
•If state component i is a user state component, ECX[0] return 0; if state component i is a supervisor 
state component, ECX[0] returns 1.
•The value returned by ECX[1] indica tes the alignment of state component i when the compacted format 
of the extended region of an XSAVE area is used  (see Section 13.4.3). If ECX[1] returns 0, state 
component i is located immediately following the preceding state component; if ECX[1] returns 1, state 
component i is located on the next 64-byte boundary following the preceding state component.
•If the processor supports XFD for state component i, ECX[2] returns 1; otherwise, ECX[2] returns 0.
•ECX[31:3] and EDX return 0.
If the XSAVE feature set does not support state component i, sub-function i returns 0 in EAX, EBX, ECX, and 
EDX.Vol. 1 13-5MANAGING STATE USING THE XSAVE FEATURE SET
13.3 ENABLING THE XSAVE FEATUR E SET AND XSAVE-ENABLED FEATURES
Software enables the XSAVE feature set by setting CR4.OS XSAVE[bit 18] to 1 (e.g., with the MOV to CR4 instruc-
tion). If this bit is 0, execution of any of XGETBV, XRSTOR, XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and 
XSETBV causes an invalid-opcode exception (#UD).
When CR4.OSXSAVE = 1 and CPL = 0, executing the XSETBV instruction with ECX = 0 writes the 64-bit value in 
EDX:EAX to XCR0 (EAX is written to XCR0[31:0] and EDX to XCR0[63:32]). (Execution of the XSETBV instruction 
causes a general-protection fault — #GP — if CPL > 0.) The following items provide details regarding individual bits 
in XCR0:
•XCR0[0] is associated with x87 state (see Section 13.5.1). XCR0[0] is always 1. It has that value coming out of 
RESET. Executing the XSETBV instruct ion causes a general-protection fault (#GP) if ECX = 0 and EAX[0] is 0.
•XCR0[1] is associated with SSE state (see Section 13.5.2 ). Software can use the XSAVE feature set to manage 
SSE state only if XCR0[1] = 1. The value of XCR0[1] in no way determines whether software can execute SSE 
instructions (these instructions can be executed even if XCR0[1] = 0).
XCR0[1] is 0 coming out of RESET. As noted in Sectio n 13.2, every processor that supports the XSAVE feature 
set allows software to set XCR0[1].
•XCR0[2] is associated with AVX state (see Section 13.5.3). Software can use the XSAVE feature set to manage 
AVX state only if XCR0[2] = 1. In a ddition, software can execute Intel AVX instructions only if CR4.OSXSAVE = 
XCR0[2] = 1. Otherwise, any execution of an Intel AV X instruction causes an invalid-opcode exception (#UD).
XCR0[2] is 0 coming out of RESET. As noted in Section 13.2, a processor allows software to set XCR0[2] if and 
only if CPUID.(EAX=0DH,ECX =0):EAX[2] = 1. In addition, executing th e XSETBV instruction causes a general-
protection fault (#GP) if ECX = 0 and EAX[2:1] has the value 10b; that is, software cannot enable the XSAVE 
feature set for AVX state but not for SSE state.
As noted in Section 13.1, the processor will preserve  AVX state unmodified if software clears XCR0[2]. 
However, clearing XCR0[2] while AVX state is not in its initial configuration may cause SSE instructions to incur 
a power and performance penalty. See Section 14.5.3, “Enable the Use Of XSAVE Feature Set And XSAVE State 
Components,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for how 
system software can avoid this penalty.
•XCR0[4:3] are associated with MPX state (see Section 13.5.4). Software can use the XSAVE feature set to 
manage MPX state only if XCR0[4:3] = 11b. In addi tion, MPX instructions operate as defined only if 
CR4.OSXSAVE = 1 and XCR0[4:3] = 11b. Otherwise, execut ion of an MPX instruction causes no operation (as 
a NOP instruction); in addition, executions of CALL, RET, JMP, and Jcc do not initialize the bounds registers, and 
they ignore any F2H (BND) prefix.1
XCR0[4:3] have value 00b coming out of RESET. As noted in Section 13.2, a processor allows software to set 
XCR0[4:3] to 11b if and only if CP UID.(EAX=0DH,ECX=0):EAX[4:3] = 11b. In addition, executing the XSETBV 
instruction causes a general-protection fault (#GP) if  ECX = 0, EAX[4:3] is neither 00b nor 11b; that is, 
software can enable the XSAVE feature set for MPX stat e only if it does so for both state components.
As noted in Section 13.1, the processor will preserve  MPX state unmodified if software clears XCR0[4:3].
•XCR0[7:5] are associated with AVX-512 state (see Section 13.5.5). Software can use the XSAVE feature set to 
manage AVX-512 state only if XCR0[7:5] = 111b. In addition, software can execute Intel AVX-512 instructions only if CR4.OSXSAVE = 1 and XCR0[7:5] = 111b. Otherw ise, any execution of an Intel AVX-512 instruction 
causes an invalid-opcode exception (#UD).
XCR0[7:5] have value 000b coming out of RESET. As note d in Section 13.2, a processor allows software to set 
XCR0[7:5] to 111b if and only if  CPUID.(EAX=0DH,ECX=0):EAX[7:5] = 111b. In addition, executing the 
XSETBV instruction causes a general-protection fault (# GP) if ECX = 0, EAX[7:5] is not 000b, and any bit is 
clear in EAX[2:1] or EAX[7:5]; that is, software can enable the XSAVE feature set for AVX-512 state only if it 
does so for all three state components, and only if it also  does so for AVX state and SSE state. This implies that 
the value of XCR0[7:5] is always either 000b or 111b.
As noted in Section 13.1, the processor will preserve AVX-512 state unmodified if software clears XCR0[7:5]. 
However, clearing XCR0[7:5] while AVX-512 state is not in its initial configuration may cause SSE and Intel AVX 
instructions to incur a power and performance penalty.  See Section 14.5.3, “Enable the Use Of XSAVE Feature 
1. Prior to the introduction of M PX, the opcodes defining MPX inst ructions operated as NOP, and the CALL, RET, JMP, and Jcc inst ruc-
tions ignored any F2H prefix.13-6 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
Set And XSAVE State Components,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 3A, for how system software can avoid this penalty.
•XCR0[9] is associated with PKRU state (see Section 13.5.7). Software can use the XSAVE feature set to manage PKRU state only if XCR0[9] = 1. The value of XCR0[9] in no way determines whether software can use 
protection keys or execute other instructions that access PKRU state (these instructions can be executed even 
if XCR0[9] = 0).
XCR0[9] is 0 coming out of RESET. As noted in Section 13.2, a processor allows software to set XCR0[9] if and 
only if CPUID.(EAX=0 DH,ECX=0):EAX[9] = 1.
•XCR0[18:17] are associated with AMX state (see Section 13.5.5). Software can use the XSAVE feature set to 
manage AMX state only if XCR0[18:17] = 11b. In addition, software can execute Intel AMX instructions only if 
CR4.OSXSAVE = 1 and XCR0[18:17] = 11b. Otherwise, any execution of an Intel AMX instruction causes an 
invalid-opcode exception (#UD).
XCR0[18:17] have value 00b coming out of RESET. As noted in Section 13.2, a processor allows software to set 
XCR0[18:17] to 11b if and only if CPUID.(EAX=0DH,E CX=0):EAX[18:17] = 11b. In addition, executing the 
XSETBV instruction causes a general-protec tion fault (#GP) if ECX = 0 and EAX[17] ≠ EAX[18] (TILECFG and 
TILEDATA must be enabled together). This implies that the value of XCR0[18:17] is always either 00b or 11b.
While Intel AMX instructions can be executed only in 64-bit mode, instructions of the XSAVE feature set can 
operate on TILECFG and TILEDATA in any mode. It is recommended that only 64-bit operating systems enable 
Intel AMX by setting XCR0[18:17].
•XCR0[63:19], XCR0[16:10], and XCR0[8] are reserved.1 Executing the XSETBV instruction causes a general-
protection fault (#GP) if ECX = 0 and any corresponding bit in EDX:EAX is no t 0. These bits in XCR0 are all 0 
coming out of RESET.

Software operating with CPL > 0 may need to determine whether the XSAVE feature set and certain XSAVE-
enabled features have been enabled. If CPL > 0, exec ution of the MOV from CR4 instruction causes a general-
protection fault (#GP). The following alternative mechanis ms allow software to discover the enabling of the XSAVE 
feature set regardless of CPL:
•The value of CR4.OSXSAVE is returned in CPUID.1:ECX.OSXSAVE[bit 27]. If software determines that 
CPUID.1:ECX.OSXSAVE = 1, the processor supports the XSAVE feature set and the feature set has been enabled in CR4.
•Executing the XGETBV instruction wi th ECX = 0 returns the value of XC R0 in EDX:EAX. XGETBV can be 
executed if CR4.OSXSAVE = 1 (if CPUID.1:ECX.OSXSAVE = 1), regardless of CPL.
Thus, software can use the following algorithm to determine the support and enabling for the XSAVE feature set:
1. Use CPUID to discover the value of CPUID.1:ECX.OSXSAVE.
— If the bit is 0, either the XSAVE feature set is not supported by the processor or has not been enabled by 
software. Either way, the XSAVE feature set is not av ailable, nor are XSAVE-enabled features such as AVX.
— If the bit is 1, the processor supports the XSAVE feat ure set — including the XGETBV instruction — and it 
has been enabled by software. The XSAVE feature set can be used to manage x87 state (because XCR0[0] is always 1). Software requiring more detailed information can go on to the next step.
2. Execute XGETBV with ECX = 0 to discover the value of  XCR0. If XCR0[1] = 1, the XSAVE feature set can be 
used to manage SSE state. If XCR0[2] = 1, the XSAVE feature set can be used to manage AVX state and 
software can execute Intel AVX instructions. If XCR0[4:3 ] is 11b, the XSAVE feature set can be used to manage 
MPX state and software can execute Intel MPX instructio ns. If XCR0[7:5] is 111b, the XSAVE feature set can be 
used to manage AVX-512 state and software can exec ute Intel AVX-512 instructions. If XCR0[9] = 1, the 
XSAVE feature set can be used to manage PKRU state.
The IA32_XSS MSR (with MSR index DA0H) is zero  coming out of RESET. If CR4.OSXSAVE = 1, 
CPUID.(EAX=0DH,ECX=1):EAX[3] = 1, and CPL = 0, execut ing the WRMSR instruction with ECX = DA0H writes 
the 64-bit value in EDX:EAX to the IA32_XSS MS R (EAX is written to IA32_XSS[31:0] and EDX to 
IA32_XSS[63:32]). The following items provide detail s regarding individual bits in the IA32_XSS MSR:
1. Bit 8 and bits 16:10 correspond to supervisor state components. Since bits can be set in XCR0 only for user state components, t hose 
bits of XCR0 must be 0.Vol. 1 13-7MANAGING STATE USING THE XSAVE FEATURE SET
•IA32_XSS[8] is associated with PT state (see Sectio n 13.5.6). Software can use XSAVES and XRSTORS to 
manage PT state only if IA32_XSS[8] = 1. The value of  IA32_XSS[8] does not determine whether software can 
use Intel Processor Trace (the feature can be used even if IA32_XSS[8] = 0).
•IA32_XSS[10] is associated with PASID state (see Section 13.5.8). Software can use the XSAVES and 
XRSTORS to manage PASID state only if IA32_XSS[10] = 1. The value of IA32_XSS[10] does not determine 
whether software can use the ENQCMD instruction, wh ich uses the IA32_PASID MSR. (ENQCMD can be used 
even if IA32_XSS[10] is 0.)
•IA32_XSS[12:11] are associated with CET state (see Section 13.5.9), IA32_XSS[11] with CET_U state and 
IA32_XSS[12] with CET_S state. Software can use the XSAVES and XRSTORS to manage CET_U state (respec-
tively, CET_S state) only if IA32_XSS[11] = 1 (respectively, IA32_XSS[12] = 1). The value of 
IA32_XSS[12:11] does not determine whether software can us e CET (the feature can be used even if either of 
IA32_XSS[12:11] is 0).
•IA32_XSS[13] is associated with HDC state (see Section 13.5.10). Software can use XSAVES and XRSTORS to 
manage HDC state only if IA32_XSS[13] = 1. The value of  IA32_XSS[13] does not determine whether software 
can use hardware duty cycling (the feature can be used even if IA32_XSS[13] = 0).
•IA32_XSS[14] is associated with UINTR state (see Section 13.5.11). Software can use XSAVES and XRSTORS 
to manage UINTR state only if IA32_XSS[14] = 1. Th e value of IA32_XSS[14] does not determine whether 
software can use user interrupts (the feature can be used even if IA32_XSS[14] = 0).
•IA32_XSS[15] is associated with LBR state (see Section 13.5.12). Software can use XSAVES and XRSTORS to 
manage LBR state only if IA32_XSS[15] = 1. The value of  IA32_XSS[15] does not determine whether software 
can use LBRs (the feature can be used even if IA32_XSS[15] = 0).
•IA32_XSS[16] is associated with HWP state (see Section 13.5.13). Software can use XSAVES and XRSTORS to manage HWP state only if IA32_XSS[16] = 1. The value of IA32_XSS[16] does not determine whether 
software can use hardware P-states (the feature can be used even if IA32_XSS[16] = 0).
•IA32_XSS[63:17], IA32_XSS[9] and IA32_XSS[7:0] are reserved.1 Executing the WRMSR instruction causes 
a general-protection fault (#GP) if ECX = DA0H and any corresponding bit in EDX:EAX is not 0. These bits in 
XCR0 are all 0 coming out of RESET.
The IA32_XSS MSR is 0 coming out of RESET.There is no mechanism by which software operating wi th CPL > 0 can discover the value of the IA32_XSS MSR.
13.4 XSAVE AREA
The XSAVE feature set includes instructions that save and restore the XSAVE-managed state components to and 
from memory: XSAVE, XSAVEOPT, XSAVEC, and XSAVES (for saving); and XRSTOR and XRSTORS (for restoring). 
The processor organizes the state components in a region of memory called an XSAVE area . Each of the save and 
restore instructions takes a memory operand that specifie s the 64-byte aligned base address of the XSAVE area on 
which it operates.
Every XSAVE area has the following format:
•The legacy region . The legacy region of an XSAVE area comprises the 512 bytes starting at the area’s base 
address. It is used to manage the state components for x87 state and SSE state. The legacy region is described 
in more detail in Section 13.4.1.
•The XSAVE header . The XSAVE header of an XSAVE area comprises the 64 bytes starting at an offset of 512 
bytes from the area’s base address. The XSAVE header  is described in more detail in Section 13.4.2.
•The extended region . The extended region of an XSAVE area starts  at an offset of 576 bytes from the area’s 
base address. It is used to manage the state compon ents other than those for x87 state and SSE state. The 
extended region is described in more detail in Section 13 .4.3. The size of the extended region is determined by 
which state components the processor supports and whic h bits have been set in XCR0 and IA32_XSS (see 
Section 13.3).
1. Bit 9 and bits 7:0 correspond to user state components. Since bi ts can be set in the IA32_XSS MSR only for supervisor state co mpo-
nents, those bits of  the MSR must be 0.13-8 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
13.4.1 Legacy Region of an XSAVE Area
The legacy region of an XSAVE area comprises the 512 bytes starting at the area’s base address. It has the same 
format as the FXSAVE area (see Sect ion 10.5.1). The XSAVE feature set uses the legacy area for x87 state (state 
component 0) and SSE state (state component 1). Table 13- 1 illustrates the format of the first 416 bytes of the 
legacy region of an XSAVE area.
bytes 31:24 and bytes 415:160. The XSAVE feature set do es not use bytes 511:416; bytes 463:416 are reserved.
Section 13.7 through Section 13.9 provide details of how instructions in the XSAVE feature set use the legacy 
region of an XSAVE area.Table 13-1.  Format of the Legacy Region of an XSAVE Area
FIP[63:48] or 
reserved FCS or 
FIP[47:32] FIP[31:0] FOP Rsvd. FTW FSW FCW 0
MXCSR_MASK MXCSRFDP[63:48] 
or reserved FDS or 
FDP[47:32] FDP[31:0] 16
XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
XMM15 400Vol. 1 13-9MANAGING STATE USING THE XSAVE FEATURE SET
13.4.2 XSAVE Header
The XSAVE header of an XSAVE area comprises the 64 bytes starting at offset 512 from the area’s base address:
•Bytes 7:0 of the XSAVE header is a state-component bitmap (see Section 13.1) called XSTATE_BV . It 
identifies the state components in the XSAVE area.
•Bytes 15:8 of the XSAVE header is a state-component bitmap called XCOMP_BV . It is used as follows:
— XCOMP_BV[63] indicates the format of the extended regi on of the XSAVE area (see Section 13.4.3). If it is 
clear, the standard format is used. If it is set, the compacted format is used; XCOMP_BV[62:0] provide 
format specifics as specified in Section 13.4.3.
— XCOMP_BV[63] determines which form of the XRSTOR in struction is used. If the bit is set, the compacted

XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
— XCOMP_BV[63] determines which form of the XRSTOR in struction is used. If the bit is set, the compacted 
form is used; otherwise, the standard form is used. See Section 13.8.
— All bits in XCOMP_BV should be 0 if the processor do es not support the compaction extensions to the XSAVE 
feature set.
•Bytes 63:16 of the XSAVE header are reserved.
Section 13.7 through Section 13.9 provide details of ho w instructions in the XSAVE feature set use the XSAVE 
header of an XSAVE area.
13.4.3 Extended Region of an XSAVE Area
The extended region of an XSAVE area starts at byte o ffset 576 from the area’s base address. The size of the 
extended region is determined by which state components  the processor supports and which bits have been set in 
XCR0 | IA32_XSS (see Section 13.3). The XSAVE feature se t uses the extended area for each state component i, 
where i≥ 2.
The extended region of the an XSAVE area may have one of two formats. The standard format  is supported by all 
processors that support th e XSAVE feature set; the compacted format  is supported by those processors that 
support the compaction extensions to the XSAVE feature set (see Section 13.2). Bit 63 of the XCOMP_BV field in 
the XSAVE header (see Section 13.4.2) indicates which format is used.
The following items describe the two possible formats of the extended region:
•Standard format.  Each state component i (i≥ 2) is located at the byte offs et from the base address of the 
XSAVE area enumerated in CPUID.(E AX=0DH,ECX= i):EBX. (CPUID.(EAX=0DH,ECX= i):EAX enumerates the 
number of bytes required for state component i.
•Compacted format.  Each state component i (i≥ 2) is located at a byte offset from the base address of the 
XSAVE area based on the XCOMP_BV field in the XSAVE header:
—I f  X C O M P _ B V [ i] = 0, state component i is not in the XSAVE area.
—I f  X C O M P _ B V [ i] = 1, state component i is located at a byte offset locationI from the base address of the 
XSAVE area, where locationI is determined by the following items:
•If XCOMP_BV[ j] = 0 for every j, 2≤ j< i, locationI is 576. (This item applies if i is the first bit set in 
bits 62:2 of the XCOMP_BV; it implies that state component i is located at the beginning of the 
extended region.) 
•Otherwise, let j, 2≤ j< i, be the greatest value such that XCOMP_BV[ j] = 1. Then locationI is 
determined by the following values: locationJ; sizeJ, as enumerated in CPUID.(EAX=0DH,ECX= j):EAX; 
and the value of alignI, as enumerated in CPUID.(EAX=0DH,ECX= i):ECX[1]:
—If alignI= 0, locationI= locationJ + sizeJ. (This item implies that state component i is located 
immediately following the preceding state component whose bit is set in XCOMP_BV.)
—If alignI= 1, locationI= ceiling( locationJ + sizeJ, 64). (This item implies that state component i is 
located on the next 64-byte boundary following th e preceding state component whose bit is set in 
XCOMP_BV.)13-10 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
13.5 XSAVE-MANAGED STATE
The section provides details regarding how the XSAVE feature set interacts with the various XSAVE-managed state 
Unless otherwise state, the state pertaining to a particul ar state component is saved beginning at byte 0 of the 
section of the XSAVE are corresponding to that state component.
13.5.1 x87 State
Instructions in the XSAVE feature set can manage th e same state of the x87 FPU execution environment ( x87 
state ) that can be managed using the FXSAVE and FXRSTOR instructions. They organize all x87 state as a user 
state component in the legacy region of the XSAVE area  (see Section 13.4.1). This region is illustrated in 
Table 13-1; the x87 state is listed below, along with de tails of its interactions with the XSAVE feature set:
•Bytes 1:0, 3:2, 7:6. These are used for the x87 FPU Control Word (FCW), the x87 FPU Status Word (FSW), and 
the x87 FPU Opcode (FOP), respectively.
—F o r  e a c h  j, 0≤ j≤ 7, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save a 0 into bit j of byte 4 if x87 FPU data 
register ST j has a empty tag; otherwise, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save a 1 into bit j of byte 
4.
—F o r  e a c h  j, 0≤ j≤ 7, XRSTOR and XRSTORS establish the tag value for x87 FPU data register ST j as follows. 
If bit j of byte 4 is 0, the tag for ST j in the tag register for that data register is marked empty (11B); 
otherwise, the x87 FPU sets the tag for ST j based on the value being loaded into that register (see below).
•If CPUID.(EAX=07H,ECX=0H ):EBX[bit 13] = 0, bytes 13:12 are used for x87 FPU Instruction Pointer 
Selector (FCS). Otherwise, XSAVE, XSAVEOPT, XS AVEC, and XSAVES save these bytes as 0000H, and 
XRSTOR and XRSTORS ignore them.
•If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0, bytes 21:20 are used for x87 FPU Data Pointer Selector 
(FDS). Otherwise, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save these bytes as 0000H; and XRSTOR 
and XRSTORS ignore them.
•Bytes 31:24 are used for SSE state (see Section 13.5.2).
•Bytes 159:32 are used for the registers ST0–ST7 (MM0–MM7 ). Each of the 8 register is allocated a 128-bit 
x87 state is XSAVE-managed but the x87 FPU feature is no t XSAVE-enabled. The XSAVE feature set can operate on 
x87 state only if the feature se t is enabled (CR4.OSXSAVE = 1).1 Software can otherwise use x87 state even if the 
XSAVE feature set is not enabled.
1. The processor ensures that XCR0[0] is always 1.Vol. 1 13-11MANAGING STATE USING THE XSAVE FEATURE SET
13.5.2 SSE State
Instructions in the XSAVE feature set can manage the registers used by the streaming SIMD extensions ( SSE 
state ) just as the FXSAVE and FXRSTOR instructions do. They  organize all SSE state as a user state component in 
the legacy region of the XSAVE area (s ee Section 13.4.1). This region is illustrated in Table 13-1; the SSE state is 
listed below, along with details of its interactions with the XSAVE feature set:
•Bytes 23:0 are used for x87 state (see Section 13.5.1).
•Bytes 27:24 are used for the MXCSR register. XRSTOR and XRSTORS generate general-protection faults (#GP) 
in response to attempts to set any of the reserved bits of the MXCSR register.1
•Bytes 31:28 are used for the MXCSR_MASK value. XRSTOR and XRSTORS ignore this field.
of XSAVE, XSAVEOPT, XSAVEC, and XSAVES outside 64-bit mode do not modify these bytes; executions of XRSTOR and XRSTORS outside 64-bit mode do not update XMM8–XMM15. See Section 13.13.
SSE state is XSAVE-managed but the SSE feature is not XSAVE-enabled. The XSAVE feature set can operate on SSE 
state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage SSE state 
(XCR0[1] = 1). Software can otherwise use SSE state even if the XSAVE feature set is not enabled or has not been configured to manage SSE state.
13.5.3 AVX State
The register state used by the Intel® Advanced Vector Extensions (Intel AVX) comprises the MXCSR register and 
16 256-bit vector registers called YMM0–YMM15. The low 128 bits of each register YMM i is identical to the SSE 
register XMM i. Thus, the new state register state added by Inte l AVX comprises the upper 128 bits of the registers 
YMM0–YMM15. These 16 128-bit values are denote d YMM0_H–YMM15_H and are collectively called AVX state .
As noted in Section 13.1, the XSAVE feature set manages AVX state as user state component 2. Thus, AVX state is 
located in the extended region of the XSAVE area (see Section 13.4.3).
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=2):EBX enum erates the offset (in bytes, from the base of the 
XSAVE area) of the section of the extended region of the XSAVE area used for AVX state (when the standard format 
of the extended region is used). CPUID.(EAX=0DH,ECX=2 ):EAX enumerates the size (in bytes) required for AVX 
state.
The XSAVE feature set partitions YMM0_H–YMM15_H in a ma nner similar to that used for the XMM registers (see 
Section 13.5.2). Bytes 127:0 of the AVX-state section are used for YMM0_H–YMM7_H. Bytes 255:128 are used for YMM8_H–YMM15_H, but they are used only in 64-bit mo de. Executions of XSAVE, XSAVEOPT, XSAVEC, and

state.
Section 13.5.2). Bytes 127:0 of the AVX-state section are used for YMM0_H–YMM7_H. Bytes 255:128 are used for YMM8_H–YMM15_H, but they are used only in 64-bit mo de. Executions of XSAVE, XSAVEOPT, XSAVEC, and 
XSAVES outside 64-bit mode do not modify bytes 255:1 28; executions of XRSTOR and XRSTORS outside 64-bit 
mode do not update YMM8_H–YMM15_H. See Section 13.13. In general, bytes 16 i+15:16 i are used for YMM i_H 
(for 0 ≤ i≤ 15).
AVX state is XSAVE-managed and the Intel AVX feature is  XSAVE-enabled. The XSAVE feature set can operate on 
AVX state only if the feature set is enabled (CR4.OSXSA VE = 1) and has been configured to manage AVX state 
(XCR0[2] = 1). Intel AVX instructions cannot be used unle ss the XSAVE feature set is enabled and has been config-
ured to manage AVX state.
13.5.4 MPX State
The register state used by the Intel® Memory Protection Extensions (MPX) comprises the 4 128-bit bounds regis-
ters BND0–BND3 ( BNDREGS state ); and the 64-bit user-mode configuration register BNDCFGU and the 64-bit 
MPX status register BNDSTATUS (collectively, BNDCSR state ). Together, these two user state components 
compose MPX state .
1. While MXCSR and MXCSR_MASK are part of SSE state, their treatmen t by the XSAVE feature set is no t the same as that of the XMM  
registers. See Section 13.7 through Section 13.11 for details.13-12 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
As noted in Section 13.1, the XSAVE feature set manages MPX state as state components 3–4. Thus, MPX state is 
located in the extended region of the XSAVE area (see Section 13.4.3). The following items detail how these state 
components are organized in this region:
•BNDREGS state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=3):EBX enum erates the offset (in bytes, from the base of the 
XSAVE area) of the section of the extended region of the XSAVE area used for BNDREGS state (when the 
standard format of the extended region is used).  CPUID.(EAX=0DH,E CX=3):EAX enumerates the size (in 
bytes) required for BNDREGS state. The BNDREGS section is used for the 4 128-bit bound registers BND0–
BND3, with bytes 16 i+15:16 i being used for BND i.
•BNDCSR state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=4):EBX e numerates the offset of the section of the extended 
region of the XSAVE area used for BNDCSR state (when th e standard format of the extended region is used). 
CPUID.(EAX=0DH,ECX=4):EAX enumerates the size (in by tes) required for BNDCSR state. In the BNDSCR 
section, bytes 7:0 are used for BNDCFGU and bytes 15:8 are used for BNDSTATUS.
Both components of MPX state are XSAVE-managed and the Intel MPX feature is XSAVE-enabled. The XSAVE 
feature set can operate on MPX state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured 
to manage MPX state (XCR0[4:3] = 11b). Intel MPX instructions cannot be used unless the XSAVE feature set is 
enabled and has been configured to manage MPX state.
13.5.5 AVX-512 State
The register state used by the Intel® Advanced Vector Extensions 512 (Intel AVX-512) comprises the MXCSR 
register, the 8 64-bit opmask registers k0–k7, and 32 512-bit vector registers called ZMM0–ZMM31. For each i, 0≤ 
i≤ 15, the low 256 bits of register ZMM i is identical to the Intel AVX register YMM i. Thus, the new state register 
state added by Intel AVX-512 comprises the following user state components:
•The opmask registers, collectively called opmask state .
•The upper 256 bits of the registers ZMM0–ZMM15. Th ese 16 256-bit values are denoted ZMM0_H–ZMM15_H 
and are collectively called ZMM_Hi256 state .
•The 16 512-bit registers ZMM16–ZMM31, collectively called Hi16_ZMM state .
Together, these three state components compose AVX-512 state .
As noted in Section 13.1, the XSAVE feature set manages AVX-512 state as state components 5–7. Thus, AVX-512 
state is located in the extended region of the XSAVE area  (see Section 13.4.3). The following items detail how these 
state components are organized in this region:
•Opmask state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=5):EBX enum erates the offset (in bytes, from the base of the 
XSAVE area) of the section of the extended region of th e XSAVE area used for opmask state (when the standard 
format of the extended region is used). CPUID.(EAX=0 DH,ECX=5):EAX enumerates the size (in bytes) required 
for opmask state. The opmask section is used fo r the 8 64-bit opmask registers k0–k7, with bytes 8 i+7:8i 
being used for k i.
•ZMM_Hi256 state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=6):EBX e numerates the offset of the section of the extended 
region of the XSAVE area used for ZMM_Hi256 state (w hen the standard format of the extended region is 
used). CPUID.(EAX=0 DH,ECX=6):EAX enumerates the size (in bytes) required for ZMM_Hi256 state.
The XSAVE feature set partitions ZMM0_H–ZMM15_H in a manner similar to that used for the XMM registers 
(see Section 13.5.2). Bytes 255:0 of the ZMM_ Hi256-state section are used for ZMM0_H–ZMM7_H. 
Bytes 511:256 are used for ZMM8_H–ZMM15_H, but they are used only in 64-bit mode. Executions of XSAVE, 
XSAVEOPT, XSAVEC, and XSAVES outside 64-bit mode do not modify bytes 511:256; executions of XRSTOR 
and XRSTORS outside 64-bit mode do not update ZMM8_H–ZMM15_H. See Section 13.13. In general, 
bytes 32 i+31:32 i are used for ZMM i_H (for 0 ≤ i≤ 15).
•Hi16_ZMM state.
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=7):EBX e numerates the offset of the section of the extended 
region of the XSAVE area used for Hi16_ZMM state (when th e standard format of the ex tended region is used). 
CPUID.(EAX=0DH,ECX=7):EAX enumerates the size  (in bytes) required for Hi16_ZMM state.Vol. 1 13-13MANAGING STATE USING THE XSAVE FEATURE SET
The XSAVE feature set accesses Hi16_ZMM state only in 64-bit mode. Executions of XSAVE, XSAVEOPT, 
XSAVEC, and XSAVES outside 64-bit mode do not modi fy the Hi16_ZMM section; executions of XRSTOR and 
XRSTORS outside 64-bit mode do not update ZMM16–ZMM31. See Section 13.13. In general, 
bytes 64( i-16)+63:64( i-16) are used for ZMM i (for 16 ≤ i≤ 31).
All three components of AVX-512 state are XSAVE-managed and the Intel AVX-512 feature is XSAVE-enabled. The 
XSAVE feature set can operate on AVX-512 state only if  the feature set is enabled (CR4.OSXSAVE = 1) and has 
been configured to manage AVX-512 state (XCR0[7:5] = 1 11b). Intel AVX-512 instructions cannot be used unless 
the XSAVE feature set is enabled and has been configured to manage AVX-512 state.
13.5.6 PT State
The register state used by Intel Processor Trace ( PT state ) comprises the following 9 MSRs: IA32_RTIT_CTL, 
IA32_RTIT_OUTPUT_BASE, IA32_RTIT_OUTPUT_MASK_PTRS, IA32_RTIT_STATUS, IA32_RTIT_CR3_MATCH, 
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B, IA32_RTIT_ADDR1_A, and IA32_RTIT_ADDR1_B.1
As noted in Section 13.1, the XSAVE feature set manages PT state as supervisor state component 8. Thus, PT state is located in the extended region of the XSAVE ar ea (see Section 13.4.3). As noted in Section 13.2, 
CPUID.(EAX=0DH,ECX=8):EAX enumerates th e size (in bytes) required for PT state. The MSRs are each allocated 
8 bytes in the state component in the order given above. Thus, IA32_RTIT_CTL is at byte offset 0, IA32_RTIT_OUTPUT_BASE at byte offset 8,  etc. Any locations in the state component at or beyond byte offset 72 
are reserved.
PT state is XSAVE-managed but Intel Processor Trace is not XSAVE-enabled. The XSAVE feature set can operate on 
PT state only if the feature set is enabled (CR4.OSXSA VE = 1) and has been configured to manage PT state 
(IA32_XSS[8] = 1). Software can otherwise use Intel Processor Trace and access its MSRs (using RDMSR and WRMSR) even if the XSAVE feature set is not enable d or has not been configured to manage PT state.
The following items describe special treatment of PT state by the XSAVES and XRSTORS instructions:
•If XSAVES saves PT state, the instruction clears IA32_R TIT_CTL.TraceEn (bit 0) after saving the value of the 
IA32_RTIT_CTL MSR and before saving any other PT state. If XSAVES causes a fault or a VM exit, it restores 
IA32_RTIT_CTL.TraceEn to its original value.
•If XSAVES saves PT state, the instruction saves zero es in the reserved portions of the state component.
•If XRSTORS would restore (or initialize) PT state and IA32_RTIT_CTL.TraceEn = 1, the instruction causes a 
general-protection exception (#GP) before modifying PT state.
•If XRSTORS causes an exception or a VM exit, it does so before any modification to IA32_RTIT_CTL.TraceEn (even if it has loaded other PT state).
13.5.7 PKRU State
The register state used by the protection-key feature ( PKRU state ) is the 32-bit PKRU register. As noted in Section 
13.1, the XSAVE feature set manages PKRU state as user state component 9. Thus, PKRU state is located in the 
extended region of the XSAVE area (see Section 13.4.3).
As noted in Section 13.2, CPUID.(EAX=0DH,ECX=9):EBX enum erates the offset (in bytes, from the base of the 
XSAVE area) of the section of the extended region of the XSAVE area used for PKRU state (when the standard 
format of the extended region is used). CPUID.(EAX=0DH,ECX=9):EAX enumerates the size (in bytes) required for

format of the extended region is used). CPUID.(EAX=0DH,ECX=9):EAX enumerates the size (in bytes) required for 
PKRU state. The XSAVE feature set uses bytes 3:0 of the PK-state section for the PKRU register.
PKRU state is XSAVE-managed but the protection-key fe ature is not XSAVE-enabled. The XSAVE feature set can 
operate on PKRU state only if the feature set is enable d (CR4.OSXSAVE = 1) and has been configured to manage 
PKRU state (XCR0[9] = 1). Software can otherwise use prot ection keys and access PKRU state even if the XSAVE 
feature set is not enabled or has not been configured to manage PKRU state.
1. These MSRs might not be supported by every processor that supports Intel Processor Trace. Software can use the CPUID instruct ion 
to discover which are supported; see Section 33.3.1, “Detection of Intel Processor Trace and Capability Enumeration,” of Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 3C.13-14 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
The value of the PKRU register determines the access ri ghts for user-mode linear addresses. (See Section 4.6, 
“Access Rights,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.) The access rights 
that pertain to an execution of the XRSTOR and XRSTORS in structions are determined by the value of the register 
before the execution and not by any value that th e execution might load into the PKRU register.
13.5.8 PASID State
The register state used by the ENQCMD instru ction and process address space identifiers ( PASID state ) comprises 
the IA32_PASID MSR.
As noted in Section 13.1, the XSAVE feature set manages PASID state as supervisor state component 10. Thus, 
PASID state is located in the extended region of the XS AVE area (see Section 13.4.3). As noted in Section 13.2, 
CPUID.(EAX=0DH,ECX=10):E AX enumerates the size (in bytes) required for PASID state. The IA32_PASID MSR is 
allocated 8 bytes at byte offset 0 in the state component.
PASID state is XSAVE-managed but the ENQCMD instruction and process address space identifiers are not XSAVE-
enabled. The XSAVE feature set can operate on PASID stat e only if the feature set is enabled (CR4.OSXSAVE = 1) 
and has been configured to manage PASID state (IA32_ XSS[10] = 1). Software can otherwise use the ENQCMD 
instruction and process address space identifiers, an d access the IA32_PASID MSR (using RDMSR and WRMSR) 
even if the XSAVE feature set is not enabled or has not been configured to manage PASID state.
13.5.9 CET State
The register state used by Control-Flow Enforcem ent Technology (CET) comprises the two 64-bit MSRs 
(IA32_U_CET and IA32_PL3_SSP) th at manage CET when CPL = 3 ( CET_U state ); and the three 64-bit MSRs 
(IA32_PL0_SSP–IA32_PL2_SSP) that manage CET when CPL < 3 ( CET_S state ). Together, these two supervisor 
state components compose CET state .1
As noted in Section 13.1, the XSAVE feature set manage s CET state as supervisor state components 11–12. Thus, 
CET state is located in the extended region of the XSAVE area (see Section 13.4.3). The following items detail how 
these state components are organized in this region:
•CET_U state.
As noted in Section 13.2, CPUID.(EAX =0DH,ECX=11):EAX enumerates the si ze (in bytes) required for CET_U 
state. The CET_U section is used for the 64-bit MSRs  IA32_U_CET and IA32_PL3_SSP, with bytes 7:0 being 
used for IA32_U_CET and bytes 15:8 being used for IA32_PL3_SSP.
•CET_S state.
As noted in Section 13.2, CPUID.(EAX =0DH,ECX=12):EAX enumerates the si ze (in bytes) required for CET_S 
state. The CET_S section is used for the three 64 -bit MSRs IA32_PL0_SSP–IA32_PL2_SSP, with bytes 8 i+7:8i 
being used for IA32_PL i_SSP.
The two components of CET state are XSAVE-managed and CET is not XSAVE-enabled. The XSAVE feature set can 
operate on CET_U state (respectively, CET_S state) only if the feature set is enabled (CR4.OSXSAVE = 1) and has 
been configured to manage CET_U state (respectively, CET_S state) by setting IA32_XSS[11] (respectively, 
IA32_XSS[12]). Software can otherwise use CET and acce ss the CET MSRs (using RDMSR and WRMSR) even if the 
XSAVE feature set is not enabled or has not been configured to manage CET state.
13.5.10 HDC State
The register state used by  hardware duty cycling ( HDC state ) comprises the IA32_PM_CTL1 MSR.
As noted in Section 13.1, the XSAVE feature set manages HDC state as supervisor state component 13. Thus, HDC 
state is located in the extended region of the XSAVE area (see Section 13.4.3). As noted in Section 13.2, 
CPUID.(EAX=0DH,ECX=13 ):EAX enumerates the size (in bytes) requ ired for HDC state. The IA32_PM_CTL1 MSR 
is allocated 8 bytes at byte offset 0 in the state component.
1. The IA32_S_CET and IA32_INTERRUPT_SSP_TABLE _ADDR MSRs also control CET when CPL < 3. However, they are not managed by 
the XSAVE feature set an d are thus not considered in this chapter.Vol. 1 13-15MANAGING STATE USING THE XSAVE FEATURE SET
HDC state is XSAVE-managed but hardware duty cycling is not XSAVE-enabled. The XSAVE feature set can operate 
on HDC state only if the feature set is enabled (CR4.OSX SAVE = 1) and has been configured to manage HDC state 
(IA32_XSS[13] = 1). Software can otherwise use hardware duty cycling and access the IA32_PM_CTL1 MSR (using 
RDMSR and WRMSR) even if the XSAVE feature set is not en abled or has not been configured to manage HDC state.
13.5.11 UINTR State
The register state used by user interrupts ( UINTR state ) comprises 48 bytes in memory with the following layout:
•Bytes 7:0 are for the IA32_UINTR_HANDLER MSR.
•Bytes 15:8 are for the IA32_UINTR_STACKADJUST MSR.
•Bytes 23:16 are for the IA32_UINTR_MISC MSR with exception of the last bit (bit 7 of byte 23), which is used 
for UIF. (Because UIF is not part of the IA32_UINTR_M ISC MSR, software that reads a value from bytes 23:16 
should clear bit 63 of that 64-bit value before a ttempting to write it to the IA32_UINTR_MISC MSR.).
•Bytes 31:24 are for the IA32_UINTR_PD MSR.
•Bytes 39:32 are for the IA32_UINTR_RR MSR.
•Bytes 47:40 are for the IA32_UINTR_TT MSR.
As noted in Section 13.1, the XSAVE feature set manages UINTR state as supervisor state component 14. Thus, 
UINTR state is located in the extended region of the XSAVE area (see Sectio n 13.4.3). As noted in Section 13.2, 
CPUID.(EAX=0DH,ECX=14):EAX enumerates the size (in bytes) required for UINTR state.
UINTR state is XSAVE-managed but user interrupts are not XSAVE-enabled. The XSAVE feature set can operate on 
UINTR state only if the feature set is enabled (CR4.OSXSA VE = 1) and has been configured to manage UINTR state 
(IA32_XSS[14] = 1). Software can otherwise use user in terrupts and access the MSRs (using RDMSR and WRMSR) 
even if the XSAVE feature set is not enabled or has not been configured to manage UINTR state.
The management of the UINTR state component by XSAVES follows the architecture of the XSAVE feature set. The 
following items identify points that are specific to saving the UINTR state component:
•XSAVES writes the user-interrupt registers to the user -interrupt state component using the format specified 
above.
•XSAVES stores zeros to bits and bytes identified above as reserved.
•The values saved for the IA32_UINTR_HANDLER , IA32_UINTR_STACKADJUST, IA32_UINTR_PD, and 
IA32_UINTR_TT MSRs are always canonical relative to the maximum linear-address width enumerated by CPUID
1.
•After saving the user-interrupt state component, XSAVES clears UINV. (UINV is IA32_UINTR_MISC[39:32]; 
XSAVES does not modify the remainder of that MSR.)
The management of the user-interrupt state component by  XRSTORS follows the architecture of the XSAVE feature 
set. The following items identify points that are spec ific to restoring the user-interrupt state component:
•Before restoring the user-interrupt state component, XRST ORS verifies that UINV is 0. If it is not, XRSTORS 
causes a general-protection fault (#GP) before loading any part of the user-interrupt state component. (UINV 
is IA32_UINTR_MISC[39:32]; XRSTORS does not check the contents of the remainder of that MSR.)
•If the instruction mask and XSAVE area used by XRSTORS indicates that the user-interrupt state component 
should be loaded from the XSAVE area, XRSTORS reads the user-interrupt registers from the XSAVE area using the format identified above. The values read cause a general-protection fault (#GP ) in any of the following 
cases:
— If the value to be loaded into any one of the IA32_UINTR_HANDLER, IA32_UINTR_STACKADJUST, 
IA32_UINTR_PD, or IA32_UINTR_TT MSRs is not canonical relative to the maximum linear-address width 
enumerated by CPUID.
— If the value to be loaded into the IA32_UINTR_MISC MSR sets any of bits 62:40. These bits are reserved in 
the MSR. (Bit 63 is also reserved in the MSR, but the XSAVE feature set uses bit 63 of this value for UIF.)
1. They might not be canonical relative to the current pagi ng mode if it supports on ly smaller linear addresses.13-16 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
— If the value to be loaded into the IA32_UINTR_ PD MSR sets any of bits 5:0. These bits are reserved in the 
MSR.

cases:
MSR.
— If the value to be loaded into the IA32_UINTR_ TT MSR sets any of bits 3:1. These bits are reserved in the 
MSR.
•If XRSTORS causes a fault or a VM exit after loading an y part of the user-interrupt state component, XRSTORS 
clears UINV before delivering the fault or VM exit. (Other  elements of user-interrupt state, including other parts 
of the IA32_UINTR_MISC MSR, may retain th e values that were loaded by XRSTORS.)
•After an execution of XRSTORS that loads the user-interrupt state component, the logical processor recognizes 
a pending user interrupt if and only if some bit is set in the IA32_UINTR_RR MSR (see Section 7.4.1 in the 
Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 3A).
13.5.12 LBR State
The register state used by last-branch records ( LBR state ) comprises 101 MSRs organized as follows: 
IA32_LBR_CTL; IA32_LBR_DEPTH; IA32_LER_FROM_IP; IA32_LER_TO_IP; IA32_LER_INFO; and 32 triples of 
MSRs, IA32_LBR_ i_FROM_IP, IA32_LBR_ i_TO_IP, IA32_LBR_ i_INFO, for each value of i, 0≤ i≤ 31.
As noted in Section 13.1, the XSAVE feature set manages LBR state as supervisor state component 15. Thus, LBR 
state is located in the extended region of the XSAV E area (see Section 13.4.3). As noted in Section 13.2, 
CPUID.(EAX=0DH,ECX=15):EAX enumerates the size (in by tes) required for LBR state. The IA32_LBR_CTL MSR is 
allocated 8 bytes at byte offset 0 in the state componen t. The remaining MSRs are ea ch allocated 8 bytes in the 
state component in the order given above. Thus, IA32_LBR_D EPTH is at byte offset 8, … , IA32_LBR_0_FROM_IP 
at byte offset 40, IA32_LBR_0_TO_IP at byte offset 48, IA32_LBR_0_INFO at byte offset 56, 
IA32_LBR_1_FROM_IP at byte offset 64, …, and IA32_LBR_ 31_INFO at byte offset 800. Any locations in the state 
component at or beyond byte offset 808 are reserved.
LBR state is XSAVE-managed but LBRs are not XSAVE-enabled. The XSAVE feature set can operate on LBR state 
only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage LBR state 
(IA32_XSS[15] = 1). Software can otherwise use LBRs an d access the MSRs (using RD MSR and WRMSR) even if 
the XSAVE feature set is not enabled or has not been configured to manage LBR state.
The following items describe special treatment of LB R state by the XSAVES and XRSTORS instructions:
•If XSAVES would save LBR state and that state is no t in its initial configuration (see Section 13.6), the 
instruction always saves IA32_LBR_CTL, IA32_LBR_DEPTH, IA32_LER_FROM_IP, IA32_LER_TO_IP, and IA32_LER_INFO. It saves the triples IA32_LBR_ i_FROM_IP, IA32_LBR_ i_TO_IP, IA32_LBR_ i_INFO, for each 
value of i, 0≤ i< D, where D is the value of IA32_LBR_DEPTH. It will not save the values of the remaining 
triples, although it may access the co rresponding fields in the XSAVE area.
•If XSAVES would save LBR state and that state is in its initial configuration, the instruction does not save any 
LBR state and will not access that component of the XSAVE area.
•If XRSTORS would initialize LBR state, IA32_LBR_DEPTH is  not modified and zero is written to the other MSRs 
that compose LBR state.
•If XRSTORS would restore LBR state, behavior depends on the current value of IA32_LBR_DEPTH and the value 
of corresponding field in the XSAVE area:
— If the current value of IA32_LBR_DEPTH equals the value of corresponding field in the XSAVE area, the 
instruction restores IA32_LBR_CTL, IA32_LER_FROM_IP, IA32_LER_TO_IP, IA32_LER_INFO, and the triples IA32_LBR_ i_FROM_IP, IA32_LBR_ i_TO_IP, IA32_LBR_ i_INFO, for each value of i, 0≤ i< D, where 
D is the value of IA32_LBR_DEPTH. It will not restore th e values of the remaining triples, although it may 
access the corresponding fields in the XSAVE area.
— If the IA32_LBR_DEPTH field in the XSAVE area sets any reserved bits, the instruction causes a general-
protection exception (#GP).
— If neither of the previous item s apply, the instruction restores IA32_LBR_CTL, IA32_LER_FROM_IP, 
IA32_LER_TO_IP, and IA32_LER_INFO, but it writes zero to the triples IA32_LBR_ i_FROM_IP, 
IA32_LBR_ i_TO_IP, IA32_LBR_ i_INFO, for each value of i, 0≤ i≤ 31. Such an execution does not modify 
XINUSE[15] (see Section 13.6 and Section 13.12).Vol. 1 13-17MANAGING STATE USING THE XSAVE FEATURE SET
13.5.13 HWP State
The register state used by hardware P-states ( HWP state ) comprises the IA32_HWP_REQUEST MSR.
As noted in Section 13.1, the XSAVE feature set manages HWP state as supervisor state component 16. Thus, HWP 
CPUID.(EAX=0DH,ECX=16):EAX enumerates the size (in by tes) required for HWP state. The IA32_HWP_REQUEST 
MSR is allocated 8 bytes at byte offset 0 in the state component.
HWP state is XSAVE-managed but the hardware P-states fe ature is not XSAVE-enabled. The XSAVE feature set can 
operate on HWP state only if the feature set is enable d (CR4.OSXSAVE = 1) and has been configured to manage 
HWP state (IA32_XSS[16] = 1). Software can otherwise use hardware P-states and access the 
IA32_HWP_REQUEST MSR (using RDMSR and WRMSR) even if the XSAVE feature set is not enabled or has not 
been configured to manage HWP state.
13.5.14 AMX State
The register state used by the Intel® Advanced Matrix Extensions (Intel AMX) comprises two state components, 
TILECFG and TILEDATA. Together, these two state components compose AMX state .
As noted in Section 13.1, the XSAVE feature set manage s AMX state as state components 17–18. Thus, AMX state 
is located in the extended region of the XSAVE area (s ee Section 13.4.3). The following items detail how these 
•TILECFG state.As noted in Section 13.1, the XSAVE feature set manages TILECFG state as user state component 17. Thus, 
TILECFG state is located in the extended region of th e XSAVE area (see Section 13.4.3). As noted in Section 
13.2, CPUID.(EAX=0DH,ECX=17):EAX enumerates th e size (in bytes) required for TILECFG state.
•TILEDATA state.
As noted in Section 13.1, the XSAVE feature set manage s TILEDATA state as user state component 18. Thus, 
TILEDATA state is located in the extended region of th e XSAVE area (see Section 13.4.3). As noted in Section 
13.2, CPUID.(EAX=0DH,ECX=18):EAX enumerates the size (in bytes) required for TILEDATA state.
Both components of AMX state are XSAVE-managed, and the AMX feature is XSAVE-enabled. The XSAVE feature 
set can operate on AMX state only if the feature set is  enabled (CR4.OSXSAVE = 1) an d has been configured to 
manage AMX state (XCR0[18:17] = 11b). Intel AMX instruct ions cannot be used unless the XSAVE feature set is 
enabled and has been configured to manage AMX state.
The following items describe special treatment of  TILECFG and TILEDATA by the XSAVE feature set:
•Loading of TILECFG and TILEDA TA by XRSTOR and XRSTORS:
— While the LDTILECFG instruction generates a general-pr otection fault (#GP) if it would load the TILECFG 
register with an unsupported value executions of XRSTOR and XRSTORS do not do so. Instead, they 
initialize the register (resulting in TILES_CONFIGURED = 0).
While executions of LDTILECFG initialize TILEDATA, executions of XRSTOR and XRSTORS do not modify 
TILEDATA unless loading it from memory.
While the value of the TILECFG register can limit how Intel AMX instructions access TILEDATA, such 
limitations do not apply to XRSTOR and XRSTORS. An ex ecution of either of those instructions loads all 8 
KBytes of TILEDATA regardless of the value in the TILECFG register (or the value that the instruction may be loading into that register).
•Saving of TILEDATA by XSAVE, XSAVEC, XSAVEOPT, and XSAVES:
— While the value of the TILECFG register can limit  how Intel AMX instructions access TILEDATA, such 
limitations do not apply to XSAVE, XSAVEC, XSAVEOPT , and XSAVES. An execution of any of those instruc-
tions saves all 8 KBytes of TILEDATA regardless of the value in the TILECFG register.13-18 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
13.6 PROCESSOR TRACKING OF XSAVE-MANAGED STATE
The XSAVEOPT, XSAVEC, and XSAVES instructions use two op timizations to reduce the amount of data that they 
write to memory. They avoid writing data for any state component known to be in its initial configuration (the init 
optimization ). In addition, if either XSAVEOPT or XSAVES is using the same XSAVE area as that used by the most 
recent execution of XRSTOR or XRSTORS, it may avoid writing data for any state component whose configuration 
is known not to have been modified since then (the modified optimization ). (XSAVE does not use these optimi-
zations, and XSAVEC does not use the modified optimiza tion.) The operation of XSAVEOPT, XSAVEC, and XSAVES 
are described in more detail in Section 13.9 through Section 13.11.
A processor can support the init and modified optimizations with special hardware that tracks the state components

A processor can support the init and modified optimizations with special hardware that tracks the state components 
that might benefit from those optimizations. Other im plementations might not include such hardware; such a 
processor would always consider each such state component as not in its initial configuration and as modified since 
the last execution of XRSTOR or XRSTORS.
The following notation describes the state of the init and modified optimizations:
•XINUSE denotes the state-component bitmap corresp onding to the init optimization. If XINUSE[ i] = 0, state 
component i is known to be in its initial configuration; otherwise XINUSE[ i] = 1. It is possible for XINUSE[ i] to 
be 1 even when state component i is in its initial configuration. On a processor that does not support the init 
optimization, XINUSE[ i] is always 1 for every value of i.
Executing XGETBV with ECX = 1 returns in EDX:EAX th e logical-AND of XCR0 and the current value of the 
XINUSE state-component bitmap. Such an execution of XGETBV always sets EAX[1] to 1 if XCR0[1] = 1 and 
MXCSR does not have its RESET value of 1F80H. Sectio n 13.2 explains how software can determine whether a 
processor supports this use of XGETBV.
•XMODIFIED denotes the state-comp onent bitmap corresponding to the modified optimization. If 
XMODIFIED[ i] = 0, state component i is known not to have been modified since the most recent execution of 
XRSTOR or XRSTORS; otherwise XMODIFIED[ i] = 1. It is possible for XMODIFIED[ i] to be 1 even when state 
component i has not been modified since the most recent execution of XRSTOR or XRSTORS. On a processor 
that does not support the modified optimization, XMODIFIED[ i] is always 1 for every value of i.
A processor that implements the modified optimization saves information about the most recent execution of 
XRSTOR or XRSTORS in a quantity called XRSTOR_INFO , a 4-tuple containing the following: (1) the CPL; 
(2) whether the logical processor was in VMX non-root operation; (3) the linear address of the XSAVE area; and 
(4) the XCOMP_BV field in the XSAVE area. An execution of  XSAVEOPT or XSAVES uses the modified optimization 
only if that execution corresponds to XRSTOR_INFO on these four parameters.
This mechanism implies that, depending on details of the operating system, the processor might determine that an 
execution of XSAVEOPT by one user application corresponds to an earlier execution of XRSTOR by a different appli-
cation. For this reason, Intel recommends the applic ation software not use the XSAVEOPT instruction.
The following items specify the initial configuration each st ate component (for the purposes of defining the XINUSE 
bitmap):
•x87 state.  x87 state is in its initial configuration if the fo llowing all hold: FCW is 037FH; FSW is 0000H; FTW is 
FFFFH; FCS and FDS are each 0000H; FIP and FDP are each 00000000_00000000H; each of ST0–ST7 is 
0000_00000000_00000000H.
•SSE state.  In 64-bit mode, SSE state is in its initial config uration if each of XMM0–X MM15 is 0. Outside 64-bit 
mode, SSE state is in its initial configuration if each of  XMM0–XMM7 is 0. XINUSE[1] pertains only to the state 
of the XMM registers and not to MXCSR. An execution of XRSTOR or XRSTORS outside 64-bit mode does not 
update XMM8–XMM15. (See Section 13.13.)
•AVX state.  In 64-bit mode, AVX state is in its initial conf iguration if each of YMM0_H–YMM15_H is 0. Outside 
64-bit mode, AVX state is in its initial configuration if  each of YMM0_H–YMM7_H is 0. An execution of XRSTOR 
or XRSTORS outside 64-bit mode does not update YMM8_H–YMM15_H. (See Section 13.13.)
•BNDREGS state.  BNDREGS state is in its initial configuratio n if the value of each of BND0–BND3 is 0.
•BNDCSR state.  BNDCSR state is in its initial configuration if BNDCFGU and BNDCSR each has value 0.
•Opmask state.  Opmask state is in its initial configuration if each of the opmask registers k0–k7 is 0.
•ZMM_Hi256 state.  In 64-bit mode, ZMM_Hi256 state is in it s initial configuration if each of ZMM0_H–
ZMM15_H is 0. Outside 64-bit mode, ZMM_Hi256 state is in its initial configuration if each of ZMM0_H–ZMM7_H Vol. 1 13-19MANAGING STATE USING THE XSAVE FEATURE SET
is 0. An execution of XRSTOR or XRSTORS outsid e 64-bit mode does not update ZMM8_H–ZMM15_H. (See 
Section 13.13.)
•Hi16_ZMM state.  In 64-bit mode, Hi16_ZMM state is in its initia l configuration if each of ZMM16–ZMM31 is 0. 
Outside 64-bit mode, Hi16_ZMM state is always in its initial configuration. An execution of XRSTOR or XRSTORS 
outside 64-bit mode does not update ZMM31–ZMM31. (See Section 13.13.)
•PT state.  PT state is in its initial configuration if each of the 9 MSRs is 0.
•PKRU state.  PKRU state is in its initial configuration if the value of the PKRU is 0.
•PASID state.  PASID state is in its initial configuration if the value of the IA32_PASID MSR is 0.
•CET_U state.  CET_U state is in its initial config uration if both of the MSRs are 0.
•CET_S state.  CET_S state is in its initial configuration if each of the three MSRs is 0.
•HDC state.  HDC state is in its initial configuration if the value of the IA32_PM_CTL1 MSR is 1.
•UINTR state.  UINTR state is in its initial configuration if all user-interrupt registers (including UIF) are zero.
•LBR state.  LBR state is in its initial configuration if the valu e of each of the MSRs is 0, with the exception of 
IA32_LBR_DEPTH. XINUSE[15] does not pertain to IA32_LBR_DEPTH.
•HWP state.  HWP state is in its initial configuration if th e value of the IA32_HWP_REQUEST MSR is 8000FF01H.
•AMX state.  AMX state is in its initial configuration if the TILECFG register is zero and all tile data are zero.
13.7 OPERATION OF XSAVE
The XSAVE instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair 
EDX:EAX is an implicit operand used as a state- component bitmap (see Section 13.1) called the instruction 
mask . The logical-AND of XCR0 and the instruction mask is the requested-feature bitmap  (RFBM ) of the user 
state components to be saved.
The following conditions cause execution of the XSAVE instruction to generate a fault:
•If the XSAVE feature set is not enabled (CR4.OSXSA VE = 0), an invalid-opcode exception (#UD) occurs.
•If CR0.TS[bit 3] is 1, a device-not-available exception (#NM) occurs.
•If the address of the XSAVE area is not 64-byte al igned, a general-protection exception (#GP) occurs.1
If none of these conditions cause a fault, execution of  XSAVE reads the XSTATE_BV field of the XSAVE header (see 
Section 13.4.2) and writes it back to memory, setting XSTATE_BV[ i] (0 ≤ i ≤ 63) as follows:
•If RFBM[ i]=  0 ,  X S T A T E _ B V [ i] is not changed.
•If RFBM[ i]=  1 ,  X S T A T E _ B V [ i] is set to the value of XINUSE[ i]. Section 13.6 defines XINUSE to describe the 
processor init optimization and specifies the initial conf iguration of each state component. The nature of that 
optimization implies the following:
— If state component i is in its initial configuration, XINUSE[ i] may be either 0 or 1, and XSTATE_BV[ i] may 
be written with either 0 or 1.
XINUSE[1] pertains only to the state of the XMM regi sters and not to MXCSR. Thus, XSTATE_BV[1] may be 
written with 0 even if MXCSR does not have its RESET value of 1F80H.
— If state component i is not in its initial configuration, XINUSE[ i]=  1  a n d  X S T A T E _ B V [ i] is written with 1.
(As explained in Section 13.6, the initial configurations  of some state components may depend on whether the 
processor is in 64-bit mode.)
The XSAVE instruction does not write any part of the XSAVE header other than the XSTATE_BV field; in particular, 
it does not write to the XCOMP_BV field.
Execution of XSAVE saves into the XSAVE area those state components corresponding to bits that are set in RFBM. 
State components 0 and 1 are located in the legacy regi on of the XSAVE area (see Section 13.4.1). Each state 
component i, 2≤ i ≤ 62, is located in the extended region; the XSAVE instruction always uses the standard format 
for the extended region (see Section 13.4.3).
1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.13-20 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
The MXCSR register and MXCSR_MASK ar e part of SSE state (see Section 13.5.2) and are thus associated with 
RFBM[1]. However, the XSAVE instruction also saves th ese values when RFBM[2] = 1 (even if RFBM[1] = 0).
See Section 13.5 for specifics for each state component and for details regarding mode-specific operation and 
operation determined by instruction prefixes. See Sectio n 13.13 for details regarding faults caused by memory 
accesses.
13.8 OPERATION OF XRSTOR
The XRSTOR instruction takes a single memory operand, wh ich is an XSAVE area. In addition, the register pair 
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction 
state components to be restored.
The following conditions cause execution of the XRSTOR instruction to generate a fault:

accesses.
After checking for these faults, the XRSTOR instruction reads the XCOMP_BV field in the XSAVE area’s XSAVE 
header (see Section 13.4.2). If XCOMP_BV[63] = 0, the standard form of XRSTOR  is executed (see Section 
13.8.1); otherwise, the compacted form of XRSTOR  is executed (see Section 13.8.2).2
See Section 13.2 for details of ho w to determine whether the compacte d form of XRSTOR is supported.
13.8.1 Standard Form of XRSTOR
The standard from of XRSTOR performs  additional fault checking. Either of the following conditions causes a 
general-protection exception (#GP):
•The XSTATE_BV field of the XSAVE header sets a bit that is not set in XCR0.
•Bytes 23:8 of the XSAVE header are not all 0 (thi s implies that all bits  in XCOMP_BV are 0).3
If none of these conditions cause a fault, the processor updates each state component i for which RFBM[ i]=  1 .  
XRSTOR updates state component i based on the value of bit i in the XSTATE_BV field of the XSAVE header:
•If XSTATE_BV[ i] = 0, the state component is set to its initial configuration. Section 13.6 specifies the initial 
configuration of each state component.
The initial configuration of state component 1 pertains on ly to the XMM registers and not to MXCSR. See below 
for the treatment of MXCSR
•If XSTATE_BV[ i] = 1, the state component is loaded with data from the XSAVE area. See Section 13.5 for 
specifics for each state component and for details rega rding mode-specific operatio n and operation determined 
by instruction prefixes. See Section 13.13 for details regarding faults caused by memory accesses.
component i, 2≤ i ≤ 62, is located in the extended region; the standard form of XRSTOR uses the standard 
format for the extended region (see Section 13.4.3).
The MXCSR register is part of state component 1, SSE stat e (see Section 13.5.2). However, the standard form of 
XRSTOR loads the MXCSR register from memory whenever the RFBM[1] (SSE) or RFBM[2] (AVX) is set, regardless 
1. If CR0.AM = 1, CPL = 3, and EFLA GS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.
2. If the processor does not support the compacted form of XRSTOR , it may execute the standard form of XRSTOR without first read -
ing the XCOMP_BV field. A processor supports the compacted form of XRSTOR only if it enumerates CPUID.(EAX=0DH,ECX=1):EAX[1] as 1.
3. Bytes 63:24 of the XSAVE header are also reserved. Software should ensure that bytes 63:16 of the XSAVE header are all 0 in any  
XSAVE area. (Bytes 15:8 should also be 0 if the XSAVE area is to be used on a proce ssor that does not su pport the compaction 
extensions to the XSAVE feature set.)Vol. 1 13-21MANAGING STATE USING THE XSAVE FEATURE SET
of the values of XSTATE_BV[1] and XSTATE_BV[2]. The standard form of XRSTOR causes a general-protection 
exception (#GP) if it would lo ad MXCSR with an illegal value.
13.8.2 Compacted Form of XRSTOR
The compacted from of XRSTOR performs additional fault checking. Any of the following conditions causes a #GP:
•The XCOMP_BV field of the XSAVE header sets a bit in the range 62:0 that is not set in XCR0.
•The XSTATE_BV field of the XSAVE header sets a bit (including bit 63) that is not set in XCOMP_BV.
•Bytes 63:16 of the XSAVE header are not all 0.
If XSTATE_BV[1] = 0, the compacted form XRSTOR initia lizes MXCSR to 1F80H. (This differs from the standard 
from of XRSTOR, which loads MXCSR from the XSAVE area whenever either RFBM[1] or RFBM[2] is set.)
State component i is set to its initial configuration as indicated above if RFBM[ i] = 1 and XSTATE_BV[ i]=  0  —  
even if XCOMP_BV[ i]=  0 . This is true for all values of i, including 0 (x87 state) and 1 (SSE state).
•If XSTATE_BV[ i] = 1, the state component is loaded with data from the XSAVE area.1 See Section 13.5 for 
specifics for each state component and for details rega rding mode-specific operation and operation determined 
component i, 2≤ i ≤ 62, is located in the extended region; the co mpacted form of the XRSTOR instruction uses 
the compacted format for the extend ed region (see Section 13.4.3).
The MXCSR register is part of SSE state (see Section 13. 5.2) and is thus loaded from memory if RFBM[1] = 
XSTATE_BV[ i] = 1. The compacted form of XRSTOR does not consider RFBM[2] (AVX) when determining whether 
to update MXCSR. (This is a difference from the standard form of XRSTOR.) The compacted form of XRSTOR causes a general-protection exception (#GP) if it  would load MXCSR with an illegal value.
13.8.3 XRSTOR and the Init and Modified Optimizations
Execution of the XRSTOR instruction causes the processor to update its tracking for the init and modified optimiza-
tions (see Section 13.6). The following items provide details:
•The processor updates its tracking for the init optimization as follows:
—I f  R F B M [ i]=  0 ,  X I N U S E [ i] is not changed.
—I f  R F B M [ i] = 1 and XSTATE_BV[ i] = 0, state component i may be tracked as init; XINUSE[ i] may be set to 
0 or 1. (As noted in Section 13.6, a processor need no t implement the init optimization for state component 
i; a processor that does not do so implicitly maintains XINUSE[ i] = 1 at all times.)
—I f  R F B M [ i] = 1 and XSTATE_BV[ i] = 1, state component i is tracked as not init; XINUSE[ i] is set to 1.
•The processor updates its tracking for the modified optimization and records information about the XRSTOR 
execution for future interaction with the XSAVEOPT and XSAVES instructions (see Section 13.9 and Section 
13.11) as follows:
—I f  R F B M [ i] = 0, state component i is tracked as modified; XMODIFIED[ i] is set to 1.
—I f  R F B M [ i] = 1, state component i may be tracked as unmodified; XMODIFIED[ i] may be set to 0 or 1. (As 
noted in Section 13.6, a processor need not implement the modified optimization for state component i; a 
processor that does not do so implicitly maintains XMODIFIED[ i] = 1 at all times.)
1. Earlier fault checking ensured that , if the instruction has reached this point in execution and XSTATE_BV[ i] is 1, then XCOMP_BV[ i] is 
also 1.13-22 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
— XRSTOR_INFO is set to the 4-tuple w,x,y,z, where w is the CPL (0); x is 1 if the logical processor is in VMX 
non-root operation and 0 otherwise; y is the linear address of the XSAVE area; and z is XCOMP_BV. In 
particular, the standard form of XRSTOR always sets z to all zeroes, while the compacted form of XRSTORS 
never does so (because it sets at least bit 63 to 1).
Note that, if RFBM is entirely zero (e.g., because the instruction mask in EDX:EAX is zero), no state components are 
modified, the XINUSE bitmap is not mo dified, and all bits are set in the XMODIFIED bitmap. Thus, if EDX:EAX was 
zero for the most recent execution of XRSTOR, an executio n of XSAVEOPT or XSAVES will identify all state compo-
nents as modified and will thus not use the modified optimization.
13.9 OPERATION OF XSAVEOPT
The operation of XSAVEOPT is similar to that of XSAVE.  Unlike XSAVE, XSAVEOPT uses the init optimization (by 
which it may omit saving state components that are in thei r initial configuration) and the modified optimization (by 
which it may omit saving state components that have no t been modified since the last execution of XRSTOR); see 
Section 13.6. See Section 13.2 for details of how to determine whether XSAVEOPT is supported.
The XSAVEOPT instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair 
mask . The logical (bitwise) AND of XCR0  and the instruction mask is the requested-feature bitmap  (RFBM ) of 
the user state components to be saved.
The following conditions cause execution of the XSAVEOPT instruction to generate a fault:

If none of these conditions cause a fault, execution of  XSAVEOPT reads the XSTATE_BV field of the XSAVE header 
(see Section 13.4.2) and writes it back to memory, setting XSTATE_BV[ i] (0 ≤ i ≤ 63) as follows:
— If the state component is in its initial configuration, XINUSE[ i] may be either 0 or 1, and XSTATE_BV[ i] may 
XINUSE[1] pertains only to the state of the XMM regi sters and not to MXCSR. Th us, XSTATE_BV[1] may be 
— If the state component is not in it s initial configuration, XSTATE_BV[ i] is written with 1.
(As explained in Section 13.6, the init ial configurations of some state components may depend on whether the 
The XSAVEOPT instruction does not write any part of the XSAVE header other than the XSTATE_BV field; in partic-
ular, it does not write to the XCOMP_BV field.
Execution of XSAVEOPT saves into the XSAVE area those state components corresponding to bits that are set in 
RFBM (subject to the optimizations described below). State components 0 and 1 are located in the legacy region of 
the XSAVE area (see Section 13.4.1). Each state component i, 2≤ i ≤ 62, is located in the extended region; the 
XSAVEOPT instruction always uses the standard format for the extended region (see Section 13.4.3).
accesses.
Execution of XSAVEOPT performs two optimizations th at reduce the amount of data written to memory:
1. If CR0.AM = 1, CPL = 3, and EFLA GS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.Vol. 1 13-23MANAGING STATE USING THE XSAVE FEATURE SET
•Init optimization.
If XINUSE[ i] = 0, state component i is not saved to the XSAVE area (even if RFBM[ i]=  1 ) .  ( S e e  b e l o w  f o r  
exceptions made for MXCSR.)
•Modified optimization.
Each execution of XRSTOR and XRSTORS establishes XRSTOR_INFO as a 4-tuple w,x,y,z (see Section 13.8.3 
and Section 13.12). Execution of XSAVEOPT uses the modifi ed optimization only if the following all hold for the 
current value of XRSTOR_INFO:
—w= CPL;
—x= 1 if and only if the logical processor is in VMX non-root operation;
—y is the linear address of the XSAVE area being used by XSAVEOPT; and
—z is 00000000_00000000H. (This last item implies that XSAVEOPT does not use the modified optimization 
if the last execution of XRSTOR used the compacted fo rm, or if an execution of XRSTORS followed the last 
execution of XRSTOR.)
If XSAVEOPT uses the modified optimization and XMODIFIED[ i] = 0 (see Section 13.6), state component i is 
not saved to the XSAVE area.
(In practice, the benefit of the modified optimization for state component i depends on how the processor is 
tracking state component i; see Section 13.6. Limitations on the tracking ability may result in state component 
i being saved even though is in the same configuration that was loaded by the previous execution of XRSTOR.)
Depending on details of the operating system, an execut ion of XSAVEOPT by a user application might use the 
modified optimization when the most recent execution of XRSTOR was by a different application. Because of 
this, Intel recommends the application soft ware not use the XSAVEOPT instruction.
The MXCSR register and MXCSR_MASK are part of SSE stat e (see Section 13.5.2) and are thus associated with 
bit 1 of RFBM. However, the XSAVEOPT instruction also saves these values when RFBM[2] = 1 (even if RFBM[1] = 
0). The init and modified optimizations do no t apply to the MXCSR register and MXCSR_MASK.
13.10 OPERATION OF XSAVEC
The operation of XSAVEC is similar to that of XSAVE. Two main differences are (1) XSAVEC uses the compacted 
format for the extended region of the XSAVE area; and (2 ) XSAVEC uses the init optimization (see Section 13.6). 
Unlike XSAVEOPT, XSAVEC does not use the modified optimi zation. See Section 13.2 fo r details of how to deter-
mine whether XSAVEC is supported.
The XSAVEC instruction takes a single memory operand, wh ich is an XSAVE area. In addition, the register pair 
The following conditions cause execution of the XSAVEC instruction to generate a fault:
If none of these conditions cause a fault, execution of  XSAVEC writes the XSTATE_BV field of the XSAVE header 
(see Section 13.4.2), setting XSTATE_BV[ i] (0 ≤ i ≤ 63) as follows:2
•If RFBM[ i]=  0 ,  X S T A T E _ B V [ i] is written as 0.
•If RFBM[ i]=  1 ,  X S T A T E _ B V [ i] is set to the value of XINUSE[ i] (see below for an exception made for 
XSTATE_BV[1]). Section 13.6 defines XINUSE to describ e the processor init optimization and specifies the 
initial configuration of each state component. The nature of that optimization implies the following:
— If state component i is in its initial configuration, XSTATE_BV[ i] may be written with either 0 or 1.
1. If CR0.AM = 1, CPL = 3, and EFLAGS.AC =1, an alignment-check exception (#AC) may occur instead of #GP.
2. Unlike the XSAVE and XSAVEOPT instructions, the XSAVEC instruction does not read the XSTATE_BV field of the XSAVE header.13-24 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
— If state component i is not in its initial configuration, XSTATE_BV[ i] is written with 1.
XINUSE[1] pertains only to the state of the XMM regi sters and not to MXCSR. However, if RFBM[1] = 1 and 
MXCSR does not have the value 1F80H, XSAVEC writ es XSTATE_BV[1] as 1 even if XINUSE[1] = 0.
The XSAVEC instructions sets bit 63 of the XCOMP_BV field of the XSAVE header while writing RFBM[62:0] to 
XCOMP_BV[62:0]. The XSAVEC instruction does not write an y part of the XSAVE header  other than the XSTATE_BV 
and XCOMP_BV fields.
Execution of XSAVEC saves into the XSAVE area those state components corresponding to bits that are set in RFBM 
(subject to the init optimization described below). State co mponents 0 and 1 are located in the legacy region of the 
XSAVE area (see Section 13.4.1). Each state component i, 2≤ i ≤ 62, is located in the extended region; the XSAVEC 
instruction always uses the compacted format for the extended region (see Section 13.4.3).
accesses.
Execution of XSAVEC performs the init optimization to reduce the amount of data written to memory. If 
XINUSE[ i] = 0, state component i is not saved to the XSAVE area (even if RFBM[ i] = 1). However, if RFBM[1] = 1 
and MXCSR does not have the value 1F80H, XSAVEC save s all of state component 1 (SSE — including the XMM 
registers) even if XINUSE[1] = 0. Unlike the XSAVE instruction, RFBM[2] does not determine whether XSAVEC 
saves MXCSR and MXCSR_MASK.
13.11 OPERATION OF XSAVES
The operation of XSAVES is similar to that of XSAVEC. The main differences are (1) X SAVES can be executed only 
if CPL = 0; (2) XSAVES can operate on the state componen ts whose bits are set in XCR0 | IA32_XSS and can thus 
operate on supervisor state components; and (3) XSAVES us es the modified optimization (see Section 13.6). See 
Section 13.2 for details of how to determine whether XSAVES is supported.
The XSAVES instruction takes a single memory operand, wh ich is an XSAVE area. In addition, the register pair 
mask . EDX:EAX & (XCR0 | IA32_XSS) (the logical AND the in struction mask with the logical OR of XCR0 and 
IA32_XSS) is the requested-feature bitmap  (RFBM ) of the state components to be saved.
The following conditions cause execution of the XSAVES instruction to generate a fault:

•If CPL > 0 or if the address of the XSAVE area is not 64-byte aligned, a general-protection exception (#GP) 
occurs.
If none of these conditions cause a fault, execution of  XSAVES writes the XSTATE_BV field of the XSAVE header 
(see Section 13.4.2), setting XSTATE_BV[ i] (0 ≤ i ≤ 63) as follows:
MXCSR does not have the value 1F80H, XSAVES writ es XSTATE_BV[1] as 1 even if XINUSE[1] = 0.
processor is in 64-bit mode.)Vol. 1 13-25MANAGING STATE USING THE XSAVE FEATURE SET
The XSAVES instructions sets bit 63 of the XCOMP_BV fi eld of the XSAVE header while writing RFBM[62:0] to 
XCOMP_BV[62:0]. The XSAVES instruction does not write an y part of the XSAVE header other than the XSTATE_BV 
Execution of XSAVES saves into the XSAVE area those state components corresponding to bits that are set in RFBM 
(subject to the optimizations described below). State comp onents 0 and 1 are located in the legacy region of the 
XSAVE area (see Section 13.4.1). Each state component i, 2≤ i ≤ 62, is located in the extended region; the XSAVES 
operation determined by instruction prefixes; in particul ar, see Section 13.5.6, Section 13.5.11, Section 13.5.12, 
and Section 13.5.14 for special treatment by XSAVES of PT  state, UINTR state, LBR state, and AMX state, respec-
tively. See Section 13.13 for details regarding faults caused by memory accesses.
Execution of XSAVES performs the init optimization to  reduce the amount of data written to memory. If 
and MXCSR does not have the value 1F80H, XSAVES save s all of state component 1 (SSE — including the XMM 
registers) even if XINUSE[1] = 0.
Like XSAVEOPT, XSAVES may perform the modified optimi zation. Each execution of XRSTOR and XRSTORS estab-
lishes XRSTOR_INFO as a 4-tuple w,x,y,z (see Section 13.8.3 and Section 13.12). Execution of XSAVES uses the 
modified optimization only if the following all hold:
•w= CPL;
•x= 1 if and only if the logical processor is in VMX non-root operation;
•y is the linear address of the XSAVE area being used by XSAVEOPT; and
•z[63] is 1 and z[62:0] = RFBM[62:0]. (This last item implies that XSAVES does not use the modified optimi-
zation if the last execution of XRSTOR used the standa rd form and followed the last execution of XRSTORS.)
If XSAVES uses the modified  optimization and XMODIFIED[ i] = 0 (see Section 13.6), state component i is not 
saved to the XSAVE area.
13.12 OPERATION OF XRSTORS
The operation of XRSTORS is similar to that of XRSTOR. Three main differences are (1) XRSTORS can be executed only if CPL = 0; (2) XRSTORS can operate on the state co mponents whose bits are set in XCR0 | IA32_XSS and can 
thus operate on supervisor state components; and (3) X RSTORS has only a compacted form (no standard form; 
see Section 13.8). See Section 13.2 for details of how to determine whether XRSTORS is supported.
The XRSTORS instruction takes a single memory operand, wh ich is an XSAVE area. In addition, the register pair 
mask . EDX:EAX & (XCR0 | IA32_XSS) (the logical AND the instruction mask with the logical OR of XCR0 and 
IA32_XSS) is the requested-feature bitmap  (RFBM ) of the state components to be restored.
occurs.
After checking for these faults, the XRSTORS instruction re ads the first 64 bytes of the XSAVE header, including the 
XSTATE_BV and XCOMP_BV fields (see Section 13.4.2). A #GP o ccurs if any of the followin g conditions hold for the 
values read:
•XCOMP_BV[63] = 0.
•XCOMP_BV sets a bit in the range 62:0 that is not set in XCR0 | IA32_XSS.
•XSTATE_BV sets a bit (including bit 63) that is not set in XCOMP_BV.
•Bytes 63:16 of the XSAVE header are not all 0.13-26 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
XRSTORS updates state component i based on the value of bit i in the XSTATE_BV field of the XSAVE header:
configuration of each state component. If XSTA TE_BV[1] = 0, XRSTORS initializes MXCSR to 1F80H.
State component i is set to its initial configuration as indicated above if RFBM[ i]=  1  a n d  X S T A T E _ B V [ i]=  0  —  
by instruction prefixes; in particular, see Section 13.5 .6 and Section 13.5.12 for special treatment by XRSTORS 
of PT state and LBR state, respectively. See Section 13.13 for details regarding faults caused by memory 
accesses.
If XRSTORS is restoring a supervisor state component, the instruction causes a general-protection exception 
(#GP) if it would load any element of that component with  an unsupported value (e.g., by setting a reserved bit 
in an MSR) or if a bit is set in any reserved portion of the state component in the XSAVE area.
component i, 2≤ i ≤ 62, is located in the extended region; XRSTORS uses the compacted format for the 
extended region (see Section 13.4.3).
The MXCSR register is part of SSE state (see Section 13.5.2) and is thus loaded from memory if RFBM[1] = 
XSTATE_BV[ i] = 1. XRSTORS causes a general-protection exce ption (#GP) if it would load MXCSR with an 
illegal value.
If an execution of XRSTORS causes an exception or a VM exit during or after restoring a supervisor state compo-
nent, each element of that state component may have the value it held before the XRSTORS execution, the value 
loaded from the XSAVE area, or the element’s initial value (as defined in Section 13.6). See Section 13.5.6 for some 
special treatment of PT state for the case in which XRSTORS causes an exception or a VM exit.
Like XRSTOR, execution of XRSTORS causes the processor to update is tracking for the init and modified optimiza-
tions (see Section 13.6 and Section 13.8.3) . The following items provide details:
—I f  R F B M [ i]=  1  a n d  X S T A T E _ B V [ i] = 0, state component i may be tracked as init; XINUSE[ i] may be set to 
0 or 1.
—I f  R F B M [ i]=  1  a n d  X S T A T E _ B V [ i] = 1, state component i is tracked as not init; XINUSE[ i] is set to 1.2
•The processor updates its tracking for the modified optimization and records information about the XRSTORS 
execution for future interaction with the XSAVEOPT and XSAVES instructions as follows:
—I f  R F B M [ i] = 1, state component i may be tracked as unmodified; XMODIFIED[ i] may be set to 0 or 1.
— XRSTOR_INFO is set to the 4-tuple w,x,y,z, where w is the CPL; x is 1 if the logical processor is in VMX 
non-root operation and 0 otherwise; y is the linear address of the XSAVE area; and z is XCOMP_BV (this 
implies that z[63] = 1).
Note that, if RFBM is entirely zero (e.g., because the instruction mask in EDX:EAX is zero), no state components are

0 or 1.
zero for the most recent execution of XRSTORS, an execution of XSAVEOPT or XSAVES will identify all state compo-
1. Earlier fault checking ensured that, if the instruction has reached this point in execution and XSTATE_BV[ i] is 1, then XCOMP_BV[ i] is 
also 1.
2. For LBR state (state component 15), XRSTORS may leave XINIUSE[15] unmodified in certain situations even if RFBM[15] = 1 = 
XSTATE_BV[15] = 1. See Section 13.5.12.Vol. 1 13-27MANAGING STATE USING THE XSAVE FEATURE SET
13.13 MEMORY ACCESSES BY  THE XSAVE FEATURE SET
Each instruction in the XSAVE feature set operates on a set of XSAVE-managed state components. The specific set 
of components on which an instruction operates is determined by the values of XCR0, the IA32_XSS MSR, 
EDX:EAX, and (for XRSTOR and XRSTORS) the XSAVE header.
Section 13.4 provides the details necessary to determine th e location of each state component for any execution of 
an instruction in the XSAVE feature set. An execution of an instruction in the XSAVE feature set may access any byte of any state component on which that execution op erates even when saving a state component is omitted 
because it is in its initial configuration; when restoring a state component to its initial configuration; or when XFD 
is enabled for the state components (see Section 13.14).
Section 13.5 provides details of the different XSAVE-mana ged state components. Some portions of some of these 
components are accessible only in 64-bit mode. Executio ns of XRSTOR and XRSTORS outside 64-bit mode will not 
update those portions; executions of XSAVE, XSAVEC, XSAVEOPT, and XSAVES will not modify the corresponding 
locations in memory.
Despite this fact, any execution of these instructions outside 64-bit mode may access any byte in any state compo-
nent on which that execution operates — even those at addresses corresponding to registers that are accessible 
only in 64-bit mode. As a result, such an execution may incur a fault due to an attempt to access such an address.
For example, an execution of XSAVE outside 64-bit mode  may incur a page fault if paging does not map as 
read/write the section of the XSAVE area containing stat e component 7 (Hi16_ZMM state) — despite the fact that 
state component 7 can be accessed only in 64-bit mode.
13.14 EXTENDED FEATURE DISABLE (XFD)
Extended feature disable  (XFD) is an extension to the XSAVE feature set that allows an operating system to 
enable a feature while preventing specific user thread s from using the feature. This section describes XFD.
As noted in Section 13.2, a processor that supports XF D enumerates CPUID.(EAX=0DH ,ECX=1):EAX[4] as 1. Such 
a processor supports two new MSRs: IA32_XFD (MSR address 1C4H) and IA32_XFD_ERR (MSR address 1C5H). 
Each of these MSRs contains a state-component bitmap. Bit i of either MSR can be set to 1 only if 
CPUID.(EAX=0DH,ECX= i):ECX[2] is enumerated as 1 (see Section 13.2). An execution of WRMSR that attempts to 
set an unsupported bit in either MSR causes a general-prot ection fault (#GP). The reset values of both of these 
MSRs are zero.
XFD is enabled for state component i if XCR0[ i] = IA32_XFD[ i] = 1. (IA32_XFD[ i] does not affect processor oper-
ations if XCR0[ i] = 0.) In compacted format, the IA32_XFD MSR does  not impact the computation of XCOMP_BV by 
the XSAVEC or XSAVES instructions and thus does not impact the format of the extended region of the XSAVE area. 
When XFD is enabled for a state component, any instruction that would access that state component does not 
execute and instead generates a device-not-available exception (#NM).
Exceptions are made for certain instructions (including those that initialize the state component). The following 
items provide details:
•LDTILECFG and TILERELEASE initialize the TILEDATA state component. An execution of either of these instruc-
tions does not generate #NM when XCR0[18] = IA32_XFD[18] = 1; instead, it initializes TILEDATA normally. 
(Note that STTILECFG does not use the TILEDATA state component. Thus, an execution of this instruction does 
not generate #NM when XCR0[18] = IA32_XFD[18] = 1.)
•If XRSTOR or XRSTORS is loading state component i and bit i of the XSTATE_BV field of the XSAVE header is 0, 
the instruction does not generate #NM when XCR0[ i] = IA32_XFD[ i] = 1; instead, it initializes the state 
component normally. (If bit i of the XSTATE_BV field of the XSAVE header is 1, the instruction does generate 
#NM.)
•If XSAVE, XSAVEC, XSAVEOPT, or XSAVES is saving the state component i, the instruction does not generate 
#NM when XCR0[ i] = IA32_XFD[ i] = 1; instead, it operates as if XINUSE[i] = 0 (and the state component was 
in its initial state): it saves bit i of XSTATE_BV field of the XSAVE header  as 0; in addition, XSAVE saves the 
initial configuration of the state component (the other instructions do not save state component  i).
•Enclave entry instructions (ENCLU[EENTER] and ENCLU[ERESUME]) generate #NM if XCR0[ i] = IA32_XFD[ i]=  
1 and bit i is set in the XFRM field in the attributes of the enclave being entered.13-28 Vol. 1MANAGING STATE USING THE XSAVE FEATURE SET
When XFD causes an instruction to generate #NM, th e processor loads the IA32_XFD_ERR MSR to identify the 
disabled state component(s). Specifically, the MSR is lo aded with the logical AND of the IA32_XFD MSR and the 
bitmap corresponding to the state component( s) required by the faulting instruction.
Device-not-available exceptions that are not due to XFD — those resulting from setting CR0.TS to 1 — do not 
modify the IA32_XFD_ERR MSR. Vol. 1 14-1CHAPTER 14
Intel® Advanced Vector Extensions (Intel® AVX) introduces 256-bit vector processing capability. The Intel AVX 
instruction set extends 128-bit SIMD instruction sets by employing a new instruction encoding scheme via a vector extension prefix (VEX). Intel AVX also offers several enha nced features beyond those available in prior generations 
of 128-bit SIMD extensions. 
FMA (Fused Multiply Add) extensions enhances Intel AV X further in floating-point numeric computations. FMA 
provides high-throughput, arithmetic operations cover fu sed multiply-add, fused multip ly-subtract, fused multiply 
add/subtract interleave, signed-reversed multiply  on fused multiply-add and multiply-subtract. 
Intel
® Advanced Vector Extensions 2 (Intel® AVX2) provides 256-bit integer SIMD extensions that accelerate 
computation across integer and floating-point domains using 256-bit vector registers.
This chapter summarizes the key features of Intel AVX, FMA, and Intel AVX2.
14.1 INTEL® AVX OVERVIEW
Intel AVX introduces the following architectural enhancements:
•Support for 256-bit wide vectors with the YMM vector register set. 
•256-bit floating-point instruction set enhancement with up to 2X performance gain relative to 128-bit 
•Enhancement of legacy 128-bit SIMD instruction extens ions to support three-operand syntax and to simplify 
•VEX prefix-encoded instruction syntax support for gene ralized three-operand syntax to improve instruction 
programming flexibility and efficient en coding of new instruction extensions.
•Most VEX-encoded 128-bit and 256-bit AVX instructio ns (with both load and computational operation 
semantics) are not restricted to 16-byte or 32-byte memory alignment. 
With the exception of SIMD instructions operating on MMX  registers, almost all legacy 128-bit SIMD instructions 
have AVX equivalents that support three operand syntax . 256-bit AVX instructions em ploy three-operand syntax 
and some with 4-operand syntax. 
14.1.1 256-Bit Wide SIMD Register Support
Intel AVX introduces support for 256-bit wide SIMD regi sters (YMM0-YMM7 in operating modes that are 32-bit or 
less, YMM0-YMM15 in 64-bit mode). The lower 128-bits of  the YMM registers are aliased to the respective 128-bit 
XMM registers. 
Legacy SSE instructions (i.e., SIMD instructions operatin g on XMM state but not using the VEX prefix, also referred 
to non-VEX encoded SIMD instructions) will not access th e upper bits beyond bit 128 of the YMM registers. AVX 
instructions with a VEX prefix and vector length of 1 28-bits zeroes the upper bits (above bit 128) of the YMM 
register. 14-2 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
14.1.2 Instruction Syntax Enhancements
Intel AVX employs an instruction encoding scheme using a new prefix (known as “VEX” prefix). Instruction 
encoding using the VEX prefix can directly encode a regi ster operand within the VEX prefix. This support two new 
instruction syntax in Intel 64 architecture:

instruction syntax in Intel 64 architecture: 
•A non-destructive operand (in a three-operand instruction syntax): The non-destructive source reduces the number of registers, register-register copies and explicit load operations required in typical SSE loops, reduces 
code size, and improves micro-fusion opportunities. 
•A third source operand (in a four-operand instruction synt ax) via the upper 4 bits in an 8-bit immediate field. 
Support for the third source operand is defined for se lected instructions (e.g.,  VBLENDVPD, VBLENDVPS, 
PBLENDVB).
Two-operand instruction syntax previously  expressed in legacy SSE instruction as
ADDPS xmm1, xmm2/m128
128-bit AVX equivalent can be expressed in three-operand syntax as
VADDPS xmm1, xmm2, xmm3/m128
In four-operand syntax, the extra register operand is encoded in the immediate byte.
Note SIMD instructions supporting three-operand syntax bu t processing only 128-bits of data are considered part 
of the 256-bit SIMD instruction set extensions of AVX, be cause bits 255:128 of the destination register are zeroed 
by the processor. 
14.1.3 VEX Prefix Instruction Encoding Support
Intel AVX introduces a new prefix, re ferred to as VEX, in the Intel 64 and IA-32 instruction encoding format. 
Instruction encoding using the VEX pref ix provides the following capabilities:
•Direct encoding of a register operand within VEX. This provides instruction syntax support for non-destructive 
source operand. 
•Efficient encoding of instruction syntax oper ating on 128-bit and 256-bit register sets.Figure 14-1.  256-Bit Wide SIMD RegisterXMM0 YMM0
XMM1 YMM1
. . .
XMM15 YMM15Bit#
0 127128 255Vol. 1 14-3PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
•Compaction of REX prefix functionalit y: The equivalent functionality of th e REX prefix is encoded within VEX. 
•Compaction of SIMD prefix functiona lity and escape byte encoding: The func tionality of SIMD prefix (66H, F2H, 
F3H) on opcode is equivalent to an opcode extensio n field to introduce new processing primitives. This 
functionality is replaced by a more compact representation  of opcode extension within  the VEX prefix. Similarly, 
the functionality of the escape opco de byte (0FH) and two-byte escape (0F38H, 0F3AH) are also compacted 
within the VEX prefix encoding. 
•Most VEX-encoded SIMD numeric and data processing  instruction semantics with memory operand have 
relaxed memory alignment requirements than instructio ns encoded using SIMD prefixes (see Section 14.9).
VEX prefix encoding applies to SIMD instructions operat ing on YMM registers, XMM registers, and in some cases 
with a general-purpose register as one of the operand. VE X prefix is not supported fo r instructions operating on 
MMX or x87 registers. Details of VEX prefix and instru ction encoding are discussed in Chapter 2, “Instruction 
Format,” of Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 2A.
14.2 FUNCTIONAL OVERVIEW
Intel AVX provides comprehensive functional improvements  over previous generations of SIMD instruction exten-
sions. The functional improvements include:
•256-bit floating-point arithmetic primitives: Intel AVX enhances existing 128-bit floating-point arithmetic 
instructions with 256-bit capabilities for floating-point processing. Table 14-1 lists SIMD instructions promoted 
to Intel AVX.
•Enhancements for flexible SIMD data movements: Intel AVX provides a number of new data movement 
primitives to enable efficient SIMD programming in relation to loading non-unit-strided data into SIMD 
registers, intra-register SIMD data manipulation, cond itional expression and branch handling, etc. Enhance-
ments for SIMD data movement primitives cover 256-bit and 128-bit vector floating-point data, and across 
128-bit integer SIMD data processing using VEX-encoded instructions.
Table 14-1.  Promoted SSSE3 and Intel®  SSE, SSE2, SSE3, and SSE4 Instructions
VEX.256 
EncodingVEX.128 
EncodingGroup Instruction If No, Reason?
yes yes YY 0F 1X MOVUPS
no yes MOVSS scalar
yes yes MOVUPDno yes MOVSD scalar
no yes MOVLPS Note 1
no yes MOVLPD Note 1no yes MOVLHPS Redundant with VPERMILPS
yes yes MOVDDUP
yes yes MOVSLDUPyes yes UNPCKLPS
yes yes UNPCKLPD
yes yes UNPCKHPSyes yes UNPCKHPD
no yes MOVHPS Note 1
no yes MOVHPD Note 1no yes MOVHLPS Redundant with VPERMILPS
yes yes MOVAPS
yes yes MOVSHDUPyes yes MOVAPD14-4 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
no no CVTPI2PS MMX
no yes CVTSI2SS scalar
no no CVTPI2PD MMX
no yes CVTSI2SD scalarno yes MOVNTPS
no yes MOVNTPD
no no CVTTPS2PI MMXno yes CVTTSS2SI scalar
no no CVTTPD2PI MMX
no yes CVTTSD2SI scalarno no CVTPS2PI MMX
no yes CVTSS2SI scalar
no no CVTPD2PI MMX
no yes CVTSD2SI scalar
no yes UCOMISS scalarno yes UCOMISD scalar
no yes COMISS scalar
no yes COMISD scalaryes yes YY 0F 5X MOVMSKPS
yes yes MOVMSKPD
yes yes SQRTPSno yes SQRTSS scalar
yes yes SQRTPD
no yes SQRTSD scalaryes yes RSQRTPS
no yes RSQRTSS scalar
yes yes RCPPSno yes RCPSS scalar
yes yes ANDPS
yes yes ANDPDyes yes ANDNPS
yes yes ANDNPD
yes yes ORPSyes yes ORPD
yes yes XORPS
yes yes XORPDyes yes ADDPS
no yes ADDSS scalar
yes yes ADDPDno yes ADDSD scalar
yes yes MULPS
no yes MULSS scalaryes yes MULPD
no yes MULSD scalarVEX.256 
EncodingGroup Instruction If No, Reason?Vol. 1 14-5PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
yes yes CVTPS2PD
no yes CVTSS2SD scalar
yes yes CVTPD2PS
no yes CVTSD2SS scalaryes yes CVTDQ2PS
yes yes CVTPS2DQ
yes yes CVTTPS2DQyes yes SUBPS
no yes SUBSS scalar
yes yes SUBPDno yes SUBSD scalar
yes yes MINPS
no yes MINSS scalar
yes yes MINPD
no yes MINSD scalaryes yes DIVPS
no yes DIVSS scalar
yes yes DIVPDno yes DIVSD scalar
yes yes MAXPS
no yes MAXSS scalaryes yes MAXPD
no yes MAXSD scalar
no yes YY 0F 6X PUNPCKLBW VIno yes PUNPCKLWD VI
no yes PUNPCKLDQ VI
no yes PACKSSWB VIno yes PCMPGTB VI
no yes PCMPGTW VI
no yes PCMPGTD VIno yes PACKUSWB VI
no yes PUNPCKHBW VI
no yes PUNPCKHWD VIno yes PUNPCKHDQ VI
no yes PACKSSDW VI
no yes PUNPCKLQDQ VIno yes PUNPCKHQDQ VI
no yes MOVD scalar
no yes MOVQ scalaryes yes MOVDQA
yes yes MOVDQU
no yes YY 0F 7X PSHUFD VIno yes PSHUFHW VI
no yes PSHUFLW VIVEX.256 
EncodingGroup Instruction If No, Reason?14-6 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
no yes PCMPEQB VI
no yes PCMPEQW VI
no yes PCMPEQD VI
yes yes HADDPDyes yes HADDPS
yes yes HSUBPD
yes yes HSUBPSno yes MOVD VI
no yes MOVQ VI
yes yes MOVDQAyes yes MOVDQU
no yes YY 0F AX LDMXCSR
no yes STMXCSR
yes yes YY 0F CX CMPPS
no yes CMPSS scalaryes yes CMPPD
no yes CMPSD scalar
no yes PINSRW VIno yes PEXTRW VI
yes yes SHUFPS
yes yes SHUFPDyes yes YY 0F DX ADDSUBPD
yes yes ADDSUBPS
no yes PSRLW VIno yes PSRLD VI
no yes PSRLQ VI
no yes PADDQ VIno yes PMULLW VI
no no MOVQ2DQ MMX
no no MOVDQ2Q MMXno yes PMOVMSKB VI
no yes PSUBUSB VI
no yes PSUBUSW VIno yes PMINUB VI
no yes PAND VI
no yes PADDUSB VIno yes PADDUSW VI
no yes PMAXUB VI
no yes PANDN VIno yes YY 0F EX PAVGB VI
no yes PSRAW VI
no yes PSRAD VIno yes PAVGW VI
no yes PMULHUW VIVEX.256 
EncodingGroup Instruction If No, Reason?Vol. 1 14-7PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
no yes PMULHW VI
yes yes CVTPD2DQ
yes yes CVTTPD2DQ
yes yes CVTDQ2PDno yes MOVNTDQ VI
no yes PSUBSB VI
no yes PSUBSW VIno yes PMINSW VI
no yes POR VI
no yes PADDSB VIno yes PADDSW VI
no yes PMAXSW VI
no yes PXOR VI
yes yes YY 0F FX LDDQU VI
no yes PSLLW VIno yes PSLLD VI
no yes PSLLQ VI
no yes PMULUDQ VIno yes PMADDWD VI
no yes PSADBW VI
no yes MASKMOVDQUno yes PSUBB VI
no yes PSUBW VI
no yes PSUBD VIno yes PSUBQ VI
no yes PADDB VI
no yes PADDW VIno yes PADDD VI
no yes SSSE3 PHADDW VI
no yes PHADDSW VIno yes PHADDD VI
no yes PHSUBW VI
no yes PHSUBSW VIno yes PHSUBD VI
no yes PMADDUBSW VI
no yes PALIGNR VIno yes PSHUFB VI
no yes PMULHRSW VI
no yes PSIGNB VIno yes PSIGNW VI
no yes PSIGND VI
no yes PABSB VIno yes PABSW VI
no yes PABSD VIVEX.256 
EncodingGroup Instruction If No, Reason?14-8 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
yes yes SSE4.1 BLENDPS
yes yes BLENDPD
yes yes BLENDVPS Note 2
yes yes BLENDVPD Note 2no yes DPPD
yes yes DPPS
no yes EXTRACTPS Note 3no yes INSERTPS Note 3
no yes MOVNTDQA
no yes MPSADBW VIno yes PACKUSDW VI
no yes PBLENDVB VI
no yes PBLENDW VI
no yes PCMPEQQ VI
no yes PEXTRD VIno yes PEXTRQ VI
no yes PEXTRB VI
no yes PEXTRW VIno yes PHMINPOSUW VI
no yes PINSRB VI
no yes PINSRD VIno yes PINSRQ VI
no yes PMAXSB VI
no yes PMAXSD VIno yes PMAXUD VI
no yes PMAXUW VI
no yes PMINSB VIno yes PMINSD VI
no yes PMINUD VI
no yes PMINUW VIno yes PMOVSXxx VI 
no yes PMOVZXxx VI 
no yes PMULDQ VIno yes PMULLD VI
yes yes PTEST
yes yes ROUNDPDyes yes ROUNDPS
no yes ROUNDSD scalar
no yes ROUNDSS scalarno yes SSE4.2 PCMPGTQ VI
no no SSE4.2 CRC32c integer
no yes PCMPESTRI VIno yes PCMPESTRM VIVEX.256 
EncodingGroup Instruction If No, Reason?Vol. 1 14-9PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
14.2.1 256-Bit Floating-Point Arithmetic Processing Enhancements

Intel AVX provides 35 256-bit floating-point arithmetic instructions, see Table 14-2. The arithmetic operations 
cover add, subtract, multiply, divide, square-root, compare,  max, min, round, etc., on single precision and double 
precision floating-point data. 
The enhancement in AVX on floating-point compare oper ation provides 32 conditional predicates to improve 
programming flexibility in evaluating conditional expressions.
14.2.2 256-Bit Non-Arithmetic Instruction Enhancements
Intel AVX provides primitives for handling data movement within 256-bit floating-point vectors and promotes many 
128-bit floating data processing instructions to handle 256-bit floating-point vectors. 
Intel AVX includes 39 256-bit data movement and processi ng instructions that are promoted from previous gener-
ations of SIMD instruction extensions, ranging from logica l, blend, convert, test, unpa cking, shuffling, load, and 
stores (see Table 14-3). no yes PCMPISTRI VI
no yes PCMPISTRM VI
no no SSE4.2 POPCNT integer
Table 14-2.  Promoted 256-Bit and 128- Bit Arithmetic Intel® AVX Instructions
VEX.256 Encoding VEX.128 Encoding Legacy Instruction Mnemonic
yes yes SQRTPS, SQRTPD, RSQRTPS, RCPPS
yes yes ADDPS, ADDPD, SUBPS, SUBPD
yes yes MULPS, MULPD, DIVPS, DIVPD
yes yes CVTPS2PD, CVTPD2PSyes yes CVTDQ2PS, CVTPS2DQ
yes yes CVTTPS2DQ, CVTTPD2DQ
yes yes CVTPD2DQ, CVTDQ2PDyes yes MINPS, MINPD, MAXPS, MAXPD
yes yes HADDPD, HADDPS, HSUBPD, HSUBPS
yes yes CMPPS, CMPPDyes yes ADDSUBPD, ADDSUBPS, DPPS
yes yes ROUNDPD, ROUNDPS
Table 14-3.  Promoted 256-Bi t and 128-Bit Data Movement Intel® AVX Instructions 
yes yes MOVAPS, MOVAPD, MOVDQA
yes yes MOVUPS, MOVUPD, MOVDQU
yes yes MOVMSKPS, MOVMSKPDyes yes LDDQU, MOVNTPS, MOVNTPD, MOVNTDQ, MOVNTDQA
yes yes MOVSHDUP, MOVSLDUP, MOVDDUPVEX.256 
EncodingGroup Instruction If No, Reason?14-10 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
Intel AVX introduces 18 data processing instructions that  operate on 256-bit vectors, Table 14-4. These new prim-
itives cover the following operations:
•Non-unit-strided fetching of SIMD data . Intel AVX provides several flexible SIMD floating-point data fetching 
primitives: 
— Broadcast of single or multiple data elements into a 256-bit destination.
— Masked move primitives to load or store SIMD data elements conditionally.
•Intra-register manipulation of SIMD da ta elements. Intel AVX provides severa l flexible SIMD floating-point data 
manipulation primitives: 
— Insert/extract multiple SIMD floating-point data elements to/from 256-bit SIMD registers.
— Permute primitives to facilitate efficient manipulation of floating-point data elements in 256-bit SIMD 
•Branch handling. Intel AVX provides several primitives to enable handling of branches in SIMD programming:
— Variable blend instructions supports four-operand syntax with non-destructive source syntax. This is more 
flexible than the equivalent Intel SSE4 instruction synt ax which uses the XMM0 register as the implied mask 
for blend selection. 
— Packed TEST instructions for floating-point data.yes yes UNPCKHPD, UNPCKHPS, UNPCKLPD
yes yes BLENDPS, BLENDPD
yes yes SHUFPD, SHUFPS, UNPCKLPSyes yes BLENDVPS, BLENDVPD
yes yes PTEST, MOVMSKPD, MOVMSKPS
yes yes XORPS, XORPD, ORPS, ORPDyes yes ANDNPD, ANDNPS, ANDPD, ANDPS
Table 14-4.  256-Bit Intel® AVX Instruction Enhancements 
Instruction Description
VBROADCASTF128 ymm1, m128 Broadcast 128-bit floating-point values in mem to low and high 128-bits in ymm1.
VBROADCASTSD ymm1, m64 Broadcast double precision floating-point element in mem to four locations in ymm1.
VBROADCASTSS ymm1, m32 Broadcast single precision floating-point element in mem to eight locations in ymm1.
VEXTRACTF128 xmm1/m128, ymm2, 
imm8Extracts 128-bits of packed floating-point  values from ymm2 and store results in 
xmm1/mem.
VINSERTF128 ymm1, ymm2, 
xmm3/m128, imm8Insert 128-bits of packed floating-point va lues from xmm3/mem and the remaining val-
ues from ymm2 into ymm1.
VMASKMOVPS ymm1, ymm2, m256 Load packed single precision values from mem using mask in ymm2 and store in ymm1.VMASKMOVPD ymm1, ymm2, m256 Load packed double precision values from mem using mask in ymm2 and store in ymm1.
VMASKMOVPS m256, ymm1, ymm2 Stor e packed single precision values from ymm2 mask in ymm1.
VMASKMOVPD m256, ymm1, ymm2 Store packed double pr ecision values from ymm2 using mask in ymm1.
VPERMILPD ymm1, ymm2, ymm3/m256 Permute double precision floating-point values in ymm2 using controls from xmm3/mem 
and store result in ymm1.Table 14-3.  Promoted 256-Bit and 128-Bit Data Movement Intel® AVX Instructions  (Contd.)
VEX.256 Encoding VEX.128 Encoding Legacy Instruction MnemonicVol. 1 14-11PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
14.2.3 Arithmetic Primitives for 128- Bit Vector and Scalar processing
Intel AVX provides a full complement of 128-bit numeric pr ocessing instructions that employ VEX-prefix encoding. 
These VEX-encoded instructions generally provide the sa me functionality over instructions operating on XMM 
register that are encoded using SIMD prefixes. The 128-bit numeric processing instructions in AVX cover floating-
point and integer data processing; across 128-bit vector and scalar processing. Table 14-5 lists the state of promo-tion of legacy SIMD arithmetic ISA to VEX-128 encoding. Legacy SIMD floating-point arithmetic ISA promoted to 
VEX-256 encoding also support VEX-128 encoding (see Table 14-2).
The enhancement in Intel AVX on 128-bit floating-point compare operation provides 32 conditional predicates to 
improve programming flexibility in evaluating conditional expressions. This contrasts with floating-point SIMD 
compare instructions in Intel SSE and SSE2 su pporting only eight conditional predicates. VPERMILPD ymm1, ymm2/m256 imm8 Permute double precision floating-point values in ymm2/mem using controls from imm8 
and store result in ymm1.
VPERMILPS ymm1, ymm2, ymm/m256 Permute sing le precision floating-point values in  ymm2 using controls from ymm3/mem 
VPERMILPS ymm1, ymm2/m256, imm8 Permute sing le precision floating-point values in  ymm2/mem using controls from imm8 
VPERM2F128 ymm1, ymm2, 
ymm3/m256, imm8Permute 128-bit floating-point fields in ymm2 and ymm3/mem using controls from imm8 
VTESTPS ymm1, ymm2/m256 Set ZF if ymm2/mem AND ymm1 result is all 0s in packed single precision sign bits. Set CF 
if ymm2/mem AND NOT ymm1 result is all 0s  in packed single precision sign bits.
VTESTPD ymm1, ymm2/m256 Set ZF if ymm2/mem AND ymm1 result is all 0s in  packed double precision sign bits. Set 
CF if ymm2/mem AND NOT ymm1 result is all 0s in packed double precision sign bits.
VZEROALL Zero all YMM registers.VZEROUPPER Zero upper 128 bits of all YMM registers.
Table 14-5.  Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions 
VEX.256 
EncodingInstruction Reason Not Promoted
no no CVTPI2PS, CVTPI2PD, CVTPD2PI MMX
no no CVTTPS2PI, CVTTPD2PI, CVTPS2PI MMX
no yes CVTSI2SS, CVTSI2SD, CVTSD2SI Scalar
no yes CVTTSS2SI, CVTTSD2SI, CVTSS2SI Scalarno yes COMISD, RSQRTSS, RCPSS Scalar
no yes UCOMISS, UCOMISD, COMISS, Scalar
no yes ADDSS, ADDSD, SUBSS, SUBSD Scalarno yes MULSS, MULSD, DIVSS, DIVSD Scalar
no yes SQRTSS, SQRTSD Scalar
no yes CVTSS2SD, CVTSD2SS Scalarno yes MINSS, MINSD, MAXSS, MAXSD Scalar
no yes PAND, PANDN, POR, PXOR VI
no yes PCMPGTB, PCMPGTW, PCMPGTD VITable 14-4.  256-Bit Intel® AVX In struction Enhancements  (Contd.)
Instruction Description14-12 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
no yes PMADDWD, PMADDUBSW VI
no yes PAVGB, PAVGW, PMULUDQ VI
no yes PCMPEQB, PCMP EQW, PCMPEQD VI
no yes PMULLW, PMULHUW, PMULHW VIno yes PSUBSW, PADDSW, PSADBW VI
no yes PADDUSB, PADDUSW, PADDSB VI
no yes PSUBUSB, PSUBUSW, PSUBSB VIno yes PMINUB, PMINSW VI
no yes PMAXUB, PMAXSW VI
no yes PADDB, PADDW, PADDD, PADDQ VIno yes PSUBB, PSUBW,  PSUBD, PSUBQ VI
no yes PSLLW, PSLLD, PSLLQ, PSRAW VI
no yes PSRLW, PSRLD, PSRLQ, PSRAD VI
CPUID.SSSE3
no yes PHSUBW, PHSUBD, PHSUBSW VI
no yes PHADDW, PHADDD, PHADDSW VI
no yes PMULHRSW VIno yes PSIGNB, PSIGNW, PSIGND VI
no yes PABSB, PABSW, PABSD VI
CPUID.SSE4_1
no yes DPPD
no yes PHMINPOSUW, MPSADBW VI
no yes PMAXSB, PMAXSD, PMAXUD VIno yes PMINSB, PMINSD, PMINUD VI
no yes PMAXUW, PMINUW VI
no yes PMOVSXxx, PMOVZXxx VIno yes PMULDQ, PMULLD VI
no yes ROUNDSD, ROUNDSS Scalar
CPUID.POPCNT
no yes POPCNT Integer
CPUID.SSE4_2
no yes PCMPGTQ VIno no CRC32 Integer
no yes PCMPESTRI, PCMPESTRM VI
no yes PCMPISTRI, PCMPISTRM VI
CPUID.CLMUL
no yes PCLMULQDQ VI
CPUID.AESNITable 14-5.  Promotion of Legacy SIMD ISA to 128- Bit Arithmetic Intel® AV X Instructions  (Contd.)
VEX.256 
EncodingInstruction Reason Not PromotedVol. 1 14-13PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
Description of Column “Reason not promoted”:

no yes DPPD
VEX.256 
•MMX : Instructions referencing MMX registers do not support VEX.
•Scalar: Scalar instructions are not promoted to 256-bit.
•Integer:  Integer instructions are not promoted.
•VI: “Vector Integer” instructions are not promoted to 256-bit.
14.2.4 Non-Arithmetic Primitives for 128-Bit Vector and Scalar Processing
Intel AVX provides a full complement of data processing instructions that employ VEX-prefix encoding. These VEX-
encoded instructions generally provide the same functionalit y over instructions operating on XMM register that are 
encoded using SIMD prefixes. 
A subset of new functionalities listed in Table 14-4 is also extended via VEX.128 encoding. These enhancements in 
AVX on 128-bit data processing primitives include 11 new instructions (see Table 14-6) with the following capabil-
ities:
•Non-unit-strided fetching of SIMD data. AVX provides several flexible SIMD floating-point data fetching 
— broadcast of single data element into a 128-bit destination,
— masked move primitives to load or store SIMD data elements conditionally,
•Intra-register manipulation of SIMD data elements. AVX  provides several flexible SIMD floating-point data 
— permute primitives to facilitate efficient manipulati on of floating-point data elements in 128-bit SIMD 
registers
•Branch handling. AVX provides several primitives to enable handling of branch es in SIMD programming:
— new variable blend instructions supports four-operand syntax with non-destructive source syntax. 
Branching conditions dependent on floating-point data or integer data can benefit from Intel AVX. This is 
more flexible than non-VEX encoded instruction syntax  that uses the XMM0 register as implied mask for 
blend selection. While variable blend with implied XM M0 syntax is supported in SSE4 using SIMD prefix 
encoding, VEX-encoded 128-bit variable blend instruct ions only support the more flexible four-operand 
syntax.
— Packed TEST instructions for floating-point data.no yes AESDEC, AESDECLAST VI
no yes AESENC, AESENCLAST VI
no yes AESIMX, AESKEYGENASSIST VI
Table 14-6.  128-Bit Intel® AVX Instruction Enhancement 
VBROADCASTSS xmm1, m32 Broadcast single precision floating-point element in mem to four locations in xmm1.
VMASKMOVPS xmm1, xmm2, m128 Load packed single precision values from mem using mask in xmm2 and store in xmm1.
VMASKMOVPD xmm1, xmm2, m128 Load packed double precision values from mem using mask in xmm2 and store in xmm1.
VMASKMOVPS m128, xmm1, xmm2 Store packed single precision values from xmm2 using mask in xmm1.VMASKMOVPD m128, xmm1, xmm2 Store packed double precision values from xmm2 using mask in xmm1.Table 14-5.  Promotion of Legacy SIMD ISA to 128- Bit Arithmetic Intel® AV X Instructions  (Contd.)
VEX.256 
EncodingInstruction Reason Not Promoted14-14 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
The 128-bit data processing instructions in AVX cover floa ting-point and integer data movement primitives. Legacy 
SIMD non-arithmetic ISA promoted to VEX-256 encoding also support VEX-128 encoding (see Table 14-3). Table 
14-7 lists the state of promotion of the remaining le gacy SIMD non-arithmetic ISA to VEX-128 encoding. VPERMILPD xmm1, xmm2, xmm3/m128 Permute double precision floating-point values in xmm2 using controls from xmm3/mem 
and store result in xmm1.
VPERMILPD xmm1, xmm2/m128, imm8 Permute double precision floating-point values in xmm2/mem using controls from imm8 
VPERMILPS xmm1, xmm2, xmm3/m128 Permute si ngle precision floating-point values in xmm2 using controls from xmm3/mem 
VPERMILPS xmm1, xmm2/m128, imm8 Permute single precision floating-point values in xmm2/mem using controls from imm8 
VTESTPS xmm1, xmm2/m128 Set ZF if xmm2/mem AND xmm1 result is all 0s in packed single precision sign bits. Set CF 
if xmm2/mem AND NOT xmm1 re sult is all 0s in packed single precision sign bits.
VTESTPD xmm1, xmm2/m128 Set ZF if xmm2/mem AND xmm1 result is all 0s in packed single precision sign bits. Set CF 
if xmm2/mem AND NOT xmm1 re sult is all 0s in packed double precision sign bits.
Table 14-7.  Promotion of Legacy  SIMD ISA to 128-Bit Non-Arit hmetic Intel® AVX instruction 
VEX.256 
no no MOVQ2DQ, MOVDQ2Q MMX
no yes LDMXCSR, STMXCSR
no yes MOVSS, MOVSD, CMPSS, CMPSD Scalarno yes MOVHPS, MOVHPD Note 1
no yes MOVLPS, MOVLPD Note 1
no yes MOVLHPS, MOVHLPS Redundant with VPERMILPSno yes MOVQ, MOVD Scalar
no yes PACKUSWB, PACKSSDW, PACKSSWB VI
no yes PUNPCKHBW, PUNPCKHWD VIno yes PUNPCKLBW, PUNPCKLWD VI
no yes PUNPCKHDQ, PUNPCKLDQ VI
no yes PUNPCKLQDQ, PUNPCKHQDQ VIno yes PSHUFHW, PSHUFLW, PSHUFD VI
no yes PMOVMSKB, MASKMOVDQU VI
no yes PAND, PANDN, POR, PXOR VIno yes PINSRW, PEXTRW, VI
no yes PALIGNR, PSHUFB VI
no yes EXTRACTPS, INSERTPS Note 3
no yes PACKUSDW, PCMPEQQ VITable 14-6.  128-Bit Intel® AVX Instruction Enhancement  (Contd.)
Instruction DescriptionVol. 1 14-15PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
Description of column “Reason not promoted”:
•Note 1 : MOVLPD/PS and MOVHPD/PS are not promoted to 256- bit. The equivalent functionality are provided 
by VINSERTF128 and VEXTRACTF128 instructions as the ex isting instructions have no natural 256b extension
•Note 3 : It is expected that using 128-bit INSERTPS followed by a VINSERTF128 would be better than 
promoting INSERTPS to 256-bit (for example).
14.3 DETECTION OF INTEL® AVX INSTRUCTIONS
Intel AVX instructions operate on the 256-bit YMM register  state. Application detection of new instruction exten-
sions operating on the YMM state follows the general procedural flow in Figure 14-2.
Prior to using Intel AVX, the applicatio n must identify that the operating sy stem supports the XGETBV instruction, 
the YMM register state, in addition to processor’s su pport for YMM state management using XSAVE/XRSTOR and 
AVX instructions. The following si mplified sequence accomplishes both and is strongly recommended.
1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1).
2) Issue XGETBV and verify that XCR0[2:1] = ‘1 1b’ (XMM state and YMM state are enabled by OS).
3) detect CPUID.1:ECX.AVX[bit 28] = 1 (AVX instructions supported).
(Step 3 can be done in any order relative to 1 and 2.)no yes PBLENDVB, PBLENDW VI
no yes PEXTRW, PEXTRB, PEXTRD, PEXTRQ VI
no yes PINSRB, PINSRD, PINSRQ VI
1. If CPUID.01H:ECX.OSXSAVE reports 1, it also indirectly implies the processor su pports XSAVE, XRSTOR, XGETBV, processor 
extended state bit vector XCR0. Thus an application may streamline the checking of CPUID feature flags for XSAVE and OSXSAVE. XSETBV is a privileged instruction.Figure 14-2.  General Procedural Flow of Application Detection of Intel® AVXTable 14-7.  Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic  Intel® AVX instruction  (Contd.)
VEX.256 
Implied HW support for
Check enabled state in
XCR0 via XGETBVCheck feature flag 
for Instruction setCheck feature flag
CPUID.1H:ECX.OSXSAVE = 1? 
OS provides processor
extended state management
State ok to useXSAVE, XRSTOR, XGETBV, XCR0
enabled InstructionsYes 14-16 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
The following pseudocode illustrates this recomm ended application Intel AVX detection process: 
NOTE
It is unwise for an application to rely exclusively on CPUID.1:ECX.AVX[bit 28] or at all on 
CPUID.1:ECX.XSAVE[bit 26]: These indicate hardware  support but not operating system support. If 
YMM state management is not enabled by an oper ating systems, Intel AVX instructions will #UD 
regardless of CPUID.1:ECX.AVX[bit 28]. “CPUID.1:E CX.XSAVE[bit 26] = 1” does not guarantee the 
OS actually uses the XSAVE process for state management.
These steps above also apply to enhanced 128-bit SIMD floating-pointing instructions in Intel AVX (using VEX 
prefix-encoding) that operate on the YMM states. Example 14-1.  Detection of  Intel® AVX Instruction 
INT supports_AVX()
{m o v  e a x ,  1
cpuidand ecx, 018000000Hcmp ecx, 018000000H; check both OSXSAVE and AVX feature flags jne not_supported; processor supports AVX instructions and XGETBV is enabled by OSmov ecx, 0; specify 0 for XCR0 registerXGETBV ; result in EDX:EAXand eax, 06Hcmp eax, 06H; check OS has enabled both XMM and YMM state supportjne not_supportedmov eax, 1jmp done
NOT_SUPPORTED:
mov eax, 0done:
}Vol. 1 14-17PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
14.3.1 Detection of VEX-Encoded AES and VPCLMULQDQ
The VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESI MC/VAESKEYGENASSIST instructions operate on 
YMM states. The detection sequence must combine checki ng for CPUID.1:ECX.AES[bit 25] = 1 and the sequence

{m o v  e a x ,  1
YMM states. The detection sequence must combine checki ng for CPUID.1:ECX.AES[bit 25] = 1 and the sequence 
for detection application support for Intel AVX. 
Similarly, the detection sequence for VPCLMULQDQ must  combine checking for CPUID.1:ECX.PCLMULQDQ[bit 1] = 
1 and the sequence for detection application support for Intel AVX. 
This is shown in the pseudocode provided in Example 14-3.Example 14-2.  Detection of VEX-Encoded Intel® AES-NI Instructions 
INT supports_VAESNI()
{m o v  e a x ,  1
cpuidand ecx, 01A000000Hcmp ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags jne not_supported; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OSmov ecx, 0; specify 0 for XCR0 registerXGETBV ; result in EDX:EAX
and eax, 06H
cmp eax, 06H; check OS has enabled both XMM and YMM state supportjne not_supportedmov eax, 1jmp done
mov eax, 0
done:
Example 14-3.  Detection of VEX-Encoded Intel® AES-NI Instructions 
INT supports_VPCLMULQDQ)
{m o v  e a x ,  1
cpuidand ecx, 018000002Hcmp ecx, 018000002H; check OSXSAVE AVX and PCLMULQDQ feature flags jne not_supported; processor supports AVX and VEX-encoded PCLMULQDQ and XGETBV is enabled by OSmov ecx, 0; specify 0 for XCR0 registerXGETBV ; result in EDX:EAXand eax, 06Hcmp eax, 06H; check OS has enabled both XMM and YMM state supportjne not_supported
mov eax, 1
jmp done
mov eax, 0
done:14-18 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
14.4 HALF PRECISION FLOATING-POINT CONVERSION
VCVTPH2PS and VCVTPS2PH are two instruct ions supporting half precision floating-point data type conversion to 
and from single precision floating-point data types. 
Half precision floating-point values are not used by the pr ocessor directly for arithmetic operations. But the conver-
sion operation are subject to SIMD floating-point exceptions. 
Additionally, the conversion operations of VCVTPS2PH a llow programmer to specify rounding control using control 
fields in an immediate byte. The effects of  the immediate byte are listed in Table 14-8.
Rounding control can use Imm[2] to select an override RC field specified in Imm[1:0] or use MXCSR setting. 
Specific SIMD floating-point exceptions that can occu r in conversion operations are shown in Table 14-9 and 
Table 14-10.
The VCVTPS2PH instruction can cause deno rmal exceptions if the value of the source operand is denormal relative
to the numerical range represented by the source format (see Table 14-11).Table 14-8.  Immediate Byte Encoding for 16-Bit Floating-Point Conversion Instructions
Bits Field Name/value Description Comment
Imm[1:0] RC=00B Round to nearest even If Imm[2] = 0
RC=01B Round down
RC=10B Round upRC=11B Truncate
Imm[2] MS1=0 Use imm[1:0] for rounding Ignore MXCSR.RC 
MS1=1 Use MXCSR.RC for rounding
Imm[7:3] Ignored Ignored by processor
Table 14-9.  Non-Numerical Behavi or for VCVTPH2PS and VCVTPS2PH
Source Operands Masked Result Unmasked Result
QNaN QNaN11
NOTES:
1. The half precision output QNaN1 is created from the single pr ecision input QNaN as follows: the sign bit is preserved, the 8 -bit expo-
nent FFH is replaced by the 5-bit exponent 1FH, and the 24-bit significand is truncated to an 11-bit significand by removing it s 14
least significant bits.QNaN11 (not an exception)
SNaN QNaN12
2. The half precision output QNaN1 is created from the single pr ecision input SNaN as follows: the sign bit is preserved, the 8 -bit expo-
least significant bits. The second most sign ificant bit of the significand is changed from 0 to 1 to convert the signaling NaN into a quiet
NaN.None
Table 14-10.  Invalid Operatio n for VCVTPH2PS and VCVTPS2PH 
Instruction  Condition Maske d Result Unmasked Result
VCVTPH2PS SRC = NaN See Table 14-9 #I=1
VCVTPS2PH SRC = NaN See Table 14-9 #I=1Vol. 1 14-19PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
The VCVTPS2PH instruction can cause an underflow exception if the result of the conversion is less than the un-
derflow threshold for half precision floating-point data type, i.e., | x | < 1.0 ∗ 2−14. 
The VCVTPS2PH instruction can cause an overflow exception if the result of the conversion is greater than the
maximum representable value for half precision floating-point data type, i.e., | x | ≥ 1.0 ∗ 216. 
The VCVTPS2PH instruction can cause an inexact exception if the result of the conversion is not exactly repre-
sentable in the destination format. Table 14-11.  Denormal Condition Summary
Instruction  Condition Masked Result Unmasked Result
VCVTPH2PS SRC is denormal relative to 
input formatres = Result rounded to the destination precision and 
using the bounded exponent, but only if no unmasked 
post-computation exception occurs.
#DE unchangedSame as masked result. 
VCVTPS2PH SRC is denormal relative to 
#DE=1#DE=1
Table 14-12.  Underflow Condition for VCVTPS2PH 
Instruction  Condition Masked Result1
NOTES:
1. Masked and unmasked results are shown in Table 14-11.Unmasked Result
VCVTPS2PH Result < sm allest destination 
precision final normal value2
2.  MXCSR.FTZ is ignored, the processor behaves as if MXCSR.FTZ = 0.Result = +0 or -0, denormal, normal.
#UE =1. 
#PE = 1 if the result is inexact.#UE=1,
#PE = 1 if the result is inexact.
Table 14-13.  Overflow Condition for VCVTPS2PH 
VCVTPS2PH Result ≥ largest destination 
precision finial normal value1Result = +Inf or -Inf.
#OE=1.#OE=1.
Table 14-14.  Inexact Condition for VCVTPS2PH 
NOTES:
1. If a source is denormal relative to input format with DM masked and at least one of PM or UM unmasked, then an exception wil l be
raised with DE, UE, and PE set.Unmasked Result
VCVTPS2PH The result is not 
representable in 
the destination 
formatres = Result rounded to the destination 
precision and using the bounded 
exponent, but only if no unmasked 
underflow or overflow conditions occur (this exception can o ccur in the presence 
of a masked underflow or overflow).
#PE=1 .Only if no underflow/overflow condition occurred, 
or if the corresponding exceptions are masked:
• Set #OE if masked over flow and set result as 
described above for masked overflow.
• Set #UE if masked underflow and set result as 
described above for masked underflow.
If neither underflow nor overflow, result equals 
the result rounded to the destination precision and 
using the bounded exponent set #PE = 1.14-20 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
14.4.1 Detection of F16C Instructions 
Applications using float 16 instruction must follow a detection sequence similar to Intel AVX to ensure:
•The OS has enabled YMM state management support.
•The processor supports Intel AVX as indicated by the CPUID feature flag, i.e., CPUID.01H:ECX.AVX[bit 28] = 1.
•The processor supports 16-bit floating-point conversion instructions via a CPUID feature flag 
(CPUID.01H:ECX.F16C[bit 29] = 1).
Application detection of Float-16 conversion instructio ns follow the general procedural flow in Figure 14-3.
INT supports_f16c(){ ; result in eax
mov eax, 1cpuidand ecx, 038000000H
cmp ecx, 038000000H; check OSXSAVE, AVX, F16C feature flags
 jne not_supported; processor supports AVX,F16C instruct ions and XGETBV is enabled by OS
mov ecx, 0; specify 0 for XCR0 registerXGETBV; result in EDX:EAXand eax, 06Hcmp eax, 06H; check OS has enabled both XMM and YMM state supportjne not_supportedmov eax, 1jmp doneNOT_SUPPORTED:mov eax, 0
done:
}-------------------------------------------------------------------------------Figure 14-3.  General Procedural Flow of Application Detection of Float-16 Implied HW support for
Check enabled YMM state in
XCR0 via XGETBVCheck feature flags 
for AVX and F16CCheck feature flag
enabled InstructionsYes Vol. 1 14-21PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
14.5 FUSED-MULTIPLY-ADD (FMA) EXTENSIONS
FMA extensions also provide 60 128-bit floating-point in structions to process 128-bit vector and scalar data. The 
arithmetic operations cover fused multiply-add, fused multiply-subtract, signed-r eversed multiply on fused 
multiply-add and multiply-subtract. 
Table 14-15.  FMA Instructions 
VFMADD132PD/VFMADD 213PD/VFMADD231PD

xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Multiply-Add of Packed Double Precision Floating-Point 
Values
VFMADD132PS/VFMADD213PS/VFMADD231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Multiply-Add of Packed Single Precision Floating-Point 
Values
VFMADD132SD/VFMADD 213SD/VFMADD231SD
xmm0, xmm1, xmm2/m64Fused Multiply-Add of Scalar Double Precision Floating-Point 
Values
VFMADD132SS/VFMADD213SS/VFMADD231SS
xmm0, xmm1, xmm2/m32Fused Multiply-Add of Scalar Single Precision Floating-Point 
Values
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Multiply-Alternating Add/Su btract of Packed Double Pre-
cision Floating-Point Values
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Multiply-Alternating Add/Subtract of Packed Single Pre-
VFMSUBADD132PD/VFMSUBA DD213PD/VFMSUBADD231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Multiply-Alternating Subt ract/Add of Packed Double Pre-
VFMSUBADD132PS/VFMSUBA DD213PS/VFM SUBADD231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Multiply-Alternating Subtract/Add of Packed Single Pre-
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Multiply-Subtract of Pack ed Double Precision Floating-
Point Values
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Multiply-Subtract of Pack ed Single Precision Floating-
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD
xmm0, xmm1, xmm2/m64Fused Multiply-Subtract of Scal ar Double Precision Floating-
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS
xmm0, xmm1, xmm2/m32Fused Multiply-Subtract of Scalar Single Precision Floating-
VFNMADD132PD/VFNMA DD213PD/VFNMADD231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Negative Multiply-Add of Packed Double Precision Float-
ing-Point Values
VFNMADD132PS/VFNMA DD213PS/VFNMADD231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Negative Multiply-Add of Packed Single Precision Float-
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD
xmm0, xmm1, xmm2/m64Fused Negative Multiply-Add of Scalar Double Precision Float-
VFNMADD132SS/VFNMA DD213SS/VFNMADD231SS
xmm0, xmm1, xmm2/m32Fused Negative Multiply-Add of Scalar Single Precision Float-
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Negative Multip ly-Subtract of Packed  Double Precision 
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS
xmm0, xmm1, xmm2/m128; ymm0, ymm1, ymm2/m256Fused Negative Multip ly-Subtract of Packed  Single Precision 
Floating-Point Values14-22 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
14.5.1 FMA Instruction Operand Order and Arithmetic Behavior
FMA instruction mnemonics are defined explicitly with an  ordered three digits, e.g., VFMADD132PD. The value of 
each digit refers to the ordering of the three source operand as defined by instru ction encoding specification:
•‘1’: The first source operand (also the destination operand) in the syntactical order listed in this specification.
•‘2’: The second source operand in the syntactical order.  This is a YMM/XMM register , encoded using VEX prefix.
•‘3’: The third source operand in the syntactical order. The first and third operand are encoded following ModR/M 
encoding rules. 
The ordering of each digit within the mnemonic refers to th e floating-point data listed on the right-hand side of the 
arithmetic equation of each FMA operation (see Table 14-17):
•The first position in the three digits of a FMA mnemonic  refers to the operand position of the first FP data 
expressed in the arithmetic equation of FMA operation, the multiplicand.
•The second position in the three digits of a FMA mnemonic  refers to the operand position of the second FP data 
expressed in the arithmetic equation of FMA operation, the multiplier.
•The third position in the three digits of a FMA mnemonic  refers to the operand position of the FP data being 
added/subtracted to the multiplication result. 
Note the non-numerical result of an FMA operation does  not resemble the mathematically-defined commutative 
property between the multiplicand and the multiplier values (see Table 14-17). Consequently, software tools (such 
as an assembler) may support a complementary set of FMA mnemonics for each FMA instruction for ease of 
programming to take advantage of the mathematical prop erty of commutative multiplications. For example, an 
assembler may optionally support the complementary mnemonic “VFMADD312PD” in addition to the true 
mnemonic “VFMADD132PD“. The assembler will generate th e same instruction opcode sequence corresponding to 
VFMADD132PD. The processor executes VFMADD132PD and report any NAN conditions based on the definition of 
VFMADD132PD. Similarly, if the complementary mnemonic VFMADD123PD is supported by  an assembler at source 
level, it must generate the opcode sequence corresp onding to VFMADD213PD; the complementary mnemonic 
VFMADD321PD must produce the opcode sequence defined by VFMADD231PD. In the absence of FMA operations 
reporting a NAN result, the numerical results of using either mnemonic with an assembler supporting both 
mnemonics will match the behavior defined in Table 1 4-17. Support for the complementary FMA mnemonics by 
software tools is optional. 
14.5.2 Fused-Multiply-ADD (FMA) Numeric Behavior
FMA instructions can perform fused-multiply-add operatio ns (including fused-multiply-subtract, and other vari-
eties) on packed and scalar data elements in the instruction operands. Separate FMA instructions are provided to 
handle different types of arithmetic operations on the three source operands.
FMA instruction syntax is defined using three source operands and the first source operand is updated based on the 
result of the arithmetic operations of the data elemen ts of 128-bit or 256-bit operands, i.e., The first source 
operand is also the destination operand.
The arithmetic FMA operation performed in an FMA instruct ion takes one of several form s, r=(x*y)+z, r=(x*y)-z, 
r=-(x*y)+z, or r=-(x*y)-z. Pa cked FMA instructions can perform eight single precision FMA operations or four 
double precision FMA operations with 256-bit vectors. 
Scalar FMA instructions only perform one arithmetic oper ation on the low order data element. The content of the 
rest of the data elements in the lower 128-bits of the destination operand is preserved. the upper 128bits of the 
destination operand are filled with zero. VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD
xmm0, xmm1, xmm2/m64Fused Negative Multip ly-Subtract of Scalar Double Precision 
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS
xmm0, xmm1, xmm2/m32Fused Negative Multiply-Subtract of Scalar Single Precision 
Floating-Point ValuesTable 14-15.  FMA Instructions  (Contd.)
Instruction DescriptionVol. 1 14-23PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
An arithmetic FMA operation of the form, r=(x*y)+z, ta kes two IEEE-754-2008 single (double) precision values 
and multiplies them to form an infinite precision intermed iate value. This intermediate value is added to a third 
single (double) precision value (also at infinite precision)  and rounded to produce a single (double) precision result. 
Table 14-17 describes the numerical behavior of the FMA operation, r=(x*y)+z, r=(x *y)-z, r=-(x*y)+z, r=-(x*y)-
z for various input values. The input values can be 0, finite non-zero (F in Table 14-17), infinity of either sign (INF 
in Table 14-17), positive infinity (+INF in Table 14-17), ne gative infinity (-INF in Table 14-17), or NaN (including 
QNaN or SNaN). If any one of the input values is a NAN, th e result of FMA operation, r, may be a quietized NAN. The 
result can be either Q(x), Q(y), or Q(z), see Table 14-17. If x is a NaN, then:
•Q(x) = x if x is QNaN, or
•Q(x) = the quietized NaN obtained from x if x is SNaN.
The notation for the output value in Table 14-17 are:
•“+INF”: positive infinity, “-INF”: negative infinity. When  the result depends on a conditional expression, both 
values are listed in the result column and th e condition is described in the comment column.
•QNaNIndefinite represents the QNaN which has the sign bit equal to 1, the most significand field equal to 1, and 
the remaining significand field bits equal to 0. 
•The summation or subtraction of 0s or identical values in FMA operation can lead to the following situations shown in Table 14-16.
•If the FMA computation represents an invalid operation (e .g., when adding two INF with opposite signs)), the 
invalid exception is signaled, and the MXCSR.IE flag is set.
Table 14-16.  Rounding Behavior of  Zero Result in FMA Operation
Table 14-17.  FMA Numeric Behavior x*y z (x*y) + z (x*y) - z - (x*y) + z - (x*y) - z
(+0) (+0)+0 in all rounding modes - 0 when rounding down,

(+0) (+0)+0 in all rounding modes - 0 when rounding down, 
and +0 otherwise- 0 when rounding down, 
and +0 otherwise- 0 in all rounding modes
(+0) (-0)- 0 when rounding down, 
and +0 otherwise+0 in all rounding modes - 0 in all rounding modes - 0 when rounding down, 
and +0 otherwise
(-0) (+0)- 0 when rounding down, 
and +0 otherwise- 0 in all rounding modes + 0 in all rounding modes - 0 when rounding down, 
(-0) (-0)- 0 in all rounding modes - 0 when rounding down, 
and +0 otherwise+ 0 in all rounding modes
F- F- 0 when rounding down, 
and +0 otherwise2*F -2*F - 0 when rounding down, 
FF2*F - 0 when rounding down, 
and +0 otherwise-2*F
x 
(multiplicand)y 
(multiplier)zr=(x*y)
+zr=(x*y) 
-zr = 
-(x*y)+zr=
-(x*y)-zComment
NaN 0, F, INF, 
NaN0, F, 
INF, 
NaNQ(x) Q(x) Q(x) Q(x) Signal invalid exception if x or y or z is SNaN
0, F, INF NaN 0, F, 
INF, 
NaNQ(y) Q(y) Q(y) Q(y) Signal invalid exception if y or z is SNaN
0, F, INF 0, F, INF NaN Q(z) Q(z) Q(z) Q(z) Signal invalid exception if z is SNaN
INF F, INF +IN
F+INF QNaNIn
definiteQNaNInd
efinite-INF if x*y and z have the same sign
QNaNIn
definite -INF +INF QNaNInd
efiniteif x*y and z have opposite signs14-24 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
If unmasked floating-point exceptions are signaled (inval id operation, denormal operand, overflow, underflow, or 
inexact result) the result register is left unchange d and a floating-point exception handler is invoked.
14.5.3 Detection of FMA 
Hardware support for FMA is indica ted by CPUID.1:ECX.FMA[bit 12]=1. 
Application Software must identify that hardware supports AVX, after that it must also detect support for FMA by 
CPUID.1:ECX.FMA[bit 12]. The recommended pseu docode sequence for detection of FMA is: INF F, INF -INF -INF QNaNIn
efinite+INF if x*y and z have the same sign
QNaNIn
definite +INF -INF QNaNInd
efiniteif x*y and z have opposite signs
INF F, INF 0, F +INF +INF -INF -INF i f x and y have the same sign
-INF -INF +INF +INF if x and y have opposite signs
INF 0 0, F, 
INFQNaNIn
definiteQNaNIn
efiniteQNaNInd
efiniteSignal invalid exception
0I N F 0 ,  F ,  
INFQNaNIn
FI N F + I N
QNaNIn
definite-INF +INF  
QNaNInd
F INF -INF -INF QNaNIn
QNaNIn
definite+INF -INF QNaNInd
F INF 0,F  +INF +INF -INF  -INF if x * y > 0
-INF -INF +INF +INF if x * y < 0
0,F 0,F INF  +INF -INF  +INF -INF if z > 0
-INF +INF -INF +INF if z < 0
0 0 0 0 0 0 0 The sign of the result depends on the sign of 
the operands and on the rounding mode. The 
product x*y is +0 or -0, depending on the signs of x and y. The summat ion/subtraction of the 
zero representing (x*y) and the zero represent-
ing z can lead to one of the four cases shown in 
Table 14-16.0F 0 0 0 0 0
F0 0 0 0 0 0
00 F z - z z - z
0F F z - z z - zF0 F z - z z - z
F F 0 x*y x*y -x*y -x*y Rounded to th e destination precision, with 
bounded exponent
F F F (x*y)+z (x*y)-z -(x*y)+z -(x*y)-z Rounded  to the destinatio n precision, with 
bounded exponent; however, if the exact values 
of x*y and z are equal in magnitude with signs resulting in the FMA operation producing 0, the 
rounding behavior described in Table 14-16.x 
+zr=(x*y) 
-zr = 
-(x*y)-zCommentVol. 1 14-25PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
INT supports_fma(){ ; result in eax
mov eax, 1cpuidand ecx, 018001000H
cmp ecx, 018001000H; check OSXSAVE, AVX, FMA feature flags
 jne not_supported; processor supports AVX,FMA instructions and XGETBV is enabled by OSmov ecx, 0; specify 0 for XCR0 registerXGETBV; result in EDX:EAXand eax, 06Hcmp eax, 06H; check OS has enabled both XMM and YMM state supportjne not_supportedmov eax, 1jmp doneNOT_SUPPORTED:mov eax, 0
done:
}-------------------------------------------------------------------------------Note that FMA comprises 256-bit and 128-bit SIMD instructions operating on YMM states.
14.6 OVERVIEW OF INTEL®  ADVANCED VECTOR EXTE NSIONS 2 (INTEL® AVX2)
Intel® AVX2 extends Intel AVX by promoting most of the 128-bit SIMD integer instructions with 256-bit numeric 
In addition, Intel AVX2 provide enha nced functionalities for broadcast/permute operations on data elements, 
vector shift instructions with variable-shift count per data  element, and instructions to fetch non-contiguous data 
14.6.1 Intel® AVX2 and 256-Bit Vector Integer Processing
Intel AVX2 promotes the vast majority of 128-bit integer SIMD instruction sets to operate with 256-bit wide YMM 
registers. Intel AVX2 instructions are encoded using the VEX prefix and require the sa me operating system support 
as Intel AVX. Generally, most of the promoted 256-bit vect or integer instructions follow the 128-bit lane operation, 
similar to the promoted 256-bit floating-point SIMD instructions in Intel AVX.
Newer functionalities in Intel AVX2 generally fall into the following categories:
•Fetching non-contiguous data elements from memory using vector-index memory addressing. These “gather” 
instructions introduce a new memory-addressing form, consisting of a base register and multiple indices 
specified by a vector register (either XMM or YMM). Data  elements sizes of 32 and 64-bits are supported, and 
data types for floating-point and integer elements are also supported.
•Cross-lane functionalities are provided with several new instructions for broadcast and permute operations. 
Some of the 256-bit vector integer instructions promoted  from legacy SSE instruction sets also exhibit cross-
lane behavior, e.g., VPMOVZ/VPMOVS family.
•Intel AVX2 complements the Intel AVX instructions that  are typed for floating-point operation with a full 
compliment of equivalent set for operating with 32/64-bit integer data elements.14-26 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
•Vector shift instructions with per-element shift count. Data elements sizes of 32 and 64 bits are supported.
14.7 PROMOTED VECTOR INTEGER INSTRUCTIONS IN INTEL® AVX2 
In Intel AVX2, most SSSE3 and Intel SSE, SSE2, SSE3, and SSE4 vector integer instructions have been promoted 
to support VEX.256 encodings. Table 14-18 summarizes the promotion status for existing instructions. The column 
“VEX.128” indicates whether the instruction us ing VEX.128 prefix encoding is supported. 
The column “VEX.256” indicates whether 256-bit vector form  of the instruction using the VEX.256 prefix encoding 
is supported, and under which feature flag. 
Table 14-18.  Promoted Vector Intege r SIMD Instructions in Intel® AVX2 
VEX.256 Encoding VEX.128 Encoding Group Instruction
AVX2 AVX YY 0F 6X PUNPCKLBW
AVX2 AVX PUNPCKLWDAVX2 AVX PUNPCKLDQAVX2 AVX PACKSSWB
AVX2 AVX PCMPGTB
AVX2 AVX PCMPGTWAVX2 AVX PCMPGTD
AVX2 AVX PACKUSWB
AVX2 AVX PUNPCKHBWAVX2 AVX PUNPCKHWD
AVX2 AVX PUNPCKHDQ
AVX2 AVX PACKSSDWAVX2 AVX PUNPCKLQDQ
AVX2 AVX PUNPCKHQDQ
no AVX MOVDno AVX MOVQ
AVX AVX MOVDQA
AVX AVX MOVDQUAVX2 AVX YY 0F 7X PSHUFD
AVX2 AVX PSHUFHW
AVX2 AVX PSHUFLWAVX2 AVX PCMPEQB
AVX2 AVX PCMPEQW
AVX2 AVX PCMPEQDAVX AVX MOVDQA
AVX AVX MOVDQU
no AVX PINSRWno AVX PEXTRW
AVX2 AVX PSRLW
AVX2 AVX PSRLDVol. 1 14-27PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
AVX2 AVX PSRLQ
AVX2 AVX PADDQ
AVX2 AVX PMULLW
AVX2 AVX PMOVMSKBAVX2 AVX PSUBUSB
AVX2 AVX PSUBUSW
AVX2 AVX PMINUBAVX2 AVX PAND
AVX2 AVX PADDUSB
AVX2 AVX PADDUSWAVX2 AVX PMAXUBAVX2 AVX PANDN
AVX2 AVX YY 0F EX PAVGB
AVX2 AVX PSRAWAVX2 AVX PSRAD
AVX2 AVX PAVGW
AVX2 AVX PMULHUWAVX2 AVX PMULHW
AVX AVX MOVNTDQ
AVX2 AVX PSUBSBAVX2 AVX PSUBSW
AVX2 AVX PMINSW
AVX2 AVX PORAVX2 AVX PADDSB
AVX2 AVX PADDSW
AVX2 AVX PMAXSWAVX2 AVX PXOR
AVX AVX YY 0F FX LDDQU
AVX2 AVX PSLLWAVX2 AVX PSLLD
AVX2 AVX PSLLQ
AVX2 AVX PMULUDQAVX2 AVX PMADDWD
AVX2 AVX PSADBW
AVX2 AVX PSUBBAVX2 AVX PSUBW
AVX2 AVX PSUBD
AVX2 AVX PSUBQTable 14-18.  Promoted Vector Integer SIMD  Instructions in In tel® AVX2  (Contd.)
VEX.256 Encoding VEX.128 Encoding Group Instruction14-28 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
AVX2 AVX PADDB
AVX2 AVX PADDW
AVX2 AVX PADDD
AVX2 AVX SSSE3 PHADDWAVX2 AVX PHADDSW
AVX2 AVX PHADDD
AVX2 AVX PHSUBWAVX2 AVX PHSUBSW
AVX2 AVX PHSUBD
AVX2 AVX PMADDUBSWAVX2 AVX PALIGNRAVX2 AVX PSHUFB
AVX2 AVX PMULHRSW
AVX2 AVX PSIGNBAVX2 AVX PSIGNW
AVX2 AVX PSIGND
AVX2 AVX PABSBAVX2 AVX PABSW
AVX2 AVX PABSD
AVX2 AVX MOVNTDQAAVX2 AVX MPSADBW
AVX2 AVX PACKUSDW
AVX2 AVX PBLENDVBAVX2 AVX PBLENDW
AVX2 AVX PCMPEQQ
no AVX PEXTRDno AVX PEXTRQ
no AVX PEXTRB
no AVX PEXTRWno AVX PHMINPOSUW
no AVX PINSRB
no AVX PINSRDno AVX PINSRQ

AVX2 AVX PMAXSB
AVX2 AVX PMAXSDAVX2 AVX PMAXUD
AVX2 AVX PMAXUW
AVX2 AVX PMINSBTable 14-18.  Promoted Vector Integer SIMD Instructions in Intel® AVX2  (Contd.)
VEX.256 Encoding VEX.128 Encoding Group InstructionVol. 1 14-29PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
Table 14-19 compares complementary SIMD functionalities introduced in Intel AVX and AVX2. instructions. AVX2 AVX PMINSD
AVX2 AVX PMINUD
AVX2 AVX PMINUW
AVX2 AVX PMOVSXxxAVX2 AVX PMOVZXxx
AVX2 AVX PMULDQ
AVX2 AVX PMULLDAVX AVX PTEST
AVX2 AVX SSE4.2 PCMPGTQ
no AVX PCMPESTRIno AVX PCMPESTRMno AVX PCMPISTRI
no AVX PCMPISTRM
no AVX AESNI AESDECno AVX AESDECLAST
no AVX AESENC
no AVX AESECNLASTno AVX AESIMC
no AVX AESKEYGENASSIST
no AVX CLMUL PCLMULQDQ
Table 14-19.   VEX-Only SIMD Inst ructions in Intel® AVX and AVX2 
lntel® AVX2 Intel® AVX Comment
VBROADCASTI128 VBROADCASTF128 256-bit onlyVBROADCASTSD ymm1, xmm VBROADCASTSD ymm1, m64 256-bit only
VBROADCASTSS (from xmm) VBROADCASTSS (from m32)
VEXTRACTI128 VEXTRACTF128 256-bit onlyVINSERTI128 VINSERTF128 256-bit only
VPMASKMOVD VMASKMOVPS
VPMASKMOVQ! VMASKMOVPD
VPERMILPD in-lane
VPERMILPS in-lane
VPERM2I128 VPERM2F128 256-bit onlyVPERMD cross-lane
VPERMPS cross-lane
VPERMQ cross-lane
VPERMPD cross-laneTable 14-18.  Promoted Vector Integer SIMD  Instructions in In tel® AVX2  (Contd.)
VEX.256 Encoding VEX.128 Encoding Group Instruction14-30 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
Table 14-20.  New Primitive in Intel® AVX2 Instructions  VTESTPD
VTESTPS
VPBLENDD
VPSLLVD/QVPSRAVD
VPSRLVD/Q
VGATHERDPD/QPDVGATHERDPS/QPS
VPGATHERDD/QD
VPGATHERDQ/QQ
VPERMD ymm1, ymm2, ymm3/m256 Permute doublewords in ymm3/m256 using indexes in ymm2 and store the result in ymm1.VPERMPD ymm1, ymm2/m256, imm8 Permute double precision FP el ements in ymm2/m256 using indexes in imm8 and store the 
result in ymm1.
VPERMPS ymm1, ymm2, ymm3/m256 Permute sing le precision FP elements in ymm3/m2 56 using indexes in ymm2 and store the 
VPERMQ ymm1, ymm2/m256, imm8 Permute quadwords in ymm2/m256 using indexes in imm8 and store the result in ymm1.
VPSLLVD xmm1, xmm2, xmm3/m128 Shift doublewords in xmm2 le ft by amount specified in the corresponding element of 
xmm3/m128 while shifting in 0s.
VPSLLVQ xmm1, xmm2, xmm3/m128 Shift quadwords in xmm2 left by amount specified in the corresponding element of 
VPSLLVD ymm1, ymm2, ymm3/m256 Shift doublewords in ymm2 left by amount specified in the corresponding element of 
ymm3/m256 while shifting in 0s.
VPSLLVQ ymm1, ymm2, ymm3/m256 Shift quadwords in ymm2 left by amount specified in the corresponding element of 
VPSRAVD xmm1, xmm2, xmm3/m128 Shift doublewords in xmm2 right by amount specified in the corresponding element of 
xmm3/m128 while shifting in the sign bits.
VPSRLVD xmm1, xmm2, xmm3/m128 Shift doublewords in xmm2 right by amount specified in the corresponding element of 
VPSRLVQ xmm1, xmm2, xmm3/m128 Shift quadwords in xmm2 right by amount specified in the corresponding element of 
VPSRLVD ymm1, ymm2, ymm3/m256 Shift doublewords in ymm2 right by amount specified in the corresponding element of 
VPSRLVQ ymm1, ymm2, ymm3/m256 Shift quadwords in ymm2 righ t by amount specified in the corresponding element of 
VGATHERDD xmm1, vm32x, xmm2 Using dword indices specified in vm32x, gather dword values from memory conditioned on 
mask specified by xmm2. Conditionally gathered elements are merged into xmm1.
VGATHERQD xmm1, vm64x, xmm2 Using qword indices specified in vm64x, gather dword values from memory conditioned on 
VGATHERDD ymm1, vm32y, ymm2 Using dword indices specified in vm32y, gather dword values from memory conditioned on 
mask specified by ymm2. Conditionally gathered elements are merged into ymm1.
VGATHERQD ymm1, vm64y, ymm2 Using qword indices specified in vm64y, gather dword values from memory conditioned on 
mask specified by ymm2. Conditionally gathered elements are merged into ymm1.Table 14-19.   VEX-Only SIMD Instruct ions in Intel® AVX and AVX2  (Contd.)
lntel® AVX2 Intel® AVX CommentVol. 1 14-31PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
14.7.1 Detection of Intel® AVX2 
Hardware support for Intel AVX2 is indicated by CPUID.(EAX=07H, ECX= 0H):EBX.AVX2[bit 5]=1. 
Application Software must identify that hardware supports In tel AVX, after that it must also detect support for Intel 
AVX2 by checking CPUID.(EAX=07H, ECX=0H):EBX.AVX2[ bit 5]. The recommended pseudocode sequence for 
detection of Intel AVX2 is: 
----------------------------------------------------------------------------------------INT supports_avx2(){ ; result in eax
mov eax, 1cpuidand ecx, 018000000H
cmp ecx, 018000000H; check both OSXSAVE and AVX feature flags
 jne not_supported; processor supports AVX instructions and XGETBV is enabled by OSmov eax, 7VGATHERDPD xmm1, vm32x, xmm2 Using dword indices specified in  vm32x, gather double precis ion FP values from memory 
conditioned on mask specified by xmm2. Conditionally gathered elements are merged into 
xmm1.
VGATHERQPD xmm1, vm64x, xmm2 Using qword indices specified in  vm64x, gather double precis ion FP values from memory 
xmm1.
VGATHERDPD ymm1, vm32x, ymm2 Using dword indices specified in vm32x, gather double precis ion FP values from memory 
conditioned on mask specified by ymm2. Conditionally gathered elements are merged into 
ymm1.
VGATHERQPD ymm1, vm64y ymm2 Using qword indices specified in vm64y, gather double precis ion FP values from memory 
ymm1.
VGATHERDPS xmm1, vm32x, xmm2 Using dword indices specified in vm32x, gather single precision FP values from memory con-
ditioned on mask specified by xmm2. Conditionally gathered elements are merged into 
xmm1.
VGATHERQPS xmm1, vm64x, xmm2 Using qword indices specified in vm64x, gather single precision FP values from memory con-
xmm1.
VGATHERDPS ymm1, vm32y, ymm2 Using dword indices specified in vm32y, gather single precisio n FP values from memory con-
ditioned on mask specified by ymm2. Conditionally gathered elements are merged into 
ymm1.
VGATHERQPS xmm1, vm64y, xmm2 Using qword indices specified in vm64y, gather single precisio n FP values from memory con-
xmm1.
VGATHERDQ xmm1, vm32x, xmm2 Using dword indices specified in vm32x, gather qword values from memory conditioned on 
VGATHERQQ xmm1, vm64x, xmm2 Using qword indices specified in vm64x, gather qword values from memory conditioned on 
VGATHERDQ ymm1, vm32x, ymm2 Using dword indices specified in vm32x, gather qword values from memory conditioned on 
VGATHERQQ ymm1, vm64y, ymm2 Using qword indices specified in vm64y, gather qword values from memory conditioned on 
mask specified by ymm2. Conditionally gathered elements are merged into ymm1.Instruction Description14-32 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
mov ecx, 0
cpuidand ebx, 20H
cmp ebx, 20H; check AVX2 feature flags
 jne not_supportedmov ecx, 0; specify 0 for XCR0 registerXGETBV; result in EDX:EAXand eax, 06Hcmp eax, 06H; check OS has enabled both XMM and YMM state supportjne not_supportedmov eax, 1jmp doneNOT_SUPPORTED:mov eax, 0
done:
}-------------------------------------------------------------------------------
14.8 ACCESSING YMM REGISTERS
The lower 128 bits of a YMM register is aliased to the co rresponding XMM register. Legacy SSE instructions (i.e., 
SIMD instructions operating on XMM state but not using the VEX prefix, also referred to non-VEX encoded SIMD 
instructions) will not access the upper bits (255:128) of the YMM registers. AVX and FMA instructions with a VEX 
prefix and vector length of 128-bits zero es the upper 128 bits of the YMM register.
Upper bits of YMM registers (255:128) can be read and written by many instructions with a VEX.256 prefix. 
XSAVE and XRSTOR may be used to save and restore the upper bits of the YMM registers.
14.9 MEMORY ALIGNMENT 
Memory alignment requirements on VEX-encoded instruct ion differs from non-VEX-encoded instructions. Memory 
alignment applies to non-VEX-encoded SIMD instructions in three categories:
•Explicitly-aligned SIMD load and store instructions accessing 16 bytes of memory (e.g., MOVAPD, MOVAPS,

•Explicitly-aligned SIMD load and store instructions accessing 16 bytes of memory (e.g., MOVAPD, MOVAPS, 
MOVDQA, etc.). These instructions always require memory address to be aligned on 16-byte boundary.
•Explicitly-unaligned SIMD load and store instructions a ccessing 16 bytes or less of data from memory (e.g., 
MOVUPD, MOVUPS, MOVDQU, MOVQ, MOVD, etc.). These in structions do not require memory address to be 
aligned on 16-byte boundary.
•The vast majority of arithmetic and data processing instructions in legacy SSE instructions (non-VEX-encoded 
SIMD instructions) support memory access semantics. When these instructions access 16 bytes of data from 
memory, the memory address must be aligned on 16-byte boundary.
Most arithmetic and data processing instructions encoded using the VEX prefix and performing memory accesses 
have more flexible memory alignment requirements than  instructions that are encoded without the VEX prefix. 
Specifically, 
•With the exception of explicitly aligned 16 or 32 by te SIMD load/store instructions, most VEX-encoded, 
arithmetic and data processing instructions operate in a flexible environment regarding memory address 
alignment, i.e., VEX-encoded instruction with 32-byte or 16-byte load semantics will support unaligned load 
operation by default. Memory arguments for most inst ructions with VEX prefix operate normally without Vol. 1 14-33PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
causing #GP(0) on any byte-granularity alignment (unlike Legacy SSE instructions). The instructions that 
require explicit memory alignment requirements are listed in Table 14-22.
Software may see performance penalties when unaligned accesses cross cacheline boundaries, so reasonable 
attempts to align commonly used data sets should continue to be pursued.
Atomic memory operation in Intel 64 an d IA-32 architecture is guaranteed only for a subset of memory operand 
sizes and alignment scenarios. The list of guaranteed atomic  operations are described in Section 9.1.1 of the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. Intel AVX and FMA instructions do not intro-
duce any new guaranteed atomic memory operations.
Intel AVX instructions can generate an #AC(0) fault on mi saligned 4 or 8-byte memory references in Ring-3 when 
CR0.AM=1. 16 and 32-byte memory references will not generate #AC(0) fault. See Table 14-21 for details.
Certain Intel AVX instructions always require 16- or 32-byt e alignment (see the complete list of such instructions 
in Table 14-22). These instructions will #GP(0) if not a ligned to 16-byte boundaries (for 16-byte granularity loads 
and stores) or 32-byte boundaries (for 32-byte loads and stores).
Table 14-21.  Alignment Faulting Conditions when Memory Access is Not Aligned 
EFLAGS.AC==1 && Ring-3 && CR0.AM == 1 0 1Instruction Type
AVX, FMA,16- or 32-byte “explicitly unaligned” loads and stores (see Table 
14-23)no fault no fault
VEX op YMM, m256 no fault no fault
VEX op XMM, m128 no fault no fault
“explicitly aligned” loads and stores (see Table 14-22) #GP(0) #GP(0)
2, 4, or 8-byte loads and stores no fault #AC(0)SSE16 byte “explicitly unaligned” loads and stores (see Table 14-23) no fault no fault
op XMM, m128 #GP(0) #GP(0)
“explicitly aligned” loads and stores (see Table 14-22) #GP(0) #GP(0)2, 4, or 8-byte loads and stores no fault #AC(0)
Table 14-22.  Instructions Requ iring Explicitly Aligned Memory
Require 16-byte alignment Require 32-byte alignment
(V)MOVDQA xmm, m128 VMOVDQA ymm, m256
(V)MOVDQA m128, xmm VMOVDQA m256, ymm
(V)MOVAPS xmm, m128 VMOVAPS ymm, m256
(V)MOVAPS m128, xmm VMOVAPS m256, ymm
(V)MOVAPD xmm, m128 VMOVAPD ymm, m256(V)MOVAPD m128, xmm VMOVAPD m256, ymm
(V)MOVNTPS m128, xm m VMOVNTPS m256, ymm
(V)MOVNTPD m128, xm m VMOVNTPD m256, ymm
(V)MOVNTDQ m128, xmm VMOVNTDQ m256, ymm
(V)MOVNTDQA xmm, m128 VMOVNTDQA ymm, m25614-34 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2
14.10 SIMD FLOATING-POINT EXCEPTIONS
Intel AVX instructions can generate SIMD floating-point exceptions (#XM) and respond to exception masks in the 
same way as Legacy SSE instructions. When CR4.OSX MMEXCPT=0 any unmasked FP exceptions generate an 
Undefined Opcode exception (#UD).
Intel AVX FP exceptions are created in a similar fashion (d iffering only in number of elements) to Legacy SSE and
SSE2 instructions capable of generating SIMD floating-point exceptions.
AVX introduces no new arithmetic operations (AVX floati ng-point are analogues of existing Legacy SSE instruc-
tions). 
F16C, FMA instructions can generate SIMD floating-point exceptions (#XM). The requirements that apply to Intel
AVX also apply to F16C and FMA.
The subset of Intel AVX2 instructions that oper ate on floating-point data do not generate #XM.
The detailed exception conditions for Intel AVX instructions  and legacy SIMD instructions (excluding instructions 
that operates on MMX registers) are described in a numb er of exception class types, depending on the operand 
syntax and memory operation characteristics. The comple te list of SIMD instruction exception class types are 
defined in Chapter 2, “Instruc tion Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A.
14.11 EMULATION
Setting the CR0.EMbit to 1 prov ides a technique to emulate Legacy SSE floating-point instruction sets in software. 
This technique is not supported with AVX instructions. 
If an operating system wishes to emul ate AVX instructions, set XCR0[2:1] to zero. This will cause AVX instructions 
to #UD. Emulation of F16C, AVX2, and FMA by operating system can be done similarly as with emulating AVX 
14.12 WRITING INTEL® AVX FLOA TING-POINT EXCEPTION HANDLERS
Intel AVX and FMA floating-point exceptions are handled in an entirely analogous way to Legacy SSE floating-point 
exceptions. To handle unmasked SIMD floating-point exce ptions, the operating system or executive must provide 
an exception handler. The section titled “SSE and SSE2 SIMD Floating-Point Exceptions” in Chapter 11, “Program-Table 14-23.  Instructions Not Re quiring Explicit Memory Alignment
(V)MOVDQU xmm, m128
(V)MOVDQU m128, m128
(V)MOVUPS xmm, m128(V)MOVUPS m128, xmm
(V)MOVUPD xmm, m128
(V)MOVUPD m128, xmm
VMOVDQU ymm, m256
VMOVDQU m256, ymm
VMOVUPS ymm, m256VMOVUPS m256, ymm
VMOVUPD ymm, m256
VMOVUPD m256, ymmVol. 1 14-35PROGRAMMING WITH INTEL® AV X, FMA, AND INTEL® AVX2
ming with Streaming SIMD Extensions 2 (SSE2),” describ es the SIMD floating-point exception classes and gives 
suggestions for writing an exception handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point exceptions (#XM), the CR4.OSXM-
MEXCPT flag (bit 10) must be set.
The guidelines for writing Intel AVX floating-point  exception handlers also apply to F16C and FMA.
14.13 GENERAL PURPOSE INST RUCTION SET ENHANCEMENTS
Enhancements in the general-purpose instruction set consist of several categories:
•A rich collection of instructions to manipulate integer data at bit-granul arity. Most of the bit-manipulation 
instructions employ VEX-prefix en coding to support three-operand syntax with non-destructive source 
operands. Two of the bit-manipulating instructions (LZCNT, TZCNT) are not encoded using VEX. The VEX-
encoded bit-manipulation instructions include: ANDN , BEXTR, BLSI, BLSMSK, BLSR, BZHI, PEXT, PDEP, SARX, 
SHLX, SHRX, and RORX. 
•Enhanced integer multiply instruction (MULX) in conjunct ions with some of the bit-manipulation instructions 
allow software to accelerate calculation of large integer numerics (wider than 128-bits).
•INVPCID instruction targets system software that manages processor context IDs.14-36 Vol. 1PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2Vol. 1 15-1CHAPTER 15
15.1 OVERVIEW
The Intel AVX-512 family comprises a collection of instruction set extensions, including AVX-512 Foundation,
AVX-512 Exponential and Reciprocal instructions, AVX-512 Conflict, AVX-512 Prefetch, and additional 512-bit
SIMD instruction extensions, including AVX512-FP16. Inte l AVX-512 instructions are natural extensions to Intel
AVX and Intel AVX2. Intel AVX-512 introduces  the following architectural enhancements:
•Support for 512-bit wide vectors and SIMD register set. 512-bit register state is managed by the operating 
system using XSAVE/XRSTOR instructions introduced in 45 nm Intel 64 processors (see the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 2B, and the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3A). 
•Support for 16 new, 512-bit SIMD registers (for a total of  32 SIMD registers, ZMM0 through ZMM31) in 64-bit 
mode. The extra 16 registers state is managed by the operating system using XSAVE/XRSTOR/XSAVEOPT.
•Support for 8 new opmask registers (k0 through k7) used  for conditional execution and efficient merging of 
destination operands. The opmask register state is managed by the operating system using the 
XSAVE/XRSTOR/XSAVEOPT instructions.

•A new encoding prefix (referred to as  EVEX) to support additional vector length encoding up to 512 bits. The 
EVEX prefix builds upon the foundations of the VEX pref ix to provide compact, efficient encoding for function-
ality available to VEX encoding plus the following enhanced vector capabilities: 
—O p m a s k s .— Embedded broadcast.
— Instruction prefix-embedded rounding control.
— Compressed address displacements.
15.1.1 512-Bit Wide SIMD Register Support
Intel AVX-512 instructions support 512-bit wide SIMD registers (ZMM0-ZMM31). The lower 256-bits of the ZMM 
registers are aliased to the respective 256-bit YMM registers and the lower 128-bit are aliased to the respective 
128-bit XMM registers.
15.1.2 32 SIMD Register Support
Intel AVX-512 instructions also support 32 SIMD re gisters in 64-bit mode (XMM0-XMM31, YMM0-YMM31 and 
ZMM0-ZMM31). The number of available vector  registers in 32-bit mode is still 8.
15.1.3 Eight Opmask Register Support
Intel AVX-512 instructions support 8 opmask registers (k0- k7). The width of each opmask register is architectur-
ally defined as size MAX_KL (64 bits). Seven of the eight opmask registers (k1-k7) can be used in conjunction with 
EVEX-encoded AVX-512 Foundation instructions to provid e conditional execution and efficient merging of data 
elements in the destination operand. The encoding of opmask  register k0 is typically used when all data elements 
(unconditional processing) are desired. Additionally, the opmask registers are also used as vector flags/element-
level vector sources to introduce novel SIMD functional ity as seen in new instructions such as VCOMPRESSPS.15-2 Vol. 1PROGRAMMING WITH INTEL® AVX-512
15.1.4 Instruction Syntax Enhancement
The architecture of EVEX encoding enhances the vector instruction encoding scheme in the following way: 
•512-bit vector-length, up to 32 ZMM registers, and enhanced vector programming environment are supported 
using the enhanced VEX (EVEX).
The EVEX prefix provides more  encodable bit fields than th e VEX prefix. In addition to encoding 32 ZMM registers 
in 64-bit mode, instruction encoding using the EVEX prefix can directly encode 7 (out of 8) opmask register oper-
ands to provide conditional processing in vector instru ction programming. The enhanced vector programming envi-
ronment can be explicitly expressed in the instru ction syntax to include the following elements: 
•An opmask operand: the opmask registers are expressed using the notation “k1” through “k7”. An EVEX-
encoded instruction supporting conditional vector oper ation using the opmask register k1 is expressed by 
attaching the notation {k1} next to the destination operan d. The use of this feature is optional for most instruc-
tions. There are two types of maskin g (merging and zeroing) differentia ted using the EVEX.z bit ({z} in 
instruction signature).
•Embedded broadcast may be supported for some instructio ns on the source operand that can be encoded as a 
memory vector. Data elements of a memory vect or may be conditionally fetched or written to.
•For instruction syntax that operates only on floating-poi nt data in SIMD registers with rounding semantics, the 
EVEX encoding can provide explicit rounding control within  the EVEX bit fields at either scalar or 512-bit vector 
length. 
In AVX-512 instructions, vector addition of all elements of the source operands can be expressed in the same 
syntax as AVX instruction:
VADDPS zmm1, zmm2, zmm3
Additionally, the EVEX encoding scheme of AVX-512 Foun dation can express conditional vector addition as:
VADDPS zmm1 {k1}{z}, zmm2, zmm3
where:
•Conditional processing and updates to destination are expressed with an opmask register.
•Zeroing behavior of the opmask selected destination element is expressed by the {z} modifier (with merging 
as the default if no modifier is specified).Figure 15-1.  512-Bit Wide Vectors and SIMD Register Set. . .
XMM31 ZMM31Bit#
0 255256 511
YMM31127128
XMM1 ZMM1 YMM1XMM0 ZMM0 YMM0Vol. 1 15-3PROGRAMMING WITH INTEL® AVX-512
Note that some SIMD instructions supporting three-operan d syntax but processing only less than or equal to 128-
bits of data are considered part of the 512-bit SIMD in struction set extensions, because bits MAXVL-1:128 of the 
destination register are zeroed by the processor. The same rule applies to instructions operating on 256-bits of data 
where bits MAXVL-1:256 of the destination register are zeroed.
15.1.5 EVEX Instruction Encoding Support
Intel AVX-512 instructions employ a new encoding prefix, re ferred to as EVEX, in the In tel 64 and IA-32 instruction 
encoding format. Instruction encoding using the EV EX prefix provides the following capabilities:
•Direct encoding of a SIMD register operand within EV EX (similar to VEX). This provides instruction syntax 
support for three source operands. 
•Compaction of REX prefix functionality and extended SIMD register encoding: the equivalent REX-prefix 
compaction functionality offered by the VEX prefix is provided within EVEX. Furthermore, EVEX extends the 
operand encoding capability to allow direct addr essing of up to 32 ZMM registers in 64-bit mode.
•Compaction of SIMD prefix functionality and escape by te encoding: the functionality of a SIMD prefix (66H, 
F2H, F3H) on opcode is equivalent to an opcode exte nsion field to introduce new processing primitives. This 
functionality is provided in the VEX prefix encoding sch eme and employed within the EVEX prefix. Similarly, the 
functionality of the escape opcode byte (0FH) and two- byte escape (0F38H, 0F3AH) are also compacted within 
the EVEX prefix encoding. 
•Most EVEX-encoded SIMD numeric and data processing instruction semantics with memory operands have more relaxed memory alignment requirements than instructions encoded using SIMD prefixes (see Section 
15.7, “Memory Alignment”).
•Direct encoding of an opmask operan d within the EVEX prefix. This prov ides instruction syntax support for 
conditional vector-element operation and merging of de stination operand using an opmask register (k1-k7).
•Direct encoding of a broadcast attribute for instruct ions with a memory operand source. This provides 
instruction syntax support for elements broadcasting the second operand before being used in the actual 
•Compressed memory address displace ments for a more compact instruction encoding byte sequence.
EVEX encoding applies to SIMD instructions operating on XMM, YMM, and ZMM registers. EVEX is not supported for 
instructions operating on MMX or x87 registers. Details of  EVEX instruction encoding are discussed in Section 2.7, 
“Intel® AVX-512 Encoding,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
15.2 DETECTION OF AVX-512 FOUNDATION INSTRUCTIONS 
The majority of AVX-512 Foundation instructions are encoded using the EVEX enco ding scheme. EVEX-encoded 
instructions can operate on the 512-bit ZMM register stat e plus 8 opmask registers. The opmask instructions in 
AVX-512 Foundation instructions operate only on opmask  registers or with a general purpose register. System 
software requirements to support the ZMM state and opmask  instructions are described in Section 15.5, “Accessing 
XMM, YMM, AND ZMM Registers.”
Processor support of AVX-512 Foundation instructions is indicated by CPUID.(EAX =07H, ECX=0):EBX.AVX512F[bit 
16] = 1. Detection of AVX-512 Foundation instructions op erating on ZMM states and opmask registers needs to 
follow the general procedural flow in Figure 15-2.15-4 Vol. 1PROGRAMMING WITH INTEL® AVX-512
Prior to using AVX-512 Foundation instructions, the applicat ion must identify that the operating system supports 
the XGETBV instruction and the ZMM register state, in addi tion to confirming the processor’s support for ZMM state 
management using XSAVE/XRSTOR and AVX-512 Foundatio n instructions. The following simplified sequence 
accomplishes both and is strongly recommended.
1. Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1).
2. Execute XGETBV and verify that XCR0[7:5] = ‘111 b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and 
ZMM16-ZMM31 state are enabled by OS ) and that XCR0[2:1] = ‘11b’ (XMM st ate and YMM state are enabled by 
OS).
3. Detect CPUID.0x7.0:EBX.AVX512F[bit 16] = 1.
15.2.1 Additional 512-Bit Instruction Ex tensions of the Intel® AVX-512 Family
Processor support of the Intel AVX-5 12 Exponential and Reciprocal instruct ions are indicated by querying the 
feature flag:
•If CPUID.(EAX=07H, ECX=0):EBX.AVX51 2ER[bit 27] = 1, the collection of 
VEXP2PD/VEXP2PS/VRCP28xx/VRSQRT28xx instructions are supported.
Processor support of the Intel AVX-512 Prefetch instru ctions are indicated by qu erying the feature flag:
•If CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1, a collection of VGATHERPF0xxx/VGATHER-
PF1xxx/VSCATTERPF0xxx/VSCATTERPF1xxx instructions are supported. 
Detection of 512-bit instructions operating on ZMM states  and opmask registers, outside of AVX-512 Foundation,

OS).
Detection of 512-bit instructions operating on ZMM states  and opmask registers, outside of AVX-512 Foundation, 
needs to follow the general procedural flow in Figure 15-3.Figure 15-2.  Procedural Flow for Applicatio n Detection of AVX-512 Foundation Instructions
1. If CPUID.01H:ECX.OSXSAVE reports 1, it also indire ctly implies the processor supports XSAVE, XRSTOR, 
XGETBV, processor extended state bit vector XCR0 regi ster. Thus an application may streamline the checking 
of CPUID feature flags for XSAVE and OSXSAVE. XSETBV is a privileged instruction.Implied HW support for
XCR0 via XGETBVCheck AVX512F flag Check feature flag
States ok to useXSAVE, XRSTOR, XGETBV, XCR0
enabled InstructionsYes 
YMM,ZMMOpmask,Vol. 1 15-5PROGRAMMING WITH INTEL® AVX-512
PREFETCHT1W does not require OS support for XMM/YMM/ZMM/k-reg, SIMD FP exception support.
Procedural Flow of Application Dete ction of other 512-bit extensions:
Prior to using the Intel AVX- 512 Exponential and Reciprocal instructions, the application must identify that the 
operating system supports the XGETBV instruction and the ZMM register state, in addition to confirming the 
processor’s support for ZMM state management using XSAVE/XRSTOR and AVX-512 Foundation instructions. The 
following simplified sequence accomplishes both and is strongly recommended.
1. Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).
2. Execute XGETBV and verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and 
ZMM16-ZMM31 state are enabled by OS) and that XCR0 [2:1] = ‘11b’ (XMM state an d YMM state are enabled 
by OS).
3. Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, and CPUID.0x7.0:EBX.AVX512ER[bit 27] = 1.
Prior to using the Intel AVX-512 Prefet ch instructions, the application must identify that the operating system 
supports the XGETBV instruction and the ZMM register state, in addition to confirming the processor’s support for 
ZMM state management using XSAVE/XRSTOR and AVX-51 2 Foundation instructions. The following simplified 
sequence accomplishes both and is strongly recommended.
by OS).
3. Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, and CPUID.0x7.0:EBX.AVX512PF[bit 26] = 1.
15.2.2 Detection of AVX512-FP16 Instructions
The AVX512-FP16 ISA extensions require that the AVX512BW feature be implemented since the instructions for 
manipulating 32b masks are associated with AVX512BW.Figure 15-3.  Procedural Flow for Appl ication Detection of 512-Bit InstructionsImplied HW support for
XCR0 via XGETBVCheck AVX512F and
additional 512-bit flagsCheck feature flag
YMM,ZMMOpmask,15-6 Vol. 1PROGRAMMING WITH INTEL® AVX-512
15.3 DETECTION OF 512-BIT INST RUCTION GROUPS OF THE INTEL ® AVX-512 
FAMILY
In addition to the Intel AVX-512 Foundation instructions , the Intel AVX-512 family provides several groups of 
instruction extensions that can operate in vector length s of 512/256/128 bits. Each group is enumerated by a 
CPUID leaf 7 feature flag and can be encoded via the EVEX.L ’L field to support operation at vector lengths smaller 
than 512 bits. These instruction groups are listed in Table 15-1.
Software must follow the detection procedure for the 512- bit AVX-512 Foundation instructions as described in 
Section 15.2.
Detection of other 512-bit sibling instruction groups listed  in Table 15-1 (excluding AVX512F) follows the procedure 
described in Figure 15-4.
To detect 512-bit instructions enumerated by AVX512C D, the following sequence is strongly recommended.
1. Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).2. Execute XGETBV and verify that XCR0[7:5] = ‘111 b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and 
OS).
3. Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, CPUID.0x7.0:EBX.AVX512CD[bit 28] = 1.
Similarly, the detection procedure for enumerating 512-bi t instructions reported by AVX512DW follows the same 
flow.Table 15-1.  512-Bit Instruction Gr oups in the Intel® AVX-512 Family
CPUID Leaf 07H Feature Flag Bit Fea ture Flag Abbreviation of 512-Bit Instruction Group SW Detection Flow
CPUID.(EAX=07H, ECX=0):EBX[bit 16] AVX 512F (AVX-512 Foundation) Figure 15-2
CPUID.(EAX=07H, ECX=0):EBX[ bit 28] AVX512CD Figure 15-4
CPUID.(EAX=07H, ECX=0):EBX[ bit 17] AVX512DQ Figure 15-4
CPUID.(EAX=07H, ECX=0):EBX[bit 30] AVX512BW Figure 15-4
Figure 15-4.  Procedural Flow for Applicat ion Detection of 512-Bit Instruction GroupsImplied HW support for
a sibling 512-bit flagCheck feature flag
CPUID.1H:ECX.OXSAVE = 1? 
YMM,ZMMOpmask,Vol. 1 15-7PROGRAMMING WITH INTEL® AVX-512
15.4 DETECTION OF INTEL® AVX-512 INSTRUCTION GROUPS OPERATING AT 
256 AND 128-BIT VECTOR LENGTHS
For each of the 512-bit instruction groups in the Intel AVX-512 family listed in Table 15-1, the EVEX encoding 
scheme may support a vast majority of these instructions operating at 256-bit or 128-bit (if applicable) vector 
lengths. Encoding support for vector lengths sma ller than 512-bits is indicated by CPUID.(EAX=07H, 
ECX=0):EBX[bit 31], abbreviated as AVX512VL.
The AVX512VL flag alone is never sufficient to determ ine a given Intel AVX-512 instruction may be encoded at 
vector lengths smaller than 512 bits. Software must us e the procedure described in Figure 15-5 and Table 15-2.
To illustrate the procedure described in Figure 15-5 and Table 15-2 for software to use EVEX.256 encoded VPCON-
FLICT, the following sequence is provided. It is strongly recommended this sequence is followed.
1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).2) Execute XGETBV and verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and 
ZMM16-ZMM31 state are enabled by OS) and that XCR0[2 :1] = ‘11b’ (XMM state and YMM state are enabled by 
OS).
3) Verify CPUID.0x7.0:EBX.AVX512F[bit 16] = 1,  CPUID.0x7.0:EBX.AVX512CD[bit 28] = 1, and 
CPUID.0x7.0:EBX.AVX512VL[bit 31] = 1.
In some specific cases, AVX512VL may only support EVEX .256 encoding but not EVEX.128. These cases are listed 
in Table 15-3.Figure 15-5.  Procedural Flow for Detection of Intel®  AVX-512 Instructions Operat ing at Vector Lengths < 512
Table 15-2.  Feature Flag Collection Required of 256/128 Bit Vector Lengths for Each Instruction Group 
Usage of 256/128 Vector Lengths Feature Flag Collection to Verify
AVX512F AVX512F & AVX512VL
AVX512CD AVX512F & AVX512CD & AVX512VL
AVX512DQ AVX512F & AVX512DQ & AVX512VL
AVX512BW AVX512F & AVX512BW & AVX512VLImplied HW support for
XCR0 via XGETBVCheck applicable collection of
CPUID flags listed in Table 2-2Check feature flag
YMM,ZMMOpmask,15-8 Vol. 1PROGRAMMING WITH INTEL® AVX-512
15.5 ACCESSING XMM, YMM, AND ZMM REGISTERS
instructions) will not access the upper bits (MAXVL-1:128) of the YMM registers. AVX and FMA instructions with a 
VEX prefix and vector length of 128-bits ze roes the upper 128 bits of the YMM register.
Upper bits of YMM registers (255:128) can be read and wr itten to by many instructions with a VEX.256 prefix. 
XSAVE and XRSTOR may be used to save and restore the upper bits of the YMM registers. The lower 256 bits of a ZMM register are aliased to the corresponding YMM register. Legacy SSE instructions (i.e., 
instructions) will not access the upper bits (MAXVL-1:128) of the ZMM registers, wher e MAXVL is maximum vector 
length (currently 512 bits). AVX and FMA instructions with a VEX prefix and vector length of 128-bits zero the upper 
384 bits of the ZMM register, while the VEX prefix and vect or length of 256-bits zeroes the upper 256 bits of the 
ZMM register.
Upper bits of ZMM registers (511:256) can be read and written to by instructions with an EVEX.512 prefix. 
15.6 ENHANCED VECTOR PROGRAMMING ENVIRONMENT USING EVEX 
ENCODING
EVEX-encoded AVX-512 instructions support an enhanced vector programming environment. The enhanced vector

ENCODING
EVEX-encoded AVX-512 instructions support an enhanced vector programming environment. The enhanced vector 
programming environment uses the combin ation of EVEX bit-field encodings and a set of eight opmask registers to 
provide the following capabilities:
•Conditional vector processing of an EVEX-encoded instru ction. Opmask registers k1 through k7 can be used to 
conditionally govern the per-data-element computational operation and the per-element updates to the 
destination operand of an AVX-512 Foundation instruction. Each bit of the opmask register governs one vector element operation (a vector element can be 8 bits, 16 bits, 32 bits or 64 bits). 
•In addition to providing predication control on vector  instructions via EVEX bit-field encoding, the opmask 
registers can also be used similarly on general-purpose registers as source/destination operands using modR/M 
encoding for non-mask-related instructions. In this case, an opmask register k0 through k7 can be selected.
•In 64-bit mode, 32 vector registers ca n be encoded using the EVEX prefix.
•Broadcast may be supported for some instructions on the operand that can be encoded as a memory vector. 
The data elements of a memory vector may be conditio nally fetched or written to, and the vector size is 
dependent on the data transformation function.
•Flexible rounding control for the register-to-register fl avor of EVEX encoded 512-bit and scalar instructions. 
Four rounding modes are supported by direct encoding within the EVEX prefix, overriding MXCSR settings.
•Broadcast of one element to the rest of the destination vector register.
•Compressed 8-bit displacement encoding scheme to increase the instruction encoding density for instructions that normally require disp32 syntax.Table 15-3.  Instruction Mnemonics That  Do Not Support EVEX.128 Encoding 
Instruction Group Instruction Mnemonics Supporting EVEX.256 Only Using AVX512VL
AVX512F VBROADCASTSD, VBROADCASTF32X4, VEXTRACTI 32X4, VINSERTF32X4, VI NSERTI32X4, VPERMD, 
VPERMPD, VPERMPS, VPERMQ, VSHUFF32X4, VSHUFF64X2, VSHUFI32X4, VSHUFI64X2
AVX512CD
AVX512DQVBROADCASTF32X2, VBROADCASTF64X2, VBROADCA STI32X4, VBROADCASTI6 4X2, VEXTRACTI64X2, 
VINSERTF64X2, VINSERTI64X2, 
AVX512BWVol. 1 15-9PROGRAMMING WITH INTEL® AVX-512
15.6.1 OPMASK Register to Pred icate Vector Data Processing
AVX-512 instructions using EVEX encode a predicate oper and to conditionally control per-element computational 
operation and updating of the result to the destination operand. The predicate operand is known as the opmask 
register. The opmask is a set of eight architectural registers of size MAX_KL (64-bit). Note that from this set of eight 
architectural registers, only k1 through k7 can be addre ssed as a predicate operand. k0 can be used as a regular 
source or destination but cannot be encoded as a predic ate operand. Note also that a predicate operand can be 
used to enable memory fault-suppression for some instru ctions with a memory operand (source or destination). 
As a predicate operand, the opmask registers contain one bi t to govern the operation/update to each data element 
of a vector register. In general, opmask registers can suppo rt instructions with all element sizes: byte (int8), word 
(int16), single precision floating-point (float32), inte ger doubleword(int32), double precision floating-point 
(float64), integer quadword (int64). Therefore, a ZMM vector  register can hold 8, 16, 32, or 64 elements in prin-
ciple. The length of an opmask register, MAX_KL, is sufficien t to handle up to 64 elements with one bit per element, 
i.e., 64 bits. Masking is supported in most of the AVX-512 instructions. For a given vector length, each instruction 
accesses only the number of least significant mask bits th at are needed based on its data type. For example, AVX-
512 Foundation instructions operating on 64-bit data elem ents with a 512-bit vector length, only use the 8 least 
significant bits of the opmask register.
An opmask register affects an AVX-512 instruction at pe r-element granularity. Any numeric or non-numeric oper-
ation of each data element and per-element updates of in termediate results to the destination operand are predi-
cated on the corresponding bit of the opmask register. 
An opmask serving as a predicate operand in AVX-512 obeys the following properties:
•The instruction’s operation is not performed for an elem ent if the corresponding opmask bit is not set. This 
implies that no exception or violation can be caused by an operation on a masked-off element. Consequently, 
no MXCSR exception flag is updated as a result of a masked-off operation.
•A destination element is not updated with the result of the operation if the corresponding writemask bit is not 
set. Instead, the destination element value must be pr eserved (merging-masking) or it must be zeroed out 
(zeroing-masking). 
•For some instructions with a memory operand, memory faults are suppressed for elements with a mask bit of 
0.
Note that this feature provides a versatile construct to implement control-flow predication as the mask in effect 
provides a merging behavior for AVX-512 vector register destinations. As an alternative the masking can be used 
for zeroing instead of merging, so that the masked out el ements are updated with 0 instead of preserving the old 
value. The zeroing behavior is provided to remove the imp licit dependency on the old value when it is not needed.
Most instructions with masking enabled accept both forms of masking. Instructions that must have EVEX.aaa bits 
different than 0 (gather and scatter) and instructions that write to memory only accept merging-masking. 
It’s important to note that the per-element destination u pdate rule also applies when the destination operand is a 
memory location. Vectors are written on a per element basis, based on the opmask register used as a predicate 
operand. 
The value of an opmask register can be:
•Generated as a result of a vector instruction (e.g., CMP, FPCLASS, etc.).
•Loaded from memory.
•Loaded from a GPR register.
•Modified by mask-to-mask operations.
Opmask registers can be used for purposes outside of pred ication. For example, they can be used to manipulate 
sparse sets of elements from a vector, or used to set the EFLAGS based on the 0/0xFFFFFFFFFFFFFFFF/other status of the OR of two opmask registers.
15.6.1.1  Opmask Register K0
The only exception to the opmask rules described above is that opmask k0 can not be used as a predicate operand. 
Opmask k0 cannot be encoded as a predicate operand for a vector operation; the encoding value that would select 
opmask k0 will instead select an implicit opmask value of 0xFFFFFFFFFFFFFFFF, thereby effectively disabling 15-10 Vol. 1PROGRAMMING WITH INTEL® AVX-512
masking. Opmask register k0 can still be used for any in struction that takes opmask register(s) as operand(s) 
(either source or destination).
Note that certain instructions implicitly use the opmask as  an extra destination operand. In such cases, trying to 
use the “no mask” feature will translate into a #UD fault being raised.
15.6.1.2  Example of Opmask Usages
The example below illustrates the predicated vector add op eration and predicated updates of added results into the 
destination operand. The initial state of vect or registers zmm0, zmm1, and zmm2 and k3 are:
MSB........................................LSB
zmm0 =
[ 0x00000003 0x00000002 0x00000001 0x00000000 ] (bytes 15 through 0)
[ 0x00000007 0x00000006 0x00000005 0x00000004 ] (bytes 31 through 16)
[ 0x0000000B 0x0000000A 0x00000009 0x00000008 ] (bytes 47 through 32)
[ 0x0000000F 0x0000000E 0x0000000D 0x0000000C ] (bytes 63 through 48)
zmm1 = 
[ 0x0000000F 0x0000000F 0x0000000F 0x0000000F ] (bytes 15 through 0)
[ 0x0000000F 0x0000000F 0x0000000F 0x0000000F ] (bytes 31 through 16)
[ 0x0000000F 0x0000000F 0x0000000F 0x0000000F ] (bytes 47 through 32)[ 0x0000000F 0x0000000F 0x0000000F 0x0000000F ] (bytes 63 through 48)
zmm2 = 
[ 0xAAAAAAAA 0xAAAAAAAA 0xAAAAAAAA 0xAAAAAAAA ] (bytes 15 through 0)
[ 0xBBBBBBBB 0xBBBBBBBB 0xBBBBBBBB 0xBBBBBBBB ] (bytes 31 through 16)
[ 0xCCCCCCCC 0xCCCCCCCC 0xCCCCCCCC 0xCCCCCCCC ] (bytes 47 through 32)[ 0xDDDDDDDD 0xDDDDDDDD 0xDDDDDDDD 0xDDDDDDDD ] (bytes 63 through 48)
k3 = 0x8F03 (1000 1111 0000 0011)
An opmask register serving as a predicate operand is ex pressed as a curly-braces-enclosed decorator following the 
first operand in the Intel assembly syntax. Given this  state, we will execute the following instruction:
vpaddd zmm2 {k3}, zmm0, zmm1The vpaddd instruction performs 32-bit  integer additions on each data element conditionally based on the corre-
sponding bit value in the predicate op erand k3. Since per-element operations are not operated if the corresponding 
bit of the predicate mask is not set, the intermediate result is:
[ ********** ********** 0x00000010 0x0000000F ] (bytes 15 through 0)
[ ********** ********** ********** ********** ] (bytes 31 through 16)[ 0x0000001A 0x00000019 0x00000018 0x00000017 ] (bytes 47 through 32)[ 0x0000001E ********** ********** ********** ] (bytes 63 through 48)

where ”**********” indicates that no operation is performed.
This intermediate result is then written into the destinat ion vector register, zmm2, using the opmask register k3 as 
the writemask, producing the following final result:Vol. 1 15-11PROGRAMMING WITH INTEL® AVX-512
zmm2 =
[ 0xAAAAAAAA 0xAAAAAAAA 0x00000010 0x0000000F ] (bytes 15 through 0)[ 0xBBBBBBBB 0xBBBBBBBB 0xBBBBBBBB 0xBBBBBBBB ] (bytes 31 through 16)[ 0x0000001A 0x00000019 0x00000018 0x00000017 ] (bytes 47 through 32)[ 0x0000001E 0xDDDDDDDD 0xDDDDDDDD 0xDDDDDDDD ] (bytes 63 through 48)
Note that for a 64-bit instruction (for example, vaddpd), on ly the 8 LSB of mask k3 (0x03) would be used to iden-
tify the predicate operation on each one of th e 8 elements of the source/destination vectors.
15.6.2 OpMask Instructions 
AVX-512 Foundation instructions provide a collection of opmask instructions that allow programmers to set, copy, 
or operate on the contents of a given opmask register. There are three types of opmask instructions:
•Mask read/write instructions : These instructions move data between a general-purpose integer register or 
memory and an opmask mask register, or between two opmask registers. For example:
— kmovw k1, ebx; move lower 16 bits of ebx to k1.
•Flag instructions : This category consists of instructions that modify EFLAGS based on the content of opmask 
— kortestw k1, k2; OR registers k1 and k2 and updated EFLAGS accordingly.
•Mask logical instructions : These instructions perform standard bi twise logical operations between opmask 
— kandw k1, k2, k3; AND lowest 16 bits of registers k2 and k3, leaving the result in k1.
15.6.3 Broadcast
EVEX encoding provides a bit-field to encode data broadcast for some load-op instructions, i.e., instructions that 
load data from memory and perform some computational or data movement operation. A source element from 
memory can be broadcasted (repeated) across all the elemen ts of the effective source operand (up to 16 times for 
a 32-bit data element, up to 8 times for a 64-bit data element). This is useful wh en reusing the same scalar 
operand for all the operations in a vector instruction. Note  that some processors may perform multiple loads of the 
source element and thus software should not rely on atom icity of the data being broadcast (e.g., when the source 
element is simultaneously modified by another logical processor).
Broadcast is only enabled on instructions with an element size of 32 bits or 64 bits. Byte and word instructions do 
not support embedded broadcast. 
The functionality of data broadcast is expressed as a curly-braces-enclosed decorator following the last 
register/memory operand in the Intel assembly syntax.
For instance:
vmulps zmm1, zmm2, [rax] {1to16}
The {1to16} primitive loads one float32 (single precision) element from memory, replicates it 16 times to form a 
vector of 16 32-bit floating-point elements, multiplies the 16 float32 elements with the corresponding elements in the first source operand vector, and puts each of the 16 results into the destination operand. 
AVX-512 instructions with store semantics and pure load instructions do not support broadcast primitives. 
vmovaps [rax] {k3}, zmm1915-12 Vol. 1PROGRAMMING WITH INTEL® AVX-512
In contrast, the k3 opmask register is used as the pred icate operand in the above example. Only the store opera-
tion on data elements corresponding to th e non-zero bits in k3 will be performed.
15.6.4 Static Rounding Mode and Suppress All Exceptions
In previous SIMD instruction extensions (up to AVX and AVX2), rounding control is ge nerally specified in MXCSR, 
with a handful of instructions providing per-instruction rounding override via encoding fields within the imm8 
operand. AVX-512 offers a more flexible encoding attribut e to override MXCSR-based rounding control for floating-
pointing instructions with rounding semantics. This roundin g attribute embedded in the EV EX prefix is called Static 
(per instruction) Rounding Mode or Rounding Mode override . This attribute allows programmers to statically apply 
a specific arithmetic rounding mode irrespective of the value of RM bits in MXCSR. It is available only to register-to-
register flavors of EVEX-encoded floating-point instructio ns with rounding semantic. The differences between these 
three rounding control interfaces  are summarized in Table 15-4. 
The static rounding-mode override in Intel AVX-512 also im plies the “suppress-all-exceptions” (SAE) attribute. The 
SAE effect is as if all the MXCSR mask  bits are set, and none of the MXCS R flags will be updated. Using static 
rounding-mode via EVEX without SAE is not supported.
Static Rounding Mode and SAE control can be enabled in th e encoding of the instruction by setting the EVEX.b bit 
to 1 in a register-register vector instruction. In such a ca se, vector length is assumed to be MAXVL (512-bit in case 
of AVX-512 packed vector instructions) or 128-bit for sca lar instructions. Table 15-5 summarizes the possible static 
rounding-mode assignments in AVX-512 instructions.
Note that some instructions already allow specifying th e rounding mode statically via immediate bits. In such 
cases, the immediate bits take precedence over the embe dded rounding mode (in the same vein that they take 
precedence over whatever MXCSR.RM says).
An example of use would be as follows:
vaddps zmm7 {k6}, zmm2, zmm4, {rd-sae}Table 15-4.  Characteristics of Three Rounding Control Interfaces
Rounding InterfaceStatic Rounding 
OverrideImm8 Embedded Rounding 
OverrideMXCSR Rounding Control
Semantic Requirement FP rounding FP rounding FP rounding
Prefix Requirement EVEX.B = 1 NA NA
Rounding Control EVEX.L’L IMM8[1:0] or MXCSR.RC
(depending on IMM8[2])MXCSR.RC
Suppress All Exceptions (SAE) Implied no no
SIMD FP Exception #XM All suppressed Can raise #I , #P (unless SPE is se t) MXCSR masking controls
MXCSR flag update No yes (except PE if SPE is set) Yes
Precedence Above MXCSR.RC Above EVEX.L’L Default
Scope 512-bit, reg-reg, 
Scalar reg-regROUNDPx, ROUNDSx, 
VCVTPS2PH, VRNDSCALExxAll SIMD operands, vector lengths
Table 15-5.  Static Rounding Mode
{rn-sae} Round to nearest (even) + SAE{rd-sae} Round down (toward -inf) + SAE
{ru-sae} Round up (toward +inf) + SAE
{rz-sae} Round toward zero (Truncate) + SAEVol. 1 15-13PROGRAMMING WITH INTEL® AVX-512
This would perform the single precision floating-point addition of vectors zmm2 and zmm4 with round-towards-
minus-infinity, leaving the result in vector zmm7 using k6 as conditional writemask.
Note that MXCSR.RM bits are ignored and una ffected by the outcome of this instruction.
Examples of instruction instances where the stat ic rounding-mode is not allowed are shown below:
; rounding-mode already specified in the instruction immediatevrndscaleps zmm7 {k6}, zmm2, 0x00
; instructions with memory operands
vmulps zmm7 {k6}, zmm2,[rax], {rd-sae}
; instructions with vector length different than MAXVL (512-bit)
vaddps ymm7 {k6}, ymm2, ymm4,{rd-sae}
15.6.5 Compressed Disp8*N Encoding
EVEX encoding supports a new displacement representation  that allows for a more compact encoding of memory 
addressing commonly used in unrolled code, where an 8-bit displacement can address a range exceeding the 
dynamic range of an 8-bit value. This compressed displace ment encoding is referred to as disp8*N, where N is a 
constant implied by the memory operation characteristic of each instruction. 
The compressed displacement is based on the assumption that the effective displacement (of a memory operand 
occurring in a loop) is a multiple of th e granularity of the memory access of each iteration. Since the base register 
in memory addressing already provides  byte-granular resolution, the lower bits of the traditional disp8 operand 
become redundant, and can be implied fr om the memory operation characteristic. 
The memory operation characteristics depend on the following:
•The destination operand is updated as a full vector, a single element, or multi-element tuples.
•The memory source operand (or vector source operand if the destination operand is memory) is fetched (or 
treated) as a full vector, a single element, or multi-element tuples.
For example:vaddps zmm7, zmm2, disp8[membase + index*8]The destination zmm7 is updated as a full 512-bit vector, and 64-bytes of data are fetched from memory as a full 
vector; the next unrolled iteration may fetch from memory in  64-byte granularity per iteration. There are 6 bits of 
lowest address that can be compressed, hence N = 2^6 = 64. The contribution of “disp8” to effective address 
calculation is 64*disp8.
vbroadcastf32x4 zmm7, disp8[membase + index*8]In VBROADCASTF32x4, memory is fetched as a 4tuple of 4 32-bit entities. Hence the common lowest address bits 
that can be compressed are 4, corresponding to the 4tuple  width of 2^4 = 16 bytes (4x32 bits). Therefore, N = 
2^4.

2^4.
For EVEX encoded instructions that upda te only one element in the destinatio n, or the source element is fetched 
individually, the number of lowest address bits that can be  compressed is generally the width in bytes of the data 
element, hence N = 2^(width).
15.7 MEMORY ALIGNMENT 
Memory alignment requirements on EVEX-encoded SIMD instructions are similar to VEX-encoded SIMD instruc-
tions. Memory alignment applies to EVEX-encod ed SIMD instructions in three categories:
•Explicitly-aligned SIMD load and store instructions a ccessing 64 bytes of memory with EVEX prefix encoded 
vector length of 512 bits (e.g., VMOVAPD, VMOVAPS, VMOVDQA, etc.). These instructions always require the 
memory address to be aligned on a 64-byte boundary.15-14 Vol. 1PROGRAMMING WITH INTEL® AVX-512
•Explicitly-unaligned SIMD load and store instructions a ccessing 64 bytes or less of data from memory (e.g., 
VMOVUPD, VMOVUPS, VMOVDQU, VMOV Q, VMOVD, etc.). These instructions do not require the memory 
address to be aligned on a natural vector-length byte boundary.
•Most arithmetic and data processing instructions encoded using EVEX support memory access semantics. 
When these instructions access from memory, there are no alignment restrictions.
Software may see performance penalties when unaligned accesses cross cacheline boundaries or vector-length 
naturally-aligned boundaries, so reason able attempts to align commonly used data sets should continue to be 
pursued.
Atomic memory operation in Intel 64 and IA-32 architecture  is guaranteed only for a subset of memory operand 
sizes and alignment scenarios. The guaranteed atomic op erations are described in Section 9.1.1, “Guaranteed 
Atomic Operations,” of the Intel® 64 and IA-32 Architectures Software De veloper’s Manual, Volume 3A. Intel AVX 
and FMA instructions do not introduce any new guaranteed atomic memory operations.
Intel AVX-512 instructions may generate an #AC(0) fault on  misaligned 4 or 8-byte memory references in Ring-3 
when CR0.AM=1. 16, 32, and 64-byte memory references will not generate an #AC(0) fault. See Table 15-7 for 
details.
Certain AVX-512 Foundation instructions always require 64 -byte alignment (see the comp lete list of VEX and EVEX 
encoded instructions in Table 15-6). These instructio ns will #GP(0) if not aligned to 64-byte boundaries.
15.8 SIMD FLOATING-POINT EXCEPTIONS
AVX-512 instructions can generate SIMD floating-point exceptions (#XM) if embedded “suppress all exceptions” 
(SAE) in EVEX is not set. When SAE is not set, these inst ructions will respond to exception masks of MXCSR in the 
same way as VEX-encoded AVX instructions. When CR4. OSXMMEXCPT=0, any unmasked FP exceptions generate 
an Undefined Opcode exception (#UD).Table 15-6.   SIMD In structions Requiring Explicitly Aligned Memory
Require 16-byte alignment Require 32-byte  alignment Require 64-byte alignment*
(V)MOVDQA xmm, m128 VMOVDQA ymm, m256 VMOVDQA zmm, m512
(V)MOVDQA m128, xmm VMOVDQA m256, ymm VMOVDQA m512, zmm
(V)MOVAPS xmm, m128 VMOVAPS ymm, m256 VMOVAPS zmm, m512
(V)MOVAPS m128, xmm VMOVAPS m256, ymm VMOVAPS m512, zmm
(V)MOVAPD xmm, m128 VMOVAPD ymm, m256 VMOVAPD zmm, m512(V)MOVAPD m128, xmm VMOVAPD m256, ymm VMOVAPD m512, zmm
(V)MOVNTDQA xmm, m128 VMOVNTPS m256, ymm VMOVNTPS m512, zmm
(V)MOVNTPS m128, xmm VMOVNTPD m256, ymm VMOVNTPD m512, zmm
(V)MOVNTPD m128, xmm VMOVNTDQ m256, ymm VMOVNTDQ m512, zmm
(V)MOVNTDQ m128, xmm V MOVNTDQA ymm, m256 VMOVNTDQA zmm, m512
Table 15-7.  Instructions Not Requ iring Explicit Memory Alignment
(V)MOVDQU xmm, m128 VMOVDQU ymm, m256 VMOVDQU zmm, m512
(V)MOVDQU m128, m128 VMOVDQU m256, ymm VMOVDQU m512, zmm
(V)MOVUPS xmm, m128 VMOVUPS ymm, m256 VMOVUPS zmm, m512
(V)MOVUPS m128, xmm VMOVUPS m256, ymm VMOVUPS m512, zmm
(V)MOVUPD xmm, m128 VMOVUPD ymm, m256 VMOVUPD zmm, m512
(V)MOVUPD m128, xmm VMOVUPD m256, ymm VMOVUPD m512, zmmVol. 1 15-15PROGRAMMING WITH INTEL® AVX-512
15.9 INSTRUCTION EXCEPTION SPECIFICATION
Exception behavior of VEX-encoded Intel AVX and In tel AVX2 instructions are described in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 2A. Ex ception behavior of Intel AVX-512 Foundation instruc-
tions and additional 512-bit extensions are described in Section 2.8, “Exception Classifications of EVEX-Encoded 
instructions,” and Section 2.9, “Exception Classificati ons of Opmask instructions, Type K20 and Type K21.”
15.10 EMULATION
Setting the CR0.EM bit to 1 provides a technique to emulate legacy Intel SSE floating-point instruction sets in soft-
ware. This technique is not supported with Intel AVX instructions, nor FMA instructions. 
If an operating system wishes to emulate Intel AVX instru ctions, set XCR0[2:1] to zero. This will cause Intel AVX 
instructions to #UD. Emulatio n of FMA by the operating system can be done similarly as with emulating Intel AVX 
15.11 WRITING FLOATING-POINT EXCEPTION HANDLERS
Intel AVX-512, Intel AVX, and FMA floating-point exceptions  are handled in an entirely analogous way to legacy 
SSE floating-point exceptions. To handle unmasked SIMD floating-point exceptions, the operating system or exec-
utive must provide an exception handler. Section 11.5.1 , “SIMD Floating-Point Exceptions,” describes the SIMD 
floating-point exception classes and gives suggestions for writing an exception handler to handle them.
MEXCPT flag (bit 10) must be set.15-16 Vol. 1PROGRAMMING WITH INTEL® AVX-512Vol. 1 16-1CHAPTER 16
PROGRAMMING WITH INTEL® TRANSACTIONAL SYNCHRONIZATION
EXTENSIONS
16.1 OVERVIEW
This chapter describes the software programming interface to the Intel® Transactional Synchronization Extensions 
of the Intel 64 architecture.
Multi-threaded applications take adva ntage of increasing number of cores to achieve high performance. However, 
writing multi-threaded applications requires programmers to reason about data sharing among multiple threads. 
Access to shared data typically requires synchronizatio n mechanisms. These mechanisms ensure multiple threads 
update shared data by serializing operations on the sh ared data, often through the use of a critical section 
protected by a lock. Since serialization limits concurrenc y, programmers try to limit synchronization overheads. 
They do this either through minimizing the use of synchr onization or through the use of fine-grain locks; where 
multiple locks each protect different shared data. Unfortunately, this process is difficult and error prone; a missed 
or incorrect synchronization can cause an application to fail. Conservatively adding synchronization and using 
coarser granularity locks, where a few locks each protect many items of shared data, helps avoid correctness prob-
lems but limits performance due to excessive serializatio n. While programmers must use static information to 
determine when to serialize, the determination as to wh ether actually to serialize is best done dynamically. 
Intel® Transactional Synchronization Extensions aim to impr ove the performance of lock-protected critical sections 
while maintaining the lock-based programming model.
16.2 INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS
Intel® Transactional Synchronization Extensions (Intel® TSX) allow the processor to determine dynamically 
whether threads need to serialize through lock-protected cr itical sections, and to perform serialization only when 
required. This lets the hardware expose and exploit conc urrency hidden in an application due to dynamically unnec-
essary synchronization through a technique known as lock elision. 
With lock elision, the hardware executes the programmer-specified critical sections (also referred to as transac-
tional regions) transactionally. In such an execution, the lock variable is only read within the transactional region; 
it is not written to (and therefore not acquired) with the expectation that the lock variable remains unchanged after 
the transactional region, thus exposing concurrency.
If the transactional execution completes successfully, then the hardware ensures that all memory operations 
performed within the transactional region will appear to  have occurred instantaneously when viewed from other 
logical processors, a process referred to as an atomic commit . Any updates performed within the transactional 
region are made visible to other processors only on an atomic commit.
Since a successful transactional execution ensures an atomic commit, the processor can execute the programmer-
specified code section optimistically without synchronizat ion. If synchronization was unnecessary for that specific 
execution, execution can commit without any cross-thread serialization. 
If the transactional execution is unsuccessful, the processor cannot commit the updates atomically. When this 
happens, the processor will roll back the execution, a process referred to as a transactional abort . On a transac-

tional abort, the processor will discard all updates performe d in the region, restore architectural state to appear as 
if the optimistic execution never occurred, and resume execution non-transactionally. Depending on the policy in place, lock elision may be retried or the lock may be explicitly acquired to ensure forward progress.
Intel TSX provides two software interfaces for programmers.
•Hardware Lock Elision (HLE) is a legacy compatible instruction set extension comprising the XACQUIRE and 
XRELEASE prefixes.
•Restricted Transactional Memory (RTM) is an instruction set interface comprising the XBEGIN and XEND 
instructions. 16-2 Vol. 1PROGRAMMING WITH INTEL® TRANSACT IONAL SYNCHRONIZ ATION EXTENSIONS
Programmers who would like to run Intel TSX-enabled softwa re on legacy hardware would use the HLE interface to 
implement lock elision. On the other hand, programmers who do not have legacy hardware requirements and who 
deal with more complex locking primitives would use the RTM software interface of In tel TSX to implement lock 
elision. In the latter case when using new instructions, the programmer must always provide a non-transactional 
path (which would have code to eventu ally acquire the lock being elided) to execute following a transactional abort 
and must not rely on the transactional execution alone.
Intel TSX provides the XTEST instruction to test whether a logical processor is executing transactionally, and the 
XABORT instruction to abort a transactional region.
A processor can perform a transactional abort for numerous reasons. A primary cause is due to conflicting accesses 
between the transactionally executing logical processor an d another logical processor. Such conflicting accesses 
may prevent a successful transactional execution. Memory addresses read from within a transactional region 
constitute the read-set  of the transactional region and addresses written to within the transactional region consti-
tute the write-set  of the transactional region. Intel TSX maintains the read- and write-sets at the granularity of a 
cache line. 
A conflicting data access occurs if another logical processor either reads a location that is part of the transactional 
region’s write-set or writes a location that is a part of either the read- or write-set of the transactional region. We 
refer to this as a data conflict . Since Intel TSX detects data conflicts at the granularity of a cache line, unrelated 
data locations placed in the same cache line will be detect ed as conflicts. Transactional aborts may also occur due 
to limited transactional resources. For example, the amount of data accessed in the region may exceed an imple-mentation-specific capacity. Additionally, some instruct ions and system events may cause transactional aborts. 
Additionally, Intel TSX provides the XSUSLDTRK and XRESLD TRK instructions to suspend and resume load address 
tracking.
16.2.1 HLE Software Interface
HLE provides two instruction prefix hints: XACQUIRE and XRELEASE. 
The programmer uses the XACQUIRE prefix  in front of the instruction that is used to acquire the lock that is 
protecting the critical section. The processor treats the indication as a hint to elide the write associated with the lock acquire operation. Even though th e lock acquire has an associated write operation to the lock, the processor 
does not add the address of the lock to the transactional re gion’s write-set nor does it issue any write requests to 
the lock. Instead, the address of the lo ck is added to the read-set. The logical processor enters transactional execu-
tion. If the lock was available before the XACQUIRE prefixed instruction, all other processors will continue to see it 
as available afterwards. Since the transactionally executin g logical processor neither added the address of the lock 
to its write-set nor performed externally visible write oper ations to it, other logical processors can read the lock 
without causing a data conflict. This allows other logical pr ocessors to also enter and concurrently execute the crit-
ical section protected by the lock. The processor automati cally detects any data conflicts that occur during the 
transactional execution and will perform a transactional abort if necessary.
Even though the eliding processor did not perform any exte rnal write operations to the lock, the hardware ensures 
program order of operations on the lock. If the eliding proc essor itself reads the value of the lock in the critical 
section, it will appear as if the processor had acquired th e lock, i.e., the read will return the non-elided value. This 
behavior makes an HLE execution functionally equivalent to an execution without the HLE prefixes.
The programmer uses the XRELEASE prefix in front of the inst ruction that is used to release the lock protecting the 
critical section. This involves a write to the lock. If the in struction is restoring the value of the lock to the value it 
had prior to the XACQUIRE prefixed lock acquire operation on the same lock, then the processor elides the external 
write request associated with the release of the lock and do es not add the address of the lock to the write-set. The 
processor then attempts to commit the transactional execution. 
With HLE, if multiple threads execute critical sections protected by the same lock but they do not perform any 
conflicting operations on each other’s data, then the threads can execute concurrently and without serialization. 
Even though the software uses lock acquisition operations  on a common lock, the hardwa re recognizes this, elides 
the lock, and executes the critical sections on the two threads without requiring any communication through the 
lock — if such communication was dynamically unnecessary.
If the processor is unable to execute the region transactionally, it will execute the region non-transactionally and 
without elision. HLE enabled software has the same forw ard progress guarantees as the underlying non-HLE lock-
based execution. For successful HLE execution, the lock and the critical section code must follow certain guidelines Vol. 1 16-3PROGRAMMING WITH INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS
(discussed in Section 16.3.3 and Section 16.3.9). These guid elines only affect performance; not following these 
guidelines will not cause a functional failure.
Hardware without HLE support will ignore the XACQUIRE  and XRELEASE prefix hints and will not perform any 
elision since these prefixes correspond to the REPNE/REPE  IA-32 prefixes which are ignored on the instructions 
where XACQUIRE and XRELEASE are valid. Importantly, HLE is compatible with the existing lock-based program-
ming model. Improper use of hints will not cause functional  bugs though it may expose latent bugs already in the 
code. 
16.2.2 RTM Software Interface
RTM provides three instructions: XBEGIN, XEND, and XABORT. 
Software uses the XBEGIN instruction to specify the start of the transactional region and the XEND instruction to 
specify the end of the transactional region. The XBEGIN inst ruction takes an operand that provides a relative offset 
to the fallback instruction address  if the transactional region could not be successfully executed transactionally. 
Software using these instructions to implement lock elisio n must test the lock within the transactional region, and 
only if free should try to commit. Further, the software may also define a policy to retry if the lock is not free.
A processor may abort transactional execution for many reasons. The hardware automatically detects transactional 
abort conditions and restarts execution from the fallback instruction address with the architectural state corre-
sponding to that at the start of the XBEGIN instruction and the EAX register updated to describe the abort status. 
The XABORT instruction allows progra mmers to abort the execution of a transactional region explicitly. The 
XABORT instruction takes an 8 bit immedi ate argument that is loaded into the EAX register and will thus be avail-
able to software following a transactional abort.
Hardware provides no guarantees as to whether a transa ctional execution will ever successfully commit. Program-
mers must always provide an alternative code sequence in the fallback path to guarantee forward progress. When 
using the instructions for lock elision, this may be as si mple as acquiring a lock and executing the specified code 
region non-transactionally. Further, a transactional region that always aborts on a given implementation may 
complete transactionally on a future implementation. Ther efore, programmers must ensure the code paths for the 
transactional region and the alternative code sequence are functionally tested.
If the RTM software interface is used for anything other than lock elision, the programmer must similarly ensure 
that the fallback path is inter-operable with the transactionally executing path.
16.3 INTEL® TSX APPLICATION PROGRAMMING MODEL

16.3.1 Detection of Transactio nal Synchronization Support
16.3.1.1  Detect ion of HLE Support
A processor supports HLE execution if CPUID.07H.EBX.HLE [bit 4] = 1. However, an application can use the HLE 
prefixes (XACQUIRE and XRELEASE) without checking wh ether the processor supports HLE. Processors without 
HLE support ignore these prefixes and will execute the code without entering transactional execution.
16.3.1.2  Detection of RTM Support
A processor supports RTM execution if CPUID.07H.EBX.RTM [b it 11] = 1. An application must check if the processor 
supports RTM before it uses the RTM instructions (XBEGIN,  XEND, and XABORT). These in structions will generate 
a #UD exception when used on a processor that does not support RTM.16-4 Vol. 1PROGRAMMING WITH INTEL® TRANSACT IONAL SYNCHRONIZ ATION EXTENSIONS
16.3.1.3  Detection of XTEST Instruction
A processor supports the XTEST instruction if it supports ei ther HLE or RTM. An application must check either of 
these feature flags before using the XTEST instruction. Th is instruction will generate a #UD exception when used 
on a processor that does not support either HLE or RTM.
16.3.1.4  Detection of  Intel® TSX Suspend Load Address Tracking
A processor supports Intel TSX suspend/resume of load address tracking if CPUID.07H.EDX.TSXLDTRK [bit 16] = 
1. An application must check if the processor supports Inte l TSX suspend/resume of load address tracking before it 
uses the Intel TSX suspend/resume load address trac king instructions (XSUSLDTRK and XRESLDTRK). These 
instructions will generate a #UD exception when used on a processor that does not support Intel TSX suspend/resume load address tracking.
16.3.2 Querying Transactional Execution Status
The XTEST instruction can be used to determine the transact ional status of a transactio nal region specified by HLE 
or RTM. Note, while the HLE prefixes are ignored on proce ssors that do not support HLE, the XTEST instruction will 
generate a #UD exception when used on proce ssors that do not support either HLE or RTM.
16.3.3 Requirements for HLE Locks
For HLE execution to successfully commit transactionally, th e lock must satisfy certain properties and access to the 
lock must follow certain guidelines. 
•An XRELEASE prefixed instruction must restore the value of  the elided lock to the value it had before the lock 
acquisition. This allows hardware to safely elide locks by not adding them to the write-set. The data size and 
data address of the lock release (XRELEASE prefixed ) instruction must match that of the lock acquire 
(XACQUIRE prefixed) and the lock mu st not cross a cache line boundary.
•Software should not write to the elided lock inside a transactional HLE region with any instruction other than an 
XRELEASE prefixed instruction, otherwise it may caus e a transactional abort. In addition, recursive locks 
(where a thread acquires the same lock multiple times without first releasing the lock) may also cause a trans-actional abort. Note that software ca n observe the result of the elided lock acquire inside the critical section. 
Such a read operation will return th e value of the write to the lock.
The processor automatically detects violations to these guidelines, and safely transitions to a non-transactional 
execution without elision. Since Intel TSX detects conflicts at the granularity of a cache line, writes to data collo-
cated on the same cache line as the elided lock may be dete cted as data conflicts by other logical processors eliding 
the same lock.
16.3.4 Transactional Nesting
Both HLE- and RTM-based transactional executions support nested transactional regions. However, a transactional 
abort restores state to the operation that started transact ional execution: either the outermost XACQUIRE prefixed 
HLE eligible instruction or the outermost XBEGIN instructio n. The processor treats all nested transactional regions 
as one monolithic transactional region.
16.3.4.1  HLE Nesting and Elision
Programmers can nest HLE regions up to an implementati on specific depth of MAX_HL E_NEST_COUNT. Each logical 
processor tracks the nesting count internally but this count is not available to software. An XACQUIRE prefixed HLE-eligible instruction increments the nesting count, and an XR ELEASE prefixed HLE-eligible  instruction decrements it. 
The logical processor enters transactional execution when the nesting count goes from zero to one. The logical 
processor attempts to commit only when the nesting count becomes zero. A transactional abort may occur if the nesting count exceeds MAX_HLE_NEST_COUNT.
In addition to supporting nested HLE regions, the proce ssor can also elide multiple nested locks. The processor 
tracks a lock for elision beginning with the XACQUIRE prefix ed HLE eligible instruction for that lock and ending with Vol. 1 16-5PROGRAMMING WITH INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS
the XRELEASE prefixed HLE eligible instruction for that sa me lock. The processor can, at any one time, track up to 
a MAX_HLE_ELIDED_LOCKS number of locks. For example, if the implementation supports a 
MAX_HLE_ELIDED_LOCKS value of two and if the programm er nests three HLE identified critical sections (by 
performing XACQUIRE prefixed HLE eligible instructions on  three distinct locks without performing an intervening 
XRELEASE prefixed HLE eligible instruct ion on any one of the locks), then the first two locks will be elided, but the 
third won't be elided (but will be added to the transaction’s write-set). However, the execution will still continue 
transactionally. Once an XRELEASE for one of the two el ided locks is encountered, a subsequent lock acquired 
through the XACQUIRE prefixed HLE e ligible instruction will be elided.
The processor attempts to commit the HLE execution when all elided XACQUIRE and XRELEASE pairs have been 
matched, the nesting count goes to zero, and the locks have  satisfied the requirements described earlier. If execu-
tion cannot commit atomically, then execution transitions to a non-transactional execution without elision as if the 
first instruction did not have an XACQUIRE prefix.
16.3.4.2  RTM Nesting
Programmers can nest RTM-based transactional regions up to an implementation specific 
MAX_RTM_NEST_COUNT. The logical processor tracks the nestin g count internally but this count is not available to 
software. An XBEGIN instruction increments the nesting co unt, and an XEND instruction decrements it. The logical 
processor attempts to commit only if the nesting count becomes zero. A transactional abort occurs if the nesting count exceeds MAX_RTM_NEST_COUNT.
16.3.4.3  Nesting HLE and RTM
HLE and RTM provide two alternative software interfaces to a common transactional execution capability. The behavior when HLE and RTM are nested together—HLE insi de RTM or RTM inside HLE—is implementation specific. 
However, in all cases, the implementation will maintain HLE and RTM semantics. An implementation may choose to 
ignore HLE hints when used inside RTM regions, and may cause a transactional abort when RTM instructions are used inside HLE regions. In the latter case, the transition  from transactional to non-transactional execution occurs 
seamlessly since the processor will re-execute the HLE region without actually doing elision, and then execute the 
RTM instructions. 
16.3.5 RTM Abort Status Definition
RTM uses the EAX register to communicate abort status to  software. Following an RTM abort the EAX register has 
the following definition.
The EAX abort status for RTM only provides causes for abor ts. It does not by itself encode whether an abort or 
commit occurred for the RTM region. The value of EAX ca n be 0 following an RTM abort. For example, a CPUID Table 16-1.  RTM Abort Status Definition
EAX Register Bit 
PositionMeaning
0 Set if abort caused by XABORT instruction.
1 If set, the transactional execution may succeed on a retry.  This bit is always clear if bit 0 is set.
2 Set if another logical processor conflicted with a memory address that was part of the transactional execution 
that aborted. 
3 Set if an internal buffer to track transactional state overflowed. 4 Set if a debug exception (#DB) or breakpoint exception (#BP) was hit.
5 Set if an abort occurred during execution of a nested transactional execution.
23:6 Reserved.
31:24 XABORT argument (only valid if bit 0 set, otherwise reserved).16-6 Vol. 1PROGRAMMING WITH INTEL® TRANSACT IONAL SYNCHRONIZ ATION EXTENSIONS
instruction when used inside an RTM region causes a transactional abort and may not satisfy the requirements for 
setting any of the EAX bits. This may result in an EAX value of 0.
16.3.6 RTM Memory Ordering
A successful RTM commit causes all memory operations in the RTM region to appear to execute atomically. A 
successfully committed RTM region consisting of an XBEGIN followed by an XEND, even with no memory operations 
in the RTM region, has the same ordering semantics as a LOCK prefixed instruction.

The XBEGIN instruction does not have fencing semantics. However, if an RTM execution aborts, all memory updates 
from within the RTM region are discarded and ne ver made visible to any other logical processor.
16.3.7 RTM-Enabled Debugger Support
Any debug exception (#DB) or breakpoint exception (#BP) in side an RTM region causes a transactional abort and, 
by default, redirects control flow to the fallback instruction address with architectural state recovered and bit 4 in 
EAX set. However, to allow software debuggers to interc ept execution on debug or breakpoint exceptions, the RTM 
architecture provides additional capability called advanced debugging of RTM transactional regions . 
Advanced debugging of RTM transactional regions is enab led if bit 11 of DR7 and bit 15 of the IA32_DEBUGCTL MSR 
are both 1. In this case, any RTM transactional abort due to a #DB or #BP causes execution to roll back to just 
before the XBEGIN instruction (EAX is restored to the value it had before XBEGIN) and then delivers a #DB. (A #DB 
is delivered even if the transactional abort was caused by a #BP.) DR6[16] is cleared to indicate that the exception 
resulted from a debug or breakpoint exception inside an  RTM region. See also Section 18.3.3, “Debug Exceptions, 
Breakpoint Exceptions, and Restricted Tr ansactional Memory (RTM),” of the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3B.
16.3.8 Intel® TSX Suspend/Resume Load Address Tracking Support
Programmers can use Intel TSX suspend/resume of load ad dress tracking to choose which memory accesses do not 
need to be tracked in the Intel TSX read set. A progra mmer who uses the suspend/resume load address tracking 
feature must ensure that there are no atomicity requiremen ts related to the addresses they choose to exclude from 
the read set as hardware will not detect  read-write conflicts for those addresses.
To prevent load addresses from being entered into the read set, the programmer should use the XSUSLDTRK and 
XRESLDTRK instructions. The XSUSLDTRK instruction suspends loads tracking and thus specifies the start of a 
suspend region ; addresses of subsequent loads will not be added to the transaction read set. The XRESLDTRK 
instruction resumes load tracking and thus specifies the end of a suspend region; addresses of subsequent loads 
will be added to the transaction read set. 
The execution of a suspend region is similar to tr ansaction execution with the following exceptions:
•The addresses of loads in a suspend region are not tracke d for read-write conflicts if the addresses are accessed 
inside the suspend region only (they are not added to the transaction read set). The addresses are still tracked 
if they are accessed outside of the suspend region inside the transaction.
•Transaction start/end inside a suspend region is not supported; any execution of XBEGIN or XEND inside a suspend region will cause the transaction to abort.
•There is no support for nesting of suspend regions; ex ecution of XSUSLDTRK in a suspend region will cause a 
transaction to abort.
16.3.9 Programming Considerations
Typical programmer-identified regions are expected to execute transactionally and to commit successfully. 
However, Intel TSX does not provide any such guarantee. A transactional execution may abort for many reasons. 
To take full advantage of the transactional capabilities, programmers should follow cert ain guidelines to increase 
the probability of their transactional execution committing successfully.
This section discusses various events that may cause transactional aborts. The architecture ensures that updates 
performed within a transactional region that subsequent ly aborts execution will never become visible. Only a Vol. 1 16-7PROGRAMMING WITH INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS
committed transactional execution updates architectural stat e. Transactional aborts never cause functional failures 
and only affect performance.
16.3.9.1  Instructio n Based Considerations
Programmers can use any instruction safely inside a transactional region. Further, programmers can use the Intel 
TSX instructions and prefixes at any privilege level. Howe ver, some instructions will always abort the transactional 
execution and cause execution to seamlessly and safely transition to a non-transactional path. 
Intel TSX allows for most common instructions to be used inside transactional regions without causing aborts. The 
following operations inside a transactional region do not typically cause an abort.
•Operations on the instruction pointer register, general purpose registers (GPRs) and the status flags (CF, OF, SF, 
PF, AF, and ZF).
•Operations on XMM and YMM re gisters and the MXCSR register
However, programmers must be careful when intermixing SSE and AVX operations inside a transactional region. 
Intermixing SSE instructions accessing XMM registers an d AVX instructions accessing YMM registers may cause 
transactional regions to abort. 
CLD and STD instructions when used inside transactional re gions may cause aborts if they change the value of the 
DF flag. However, if DF is 1, the STD instruction will not ca use an abort. Similarly, if DF is 0, the CLD instruction will 
not cause an abort.
Instructions not enumerated here as causing abort when used inside a transactional region will typically not cause 
the execution to abort (examples include but are not lim ited to MFENCE, LFENCE, SFENCE, RDTSC, RDTSCP, etc.).
The following instructions will abort transactional execution on any implementation:
•XABORT
•CPUID
•PAUSE
•ENCLS
•ENCLU
In addition, in some implementations, the following in structions may always cause transactional aborts. These 
instructions are not expected to be commonly used inside typical transactional regions. However, programmers 
must not rely on these instructions to force a transactional abort, since whether they cause transactional aborts is 
•Operations on X87 and MMX architecture state. This includes all MMX and X87 instructions, including the 
FXRSTOR and FXSAVE instructions.
•Update to non-status portion of EFLAGS or to UIF: CLI, CLUI, STI, STUI, POPFD, POPFQ, CLAC, and STAC.
•Instructions that update segment registers, debug registers and/or control registers: MOV to 
DS/ES/FS/GS/SS, POP DS/ES/FS/GS/SS, LDS, LES, LFS, LGS, LSS, SWAPGS, WRFSBASE, WRGSBASE, LGDT, 
SGDT, LIDT, SIDT, LLDT, SLDT, LTR, STR, Far CALL, Far JMP, Far RET, IRET, MOV to DRx, MOV to CR0/CR2/CR3/CR4/CR8, CLTS, and LMSW.
•Ring transitions: SYSENTER, SYSCALL, SYSEXIT, and SYSRET.
•TLB and Cacheability control: CLFL USH, CLFLUSHOPT, CLWB, INVD, WBINVD, INVLPG, INVPCID, and memory 
instructions with a non-temporal hint (V/MOVNTDQ A, V/MOVNTDQ, V/MOVNTI, V/MOVNTPD, V/MOVNTPS, 
V/MOVNTQ, V/MASKMOVQ, and V/MASKMOVDQU).
•Extended state management: XRSTOR, XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and XSETBV.
•Interrupts: INT n, INTO, INT3, and INT1.
•I/O: IN, INS, REP INS, OUT, OUTS, REP OUTS and their variants.
•VMX: VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, 
VMXON, INVEPT, INVVPID, and VMFUNC.
•SMX: GETSEC.
•UD0, UD1, UD2, RSM, RDMSR, WRMSR, WRPK RU, HLT, MONITOR, MWAIT, and VZEROUPPER.16-8 Vol. 1PROGRAMMING WITH INTEL® TRANSACT IONAL SYNCHRONIZ ATION EXTENSIONS
16.3.9.2  Runtime Considerations
In addition to the instruction-based considerations, runtime events may cause transactional execution to abort. 
These may be due to data access patterns or micro-archit ectural implementation causes. Keep in mind that the 
following list is not a comprehensive discussion of all abort causes. 
Any fault or trap in a transactional region that must be  exposed to software will be suppressed. Transactional 
execution will abort and execution will transition to a non-transactional execution, as if the fault or trap had never occurred. If any exception is not masked, that will result in a transactional abort and it will be as if the exception 
had never occurred.
When executed in VMX non-root operation, certain instructions may result in a VM exit. When such instructions are 
executed inside a transactional region, then instead of ca using a VM exit, they will cause a transactional abort and 
the execution will appear as if instruction that would have caused a VM exit never executed.
Synchronous exception events (#DE, #OF, #NP, #SS, #GP, #BR, #UD, #AC, #XM, #PF, #NM, #TS, #MF, #DB, 
#BP/INT3) that occur during transactional execution may cause an execution not to commit transactionally, and 
require a non-transactional execution. These events are su ppressed as if they had never occurred. With HLE, since 
the non-transactional code path is identical to the transa ctional code path, these events will typically re-appear 
when the instruction that caused the exception is re-executed non-transactionally, causing the associated synchro-
nous events to be delivered appropriately in the non-transactional execution. The same behavior also applies to

nous events to be delivered appropriately in the non-transactional execution. The same behavior also applies to 
synchronous events (EPT violations, EPT misconfiguratio ns, and accesses to the APIC-access page) that occur in 
VMX non-root operation.
Asynchronous events (NMI, SMI, INTR, IPI, PMI, etc.) occurring during transactional execution may cause the 
transactional execution to abort and transition to a non-transactional execution. The asynchronous events will be 
pended and handled after the transactional abort is proce ssed. The same behavior also applies to asynchronous 
events (VMX-preemption timer expiry, virtual-interrupt delivery, and interrupt-window exiting) that occur in VMX non-root operation.
Transactional execution only supports write-back cachea ble memory type operations. A transactional region may 
always abort if it includes operations on any other memo ry type. This includes instruction fetches to UC memory 
type.
Memory accesses within a transactional region may require the processor to set the Accessed and Dirty flags of the 
referenced page table entry. The behavior of how the processor handles this is implementation specific. Some 
implementations may allow the updates to these flags to beco me externally visible even if the transactional region 
subsequently aborts. Some Intel TSX implementations ma y choose to abort the transactional execution if these 
flags need to be updated. Further, a processor's page-table walk may generate accesses to its own transactionally 
written but uncommitted state. Some Intel TSX implementations may choose to abort the execution of a transac-
tional region in such situations. Regardless, the architectu re ensures that, if the transactional region aborts, then 
the transactionally written state will not be made architecturally visible through the behavior of structures such as 
TLBs.
Executing self-modifying code transactionally may also cause transactional aborts. Programmers must continue to 
follow the Intel recommended guidelines for writing self-modifying and cross- modifying code even  when employing 
Intel TSX.
While an Intel TSX implementation will typically provide sufficient resources for executing common transactional 
regions, implementation constraints and excessive sizes for transactional regions may cause a transactional execu-
tion to abort and transition to a non-transactional executio n. The architecture provides no guarantee of the amount 
of resources available to do transactional execution and do es not guarantee that a transactional execution will ever 
succeed.
Conflicting requests to a cache line accessed within a transactional region may prevent the transactional region 
from executing successfully. For example, if logical processor P0 reads line A in a transactional region and another logical processor P1 writes A (either inside or outside a tr ansactional region) then logical processor P0 may abort if 
logical processor P1’s write interferes with processor P0's ability to execute transactionally. Similarly, if P0 writes 
line A in a transactional region and P1 reads or writes A (either inside or outside a transactional region), then P0 
may abort if P1's access to A interferes with P0's abilit y to execute transactionally. In addition, other coherence 
traffic may at times appear as conflicting requests and may cause aborts. While these false conflicts may happen, 
they are expected to be uncommon. The conflict resolution  policy to determine whether P0 or P1 aborts in the 
above scenarios is implementation specific.Vol. 1 17-1CHAPTER 17
17.1 INTRODUCTION
Return-oriented programming (ROP), and similarly CALL /JMP-oriented programming (COP/JOP), have been the 
prevalent attack methodologies for stealth exploit writers targeting vulnerabilities in programs. These attack meth-odologies have the common elements:
•A code module with execution privilege and contain small snippets of code sequence with the characteristic: at 
least one instruction in the sequence being a control transfer instruction that depends on data either in the 
return stack or in a register for the target address.
•Diverting the control flow instruction (e.g., RET, CALL, JMP)  from its original target address to a new target (via 
modification in the data stack or in the register).
Control-Flow Enforcement Technology (CET) provides the following capabilities to defend against ROP/COP/JOP 
style control-flow subversion attacks:
•Shadow stack: Return address protection to defend against ROP.
•Indirect branch tracking: Free branch protection to defend against COP/JOP.
Both capabilities introduce new instruction se t extensions, and are described in the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D.
Control-Flow Enforcement Technology introduces a new exception (#CP) with interrupt vector 21.
17.1.1 Shadow Stack
A shadow stack is a second stack for the program that is used exclusively for control transfer operations. This stack 
is separate from the data stack and can be enabled for op eration individually in user mode or supervisor mode. 
When shadow stacks are enabled, the CALL instruction pushes the return address on both the data and shadow 
stack. The RET instruction pops the return address from both stacks and compares th em. If the return addresses 
from the two stacks do not match, the processor signal s a control protection exception (#CP). Note that the 
shadow stack only holds the return addresses and not parameters passed to the call instruction.
The shadow stack is protected from tamper through the page table protections such that regular store instructions 
cannot modify the contents of the shadow stack. To provid e this protection the page table protections are extended 
to support an additional attribute for pages to mark th em as “Shadow Stack” pages. When shadow stacks are 
enabled, control transfer instructions/flows like near call,  far call, call to interrupt/exception handlers, etc. store 
return addresses to the shadow stack and the access will fa ult if the underlying page is not marked as a “Shadow 
Stack” page. However stores from instructions like MOV, XSAV E, etc. will not be allowed. Likewise control transfer 
instructions like near RET, far RET, IR ET, etc. when they attempt to read from the shadow stack the access will fault 
if the underlying page is not marked as a “Shadow Stack” page. This paging protection detects and prevents condi-
tions that cause an overflow or underflow of the shadow stack when the shadow stack is delimited by non-shadow 
stack guard pages, or any malicious attempts to redirect the processor to consume data from addresses that are 
not shadow stack addresses.
17.1.2 Indirect Branch Tracking
The ENDBRANCH instruction is a new instruction that is used  to mark valid jump target addresses of indirect calls 
and jumps in the program. This instruction opcode is selected  to be one that is a NOP on legacy machines such that 
programs compiled with ENDBRANCH new instruction cont inue to function on old machines without the CET 
enforcement. On processors that support CET the ENDBRA NCH is still a NOP and is primarily used as a marker 
instruction by the processor pipeline to detect control flow violations. The CPU implements a state machine that 
tracks indirect JMP and CALL instructions. When one of these instructions is executed, the state machine moves 
from IDLE to WAIT_FOR_ENDBRANCH st ate. In WAIT_FOR_ENDBRANCH state the next instruction in the program 17-2 Vol. 1CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
stream must be an ENDBRANCH. If the next instructio n is not an ENDBRANCH, the processor causes a control 
protection exception (#CP); otherwise, the state machine moves back to IDLE state.
17.1.3 Speculative Behavior when CET is Enabled
Speculative execution of near indirect JMP/CALL/RET indirect branches may be able to create an active side channel 
vulnerability that reveals the contents of data.
There are two basic methods that an attacker may be able to  use to control indirect branch speculation in order to 
speculatively execute code that causes a side channel:
1. Attacker controlled prediction.
2. Attacker controlled jump redirection.
With attacker controlled prediction, the attacker trains indirect branch predictors such that the desired victim indi-
rect branch goes to the attacker desired location. Examples include Branch Target Injection (also called “Variant 2” 
and “Spectre”) and RSB wrap on underflow (also called “ret2spec”).
With attacker controlled jump redirection, the attacker controls a speculative-only value used as input to the indi-
rect branch so that the branch mispredicts to the attack er desired location. Examples of this include Bound Check 
Bypass Store (where a speculative store containing an attacker controlled value may overwrite the indirect branch target before the load of the target) and Speculative Stor e Bypass (where a load of the indirect branch target may

Bypass Store (where a speculative store containing an attacker controlled value may overwrite the indirect branch target before the load of the target) and Speculative Stor e Bypass (where a load of the indirect branch target may 
bypass the most recent store of the target value and thus speculatively read an older attacker controlled value at 
the same memory location).
In addition to the existing mitigation features like IB RS, STIBP, and IBPB, processors supporting CET will have a 
variety of additional features to constrain control flow spec ulation in order to mitigate such attacks. For details on 
these features, see Section 17.2.6, “Constraining Executio n at Targets of RET,” and Section 17.3.8, “Constraining 
Speculation after Missing ENDBRANCH.”
17.2 SHADOW STACKS
A shadow stack is a second expand down stack used exclus ively for control transfer operations. This stack is sepa-
rate from the data stack. The shadow stack is not used to  store data and hence is not explicitly writeable by soft-
ware. Writes to the shadow stack are restricted to cont rol transfer instructions and shadow stack management 
instructions. The shadow stack feature can be enabled sepa rately in user mode (CPL == 3) or supervisor mode 
(CPL < 3).
Shadow stacks operate only in protected mode. Shad ow stacks cannot be enabled in virtual 8086 mode.
It is recommended to not configure the shadow stack in the linear address range 0 to 64 KB or adjacent to the 
canonical address boundary.
17.2.1 Shadow Stack Pointer and its Operand and Address Size Attributes
When CET is enabled the processor supports a new archit ectural register, shadow stack pointer (SSP), when the 
processor supports the shadow stack feature. The SSP cann ot be directly encoded as a source, destination or 
memory operand in instructions. The SSP points to the current top of the shadow stack.
The width of the shadow stack is 32-bit in 32-bit/compatib ility mode and is 64-bit in 64-bit mode. The address-size 
attribute of the shadow stack is likewise 32-bit in 32-bit/compatibility mode and 64-bit in 64-bit mode.
17.2.2 Terminology
When shadow stacks are enabled, ce rtain control transfer instructions/flows and shadow stack management 
instructions do loads and stores from and to the shadow st ack. Such loads and stores from control transfer instruc-
tions and shadow stack management instructions are termed as shadow-stack loads  and shadow-stack stores  
to distinguish them from a loads and stores performed by other instructions like MOV, XSAVES, etc.Vol. 1 17-3CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
The pseudocode for the instruction operations use the no tation ShadowStackEnabled(CPL) as a test of whether 
shadow stacks are enabled at the CPL. This term returns a TRUE or FALSE indication as follows.
ShadowStackEnabled(CPL):
IF CR4.CET = 1 AND CR0.PE = 1 AND EFLAGS.VM = 0
IF CPL = 3
THEN
(* Obtain the shadow stack enable from IA32 _U_CET MSR (MSR address 6A0H) used to enable
 feature for CPL = 3 *)SHADOW_STACK_ENABLED = IA32_U_CET.SH_STK_EN;
ELSE
(* Obtain the shadow stack enable from IA32 _S_CET MSR (MSR address 6A2H) used to enable
 feature for CPL < 3 *)SHADOW_STACK_ENABLED = IA32_S_CET.SH_STK_EN;
FI;IF SHADOW_STACK_ENABLED = 1
THEN
ELSE
FI;
ELSE
(* Shadow stacks not enabled in real mode and virtual-8086 mode or if the master CET featureenable in CR4 is disabled *)
ENDIF
Additionally, the following terms are used.
•ShadowStackPush4B: Decrements the shadow stack poin ter (SSP) by 4 bytes and copies the 4 byte source 
operand to the top of the shadow stack.
•ShadowStackPush8B : Decrements the shadow stack poin ter (SSP) by 8 bytes and copies the 8 byte source 
•ShadowStackPop4B: Copies 4 bytes at the current top of stack (indicated by the SSP register) to the location 
specified with the destination operand. It then incremen ts the SSP register by 4 bytes to point to the new top 
of stack.
•ShadowStackPop8B: Copies 8 bytes at the current top of stack (indicated by the SSP register) to the location 
specified with the destination operand. It then incremen ts the SSP register by 8 bytes to point to the new top 
of stack.
•shadow_stack_lock_cmpxchg8B(address,  new_value, expected_value): this function executes atomically and 
compares the expected_value to the 8 byte read from memory specified by the address operand using a locked 
shadow-stack load. If the two values are equal, the ne w_value is written to the address using an unlocking 
shadow-stack store. If the two values are not equal, th en the value read by the shadow-stack load is written 
back, also using an unlocking shadow-stack store. Th e function returns the value read from the memory 
specified by the address operand.
17.2.3 Supervisor Shadow Stack Token
On an inter-privilege far CALL  or when calling an interrupt/exception handler at a higher privilege level, a stack 
switch occurs; if shadow stacks are enabled at the new pr ivilege level, then a shadow stack switch occurs. Shadow 
stacks that can be switched to by hardware as part of a privilege change are required to have a supervisor shadow 
stack token set up by the supervisor to provide the addr ess of the new SSP register. The supervisor shadow stack 
tokens also serve the purpose of enforcing that a shadow stack can be made active on only one logical processor 
when switched to by the processor. The supervisor shad ow stack token must be set up only on shadow stacks 
intended to be used on these transfers. The address of the supervisor shadow stack token is programmed into the 17-4 Vol. 1CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
IA32_PLx_SSP MSR (where 0 ≤ x ≤ 2). The WRMSR and XRSTORS instructions require the address specified in the 
IA32_PLx_SSP MSR (where 0 ≤ x ≤ 2) to be 4 byte aligned; otherwise, th e instruction causes a general protection 
exception (#GP(0)).
The supervisor shadow stack token is a 64-bit value formulated as follows.
•Bit 63:3: Bits 63:3 of the linear address of the supervisor shadow stack token.
•Bit 2: Reserved. Must be zero.
•Bit 1: Reserved. Must be zero.
•Bit 0: Busy bit. If 0, indicates this shadow stack is not ac tive on any logical processor. If 1, indicates this shadow 
stack is currently active on one of the logical processors.
The following figure illustrates a supervis or shadow stack with a supervisor sh adow stack token located at its base.
If the far CALL or event delivery will push a 24-byte stac k frame after the token is acquired, the 8-byte supervisor 
shadow stack token and the stack frame must be fully contai ned within a 32-byte region that is aligned to 32-bytes 
on the shadow stack. If they are not, a general-protection exception (#GP(0)) occurs.
The processor does the following checks prior to switch ing to a supervisor shadow stack programmed into the 
IA32_PLx_SSP MSR. These steps are performed atomically.
1. Load the supervisor shadow stack token from the addr ess specified in the IA32_P Lx_SSP MSR using a locked 
shadow-stack store.
2. Check if the busy bit in the token is 0; reserved bits must be 0.
3. Check if the address programmed in the MSR matches the address in the supervisor shadow stack token; 
reserved bits must be 0.
4. If checks 2 and 3 are successful, then set the busy bit in the token using an unlocking shadow-stack store and 
switching the SSP to the value sp ecified in the IA32_PLx_SSP MSR.
5. If checks 2 or 3 fail, write back the value read at step  1 using an unlocking shadow-stack store (the busy bit is 
not set) and raise a #GP(0) exception.
If the far CALL or event delivery pushes a stack frame afte r the token is acquired and any of the pushes causes a 
fault or VM exit, the processor will revert to the old shad ow stack and the busy bit in the new shadow stack's token 
remains set. The new shadow stack is said to be prematurely busy . Software should enable supervisor shadow 
stacks only if it is certain that this situation cannot occur. If CPUID.(EAX=07H,ECX=1 H):EDX[bit 18] is enumerated 
as 1, it is sufficient for an operating system to ensure that none of the pushes can cause a page fault.
On a far RET to a lesser privilege level or on an IRET that switches shadow stack, the instruction clears the busy bit 
in the shadow stack token as follows. Th ese steps are also performed atomically.
1. Load the supervisor shadow stack token from the SSP using a locked shadow-stack load.
2. Check if the busy bit in the token is 1; reserved bits must be 0.Figure 17-1.  Supervisor Shadow Stack with a Supervisor Shadow Stack Token0xFF8 | busy<Next push saves here>
IA32_PLx_SSP = 0xFF8Vol. 1 17-5CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
3. Check if the address programmed in  supervisor shadow stack token matches SSP; reserved bits must be 0.
4. If checks 2 and 3 are successful, then write back the to ken with an unlocking shadow-stack store, clearing the 
busy bit; otherwise, write back the value read at step  1 using an unlocking shadow-stack store and continue 
without modifying the contents of the shadow stack pointed to by SSP.
17.2.4 Shadow Stack Usage on Task Switch
A task switch (see Chapter 8, “Task Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A) may be invoked by:

•JMP or CALL instruction to a TSS descriptor in the GDT.
•JMP or CALL instruction to a task-gate descriptor in the GDT or the current LDT.
•An interrupt or exception vector points to a task-gate descriptor in the IDT.
With shadow stack enabled, the new task must be associated with a 32-bit TSS and must not be in virtual-8086 
mode. The 32-bit SSP for the new task is located at offset 104 in the 32-bit TSS. Thus the TSS of the new task must 
be at least 108 bytes. This SSP is required to be 8 byte  aligned, and required to point to a “supervisor shadow 
stack” token (though the task may be at CPL3).
On a task switch initiated by a CALL instruction, an interru pt, or exception, the SSP of the old task is pushed onto 
the shadow stack of the new task along with the CS and LI P of the old task. This is true even for a nested task 
switch initiated by a CALL instruction. Likewise, on a ta sk switch initiated by IRET, the SSP of the new task is 
restored from the shadow stack of old task. The CS an d LIP on the shadow stack of the old task are matched 
against the return address determined by the CS and EIP of the new task. If the match fails, a #CP(FAR-RET/IRET) 
exception is reported.
17.2.5 Switching Shadow Stacks
The architecture provides a mechanism to switch shadow stacks using a pair of instructions; RSTORSSP and SAVE-
PREVSSP. The RSTORSSP instruction verifies a shadow-stack-restore token located at the top of the new shadow stack and referenced by the memory operand of this inst ruction. After RSTORSSP determines the validity of the 
restore point on the new shadow stack, it switches the SSP to point to the token. The shadow-stack-restore token 
is a 64-bit value formatted as follows.
•Bit 63:2: Value of shadow stack pointer when this restore point was created.
•Bit 0: Mode bit. If 0, the token is a compatibility/lega cy mode shadow-stack-restore token. If 1, then this 
shadow stack restore token can be used with a RSTORSSP instruction in 64-bit mode.
The shadow-stack-restore token is created by the SAVEPREVSSP instruction. The operating system may also 
create a restore point on a shadow stack by creating a shadow-stack-restore token.
Once the shadow stack has been switched to a new shad ow stack by the RSTORSSP instruction, software can 
create a restore point on the old shadow stack by executing the SAVEPREVSSP instruction. In order to allow the 
SAVEPREVSSP instruction to determine the address where to  save the shadow-stack-restore token, the RSTORSSP 
instruction replaces the shadow-stack-restore token with a previous-ssp token that holds the value of the SSP at the time the RSTORSSP instruction was invoked. The previous-ssp token is formatted as follows.
•Bit 63:2: Shadow stack pointer when the RSTORSSP inst ruction was invoked, i.e., the SSP of the old shadow 
stack.
•Bit 1: Set to 1.
•Bit 0: Mode bit. If 0, then this previous-ssp token can be used with a SAVEPREVSSP instruction in compati-
bility/legacy mode. If 1, then this previous-ssp token can be used with a SAVEPREVSSP instruction in 64-bit 
mode.
The following figure illustrates the RSTORSSP instructio n operation during a shadow stack switching sequence.17-6 Vol. 1CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
In this example, the initial SSP is 1000H and the shadow-s tack-restore token is on a new shadow stack at address 
3FF8H. The token at address 3FF8H holds the SSP when this restore point was created; in this example it is 4000H.
In order to switch to the new shadow stack, the RSTORSSP instruction is invoked with the memory operand 
pointing set to 3FF8H. When the RSTORSSP instruction co mpletes, the SSP is set to 3FF8H and the shadow-stack-
restore token at 3FF8H is replaced by a previous-ssp token that holds the address 1000H, i.e., the old SSP.
The following figure illustrates the SAVEPREVSSP instruct ion operation during a shadow stack switching sequence.
To allow switching back to this old shadow stack, a SAVEPREVSSP instruction is now invoked. The SAVEPREVSSP 
instruction does not take any memory operand and expects to find a previous-ssp token at the top of the shadow 
stack, i.e., at address 3FF8H. The SAVEPREVSSP instruction then saves a shadow-stack-restore token on the old 
shadow stack at address FF8H, and the token itself holds the address 1000H which is the address recorded in the 
previous-ssp token. The SAVEPREVSSP instruction also po ps the previous-ssp token off the current shadow stack 
and thus the SSP following SAVEPREVSSP is 4000H.
Subsequently to switch back to the old shadow stack,  a RSTORSSP instruction may be invoked with memory 
operand set to FF8H.
If, following a switch to a new shadow stack, it is not re quired to create a restore point on the old shadow stack, 
then the previous-ssp token created by the RSTORSSP inst ruction can be popped off the shadow stack by using the 
INCSSP instruction.
See the SAVEPREVSSP and RSTORSSP instruct ion operations for the detailed algorithm.Figure 17-2.  RSTORSSP to Switch to New Shadow Stack
Figure 17-3.  SAVEPREVSSP to Save a Restore PointCurrent 
Current active shadow stackFF8H
1000HNew Shadow 
Stack to switch 
to
4000H
Shadow stack to switch to3FF8H
4000H0M
SSPNew Shadow 
Stack
1000H
State following successful 
RSTORSSP1M SSP
3FF8H
4000HNew Shadow 
Stack
1000H
Current active shadow stack 
with a “previous SSP” token1M SSPNew Shadow 
Stack
1000H
with a “previous SSP” token 
popped off3FF8H
4000H SSP1MPrevious 
1000H
“shadow stack restore” token 
pushed on previous shadow 
stack following 
SAVEPREVSSP0MVol. 1 17-7CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
17.2.6 Constraining Execution at Targets of RET
Instructions at the target of a RET instruction will not execute, even speculatively, if the RET addresses (either from 
normal stack or shadow stack) are speculative-only or do not match, unless the target of the RET is also predicted 
(e.g., by a Return Stack Buffer prediction), when CET shadow stack is enabled. A RET address would be specula-
tive-only if it was modified by an older speculative-only store, or was an older value than the most recent value 
stored to that address on the logical processor.
17.3 INDIRECT BRANCH TRACKING
When the indirect branch tracking feature is active, the indirect JMP/CALL instruction behavior changes as follows.
•JMP: If the next instruction retired after an indirect JMP is not an ENDBR32 instruction in legacy and compati-
bility mode, or ENDBR64 instruction in 64-bit mode, then a #CP fault is generated. Below JMP instructions are 
tracked to enforce an ENDBRANCH. Note that Jcc, RIP relative, and far direct JMP are not included as these 
have an offset encoded into the instruction and are not exploitable to create unintended control transfers.
— JMP r/m16, JMP r/m32, JMP r/m64— JMP m16:16, JMP m16:32, JMP m16:64
•CALL: If the next instruction retired after an indirect CA LL is not an ENDBR32 instruction in legacy and compat-
ibility mode, or ENDBR64 in 64-bit mode, then a #CP fault is generated. Below CALL instructions are tracked to 
enforce an ENDBRANCH. Note that rela tive and zero displacement forms of CALL instructions are not included 
as these have an offset encoded into the instruction and are not exploitable to create unintended control 
— CALL r/m16, CALL r/m32, CALL r/m64— CALL m16:16, CALL m16:32, CALL m16:64
The ENDBR32 and ENDBR64 instructions will have the same effect as the NOP instruction on Intel 64 processors 
that do not support CET. On processors supporting CET, thes e instructions do not change register or flag state. This 
allows CET instrumented programs to execute on processors that do not support CET. Even when CET is supported and enabled, these NOP-like instructions do not affect th e execution state of the program, do not cause any addi-
tional register pressure, and ar e minimally intrusive from power and performance perspectives.
The processor implements two dual-state machines to trac k indirect CALL/JMP for terminations. One state machine 
is maintained for user mode and one for supervisor mode . At reset the user and supervisor mode state machines 
are in IDLE state.
On instructions other than indirect CALL/JMP, the state machine stays in the IDLE state.
On an indirect CALL or JMP instruction, the state machine transitions to the WAIT_FOR_ENDBRANCH state.
In the WAIT_FOR_ENDBRANCH state, the indirect branch trac king state machine verifies the next instruction is an 
ENDBR32 instruction in legacy and compatibility mode, or ENDBR64 instruction in 64-bit mode, and either:
•Causes a #CP fault, or
•Allows the next instruction if legacy compatib ility configuration allows (see Section 17.3.6).
The priority of the #CP(ENDBRANCH) exceptio n relative to other events is as follows.17-8 Vol. 1CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
Higher priority faults/traps/events that occur at the en d of an indirect CALL/JMP are delivered ahead of any

Higher priority faults/traps/events that occur at the en d of an indirect CALL/JMP are delivered ahead of any 
#CP(ENDBRANCH) fault. The CET state machine at the priv ilege level where the higher priority fault/trap/event 
occurred retains its state when the control transfers to the fault/trap/event handler. The instruction pointer pushed 
on the stack for a #CP(ENDBRANCH) fault is the address of the instruction at the target of the indirect CALL/JMP 
that caused the fault.
17.3.1 No-track Prefix for Near Indirect CALL/JMP
CET allows software to designate certain indirect CALL and JMP instructions as “non-tracked indirect control 
transfer instructions”. Software (e.g., compiler generated code for switch statements, jump tables, etc.) should use 
the no-track prefix only if they have generated code to validate the possible targets of  this CALL/JMP to be legal 
targets. Software (e.g., compilers), when using the no-track prefix with CALL/JMP where an absolute offset is spec-ified indirectly in a memory location, should ensure that such memory locations cannot be tampered. When 
enabled by setting the NO_TRACK_EN control in the IA3 2_U_CET/IA32_S_CET MSR, near  indirect CALL and JMP 
instructions when prefixed with 3EH do not modify the CE T indirect branch tracker. Far CALL and JMP instructions 
are always tracked and ignore the 3EH prefix. When this co ntrol is 0, near indirect CALL and JMP instructions are 
always tracked irrespective of the presence of the 3EH prefix.
In 64-bit mode, the 3EH prefix on an indirect CALL or JMP is recognized as a no-track prefix if there isn’t a 64H/65H 
prefix on the instruction.
In legacy/compatibility mode, th e 3EH prefix on an indirect CALL or JMP is recognized as a no-track prefix when it 
is the last group 2 prefix on the instruction.Figure 17-4.  Priority of Control Prot ection Exception on Missing ENDBRANCHIndirect CALL/JMP, RET
TSS Trap / PEBS / BTS / VAPIC TrapRESET / #MC
NMISIPI / STOPCLK / LTCYC / SMI / INIT
Hardware Interrupts / Probe
Code Breakpoint
CS Limit Violation / Code Page Fault
#UD / #NM (Decode Faults)Target Instruction#CP FaultVol. 1 17-9CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
17.3.2 Terminology
The pseudocode for the instruction operations use a notati on EndbranchEnabled(CPL) as a test of whether indirect 
branch tracking is enabled at the CPL. This term returns a TRUE or FALSE indication as follows.
EndbranchEnabled(CPL):
IF CPL = 3
THEN
(* Obtain the ENDBRANCH enable from MSR used to enable feature for CPL = 3 *)ENDBR_ENABLED = IA32_U_CET.ENDBR_EN;
ELSE
(* Obtain the ENDBRANCH enable from MSR used to enable feature for CPL < 3 *)ENDBR_ENABLED = IA 32_S_CET.ENDBR_EN;
FI;IF ENDBR_ENABLED = 1
THEN
ELSE
FI;
ELSE
(* Indirect branch tracking is not enabled in real mo de and virtual-8086 mode or if the master CET feature
 enable in CR4 is disabled *)
ENDIF
Likewise the notation EndbranchEnabled AndNotSuppressed is defined as follows:
EndbranchEnabledAndNotSuppressed(CPL):
IF CPL = 3
THEN
(* Obtain the ENDBRANCH enable from MSR used to enable feature for CPL = 3 *)ENDBR_ENABLED = IA32_U_CET.ENDBR_EN;SUPPRESSED = IA32_U_CET.SUPPRESS;
ELSE
SUPPRESSED = IA32_S_CET.SUPPRESS;
FI;IF ENDBR_ENABLED = 1 AND SUPPRESSED = 0
THEN
ELSE
FI;
ELSE
ENDIF17-10 Vol. 1CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
17.3.3 Indirect Branch Tracking
The hardware implements two CET indirect branch tracker state machines, one for user mode (CPL == 3) and one 
for supervisor mode (CPL < 3). At any ti me, which of the CET indirect branch trackers is in the active state depends 
on the CPL of the machine. When a user space program is  executing, the CPL 3 CET indirect branch tracker is 
active. When supervisor mode software is executing, th e CPL < 3 tracker is active. This section describes the 
various control transfer conditions and the tracker state on those transfers.
17.3.3.1  Control Transfers between CPL 3 and CPL < 3
Some events and instructions can cause control transfer to occur from CPL 3 to CPL < 3, and vice versa. As part of 
the CPL change the hardware also switches the active CET indirect branch tracker. For example, when an interrupt 
occurs during execution of a user mode (CPL == 3) prog ram and it causes the CPL to switch to supervisor mode 
(CPL < 3) then, as part of the CPL change, the user mo de CET indirect branch tracker becomes inactive and the 
supervisor mode CET indirect branch tracker becomes active. A subsequent IRET is used by the interrupt handler 
to return to the interrupted user mode program. This IR ET causes the processor to switch the CPL to user mode 
(CPL ==3) and, as part of the CPL ch ange, the supervisor mode CET indirect branch tracker becomes inactive and 
the user mode CET indirect branch tracker becomes active.
The CPL where the event or instruction th at caused the control transfer occurs is termed the source CPL, and the 
CET indirect branch tracker state at that CPL is referred he re as the source CET indirect branch tracker state. The 
CPL reached at the end of the control tr ansfer is termed the destination CPL,  and the CET indirect branch tracker 
state at that CPL is referred to as the destination CET indirect branch tracker state.
This section describes various cases of control transfers that occur between user mode (CPL 3) and supervisor 
mode (CPL < 3).
In all these cases the source CET indirect branch tracker state becomes not active and retains its state (IDLE, 
WAIT_FOR_ENDBRANCH), and the target CET indirect branch  tracker state becomes active if there was no fault 
during the transfer.
•Case 1: Far CALL/JMP, SYSCALL/SYSENTER
— If indirect branch tracking is enabled, the target indirect branch tracker state becomes active and is unsup-
pressed and goes to WAIT_FOR_ENDBRANCH. This enforc es that the subroutine invoked by a far CALL/JMP 
must begin with an ENDBRANCH.
•Case 2: Hardware interrupt/trap/exception/NMI/Software interrupt/Machine Checks
pressed and goes to WAIT_FOR_ENDBRANCH.
•Case 3: IRET/Far RET
— If indirect branch tracking enabled, the target indirect  branch tracker becomes active and keeps its state. If 
the user mode was interrupted by a higher priority event, like an interrupt at the end of the indirect CALL/JMP, then when an IRET or Far RET is used to re turn to the interrupted user mode program, the user 
mode indirect branch tracker retains its state and a #CP fault will occur if the next instruction decoded is not 
an ENDBR32/64 according to mode of machine.
17.3.3.2  Control Transfer s within CPL 3 or CPL < 3
Some events and instructions can cause control transfer to  occur within CPL 3 or CPL < 3. For such transfers since 
the CPL class does not change, the same indirect branch tracker is used at the beginning and end of the control 
transfer.
•Case 1: Far CALL/JMP, Near indirect CALL/JMPCALL/JMP
— Far CALL/JMP: If indirect branch tracking is enable d, active indirect branch tracker is unsuppressed and 
goes to WAIT_FOR_ENDBRANCH.
— Near indirect CALL/JMPCALL/JMP: If indirect branch tr acking is enabled and not suppressed, active indirect 
branch tracker goes to WAIT_FOR_ENDBRANCH.
•Case 2: Hardware interrupt/trap/exception/NMI/Software interrupt/Machine ChecksVol. 1 17-11CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
— If indirect branch tracking is enabled, the active indirect branch tracker is unsuppressed and goes to 
WAIT_FOR_ENDBRANCH.
•Case 3: IRET
— If indirect branch tracking is enabled, the active indirect branch tracker keeps its state.
17.3.4 Indirect Branch Tracking State Machine
The state machine is described by Table 17-1.
Table 17-1.  Indirect Bran ch Tracking State Machine
Current State Trigger Next State
TRACKER=IDLE, SUPPRESS=0, 
ENDBR_EN=1Instructions other than indirect CALL/JMP or 
3EH prefixed near in direct CALL/JMP and 
NO_TRACK_EN=1TRACKER=IDLE, SUPPRESS=0, 
ENDBR_EN=1
Indirect CALL/JMP without 3EH prefix
Indirect CALL/JMP with 3EH prefix and 
NO_TRACK_EN=0
Far CALL/JMPTRACKER=WAIT_FOR_ENDBRANCH, SUP-
PRESS=0, ENDBR_EN=1
TRACKER= WAIT_FOR_ENDBRANCH, SUP-
PRESS=0, ENDBR_EN=1INT3/INT1TRACKER= WAIT_FOR_ENDBRANCH, SUP-
ENDBRANCH instructionTRACKER=IDLE, SUPPRESS=0, 
Successful ENCLU[ERESUME]TRACKER=IDLE, SUPPRESS=0, 
Instructions other than ENDBRANCH, suc-
cessful ENCLU[ERESUME] or INT3 or INT1If legacy compatibil ity treatment is not 
enabled or if not allowed by legacy code page bitmap:
• No state change and deliver #CP 
(ENDBRANCH)
If legacy compatib ility treatment is 
enabled and transfer allowed by legacy 
code page bitmap:
• TRACKER=IDLE, 
SUPRESS=!SUPPRESS_DIS, 

TRACKER=x, SUPPRESS=x, ENDBR_EN=0 All inst ructions TRACKER=x, SUPPRESS=x, ENDBR_EN=0
TRACKER=IDLE, SUPPRESS=1, 
ENDBR_EN=1Far CALL/JMP, INTn/INT3/INTOTRACKER=WAIT_FOR_ENDBRANCH, SUP-
ENDBRANCH instruction
All other instructions including indirect 
CALL/JMPTRACKER=IDLE, SUPPRESS=1, 
TRACKER=1, SUPPRESS=1, ENDBR_EN=1
(This state cannot be reached by hardware and is disallowed as a valid state by 
WRMSR/XRSTORS/VM entry/VM exit)NA NA17-12 Vol. 1CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
17.3.5 INT3 Treatment
INT3 are treated special in the WAIT_FOR_ENDBRANCH state.  Occurrence of INT3 do not move the tracker to IDLE 
but instead the #BP trap from the INT3 instructions respectively is delive red as a higher priority event than the #CP 
exception due to missing ENDBRANCH.
Inside an enclave, INT3 delivers a fault-class exception and thus does not require the CPL to be less than DPL in the 
IDT gate 3. Following opt-out entry, the instruction delive rs #UD. Following opt-in entry, INT3 delivers #BP. The 
special treatment of INT3 in WAIT_FOR_ENDBRANCH state does not apply in enclave mode following opt-out entry.
17.3.6 Legacy Compatibility Treatment
ENDBRANCH legacy compatibility treatment allows a CET en abled program to be used with legacy software that 
was not compiled / instrumented with ENDBRANCH. A CET enabled program enters legacy compatibility treatment 
when all of the below conditions are met.
1. Legacy compatibility configuration is enabled in  this CPL class by setti ng the LEG_IW_EN bit in 
IA32_U_CET/IA32_S_CET.
2. Control transfer is performed using an indirect CALL/JMP  without no-track prefix to an instruction other than 
ENDBRANCH.
3. The legacy code page bitmap is setup to indicate that the target of the control transfer is a legacy code page.
The legacy code page bitmap is a data structure in progra m memory that is used by the hardware to determine if 
the code page to which a legacy transfer is being perfor med is allowed. The access rights for accessing the legacy 
code page bitmap is determined by the current privilege le vel (CPL). The legacy code pa ge bitmap is expected to 
be setup as a read-only data structure.
When a matching ENDBRANCH instruction is not decoded at the target of an indirect CALL/JMP when required, the 
processor performs the below actions.
CET indirect branch tracking state machine violation event handler:
If LEG_IW_EN == 1
LA = LIP;IF ENCLAVE_MODE == 1
LA = LA – SECS.BASEADDR;
ENDIF(* Load byte from bitmap. Addres s-size attribute for this load is 64 bits if IA32_EFER.LMA is  1 and is 32 bits when IA32_EFER.L MA 
is 0 *)
IF (IA32_EFER.LMA & CS.L) == 0
BITMAP_BYTE = load 1 byte from address (BITMAP_BASE + LA[31:15])
ELSE IF (CR4.LA57 == 0)
BITMAP_BYTE = load 1 byte from address (BITMAP_BASE + LA[47:15])
ELSE
BITMAP_BYTE = load 1 byte from address (BITMAP_BASE + LA[56:15])
FI;IF BITMAP_BYTE & (1 << LA[14:12]) == 0 then Deliver #CP(ENDBRANCH) fault
IF CPL = 3
IA32_U_CET.TRACKER = IDLEIA32_U_CET.SUPPRESS = IA32_U_CE T.SUPPRESS_DIS == 0 ? 1 : 0
ELSE
IA32_S_CET.TRACKER = IDLEIA32_S_CET.SUPPRESS = IA32_S_ CET.SUPPRESS_DIS == 0 ? 1 : 0
ENDIFRestart the instruction (h andle all arch. consistency around MOV SS state machines, STI etc.) without 
opening up interrupt/trap window.
ELSE
Deliver #CP(ENDBRANCH) FaultVol. 1 17-13CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
ENDIF
Faults/traps in pseudocode are delivered normally (e.g., #P F, EPT violation). On a fault, the active tracker holds the 
last value (WAIT_FOR_ENDBRANCH) and the address saved on the stack is the current IP (instruction that wasn’t 
the ENDBRANCH).
The CET indirect branch tracking state machine is supp ressed in legacy compatibility mode if the SUPPRESS_DIS 
control bit is 0.
Once the CET indirect branch tracking state machine has been suppressed, subsequent indirect CALL/JMP are not 
tracked for termination instruction.
Once CET indirect branch tracking has been suppressed, subsequent execution of ENDBRANCH instructions will do 
the following (see the ENDBR32 and ENDBR64 instructions in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2A for details).
IF EndbranchEnabled(CPL) == 0
NOP
ELSE
SUPPRESS = 0TRACKER = IDLE
ENDIF
17.3.6.1  Legacy Code  Page Bitmap Format
The legacy code page bitmap is a fl at bitmap whose linear address is po inted to by the EB _LEG_BITMAP_BASE. 
Each bit in the bitmap represents a 4K page in linear memory . If the bit is 1 it indicates that the corresponding code 
page is a legacy code page; else it is a CET-enabled code page.
The processor uses the linear address of the instruction to which legacy transfer was attempted to lookup the 
bitmap. Bits of the linear address used as index in the bitmap are as follows.
•In legacy and compatibility mode: Bits 31:12.
•In 64-bit mode (EFER.LMA=1 and CS.L=1): Bits 47:12.
17.3.7 Other Considerations
17.3.7.1  Intel® Transactional Synchroniz ation Extensions (Intel® TSX) Interactions
The XBEGIN instruction encodes the relative offset to the abort handler and hence the fallback to the abort handler 
can be considered as a “direct” branch and the ab ort handler does not need to have an ENDBRANCH.
CET continues to enforce indirect CALL/JMP tracking with in a transaction. Legacy compatibility treatment inside a 
transaction functions normally. If a transaction abort occurs then the processor sets the state of the indirect branch tracker to IDLE and not-suppressed.
17.3.7.2  #CP(ENDBRANCH) Priority w.r.t #NM and #UD
#NM, #UD and #CP(ENDBRANCH) are opco de based faults. However, #CP(ENDB RANCH) is in a higher priority 
class than #NM and #UD as CET architecturally requir es an ENDBRANCH at target  of indirect CALL/JMP.
17.3.7.3  #CP(ENDBRANCH) Priority w.r.t #BP and #DB
Debug Exceptions priority is as follows.
•Traps delivered before any #CP(ENDBRANCH) fault: Data breakpoint trap, IO breakpoint trap single step trap, 
task switch trap.
•Code Breakpoint fault detected before instruct ion decode and delivered before #CP(ENDBRANCH).
•General-detect (GD) exception condition fault: Lower priority than #CP(ENDBRANCH).17-14 Vol. 1CONTROL-FLOW ENFORCEMENT TECHNOLOGY (CET)
•On IRET back from #DB/#BP, the source indirect bran ch tracker becomes active if enabled and not suppressed.
INT3 does not cause #CP(ENDBRANCH) to support debugger  usage of replacing bytes of ENDBRANCH with INT3 to 
set breakpoints. INT3 at target of a CALL-JMP(ind irect) cause #BP(INT3) instead of #CP(ENDBRANCH), 
#CP(ENDBRANCH) fault is delayed. #BP caused by INT3 trea ted like other events that are higher priority than CET 
fault. On IRET back from #BP the source indirect tracker becomes active if enabled and not suppressed.
17.3.8 Constraining Speculation after Missing ENDBRANCH
When the CET tracker is in the WAIT_FOR_ENDBRANCH state, instruction execution will be limited or blocked, even 
speculatively, if the next instruction is not an ENDBRANCH.
This means that when indirect branch tracking is enable d and not suppressed, the instructions at the target of a 
near indirect JMP/CALL without the no-track prefix will on ly speculatively execute if th ere is an ENDBRANCH at the 
target. This can constrain both attacker controlled prediction as well as attacker controlled jump redirection attacks on near indirect JMPs/CALLs by reducing the gadgets ava ilable to an attacker using these techniques. Early imple-
mentations of CET may limit the speculative execution to a sm all number of instructions (less than 8, with no more 
than 5 loads) past a missing ENDBRANC H, while later implementations will completely block the speculative execu-
tion of instructions after a missing ENDBRANCH.
This mechanism also limits or blocks speculation of the next  sequential instructions after an indirect JMP or CALL, 
presuming the JMP/CALL puts the CET tracker into th e WAIT_FOR_ENDBRANCH state and the next sequential 
instruction is not an ENDBRANCH.
17.4 INTEL® TRUSTED EXECUTION TEC HNOLOGY (INTEL® TXT) INTERACTIONS
GETSEC[ENTERACCS] and GETSEC[SENTER] clear CR4.CET, and it is not restored when these instructions 
complete.
GETSEC[EXITAC] will cause #GP(0) fault if CR4.CET is set.Vol. 1 18-1CHAPTER 18
PROGRAMMING WITH INTEL® ADVANCED MATRIX EXTENSIONS
18.1 INTRODUCTION
Intel® Advanced Matrix Extensions (Intel® AMX) is a new 64-bit programming paradigm consisting of two compo-
nents: a set of 2-dimensional registers (tiles) representing  sub-arrays from a larger 2-dimensional memory image, 
and an accelerator able to operate on tiles, the first im plementation is called TMUL (tile matrix multiply unit).
An Intel AMX implementation enumerates to the progra mmer how the tiles can be programmed by providing a 
palette of options. Two palettes are supported; palette 0 repr esents the initialized state, and palette 1 consists of 8 
KB of storage spread across 8 tile re gisters named TMM0..TMM7. Each tile ha s a maximum size of 16 rows x 64

complete.
KB of storage spread across 8 tile re gisters named TMM0..TMM7. Each tile ha s a maximum size of 16 rows x 64 
bytes, (1 KB), however the programmer can configure each  tile to smaller dimensions appropriate to their algo-
rithm. The tile dimensions supplied by th e programmer (rows and bytes_per_row, i.e., colsb ) are metadata that 
drives the execution of tile and accelerator instructions. In this way, a single instruction can launch autonomous 
multi-cycle execution in the tile and accelerator hardware. The palette value ( palette_id ) and metadata are held 
internally in a tile related control register (TILECFG). The TILECFG contents will be commensurate with that 
reported in the palette_table (see “C PUID—CPU Identifica tion” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2A for a description of the available parameters).
Intel AMX is an extensible architecture. New accelerators can be added, or the TMUL accelerator may be enhanced 
to provide higher performance. In these cases, the state (T ILEDATA) provided by tiles may need to be made larger, 
either in one of the metadata dimensions (more rows or colsb) and/or by supporting mo re tile registers (names). 
The extensibility is carried out by adding new palette entr ies describing the additional state. Since execution is 
driven through metadata, an existing Intel AMX binary co uld take advantage of larger storage sizes and higher 
performance TMUL units by selecting the most powerful pa lette indicated by CPUID and adjusting loop and pointer 
updates accordingly.
Figure 18-1.  Intel® AMX ArchitectureIA Host
Coherent Memory 
InterfaceAccelerator 1 (TMUL)
tmm0 += tmm1*tmm2
Accelerator 2Tiles and 
Accelerator 
Commands
TILECFG
tmm0
tmm1
tmm[n-1]...
New state to be managed by the OS.
Commands and status delivered synchronously via tile/accelerator instructions.
Dataflow; accelerators communicate to host through memory.18-2 Vol. 1PROGRAMMING WITH INTEL® ADVANCED MATRIX EXTENSIONS
Figure 18-1 shows a conceptual diagram of the Intel AMX arch itecture. An Intel architecture host drives the algo-
rithm, the memory blocking, loop indices and pointer arit hmetic. Tile loads and stores and accelerator commands 
are sent to multi-cycle execution units. Status, if required , is reported back. Intel AMX instructions are synchronous 
in the Intel architecture instruction stream and the memory loaded and stored by the tile instructions is coherent 
with respect to the host’s memory accesses. There are no re strictions on interleaving of Intel architecture and Intel 
AMX code or restrictions on the resources the host can use in parallel with Intel AMX (e.g., Intel AVX-512). There is 
also no architectural requirement on the Intel architecture  compute capability of the Intel architecture host other 
than it supports 64-bit mode.
Intel AMX instructions use new registers and inherit basic behavior from Intel architecture in the same manner that 
Intel SSE and Intel AVX did. Tile instructions include lo ads and stores using the traditional Intel architecture 
register set as pointers. The TMUL instruction set (def ined to be CPUID bits AMX-BF16 and AMX-INT8) only 
supports reg-reg operations.
TILECFG is programmed using the LDTILECFG instruction. The selected palette defines the available storage and 
general configuration while the rest of the memory data specifies the number of rows and column bytes for each 
tile. Consistency checks are performed to ensure the TI LECFG matches the restrictions of the palette. A General 
Protection fault (#GP) is reported if the LDTILECFG fails consistency checks. A successful load of 
TILECFG with a palette_id other than 0 is represented in  this document with TILES_CONFIGURED = 1. When the 
TILECFG is initialized (palette_id = 0), it is represente d in the document as TILES_CONFIGURED = 0. Nearly all 
Intel AMX instructions will generate a #UD exception if TILES_CONFIGURED is not equal to 1; the exceptions are 
those that do TILECFG maintenance: LD TILECFG, STTILECFG, and TILERELEASE.
If a tile is configured to contain M rows by N column by tes, LDTILECFG will ensure that the metadata values are 
appropriate to the palette (e.g., that M ≤ 16 and N ≤ 64 for palette 1). The four M and N values can all be different 
as long as they adhere to the restrictions of the palette . Further dynamic checks are done in the tile and the TMUL 
instruction set to deal with cases where a legally configured  tile may be inappropriate for the instruction operation. 
Tile registers can be set to ‘invalid’ by  configuring the rows and colsb to ‘0’. 
Tile loads and stores are strided accesses from the app lication memory to packed rows of data. Algorithms are 
expressed assuming row major data layout. Column majo r users should translate the terms according to their 
orientation.
TILELOAD* and TILESTORE* instructions are restartable and can handle (up to) 2*rows page faults per instruction. 
Restartability is provided by a start_row  parameter in the TILECFG register.
The TMUL unit is conceptually a grid of fused multiply-add units able to read and write tiles. The dimensions of the 
TMUL unit (tmul_maxk and tmul_maxn) are enumerated si milar to the maximum dimensions of the tiles (see 
“CPUID—CPU Identification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A for 
details). 
The matrix multiplications in the TMUL instruction set compute C[M][N] += A[M][K] * B[K][N]. The M, N, and K 
values will cause the TMUL instruction set to generate a #UD exception if the dimensions do not match for matrix 
multiply or do not match the palette.
In Figure 18-2, the number of rows in tile B matches th e K dimension in the matrix multiplication pseudocode. K 
dimensions smaller than that enumerated in the TMUL grid are also possible and any additional computation the TMUL unit can support will not affect the result.
The number of elements specified by colsb of the B matrix  is also less than or equal to tmul_maxn. Any remaining 
values beyond that specified by the metadata will be set to zero. Vol. 1 18-3PROGRAMMING WITH INTEL® AD VANCED MATRIX EXTENSIONS
The XSAVE feature set supports context management of the new state defined for Intel AMX. This support is 
described in Section 18.2.
18.1.1 Tile Architecture Details
The supported parameters for the tile architecture are repo rted via CPUID; this includes information about how the 
number of tile registers (max_names) can be configured (the  palette). Configuring the tile architecture is intended 
to be done once when entering a region of tile code us ing the LDTILECFG instruction specifying the selected palette 
and describing in detail the configuration for each tile. Incorrect assignments will result in a General Protection fault 
(#GP). Successful LDTILECFG initializes (zeroes) TILEDATA.
Exiting a tile region is done with the TILERELEASE instruct ion. It takes no parameters and invalidates all tiles (indi-
cating that the data no longer needs any saving or restor ing). Essentially, it is an optimization of LDTILECFG with 
an implicit palette of 0.
For applications that execute consecutive Intel AMX regi ons with differing configur ations, TILERELEASE is not 
required between them since the second LDTILECFG will cl ear all the data while loading the new configuration. 
There is no instruction set support for automatic nesting of tile regions, though with sufficient effort software can 
accomplish this by saving and restoring TILEDATA and TI LECFG either through the XSAVE architecture or the Intel 
AMX instructions.
The tile architecture boots in its INIT state, with TI LECFG and TILEDATA set to zero. A successfully executing 
LDTILECFG instruction to a non-zero palette sets the TI LES_CONFIGURED=1, in dicating the TILECFG is not in the 
INIT state. The TILERELEASE instruction sets TILES_ CONFIGURED = 0 and initializes (zeroes) TILEDATA.
To facilitate handling of tile configuration data, there is a STTILECFG instruction. If the tile configuration is in the 
INIT state (TILES_CONFIGURED == 0), then STTILECFG wi ll write 64 bytes of zeros. Otherwise STTILECFG will 
store the TILECFG to memory in the format used by LDTILECFG.Figure 18-2.  The TMUL UnitC[M][N]
B[K][N]. . . .FMA.0.N-1. . . .FMA.1.N-1
FMA.K-1.N-1A[M][K]FMA.0.0. . . .FMA.1.0
FMA.K-1.0FMA.0.1. . . .FMA.1.1
FMA.K-1.1A[m-1][1]A[m][0]
. . . .. . . .
A[m-K+1][K-1]C[m][n-1]
C[m-K+1][n-1]C[m][1]
C[m-K+1][1]C[m][0]
C[m-K+1][0]B[0][:N]
B[1][:N]
B[K-1][:N]
for m < M: // time steps
    for k < K: // grid height        for n < N: // SIMD dimension            C[m][n] += VNNI_MUL(A[m][k], B[k][n])18-4 Vol. 1PROGRAMMING WITH INTEL® ADVANCED MATRIX EXTENSIONS
18.1.2 TMUL Architecture Details
The supported parameters for the TMUL architecture are reported via CPUID; see “CPUID—CPU Identification” in 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for details. These parameters 
include a maximum height ( tmul_maxk ) and a maximum SIMD dimension ( tmul_maxn ). The metadata that

. . . .. . . .
B[1][:N]
include a maximum height ( tmul_maxk ) and a maximum SIMD dimension ( tmul_maxn ). The metadata that 
accompanies the srcdest, src1, and src2 tiles to the TMUL unit will be dynamically checked to see that they match 
the TMUL unit support for the data type and match the requirements of a meaningful matrix multiplication.
Figure 18-3 shows an example of the inner loop of an algori thm of using the TMUL architecture to compute a matrix 
multiplication. In this example, we use two result tiles,  tmm0 and tmm1, from matrix C to accumulate the interme-
diate results. One tile from the A matrix (tmm2) is re-used twice as we multiply it by two tiles from the B matrix. 
The algorithm then advances pointers to load a new A tile  and two new B tiles from the directions indicated by the 
arrows. An outer loop, not shown, adjusts the pointers for the C tiles.
18.1.3 Handling of Tile Row and Column Limits
Intel AMX operations will zero any rows and any columns be yond the dimensions specified by TILECFG. Tile opera-
tions will zero the data beyond the conf igured number of column bytes as each  row is written. For example, with 
64-byte rows and a tile configured with 10 rows and 48 columns, an operation writing dword elements would write Figure 18-3.  Matrix Multiply C+= A*B   LDTILECFG [rax]
// assume some outer loops driving the cache tiling (not shown){   TILELOADD tmm0, [rsi+rdi]     // srcdst, RSI points to C, RDI is strided value    TILELOADD tmm1, [rsi+rdi+N]   // second tile of C, unrolling in SIMD dimension N
   MOV r14, 0
LOOP:   TILELOADD tmm2, [r8+r9]       // src2 is strided load of A, reused for 2 TMUL instr.   TILELOADD tmm3, [r10+r11]     // src1 is strided load of B   TDPBUSD   tmm0, tmm2, tmm3  // update left tile of C   TILELOADD tmm3, [r10+r11+N]   // src1 loaded with B from next rightmost tile
   TDPBUSD   tmm1, tmm2, tmm3  // update right tile of C
   ADD r8, K                  // update pointers by constants known outside of loop   ADD r10, K*r11   ADD r14, K   CMP r14, LIMIT   JNE LOOP
   TILESTORED [rsi+rdi],   tmm0  // update the C matrix in memory
   TILESTORED [rsi+rdi+M], tmm1     } // end of outer loop
   TILERELEASE         // return tiles to INIT stateC B AVol. 1 18-5PROGRAMMING WITH INTEL® AD VANCED MATRIX EXTENSIONS
each of the first 10 rows with 48 bytes of output/result da ta and zero the remaining 16 bytes in each row. Tile oper-
ations also fully zero any rows after the first 10 configured rows. When using a 1 KByte tile with 64-byte rows, there would be 16 rows, so in this example, the last 6 rows would also be zeroed.
Intel AMX instructions will always obey the metadata on re ads and the zeroing rules on writes, and so a subsequent 
XSAVE would see zeros in the appropriate locations. Tiles that are not written by Intel AMX instructions between 
XRSTOR and XSAVE will write back with the same image they  were loaded with regardle ss of the value of TILECFG.
18.1.4 Exceptions and Interrupts
Tile instructions are restartable so that operations that  access strided memory can restart after page faults. To 
support restarting instructions after these events, the instructions store information in the TILECFG.start_row  
register. TILECFG.start_row indicates the row that should be used for restart; i.e., it indicates next row after  the 
rows that have already been successfully loaded (on a TILELOAD) or written to memory (on a TILESTORE) and 
prevents repeating work that was successfully done.
The TMUL instruction set is not sensitive to the TILECFG.start_row value; this is due to there not being TMUL 
instructions with memory operands or any restartable faults.
18.2 RECOMMENDATIONS FOR SYSTEM SOFTWARE
Intel AMX is an XSAVE-enabled feature, meaning that it requires use of the XSAVE feature set for their enabling. 
Specifically, Intel AMX instructions and state are availabl e only if system software has set CR4.OSXSAVE and also 
set XCR0[18:17] to 11B. In addition, use of Intel AMX instru ctions is disabled if system software has used extended 
feature disable (XFD) and set either IA32_XFD[17] or IA 32_XFD[18] to 1. See Chapter 13, “Managing State Using 
the XSAVE Feature Set,” for more details.
NOTE
The first processors implementing Intel AMX will support setting IA32_XFD[18] but not IA32_XFD[17]. 
Once Intel AMX has been enabled, system software can disable it by clearing XCR0[18:17], by clearing 
CR4.OSXSAVE, or by setting either IA32_XFD[17] or IA32 _XFD[18]. Before doing do, system software should first 
initialize AMX state (e.g., by execut ing TILERELEASE); maintaining AMX state in a non-initialized state may have 
negative power and performance implications. In addition, so ftware should not rely on the state of the tile data 
after setting IA32_XFD[17] or IA32_XFD[18]; software shou ld always reload or reinitialize the tile data after 
clearing IA32_XFD[17] and IA32_XFD[18].
System software should not use XFD to implement a “lazy restore” approach to management of the TILEDATA state 
component. This approach will not operate correctly for a variety of reasons. One is that the LDTILECFG and 
TILERELEASE instructions initialize TILEDATA and do not cause an #NM exception. Another is that an execution of 
XSAVE, XSAVEC, XSAVEOPT, or XSAVES by a user thread will save TILEDATA as initialized instead of the data 
expected by the user thread.
18.3 IMPLEMENTATION PARAMETERS
The parameters are reported via CPUID leaf 1D H. Index 0 reports all zeros for all fields.18-6 Vol. 1PROGRAMMING WITH INTEL® ADVANCED MATRIX EXTENSIONS
The tile parameters are set by LDTILECFG or XRSTOR* of TILECFG:
18.4 HELPER FUNCTIONS
The helper functions used in Intel AMX instructions are defined below.define palette_table[id]: 
uint16_t total_tile_bytes 
uint16_t bytes_per_tile uint16_t bytes_per_row uint16_t max_names uint16_t max_rows
define tile[tid]: 
byte rowsword colsb // bytes_per_row 
bool valid
define write_row_and_zero(treg, r, data, nbytes): 
for j in 0 ... nbytes-1:
treg.row[r].byte[j] := data.byte[j]
// zero the rest of the row
for j in nbytes ... palette_table[tilecfg.palette_id].bytes_per_row-1:
treg.row[r].byte[j] := 0
define zero_upper_rows(treg, r):
for i in r ... palette_table[tilecfg.palette_id].max_rows-1:
for j in 0 ... palette_table[tilecfg.palette_id].bytes_per_row-1: 
treg.row[i].byte[j] := 0
define zero_tilecfg_start(): 
tilecfg.start_row := 0
define zero_all_tile_data(): 
if XCR0[TILEDATA]:
b := CPUID(0xD,TILEDATA).EAX // size of feature 
for j in 0 ... b:
TILEDATA.byte[j] := 0Vol. 1 18-7PROGRAMMING WITH INTEL® AD VANCED MATRIX EXTENSIONS
define xcr0_supports_palette(palette_id): 
if palette_id == 0:
return 1
elif palette_id == 1:
if XCR0[TILECFG] and XCR0[TILEDATA]:
return 1
return 018-8 Vol. 1PROGRAMMING WITH INTEL® ADVANCED MATRIX EXTENSIONSVol. 1 19-1CHAPTER 19
In addition to transferring data to and from external me mory, IA-32 processors can also transfer data to and from 
input/output ports (I/O ports). I/O ports are created in system hardware by circuity that decodes the control, data, and address pins on the processor. These I/O ports are then  configured to communicate with peripheral devices. An 
I/O port can be an input port, an output port, or a bidirectional port. Some I/O ports are used for transmitting data, 
such as to and from the transmit and receive registers, re spectively, of a serial interface device. Other I/O ports are 
used to control peripheral devices, such as  the control registers of a disk controller.
This chapter describes the processor’s I/O architecture. The topics discussed include:
•I/O port addressing.
•I/O instructions.
•I/O protection mechanism.
19.1 I/O PORT ADDRESSING
The processor permits applications to access I/O ports in either of two ways:
•Through a separate I/O address space.
•Through memory-mapped I/O.
Accessing I/O ports through the I/O address space is hand led through a set of I/O instructions and a special I/O 
protection mechanism. Accessing I/O ports through memo ry-mapped I/O is handled with the processor’s general-
purpose move and string instructions, with protection pr ovided through segmentation or paging. I/O ports can be 
mapped so that they appear in the I/O address spac e or the physical-memory address space (memory mapped 
I/O) or both.
One benefit of using the I/O address space is that writes to I/O ports are guaranteed to be completed before the 
next instruction in the instruction stream is executed. Thus, I/O writes to control system hardware cause the hard-ware to be set to its new state before any other instru ctions are executed. See Section 19.6, “Ordering I/O,” for 
more information on serializing of I/O operations.
19.2 I/O PORT HARDWARE
From a hardware point of view, I/O addressing is handled through the processor’s address lines. For the P6 family, 
Pentium 4, and Intel Xeon processors, the request command lines signal whether the address lines are being driven 
with a memory address or an I/O address; for Pentium pr ocessors and earlier IA-32 processors, the M/IO# pin indi-
cates a memory address (1) or an I/O address (0). When the separate I/O address space is selected, it is the

cates a memory address (1) or an I/O address (0). When the separate I/O address space is selected, it is the 
responsibility of the hardware to decode the memory-I/O bus transaction to select I/O ports rather than memory. 
Data is transmitted between the processor and an I/O device through the data lines.
19.3 I/O ADDRESS SPACE
The processor’s I/O address space is separate and dist inct from the physical-memory address space. The I/O 
address space consists of 216 (64K) individually addressable 8-bit I/O ports, numbered 0 through FFFFH. I/O port 
addresses 0F8H through 0FFH are reserved. Do not assign I/O ports to these addresses. The result of an attempt 
to address beyond the I/O address space limit of FFFFH is  implementation-specific; see the Developer’s Manuals for 
specific processors for more details.
Any two consecutive 8-bit ports can be treated as a 16-bit port, and any four consecutive ports can be a 32-bit port. 
In this manner, the processor can transfer 8, 16, or 32 bits to or from a device in the I/O address space. Like words 
in memory, 16-bit ports should be aligned to even addresses (0 , 2, 4, ...) so that all 16 bits can be transferred in a 19-2 Vol. 1INPUT/OUTPUT
single bus cycle. Likewise, 32-bit ports should be aligned to  addresses that are multiples of four (0, 4, 8, ...). The 
processor supports data transfers to unaligned ports, but there is a performance penalty because one or more extra bus cycle must be used.
The exact order of bus cycles used to access unaligned port s is undefined and is not guaranteed to remain the same 
in future IA-32 processors. If hardware or software requires that I/O ports be written to in a particular order, that 
order must be specified explicitly. For example, to load a word-length I/O port at address 2H and then another word 
port at 4H, two word-length writes must be used , rather than a single doubleword write at 2H.
Note that the processor does not mask parity errors for bus cycles to the I/O address space. Accessing I/O ports 
through the I/O address space is thus a possible source of parity errors.
19.3.1 Memory-Mapped I/O
I/O devices that respond like memory components ca n be accessed through the processor’s physical-memory 
address space (see Figure 19-1). When using memory-mapped I/O, any of the processor’s instructions that refer-
ence memory can be used to access an I/O port locate d at a physical-memory address. For example, the MOV 
instruction can transfer data between any register and a memory-mapped I/O port. The AND, OR, and TEST 
instructions may be used to manipulate bits in the co ntrol and status registers of a memory-mapped peripheral 
device.
Certain instructions may take an exception or VM exit af ter completing a memory access (either a read or a write) 
to a memory-mapped I/O address. This exception or VM ex it could be due to the instruction performing multiple 
memory accesses (e.g., MOVS, PUSH mem, POP mem, PUSHAD , etc.) or could be due to the ordering of exceptions 
or VM exits within the instruction (e.g., a DIV mem that ta kes a #DE or a CALL that causes a task switch VM exit). 
If software later re-executes that instruction (e.g., af ter an IRET or VMRESUME), the MMIO (memory-mapped I/O) 
access may occur again. If the memory-mapped I/O access has a side-effect, that side-effect may be executed 
each time the memory-mapped I/O access occurs. If that is problematic, software must ensure that exceptions or 
VM exits do not occur after accessing the MMIO.
When using memory-mapped I/O, cachin g of the address space mapped for I/O operations must be prevented. 
With the Pentium 4, Intel Xeon, and P6 family processo rs, caching of I/O accesses can be prevented by using 
memory type range registers (MTRRs) to map the addre ss space used for the memory-mapped I/O as uncacheable 
(UC). See Chapter 12, “Memory Cache Control,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A, for a complete discussion of the MTRRs.
The Pentium and Intel486 processors do not support MTRRs. Instead, they provide the KE N# pin, which when held 
inactive (high) prevents caching of all addresses sent ou t on the system bus. To use this pin, external address 
decoding logic is required to block caching in specific address spaces.
Figure 19-1.  Memory-Mapped I/OFFFF 
I/O PortEPROM
RAMPhysical Memory
0I/O Port
I/O PortVol. 1 19-3INPUT/OUTPUT
All the IA-32 processors that have on-chip caches also prov ide the PCD (page-level cache disable) flag in page table 
and page directory entries. This flag allows caching to be disabled on a page-by-page basis. See “Page-Directory and Page-Table Entries” in Chapter 4 of the Intel
Volume 3A.
19.4 I/O INSTRUCTIONS
The processor’s I/O instructions provide access to I/O ports through the I/O address space. (These instructions cannot be used to access memory-mapped I/O ports.) There are two groups of I/O instructions:
•Those that transfer a single item (byte, word, or doubleword) between an I/O port and a general-purpose 
register.
•Those that transfer strings of items (strings of byte s, words, or doublewords) between an I/O port and 
memory.
The register I/O instructions IN (input from I/O port) and OUT (output to I/O port) move data between I/O ports 
and the EAX register (32-bit I/O), the AX register (16-bit I/O), or the AL (8-bit I/O) register. The address of the I/O 
port can be given with an immediate value or a value in the DX register. 
The string I/O instructions INS (input string from I/O port) and OUTS (output string to I/O port) move data 
between an I/O port and a memory location. The address of the I/O port being accessed is given in the DX register; 
the source or destination memory address is given in the DS:ESI or ES:EDI register, respectively.
When used with the repeat prefix REP, the INS and OUTS instructions perform string (or block) input or output 
operations. The repeat prefix REP modifi es the INS and OUTS instructions to transfer blocks of data between an I/O 
port and memory. Here, the ESI or EDI register is increm ented or decremented (according to the setting of the DF 
flag in the EFLAGS register) after each  byte, word, or doubleword is transferred between the selected I/O port and 
memory.
See the references for IN, INS, OUT, and OUTS in Chapter 3 and Chapter 4 of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2 D, for more information on these instructions.
19.5 PROTECTED-MODE I/O
When the processor is running in protected mode, the following protection mechanisms regulate access to I/O 
ports:
•When accessing I/O ports through the I/O address space, two protection devices control access:
— The I/O privilege level (IOPL) field in the EFLAGS register.— The I/O permission bit map of a task state segment (TSS).
•When accessing memory-mapped I/O ports, the normal segmentation and paging protection and the MTRRs 
(in processors that support them) also affect access to I/O ports. See Chapter 5, “P rotection,” and Chapter 12, 
“Memory Cache Control,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for 
a complete discussion of memory protection. 
The following sections describe the protection mechanisms available when accessing I/O ports in the I/O address 
space with the I/O instructions.
19.5.1 I/O Privilege Level
In systems where I/O protection is used, the IOPL field in  the EFLAGS register controls access to the I/O address 
space by restricting use of selected instructions. This pr otection mechanism permits the operating system or exec-
utive to set the privilege level needed to perform I/O. In a typical protection ring model, access to the I/O address 
space is restricted to privilege levels 0 and 1. Here, the kernel and the device drivers are allowed to perform I/O, 
while less privileged device drivers and application progra ms are denied access to the I/O address space. Applica-
tion programs must then make calls to the operating system to perform I/O.19-4 Vol. 1INPUT/OUTPUT
The following instructions can be executed only if the curre nt privilege level (CPL) of the program or task currently 
executing is less than or equal to the IOPL: IN, INS, OU T, OUTS, CLI (clear interrupt-enable flag), and STI (set 
interrupt-enable flag). These instructions are called I/O sensitive  instructions, because they are sensitive to the 
IOPL field. Any attempt by a less privileged program or task  to use an I/O sensitive instruction results in a general-
protection exception (#GP) being signaled. Because each ta sk has its own copy of the EFLAGS register, each task 
can have a different IOPL.
The I/O permission bit map in the TSS can be used to modify the effect of the IOPL on I/O sensitive instructions, 
allowing access to some I/O ports by less privileged programs or tasks (see Section 19.5.2, “I/O Permission Bit 
Map”).
A program or task can change its IOPL only with the POPF and IRET instructions; however, such changes are privi-

Map”).
leged. No procedure may change the current IOPL unless it is  running at privilege level 0. An attempt by a less priv-
ileged procedure to change the IOPL does not result in an exception; the IOPL  simply remains unchanged.
The POPF instruction also may be used to change the st ate of the IF flag (as can the CLI and STI instructions); 
however, the POPF instruction in this case is also I/O sensitive. A procedure may use the POPF instruction to change the setting of the IF flag only if th e CPL is less than or equal to the curre nt IOPL. An attempt by a less privileged 
procedure to change the IF flag does not result in an exception; the IF flag simply remains unchanged.
19.5.2 I/O Permission Bit Map
The I/O permission bit map is a device for permitting lim ited access to I/O ports by less privileged programs or 
tasks and for tasks operating in virtual-8086 mode. The I/O permission bit map is located in the TSS (see 
Figure 19-2) for the currently running task or program. The address of the first byte of the I/O permission bit map 
is given in the I/O map base address field of the TSS. The size of the I/O permission bit map and its location in the 
TSS are variable. 
Because each task has its own TSS, each task has its own I/O permission bit map. Access to individual I/O ports 
can thus be granted to individual tasks.
If in protected mode and the CPL is less than or equal to the current IOPL, the processor allows all I/O operations 
to proceed. If the CPL is greater than the IOPL or if th e processor is operating in virtual-8086 mode, the processor 
checks the I/O permission bit map to determine if access to a particular I/O port is allowed. Each bit in the map 
corresponds to an I/O port byte address. For example, th e control bit for I/O port address 29H in the I/O address 
space is found at bit position 1 of the sixth byte in the bit map. Before granting I/O access, the processor tests all the bits corresponding to the I/O port being addressed. Fo r a doubleword access, for example, the processors tests 
the four bits corresponding to the four adjacent 8-bit port addresses. If any tested bit is set, a general-protection 
exception (#GP) is signaled. If all tested bits are clear, the I/O operation is allowed to proceed.Figure 19-2.  I/O Permission Bit MapI/O Map BaseTask State Segment (TSS)
64H31 2423 0
1 1111111
I/O Permission Bit Map
0I/O map base 
must not 
exceed DFFFH.Last byte of bitmap must be 
followed by a 
byte with all bits set.Vol. 1 19-5INPUT/OUTPUT
Because I/O port addresses are not necessarily aligned to  word and doubleword boundaries, the processor reads 
two bytes from the I/O permission bit map for every access to an I/O port. To prevent exceptions from being gener-
ated when the ports with the highest addresses are accessed,  an extra byte needs to be included in the TSS imme-
diately after the table. This byte must have all of it s bits set, and it must be  within the segment limit.
It is not necessary for the I/O permission bit map to repr esent all the I/O addresses. I/O addresses not spanned by 
the map are treated as if they had set bits in the map. Fo r example, if the TSS segment limit is 10 bytes past the 
bit-map base address, the map has 11 bytes and the firs t 80 I/O ports are mapped. Higher addresses in the I/O 
address space generate exceptions.
If the I/O bit map base address is greater than or equal to the TSS segment limit, there is no I/O permission map, 
and all I/O instructions generate exceptions wh en the CPL is greater than the current IOPL.
19.6 ORDERING I/O
When controlling I/O devices it is often important that me mory and I/O operations be carried out in precisely the 
order programmed. For example, a program may write a comma nd to an I/O port, then read the status of the I/O 
device from another I/O port. It is important that the status returned be the status of the device after  it receives 
the command, not before . 
When using memory-mapped I/O, cautio n should be taken to avoid situations in which the programmed order is 
not preserved by the processor. To optimize performanc e, the processor allows cacheable memory reads to be 
reordered ahead of buffered writes in  most situations. Internally, processor reads (cache hits) can be reordered 
around buffered writes. When using memory-mapped I/O, th erefore, it is possible that an I/O read might be 
performed before the memory write of a previous inst ruction. The recommended method of enforcing program 
ordering of memory-mapped I/O accesses with the Pentium 4,  Intel Xeon, and P6 family processors is to use the 
MTRRs to make the memory mapped I/O address space uncacheable; for the Pentium and Intel486 processors, 
either the KEN# pin or the PCD flags can be used for this purpose (see Section 19.3.1, “Memory-Mapped I/O”). 
When the target of a read or write is in an uncachea ble region of memory, memory  reordering does not occur 
externally at the processor’s pins (that is, reads and wr ites appear in-order). Designating a memory mapped I/O 
region of the address space as uncacheable ensures that re ads and writes of I/O devices are carried out in program 
order. See Chapter 12, “Memory Cache Control,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A, for more information on using MTRRs.
Another method of enforcing program order is to insert one of the serializing instructions, such as the CPUID 
instruction, between operations. See Chapter 9, “Multiple-Processor Management,” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 3A, fo r more information on serialization of instructions.
It should be noted that the chipset being used to support  the processor (bus controller, memory controller, and/or 
I/O controller) may post writes to uncacheable memory which can lead to out-of-order execution of memory 
accesses. In situations where out-of-order processing of memory accesses by the chipset can potentially cause 
faulty memory-mapped I/O processing, code must be wri tten to force synchronization and ordering of I/O opera-
tions. Serializing instructions can often be used for this purpose.
When the I/O address space is used instead of memory-mapped I/O, the situation is different in two respects:
•The processor never buffers I/O writes. Therefore, stri ct ordering of I/O operations is enforced by the 
processor. (As with memory-mapped I/O, it is possible for a chipset to post writes in certain I/O ranges.)
•The processor synchronizes I/O instruction executio n with external bus activity (see Table 19-1). 19-6 Vol. 1INPUT/OUTPUT
Table 19-1.  I/O Instruction Serialization
Instruction Being 
ExecutedProcessor Delays Execution of … Until Completion of …
Current Instruction? Next Instruct ion? Pending Stores? Current Store?
IN Yes YesINS Yes Yes
REP INS Yes Yes
OUT Yes Yes YesOUTS Yes Yes Yes
REP OUTS Yes Yes YesVol. 1 20-1CHAPTER 20
When writing software intended to run on IA-32 processors, it is necessary to identify the type of processor present 
in a system and the processor features that are available to an application.
20.1 USING THE CPUID INSTRUCTION
Use the CPUID instruction for processor identification in the Pentium M processor family, Pentium 4 processor family, Intel Xeon processor family, P6 family, Pentium processor, and later Intel486 processors. This instruction returns the family, model, and (for some processors) a brand string for the processor that executes the instruction. 
It also indicates the features that are present in the processor and gives information about the processor’s caches 
and TLB.
The ID flag (bit 21) in the EFLAGS register indicates supp ort for the CPUID instruction. If a software procedure can 
set and clear this flag, the processor executing the proc edure supports the CPUID inst ruction. The CPUID instruc-
tion will cause the invalid opcode exception (#UD) if  executed on a processor that does not support it.
To obtain processor identification information, a source op erand value is placed in the EAX register to select the 
type of information to be returned. When the CPUID instruct ion is executed, selected information is returned in the 
EAX, EBX, ECX, and EDX registers. For a complete description of the CPUID instruction, tables indicating values 
returned, and example code, see CPUID—CPU Id entification in Chapter 3 of the Intel
® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 2A.
20.1.1 Notes on Where to Start
The following guidelines are among the most important,  and should always be followed when using the CPUID 
instruction to determine available features:
•Always begin by testing for the “GenuineIntel,” message  in the EBX, EDX, and ECX registers when the CPUID 
instruction is executed with EAX equal to 0. If the proce ssor is not genuine Intel, the feature identification flags 
may have different meanings than ar e described in Intel documentation.

•Test feature identification flags individually an d do not make assumptions about undefined bits.
20.1.2 Identification of Earlier IA-32 Processors
The CPUID instruction is not available in earlier IA-32 processors up through the earlier Intel486 processors. For 
these processors, several other architectural features can be exploited to identify the processor.
The settings of bits 12 and 13 (IOPL), 14 (NT), and 15 (res erved) in the EFLAGS register are different for Intel’s 32-
bit processors than for the Intel 8086 and Intel 286 proce ssors. By examining the settings of these bits (with the 
PUSHF/PUSHFD and POPF/POPFD instructions), an application program can determine whether the processor is an 8086, Intel 286, or one of the Intel 32-bit processors:
•8086 processor — Bits 12 through 15 of the EFLAGS register are always set.
•Intel 286 processor — Bits 12 through 15 are always clear in real-address mode.
•32-bit processors — In real-address mode, bit 15 is alwa ys clear and bits 12 through 14 have the last value 
loaded into them. In protected mode, bit 15 is always clea r, bit 14 has the last value loaded into it, and the IOPL 
bits depend on the current privilege level (CPL). The IOPL field can be changed only if the CPL is 0.
Other EFLAGS register bits that can be used to differentiate between the 32-bit processors:
•Bit 18 (AC) — Implemented only on the Pentium 4, Inte l Xeon, P6 family, Pentium, and Intel486 processors. 
The inability to set or clear this bit distinguishes an Intel386 processor from the later IA-32 processors.
•Bit 21 (ID) — Determines if the processor is able to ex ecute the CPUID instruction. The ability to set and clear 
this bit indicates that it is a Pentium 4, Intel Xeon, P6 family, Pentium, or later-version Intel486 processor.20-2 Vol. 1PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION
To determine whether an x87 FPU or Numeric Processor Ex tension (NPX) is present in a system, applications can 
write to the x87 FPU status and control registers using the FNINIT instruction and then verify that the correct values are read back using the FNSTENV instruction. 
After determining that an x87 FPU or NPX is present, its ty pe can then be determined. In most cases, the processor 
type will determine the type of FPU or NPX; however, an Intel386 processor is compatible with either an Intel 287 
or Intel 387 math coprocessor. 
The method the coprocessor uses to represent ∞ (after the execution of the FINIT, FNINIT, or RESET instruction) 
indicates which coprocessor is present. The Intel 287 ma th coprocessor uses the same bit representation for + ∞ 
and −∞; whereas, the Intel 387 math coprocessor uses different representations for + ∞ and −∞.Vol. 1 A-1APPENDIX A
EFLAGS CROSS-REFERENCE
A.1 EFLAGS AND INSTRUCTIONS
Table A-2 summarizes how the instructions affect the fl ags in the EFLAGS register. The following codes describe 
how the flags are affected.
Table A-1.  Codes Describing Flags
T Instruction tests flag.
M Instruction modifies flag (either sets or resets depending on operands).
0 Instruction resets flag.
1 Instruction sets flag.— Instruction's effect on flag is undefined.R Instruction restores prior value of flag.
Blank Instruction does not affect flag.
Table A-2.  EFLAGS Cross-Reference
Instruction OF SF ZF AF PF CF TF IF DF NT RF
AAA — — — TM — MAAD — M M — M —
AAM — M M — M —
AAS — — — TM — MA D C MMMMM T M
A D D MMMMMM
AND 0 M M — M 0ARPL M
BOUND
BSF/BSR — — M — — —BSWAP
BT/BTS/BTR/BTC — — — — M
CALLCBW
CLC 0
CLD 0
CLI 0
CLTS
CMC M
CMOV cc TTT TT
C M P MMMMMMA-2 Vol. 1EFLAGS CROSS-REFERENCE
C M P S MMMMMM T
C M P X C H G MMMMMM
CMPXCHG8B M
COMISD 0 0 M 0 M MCOMISS 0 0 M 0 M M
CPUID
CWDDAA — M M TM M TM
DAS — M M TM M TM
D E C MMMMMD I V ——————ENTER
ESC
FCMOV cc TT T
FCOMI, FCOMIP, FUCOMI, FUCOMIP 0 0 M 0 M M
HLT
I D I V ——————I M U L M————M
IN
I N C MMMMMINS T
INT 00
INTO T 0 0INVD
INVLPG
U C O M I S D 00M0MMU C O M I S S 00M0MM
I R E T RRRRRRRRRT
Jcc TTT TT
JCXZ
JMP
LAHFLAR M
LDS/LES/LSS/LFS/LGS
LEALEAVE
LGDT/LIDT/LLDT/LMSW
LOCKTable A-2.  EFLAGS Cross-Reference (Contd.)
I n s t r u c t i o n O FS FZ FA FP FC FT FI F D FN T R FVol. 1 A-3EFLAGS CROSS-REFERENCE
LODS T
LOOP
LOOPE/LOOPNE T
LSL MLTR
MONITOR
MWAITMOV
M O V  c o n t r o l ,  d e b u g ,  t e s t ——————
MOVS T
MOVSX/MOVZXM U L M————M
N E G MMMMMM
NOPNOT
OR 0 M M — M 0
OUTOUTS T
POP/POPA
P O P F RRRRRRRRRRPUSH/PUSHA/PUSHF
RCL/RCR 1 M TM
RCL/RCR count — TMRDMSR
RDPMC
RDTSCREP/REPE/REPNE
RET
ROL/ROR 1 M MROL/ROR count — M
R S M MMMMMMMMMMM
S A H F RRRRRSAL/SAR/SHL/SHR 1 M M M — M M
SAL/SAR/SHL/SHR count — M M — M M
S B B MMMMM T MS C A S MMMMMM T
SETcc TTT TT
SGDT/SIDT/SLDT/SMSWTable A-2.  EFLAGS Cross-Reference (Contd.)
I n s t r u c t i o n O FS FZ FA FP FC FT FI F D FN T R FA-4 Vol. 1EFLAGS CROSS-REFERENCE
SHLD/SHRD — M M — M M
STC 1
STD 1
STI 1
STOS T
STR
S U B MMMMMMTEST 0 M M — M 0
UD
VERR/VERRW MWAITWBINVD
WRMSR
X A D D MMMMMMXCHG
XLAT 
XOR 0 M M — M 0Table A-2.  EFLAGS Cross-Reference (Contd.)
I n s t r u c t i o n O FS FZ FA FP FC FT FI F D FN T R FVol. 1 B-1APPENDIX B
EFLAGS CONDITION CODES
B.1 CONDITION CODES
Table B-1 lists condition codes that can be queried using CMOV cc, FCMOV cc, Jcc, and SET cc. Condition codes refer 
to the setting of one or more status flags (CF, OF, SF , ZF, and PF) in the EFLAGS register. In the table below:
•The “Mnemonic” column provides the suffix (cc) adde d to the instruction to specify a test condition. 
•“Condition Tested For” describes the targeted condition. 
•“Instruction Subcode” provides the opcode suffix adde d to the main opcode to specify the test condition. 
•“Status Flags Setting” desc ribes the flag setting. 
Table B-1.  EFLAGS Condition Codes 
Mnemonic ( cc) Condition Tested ForInstruction
Subcode Status Flags Setting
O Overflow 0000 OF = 1
NO No overflow 0001 OF = 0
B
C
NAEBelow
Carry
Neither above nor equal0010 CF = 1
NB
NC
AENot below
Not carry
Above or equal0011 CF = 0
E
ZEqual
Zero0100 ZF = 1
NE
NZNot equal
Not zero0101 ZF = 0
BE
NABelow or equal
Not above0110 (CF OR ZF) = 1
NBE
ANeither below nor equal
Above0111 (CF OR ZF) = 0
S Sign 1000 SF = 1
NS No sign 1001 SF = 0
P
PEParity
Parity even1010 PF = 1
NP
PONo parity
Parity odd1011 PF = 0
L
NGELess
Neither greater nor equal1100 (SF XOR OF) = 1
NL
GENot less
Greater or equal1101 (SF XOR OF) = 0
LE
NGLess or equal
Not greater1110 ((SF XOR OF) OR ZF) = 1
NLE
GNeither less nor equal
Greater1111 ((SF XOR OF) OR ZF) = 0B-2 Vol. 1EFLAGS CONDITION CODES
Many of the test conditions are described in two differ ent ways. For example, LE (less or equal) and NG (not 
greater) describe the same test condition. Alternate mn emonics are provided to make code more intelligible.
The terms “above” and “below” are associated with the CF  flag and refer to the rela tion between two unsigned 
integer values. The terms “greater” and “less” are associat ed with the SF and OF flags and refer to the relation 
between two signed integer values.Vol. 1 C-1APPENDIX C
FLOATING-POINT EXCEPTIONS SUMMARY
C.1 OVERVIEW
This appendix shows which of the floating-point exceptions can be generated for: 
•x87 FPU instructions — see Table C-2.
•Intel SSE instructions — see Table C-3.
•Intel SSE2 instructions — see Table C-4.
•Intel SSE3 instructions — see Table C-5.
•Intel SSE4 instructions — see Table C-6.
Table C-1 lists types of floating-point exceptions that pote ntially can be generated by the x87 FPU and by Intel SSE, 
SSE2, and SSE3 instructions.
The floating-point exceptions shown in Table C-1 (except for #D and #IS) are defined in IEEE Standard 754-1985 
for Binary Floating-Point Arithmetic. See Section 4.9.1, “F loating-Point Exception Conditions,” for a detailed discus-
sion of floating-point exceptions.
C.2 X87 FPU INSTRUCTIONS
Table C-2 lists the x87 FPU instructions in alphabetical orde r. For each instruction, it summarizes the floating-point 
exceptions that the instruction can generate.Table C-1.  x87 FPU and SIMD  Floating-Point Exceptions
Floating-
point 
Exception Description
#IS Invalid-operation exception for stack underflow or stack overflow (can only be generated for x87 FPU instructions)*
#IA or #I Invalid-operation exception for invalid arithmetic operands and unsupported formats*
#D Denormal-operand exception
#Z Divide-by-zero exception#
O Numeric-overflow exception
#U Numeric-underflow exception
#P Inexact-result (precision) exceptionNOTE:
* The x87 FPU instruction set generates two types of invalid-operation exceptions: #IS (stack underflow or stack overflow) and # IA
(invalid arithmetic operation due to invalid arithmetic operands  or unsupported formats). Intel SSE, SSE2, and SSE3 instruction s
potentially generate #I (invalid operation exceptions due to invalid arithmetic operands or unsupported formats).
Table C-2.  Exceptions Generated with x87 FPU Floating-Point Instructions
Mnemonic Instruction #IS #IA #D #Z #O #U #P
F2XM1 Exponential Y Y Y Y Y
FABS Absolute value Y

Floating-
point 
FADD(P) Add floating-point Y Y Y Y Y YFBLD BCD load YC-2 Vol. 1FLOATING-POINT EXCEPTIONS SUMMARY
FBSTP BCD store and pop Y Y Y
FCHS Change sign Y
FCLEX Clear exceptions
FCMOV cc Floating-point conditional move Y
FCOM, FCOMP, FCOMPP Compare floating-point Y Y Y
FCOMI, FCOMIP, FUCOMI, 
FUCOMIPCompare floating-point and set EFLAGS Y Y Y
FCOS Cosine Y Y Y Y
FDECSTP Decrement stack pointerF D I V ( R ) ( P ) D i v i d e  f l o a t i n g - p o i n t YY YYYYYFFREE Free register
FIADD Integer add Y Y Y Y Y Y
FICOM(P) Integer compare Y Y YFIDIV Integer divide Y Y Y Y Y Y
F I D I V R I n t e g e r  d i v i d e  r e v e r s e d YY YYYYY
FILD Integer load YFIMUL Integer multiply Y Y Y Y Y Y
FINCSTP Increment stack pointer
FINIT Initialize processorFIST(P) Integer store Y Y Y
FISTTP Truncate to integer 
(SSE3 instruction)YY Y
F I S U B ( R ) I n t e g e r  s u b t r a c t YY Y YYY
FLD extended or stack Load floating-point YFLD single or double Load floating-point Y Y Y
FLD1 Load + 1.0 Y
F L D C W L o a d  C o n t r o l  w o r d YY YYYYYF L D E N V L o a d  e n v i r o n m e n t YY YYYYY
2eY
FLDL2T Load log210 Y
FLDLG2 Load log102Y
FLDLN2 Load loge2Y
FLDPI Load π Y
FLDZ Load + 0.0 Y
FMUL(P) Multiply floating-point Y Y Y Y Y Y
FNOP No operationFPATAN Partial arctangent Y Y Y Y Y
FPREM Partial remainder Y Y Y Y
FPREM1 IEEE partial remainder Y Y Y YTable C-2.  Exceptions Generated with x8 7 FPU Floating-Point Instructions (Contd.)
Mnemonic Instruction #IS #IA #D #Z #O #U #PVol. 1 C-3FLOATING-POINT EXCEPTIONS SUMMARY
C.3 INTEL® SSE INSTRUCTIONS
Table C-3 lists the Intel SSE instructions with at least one of the following characteristics:
•Has floating-point operands.
•Generates floating-point results.
•Reads or writes floating-point status and control information.
The table also summarizes the floating-point exceptions that each instruction can generate.F P T A N P a r t i a l  t a n g e n t YYY Y Y
FRNDINT Round to integer Y Y Y Y
F R S T O R R e s t o r e  s t a t e Y Y YYYYY
FSAVE Save stateFSCALE Scale Y Y Y Y Y Y
FSIN Sine Y Y Y Y Y
F S I N C O S S i n e  a n d  c o s i n e YYY Y YFSQRT Square root Y Y Y Y
FST(P) stack or extended Store floating-point Y
FST(P) single or double Store floating-point Y Y Y Y YFSTCW Store control wordFSTENV Store environment
FSTSW (AX) Store status word
FSUB(R)(P) Subtract floating-point Y Y Y Y Y YF T S T T e s t YYY
FUCOM(P)(P) Unordered compare floating-point Y Y Y
FWAIT CPU WaitFXAM Examine
FXCH Exchange registers Y
FXTRACT Extract Y Y Y YF Y L 2 X L o g a r i t h m Y Y YYYYY
F Y L 2 X P 1 L o g a r i t h m  e p s i l o n YYY Y Y Y
Table C-3.  Exceptions Generate d with Intel® SSE Instructions
Mnemonic Instruction #I #D #Z #O #U #P
A D D P S P a c k e d  a d d . YY YYYA D D S S S c a l a r  a d d . YY YYY
ANDNPS Packed logical INVERT and AND.
ANDPS Packed logical AND.CMPPS Packed compare. Y Y
CMPSS Scalar compare. Y YTable C-2.  Exceptions Generated with x87 FPU Floating-Point Instructions (Contd.)
Mnemonic Instruction #IS #IA #D #Z #O #U #PC-4 Vol. 1FLOATING-POINT EXCEPTIONS SUMMARY
COMISS Scalar ordered compare lower SP FP numbers and set the status 
flags.YY
CVTPI2PS Convert two 32-bit signed integers from MM2/Mem to two SP FP. Y
CVTPS2PI Convert lower two SP FP from XMM/Mem to two 32-bit signed 
integers in MM using rounding specified by MXCSR.YY
CVTSI2SS Convert one 32-bit signed in teger from Integer Reg/Mem to one 
SP FP.Y
CVTSS2SI Convert one SP FP from XMM/Mem to one 32-bit signed integer 
using rounding mode specified by MXCSR, and move the result to an integer register. YY
CVTTPS2PI Convert two SP FP from XMM2/Mem to two 32-bit signed 
integers in MM1 using truncate.YY
CVTTSS2SI Convert lowest SP FP fr om XMM/Mem to one 32-bit signed 
integer using truncate, and move the result to an integer register. YY
D I V P S P a c k e d  d i v i d e . YYYYYY
D I V S S S c a l a r  d i v i d e . YYYYYYLDMXCSR Load control/status word.
MAXPS Packed maximum. Y Y
MAXSS Scalar maximum. Y YMINPS Packed minimum. Y Y
MINSS Scalar minimum. Y Y
MOVAPS Move four packed SP values.MOVHLPS Move packed SP high to low.
MOVHPS Move two packed SP values between memory and the high half of 
an XMM register.
MOVLHPS Move packed SP low to high.
MOVLPS Move two packed SP values be tween memory and the low half of 
MOVMSKPS Move sign  mask to r32.
MOVSS Move scalar SP number between an XMM register and memory or 
a second XMM register.
MOVUPS Move unaligned packed data.
MULPS Packed multiply. Y Y Y Y Y
MULSS Scalar multiply. Y Y Y Y YORPS Packed OR.
RCPPS Packed reciprocal.
RCPSS Scalar reciprocal.RSQRTPS Packed reciprocal square root.
RSQRTSS Scalar reciprocal square root.
SHUFPS Shuffle.SQRTPS Square Root of the packed SP FP numbers. Y Y Y
SQRTSS Scalar square root. Y Y YTable C-3.  Exceptions Generated wi th Intel® SSE Inst ructions (Contd.)
Mnemonic Instruction #I #D #Z #O #U #PVol. 1 C-5FLOATING-POINT EXCEPTIONS SUMMARY
C.4 INTEL® SSE2 INSTRUCTIONS
Table C-4 lists the Intel SSE2 instructions with at least one of the following characteristics:
•Floating-point operands.
•Floating-point results.
For each instruction, the table summarizes the floating -point exceptions that the instruction can generate.STMXCSR Store control/status word.
SUBPS Packed subtract. Y Y Y Y Y
SUBSS Scalar subtract. Y Y Y Y Y
UCOMISS Unordered compare lower SP FP numbers and set the status flags. Y YUNPCKHPS Interleave SP FP numbers.
UNPCKLPS Interleave SP FP numbers.
XORPS Packed XOR.
Table C-4.  Exceptions Generate d with Intel® SSE2 Instructions
Instruction Description #I #D #Z #O #U #P
ADDPD Add two packed DP FP numb ers from XMM2/Mem to XMM1. Y Y Y Y Y
ADDSD Add the lower DP  FP number from XM M 2 / M e m  t o  X M M 1 . YY YYY
ANDNPD Invert the 128 bits in XMM1  and then AND the result with 128 
bits from XMM2/Mem.
ANDPD Logical And of 128 bits fr om XMM2/Mem to XMM1 register.
CMPPD Compare packed DP FP numbers from XMM2/Mem to packed DP 
FP numbers in XMM1 register using imm8 as predicate.YY
CMPSD Compare lowest DP FP number from XMM2/Mem to lowest DP FP 
number in XMM1 register using imm8 as predicate.YY
COMISD Compare lower DP FP number in XMM1 register with lower DP FP 
number in XMM2/Mem and set the status flags accordinglyYY
CVTDQ2PS Convert four 32-bit signed integers from XMM/Mem to four SP FP. Y
CVTPS2DQ Convert four SP FP from XMM/ Mem to four 32-bit signed integers 
in XMM using rounding specified by MXCSR.YY
CVTTPS2DQ Convert four SP FP from XMM/ Mem to four 32-bit signed integers 
in XMM using truncate.YY
CVTDQ2PD Convert two 32-bit signed inte gers in XMM2/Mem to 2 DP FP in 
xmm1 using rounding specified by MXCSR.
CVTPD2DQ Convert two DP FP from XMM2/Mem to two 32-bit signed 
integers in xmm1 using rounding specified by MXCSR.YY
CVTPD2PI Convert lower two DP FP from XMM/Mem to two 32-bit signed 
CVTPD2PS Convert two DP FP to two SP FP. Y Y Y Y Y
CVTPI2PD Convert two 32-bit signed integers from MM2/Mem to two DP FP.  
CVTPS2PD Convert two SP FP to two DP FP. Y YTable C-3.  Exceptions Generated with Intel® SSE Instructions (Contd.)
Mnemonic Instruction #I #D #Z #O #U #PC-6 Vol. 1FLOATING-POINT EXCEPTIONS SUMMARY
CVTSD2SI Convert one DP FP from XMM/Mem to one 32 bit signed integer 
using rounding mode specified by MXCSR, and move the result to 
an integer register. YY
CVTSD2SS Convert scalar DP FP to scalar SP FP. Y Y Y Y Y
CVTSI2SD Convert one 32-bit signed integer from Integer Reg/Mem to one 
DP FP. 
CVTSS2SD Convert scalar SP FP to scalar DP FP. Y Y
CVTTPD2DQ Convert two DP FP from XMM2/Mem to two 32-bit signed 
integers in XMM1 using truncate.YY
CVTTPD2PI Convert two DP FP from XMM2/Mem to two 32-bit signed 
CVTTSD2SI Convert lowest DP FP from XMM/Mem to one 32 bit signed 
integer using truncate, and move th e result to an integer register. YY
D I V P D D i v i d e  p a c k e d  D P  F P  n u m b e r s  i n  X M M 1  b y  X M M 2 / M e m YYYYYY
D I V S D D i v i d e  l o w e r  D P  F P  n u m b e r s  i n  X M M 1  b y  X M M 2 / M e m YYYYYY
MAXPD Return the maximum DP FP numbers between XMM2/Mem and 
XMM1.YY
MAXSD Return the maximum DP FP number between the lower DP FP 
numbers from XMM2/Mem and XMM1.YY
MINPD Return the minimum DP numbers between XMM2/Mem and 
XMM1.YY
MINSD Return the minimum DP FP number between the lowest DP FP 
MOVAPD Move 128 bits representing 2 packed DP data from XMM2/Mem to 
XMM1 register.
Or Move 128 bits representing 2 packed DP from XMM1 register 
to XMM2/Mem.
MOVHPD Move 64 bits representing one DP operand from Mem to upper 
field of XMM register.
Or move 64 bits representing one DP operand from upper field of 
XMM register to Mem.
MOVLPD Move 64 bits representing one DP operand from Mem to lower 
Or move 64 bits representing one DP operand from lower field of 
MOVMSKPD Move the si gn mask to r32.

XMM1.YY
XMM1.YY
MOVMSKPD Move the si gn mask to r32. 
MOVSD Move 64 bits representing one scalar DP operand from 
XMM2/Mem to XMM1 register.
Or move 64 bits representing on e scalar DP operand from XMM1 
register to XMM2/Mem.
MOVUPD Move 128 bits representing 2 DP data from XMM2/Mem to XMM1 
register.
Or move 128 bits repr esenting 2 DP data from XMM1 register to 
XMM2/Mem.
MULPD  Multiply packed DP FP num bers in XMM2/Mem to XMM1. Y Y Y Y YTable C-4.  Exceptions Generated with  Intel® SSE2 Inst ructions (Contd.)
Instruction Description #I #D #Z #O #U #PVol. 1 C-7FLOATING-POINT EXCEPTIONS SUMMARY
C.5 INTEL® SSE3 INSTRUCTIONS 
Table C-5 lists the Intel SSE3 instructions that have at least one of the following characteristics:
For each instruction, the table summarizes the floating -point exceptions that the instruction can generate.
Other Intel SSE3 instructions do not generate floating-point exceptions.
C.6 SSSE3 INSTRUCTIONS 
SSSE3 instructions operate on integer data elements . They do not generate floating-point exceptions.
C.7 INTEL® SSE4 INSTRUCTIONS 
Table C-6 lists the Intel SSE4.1 instructions that generate floating-point results.
For each instruction, the table summarizes the floating -point exceptions that the instruction can generate.MULSD Multiply the lowest DP FP nu mber in XMM2/Mem to XMM1. Y Y Y Y Y
ORPD OR 128 bits from XMM2 /Mem to XMM1 register.
SHUFPD Shuffle Double.
SQRTPD Square Root Packed Double Precision Y Y YSQRTSD Square Root Scaler Double Precision Y Y Y
SUBPD Subtract Packed Double Precision. Y Y Y Y Y
SUBSD Subtract Scaler Double Precision. Y Y Y Y YUCOMISD Compare lower DP FP number in XMM1 register with lower DP FP 
number in XMM2/Mem and set the status flags accordingly.YY
UNPCKHPD Interleaves DP FP numbers fr om the high halves of XMM1 and 
XMM2/Mem into XMM1 register.
UNPCKLPD Interleaves DP FP numbers from the low halves of XMM1 and 
XORPD XOR 128 bits from XM M2/Mem to XMM1 register.
Table C-5.  Exceptions Generated with Intel® SSE3 Instructions 
ADDSUBPD Add /Sub packed DP FP nu mbers from XMM2/Mem to XMM1. Y Y Y Y Y
ADDSUBPS Add /Sub packed SP FP nu mbers from XMM2/Mem to XMM1. Y Y Y Y Y
FISTTP See Table C-2. Y Y
HADDPD Add horizontally packed DP FP numbers XMM2/M em to XMM1. Y Y Y Y Y
HADDPS Add horizontally packed SP FP numbers XMM2/Mem to XMM1 Y Y Y Y Y
HSUBPD Sub horizontally packed DP FP numbers XMM2/Mem to XMM1 Y Y Y Y Y
HSUBPS Sub horizontally packed SP FP numbers XMM2/Mem to XMM1 Y Y Y Y YTable C-4.  Exceptions Generated with  Intel® SSE2 Instructions (Contd.)
Instruction Description #I #D #Z #O #U #PC-8 Vol. 1FLOATING-POINT EXCEPTIONS SUMMARY
Other Intel SSE4.1 and SSE4.2 instructions do not generate floating-point exceptions.Table C-6.  Exceptions Generated with Intel® SSE4 Instructions 
D P P D  D P  F P  d o t  p r o d u c t . YY YYY
D P P S  S P  F P  d o t  p r o d u c t . YY YYYROUNDPD Round packed DP FP va lues to integer FP values. Y Y
1
NOTES:
1. If bit 3 of immediate operand is 0.ROUNDPS Round packed SP FP values to in teger FP values. Y Y1
ROUNDSD Round scalar DP FP value to integer FP value. Y Y1
ROUNDSS Round scalar SP FP value to integer FP value. Y Y1Vol. 1 D-1APPENDIX D
GUIDELINES FOR WRITING SIMD  FLOATING-POINT EXCEPTION
HANDLERS
See Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,”  for a detailed discussion of SIMD floating-point excep-
tions.
This appendix considers only Intel SSE, SSE2, and SSE3 instructions that can generate numeric (SIMD floating-
point) exceptions, and gives an overview of the necessary  support for handling such exceptions. This appendix 
does not address instructions that do not generate floati ng-point exceptions (such as RSQRTSS, RSQRTPS, RCPSS, 
or RCPPS), any x87 instructions, or any unlisted instruction. 
For detailed information on which instructions generate num eric exceptions, and a listing of those exceptions, refer 
to Appendix C, “Floating-Point Exceptions Summary.” Non- numeric exceptions are handled in a way similar to that 
for the standard IA-32 instructions.
D.1 TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS
Just as for x87 FPU floating-point exceptions, the proce ssor takes one of two possible courses of action when an 
SSE/SSE2/SSE3 instruction raises a floating-point exception: 
•If the exception being raised is masked (by setting th e corresponding mask bit in the MXCSR to 1), then a 
default result is produced which is acceptable in most situations. No external indication of the exception is 
given, but the corresponding exception flags in the MXCSR are set and may be examined later. Note though 
that for packed operations, an exception flag that is set in the MXCSR will not tell which of the sub-operands 
caused the event to occur.
•If the exception being raised is not masked (by setti ng the corresponding mask bit in the MXCSR to 0), a 
software exception handler previously registered by th e user with operating system support will be invoked 
through the SIMD floating-point exception (#XM, exceptio n 19). This case is discussed below in Section D.2, 
“Software Exception Handling.”
D.2 SOFTWARE EXCEPTION HANDLING
The #XM handler is usually part of the system software (the operating system kernel). Note that an interrupt 
descriptor table (IDT) entry must have been previously set up for exception 19 (refer to Chapter 6, “Interrupt and 
Exception Handling,” in the Intel® 64 and IA-32 Architectures Software De veloper’s Manual, Volume 3A). Some 
compilers use specific run-time libraries to assist in floa ting-point exception handling. If any x87 FPU floating-point 
operations are going to be performed that might raise floating-point exceptions, then the exception handling 
routine must either disable all floating-point exceptions (f or example, loading a local control word with FLDCW), or 
it must be implemented as re-entrant. If this is not the case, the routine has to clear the status flags for x87 FPU exceptions or to mask all x87 FPU floating-point exceptio ns. For SIMD floating-point exceptions though, the excep-
tion flags in MXCSR do not have to be cleared, even if they remain unmasked (but they may still be cleared). Excep-
tions are in this case precise and occur immediately, and a SIMD floating-point exception status flag that is set 
when the corresponding exception is unmasked will not generate an exception.
Typical actions performed by this low-level exception handling routine are:
•Incrementing an exception counter for later display or printing.
•Printing or displaying diagnostic inform ation (e.g., the MXCS R and XMM registers).
•Aborting further execution, or using the exception pointers to build an instruction that will run without 
exception and executing it.
•Storing information about the exception in a data structur e that will be passed to a higher level user exception 
handler.D-2 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
In most cases (and this applies also to the Intel SSE,  SSE2, and SSE3 instructions), there will be three main 
components of a low-level floating-point exception handler: a prologue, a body, and an epilogue.
The prologue performs functions that must be protected from possible interruption by  higher-priority sources - 
typically saving registers and transferring diagnostic information from the processor to memory. When the critical processing has been completed, the prologue may re-enabl e interrupts to allow higher-priority interrupt handlers 
to preempt the exception handler (assuming that the in terrupt handler was called through an interrupt gate, 
meaning that the processor cleared the interrupt enable (IF)  flag in the EFLAGS register - refer to Section 6.5.1, 
“Call and Return Operation for Interrupt or Exception Handling Procedures”).
The body of the exception handler examines the diagnostic  information and makes a response that is application-
dependent. It may range from halting execution, to disp laying a message, to attempting to fix the problem and 
then proceeding with normal execution, to setting up a da ta structure, calling a higher-level user exception handler 
and continuing execution upon return from it. This latter case will be assumed in Section D.4, “SIMD Floating-Point 
Exceptions and the IEEE Standard 754,” below.
Finally, the epilogue essentially reverses the actions of the prologue, restoring the processor state so that normal 
execution can be resumed.
The following example represents a typical exception handler. To link it with Example D-2 that will follow in Section 
D.4.3, “Example SIMD Floating-Point Emulation Implementation,” assume that the body of the handler (not shown 
here in detail) passes the saved state to a routine that will examine in turn  all the sub-operands of the excepting 
instruction, invoking a user floating-point exception handler if a particular set of sub-operands raises an unmasked

instruction, invoking a user floating-point exception handler if a particular set of sub-operands raises an unmasked 
(enabled) exception, or emulating the instruction otherwise.
Example D-1.  SIMD Floating-Point Exception Handler
SIMD_FP_EXC_HANDLER PROC
;PROLOGUE
;SAVE REGISTERS THAT MIGHT BE USED BY THE EXCEPTION HANDLER    PUSH EBP ;SAVE EBP    PUSH EAX ;SAVE EAX
    ...    MOV EBP, ESP ;SAVE ESP in EBP    SUB ESP, 512 ;ALLOCATE 512 BYTES    AND ESP, 0fffffff0h ;MAKE THE ADDRESS 16-BYTE ALIGNED    FXSAVE [ESP ] ;SAVE FP, MMX, AND SIMD FP STATE
    PUSH [EBP+EFLAGS_OFFSET] ;COPY OLD EFLAGS TO STACK TOP    POPFD ;RESTORE THE INTERRUPT ENABLE FLAG IF
;TO VALUE BEFORE SIMD FP EXCEPTION
;BODY
;APPLICATION-DEPENDENT EXCEPTI ON HANDLING CODE GOES HERE
    LDMXCSR LOCAL_MXCSR ;LOAD LOCAL MXCSR VALUE IF NEEDED    ...    ...;EPILOGUE    FXRSTOR [ESP] ;RESTORE MODIFIED STATE IMAGE    MOV ESP, EBP ;DE-ALLOCATE STACK SPACE    ...    POP EAX ;RESTORE EAX    POP EBP ;RESTORE EBP    IRET ;RETURN TO INTERRUPTED CALCULATION
SIMD_FP_EXC_HANDLER ENDPVol. 1 D-3GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
D.3 EXCEPTION SYNCHRONIZATION
An SSE/SSE2/SSE3 instruction can execute in parallel with other similar instructions, with integer instructions, and 
with floating-point or MMX instructions. Unlike for x87 instructions, special precaution for exception synchroniza-
tion is not necessary in this case. This is because floa ting-point exceptions for SSE/SSE2/SSE3 instructions occur 
immediately and are not delayed until a subsequent floati ng-point instruction is ex ecuted. However, floating-
point emulation may be necessary when unmaske d floating-point exceptions are generated.
D.4 SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754
SSE/SSE2/SSE3 extensions are 100% compatible with the IEEE Standard 754 for Floating-Point Arithmetic, satis-
fying all of its mandatory requirements (when the flush-to-zero or denormals-are-zeros modes are not enabled). 
But a programming environment that includes SSE/SSE2/SSE3 instructions will comply with both the obligatory and the strongly recommended requirements of the IEEE Standard 754 regarding floating-point exception 
handling, only as a combination of hardware and software (which is acceptable). The standard states that a user 
should be able to request a trap on any of the five floa ting-point exceptions (note that the denormal exception is 
an IA-32 addition), and it also specifies the values (opera nds or result) to be delivered to the exception handler. 
The main issue is that for SSE/SSE2/SSE3 instructions th at raise post-computation exceptions (traps: overflow, 
underflow, or inexact), unlike for x87 FPU instructions, th e processor does not provide the result recommended by 
IEEE Standard 754 to the user handler. If a user program needs the result of an instruction that generated a post-
computation exception, it is the responsibility of the software to produce this result by emulating the faulting 
SSE/SSE2/SSE3 instruction. Another issue is that the standa rd does not specify explicitly how to handle multiple 
floating-point exceptions that occur simultaneously. For packed operations, a logical OR of the flags that would be set by each sub-operation is used to set the exception flags in the MXCSR. The following subsections present one 
possible way to solve these problems.
D.4.1  Floating-Point Emulation
Every operating system must provide a kernel level floati ng-point exception handler (a template was presented in 
Section D.2, “Software Exception Handling,” above). In the following discussion, assume that a user mode floating-point exception filter is supplied for SI MD floating-point exceptions (for example as part of a library of C functions), 
that a user program can invoke in order to handle unmasked exceptions. The user mode floating-point exception 
filter (not shown here) has to be able to emulate the subset of Intel SSE, SSE2, and SSE3 instructions that can generate numeric exceptions, and has to be able to invo ke a user provided floating-point exception handler for 
floating-point exceptions. When a floating-point exception th at is not masked is raised by an Intel SSE, SSE2, and 
SSE3 instruction, the low-level floating-point exception ha ndler will be called. This low-level handler may in turn 
call the user mode floating-point exception filter. The filter  function receives the original operands of the excepting 
instruction as no results are provided by the hardware, whether a pre-computation or a post-computation excep-
tion has occurred. The filter will unpack the operands into up to four sets of sub-operands, and will submit them 
one set at a time to an emulation function (See Exampl e D-2 in Section D.4.3, “Example SIMD Floating-Point 
Emulation Implementation.”) The emulation function will examine the sub-operands, and will possibly redo the 
necessary calculation. 
Two cases are possible:
•If an unmasked (enabled) exception would occur in this pr ocess, the emulation function will return to its caller 
(the filter function) with the approp riate information. The filter will invoke a (previously registered) user 
floating-point exception handler for this set of sub-oper ands, and will record the result upon return from the 
user handler (provided the user handler allows continuation of the execution). 
•If no unmasked (enabled) exception would occur, the emul ation function will determine and will return to its 
caller the result of the operation for the current set of sub-operands (it has to be IEEE Standard 754 
compliant). The filter function will record  the result (plus any new flag settings).
The user level filter function will then call the emulation function for the next set of sub-operands (if any). When 
done with all the operand sets, the partial results will be packed (if the excepting instruction has a packed floating-
point result, which is true for most SSE/SSE2/SSE3 numeric instructions) and the filter will return to the low-level 
exception handler, which in turn will return from the inte rruption, allowing execution to continue. Note that the D-4 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
instruction pointer (EIP) has to be altered to point to the instruction following the except ing instruction, in order to 
continue execution correctly.
If a user mode floating-point exception filter is not prov ided, then all the work for decoding the excepting instruc-
tion, reading its operands, emulating the instruction for the components of the result that do not correspond to unmasked floating-point exceptions, and providing the comp ounded result will have to be performed by the user-
provided floating-point exception handler.
Actual emulation might have to take place for one operand or pair of operands for scalar operations, and for all sub-
operands or pairs of sub-operands for packed op erations. The steps to perform are the following:
•The excepting instruction has to be decoded and the operands have to be read from the saved context.
•The instruction has to be emulated for each (pair of) sub-operand(s); if no floating-point exception occurs, the 
partial result has to be saved; if a masked floating-point exception occurs, the masked result has to be produced through emulation and saved, and the appropri ate status flags have to be set; if an unmasked 
floating-point exception occurs, the result has to be ge nerated by the user provided floating-point exception 
handler, and the appropriate status flags have to be set.
•The partial results have to be combin ed and written to the context that will be restored upon application 
program resumption.
A diagram of the control flow in handling an unmasked floating-point exception is presented below.
From the user-level floating-point filter, Example D-2 in  Section D.4.3, “Example SIMD Floating-Point Emulation 
Implementation,” presents only the floating-point emulatio n part. In order to understand the actions involved, the 
expected response to exceptions has to be known for a ll Intel SSE, SSE2, and SSE3 numeric instructions in two 
situations: with exceptions enabled (unmasked result), an d with exceptions disabled (masked result). The latter 
can be found in Section 6.5, “Interrupts and Exceptions.” The response to NaN operands that do not raise an excep-
tion is specified in Section 4.8.3.4, “NaNs.” Operations on  NaNs are explained in the same source. This response is 
also discussed in more detail in the next subsection, along with the unmasked and masked responses to floating-point exceptions.
D.4.2  Intel® SSE, SSE2, and SSE3 Re sponse To Floating-Point Exceptions
This subsection specifies the unmasked response expected from the Intel SSE, SSE2, and SSE3 instructions that 
raise floating-point exceptions. The masked response is given in parallel, as it is necessary in the emulation process Figure D-1.  Control Flow for Handling Unmasked Floating-Point ExceptionsUser Application
User Level Floating-Point Exception Filter Low-Level Floating-Point Exception Handler
User Floating-Point Exception HandlerVol. 1 D-5GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS

of the instructions that raise unmasked floating-point except ions. The response to NaN operands is also included in 
more detail than in Section 4.8.3.4, “NaNs.” For floating -point exception priority, refer to “Priority Among Simulta-
neous Exceptions and Interrupts” in Chapter 6, “I nterrupt and Exception Handling,” of the Intel® 64 and IA-32 
D.4.2.1  Numeric Exceptions
There are six classes of numeric (floating-point) exception conditions that can occur: Invalid operation (#I), 
Divide-by-Zero (#Z), Denormal Operand (#D), Numeric Overflow (#O), Numeric Underflow (#U), and Inexact 
Result (precision) (#P). #I, #Z, #D are pre-computation ex ceptions (floating-point faults), detected before the 
arithmetic operation. #O, #U, #P are post-com putation exceptions (floating-point traps). 
Users can control how the Intel SSE, SSE2, and SSE3 fl oating-point exceptions are handled by setting the 
mask/unmask bits in MXCSR. Masked exceptions are handled by the processor, or by software if they are combined 
with unmasked exceptions occurring in the same instruction. Unmasked exceptions are usually handled by the low-
level exception handler, in conjunction with user-level software.
D.4.2.2  Results of Operations with NaN Operands or a NaN Resu lt for Intel® SSE, SSE2, and SSE3 
Numeric Instructions
The tables below (E-1 through E-10) specify the response of  Intel SSE, SSE2, and SSE3 instructions to NaN inputs, 
or to other inputs that lead to NaN results.
These results will be referenced by subsequent tables (e.g., E-10). Most operations do not raise an invalid excep-
tion for quiet NaN operands, but even so, they will have hi gher precedence over raising floating-point exceptions 
other than invalid operation. 
Note that the single precision QNaN Indefinite value is  FFC00000H, the double precision QNaN Indefinite value is 
FFF8000000000000H, and the Integer Indefinite value is 80000000H (not a floating-point number, but it can be 
the result of a conversion instruction from floating-point to integer).
For an unmasked exception, no result will be provided by the hardware to the user handler. If a user registered 
floating-point exception handler is invo ked, it may provide a result for the ex cepting instruction, that will be used 
if execution of the application code is co ntinued after returning from the interruption.
In Tables D-1 through Table D-12, the specified operands  cause an invalid exception, unless the unmasked result 
is marked with “not an exception”. In this latter case, the unmasked and masked results are the same. 
Table D-1.  ADDPS, ADDSS, SUBPS, SU BSS, MULPS, MULSS, DIVPS, DIVSS, A DDPD, ADDSD, SUBPD, SUBSD, MULPD, 
MULSD, DIVPD, DIVSD, ADDSUBPS, ADDSUBPD, HADDPS, HADDPD, HSUBPS, and HSUBPD
SNaN1 op1 SNaN2 SNaN1 | 00400000H or 
SNaN1 | 0008000000000000H2None
SNaN1 op QNaN2 SNaN1 | 00400000H or
QNaN1 op SNaN2 QNaN1 None
QNaN1 op QNaN2 QNaN1 QNaN 1 (not an exception)
SNaN op real value SNaN | 00400000H or
Real value op SNaN SNaN | 00400000H or
QNaN op real value QNaN QNaN (not an exception)
Real value op QNaN QNaN QN aN (not an exception)D-6 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
Neither source operand is SNaN,
but #I is signaled (e.g., for Inf - Inf, 
Inf ∗ 0, Inf / Inf, 0/0) Single precision or double precision QNaN 
IndefiniteNone
NOTES:
1. For Tables E-1 to E-12: op denotes the operation to be performed.2. SNaN | 00400000H is a quiet NaN in single precision format (if SNaN is in single precision) and SNaN | 0008000000000000H is a
quiet NaN in double precision format (if SNaN is in double precision), obtained from the signaling NaN given as input.
3. Operations involving only quiet NaNs do not raise floating-point exceptions.
Table D-2.  CMPPS.EQ, CMPSS. EQ, CMPPS.ORD, CMPSS.ORD, 
CMPPD.EQ, CMPSD.EQ, CMPP D.ORD, and CMPSD.ORD
NaN op Opd2 (any Opd2) 00000000H or 0000000000000000H100000000H or 0000000000000000H1 
(not an exception)
Opd1 op NaN (any Opd1) 00000000H or 0000000000000000H100000000H or 0000000000000000H1 
NOTE:
1. 32-bit results are for single, and 64-bit  results for double precision operations.
Table D-3.  CMPPS.NEQ, CMP SS.NEQ, CMPPS.UNORD, CMPSS.UN ORD, CMPPD.NEQ, CMPSD.NEQ, 
CMPPD.UNORD, and CMPSD.UNORD
NaN op Opd2 (any Opd2) FFFFFFFFH or FFFFFFFFFFFFFFFFH1FFFFFFFFH or FFFFFFFFFFFFFFFFH1 (not 
an exception)
Opd1 op NaN (any Opd1) FFFFFFFFH or FFFFFFFFFFFFFFFFH1FFFFFFFFH or FFFFFFFFFFFFFFFFH1 (not 
NOTE: 
Table D-4.  CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPS S.LE, CMPPD.LT, CMPSD.LT , CMPPD.LE, and CMPSD.LE
NaN op Opd2 (any Opd2) 00000000H or 0000000000000000H1 None
Opd1 op NaN (any Opd1) 00000000H or 0000000000000000H1 None
NOTE:
1. 32-bit results are for single, and 64-bit results for double pr ecision operations.Table D-1.  ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVPS, DIV SS, ADDPD, ADDSD, SUBPD, SUBSD, MULPD, 
MULSD, DIVPD, DIVSD, ADDSUBPS, ADDSUBPD, HADDPS, HADDPD, HSUBPS, and HSUBPD (Contd.)
Source Operands Masked Result Unmasked ResultVol. 1 D-7GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
Table D-5.  CMPPS.NLT, CMPSS.NLT, CMPPS.NLE, CMPSS.NLE, CMPPD.NLT, CM PSD.NLT, CMPPD.NL E, and CMPSD.NLE
NaN op Opd2 (any Opd2) FFFFFFFFH or FFFFFFFFFFFFFFFFH1None
Opd1 op NaN (any Opd1) FFFFFFFFH or FFFFFFFFFFFFFFFFH1None
NOTE:
Table D-6.  COMISS and COMISD
SNaN op Opd2 (any O pd2) OF, SF, AF = 000  
ZF, PF, CF = 111None
Opd1 op SNaN (any O pd1) OF, SF, AF = 000  
QNaN op Opd2 (any Op d2) OF, SF, AF = 000 
Opd1 op QNaN (any Op d1) OF, SF, AF = 000 
Table D-7.  UCOMISS and UCOMISD
QNaN op Opd2 
(any Opd2 ≠ SNaN)OF, SF, AF = 000  
ZF, PF, CF = 111OF, SF, AF = 000  
ZF, PF, CF = 111 (not an exception)
Opd1 op QNaN 
(any Opd1 ≠ SNaN)OF, SF, AF = 000  
Table D-8.  CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, CVTPD2PI, CVTSD2SI, CVTTPD2PI, CVTTSD2SI, 
CVTPS2DQ, CVTTPS2DQ, CVTPD2DQ, and CVTTPD2DQ
Source Operand Masked Result Unmasked Result
SNaN 80000000H or 80000000000000001 
(Integer Indefinite)None
QNaN 80000000H or 80000000000000001 
NOTE: 
1. 32-bit results are for single, and 64-bit results for double precision operations.D-8 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
Table D-9.  MAXPS, MAXSS, MINPS, MI NSS, MAXPD, MAXSD, MINPD, and MINSD
Opd1 op NaN2 (any Opd1) NaN2 None
NaN1 op Opd2 (any Opd2) Opd2 None
NOTE:
1. SNaN and QNaN operands raise an Invalid Operation fault.
Table D-10.  SQRTPS, SQRTSS, SQRTPD, and SQRTSD
QNaN QNaN QNaN (not an exception)
SNaN SNaN | 00400000H or
SNaN | 0008000000000000H1None
Source operand is not SNaN;
but #I is signaled (e.g., for sqrt (-1.0))Single precision or 
double precision QNaN IndefiniteNone
NOTE:
1. SNaN | 00400000H is a quiet NaN in single precision format (i f SNaN is in single precision) and SNaN | 0008000000000000H is a  
Table D-11.  CVTPS2PD and CVTSS2SD
QNaN QNaN11QNaN11 (not an exception)
SNaN QNaN12None
NOTES:
1. The double precision output QNaN1 is created from the single precision input QNaN as follows: the sign bit is preserved, the 8-bit 
exponent FFH is replaced by the 11-bit exponent 7FFH, and the 24-bit significand is extended to a 53-bit significand by appendi ng 
29 bits equal to 0.
2. The double precision output QNaN1 is crea ted from the single precision input SNaN as  follows: the sign bit is preserved, the 8-bit
exponent FFH is replaced by the 11-bit exponent 7FFH, and the 24-bit significand is extended to a 53-bit significand by pending
29 bits equal to 0. The second most significant bit of the sign ificand is changed from 0 to 1 to convert the signaling NaN into  a
quiet NaN.
Table D-12.  CVTPD2PS and CVTSD2SS
NOTES:

NOTES:
quiet NaN.
NOTES:
1. The single precision output QNaN1 is crea ted from the double precision input QNaN as follows: the sign bit is preserved, the 11-bit 
exponent 7FFH is replaced by the 8-bit exponent FFH, and the 53- bit significand is truncated to a 24-bit significand by removin g its 
29 least significant bits.
2. The single precision output QNaN1 is created from the double precision input SNaN as follows: the sign bit is preserved, the 11-bit
exponent 7FFH is replaced by the 8-bit exponent FFH, and the 53-bit significand is truncated to a 24-bit significand by removin g its
29 least significant bits. The second most significant bit of the significand is changed from 0 to 1 to convert the signaling N aN into
a quiet NaN.Vol. 1 D-9GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
D.4.2.3  Condition Codes, Exception Flags, an d Response for Masked and Unmasked Numeric 
Exceptions
In the following, the masked response is what the proce ssor provides when a masked exception is raised by an 
Intel SSE, SSE2, or SSE3 numeric instruction. The same re sponse is provided by the floating-point emulator for 
Intel SSE, SSE2, and SSE3 numeric instructions, when certain components of the quadruple input operands 
generate exceptions that are masked (the emulator also  generates the correct answer, as specified by IEEE Stan-
dard 754 wherever applicable, in the case when no floating-point exception occurs). The unmasked response is 
what the emulator provides to the user handler for those components of the packed operands of Intel SSE, SSE2, 
and SSE3 instructions that raise unmasked exceptions. No te that for pre-computation exceptions (floating-point 
faults), no result is provided to the user handler. For po st-computation exceptions (floating-point traps), a result is 
provided to the user handler, as specified below.
In the following tables, the result is denoted by 'res', wi th the understanding that for the actual instruction, the 
destination coincides with the first source operand (e xcept for COMISS, UCOMISS, COMISD, and UCOMISD, whose 
destination is the EFLAGS register).
Table D-13.  #I - Invalid Operations 
Instruction Condition Masked ResponseUnmasked Response 
and Exception Code
ADDPS
ADDPD
ADDSS ADDSD
HADDPS
HADDPDsrc1 or src2
1 = SNaN Refer to Table D-1 for 
NaN operands, #IA = 1
src1, src2 unchanged; #IA 
= 1
ADDSUBPS (the 
addition component)ADDSUBPD (the 
addition component)src1 = +Inf, src2 = -Inf or
src1 = -Inf, src2 = +Infres
1 = QNaN Indefinite,
#IA = 1
SUBPS
SUBPD
SUBSS SUBSD
HSUBPS
HSUBPDsrc1 or src2 = SNaN Refe r to Table D-1 for NaN 
operands, #IA = 1
= 1 ADDSUBPS (the 
subtraction component)
ADDSUBPD (the 
subtraction component)src1 = +Inf, src2 = +Inf or
src1 = -Inf, src2 = -Infres = QNaN Indefinite, 
#IA = 1
MULPS
MULPDsrc1 or src2 = SNaN Re fer to Table D-1 for 
NaN operands, #IA = 1 src1, src2 unchanged; 
#IA = 1 MULSS 
MULSDsrc1 = ±Inf, src2 = ±0 or
src1 = ±0, src2 = ±Infres = QNaN Indefinite,
#IA = 1
DIVPS
DIVPDsrc1 or src2 = SNaN Re fer to Table D-1 for 
#IA = 1 DIVSS 
DIVSDsrc1 = ±Inf, src2 = ±Inf or
src1 = ±0, src2 = ±0res = QNaN Indefinite, 
#IA = 1
SQRTPS
SQRTPD
SQRTSS 
SQRTSDsrc = SNaN Refer to Table D-10 for 
NaN operands, #IA = 1src unchanged, 
#IA = 1
src < 0 
(note that -0 < 0 is false)res = QNaN Indefinite, 
#IA = 1D-10 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
MAXPS
MAXSS
MAXPDMAXSDsrc1 = NaN or src2 = NaN res = src2 , #IA = 1 src1, src2 unchanged; #IA 
= 1
MINPS
MINSS 
MINPD
MINSDsrc1 = NaN or src2 = NaN res = src2 , #IA = 1 src1, src2 unchanged; #IA 
= 1
CMPPS.LT
CMPPS.LECMPPS.NLT
CMPPS.NLE
CMPSS.LT
CMPSS.LE
CMPSS.NLTCMPSS.NLE
CMPPD.LT
CMPPD.LECMPPD.NLT
CMPPD.NLE
CMPSD.LTCMPSD.LE
CMPSD.NLT
CMPSD.NLEsrc1 = NaN or src2 = NaN Refer to Table D-4 and Table D-5 for 
NaN operands; #IA = 1src1, src2 unchanged; #IA 
= 1
COMISS     
COMISDsrc1 = NaN or src2 = NaN Refer to Table D-6 for NaN 
operandssrc1, src2, EFLAGS 
unchanged; #IA = 1
UCOMISS   
UCOMISDsrc1 = SNaN or src2 = SNaN Refer to Table D-7 for NaN 
CVTPS2PI
CVTSS2SI CVTPD2PI
CVTSD2SI
CVTPS2DQCVTPD2DQsrc = NaN, ±Inf, or
|(src)
rnd | > 7FFFFFFFH and (src)rnd ≠ 
80000000H
See Note2 for information 
on rnd.res = Integer Indefinite, 
#IA = 1src unchanged, 
#IA = 1
CVTTPS2PI
CVTTSS2SI 
CVTTPD2PI
CVTTSD2SICVTTPS2DQ
CVTTPD2DQsrc = NaN, ±Inf, or
|(src)
rz | > 7FFFFFFFH and (src)rz ≠ 
80000000H
See Note2 for information
on rz.res = Integer Indefinite, 
#IA = 1src unchanged,
#IA = 1Table D-13.  #I - Invali d Operations  (Contd.)
and Exception CodeVol. 1 D-11GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
CVTPS2PD
CVTSS2SDsrc = SNAN Refer to Table D-11 for 
NaN operandssrc unchanged, 
#IA = 1
CVTPD2PS
CVTSD2SSsrc = SNAN Refer to Table D-12 for 
#IA = 1
NOTES:
1. For Tables E-13 to E-18:
- src denotes the single source  operand of a unary operation.
- src1, src2 denote the fi rst and second source operand of a binary operation.
- res denotes the numerical result of an operation.
2. rnd signifies the user rounding mode from MXCSR, and rz signifies the rounding mode toward zero. (truncate), when rounding a
floating-point value to an integer. Fo r more information, refer to Table 4-8.
3. For NAN encodings, see Table 4-3.
Table D-14.  #Z - Divide-by-Zero
DIVPS
DIVSS
DIVPDDIVPSsrc1 = finite non-zero (normal, or 
denormal)
src2 = ±0res = ±Inf,
#ZE = 1src1, src2 unchanged; 
#ZE = 1Table D-13.  #I - Invalid Operations  (Contd.)
and Exception CodeD-12 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
Table D-15.  #D - Denormal Operand
Instruction Condition Masked ResponseUnmasked Response and 
Exception Code
ADDPS
ADDPD
ADDSUBPSADDSUBPD
HADDPS
HADDPDSUBPS
SUBPD
HSUBPSHSUBPD
MULPS
MULPDDIVPS
DIVPD
SQRTPS
SQRTPD
MAXPSMAXPD
MINPS
MINPDADDSS
ADDSD
SUBSSSUBSD
MULSS
MULSDDIVSS
DIVSD
SQRTSSSQRTSD
MAXSS
MAXSDMINSS
MINSD
CVTPS2PDCVTSS2SD
CVTPD2PS
CVTSD2SSsrc1 = denormal
1 or 
src2 = denormal (and 
the DAZ bit in MXCSR is 0)res = Result rounded to the 
destination precision and using the 
bounded exponent, but only if no unmasked post-computation 
exception occurs; 
#DE = 1.src1, src2 unchanged; 
#DE = 1
Note that SQRT, CVTPS2PD, 
CVTSS2SD, CVTPD2PS, CVTSD2SS 
have only 1 src.
CMPPS
CMPPDCMPSS
CMPSDsrc1 = denormal
1 or
src2 = denormal (andthe DAZ bit in MXCSR
is 0)Comparison result , stored in the 
destination register;#DE = 1src1, src2 unchanged;
#DE = 1
COMISS
COMISD
UCOMISSUCOMISDsrc1 = denormal
1 or
src2 = denormal (and
the DAZ bit in MXCSRis 0)Comparison result , stored in the 
EFLAGS register;
#DE = 1src1, src2 unchanged;
#DE = 1
NOTE: 
1. For denormal encodings, see Se ction 4.8.3.2, “Normalized and Denormalized Finite Numbers.”Vol. 1 D-13GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
Table D-16.  #O - Numeric Overflow
ADDPS
ADDSUBPSHADDPS
SUBPS
HSUBPSMULPS
DIVPS
ADDSSSUBSS
MULSS
DIVSSCVTPD2PS
CVTSD2SSRounded result > 
largest single precision finite 
normal value Rounding Sign Result & Status Flags
res = (result calculated with 
unbounded exponent and rounded 
to the destination precision) / 2
192
#OE = 1
#PE = 1 if the result is inexactTo 
nearest +
-#OE = 1, #PE = 1
res = res = 
Toward 
+
res = 1.11…1 * 2
127
res = 
Toward 
+
res = 
res = -1.11…1 * 2127
Toward 
0+
res = 1.11…1 * 2127
ADDPDADDSUBPDHADDPD
SUBPD
HSUBPDMULPD
DIVPD
ADDSDSUBSD
MULSD
DIVSDRounded result > 
largest double 
precision finite 
unbounded exponent and rounded to the destination precision) / 2
1536
•# O E  =  1
• #PE = 1 if the result is inexactTo 
nearest +
res = 
res = 
Toward 
+
res = 1.11…1 * 21023
res = 
Toward 
+
res = res = -1.11…1 * 2
1023
Toward 
0+
res = -1.11…1 * 21023∞+
∞–
∞–
∞–
∞+
∞+
∞+
∞–
∞–
∞–
∞+
∞+D-14 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
Table D-17.  #U - Numeric Underflow
ADDPS
ADDSUBPS
HADDPS
SUBPSHSUBPS
MULPS
DIVPSADDSS
SUBSS
MULSSDIVSS
CVTPD2PS
CVTSD2SSResult calculated with unbounded 
exponent and rounded to the 
destination precis ion < smallest 
single precision finite normal value.res = ±0, denormal, or normal
#UE = 1 and #PE = 1,
but only if the result isinexactres = (result calculated with 
to the destination precision) * 2
192
•# U E  =  1
• #PE = 1 if the result is inexact
ADDPD
ADDSUBPD
HADDPD
SUBPDHSUBPD
MULPD
DIVPDADDSD
SUBSD

nearest +
res = 
res = 
Toward 
+
res = 
Toward 
+
1023
Toward 
0+
∞–
∞–
∞–
∞+
∞+
∞+
∞–
∞–
∞–
∞+
ADDPS
ADDSUBPS
HADDPS
MULPS
SUBSS
CVTPD2PS
192
•# U E  =  1
ADDPD
ADDSUBPD
HADDPD
MULPD
SUBSD
MULSDDIVSDResult calculated with unbounded 
double precision finite normal value.res = ±0, denormal or normal
1536
•# U E  =  1
• #PE = 1 if the result is inexactVol. 1 D-15GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
D.4.3  Example SIMD Floating-Point Emulation Implementation
The sample code listed below may be considered as being pa rt of a user-level floating-point exception filter for the 
intel SSE, SSE2, and SSE3 numeric instructions. It is assu med that the filter function is invoked by a low-level 
exception handler (invoked for exception 19 when an unmas ked floating-point exception occurs), and that it oper-
ates as explained in Section D.4.1, “Floating-Point Emul ation.” The sample code does the emulation only for the 
SSE instructions for addition, subtraction, multiplication, and division. For this, it uses C code and x87 FPU opera-
tions. Operations corresponding to other Intel SSE, SSE2 , and SSE3 numeric instructions can be emulated simi-
larly. The example assumes that the emulation function receives a pointer to a data structure specifying a number 
of input parameters: the operation that caused the exceptio n, a set of sub-operands (unpacked, of type float), the Table D-18.  #P - Inex act Result (Precision)
Instruction Condition Masked Response Unmasked Response and Exception Code
ADDPS
ADDPD
ADDSUBPS
ADDSUBPDHADDPS
HADDPD
SUBPSSUBPD
HSUBPS
HSUBPDMULPS
MULPD
DIVPS
DIVPD
SQRTPSSQRTPD
CVTDQ2PS
CVTPI2PSCVTPS2PI
CVTPS2DQ
CVTPD2PICVTPD2DQ
CVTPD2PS
CVTTPS2PICVTTPD2PI
CVTTPD2DQ
CVTTPS2DQADDSS
ADDSD
MULSS
DIVSD
CVTSI2SS
CVTSS2SICVTSD2SI
CVTSD2SS
CVTTSS2SICVTTSD2SIThe result is not exactly 
representable in the 
destination format.res = Result rounded to the 
destination precision and 
using the bounded 
exponent, but only if no unmasked underflow or 
overflow conditions occur 
(this exception can occur in the presence of a masked 
underflow or overflow); #PE 
= 1.Only if no underflow/overflow condition occurred, or 
if the corresponding exceptions are masked:
• Set #OE if masked overflow and set result as 
described above for masked overflow. 
• Set #UE if masked unde rflow and set result as 
If neither underflow nor overflow, res equals the 
result rounded to the destination precision and using 
the bounded exponent set #PE = 1.D-16 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
rounding mode (the precision is always single), exceptio n masks (having the same relative bit positions as in the 
MXCSR but starting from bit 0 in an unsigned integer), and flush-to-zero and denormals-are-zeros indicators. 
The output parameters are a floating-point result (of type float), the cause of the exception (identified by constants 
not explicitly defined below), and the exception st atus flags. The corresponding C definition is:
unsigned int operation; //SSE or SSE2 operation: ADDPS, ADDSS, ...
  unsigned int operand1_uin t32; //first operand value
unsigned int operand2_uint32; //second operand value (if any)
  float result_fval; // result value (if any)
  unsigned int rounding_mode; //rounding mode  unsigned int exc_masks; //excepti on masks, in the order P,U,O,Z,D,I
  unsigned int exception_ cause; //exception cause
  unsigned int status_flag_inexact; //inexact status flag  unsigned int status_flag_underflow; //underflow status flag  unsigned int status_flag_overflow; //overflow status flag  unsigned int status_flag_divide_by_zero; 
//divide by zero status flag
  unsigned int status_flag_denormal_operand; 
//denormal operand status flag
  unsigned int status_f lag_invalid_ operation; 
//invalid operation status flag
  unsigned int ftz; // flush-to-zero flag
unsigned int daz; // denormals-are-zeros flag
} EXC_ENV;
The arithmetic operations exemplified are emulated as follows:
1. If the denormals-are-zeros mode is enabled (the DAZ bit in MXCSR is set to 1), replace all the denormal inputs 
with zeroes of the same sign (the denorm al flag is not affected by this change).
2. Perform the operation using x87 FPU instructions, with exceptions disabled, the original user rounding mode, 
and single precision. This reveals invalid, denormal, or divide-by-zero exceptions (if there are any) and stores 
the result in memory as a double precision value (w hose exponent range is large enough to look like 
“unbounded” to the result of the single precision computation).
3. If no unmasked exceptions were detected, determine if  the magnitude of the result is less than the smallest 
normal number that can be represented in single precis ion format, or greater than the largest normal number 
that can be represented in single precision format (huge). If an unmasked overflow or underflow occurs, 
calculate the scaled result that will be handed to the us er exception handler, as sp ecified by IEEE Standard 754.
4. If no exception was raised, calculate the result with a “bounded” exponent. If the result is tiny, it requires 
denormalization (shifting the significan d right while incrementing the exponent to bring it into the admissible 
range of [-126,+127] for single precision floating-point numbers).
The result obtained in step 2 cannot be used because it  might incur a double rounding error (it was rounded to 
24 bits in step 2, and might have to be rounded agai n in the denormalization process). To overcome this is, 
calculate the result as a double precision value, an d store it to memory in single precision format. 
Rounding first to 53 bits in the significand, and th en to 24 never causes a double rounding error (exact 
properties exist that state when double-rounding error occurs, but for the elementary arithmetic operations, 
the rule of thumb is that if an infinite ly precise result is rounded to 2p+1 bits and then again to p bits, the result 
is the same as when rounding directly to p bits, which means that no double-rounding error occurs).
5. If the result is inexact and the inexact exceptions are unmasked, the calculated result will be delivered to the 
user floating-point exception handler.
6. The flush-to-zero case is dealt with if the result is tiny.Vol. 1 D-17GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
7. The emulation function returns RAISE_EXCEPTION to the fi lter function if an exception has to be raised (the 
exception_cause field indicates the cause). Othe rwise, the emulation function returns DO_NOT_ 
RAISE_EXCEPTION. In the first case, the result is provid ed by the user exception handler called by the filter 
function. In the second case, it is provided by the emul ation function. The filter function has to collect all the 
partial results, and to assemble the scalar or packed result that is used if execution is to continue.
Example D-2.  SIMD Fl oating-Point Emulation
// masks for individual status word bits
#define PRECISION_MASK 20H
#define UNDERFLOW_MASK 10H
#define OVERFLOW_MASK 08H#define ZERODIVIDE_MASK 04H
#define DENORMAL_MASK 02H
#define INVALID_MASK 01H
// 32-bit constants
static unsigned ZEROF_ARRAY[] = {00000000H};
#define  ZEROF *(float *) ZEROF_ARRAY
    // +0.0static unsigned NZEROF_ARRAY[] = {80000000H};
#define  NZEROF *(float *) NZEROF_ARRAY
    // -0.0static unsigned POSINFF_ARRAY[] = {7f800000H};
#define POSINFF *(float *)POSINFF_ARRAY
    // +Infstatic unsigned NEGINFF_ARRAY[] = {ff800000H};
#define NEGINFF *(float *)NEGINFF_ARRAY
    // -Inf
// 64-bit constants
static unsigned MIN_SINGLE_NORMAL_ARRAY [] = {00000000H, 38100000H}; #define MIN_SINGLE_NORMAL *(double *)MIN_SINGLE_NORMAL_ARRAY
    // +1.0 * 2^-126
static unsigned MAX_SINGLE_NORMAL_ARRAY [] = {70000000H, 47efffffH}; #define MAX_SINGLE_NORMAL *(double *)MAX_SINGLE_NORMAL_ARRAY    // +1.1...1*2^127
static unsigned TWO_TO_192_ARRAY[] = {00000000H, 4bf00000H};
#define TWO_TO_192 *(double *)TWO_TO_192_ARRAY    // +1.0 * 2^192
static unsigned TWO_TO_M192_ARRAY[] = {00000000H, 33f00000H};
#define TWO_TO_M192 *(double *)TWO_TO_M192_ARRAY    // +1.0 * 2^-192
// auxiliary functions
static int isnanf (unsigned int ); // returns 1 if f is a NaN, and 0 otherwise
static float quietf (unsigned int ); // converts a signaling NaN to a quiet 
// NaN, and leaves a quiet NaN unchanged
static unsigned int check_for_daz (unsigned int ); // converts denormals 
// to zeros of the same sign; 
// does not affect any status flags
// emulation of SSE and SSE2 instructions using
// C code and x87 FPU instructions
unsigned int
simd_fp_emulate (EXC_ENV *exc_env)
{
  int uiopd1; // first operand of the add, subtract, multiply, or divide
  int uiopd2; // second operand of the add, subtract, multiply, or divide

{
  float res; // result of the add, subtract, multiply, or divide  double dbl_res24; // result with 24-bit significand, but "unbounded" exponentD-18 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
      // (needed to check tininess, to provide a scaled result to
      // an underflow/overflow trap handler, and in flush-to-zero mode)
  double dbl_res;  // result in double precision format (needed to avoid a     // double rounding error when denormalizing)
  unsigned int result_tiny;
  unsigned int result_huge;  unsigned short int sw; // 16 bits
  unsigned short int cw; // 16 bits
  // have to check first for faults (V, D, Z), and then for traps (O, U, I)
  // initialize x87 FPU (floating-point exceptions are masked)
  _asm {
    fninit;  }
  result_tiny = 0;
  result_huge = 0;
  switch (exc_env->operation) {    case ADDPS:
    case ADDSS:    case SUBPS:
    case SUBSS:
    case MULPS:    case MULSS:
    case DIVPS:
    case DIVSS:
      uiopd1 = exc_env->operand1_uint32; // copy as unsigned int
// do not copy as float to avoid conversion // of SNaN to QNaN by compiled code
      uiopd2 = exc_env->operand2_uint32;
// do not copy as float to avoid conversion of SNaN // to QNaN by compiled code
uiopd1 = check_for_daz (uiopd1); // operand1 = +0.0 * operand1 if it is 
// denormal and DAZ=1
      uiopd2 = check_for_daz (uiopd2); // operand2 = +0.0 * operand2 if it is 
      // execute the operation and check whether the invalid, denormal, or 
      // divide by zero flags are set and the respective exceptions enabled
      // set control word with rounding mode set to exc_env->rounding_mode, 
      // single precision, and all exceptions disabled
      switch (exc_env->rounding_mode) {
        case ROUND_TO_NEAREST:          cw = 003fH; // round to nearest, single precision, exceptions masked
          break;
        case ROUND_DOWN:          cw = 043fH; // round down, single precision, exceptions masked
          break;
        case ROUND_UP:          cw = 083fH; // round up, single precision, exceptions masked
          break;
        case ROUND_TO_ZERO:          cw = 0c3fH; // round to zero, single precision, exceptions masked
          break;
        default:          ; 
      }
      __asm {        fldcw WORD PTR cw;Vol. 1 D-19GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
      }
      // compute result and round to the destination precision, with
      // "unbounded" exponent (first IEEE rounding)
      switch (exc_env->operation) {
        case ADDPS:
        case ADDSS:
          // perform the addition          __asm {
            fnclex; 
            // load input operands            fld DWORD PTR uiopd1; // may set denormal or invalid status flags
            fld DWORD PTR uiopd2; // may set denormal or invalid status flags
            faddp st(1), st(0); // may set inexact or invalid status flags            // store result
            fstp  QWORD PTR dbl_res24; // exact
          }          break;
        case SUBPS:
        case SUBSS:
          // perform the subtraction
          __asm {            fnclex; 
            // load input operands
            fld DWORD PTR uiopd1; // may set denormal or invalid status flags            fld DWORD PTR uiopd2; // may set denormal or invalid status flags
            fsubp st(1), st(0); // may set the inexact or invalid status flags
            
// store result
          }          break;
        case MULPS:
        case MULSS:
          // perform the multiplication
          __asm {            fnclex;             // load input operands
            fld DWORD PTR uiopd1; // may set denormal or invalid status flags
            fld DWORD PTR uiopd2; // may set denormal or invalid status flags            fmulp st(1), st(0); // may set inexact or invalid status flags
            
          }
          break;
        case DIVPS:
        case DIVSS:          // perform the division
          __asm {
            fnclex;             // load input operands
            fld DWORD PTR uiopd2; // may set denormal or invalid status flags            fdivp st(1), st(0); // may set the inexact, divide by zero, or 
                                // invalid status flags
            // store result            fstp  QWORD PTR dbl_res24; // exact
          }
          break;D-20 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
        default:
          ; // will never occur
      }
      // read status word
      __asm {
        fstsw WORD PTR sw;
}
if (sw & ZERODIVIDE_MASK)
sw = sw & ~DENORMAL_MASK; // clear D flag for (denormal / 0)
      // if invalid flag is set, and invalid exceptions are enabled, take trap
      if (!(exc_env->exc_masks & INVALID_MASK) && (sw & INVALID_MASK)) {        exc_env->status_flag_invalid_operation = 1;
        exc_env->exception_cause = INVALID_OPERATION;
        return (RAISE_EXCEPTION);      }
// checking for NaN operands has priority over denormal exceptions; 
// also fix for the SSE and SSE2 
// differences in treating two NaN inputs between the
// instructions and other IA-32 instructionsif (isnanf (uiopd1) || isnanf (uiopd2)) {
        if (isnanf (uiopd1) && isnanf (uiopd2))
            exc_env->result_fval = quietf (uiopd1);
        else
            exc_env->result_fval = (float)dbl_res24; // exact 
        if (sw & INVALID_MASK) exc_env->status_flag_invalid_operation = 1;
        return (DO_NOT_RAISE_EXCEPTION);      }
      // if denormal flag set, and denormal exceptions are enabled, take trap
      if (!(exc_env->exc_masks & DENORMAL_MASK) && (sw & DENORMAL_MASK)) {
        exc_env->status_flag_denormal_operand = 1;
        exc_env->exception_cause = DENORMAL_OPERAND;        return (RAISE_EXCEPTION);      }
      // if divide by zero flag set, and divide by zero exceptions are 
      // enabled, take trap (for divide only)
      if (!(exc_env->exc_masks & ZERODIVIDE_MASK) && (sw & ZERODIVIDE_MASK)) {
        exc_env->status_flag_divide_by_zero = 1;        exc_env->exception_cause = DIVIDE_BY_ZERO;
        return (RAISE_EXCEPTION);
      }
      // done if the result is a NaN (QNaN Indefinite)
      res = (float)dbl_res24;      if (isnanf (*(unsigned int *)&res)) {
        exc_env->result_fval = res; // exact
        exc_env->status_flag_invalid_operation = 1;        return (DO_NOT_RAISE_EXCEPTION);
      }
      // dbl_res24 is not a NaN at this point
      if (sw & DENORMAL_MASK) exc_env->status_flag_denormal_operand = 1;      // Note: (dbl_res24 == 0.0 && sw & PRECISION_MASK) cannot occur
      if (-MIN_SINGLE_NORMAL < dbl_res24 && dbl_res24 < 0.0 ||            0.0 < dbl_res24 && dbl_res24 < MIN_SINGLE_NORMAL) {Vol. 1 D-21GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
        result_tiny = 1;
      }
      // check if the result is huge
      if (NEGINFF < dbl_res24 && dbl_res24 < -MAX_SINGLE_NORMAL || 
          MAX_SINGLE_NORMAL < dbl_res24 && dbl_res24 < POSINFF) {         result_huge = 1;
      }
      // at this point, there are no enabled I,D, or Z exceptions 
 // to take; the instr.
      // might lead to an enabled underflow, enabled underflow and inexact,       // enabled overflow, enabled overflow and inexact, enabled inexact, or
      // none of these; if there are no U or O enabled exceptions, re-execute
      // the instruction using IA-32 double precision format, and the       // user's rounding mode; exceptions must have 
// been disabled before calling
      // this function; an inexact exception may be reported on the 53-bit      // fsubp, fmulp, or on both the 53-bit and 24-bit conversions, while an 
      // overflow or underflow (with traps disabled) may be reported on the 
      // conversion from dbl_res to res
// check whether there is an underflow, overflow,
 // or inexact trap to be taken
// if the underflow traps are enabled and the result is 
// tiny, take underflow trap
      if (!(exc_env->exc_masks & UNDERFLOW_MASK) && result_tiny) {
        dbl_res24 = TWO_TO_192 * dbl_res24; // exact
        exc_env->status_flag_underflow = 1;        exc_env->exception_cause = UNDERFLOW;
        exc_env->result_fval = (float)dbl_res24; // exact
        if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;        return (RAISE_EXCEPTION);
      } 
      // if overflow traps are enabled and the result is huge, take
      // overflow trap
      if (!(exc_env->exc_masks & OVERFLOW_MASK) &&  result_huge) {        dbl_res24 = TWO_TO_M192 * dbl_res24; // exact        exc_env->status_flag_overflow = 1;
        exc_env->exception_cause = OVERFLOW;
        exc_env->result_fval = (float)dbl_res24; // exact         if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;
      } 
      // set control word with rounding mode set to exc_env->rounding_mode,

      } 
      } 
      // double precision, and all exceptions disabled      cw = cw | 0200H; // set precision to double
      __asm {
        fldcw WORD PTR cw;      }
      switch (exc_env->operation) {        case ADDPS:
        case ADDSS:          // perform the addition
          __asm {
            // load input operands            fld DWORD PTR uiopd1; // may set the denormal status flag
            fld DWORD PTR uiopd2; // may set the denormal status flag
            faddp st(1), st(0); // rounded to 53 bits, may set the inexact                                 // status flagD-22 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
            // store result
            fstp  QWORD PTR dbl_res; // exact, will not set any flag
          }          break;
          __asm {            // load input operands
            fld DWORD PTR uiopd1; // may set the denormal status flag
            fld DWORD PTR uiopd2; // may set the denormal status flag            fsubp st(1), st(0); // rounded to 53 bits, may set the inexact
                                // status flag
            // store result            fstp  QWORD PTR dbl_res; // exact, will not set any flag
          }
          break;
        case MULSS:          // perform the multiplication
          __asm {
            fmulp st(1), st(0); // rounded to 53 bits, exact
          }          break;
        case DIVSS:
          // perform the division
            fld DWORD PTR uiopd2; // may set the denormal status flag            fdivp st(1), st(0); // rounded to 53 bits, may set the inexact
// status flag
            fstp  QWORD PTR dbl_res; // exact, will not set any flag          }
          break;
        default:
      }
      // calculate result for the case an inexact trap has to be taken, or
      // when no trap occurs (second IEEE rounding)
      res = (float)dbl_res; 
          // may set P, U or O; may also involve denormalizing the result
      __asm {        fstsw WORD PTR sw;
      }
      // if inexact traps are enabled and result is inexact, take inexact trap
      if (!(exc_env->exc_masks & PRECISION_MASK) && 
          ((sw & PRECISION_MASK) || (exc_env->ftz && result_tiny))) {        exc_env->status_flag_inexact = 1;Vol. 1 D-23GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
        exc_env->exception_cause = INEXACT;
        if (result_tiny) {
          exc_env->status_flag_underflow = 1;
          // if ftz = 1 and result is tiny, result = 0.0
          // (no need to check for underflow traps disabled: result tiny and          // underflow traps enabled would have caused taking an underflow
          // trap above)
          if (exc_env->ftz) {            if (res > 0.0)
              res = ZEROF;
            else if (res < 0.0)              res = NZEROF;
            // else leave res unchanged
          }        }
        if (result_huge) exc_env->status_flag_overflow = 1;
        exc_env->result_fval = res;         return (RAISE_EXCEPTION);
      } 
      // if it got here, then there is no trap to be taken; the following must
      // hold: ((the MXCSR U exceptions are disabled  or
      //      // the MXCSR underflow exceptions are enabled and the underflow flag is
      // clear and (the inexact flag is set or the inexact flag is clear and
      // the 24-bit result with unbounded exponent is not tiny)))      // and (the MXCSR overflow traps are disabled or the overflow flag is
      // clear) and (the MXCSR inexact traps are disabled or the inexact flag
      // is clear)      //
      // in this case, the result has to be delivered (the status flags are 
      // sticky, so they are all set correctly already)
      // read status word to see if result is inexact
      }
       if (sw & UNDERFLOW_MASK) exc_env->status_flag_underflow = 1;      if (sw & OVERFLOW_MASK) exc_env->status_flag_overflow = 1;
      if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;
      // if ftz = 1, and result is tiny (underflow traps must be disabled),
      // result = 0.0
      if (exc_env->ftz && result_tiny) {        if (res > 0.0)
          res = ZEROF;
        else if (res < 0.0)          res = NZEROF;
        // else leave res unchanged
        exc_env->status_flag_inexact = 1;
        exc_env->status_flag_underflow = 1;
      }
      exc_env->result_fval = res; 
      if (sw & ZERODIVIDE_MASK) exc_env->status_flag_divide_by_zero = 1;      if (sw & DENORMAL_MASK) exc_env->status_flag_denormal= 1;
      if (sw & INVALID_MASK) exc_env->status_flag_invalid_operation = 1;
      return (DO_NOT_RAISE_EXCEPTION);
      break;
    case CMPPS:D-24 Vol. 1GUIDELINES FOR WRITING SIMD FL OATING-POINT EXCEPTION HANDLERS
    case CMPSS:
      ...      break;
    case COMISS:
    case UCOMISS:
      ...
      break;    case CVTPI2PS:
    case CVTSI2SS:
      ...
      break;
    case CVTPS2PI:
    case CVTSS2SI:
    case CVTTPS2PI:
    case CVTTSS2SI:
      ...
      break;
    case MAXPS:
    case MAXSS:
    case MINPS:
    case MINSS:
      ...
      break;
    case SQRTPS:
    case SQRTSS:
      ...
      break;
...case UNSPEC:
      ...
      break;    default:
      ...
  }
}Vol. 1 E-1APPENDIX E
INTEL® MEMORY PROTECTION EXTENSIONS
NOTE
Intel® MPX has been deprecated and will not be available on any future processors.
E.1 INTEL® MEMORY PROTECTI ON EXTENSIONS (INTEL® MPX)
Intel® Memory Protection Extensions (Intel® MPX) is a new capabilit y introduced into Intel Architecture. Intel
MPX can increase the robustness of software when it is used in conjunction with compiler changes to check mem-
ory references, for those references whose compile-time normal intentions are usurped at runtime due to buffer
overflow or underflow. Two of the most important goals of  Intel MPX are to provide this capability at low perfor-
mance overhead for newly compiled code, and to provid e compatibility mechanisms with legacy software com-
ponents. A direct benefit Intel MPX provides is hardenin g software against malicious attacks designed to cause
or exploit buffer overruns. This chapter describes th e software visible interfaces of this extension.
E.2 INTRODUCTION
Intel MPX is designed to allow a system (i.e., the logica l processor(s) and the OS software) to run both Intel MPX 
enabled software and legacy software (written for proc essors without Intel MPX). When executing software 
containing a mixture of Intel MPX-unaware code (legacy code) and Intel MPX-enabled code, the legacy code does 
not benefit from Intel MPX, but it also does not experience  any change in functionality or reduction in performance. 
The performance of Intel MPX-enabled code running on proc essors that do not support Intel MPX may be similar to 
the use of embedding NOPs in the instruction stream.
Intel MPX is designed such that an In tel MPX enabled application can link with , call into, or be called from legacy 
software (libraries, etc.) while maintaining existing applic ation binary interfaces (ABIs). And in most cases, the 
benefit of Intel MPX requires minimal changes to the source  code at the application programming interfaces (APIs) 
to legacy library/applications. As described later, Intel MPX associates bounds  with pointers in a novel manner, 
and the Intel MPX hardware uses bounds  to check that the pointer based accesses are suitably constrained. Intel 
MPX enabled software is not required to uniformly or uni versally utilize the new hardware capabilities over all 
memory references. Specifically, prog rammers can selectively use Intel MPX to protect a subset of pointers. 
The code enabled for Intel MPX benefits from memory pr otection against vulnerability such as buffer overrun. 
Therefore there is a heightened incentive for software ve ndors to adopt this technology. At the same time, the 
security benefit of Intel MPX-protection can be implem ented according to the business priorities of software 
vendors. A software vendor can choose to adopt Intel MPX in  some modules to realize partial benefit from Intel MPX 
quickly, and introduce Intel MPX in other modules in ph ases (e.g., some programmer intervention might be 
required at the interface to legacy calls). This adaptive pr operty of Intel MPX is designed to give software vendors 
control on their schedule and modularity of adoption. It also  allows a software vendor to secure defense for higher

control on their schedule and modularity of adoption. It also  allows a software vendor to secure defense for higher 
priority or more attack-prone software first; and allows the use of Intel MPX features in one phase of software engi-
neering (e.g., testing) and not in another (e.g., general release) as dictated by business realities.
The initial goal of Intel MPX is twofold: (1) provide me ans to defend a system against attacks that originate 
external to some trust perimeter where the trust perimete r subsumes the system memory  and integral data repos-
itories, and (2) provide means to pinpoint accidental logi c defects in pointer usage, by  undergirding memory refer-
ences with hardware based pointer validation. 
As with any instruction set extensions, Intel MPX can be used by application develope rs beyond detecting buffer 
overflow, the processor does not limit the use of Intel MPX for buffer overflow detection.E-2 Vol. 1INTEL® MEMORY PROTECTION EXTENSIONS
E.3 INTEL MPX PROGRAMMING ENVIRONMENT
Intel MPX introduces new bounds register s and new instructions that operate on bounds registers. Intel MPX 
allows an OS to support user mode software (operating at CPL=3) and supervisor mode software (CPL < 3) to add memory protection capability against buffer overrun. It pr ovides controls to enable Intel MPX extensions for user 
mode and supervisor mode independently. Intel MPX exte nsions are designed to allow software to associate 
bounds with pointers, and allow software to check memory  references against the bounds associated with the 
pointer to prevent out of bound memory access (thus prev enting buffer overflow).The bounds registers hold lower 
bound and upper bound that can be checked when refere ncing memory. An out-of-bounds memory reference then 
causes a #BR exception. Intel MPX also introduces configuration facilities that the OS must manage to support enabling of user-mode (and/or supervisor-mode) software operations using bounds registers.
E.3.1 Detection and Enumeration of Intel MPX Interfaces
Detection of hardware support for processor extended stat e component is provided by the main CPUID leaf func-
tion 0DH with index ECX = 0. Specific ally, the return value in EDX:EAX of  CPUID.(EAX=0DH, ECX=0) provides a 
64-bit wide bit vector of hardware support of processor state components. 
If CPUID.(EAX=07H,ECX =0H):EBX.MPX[bit 14] = 1 (the processor supports Intel MPX), 
CPUID.(EAX=0DH,ECX =0):EAX[bits 4:3] will enumerate the XSAVE stat e components associated with Intel MPX. 
These two component states of Intel MPX are the following:
•BNDREGS: CPUID.(EAX=0DH,ECX=0):EAX[3 ] indicates XCR0.BNDREGS[bit 3] is supported. This bit indicates 
bound register component of Intel MPX state, comprise d of four bounds registers, BND0-BND3 (see Appendix 
E.3.2).
•BNDCSR: CPUID.(EAX=0DH,ECX =0):EAX[4] indicates XCR0.BNDCSR[bit 4]  is supported. This bit indicates 
bounds configuration and status component of Intel MPX comprised of BNDCFGU and BNDSTATUS. OS must 
enable both BNDCSR and BNDREGS bits in XCR0 to ensure full Intel MPX support to applications.
•The size of the processor state component, enabled by XCR0.BNDREGS, is enumerated by 
CPUID.(EAX=0DH,ECX=03H).EAX[31:0] and the byte offset of this component relative to the beginning of the 
XSAVE/XRSTOR area is reported by  CPUID.(EAX=0DH, ECX=03H).EBX[31:0]. 
•The size of the processor state component, enabled by XCR0.BNDCSR, is enumerated by 
CPUID.(EAX=0DH,ECX=04H).EAX[31:0] and the byte offset of this component relative to the beginning of the 
XSAVE/XRSTOR area is reported by  CPUID.(EAX=0DH, ECX=04H).EBX[31:0]. 
On processors that support Intel MPX, CPUID.(EAX =0DH,ECX=0):EAX[3] and CPUI D.(EAX=0DH,ECX=0):EAX[4] 
will both be 1. On processors that do not su pport Intel MPX, CPUID.(E AX=0DH,ECX=0):EAX[3] and 
CPUID.(EAX=0DH,E CX=0):EAX[4] will both be 0. 
The layout of XCR0 for extended processor state components defined in Intel Architecture is shown in Figure 2-8 of 
the Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 3A.
Enabling Intel MPX requires an OS to manage bits [4:3] of XCR0; see Section 13.5.The BNDLDX and BNDSTX instructions (Appendix E.4.3) each take an operand whose bits are used to traverse data 
structures in memory. In 64-bit mode, these instructions  operate only on the lower bits in the supplied 64-bit 
addresses. The number of bits used is 48 plus a value called the MPX address-width adjust  (MAWA ). The MAWA 
value depends on CPL:
•If CPL < 3, the supervisor MAWA ( MAWAS ) is used. This value is 0.
•If CPL = 3, the user MAWA ( MAWAU ) is used. The value of MAWAU is enumerated in 
CPUID.(EAX=07H,ECX=0H):E CX.MAWAU[bits 21:17].
(Outside of 64-bit mode, BNDLDX, and BNDSTX use the en tire 32 bits of the supplied linear-address operands.)
E.3.2 Bounds Registers
Intel MPX Architecture defines four new registers, BND0 -BND3, which Intel MPX inst ructions operate on. Each 
bounds register stores a pair of 64-bit values which are th e lower bound (LB) and upper bound (UB) of a buffer, see 
Figure E-1.Vol. 1 E-3INTEL® MEMORY PROTECTION EXTENSIONS
The bounds are unsigned effective addresses, and are in clusive. The upper bounds are architecturally represented 
in 1/’s complement form. Lower bound = 0, and upper bound = 0 (1’s complement of all 1s) will allow access to the 
entire address space. The bounds are considered as IN IT when both lower and upper bounds are 0 (cover the 
entire address space). The two Intel MPX instructions which operate on the upper bound (BNDMK and BNDCU) 
account for the 1’s complement representation of the upper bounds. 
The instruction set does not impose any conventions on the use of bounds registers. Software has full flexibility 
associating pointers to bounds registers including sharing them for multiple pointers.
RESET or INIT# will initialize (write zero to) BND0–BND3.
E.3.3 Configuration and Status Registers
Intel MPX defines two configuration registers and one stat us register. The two configuration registers are defined 
for user mode (CPL = 3) and supervisor mode (CPL < 3). The user-mode configuration register BNDCFGU is acces-
sible only with the XSAVE feature set instructions. 
The supervisor mode configuration register is an MSR, referred to as IA32_BNDCFGS (MSR 0D90H). Because both 
configuration registers share a common layout (see Figure E-2), when describing the common behavior, these 
configuration registers are often denoted as BNDCFGx, wh ere x can be U or S, for user and supervisor mode 
The Enable bit in BNDCFGU enables Intel MPX in user mode  (CPL = 3), and the Enable bit in BNDCFGS enables Intel 
MPX in supervisor mode (CPL < 3). The BNDPRESERVE bit co ntrols the initialization behavior of CALL/RET/JMP/Jcc 
instructions without the BND (F 2H) prefix; see Appendix E.5.3.
WRMSR to BNDCFGS will #GP if any of the reserved bits of BNDCFGS is not zero or if th e base address of the bound 
directory is not canonical. XRSTOR of BNDCFGU ignores th e reserved bits and does not fault if any is non-zero; 
similarly, it ignores the upper bits of the base address of the bound directory and sign-extends the highest imple-
mented bit of the linear address to gu arantee the canonicality of this address.
Intel MPX also defines a status register (BNDSTATUS) pr imarily used to communicate status information for #BR 
exception. The layout of the status register is shown in Figure E-3. Figure E-1.  Layout of the Bounds Registers BND0-BND3
Figure E-2.  Common Layout of the Bound Configuration Registers BNDCFGU and BNDCFGS64 63 0 127
Upper Bound (UB) Lower Bound (LB)
12 11 0 63
Base of Bound Directory (Linear Address) Reserved (must be zero)
Bprv: BNDPRESERVEEn12
En: EnableE-4 Vol. 1INTEL® MEMORY PROTECTION EXTENSIONS
The BNDSTATUS register provides two fields to communicate the status of Intel MPX operations:
•EC (bits 1:0): The error code field communicates stat us information of a bound range exception #BR or 
operation involving bound directory. 
•ABD: (bits 63:2):The address field of a bound director y entry can provide information when operation on the 
bound directory caused a #BR.
The valid error codes are defined in Table E-1.
RESET or INIT# will set BNDCFGx and BNDSTATUS registers to zero.
E.3.4 Read and Write of IA32_BNDCFGS
The RDMSR and WRMSR instructions can be used to re ad and write the IA32_BNDCFGS MSR. (The XSAVE state 
does not include IA32_BNDCFGS, and instructions in the XS AVE feature set do not access that register). Attempts 
to write to IA32_BNDCFGS check for canonicality of the a ddresses being loaded into IA32_BNDCFGS (regardless of 
mode at the time of execution) and will #GP if the addr ess is not canonical or if reserved bits would be set.
Software can use RDMSR and WRMSR to read and write IA 32_BNDCFGS as long as the processor implements Intel 
MPX, i.e., CPUID.(EAX=07H, ECX=0H).EBX.M PX = 1. The states of CR4 and XCR0 have no impact on the ability to 
access IA32_BNDCFGS.
E.4 INTEL MPX INSTRUCTION SUMMARY
When Intel MPX is not enabled or not present, all Intel MPX instructions behave as NOP. There are eight Intel MPX 
instructions, Table E-2 provides a summary.

A C/C++ compiler can implement intrinsic support for Intel MPX instructions to facilitate pointer operation with 
capability of checking for valid bounds on pointers. Typi cally, Intel MPX intrinsics are implemented by compiler via 
inline code generation where bounds register allocati ons are handled by the comp iler without requiring the Figure E-3.  Layout of the Bound Status Registers BNDSTATUS
Table E-1.   Error Code Definition of BNDSTATUS
EC Description Meaning
00b1
NOTES:
1. When legacy BOUND instruction cause a #BR with Inte l MPX enabled (see Appendix E.5.4), EC is written with
Zero.No Intel MPX exception No exception caused by Intel MPX operations.
01b Bounds violation#BR caused by BNDCL, BNDCU or BNDCN instructions; 
ABD is 0.
10b Invalid BD entry#BR caused by BNDLDX or BNDSTX instructions, ABD will be set to the linear address of the 
invalid bound-directory entry
11b Reserved Reserved21 0 63
ABD: Address Bound Directory Entry - Linear Address
EC: Error CodeVol. 1 E-5INTEL® MEMORY PROTECTION EXTENSIONS
programmer to directly manipulate any bounds registers.  Therefore no new data type for a bounds register is 
needed in the syntax of Intel MPX intrinsics. 
E.4.1 Instruction Encoding
All Intel MPX instructions are NOP on processors that re port CPUID.(EAX=07H, ECX=0H). EBX.MPX [bit 14] = 0, or 
if Intel MPX is not enabled by the operating system (see Se ction 13.5). Applications can selectively opt-in to use 
Intel MPX instructions.
All Intel MPX opcodes encoded to operate on BND0-BND3 are valid Intel MPX instructions. All Intel MPX opcodes 
encoded to operate on bound registers beyond BND3 will #UD if Intel MPX is enabled.
BNDLDX/BNDSTX opcodes require 66H as a mandatory prefix with its operand size tied to the address size attri-
bute of the supported operating modes. Attempt to overri de operand size attribute with 66H or with REX.W in 64-
bit mode is ignored. 
E.4.2 Usage and Examples
BNDMK is typically used after memory is allocated for a buffer, e.g., by functions such as malloc, calloc, or when 
the memory is allocated on the stack. However, many other usages are possible such as when accessing an array 
member of a structure. 
BNDMOV is typically used to copy bounds from one bound register to another when a pointer is copied from one 
general purpose register to another, or to spill/fill bound s into memory corresponding to a spill/fill of a pointer. Table E-2.   Intel MPX Instruction Summary
Intel MPX 
InstructionDescription
BNDMK b, m Create LowerBound (LB) and UpperBound (UB) in the bounds register b
BNDCL b, r/m Checks the address of a memory refe rence or address in r against the lower bound 
BNDCU b, r/m Checks the address of a memory reference or a ddress in r against the upper bound in 1's complement form
BNDCN b, r/mChecks the address of a memory reference or address in r against the upper bound not in 1's complement 
form
BNDMOV b, b/m Copy/load LB and UB bounds from memory or a bounds registerBNDMOV b/m, b Store LB and UB bounds in a bounds register to memory or another register
BNDLDX b, mib Load bounds using address transl ation using an sib-addressing expression mib
BNDSTX mib, b Store bounds using address translation using an sib-addressing expression mib
Example E-1.  BNDMK Example Usag e in Application and Library Code
int A[100]; //assume the array A is a llocated on the stack at ‘offset’ 
from RBP. // the instruction to store star ting address of array will be:
                LEA RAX, [RBP+offset]// the instruction to create the bounds for array A will be:
                BNDMK BND0, [RAX+399]// Store RAX into BND0.LB, and ~(RAX+399) into BND0.UB.// similarly, for a library implementation of dynamic allocated 
memory                int * k = malloc(100);// assuming that malloc returns pointer k in RAX and holds (size 
- 1) in RCX // the malloc implementation will execute the following instruction before returning:               BNDMK BND0, [RAX+RCX] // BND0.LB stores RAX, and BND0.UB stores ~(RAX+RCX)
Example E-2.  BNDMOV Example 
Spilling or caller sa ve of bound register would use BNDMOV [RBP+ offset], BNDx. 
Assuming that the calling convention is that bound of first pointer is passed in BND0, and that bound happens to be in BND3 bef ore 
the call, the software  will add instructio n BNDMOV BND0, BND3 prior to the call.E-6 Vol. 1INTEL® MEMORY PROTECTION EXTENSIONS
BNDCL/BNDCU/BNDCN are typically used before writing to a buffer but can be used in other instances as well. If 
there are no bounds violations as a result of bound check instruction, the processor will proceed to execute the next 
instruction. However, if the bound check fails, it will signal #BR exception (fault).
Typically, the pointer used to write to memory will be compared against lower bound. However, for upper bound 
check, the software must add the (operand size - 1) to the pointer before upper bound checking.
For example, the software intend to write 32-bit integer in  64-bit mode into a buffer at address specified in RAX, 
and the bounds are in register BND0, the instruction sequence will be:
             BNDCL BND0, [RAX]             BNDCU BND0, [RAX+3] ; operand size is 4             MOV Dword ptr [RAX], RBX ; RBX has the data to be written to the buffer.
Software may move one of the two bound checks out of a l oop if it can determine that memory is accessed strictly 
in ascending or descending order. For string instructions  of the form REP MOVS, the software may choose to do 
check lower bound against first access and upper bound against last access to memory. However, if software wants 
to also check for wrap around conditions as part of address computation, it should check for both upper and lower bound for first and last instructions (total of four bound checks).
BNDSTX is used to store the bounds associated with a buff er and the “pointer value” of the pointer to that buffer 
onto a bound table entry via address translation using a two-level structure, see Appendix E.4.3.
For example, the software has a buffer with bounds stored in  BND0, the pointer to the buffer is in ESI, the following 
sequence will store the “pointer value” (the buffer) an d the bounds into a configured bound table entry using 
address translation from the linear address associated with the base of a SIB-addressing form consisting of a base 
register and a index register:
             MOV ECX, Dword ptr [ESI] ; store the pointer value in the index register ECX             MOV EAX, ESI ; store the pointer in the base register EAX             BNDSTX Dword ptr [EAX+ECX], BND0 ; pe rform address translation from the linear address of the base 
EAX and store bounds and pointer value ECX onto a bound table entry.
Similarly to retrieve a buffer and its associated bounds from a bound table entry:             MOV EAX, dword ptr [EBX] ;              BNDLDX BND0, dword ptr [EBX+EAX]; perform address translation from the linear address of the base EBX, 
and loads bounds and pointer value from a bound table entry
E.4.3 Loading and Storing Bounds in Memory
Intel MPX defines two instructions to load and store of th e linear address of a pointer to a buffer, along with the 
bounds of the buffer into a data structure of extended bounds. When storing these extended bounds, the processor 
parses the address of the pointer (where it is stored) to locate an entry in a bound table  in which to store the 
extended bounds. Loading of an extended bounds performs the reverse sequence.
The memory representation of an extended bound is a 4-tuple consisting of lower bound, upper bound, pointer 
value and a reserved field (for use by future versions of Intel MPX; software must not use this field). Accesses to 
these extended bounds use 32-bit or 64-bit operands acco rding to the current paging mode. Thus, a bound table 
entry is 4*64 bits (32 bytes) in 64-bit mode and 4*32 bits  (16 bytes) outside 64-bit mode The linear address of a 
bound table is stored in a bound-directory entry (BDE). The linear address of the bound directory  is derived from 
either BNDCFGU (CPL = 3) or BNDCFGS (CPL < 3).
The bound directory and bound tables are stored in app lication memory and are allocated by the application (in 
case of kernel use, the structures will be in kernel memory). The bound directory and each bound table are in 
contiguous linear memory.
Software should take care to allocate sufficient memory  for the bound directory and the bound tables. The amount 
of memory required depends on the current op erating mode and, in some cases, on CPL:
•In 64-bit mode:
— Each bound table comprises 217 32-byte entries thus, the size of a bo und table in 64-bit mode is 4 MBytes.Vol. 1 E-7INTEL® MEMORY PROTECTION EXTENSIONS
— The size of the bound directory depends on the valu e of MAWA. Specifically, the bound directory comprises 
228+MAWA 64-bit entries; thus, the size of a bound directory in 64-bit mode is 21+MAWAGBytes. The value 
of MAWA depends on CPL:

•If CPL < 3, the supervisor MAWA (MAWAS) is used . This value is 0. Thus, when CPL < 3, a bound 
directory comprises 228 64-bit entries and the size of a bound directory is 2 GBytes.
•If CPL = 3, the user MAWA (MAWAU) is used. The value of MAWAU is enumerated in 
CPUID.(EAX=07H,ECX=0H):E CX.MAWAU[bits 21:17]. When CPL = 3, a bound directory comprises 
228+MAWAU 64-bit entries and the size of a bound directory is 21+MAWAUGBytes.
NOTE
Software operating with CPL = 3 in 64-bit mode should use CPUID to determine the proper amount of memory to allocate for the bound directory.
•Outside 64-bit mode:
— Each bound table comprises 210 16-byte entries; thus, the size of a bound table outside 64-bit mode is 
16 KBytes.
— The bound directory comprises 220 32-bit entries; thus, the size of a bound directory outside 64-bit mode 
is 4 MBytes. This size is independent of MAWA and CPL.
Bounds in memory are associated with the memory address where the pointer is stored, i.e., Ap. A linear address 
LAp is computed by adding the appropriate segment base to Ap. (Note: for these instructions, the segment over-
ride applies only to the computation.) Appendix E.4.3. 1 and Appendix E.4.3.2 describe how BNDLDX and BNDSTX 
parse LAp to locate a bound-directory entry (BDE), which contains the address of a bound table, and then a bound-
table entry (BTE), which contains the extended bounds for the pointer. 
E.4.3.1  BNDLDX and BNDSTX in 64-Bit Mode
Figure E-4 shows the two-level structures for address translation of extended bounds in 64-bit mode.
Figure E-4.  Bound Paging Structure and Address Translat ion in 64-Bit Mode12 11 63BNDCFGU/BNDCFGS
0
20 19 63 0
Lower BoundUpper BoundPointer ValueReservedLinear Address of “pointer” (LAp)
3
0 5
021
LAp[19:3]
220 3
030+MAWA
LAp[47+MAWA:20]
31+MAWA
Bound Table Entries
Bound Table (4 MBytes)Bound Directory Entries47+MAWA
Bound Directory (21+MAWAGBytes)0 12
063
BNDCFGx[63:12]
081624
0
0Base of Bound Directory (Linear Address)
64
61E-8 Vol. 1INTEL® MEMORY PROTECTION EXTENSIONS
As noted earlier, the linear address of the bound direct ory is derived from either BNDCFGU (CPL = 3) or BNDCFGS 
(CPL < 3). In 64-bit mode, each bound-directory entry (BDE ) is 8 bytes. The number of entries in the bound direc-
tory is determined by the MPX address-width adjust (M AWA; see Appendix E.3.1). Specifically, the number of 
entries is 228+MAWA.
In 64-bit mode, the processor uses the two-level structures to access extended bounds as follows:
•A bound directory is located at the 4-KByte aligned lin ear address specified in bits 63:12 of BNDCFGx (see 
Figure E-2). A bound directory comprises 228+MAWA 64-bit entries (BDEs); thus, the size of a bound directory 
in 64-bit mode is 21+MAWAGBytes. A BDE is selected using the LAp (linear address of pointer to a buffer) to 
construct a 64-bit offset as follows:
— bits 63:31+MAWA are 0;
— bits 30+MAWA:3 are LAp[47+MAWA:20]; and— bits 2:0 are 0.
The address of the BDE is the sum of the bound-directory base address (from BNDCFGx) plus this 64-bit offset.
•Bit 0 of a BDE is a valid bit. If this bit is 0, use of the BDE by BNDLDX or BNDSTX causes #BR, sets 
BNDSTATUS[1:0] to 10b (the error code), and loads BNDSTATUS[63:2] with bits 63:2 of the linear address of 
the BDE. Otherwise, the processor uses bits 63:3 of th e BDE as the 8-byte aligned address of a bound table 
(BT); the processor ignores bits 2:1 of a BDE.
A bound table comprises 217 32-byte entries (BTEs); thus, the size of a bound table in 64-bit mode is 4 MBytes. 
A BTE is selected using the LAp (linear address of poin ter to a buffer) to construct an offset as follows:
— bits 21:5 are LAp[19:3]; and— bits 4:0 are 0.
The address of the BTE is the sum of the bound-tabl e base address (from the BDE) plus this offset.
•Each BTE comprises the following:
— a 64-bit lower bound (LB) field;
— a 64-bit upper bound (UB) field;— a 64-bit pointer value; and
— a 64-bit reserved field. This field is reserved  for future Intel MPX; software must not use it.
E.4.3.2  BNDLDX and BNDSTX Outside 64-Bit Mode
Figure E-5 shows the two-level structures for address translation of extended bounds outside 64-bit mode.
(CPL < 3). Outside 64-bit mode, each bound-directory entr y (BDE) is 4 bytes. The number of entries in the bound 
directory is 220.
Outside 64-bit mode, the processor uses the two-level structures to access extended bounds as follows:
•A bound directory is located at the 4-KByte aligned lin ear address specified in bits 31:12 of BNDCFGx (see 
Figure E-2). A bound directory comprises 220 32-bit entries (BDEs); thus, the size of a bound directory outside 
64-bit mode is 4 MBytes. A BDE is selected using the LAp (linear address of pointer to a buffer) to construct an 
offset as follows:
— bits 21:2 are LAp[31:12]; and
— bits 1:0 are 0.
The address of the BDE is the sum of the bound-directo ry base address (from BNDCFGx) plus this offset.
BNDSTATUS[1:0] to 10b (the error code), and loads BNDSTATUS[31:2] with bits 31:2 of the linear address of 
the BDE. Otherwise, the processor uses bits 31:2 of th e BDE as the 4-byte aligned address of a bound table 
(BT); the processor ignores bit 1 of a BDE.Vol. 1 E-9INTEL® MEMORY PROTECTION EXTENSIONS
A bound table comprises 210 16-byte entries (BTEs); thus, the size of  a bound table outside 64-bit mode is 
16 KBytes. A BTE is selected using the LAp (linear address of pointer to a buffer) to construct an offset as follows:
— bits 13:4 are LAp[11:2]; and— bits 3:0 are 0.
The address of the BTE is the sum of the bound-table base  address (from the BDE) plus this offset. This address 
is use as an offset into the DS segment to determine the linear address of the BTE.
— a 32-bit lower bound (LB) field;
— a 32-bit upper bound (UB) field;
— a 32-bit pointer value; and— a 32-bit reserved field. This field is reserved for future Intel MPX; software must not use it.
E.5 INTERACTIONS WITH INTEL MPX
E.5.1 Intel MPX and Operating Modes
In 64-bit Mode, all Intel MPX instructions use 64-bit op erands for bounds and 64 bit addressing, i.e., REX.W & 67H 
have no effect on data or address size. 
XSAVE, XSAVEOPT, and XRSTOR load/store 64-bit values in all modes, as these state-management instructions 
are not Intel MPX instructions.Figure E-5.  Bound Paging Structure and Address Translation Outside 64-Bit Mode12 11 31BNDCFGU/BNDCFGS
0
12 11 31 0
2
0 4
013
LAp[11:2]
140 2
021
LAp[31:12]
22
Bound Table (16 KBytes)Bound Directory Entries
Bound Directory (4 MBytes)0 12
031
BNDCFGx[31:12]
04812
0
32
30E-10 Vol. 1INTEL® MEMORY PROTECTION EXTENSIONS
In compatibility and legacy modes (including 16-bit code  segments, real and virtual 8086 modes) all Intel MPX 
instructions use 32-bit operands for bounds and 32 bit ad dressing. The upper 32-bits of destination bound register 
are cleared (consistent with behavior of integer registers)
In 32-bit and compatibility mode, the bounds are 32-bit, and are treated same as 32-bit integer registers. There-
fore, when 32-bit bound is updated in a bound register, th e upper 32-bits are undefined. When switching from 64-
bit, the behavior of content of bounds register will be similar to that of general purpose registers.
Table E-3 describes the impact of 67H pr efix on memory forms of Intel MPX inst ructions (register-only forms ignore 
67H prefix) when Intel MPX is enabled:
E.5.2 Intel® MPX Support for Pointer Operations with Branching
Intel MPX provides flexibility in supporting pointer op eration across control flow changes. Intel MPX allows 
•compatibility with legacy code that may perform pointe r operation across control flow changes and are unaware 
of Intel MPX, along with
•Intel MPX-aware code that adds bounds checking protec tion to pointer operation across control flow changes.
The interface to provide such flexibility consists of:
•Using a prefix, referred to as BND prefix, to releva nt branch instructions: CALL, RET, JMP, and Jcc.
•BNDCFGU and BNDCFGS provides the bit field, BNDPRESERVE (bit 1).
The value of BNDPRESERVE in conjunction  with the presence/absence the BND prefix with those branching instruc-
tion will determine whether the values in BN D0-BND3 will be initialized or unchanged.
E.5.3 CALL, RET, JMP, and All Jcc
An application compiled to use Intel MPX will use the REPN E (F2H) prefix (denoted by BND) for all forms of near 
CALL, near RET, near JMP, short & near Jcc instructions  (BND+CALL, BND+RET, BND+JMP, BND+Jcc). See Table E-4 
for specific opcodes. All far CALL, RET,  and JMP instructions plus short JMP (J MP rel 8, opcode EB) instructions will 
never cause bound registers to be initialized.

If BNDPRESERVE bit is one, above instructions will NOT IN IT the bounds registers when BND prefix is not present 
for above instructions (legacy behavior). However, If BNDP RESERVE is zero, above instructions will INIT ALL bound 
registers (BND0-BND3) when BND prefix is not present for above instructions. If BND prefix is present for above 
instructions, the BND registers will NOT INIT any bound registers (BND0-BND3).
The legacy code will continue to use non-prefixed forms of these instructions, so if BNDPRESERVE is zero, all the 
bound registers will INIT by legacy code. This allows the legacy function to execute and return to callee with all 
bound registers initialized (legacy code by definition cannot make or load bounds in bound registers because it does not have Intel MPX instructions). This will eliminate co mpatibility concerns when legacy function might have 
changed the pointer in registers but did not update the value of the bounds registers associated with these 
pointers. 
If BNDCFGx.BNDPRESERVE is clear then non-prefixed forms of  these instructions will initialize all the bound regis-
ters. If this bit is set then non-prefixed and prefixed form s of these instructions will preserve the contents of bound 
registers as shown in Table E-4.Table E-3.   Effective Addr ess Size of Intel® MPX Instructions with 67H Prefix
Addressing Mode 67H Prefix Effective Address Size used for Intel MPX instructions when Intel MPX is enabled
64-bit Mode Y 64 bit addressing used 64-bit Mode N 64 bit addressing used 
32-bit Mode Y #UD
32-bit Mode N 32 bit addressing used 16-bit Mode Y 32 bit addressing used 16-bit Mode N #UDVol. 1 E-11INTEL® MEMORY PROTECTION EXTENSIONS
E.5.4 BOUND Instruction and Intel MPX
If Intel MPX in enabled (see Section 13.5) and a #BR was caused due to a BOUND instruction, then BOUND instruc-
tion will write zero to the BNDSTATUS register. In all other situations, BOUND instruction will not modify BNDSTATUS. Specifically, the operation of the BOUND instruction can be described as:
IF ( ( BOUND instruction caused #BR) AND ( CR4.OXXSAVE =1 AND XCR0.BNDREGS=1 AND XCR0.BNDCSR =1) AND 
( (CPL=3 AND BNDCFGU.ENABLE = 1) OR (C PL < 3 AND BNDCFGS.ENABLE = 1) ) ) THEN
BNDSTATUS := 0; 
ELSE
BNDSTATUS is not modified;
FI;
E.5.5 Programming Considerations
Intel MPX instruction set does not dictate any calling conven tion, but allows the calling convention extensions to be 
interoperable with legacy code by making use of the of the bound registers and the bound tables to convey argu-
ments and return values. 
E.5.6 Intel MPX and System Management Mode
Upon delivery of an SMI to a processor supporting Intel MP X, the contents of IA32_BNDCFGS is saved to SMM state 
save map (at offset 7ED0H) and the register is then clea red when entering into SMM. RSM restores IA32_BNDCFGS 
from the SMM state save map. The instruction forces the reserved bits (11:2) to 0 and sign-extends the highest 
implemented bit of the linear address to guarantee the cano nicality of this address (regardless of what is in SMM 
state save map).
The content of IA32_BNDCFGS is cleared after entering in to SMM. Thus, Intel MPX is disabled inside an SMM 
handler until SMM code enables it explicitly. This will prev ent initialization of the boun d registers by execution of 
CALL, RET, JMP, or Jcc in SMM code.
E.5.7 Support of Intel MPX in VMCS
A new guest-state field for IA32_BNDCFGS is added to the VMCS. In addition, two new controls are added: 
•a VM-exit control called “clear BNDCFGS” 
•a VM-entry control called “load BNDCFGS.” Table E-4.   Bounds Register INIT Behavior  Due to BND Prefix with Branch Instructions
Instruction Branch Instruction Opcodes BNDPRESERVE = 0 BNDPRESERVE = 1
CALL E8, FF/2 Init BND0-BND3 BND0-BND3 unchanged
BND + CALL F2 E8, F2 FF/2 BND0-BND3 unchanged BND0-BND3 unchanged
RET C2, C3 Init BND0-BND3 BND0-BND3 unchanged
BND + RET F2 C2, F2 C3 BND0-BND3 unchanged BND0-BND3 unchanged
JMP E9, FF/4 Init BND0-BND3 BND0-BND3 unchanged
BND + JMP F2 E9, F2 FF/4 BND0-BND 3 unchanged BND0-BND3 unchanged
Jcc70 through 7F, 
0F 80 through 0F 8FInit BND0-BND3 BND0-BND3 unchanged
BND + JccF2 70 through F2 7F, 
F2 0F 80 through F2 0F 8FBND0-BND3 unchanged BND0-BND3 unchangedE-12 Vol. 1INTEL® MEMORY PROTECTION EXTENSIONS
VM exits always save IA32_BNDCFGS into BNDCFGS field of VMCS; if “clear BNDCFGS” is 1, VM exits clear 
IA32_BNDCFGS. If “load BNDCFGS” is 1, VM entry load s IA32_BNDCFGS from VMCS. If loading IA32_BNDCFGS, 
VM entry should check the value of that  register in the guest-state area of the VMCS and cause the VM entry to fail 
(late) if the value is one that would causes WRMSR to fault if executed in ring 0.
E.5.8 Support of Intel MPX in Intel TSX
For some processor implementations, the following Intel MPX instructions may always cause transactional aborts:
•An Intel TSX transaction abort will occur in case of lega cy branch (that causes bounds registers INIT) when at 
least one bounds register was in a NON-INIT state.
•An Intel TSX transaction abort will occur in case of a BNDLDX & BNDSTX instruction on non-flat segment.
Intel MPX Instructions (including BND prefix + branch in structions) not enumerated above as causing transactional 
abort when used inside a transaction will typically not cause an Intel TSX transaction to abort.Intel® 64 and IA-32 Architectures
Volume 2 (2A, 2B, 2C, & 2D):
Instruction Set Reference, A-Z
NOTE:  The Intel 64 and IA-32 Architec tures Software Developer's Manu al consists of four volumes:
Basic Architecture , Order Number 253665; Instruction Set Reference, A-Z , Order Number 325383;
Order Number:  325383-082US
names and brands may be claimed as the property of others.Vol. 2A iiiCONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL1.1 INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .  1-1
1.2 OVERVIEW OF VOLUME 2A, 2B, 2C, AND 2D: INSTRUCTION SET REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .  1-4
1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-5
1.3.1 Bit and Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.2 Reserved Bits and Software Compatibility  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

PAGE
CHAPTER 1
1.3.3 Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.4 Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3.5 Segmented Addressing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3.6 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3.7 A New Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-8
CHAPTER 2
INSTRUCTION FORMAT
2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE. . . . . . . . . . . . . . . . . . . .  2-1
2.1.1 Instruction Prefixes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.2 Opcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.3 ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.4 Displacement and Immediate Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2 IA-32E MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-7
2.2.1 REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1.1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.1.2 More on REX Prefix Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.1.3 Displacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.4 Direct Memory-Offset MOVs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.5 Immediates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.6 RIP-Relative Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.1.7 Default 64-Bit Operand Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.2 Additional Encodings for Control and Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3 INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.2 VEX and the LOCK prefix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.3 VEX and the 66H, F2H, and F3H prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.4 VEX and the REX prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.5 The VEX Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.5.1 VEX Byte 0, bits[7:0]  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.5.2 VEX Byte 1, bit [7] - ‘R’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.5.3 3-byte VEX byte 1, bit[6] - ‘X’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.4 3-byte VEX byte 1, bit[5] - ‘B’  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.5 3-byte VEX byte 2, bit[7] - ‘W’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.6 2-byte VEX Byte 1, bits[6:3 ] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or Dest Register Specifier. . . . . 2- 16
2.3.6 Instruction Operand Encoding and VEX.vvvv, ModR/M  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.6.1 3-byte VEX byte 1, bits[4:0] - “m-mmmm”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.6.2 2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L”  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 2-18
2.3.6.3 2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 2-19
2.3.7 The Opcode Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.8 The ModR/M, SIB, and Displacement Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.9 The Third Source Operand (Immediate Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.10 Intel® AVX Instructions and the Upper 128-bits of YMM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.10.1 Vector Length Transition and Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.11 Intel® AVX Instruction Length  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.12 Vector SIB (VSIB) Memory Addressing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.3.12.1 64-bit Mode VSIB Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.4 INTEL® ADVANCED MATRIX EXTENSIONS (INTEL® AMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.5 INTEL® AVX AND INTEL® SSE INSTRUCTION EXCEPTION CLASSIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 2-22
2.5.1 Exceptions Type 1 (Aligned Memory Reference). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.5.2 Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 2-28CONTENTS
ivVol. 2APAGE
2.5.3 Exceptions Type 3 (<16 Byte Memory Argument) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.5.4 Exceptions Type 4 (>=16 Byte Mem Arg, No Alignment, No Floating-point Exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.5.5 Exceptions Type 5 (<16 Byte Mem Arg and No FP Exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 2-31
2.5.6 Exceptions Type 6 (VEX-Encoded Instructions without Legacy SSE Analogues). . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 2-32
2.5.7 Exceptions Type 7 (No FP Exceptions, No Memory Arg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 2-33
2.5.8 Exceptions Type 8 (AVX and No Memory Argument). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.5.9 Exceptions Type 11 (VEX-only, Mem Arg, No AC, Floating-point Exceptions)  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 2-34
2.5.10 Exceptions Type 12 (VEX-only, VSIB Mem Arg, No AC, No Floating-point Exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.6 VEX ENCODING SUPPORT FOR GPR INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.6.1 Exceptions Type 13 (VEX-Encoded GPR Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.7 INTEL® AVX-512 ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.7.1 Instruction Format and EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2.7.2 Register Specifier Encoding and EVEX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.7.3 Opmask Register Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.7.4 Masking Support in EVEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.7.5 Compressed Displacement (disp8*N) Support in EVEX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
2.7.6 EVEX Encoding of Broadcast/Rounding/SAE Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.7.7 Embedded Broadcast Support in EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.7.8 Static Rounding Support in EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.7.9 SAE Support in EVEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.7.10 Vector Length Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.7.11 #UD Equations for EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
2.7.11.1 State Dependent #UD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
2.7.11.2 Opcode Independent #UD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
2.7.11.3 Opcode Dependent #UD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
2.7.12 Device Not Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
2.7.13 Scalar Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
2.8 EXCEPTION CLASSIFICATIONS OF EVEX-ENCODED INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
2.8.1 Exceptions Type E1 and E1NF of EVEX-Encoded Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 2-49
2.8.2 Exceptions Type E2 of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
2.8.3 Exceptions Type E3 and E3NF of EVEX-Encoded Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 2-52
2.8.4 Exceptions Type E4 and E4NF of EVEX-Encoded Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 2-54
2.8.5 Exceptions Type E5 and E5NF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56
2.8.6 Exceptions Type E6 and E6NF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
2.8.7 Exceptions Type E7NM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
2.8.8 Exceptions Type E9 and E9NF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
2.8.9 Exceptions Type E10 and E10NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
2.8.10 Exceptions Type E11 (EVEX-only, Mem Arg, No AC, Floating-point Exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
2.8.11 Exceptions Type E12 and E12NP (VSIB Mem Arg, No AC, No Floating-point Exceptions). . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
2.9 EXCEPTION CLASSIFICATIONS OF OPMASK INSTRUCTIONS, TYPE K20 AND TYPE K21 . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 2-68
2.9.1 Exceptions Type K20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68
2.9.2 Exceptions Type K21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
2.10 INTEL® AMX INSTRUCTION EXCEPTION CLASSES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
CHAPTER 3
INSTRUCTION SET REFERENCE, A-L

CHAPTER 3
3.1 INTERPRETING THE INSTRUCTION REFERENCE PAGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-1
3.1.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1.1 Opcode Column in the Instruction Summary Table (Instructions without VEX Prefix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.1.2 Opcode Column in the Instruction Summary Table (Instructions with VEX prefix) . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 3-3
3.1.1.3 Instruction Column in the Opcode Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.1.1.4 Operand Encoding Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.1.1.5 64/32-bit Mode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 3-8
3.1.1.6 CPUID Support Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.1.7 Description Column in the Instruction Summary Table  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.1.8 Description Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.1.9 Operation Section  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.1.10 Intel® C/C++ Compiler Intrinsics Equivalents Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.1.1.11 Flags Affected Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.1.1.12 FPU Flags Affected Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.1.1.13 Protected Mode Exceptions Section  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.1.1.14 Real-Address Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.1.1.15 Virtual-8086 Mode Exceptions Section  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.1.1.16 Floating-Point Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16Vol. 2A vCONTENTS
PAGE
3.1.1.17 SIMD Floating-Point Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.1.1.18 Compatibility Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.1.1.19 64-Bit Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.2 INTEL® AMX CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-16
3.2.1 Implementation Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.2.2 Helper Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.3 INSTRUCTIONS (A-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-18
AAA—ASCII Adjust After Addition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
AAD—ASCII Adjust AX Before Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
AAM—ASCII Adjust AX After Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
AAS—ASCII Adjust AL After Subtraction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
ADC—Add With Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
ADCX—Unsigned Integer Addition of Two Operands With Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
ADD—Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
ADDPD—Add Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
ADDPS—Add Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
ADDSD—Add Scalar Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
ADDSS—Add Scalar Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
ADDSUBPD—Packed Double Precision Floating-Point Add/Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 3-44
ADDSUBPS—Packed Single Precision Floating-Point Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 3-46
ADOX — Unsigned Integer Addition of Two Operands With Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 3-49
AESDEC—Perform One Round of an AES Decryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 3-51
AESDEC128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker Using 128-Bit Key. . . . . . . . . . . . . . . . . 3-53
AESDEC256KL—Perform 14 Rounds of AES Decryption Flow With Key Locker Using 256-Bit Key. . . . . . . . . . . . . . . . . . 3-55AESDECLAST—Perform Last Round of an AES Decryption Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 3-57
AESDECWIDE128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker on 8 Blocks Using 128-Bit Key 3-59
AESDECWIDE256KL—Perform 14 Rounds of AES Decryption Flow  With Key Locker on 8 Blocks Using 256-Bit Key . 3-61
AESENC—Perform One Round of an AES Encryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 3-63
AESENC128KL—Perform Ten Rounds of AES Encryption Flow With Key Locker Using 128-Bit Key. . . . . . . . . . . . . . . . . 3-65
AESENC256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit Key . . . . . . . . . . . . . . . . . . 3-67AESENCLAST—Perform Last Round of an AES Encryption Flow  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 3-69
AESENCWIDE128KL—Perform Ten Rounds of AES Encryption Fl ow With Key Locker on 8 Blocks Using 128-Bit Key 3-71

AESENCWIDE256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 Blocks Using 256-Bit Key . 3-73AESIMC—Perform the AES InvMixColumn Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 3-75
AESKEYGENASSIST—AES Round Key Generation Assist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
AND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
ANDN—Logical AND NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 3-81
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 3-84
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 3-87
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 3-90
ARPL—Adjust RPL Field of Segment Selector  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-93
BEXTR—Bit Field Extract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95
BLENDPD—Blend Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96
BLENDPS—Blend Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98
BLENDVPD—Variable Blend Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100
BLENDVPS—Variable Blend Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
BLSI—Extract Lowest Set Isolated Bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105
BLSMSK—Get Mask Up to Lowest Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106
BLSR—Reset Lowest Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
BNDCL—Check Lower Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108
BNDCU/BNDCN—Check Upper Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
BNDLDX—Load Extended Bounds Using Address Translation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 3-112
BNDMK—Make Bounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
BNDMOV—Move Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117
BNDSTX—Store Extended Bounds Using Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 3-120
BOUND—Check Array Index Against Bounds  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123
BSF—Bit Scan Forward  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125
BSR—Bit Scan Reverse  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127CONTENTS
viVol. 2APAGE
BSWAP—Byte Swap  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129
BT—Bit Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130
BTC—Bit Test and Complement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-132
BTR—Bit Test and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134
BTS—Bit Test and Set  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-136
BZHI—Zero High Bits Starting with Specified Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-138
CALL—Call Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-139
CBW/CWDE/CDQE—Convert Byte to Word/Con vert Word to Doubleword /Convert Doubleword to Quadword . . . . . . . 3-156
CLAC—Clear AC Flag in EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-157
CLC—Clear Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-158
CLD—Clear Direction Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-159
CLDEMOTE—Cache Line Demote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-160
CLFLUSH—Flush Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-162
CLFLUSHOPT—Flush Cache Line Optimized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-164
CLI—Clear Interrupt Flag  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-166
CLRSSBSY—Clear Busy Flag in a Supervisor Shadow Stack Token. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-168
CLTS—Clear Task-Switched Flag in CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-170
CLUI—Clear User Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-171
CLWB—Cache Line Write Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-172
CMC—Complement Carry Flag  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-174
CMOVcc—Conditional Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-175
CMP—Compare Two Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-179

CMPPD—Compare Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 3-181
CMPPS—Compare Packed Single Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 3-188
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 3-195
CMPSD—Compare Scalar Double Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 3-199
CMPSS—Compare Scalar Single Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 3-203
CMPXCHG—Compare and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-208
CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 3-210
COMISD—Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . .  . 3-213
COMISS—Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS  . . . . . . . . . . . . . . . . . . . . . .  . . 3-215
CPUID—CPU Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-217
CRC32—Accumulate CRC32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-263
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values . . . . . . . . . . . . . 3-266CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . 3-270
CVTPD2DQ—Convert Packed Double Precision Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . . 3-273
CVTPD2PI—Convert Packed Double Precision Floating-Point Values to Packed Dword Integers. . . . . . . . . . . . . . . . . . . . 3 -277
CVTPD2PS—Convert Packed Double Precision Floating-Point  Values to Packed Single Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-278
CVTPI2PD—Convert Packed Dword Integers to Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . 3 -282
CVTPI2PS—Convert Packed Dword Integers to Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . 3-283
CVTPS2DQ—Convert Packed Single Precision Floating-Point Values to Packed Signed Doubleword Integer Values . 3-284
CVTPS2PD—Convert Packed Single Precision Floating-Point Values to Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-287
CVTPS2PI—Convert Packed Single Precision Floating-Point Values to Packed Dword Integers. . . . . . . . . . . . . . . . . . . . . 3-290
CVTSD2SI—Convert Scalar Double Precision Floating-Point Value to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . . 3-291
CVTSD2SS—Convert Scalar Double Precision Floating-Point Value to Scalar Single Precision Floating-Point Value . . 3-293
CVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . 3-295
CVTSI2SS—Convert Doubleword Integer to Scalar Single Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . .  . . . . 3-297
CVTSS2SD—Convert Scalar Single Precision Floating-Point Valu e to Scalar Double Precision Floating-Point Value . . 3-299
CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . .  . . . . 3-301
CVTTPD2DQ—Convert with Truncation Packed Double Precision Floating-Point Values to Packed Doubleword 
Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-303
CVTTPD2PI—Convert With Truncati on Packed Double Precision Floating-Point Values to Packed Dword Integers . . 3-307
CVTTPS2DQ—Convert With Truncation Packed Single Precisio n Floating-Point Values to Packed Signed Doubleword 
Integer Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-308
CVTTPS2PI—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Dword Integers . . . 3-311
CVTTSD2SI—Convert With Truncation Scalar Double Precision Floating-Point Value to Signed Integer . . . . . . . . . . . . . 3-312
CVTTSS2SI—Convert With Truncation Scalar Single Precision Floating-Point Value to Integer . . . . . . . . . . . . . . . . . . . . . 3-314Vol. 2A viiCONTENTS
PAGE
CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 3-316
DAA—Decimal Adjust AL After Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-317
DAS—Decimal Adjust AL After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-319
DEC—Decrement by 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-321
DIV—Unsigned Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-323
DIVPD—Divide Packed Double Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-326
DIVPS—Divide Packed Single Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-329
DIVSD—Divide Scalar Double Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-332
DIVSS—Divide Scalar Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 3-334
DPPD—Dot Product of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-336
DPPS—Dot Product of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-338
EMMS—Empty MMX Technology State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-341
ENCODEKEY128—Encode 128-Bit Key With Key Locker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 3-342
ENCODEKEY256—Encode 256-Bit Key With Key Locker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 3-344
ENDBR32—Terminate an Indirect Branch in 32-bit and Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 3-346
ENDBR64—Terminate an Indirect Branch in 64-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-347
ENQCMD—Enqueue Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-348
ENQCMDS—Enqueue Command Supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 3-351
ENTER—Make Stack Frame for Procedure Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-354
EXTRACTPS—Extract Packed Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-357

F2XM1—Compute 2x–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-359
FABS—Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-361
FADD/FADDP/FIADD—Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-362
FBLD—Load Binary Coded Decimal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-365
FBSTP—Store BCD Integer and Pop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-367
FCHS—Change Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-369
FCLEX/FNCLEX—Clear Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-371
FCMOVcc—Floating-Point Conditional Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-373
FCOM/FCOMP/FCOMPP—Compare Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-375
FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 3-378
FCOS—Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-381
FDECSTP—Decrement Stack-Top Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-383
FDIV/FDIVP/FIDIV—Divide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-384
FDIVR/FDIVRP/FIDIVR—Reverse Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 3-387
FFREE—Free Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-390
FICOM/FICOMP—Compare Integer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-391
FILD—Load Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-393
FINCSTP—Increment Stack-Top Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-395
FINIT/FNINIT—Initialize Floating-Point Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-396
FIST/FISTP—Store Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-398
FISTTP—Store Integer With Truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-401
FLD—Load Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-403
FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 3-405
FLDCW—Load x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-407
FLDENV—Load x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 3-409
FMUL/FMULP/FIMUL—Multiply  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-411
FNOP—No Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-414
FPATAN—Partial Arctangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-415
FPREM—Partial Remainder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-417
FPREM1—Partial Remainder  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-419
FPTAN—Partial Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-421
FRNDINT—Round to Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-423
FRSTOR—Restore x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-424
FSAVE/FNSAVE—Store x87 FPU State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-426
FSCALE—Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-429
FSIN—Sine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431
FSINCOS—Sine and Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-433
FSQRT—Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-435
FST/FSTP—Store Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-437CONTENTS
viii Vol. 2APAGE
FSTCW/FNSTCW—Store x87 FPU Control Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-439
FSTENV/FNSTENV—Store x87 FPU Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 3-441
FSTSW/FNSTSW—Store x87 FPU Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-443
FSUB/FSUBP/FISUB—Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-445
FSUBR/FSUBRP/FISUBR—Reverse Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 3-448
FTST—TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-451
FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 3-453
FXAM—Examine Floating-Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-455

FXCH—Exchange Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-457
FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-459
FXSAVE—Save x87 FPU, MMX Technology, and SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-462
FXTRACT—Extract Exponent and Significand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 3-470
FYL2X—Compute y * log2x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-472
FYL2XP1—Compute y * log2(x +1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-474
GF2P8AFFINEINVQB—Galois Field Affine Transformation Inverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 3-476
GF2P8AFFINEQB—Galois Field Affine Transformation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-479
GF2P8MULB—Galois Field Multiply Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-481
HADDPD—Packed Double Precision Floating-Point Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 3-483
HADDPS—Packed Single Precision Floating-Point Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-486
HLT—Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-489
HRESET—History Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-490
HSUBPD—Packed Double Precision Floating-Point Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-492
HSUBPS—Packed Single Precision Floating-Point Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-495
IDIV—Signed Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-498
IMUL—Signed Multiply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-501
IN—Input From Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-505
INC—Increment by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-507
INCSSPD/INCSSPQ—Increment Shadow Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 3-509
INS/INSB/INSW/INSD—Input from Port to String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 3-511
INSERTPS—Insert Scalar Single Precision Floating-Point Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-514
INT n/INTO/INT3/INT1—Call to Interrupt Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 3-517
INVD—Invalidate Internal Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-532
INVLPG—Invalidate TLB Entries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-534
INVPCID—Invalidate Process-Context Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-536
IRET/IRETD/IRETQ—Interrupt Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-539
Jcc—Jump if Condition Is Met. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-548
JMP—Jump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-553
KADDW/KADDB/KADDQ/KADDD—ADD Two Masks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-562
KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 3-564
KANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 3-565
KMOVW/KMOVB/KMOVQ/KMOVD—Move From and to Mask Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-566
KNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-568
KORW/KORB/KORQ/KORD—Bitwise Logical OR Masks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-569
KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks and Set Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 3-570
KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 3-572
KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 3-574
KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-576
KUNPCKBW/KUNPCKWD/KUNPCKDQ—Unpack for Mask Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 3-578
KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 3-579
KXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 3-580
LAHF—Load Status Flags Into AH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-581
LAR—Load Access Rights Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-582
LDDQU—Load Unaligned Integer 128 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-585
LDMXCSR—Load MXCSR Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-587
LDS/LES/LFS/LGS/LSS—Load Far Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 3-588
LDTILECFG—Load Tile Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-592
LEA—Load Effective Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-595
LEAVE—High Level Procedure Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-597

LFENCE—Load Fence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-599Vol. 2A ixCONTENTS
PAGE
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-600
LLDT—Load Local Descriptor Table Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-603
LMSW—Load Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-605
LOADIWKEY—Load Internal Wrapping Key With Key Locker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-607
LOCK—Assert LOCK# Signal Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-610
LODS/LODSB/LODSW/LODSD/LODSQ—Load String  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-612
LOOP/LOOPcc—Loop According to ECX Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 3-615
LSL—Load Segment Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-618
LTR—Load Task Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-621
LZCNT—Count the Number of Leading Zero Bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 3-623
CHAPTER 4
INSTRUCTION SET REFERENCE, M-U4.1 IMM8 CONTROL BYTE OPERATION FOR PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM . . . . . . . . . . . . . . . . . . . . . . . . .  4-1
4.1.1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1.2 Source Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.3 Aggregation Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.4 Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.1.5 Output Selection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.1.6 Valid/Invalid Override of Comparisons  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.1.7 Summary of Im8 Control byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.1.8 Diagram Comparison and Aggregation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
4.2 COMMON TRANSFORMATION AND PRIMITIVE FU NCTIONS FOR SHA1XXX AND SHA256XXX . . . . . . . . . . . . . . . . . . . . . . . . . .  4-6
4.3 INSTRUCTIONS (M-U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-7
MASKMOVDQU—Store Selected Bytes of Double Quadword  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
MASKMOVQ—Store Selected Bytes of Quadword  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-10
MAXPD—Maximum of Packed Double Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
MAXPS—Maximum of Packed Single Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
MAXSD—Return Maximum Scalar Double Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
MAXSS—Return Maximum Scalar Single Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
MFENCE—Memory Fence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
MINPD—Minimum of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 4-23
MINPS—Minimum of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 4-26
MINSD—Return Minimum Scalar Double Precision Floating-Point Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 4-29
MINSS—Return Minimum Scalar Single Precision Floating-Point Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 4-31
MONITOR—Set Up Monitor Address  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
MOV—Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
MOV—Move to/from Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
MOV—Move to/from Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
MOVAPD—Move Aligned Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
MOVAPS—Move Aligned Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
MOVBE—Move Data After Swapping Bytes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
MOVD/MOVQ—Move Doubleword/Move Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
MOVDDUP—Replicate Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 4-58
MOVDIRI—Move Doubleword as Direct Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61
MOVDIR64B—Move 64 Bytes as Direct Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4-63
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 4-65
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
MOVDQ2Q—Move Quadword from XMM to MMX Technology Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-77
MOVHLPS—Move Packed Single Precision Floating-Point Values High to Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
MOVHPD—Move High Packed Double Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
MOVHPS—Move High Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 4-82

MOVLHPS—Move Packed Single Precision Floating-Point Values Low to High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
MOVLPD—Move Low Packed Double Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86
MOVLPS—Move Low Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 4-88
MOVMSKPD—Extract Packed Double Precision Floating-Point Sign Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-90
MOVMSKPS—Extract Packed Single Precision Floating-Point Sign Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92
MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
MOVNTDQ—Store Packed Integers Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 4-96
MOVNTI—Store Doubleword Using Non-Temporal Hint  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-98CONTENTS
xVol. 2APAGE
MOVNTPD—Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint  . . . . . . . . . . . . . . . . . . . . . . 4-100
MOVNTPS—Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint. . . . . . . . . . . . . . . . . . . . . . . . 4-102
MOVNTQ—Store of Quadword Using Non-Temporal Hint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 4-104
MOVQ—Move Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-105
MOVQ2DQ—Move Quadword from MMX Technology to XMM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-108
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data From String to String  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-110
MOVSD—Move or Merge Scalar Double Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114
MOVSHDUP—Replicate Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-117
MOVSLDUP—Replicate Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-120
MOVSS—Move or Merge Scalar Single Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-123
MOVSX/MOVSXD—Move With Sign-Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-126
MOVUPD—Move Unaligned Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-128
MOVUPS—Move Unaligned Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-132
MOVZX—Move With Zero-Extend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-136
MPSADBW—Compute Multiple Packed Sums of Absolute Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 4-138
MUL—Unsigned Multiply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-146
MULPD—Multiply Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-148
MULPS—Multiply Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-151
MULSD—Multiply Scalar Double Precision Floating-Point Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 4-154
MULSS—Multiply Scalar Single Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-156
MULX—Unsigned Multiply Without Affecting Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 4-158
MWAIT—Monitor Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-160
NEG—Two's Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-163
NOP—No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-165
NOT—One's Complement Negation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-166
OR—Logical Inclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-168
ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 4-170
ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 4-173
OUT—Output to Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-176
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 4-178
PABSB/PABSW/PABSD/PABSQ—Packed Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 4-182
PACKSSWB/PACKSSDW—Pack With Signed Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-188
PACKUSDW—Pack With Unsigned Saturation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 4-196
PACKUSWB—Pack With Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 4-201
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 4-206
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-213
PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-217
PALIGNR—Packed Align Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-221
PAND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-224
PANDN—Logical AND NOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-227
PAUSE—Spin Loop Hint  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-230
PAVGB/PAVGW—Average Packed Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-231
PBLENDVB—Variable Blend Packed Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 4-235
PBLENDW—Blend Packed Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-239

PCLMULQDQ—Carry-Less Multiplication Quadword  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-242
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-245
PCMPEQQ—Compare Packed Qword Data for Equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-251
PCMPESTRI—Packed Compare Explicit Length Strings, Return Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 4-254
PCMPESTRM—Packed Compare Explicit Length Strings, Return Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 4-256
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-258
PCMPGTQ—Compare Packed Data for Greater Than  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-264
PCMPISTRI—Packed Compare Implicit Length Strings, Return Index  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 4-267
PCMPISTRM—Packed Compare Implicit Length Strings, Return Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-269
PCONFIG—Platform Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-271
PDEP—Parallel Bits Deposit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-277
PEXT—Parallel Bits Extract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-279
PEXTRB/PEXTRD/PEXTRQ—Extract Byte/Dword/Qword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-281
PEXTRW—Extract Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-284
PHADDW/PHADDD—Packed Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-287Vol. 2A xiCONTENTS
PAGE
PHADDSW—Packed Horizontal Add and Saturate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-291
PHMINPOSUW—Packed Horizontal Word Minimum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-293
PHSUBW/PHSUBD—Packed Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-295
PHSUBSW—Packed Horizontal Subtract and Saturate  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-298
PINSRB/PINSRD/PINSRQ—Insert Byte/Dword/Qword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 4-300
PINSRW—Insert Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-303
PMADDUBSW—Multiply and Add Packed Signed and Unsigned Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 4-305
PMADDWD—Multiply and Add Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-311
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-318
PMAXUD/PMAXUQ—Maximum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-323
PMINSB/PMINSW—Minimum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-327
PMINSD/PMINSQ—Minimum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 4-332
PMINUB/PMINUW—Minimum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-336
PMINUD/PMINUQ—Minimum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 4-341
PMOVMSKB—Move Byte Mask  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-345
PMOVSX—Packed Move With Sign Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4-347
PMOVZX—Packed Move With Zero Extend  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-356
PMULDQ—Multiply Packed Doubleword Integers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-366
PMULHRSW—Packed Multiply High With Round and Scale  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 4-369
PMULHUW—Multiply Packed Unsigned Integers and Store High Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-373
PMULHW—Multiply Packed Signed Integers and Store High Result  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-377
PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-381
PMULLW—Multiply Packed Signed Integers and Store Low Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 4-385
PMULUDQ—Multiply Packed Unsigned Doubleword Integers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-389
POP—Pop a Value From the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-392
POPA/POPAD—Pop All General-Purpose Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-397
POPCNT—Return the Count of Number of Bits Set to 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-399
POPF/POPFD/POPFQ—Pop Stack Into EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-401
POR—Bitwise Logical OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-405
PREFETCHh—Prefetch Data Into Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-408
PREFETCHW—Prefetch Data Into Caches in Anticipation of a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 4-410
PSADBW—Compute Sum of Absolute Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-412
PSHUFB—Packed Shuffle Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-416
PSHUFD—Shuffle Packed Doublewords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-420
PSHUFHW—Shuffle Packed High Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-424
PSHUFLW—Shuffle Packed Low Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-427

PSHUFW—Shuffle Packed Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-430
PSIGNB/PSIGNW/PSIGND—Packed SIGN  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 4-431
PSLLDQ—Shift Double Quadword Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-435
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-437
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 4-449
PSRLDQ—Shift Double Quadword Right Logical  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-459
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 4-461
PSUBB/PSUBW/PSUBD—Subtract Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-473
PSUBQ—Subtract Packed Quadword Integers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-481
PSUBSB/PSUBSW—Subtract Packed Signed Integers With Signed Saturation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-484
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers With Unsigned Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 4-488
PTEST—Logical Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-492
PTWRITE—Write Data to a Processor Trace Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-494
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .4 - 4 9 6
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 4-506
PUSH—Push Word, Doubleword, or Quadword Onto the Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 4-516
PUSHA/PUSHAD—Push All General-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-519
PUSHF/PUSHFD/PUSHFQ—Push EFLAGS Register Onto the Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-521
PXOR—Logical Exclusive OR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-523
RCL/RCR/ROL/ROR—Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-526
RCPPS—Compute Reciprocals of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-531
RCPSS—Compute Reciprocal of Scalar Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 4-533CONTENTS
xiiVol. 2APAGE
RDFSBASE/RDGSBASE—Read FS/GS Segment Base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-535
RDMSR—Read From Model Specific Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4-537
RDPID—Read Processor ID  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-539
RDPKRU—Read Protection Key Rights for User Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-540
RDPMC—Read Performance-Monitoring Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-542
RDRAND—Read Random Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-544
RDSEED—Read Random SEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-546
RDSSPD/RDSSPQ—Read Shadow Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-548
RDTSC—Read Time-Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-550
RDTSCP—Read Time-Stamp Counter and Processor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-552
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-554
RET—Return From Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-558
RORX — Rotate Right Logical Without Affecting Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-571
ROUNDPD—Round Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-572
ROUNDPS—Round Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-575
ROUNDSD—Round Scalar Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-577
ROUNDSS—Round Scalar Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-579
RSM—Resume From System Management Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 4-581
RSQRTPS—Compute Reciprocals of Square Roots of Packed Single Precision Floating-Point Values  . . . . . . . . . . . . . . . 4-583RSQRTSS—Compute Reciprocal of Square Root of Scalar Single Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . 4-585
RSTORSSP—Restore Saved Shadow Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-587
SAHF—Store AH Into Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-590
SAL/SAR/SHL/SHR—Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-592
SARX/SHLX/SHRX—Shift Without Affecting Flags  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-597
SAVEPREVSSP—Save Previous Shadow Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-599
SBB—Integer Subtraction With Borrow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-601
SCAS/SCASB/SCASW/SCASD—Scan String  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4-604
SENDUIPI—Send User Interprocessor Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-608
SERIALIZE—Serialize Instruction Execution  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-610
SETcc—Set Byte on Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-611

SETSSBSY—Mark Shadow Stack Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-614
SFENCE—Store Fence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-616
SGDT—Store Global Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-617
SHA1RNDS4—Perform Four Rounds of SHA1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 4-619
SHA1NEXTE—Calculate SHA1 State Variable E After Four Rounds  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 4-621
SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords  . . . . . . . . . . . . . . . . . . . . . 4-6 22
SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Me ssage Dwords. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 4-623
SHA256RNDS2—Perform Two Rounds of SHA256 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 4-624
SHA256MSG1—Perform an Intermed iate Calculation for the Next Four SHA256 Message Dwords . . . . . . . . . . . . . . . . 4-626
SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords . . . . . . . . . . . . . . . . . . . . . . . . . 4-627
SHLD—Double Precision Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-628
SHRD—Double Precision Shift Right. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-631
SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-634
SHUFPS—Packed Interleave Shuffle of Quadruplets of Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . 4-639
SIDT—Store Interrupt Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4-643
SLDT—Store Local Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 4-645
SMSW—Store Machine Status Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-647
SQRTPD—Square Root of Double Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-649
SQRTPS—Square Root of Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 4-652
SQRTSD—Compute Square Root of Scalar Double Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 4-655
SQRTSS—Compute Square Root of Scalar Single Precision Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 4-657
STAC—Set AC Flag in EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-659
STC—Set Carry Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-660
STD—Set Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-661
STI—Set Interrupt Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-662
STMXCSR—Store MXCSR Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-664
STOS/STOSB/STOSW/STOSD/STOSQ—Store String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-665
STR—Store Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-668
STTILECFG—Store Tile Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-670Vol. 2A xiiiCONTENTS
PAGE
STUI—Set User Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-672
SUB—Subtract  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-673
SUBPD—Subtract Packed Double Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-675
SUBPS—Subtract Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 4-678
SUBSD—Subtract Scalar Double Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-681
SUBSS—Subtract Scalar Single Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-683
SWAPGS—Swap GS Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-685
SYSCALL—Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-687
SYSENTER—Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-690
SYSEXIT—Fast Return from Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4-693
SYSRET—Return From Fast System Call  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 4-696
TDPBF16PS—Dot Product of BF16 Tiles Accumulated into Packed Single Precision Tile . . . . . . . . . . . . . . . . . . . . . . .  . . . 4-699
TDPBSSD/TDPBSUD/TDPBUSD/TDPBUUD—Dot Pr oduct of Signed/Unsigned Bytes with Dword Accumulation  . . . . 4-701
TEST—Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-703
TESTUI—Determine User Interrupt Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 4-705
TILELOADD/TILELOADDT1—Load Tile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-706
TILERELEASE—Release Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-708
TILESTORED—Store Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-709
TILEZERO—Zero Tile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-710
TPAUSE—Timed PAUSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-711
TZCNT—Count the Number of Trailing Zero Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 4-713
UCOMISD—Unordered Compare Scalar Double Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . 4-7 15

UCOMISS—Unordered Compare Scalar Single Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . 4 -717
UD—Undefined Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-719
UIRET—User-Interrupt Return. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-720
UMONITOR—User Level Set Up Monitor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-722
UMWAIT—User Level Monitor Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-724
UNPCKHPD—Unpack and Interleave High Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . 4-726
UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . 4-730
UNPCKLPD—Unpack and Interleave Low Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . .  . . 4-734
UNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . .  . . . 4-738
CHAPTER 5
INSTRUCTION SET REFERENCE, V5.1 TERNARY BIT VECTOR LOGIC TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-1
5.2 INSTRUCTIONS (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-4
VADDPH—Add Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
VADDSH—Add Scalar FP16 Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .5-8
VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
VBROADCAST—Load with Broadcast Floating-Point Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 5-13
VCMPPH—Compare Packed FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
VCMPSH—Compare Scalar FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
VCOMISH—Compare Scalar Ordered FP16 Values and Set EFLAGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
VCOMPRESSPD—Store Sparse Packed Double Precision Floating-Point Values Into Dense Memory . . . . . . . . . . . . . . . . . 5-27
VCOMPRESSPS—Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory . . . . . . . . . . . . . . . . . . 5-2 9
VCVTDQ2PH—Convert Packed Signed Doubleword Integers to Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . 5-31
VCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 5-33
VCVTNEPS2BF16—Convert Packed Single Data to Packed BF16 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 5-35
VCVTPD2PH—Convert Packed Double Precision FP Values to Packed FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
VCVTPD2QQ—Convert Packed Double Precision Floating-Point Values to Packed Quadword Integers . . . . . . . . . . . . . . 5-39
VCVTPD2UDQ—Convert Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers. . 5-41
VCVTPD2UQQ—Convert Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers . . . 5-43
VCVTPH2DQ—Convert Packed FP16 Values to Signed Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-45
VCVTPH2PD—Convert Packed FP16 Values to FP64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-47
VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Values to Single Precision Floating-Point Values . . . . . . . . . . . . . . . 5-49
VCVTPH2QQ—Convert Packed FP16 Values to Signed Quadword Integer Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53
VCVTPH2UDQ—Convert Packed FP16 Values to Unsigned Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
VCVTPH2UQQ—Convert Packed FP16 Values to Unsigned Quadword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57CONTENTS
xiv Vol. 2APAGE
VCVTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 5-59
VCVTPH2W—Convert Packed FP16 Values to Signed Word Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61
VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 5-63
VCVTPS2PHX—Convert Packed Single Precision Floating-Point Values to Packed FP16 Values. . . . . . . . . . . . . . . . . . . . .  5-67
VCVTPS2QQ—Convert Packed Single Precisio n Floating-Point Values to Packed Si gned Quadword Integer Values . . 5-69
VCVTPS2UDQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . 5-76VCVTQQ2PH—Convert Packed Signed Quadword Integers to Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 5-78
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single Precision Floating-Point Values  . . . . . . . . . . . . . . . 5-80
VCVTSD2SH—Convert Low FP64 Value to an FP16 Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 5-82
VCVTSD2USI—Convert Scalar Double Precision Floating-Point Value to Unsigned Doubleword Integer. . . . . . . . . . . . . . 5-83
VCVTSH2SD—Convert Low FP16 Value to an FP64 Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 5-85
VCVTSH2SI—Convert Low FP16 Value to Signed Integer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86
VCVTSH2SS—Convert Low FP16 Value to FP32 Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 5-87
VCVTSH2USI—Convert Low FP16 Value to Unsigned Integer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-88
VCVTSI2SH—Convert a Signed Doubleword/Quadword Integer to an FP16 Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 5-89
VCVTSS2SH—Convert Low FP32 Value to an FP16 Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91
VCVTSS2USI—Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword Integer. . . . . . . . . . . . . . . 5-9 2
VCVTTPD2QQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Quadword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
VCVTTPD2UDQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned

VCVTTPD2UDQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned 
Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
VCVTTPD2UQQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned 
Quadword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98
VCVTTPH2DQ—Convert with Truncation Packed FP16 Values to Signed Doubleword Integers. . . . . . . . . . . . . . . . . . . . 5-100VCVTTPH2QQ—Convert with Truncation Packed FP16 Values to Signed Quadword Integers  . . . . . . . . . . . . . . . . . . . . . 5-10 2
VCVTTPH2UDQ—Convert with Truncation Packed FP16 Values to Unsigned Doubleword Integers . . . . . . . . . . . . . . . . 5-104
VCVTTPH2UQQ—Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers  . . . . . . . . . . . . . . . . . 5-106VCVTTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-108
VCVTTPH2W—Convert Packed FP16 Values to Signed Word Integers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-110
VCVTTPS2QQ—Convert With Truncation Packed Single Precis ion Floating-Point Values to Packed Signed Quadword 
Integer Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
VCVTTPS2UDQ—Convert With Truncation Packed Single Pr ecision Floating-Point Values to Packed Unsigned 
Doubleword Integer Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-114
VCVTTPS2UQQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned 
Quadword Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-116
VCVTTSD2USI—Convert With Truncation Scalar Double Precision Floating-Point Value to Unsigned Integer  . . . . . . . 5-118VCVTTSH2SI—Convert with Truncation Low FP16 Value to a Signed Integer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-119
VCVTTSH2USI—Convert with Truncation Low FP16 Value to an Unsigned Integer . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 5-120
VCVTTSS2USI—Convert With Truncation Scalar Single Precision Fl oating-Point Value to Unsigned Integer. . . . . . . . . 5-121
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double Precision Floating-Point Values. 5-122
VCVTUDQ2PH—Convert Packed Unsigned Doubleword Integers to Packed FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . 5-124
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single Precision Floating-Point Values . . 5-126VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double Precision Floating-Point Values  . . 5-128
VCVTUQQ2PH—Convert Packed Unsigned Quadword Integers to Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-130
VCVTUSI2SH—Convert Unsigned Doubleword Integer to an FP16 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-132
VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single Precision Floating-Point Values  . . . 5-134
VCVTUSI2SD—Convert Unsigned Integer to Scalar Double Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
VCVTUSI2SS—Convert Unsigned Integer to Scalar Single Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . 5-138
VCVTUW2PH—Convert Packed Unsigned Word Integers to FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 5-140
VCVTW2PH—Convert Packed Signed Word Integers to FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-142
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes. . . . . . . . . . . . . . . . . . . . . . . . . 5-144
VDIVPH—Divide Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-147
VDIVSH—Divide Scalar FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-149
VDPBF16PS—Dot Product of BF16 Pairs Accumulated Into Packed Single Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-150
VERR/VERW—Verify a Segment for Reading or Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-152Vol. 2A xvCONTENTS
PAGE
VEXPANDPD—Load Sparse Packed Double Precision Floating-Point Values From Dense Memory. . . . . . . . . . . . . . . . . . 5-154
VEXPANDPS—Load Sparse Packed Single Precision Floating-Point Values From Dense Memory. . . . . . . . . . . . . . . . . . . 5-156VEXTRACTF128/VEXTRACTF3 2x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4— Extract Packed 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-158
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRAC TI32x8/VEXTRACTI64x4—Ext ract Packed Integer 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-164
VFCMADDCPH/VFMADDCPH—Complex Multiply and Accumulate FP16 Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-170
VFCMADDCSH/VFMADDCSH—Complex Multiply and Accumulate Scalar FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .5 - 1 7 3
VFCMULCPH/VFMULCPH—Complex Multiply FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-175
VFCMULCSH/VFMULCSH—Complex Multiply Scalar FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 5-178
VFIXUPIMMPD—Fix Up Special Packed Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 5-180
VFIXUPIMMPS—Fix Up Special Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 5-184
VFIXUPIMMSD—Fix Up Special Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-188
VFIXUPIMMSS—Fix Up Special Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 5-191
VFMADD132PD/VFMADD213PD/VFM ADD231PD—Fused Multiply-Add of Packed Double Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-194
VF[,N]MADD[132,213,231]PH—Fused Multiply-Add of Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-201
VFMADDRND231PD - Fused Multiply-Add of Packed Double-Precision Floating-Point  Values with rounding control 5-207
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-210
VFMADD132SD/VFMADD213SD/VFMADD231SD— Fused Multiply-Add of Scalar Do uble Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-216
VF[,N]MADD[132,213,231]SH—Fused Multiply-Add of Scalar FP16 Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-219
VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-222
VFMADDSUB132PD/VFMADDSUB213PD/VFMA DDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed

VFMADDSUB132PD/VFMADDSUB213PD/VFMA DDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed 
Double Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-225
VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH—Fused Multiply-Alternating Ad d/Subtract of Packed 
FP16 Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-232
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed 
Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-237
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Sub tract of Packed Double Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-244
VF[,N]MSUB[132,213,231]PH—Fused Multiply-Subtract of Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-250
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Sub tract of Packed Single Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-256
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-262
VF[,N]MSUB[132,213,231 ]SH—Fused Multiply-Subtract of Scalar FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 5-265
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Sub tract of Scalar Single Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-268
VFMSUBADD132PD/VFMSUBADD213 PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed 
Double Precision Floating-Point Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-271
VFMSUBADD132PH/VFMSUBADD213PH/VFMSU BADD231PH—Fused Multip ly-Alternating Subtra ct/Add of Packed 
FP16 Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-278
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused  Multiply-Alternating Subtract/Add of Packed 
Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-283
VFNMADD132PD/VFNMADD213PD/V FNMADD231PD—Fused Negative Multiply -Add of Packed Double Precision 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-291
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Nega tive Multiply-Add of Pa cked Single Precision 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-298
VFNMADD132SD/VFNMADD213SD/VFNMADD2 31SD—Fused Negative Multiply-Add  of Scalar Double Precision 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-304
VFNMADD132SS/VFNMADD213SS /VFNMADD231SS—Fused Negative Multiply-Add of Scalar Single Precision 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-307
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative  Multiply-Subtract of Pa cked Double Precision 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-310
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single Precision 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-317CONTENTS
xvi Vol. 2APAGE
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of Scalar Double Precision 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-323
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of Scalar Single Precision 
Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-326
VFPCLASSPD—Tests Types of Packed Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-329
VFPCLASSPH—Test Types of Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 5-332
VFPCLASSPS—Tests Types of Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 5-335
VFPCLASSSD—Tests Type of a Scalar Float64 Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 5-337
VFPCLASSSH—Test Types of Scalar FP16 Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 5-339
VFPCLASSSS—Tests Type of a Scalar Float32 Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-340
VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Floating-Point Values Using Signed Dword/Qword 
Indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-342
VGATHERDPS/VGATHERQPS—Gather Packed Single Precision Floating-Point Values Using Signed Dword/Qword Indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-346
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword Indices . . . . . . . . . . . . . . . . . . 5-350
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices . . . . . . . . . . . . . . . . . . 5-353VGETEXPPD—Convert Exponents of  Packed Double Precision Floating-Point Va lues to Double Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-356
VGETEXPPH—Convert Expo nents of Packed FP16 Valu es to FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-359
VGETEXPPS—Convert Exponents of  Packed Single Precision Floating-Point Va lues to Single Precision Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-362
VGETEXPSD—Convert Exponents of Scalar Double Precision Fl oating-Point Value to Double Precision Floating-Point 
Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-366
VGETEXPSH—Convert Exponents of Scalar FP16 Values to FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-368

VGETEXPSS—Convert Exponents of Scalar Single Precision Floating-Point Value to Single Precision Floating-Point Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-370
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas From Float64 Vector. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-372
VGETMANTPH—Extract FP16 Vector of Normalized Mantissas from FP16 Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-376
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas From Float32 Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-380
VGETMANTSD—Extract Float64 of Normalized Mantissa From Float64 Scalar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-383
VGETMANTSH—Extract FP16 of Normalized Mantissa from FP16 Scalar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-385
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa From Float32 Scalar . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . 5-387
VINSERTF128/VINSERTF32x4/VINSERTF 64x2/VINSERTF32x8/VINSERTF64x4—In sert Packed Floating-Point 
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-389
VINSERTI128/VINSERTI32x4/VINSERTI64x2/V INSERTI32x8/VINSERTI64x4—Insert Packed Integer Values  . . . . . . 5-393
VMASKMOV—Conditional SIMD Packed Loads and Stores  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 5-397
VMAXPH—Return Maximum of Packed FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-400
VMAXSH—Return Maximum of Scalar FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-402
VMINPH—Return Minimum of Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 5-404
VMINSH—Return Minimum Scalar FP16 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 5-406
VMOVSH—Move Scalar FP16 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-408
VMOVW—Move Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-410
VMULPH—Multiply Packed FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 5-411
VMULSH—Multiply Scalar FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 5-413
VP2INTERSECTD/VP2INTERSECTQ—Compute  Intersection Between DWORDS/Q UADWORDS to a Pair of Mask 
Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-414
VPBLENDD—Blend Packed Dwords  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-416
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-418
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . 5-420
VPBROADCASTB/W/D/Q—Load With Broadcast Integer Data From General Purpose Register . . . . . . . . . . . . . . . . . . . . . 5-42 3
VPBROADCAST—Load Integer and Broadcast  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-426
VPBROADCASTM—Broadcast Mask to Vector Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-435
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 5-437
VPCMPD/VPCMPUD—Compare Packed Integer Values Into Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 5-440
VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into Mask  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-443
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-446
VPCOMPRESSB/VCOMPRESSW—Store Sparse Packed Byte/Word Integer Values Into Dense Memory/Register . . . . 5-449VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values Into Dense Memory/Register . . . . . . . . . . . . . . . . . . 5-452
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values Into Dense Memory/Register. . . . . . . . . . . . . . . . . . . . 5-454Vol. 2A xviiCONTENTS
PAGE
VPCONFLICTD/Q—Detect Conflict s Within a Vector of Packed Dword/Qword Values Into Dense Memory/ Register. 5-456
VPDPBUSD—Multiply and Add Unsigned and Signed Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-459
VPDPBUSDS—Multiply and Add Unsigned and Signed Bytes With Saturation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-461
VPDPWSSD—Multiply and Add Signed Word Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-463
VPDPWSSDS—Multiply and Add Signed Word Integers With Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 5-465
VPERM2F128—Permute Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 5-467
VPERM2I128—Permute Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-469
VPERMB—Permute Packed Bytes Elements  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 5-471
VPERMD/VPERMW—Permute Packed Doubleword/Word Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 5-473
VPERMI2B—Full Permute of Bytes From Two Tables Overwriting the Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-476
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 5-478
VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 5-484
VPERMILPS—Permute In-Lane of Quadruples of Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-489
VPERMPD—Permute Double Precision Floating-Point Elements  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-494
VPERMPS—Permute Single Precision Floating-Point Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-497
VPERMQ—Qwords Element Permutation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-500
VPERMT2B—Full Permute of Bytes From Two Tables Overwriting a Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 5-503
VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-505
VPEXPANDB/VPEXPANDW—Expand Byte/Word Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 5-510
VPEXPANDD—Load Sparse Packed Doubleword Integer Values From Dense Memory/Register. . . . . . . . . . . . . . . . . . . . 5-513
VPEXPANDQ—Load Sparse Packed Quadword Integer Values From Dense Memory/Register . . . . . . . . . . . . . . . . . . . . . 5-515
VPGATHERDD/VPGATHERQD—Gather Pack ed Dword Values Using Signed Dword/Qword In dices . . . . . . . . . . . . . . . . . 5-517
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With Signed Dword Indices . . . . . . . . . . . . . . . . . 5-521

VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword Indices. . . . . . . . . . . . . . . . . 5-524
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices . . . . . . . . . . . . . . . . . 5-528VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword,  Packed Qword Values . . . . . . . . . . . . . . 5-531
VPMADD52HUQ—Packed Multiply of Unsigned 52-Bit Unsign ed Integers and Add High 52-Bit Products to 64-Bit 
Accumulators  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-534
VPMADD52LUQ—Packed Multip ly of Unsigned 52-Bit Integers and Add the Low 52-Bit Products to Qword 
Accumulators  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-536
VPMASKMOV—Conditional SIMD Integer Packed Loads and Stores  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-538
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask  . . . . . . . . . . . . . . . . . . . . . . 5-541
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 5-544
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 5-548
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register . . . . . . . . . . . . . . 5-552
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 5-555
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 5-559
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 5-563
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-567
VPMULTISHIFTQB—Select Packed Unaligned Bytes From Quadword Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-571
VPOPCNT—Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD. . . . . . . . . . . . . . . . . . . . . . . . 5-57 3
VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 5-576
VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-580
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed 
Dword, Signed Qword Indices  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-584
VPSHLD—Concatenate and Shift Packed Data Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-588
VPSHLDV—Concatenate and Variable Shift Packed Data Left Logical  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-591
VPSHRD—Concatenate and Shift Packed Data Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-594
VPSHRDV—Concatenate and Variable Shift Packed Data Right Logical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 5-597
VPSHUFBITQMB—Shuffle Bits From Quadword Elements Using Byte In dexes Into Mask  . . . . . . . . . . . . . . . . . . . . . . . . .5 - 6 0 0
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 5-601
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-606
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 
. . . . . . . . . . . . . 5-611
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-616
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-619
VPTESTNMB/W/D/Q—Logical NAND and Set  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-622
VRANGEPD—Range Restriction Calculation for Packed Pairs of Float64 Values  . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-625
 VRANGEPS—Range Restriction Calculation for Packed Pairs of Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-629
VRANGESD—Range Restriction Calculation From a Pair of Scalar Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-632CONTENTS
xviii Vol. 2APAGE
VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-635
VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-638
VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-640
VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-642
VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 5-644
VRCPPH—Compute Reciprocals of Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 5-646
VRCPSH—Compute Reciprocal of Scalar FP16 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 5-648
VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 5-649
VREDUCEPH—Perform Reduction Transformation on Packed FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-652
VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-655
 VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-657
VREDUCESH—Perform Reduction Transformation on Scalar FP16 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-659
VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-661
VRNDSCALEPD—Round Packed Float64 Values to Include a Given Number of Fraction Bits . . . . . . . . . . . . . . . . . . . . . . . 5-663
VRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of Fraction Bits  . . . . . . . . . . . . . . . . . . . . . . . .  . 5-666
VRNDSCALEPS—Round Packed Float32 Values to Include a Given Number of Fraction Bits . . . . . . . . . . . . . . . . . . . . . . . 5-669
VRNDSCALESD—Round Scalar Float64 Value to Include a Given Number of Fraction Bits . . . . . . . . . . . . . . . . . . . . . . .  . . 5-672
VRNDSCALESH—Round Scalar FP16 Value to Include a Given Number of Fraction Bits. . . . . . . . . . . . . . . . . . . . . . . . .  . . . 5-674
VRNDSCALESS—Round Scalar Float32 Value to Include a Given Number of Fraction Bits. . . . . . . . . . . . . . . . . . . . . . . . . . 5-676
VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values. . . . . . . . . . . . . . . . . . . . 5-678
VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . 5-680
VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values . . . . . . . . . . . . . . . . . . . . 5-682
VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . 5-684
VRSQRTPH—Compute Reciprocals of Square Roots of Packed FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 5-686
VRSQRTSH—Compute Approximate Reciprocal of Square Root of Scalar FP16 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-688

VSCALEFPD—Scale Packed Float64 Values With Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-689
VSCALEFPH—Scale Packed FP16 Values with FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-692
VSCALEFPS—Scale Packed Float32 Values With Float32 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-694
VSCALEFSD—Scale Scalar Float64 Values With Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-697
VSCALEFSH—Scale Scalar FP16 Values with FP16 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-699
VSCALEFSS—Scale Scalar Float32 Value With Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-701
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS /VSCATTERQPD—Scatter Packed Single, Packed Double with Signed 
Dword and Qword Indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-703
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-Bit Granularity. . . . . . . . . . . 5-707
VSQRTPH—Compute Square Root of Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-712
VSQRTSH—Compute Square Root of Scalar FP16 Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-714
VSUBPH—Subtract Packed FP16 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-715
VSUBSH—Subtract Scalar FP16 Value  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 5-717
VTESTPD/VTESTPS—Packed Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-718
VUCOMISH—Unordered Compare Scalar FP16 Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 5-721
VZEROALL—Zero XMM, YMM, and ZMM Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 5-722
VZEROUPPER—Zero Upper Bits of YMM and ZMM Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 5-723
CHAPTER 6
INSTRUCTION SET REFERENCE, W-Z
6.1 INSTRUCTIONS (W-Z)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-1
WAIT/FWAIT—Wait  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
WBINVD—Write Back and Invalidate Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
WBNOINVD—Write Back and Do Not Invalidate Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
WRFSBASE/WRGSBASE—Write FS/GS Segment Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
WRMSR—Write to Model Specific Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
WRPKRU—Write Data to User Page Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
WRSSD/WRSSQ—Write to Shadow Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
WRUSSD/WRUSSQ—Write to User Shadow Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 6-15
XABORT—Transactional Abort  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
XACQUIRE/XRELEASE—Hardware Lock Elision Prefix Hints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 6-19
XADD—Exchange and Add  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
XBEGIN—Transactional Begin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
XCHG—Exchange Register/Memory With Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28Vol. 2A xixCONTENTS
PAGE
XEND—Transactional End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
XGETBV—Get Value of Extended Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 6-32
XLAT/XLATB—Table Look-up Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
XOR—Logical Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
XORPD—Bitwise Logical XOR of Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 6-38
XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 6-41
XRESLDTRK—Resume Tracking Load Addresses  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
XRSTOR—Restore Processor Extended States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 6-45
XRSTORS—Restore Processor Extended States Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 6-50
XSAVE—Save Processor Extended States  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
XSAVEC—Save Processor Extended States With Compaction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 6-57
XSAVEOPT—Save Processor Extended States Optimized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 6-60
XSAVES—Save Processor Extended States Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63
XSETBV—Set Extended Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66
XSUSLDTRK—Suspend Tracking Load Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68
XTEST—Test if in Transactional Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69
CHAPTER 7
SAFER MODE EXTENSIONS REFERENCE7.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7-1
7.2 SMX FUNCTIONALITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7-1
7.2.1 Detecting and Enabling SMX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

CHAPTER 7
7.2.2 SMX Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2
7.2.2.1 GETSEC[CAPABILITIES]  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
7.2.2.2 GETSEC[ENTERACCS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
7.2.2.3 GETSEC[EXITAC]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
7.2.2.4 GETSEC[SENTER] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.2.2.5 GETSEC[SEXIT] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.2.2.6 GETSEC[PARAMETERS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.2.2.7 GETSEC[SMCTRL]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.2.2.8 GETSEC[WAKEUP] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.2.3 Measured Environment and SMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
7.3 GETSEC LEAF FUNCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7-5
GETSEC[CAPABILITIES]—Report the SMX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .7-7
GETSEC[ENTERACCS]—Execute Authenticated Chipset Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 7-10
GETSEC[EXITAC]—Exit Authenticated Code Execution Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 7-18
GETSEC[SENTER]—Enter a Measured Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 7-21
GETSEC[SEXIT]—Exit Measured Environment  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 7-30
GETSEC[PARAMETERS]—Report the SMX Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
GETSEC[SMCTRL]—SMX Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
GETSEC[WAKEUP]—Wake Up Sleeping Processors in Measured Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 7-40
CHAPTER 8
INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
PREFETCHWT1—Prefetch Vector Data Into Caches With Intent to Write and T1 Hint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
V4FMADDPS/V4FNMADDPS—Packed Single Precision Floating-Point Fu sed Multiply-Add (4-Iterations). . . . . . . . . . . . . . .8-4
V4FMADDSS/V4FNMADDSS—Scalar Single Precision Floating-Point Fused Multiply-Add (4-Iterations)  . . . . . . . . . . . . . . .8-6
VEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point Values With Less Than 2^-23 Relative Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
VEXP2PS—Approximation to the Exponential 2^x of Packed Single Precision Floating-Point Values With Less Than 
2^-23 Relative Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHE RPF0QPD—Sparse Prefetch Packed SP/DP Data 
Values With Signed Dword, Signed Qword Indices Using T0 Hint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 8-12
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHE RPF1QPD—Sparse Prefetch Packed SP/DP Data 
Values With Signed Dword, Signed Qword Indices Using T1 Hint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 8-14
VP4DPWSSDS—Dot Product of Signed Words With Dword Accumulation and Saturation (4-Iterations)  . . . . . . . . . . . . . 8-16VP4DPWSSD—Dot Product of Signed Words With Dword Accumulation (4-Iterations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
VRCP28PD—Approximation to the Reciproc al of Packed Double Precision Floating-Point Values With Less Than 
2^-28 Relative Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
VRCP28SD—Approximation to the Reciprocal of Scalar Double Precision Floating-Point Value With Less Than CONTENTS
xx Vol. 2APAGE
2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
VRCP28PS—Approximation to the Reciprocal of Packed Single Precision Floating-Point Values With Less Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
VRCP28SS—Approximation to the Reciprocal of Scalar Single Precision Floating-Point Value With Less Than 
2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double Precision Floating-Point Values 
With Less Than 2^-28 Relative Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double Precision Floating-Point Value With 
Less Than 2^-28 Relative Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single Precision Floating-Point Values With 
Less Than 2^-28 Relative Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-Point Value With Less 
Than 2^-28 Relative Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCA TTERPF0QPD—Sparse Prefetch Packed SP/DP Data 
Values with Signed Dword, Signed Qword Indices Using T0 Hint With Intent to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCA TTERPF1QPD—Sparse Prefetch Packed SP/DP Data 
Values With Signed Dword, Signed Qword Indices Using T1 Hint With Intent to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38
APPENDIX A
OPCODE MAP
A.1 USING OPCODE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-1
A.2 KEY TO ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-1

APPENDIX A
OPCODE MAP
A.2.1 Codes for Addressing Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2.2 Codes for Operand Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2.3 Register Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.2.4 Opcode Look-up Examples for One, Two, and Three-Byte Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . A-3
A.2.4.1 One-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.2.4.2 Two-Byte Opcode Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A.2.4.3 Three-Byte Opcode Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.2.4.4 VEX Prefix Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.2.5 Superscripts Utilized in Opcode Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A.3 ONE, TWO, AND THREE-BYTE OPCODE MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-6
A.4 OPCODE EXTENSIONS FOR ONE-BYTE AND TWO-BYTE OPCODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .  A-17
A.4.1 Opcode Look-up Examples Using Opcode Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . A-17
A.4.2 Opcode Extension Tables  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.5 ESCAPE OPCODE INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-20
A.5.1 Opcode Look-up Examples for Escape Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2 Escape Opcode Instruction Tables  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2.1 Escape Opcodes with D8 as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2.2 Escape Opcodes with D9 as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
A.5.2.3 Escape Opcodes with DA as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
A.5.2.4 Escape Opcodes with DB as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
A.5.2.5 Escape Opcodes with DC as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
A.5.2.6 Escape Opcodes with DD as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
A.5.2.7 Escape Opcodes with DE as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
A.5.2.8 Escape Opcodes with DF As First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
APPENDIX B
INSTRUCTION FORMATS AND ENCODINGSB.1 MACHINE INSTRUCTION FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-1
B.1.1 Legacy Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1.2 REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
B.1.3 Opcode Fields  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
B.1.4 Special Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
B.1.4.1 Reg Field (reg) for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
B.1.4.2 Reg Field (reg) for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
B.1.4.3 Encoding of Operand Size (w) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
B.1.4.4 Sign-Extend (s) Bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
B.1.4.5 Segment Register (sreg) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
B.1.4.6 Special-Purpose Register (eee) Field  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
B.1.4.7 Condition Test ( tttn) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
B.1.4.8 Direction (d) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
B.1.5 Other Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6Vol. 2A xxiCONTENTS
PAGE
B.2 GENERAL-PURPOSE INSTRUCTION FORMATS AND ENCODINGS FOR NON-64-BIT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-7
B.2.1 General Purpose Instruction Formats and Encodings for 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . B-18
B.3 PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
B.4 64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . B-37
B.5 MMX INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  B-38
B.5.1 Granularity Field (gg)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
B.5.2 MMX Technology and General-Purpose Register Fields (mmxreg and reg). . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . B-38
B.5.3 MMX Instruction Formats and Encodings Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . B-38

B.6 PROCESSOR EXTENDED STATE INSTRUCTION FORMATS AND ENCODINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
B.7 P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-41
B.8 SSE INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .  B-42
B.9 SSE2 INSTRUCTION FORMATS AND ENCODINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-47
B.9.1 Granularity Field (gg)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47
B.10 SSE3 FORMATS AND ENCODINGS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-57
B.11 SSSE3 FORMATS AND ENCODING TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-58
B.12 AESNI AND PCLMULQDQ INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .  B-60
B.13 SPECIAL ENCODINGS FOR 64-BIT MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-61
B.14 SSE4.1 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-64
B.15 SSE4.2 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-69
B.16 AVX FORMATS AND ENCODING TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70
B.17 FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .  B-108
B.18 VMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-112
B.19 SMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-113
APPENDIX C
INTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTS
C.1 SIMPLE INTRINSICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-2
C.2 COMPOSITE INTRINSICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  C-14CONTENTS
xxii Vol. 2APAGE
FIGURES
Figure 2-1. Intel 64 and IA-32 Architectures Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Figure 2-2. Table Interpretation of ModR/M Byte (C8H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-3. Prefix Ordering in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-4. Memory Addressing Without an SIB Byte; REX.X Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 2-5. Register-Register Addressing (No Memory Operand); REX.X Not Used . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 2-9
Figure 2-6. Memory Addressing With a SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2-8. Instruction Encoding Format with VEX Prefix  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Figure 2-9. VEX bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Figure 2-10. Intel® AVX-512 Instruction Format and the EVEX Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 2-37
Figure 2-11. Bit Field Layout of the EVEX Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Figure 3-1. Bit Offset for BIT[RAX, 21]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Figure 3-2. Memory Bit Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Figure 3-3. ADDSUBPD—Packed Double Precision Floating-Point Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
Figure 3-4. ADDSUBPS—Packed Single Precision Floating-Point Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Figure 3-5. Memory Layout of BNDMOV to/from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-117
Figure 3-6. Version Information Returned by CPUID in EAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-241
Figure 3-7. Feature Information Returned in the ECX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-243
Figure 3-8. Feature Information Returned in the EDX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-245
Figure 3-9. Determination of Support for the Processor Brand String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 3-255
Figure 3-10. Algorithm for Extracting Processor Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-256
Figure 3-11. CVTDQ2PD (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-267
Figure 3-12. VCVTPD2DQ (VEX.256 encoded version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-274
Figure 3-13. VCVTPD2PS (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-279
Figure 3-14. CVTPS2PD (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-288
Figure 3-15. VCVTTPD2DQ (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-304
Figure 3-16. 64-Byte Data Written to Enqueue Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-348
Figure 3-17. HADDPD—Packed Double Precision Floating-Point Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 3-483

Figure 3-18. VHADDPD Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-484
Figure 3-19. HADDPS—Packed Single Precision Floating-Point Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 3-487
Figure 3-20. VHADDPS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-487
Figure 3-21. HSUBPD—Packed Double Precision Floating-Point Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-492
Figure 3-22. VHSUBPD operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-493
Figure 3-23. HSUBPS—Packed Single Precision Floating-Point Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-496
Figure 3-24. VHSUBPS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-496
Figure 3-25. INVPCID Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-536
Figure 4-1. Operation of PCMPSTRx and PCMPESTRx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Figure 4-2. VMOVDDUP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
Figure 4-3. MOVSHDUP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-117
Figure 4-4. MOVSLDUP Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-120
Figure 4-5. 256-bit VMPSADBW Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-139
Figure 4-6. Operation of the PACKSSDW Instruction Using 64-Bit Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 4-189
Figure 4-7. 256-bit VPALIGN Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-222
Figure 4-8. PDEP Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-277
Figure 4-9. PEXT Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-279
Figure 4-10. 256-bit VPHADDD Instruction Oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-288
Figure 4-11. PMADDWD Execution Model Using 64-bit Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-309
Figure 4-12. PMULHUW and PMULHW Instruction Operation Using 64-bit Operands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-374
Figure 4-13. PMULLU Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-386
Figure 4-14. PSADBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 4-413
Figure 4-15. PSHUFB with 64-Bit Operands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-418
Figure 4-16. 256-bit VPSHUFD Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-421
Figure 4-17. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-439
Figure 4-18. PSRAW and PSRAD Instruction Operation Using a 64-bit Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-451
Figure 4-19. PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-463
Figure 4-20. PUNPCKHBW Instruction Operation Using 64-bit Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-498
Figure 4-21. 256-bit VPUNPCKHDQ Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 4-498
Figure 4-22. PUNPCKLBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-508
Figure 4-23. 256-bit VPUNPCKLDQ Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-508
Figure 4-24. Bit Control Fields of Immediate Byte for ROUNDxx Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-573Vol. 2A xxiiiCONTENTS
PAGE
Figure 4-25. 256-bit VSHUFPD Operation of Four Pairs of Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . 4-635
Figure 4-26. 256-bit VSHUFPS Operation of Selection from Input Quadruplet and Pair-wise Interleaved Result . . . . . . . . . . . . . 4-640
Figure 4-27. VUNPCKHPS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-731
Figure 4-28. VUNPCKLPS Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-739
Figure 5-1. VBROADCASTSS Operation (VEX.256 encoded version)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-2. VBROADCASTSS Operation (VEX.128-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-3. VBROADCASTSD Operation (VEX.256-bit version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-4. VBROADCASTF128 Operation (VEX.256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-5. VBROADCASTF64X4 Operation (512-bit version with writ emask all 1s) . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 5-16
Figure 5-6. VCVTPH2PS (128-bit Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50
Figure 5-7. VCVTPS2PH (128-bit Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
Figure 5-8. 64-bit Super Block of SAD Operation in VDBPSADBW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-145
Figure 5-9. VFIXUPIMMPD Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 5-182
Figure 5-10. VFIXUPIMMPS Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-186
Figure 5-11. VFIXUPIMMSD Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-190
Figure 5-12. VFIXUPIMMSS Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 5-193

Figure 5-13. Imm8 Byte Specifier of Special Case Floating-Point Values for VFPCLASSPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . 5-329
Figure 5-14. VGETEXPPS Functionalit y On Normal Input values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 5-363
Figure 5-15. Imm8 Controls for VGETMANTPD/SD/PS/SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-372
Figure 5-16. VPBROADCASTD Operation (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-428
Figure 5-17. VPBROADCASTD Operation (128-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-428
Figure 5-18. VPBROADCASTQ Operation (256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-428
Figure 5-19. VBROADCASTI128 Operation (256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-429
Figure 5-20. VBROADCASTI256 Operation (512-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-429
Figure 5-21. VPERM2F128 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-467
Figure 5-22. VPERM2I128 Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-469
Figure 5-23. VPERMILPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-485
Figure 5-24. VPERMILPD Shuffle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-485
Figure 5-25. VPERMILPS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-490
Figure 5-26. VPERMILPS Shuffle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-490
Figure 5-27. Imm8 Controls for VRANGEPD/SD/PS/SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-625
Figure 5-28. Imm8 Controls for VREDUCEPD/SD/PS/SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-649
Figure 5-29. Imm8 Controls for VRNDSCALEPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 5-664
Figure 8-1. Register Source-Block Dot Product of Two Signed Word Operands With Doubleword Accumulation . . . . . . . . . . . . .  8-18
Figure A-1. ModR/M Byte nnn Field (Bits 5, 4, and 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
Figure B-1. General Machine Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
Figure B-2. Hybrid Notation of VEX-Encoded Key Instruction Bytes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . B-70CONTENTS
xxiv Vol. 2APAGE
TABLES
Table 2-1. 16-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
Table 2-3. 32-Bit Addressing Forms with the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Table 2-4. REX Prefix Fields [BITS: 0100WRXB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Table 2-6. Direct Memory Offset Form of MOV  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Table 2-5. Special Cases of REX Encodings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Table 2-7. RIP-Relative Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Table 2-8. VEX.vvvv to register name mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Table 2-9. Instructions with a VEX.vvvv destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Table 2-10.  VEX.m-mmmm interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Table 2-11. VEX.L interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Table 2-12. VEX.pp interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Table 2-13. 32-Bit VSIB Addressing Forms of the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Table 2-14. Exception Class Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Table 2-15. Instructions in each Exception Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Table 2-16. #UD Exception and VEX.W=1 Encoding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Table 2-17. #UD Exception and VEX.L Field Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Table 2-18. Type 1 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Table 2-19. Type 2 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Table 2-20. Type 3 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Table 2-21. Type 4 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Table 2-22. Type 5 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Table 2-23. Type 6 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Table 2-24. Type 7 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Table 2-25. Type 8 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

Table 2-26. Type 11 Class Exception Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Table 2-27. Type 12 Class Exception Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Table 2-28. VEX-Encoded GPR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Table 2-29. Type 13 Class Exception Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Table 2-30. EVEX Prefix Bit Field Functional Grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Table 2-31. 32-Register Support in 64-bit Mode Using EVEX with Embedded REX Bits . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 2-39
Table 2-32. EVEX Encoding Register Specifiers in 32-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Table 2-33. Opmask Register Specifier Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
Table 2-34. Compressed Displacement (DISP8*N) Affected by Embedded Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 2-41
Table 2-35. EVEX DISP8*N for Instructions Not Affected by Embedd ed Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Table 2-36. EVEX Embedded Broadcast/Rounding/SAE and Vector Length on Vector Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
Table 2-37. OS XSAVE Enabling Requirements of Instruction Categories  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 2-43
Table 2-38. Opcode Independent, State Dependent EVEX Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 2-43
Table 2-39. #UD Conditions of Operand-Encoding EVEX Prefix Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
Table 2-40. #UD Conditions of Opmask Related Encoding Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
Table 2-41. #UD Conditions Dependent on EVEX.b Context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
Table 2-42. EVEX-Encoded Instruction Exception Class Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 2-45
Table 2-43. EVEX Instructions in Each Exception Class  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
Table 2-44. Type E1 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Table 2-45. Type E1NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Table 2-46. Type E2 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
Table 2-47. Type E3 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
Table 2-48. Type E3NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Table 2-49. Type E4 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
Table 2-50. Type E4NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
Table 2-51. Type E5 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56
Table 2-52. Type E5NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Table 2-53. Type E6 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
Table 2-54. Type E6NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Table 2-55. Type E7NM Class Exception Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
Table 2-56. Type E9 Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
Table 2-57. Type E9NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62Vol. 2A xxvCONTENTS
PAGE
Table 2-58. Type E10 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
Table 2-59. Type E10NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Table 2-60. Type E11 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
Table 2-61. Type E12 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
Table 2-62. Type E12NP Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
Table 2-63. TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68
Table 2-64. TYPE K21 Exception Definition (VEX-Encoded OpMask Instructions Addressing Memory) . . . . . . . . . . . . . . . . . .  . . . . . 2-69
Table 2-65. Intel® AMX Exception Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Table 3-2. Range of Bit Positions Specified by Bit Offset Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Table 3-3. Standard and Non-Standard Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Table 3-4. Intel 64 and IA-32 General Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Table 3-5. x87 FPU Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Table 3-6. SIMD Floating-Point Exceptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Table 3-7. Decision Table for CLI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-166
Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 3-182

Table 3-2. Pseudo-Op and CMPPD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183
Table 3-3. Pseudo-Op and VCMPPD Implementation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-184
Table 3-4. Pseudo-Op and CMPPS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-189
Table 3-5. Pseudo-Op and VCMPPS Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-190
Table 3-6. Pseudo-Op and CMPSD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-200
Table 3-7. Pseudo-Op and VCMPSD Implementation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-200
Table 3-8. Pseudo-Op and CMPSS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-204
Table 3-9. Pseudo-Op and VCMPSS Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-204
Table 3-8. Information Returned by CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-218
Table 3-9. Processor Type Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-241
Table 3-10. Feature Information Returned in the ECX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3-243
Table 3-11. More on Feature Information Returned in the EDX Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 3-246
Table 3-12. Encoding of CPUID Leaf 2 Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-248
Table 3-13. Processor Brand String Returned with Pentium 4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-255
Table 3-14. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-257
Table 3-15. DIV Action  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-323
Table 3-16. Results Obtained from F2XM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-359
Table 3-17. Results Obtained from FABS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-361
Table 3-18. FADD/FADDP/FIADD Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-363
Table 3-19. FBSTP Results  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-367
Table 3-20. FCHS Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-369
Table 3-21. FCOM/FCOMP/FCOMPP Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-375
Table 3-22. FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-378
Table 3-23. FCOS Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-381
Table 3-24. FDIV/FDIVP/FIDIV Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-385
Table 3-25. FDIVR/FDIVRP/FIDIVR Results  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-388
Table 3-26. FICOM/FICOMP Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-391
Table 3-27. FIST/FISTP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-398
Table 3-28. FISTTP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-401
Table 3-29. FMUL/FMULP/FIMUL Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-412
Table 3-30. FPATAN Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-415
Table 3-31. FPREM Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-417
Table 3-32. FPREM1 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-419
Table 3-33. FPTAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-421
Table 3-34. FSCALE Results  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-429
Table 3-35. FSIN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431
Table 3-36. FSINCOS Results  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-433
Table 3-37. FSQRT Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-435
Table 3-38. FSUB/FSUBP/FISUB Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-446
Table 3-39. FSUBR/FSUBRP/FISUBR Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-449
Table 3-40. FTST Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-451
Table 3-41. FUCOM/FUCOMP/FUCOMPP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-453
Table 3-42. FXAM Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-455CONTENTS
xxvi Vol. 2APAGE
Table 3-43. Non-64-Bit-Mode Layout of FXSAVE and FXRSTOR Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-462

Table 3-44. Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-463
Table 3-45. Recreating FSAVE Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-465
Table 3-46. Layout of the 64-Bit Mode FXSAVE64 Map (Requires REX.W = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-466
Table 3-47. Layout of the 64-Bit Mode FXSAVE Map (REX.W = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-467
Table 3-48. FYL2X Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-472
Table 3-49. FYL2XP1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-474
Table 3-50. Inverse Byte Listings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-477
Table 3-51. IDIV Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-498
Table 3-52. Decision Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-518
Table 3-53. Segment and Gate Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-583
Table 3-10. Memory Area Layout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-592
Table 3-54. Non-64-bit Mode LEA Operation with Address and Operand Size Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-595
Table 3-55. 64-bit Mode LEA Operation with Address and Operand Size Attributes . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 3-595
Table 3-56. Segment and Gate Descriptor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-619
Table 4-1. Source Data Format  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Table 4-2. Aggregation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Table 4-3. Aggregation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Table 4-4. Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Table 4-5. Output Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Table 4-6. Output Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Table 4-7. Comparison Result for Each Element Pair BoolRes[i.j] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Table 4-8. Summary of Imm8 Control Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Table 4-9. MUL Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-146
Table 4-10. MWAIT Extension Register (ECX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-161
Table 4-11. MWAIT Hints Register (EAX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-161
Table 4-12. Recommended Multi-Byte Sequence of NOP Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-165
Table 4-13. PCLMULQDQ Quadword Selection of Immediate Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-243
Table 4-14. Pseudo-Op and PCLMULQDQ Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-243
Table 4-15. MKTME_KEY_PROGRAM_STRUCT Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 4-271
Table 4-16. Effect of POPF/POPFD on the EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-402
Table 4-17. Repeat Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-555
Table 4-18. Rounding Modes and Encoding of Rounding Control (RC) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-573
Table 4-19. Decision Table for STI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-662
Table 4-20. TPAUSE Input Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-711
Table 4-21. UMWAIT Input Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-724
Table 5-1. Lower 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations. . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .5-2
Table 5-2. Upper 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .5-3
Table 5-3. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
Table 5-1. NaN Propagation Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-150
Table 5-2. VF[,N]MADD[132,213,231]PH Notation for Operands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 5-202
Table 5-3. Immediate Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-208
Table 5-4. VF[,N]MADD[132,213,231]SH Notation for Operands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 5-219
Table 5-5. VFMADDSUB[132,213,231]PH Notation for Odd and Even Elem ents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 5-233
Table 5-6. VF[,N]MSUB[132,213,231]PH Notation for Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-251
Table 5-7. VF[,N]MSUB[132,213,231]SH Notation for Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-265
Table 5-8. VFMSUBADD[132,213,231]PH Notation for Odd and Even Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 5-279
Table 5-4. Classifier Operations for VFPCLASSPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-329

Table 5-9. Classifier Operations for VFPCLASSPH/VFPCLASSSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 5-332
Table 5-5. VGETEXPPD/SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-356
Table 5-6. VGETEXPPH/VGETEXPSH Special Cases.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-359
Table 5-7. VGETEXPPS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-362
Table 5-8. GetMant() Special Float Values Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-373
Table 5-9. imm8 Controls for VGETMANTPH/VGETMANTSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 5-376
Table 5-10. GetMant() Special Float Values Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-377
Table 5-11. Pseudo-Op and VPCMP* Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-438
Table 5-12. Examples of VPTERNLOGD/Q Imm8 Boolean Function and Input Index Values. . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 5-617
Table 5-13. Signaling of Comparison Operation of One or More NaN Input Values and Effect of Imm8[3:2] . . . . . . . . . . . . . . . . . 5-626
Table 5-14. Comparison Result for Opposite-Signed Zero Cases for MIN, MIN_ABS, and MAX, MAX_ABS. . . . . . . . . . . . . . . . .  . . . 5-626Vol. 2A xxviiCONTENTS
PAGE
Table 5-15. Comparison Result of Equal-Magnitude Input Cases for MIN_ABS and MAX_ABS, (|a| = |b|, a>0, b<0). . . . . . . . . . .  . 5-626
Table 5-16. VRCP14PD/VRCP14SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-638
Table 5-17. VRCP14PS/VRCP14SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-642
Table 5-18. VRCPPH/VRCPSH Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-646
Table 5-19. VREDUCEPD/SD/PS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-650
Table 5-20. VREDUCEPH/VREDUCESH Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-653
Table 5-21. VRNDSCALEPD/SD/PS/SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-664
Table 5-22. Imm8 Controls for VRNDSCALEPH/VRNDSCALESH  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-667
Table 5-23. VRNDSCALEPH/VRNDSCALESH Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 5-667
Table 5-24. VRSQRT14PD Special Cases  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-679
Table 5-25. VRSQRT14SD Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-681
Table 5-26. VRSQRT14PS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-683
Table 5-27. VRSQRT14SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-685
Table 5-28. VRSQRTPH/VRSQRTSH Special Cases  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-686
Table 5-29. VSCALEFPD/SD/PS/SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-689
Table 5-30. Additional VSCALEFPD/SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-690
Table 5-31. VSCALEFPH/VSCALEFSH Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-692
Table 5-32. Additional VSCALEFPH/VSCALEFSH Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-692
Table 5-33. Additional VSCALEFPS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-694
Table 7-1. Layout of IA32_FEATURE_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7-2. GETSEC Leaf Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Table 7-3. GETSEC Capability Result Encoding (EBX = 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Table 7-4. Register State Initialization After GETSEC[ENTERACCS]  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 7-12
Table 7-5. IA32_MISC_ENABLE MSR Initialization by ENTERACCS and SENTER  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 7-13
Table 7-6. Register State Initialization After GETSEC[SENTER] and GETSEC[WAKEUP] . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 7-24
Table 7-7. SMX Reporting Parameters Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
Table 7-8. TXT Feature Extensions Flags  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Table 7-9. External Memory Types Using Parameter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
Table 7-10. Default Parameter Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
Table 7-11. Supported Actions for GETSEC[SMCTRL(0)] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Table 7-12. RLP MVMM JOIN Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
Table 8-1. Special Values Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Table 8-2. Special Values Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Table 8-3. VRCP28PD Special Cases  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
Table 8-4. VRCP28SD Special Cases  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
Table 8-5. VRCP28PS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Table 8-6. VRCP28SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

Table 8-7. VRSQRT28PD Special Cases  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Table 8-8. VRSQRT28SD Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
Table 8-9. VRSQRT28PS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
Table 8-10. VRSQRT28SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
Table A-1. Superscripts Utilized in Opcode Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-6
Table A-2. One-byte Opcode Map: (00H — F7H) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-7
Table A-3. Two-byte Opcode Map: 00H — 77H (First Byte is 0FH) *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .A-9
Table A-4. Three-byte Opcode Map: 00H — F7H (First Two Bytes are 0F 38H) *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
Table A-5. Three-byte Opcode Map: 00H — F7H (First two bytes are 0F 3AH) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group Number * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18
Table A-7. D8 Opcode Map When ModR/M Byte is Within 00H to BFH *  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . A-20
Table A-8. D8 Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
Table A-9. D9 Opcode Map When ModR/M Byte is Within 00H to BFH *  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . A-21
Table A-10. D9 Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . A-22
Table A-11. DA Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
Table A-12. DA Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
Table A-13. DB Opcode Map When ModR/M Byte is Within 00H to BFH *  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
Table A-14. DB Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . A-24
Table A-15. DC Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . A-24
Table A-16. DC Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . A-25
Table A-17. DD Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
Table A-18. DD Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26CONTENTS
xxviii Vol. 2APAGE
Table A-19. DE Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . A-26
Table A-20. DE Opcode Map When ModR/M Byte is Outside 00H to BFH *  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . A-27
Table A-21. DF Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . A-27
Table A-22. DF Opcode Map When ModR/M Byte is Outside 00H to BFH *  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . A-28
Table B-1. Special Fields Within Instruction Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
Table B-2. Encoding of reg Field When w Field is Not Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-3
Table B-3. Encoding of reg Field When w Field is Present in Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-3
Table B-4. Encoding of reg Field When w Field is Not Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Table B-5. Encoding of reg Field When w Field is Present in Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Table B-6. Encoding of Operand Size (w) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Table B-7. Encoding of Sign-Extend (s) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Table B-8. Encoding of the Segment Register (sreg) Field  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Table B-9. Encoding of Special-Purpose Register (eee) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Table B-10. Encoding of Conditional Test (tttn) Field  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
Table B-11. Encoding of Operation Direction (d) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .B-7
Table B-12. Notes on Instruction Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-7
Table B-14. Special Symbols  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . B-18
Table B-16. Pentium® Processor Family Instruction Formats and Encodings, Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Table B-17. Pentium® Processor Family Instruction Formats and Encodings, 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Table B-18. Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Table B-19. MMX Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Table B-20. Formats and Encodings of XSAVE/XRSTOR/XGETBV/XSETBV Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
Table B-21. Formats and Encodings of P6 Family Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
Table B-22. Formats and Encodings of SSE Floating-Point Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . B-42
Table B-23. Formats and Encodings of SSE Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . B-46
Table B-25. Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47

Table B-24. Format and Encoding of SSE Cacheability & Memory Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . B-48
Table B-27. Formats and Encodings of SSE2 Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-52
Table B-28. Format and Encoding of SSE2 Cacheability Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . B-56
Table B-29. Formats and Encodings of SSE3 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . B-57
Table B-30. Formats and Encodings for SSE3 Event Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-57
Table B-31. Formats and Encodings for SSE3 Integer and Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-57
Table B-32. Formats and Encodings for SSSE3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . B-58
Table B-33. Formats and Encodings of AESNI and PCLMULQDQ Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-61
Table B-34. Special Case Instructions Promoted Using REX.W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-61
Table B-35. Encodings of SSE4.1 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64
Table B-36. Encodings of SSE4.2 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-69
Table B-37. Encodings of AVX instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-71
Table B-38. General Floating-Point Instruction Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-108
Table B-39. Floating-Point Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . B-108
Table B-40. Encodings for VMX Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-112
Table B-41. Encodings for SMX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113
Table C-1. Simple Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-2
Table C-2. Composite Intrinsics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14Vol. 2A 1-1CHAPTER 1
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D: Instruction Set 
Reference (order numbers 253666, 253667, 326018, and 334569), is part of a set that describes the architecture 
and programming environment of all Intel 64 and IA-32 ar chitecture processors. Other volumes in this set are:
•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (Order 
Number 253665).
•The Intel® 64 and IA-32 Architectures Software Develope r’s Manual, Volumes 3A, 3B, 3C, & 3D: System 
•The Intel® 64 and IA-32 Architectures Software Develo per’s Manual, Volume 4: Model-Specific Registers 
(order number 335592).
Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, describes the instruction set of the processor and the opcode struc-
utives. The Intel® 64 and IA-32 Architectures Software Develope r’s Manual, Volumes 3A, 3B, 3C, & 3D, describes 
include: 
•Intel® Xeon® processor 7100 series1-2 Vol. 2AABOUT THIS MANUAL
•Intel® Core™ i5 processor
•2nd generation Intel® Xeon® Scalable Processor FamilyVol. 2A 1-3ABOUT THIS MANUAL
•3rd generation Intel® Xeon® Scalable Processor Family 
Pro, Pentium® II, Pentium® III, and Pentium® III Xeon® processors. 

The Intel Atom® processor Z8000 series is based on the Airmont microarchitecture.1-4 Vol. 2AABOUT THIS MANUAL
1.2 OVERVIEW OF VOLUME 2A, 2B , 2C, AND 2D: INSTRUCTION SET 
REFERENCE
A description of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, 
content follows:Vol. 2A 1-5ABOUT THIS MANUAL
Chapter 1  — About This Manual.  Gives an overview of all ten volumes of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel® 
manuals and documentation of interest to programmers and hardware designers.
Chapter 2 — Instruction Format. Describes the machine-level instruction format used for all IA-32 instructions 
and gives the allowable encodings of prefixes, the operan d-identifier byte (ModR/M byte), the addressing-mode 
specifier byte (SIB byte), and th e displacement and immediate bytes.
Chapter 3 — Instruction Set Reference, A-L. Describes Intel 64 and IA-32 instructions in detail, including an 
algorithmic description of operations, the effect on flags,  the effect of operand- and address-size attributes, and 
the exceptions that may be generated. The instructions ar e arranged in alphabetical order. General-purpose, x87 
FPU, Intel MMX™ technology, SSE/SSE2/SSE3/SSSE3/SSE4 extensions, and system instructions are included.
Chapter 4 — Instruction Set Reference, M-U. Continues the description of Intel 64 and IA-32 instructions 
started in Chapter 3. It starts Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
Chapter 5 — Instruction Set Reference, V. Continues the description of Intel 64 and IA-32 instructions started 
in chapters 3 and 4. This chapter starts Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2C.
Chapter 6 — Instruction Set Reference, W-Z. Continues the description of Intel 64 and IA-32 instructions 
started in chapters 3, 4, and 5. It provides the balance of the alphabetized list of instructions and starts Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 2D.
Chapter 7 — Safer Mode Extensions Reference. Describes the safer mode extensions (SMX). SMX is intended 
for a system executive to support launching a measured en vironment in a platform where the identity of the soft-
ware controlling the platform hardware can be measured for the purpose of making trust decisions.

2C.
Chapter 8— Instruction Set Reference Uniq ue to Intel® Xeon Phi™ Processors. Describes the instruction 
set that is unique to Intel® Xeon Phi™ processors based on the Knights Landing and Knights Mill microarchitec-
tures. The set is not supported in any other Intel processors.
Appendix A — Opcode Map. Gives an opcode map for the IA-32 instruction set.
Appendix B — Instruction Formats and Encodings. Gives the binary encoding of each form of each IA-32 
Appendix C — Intel® C/C ++ Compiler Intrinsics and Functional Equivalents. Lists the Intel® C/C ++ compiler 
intrinsics and their assembly code equivalents for ea ch of the IA-32 MMX and SSE/SSE2/SSE3 instructions.
hexadecimal and binary numbers. A review of this notation makes the manual easier to read.
two raised to the power of the bit position. IA-32 processo rs are “little endian” machines; this means the bytes of 
a word are numbered starting from the least signif icant byte. Figure 1-1 illustrates these conventions.1-6 Vol. 2AABOUT THIS MANUAL
able. Software should follow these guidelines in dealing with reserved bits:
•Do not depend on the states of any reserved bits when testing the values of registers which contain such bits. Mask out the reserved bits before testing.
•Do not depend on the ability to retain in formation written into any reserved bits.
•When loading a register, always load the reserved bits with  the values indicated in the documentation, if any, or 
reload them with values previous ly read from the same register.
NOTE
Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon 
the values of reserved register bits will make software dependent upon the unspecified manner in 
which the processor handles these bits. Programs that depend upon reserved values risk incompat-ibility with future processors.
1.3.3 Instruction Operands
where:
•The operands argument1 , argument2 , and argument3  are optional. There may be from zero to three operands, 
depending on the opcode. When present, they take the fo rm of either literals or identifiers for data items. 
Operand identifiers are either reserved names of regi sters or are assumed to be assigned to data items 
When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left 
For example:Figure 1-1.  Bit and Byte OrderByte 3Data Structure 
28
24
20
16
12
8
40
Address
AddressVol. 2A 1-7ABOUT THIS MANUAL
1.3.4 Hexadecimal an d Binary Numbers
example, F82EH). A hexadecimal digit is a character from the follo wing set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, 
E, and F.
arise.
1.3.5 Segmented Addressing
Whether one or more bytes are being accessed, a byte addre ss is used to locate the byte or bytes in memory. The 
independent address spaces, called segments . For example, a program can keep its code (instructions) and stack 
refer to the stack space. The following notation is  used to specify a byte address within a segment:
register:
DS:FF79H
CS:EIP
divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other condi-
reported. Under some conditions, exceptions which produc e error codes may not be able to report an accurate 
code. In this case, the error code is zero, as shown below for a general-protection exception:
#GP(0)
1.3.7 A New Syntax for CPUID, CR, and MSR Values
See Figure 1-2.1-8 Vol. 2AABOUT THIS MANUAL
See also: 
•Software developer resources, guidance, and insights for security advisories:
https://software.intel.com/security-software-guidance/
http://software.intel.com/en-us/articles/intel-compilers/Figure 1-2.  Syntax for CPUID,  CR, and MSR Data PresentationInput value for EAX register
Feature flag or field nam e with bit position(s)
SDM29002Vol. 2A 1-9ABOUT THIS MANUAL

tions.pdf
https://software.intel.com/en-us
•Developer centers:http://www.intel.com/content/www/us/en/har dware-developers/developer-centers.html
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm1-10 Vol. 2AABOUT THIS MANUALVol. 2A 2-1CHAPTER 2
This chapter describes the instruction format for all Intel 64 and IA-32 processors. The instruction format for 
protected mode, real-address mode and virtual-8086 mode is described in Section 2.1. Increments provided for IA-
32e mode and its sub-modes are described in Section 2.2.
2.1 INSTRUCTION FORMAT FOR PROT ECTED MODE, REAL-ADDRESS MODE, 
AND VIRTUAL-8086 MODE
The Intel 64 and IA-32 architectures instruction encodings are subsets of the format shown in Figure 2-1. Instruc-
tions consist of optional instruction prefixes (in any order), primary opcode byte s (up to three bytes), an 
addressing-form specifier (if required) consisting of th e ModR/M byte and sometimes the SIB (Scale-Index-Base) 
byte, a displacement (if required), and an immediate data field (if required).
2.1.1 Instruction Prefixes
Instruction prefixes are divided into four groups, each with a set of allowable prefix codes. For each instruction, it 
is only useful to include up to one prefix code from each of the four groups (Groups 1, 2, 3, 4). Groups 1 through 4 
may be placed in any order relative to each other.
•Group 1
— Lock and repeat prefixes:
•LOCK prefix is encoded using F0H.
•REPNE/REPNZ prefix is encoded using F2H. Repeat -Not-Zero prefix applies only to string and 
input/output instructions. (F2H is also used as a mandatory prefix for some instructions.)
•REP or REPE/REPZ is encoded using F3H. The repeat prefix applies only to string and input/output 
instructions. (F3H is also used as a mandatory prefix for some instructions.)Figure 2-1.  Intel 64 and IA-3 2 Architectures Instruction FormatInstruction
PrefixesOpcode ModR/M SIB Displacement Immediate
Mod R/MReg/
Opcode0 2 76 5 3
Scale Base0 2 76 5 3
IndexImmediate
data of
1, 2, or 4
bytes or none3Address
of 1, 2, or 4
bytes or none31 byte
(if required)1 byte(if required) 1-, 2-, or 3-byteopcode Prefixes of1 byte each
(optional)1, 2
1. The REX prefix is optional, but if used mu st be immediately before the opcode; see Section 
2.2.1, “REX Prefixes” for additional information.
2. For VEX encoding information, see Section 2. 3, “Intel® Advanced Vector Extensions (Intel® 
AVX)”.
3. Some rare instructions can take an 8B immediate or 8B displacement.2-2 Vol. 2AINSTRUCTION FORMAT
— BND prefix is encoded using F2H if the following conditions are true:
•CPUID.(EAX=07H, ECX=0):EBX .MPX[bit 14] is set.
•BNDCFGU.EN and/or IA32_BNDCFGS.EN is set.
•When the F2 prefix precedes a near CALL, a near RET,  a near JMP, a short Jcc, or a near Jcc instruction 
(see Appendix E, “Intel® Memory Protection Extensions,” of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 1).
•Group 2
— Segment override prefixes:
•2EH—CS segment override (use with any branch instruction is reserved).
•36H—SS segment override prefix (use with any branch instruction is reserved).
•3EH—DS segment override prefix (use with any branch instruction is reserved).
•26H—ES segment override prefix (use with  any branch instruction is reserved).
•64H—FS segment override prefix (use with  any branch instruction is reserved).
•65H—GS segment override prefix (use with  any branch instruction is reserved).
— Branch hints1:
•2EH—Branch not taken (used only with J cc instructions).
•3EH—Branch taken (used only with J cc instructions).
•Group 3
•Operand-size override prefix is encoded using 66H ( 66H is also used as a mandatory prefix for some 
instructions).
•Group 4
•67H—Address-size override prefix.
The LOCK prefix (F0H) forces an operation that ensures exclusive use of shared memory in a multiprocessor envi-
ronment. See “LOCK—Assert LOCK# Signal Prefix” in Chapte r 3, “Instruction Set Reference, A-L,” for a description 
of this prefix. 
Repeat prefixes (F2H, F3H) cause an instruction to be re peated for each element of a string. Use these prefixes 
only with string and I/O instructions (MOVS, CMPS, SCAS , LODS, STOS, INS, and OUTS). Use of repeat prefixes 
and/or undefined opcodes with other Intel 64 or IA-32 inst ructions is reserved; such use may cause unpredictable 
behavior.
Some instructions may use F2H,F3H as a mandatory prefix to express distinct functionality.
Branch hint prefixes (2EH, 3EH) allow a program to give a hint to the processor about the most likely code path for 
a branch. Use these prefixes only with conditional branch instructions (J cc). Other use of branch hint prefixes 
and/or other undefined opcodes with Intel 64 or IA-32 inst ructions is reserved; such use may cause unpredictable 
behavior.
The operand-size override prefix allows  a program to switch between 16- and 32 -bit operand sizes. Either size can 
be the default; use of the prefix selects the non-default size. 
Some SSE2/SSE3/SSSE3/SSE4 instructions  and instructions using a three-byte sequence of primary opcode bytes 
may use 66H as a mandatory prefix to express distinct functionality.
Other use of the 66H prefix is reserved; such use may cause unpredictable behavior.
The address-size override prefix (67H) allows programs to  switch between 16- and 32-bit addressing. Either size 
can be the default; the prefix selects the non-default size . Using this prefix and/or other undefined opcodes when 
operands for the instruction do not reside in memory is reserved; such use may cause unpredictable behavior.
1. Some earlier microarchitectures used these as branch hints, but recent generations have not and they are reserved for future hint 
usage.Vol. 2A 2-3INSTRUCTION FORMAT
2.1.2 Opcodes
A primary opcode can be 1, 2, or 3 bytes in length. An additional 3-bit opcode field is sometimes encoded in the 
ModR/M byte. Smaller fields can be defined within the pr imary opcode. Such fields define the direction of opera-
tion, size of displacements, register encoding, condition codes, or sign extension. Encoding fields used by an 
opcode vary depending on the class of operation.
Two-byte opcode formats for general-purpose and SIMD  instructions consist of one of the following: 
•An escape opcode byte 0FH as the primary opcode and a second opcode byte.
•A mandatory prefix (66H, F2H, or F3H), an escape opco de byte, and a second opcode byte (same as previous 
bullet).
For example, CVTDQ2PD consists of the following sequence: F3  0F E6. The first byte is a mandatory prefix (it is not 
considered as a repeat prefix). 
Three-byte opcode formats for general-purpose and SI MD instructions consist of one of the following: 
•An escape opcode byte 0FH as the primary opcode, plus two additional opcode bytes.
•A mandatory prefix (66H, F2H, or F3 H), an escape opcode byte, plus two additional opcode bytes (same as 
previous bullet).
For example, PHADDW for XMM registers consists of the following sequence: 66 0F 38 01. The first byte is the 
mandatory prefix.
Valid opcode expressions are define d in Appendix A and Appendix B.
2.1.3 ModR/M and SIB Bytes
Many instructions that refer to an operand in memory ha ve an addressing-form specifier byte (called the ModR/M 
byte) following the primary opcode. The ModR/M byte contains three fields of information:
•The mod field combines with the r/m field to form 32 possible values: eight registers and 24 addressing modes.
•The reg/opcode  field specifies either a register number or thre e more bits of opcode information. The purpose 
of the reg/opcode field is sp ecified in the primary opcode.
•The r/m field can specify a register as an operand or it can be combined with the mod field to encode an 
addressing mode. Sometimes, certain combinations of the mod field and the r/m field are used to express 
opcode information for some instructions.
Certain encodings of the ModR/M byte require a second ad dressing byte (the SIB byte ). The base-plus-index and 
scale-plus-index forms of 32-bit addressing require the SIB byte. The SIB byte includes the following fields:
•The scale field specifies the scale factor.
•The index  field specifies the register number of the index register.
•The base field specifies the register number of the base register.

See Section 2.1.5 for the encodings of the ModR/M and SIB bytes.
2.1.4 Displacement and Immediate Bytes
Some addressing forms include a displacement immediately following the ModR/M byte (or the SIB byte if one is 
present). If a displacement is required, it can be 1, 2, or 4 bytes.
If an instruction specifies an immediate operand, the op erand always follows any displacement bytes. An imme-
diate operand can be 1, 2 or 4 bytes.2-4 Vol. 2AINSTRUCTION FORMAT
2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes
The values and corresponding addressing forms of the Mo dR/M and SIB bytes are shown in Table 2-1 through Table 
2-3: 16-bit addressing forms specified by the ModR/M by te are in Table 2-1 and 32-bit addressing forms are in 
Table 2-2. Table 2-3 shows 32-bit addressing forms specif ied by the SIB byte. In cases where the reg/opcode field 
in the ModR/M byte represents an extended op code, valid encodings are shown in Appendix B.
In Table 2-1 and Table 2-2, the Effective Address column lis ts 32 effective addresses that can be assigned to the 
first operand of an instruction by using the Mod and R/M fields of the ModR/M byte. The first 24 options provide 
ways of specifying a memory location; the last eight (Mod  = 11B) provide ways of specifying general-purpose, MMX 
technology and XMM registers. 
The Mod and R/M columns in Table 2-1 and Table 2-2 give th e binary encodings of the Mod and R/M fields required 
to obtain the effective address listed in the first column . For example: see the row in dicated by Mod = 11B, R/M = 
000B. The row identifies the general-purpose registers EA X, AX or AL; MMX technology register MM0; or XMM 
register XMM0. The register used is determined by  the opcode byte and the operand-size attribute.
Now look at the seventh row in either table (labeled “REG =”). This row specifies the use of the 3-bit Reg/Opcode 
field when the field is used to give the location of a second operand. The second operand must be a general-
purpose, MMX technology, or XMM register. Rows one thro ugh five list the registers that may correspond to the 
value in the table. Again, the register used is determined by the opcode byte along with the operand-size attribute. 
If the instruction does not require a second operand, then  the Reg/Opcode field may be used as an opcode exten-
sion. This use is represented by the sixth row in the tables (labeled “/digit (Opcode)”). Note that values in row six are represented in decimal form.
The body of Table 2-1 and Table 2-2 (under the label “Value of ModR/M Byte (in Hexadecimal)”) contains a 32 by 
8 array that presents all of 256 values of the ModR/M byte  (in hexadecimal). Bits 3, 4, and 5 are specified by the 
column of the table in which a byte resides. The row specif ies bits 0, 1, and 2; and bits 6 and 7. The figure below 
demonstrates interpretation of one table value.
Figure 2-2.  Table Interpretation of ModR/M Byte (C8H)Mod 11
RM 000
REG = 001
C8H 11 001000/digit (Opcode);Vol. 2A 2-5INSTRUCTION FORMAT
NOTES:
1. The default segment register is SS for the effective addre sses containing a BP index, DS  for other effe ctive addresses.
2. The disp16 nomenclature denotes a 16-bit  displacement that follows  the ModR/M byte and that  is added to the index. 
3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte and that is sign-extended and added to the
index. Table 2-1.  16-Bit Addressing  Forms with the ModR/M Byte
r8(/r)
r16(/r)r32(/r)mm(/r)xmm(/r)(In decimal) /digit (Opcode)(In binary) REG =AL
AXEAXMM0XMM00000CL
CXECXMM1XMM11001DL
DXEDXMM2XMM22010BL
BXEBXMM3XMM33011AH
SPESPMM4XMM44100CH
BP
1
EBPMM5XMM55101DH
SIESIMM6XMM66110BH
DIEDIMM7XMM77111
Effective Address Mod R/M Value of  ModR/M Byte (in Hexadecimal)
[BX+SI]
[BX+DI]
[BP+SI]
[BP+DI]
[SI][DI]disp16
2
[BX]00 000
00101001110010111011100
0102030405060708
090A0B0C0D0E0F10
1112131415161718
191A1B1C1D1E1F20
2122232425262728
292A2B2C2D2E2F30
3132333435363738
393A3B3C3D3E3F
[BX+SI]+disp8
3
[BX+DI]+disp8
[BP+SI]+disp8
[BP+DI]+disp8
[SI]+disp8
[DI]+disp8
[BP]+disp8
[BX]+disp801 000
001
01001110010111011140
41
42434445464748
49
4A4B4C4D4E4F50
51
52535455565758
59
5A5B5C5D5E5F60
61
62636465666768
69
6A6B6C6D6E6F70
71
72737475767778
79
7A7B7C7D7E7F
[BX+SI]+disp16
[BX+DI]+disp16
[BP+SI]+disp16
[BP+DI]+disp16
[SI]+disp16
[DI]+disp16
[BP]+disp16
[BX]+disp1610 000
00101001110010111011180
8182838485868788
898A8B8C8D8E8F90
9192939495969798
999A9B9C9D9E9FA0
A1A2A3A4A5A6A7A8
A9AAABACADAEAFB0
B1
B2B3B4B5B6B7B8
B9BABBBCBDBEBF
EAX/AX/AL/MM0/XMM0
ECX/CX/CL/MM1/XMM1EDX/DX/DL/MM2/XMM2EBX/BX/BL/MM3/XMM3ESP/SP/AHMM4/XMM4EBP/BP/CH/MM5/XMM5ESI/SI/DH/MM6/XMM6EDI/DI/BH/MM7/XMM711 000
001010011100101110111C0
C1C2C3C4C5C6C7C8
C9CACBCCCDCECFD0
D1D2D3D4D5D6D7D8
D9DADBDCDDDEDFE0
E1E2E3E4E5E6E7E8
E9EAEBECEDEEEFF0
F1F2F3F4F5F6F7F8
F9FAFBFCFDFEFF2-6 Vol. 2AINSTRUCTION FORMAT
NOTES:
1. The [--][--] nomencla ture means a SIB foll ows the ModR/M byte.
2. The disp32 nomenclature denotes a 32-bit displacement that follows the ModR/M byte (or the SIB byte if one is present) and th at is
added to the index.
3. The disp8 nomenclature denotes an  8-bit displacement that follows the ModR/M byte  (or the SIB byte if one is present) and tha t is
sign-extended and added to the index.
Table 2-3 is organized to give 256 possible values of the SIB byte (in hexadecimal). General purpose registers used 
as a base are indicated across the top of the table, along with corresponding values for the SIB byte’s base field. 
Table rows in the body of the table indicate the register used  as the index (SIB byte bits 3, 4, and 5) and the scaling 
factor (determined by SIB byte bits 6 and 7).Table 2-2.  32-Bit Addressing Forms with the ModR/M Byte
r8(/r)
BPEBPMM5XMM55101DH
[EAX]
[ECX][EDX][EBX][--][--]
1
disp322
[ESI][EDI]00 000
[EAX] +disp8
3
[ECX] +disp8
[EDX] +disp8
[EBX] +disp8
[--][--] +disp8
[EBP] +disp8
[ESI] +disp8
[EDI] +disp801 000
00101001110010111011140
4142434445464748
494A4B4C4D4E4F50
5152535455565758
595A5B5C5D5E5F60
6162636465666768
696A6B6C6D6E6F70
7172737475767778
797A7B7C7D7E7F
[EAX] +disp32
[ECX] +disp32
[EDX] +disp32
[EBX] +disp32
[--][--] +disp32
[EBP] +disp32
[ESI] +disp32
[EDI] +disp3210 000
B1B2B3B4B5B6B7B8
ECX/CX/CL/MM/XMM1EDX/DX/DL/MM2/XMM2EBX/BX/BL/MM3/XMM3ESP/SP/AH/MM4/XMM4EBP/BP/CH/MM5/XMM5ESI/SI/DH/MM6/XMM6EDI/DI/BH/MM7/XMM711 000
F9
FAFBFCFDFEFFVol. 2A 2-7INSTRUCTION FORMAT
NOTES:
1. The [*] nomenclature means a di sp32 with no base if the MOD is 00B. Otherwise, [*] means disp8 or disp32 + [EBP]. This provid es the
following address modes:
MOD bits Effective Address
00 [scaled index] + disp32 
01 [scaled index] + disp8 + [EBP]
10  [scaled index] + disp32 + [EBP]
2.2 IA-32E MODE
IA-32e mode has two sub-modes. These are: 
•Compatibility Mode.  Enables a 64-bit operating system to run most legacy protected mode software 
•64-Bit Mode. Enables a 64-bit operating system to run applications written to access 64-bit address space. 
2.2.1 REX Prefixes
REX prefixes are instruction- prefix bytes used in 64-bit mode. They do the following:
•Specify GPRs and SSE registers.Table 2-3.  32-Bit Addressing Forms with the SIB Byte
r32
(In decimal) Base =
(In binary) Base =EAX
0000ECX
1001EDX
2010EBX
3011ESP
4100[*]
5101ESI
6110EDI
7111
Scaled Index SS Index Value of SIB Byte (in Hexadecimal)
[EAX]
[ECX][EDX][EBX]none[EBP][ESI][EDI]00 000
0810182028303801
0911192129313902
0A121A222A323A03
0B131B232B333B04
0C141C242C343C05
0D151D252D353D06
0E161E262E363E07
0F171F272F373F
[EAX*2]
[ECX*2][EDX*2][EBX*2]none[EBP*2][ESI*2][EDI*2]01 000
4850586068707841
4951596169717942
4A525A626A727A43
4B535B636B737B44
4C545C646C747C45
4D555D656D757D46
4E565E666E767E47
4F575F676F777F
[EAX*4]
[ECX*4][EDX*4][EBX*4]none[EBP*4][ESI*4][EDI*4]10 000
889098A0A8B0B881
899199A1A9B1B982
8A929AA2AAB2BA83
8B939BA3ABB3BB84
8C949CA4ACB4BC85
8D959DA5ADB5BD86
8E969EA6AEB6BE87
8F979FA7AFB7BF
[EAX*8]
[ECX*8][EDX*8][EBX*8]none[EBP*8][ESI*8][EDI*8]11 000
C8D0D8E0E8F0F8C1
C9D1D9E1E9F1F9C2
CAD2DAE2EAF2FAC3
CBD3DBE3EBF3FBC4
CCD4DCE4ECF4FCC5
CDD5DDE5EDF5FDC6
CED6DEE6EEF6FEC7
CF
D7DFE7EFF7FF2-8 Vol. 2AINSTRUCTION FORMAT
•Specify 64-bit operand size.
•Specify extended control registers.

[EAX]
[EAX*2]
[EAX*4]
[EAX*8]
CF
Not all instructions require a REX prefix in 64-bit mode. A prefix is necessary only if an instruction references one 
of the extended registers or uses a 64-bit operand. If a REX prefix is used when it has no meaning, it is ignored, as 
are individual bits in the pref ix when they have no meaning.
Only one meaningful REX prefix is allo wed per instruction. If used, the REX prefix byte must immediately precede 
the opcode byte or the escape opcode byte (0FH). When a REX prefix is used in conj unction with an instruction 
containing a mandatory prefix, the mandatory prefix must come before the REX so the REX prefix can immediately 
precede the opcode or the escape byte. For example, CVTDQ2PD with a REX prefix should have REX placed 
between F3 and 0F E6. Other placements are ignored. The in struction-size limit of 15 bytes still applies to instruc-
tions with a REX prefix. See Figure 2-3.
2.2.1.1  Encoding
Intel 64 and IA-32 instruction formats specify up to three re gisters by using 3-bit fields in the encoding, depending 
on the format:
•ModR/M: the reg and r/m fields of the ModR/M byte.
•ModR/M with SIB: the reg field of the ModR/M byte, the base and index fields of the SIB (scale, index, base) 
byte.
•Instructions without ModR/M: the reg field of the opcode.
In 64-bit mode, these formats do not change. Bits needed to define fields in the 64-bit context are provided by the 
addition of REX prefixes.
2.2.1.2  More on REX Prefix Fields 
REX prefixes are a set of 16 opcodes that span one row of the opcode map and occupy entries 40H to 4FH. These 
opcodes represent valid instructions (INC or DEC) in IA-32 operating modes and in compatibility mode. In 64-bit mode, the same opcodes represent the instruction prefix  REX and are not treated as individual instructions. 
The single-byte-opcode forms of the INC/DEC instructions  are not available in 64-bit mode. INC/DEC functionality 
is still available using ModR/M forms of the same instructions (opcodes FF/0 and FF/1). 
See Table 2-4 for a summary of the REX prefix format. Fi gure 2-4 though Figure 2-7 show  examples of REX prefix 
fields in use. Some combinations of REX prefix fields are invalid. In such cases, the pr efix is ignored. Some addi-
tional information follows:
•Setting REX.W can be used to determine the operand size  but does not solely determine operand width. Like 
the 66H size prefix, 64-bit operand size overri de has no effect on byte-specific operations. 
•For non-byte operations: if a 66H prefix is us ed with prefix (REX.W = 1), 66H is ignored. 
•If a 66H override is used with REX and REX.W = 0, the operand size is 16 bits.
•REX.R modifies the ModR/M reg field when that field en codes a GPR, SSE, control or debug register. REX.R is 
ignored when ModR/M specifies other registers or defines an extended opcode.
•REX.X bit modifies the SIB index field.Figure 2-3.  Prefix Ordering in 64-bit ModeREX
Immediate data 
of 1, 2, or 4 
bytes or noneAddress displacement of 
1, 2, or 4 bytes 1 byte
(if required)1 byte(if required)1-, 2-, or 
3-byte opcode(optional) Grp 1, Grp 
2, Grp 3, 
Grp 4
(optional)Legacy
PrefixOpcode ModR/M SIB Displacement ImmediatePrefixesVol. 2A 2-9INSTRUCTION FORMAT
•REX.B either modifies the base in the ModR/M r/m field or SIB base field; or it modifies the opcode reg field 
used for accessing GPRs.
Table 2-4.  REX Prefix Fields [BITS: 0100WRXB]
Field Name Bit Position Definition
- 7:4 0100
W 3 0 = Operand size determined by CS.D
1 = 64 Bit Operand Size
R 2 Extension of the ModR/M reg field
X 1 Extension of the SIB index field
B 0 Extension of the ModR/M r/m field, SIB base field, or Opcode reg field
Figure 2-4.  Memory Addressing Without an SIB Byte; REX.X Not Used
Figure 2-5.  Register-Register Addressi ng (No Memory Operand); REX.X Not UsedREX PREFIX  
0100WR0BOpcode mod
≠11reg r/m
Rrrr BbbbModRM Byte
rrr bbb
OM17Xfig1-3
REX PREFIX  
11reg r/m
rrr bbb
OM17Xfig1-42-10 Vol. 2AINSTRUCTION FORMAT
In the IA-32 architecture, byte registers (AH, AL, BH, BL, CH, CL, DH, and DL) are encoded in the ModR/M byte’s 
reg field, the r/m field or the opcode reg field as regi sters 0 through 7. REX prefixes provide an additional 
addressing capability for byte-registers that makes the leas t-significant byte of GPRs av ailable for byte operations.
Certain combinations of the fields of the ModR/M byte and the SIB byte have special meaning for register encod-
ings. For some combinations, fields expanded by the RE X prefix are not decoded. Table 2-5 describes how each 
case behaves.Figure 2-6.  Memory Addressing With a SIB Byte
Figure 2-7.  Register Operand Coded in Opcode Byte; REX.X & REX.R Not Usedmod
≠ 11ModRM Byte
r/m
100reg
rrrscale
ssSIB Byte
REX PREFIX  
0100WRXBOpcode
Rrrrbase
Bbbbbbb
Xxxxindex
xxx
OM17Xfig1-5
REX PREFIX  
0100W00BOpcode
Bbbbreg
bbb
OM17Xfig1-6Vol. 2A 2-11INSTRUCTION FORMAT
2.2.1.3  Displacement 
Addressing in 64-bit mode uses existing 32-bit ModR/M  and SIB encodings. The ModR/M and SIB displacement 
sizes do not change. They remain 8 bits or  32 bits and are sign-extended to 64 bits.
2.2.1.4  Direct Memory-Offset MOVs
In 64-bit mode, direct memory-offset forms of the MOV instruction are extended to specify a 64-bit immediate 
absolute address. This address is called a moffset. No prefix is needed to specify this 64-bit memory offset. For these MOV instructions, the size of the memory offset follow s the address-size default (64 bits in 64-bit mode). See 
Table 2-6.
2.2.1.5  Immediates 
In 64-bit mode, the typical size of immediate operands remains 32 bits. When the operand size is 64 bits, the 
processor sign-extends all immediates to 64 bits prior to their use. 
Support for 64-bit immediate operands is accomplished by  expanding the semantics of the existing move (MOV 
reg, imm16/32) instructions. These instructions (opcodes B8H – BFH) move 16-bits or 32-bits of immediate data 
(depending on the effective operand size) into a GPR. When the effective operand size is 64 bits, these instructions 
can be used to load an immediate into a GPR. A REX prefix  is needed to override the 32-bit default operand size to 
a 64-bit operand size. 
48 B8 8877665544332211 MOV RAX,1122334455667788HTable 2-5.  Special Cases of REX Encodings 
ModR/M or 
SIB Sub-field
EncodingsCompatibility Mode 
OperationCompatibility Mode 
Implications Additional Implications
ModR/M Byte mod ? 11 SIB byte present. SIB byte required for 
ESP-based addressing.REX prefix adds a fourth bit (b) which is not decoded 
(don't care).
SIB byte also required for R12-based addressing.r/m = 
b*100(ESP)
ModR/M Byte mod = 0 Base register not 
used.EBP without a 
displacement must be done using 
mod = 01 with 
displacement of 0.REX prefix adds a fourth bit (b) which is not decoded 
Using RBP or R13 without displacement must be done 
using mod = 01 with a displacement of 0.r/m = 
b*101(EBP)
SIB Byte index = 
0100(ESP)Index register not 
used.ESP cannot be used as 
an index register.REX prefix adds a fourth bit (b) which is decoded.
There are no additional implications. The expanded 
index field allows distinguishing RSP from R12, 
therefore R12 can be used as an index.
SIB Byte base = 
0101(EBP)Base register is 
unused if mod = 0.Base register depends 
on mod encoding.REX prefix adds a fourth bit (b) which is not decoded.
This requires explicit disp lacement to be used with 
EBP/RBP or R13.
NOTES:
* Don’t care about value of REX.B
Table 2-6.  Direct Memory Offset Form of MOV
Opcode Instruction
A0 MOV AL, moffset
A1 MOV EAX, moffsetA2 MOV moffset, AL
A3 MOV moffset, EAX2-12 Vol. 2AINSTRUCTION FORMAT
2.2.1.6  RIP-Relative Addressing
A new addressing form, RIP-relative (relative instruction- pointer) addressing, is implemented in 64-bit mode. An 
effective address is formed by adding displace ment to the 64-bit RIP of the next instruction.
In IA-32 architecture and compatibility mode, addressing relative to the instru ction pointer is available only with 
control-transfer instructions. In 64-bit mode, instructions that use ModR/M addressing can use RIP-relative 
addressing. Without RIP-relative addressing, all ModR/M modes address memo ry relative to zero. 
RIP-relative addressing allows specific ModR/M modes to address memory relative to the 64-bit RIP using a signed 
32-bit displacement. This provides an offset range of ±2GB from the RIP. Table 2-7 shows the ModR/M and SIB 
encodings for RIP-relative addressing. Redundant forms of  32-bit displacement-addressing exist in the current 
ModR/M and SIB encodings. There is one ModR/M encodi ng and there are several SIB encodings. RIP-relative 
addressing is encoded using a redundant form. 
In 64-bit mode, the ModR/M Disp32 (32-bit displacement) encoding is re-defined to be RIP+Disp32 rather than 
displacement-only. See Table 2-7.
The ModR/M encoding for RIP-relative addressing does not depend on using a prefix. Specifically, the r/m bit field

The ModR/M encoding for RIP-relative addressing does not depend on using a prefix. Specifically, the r/m bit field 
encoding of 101B (used to select RIP- relative addressing) is not affected by the REX prefix. For example, selecting 
R13 (REX.B = 1, r/m = 101B) with mod = 00B still results in  RIP-relative addressing. The 4-bit r/m field of REX.B 
combined with ModR/M is not fully decoded. In order to address R13 with no displacement, software must encode 
R13 + 0 using a 1-byte displacement of zero. 
RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. The use of the address-size prefix 
does not disable RIP-relative addressing. The effect of th e address-size prefix is to truncate and zero-extend the 
computed effective address to 32 bits. 
2.2.1.7  Default 64-Bit Operand Size
In 64-bit mode, two groups of instructions have a default op erand size of 64 bits (do not need a REX prefix for this 
operand size). These are:
•All instructions, except far branches, that implicitly reference the RSP.
2.2.2 Additional Encodings for Control and Debug Registers
In 64-bit mode, more encodings for control and debug regist ers are available. The REX.R bit is used to modify the 
ModR/M reg field when that field encodes a control or debug register (see Table 2-4). These encodings enable the processor to address CR8-CR15 and DR8- DR15. An addition al control register (CR8) is defined in 64-bit mode. CR8 
becomes the Task Priority Register (TPR). 
In the first implementation of IA-32e mode, CR9-CR15 an d DR8-DR15 are not implemented. Any attempt to access 
unimplemented registers results in an invalid-opcode exception (#UD).Table 2-7.  RIP-Relative Addressing
ModR/M and SIB Sub-field Encodings Compatibility Mode 
Operation64-bit Mode 
OperationAdditional Implications in 64-bit mode
ModR/M Byte mod = 00 Disp32 RIP + Disp32 In 64 -bit mode, if one wants to use a Disp32 
without specifying a base register, one can use a SIB byte encoding (indicated by ModR/M.r/m=100) 
as described in the next row.r/m = 101 (none)
SIB Byte base = 101 (none) If mod = 00, Disp32 Same as legacy None
index = 100 (none)scale = 0, 1, 2, 4Vol. 2A 2-13INSTRUCTION FORMAT
2.3 INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX)
Intel AVX instructions are encoded using an encoding schem e that combines prefix bytes, opcode extension field, 
operand encoding fields, and vector length encoding capa bility into a new prefix, refe rred to as VEX. In the VEX 
encoding scheme, the VEX prefix may be two or three byte s long, depending on the instruction semantics. Despite 
the two-byte or three-byte length of the VEX prefix, th e VEX encoding format provides a more compact represen-
tation/packing of the components of encoding an inst ruction in Intel 64 architectu re. The VEX encoding scheme 
also allows more headroom for future growth of Intel 64 architecture.
2.3.1 Instruction Format
Instruction encoding using VEX pref ix provides several advantages:
•Instruction syntax support for three operands and up-to four operands when necessary. For example, the third 
source register used by VBLENDVPD is enco ded using bits 7:4 of the immediate byte.
•Encoding support for vector length of 128 bits (using  XMM registers) and 256 bits (using YMM registers).
•Encoding support for instruction syntax of non-destructive source operands.
•Elimination of escape opcode byte (0 FH), SIMD prefix byte (66H, F2H, F3 H) via a compact bit field represen-
tation within the VEX prefix.
•Elimination of the need to use REX prefix to encode th e extended half of general-purpose register sets (R8-
R15) for direct register access, memory addressing, or accessing XMM8-XMM15 (including YMM8-YMM15).
•Flexible and more compact bit fields are provided in the VEX prefix to retain the fu ll functionality provided by 
REX prefix. REX.W, REX.X, RE X.B functionalities are provided in the th ree-byte VEX prefix only because only a 
subset of SIMD instructions need them. 
•Extensibility for future instruction extensions without significant instru ction length increase.
Figure 2-8 shows the Intel 64 instruction encoding format  with VEX prefix support. Legacy instruction without a 
VEX prefix is fully supported and unchan ged. The use of VEX prefix in an Intel 64 instruction is optional, but a VEX 
prefix is required for Intel 64 instructions that operate on YMM registers or support th ree and four operand syntax. 
VEX prefix is not a constant-valued, “single-purpose” byte like 0FH, 66H, F2H, F3H in legacy SSE instructions. VEX 
prefix provides substantially richer capability than the REX prefix. 
Figure 2-8.  Instruction Encoding Format with VEX Prefix
2.3.2 VEX and the LOCK prefix
Any VEX-encoded instruction with a LOCK prefix preceding VEX will #UD.
2.3.3 VEX and the 66H, F2H, and F3H prefixes
Any VEX-encoded instruction with a 66H, F2H,  or F3H prefix preceding VEX will #UD.
2.3.4 VEX and the REX prefix
Any VEX-encoded instruction with a RE X prefix proceeding VEX will #UD. ModR/M1
[Prefixes] [VEX] OPCODE [SIB] [DISP] [IMM]2,3 1 0,1 0,1,2,4 0,1 # Bytes2-14 Vol. 2AINSTRUCTION FORMAT
2.3.5 The VEX Prefix 
The VEX prefix is encoded in either the two-byte form (the first byte must be C5H) or in the three-byte form (the 
first byte must be C4H). The two-byte VEX is used ma inly for 128-bit, scalar, and the most common 256-bit AVX 
instructions; while the three-byte VEX provides a compac t replacement of REX and 3-byte opcode instructions 
(including AVX and FMA instructions). Beyond the first byte of the VEX prefix, it consists of a number of bit fields 
providing specific capability, th ey are shown in Figure 2-9. 
The bit fields of the VEX prefix can be summarized by its functional purposes:
•Non-destructive source register encoding (applicable to three and four operand syntax): This is the first source 
operand in the instruction syntax. It is represented by the notation, VEX.vvvv. This field is encoded using 1’s 
complement form (inverted form), i.e., XMM0/YMM0/R 0 is encoded as 1111B, XMM15/YMM15/R15 is encoded 
as 0000B.
•Vector length encoding: This 1-bit field represented by th e notation VEX.L. L= 0 means vector length is 128 bits 
wide, L=1 means 256 bit vector. The value of this field is  written as VEX.128 or VEX.256 in this document to 
distinguish encoded values of other VEX bit fields. 
•REX prefix functionality: Full REX prefix functionality is  provided in the three-byte form of VEX prefix. However 
the VEX bit fields providing REX functionality are enco ded using 1’s complement form, i.e., XMM0/YMM0/R0 is 
encoded as 1111B, XMM15/YMM15/R15 is encoded as 0000B. 
— Two-byte form of the VEX prefix only provides the eq uivalent functionality of REX.R, using 1’s complement 
encoding. This is represented as VEX.R.
— Three-byte form of the VEX prefix provides REX.R,  REX.X, REX.B functionality using 1’s complement 
encoding and three dedicated bit fields represented as VEX.R, VEX.X, VEX.B.
— Three-byte form of the VEX prefix provides the functional ity of REX.W only to specif ic instructions that need 
to override default 32-bit operand size for a general purpose register to 64-bit size in 64-bit mode. For 
those applicable instructions, VEX.W field provides the same functionality as REX.W. VEX.W field can 
provide completely different functionality for other instructions.
Consequently, the use of REX prefix wi th VEX encoded instructions is not al lowed. However, the intent of the
REX prefix for expanding register set is reserved fo r future instruction set extensions using VEX prefix
encoding format.
•Compaction of SIMD prefix: Legacy SSE instructions e ffectively use SIMD prefixes (66H, F2H, F3H) as an 
opcode extension field. VEX prefix encoding allows the functional capability of such legacy SSE instructions 
(operating on XMM registers, bits 255:128 of correspo nding YMM unmodified) to be encoded using the VEX.pp 
field without the presence of any SIMD prefix. The VE X-encoded 128-bit instruction will zero-out bits 255:128 
of the destination register. VEX-encoded instruction may have 128 bit vector length or 256 bits length.
•Compaction of two-byte and three-byte opcode: More re cently introduced legacy SSE instructions employ two 
and three-byte opcode. The one or two leading bytes ar e: 0FH, and 0FH 3AH/0FH 38H. The one-byte escape 
(0FH) and two-byte escape (0FH 3AH, 0FH 38H) can also  be interpreted as an opcode extension field. The 
VEX.mmmmm field provides compaction to allow many legacy instruction to be encoded without the constant byte sequence, 0FH, 0FH 3AH, 0FH 38H. These VEX-encode d instruction may have 128 bit vector length or 256 
bits length.
The VEX prefix is required to be the last prefix and imme diately precedes the opcode bytes. It must follow any other 
prefixes. If VEX prefix is present a REX prefix is not supported. 
The 3-byte VEX leaves room for futu re expansion with 3 reserved bits. REX and the 66h/F2h/F3h prefixes are 
reclaimed for future use.
VEX prefix has a two-byte form and a th ree byte form. If an instruction synt ax can be encoded using the two-byte

VEX prefix has a two-byte form and a th ree byte form. If an instruction synt ax can be encoded using the two-byte 
form, it can also be encoded using the three byte form of VEX. The latter increases the le ngth of the instruction by 
one byte. This may be helpful in so me situations for code alignment. 
The VEX prefix supports 256-bit versio ns of floating-point SSE, SSE2, SSE3 , and SSE4 instructions. Note, certain 
new instruction functionality can only  be encoded with the VEX prefix.
The VEX prefix will #UD on any instruction containing MMX register sources or destinations. Vol. 2A 2-15INSTRUCTION FORMAT
Figure 2-9.  VEX bit fields
The following subsections describe the various fields in two or three-byte VEX prefix.
2.3.5.1  VEX Byte 0, bits[7:0] 
VEX Byte 0, bits [7:0] must contain the value 11000101b (C5h) or 11000100b (C4h). The 3-byte VEX uses the C4h 
first byte, while the 2-byte VEX uses the C5h first byte.
2.3.5.2  VEX Byte 1, bit [7] - ‘R’
VEX Byte 1, bit [7] contains a bit analogous to a bit inve rted REX.R. In protected and compatibility modes the bit 
must be set to ‘1’ otherwise the instruction is LES or LDS.11000100 167 0
 vvvv10 32
L  7
R: REX.R in 1’s complement (inverted) form
00000: Reserved for future use (will #UD)
00001: implied 0F leading opcode byte
00010: implied 0F 38 leading opcode bytes
00011: implied 0F 3A leading opcode bytes
00100-11111: Reserved for future use (will #UD)Byte 0 Byte 2
(Bit Position)
vvvv: a register specifier (in 1’s complement form) or 1111 if unused.670
R X BByte 1
pp: opcode extension providing equivalent  functionality of a SIMD prefixW: opcode specific (use like REX.W, or used for opcodem-mmmm5
m-mmmm: W
L: Vector Length0: Same as REX.R=1 (64-bit mode only)1: Same as REX.R=0 (must be 1 in 32-bit mode)4
pp 3-byte VEX
11000101 1670
vvvv10 32
L 7
R pp 2-byte VEX
B: REX.B in 1’s complement (inverted) form
0: Same as REX.B=1 (64-bit mode only)1: Same as REX.B=0 (Ignored in 32-bit mode).
 extension, or ignored, depending on the opcode byte)
0: scalar or 128-bit vector
1: 256-bit vector
00: None
01: 66
10: F3
11: F20: Same as REX.X=1 (64-bit mode only)1: Same as REX.X=0 (must be 1 in 32-bit mode)X: REX.X in 1’s complement (inverted) form2-16 Vol. 2AINSTRUCTION FORMAT
This bit is present in both 2- and 3-byte VEX prefixes.
The usage of WRXB bits for legacy instructions is explaine d in detail section 2.2.1.2 of Intel 64 and IA-32 Architec-
tures Software developer’s manual, Volume 2A.
This bit is stored in bit inverted format.
2.3.5.3  3-byte VEX byte 1, bit[6] - ‘X’ 
Bit[6] of the 3-byte VEX byte 1 encodes a bit analogous to a bit inverted REX.X.  It is an extension of the SIB Index 
field in 64-bit modes. In 32-bit modes, this bit must be set to ‘1’ otherwise the instruction is LES or LDS.
This bit is available only in the 3-byte VEX prefix.
2.3.5.4  3-byte VEX byte 1, bit[5] - ‘B’ 
Bit[5] of the 3-byte VEX byte 1 encodes a bit analogous to a bit inverted REX.B. In 64-bit modes, it is an extension 
of the ModR/M r/m field, or the SIB base field. In 32-bit modes, this bit is ignored.
2.3.5.5  3-byte VEX byte 2, bit[7] - ‘W’ 
Bit[7] of the 3-byte VEX byte 2 is represented by the nota tion VEX.W. It can provide following functions, depending 
on the specific opcode. 
• For AVX instructions that have equivalent legacy SSE instructions (typically these SSE instructions have a 
general-purpose register operand with its operand size  attribute promotable by REX.W), if REX.W promotes 
the operand size attribute of the general-purpose regist er operand in legacy SSE instruction, VEX.W has same 
meaning in the corresponding AVX equi valent form. In 32-bit modes for these instructions, VEX.W is silently 
ignored.
• For AVX instructions that have equivalent legacy SSE instructions (typically these SSE instructions have oper-
ands with their operand size attribute fixed and not prom otable by REX.W), if REX.W is don’t care in legacy 
SSE instruction, VEX.W is ignored in the correspon ding AVX equivalent form irrespective of mode.
• For new AVX instructions where VEX.W has no defined function (typically these meant the combination of the 
opcode byte and VEX.mmmmm did not have any equivalent  SSE functions), VEX.W is reserved as zero and 
setting to other than zero will cause instruction to #UD.
2.3.5.6  2-byte VEX Byte 1, bits[6:3] and 3-byte VE X Byte 2, bits [6:3]- ‘v vvv’ the Source or Dest 
Register Specifier
In 32-bit mode the VEX first byte C4 and C5 alias onto th e LES and LDS instructions. To maintain compatibility with 
existing programs the VEX 2nd byte, bits [7:6] must be 11 b. To achieve this, the VEX payload bits are selected to 
place only inverted, 64-bit valid fields (extended register selectors) in these upper bits. 
The 2-byte VEX Byte 1, bits [6:3] and the 3-byte VEX, Byte  2, bits [6:3] encode a field (shorthand VEX.vvvv) that 
for instructions with 2 or more source registers and an XMM or YMM or memory destination encodes the first source register specifier stored in inverted (1’s complement) form. 
VEX.vvvv is not used by the instructions with one source (e xcept certain shifts, see below) or on instructions with 
no XMM or YMM or memory destination. If an instructio n does not use VEX.vvvv then it should be set to 1111b 
otherwise instruction will #UD.
In 64-bit mode all 4 bits may be used. See Table 2-8 for the encoding of the XMM or YMM registers. In 32-bit and 
16-bit modes bit 6 must be 1 (if bit 6 is not 1, the 2-byte  VEX version will generate LD S instruction and the 3-byte 
VEX version will ignore this bit).Vol. 2A 2-17INSTRUCTION FORMAT
Table 2-8.  VEX.vvvv to register name mapping
The VEX.vvvv field is encoded in bit inverted format for accessing a register operand.
2.3.6 Instruction Operand Encoding and VEX.vvvv, ModR/M
VEX-encoded instructions support three-operand and four-operand instruction syntax. Some VEX-encoded 
instructions have syntax with less than three operands , e.g., VEX-encoded pack shift instructions support one 
source operand and one destination operand). 
The roles of VEX.vvvv, reg field of ModR/M byte (ModR/ M.reg), r/m field of ModR/M byte (ModR/M.r/m) with 
respect to encoding destination and source operands  vary with different type of instruction syntax.
The role of VEX.vvvv can be su mmarized to three situations:
•VEX.vvvv encodes the first source register operand, specif ied in inverted (1’s complement) form and is valid for 
instructions with 2 or more source operands. 
•VEX.vvvv encodes the destination register  operand, specified in 1’s complement form for certain vector shifts. 
The instructions where VEX.vvvv is used as a destinatio n are listed in Table 2-9. The notation in the “Opcode” 
column in Table 2-9 is described in detail in section 3.1.1.
•VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. 
Table 2-9.  Instructions with a VEX.vvvv destination VEX.vvvv Dest RegisterGeneral-Purpose Register 
(If Applicable)1
NOTES:
1. See Section 2.6, “VEX Encoding Support for GPR Instructions” for additional details.Valid in Legacy/Compatibility 
32-bit modes?2
2. Only the first eight General-Purpose Registers are accessible/encodable in 16/32b modes.1111B XMM0/YMM0 RAX/EAX Valid
1110B XMM1/YMM1 RCX/ECX Valid
1101B XMM2/YMM2 RDX/EDX Valid
1100B XMM3/YMM3 RBX/EBX Valid1011B XMM4/YMM4 RSP/ESP Valid
1010B XMM5/YMM5 RBP/EBP Valid
1001B XMM6/YMM6 RSI/ESI Valid1000B XMM7/YMM7 RDI/EDI Valid
0111B XMM8/YMM8 R8/R8D Invalid
0110B XMM9/YMM9 R9/R9D Invalid0101B XMM10/YMM10 R10/R10D Invalid
0100B XMM11/YMM11 R11/R11D Invalid
0011B XMM12/YMM12 R12/R12D Invalid
0010B XMM13/YMM13 R13/R13D Invalid
0001B XMM14/YMM14 R14/R14D Invalid0000B XMM15/YMM15 R15/R15D Invalid
Opcode Instruction mnemonic
VEX.128.66.0F 73 /7 ib VPSLLDQ xmm1, xmm2, imm8
VEX.128.66.0F 73 /3 ib VPSRLDQ xmm1, xmm2, imm8
VEX.128.66.0F 71 /2 ib VPSRLW xmm1, xmm2, imm8VEX.128.66.0F 72 /2 ib VPSRLD xmm1, xmm2, imm8
VEX.128.66.0F 73 /2 ib VPSRLQ xmm1, xmm2, imm8
VEX.128.66.0F 71 /4 ib VPSRAW xmm1, xmm2, imm82-18 Vol. 2AINSTRUCTION FORMAT
The role of ModR/M.r/m field can be summarized to two situations:
•ModR/M.r/m encodes the instruction oper and that references a memory address.
•For some instructions that do not support memory ad dressing semantics, ModR/M.r/m encodes either the 
destination register operand or a source register operand.
The role of ModR/M.reg field can be summarized to two situations:
•ModR/M.reg encodes either the destination register operand or a source register operand.
•For some instructions, ModR/M.reg is treated as an op code extension and not used to encode any instruction 
operand.
For instruction syntax that support four operands, VEX. vvvv, ModR/M.r/m, ModR/M.reg encodes three of the four 
operands. The role of bits 7:4 of the imme diate byte serves the following situation:
•Imm8[7:4] encodes the third source register operand.
2.3.6.1  3-byte VEX byte  1, bits[4:0] - “m-mmmm”

operand.
2.3.6.1  3-byte VEX byte  1, bits[4:0] - “m-mmmm” 
Bits[4:0] of the 3-byte VEX by te 1 encode an implied leading opcode byte (0F, 0F 38, or 0F 3A). Several bits are 
reserved for future use and will #UD unless 0. 
Table 2-10.   VEX. m-mmmm interpretation
VEX.m-mmmm is only available on the 3-byte VEX. The 2-byte VEX implies a leading 0Fh opcode byte.
2.3.6.2  2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L”
The vector length field, VEX.L, is encoded in bit[2] of eith er the second byte of 2-byte VEX, or the third byte of 3-
byte VEX. If “VEX.L = 1”, it indicate s 256-bit vector operation. “VEX.L = 0” indicates scalar and 128-bit vector 
The instruction VZEROUPPER is a special case that is enco ded with VEX.L = 0, although its operation zero’s bits 
255:128 of all YMM registers accessible in the current operating mode.
See the following table.VEX.128.66.0F 72 /4 ib VPSRAD xmm1, xmm2, imm8
VEX.128.66.0F 71 /6 ib VPSLLW xmm1, xmm2, imm8
VEX.128.66.0F 72 /6 ib VPSLLD xmm1, xmm2, imm8
VEX.128.66.0F 73 /6 ib VPSLLQ xmm1, xmm2, imm8
VEX.m-mmmm Implied Leading Opcode Bytes
00000B Reserved00001B 0F
00010B 0F 38
00011B 0F 3A
00100-11111B Reserved
(2-byte VEX) 0FOpcode Instruction mnemonicVol. 2A 2-19INSTRUCTION FORMAT
Table 2-11.  VEX.L interpretation
2.3.6.3  2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”
Up to one implied prefix is encoded by bits[1:0] of either the 2-byte VEX byte 1 or the 3- byte VEX byte 2. The prefix 
behaves as if it was encoded prior to VE X, but after all other encoded prefixes.
See the following table.
Table 2-12.  VEX.pp interpretation
2.3.7 The Opcode Byte
One (and only one) opcode byte follows the 2 or 3 byte VE X. Legal opcodes are specified in Appendix B,  in color. 
Any instruction that uses illegal opcode will #UD.
2.3.8 The ModR/M, SIB, and Displacement Bytes
The encodings are unchanged but the interpretation  of reg_field or rm_field differs (see above).
2.3.9 The Third Source Operand (Immediate Byte)
VEX-encoded instructions can support instruction with  a four operand syntax. VBLENDVPD, VBLENDVPS, and 
PBLENDVB use imm8[7:4] to encode  one of the source registers. 
2.3.10 Intel® AVX Instructions and the Upper 128-bits of YMM registers
If an instruction with a destination XMM register is enco ded with a VEX prefix, the processor zeroes the upper bits 
(above bit 128) of the equivalent YMM register. Legacy  SSE instructions without VEX preserve the upper bits.
2.3.10.1  Vector Length Transition and Programming Considerations 
An instruction encoded with a VEX.128 prefix that loads a YMM register operand operates as follows:
•Data is loaded into bits 127:0 of the register
•Bits above bit 127 in the register are cleared.
Thus, such an instruction clears bits 255:128 of a destination YMM register on processors with a maximum vector-
register width of 256 bits. In the event that future proc essors extend the vector registers to greater widths, an 
instruction encoded with a VEX.128 or VE X.256 prefix will also clear any bits beyond bit 255. (This is in contrast 
with legacy SSE instructions, which have no VEX prefix; th ese modify only bits 127:0 of any destination register 
operand.)
Programmers should bear in mind that instructions en coded with VEX.128 and VEX.256 prefixes will clear any 
future extensions to the vector register s. A calling function that uses such exte nsions should save their state before 
calling legacy functions. This is not possible for involuntar y calls (e.g., into an interrupt-service routine). It is 
recommended that software handling involuntary calls a ccommodate this by not executing instructions encoded VEX.L Vector Length
0 128-bit (or 32/64-bit scalar)
1 256-bit
pp Implies this prefix after other prefixes but before VEX
00B None
01B 66
10B F3
11B F22-20 Vol. 2AINSTRUCTION FORMAT
with VEX.128 and VEX.256 prefixes. In the event that it is not possible or desirable to restrict these instructions, 
then software must take special care to avoid actions that would, on future processors, zero the upper bits of vector 
Processors that support further vector-register extensions  (defining bits beyond bit 255) will also extend the 
XSAVE and XRSTOR instructions to save and restore thes e extensions. To ensure forward compatibility, software 
that handles involuntary calls and that uses instructions  encoded with VEX.128 and VEX.256 prefixes should first 
save and then restore the vector registers (with any ex tensions) using the XSAVE and XRSTOR instructions with 
save/restore masks that set bits that correspond to all vect or-register extensions. Ideally, software should rely on 
a mechanism that is cognizant of which bits to set. (E.g.,  an OS mechanism that sets the save/restore mask bits 
for all vector-register extensions that are enabled in XCR0.)  Saving and restoring state with instructions other than 
XSAVE and XRSTOR will, on future processors with wider ve ctor registers, corrupt the extended state of the vector 
registers - even if doing so functions correctly on processors supporting 256-bit vector registers. (The same is true 
if XSAVE and XRSTOR are used with a save/restore mask that does not set bits corresponding to all supported 
extensions to the vector registers.)
2.3.11 Intel® AVX Instruction Length
The Intel AVX instructions described in this document (inc luding VEX and ignoring other prefixes) do not exceed 11 
bytes in length, but may increase in the future. The maxi mum length of an Intel 64 and IA-32 instruction remains 
15 bytes.
2.3.12 Vector SIB (VSIB) Memory Addressing 
In Intel® Advanced Vector Extensions 2 (Intel® AVX2), an SIB byte that follows the ModR/M byte can support VSIB 
memory addressing to an array of line ar addresses. VSIB addressing is only  supported in a subset of Intel AVX2 
instructions. VSIB memory addressing requires 32-bit or 64 -bit effective address. In 32-bit mode, VSIB addressing 
is not supported when address size attribute is overri dden to 16 bits. In 16-bit protected mode, VSIB memory 
addressing is permitted if address size attribute is overri dden to 32 bits. Additionally, VSIB memory addressing is 
supported only with VEX prefix.
In VSIB memory addressing, the SIB byte consists of:
•The scale field (bit 7:6) specifies the scale factor.
•The index field (bits 5:3) specifies the register number of  the vector index register, each element in the vector 
register specifies an index.
•The base field (bits 2:0) specifies the register number of the base register.
Table 2-13 shows the 32-bit VSIB addressing form. It is or ganized to give 256 possible values of the SIB byte (in 
hexadecimal). General purpose registers used as a base are indicated across the top of the table, along with corre-
sponding values for the SIB byte’s base field. The register  names also include R8D-R15D applicable only in 64-bit 
mode (when address size override prefix is used, but th e value of VEX.B is not shown in Table 2-13). In 32-bit 
mode, R8D-R15D does not apply.
Table rows in the body of the table in dicate the vector index register used as the index field and each supported 
scaling factor shown separately. Vector registers used in the index field can be XMM or YMM registers. The left-most column includes vector registers VR8-VR15 (i.e.,  XMM8/YMM8-XMM15/YMM15), which are only available in 
64-bit mode and does not apply if encoding in 32-bit mode. Vol. 2A 2-21INSTRUCTION FORMAT
2.3.12.1  64-bit Mode VSIB Memory Addressing 
In 64-bit mode VSIB memory addressing uses the VEX.B fi eld and the base field of the SIB byte to encode one of 
the 16 general-purpose register as the base register. The VEX.X field and the index field of the SIB byte encode one 
of the 16 vector registers as the vector index register. 
In 64-bit mode the top row of Table 2-13 base register sh ould be interpreted as the full 64-bit of each register. 
2.4 INTEL® ADVANCED MATRIX  EXTENSIONS (INTEL® AMX)
Intel® AMX instructions follow the general documentation convention established in previous sections. Additionally, 
Intel® Advanced Matrix Extensions use notation conventions as described below. 
In the instruction encoding boxes, sibmem  is used to denote an encoding where a ModR/M byte and SIB byte are 
used to indicate a memory operation where the base and displacement are used to point to memory, and the index Table 2-13.  32-Bit VSIB Addr essing Forms of the SIB Byte
r32
(In binary) Base =EAX/
R8D0000ECX/
R9D1001EDX/
R10D2010EBX/
R11D3011ESP/
R12D4100EBP/
R13D
1
5101
NOTES:
1. If ModR/M.mod = 00b, the base address is zero, then effectiv e address is computed as [scaled vector index] + disp32. Otherwi se the
base address is computed as [EBP/R13]+ disp, the displacement is either 8 bit or 32 bit depending on the value of ModR/M.mod:
MOD Effective Address00b [Scaled Vector Register] + Disp32
01b [Scaled Vector Register] + Disp8 + [EBP/R13]
10b [Scaled Vector Register] + Disp32 + [EBP/R13]ESI/
R14D6110EDI/
R15D7111
VR0/VR8

r32
R13D
1
5101
NOTES:
R15D7111
VR0/VR8
VR1/VR9VR2/VR10VR3/VR11VR4/VR12VR5/VR13VR6/VR14VR7/VR15*1 00 000
VR0/VR8
VR1/VR9VR2/VR10
VR3/VR11
VR4/VR12VR5/VR13VR6/VR14VR7/VR15*2 01 000
001010
011
10010111011140
4850
58
6068707841
4951
59
6169717942
4A52
5A
626A727A43
4B53
5B
636B737B44
4C54
5C
646C747C45
4D55
5D
656D757D46
4E56
5E
666E767E47
4F57
5F
676F777F
VR0/VR8
VR1/VR9VR2/VR10VR3/VR11VR4/VR12VR5/VR13VR6/VR14VR7/VR15*4 10 000
899189A1A9B1B982
VR0/VR8
VR1/VR9VR2/VR10VR3/VR11VR4/VR12VR5/VR13VR6/VR14VR7/VR15*8 11 000
CA
D2DAE2EAF2FAC3
CFD7DFE7EFF7FF2-22 Vol. 2AINSTRUCTION FORMAT
register (if present) is used to denote a stride between memory rows. The index register is scaled by the sib.scale 
field as usual. The base register is added to the displacement, if present.
In the instruction encoding, the ModR/M byte is represen ted several ways depending on the role it plays. The 
ModR/M byte has 3 fields: 2-bit ModR/M.mod field, a 3-bit ModR/M.reg field and a 3-bit ModR/M.r/m field. When all 
bits of the ModR/M byte have fixed values for an instruct ion, the 2-hex nibble value of that byte is presented after 
the opcode in the encoding boxes on the instruction descrip tion pages. When only some fields of the ModR/M byte 
must contain fixed values, those values are specified as follows:
•If only the ModR/M.mod must be 0b11, and ModR/M.reg  and ModR/M.r/m fields are unrestricted, this is 
denoted as 11:rrr:bbb . The rrr correspond to the 3-bits of the ModR/M.reg field and the bbb correspond to the 
3-bits of the ModR/M.r/m field.
•If the ModR/M.mod field is constrained to be a value ot her than 0b11, i.e., it must be one of 0b00, 0b01, or 
0b10, then the notation !(11) is used.
•If the ModR/M.reg field had a specific required valu e, e.g., 0b101, that would be denoted as mm:101:bbb. 
NOTE
Historically this document only sp ecified the ModR/M.reg field restrictions with the notation /0 ... /7 
and did not specify restrictions on the ModR/M.mod  and ModR/M.r/m fields in the encoding boxes.
2.5 INTEL® AVX AND INTEL® SSE IN STRUCTION EXCEPTION CLASSIFICATION
To look up the exceptions of legacy 128-bit SIMD instru ction, 128-bit VEX-encoded instructions, and 256-bit VEX-
encoded instruction, Table 2-14 summarizes the exception be havior into separate classes, with detailed exception 
conditions defined in sub-sections 2.5.1 throug h 2.6.1. For example, ADDPS contains the entry:
“See Exceptions Type 2”In this entry, “Type2” can be looked up in Table 2-14. 
The instruction’s corresponding CPUID feature flag can be identified in the fourth column of the Instruction 
summary table. 
Note: #UD on CPUID feature flags=0 is not guaranteed in a virtualized environment if the hardware supports the 
feature flag.
NOTE
Instructions that operate only with MMX, X87, or general-purpose registers are not covered by the exception classes defined in this section. For instructions that operate on MMX registers, see 
Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” 
in the Intel
® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.Vol. 2A 2-23INSTRUCTION FORMAT
Table 2-14.  Exception Class Description 
See Table 2-15 for lists of instructions in each exception class.Exception Class Instruction set Mem argFloating-Point 
Exceptions (#XM)
Type 1AVX,
Legacy SSE16/32 byte explicitly 
alignedNone
Type 2AVX,
Legacy SSE16/32 byte not explicitly 
alignedYes
Type 3AVX,
Legacy SSE< 16 byte Yes
Type 4AVX,
alignedNo
Type 5AVX, 
Legacy SSE< 16 byte No
Type 6 AVX (no Legacy SSE) Va ries (At present, none do)
Type 7AVX, 
Legacy SSENone None
Type 8 AVX None None
Type 11F16C 8 or 16 byte, Not explicitly 
aligned, no AC#Yes
Type 12AVX2 Gathers Not explicitly aligned, no 
AC#No2-24 Vol. 2AINSTRUCTION FORMAT
Table 2-15.  Instructions in each Exception Class
(*) - Additional exception restrictions are present - see the Instruction description for detailsException Class Instruction
Type 1 (V)MOVAPD, (V)MOVAPS, (V)MOVDQA, (V)MOVNT DQ, (V)MOVNTDQA, (V )MOVNTPD, (V)MOVNTPS
Type 2(V)ADDPD, (V)ADDPS, (V)ADDSUBPD, (V)ADDSUBPS, (V)CMPPD , (V)CMPPS, (V)CVTDQ2PS, (V)CVTPD2DQ, 
(V)CVTPD2PS, (V)CVTPS2D Q, (V)CVTTPD2DQ, (V)CV TTPS2DQ, (V)DIVPD, (V)DIVPS, (V)DPPD*, (V)DPPS*, 
VFMADD132PD, VFMADD213PD, VFMADD231PD, VFMADD132PS, VFMADD21 3PS, VFMADD231PS, 
VFMADDSUB132PD, VFMADDSUB213P D, VFMADDSUB231PD, VFMADD SUB132PS, VFMADDSUB213PS, 
VFMADDSUB231PS, VFMSUBADD132PD, VFMSUBA DD213PD, VFMSUBADD231P D, VFMSUBADD132PS, 
VFMSUBADD213PS, VFMSUBADD231PS, VFMSUB132PD,  VFMSUB213PD, VFMSUB231PD, VFMSUB132PS, 
VFMSUB213PS, VFMSUB231PS, VFNMADD132PD, VF NMADD213PD, VFNMADD231PD, VFNMADD132PS, 
VFNMADD213PS, VFNMADD231PS, VFNMSUB132PD, VFNMSUB213PD, VFNMSUB231PD, VFNMSUB132PS, 
VFNMSUB213PS, VFNMSUB231PS, (V)H ADDPD, (V)HADDPS, (V)HSUBPD, (V)HSUBPS, (V)M AXPD, (V)MAXPS, 
(V)MINPD, (V)MINPS, (V)MULPD, (V)M ULPS, (V)ROUNDPD, (V)R OUNDPS, (V)SQR TPD, (V)SQRTPS, (V)SUBPD, 
(V)SUBPS
Type 3(V)ADDSD, (V)ADDSS, (V)CMPSD, (V)CMP SS, (V)COMISD, (V)COMIS S, (V)CVTPS2PD, (V)CVT SD2SI, (V)CVTSD2SS, 
(V)CVTSI2SD, (V)CVTSI2SS,  (V)CVTSS2SD, (V)CVTSS2S I, (V)CVTTSD2SI, (V)CVTTS S2SI, (V)DIVSD, (V)DIVSS, 
VFMADD132SD, VFMADD213SD, VFMADD231SD, VFMA DD132SS, VFMADD213S S, VFMADD231SS, 
VFMSUB132SD, VFMSUB213SD, VFMSUB231SD, VFMSUB132SS, VFMSUB213SS, VFMSUB231SS, VFNMADD132SD, VFNMADD213SD, VFNMADD231SD, VFNMADD132SS, VFNMADD213SS, VFNMADD231SS, 
VFNMSUB132SD, VFNMSUB213SD, VFNMSUB231SD, VFNMSUB132SS, VFNMSUB213SS, VFNMSUB231SS, 
(V)MAXSD, (V)MAXSS, (V)MINSD, (V )MINSS, (V)MULSD, (V)M ULSS, (V)ROUNDSD, (V)ROUNDSS, (V)SQRTSD, 
(V)SQRTSS, (V)SUB SD, (V)SUBSS, (V)U COMISD, (V)UCOMISS
Type 4(V)AESDEC, (V)AESDECLAST,  (V)AESENC, (V)AESENCL AST, (V)AESIMC, (V)AES KEYGENASSIST, (V)ANDPD, 
(V)ANDPS, (V)ANDNPD, (V )ANDNPS, (V)BLENDPD, (V )BLENDPS, VBLENDVPD, VB LENDVPS, (V)LDDQU***, 
(V)MASKMOVDQU, (V)PTEST, VTESTPS,  VTESTPD, (V)MOVDQU*, (V)MOVSH DUP, (V)MOVSLDUP, (V)MOVUPD*, 
(V)MOVUPS*, (V)MPSADBW, (V )ORPD, (V)ORPS, (V)PABSB , (V)PABSW, (V)PABSD, (V)P ACKSSWB, (V)PACKSSDW, 
(V)PACKUSWB, (V)PACKUSDW, (V)P ADDB, (V)PADDW, (V)PADDD, (V)P ADDQ, (V)PADDSB, (V)PADDSW, 
(V)PADDUSB, (V)PAD DUSW, (V)PALIGNR, (V)PAND, (V)PANDN , (V)PAVGB, (V)PAV GW, (V)PBLENDVB, 
(V)PBLENDW, (V)PCMP(E/I)STRI/M***,  (V)PCMPEQB, (V)PCMPEQW, (V)PCM PEQD, (V)PCMPEQQ, (V)PCMPGTB, 
(V)PCMPGTW, (V)PCMPGTD, (V)P CMPGTQ, (V)PCLMULQDQ, (V)PHA DDW, (V)PHADDD, (V)PHADDSW, 
(V)PHMINPOSUW, (V )PHSUBD, (V)PHSUBW, (V )PHSUBSW, (V)PMADDWD, (V )PMADDUBSW, (V)PMAXSB, 
(V)PMAXSW, (V)PMAXSD, (V)PMAXU B, (V)PMAXUW, (V)PMAXUD, (V)PMINSB, (V)PMINSW, (V)PMINSD, 
(V)PMINUB, (V)PMINUW, (V)PMINU D, (V)PMULHUW, (V)PMU LHRSW, (V)PMU LHW, (V)PMULLW, (V)PMULLD, 
(V)PMULUDQ, (V)PMULDQ, (V)POR, (V)P SADBW, (V)PSHUFB, (V)PSHUFD, (V )PSHUFHW, (V)PSHUFLW, (V)PSIGNB, 
(V)PSIGNW, (V)PSIGND, (V )PSLLW, (V)PSLLD, (V)PSLLQ, (V)PSRAW, (V )PSRAD, (V)PSRLW, (V)PSRLD, (V)PSRLQ, 
(V)PSUBB, (V)PSUBW, (V)PSUBD, (V)PSUBQ, (V)PSUBSB, (V)PSUBS W, (V)PSUBUSB , (V)PSUBUSW, 
(V)PUNPCKHBW, (V)PUNPCKHWD, (V )PUNPCKHDQ, (V)PUNPCKHQDQ, (V)PUNPCKLBW, (V)PUNPCKLWD, 
(V)PUNPCKLDQ, (V)PUNPCKLQDQ, (V) PXOR, (V)RCPPS, (V)RSQ RTPS, (V)SHUFPD, (V)S HUFPS, (V)UNPCKHPD, 
(V)UNPCKHPS, (V)UNPCKLPD, (V)UNP CKLPS, (V)XORPD, (V)X ORPS, VPBLENDD, VPERMD, VPERMPS, VPERMPD, 
VPERMQ, VPSLLVD, VPSLLVQ, VPSRAVD, VPSRLVD, VPSRLVQ, VPERMILPD, VPERMILPS, VPERM2F128
Type 5(V)CVTDQ2PD, (V)EXT RACTPS, (V)INSERTPS, (V)M OVD, (V)MOVQ, (V )MOVDDUP, (V)MOVLP D, (V)MOVLPS, 
(V)MOVHPD, (V)MOVHPS,  (V)MOVSD, (V)MOVSS, (V)PEX TRB, (V)PEXTRD, (V)PEXTRW,  (V)PEXTRQ, (V)PINSRB, 
(V)PINSRD, (V)PINSRW, (V)PINSRQ, PMOVSXBW, (V )RCPSS, (V)RSQRTSS, (V)P MOVSX/ZX, VLDMXCSR*, 
VSTMXCSR
Type 6VEXTRACTF128/VEXTRACTFxxxx, VBROADCASTSS, VBROADCASTSD, VBROADCASTF128, VINSERTF128, 
VMASKMOVPS**, VMASKMOVPD**, VPMASKMOVD, VPMASKMOVQ, VBROADCASTI128, VPBROADCASTB, 
VPBROADCASTD, VPBROADCASTW, VPBROADCASTQ, VEXTRACTI128, VINSERTI128, VPERM2I128
Type 7(V)MOVLHPS, (V)MOVHLPS, (V )MOVMSKPD, (V)MOVMSKPS, (V)PMOVMSKB, (V)PSLLDQ,  (V)PSRLDQ, (V)PSLLW, 
(V)PSLLD, (V)PSLLQ, (V)PSRAW, (V)P SRAD, (V)PSRLW, (V)PSRLD, (V)PSRLQ
Type 8 VZEROALL, VZEROUPPER
Type 11 VCVTPH2PS, VCVTPS2PH
Type 12VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHE RQPD, VPGATHERDD, VPGATHERDQ, VPGATHERQD, 
VPGATHERQQVol. 2A 2-25INSTRUCTION FORMAT
(**) - Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits of a ll 1s, i.e., no
alignment checks are performed.
(***) - PCMPESTRI, PC MPESTRM, PCMPISTRI, PCMPISTRM, and L DDQU instructions do not cause #G P if the memory operand is not
aligned to 16-Byte boundary.

VSTMXCSR
Table 2-15 classifies exception behaviors for AVX instructions. Within each class of exception conditions that are 
listed in Table 2-18 through Table 2-27, certain subsets of AVX instructions may be subject to #UD exception depending on the encoded value of the VEX.L field. Tabl e 2-17 provides supplemental information of AVX instruc-
tions that may be subject to #UD exception if encoded with incorrect values in the VEX.W or VEX.L field.
Table 2-16.  #UD Exception and VEX.W=1 Encoding
Exception Class #UD If VEX.W = 1 in all modes#UD If VEX.W = 1 in 
non-64-bit modes
Type 1
Type 2
Type 3
Type 4VBLENDVPD, VBLENDVPS, VPBLENDVB, VTESTPD, VTESTPS, VPBLENDD, VPERMD, 
VPERMPS, VPERM2I128, VPSRAVD, VPERMILPD, VPERMILPS, VPERM2F128
Type 5
Type 6VEXTRACTF128, VBROADCASTSS, VB ROADCASTSD, VBROADCASTF128, 
VINSERTF128, VMASKMOVPS, VMASKMOVPD, VBROADCASTI128, 
VPBROADCASTB/W/D, VEXTRACTI128, VINSERTI128
Type 7Type 8
Type 122-26 Vol. 2AINSTRUCTION FORMAT
Table 2-17.  #UD Exception and VEX.L Field Encoding
Exception 
Class#UD If VEX.L = 0#UD If (VEX.L = 1 && AV X2 not present && AVX 
present)#UD If (VEX.L = 1 && AVX2 
present)
Type 1 VMOVNTDQA
Type 2VDPPD VDPPD
Type 3
Type 4VMASKMOVDQU, VMPSADBW, VPABSB/W/D, 
VPACKSSWB/DW, VPACKUSWB/DW, VPADDB/W/D, 
VPADDQ, VPADDSB/W, VPADDUSB/W, VPALIGNR, VPAND, VPANDN, VPAVGB/W, VPBLENDVB, VPBLENDW, 
VPCMP(E/I)STRI/M, VPCMPEQB /W/D/Q, VPCMPGTB/W/D/Q, 
VPHADDW/D, VPHADDSW, VPHMINPOSUW, VPHSUBD/W, VPHSUBSW, VPMADDWD, VPMADDUBSW, VPMAXSB/W/D, 
VPMAXUB/W/D, VPMINSB/W/D, VPMINUB/W/D, 
VPMULHUW, VPMULHRSW, VPMULHW/LW, VPMULLD, 
VPMULUDQ, VPMULDQ, VPOR, VPSADBW, VPSHUFB/D, 
VPSHUFHW/LW, VPSIGNB/W/D, VPSLLW/D/Q, VPSRAW/D, VPSRLW/D/Q, VPSUBB/W/D/Q, VPSUBSB/W, 
VPUNPCKHBW/WD/DQ, VPUNPCKHQDQ, 
VPUNPCKLBW/WD/DQ, VP UNPCKLQDQ, VPXORVPCMP(E/I)STRI/M, 
PHMINPOSUW
Type 5VEXTRACTPS, VINSERTPS, VMOVD, VMOVQ, VMOVLPD, 
VMOVLPS, VMOVHPD, VMOVHPS, VPEXTRB, VPEXTRD, 
VPEXTRW, VPEXTRQ, VPINSRB, VPINSRD, VPINSRW, VPINSRQ, VPMOVSX/ZX, VLDMXCSR, VSTMXCSRSame as column 3
Type 6VEXTRACTF128, 
VPERM2F128, VBROADCASTSD, 
VBROADCASTF128, 
VINSERTF128, 
Type 7VMOVLHPS, VMOVHLPS, VPMOVMSKB, VPSLLDQ, 
VPSRLDQ, VPSLLW, VPSLLD, VPSLLQ, VPSRAW, VPSRAD, 
VPSRLW, VPSRLD, VPSRLQVMOVLHPS, VMOVHLPS
Type 8
Type 11
Type 12Vol. 2A 2-27INSTRUCTION FORMAT
2.5.1 Exceptions Type 1 (Aligned Memory Reference) 
Table 2-18.  Type 1 Class Exception Conditions
Exception
Real
Virtual-8086
Protected and 
Compatibility
64-bit Cause of Exception
Invalid Opcode, 
#UDXX V E X  p r e f i x .
XXVEX prefix:
If XCR0[2:1] ? ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
XXX XLegacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X X X X If preceded by a LOCK prefix (F0H).
X X If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X X X X If any corresponding CPUID feature flag is ‘0’.
Device Not Avail-
able, #NMXXX X I f  C R 0 . T S [ b i t  3 ] = 1 .
Stack, #SS(0)X For an illegal address in the SS segment.
X If a memory address referencing the SS segment is in a non-canonical form.
General Protec-
tion, #GP(0)XXVEX.256: Memory operand is not 32-byte aligned.
VEX.128: Memory operand is not 16-byte aligned.
X X X X Legacy SSE: Memory oper and is not 16-byte aligned.
XFor an illegal memory operand effective address in the CS, DS, ES, FS or GS seg-
ments.
X If the memory address is in a non-canonical form.
X X If any part of the operand lies outside the effective address space from 0 to FFFFH.
Page Fault 
#PF(fault-code)X X X For a page fault.2-28 Vol. 2AINSTRUCTION FORMAT
2.5.2 Exceptions Type 2 (>=16 By te Memory Reference, Unaligned) 
Table 2-19.  Type 2 Class Exception Conditions
Exception
Real
Virtual 8086
X X X X If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. 
XX XXLegacy SSE instruction:
able, #NMX X X X If CR0.TS[bit 3]=1.
Stack, #SS(0)X For an illegal addre ss in the SS segment.
tion, #GP(0)X X X X Legacy SSE: Memory operand is not 16-byte aligned.
X For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
Page Fault 
#PF(fault-code)X X X For a page fault.
SIMD Floating-
point Exception, #XMX X X X If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.Vol. 2A 2-29INSTRUCTION FORMAT
2.5.3 Exceptions Type 3 (<16 Byte Memory Argument) 
Table 2-20.  Type 3 Class Exception Conditions
Exception
Real
Invalid Opcode, #UDXX V E X  p r e f i x .
Device Not Available, 
#NMX X X X If CR0.TS[bit 3]=1.
General Protection, 
#GP(0)XFor an illegal memory operand effective address in the CS, DS, ES, FS or GS seg-
ments.
XXIf any part of the operand lies outside the effective address space from 0 to 
FFFFH.
Page Fault 
Alignment Check 
#AC(0)XX XFor 2, 4, or 8 byte memory access if  alignment checking is enabled and an 
unaligned memory access is made while the current privilege level is 3.
SIMD Floating-point 
Exception, #XMX X X X If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.2-30 Vol. 2AINSTRUCTION FORMAT
2.5.4 Exceptions Type 4 (>=16 Byte Mem Arg, No Alignment, No Floating-point Exceptions)
Table 2-21.  Type 4 Class Exception Conditions
Exception
Real
#NMXXX X I f  C R 0 . T S [ b i t  3 ] = 1 .
#GP(0)XXX X Legacy SSE: Memory operan d is not 16-byte aligned.1
NOTES:
1. LDDQU, MOVUPD, MOVUPS, PCMPESTRI, PC MPESTRM, PCMPISTRI, and PCMPISTRM instructions do not cause #GP if the memory
operand is not aligned to 16-Byte boundary.XFor an illegal memory operand effective address in the CS, DS, ES, FS or GS seg-
ments.
FFFFH.
Page Fault 
#PF(fault-code)X X X For a page fault.Vol. 2A 2-31INSTRUCTION FORMAT
2.5.5 Exceptions Type 5 (<16 Byte  Mem Arg and No FP Exceptions)
Table 2-22.  Type 5 Class Exception Conditions
Exception
Real
ments.
FFFFH.
Page Fault 
#AC(0)XX XFor 2, 4, or 8 byte memory access if alignment checking is enabled and an 
unaligned memory access is made while the current privilege level is 3.2-32 Vol. 2AINSTRUCTION FORMAT
2.5.6 Exceptions Type 6 (VEX-Encoded In structions without Legacy SSE Analogues)

ments.
FFFFH.
Page Fault 
Note: At present, the AVX instructions in this ca tegory do not generate floating-point exceptions.
Table 2-23.  Type 6 Class Exception Conditions
Exception
Real
XXIf XCR0[2:1] ? ‘11b’.
X X If preceded by a LOCK prefix (F0H).
X X If any corresponding CPUID feature flag is ‘0’.
#NMX X If CR0.TS[bit 3]=1.
ments.
Page Fault 
#PF(fault-code)X X For a page fault.
#AC(0)XXFor 2, 4, or 8 byte memory access if  alignment checking is enabled and an 
unaligned memory access is made while the current privilege level is 3.Vol. 2A 2-33INSTRUCTION FORMAT
2.5.7 Exceptions Type 7 (No FP Exceptions, No Memory Arg)
Table 2-24.  Type 7 Class Exception Conditions
2.5.8 Exceptions Type 8 (AVX and No Memory Argument)
Table 2-25.  Type 8 Class Exception ConditionsException
Real
#NMXX I f  C R 0 . T S [ b i t  3 ] = 1 .
Exception
Real
Invalid Opcode, #UD X X Always in  Real or Virtual-8086 mode.
XX If XCR0[2:1] ? ‘11b’.
If CPUID.01H.ECX.AVX[bit 28]=0.
If VEX.vvvv ? 1111B.
X X X X If proceeded by a LOCK prefix (F0H).
#NMX X If CR0.TS[bit 3]=1.2-34 Vol. 2AINSTRUCTION FORMAT
2.5.9 Exceptions Type 11 (VEX-only, Mem Arg, No AC, Floating-point Exceptions)
Table 2-26.  Type 11 Class Exception Conditions
Exception
Real
Invalid Opcode, #UD X X VEX prefix.
XX V E X  p r e f i x :
Stack, #SS(0) X For an illegal address in the SS segment.
#GP(0)X For an illegal memo ry operand effective address in the CS, DS, ES, FS or GS seg-
ments.
X X If any part of the operand lies outside the effective address space from 0 to 
FFFFH.
Page Fault #PF 
(fault-code)X X X For a page fault.
SIMD Floating-Point 
Exception, #XMX X X X If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.Vol. 2A 2-35INSTRUCTION FORMAT
2.5.10 Exceptions Type 12 (VEX-only, VSIB Mem Arg, No AC, No Floating-point Exceptions)
2.6 VEX ENCODING SUPPORT  FOR GPR INSTRUCTIONS 
VEX prefix may be used to encode instructions that operate on neither YMM nor XMM registers. VEX-encoded 
general-purpose-register instructio ns have the following properties:
•Instruction syntax support for three encodable operands.
•Encoding support for instruction syntax of non-destru ctive source operand, destination operand encoded via 
VEX.vvvv, and destructive three-operand syntax.
•Elimination of escape opcode byte (0FH), two-byte esca pe via a compact bit field representation within the VEX 
prefix.
R15) for direct register access or memory addressing.
REX prefix. REX.W, REX.X, REX.B functionalities are provided in the three-byte VEX prefix only. 
•VEX-encoded GPR instructions are encoded with VEX.L=0.Table 2-27.  Type 12 Cl ass Exception Conditions
Exception
Real
X X X NA If address size attribute is 16 bit.XX X XI f  M o d R / M . m o d  =  ‘ 1 1 b ’ .
XX X X If ModR/M.rm 
? ‘100b’.
X X X X If any vector register is  used more than once between the destination register, 
mask register and the index re gister in VSIB addressing.
#NMXX X XI f  C R 0 . T S [ b i t  3 ] = 1 .
#GP(0)X For an illegal memory oper and effective address in the CS, DS, ES, FS or GS seg-
ments.
FFFFH.
Page Fault #PF (fault-
code)X X X For a page fault.2-36 Vol. 2AINSTRUCTION FORMAT
Any VEX-encoded GPR instruction with a 66H, F2 H, or F3H prefix preceding VEX will #UD.
Any VEX-encoded GPR instruction with a REX prefix proceeding VEX will #UD. 
VEX-encoded GPR instructions are not supported in real and virtual 8086 modes.
2.6.1 Exceptions Type 13 (VEX-Encoded GPR Instructions)
The exception conditions applicable to  VEX-encoded GPR instruction differs fr om those of legacy GPR instructions. 
Table 2-28 lists VEX-encoded GPR instructions. The exception conditions for VEX-encoded GRP instructions are 
found in Table 2-29 for those instructions which have a de fault operand size of 32 bits and 16-bit operand size is 
not encodable.
(*) - Additional exception restrictions are present - see the Instruction description for details.
2.7 INTEL® AVX-512 ENCODING
The majority of the Intel AVX-512 family of instructions (operating on 512/256/128-bit vector register operands) 
are encoded using a new prefix (called EVEX). Opmask instructions (operating on opmask register operands) are 
encoded using the VEX prefix. The EVEX  prefix has some parts resembling the instruction encoding scheme using 
the VEX prefix, and many other capabilities not available with the VEX prefix. Table 2-28.  VEX-Encoded GPR Instructions
Exception Class Instruction
Type 13 ANDN, BEXTR, BLSI, BLSMSK, BLSR, BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX
Table 2-29.  Type 13 Class Exception Conditions
Exception
Real
Invalid Opcode, #UD X X X X If BMI1/B MI2 CPUID feature flag is ‘0’.
X X If a VEX prefix is present.X X X X If VEX.L = 1.
Stack, #SS(0) X X X For an illegal address in the SS segment.
#GP(0)X For an illegal memory operand effective address in the CS, DS, ES, FS or GS seg-
ments. 
If the DS, ES, FS, or GS re gister is used to access memory and it contains a null 
segment selector.
FFFFH.
Page Fault #PF(fault-
code)X X X For a page fault.
#AC(0)X X X For 2, 4, or 8 byte memory access if alignment checking is enabled and an 
unaligned memory access is made while the current privilege level is 3.Vol. 2A 2-37INSTRUCTION FORMAT
The significant feature differences betw een EVEX and VEX are summarized below.
•EVEX is a 4-Byte prefix (the first by te must be 62H); VEX is either a 2-Byte  (C5H is the first byte) or 3-Byte 
(C4H is the first byte) prefix.
•EVEX prefix can encode 32 vector regi sters (XMM/YMM/ZMM) in 64-bit mode.
•EVEX prefix can encode an opmask register for conditional processing or selection control in EVEX-encoded 
vector instructions. Opmask instructions, whose source/destination operands are opmask registers and treat 
the content of an opmask register as a sing le value, are encoded using the VEX prefix.
•EVEX memory addressing with disp8 form uses a comp ressed disp8 encoding scheme to improve the encoding 
density of the instruction byte stream.
•EVEX prefix can encode functionality that are specific to instruction classes (e.g., packed instruction with

•EVEX prefix can encode functionality that are specific to instruction classes (e.g., packed instruction with 
“load+op” semantic can support embedded broadcast func tionality, floating-point instruction with rounding 
semantic can support static rounding functionality, fl oating-point instruction with non-rounding arithmetic 
semantic can support “suppress all exceptions” functionality).
2.7.1 Instruction Format and EVEX
The placement of the EVEX prefix in an IA instruction is represented in Figure 2-10. Note that the values contained 
within brackets are optional.
The EVEX prefix is a 4-byte prefix, wi th the first two bytes derived from unus ed encoding form of the 32-bit-mode-
only BOUND instruction. The layout of the EVEX prefix is shown in Figure 2-11. The first byte must be 62H, followed 
by three payload bytes, denoted as P0, P1, and P2 indi vidually or collectively as P[23:0] (see Figure 2-11).Figure 2-10.  Intel® AVX-512 Instruction Format and the EVEX Prefix
Figure 2-11.  Bit Field Layout of the EVEX Prefix1
NOTES:
1. See Table 2-30 for additional details on bit fields.[Immediate] [Prefixes] [Disp16,32] [SIB] ModR/M Opcode EVEX# of bytes: 4 1 112 ,  4 1
[Disp8*N]1
EVEX 62H P0 P1 P2
P0765432 0 1
RXBR ’ 0 m m m
P1765432 0 1
W vvvv1 p p
P2765432 0 1
zL ’ LbV ’ a a aP[7:0]
P[15:8]
P[23:16]2-38 Vol. 2AINSTRUCTION FORMAT
The bit fields in P[23:0] are divided into the following fu nctional groups (Table 2-30 provides a tabular summary):
•Reserved bits: P[3] must be 0, otherwise #UD.
•Fixed-value bit: P[10] must be 1, otherwise #UD.
•Compressed legacy prefix/escape bytes: P[1:0] is identical to the lowest 2 bits of VEX.mmmmm; P[9:8] is 
identical to VEX.pp.
•EVEX.mmm: P[2:0] provides access to up to eight decodi ng maps. Currently, only the following decoding maps 
are supported: 1, 2, 3, 5, and 6. Map ids 1, 2, and 3 are denoted by 0F, 0F38, and 0F3A, respectively, in the 
instruction encoding descriptions.
•Operand specifier modifier bits for vector register, gene ral purpose register, memory addressing: P[7:5] allows 
access to the next set of 8 registers beyond the low 8 re gisters when combined with ModR/M register specifiers. 
•Operand specifier modifier bit for vector register: P[4] (or EVEX.R’) allows access to the high 16 vector register 
set when combined with P[7] and ModR/M.reg specifier;  P[6] can also provide access to a high 16 vector 
register when SIB or VSIB addressing are not needed.
•Non-destructive source /vector index operand specifier: P[19] and P[14:11] encode the second source vector 
register operand in a non-destructive source syntax, ve ctor index register operand can access an upper 16 
vector register using P[19].
•Op-mask register specifiers: P[18:16] encodes op-mask register set k0-k7 in instructions operating on vector registers.
•EVEX.W: P[15] is similar to VEX.W which serves either as opcode extension bit or operand size promotion to 
64-bit in 64-bit mode.
•Vector destination merging/zeroing: P[23] encodes the destination result behavior which either zeroes the 
masked elements or leave masked element unchanged.
•Broadcast/Static-rounding/SAE context bit: P[20] encodes multiple functionality, which differs across different classes of instructions and can affect the meaning of the remaining field (EVEX.L’L). The functionality for the 
following instruction classes are:Table 2-30.  EVEX Prefix Bit Field Functional Grouping
Notation Bit field Group Position Comment
EVEX.mmm Access to up to eigh t decoding maps P[2:0] Currently, only the following decoding maps are supported: 1, 
2, 3, 5, and 6.
-- Reserved P[3] Must be 0.EVEX.R’ High-16 register specifier modifier P[4] Combine with EVEX.R and ModR/M.reg. This bit is stored in 
inverted format.
EVEX.RXB Next-8 register specifier modifier P[7:5] Combine with ModR/M.reg, ModR/M.rm (base, index/vidx). This 
field is encoded in bit inverted format.
EVEX.X High-16 register specifier modifier P[6] Combine with EVEX.B and ModR/M.rm, when SIB/VSIB absent.
EVEX.pp Compressed legacy prefix P[9:8] Identical to VEX.pp.
-- Fixed Value P[10] Must be 1.EVEX.vvvv VVVV register specifier P[14:11] Same as VEX.vvv v. This field is encoded in bit inverted format.
EVEX.W Operand size promotion/Opcode 
extensionP[15]
EVEX.aaa Embedded opmask register specifier P[18:16]
EVEX.V’ High-16 VVVV/VIDX register specifier P[19] Combine with EVEX.vvvv or when VSIB present. This bit is 
stored in inverted format.
EVEX.b Broadcast/RC/SAE Context P[20]
EVEX.L’L Vector length/RC P[22:21]EVEX.z Zeroing/Merging P[23]Vol. 2A 2-39INSTRUCTION FORMAT
— Broadcasting a single element across the destination vector register: this applies to the instruction class 
with Load+Op semantic where one of the source operand is from memory. 
— Redirect L’L field (P[22:21]) as static rounding cont rol for floating-point instructions with rounding 
semantic. Static rounding control overrides MXCSR.RC field and implies “Suppress all exceptions” (SAE).
— Enable SAE for floating -point instructions with arithmetic semantic that is not rounding.
— For instruction classes outside of the afore-mentio ned three classes, setting EVEX.b will cause #UD.
•Vector length/rounding control specifier: P[22:21] can serve one of three options.
— Vector length information for packed vector instructions.— Ignored for instructions operating on vector register content as a single data element.
— Rounding control for floating-point instructions that have a rounding semantic and whose source and 
destination operands are all vector registers.
2.7.2 Register Specifier Encoding and EVEX
EVEX-encoded instruction can access 8 opmask registers, 16 general-purpose registers and 32 vector registers in 
64-bit mode (8 general-purpose registers and 8 vector re gisters in non-64-bit modes). EVEX-encoding can support 
instruction syntax that access up to 4 instruction oper ands. Normal memory addressing modes and VSIB memory 
addressing are supported with EVEX pref ix encoding. The mapping of register operands used by various instruction 
syntax and memory addressing in 64-bit mode are shown in  Table 2-31. Opmask register encoding is described in 
Section 2.7.3.
The mapping of register operands used by various instru ction syntax and memory addressing in 32-bit modes are 
shown in Table 2-32.Table 2-31.  32-Register Support in 64-bit Mode Using EVEX with Embedded REX Bits
41
NOTES:
1. Not applicable for accessing general purpose registers.3 [2:0] Reg. Type Common Usages 
REG EVEX.R’ REX.R modrm.reg GPR, Vector Destination or Source
VVVV EVEX.V’ EVEX.vvvv GPR, Vector 2ndSource or Destination
RM EVEX.X EVEX.B modrm.r/m GPR, Vector 1st Source or Destination
BASE 0 EVEX.B modrm.r/m GPR memory addressing
INDEX 0 EVEX.X sib.index GPR memory addressing
VIDX EVEX.V’ EVEX.X sib.index Vector VSIB memory addressing
Table 2-32.  EVEX Encoding Regist er Specifiers in 32-bit Mode 
[2:0] Reg. Type Common Usages 
REG modrm.reg GPR, Vector Destination or Source
VVVV EVEX.vvv GPR, Vector 2nd Source or Destination
RM modrm.r/m GPR, Vector 1st Source or Destination
BASE modrm.r/m GPR Memory Addressing
INDEX sib.index GPR Memory Addressing
VIDX sib.index Vector VSIB Memory Addressing2-40 Vol. 2AINSTRUCTION FORMAT
2.7.3 Opmask Register Encoding
There are eight opmask registers, k0-k7. Opmask  register encoding falls into two categories:
•Opmask registers that are the source or destination oper ands of an instruction treating the content of opmask 
register as a scalar value, are encoded using the VEX pref ix scheme. It can support up to three operands using 
standard modR/M byte’s reg field and rm field and VEX. vvvv. Such a scalar opmask instruction does not support 
conditional update of the destination operand.
•An opmask register providing conditional processing and/ or conditional update of the destination register of a 
vector instruction is encoded using EVEX.aaa field (see Section 2.7.4).
•An opmask register serving as the destination or source operand of a vector instruction is encoded using 
standard modR/M byte’s reg field and rm fields.
2.7.4 Masking Support in EVEX
EVEX can encode an opmask register to conditionally co ntrol per-element computational operation and updating of 
result of an instruction to the destination operand. Th e predicate operand is known as the opmask register. The 
EVEX.aaa field, P[18:16] of the EVEX pr efix, is used to encode one out of a set of eight 64-bit architectural regis-
ters. Note that from this set of 8 architectural registers,  only k1 through k7 can be addressed as predicate oper-
ands. k0 can be used as a regular source or destin ation but cannot be encoded as a predicate operand. 
AVX-512 instructions support two type s of masking with EVEX.z bit (P[23 ]) controlling the type of masking: 
•Merging-masking, which is the default type of masking for EVEX-encoded vector instructions, preserves the old 
value of each element of the destination where the corresp onding mask bit has a 0. It corresponds to the case 
of EVEX.z = 0.
•Zeroing-masking, is enabled by having the EVEX.z bit set to 1. In this case , an element of the destination is set

•Zeroing-masking, is enabled by having the EVEX.z bit set to 1. In this case , an element of the destination is set 
to 0 when the corresponding mask bit has a 0 value. 
AVX-512 Foundation instructions can be  divided into the following groups:
•Instructions which support “zeroing-masking”.
— Also allow merging-masking.
•Instructions which require aaa = 000.— Do not allow any form of masking.
•Instructions which allow merging-mask ing but do not allow zeroing-masking.
— Require EVEX.z to be set to 0.
— This group is mostly composed of instructions that write to memory.
•Instructions which require aaa <> 000 do  not allow EVEX.z to be set to 1.
— Allow merging-masking and do not allow zeroing-masking, e.g., gather instructions.Table 2-33.  Opmask Register Specifier Encoding
[2:0] Register Access Common Usages 
REG modrm.reg k0-k7 Source
VVVV VEX.vvvv k0-k7 2nd Source 
RM modrm.r/m k0-7 1st Source 
{k1} EVEX.aaa k01-k7
NOTES:
1. Instructions that overwrite the conditional mask in  opmask do not permit using k0 as the embedded mask.OpmaskVol. 2A 2-41INSTRUCTION FORMAT
2.7.5 Compressed Displacement (disp8*N) Support in EVEX
For memory addressing using disp8 form, EVEX-encoded  instructions always use a compressed displacement 
scheme by multiplying disp8 in conjunct ion with a scaling factor N that is de termined based on the vector length, 
the value of EVEX.b bit (embedded broadc ast) and the input element size of the instruction. In general, the factor 
N corresponds to the number of bytes characterizing the in ternal memory operation of the input operand (e.g., 64 
when the accessing a full 512-bit memory vector). The sca le factor N is listed in Table 2-34 and Table 2-35 below, 
where EVEX encoded instructions are classified using the tupletype  attribute. The scale factor N of each tupletype 
is listed based on the vector length (VL) and other factors affecting it.
Table 2-34 covers EVEX-encoded instructions which has a load semantic in conjunction with additional computa-
tional or data element movement operation, operating either on the full vector or half vector (due to conversion of 
numerical precision from a wider format to narrower format ). EVEX.b is supported for such instructions for data 
element sizes which are either dword or qword (see Section 2.7.11). 
EVEX-encoded instruction that are pure load/store, and “Load+op” instruction semantic that operate on data 
element size less then dword do not support broadcasting using EVEX.b. These are listed in Table 2-35. Table 2-35 
also includes many broadcast instructions which perform broadcast using a subset of data elements without using 
EVEX.b. These instructions and a few data element size co nversion instruction are covered in Table 2-35. Instruc-
tion classified in Table 2-35 do not use EVEX.b and EVEX.b must be 0, otherwise #UD will occur.
The tupletype will be referenced in the instruction operand en coding table in the reference page of each instruction, 
providing the cross reference for the scaling fact or N to encoding memory addressing operand. 
Note that the disp8*N rules still apply when using 16b addressing.
Table 2-34.  Compressed Displacement (D ISP8*N) Affected by Embedded Broadcast
TupleType EVEX.b InputSize EVEX.W Broadcas t N (VL=128) N (VL=256) N (VL= 512) Comment
Full0 32bit 0 none 16 32 64
Load+Op (Full Vector 
Dword/Qword)1 32bit 0 {1tox} 4 4 4
0 64bit 1 none 16 32 64
1 64bit 1 {1tox} 8 8 8
Half0 32bit 0 none 8 16 32
Load+Op (Half Vector)
1 32bit 0 {1tox} 4 4 4
Table 2-35.  EVEX DISP8*N for Instructio ns Not Affected by Embedded Broadcast
TupleType InputSize EVEX.W N (VL= 128) N (VL= 256) N (VL= 512) Comment
Full Mem N/A N/A 16 32 64 Load/store or subDword full vector
Tuple1 Scalar8bit N/A 1 1 1
1Tuple16bit N/A 2 2 2
32bit 0 4 4 4
64bit 1 8 8 8
Tuple1 Fixed32bit N/A 4 4 4 1 Tuple, memsize not affected by 
EVEX.W 64bit N/A 8 8 8
Tuple232bit 0 8 8 8
Broadcast (2 elements) 
64bit 1 NA 16 16
Tuple432bit 0 NA 16 16
Broadcast (4 elements) 
64bit 1 NA NA 32
Tuple8 32bit 0 NA NA 32 Broadcast (8 elements) 
Half Mem N/A N/A 8 16 32  SubQword Conversion
Quarter Mem N/A N/A 4 8 16 SubDword Conversion2-42 Vol. 2AINSTRUCTION FORMAT
2.7.6 EVEX Encoding of Broa dcast/Rounding/SAE Support
EVEX.b can provide three types of encoding co ntext, depending on the instruction classes:
•Embedded broadcasting of one data element from a so urce memory operand to the destination for vector 
instructions with “load+op” semantic.
•Static rounding control overriding MXCSR.RC for fl oating-point instructions with rounding semantic.
•“Suppress All exceptions” (SAE) overriding MXCSR mask co ntrol for floating-point arithmetic instructions that 
do not have rounding semantic.
2.7.7 Embedded Broadcast Support in EVEX
EVEX encodes an embedded broadcast functionality that is  supported on many vector instructions with 32-bit 
(double word or single precision floating-point) and 64-bit data elements, and when the source operand is from memory. EVEX.b (P[20]) bit is used to enable broadcast on load-op instructions. When enabled, only one element 
is loaded from memory and broadcasted to all other elements instead of loading the full memory size. 
The following instruction classes do not support embedded broadcasting:
•Instructions with only one scalar result is written to the vector destination.
•Instructions with explicit broadcast functionality provided by its opcode.
•Instruction semantic is a pure load or a pure store operation.
2.7.8 Static Rounding Support in EVEX
Static rounding control embedded in the EVEX encoding system applies only  to register-to-register flavor of 
floating-point instructions with rounding semantic at two distinct vector lengths: (i) scalar, (ii) 512-bit. In both cases, the field EVEX.L’L expresses rounding mode control ov erriding MXCSR.RC if EVEX.b is set. When EVEX.b is 
set, “suppress all exceptions” is implied. The proce ssor behaves as if all MXCSR masking controls are set.
2.7.9 SAE Support in EVEX
The EVEX encoding system allows arithmetic floating-poi nt instructions without rounding semantic to be encoded 
with the SAE attribute. This capability applies to scalar an d 512-bit vector lengths, register-to-register only, by 
setting EVEX.b. When EVEX.b is set, “suppress all exceptions” is implied. The processor behaves as if all MXCSR 
masking controls are set.
2.7.10 Vector Length Orthogonality 
The architecture of EVEX encoding scheme can support SIMD instructions operating at multiple vector lengths. Many AVX-512 Foundation instructions operate at 512-bit ve ctor length. The vector length of EVEX encoded vector 
instructions are generally determined using the L’L field in  EVEX prefix, except for 512-bit floating-point, reg-reg 
instructions with rounding semantic. The table below shows the vector length corresponding to various values of the L’L bits. When EVEX is used to encode scalar instructions, L’L is generally ignored.
When EVEX.b bit is set for a register-register instructions  with floating-point rounding semantic, the same two bits 
P2[6:5] specifies rounding mode for the instruction, with  implied SAE behavior. The mapping of different instruc-
tion classes relative to the embedded broadcast/rounding /SAE control and the EVEX.L’L fields are summarized in 
Table 2-36. Eighth Mem N/A N/A 2 4 8 SubWord Conversion
Mem128 N/A N/A 16 16 16 Shift count from memory
MOVDDUP N/A N/A 8 32 64 VMOVDDUPTable 2-35.  EVEX DISP8*N for Instructions Not Affected by Embedded Broadcast (Contd.)
TupleType InputSize EVEX.W N (VL= 128) N (VL= 256) N (VL= 512) CommentVol. 2A 2-43INSTRUCTION FORMAT
2.7.11 #UD Equations for EVEX
Instructions encoded using EVEX can face three types of UD conditions: state dependent, opcode independent and 
opcode dependent.
2.7.11.1  State Dependent #UD
In general, attempts of execute an instruction, which required OS support for incremental extended state compo-
nent, will #UD if required state components were not en abled by OS. Table 2-37 lists instruction categories with 
respect to required processor state components. Attempts  to execute a given category of instructions while 
enabled states were less than the required bit vector in XCR0 shown in Table 2-37 will cause #UD.
2.7.11.2  Opcode Independent #UD
A number of bit fields in EVEX encoded instruction mu st obey mode-specific but opcode-independent patterns 
listed in Table 2-38.Table 2-36.  EVEX Embedded Broadcast/Rounding/SAE and Vector Length on Vector Instructions
Position P2[4] P2[6:5] P2[6:5]
Broadcast/Rounding/SAE Context EVEX.b EVEX.L’L EVEX.RC
Reg-reg, FP Instructions w/ rounding semantic or SAE Enable static rounding 
control (SAE implied)Vector length Implied 
(512 bit or scalar)00b: SAE + RNE
01b: SAE + RD10b: SAE + RU
11b: SAE + RZ
Load+op Instructions w/ memory so urce Broadcast Control 00b: 128-bit
01b: 256-bit
10b: 512-bit11b: Reserved (#UD)NA
Other Instructions (
Explicit Load/Store/Broadcast/Gather/Scatter)Must be 0 (otherwise 
#UD)NA
Table 2-37.  OS XSAVE Enabling Requirements of Instruction Categories
Instruction Categories Vector Register State Access Required XCR0 Bit Vector [7:0]

#UD)NA
Legacy SIMD prefix encoded Instructions (e.g SSE) XMM xxxxxx11b
VEX-encoded instructions operating on YMM YMM xxxxx111b
EVEX-encoded 128-bit instructions ZMM 111xx111b
EVEX-encoded 256-bit instructions ZMM 111xx111b
EVEX-encoded 512-bit instructions ZMM 111xx111b
VEX-encoded instructions operating on opmask k-reg 111xxx11b
Table 2-38.  Opcode Independent, State Dependent EVEX Bit Fields
Position Notation 64-bit #UD Non-64-bit #UD
P[3] -- if > 0 if > 0
P[10] -- if 0 if 0P[2:0] EVEX.mmm if 000b, 100b, or 111b if 000b, 100b, or 111bP[7 : 6] EVEX.RX None (valid) None (BOUND if EVEX.RX != 11b)2-44 Vol. 2AINSTRUCTION FORMAT
2.7.11.3  Opcode Dependent #UD
This section describes legal values for the rest of the EVEX  bit fields. Table 2-39 lists the #UD conditions of EVEX 
prefix bit fields which encodes or modifies register operands.
Table 2-40 lists the #UD conditions of instruction en coding of opmask register using EVEX.aaa and EVEX.zTable 2-39.  #UD Conditio ns of Operand-Encoding EVEX Prefix Bit Fields 
Notation Position  Operand Enco ding 64-bit #UD Non-64-bit #UD
EVEX.R P[7] ModRM.reg encodes k-reg If EVEX.R = 0 None (BOUND if 
EVEX.RX != 11b)ModRM.reg is opcode extension None (ignored)
ModRM.reg encodes all other registers None (valid)
EVEX.X P[6] ModRM.r/m encodes ZMM/YMM/XMM None (valid)
ModRM.r/m encodes k-reg or GPR None (ignored)ModRM.r/m without SIB/VSIB None (ignored)
ModRM.r/m with SIB/VSIB None (valid)
EVEX.B P[5] ModRM.r/m encodes k-re g None (ignored) None (ignored)
ModRM.r/m encodes other registers None (valid)ModRM.r/m base present None (valid)
ModRM.r/m base not present None (ignored)
EVEX.R’ P[4] ModRM.reg encodes k- reg or GPR If 0 None (ignored)
ModRM.reg is opcode extension None (ignored)
ModRM.reg encodes ZMM/YMM/XMM None (valid)
EVEX.vvvv P[14:11] vvvv encodes ZMM/YMM/XMM None (valid) None (valid)
P[14] ignored
Otherwise If != 1111b If != 1111b
EVEX.V’ P[19] Encodes ZMM/YMM/XMM None (valid) If 0
Otherwise If 0 If 0
Table 2-40.  #UD Conditions of Opmask Related Encoding Field 
Notation Position Operand Encoding 64-bit #UD Non-64-bit #UD
EVEX.aaa P[18:16] Instructions do not use opmask for conditional processing1.
NOTES:
1. E.g., VPBROADCASTMxxx, VPMOVM2x, VPMOVx2M.If aaa != 000b If aaa != 000b
Opmask used as conditional processing mask and updated 
at completion2.
2. E.g., Gather/Scatter family.If aaa = 000b If aaa = 000b;
Opmask used as conditional processing. None (valid3)
3. aaa can take any value. A value of 000 in dicates that there is no mask ing on the instruction; in this case, all elements wil l be pro-
cessed as if there was a mask of ‘all on es’ regardless of the actual value in K0.None (valid1)
EVEX.z P[23] Vector instruction using opmask as source  or destination4.
4. E.g., VFPCLASSPD/PS, VCMPB/D/ Q/W family, VPMOVM2x, VPMOVx2M.If EVEX.z != 0 If EVEX.z != 0
Store instructions or gather/scatter instructions. If EVEX.z != 0 If EVEX.z != 0
Instructions with EVEX.aaa = 000b. If EVEX.z != 0 If EVEX.z != 0
VEX.vvvv Varies K-regs are instruction operan ds not mask control. If vvvv = 0xxxb NoneVol. 2A 2-45INSTRUCTION FORMAT
Table 2-41 lists the #UD conditions of EVEX bit fields that depends on the context of EVEX.b.
2.7.12 Device Not Available
EVEX-encoded instructions follow the same rules when it  comes to generating #NM (Device Not Available) excep-
tion. In particular, it is generated when CR0.TS[bit 3]= 1.
2.7.13 Scalar Instructions
EVEX-encoded scalar SIMD instructions can access up to 32  registers in 64-bit mode. Scalar instructions support 
masking (using the least significant bit of the opma sk register), but broadcasting is not supported. 
2.8 EXCEPTION CLASSIFICATIONS OF EVEX-ENCODED INSTRUCTIONS
The exception behavior of EVEX-encoded instructions can be  classified into the classes shown in the rest of this 
section. The classification of EVEX-encoded instructions  follow a similar framework as those of AVX and AVX2 
instructions using the VEX prefix. Exception types for EVEX-encoded instructions are named in the style of
“E##” or with a suffix “E##XX”. The “##” designation generally follows that of AVX/AVX2 instructions. The 
majority of EVEX encoded instruction with “Load+op” se mantic supports memory fault suppression, which is repre-
sented by E##. The instructions with “Load+op” sema ntic but do not support fault suppression are named 
“E##NF”. A summary table of exception cl asses by class names are shown below.Table 2-41.  #UD Conditions Dependent on EVEX.b Context
Notation Position Operand Encodi ng 64-bit #UD Non-64-bit #UD
EVEX.L’Lb P[22 : 20] Reg-reg, FP instructions with rounding semantic. None (valid1)
NOTES:
1. L’L specifies rounding control, se e Table 2-36, supports {er} syntax.None (valid1)
Other reg-reg, FP instructions that can cause #XM. None (valid2)
2. L’L is ignored.None (valid2)
Other reg-mem instructions in Table 2-34. None (valid3)
3. L’L specifies vector length, see Table 2-36, supports embedded broadcast syntaxNone (valid3)
Other instruction classes4 in Table 2-35.
4. L’L specifies either ve ctor length or ignored.If EVEX.b = 1 If EVEX.b = 1
Table 2-42.  EVEX-Encoded Instruction Exception Class Summary 
Exception Class Instruction set Mem arg (#XM)
Type E1 Vector Moves/Load/Stores Explici tly aligned, w/ fa ult suppression None
Type E1NF Vector Non-temporal Stores Explicitly aligned, no fault suppression None
Type E2 FP Vector Load+op Support fault suppression Yes
Type E2NF FP Vector Load+op No fault suppression Yes
Type E3 FP Scalar/Partial Vector, Load+Op Support fault suppression Yes
Type E3NF FP Scalar/Partial Vector, Load+Op No fault suppression Yes
Type E4 Integer Vector Load+op Support fault suppression No
Type E4NF Integer Vector Load+op No fault suppression No
Type E5 Legacy-like Promotion Varies, Support fault suppression No
Type E5NF Legacy-like Promotion V aries, No fault suppression No2-46 Vol. 2AINSTRUCTION FORMAT
Table 2-43 lists EVEX-encoded instru ction mnemonic by exception classes.Type E6 Post AVX Promotion Var ies, w/ faul t suppression No
Type E6NF Post AVX Promotion Varies, no fault suppression No
Type E7NM Register-to-register op None None
Type E9NF Miscellaneous 128-bit Vector-length Specific, no fault suppression None
Type E10 Non-XF Scalar Vector Length ignored, w/ fault suppression None
Type E10NF Non-XF Scalar Vector Length ignored, no fault suppression None
Type E11 VCVTPH2PS, VCVTPS2PH Half Vector Length, w/ fault suppression YesType E12 Gather and Scatter Family VSIB addressing, w/ fault suppression None
Type E12NP Gather and Scatter Prefetch Family VSIB addressing, w/o page fault None
Table 2-43.  EVEX Instructio ns in Each Exception Class
Type E1 VMOVAPD, VMOVAPS, VMOVDQA32, VMOVDQA64
Type E1NF VMOVNTDQ, VMOVNTDQA, VMOVNTPD, VMOVNTPS
Type E2VADDPD, VADDPH, VADDPS, VCMPPD, VCMPPH, VCMPPS, VCVTDQ2PH, VCVTDQ2PS, VCVTPD2DQ, VCVTPD2PH, 
VCVTPD2PS, VCVTPD2QQ, VCVTPD2UQQ, VCVTPD2UDQ, VCVTPH2DQ, VCVTPH2PD, VCVTPH2QQ, VCVTPH2UDQ, 
VCVTPH2UQQ, VCVTPH2UW, VCVTPH2W, VCVTPS2DQ, VCVTPS2UDQS, VCVTQQ2PD, VCVTQQ2PH, VCVTQQ2PS, VCVTTPD2DQ, VCVTTPD2QQ, VCVTTPD2UDQ, VCVTTPD2 UQQ, VCVTTPH2DQ, VCVTTPH2QQ, VCVTTPH2UDQ, 
VCVTTPH2UQQ, VCVTTPH2UW, VCVTTPH2W, VCVTTPS2DQ, VCVTTPS2UDQ, VCVTUDQ2PH, VCVTUDQ2PS, 
VCVTUQQ2PD, VCVTUQQ2PH, VCVTUQQ2PS, VCVTUW2PH, VCVTW2PH, VDIVPD, VDIVPH, VDIVPS, VEXP2PD, VEXP2PS, VFIXUPIMMPD, VFIXUPIMMPS, VFMADDxxx PD, VFMADDxxxPH, VFMADDxxxPS, VFMADDSUBxxxPD, 
VFMADDSUBxxxPH, VFMADDSUBxxx PS, VFMSUBADDxxxPD, VFMSUB ADDxxxPH, VFMSUBADDxxxPS, 
VFMSUBxxxPD, VFMSUBxxxPH, VFMSUBxxxPS, VF NMADDxxxPD, VFNMADDxxxPH, VFNMADDxxxPS, 
VFNMSUBxxxPD, VFNMSUBxxxPH, VF NMSUBxxxPS, VGETEXPPD, VGETE XPPH, VGETEXPPS, VGETMANTPD, 
VGETMANTPH, VGETMANTPS, VGETMANTSH, VMAXPD, VM AXPH, VMAXPS, VMINPD, VM INPH, VMINPS, VMULPD, 
VMULPH, VMULPS, VRANGEPD, VRANGEPS, VREDUCEPD, VREDUCEPH, VREDUCEPS, VRNDSCALEPD, VRNDSCALEPH, VRNDSCALEPS, VRCP28PD, VRCP28PS, VRSQRT28PD, VRSQRT28PS, VSCALEFPD, VSCALEFPS, 
VSQRTPD, VSQRTPH, VSQRTPS, VSUBPD, 
VSUBPH, VSUBPS
Type E3VADDSD, VADDSH, VADDSS, VCMPSD, VCMPSH, VCMPSS, VCVTPS2QQ, VCVTPS2UQQ, VCVTPS2PD, VCVTSD2SH, 
VCVTSD2SS, VCVTSH2SD, VCVTSH2SS, VCVTSS2SD, VCVTSS2SH, VCVTTPS2QQ, VCVTTPS2UQQ, VDIVSD, VDIVSH, 
VDIVSS, VFMADDxxxSD, VFMADDxxxSH, VFMADDxxxSS , VFMSUBxxxSD, VFMSUBxxxSH, VFMSUBxxxSS, 
VFNMADDxxxSD, VFNMADDxxxSH, VFNMADDxxxSS, VFNMSUBxxxSD, VFNMSUBxxxSH, VFNMSUBxxxSS, 
VFIXUPIMMSD, VFIXUPIMMSS, VG ETEXPSD, VGETEXPSH, VGETEXPS S, VGETMANTSD, VGETMANTSH, 
VGETMANTSS, VMAXSD, VMAXSH, VMAXSS, VMINSD, VMINSH, VMINSS, VMULSD, VMULSH, VMULSS, VRANGESD, VRANGESS, VREDUCESD, VREDUCESH, VREDUCESS, VRNDSCALESD, VRNDSCALESH, VRNDSCALESS, VSCALEFSD, 
VSCALEFSH, VSCALEFS S, VRCP28SD, VRCP28SS, VRSQRT28SD, VRSQRT28SS, VSQRTSD, VSQRTSH, VSQRTSS, 
VSUBSD, VSUBSH, VSUBSS
Type E3NFVCOMISD, VCOMISH, VCOMISS, VCVTSD2SI, VCVTSD2USI, VCVTSH2SI, VCVTSH2USI, VCVTSI2SD, VCVTSI2SH,

Type E3NFVCOMISD, VCOMISH, VCOMISS, VCVTSD2SI, VCVTSD2USI, VCVTSH2SI, VCVTSH2USI, VCVTSI2SD, VCVTSI2SH, 
VCVTSI2SS, VCVTSS2SI, VCVTSS2USI, VCVTTSD2SI, VCVTTSD2USI, VCVTTSH2SI, VCVTTSH2USI, VCVTTSS2SI, VCVTTSS2USI, VCVTUSI2SD, VCVTUSI2SH, VCVTUSI2SS, VUCOMISD, VUCOMISH, VUCOMISSTable 2-42.  EVEX-Encoded Instruction Exception Class Summary  (Contd.)
Exception Class Instruction set Mem arg (#XM)Vol. 2A 2-47INSTRUCTION FORMAT
Type E4VANDPD, VANDPS, VANDNPD, VANDNPS, VBLENDMPD, VBLENDMPS, VFCMADDCPH, VFCMULCPH, VFMADDCPH, 
VFMULCPH, VFPCLASSPD, VF PCLASSPH, VFPCLASSPS, VORPD, VORPS,  VPABSD, VPABSQ, VPADDD, VPADDQ, 
VPANDD, VPANDQ, VPANDND, VPANDNQ, VPBLENDMB,  VPBLENDMD, VPBLENDMQ, VPBLENDMW, VPCMPD, 
VPCMPEQD, VPCMPEQQ, VPCMPGTD, VPCMPGTQ, VPCMPQ, VPCMPUD, VPCMPUQ, VPLZCNTD, VPLZCNTQ, 
VPMADD52LUQ, VPMADD52HUQ, VPMAXSD, VPMAXSQ, VPMAXUD, VPMAXUQ, VPMINSD, VPMINSQ, VPMINUD, 
VPMINUQ, VPMULLD, VPMULLQ, VPMULUDQ, VPMULDQ, VPORD, VPORQ, VPROLD, VPROLQ, VPROLVD, VPROLVQ, 
VPRORD, VPRORQ, VPRORVD, VPRORVQ, (VPSLLD, VPSLLQ, VPSRAD, VPSRAQ, VPSRAVW, VPSRAVD, VPSRAVW, VPSRAVQ, VPSRLD, VPSRLQ)
1, VPSUBD, VPSUBQ, VPSUBUSB, VPSU BUSW, VPTERNLOGD, VPTERNLOGQ, 
VPTESTMD, VPTESTMQ, VPTESTNMD, VPTESTNMQ, VPXORD, VPXORQ, VPSLLVD, VPSLLVQ, VRCP14PD, 
VRCP14PS, VRCPPH, VRSQRT14PD, VRSQRT14PS, VRSQRTPH, VXORPD, VXORPS
E4.nb2VCOMPRESSPD, VCOMPRESSPS, VEXPANDPD, VEXPANDPS, VMOVDQU8 , VMOVDQU16, VMOVDQU32, 
VMOVDQU64, VMOVUPD, VMOVUPS, VPABSB, VPABSW, VPADDB, VPADDW, VPADDSB,  VPADDSW, VPADDUSB, 
VPADDUSW, VPAVGB, VPAVGW, VPCMPB, VPCMPEQB, VPCMPEQW, VPCMPGTB, VPCMPGTW, VPCMPW, VPCMPUB, 
VPCMPUW, VPCOMPRESSD, VPCOMPRESSQ, VPEXPANDD, VPEXPANDQ, VPMAXSB, VPMAXSW, VPMAXUB, 
VPMAXUW, VPMINSB, VPMINSW, VPMINUB, VPMINU W, VPMULHRSW, VPMULHUW, VPMULHW, VPMULLW, 
VPSLLVW, VPSLLW, VPSRAW, VPSRLVW, VPSRLW, VPSUBB, VPSUBW, VPSUBSB, VPSUBSW, VPTESTMB, 
VPTESTMW, VPTESTNMB, VPTESTNMW
Type E4NFVALIGND, VALIGNQ, VPACKSSDW, VPACKUSDW, VPCONFLICTD, VPCONFLICTQ, VPERMD, VPERMI2D, VPERMI2PS, 
VPERMI2PD, VPERMI2Q, VPERMPD, VPERMPS, VPERMQ, VPERMT2D, VPERMT2PS, VPERMT2Q, VPERMT2PD, 
VPERMILPD, VPERMILPS, VPMULTISHIFTQB, VPSHUFD, VPUNPCKHDQ, VPUNPCKHQDQ, VPUNPCKLDQ, 
VPUNPCKLQDQ, VSHUFF32X4, VSHUFF6 4X2, VSHUFI32X4, VSHUFI64X2, VS HUFPD, VSHUFPS, VUNPCKHPD, 
VUNPCKHPS, VUNPCKLPD, VUNPCKLPS
E4NF.nb2VDBPSADBW, VPACKSSWB, VPACKUSWB, VPALIGNR, VPMADDWD, VPMADDUBSW, VMOVSHDUP, VMOVSLDUP, 
VPSADBW, VPSHUFB, VPSHUFHW, VPSHUFLW, VPSLLDQ, VPSRLDQ, VPSLLW, VPSRAW, VPSRLW, (VPSLLD, VPSLLQ, VPSRAD, VPSRAQ, VPSRLD, VPSRLQ)
3, VPUNPCKHBW, VPUNPCKHWD, VPUNPCKLBW, VPUNPCKLWD, 
VPERMW, VPERMI2W, VPERMT2W
Type E5PMOVSXBW, PMOVSXBW, PMOVSXBD, PMOVSXBQ, PMOVSXWD, PMOVSXWQ, PMOVSXDQ, PMOVZXBW, 
PMOVZXBD, PMOVZXBQ, PMOVZXWD, PMOVZXWQ, PMOVZXDQ, VCVTDQ2PD, VCVTUDQ2PD, VMOVSH, 
VPMOVSXxx, VPMOVZXxx, 
Type E5NF VMOVDDUP
Type E6VBROADCASTF32X2, VBROADCASTF32X4, VBROADCAST F64X2, VBROADCASTF32X8, VBROADCASTF64X4, 
VBROADCASTI32X2, VBROADCASTI32X4, VBROADCASTI64X2, VBROADCASTI32X8, VBROADCASTI64X4, 
VBROADCASTSD, VBROADCASTSS, VFPCLASSSD, VFPCLASSSS, VPBROADCASTB, VPBROADCASTD, VPBROADCASTW, VPBROADCASTQ, VPMOVQB, VPMOVSQB, VPMOVUSQB, VPMOVQW, VPMOVSQW, VPMOVUSQW, 
VPMOVQD, VPMOVSQD, VPMOVUSQD, VPMOVDB, VPMOVSDB, VPMOVUSDB, VPMOVDW, VPMOVSDW, 
VPMOVUSDW, VPMOVWB, VPMOVSWB, VPMOVUSWB
Type E6NFVEXTRACTF32X4, VEXTRACTF32X8, VEXTRACTF64X2, VEXTRACTF64X4, VEXTRACTI32X4, VEXTRACTI32X8, 
VEXTRACTI64X2, VEXTRACTI64X4,  VINSERTF32X4, VINSERTF32X8, VINSERTF64X2, VINSERTF64X4, 
VINSERTI32X4, VINSERTI32X8, VINSERTI64X2, VINS ERTI64X4, VPBROADCASTMB2Q, VPBROADCASTMW2D
Type 
E7NM.128
4VMOVHLPS, VMOVLHPS
Type E7NM.(VPBROADCASTD, VPBROADCASTQ, VPBROADCASTB, VPBROADCASTW)5, VPMOVB2M, VPMOVD2M, VPMOVM2B, 
VPMOVM2D, VPMOVM2Q, VPMOVM2W, VPMOVQ2M, VPMOVW2M
Type E9NFVEXTRACTPS, VINSERTPS, VMOVHPD, VMOVHPS, VMOVLPD, VMOVLPS, VMOVD, VMOVQ, VMOVW, VPEXTRB, 
VPEXTRD, VPEXTRW, VPEXTRQ, VPINSRB, VPINSRD, VPINSRW, VPINSRQ
Type E10VFCMADDCSH, VFMADDCSH, VFCMULCSH, VFMULCSH, VFPCLASSSH, VMOVSD, VMOVSS, VRCP14SD, VRCP14SS, 
VRCPSH, VRSQRT14SD, VRSQRT14SS, VRSQRTSH
Type E10NF (VCVTSI2SD, VCVTUSI2SD)6
Type E11 VCVTPH2PS, VCVTPS2PHTable 2-43.  EVEX Instructions in Each Exception Class (Contd.)
Exception Class Instruction2-48 Vol. 2AINSTRUCTION FORMAT
Type E12VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHE RQPD, VPGATHERDD, VPGATHERDQ, VPGATHERQD, 
VPGATHERQQ, VPSCATTERDD, VPSCATTERDQ, VPSCATTE RQD, VPSCATTERQQ, VSCA TTERDPD, VSCATTERDPS, 
VSCATTERQPD, VSCATTERQPS
Type E12NPVGATHERPF0DPD, VGATHERPF0DPS, VGATHERPF0QPD, VGATHERPF0QPS, VGATHERPF1DPD, VGATHERPF1DPS, 
VGATHERPF1QPD, VGATHERPF1QPS, VSCATTERPF0DPD, VSCATTERPF0DPS, VSCATTERPF0QPD, 
VSCATTERPF0QPS, VSCATTERPF1DPD, VSCATTER PF1DPS, VSCATTERPF1QP D, VSCATTERPF1QPS
NOTES:
1. Operand encoding Full tupletype with immediate.
2. Embedded broadcast is not supported with the “.nb” suffix.3. Operand encoding Mem128 tupletype.
4. #UD raised if EVEX.L’L !=00b (VL=128).
5. The source operand is a general purpose register.6. W0 enco ding only.Table 2-43.  EVEX Instructions in Each Exception Class (Contd.)
Exception Class InstructionVol. 2A 2-49INSTRUCTION FORMAT
2.8.1 Exceptions Type E1 and E1NF of EVEX-Encoded Instructions
EVEX-encoded instructions with memory alignment restri ctions, and supporting memory fault suppression follow 
exception class E1.
Table 2-44.  Type E1 Class Exception Conditions
Exception
Real
Virtual 80x86
#UDX X If EVEX prefix present.
XXIf CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies: 
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD co ndition of Table 2-40.
• EVEX.b encoding #UD condition of Table 2-41.• Instruction specific EVEX .L'L restriction not met.
X X If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Stack, #SS(0)X If fault suppression not set, and an  illegal address in the SS segment.
XIf fault suppression not set, and a memory  address referencing the SS segment is in 
a non-canonical form.
#GP(0)XXEVEX.512: Memory operand is not 64-byte aligned.
EVEX.256: Memory operand is not 32-byte aligned.
EVEX.128: Memory operand is not 16-byte aligned.
XIf fault suppression not set, and an illegal memory operand effective address in the 
CS, DS, ES, FS or GS segments.
X If fault suppression not set,  and the memory address is in a non-canonical form.
XXIf fault suppression not set,  and any part of the operand lies outside the effective 
address space from 0 to FFFFH.
Page Fault 
#PF(fault-code)X X X If fault suppression not set, and a page fault.2-50 Vol. 2AINSTRUCTION FORMAT
EVEX-encoded instructions with memory alignment rest rictions, but do not support memory fault suppression 
follow exception class E1NF.
Table 2-45.  Type E1NF Class Exception Conditions
Exception
Real
• State requirement,  Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.• Opmask encoding #UD co ndition of Table 2-40.
• EVEX.b encoding #UD condition of Table 2-41.
• Instruction specific EVEX.L'L restriction not met.
ments.
Page Fault 
#PF(fault-code)X X X For a page fault.Vol. 2A 2-51INSTRUCTION FORMAT
2.8.2 Exceptions Type E2 of EVEX-Encoded Instructions
EVEX-encoded vector instructions with arit hmetic semantic follow exception class E2.
Table 2-46.  Type E2 Class Exception Conditions
Exception
Real
X X X X If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 0. 
If any one of following conditions applies: • State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.• Operand encoding #UD conditions in Table 2-39.• Opmask encoding #UD condition of Table 2-40.
• Instruction specific EVEX .L'L restriction not met.

Page Fault 
Exception
Real
able, #NMXX XX I f  C R 0 . T S [ b i t  3 ] = 1 .
XIf fault suppression not set, and a memory address referencing the SS segment is in a 
non-canonical form.
tion, #GP(0)XIf fault suppression no t set, and an illegal memory operand effective address in the CS, 
DS, ES, FS or GS segments.
Page Fault 
#PF(fault-code)X X X If fault suppression no t set, and a page fault.
#AC(0)XX XFor 2, 4, or 8 byte memory access if alig nment checking is enabled and an unaligned 
memory access is made while the current privilege level is 3.
point Exception, 
#XMXX XXIf an unmasked SIMD floating-point exceptio n, {sae} or {er} not set, and CR4.OSXMMEX-
CPT[bit 10] = 1.2-52 Vol. 2AINSTRUCTION FORMAT
2.8.3 Exceptions Type E3 and E3 NF of EVEX-Encoded Instructions
EVEX-encoded scalar instructions with arithmetic semantic that support memory fault suppression follow exception 
class E3.
Table 2-47.  Type E3 Class Exception Conditions
Exception
Real
Invalid Opcode, #UDX X If EVEX prefix present.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.• EVEX.b encoding #UD condition of Table 2-41.
XIf fault suppression not set, and a memory address referencing the SS segment is 
in a non-canonical form.
#GP(0)XIf fault suppression not set,  and an illegal memory operand effective address in 
the CS, DS, ES, FS or GS segments.
X If fault suppression not set, and the memo ry address is in a non-canonical form.
code)X X X If fault suppression not set, and a page fault.
#AC(0)XX XFor 2, 4, or 8 byte memo ry access if alignment checking is enabled and an 
Exception, #XMXXX XIf an unmasked SIMD floating-point except ion, {sae} or {er} not set, and CR4.OSX-
MMEXCPT[bit 10] = 1.Vol. 2A 2-53INSTRUCTION FORMAT
EVEX-encoded scalar instructions with arithmetic semant ic that do not support memory fault suppression follow 
exception class E3NF.
Table 2-48.  Type E3NF Class Exception Conditions
Exception
Real
Invalid Opcode, #UDX X EVEX prefix.
If any one of following conditions applies: • State requirement,  Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.• Operand encoding #UD conditions in Table 2-39.• Opmask encoding #UD co ndition of Table 2-40.
Stack, #SS(0)X For an illegal addres s in the SS segment.
ments.
FFFFH.
Exception, #XMXXX XIf an unmasked SIMD floati ng-point exception, {sae} or  {er} not set, and CR4.OSX-
MMEXCPT[bit 10] = 1.2-54 Vol. 2AINSTRUCTION FORMAT
2.8.4 Exceptions Type E4 and E4 NF of EVEX-Encoded Instructions
EVEX-encoded vector instructions that cause no SIMD FP  exception and support memory fault suppression follow 
exception class E4.
Table 2-49.  Type E4 Class Exception Conditions
Exception
Real
• Opmask encoding #UD condition of Table 2-40.
• EVEX.b encoding #UD condition of Table 2-41 and in E4.nb subclass (see E4.nb 
entries in Table 2-43).
Stack, #SS(0)X If fault suppression not set, and an illegal address in the SS segment.
XIf fault suppression not set,  and a memory address referencing the SS segment is 
#GP(0)XIf fault suppression not set, and an illegal memory operand effective address in 
X If fault suppression not set, and the memory address is in a non-canonical form.
XXIf fault suppression not set, and any part of the operand lies outside the effective 
unaligned memory access is made while the current privilege level is 3.Vol. 2A 2-55INSTRUCTION FORMAT
EVEX-encoded vector instructions that do not cause SI MD FP exception nor support memory fault suppression 
follow exception class E4NF.
Table 2-50.  Type E4NF Class Exception Conditions
Exception
Real
• EVEX.b encoding #UD condition of Table 2-41 and in E4NF.nb subclass (see 
E4NF.nb entries in Table 2-43).
ments.
FFFFH.
code)X X X For a page fault.2-56 Vol. 2AINSTRUCTION FORMAT
2.8.5 Exceptions Type E5 and E5NF
EVEX-encoded scalar/partial-vector instructions that cause no SIMD FP exception and support memory fault 
suppression follow exception class E5.
EVEX-encoded scalar/partial vector instructions that do  not cause SIMD FP exception nor support memory fault 
suppression follow exception class E5NF.Table 2-51.  Type E5 Class Exception Conditions
Exception
Real

Exception
Real
Stack, #SS(0)X If fault suppression not set, and an  illegal address in  the SS segment.
#GP(0)XIf fault suppression not set, and an illegal memory operand effective address in the 
unaligned memory access is made while the current privilege level is 3.Vol. 2A 2-57INSTRUCTION FORMAT
Table 2-52.  Type E5NF Class Exception Conditions
Exception
Real
Stack, #SS(0)X If an illegal addres s in the SS segment.
#GP(0)X If an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
FFFFH.
unaligned memory access is made while the current privilege level is 3.2-58 Vol. 2AINSTRUCTION FORMAT
2.8.6 Exceptions Type E6 and E6NF
Table 2-53.  Type E6 Class Exception Conditions
Exception
Real
• EVEX.b encoding #UD co ndition of Table 2-41.
#GP(0)XIf fault suppression not set,  and an illegal memory operand effective address in the 
code)X X If fault suppression no t set, and a page fault.
#AC(0)XXFor 2, 4, or 8 byte memory access if alignment checking is enabled and an 
unaligned memory access is made while the current privilege level is 3.Vol. 2A 2-59INSTRUCTION FORMAT
EVEX-encoded instructions that do not cause SIMD FP  exception nor support memory fault suppression follow 
exception class E6NF.
Table 2-54.  Type E6NF Class Exception Conditions
Exception
Real
Invalid Opcode, #UD X X If EVEX prefix present.
X X If preceded by a LOCK prefix (F0H).X X If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
ments.
code)X X For a page fault.
unaligned memory access is made while the current privilege level is 3.2-60 Vol. 2AINSTRUCTION FORMAT
2.8.7 Exceptions Type E7NM
EVEX-encoded instructions that cause no SIMD FP except ion and do not reference memory follow exception class 
E7NM.
Table 2-55.  Type E7NM Class Exception Conditions
Exception
Real
• Instruction specific EVEX.L’L restriction not met.
#NMXX I f  C R 0 . T S [ b i t  3 ] = 1 .Vol. 2A 2-61INSTRUCTION FORMAT
2.8.8 Exceptions Type E9 and E9NF
EVEX-encoded vector or partial-vector instructions that  do not cause no SIMD FP exception and support memory 
fault suppression follow exception class E9.
Table 2-56.  Type E9 Class Exception Conditions
Exception
Real
• EVEX.b encoding #UD condition of Table 2-41.• Instruction specific EVEX.L'L restriction not met.
XIf fault suppression not set, and a memory  address referencing the SS segment is 
unaligned memory access is made while the current privilege level is 3.2-62 Vol. 2AINSTRUCTION FORMAT
EVEX-encoded vector or partial-vector instructions that must be encoded with VEX.L’L = 0, do not cause SIMD FP 
exception nor support memory fault suppression follow exception class E9NF.
Table 2-57.  Type E9NF Class Exception Conditions
Exception
Real
Device Not Available,

Exception
Real
Stack, #SS(0)X If an illegal address in the SS segment.
FFFFH.
unaligned memory access is made while the current privilege level is 3.Vol. 2A 2-63INSTRUCTION FORMAT
2.8.9 Exceptions Type E10 and E10NF
EVEX-encoded scalar instructions that ig nore EVEX.L’L vector length encoding , do not cause a SIMD FP exception, 
and support memory fault suppression follow exception class E10.
Table 2-58.  Type E10 Class Exception Conditions
Exception
Real
unaligned memory access is made while the current privilege level is 3.2-64 Vol. 2AINSTRUCTION FORMAT
and do not support memory fault suppression follow exception class E10NF.
Table 2-59.  Type E10NF Class Exception Conditions
Exception
Real
unaligned memory access is made while the current privilege level is 3.Vol. 2A 2-65INSTRUCTION FORMAT
2.8.10 Exceptions Type E11 (E VEX-only, Mem Arg, No AC, Floating-point Exceptions)
EVEX-encoded instructions that can ca use SIMD FP exception, memory oper and support fault suppression but do 
not cause #AC follow exception class E11.
Table 2-60.  Type E11 Class Exception Conditions
Exception
Real
X X If CR4.OSXSAVE[bit 18]=0.
Stack, #SS(0) X If fault suppression not set, and an illegal address in the SS segment.
X If fault suppression not set, and a memory  address referencing the SS segment is 
#GP(0)X If fault suppression not set,  and an illegal memory operand effective address in the 
X X If fault suppression not set, and any part of the operand lies outside the effective 
Exception, #XMX X X X If an unmasked SIMD floating-point exception, {sae} not set, and CR4.OSXMMEX-
CPT[bit 10] = 1.2-66 Vol. 2AINSTRUCTION FORMAT
2.8.11 Exceptions Type E12 and E12NP (VSIB Mem Arg, No AC, No Floating-point Exceptions)
Table 2-61.  Type E12 Class Exception Conditions
Exception
Real
• Instruction specific EVEX.L'L restriction not met.• If vvvv != 1111b.
X X X NA If address size attribute is 16 bit.
X X X X If ModR/M.mod = ‘11b’.
X X X X If ModR/M.rm != ‘100b’.X X X X If any corresponding CPUID feature flag is ‘0’.
X X X X If k0 is used (gather or scatter operation).
X X X X If index = destination register (gather operation).
Stack, #SS(0) X For an illega l address in the SS segment.
ments.
FFFFH.
code)X X X For a page fault.Vol. 2A 2-67INSTRUCTION FORMAT
EVEX-encoded prefetch instructions that do not cause #PF follow exception class E12NP.
Table 2-62.  Type E12NP Class Exception Conditions
Exception
Real
X X X X If ModR/M.rm != ‘100b’.
X X X X If any corresponding CPUID feature flag is ‘0’.X X X X If k0 is used (gathe r or scatter operation).
#NMXX X XI f  C R 0 . T S [ b i t  3 ] = 1 .2-68 Vol. 2AINSTRUCTION FORMAT
2.9 EXCEPTION CLASSIFICATIONS OF OP MASK INSTRUCTIONS, TYPE K20 AND 
TYPE K21
The exception behavior of VEX-encoded opmask instructions are listed below.
2.9.1 Exceptions Type K20
Exception conditions of Opmask instructions that do not address memory are listed as Type K20.
Table 2-63.  TYPE K20 Exception Definition (VEX -Encoded OpMask Instru ctions w/o Memory Arg)
Exception
Real

TYPE K21
Exception
Real
Invalid Opcode, #UD X X X X If relevant CPUID feature flag is ‘0’.
X X If a VEX prefix is present.
X X If ModRM:[7:6] != 11b.
#NMX X X X If CR0.TS[bit 3]=1.Vol. 2A 2-69INSTRUCTION FORMAT
2.9.2 Exceptions Type K21
Exception conditions of Opmask instructions that address memory are listed as Type K21.
Table 2-64.  TYPE K21 Exception Definition (VEX-E ncoded OpMask Instructio ns Addressing Memory)
Exception
Real
Stack, #SS(0) X X X For an ille gal address in the SS segment.
ments. If the DS, ES, FS, or GS regi ster is used to access me mory and it contains a null 
FFFFH.
#AC(0)X X X For 2, 4, or 8 byte memory access if  alignment checking is enabled and an 
unaligned memory access is made while the current privilege level is 3.2-70 Vol. 2AINSTRUCTION FORMAT
2.10 INTEL® AMX INSTRUCTION EXCEPTION CLASSES
Alignment exceptions: The Intel AMX instructions that  access memory will never generate #AC exceptions.
Table 2-65.  Intel® AMX Exception Classes 
Class Description
AMX-E1• #UD if preceded by LOCK, 66H, F2H, F3H or REX prefixes.
• #UD if CR4.OSXSAVE ≠ 1.
• #UD if XCR0[18:17] ≠ 0b11.
• #UD if IA32_EFER.LMA ≠ 1 OR CS.L ≠ 1.
• #UD if VVVV ≠ 0b1111.
• #GP based on palette and configuration checks (see pseudocode).
• #GP if the memory address is in a non-canonical form.
• #SS(0) if the memory address referencing the SS segment is in a non-canonical form.
• #PF if a page fault occurs.
AMX-E2• #UD if preceded by LOCK, 66H, F2H, F3H or REX prefixes.
• #GP if the memory address is in a non-canonical form.• #SS(0) if the memory address referencing the SS segment is in a non-canonical form.
AMX-E3• #UD if preceded by LOCK, 66H, F2H, F3H or REX prefixes.
• #UD if CR4.OSXSAVE 
≠ 1.
• #UD if not using SIB addressing.
• #UD if TILES_CO NFIGURED == 0.
• #UD if tsrc or tdes t are not valid tiles.
• #UD if tsrc/tdest are ≥ palette_table[tilecfg.palette_id].max_names.
• #UD if tsrc.colbytes mod 4 ≠ 0 OR tdest.colbytes mod 4 ≠ 0.
• #UD if tilecfg.start_row ≥ tsrc.rows OR tilecfg.start_row ≥ tdest.rows.
• #PF if any memory operand causes a page fault.
• #NM if XFD[18] == 1.Vol. 2A 2-71INSTRUCTION FORMAT
AMX-E4• #UD if preceded by LOCK, 66H, F2H, F3H or REX prefixes.
• #UD if srcdest == src1 OR src1  == src2 OR srcdest == src2.
• #UD if TILES_CONFIGURED == 0.
• #UD if srcdest.colbytes mod 4 ≠ 0.
• #UD if src1.colbytes mod 4 ≠ 0.
• #UD if src2.colbytes mod 4 ≠ 0.
• #UD if srcdest/src1/src2 are not valid tiles.• #UD if srcdest/src1/src2 are 
≥ palette_table[tilecfg.palette_id].max_names.
• #UD if srcdest.colbytes ≠ src2.colbytes.
• #UD if srcdest.rows ≠ src1.rows.
• #UD if src1.colbytes / 4 ≠ src2.rows.
• #UD if srcdest.colbytes > tmul_maxn.
• #UD if src2.colbytes > tmul_maxn.
• #UD if src1.colbytes/4 > tmul_maxk.
• #UD if src2.rows > tmul_maxk.
• #NM if XFD[18] == 1.
AMX-E5• #UD if preceded by LOCK, 66H, F2H, F3H or REX prefixes.
• #UD if TILES_CONFIGURED == 0.• #UD if tdest is not a valid tile.
• #UD if tdest is 
≥ palette_table[tilecfg. palette_id].max_names.
AMX-E6• #UD if preceded by LOCK, 66H, F2H, F3H or REX prefixes.
• #UD if VVVV ≠ 0b1111.Table 2-65.  Intel® AMX Exception Classes  (Contd.)
Class Description2-72 Vol. 2AINSTRUCTION FORMATVol. 2A 3-1CHAPTER 3
This chapter describes the instruction set for the Intel 64 and IA-32 architectures (A -L) in IA-32e, protected, 
virtual-8086, and real-address modes of operation. The set includes general-purpose, x87 FPU, MMX, SSE/SSE2/SSE3/SSSE3/SSE4, AESNI/PCLMULQDQ, AVX, and system instructions. See also Chapter 4, “Instruc-
tion Set Reference, M-U,” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B; 
Chapter 5, “Instruction Set Reference, V,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2C; and Chapter 6, “Instruction  Set Reference, W-Z,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2D.
For each instruction, each operand combination is described. A description of the instruction and its operand, an 
operational description, a description of the effect of the instructions on flags in the EFLAGS register, and a 
summary of exceptions that can be generated are also provided.
3.1 INTERPRETING THE INST RUCTION REFERENCE PAGES
This section describes the format of information contained in the instruction reference pages in this chapter. It 
explains notational conventions and abbreviations used in these sections.
3.1.1 Instruction Format
The following is an example of the format used for each instruction description in this  chapter. The heading below 
introduces the example. The table below provides an example summary table.
CMC—Complement Carry Flag  [this is an example]
Instruction Operand EncodingOpcode Instruction Op/En 64/32-bit 
ModeCPUID 
Feature FlagDescription
F5 CMC ZO V/V N/A Complement carry flag.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ZO N/A N/A N/A N/AINSTRUCTION SET REFERENCE, A-L
3-2 Vol. 2A3.1.1.1  Opcode Column in the Instruction Su mmary Table (Instructions without VEX Prefix)
The “Opcode” column in the table above shows the object code produced for each form of the instruction. When 
possible, codes are given as hexadecimal bytes in the same  order in which they appear in memory. Definitions of 
entries other than hexadecimal bytes are as follows:
•NP — Indicates the use of 66/F2/F3 prefixes (beyond thos e already part of the instructions opcode) are not 
allowed with the instruction. Such use will either ca use an invalid-opcode exception (#UD) or result in the 
encoding for a different instruction.
•NFx — Indicates the use of F2/F3 prefixes (beyond those already part of the instructions opcode) are not 
•REX.W — Indicates the use of a REX prefix that affects oper and size or instruction semantics. The ordering of 
the REX prefix and other optional/m andatory instruction prefixes are discussed Chapter 2. Note that REX 
prefixes that promote legacy instructions to 64-bit be havior are not listed explicitly in the opcode column.
•/digit — A digit between 0 and 7 indicates that the ModR/M by te of the instruction uses only the r/m (register 
or memory) operand. The reg field contains the digit that provides an extension to the instruction's opcode.
•/r — Indicates that the ModR/M byte of the instruction contains a register operand and an r/m operand.
•cb, cw, cd, cp, co, ct — A 1-byte (cb), 2-byte (cw), 4-byte (cd), 6-by te (cp), 8-byte (co) or 10-byte (ct) value 
following the opcode. This value is used to specify a co de offset and possibly a new value for the code segment 
register.
•ib, iw, id, io — A 1-byte (ib), 2-byte (iw), 4-byte (id) or 8-byte  (io) immediate operand to the instruction that 
follows the opcode, ModR/M bytes or scale-indexing bytes.  The opcode determines if the operand is a signed 
value. All words, doublewords, and quadword s are given with the low-order byte first.

register.
•+rb, +rw, +rd, +ro — Indicated the lower 3 bits of the opcode byte  is used to encode the register operand 
without a modR/M byte. The instruction lists the correspon ding hexadecimal value of the opcode byte with low 
3 bits as 000b. In non-64-bit mode, a register code, from  0 through 7, is added to the hexadecimal value of the 
opcode byte. In 64-bit mode, indicates the four bit fiel d of REX.b and opcode[2:0] field encodes the register 
operand of the instruction. “+ro” is applicable only in 64-bit mode. See Table 3-1 for the codes.
• +i — A number used in floating-point instructions when one of  the operands is ST(i) from the FPU register stack. 
The number i (which can range from 0 to 7) is added to the hexadecimal byte given at the left of the plus sign 
to form a single opcode byte.
Table 3-1.  Register Codes Associ ated With +rb, +rw, +rd, +ro
byte register word register dwor d register quadword register 
(64-Bit Mode only)Register
REX.B 
Reg Field
Register
REX.B
Reg Field
Register
REX.B 
Reg Field
Register
REX.B 
Reg Field
AL None 0 AX None 0 EAX None 0 RAX None 0
CL None 1 CX None 1 ECX None 1 RCX None 1DL None 2 DX None 2 EDX None 2 RDX None 2
BL None 3 BX None 3 EBX None 3 RBX None 3
AH Not 
encodable (N.E.)4 SP None 4 ESP None 4 N/A N/A N/A
CH N.E. 5 BP None 5 EBP None 5 N/A N/A N/A
DH N.E. 6 SI None 6 ESI None 6 N/A N/A N/A
BH N.E. 7 DI None 7 EDI None 7 N/A N/A N/ASPL Yes 4 SP None 4 ESP None 4 RSP None 4
BPL Yes 5 BP None 5 EBP None 5 RBP None 5INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-33.1.1.2  Opcode Column in the Instruction Summary Table (Instructi ons with VEX prefix)
In the Instruction Summary Table, the Opcode column pres ents each instruction encoded using the VEX prefix in 
following form (including the modR/M byte if applicable, the immediat e byte if applicable):
VEX.[128,256].[66,F2,F3].0F/0F3A/0F38 .[W0,W1] opcode [/r] [/ib,/is4]
•VEX — Indicates the presence of the VEX prefix is requ ired. The VEX prefix can be  encoded using the three-
byte form (the first byte is C4H), or  using the two-byte form (the first by te is C5H). The two-byte form of VEX 
only applies to those instructions that do not require the following fields to be encoded: VEX.mmmmm, VEX.W, 
VEX.X, VEX.B. Refer to Section 2.3 for more detail on the VEX prefix.
The encoding of various sub-fields of the VEX prefix is described using the following notations:
—128,256:  VEX.L field can be 0 (denoted by VEX.128, VEX. L0, or VEX.LZ) or 1 (denoted by VEX.256 or 
VEX.L1). The VEX.L field can be encoded using either the 2-byte or 3-byte form of the VEX prefix. The 
presence of the notation VEX.256 or VEX.128 in the opcode column should be interpreted as follows:
•If VEX.256 is present in the opcode column: The se mantics of the instruction must be encoded with 
VEX.L = 1. An attempt to encode this instruction with  VEX.L= 0 can result in one of two situations: (a) 
if VEX.128 version is defined, the processor will beha ve according to the defi ned VEX.128 behavior; (b) 
an #UD occurs if there is no VEX.128 version defined.
•If VEX.128 is present in the opcode column but there is no VEX.256 version defined for the same 
opcode byte: Two situations apply: (a) For VEX-encoded, 128-bit SIMD integer instructions, software must encode the instruction with VEX.L = 0. The processor will treat the opcode byte encoded with 
VEX.L= 1 by causing an #UD exception; (b) For VE X-encoded, 128-bit packed floating-point instruc-
tions, software must encode the instruction with VEX.L = 0. The processor will treat the opcode byte 
encoded with VEX.L= 1 by causing an #UD exception (e.g., VMOVLPS).
•If VEX.L0 or VEX.L1 is present in the opcode column : The specified VEX.L value is required for encoding 
this instruction but does not have the connotation of specifying vector length.
•If VEX.LIG is present in the opcode  column: The VEX.L value is ignore d. This generally applies to VEX-
encoded scalar SIMD floating-point instructions. Scalar SIMD floating-point instruction can be distin-
guished from the mnemonic of the instruction. Ge nerally, the last two letters of the instruction 
mnemonic would be either “SS”, “SD”, or “SI” for SIMD floating-point conversion instructions.
•If VEX.LZ is present in the opcode column: The VEX.L must be encoded to be 0B, an #UD occurs if 
VEX.L is not zero.SIL Yes 6 SI None 6 ESI None 6 RSI None 6
DIL Yes 7 DI None 7 EDI None 7 RDI None 7
Registers R8 - R15 (see below): Available in 64-Bit Mode OnlyR8B Yes 0 R8W Yes 0 R8D Yes 0 R8 Yes 0
R9B Yes 1 R9W Yes 1 R9D Yes 1 R9 Yes 1
R10B Yes 2 R10W Yes 2 R10D Yes 2 R10 Yes 2R11B Yes 3 R11W Yes 3 R11D Yes 3 R11 Yes 3
R12B Yes 4 R12W Yes 4 R12D Yes 4 R12 Yes 4
R13B Yes 5 R13W Yes 5 R13D Yes 5 R13 Yes 5
R14B Yes 6 R14W Yes 6 R14D Yes 6 R14 Yes 6
R15B Yes 7 R15W Yes 7 R15D Yes 7 R15 Yes 7Table 3-1.  Register Codes Associated  With +rb, +rw, +rd, +ro (Contd.)
byte register word register dword register quadword register 
REX.B 
Reg Field
Register
REX.B
Reg Field
Register
REX.B 
Reg Field
Register
REX.B 
Reg FieldINSTRUCTION SET REFERENCE, A-L
3-4 Vol. 2A—66,F2,F3: The presence or absence of these values map to  the VEX.pp field encodings. If absent, this 
corresponds to VEX.pp=00B. If present, the correspondi ng VEX.pp value affects the “opcode” byte in the 
same way as if a SIMD prefix (66H, F2H or F3H) does to the ensuing opcode byte. Thus a non-zero encoding 
of VEX.pp may be considered as an implied 66H/F2H/F3H prefix. The VEX.pp field may be encoded using 
either the 2-byte or 3-byte form of the VEX prefix.
—0F,0F3A,0F38: The presence maps to a valid encoding of the VEX.mmmmm field. Only three encoded 
values of VEX.mmmmm are defined as valid, corresponding  to the escape byte sequence of 0FH, 0F3AH, 
and 0F38H. The effect of a valid VEX.mmmmm encoding on  the ensuing opcode byte is same as if the corre-
sponding escape byte sequence on the ensuing opcode  byte for non-VEX encoded instructions. Thus a valid 
encoding of VEX.mmmmm may be consider as an implie s escape byte sequence of either 0FH, 0F3AH or 
0F38H. The VEX.mmmmm field must be encoded using the 3-byte fo rm of VEX prefix. 
—0F,0F3A,0F38 and 2-byte/3-byte VEX: The presence of 0F3A and 0F38 in the opcode column implies 
that opcode can only be encoded by the three-byte form  of VEX. The presence of 0F in the opcode column 
does not preclude the opcode to be encoded by the two-byte of VEX if th e semantics of the opcode does not 
require any subfield of VEX not present in  the two-byte form of the VEX prefix.
—W0: VEX.W=0. 
—W1: VEX.W=1.
— The presence of W0/W1 in the opcode column applies to two situations: (a) it is treated as an extended 
opcode bit, (b) the instruction semantics support an operand size promotion to 64-bit of a general-purpose 
register operand or a 32-bit memory operand. The presen ce of W1 in the opcode column implies the opcode 
must be encoded using the 3-byte form of the VEX pref ix. The presence of W0 in the opcode column does 
not preclude the opcode to be encoded using the C5H fo rm of the VEX prefix, if the semantics of the opcode 
does not require other VEX subfields not present in the two-byte form of the VEX prefix. Please see Section 
2.3 on the subfield definitions within VEX.
—WIG: can use C5H form (if not requiring VEX.mmmmm) or VEX.W value is ignored in the C4H form of VEX 
prefix.
— If WIG is present, the instruction may be encoded using either the two-byte form or the three-byte form of 
VEX. When encoding the instruction using the three-by te form of VEX, the valu e of VEX.W is ignored. 
•opcode — Instruction opcode.
•/is4 — An 8-bit immediate byte is present containing a sour ce register specifier in either imm8[7:4] (for 64-bit 
mode) or imm8[6:4] (for 32-bit mode), and instruction-specific payload in imm8[3:0].
•In general, the encoding o f VEX.R, VEX.X, VEX.B fiel d are not shown explicitly in the opcode column. The 
encoding scheme of VEX.R, VEX.X, VEX.B fields  must follow the rules defined in Section 2.3.
EVEX.[128,256,512,LLIG].[66,F2,F3].0F/0F3A/0F38.[W0,W1,WIG] opcode [/r] [ib]
•EVEX — The EVEX prefix is encoded using the four-byte form (the first byte is 62H). Refer to Section 2.7.1 for 
more detail on the EVEX prefix.
The encoding of various sub-fields of the EVEX prefix is described using the following notations:
—128, 256, 512, LLIG:  This corresponds to the vector length; th ree values are allowed by EVEX: 512-bit, 
256-bit and 128-bit. Alternatively, vector length is ignored (LIG) for certain instructions; this typically 
applies to scalar instructions operating on one data element of a vector register.
—66,F2,F3: The presence of these value maps to the EVEX .pp field encodings. Th e corresponding VEX.pp 
value affects the “opcode” byte in the same way as if a SIMD prefix (66H, F2H or F3H) does to the ensuing 
opcode byte. Thus a non-zero encoding of VEX.pp ma y be considered as an implied 66H/F2H/F3H prefix.

opcode byte. Thus a non-zero encoding of VEX.pp ma y be considered as an implied 66H/F2H/F3H prefix. 
—0F,0F3A,0F38: The presence maps to a valid encoding of th e EVEX.mmm field. Only three encoded values 
of EVEX.mmm are defined as valid, corresponding to th e escape byte sequence of 0FH, 0F3AH, and 0F38H. 
The effect of a valid EVEX.mmm encoding on the ensuin g opcode byte is the same as if the corresponding 
escape byte sequence on the ensu ing opcode byte for non-EVEX en coded instructions. Thus a valid 
encoding of EVEX.mmm may be considered as an implie d escape byte sequence of either 0FH, 0F3AH or 
0F38H. 
—W0: EVEX.W=0. INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-5—W1: EVEX.W=1.
—WIG: EVEX.W bit ignored
•In general, the encoding of EVEX.R and R’, EVEX.X and X’ , and EVEX.B and B’ fields are not shown explicitly in 
the opcode column. 
NOTE
Previously, the terms NDS, NDD, and DDS were used in instructions with an EVEX (or VEX) prefix. 
These terms indicated that the vvvv field was va lid for encoding, and specified register usage. 
These terms are no longer necessary and are redundant with the instruction operand encoding tables provided with each instruction. The instruct ion operand encoding tables give explicit details 
on all operands, indicating where every operand is st ored and if they are read or written. If vvvv is 
not listed as an operand in the in struction operand encoding table, then EVEX (or VEX) vvvv must 
be 0b1111.
3.1.1.3  Instruction Column in the Opcode Summary Table
The “Instruction” column gives the synt ax of the instruction statement as it would appear in an ASM386 program. 
The following is a list of the symbols used to re present operands in the instruction statements:
•rel8 — A relative address in the range from 128 bytes befo re the end of the instruction to 127 bytes after the 
end of the instruction.
•rel16, rel32 — A relative address within the same code segment as the instruction assembled. The rel16 
symbol applies to instructions with an operand-size attrib ute of 16 bits; the rel32 symbol applies to instructions 
with an operand-size attribute of 32 bits.
•ptr16:16, ptr16:32 — A far pointer, typically to a code segment different from that of the instruction. The 
notation 16:16  indicates that the value of the pointer has two pa rts. The value to the left of the colon is a 16-
bit selector or value destined for the code segment regi ster. The value to the right corresponds to the offset 
within the destination segment. The ptr16:16 symbol is used when the instruction's operand-size attribute is 
16 bits; the ptr16:32 symbol is used when the operand-size attribute is 32 bits.
•r8 — One of the byte general-purpose registers: AL, CL, DL, BL, AH, CH, DH, BH, BPL, SPL, DIL, and SIL; or 
one of the byte registers (R8B - R15B) av ailable when using REX.R and 64-bit mode. 
•r16 — One of the word general-purpose registers: AX, CX, DX, BX, SP, BP, SI, DI; or one of the word registers 
(R8-R15) available when using REX.R and 64-bit mode.
•r32 — One of the doubleword general-purpose registers: EAX,  ECX, EDX, EBX, ESP, EBP, ESI, EDI; or one of 
the doubleword registers (R8D - R15D) ava ilable when using REX.R in 64-bit mode.
•r64 — One of the quadword general-purpose registers: RA X, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8–R15. 
These are available when using REX.R and 64-bit mode.
•imm8 — An immediate byte value. The imm8 symbol is a signed number between –128 and +127 inclusive. 
For instructions in which imm8 is combined with a word  or doubleword operand, the immediate value is sign-
extended to form a word or doubleword. The upper byte  of the word is filled with the topmost bit of the 
immediate value.
•imm16 — An immediate word value used for instructions whose operand-size attribute is 16 bits. This is a 
number between –32,768 and +32,767 inclusive.
•imm32 — An immediate doubleword value used for instructions whose operand-size attribute is 32 
bits. It allows the use of a number betw een +2,147,483,647 and –2,147,483,648 inclusive.
•imm64 — An immediate quadword value used for instruct ions whose operand-size attribute is 64 bits. 
The value allows the use of a number between +9,223,372,036,854,775,807 and –9,223,372,036,854,775,808 inclusive.
•r/m8 — A byte operand that is either the contents of a by te general-purpose register (AL, CL, DL, BL, AH, CH, 
DH, BH, BPL, SPL, DIL, and SIL) or a byte from memo ry. Byte registers R8B - R15B are available using REX.R 
in 64-bit mode.INSTRUCTION SET REFERENCE, A-L
3-6 Vol. 2A•r/m16 — A word general-purpose register or memory op erand used for instructions whose operand-size 
attribute is 16 bits. The word general-purpose register s are: AX, CX, DX, BX, SP, BP, SI, DI. The contents of 
memory are found at the address provided by the effe ctive address computation. Word registers R8W - R15W 
are available using REX.R in 64-bit mode.
•r/m32  — A doubleword general-purpose register or memo ry operand used for instructions whose operand-
size attribute is 32 bits. The doubleword general-purpos e registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI, 
EDI. The contents of memory are found at the addr ess provided by the effect ive address computation. 
Doubleword registers R8D - R15D are available when using REX.R in 64-bit mode.
•r/m64 — A quadword general-purpose register or memory operand used for instructions whose operand-size 
attribute is 64 bits when using REX.W. Quadword gene ral-purpose registers are: RA X, RBX, RCX, RDX, RDI, 
RSI, RBP, RSP, R8–R15; these are available only in 64 -bit mode. The contents of memory are found at the 
address provided by the ef fective address computation.
•reg — A general-purpose register used for instructions when the width of the register does not matter to the 
semantics of the operation of the instruction. The register can be r16, r32, or r64.
•m — A 16-, 32- or 64-bit operand in memory.
•m8 — A byte operand in memory, usually expressed as a variable or array name, but pointed to by the 
DS:(E)SI or ES:(E)DI registers. In  64-bit mode, it is pointed to by the RSI or RDI registers.
•m16 — A word operand in memory, usually expressed as a variable or array name, but pointed to by the 
DS:(E)SI or ES:(E)DI registers. This nomenclature  is used only with the string instructions.
•m32 — A doubleword operand in memory. The contents of  memory are found at the address provided by the 
effective address computation.
•m64 — A memory quadword operand in memory. 
•m128 — A memory double quadword operand in memory. 
•m16:16, m16:32 & m16:64 — A memory operand containing a far pointer composed of two numbers. The 
number to the left of the colon corresponds to the pointer's segment selector. The number to the right 
corresponds to its offset.
•m16&32, m16&16, m32&32, m16&64 — A memory operand consisting of data item pairs whose sizes are 
indicated on the left and the right side of the ampe rsand. All memory addressing modes are allowed. The 
m16&16 and m32&32 operands are used by the BOUND in struction to provide an operand containing an upper 
and lower bounds for array indices. The m16&32 operand is  used by LIDT and LGDT to provide a word with 
which to load the limit field, and a do ubleword with which to load the base field of the corresponding GDTR and 
IDTR registers. The m16&64 operand is used by LIDT and LGDT in 64-bit mode to provide a word with which to 
load the limit field, and a quadword with which to load the base field of the corresponding GDTR and IDTR 
•m80bcd — A Binary Coded Decimal (BCD) operand in memory, 80 bits.
•moffs8, moffs16, moffs32, moffs64 — A simple memory variable (memor y offset) of type byte, word, or 
doubleword used by some variants of the MOV instruct ion. The actual address is given by a simple offset 
relative to the segment base. No ModR/M byte is us ed in the instruction. The number shown with moffs 
indicates its size, which is determined by th e address-size attribute of the instruction. 
•Sreg — A segment register. The segment register bit assign ments are ES = 0, CS = 1, SS = 2, DS = 3, FS = 4, 
and GS = 5.
•m32fp, m64fp, m80fp — A single precision, double precision, an d double extended-precision (respectively) 
floating-point operand in memory. These symbols designate floating-point values that are used as operands for 
x87 FPU floating-point instructions.
•m16int, m32int, m64int — A word, doubleword, and qu adword integer (respectively) operand in memory. 
These symbols designate integers that are used as operands for x87 FPU integer instructions.
•ST or ST(0) — The top element of the FPU register stack.
•ST(i) — The ith element from the top of the FPU register stack ( i := 0 through 7).
•mm — An MMX register. The 64-bit MMX registers are: MM0 through MM7.
•mm/m32 — The low order 32 bits of an MMX register or a 32-bit memory operand. The 64-bit MMX registers 
are: MM0 through MM7. The contents of memory are fo und at the address provided by the effective address 
computation.INSTRUCTION SET REFERENCE, A-L

and GS = 5.
Vol. 2A 3-7•mm/m64 — An MMX register or a 64-bit memory operand. The 64-bit MMX registers are: MM0 through MM7. 
The contents of memory are found at the addre ss provided by the effective address computation.
•xmm — An XMM register. The 128-bit XMM registers ar e: XMM0 through XMM7; XMM8 through XMM15 are 
available using REX.R in 64-bit mode.
•xmm/m32 — An XMM register or a 32-bit memory operand.  The 128-bit XMM registers are XMM0 through 
XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at 
the address provided by the effective address computation.
•xmm/m64 — An XMM register or a 64-bit memory operand. The 128-bit SIMD floating-point registers are 
XMM0 through XMM7; XMM8 through XMM15 are availa ble using REX.R in 64-bit mode. The contents of 
memory are found at the address provided by the effective address computation.
•xmm/m128 — An XMM register or a 128-bit memory operand.  The 128-bit XMM registers are XMM0 through 
XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation.
•<XMM0> — Indicates implied use of the XMM0 register.
When there is ambiguity, xmm1 indicates the first sour ce operand using an XMM register and xmm2 the second 
source operand using an XMM register. 
Some instructions use the XMM0 register as the third source operand, indicated by <XMM0>. The use of the 
third XMM register operand is implicit in the instruct ion encoding and does not affect the ModR/M encoding.
•ymm — A YMM register. The 256-bit YMM registers are: YMM0 through YMM7 ; YMM8 through YMM15 are 
available in 64-bit mode. 
•m256 — A 32-byte operand in memory. This nomencla ture is used only with AVX instructions.
•ymm/m256  — A YMM register or 256-bit memory operand. 
•<YMM0> — Indicates use of the YMM0 register as an implicit argument.
•bnd — A 128-bit bounds register. BND0 through BND3.
•mib — A memory operand using SIB addressing form, where the index register is not used in address calcu-
lation, Scale is ignored. Only the base and displacement are used in effective address calculation.
•m512  — A 64-byte operand in memory. 
•zmm/m512  — A ZMM register or 512-bit memory operand. 
•{k1}{z}  — A mask register used as instruction writemask. The 64-bit k registers are: k1 through k7. 
Writemask specification is available exclusively via EVEX  prefix. The masking can either be done as a merging-
masking, where the old values are preserved for masked out elements or as a zeroing masking. The type of 
masking is determined by using the EVEX.z bit.
•{k1}  — Without {z}: a mask register used as instruction writemask for instructions that do not allow zeroing-
masking but support merging-masking. This corresponds to  instructions that require the value of the aaa field 
to be different than 0 (e.g., gather) and store-ty pe instructions which allow only merging-masking. 
•k1 — A mask register used as a regular operand (either destination or source). The 64-bit k registers are: k0 
through k7.
•mV — A vector memory operand; the operan d size is dependent on the instruction.
•vm32{x,y, z}  — A vector array of memory operands specified using VSIB memory addressing. The array of 
memory addresses are specified using a common base register, a constant scale factor, and a vector index 
register with individual elements of 32-bit index value in an XMM register (vm32x), a YMM register (vm32y) or 
a ZMM register (vm32z).
•vm64{x,y, z}  — A vector array of memory operands specified using VSIB memory addressing. The array of 
register with individual elements of 64-bit index value in an XMM register (vm64x), a YMM register (vm64y) or 
a ZMM register (vm64z).
•zmm/m512/m32bcst  — An operand that can be a ZMM register, a 512-bit memory location or a 512-bit 
vector loaded from a 32-bit memory location. 
•zmm/m512/m64bcst  — An operand that can be a ZMM register, a 512-bit memory location or a 512-bit 
vector loaded from a 64-bit memory location.INSTRUCTION SET REFERENCE, A-L
3-8 Vol. 2A•<ZMM0>  — Indicates use of the ZMM0 register as an implicit argument.
•{er} — Indicates support for embedded rounding control, which is only applicable to the register-register form 
of the instruction. This also implies support for SAE (Suppress All Exceptions).
•{sae}  — Indicates support for SAE (Suppress All Exceptions). This is used for instructions that support SAE, 
but do not support embedded rounding control.
•SRC1 — Denotes the first source operand in the instruct ion syntax of an instruction encoded with the 
VEX/EVEX prefix and having two or more source operands.
•SRC2 — Denotes the second source operand in the instruct ion syntax of an instruction encoded with the 
•SRC3 — Denotes the third source operand in the instruct ion syntax of an instruction encoded with the 
VEX/EVEX prefix and having three source operands.
•SRC — The source in a single-source instruction.
•DST — The destination in an instruction. This field is encoded by reg_field.
In the instruction encoding, the MODRM byte is represen ted several ways depending on the role it plays. The 
MODRM byte has 3 fields: 2-bit MODRM.MOD field, a 3-bit MODRM.REG field and a 3-bit MODRM.RM field. When all 
bits of the MODRM byte have fixed values for an instructio n, the 2-hex nibble value of that byte is presented after 
the opcode in the encoding boxes on the instruction descrip tion pages. When only some fields of the MODRM byte 
•If only the MODRM.MOD must be 0b11, and MODRM.RE G and MODRM.RM fields are unrestricted, this is 
denoted as 11:rrr:bbb . The rrr correspond to the 3-bits of the MODRM.REG field and the bbb correspond to 
the 3-bits of the MODMR.RM field.
•If the MODRM.MOD field is constrained to be a value othe r than 0b11, i.e., it must be one of 0b00, 0b01, or 
0b10, then we use the notation !(11).
•If the MODRM.REG field had a specific required value, e.g., 0b101, that would be denoted as mm:101:bbb. 
3.1.1.4  Operand Encoding Column in the Instruction Summary Table
The “operand encoding” column is abbreviated as Op/En in the Instruction Summary table heading. Instruction 
operand encoding information is provided for each assembly  instruction syntax using a letter to cross reference to 
a row entry in the operand encoding definition table that follows the instruction summary table. The operand encoding table in each instruction reference page lists each instruction operand (according to each instruction 
syntax and operand ordering shown in the instruction colu mn) relative to the ModRM byte, VEX.vvvv field or addi-
tional operand encoding placement. 
EVEX encoded instructions employ compressed disp8*N encodi ng of the displacement bytes, where N is defined in 
Table 2-34 and Table 2-35, according to tupletypes. The tu pletype for an instruction is listed in the operand 
encoding definition table where applicable.
NOTES
•The letters in the Op/En column of an instructio n apply ONLY to the encoding definition table 
immediately following the instruction summary table.
•In the encoding definition table, the letter ‘r’ within a pair of parenthesis denotes the content of the operand will be read by the processor. The le tter ‘w’ within a pair of parenthesis denotes the 
content of the operand will be updated by the processor.
3.1.1.5  64/32-bit Mode Column in the Instruction Summary Table
The “64/32-bit Mode” column indicates whether the opcode  sequence is supported in (a) 64-bit mode or (b) the 
Compatibility mode and other IA-32 modes that apply in conj unction with the CPUID feature flag associated specific 
instruction extensions. 
The 64-bit mode support is to the left of the ‘slash’ and has the following notation:
•V — Supported.
•I — Not supported.INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-9•N.E. — Indicates an instruction syntax is not encodable in 64-bit mode (it may represent part of a sequence of 
valid instructions in other modes).
•N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bit mode.
•N.I. — Indicates the opcode is treated as a new instruction in 64-bit mode.
•N.S. — Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not 
supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior.
The Compatibility/Legacy Mode support is to the ri ght of the ‘slash’ and has the following notation:
• V — Supported.
• I — Not supported.
• N.E. —  Indicates an Intel 64 instruction mnemonics/syntax that is not encodable; the opcode sequence is not
applicable as an individual instruction in compatibi lity mode or IA-32 mode. The opcode may represent a valid
sequence of legacy IA-32 instructions.
3.1.1.6  CPUID Support Column in  the Instruction Summary Table

The fourth column holds abbreviated CPUID featur e flags (e.g., appropriate bit in CPUID.01H.ECX,
CPUID.01H.EDX for SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4 .2/AESNI/PCLMULQDQ/AVX/RDRAND support) that
indicate processor support for the instruction. If the corresponding flag is ‘0’,  the instruction will #UD.
3.1.1.7  Description Column in the Instruction Summary Table
The “Description” column briefly explains forms of the instruction. 
3.1.1.8  Description Section 
Each instruction is then described by number of info rmation sections. The “Description” section describes the 
purpose of the instructions and required operands in more detail.
Summary of terms that may be used in the description section:
•Legacy SSE  — Refers to SSE, SSE2, SSE3, SSSE3, SSE4, AESNI, PCLMULQDQ, and any future instruction sets 
referencing XMM registers and encoded without a VEX prefix.
•VEX.vvvv  — The VEX bit field specifying a source or destination register (in 1’s complement form).
•rm_field  — shorthand for the ModR/M r/m field and any REX.B
•reg_field  — shorthand for the ModR/M reg field and any REX.R
3.1.1.9  Operation Section
The “Operation” section contains an algorithm description (frequently written in pseudo-code) for the instruction. 
Algorithms are composed of the following elements:
•Comments are enclosed within the symbol pairs “(*” and “*)”. 
•Compound statements are enclosed in keywords, such as : IF, THEN, ELSE, and FI for an if statement; DO and 
OD for a do statement; or CASE... OF for a case statement.
•A register name implies the contents of the register. A re gister name enclosed in brackets implies the contents 
of the location whose address is contained in that regi ster. For example, ES:[DI] indicates the contents of the 
location whose ES segment relative address is in register DI. [SI] indicates the contents of the address contained in register SI relative to the SI regist er’s default segment (DS) or the overridden segment.
•Parentheses around the “E” in a general-purpose register na me, such as (E)SI, indicates that the offset is read 
from the SI register if the address-size attribute is 16, from the ESI register if the address-size attribute is 32. 
Parentheses around the “R” in a general-purpose register  name, (R)SI, in the presence of a 64-bit register 
definition such as (R)SI, indicates that the offset is read from the 64-bit RSI register if the address-size 
attribute is 64.INSTRUCTION SET REFERENCE, A-L
3-10 Vol. 2A•Brackets are used for memory operands where they me an that the contents of the memory location is a 
segment-relative offset. For example, [SRC] indicates that the content of the source operand is a segment-
relative offset.
•A := B indicates that the value of B is assigned to A.
•The symbols =, ≠, >, <, ≥, and ≤ are relational operators used to compare two values: meaning equal, not 
equal, greater or equal, less or equal, resp ectively. A relational expression such as A  = B is TRUE if the value of 
A is equal to B; otherwise it is FALSE.
•The expression “« COUNT” and “» COUNT” indicates that the destination operand should  be shifted left or right 
by the number of bits indicated by the count operand.
The following identifiers are used in the algorithmic descriptions:
•OperandSize and AddressSize — The OperandSize identifier represents  the operand-size attribute of the 
instruction, which is 16, 32 or 64-bits. The AddressSize identifier represents the address-size attribute, which 
is 16, 32 or 64-bits. For example, the following pseudo -code indicates that the operand-size attribute depends 
on the form of the MOV instruction used.
IF Instruction = MOVW
THEN OperandSize := 16;
ELSE
IF Instruction = MOVD
THEN OperandSize := 32;
ELSE
IF Instruction = MOVQ
THEN OperandSize := 64; 
FI;
FI;
FI;
See “Operand-Size and Address-Size A ttributes” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1, for guidelines on how these attributes are determined.
•StackAddrSize — Represents the stack address-size attribute associated with the instruction, which has a 
value of 16, 32 or 64-bits. See “Addres s-Size Attribute for Stack” in Chapter 6, “Procedure Calls, Interrupts, and 
Exceptions,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
•SRC — Represents the source operand.
•DEST — Represents the destination operand.
•MAXVL — The maximum vector register width pertaining to the instruction. This is not the vector-length 
encoding in the instruction's encoding but is instead de termined by the current value of XCR0. For details, refer 
to the table below. Note that the value of MAXVL is the largest of the features enabled. Future processors may 
define new bits in XCR0 whose setti ng may imply other values for MAXVL.
MAXVL Definition
The following functions are used in the algorithmic descriptions:
•ZeroExtend(value) — Returns a value zero-extended to the operand-size attribute of the instruction. For 
example, if the operand-size attribute is 32, zero extend ing a byte value of –10 converts the byte from F6H to 
a doubleword value of 000000F6H. If the value passed to the ZeroExtend function and the operand-size 
attribute are the same size, ZeroExtend returns the value unaltered.
•SignExtend(value) — Returns a value sign-extended to the operand-size attribute of the instruction. For 
example, if the operand-size attribute is 32, sign exte nding a byte containing the value –10 converts the byte XCR0 Component MAXVL
XCR0.SSE 128
XCR0.AVX 256
XCR0.{ZMM_Hi256, Hi16_ZMM, OPMASK} 512INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-11from F6H to a doubleword value of FFFFFFF6H. If the valu e passed to the SignExtend function and the operand-
size attribute are the same size, SignExtend returns the value unaltered.
•SaturateSignedWo rdToSignedByte — Converts a signed 16-bit value to a signed 8-bit value. If the signed 
16-bit value is less than –128, it is represented by the saturated value -128 (80H); if it is greater than 127, it 
is represented by the sa turated value 127 (7FH).
•SaturateSignedDw ordToSignedWord — Converts a signed 32-bit value to a signed 16-bit value. If the 
signed 32-bit value is less than –32768, it is repr esented by the saturated value –32768 (8000H); if it is 
greater than 32767, it is represented by the saturated value 32767 (7FFFH).
•SaturateSignedWord ToUnsignedByte — Converts a signed 16-bit value to  an unsigned 8-bit value. If the 
signed 16-bit value is less than zero, it is represented by the saturated value zero ( 00H); if it is greater than 
255, it is represented by the saturated value 255 (FFH).
•SaturateToSignedByte — Represents the result of an operation as a signed 8-bit value. If the result is less 
than –128, it is represented by the saturated value –128 (80H); if it is greater than 127, it is represented by 
the saturated value 127 (7FH).
•SaturateToSignedWord — Represents the result of an operation as a signed 16-bit value. If the result is less 
than –32768, it is represented by the saturated valu e –32768 (8000H); if it is greater than 32767, it is 
represented by the saturated value 32767 (7FFFH).
•SaturateToUnsignedByte — Represents the result of an operation as a signed 8-bit value. If the result is less 
than zero it is represented by the saturated value zero (0 0H); if it is greater than 255, it is represented by the 
saturated value 255 (FFH).
•SaturateToUnsignedWord — Represents the result of an operation as a signed 16-bit value. If the result is 
less than zero it is represented by the saturated value ze ro (00H); if it is greater than 65535, it is represented 
by the saturated value 65535 (FFFFH).
•LowOrderWord(DEST * SRC)  — Multiplies a word operand by a word operand and stores the least significant 
word of the doubleword result in the destination operand.
•HighOrderWord(DEST * SRC)  — Multiplies a word operand by a word operand and stores the most 
significant word of the doubleword result in the destination operand.
•Push(value) — Pushes a value onto the stack. The number of by tes pushed is determined by the operand-size 
attribute of the instruction. See the “Operation” su bsection of the “PUSH—Push Word, Doubleword, or 
Quadword Onto the Stack” section in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2B.
•Pop()  — removes the value from the top of the stack and returns it. The statement EAX := Pop(); assigns to 
EAX the 32-bit value from the top of the stack. Pop wi ll return either a word, a doubleword or a quadword 
depending on the operand-size attribute. See the “Ope ration” subsection in the “POP—Pop a Value From the 
Stack” section of Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
•PopRegisterStack — Marks the FPU ST(0) register as empty and increments the FPU register stack pointer 
(TOP) by 1.
•Switch-Tasks — Performs a task switch.
•Bit(BitBase, BitOffset) — Returns the value of a bit within a bit string. The bit string is a sequence of bits in

(TOP) by 1.
•Bit(BitBase, BitOffset) — Returns the value of a bit within a bit string. The bit string is a sequence of bits in 
memory or a register. Bits are numbered from low-orde r to high-order within registers and within memory 
bytes. If the BitBase is a register, the BitOffset can be  in the range 0 to [15, 31, 63] depending on the mode 
and register size. See Figure 3-1: the function Bit[RAX, 21] is illustrated.
Figure 3-1.  Bit Offs et for BIT[RAX, 21]0 21 31
Bit Offset := 2163INSTRUCTION SET REFERENCE, A-L
3-12 Vol. 2AIf BitBase is a memory address, the BitOffset has diff erent ranges depending on the operand size (see Table 
3-2). 
The addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)) where 
DIV is signed division with rounding towards negati ve infinity and MOD returns a positive number (see 
Figure 3-2).
3.1.1.10  Intel ® C/C++ Compiler Intrinsics Equivalents Section
The Intel C/C ++ compiler intrinsic functions give access to the full power of the Intel Architecture Instruction Set, 
while allowing the compiler to optimize register allocation and instruction scheduling for faster execution. Most of these functions are associated with a single IA instructio n, although some may generate multiple instructions or 
different instructions depending upon how they are used. In particular, these functions are used to invoke instruc-
tions that perform operations on vector registers that can hold multiple data elements. These SIMD instructions 
use the following data types.
•__m128, __m256, and __m512 can represent 4, 8, or 16 pa cked single precision floating-point values, and are 
used with the vector registers and SSE, AVX, or AVX-512 instruction set extension families. The __m128 data type is also used with various single precision floating-point scalar instructions that perform calculations using 
only the lowest 32 bits of a vector register; the remaining bits of the result come from one of the sources or are 
set to zero depending upon the instruction.
•__m128d, __m256d, and __m512d can represent 2, 4, or 8 packed double precision floating-point values, and 
are used with the vector registers and SSE, AVX, or AVX-512 instruction set extension families. The __m128d 
data type is also used with various double precision fl oating-point scalar instructions that perform calculations 
using only the lowest 64 bits of a vector register; the re maining bits of the result come from one of the sources 
or are set to zero depending upon the instruction.
•__m128i, __m256i, and __m512i can represent integer data  in bytes, words, doub lewords, quadwords, and 
occasionally larger data types.Table 3-2.  Range of Bit Position s Specified by Bit Offset Operands
Operand Size Immediate Bi tOffset Register BitOffset
16 0 to 15 − 215 to 215 − 1 
32 0 to 31 − 231 to 231 − 1 
64 0 to 63 − 263 to 263 − 1 
Figure 3-2.  Memory Bit IndexingBitBase + 1 0 7 7 75 0 0
BitBase − 2 0 7 7 75 00BitBase BitBase − 1 
BitOffset := +13
BitBase − 1 BitBase
BitOffset := −11INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-13Each of these data types incorporates in its name the nu mber of bits it can hold. For example, the __m128 type 
holds 128 bits, and because each single precision floati ng-point value is 32 bits long the __m128 type holds 
(128/32) or four values. Normally the compiler will allocate  memory for these data types on an even multiple of the 
size of the type. Such aligned memory locations may be faster to read and write than locations at other addresses.
These SIMD data types are not basic Standard C data types or C ++ objects, so they may be used only with the 
assignment operator, passed as function arguments, and re turned from a function call. If you access the internal 
members of these types directly, or indirectly by using them in a union, there may be side effects affecting optimi-zation, so it is recommended to use them only with the SI MD instruction intrinsic functions described in this manual 
or the Intel C/C ++ compiler documentation.
Many intrinsic functions names are prefixed with an indicator of the vector length and suffixed by an indicator of 
the vector element data type, although some functions do not follow the rules below. The prefixes are:
•_mm_ indicates that the function operates on 128-bit (or sometimes 64-bit) vectors.
•_mm256_ indicates the function operates on 256-bit vectors.
•_mm512_ indicates that the function operates on 512-bit vectors.
The suffixes include:
•_ps, which indicates a function that operates on packed  single precision floating-point data. Packed single 
precision floating-point data corresponds to arrays of the C/C ++ type float with either 4, 8 or 16 elements. 
Values of this type can be loaded from an array using the _mm_loadu_ps, _mm256_loadu_ps,  or 
_mm512_loadu_ps  functions, or created from individual values using _mm_set_ps, _mm256_set_ps, or 
_mm512_set_ps  functions, and they can be stored in an array using _mm_storeu_ps, _mm256_storeu_ps,  or 
_mm512_storeu_ps .
•_ss, which indicates a function that operates on scalar single precision floating-point data. Single precision 
floating-point data corresponds to the C/C ++ type float, and values of type float can be converted to type 
__m128 for use with these functions using the  _mm_set_ss  function, and converted back using the 
_mm_cvtss_f32  function. When used with functions that operate on packed single precision floating-point data 
the scalar element corresponds with the first packed value.
•_pd, which indicates a function that operates on packed  double precision floating-point data. Packed double 
precision floating-point data corresponds to arrays of the C/C ++ type double with either 2, 4, or 8 elements. 
Values of this type can be loaded from an array using the _mm_loadu_pd, _mm256_loadu_pd,  or 
_mm512_loadu_pd  functions, or created from individual values using _mm_set_pd, _mm2566_set_pd,  or 
_mm512_set_pd  functions, and they can be stored in an array using _mm_storeu_pd, _mm256_storeu_pd, or 
_mm512_storeu_pd .
•_sd, which indicates a function that operates on scalar double precision floating-point data. Double-precision 
floating-point data corresponds to the C/C ++ type double , and values of type double can be converted to type 
__m128d for use with these functions using the _mm_set_sd  function, and converted back using the 
_mm_cvtsd_f64  function. When used with functions that operate on packed double precision floating-point 
data the scalar element corresponds with the first packed value.
•_epi8, which indicates a function that operates on pa cked 8-bit signed integer values. Packed 8-bit signed 
integers correspond to an array of signed char  with 16, 32 or 64 elements. Values of this type can be created 
from individual elements using _mm_set_epi8, _mm256_set_epi8,  or _mm512_set_epi8  functions.
•_epi16, which indicates a function that operates on packed 16-bit signed integer values. Packed 16-bit signed 
integers correspond to an array of short with 8, 16 or 32 elements. Values of this type can be created from 
individual elements using _mm_set_epi16, _mm256_set_epi16,  or _mm512_set_epi16  functions.
•_epi32, which indicates a function that operates on packed 32-bit signed integer values. Packed 32-bit signed 
integers correspond to an array of int with 4, 8 or 16 elements. Values of this type can be created from 
individual elements using _mm_set_epi32, _mm256_set_epi32,  or _mm512_set_epi32  functions.
•_epi64, which indicates a function that operates on packed 64-bit signed integer values. Packed 64-bit signed 
integers correspond to an array of  long long  (or long if it is a 64-bit data type) with 2, 4 or 8 elements. Values 
of this type can be created from individual elements using _mm_set_epi32, _mm256_set_epi32,  or 
_mm512_set_epi32  functions.
•_epu8, which indicates a function that operates on pa cked 8-bit unsigned integer values. Packed 8-bit unsigned 
integers correspond to an array of unsigned char  with 16, 32 or 64 elements.INSTRUCTION SET REFERENCE, A-L
3-14 Vol. 2A•_epu16, which indicates a function that operates on  packed 16-bit unsigned integer values. Packed 16-bit 
unsigned integers correspond to an array of unsigned short  with 8, 16 or 32 elements.
•_epu32, which indicates a function that operates on  packed 32-bit unsigned integer values. Packed 32-bit 
unsigned integers correspond to an array of unsigned  with 4, 8 or 16 elements.
•_epu64, which indicates a function that operates on  packed 64-bit unsigned integer values. Packed 64-bit 
unsigned integers correspond to an array of unsigned long long  (or unsigned long  if it is a 64-bit data type) with 
2, 4 or 8 elements.
•_si128, which indicates a function that operates  on a single 128-bit value of type __m128i.
•_si256, which indicates a function that operates on a single a 256-bit value of type __m256i.
•_si512, which indicates a function that operates on a single a 512-bit value of type __m512i.
Values of any packed integer type ca n be loaded from an array using the _mm_loadu_si128,

Values of any packed integer type ca n be loaded from an array using the _mm_loadu_si128, 
_mm256_loadu_si256, or _mm512_loadu_si512 functions, and they can be stored in an array using 
_mm_storeu_si128, _mm256_storeu_si256, or _mm512_storeu_si512 .
These functions and data types are used with the SSE, AVX, and AVX-512 instruction set extension families. In 
addition there are similar functions that correspond to MMX instructions. These are less frequently used because 
they require additional state management, and on ly operate on 64-bit packed integer values.
The declarations of Intel C/C ++ compiler intrinsic functions may reference some non-standard data types, such as 
__int64. The C Standard header stdint.h  defines similar platform-independent  types, and the documentation for 
that header gives characteristics that apply to corresponding non-standard types according to the following table. 
For a more detailed description of each intrinsic function an d additional information relate d to its usage, refer to the 
online Intel Intrinsics Guide, https://software.intel.com/sites/landingpage/IntrinsicsGuide .
3.1.1.11  Flags Affected Section 
The “Flags Affected” section lists the flags in the EFLAGS re gister that are affected by the instruction. When a flag 
is cleared, it is equal to 0; when it is set, it is equal to  1. The arithmetic and logical instructions usually assign values 
to the status flags in a uniform manner (see Appe ndix A, “EFLAGS Cross-Reference,” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 1). Non-conventional assignments are described in the “Oper-ation” section. The values of flags listed as undefined  may be changed by the instruction in an indeterminate 
manner. Flags that are not listed are unchanged by the instruction.
3.1.1.12  FPU Flags Affected Section 
The floating-point instructions have an “FPU Flags Affected” section that describes how each instruction can affect 
the four condition code flags of the FPU status word.
3.1.1.13  Protected Mo de Exceptions Section
The “Protected Mode Exceptions” section lists the exceptio ns that can occur when the instruction is executed in 
protected mode and the reasons for the exceptions. Each ex ception is given a mnemonic that consists of a pound Table 3-3.  Standard and Non-Standard Data Types
Non-standard Type Standard Type (from stdint.h)
__int64 int64_t
unsigned __int64 uint64_t__int32 int32_t
unsigned __int32 uint32_t
__int16 int16_tunsigned __int16 uint16_tINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-15sign (#) followed by two letters and an optional error code  in parentheses. For example, #GP(0) denotes a general 
protection exception with an error code of 0. Table 3-4 associates each two-letter mnemonic with the corre-
sponding exception vector and name. See Chapter 6, “Procedure Calls, Interrupts, and Exceptions,” in the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Vo lume 3A, for a detailed description of the exceptions. 
Application programmers should consult the documentatio n provided with their operating systems to determine 
the actions taken when exceptions occur.
3.1.1.14  Real-Address Mo de Exceptions Section
The “Real-Address Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in 
real-address mode (see Table 3-4).
3.1.1.15  Virtual-8086 Mo de Exceptions Section
The “Virtual-8086 Mode Exceptions” section lists the exceptio ns that can occur when the instruction is executed in 
virtual-8086 mode (see Table 3-4).Table 3-4.  Intel 64 and IA-32 General Exceptions 
Vector Name Source Protected 
Mode1Real Address 
ModeVirtual 
8086 
Mode
 0# D E — D i v i d e  E r r o r D I V  a n d  IDIV instructions. Yes Yes Yes
 1 #DB—Debug Any code or data reference. Yes Yes Yes
 3 #BP—Breakpoint INT3 instruction. Yes Yes Yes
 4 #OF—Overflow INTO instruction. Yes Yes Yes 5 #BR—BOUND Range Exceeded BOUND instruction. Yes Yes Yes 6 #UD—Invalid Opcode (Undefined 
Opcode)UD instruction or reserved opcode. Yes Yes Yes
 7 #NM—Device Not Available (No 
Math Coprocessor)Floating-point or WAIT/FWA IT instruction. Yes Yes Yes
 8 #DF—Double Fault Any instruction that can generate an 
exception, an NMI, or an INTR.Yes Yes Yes
10 #TS—Invalid TSS Task switch or TSS access. Yes Reserved Yes
11 #NP—Segment Not Present Loading segm ent registers or accessing system 
segments.Yes Reserved Yes
12 #SS—Stack Segment Fault Stack operations and SS register loads. Yes Yes Yes
13 #GP—General Protection
2Any memory reference and other protection 
checks.Yes Yes Yes
14 #PF—Page Fault Any memory reference. Yes Reserved Yes
16 #MF—Floating-Point Error (Math 
Fault)Floating-point or WAIT/FWA IT instruction. Yes Yes Yes
17 #AC—Alignment Check Any data reference in memory. Yes Reserved Yes
18 #MC—Machine Check Model dependent machine check errors. Yes Yes Yes
19 #XM—SIMD Floating-Point 
Numeric ErrorSSE/SSE2/SSE3 floating-point instructions. Yes Yes Yes
NOTES:
1. Apply to protected mode, compatibility mode, and 64-bit mode.
2. In the real-address mode, vector 13 is the segment overrun exception.INSTRUCTION SET REFERENCE, A-L
3-16 Vol. 2A3.1.1.16  Floating-Point Exceptions Section
The “Floating-Point Exceptions” section lists exceptions that can occur when an x87 FPU floating-point instruction 
is executed. All of these exception conditions result in a floating-point error exception (#MF, exception 16) being 
generated. Table 3-5 associates a one- or two-letter mnemonic with the corresponding exception name. See 
“Floating-Point Exception Conditions” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, for a detailed description of these exceptions.
3.1.1.17  SIMD Floating-Point Exceptions Section
The “SIMD Floating-Point Exceptions” section lists exceptions that can occur when an SSE/SSE2/SSE3 floating-
point instruction is executed. All of these exception conditio ns result in a SIMD floating-point error exception (#XM, 
exception 19) being generated. Table 3-6 associates a one-letter mnemonic with the corresponding exception 
name. For a detailed description of these exceptions, refe r to ”SSE and SSE2 Exceptions”, in Chapter 11 of the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
3.1.1.18  Compatibility Mode Exceptions Section
This section lists exceptions that occur within compatibility mode.
3.1.1.19  64-Bit Mode  Exceptions Section
This section lists exceptions that occur within 64-bit mode.
3.2 INTEL® AMX CONSIDERATIONS
The following implementation parameters and he lper functions are applicable to the Intel® AMX instructions.Table 3-5.  x87 FPU Floating-Point Exceptions
Mnemonic Name Source
#IS
#IAFloating-point invalid operation:
- Stack overflow or underflow- Invalid arithmetic operation- x87 FPU stack overflow or underflow
- Invalid FPU arithmetic operation
#Z Floating-point divide -by-zero Divide-by-zero
#D Floating-point denormal operand Source operand that is a denormal number
#O Floating-point numeric overflow Overflow in result
#U Floating-point numeric underflow Underflow in result
#P Floating-point inexact result (precision) Inexact result (precision)
Table 3-6.  SIMD Floating-Point Exceptions
#I Floating-point invalid operation Invalid arithmetic operation or source operand
#Z Floating-point divide-by-zero Divide-by-zero
#P Floating-point inexact result Inexact result (precision)INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-173.2.1 Implementation Parameters
The parameters are reported via CPUID leaf 1D H. Index 0 reports all zeros for all fields.
3.2.2 Helper Functions
uint16_t total_tile_bytes uint16_t bytes_per_tile uint16_t bytes_per_row uint16_t max_names uint16_t max_rows
byte rowsword colsb // bytes_per_row bool valid
TILEDATA.byte[j] := 0INSTRUCTION SET REFERENCE, A-L
3-18 Vol. 2A3.3 INSTRUCTIONS (A-L)
The remainder of this chapter provides descriptions of Inte l 64 and IA-32 instructions (A-L). See also: Chapter 4, 
“Instruction Set Reference, M-U,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2B; Chapter 5, “Instruction Se t Reference, V,” in the Intel® 64 and IA-32 Architectures Software Developer’s

2B; Chapter 5, “Instruction Se t Reference, V,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2C; and Chapter 6, “Instruc tion Set Reference, W-Z,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 2D.define xcr0_supports_palette(palette_id): 
return 1
return 1
return 0AAA—ASCII Adjust After AdditionINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-19AAA—ASCII Adjust After Addition
Instruction Operand Encoding
Adjusts the sum of two unpacked BCD values to create an  unpacked BCD result. The AL register is the implied 
source and destination operand for this instruction. The AAA instruction is only usef ul when it follows an ADD 
instruction that adds (binary addition) two unpacked BCD va lues and stores a byte result in the AL register. The 
AAA instruction then adjusts the conten ts of the AL register to contain the correct 1-digit unpacked BCD result. 
If the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there 
was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4 
through 7 of the AL register are set to 0.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
IF ((AL AND 0FH) > 9) or (AF = 1)
THEN
AX := AX + 106H;
AF := 1;CF := 1;
ELSE
AF := 0;CF := 0;
FI;
AL := AL AND 0FH;
FI;
Flags Affected
The AF and CF flags are set to 1 if the adjustment result s in a decimal carry; otherwise they are set to 0. The OF, 
SF, ZF, and PF flags are undefined.
Protected Mode Exceptions
#UD If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.Opcode Instruction Op/ 
En64-bit 
ModeCompat/
Leg ModeDescription
37 AAA ZO Invalid Valid ASCII adjust AL after addition.
ZO N/A N/A N/A N/AAAA—ASCII Adjust After AdditionINSTRUCTION SET REFERENCE, A-L
3-20 Vol. 2ACompatibility Mode Exceptions
64-Bit Mode Exceptions
#UD If in 64-bit mode.AAD—ASCII Adjust AX Before DivisionINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-21AAD—ASCII Adjust AX Before Division
Adjusts two unpacked BCD digits (the leas t-significant digit in the AL register and the most-significant digit in the 
AH register) so that a division operation performed on th e result will yield a correct unpacked BCD value. The AAD 
instruction is only useful when it precedes a DIV instruct ion that divides (binary division) the adjusted value in the 
AX register by an unpacked BCD value.
The AAD instruction sets the valu e in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H. 
The value in the AX register is then equal to the binary  equivalent of the original unpacked two-digit (base 10) 
number in registers AH and AL.
The generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the 
“Operation” section below), by setting the imm8  byte to the selected number base (for example, 08H for octal, 0AH 
for decimal, or 0CH for base 12 numbers). The AAD mnemon ic is interpreted by all assemblers to mean adjust 
ASCII (base 10) values. To adjust values in another numb er base, the instruction must be hand coded in machine 
code (D5 imm8 ).
Operation
THEN
#UD;
ELSE
tempAL := AL;
tempAH := AH;AL := (tempAL + (tempAH ∗ imm8 )) AND FFH; 
(* imm8  is set to 0AH for the AAD mnemonic.*)
AH := 0;
FI;The immediate value ( imm8 ) is taken from the second  byte of the instruction.
The SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags 
are undefined.
En64-bit 
D5 0A AAD ZO Invalid Valid ASCII adjust AX before division.
D5 ib AAD imm8 ZO Invalid Valid Adjust AX  before division to number base 
imm8.
ZO N/A N/A N/A N/AAAD—ASCII Adjust AX Before DivisionINSTRUCTION SET REFERENCE, A-L
3-22 Vol. 2ACompatibility Mode Exceptions
#UD If in 64-bit mode.AAM—ASCII Adjust AX After MultiplyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-23AAM—ASCII Adjust AX After Multiply
Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD 
values. The AX register is the implied source and destination operand for this instruction. The AAM instruction is 
only useful when it follows an MUL instruction that mu ltiplies (binary multiplication)  two unpacked BCD values and 
stores a word result in the AX register. The AAM instructio n then adjusts the contents of the AX register to contain 
the correct 2-digit unpacked (base 10) BCD result. 
The generalized version of this instruction allows adjust ment of the contents of the AX to create two unpacked 
digits of any number base (see the “Operation” section below). Here, the imm8  byte is set to the selected number 
base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted 
by all assemblers to mean adjust to ASCII (base 10) va lues. To adjust to values in another number base, the 
instruction must be hand coded in machine code (D4 imm8 ).
Operation
THEN
#UD;
ELSE
AH := tempAL / imm8 ; (* imm8  is set to 0AH for the AAM mnemonic *)
AL := tempAL MOD imm8 ;
FI;
The immediate value ( imm8 ) is taken from the second byte of the instruction.
The SF, ZF, and PF flags are set according to the resulting binary value in the AL register. The OF, AF, and CF flags 
#DE If an immediate value of 0 is used.
En64-bit 
D4 0A AAM ZO Invalid Valid ASCII adjust AX after multiply.
D4 ib AAM imm8 ZO Invalid Valid Adjust AX after multiply to number base 
imm8.
ZO N/A N/A N/A N/AAAM—ASCII Adjust AX After MultiplyINSTRUCTION SET REFERENCE, A-L
3-24 Vol. 2ACompatibility Mode Exceptions
#UD If in 64-bit mode.AAS—ASCII Adjust AL After SubtractionINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-25AAS—ASCII Adjust AL After Subtraction
Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register 
is the implied source and destination operand for this instru ction. The AAS instruction is on ly useful when it follows 
a SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte 
result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-
digit unpacked BCD result. 
If the subtraction produced a decimal carry, the AH register decrements by 1, and the CF and AF flags are set. If no 
decimal carry occurred, the CF and AF flags are cleared, an d the AH register is unchange d. In either case, the AL 
register is left with its top four bits set to 0.
Operation
IF 64-bit mode
THEN
#UD;
ELSE
THEN
AX := AX – 6;AH := AH – 1;AF := 1;CF := 1;AL := AL AND 0FH;
ELSE
CF := 0;AF := 0;AL := AL AND 0FH;
FI;
FI;
The AF and CF flags are set to 1 if there is a decimal borro w; otherwise, they are cleared to 0. The OF, SF, ZF, and 
PF flags are undefined.
En64-bit 
3F AAS ZO Invalid Valid ASCII adjust AL after subtraction.
ZO N/A N/A N/A N/AAAS—ASCII Adjust AL After SubtractionINSTRUCTION SET REFERENCE, A-L
3-26 Vol. 2ACompatibility Mode Exceptions
#UD If in 64-bit mode.ADC—Add With CarryINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-27ADC—Add With Carry

#UD;
ELSE
THEN
ELSE
FI;
FI;
En64-bit 
Adds the destination operand (first operand), the source  operand (second operand), and the carry (CF) flag and 
stores the result in the destination operand. The destinat ion operand can be a register or a memory location; the 
source operand can be an immediate, a register, or a memory location. (How ever, two memory operands cannot be 
used in one instruction.) The state of the CF flag repres ents a carry from a previous addition. When an immediate 
value is used as an operand, it is sign-extende d to the length of the destination operand format.Opcode Instruction Op/ 
En64-bit 
14 ib ADC AL, imm8 I Valid Valid Add with carry imm8 to AL.
15 iw ADC AX, imm16 I Valid Valid Add with carry imm16 to AX.15 id ADC EAX, imm32 I Valid Valid Add with carry imm32 to EAX.
REX.W + 15 id ADC RAX, imm32 I Valid N.E. Add  with carry imm32 si gn extended to 64-
bits to RAX.
80 /2 ib ADC r/m8, imm8 MI Valid Valid Add with carry imm8 to r/m8.REX + 80 /2 ib ADC r/m8
*, imm8 MI Valid N.E. Add with carry imm8 to r/m8.
81 /2 iw ADC r/m16, imm16 MI Valid Va lid Add with carry imm16 to r/m16.
81 /2 id ADC r/m32, imm32 MI Valid Valid Add with CF imm32 to r/m32.REX.W + 81 /2 id ADC r/m64, imm32 MI Valid N.E. Ad d with CF imm32 sign extended to 64-bits 
to r/m64.
83 /2 ib ADC r/m16, imm8 MI Valid Valid Add with CF sign-extended imm8 to r/m16.
83 /2 ib ADC r/m32, imm8 MI Valid Valid Add with CF sign-extended imm8 into r/m32.
REX.W + 83 /2 ib ADC r/m64, imm8 MI Valid N.E. A dd with CF sign-extended imm8 into r/m64.
10 /r ADC r/m8, r8 MR Valid Valid Add with carry byte register to r/m8.REX + 10 /r ADC r/m8
*, r8*MR Valid N.E. Add with carry byte register to r/m64.
11 /r ADC r/m16, r16 MR Valid Valid Add with carry r16 to r/m16.11 /r ADC r/m32, r32 MR Valid Valid Add with CF r32 to r/m32.REX.W + 11 /r ADC r/m64, r64 MR Valid N.E. Add with CF r64 to r/m64.12 /r ADC r8, r/m8 RM Valid Valid Add with carry r/m8 to byte register.REX + 12 /r ADC r8
*, r/m8*RM Valid N.E. Add with carry r/m64 to byte register.
13 /r ADC r16, r/m16 RM Valid Valid Add with carry r/m16 to r16.13 /r ADC r32, r/m32 RM Valid Valid Add with CF r/m32 to r32.REX.W + 13 /r ADC r64, r/m64 RM Valid N.E. Add with CF r/m64 to r64.NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.
RM ModRM:reg (r, w) ModRM:r/m (r) N/A N/A
MR ModRM:r/m (r, w) ModRM:reg (r) N/A N/A
MI ModRM:r/m (r, w) imm8/16/32 N/A N/A
I AL/AX/EAX/RAX imm8/16/32 N/A N/AADC—Add With CarryINSTRUCTION SET REFERENCE, A-L
3-28 Vol. 2AThe ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates 
the result for both data types and sets  the OF and CF flags to indicate a carry in the signed or unsigned result, 
respectively. The SF flag indicates the sign of the signed result.
The ADC instruction is usually executed as part of a multib yte or multiword addition in which an ADD instruction is 
followed by an ADC instruction.
This instruction can be used with a LOCK prefix to  allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is  32 bits. Using a REX prefix in  the form of REX.R permits 
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See 
the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST := DEST + SRC + CF;
Intel C/C ++ Compiler Intrinsic Equivalent
ADC extern unsigned char _addcarry_u8(unsi gned char c_in, unsigned ch ar src1, unsigned char src2 , unsigned char *sum_out);
ADC extern unsigned char _addcarry_u16(uns igned char c_in, unsigned sh ort src1, unsigned short src2 , unsigned short *sum_out);
ADC extern unsigned char _addcarry_u32(uns igned char c_in, unsigned int src1, unsigned char int, unsigned int *sum_out);
ADC extern unsigned char _addcarry_u64(uns igned char c_in, unsigned __int64 src1, unsigned __in t64 src2, unsigned __int64 
*sum_out);
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
#GP(0) If the destination is located in a non-writable segment.
If a memory operand effective address is outs ide the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment 
selector.
#SS(0) If a memory operand effective ad dress is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the 
current privilege level is 3.
#UD If the LOCK prefix is used but the destination is not a memory operand.
#GP If a memory operand effective address is ou tside the CS, DS, ES, FS, or GS segment limit.
#SS If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled an d an unaligned memory reference is made.
Compatibility Mode Exceptions
Same exceptions as in protected mode.ADC—Add With CarryINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-2964-Bit Mode Exceptions
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
#GP(0) If the memory address is in a non-canonical form.#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the 
#UD If the LOCK prefix is used but th e destination is not a memory operand.ADCX—Unsigned Integer Addition of Two Operands With Carry FlagINSTRUCTION SET REFERENCE, A-L
3-30 Vol. 2AADCX—Unsigned Integer Addition of Two Operands With Carry Flag 
Performs an unsigned addition of the destination operand (first operand), the source operand (second operand) 
and the carry-flag (CF) and stores the result in the de stination operand. The destination operand is a general-
purpose register, whereas the source operand can be a general-purpose register or memory location. The state of 
CF can represent a carry from a previous addition. The inst ruction sets the CF flag with the carry generated by the 
unsigned addition of the operands. 
The ADCX instruction is executed in the context of multi-pr ecision addition, where we add a series of operands with 
a carry-chain. At the beginning of a chain of additions, we need to make sure the CF is in a desired initial state. 
Often, this initial state needs to be 0, which can be ac hieved with an instruction to zero the CF (e.g. XOR).
This instruction is supported in real mode and virtual-8086 mo de. The operand size is always 32 bits if not in 64-bit 
mode. 
In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of RE X.R permits access to addi-
tional registers (R8-15). Using REX Prefix in th e form of REX.W promotes operation to 64 bits.
ADCX executes normally either inside or outside a transaction region.Note: ADCX defines the OF flag differently than the ADD/ADC instructions as defined in the Intel
Architectures Software Developer’s Manual, Volume 2A.
Operation
IF OperandSize is 64-bit
THEN CF:DEST[63:0] := DE ST[63:0] + SRC[63:0] + CF;
ELSE CF:DEST[31:0] := DEST[31:0] + SRC[31:0] + CF;
FI;
CF is updated based on result. OF, SF, ZF, AF, and PF flags are unmodified.
Intel C/C++ Compiler Intrinsic Equivalent
unsigned char _addcarryx_u32 (unsigned char c_in, unsigned  int src1, unsigned int sr c2, unsigned int *sum_out);
unsigned char _addcarryx_u64 (u nsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
SIMD Floating-Point Exceptions
None.Opcode/
InstructionOp/ 
En64/32bit 
Mode SupportCPUID 
66 0F 38 F6 /r
ADCX r32, r/m32RM V/V ADX Unsigned addition of r32 with CF, r/m32 to r32, writes CF.
66 REX.w 0F 38 F6 /r
ADCX r64, r/m64RM V/N.E. ADX Unsigned addition of r64 with CF, r/m64 to r64, writes CF.
RM ModRM:reg (r, w) ModRM:r/m (r) N/A N/AADCX—Unsigned Integer Addition of  Two Operands With Carry FlagINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-31Protected Mode Exceptions
If CPUID.(EAX=07H, ECX= 0H):EBX.ADX[bit 19] = 0.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. 
If the DS, ES, FS, or GS register is used to access memory and it contains a null segment 
selector.

selector.
#PF(fault-code) For a page fault.
#AC(0) If alignment checking is enabled and an  unaligned memory reference is made while the 
#GP(0) If any part of the operand lies outsid e the effective address space from 0 to FFFFH.
#SS(0) For an illegal address in the SS segment.#GP(0) If any part of the operand lies outsid e the effective address space from 0 to FFFFH.
Same exceptions as in protected mode.
#GP(0) If the memory address is in a non-canonical form.#PF(fault-code) For a page fault.
current privilege level is 3.ADD—AddINSTRUCTION SET REFERENCE, A-L
3-32 Vol. 2AADD—Add
Adds the destination operand (first operand) and the sour ce operand (second operand) and then stores the result 
in the destination operand. The destination operand can be  a register or a memory location; the source operand 
can be an immediate, a register, or a memory location . (However, two memory operands cannot be used in one 
instruction.) When an immediate value is used as an operan d, it is sign-extended to the length of the destination 
operand format.
The ADD instruction performs integer addition. It evaluate s the result for both signed and unsigned integer oper-
ands and sets the OF and CF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.Opcode Instruction Op/ 
En64-bit 
04 ib ADD AL, imm8 I Valid Valid Add imm8 to AL.
05 iw ADD AX, imm16 I Valid Valid Add imm16 to AX.05 id ADD EAX, imm32 I Valid Valid Add imm32 to EAX.REX.W + 05 id ADD RAX, imm32 I Valid N.E. Add imm32 sign-extended to 64-bits to RAX.80 /0 ib ADD r/m8, imm8 MI Valid Valid Add imm8 to r/m8.REX + 80 /0 ib ADD r/m8
*, imm8 MI Valid N.E. Add sign-extended imm8 to r/m8.
81 /0 iw ADD r/m16, imm16 MI Valid Valid Add imm16 to r/m16.81 /0 id ADD r/m32, imm32 MI Valid Valid Add imm32 to r/m32.REX.W + 81 /0 id ADD r/m64, imm32 MI Valid N. E. Add imm32 sign-extended to 64-bits to 
r/m64.
83 /0 ib ADD r/m16, imm8 MI Valid Valid Add sign-extended imm8 to r/m16.83 /0 ib ADD r/m32, imm8 MI Valid Valid Add sign-extended imm8 to r/m32.REX.W + 83 /0 ib ADD r/m64, imm8 MI Valid N.E. Add sign-extended imm8 to r/m64.00 /r ADD r/m8, r8 MR Valid Valid Add r8 to r/m8.REX + 00 /r ADD r/m8
*, r8*MR Valid N.E. Add r8 to r/m8.
01 /r ADD r/m16, r16 MR Valid Valid Add r16 to r/m16.01 /r ADD r/m32, r32 MR Valid Valid Add r32 to r/m32.REX.W + 01 /r ADD r/m64, r64 MR Valid N.E. Add r64 to r/m64.02 /r ADD r8, r/m8 RM Vali dV a l i d A d d  r / m 8  t o  r 8 .
REX + 02 /r ADD r8
*, r/m8*RM Valid N.E. Add r/m8 to r8.
03 /r ADD r16, r/m16 RM Valid Valid Add r/m16 to r16.03 /r ADD r32, r/m32 RM Valid Valid Add r/m32 to r32.REX.W + 03 /r ADD r64, r/m64 RM Valid N.E. Add r/m64 to r64.NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. 
I AL/AX/EAX/RAX imm8/16/32 N/A N/AADD—AddINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-33This instruction can be used with a LOCK prefix to  allow the instruction to be executed atomically.
Operation
DEST := DEST + SRC;
selector.
#SS(0) If a memory operand effective a ddress is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#UD If the LOCK prefix is used but th e destination is not a memory operand.
#SS If a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used but th e destination is not a memory operand.
#AC(0) If alignment checking is enabled an d an unaligned memory reference is made.
#UD If the LOCK prefix is used but th e destination is not a memory operand.ADDPD—Add Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-34 Vol. 2AADDPD—Add Packed Double Precision Floating-Point Values
Adds two, four or eight packed double precision floating-p oint values from the first source operand to the second 
source operand, and stores the packed double precis ion floating-point result in the destination operand.
EVEX encoded versions: The first source operand is a ZM M/YMM/XMM register. The second source operand can be 
a ZMM/YMM/XMM register, a 512/256/128-bit memory locati on or a 512/256/128-bit vector broadcasted from a 
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with 
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second so urce operand can be a YMM 
register or a 256-bit memory location. The destination op erand is a YMM register. The upper bits (MAXVL-1:256) of 
the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM 
register or 128-bit memory location. The destination oper and is an XMM register. The upper bits (MAXVL-1:128) of 
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM regist er and the upper Bits (MAXVL-1:128) of the corresponding 
ZMM register destination are unmodified.Opcode/
InstructionOp / 
En64/32 bit 
Mode 
SupportCPUID 
Feature 
FlagDescription
66 0F 58 /r
ADDPD xmm1, xmm2/m128A V/V SSE2 Add packed double precision floating-point values from 
xmm2/mem to xmm1 and store result in xmm1.
VEX.128.66.0F.WIG 58 /r
VADDPD xmm1,xmm2, 
xmm3/m128B V/V AVX Add packed double precision floating-point values from 
xmm3/mem to xmm2 and store result in xmm1.
VEX.256.66.0F.WIG 58 /r
VADDPD ymm1, ymm2, 
ymm3/m256B V/V AVX Add packed double precision floating-point values from 
ymm3/mem to ymm2 and store result in ymm1.
EVEX.128.66.0F.W1 58 /r
VADDPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst C V/V AVX512VL
AVX512FAdd packed double precision floating-point values from 
xmm3/m128/m64bcst to xmm2 and store result in xmm1 with writemask k1.
EVEX.256.66.0F.W1 58 /r
VADDPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstC V/V AVX512VL
ymm3/m256/m64bcst to ymm2 and store result in ymm1 with writemask k1.
EVEX.512.66.0F.W1 58 /r
VADDPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst{er} C V/V AVX512F Add packed double precision floating-point values from 
zmm3/m512/m64bcst to zmm2 and store result in zmm1 
with writemask k1.

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (r, w) ModRM:r/m (r) N/A N/A
B N/A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AADDPD—Add Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-35Operation
VADDPD (EVEX Encoded Versions) When SRC2 Operand is a Vector Register
(KL, VL) = (2, 128),  (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) 
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE 
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;FOR j := 0 TO KL-1
i := j * 64IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := SRC1[i+63:i] + SRC2[i+63:i]ELSE 
IF *merging-masking* ; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE ; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0
VADDPD (EVEX Encoded Versions) When SRC2 Operand is a Memory Source
FOR j := 0 TO KL-1
THEN 
IF (EVEX.b = 1) 
THEN
DEST[i+63:i] := SRC1[i+63:i] + SRC2[63:0]
ELSE 
DEST[i+63:i] := SRC1[i+63:i] + SRC2[i+63:i]
FI;
ELSE 
THEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-masking
FI
FI;
VADDPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] + SRC2[63:0]DEST[127:64] := SRC1[127:64] + SRC2[127:64]DEST[191:128] := SRC1[1 91:128] + SRC2[191:128]
DEST[255:192] := SRC1[2 55:192] + SRC2[255:192]
DEST[MAXVL-1:256] := 0.ADDPD—Add Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-36 Vol. 2AVADDPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] + SRC2[63:0]DEST[127:64] := SRC1[127:64] + SRC2[127:64]DEST[MAXVL-1:128] := 0
ADDPD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] + SRC[63:0]DEST[127:64] := DEST[127:64] + SRC[127:64]DEST[MAXVL-1:128] (Unmodified)
VADDPD __m512d _mm512_add_pd (__m512d a, __m512d b);VADDPD __m512d _mm512_mask_add_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);VADDPD __m512d _mm512_maskz_add_pd (__mmask8 k, __m512d a, __m512d b);VADDPD __m256d _mm256_mask_add_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);VADDPD __m256d _mm256_maskz_add_pd (__mmask8 k, __m256d a, __m256d b);VADDPD __m128d _mm_mask_add_pd (__m128d s,  __mmask8 k, __m128d a, __m128d b);
VADDPD __m128d _mm_maskz_add_pd (__m mask8 k, __m128d a, __m128d b);
VADDPD __m512d _mm512_add_round_pd (__m512d a, __m512d b, int);VADDPD __m512d _mm512_mask_add_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VADDPD __m512d _mm512_maskz_add_round_pd ( __mmask8 k, __m512d a, __m512d b, int);
ADDPD __m256d _mm256_add_pd (__m256d a, __m256d b);ADDPD __m128d _mm_add_pd (__m128d a, __m128d b);
Overflow, Underflow, Invalid, Precision, Denormal.
Other Exceptions
VEX-encoded instruction, see Table 2-19,  “Type 2 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”ADDPS—Add Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-37ADDPS—Add Packed Single Prec ision Floating-Point Values
Adds four, eight or sixteen packed single precision floati ng-point values from the first source operand with the 
second source operand, and stores the packed single pr ecision floating-point result in the destination operand.
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with 
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM 
128-bit Legacy SSE version: The second source can be an  XMM register or an 128-bi t memory location. The desti-
Mode 
Feature 
NP 0F 58 /r
ADDPS xmm1, xmm2/m128A V/V SSE Add packed single precision floating-point values from 
xmm2/m128 to xmm1 and store result in xmm1.
VEX.128.0F.WIG 58 /r
VADDPS xmm1,xmm2, xmm3/m128B V/V AVX Add packed single precision floating-point values from 
xmm3/m128 to xmm2 and store result in xmm1.
VEX.256.0F.WIG 58 /r
VADDPS ymm1, ymm2, ymm3/m256B V/V AVX Add packed single precision floating-point values from 
ymm3/m256 to ymm2 and store result in ymm1.
EVEX.128.0F.W0 58 /r
VADDPS xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcstC V/V AVX512VL
AVX512FAdd packed single precision floating-point values from 
xmm3/m128/m32bcst to xmm2 and store result in 
xmm1 with writemask k1.
EVEX.256.0F.W0 58 /r
VADDPS ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcst C V/V AVX512VL
ymm3/m256/m32bcst to ymm2 and store result in 
ymm1 with writemask k1.
EVEX.512.0F.W0 58 /r
VADDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst {er}C V/V AVX512F Add packed single precision floating-point values from 
zmm3/m512/m32bcst to zmm2 and store result in zmm1 with writemask k1.
CF u l l M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/AADDPS—Add Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-38 Vol. 2AOperation
VADDPS (EVEX Encoded Versions) Wh en SRC2 Operand is a Register
(KL, VL) = (4, 128), (8, 256), (16, 512)IF (VL = 512) AND (EVEX.b = 1) 
THEN
SET_ROUNDING_MODE_FOR_TH IS_INSTRUCTION(EVEX.RC);
ELSE 
i := j * 32IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SR C1[i+31:i] + SRC2[i+31:i]
ELSE 
THEN *DEST[i+31:i] remains unchanged*
DEST[i+31:i] := 0
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0
VADDPS (EVEX Encoded Versions) When SRC2 Operand is a Memory Source
(KL, VL) = (4, 128), (8, 256), (16, 512)
THEN 
THEN
DEST[i+31:i] := SRC1[i+31:i] + SRC2[31:0]
ELSE 
DEST[i+31:i] := SRC1[i +31:i] + SRC2[i+31:i]
FI;
ELSE 
THEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-masking
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0ADDPS—Add Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-39VADDPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] + SRC2[31:0]DEST[63:32] := SRC1[63:32] + SRC2[63:32]DEST[95:64] := SRC1[95:64] + SRC2[95:64]DEST[127:96] := SRC1[127:96] + SRC2[127:96]DEST[159:128] := SRC1[1 59:128] + SRC2[159:128]
DEST[191:160]:= SRC1[191 :160] + SRC2[191:160]
DEST[223:192] := SRC1[2 23:192] + SRC2[223:192]
DEST[255:224] := SRC1[2 55:224] + SRC2[255:224].
DEST[MAXVL-1:256] := 0
VADDPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] + SRC2[31:0]DEST[63:32] := SRC1[63:32] + SRC2[63:32]DEST[95:64] := SRC1[95:64] + SRC2[95:64]DEST[127:96] := SRC1[127:96] + SRC2[127:96]DEST[MAXVL-1:128] := 0
ADDPS (128-bit Legacy SSE Version)
DEST[31:0] := SRC1[31:0] + SRC2[31:0]DEST[63:32] := SRC1[63:32] + SRC2[63:32]DEST[95:64] := SRC1[95:64] + SRC2[95:64]DEST[127:96] := SRC1[127:96] + SRC2[127:96]DEST[MAXVL-1:128 ] (Unmodified)
VADDPS __m512 _mm512_add_ps (__m512 a, __m512 b);
VADDPS __m512 _mm512_mask_add_ps (__m5 12 s, __mmask16 k, __m512 a, __m512 b);
VADDPS __m512 _mm512_maskz_add_ps (__mmask16 k, __m512 a, __m512 b);VADDPS __m256 _mm256_mask_add_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);VADDPS __m256 _mm256_maskz_add_ps (__mmask8 k, __m256 a, __m256 b);VADDPS __m128 _mm_mask_add_ps (__m128d s, __mmask8 k, __m128 a, __m128 b);VADDPS __m128 _mm_maskz_add_ps (__mmask8 k, __m128 a, __m128 b);VADDPS __m512 _mm512_add_round_ps (__m512 a, __m512 b, int);VADDPS __m512 _mm512_mask_add_round_ps (__m512 s,  __mmask16 k, __m512 a, __m512 b, int);
VADDPS __m512 _mm512_maskz_add_round_ps (__m mask16 k, __m512 a, __m512 b, int);
ADDPS __m256 _mm256_add_ps (__m256 a, __m256 b);ADDPS __m128 _mm_add_ps (__m128 a, __m128 b);

VEX-encoded instruction, see Table 2-19, “Type 2 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”ADDSD—Add Scalar Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-40 Vol. 2AADDSD—Add Scalar Double Prec ision Floating-Point Values
Adds the low double precision floating-point values from  the second source operand and the first source operand 
and stores the double precision floating-point result in the destination operand.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination 
operands are XMM registers. 
128-bit Legacy SSE version: The first source and destin ation operands are the same. Bits (MAXVL-1:64) of the 
corresponding destination register remain unchanged.
EVEX and VEX.128 encoded version: The first source operan d is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:64) of 
the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128) of 
the destination register are zeroed. 
EVEX version: The low quadword element of the de stination is updated according to the writemask.
Software should ensure VADDSD is encoded with VEX.L=0. Encoding VADDSD with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.Opcode/
Mode 
Feature 
F2 0F 58 /r
ADDSD xmm1, xmm2/m64A V/V SSE2 Add the low double precision floating-point value from 
xmm2/mem to xmm1 and store the result in xmm1.
VEX.LIG.F2.0F.WIG 58 /r
VADDSD xmm1, xmm2, 
xmm3/m64B V/V AVX Add the low double precision floating-point value from 
xmm3/mem to xmm2 and store the result in xmm1.
EVEX.LLIG.F2.0F.W1 58 /r
VADDSD xmm1 {k1}{z}, xmm2, 
xmm3/m64{er}C V/V AVX512F Add the low double precision floating-point value from 
xmm3/m64 to xmm2 and store the result in xmm1 with 
C Tuple1 Scalar ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/AADDSD—Add Scalar Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-41Operation
VADDSD (EVEX Encoded Version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
ELSE 
FI;IF k1[0] or *no writemask*
THEN DEST[63:0] := SRC1[63:0] + SRC2[63:0]ELSE 
THEN *DEST[63:0] remains unchanged*ELSE ; zeroing-masking
THEN DEST[63:0] := 0
FI;
FI;DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
VADDSD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] + SRC2[63:0]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
ADDSD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] + SRC[63:0]DEST[MAXVL-1:64] (Unmodified)
VADDSD __m128d _mm_mask_add_sd (__m128d s,  __mmask8 k, __m128d a, __m128d b);
VADDSD __m128d _mm_maskz_add_sd (__m mask8 k, __m128d a, __m128d b);
VADDSD __m128d _mm_add_round_sd (__m128d a, __m128d b, int);VADDSD __m128d _mm_mask_add_round _sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VADDSD __m128d _mm_maskz_add_round_sd (__m mask8 k, __m128d a, __m128d b, int);
ADDSD __m128d _mm_add_sd (__m128d a, __m128d b);
VEX-encoded instruction, see Table 2-20, “Type 3 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”ADDSS—Add Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-42 Vol. 2AADDSS—Add Scalar Single Precision Floating-Point Values
Adds the low single precision floating-point values from the second source operand and the first source operand, 
128-bit Legacy SSE version: The first source and destin ation operands are the same. Bits (MAXVL-1:32) of the 
corresponding the destination register remain unchanged.
EVEX and VEX.128 encoded version: The first source operan d is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:32) of 
the destination register are zeroed.
EVEX version: The low doubleword element of the destination is updated according to the writemask.
Software should ensure VADDSS is encoded with VEX.L= 0. Encoding VADDSS with VEX.L=1 may encounter unpre-
Mode 
Feature 
F3 0F 58 /r
ADDSS xmm1, xmm2/m32A V/V SSE Add the low single precision floating-point value from xmm2/mem 
to xmm1 and store th e result in xmm1.
VEX.LIG.F3.0F.WIG 58 /r
VADDSS xmm1,xmm2, 
xmm3/m32B V/V AVX Add the low single precision floating-point value from xmm3/mem 
to xmm2 and store th e result in xmm1.
EVEX.LLIG.F3.0F.W0 58 /r
VADDSS xmm1{k1}{z}, xmm2, 
xmm3/m32{er}C V/V AVX512F Add the low single precision floating-point value from xmm3/m32 
to xmm2 and store the result  in xmm1with writemask k1.
C Tuple1 Scalar ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/AADDSS—Add Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-43Operation
VADDSS (EVEX Encoded Versions)
THEN
ELSE 
THEN DEST[31:0] := SRC1[31:0] + SRC2[31:0]ELSE 
THEN *DEST[31:0] remains unchanged*ELSE ; zeroing-masking
THEN DEST[31:0] := 0
FI;
FI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
VADDSS DEST, SRC1, SRC2 (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] + SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
ADDSS DEST, SRC (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0] + SRC[31:0]DEST[MAXVL-1:32] (Unmodified)
VADDSS __m128 _mm_mask_add_ss (__m128 s,  __mmask8 k, __m128 a, __m128 b);
VADDSS __m128 _mm_maskz_add_ss (_ _mmask8 k, __m128 a, __m128 b);
VADDSS __m128 _mm_add_round_ss (__m128 a, __m128 b, int);VADDSS __m128 _mm_mask_add_round_ ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VADDSS __m128 _mm_maskz_add_round_ss (__mma sk8 k, __m128 a, __m128 b, int);
ADDSS __m128 _mm_add_ss (__m128 a, __m128 b);
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”ADDSUBPD—Packed Double Precision Floating-Point Add/SubtractINSTRUCTION SET REFERENCE, A-L
3-44 Vol. 2AADDSUBPD—Packed Double Precisio n Floating-Point Add/Subtract
Adds odd-numbered double precision floating-point values of the first source operand (second operand) with the 
corresponding double precision floating-point values from  the second source operand (third operand); stores the 
result in the odd-numbered values of the destination op erand (first operand). Subtracts the even-numbered double 
precision floating-point values from the second source operand from the corresponding double precision floating 
values in the first source operand; stores the result in to the even-numbered values of the destination operand. 
In 64-bit mode, using a REX prefix in the form of REX. R permits this instruction to access additional registers 
(XMM8-XMM15).
nation is not distinct from the first source XMM regist er and the upper bits (MAXVL-1:128) of the corresponding 
YMM register destination are unmodified. See Figure 3-3.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination 
operand is an XMM register. The upper bits (MAXVL-1:1 28) of the corresponding YMM register destination are 
zeroed.
register or a 256-bit memory location. Th e destination operand is a YMM register. Opcode/
En64/32-bit 
ModeCPUID 
Feature 
66 0F D0 /r
ADDSUBPD xmm1, xmm2/m128RM V/V SSE3 Add/subtract double precision floating-point 
values from xmm2 /m128 to xmm1.
VEX.128.66.0F.WIG D0 /r

zeroed.
ModeCPUID 
Feature 
66 0F D0 /r
VADDSUBPD xmm1, xmm2, xmm3/m128RVM V/V AVX Add/subtract packed double precision 
floating-point values from xmm3/mem to 
xmm2 and stores result in xmm1.
VEX.256.66.0F.WIG D0 /r
VADDSUBPD ymm1, ymm2, ymm3/m256RVM V/V AVX Add / subtract packed double precision 
floating-point values from ymm3/mem to 
ymm2 and stores result in ymm1.
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AADDSUBPD—Packed Double Precision Floating-Point Add/SubtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-45Operation
ADDSUBPD (128-bit Le gacy SSE Version)
DEST[63:0] := DEST[63:0] - SRC[63:0]DEST[127:64] := DEST[127:64] + SRC[127:64]DEST[MAXVL-1:128 ] (Unmodified)
VADDSUBPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] - SRC2[63:0]DEST[127:64] := SRC1[127:64] + SRC2[127:64]DEST[MAXVL-1:128] := 0
VADDSUBPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] - SRC2[63:0]DEST[127:64] := SRC1[127:64] + SRC2[127:64]DEST[191:128] := SRC1[1 91:128] - SRC2[191:128]
ADDSUBPD __m128d _mm_addsub_pd(__m128d a, __m128d b)
VADDSUBPD __m256d _mm256_addsub_pd (__m256d a, __m256d b)
When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection 
exception (#GP) will be generated.
See Table 2-19, “Type 2 Class Exception Conditions.”Figure 3-3.  ADDSUBPD—Packed Double Precision Floating-Point Add/Subtract[127:64]
xmm1[127:64] + xmm2/m128[127:64] xmm1[63:0] - xmm2/m128[63:0][63:0]
[127:64] [63:0]ADDSUBPD xmm1, xmm2/m128
RESULT:
xmm1xmm2/m128ADDSUBPS—Packed Single Precision Floating-Point Add/SubtractINSTRUCTION SET REFERENCE, A-L
3-46 Vol. 2AADDSUBPS—Packed Single Precisio n Floating-Point Add/Subtract
Adds odd-numbered single precision floating-point values of the first source operand (second operand) with the 
corresponding single precision floating-point values from  the second source operand (third operand); stores the 
result in the odd-numbered values of the destination op erand (first operand). Subtracts the even-numbered single 
precision floating-point values from the second source operand from the corresponding single precision floating 
values in the first source operand; stores the result into the even-numbered values of the destination operand.
YMM register destination are unmodified. See Figure 3-4.
zeroed.
ModeCPUID 
Feature 
F2 0F D0 /r
ADDSUBPS xmm1, xmm2/m128RM V/V SSE3 Add/subtract single precision floating-point 
values from xmm2/m128 to xmm1.
VEX.128.F2.0F.WIG D0 /r
VADDSUBPS xmm1, xmm2, xmm3/m128RVM V/V AVX Add/subtract single precision floating-point 
values from xmm3/mem to xmm2 and stores 
result in xmm1.
VEX.256.F2.0F.WIG D0 /r
VADDSUBPS ymm1, ymm2, ymm3/m256RVM V/V AVX Add / subtract single precision floating-point 
values from ymm3/mem to ymm2 and stores 
RVM ModRM:reg (w) VEX.vv vv (r) ModRM:r/m (r) N/AADDSUBPS—Packed Single Precision Floating-Point Add/SubtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-47Operation
ADDSUBPS (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0] - SRC[31:0]DEST[63:32] := DEST[63:32] + SRC[63:32]DEST[95:64] := DEST[95:64] - SRC[95:64]DEST[127:96] := DEST[127:96] + SRC[127:96]DEST[MAXVL-1:128 ] (Unmodified)
VADDSUBPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[63:32] := SRC1[63:32] + SRC2[63:32]DEST[95:64] := SRC1[95:64] - SRC2[95:64]DEST[127:96] := SRC1[127:96] + SRC2[127:96]DEST[MAXVL-1:128] := 0
VADDSUBPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[63:32] := SRC1[63:32] + SRC2[63:32]DEST[95:64] := SRC1[95:64] - SRC2[95:64]DEST[127:96] := SRC1[127:96] + SRC2[127:96]DEST[159:128] := SRC1[1 59:128] - SRC2[159:128]
DEST[191:160] := SRC1[1 91:160] + SRC2[191:160]
DEST[223:192] := SRC1[2 23:192] - SRC2[223:192]
DEST[255:224] := SRC1[2 55:224] + SRC2[255:224]
ADDSUBPS __m128 _mm_addsub_ps(__m128 a, __m128 b)
VADDSUBPS __m256 _mm256_addsub_ps (__m256 a, __m256 b)
When the source operand is a memory operand, the oper and must be aligned on a 16-byte boundary or a general-
protection exception (#GP) will be generated.Figure 3-4.  ADDSUBPS—Packed Single Precision Floating-P oint Add/SubtractOM15992ADDSUBPS xmm1, xmm2/m128
RESULT:
xmm1xmm2/
m128
xmm1[31:0] - 
xmm2/m128[31:0][31:0]
xmm1[63:32] + 
xmm2/m128[63:32][63:32]
xmm1[95:64] - xmm2/
m128[95:64][95:64]
xmm1[127:96] + 
xmm2/m128[127:96][127:96]
[127:96] [95:64] [63:32] [31:0]ADDSUBPS—Packed Single Precision Floating-Point Add/SubtractINSTRUCTION SET REFERENCE, A-L
3-48 Vol. 2ASIMD Floating-Point Exceptions
See Table 2-19, “Type 2 Class Exception Conditions.”ADOX — Unsigned Integer Addition of Two Operands With Overflow FlagINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-49ADOX — Unsigned Integer Addition of Two Operands With Overflow Flag
Performs an unsigned addition of the destination operan d (first operand), the source operand (second operand) 
and the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a general-
purpose register, whereas the source operand can be a gene ral-purpose register or memory location. The state of 
OF represents a carry from a previous addition. The instru ction sets the OF flag with the carry generated by the 
The ADOX instruction is executed in th e context of multi-precision addition, wh ere we add a series of operands with 
a carry-chain. At the beginning of a chain of additions, we execute an instruction to zero the OF (e.g. XOR).
This instruction is supported in real mode and virtual-80 86 mode. The operand size is always 32 bits if not in 64-
bit mode. 
In 64-bit mode, the default operation size is 32 bits. Usin g a REX Prefix in the form of  REX.R permits access to addi-
tional registers (R8-15). Using REX Prefix in th e form of REX.W promotes operation to 64-bits.
ADOX executes normally either inside or outside a transaction region.Note: ADOX defines the CF and OF flags differently than the ADD/ADC instructions as defined in Intel
® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 2A.
Operation
THEN OF:DEST[63:0] := DEST[63:0] + SRC[63:0] + OF;ELSE OF:DEST[31:0] := DEST[31:0] + SRC[31:0] + OF;
FI;
OF is updated based on result. CF, SF , ZF, AF, and PF flags are unmodified.
unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
F3 0F 38 F6 /r
ADOX r32, r/m32RM V/V ADX Unsigned addition of r32 wi th OF, r/m32 to r32, writes OF.
F3 REX.w 0F 38 F6 /r
ADOX r64, r/m64RM V/N.E. ADX Unsigned addition of r64 with OF, r/m64 to r64, writes OF.
RM ModRM:reg (r, w) ModRM:r/m (r) N/A N/AADOX — Unsigned Integer Addition of  Two Operands With Overflow FlagINSTRUCTION SET REFERENCE, A-L
3-50 Vol. 2AProtected Mode Exceptions
selector.

selector.
#GP(0) If any part of the operand lies outs ide the effective address space from 0 to FFFFH.
#SS(0) For an illegal address in the SS segment.#GP(0) If any part of the operand lies outs ide the effective address space from 0 to FFFFH.
current privilege level is 3.AESDEC—Perform One Round of an AES Decryption FlowINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-51AESDEC—Perform One Round of an AES Decryption Flow
This instruction performs a single round of the AES decryption flow using the Equivalent Inverse Cipher, using 
one/two/four (depending on vector length) 128-bit data (s tate) from the first source operand with one/two/four 
(depending on vector length) round key(s) from the second  source operand, and stores the result in the destina-
tion operand. 
Use the AESDEC instruction for all but the last decrypti on round. For the last decryption round, use the AESDE-
CLAST instruction.
VEX and EVEX encoded versions of th e instruction allow 3-operand (non-destructive) operation. The legacy 
encoded versions of the instruction require that the firs t source operand and the destination operand are the same 
and must be an XMM register.
The EVEX encoded form of this instruction does not support memory fault suppression.Opcode/
ModeCPUID 
Feature 
66 0F 38 DE /r 
AESDEC xmm1, xmm2/m128A V/V AES Perform one round of an AES decryption flow, using 
the Equivalent Inverse Cipher, using one 128-bit data 
(state) from xmm1 with on e 128-bit round key from 
xmm2/m128.
VEX.128.66.0F38.WIG DE /r
VAESDEC xmm1, xmm2, xmm3/m128BV / V A E S  
AVXPerform one round of an AES decryption flow, using 
(state) from xmm2 with on e 128-bit round key from 
xmm3/m128; store the result in xmm1.
VEX.256.66.0F38.WIG DE /r 
VAESDEC ymm1, ymm2, ymm3/m256B V/V VAES Perform one round of an AES decryption flow, using 
the Equivalent Inverse Cipher, using two 128-bit data 
(state) from ymm2 with tw o 128-bit round keys from 
ymm3/m256; store the result in ymm1.
EVEX.128.66.0F38.WIG DE /r
VAESDEC xmm1, xmm2, xmm3/m128CV / V V A E S
AVX512VLPerform one round of an AES decryption flow, using 
EVEX.256.66.0F38.WIG DE /r
VAESDEC ymm1, ymm2, ymm3/m256CV / V V A E S
EVEX.512.66.0F38.WIG DE /r
VAESDEC zmm1, zmm2, zmm3/m512CV / V V A E S
AVX512FPerform one round of an AES decryption flow, using 
the Equivalent Inverse Cipher, using four 128-bit data 
(state) from zmm2 with four 128-bit round keys from zmm3/m512; store the result in zmm1.
Op/En Tuple Operand 1 Operand 2 Operand 3 Operand 4
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/AAESDEC—Perform One Round of an AES Decryption FlowINSTRUCTION SET REFERENCE, A-L
3-52 Vol. 2AOperation
AESDEC 
STATE := SRC1;RoundKey  := SRC2;
STATE  := InvShiftRows( STATE );
STATE  := InvSubBytes( STATE );
STATE  := InvMixColumns( STATE );
DEST[127:0] := STATE XOR RoundKey;DEST[MAXVL-1:128] (Unmodified)
VAESDEC (128b and 256b VEX Encoded Versions)
(KL,VL) = (1,128), (2,256)FOR i = 0 to KL-1:
STATE 
:= SRC1.xmm[i]
RoundKey := SRC2.xmm[i]
STATE := InvShiftRows ( STATE )
STATE := InvSubBytes( STATE )
STATE := InvMixColumns( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] := 0
VAESDEC (EVEX Encoded Version)
(KL,VL) = (1,128),  (2,256), (4,512)
FOR i = 0 to KL-1:
STATE := SRC1.xmm[i]
DEST[MAXVL-1:VL] :=0
(V)AESDEC __m128i _mm_aesdec (__m128i, __m128i)VAESDEC __m256i _mm256_aesdec_epi128(__m256i, __m256i);VAESDEC __m512i _mm512_aesdec_epi128(__m512i, __m512i);
None.
See Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions.”AESDEC128KL—Perform Ten Rounds of AES Decrypti on Flow With Key Locker Using 128-Bit KeyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-53AESDEC128KL—Perform Ten Rounds of AES Decryp tion Flow With Key Locker Using 128-Bit 
Key
The AESDEC128KL1 instruction performs 10 rounds of AES to decr ypt the first operand using the 128-bit key indi-
cated by the handle from the second operand. It stores the result in the first operand if the operation succeeds (e.g., does not run into a handle violation failure).
Operation
AESDEC128KL 
Handle := UnalignedLoad of 384 bit (SRC); // Load is not guaranteed to be atomic.
Illegal Handle = (HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||Handle [2] ||HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES128);
IF (Illegal Handle) {
THEN RFLAGS.ZF := 1;ELSE 
(UnwrappedKey, Authentic) := UnwrapKeyA ndAuthenticate384 (Handle[383:0], IWKey);
IF (Authentic == 0) 
DEST := AES128Decrypt (DEST, UnwrappedKey) ;RFLAGS.ZF := 0;
FI;
FI;RFLAGS.OF, SF, AF, PF, CF := 0;
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other 
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
AESDEC128KL unsigned char _mm_aesdec128kl_u8(__m128i* odata, __m128i idata, const void* h);Opcode/
ModeCPUID 
Feature 
F3 0F 38 DD !(11):rrr:bbb 
AESDEC128KL xmm, m384A V/V AESKLE Decrypt xmm using 128-bit AES key indicated by han-
dle at m384 and store result in xmm.
1. Further details on Key Locker and usage of this instruction can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html .AESDEC128KL—Perform Ten Rounds of AES Decrypti on Flow With Key Locker Using 128-Bit KeyINSTRUCTION SET REFERENCE, A-L
3-54 Vol. 2AExceptions (All Operating Modes)
If CPUID.07H:ECX.KL[bit 23] = 0.If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE[bit 0] = 0.
If CR0.EM = 1.If CR4.OSFXSR = 0.
#NM If CR0.TS = 1.
#PF If a page fault occurs.#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
selector.
If the memory address is in a non-canonical form.
If a memory address referencing the SS segment is in a non-canonical form.AESDEC256KL—Perform 14 Rounds of AES Decrypti on Flow With Key Locker Using 256-Bit KeyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-55AESDEC256KL—Perform 14 Rounds of AES Decryption Flow With Key Locker Using 256-Bit Key
The AESDEC256KL1 instruction performs 14 rounds of AES to decr ypt the first operand using the 256-bit key indi-
cated by the handle from the second operand. It stores the result in the first operand if the operation succeeds 
(e.g., does not run into a handle violation failure).
Operation
AESDEC256KL 
Handle := UnalignedLoad of 512 bit (SRC); // Load is not guaranteed to be atomic.
(Handle[0] AND (CPL > 0)) ||Handle [2] ||HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES256);
IF (Illegal Handle) 
(UnwrappedKey, Authentic) := UnwrapKeyA ndAuthenticate512 (Handle[511:0], IWKey);
DEST := AES256Decrypt (DEST, UnwrappedKey) ;RFLAGS.ZF := 0;
FI;

Operation
FI;
AESDEC256KL unsigned char _mm_aesdec256kl_u8(__m128i* odata, __m128i idata, const void* h);Opcode/
ModeCPUID 
Feature 
F3 0F 38 DF !(11):rrr:bbb 
AESDEC256KL xmm, m512A V/V AESKLE Decrypt xmm using 256-bit AES key indicated by han-
dle at m512 and store result in xmm.
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html .AESDEC256KL—Perform 14 Rounds of AES Decryption  Flow With Key Locker Using 256-Bit KeyINSTRUCTION SET REFERENCE, A-L
3-56 Vol. 2AExceptions (All Operating Modes)
selector.
If a memory address referencing the SS segment is in a non-canonical form.AESDECLAST—Perform Last Round of an AES Decryption FlowINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-57AESDECLAST—Perform Last Round of an AES Decryption Flow
This instruction performs the last round of the AES decryption flow using the Equivalent Inverse Cipher, using 
ModeCPUID 
Feature 
66 0F 38 DF /r
AESDECLAST xmm1, xmm2/m128A V/V AES Perform the last round of an AES decryption flow, 
using the Equivalent Inverse Cipher, using one 128-bit 
data (state) from xmm1 wi th one 128-bit round key 
from xmm2/m128.
VEX.128.66.0F38.WIG DF /r
VAESDECLAST xmm1, xmm2, xmm3/m128BV / V A E S
AVXPerform the last round of an AES decryption flow, 
data (state) from xmm2 wi th one 128-bit round key 
from xmm3/m128; store the result in xmm1.
VEX.256.66.0F38.WIG DF /r 
VAESDECLAST ymm1, ymm2, ymm3/m256B V/V VAES Perform the last round of an AES decryption flow, 
using the Equivalent Inverse Cipher, using two 128-
bit data (state) from ymm2  with two 128-bit round 
keys from ymm3/m256; st ore the result in ymm1.
EVEX.128.66.0F38.WIG DF /r
VAESDECLAST xmm1, xmm2, xmm3/m128CV / V V A E S
AVX512VLPerform the last round of an AES decryption flow, 
EVEX.256.66.0F38.WIG DF /r
VAESDECLAST ymm1, ymm2, ymm3/m256CV / V V A E S
EVEX.512.66.0F38.WIG DF /r
VAESDECLAST zmm1, zmm2, zmm3/m512CV / V V A E S
AVX512FPerform the last round of an AES decryption flow, 
using the Equivalent Inverse Cipher, using four128-bit 
data (state) from zmm2 with  four 128-bit round keys 
from zmm3/m512; store the result in zmm1.
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/AAESDECLAST—Perform Last Round of an AES Decryption FlowINSTRUCTION SET REFERENCE, A-L
3-58 Vol. 2AOperation
AESDECLAST 
STATE  := SRC1;
RoundKey  := SRC2;
DEST[127:0]  := STATE XOR RoundKey;
DEST[MAXVL-1:128] (Unmodified)
VAESDECLAST (128b and 256b VEX Encoded Versions)
STATE 
VAESDECLAST (EVEX Encoded Version)
(V)AESDECLAST __m128i _mm_ae sdeclast (__m128i, __m128i)
VAESDECLAST __m256i _mm256_aesdeclast_epi128(__m256i, __m256i);VAESDECLAST __m512i _mm512_aesdeclast_epi128(__m512i, __m512i);
None.
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions.”AESDECWIDE128KL—Perform Ten Rounds of AES Decryption Fl ow With Key Locker on 8 Blocks Using 128-Bit KeyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-59AESDECWIDE128KL—Perform Ten Round s of AES Decryption Flow Wi th Key Locker on 8 Blocks 
Using 128-Bit Key
The AESDECWIDE128KL1 instruction performs ten rounds of AES to decrypt each of the eight blocks in XMM0-7 
using the 128-bit key indicated by the handle from the second operand. It replaces each input block in XMM0-7 
with its corresponding decrypted block if the operation succe eds (e.g., does not run into a handle violation failure).
Operation
AESDECWIDE128KL
IF Authentic == 0 {
XMM0 := AES128Decrypt (XMM0, UnwrappedKey) ;XMM1 := AES128Decrypt (XMM1, UnwrappedKey) ;XMM2 := AES128Decrypt (XMM2, UnwrappedKey) ;XMM3 := AES128Decrypt (XMM3, UnwrappedKey) ;XMM4 := AES128Decrypt (XMM4, UnwrappedKey) ;XMM5 := AES128Decrypt (XMM5, UnwrappedKey) ;XMM6 := AES128Decrypt (XMM6, UnwrappedKey) ;XMM7 := AES128Decrypt (XMM7, UnwrappedKey) ;RFLAGS.ZF := 0;
FI;
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.Opcode/
ModeCPUID Feature 
F3 0F 38 D8 !(11):001:bbb 
AESDECWIDE128KL m384, <XMM0-7>A V/V AESKLEWIDE_KL Decrypt XMM0-7 using 128-bit AES key indicated 
by handle at m384 and store each resultant block back to its corresponding register.
Op/En Tuple Operand 1 Operands 2—9
A N/A ModRM:r/m (r) Implicit XMM0-7 (r, w)
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html .AESDECWIDE128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker on 8 Blocks Using 128-Bit KeyINSTRUCTION SET REFERENCE, A-L
3-60 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
AESDECWIDE128KLunsigned char _mm_aesdecwide128kl_u8(__m128i odata[8], const __m128i idata[8], const void* h);
Exceptions (All Operating Modes)
If CPUID.19H:EBX.WIDE_KL[bit 2] = 0.
#NM If CR0.TS = 1.#PF If a page fault occurs.
selector.
If a memory address referencing the SS segment is in a non-canonical form.AESDECWIDE256KL—Perform 14 Rounds of AES Decryption Fl ow With Key Locker on 8 Blocks Using 256-Bit KeyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-61AESDECWIDE256KL—Perform 14 Rounds of AES Decryp tion Flow With Key Locker on 8 Blocks 
Using 256-Bit Key
The AESDECWIDE256KL1 instruction performs 14 rounds of AES to decrypt each of the eight blocks in XMM0-7 
using the 256-bit key indicated by the handle from the second operand. It replaces each input block in XMM0-7

selector.
using the 256-bit key indicated by the handle from the second operand. It replaces each input block in XMM0-7 
Operation
AESDECWIDE256KL
(Handle[0] AND (CPL > 0)) ||Handle [2] ||HandleKeyType (Handle) !=  HANDLE_KEY_TYPE_AES256);
XMM0 := AES256Decrypt (XMM0, UnwrappedKey) ;XMM1 := AES256Decrypt (XMM1, UnwrappedKey) ;XMM2 := AES256Decrypt (XMM2, UnwrappedKey) ;XMM3 := AES256Decrypt (XMM3, UnwrappedKey) ;XMM4 := AES256Decrypt (XMM4, UnwrappedKey) ;XMM5 := AES256Decrypt (XMM5, UnwrappedKey) ;XMM6 := AES256Decrypt (XMM6, UnwrappedKey) ;XMM7 := AES256Decrypt (XMM7, UnwrappedKey) ;RFLAGS.ZF := 0;
FI;
F3 0F 38 D8 !(11):011:bbb 
AESDECWIDE256KL m512, <XMM0-7>A V/V AESKLEWIDE_KL Decrypt XMM0-7 using 256-bit AES key indicated 
by handle at m512 and store each resultant block back to its corresponding register.
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html .AESDECWIDE256KL—Perform 14 Rounds of AES Decryption Fl ow With Key Locker on 8 Blocks Using 256-Bit KeyINSTRUCTION SET REFERENCE, A-L
3-62 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
AESDECWIDE256KLunsigned char _mm_aesdecwide256kl_u8(__m128i odata[8], const __m128i idata[8], const void* h);
selector.
If a memory address referencing the SS segment is in a non-canonical form.AESENC—Perform One Round of an AES Encryption FlowINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-63AESENC—Perform One Round of an AES Encryption Flow
This instruction performs a single round of an AES encr yption flow using one/two/four (depending on vector 
length) 128-bit data (state) from the first source operan d with one/two/four (depending on vector length) round 
key(s) from the second source operand, and st ores the result in the destination operand. 
Use the AESENC instruction for all but the last encryption  rounds. For the last encryption round, use the AESENC-
The EVEX encoded form of this instruction does not support memory fault suppression.
Operation
AESENC 
STATE  := ShiftRows( STATE );
STATE  := SubBytes( STATE );
STATE  := MixColumns( STATE );
DEST[MAXVL-1:128 ] (Unmodified)Opcode/
ModeCPUID 
Feature 
66 0F 38 DC /r 
AESENC xmm1, xmm2/m128A V/V AES Perform one round of an AES encryption flow, using one 
128-bit data (state ) from xmm1 with one 128-bit round 
key from xmm2/m128.
VEX.128.66.0F38.WIG DC /r
VAESENC xmm1, xmm2, xmm3/m128BV / V A E S
AVXPerform one round of an AES encryption flow, using one 
128-bit data (state ) from xmm2 with one 128-bit round 
key from the xmm3/m128; store the result in xmm1.
VEX.256.66.0F38.WIG DC /r 
VAESENC ymm1, ymm2, ymm3/m256B V/V VAES Perform one round of an AES encryption flow, using two 
128-bit data (state) from ym m2 with two 128-bit round 
keys from the ymm3/m256; store the result in ymm1.
EVEX.128.66.0F38.WIG DC /r
VAESENC xmm1, xmm2, xmm3/m128CV / V V A E S
AVX512VLPerform one round of an AES encryption flow, using one 
EVEX.256.66.0F38.WIG DC /r
VAESENC ymm1, ymm2, ymm3/m256CV / V V A E S
AVX512VLPerform one round of an AES encryption flow, using two 
EVEX.512.66.0F38.WIG DC /r
VAESENC zmm1, zmm2, zmm3/m512CV / V V A E S
AVX512FPerform one round of an AES encryption flow, using four 
128-bit data (state) from z mm2 with four 128-bit round 
keys from the zmm3/m512; store the result in zmm1.
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AAESENC—Perform One Round of an AES Encryption FlowINSTRUCTION SET REFERENCE, A-L
3-64 Vol. 2AVAESENC (128b and 256b VEX Encoded Versions)
(KL,VL) = (1,128), (2,256)FOR I 
:= 0 to KL-1:
STATE := ShiftRows( STATE )
STATE := SubBytes( STATE )
STATE := MixColumns( STATE )
VAESENC (EVEX Encoded Version)
FOR i := 0 to KL-1:
STATE := SRC1.xmm[i] // xmm[i] is the i’th xmm word in the SIMD register
(V)AESENC __m128i _mm_aesenc (__m128i, __m128i)VAESENC __m256i _mm256_aesenc_epi128(__m256i, __m256i);VAESENC __m512i _mm512_aesenc_epi128(__m512i, __m512i);
None.
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions.”AESENC128KL—Perform Ten Rounds of AES Encrypti on Flow With Key Locker Using 128-Bit KeyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-65AESENC128KL—Perform Ten Rounds of AES Encryption  Flow With Key Lock er Using 128-Bit Key
The AESENC128KL1 instruction performs ten rounds of AES to encr ypt the first operand using the 128-bit key indi-
Operation
AESENC128KL 
Illegal Handle = (
HandleReservedBitSet (Handle) ||(Handle[0] AND (CPL > 0)) ||Handle [1] ||HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES128);
IF (Authentic == 0) THEN RFLAGS.ZF := 1;ELSE 
DEST := AES128Encrypt (DEST, UnwrappedKey) ;RFLAGS.ZF := 0;
FI;
AESENC128KL unsigned char _mm_aesenc128kl_u8(__m128i* odata, __m128i idata, const void* h);Opcode/
ModeCPUID 
Feature 
F3 0F 38 DC !(11):rrr:bbb 
AESENC128KL xmm, m384A V/V AESKLE Encrypt xmm using 128-bit AES key indicated by han-
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.AESENC128KL—Perform Ten Rounds of AES Encrypti on Flow With Key Locker Using 128-Bit KeyINSTRUCTION SET REFERENCE, A-L
3-66 Vol. 2AExceptions (All Operating Modes)
selector.

selector.
If a memory address referencing the SS segment is in a non-canonical form.AESENC256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit KeyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-67AESENC256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit Key
The AESENC256KL1 instruction performs 14 rounds of AES to encr ypt the first operand using the 256-bit key indi-
Operation
AESENC256KL 
HandleReservedBitSet (Handle) ||(Handle[0] AND (CPL > 0)) ||Handle [1] ||HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES256);
DEST := AES256Encrypt (DEST, UnwrappedKey) ;RFLAGS.ZF := 0;
FI;
AESENC256KL unsigned char _mm_aesenc256kl_u8(__m128i* odata, __m128i idata, const void* h);Opcode/
ModeCPUID 
Feature 
F3 0F 38 DE !(11):rrr:bbb 
AESENC256KL xmm, m512A V/V AESKLE Encrypt xmm using 256-bit AES key indicated by han-
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.AESENC256KL—Perform 14 Rounds of AES Encryption  Flow With Key Locker Using 256-Bit KeyINSTRUCTION SET REFERENCE, A-L
3-68 Vol. 2AExceptions (All Operating Modes)
selector.
If a memory address referencing the SS segment is in a non-canonical form.AESENCLAST—Perform Last Round of an AES Encryption FlowINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-69AESENCLAST—Perform Last Round  of an AES Encryption Flow
This instruction performs the last round of an AES encrypti on flow using one/two/four (depending on vector length) 
128-bit data (state) from the first source operand with one/two/four (depending on vector length) round key(s) 
from the second source operand, and stores the result in the destination operand. 
VEX and EVEX encoded versions of th e instruction allows 3-operand (non-destructive) operation. The legacy 
ModeCPUID 
Feature 
66 0F 38 DD /r
AESENCLAST xmm1, xmm2/m128A V/V AES Perform the last round of an AES encryption flow, 
using one 128-bit data (state) from  xmm1 with one 
128-bit round key from xmm2/m128.
VEX.128.66.0F38.WIG DD /r
VAESENCLAST xmm1, xmm2, xmm3/m128BV / V A E S
AVXPerform the last round of an AES encryption flow, 
using one 128-bit data (state) from  xmm2 with one 
128-bit round key from xmm3/m128; store the result 
in xmm1.
VEX.256.66.0F38.WIG DD /r 
VAESENCLAST ymm1, ymm2, ymm3/m256B V/V VAES Perform the last round of an AES encryption flow, 
using two 128-bit data (sta te) from ymm2 with two 
128-bit round keys from ymm3/m256; store the 
EVEX.128.66.0F38.WIG DD /r
VAESENCLAST xmm1, xmm2, xmm3/m128CV / V V A E S
AVX512VLPerform the last round of an AES encryption flow, 
in xmm1.
EVEX.256.66.0F38.WIG DD /r
VAESENCLAST ymm1, ymm2, ymm3/m256CV / V V A E S
EVEX.512.66.0F38.WIG DD /r
VAESENCLAST zmm1, zmm2, zmm3/m512CV / V V A E S
AVX512FPerform the last round of an AES encryption flow, 
using four 128-bit data (sta te) from zmm2 with four 
128-bit round keys from zmm3/m512; store the 
result in zmm1.
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/AAESENCLAST—Perform Last Round of an AES Encryption FlowINSTRUCTION SET REFERENCE, A-L
3-70 Vol. 2AOperation
AESENCLAST 
VAESENCLAST (128b and 256b VEX Encoded Versions)
(KL, VL) = (1,128), (2,256)FOR I=0 to KL-1:
STATE 
VAESENCLAST (EVEX Encoded Version)
(V)AESENCLAST __m128i _mm_ae senclast (__m128i, __m128i)
VAESENCLAST __m256i _mm256_aesenclast_epi128(__m256i, __m256i);VAESENCLAST __m512i _mm512_aesenclast_epi128(__m512i, __m512i);
None.
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions.”AESENCWIDE128KL—Perform Ten Rounds of AES Encryption Fl ow With Key Locker on 8 Blocks Using 128-Bit KeyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-71AESENCWIDE128KL—Perform Ten Rounds of AES Encr yption Flow With Key Locker on 8 Blocks 
The AESENCWIDE128KL1 instruction performs ten rounds of AES to encrypt each of the eight blocks in XMM0-7 
with its corresponding encrypted block if the operation succeeds (e.g., does not run into a handle violation failure).
Operation
AESENCWIDE128KL 
IF Authentic == 0 
THEN RFLAGS.ZF := 1;ELSE XMM0 := AES128Encrypt (XMM0, UnwrappedKey) ;
XMM1 := AES128Encrypt (XMM1, UnwrappedKey) ;XMM2 := AES128Encrypt (XMM2, UnwrappedKey) ;XMM3 := AES128Encrypt (XMM3, UnwrappedKey) ;XMM4 := AES128Encrypt (XMM4, UnwrappedKey) ;XMM5 := AES128Encrypt (XMM5, UnwrappedKey) ;XMM6 := AES128Encrypt (XMM6, UnwrappedKey) ;XMM7 := AES128Encrypt (XMM7, UnwrappedKey) ;RFLAGS.ZF := 0;
FI;
FI;RFLAGS.OF, SF, AF, PF, CF := 0;Opcode/
F3 0F 38 D8 !(11):000:bbb 
AESENCWIDE128KL m384, <XMM0-7>A V/V AESKLE WIDE_KL Encrypt XMM0-7 using 128-bit AES key indicated 
by handle at m384 and store each resultant block back to its corresp onding register.
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.AESENCWIDE128KL—Perform Ten Rounds of AES Encryption Fl ow With Key Locker on 8 Blocks Using 128-Bit KeyINSTRUCTION SET REFERENCE, A-L
3-72 Vol. 2AFlags Affected

FI;
AESENCWIDE128KLunsigned char _mm_aesencwide128kl_u8(__m 128i odata[8], const __m128i idata[8], const void* h);
If CPUID.07H:ECX.KL[bit 23] = 0.
If CR4.KL = 0.If CPUID.AESKLE = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
selector.
If a memory address referencing the SS segment is in a non-canonical form.AESENCWIDE256KL—Perform 14 Rounds of AES Encryption Fl ow With Key Locker on 8 Blocks Using 256-Bit KeyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-73AESENCWIDE256KL—Perform 14 Rounds of AES Encryp tion Flow With Key Locker on 8 Blocks 
The AESENCWIDE256KL1 instruction performs 14 rounds of AES to encrypt each of the eight blocks in XMM0-7 
Operation
AESENCWIDE256KL 
XMM0 := AES256Encrypt (XMM0, UnwrappedKey) ;XMM1 := AES256Encrypt (XMM1, UnwrappedKey) ;XMM2 := AES256Encrypt (XMM2, UnwrappedKey) ;XMM3 := AES256Encrypt (XMM3, UnwrappedKey) ;XMM4 := AES256Encrypt (XMM4, UnwrappedKey) ;XMM5 := AES256Encrypt (XMM5, UnwrappedKey) ;XMM6 := AES256Encrypt (XMM6, UnwrappedKey) ;XMM7 := AES256Encrypt (XMM7, UnwrappedKey) ;RFLAGS.ZF := 0;
FI;
F3 0F 38 D8 !(11):010:bbb 
AESENCWIDE256KL m512, <XMM0-7>A V/V AESKLE WIDE_KL Encrypt XMM0-7 using 256-bit AES key indicated 
by handle at m512 and store each resultant block back to its corresp onding register.
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.AESENCWIDE256KL—Perform 14 Rounds of AES Encryption Fl ow With Key Locker on 8 Blocks Using 256-Bit KeyINSTRUCTION SET REFERENCE, A-L
3-74 Vol. 2AFlags Affected
AESENCWIDE256KLunsigned char _mm_aesencwide256kl_u8(__m 128i odata[8], const __m128i idata[8], const void* h);
If CR4.KL = 0.If CPUID.19H:EBX.AESKLE[bit 0] = 0.
selector.
If a memory address referencing the SS segment is in a non-canonical form.AESIMC—Perform the AES InvMixColumn TransformationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-75AESIMC—Perform the AES InvMixColumn Transformation
Perform the InvMixColumns transformation on the source op erand and store the result in  the destination operand. 
The destination operand is an XMM register. The source op erand can be an XMM register or a 128-bit memory loca-
tion. 
Note: the AESIMC instruction should be applied to the expa nded AES round keys (except for the first and last round 
key) in order to prepare them for decryption using the “Equivalent Inverse Cipher” (defined in FIPS 197). 
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain 
VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESIMC
DEST[127:0] := InvMixColumns( SRC );DEST[MAXVL-1:128 ] (Unmodified)
VAESIMC 
DEST[127:0] := InvMixColumns( SRC );DEST[MAXVL-1:128] := 0;
(V)AESIMC __m128i _mm_aesimc (__m128i)
None.
See Table 2-21, “Type 4 Class Exce ption Conditions,” additionally:
#UD If VEX.vvvv ≠ 1111B.Opcode/
ModeCPUID 
Feature 
66 0F 38 DB /r
AESIMC xmm1, xmm2/m128RM V/V AES Perform the InvMixColumn transformation on 
a 128-bit round key from xmm2/m128 and 
store the result in xmm1.
VEX.128.66.0F38.WIG DB /r
VAESIMC xmm1, xmm2/m128RM V/V Both AES 
andAVX flagsPerform the InvMixColumn transformation on 
a 128-bit round key from xmm2/m128 and store the result in xmm1.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AAESKEYGENASSIST—AES Round Key Generation AssistINSTRUCTION SET REFERENCE, A-L
3-76 Vol. 2AAESKEYGENASSIST—AES Round  Key Generation Assist
Assist in expanding the AES cipher key, by computing st eps towards generating a round key for encryption, using 
128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the result in the destination operand.
tion.
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.
Note: In VEX-encoded versions, VEX.v vvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESKEYGENASSIST
X3[31:0]  := SRC [127: 96];
X2[31:0]  := SRC [95: 64];
X1[31:0] := SRC [63: 32];X0[31:0]  := SRC [31: 0];
RCON[31:0 ] := ZeroExtend(imm8[7:0]);
DEST[31:0]  := SubWord(X1);
DEST[63:32 ]  := RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64] := SubWord(X3);DEST[127:96]  := RotWord( SubWord(X3) ) XOR RCON;
DEST[MAXVL-1:128] (Unmodified)Opcode/
ModeCPUID 
Feature 
66 0F 3A DF /r ib
AESKEYGENASSIST xmm1, xmm2/m128, imm8RMI V/V AES Assist in AES round key generation using an 8 
bits Round Constant (RCON) specified in the 
immediate byte, operating on 128 bits of data 
specified in xmm2/m128 and stores the result in xmm1.
VEX.128.66.0F3A.WIG DF /r ib
VAESKEYGENASSIST xmm1, xmm2/m128, imm8RMI V/V Both AES 
and
AVX flagsAssist in AES round key generation using 8 
immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the 
RMI ModRM:reg (w) ModRM:r/m (r) imm8 N/AAESKEYGENASSIST—AES Round Key Generation AssistINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-77VAESKEYGENASSIST 
X3[31:0] := SRC [127: 96];X2[31:0] := SRC [95: 64];X1[31:0] := SRC [63: 32];X0[31:0] := SRC [31: 0];RCON[31:0] := ZeroExtend(imm8[7:0]);DEST[31:0] := SubWord(X1);DEST[63:32 ] := RotWord( SubWord(X1) ) XOR RCON;DEST[95:64] := SubWord(X3);DEST[127:96] := RotWord( SubWord(X3) ) XOR RCON;DEST[MAXVL-1:128] := 0;
(V)AESKEYGENASSIST __m128i _mm_aeskeygenassist (__m128i, const int)
None.
#UD If VEX.vvvv ≠ 1111B.AND—Logical ANDINSTRUCTION SET REFERENCE, A-L
3-78 Vol. 2AAND—Logical AND
Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in 
the destination operand location. The source operand can be  an immediate, a register, or a memory location; the 
destination operand can be a register or a memory loca tion. (However, two memory operands cannot be used in 
one instruction.) Each bit of the result is set to 1 if both  corresponding bits of the first and second operands are 1; 
otherwise, it is set to 0.
This instruction can be used with a LOCK prefix  to allow the it to be executed atomically.

None.
the summary chart at the beginning of this section for encoding data and limits.Opcode Instruction Op/ 
En64-bit 
24 ib AND AL, imm8 I Valid Valid AL AND imm8.
25 iw AND AX, imm16 I Valid Valid AX AND imm16.25 id AND EAX, imm32 I Valid Valid EAX AND imm32.REX.W + 25 id AND RAX, imm32 I Valid N.E. RAX  AND imm32 sign-extended to 64-bits.
80 /4 ib AND r/m8, imm8 MI Valid Valid r/m8 AND imm8.REX + 80 /4 ib AND r/m8
*, imm8 MI Valid N.E. r/m8 AND imm8.
81 /4 iw AND r/m16, imm16 MI Valid Valid r/m16 AND imm16.81 /4 id AND r/m32, imm32 MI Valid Valid r/m32 AND imm32.REX.W + 81 /4 id AND r/m64, imm32 MI Valid N.E. r/m64 AND imm32 sign extended to 64-bits.83 /4 ib AND r/m16, imm8 MI Valid Valid r/m16 AND imm8 (sign-extended).
83 /4 ib AND r/m32, imm8 MI Valid Valid r/m32 AND imm8 (sign-extended).
REX.W + 83 /4 ib AND r/m64, imm8 MI Valid N.E. r/m64 AND imm8 (sign-extended).20 /r AND r/m8, r8 MR Valid Valid r/m8 AND r8.REX + 20 /r AND r/m8
*, r8*MR Valid N.E. r/m64 AND r8 (sign-extended).
21 /r AND r/m16, r16 MR Valid Valid r/m16 AND r16.21 /r AND r/m32, r32 MR Valid Valid r/m32 AND r32.REX.W + 21 /r AND r/m64, r64 MR Valid N.E. r/m64 AND r32.22 /r AND r8, r/m8 RM Valid Valid r8 AND r/m8.REX + 22 /r AND r8
*, r/m8*RM Valid N.E. r/m64 AND r8 (sign-extended).
23 /r AND r16, r/m16 RM Valid Valid r16 AND r/m16.23 /r AND r32, r/m32 RM Valid Valid r32 AND r/m32.REX.W + 23 /r AND r64, r/m64 RM Valid N.E. r64 AND r/m64.NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
RM ModRM:reg (r, w) ModRM:r/m (r) N/A N/AMR ModRM:r/m (r, w) ModRM:reg (r) N/A N/A
I AL/AX/EAX/RAX imm8/16/32 N/A N/AAND—Logical ANDINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-79Operation
DEST := DEST AND SRC;
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is 
#GP(0) If the destination operand points to a non-writable segment.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#GP(0) If the memory address is in a non-canonical form.
#UD If the LOCK prefix is used but th e destination is not a memory operand.ANDN—Logical AND NOTINSTRUCTION SET REFERENCE, A-L
3-80 Vol. 2AANDN—Logical AND NOT 
Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the 
second source operand). The result is stored in the first operand (destination operand).
This instruction is not supported in real mode and virtua l-8086 mode. The operand size is always 32 bits if not in 
64-bit mode. In 64-bit mode operand size 64 requires VEX. W1. VEX.W1 is ignored in non-64-bit modes. An attempt 
to execute this instruction with VE X.L not equal to 0 will cause #UD.
Operation
DEST := (NOT SRC1) bitwiseAND SRC2;
SF := DEST[OperandSize -1];ZF := (DEST = 0);
SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.
Auto-generated from high-level language.
None.
See Table 2-29, “Type 13 Class Exception Conditions.”Opcode/Instruction Op/ 
En64/32-
bit ModeCPUID 
VEX.LZ.0F38.W0 F2 /r
ANDN r32a, r32b, r/m32RVM V/V BMI1 Bitwise AND of inverted r32b with r/m32, store result in r32a.
VEX.LZ. 0F38.W1 F2 /r
ANDN r64a, r64b, r/m64RVM V/N.E. BMI1 Bitwise AND of inverted r6 4b with r/m64, store result in r64a.
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AANDPD—Bitwise Logical AND of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-81ANDPD—Bitwise Logical AND of Packed Do uble Precision Floating-Point Values
Performs a bitwise logical AND of the two, four or eight pa cked double precision floating-point values from the first 
source operand and the second so urce operand, and stores the result in the destination operand.
a ZMM/YMM/XMM register, a 512/256/128-bit memory locati on, or a 512/256/128-bit vector broadcasted from a 
VEX.256 encoded version: The first source operand is a YM M register. The second source operand is a YMM register 
or a 256-bit memory location. The destination operand is  a YMM register. The upper bits (MAXVL-1:256) of the 
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM 
register destination are unmodified.Opcode/
Mode 
Feature 
66 0F 54 /r
ANDPD xmm1, xmm2/m128A V/V SSE2 Return the bitwise logical AND of packed double precision 
floating-point values in xmm1 and xmm2/mem. 
VEX.128.66.0F 54 /r
VANDPD xmm1, xmm2, xmm3/m128B V/V AVX Return the bitwise logical AND of packed double precision 
floating-point values in xmm2 and xmm3/mem. 
VEX.256.66.0F 54 /r
VANDPD ymm1, ymm2, ymm3/m256B V/V AVX Return the bitwise logical AND of packed double precision 
floating-point values in ymm2 and ymm3/mem.
EVEX.128.66.0F.W1 54 /r
VANDPD xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcstC V/V AVX512VL
AVX512DQReturn the bitwise logical AND of packed double precision 
floating-point values in xmm2 and xmm3/m128/m64bcst 
subject to writemask k1.
EVEX.256.66.0F.W1 54 /r
VANDPD ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcstC V/V AVX512VL
floating-point values in ymm2 and ymm3/m256/m64bcst 
EVEX.512.66.0F.W1 54 /r
VANDPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512DQ Return the bitwise logica l AND of packed double precision 
floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AANDPD—Bitwise Logical AND of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-82 Vol. 2AOperation
VANDPD (EVEX Encoded Versions) 
(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1
THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] := SRC1[i+63: i] BITWISE AND SRC2[63:0]
ELSE 
DEST[i+63:i] := SRC1[i+63: i] BITWISE AND SRC2[i+63:i]
FI;
ELSE 
DEST[i+63:i] = 0
FI;
FI;

THEN
THEN
ELSE 
FI;
ELSE 
FI;
FI;
VANDPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] BITWISE AND SRC2[63:0]DEST[127:64] := SRC1[127:64] BITWISE AND SRC2[127:64]DEST[191:128] := SRC1[191:128] BITWISE AND SRC2[191:128]DEST[255:192] := SRC1[255:192] BITWISE AND SRC2[255:192]DEST[MAXVL-1:256] := 0
VANDPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] BITWISE AND SRC2[63:0]DEST[127:64] := SRC1[127:64] BITWISE AND SRC2[127:64]DEST[MAXVL-1:128] := 0
ANDPD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] BITWISE AND SRC[63:0]DEST[127:64] := DEST[127:64] BITWISE AND SRC[127:64]DEST[MAXVL-1:128] (Unmodified)
VANDPD __m512d _mm512_and_pd (__m512d a, __m512d b);VANDPD __m512d _mm512_mask_and_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);VANDPD __m512d _mm512_maskz_and_pd ( __mmask8 k, __m512d a, __m512d b);
VANDPD __m256d _mm256_mask_and_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);VANDPD __m256d _mm256_maskz_and_pd ( __mmask8 k, __m256d a, __m256d b);
VANDPD __m128d _mm_mask_and_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);VANDPD __m128d _mm_maskz_and_pd (__mmask8 k, __m128d a, __m128d b);VANDPD __m256d _mm256_and_pd (__m256d a, __m256d b);ANDPD __m128d _mm_and_pd (__m128d a, __m128d b);
None.ANDPD—Bitwise Logical AND of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-83Other Exceptions
VEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-84 Vol. 2AANDPS—Bitwise Logical AND of Packed Si ngle Precision Floating-Point Values
Performs a bitwise logical AND of the four, eight or sixtee n packed single precision floating-point values from the 
first source operand and the second source operand,  and stores the result in the destination operand.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register 
VEX.128 encoded version: The first source operand is an  XMM register. The second source operand is an XMM 
Mode 
NP 0F 54 /r
ANDPS xmm1, xmm2/m128A V/V SSE Return the bitwise logical AND of packed single precision 
VEX.128.0F 54 /r
VANDPS xmm1,xmm2, 
xmm3/m128B V/V AVX Return the bitwise logical AND of packed single precision 
VEX.256.0F 54 /r
VANDPS ymm1, ymm2, 
ymm3/m256B V/V AVX Return the bitwise logical AND of packed single precision 
EVEX.128.0F.W0 54 /r
VANDPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstC V/V AVX512VL
AVX512DQReturn the bitwise logical AND of packed single precision 
floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1.
EVEX.256.0F.W0 54 /r
VANDPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstC V/V AVX512VL
floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1.
EVEX.512.0F.W0 54 /r
VANDPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512DQ Return the bitwise logica l AND of packed single precision 
floating-point values in zmm2 and zmm3/m512/m32bcst 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AANDPS—Bitwise Logical AND of Packed Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-85Operation
VANDPS (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1
IF (EVEX.b == 1) AN D (SRC2 *is memory*)
THEN
DEST[i+63:i] := SRC1[i+31:i] BITWISE AND SRC2[31:0]
ELSE 
DEST[i+31:i] := SRC1[i+31: i] BITWISE AND SRC2[i+31:i]
FI;
ELSE 
FI;
FI;
ENDFORDEST[MAXVL-1:VL] := 0;
VANDPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] BITWISE AND SRC2[31:0]DEST[63:32] := SRC1[63:32] BITWISE AND SRC2[63:32]DEST[95:64] := SRC1[95:64] BITWISE AND SRC2[95:64]DEST[127:96] := SRC1[127:96] BITWISE AND SRC2[127:96]DEST[159:128] := SRC1[159:128] BITWISE AND SRC2[159:128]DEST[191:160] := SRC1[191:160] BITWISE AND SRC2[191:160]DEST[223:192] := SRC1[223:192] BITWISE AND SRC2[223:192]DEST[255:224] := SRC1[255:224] BITWISE AND SRC2[255:224].DEST[MAXVL-1:256] := 0;
VANDPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] BITWISE AND SRC2[31:0]DEST[63:32] := SRC1[63:32] BITWISE AND SRC2[63:32]DEST[95:64] := SRC1[95:64] BITWISE AND SRC2[95:64]DEST[127:96] := SRC1[127:96] BITWISE AND SRC2[127:96]DEST[MAXVL-1:128] := 0;
ANDPS (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0] BITWISE AND SRC[31:0]DEST[63:32] := DEST[63:32] BITWISE AND SRC[63:32]DEST[95:64] := DEST[95:64] BITWISE AND SRC[95:64]DEST[127:96] := DEST[127:96] BITWISE AND SRC[127:96]DEST[MAXVL-1:128 ] (Unmodified)ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-86 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
VANDPS __m512 _mm512_and_ps (__m512 a, __m512 b);
VANDPS __m512 _mm512_mask_and_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);VANDPS __m512 _mm512_maskz_and_ps ( __mmask16 k, __m512 a, __m512 b);
VANDPS __m256 _mm256_mask_and_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);VANDPS __m256 _mm256_maskz_and_ps (__mmask8 k, __m256 a, __m256 b);
VANDPS __m128 _mm_mask_and_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VANDPS __m128 _mm_maskz_and_ps ( __mmask8 k, __m128 a, __m128 b);
VANDPS __m256 _mm256_and_ps (__m256 a, __m256 b);ANDPS __m128 _mm_and_ps (__m128 a, __m128 b);
None.
VEX-encoded instruction, see Table 2-21,  “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”ANDNPD—Bitwise Logical AND NOT of Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-87ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
Performs a bitwise logical AND NOT of the two, four or eigh t packed double precision floating-point values from the 
Mode 
Feature 
66 0F 55 /r
ANDNPD xmm1, xmm2/m128A V/V SSE2 Return the bitwise logi cal AND NOT of packed double 
precision floating-point values in xmm1 and xmm2/mem. 
VEX.128.66.0F 55 /r
VANDNPD xmm1, xmm2,

Mode 
Feature 
66 0F 55 /r
VANDNPD xmm1, xmm2, 
xmm3/m128B V/V AVX Return the bitwise logical AND NOT of packed double 
precision floating-point values in xmm2 and xmm3/mem. 
VEX.256.66.0F 55/r
VANDNPD ymm1, ymm2, 
ymm3/m256B V/V AVX Return the bitwise logical AND NOT of packed double 
precision floating-point values in ymm2 and ymm3/mem.
EVEX.128.66.0F.W1 55 /r
VANDNPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV / V A V X 5 1 2 V L
AVX512DQReturn the bitwise logical AND NOT of packed double 
precision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1.
EVEX.256.66.0F.W1 55 /r
VANDNPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV / V A V X 5 1 2 V L
precision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1.
EVEX.512.66.0F.W1 55 /r
VANDNPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512DQ Return the bitwise logical AND NOT of packed double 
precision floating-point values in zmm2 and 
zmm3/m512/m64bcst subject to writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AANDNPD—Bitwise Logical AND NOT of Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-88 Vol. 2AOperation
VANDNPD (EVEX Encoded Versions) 
THEN
DEST[i+63:i] := (NOT(SRC1[i+ 63:i])) BITWISE AND SRC2[63:0]
ELSE 
DEST[i+63:i] := (NOT(SRC1[i+63:i])) BITWISE AND SRC2[i+63:i]
FI;
ELSE 
FI;
FI;
VANDNPD (VEX.256 Encoded Version)
DEST[63:0] := (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]DEST[127:64] := (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]DEST[191:128] := (NOT(SRC1[191:128])) BITWISE AND SRC2[191:128]DEST[255:192] := (NOT(SRC1[255:192])) BITWISE AND SRC2[255:192]DEST[MAXVL-1:256] := 0
VANDNPD (VEX.128 Encoded Version)
DEST[63:0] := (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]DEST[127:64] := (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]DEST[MAXVL-1:128] := 0
ANDNPD (128-bit Legacy SSE Version)
DEST[63:0] := (NOT(DEST[63:0])) BITWISE AND SRC[63:0]DEST[127:64] := (NOT(DEST[12 7:64])) BITWISE AND SRC[127:64]
VANDNPD __m512d _mm512_andnot_pd (__m512d a, __m512d b);VANDNPD __m512d _mm512_mask_andnot_pd (__m5 12d s, __mmask8 k, __m512d a, __m512d b);
VANDNPD __m512d _mm512_maskz_andnot_pd (__mmask8 k, __m512d a, __m512d b);VANDNPD __m256d _mm256_mask_andnot_pd (__m2 56d s, __mmask8 k, __m256d a, __m256d b);
VANDNPD __m256d _mm256_maskz_andnot_pd (__mmask8 k, __m256d a, __m256d b);VANDNPD __m128d _mm_mask_andnot_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);VANDNPD __m128d _mm_maskz_andnot_pd ( __mmask8 k, __m128d a, __m128d b);
VANDNPD __m256d _mm256_andnot_pd (__m256d a, __m256d b);ANDNPD __m128d _mm_andnot_pd (__m128d a, __m128d b);
None.ANDNPD—Bitwise Logical AND NOT of Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-89Other Exceptions
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”ANDNPS—Bitwise Logical AND NOT of Packed  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-90 Vol. 2AANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
Performs a bitwise logical AND NOT of the four, eight or si xteen packed single precision floating-point values from 
the first source operand and the second source operan d, and stores the result in the destination operand.
Mode 
Feature 
NP 0F 55 /r
ANDNPS xmm1, xmm2/m128A V/V SSE Return the bitwise logical AND NOT of packed single precision 
VEX.128.0F 55 /r
VANDNPS xmm1, xmm2, 
xmm3/m128B V/V AVX Return the bitwise logical AND NOT of packed single precision 
VEX.256.0F 55 /r
VANDNPS ymm1, ymm2, 
ymm3/m256B V/V AVX Return the bitwise logical AND NOT of packed single precision 
EVEX.128.0F.W0 55 /r
VANDNPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV / V A V X 5 1 2 V L
EVEX.256.0F.W0 55 /r
VANDNPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV / V A V X 5 1 2 V L
EVEX.512.0F.W0 55 /r
VANDNPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512DQ Return the bi twise logical AND of pa cked single precision 
CF u l l M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/AANDNPS—Bitwise Logical AND NOT of Packed  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-91Operation
VANDNPS (EVEX Encoded Versions)
THEN
DEST[i+31:i] := (NOT(SRC1[i+31:i])) BITWISE AND SRC2[31:0]
ELSE 
DEST[i+31:i] := (NOT(SRC1[i+31:i])) BITWISE AND SRC2[i+31:i]
FI;
ELSE 
DEST[i+31:i] = 0
FI;
FI;
VANDNPS (VEX.256 Encoded Version)
DEST[31:0] := (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]DEST[63:32] := (NOT(SRC1[63: 32])) BITWISE AND SRC2[63:32]
DEST[95:64] := (NOT(SRC1[95: 64])) BITWISE AND SRC2[95:64]
DEST[127:96] := (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]DEST[159:128] := (NOT(SRC1[159:128])) BITWISE AND SRC2[159:128]DEST[191:160] := (NOT(SRC1[191:160])) BITWISE AND SRC2[191:160]DEST[223:192] := (NOT(SRC1[223:192])) BITWISE AND SRC2[223:192]DEST[255:224] := (NOT(SRC1[255:224])) BITWISE AND SRC2[255:224].DEST[MAXVL-1:256] := 0
VANDNPS (VEX.128 Encoded Version)
DEST[127:96] := (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]DEST[MAXVL-1:128] := 0
ANDNPS (128-bit Legacy SSE Version)
DEST[31:0] := (NOT(DEST[31 :0])) BITWISE AND SRC[31:0]
DEST[63:32] := (NOT(DEST[63:32])) BITWISE AND SRC[63:32]DEST[95:64] := (NOT(DEST[95:64])) BITWISE AND SRC[95:64]DEST[127:96] := (NOT(DEST[127:96])) BITWISE AND SRC[127:96]DEST[MAXVL-1:128 ] (Unmodified)ANDNPS—Bitwise Logical AND NOT of Packed  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-92 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
VANDNPS __m512 _mm512_andnot_ps (__m512 a, __m512 b);
VANDNPS __m512 _mm512_mask_andnot_ps (__m 512 s, __mmask16 k, __m512 a, __m512 b);
VANDNPS __m512 _mm512_maskz_andnot_ps  (__mmask16 k, __m512 a, __m512 b);
VANDNPS __m256 _mm256_mask_andnot_ps (__m2 56 s, __mmask8 k, __m256 a, __m256 b);
VANDNPS __m256 _mm256_maskz_andnot_ps (__mmask8 k, __m256 a, __m256 b);VANDNPS __m128 _mm_mask_andnot_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VANDNPS __m128 _mm_maskz_andnot_ps ( __mmask8 k, __m128 a, __m128 b);

VANDNPS __m256 _mm256_andnot_ps (__m256 a, __m256 b);ANDNPS __m128 _mm_andnot_ps (__m128 a, __m128 b);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”ARPL—Adjust RPL Field of Segment SelectorINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-93ARPL—Adjust RPL Fiel d of Segment Selector
Compares the RPL fields of two segment selectors. The first operand (the destination operand) contains one 
segment selector and the second operand (source operand) co ntains the other. (The RPL field is located in bits 0 
and 1 of each operand.) If the RPL field of the destination operand is less than the RPL field of the source operand, 
the ZF flag is set and the RPL field of the destination op erand is increased to match that of the source operand. 
Otherwise, the ZF flag is cleared and no change is made  to the destination operand. (The destination operand can 
be a word register or a memory location; the source operand must be a word register.)
The ARPL instruction is provided for use by operating-syst em procedures (however, it can also be used by applica-
tions). It is generally used to adjust the RPL of a segm ent selector that has been passed to the operating system 
by an application program to match the privilege level of the application program. Here the segment selector 
passed to the operating system is placed in the destin ation operand and segment selector for the application 
program’s code segment is placed in the source operand. (The RPL field in the source operand represents the priv-
ilege level of the application program.) Execution of the AR PL instruction then ensures that the RPL of the segment 
selector received by the operating system is no lower (doe s not have a higher privilege) than the privilege level of 
the application program (the segment selector for the a pplication program’s code segment can be read from the 
stack following a procedure call).
This instruction executes as described in compatibility mode and legacy mode. It is not encodable in 64-bit mode. See “Checking Caller Access Privileges” in Chapter 3,  “Protected-Mode Memory Management,” of the Intel
® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information about the use of this instruc-
tion.
Operation
IF 64-BIT MODE
THEN
See MOVSXD;
ELSE
IF DEST[RPL] < SRC[RPL]
THEN
ZF := 1;DEST[RPL] := SRC[RPL];
ELSE
ZF := 0;
FI;
FI;
The ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise, 
it is set to 0.Opcode Instruction Op/ 
En64-bit 
63 /r ARPL r/m16, r16 MR N. E. Valid Adjust RPL of r/m16 to not less than RPL of 
r16.
MR ModRM:r/m (w) ModRM:reg (r) N/A N/AARPL—Adjust RPL Field of Segment SelectorINSTRUCTION SET REFERENCE, A-L
3-94 Vol. 2AProtected Mode Exceptions
selector.
#UD The ARPL instruction is not recognized in real-address mode.
If the LOCK prefix is used.
#UD The ARPL instruction is not recognized in virtual-8086 mode.
Not applicable.BEXTR—Bit Field ExtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-95BEXTR—Bit Field Extract 
Extracts contiguous bits from the first source operand (t he second operand) using an index value and length value 
specified in the second source operand (the third operan d). Bit 7:0 of the second source operand specifies the 
starting bit position of bit extraction. A START value exce eding the operand size will not extract any bits from the 
second source operand. Bit 15:8 of the second source  operand specifies the maximum number of bits (LENGTH) 
beginning at the START position to extract. Only bit positi ons up to (OperandSize -1) of the first source operand are 
extracted. The extracted bits are written to the destination re gister, starting from the least significant bit. All higher 
order bits in the destination operand (starting at bit po sition LENGTH) are zeroed. The destination register is 
cleared if no bits are extracted.
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An 
attempt to execute this instruction with  VEX.L not equal to 0 will cause #UD.
Operation
START := SRC2[7:0];
LEN := SRC2[15:8];TEMP := ZERO_EXTEND_TO_512 (SRC1 );DEST := ZERO_EXTEND(TEMP[START+LEN -1: START]);ZF := (DEST = 0);
ZF is updated based on the result. AF, SF, and PF are undefined. All other flags are cleared. 
BEXTR unsigned __int32 _bextr_u32(u nsigned __int32 src, un signed __int32 start. unsigned __int32 len);
BEXTR unsigned __int64 _bextr_u64(u nsigned __int64 src, un signed __int32 start. unsigned __int32 len);
None.
See Table 2-29, “Type 13 Class Exception Conditions,” additionally:
#UD If VEX.W = 1.Opcode/Instruction Op/ 
En64/32-
VEX.LZ.0F38.W0 F7 /r
BEXTR r32a, r/m32, r32bRMV V/V BMI1 Contiguous bitwise extract from r/m32 using r32b as control; store 
result in r32a.
VEX.LZ.0F38.W1 F7 /r
BEXTR r64a, r/m64, r64bRMV V/N.E. BMI1 Contiguous bitw ise extract from r/m64 usin g r64b as control; store 
result in r64a.
RMV ModRM:reg (w) ModRM:r/m (r) VEX.vvvv (r) N/ABLENDPD—Blend Packed Double Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-96 Vol. 2ABLENDPD—Blend Packed Double Pr ecision Floating-Point Values
Double-precision floating-point values from the second source operand (third operand) are conditionally merged 
with values from the first source operand (second operand) and written to the destination operand (first operand). 
The immediate bits [3:0] determine whether the correspondi ng double precision floating-point value in the desti-
nation is copied from the second source or first source. If  a bit in the mask, corresponding to a word, is ”1”, then 
the double precision floating-point value in the second sour ce operand is copied, else the value in the first source 
operand is copied.
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an  XMM register. The second source operand is an XMM 
the corresponding YMM register destination are zeroed.
register or a 256-bit memory location. Th e destination operand is a YMM register. 
Operation
BLENDPD (128-bit Legacy SSE Version)
IF (IMM8[0] = 0)THEN DE ST[63:0] := DEST[63:0]
ELSE DEST [63:0] := SRC[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] := DEST[127:64]
ELSE DEST [127:64] := SRC[127:64] FI
VBLENDPD (VEX.128 Encoded Version)
IF (IMM8[0] = 0)THEN DE ST[63:0] := SRC1[63:0]
ELSE DEST [63:0] := SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] := SRC1[127:64]
ELSE DEST [127:64] := SRC2[127:64] FI
DEST[MAXVL-1:128] := 0Opcode/
ModeCPUID 
Feature 
66 0F 3A 0D /r ib
BLENDPD xmm1, xmm2/m128, imm8RMI V/V SSE4_1 Select packed double precision floating-point 
values from xmm1 and xmm2/m128 from 
mask specified in imm8 and store the values 
into xmm1.
VEX.128.66.0F3A.WIG 0D /r ib
VBLENDPD xmm1, xmm2, xmm3/m128, imm8RVMI V/V AVX Select packed double precision floating-point 
Values from xmm2 and xmm3/m128 from 
mask in imm8 and stor e the values in xmm1.
VEX.256.66.0F3A.WIG 0D /r ib
VBLENDPD ymm1, ymm2, ymm3/m256, imm8RVMI V/V AVX Select packed double precision floating-point 
Values from ymm2 and ymm3/m256 from

ModeCPUID 
Feature 
into xmm1.
Values from ymm2 and ymm3/m256 from 
mask in imm8 and stor e the values in ymm1.
RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 N/A
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8[3:0]BLENDPD—Blend Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-97VBLENDPD (VEX.256 Encoded Version)
IF (IMM8[0] = 0)THEN DEST[63:0] := SRC1[63:0]
IF (IMM8[2] = 0) THEN DEST [191:128] := SRC1[191:128]
ELSE DEST [191:128] := SRC2[191:128] FI
IF (IMM8[3] = 0) THEN DEST [255:192] := SRC1[255:192]
ELSE DEST [255:192] := SRC2[255:192] FI
BLENDPD __m128d _mm_blend_pd (__m128d v1, __m128d v2, const int mask);
VBLENDPD __m256d _mm256_blend_pd (__m256d a, __m256d b, const int mask);
None.
See Table 2-21, “Type 4 Class Exception Conditions.”BLENDPS—Blend Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-98 Vol. 2ABLENDPS—Blend Packed Single Pr ecision Floating-Point Values
Packed single precision floating-point values from the second source operand (third operand) are conditionally 
merged with values from the first source operand (secon d operand) and written to the destination operand (first 
operand). The immediate bits [7:0] determine whether the corresponding single precision floating-point value in 
the destination is copied from the second source or first so urce. If a bit in the mask, corresponding to a word, is “1”, 
then the single precision floating-point value in the seco nd source operand is copied, else the value in the first 
source operand is copied.
VEX.128 encoded version: The first source operand an XMM register. The second source operand is an XMM register 
or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the 
corresponding YMM register destination are zeroed.
Operation
BLENDPS (128-bit Legacy SSE Version)
IF (IMM8[0] = 0) THEN DEST[31:0] :=DEST[31:0]
ELSE DEST [31:0] := SRC[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32] := DEST[63:32]
ELSE DEST [63:32] := SRC[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64] := DEST[95:64]
ELSE DEST [95:64] := SRC[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96] := DEST[127:96]
ELSE DEST [127:96] := SRC[127:96] FI
ModeCPUID 
Feature 
66 0F 3A 0C /r ib
BLENDPS xmm1, xmm2/m128, imm8RMI V/V SSE4_1 Select packed single precision floating-point 
mask specified in imm8  and store the values 
into xmm1.
VEX.128.66.0F3A.WIG 0C /r ib
VBLENDPS xmm1, xmm2, xmm3/m128, imm8RVMI V/V AVX Select packed single precision floating-point 
values from xmm2 and xmm3/m128 from 
mask in imm8 and store the values in xmm1.
VEX.256.66.0F3A.WIG 0C /r ib
VBLENDPS ymm1, ymm2, ymm3/m256, imm8RVMI V/V AVX Select packed single precision floating-point 
values from ymm2 and ymm3/m256 from mask in imm8 and store the values in ymm1.
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8BLENDPS—Blend Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-99VBLENDPS (VEX.128 Encoded Version)
IF (IMM8[0] = 0) THEN DEST[31:0] :=SRC1[31:0]
ELSE DEST [31:0] := SRC2[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32] := SRC1[63:32]
ELSE DEST [63:32] := SRC2[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64] := SRC1[95:64]
ELSE DEST [95:64] := SRC2[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96] := SRC1[127:96]
ELSE DEST [127:96] := SRC2[127:96] FI
DEST[MAXVL-1:128] := 0
VBLENDPS (VEX.256 Encoded Version)
IF (IMM8[4] = 0) THEN DEST [159:128] := SRC1[159:128]
ELSE DEST [159:128] := SRC2[159:128] FI
IF (IMM8[5] = 0) THEN DEST [191:160] := SRC1[191:160]
ELSE DEST [191:160] := SRC2[191:160] FI
IF (IMM8[6] = 0) THEN DEST [223:192] := SRC1[223:192]
ELSE DEST [223:192] := SRC2[223:192] FI
IF (IMM8[7] = 0) THEN DEST [255:224] := SRC1[255:224]
ELSE DEST [255:224] := SRC2[255:224] FI.
BLENDPS __m128 _mm_blend_ps (__m128 v1, __m128 v2, const int mask);
VBLENDPS __m256 _mm256_blend_ps (__m256 a, __m256 b, const int mask);
None.
See Table 2-21, “Type 4 Class Exception Conditions.”BLENDVPD—Variable Blend Packed Doub le Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-100 Vol. 2ABLENDVPD—Variable Blend Packed Double Precision Floating-Point Values
Conditionally copy each quadword data element of double  precision floating-point value from the second source 
operand and the first source operand depending on mask bits  defined in the mask register operand. The mask bits 
are the most significant bit in each quadword element of the mask register.
Each quadword element of the destination operand is copied from:
•the corresponding quadword element in the second  source operand, if a mask bit is “1”; or
•the corresponding quadword element in the first source operand, if a mask bit is “0”
The register assignment of the implicit mask operand fo r BLENDVPD is defined to be the architectural register 
XMM0.
128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (MAXVL-1:128) 
of the corresponding YMM destination register remain uncha nged. The mask register operand is implicitly defined 
to be the architectural register XMM0. An attempt to  execute BLENDVPD with a VEX prefix will cause #UD.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second 
source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and 
encoded in bits[7:4] of the immediate byte(imm8). The bits [3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is 
ignored. The upper bits (MAXVL-1:128) of the corresponding  YMM register (destination register) are zeroed. VEX.W 
must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and de stination operand are YMM registers. The second source 
operand can be a YMM register or a 256-bit memory locati on. The mask operand is the third source register, and 
ignored. VEX.W must be 0, otherwise, the instruction will #UD.
VBLENDVPD permits the mask to be any XMM or YMM register. In contrast, BLENDVPD treats XMM0 implicitly as the 
mask and do not support non-destructive destination operation. Opcode/
ModeCPUID 
Feature 
66 0F 38 15 /r
BLENDVPD xmm1, xmm2/m128 , <XMM0>RM0 V/V SSE4_1 Select packed double precision floating-point 
values from xmm1 and xm m2 from mask specified 
in XMM0 and store the values in xmm1.
VEX.128.66.0F3A.W0 4B /r /is4
VBLENDVPD xmm1, xmm2, xmm3/m128, xmm4RVMR V/V AVX Conditionally copy double precision floating-point 
values from xmm2 or xmm3/m128 to xmm1, based on mask bits in the mask operand, xmm4.
VEX.256.66.0F3A.W0 4B /r /is4
VBLENDVPD ymm1, ymm2, ymm3/m256, ymm4RVMR V/V AVX Conditionally copy double precision floating-point 
values from ymm2 or ymm3/m256 to ymm1, based 
on mask bits in the mask operand, ymm4.
RM0 ModRM:reg (r, w) ModRM:r/m (r) implicit XMM0 N/A
RVMR ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8[7:4]BLENDVPD—Variable Blend Packed Doub le Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-101Operation
BLENDVPD (128-bit Legacy SSE Version)
MASK := XMM0IF (MASK[63] = 0) THEN DEST[63:0] := DEST[63:0]
IF (MASK[127] = 0) THEN DEST[127:64] := DEST[127:64]
DEST[MAXVL-1:128 ] (Unmodified)
VBLENDVPD (VEX.128 Encoded Version)
MASK := SRC3IF (MASK[63] = 0) THEN DEST[63:0] := SRC1[63:0]
IF (MASK[127] = 0) THEN DEST[127:64] := SRC1[127:64]

VBLENDVPD (VEX.256 Encoded Version)
IF (MASK[191] = 0) THEN DEST[191:128] := SRC1[191:128]
IF (MASK[255] = 0) THEN DEST[255:192] := SRC1[255:192]
BLENDVPD __m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3);
VBLENDVPD __m128 _mm_blendv_pd (__m128d a, __m128d b, __m128d mask);VBLENDVPD __m256 _mm256_blendv_pd (__m256d a, __m256d b, __m256d mask);
None.
See Table 2-21, “Type 4 Class Exception Conditions,” additionally:
#UD If VEX.W = 1.BLENDVPS—Variable Blend Packed Sing le Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-102 Vol. 2ABLENDVPS—Variable Blend Packed Single Precision Floating-Point Values
Conditionally copy each dword data element of single precision floating-point value from the second source 
are the most significant bit in each dword element of the mask register.
•the corresponding dword element in the second source operand, if a mask bit is “1”; or
•the corresponding dword element in the first source operand, if a mask bit is “0”.
The register assignment of the implicit mask operand fo r BLENDVPS is defined to be the architectural register 
XMM0.
to be the architectural register XMM0. An attempt to  execute BLENDVPS with a VEX prefix will cause #UD.
VBLENDVPS permits the mask to be any XMM or YMM register . In contrast, BLENDVPS treats XMM0 implicitly as the 
ModeCPUID 
Feature 
66 0F 38 14 /r
BLENDVPS xmm1, xmm2/m128, <XMM0>RM0 V/V SSE4_1 Select packed single precision floating-point values 
from xmm1 and xmm2/m128 from mask specified 
in XMM0 and store the values into xmm1.
VEX.128.66.0F3A.W0 4A /r /is4
VBLENDVPS xmm1, xmm2, xmm3/m128, xmm4RVMR V/V AVX Conditionally copy single precision floating-point 
values from xmm2 or xmm3/m128 to xmm1, based on mask bits in the specified mask operand, xmm4.
VEX.256.66.0F3A.W0 4A /r /is4
VBLENDVPS ymm1, ymm2, ymm3/m256, ymm4RVMR V/V AVX Conditionally copy single precision floating-point 
on mask bits in the spec ified mask register, ymm4.
RVMR ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8[7:4]BLENDVPS—Variable Blend Packed Sing le Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-103Operation
BLENDVPS (128-bit Legacy SSE Version)
MASK := XMM0IF (MASK[31] = 0) THEN DEST[31:0] := DEST[31:0]
IF (MASK[63] = 0) THEN DEST[63:32] := DEST[63:32]
IF (MASK[95] = 0) THEN DEST[95:64] := DEST[95:64]
IF (MASK[127] = 0) THEN DEST[127:96] := DEST[127:96]
VBLENDVPS (VEX.128 Encoded Version)
MASK := SRC3
IF (MASK[31] = 0) THEN DEST[31:0] := SRC1[31:0]
IF (MASK[63] = 0) THEN DEST[63:32] := SRC1[63:32]
IF (MASK[95] = 0) THEN DEST[95:64] := SRC1[95:64]
IF (MASK[127] = 0) THEN DEST[127:96] := SRC1[127:96]
VBLENDVPS (VEX.256 Encoded Version)
MASK := SRC3IF (MASK[31] = 0) THEN DEST[31:0] := SRC1[31:0]
IF (MASK[159] = 0) THEN DEST[159:128] := SRC1[159:128]
IF (MASK[191] = 0) THEN DEST[191:160] := SRC1[191:160]
IF (MASK[223] = 0) THEN DEST[223:192] := SRC1[223:192]
IF (MASK[255] = 0) THEN DEST[255:224] := SRC1[255:224]
ELSE DEST [255:224] := SRC2[255:224] FI
BLENDVPS __m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3);
VBLENDVPS __m128 _mm_blendv_ps ( __m128 a, __m128 b, __m128 mask);
VBLENDVPS __m256 _mm256_blendv_ps (__m256 a, __m256 b, __m256 mask);
None.BLENDVPS—Variable Blend Packed Sing le Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-104 Vol. 2AOther Exceptions
#UD If VEX.W = 1.BLSI—Extract Lowest Set Isolated BitINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-105BLSI—Extract Lowest Set Isolated Bit
Extracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All 
other bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in 
the destination to 0 and sets ZF and CF.
Operation
temp := (-SRC) bi twiseAND (SRC); 
SF := temp[OperandSize -1];ZF := (temp = 0);IF SRC = 0
CF := 0;
ELSE
CF := 1;
FIDEST := temp;
ZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF 
flags are undefined.
BLSI unsigned __int32 _blsi_u32(unsigned __int32 src);
BLSI unsigned __int64 _blsi_u64(unsigned __int64 src);
None.
En64/32-
VEX.LZ.0F38.W0 F3 /3
BLSI r32, r/m32VM V/V BMI1 Extract lowest set bit fr om r/m32 and set that bit in r32.
VEX.LZ.0F38.W1 F3 /3
BLSI r64, r/m64VM V/N.E. BMI1 Extract lowest set bit fr om r/m64, and set that bit in r64.
VM VEX.vvvv (w) ModRM:r/m (r) N/A N/ABLSMSK—Get Mask Up to Lowest Set BitINSTRUCTION SET REFERENCE, A-L
3-106 Vol. 2ABLSMSK—Get Mask Up to Lowest Set Bit
Sets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source 
operand. If source operand is zero, BLSMSK sets all bits  of the destination operand to 1 and also sets CF to 1.
Operation
temp := (SRC-1) XOR (SRC) ;
SF := temp[OperandSize -1];ZF := 0;IF SRC = 0
CF := 1;
ELSE
CF := 0;
SF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are 
BLSMSK unsigned __int32 _blsms k_u32(unsigned __int32 src);
BLSMSK unsigned __int64 _blsms k_u64(unsigned __int64 src);
None.

Operation
CF := 1;
ELSE
CF := 0;
None.
En64/32-
VEX.LZ.0F38.W0 F3 /2
BLSMSK r32, r/m32VM V/V BMI1 Set all lower bits in r32 to “1” starting from bit 0 to  lowest set bit in 
r/m32.
VEX.LZ.0F38.W1 F3 /2
BLSMSK r64, r/m64VM V/N.E. BMI1 Set all lower bits in r64 to “1” starting from bit 0 to lowest set bit in 
r/m64.
VM VEX.vvvv (w) ModRM:r/m (r) N/A N/ABLSR—Reset Lowest Set BitINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-107BLSR—Reset Lowest Set Bit
Copies all bits from the source operand to the destinatio n operand and resets (=0) the bit position in the destina-
tion operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets 
CF.
Operation
temp := (SRC-1) bi twiseAND ( SRC );
CF := 1;
ELSE
CF := 0;
ZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags 
BLSR unsigned __int32 _blsr_u32(unsigned __int32 src);
BLSR unsigned __int64 _blsr_u64(unsigned __int64 src);
None.
En64/32-
VEX.LZ.0F38.W0 F3 /1
BLSR r32, r/m32VM V/V BMI1 Reset lowest set bit of r/m32, keep all other bits of r/m32 and write 
result to r32.
VEX.LZ.0F38.W1 F3 /1
BLSR r64, r/m64VM V/N.E. BMI1 Reset lowest set bit of r/m64, keep all other bits of r/m64 and write 
result to r64.
VM VEX.vvvv (w) ModRM:r/m (r) N/A N/ABNDCL—Check Lower BoundINSTRUCTION SET REFERENCE, A-L
3-108 Vol. 2ABNDCL—Check Lower Bound
Compare the address in the second operand with the lowe r bound in bnd. The second operand can be either a 
register or memory operand. If the address is lower than the lower bound in bnd.LB, it will set BNDSTATUS to 01H 
and signal a #BR exception.
This instruction does not cause any memory access, and does not read or write any flags. 
Operation
BNDCL BND, reg
IF reg < BND.LB Then
BNDSTATUS := 01H; #BR; 
FI;
BNDCL BND, mem
TEMP := LEA(mem); IF TEMP < BND.LB Then
FI;
BNDCL void   _bnd_chk_ptr_lbounds(const void *q)
None
#BR If lower bound check fails.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.Opcode/
InstructionOp/En 64/32 bit 
F3 0F 1A /r
BNDCL bnd, r/m32RM N.E./V MPX Generate a #BR if the address in r/m32 is lower than the lower 
bound in bnd.LB.
F3 0F 1A /r
BNDCL bnd, r/m64RM V/N.E. MPX Generate a #BR if the address in r/m64 is lower than the lower 
Op/En Operand 1 Operand 2 Operand 3
RM ModRM:reg (w) ModRM:r/m (r) N/ABNDCL—Check Lower BoundINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-109Real-Address Mode Exceptions
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#UD If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.Same exceptions as in protected mode.BNDCU/BNDCN—Check Upper BoundINSTRUCTION SET REFERENCE, A-L
3-110 Vol. 2ABNDCU/BNDCN—Check Upper Bound
Compare the address in the second operand with the upper bound in bnd. The second operand can be either a 
register or a memory operand. If the address is higher than the upper bound in bnd.UB, it will set BNDSTATUS to 
01H and signal a #BR exception.
BNDCU perform 1’s complement operation on the upper boun d of bnd first before proceeding with address compar-
ison. BNDCN perform address comparison directly using the upper bound in bnd that is already reverted out of 1’s 
complement form. 
This instruction does not cause any memory access, and does not read or write any flags. Effective address computation of m32/64 has identical behavior to LEA
Operation
BNDCU BND, reg
IF reg > NOT( BND.UB) Then
FI;
BNDCU BND, mem
TEMP := LEA(mem); IF TEMP > NOT(BND.UB) Then
FI;
BNDCN BND, reg
IF reg > BND.UB Then
FI;Opcode/
F2 0F 1A /r
BNDCU bnd, r/m32RM N.E./V MPX Generate a #BR if the address in r/m32 is higher than the upper 
bound in bnd.UB (bnb.UB in 1's complement form).
F2 0F 1A /r
BNDCU bnd, r/m64RM V/N.E. MPX Generate a #BR if the address in r/m64 is higher than the upper 
F2 0F 1B /r
BNDCN bnd, r/m32RM N.E./V MPX Generate a #BR if the address in r/m32 is higher than the upper 
bound in bnd.UB (bnb.UB not in 1's complement form).
F2 0F 1B /r
BNDCN bnd, r/m64RM V/N.E. MPX Generate a #BR if the address in r/m64 is higher than the upper 
RM ModRM:reg (w) ModRM:r/m (r) N/ABNDCU/BNDCN—Check Upper BoundINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-111BNDCN BND, mem
TEMP := LEA(mem); IF TEMP > BND.UB Then
FI;
BNDCU .void   _bnd_chk_ptr _ubounds(const void *q)
None
#BR If upper bound check fails.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.If 16-bit addressing is used.
#BR If upper bound check fails.#UD If the LOCK prefix is used.
#UD If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.Same exceptions as in protected mode.BNDLDX—Load Extended Bounds Using Address TranslationINSTRUCTION SET REFERENCE, A-L
3-112 Vol. 2ABNDLDX—Load Extended Bounds  Using Address Translation
BNDLDX uses the linear address constructed from the base  register and displacement of the SIB-addressing form 
of the memory operand (mib) to perform address translat ion to access a bound table entry and conditionally load 
the bounds in the BTE to the destination. The destination register is updated with the bounds in the BTE, if the 
content of the index register of mib matches the pointer value stored in the BTE. 
If the pointer value comparison fails, the destination is up dated with INIT bounds (lb = 0x0, ub = 0x0) (note: as 
articulated earlier, the upper bound is represented using 1's complement, therefore, the 0x0 value of upper bound 
allows for access to full memory). 
This instruction does not cause memory access to the linear address of mib nor the effective address referenced by 
the base, and does not read or write any flags. 
Segment overrides apply to the linear address computation with the base of mib, and are used during address 
translation to generate the address of the bound table entr y. By default, the address of the BTE is assumed to be 
linear address. There are no segmentation checks performed on the base of mib. 
The base of mib will not be checked for canonical address violation as it does not access memory. Any encoding of this instruction that does not specify base or index register will treat those registers as zero 
(constant). The reg-reg form of this instruction will remain a NOP.
The scale field of the SIB byte has no effect on these instructions and is ignored.The bound register may be partially updated on memory fa ults. The order in which memory operands are loaded is 
implementation specific.
Operation
base := mib.SIB.base ? mib.SIB.base + Disp: 0;
ptr_value := mib.SIB.index ? mib.SIB.index : 0;
Outside 64-bit Mode

Operation
A_BDE[31:0] := (Zero_extend32(base[31:12] « 2) + (BNDCFG[31:12] «12 );A_BT[31:0] := LoadFrom(A_BDE );IF A_BT[0] equal 0 Then
BNDSTATUS := A_BDE | 02H; #BR; 
FI;A_BTE[31:0] := (Zero_extend32(base[11:2] « 4) + (A_BT[31:2] « 2 );Temp_lb[31:0] := LoadFrom(A_BTE);
Temp_ub[31:0] := LoadFrom(A_BTE + 4);Temp_ptr[31:0] := LoadFrom(A_BTE + 8);IF Temp_ptr equal ptr_value Then
BND.LB := Temp_lb; BND.UB := Temp_ub; Opcode/
NP 0F 1A /r
BNDLDX bnd, mibRM V/V MPX Load the bounds stored in a bound table entry (BTE) into bnd with 
address translation using the base  of mib and conditional on the 
index of mib matching the pointer value in the BTE.
RM ModRM:reg (w)SIB.base (r): Address of pointer
SIB.index(r)N/ABNDLDX—Load Extended Bounds Using Address TranslationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-113ELSE
BND.LB := 0;BND.UB := 0;
FI;
In 64-bit Mode
A_BDE[63:0] := (Zero_extend64(base[47+MAWA:20] « 3) + (BNDCFG[63:12] «12 );
1
A_BT[63:0] := LoadFrom(A_BDE);IF A_BT[0] equal 0 Then
FI;A_BTE[63:0] := (Zero_extend64(base[19:3] « 5) + (A_BT[63:3] « 3 );Temp_lb[63:0] := LoadFrom(A_BTE);
Temp_ub[63:0] := LoadFrom(A_BTE + 8);Temp_ptr[63:0] := LoadFrom(A_BTE + 16);IF Temp_ptr equal ptr_value Then
BND.LB := Temp_lb; BND.UB := Temp_ub; 
ELSE
FI;
BNDLDX: Generated by compiler as needed.
None.
#BR If the bound directory entry is invalid.
#GP(0) If a destination effective address of the Bo und Table entry is outside the DS segment limit.
If DS register contains a NULL segment selector.
#PF(fault code) If a page fault occurs.
1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enum er-
ated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Appendix E.3.1 of Intel® 64 and IA-32 Architectures Software 
Developer’s Manu al, Volume 1.BNDLDX—Load Extended Bounds Using Address TranslationINSTRUCTION SET REFERENCE, A-L
3-114 Vol. 2AVirtual-8086 Mode Exceptions
#BR If the bound directory entry is invalid.#UD If ModRM is RIP relative.
If ModRM.r/m and REX encodes BND4-B ND15 when Intel MPX is enabled.
#GP(0) If the memory address (A_BDE or A_BTE) is in a non-canonical form.
#PF(fault code) If a page fault occurs.BNDMK—Make BoundsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-115BNDMK—Make Bounds
Makes bounds from the second operand and stores the lo wer and upper bounds in the bound register bnd. The 
second operand must be a memory operand. The content of  the base register from the memory operand is stored 
in the lower bound bnd.LB. The 1's complement of the effe ctive address of m32/m64 is stored in the upper bound 
b.UB. Computation of m32/m64 has identical behavior to LEA.
This instruction does not cause any memory access, and does not read or write any flags. If the instruction did not specify base register, the lower bound will be zero. The reg-reg form of this instruction 
retains legacy behavior (NOP). 
The instruction causes an invalid-opcode exception (#UD) if executed in 64-bit mode with RIP-relative addressing.
Operation
BND.LB := SRCMEM.base;
IF 64-bit mode Then
BND.UB := NOT(LEA. 64_bits(SRCMEM)); 
ELSE
BND.UB := Zero_Extend.64_bit s(NOT(LEA.32_bits(SRCMEM)));
FI;
BNDMKvoid * _bnd_set_ptr_bounds(const void * q, size_t size); 
None.
If 16-bit addressing is used.Opcode/
F3 0F 1B /r
BNDMK bnd, m32RM N.E./V MPX Make lower and upper bounds from m32 and store them in bnd.
F3 0F 1B /r
BNDMK bnd, m64RM V/N.E. MPX Make lower and upper bounds from m64 and store them in bnd.
RM ModRM:reg (w) ModRM:r/m (r) N/ABNDMK—Make BoundsINSTRUCTION SET REFERENCE, A-L
3-116 Vol. 2AVirtual-8086 Mode Exceptions
If RIP-relative addressing is used.
#SS(0) If the memory address referencing the SS segment is in a non-canonical form.#GP(0) If the memory address is in a non-canonical form.
Same exceptions as in protected mode.BNDMOV—Move BoundsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-117BNDMOV—Move Bounds
BNDMOV moves a pair of lower and upper bound values fr om the source operand (the second operand) to the 
destination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction. 
The memory format for loading/store bounds in 64-bit mode is shown in Figure 3-5.
This instruction does not change flags.
Operation
BNDMOV register to register
DEST.LB := SRC.LB; DEST.UB := SRC.UB; Opcode/
66 0F 1A /r
BNDMOV bnd1, bnd2/m64RM N.E./V MPX Move lower and upper bound from bnd2/m64 to bound register 
bnd1.
66 0F 1A /r
BNDMOV bnd1, bnd2/m128RM V/N.E. MPX Move lower and upper bound from bnd2/m128 to bound register 
bnd1.
66 0F 1B /r
BNDMOV bnd1/m64, bnd2MR N.E./V MPX Move lower and upper bound from bnd2 to bnd1/m64.
66 0F 1B /r
BNDMOV bnd1/m128, bnd2MR V/N.E. MPX Move lower and upper bound from bnd2 to bound register 
bnd1/m128.
RM ModRM:reg (w) ModRM:r/m (r) N/AMR ModRM:r/m (w) ModRM:reg (r) N/A
Figure 3-5.  Memory Layout  of BNDMOV to/from MemoryUpper Bound (UB) Lower Bound (LB)
8 0 16 Byte offsetBNDMOV to memory in 64-bit mode
8 0 16 Byte offsetBNDMOV to memory in 32-bit mode
4BNDMOV—Move BoundsINSTRUCTION SET REFERENCE, A-L
3-118 Vol. 2ABNDMOV from memory
IF 64-bit mode THEN
DEST.LB := LOAD_QWORD(SRC); DEST.UB := LOAD_QWORD(SRC+8); 
ELSE
DEST.LB := LOAD_DWORD_ZERO_EXT(SRC); DEST.UB := LOAD_DWO RD_ZERO_EXT(SRC+4); 
FI;
BNDMOV to memory
DEST[63:0] := SRC.LB; DEST[127:64] := SRC.UB; 
ELSE
DEST[31:0] := SRC.LB; DEST[63:32] := SRC.UB; 
FI;
BNDMOV void * _bnd_copy_ptr_bounds(const void *q, const void *r)
None.
#SS(0) If the memory operand effective address is outside the SS segment limit.#GP(0) If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the destination operand points to a non-writable segment
If the DS, ES, FS, or GS segment register contains a NULL segment selector.
#AC(0) If alignment checking is enabled and an una ligned memory reference is made while CPL is 3.
#GP(0) If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS If the memory operand effective address is outside the SS segment limit.BNDMOV—Move BoundsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-119Virtual-8086 Mode Exceptions

#SS(0) If the memory operand effective ad dress is outside the SS segment limit.
#AC(0) If alignment checking is enabled and an un aligned memory reference is made while CPL is 3.
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#SS(0) If the memory address referencing th e SS segment is in a non-canonical form.
#PF(fault code) If a page fault occurs.BNDSTX—Store Extended Bounds Using Address TranslationINSTRUCTION SET REFERENCE, A-L
3-120 Vol. 2ABNDSTX—Store Extended Bounds  Using Address Translation
BNDSTX uses the linear address constructed from the displa cement and base register of the SIB-addressing form 
of the memory operand (mib) to perform address translatio n to store to a bound table entry. The bounds in the 
source operand bnd are written to the lower and upper bound s in the BTE. The content of the index register of mib 
is written to the pointer value field in the BTE. 
Operation
A_BDE[31:0] := (Zero_extend32(base[31:12] « 2) + (BNDCFG[31:12] «12 );A_BT[31:0] := LoadFrom(A_BDE);IF A_BT[0] equal 0 Then
FI;A_DEST[31:0] := (Zero_extend32(base[11:2] « 4) + (A_BT[31:2] « 2 ); // address of Bound table entryA_DEST[8][31:0] := ptr_value; 
A_DEST[0][31:0]  := BND.LB; 
A_DEST[4][31:0]  := BND.UB; Opcode/
NP 0F 1B /r
BNDSTX mib, bndMR V/V MPX Store the bounds in bnd and the pointer value in the index register 
of mib to a bound table entry (BTE ) with address translation using 
the base of mib.
MRSIB.base (r): Address of pointer
SIB.index(r)ModRM:reg (r) N/ABNDSTX—Store Extended Bounds Using Address TranslationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-121In 64-bit Mode
A_BDE[63:0] := (Zero_extend64(base[47+MAWA:20] « 3) + (BNDCFG[63:12] «12 );1
FI;A_DEST[63:0] := (Zero_extend64(base[19:3] « 5) + (A_BT[63:3] « 3 ); // addr ess of Bound table entry
A_DEST[16][63:0] := ptr_value; A_DEST[0][63:0]  := BND.LB; 
A_DEST[8][63:0]  := BND.UB; 
BNDSTX: _bnd_store_ptr_bounds(const void  **ptr_addr, const void *ptr_val); 
None.
Developer’s Manu al, Volume 1.BNDSTX—Store Extended Bounds Using Address TranslationINSTRUCTION SET REFERENCE, A-L
3-122 Vol. 2A64-Bit Mode Exceptions
#UD If ModRM is RIP relative.
#PF(fault code) If a page fault occurs.BOUND—Check Array Index Against BoundsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-123BOUND—Check Array Index Against Bounds
BOUND determines if the first operand (array index) is wi thin the bounds of an array specified the second operand 
(bounds operand). The array index is a signed integer located in a register. The bounds operand is a memory loca-tion that contains a pair of signed doubleword-integers (w hen the operand-size attribute is 32) or a pair of signed 
word-integers (when the operand-size attribute is 16). Th e first doubleword (or word) is the lower bound of the 
array and the second doubleword (or word) is the upper bo und of the array. The array index must be greater than 
or equal to the lower bound and less than or equal to the upper bound plus the operand size in bytes. If the index 
is not within bounds, a BOUND range exceeded exception (# BR) is signaled. When this exception is generated, the 
saved return instruction pointer points to the BOUND instruction.
The bounds limit data structure (two words or doublewords containing the lower and upper limits of the array) is 
usually placed just before the array itself, making the limit s addressable via a constant offset from the beginning of 
the array. Because the address of the array already will be  present in a register, this practice avoids extra bus 
cycles to obtain the effective address of the array bounds.
Operation
IF 64bit Mode
THEN
#UD;
ELSE
IF (ArrayIndex < LowerBound OR ArrayIndex > UpperBound) THEN
(* Below lower bound or above upper bound *)
IF <equation for PL enabled> THEN BNDSTATUS := 0#BR; 
FI;
FI;
None.Opcode Instruction Op/ 
En64-bit 
62 /r BOUND r16, m16&16 RM Invalid Valid Check if r16 (array index) is within bounds 
specified by m16&16.
62 /r BOUND r32, m32&32 RM Invalid Valid Check if r32 (array index) is within bounds 
specified by m32&32.
RM ModRM:reg (r) ModRM:r/m (r) N/A N/ABOUND—Check Array Index Against BoundsINSTRUCTION SET REFERENCE, A-L
3-124 Vol. 2AProtected Mode Exceptions
#BR If the bounds test fails.
#UD If second operand is not a memory location.
#BR If the bounds test fails.#UD If second operand is not a memory location.

#UD If in 64-bit mode.BSF—Bit Scan ForwardINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-125BSF—Bit Scan Forward
Searches the source operand (second operand) for the least si gnificant set bit (1 bit). If a least significant 1 bit is 
found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a 
memory location; the destination operand is a register. The bi t index is an unsigned offset from bit 0 of the source 
operand. If the content of the source operand is 0,  the content of the destination operand is undefined.
Operation
IF SRC = 0
THEN
ZF := 1;DEST is undefined;
ELSE
ZF := 0;temp := 0;WHILE Bit(SRC, temp) 
= 0
DO
temp := temp + 1;
OD;DEST := temp;
FI;
The ZF flag is set to 1 if the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF flags 
#UD If the LOCK prefix is used.Opcode Instruction Op/ 
En64-bit 
0F BC /r BSF r16, r/m16 RM Valid Va lid Bit scan forward on r/m16.
0F BC /r BSF r32, r/m32 RM Valid Va lid Bit scan forward on r/m32.
REX.W + 0F BC /r BSF r64, r/m64 RM Valid N.E. Bit scan forward on r/m64.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ABSF—Bit Scan ForwardINSTRUCTION SET REFERENCE, A-L
3-126 Vol. 2AReal-Address Mode Exceptions
#SS If a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#GP(0) If the memory address is in a non-canonical form.
#UD If the LOCK prefix is used.BSR—Bit Scan ReverseINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-127BSR—Bit Scan Reverse
Searches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is 
operand. If the content source operand is 0, th e content of the destination operand is undefined.
Operation
IF SRC = 0
THEN
ELSE
ZF := 0;temp := OperandSize – 1;WHILE Bit(SRC, temp) 
= 0
DO
temp := temp - 1;
FI;
En64-bit 
0F BD /r BSR r16, r/m16 RM Valid Valid Bit scan reverse on r/m16.
0F BD /r BSR r32, r/m32 RM Valid Valid Bit scan reverse on r/m32.REX.W + 0F BD /r BSR r64, r/m64 RM Valid N.E. Bit scan reverse on r/m64.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ABSR—Bit Scan ReverseINSTRUCTION SET REFERENCE, A-L
3-128 Vol. 2AReal-Address Mode Exceptions
#UD If the LOCK prefix is used.BSWAP—Byte SwapINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-129BSWAP—Byte Swap
Reverses the byte order of a 32-bit or 64-bit (destination) register. This instruction is provided for converting little-
endian values to big-endian format and vice versa. To sw ap bytes in a word value (16-bit register), use the XCHG 
instruction. When the BSWAP instruction referenc es a 16-bit register, the result is undefined.
IA-32 Architecture Le gacy Compatibility
The BSWAP instruction is not supported on IA-32 processors earlier than the Intel486™ processor family. For 
compatibility with this instruction, so ftware should include functionally equivalent code for execution on Intel 
processors earlier than the Intel486 processor family.
Operation
TEMP := DEST
IF 64-bit mode AND OperandSize = 64
THEN
DEST[7:0] := TEMP[63:56];
DEST[15:8] := TEMP[55:48];DEST[23:16] := TEMP[47:40];DEST[31:24] := TEMP[39:32];DEST[39:32] := TEMP[31:24];DEST[47:40] := TEMP[23:16];DEST[55:48] := TEMP[15:8];DEST[63:56] := TEMP[7:0];
ELSE
DEST[7:0] := TEMP[31:24];
DEST[15:8] := TEMP[23:16];DEST[23:16] := TEMP[15:8];DEST[31:24] := TEMP[7:0];
FI;
None.
En64-bit 
0F C8+ rd BSWAP r32 O Valid* Valid Reverses the byte order of a 32-bit register.
REX.W + 0F C8+ rd BSWAP r64 O Valid N.E. Reverses the byte order of a 64-bit register.
NOTES:
* See IA-32 Architecture Compatibility section below.
Oo p c o d e  +  r d  ( r ,  w ) N / A N / A N / ABT—Bit TestINSTRUCTION SET REFERENCE, A-L
3-130 Vol. 2ABT—Bit Test
Selects the bit in a bit string (specified with the first oper and, called the bit base) at the bit-position designated by 
the bit offset (specified by the second operand) and stores  the value of the bit in the CF flag. The bit base operand 
can be a register or a memory location; the bit offset operand can be a register or an immediate value:
•If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset 
operand (modulo size depends on the mode and register  size; 64-bit operands are available only in 64-bit

NOTES:
operand (modulo size depends on the mode and register  size; 64-bit operands are available only in 64-bit 
mode). 
•If the bit base operand specifies a memory location, the operand represents the address of the byte in memory 
that contains the bit base (bit 0 of the specified byte) of  the bit string. The range of the bit position that can be 
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11. 
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-
tion with the displacement field of the memory operand. In  this case, the low-order 3 or 5 bits (3 for 16-bit oper-
ands, 5 for 32-bit operands) of the immediate bit offset are stored in the immediate bit offset field, and the high-
order bits are shifted and combined with the byte displa cement in the addressing mode by the assembler. The 
processor will ignore the high or der bits if they are not zero.
When accessing a bit in memory, the processor may access 4 bytes starting from the memory address for a 32-bit 
operand size, using by the following relationship:
Effective Address + (4 ∗ (BitOffset DIV 32))
Or, it may access 2 bytes starting from the memory ad dress for a 16-bit operand, using this relationship:
Effective Address + (2 ∗ (BitOffset DIV 16))
It may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit 
addressing mechanism, software should avoid referencing ar eas of memory close to address space holes. In partic-
ular, it should avoid references to memory-mapped I/O registers. Instead, software should use the MOV instruc-
tions to load from or store to these addresses, and use the register form of these instructions to manipulate the data.
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit oper-
ands. See the summary chart at the beginning of  this section for encoding data and limits.
Operation
CF := Bit(BitBase, BitOffset);Opcode Instruction Op/ 
En64-bit 
0F A3 /r BT r/m16, r16 MR Valid Vali d Store selected bit in CF flag.
0F A3 /r BT r/m32, r32 MR Valid Vali d Store selected bit in CF flag.
REX.W + 0F A3 /r BT r/m64, r64 MR Valid N.E. Store selected bit in CF flag.
0F BA /4 ib BT r/m16, imm8 MI Valid V alid Store selected bit in CF flag.
0F BA /4 ib BT r/m32, imm8 MI Valid V alid Store selected bit in CF flag.
REX.W + 0F BA /4 ib BT r/m64, imm8 MI Va lid N.E. Store selected  bit in CF flag.
MR ModRM:r/m (r) ModRM:reg (r) N/A N/A
MI ModRM:r/m (r) imm8 N/A N/ABT—Bit TestINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-131Flags Affected
The CF flag contains the value of the selected bit. The ZF flag is unaffected. The OF, SF, AF, and PF flags are 
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#GP(0) If the memory address is in a non-canonical form.#PF(fault-code) If a page fault occurs.
#UD If the LOCK prefix is used.BTC—Bit Test and ComplementINSTRUCTION SET REFERENCE, A-L
3-132 Vol. 2ABTC—Bit Test and Complement
the bit offset operand (second operand), stores the value of the bit in the CF flag, and complements the selected 
bit in the bit string. The bit base operand can be a regist er or a memory location; the bit offset operand can be a 
register or an immediate value:
mode). This allows any bit position to be selected. 
tion with the displacement field of the memory operand. See “BT—Bit Test” in this chapter for more information on 
this addressing mechanism.
Operation
CF := Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) := NOT Bit(BitBase, BitOffset);
The CF flag contains the value of the selected bit before it is complemented. The ZF flag is unaffected. The OF, SF, 
AF, and PF flags are undefined.Opcode Instruction Op/ 
En64-bit 
0F BB /r BTC r/m16, r16 MR Valid Valid Store selected bit in CF flag and complement.
0F BB /r BTC r/m32, r32 MR Valid Valid Store selected bit in CF flag and complement.
REX.W + 0F BB /r BTC r/m64, r64 MR Valid N.E. Store selected bit in CF flag and complement.0F BA /7 ib BTC r/m16, imm8 MI Valid Valid Store selected bit in CF flag and complement.0F BA /7 ib BTC r/m32, imm8 MI Valid Valid Store selected bit in CF flag and complement.REX.W + 0F BA /7 ib BTC r/m64, imm8 MI Valid N.E. Store selected bit in CF flag and complement.
MI ModRM:r/m (r, w) imm8 N/A N/ABTC—Bit Test and ComplementINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-133Protected Mode Exceptions
#UD If the LOCK prefix is used but th e destination is not a memory operand.BTR—Bit Test and ResetINSTRUCTION SET REFERENCE, A-L
3-134 Vol. 2ABTR—Bit Test and Reset

the bit offset operand (second operand), stores the value of the bit in the CF flag, and clears the selected bit in the 
bit string to 0. The bit base operand can be a register or a memory location; the bit offset operand can be a register 
or an immediate value:
Operation
Bit(BitBase, BitOffset) := 0;
The CF flag contains the value of the selected bit before it  is cleared. The ZF flag is unaffected. The OF, SF, AF, and 
PF flags are undefined.Opcode Instruction Op/ 
En64-bit 
0F B3 /r BTR r/m16, r16 MR Valid Valid Sto re selected bit in CF flag and clear.
0F B3 /r BTR r/m32, r32 MR Valid Valid Sto re selected bit in CF flag and clear.
REX.W + 0F B3 /r BTR r/m64, r64 MR Valid N.E. Store selected bit in CF flag and clear.
0F BA /6 ib BTR r/m16, imm8 MI Valid Valid Store selected bit in CF flag and clear.
0F BA /6 ib BTR r/m32, imm8 MI Valid Valid Store selected bit in CF flag and clear.
REX.W + 0F BA /6 ib BTR r/m64, imm8 MI Valid N .E. Store selected bit in CF flag and clear.
MI ModRM:r/m (r, w) imm8 N/A N/ABTR—Bit Test and ResetINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-135Protected Mode Exceptions
#UD If the LOCK prefix is used but th e destination is not a memory operand.BTS—Bit Test and SetINSTRUCTION SET REFERENCE, A-L
3-136 Vol. 2ABTS—Bit Test and Set
the bit offset operand (second operand), stores the value of the bit in the CF flag, and sets the selected bit in the 
bit string to 1. The bit base operand can be a register or a memory location; the bit offset operand can be a register 
or an immediate value: 
mode). This allows any bit position to be selected.
Operation
Bit(BitBase, BitOffset) := 1;
The CF flag contains the value of the selected bit before it  is set. The ZF flag is unaffected. The OF, SF, AF, and PF 
flags are undefined.Opcode Instruction Op/ 
En64-bit 
0F AB /r BTS r/m16, r16 MR Valid Valid Sto re selected bit in  CF flag and set.
0F AB /r BTS r/m32, r32 MR Valid Valid Sto re selected bit in  CF flag and set.
REX.W + 0F AB /r BTS r/m64, r64 MR Valid N. E. Store selected bit in CF flag and set.
0F BA /5 ib BTS r/m16, imm8 MI Valid Valid Store selected bit in CF flag and set.
0F BA /5 ib BTS r/m32, imm8 MI Valid Valid Store selected bit in CF flag and set.
REX.W + 0F BA /5 ib BTS r/m6 4, imm8 MI Valid N.E. Store sele cted bit in CF flag and set.
MI ModRM:r/m (r, w) imm8 N/A N/ABTS—Bit Test and SetINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-137Protected Mode Exceptions
#SS If a memory operand effective address is outside the SS segment limit.#PF(fault-code) If a page fault occurs.
#UD If the LOCK prefix is used but th e destination is not a memory operand.BZHI—Zero High Bits Starting with Specified Bit PositionINSTRUCTION SET REFERENCE, A-L

3-138 Vol. 2ABZHI—Zero High Bits Starting with Specified Bit Position 
BZHI copies the bits of the first source operand (the second operand) into the destination operand (the first 
operand) and clears the higher bits in the destination a ccording to the INDEX value specified by the second source 
operand (the third operand). The INDEX is specified by bits  7:0 of the second source operand. The INDEX value is 
saturated at the value of OperandSize -1. CF is set, if the number contained in the 8 low bits of the third operand is 
greater than OperandSize -1.
Operation
N := SRC2[7:0]
DEST := SRC1IF (N < OperandSize)
DEST[OperandSize-1:N] := 0
FIIF (N > OperandSize - 1)
CF := 1
ELSE
CF := 0
FI
ZF and SF flags are updated based on the result. CF flag is  set as specified in the Operation section. OF flag is 
cleared. AF and PF flags are undefined.
BZHI unsigned __int32 _bzhi_u32(unsigned __int32 src, unsigned __int32 index);
BZHI unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);
None.
En64/32-
VEX.LZ.0F38.W0 F5 /r
BZHI r32a, r/m32, r32bRMV V/V BMI2 Zero bits in r/m32 starting with  the position in r32b, write result to 
r32a.
VEX.LZ.0F38.W1 F5 /r
BZHI r64a, r/m64, r64bRMV V/N.E. BMI2 Zero bits in r/m6 4 starting with the position  in r64b, write result to 
r64a.
RMV ModRM:reg (w) ModRM:r/m (r) VEX.vvvv (r) N/ACALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-139CALL—Call Procedure
Saves procedure linking information on the stack and branch es to the called procedure specified using the target 
operand. The target operand specifies the address of the fi rst instruction in the called procedure. The operand can 
be an immediate value, a general-purp ose register, or a memory location.
This instruction can be used to execute four types of calls:
•Near Call  —  A call to a procedure in the current code segm ent (the segment currently pointed to by the CS 
register), sometimes referred to as an intra-segment call.
•Far Call — A call to a procedure located in a different segment than the current code segment, sometimes 
referred to as an inter-segment call.
•Inter-privilege-level far call — A far call to a procedure in a segment at a different privilege level than that 
of the currently executing program or procedure.
•Task switch — A call to a procedure located in a different task.
The latter two call types (inter-privilege-level call and task  switch) can only be executed in protected mode. See 
“Calling Procedures Using Call an d RET” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, for additional information on near, fa r, and inter-privilege-level calls. See Chapter 8, “Task 
Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for information 
on performing task switches with the CALL instruction.Opcode Instruction Op/ 
En64-bit 
E8 cw CALL rel16 D N.S. Valid Ca ll near, relative, displace ment relative to next 
E8 cd CALL rel32 D Valid Valid Call near, rela tive, displacement relative to next 
instruction. 32-bit displace ment sign extended to 
64-bits in 64-bit mode.
FF /2 CALL r/m16 M N.E. Valid Call near, absolu te indirect, address given in r/m16. 
FF /2 CALL r/m32 M N.E. Valid Call near, absolu te indirect, address given in r/m32. 
FF /2 CALL r/m64 M Valid N.E. Call near, abso lute indirect, address given in r/m64.
9A cd CALL ptr16:16 D Invalid Valid Call far,  absolute, address given in operand.
9A cp CALL ptr16:32 D Invalid Valid Call far,  absolute, address given in operand.
FF /3 CALL m16:16 M Valid Valid Call far, abso lute indirect address given in m16:16.
In 32-bit mode: if selector points to a gate, then RIP 
= 32-bit zero extended displacement taken from 
gate; else RIP = zero exte nded 16-bit offset from 
far pointer referenced in the instruction.
FF /3 CALL m16:32 M Valid Valid In 64-bit mode: If  selector points to  a gate, then RIP 
= 64-bit displacement taken from gate; else RIP = 
zero extended 32-bit of fset from far pointer 
referenced in the instruction. 
REX.W FF /3 CALL m16:64 M Valid N.E. In 64-bit mode : If selector points to a gate, then RIP 
64-bit offset from far pointer referenced in the 
instruction. 
D Offset N/A N/A N/A
M ModRM:r/m (r) N/A N/A N/ACALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
3-140 Vol. 2ANear Call. When executing a near call, the processor pushes the value of the EIP register (which contains the offset 
of the instruction following the CALL instruction) on the stack (for use later as a return-instruction pointer). The processor then branches to the address in the current co de segment specified by the target operand. The target 
operand specifies either an absolute offset in the code se gment (an offset from the base of the code segment) or a 
relative offset (a signed displacement relative to the current value of the instruction pointer in the EIP register; this value points to the instruction following the CALL instru ction). The CS register is not changed on near calls.
For a near call absolute, an absolute offset is specified in directly in a general-purpose register or a memory location 
(r/m16 , r/m32, or r/m64 ). The operand-size attribute determines the size  of the target operand (16, 32 or 64 bits). 
When in 64-bit mode, the operand size for near call (and all near branches) is forced to 64-bits. Absolute offsets 
are loaded directly into the EIP(RIP) register. If the op erand size attribute is 16, the upper two bytes of the EIP 
register are cleared, resulting in a maximum instruction poin ter size of 16 bits. When accessing an absolute offset 
indirectly using the stack pointer [ESP] as the base register , the base value used is the value of the ESP before the 
instruction executes.
A relative offset ( rel16 or rel32) is generally specified as a label in assemb ly code. But at the machine code level, it 
is encoded as a signed, 16- or 32-bit immediate value. This value is added to the value in the EIP(RIP) register. In 
64-bit mode the relative offset is always a 32-bit immediate value which is sign extended to 64-bits before it is 
added to the value in the RIP register for the target calculat ion. As with absolute offsets, the operand-size attribute 
determines the size of the target operand (16, 32, or 64 bi ts). In 64-bit mode the target operand will always be 64-
bits because the operand size is forced to 64-bits for near branches.
Far Calls in Real-Address or Virtual-8086 Mode.  When executing a far call in real- address or virtual-8086 mode, the 
processor pushes the current value of both the CS and EI P registers on the stack for use as a return-instruction 
pointer. The processor then performs a “far branch” to the code segment and offset specified with the target 
operand for the called procedure. The target operand specifie s an absolute far address either directly with a pointer 
(ptr16:16  or ptr16:32 ) or indirectly with a memory location ( m16:16  or m16:32 ). With the pointer method, the 
segment and offset of the called procedure is encoded in the instruction using a 4-byte (16-bit operand size) or 6-
byte (32-bit operand size) far address immediate. With th e indirect method, the target  operand specifies a memory 
location that contains a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address. The operand-size 
attribute determines the size of the offset (16 or 32 bits) in  the far address. The far address is loaded directly into 
the CS and EIP registers. If the operand-size attribute is  16, the upper two bytes of the EIP register are cleared.
Far Calls in Protected Mode.  When the processor is operating in protecte d mode, the CALL instruction can be used to 
perform the following types of far calls:
•Far call to the same privilege level
•Far call to a different privilege level (inter-privilege level call)
•Task switch (far call to another task)
In protected mode, the processor always uses the segment selector part of the far address to access the corre-
sponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access 
rights determine the type of ca ll operation to be performed.

If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is 
performed. (If the selected code segment is at a differen t privilege level and the code segment is non-conforming, 
a general-protection exception is generated.) A far call to the same privilege level in protected mode is very similar 
to one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far address either 
directly with a pointer ( ptr16:16  or ptr16:32 ) or indirectly with a memory location ( m16:16  or m16:32 ). The 
operand- size attribute determines the size of the offset  (16 or 32 bits) in the far address. The new code segment 
selector and its descriptor are loaded into CS register; the o ffset from the instruction is loaded into the EIP register. 
A call gate (described in the next paragraph) can also be  used to perform a far call to a code segment at the same 
privilege level. Using this mechanism pr ovides an extra level of indirection an d is the preferred method of making 
calls between 16-bit and 32-bit code segments.
When executing an inter-privilege-level far call, the code  segment for the procedure being called must be accessed 
through a call gate. The segment selector specified by th e target operand identifies the call gate. The target 
operand can specify the call gate segment selector either directly with a pointer ( ptr16:16  or ptr16:32 ) or indirectly 
with a memory location ( m16:16  or m16:32 ). The processor obtains the segment selector for the new code 
segment and the new instruction pointer (offset) from the ca ll gate descriptor. (The offs et from the target operand 
is ignored when a call gate is used.) CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-141On inter-privilege-level calls, the processor switches to th e stack for the privilege level of the called procedure. The 
segment selector for the new stack segment is specified in  the TSS for the currently running task. The branch to 
the new code segment occurs after the stack switch. (Note that when using a call gate to perform a far call to a 
segment at the same privilege level, no  stack switch occurs.) On the new stack, the processor pushes the segment 
selector and stack pointer for the calling procedure’s stack,  an optional set of parameters from the calling proce-
dures stack, and the segment selector and instruction poin ter for the calling procedure’s code segment. (A value in 
the call gate descriptor determines how many parameters  to copy to the new stack.) Finally, the processor 
branches to the address of the procedure being called within the new code segment.
Executing a task switch with the CALL instruction is similar to executing a call through a call gate. The target 
operand specifies the segment selector of  the task gate for the new task activated by the switch (the offset in the 
target operand is ignored). The task ga te in turn points to the TSS for the new task, which contains the segment 
selectors for the task’s code and stack segments. Note that  the TSS also contains the EIP value for the next instruc-
tion that was to be executed before the calling task was su spended. This instruction pointer value is loaded into the 
EIP register to re-start the calling task. 
The CALL instruction can also specify the segment selector of the TSS directly, which eliminates the indirection of 
the task gate. See Chapter 8, “T ask Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A, for information on  the mechanics of a task switch.
When you execute at task switch with a CALL instruction, the nested task flag (NT) is set in the EFLAGS register 
and the new TSS’s previous task link field is loaded with the old task’s TSS selector. Code is expected to suspend 
this nested task by executing an IRET instruction which, be cause the NT flag is set, automatically uses the previous 
task link to return to the calling task. (See  “Task Linking” in Chapter 8 of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3A , for information on nested tasks.) Switching tasks with the CALL instruc-
tion differs in this regard from JMP instruction. JMP does not set the NT flag and therefore does not expect an IRET 
instruction to suspend the task.
Mixing 16-Bit and 32-Bit Calls.  When making far calls between 16-bit and 32-bit code segments, use a call gate. If 
the far call is from a 32-bit code segment to a 16-bit code segment, the call should be made from the first 64 
KBytes of the 32-bit code segment. This is because the oper and-size attribute of the instruction is set to 16, so only 
a 16-bit return address offset can be saved. Also, the call should be made using a 16-bit call gate so that 16-bit 
values can be pushed on the stack. See Chapter 22,  “Mixing 16-Bit and 32-Bit Code,” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 3B, for more information.
Far Calls in Compatibility Mode.  When the processor is operating in compat ibility mode, the CALL instruction can be 
used to perform the following types of far calls:
•Far call to the same privilege leve l, remaining in compatibility mode
•Far call to the same privilege level, transitioning to 64-bit mode
•Far call to a different privilege level (inter-priv ilege level call), transitioning to 64-bit mode
Note that a CALL instruction can not be used to cause a task switch in compatibility mode since task switches are 
not supported in IA-32e mode.
In compatibility mode, the processor always uses the segm ent selector part of the far address to access the corre-
sponding descriptor in the GDT or LDT. The descriptor ty pe (code segment, call gate) and access rights determine 
the type of call operation to be performed.
performed. (If the selected code segment is at a different  privilege level and the code segment is non-conforming, 
a general-protection exception is generated.) A far call to the same privilege level in compatibility mode is very 
similar to one carried out in protected mode. The target op erand specifies an absolute far address either directly 
with a pointer ( ptr16:16  or ptr16:32 ) or indirectly with a memory location ( m16:16  or m16:32 ). The operand-size 
attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment selector and its 
descriptor are loaded into CS register an d the offset from the instruction is loaded into the EIP register. The differ-
ence is that 64-bit mode may be entered. This spec ified by the L bit in the new code segment descriptor.
Note that a 64-bit call gate (described in the next para graph) can also be used to perform a far call to a code 
segment at the same privilege level. However, using th is mechanism requires that the target code segment 
descriptor have the L bit set, causing an entry to 64-bit mode.
When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed 
through a 64-bit call gate. The segment selector specified by the target operand identifies the call gate. The target CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
3-142 Vol. 2Aoperand can specify the call gate segment selector either directly with a pointer ( ptr16:16  or ptr16:32 ) or indirectly 
segment and the new instruction pointer (offset) from the 16 -byte call gate descriptor. (The offset from the target 
operand is ignored when a call gate is used.) 
On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The 
segment selector for the new stack segment is set to NULL . The new stack pointer is specified in the TSS for the 
currently running task. The branch to the new code segmen t occurs after the stack switch. (Note that when using 
a call gate to perform a far call to a segment at the same priv ilege level, an implicit stack switch occurs as a result 
of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use a segment base of 0x0, the 
limit is ignored, and the default stack size is 64-bits. The full value of RSP is used for the offset, of which the upper 
32-bits are undefined.) On the new stack, the processor pushes the segment selector and stack pointer for the 
calling procedure’s stack and the segment selector and instruction pointer for the calling procedure’s code 
segment. (Parameter copy is not supported in IA-32e mode .) Finally, the processor branches to the address of the 
procedure being called within the new code segment.
Near/(Far) Calls in 64-bit Mode.  When the processor is operating in 64-bit mode, the CALL instruction can be used to 

•Far call to the same privilege level, transitioning to compatibility mode
•Far call to the same privilege level, remaining in 64-bit mode
•Far call to a different privilege level (inter-pri vilege level call), remaining in 64-bit mode
Note that in this mode the CALL instruction can not be used to cause a task switch in 64-bit mode since task 
switches are not supported in IA-32e mode.
In 64-bit mode, the processor always uses the segment sele ctor part of the far address to access the corresponding 
descriptor in the GDT or LDT. The descriptor type (code se gment, call gate) and access rights determine the type of 
call operation to be performed.
a general-protection exception is generated.) A far call to the same privilege level in 64-bit mode is very similar to 
one carried out in compatibility mode. The target operan d specifies an absolute far address indirectly with a 
memory location ( m16:16, m16:32  or m16:64 ). The form of CALL with a direct specification of absolute far address 
is not defined in 64-bit mode. The operand-size attribute determ ines the size of the offset (16, 32, or 64 bits) in the 
far address. The new code segment selector and its descripto r are loaded into the CS register; the offset from the 
instruction is loaded into the EIP register. The new code segment may specify entry either into compatibility or 64-bit mode, based on the L bit value.
A 64-bit call gate (described in the next paragraph) can also be used to perform a far call to a code segment at the 
same privilege level. However, using this mechanism requ ires that the target code segment descriptor have the L 
bit set.
through a 64-bit call gate. The segment selector specified by  the target operand identifies the call gate. The target 
operand can only specify the call gate segment se lector indirectly with a memory location ( m16:16, m16:32  or 
m16:64 ). The processor obtains the segment selector for th e new code segment and the new instruction pointer 
(offset) from the 16-byte call gate de scriptor. (The offset from the target operand is ignored when a call gate is 
used.)
currently running task. The branch to the new code segment occurs after the stack switch. 
Note that when using a call gate to perform a far call to a segment at the same privilege level, an implicit stack 
switch occurs as a result of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use a 
segment base of 0x0, the limit is ignored, and the default st ack size is 64-bits. (The full value of RSP is used for the 
offset.) On the new stack, the processor pushes the segm ent selector and stack pointer for the calling procedure’s 
stack and the segment selector and instruction pointer for the calling procedure’s code segment. (Parameter copy 
is not supported in IA-32e mode.) Finally, the processo r branches to the address of the procedure being called 
within the new code segment.CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-143Refer to Chapter 6, “Procedure Call s, Interrupts, and Exceptions‚” and Chapter 17, “Control-flow Enforcement 
Technology (CET)‚” in the Intel® 64 and IA-32 Architectures Software De veloper’s Manual, Volume 1, for CET 
details.
Instruction ordering.  Instructions following a far call may be fetc hed from memory before earlier instructions 
complete execution, but they will not execute (even specul atively) until all instructions prior to the far call have 
completed execution (the later instructions may execute before data stored by the earlier instructions have 
become globally visible).
Instructions sequentially following a near indirect CALL in struction (i.e., those not at the target) may be executed 
speculatively. If software needs to prevent this (e.g., in order to prevent a speculative execution side channel), then an LFENCE instruction opcode can be placed after th e near indirect CALL in order to block speculative execu-
tion.
Operation
IF near call
THEN IF near relative call
THEN 
IF OperandSize = 64
THEN
tempDEST := SignExtend(DES T); (* DEST is rel32 *) 
tempRIP := RIP + tempDEST;
IF stack not large enough for a 8-byte return address
THEN #SS(0); FI;
Push(RIP);IF ShadowStackEnabled(CPL) AND DEST != 0
ShadowStackPush8B(RIP);
FI;RIP := tempRIP;
FI;IF OperandSize 
= 32
THEN
tempEIP := EIP + DEST; (* DEST is rel32  *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
IF stack not large enough for a 4-byte return address
Push(EIP);IF ShadowStackEnabled(CPL) AND DEST != 0
ShadowStackPush4B(EIP);
FI;EIP := tempEIP;
FI;IF OperandSize = 16
THEN
tempEIP := (EIP + DEST) AND 0000FFFFH; (* DEST is rel16  *)
IF stack not large enough for a 2-byte return address 
Push(IP);IF ShadowStackEnabled(CPL) AND DEST != 0
(* IP is zero extended and pushed as a 32 bit value on shadow stack *)
ShadowStackPush4B(IP);
FI;
ELSE (* Near absolute call *)CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
3-144 Vol. 2AIF OperandSize = 64
THEN
tempRIP := DEST; (* DEST is r/m64  *)
IF stack not large enough for a 8-byte return address 
Push(RIP); IF ShadowStackEnabled(CPL)
= 32
THEN
tempEIP := DEST; (* DEST is r/m32  *)
IF stack not large enough for a 4-byte return address 
Push(EIP); IF ShadowStackEnabled(CPL)
= 16
THEN
tempEIP := DEST AND 0000FFFFH; (* DEST is r/m16  *)
Push(IP);IF ShadowStackEnabled(CPL)
FI;
FI;rel/absIF (Call near indirect , absolute indirect)
IF EndbranchEnabledAndNotSuppressed(CPL)
IF CPL = 3
THEN
IF ( no 3EH prefix OR IA32 _U_CET.NO_TRACK_EN == 0 )
THEN
IA32_U_CET.TRACKER = WAIT_FOR_ENDBRANCH
FI;
ELSE
IF ( no 3EH prefix OR IA32 _S_CET.NO_TRACK_EN == 0 )
THEN
IA32_S_CET.TRACKER = WAIT_FOR_ENDBRANCH
FI;
FI;
FI;
FI;
FI; nearCALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-145IF far call and (PE = 0 or (PE = 1 and VM = 1)) (* Real-address or  virtual-8086 mode *)
THEN
IF OperandSize  = 32
THEN
IF stack not large enough for a 6-byte return address 
IF DEST[31:16] is not zero THEN #GP(0); FI;Push(CS); (* Padded with 16 high-order bits *)Push(EIP);CS := DEST[47:32]; (* DEST is ptr16:32  or [m16:32 ] *)
EIP := DEST[31:0]; (* DEST is ptr16:32  or [m16:32 ] *)
ELSE (* OperandSize
 = 16 *)
Push(CS);Push(IP);CS := DEST[31:16]; (* DEST is ptr16:16  or [m16:16 ] *)
EIP := DEST[15:0]; (* DEST is ptr16:16  or [m16:16 ]; clear upper 16 bits *)
FI;
FI;
IF far call and (PE 
= 1 and VM = 0) (* Protected mode or IA-32e Mode, not virtual-8086 mode*)
THEN
IF segment selector in target operand NULL 
THEN #GP(0); FI;
IF segment selector index not within descriptor table limits
THEN #GP(new code se gment selector); FI;
Read type and access rights of selected segment descriptor;IF IA32_EFER.LMA = 0
THEN
IF segment type is not a conforming or nonconfo rming code segment, call 
gate, task gate, or TSS 
THEN #GP(segment selector); FI;
ELSE 
IF segment type is not a conforming or nonconforming code segment or 64-bit call gate, 
FI;Depending on type and access rights:
GO TO CONFORMING-CODE-SEGMENT;GO TO NONCONFORM ING-CODE-SEGMENT;
GO TO CALL-GATE;GO TO TASK-GATE;GO TO TASK-STATE-SEGMENT;
FI;
CONFORMING-CODE-SEGMENT:
IF L bit 
= 1 and D bit = 1 and IA32_EFER.LMA = 1 
THEN GP(new code se gment selector); FI;
IF DPL > CPL 
IF segment not present 
THEN #NP(new code segment selector); FI;CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
3-146 Vol. 2AIF stack not large enough for return address
tempEIP := DEST(Offset);IF target mode = Compatibility mode
    THEN tempEIP := tempEIP AND 00000000_FFFFFFFFH; FI;
IF OperandSize
 = 16
THEN
tempEIP := tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)
IF (IA32_EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code segment limit) 
IF tempEIP is non-canonical 
IF ShadowStackEnabled(CPL)

FI;
IF L bit 
IF DPL > CPL 
 = 16
THEN
IF OperandSize = 32
THEN
tempPushLIP = CSBASE + EIP;
ELSE
IF OperandSize = 16
THEN
tempPushLIP = CSBASE + IP;
ELSE (* OperandSize = 64 *)
tempPushLIP = RIP;
FI;
FI;tempPushCS = CS;
= 32
THEN
Push(CS); (* Padded with 16 high-order bits *)Push(EIP);CS := DEST(CodeSegmentSelector); (* Segment descriptor information also loaded *)CS(RPL) := CPL;EIP := tempEIP;
ELSE
IF OperandSize 
= 16
THEN
Push(CS);Push(IP);CS := DEST(CodeSegmentSelector); (* Segment descriptor information also loaded *)CS(RPL) := CPL;EIP := tempEIP;
ELSE (* OperandSize 
= 64 *)
Push(CS); (* Padded with 48 high-order bits *)Push(RIP);CS := DEST(CodeSegmentSelector); (* Segment descriptor information also loaded *)CS(RPL) := CPL;RIP := tempEIP;
FI;
FI;IF ShadowStackEnabled(CPL)
IF (IA32_EFER.LMA and DEST(CodeSegmentSelector).L) = 0CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-147(* If target is legacy or compatibility mode then the SSP mu st be in low 4GB *)
IF (SSP & 0xFFFFFFFF00000000 != 0)
FI;(* align to 8 byte boundary if not already aligned *)tempSSP = SSP;Shadow_stack_store 4 by tes of 0 to (SSP – 4)
SSP = SSP & 0xFFFFFFFFFFFFFFF8HShadowStackPush8B(tempPushCS); (* Padd ed with 48 high-o rder bits of 0 *)
ShadowStackPush8B(tempPushLIP); (* Padded with 32 high-order bits of 0 for 32 bit LIP*)ShadowStackPush8B(tempSSP);
FI;IF EndbranchEnabled(CPL)
IF CPL = 3
THEN
IA32_U_CET.SUPPRESS = 0
ELSE
IA32_S_CET.SUPPRESS = 0
FI;
FI;
END;
NONCONFORMING-CODE-SEGMENT:
IF L-Bit
 = 1 and D-BIT = 1 and IA32_EFER.LMA = 1 
IF (RPL > CPL) or (DPL  ≠ CPL) 
THEN #NP(new code segment selector); FI;
IF stack not large enough for return address 
= 16
THEN tempEIP := tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)
IF (IA32_EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code segment limit)
IF IA32_EFER.LMA & CS.L
        tempPushLIP = RIP    ELSE        tempPu shLIP = CSBASE + EIP;
    FI;
tempPushCS = CS;
= 32
THEN
Push(CS); (* Padded with 16 high-order bits *)Push(EIP);CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
3-148 Vol. 2ACS := DEST(CodeSegmentSelector); 
(* Segment descriptor information also loaded *)CS(RPL) := CPL;EIP := tempEIP;
ELSE
THEN
FI;
IF (IA32_EFER.LMA and DEST(CodeSegmentSelector).L) = 0
(* If target is legacy or compatibility mode then the SSP mu st be in low 4GB *)
FI;
(* align to 8 byte boundary  if not already aligned *)
tempSSP = SSP;Shadow_stack_store 4 bytes of 0 to (SSP – 4)SSP = SSP & 0xFFFFFFFFFFFFFFF8HShadowStackPush8B(tempPushCS); (* Padded with 48 high-order 0 bits *)ShadowStackPush8B(tempPushLIP); (* Padded 32 high-order bits of 0 for 32 bit LIP*)ShadowStackPush8B(tempSSP);FI;IF EndbranchEnabled(CPL)
IF CPL = 3
THEN
IA32_U_CET.TRACKER = WAIT_FOR_ENDBRANCHIA32_U_CET.SUPPRESS = 0
ELSE
FI;
FI;
END;
CALL-GATE:
IF call gate (DPL < CPL) or (RPL > DPL)
THEN #GP(call-gate selector); FI;
IF call gate not present 
THEN #NP(call-gate selector); FI;
IF call-gate code-segme nt selector is NULLCALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-149THEN #GP(0); FI;
IF call-gate code-segment selector index is outside descriptor table limits
THEN #GP(call-gate code-s egment selector); FI;
Read call-gate code-segment descriptor;IF call-gate code-segment descriptor  does not indicate a code segment
or call-gate code-seg ment descriptor DPL > CPL 
IF IA32_EFER.LMA = 1 AND (call-ga te code-segment descriptor is 
not a 64-bit code segment or ca ll-gate code-segment descriptor has both L-bit and D-bit set)
IF call-gate code segment not present 
THEN #NP(call-gate code-s egment selector); FI;
IF call-gate code segment is non-conforming and DPL < CPL
THEN go to MORE-PRIVILEGE;ELSE go to SAME-PRIVILEGE;
FI;
END;
MORE-PRIVILEGE:
IF current TSS is 32-bit
THEN 
TSSstackAddress := (n ew code-segment DPL ∗ 8) + 4;
IF (TSSstackAddress + 5) > current TSS limit
THEN #TS(current TSS selector); FI;
NewSS := 2 bytes loaded from (TSS base + TSSstackAddress + 4);
NewESP := 4 bytes loaded from (TSS base + TSSstackAddress);
ELSE 
IF current TSS is 16-bit
THEN
TSSstackAddress := (n ew code-segment DPL ∗ 4) + 2
IF (TSSstackAddress + 3) > current TSS limit
NewSS := 2 bytes loaded from (TSS base + TSSstackAddress + 2);
NewESP := 2 bytes loaded from (TSS base + TSSstackAddress);
ELSE (* current TSS is 64-bit *)
IF (TSSstackAddress + 7) > current TSS limit
NewSS := new code-segment DPL; (* NULL selector with RPL = new CPL *)NewRSP := 8 bytes loaded from (current TSS base + TSSstackAddress);
FI;
FI;IF IA32_EFER.LMA = 0 and NewSS is NULL
THEN #TS(NewSS); FI;
Read new stack-se gment descriptor; 
IF IA32_EFER.LMA = 0 and (NewSS RPL 
≠ new code-segment DPL
or new stack-segment DPL ≠ new code-segment DPL or new stack segment is not a
writable data segment)
THEN #TS(NewSS); FI
IF IA32_EFER.LMA = 0 and new stack segment not present 
THEN #SS(NewSS); FI;
IF CallGateSize = 32
THEN
IF new stack does not have room  for parameters plus 16 bytesCALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
3-150 Vol. 2ATHEN #SS(NewSS); FI;
IF CallGate(InstructionPointer) not within new code-segment limit 
SS := newSS; (* Segment descriptor information also loaded *)ESP := newESP; CS:EIP := CallGate(CS:InstructionPointer); (* Segment descriptor information also loaded *)Push(oldSS:oldESP); (* Fr om calling procedure *)
temp := parameter co unt from call gate, masked to 5 bits;
Push(parameters from calling procedure’s stack, temp)Push(oldCS:oldEIP); (* Return address to calling procedure *)
ELSE 
IF CallGateSize = 16
THEN
IF new stack does not have room for parameters plus 8 bytes
IF (CallGate(InstructionPointer) AND FFFFH) not in new code-segment limit
SS := newSS; (* Segment descriptor information also loaded *)ESP := newESP; CS:IP := CallGate(CS:InstructionPointer);(* Segment descriptor information also loaded *)Push(oldSS:oldESP); (* Fr om calling procedure *)
ELSE (* CallGateSize = 64 *)
IF pushing 32 bytes on the stack would use a non-canonical address
IF (CallGate(InstructionPointer) is non-canonical) 
SS := NewSS; (* NewSS is NULL)RSP := NewESP; CS:IP := CallGate(CS:InstructionPointer);(* Segment descriptor information also loaded *)Push(oldSS:oldESP); (* Fr om calling procedure *)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
FI;
FI;IF ShadowStackEnabled(CPL) AND CPL = 3
THEN
IF IA32_EFER.LMA = 0
THEN IA32_PL3_SSP := SSP;ELSE (* adjust so bits 63:N get the value of bit N–1,  where N is the CPU’s maximum linear-address width *)
IA32_PL3_SSP := LA_adjust(SSP);
FI;
FI;CPL := CodeSegment(DPL)CS(RPL) := CPLIF ShadowStackEnabled(CPL)
oldSSP := SSPSSP := IA32_PLi_SSP; (* where i is the CPL *)IF SSP & 0x07 != 0 (* if SSP not aligned to 8 bytes then #GP *)
THEN #GP(0); FI;CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-151(* Token and CS:LIP:oldSSP pushed on  shadow stack must be contained in a naturally aligned 32-byte region*)
IF (SSP & ~0x1F) != ((SSP – 24) & ~0x1F)
#GP(0); FI;
IF ((IA32_EFER.LMA and CS.L) = 0 AND SSP[63:32] != 0)
expected_token_value = SSP (* busy bit - bit position 0 - must be clear *)new_token_value = SSP | BUSY_BIT    (* Set the busy bit *)
IF shadow_stack_lock_cmpx chg8b(SSP, new_token_value, expected_token_value) != expected_token_value
IF oldSS.DPL != 3
ShadowStackPush8B(o ldCS); (* Padded with 48 high-order bits of 0 *)
ShadowStackPush8B(oldCSBASE+oldRIP); (* Padded with 32 high-order bits of 0 for 32 bit LIP*)ShadowStackPush8B(oldSSP);
FI;
FI;IF EndbranchEnabled (CPL)
FI;
END;
SAME-PRIVILEGE:
THEN

FI;
FI;
END;
THEN
IF stack does not have room for 8 bytes
IF CallGate(Instructio nPointer) not within code segment limit 
CS:EIP := CallGate(CS:EIP) (* Segment descriptor information also loaded *)Push(oldCS:oldEIP); (* Return address to calling procedure *)
ELSE 
If CallGateSize 
= 16
THEN
IF stack does not have room for 4 bytes
CS:IP := CallGate(CS:i nstruction pointer); 
(* Segment descriptor information also loaded *)Push(oldCS:oldIP); (* Return address to calling procedure *)
ELSE (* CallGateSize = 64)
IF pushing 16 bytes on the stac k touches non-canonical addresses
IF RIP non-canonical 
FI;
FI;CS(RPL) := CPLIF ShadowStackEnabled(CPL)
(* Align to next 8 byte boundary *)tempSSP = SSP;CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
3-152 Vol. 2AShadow_stack_store 4 bytes of 0 to (SSP – 4)
SSP = SSP & 0xFFFFFFFFFFFFFFF8H;(* push cs:lip:ssp on shadow stack *)ShadowStackPush8B(oldCS); (* Padded with 48 high-order bits of 0 *)ShadowStackPush8B(oldCSBASE + oldRIP); (* Padded with 32 high-order bits of 0 for 32 bit LIP*)
ShadowStackPush8B(tempSSP);
IF CPL = 3
THEN
IA32_U_CET.TRACKER = WAIT_FOR_ENDBRANCH;IA32_U_CET.SUPPRESS = 0
ELSE
IA32_S_CET.TRACKER = WAIT_FOR_ENDBRANCH;
FI;
FI;
END;
TASK-GATE:
IF task gate DPL < CPL or RPL 
THEN #GP(task gate selector); FI;
IF task gate not present 
THEN #NP(task gate selector); FI;
Read the TSS segment selector in the task-gate descriptor;IF TSS segment select or local/global bit is set to local
or index not within GDT limits
THEN #GP(TSS selector); FI;
Access TSS descriptor in GDT;IF descriptor is not a TSS segment
              THEN #GP(TSS selector); FI;
IF TSS descriptor specif ies that the TSS is busy
IF TSS not present 
THEN #NP(TSS selector); FI;
SWITCH-TASKS (with nesting) to TSS;IF EIP not within code segment limit 
END;
TASK-STATE-SEGMENT:
IF TSS DPL < CPL or RPL
or TSS descriptor indicates TSS not available
IF TSS is not present 
END;
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-153Protected Mode Exceptions
#GP(0) If the target offset in destination op erand is beyond the new code segment limit.
If the segment selector in th e destination operand is NULL.
If the code segment selector in the gate is NULL.
selector.
If target mode is compatibility mode and SSP is not in low 4GB.
If SSP in IA32_PLi_SSP (where i is the new CPL) is not 8 byte aligned.
If the token and the stack frame to be pushed on  shadow stack are not contained in a naturally 
aligned 32-byte region of the shadow stack.
If “supervisor Shadow Stack” token on new shadow stack is marked busy.If destination mode is 32-bit or compatibility mode, but SSP address in “supervisor shadow 
stack” token is beyond 4GB.
If SSP address in “supervisor shadow stack” token does not match SSP address in 
IA32_PLi_SSP (where i is the new CPL).
#GP(selector) If a code segment or gate or TSS selector index is outside descriptor table limits. 
If the segment descriptor pointed to by the segment selector in the destination operand is not 
for a conforming-code segment, nonconforming-co de segment, call gate, task gate, or task 
state segment.
If the DPL for a nonconforming-code segment is not equal to the CPL or the RPL for the 
segment’s segment selector is greater than the CPL.
If the DPL for a conforming-code segment is greater than the CPL.If the DPL from a call-gate, task-gate, or TSS segment descriptor is less than the CPL or than 
the RPL of the call-gate, task-gate, or TSS’s segment selector.
If the segment descriptor for a segment selector from a call gate does not indicate it is a code 
segment.
If the segment selector from a call ga te is beyond the descriptor table limits.
If the DPL for a code-segment obtained from a call gate is greater than the CPL.If the segment selector for a TSS has its local/global bit set for local.
If a TSS segment descriptor specifies that the TSS is busy or not available.
#SS(0) If pushing the return address, parameters, or stack segment pointer onto the stack exceeds 
the bounds of the stack segment, when no stack switch occurs.
If a memory operand effective address is outside the SS segment limit.
#SS(selector) If pushing the return address, paramete rs, or stack segment pointer onto the stack exceeds 
the bounds of the stack segment, when a stack switch occurs.
If the SS register is being loaded as part of  a stack switch and the segment pointed to is 
marked not present.
If stack segment does not have room for the return address, parameters, or stack segment 
pointer, when stack switch occurs.
#NP(selector) If a code segment, data segment, call gate, task gate, or TSS is not present.CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
3-154 Vol. 2A#TS(selector) If the new stack segment selector and ESP are beyond the end of the TSS.
If the new stack segment selector is NULL.If the RPL of the new stack segment selector in  the TSS is not equal to the DPL of the code 
segment being accessed.
If DPL of the stack segment descriptor for the ne w stack segment is not equal to the DPL of the 
code segment descriptor.
If the new stack segment is not a writable data segment.
If segment-selector index for stack segment is outside descriptor table limits. 
If the target offset is beyond the code segment limit.
Same exceptions as in protected mode.#GP(selector) If a memory address accessed by the selector is in non-canonical space.#GP(0) If the target offset in the destination operand is non-canonical.
#GP(0) If a memory address is non-canonical.
If target offset in destination operand is non-canonical.If the segment selector in th e destination operand is NULL.
If the code segment selector in the 64-bit gate is NULL.
If target mode is compatibility mode and SSP is not in low 4GB.If SSP in IA32_PLi_SSP (where i is the new CPL) is not 8 byte aligned.
If “supervisor Shadow Stack” token on new shadow stack is marked busy.
If destination mode is 32-bit mode or compat ibility mode, but SSP address in “super-visor 
shadow” stack token is beyond 4GB.
IA32_PLi_SSP (where i is the new CPL).CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-155#GP(selector) If code segment or 64-bit call  gate is outside descriptor table limits. 
If code segment or 64-bit call gate overlaps non-canonical space. If the segment descriptor pointed to by the segment selector in the destination operand is not 
for a conforming-code segment, nonconform ing-code segment, or 64-bit call gate.
If the segment descriptor pointed to by the segm ent selector in the destination operand is a 
code segment and has both the D-bit and the L- bit set.
If the DPL for a nonconforming-code segment is  not equal to the CPL, or the RPL for the 
If the DPL for a conforming-code segment is greater than the CPL.
If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.
If the upper type field of a 64-bit call gate is not 0x0.If the segment selector from a 64-bit call gate is beyond the descriptor table limits.
If the DPL for a code-segment obtained from a 64-bit call gate is greater than the CPL.
If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the 
L-bit set and the D-bit clear.

If the segment descriptor for a segment selector from the 64-bit call gate does not indicate it 
is a code segment. 
#SS(0) If pushing the return offset or CS selector onto the stack exceeds the bounds of the stack 
segment when no stack switch occurs.
If the stack address is in a non-canonical form.
#SS(selector) If pushing the old values of SS selector, stack pointer, EFLAGS, CS selector, offset, or error 
code onto the stack violates the canonical boundary when a stack switch occurs.
#NP(selector) If a code segment or 64-bit call gate is not present.
#TS(selector) If the load of the ne w RSP exceeds the limit of the TSS.
#UD (64-bit mode only) If a far call is direct to an absolute address in memory.
current privilege level is 3.CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to QuadwordINSTRUCTION SET REFERENCE, A-L
3-156 Vol. 2ACBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to 
Quadword
Double the size of the source operand by means of sign  extension. The CBW (convert  byte to word) instruction 
copies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to double-
word) instruction copies the sign (bit 15) of the word in the AX register into the high 16 bits of the EAX register. 
CBW and CWDE reference the same opcode. The CBW instruct ion is intended for use when the operand-size attri-
bute is 16; CWDE is intended for use when the operan d-size attribute is 32. Some assemblers may force the 
operand size. Others may treat these two mnemonics as  synonyms (CBW/CWDE) and use the setting of the 
operand-size attribute to determine the size of values to be converted.
In 64-bit mode, the default operation size is the size of the destination register. Use of the REX.W prefix promotes 
this instruction (CDQE when promoted) to operate on 64-bit  operands. In which case, CDQE copies the sign (bit 31) 
of the doubleword in the EAX regist er into the high 32 bits of RAX.
Operation
IF OperandSize = 16 (* Instruction = CBW *)
THEN 
AX := SignExtend(AL);
ELSE IF (OperandSize = 32, Instruction = CWDE)
EAX := SignExtend(AX); FI;
ELSE (* 64-Bit Mode, OperandSize  = 64, Instruction = CDQE*)
RAX := SignExtend(EAX);
FI;
None.
En64-bit 
98 CBW ZO Valid Valid AX := sign-extend of AL.
98 CWDE ZO Valid Valid EAX := sign-extend of AX.REX.W + 98 CDQE ZO Valid N.E. RAX := sign-extend of EAX.
ZO N/A N/A N/A N/ACLAC—Clear AC Flag in EFLAGS RegisterINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-157CLAC—Clear AC Flag in EFLAGS Register
Clears the AC flag bit in EFLAGS register. This disables any alignment checking of user -mode data accesses. If the 
SMAP bit is set in the CR4 register, this disallows ex plicit supervisor-mode data accesses to user-mode pages.
This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute CLAC when 
CPL > 0 cause #UD.
Operation
EFLAGS.AC := 0;
AC cleared. Other flags are unaffected.
If the CPL > 0.If CPUID.(EAX=07H, ECX= 0H):EBX.SMAP[bit 20] = 0.
If CPUID.(EAX=07H, ECX= 0H):EBX.SMAP[bit 20] = 0.
#UD The CLAC instruction is not recognized in virtual-8086 mode.
If the CPL > 0.If CPUID.(EAX=07H, ECX= 0H):EBX.SMAP[bit 20] = 0.Opcode/
Mode 
Feature 
NP 0F 01 CA
CLACZO V/V SMAP Clear the AC flag in the EFLAGS register.
ZO N/A N/A N/A N/ACLC—Clear Carry FlagINSTRUCTION SET REFERENCE, A-L
3-158 Vol. 2ACLC—Clear Carry Flag
Clears the CF flag in the EFLAGS register. Operation is the same in all modes.
Operation
CF := 0;
The CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected.
En64-bit 
F8 CLC ZO Valid Valid C lear CF flag.
ZO N/A N/A N/A N/ACLD—Clear Direction FlagINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-159CLD—Clear Direction Flag
Clears the DF flag in the EFLAGS register. When the DF flag  is set to 0, string operations increment the index regis-
ters (ESI and/or EDI). Operation is the same in all modes.
Operation
DF := 0;
The DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
En64-bit 
FC CLD ZO Valid Valid Clear DF flag.
ZO N/A N/A N/A N/ACLDEMOTE—Cache Line DemoteINSTRUCTION SET REFERENCE, A-L
3-160 Vol. 2ACLDEMOTE—Cache Line Demote
Instruction Operand Encoding1
Hints to hardware that the cache line that contains the lin ear address specified with the memory operand should be 
moved (“demoted”) from the cache(s) closest to the processor core to a level more distant from the processor core. 
This may accelerate subsequent accesses to the line by ot her cores in the same coherence domain, especially if the 
line was written by the core that demotes the line. Moving  the line in such a manner is a performance optimization, 
i.e., it is a hint which does not modify architectural st ate. Hardware may choose which level in the cache hierarchy 
to retain the line (e.g., L3 in typical server designs). The source operand is a byte memory location. 
The availability of the CLDEMOTE instruction is indicated by  the presence of the CPUID feature flag CLDEMOTE (bit 
25 of the ECX register in sub-leaf 07H , see “CPUID—CPU Identification”). On processors which do not support the 
CLDEMOTE instruction (including legacy hardwa re) the instruction will be treated as a NOP.
A CLDEMOTE instruction is ordered with respect to stores  to the same cache line, but unordered with respect to 
other instructions including memory fences, CLDEMOTE, CL WB or CLFLUSHOPT instructions to a different cache 
line. Since CLDEMOTE will retire in order with respect to st ores to the same cache line, software should ensure that 
after issuing CLDEMOTE the line is not accessed again imme diately by the same core to avoid cache data move-
ment penalties. 
The effective memory type of the page containing the affected line determ ines the effect; cacheable types are likely 
to generate a data movement operation, while uncacheable types may cause the instruction to be ignored. 
Speculative fetching can occur at any time and is not tied to instruction execution. The CLDEMOTE instruction is not 
ordered with respect to PREFETCHh instructions or any of  the speculative fetching mechanisms. That is, data can 
be speculatively loaded into a cache line just before, duri ng, or after the execution of a CLDEMOTE instruction that 
references the cache line.
Unlike CLFLUSH, CLFLUSHOPT, and CLWB instructions, CLDEMOTE  is not guaranteed to write back modified data to 
memory. 
The CLDEMOTE instruction may be ignored by hard ware in certain cases and is not a guarantee. 
The CLDEMOTE instruction can be used at all privilege le vels. In certain processor implementations the CLDEMOTE 
instruction may set the A bit but not the D bit in the page tables. 
If the line is not found in the cache, the instruction will be treated as a NOP. In some implementations, the CLDEMOTE instruction may always cause a transactional abort with Transactional 
Synchronization Extensions (TSX). However, programmers must not rely on CLDEMOTE instruction to force a trans-actional abort. Opcode/
Mode SupportCPUID Feature 
NP 0F 1C /0
CLDEMOTE m8A V/V CLDEMOTE Hint to hardware to move  the cache line containing m8 to a 
more distant level of the cach e without writing back to mem-
ory.
A ModRM:r/m (w) N/A N/A N/A
1. The Mod field of the ModR/M byte cannot have value 11B.CLDEMOTE—Cache Line DemoteINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-161Operation
Cache_Line_Demote(m8);
None.
C/C++ Compiler Intrinsic Equivalent
CLDEMOTE void _cldemote(const void*);

NP 0F 1C /0
ory.
None.
Same exceptions as in real address mode.
#UD If the LOCK prefix is used.CLFLUSH—Flush Cache LineINSTRUCTION SET REFERENCE, A-L
3-162 Vol. 2ACLFLUSH—Flush Cache Line
Invalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the 
linear address specified with the memory  operand. If that cache line contains modified data at any level of the 
cache hierarchy, that data is written back to memory. The source operand is a byte memory location.
The availability of CLFLUSH is indicated by the presence of the CPUID feature flag CLFSH 
(CPUID.01H:EDX[bit 19]). The aligned cache line size affect ed is also indicated with the CPUID instruction (bits 8 
through 15 of the EBX register when the initial value in the EAX register is 1).
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It 
should be noted that processors are free to speculatively fetch and cache data from system memory regions 
assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCH h 
instructions can be used to provide the processor with hints for this speculative behavior. Because this speculative 
fetching can occur at any time and is not tied to instruct ion execution, the CLFLUSH instruction is not ordered with 
respect to PREFETCH h instructions or any of the speculative fetching mechanisms (that is, data can be specula-
tively loaded into a cache line just before, during, or af ter the execution of a CLFLUSH instruction that references 
the cache line).
Executions of the CLFLUSH instruction are ordered with re spect to each other and with respect to writes, locked 
read-modify-write instructions, and fence instructions.1 They are not ordered with respect to executions of 
CLFLUSHOPT and CLWB. Software can use the SFENCE instruction to order an execution of CLFLUSH relative to one of those operations.
The CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking and faults asso-
ciated with a byte load (and in addition, a CLFLUSH instru ction is allowed to flush a linear address in an execute-
only segment). Like a load, the CLFLUSH instruction se ts the A bit but not the D bit in the page tables.
In some implementations, the CLFLUSH instruction may always cause transactional abort with Transactional 
Synchronization Extensions (TSX). The CLFLUSH instruction is not expected to be commonly used inside typical 
transactional regions. However, programmers must not rely  on CLFLUSH instruction to force a transactional abort, 
since whether they cause transactional abort is implementation dependent.
The CLFLUSH instruction was introduced with the SSE2 extensions; however, because it has its own CPUID feature 
flag, it can be implemented in IA-32 processors that do not include the SSE2 extensions. Also, detecting the pres-
ence of the SSE2 extensions with the CPUID instruction does not guarantee that the CLFLUSH instruction is imple-
mented in the processor.
CLFLUSH operation is the same in non-64-bit modes and 64-bit mode.
Operation
Flush_Cache_Line(SRC);
Intel C/C ++ Compiler Intrinsic Equivalents
CLFLUSH void _mm_clflush(void const *p)Opcode /
En64-bit 
NP 0F AE /7
CLFLUSH m8M Valid Valid Flushes ca che line containing m8.
M ModRM:r/m (w) N/A N/A N/A
1. Earlier versions of this manual specified that executions of  the CLFLUSH instruction were ordered only by the MFENCE instruct ion. 
All processors implementing the CLFLUSH instruction also order it relative to the other operations enumerated above.CLFLUSH—Flush Cache LineINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-163Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault.
#UD If CPUID.01H:EDX.CLFSH[bit 19] = 0.
#GP If any part of the operand lies outside the effective address space from 0 to FFFFH.
#PF(fault-code) For a page fault.#UD If CPUID.01H:EDX.CLFSH[bit 19] = 0.
If the LOCK prefix is used.CLFLUSHOPT—Flush Cache Line OptimizedINSTRUCTION SET REFERENCE, A-L
3-164 Vol. 2ACLFLUSHOPT—Flush Cache Line  Optimized
The availability of CLFLUSHOPT is indicated by th e presence of the CPUID feature flag CLFLUSHOPT 
(CPUID.(EAX=07H,ECX=0H):EBX[b it 23]). The aligned cache line size affected is also indicated with the CPUID 
instruction (bits 8 through 15 of the EBX register wh en the initial value in the EAX register is 1).
Executions of the CLFLUSHOPT instruction are ordered wi th respect to fence instructions and to locked read-
modify-write instructions; they are also ordered with resp ect to older writes to the cache line being invalidated. 
They are not ordered with respect to other executions of  CLFLUSHOPT, to executions of CLFLUSH and CLWB, or to 
younger writes to the cache line being invalidated. Softwa re can use the SFENCE instruction to order an execution 
of CLFLUSHOPT relative to  one of those operations.
The CLFLUSHOPT instruction can be used at all privilege leve ls and is subject to all permission checking and faults 
associated with a byte load (and in addition, a CLFLUSHO PT instruction is allowed to flush a linear address in an 
execute-only segment). Like a load, the CLFLUSHOPT instruct ion sets the A bit but not the D bit in the page tables.
In some implementations, the CLFLUSHOPT instruction may always cause transactional abort with Transactional 
Synchronization Extensions (TSX). The CLFLUSHOPT instructio n is not expected to be commonly used inside typical 
transactional regions. However, programmers must not re ly on CLFLUSHOPT instruction to force a transactional 
abort, since whether they cause transactional abort is implementation dependent.
CLFLUSHOPT operation is the same in non-64-bit modes and 64-bit mode.
Operation
Flush_Cache_Line_Optimized(SRC);
CLFLUSHOPT void _mm_clflushopt(void const *p)Opcode /
En64-bit 
NFx 66 0F AE /7
CLFLUSHOPT m8M Valid Valid Flushes cach e line containing m8.
M ModRM:r/m (w) N/A N/A N/ACLFLUSHOPT—Flush Cache Line OptimizedINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-165Protected Mode Exceptions
#UD If CPUID.(EAX=07H,ECX=0H ):EBX.CLFLUSHOPT[bit 23] = 0.
If the LOCK prefix is used.If an instruction prefix F2H or F3H is used.
If an instruction prefix F2H or F3H is used.

If an instruction prefix F2H or F3H is used.CLI—Clear Interrupt FlagINSTRUCTION SET REFERENCE, A-L
3-166 Vol. 2ACLI—Clear Interrupt Flag
In most cases, CLI clears the IF flag in the EFLAGS regi ster and no other flags are affected. Clearing the IF flag 
causes the processor to ignore maskable external interrupts. The IF flag and the CLI and STI instruction have no 
effect on the generation of exceptions and NMI interrupts.
Operation is different in two modes defined as follows:
•PVI mode  (protected-mode virtual interrupts): CR0.PE = 1, EFLAGS.VM = 0, CPL = 3, and CR4.PVI = 1;
•VME mode  (virtual-8086 mode extensions): CR0.PE = 1, EFLAGS.VM = 1, and CR4.VME = 1.
If IOPL < 3 and either VME mode or PVI mode is active, CL I clears the VIF flag in the EFLAGS register, leaving IF 
unaffected.
Table 3-7 indicates the action of the CLI instruction de pending on the processor operating mode, IOPL, and CPL. Opcode Instruction Op/ 
En64-bit 
FA CLI ZO Valid Valid Clear interrupt flag; interrupts disabled when 
interrupt flag cleared.
ZO N/A N/A N/A N/A
Table 3-7.  Decision Table for CLI Results
Mode IOPL CLI Result
Real-address X1
NOTES:
1. X = This setting has no ef fect on instruction operation.IF = 0
Protected, not PVI2
2. For this table, “protected mode” applies whenever CR0.PE = 1 and EFLAGS.VM = 0; it includes compatibility mode and 64-bit mode .≥ CPL IF = 0
< CPL #GP fault
Protected, PVI3
3. PVI mode and virtual-8086 mode each imply CPL = 3.3I F  = 0
0–2 VIF  = 0
Virtual-8086, not VME33I F  = 0
0–2 #GP fault
Virtual-8086, VME33I F  = 0
0–2 VIF  = 0CLI—Clear Interrupt FlagINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-167Operation
IF CR0.PE = 0
THEN IF := 0; (* Reset Interrupt Flag *)ELSE
IF IOPL ≥ CPL (* CPL = 3 if EFLAGS.VM = 1 *)
IF VME mode OR PVI mode
THEN VIF := 0; (* Reset Virtual Interrupt Flag *)
ELSE #GP(0);
FI;
FI;
FI;
Either the IF flag or the VIF flag is cleared to 0. Other flags are unaffected.
#GP(0) If CPL is greater than IOPL and PVI mode is not active.
If CPL is greater than IOPL and less than 3.
#GP(0) If IOPL is less than 3 and VME mode is not active.#UD If the LOCK prefix is used.
Same exceptions as in protected mode.CLRSSBSY—Clear Busy Flag in a Supervisor Shadow Stack TokenINSTRUCTION SET REFERENCE, A-L
3-168 Vol. 2ACLRSSBSY—Clear Busy Flag in a Supervisor Shadow Stack Token
Clear busy flag in supervisor shadow stack token refere nce by m64. Subsequent to marking the shadow stack as 
not busy the SSP is loaded with value 0.
Operation
IF (CR4.CET = 0)
THEN #UD; FI;
IF (IA32_S_CET.SH_STK_EN = 0)
IF CPL > 0
THEN GP(0); FI;
SSP_LA = Linear_Address(mem operand)
IF SSP_LA not aligned to 8 bytes
expected_token_value = SSP_LA | BUSY_BIT (* busy bit - bit position  0 - must be set *)
new_token_value = SSP_LA (* Clear the busy bit *)IF shadow_stack_lock_cmpx chg8b(SSP_LA, new_token_value, expected_token_value) != expected_token_value
invalid_token := 1; FI
(* Set the CF if invali d token was detected *)
RFLAGS.CF = (invalid_token == 1) ? 1 : 0;RFLAGS.ZF,PF,AF,OF,SF := 0;SSP := 0
CF is set if an invalid token was detected, else it is cleared. ZF, PF, AF, OF, and SF are cleared.Opcode/
Mode 
Feature 
F3 0F AE /6
CLRSSBSY m64M V/V CET_SS Clear busy flag in supervisor shadow stack token 
reference by m64.
M N/A ModRM:r/m (r, w) N/A N/A N/ACLRSSBSY—Clear Busy Flag in a Supervisor Shadow Stack TokenINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-169Protected Mode Exceptions
If CR4.CET = 0.IF IA32_S_CET.SH_STK_EN = 0.
#GP(0) If memory operand linear address not aligned to 8 bytes.
If destination is located in a non-writeable segment.
selector.
If CPL is not 0.
#UD The CLRSSBSY instruction is not recognized in real-address mode.
#UD The CLRSSBSY instru ction is not recognized in virtual-8086 mode.
#UD Same exceptions as in protected mode.
#GP(0) Same exceptions as in protected mode.
If CR4.CET = 0.
IF IA32_S_CET.SH_STK_EN = 0.
If the memory address is in a non-canonical form.If token is invalid.
#PF(fault-code) If a page fault occurs.CLTS—Clear Task-Switched Flag in CR0INSTRUCTION SET REFERENCE, A-L
3-170 Vol. 2ACLTS—Clear Task-Switched Flag in CR0
Clears the task-switched (TS) flag in the CR0 register. Th is instruction is intended for use in operating-system 
procedures. It is a privileged instruction th at can only be executed at a CPL of 0. It is allowed to be executed in real-
address mode to allow initialization for protected mode.
The processor sets the TS flag every time a task switch o ccurs. The flag is used to synchronize the saving of FPU 
context in multitasking applications. See the description of the TS flag in the section titled “Control Registers” in 
Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information 
about this flag. 
CLTS operation is the same in non-64-bit modes and 64-bit mode.See Chapter 26, “VMX Non-Root Operation,” of the Intel
Volume 3C, for more information about the behavior  of this instruction in VMX non-root operation.
Operation
CR0.TS[bit 3] := 0;
The TS flag in CR0 register is cleared.
#GP(0) If the current privilege level is not 0.
#GP(0) CLTS is not recognized in virtual-8086 mode.#UD If the LOCK prefix is used.
#GP(0) If the CPL is greater than 0.#UD If the LOCK prefix is used.Opcode Instruction Op/ 
En64-bit 
0F 06 CLTS ZO Valid Valid Clears TS flag in CR0.
ZO N/A N/A N/A N/ACLUI—Clear User Interrupt FlagINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-171CLUI—Clear User Interrupt Flag
CLUI clears the user interrupt flag (U IF). Its effect takes place immediately: a user interrupt cannot be delivered 
on the instruction boundary following CLUI.
An execution of CLUI inside a transactional region causes a transactional abort; the abort loads EAX as it would 
have had it been caused due to an execution of CLI.
Operation
UIF := 0;
None.
#UD The CLUI instruction is not recognized in protected mode.
#UD The CLUI instruction is not recognized in real-address mode.
#UD The CLUI instruction is not recognized in virtual-8086 mode.
#UD The CLUI instruction is not recognized in compatibility mode.
If executed inside an enclave.
If CR4.UINTR = 0.
If CPUID.07H.0H:EDX.UINTR[bit 5] = 0.Opcode/
InstructionOp/
Mode 
SupportCPUID Feature 
F3 0F 01 EE
CLUIZO V/I UINTR Clear user interrupt flag; user interrupts blocked 
when user interrupt flag cleared.
ZO N/A N/A N/A N/A N/ACLWB—Cache Line Write BackINSTRUCTION SET REFERENCE, A-L
3-172 Vol. 2ACLWB—Cache Line Write Back
Writes back to memory the cache line (if modified) that  contains the linear address specified with the memory

Mode 
F3 0F 01 EE
Writes back to memory the cache line (if modified) that  contains the linear address specified with the memory 
operand from any level of the cache hierarchy in the ca che coherence domain. The line may be retained in the 
cache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization 
(treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may 
choose to retain the line at any of the levels in the cach e hierarchy, and in some cases, may invalidate the line from 
the cache hierarchy. The source operand is a byte memory location. 
The availability of CLWB instruction is indicated by the pres ence of the CPUID feature flag CLWB (bit 24 of the EBX 
register, see “CPUID — CPU Identification” in this chapter) . The aligned cache line size affected is also indicated 
with the CPUID instruction (bits 8 through 15 of the EBX re gister when the initial value in the EAX register is 1).
should be noted that processors are free to speculatively fetch and cache data from system memory regions that 
are assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). 
PREFETCHh instructions can be used to provide the processo r with hints for this speculative behavior. Because this 
speculative fetching can occur at any time and is not tied to instruction execution, the CLWB instruction is not 
ordered with respect to PREFETCHh instructions or any of  the speculative fetching mechanisms (that is, data can 
be speculatively loaded into a cache line just before, duri ng, or after the execution of a CLWB instruction that refer-
ences the cache line). 
Executions of the CLWB instruction are ordered with respect to fence instructions and to locked read-modify-write 
instructions; they are also ordered with respect to older writes to the cache line being written back. They are not 
ordered with respect to other executions of CLWB, to executions of CLFLUSH and CLFLUSHOPT, or to younger 
writes to the cache line being written back. Software can use the SFENCE instruction to order an execution of CLWB 
relative to one of those operations.
For usages that require only writing back modified data fr om cache lines to memory (do not require the line to be 
invalidated), and expect to subsequently access the data, software is recommended to use CLWB (with appropriate 
fencing) instead of CLFLUSH or CL FLUSHOPT for improved performance.
The CLWB instruction can be used at all privilege levels an d is subject to all permission checking and faults associ-
ated with a byte load. Like a load, the CLWB instruction sets the accessed flag but not the dirty flag in the page 
tables.
In some implementations, the CLWB instruction may always cause transactional abort with Transactional Synchro-
nization Extensions (TSX). CLWB instruction is not expe cted to be commonly used inside typical transactional 
regions. However, programmers must not rely on CLWB instruction to force a transactional abort, since whether 
they cause transactional abort is implementation dependent.
Operation
Cache_Line_Write_Back(m8);Opcode/
66 0F AE /6
CLWB m8M V/V CLWB Writes back modified cache line containing m8, and may 
retain the line in cache hierarchy in non-modified state.
1. The Mod field of the ModR/M byte cannot have value 11B.CLWB—Cache Line Write BackINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-173Flags Affected
None.
CLWB void _mm_clwb(void const *p);
If CPUID.(EAX=07H, ECX= 0H):EBX.CLWB[bit 24] = 0.
#SS(0) For an illegal address in the SS segment. 
#PF(fault-code) For a page fault.CMC—Complement Carry FlagINSTRUCTION SET REFERENCE, A-L
3-174 Vol. 2ACMC—Complement Carry Flag
Complements the CF flag in the EFLAGS register. CMC operation is the same in non-64-bit modes and 64-bit mode.
Operation
EFLAGS.CF[bit 0] := NOT EFLAGS.CF[bit 0];
The CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.
En64-bit 
F5 CMC ZO Valid Valid Complement CF flag.
ZO N/A N/A N/A N/ACMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-175CMOV cc—Conditional Move
Opcode Instruction Op/ 
En64-Bit 
0F 47 /r CMOVA r16, r/m16 RM Valid Valid Move if above (CF=0 and ZF=0).
0F 47 /r CMOVA r32, r/m32 RM Valid Valid Move if above (CF=0 and ZF=0).REX.W + 0F 47 /r CMOVA r64, r/m64 RM Valid N.E. Move if above (CF=0 and ZF=0).0F 43 /r CMOVAE r16, r/m16 RM Valid Va lid Move if above or equal (CF=0).
0F 43 /r CMOVAE r32, r/m32 RM Valid Va lid Move if above or equal (CF=0).
REX.W + 0F 43 /r CMOVAE r64, r/m64 RM Val id N.E. Move if above or equal (CF=0).
0F 42 /r CMOVB r16, r/m16 RM Valid Valid Move if below (CF=1).0F 42 /r CMOVB r32, r/m32 RM Valid Valid Move if below (CF=1).REX.W + 0F 42 /r CMOVB r64, r/m64 RM Valid N.E. Move if below (CF=1).0F 46 /r CMOVBE r16, r/m16 RM Valid Valid Move if below or equal (CF=1 or ZF=1).0F 46 /r CMOVBE r32, r/m32 RM Valid Valid Move if below or equal (CF=1 or ZF=1).REX.W + 0F 46 /r CMOVBE r64, r/m64 RM Valid N. E. Move if below or equal (CF=1 or ZF=1).
0F 42 /r CMOVC r16, r/m16 RM Valid Valid Move if carry (CF=1).0F 42 /r CMOVC r32, r/m32 RM Valid Valid Move if carry (CF=1).REX.W + 0F 42 /r CMOVC r64, r/m64 RM Valid N.E. Move if carry (CF=1).0F 44 /r CMOVE r16, r/m16 RM Val id Valid Move if equal (ZF=1).
0F 44 /r CMOVE r32, r/m32 RM Val id Valid Move if equal (ZF=1).
REX.W + 0F 44 /r CMOVE r64, r/m64 RM Valid N.E. Move if equal (ZF=1).0F 4F /r CMOVG r16, r/m16 RM Valid Valid Move if greater (ZF=0 and SF=OF).0F 4F /r CMOVG r32, r/m32 RM Valid Valid Move if greater (ZF=0 and SF=OF).REX.W + 0F 4F /r CMOVG r64, r/m64 RM V/N.E . N/A Move if greater (ZF=0 and SF=OF).
0F 4D /r CMOVGE r16, r/m16 RM Valid Valid Move if greater or equal (SF=OF).0F 4D /r CMOVGE r32, r/m32 RM Valid Valid Move if greater or equal (SF=OF).REX.W + 0F 4D /r CMOVGE r64, r/m64 RM Valid N.E. Move if greater or equal (SF=OF).0F 4C /r CMOVL r16, r/m16 RM Valid Valid Move if less (SF
≠ OF).
0F 4C /r CMOVL r32, r/m32 RM Valid Valid Move if less (SF ≠ OF).
REX.W + 0F 4C /r CMOVL r64, r/m64 RM Valid N.E. Move if less (SF ≠ OF).
0F 4E /r CMOVLE r16, r/m16 RM Valid Valid Move if less or equal (ZF=1 or SF ≠ OF).
0F 4E /r CMOVLE r32, r/m32 RM Valid Valid Move if less or equal (ZF=1 or SF ≠ OF).
REX.W + 0F 4E /r CMOVLE r64, r/m64 RM Valid N.E. Move if less or equal (ZF=1 or SF ≠ OF).
0F 46 /r CMOVNA r16, r/m16 RM Valid Va lid Move if not above (CF=1 or ZF=1).
0F 46 /r CMOVNA r32, r/m32 RM Valid Va lid Move if not above (CF=1 or ZF=1).
REX.W + 0F 46 /r CMOVNA r64, r/m64 RM Valid N.E. Move if not above (CF=1 or ZF=1).
0F 42 /r CMOVNAE r16, r/m16 RM Valid Valid Move if not above or equal (CF=1).0F 42 /r CMOVNAE r32, r/m32 RM Valid Valid Move if not above or equal (CF=1).REX.W + 0F 42 /r CMOVNAE r64, r/m64 RM Valid N.E. Move if not above or equal (CF=1).
0F 43 /r CMOVNB r16, r/m16 RM Valid Valid Move if not below (CF=0).0F 43 /r CMOVNB r32, r/m32 RM Valid Valid Move if not below (CF=0).REX.W + 0F 43 /r CMOVNB r64, r/m64 RM Valid N.E. Move if not below (CF=0).0F 47 /r CMOVNBE r16, r/m16 RM Valid Valid Move if not below or equal (CF=0 and ZF=0).CMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-L
3-176 Vol. 2AOpcode Instruction Op/ 
En64-Bit 
0F 47 /r CMOVNBE r32, r/m32 RM Valid Valid Move if not below or equal (CF=0 and ZF=0).
REX.W + 0F 47 /r CMOVNBE r64, r/m64 RM Valid N.E. Move if not below or equal (CF=0 and ZF=0).
0F 43 /r CMOVNC r16, r/m16 RM Valid Valid Move if not carry (CF=0).0F 43 /r CMOVNC r32, r/m32 RM Valid Valid Move if not carry (CF=0).REX.W + 0F 43 /r CMOVNC r64, r/m64 R M Valid N.E. Move if not carry (CF=0).

En64-Bit 
0F 45 /r CMOVNE r16, r/m16 RM Valid Valid Move if not equal (ZF=0).0F 45 /r CMOVNE r32, r/m32 RM Valid Valid Move if not equal (ZF=0).REX.W + 0F 45 /r CMOVNE r64, r/m64 R MV a l i d N . E . M o v e  i f  n o t  e q u a l  ( Z F = 0 ) .
0F 4E /r CMOVNG r16, r/m16 RM Valid Valid Move if not greater (ZF=1 or SF
≠ OF).
0F 4E /r CMOVNG r32, r/m32 RM Valid Valid Move if not greater (ZF=1 or SF ≠ OF).
REX.W + 0F 4E /r CMOVNG r64, r/m64 RM Val id N.E. Move if not greater (ZF=1 or SF ≠ OF).
0F 4C /r CMOVNGE r16, r/m16 RM Valid Valid Move if not greater or equal (SF ≠ OF).
0F 4C /r CMOVNGE r32, r/m32 RM Valid Valid Move if not greater or equal (SF ≠ OF).
REX.W + 0F 4C /r CMOVNGE r64, r/m64 RM Valid N.E. Move if not greater or equal (SF ≠ OF).
0F 4D /r CMOVNL r16, r/m16 RM Val id Valid Move if not less (SF=OF).
0F 4D /r CMOVNL r32, r/m32 RM Val id Valid Move if not less (SF=OF).
REX.W + 0F 4D /r CMOVNL r64, r/m64 R M Valid N.E. Move if not less (SF=OF).
0F 4F /r CMOVNLE r16, r/m16 RM Valid Valid Mov e if not less or equal (ZF=0 and SF=OF).
0F 4F /r CMOVNLE r32, r/m32 RM Valid Valid Mov e if not less or equal (ZF=0 and SF=OF).
REX.W + 0F 4F /r CMOVNLE r64, r/m64 RM Valid N.E. Move if not less or equal (ZF=0 and SF=OF).
0F 41 /r CMOVNO r16, r/m16 RM Valid Valid Move if not overflow (OF=0).
0F 41 /r CMOVNO r32, r/m32 RM Valid Valid Move if not overflow (OF=0).
REX.W + 0F 41 /r CMOVNO r64, r/m64 RM V alid N.E. Move if not overflow (OF=0).
0F 4B /r CMOVNP r16, r/m16 RM Valid Valid Move if not parity (PF=0).
0F 4B /r CMOVNP r32, r/m32 RM Valid Valid Move if not parity (PF=0).
REX.W + 0F 4B /r CMOVNP r64, r/m64 RM V alid N.E. Move if not parity (PF=0).
0F 49 /r CMOVNS r16, r/m16 RM Val id Valid Move if not sign (SF=0).
0F 49 /r CMOVNS r32, r/m32 RM Val id Valid Move if not sign (SF=0).
REX.W + 0F 49 /r CMOVNS r64, r/m64 R M Valid N.E. Move if not sign (SF=0).
0F 45 /r CMOVNZ r16, r/m16 RM Valid Valid Move if not zero (ZF=0).0F 45 /r CMOVNZ r32, r/m32 RM Valid Valid Move if not zero (ZF=0).REX.W + 0F 45 /r CMOVNZ r64, r/m64 R M Valid N.E. Move if not zero (ZF=0).
0F 40 /r CMOVO r16, r/m16 RM Valid Valid Move if overflow (OF=1).
0F 40 /r CMOVO r32, r/m32 RM Valid Valid Move if overflow (OF=1).
REX.W + 0F 40 /r CMOVO r64, r/m64 RM Valid N.E. Move if overflow (OF=1).0F 4A /r CMOVP r16, r/m16 RM Valid Valid Move if parity (PF=1).0F 4A /r CMOVP r32, r/m32 RM Valid Valid Move if parity (PF=1).REX.W + 0F 4A /r CMOVP r64, r/m64 RM Valid N.E. Move if parity (PF=1).
0F 4A /r CMOVPE r16, r/m16 RM Valid Valid Move if parity even (PF=1).
0F 4A /r CMOVPE r32, r/m32 RM Valid Valid Move if parity even (PF=1).
REX.W + 0F 4A /r CMOVPE r64, r/m64 RM V alid N.E. Move if parity even (PF=1).CMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-177Instruction Operand Encoding
Each of the CMOVcc instructions performs a move operation if the status flags in the EFLAGS register (CF, OF, PF, 
SF, and ZF) are in a specified state (or condition). A condition code ( cc) is associated with each instruction to indi-
cate the condition being tested for. If the condition is  not satisfied, a move is not performed and execution 
continues with the instruction following the CMOV cc instruction.
Specifically, CMOVcc loads data from its source operand in to a temporary register unconditionally (regardless of 
the condition code and the status flags in the EFLAGS regist er). If the condition code associated with the instruction 
(cc) is satisfied, the data in the temporary register is then copied into the instruction's destination operand.
These instructions can move 16-bit, 32-bit or 64-bit values  from memory to a general-purpose register or from one 
general-purpose register to another. Conditional mo ves of 8-bit register operands are not supported.
The condition for each CMOV cc mnemonic is given in the description column of the above table. The terms “less” 
and “greater” are used for comparisons of signed inte gers and the terms “above” and “below” are used for 
unsigned integers.
Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are 
defined for some opcodes. For example, the CMOVA (con ditional move if above) instruction and the CMOVNBE 
(conditional move if not below or equal) instruct ion are alternate mnemonics for the opcode 0F 47H. 
The CMOV cc instructions were introduced in P6 family processors; however, these instructions may not be 
supported by all IA-32 processors. Software can determine if the CMOV cc instructions are supported by checking 
the processor’s feature information with the CPUID instruction (see “CPUID—CPU Identification” in this chapter).
In 64-bit mode, the instruction’s default operation size is  32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the 
beginning of this section for encoding data and limits.
Operation
temp := SRC
IF condition TRUE
THEN DEST := temp;
ELSE IF (OperandSize = 32 and IA-32e mode active)
THEN DEST[63:32] := 0;
FI;Opcode Instruction Op/ 
En64-Bit 
0F 4B /r CMOVPO r16, r/m16 RM Valid Valid Move if parity odd (PF=0).
0F 4B /r CMOVPO r32, r/m32 RM Valid Valid Move if parity odd (PF=0).
REX.W + 0F 4B /r CMOVPO r64, r/m64 RM Valid N.E. Move if parity odd (PF=0).0F 48 /r CMOVS r16, r/m16 RM Valid Valid Move if sign (SF=1).0F 48 /r CMOVS r32, r/m32 RM Valid Valid Move if sign (SF=1).REX.W + 0F 48 /r CMOVS r64, r/m64 RM Valid N.E. Move if sign (SF=1).0F 44 /r CMOVZ r16, r/m16 RM Valid Valid Move if zero (ZF=1).0F 44 /r CMOVZ r32, r/m32 RM Valid Valid Move if zero (ZF=1).REX.W + 0F 44 /r CMOVZ r64, r/m64 RM Valid N.E. Move if zero (ZF=1).
RM ModRM:reg (r, w) ModRM:r/m (r) N/A N/ACMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-L
3-178 Vol. 2AFlags Affected
None.
#UD If the LOCK prefix is used.CMP—Compare Two OperandsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-179CMP—Compare Two Operands
Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register 
according to the results. The comparison is performed by  subtracting the second operand from the first operand 
and then setting the status flags in the same manner as th e SUB instruction. When an immediate value is used as 
an operand, it is sign-extended to the length of the first operand.
The condition codes used by the J cc, CMOV cc, and SET cc instructions are based on the results of a CMP instruction. 
Appendix B, “EFLAGS Condit ion Codes,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1, shows the relationship of the status flags and the condition codes.Opcode Instruction Op/ 
En64-Bit 
3C ib CMP AL, imm8 I Valid Valid Compare imm8 with AL.
3D iw CMP AX, imm16 I Valid Valid Compare imm16 with AX.3D id CMP EAX, imm32 I Valid Valid Compare imm32 with EAX.REX.W + 3D id CMP RAX, imm32 I Valid N.E. Compare imm32 sign-extended to 64-bits 
with RAX.
80 /7 ib CMP r/m8, imm8 MI Valid Valid Compare imm8 with r/m8.REX + 80 /7 ib CMP r/m8
*, imm8 MI Valid N.E. Compare imm8 with r/m8.
81 /7 iw CMP r/m16, imm16 MI Valid Valid Compare imm16 with r/m16.81 /7 id CMP r/m32, imm32 MI Valid Valid Compare imm32 with r/m32.REX.W + 81 /7 id CMP r/m64, imm32 MI Valid N.E. Compare imm32 sign-extended to 64-bits 
with r/m64.
83 /7 ib CMP r/m16, imm8 MI Vali d Valid Compare imm8 with r/m16.
83 /7 ib CMP r/m32, imm8 MI Vali d Valid Compare imm8 with r/m32.

En64-Bit 
with RAX.
REX.W + 83 /7 ib CMP r/m64, imm8 MI Valid N.E. Compare imm8 with r/m64.38 /r CMP r/m8, r8 MR Valid Valid Compare r8 with r/m8.REX + 38 /r CMP r/m8
*, r8*MR Valid N.E. Compare r8 with r/m8.
39 /r CMP r/m16, r16 MR Valid Valid Compare r16 with r/m16.39 /r CMP r/m32, r32 MR Valid Valid Compare r32 with r/m32.REX.W + 39 /r CMP r/m64,r64 MR Valid N.E. Compare r64 with r/m64.3A /r CMP r8, r/m8 RM Valid Valid Compare r/m8 with r8.REX + 3A /r CMP r8
*, r/m8*RM Valid N.E. Compare r/m8 with r8.
3B /r CMP r16, r/m16 RM Valid Valid Compare r/m16 with r16.3B /r CMP r32, r/m32 RM Valid Valid Compare r/m32 with r32.REX.W + 3B /r CMP r64, r/m64 RM Valid N.E. Compare r/m64 with r64.NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH. 
RM ModRM:reg (r) ModRM:r/m (r) N/A N/A
MI ModRM:r/m (r) imm8/16/32 N/A N/A
I AL/AX/EAX/RAX (r) imm8/16/32 N/A N/ACMP—Compare Two OperandsINSTRUCTION SET REFERENCE, A-L
3-180 Vol. 2AIn 64-bit mode, the instruction’s default operation size is  32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
Operation
temp := SRC1 − SignExtend(SRC2); 
ModifyStatusFlags; (* Modify status flags in  the same manner as the SUB instruction*)
The CF, OF, SF, ZF, AF, and PF flags are set according to the result.
#UD If the LOCK prefix is used.CMPPD—Compare Packed Double Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-181CMPPD—Compare Packed Double Pr ecision Floating-Point Values
Performs a SIMD compare of the packed double precision floating-point values in the second source operand and 
the first source operand and returns the result of the comp arison to the destination operand. The comparison pred-
icate operand (immediate byte) specifies the type of compar ison performed on each pair of packed values in the 
two source operands. 
EVEX encoded versions: The first source operand (sec ond operand) is a ZMM/YMM/XMM register. The second 
source operand can be a ZMM/YMM/XMM register, a 512/2 56/128-bit memory location or a 512/256/128-bit vector 
broadcasted from a 64-bit memory location. The destinat ion operand (first operand)  is an opmask register. 
Comparison results are written to the destination operan d under the writemask k2. Each comparison result is a 
single mask bit of 1 (comparison true) or 0 (comparison false).
VEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source 
operand (third operand) can be a YMM register or a 256 -bit memory location. The destination operand (first 
operand) is a YMM register. Four comparisons are performed with results written to the destination operand. The 
result of each comparison is a quadword mask of a ll 1s (comparison true) or all 0s (comparison false).
128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The 
second source operand (second operand) can be an XMM re gister or 128-bit memory location. Bits (MAXVL-1:128) 
of the corresponding ZMM destination register remain unchanged. Two comparisons are performed with results 
written to bits 127:0 of the destination operand. The resu lt of each comparison is a quadword mask of all 1s 
(comparison true) or all 0s (comparison false).Opcode/
Mode 
Feature 
66 0F C2 /r ib
CMPPD xmm1, xmm2/m128, imm8A V/V SSE2 Compare packed double precision floating-point values 
in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a 
comparison predicate.
VEX.128.66.0F.WIG C2 /r ib
VCMPPD xmm1, xmm2, xmm3/m128, imm8B V/V AVX Compare packed double precision floating-point values 
in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a comparison predicate.
VEX.256.66.0F.WIG C2 /r ib
VCMPPD ymm1, ymm2, ymm3/m256, 
imm8B V/V AVX Compare packed double precision floating-point values 
in ymm3/m256 and ymm2 usin g bits 4:0 of imm8 as a 
EVEX.128.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, xmm2, 
xmm3/m128/m64bcst, imm8CV / V A V X 5 1 2 V L
AVX512FCompare packed double precision floating-point values 
in xmm3/m128/m64bcst and xmm2 using bits 4:0 of 
imm8 as a comparison predicate with writemask k2 and 
leave the result in mask register k1.
EVEX.256.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, ymm2, 
ymm3/m256/m64bcst, imm8CV / V A V X 5 1 2 V L
in ymm3/m256/m64bcst and ymm2 using bits 4:0 of 
imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1.
EVEX.512.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, zmm2, 
zmm3/m512/m64bcst{sae}, imm8C V/V AVX512F Compare packed double precision floating-point values 
in zmm3/m512/m64bcst and zmm2 using bits 4:0 of 
A N/A ModRM:reg (r, w) ModRM:r/m (r) imm8 N/A
B N/A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8
CF u l lM o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) imm8CMPPD—Compare Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-182 Vol. 2AVEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source 
operand (third operand) can be an XMM register or a 1 28-bit memory location. Bits (MAXVL-1:128) of the destina-
tion ZMM register are zeroed. Two comparisons are performe d with results written to bits 127:0 of the destination 
operand.
The comparison predicate operand is an 8-bit immediate:
•For instructions encoded using the VEX or EVEX prefix, bi ts 4:0 define the type of comparison to be performed 
(see Table 3-1). Bits 5 through 7 of the immediate are reserved. 
•For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see the 
first 8 rows of Table 3-1). Bits 3 th rough 7 of the immediate are reserved. 
Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions 
Predicate imm8 
ValueDescription Result: A Is 1st Oper and, B Is 2nd Operand Signals 
#IA on 
QNANA >B A < B A = B Unordered1
EQ_OQ (EQ) 0H Equal (ordered, non-signaling) False False True False No
LT_OS (LT) 1H Less-than (ordered, signaling) False True False False Yes
LE_OS (LE) 2H Less-than-or-equal (ordered, signaling) False True True False Yes
UNORD_Q (UNORD) 3H Unordered (non-signaling) False False False True NoNEQ_UQ (NEQ) 4H Not-equal (unordered, non-signaling) True True False True No
NLT_US (NLT) 5H Not-less-than (unordered, signaling) True False True True Yes
NLE_US (NLE) 6H Not-less-than-or-equal (unordered, signaling) True False False True YesORD_Q (ORD) 7H Ordered (non-signaling) True True True False No
EQ_UQ 8H Equal (unordered, non-signaling) False False True True No
NGE_US (NGE) 9H Not-greater-t han-or-equal (unordered, 
signaling)False True False True Yes
NGT_US (NGT) AH Not-greater-than (unord ered, signaling) False True True True Yes
FALSE_OQ(FALSE) BH False (ordered, no n-signaling) False False False False No
NEQ_OQ CH Not-equal (ordered, non- signaling) True True False False No
GE_OS (GE) DH Greater-than-or-equal (ord ered, signaling) True False True False Yes
GT_OS (GT) EH Greater-than (ordered, signaling) True False False False Yes
TRUE_UQ(TRUE) FH True (unordered, non-signaling) True True True True No

EQ_OS 10H Equal (ordered, signaling) False False True False YesLT_OQ 11H Less-than (ordered, nons ignaling) False True False False No
LE_OQ 12H Less-than-or-equal (ordered, nonsignaling) False True True False No
UNORD_S 13H Unordered (signaling) False False False True YesNEQ_US 14H Not-equal (unordered, signaling) True True False True Yes
NLT_UQ 15H Not-less-than (unordered, nonsignaling) True False True True No
NLE_UQ 16H Not-less-than-or-equal (unordered, nonsig-
naling)True False False True No
ORD_S 17H Ordered (signaling) True True True False YesEQ_US 18H Equal (unordered, signaling) False False True True Yes
NGE_UQ 19H Not-greater-than-or-equal (unordered, non-
signaling)False True False True NoCMPPD—Compare Packed Double Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-183The unordered relationship is true when at least one of  the two source operands being compared is a NaN; the 
ordered relationship is true when neither source operand is a NaN. 
A subsequent computational instruction that uses the mask result in the destination operand as an input operand 
will not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask 
of all 1s corresponds to a QNaN. 
Note that processors with “CPUID.1H: ECX.AVX =0” do not implement the “gre ater-than”, “greater-than-or-equal”, 
“not-greater than”, and “not-greater-than-or-equal relati ons” predicates. These comparisons can be made either 
by using the inverse relationship (that is, use the “not-l ess-than-or-equal” to make a “greater-than” comparison) 
or by using software emulation. When using software em ulation, the program must swap the operands (copying 
registers when necessary to protect the data that will now be in the destination), and then perform the compare 
using a different predicate. The predicate to be used for th ese emulations is listed in the first 8 rows of Table 3-7 
(Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A) under the heading Emulation. 
Compilers and assemblers may implement the following two- operand pseudo-ops in addition to the three-operand 
CMPPD instruction, for processors with “CPUID.1H:EC X.AVX =0”. See Table 3-2. The compiler should treat 
reserved imm8 values as illegal syntax.
:
The greater-than relations that the processor does not im plement require more than on e instruction to emulate in 
software and therefore should not be implemented as ps eudo-ops. (For these, the programmer should reverse the 
operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to 
the correct destination register and that the source operand is left intact.)
Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table 3-3, soft-
ware emulation is no longer needed. Compilers and assemblers may implement the following three-operand 
pseudo-ops in addition to the four-operand VCMPPD inst ruction. See Table 3-3, where the notations of reg1 reg2, 
and reg3 represent either XMM registers or YMM register s. The compiler should treat reserved imm8 values as NGT_UQ 1AH Not-greater-than (unordered, nonsignaling) False True True True No
FALSE_OS 1BH False (ordered, signaling) False False False False YesNEQ_OS 1CH Not-equal (ordered, signaling) True True False False Yes
GE_OQ 1DH Greater-than-or-equal (ordered, nonsignal-
ing)True False True False No
GT_OQ 1EH Greater-than (ordered, nonsignaling) True False False False No
TRUE_US 1FH True (unordered, signaling) True True True True Yes
NOTES:
1. If either operand A or B is a NAN.
Table 3-2. Pseudo-Op and CMPPD Implementation
Pseudo-Op CMPPD ImplementationCMPEQPD xmm1, xmm2 CMPPD xmm1, xmm2, 0CMPLTPD xmm1, xmm2 CMPPD xmm1, xmm2, 1
CMPLEPD xmm1, xmm2 CMPPD xmm1, xmm2, 2
CMPUNORDPD xmm1, xmm2 CMPPD xmm1, xmm2, 3CMPNEQPD xmm1, xmm2 CMPPD xmm1, xmm2, 4
CMPNLTPD xmm1, xmm2 CMPPD xmm1, xmm2, 5
CMPNLEPD xmm1, xmm2 CMPPD xmm1, xmm2, 6
CMPORDPD xmm1, xmm2 CMPPD xmm1, xmm2, 7Table 3-1. Comparison Predicate for CM PPD and CMPPS Instructions  (Contd.)
ValueDescription Result: A Is 1st Operand, B Is 2nd Operand Signals 
#IA on QNANA >B A < B A = B Unordered1CMPPD—Compare Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-184 Vol. 2Aillegal syntax. Alternately, intrinsics can map the pseudo-ops  to pre-defined constants to support a simpler intrinsic 
interface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPPD instructions in a similar fashion by ex tending the syntax listed in Table 3-3.
:Table 3-3. Pseudo-Op an d VCMPPD Implementation
Pseudo-Op CMPPD Implementation
VCMPEQPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0
VCMPLTPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1
VCMPLEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 2
VCMPUNORDPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 3
VCMPNEQPD reg1, reg2, reg3 VCMPPD  reg1, reg2, reg3, 4
VCMPNLTPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 5
VCMPNLEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 6
VCMPORDPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 7
VCMPEQ_UQPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 8
VCMPNGEPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 9
VCMPNGTPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0AH
VCMPFALSEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0BH
VCMPNEQ_OQPD reg1, reg2, reg3 VCMPPD  reg1, reg2, reg3, 0CH
VCMPGEPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0DH
VCMPGTPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0EH
VCMPTRUEPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0FH
VCMPEQ_OSPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 10H
VCMPLT_OQPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 11H
VCMPLE_OQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 12H
VCMPUNORD_SPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 13H
VCMPNEQ_USPD reg1, reg2, reg3 VCMPPD  reg1, reg2, reg3, 14H
VCMPNLT_UQPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 15H
VCMPNLE_UQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 16H
VCMPORD_SPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 17H
VCMPEQ_USPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 18H
VCMPNGE_UQPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 19H
VCMPNGT_UQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1AH
VCMPFALSE_OSPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1BH
VCMPNEQ_OSPD reg1, reg2, reg3 VCMPPD  reg1, reg2, reg3, 1CH
VCMPGE_OQPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1DH
VCMPGT_OQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1EH
VCMPTRUE_USPD  reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1FHCMPPD—Compare Packed Double Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-185Operation
CASE (COMPARISON PREDICATE) OF
0: OP3 := EQ_OQ; OP5 := EQ_OQ;
1: OP3 := LT_OS; OP5 := LT_OS;2: OP3 := LE_OS; OP5 := LE_OS;3: OP3 := UNORD_Q; OP5 := UNORD_Q;4: OP3 := NEQ_UQ; OP5 := NEQ_UQ;5: OP3 := NLT_US; OP5 := NLT_US;6: OP3 := NLE_US; OP5 := NLE_US;7: OP3 := ORD_Q; OP5 := ORD_Q;8: OP5 := EQ_UQ;9: OP5 := NGE_US;10: OP5 := NGT_US;11: OP5 := FALSE_OQ;12: OP5 := NEQ_OQ;
13: OP5 := GE_OS;
14: OP5 := GT_OS;15: OP5 := TRUE_UQ;16: OP5 := EQ_OS;17: OP5 := LT_OQ;18: OP5 := LE_OQ;19: OP5 := UNORD_S;20: OP5 := NEQ_US;21: OP5 := NLT_UQ;22: OP5 := NLE_UQ;23: OP5 := ORD_S;24: OP5 := EQ_US;25: OP5 := NGE_UQ;26: OP5 := NGT_UQ;27: OP5 := FALSE_OS;28: OP5 := NEQ_OS;29: OP5 := GE_OQ;30: OP5 := GT_OQ;31: OP5 := TRUE_US;DEFAULT: Reserved;
ESAC;CMPPD—Compare Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-186 Vol. 2AVCMPPD (EVEX Encoded Versions)
i := j * 64IF k2[j] OR *no writemask*
THEN 
IF (EVEX.b = 1) AN D (SRC2 *is memory*)
THEN
CMP := SRC1[i+63:i] OP5 SRC2[63:0]
ELSE 
CMP := SRC1[i+63:i] OP5 SRC2[i+63:i]
FI;IF CMP = TRUE
THEN DEST[j] := 1;ELSE DEST[j] := 0; FI;
ELSE DEST[j] := 0 ; zeroing-masking only
FI;
ENDFORDEST[MAX_KL-1:KL] := 0
VCMPPD (VEX.256 Encoded Version)
CMP0 := SRC1[63:0] OP5 SRC2[63:0];CMP1 := SRC1[127:64] OP5 SRC2[127:64];CMP2 := SRC1[191:128] OP5 SRC2[191:128];CMP3 := SRC1[255:192] OP5 SRC2[255:192];IF CMP0 = TRUE
THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0000000000000000H; FI;
IF CMP1 = TRUE
THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;ELSE DEST[127:64] := 0000000000000000H; FI;
IF CMP2 = TRUE
THEN DEST[191:128] := FFFFFFFFFFFFFFFFH;ELSE DEST[191:128] := 0000000000000000H; FI;
IF CMP3 = TRUE
THEN DEST[255:192] := FFFFFFFFFFFFFFFFH;ELSE DEST[255:192] := 0000000000000000H; FI;
VCMPPD (VEX.128 Encoded Version)
CMP0 := SRC1[63:0] OP5 SRC2[63:0];CMP1 := SRC1[127:64] OP5 SRC2[127:64];IF CMP0 = TRUE
DEST[MAXVL-1:128] := 0CMPPD—Compare Packed Double Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-187CMPPD (128-bit Legacy SSE Version)

CMP0 := SRC1[63:0] OP3 SRC2[63:0];CMP1 := SRC1[127:64] OP3 SRC2[127:64];IF CMP0 = TRUE
VCMPPD __mmask8 _mm512_cmp_pd_mask( __m512d a, __m512d b, int imm);
VCMPPD __mmask8 _mm512_cmp_round_pd_mask( __ m512d a, __m512d b, int imm, int sae);
VCMPPD __mmask8 _mm512_mask_cmp_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm);VCMPPD __mmask8 _mm512_mask_cmp_round_pd_mask( __mma sk8 k1, __m512d a, __m512d b, int imm, int sae);
VCMPPD __mmask8 _mm256_cmp_pd_mask( __m256d a, __m256d b, int imm);
VCMPPD __mmask8 _mm256_mask_cmp_pd_mask( __mmask8 k1, __m256d a, __m256d b, int imm);VCMPPD __mmask8 _mm_cmp_pd_mask( __m128d a, __m128d b, int imm);VCMPPD __mmask8 _mm_mask_cmp _pd_mask( __mmask8 k1, __m128 d a, __m128d b, int imm);
VCMPPD __m256 _mm256_cmp_pd(__m256d a, __m256d b, int imm)(V)CMPPD __m128 _mm_cmp_pd(__m128d a, __m128d b, int imm)
Invalid if SNaN operand and invalid if QNaN and predicate as listed in Table 3-1, Denormal.
VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”CMPPS—Compare Packed Single Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-188 Vol. 2ACMPPS—Compare Packed Single Precision Floating-Point Values
Performs a SIMD compare of the packed single precision fl oating-point values in the second source operand and the 
first source operand and returns the result of the comparis on to the destination operand. The comparison predicate 
operand (immediate byte) specifies the type of comparison performed on each of the pairs of packed values. 
source operand can be a ZMM/YMM/XMM register, a 512/25 6/128-bit memory location or a 512/256/128-bit vector 
broadcasted from a 32-bit memory location. The destinat ion operand (first operand) is an opmask register. 
VEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source operand 
(third operand) can be a YMM register or a 256-bit memory  location. The destination operand (first operand) is a 
YMM register. Eight comparisons are performed with results written to the destination operand. The result of each 
comparison is a doubleword mask of all 1s (c omparison true) or all 0s (comparison false).
128-bit Legacy SSE version: The first source and destin ation operand (first operand) is an XMM register. The 
of the corresponding ZMM destination register remain unchanged. Four comparisons are performed with results 
written to bits 127:0 of the destination operand. The result  of each comparison is a doubleword mask of all 1s 
Mode 
Feature 
NP 0F C2 /r ib
CMPPS xmm1, xmm2/m128, imm8A V/V SSE Compare packed single precision floating-point values in 
xmm2/m128 and xmm1 using bits 2:0 of imm8 as a 
VEX.128.0F.WIG C2 /r ib
VCMPPS xmm1, xmm2, xmm3/m128, imm8B V/V AVX Compare packed single precision floating-point values in 
xmm3/m128 and xmm2 using bits 4:0 of imm8 as a comparison predicate.
VEX.256.0F.WIG C2 /r ib
VCMPPS ymm1, ymm2, 
ymm3/m256, imm8B V/V AVX Compare packed single precision floating-point values in 
ymm3/m256 and ymm2 using bits 4:0 of imm8 as a 
EVEX.128.0F.W0 C2 /r ib
VCMPPS k1 {k2}, xmm2, 
xmm3/m128/m32bcst, imm8CV / V A V X 5 1 2 V L
AVX512FCompare packed single precision floating-point values in 
xmm3/m128/m32bcst and xmm2 using bits 4:0 of imm8 as a 
comparison predicate with writemask k2 and leave the result 
in mask register k1.
EVEX.256.0F.W0 C2 /r ib
VCMPPS k1 {k2}, ymm2, 
ymm3/m256/m32bcst, imm8CV / V A V X 5 1 2 V L
ymm3/m256/m32bcst and ymm2 using bits 4:0 of imm8 as a 
comparison predicate with writemask k2 and leave the result in mask register k1.
EVEX.512.0F.W0 C2 /r ib
VCMPPS k1 {k2}, zmm2, 
zmm3/m512/m32bcst{sae}, imm8C V/V AVX512F Compare packed single precision floating-point values in 
zmm3/m512/m32bcst and zmm2 using bits 4:0 of imm8 as a 
B N/A ModRM:reg (w) VEX.vv vv (r) ModRM:r/m (r) imm8
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8CMPPS—Compare Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-189VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source 
operand (third operand) can be an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destina-tion ZMM register are zeroed. Four comparisons are performe d with results written to bits 127:0 of the destination 
operand.
The comparison predicate operand is an 8-bit immediate: 
•For instructions encoded using the VEX prefix and EVEX prefix, bits 4:0 defi ne the type of comparison to be 
performed (see Table 3-1). Bits 5 through 7 of the immediate are reserved. 
•For instruction encodings that do not use VEX prefix, bits  2:0 define the type of comparison to be made (see 
the first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved. 
The unordered relationship is true when at least one of  the two source operands being compared is a NaN; the 
CMPPS instruction, for processors with  “CPUID.1H:ECX.AVX =0”. See Table 3-4. The compiler should treat reserved 
imm8 values as illegal syntax.
:
the correct destination register and that the source operand is left intact.) 
Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table 3-5, soft-
pseudo-ops in addition to the four-o perand VCMPPS instruction. See Table 3-5, where the notation of reg1 and 
reg2 represent either XMM registers or YMM registers. Th e compiler should treat reserved imm8 values as illegal 
syntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic inter-
face. Compilers and assemblers may implement three-oper and pseudo-ops for EVEX en coded VCMPPS instructions 
in a similar fashion by extending the syntax listed in Table 3-5.
:Table 3-4. Pseudo-Op and CMPPS Implementation
Pseudo-Op CMPPS Implementation
CMPEQPS xmm1, xmm2 CMPPS xmm1, xmm2, 0
CMPLTPS xmm1, xmm2 CMPPS xmm1, xmm2, 1
CMPLEPS xmm1, xmm2 CMPPS xmm1, xmm2, 2CMPUNORDPS xmm1, xmm2 CMPPS xmm1, xmm2, 3
CMPNEQPS xmm1, xmm2 CMPPS xmm1, xmm2, 4
CMPNLTPS xmm1, xmm2 CMPPS xmm1, xmm2, 5CMPNLEPS xmm1, xmm2 CMPPS xmm1, xmm2, 6
CMPORDPS xmm1, xmm2 CMPPS xmm1, xmm2, 7CMPPS—Compare Packed Single Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L

3-190 Vol. 2ATable 3-5. Pseudo-Op and VCMPPS Implementation
VCMPEQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 0
VCMPLTPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 1
VCMPLEPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 2
VCMPUNORDPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 3
VCMPNEQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 4
VCMPNLTPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 5
VCMPNLEPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 6
VCMPORDPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 7
VCMPEQ_UQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 8
VCMPNGEPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 9
VCMPNGTPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 0AH
VCMPFALSEPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 0BH
VCMPNEQ_OQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 0CH
VCMPGEPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 0DH
VCMPGTPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 0EH
VCMPTRUEPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 0FH
VCMPEQ_OSPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 10H
VCMPLT_OQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 11H
VCMPLE_OQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 12H
VCMPUNORD_SPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 13H
VCMPNEQ_USPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 14H
VCMPNLT_UQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 15H
VCMPNLE_UQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 16H
VCMPORD_SPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 17H
VCMPEQ_USPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 18H
VCMPNGE_UQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 19H
VCMPNGT_UQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 1AH
VCMPFALSE_OSPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 1BH
VCMPNEQ_OSPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 1CH
VCMPGE_OQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 1DH
VCMPGT_OQPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 1EH
VCMPTRUE_USPS r eg1, reg2, reg3 VCMPPS r eg1, reg2, reg3, 1FHCMPPS—Compare Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-191Operation
0: OP3 := EQ_OQ; OP5 := EQ_OQ;1: OP3 := LT_OS; OP5 := LT_OS;2: OP3 := LE_OS; OP5 := LE_OS;3: OP3 := UNORD_Q; OP5 := UNORD_Q;4: OP3 := NEQ_UQ; OP5 := NEQ_UQ;5: OP3 := NLT_US; OP5 := NLT_US;6: OP3 := NLE_US; OP5 := NLE_US;7: OP3 := ORD_Q; OP5 := ORD_Q;8: OP5 := EQ_UQ;9: OP5 := NGE_US;10: OP5 := NGT_US;11: OP5 := FALSE_OQ;12: OP5 := NEQ_OQ;
14: OP5 := GT_OS;15: OP5 := TRUE_UQ;16: OP5 := EQ_OS;17: OP5 := LT_OQ;18: OP5 := LE_OQ;19: OP5 := UNORD_S;20: OP5 := NEQ_US;21: OP5 := NLT_UQ;22: OP5 := NLE_UQ;23: OP5 := ORD_S;24: OP5 := EQ_US;25: OP5 := NGE_UQ;26: OP5 := NGT_UQ;27: OP5 := FALSE_OS;28: OP5 := NEQ_OS;29: OP5 := GE_OQ;30: OP5 := GT_OQ;31: OP5 := TRUE_US;DEFAULT: Reserved
ESAC;CMPPS—Compare Packed Single Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-192 Vol. 2AVCMPPS (EVEX Encoded Versions) 
i := j * 32IF k2[j] OR *no writemask*
THEN 
THEN
CMP := SRC1[i+31:i] OP5 SRC2[31:0]
ELSE 
CMP := SRC1[i+31:i] OP5 SRC2[i+31:i]
ELSE DEST[j] := 0 ; zeroing-masking onlyFI;
FI;
VCMPPS (VEX.256 Encoded Version)
CMP0 := SRC1[31:0] OP5 SRC2[31:0];CMP1 := SRC1[63:32] OP5 SRC2[63:32];CMP2 := SRC1[95:64] OP5 SRC2[95:64];CMP3 := SRC1[127:96] OP5 SRC2[127:96];CMP4 := SRC1[159:128] OP5 SRC2[159:128];CMP5 := SRC1[191:160] OP5 SRC2[191:160];CMP6 := SRC1[223:192] OP5 SRC2[223:192];CMP7 := SRC1[255:224] OP5 SRC2[255:224];IF CMP0 = TRUE
THEN DEST[31:0] :=FFFFFFFFH;ELSE DEST[31:0] := 000000000H; FI;
THEN DEST[63:32] := FFFFFFFFH;ELSE DEST[63:32] :=000000000H; FI;
THEN DEST[95:64] := FFFFFFFFH;ELSE DEST[95:64] := 000000000H; FI;
THEN DEST[127:96] := FFFFFFFFH;ELSE DEST[127:96] := 000000000H; FI;
IF CMP4 = TRUE
THEN DEST[159:128] := FFFFFFFFH;ELSE DEST[159:128] := 000000000H; FI;
IF CMP5 = TRUE
THEN DEST[191:160] := FFFFFFFFH;ELSE DEST[191:160] := 000000000H; FI;
IF CMP6 = TRUE
THEN DEST[223:192] := FFFFFFFFH;ELSE DEST[223:192] :=000000000H; FI;
IF CMP7 = TRUE
THEN DEST[255:224] := FFFFFFFFH;ELSE DEST[255:224] := 000000000H; FI;
DEST[MAXVL-1:256] := 0CMPPS—Compare Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-193VCMPPS (VEX.128 Encoded Version)
CMP0 := SRC1[31:0] OP5 SRC2[31:0];CMP1 := SRC1[63:32] OP5 SRC2[63:32];CMP2 := SRC1[95:64] OP5 SRC2[95:64];CMP3 := SRC1[127:96] OP5 SRC2[127:96];IF CMP0 = TRUE
THEN DEST[63:32] := FFFFFFFFH;ELSE DEST[63:32] := 000000000H; FI;
THEN DEST[127:96] := FFFFFFFFH;ELSE DEST[127:96] :=000000000H; FI;
CMPPS (128-bit Legacy SSE Version)
CMP0 := SRC1[31:0] OP3 SRC2[31:0];CMP1 := SRC1[63:32] OP3 SRC2[63:32];CMP2 := SRC1[95:64] OP3 SRC2[95:64];CMP3 := SRC1[127:96] OP3 SRC2[127:96];IF CMP0 = TRUE
VCMPPS __mmask16 _mm512_cmp_ps_mask( __m512 a, __m512 b, int imm);
VCMPPS __mmask16 _mm512_cmp_round_ps_mask ( __m512 a, __m512 b, int imm, int sae);
VCMPPS __mmask16 _mm512_mask_cmp_ps_mask( __mmask16 k1, __m512 a, __m512 b, int imm);VCMPPS __mmask16 _mm512_mask_cmp_round_ps_mask( __m mask16 k1, __m512 a, __m512 b, int imm, int sae);
VCMPPS __mmask8 _mm256_cmp_ps_mask( __m256 a, __m256 b, int imm);VCMPPS __mmask8 _mm256_mask_cmp_ps_mask( __ mmask8 k1, __m256 a, __m256 b, int imm);
VCMPPS __mmask8 _mm_cmp_ps_mask(  __m128 a, __m128 b, int imm);
VCMPPS __mmask8 _mm_mask_cmp_ps_mask( __m mask8 k1, __m128 a, __m128 b, int imm);
VCMPPS __m256 _mm256_cmp_ps(__m256 a, __m256 b, int imm)CMPPS __m128 _mm_cmp_ps(__m128 a, __m128 b, int imm)
Invalid if SNaN operand and invalid if QNaN and predicate as listed in Table 3-1, Denormal.CMPPS—Compare Packed Single Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-194 Vol. 2AOther Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-195CMPS/CMPSB/CMPSW/CMPSD/CMP SQ—Compare String Operands
Compares the byte, word, doubleword, or quadword specif ied with the first source op erand with the byte, word, 
doubleword, or quadword specified with the second source operand and sets the status flags in the EFLAGS register 
according to the results.
Both source operands are located in memory. The address of  the first source operand is  read from DS:SI, DS:ESI 
or RSI (depending on the address-size attribute of the inst ruction is 16, 32, or 64, respectively). The address of the 
second source operand is read from ES :DI, ES:EDI or RDI (again depending on the address-size attribute of the 
instruction is 16, 32, or 64). The DS segment may be overridden with a segment override prefix, but the ES 
segment cannot be overridden.
At the assembly-code level, two forms of this instructio n are allowed: the “explicit-operands” form and the “no-
operands” form. The explicit-operands form (specified wi th the CMPS mnemonic) allows the two source operands 
to be specified explicitly. Here, the so urce operands should be symbols that indicate the size and location of the 
source values. This explicit-operand form is provided to  allow documentation. However, note that the documenta-
tion provided by this form can be mi sleading. That is, the source operand symbols must specify the correct type 
(size) of the operands (bytes, words, or doublewords, quadwords), but they do not have to specify the correct loca-Opcode Instruction Op/ 
En64-Bit 
A6 CMPS m8, m8 ZO Valid Valid For legacy mode, compare byte at address DS:(E)SI with 
byte at address ES:(E)DI; For 64-bit mode compare byte 
at address (R|E)SI to byte at address (R|E)DI. The status 
flags are set accordingly.
A7 CMPS m16 , m16 ZO Valid Valid For legacy mode, compare word at address DS:(E)SI 
with word at address ES:(E)DI; For 64-bit mode 
compare word at address (R|E)SI with word at address 
(R|E)DI. The status fl ags are set accordingly.
A7 CMPS m32, m32 ZO Valid Valid For legacy mode, compare dword at address DS:(E)SI at 
dword at address ES:(E)DI; For 64-bit mode compare 
dword at address (R|E)SI at dword at address (R|E)DI. 
The status flags are set accordingly.

En64-Bit 
REX.W + A7 CMPS m64, m64 ZO Valid N.E. Compares quadword at address (R|E)SI with quadword 
at address (R|E)DI and sets the status flags accordingly.
A6 CMPSB ZO Valid Valid For legacy mode, compare byte at address DS:(E)SI with 
byte at address ES:(E)DI; For 64-bit mode compare byte at address (R|E)SI with byte  at address (R|E)DI. The 
status flags are set accordingly.
A7 CMPSW ZO Valid Valid For legacy mode, compare word at address DS:(E)SI 
with word at address ES:(E)DI; For 64-bit mode compare word at address (R|E)SI with word at address 
A7 CMPSD ZO Valid Valid For legacy mode, compare dword at address DS:(E)SI 
with dword at address ES:(E)DI; For 64-bit mode compare dword at address (R|E)SI with dword at 
address (R|E)DI. The status  flags are set accordingly.
REX.W + A7 CMPSQ ZO Valid N.E. Compares quadword at address (R|E)SI with quadword 
ZO N/A N/A N/A N/ACMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-L
3-196 Vol. 2Ation. Locations of the source operands are always specif ied by the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) regis-
ters, which must be loaded correctly before the compare string instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the CMPS instructions. 
Here also the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) regi sters are assumed by the processor to specify the loca-
tion of the source operands. The size of the source oper ands is selected with the mnemonic: CMPSB (byte compar-
ison), CMPSW (word comparison), CMPSD (doubleword comparison), or CMPSQ (quadword comparison using 
REX.W).
After the comparison, the (E/R)SI and (E/R)DI registers increment or decrement automatically according to the 
setting of the DF flag in the EFLAGS register. (If the DF fl ag is 0, the (E/R)SI and (E/R)D I register increment; if the 
DF flag is 1, the registers decrement.) The registers increm ent or decrement by 1 for byte operations, by 2 for word 
operations, 4 for doubleword operations. If operand size is 64, RSI and RDI registers increment by 8 for quadword 
The CMPS, CMPSB, CMPSW, CMPSD, and CMPSQ instructions can be preceded by the REP prefix for block compar-
isons. More often, however, these instructions will be used  in a LOOP construct that takes some action based on the 
setting of the status flags before the next comparis on is made. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat 
String Operation Prefix” in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2B, for a description of the REP prefix.
In 64-bit mode, the instruction’s default address size is 64 bits, 32 bit address size is supported using the prefix 
67H. Use of the REX.W prefix promotes doubleword operation to 64 bits (see CMPSQ ). See the summary chart at 
the beginning of this section for encoding data and limits.
Operation
temp := SRC1 - SRC2;
SetStatusFlags(temp);
IF (64-Bit Mode)
THEN
IF (Byte comparison)
THEN IF DF = 0
THEN 
(R|E)SI := (R|E)SI + 1; 
(R|E)DI := (R|E)DI + 1; 
ELSE 
(R|E)SI := (R|E)SI – 1; (R|E)DI := (R|E)DI – 1; 
FI;
ELSE IF (Word comparison)
THEN IF DF 
= 0
THEN 
(R|E)SI := (R|E)SI + 2; 
(R|E)DI := (R|E)DI + 2; 
ELSE 
(R|E)SI := (R|E)SI – 2; (R|E)DI := (R|E)DI – 2; 
FI;
ELSE IF (Doubleword comparison)
THEN IF DF 
= 0
THEN 
(R|E)SI := (R|E)SI + 4; 
(R|E)DI := (R|E)DI + 4; 
ELSE 
(R|E)SI := (R|E)SI – 4; (R|E)DI := (R|E)DI – 4; 
FI;CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-197ELSE (* Quadword comparison *)
(R|E)SI := (R|E)SI + 8; 
(R|E)DI := (R|E)DI + 8; 
ELSE 
(R|E)SI := (R|E)SI – 8; (R|E)DI := (R|E)DI – 8; 
FI;
FI;
ELSE (* Non-64-bit Mode *)
IF (byte comparison)THEN IF DF 
= 0
THEN 
(E)SI := (E)SI + 1; 
(E)DI := (E)DI + 1; 
ELSE 
(E)SI := (E)SI – 1; (E)DI := (E)DI – 1; 
FI;
THEN IF DF
 = 0
(E)SI := (E)SI + 2; 
(E)DI := (E)DI + 2; 
ELSE 
(E)SI := (E)SI – 2; (E)DI := (E)DI – 2; 
FI;
ELSE (* Doubleword comparison *)
THEN IF DF 
= 0
(E)SI := (E)SI + 4; 
(E)DI := (E)DI + 4; 
ELSE 
(E)SI := (E)SI – 4; (E)DI := (E)DI – 4; 
FI;
FI;
FI;
The CF, OF, SF, ZF, AF, and PF flags are set accord ing to the temporary result of the comparison.
#UD If the LOCK prefix is used.CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-L
3-198 Vol. 2AReal-Address Mode Exceptions
#UD If the LOCK prefix is used.CMPSD—Compare Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-199CMPSD—Compare Scalar Double Pr ecision Floating-Point Value
Compares the low double precision floating-point values in  the second source operand and the first source operand 
and returns the result of the comparison to the destin ation operand. The comparison predicate operand (imme-
diate operand) specifies the type of comparison performed. 
second source operand (second operand) can be an XMM regi ster or 64-bit memory location. Bits (MAXVL-1:64) of 
the corresponding YMM destination register remain unchanged . The comparison result is a quadword mask of all 1s 
(comparison true) or all 0s (comparison false). 
VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source 
operand (third operand) can be an XMM register or a 64-bit  memory location. The result is stored in the low quad-
word of the destination operand; the high quadword is fi lled with the contents of the high quadword of the first 
source operand. Bits (MAXVL-1:128) of the destination ZM M register are zeroed. The comparison result is a quad-
word mask of all 1s (comparison true) or all 0s (comparison false). 
EVEX encoded version: The first source operand (second op erand) is an XMM register. The second source operand 
can be a XMM register or a 64-bit memory location. The de stination operand (first operan d) is an opmask register. 
The comparison result is a single mask bit of 1 (compariso n true) or 0 (comparison false), written to the destination 
starting from the LSB according to the writemask k2. Bits  (MAX_KL-1:128) of the destination register are cleared.
•For instructions encoded using the VEX prefix, bits 4:0 define the type of comparis on to be performed (see 
Table 3-1). Bits 5 through 7 of the immediate are reserved. 
“not-greater than”, and “not-greater-than-or-equal relati ons” predicates. These comparisons can be made either Opcode/
Mode 
Feature 
F2 0F C2 /r ib

Mode 
Feature 
CMPSD xmm1, xmm2/m64, imm8A V/V SSE2 Compare low double precision floating-point value in 
xmm2/m64 and xmm1 using bits 2:0 of imm8 as comparison 
predicate.
VEX.LIG.F2.0F.WIG C2 /r ib
VCMPSD xmm1, xmm2, xmm3/m64, imm8B V/V AVX Compare low double precision floating-point value in 
xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison 
EVEX.LLIG.F2.0F.W1 C2 /r ib
VCMPSD k1 {k2}, xmm2, 
xmm3/m64{sae}, imm8C V/V AVX512F Compare low double precision floating-point value in 
predicate with writemask k2 and leave the result in mask register k1.
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8CMPSD—Compare Scalar Double Pr ecision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-200 Vol. 2Aby using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison) 
CMPSD instruction, for processors with “CPUID.1H:ECX. AVX =0”. See Table 3-6. The compiler should treat 
:
The greater-than relations that the processor does not implement require more than one instruction to emulate in software and therefore should not be implemented as ps eudo-ops. (For these, the programmer should reverse the 
Processors with “CPUID.1H:ECX.AVX =1” implement the full co mplement of 32 predicates shown in Table 3-7, soft-
pseudo-ops in addition to the four-operand VCMPSD instru ction. See Table 3-7, where the notations of reg1 reg2, 
and reg3 represent either XMM registers or YMM register s. The compiler should treat reserved imm8 values as 
illegal syntax. Alternately, intrinsics can map the pseudo-ops  to pre-defined constants to support a simpler intrinsic 
interface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPSD instructions in a similar fashion by ex tending the syntax listed in Table 3-7.
:Table 3-6. Pseudo-Op and CMPSD Implementation
Pseudo-Op CMPSD Implementation
CMPEQSD xmm1, xmm2 CMPSD xmm1, xmm2, 0
CMPLTSD xmm1, xmm2 CMPSD xmm1, xmm2, 1CMPLESD xmm1, xmm2 CMPSD xmm1, xmm2, 2
CMPUNORDSD xmm1, xmm2 CMPSD xmm1, xmm2, 3
CMPNEQSD xmm1, xmm2 CMPSD xmm1, xmm2, 4CMPNLTSD xmm1, xmm2 CMPSD xmm1, xmm2, 5CMPNLESD xmm1, xmm2 CMPSD xmm1, xmm2, 6
CMPORDSD xmm1, xmm2 CMPSD xmm1, xmm2, 7
Table 3-7. Pseudo-Op and VCMPSD Implementation
Pseudo-Op CMPSD ImplementationVCMPEQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0
VCMPLTSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1VCMPLESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 2
VCMPUNORDSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 3
VCMPNEQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 4VCMPNLTSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 5
VCMPNLESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 6
VCMPORDSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 7VCMPEQ_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 8
VCMPNGESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 9
VCMPNGTSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0AHVCMPFALSESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0BH
VCMPNEQ_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0CH
VCMPGESD reg1, reg2, reg3 VC MPSD reg1, reg2, reg3, 0DHCMPSD—Compare Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-201Software should ensure VCMPSD is encoded with VEX.L= 0. Encoding VCMPSD with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.
Operation
0: OP3 := EQ_OQ; OP5 := EQ_OQ;1: OP3 := LT_OS; OP5 := LT_OS;2: OP3 := LE_OS; OP5 := LE_OS;3: OP3 := UNORD_Q; OP5 := UNORD_Q;4: OP3 := NEQ_UQ; OP5 := NEQ_UQ;5: OP3 := NLT_US; OP5 := NLT_US;6: OP3 := NLE_US; OP5 := NLE_US;7: OP3 := ORD_Q; OP5 := ORD_Q;8: OP5 := EQ_UQ;9: OP5 := NGE_US;10: OP5 := NGT_US;11: OP5 := FALSE_OQ;12: OP5 := NEQ_OQ;13: OP5 := GE_OS;14: OP5 := GT_OS;15: OP5 := TRUE_UQ;16: OP5 := EQ_OS;17: OP5 := LT_OQ;18: OP5 := LE_OQ;19: OP5 := UNORD_S;20: OP5 := NEQ_US;21: OP5 := NLT_UQ;VCMPGTSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0EH
VCMPTRUESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0FH
VCMPEQ_OSSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 10H
VCMPLT_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 11HVCMPLE_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 12H
VCMPUNORD_SSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 13H
VCMPNEQ_USSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 14H
VCMPNLT_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 15H
VCMPNLE_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 16H
VCMPORD_SSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 17HVCMPEQ_USSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 18HVCMPNGE_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 19H
VCMPNGT_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1AH
VCMPFALSE_OSSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1BHVCMPNEQ_OSSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1CH
VCMPGE_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1DH
VCMPGT_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1EHVCMPTRUE_USSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1FHTable 3-7. Pseudo-Op and VCMPSD Implementation
Pseudo-Op CMPSD ImplementationCMPSD—Compare Scalar Double Pr ecision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-202 Vol. 2A22: OP5 := NLE_UQ;
23: OP5 := ORD_S;24: OP5 := EQ_US;25: OP5 := NGE_UQ;26: OP5 := NGT_UQ;27: OP5 := FALSE_OS;28: OP5 := NEQ_OS;29: OP5 := GE_OQ;30: OP5 := GT_OQ;31: OP5 := TRUE_US;DEFAULT: Reserved
ESAC;
VCMPSD (EVEX Encoded Version) 
CMP0 := SRC1[63:0] OP5 SRC2[63:0];
IF k2[0] or *no writemask*
THEN IF CMP0 = TRUE
THEN DEST[0] := 1;ELSE DEST[0] := 0; FI;
ELSE DEST[0] := 0 ; zeroing-masking only
FI;DEST[MAX_KL-1:1] := 0
CMPSD (128-bit Legacy SSE Version)
CMP0 := DEST[63:0] OP3 SRC[63:0];IF CMP0 = TRUETHEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0000000000000000H; FI;DEST[MAXVL-1:64] (Unmodified)
VCMPSD (VEX.128 Encoded Version)
CMP0 := SRC1[63:0] OP5 SRC2[63:0];IF CMP0 = TRUETHEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0000000000000000H; FI;DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
VCMPSD __mmask8 _mm_cmp_sd_mask( __m128d a, __m128d b, int imm);VCMPSD __mmask8 _mm_cmp_round_sd_mask( __m 128d a, __m128d b, int imm, int sae);
VCMPSD __mmask8 _mm_mask_cmp_sd_mask( __mma sk8 k1, __m128d a, __m128d b, int imm);
VCMPSD __mmask8 _mm_mask_cmp_round_sd_mask( __mmask 8 k1, __m128d a, __m128d b, int imm, int sae);
(V)CMPSD __m128d _mm_cmp_sd(__m128d a, __m128d b, const int imm)
Invalid if SNaN operand, Invalid if QNaN an d predicate as listed in Table 3-1, Denormal.
VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”CMPSS—Compare Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-203CMPSS—Compare Scalar Single Pr ecision Floating-Point Value
Compares the low single precision floating-point values in  the second source operand and the first source operand 
second source operand (second operand) can be an XMM regi ster or 32-bit memory location. Bits (MAXVL-1:32) of 
the corresponding YMM destination register remain unchange d. The comparison result is a doubleword mask of all 
1s (comparison true) or all 0s (comparison false). 
operand (third operand) can be an XMM register or a 32-bit memory location. The result is stored in the low 32 bits 
of the destination operand; bits 127:32 of the destination operand are copied from the first source operand. Bits

of the destination operand; bits 127:32 of the destination operand are copied from the first source operand. Bits 
(MAXVL-1:128) of the destination ZMM re gister are zeroed. The comparison resu lt is a doubleword mask of all 1s 
can be a XMM register or a 32-bit memory location. The de stination operand (first operan d) is an opmask register. 
starting from the LSB according to the writemask k2. Bits (MAX_KL-1:128) of the destination register are cleared. 
of all 1s corresponds to a QNaN. Opcode/
Mode 
Feature 
F3 0F C2 /r ib
CMPSS xmm1, xmm2/m32, imm8A V/V SSE Compare low single precision floating-point value in 
xmm2/m32 and xmm1 using bits 2:0 of imm8 as 
VEX.LIG.F3.0F.WIG C2 /r ib
VCMPSS xmm1, xmm2, xmm3/m32, imm8B V/V AVX Compare low single prec ision floating-point value in 
xmm3/m32 and xmm2 using bits 4:0 of imm8 as comparison predicate.
EVEX.LLIG.F3.0F.W0 C2 /r ib
VCMPSS k1 {k2}, xmm2, 
xmm3/m32{sae}, imm8C V/V AVX512F Compare low single prec ision floating-point value in 
xmm3/m32 and xmm2 using bits 4:0 of imm8 as 
C Tuple1 Scalar ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) imm8CMPSS—Compare Scalar Single Pr ecision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-204 Vol. 2ANote that processors with “CPUID.1H: ECX.AVX =0” do not implement the “greater-than”, “greater-than-or-equal”, 
by using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison) 
CMPSS instruction, for processors with “CPUID.1H:ECX.AVX =0”. See Table 3-8. The compiler should treat reserved 
:
The greater-than relations that the processor does not implement require more than one instruction to emulate in 
operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.) 
pseudo-ops in addition to the four-operand VCMPSS instru ction. See Table 3-9, where the notations of reg1 reg2, 
interface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPSS 
instructions in a similar fashion by ex tending the syntax listed in Table 3-9.
:Table 3-8. Pseudo-Op and CMPSS Implementation
Pseudo-Op CMPSS Implementation
CMPEQSS xmm1, xmm2 CMPSS xmm1, xmm2, 0CMPLTSS xmm1, xmm2 CMPSS xmm1, xmm2, 1CMPLESS xmm1, xmm2 CMPSS xmm1, xmm2, 2
CMPUNORDSS xmm1, xmm2 CMPSS xmm1, xmm2, 3
CMPNEQSS xmm1, xmm2 CMPSS xmm1, xmm2, 4CMPNLTSS xmm1, xmm2 CMPSS xmm1, xmm2, 5
CMPNLESS xmm1, xmm2 CMPSS xmm1, xmm2, 6
CMPORDSS xmm1, xmm2 CMPSS xmm1, xmm2, 7
Table 3-9. Pseudo-Op an d VCMPSS Implementation
VCMPEQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0VCMPLTSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1
VCMPLESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 2
VCMPUNORDSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 3VCMPNEQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 4
VCMPNLTSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 5
VCMPNLESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 6VCMPORDSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 7
VCMPEQ_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 8
VCMPNGESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 9VCMPNGTSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0AH
VCMPFALSESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0BHCMPSS—Compare Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-205Software should ensure VCMPSS is encoded with VEX.L= 0. Encoding VCMPSS with VEX.L=1 may encounter unpre-
Operation
0: OP3 := EQ_OQ; OP5 := EQ_OQ;1: OP3 := LT_OS; OP5 := LT_OS;2: OP3 := LE_OS; OP5 := LE_OS;3: OP3 := UNORD_Q; OP5 := UNORD_Q;4: OP3 := NEQ_UQ; OP5 := NEQ_UQ;5: OP3 := NLT_US; OP5 := NLT_US;6: OP3 := NLE_US; OP5 := NLE_US;7: OP3 := ORD_Q; OP5 := ORD_Q;8: OP5 := EQ_UQ;9: OP5 := NGE_US;10: OP5 := NGT_US;11: OP5 := FALSE_OQ;12: OP5 := NEQ_OQ;13: OP5 := GE_OS;14: OP5 := GT_OS;15: OP5 := TRUE_UQ;16: OP5 := EQ_OS;17: OP5 := LT_OQ;18: OP5 := LE_OQ;VCMPNEQ_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0CH
VCMPGESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0DH
VCMPGTSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0EH
VCMPTRUESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0FHVCMPEQ_OSSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 10H
VCMPLT_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 11H
VCMPLE_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 12HVCMPUNORD_SSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 13H
VCMPNEQ_USSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 14H
VCMPNLT_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 15HVCMPNLE_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 16HVCMPORD_SSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 17H
VCMPEQ_USSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 18H
VCMPNGE_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 19HVCMPNGT_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1AH
VCMPFALSE_OSSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1BH
VCMPNEQ_OSSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1CHVCMPGE_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1DH
VCMPGT_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1EH
VCMPTRUE_USSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1FHTable 3-9. Pseudo-Op and VCMPSS Implementation
Pseudo-Op CMPSS ImplementationCMPSS—Compare Scalar Single Pr ecision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-206 Vol. 2A19: OP5 := UNORD_S;
20: OP5 := NEQ_US;21: OP5 := NLT_UQ;22: OP5 := NLE_UQ;23: OP5 := ORD_S;24: OP5 := EQ_US;25: OP5 := NGE_UQ;26: OP5 := NGT_UQ;27: OP5 := FALSE_OS;28: OP5 := NEQ_OS;29: OP5 := GE_OQ;30: OP5 := GT_OQ;31: OP5 := TRUE_US;DEFAULT: Reserved
ESAC;
VCMPSS (EVEX Encoded Version) 
CMP0 := SRC1[31:0] OP5 SRC2[31:0];
CMPSS (128-bit Legacy SSE Version)
CMP0 := DEST[31:0] OP3 SRC[31:0];IF CMP0 = TRUETHEN DEST[31:0] := FFFFFFFFH;ELSE DEST[31:0] := 00000000H; FI;DEST[MAXVL-1:32] (Unmodified)
VCMPSS (VEX.128 Encoded Version)
CMP0 := SRC1[31:0] OP5 SRC2[31:0];IF CMP0 = TRUETHEN DEST[31:0] := FFFFFFFFH;ELSE DEST[31:0] := 00000000H; FI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
VCMPSS __mmask8 _mm_cmp_ss_mask( __m128 a, __m128 b, int imm);VCMPSS __mmask8 _mm_cmp_round_ss_mask( __m 128 a, __m128 b, int imm, int sae);
VCMPSS __mmask8 _mm_mask_cmp_ss_mask( __mm ask8 k1, __m128 a, __m128 b, int imm);

ESAC;
VCMPSS __mmask8 _mm_mask_cmp_rou nd_ss_mask( __mmask8 k1, __m128 a,  __m128 b, int imm, int sae);
(V)CMPSS __m128 _mm_cmp_ss(__m128 a, __m128 b, const int imm)
Invalid if SNaN operand, Invalid if QNaN an d predicate as listed in Table 3-1, Denormal.CMPSS—Compare Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-207Other Exceptions
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”CMPXCHG—Compare and ExchangeINSTRUCTION SET REFERENCE, A-L
3-208 Vol. 2ACMPXCHG—Compare and Exchange
Compares the value in the AL, AX, EAX, or RAX register with the first operand (destination operand). If the two 
values are equal, the second operand (source operand) is  loaded into the destination operand. Otherwise, the 
destination operand is loaded into the AL, AX, EAX or RAX register. RAX register  is available only in 64-bit mode.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the 
interface to the processor’s bus, the destination operand re ceives a write cycle without regard to the result of the 
comparison. The destination operand is written back if the comparison fails;  otherwise, the source operand is 
written into the destination. (The processor never produces  a locked read without also producing a locked write.)
IA-32 Architecture Compatibility
This instruction is not supported on Intel pr ocessors earlier than the Intel486 processors.
Operation
(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, or quadword comparison is being performed *)
TEMP := DESTIF accumulator 
= TEMP
THEN
ZF := 1;DEST := SRC;
ELSE
ZF := 0;accumulator := TEMP;DEST := TEMP;
En64-Bit 
0F B0/r
CMPXCHG r/m8, r8MR Valid Valid* Compare AL with r/m8. If eq ual, ZF is set and r8 is loaded into 
r/m8. Else, clear ZF and load r/m8 into AL.
REX + 0F B0/r
CMPXCHG r/m8**,r8MR Valid N.E. Compare AL with r/m8. If equa l, ZF is set and r8  is loaded into 
0F B1/r
CMPXCHG r/m16, r16MR Valid Valid* Compare AX wi th r/m16. If equal, ZF is set and r16 is loaded 
into r/m16. Else, clear ZF and load r/m16 into AX.
0F B1/r
CMPXCHG r/m32, r32MR Valid Valid* Compare EAX with r/m32. If  equal, ZF is set and r32 is loaded 
into r/m32. Else, clear ZF and load r/m32 into EAX.
REX.W + 0F B1/r
CMPXCHG r/m64, r64MR Valid N.E. Compare RAX with  r/m64. If equal, ZF is  set and r64 is loaded 
into r/m64. Else, clear ZF and load r/m64 into RAX.
NOTES:
* See the IA-32 Architecture Compatibility section below. 
** In 64-bit mode, r/m8 can not be encoded to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH. 
MR ModRM:r/m (r, w) ModRM:reg (r) N/A N/ACMPXCHG—Compare and ExchangeINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-209Flags Affected
The ZF flag is set if the values in the destination operan d and register AL, AX, or EAX are equal; otherwise it is 
cleared. The CF, PF, AF, SF, and OF flags are set a ccording to the results of the comparison operation.
#UD If the LOCK prefix is used but th e destination is not a memory operand.CMPXCHG8B/CMPXCHG16B—Compa re and Exchange BytesINSTRUCTION SET REFERENCE, A-L
3-210 Vol. 2ACMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes
Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand size is 128 bits) with the operand 
(destination operand). If the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored 
in the destination operand. Otherwise,  the value in the destination operand is loaded into EDX:EAX (or RDX:RAX). 
The destination operand is an 8-byte me mory location (or 16-byte memory location if operand size is 128 bits). For 
the EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the 
low-order 32 bits of a 64-bit value. For the RDX:RAX an d RCX:RBX register pairs, RD X and RCX contain the high-
order 64 bits and RAX and RBX contain the low-order 64bits of a 128-bit value. 
In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes operation to 128 bits. Note that 
CMPXCHG16B requires that the destination (memory) oper and be 16-byte aligned. See the summary chart at the 
beginning of this section for encoding data and limits. For information on the CPUID flag that indicates CMPX-
CHG16B, see page 3-243 .
This instruction encoding is not supported on Intel processors earlier than the Pentium processors.Opcode/
En64-Bit 
0F C7 /1 
CMPXCHG8B m64M Valid Valid* Compare EDX:EAX with m6 4. If equal, set ZF and load 
ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.
REX.W + 0F C7 /1 
CMPXCHG16B m128M Valid N.E. Compare RDX:RAX with m128. If equal, set ZF and load 
RCX:RBX into m128. Else, clea r ZF and load m128 into 
RDX:RAX.
NOTES:
*See IA-32 Architecture Compatibility section below.
M ModRM:r/m (r, w) N/A N/A N/ACMPXCHG8B/CMPXCHG16B—Compare and Exchange BytesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-211Operation
IF (64-Bit Mode and OperandSize = 64)
THEN
TEMP128 := DESTIF (RDX:RAX 
= TEMP128)
THEN
ZF := 1;DEST := RCX:RBX;
ELSE
ZF := 0;RDX:RAX := TEMP128;DEST := TEMP128;FI;
FI
ELSE
TEMP64 := DEST;
IF (EDX:EAX 
= TEMP64)
THEN
ZF := 1;DEST := ECX:EBX;
ELSE
ZF := 0;EDX:EAX := TEMP64;DEST := TEMP64;FI;
FI;
FI;
The ZF flag is set if the destination operand and EDX:EAX ar e equal; otherwise it is cleared. The CF, PF, AF, SF, and 
OF flags are unaffected.
#UD If the destination is not a memory operand.
#UD If the destination operand is not a memory location.

= TEMP64)
THEN
ELSE
FI;
FI;
#SS If a memory operand effective address is outside the SS segment limit.CMPXCHG8B/CMPXCHG16B—Compa re and Exchange BytesINSTRUCTION SET REFERENCE, A-L
3-212 Vol. 2AVirtual-8086 Mode Exceptions
If memory operand for CMPXCHG16B is  not aligned on a 16-byte boundary.
If CPUID.01H:ECX.CMPXCHG16B[bit 13] = 0.
current privilege level is 3.COMISD—Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-213COMISD—Compare Scalar Ordered Double Precis ion Floating-Point Values and Set EFLAGS
Compares the double precision floating-point values in th e low quadwords of operand 1 (first operand) and operand 
2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register accordin g to the result (unordered, 
greater than, less than, or equal). The OF, SF, and AF flags in  the EFLAGS register are set to 0. The unordered result 
is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM re gister or a 64 bit memory location. The COMISD instruc-
tion differs from the UCOMISD instruction in that it sign als a SIMD floating-point invalid operation exception (#I) 
when a source operand is either a QNaN or SNaN. The UC OMISD instruction signals an invalid operation exception 
only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmask ed SIMD floating-point exception is generated.
VEX.vvvv and EVEX.vvvv ar e reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISD is encoded with VE X.L=0. Encoding VCOMISD with VEX.L=1 may encounter 
unpredictable behavior across different processor generations.
Operation
COMISD (All Versions)
RESULT := OrderedCompare(DEST[63:0] <> SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF := 111;GREATER_THAN: ZF,PF,CF := 000;LESS_THAN: ZF,PF,CF := 001;EQUAL: ZF,PF,CF := 100;
ESAC;OF, AF, SF := 0; }Opcode/
Mode 
Feature 
66 0F 2F /r
COMISD xmm1, xmm2/m64A V/V SSE2 Compare low double precision floating-point values in 
xmm1 and xmm2/mem64 and set the EFLAGS flags 
VEX.LIG.66.0F.WIG 2F /r
VCOMISD xmm1, xmm2/m64A V/V AVX Compare low double precision floating-point values in 
xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.
EVEX.LLIG.66.0F.W1 2F /r
VCOMISD xmm1, xmm2/m64{sae}B V/V AVX512F Compare low double precision floating-point values in 
A N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
B Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/ACOMISD—Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-L
3-214 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
VCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae); 
VCOMISD int _mm_comieq_sd (__m128d a, __m128d b)VCOMISD int _mm_comilt_sd (__m128d a, __m128d b)VCOMISD int _mm_comile_sd (__m128d a, __m128d b)VCOMISD int _mm_comigt_sd (__m128d a, __m128d b)VCOMISD int _mm_comige_sd (__m128d a, __m128d b)VCOMISD int _mm_comineq_sd (__m128d a, __m128d b)
Invalid (if SNaN or QNaN operands), Denormal.
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
Additionally:
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.COMISS—Compare Scalar Ordered Single Prec ision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-215COMISS—Compare Scalar Ordered Single Precis ion Floating-Point Values and Set EFLAGS
Compares the single precision floating-point values in th e low quadwords of operand 1 (first operand) and operand 
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location. The COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid opera-
tion exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid operation exception only if a source operand is an SNaN.
Software should ensure VCOMISS is encoded with VE X.L=0. Encoding VCOMISS with VEX.L=1 may encounter 
Operation
COMISS (All Versions)
RESULT := OrderedCompare(DEST[31:0] <> SRC[31:0]) {
Mode 
Feature 
NP 0F 2F /r
COMISS xmm1, xmm2/m32A V/V SSE Compare low single precision floating-point values in 
xmm1 and xmm2/mem32 and set the EFLAGS flags 
VEX.LIG.0F.WIG 2F /r
VCOMISS xmm1, xmm2/m32A V/V AVX Compare low single precision floating-point values in 
xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.
EVEX.LLIG.0F.W0 2F /r
VCOMISS xmm1, xmm2/m32{sae}B V/V AVX512F Compare low single precision floating-point values in 
B Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/ACOMISS—Compare Scalar Ordered Single Prec ision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-L
3-216 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
VCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae); 
VCOMISS int _mm_comieq_ss (__m128 a, __m128 b)VCOMISS int _mm_comilt_ss (__m128 a, __m128 b)VCOMISS int _mm_comile_ss (__m128 a, __m128 b)VCOMISS int _mm_comigt_ss (__m128 a, __m128 b)VCOMISS int _mm_comige_ss (__m128 a, __m128 b)VCOMISS int _mm_comineq_ss (__m128 a, __m128 b)
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-217CPUID—CPU Identification
The ID flag (bit 21) in the EFLAGS register indicates suppo rt for the CPUID instruction. If a software procedure can 
set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction 
operates the same in non-64-bit modes and 64-bit mode.
CPUID returns processor identification and feature in formation in the EAX, EBX, ECX, and EDX registers.1 The 
instruction’s output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well). 
For example, the following pseudocode loads EAX with 00 H and causes CPUID to return a Maximum Return Value 
and the Vendor Identification String in the appropriate registers:
MOV EAX, 00H
CPUID
Table 3-8 shows information returned, depending on the initial value loaded into the EAX register. 
Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX 
is higher than the maximum input value for basic or extended function for that processor then the data for the 
highest basic information leaf is re turned. For example, using some Intel processors, the following is true:
CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)

CPUID
CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *) 
CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *) CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)
2 
CPUID.EAX =1FH (* Returns V2 Extended Topology Enumeration leaf. *)2 
CPUID.EAX = 80000008H (* Returns li near/physical addr ess size data. *)
CPUID.EAX = 8000000AH (* INVA LID: Returns same informat ion as CPUID.EAX = 0BH. *)
If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on 
that processor then 0 is returned in all the registers.
When CPUID returns the highest basic leaf information as a result of an invalid inpu t EAX value, any dependence 
on input ECX value in the basic leaf is honored.
CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution 
guarantees that any modifications to flags, registers, an d memory for previous instructions are completed before 
the next instruction is fetched and executed.
See also:  
“Serializing Instructions” in Chapter 9, “Mul tiple-Processor Management,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3A.
“Caching Translation Information” in Chapter 4, “Paging,” in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 3A.Opcode Instruction Op/ 
En64-Bit 
0F A2 CPUID ZO Valid Valid Returns processor identification and feature 
information to the EAX, EBX, ECX, and EDX 
registers, as determined  by input entered in 
EAX (in some case s, ECX as well).
1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes.
2. CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence of CPUID leaf 1FH befor e 
using leaf 0BH.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-218 Vol. 2ATable 3-8.  Information Retu rned by CPUID Instruction
Initial EAX 
Value Information Provided about the Processor
Basic CPUID Information
0H EAX Maximum Input Value for Basic CPUID Information.
EBX “Genu”ECX “ntel”
EDX “ineI”
01H EAX Version Information: Type, Family, Model, and Stepping ID (see Figure 3-6).
EBX Bits 07-00: Brand Index.
Bits 15-08: CLFLUSH line size (Value ∗ 8 = cache line size in bytes;  used also by CLFLUSHOPT).
Bits 23-16: Maximum number of ad dressable IDs for logical processors in this physical package*. 
Bits 31-24: Initial APIC ID**.
ECX Feature Information (see Figure 3-7 and Table 3-10).
EDX Feature Information (see Figure 3-8 and Table 3-11).
NOTES: 
*T h e  n e a r e s t  p o w e r - o f - 2  i n teger that is not smaller than EBX[23:16] is the number of unique initial APIC
IDs reserved for addressing different logical processors in a physical package. This field is only valid ifCPUID.1.EDX.HTT[bit 28]= 1.
**The 8-bit initial APIC ID in EBX[31:24] is replaced by the 32-bit x2APIC ID, available in Leaf 0BH and 
Leaf 1FH.
02H EAX Cache and TLB Information (see Table 3-12).
EBX Cache and TLB Information.
ECX Cache and TLB Information.
EDX Cache and TLB Information.
03H EAX Reserved.
EBX Reserved.
ECX Bits 00-31 of 96-bit processor se rial number. (Available  in Pentium III processo r only; otherwise, the 
value in this register is reserved.)
EDX Bits 32-63 of 96-bit processor se rial number. (Available  in Pentium III processo r only; otherwise, the 
NOTES: 
Processor serial number (PSN) is no t supported in the Pentium 4 proce ssor or later. On all models, use
the PSN flag (returned using CPUID) to check for PSN support before accessing the feature. 
CPUID leaves above 2 and below 80000000H are visible only when IA32_MISC_ENABLE[bit 22 ] has its default value of 0.
Deterministic Cache Parameters Leaf (Initial EAX Value = 04H)
04H NOTES:
Leaf 04H output depends on the initial value in ECX.* 
See also: “INPUT EAX = 04H: Returns Deterministi c Cache Parameters for Each Level” on page 251.
EAX Bits 04-00: Cache Type Field.
0 = Null - No more caches.1 = Data Cache. 
2 = Instruction Cache.
3 = Unified Cache.4-31 = Reserved.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-219Bits 07-05: Cache Level (starts at 1). 
Bit 08: Self Initializing  cache level (does not ne ed SW initialization).
Bit 09: Fully Associative cache.
Bits 13-10: Reserved.
Bits 25-14: Maximum number of addressable IDs for logical proces sors sharing this cache**, ***. 
Bits 31-26: Maximum number of addressable IDs for processor cores in the physical 
package**, ****, *****.
EBX Bits 11-00: L = System Coherency Line Size**.
Bits 21-12: P = Physical Line partitions**.
Bits 31-22: W = Ways of associativity**.
ECX Bits 31-00: S = Number of Sets**.EDX Bit 00: Write-Back Invalidate/Invalidate.
0 = WBINVD/INVD from threads sharing this cache acts upon lower level cach es for threads sharing this 
cache.
1 = WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing 
this cache.
Bit 01: Cache Inclusiveness.
0 = Cache is not inclusive of lower cache levels.
1 = Cache is inclusive of  lower cache levels.
Bit 02: Complex Cache Indexing.
0 = Direct mapped cache.
1 = A complex function is used to index the cache, potentially using all address bits.
Bits 31-03: Reserved = 0.
NOTES:
* If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n+1 is invalid if sub-
leaf n returns EAX[4:0] as 0.
** Add one to the return value to get the result. 
***The nearest power-of-2 in teger that is not smaller than (1 + EA X[25:14]) is the numb er of unique ini-
tial APIC IDs reserved for ad dressing different logical pr ocessors sharing this cache.
**** The nearest power-of-2 integer th at is not smaller than (1 + EAX[ 31:26]) is the number of unique 
Core_IDs reserved for addressing different processor co res in a physical package. Core ID is a subset of 
bits of the initial APIC ID. 
***** The returned value is constant for valid initial values  in ECX. Valid ECX va lues start from 0. 
MONITOR/MWAIT Leaf (Initial EAX Value = 05H)
05H EAX Bits 15-00: Smallest monito r-line size in bytes (default is processor' s monitor granularity). 
Bits 31-16: Reserved = 0.
EBX Bits 15-00: Largest monitor-line size in byte s (default is processor' s monitor granularity). 
ECX Bit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported.
Bit 01: Supports treating  interrupts as break-event for MWAIT, even when interrupts disabled.
Bits 31-02: Reserved. 
EDX Bits 03-00: Number of C0* su b C-states supported using MWAIT.
Bits 07-04: Number of C1* sub C-states supported using MWAIT.
Bits 11-08: Number of C2* sub C-states supported using MWAIT.
Bits 15-12: Number of C3* sub C-states supported using MWAIT.
Bits 19-16: Number of C4* sub C-states supported using MWAIT.
Bits 23-20: Number of C5* sub C-states supported using MWAIT.
Bits 27-24: Number of C6* sub C-states supported using MWAIT.
Bits 31-28: Number of C7* sub C-states supported using MWAIT.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Value Information Provided about the ProcessorCPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-220 Vol. 2ANOTE:
* The definition of C0 through C7 states for MWAIT extension are processor-specific C-states, not ACPI C-
states.
Thermal and Power Management Le af (Initial EAX Value = 06H)
06H EAX Bit 00: Digital temperatur e sensor is supported if set.
Bit 01: Intel Turbo Boos t Technology available (see description of IA32_MISC_ENABLE[38]).
Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.
Bit 03: Reserved.
Bit 04: PLN. Power limit notificati on controls are supported if set.
Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.
Bit 06: PTM. Package thermal ma nagement is supported if set.
Bit 07: HWP. HWP base registers (IA32_PM_ENABL E[bit 0], IA32_HWP_CAPAB ILITIES, IA32_HWP_RE-
QUEST, IA32_HWP_STATUS)  are supported if set.
Bit 08: HWP_Notification . IA32_HWP_INTERRUPT MSR is supported if set.
Bit 09: HWP_Activity_Window.  IA32_HWP_REQUEST[bits 41: 32] is supported if set.
Bit 10: HWP_Energy_Performance_Preference. IA32 _HWP_REQUEST[bits 31:24] is supported if set.
Bit 11: HWP_Package_Level_Re quest. IA32_HWP_REQUEST_PKG  MSR is supported if set.
Bit 12: Reserved.
Bit 13: HDC. HDC base register s IA32_PKG_HDC_CTL, IA32_PM_CTL1 , IA32_THREAD_STALL MSRs are 
supported if set.Bit 14: Intel® Turbo Boost Ma x Technology 3.0 available.
Bit 15: HWP Capabilities. Highest Perf ormance change is supported if set.
Bit 16: HWP PECI override is supported if set.Bit 17: Flexible HWP is supported if set. 
Bit 18: Fast access mode for the IA32 _HWP_REQUEST MSR is supported if set.
Bit 19: HW_FEEDBACK. IA32_HW_FEEDBACK_PTR MSR,  IA32_HW_FEEDBACK_CON FIG MSR, IA32_PACK-
AGE_THERM_STATUS MSR bit 26, and IA32_PACKAGE_ THERM_INTERRUPT MSR bit 25 are supported if 
set.

set.
Bit 20: Ignoring Idle Logical Proces sor HWP request is supported if set.
Bits 22-21: Reserved.
Bit 23: Intel® Thread Director supported if set. IA32_HW_FEEDB ACK_CHAR and IA32_HW_FEEDBACK_-
THREAD_CONFIG MSRs are supported if set.Bit 24: IA32_THERM_INTERRUPT MS R bit 25 is supported if set.
Bits 31-25: Reserved.
EBX Bits 03-00: Number of Interrupt Thresholds in Digital Thermal Sensor.
Bits 31-04: Reserved. 
ECX Bit 00: Hardware Coordination Feedback Capabi lity (Presence of IA32_MPERF and IA32_APERF). The 
capability to provide a measure of delivered processor performance (since last reset of the counters), as 
a percentage of the expected processor performance when running at the TSC frequency.Bits 02-01: Reserved = 0.
Bit 03: The processor supports performance-energy bias  preference if CPUID.06H:ECX.SETBH[bit 3] is set 
and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).Bits 07-04: Reserved = 0.
Bits 15-08: Number of In tel® Thread Director classes supported by the processor. Information for that 
many classes is written into the Intel Thread Director Table by the hardware.Bits 31-16: Reserved = 0.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-221EDX Bits 07-00: Bitmap of supported hardware feedback interface capabilities.
0 = When set to 1, indicates support for performance capability reporting.
1 = When set to 1, indicate s support for energy efficiency capability reporting.
2-7 = Reserved
Bits 11-08: Enumerates the size of  the hardware feedback interface st ructure in number of 4 KB pages; 
add one to the re turn value to get the result.
Bits 31-16: Index (starting at 0) of  this logical processor's row in th e hardware feedback interface struc-
ture. Note that on some parts the index may be same for multiple logical processors. On some parts the 
indices may not be contiguous, i.e., there may be unused rows in the hardware feedback interface struc-ture.
NOTE:
Bits 0 and 1 will alwa ys be set together.
Structured Extended Feature Flags Enumeration Leaf (Initi al EAX Value = 07H, ECX = 0)
07H EAX Bits 31-00: Reports the maximum input value for supported leaf 7 sub-leaves.
EBX Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
Bit 01: IA32_TSC_ADJUST MSR is supported if 1.Bit 02: SGX. Supports Intel®  Software Guard Extensions (Intel® SGX Extensions) if 1.
Bit 03: BMI1.
Bit 04: HLE.Bit 05: AVX2. Supports Intel® Advanced Vector Extensions 2 (Intel® AVX2) if 1.
Bit 06: FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1.
Bit 07: SMEP. Supports Supervisor-Mode Execution Prevention if 1.Bit 08: BMI2.
Bit 09: Supports Enhanced REP MOVSB/STOSB if 1.
Bit 10: INVPCID. If 1, supports INVPCID instructio n for system software that  manages process-context 
identifiers.
Bit 11: RTM.
Bit 12: RDT-M. Supports Inte l® Resource Direct or Technology (Intel® RDT) Monitoring capa bility if 1.
Bit 13: Deprecates FPU CS and FPU DS values if 1.
Bit 14: MPX. Supports Intel® Memo ry Protection Extensions if 1.
Bit 15: RDT-A. Supports Intel® Resource Director Te chnology (Intel® RDT) Allo cation capability if 1.
Bit 16: AVX512F.
Bit 17: AVX512DQ.
Bit 18: RDSEED.Bit 19: ADX.
Bit 20: SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.
Bit 21: AVX512_IFMA.Bit 22: Reserved.
Bit 23: CLFLUSHOPT.
Bit 24: CLWB.Bit 25: Intel Processor Trace.
Bit 26: AVX512PF. (Intel® Xeon Phi™ only.)
Bit 27: AVX512ER. (Intel® Xeon Phi™ only.)Bit 28: AVX512CD.
Bit 29: SHA. supports Intel® Se cure Hash Algorithm Extensions (Intel® SHA Extensions) if 1.
Bit 30: AVX512BW.Bit 31: AVX512VL.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-222 Vol. 2AECX Bit 00: PREFETCHWT1. (Intel® Xeon Phi™ only.)
Bit 01: AVX512_VBMI.
Bit 02: UMIP. Supports user-mode instruction prevention if 1.Bit 03: PKU. Supports protection keys for user-mode pages if 1.
Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable  protection keys (and the RDPKRU/WRPKRU instruc-
tions).Bit 05: WAITPKG.
Bit 06: AVX512_VBMI2.
Bit 07: CET_SS. Supports CET shadow stack features if 1.  Processors that set this bit define bits 1:0 of the 
IA32_U_CET and IA32_S_CET MSRs. Enumerates support for the following MSRs: 
IA32_INTERRUPT_SPP_TABLE_ADDR, IA32_PL 3_SSP, IA32_PL2_SSP, IA32_PL1_SSP, and 
IA32_PL0_SSP.Bit 08: GFNI.
Bit 09: VAES.
Bit 10: VPCLMULQDQ.
Bit 11: AVX512_VNNI.
Bit 12: AVX512_BITALG.Bits 13: TME_EN. If 1, the followi ng MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, 
IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
Bit 14: AVX512_VPOPCNTDQ. Bit 15: Reserved.
Bit 16: LA57. Supports 57-bit linear addresses and five-level paging if 1.
Bits 21-17: The value of MAWAU used by the BN DLDX and BNDSTX instructions in 64-bit mode.
Bit 22: RDPID and IA32_TSC_AUX are available if 1.
Bit 23: KL. Supports Key Locker if 1.
Bit 24: BUS_LOCK_DETECT. If 1, indicates support for OS bus-lock detection.Bit 25: CLDEMOTE. Supports cache line de mote if 1.
Bit 26: Reserved.
Bit 27: MOVDIRI. Supp orts MOVDIRI if 1.
Bit 28: MOVDIR64B. Supports MOVDIR64B if 1.
Bit 29: ENQCMD. Supports Enqueue Stores if 1.
Bit 30: SGX_LC. Supports SGX Launch Configuration if 1.Bit 31: PKS. Supports pr otection keys for supervisor-mode pages if 1.
EDX Bit 00: Reserved.
Bit 01: SGX-KEYS. If 1, Attestation Se rvices for Intel® SGX is supported.
Bit 02: AVX512_4VNNIW. (I ntel® Xeon Phi™ only.)
Bit 03: AVX512_4FMAPS. (Intel® Xeon Phi™ only.)Bit 04: Fast Short REP MOV.
Bit 05: UINTR. If 1, the proces sor supports us er interrupts.
Bits 07-06: Reserved.Bit 08: AVX512_VP2INTERSECT.
Bit 09: SRBDS_CTRL. If 1, enumerates support for the IA32_MCU_OPT_CTRL MSR and indicates its bit 0 
(RNGDS_MITG_DIS) is also supported.Bit 10: MD_CLEAR supported.
Bit 11: RTM_ALWAYS_ABORT. If set, any execution of XBEGIN immediately aborts and transitions to the 
specified fallback address.Bit 12: Reserved.
Bit 13: If 1, RTM_FORCE_ABORT supported. Processors that set this bit support the 
IA32_TSX_FORCE_ABORT MSR. They allow software to set IA32_TSX_FORCE_ABORT[0] (RTM_FORCE_ABORT).
Bit 14: SERIALIZE.
Bit 15: Hybrid. If 1, the processor is identified as a hybrid part. If CPUID.0.MAXLEAF ≥ 1AH and 
CPUID.1A.EAX 
≠ 0, then the Native Model ID Enumeration Leaf 1AH exists.
Bit 16: TSXLDTRK. If 1, the processor supports In tel TSX suspend/resume of  load address tracking.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-223Bit 17: Reserved.
Bit 18: PCONFIG. Supports PCONFIG if 1.
Bit 19: Architectural LBRs. If 1, indi cates support for architectural LBRs.
Bit 20: CET_IBT. Supports CET indirect branch tracking features if 1. Processors that set this bit define 
bits 5:2 and bits 63:10 of the IA32_U_CET and IA32_S_CET MSRs.
Bit 21: Reserved.Bit 22: AMX-BF16. If 1, the proc essor supports tile computational operations on bfloat16 numbers.
Bit 23: AVX512_FP16.
Bit 24: AMX-TILE. If 1, the proce ssor supports tile architecture.
Bits 25: AMX-INT8. If 1, the proc essor supports tile computational operations on 8-bit integers.
Bit 26: Enumerates support for indirect branch restri cted speculation (IBRS) and the indirect branch pre-
dictor barrier (IBPB). Processo rs that set this bit support the IA32_SPEC_CTRL MSR and the 
IA32_PRED_CMD MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS)  and IA32_PRED_CMD[0] 
(IBPB).
Bit 27: Enumerates support fo r single thread indirect branch predictors (STIBP). Processors that set this 
bit support the IA32_SPEC_CTRL MS R. They allow software to set IA32_SPEC_CTRL[1] (STIBP).
Bit 28: Enumerates suppor t for L1D_FLUSH. Processors that se t this bit support the IA32_FLUSH_CMD 
MSR. They allow software to set IA32_FLUSH_CMD[0] (L1D_FLUSH).
Bit 29: Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
Bit 30: Enumerates support for the IA32_CORE_CAPABILITIES MSR. 
IA32_CORE_CAPABILITIES is an architectural MSR that enumerates model-specific features. A bit being 
set in this MSR indicates that a mo del specific feature is supported; software must still consult CPUID 
family/model/stepping to determine the behavior of the enumerated feature as features enumerated in IA32_CORE_CAPABILITIES may have different behavior  on different processor models. Some of these 
features may have behavior that is consistent across processor models (and for which consultation of 
CPUID family/model/ste pping is not necessary); such features are identified explicitly where they are 
documented in this manual.
Bit 31: Enumerates support for Speculative Store Bypa ss Disable (SSBD). Processors  that set this bit sup-

port the IA32_SPEC_CTRL MSR. They allow software to set IA32 _SPEC_CTRL[2] (SSBD).
NOTE:
* If ECX contains an invalid sub-leaf index, EAX/EBX/ ECX/EDX return 0. Sub-leaf  index n is invalid if n 
exceeds the value that sub-leaf 0 returns in EAX.
Structured Extended Feature Enumeration Sub-leaf (Initial EAX Value = 07H, ECX = 1)
07H NOTES:
Leaf 07H output depends on the initial value in ECX. 
If ECX contains an invalid sub leaf  index, EAX/EBX/ECX/EDX return 0.
EAXThis field reports 0 if the sub-leaf index, 1, is invalid.
Bits 03-00: Reserved.
Bit 04: AVX-VNNI. AVX (VEX-encoded) versions of the Vector Neural Network Instructions.Bit 05: AVX512_BF16. Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.Bits 09-06: Reserved.
Bit 10: If 1, supports fast zero-length REP MOVSB.
Bit 11: If 1, supports fast short REP STOSB.Bit 12: If 1, supports fast short REP CMPSB, REP SCASB.Bits 21-13: Reserved.Bit 22: HRESET. If 1, supports history reset via the HRESET instruction and the IA32_HRESET_ENABLE 
MSR. When set, indicates that the Processo r History Reset Leaf (E AX = 20H) is valid.
Bits 29-23: Reserved.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-224 Vol. 2ABit 30: INVD_DISABLE_POST_BIOS_DON E. If 1, supports INVD execut ion prevention af ter BIOS Done.
Bit 31: Reserved.
EBXThis field reports 0 if the sub-leaf index, 1, is invalid.
Bit 00: Enumerates the presence of the IA32_PPIN and IA32_PPIN_CTL MSRs. If 1, these MSRs are sup-
ported.
Bits 31-01: Reserved.
ECX This field reports 0 if  the sub-leaf index, 1, is invalid; otherwise it is reserved.
EDX This field reports 0 if  the sub-leaf index, 1, is invalid.
Bits 17-00: Reserved.Bit 18: CET_SSS. If 1, indi cates that an operating system can enable  supervisor shadow stacks as long as 
it ensures that a supervis or shadow stack cannot become prematur ely busy due to page faults (see Sec-
tion 17.2.3 of the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). When 
emulating the CPUID instruction, a virtual-machine moni tor (VMM) should return th is bit as 1 only if it 
ensures that VM exits cannot cause a guest supervisor shadow stack to appear to be prematurely busy. 
Such a VMM could set the “premature ly busy shadow stack” VM-exit control and use the additional infor-
mation that it provides.
Bits 31-19: Reserved.
Structured Extended Feature Enumeration Sub-leaf (Initial EAX Value = 07H, ECX = 2)
07H NOTES:
EAX This field reports 0 if the sub-leaf index, 2, is invalid; otherwise it is reserved.
EBX This field reports 0 if the sub-leaf index, 2, is invalid; otherwise it is reserved.
ECX This field reports 0 if the sub-leaf index, 2, is invalid; otherwise it is reserved.EDX This field reports 0 if the sub-leaf index, 2, is invalid.
Bit 00: PSFD. If 1, indicates bit 7 of the IA32_SPEC_CTRL MSR is supported. Bit 7 of this MSR disables 
Fast Store Forwarding Predictor withou t disabling Speculative Store Bypass.
Bit 01: IPRED_CTRL. If 1, indicates bits 3 and 4 of the IA32_SPEC_CTRL MSR are supported.  Bit 3 of this 
MSR enables IPRED_DIS control for CPL3. Bit 4 of this MSR enables IPRED_DI S control for CPL0/1/2.
Bit 02: RRSBA_CTRL. If 1, indicates bits 5 and 6 of the IA32_SPEC_CTRL MSR are supported. Bit 5 of this 
MSR disables RRSBA behavior for CPL3. Bit 6 of this MSR disables RRSBA behavior for CPL0/1/2.
Bit 03: DDPD_U. If 1, indicates bit 8 of the IA32_SPEC_CTRL MSR is supp orted. Bit 8 of th is MSR disables 
Data Dependent Prefetcher.
Bit 04: BHI_CTRL. If 1, indicates bit 10 of the IA32 _SPEC_CTRL MSR is supported. Bit 10 of this MSR 
enables BHI_DIS_S behavior.Bit 05: MCDT_NO. Processors that enumerate this bit as 1 do not exhibit MXCSR Configuration Depen-
dent Timing (MCDT) behavior and do not need to be mitigated to avoid data-dependent behavior for cer-
tain instructions.
Bits 31-06: Reserved.
Direct Cache Access Information Leaf (Initial EAX Value = 09H)
09H EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
EBX Reserved. 
ECX Reserved.EDX Reserved. Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-225Architectural Performance Monitoring  Leaf (Initial EAX Value = 0AH)
0AH EAX Bits 07-00: Version ID of architectural performance monitoring.
Bits 15-08: Number of general-purpose performance monitoring counter per logical processor.
Bits 23-16: Bit width of general-purpose, performance monitoring counter.
Bits 31-24: Length of EBX bit ve ctor to enumerate architectural performance monitoring events. Archi-
tectural event x is supported if EBX[x]=0 && EAX[31:24]>x.
EBX Bit 00: Core cycle event not available if 1 or if EAX[31:24]<1.
Bit 01: Instruction retired event not available if 1 or if EAX[31:24]<2.
Bit 02: Reference cycles event not available if 1 or if EAX[31:24]<3.
Bit 03: Last-level cache reference event not available if 1 or if EAX[31:24]<4. Bit 04: Last-level cache misses event not available if 1 or if EAX[31:24]<5.
Bit 05: Branch instruction retired event not available if 1 or if EAX[31:24]<6.
Bit 06: Branch mispredict retired event not available if 1 or if EAX[31:24]<7.
Bit 07: Top-down slots event not available if 1 or if EAX[31:24]<8.
Bits 31-08: Reserved = 0.
ECX Bits 31-00: Supported fixed counters bit mask. Fixed-fu nction performance counter 'i' is supported if bit ‘i’ 
is 1 (first counter index starts at zero). It is recommended to use th e following logic to  determine if a 
Fixed Counter is supported: FxCtr[i]_is_supported := ECX[i] || (EDX[4:0] > i);
EDX Bits 04-00: Number of contiguous  fixed-function performance counters starting from 0 (if Version ID > 
1).
Bits 12-05: Bit width of fixed-function performance counters (if Version ID > 1).
Bits 14-13: Reserved = 0.Bit 15: AnyThread deprecation.
Extended Topology Enumeration Leaf (Initial EAX Value = 0BH)
0BH NOTES:
CPUID leaf 1FH is a preferred superset to leaf 0B H. Intel recommends first ch ecking for the existence 
of Leaf 1FH before using leaf 0BH.
The sub-leaves of CPUID leaf 0BH describe an ordered hierarchy of logical processors starting from the 
smallest-scoped domain of a Logical Processor (sub-leaf index 0) to the Core domain (sub-leaf index 1) to the largest-scoped doma in (the last valid sub-le af index) that is implicitly subordinate to the 
unenumerated highest-scoped domain of the processor package (socket).
The details of each valid domain is enumerated by a corresponding sub-leaf. Details for a domain 
include its type and how all instances of that domain determine the number of logical processors and 
x2 APIC ID partitioning at the next higher-scoped domain. The ordering of domains within the hierarchy is fixed architectura lly as shown below. For a given processor, not all domains may be relevant or 
enumerated; however, the logical processor and core domains are always enumerated.
For two valid sub-leaves N and N+1, sub-leaf N+1 represents the next immediate higher-scoped 
domain with respect to the domain of sub-leaf N for the given processor.
If sub-leaf index “N” returns an invalid domain type  in ECX[15:08] (00H), then all sub-leaves with an 
index greater than “N” shall also return an invalid domain type. A sub-leaf returning an invalid domain 
always returns 0 in EAX and EBX.
EAX Bits 04-00: The number of bits th at the x2APIC ID must be shifted to  the right to address instances of 
the next higher-scoped domain. When logical processor is not supported by the processor, the value of this field at the Logical Processor domain sub-leaf ma y be returned as either 0 (no allocated bits in the 
x2APIC ID) or 1 (one allocate d bit in the x2APIC ID); soft ware should plan accordingly.
Bits 31-05: Reserved.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-226 Vol. 2AEBX Bits 15-00: The number of logical processors across all inst ances of this domain wi thin the next higher-
scoped domain. (For example, in a processor socket/p ackage comprising “M” dies  of “N” cores each, where 
each core has “L” logical processors, the “die” domain sub-leaf value of this field would be M*N*L.) This number reflects configuration as shipped by Intel. Note, software must not us e this field to enumerate 
processor topology*.
Bits 31-16: Reserved.
ECX Bits 07-00: The input ECX sub-leaf index.
Bits 15-08: Domain Type. This field provides an identification value wh ich indicates the domain as shown 
below. Although domains are ordered, their assigned identification values are not and software should 
not depend on it.
Hierarchy

Hierarchy
Domain Domain Type Iden tification Value
Lowest Logical Processor 1
Highest Core 2
(Note that enumeration values of 0 and 3-255 are reserved.)
EDX Bits 31-00: x2APIC ID of the current logical processor.
NOTES:
* Software must not use the value of EBX[15:0] to enumerate processor topology of the system. The value is only intended for display and diagnostic purposes. The actual number of logical processors avail-
able to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software and 
platform hardware configurations.
Processor Extended State Enumeration Main Leaf (Initial EAX Value = 0DH, ECX = 0)
0DH NOTES:
Leaf 0DH main leaf (ECX = 0). 
EAX Bits 31-00: Reports the supported bits of the lower 32 bi ts of XCR0. XCR0[n] can be set to 1 only if 
EAX[n] is 1.
Bit 00: x87 state. Bit 01: SSE state.
Bit 02: AVX state.
Bits 04-03: MPX state.Bits 07-05: AVX-512 state.
Bit 08: Used for IA32_XSS.
Bit 09: PKRU state.Bits 16-10: Used for IA32_XSS.
Bit 17: TILECFG state.
Bit 18: TILEDATA state.Bits 31-19: Reserved.
EBX Bits 31-00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by 
enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area 
are not enabled.
ECX Bit 31-00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the 
XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in 
XCR0. 
EDX Bit 31-00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if 
EDX[n] is 1.Bits 31-00: Reserved.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-227Processor Extended State E numeration Sub-leaf (Initial EAX Value = 0DH, ECX = 1)
0DH EAX Bit 00: XSAVEOPT is available.
Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.
Bit 02: Supports XGETBV  with ECX = 1 if set.
Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.
Bit 04: Supports ex tended feature disable (XFD) if set.
Bits 31-05: Reserved.
EBX Bits 31-00: The size in bytes of  the XSAVE area containing all states enabled by XCRO | IA32_XSS.
NOTES:
If EAX[3] is enumerated as 0 and EAX[1] is enumerat ed as 1, EBX enumerates the size of the XSAVE area 
containing all states enabled by XCRO. If EAX[1] an d EAX[3] are both enumerated as 0, EBX enumerates 
zero.
ECX Bits 31-00: Reports the supported bits of the lower 32 bi ts of the IA32_XSS MSR. IA32_XSS[n] can be 
set to 1 only if ECX[n] is 1.Bits 07-00: Used for XCR0.
Bit 08: PT state.
Bit 09: Used for XCR0.Bit 10: PASID state.
Bit 11: CET user state.
Bit 12: CET supervisor state.Bit 13: HDC state.
Bit 14: UINTR state.
Bit 15: LBR state (only for the architectural LBR feature).Bit 16: HWP state.
Bits 18-17: Used for XCR0.
EDX Bits 31-00: Reports th e supported bits of the upper 32 bits of  the IA32_XSS MSR. IA32_XSS[n+32] can 
be set to 1 only if EDX[n] is 1.Bits 31-00: Reserved.
Processor Extended State Enumeration Sub-leaves  (Initial EAX Value = 0DH, ECX = n, n > 1)
0DH NOTES:
Leaf 0DH output depends on the initial value in ECX. 
Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the 
XCR0 register or the IA32_XSS MSR.
* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/ED X return 0. Sub-leaf n (0 ≤ n ≤ 31) is invalid 
if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 ≤ n ≤ 63) is invalid if 
sub-leaf 0 returns 0 in EDX[n-32] an d sub-leaf 1 returns 0 in EDX[n-32].
EAX Bits 31-00: The size in bytes (fro m the offset specified in EBX) of the save area for an extended state 
feature associated with a valid sub-leaf index, n.
EBX Bits 31-00: The offset in bytes of this extended state component’s save area from the beginning of the 
XSAVE/XRSTOR area.
This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register*.
ECX Bit 00 is set if the bit n (correspon ding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear 
if bit n is instead supported in XCR0.Bit 01 is set if, when the compacted format of an XSAVE area is used, this extended state component 
located on the next 64-byte bounda ry following the preceding state co mponent (otherwise , it is located 
immediately following the preceding state component).Bits 31-02 are reserved.
This field reports 0 if the sub-leaf index, n, is invalid*.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-228 Vol. 2AEDX This field reports 0 if  the sub-leaf index, n, is invalid*; otherwise it is reserved.
Intel® Resource Director Technology (I ntel® RDT) Monitoring Enumeration Sub-le af (Initial EAX Value = 0FH, ECX = 0)
0FH NOTES:
Leaf 0FH output depends on the initial value in ECX. 
Sub-leaf index 0 reports valid resource type starting at bit position 1 of EDX.
EAX Reserved.
EBX Bits 31-00: Maximum range (zero-based) of RMID  within this physical processor of all types.
ECX Reserved.EDX Bit 00: Reserved.
Bit 01: Supports L3 Cache Intel RDT Monitoring if 1.
Bits 31-02: Reserved.
L3 Cache Intel® RDT Monitoring Capability Enumer ation Sub-leaf (Initial EAX Value = 0FH, ECX = 1)
0FH NOTES:
EAX Bits 07-00:The counter width is encoded as an offset from 24b. A value of zero in this field indicates that 
24-bit counters are suppor ted. A value of 8 in this field indica tes that 32-bit coun ters are supported.
Bit 08: If 1, indicates the presence of an overflow bit in the IA32_QM_CTR MSR (bit 61).
Bit 09: If 1, indicates the presence of non-CPU agent Intel RDT CMT support.
Bit 10: If 1, indicates the presence of non-CPU agent Intel RDT MBM support.
Bits 31-11: Reserved.
EBX Bits 31-00: Conversion factor from reported IA 32_QM_CTR value to occupancy metric (bytes) and Mem-
ory Bandwidth Monitoring (MBM) metrics.
ECX Maximum range (zero-based) of  RMID of this resource type.
EDX Bit 00: Supports L3 o ccupancy monitoring if 1.
Bit 01: Supports L3 Total Bandwidth monitoring if 1.
Bit 02: Supports L3 Local Bandwidth monitoring if 1.
Bits 31-03: Reserved.
Intel® Resource Director Technology (I ntel® RDT) Allocation Enumeration Sub-le af (Initial EAX Value = 10H, ECX = 0)
10H NOTES:
Leaf 10H output depends on the initial value in ECX. Sub-leaf index 0 reports valid resource identification (ResID) starting at bit position 1 of EBX.
EBX Bit 00: Reserved.
Bit 01: Supports L3 Cache Al location Technology if 1.
Bit 02: Supports L2 Cache Al location Technology if 1.
Bit 03: Supports Memory Bandwidth Allocation if 1.Bits 31-04: Reserved.
ECX Reserved.EDX Reserved.
L3 Cache Allocation Technology Enumeration Sub- leaf (Initial EAX Value = 10H, ECX = ResID =1)
10H NOTES:
Leaf 10H output depends on the initial value in ECX. Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-229EAX Bits 04-00: Length of the capacity  bit mask for the corresponding ResI D. Add one to the return value to 
get the result.
EBX Bits 31-00: Bit-granular map of isolation/contention of allocation units.
ECX Bit 00: Reserved.
Bit 01: If 1, indicates L3 CAT for non-CPU agents is supported.
Bit 02: If 1, indicates L3 Code and Data  Prioritization Tech nology is supported.
Bit 03: If 1, indicates non-contiguous  capacity bitmask is supported. Th e bits that are se t in the various 
IA32_L3_MASK_n registers do not have to be contiguous.
Bits 31-04: Reserved.
EDX Bits 15-00: Highest Class of Service (COS) number support ed for this ResID.
L2 Cache Allocation Technology Enumeration Sub- leaf (Initial EAX Value = 10H, ECX = ResID =2)
10H NOTES:
Leaf 10H output depends on the initial value in ECX. 
EAX Bits 04-00: Length of the capacity  bit mask for the corresponding ResI D. Add one to the return value to 
get the result.Bits 31-05: Reserved.
EBX Bits 31-00: Bit-granular map of isolation/contention of allocation units.ECX Bits 01-00: Reserved.
Bit 02: CDP. If 1, indicates L2 Code and Da ta Prioritization Tec hnology is supported.
IA32_L2_MASK_n registers do not have to be contiguous.
EDX Bits 15-00: Highest COS numb er supported for this ResID.
Memory Bandwidth Allocation Enumeration Sub-le af (Initial EAX Value = 10H, ECX = ResID =3)
10H NOTES:
EAX Bits 11-00: Reports the maximum MBA throttling valu e supported for the corresponding ResID. Add one

10H NOTES:
10H NOTES:
EAX Bits 11-00: Reports the maximum MBA throttling valu e supported for the corresponding ResID. Add one 
to the return value to get the result.
Bits 31-12: Reserved.
EBX Bits 31-00: Reserved.
ECX Bits 01-00: Reserved.
Bit 02: Reports whether the response  of the delay values is linear. 
Intel® SGX Capability Enumeration Leaf, Su b-leaf 0 (Initial EAX Value = 12H, ECX = 0)
12H NOTES:
Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1. Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-230 Vol. 2AEAX Bit 00: SGX1. If 1, Indica tes Intel SGX su pports the collection of  SGX1 leaf functions.
Bit 01: SGX2. If 1, Indicates Intel SGX supports the collect ion of SGX2 leaf functions.
Bits 04-02: Reserved.Bit 05: If 1, indicates Intel SGX supports ENCLV instruction leaves EINCVIRTCHILD, EDECVIRTCHILD, and 
ESETCONTEXT.
Bit 06: If 1, indicates Intel SGX su pports ENCLS instruction leaves ET RACKC, ERDINFO, ELDBC, and ELDUC.
Bit 07: If 1, indicates Intel SGX supports ENCLU instruction leaf EVERIFYREPORT2.
Bits 09-08: Reserved.
Bit 10: If 1, indicates Intel SGX supports ENCLS instruction leaf EUPDATESVN.Bit 11: If 1, indicates Intel SGX su pports ENCLU instruction leaf EDECCSSA.
Bits 31-12: Reserved. 
EBX Bits 31-00: MISCSELECT. Bit vector of supported extended SGX features.
ECX Bits 31-00: Reserved.EDX Bits 07-00: MaxEnclaveSize_Not64. The maximum supported enclave size in non-64-bit mode is 
2^(EDX[7:0]).
Bits 15-08: MaxEnclaveSize_64. The maximum support ed enclave size in 64-bit mode is 2^(EDX[15:8]).
Intel SGX Attributes Enumeration Leaf, Sub- leaf 1 (Initial EAX Value = 12H, ECX = 1)
12H NOTES:
Leaf 12H sub-leaf 1 (ECX = 1) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1. 
EAX Bit 31-00: Reports the valid bits of SECS.ATTRI BUTES[31:0] that software  can set with ECREATE.
EBX Bit 31-00: Reports the valid bits of SECS.ATTRI BUTES[63:32] that software can set with ECREATE.
ECX Bit 31-00: Reports the valid bits of SECS.ATTRI BUTES[95:64] that software can set with ECREATE.
EDX Bit 31-00: Reports the valid bits of SECS.ATTRI BUTES[127:96] that softwa re can set with ECREATE.
Intel® SGX EPC Enumeration Leaf, Sub-leaves (I nitial EAX Value = 12H, ECX = 2 or higher)
12H NOTES:
Leaf 12H sub-leaf 2 or higher (E CX >= 2) is supported if CPUI D.(EAX=07H, ECX=0H):EBX[SGX] = 1. 
For sub-leaves (ECX = 2 or higher), definition of  EDX,ECX,EBX,EAX[31:4] depends on the sub-leaf type
listed below. 
EAX Bit 03-00: Sub-leaf Type
0000b: Indicates this sub-leaf is invalid. 
0001b: This sub-leaf enumerates an EPC section. EBX:EAX and EDX:ECX provide information on the 
Enclave Page Cache (EPC) section.All other type encodings are reserved.
Type 0000b. This sub-leaf is invalid. 
EDX:ECX:EBX:EAX return 0.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-231Type 0001b. This sub-leaf enumerates an EPC sect ions with EDX:ECX, EBX:EAX defined as follows. 
EAX[11:04]: Reserved (enumerate 0). 
EAX[31:12]: Bits 31:12 of the physical address of the base of the EPC section. 
EBX[19:00]: Bits 51:32 of the physical address of the base of the EPC section. 
EBX[31:20]: Reserved.
ECX[03:00]: EPC section property encoding defined as follows: 
If ECX[3:0] = 0000b, then all bits of  the EDX:ECX pair are enumerated as 0.
If ECX[3:0] = 0001b, then this section ha s confidentiality and integrity protection.
If ECX[3:0] = 0010b, then this sectio n has confidentiality protection only.
All other encodings are reserved.
ECX[11:04]: Reserved (enumerate 0). 
ECX[31:12]: Bits 31:12 of the size of the corresponding EPC section within the Processor Reserved 
Memory.
EDX[19:00]: Bits 51:32 of the size of the corres ponding EPC section within  the Processor Reserved 
Memory. 
EDX[31:20]: Reserved.
Intel® Processor Trace Enumeration Main Leaf (Initial EAX Value = 14H, ECX = 0)
14H NOTES:
Leaf 14H main leaf (ECX = 0). 
EAX Bits 31-00: Reports the maximum sub-leaf supported in leaf 14H.
EBX Bit 00: If 1, indicates that IA 32_RTIT_CTL.CR3Filter can be set to  1, and that IA32_RTIT_CR3_MATCH 
MSR can be accessed.Bit 01: If 1, indicates support of Configurable PSB and Cycle-Accurate Mode.
Bit 02: If 1, indicate s support of IP Filtering, TraceStop filterin g, and preservation of Intel PT MSRs across 
warm reset.Bit 03: If 1, indicates support of MTC timing packet and suppression of COFI-based packets.
Bit 04: If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and 
IA32_RTIT_CTL[5] (FUPonPTW), an d PTWRITE can generate packets.
Bit 05: If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn), 
enabling Power Event Trace packet generation.
Bit 06: If 1, indicates support for PSB and PMI preser vation. Writes can set IA32_RTIT_CTL[56] (InjectPsb-
PmiOnEnable), enabling the processor to set IA32_RTIT_STATUS[7] (PendTopaPMI) and/or IA32_R-
TIT_STATUS[6] (PendPSB) in order to preserve ToPA PMIs and/or PSBs  otherwise lost due to Intel PT 
disable. Writes can also set PendToPAPMI and PendPSB.
Bit 07: If 1, writes can set IA32_RTIT_CTL[31] (E ventEn), enabling Event Trace packet generation.
Bit 08: If 1, writes can set IA32_RTIT_CTL[55 ] (DisTNT), disabling TNT packet generation.
Bit 31-09: Reserved. 
ECX Bit 00: If 1, Tracing can be enabled with IA32_R TIT_CTL.ToPA = 1, hence utilizing the ToPA output 
scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTI T_OUTPUT_MASK_PTRS MSRs can be accessed.
Bit 01: If 1, ToPA tables can hold  any number of output entries, up to the maximum allowed by the 
MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.Bit 02: If 1, indicates support of Single-Range Output scheme.
Bit 03: If 1, indicates support of output to Trace Tr ansport subsystem.
Bit 30-04: Reserved.Bit 31: If 1, generated packets which contain IP payloads have LIP values, which include the CS base com-
ponent.
EDX Bits 31-00: Reserved.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-232 Vol. 2AIntel® Processor Trace Enumeration Sub-le af (Initial EAX Value = 14H, ECX = 1)
14H EAX Bits 02-00: Number of configurable Address Ranges for filtering.
Bits 15-03: Reserved.
Bits 31-16: Bitmap of supp orted MTC period encodings.
EBX Bits 15-00: Bitmap of supported Cycle Threshold value encodings.
Bit 31-16: Bitmap of supported Configurable PSB frequency encodings.
ECX Bits 31-00: Reserved.
EDX Bits 31-00: Reserved.
Time Stamp Counter and Nominal Core Crystal Cl ock Information Leaf (Initial EAX Value = 15H)
15H NOTES:
If EBX[31:0] is 0, the TSC/”core crystal clock” ratio is not enumerated.EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.
If ECX is 0, the nominal core crystal clock frequency is not enumerated.
“TSC frequency” = “core crystal clock frequency” * EBX/EAX.
The core crystal clock may differ from the refere nce clock, bus clock, or core clock frequencies.
EAX Bits 31-00: An unsigned integer which is the denominator of the TSC/”c ore crystal clock” ratio.
EBX Bits 31-00: An unsigned integer which is the numerator of the TSC/”cor e crystal clock” ratio.
ECX Bits 31-00: An unsigned integer which is the nominal frequency of the core crystal clock in Hz.EDX Bits 31-00: Reserved = 0.
Processor Frequency Information Leaf (Initial EAX Value = 16H)
16H EAX Bits 15-00: Processor Base Frequency (in MHz).
Bits 31-16: Reserved =0.
EBX Bits 15-00: Maximum Frequency (in MHz).
ECX Bits 15-00: Bus (Reference) Frequency (in MHz).
EDX Reserved.
NOTES:
* Data is returned from th is interface in accordance with the processor's specification and does not reflect 
actual values. Suitable use of this da ta includes the display of processor information in like manner to the 
processor brand string and for determining the appr opriate range to use when displaying processor 
information e.g. frequency history graphs. The returned information should not be used for any other purpose as the returned information does not accurately corre late to information / counters returned by 
other processor interfaces. 
While a processor may support the Processor Frequency Information leaf, fields that return a value of 
zero are not supported.
System-On-Chip Vendor Attribut e Enumeration Main Leaf (Initi al EAX Value = 17H, ECX = 0)
17H NOTES:
Leaf 17H main leaf (ECX = 0).
Leaf 17H output depends on the initial value in ECX.
Leaf 17H sub-leaves 1 through 3 reports SOC Vendor Brand String.
Leaf 17H is valid if MaxSOCID_Index >= 3.
Leaf 17H sub-leaves 4 and above are reserved.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Initial EAX

17H NOTES:
Vol. 2A 3-233EAX Bits 31-00: MaxSOCID_Index. Reports the maximum input value of supported sub-leaf in leaf 17H.
EBX Bits 15-00: SOC Vendor ID.
Bit 16: IsVendorScheme. If 1, the SOC Vendor ID fiel d is assigned via an indu stry standard  enumeration
scheme. Otherwise, the SOC Vendor ID field is assigned by Intel.
Bits 31-17: Reserved = 0.
ECX Bits 31-00: Project ID. A unique number an SOC vendor assigns to its SOC projects.
EDX Bits 31-00: Stepping ID. A unique number within an SOC project that an SOC vendor assigns.
System-On-Chip Vendor Attribut e Enumeration Sub-leaf (Initial  EAX Value = 17H, ECX = 1..3)
17H EAX Bit 31-00: SOC Vendor Brand String. UTF-8 encoded string.
EBX Bit 31-00: SOC Vendor Brand String. UTF-8 encoded string.
ECX Bit 31-00: SOC Vendor Brand String. UTF-8 encoded string.EDX Bit 31-00: SOC Vendor Brand String. UTF-8 encoded string.
NOTES:
SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H.The complete SOC Vendor Brand String is constructed by concatenating in ascending order of
EAX:EBX:ECX:EDX and from the sub-le af 1 fragment towards sub-leaf 3.
System-On-Chip Vendor Attribute E numeration Sub-leaves (Initial EAX Value = 17H, ECX > MaxSOCID_Index)
17H NOTES:
EAX Bits 31-00: Reserved = 0.EBX Bits 31-00: Reserved = 0.
ECX Bits 31-00: Reserved = 0.
EDX Bits 31-00: Reserved = 0.
Deterministic Address Translation Parameters Main Leaf (Initial EAX Value = 18H, ECX = 0)
18H NOTES:
Each sub-leaf enumerates a different address translation structure. If ECX contains an invalid sub-leaf index, EAX/EBX/ ECX/EDX return 0. Sub-leaf index n is invalid if n 
exceeds the value that sub-leaf 0 returns in EAX. A su b-leaf index is also invalid if EDX[4:0] returns 0. 
Valid sub-leaves do not need to be contiguous or in  any particular order. A valid sub-leaf may be in a 
higher input ECX value than an invalid sub-leaf or th an a valid sub-leaf of a higher or lower-level struc-
ture. 
* Some unified TLBs will allow a sing le TLB entry to satisfy data read /write and instruction fetches. 
Others will require separate entries (e.g., one loaded on data read/write and another loaded on an instruction fetch). See the Intel® 64 and IA-32 Archit ectures Optimization Refe rence Manual for details 
of a particular product. 
** Add one to the return value to get the result.
EAX Bits 31-00: Reports the maximum input va lue of supported sub-leaf in leaf 18H.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-234 Vol. 2AEBX Bit 00: 4K page size entries supported by this structure.
Bit 01: 2MB page size  entries supported by this structure.
Bit 02: 4MB page size  entries supported by this structure.
Bit 03: 1 GB page size entries supported by this structure.
Bits 07-04: Reserved.
Bits 10-08: Partitioning (0: Soft partitioning betw een the logical processors sharing this structure).
Bits 15-11: Reserved.
Bits 31-16: W = Ways of associativity.
ECX Bits 31-00: S = Number of Sets.
EDX Bits 04-00: Translation cache type field.
00000b: Null (indicates this  sub-leaf is not valid).
00001b: Data TLB.
00010b: Instruction TLB.
00011b: Unified TLB*.
00100b: Load Only TLB. Hit on load s; fills on both loads and stores.
00101b: Store Only TLB. Hit on stores; fill on stores.
Bits 07-05: Translation cache level (starts at 1).Bit 08: Fully asso ciative structure.
Bits 13-09: Reserved.
Bits 25-14: Maximum number of ad dressable IDs for logical processors  sharing this translation cache.**
Bits 31-26: Reserved.
Deterministic Address Translation Parameters Sub-leaf (Initial EAX Value = 18H, ECX ≥ 1)
18H NOTES:
Each sub-leaf enumerates a different address translation structure. 
If ECX contains an invalid sub-leaf index, EAX/EBX/ ECX/EDX return 0. Sub-leaf index n is invalid if n 
exceeds the value that sub-leaf 0 retu rns in EAX. A sub-leaf index is also invalid if EDX[4:0] returns 0. 
higher input ECX value than an invalid sub-leaf or th an a valid sub-leaf of a hi gher or lower-level struc-
ture. 
* Some unified TLBs will allow a si ngle TLB entry to satisfy data re ad/write and instruction fetches. 
Others will require separate entries (e.g., one loaded on data read/write and another loaded on an 
instruction fetch. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for details 
EAX Bits 31-00: Reserved.
EBX Bit 00: 4K page size entries supported by this structure.
Bit 03: 1 GB page size entries supported by this structure.Bits 07-04: Reserved.
Bits 15-11: Reserved.Bits 31-16: W = Ways of associativity.
ECX Bits 31-00: S = Number of Sets.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-235EDX Bits 04-00: Translati on cache type field.
0000b: Null (indicates this sub-leaf is not valid).
0001b: Data TLB.0010b: Instruction TLB.
0011b: Unified TLB*.
Bits 07-05: Translation cache level (starts at 1).
Bit 08: Fully associative structure.
Bits 13-09: Reserved.Bits 25-14: Maximum number of addressable IDs for logical processors sharing this translation cache**
Key Locker Leaf (Initial EAX Value = 19H)
19H EAX Bit 00: Key Locker restriction of CPL0-only supported.
Bit 01: Key Locker restriction of no-encrypt supported.
Bit 02: Key Locker restriction of no-decrypt supported.Bits 31-03: Reserved.
EBX Bit 00: AESKLE. If 1, the AES Key Locker instructions are fully enabled.
Bit 01: Reserved.
Bit 02: If 1, the AES wide Key Lo cker instructions are supported.
Bit 03: Reserved.Bit 04: If 1, the platform supports the Key Locker MSRs (IA32_COPY_LOCAL_TO_PLATFORM, 
IA23_COPY_PLATFORM_TO_LOCAL, IA32_COPY_STATUS,  and IA32_IWKEYBACKUP _STATUS) and backing 
up the internal wrapping key.Bits 31-05: Reserved.
ECX Bit 00: If 1, the NoBackup pa rameter to LOADIWKEY is supported.
Bit 01: If 1, KeySource encoding of 1 (randomizati on of the internal wrap ping key) is supported.
Native Model ID Enumeration Leaf (Initial EAX Value = 1AH, ECX = 0)
1AH NOTES:
This leaf exists on all hybr id parts, however this leaf is not only available on hybrid parts. The following 
algorithm is used for detection of this leaf: 
If CPUID.0.MAXLEAF ≥ 1AH and CPUID.1A.EAX ≠ 0, then the leaf exists.
EAX Enumerates the native model ID and core type.
Bits 31-24: Core type*
10H: Reserved
20H: Intel Atom®30H: Reserved
40H: Intel® Core™
Bits 23-00: Native model ID of th e core. The core-type and native model ID can be used to uniquely 
identify the microarchitectur e of the core. This native model ID is  not unique across co re types, and not 
related to the model ID reported in CPUID leaf 01H, and does not identify the SOC.
* The core type may only be  used as an identification  of the microarchitecture for this logical processor 
and its numeric value has no significance, neither larg e nor small. This field ne ither implies nor expresses 
any other attribute to this logical proces sor and software shou ld not assume any.
ECX Reserved.EDX Reserved.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-236 Vol. 2APCONFIG Information Sub-leaf (I nitial EAX Value = 1BH, ECX ≥ 0)
1BH For details on this sub-leaf, see “INPUT EAX = 1BH: Returns PCONFIG Information” on page 3-253.
NOTE:
Leaf 1BH is supported if CPUID.(EAX=07H, ECX=0H):EDX[18] = 1.
Last Branch Records Information Leaf (Initial EAX Value = 1CH)
1CH NOTE:
This leaf pertains to the architectural feature.
EAX Bits 07-00: Supported LBR Depth Values. For each bit n set in this field, the IA32_LBR_DEPTH.DEPTH 
value 8*(n+1) is supported.Bits 29-08: Reserved.
Bit 30: Deep C-state Reset. If set, indicates that LBRs may be cleared on an MWAIT that requests a C-state 
numerically greater than C1.
Bit 31: IP Values Contain LIP. If se t, LBR IP values contain LIP. If clear, IP values contain Effective IP.
EBX Bit 00: CPL Filtering Supported. If set, the proc essor supports setting IA32_ LBR_CTL[2:1] to non-zero 
value.

NOTE:
1CH NOTE:
value.
Bit 01: Branch Filtering Supported. If set, the pr ocessor supports setting IA32_LBR_CTL[22:16] to non-
zero value.
Bit 02: Call-stack Mode Supported. If set, the processor supports setting IA32_LBR_CTL[3] to 1.
ECX Bit 00: Mispredict Bit Supported. IA32_LBR_x_I NFO[63] holds indication of branch misprediction 
(MISPRED).Bit 01: Timed LBRs Supported. IA32_LBR_x_INFO[15:0] holds CPU cycles since last LBR entry (CYC_CNT), 
and IA32_LBR_x_INFO[60] holds an indication of whet her the value held there is valid (CYC_CNT_VALID).
Bit 02: Branch Type Field Supported. IA32_LBR_I NFO_x[59:56] holds indication of the recorded 
operation's branch type (BR_TYPE).
Tile Information Main Leaf (Initial EAX Value = 1DH, ECX = 0)
1DH NOTES:
For sub-leaves of 1DH, they are indexed by the palette id.
Leaf 1DH sub-leaves 2 and above are reserved.
EAX Bits 31-00: max_palette. Highest numbered palette su b-leaf. Value = 1.
EBX Bits 31-00: Reserved = 0.
ECX Bits 31-00: Reserved = 0.EDX Bits 31-00: Reserved = 0.
Tile Palette 1 Sub-leaf (Initi al EAX Value = 1DH, ECX = 1)
1DH EAX Bits 15-00: Palette 1 to tal_tile_bytes. Value = 8192. 
Bits 31-16: Palette 1 bytes_per_tile. Value = 1024.
EBX Bits 15-00: Palette 1 bytes_per_row. Value = 64.
Bits 31-16: Palette 1 max_names (number of tile registers). Value = 8.
ECX Bits 15-00: Palette 1 max_rows. Value = 16.
EDX Bits 31-00: Reserved = 0.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-237TMUL Information Main Leaf (Ini tial EAX Value = 1EH, ECX = 0)
1EH NOTE:
Leaf 1EH sub-leaves 1 and above are reserved.
EAX Bits 31-00: Reserved = 0.
EBX Bits 07-00: tmul_maxk (rows or columns). Value = 16.
Bits 23-08: tmul_maxn (c olumn bytes). Value = 64.
Bits 31-24: Reserved = 0.
V2 Extended Topology Enumeratio n Leaf (Initial EAX Value = 1FH)
1FH NOTES:
CPUID leaf 1FH is a preferred superset to leaf 0B H. Intel recommends using leaf 1FH when available 
rather than leaf 0BH and ensuring that any leaf 0BH algorithms are updated to support leaf 1FH.
The sub-leaves of CPUID leaf 1FH describe an ordered hierarchy of logical processors starting from the 
smallest-scoped domain of a Logical Processor (sub-leaf index 0) to the Core domain (sub-leaf index 1) 
to the largest-scoped doma in (the last valid sub-le af index) that is implicitly subordinate to the 
x2 APIC ID partitioning at the next higher-scoped domain. The ordering of domains within the hierarchy 
is fixed architectura lly as shown below. For a given processor, not all domains may be relevant or 
enumerated; however, the logical processor and core domains are always enumerated. As an example, 
a processor may report an ordered hierarchy consisting  only of “Logical Proce ssor,” “Core,” and “Die.” 
EBX Bits 15-00: The number of logical processors across all instances of this domain  within the next higher-
scoped domain relative to this cu rrent logical processor. (For example, in a processor socket/package 
comprising “M” dies of “N” cores each, where each core has “L” logical processors, the “die” domain sub-
leaf value of this field would be M*N*L. In an asymmetric topology this would be the summation of the 
value across the lower domain level instances to create  each upper domain level instance.) This number 
reflects configuration as shipped by Intel. Note, software must not use this field to enumerate processor 
topology*.
Bits 31-16: Reserved.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-238 Vol. 2AECX Bits 07-00: The input ECX sub-leaf index.
below. Although domains are ordered, as also shown below, their assigned identification values are not and software should not depend on it. (For example, if a new domain between core and module is speci-
fied, it will have an identification value higher than 5.)
Hierarchy
... Core 2... Module 3
... Tile 4
... Die 5... DieGrp 6
Highest Package/Socket (implied)
(Note that enumeration values of 0 and 7-255 are reserved.)
EDX Bits 31-00: x2APIC ID of the current logical processo r. It is always valid and does not vary with the sub-
leaf index in ECX.
NOTES:
platform hardware configurations. 
Processor History Reset Sub-leaf (Initial EAX Value = 20H, ECX = 0)
20H EAX Reports the maximum number of sub-leaves that are supported in leaf 20H.
EBX Indicates which bits may be se t in the IA32_HRESET_ENABLE MSR to  enable reset of different compo-
nents of hardware-maintained history.
Bit 00: Indicates supp ort for both HRESET’s EAX[0] parameter,  and IA32_HRESET_ENABLE[0] set by the 
OS to enable reset of Inte l® Thread Director history.
Bits 31-01: Reserved = 0.
Unimplemented CPUID Leaf Functions
21H Invalid. No existing or future CPU will return processor identification or feature information if the initial 
EAX value is 21H. If the value returned by CPUID.0:EAX (the maximum input value for basic CPUID 
information) is at least 21H, 0 is returned in the re gisters EAX, EBX, ECX, and EDX. Otherwise, the data 
for the highest basic information leaf is returned.
40000000H
− 
4FFFFFFFHInvalid. No existing or future CPU will return processor identification or feature information if the initial 
EAX value is in the range 40000000H to 4FFFFFFFH.
Extended Function CPUID Information
80000000H EAX Maximum Input Value for Extended Function CPUID Information.
Vol. 2A 3-23980000001H EAX Extended Processor Signature and Feature Bits.
EBX Reserved.ECX Bit 00: LAHF/SAHF available in 64-bit mode.*
Bits 04-01: Reserved.Bit 05: LZCNT.
Bits 07-06: Reserved.
Bit 08: PREFETCHW.Bits 31-09: Reserved.
EDX Bits 10-00: Reserved.
Bit 11: SYSCALL/SYSRET.**
Bits 19-12: Reserved = 0.
Bit 20: Execute Disable Bit available.
Bits 25-21: Reserved = 0.
Bit 26: 1-GByte pages are available if 1.Bit 27: RDTSCP and IA32_TSC_AUX are available if 1.
Bit 28: Reserved = 0.
Bit 29: Intel
® 64 Architecture available if 1.
Bits 31-30: Reserved = 0.
NOTES:
* LAHF and SAHF are always available in other modes, regardless of the enumeration of this feature flag.
** Intel processors support SYSCALL and SYSRET only in 64-bit mode. This feature flag is always enumer-
ated as 0 outside 64-bit mode.
80000002H EAX
EBX
ECX
EDXProcessor Brand String.
Processor Brand String Continued.
80000003H EAX
EBXECX
EDXProcessor Brand String Continued.
Processor Brand String Continued.Processor Brand String Continued.
80000004H EAX
EBX
ECXEDXProcessor Brand String Continued.
80000005H EAX
EBX
ECX
EDXReserved = 0.
Reserved = 0.
80000006H EAX
EBXReserved = 0.
ECX
EDXBits 07-00: Cache Li ne size in bytes.

NOTES:
EBX
ECX
EBXECX
EBX
EBX
ECX
ECX
Bits 11-08: Reserved.Bits 15-12: L2 Associativity field *.
Bits 31-16: Cache size in 1K units.
Reserved = 0.Table 3-8.  Information Returned by CPUID Instruction (Contd.)
3-240 Vol. 2AINPUT EAX = 0: Returns CPUID’s Highest Value for Basic Pr ocessor Information and the Ve ndor Identification String
When CPUID executes with EAX set to 0, the processo r returns the highest value the CPUID recognizes for 
returning basic processor information. The value is retu rned in the EAX register and is processor specific.
A vendor identification string is also returned in EBX,  EDX, and ECX. For Intel processors, the string is “Genu-
ineIntel” and is expressed:
EBX := 756e6547h (* “Genu”, with G in the low eight bits of BL *)
EDX := 49656e69h (* “ineI”, with i in the low eight bits of DL *)
ECX := 6c65746eh (* “ntel”, with n in the low eight bits of CL *)
INPUT EAX = 80000000H: Returns CPUID’s Highes t Value for Extended Processor Information
When CPUID executes with EAX set to 80000000H, the pr ocessor returns the highest value the processor recog-
nizes for returning extended processor information. The va lue is returned in the EAX register and is processor 
specific.
IA32_BIOS_SIGN_ID Returns Mi crocode Update Signature
For processors that support the microcode update facility,  the IA32_BIOS_SIGN_ID MSR is loaded with the update 
signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 10 in 
the Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 3A. NOTES:
* L2 associativity field encodings:
00H - Disabled 08H - 16 ways
01H - 1 way (direct mapped)  09H - Reserved02H - 2 ways  0AH - 32 ways
03H - Reserved 0BH - 48 ways
04H - 4 ways 0CH - 64 ways05H - Reserved 0DH - 96 ways
06H - 8 ways 0EH - 128 ways
07H - See CPUID leaf 04H, sub-le af 2** 0FH - Fully associative
** CPUID leaf 04H provides details of deterministic ca che parameters, incl uding the L2 cach e in sub-leaf 2
80000007H EAX
EBX
ECX
Bits 07-00: Reserved = 0.
Bit 08: Invariant TSC available if 1.Bits 31-09: Reserved = 0.
80000008H EAX Linear/Physical Address size.
Bits 07-00: #Physical Address Bits*.
Bits 15-08: #Linear Address Bits.
EBX
ECX
EDXBits 08-00: Reserved = 0.
Bit 09: WBNOINVD is available if 1.Bits 31-10: Reserved = 0.
NOTES:
* If CPUID.80000008H:EAX[7:0] is supported, the ma ximum physical address nu mber supported should 
come from this field. If TME-MK is enabled, the numb er of bits that can be used to address physical 
memory is CPUID.80000008H:EAX[7: 0] - IA32_TME_ACTIVATE[35:32].Table 3-8.  Information Returned by CPUID Instruction (Contd.)
Vol. 2A 3-241INPUT EAX = 01H: Returns Model,  Family, Stepping Information
When CPUID executes with EAX set to 01H, version inform ation is returned in EAX (see Figure 3-6). For example: 
model, family, and processor type for the Inte l Xeon processor 5100 series is as follows:
•Model — 1111B
•Family — 0101B
•Processor Type — 00B
See Table 3-9 for available processor type va lues. Stepping IDs are provided as needed.
NOTE
See Chapter 20 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, 
for information on identifying earlier IA-32 processors.
The Extended Family ID needs to be ex amined only when the Family ID is 0F H. Integrate the fields into a display 
using the following rule:
IF Family_ID ≠ 0FH
THEN DisplayFam ily = Family_ID;
ELSE DisplayFamily = Extended_Family_ID + Family_ID;
FI;(* Show DisplayFamily as HEX field. *)Figure 3-6.  Version Informat ion Returned by CPUID in EAX
Table 3-9.  Processor Type Field 
Type Encoding
Original OEM Processor 00BIntel OverDrive
® Processor 01B
Dual processor (not applicable to Intel486 processors) 10BIntel reserved 11BOM16525Processor Type 0 34 78 111213141516 1920 2728 31
EAX
Family (0FH for the Pentium 4 Processor Family)
Model Extended
Family IDExtended
Model IDFamily
IDModelStepping
ID
Extended Family ID (0)
Extended Model ID (0)
ReservedCPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-242 Vol. 2AThe Extended Model ID needs to be exam ined only when the Family ID is 06 H or 0FH. Integrate the field into a 
display using the following rule:
IF (Family_ID = 06H or Family_ID = 0FH)
THEN DisplayModel = (Extended_Model_ID « 4) + Model_ID;(* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)ELSE DisplayModel = Model_ID;
FI;(* Show DisplayModel as HEX field. *)
INPUT EAX = 01H: Returns Additional Information in EBX
When CPUID executes with EAX set to 01H, addition al information is returned to the EBX register: 
•Brand index (low byte of EBX) — this number provides an  entry into a brand string table that contains brand 
strings for IA-32 processors. More information about this field is provided later in this section. 
•CLFLUSH instruction cache line size (second byte of EBX)  — this number indicates the size of the cache line 
flushed by the CLFLUSH and CLFLUSHOPT instructions in 8-byte increments. This field was introduced in the 
Pentium 4 processor.
•Local APIC ID (high byte of EBX) — this number is the 8-bit ID that is assigned to the local APIC on the 
processor during power up. This field was introduced in the Pentium 4 processor.
INPUT EAX = 01H: Returns Feature Information in ECX and EDX
When CPUID executes with EAX set to 01H, feature information is returned in ECX and EDX.
•Figure 3-7 and Table 3-10 show encodings for ECX.
•Figure 3-8 and Table 3-11 show encodings for EDX.
For all feature flags, a 1 indicates that the feature is supported. Use Intel to prop erly interpret feature flags.
NOTE
Software must confirm that a processor feature is  present using feature flags returned by CPUID 
prior to using the feature. Software should not de pend on future offerings retaining all features.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-243Figure 3-7.  Feature Information Returned in the ECX Register
Table 3-10.  Feature Information Returned in the ECX Register 
Bit # Mnemonic Description
0 SSE3 Streaming SIMD Extensions 3 (SSE3).  A value of 1 indicates th e processor supports this 
technology.
1P C L M U L Q D Q PCLMULQDQ.  A value of 1 indicates the processo r supports the PCLMULQDQ instruction.
2D T E S 6 4 64-bit DS Area.  A value of 1 indicates the processor supports DS area using 64-bit layout.
3 MONITOR MONITOR/MWAIT.  A value of 1 indicates the proc essor supports this feature. 
4 DS-CPL CPL Qualified Debug Store.  A value of 1 indicates the processo r supports the extensions to the 
Debug Store feature to allow for branch message storage qualified by CPL.
5V M X Virtual Machine Extensions.  A value of 1 indicates that the pr ocessor supports this technology.
6S M X Safer Mode Extensions. A value of 1 indicates that the proc essor supports this  technology. See 
Chapter 7, “Safer Mode Extensions Reference.”
7 EIST Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor su pports this 
8 TM2 Thermal Monitor 2.  A value of 1 indicates whether the processor supports this technology. 
9 SSSE3 A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A 
value of 0 indicates the in struction extensions are no t present in the processor.OM16524bCNXT-ID — L1 Context ID0 12345678910111213141516171819202122232425262728293031
ECX
TM2 — Thermal Monitor 2
EIST —  Enhanced  Intel  SpeedStep®  Technology
DS-CPL — CPL Qualified Debug Store
MONITOR — MONITOR/MWAIT
PCLMULQDQ  —  Carryless Multiplication
ReservedCMPXCHG16B
SMX — Safer Mode ExtensionsxTPR Update Control
SSSE3 —  SSSE3 ExtensionsPDCM —  Perf/Debug Capability MSR
VMX — Virtual Machine Extensions  SSE4_1 —  SSE4.1OSXSAVE
SSE4_2 —  SSE4.2
DCA —  Direct Cache Accessx2APICPOPCNTXSAVEAVX
AES
FMA —  Fused Multiply Add
SSE3  —  SSE3 ExtensionsPCID —  Process-context Identifiers0
DTES64  —  64-bit DS AreaMOVBETSC-DeadlineF16CRDRAND
SDBGCPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-244 Vol. 2A10 CNXT-ID L1 Context ID. A value of 1 indicates the L1  data cache mode can be se t to either adaptive mode 
or shared mode. A value of 0 indicates this fe ature is not supported. See definition of the 
IA32_MISC_ENABLE MSR Bit 24 (L1 Da ta Cache Context Mode) for details.
11 SDBG A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.
12 FMA A value of 1 indicates the processor supports FMA extensions using YMM state.13 CMPXCHG16B CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the 
“CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes” section in this chapter for a 
14 xTPR Update

AES
14 xTPR Update 
ControlxTPR Update Control. A value of 1 indicates that th e processor supports changing 
IA32_MISC_ENABLE[bit 23]. 
15 PDCM Perfmon and Debug Capability: A value of 1 indicates the proc essor supports the performance 
and debug feature indication MSR IA32_PERF_CAPABILITIES.
16 Reserved Reserved
17 PCID Process-context identifiers.  A value of 1 indicates that the processor supports PCIDs and that 
software may set CR4.PCIDE to 1.
18 DCA  A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped 
device.
19 SSE4_1 A value of 1 indicates that the processor supports SSE4.1. 
20 SSE4_2 A value of 1 indicates that the processor supports SSE4.2. 21 x2APIC A value of 1 indicates that th e processor supports x2APIC feature.
22 MOVBE A value of 1 indicates that th e processor supports MOVBE instruction.
23 POPCNT A value of 1 indicate s that the processor suppor ts the POPCNT instruction.
24 TSC-Deadline A value of 1 indicates that the processor’ s local APIC timer supports one-shot operation using a 
TSC deadline value.
25 AESNI A value of 1 indicates that the proces sor supports the AESNI instruction extensions.
26 XSAVE A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states 
feature, the XSETBV/XGETBV instructions, and XCR0.
27 OSXSAVE A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to  enable XSETBV/XGETBV 
instructions to access XCR0 and to support processor extended state management using 
XSAVE/XRSTOR.
28 AVX A value of 1 indicates the processor supports the AVX instruction extensions.
29 F16C A value of 1 indicates that processor supports 16-bit floating -point conversion  instructions.
30 RDRAND A value of 1 indicates that processor supports RD RAND instruction.
31 Not Used Always returns 0.Table 3-10.  Feature Information Retu rned in the ECX Register  (Contd.)
Bit # Mnemonic DescriptionCPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-245 
Figure 3-8.  Feature Information Returned in the EDX RegisterOM16523PBE–Pend. Brk. EN.012345678910111213141516171819202122232425262728293031
EDX
TM–Therm. Monitor
HTT–Multi-threading
SS–Self SnoopSSE2–SSE2 ExtensionsSSE–SSE ExtensionsFXSR–FXSAVE/FXRSTORMMX–MMX Technology
ACPI–Thermal Monitor and Clock Ctrl
DS–Debug StoreCLFSH–CLFLUSH instructionPSN–Processor Serial Number
PSE-36 – Page Size Extension
PAT–Page Attribute Table
CMOV–Conditional Move/Compare Instruction
MCA–Machine Check ArchitecturePGE–PTE Global BitMTRR–Memory Type Range Registers
SEP–SYSENTER and SYSEXIT
APIC–APIC on ChipCX8–CMPXCHG8B Inst.MCE–Machine Check ExceptionPAE–Physical Address ExtensionsMSR–RDMSR and WRMSR Support
TSC–Time Stamp Counter
PSE–Page Size Extensions
DE–Debugging Extensions
VME–Virtual-8086 Mode Enhancement
FPU–x87 FPU on Chip
3-246 Vol. 2ATable 3-11.  More on Feature Inform ation Returned in the EDX Register
0 FPU Floating-Point Unit On-Chip.  The processor contains an x87 FPU.
1 VME Virtual 8086 Mode Enhancements.  Virtual 8086 mode enhancements, including CR4.VME for controlling the 
feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirect ion, expansion of the TSS 
with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags. 
2 DE Debugging Extensions.  Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional 
trapping of accesses to DR4 and DR5. 
3 PSE Page Size Extension.  Large pages of size 4 MByte are supported, including CR4.PSE for controlling the 
feature, the defined dirty bit in PDE (Page Directory Entr ies), optional reserved bit trapping in CR3, PDEs, and 
PTEs. 
4 TSC Time Stamp Counter.  The RDTSC instruction is supported, including CR4.TSD for controlling privilege.
5 MSR Model Specific Registers RDMSR and WRMSR Instructions.  The RDMSR and WRMSR instructions are 
supported. Some of the MSRs are implementation dependent.
6 PAE Physical Address Extension.  Physical addresses greater than 32 bits are supported: extended page table 
entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of 
4 Mbyte pages if PAE bit is 1. 
7 MCE Machine Check Exception.  Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the 
feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor 
version to do model specific processing of the exception, or test for the presence of the Machine Check feature.
8 CX8 CMPXCHG8B Instruction.  The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly 
locked and atomic). 
9 APIC APIC On-Chip. The processor contains an Advanced Programmabl e Interrupt Controller (A PIC), responding to 
memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some 
processors permit the APIC to be relocated). 
10 Reserved Reserved 
11 SEP SYSENTER and SYSEXIT Instructions.  The SYSENTER and SYSEXIT and associated MSRs are supported. 
12 MTRR Memory Type Range Registers.  MTRRs are supported. The MTRRcap MSR contains feature bits that describe 
what memory types are supported, how many variable  MTRRs are supported, and whether fixed MTRRs are 
supported. 
13 PGE Page Global Bit.  The global bit is supported in paging-structure  entries that map a page, indicating TLB entries 
that are common to differ ent processes and need not be flushed. The CR4.PGE bit controls this feature. 
14 MCA Machine Check Architecture.  A value of 1 indicates the Machine Check Architecture of reporting machine 
errors is supported. The MCG_CAP MSR contains featur e bits describing how many banks of error reporting 
MSRs are supported. 
15 CMOV Conditional Move Instructions.  The conditional move instruction CMOV is supported. In addition, if x87 FPU is 
present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported 
16 PAT Page Attribute Table.  Page Attribute Table is supported. This feature augments the Memory Type Range 
Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear 
address on a 4KB granularity.
17 PSE-36 36-Bit Page Size Extension.  4-MByte pages addressing physical memory beyond 4 GBytes are supported with 
32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in 
bits 20:13 of the page-directory entry.  Such physical addresses are limited by MAXPHYADDR and may be up to 
40 bits in size.
18 PSN Processor Serial Number. The processor supports the 96-bit processo r identification numb er feature and the 
feature is enabled.
19 CLFSH CLFLUSH Instruction.  CLFLUSH Instruction is supported.
20 Reserved ReservedCPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-247INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX
When CPUID executes with EAX set to 02H, the processor returns information about the processor’s internal TLBs, 
cache, and prefetch hardware in the EAX, EBX, ECX, an d EDX registers. The information is reported in encoded 
form and fall into the following categories:
•The least-significant byte in register EAX (register AL) will always return 01H . Software should ignore this value 
and not interpret it as an informational descriptor.
•The most significant bit (bit 31) of each register indicates whether the register contains valid information (set 
to 0) or is reserved (set to 1).
•If a register contains valid information, the information is contained in 1 byte descriptors. There are four types 
of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-12. Table 
3-12 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX 
registers is not defined; that is, specific bytes are no t designated to contain descriptors for specific cache, 
prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general 
descriptor type (FFH) and not report any byte descriptor of “cache type” via CPUID leaf 2.21 DS Debug Store.  The processor supports the ability to write debug information into a memory resident buffer. 
This feature is used by the branch trace store (BTS) and processor event-based sampling (PEBS) facilities (see 
Chapter 24, “Introduction to Virtual Machine Extensions,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manu al, Volume 3C).
22 ACPI Thermal Monitor and Software Controlled Clock Facilities.  The processor implements internal MSRs that 
allow processor temperature to be monitored and proces sor performance to be modulated in predefined duty 
cycles under so ftware control.
23 MMX Intel MMX Technology. The processor supports th e Intel MMX technology.

24 FXSR FXSAVE and FXRSTOR Instructions.  The FXSAVE and FXRSTOR instructions  are supported fo r fast save and 
restore of the floating-point context. Presence of this bit also indicates that CR4. OSFXSR is available for an 
operating system to indicate  that it supports the FXSA VE and FXRSTOR instructions.
25 SSE SSE.  The processor supports  the SSE extensions.
26 SSE2 SSE2.  The processor supports  the SSE2 extensions.
27 SS Self Snoop.  The processor supports the management of confli cting memory types by performing a snoop of its 
own cache structure for transa ctions issued to the bus.
28 HTT Max APIC IDs reserved field is Valid.  A value of 0 for HTT indicates there is  only a single lo gical processor in 
the package and software should assume only a single AP IC ID is reserved. A value of 1 for HTT indicates the 
value in CPUID.1.EBX[23:16] (the Maximum number of addr essable IDs for logical proce ssors in this package) is 
valid for the package.
29 TM Thermal Monitor.  The processor implements the thermal monito r automatic thermal co ntrol circuitry (TCC).
30 Reserved Reserved31 PBE Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the 
stop-clock state (STPCLK# is assert ed) to signal the proces sor that an interrupt is  pending and that the 
processor should return to normal operation to handle the interrupt.Table 3-11.  More on Feature Informatio n Returned in the ED X Register (Contd.)
3-248 Vol. 2ATable 3-12.  Encoding of CPUID Leaf 2 Descriptors 
 Descriptor
ValueType Cache or TLB Description
00H General Null descriptor, this byte contains no information.
01H TLB Instruction TLB: 4 KByte pages,  4-way set associat ive, 32 entries.
02H TLB Instruction TLB: 4 MByte pages, fully associative, 2 entries.03H TLB Data TLB: 4 KByte pages, 4- way set associative, 64 entries.
04H TLB Data TLB: 4 MByte pages, 4-way set associat ive, 8 entries.
05H TLB Data TLB1: 4 MByte pages, 4-way set associative, 32 entries.06H Cache 1st-level instruction ca che: 8 KBytes, 4-way set associative, 32  byte line size.
08H Cache 1st-level instruction ca che: 16 KBytes, 4-way set associative, 32 byte line size.
09H Cache 1st-level instruction ca che: 32KBytes, 4-way set associative, 64 byte line size.
0AH Cache 1st-level data cache: 8 KBytes, 2- way set associative, 32 byte line size.
0BH TLB Instruction TLB: 4 MByte pages,  4-way set associ ative, 4 entries.
0CH Cache 1st-level data cache: 16 KBytes, 4- way set associative, 32 byte line size.
0DH Cache 1st-level data cache: 16 KBytes, 4- way set associative, 64 byte line size.
0EH Cache 1st-level data cache: 24 KBytes, 6- way set associative, 64 byte line size.
1DH Cache 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size.
21H Cache 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size.22H Cache 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector.23H Cache 3rd-level cache: 1 MBytes, 8-way set asso ciative, 64 byte line si ze, 2 lines per sector.
24H Cache 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size.25H Cache 3rd-level cache: 2 MBytes, 8-way set asso ciative, 64 byte line si ze, 2 lines per sector.
29H Cache 3rd-level cache: 4 MBytes, 8-way set asso ciative, 64 byte line si ze, 2 lines per sector.
2CH Cache 1st-level data cache: 32 KBytes, 8- way set associative, 64 byte line size.
30H Cache 1st-level instruction ca che: 32 KBytes, 8-way set associative, 64 byte line size.
40H Cache No 2nd-level cache or, if processor contai ns a valid 2nd-level cach e, no 3rd-level cache.
41H Cache 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size.42H Cache 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size.43H Cache 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size.44H Cache 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size.45H Cache 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size.46H Cache 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size.47H Cache 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size.48H Cache 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size.49H Cache 3rd-level cache: 4MB, 16-way set associative, 64 -byte line size (Intel Xeon processor MP, Family 0FH, 
Model 06H);
2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size.
4AH Cache 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size.
4BH Cache 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size.
4CH Cache 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size.
4DH Cache 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size.
4EH Cache 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size.4FH TLB Instruction TLB: 4 KByte pages, 32 entries.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-24950H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries.
51H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries.52H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries.55H TLB Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries.56H TLB Data TLB0: 4 MByte pages, 4-way set associative, 16 entries.57H TLB Data TLB0: 4 KByte pages, 4-way associative, 16 entries.59H TLB Data TLB0: 4 KByte pages, fully associative, 16 entries.
5AH TLB Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries.
5BH TLB Data TLB: 4 KByte and 4 MByte pages, 64 entries.
5CH TLB Data TLB: 4 KByte and 4 MByte pages,128 entries.
5DH TLB Data TLB: 4 KByte and 4 MByte pages,256 entries.
60H Cache 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size.61H TLB Instruction TLB: 4 KByte pages, fully associative, 48 entries.63H TLB Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte 
pages, 4-way set associativ e, 4 entries.
64H TLB Data TLB: 4 KByte pages, 4- way set associative, 512 entries.
66H Cache 1st-level data cache: 8 KByte, 4- way set associative, 64 byte line size.
67H Cache 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size.68H Cache 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size.
6AH Cache uTLB: 4 KByte pages, 8- way set associative, 64 entries.
6BH Cache DTLB: 4 KByte pages, 8-way set associative, 256 entries.
6CH Cache DTLB: 2M/4M pages, 8-way set associative, 128 entries.
6DH Cache DTLB: 1 GByte pages, fu lly associative, 16 entries.
70H Cache Trace cache: 12 K- μop, 8-way set associative.
71H Cache Trace cache: 16 K- μop, 8-way set associative.
72H Cache Trace cache: 32 K- μop, 8-way set associative.
76H TLB Instruction TLB: 2M/4M pages,  fully associative, 8 entries.
78H Cache 2nd-level cache: 1 MByte, 4-wa y set associative, 64byte line size.
79H Cache 2nd-level cache: 128 KByte, 8-way set asso ciative, 64 byte line size, 2 lines per sector.
7AH Cache 2nd-level cache: 256 KByte, 8-way set asso ciative, 64 byte line size, 2 lines per sector.
7BH Cache 2nd-level cache: 512 KByte, 8-way set asso ciative, 64 byte line size, 2 lines per sector.
7CH Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector.
7DH Cache 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size.
7FH Cache 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size.
80H Cache 2nd-level cache: 512 KByte, 8-wa y set associative, 64-byte line size.
82H Cache 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size.83H Cache 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size.84H Cache 2nd-level cache: 1 MByte, 8-way set associative, 32  byte line size.
85H Cache 2nd-level cache: 2 MByte, 8-way set associative, 32  byte line size.
86H Cache 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size.87H Cache 2nd-level cache: 1 MByte, 8-way set associative, 64  byte line size.Table 3-12.  Encoding of CPUID Leaf 2 Descriptors  (Contd.)
ValueType Cache or TLB DescriptionCPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-250 Vol. 2AA0H DTLB DTLB: 4k pages, fully  associative, 32 entries.
B0H TLB Instruction TLB: 4 KByte pages,  4-way set associative, 128 entries.
B1H TLB Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries.B2H TLB Instruction TLB: 4KByte pages,  4-way set associat ive, 64 entries.
B3H TLB Data TLB: 4 KByte pages, 4- way set associativ e, 128 entries.
B4H TLB Data TLB1: 4 KByte pages, 4-way associative, 256 entries.B5H TLB Instruction TLB: 4KByte pages,  8-way set associat ive, 64 entries.
B6H TLB Instruction TLB: 4KByte pages,  8-way set associative, 128 entries.
BAH TLB Data TLB1: 4 KByte pages, 4-way associativ e, 64 entries.
C0H TLB Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries.
C1H STLB Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries.

C2H DTLB DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries.C3H STLB Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6- way associative, 1536 entrie s. Also 1GBbyte pages, 4-
way, 16 entries.
C4H DTLB DTLB: 2M/4M Byte pages, 4-way associative, 32 entries.
CAH STLB Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries.
D0H Cache 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size.D1H Cache 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size.D2H Cache 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size.D6H Cache 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size.D7H Cache 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size.D8H Cache 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size.
DCH Cache 3rd-level cache: 1.5 MByte, 12-way  set associative, 64  byte line size.
DDH Cache 3rd-level cache: 3 MByte, 12-way set associat ive, 64 byte  line size.
DEH Cache 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size.
E2H Cache 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size.E3H Cache 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size.E4H Cache 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size.
EAH Cache 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size.
EBH Cache 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size.
ECH Cache 3rd-level cache: 24 MByte, 24-way set associative, 64 byte line size.
F0H Prefetch 64-Byte prefetching.F1H Prefetch 128-Byte prefetching.
FEH General CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other 
address translation parameters.
FFH General CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters.Table 3-12.  Encoding of CPUID Leaf 2 Descriptors  (Contd.)
Vol. 2A 3-251Example 3-1.  Example of Cache and TLB Interpretation
The first member of the family of Pe ntium 4 processors returns the following information about caches and TLBs 
when the CPUID executes with an input value of 2:
EAX 66 5B 50 01H
EBX 0H
ECX 0H
EDX 00 7A 70 00H
Which means:
•The least-significant byte (byte 0) of register EA X is set to 01H. This value should be ignored.
•The most-significant bit of all four registers (EAX, EBX, EC X, and EDX) is set to 0, indicating that each register 
contains valid 1-byte descriptors.
•Bytes 1, 2, and 3 of register EAX indicate that the processor has:
— 50H - a 64-entry instruction TLB, for mapp ing 4-KByte and 2-MByte or 4-MByte pages.
— 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.
— 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size.
•The descriptors in registers EBX and ECX are valid, but contain NULL descriptors.
•Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has:
— 00H - NULL descriptor.— 70H - Trace cache: 12 K
-μop, 8-way set associative.
— 7AH - a 256-KByte 2nd level cache, 8-way set asso ciative, with a sectored, 64-byte cache line size.
— 00H - NULL descriptor.
INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level
When CPUID executes with EAX set to 04H and ECX contai ns an index value, the processor returns encoded data 
that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid 
index values start from 0.
Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an 
index value of 0, until the parameters re port the value associated with the cach e type field is 0. The architecturally 
defined fields reported by deterministic ca che parameters are documented in Table 3-8.
This Cache Size in Bytes
= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)
= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)
The CPUID leaf 04H also reports data that can be used to  derive the topology of processor cores in a physical 
package. This information is constant for all valid index values. Software can query the raw data reported by 
executing CPUID with EAX=04H and ECX=0 and use it as part of the topology  enumeration algorithm described in 
Chapter 9, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
INPUT EAX = 05H: Returns MONITOR and MW AIT Features
When CPUID executes with EAX set to 05H, the proce ssor returns information about features available to 
MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power manage-
ment. See Table 3-8. 
INPUT EAX = 06H: Returns Thermal and Power Management Features
When CPUID executes with EAX set to 06H, the processo r returns information about thermal and power manage-
ment features. See Table 3-8. CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-252 Vol. 2AINPUT EAX = 07H: Returns Structured Ex tended Feature Enumeration Information
When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum 
input value for sub-leaves that contain extended feature flags. See Table 3-8. 
When CPUID executes with EAX set to 07H and the input va lue of ECX is invalid (see leaf 07H entry in Table 3-8), 
the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest 
leaf 7 sub-leaf, and EBX, ECX & EDX contai n information of extended feature flags.
INPUT EAX = 09H: Returns Dire ct Cache Access Information
When CPUID executes with EAX set to 09H, the processo r returns information about Direct Cache Access capabili-
ties. See Table 3-8. 
INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features
When CPUID executes with EAX set to 0AH, the proce ssor returns information about support for architectural 
performance monitoring capabilities. Architectural performa nce monitoring is supported if the version ID (see Table 
3-8) is greater than Pn 0. See Table 3-8.
For each version of architectural performance monitoring capability, software must enumerate this leaf to discover 
the programming facilities and the architectural performa nce events available in the processor. The details are 
described in Chapter 24, “Introduction to Virtual Machine Extensions,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3C.
INPUT EAX = 0BH: Returns Extended Topology Information
CPUID leaf 1FH is a preferred superset to leaf 0BH. Inte l recommends first checking for the existence of Leaf 1FH 
before using leaf 0BH.
When CPUID executes with EAX set to 0BH, the processo r returns information about extended topology enumera-
tion data. Software must detect the presence of CPUID le af 0BH by verifying (a) the highest leaf index supported 
by CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.
INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information
When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector 
representation of all processor state extensions that are supported in the processor and storage size requirements of the XSAVE/XRSTOR area. See Table 3-8. 
When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns 
information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area. 
See Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves 
and obtain size and offset information for each processor extended state save area:
For i = 2 to 62 // sub-leaf 1 is reserved
IF (CPUID.(EAX=0DH, ECX=0H):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX
Execute CPUID.(EAX=0DH, ECX = i) to exam ine size and offset for sub-leaf i; 
FI;
INPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information
When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector 
representation of QoS monitoring resource types that ar e supported in the processor and maximum range of RMID 
values the processor can use to monitor of any supported reso urce types. Each bit, starti ng from bit 1, corresponds 
to a specific resource type if the bit is set. The bit posi tion corresponds to the sub-leaf index (or ResID) that soft-
ware must use to query QoS monitoring capab ility available for that type. See Table 3-8.
When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-
mation software can use to program IA32_PQR_ASSOC, IA3 2_QM_EVTSEL MSRs before reading QoS data from the 
IA32_QM_CTR MSR.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L

FI;
Vol. 2A 3-253INPUT EAX = 10H: Returns Intel Resour ce Director Technology (Intel RDT) Allocation Enumeration Information
When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector 
representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit 
1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or 
ResID) that software must use to query QoS enforcem ent capability available for that type. See Table 3-8.
When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-
mation about available classes of service and range of Qo S mask MSRs that software can use to configure each 
class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.
INPUT EAX = 12H: Returns Intel SGX Enumeration Information
When CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capa-
bilities. See Table 3-8. 
When CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attri-
butes. See Table 3-8. 
When CPUID executes with EAX set to 12H and ECX = n (n  > 1), the processor returns information about Intel SGX 
Enclave Page Cache. See Table 3-8.
INPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information
When CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor 
Trace extensions. See Table 3-8. 
When CPUID executes with EAX set to 14H and ECX = n (n  > 0 and less than the number of non-zero bits in 
CPUID.(EAX=14H, ECX= 0H).EAX), the processor returns in formation about packet generation in Intel Processor 
Trace. See Table 3-8. 
INPUT EAX = 15H: Returns Time Stamp Counter and Nominal Core Crystal Clock Information
When CPUID executes with EAX set to 15H and ECX = 0H , the processor returns information about Time Stamp 
Counter and Core Crystal Clock. See Table 3-8.
INPUT EAX = 16H: Returns Proc essor Frequency Information
When CPUID executes with EAX set to  16H, the processor returns information about Processor Frequency Informa-
tion. See Table 3-8. 
INPUT EAX = 17H: Returns System-On-Chip Information
When CPUID executes with EAX set to 17H, the processo r returns information about the System-On-Chip Vendor 
Attribute Enumeration. See Table 3-8. 
INPUT EAX = 18H: Returns Deterministic Ad dress Translation Para meters Information
When CPUID executes with EAX set to 18H, the processo r returns information about the Deterministic Address 
Translation Parameters. See Table 3-8. 
INPUT EAX = 19H: Returns Key Locker Information
When CPUID executes with EAX set to 19H, the processo r returns information about Key Locker. See Table 3-8. 
INPUT EAX = 1AH: Returns Na tive Model ID Information
When CPUID executes with EAX set to 1AH, the processo r returns information about Native Model Identification. 
See Table 3-8.
INPUT EAX = 1BH: Returns PCONFIG Information
When CPUID executes with EAX set to 1BH, the processo r returns information about PCONFIG capabilities. This 
information is enumerated in sub-leaves sele cted by the value of ECX (starting with 0).CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-254 Vol. 2AEach sub-leaf of CPUID function 1BH enumerates its sub-leaf type  in EAX. If a sub-leaf type is 0, the sub-leaf is 
invalid and zero is returned in EBX, ECX, and EDX. In this  case, all subsequent sub-leaves (selected by larger input 
values of ECX) are also invalid.
The only valid sub-leaf type currently defined is 1, indicati ng that the sub-leaf enumerates target identifiers for the 
PCONFIG instruction. Any non-zero value returned in EBX, ECX, or EDX indicates a valid target identifier of the 
PCONFIG instruction (any value of zero should be ignored). The only target identifier cu rrently defined is 1, indi-
cating TME-MK. See the “PCONFIG—Platform Configuration” instruction in Chapter 4 of the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 2B, for more information.
INPUT EAX = 1CH: Returns Last  Branch Record Information
When CPUID executes with EAX set to 1CH, the proce ssor returns information about LBRs (the architectural 
feature). See Table 3-8.
INPUT EAX = 1DH: Returns Tile Information
When CPUID executes with EAX set to 1DH and ECX = 0H, the processor returns information about tile 
architecture. See Table 3-8.
When CPUID executes with EAX set to 1DH and ECX = 1H, the processor returns information about tile palette 1. 
INPUT EAX = 1EH: Returns TMUL Information
When CPUID executes with EAX set to 1EH and ECX = 0H, the processor returns information about TMUL 
capabilities. See Table 3-8.
INPUT EAX = 1FH: Returns V2 Extended Topology Information
When CPUID executes with EAX set to 1FH, the processo r returns information about extended topology enumera-
tion data. Software must detect the presence of CPUID le af 1FH by verifying (a) the highest leaf index supported 
by CPUID is >= 1FH, and (b) CPUID.1FH:EBX[15: 0] reports a non-zero value. See Table 3-8. 
INPUT EAX = 20H: Returns History Reset Information
When CPUID executes with EAX set to 20H, the processo r returns information about History Reset. See Table 3-8.
METHODS FOR RETURNING BRANDING INFORMATION
Use the following techniques to access branding information:
1. Processor brand string method.
2. Processor brand index; this method uses a software supplied brand string table.These two methods are discussed in the following sections. For methods that are available in early processors, see 
Section: “Identification of Earlier IA-32 Processors” in Chapter 20 of the Intel
® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 1.
The Processor Brand String Method
Figure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software 
should execute this algorithm on all Intel 64 and IA-32 processors. 
This method (introduced with Pentium 4 processors) return s an ASCII brand identification string and the Processor 
Base frequency of the processor to th e EAX, EBX, ECX, and EDX registers.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-255How Brand Strings Work
To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input 
value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-termi-
nated.
Table 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.Figure 3-9.  Determination of Su pport for the Processor Brand String
Table 3-13.  Processor Brand String Returned with Pentium 4 Processor 
EAX Input Value Return Values ASCII Equivalent
80000002H EAX = 20202020H
EBX = 20202020H
ECX = 20202020H
EDX = 6E492020H“ ”  
“”
“”“nI  ”
80000003H EAX = 286C6574H
EBX = 50202952H
ECX = 69746E65H
EDX = 52286D75H“(let”
“P )R”
“itne”“R(mu”OM15194IF (EAX & 0x80 000000)CPUID
IF (EAX Return Value 
≥0x80000004)CPUID 
Function
SupportedTrue ≥
Extended
EAX Return Value =
Max. Extended CPUID
Function IndexInput: EAX= 0x80000000
Processor Brand
String Not
SupportedFalse
String SupportedTrueCPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-256 Vol. 2AExtracting the Processor Frequency from Brand Strings
Figure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the 
processor brand string.
The Processor Brand Index Method
The brand index method (introduced with Pentium® III Xeon® processors) provides an entry point into a brand 
identification table that is maintained in memory by system software and is accessible from system- and user-level 
code. In this table, each brand index is associate with an AS CII brand identification string that identifies the official 
Intel family and model number of a processor.
When CPUID executes with EAX set to 1, the processor retu rns a brand index to the low byte in EBX. Software can 
then use this index to locate the brand identification stri ng for the processor in the brand identification table. The 
first entry (brand index 0) in this table is reserved, allowi ng for backward compatibility with processors that do not 
support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand 
index method is no longer supported . Use brand string method instead.
Table 3-14 shows brand indices that have identification strings associated with them.80000004H EAX = 20342029H
EBX = 20555043H
ECX = 30303531H
EDX = 007A484DH“ 4 )”
“ UPC”
“0051”
“\0zHM”
Figure 3-10.  Algorithm for Extracting Processor FrequencyTable 3-13.  Processor Brand String Retu rned with Pentium 4 Processor  (Contd.)
IF Substring Matched"zHM", or 
"zHG", or 
"zHT"
Determine "Freq"
and "Multiplier"True
Determine "Multiplier"Scan "Brand String" in
Reverse Byte Order

“ UPC”
“0051”
“\0zHM”
"zHG", or 
"zHT"
Report ErrorFalse
Scan Digits 
Until BlankMatch
Substring
Determine "Freq"Reverse Digits
To Decimal Value
Processor Base
Frequency =
"Freq" x "Multiplier""Freq" = X.YZ if
Digits = "ZY.X"In Reverse OrderIf "zHM"
If "zHG"
If "zHT"Multiplier = 1 x 1012Multiplier = 1 x 109Multiplier = 1 x 106CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-257IA-32 Architecture Compatibility
CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the 
Intel486 processor.
Operation
IA32_BIOS_SIGN_ID MSR := Update with installed microcode revision number;
CASE (EAX) OF
EAX = 0:
EAX := Highest basic function input value understood by CPUID;
EBX := Vendor identifi cation string;
EDX := Vendor identification string;
ECX := Vendor identifi cation string;
BREAK;EAX 
= 1H:
EAX[3:0] := Stepping ID; 
EAX[7:4] := Model; 
EAX[11:8] := Family; Table 3-14.  Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings
Brand Index Brand String
00H This processor does not support the brand identification feature
01H Intel(R) Celeron(R) processor1
02H Intel(R) Pentium(R) III processor1
03H Intel(R) Pentium(R) III Xeon(R) processor; If proce ssor signature = 000006B1h, th en Intel(R) Celeron(R) 
processor
04H Intel(R) Pentium(R) III processor06H Mobile Intel(R) Pent ium(R) III processor-M
07H Mobile Intel(R) Celeron(R) processor
1
08H Intel(R) Pentium(R) 4 processor
09H Intel(R) Pentium(R) 4 processor
0AH Intel(R) Celeron(R) processor1
0BH Intel(R) Xeon(R) processo r; If processor signature = 00000F13h,  then Intel(R) Xe on(R) processor MP
0CH Intel(R) Xeon(R) processor MP0EH Mobile Intel(R) Pentium(R) 4 processor-M; If processo r signature = 00000F13h, then Intel(R) Xeon(R) processor
0FH Mobile Intel(R) Celeron(R) processor
1
11H Mobile Genuine Intel(R) processor
12H Intel(R) Celeron(R) M processor
13H Mobile Intel(R) Celeron(R) processor1
14H Intel(R) Celeron(R) processor
15H Mobile Genuine Intel(R) processor
16H Intel(R) Pentium(R) M processor
17H Mobile Intel(R) Celeron(R) processor1
18H – 0FFH RESERVED
NOTES:
1. Indicates versions of these processors that were introduced  after the Pentium III CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-258 Vol. 2AEAX[13:12] := Processor type; 
EAX[15:14] := Reserved;
EAX[19:16] := Extended Model;
EAX[27:20] := Extended Family;
EAX[31:28] := Reserved;
EBX[7:0] := Brand Index; (* Reserved if the value is zero. *)
EBX[15:8] := CLFLUSH Line Size;
EBX[16:23] := Reserved; (* Number of threads enab led = 2 if MT enable fuse set. *)
EBX[24:31] := Initial APIC ID;
ECX := Feature flags; (* See Figure 3-7. *)
EDX := Feature flags; (* See Figure 3-8. *)
BREAK;EAX 
= 2H:
EAX := Cache and TLB information; 
 EBX := Cache and TLB information; 
 ECX := Cache and TLB information; 
EDX := Cache and TLB information; 
BREAK;EAX 
= 3H:
EAX := Reserved; 
 EBX := Reserved; 
 ECX := ProcessorSerialN umber[31:0]; 
(* Pentium III processors only, otherwise reserved. *)EDX 
:= ProcessorSerialNumber[63:32]; 
(* Pentium III processors only, otherwise reserved. *
BREAKEAX
 = 4H:
EAX := Deterministic Cache Parameters  Leaf; (* See Table 3-8. *)
EBX := Deterministic Cache Parameters Leaf; 
 ECX := Deterministic Cache Parameters Leaf; 
EDX := Deterministic Cache Parameters Leaf; 
BREAK;EAX 
= 5H:
EAX := MONITOR/MWAIT Leaf; (* See Table 3-8. *)
 EBX := MONITOR/MWAIT Leaf; 
 ECX := MONITOR/MWAIT Leaf; 
EDX := MONITOR/MWAIT Leaf; 
BREAK;EAX 
= 6H:
EAX := Thermal and Power Management Leaf; (* See Table 3-8. *)
 EBX := Thermal and Power Management Leaf; 
 ECX := Thermal and Power Management Leaf; 
EDX := Thermal and Power Management Leaf; 
BREAK;EAX
 = 7H:
EAX := Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)
EBX := Structured Extended Feature Flags Enumeration Leaf; 
 ECX := Structured Extended Feature Flags Enumeration Leaf; 
EDX := Structured Extended Feature Flags Enumeration Leaf; 
BREAK;EAX 
= 8H:
EAX := Reserved = 0;
 EBX := Reserved = 0; 
 ECX := Reserved = 0; CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-259EDX := Reserved = 0; 
BREAK;EAX 
= 9H:
EAX := Direct Cache Access Informatio n Leaf; (* See Table 3-8. *)
 EBX := Direct Cache Access  Information Leaf; 
 ECX := Direct Cache Access Information Leaf; 
EDX := Direct Cache Access Information Leaf; 
BREAK;EAX 
= AH:
EAX := Architectural Performance Monitori ng Leaf; (* See Table 3-8. *)
 EBX := Architectural Performance Monitoring Leaf; 
 ECX := Architectural Performance Monitoring Leaf; 
EDX := Architectural Performa nce Monitoring Leaf; 
BREAK
EAX = BH:
EAX := Extended Topology Enumeration Leaf; (* See Table 3-8. *)
EBX := Extended Topology Enumeration Leaf; 
 ECX := Extended Topology Enumeration Leaf; 
EDX := Extended Topology Enumeration Leaf; 
BREAK;EAX 
= CH:
 ECX := Reserved = 0; 
EDX := Reserved = 0; 
BREAK;EAX 
= DH:
EAX := Processor Extended State Enumeration Leaf; (* See Table 3-8. *)
 EBX := Processor Extended State Enumeration Leaf; 
 ECX := Processor Extended State Enumeration Leaf; 
EDX := Processor Extended State Enumeration Leaf; 
BREAK;EAX 
= EH:
BREAK;EAX 
= FH:
EAX := Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)
 EBX := Intel Resource Director Technology Monitoring Enumeration Leaf; 
 ECX := Intel Resource Director Technology Monitoring Enumeration Leaf; 
EDX := Intel Resource Director Technology Monitoring Enumeration Leaf; 
BREAK;EAX 
= 10H:
EAX := Intel Resource Director  Technology Allocation Enumeration Leaf; (* See Table 3-8. *)
 EBX := Intel Resource Director  Technology Allocati on Enumeration Leaf; 
 ECX := Intel Resource Director  Technology Allocation Enumeration Leaf; 
EDX := Intel Resource Director  Technology Allocati on Enumeration Leaf; 
BREAK;EAX 
= 12H:
EAX := Intel SGX Enumeration Leaf; (* See Table 3-8. *)
 EBX := Intel SGX Enumeration Leaf; 
 ECX := Intel SGX Enumeration Leaf; CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-260 Vol. 2AEDX := Intel SGX Enumeration Leaf; 
BREAK;EAX 
= 14H:
EAX := Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *)
 EBX := Intel Processor Trace Enumeration Leaf; 
 ECX := Intel Processor Trace Enumeration Leaf; 
EDX := Intel Processor Trace Enumeration Leaf; 
BREAK;EAX 
= 15H:
EAX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; (* See Table 3-8. *)
 EBX := Time Stamp Counter and Nominal Core  Crystal Clock Information Leaf; 
 ECX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; 
EDX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; 
BREAK;EAX 
= 16H:
EAX := Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *)
 EBX := Processor Frequency Information Enumeration Leaf; 
 ECX := Processor Frequency Information Enumeration Leaf; 
EDX := Processor Frequency Information Enumeration Leaf; 
BREAK;EAX 
= 17H:
EAX := System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *)
 EBX := System-On-Chip Vendor Attribute Enumeration Leaf; 
 ECX := System-On-Chip Vendor Attribute Enumeration Leaf; 
EDX := System-On-Chip Vendor Attribute Enumeration Leaf; 
BREAK;EAX 
= 18H:
EAX := Deterministic Address Translation Parameters Enumeration Leaf; (* See Table 3-8. *)
 EBX := Deterministic Address Translation Parameters Enumeration Leaf; 
 ECX := Deterministic Address Translation Parameters Enumeration Leaf; 
EDX := Deterministic Address Translation Parameters Enumeration Leaf; 
BREAK;
EAX = 19H:
EAX := Key Locker Enumeration Leaf; (* See Table 3-8. *)
 EBX := Key Locker Enumeration Leaf; 
 ECX := Key Locker Enumeration Leaf; 
EDX := Key Locker Enumeration Leaf; 
BREAK;EAX
 = 1AH:
EAX := Native Model ID Enumeration Leaf; (* See Table 3-8. *)
EBX := Native Model ID Enumeration Leaf; 
 ECX := Native Model ID Enumeration Leaf; 
EDX := Native Model ID Enumeration Leaf; 
BREAK;EAX
 = 1BH:
EAX := PCONFIG Information Enumeration Leaf; (* See “INPUT EAX = 1BH: Returns PCONFIG Information” on page 3-253. *)
EBX := PCONFIG Information Enumeration Leaf; 
 ECX := PCONFIG Information Enumeration Leaf; 
EDX := PCONFIG Information Enumeration Leaf; 
BREAK;EAX
 = 1CH:
EAX := Last Branch Record Information Enumeration Leaf; (* See Table 3-8. *)
EBX := Last Branch Record Info rmation Enumeration Leaf; 
 ECX := Last Branch Record Information Enumeration Leaf; CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-261EDX := Last Branch Record Information Enumeration Leaf; 
BREAK;EAX
 = 1DH:
EAX := Tile Information Enumeration Leaf; (* See Table 3-8. *)
EBX := Tile Information Enumeration Leaf; 
 ECX := Tile Information Enumeration Leaf; 
EDX := Tile Information Enumeration Leaf; 
BREAK;EAX
 = 1EH:
EAX := TMUL Information Enumeration Leaf; (* See Table 3-8. *)
EBX := TMUL Information Enumeration Leaf; 
 ECX := TMUL Information Enumeration Leaf; 
EDX := TMUL Information Enumeration Leaf; 
BREAK;EAX
 = 1FH:

BREAK;EAX
 = 1CH:
BREAK;EAX
 = 1DH:
BREAK;EAX
 = 1EH:
BREAK;EAX
 = 1FH:
EAX := V2 Extended Topology Enumeration Leaf; (* See Table 3-8. *)
EBX := V2 Extended Topology Enumeration Leaf; 
 ECX := V2 Extended Topology Enumeration Leaf; 
EDX := V2 Extended Topology Enumeration Leaf; 
BREAK;EAX
 = 20H:
EAX := Processor History Reset Sub-leaf; (* See Table 3-8. *)
EBX := Processor History Reset Sub-leaf; 
 ECX := Processor History Reset Sub-leaf; 
EDX := Processor History Reset Sub-leaf; 
BREAK;EAX = 80000000H:
EAX 
:= Highest extended function inpu t value understood by CPUID;
EBX := Reserved; 
ECX := Reserved; 
EDX := Reserved; 
BREAK;EAX 
= 80000001H:
ECX := Extended Feature Bits (* See Table 3-8.*); 
EDX := Extended Feature Bits (* See Table 3-8. *); 
BREAK;EAX
 = 80000002H:
EAX := Processor Brand String; 
EBX := Processor Brand String, continued;
ECX := Processor Brand String, continued; 
EDX := Processor Brand String, continued; 
BREAK;EAX
 = 80000003H:
EAX := Processor Brand String, continued; 
EBX := Processor Brand String, continued; 
BREAK;EAX 
= 80000004H:
ECX := Processor Brand String, continued; CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
3-262 Vol. 2AEDX := Processor Brand String, continued;
BREAK;EAX
 = 80000005H:
EAX := Reserved = 0; 
EBX := Reserved = 0; 
ECX := Reserved = 0; 
BREAK;EAX
 = 80000006H:
ECX := Cache information; 
BREAK;EAX
 = 80000007H:
EDX := Reserved = Misc Feature Flags; 
BREAK;EAX
 = 80000008H:
EAX := Address Size Information; 
EBX := Misc Feature Flags; 
BREAK;EAX >= 40000000H and EAX <= 4FFFFFFFH:DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)
(* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)EAX 
:= Reserved; (* Information returned fo r highest basic information leaf. *)
EBX := Reserved; (* Information returned for highest basic information leaf. *)
ECX := Reserved; (* Information returned fo r highest basic information leaf. *)
EDX := Reserved; (* Information returned for highest basic information leaf. *)
BREAK;
ESAC;
None.
In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruc-
tion results in an invalid opcode (#UD) exception being generated.CRC32—Accumulate CRC32 ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-263CRC32—Accumulate CRC32 Value
Starting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial 
11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The 
source operand can be a register or a memory location. Th e destination operand must be an r32 or r64 register. If 
the destination is an r64 register, then the 32-bit resu lt is stored in the least significant double word and 
00000000H is stored in the most signific ant double word of the r64 register.
The initial value supplied in the destination operand is a do uble word integer stored in the r32 register or the least 
significant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result of the previous CRC32 operation in the destination operan d, then executes the CRC32 instruction again with new 
input data in the source operand. Data contained in the source operand is processed in reflected bit order. This 
means that the most significant bit of the source operand is  treated as the least significant bit of the quotient, and 
so on, for all the bits of the source operand. Likewise, th e result of the CRC operation is stored in the destination 
operand in reflected bit order. This means that the most sign ificant bit of the resulting CRC (bit 31) is stored in the 
least significant bit of the destination operand (b it 0), and so on, for all the bits of the CRC.
Operation
Notes:
BIT_REFLECT64: DST[63-0] = SRC[0-63]
BIT_REFLECT32: DST[31-0] = SRC[0-31]BIT_REFLECT16: DST[15-0] = SRC[0-15]BIT_REFLECT8: DST[7-0] = SRC[0-7]MOD2: Remainder from Polynomial division modulus 2Opcode/
En64-Bit 
F2 0F 38 F0 /r
CRC32 r32, r/m8RM Valid Valid Accumulate CRC32 on r/m8.
F2 REX 0F 38 F0 /r
CRC32 r32, r/m8
1
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH. RM Valid N.E. Accumulate CRC32 on r/m8.
F2 0F 38 F1 /r
CRC32 r32, r/m16RM Valid Valid Accumulate CRC32 on r/m16.
CRC32 r32, r/m32RM Valid Valid Accumulate CRC32 on r/m32.
F2 REX.W 0F 38 F0 /r
CRC32 r64, r/m8RM Valid N.E. Accumulate CRC32 on r/m8.
F2 REX.W 0F 38 F1 /r
CRC32 r64, r/m64RM Valid N.E. Accumulate CRC32 on r/m64.
RM ModRM:reg (r, w) ModRM:r/m (r) N/A N/ACRC32—Accumulate CRC32 ValueINSTRUCTION SET REFERENCE, A-L
3-264 Vol. 2ACRC32 instruction for 64-bit source operand and 64-bit destination operand:
TEMP1[63-0] := BIT_REFLECT64 (SRC[63-0])
TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])TEMP3[95-0] := TEMP1[63-0] « 32TEMP4[95-0] := TEMP2[31-0] « 64TEMP5[95-0] := TEMP3[95-0] XOR TEMP4[95-0]TEMP6[31-0] := TEMP5[95-0] MOD2 11EDC6F41HDEST[31-0] := BIT_REFLECT (TEMP6[31-0])DEST[63-32] := 00000000H
CRC32 instruction for 32-bit source operand and 32-bit destination operand:
TEMP1[31-0] := BIT_REFLECT32 (SRC[31-0])
TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])TEMP3[63-0] := TEMP1[31-0] « 32TEMP4[63-0] := TEMP2[31-0] « 32TEMP5[63-0] := TEMP3[63-0] XOR TEMP4[63-0]TEMP6[31-0] := TEMP5[63-0] MOD2 11EDC6F41HDEST[31-0] := BIT_REFLECT (TEMP6[31-0])
CRC32 instruction for 16-bit source operand and 32-bit destination operand:
TEMP1[15-0] := BIT_REFLECT16 (SRC[15-0])
TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])TEMP3[47-0] := TEMP1[15-0] « 32TEMP4[47-0] := TEMP2[31-0] « 16TEMP5[47-0] := TEMP3[47-0] XOR TEMP4[47-0]TEMP6[31-0] := TEMP5[47-0] MOD2 11EDC6F41HDEST[31-0] := BIT_REFLECT (TEMP6[31-0])
CRC32 instruction for 8-bit source operand and 64-bit destination operand:
TEMP1[7-0] := BIT_REFLECT8(SRC[7-0])
TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])TEMP3[39-0] := TEMP1[7-0] « 32TEMP4[39-0] := TEMP2[31-0] « 8TEMP5[39-0] := TEMP3[39-0] XOR TEMP4[39-0]TEMP6[31-0] := TEMP5[39-0] MOD2 11EDC6F41HDEST[31-0] := BIT_REFLECT (TEMP6[31-0])DEST[63-32] := 00000000H
CRC32 instruction for 8-bit source operand and 32-bit destination operand:
TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])TEMP3[39-0] := TEMP1[7-0] « 32TEMP4[39-0] := TEMP2[31-0] « 8TEMP5[39-0] := TEMP3[39-0] XOR TEMP4[39-0]TEMP6[31-0] := TEMP5[39-0] MOD2 11EDC6F41HDEST[31-0] := BIT_REFLECT (TEMP6[31-0])
None.CRC32—Accumulate CRC32 ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-265Intel C/C++ Compiler Intrinsic Equivalent
unsigned int _mm_crc32_ u8( unsigned int crc, unsigned char data )
unsigned int _mm_crc32_u1 6( unsigned int crc, unsigned short data )
unsigned int _mm_crc32_ u32( unsigned int crc, unsigned int data )
unsigned __int64 _mm_crc32_u64( unsigned __int64 crc, unsigned __int64 data )
None.
#GP(0) If a memory operand effective address is  outside the CS, DS, ES, FS or GS segments.
#PF (fault-code) For a page fault.
#UD If CPUID.01H:ECX.SSE4_2[Bit 20] = 0.
If LOCK prefix is used.
#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
Virtual 8086 Mode Exceptions
Same exceptions as in Protected Mode.
#GP(0) If the memory address is in a non-canonical form.#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

If LOCK prefix is used.CVTDQ2PD—Convert Packed Doubleword Integers to  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-266 Vol. 2ACVTDQ2PD—Convert Packed Double word Integers to Packed Double Precision Floating-Point 
Values
Converts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two, 
four or eight packed double precision floating-point values in the destination operand (the first operand). 
EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit 
memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand 
is a ZMM/YMM/XMM register conditionally updated with writ emask k1. Attempt to encode this instruction with EVEX 
embedded rounding is ignored.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is a YMM register. 
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination 
operand is a XMM register. The upper Bits (MAXVL-1:128 ) of the corresponding ZMM register destination are 
zeroed.
128-bit Legacy SSE version: The source operand is an XM M register or 64- bit memory location. The destination 
operand is an XMM register. The upper Bits (MAXVL-1: 128) of the corresponding ZMM register destination are 
unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Opcode/
Mode 
Feature 
F3 0F E6 /r
CVTDQ2PD xmm1, xmm2/m64A V/V SSE2 Convert two packed signed doubleword integers from 
xmm2/mem to two packed double precision floating-point 
values in xmm1.
VEX.128.F3.0F.WIG E6 /r
VCVTDQ2PD xmm1, xmm2/m64A V/V AVX Convert two packed signed doubleword integers from 
VEX.256.F3.0F.WIG E6 /r
VCVTDQ2PD ymm1, xmm2/m128A V/V AVX Convert four packed signed doubleword integers from 
xmm2/mem to four packed double precision floating-point values in ymm1.
EVEX.128.F3.0F.W0 E6 /r
VCVTDQ2PD xmm1 {k1}{z}, 
xmm2/m64/m32bcst BV / V A V X 5 1 2 V L
AVX512FConvert 2 packed signed doubleword integers from 
xmm2/m64/m32bcst to eight packed double precision 
floating-point values in xmm1 with writemask k1.
EVEX.256.F3.0F.W0 E6 /r
VCVTDQ2PD ymm1 {k1}{z}, 
xmm2/m128/m32bcst BV / V A V X 5 1 2 V L
AVX512FConvert 4 packed signed doubleword integers from 
xmm2/m128/m32bcst to 4 packed double precision 
floating-point values in ymm1 with writemask k1.
EVEX.512.F3.0F.W0 E6 /r
VCVTDQ2PD zmm1 {k1}{z}, 
ymm2/m256/m32bcst B V/V AVX512F Convert eight packed signed doubleword integers from 
ymm2/m256/m32bcst to eight packed double precision 
floating-point values in zmm1 with writemask k1.
B Half ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTDQ2PD—Convert Packed Doubleword Integers to  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-267Operation
VCVTDQ2PD (EVEX Encoded Versions) When SRC Operand is a Register
i := j * 64k := j * 32IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Integer_To_Double_Precisi on_Floating_Point(SRC[k+31:k])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0Figure 3-11.  CVTDQ2PD (VEX.256 encoded version)DESTSRC X0 X1 X2 X3
X3 X2 X1 X0CVTDQ2PD—Convert Packed Doubleword Integers to  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-268 Vol. 2AVCVTDQ2PD (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
THEN 
THEN
DEST[i+63:i] :=
Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE 
FI;
ELSE 
FI
FI;
VCVTDQ2PD (VEX.256 Encoded Version)
DEST[63:0] := Convert_Integer_To_Doubl e_Precision_Floating_Point(SRC[31:0])
DEST[127:64] := Convert_Integer_To_Doub le_Precision_Floatin g_Point(SRC[63:32])
DEST[191:128] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])DEST[255:192] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)DEST[MAXVL-1:256] := 0
VCVTDQ2PD (VEX.128 Encoded Version)
CVTDQ2PD (128-bit Legacy SSE Version)
DEST[MAXVL-1:128 ] (unmodified)
VCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);
VCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);VCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);VCVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src);VCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);VCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);VCVTDQ2PD __m128d _mm_mask_cvtepi32_pd(  __m128d s, __mmask8 k, __m128i a);
VCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);CVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)CVTDQ2PD—Convert Packed Doubleword Integers to  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-269Other Exceptions
VEX-encoded instructions, see Table 2-22, “Type 5 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-51,  “Type E5 Class Exception Conditions.”
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.CVTDQ2PS—Convert Packed Doubleword Integers to  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-270 Vol. 2ACVTDQ2PS—Convert Packed Doubleword Integers  to Packed Single Precision Floating-Point 
Values
Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen 
packed single precision floating-point values in the destination operand.
EVEX encoded versions: The source operand can be a Z MM/YMM/XMM register, a 512/256/128-bit memory location 
or a 512/256/128-bit vector broadcasted from a 32-bi t memory location. The destination operand is a 
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is a YMM re gister or 256- bit memory location. The destination 
operand is a YMM register. Bits (MAXVL-1:256) of the corresponding register destination are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.
128-bit Legacy SSE version: The source operand is an XM M register or 128- bit memory location. The destination 
operand is an XMM register. The upper Bits (MAXVL-1:128)  of the corresponding regist er destination are unmodi-
fied.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Opcode
Mode 
Feature 
NP 0F 5B /r
CVTDQ2PS xmm1, xmm2/m128A V/V SSE2 Convert four packed signed doubleword integers from 
xmm2/mem to four packed single precision floating-
point values in xmm1.
VEX.128.0F.WIG 5B /r
VCVTDQ2PS xmm1, xmm2/m128A V/V AVX Convert four packed signed doubleword integers from 
VEX.256.0F.WIG 5B /r
VCVTDQ2PS ymm1, ymm2/m256A V/V AVX Convert eight packed signed doubleword integers from 
ymm2/mem to eight packed single precision floating-point values in ymm1.
EVEX.128.0F.W0 5B /r
VCVTDQ2PS xmm1 {k1}{z}, 
xmm2/m128/m32bcstB V/V AVX512VL
AVX512FConvert four packed signed doubleword integers from 
xmm2/m128/m32bcst to four packed single precision 
floating-point values in xmm1with writemask k1.
EVEX.256.0F.W0 5B /r
VCVTDQ2PS ymm1 {k1}{z}, 
ymm2/m256/m32bcstB V/V AVX512VL
AVX512FConvert eight packed signed doubleword integers from 
ymm2/m256/m32bcst to eight packed single precision 
floating-point values in ymm1with writemask k1.
EVEX.512.0F.W0 5B /r
VCVTDQ2PS zmm1 {k1}{z}, 
zmm2/m512/m32bcst{er}B V/V AVX512F Convert sixteen packed signed doubleword integers 
from zmm2/m512/m32bcst to sixteen packed single 
precision floating-point values in zmm1with writemask 
k1.

k1.
B Full ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTDQ2PS—Convert Packed Doubleword Integers to  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-271Operation
VCVTDQ2PS (EVEX Encoded Versions) When SRC Operand is a Register
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC );  ; refer to Table 15-4 in the Intel
Software Developer’s Manual, Volume 1
ELSE 
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.R C);  ; refer to Table 15-4 in the Intel® 64 and IA-32 Architectures 
FI;
THEN DEST[i+31:i] :=
Convert_Integer_To_Single_Precisi on_Floating_Point(SRC[i+31:i])
ELSE 
FI
FI;
VCVTDQ2PS (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
DEST[i+31:i] :=
Convert_Integer_To_Single_Preci sion_Floating_Point(SRC[31:0])
ELSE 
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0CVTDQ2PS—Convert Packed Doubleword Integers to  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-272 Vol. 2AVCVTDQ2PS (VEX.256 Encoded Version)
DEST[31:0] := Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[31:0])
DEST[63:32] := Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[63:32])
DEST[95:64] := Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[95:64])
DEST[127:96] := Convert_Integer_To_Sing le_Precision_Floating_Point(SRC[127:96)
DEST[159:128] := Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[159:128])
DEST[191:160] := Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[191:160])
DEST[223:192] := Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[223:192])
DEST[255:224] := Convert_Integer_To_Sin gle_Precision_Floating_Point(SRC[255:224)
VCVTDQ2PS (VEX.128 Encoded Version)
DEST[127:96] := Convert_Integer_To_Sing le_Precision_Floating_Point(SRC[127z:96)
CVTDQ2PS (128-bit Legacy SSE Version)
VCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);
VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps(  __m512 s, __mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);
VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi3 2_ps( __mmask16 k, __m512i a, int r);
VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps(  __m256 s, __mmask8 k, __m256i a);
VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);
VCVTDQ2PS __m128 _mm_maskz_cvtepi 32_ps( __mmask8 k, __m128i a);
CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)
Precision.
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.CVTPD2DQ—Convert Packed Double Precision Floating-Point Values to Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-273CVTPD2DQ—Convert Packed Double Precision Fl oating-Point Values to Packed Doubleword 
Integers
Converts packed double precision floating-point values in  the source operand (second operand) to packed signed 
doubleword integers in the destination operand (first operand). 
When a conversion is inexact, the value returned is round ed according to the rounding control bits in the MXCSR 
register or the embedded rounding control bits. If a co nverted result cannot be represented in the destination 
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value 
(2w-1, where w represents the number of bits  in the destination format) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/ XMM register, a 512-bit memory location, or a 512-bit 
vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-
tionally updated with writemask k1. The upper bits (MAX VL-1:256/128/64) of the corresponding destination are 
zeroed.
operand is an XMM register. The upper bits (MAXVL-1:1 28) of the corresponding ZMM register destination are 
zeroed.
operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.
operand is an XMM register. Bits[127:64] of the destinat ion XMM register are zeroed. However, the upper bits 
(MAXVL-1:128) of the corresponding ZMM register destination are unmodified. 
VEX.vvvv and EVEX.vvvv ar e reserved and must be 1111b, otherwise instructions will #UD.Opcode
Mode 
Feature 
F2 0F E6 /r
CVTPD2DQ xmm1, xmm2/m128A V/V SSE2 Convert two packed double precision floating-point 
values in xmm2/mem to two signed doubleword 
integers in xmm1.
VEX.128.F2.0F.WIG E6 /r
VCVTPD2DQ xmm1, xmm2/m128A V/V AVX Convert two packed double precision floating-point 
VEX.256.F2.0F.WIG E6 /r
VCVTPD2DQ xmm1, ymm2/m256A V/V AVX Convert four packed double precision floating-point 
values in ymm2/mem to four signed doubleword 
EVEX.128.F2.0F.W1 E6 /r
VCVTPD2DQ xmm1 {k1}{z}, 
xmm2/m128/m64bcstB V/V AVX512VL
AVX512FConvert two packed double precision floating-point 
values in xmm2/m128/m64bcst to two signed 
doubleword integers in xmm1 subject to writemask k1.
EVEX.256.F2.0F.W1 E6 /r
ymm2/m256/m64bcstB V/V AVX512VL
AVX512FConvert four packed double precision floating-point 
values in ymm2/m256/m64bcst to four signed 
EVEX.512.F2.0F.W1 E6 /r
VCVTPD2DQ ymm1 {k1}{z}, 
zmm2/m512/m64bcst{er}B V/V AVX512F Convert eight packed double precision floating-point 
values in zmm2/m512/m64bcst to eight signed 
doubleword integers in ymm1  subject to writemask k1.
B Full ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTPD2DQ—Convert Packed Double Precision Floating-Point Values to Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A-L
3-274 Vol. 2AOperation
VCVTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)IF (VL = 512) AND (EVEX.b = 1) 
THEN
ELSE 
FI;
i := j * 32k := j * 64IF k1[j] OR *no writemask*
Convert_Double_Precision_Floating _Point_To_Integer(SRC[k+63:k])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0Figure 3-12.  VCVTPD2DQ (VEX.256 encoded version)DESTSRC
X0 X1 X2 X3X3 X2 X1 X0
0CVTPD2DQ—Convert Packed Double Precision Floating-Point Values to Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-275VCVTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Double_Precision_Floati ng_Point_To_Integer(SRC[63:0])
ELSE

THEN
ELSE 
FI;
ELSE 
FI
FI;
THEN 
THEN
ELSE 
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0
VCVTPD2DQ (VEX.256 Encoded Version)
DEST[31:0] := Convert_Double_Precision _Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] := Convert_Doub le_Precision_Float ing_Point_To_Integer(SRC[127:64])
DEST[95:64] := Convert_Doub le_Precision_Float ing_Point_To_Integer(SRC[191:128])
DEST[127:96] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)DEST[MAXVL-1:128] := 0
VCVTPD2DQ (VEX.128 Encoded Version)
DEST[MAXVL-1:64] := 0
CVTPD2DQ (128-bit Legacy SSE Version)
DEST[127:64] := 0DEST[MAXVL-1:128 ] (unmodified)CVTPD2DQ—Convert Packed Double Precision Floating-Point Values to Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A-L
3-276 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
VCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);
VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi3 2( __m256i s, __mmask8 k, __m512d a);
VCVTPD2DQ __m256i _mm512_maskz_cvt pd_epi32( __mmask8 k, __m512d a);
VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32 ( __m256i s, __mmask8 k,  __m512d a, int r);
VCVTPD2DQ __m256i _mm512_maskz_cvt_round pd_epi32( __mmask8 k, __m512d a, int r);
VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi3 2( __m128i s, __mmask8 k, __m256d a);
VCVTPD2DQ __m128i _mm256_maskz_cvt pd_epi32( __mmask8 k, __m256d a);
VCVTPD2DQ __m128i _mm_mask _cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);
VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)
Invalid, Precision.
See Table 2-19, “Type 2 Class Exception Conditions.”
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.CVTPD2PI—Convert Packed Double Precision Floa ting-Point Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-277CVTPD2PI—Convert Packed Double Precision Floa ting-Point Values to Packed Dword Integers
Converts two packed double precision floating-point values  in the source operand (second operand) to two packed 
signed doubleword integers in the destination operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-
nology register. 
register. If a converted result is larger than the maximu m signed doubleword integer, the floating-point invalid 
exception is raised, and if this exception is masked , the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MM X technology operation (that is, the x87 FPU top-of-stack 
pointer is set to 0 and the x87 FPU tag word is set to all 0s  [valid]). If this instruction is executed while an x87 FPU 
floating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] := Convert_Double_Precision _Floating_Point_To_Integer32(SRC[63:0]);
DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);
CVTPD1PI __m64 _mm_cvtpd_pi32(__m128d a)
See Table 23-4, “Exception Conditions for Legacy SIMD/M MX Instructions with FP Exception and 16-Byte Align-
ment” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.Opcode/
Mode 
Feature 
66 0F 2D /r
CVTPD2PI mm, xmm/m128RM V/V SSE2 Convert two packed double precision floating-
point values from xmm/m128 to two packed 
signed doubleword integers in mm.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTPD2PS—Convert Packed Double Precis ion Floating-Point Values to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-278 Vol. 2ACVTPD2PS—Convert Packed Double Precision Floati ng-Point Values to Packed Single Precision 
Converts two, four or eight packed double precision floa ting-point values in the source operand (second operand) 
to two, four or eight packed single precision floating-point values in the destination operand (first operand). 
register or the embedded rounding control bits. 
EVEX encoded versions: The source operand is a ZMM/YM M/XMM register, a 512/256/128-bit memory location, or 
a 512/256/128-bit vector broadcasted from a 64-bit  memory location. The destination operand is a 
YMM/XMM/XMM (low 64-bits) register conditionally updated with writemask k1. The upper bits (MAXVL-
1:256/128/64) of the corresponding destination are zeroed.
zeroed.
operand is a XMM register. The upper bits (MAXVL-1:64) of  the corresponding ZMM register destination are zeroed.
operand is an XMM register. Bits[127:64] of the destinat ion XMM register are zeroed. However, the upper Bits 
(MAXVL-1:128) of the corresponding ZMM register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.Opcode/
Mode 
Feature 
66 0F 5A /r
CVTPD2PS xmm1, xmm2/m128A V/V SSE2 Convert two packed double precision floating-point 
values in xmm2/mem to two single precision floating-
VEX.128.66.0F.WIG 5A /r
VCVTPD2PS xmm1, xmm2/m128A V/V AVX Convert two packed double precision floating-point 
 VEX.256.66.0F.WIG 5A /r
VCVTPD2PS xmm1, ymm2/m256A V/V AVX Convert four packed double precision floating-point 
values in ymm2/mem to four  single precision floating-
EVEX.128.66.0F.W1 5A /r
VCVTPD2PS xmm1 {k1}{z}, 
values in xmm2/m128/m64bcst to two single 
precision floating-point values in xmm1with 
EVEX.256.66.0F.W1 5A /r
VCVTPD2PS xmm1 {k1}{z}, ymm2/m256/m64bcst B V/V AVX512VL
values in ymm2/m256/m64bcst to four single precision floating-point values in xmm1with 
EVEX.512.66.0F.W1 5A /r
VCVTPD2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er}B V/V AVX512F Convert eight packed double precision floating-point 
values in zmm2/m512/m64bcst to eight single precision floating-point values in ymm1with 
B Full ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTPD2PS—Convert Packed Double Precision Floating-Point Values to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-279Operation
VCVTPD2PS (EVEX Encoded Version) When SRC Operand is a Register
THEN
ELSE 
FI;
THEN 
DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0Figure 3-13.  VCVTPD2PS (VEX.256 encoded version)DESTSRC
0CVTPD2PS—Convert Packed Double Precis ion Floating-Point Values to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-280 Vol. 2AVCVTPD2PS (EVEX Encoded Version) Wh en SRC Operand is a Memory Source

THEN
ELSE 
FI;
THEN 
ELSE 
FI
FI;
THEN 
THEN
DEST[i+31:i] :=Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE 
DEST[i+31:i] := Convert_Double_Pre cision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])
FI;
ELSE 
FI
FI;
VCVTPD2PS (VEX.256 Encoded Version)
DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])DEST[63:32] := Convert_Double_Precision_To_ Single_Precision_Floating_Point(SRC[127:64])
DEST[95:64] := Convert_Double_Precision_To_Si ngle_Precision_Floating_Point(SRC[191:128])
DEST[127:96] := Convert_Double_Precision_To _Single_Precision_Floating_Point(SRC[255:192)
VCVTPD2PS (VEX.128 Encoded Version)
CVTPD2PS (128-bit Legacy SSE Version)
DEST[127:64] := 0DEST[MAXVL-1:128 ] (unmodified)CVTPD2PS—Convert Packed Double Precision Floating-Point Values to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-281Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2PS __m256 _mm512_cvtpd_ps( __m512d a);
VCVTPD2PS __m256 _mm512_mask_cvtpd_ps( __m256 s, __mmask8 k, __m512d a);VCVTPD2PS __m256 _mm512_maskz_cvtpd_ps( __mmask8 k, __m512d a);VCVTPD2PS __m256 _mm512_cvt_roundpd_ps( __m512d a, int r);VCVTPD2PS __m256 _mm512_mask_cvt_roundpd_ps( __m256 s, __mmask8 k, __m512d a, int r);
VCVTPD2PS __m256 _mm512_maskz_cvt_roundpd_ps( __mmask8 k, __m512d a, int r);VCVTPD2PS __m128 _mm256_mask_cvtpd_ps( __m128 s, __mmask8 k, __m256d a);VCVTPD2PS __m128 _mm256_maskz_cvtpd_ps( __mmask8 k, __m256d a);VCVTPD2PS __m128 _mm_mask_cvtpd_ps( __m128 s, __mmask8 k, __m128d a);VCVTPD2PS __m128 _mm_maskz_cvtpd_ps( __mmask8 k, __m128d a);VCVTPD2PS __m128 _mm256_cvtpd_ps (__m256d a)CVTPD2PS __m128 _mm_cvtpd_ps (__m128d a)
Invalid, Precision, Underflow, Overflow, Denormal.
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.CVTPI2PD—Convert Packed Dword Integers to Pa cked Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-282 Vol. 2ACVTPI2PD—Convert Packed Dword Integers to Pa cked Double Precision Floating-Point Values
Converts two packed signed doubleword integers in the source operand (second operand) to two packed double 
precision floating-point values in the destination operand (first operand). 
The source operand can be an MMX technology register or  a 64-bit memory location. The destination operand is an 
XMM register. In addition, depend ing on the operand configuration:
•For operands xmm , mm: the instruction causes a transition from x87 FPU to MMX technology operation (that 
is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this 
instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPI2PD instruction is executed.
•For operands xmm , m64 : the instruction does not cause a transition to MMX technology and does not take 
x87 FPU exceptions.
Operation
DEST[63:0] := Convert_Integer_To_Doubl e_Precision_Floating_Point(SRC[31:0]);
DEST[127:64] := Convert_Integer_To_Doub le_Precision_Floatin g_Point(SRC[63:32]);
CVTPI2PD __m128d _mm_cvtpi32_pd(__m64 a)
None.
See Table 23-6, “Exception Conditions for Legacy SIMD/MMX  Instructions with XMM and without FP Exception” in 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.Opcode/
En64-Bit 
66 0F 2A /r
CVTPI2PD xmm, mm/m641
NOTES:
1. Operation is different for different operand sets; see the Description section.RM Valid Valid Convert two packed signed doubleword 
integers from mm/mem64 to two packed 
double precision floating-point values in xmm.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTPI2PS—Convert Packed Dword Integers to Pa cked Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-283CVTPI2PS—Convert Packed Dword Integers to Pa cked Single Precision Floating-Point Values
Converts two packed signed doubleword  integers in the source operand (second operand) to two packed single 
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an 
XMM register. The results are stored in the low quadword  of the destination operand, and the high quadword 
remains unchanged. When a conversion is inexact, the valu e returned is rounded according to the rounding control 
bits in the MXCSR register. 
floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.
Operation
DEST[31:0] := Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[31:0]);
DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);(* High quadword of destination unchanged *)
CVTPI2PS __m128 _mm_cvtpi32_ps(__m128 a, __m64 b)
See Table 23-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception” in the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.Opcode/
En64-Bit 
NP 0F 2A /r
CVTPI2PS xmm, mm/m64RM Valid Valid Convert two sign ed doubleword integers 
from mm/m64 to two single precision 
floating-point values in xmm.
RM ModRM:reg (r, w) ModRM:r/m (r) N/A N/ACVTPS2DQ—Convert Packed Single Precision Floating-Point  Values to Packed Signed Doubleword Integer ValuesINSTRUCTION SET REFERENCE, A-L
3-284 Vol. 2ACVTPS2DQ—Convert Packed Single Precision Floating-Point Values  to Packed Signed 
Doubleword Integer Values
Converts four, eight or sixteen packed single precision floa ting-point values in the source operand to four, eight or 
sixteen signed doubleword intege rs in the destination operand.
EVEX encoded versions: The source operand is a ZMM regi ster, a 512-bit memory location or a 512-bit vector 
broadcasted from a 32-bit memory location. The destinatio n operand is a ZMM register conditionally updated with 
writemask k1. 
operand is a YMM register. The upper bits (MAXVL-1:256 ) of the corresponding ZMM register destination are 
zeroed.
operand is a XMM register. The upper bits (MAXVL-1:128)  of the corresponding ZMM register destination are 
zeroed.
Mode 
Feature 
66 0F 5B /r
CVTPS2DQ xmm1, xmm2/m128A V/V SSE2 Convert four packed single precision floating-point values

zeroed.
zeroed.
Mode 
Feature 
66 0F 5B /r
CVTPS2DQ xmm1, xmm2/m128A V/V SSE2 Convert four packed single precision floating-point values 
from xmm2/mem to four packed signed doubleword values 
in xmm1.
VEX.128.66.0F.WIG 5B /r
VCVTPS2DQ xmm1, xmm2/m128A V/V AVX Convert four packed single precision floating-point values 
in xmm1.
VEX.256.66.0F.WIG 5B /r
VCVTPS2DQ ymm1, ymm2/m256A V/V AVX Convert eight packed single precision floating-point values 
from ymm2/mem to eight packed signed doubleword values in ymm1.
EVEX.128.66.0F.W0 5B /r
VCVTPS2DQ xmm1 {k1}{z}, 
AVX512FConvert four packed single precision floating-point values 
from xmm2/m128/m32bcst to four packed signed 
doubleword values in xmm1  subject to writemask k1.
EVEX.256.66.0F.W0 5B /r
VCVTPS2DQ ymm1 {k1}{z}, 
AVX512FConvert eight packed single precision floating-point values 
from ymm2/m256/m32bcst to eight packed signed 
doubleword values in ymm1 subject to writemask k1.
EVEX.512.66.0F.W0 5B /r
VCVTPS2DQ zmm1 {k1}{z}, 
zmm2/m512/m32bcst{er}B V/V AVX512F Convert sixteen packed single precision floating-point 
values from zmm2/m512/m32bcst to sixteen packed 
signed doubleword values in zmm1 subject to writemask 
k1.
B Full ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTPS2DQ—Convert Packed Single Precision Floating-Point  Values to Packed Signed Doubleword Integer ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-285Operation
VCVTPS2DQ (Encoded Versions) Wh en SRC Operand is a Register
THEN
ELSE 
FI;
Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])
ELSE 
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] :=  0
VCVTPS2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
FOR j := 0 TO 15
THEN 
THEN
Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
ELSE 
Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])FI;
ELSE 
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0CVTPS2DQ—Convert Packed Single Precision Floating-Point  Values to Packed Signed Doubleword Integer ValuesINSTRUCTION SET REFERENCE, A-L
3-286 Vol. 2AVCVTPS2DQ (VEX.256 Encoded Version)
DEST[31:0] := Convert_Single_Precision _Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])DEST[127:96] := Convert_Single_Precisio n_Floating_Point_To_Integer(SRC[127:96)
DEST[159:128] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])DEST[191:160] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])DEST[223:192] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])DEST[255:224] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])
VCVTPS2DQ (VEX.128 Encoded Version)
DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])DEST[127:96] := Convert_Single_Precisio n_Floating_Point_To_Integer(SRC[127:96])
CVTPS2DQ (128-bit Legacy SSE Version)
VCVTPS2DQ __m512i _mm512_cvtps_epi32( __m512 a);
VCVTPS2DQ __m512i _mm512_mask_cvtps_epi 32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2DQ __m512i _mm512_maskz_cvtps_epi32( __mmask16 k, __m512 a);VCVTPS2DQ __m512i _mm512_cvt_roundps_epi32( __m512 a, int r);VCVTPS2DQ __m512i _mm512_mask_cvt _roundps_epi32( __m512i s, __ mmask16 k, __m512 a, int r);
VCVTPS2DQ __m512i _mm512_maskz_cvt_roundps_epi32( __mmask16 k, __m512 a, int r);VCVTPS2DQ __m256i _mm256_mask_cvtps_epi32( __m256i s, __mmask8 k, __m256 a);VCVTPS2DQ __m256i _mm256_maskz_cvtps_epi32( __mmask8 k, __m256 a);VCVTPS2DQ __m128i _mm_mask_cvtps_epi32 ( __m128i s, __mmask8 k, __m128 a);
VCVTPS2DQ __m128i _mm_maskz_cvtps_epi32( __mmask8 k, __m128 a);VCVTPS2DQ __ m256i _mm256_cvtps_epi32 (__m256 a)CVTPS2DQ __m128i _mm_cvtps_epi32 (__m128 a)
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.CVTPS2PD—Convert Packed Single Precision Floating-Point Values to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-287CVTPS2PD—Convert Packed Single Precision Floa ting-Point Values to Packed Double Precision 
Converts two, four or eight packed single precision floati ng-point values in the source operand (second operand) to 
two, four or eight packed double precision floating-poi nt values in the destination operand (first operand). 
EVEX encoded versions: The source operand is a YMM/XM M/XMM (low 64-bits) register, a 256/128/64-bit memory 
location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a 
ZMM/YMM/XMM register conditionally updated with writemask k1. 
operand is a YMM register. Bits (MAXVL-1:256) of th e corresponding destination ZMM register are zeroed.
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination 
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.Opcode/
Mode 
NP 0F 5A /r
CVTPS2PD xmm1, xmm2/m64A V/V SSE2 Convert two packed single precision floating-point values in 
xmm2/m64 to two packed double precision floating-point 
VEX.128.0F.WIG 5A /r
VCVTPS2PD xmm1, xmm2/m64A V/V AVX Convert two packed single precision floating-point values in 
VEX.256.0F.WIG 5A /r
VCVTPS2PD ymm1, xmm2/m128A V/V AVX Convert four packed single precision floating-point values in 
xmm2/m128 to four packed double precision floating-point values in ymm1.
EVEX.128.0F.W0 5A /r
VCVTPS2PD xmm1 {k1}{z}, 
xmm2/m64/m32bcst B V/V AVX512VL
AVX512FConvert two packed single precision floating-point values in 
xmm2/m64/m32bcst to packed double precision floating-
point values in xmm1 with writemask k1.
EVEX.256.0F.W0 5A /r
VCVTPS2PD ymm1 {k1}{z}, 
xmm2/m128/m32bcst B V/V AVX512VL
AVX512FConvert four packed single precision floating-point values in 
xmm2/m128/m32bcst to packed double precision floating-
point values in ymm1 with writemask k1.
EVEX.512.0F.W0 5A /r
VCVTPS2PD zmm1 {k1}{z}, 
ymm2/m256/m32bcst{sae} B V/V AVX512F Convert eight packed single precision floating-point values in 
ymm2/m256/b32bcst to eight packed double precision 
B Half ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTPS2PD—Convert Packed Single Precision Floating-Point Values to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-288 Vol. 2AOperation
VCVTPS2PD (EVEX Encoded Versions) When SRC Operand is a Register
Convert_Single_Precision_To_Double_Pr ecision_Floating_Point(SRC[k+31:k])
ELSE 
FI
FI;
VCVTPS2PD (EVEX Encoded Versions) When SRC Operand is a Memory Source

ELSE 
FI
FI;
THEN 
THEN
Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE 
FI;
ELSE Figure 3-14.  CVTPS2PD (VEX.256 encoded version)DESTSRC X0 X1 X2 X3
X3 X2 X1 X0CVTPS2PD—Convert Packed Single Precision Floating-Point Values to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-289IF *merging-masking* ; merging-masking
FI
FI;
VCVTPS2PD (VEX.256 Encoded Version)
DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])DEST[191:128] := Convert_Single_Precision_T o_Double_Precision_Flo ating_Point(SRC[95:64])
DEST[255:192] := Convert_Single_Precision_T o_Double_Precision_Floating_Point(SRC[127:96)
VCVTPS2PD (VEX.128 Encoded Version)
DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])DEST[MAXVL-1:128] := 0
CVTPS2PD (128-bit Legacy SSE Version)
DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])DEST[MAXVL-1:128 ] (unmodified)
VCVTPS2PD __m512d _mm512_cvtps_pd( __m256 a);
VCVTPS2PD __m512d _mm512_mask_cvtps_pd( __m512d s, __mmask8 k, __m256 a);VCVTPS2PD __m512d _mm512_maskz_cvtps_pd( __mmask8 k, __m256 a);VCVTPS2PD __m512d _mm512_cvt_roundps_pd( __m256 a, int sae);VCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd( __m512d s, __mmask8 k, __m256 a, int sae);VCVTPS2PD __m512d _mm512_maskz_cvt_roundps _pd( __mmask8 k, __m256 a, int sae);
VCVTPS2PD __m256d _mm256_mask_cvtps_pd( __m256d s, __mmask8 k, __m128 a);VCVTPS2PD __m256d _mm256_maskz_cvtps_pd( __mmask8 k, __m128a);VCVTPS2PD __m128d _mm_mask_cvtps_pd(  __m128d s, __mmask8 k, __m128 a);
VCVTPS2PD __m128d _mm_maskz_cvtps_pd( __mmask8 k, __m128 a);VCVTPS2PD __m256d _mm256_cvtps_pd (__m128 a)CVTPS2PD __m128d _mm_cvtps_pd (__m128 a)
Invalid, Denormal.
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.CVTPS2PI—Convert Packed Single Precision Floa ting-Point Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-L
3-290 Vol. 2ACVTPS2PI—Convert Packed Single Precision Floa ting-Point Values to Packed Dword Integers
Converts two packed single precision floating-point values  in the source operand (second operand) to two packed 
nology register. When the source operand is an XMM regi ster, the two single precision floating-point values are 
contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded 
according to the rounding control bits in the MXCSR regist er. If a converted result is larger than the maximum 
signed doubleword integer, the floating -point invalid exception is raised, and if this exception is masked, the indef-
inite integer value (80000000H) is returned.
CVTPS2PI causes a transition from x87 FPU to MMX techno logy operation (that is, the x87 FPU top-of-stack pointer 
is set to 0 and the x87 FPU tag word is set to all 0s [valid]).  If this instruction is execut ed while an x87 FPU floating-
point exception is pending, the exception is hand led before the CVTPS2PI instruction is executed.
Operation
DEST[31:0] := Convert_Single_Precision _Floating_Point_To_Integer(SRC[31:0]);
DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);
CVTPS2PI __m64 _mm_cvtps_pi32(__m128 a)
See Table 23-5, “Exception Conditions for Legacy SIMD/M MX Instructions with XMM and FP Exception,” in the 
En64-Bit 
NP 0F 2D /r
CVTPS2PI mm, xmm/m64RM Valid Valid Convert two packed single precision floating-
point values from xm m/m64 to two packed 
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTSD2SI—Convert Scalar Double Precision Fl oating-Point Value to Doubleword IntegerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-291CVTSD2SI—Convert Scalar Double Precision Fl oating-Point Value to Doubleword Integer
Converts a double precision floating-point value in the so urce operand (the second operand) to a signed double-
word integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit 
memory location. The destination operand is a general- purpose register. When the source operand is an XMM 
register, the double precision floating-point value is contained in the low quadword of the register.
register. 
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode 
with REX.W/VEX.W/EVEX.W=0), the floati ng-point invalid exception is raised, and if this exception is masked, the 
indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of  signed quadword integer (in 64-bit mode and 
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exce ption is raised, and if this exception is masked, the 
indefinite integer value (80000000_00000000H) is returned.
Legacy SSE instruction: Use of the RE X.W prefix promotes the instruction to produce 64-bit data in 64-bit mode. 
See the summary chart at the beginning of this section for encoding data and limits.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter 
unpredictable behavior across different processor generations.Opcode/
Mode 
Feature 
F2 0F 2D /r
CVTSD2SI r32, xmm1/m64A V/V SSE2 Convert one double precision floating-point value from 
xmm1/m64 to one signed doubleword integer r32.
F2 REX.W 0F 2D /r
CVTSD2SI r64, xmm1/m64A V/N.E. SSE2 Convert one double precision floating-point value from 
xmm1/m64 to one signed quadword integer sign-
extended into r64.
VEX.LIG.F2.0F.W0 2D /r 
1
VCVTSD2SI r32, xmm1/m64
NOTES:
1. Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter unpredictable 
behavior across different processor generations.A V/V AVX Convert one double precision floating-point value from 
VEX.LIG.F2.0F.W1 2D /r 1
VCVTSD2SI r64, xmm1/m64AV / N . E .2AVX Convert one double precision floating-point value from 
EVEX.LLIG.F2.0F.W0 2D /r
VCVTSD2SI r32, xmm1/m64{er}B V/V AVX512F Convert one double precision floating-point value from 
EVEX.LLIG.F2.0F.W1 2D /r
VCVTSD2SI r64, xmm1/m64{er}BV / N . E .2
2. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVX512F Convert one double precision floating-point value from 
xmm1/m64 to one signed quadword integer sign-extended into r64.
B Tuple1 Fixed ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTSD2SI—Convert Scalar Double Precision Floating-Point Value to Doubleword IntegerINSTRUCTION SET REFERENCE, A-L
3-292 Vol. 2AOperation
VCVTSD2SI (EVEX Encoded Version)
IF SRC *is register * AND (EVEX.b = 1) 
THEN
ELSE 
FI;IF 64-Bit Mode and OperandSize = 64
THEN DEST[63:0] := Convert_Double_Precisi on_Floating_Point_To_Integer(SRC[63:0]);
ELSE DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
FI
(V)CVTSD2SI 
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Double_Precision _Floating_Point_To_Integer(SRC[63:0]);
ELSE

THEN
ELSE 
FI
THEN
ELSE
DEST[31:0] := Convert_Double_Precision _Floating_Point_To_Integer(SRC[63:0]);
FI;
VCVTSD2SI int _mm_cvtsd_i32(__m128d);VCVTSD2SI int _mm_cvt_roun dsd_i32(__m128d, int r);
VCVTSD2SI __int64 _mm_cvtsd_i64(__m128d);VCVTSD2SI __int64 _mm_cvt_roundsd_i64(__m128d, int r);CVTSD2SI __int64 _mm_cvtsd_si64(__m128d);CVTSD2SI int _mm_cvtsd_si32(__m128d a)
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.CVTSD2SS—Convert Scalar Double Precision Floating-Point Value to Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-293CVTSD2SS—Convert Scalar Double  Precision Floating-Point Valu e to Scalar Single Precision 
Floating-Point Value
Converts a double precision floating-point value in the “c onvert-from” source operand (the second operand in SSE2 
version, otherwise the third operand) to a single prec ision floating-point value in the destination operand.
When the “convert-from” operand is an XMM register, the do uble precision floating-point value is contained in the 
low quadword of the register. The result is stored in the low doubleword of the de stination operand. When the 
conversion is inexact, the value returned is rounded acco rding to the rounding control bits in the MXCSR register.
128-bit Legacy SSE version: The “convert-from” source operand (the second operand)  is an XMM register or 
memory location. Bits (MAXVL-1:32) of the corresponding  destination register remain unchanged. The destination 
operand is an XMM register. 
VEX.128 and EVEX encoded versions: Th e “convert-from” source operand (the third operand) can be an XMM 
register or a 64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of 
the XMM register destination are copied from the correspon ding bits in the first source operand. Bits (MAXVL-
1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to  the low doubleword element of the destination under the 
writemask.
Software should ensure VCVTSD2SS is encoded with VE X.L=0. Encoding VCVTSD2SS with VEX.L=1 may encounter 
Mode 
Feature 
F2 0F 5A /r
CVTSD2SS xmm1, xmm2/m64A V/V SSE2 Convert one double precision floating-point value in 
xmm2/m64 to one single precision floating-point value in 
xmm1.
VEX.LIG.F2.0F.WIG 5A /r
VCVTSD2SS xmm1,xmm2, xmm3/m64B V/V AVX Convert one double precision floating-point value in 
xmm3/m64 to one single precision floating-point value 
and merge with high bits in xmm2.
EVEX.LLIG.F2.0F.W1 5A /r
VCVTSD2SS xmm1 {k1}{z}, xmm2, xmm3/m64{er}C V/V AVX512F Convert one double precision floating-point value in 
xmm3/m64 to one single precision floating-point value and merge with high bits in xmm2 under writemask k1.
C Tuple1 Scalar ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/ACVTSD2SS—Convert Scalar Double Precision Floating-Point Value to Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-294 Vol. 2AOperation
VCVTSD2SS (EVEX Encoded Version)
IF (SRC2 *is register*) AND (EVEX.b = 1) 
THEN
ELSE 
THEN DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);ELSE 
FI;
VCVTSD2SS (VEX.128 Encoded Version)
DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
CVTSD2SS (128-bit Legacy SSE Version)
DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);(* DEST[MAXVL-1:32] Unmodified *)
VCVTSD2SS __m128 _mm_mask_cvtsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b);
VCVTSD2SS __m128 _mm_maskz_cvtsd_ss( __mmask8 k, __m128 a,__m128d b);
VCVTSD2SS __m128 _mm_cvt_roundsd_ss(__m128 a, __m128d b, int r);VCVTSD2SS __m128 _mm_mask_cvt_r oundsd_ss(__m128 s, __mmask8 k,  __m128 a, __m128d b, int r);
VCVTSD2SS __m128 _mm_maskz_cvt_roundsd_ss( __mmask8 k, __m128 a,__m128d b, int r);
CVTSD2SS __m128_mm_cvtsd_ss(__m128 a, __m128d b)
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”CVTSI2SD—Convert Doubleword Integer to Scal ar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-295CVTSI2SD—Convert Doubleword Integer to Scal ar Double Precision Floating-Point Value
Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from” 
source operand to a double precision floating-point value in  the destination operand. The result is stored in the low 
quadword of the destination operand, and the high quadwo rd left unchanged. When co nversion is inexact, the 
value returned is rounded according to the rounding control bits in the MXCSR register.
The second source operand can be a general-purpose regist er or a 32/64-bit memory location. The first source and 
destination operands are XMM registers. 
128-bit Legacy SSE version: Use of the REX.W prefix prom otes the instruction to 64-bit operands. The “convert-
from” source operand (the second operand) is a general-purpose register or memory location. The destination is 
an XMM register Bits (MAXVL-1:64) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: Th e “convert-from” source operand (the third operand) can be a general-
purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:64) 
of the XMM register destination are copied from the corresp onding bits in the first source operand. Bits (MAXVL-
EVEX.W0 version: attempt to encode this instru ction with EVEX embedded rounding is ignored.
VEX.W1 and EVEX.W1 versions: prom otes the instruction to use 64-bit input value in 64-bit mode.
Software should ensure VCVTSI2SD is encoded with VE X.L=0. Encoding VCVTSI2SD with VEX.L=1 may encounter 
Mode 
Feature 
F2 0F 2A /r
CVTSI2SD xmm1, r32/m32A V/V SSE2 Convert one signed doubleword integer from 
r32/m32 to one double precision floating-point 
value in xmm1.
F2 REX.W 0F 2A /r
CVTSI2SD xmm1, r/m64A V/N.E. SSE2 Convert one signed quadword integer from r/m64 
to one double precision floating-point value in xmm1.
VEX.LIG.F2.0F.W0 2A /r
VCVTSI2SD xmm1, xmm2, r/m32B V/V AVX Convert one signed doubleword integer from 
r/m32 to one double precision floating-point value 
in xmm1.
VEX.LIG.F2.0F.W1 2A /r
VCVTSI2SD xmm1, xmm2, r/m64BV / N . E .
1AVX Convert one signed quadword integer from r/m64 
to one double precision floating-point value in 
xmm1.
EVEX.LLIG.F2.0F.W0 2A /r
VCVTSI2SD xmm1, xmm2, r/m32C V/V AVX512F Convert one signed doubleword integer from 
in xmm1.
EVEX.LLIG.F2.0F.W1 2A /r
VCVTSI2SD xmm1, xmm2, r/m64{er}CV / N . E .1
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVX512F Convert one signed quadword integer from r/m64 
C Tuple1 Scalar ModRM:reg (w) E VEX.vvvv (r) ModRM:r/m (r) N/ACVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-296 Vol. 2AOperation
VCVTSI2SD (EVEX Encoded Version)
THEN
ELSE 
FI;IF 64-Bit Mode And OperandSize = 64THEN
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;DEST[127:64] := SRC1[127:64]
VCVTSI2SD (VEX.128 Encoded Version)
IF 64-Bit Mode And OperandSize = 64THEN

THEN
ELSE 
ELSE
ELSE
CVTSI2SD 
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
FI;DEST[MAXVL-1:64] (Unmodified)
VCVTSI2SD __m128d _mm_cvti32_sd(__m128d s, int a);VCVTSI2SD __m128d _mm_cvti64_sd(__m128d s, __int64 a);VCVTSI2SD __m128d _mm_cvt_roundi64_ sd(__m128d s, __int 64 a, int r);
CVTSI2SD __m128d _mm_cvtsi64_ sd(__m128d s, __int64 a);
CVTSI2SD __m128d_mm_cvtsi32_sd(__m128d a, int b)
VEX-encoded instructions, see Table 2-20, “Type 3 Class Ex ception Conditions,” if W1; else see Table 2-22, “Type 
5 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions,” if W1; else see Table 2-59, 
“Type E10NF Class Exception Conditions.”CVTSI2SS—Convert Doubleword Integer to Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-297CVTSI2SS—Convert Doubleword Integer to Scal ar Single Precision Floating-Point Value
source operand to a single precision floating-point value in the destination operand (first operand). The “convert-
from” source operand can be a general-purpose register or a memory location. The destination operand is an XMM 
register. The result is stored in the low doubleword of  the destination operand, an d the upper three doublewords 
are left unchanged. When a conversion is inexact, the va lue returned is rounded according to the rounding control 
bits in the MXCSR register or the embedded rounding control bits.
128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input 
value. The “convert-from” source operand (the second operand) is a general-purpose register or memory location. Bits (MAXVL-1:32) of the corresponding destination register remain unchanged.
purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32) 
of the XMM register destination are copied from correspondi ng bits in the first source operand. Bits (MAXVL-1:128) 
of the destination register are zeroed.
Software should ensure VCVTSI2SS is encoded with VE X.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter 
Mode 
Feature 
F3 0F 2A /r
CVTSI2SS xmm1, r/m32A V/V SSE Convert one signed do ubleword integer from r/m32 
to one single precision floating-point value in xmm1.
F3 REX.W 0F 2A /r
CVTSI2SS xmm1, r/m64A V/N.E. SSE Convert one signed quadword integer from r/m64 to 
one single precision floating-point value in xmm1.
VEX.LIG.F3.0F.W0 2A /r
VCVTSI2SS xmm1, xmm2, r/m32B V/V AVX Convert one signed do ubleword integer from r/m32 
VEX.LIG.F3.0F.W1 2A /r
VCVTSI2SS xmm1, xmm2, r/m64BV / N . E .
1AVX Convert one signed quadword integer from r/m64 to 
EVEX.LLIG.F3.0F.W0 2A /r
VCVTSI2SS xmm1, xmm2, r/m32{er}C V/V AVX512F Convert one signed doubleword integer from r/m32 
EVEX.LLIG.F3.0F.W1 2A /r
VCVTSI2SS xmm1, xmm2, r/m64{er}CV / N . E .1
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVX512F Convert one signed quadword integer from r/m64 to 
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ACVTSI2SS—Convert Doubleword Integer to Scal ar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-298 Vol. 2AOperation
VCVTSI2SS (EVEX Encoded Version)
THEN
ELSE 
DEST[31:0] := Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[63:0]);
ELSE
VCVTSI2SS (VEX.128 Encoded Version)
ELSE
CVTSI2SS (128-bit Legacy SSE Version)
ELSE
DEST[31:0] :=Convert_Integer_To_Singl e_Precision_Floating_Point(SRC[31:0]);
FI;DEST[MAXVL-1:32] (Unmodified)
VCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a);VCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r);VCVTSI2SS __m128 _mm_cvti64_ ss(__m128 s, __int64 a);
VCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r);CVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a);CVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”CVTSS2SD—Convert Scalar Single Precision Floating-Point Value to Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-299CVTSS2SD—Convert Scalar Single Precision Floa ting-Point Value to Scalar Double Precision 
Converts a single precision floating-point value in the “convert-from” source operand to a double precision floating-
point value in the destination operand. When the “convert -from” source operand is an XMM register, the single 
precision floating-point value is contained in the low doub leword of the register. The re sult is stored in the low 
memory location. Bits (MAXVL-1:64) of the corresponding  destination register remain unchanged. The destination 
register or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of 
Software should ensure VCVTSS2SD is encoded with VE X.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter 
Operation
VCVTSS2SD (EVEX Encoded Version)
IF k1[0] or *no writemask*
THEN DEST[63:0] := Convert_Single_Precision_T o_Double_Precision_Floating_Point(SRC2[31:0]);
ELSE 
THEN DEST[63:0] = 0
FI;
FI;DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0Opcode/
Mode 
Feature 
F3 0F 5A /r
CVTSS2SD xmm1, xmm2/m32A V/V SSE2 Convert one single precision floating-point value in 
xmm2/m32 to one double precision floating-point value in 
xmm1.
VEX.LIG.F3.0F.WIG 5A /r
VCVTSS2SD xmm1, xmm2, 
xmm3/m32B V/V AVX Convert one single precision floating-point value in 
xmm3/m32 to one double precision floating-point value 
and merge with high bits of xmm2.
EVEX.LLIG.F3.0F.W0 5A /r
VCVTSS2SD xmm1 {k1}{z}, xmm2, 
xmm3/m32{sae}C V/V AVX512F Convert one single precision floating-point value in 
xmm3/m32 to one double precision floating-point value and merge with high bits of xmm2 under writemask k1.
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ACVTSS2SD—Convert Scalar Single Precision Floating-Point Value to Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-300 Vol. 2AVCVTSS2SD (VEX.128 Encoded Version)

xmm1.
DEST[63:0] := Convert_Single_Precision_To_ Double_Precision_Float ing_Point(SRC2[31:0])
DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
CVTSS2SD (128-bit Legacy SSE Version)
DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);DEST[MAXVL-1:64] (Unmodified)
VCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);VCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128 d s, __mmask8 m, __m128d a,__m128 b, int r);
VCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__m mask8 k, __m128d a, __m128 a, int r);
VCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);
VCVTSS2SD __m128d _mm_maskz_cvtss_sd (__mmask8 m, __m128d a,__m128 b);
CVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword IntegerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-301CVTSS2SI—Convert Scalar Single Precision Fl oating-Point Value to Doubleword Integer
Converts a single precision floating-point value in the sour ce operand (the second operand) to a signed doubleword 
integer (or signed quadword integer if operand size is 64  bits) in the destination operand (the first operand). The 
source operand can be an XMM register or a memory location. The destination operand is a general-purpose 
register. When the source operand is an XMM register, the single precision floating-point value is contained in the 
low doubleword of the register.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data. 
VEX.W1 and EVEX.W1 versions: prom otes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCVTSS2SI is encoded with VE X.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter 
Mode 
Feature 
F3 0F 2D /r
CVTSS2SI r32, xmm1/m32A V/V SSE Convert one single precision floating-point value from 
xmm1/m32 to one signed do ubleword integer in r32.
F3 REX.W 0F 2D /r
CVTSS2SI r64, xmm1/m32A V/N.E. SSE Convert one single precision floating-point value from 
xmm1/m32 to one signed quadword integer in r64.
VEX.LIG.F3.0F.W0 2D /r 
1
VCVTSS2SI r32, xmm1/m32
NOTES:
1. Software should ensure VCVTSS2SI is encoded wi th VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may 
encounter unpredictable behavior across different processor generations.A V/V AVX Convert one single precision floating-point value from 
VEX.LIG.F3.0F.W1 2D /r 1
VCVTSS2SI r64, xmm1/m32AV / N . E .2AVX Convert one single precision floating-point value from 
EVEX.LLIG.F3.0F.W0 2D /r
VCVTSS2SI r32, xmm1/m32{er}B V/V AVX512F Convert one single precision floating-point value from 
EVEX.LLIG.F3.0F.W1 2D /r
VCVTSS2SI r64, xmm1/m32{er}BV / N . E .2
2. VEX.W1/EVEX.W1 in non-64 bit is ignored; the in structions behaves as if the W0 version is used.AVX512F Convert one single precision floating-point value from 
BT u p l e 1  F i x e dM o d R M : r e g  (w) ModRM:r/m (r) N/A N/ACVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword IntegerINSTRUCTION SET REFERENCE, A-L
3-302 Vol. 2AOperation
VCVTSS2SI (EVEX Encoded Version)
IF (SRC *is register*) AND (EVEX.b = 1) 
THEN
ELSE 
FI;IF 64-bit Mode and OperandSize = 64THEN
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;
(V)CVTSS2SI (Legacy and VEX.128 Encoded Version) 
IF 64-bit Mode and OperandSize = 64THEN
ELSE
FI;
VCVTSS2SI int _mm_cvtss_i32( __m128 a);VCVTSS2SI int _mm_cvt_round ss_i32( __m128 a, int r);
VCVTSS2SI __int64 _mm_cv tss_i64( __m128 a);
VCVTSS2SI __int64 _mm_cvt_roun dss_i64( __m128 a, int r);
VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions,” additionally:
#UD If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”CVTTPD2DQ—Convert with Truncation Packed Double Precisio n Floating-Point Values to Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-303CVTTPD2DQ—Convert with Trunca tion Packed Double Precision Floating-Point Values to 
Packed Doubleword Integers
Converts two, four or eight packed do uble precision floating-point values in  the source operand (second operand) 
to two, four or eight packed signed doubleword in tegers in the destination operand (first operand). 
When a conversion is inexact, a truncated (round toward zero ) value is returned. If a converted result is larger than 
the maximum signed doubleword integer, the floating-point  invalid exception is raised, and if this exception is 
masked, the indefinite integer value (80000000H) is returned.
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a 
YMM/XMM/XMM (low 64 bits) register conditionally update d with writemask k1. The upper bits (MAXVL-1:256) of 
the corresponding destination are zeroed.
zeroed.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Opcode/
Mode 
Feature 
66 0F E6 /r
CVTTPD2DQ xmm1, xmm2/m128A V/V SSE2 Convert two packed double precision floating-point 
values in xmm2/mem to two signed doubleword integers 
in xmm1 using truncation.
VEX.128.66.0F.WIG E6 /r
VCVTTPD2DQ xmm1, xmm2/m128A V/V AVX Convert two packed double precision floating-point 
VEX.256.66.0F.WIG E6 /r
VCVTTPD2DQ xmm1, ymm2/m256A V/V AVX Convert four packed double precision floating-point 
values in ymm2/mem to four signed doubleword integers in xmm1 using truncation.
EVEX.128.66.0F.W1 E6 /r
VCVTTPD2DQ xmm1 {k1}{z}, 
xmm2/m128/m64bcstBV / V A V X 5 1 2 V L
doubleword integers in xmm1 using truncation subject to 
EVEX.256.66.0F.W1 E6 /r
VCVTTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcstBV / V A V X 5 1 2 V L
values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 using truncation subject to 
EVEX.512.66.0F.W1 E6 /r
VCVTTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst{sae}B V/V AVX512F Convert eight packed double precision floating-point 
values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 using truncation subject to 

B Full ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTTPD2DQ—Convert with Truncation Packed Double Precisio n Floating-Point Values to Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A-L
3-304 Vol. 2AOperation
VCVTTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Register
Convert_Double_Precision_Floating_Poi nt_To_Integer_Truncate(SRC[k+63:k])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0Figure 3-15.  VCVTTPD2DQ (VEX.256 encoded version)DESTSRC
0CVTTPD2DQ—Convert with Truncation Packed Double Precisio n Floating-Point Values to Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-305VCVTTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Double_Precision_Floating_Poi nt_To_Integer_Truncate(SRC[63:0])
ELSE 
Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])FI;
ELSE 
FI
FI;
VCVTTPD2DQ (VEX.256 Encoded Version)
DEST[31:0] := Convert_Double _Precision_Flo ating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] := Conver t_Double_Precision_Floating_Point_ To_Integer_Truncate(SRC[127:64])
DEST[95:64] := Convert_ Double_Precision_Floating_Point_To _Integer_Truncate(SRC[191:128])
DEST[127:96] := Convert_Double_Precision_Flo ating_Point_To_Integer_Truncate(SRC[255:192)
VCVTTPD2DQ (VEX.128 Encoded Version)
CVTTPD2DQ (128-bit Legacy SSE Version)
DEST[127:64] := 0DEST[MAXVL-1:128 ] (unmodified)CVTTPD2DQ—Convert with Truncation Packed Double Precisio n Floating-Point Values to Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A-L
3-306 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2DQ __m256i _mm512_cvttpd_epi32( __m512d a);
VCVTTPD2DQ __m256i _mm512_mask_cvttpd_epi32( __m256i s, __mmask8 k, __m512d a);VCVTTPD2DQ __m256i _mm512_maskz_cvttpd_epi32( __mmask8 k, __m512d a);VCVTTPD2DQ __m256i _mm512_cvtt_roundpd_epi32( __m512d a, int sae);VCVTTPD2DQ __m256i _mm512_mask_cvtt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int sae);VCVTTPD2DQ __m256i _mm512_maskz_cvtt_roundpd_epi32( __mmask8 k, __m512d a, int sae);VCVTTPD2DQ __m128i _mm256_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m256d a);VCVTTPD2DQ __m128i _mm256_maskz_cvttpd_epi32( __mmask8 k, __m256d a);VCVTTPD2DQ __m128i _mm_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m128d a);VCVTTPD2DQ __m128i _mm_maskz_cvtt pd_epi32( __mmask8 k, __m128d a);
VCVTTPD2DQ __m128i _mm256_cvttpd_epi32 (__m256d src);CVTTPD2DQ __m128i _mm_cvttpd_epi32 (__m128d src);
Additionally:#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.CVTTPD2PI—Convert With Truncation Packed Double Precis ion Floating-Point Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-307CVTTPD2PI—Convert With Truncati on Packed Double Precision Floa ting-Point Valu es to Packed 
Dword Integers
signed doubleword integers in the dest ination operand (first operand). The source operand can be an XMM register 
or a 128-bit memory location. The destination operand is an MMX technology register. 
When a conversion is inexact, a truncated (round toward ze ro) result is returned. If a converted result is larger 
than the maximum signed doubleword integer, the floating-poi nt invalid exception is raised, and if this exception is 
floating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.
Operation
DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);
DEST[63:32] := Convert_ Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[127:64]);
CVTTPD1PI __m64 _mm_cvttpd_pi32(__m128d a)
Other Mode Exceptions
ment,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.Opcode/
En64-Bit 
66 0F 2C /r
CVTTPD2PI mm, xmm/m128RM Valid Valid Convert two packer double precision floating-
point values from xmm/m128 to two packed signed doubleword integers in mm using 
truncation.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTTPS2DQ—Convert With Truncation Packed Single Precision Floa ting-Point Values to Packed Signed Doubleword Integer ValuesINSTRUCTION SET REFERENCE, A-L
3-308 Vol. 2ACVTTPS2DQ—Convert With Truncatio n Packed Single Precision Floa ting-Point Values to Packed 
Signed Doubleword Integer Values
EVEX encoded versions: The source operand is a ZMM/Y MM/XMM register, a 512/256/128-bit memory location or 
a 512/256/128-bit vector broadcasted from a 32-bit  memory location. The destination operand is a 
zeroed.
zeroed.
Mode 
F3 0F 5B /r
CVTTPS2DQ xmm1, xmm2/m128A V/V SSE2 Convert four packed single precision floating-point 
values from xmm2/mem to  four packed signed 
doubleword values in xmm1 using truncation.
VEX.128.F3.0F.WIG 5B /r
VCVTTPS2DQ xmm1, xmm2/m128A V/V AVX Convert four packed single precision floating-point 
VEX.256.F3.0F.WIG 5B /r
VCVTTPS2DQ ymm1, ymm2/m256A V/V AVX Convert eight packed single precision floating-point 
values from ymm2/mem to eight packed signed doubleword values in ymm1 using truncation.
EVEX.128.F3.0F.W0 5B /r
VCVTTPS2DQ xmm1 {k1}{z}, 
AVX512FConvert four packed single precision floating-point 
values from xmm2/m128/m32bcst to four packed 
signed doubleword values in xmm1 using truncation 
EVEX.256.F3.0F.W0 5B /r
VCVTTPS2DQ ymm1 {k1}{z}, ymm2/m256/m32bcstB V/V AVX512VL
AVX512FConvert eight packed single precision floating-point 
values from ymm2/m256/m32bcst to eight packed signed doubleword values in ymm1 using truncation 
EVEX.512.F3.0F.W0 5B /r

VCVTTPS2DQ zmm1 {k1}{z}, zmm2/m512/m32bcst {sae}B V/V AVX512F Convert sixteen packed single precision floating-point 
values from zmm2/m512/m32bcst to sixteen packed signed doubleword values in zmm1 using truncation 
B Full ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTTPS2DQ—Convert With Truncation Packed Single Precision Floati ng-Point Values to Packed Signed Doubleword Integer ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-309Operation
VCVTTPS2DQ (EVEX Encoded Versions ) When SRC Operand is a Register
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])
ELSE 
FI
FI;
ENDFOR
DEST[MAXVL-1:VL]  := 0
VCVTTPS2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
ELSE 
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])FI;
ELSE 
FI
FI;
ENDFOR
VCVTTPS2DQ (VEX.256 Encoded Version)
DEST[31:0] := Convert_Single_Precision_Flo ating_Point_To_Integer _Truncate(SRC[31:0])
DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])DEST[127:96] := Convert_Single_Precision_F loating_Point_To_Integer_Truncate(SRC[127:96)
DEST[159:128] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[159:128])DEST[191:160] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[191:160])DEST[223:192] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[223:192])DEST[255:224] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[255:224])CVTTPS2DQ—Convert With Truncation Packed Single Precision Floa ting-Point Values to Packed Signed Doubleword Integer ValuesINSTRUCTION SET REFERENCE, A-L
3-310 Vol. 2AVCVTTPS2DQ (VEX.128 Encoded Version)
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])DEST[127:96] := Convert_Single_Precision_Floa ting_Point_To_Integer_Truncate(SRC[127:96])
CVTTPS2DQ (128-bit Legacy SSE Version)
VCVTTPS2DQ __m512i _mm512_cvttps_epi32( __m512 a);
VCVTTPS2DQ __m512i _mm512_mask_cvttps_epi 32( __m512i s, __mmask16 k, __m512 a);
VCVTTPS2DQ __m512i _mm512_maskz_cvt tps_epi32( __mmask16 k, __m512 a);
VCVTTPS2DQ __m512i _mm512_cvtt_ro undps_epi32( __m512 a, int sae);
VCVTTPS2DQ __m512i _mm512_mask_cvtt_roundps_epi 32( __m512i s, __mmask16 k,  __m512 a, int sae);
VCVTTPS2DQ __m512i _mm512_mas kz_cvtt_roundps_epi32( __mmask16 k, __m512 a, int sae);
VCVTTPS2DQ __m256i _mm256_mask_cvttps_epi 32( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2DQ __m256i _mm256_maskz_cvt tps_epi32( __mmask8 k, __m256 a);
VCVTTPS2DQ __m128i _mm_mask_cvttps_epi 32( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2DQ __m128i _mm_maskz_cvttp s_epi32( __mmask8 k, __m128 a);
VCVTTPS2DQ __m256i _mm256_cvttps_epi32 (__m256 a)CVTTPS2DQ __m128i _mm_cvttps_epi32 (__m128 a)
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”Additionally:
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.CVTTPS2PI—Convert With Truncation Packed Single Precis ion Floating-Point Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-311CVTTPS2PI—Convert With Truncation Packed Single Precision Floating-Point Values to Packed 
or a 64-bit memory location. The destination operand is an  MMX technology register. Wh en the source operand is 
an XMM register, the two single precision floating-point va lues are contained in the low quadword of the register.
floating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.
Operation
DEST[31:0] := Convert_Single_Precision_Flo ating_Point_To_Integer _Truncate(SRC[31:0]);
DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);
CVTTPS2PI __m64 _mm_cvttps_pi32(__m128 a)
En64-Bit 
NP 0F 2C /r
CVTTPS2PI mm, xmm/m64RM Valid Valid Convert two single precision floating-point 
values from xmm/m64 to two signed doubleword signed integers in mm using 
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTTSD2SI—Convert With Truncation Scalar Double Pr ecision Floating-Point Value to Signed IntegerINSTRUCTION SET REFERENCE, A-L
3-312 Vol. 2ACVTTSD2SI—Convert With Truncati on Scalar Double Precision Floating-Point Value to Signed 
Integer
Converts a double precision floating-point value in the source operand (the second operand) to a signed double-
word integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general 
purpose register. When the source operand is an XMM re gister, the double precision floating-point value is 
contained in the low quadword of the register. 
register. 
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of  signed quadword inte ger (in 64-bit mode and 
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See 
VEX.W1 and EVEX.W1 versions: promotes the instru ction to produce 64-bit data in 64-bit mode.Opcode/
Mode 
Feature 
F2 0F 2C /r
CVTTSD2SI r32, xmm1/m64A V/V SSE2 Convert one double precision floating-point value from 
xmm1/m64 to one signed doubleword integer in r32 
using truncation.
F2 REX.W 0F 2C /r
CVTTSD2SI r64, xmm1/m64A V/N.E. SSE2 Convert one double precision floating-point value from 
xmm1/m64 to one signed quadword integer in r64 
VEX.LIG.F2.0F.W0 2C /r 
1
VCVTTSD2SI r32, xmm1/m64

Mode 
Feature 
F2 0F 2C /r
1
NOTES:
1. Software should ensure  VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may encounter unpredictable 
xmm1/m64 to one signed doubleword integer in r32 using truncation.
VEX.LIG.F2.0F.W1 2C /r 
1
VCVTTSD2SI r64, xmm1/m64BV / N . E .2AVX Convert one double precision floating-point value from 
EVEX.LLIG.F2.0F.W0 2C /r
VCVTTSD2SI r32, xmm1/m64{sae}B V/V AVX512F Convert one double precision floating-point value from 
EVEX.LLIG.F2.0F.W1 2C /r
VCVTTSD2SI r64, xmm1/m64{sae}BV / N . E .2
2. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVX512F Convert one double precision floating-point value from 
B Tuple1 Fixed ModRM:reg (w) ModRM:r/m (r) N/A N/ACVTTSD2SI—Convert With Truncation Scalar Double Pr ecision Floating-Point Value to Signed IntegerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-313Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTTSD2SI is encoded with  VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may 
encounter unpredictable behavior ac ross different processor generations.
Operation
(V)CVTTSD2SI (All Versions)
IF 64-Bit Mode and OperandSize = 64THEN
DEST[63:0] := Convert_Double _Precision_Floating_ Point_To_Integer_Truncate(SRC[63:0]);
ELSE
DEST[31:0] := Convert_Double _Precision_Floating_ Point_To_Integer_Truncate(SRC[63:0]);
FI;
VCVTTSD2SI int _mm_cvttsd_i32( __m128d a);VCVTTSD2SI int _mm_cvtt_round sd_i32( __m128d a, int sae);
VCVTTSD2SI __int64 _mm_cvttsd_i64( __m128d a);VCVTTSD2SI __int64 _mm_cvtt_roundsd_i64( __m128d a, int sae);CVTTSD2SI int _mm_cvttsd_si32( __m128d a);CVTTSD2SI __int64 _mm_cvttsd_si64( __m128d a);
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”CVTTSS2SI—Convert With Truncation Scalar Single Precision Floating-Point Value to IntegerINSTRUCTION SET REFERENCE, A-L
3-314 Vol. 2ACVTTSS2SI—Convert With Truncation Scalar Single  Precision Floating-Point Value to Integer
integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The 
source operand can be an XMM register or a 32-bit memo ry location. The destination operand is a general purpose 
low doubleword of the register. 
When a conversion is inexact, a truncated (round toward zero ) result is returned. If a converted result is larger than 
the maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked, 
the indefinite integer value (80000000H or 80000000_00000 000H if operand size is 64 bits) is returned.
VEX.W1 and EVEX.W1 versions: promotes the instru ction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and mu st be 1111b, otherwise instructions will #UD.
Software should ensure VCVTTSS2SI is encoded with  VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may 
encounter unpredictable behavior acro ss different processor generations.Opcode/
Mode 
Feature 
F3 0F 2C /r
CVTTSS2SI r32, xmm1/m32A V/V SSE Convert one single precision floating-point value from 
xmm1/m32 to one signed do ubleword integer in r32 
F3 REX.W 0F 2C /r
CVTTSS2SI r64, xmm1/m32A V/N.E. SSE Convert one single precision floating-point value from 
xmm1/m32 to one signed quadword integer in r64 
VEX.LIG.F3.0F.W0 2C /r 1
VCVTTSS2SI r32, xmm1/m32
NOTES:
1. Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may encounter unpredictable 
behavior across different processor generations.A V/V AVX Convert one single precision floating-point value from 
VEX.LIG.F3.0F.W1 2C /r 1
VCVTTSS2SI r64, xmm1/m32AV / N . E .2AVX Convert one single precision floating-point value from 
EVEX.LLIG.F3.0F.W0 2C /r
VCVTTSS2SI r32, xmm1/m32{sae}B V/V AVX512F Convert one single precision floating-point value from 
EVEX.LLIG.F3.0F.W1 2C /r
VCVTTSS2SI r64, xmm1/m32{sae}BV / N . E .2
2. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVX512F Convert one single precision floating-point value from 
BT u p l e 1  F i x e d M o d R M : r e g  (w) ModRM:r/m (r) N/A N/ACVTTSS2SI—Convert With Truncation Scalar Single Precision Floating-Point Value to IntegerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-315Operation
(V)CVTTSS2SI (All Versions)
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
FI;
VCVTTSS2SI int _mm_cvttss_i32( __m128 a);VCVTTSS2SI int _mm_cvtt_round ss_i32( __m128 a, int sae);
VCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);VCVTTSS2SI __int64 _mm_cvtt_rou ndss_i64( __m128 a, int sae);
CVTTSS2SI int _mm_cvttss_si32( __m128 a);
CVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);
See Table 2-20, “Type 3 Class Exce ption Conditions,” additionally:
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to QuadwordINSTRUCTION SET REFERENCE, A-L
3-316 Vol. 2ACWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword
Doubles the size of the operand in register AX, EAX, or  RAX (depending on the oper and size) by means of sign 
extension and stores the result in registers DX:AX, ED X:EAX, or RDX:RAX, respectively. The CWD instruction 
copies the sign (bit 15) of the value in the AX register in to every bit position in the DX register. The CDQ instruction 
copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruc-
tion (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position 
in the RDX register.
The CWD instruction can be used to produce a doubleword  dividend from a word before word division. The CDQ 
instruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO 
instruction can be used to produce a double quadword dividend from a quadword before a quadword division.
The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the 
operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers 
may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these 
mnemonics as synonyms (CWD/CDQ) and use the current se tting of the operand-size attribute to determine the 
size of values to be converted, regardless of the mnemonic used.
In 64-bit mode, use of the REX.W prefix promotes oper ation to 64 bits. The CQO mnemonics reference the same 
opcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits.
Operation
IF OperandSize = 16 (* CWD instruction *)
THEN 
DX := SignExtend(AX);
ELSE IF OperandSize = 32 (* CDQ instruction *)
EDX := SignExtend(EAX); FI;
ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)
RDX := SignExtend(RAX); FI;
FI;
None.
En64-Bit 
99 CWD ZO Valid Valid DX:AX := sign-extend of AX.

Operation
THEN 
FI;
None.
En64-Bit 
99 CDQ ZO Valid Valid EDX:EAX := sign-extend of EAX.REX.W + 99 CQO ZO Valid N.E. RDX:RAX:= sign-extend of RAX.
ZO N/A N/A N/A N/ADAA—Decimal Adjust AL After AdditionINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-317DAA—Decimal Adjust AL After Addition
Adjusts the sum of two packed BCD values to create a pack ed BCD result. The AL register is the implied source and 
destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addi-
tion) two 2-digit, packed BCD values and stores a byte re sult in the AL register. The DAA instruction then adjusts 
the contents of the AL register to contain the correct 2-di git, packed BCD result. If a decimal carry is detected, the 
CF and AF flags are set accordingly.
This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
THEN
#UD;
ELSE
old_AL := AL;old_CF := CF;CF := 0;IF (((AL AND 0FH) 
> 9) or AF = 1)
 THEN
 AL := AL + 6;
 CF := old_CF or (Carry from AL := AL + 6);
 AF := 1;
  ELSE  AF := 0;
FI;IF ((old_AL 
> 99H) or (old_CF = 1))
 THEN
 AL := AL  + 60H;
  CF := 1;
ELSE
 CF := 0;
FI;
FI;
Example
ADD AL, BL Before: AL =79H BL =35H EFLAGS(OSZAPC) =XXXXXX
After: AL =AEH BL =35H EFLAGS(0SZAPC) =110000
DAA Before: AL =AEH BL =35H EFLAGS(OSZAPC) =110000
After: AL =14H BL =35H EFLAGS(0SZAPC) =X00111
DAA Before: AL =2EH BL =35H EFLAGS(OSZAPC) =110000
After: AL =34H BL =35H EFLAGS(0SZAPC) =X00101Opcode Instruction Op/ 
En64-Bit 
27 DAA ZO Invalid Valid Decimal adjust AL after addition.
3-318 Vol. 2AFlags Affected
The CF and AF flags are set if the adjustment of the value re sults in a decimal carry in either digit of the result (see 
the “Operation” section above). The SF, ZF, and PF flags ar e set according to the result. The OF flag is undefined.
#UD If in 64-bit mode.DAS—Decimal Adjust AL After SubtractionINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-319DAS—Decimal Adjust AL After Subtraction
Adjusts the result of the subtraction of two packed BCD valu es to create a packed BCD result. The AL register is the 
implied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that 
subtracts (binary subtraction) one 2-digit, packed BCD va lue from another and stores a byte result in the AL 
register. The DAS instruction then adjusts the contents of th e AL register to contain the correct 2-digit, packed BCD 
result. If a decimal borrow is detected, the CF and AF flags are set accordingly.
Operation
THEN
#UD;
ELSE
old_AL := AL;old_CF := CF;CF := 0;IF (((AL AND 0FH) > 9) or AF 
= 1)
 THEN AL := AL
 - 6;
CF := old_CF or (Borrow from AL := AL − 6);
AF := 1;
ELSE
AF := 0;
FI;IF ((old_AL > 99H) or (old_CF 
= 1))
 THEN
AL := AL − 60H;
CF := 1;
FI;
FI;
Example
SUB AL, BL Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX
After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111
DAA Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111
After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111
The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result 
(see the “Operation” section above). The SF, ZF, and PF flag s are set according to the result. The OF flag is unde-
fined.Opcode Instruction Op/ 
En64-Bit 
2F DAS ZO Invalid Valid Decimal adjust AL after subtraction.
ZO N/A N/A N/A N/ADAS—Decimal Adjust AL After SubtractionINSTRUCTION SET REFERENCE, A-L
3-320 Vol. 2AProtected Mode Exceptions
#UD If in 64-bit mode.DEC—Decrement by 1INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-321DEC—Decrement by 1
Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be 
a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. 
(To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of 
1.)
In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes). 
Otherwise, the instruction’s 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to 
additional registers (R8-R15). Use of the RE X.W prefix promotes operation to 64 bits. 
Operation
DEST := DEST – 1;
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
#GP(0) If the destination operand is located in a non-writable segment.
#GP If a memory operand effective address is ou tside the CS, DS, ES, FS, or GS segment limit.Opcode Instruction Op/ 
En64-Bit 
FE /1 DEC r/m8 MV a l i d V a l i d D e c r e m e n t  r/m8  by 1.
REX + FE /1 DEC r/m8*MV a l i d N . E . D e c r e m e n t  r/m8  by 1.
FF /1 DEC r/m16 MV a l i d V a l i d D e c r e m e n t  r/m16  by 1.
FF /1 DEC r/m32 MV a l i d V a l i d D e c r e m e n t  r/m32  by 1.
REX.W + FF /1 DEC r/m64 MV a l i d N . E . D e c r e m e n t  r/m64  by 1.
48+rw DEC r16 ON . E . V a l i d D e c r e m e n t  r16 by 1.
48+rd DEC r32 ON . E . V a l i d D e c r e m e n t  r32 by 1.
NOTES:
M ModRM:r/m (r, w) N/A N/A N/A
O opcode + rd (r, w) N/A N/A N/ADEC—Decrement by 1INSTRUCTION SET REFERENCE, A-L
3-322 Vol. 2A#SS If a memory operand effective address is outside the SS segment limit.
#UD If the LOCK prefix is used but the destination is not a memory operand.DIV—Unsigned DivideINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-323DIV—Unsigned Divide
Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand 
(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX: RAX registers. The source operand can 
be a general-purpose register or a memory location. The action of this instruction depends on the operand size 
(dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.
Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magni-
tude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.

tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is 
applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in 
RAX, the remainder in RDX. 
See the summary chart at the beginning of this se ction for encoding data and limits. See Table 3-15.Opcode Instruction Op/ 
En64-Bit 
F6 /6 DIV r/m8 M Valid Valid Unsigned divide AX by r/m8, with result 
stored in AL  := Quotient, AH  := Remainder.
REX + F6 /6 DIV r/m81
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.M Valid N.E. Unsigned divide AX by r/m8, with result 
F7 /6 DIV r/m16 M Valid Valid Unsigned divide DX:AX by r/m16, with result 
stored in AX  := Quotient, DX  := Remainder.
F7 /6 DIV r/m32 M Valid Valid Unsigned divide EDX:EAX by r/m32, with 
result stored in EAX  := Quotient, EDX  := 
Remainder.
REX.W + F7 /6 DIV r/m64 M Valid N.E. Unsig ned divide RDX:RAX by r/m64, with 
result stored in RAX  := Quotient, RDX  := 
Table 3-15.  DIV Action 
Operand Size Dividend Di visor Quotient RemainderMaximum 
Quotient
Word/byte AX r/m8 AL AH 255
Doubleword/word DX:AX r/m16 AX DX 65,535Quadword/doubleword EDX:EAX r/m32 EAX EDX 2
32 − 1
Doublequadword/
quadwordRDX:RAX r/m64 RAX RDX 264 − 1DIV—Unsigned DivideINSTRUCTION SET REFERENCE, A-L
3-324 Vol. 2AOperation
IF SRC  = 0
THEN #DE; FI; (* Divide Error *) 
IF OperandSize = 8 (* Word/Byte Operation *)
THEN
temp := AX / SRC;IF temp > FFH
THEN #DE; (* Divide error *) ELSE
AL := temp;AH := AX MOD SRC;
FI;
ELSE IF OperandSize 
= 16 (* Doubleword/word operation *)
THEN
temp := DX:AX / SRC;
IF temp > FFFFH
THEN #DE; (* Divide error *) 
ELSE
AX := temp;DX := DX:AX MOD SRC;
FI;
FI;
ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)
THEN
temp := EDX:EAX / SRC;IF temp > FFFFFFFFH
ELSE
EAX := temp;EDX := EDX:EAX MOD SRC;
FI;
FI;
ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)
THEN
temp := RDX:RAX / SRC;IF temp > FFFFFFFFFFFFFFFFH
ELSE
RAX := temp;RDX := RDX:RAX MOD SRC;
FI;
FI;
FI;
The CF, OF, SF, ZF, AF, and PF flags are undefined.DIV—Unsigned DivideINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-325Protected Mode Exceptions
#DE If the source operand (divisor) is 0
If the quotient is too large for the designated register.
#DE If the source operand (divisor) is 0.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#GP(0) If the memory address is in a non-canonical form.#DE If the source operand (divisor) is 0
#UD If the LOCK prefix is used.DIVPD—Divide Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-326 Vol. 2ADIVPD—Divide Packed Double Precision Floating-Point Values
Performs a SIMD divide of the double precision floating-p oint values in the first source operand by the floating-
point values in the second source oper and (the third operand). Results are written to the destination operand (the 
first operand).
EVEX encoded versions: The first source operand (the se cond operand) is a ZMM/YMM/XMM register. The second 
broadcasted from a 64-bit memory location. The destinat ion operand is a ZMM/YMM/XMM register conditionally 
updated with writemask k1.
VEX.256 encoded version: The first source operand (the second operand) is a YMM register. The second source 
operand can be a YMM register or a 256-bit memory locati on. The destination operand is a YMM register. The upper 
bits (MAXVL-1:256) of the corresponding destination are zeroed.
VEX.128 encoded version: The first source operand (the second operand) is a XMM register. The second source 
operand can be a XMM register or a 128-bit memory locati on. The destination operand is a XMM register. The upper 
bits (MAXVL-1:128) of the corresponding destination are zeroed.
128-bit Legacy SSE version: The second source operand (the second operand) can be an XMM register or an 128-
bit memory location. The destination is the same as the fi rst source operand. The upper bits (MAXVL-1:128) of the 
corresponding destination are unmodified.Opcode/
Mode 
Feature 
66 0F 5E /r
DIVPD xmm1, xmm2/m128A V/V SSE2 Divide packed double precision floating-point values in 
xmm1 by packed double precision floating-point 
values in xmm2/mem.
VEX.128.66.0F.WIG 5E /r
VDIVPD xmm1, xmm2, xmm3/m128B V/V AVX Divide packed double precision floating-point values in 
xmm2 by packed double precision floating-point values in xmm3/mem.
VEX.256.66.0F.WIG 5E /r
VDIVPD ymm1, ymm2, ymm3/m256B V/V AVX Divide packed double precision floating-point values in 
ymm2 by packed double precision floating-point 
values in ymm3/mem.
EVEX.128.66.0F.W1 5E /r
VDIVPD xmm1 {k1}{z}, xmm2, 
AVX512FDivide packed double precision floating-point values in 
xmm2 by packed double precision floating-point 
values in xmm3/m128/m64bcst and write results to 
xmm1 subject to writemask k1.
EVEX.256.66.0F.W1 5E /r
VDIVPD ymm1 {k1}{z}, ymm2, 
values in ymm3/m256/m64bcst and write results to ymm1 subject to writemask k1.
EVEX.512.66.0F.W1 5E /r
VDIVPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst{er}C V/V AVX512F Divide packed double precision floating-point values in 
zmm2 by packed double precision floating-point values 
in zmm3/m512/m64bcst and write results to zmm1 subject to writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ADIVPD—Divide Packed Double Pr ecision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-327Operation
VDIVPD (EVEX Encoded Versions)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC );  ; refer to Table 15-4 in the Intel® 64 and IA-32 Architectures 
ELSE 
THEN 
THEN
DEST[i+63:i] := SRC1[i+63:i] / SRC2[63:0]
ELSE 
DEST[i+63:i] := SRC1[i +63:i] / SRC2[i+63:i]
FI;
ELSE 
FI
FI;
VDIVPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] / SRC2[63:0]DEST[127:64] := SRC1[127:64] / SRC2[127:64]DEST[191:128] := SRC1[1 91:128] / SRC2[191:128]
DEST[255:192] := SRC1[2 55:192] / SRC2[255:192]
DEST[MAXVL-1:256] := 0;
VDIVPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] / SRC2[63:0]DEST[127:64] := SRC1[127:64] / SRC2[127:64]DEST[MAXVL-1:128] := 0;

THEN
ELSE 
THEN 
THEN
ELSE 
FI;
ELSE 
FI
FI;
DIVPD (128-bit Legacy SSE Version)
DEST[63:0] := SRC1[63:0] / SRC2[63:0]DEST[127:64] := SRC1[127:64] / SRC2[127:64]DEST[MAXVL-1:128 ] (Unmodified)DIVPD—Divide Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-328 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
VDIVPD __m512d _mm512_div_pd( __m512d a, __m512d b);
VDIVPD __m512d _mm512_mask_div_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);VDIVPD __m512d _mm512_maskz_div_pd(  __mmask8 k, __m512d a, __m512d b);
VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);VDIVPD __m256d _mm256_maskz_div_pd(  __mmask8 k, __m256d a, __m256d b);
VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);
VDIVPD __m512d _mm512_div_round_ pd( __m512d a, __m512d b, int);
VDIVPD __m512d _mm512_mask_div_round_pd(__m512 d s, __mmask8 k, __m512d a, __m512d b, int);
VDIVPD __m512d _mm512_maskz_div_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VDIVPD __m256d _mm256_div_pd (__m256d a, __m256d b);DIVPD __m128d _mm_div_pd (__m128d a, __m128d b);
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”DIVPS—Divide Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-329DIVPS—Divide Packed Single Precision Floating-Point Values
Performs a SIMD divide of the four, eight or sixteen packed single precision floating-point values in the first source 
operand (the second operand) by the four, eight or sixtee n packed single precision floating-point values in the 
second source operand (the third operand). Results are written to the destination operand (the first operand).
broadcasted from a 32-bit memory location. The destinat ion operand is a ZMM/YMM/XMM register conditionally 
register or a 256-bit memory location. The destination operand is a YMM register. 
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM 
register or a 128-bit memory location. The destination op erand is a XMM register. The upper bits (MAXVL-1:128) of 
Mode 
Feature 
NP 0F 5E /r
DIVPS xmm1, xmm2/m128A V/V SSE Divide packed single precision floating-point values in 
xmm1 by packed single precision floating-point values 
in xmm2/mem.
VEX.128.0F.WIG 5E /r
VDIVPS xmm1, xmm2, xmm3/m128B V/V AVX Divide packed single precision floating-point values in 
xmm2 by packed single precision floating-point values in xmm3/mem.
VEX.256.0F.WIG 5E /r
VDIVPS ymm1, ymm2, ymm3/m256B V/V AVX Divide packed single precision floating-point values in 
ymm2 by packed single precision floating-point values 
in ymm3/mem.
EVEX.128.0F.W0 5E /r
VDIVPS xmm1 {k1}{z}, xmm2, 
AVX512FDivide packed single precision floating-point values in 
xmm2 by packed single precision floating-point values 
in xmm3/m128/m32bcst and write results to xmm1 
EVEX.256.0F.W0 5E /r
VDIVPS ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcstC V/V AVX512VL
in ymm3/m256/m32bcst and write results to ymm1 subject to writemask k1.
EVEX.512.0F.W0 5E /r
VDIVPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst{er}C V/V AVX512F Divide packed single precision floating-point values in 
zmm2 by packed single precision floating-point values 
in zmm3/m512/m32bcst and write results to zmm1 subject to writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ADIVPS—Divide Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-330 Vol. 2AOperation
VDIVPS (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
ELSE 
THEN 
THEN
DEST[i+31:i] := SRC1[i+31:i] / SRC2[31:0]
ELSE 
DEST[i+31:i] := SRC1[i +31:i] / SRC2[i+31:i]
FI;
ELSE 
FI
FI;
VDIVPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] / SRC2[31:0]DEST[63:32] := SRC1[63:32] / SRC2[63:32]DEST[95:64] := SRC1[95:64] / SRC2[95:64]DEST[127:96] := SRC1[127:96] / SRC2[127:96]DEST[159:128] := SRC1[1 59:128] / SRC2[159:128]
DEST[191:160] := SRC1[1 91:160] / SRC2[191:160]
DEST[223:192] := SRC1[2 23:192] / SRC2[223:192]
DEST[255:224] := SRC1[2 55:224] / SRC2[255:224].
VDIVPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] / SRC2[31:0]DEST[63:32] := SRC1[63:32] / SRC2[63:32]DEST[95:64] := SRC1[95:64] / SRC2[95:64]DEST[127:96] := SRC1[127:96] / SRC2[127:96]DEST[MAXVL-1:128] := 0DIVPS—Divide Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-331DIVPS (128-bit Legacy SSE Version)
DEST[31:0] := SRC1[31:0] / SRC2[31:0]DEST[63:32] := SRC1[63:32] / SRC2[63:32]DEST[95:64] := SRC1[95:64] / SRC2[95:64]DEST[127:96] := SRC1[127:96] / SRC2[127:96]DEST[MAXVL-1:128 ] (Unmodified)
VDIVPS __m512 _mm512_div_ps( __m512 a, __m512 b);
VDIVPS __m512 _mm512_mask_div_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VDIVPS __m512 _mm512_maskz_div_ps(__mmask16 k, __m512 a, __m512 b);VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __ mmask8 k, __m128d a, __m128d b);
VDIVPS __m512 _mm512_div_round_ps( __m512 a, __m512 b, int);VDIVPS __m512 _mm512_mask_div_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_maskz_div_round_ps(__mmask16 k, __m512 a, __m512 b, int);VDIVPS __m256 _mm256_div_ps (__m256 a, __m256 b);DIVPS __m128 _mm_div_ps (__m128 a, __m128 b);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”DIVSD—Divide Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-332 Vol. 2ADIVSD—Divide Scalar Double Precision Floating-Point Value
Divides the low double precision floating-point value in  the first source operand by the low double precision 
floating-point value in the second source operand, and stor es the double precision floating-point result in the desti-
nation operand. The second source operand can be an X MM register or a 64-bit memory location. The first source 
and destination are XMM registers. 
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-
1:64) of the corresponding ZMM destination register remain unchanged.
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits 
127:64 of the destination operand is copied from the corre sponding quadword of the first source operand. Bits 
(MAXVL-1:128) of the destination register are zeroed.
EVEX.128 encoded version: The first source operand is  an xmm register encoded by EVEX.vvvv. The quadword 
element of the destination operand at bits 127:64 are copied  from the first source operand. Bits (MAXVL-1:128) of 
Software should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpre-

Mode 
Feature 
F2 0F 5E /r
DIVSD xmm1, xmm2/m64A V/V SSE2 Divide low double precision floating-point value in 
xmm1 by low double precision floating-point value in 
xmm2/m64.
VEX.LIG.F2.0F.WIG 5E /r
VDIVSD xmm1, xmm2, xmm3/m64B V/V AVX Divide low double precision floating-point value in 
xmm2 by low double precision floating-point value in xmm3/m64.
EVEX.LLIG.F2.0F.W1 5E /r
VDIVSD xmm1 {k1}{z}, xmm2, 
xmm3/m64{er}C V/V AVX512F Divide low double precision floating-point value in 
xmm2 by low double precision floating-point value in 
xmm3/m64.
B N/A ModRM:reg (w) VEX.vvv v (r) ModRM:r/m (r) N/A
C Tuple1 Scalar ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/ADIVSD—Divide Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-333Operation
VDIVSD (EVEX Encoded Version)
THEN
ELSE 
THEN DEST[63:0] := SRC1[63:0] / SRC2[63:0]ELSE 
FI;
VDIVSD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] / SRC2[63:0]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
DIVSD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] / SRC[63:0]DEST[MAXVL-1:64] (Unmodified)
VDIVSD __m128d _mm_mask_div_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);VDIVSD __m128d _mm_maskz_div_sd( __mmask8 k, __m128d a, __m128d b);VDIVSD __m128d _mm_div_round_sd( __m128d a, __m128d b, int);VDIVSD __m128d _mm_mask_div_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VDIVSD __m128d _mm_maskz_div_round_sd( __mmask8 k, __m128d a, __m128d b, int);DIVSD __m128d _mm_div_sd (__m128d a, __m128d b);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”DIVSS—Divide Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-334 Vol. 2ADIVSS—Divide Scalar Single Pr ecision Floating-Point Values
Divides the low single precision floating-point value in the first source operand by the low single precision floating-
point value in the second source operand, and stores the single precision floating-point result in the destination 
operand. The second source operand can be an XMM register or a 32-bit memory location.
1:32) of the corresponding YMM dest ination register remain unchanged. 
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX. vvvv. The three high-order 
doublewords of the destination operand are copied from th e first source operand. Bits (MAXVL-1:128) of the desti-
nation register are zeroed.
EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword 
elements of the destination operand at bits 127:32 are co pied from the first source operand. Bits (MAXVL-1:128) 
Software should ensure VDIVSS is encoded with VEX.L= 0. Encoding VDIVSS with VEX.L=1 may encounter unpre-
Mode 
Feature 
F3 0F 5E /r
DIVSS xmm1, xmm2/m32A V/V SSE Divide low single precision floating-point value in 
xmm1 by low single precision floating-point value in 
xmm2/m32.
VEX.LIG.F3.0F.WIG 5E /r
VDIVSS xmm1, xmm2, xmm3/m32B V/V AVX Divide low single precision floating-point value in 
xmm2 by low single precision floating-point value in xmm3/m32.
EVEX.LLIG.F3.0F.W0 5E /r
VDIVSS xmm1 {k1}{z}, xmm2, 
xmm3/m32{er}C V/V AVX512F Divide low single precision floating-point value in 
xmm2 by low single precision floating-point value in 
xmm3/m32.
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ADIVSS—Divide Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-335Operation
VDIVSS (EVEX Encoded Version)
THEN
ELSE 
THEN DEST[31:0] := SRC1[31:0] / SRC2[31:0]ELSE 
FI;
VDIVSS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] / SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
DIVSS (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0] / SRC[31:0]DEST[MAXVL-1:32] (Unmodified)
VDIVSS __m128 _mm_mask_div_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VDIVSS __m128 _mm_maskz_div_ss( __mmask8 k, __m128 a, __m128 b);
VDIVSS __m128 _mm_div_round_ss( __m128 a, __m128 b, int);VDIVSS __m128 _mm_mask_div_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VDIVSS __m128 _mm_maskz_div_round_ss( __mmask8 k, __m128 a, __m128 b, int);DIVSS __m128 _mm_div_ss(__m128 a, __m128 b);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”DPPD—Dot Product of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-336 Vol. 2ADPPD—Dot Product of Packed Double Precision Floating-Point Values
Conditionally multiplies the packed double precision floating -point values in the destination operand (first operand) 
with the packed double precision floating-point values  in the source (second operand) depending on a mask 
extracted from bits [5:4] of the immediate operand (third  operand). If a condition mask bit is zero, the corre-
sponding multiplication is replaced by a value of 0. 0 in the manner described by Section 12.8.4 of Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 1.
The two resulting double precision values are summed into an intermediate result. The intermediate result is condi-
tionally broadcasted to the destination using a broadcas t mask specified by bits [1:0] of the immediate byte. 
If a broadcast mask bit is “1”, the intermediate result is  copied to the corresponding qword element in the destina-
tion operand. If a broadcast mask bit is zero, the co rresponding element in the destination is set to zero.
DPPD follows the NaN forwarding rules stated in the Softwa re Developer’s Manual, vol. 1, table 4.7. These rules do 
not cover horizontal prioritization of NaNs. Horizontal prop agation of NaNs to the destination and the positioning of 
those NaNs in the destination is implementation dependen t. NaNs on the input sources or computationally gener-
ated NaNs will have at least one NaN propagated to the destination.
zeroed.
If VDPPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an 
#UD exception.Opcode/
ModeCPUID 
Feature 
66 0F 3A 41 /r ib
DPPD xmm1, xmm2/m128, imm8RMI V/V SSE4_1 Selectively multip ly packed double precision 
floating-point values from xmm1 with packed 
double precision floating-point values from 
xmm2, add and selectively store the packed double precision floating-point values to 
xmm1.
VEX.128.66.0F3A.WIG 41 /r ib
VDPPD xmm1,xmm2, xmm3/m128, imm8RVMI V/V AVX Selectively multiply  packed double precision 
floating-point values from xmm2 with packed double precision floating-point values from 
xmm3, add and selectively store the packed 
double precision floating-point values to xmm1.

zeroed.
ModeCPUID 
Feature 
xmm1.
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8DPPD—Dot Product of Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-337Operation
DP_primitive (SRC1, SRC2)
IF (imm8[4] = 1) 
THEN Temp1[63:0] := DEST[63:0] * SRC[ 63:0]; // update SIMD exception flags
ELSE Temp1[63:0] := +0.0; FI;
IF (imm8[5] = 1) 
THEN Temp1[127:64] := DEST[127:64] * SRC[ 127:64]; // update SIMD exception flags
ELSE Temp1[127:64] := +0.0; FI;
/* if unmasked exception reported, execute exception handler*/
Temp2[63:0] := Temp1[63:0] + Temp1[127:64]; // update SIMD exception flags
IF (imm8[0] = 1) 
THEN DEST[63:0] := Temp2[63:0];
ELSE DEST[63:0] := +0.0; FI;
IF (imm8[1] = 1) 
THEN DEST[127:64] := Temp2[63:0];ELSE DEST[127:64] := +0.0; FI;
DPPD (128-bit Legacy SSE Version)
DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);DEST[MAXVL-1:128 ] (Unmodified)
VDPPD (VEX.128 Encoded Version)
DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);DEST[MAXVL-1:128] := 0
None.
DPPD __m128d _mm_dp_pd ( __m128d a, __m128d b, const int mask);
Exceptions are determined separately for each add and multiply operation. Unmasked exceptions will leave the 
destination untouched.
See Table 2-19, “Type 2 Class Exce ption Conditions,” additionally:
#UD If VEX.L= 1.DPPS—Dot Product of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-338 Vol. 2ADPPS—Dot Product of Packed Single Precision Floating-Point Values
Conditionally multiplies the packed single precision floating -point values in the destination operand (first operand) 
with the packed single precision floats in the source (second operand) depending on a mask extracted from the 
high 4 bits of the immediate byte (third operand). If a condition mask bit in imm8[7:4] is zero, the corresponding 
multiplication is replaced by a value of 0.0 in  the manner described by Section 12.8.4 of Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1.
The four resulting single precision values are summed into an intermediate result. The intermediate result is condi-
tionally broadcasted to the destination using a broadcas t mask specified by bits [3:0] of the immediate byte.
If a broadcast mask bit is “1”, the intermediate result is  copied to the corresponding dword element in the destina-
DPPS follows the NaN forwarding rules stated in the Softwa re Developer’s Manual, vol. 1, table 4.7. These rules do 
zeroed.
register or a 256-bit memory location. Th e destination operand is a YMM register.Opcode/
ModeCPUID 
Feature 
66 0F 3A 40 /r ib
DPPS xmm1, xmm2/m128, imm8RMI V/V SSE4_1 Selectively multiply pa cked single precision floating-
point values from xmm1 with  packed single precision 
floating-point values from xmm2, add and selectively 
store the packed single precision floating-point values or zero values to xmm1.
VEX.128.66.0F3A.WIG 40 /r ib
VDPPS xmm1,xmm2, xmm3/m128, imm8RVMI V/V AVX Multiply packed single precision floating-point values 
from xmm1 with packed single precision floating-point 
values from xmm2/mem selectively add and store to xmm1.
VEX.256.66.0F3A.WIG 40 /r ib
VDPPS ymm1, ymm2, ymm3/m256, imm8RVMI V/V AVX Multiply packed single precision floating-point values 
from ymm2 with packed single precision floating-point 
values from ymm3/mem, se lectively add pairs of 
elements and store to ymm1.
RVMI ModRM:reg (w) VEX.vvvv  (r) ModRM:r/m (r) imm8DPPS—Dot Product of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-339Operation
THEN Temp1[31:0] := DEST[31:0] * SRC[ 31:0]; // update SIMD exception flags
ELSE Temp1[31:0] := +0.0; FI;
THEN Temp1[63:32] := DEST[63:32] * SRC[63:32]; // update SIMD exception flagsELSE Temp1[63:32] := +0.0; FI;
IF (imm8[6] = 1) 
THEN Temp1[95:64] := DEST[95:64] * SRC[95:64]; // update SIMD exception flagsELSE Temp1[95:64] := +0.0; FI;
IF (imm8[7] = 1) 
THEN Temp1[127:96] := DEST[127:96] * SRC[ 127:96]; // update SIMD exception flags
ELSE Temp1[127:96] := +0.0; FI;
Temp2[31:0] := Temp1[31:0] + Temp1[63:32]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/Temp3[31:0] := Temp1[95:64] + Temp1[127:96]; // update SIMD exception flags/* if unmasked exception reported, execute exception handler*/Temp4[31:0] := Temp2[31:0] + Temp3[31:0]; // update SIMD exception flags/* if unmasked exception reported, execute exception handler*/
THEN DEST[31:0] := Temp4[31:0];ELSE DEST[31:0] := +0.0; FI;
THEN DEST[63:32] := Temp4[31:0];ELSE DEST[63:32] := +0.0; FI;
IF (imm8[2] = 1) 
THEN DEST[95:64] := Temp4[31:0];ELSE DEST[95:64] := +0.0; FI;
IF (imm8[3] = 1) 
THEN DEST[127:96] := Temp4[31:0];ELSE DEST[127:96] := +0.0; FI;
DPPS (128-bit Legacy SSE Version)
VDPPS (VEX.128 Encoded Version)
VDPPS (VEX.256 Encoded Version)
DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);DEST[255:128] := DP_Primitive(S RC1[255:128], SRC2[255:128]);
None.DPPS—Dot Product of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-340 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
(V)DPPS __m128 _mm_dp_ps ( __m128 a, __m128 b, const int mask);
VDPPS __m256 _mm256_dp_ps ( __m256 a, __m256 b, const int mask);
Exceptions are determined separately for each add and multiply operation, in the order of their execution. 
Unmasked exceptions will leave the destination operands unchanged.
See Table 2-19, “Type 2 Class Exception Conditions.”EMMS—Empty MMX Technology StateINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-341EMMS—Empty MMX Technology State
Description 
Sets the values of all the tags in th e x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data 
registers (which are aliased to the MMX technology register s) as available for use by x87 FPU floating-point instruc-
tions. (See Figure 8-7 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the 
format of the x87 FPU tag word.) All other MMX instructions  (other than the EMMS instruction) set all the tags in 
x87 FPU tag word to valid (all 0s).
The EMMS instruction must be used to clear the MMX techno logy state at the end of all MMX technology procedures 
or subroutines and before calling other procedures or subr outines that may execute x87 floating-point instructions. 
If a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag 
word has been reset by the EMMS inst ruction, an x87 floating-point register stack overflow can occur that will 
result in an x87 floating-point exception or incorrect result.
EMMS operation is the same in non-64-bit modes and 64-bit mode.
Operation
x87FPUTagWord := FFFFH;
void _mm_empty()
None
#UD If CR0.EM[bit 2] = 1.
#NM If CR0.TS[bit 3] = 1.
#MF If there is a pending FPU exception.#UD If the LOCK prefix is used.
Real-Address Mode Exceptions 
Same exceptions as in protected mode.Opcode Instruction Op/ 
En64-Bit 

Operation
None
En64-Bit 
NP 0F 77 EMMS ZO Valid Valid Set th e x87 FPU tag word to empty.
Z O N / AN / AN / AN / AENCODEKEY128—Encode 128-Bit Key With Key LockerINSTRUCTION SET REFERENCE, A-L
3-342 Vol. 2AENCODEKEY128—Encode 128-Bit Key With Key Locker
The ENCODEKEY1281 instruction wraps a 128-bit AES key from the implicit operand XMM0 into a key handle that 
is then stored in the implicit destination operands XMM0-2.
The explicit source operand specifies handle restrictions, if any.The explicit destination operand is po pulated with information on the source of the key and its attributes. XMM4 
through XMM6 are reserved for future usages and so ftware should not rely upon them being zeroed.
Operation
ENCODEKEY128 
#GP (0) if a reserved bit2 in SRC[31:0] is set
InputKey[127:0] := XMM0;KeyMetadata[2:0] = SRC[2:0];KeyMetadata[23:3] = 0; // Reserved for future usageKeyMetadata[27:24] = 0; // KeyType is AES-128 (value of 0)KeyMetadata[127:28] = 0; // Reserved for future usage
// KeyMetadata is the AAD input and InputK ey is the Plaintext input for WrapKey128
Handle[383:0] := WrapKey128(InputKey[127:0], KeyMetadata[127:0 ], IWKey.Integrity Key[127:0], IWKey.Encryption  Key[255:0]);
DEST[0] := IWKey.NoBackup;
DEST[4:1] := IWKe y.KeySource[3:0];
DEST[31:5] = 0;XMM0 := Handle[127:0];  // AADXMM1 := Handle[255:128]; // Integrity TagXMM2 := Handle[383:256]; // CipherTextXMM4 := 0; // Reserved for future usageXMM5 := 0; // Reserved for future usageXMM6 := 0; // Reserved for future usageRFLAGS.OF, SF, ZF, AF, PF, CF := 0;
All arithmetic flags (OF, SF, ZF, AF, PF, CF) are cleared to 0. Although they are cleared for the currently defined oper-
ations, future extensions may report information in the flags.Opcode/
ModeCPUID 
Feature 
F3 0F 38 FA 11:rrr:bbb 
ENCODEKEY128 r32, r32, <XMM0-2>, 
<XMM4-6>A V/V AESKLE Wrap a 128-bit AES key from XMM0 into a key handle 
and output handle in XMM0—2.
Op/En Tuple Operand 1 Operand 2 Operand 3 Operands 4—5 Operands 6—7
A N/A ModRM:reg (w) ModRM:r/m (r) I mplicit XMM0 (r, w) Implicit XM M1—2 (w) Implicit XMM4—6 (w)
https://software.intel.com/content/www/us/en/deve lop/download/intel-key-locker-specification.html .
2. SRC[31:3] are currently reserved for futu re usages. SRC[2], which indicates a no-dec rypt restriction, is reserved if CPUID.19 H:EAX[2] 
is 0. SRC[1], which indicates a no-encrypt restriction, is reserved if CPUID.19H:EAX[1] is 0. SRC[0], which indicates a CPL0-on ly 
restriction, is reserved if CPUID.19H:EAX[0] is 0.ENCODEKEY128—Encode 128-Bit Key With Key LockerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-343Intel C/C++ Compiler Intrinsic Equivalent
ENCODEKEY128 unsigned int _mm_encodekey128_u32(unsigned int htype, __m128i key, void* h);
#GP If reserved bit is set in source register value.
If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE[bit 0] = 0.If CR0.EM = 1.
#NM If CR0.TS = 1.ENCODEKEY256—Encode 256-Bit Key With Key LockerINSTRUCTION SET REFERENCE, A-L
3-344 Vol. 2AENCODEKEY256—Encode 256-Bit Key With Key Locker
The ENCODEKEY2561 instruction wraps a 256-bit AES key from the implicit operand XMM1:XMM0 into a key handle 
that is then stored in the implicit destination operands XMM0-3.
The explicit source operand is a general-purpose register an d specifies what handle restrictions should be built into 
the handle.
The explicit destination operand is po pulated with information on the source of the key and its attributes. XMM4 
Operation
ENCODEKEY256 
InputKey[255:0] := XMM1:XMM0;KeyMetadata[2:0] = SRC[2:0];KeyMetadata[23:3] = 0; // Reserved for future usageKeyMetadata[27:24] = 1; // KeyType is AES-256 (value of 1)KeyMetadata[127:28] = 0; // Reserved for future usage
// KeyMetadata is the AAD input and InputK ey is the Plaintext input for WrapKey256
Handle[511:0] := WrapKey256(InputKey[255:0], KeyMetadata[127:0 ], IWKey.Integrity Key[127:0], IWKey.Encryption  Key[255:0]);
DEST[31:5] = 0;XMM0 := Handle[127:0];  // AADXMM1 := Handle[255:128]; // Integrity TagXMM2 := Handle[383:256]; // CipherText[127:0]XMM3 := Handle[511:384]; // CipherText[255:128]
XMM4 := 0; // Reserved for future usage
XMM5 := 0; // Reserved for future usageXMM6 := 0; // Reserved for future usage
RFLAGS.OF, SF, ZF, AF, PF, CF := 0;Opcode/
ModeCPUID 
Feature 
F3 0F 38 FB 11:rrr:bbb 
ENCODEKEY256 r32, r32 <XMM0-6>A V/V AESKLE Wrap a 256-bit AES key from XMM1:XMM0 into a key 
handle and store it in XMM0—3.
Op/En Tuple Operand 1 Operand 2 Operands 3—4 Operands 5—9
A N/A ModRM:reg (w) ModRM:r/m (r) Implicit XMM0—1 (r, w) Implicit XMM2—6 (w)
restriction, is reserved if CPUID.19H:EAX[0] is 0.ENCODEKEY256—Encode 256-Bit Key With Key LockerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-345Flags Affected
ations, future extensions may report information in the flags.
ENCODEKEY256 unsigned int _mm_encodekey256_u32(unsigned int htype, __m128i key_lo, __m128i key_hi, void* h);
#NM If CR0.TS = 1.ENDBR32—Terminate an Indirect Bran ch in 32-bit and Compatibility ModeINSTRUCTION SET REFERENCE, A-L
3-346 Vol. 2AENDBR32—Terminate an Indirect Bran ch in 32-bit and Compatibility Mode
Terminate an indirect branch in 32 bit and compatibility mode.
Operation
IF EndbranchEnabled(CPL) & (IA32_EFER.LMA = 0 | (IA32_EFER.LMA=1 & CS.L = 0)
IF CPL = 3
THEN
IA32_U_CET.TRACKER = IDLEIA32_U_CET.SUPPRESS = 0
ELSE
IA32_S_CET.TRACKER = IDLEIA32_S_CET.SUPPRESS = 0
FI;
FI;
None.
Mode 
Feature 
F3 0F 1E FB
ENDBR32ZO V/V CET_IBT Terminate indirect branch in 32-bit and compatibility 
mode.
ZO N/A N/A N/A N/A N/AENDBR64—Terminate an Indirect Branch in 64-bit ModeINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-347ENDBR64—Terminate an Indirect Branch in 64-bit Mode
Terminate an indirect branch in 64 bit mode.
Operation
IF EndbranchEnabled(CPL) & IA32_EFER.LMA = 1 & CS.L = 1
IF CPL = 3
THEN
ELSE
FI;
FI;
None.
Mode 
Feature 
F3 0F 1E FA
ENDBR64ZO V/V CET_IBT Terminate indirect branch in 64-bit mode.
ZO N/A N/A N/A N/A N/AENQCMD—Enqueue CommandINSTRUCTION SET REFERENCE, A-L
3-348 Vol. 2AENQCMD—Enqueue Command
The ENQCMD instruction allows so ftware to write commands to enqueue registers , which are special device 
registers accessed using memory-mapped I/O (MMIO).
Enqueue registers expect writes to have the following format:
Bits 19:0 convey the process address space identifier (PAS ID), a value which system software may assign to indi-
vidual software threads. Bit 31 contains privilege identi fication (0 = user; 1 = supervisor). Devices implementing 
enqueue registers may use these two values along with  a device-specific command in the upper 60 bytes.
The ENQCMD instruction begins by reading 64 bytes of comm and data from its source memory operand. This is an 
ordinary load with cacheability and memory ordering im plied normally by the memory type. The source operand 
need not be aligned, and there is no guarantee that all 64 bytes are loaded atomically. Bits 31:0 of the source 
operand must be zero.
The instruction then formats those 64 bytes into command data  with a format consistent with that given in 
Figure 3-16:
•Command[19:0] get IA32_PASID[19:0].1

•Command[30:20] are zero.
•Command[31] is 0 (indicating user; this value is used regardless of CPL).
•Command[511:32] get bits 511:32 of the source operand that was read from memory.
The ENQCMD instruction uses an enqueue store  (defined below) to write this command data to the destination 
operand. The address of the destination operand is specified in a general-purpose register as an offset into the ES 
segment (the segment cannot be overridden).2 The destination linear address must be 64-byte aligned. The oper-
ation of an enqueue store disregards the memo ry type of the destination memory address.Opcode/
Mode 
F2 0F 38 F8 !(11):rrr:bbb
ENQCMD r32/r64, m512A V/V ENQCMD Atomically enqueue 64-byte user command from 
source memory operand to destination offset in 
ES segment specified in register operand as 
offset in ES segment.
Figure 3-16.  64-Byte Data Written to Enqueue Registers
1. It is expected that system software will load the IA32_PASID MSR so that bi ts 19:0 contain the PASI D of the current soft-
ware thread. The MSR’s valid bit, IA32_PASID[31], must be 1. For additional details on the IA32_PASID MSR, see the Intel® 
64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 4.
2. In 64-bit mode, the width of th e register operand is 64 bits ( 32 bits with a 67H prefix). Ou tside 64-bit mode when CS.D = 
1, the width is 32 bits (16 bits with a 67H prefix). Outside 64-bit mode when CS.D=0, the widt h is 16 bits (32 bits with a 
67H prefix).RESERVED PRIV
01920 30 31 32 511
PASID DEVICE SPECIFIC COMMANDENQCMD—Enqueue CommandINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-349An enqueue store is not ordered relative to older stores to WB or WC memory (including non-temporal stores) or 
to executions of the CLFLUSHOPT or CLWB (when applied to  addresses other than that of the enqueue store). Soft-
ware can enforce such ordering by executing a fencing instruction such as SFENCE or MFENCE before the enqueue 
store.
An enqueue store does not write the data into the cache hi erarchy, nor does it fetch any data into the cache hier-
archy. An enqueue store’s command data is never combin ed with that of any other store to the same address.
Unlike other stores, an enqueue store returns a status, whic h the ENQCMD instruction loads into the ZF flag in the 
RFLAGS register:
•ZF = 0 (success) reports that the 64-byte command data wa s written atomically to a device’s enqueue register 
and has been accepted by the device. (It does not guar antee that the device has acted on the command; it may 
have queued it for later execution.)
•ZF = 1 (retry) reports that the command data was not a ccepted. This status is returned if the destination 
address is an enqueue register but the command was not accepted due to capacity or other temporal reasons. 
This status is also returned if the destination addre ss was not an enqueue register (including the case of a 
memory address); in these cases, the store is drop ped and is written neither to MMIO nor to memory.
Availability of the ENQCMD instruction is indicated by the presence of the CPUID feature flag ENQCMD 
(CPUID.(EAX=07H, EC X=0H):ECX[bit 29]).
Operation
IF IA32_PASID[31] = 0
THEN #GP;
ELSE
COMMAND := (SRC & ~FFFFFFFFH) | (IA32_PASID & FFFFFH);
DEST := COMMAND;
FI;
ENQCMD int_enqcmd(void *dst, const void *src)
The ZF flag is set if the enqueue-store completion returns the retry status; otherwise it is cleared. All other flags 
are cleared.
None.
If destination linear address is not aligned to a 64-byte boundary.
If the PASID Valid field (bit 31) is 0 in IA32_PASID MSR.
If bits 31:0 of the source operand are not all zero.
#UD If CPUID.07H.0H:ECX.ENQCMD[bit 29] = 0.
If the LOCK prefix is used.ENQCMD—Enqueue CommandINSTRUCTION SET REFERENCE, A-L
3-350 Vol. 2AReal-Address Mode Exceptions
#GP If any part of the operand lies outsid e the effective address space from 0 to FFFFH.
If destination linear address is not aligned to a 64-byte boundary.If the PASID Valid field (bit 31) is 0 in IA32_PASID MSR.
Same exceptions as in real-address mode. Additionally:
#SS(0) If a memory address referencing the SS segment is in non-canonical form.
#GP(0) If the memory address is in non-canonical form.
If the PASID Valid field (bit 31) is 0 in IA32_PASID MSR.If bits 31:0 of the source operand are not all zero.
#UD If CPUID.07H.0H:ECX.ENQCMD[bit 29].
If the LOCK prefix is used.ENQCMDS—Enqueue Command SupervisorINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-351ENQCMDS—Enqueue Command Supervisor
The ENQCMDS instruction allows syst em software to write commands to enqueue registers , which are special 
device registers accessed using memory-mapped I/O (MMIO).
Enqueue registers expect writes to have the format given in Figure 3-16 and explained in the section on 
“ENQCMD—Enqueue Command.”
The ENQCMDS instruction begins by read ing 64 bytes of command data from its source memory operand. This is 
an ordinary load with cacheability an d memory ordering implied normally by  the memory type. The source operand 
need not be aligned, and there is no guarantee that all 64 bytes are loaded atomically. Bits 30:20 of the source 
ENQCMDS formats its source data differently from  ENQCMD. Specifically, it formats them into command data  as 
follows:
•Command[19:0] get bits 19:0 of the source operand that  was read from memory. These 20 bits communicate 
a process address-space identifier (PASID). 
•Command[511:31] get bits 511:31 of the source operan d that was read from memory. Bit 31 communicates a 
privilege identification (0 = user; 1 = supervisor).
The ENQCMDS instruction then uses an enqueue store  (defined below) to write this command data to the desti-
nation operand. The address of the dest ination operand is specified in a general-purpose register as an offset into 
the ES segment (the segm ent cannot be overridden).1 The destination linear address must be 64-byte aligned. The 
operation of an enqueue store disregards the me mory type of the destination memory address.
An enqueue store is not ordered relative to older stores to WB or WC memory (including non-temporal stores) or 
store.
Unlike other stores, an enqueue store returns a status, whic h the ENQCMDS instruction loads into the ZF flag in the 
address is an enqueue register but the command was not accepted due to capacity or other temporal reasons. Opcode/
Mode 
F3 0F 38 F8 !(11):rrr:bbb
ENQCMDS r32/r64, m512A V/V ENQCMD Atomically enqueue 64-byte command with 
PASID from source memory operand to 
destination offset in ES segment specified in 
register operand as offset in ES segment.
1. In 64-bit mode, the width of the register oper and is 64 bits (32 bits with a 67H pref ix). Outside 64-bit mode when CS.D = 
67H prefix).ENQCMDS—Enqueue Command SupervisorINSTRUCTION SET REFERENCE, A-L
3-352 Vol. 2AThis status is also returned if the destination addre ss was not an enqueue register (including the case of a

Mode 
3-352 Vol. 2AThis status is also returned if the destination addre ss was not an enqueue register (including the case of a 
memory address); in these cases, the store is dro pped and is written neither to MMIO nor to memory.
The ENQCMDS instruction may be executed  only if CPL = 0. Availability of th e ENQCMDS instruction is indicated by 
the presence of the CPUID feature flag EN QCMD (CPUID.(EAX=07H, ECX=0H):ECX[bit 29]).
Operation
DEST := SRC;
ENQCMDS int_enqcmds(void *dst, const void *src)
None.
If the current privilege level is not 0.
If bits 30:20 of the source operand are not all zero.
If destination linear address is not aligned to a 64-byte boundary.If bits 30:20 of the source operand are not all zero.
#GP(0) The ENQCMDS instruction is not recognized in virtual-8086 mode.
If the current privilege level is not 0.If bits 30:20 of the source operand are not all zero.
#PF(fault-code) For a page fault.ENQCMDS—Enqueue Command SupervisorINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-353#UD If CPUID.07H.0H:ECX.ENQCMD[bit 29].
If the LOCK prefix is used.ENTER—Make Stack Frame for Procedure ParametersINSTRUCTION SET REFERENCE, A-L
3-354 Vol. 2AENTER—Make Stack Frame for Procedure Parameters
Creates a stack frame (comprising of space for dynamic storage and 1-32 frame pointer storage) for a procedure. 
The first operand (imm16) specifies the size of the dynami c storage in the stack frame (that is, the number of bytes 
of dynamically allocated on the stack for the procedure). The second operand (imm8) gives the lexical nesting level 
(0 to 31) of the procedure. The nesting level (imm8 mod 32) and the OperandSize attribute determine the size in 
bytes of the storage sp ace for frame pointers.
The nesting level determines the number of frame pointers th at are copied into the “dis play area” of the new stack 
frame from the preceding frame. The default size of the frame pointer is the StackAddrSize attribute, but can be 
overridden using the 66H prefix. Thus, the OperandSize attr ibute determines the size of each frame pointer that 
will be copied into the stack frame and the data being tr ansferred from SP/ESP/RSP re gister into the BP/EBP/RBP 
register.
The ENTER and companion LEAVE instructions are provided  to support block structured languages. The ENTER 
instruction (when used) is typically the first instruction in a procedure and is used to set up a new stack frame for a procedure. The LEAVE instruction is then used at the en d of the procedure (just before the RET instruction) to 
release the stack frame.
If the nesting level is 0, the processor pushes the fram e pointer from the BP/EBP/RBP register onto the stack, 
copies the current stack pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and loads the 
SP/ESP/RSP register with the current stack-pointer value mi nus the value in the size operand. For nesting levels of 
1 or greater, the processor pushes additional frame pointe rs on the stack before adjusting the stack pointer. These 
additional frame pointers provide the called procedure with access points to other nested frames on the stack. See 
“Procedure Calls for Block-Structured Languages” in Chapter 6 of the Intel
Developer’s Manual, Volume 1, for more information about the actions of the ENTER instruction.
The ENTER instruction causes a page fault whenever a writ e using the final value of the stack pointer (within the 
current stack segment) would do so.
In 64-bit mode, default operation size is 64 bits; 32-bi t operation size cannot be encoded. Use of 66H prefix 
changes frame pointer operand size to 16 bits.
When the 66H prefix is used and causin g the OperandSize attribute to be less than the StackAddrSize, software is 
responsible for the following:
•The companion LEAVE instruction must also use the 66H prefix,
•The value in the RBP/EBP register prior to executing “66H  ENTER” must be within the same 16KByte region of 
the current stack pointer (RSP/ESP), such that the valu e of RBP/EBP after “66H ENTE R” remains a valid address 
in the stack. This ensures “66H LEAVE” can restore 16-bits of data from the stack.Opcode Instruction Op/ 
En64-Bit 
C8 iw 00 ENTER imm16, 0 II Valid Valid Create a stack frame for a procedure.
C8 iw 01 ENTER imm16,1 II Valid Valid Create a stack frame with a nested pointer for 
a procedure.
C8 iw ib ENTER imm16, imm8 II Valid Valid Create a stack frame with nested pointers for 
II iw imm8 N/A N/AENTER—Make Stack Frame for Procedure ParametersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-355Operation
AllocSize := imm16;
NestingLevel :=  imm8 MOD 32;
IF (OperandSize = 64)
THEN 
Push(RBP); (* RSP decrements by 8 *)FrameTemp := RSP; 
= 32
THEN 
Push(EBP); (* (E)SP decrements by 4 *)FrameTemp := ESP; FI;
= 16 *)
Push(BP); (* RSP or (E)SP decrements by 2 *)FrameTemp := SP; 
FI;
IF NestingLevel
 = 0
THEN GOTO CONTINUE;
FI;
IF (NestingLevel > 1) 
THEN FOR i := 1 to (NestingLevel - 1)
DO 
THEN
RBP := RBP - 8;Push([RBP]); (* Quadword push *)
ELSE IF OperandSize = 32
THEN
IF StackSize = 32
EBP := EBP - 4;Push([EBP]); (* Doubleword push *)
ELSE (* StackSize = 16 *)
BP := BP - 4;Push([BP]); (* Doubleword push *)
FI;
FI;
ELSE (* OperandSize = 16 *)
IF StackSize = 64
THEN
RBP := RBP - 2;Push([RBP]); (* Word push *)
ELSE IF StackSize = 32
THEN
EBP := EBP - 2;Push([EBP]); (* Word push *)
BP := BP - 2;Push([BP]); (* Word push *)
FI;
FI;
OD;
FI;
IF (OperandSize = 64) (* nestinglevel 1 *)ENTER—Make Stack Frame for Procedure ParametersINSTRUCTION SET REFERENCE, A-L
3-356 Vol. 2ATHEN
Push(FrameTemp); (* Quadword push and RSP decrements by 8 *)
THEN 
Push(FrameTemp); FI; (* Doubleword push and (E)SP decrements by 4 *)
Push(FrameTemp); (* Word push and RSP|ESP|SP decrements by 2 *)
FI;
CONTINUE:
IF 64-Bit Mode (StackSize = 64)
THEN
RBP := FrameTemp;RSP := RSP 
− AllocSize;
ELSE IF OperandSize  = 32 
THEN
EBP := FrameTemp;
ESP := ESP − AllocSize; FI;
BP := FrameTemp[15:1]; (* Bits 16 and above of applicable RBP/EBP are unmodified *)SP := SP 
FI;
END;
None.
#SS(0) If the new value of the SP or ESP register is outside the stack segment limit.
#PF(fault-code) If a page fault occurs or if a write usin g the final value of the stack pointer (within the current 
stack segment) would cause a page fault.
#SS If the new value of the SP or ESP register is outside the stack segment limit.
#SS(0) If the new value of the SP or ESP register is outside the stack segment limit.#PF(fault-code) If a page fault occurs or if a write usin g the final value of the stack pointer (within the current 
#SS(0) If the stack address is in a non-canonical form.#PF(fault-code) If a page fault occurs or if a write usin g the final value of the stack pointer (within the current 
#UD If the LOCK prefix is used.EXTRACTPS—Extract Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-357EXTRACTPS—Extract Packed Floating-Point Values
Extracts a single precision floating-point value from the source operand (second operand) at the 32-bit offset spec-
ified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored.
The extracted single precision floating-point value is stored in the low 32-bits of the destination operand
In 64-bit mode, destination register operand has default op erand size of 64 bits. The upper 32-bits of the register

In 64-bit mode, destination register operand has default op erand size of 64 bits. The upper 32-bits of the register 
are filled with zero. REX.W is ignored.
VEX.128 and EVEX encoded version: When VEX.W1 or EV EX.W1 form is used in 64-bit mode with a general 
purpose register (GPR) as a destination operand, the pa cked single quantity is zero extended to 64 bits. 
VEX.vvvv/EVEX.vvvv is reserved and must be  1111b otherwise instructions will #UD.
128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as 
a destination operand, the packed single quantity is zero extended to 64 bits.
The source register is an XMM register. Imm8[1:0] determ ine the starting DWORD offset from which to extract the 
32-bit floating-point value.
If VEXTRACTPS is encoded with VEX.L=  1, an attempt to execute the instru ction encoded with VEX.L= 1 will cause 
an #UD exception.
Operation
VEXTRACTPS (EVEX and VEX.128 Encoded Version)
SRC_OFFSET := IMM8[1:0]IF (64-Bit Mode and DEST is register)
DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFhDEST[63:32] := 0
ELSE
DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
FIOpcode/
Mode 
66 0F 3A 17 /r ib
EXTRACTPS reg/m32, xmm1, imm8A VV SSE4_1 Extract one single precision floating-point value from 
xmm1 at the offset specified by imm8 and store the 
result in reg or m32. Zero extend the results in 64-bit 
register if applicable.
VEX.128.66.0F3A.WIG 17 /r ib
VEXTRACTPS reg/m32, xmm1, imm8A V/V AVX Extract one single precision floating-point value from 
EVEX.128.66.0F3A.WIG 17 /r ib
VEXTRACTPS reg/m32, xmm1, imm8B V/V AVX512F Extract one single precision floating-point value from 
A N/A ModRM:r/m (w) ModRM:reg (r) imm8 N/A
B Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) imm8 N/AEXTRACTPS—Extract Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-358 Vol. 2AEXTRACTPS (128-bit Legacy SSE Version)
ELSE
FI
EXTRACTPS int _mm_extract_ps (__m128 a, const int nidx);
None.
EVEX-encoded instructions, see Table 2-57, “Type E9NF Class Exception Conditions.”Additionally:
#UD IF VEX.L = 0.
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.F2XM1—Compute 2x–1INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-359F2XM1—Compute 2x–1
Computes the exponential value of 2 to the power of the so urce operand minus 1. The source operand is located in 
register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range –1.0 to 
+1.0. If the source value is outside this range, the result is undefined.
The following table shows the results obtained when co mputing the exponential value of various classes of 
numbers, assuming that neither overflow nor underflow occurs.
Values other than 2 can be exponentiated using the following formula:
xy := 2(y ∗ log2x)
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
ST(0) := (2ST(0) − 1);
FPU Flags Affected
C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
Floating-Point Exceptions
#IS Stack underflow occurred.#IA Source operand is an SNaN value or unsupported format.#D Source is a denormal value.
#U Result is too small for destination format.
#P Value cannot be represented exactly in destination format.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
Same exceptions as in protected mode.Opcode Instruction 64-Bit 
D9 F0 F2XM1 Valid Valid Replace ST(0) with (2ST(0) – 1).
Table 3-16.  Results Obtained from F2XM1
ST(0) SRC ST(0) DEST
− 1.0 to −0 − 0.5 to − 0
− 0 − 0
+ 0 + 0
+ 0 to +1.0 + 0 to 1.0 F2XM1—Compute 2x–1INSTRUCTION SET REFERENCE, A-L
3-360 Vol. 2ACompatibility Mode Exceptions
Same exceptions as in protected mode.FABS—Absolute ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-361FABS—Absolute Value
Clears the sign bit of ST(0) to create the absolute va lue of the operand. The following table shows the results 
obtained when creating the absolute value of various classes of numbers.
Operation
ST(0) := |ST(0)|;
C1 Set to 0.
#IS Stack underflow occurred.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UD If the LOCK prefix is used.
D9 E1 FABS Valid Valid Replace ST with its absolute value.
Table 3-17.  Results Obtained from FABS 
− ∞ + ∞
− F + F
− 0 + 0
+ 0 + 0
+ F + F
+ ∞ + ∞
NaN NaN 
NOTES:
F Means finite floating-point value.FADD/FADDP/FIADD—AddINSTRUCTION SET REFERENCE, A-L
3-362 Vol. 2AFADD/FADDP/FIADD—Add
Adds the destination and source operands and stores the sum in the destination location. The destination operand 
is always an FPU register; the source operand can be a re gister or a memory location. Source operands in memory 
can be in single precision or double precision floating-p oint format or in word or doubleword integer format.
The no-operand version of the instruction adds the conten ts of the ST(0) register to the ST(1) register. The one-
operand version adds the contents of a memory location (eit her a floating-point or an integer value) to the contents 
of the ST(0) register. The two-operand version, adds the cont ents of the ST(0) register to the ST(i) register or vice 
versa. The value in ST(0) can be doubled by coding:
FADD ST(0), ST(0);
The FADDP instructions perform the additional operation of  popping the FPU register stack after storing the result. 
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) 
by 1. (The no-operand version of the floating-point add instructions always results in the register stack being 
popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)
The FIADD instructions convert an integer source operan d to double extended-precision floating-point format 
before performing the addition.
The table on the following page shows the results obtained  when adding various classes of numbers, assuming that 
neither overflow nor underflow occurs.
When the sum of two operands with op posite signs is 0, the result is +0, except for the round toward −∞ mode, in 
which case the result is −0. When the source operand is an integer 0, it is treated as a +0.
When both operand are infinities of the same sign, the result is ∞ of the expected sign. If both operands are infini-
ties of opposite signs, an invalid-operation exception is generated. See Table 3-18.Opcode Instruction 64-Bit 
D8 /0 FADD m32fp Valid Valid Add m32fp to  ST(0) and store result in ST(0).
DC /0 FADD m64fp Valid Valid Add m64fp to  ST(0) and store result in ST(0).
D8 C0+i FADD ST(0), ST(i) Valid Valid Add ST (0) to ST(i) and store result in ST(0).
DC C0+i FADD ST(i), ST(0) Valid Valid Add ST (i) to ST(0) and stor e result in ST(i).
DE C0+i FADDP ST(i), ST(0) Valid Valid Add ST(0) to  ST(i), store result in ST(i), and pop the 
register stack.
DE C1 FADDP Valid Valid Add ST(0) to ST(1),  store result in ST(1), and pop the 
DA /0 FIADD m32int Valid Valid Add m32int to ST(0) and store result in ST(0).
DE /0 FIADD m16int Valid Valid Add m16int to ST(0) and store result in ST(0).FADD/FADDP/FIADD—AddINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-363This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF Instruction = FIADD
THEN
DEST := DEST + ConvertToDoubleExtendedPrecisionFP(SRC);
ELSE (* Source operand is floating-point value *)
FI;
IF Instruction = FADDP 
THEN 
PopRegisterStack;
FI;

Operation
THEN
FI;
THEN 
FI;
#IA Operand is an SNaN value or unsupported format.
Operands are infinities of unlike sign.
#D Source operand is a denormal value.#U Result is too small for destination format.
#O Result is too large for destination format.
#P Value cannot be represented exactly in destination format.Table 3-18.  FADD/FADDP/FIADD Results
DEST
− ∞−  F − 0 + 0 + F + ∞ NaN
− ∞−  ∞−  ∞−  ∞ −  ∞−  ∞ *N a N
− F or − I − ∞−  FS R C S R C ± F or ± 0 + ∞ NaN
SRC −0 − ∞ DEST − 0 ± 0D E S T + ∞ NaN
+ 0 − ∞ DEST ± 0 + 0D E S T + ∞ NaN
+ F or + I − ∞±  F or ± 0S R C S R C + F + ∞ NaN
+ ∞ * + ∞+  ∞+  ∞+  ∞+  ∞ NaN
NaN NaN NaN NaN NaN NaN NaN NaN
NOTES:
F Means finite floating-point value.IM e a n s  i n t e g e r .* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FADD/FADDP/FIADD—AddINSTRUCTION SET REFERENCE, A-L
3-364 Vol. 2AProtected Mode Exceptions
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MF If there is a pending x87 FPU exception.
#UD If the LOCK prefix is used.FBLD—Load Binary Coded DecimalINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-365FBLD—Load Binary Coded Decimal
Converts the BCD source operand into double extended-pre cision floating-point format and pushes the value onto 
the FPU stack. The source operand is loaded without roundin g errors. The sign of the source operand is preserved, 
including that of −0.
The packed BCD digits are assumed to be in the range 0 th rough 9; the instruction does not check for invalid digits 
(AH through FH). Attempting to load an inva lid encoding produces an undefined result.
Operation
TOP := TOP − 1;
ST(0) := ConvertToDoubleE xtendedPrecisionFP(SRC); 
C1 Set to 1 if stack overflow occurred; otherwise, set to 0.
#IS Stack overflow occurred.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code) If a page fault occurs.
#SS If a memory operand effective address is outside the SS segment limit.#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD If the LOCK prefix is used.Opcode Instruction 64-Bit 
DF /4 FBLD m80bcd Valid Valid Convert BCD value to floating-point and push onto the 
FPU stack.FBLD—Load Binary Coded DecimalINSTRUCTION SET REFERENCE, A-L
3-366 Vol. 2ACompatibility Mode Exceptions
#MF If there is a pending x87 FPU exception.#PF(fault-code) If a page fault occurs.
#UD If the LOCK prefix is used.FBSTP—Store BCD Integer and PopINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-367FBSTP—Store BCD Integer and Pop
Converts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination 
operand, and pops the register stack. If the source value is  a non-integral value, it is rounded to an integer value, 
according to rounding mode specified by the RC field of  the FPU control word. To pop the register stack, the 
processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The destination operand specifies the address where the firs t byte destination value is to be stored. The BCD value 
(including its sign bit) requir es 10 bytes of space in memory. 
The following table shows the results obtained when stor ing various classes of numbers in packed BCD format.
If the converted value is too large for the destin ation format, or if the source operand is an ∞, SNaN, QNAN, or is in 
an unsupported format, an invalid-arithmetic-operand condit ion is signaled. If the invalid-operation exception is 
not masked, an invalid-arithmetic-operand exception (#IA) is  generated and no value is stored in the destination 
operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory.
Operation
DEST := BCD(ST(0));
C0, C2, C3 Undefined.Opcode Instruction 64-Bit 
DF /6 FBSTP m80bcd Valid Valid Store ST(0) in m80bcd and pop ST(0).
Table 3-19.  FBSTP Results
ST(0) DEST
− ∞ or Value Too Large for DEST Format *
F ≤ − 1 − D
−1 < F < -0 **
− 0 − 0
+ 0 + 0
+ 0 < F < +1 **
F ≥ +1 + D
+ ∞ or Value Too Large for DEST Format *
NaN *
NOTES:
F Means finite floating-point value.
D Means packed-BCD number.* Indicates floating-point invalid-operation (#IA) exception.
**±0 or ±1, depending on the rounding mode.FBSTP—Store BCD Integer and PopINSTRUCTION SET REFERENCE, A-L
3-368 Vol. 2AFloating-Point Exceptions
#IA Converted value that exceeds 18 BCD digits in length.
Source operand is an SNaN, QNaN, ±∞, or in an unsupported format.
#GP(0) If a segment register is being loaded with a segment selector that points to a non-writable 
segment.

#UD If the LOCK prefix is used.FCHS—Change SignINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-369FCHS—Change Sign
Complements the sign bit of ST(0). This operation change s a positive value into a negative value of equal magni-
tude or vice versa. The following table shows the results obtained when changing the sign of various classes of 
numbers.
Operation
SignBit(ST(0)) := NO T (SignBit(ST(0)));
C1 Set to 0.
D9 E0 FCHS Valid Valid Complements sign of ST(0).
Table 3-20.  FCHS Results
− ∞ + ∞
− F + F
− 0 + 0
+ 0 − 0
+ F − F
+ ∞ − ∞
NaN NaN NOTES:
* F means finite floating-point value.FCHS—Change SignINSTRUCTION SET REFERENCE, A-L
3-370 Vol. 2A64-Bit Mode Exceptions
Same exceptions as in protected mode.FCLEX/FNCLEX—Clear ExceptionsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-371FCLEX/FNCLEX—Clear Exceptions
Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the 
stack fault flag (SF), and the busy fl ag (B) in the FPU status word. The FCLEX instruction checks for and handles 
any pending unmasked floating-point exceptions before cl earing the exception flags; the FNCLEX instruction does 
not.
The assembler issues two instructions for the FCLEX in struction (an FWAIT instruction followed by an FNCLEX 
instruction), and the processor executes each of these instructions separately. If an exception is generated for 
either of these instructions, the save EIP points to the instruction that caused the exception.
When operating a Pentium or Intel486 processor in MS-D OS* compatibility mode, it is possible (under unusual 
circumstances) for an FNCLEX instruction to be interrupted  prior to being executed to handle a pending FPU excep-
tion. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Vo lume 1, for a description of these circumstances. An 
FNCLEX instruction cannot be interrupted  in this way on later Intel processors, except for the Intel QuarkTM X1000 
This instruction affects only the x87 FPU floating-point exce ption flags. It does not affect the SIMD floating-point 
exception flags in the MXCSR register.
Operation
FPUStatusWord[0:7] := 0;
FPUStatusWord[15] := 0;
The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are 
None.
Same exceptions as in protected mode.Opcode1Instruction 64-Bit 
9B DB E2 FCLEX Valid Valid Clear floating-point exception flags after checking for 
pending unmasked floating-point exceptions.
DB E2 FNCLEX1
NOTES:
1. See IA-32 Architecture Compatibility section below.Valid Valid Clear floating-point exce ption flags withou t checking for 
pending unmasked floating-point exceptions.FCLEX/FNCLEX—Clear ExceptionsINSTRUCTION SET REFERENCE, A-L
3-372 Vol. 2AVirtual-8086 Mode Exceptions
Same exceptions as in protected mode.FCMOVcc—Floating-Point Conditional MoveINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-373FCMOV cc—Floating-Point Conditional Move
Tests the status flags in the EFLAGS register and moves the source operand (second operand) to the destination 
operand (first operand) if the given test condition is true . The condition for each mnemonic os given in the Descrip-
tion column above and in Chapter 8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
1. The source operand is always in the ST(i) regi ster and the destination operand is always ST(0).
The FCMOV cc instructions are useful for optimizing small IF constructions. They also help eliminate branching over-
head for IF operations and the possibility of branch mispredictions by the processor. 
A processor may not support the FCMOV cc instructions. Software can check if the FCMOV cc instructions are 
supported by checking the processor’s feature informat ion with the CPUID instruction (see “COMISS—Compare 
Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS” in this chapter) . If both the CMOV and FPU 
feature bits are set, the FCMOV cc instructions are supported.
The FCMOVcc instructions were introduced to the IA-32 Arch itecture in the P6 family processors and are not avail-
able in earlier IA-32 processors.
Operation
THEN ST(0) := ST(i);
FI;
Integer Flag s Affected
None.Opcode1
NOTES:
1. See IA-32 Architecture Compatibility section below.Instruction 64-Bit 
Leg Mode1Description
DA C0+i FCMOVB ST(0), ST(i) Val id Valid Move if below (CF=1).
DA C8+i FCMOVE ST(0), ST(i) Val id Valid Move if equal (ZF=1).
DA D0+i FCMOVBE ST(0), ST(i) Valid Valid Move if below or equal (CF=1 or ZF=1).DA D8+i FCMOVU ST(0), ST(i) Valid Valid Move if unordered (PF=1).
DB C0+i FCMOVNB ST(0),  ST(i) Valid Valid Move if not below (CF=0).
DB C8+i FCMOVNE ST(0),  ST(i) Valid Valid Move if not equal (ZF=0).
DB D0+i FCMOVNBE ST(0), ST(i) Valid Valid Move if not below or equal (CF=0 and ZF=0).DB D8+i FCMOVNU ST(0), ST(i) Valid Va lid Move if not unordered (PF=0).FCMOVcc—Floating-Point Conditional MoveINSTRUCTION SET REFERENCE, A-L
3-374 Vol. 2AProtected Mode Exceptions
Same exceptions as in protected mode.FCOM/FCOMP/FCOMPP—Compare Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-375FCOM/FCOMP/FCOMPP—Compare Floating-Point Values
Compares the contents of register ST(0) and source value and sets condition code flags C0, C2, and C3 in the FPU 
status word according to the results (see the table below). The source operand can be a data register or a memory 
location. If no source operand is given, the value in ST(0) is compared with the value in ST(1). The sign of zero is 
ignored, so that –0.0 is equal to  +0.0. 
This instruction checks the class of the numbers being compared (see “FXAM—Examine Floating-Point” in this 
chapter). If either operand is a NaN or is in an unsupp orted format, an invalid-arithmetic-operand exception (#IA) 
is raised and, if the exception is masked, the condition flags are set to “unordered.” If the invalid-arithmetic-
operand exception is unmasked, the condition code flags are not set.
The FCOMP instruction pops the register stack following  the comparison operation and the FCOMPP instruction 
pops the register stack twice following the comparison op eration. To pop the register stack, the processor marks 
the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The FCOM instructions perform the sa me operation as the FUCOM instructions. The only difference is how they 
handle QNaN operands. The FCOM instru ctions raise an invalid-arithmetic-oper and exception (#IA) when either or 
both of the operands is a NaN value or is in an unsu pported format. The FUCOM instructions perform the same 
operation as the FCOM instructions, except that they do not generate an invalid-arithmetic-operand exception for 
QNaNs.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.Opcode Instruction 64-Bit 

QNaNs.
D8 /2 FCOM m32fp Valid Valid Compare ST(0) with m32fp.
DC /2 FCOM m64fp Valid Valid Compare ST(0) with m64fp.D8 D0+i FCOM ST(i) Valid Vali d Compare ST(0) with ST(i).
D8 D1 FCOM Valid Valid Comp are ST(0) with ST(1).
D8 /3 FCOMP m32fp Valid Valid Compare ST(0) with m32fp and pop register stack.DC /3 FCOMP m64fp Valid Valid Compare ST(0) with m64fp and pop register stack.D8 D8+i FCOMP ST(i) Valid Valid Compare ST (0) with ST(i) and pop register stack.
D8 D9 FCOMP Valid Valid Compare ST(0) with ST(1) and pop register stack.
DE D9 FCOMPP Valid Valid Co mpare ST(0) with ST(1) and pop register stack 
twice.
Table 3-21.  FCOM/FCOMP/FCOMPP Results
ST(0)  > SRC 0 0 0
ST(0)  < SRC 0 0 1
ST(0)  = SRC 1 0 0
Unordered* 1 1 1
NOTES:
* Flags not set if unmasked invalid-arithm etic-operand (#IA) exception is generated.FCOM/FCOMP/FCOMPP—Compare Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-376 Vol. 2AOperation
CASE (relation of operands) OF
ST > SRC: C3, C2, C0 := 000;
ST < SRC: C3, C2, C0 := 001;
ST = SRC: C3, C2, C0 := 100;
ESAC;
IF ST(0) or SRC = NaN or unsupported format
THEN 
#IAIF FPUControlWord.IM 
= 1
THEN 
C3, C2, C0 := 111;
FI;
FI;
IF Instruction = FCOMP 
THEN 
FI;
IF Instruction = FCOMPP 
THEN 
PopRegisterStack;PopRegisterStack;
FI;
C1 Set to 0.
C0, C2, C3 See table on previous page.
#IS Stack underflow occurred.#IA One or both operands are NaN values or have unsupported formats.
Register is marked empty.
#D One or both operands are denormal values.
#UD If the LOCK prefix is used.FCOM/FCOMP/FCOMPP—Compare Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-377Virtual-8086 Mode Exceptions
#MF If there is a pending x87 FPU exception.
#UD If the LOCK prefix is used.FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-L
3-378 Vol. 2AFCOMI/FCOMIP/  FUCOMI/FUCOMIP—Compare Floating -Point Values and Set EFLAGS
Performs an unordered comparison of the contents of regi sters ST(0) and ST(i) and sets the status flags ZF, PF, and 
CF in the EFLAGS register according to the results (see the table below). The sign of zero is ignored for compari-
sons, so that –0.0 is equal to +0.0. 
An unordered comparison checks the class of the numb ers being compared (see “FXAM—Examine Floating-Point” 
in this chapter). The FUCOMI/FUCOMIP instructions perf orm the same operations as the FCOMI/FCOMIP instruc-
tions. The only difference is that the FUCOMI/FUCOMIP in structions raise the invalid-arithmetic-operand exception 
(#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition code flags to be set to unordered, but do not cause an exception to be generated. The FCOMI/FCOMIP instructions 
raise an invalid-operation exception when either or both of  the operands are a NaN value of any kind or are in an 
unsupported format.
If the operation results in an invalid-arithmetic-operand  exception being raised, the status flags in the EFLAGS 
register are set only if the exception is masked. 
The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions set the OF, SF, and AF flags to zero in the EFLAGS register 
(regardless of whether an invalid-operation exception is detected).
The FCOMIP and FUCOMIP instructions also pop the register  stack following the comparison operation. To pop the 
register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were intr oduced to the IA-32 Architecture in the P6 family 
processors and are not available in earlier IA-32 processors. Opcode Instruction 64-Bit 
DB F0+i FCOMI ST, ST(i) Valid Vali d Compare ST(0) with ST(i) and set status flags accordingly.
DF F0+i FCOMIP ST, ST(i) Valid Vali d Compare ST(0) with ST(i), set status flags accordingly, and 
pop register stack.
DB E8+i FUCOMI ST, ST(i) Valid Valid Compare ST(0) with ST(i), check for ordered values, and set 
status flags accordingly.
DF E8+i FUCOMIP ST, ST(i) Valid Valid Compare ST(0 ) with ST(i), check fo r ordered values, set 
status flags accordingly, and pop register stack.
Table 3-22.  FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results
Comparison Results* ZF PF CF
ST0 > ST(i) 0 0 0
ST0 < ST(i) 0 0 1
ST0 = ST(i) 1 0 0
Unordered** 1 1 1
NOTES:
* See the IA-32 Architecture Compatibility section below.
** Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-379Operation
ST(0) > ST(i): ZF, PF, CF := 000;
ST(0) < ST(i): ZF, PF, CF := 001;
ST(0) = ST(i): ZF, PF, CF := 100;
ESAC;
IF Instruction is FCOMI or FCOMIP
THEN
IF ST(0) or ST(i) = NaN or unsupported format
THEN 
= 1
THEN 
ZF, PF, CF := 111;
FI;
FI;
FI;
IF Instruction is FUCOMI or FUCOMIP
THEN
IF ST(0) or ST(i) = QNaN, but not SNaN or unsupported format
THEN 
ELSE (* ST(0) or ST(i) is SN aN or unsupported format *)
 #IA;IF FPUControlWord.IM 
= 1
THEN 
FI;
FI;
FI;
IF Instruction is FCOMIP or FUCOMIP 
THEN 
FI;
C1 Set to 0.
C0, C2, C3 Not affected.
#IS Stack underflow occurred.#IA (FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported 
formats.
(FUCOMI or FUCOMIP instruction) One or both op erands are SNaN values (but not QNaNs) or 
have undefined formats. Detection of a QNaN value does not raise an invalid-operand excep-tion.FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-L
3-380 Vol. 2AProtected Mode Exceptions
#MF If there is a pending x87 FPU exception.#UD If the LOCK prefix is used.
Same exceptions as in protected mode.FCOS—CosineINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-381FCOS—Cosine
Computes the approximate cosine of th e source operand in register ST(0) and stores the result in ST(0). The 
source operand must be given in radians and must be within the range −263 to +263. The following table shows the 
results obtained when taking the cosine of various classes of numbers.
If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in 
register ST(0) remains unchanged. The in struction does not raise an exception when the source operand is out of 
range. It is up to the program to check the C2 flag fo r out-of-range conditions. Source values outside the range −
263 to +263 can be reduced to the range of the instruction by  subtracting an appropriate integer multiple of 2 π. 
However, even within the range -263 to +263, inaccurate results can occur because the finite approximation of π 
used internally for argument reduction is not sufficient in al l cases. Therefore, for accurate results it is safe to apply 
FCOS only to arguments reduced accurately in soft ware, to a value smaller in absolute value than 3 π/8. See the

FCOS only to arguments reduced accurately in soft ware, to a value smaller in absolute value than 3 π/8. See the 
sections titled “Approximation of Pi” and “Transcend ental Instruction Accuracy” in Chapter 8 of the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 1, for a discussion of the proper value to use for π in 
performing such reductions.
Operation
IF |ST(0)| < 263
THEN
C2 := 0;ST(0) := FCOS(ST(0)); // approximation of cosine
ELSE (* Source operand is out-of-range *)
C2 := 1;
FI;Opcode Instruction 64-Bit 
D9 FF FCOS Valid Valid Replace ST(0) with its approximate cosine.
Table 3-23.  FCOS Results
− ∞ *
− F −1 to +1
− 0 + 1
+ 0 + 1
+ F − 1 to + 1
+ ∞ *
NaN NaN 
NOTES:
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FCOS—CosineINSTRUCTION SET REFERENCE, A-L
3-382 Vol. 2AFPU Flags Affected
Set if result was rounded up; cleared otherwise.Undefined if C2 is 1.
C2 Set to 1 if outside range ( −2
63 < source operand < +263); otherwise, set to 0.
C0, C3 Undefined.
#IA Source operand is an SNaN value, ∞, or unsupported format.
#D Source is a denormal value.#P Value cannot be represented exactly in destination format.
Same exceptions as in protected mode.FDECSTP—Decrement Stack-Top PointerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-383FDECSTP—Decrement Stack-Top Pointer
Subtracts one from the TOP field of the FPU status word (decrements the top-of-stack pointer). If the TOP field 
contains a 0, it is set to 7. The effect of this instructio n is to rotate the stack by one position. The contents of the 
FPU data registers and tag register are not affected. 
Operation
IF TOP = 0
THEN TOP := 7;ELSE TOP := TOP – 1;
FI;
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.
None.
D9 F6 FDECSTP Valid Valid Decrement TOP field in FPU status word.FDIV/FDIVP/FIDIV—DivideINSTRUCTION SET REFERENCE, A-L
3-384 Vol. 2AFDIV/FDIVP/FIDIV—Divide
Divides the destination operand by the source operand and stores the result in the destination location. The desti-
nation operand (dividend) is always in an FPU register; th e source operand (divisor) can be a register or a memory 
location. Source operands in memory can be in single prec ision or double precision floating-point format, word or 
doubleword integer format.
The no-operand version of the instruction divides the conten ts of the ST(1) register by the contents of the ST(0) 
register. The one-operand version divides the contents of th e ST(0) register by the contents of a memory location 
(either a floating-point or an integer value). The two-operan d version, divides the contents of the ST(0) register by 
the contents of the ST(i) register or vice versa.
The FDIVP instructions perform the additional operation of  popping the FPU register stack after storing the result. 
by 1. The no-operand version of the floating-point divide  instructions always results in the register stack being 
popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.
The FIDIV instructions convert an integer source operan d to double extended-precision floating-point format 
before performing the division. When the source operand is an integer 0, it is treated as a +0.
If an unmasked divide-by-zero exception (#Z) is generate d, no result is stored; if the exception is masked, an ∞ of 
the appropriate sign is stored in the destination operand.
The following table shows the results obtained when dividi ng various classes of numbers, assuming that neither 
overflow nor underflow occurs.Opcode Instruction 64-Bit 
D8 /6 FDIV m32fp Valid Valid Divide ST(0) by m32fp and store result in ST(0).
DC /6 FDIV m64fp Valid Valid Divide ST(0) by m64fp and store result in ST(0).
D8 F0+i FDIV ST(0), ST(i) Valid Valid Divide ST(0) by ST(i) and store result in ST(0).
DC F8+i FDIV ST(i), ST(0) Valid Valid Divide ST(i) by ST(0) and store result in ST(i).
DE F8+i FDIVP ST(i), ST(0) Valid Va lid Divide ST(i) by ST(0), store result in ST(i), and pop the 
DE F9 FDIVP Valid Valid Divide ST(1) by ST (0), store result in ST(1), and pop 
the register stack.
DA /6 FIDIV m32int Valid Valid Divide ST(0) by m32int and store result in ST(0).
DE /6 FIDIV m16int Valid Valid Divide ST(0) by m16int and store result in ST(0).FDIV/FDIVP/FIDIV—DivideINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-385This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF SRC = 0
THEN
#Z;
ELSE
IF Instruction is FIDIV
THEN
DEST := DEST / ConvertToDoubleExtendedPrecisionFP(SRC);
DEST := DEST / SRC;
FI;
FI;
IF Instruction = FDIVP 
THEN 
FI;
C0, C2, C3 Undefined.Table 3-24.  FDIV/FDIVP/FIDIV Results
DEST
− ∞ − F − 0 + 0 + F + ∞ NaN
− ∞ * + 0 + 0 − 0 − 0* N a N
− F + ∞ + F + 0 − 0 − F − ∞ NaN
− I + ∞ + F + 0 − 0 − F − ∞ NaN
SRC − 0 + ∞ ** * * ** − ∞ NaN
+ 0 − ∞ ** * * ** + ∞ NaN
+ I − ∞ − F − 0 + 0 + F + ∞ NaN
+ F − ∞ − F − 0 + 0 + F + ∞ NaN
+ ∞ * − 0 − 0 + 0 + 0* N a N
NOTES:
IM e a n s  i n t e g e r .
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.** Indicates floating-point zero-divide (#Z) exception.FDIV/FDIVP/FIDIV—DivideINSTRUCTION SET REFERENCE, A-L
3-386 Vol. 2AFloating-Point Exceptions
±∞ / ±∞ ; ±0 / ±0
#D Source is a denormal value.
#Z DEST / ±0, where DEST is not equal to ±0.
#UD If the LOCK prefix is used.FDIVR/FDIVRP/FIDIVR—Reverse DivideINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-387FDIVR/FDIVRP/FIDIVR—Reverse Divide
Divides the source operand by the destination operand and stores the result in the destination location. The desti-

nation operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory 
location. Source operands in memory can be in single precision or double precision floating-point format, word or 
These instructions perform the reverse operations of the FD IV, FDIVP, and FIDIV instructions. They are provided to 
support more efficient coding.
The no-operand version of the instruction divides the conten ts of the ST(0) register by the contents of the ST(1) 
register. The one-operand version divides the contents of a memory location (either a floating-point or an integer 
value) by the contents of the ST(0) register. The two-operan d version, divides the contents of the ST(i) register by 
the contents of the ST(0) register or vice versa.
The FDIVRP instructions perform the additional operation of  popping the FPU register stack after storing the result. 
popped. In some assemblers, the mnemonic for th is instruction is FDIVR rather than FDIVRP.
The FIDIVR instructions convert an integer source operan d to double extended-precision floating-point format 
before performing the division.
If an unmasked divide-by-zero exception (#Z) is generated,  no result is stored; if the exception is masked, an ∞ of 
D8 /7 FDIVR m32fp Valid Valid Divide m32fp by ST(0) and store result in ST(0).
DC /7 FDIVR m64fp Valid Valid Divide m64fp by ST(0) and store result in ST(0).
D8 F8+i FDIVR ST(0), ST(i) Val id Valid Divide ST(i) by ST(0) and store result in ST(0).
DC F0+i FDIVR ST(i), ST(0) Valid Valid Divide ST(0) by ST(i) and store result in ST(i).
DE F0+i FDIVRP ST(i), ST(0) Valid Valid Divide ST(0) by ST (i), store result in ST(i), and pop the 
DE F1 FDIVRP Valid Valid Divide ST(0) by ST(1 ), store result in ST(1), and pop the 
DA /7 FIDIVR m32int Valid Val id Divide m32int by ST(0) and store result in ST(0).
DE /7 FIDIVR m16int Valid Valid Divide m16i nt by ST(0) and store result in ST(0).FDIVR/FDIVRP/FIDIVR—Reverse DivideINSTRUCTION SET REFERENCE, A-L
3-388 Vol. 2AWhen the source operand is an integer 0, it is treated as a +0. This instruction’s operation is the same in non-64-bit 
modes and 64-bit mode.
Operation
IF DEST = 0
THEN
#Z;
ELSE
IF Instruction = FIDIVR
THEN
DEST := ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;
DEST := SRC / DEST;
FI;
FI;
IF Instruction = FDIVRP 
THEN 
FI;
C0, C2, C3 Undefined.Table 3-25.  FDIVR/FDIVRP/FIDIVR Results
DEST
− ∞ * + ∞ + ∞ − ∞ − ∞ *N a N
SRC − F + 0 + F* ** * − F − 0N a N
− I + 0 + F* ** * − F − 0N a N
− 0 + 0 + 0* * − 0 − 0N a N
+ 0 − 0 − 0* * + 0 + 0N a N
+ I − 0 − F* ** * + F + 0N a N
+ F − 0 − F* ** * + F + 0N a N
+ ∞ * − ∞ − ∞ + ∞ + ∞ *N a N
NOTES:
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.** Indicates floating-point zero-divide (#Z) exception.FDIVR/FDIVRP/FIDIVR—Reverse DivideINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-389Floating-Point Exceptions
#Z SRC / ±0, where SRC is not equal to ±0.
#UD If the LOCK prefix is used.FFREE—Free Floating-Point RegisterINSTRUCTION SET REFERENCE, A-L
3-390 Vol. 2AFFREE—Free Floating-Point Register
Sets the tag in the FPU tag register associated with regist er ST(i) to empty (11B). The contents of ST(i) and the FPU 
stack-top pointer (TOP) are not affected.
Operation
TAG(i) := 11B;
C0, C1, C2, C3 undefined.
None
DD C0+i FFREE ST(i) Valid Valid Sets tag for ST(i) to empty.FICOM/FICOMP—Compare IntegerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-391FICOM/FICOMP—Compare Integer
Compares the value in ST(0) with an integer source operand and sets the co ndition code flags C0, C2, and C3 in 
the FPU status word according to the results (see table be low). The integer value is converted to double extended-
precision floating-point format before the comparison is made.
These instructions perform an “unordered comparison.” An unordered comparison also checks the class of the 
numbers being compared (see “FXAM—Examine Floating-Point” in  this chapter). If either operand is a NaN or is in 
an undefined format, the condition flags are set to “unordered.”
The sign of zero is ignored, so that –0.0  := +0.0.
The FICOMP instructions pop the register stack following the comparison. To pop the register stack, the processor 
marks the ST(0) register empty and increments the stack pointer (TOP) by 1.
Operation
ST(0) > SRC: C3, C2, C0 := 000;ST(0) < SRC: C3, C2, C0 := 001;ST(0) 
= SRC: C3, C2, C0 := 100;
Unordered: C3, C2, C0 := 111;
ESAC;
IF Instruction = FICOMP 
THEN 
PopRegisterStack; 
FI;
C1 Set to 0.
#IA One or both operands are NaN values or have unsupported formats.
#D One or both operands are denormal values.Opcode Instruction 64-Bit 
DE /2 FICOM m16int Valid Valid Compare ST(0) with m16int.
DA /2 FICOM m32int Valid Valid Compare ST(0) with m32int.DE /3 FICOMP m16int Valid Valid Compare ST(0) with m16int and pop stack register.DA /3 FICOMP m32int Valid Valid Compare ST(0) with m32int and pop stack register.
Table 3-26.  FICOM/FICOMP Results
ST(0) > SRC 0 0 0
ST(0) = SRC 1 0 0
Unordered 1 1 1FICOM/FICOMP—Compare IntegerINSTRUCTION SET REFERENCE, A-L
3-392 Vol. 2AProtected Mode Exceptions

#UD If the LOCK prefix is used.FILD—Load IntegerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-393FILD—Load Integer
Converts the signed-integer source operand into double extended-precision floating-point format and pushes the 
value onto the FPU register stack. The source operand can be  a word, doubleword, or quadword integer. It is loaded 
without rounding errors. The sign of  the source operand is preserved.
Operation
ST(0) := ConvertToDoubleE xtendedPrecisionFP(SRC);
C1 Set to 1 if stack overflow occurred; set to 0 otherwise.
DF /0 FILD m16int Valid Valid Push m16int onto the FPU register stack.
DB /0 FILD m32int Valid Valid Push m32int onto the FPU register stack.DF /5 FILD m64int Valid Valid Push m64int onto the FPU register stack.FILD—Load IntegerINSTRUCTION SET REFERENCE, A-L
3-394 Vol. 2ACompatibility Mode Exceptions
#UD If the LOCK prefix is used.FINCSTP—Increment Stack-Top PointerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-395FINCSTP—Increment Stack-Top Pointer
Adds one to the TOP field of the FPU status word (increme nts the top-of-stack pointer). If the TOP field contains a 
7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected. This operation is not equivalent to popping the stack, because the tag 
for the previous top-of-stack register is not marked empty.
Operation
IF TOP  = 7
THEN TOP := 0;ELSE TOP := TOP + 1;
FI;
None.
D9 F7 FINCSTP Valid Valid Increment the TOP field in the FPU status register.FINIT/FNINIT—Initialize Floating-Point UnitINSTRUCTION SET REFERENCE, A-L
3-396 Vol. 2AFINIT/FNINIT—Initializ e Floating-Point Unit
Sets the FPU control, status, tag, instruction pointer, an d data pointer registers to their default states. The FPU 
control word is set to 037FH (round to nearest, all except ions masked, 64-bit precision). The status word is cleared 
(no exception flags set, TOP is set to 0). The data register s in the register stack are left unchanged, but they are all 
tagged as empty (11B). Both the inst ruction and data pointers are cleared.
The FINIT instruction checks for and handles any pending unmasked floating-point exceptions before performing 
the initialization; the FNINIT instruction does not.
The assembler issues two instructions for the FINIT instruction (an FWAIT instruction followed by an FNINIT 
instruction), and the processor executes each of these inst ructions in separately. If an exception is generated for 
When operating a Pentium or Intel486 processor in MS -DOS compatibility mode, it is possible (under unusual 
circumstances) for an FNINIT instruction to be interrupted  prior to being executed to handle a pending FPU excep-
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An 
FNINIT instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000 
In the Intel387 math coprocessor, the FINIT/FNINIT inst ruction does not clear the instruction and data pointers.
This instruction affects only the x87 FPU. It does not affect the XMM and MXCSR registers.
Operation
FPUControlWord := 037FH;
FPUStatusWord := 0;FPUTagWord := FFFFH;FPUDataPointer := 0;FPUInstructionPointer := 0;FPULastInstructionOpcode := 0;
C0, C1, C2, C3 set to 0.
None.Opcode Instruction 64-Bit 
9B DB E3 FINIT Valid Valid Initialize FPU after checking for pending unmasked 
floating-point exceptions.
DB E3 FNINIT1
NOTES:
1. See IA-32 Architecture Compatibility section below.Valid Valid Initialize FPU without checking for pending unmasked 
floating-point exceptions.FINIT/FNINIT—Initialize Floating-Point UnitINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-397Protected Mode Exceptions
Same exceptions as in protected mode.FIST/FISTP—Store IntegerINSTRUCTION SET REFERENCE, A-L
3-398 Vol. 2AFIST/FISTP—Store Integer
The FIST instruction converts the value in the ST(0) register to a signed inte ger and stores the result in the desti-
nation operand. Values can be stored in word or double word integer format. The dest ination operand specifies the 
address where the first byte of the destination value is to be stored.
The FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop

The FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop 
the register stack, the processor marks the ST(0) register  as empty and increments the stack pointer (TOP) by 1. 
The FISTP instruction also stores values in quadword integer format.
The following table shows the results obtained when st oring various classes of numbers in integer format.
If the source value is a non-integral va lue, it is rounded to an integer valu e, according to the rounding mode spec-
ified by the RC field of the FPU control word. 
not masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination operand. If the invalid-operation exception is masked , the integer indefinite value is stored in memory.
DF /2 FIST m16int Valid Valid Store ST(0) in m16int.
DB /2 FIST m32int Valid Valid Store ST(0) in m32int.DF /3 FISTP m16int Valid Valid Store ST(0) in m16int and pop register stack.DB /3 FISTP m32int Valid Valid Store ST(0) in m32int and pop register stack.DF /7 FISTP m64int Valid Valid Store ST(0) in m64int and pop register stack.
Table 3-27.  FIST/FISTP Results 
ST(0) DEST
F ≤ −1 − I
−1 < F < −0 **
− 00
+ 00
+ 0 < F < + 1 **
F ≥ + 1 + I
NaN *
NOTES:
F Means finite floating-point value.IM e a n s  i n t e g e r .
* Indicates floating-point invalid-operation (#IA) exception.
** 0 or ±1, depending on the rounding mode.FIST/FISTP—Store IntegerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-399Operation
DEST := Integer(ST(0));
IF Instruction = FISTP 
THEN 
FI;
Indicates rounding direction of if the inexact exception (#P) is generated: 0  := not roundup; 1  
:= roundup.
Set to 0 otherwise.
#IS Stack underflow occurred.#IA Converted value is too large for the destination format.
Source operand is an SNaN, QNaN, ±∞, or unsupported format.
selector.
3-400 Vol. 2A64-Bit Mode Exceptions
#GP(0) If the memory address is in a non-canonical form.#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD If the LOCK prefix is used.FISTTP—Store Integer With TruncationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-401FISTTP—Store Integer With Truncation
FISTTP converts the value in ST into a signed intege r using truncation (chop) as rounding mode, transfers the 
result to the destination, and pop ST. FISTTP accepts word, short integer, and long integer destinations.
Operation
DEST := ST;
pop ST;
C1 is cleared; C0, C2, C3 undefined.
Numeric Exceptions
Invalid, Stack Invalid (stack underflow), Precision.
#GP(0) If the destination is in a nonwritable segment.
For an illegal memory operand effective addr ess in the CS, DS, ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.#PF(fault-code) For a page fault.
#NM If CR0.EM[bit 2] = 1.
If CR0.TS[bit 3] = 1.
#UD If CPUID.01H:ECX.SSE3[bit 0] = 0.
If the LOCK prefix is used.Opcode Instruction 64-Bit Mode Compat/
DF /1 FISTTP m16int Valid Valid Store ST(0) in m16int with truncation.
DB /1 FISTTP m32int Valid Valid Store ST(0) in m32int with truncation.DD /1 FISTTP m64int Valid Valid Store ST(0) in m64int with truncation.
Table 3-28.  FISTTP Results
ST(0) DEST
− ∞ or  Value Too Larg e for DEST Format *
F≤ − 1 − I
− 1<F<+ 1 0
FŠ+ 1 + I
NaN *
NOTES:
ΙMeans integer.
∗Indicates floating-point invalid-operation (#IA) exception.FISTTP—Store Integer With TruncationINSTRUCTION SET REFERENCE, A-L
3-402 Vol. 2AReal Address Mode Exceptions
GP(0) If any part of the operand would lie outsid e of the effective address space from 0 to 0FFFFH.
#AC(0) For unaligned memory reference if the current privilege is 3.
If the LOCK prefix is used.FLD—Load Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-403FLD—Load Floating-Point Value
Pushes the source operand onto the FPU register stack. The source operand can be in  single precision, double 
precision, or double extended-precision floating-point format . If the source operand is in single precision or double 
precision floating-point format, it is automatically converte d to the double extended-precision floating-point format 
before being pushed on the stack.
The FLD instruction can also push the value in a selected FP U register [ST(i)] onto the stack. Here, pushing register 
ST(0) duplicates the stack top.
NOTE
When the FLD instruction loads a denormal value and the DM bit in the CW is not masked, an exception is flagged but the value is still pushed onto the x87 stack.
Operation
IF SRC is ST(i)
THEN
temp := ST(i);
FI;
TOP := TOP  − 1;
IF SRC is memory-operand
THEN
ST(0) := ConvertToDoubleExtendedPrecisionFP(SRC);
ELSE (* SRC is ST(i) *)
ST(0) := temp;
FI;
#IS Stack underflow or overflow occurred.
#IA Source operand is an SNaN. Does not occur if the source operand is in double extended-preci-
sion floating-point format (FLD m80fp or FLD ST(i)).
#D Source operand is a denormal value. Does not occur if the source operand is in double 
extended-precision floating-point format.Opcode Instruction 64-Bit 
D9 /0 FLD m32fp Valid Valid Push m32fp onto the FPU register stack.
DD /0 FLD m64fp Valid Valid Push m64f p onto the FPU register stack.
DB /5 FLD m80fp Valid Valid Push m80fp onto the FPU register stack.D9 C0+i FLD ST(i) Valid Valid Push ST(i) onto the FPU register stack.FLD—Load Floating-Point ValueINSTRUCTION SET REFERENCE, A-L

FI;
THEN
FI;
3-404 Vol. 2AProtected Mode Exceptions
#GP(0) If destination is located in a non-writable segment.
selector.
#UD If the LOCK prefix is used.FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load ConstantINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-405FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG 2/FLDLN2/FLDZ—Load Constant
Push one of seven commonly used constants (in double ex tended-precision floating-point format) onto the FPU 
register stack. The constants that can be loaded with these instructions include +1.0, +0.0, log210, log2e, π, log102, 
and loge2. For each constant, an internal 66-bit constant is rounded (as specified by the RC field in the FPU control 
word) to double extended-precision floating-point format. The inexact-result exception (#P) is not generated as a 
result of the rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up. 
See the section titled “Approximation  of Pi” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 1, for a description of the π constant.
When the RC field is set to round-to-nearest, the FPU prod uces the same constants that is produced by the Intel 
8087 and Intel 287 math coprocessors.
Operation
ST(0) := CONSTANT;
Same exceptions as in protected mode.Opcode* Instruction 64-Bit 
D9 E8 FLD1 Valid Valid Push +1.0 onto the FPU register stack.
D9 E9 FLDL2T Valid Valid Push log210 onto the FPU register stack.
D9 EA FLDL2E Valid Valid Push log2e onto the FPU register stack.
D9 EB FLDPI Valid Valid Push π onto the FPU register stack.
D9 EC FLDLG2 Valid Valid Push log102 onto the FPU register stack.
D9 ED FLDLN2 Valid Valid Push loge2 onto the FPU register stack.
D9 EE FLDZ Valid Valid Push +0.0 onto the FPU register stack.
NOTES:
* See IA-32 Architecture Compatibility section below.FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load ConstantINSTRUCTION SET REFERENCE, A-L
3-406 Vol. 2AVirtual-8086 Mode Exceptions
Same exceptions as in protected mode.FLDCW—Load x87 FPU Control WordINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-407FLDCW—Load x87 FPU Control Word
Loads the 16-bit source operand into the FPU control word . The source operand is a memory location. This instruc-
tion is typically used to establish or change the FPU’s mode of operation.
If one or more exception flags are set in the FPU status word prior to loading a new FPU control word and the new 
control word unmasks one or more of those exceptions, a floating-point exception will be generated upon execution of the next floating-point instruction (except for the no-wai t floating-point instructions, see the section titled “Soft-
ware Exception Handling” in Chapter 8 of the Intel
Volume 1). To avoid raising exceptions when changing FP U operating modes, clear any pending exceptions (using 
the FCLEX or FNCLEX instruction) be fore loading the new control word.
Operation
FPUControlWord := SRC;
None; however, this operation might unmask a pending exce ption in the FPU status word. That exception is then 
generated upon execution of the next “waiting” floating-point instruction.
selector.
D9 /5 FLDCW m2byte Valid Valid Load FPU control word from m2byte.FLDCW—Load x87 FPU Control WordINSTRUCTION SET REFERENCE, A-L
3-408 Vol. 2AVirtual-8086 Mode Exceptions
#UD If the LOCK prefix is used.FLDENV—Load x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-409FLDENV—Load x87 FPU Environment
Loads the complete x87 FPU operating environment from me mory into the FPU registers.  The source operand spec-
ifies the first byte of the operating-environment data in memory. This data is typically written to the specified 
memory location by a FSTENV or FNSTENV instruction.
The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data 
pointer, and last opcode. Figures 8-9 through 8-12 in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, show the layout in memory of the load ed environment, depending on the operating mode of the 
processor (protected or real) and the current operand-size  attribute (16-bit or 32-bit). In virtual-8086 mode, the 
real mode layouts are used.
The FLDENV instruction should be executed in the same  operating mode as the corresponding FSTENV/FNSTENV 
If one or more unmasked exception flags are set in the ne w FPU status word, a floating-point exception will be 
generated upon execution of the next floating-point instru ction (except for the no-wait floating-point instructions, 
see the section titled “Software Exceptio n Handling” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1). To avoid generating exce ptions when loading a new environment, clear all the

Developer’s Manual, Volume 1). To avoid generating exce ptions when loading a new environment, clear all the 
exception flags in the FPU status  word that is being loaded.
If a page or limit fault occurs during the execution of this  instruction, the state of the x87 FPU registers as seen by 
the fault handler may be different than the state being lo aded from memory. In such situations, the fault handler 
should ignore the status of the x87 FP U registers, handle the fault, and re turn. The FLDENV instruction will then 
complete the loading of the x87 FPU register s with no resulting context inconsistency.
Operation
FPUControlWord := SRC[FPUControlWord];
FPUStatusWord := SRC[FPUStatusWord];FPUTagWord := SRC[FPUTagWord];FPUDataPointer := SRC[FPUDataPointer];FPUInstructionPointer := SR C[FPUInstructionPointer];
FPULastInstructionOpcode := SRC[FPULastInstructionOpcode];
The C0, C1, C2, C3 flags are loaded.
None; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next 
“waiting” floating-point instruction.Opcode Instruction 64-Bit 
D9 /4 FLDENV m14/28byte Valid Valid Load FPU environment from m14byte or m28byte.FLDENV—Load x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-L
3-410 Vol. 2AProtected Mode Exceptions
selector.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#GP(0) If the memory address is in a non-canonical form.#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD If the LOCK prefix is used.FMUL/FMULP/FIMUL—MultiplyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-411FMUL/FMULP/FIMUL—Multiply
Multiplies the destination and source operands and stores  the product in the destination location. The destination 
operand is always an FPU data register; the source oper and can be an FPU data regi ster or a memory location. 
Source operands in memory can be in single precision or  double precision floating-point format or in word or 
The no-operand version of the instruction multiplies the cont ents of the ST(1) register by the contents of the ST(0) 
register and stores the product in the ST(1) register. The one-operand version multiplies the contents of the ST(0) 
register by the contents of a memory location (either a floa ting-point or an integer value) and stores the product in 
the ST(0) register. The two-operand version, multiplies the contents of the ST(0) register by the contents of the 
ST(i) register, or vice versa, with the result being stored in the register specified with the first operand (the desti-
nation operand). 
The FMULP instructions perform the additional operatio n of popping the FPU register stack after storing the 
product. To pop the register stack, the processor mark s the ST(0) register as empty and increments the stack 
pointer (TOP) by 1. The no-operand version of the floating-p oint multiply instructions always results in the register 
stack being popped. In some assemblers, the mnemonic for this instruction is FMUL rather than FMULP.
The FIMUL instructions convert an integer source operand to double extended-
precision floating-point format before performing the multiplication.
The sign of the result is always the exclusive-OR of the so urce signs, even if one or more of the values being multi-
plied is 0 or ∞. When the source operand is an integer 0, it is treated as a +0.
The following table shows the results obtained when multip lying various classes of numbers, assuming that neither 
D8 /1 FMUL m32fp Valid Valid Multiply ST(0) by m32fp and store result in ST(0).
DC /1 FMUL m64fp Valid Valid Multiply ST(0) by m64fp and store result in ST(0).D8 C8+i FMUL ST(0), ST(i) Valid Valid Multiply ST(0) by ST(i) and st ore result in ST(0).
DC C8+i FMUL ST(i), ST(0) Valid Valid Multiply ST(i) by ST(0) and st ore result in ST(i).
DE C8+i FMULP ST(i), ST(0) Valid Valid Multiply ST(i) by ST(0), store result in ST(i), and pop the 
DE C9 FMULP Valid Valid Multiply ST(1) by ST (0), store result in ST(1), and pop 
DA /1 FIMUL m32int Valid Valid Multiply ST(0 ) by m32int and store result in ST(0).
DE /1 FIMUL m16int Valid Valid Multiply ST(0 ) by m16int and store result in ST(0).FMUL/FMULP/FIMUL—MultiplyINSTRUCTION SET REFERENCE, A-L
3-412 Vol. 2AThis instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF Instruction = FIMUL
THEN
DEST := DEST ∗ ConvertToDoubleExten dedPrecisionFP(SRC);
DEST := DEST ∗ SRC;
FI;
IF Instruction = FMULP 
THEN 
FI;
One operand is ±0 and the other is ±∞.
#D Source operand is a denormal value.
#O Result is too large for destination format.#P Value cannot be represented exactly in destination format.Table 3-29.  FMUL/FMULP/FIMUL Results
DEST
− ∞ + ∞ + ∞ ** − ∞ − ∞ NaN
SRC − 0 * + 0 + 0 − 0 − 0 * NaN
+ 0 * − 0 − 0 + 0 + 0 * NaN
+ ∞ − ∞ − ∞ ** +  ∞ + ∞ NaN
NOTES:
IM e a n s  I n t e g e r .
* Indicates invalid-arithmetic-operand (#IA) exception.FMUL/FMULP/FIMUL—MultiplyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-413Protected Mode Exceptions
selector.
#UD If the LOCK prefix is used.FNOP—No OperationINSTRUCTION SET REFERENCE, A-L
3-414 Vol. 2AFNOP—No Operation

Performs no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or 
machine context, except the EIP regi ster and the FPU Instruction Pointer.
None.
D9 D0 FNOP Valid Valid No operation is performed.FPATAN—Partial ArctangentINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-415FPATAN—Partial Arctangent
Computes the arctangent of the source operand in register  ST(1) divided by the source operand in register ST(0), 
stores the result in ST(1), and pops the FPU register stack. The result in register ST(0) has the same sign as the 
source operand ST(1) and a magnitude less than +π.
The FPATAN instruction returns the angle between the X axis and the line from the origin to the point (X,Y), where 
Y (the ordinate) is ST(1) and X (the abscissa) is ST(0). The angle depends on the sign of X and Y independently, 
not just on the sign of the ratio Y/X. This is because a point ( −X,Y) is in the second quadrant, resulting in an angle 
between π/2 and π, while a point (X, −Y) is in the fourth quadrant, resulting in an angle between 0 and −π/2. A point 
(−X,−Y) is in the third quadrant , giving an angle between −π/2 and −π.
The following table shows the results obtained when co mputing the arctangent of various classes of numbers, 
assuming that underflow does not occur.
There is no restriction on the range of source operands that FPATAN can accept.
The source operands for this instruction are restricted  for the 80287 math coprocessor to the following range:
0 ≤ |ST(1)| < |ST(0)| < +∞Opcode1
NOTES:
D9 F3 FPATAN Valid Valid Replace ST(1) with arctan(ST(1) /ST(0)) and pop the register stack.
Table 3-30.  FPATAN Results
ST(0)
− ∞ − 3π/4* − π/2 − π/2 − π/2 − π/2 − π/4* NaN
ST(1) − F- p −π to −π/2 −π/2 −π/2 −π/2 to −0-  0 N a N
− 0- p - p - p * − 0* − 0 − 0N a N
+ 0+ p +  p + π* + 0* + 0 + 0N a N
+ F+ p +π to +π/2 + π/2 +π/2 +π/2 to +0 + 0N a N
+ ∞ +3π/4* +π/2 +π/2 +π/2 + π/2 + π/4* NaN
NOTES:
* Table 8-10 in the Intel® 64 and IA-32 Architectures Software Developer’s Ma nual, Volume 1, specifies that the ratios 0/0 and ∞/∞ 
generate the floating-point invalid arithmetic-operation exception and, if this exception is masked, the floating-point QNaN in defi-
nite value is returned . With the FPATAN inst ruction, the 0/0 or ∞/∞ value is actually not calculated using division. Instead, the arc-
tangent of the two variables is derived from a standard mathematical formulation that is generalized to allow complex numbers a s 
arguments. In this complex variable formulation, arctangent(0,0 ) etc. has well defined values. These values are needed to devel op 
a library to compute transcendental function s with complex arguments, based on the FP U functions that only  allow floating-point  
values as arguments.FPATAN—Partial ArctangentINSTRUCTION SET REFERENCE, A-L
3-416 Vol. 2AOperation
ST(1) := arctan(ST(1) / ST(0));
#IS Stack underflow occurred.#IA Source operand is an SNaN value or unsupported format.#D Source operand is a denormal value.
Same exceptions as in protected mode.FPREM—Partial RemainderINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-417FPREM—Partial Remainder
Computes the remainder obtained from dividing the value in  the ST(0) register (the dividend) by the value in the 
ST(1) register (the divisor or modulus ), and stores the result in ST(0). The remainder represents the following 
value:
Remainder  := ST(0) − (Q ∗ ST(1))
Here, Q is an integer value that is obtained by truncatin g the floating-point number quotient of [ST(0) / ST(1)] 
toward zero. The sign of the remainder is the same as th e sign of the dividend. The magnitude of the remainder is 
less than that of the modulus, unless a partial remainder was computed (as described below).
This instruction produces an exact result; the inexact-re sult exception does not occur and the rounding control has 
no effect. The following table shows the results obtained  when computing the remainder of various classes of 
numbers, assuming that underflow does not occur.
When the result is 0, its sign is the same as that of the dividend. When the modulus is ∞, the result is equal to the 
value in ST(0). 
The FPREM instruction does not compute the remainder sp ecified in IEEE Std 754. The IEEE specified remainder 
can be computed with the FPREM1 instruction. The FPREM instruction is provided for compatibility with the Intel 
8087 and Intel287 math coprocessors.
The FPREM instruction gets its name “partial remainder” because of the way it computes the remainder. This 
instruction arrives at a remainder through iterative subtract ion. It can, however, reduce the exponent of ST(0) by 
no more than 63 in one execution of the instruction. If the instruction succeeds in producing a remainder that is 
less than the modulus, the operation is complete and the C2 flag in the FPU status word is cleared. Otherwise, C2 
is set, and the result in ST(0) is called the partial remainder . The exponent of the partial remainder will be less 
than the exponent of the original divide nd by at least 32. Software can re-execute the instruction (using the partial 
remainder in ST(0) as the dividend) until C2 is cleared.  (Note that while executing such a remainder-computation 
loop, a higher-priority interrupting routine that needs th e FPU can force a context switch in-between the instruc-
tions in the loop.)
An important use of the FPREM instruction is to reduce the arguments of periodic functions. When reduction is 
complete, the instruction stores the three least-significant bi ts of the quotient in the C3, C1, and C0 flags of the FPU Opcode Instruction 64-Bit 
D9 F8 FPREM Valid Valid Replace ST(0) with the remainder obtained from dividing 
ST(0) by ST(1).
Table 3-31.  FPREM Results
ST(1)
-∞ -F -0 +0 +F + ∞ NaN
-∞ *** *** NaN
ST(0) -F ST(0) -F or -0 * * -F or -0 ST(0) NaN
-0 -0 -0 * * -0 -0 NaN
+0 +0 +0 * * +0 +0 NaN
+F ST(0) +F or +0 * * +F or +0 ST(0) NaN
+∞ *** *** NaN
NOTES:
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FPREM—Partial RemainderINSTRUCTION SET REFERENCE, A-L
3-418 Vol. 2Astatus word. This information is important in argument reduction for the tangent function (using a modulus of π/4), 
because it locates the original angle in the correct one of eight sectors of the unit circle.
Operation
D := exponent(ST(0)) – exponent(ST(1));
IF D < 64
THEN
Q := Integer(TruncateTowardZero(ST(0) / ST(1)));
ST(0) := ST(0) – (ST(1) ∗ Q);
C2 := 0;C0, C3, C1 := LeastSignifica ntBits(Q); (* Q2, Q1, Q0 *)
ELSE
C2 := 1;N := An implementation-dependent number between 32 and 63;
QQ := Integer(TruncateTowardZero((ST(0)  / ST(1)) / 2
(D − N)));
ST(0) := ST(0) – (ST(1) ∗ QQ ∗ 2(D − N)); 
FI;
C0 Set to bit 2 (Q2) of the quotient.
C1 Set to 0 if stack underflow occurred; otherwise,  set to least significant bit of quotient (Q0).
C2 Set to 0 if reduction comple te; set to 1 if incomplete.
C3 Set to bit 1 (Q1) of the quotient.
#IA Source operand is an SNaN value, modulus is 0, dividend is ∞, or unsupported format.

Operation
IF D < 64
THEN
ELSE
(D − N)));
FI;
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MF If there is a pending x87 FPU exception.#UD If the LOCK prefix is used.
Same exceptions as in protected mode.FPREM1—Partial RemainderINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-419FPREM1—Partial Remainder
Computes the IEEE remainder obtained from dividing the va lue in the ST(0) register (the dividend) by the value in 
the ST(1) register (the divisor or modulus ), and stores the result in ST(0). The remainder represents the following 
value:
Here, Q is an integer value that is obtained by roundin g the floating-point number quotient of [ST(0) / ST(1)] 
toward the nearest integer value. The magnitude of the rema inder is less than or equal to half the magnitude of the 
modulus, unless a partial remainder was computed (as described below).
This instruction produces an exact result; the precision (inexact) exception does not occur and the rounding control 
has no effect. The following table shows the results obtained when computing the remainder of various classes of numbers, assuming that underflow does not occur.
The FPREM1 instruction computes the remainder specified in  IEEE Standard 754. This instruction operates differ-
ently from the FPREM instruction in the way that it rounds the quotient of ST(0) divided by ST(1) to an integer (see 
the “Operation” section below).
Like the FPREM instruction, FPREM1 computes the remain der through iterative subtraction, but can reduce the 
exponent of ST(0) by no more than 63 in one execution of  the instruction. If the instruction succeeds in producing 
a remainder that is less than one half the modulus, the operation is complete an d the C2 flag in the FPU status word 
is cleared. Otherwise, C2 is set, and the result in ST(0) is called the partial remainder . The exponent of the partial 
remainder will be less than the exponent of the original  dividend by at least 32. Software can re-execute the 
instruction (using the partial remainder in ST(0) as the di vidend) until C2 is cleared. (Note that while executing 
such a remainder-computation loop, a higher-priority inte rrupting routine that needs the FPU can force a context 
switch in-between the instructions in the loop.)
An important use of the FPREM1 instruction is to reduce the arguments of periodic functions. When reduction is 
complete, the instruction stores the three least-significant bi ts of the quotient in the C3, C1, and C0 flags of the FPU 
status word. This information is important in argument reduction for the tangent function (using a modulus of π/4), 
because it locates the original angle in the correct one of eight sectors of the unit circle.Opcode Instruction 64-Bit 
D9 F5 FPREM1 Valid Valid Replace ST(0) with the IEEE remainder obtained from dividing 
Table 3-32.  FPREM1 Results
ST(1)
− ∞ *** *** N a N
ST(0) − FS T ( 0 ) ±F or −0* * ± F or − 0S T ( 0 ) N a N
− 0 − 0 − 0* * − 0- 0 N a N
+ 0 + 0 + 0* * + 0+ 0 N a N
+ FS T ( 0 ) ± F or + 0* * ± F or + 0S T ( 0 ) N a N
+ ∞ *** *** N a N
NOTES:
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FPREM1—Partial RemainderINSTRUCTION SET REFERENCE, A-L
3-420 Vol. 2AThis instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation 
IF D < 64
THEN
Q := Integer(RoundTowardNearestInteger(ST(0) / ST(1)));
ELSE
C2 := 1;N := An implementation-dependent number between 32 and 63;QQ := Integer(TruncateTowardZero((ST(0)  / ST(1)) / 2
(D − N)));
FI;
#IA Source operand is an SNaN value, modulus (divisor) is 0, dividend is ∞, or unsupported 
format.
Same exceptions as in protected mode.FPTAN—Partial TangentINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-421FPTAN—Partial Tangent
Computes the approximate tangent of the source operand in register ST(0), stores the result in ST(0), and pushes 
a 1.0 onto the FPU register stack. The source operand must be given in radians and must be less than ±263. The 
following table shows the unmasked results obtained when  computing the partial tangent of various classes of 
FPTAN only to arguments reduced accurately in software, to a value smaller in absolute value than 3 π/8. See the 
The value 1.0 is pushed onto the register stack after the tangent has been computed to maintain compatibility with 
the Intel 8087 and Intel287 math coprocessors. This operatio n also simplifies the calculation of other trigonometric 
functions. For instance, the cotangent (which is the reci procal of the tangent) can be computed by executing a 
FDIVR instruction after the FPTAN instruction.
D9 F2 FPTAN Valid Valid Replace ST(0) with its approximate tangent and push 1 
onto the FPU stack.
Table 3-33.  FPTAN Results
− ∞ *
− F − F to + F
− 0 - 0
+ 0 + 0
+ F − F to + F
+ ∞ *
NaN NaN  
NOTES:
F Means finite floating-point value.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FPTAN—Partial TangentINSTRUCTION SET REFERENCE, A-L
3-422 Vol. 2AOperation
IF ST(0) < 263
THEN
C2 := 0;ST(0) := fptan(ST(0)); // approximation of tanTOP := TOP − 1;
ST(0) := 1.0;
C2 := 1;
FI;
C1 Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.
C2 Set to 1 if outside range ( −263 < source operand < +263); otherwise, set to 0.
#IS Stack underflow or overflow occurred.#IA Source operand is an SNaN value, ∞, or unsupported format.
Same exceptions as in protected mode.FRNDINT—Round to IntegerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-423FRNDINT—Round to Integer
Rounds the source value in the ST(0) register to the near est integral value, depending on the current rounding 
mode (setting of the RC field of the FPU co ntrol word), and stores the result in ST(0).

If the source value is ∞, the value is not changed. If the source value is not an integral value, the floating-point 
inexact-result exception (#P) is generated.
Operation
ST(0) := RoundToIntegralValue(ST(0));
#IA Source operand is an SNaN value or unsupported format.
#D Source operand is a denormal value.#P Source operand is not an integral value.
D9 FC FRNDINT Valid Valid Round ST(0) to an integer.FRSTOR—Restore x87 FPU StateINSTRUCTION SET REFERENCE, A-L
3-424 Vol. 2AFRSTOR—Restore x87 FPU State
Loads the FPU state (operating environment and register st ack) from the memory area specified with the source 
operand. This state data is typically written to the specified memory locati on by a previous FSAVE/FNSAVE instruc-
tion.
Manual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the 
real mode layouts are used. The contents of the FPU regist er stack are stored in the 80 bytes immediately following 
the operating environment image.
The FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE 
If one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be 
generated upon execution of the next fl oating-point instruction (except for the no-wait floating-point instructions, 
Developer’s Manual, Volume 1). To avoid raising exceptio ns when loading a new operat ing environment, clear all 
the exception flags in the FPU stat us word that is being loaded.
Operation
FPUStatusWord := SRC[FPUStatusWord];FPUTagWord := SRC[FPUTagWord];FPUDataPointer := SRC[FPUDataPointer];FPUInstructionPointer := SRC[FPUInstructionPointer];FPULastInstructionOpcode := SRC[FPULastInstructionOpcode];
ST(0) := SRC[ST(0)];
ST(1) := SRC[ST(1)];ST(2) := SRC[ST(2)];ST(3) := SRC[ST(3)];ST(4) := SRC[ST(4)];ST(5) := SRC[ST(5)];ST(6) := SRC[ST(6)];ST(7) := SRC[ST(7)];
DD /4 FRSTOR m94/108byte Valid Valid Load FPU state from m94byte or m108byte.FRSTOR—Restore x87 FPU StateINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-425Protected Mode Exceptions
selector.
#UD If the LOCK prefix is used.FSAVE/FNSAVE—Store x87 FPU StateINSTRUCTION SET REFERENCE, A-L
3-426 Vol. 2AFSAVE/FNSAVE—Store x87 FPU State
Stores the current FPU state (operating environment and re gister stack) at the specified destination in memory, 
and then re-initializes the FPU. The FSAVE instruction checks for and handles pending unmasked floating-point exceptions before storing the FPU state; the FNSAVE instruction does not.
pointer, and last opcode. Figures 8-9 through 8-12 in the Intel
® 64 and IA-32 Architectures Software Developer’s 
real mode layouts are used. The contents of the FPU regi ster stack are stored in the 80 bytes immediately follow 
The saved image reflects the state of the FPU after all floating-point instructions preceding the FSAVE/FNSAVE 
instruction in the instruction stream have been executed.
After the FPU state has been saved, the FPU is reset to the same default values it is set to with the FINIT/FNINIT 
instructions (see “FINIT/FNINIT—Initialize  Floating-Point Unit” in this chapter).
The FSAVE/FNSAVE instructions are typically used when th e operating system needs to perform a context switch, 
an exception handler needs to use the FPU, or an applic ation program needs to pass a “clean” FPU to a procedure.
The assembler issues two instructions for the FSAVE instruction (an FWAIT instruction followed by an FNSAVE 
instruction), and the processor executes each of these instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception.
For Intel math coprocessors and FPUs prior to the Inte l Pentium processor, an FWAIT instruction should be 
executed before attempting to read from the memory image stored with a prior FSAVE/FNSAVE instruction. This 
FWAIT instruction helps ensure that the storage operation has been completed.
circumstances) for an FNSAVE instruction to be interrupted  prior to being executed to handle a pending FPU excep-
FNSAVE instruction cannot be interrupted in this way on  later Intel processors, except for the Intel QuarkTM X1000 
processor.Opcode Instruction 64-Bit 
9B DD /6 FSAVE m94/108byte Valid Valid Store FPU state to m94byte or m108byte after 
checking for pending unmasked floating-point 
exceptions. Then re-initialize the FPU.
DD /6 FNSAVE1 m94/108byte
NOTES:
1. See IA-32 Architecture Compatibility section below.Valid Valid Store FPU environment to m94byte or m108byte 
without checking for pend ing unmasked floating-
point exceptions. Then re-initialize the FPU.FSAVE/FNSAVE—Store x87 FPU StateINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-427Operation
(* Save FPU State and Registers *)
DEST[FPUControlWord] := FPUControlWord;

NOTES:
DEST[FPUStatusWord] := FPUStatusWord;DEST[FPUTagWord] := FPUTagWord;DEST[FPUDataPointer] := FPUDataPointer;DEST[FPUInstructionPointer] := FPUInstructionPointer;DEST[FPULastInstructionOpcode] := FPULastInstructionOpcode;
DEST[ST(0)] := ST(0);
DEST[ST(1)] := ST(1);DEST[ST(2)] := ST(2);DEST[ST(3)] := ST(3);DEST[ST(4)]:= ST(4);DEST[ST(5)] := ST(5);DEST[ST(6)] := ST(6);DEST[ST(7)] := ST(7);
(* Initialize FPU *)
The C0, C1, C2, and C3 flags are saved and then cleared.
None.
selector.
3-428 Vol. 2AVirtual-8086 Mode Exceptions
current privilege level is 3.FSCALE—ScaleINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-429FSCALE—Scale
Truncates the value in the source operand (toward 0) to an integral value and adds that value to the exponent of 
the destination operand. The destination and source operands are floating-point values located in registers ST(0) and ST(1), respectively. This instruction provides rapid mu ltiplication or division by integral powers of 2. The 
following table shows the results obtained when scaling va rious classes of numbers, assuming that neither over-
flow nor underflow occurs.
In most cases, only the exponent is changed and the mantissa (significand) remains unchanged. However, when 
the value being scaled in ST(0) is a denormal value, the mant issa is also changed and the result may turn out to be 
a normalized number. Similarly, if over flow or underflow results from a scale operation, the resulting mantissa will 
differ from the source’s mantissa.
The FSCALE instruction can also be used to reverse the acti on of the FXTRACT instruction, as shown in the following 
example:
FXTRACT;
FSCALE;FSTP ST(1);
In this example, the FXTRACT instruction extracts the sign ificand and exponent from the value in ST(0) and stores 
them in ST(0) and ST(1) respectively. The FSCALE then sca les the significand in ST(0) by the exponent in ST(1), 
recreating the original value before the FXTRACT operatio n was performed. The FSTP ST(1) instruction overwrites 
the exponent (extracted by the FXTRACT instruction) with the recreated value, which returns the stack to its orig-
inal state with only one register [ST(0)] occupied.
Operation
ST(0) := ST(0) ∗ 2RoundTowardZero(ST(1));
D9 FD FSCALE Valid Valid Scale ST(0) by ST(1).
Table 3-34.  FSCALE Results
ST(1)
− ∞ NaN − ∞ − ∞ − ∞ − ∞ − ∞ NaN
ST(0) − F − 0 − F − F − F − F − ∞ NaN
− 0 − 0 − 0 − 0 − 0 − 0 NaN NaN
+ 0 + 0 + 0 + 0 + 0 + 0 NaN NaN
+ F + 0 + F + F + F + F + ∞ NaN
+ ∞ NaN + ∞ + ∞ + ∞ + ∞ + ∞ NaN
NaN NaN  NaN NaN  NaN  NaN  NaN  NaN
NOTES:
F Means finite floating-point value.FSCALE—ScaleINSTRUCTION SET REFERENCE, A-L
3-430 Vol. 2AFloating-Point Exceptions
#IA Source operand is an SNaN value or unsupported format.#D Source operand is a denormal value.
#O Result is too large for destination format.#P Value cannot be represented exactly in destination format.
Same exceptions as in protected mode.FSIN—SineINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-431FSIN—Sine
Computes an approximation of the sine of the source operan d in register ST(0) and stores the result in ST(0). The 
results obtained when taking the sine of various classe s of numbers, assuming that underflow does not occur.
FSIN only to arguments reduced accurately in software, to a value smaller in absolute value than 3 π/4. See the 
Operation
IF -263 < ST(0) < 263
THEN
C2 := 0;ST(0) := fsin(ST(0)); // approximation of the mathematical sin function
ELSE (* Source operand out of range *)
C2 := 1;
FI;
C0, C3 Undefined.Opcode Instruction 64-Bit 
D9 FE FSIN Valid Valid Replace ST(0) with the approximate of its sine.
Table 3-35.  FSIN Results
SRC (ST(0)) DEST (ST(0))
− ∞ *
− F − 1 to + 1
− 0 −0
+ 0 + 0
+ F − 1 to +1
+ ∞ *
NaN NaN 
NOTES:
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FSIN—SineINSTRUCTION SET REFERENCE, A-L
3-432 Vol. 2AFloating-Point Exceptions
Same exceptions as in protected mode.FSINCOS—Sine and CosineINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-433FSINCOS—Sine and Cosine
Computes both the approximate sine and the cosine of the source operand in register ST(0), stores the sine in 
ST(0), and pushes the cosine onto the top of the FPU regist er stack. (This instruction is faster than executing the 
FSIN and FCOS instructions in succession.)

The source operand must be given in radians and must be within the range −263 to +263. The following table shows 
the results obtained when taking the sine and cosine of various classes of numbers, assuming that underflow does 
not occur.
FSINCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3 π/8. See the 
D9 FB FSINCOS Valid Valid Compute the sine and cosine of ST(0); re place ST(0) with the 
approximate sine, and push the approximate cosine onto the 
Table 3-36.  FSINCOS Results
SRC DEST
ST(0) ST(1) Cosine ST(0) Sine
− ∞ **
− F − 1 to + 1 − 1 to + 1
− 0 + 1 − 0
+ 0 + 1 + 0
+ F − 1 to + 1 − 1 to + 1
+ ∞ **
NaN NaN NaN
NOTES:
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FSINCOS—Sine and CosineINSTRUCTION SET REFERENCE, A-L
3-434 Vol. 2AOperation
THEN
C2 := 0;TEMP := fcos(ST(0)); // approximation of cosineST(0) := fsin(ST(0)); //  approximation of sine
ST(0) := TEMP;
C2 := 1;
FI;
C1 Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs.
Same exceptions as in protected mode.FSQRT—Square RootINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-435FSQRT—Square Root
Computes the square root of the source value in the ST(0) register and stores the result in ST(0).
The following table shows the results obtained when ta king the square root of various classes of numbers, 
assuming that neither overflow nor underflow occurs.
Operation
ST(0) := SquareRoot(ST(0));
#IS Stack underflow occurred.#IA Source operand is an SNaN value or unsupported format.
Source operand is a negative value (except for −0).
D9 FA FSQRT Valid Valid Computes square root of ST(0) and stores the result in ST(0).
Table 3-37.  FSQRT Results
− ∞ *
− F *
− 0 − 0
+ 0 + 0
+ F + F
+ ∞ + ∞
NaN NaN 
NOTES:
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FSQRT—Square RootINSTRUCTION SET REFERENCE, A-L
3-436 Vol. 2AVirtual-8086 Mode Exceptions
Same exceptions as in protected mode.FST/FSTP—Store Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-437FST/FSTP—Store Floating-Point Value
The FST instruction copies the value in the ST(0) register to the destination operand, which can be a memory loca-
tion or another register in the FPU register stack. When  storing the value in memory, the value is converted to 
single precision or double precision floating-point format. 
The FSTP instruction performs the same operation as the FS T instruction and then pops the register stack. To pop 
The FSTP instruction can also store values in memory in double extended-precision floating-point format.
If the destination operand is a memory location, the operan d specifies the address where the first byte of the desti-
nation value is to be stored. If the destination operand is a register, the operand specifies a register in the register stack relative to the top of the stack.
If the destination size is single precision or double precis ion, the significand of the valu e being stored is rounded to 
the width of the destination (according to the rounding mode specified by the RC field of the FPU control word), and 
the exponent is converted to the width and bias of the dest ination format. If the value being stored is too large for 
the destination format, a numeric overflow exception (#O)  is generated and, if the exception is unmasked, no 
value is stored in the destination oper and. If the value being stored is a de normal value, the denormal exception 
(#D) is not generated. This condition is simply signaled as a numeric underflow exception (#U) condition.
If the value being stored is ±0, ± ∞, or a NaN, the least-significant bits of the significand and the exponent are trun-
cated to fit the destination format. This operation preserves the value’s identity as a 0, ∞, or NaN.
If the destination operand is a non-empty register , the invalid-operation exception is not generated.
Operation
DEST := ST(0);IF Instruction 
= FSTP 
THEN 
FI;
Indicates rounding direction of if the floating-point inexact exception (#P) is generated: 0  := 
not roundup; 1  := roundup.
D9 /2 FST m32fp Valid Valid Copy ST(0) to m32fp.
DD /2 FST m64fp Valid Valid Copy ST(0) to m64fp.DD D0+i FST ST(i) Valid Valid Copy ST(0) to ST(i).D9 /3 FSTP m32fp Valid Valid Copy ST(0) to m32fp and pop register stack.DD /3 FSTP m64fp Valid Valid Copy ST(0) to m64fp and pop register stack.DB /7 FSTP m80fp Valid Valid Copy ST(0) to m80fp and pop register stack.DD D8+i FSTP ST(i) Valid Valid Copy ST(0 ) to ST(i) and pop register stack.FST/FSTP—Store Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-438 Vol. 2AFloating-Point Exceptions
#IA If destination result is an SNaN value or unsupported format, except when the destination 
format is in double extended-precision floating-point format.
#U Result is too small for the destination format.
#O Result is too large for the destination format.#P Value cannot be represented exactly in destination format.
selector.

selector.
#UD If the LOCK prefix is used.FSTCW/FNSTCW—Store x87 FPU Control WordINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-439FSTCW/FNSTCW—Store x87 FPU Control Word
Stores the current value of the FPU control word at th e specified destination in memory. The FSTCW instruction 
checks for and handles pending unmasked floating-point exceptions before storing the control word; the FNSTCW 
instruction does not.
The assembler issues two instructions for the FSTCW in struction (an FWAIT instruction followed by an FNSTCW 
instruction), and the processor executes each of these instructions in separately. If an exception is generated for 
When operating a Pentium or Intel486  processor in MS-DOS compatibility mode, it is possible (under unusual 
circumstances) for an FNSTCW instruction to be interrupted prior to being executed to handle a pending FPU 
exception. See the section titled “No-Wait FPU Instructions  Can Get FPU Interrupt in Window” in Appendix D of the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circum-
stances. An FNSTCW instruction cannot be interrupted in th is way on later Intel processors, except for the Intel 
QuarkTM X1000 processor.
Operation
DEST := FPUControlWord;
The C0, C1, C2, and C3 flags are undefined.
None.
selector.
9B D9 /7 FSTCW m2byte Valid Valid Store FPU control word to m2byte after checking for 
D9 /7 FNSTCW
1 m2byte
NOTES:
1. See IA-32 Architecture Compatibility section below.Valid Valid Store FPU control word to m2byte withou t checking for 
pending unmasked floating-point exceptions.FSTCW/FNSTCW—Store x87 FPU Control WordINSTRUCTION SET REFERENCE, A-L
3-440 Vol. 2AReal-Address Mode Exceptions
#UD If the LOCK prefix is used.FSTENV/FNSTENV—Store x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-441FSTENV/FNSTENV—Store x87 FPU Environment
Saves the current FPU operating environment at the memory location specified with the destination operand, and 
then masks all floating-point exceptions. The FPU operating environment consists of the FPU control word, status 
word, tag word, instruction pointer, data pointer, an d last opcode. Figures 8-9 through 8-12 in the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 1, show the layout in memory of the stored environ-ment, depending on the operating mode of the processor (p rotected or real) and the current operand-size attribute 
(16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used.
The FSTENV instruction checks for and handles any pending unmasked floating-point exceptions before storing 
the FPU environment; the FNSTENV instruction does not. The saved image reflects the state of the FPU after all 
floating-point instructions preceding the FSTENV/FNSTE NV instruction in the instruction stream have been 
executed.
These instructions are often used by exception handlers  because they provide access to the FPU instruction and 
data pointers. The environment is typically saved in the stack. Masking all exceptions after saving the environment 
prevents floating-point exceptions fr om interrupting the exception handler.
The assembler issues two instructions for the FSTENV in struction (an FWAIT instruction followed by an FNSTENV 
circumstances) for an FNSTENV instruction to be interrupted prior to being executed to handle a pending FPU 
stances. An FNSTENV instruction cannot be interrupted in this way on later Intel processors, except for the Intel 
Operation
The C0, C1, C2, and C3 are undefined.Opcode Instruction 64-Bit 
9B D9 /6 FSTENV m14/28byte Valid Valid Store FPU environment to m14byte or m28byte 
after checking for pending unmasked floating-point 
exceptions. Then mask all floating-point exceptions.
D9 /6 FNSTENV1 m14/28byte
NOTES:
1. See IA-32 Architecture Compatibility section below.Valid Valid Store FPU environment to m14byte or m28byte 
without checking for pending unmasked floating-point exceptions. Then mask all floating-
point exceptions.FSTENV/FNSTENV—Store x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-L
3-442 Vol. 2AFloating-Point Exceptions
None.
selector.

None.
selector.
#UD If the LOCK prefix is used.FSTSW/FNSTSW—Store x87 FPU Status WordINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-443FSTSW/FNSTSW—Store x87 FPU Status Word
Stores the current value of the x87 FPU status word in the destination location. The destination operand can be 
either a two-byte memory location or the AX register . The FSTSW instruction checks for and handles pending 
unmasked floating-point exceptions before storing the status word; the FNSTSW instruction does not.
The FNSTSW AX form of the instruction is used primarily  in conditional branching (for instance, after an FPU 
comparison instruction or an FPREM, FPREM1, or FXAM instruction), where th e direction of the branch depends on 
the state of the FPU condition code flags. (See the sectio n titled “Branching and Conditional Moves on FPU Condi-
tion Codes” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.) This 
instruction can also be used to invoke exception handlers  (by examining the exception flags) in environments that 
do not use interrupts. When the FNSTSW AX instruction is executed, the AX register is updated before the 
processor executes any further instructions. The status stored in the AX register is thus guaranteed to be from the 
completion of the prior FPU instruction. 
The assembler issues two instructions for the FSTSW in struction (an FWAIT instruction followed by an FNSTSW 
circumstances) for an FNSTSW instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled “No-Wait FPU Instructions  Can Get FPU Interrupt in Window” in Appendix D of the 
Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circum-
stances. An FNSTSW instruction cannot be interrupted in th is way on later Intel processors, except for the Intel 
Operation
DEST := FPUStatusWord;
The C0, C1, C2, and C3 are undefined.
9B DD /7 FSTSW m2byte Valid Valid Store FPU status word at m2byte after checking 
for pending unmasked floating-point exceptions.
9B DF E0 FSTSW AX Valid Valid Store FPU status word in AX register after 
DD /7 FNSTSW1 m2byte
NOTES:
1. See IA-32 Architecture Compatibility section below.Valid Valid Store FPU status word at m2byte without 
DF E0 FNSTSW1 AX Valid Valid Store FPU status word in AX register without 
checking for pending unmasked floating-point exceptions.FSTSW/FNSTSW—Store x87 FPU Status WordINSTRUCTION SET REFERENCE, A-L
3-444 Vol. 2AProtected Mode Exceptions
selector.
#UD If the LOCK prefix is used.FSUB/FSUBP/FISUB—SubtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-445FSUB/FSUBP/FISUB—Subtract
Subtracts the source operand from the destination operand and stores the difference in the destination location. 
The destination operand is always an FPU data register; th e source operand can be a register or a memory location. 
The no-operand version of the instruction subtracts the cont ents of the ST(0) register from the ST(1) register and 
stores the result in ST(1). The one-operand version subtra cts the contents of a memory location (either a floating-
point or an integer value) from the contents of the ST(0) register and stores the result in ST(0). The two-operand 
version, subtracts the contents of the ST(0) register from the ST(i) register or vice versa.
The FSUBP instructions perform the additional operation of popping the FPU register stack following the subtrac-
tion. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer 
(TOP) by 1. The no-operand version of the floating-point su btract instructions always results in the register stack 
being popped. In some assemblers, the mnemonic fo r this instruction is FSUB rather than FSUBP.
The FISUB instructions convert an integer source operan d to double extended-precisi on floating-point format 
before performing the subtraction.
Table 3-38 shows the results obtained when subtracting va rious classes of numbers from one another, assuming 
that neither overflow nor underflow occurs. Here, the SRC value is subtracted from the DEST value (DEST − SRC  = 
result).
When the difference between two operands of like sign is 0, the result is +0, except for the round toward −∞ mode, 
in which case the result is −0. This instruction also guarantees that +0 − (−0) = +0, and that −0 − (+0) = −0. When the 
source operand is an integer 0, it is treated as a +0.
When one operand is ∞, the result is ∞ of the expected sign. If both operands are ∞ of the same sign, an invalid-
operation exception is generated.Opcode Instruction 64-Bit 
D8 /4 FSUB m32fp Valid Valid Subtract m32fp from ST(0) and store result in ST(0).
DC /4 FSUB m64fp Valid Valid Subtract m64fp from ST(0) and store result in ST(0).
D8 E0+i FSUB ST(0), ST(i) Valid Valid Subtract ST(i) from ST(0) and store result in ST(0).
DC E8+i FSUB ST(i), ST(0) Valid Valid Subtract ST(0) from ST(i) and store result in ST(i).
DE E8+i FSUBP ST(i), ST(0) Valid Valid Subtract ST(0) from ST(i),  store result in ST(i), and 
DE E9 FSUBP Valid Valid Subtract ST(0) from  ST(1), store resu lt in ST(1), and 
DA /4 FISUB m32int Valid Valid Subtract m32int from ST(0) and store result in ST(0).DE /4 FISUB m16int Valid Valid Subtract m16int from ST(0) and store result in ST(0).FSUB/FSUBP/FISUB—SubtractINSTRUCTION SET REFERENCE, A-L
3-446 Vol. 2AThis instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF Instruction = FISUB
THEN
DEST := DEST − ConvertToDoubleExtendedPrecisionFP(SRC);
DEST := DEST − SRC;
FI;

Operation
THEN
FI;
IF Instruction = FSUBP 
THEN 
FI;
Operands are infinities of like sign.
#P Value cannot be represented exactly in destination format.Table 3-38.  FSUB/FSUBP/FISUB Results
SRC
− ∞ − F or − I − 0 + 0 + F or + I + ∞ NaN
− ∞ * − ∞ − ∞ − ∞ − ∞ − ∞ NaN
− F + ∞ ±F or ±0 DEST DEST − F − ∞ NaN
DEST − 0 + ∞ −SRC ±0 − 0 − SRC − ∞ NaN
+ 0 + ∞ −SRC + 0 ±0 − SRC − ∞ NaN
+ F + ∞ + F DEST DEST ±F or ±0 − ∞ NaN
+ ∞ + ∞ + ∞ + ∞ + ∞ + ∞ *N a N
NOTES:
F Means finite floating-point value.IM e a n s  i n t e g e r .* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FSUB/FSUBP/FISUB—SubtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-447Protected Mode Exceptions
selector.
#UD If the LOCK prefix is used.FSUBR/FSUBRP/FISUBR—Reverse SubtractINSTRUCTION SET REFERENCE, A-L
3-448 Vol. 2AFSUBR/FSUBRP/FISUBR—Reverse Subtract
Subtracts the destination operand from the source operand and stores the difference in the destination location. 
The destination operand is always an FPU register; the so urce operand can be a register or a memory location. 
These instructions perform the reverse operations of the FSUB, FSUBP, and FISUB instru ctions. They are provided 
to support more efficient coding.
The no-operand version of the instruction subtracts the cont ents of the ST(1) register from the ST(0) register and 
stores the result in ST(1). The one-operand version subtracts the contents of the ST(0) register from the contents 
of a memory location (either a floating-point or an intege r value) and stores the result  in ST(0). The two-operand 
version, subtracts the contents of the ST(i) register from the ST(0) register or vice versa.
The FSUBRP instructions perform the ad ditional operation of popping the FPU register stack following the subtrac-
(TOP) by 1. The no-operand version of the floating-point reverse subtract instructions always results in the register 
stack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP.
The FISUBR instructions convert an integer source operan d to double extended-precision floating-point format 
The following table shows the results obtained when subt racting various classes of numbers from one another, 
assuming that neither overflow nor underflow occurs. Here , the DEST value is subtracted from the SRC value (SRC 
− DEST  = result).
D8 /5 FSUBR m32fp Valid Valid Subtract ST(0) from m32fp and store result in ST(0).
DC /5 FSUBR m64fp Valid Valid Subtract ST(0) from m64fp and store result in ST(0).
D8 E8+i FSUBR ST(0), ST(i) Valid Valid Subtract ST(0) from ST(i) and store result in ST(0).
DC E0+i FSUBR ST(i), ST(0) Valid Valid Subtract ST(i) from ST(0)  and store result in ST(i).
DE E0+i FSUBRP ST(i), ST(0) Valid Valid Subtract ST (i) from ST(0), store result in ST(i), and 
DE E1 FSUBRP Valid Valid Subtract ST(1) from  ST(0), store result in ST(1), and 
DA /5 FISUBR m32int Valid Valid Subtract ST(0) from m32int and store result in ST(0).DE /5 FISUBR m16int Valid Valid Subtract ST(0) from m16int and store result in ST(0).FSUBR/FSUBRP/FISUBR—Reverse SubtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-449This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF Instruction = FISUBR
THEN
DEST := ConvertToDoubleExtendedPrecisionFP(SRC) − DEST;
DEST := SRC − DEST; FI;
IF Instruction =  FSUBRP 
THEN 
PopRegisterStack; FI;
#O Result is too large for destination format.#P Value cannot be represented exactly in destination format.Table 3-39.  FSUBR/FSUBRP/FISUBR Results
SRC
− ∞ −F or −I −0 +0 +F or +I + ∞ NaN
− ∞ * + ∞ + ∞ + ∞ + ∞ + ∞ NaN
− F − ∞ ±F or ±0 −DEST −DEST + F + ∞ NaN
DEST − 0 − ∞ SRC ±0 + 0S R C + ∞ NaN
+ 0 − ∞ SRC − 0 ±0S R C + ∞ NaN
+ F − ∞ − F −DEST −DEST ±F or ±0 + ∞ NaN
+ ∞ − ∞ − ∞ − ∞ − ∞ − ∞ *N a N
NOTES:
F Means finite floating-point value.IM e a n s  i n t e g e r .* Indicates floating-point invalid-arithmetic-operand (#IA) exception.FSUBR/FSUBRP/FISUBR—Reverse SubtractINSTRUCTION SET REFERENCE, A-L
3-450 Vol. 2AProtected Mode Exceptions
selector.

#UD If the LOCK prefix is used.FTST—TESTINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-451FTST—TEST
Compares the value in the ST(0) register with 0.0 and se ts the condition code flags C0, C2, and C3 in the FPU 
status word according to the results (see table below).
This instruction performs an “unordered comparison.” An unordered comparison also checks the class of the 
numbers being compared (see “FXAM—Examine Floating-Point” in this chapter). If the value in register ST(0) is a 
NaN or is in an undefined format, the condition flags are set to “unordered” and the in valid operation exception is 
The sign of zero is ignored, so that (– 0.0  := +0.0).
Operation
Not comparable: C3, C2, C0 := 111;ST(0) > 0.0: C3, C2, C0 := 000;
ST(0) < 0.0: C3, C2, C0 := 001;
ST(0) 
= 0.0: C3, C2, C0 := 100;
ESAC;
C1 Set to 0.
C0, C2, C3 See Table 3-40.
#IS Stack underflow occurred.#IA The source operand is a NaN value or is in an unsupported format.#D The source operand is a denormal value.
D9 E4 FTST Valid Valid Compare ST(0) with 0.0.
Table 3-40.  FTST Results
ST(0) > 0.0 0 0 0
ST(0) < 0.0 0 0 1
ST(0) = 0.0 1 0 0
Unordered 1 1 1FTST—TESTINSTRUCTION SET REFERENCE, A-L
3-452 Vol. 2AVirtual-8086 Mode Exceptions
Same exceptions as in protected mode.FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-453FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating-Point Values
Performs an unordered comparison of the contents of regi ster ST(0) and ST(i) and sets condition code flags C0, C2, 
and C3 in the FPU status word according to the results (see the table below). If no operand is specified, the 
contents of registers ST(0) and ST(1) are compared. The si gn of zero is ignored, so that –0.0 is equal to +0.0.
in this chapter). The FUCOM/FUCOMP/FUCOMPP inst ructions perform the same operations as the 
FCOM/FCOMP/FCOMPP instructions. The only difference is that the FUCOM/ FUCOMP/FUCOMPP instructions raise 
the invalid-arithmetic-operand exception (#IA) only when eith er or both operands are an SNaN or are in an unsup-
ported format; QNaNs cause the condition code flags to be set to unordered, but do not cause an exception to be 
generated. The FCOM/FCOMP/FCOMPP instru ctions raise an invalid-operation exception when either or both of the 
operands are a NaN value of any kind or are in an unsupported format.
As with the FCOM/FCOMP/FCOMPP instructions, if the oper ation results in an invalid-arithmetic-operand exception 
being raised, the condition code flags ar e set only if the exception is masked.
The FUCOMP instruction pops the register stack followin g the comparison operation and the FUCOMPP instruction 
DD E0+i FUCOM ST(i) Valid Valid C ompare ST(0) with ST(i).
DD E1 FUCOM Valid Valid Compare ST(0) with ST(1).DD E8+i FUCOMP ST(i) Valid Valid Compare ST (0) with ST(i) and pop register stack.
DD E9 FUCOMP Valid Valid Compare ST(0) wi th ST(1) and pop register stack.
DA E9 FUCOMPP Valid Valid Compare ST(0) with ST(1) and pop register stack twice.
Table 3-41.  FUCOM/FU COMP/FUCOMPP Results
Comparison Results* C3 C2 C0
Unordered 1 1 1
NOTES:
* Flags not set if unmasked invalid-arithm etic-operand (#IA) exception is generated.FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating-Point ValuesINSTRUCTION SET REFERENCE, A-L
3-454 Vol. 2AOperation
ESAC;
IF ST(0) or SRC = QNaN, but not SNaN or unsupported format
THEN 
ELSE (* ST(0) or SRC is SN aN or unsupported format *)
= 1
THEN 
FI;
FI;
IF Instruction = FUCOMP 
THEN 
FI;
IF Instruction = FUCOMPP 
THEN 
FI;
C0, C2, C3 See Table 3-41.
#IS Stack underflow occurred.#IA One or both operands are SNaN values or have unsupported formats. Detection of a QNaN 
value in and of itself does not raise an invalid-operand exception.
Same exceptions as in protected mode.FXAM—Examine Floating-PointINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-455FXAM—Examine Floating-Point
Examines the contents of the ST(0) register and sets the co ndition code flags C0, C2, and C3 in the FPU status word 
to indicate the class of value or number in the register (see the table below).
.
The C1 flag is set to the sign of the value in ST(0),  regardless of whether the register is empty or full.
Operation
C1 := sign bit of ST; (* 0 for positive, 1 for negative *)CASE (class of value or number in ST(0)) OF
Unsupported:C3, C2, C0 := 000;NaN: C3, C2, C0 := 001;Normal: C3, C2, C0 := 010;Infinity: C3, C2, C0 := 011;Zero: C3, C2, C0 := 100;Empty: C3, C2, C0 := 101;Denormal: C3, C2, C0 := 110;
ESAC;
C1 Sign of value in ST(0).
C0, C2, C3 See Table 3-42.
None.
D9 E5 FXAM Valid Valid Classify value or number in ST(0).
Table 3-42.  FXAM Results
Class C3 C2 C0
Unsupported 00 0
NaN 00 1
Normal finite number 01 0
Infinity 01 1
Zero 10 0
Empty 10 1
Denormal number 11 0FXAM—Examine Floating-PointINSTRUCTION SET REFERENCE, A-L
3-456 Vol. 2AVirtual-8086 Mode Exceptions
Same exceptions as in protected mode.FXCH—Exchange Register ContentsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-457FXCH—Exchange Register Contents
Exchanges the contents of registers ST(0 ) and ST(i). If no source operand is specified, the contents of ST(0) and 
ST(1) are exchanged.
This instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)], 
so that they can be operated on by those floating-point in structions that can only operate on values in ST(0). For 
example, the following instruction sequence takes the square root of the third register from the top of the register 
stack:
FXCH ST(3);
FSQRT;FXCH ST(3);
Operation
IF (Number-of-operands) is 1
THEN
temp := ST(0);ST(0) := SRC;SRC := temp;
ELSE
temp := ST(0);ST(0) := ST(1);ST(1) := temp;
FI;
C1 Set to 0.
D9 C8+i FXCH ST(i) Valid Valid Exchang e the contents of ST(0) and ST(i).
D9 C9 FXCH Valid Valid Exchange th e contents of ST(0) and ST(1).FXCH—Exchange Register ContentsINSTRUCTION SET REFERENCE, A-L
3-458 Vol. 2ACompatibility Mode Exceptions
Same exceptions as in protected mode.FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR StateINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-459FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR State

FI;
C1 Set to 0.
Reloads the x87 FPU, MMX technology, XMM, and MXCSR re gisters from the 512-byte memory image specified in 
the source operand. This data should have been written to memory previously using the FXSAVE instruction, and 
in the same format as required by the operating modes. Th e first byte of the data shou ld be located on a 16-byte 
boundary. There are three distinct layouts of the FXSAVE  state map: one for legacy and compatibility mode, a 
second format for 64-bit mode FXSAVE/FXRSTOR with REX. W=0, and the third format is for 64-bit mode with 
FXSAVE64/FXRSTOR64. Table 3-43 shows the layout of th e legacy/compatibility mode state information in 
memory and describes the fields in the memory imag e for the FXRSTOR and FXSAVE instructions. Table 3-46 
shows the layout of the 64-bit mode state informatio n when REX.W is set (FXSAVE64/FXRSTOR64). Table 3-47 
shows the layout of the 64-bit mode state information when REX.W is clear (FXSAVE/FXRSTOR).
The state image referenced with an FXRSTOR instruction mu st have been saved using an FXSAVE instruction or be 
in the same format as required by Table 3-43, Table 3-46, or Table 3-47. Referencing a state image saved with an 
FSAVE, FNSAVE instruction or incompatible field layo ut will result in an incorrect state restoration.
The FXRSTOR instruction does not flush pending x87 FPU ex ceptions. To check and raise exceptions when loading 
x87 FPU state information with the FX RSTOR instruction, use an FWAIT instruction after the FXRSTOR instruction.
If the OSFXSR bit in control register CR4 is not set, th e FXRSTOR instruction may not restore the states of the XMM 
and MXCSR registers. This behavior is implementation dependent.
If the MXCSR state contains an unmasked exception with a corresponding status flag also set, loading the register 
with the FXRSTOR instruction will not result in a SIMD floa ting-point error condition being generated. Only the next 
occurrence of this unmasked exception will result in the exception being generated.
Bits 16 through 32 of the MXCSR register are defined as rese rved and should be set to 0. Attempting to write a 1 
in any of these bits from the saved st ate image will result in a general protection exception (#GP) being generated.
Bytes 464:511 of an FXSAVE image are available for soft ware use. FXRSTOR ignores the content of bytes 464:511 
in an FXSAVE state image.
Operation
      THEN                            (x87 FPU, MMX,  XMM15-XMM0, MXCSR)      Load(SRC);
      ELSE
(x87 FPU, MMX, XMM7-XMM0, MXCSR) := Load(SRC);
FI;
x87 FPU and SIMD Floating-Point Exceptions
En64-Bit 
NP 0F AE /1
FXRSTOR m512byteM Valid Valid Restore the x87 FPU, MMX, XMM, and MXCSR 
register state from m512byte.
NP REX.W + 0F AE /1
FXRSTOR64 m512byteM Valid N.E. Restore the x87 FP U, MMX, XMM, and MXCSR 
M ModRM:r/m (r) N/A N/A N/AFXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR StateINSTRUCTION SET REFERENCE, A-L
3-460 Vol. 2AProtected Mode Exceptions
If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See align-
ment check exception [#AC] below.)
For an attempt to set reserved bits in MXCSR.
#NM If CR0.TS[bit 3] = 1. 
#UD If CPUID.01H:EDX.FXSR[bit 24] = 0.
If instruction is preceded by a LOCK prefix.
#AC If this exception is disabled a general protec tion exception (#GP) is signaled if the memory 
operand is not aligned on a 16-byte boundary, as described above. If the alignment check 
exception (#AC) is enabled (and the CPL is 3) , signaling of #AC is not guaranteed and may 
vary with implementation, as follows. In all implementations where #AC is not signaled, a 
general protection exception is signaled in its place. In addition, the width of the alignment 
check may also vary with implementation. For instance, for a given implementation, an align-ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-
tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte 
misalignments).
#GP If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#PF(fault-code) For a page fault.#AC For unaligned memory reference.
Vol. 2A 3-46164-Bit Mode Exceptions
If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#PF(fault-code) For a page fault.#NM If CR0.TS[bit 3] = 1. 
check may also vary with implementation. For instance, for a given implementation, an align-
ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte 
misalignments).FXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-L
3-462 Vol. 2AFXSAVE—Save x87 FPU, MMX Technology, and SSE State
Saves the current state of the x87 FPU, MMX technology , XMM, and MXCSR registers to a 512-byte memory loca-
tion specified in the destination operand. The content layout of the 512 byte region depends on whether the 
processor is operating in non-64-bit operating modes or 64-bit sub-mode of IA-32e mode. 
Bytes 464:511 are available to software use. The proce ssor does not write to bytes 464:511 of an FXSAVE area. 
The operation of FXSAVE in non-64-bit modes is described first.
Non-64-Bit Mode Operation
Table 3-43 shows the layout of the state information in me mory when the processor is operating in legacy modes.Opcode/
En64-Bit 
NP 0F AE /0
FXSAVE m512byteM Valid Valid Save the x87 FPU, MMX, XMM, and MXCSR 
register state to m512byte.
NP REX.W + 0F AE /0
FXSAVE64 m512byteM Valid N.E. Save the x87 FPU, MMX, XMM, and MXCSR 
Table 3-43.  Non-64-Bit-Mode Layout of FXSAVE and FXRSTOR Memory Region
15 14 13  12 11 10 9  8 7 6 5 4 3 2 1 0
Rsvd FCS FIP[31:0] FOP Rsvd FTW FSW FCW 0
MXCSR_MASK MXCSR Rsrvd FDS FDP[31:0] 16
XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
Reserved 288FXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-463The destination operand contains the first byte of the memory image, and it must be aligned on a 16-byte 
boundary. A misaligned destination operand will result in  a general-protection (#GP) exception being generated (or 
in some cases, an alignment check exception [#AC]).
The FXSAVE instruction is used when an operating system needs to perform a context switch or when an exception 
handler needs to save and examine the current state of  the x87 FPU, MMX technology, and/or XMM and MXCSR 
The fields in Table 3-43 are defined in Table 3-44.Reserved 304
Reserved 320
Reserved 336
Reserved 352
Reserved 368
Reserved 384
Reserved 400
Reserved 416
Reserved 432
Reserved 448
Available 464
Available 480
Available 496
Table 3-44.  Field Definitions 
Field Definition
FCW x87 FPU Control Word (16 bits). See Figure 8-6 in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume  1, for the layout of the x87 FPU control word.

FSW x87 FPU Status Word (16 bits). See Figure 8-4 in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume  1, for the layout of the x87 FPU status word.
Abridged FTW x87 FPU Tag Word (8 bits). The tag informatio n saved here is abridged, as described in the following 
paragraphs.
FOP x87 FPU Opcode (16 bits). The lower 11 bits of this field contain the opcode, upper 5 bits are reserved. 
See Figure 8-8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for 
the layout of the x87 FPU opcode field.
FIP x87 FPU Instruction Pointer Offset (64 bits). The contents of this field differ depending on the current 
addressing mode (32-bit, 16-bit, or 64-bit) of the processor when the FXSAVE instruction was 
executed:
32-bit mode — 32-bit IP offset.16-bit mode — low 16 bits are IP offset; high 16 bits are reserved.
64-bit mode wi th REX.W — 64-bit IP offset.
64-bit mode with out REX.W — 32-bit IP offset.
See “x87 FPU Instruction and Operand (Data) Pointers” in Chapter 8 of the Intel
Architectures Software Developer’s Manual, Volume 1, for a description of the x87 FPU instruction 
pointer.
FCS x87 FPU Instruction Pointer Selector (16 bits). If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 1, the 
processor deprecates FCS and FDS, and this field is saved as 0000H.Table 3-43.  Non-64-Bit-Mode Layout of FX SAVE and FXRSTOR Memory Region (Contd.)
15 14 13  12 11 10 9  8 7 6 5 4 3 2 1 0FXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-L
3-464 Vol. 2AThe FXSAVE instruction saves an abridged version of the x87 FPU tag word in the FTW field (unlike the FSAVE 
instruction, which saves the complete tag word). The ta g information is saved in physical register order (R0 
through R7), rather than in top-of-stack (TOS) order. With the FXSAVE instruction, however, only a single bit (1 for 
valid or 0 for empty) is saved for each tag. For example,  assume that the tag word is currently set as follows:
R7 R6 R5 R4 R3 R2 R1 R0
11 xx xx xx 11 11 11 11
Here, 11B indicates empty stack elements and “xx” indi cates valid (00B), zero (01B), or special (10B). 
For this example, the FXSAVE instruction save s only the following 8 bits of information:
01110000
Here, a 1 is saved for any valid, zero, or special tag, and a 0 is saved for any empty tag.The operation of the FXSAVE instruction differs from that of the FSAVE instruction, the as follows:
•FXSAVE instruction does not check for pending unmasked floating-point exceptions. (The FXSAVE operation in 
this regard is similar to the operation of the FNSAVE instruction). 
•After the FXSAVE instruction has saved the state of th e x87 FPU, MMX technology, XMM, and MXCSR registers, 
the processor retains the contents of the registers. Because of this behavior, the FXSAVE instruction cannot be 
used by an application program to pass a “clean” x87 FP U state to a procedure, since it retains the current 
state. To clean the x87 FPU state, an application must explicitly execute an FINIT instruction after an FXSAVE 
instruction to reinitialize the x87 FPU state.FDP x87 FPU Instruction Operand (Data) Pointer Offset (64 bits). The contents of this field differ 
depending on the current addressing mode (32-bit, 16-bit, or 64-bit) of the processor when the FXSAVE instruction was executed:
32-bit mode — 32-bit DP offset.
16-bit mode — low 16 bits are DP offset; high 16 bits are reserved.
64-bit mode with REX. W — 64-bit DP offset.
64-bit mode without REX. W — 32-bit DP offset.
Architectures Software Developer’s Manual, Volume  1, for a description of the x87 FPU operand 
pointer.
FDS x87 FPU Instruction Operand (Data) Pointer Select or (16 bits). If CPUID.(EAX=07H,ECX=0H):EBX[bit 
13] = 1, the processor deprecates FCS and FDS, and this field is saved as 0000H.
MXCSR MXCSR Register State (32 bits ). See Figure 10 -3 in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume  1, for the layout of the MXCSR register. If th e OSFXSR bit in control 
register CR4 is not set, the FX SAVE instruction may not save th is register. This behavior is 
MXCSR_
MASKMXCSR_MASK (32 bits). This mask  can be used to adjust values  written to the MXCSR register, 
ensuring that reserved bits are set to 0. Set th e mask bits and flags in  MXCSR to the mode of 
operation desired for SSE and SSE2 SIMD floating-point instructions. See “Guidelines for Writing to the MXCSR Register” in Chap ter 11 of the Intel
Volume 1, for instructions for how to determine and use the MXCSR_MASK value.
ST0/MM0 through 
ST7/MM7x87 FPU or MMX technology registers. These 80-bit fields contain the x87 FPU data registers or the 
MMX technology registers, depending on the state of the processor prior to the execution of the 
FXSAVE instruction. If the processor had been executing x87 FPU instruction prior to the FXSAVE 
instruction, the x87 FPU data regist ers are saved; if it had been executing MMX instructions (or SSE or 
SSE2 instructions that operated on the MMX techno logy registers), the MMX technology registers are 
saved. When the MMX technology registers are saved, the high 16 bits of the field are reserved.
XMM0 through XMM7 XMM registers (128 bits per field). If the OSFXSR bit in control register  CR4 is not set, the FXSAVE 
instruction may not save these registers. Th is behavior is impl ementation dependent.Table 3-44.  Field Definitions  (Contd.)
Field DefinitionFXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-465•The format of the memory image saved with the FXSAVE  instruction is the same regardless of the current 
addressing mode (32-bit or 16-bit) and operating mode  (protected, real address, or system management). 
This behavior differs from the FSAVE instructions, wher e the memory image format is different depending on 
the addressing mode and operating mode. Because of the different image formats, the memory image saved 
with the FXSAVE instruction cannot be restored correctly with the FRSTOR instruction, and likewise the state saved with the FSAVE instruction cannot be restored correctly with the FXRSTOR instruction.
The FSAVE format for FTW can be recreated from the FTW valid bits and the stored 80-bit floating-point data 
(assuming the stored data was not the contents of MMX technology registers) using Table 3-45.
The J-bit is defined to be the 1-bit binary integer to the left of the decimal place in the significand. The M-bit is 
defined to be the most significant bit of the fractional port ion of the significand (i.e., the bit immediately to the right 
of the decimal place).
When the M-bit is the most significant bit of the fractional portion of the significand, it must be 0 if the fraction is 
all 0’s.
IA-32e Mode Operation
In compatibility sub-mode of IA-32e mode, legacy SSE re gisters, XMM0 through XMM7, are saved according to the 
legacy FXSAVE map. In 64-bit mode, all of the SSE regist ers, XMM0 through XMM15, are saved. Additionally, there 
are two different layouts of the FXSAVE map in 64-bi t mode, corresponding to FXSAVE64 (which requires 
REX.W=1) and FXSAVE (REX.W=0). In the FXSAVE64 map (Table 3-46), the FPU IP and FPU DP pointers are 64-bit 
wide. In the FXSAVE map for 64-bit mode (Table 3-47), the FPU IP and FPU DP pointers are 32-bits.Table 3-45.  Recreating FSAVE Format 
Exponent
all 1’sExponent
all 0’sFraction
all 0’sJ and M
bitsFTW valid bit
x87 FTW
000 0 x 1 Special 10
000 1 x 1 Valid 00
001 0 0 1 Special 10
001 1 0 1 Valid 00
010 0 x 1 Special 10
010 1 x 1 Special 10
011 0 0 1 Zero 01
011 1 0 1 Special 10
100 1 x 1 Special 10
101 0 0 1 Special 10
101 1 0 1 Special 10
For all legal comb inations above. 0 Empty 11FXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-L
3-466 Vol. 2ATable 3-46.  Layout of the 64-Bit Mode FXSAVE64 Map (Requires REX.W = 1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIP FOP Reserved FTW FSW FCW 0
MXCSR_MASK MXCSR FDP 16
XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
XMM15 400
Available 496FXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-467Table 3-47.  Layout of the 64-B it Mode FXSAVE Map (REX.W = 0)
Reserved FCS FIP[31:0] FOP Reserved FTW FSW FCW 0
MXCSR_MASK MXCSR Reserved FDS FDP[31:0] 16

XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
XMM15 400
XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
XMM15 400
3-468 Vol. 2AOperation
THEN
IF REX.W = 1
THEN
DEST := Save64BitPromotedFxsave (x87 FPU, MMX, XMM15-XMM0,
MXCSR);
ELSE
DEST := Save64BitDefaultFxsave(x87 FPU, MMX, XMM15-XMM0, MXCSR);
FI;
ELSE
DEST := SaveLegacyFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR);
FI;
If a memory operand is not aligned on a 16-by te boundary, regardless of segment. (See the 
description of the alignment check exception [#AC] below.)
#UD If the LOCK prefix is used.#AC If this exception is disabled a general protec tion exception (#GP) is signaled if the memory 
Same exceptions as in real address mode.#PF(fault-code) For a page fault.
#AC For unaligned memory reference.
Same exceptions as in protected mode.FXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-46964-Bit Mode Exceptions
ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-
The order in which the processor signals general-protection  (#GP) and page-fault (#PF) exceptions when they both 
occur on an instruction boundary is given in Table 5-2 in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 3B. This order vary for FXSAVE for different processor implementations.FXTRACT—Extract Exponent and SignificandINSTRUCTION SET REFERENCE, A-L
3-470 Vol. 2AFXTRACT—Extract Exponent and Significand
Separates the source value in the ST(0) register into its exponent and significand, stores the exponent in ST(0), 
and pushes the significand onto the register stack. Follow ing this operation, the new top-of-stack register ST(0) 
contains the value of the original significand expressed as a floating-point value. The sign and significand of this 
value are the same as those found in the source operand, and the exponent is 3FFFH (b iased value for a true expo-
nent of zero). The ST(1) register contains the value of the original operand’s true (unbiased) exponent expressed 
as a floating-point value. (The operation performed by this instruction is a supers et of the IEEE-recommended 
logb(x) function.)
This instruction and the F2XM1 instruction are useful for performing power and range scaling operations. The 
FXTRACT instruction is also useful for converting numbers in double extended-precision floating-point format to 
decimal representations (e.g., for printing or displaying).
If the floating-point zero-divide exception (#Z) is masked  and the source operand is zero, an exponent value of – ∞ 
is stored in register ST(1) and 0 with the sign of the source operand is stored in register ST(0).
Operation
TEMP := Significand(ST(0));
ST(0) := Exponent(ST(0));TOP := TOP 
− 1;
#Z ST(0) operand is ±0.
Same exceptions as in protected mode.Opcode/
Instruction64-Bit 
D9 F4
FXTRACTValid Valid Separate value in ST(0) into exponent and significand, store 
exponent in ST(0), and push the significand onto the register 
stack.FXTRACT—Extract Exponent and SignificandINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-471Compatibility Mode Exceptions
Same exceptions as in protected mode.FYL2X—Compute y * log2xINSTRUCTION SET REFERENCE, A-L
3-472 Vol. 2AFYL2X—Compute y ∗ log2x
Computes (ST(1) ∗ log2 (ST(0))), stores the result in register ST(1), and pops the FPU register stack. The source 
operand in ST(0) must be a non-zero positive number.
The following table shows the results obtained when taking  the log of various classes of numbers, assuming that 
If the divide-by-zero exception is masked and register ST(0) contains ±0, the instruction returns ∞ with a sign that 
is the opposite of the sign of th e source operand in register ST(1).
The FYL2X instruction is designed with a built-in multiplicat ion to optimize the calculation of logarithms with an 
arbitrary positive base (b):
logbx := (log2b)–1 ∗ log2x
Operation
ST(1) := ST(1) ∗ log2ST(0);
D9 F1 FYL2X Valid Valid Repla ce ST(1) with (ST(1) ∗ log2ST(0)) and pop the 
Table 3-48.  FYL2X Results
ST(0)
− ∞ − F ±0 +0<+F<+1 + 1 + F > + 1 + ∞ NaN
− ∞ ** + ∞ + ∞ * − ∞ − ∞ NaN
ST(1) − F ** * * + F − 0 − F − ∞ NaN
− 0 *** + 0 − 0 − 0* NaN
+ 0 *** − 0 + 0 + 0* NaN
+ F ** * * − F + 0 + F + ∞ NaN
+ ∞ ** − ∞ − ∞ * + ∞ + ∞ NaN
NaN NaN NaN NaN NaN NaN NaN NaN NaN
NOTES:
** Indicates floating-point zero-divide (#Z) exception.FYL2X—Compute y * log2xINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-473Floating-Point Exceptions
#IA Either operand is an SNaN or unsupported format.
Source operand in register ST(0) is a negative finite value 
(not -0).
#Z Source operand in register ST(0) is ±0.
Same exceptions as in protected mode.FYL2XP1—Compute y * log2(x +1)INSTRUCTION SET REFERENCE, A-L

(not -0).
3-474 Vol. 2AFYL2XP1—Compute y ∗ log2(x +1)
Computes (ST(1) ∗ log2(ST(0) + 1.0)), stores the result in register ST (1), and pops the FPU register stack. The 
source operand in ST(0) must be in the range:
The source operand in ST(1) can range from −∞ to +∞. If the ST(0) operand is outsid e of its acceptable range, the 
result is undefined and software should not rely on an exception being generated. Under some circumstances 
exceptions may be generated when ST(0) is out of range, bu t this behavior is implementation specific and not guar-
anteed.
The following table shows the results obtained when taking  the log epsilon of various classes of numbers, assuming 
that underflow does not occur.
This instruction provides optimal accuracy for values of eps ilon [the value in register ST(0)] that are close to 0. For 
small epsilon ( ε) values, more significant digits can be retained  by using the FYL2XP1 instruction than by using 
(ε+1) as an argument to the FYL2X instruction. The ( ε+1) expression is commonly found in compound interest and 
annuity calculations. The result can be simply converted into a value in another logarithm base by including a scale factor in the ST(1) source operand. The following equation is  used to calculate the scale factor for a particular loga-
rithm base, where n is the logarithm base desi red for the result of the FYL2XP1 instruction:
scale factor := log
n 2
Operation
ST(1) := ST(1) ∗ log2(ST(0) + 1.0);
PopRegisterStack;Opcode Instruction 64-Bit 
D9 F9 FYL2XP1 Valid Valid Re place ST(1) with ST(1) ∗ log2(ST(0) + 1.0) and pop the 
Table 3-49.  FYL2XP1 Results
ST(0)
−(1 − ( )) to −0 -0 +0 +0 to +(1 - () ) N a N
− ∞ +∞ ** − ∞ NaN
ST(1) − F+ F+ 0 - 0 − F NaN
− 0+ 0+ 0 - 0 − 0 NaN
+0 − 0 − 0+ 0 + 0 NaN
+F − F − 0+ 0 + F NaN
+∞ − ∞ ** + ∞ NaN
NaN NaN NaN NaN NaN NaN
NOTES:
F Means finite floating-point value.* Indicates floating-point invalid-operation (#IA) exception.12 2 ⁄ –() ) to 1 2 2 ⁄ –() –
22⁄ 22⁄FYL2XP1—Compute y * log2(x +1)INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-475FPU Flags Affected
#IS Stack underflow occurred.#IA Either operand is an SNaN value or unsupported format.#D Source operand is a denormal value.
Same exceptions as in protected mode.GF2P8AFFINEINVQB—Galois Field Af fine Transformation InverseINSTRUCTION SET REFERENCE, A-L
3-476 Vol. 2AGF2P8AFFINEINVQB—Galois Field A ffine Transformation Inverse
The AFFINEINVB instruction computes an affi ne transformation in the Galois Field 28. For this instruction, an affine 
transformation is defined by A * inv(x) + b where “A” is an  8 by 8 bit matrix, and “x” and “b” are 8-bit vectors. The 
inverse of the bytes in x is defined with  respect to the reduction polynomial x8 + x4 + x3 + x + 1.
One SIMD register (operand 1) holds “x” as either 16, 32 or  64 8-bit vectors. A second SIMD (operand 2) register 
or memory operand contains 2, 4, or 8 “A” values, whic h are operated upon by the correspondingly aligned 8 “x” 
values in the first register. The “b” vector is constant for all calculations and contained in the immediate byte.
The EVEX encoded form of this instruction does not su pport memory fault suppression. The SSE encoded forms of 
the instruction require 16B alignment on their memory operations.
The inverse of each byte is given by the following table. Th e upper nibble is on the vertical axis and the lower nibble 
is on the horizontal axis. For example, the inverse of 0x95 is 0x8A.Opcode/
Mode 
66 0F3A CF /r /ib
GF2P8AFFINEINVQB xmm1, 
xmm2/m128, imm8A V/V GFNI Computes inverse affine transformation in the 
finite field GF(2^8).
VEX.128.66.0F3A.W1 CF /r /ib
VGF2P8AFFINEINVQB xmm1, xmm2, xmm3/m128, imm8BV / VA V X
GFNIComputes inverse affine transformation in the 
VEX.256.66.0F3A.W1 CF /r /ib
VGF2P8AFFINEINVQB ymm1, ymm2, 
ymm3/m256, imm8BV / VA V X
EVEX.128.66.0F3A.W1 CF /r /ib
VGF2P8AFFINEINVQ B xmm1{k1}{z}, 
xmm2, xmm3/m128/m64bcst, imm8CV / V A V X 5 1 2 V L
EVEX.256.66.0F3A.W1 CF /r /ib
VGF2P8AFFINEINVQB ymm1{k1}{z}, 
ymm2, ymm3/m256/m64bcst, imm8CV / V A V X 5 1 2 V L
EVEX.512.66.0F3A.W1 CF /r /ib
VGF2P8AFFINEINVQB zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8CV / V A V X 5 1 2 F
A N/A ModRM:reg (r, w) ModRM:r/m (r) imm8 (r) N/A
B N/A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8 (r)GF2P8AFFINEINVQB—Galois Field Affine Transformation InverseINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-477Operation
define affine_inverse_byte(tsrc2qw, src1byte, imm):
FOR i := 0 to 7:
* parity(x) = 1 if x has an odd numb er of 1s in it, and 0 otherwise.*
* inverse(x) is defined in the table above *retbyte.bit[i] 
:= parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
return retbyte
VGF2P8AFFINEINVQB dest, src1, src2, imm8 (EVEX Encoded Version)
FOR j := 0 TO KL-1:
IF SRC2 is memory and EVEX.b==1:
tsrc2 := SRC2.qword[0]
ELSE:
tsrc2 := SRC2.qword[j]
FOR b := 0 to 7:
IF k1[j*8+b] OR *no writemask*:
DEST.qword[j].byte[b] := affine_inverse_byte(tsrc2, SR C1.qword[j].byte[b], imm8)
ELSE IF *zeroing*:
DEST.qword[j].byte[b] := 0
*ELSE DEST.qword[j].byte [b] remains unchanged*
DEST[MAX_VL-1:VL] := 0Table 3-50.  Inverse Byte Listings
- 0123456789ABCDEF
0 0 1 8D F6 CB 52 7B D1 E8 4F 29 C0 B0 E1 E5 C7
1 7 4B 4A A4 B9 92 B6 05 F5 83 FF DC C F F4 0E EB 22 3A 6E 5A F1 55 4D A8 C9 C1 A 98 15 30 44 A2 C2
3 2 C4 59 26 CF 33 96 64 2F 23 52 06 F7 7B B5 91 9
4 1 DF E3 76 72 D3 1F 56 9A 76 4A B1 35 42 5E 9 95 ED 5C 5 CA 4C 24 87 BF 18 3E 22 F0 51 EC 61 17
6 1 65 EA FD 34 9A 63 64 3F 44 79 1D F3 39 32 13 B
7 7 9B 79 78 51 0B 5B A3 CB 67 0D 0 6 A 1F A8 18 28 8 37 E7 F8 09 67 3B E5 69 B9 E9 5D 9F 7 2 B 9A 49 D E6 A3 26 DD 88 A8 47 22 A1 49 F8 8F 9D C8 99 A
A F B7 C2 EC 38 FB 86 54 82 6C 81 24 AC EE 7D 26 2
B C E0 1F EF 11 75 78 71 A5 8E 76 3D BD BC 86 57
C B 28 2F A3 DA D4 E4 F A9 27 53 4 1B FC AC E6
D 7A 7 AE 63 C5 DB E2 EA 94 8B C4 D5 9D F8 90 6B
E B1 D D6 EB C6 E CF AD 8 4E D7 E3 5D 50 1E B3F 5 B2 33 83 46 84 6 3 8 CD D9 C7 DA 0C D1 A4 11 CGF2P8AFFINEINVQB—Galois Field Af fine Transformation InverseINSTRUCTION SET REFERENCE, A-L
3-478 Vol. 2AVGF2P8AFFINEINVQB dest, src1, src2, imm8 (128b and 256b VEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256)FOR j 
:= 0 TO KL-1:
DEST.qword[j ].byte[b] := affine_inverse_byte(SRC2.qword[j],  SRC1.qword[j]. byte[b], imm8)
DEST[MAX_VL-1:VL] := 0
GF2P8AFFINEINVQB srcdest, src1, imm8 (128b SSE Encoded Version)
FOR j := 0 TO 1:
SRCDEST.qword[j].byte[b] := affine_inverse_byte(SRC1.qword[j],  SRCDEST.qword[j].byte[b], imm8)
(V)GF2P8AFFINEINVQB __m128i _mm_gf2p8affin einv_epi64_epi 8(__m128i, __m128i, int);
(V)GF2P8AFFINEINVQB __m128i _mm_mask_gf2p8affineinv_ep i64_epi8(__m128i, __mmask16 , __m128i, __m128i, int);
(V)GF2P8AFFINEINVQB __m128i _mm_maskz_gf2p8affineinv_epi64_epi8(__mmask16, __m128i, __m128i, int);VGF2P8AFFINEINVQB __m256i _mm256_gf2p8affineinv_epi64_epi8(__m256i, __m256i, int);VGF2P8AFFINEINVQB __m256i _mm256_mask_gf2p8affineinv_ep i64_epi8(__m256i, __mmask32, __m256i, __m256i, int);
VGF2P8AFFINEINVQB __m256i _mm256_maskz_gf2p8affin einv_epi64_epi8( __mmask32, __m256i,  __m256i, int);
VGF2P8AFFINEINVQB __m512i _mm512_gf2p8affineinv_epi64_epi8(__m512i, __m512i, int);VGF2P8AFFINEINVQB __m512i _mm512_mask_gf2p8affineinv_ep i64_epi8(__m512i, __mmask64, __m512i, __m512i, int);
VGF2P8AFFINEINVQB __m512i _mm512_maskz_gf2p8affin einv_epi64_epi8( __mmask64, __m512i,  __m512i, int);
None.
Legacy-encoded and VEX-encoded: See Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions.”GF2P8AFFINEQB—Galois Field Affine TransformationINSTRUCTION SET REFERENCE, A-L

None.
Vol. 2A 3-479GF2P8AFFINEQB—Galois Field Affine Transformation
The AFFINEB instruction computes an affine  transformation in the Galois Field 28. For this instruction, an affine 
transformation is defined by A * x + b where “A” is an 8 by  8 bit matrix, and “x” and “b” are 8-bit vectors. One SIMD 
register (operand 1) holds “x” as either 16, 32 or 64 8-bit vectors. A second SIMD (operand 2) register or memory 
operand contains 2, 4, or 8 “A” values, which are operated  upon by the correspondingly aligned 8 “x” values in the 
first register. The “b” vector is constant for all calculations and contained in the immediate byte.
the instruction require16B alignment on their memory operations.
Operation
define parity(x):
t := 0 // single bit
t = t xor x.bit[i]
return t
define affine_byte(tsrc2qw, src1byte, imm):
retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
return retbyteOpcode/
Mode 
66 0F3A CE /r /ib
GF2P8AFFINEQB xmm1, 
xmm2/m128, imm8A V/V GFNI Computes affine tran sformation in  the finite 
field GF(2^8).
VEX.128.66.0F3A.W1 CE /r /ib
VGF2P8AFFINEQB xmm1, xmm2, xmm3/m128, imm8BV / VA V X
GFNIComputes affine transfor mation in the finite 
VEX.256.66.0F3A.W1 CE /r /ib
VGF2P8AFFINEQB ymm1, ymm2, 
EVEX.128.66.0F3A.W1 CE /r /ib
VGF2P8AFFINEQB xmm1{k1}{z}, 
EVEX.256.66.0F3A.W1 CE /r /ib
VGF2P8AFFINEQB ymm1{k1}{z}, 
EVEX.512.66.0F3A.W1 CE /r /ib
VGF2P8AFFINEQB zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8CV / V A V X 5 1 2 F
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8 (r)GF2P8AFFINEQB—Galois Fiel d Affine TransformationINSTRUCTION SET REFERENCE, A-L
3-480 Vol. 2AVGF2P8AFFINEQB dest, src1, src2 , imm8 (EVEX Encoded Version)
(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j 
ELSE:
DEST.qword[j ].byte[b] := affine_byte(tsrc2, SRC1.q word[j].byte[b], imm8)
DEST.qword[j ].byte[b] := 0
*ELSE DEST.qword [j].byte[b] rema ins unchanged*
VGF2P8AFFINEQB dest, src1, src2, imm8  (128b and 256b VEX Encoded Versions)
DEST.qword[j ].byte[b] := affine_byte(SRC2.qword[j], SR C1.qword[j].byte[b], imm8)
GF2P8AFFINEQB srcdest, src1, i mm8 (128b SSE Encoded Version)
SRCDEST.qword[j].byte[b] := affine_byte(SRC1.qword[j], SRCDEST.qword[j].byte[b], imm8)
(V)GF2P8AFFINEQB __m128i _mm_gf2p8affine_epi64_epi8(__m128i, __m128i, int);
(V)GF2P8AFFINEQB __m128i _mm_mask _gf2p8affine_epi64_epi8(__m128i, __mmask16, __m128i, __m128i, int);
(V)GF2P8AFFINEQB __m128i _mm_maskz_gf2p8affin e_epi64_epi8(__mmask16, __m128i, __m128i, int);
VGF2P8AFFINEQB __m256i _mm256_gf2p8affine_epi64_epi8(__m256i, __m256i, int);VGF2P8AFFINEQB __m256i _mm256_mask_gf2p8affine_epi64_epi8(__m256i, __mmask32, __m256i, __m256i, int);VGF2P8AFFINEQB __m256i _mm256_maskz_gf2p8affine_epi64_epi8(__mmask32, __m256i, __m256i, int);VGF2P8AFFINEQB __m512i _mm512_gf2p8affine_epi64_epi8(__m512i, __m512i, int);VGF2P8AFFINEQB __m512i _mm512_mask_gf2p8affine_epi64_epi8(__m512i, __mmask64, __m512i, __m512i, int);VGF2P8AFFINEQB __m512i _mm512_maskz_gf2p8affine_epi64_epi8(__mmask64, __m512i, __m512i, int);
None.
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions.”GF2P8MULB—Galois Field Multiply BytesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-481GF2P8MULB—Galois Field Multiply Bytes
The instruction multiplies elements in the finite field GF(28), operating on a byte (field element) in the first source 
operand and the corresponding byte in a second source operand. The field GF(28) is represented in polynomial 
representation with the reduction polynomial x8 + x4 + x3 + x + 1.
This instruction does not support broadcasting.The EVEX encoded form of this instruction supports memory fault suppression. The SSE encoded forms of the 
instruction require16B alignment on their memory operations.
Operation
define gf2p8mul_byte(src1byte, src2byte):
tword 
:= 0
IF src2byte.bit[i]:
tword := tword XOR (src1byte<< i)
* carry out polynomial reduction by the characteristic polynomial p*
FOR i := 14 downto 8:
p := 0x11B << (i-8) *0x11B = 0000_0001_0001_1011 in binary*
IF tword.bit[i]:
tword := tword XOR p
return tword.byte[0]Opcode/
Mode 
66 0F38 CF /r
GF2P8MULB xmm1, xmm2/m128A V/V GFNI Multiplies elements in the finite field GF(2^8). 
VEX.128.66.0F38.W0 CF /r
VGF2P8MULB xmm1, xmm2, 
xmm3/m128BV / VA V X
GFNIMultiplies elements in the finite field GF(2^8). 
VEX.256.66.0F38.W0 CF /r
VGF2P8MULB ymm1, ymm2, 
ymm3/m256BV / VA V X
GFNIMultiplies elements in the finite field GF(2^8).
EVEX.128.66.0F38.W0 CF /r
VGF2P8MULB xmm1{k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
EVEX.256.66.0F38.W0 CF /r
VGF2P8MULB ymm1{k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
EVEX.512.66.0F38.W0 CF /r
VGF2P8MULB zmm1{k1}{z}, zmm2, 
zmm3/m512CV / V A V X 5 1 2 F
B N/A ModRM:reg (w) VEX.vvvv  (r) ModRM:r/m (r) N/A
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/AGF2P8MULB—Galois Field Multiply BytesINSTRUCTION SET REFERENCE, A-L
3-482 Vol. 2AVGF2P8MULB dest, src1, src2 (EVEX Encoded Version)
(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j 
IF k1[j] OR *no writemask*:
DEST.byte[j] := gf2p8mul_byte(SRC1.byte[j], SRC2.byte[j])
ELSE iF *zeroing*:
DEST.byte[j] := 0
* ELSE DEST.byte[j] remains unchanged*
VGF2P8MULB dest, src1, src2 (128b and 256b VEX Encoded Versions)
(KL, VL) = (16, 128), (32, 256)FOR j 
GF2P8MULB srcdest, src1 (128b SSE Encoded Version)
FOR j := 0 TO 15:
SRCDEST.byte[j] :=gf2p8mul_byte(SRCDEST.byte[j], SRC1.byte[j])
(V)GF2P8MULB __m128i _mm_gf2p8mul_epi8(__m128i, __m128i);
(V)GF2P8MULB __m128i _mm_mask_gf2p8mul_epi8(__m128i, __mmask16, __m128i, __m128i);(V)GF2P8MULB __m128i _mm_maskz_gf2p8mul_epi8(__mmask16, __m128i, __m128i);VGF2P8MULB __m256i _mm256_gf2p8mul_epi8(__m256i, __m256i);VGF2P8MULB __m256i _mm256_mask_gf2p8mul_epi8(__m256i, __mmask32, __m256i, __m256i);VGF2P8MULB __m256i _mm256_maskz_gf2p8 mul_epi8(__mmask32, __m256i, __m256i);
VGF2P8MULB __m512i _mm512_gf2p8mul_epi8(__m512i, __m512i);VGF2P8MULB __m512i _mm512_mask_gf2p8mul_epi8(__m512i, __mmask64, __m512i, __m512i);VGF2P8MULB __m512i _mm512_maskz_gf2p8 mul_epi8(__mmask64, __m512i, __m512i);
None.
EVEX-encoded: See Table 2-49, “Type E4 Class Exception Conditions.”HADDPD—Packed Double Precision Floating-Point Horizontal AddINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-483HADDPD—Packed Double Precision Floating-Point Horizontal Add
Adds the double precision floating-point values in th e high and low quadwords of the destination operand and 
stores the result in the low quad word of the destination operand. 
Adds the double precision floating-point values in the high and low quadwords of the source operand and stores the 
result in the high quadword of the destination operand. 
See Figure 3-17 for HADDPD; see Figure 3-18 for VHADDPD.Opcode/
ModeCPUID 
Feature 
66 0F 7C /r
HADDPD xmm1, xmm2/m128RM V/V SSE3 Horizontal add packed double precision

ModeCPUID 
Feature 
66 0F 7C /r
HADDPD xmm1, xmm2/m128RM V/V SSE3 Horizontal add packed double precision 
floating-point values from xmm2/m128 to 
xmm1.
VEX.128.66.0F.WIG 7C /r
VHADDPD xmm1,xmm2, xmm3/m128RVM V/V AVX Horizontal add packed double precision 
floating-point values from xmm2 and xmm3/mem.
VEX.256.66.0F.WIG 7C /r
VHADDPD ymm1, ymm2, ymm3/m256RVM V/V AVX Horizontal add packed double precision 
floating-point values from ymm2 and 
ymm3/mem.
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Figure 3-17.  HADDPD—Packed Double Precision Floating-Point Horizontal AddOM15993HADDPD xmm1, xmm2/m128
xmm1xmm2
/m128[63:0] [127:64]
[127:64] [63:0][63:0] [127:64]
Result:
xmm1xmm2/m128[63:0] +
xmm2/m128[127:64]xmm1[63:0] + xmm1[127:64]HADDPD—Packed Double Precision Floating-Point Horizontal AddINSTRUCTION SET REFERENCE, A-L
3-484 Vol. 2AFigure 3-18.  VHADDPD Operation
zeroed.
Operation
HADDPD (128-bit Legacy SSE Version)
DEST[63:0] := SRC1[127:64] + SRC1[63:0]DEST[127:64] := SRC2[127:64] + SRC2[63:0]DEST[MAXVL-1:128] (Unmodified)
VHADDPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[127:64] + SRC1[63:0]DEST[127:64] := SRC2[127:64] + SRC2[63:0]DEST[MAXVL-1:128] := 0
VHADDPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[127:64] + SRC1[63:0]DEST[127:64] := SRC2[127:64] + SRC2[63:0]DEST[191:128] := SRC1[2 55:192] + SRC1[191:128]
DEST[255:192] := SRC2[2 55:192] + SRC2[191:128]
VHADDPD __m256d _mm256_hadd_pd (__m256d a, __m256d b);
HADDPD __m128d _mm_hadd_pd (__m128d a, __m128d b);
protection exception (#GP) will be generated. 
Overflow, Underflow, Invalid, Precision, Denormal.Y2 + Y3 X2 + X3 Y0 + Y1 X0 + X1 DESTX3 X2 SRC1 X1 X0
Y3 Y2 Y1 Y0 SRC2HADDPD—Packed Double Precision Floating-Point Horizontal AddINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-485Other Exceptions
See Table 2-19, “Type 2 Class Exception Conditions.”HADDPS—Packed Single Precision Floating-Point Horizontal AddINSTRUCTION SET REFERENCE, A-L
3-486 Vol. 2AHADDPS—Packed Single Precision Floating-Point Horizontal Add
Adds the single precision floating-point values in the firs t and second dwords of the destination operand and stores 
the result in the first dword of the destination operand.
Adds single precision floating-point va lues in the third and fourth dword of the destination operand and stores the 
result in the second dword of the destination operand.
Adds single precision floating-point values in the first an d second dword of the source operand and stores the result 
in the third dword of the destination operand.
Adds single precision floating-point values in the third an d fourth dword of the source operand and stores the result 
in the fourth dword of the destination operand. 
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).Opcode/
ModeCPUID 
Feature 
F2 0F 7C /r
HADDPS xmm1, xmm2/m128RM V/V SSE3 Horizontal add packed single precision 
xmm1.
VEX.128.F2.0F.WIG 7C /r
VHADDPS xmm1, xmm2, xmm3/m128RVM V/V AVX Horizontal add packed single precision floating-
point values from xmm2 and xmm3/mem.
VEX.256.F2.0F.WIG 7C /r
VHADDPS ymm1, ymm2, ymm3/m256RVM V/V AVX Horizontal add packed single precision floating-
point values from ymm2 and ymm3/mem.
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AHADDPS—Packed Single Precision Floating-Point Horizontal AddINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-487See Figure 3-19 for HADDPS; see Figure 3-20 for VHADDPS.
Figure 3-20.  VHADDPS Operation
zeroed.
register or a 256-bit memory location. The destination operand is a YMM register.Figure 3-19.  HADDPS—Packed Single Precision Floating-Point Horizontal AddOM15994HADDPS xmm1, xmm2/m128
RESULT:
xmm1xmm2/
m128
xmm1[31:0] + 
xmm1[63:32][31:0]
xmm1[95:64] + 
xmm1[127:96][63:32]
[63:32] [31:0]xmm1 [31:0] [63:32]
xmm2/m128
[31:0] + xmm2/
m128[63:32][95:64]
xmm2/m128
[95:64] + xmm2/
m128[127:96][127:96]
[127:96] [95:64][95:64] [127:96]
Y6+Y7 X6+X7 Y2+Y3 X2+X3 DESTSRC1 X0
SRC2X1 X2 X3 X4 X5 X6 X7
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X0+X1 Y4+Y5 X4+X5 Y0+Y1HADDPS—Packed Single Precision Floating-Point Horizontal AddINSTRUCTION SET REFERENCE, A-L
3-488 Vol. 2AOperation
HADDPS (128-bit Legacy SSE Version)
DEST[31:0] := SRC1[63:32] + SRC1[31:0]DEST[63:32] := SRC1[127:96] + SRC1[95:64]DEST[95:64] := SRC2[63:32] + SRC2[31:0]DEST[127:96] := SRC2[127:96] + SRC2[95:64] DEST[MAXVL-1:128] (Unmodified)
VHADDPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[63:32] + SRC1[31:0]DEST[63:32] := SRC1[127:96] + SRC1[95:64]DEST[95:64] := SRC2[63:32] + SRC2[31:0]DEST[127:96] := SRC2[127:96] + SRC2[95:64] DEST[MAXVL-1:128] := 0
VHADDPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[63:32] + SRC1[31:0]DEST[63:32] := SRC1[127:96] + SRC1[95:64]DEST[95:64] := SRC2[63:32] + SRC2[31:0]DEST[127:96] := SRC2[127:96] + SRC2[95:64] DEST[159:128] := SRC1[1 91:160] + SRC1[159:128]
DEST[191:160] := SRC1[2 55:224] + SRC1[223:192]
DEST[223:192] := SRC2[1 91:160] + SRC2[159:128]
DEST[255:224] := SRC2[2 55:224] + SRC2[223:192]
HADDPS __m128 _mm_hadd_ps (__m128 a, __m128 b);
VHADDPS __m256 _mm256_hadd_ps (__m256 a, __m256 b);
protection exception (#GP) will be generated.
See Table 2-19, “Type 2 Class Exception Conditions.”HLT—HaltINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-489HLT—Halt
Stops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and 
SMI), a debug exception, the BINIT# signal, the INIT# signal , or the RESET# signal will resume execution. If an 
interrupt (including NMI) is used to resume executio n after a HLT instruction, the saved instruction pointer 
(CS:EIP) points to the instruction following the HLT instruction.
When a HLT instruction is executed on an Intel 64 or IA -32 processor supporting Intel Hyper-Threading Technology, 
only the logical processor that executes the instruction is halted. The other logical processors in the physical 
processor remain active, unless they are each individually halted by executing a HLT instruction.
The HLT instruction is a privileged instruction. When th e processor is running in protected or virtual-8086 mode, 
the privilege level of a program or procedur e must be 0 to execute the HLT instruction.
Operation
Enter Halt state;
None.
None.
En64-Bit 
F4 HLT ZO Valid Valid Halt
ZO N/A N/A N/A N/AHRESET—History ResetINSTRUCTION SET REFERENCE, A-L
3-490 Vol. 2AHRESET—History Reset
Requests the processor to selectively reset selected components of hardware history maintained by the current

Operation
None.
None.
En64-Bit 
Requests the processor to selectively reset selected components of hardware history maintained by the current 
logical processor. HRESET operation is controlled by th e implicit EAX operand. The value of the explicit imm8 
operand is ignored. This instruction can only be executed at privilege level 0.
The HRESET instruction can be used to request reset of multiple components of hardware history. Prior to the 
execution of HRESET, the system software must take the following steps:
1. Enumerate the HRESET capabilities via CPUID.20H.0H: EBX, which indicates what components of hardware 
history can be reset.
2. Only the bits enumerated by CPUID.20H.0H:E BX can be set in the IA32_HRESET_ENABLE MSR. 
HRESET causes a general-protection ex ception (#GP) if EAX sets any bits th at are not set in the IA32_HRESET_EN-
ABLE MSR. 
Any attempt to execute the HRESET instruction inside a tr ansactional region will result in a transaction abort.
Operation
IF EAX = 0
    THEN NOP    ELSE         FOREACH i such that EAX[i] = 1             Reset pr ediction history for feature i
FI
None.
#GP(0) If CPL > 0 or (EAX AND NOT IA32_HRESET_ENABLE) ≠0.
#UD If CPUID.07H.01H:EAX.HRESET[bit 22] = 0.
#GP(0) HRESET instruction is not recognized in virtual-8086 mode.
Mode 
F3 0F 3A F0 C0 /ib 
HRESET imm8, <EAX> A V/V HRESET Processor history reset request. Controlled by the 
EAX implicit operand.
A N/A ModRM:r/m (r) N/A N/A N/AHRESET—History ResetINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-49164-Bit Mode Exceptions
Same exceptions as in protected mode. HSUBPD—Packed Double Precision Floating-Point Horizontal SubtractINSTRUCTION SET REFERENCE, A-L
3-492 Vol. 2AHSUBPD—Packed Double Precision Floating-Point Horizontal Subtract
The HSUBPD instruction subtracts horizo ntally the packed double precision floating-point numbers of both oper-
ands. 
Subtracts the double precision floating-point value in th e high quadword of the dest ination operand from the low 
quadword of the destination operand and stores the resu lt in the low quadword of the destination operand. 
Subtracts the double precision floating-point value in the high quadword of the source operand from the low quad-
word of the source operand and stores the result in the high quadword of the destination operand. 
See Figure 3-21 for HSUBPD; see Figure 3-22 for VHSUBPD.Opcode/
ModeCPUID 
Feature 
66 0F 7D /r
HSUBPD xmm1, xmm2/m128RM V/V SSE3 Horizontal subtract packed double precision 
xmm1.
VEX.128.66.0F.WIG 7D /r
VHSUBPD xmm1,xmm2, xmm3/m128RVM V/V AVX Horizontal subtract packed double precision 
VEX.256.66.0F.WIG 7D /r
VHSUBPD ymm1, ym m2, ymm3/m256RVM V/V AVX Horizontal subtract packed double precision 
ymm3/mem.
Figure 3-21.  HSUBPD—Packed Double Precision Floating-Point Horizontal SubtractOM15995HSUBPD xmm1, xmm2/m128
xmm1xmm2
Result:
xmm1xmm2/m128[63:0] -
xmm2/m128[127:64]xmm1[63:0] - xmm1[127:64]HSUBPD—Packed Double Precision Floating-Point Horizontal SubtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-493Figure 3-22.  VHSUBPD operation
zeroed.
Operation
HSUBPD (128-bit Le gacy SSE Version)
DEST[63:0] := SRC1[63:0] - SRC1[127:64] DEST[127:64] := SRC2[63:0] - SRC2[127:64] DEST[MAXVL-1:128 ] (Unmodified)
VHSUBPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] - SRC1[127:64] DEST[127:64] := SRC2[63:0] - SRC2[127:64] DEST[MAXVL-1:128] := 0
VHSUBPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] - SRC1[127:64] DEST[127:64] := SRC2[63:0] - SRC2[127:64] DEST[191:128] := SRC1[1 91:128] - SRC1[255:192]
DEST[255:192] := SRC2[1 91:128] - SRC2[255:192]
HSUBPD __m128d _mm_hsub_pd(__m128d a, __m128d b)
VHSUBPD __m256d _mm256_hsub_pd (__m256d a, __m256d b);
Overflow, Underflow, Invalid, Precision, Denormal.Y2 - Y3 X2 - X3 Y0 - Y1 X0 - X1 DESTX3 X2 SRC1 X1 X0
Y3 Y2 Y1 Y0 SRC2HSUBPD—Packed Double Precision Floating-Point Horizontal SubtractINSTRUCTION SET REFERENCE, A-L
3-494 Vol. 2AOther Exceptions
See Table 2-19, “Type 2 Class Exception Conditions.”HSUBPS—Packed Single Precision Floating-Point Horizontal SubtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-495HSUBPS—Packed Single Precision Fl oating-Point Horizontal Subtract
Subtracts the single precision floating-point value in the second dword of the destination operand from the first 
dword of the destination operand and stores the resu lt in the first dword of the destination operand. 
Subtracts the single precision floating-point value in the fourth dword of the destination operand from the third 
dword of the destination operand and stores the result in the second dword of the destination operand. 
Subtracts the single precision floating-point value in the second dword of the source operand from the first dword 
of the source operand and stores the result in  the third dword of th e destination operand. 
Subtracts the single precision floating-point value in the fourth dword of the source operand from the third dword 
of the source operand and stores the result in  the fourth dword of the destination operand. 
See Figure 3-23 for HSUBPS; see Figure 3-24 for VHSUBPS.Opcode/
ModeCPUID 
Feature 
F2 0F 7D /r
HSUBPS xmm1, xmm2/m128RM V/V SSE3 Horizontal subtract packed single precision 
xmm1.
VEX.128.F2.0F.WIG 7D /r
VHSUBPS xmm1, xmm2, xmm3/m128RVM V/V AVX Horizontal subtract packed single precision 
VEX.256.F2.0F.WIG 7D /r
VHSUBPS ymm1, ymm2, ymm3/m256RVM V/V AVX Horizontal subtract packed single precision 
ymm3/mem.
RVM ModRM:reg (w) VEX.vvv v (r) ModRM:r/m (r) N/AHSUBPS—Packed Single Precision Floating-Point Horizontal SubtractINSTRUCTION SET REFERENCE, A-L
3-496 Vol. 2AFigure 3-24.  VHSUBPS Operation
zeroed.
register or a 256-bit memory location. Th e destination operand is a YMM register. Figure 3-23.  HSUBPS—Packed Single Precision Floating-Point Horizontal SubtractOM15996HSUBPS xmm1, xmm2/m128
RESULT:
xmm1xmm2/
m128
xmm1[95:64] - 
xmm2/m128
[31:0] - xmm2/
xmm2/m128
[95:64] - xmm2/
Y6-Y7 X6-X7 Y2-Y3 X2-X3 DESTSRC1 X0
X0-X1 Y4-Y5 X4-X5 Y0-Y1HSUBPS—Packed Single Precision Floating-Point Horizontal SubtractINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-497Operation
HSUBPS (128-bit Legacy SSE Version)

zeroed.
RESULT:
xmm1xmm2/
m128
xmm2/m128
xmm2/m128
DEST[31:0] := SRC1[31:0] - SRC1[63:32]DEST[63:32] := SRC1[95:64] - SRC1[127:96]DEST[95:64] := SRC2[31:0] - SRC2[63:32]DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[MAXVL-1:128 ] (Unmodified)
VHSUBPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC1[63:32]DEST[63:32] := SRC1[95:64] - SRC1[127:96]DEST[95:64] := SRC2[31:0] - SRC2[63:32]DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[MAXVL-1:128] := 0
VHSUBPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC1[63:32]DEST[63:32] := SRC1[95:64] - SRC1[127:96]DEST[95:64] := SRC2[31:0] - SRC2[63:32]DEST[127:96] := SRC2[95:64] - SRC2[127:96] DEST[159:128] := SRC1[1 59:128] - SRC1[191:160]
DEST[191:160] := SRC1[2 23:192] - SRC1[255:224]
DEST[223:192] := SRC2[1 59:128] - SRC2[191:160]
DEST[255:224] := SRC2[2 23:192] - SRC2[255:224]
HSUBPS __m128 _mm_hsub_ps(__m128 a, __m128 b);
VHSUBPS __m256 _mm256_hsub_ps (__m256 a, __m256 b);
See Table 2-19, “Type 2 Class Exception Conditions.”IDIV—Signed DivideINSTRUCTION SET REFERENCE, A-L
3-498 Vol. 2AIDIV—Signed Divide
Divides the (signed) value in the AX, DX :AX, or EDX:EAX (dividend) by the so urce operand (divisor) and stores the 
result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a 
memory location. The action of this instruction depends on the operand size (dividend/divisor).
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64  bits. In 64-bit mode when REX.W is 
applied, the instruction divides the signed value in RD X:RAX by the source operand. RAX contains a 64-bit 
quotient; RDX contains a 64-bit remainder. 
See the summary chart at the beginning of this se ction for encoding data and limits. See Table 3-51.Opcode Instruction Op/ 
En64-Bit 
F6 /7 IDIV r/m8 M Valid Valid Signed divide AX by r/m8, with result stored in: 
AL := Quotient, AH  := Remainder.
REX + F6 /7 IDIV r/m81
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.M Valid N.E. Signed divide AX by r/m8, with result stored in 
F7 /7 IDIV r/m16 M Valid Valid Signed divide DX:AX by r/m16, with result 
F7 /7 IDIV r/m32 M Valid Valid Signed divi de EDX:EAX by r/m32, with result 
stored in EAX  := Quotient, EDX  := Remainder.
REX.W + F7 /7 IDIV r/m64 M Valid N.E. Signed divide RDX:RAX by r/m64, with result 
stored in RAX  := Quotient, RDX  := Remainder.
M ModRM:r/m (r) N/A N/A N/A
Table 3-51.  IDIV Results
Operand Size Dividend Divisor Quo tient Remainder Quotient Range
Word/byte AX r/m8 AL AH −128 to +127
Doubleword/word DX:AX r/m16 AX DX −32,768 to +32,767
Quadword/doubleword EDX:EAX r/m32 EAX EDX −231 to 231 − 1
Doublequadword/ quadwo rd RDX:RAX r/m64 RAX RDX −263 to 263 − 1IDIV—Signed DivideINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-499Operation
IF SRC = 0
FI;
IF OperandSize = 8 (* Word/byte operation *)
THEN
temp := AX / SRC; (*  Signed division *)
IF (temp > 7FH) or (temp < 80H) 
(* If a positive result is greater than 7FH or a negative  result is less than 80H *)
AL := temp;AH := AX SignedModulus SRC;
FI;
THEN
temp := DX:AX / SRC; (* Signed division *)IF (temp > 7FFFH) or (temp < 8000H) 
(* If a positive result  is greater than 7FFFH 
or a negative result is less than 8000H *)
THEN
#DE; (* Divide error *) 
ELSE
AX := temp;DX := DX:AX SignedModulus SRC;
FI;
FI;
ELSE IF OperandSize = 32 (* Quadword/doubleword operation *)
temp := EDX:EAX / SRC; (* Signed division *)
IF (temp > 7FFFFFFFH) or (temp < 80000000H) 
(* If a positive result is greater than 7FFFFFFFH or a negative result is less than 80000000H *)
THEN 
ELSE
EAX := temp;EDX := EDXE:AX SignedModulus SRC;
FI;
FI;
ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *)
temp := RDX:RAX / SRC; (* Signed division *)
IF (temp > 7FFFFFFFFFFFFFFFH) or (temp < 8000000000000000H) 
(* If a positive result is greater than 7FFFFFFFFFFFFFFFH or a negative result is less than 8000000000000000H *)
THEN 
ELSE
RAX := temp;RDX := RDE:RAX SignedModulus SRC;
FI;
FI;
FI;IDIV—Signed DivideINSTRUCTION SET REFERENCE, A-L
3-500 Vol. 2AFlags Affected
The CF, OF, SF, ZF, AF, and PF flags are undefined.
The signed result (quotient) is too large for the destination.
selector.
The signed result (quotient) is  too large for the destination.
#UD If the LOCK prefix is used.IMUL—Signed MultiplyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-501IMUL—Signed Multiply
Performs a signed multiplication of two operands. This instruction has three forms, depending on the number of 
operands. 
•One-operand form — This form is identical to that used by th e MUL instruction. Here, the source operand (in 
a general-purpose register or memory location) is multip lied by the value in the AL, AX, EAX, or RAX register 
(depending on the operand size) and the product (twice the size of the input operand) is stored in the AX, 
DX:AX, EDX:EAX, or RDX:RAX registers, respectively.
•Two-operand form — With this form the destination operand (the first operand) is multiplied by the source 
operand (second operand). The destination operand is a ge neral-purpose register and the source operand is an 
immediate value, a general-purpose register, or a memory location. The intermediate product (twice the size of 
the input operand) is truncated and stored in the destination operand location.
•Three-operand form — This form requires a destination operand (the first operand) and two source operands 
(the second and the third operands). Here, the first so urce operand (which can be a general-purpose register 
or a memory location) is multiplied by the second so urce operand (an immediate value). The intermediate 
product (twice the size of the first source operand) is truncated and stored in the destination operand (a 
general-purpose register).Opcode Instruction Op/ 
En64-Bit 
F6 /5 IMUL r/m81
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.MV a l i d V a l i d A X : =  A L  ∗ r/m byte.
F7 /5 IMUL r/m16 M Valid Valid DX:AX := AX ∗ r/m word.
F7 /5 IMUL r/m32 M Valid Valid EDX:EAX := EAX ∗ r/m32.
REX.W + F7 /5 IMUL r/m64 M Valid N.E. RDX:RAX := RAX ∗ r/m64.

En64-Bit 
NOTES:
0F AF /r IMUL r16, r/m16 RM Valid Valid word register := word register ∗ r/m16.
0F AF /r IMUL r32, r/m32 RM Valid Valid doubleword register := doubleword register ∗ 
r/m32.
REX.W + 0F AF /r IMUL r64, r/m64 RM Valid N.E. Quadword register := Quadword register ∗ 
r/m64.
6B /r ib IMUL r16, r/m16, imm8 RM I Valid Valid word register := r/m16 ∗ sign-extended 
immediate byte.
6B /r ib IMUL r32, r/m32, imm8 RMI Val id Valid doubleword register := r/m32 ∗ sign-
extended immediate byte.
REX.W + 6B /r ib IMUL r64, r/m64, imm8 RMI Valid N.E. Quadword register := r/m64 ∗ sign-extended 
69 /r iw IMUL r16, r/m16, imm16 RMI Valid Valid word register := r/m16 ∗ immediate word.
69 /r id IMUL r32, r/m32, imm32 RMI Va lid Valid doubleword register := r/m32 ∗ immediate 
doubleword.
REX.W + 69 /r id IMUL r64, r/m64, imm3 2 RMI Valid N.E. Quadword register := r/m64 ∗ immediate 
RMI ModRM:reg (r, w) ModRM:r/m (r) imm8/16/32 N/AIMUL—Signed MultiplyINSTRUCTION SET REFERENCE, A-L
3-502 Vol. 2AWhen an immediate value is used as an operand, it is  sign-extended to the length of the destination operand 
format.
The CF and OF flags are set when the signed integer va lue of the intermediate product differs from the sign 
extended operand-size-truncated product, otherwise the CF and OF flags are cleared.
The three forms of the IMUL instruction ar e similar in that the length of the product is calculated to twice the length 
of the operands. With the one-operand form, the product is stored exactly in  the destination. With the two- and 
three- operand forms, however, the result is truncated to the length of the destination before it is stored in the 
destination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits 
are lost. 
The two- and three-operand forms may also be used with unsigned operands because the lower half of the product 
is the same regardless if the operands are signed or unsi gned. The CF and OF flags, however, cannot be used to 
determine if the upper half of the result is non-zero.
tional registers (R8-R15). Use of the REX.W prefix promotes  operation to 64 bits. Use of REX.W modifies the three 
forms of the instruction as follows.
•One-operand form  —The source operand (in a 64-bit general-purpose register or memory location) is 
multiplied by the value in the RAX register and the product is stored in the RDX:RAX registers.
•Two-operand form — The source operand is promoted to 64 bits if it is a register or a memory location. The 
destination operand is promoted to 64 bits.
•Three-operand form — The first source operand (either a register or a memory location) and destination 
operand are promoted to 64 bits. If the source operand is an immediate, it is sign extended to 64 bits. 
Operation
IF (NumberOfOperands = 1)
THEN IF (OperandSize = 8)
THEN
TMP_XP := AL ∗ SRC (* Signed multipli cation; TMP_XP is a sign ed integer at twice the width of the SRC *); 
AX := TMP_XP[15:0];IF SignExtend(TMP_XP[7:0]) 
= TMP_XP
THEN CF := 0; OF := 0;ELSE CF := 1; OF := 1; FI;
= 16
THEN 
TMP_XP := AX ∗ SRC (* Signed multipli cation; TMP_XP is a sign ed integer at twice the width of the SRC *) 
DX:AX := TMP_XP[31:0];IF SignExtend(TMP_XP[15:0]) 
= TMP_XP
= 32 
THEN 
TMP_XP := EAX ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC*) 
EDX:EAX := TMP_XP[63:0];IF SignExtend(TMP_XP[31:0]) 
= TMP_XP
TMP_XP := RAX ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at  twice the width of the SRC *)
EDX:EAX := TMP_XP[127:0];IF SignExtend(TMP_XP[63:0]) 
= TMP_XP
FI;
FI;IMUL—Signed MultiplyINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-503ELSE IF (NumberOfOperands = 2)
THEN 
TMP_XP := DEST ∗ SRC (* Signed multiplication; TMP_XP is a si gned integer at twice the width of the SRC *)
DEST := TruncateToOperandSize(TMP_XP);IF SignExtend(DEST) 
≠ TMP_XP
THEN CF := 1; OF := 1;ELSE CF := 0; OF := 0; FI;
ELSE (* NumberOfOperands 
= 3 *)
TMP_XP := SRC1 ∗ SRC2 (* Signed multiplication ; TMP_XP is a signed integer at twice the width of the SRC1 *)
≠ TMP_XP
FI;
FI;
For the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the 
upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and 
three-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the 
destination operand size and cleared when the result fits exactly in the destination operand size. The SF, ZF, AF, and PF flags are undefined.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL NULL 
Same exceptions as in protected mode.IMUL—Signed MultiplyINSTRUCTION SET REFERENCE, A-L
3-504 Vol. 2A64-Bit Mode Exceptions
#UD If the LOCK prefix is used.IN—Input From PortINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-505IN—Input From Port
Copies the value from the I/O port specified with the se cond operand (source operand) to the destination operand 
(first operand). The source operand can be a byte-immedi ate or the DX register; the destination operand can be 
register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the 
DX register as a source operand allows I/O port addre sses from 0 to 65,535 to be accessed; using a byte imme-
diate allows I/O port addresses 0 to 255 to be accessed.
When accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port, 
the operand-size attribute determines the port size. At th e machine code level, I/O instructions are shorter when 
accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.
This instruction is only useful for accessing I/O ports lo cated in the processor’s I/O address space. See Chapter 19, 
“Input/Output,” in the Intel® 64 and IA-32 Architectures Software Deve loper’s Manual, Volume 1, for more infor-
mation on accessing I/O ports in the I/O address space.
Operation
IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
IF (Any I/O Permission Bit for I/O port being accessed = 1)
THEN (* I/O operation is not allowed *)
#GP(0);
ELSE ( * I/O operation is allowed *) 
DEST := SRC; (* Read fr om selected I/O port *)
FI;
ELSE (Real Mode or Pr otected Mode with CPL ≤ IOPL *)
FI;
En64-Bit 
E4 ib IN AL, imm8 I Valid Valid Input byte  from imm8 I/O port address into 
AL.
E5 ib IN AX, imm8 I Valid Valid Input word  from imm8 I/O port address into 
AX.
E5 ib IN EAX, imm8 I Valid Valid Input dword from imm8 I/O port address into 
EAX.
EC IN AL,DX ZO Valid Valid Input byte from I/O port in DX into AL.
ED IN AX,DX ZO Valid Valid Input word from I/O port in DX into AX.

Operation
#GP(0);
FI;
FI;
En64-Bit 
AL.
AX.
EAX.
ED IN EAX,DX ZO Valid Valid Input double word from I/O po rt in DX into 
EAX.
I imm8 N/A N/A N/A
ZO N/A N/A N/A N/AIN—Input From PortINSTRUCTION SET REFERENCE, A-L
3-506 Vol. 2AProtected Mode Exceptions
#GP(0) If the CPL is greater than (has less privileg e) the I/O privilege level (IOPL) and any of the 
corresponding I/O permission bits in TS S for the I/O port being accessed is 1.
#GP(0) If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.
#UD If the LOCK prefix is used.INC—Increment by 1INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-507INC—Increment by 1
Adds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a 
register or a memory location. This instruction allows a l oop counter to be updated without disturbing the CF flag. 
(Use a ADD instruction with an immediate operand of 1 to  perform an increment operation that does updates the 
CF flag.)
In 64-bit mode, INC r16 and INC r32 are not encodable (because opcodes 40H through 47H are REX prefixes). 
additional registers (R8-R15). Use of the RE X.W prefix promotes operation to 64 bits.
Operation
DEST := DEST + 1;
If the DS, ES, FS, or GS register is used to access memory and it contains a NULLsegment 
selector.
#UD If the LOCK prefix is used but th e destination is not a memory operand.Opcode Instruction Op/ 
En64-Bit 
FE /0 INC r/m8 M Valid Valid Increment r/m byte by 1.
REX + FE /0 INC r/m81
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.M Valid N.E. Increment r/m byte by 1.
FF /0 INC r/m16 M Valid Valid Increment r/m word by 1.FF /0 INC r/m32 M Valid Valid Increment r/m doubleword by 1.REX.W + FF /0 INC r/m64 M Valid N.E. Increment r/m quadword by 1.40+ rw
2
2. 40H through 47H are REX prefixes in 64-bit mode.INC r16 O N.E. Valid Increment word register by 1.
40+ rd INC r32 O N.E. Valid Increment doubleword register by 1.
O opcode + rd (r, w) N/A N/A N/AINC—Increment by 1INSTRUCTION SET REFERENCE, A-L
3-508 Vol. 2AReal-Address Mode Exceptions
#SS If a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used but the destination is not a memory operand.
#UD If the LOCK prefix is used but the destination is not a memory operand.INCSSPD/INCSSPQ—Increment Shadow Stack PointerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-509INCSSPD/INCSSPQ—Increment Shadow Stack Pointer
This instruction can be used to increment the current shad ow stack pointer by the operand size of the instruction 
times the unsigned 8-bit value specified by bits 7:0 in the source operand. The instruction performs a pop and discard of the first and last element on the shadow stack in  the range specified by the unsigned 8-bit value in bits 
7:0 of the source operand.
Operation
IF CPL = 3
IF (CR4.CET & IA32_U_CET.SH_STK_EN) = 0
ELSE
IF (CR4.CET & IA32_S_CET.SH_STK_EN) = 0
FI;
IF (operand si ze is 64-bit)
THEN
Range := R64[7:0];shadow_stack_load 8 bytes from SSP;IF Range > 0
              THEN shadow_stack _load 8 bytes from SSP + 8 * (Range - 1);
FI;SSP := SSP + Range * 8;
ELSE
Range := R32[7:0];shadow_stack_load 4 bytes from SSP;IF Range > 0
              THEN shadow_stack _load 4 bytes from SSP + 4 * (Range - 1);
FI;SSP := SSP + Range * 4;
FI;
None.
INCSSPD void _incsspd(int);INCSSPQ void _incsspq(int);Opcode/
Mode 
Feature 
F3 0F AE /05
INCSSPD r32R V/V CET_SS Increment SSP by 4 * r32[7:0].
F3 REX.W 0F AE /05
INCSSPQ r64R V/N.E. CET_SS Increment SSP by 8 * r64[7:0].
R N/A ModRM:r/m (r) N/A N/A N/AINCSSPD/INCSSPQ—Increment Shadow Stack PointerINSTRUCTION SET REFERENCE, A-L
3-510 Vol. 2AProtected Mode Exceptions
If CR4.CET = 0.IF CPL = 3 and IA32_U_CET.SH_STK_EN = 0.
IF CPL < 3 and IA32_S_CET.SH_STK_EN = 0.
#UD The INCSSP instruction is not recognized in real-address mode.
#UD The INCSSP instruction is not recognized in virtual-8086 mode.
Same exceptions as in protected mode.INS/INSB/INSW/INSD—Input from Port to StringINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-511INS/INSB/INSW/INSD—Input  from Port to String
Copies the data from the I/O port specified with the so urce operand (second operand) to the destination operand 
(first operand). The source operand is an I/O port address (from 0 to 65,535) that is read from the DX register. The destination operand is a memory location, the address of wh ich is read from either the ES:DI, ES:EDI or the RDI 
registers (depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The ES segment 
cannot be overridden with a segment override prefix.) The size of the I/O port being accessed (that is, the size of 
the source and destination operands) is determined by the op code for an 8-bit I/O port or by the operand-size attri-
bute of the instruction for a 16- or 32-bit I/O port.
operands” form. The explicit-operands form (specified wi th the INS mnemonic) allows the source and destination 
operands to be specified explicitly. Here, the source oper and must be “DX,” and the destination operand should be 
a symbol that indicates the size of the I/O port and the de stination address. This explicit-operands form is provided 
to allow documentation; however, note that the documentation provided by this form can be misleading. That is, 
the destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), 
but it does not have to specify the correct location . The location is always specified by the ES:(E)DI registers, 
which must be loaded correctly before the INS instruction is executed.
The no-operands form provides “short forms” of the byte , word, and doubleword versions of the INS instructions. 
Here also DX is assumed by the processor to be the sour ce operand and ES:(E)DI is assumed to be the destination 
operand. The size of the I/O port is specified with the choice of mnemonic: INSB (byte), INSW (word), or INSD 
(doubleword).

After the byte, word, or doubleword is transfer from the I/O port to the memory location, the DI/EDI/RDI register 
is incremented or decremented automatically according to th e setting of the DF flag in the EFLAGS register. (If the 
DF flag is 0, the (E)DI register is incremented; if the DF  flag is 1, the (E)DI register is decremented.) The (E)DI 
register is incremented or decremented by 1 for byte oper ations, by 2 for word operations, or by 4 for doubleword 
operations.Opcode Instruction Op/ 
En64-Bit 
6C INS m8, DX ZO Valid Valid Input byte from I/O port specified in DX into 
memory location specified in ES:(E)DI or RDI.
1
NOTES:
1. In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported. In non-64-bit mode, only 32-bit (EDI) and 16 -bit (DI) 
address sizes are supported.6D INS m16, DX ZO Valid Valid Input word from I/O port specified in DX into 
memory location specified in ES:(E)DI or RDI.1
6D INS m32, DX ZO Valid Valid Input doubleword from I/O port specified in DX 
into memory location specified in ES:(E)DI or 
RDI.1
6C INSB ZO Valid Valid Input byte from I/O port specified in DX into 
memory location specified with ES:(E)DI or RDI.
1
6D INSW ZO Valid Valid Input word from I/O port specified in DX into 
6D INSD ZO Valid Valid Input doubleword from I/O port specified in DX 
RDI.1
ZO N/A N/A N/A N/AINS/INSB/INSW/INSD—Input from Port to StringINSTRUCTION SET REFERENCE, A-L
3-512 Vol. 2AThe INS, INSB, INSW, and INSD instructions can be preceded  by the REP prefix for block input of ECX bytes, words, 
or doublewords. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” in Chapter 4 of the Intel® 
64 and IA-32 Architectures Software Developer’s Manual , Volume 2B, for a description of the REP prefix.
These instructions are only useful for accessing I/O ports located in the processor’s I/ O address space. See Chapter 
19, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more 
information on accessing I/O ports in the I/O address space.
In 64-bit mode, default address size is 64 bits, 32 bit a ddress size is supported usin g the prefix 67H. The address 
of the memory destination is specifie d by RDI or EDI. 16-bit address size is not supported in 64-bit mode. The 
operand size is not promoted.
These instructions may read from the I/O port without writ ing to the memory location if  an exception or VM exit 
occurs due to the write (e.g. #PF). If this would be prob lematic, for example because the I/O port read has side-
effects, software should ensure the write to the memo ry location does not cause an exception or VM exit.
Operation
IF ((PE = 1) and ((CPL > IOPL) or (VM  = 1)))
#GP(0);
ELSE (* I/O operation is allowed *) 
DEST := SRC; (* Re ad from I/O port *)
FI;
ELSE (Real Mode or Protected Mode with CPL IOPL *)
FI;
Non-64-bit Mode:
IF (Byte transfer)
THEN (E)DI := (E)DI + 1; 
ELSE (E)DI := (E)DI – 1; FI;
ELSE IF (Word transfer)
THEN IF DF  = 0
THEN (E)DI := (E)DI + 2; 
ELSE (E)DI := (E)DI – 2; FI;
ELSE (* Doubleword transfer *)
THEN (E)DI := (E)DI + 4; 
ELSE (E)DI := (E)DI – 4; FI;
FI;
FI;
FI64-bit Mode:
THEN (E|R)DI := (E|R)DI + 1; 
ELSE (E|R)DI := (E|R)DI – 1; FI;
THEN (E|R)DI := (E|R)DI + 4; INS/INSB/INSW/INSD—Input from Port to StringINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-513ELSE (E|R)DI := (E|R)DI – 4; FI;
FI;
FI;
None.
If the destination is located in a non-writable segment.
If an illegal memory operand effective address in the ES segments is given.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#GP(0) If the CPL is greater than (has less privileg e) the I/O privilege level (IOPL) and any of the 
#UD If the LOCK prefix is used.INSERTPS—Insert Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-514 Vol. 2AINSERTPS—Insert Scalar Single Precision Floating-Point Value
(register source form)
Copy a single precision scalar floating-point element into a 128-bit vector register. The immediate operand has 
three fields, where the ZMask bits specif y which elements of the destination w ill be set to zero, the Count_D bits 
specify which element of the destination will be overwritten with the scalar value, and for vector register sources 
the Count_S bits specify which element of the source will  be copied. When the scalar source is a memory operand 
the Count_S bits are ignored. 
(memory source form)Load a floating-point element from a 32-bit memory location  and destination operand it into the first source at the 
location indicated by the Count_D bits of the immediate op erand. Store in the destination and zero out destination 
elements based on the ZMask bi ts of the immediate operand. 
128-bit Legacy SSE version: The first source register is an XMM register. The second source operand is either an 
XMM register or a 32-bit memory location. The destination is not distinct from the first source XMM register and the 
upper bits ( MAXVL-1 :128) of the corresponding register destination are unmodified.
VEX.128 and EVEX encoded version: Th e destination and first source register is an XMM register. The second 
source operand is either an XMM register or a 32-bit me mory location. The upper bits (MAXVL-1:128) of the corre-
sponding register destination are zeroed.
If VINSERTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause 
an #UD exception.Opcode/
InstructionOp / En 64/32 bit 
Mode 
Feature 
66 0F 3A 21 /r ib
INSERTPS xmm1, xmm2/m32, imm8A V/V SSE4_1 Insert a single precision floating-point value selected by 
imm8 from xmm2/m32 into xmm1 at the specified 
destination element specified by imm8 and zero out 
destination elements in xmm1 as indicated in imm8.
VEX.128.66.0F3A.WIG 21 /r ib
VINSERTPS xmm1, xmm2, xmm3/m32, 
imm8B V/V AVX Insert a single precision floating-point value selected by 
imm8 from xmm3/m32 and merge with values in xmm2 
at the specified destination element specified by imm8 
and write out the result and zero out destination elements in xmm1 as  indicated in imm8.
EVEX.128.66.0F3A.W0 21 /r ib
imm8C V/V AVX512F Insert a single precision floating-point value selected by 
and write out the result and zero out destination 
elements in xmm1 as  indicated in imm8.
C Tuple1 Scalar ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) imm8INSERTPS—Insert Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-515Operation
VINSERTPS (VEX.128 and EVEX Encoded Version)
IF (SRC = REG) THEN COUNT_S := imm8[7:6]
ELSE COUNT_S := 0
COUNT_D := imm8[5:4]ZMASK := imm8[3:0]CASE (COUNT_S) OF
0: TMP := SRC2[31:0]1: TMP := SRC2[63:32]2: TMP := SRC2[95:64]3: TMP := SRC2[127:96]
ESAC;CASE (COUNT_D) OF
0: TMP2[31:0] := TMP
TMP2[127:32] := SRC1[127:32]
1: TMP2[63:32] := TMP
TMP2[31:0] := SRC1[31:0]TMP2[127:64] := SRC1[127:64]

2: TMP2[95:64] := TMP
TMP2[63:0] := SRC1[63:0]TMP2[127:96] := SRC1[127:96]
3: TMP2[127:96] := TMP
TMP2[95:0] := SRC1[95:0]
ESAC;
IF (ZMASK[0] = 1) THEN DEST[31:0] := 00000000H
ELSE DEST[31:0] := TMP2[31:0]
IF (ZMASK[1] = 1) THEN DEST[63:32] := 00000000H
ELSE DEST[63:32] := TMP2[63:32]
IF (ZMASK[2] = 1) THEN DEST[95:64] := 00000000H
ELSE DEST[95:64] := TMP2[95:64]
IF (ZMASK[3] = 1) THEN DEST[127:96] := 00000000H
ELSE DEST[127:96] := TMP2[127:96]
INSERTPS (128-bit Legacy SSE Version)
IF (SRC = REG) THEN  COUNT_S :=imm8[7:6]
ELSE COUNT_S :=0
0: TMP := SRC[31:0]1: TMP := SRC[63:32]2: TMP := SRC[95:64]3: TMP := SRC[127:96]
ESAC;
CASE (COUNT_D) OF
TMP2[127:32] := DEST[127:32]
TMP2[31:0] := DEST[31:0]TMP2[127:64] := DEST[127:64]
2: TMP2[95:64] := TMPINSERTPS—Insert Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-L
3-516 Vol. 2ATMP2[63:0] := DEST[63:0]
TMP2[127:96] := DEST[127:96]
TMP2[95:0] := DEST[95:0]
ESAC;
VINSERTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);
INSETRTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);
None.
Non-EVEX-encoded instruction, see Table 2-22, “Type 5 Class Exception Conditions,” additionally:
#UD If VEX.L = 0.EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions.”INT n/INTO/INT3/INT1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-517INT n/INTO/INT3/INT1—Call to Interrupt Procedure
The INT n instruction generates a call to the interrupt or ex ception handler specified with the destination operand 
(see the section titled “Interrupts and Exceptions” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1). The destination operand sp ecifies a vector from 0 to 255, encoded as an 8-bit 
unsigned intermediate value. Each vector provides an index to a gate descriptor in the IDT. The first 32 vectors are reserved by Intel for system use. Some of these ve ctors are used for internally generated exceptions.
The INT n instruction is the general mnemonic for executing a so ftware-generated call to an interrupt handler. The 
INTO instruction is a special mnemonic for calling overflow  exception (#OF), exception 4. The overflow interrupt 
checks the OF flag in the EFLAGS register and calls the over flow interrupt handler if the OF flag is set to 1. (The 
INTO instruction cannot be used in 64-bit mode.)
The INT3 instruction uses a one-byte opcode (CC) and is  intended for calling the de bug exception handler with a 
breakpoint exception (#BP). (This one-byte form is useful because it can replace the first byte of any instruction at 
which a breakpoint is desired, incl uding other one-byte instructions, without overwriting other instructions.)
The INT1 instruction also uses a one-byte opcode (F1) and generates a debug exception (#DB) without setting any 
bits in DR6.
1 Hardware vendors may use the INT1 instruction fo r hardware debug. For that reason, Intel recom-
mends software vendors instead use the INT3 instruction for software breakpoints.
An interrupt generated by the INTO, INT3, or INT1  instruction differs from one generated by INT n in the following 
ways: 
•The normal IOPL checks do not occur in virtual-8086 mode. The interrupt is taken (without fault) with any IOPL 
value.
•The interrupt redirection enabled by the virtual-8086 mode  extensions (VME) does not occur. The interrupt is 
always handled by a protected-mode handler.
(These features do not pertain to CD03, the “normal” 2-by te opcode for INT 3. Intel and Microsoft assemblers will 
not generate the CD03 opcode from any mnemonic, but this  opcode can be created by direct numeric code defini-
tion or by self-modifying code.)
The action of the INT n instruction (including the INTO, INT3, and INT1 instructions) is similar to that of a far call 
made with the CALL instru ction. The primary difference is that with the INT n instruction, the EFLAGS register is 
pushed onto the stack before the return  address. (The return address is a far address consisting of the current 
values of the CS and EIP registers.) Returns from interrupt  procedures are handled with the IRET instruction, which 
pops the EFLAGS information and return address from the stack.
Each of the INT n, INTO, and INT3 instructions generates a general- protection exception (#GP) if the CPL is greater 
than the DPL value in the selected gate descriptor in the IDT. In contrast, the INT1 instruction can deliver a #DB Opcode Instruction Op/ 
En64-Bit 
CC INT3 ZO Valid Valid Generate breakpoint trap.
CD ib INT imm8 I Valid Valid Generate software interrupt with vector 
specified by immediate byte.
CE INTO ZO Invalid Valid Generate overfl ow trap if overflow flag is 1.
F1 INT1 ZO Valid Valid Generate debug trap.
1. The mnemonic ICEBP has also been used for the instruction with opcode F1.INT n/INTO/INT3/IN T1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
3-518 Vol. 2Aeven if the CPL is greater than the DPL of descriptor 1 in the IDT. (This behavior supports the use of INT1 by hard-
ware vendors performing hardware debug.)
The vector specifies an interrupt descriptor in the interrupt descriptor table (IDT); that is, it provides index into the 
IDT. The selected interrupt descriptor in turn contains a pointer to an interrupt or exception handler procedure. In protected mode, the IDT contains an array of 8-byte de scriptors, each of which is an interrupt gate, trap gate, 
or task gate. In real-address mode, the IDT is an array of 4-byte far pointers (2-byte code segment selector and 
a 2-byte instruction pointer), each of which point directly  to a procedure in the selected segment. (Note that in 
real-address mode, the IDT is called the interrupt vector table , and its pointers are called interrupt vectors.) 
The following decision table indicates which action in the lo wer portion of the table is taken given the conditions in 
the upper portion of the table. Each Y in the lower sectio n of the decision table represents a procedure defined in 
the “Operation” section for this instruction (except #GP).
When the processor is executing in virtual-8086 mode, the IO PL determines the action of the INT n instruction. If 
the IOPL is less than 3, the processor generates a #GP(select or) exception; if the IOPL is 3, the processor executes 
a protected mode interrupt to privilege level 0. The interrupt  gate's DPL must be set to 3 and the target CPL of the 
interrupt handler procedure must be 0 to execute the protected mode interrupt to privilege level 0.
The interrupt descriptor table register (IDTR) specifies the base linear address and limit of the IDT. The initial base 
address value of the IDTR after the pr ocessor is powered up or reset is 0.
Refer to Chapter 6, “Procedu re Calls, Interrupts, and Exceptions” and Ch apter 17, “Control-flow Enforcement Tech-
nology (CET)” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for CET details.Table 3-52.  Decision Table
PE 01 1 1 1 1 1 1
VM –– – – – 0 1 1
IOPL –– – – – – < 3 = 3
DPL/CPL 
RELATIONSHIP–D P L <
CPL–D P L >
CPLDPL=
CPL or CDPL<
CPL & NC––
INTERRUPT TYPE –S / W – – – – – –
GATE TYPE – – Task Trap or 
InterruptTrap or 
Interrupt
REAL-ADDRESS-MODE Y
PROTECTED-MODE YY Y Y Y Y Y
TRAP-OR-INTERRUPT-
GATEYYYYY
INTER-PRIVILEGE-LEVEL-
INTERRUPTY
INTRA-PRIVILEGE-LEVEL-
INTERRUPT-FROM-
VIRTUAL-8086-MODEY
TASK-GATE Y
#GP YY Y
NOTES:
− Don't Care.
YY e s ,  a c t i o n  t a k e n .
Blank  Action not taken.
S/W  Applies to INT n, INT3, and INTO, but not to INT1.INT n/INTO/INT3/INT1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-519Instruction ordering.  Instructions following an INT n may be fetched from memory before earlier instructions 
complete execution, but they will not execute (even specul atively) until all instructions prior to the INT n have 
become globally visible). This applies also to the INTO, INT3, and INT1 instructions, but not to executions of INTO 
when EFLAGS.OF = 0.
Operation

Interrupt
GATEYYYYY
#GP YY Y
NOTES:
Operation
The following operational description applies not only to the INT n, INTO, INT3, or INT1 instructions, but also to 
external interrupts, nonmaskable interrupts (NMIs), and exce ptions. Some of these events push onto the stack an 
error code.
The operational description specifies numerous checks whose failure may result in delivery of a nested exception. 
In these cases, the original event is not delivered.
The operational description specifies the error code deliver ed by any nested exception. In some cases, the error 
code is specified with a pseudofunction error_code(num,i dt,ext), where idt and ext are bit values. The pseudofunc-
tion produces an error code as follows: (1) if idt is 0, th e error code is (num & FCH) | ext; (2) if idt is 1, the error 
code is (num « 3) | 2 | ext.
In many cases, the pseudofunction error_code is invoked with a pseudovariable EXT. The value of EXT depends on 
the nature of the event whose delivery encountered a nested  exception: if that event is a software interrupt (INT n, 
INT3, or INTO), EXT is 0; otherwise (including INT1), EXT is 1.
IF PE = 0
THEN 
GOTO REAL-ADDRESS-MODE;
ELSE (* PE = 1 *)
IF (EFLAGS.VM = 1 AND CR4.VME = 0 AND IOPL < 3 AND INT n) 
THEN 
 #GP(0); (* Bit 0 of erro r code is 0 because INT n *)
ELSE
IF (EFLAGS.VM = 1 AND CR4.VME = 1 AND INT n)
THEN
Consult bit n of the software interrupt redirection bit map in the TSS;
IF bit n is clear
THEN (* redirect interrupt to 8086 program interrupt handler *)
Push EFLAGS[15:0]; (* if IOPL < 3, save VIF in  IF position and save IOPL position as 3 *)
Push CS;Push IP;IF IOPL = 3
THEN IF := 0; (* Clear interrupt flag *)ELSE VIF := 0; (* Clear virtual interrupt flag *)
FI;TF := 0; (* Clear trap flag *)load CS and EIP (lower 16 bits only) from entry n in interrupt vector ta ble referenced from TSS;
ELSE
IF IOPL = 3
THEN GOTO PROTECTED-MODE;ELSE #GP(0); (* Bit 0 of er ror code is 0 because INT n *)
FI;
FI;
ELSE (* Protected mode, IA-32e mode, or virtual-8086 mode interrupt *)
IF (IA32_EFER.LMA 
= 0)
THEN (* Protected mode, or virtual-8086 mode interrupt *)
GOTO PROTECTED-MODE;
ELSE (* IA-32e mode interrupt *)GOTO IA-32e-MODE;INT n/INTO/INT3/IN T1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
3-520 Vol. 2AFI;
FI;
FI;
FI;REAL-ADDRESS-MODE:
IF ((vector_number « 2) + 3)  is not within IDT limit 
THEN #GP; FI;
IF stack not large enough for a 6-byte return information 
THEN #SS; FI;
Push (EFLAGS[15:0]);IF := 0; (* Clear interrupt flag *)TF := 0; (* Clear trap flag *)AC := 0; (* Clear AC flag *)Push(CS);Push(IP);(* No error codes are pushed in real-address mode*)CS := IDT(Descriptor (vec tor_number « 2), selector));
EIP := IDT(Descriptor (vector_number « 2), offset)); (* 16 bit offset AND 0000FFFFH *)
END;PROTECTED-MODE:
IF ((vector_number « 3) + 7)  is not within IDT limits
or selected IDT descriptor is not an  interrupt-, trap-, or task-gate type
THEN #GP(error_code(vec tor_number,1,EXT)); FI;
(* idt operand to error_code set because vector is used *)
IF software interrupt (* Generated by INT n, INT3, or INTO; does not apply to INT1 *)
THEN
IF gate DPL < CPL (* PE = 1, DPL < CPL, software interrupt *)
THEN #GP(error_code(vector_number,1,0)); FI;(* idt operand to error_code set because vector is used *)
(* ext operand to error_code is 0 because INT n, INT3, or INTO*)
FI;IF gate not present 
THEN #NP(error_code(vec tor_number,1,EXT)); FI;
IF task gate (* Specif ied in the selected inte rrupt table descriptor *)
THEN GOTO TASK-GATE;ELSE GOTO TRAP-OR-INTERRUPT-GATE; (* PE = 1, trap/interrupt gate *)
FI;
END;IA-32e-MODE:
IF INTO and CS.L = 1 (64-bit mode)
THEN #UD;
FI;IF ((vector_number « 4) + 15) is not in IDT limits
or selected IDT descriptor is no t an interrupt-, or trap-gate type
THEN #GP(error_code(v ector_number,1,EXT));
FI;IF software interrupt (* Generated by INT n, INT3, or INTO; does not apply to INT1 *)
THEN
THEN #GP(error_code(vector_number,1,0));(* idt operand to error_code set because vector is used *)
(* ext operand to error_code is 0 because INT n, INT3, or INTO*)INT n/INTO/INT3/INT1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-521FI;
THEN #NP(error_code(v ector_number,1,EXT));
FI;GOTO TRAP-OR-INTERRUPT-GATE; (* Trap/interrupt gate *)
END;TASK-GATE: (* PE
 = 1, task gate *)
Read TSS selector in task  gate (IDT descriptor);
IF local/global bit is set to lo cal or index not within GDT limits
THEN #GP(error_code(TSS selector,0,EXT)); FI;(* idt operand to error_code is  0 because selector is used *)
Access TSS descriptor in GDT;IF TSS descriptor specifies that the TSS is busy (low-o rder 5 bits set to 00001)
THEN #NP(error_code(TSS  selector,0,EXT)); FI;
(* idt operand to error_code is  0 because selector is used *)
SWITCH-TASKS (with nesting) to TSS;IF interrupt caused by fault with error code
THEN
IF stack limit does not allow push of error code
THEN #SS(EXT); FI;
Push(error code);
FI;IF EIP not within code segment limit 
THEN #GP(EXT); FI;
END;TRAP-OR-INTERRUPT-GATE:
Read new code-segment selector for trap or interrupt gate (IDT descriptor);IF new code-segment selector is NULL
THEN #GP(EXT); FI; (* Error co de contains NULL selector *)
IF new code-segment selector is not within its descriptor table limits 
THEN #GP(error_code(new code-s egment selector,0,EXT)); FI;
Read descriptor referenced by new code-segment selector;IF descriptor does not indicate a code segment or new code-segment DPL > CPL
IF new code-segment descriptor is not present, 
THEN #NP(error_code(new code-s egment selector,0,EXT)); FI;
IF new code segment is non-conforming with DPL < CPL
THEN 
IF VM
 = 0
THEN 
GOTO INTER-PRIVILEG E-LEVEL-INTERRUPT; 
(* PE = 1, VM = 0, interrupt or tr ap gate, nonconforming code segment,
DPL < CPL *)
ELSE (* VM =  1 *)
IF new code-segment DPL ≠ 0 
THEN #GP(error_code(new code -segment selector,0,EXT));INT n/INTO/INT3/IN T1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
3-522 Vol. 2A(* idt operand to error_code is 0 because selector is used *)
GOTO INTERRUPT-FROM-VIRTUAL-8086-MODE; FI;(* PE
 = 1, interrupt or trap gate, DPL < CPL, VM  = 1 *)
FI;
ELSE (* PE  = 1, interrupt or trap gate, DPL ≥ CPL *)
IF VM = 1 
THEN #GP(error_code(new code -segment selector,0,EXT));
(* idt operand to error_code is 0 because selector is used *)
IF new code segment is conforming or new code-segment DPL  = CPL
THEN 
GOTO INTRA-PRIVILEG E-LEVEL-INTERRUPT; 
ELSE (* PE  = 1, interrupt or trap gate, noncon forming code segment, DPL > CPL *)
#GP(error_code(new code-s egment selector,0,EXT));
FI;
FI;
END;INTER-PRIVILEGE- LEVEL-INTERRUPT:
(* PE = 1, interrupt or trap gate, no n-conforming code segment, DPL < CPL *)
IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)
THEN(* Identify stack-segment selector for new privilege level in current TSS *)
THEN 
TSSstackAddress := (new code-segment DPL « 3) + 4;IF (TSSstackAddress + 5) > current TSS limit
THEN #TS(error_code(current TSS selector,0,EXT)); FI;(* idt operand to error_code is 0 because selector is used *)
NewSS := 2 bytes loaded from (T SS base + TSSstackAddress + 4);
ELSE (* current TSS is 16-bit *)
TSSstackAddress := (new code-segment DPL « 2) + 2IF (TSSstackAddress + 3) > current TSS limit
NewSS := 2 bytes loaded from (T SS base + TSSstackAddress + 2);
FI;IF NewSS is NULL
THEN #TS(EXT); FI; 
IF NewSS index is not within  its descriptor-table limits
or NewSS RPL 
≠ new code-segment DPL 
THEN #TS(error_code(NewSS,0,EXT)); FI;(* idt operand to error_code is 0 because selector is used *)
Read new stack-segmen t descriptor for NewSS in GDT or LDT;
IF new stack-segment DPL 
or new stack-segment Type does not indicate writable data segment
IF NewSS is not present 
THEN #SS(error_code (NewSS,0,EXT)); FI;
(* idt operand to error_code is 0 because selector is used *)NewSSP := IA32_PLi_S SP (* where i = new code-segment DPL *)
ELSE (* IA-32e mode *)INT n/INTO/INT3/INT1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L

Vol. 2A 3-523IF IDT-gate IST = 0
THEN TSSstackAddress := (new code-segment DPL « 3) + 4;ELSE TSSstackAddress := (I DT gate IST « 3) + 28;
FI;IF (TSSstackAddress + 7) > current TSS limit
THEN #TS(error_code(current TSS selector,0,EXT); FI;(* idt operand to error_code is  0 because selector is used *)
NewRSP := 8 bytes loaded from (current TSS base + TSSstackAddress);NewSS := new code-segment DPL; (* NULL selector with RPL = new CPL *)IF IDT-gate IST = 0
THEN
NewSSP := IA32_PLi_S SP (* where i = new code-segment DPL *)
ELSE
NewSSPAddress = IA32_INTERRUPT_SSP _TABLE_ADDR + (IDT-gate IST « 3)
(* Check if shadow stacks are enabled at CPL 0 *)IF ShadowStackEnabled(CPL 0)
THEN NewSSP := 8 bytes load ed from NewSSPAddress; FI;
FI;
FI;IF IDT gate is 32-bit 
THEN
IF new stack does not have room for 24 bytes (error code pushed) or 20 bytes (no error code pushed)
THEN #SS(error_code(NewSS,0,EXT)); FI;(* idt operand to error_code is  0 because selector is used *)
FI
ELSE 
IF IDT gate is 16-bit 
THEN
IF new stack does not have room for 12 bytes (error code pushed) or 10 bytes (no error code pushed);
ELSE (* 64-bit IDT gate*)
IF StackAddress is non-canonical
THEN #SS(EXT); FI; (* Error code contains NULL selector *)
FI;
FI;IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)
THEN
IF instruction pointer from IDT gate is  not within new code-segment limits 
THEN #GP(EXT); FI; (* Error code contains NULL selector *)
ESP := NewESP;SS := NewSS; (* Segment descriptor information also loaded *)
ELSE (* IA-32e mode *)
IF instruction pointer from IDT gate contains a non-canonical address
RSP := NewRSP & FFFFFFFFFFFFFFF0H;SS := NewSS;
FI;IF IDT gate is 32-bit
THEN 
CS:EIP := Gate(CS:EIP); (* Segment descriptor information also loaded *)
ELSE INT n/INTO/INT3/IN T1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
3-524 Vol. 2AIF IDT gate 16-bit
THEN 
CS:IP := Gate(CS:IP); (* Segment descriptor information also loaded *)
ELSE (* 64-bit IDT gate *)
CS:RIP := Gate(CS:RIP); (* Segment descriptor information also loaded *)
FI;
THEN
Push(far pointer to old stack); (* Old SS and ESP, 3 words padded to 4 *)Push(EFLAGS);Push(far pointer to return instruction); (* Old CS and EIP, 3 words padded to 4 *)Push(ErrorCode); (* If needed, 4 bytes *)
ELSE
IF IDT gate 16-bit
THEN
Push(far pointer to old stack); (* Old SS and SP, 2 words *)Push(EFLAGS(15:0]);Push(far pointer to return instruction); (* Old CS and IP, 2 words *)Push(ErrorCode); (* If needed, 2 bytes *)
Push(far pointer to old stack); (* Old SS and SP, each an 8-byte push *)Push(RFLAGS); (* 8-byte push *)Push(far pointer to return instruction); (* Old CS and RIP, ea ch an 8-byte push *)
Push(ErrorCode); (* If needed, 8-bytes *)
FI;
THEN
FI;
FI;CPL := new code-segment DPL;CS(RPL) := CPL;IF ShadowStackEnabled(CPL)
oldSSP := SSPSSP := NewSSPIF SSP & 0x07 != 0
(* Token and CS:LIP:oldSSP pushed on shadow stack must be contained in a naturally aligned 32-byte region *)IF (SSP & ~0x1F) != ((SSP 
– 24) & ~0x1F)
IF ((IA32_EFER.LMA and CS.L) = 0 AND SSP[63:32] != 0)INT n/INTO/INT3/INT1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-525THEN #GP(0); FI;
ShadowStackPush8B(oldCSBASE + oldRIP); (* Padded with 32 high-order bits of 0 for 32 bit LIP*)ShadowStackPush8B(oldSSP);
FI;
FI;IF IDT gate is interrupt gate
THEN IF := 0 (* Interrupt flag se t to 0, interrupts disabled *); FI;
TF := 0;VM := 0;RF := 0;NT := 0;
END;INTERRUPT-FROM-VIRTUAL-8086-MODE:
(* Identify stack-segment selector for privilege level 0 in current TSS *)IF current TSS is 32-bit
THEN 
IF TSS limit < 9
THEN #TS(error_code(current TSS selector,0,EXT)); FI;(* idt operand to error_code is  0 because selector is used *)
NewSS := 2 bytes loaded from (current TSS base + 8);NewESP := 4 bytes loaded from (current TSS base + 4);
IF TSS limit < 5
NewSS := 2 bytes loaded from (current TSS base + 4);NewESP := 2 bytes loaded from (current TSS base + 2);
THEN #TS(EXT); FI; (*  Error code contains  NULL selector *)
IF NewSS index is not within its descriptor table limitsor NewSS RPL
 ≠ 0
THEN #TS(error_code(NewSS,0,EXT)); FI;(* idt operand to error_code is  0 because selector is used *)
≠ 0 or stack segment does not in dicate writable data segment
IF new stack segm ent not present 
NewSSP := IA32_P L0_SSP (* the new code-s egment DPL must be 0 *)
IF IDT gate is 32-bit
THENINT n/INTO/INT3/IN T1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
3-526 Vol. 2AIF new stack does not have room for 40 bytes (error code pushed) 
or 36 bytes (no error code pushed)
ELSE (* IDT gate is 16-bit) 
IF new stack does not have room for 20 bytes (error code pushed) or 18 bytes (no error code pushed)
FI;IF instruction pointer from IDT gate is  not within new code-segment limits 
tempEFLAGS := EFLAGS;VM := 0;TF := 0;RF := 0;NT := 0;IF service through interrupt gate 
THEN IF = 0; FI;
TempSS := SS;TempESP := ESP;SS := NewSS;ESP := NewESP;(* Following pushes are 16 bits for 16-bit IDT gates and 32 bits for 32-bit IDT gates; Segment selector pushes in 32-bit mode are padded to two words *)Push(GS);Push(FS);Push(DS);Push(ES);Push(TempSS);Push(TempESP);Push(TempEFlags);Push(CS);Push(EIP);GS := 0; (* Segment registers made NULL, invalid for use in protected mode *)FS := 0;DS := 0;ES := 0;CS := Gate(CS); (* Segment descriptor information also loaded *)CS(RPL) := 0;CPL := 0;IF IDT gate is 32-bit
THEN
EIP := Gate(instr uction pointer);
ELSE (* IDT gate is 16-bit *)
EIP := Gate(instruction pointer) AND 0000FFFFH;
FI;IF ShadowStackEnabled(0)
– 24) & ~0x1F)INT n/INTO/INT3/INT1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-527#GP(0); FI;
expected_token_value = SSP (* busy bit - bit position 0 - must be clear *)new_token_value = SSP | BUSY_BIT (* Set the busy bit *)IF shadow_stack_lock_cmpx chg8b(SSP, new_token_value, expected_token_value) != expected_token_value
FI;
(* Start execution of new routine in Protected Mode *)END;
INTRA-PRIVILEGE-LEVEL-INTERRUPT:
NewSSP = SSP;CHECK_SS_TOKEN = 0(* PE = 1, DPL = CPL or conforming segment *)IF IA32_EFER.LMA = 1 (* IA-32e mode *)
IF IDT-descriptor IST ≠ 0
THEN
TSSstackAddress := (IDT-d escriptor IST « 3) + 28;
IF (TSSstackAddress + 7) > TSS limit
NewRSP := 8 bytes loaded from (current TSS base + TSSstackAddress);
ELSE NewRSP := RSP; 
FI;IF IDT-descriptor IST ≠ 0
THEN
NewSSPAddress = IA32_INTERRUPT_SSP _TABLE_ADDR + (IDT gate IST « 3)
NewSSP := 8 bytes load ed from NewSSPAddress
CHECK_SS_TOKEN = 1
FI;
FI;
FI;IF 32-bit gate (* implies IA32_EFER.LMA = 0 *)
THEN
IF current stack does not have room  for 16 bytes (error code pushed) 
or 12 bytes (no error code pushed)
ELSE IF 16-bit gate (* im plies IA32_EFER.LMA = 0 *) 
IF current stack does not have room for 8 bytes (error code pushed) or 6 bytes (no error code pushed)
ELSE (* IA32_EFER.LMA = 1, 64-bit gate*)

THEN
THEN
FI;
FI;
THEN
IF NewRSP contains a non-canonical address
THEN #SS(EXT); (* Error code contains NULL selector *)
FI;
3-528 Vol. 2AIF instruction pointer from IDT gate is not within new code-segment limit 
ELSE
RSP := NewRSP & FFFFFFFFFFFFFFF0H;
FI;IF IDT gate is 32-bit (* implies IA32_EFER.LMA = 0 *)
THEN
Push (EFLAGS);Push (far pointer to return instru ction); (* 3 words padded to 4 *)
CS:EIP := Gate(CS:EIP); (* Segment descriptor information also loaded *)Push (ErrorCode); (* If any *)
ELSE
IF IDT gate is 16-bit (* implies IA32_EFER.LMA = 0 *) 
THEN
Push (FLAGS);Push (far pointer to return  location); (* 2 words *)
CS:IP := Gate(CS:IP); (* Segment descriptor information also loaded *)Push (ErrorCode);  (* If any *)
Push(ErrorCode); (* If needed, 8 bytes *)
CS:RIP := GATE(CS:RIP); (* Segment descriptor information also loaded *)
FI;
FI;CS(RPL) := CPL;IF ShadowStackEnabled(CPL)
IF CHECK_SS_TOKEN == 1
THEN
IF NewSSP & 0x07 != 0
(* Token and CS:LIP:oldSSP pushed on shadow stack must be contained in a naturally aligned 32-byte region *)IF (NewSSP & ~0x1F) != ((NewSSP 
IF ((IA32_EFER.LMA and CS.L) = 0 AND NewSSP[63:32] != 0)
    THEN #GP(0); FI;
expected_token_value = NewSSP (* busy bit - bit position 0 - must be clear *)new_token_value = NewSSP | BUSY_BIT (* Set the busy bit *)IF shadow_stack_lock_cmpxchg8b(NewS SP, new_token_value, expected_tok en_value) != expe cted_token_value
FI;(* Align to next 8 byte boundary *)tempSSP = SSP;Shadow_stack_store 4 bytes of 0 to (NewSSP 
− 4)
SSP = newSSP & 0xFFFFFFFFFFFFFFF8H;(* push cs:lip:ssp on shadow stack *)INT n/INTO/INT3/INT1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-529ShadowStackPush8B(oldCS); (* Padded with 48 high-order bits of 0 *)
ShadowStackPush8B(oldCSBASE + oldRIP); (* Padded with 32 high-order bits of 0 for 32 bit LIP*)ShadowStackPush8B(tempSSP);
IF CPL = 3
THEN
ELSE
FI;
FI;IF IDT gate is interrupt gate 
THEN IF := 0; FI; (* Interrupt flag  set to 0; interrupts disabled *)
TF := 0;NT := 0;VM := 0;RF := 0;
END;
The EFLAGS register is pushed onto the stack. The IF, TF , NT, AC, RF, and VM flags may be cleared, depending on 
the mode of operation of the processor when the INT instru ction is executed (see the “Operation” section). If the 
interrupt uses a task gate, any flags may be set or cleare d, controlled by the EFLAGS image in the new task’s TSS.
#GP(error_code) If the instruction pointer in the IDT or in  the interrupt, trap, or task gate is beyond the code 
segment limits.
If the segment selector in the interrupt, trap, or task gate is NULL.
If an interrupt, trap, or task gate, code segment, or TSS segment selector index is outside its 
descriptor table limits.
If the vector selects a descriptor outside the IDT limits.
If an IDT descriptor is not an interrupt, trap, or task gate.If an interrupt is generated by the INT n, INT3, or INTO instruction and the DPL of an interrupt, 
trap, or task gate is less than the CPL.
If the segment selector in an interrupt or trap gate does not point to a segment descriptor for 
a code segment.
If the segment selector for a TSS has its local/global bit set for local.
If a TSS segment descriptor specifies that the TSS is busy or not available.If SSP in IA32_PLi_SSP (where i is the new CPL) is not 8 byte aligned.
If destination mode is 32-bit or compatibility mode, but SSP address in “supervisor shadow 
IA32_PLi_SSP (where i is the new CPL).INT n/INTO/INT3/IN T1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
3-530 Vol. 2A#SS(error_code) If pushing the return address, flags, or  error code onto the stack exceeds the bounds of the 
stack segment and no stack switch occurs.
If the SS register is being loaded and th e segment pointed to is marked not present.
If pushing the return address, flags, error co de, or stack segment pointer exceeds the bounds 
of the new stack segment when a stack switch occurs.
#NP(error_code) If code segment, interrupt gate, trap gate, task gate, or TSS is not present.
#TS(error_code) If the RPL of the stack segment selector in  the TSS is not equal to the DPL of the code segment 
being accessed by the interrupt or trap gate.
If DPL of the stack segment descriptor pointed to  by the stack segment selector in the TSS is 
not equal to the DPL of the code segment descriptor for the interrupt or trap gate.
If the stack segment selector in the TSS is NULL.If the stack segment for the TSS is not a writable data segment.
#AC(EXT) If alignment checking is  enabled, the gate DPL is 3, and a stack push is unaligned.
If the interrupt vector number is outside the IDT limits.
#SS If stack limit violation on push.
If pushing the return address, flags, or erro r code onto the stack exceeds the bounds of the 
stack segment.
#GP(error_code) (For INT n, INTO, or BOUND instruction) If the IOPL is  less than 3 or the DPL of the interrupt, 
trap, or task gate is not equal to 3.
If the instruction pointer in the IDT or in the interrupt, trap, or task gate is beyond the code 
If a interrupt gate, trap gate, task gate, code  segment, or TSS segment selector index is 
outside its descriptor table limits.
If an IDT descriptor is not an interrupt, trap, or task gate.If an interrupt is generated by INT n, INT3, or INTO and the DPL of an interrupt, trap, or task 
gate is less than the CPL.
#SS(error_code) If the SS register is being loaded and the segment pointed to is marked not present.
If pushing the return address, flags, error co de, stack segment pointer, or data segments 
exceeds the bounds of the stack segment.
#NP(error_code) If code segment, interrupt gate, trap gate, task gate, or TSS is not present.INT n/INTO/INT3/INT1—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-531#TS(error_code) If the RPL of the stack segment selector in  the TSS is not equal to the DPL of the code segment 
If DPL of the stack segment descriptor for the TSS’s stack segment is not equal to the DPL of 
the code segment descriptor for the interrupt or trap gate.
#PF(fault-code) If a page fault occurs.#OF If the INTO instruction is executed and the OF flag is set.
#GP(error_code) If the instruction pointer in the 64-b it interrupt gate or trap gate is non-canonical.
If the segment selector in the 64-bit  interrupt or trap gate is NULL.
If the vector points to a gate which is in non-canonical space.If the vector points to a descriptor which is no t a 64-bit interrupt gate or a 64-bit trap gate.
If the descriptor pointed to by the gate se lector is outside the descriptor table limit.
If the descriptor pointed to by the gate  selector is in non-canonical space.
If the descriptor pointed to by the ga te selector is not a code segment.

If the descriptor pointed to by the gate selector  doesn’t have the L-bit set, or has both the L-
bit and D-bit set.
If the descriptor pointed to by the gate selector has DPL > CPL.
If “supervisor shadow stack” token on new shadow stack is marked busy.
#SS(error_code) If a push of the old EFLAGS, CS selector, EIP, or error code is in non-canonical space with no 
stack switch.
If a push of the old SS selector, ESP, EFLAGS, CS selector, EIP, or error code is in non-canonical 
space on a stack switch (either CPL change or no-CPL with IST).
#NP(error_code) If the 64-bit interrupt-gate, 64-bit trap-gate, or code segment is not present.
#TS(error_code) If an attempt to load RSP from the TSS causes an access to non-canonical space.
If the RSP from the TSS is outside descriptor table limits. 
#UD If the LOCK prefix is used.#AC(EXT) If alignment checking is  enabled, the gate DPL is 3, and a stack push is unaligned.INVD—Invalidate Internal CachesINSTRUCTION SET REFERENCE, A-L
3-532 Vol. 2AINVD—Invalidate Internal Caches
Invalidates (flushes) the processor’s internal caches and i ssues a special-function bus cycle that directs external 
caches to also flush themselves. Data held in internal caches is not written back to main memory. 
After executing this instruction, the processor does not wait  for the external caches to complete their flushing oper-
ation before proceeding with instruction execution. It is th e responsibility of hardware to respond to the cache flush 
signal.
The INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a 
program or procedure must be 0 to execute this instruction.
The INVD instruction may be used when the cache is used  as temporary memory and the cache contents need to 
be invalidated rather than written back to memory. When  the cache is used as temporary memory, no external 
device should be actively writing data to main memory. 
Use this instruction with care. Data cached internally and not written back to main memory will be lost. Note that 
any data from an external device to main memory (for example, via a PCIWrite) can be  temporarily stored in the 
caches; these data can be lost when an INVD instruction is executed. Unless there is a specific requirement or 
benefit to flushing caches without writing back modified cache lines (for example, te mporary memory, testing, or 
fault recovery where cache coherency with main memory is not a concern), software should instead use the WBINVD instruction.
On processors that support processor reserved memory, the INVD instruction cannot be executed when processor 
reserved memory protections are activated. See Section 36.5, “EPC and Management of EPC Pages,” in the Intel
® 
64 and IA-32 Architectures Software  Developer’s Manual, Volume 3D.
Some processors prevent execution of INVD after BIOS ex ecution is complete. They report this by enumerating 
CPUID.(EAX=07H,ECX=1H ):EAX[bit 30] as 1. On such processors, INVD cannot be executed if bit 0 of 
SR_BIOS_DONE (MSR address 151H) is 1.
The INVD instruction is implementation dependent; it may be implemented differently on different families of Intel 
64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor.
Operation
Flush(InternalCaches);
SignalFlush(ExternalCaches);Continue (* Continue execution *)
NOTES:
1. See the IA-32 Architecture Compatibility section below.Instruction Op/ 
En64-Bit 
0F 08 INVD ZO Valid Valid Flush internal caches; initiate flushing of 
external caches.
ZO N/A N/A N/A N/AINVD—Invalidate Internal CachesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-533Protected Mode Exceptions
If the processor reserved memory protections are activated.If CPUID.(EAX=07H, ECX=1H):EAX[30] = 1 an d bit 0 is set in MSR_BIOS_DONE (MSR 
address 151H).
#GP(0) If CPUID.(EAX=07H, ECX= 1H):EAX[30] = 1 and bit 0 is set in MSR_BIOS_DONE (MSR 
If the processor reserved memory protections are activated.
#GP(0) The INVD instruction cannot be executed in virtual-8086 mode.
Same exceptions as in protected mode.INVLPG—Invalidate TLB EntriesINSTRUCTION SET REFERENCE, A-L
3-534 Vol. 2AINVLPG—Invalidate TLB Entries
Invalidates any translation lookaside buffer (TLB) entries sp ecified with the source operand. The source operand is 
a memory address. The processor determines the page that  contains that address and flushes all TLB entries for 
that page.1
The INVLPG instruction is a privileged instruction. When the processor is running in protected mode, the CPL must 
be 0 to execute this instruction.
The INVLPG instruction normally flushes TLB entries only for the specified page; however, in some cases, it may 
flush more entries, even the entire TLB. The instruction invalidates TLB entries associated with the current PCID 
and may or may not do so for TLB entries associated wi th other PCIDs. (If PCIDs are disabled — CR4.PCIDE = 0 — 
the current PCID is 000H.) The instruction also invalidate s any global TLB entries for the specified page, regardless 
of PCID.
For more details on operations that flush the TLB, see “MOV—Move to/from Control Registers” in the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 2B, and Section 4.10.4.1, “Operations that Invalidate 
TLBs and Paging-Structure Caches,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
3A.
This instruction’s operation is the same in all non-64-bit modes. It also operates the same in 64-bit mode, except 
if the memory address is in non-canonical form . In this case, INVLPG is the same as a NOP.
The INVLPG instruction is implementation dependent, and its function may be implemented differently on different 
families of Intel 64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the 
Operation
Invalidate(RelevantTLBEntries);
Continue; (* Continue execution *)
None.
#UD Operand is a register.
If the LOCK prefix is used.Opcode1
NOTES:
En64-Bit 
0F 01/7 INVLPG m M Valid Valid Invalidate TLB entries for page containing m.
1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that  page 
(see Section 4.10.2.3, “Details of TLB Use,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A), the 
instruction invalidates all of them.INVLPG—Invalidate TLB EntriesINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-535Real-Address Mode Exceptions
#GP(0) The INVLPG instruction cannot be executed at the virtual-8086 mode.
#GP(0) If the current privilege level is not 0.#UD Operand is a register.
If the LOCK prefix is used.INVPCID—Invalidate Process-Context IdentifierINSTRUCTION SET REFERENCE, A-L
3-536 Vol. 2AINVPCID—Invalidate Proc ess-Context Identifier
Invalidates mappings in the translation lookaside buffers  (TLBs) and paging-structure caches based on process-
context identifier (PCID). (See Section 4.10 , “Caching Translation Information,” in the Intel 64 and IA-32 Architec-
ture Software Developer’s Manual, Volume 3A .) Invalidation is based on the INVPCID type specified in the register 
operand and the INVPCID descriptor specified in the memory operand.
Outside 64-bit mode, the register operand is always 32 bi ts, regardless of the value of CS.D. In 64-bit mode the 
register operand has 64 bits.
There are four INVPCID types currently defined:

•Individual-address invalidation: If the INVPCID type is  0, the logical processor invalidates mappings—except 
global translations—for the linear address and PCID specified in the INVPCID descriptor.1 In some cases, the 
instruction may invalidate global translations or mappings  for other linear addresses (or other PCIDs) as well.
•Single-context invalidation: If the INVPCID type is 1, the logical processor invalidates all mappings—except 
global translations—associated with the PCID specified in the INVPCID descriptor. In some cases, the 
instruction may invalidate global translations or mappings for other PCIDs as well.
•All-context invalidation, including global translations: If the INVPCID type is 2, the logical processor invalidates 
all mappings—including global translations—associated with any PCID. 
•All-context invalidation: If the INVPCID type is 3, the logical processor invalidates all mappings—except global translations—associated with any PCID. In some case, the instruction may invalidate global translations as well. 
The INVPCID descriptor comprises 128 bits and consists of  a PCID and a linear address as shown in Figure 3-25. 
For INVPCID type 0, the processor uses the full 64 bits of  the linear address even outside 64-bit mode; the linear 
address is not used for other INVPCID types.Opcode/Instruction Op/ 
En64/32-
66 0F 38 82 /r
INVPCID r32, m128RM N.E./V INVPCID Invalidates entries in the TLBs and paging-structure 
caches based on invalidation type in r32 and descrip-
tor in m128.
INVPCID r64, m128RM V/N.E. INVPCID Invalidates entries in the TLBs and paging-structure 
caches based on invalidation type in r64 and descrip-
instruction invalidates all of them.Figure 3-25.  INVPCID Descriptor127 64 63 0 1112
Reserved (must be zero) Linear Address PCIDINVPCID—Invalidate Process-Context IdentifierINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-537If CR4.PCIDE = 0, a logical processor does not cache in formation for any PCID other than 000H. In this case, 
executions with INVPCID types 0 and 1 are allowed only if  the PCID specified in the INVPCID descriptor is 000H; 
executions with INVPCID types 2 and 3 invalidate mappings  only for PCID 000H. Note that CR4.PCIDE must be 0 
outside IA-32e mode (see Section 4.10.1, “Process-Context Identifiers (PCIDs),” of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 3A).
Operation
INVPCID_TYPE := value of register oper and; // must be in the range of 0–3
INVPCID_DESC := valu e of memory operand;
CASE INVPCID_TYPE OF
0: // individual-address invalidation
PCID := INVPCID_DESC[11:0];L_ADDR := INVPCI D_DESC[127:64];
Invalidate mappings for L_ADDR associated with PCID except global translations;BREAK;
1: // single PCID invalidation
PCID := INVPCID_DESC[11:0];Invalidate all mappings associated with PCID except global translations;BREAK;
2: // all PCID invalidation including global translations
Invalidate all mappings for all PCIDs, including global translations;
BREAK;
3: // all PCID invalidation retaining global translations
Invalidate all mappings for all PC IDs except global translations;
BREAK;
ESAC;
INVPCID void _invpcid(unsigned __int32 type, void * descriptor);
None.
If the memory operand effective address is ou tside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the source operand is located in an execute-only code segment.If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.
If bits 63:12 of INVPCID_DESC are not all zero.
If INVPCID_TYPE is either 0 or 1 and INVPCID_DESC[11:0] is not zero.If INVPCID_TYPE is 0 and the linear addres s in INVPCID_DESC[127:64] is not canonical.
#PF(fault-code) If a page fault occurs  in accessing the memory operand.
If the SS register contains an unusable segment.
#UD If if CPUID.(EAX=07H, ECX= 0H):EBX.INVPCID[bit 10] = 0.
3-538 Vol. 2AReal-Address Mode Exceptions
#GP If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.
If bits 63:12 of INVPCID_DESC are not all zero.If INVPCID_TYPE is either 0 or 1 and INVPCID_DESC[11:0] is not zero.
If INVPCID_TYPE is 0 and the linear addre ss in INVPCID_DESC[127:64] is not canonical.
#UD If CPUID.(EAX=07H, ECX=0H ):EBX.INVPCID[bit 10] = 0.
#GP(0) The INVPCID instruction is no t recognized in virtual-8086 mode.
If the memory operand is in the CS, DS, ES, FS , or GS segments and the memory address is 
If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.
If bits 63:12 of INVPCID_DESC are not all zero.If CR4.PCIDE=0, INVPCID_TYPE is either 0 or 1, and INVPCID_DESC[11:0] is not zero.
#SS(0) If the memory destination operand is in th e SS segment and the memory address is in a non-
canonical form.
If CPUID.(EAX=07H, ECX=0H ):EBX.INVPCID[bit 10] = 0.IRET/IRETD/IRETQ—Interrupt ReturnINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-539IRET/IRETD/IRETQ—Interrupt Return
Returns program control from an exception or interrupt ha ndler to a program or procedure that was interrupted by 
an exception, an external interrupt, or a software-generated  interrupt. These instructions  are also used to perform 
a return from a nested task. (A nested task is created when  a CALL instruction is used to initiate a task switch or 
when an interrupt or exception causes a task switch to an interrupt or exception hand ler.) See the section titled 
“Task Linking” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 3A.
IRET and IRETD are mnemonics for the same opcode. The IR ETD mnemonic (interrupt return double) is intended 
for use when returning from an interrupt when using th e 32-bit operand size; however, most assemblers use the 
IRET mnemonic interchangeably for both operand sizes.
In Real-Address Mode, the IRET instruction performs a far return to the interrupted pr ogram or procedure. During 
this operation, the processor pops the return instruction pointer, return code segment selector, and EFLAGS image 
from the stack to the EIP, CS, and EFLAGS registers, re spectively, and then resumes execution of the interrupted 
program or procedure.
In Protected Mode, the action of the IRET instruction depe nds on the settings of the NT (nested task) and VM flags 
in the EFLAGS register and the VM flag in the EFLAGS im age stored on the current stack. Depending on the setting 
of these flags, the processor performs the following types of interrupt returns:
•Return from virtual-8086 mode.
•Return to virtual-8086 mode.
•Intra-privilege level return.
•Inter-privilege level return.
•Return from nested task (task switch).
If the NT flag (EFLAGS register) is cleared, the IRET inst ruction performs a far return from the interrupt procedure, 
without a task switch. The code segment being returned to  must be equally or less privileged than the interrupt 
handler routine (as indicated by the RPL field of the code segment selector popped from the stack). 
As with a real-address mode interrupt re turn, the IRET instruction pops the retu rn instruction pointer, return code 
segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then 
resumes execution of the interrupted prog ram or procedure. If the return is to another privilege level, the IRET 
instruction also pops the stack pointer and SS from the stack, before resuming program execution. If the return is 
to virtual-8086 mode, the processor also pops the data segment registers from the stack.
If the NT flag is set, the IRET instruction performs a task  switch (return) from a nested task (a task called with a 
CALL instruction, an interrupt, or an exception) back to  the calling or interrupted task. The updated state of the

CALL instruction, an interrupt, or an exception) back to  the calling or interrupted task. The updated state of the 
task executing the IRET instruction is saved in its TSS. If th e task is re-entered later, the code that follows the IRET 
instruction is executed.
If the NT flag is set and the processor is in IA-32e mo de, the IRET instruction causes a general protection excep-
tion.
If nonmaskable interrupts (NMIs) are blocked (see Se ction 6.7.1, “Handling Mult iple NMIs” in the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 3A), execution of the IRET instruction unblocks NMIs. Opcode Instruction Op/ 
En64-Bit 
CF IRET ZO Valid Valid Interrupt return (16-bit operand size).
CF IRETD ZO Valid Valid Interrupt return (32-bit operand size).REX.W + CF IRETQ ZO Valid N.E. Interrupt return (64-bit operand size).
ZO N/A N/A N/A N/AIRET/IRETD/IRETQ—Interrupt ReturnINSTRUCTION SET REFERENCE, A-L
3-540 Vol. 2AThis unblocking occurs even if the instruction causes a fault. In such a case, NMIs are unmasked before the excep-
tion handler is invoked.
In 64-bit mode, the instruction’s default operation size is 32  bits. Use of the REX.W prefix promotes operation to 64 
bits (IRETQ). See the summary chart at the beginning  of this section for encoding data and limits. 
nology (CET)” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for CET details.
Instruction ordering.  IRET is a serializing instructio n. See Section 9.3 of the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3A.
See “Changes to Instruction Behavior in VMX No n-Root Operation” in Chapter 26 of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 3C, for more  information about the behavior of this instruction in 
Operation
IF PE = 0
THEN GOTO REAL-ADDRESS-MODE;
ELSIF (IA32_EFER.LMA = 0)
THEN
IF (EFLAGS.VM = 1)
THEN GOTO RETURN-FROM-VIRTUAL-8086-MODE;ELSE GOTO PROTECTED-MODE;
FI;
ELSE GOTO IA-32e-MODE;
FI;
REAL-ADDRESS-MODE;
THEN
EIP := Pop();CS := Pop(); (* 32-bit pop, high-order 16 bits discarded *)tempEFLAGS := Pop();EFLAGS := (tempEFLAGS AND 257FD5H) OR (EFLAGS AND 1A0000H);
= 16 *)
EIP := Pop(); (* 16-bit pop; clear upper 16 bits *)
CS := Pop(); (* 16-bit pop *)EFLAGS[15:0] := Pop();
FI;END;
RETURN-FROM-VIRTUAL-8086-MODE: 
(* Processor is in virtual-8086 mode when IRET is executed and stays in  virtual-8086 mode *)
IF IOPL 
= 3 (* Virtual mode: PE = 1, VM = 1, IOPL = 3 *)
THEN IF OperandSize = 32
THEN
EIP := Pop();CS := Pop(); (* 32-bit pop, high-order 16 bits discarded *)EFLAGS := Pop();(* VM, IOPL,VIP and VIF EFLAG bits not modified by pop *)IF EIP not within CS limit
= 16 *)
CS := Pop(); (* 16-bit pop *)EFLAGS[15:0] := Pop(); (* IOPL in  EFLAGS not modified by pop *)IRET/IRETD/IRETQ—Interrupt ReturnINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-541IF EIP not within CS limit
FI;
ELSE 
#GP(0); (* Trap to virtual-8086 monitor: PE  = 1, VM = 1, IOPL < 3 *)
FI;
END;
PROTECTED-MODE:
IF NT = 1
THEN GOTO TASK-RETURN; (* PE = 1, VM = 0, NT = 1 *)
FI;IF OperandSize
 = 32
THEN
EIP := Pop();CS := Pop(); (* 32-bit pop, high-order 16 bits discarded *)tempEFLAGS := Pop();
= 16 *)
EIP := Pop(); (* 16-bit pop; clear upper bits *)
CS := Pop(); (* 16-bit pop *)tempEFLAGS := Pop(); (* 16-bit pop; clear upper bits *)
FI;IF tempEFLAGS(VM) 
= 1 and CPL = 0
THEN GOTO RETURN-TO-VIRTUAL-8086-MODE; ELSE GOTO PROTECTED-MODE-RETURN;
FI;
TASK-RETURN: (* PE 
= 1, VM  = 0, NT = 1 *)
SWITCH-TASKS (without nesting) to TSS specified in link field of current TSS;Mark the task just abandoned as NOT BUSY;IF EIP is not wi thin CS limit
END;
RETURN-TO-VIRTUAL-8086-MODE: 
(* Interrupted procedure was in virtual-8086 mode: PE 
= 1, CPL=0, VM  = 1 in flag image *)
(* If shadow stack or indirect bran ch tracking at CP L3 then #GP(0) *)
IF CR4.CET AND (IA32_U_CET.END BR_EN OR IA32_U _CET.SHSTK_EN)
shadowStackEnabled = ShadowStackEnabled(CPL)IF EIP not within CS limit
EFLAGS := tempEFLAGS;ESP := Pop();SS := Pop(); (* Pop 2 words; throw away high-order word *)
ES := Pop(); (* Pop 2 words; throw away high-order word *)
DS := Pop(); (* Pop 2 words; throw away high-order word *)
FS := Pop(); (* Pop 2 words; throw away high-order word *)
GS := Pop(); (* Pop 2 words; throw away high-order word *)
IF shadowStackEnabled
(* check if 8 byte aligned *)IF SSP AND 0x7 != 0
THEN #CP(FAR-RET/IRET); FI;
FI;IRET/IRETD/IRETQ—Interrupt ReturnINSTRUCTION SET REFERENCE, A-L
3-542 Vol. 2ACPL := 3;
(* Resume execution in  Virtual-8086 mode *)
tempOldSSP = SSP;(* Now past all faulting points; safe to free th e token. The token free is done using the old SSP
 * and using a supervisor override as ol d CPL was a supervisor  privilege level *)
expected_token_value = tempOldSSP | BUSY_BIT  (*  busy bit - bit positi on 0 - must be set *)
new_token_value = tempOldSSP  (* clear the busy bit *)
shadow_stack_lock_cmpxchg8b(tempOldSSP, new_token_value, expected_token_value)
FI;
END;
PROTECTED-MODE-RETURN: (* PE 
= 1 *)
IF CS(RPL) > CPL
THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL; FI;
END;
RETURN-TO-OUTER-PRIVILEGE-LEVEL:
 = 32
THEN
tempESP := Pop();tempSS := Pop(); (* 32-bit pop, high-order 16 bits discarded *)
= 16 
THEN
tempESP := Pop(); (* 16-bit pop; clear upper bits *)tempSS := Pop(); (* 16-bit pop *)
= 64 *)
tempRSP := Pop();tempSS := Pop(); (* 64-bit pop, high-order 48 bits discarded *)
FI;IF new mode 
≠ 64-Bit Mode
THEN
IF EIP is not within CS limit
ELSE (* new mode = 64-bit mode *)
IF RIP is non-canonical
FI;EFLAGS (CF, PF, AF, ZF, SF, TF , DF, OF, NT) := tempEFLAGS;
= 32 or OperandSize = 64
THEN EFLAGS(RF, AC, ID) := tempEFLAGS; FI;
IF CPL ≤ IOPL 
THEN EFLAGS(IF) := tempEFLAGS; FI;
IF CPL = 0
THEN
EFLAGS(IOPL) := tempEFLAGS;IF OperandSize 
THEN EFLAGS(VIF, VIP)  := tempEFLAGS; FI;
(* check if 8 byte aligned *)IF SSP AND 0x7 != 0IRET/IRETD/IRETQ—Interrupt ReturnINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-543THEN #CP(FAR-RET/IRET); FI;
IF CS(RPL) != 3
THEN
tempSsCS = shadow_stack_load 8 bytes from SSP+16;tempSsLIP = shadow_stack_l oad 8 bytes from SSP+8;
tempSSP = shadow_stack_load 8 bytes from SSP;SSP = SSP + 24;(* Do 64 bit compare to detect  bits beyond 15 being set *)
tempCS = CS; (* zero padded to 64 bit *)
IF tempCS != tempSsCS
(* Do 64 bit compare; pad CSBASE +RIP with 0 for 32 bit LIP *)
IF CSBASE + RIP != tempSsEIP
(* check if 4 byte aligned *)IF tempSSP AND 0x3 != 0
FI;
FI;tempOldCPL = CPL;CPL := CS(RPL);
THEN
RSP := tempRSP;SS := tempSS;
ELSE
ESP := tempESP;SS := tempSS;
FI;IF new mode != 64-Bit Mode
THEN
FI;tempOldSSP = SSP;IF ShadowStackEnabled(CPL)
IF CPL = 3
THEN tempSSP := IA32_PL3_SSP; FI;
IF ((IA32_EFER.LMA AND CS.L) = 0 AND tempSSP[63:32] != 0) OR
((IA32_EFER.LMA AND CS.L) = 1 AND tempSSP is not ca nonical relative to th e current paging mode)
SSP := tempSSPFI;(* Now past all faulting points; safe to free th e token. The token free is  done using the old SSP
 * and using a supervisor override as old CPL was a supervisor privilege level *)IF ShadowStackEnabled(tempOldCPL)
expected_token_value = tempOldSSP | BUSY_BIT (*  busy bit - bit positi on 0 - must be set *)
3-544 Vol. 2AFOR each SegReg in (ES, FS, GS, and DS)
DO
tempDesc := descriptor cache for SegReg (* hidden part of segment register *)IF (SegmentSelector == NULL) OR (tempDesc(DPL) < CPL AND tempDesc(Type) is (data or non-conforming code)))
THEN (* Segment register invalid *)
SegmentSelector := 0; (*Segment selector becomes null*)
FI;
OD;
END;
RETURN-TO-SAME-PRIVI LEGE-LEVEL: (* PE 
= 1, RPL = CPL *)
IF new mode ≠ 64-Bit Mode
THEN
IF OperandSize =  32 or OperandSize = 64
IF CPL ≤ IOPL
IF CPL = 0 
  THEN 
 EFLAGS(IOPL) := tempEFLAGS; IF OperandSize = 32 or OperandSize = 64
 FI;
IF SSP AND 0x7 != 0 (* check if aligned to 8 bytes *)

DO
FI;
OD;
END;
THEN
IF CPL = 0 
  THEN 
 FI;
tempSSP = shadow_stack_load 8 bytes from SSP;SSP = SSP + 24;tempCS = CS; (* zero padded to 64 bit *)
IF tempCS != tempSsCS (* 64 bit comp are; CS zero padded to 64 bits *)
IF CSBASE + RIP != tempSsLIP (* 64  bit compare; CSBASE+RIP zero pa dded to 64 bit for 32 bit LIP *)
IF tempSSP AND 0x3 != 0 (* check if aligned to 4 bytes *)
IF IA32_EFER.LMA = 1(* In IA-32e-mode the IRET may be switching st acks if the interrupt/exception was delivered
 through an IDT with a non-zero IST *)(* In IA-32e mode for same CPL IR ET there is always a stack switch. The below check verifies if the 
 stack switch was to self stack and if so, do not tr y to free the token on th is shadow stack. If the IRET/IRETD/IRETQ—Interrupt ReturnINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-545 tempSSP was not to same stack th en there was a stack switch so do attempt to free the token *)
IF tempSSP != SSP
THEN 
expected_token_value = SSP | BUSY_BIT (* bu sy bit - bit position 0 - must be set *)
new_token_value = SSP (* clear the busy bit *)shadow_stack_lock_cm pxchg8b(SSP, new_token_value, expected_token_value)
FI;
FI;SSP := tempSSP
FI;
END;
IA-32e-MODE:
IF NT = 1
THEN #GP(0);
ELSE IF OperandSize
 = 32
THEN
EIP := Pop();CS := Pop();tempEFLAGS := Pop();
= 16 
THEN
FI;
= 64 *)
THEN
RIP := Pop();CS := Pop(); (* 64-bit pop, high-order 48 bits discarded *)tempRFLAGS := Pop();
FI;IF CS.RPL > CPL
THEN GOTO RETURN-TO- OUTER-PRIVILEGE-LEVEL;
ELSE
IF instruction began in 64-Bit Mode
THEN
 = 32
THEN
ESP := Pop();SS := Pop(); (* 32-bit pop, high-order 16 bits discarded *)
= 16 
THEN
ESP := Pop(); (* 16-bit pop; clear upper bits *)SS := Pop(); (* 16-bit pop *)
= 64 *)
RSP := Pop();SS := Pop(); (* 64-bit pop, high-order 48 bits discarded *)
FI;
FI;GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL; FI;
END;IRET/IRETD/IRETQ—Interrupt ReturnINSTRUCTION SET REFERENCE, A-L
3-546 Vol. 2AFlags Affected
All the flags and fields in the EFLAGS register are potent ially modified, depending on th e mode of operation of the 
processor. If performing a return from a nested task to  a previous task, the EFLAGS register will be modified 
according to the EFLAGS image stored in the previous task’s TSS.
#GP(0) If the return code or stack segment selector is NULL.
If the return instruction pointer is no t within the return code segment limit.
#GP(selector) If a segment selector index is outside its descriptor table limits.
If the return code segment sele ctor RPL is less than the CPL.
If the DPL of a conforming-code segment is gr eater than the return code segment selector 
RPL.
If the DPL for a nonconforming-code segment is  not equal to the RPL of the code segment 
selector.
If the stack segment descriptor DPL is not equal to the RPL of the return code segment 
selector.
If the stack segment is not a writable data segment.If the stack segment selector RPL is not equal to  the RPL of the return code segment selector.
If the segment descriptor for a code segment does not indicate it is a code segment.
If the segment selector for a TSS has its local/global bit set for local.If a TSS segment descriptor specifies that the TSS is not busy.
If a TSS segment descriptor specifies that the TSS is not available.
#SS(0) If the top bytes of stack are not within stack limits.
If the return stack segment is not present.
#NP (selector) If the return code segment is not present.
#PF(fault-code) If a page fault occurs.#AC(0) If an unaligned memory reference occurs when the CPL is 3 and alignment checking is 
enabled.
#UD If the LOCK prefix is used.#CP (Far-RET/IRET)If the previous SSP from shadow st ack (when returning to CPL <3) or from IA32_PL3_SSP 
(returning to CPL 3) is not 4 byte aligned.
If returning to 32-bit or compatibility mode and the previous SSP from shadow stack (when 
returning to CPL <3) or from IA32_PL3_SS P (returning to CPL 3) is beyond 4GB.
If return instruction pointer from stack and shadow stack do not match.
#GP If the return instruction pointer is no t within the return code segment limit.
#SS If the top bytes of stack are not within stack limits.
#GP(0) If the return instruction pointer is not within the return code segment limit.
IF IOPL not equal to 3.
#AC(0) If an unaligned memory reference occurs and alignment checking is enabled.#UD If the LOCK prefix is used.IRET/IRETD/IRETQ—Interrupt ReturnINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-547Compatibility Mode Exceptions
#GP(0) If EFLAGS.NT[bit 14] = 1.
Other exceptions same as in Protected Mode.
If the return code segment selector is NULL.
If the stack segment selector is NULL  going back to compatibility mode.
If the stack segment selector is NULL going back to CPL3 64-bit mode.
If a NULL stack segment selector RPL is not equa l to CPL going back to non-CPL3 64-bit mode.
If the return instruction pointer is not within the return code segment limit.If the return instruction pointer is non-canonical.
#GP(Selector) If a segment selector index is outside its descriptor table limits.
If a segment descriptor memory address is non-canonical.
If the proposed new code segment descriptor has both the D-bit and L-bit set.If the DPL for a nonconforming-code segment is  not equal to the RPL of the code segment 
selector.
If CPL is greater than the RPL of the code segment selector.If the DPL of a conforming-code segment is gr eater than the return code segment selector 
RPL.
If the stack segment is not a writable data segment.If the stack segment descriptor DPL is not eq ual to the RPL of the return code segment 
selector.
If the stack segment selector RPL is not equal to  the RPL of the return code segment selector.
#SS(0) If an attempt to pop a value off the stack violates the SS limit.
If an attempt to pop a value off the stack causes a non-canonical address to be referenced.
#AC(0) If an unaligned memory reference occurs when the CPL is 3 and alignment checking is 
enabled.
#CP (Far-RET/IRET)If the previous SS P from shadow stack (when returning to CPL <3) or from IA32_PL3_SSP 
returning to CPL <3) or fr om IA32_PL3_SSP (returning to CPL 3) is beyond 4GB.
If return instruction pointer from stack and shadow stack do not match.Jcc—Jump if Condition Is MetINSTRUCTION SET REFERENCE, A-L
3-548 Vol. 2AJcc—Jump if Condition Is Met
En64-Bit 
77 cb JA rel8 D Valid Valid Jump short if above (CF=0 and ZF=0).
73 cb JAE rel8 D Valid Valid Jump short if above or equal (CF=0).72 cb JB rel8 D Valid Valid Jum p short if below (CF=1).
76 cb JBE rel8 D Valid Valid Jump short if below or equal (CF=1 or ZF=1).
72 cb JC rel8 D Valid Valid Jump short if carry (CF=1).E3 cb JCXZ rel8 D N.E. Valid Jump short if CX register is 0.
E3 cb JECXZ rel8 D Valid Valid Jump short if ECX register is 0.E3 cb JRCXZ rel8 D Valid N.E. Jump short if RCX register is 0.74 cb JE rel8 D Valid Valid Jum p short if equal (ZF=1).
7F cb JG rel8 D Valid Valid Jump short if greater (ZF=0 and SF=OF).
7D cb JGE rel8 D Valid Valid Jump short if greater or equal (SF=OF).
7C cb JL rel8 D Valid Valid Jump short if less (SF
≠ OF).
7E cb JLE rel8 D Valid Valid Jump short if less or equal (ZF=1 or SF ≠ OF).
76 cb JNA rel8 D Valid Valid Jump shor t if not above (CF=1 or ZF=1).
72 cb JNAE rel8 D Valid Valid Jump short if not above or equal (CF=1).73 cb JNB rel8 D Valid Valid Jump short if not below (CF=0).
77 cb JNBE rel8 D Valid Valid Jump shor t if not below or equal (CF=0 and 
ZF=0).
73 cb JNC rel8 D Valid Valid Jump short if not carry (CF=0).75 cb JNE rel8 D Valid Valid Jump short if not equal (ZF=0).7E cb JNG rel8 D Valid Valid Jump short if not greater (ZF=1 or SF
≠ OF).
7C cb JNGE rel8 D Valid Valid Jump sh ort if not greater or equal (SF ≠ OF).
7D cb JNL rel8 D Valid Valid Jum p short if not less (SF=OF).

≠ OF).
ZF=0).
≠ OF).
7F cb JNLE rel8 D Valid Valid Jump shor t if not less or equal (ZF=0 and 
SF=OF).
71 cb JNO rel8 D Valid Valid Jump sh ort if not overflow (OF=0).
7B cb JNP rel8 D Valid Valid Jump short if not parity (PF=0).
79 cb JNS rel8 D Valid Valid Jump short if not sign (SF=0).
75 cb JNZ rel8 D Valid Valid Jump short if not zero (ZF=0).
70 cb JO rel8 D Valid Valid Jump short if overflow (OF=1).7A cb JP rel8 D Valid Valid Jum p short if parity (PF=1).
7A cb JPE rel8 D Valid Valid Jump sh ort if parity even (PF=1).
7B cb JPO rel8 D Valid Valid Jump short if parity odd (PF=0).78 cb JS rel8 D Valid Valid Jum p short if sign (SF=1).
74 cb JZ rel8 D Valid Valid Jump short if zero (ZF = 1).
0F 87 cw JA rel16 D N.S. Valid Jump ne ar if above (CF=0 and ZF=0). Not 
supported in 64-bit mode.
0F 87 cd JA rel32 D Valid Valid Jump  near if above (CF=0 and ZF=0).
0F 83 cw JAE rel16 D N.S. Valid Jump near if above or equal (CF=0). Not 
0F 83 cd JAE rel32 D Valid Valid Jump near if above or equal (CF=0).Jcc—Jump if Condition Is MetINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-5490F 82 cw JB rel16 D N.S. Valid Jump near  if below (CF=1). Not supported in 
0F 82 cd JB rel32 D Valid Valid Jump near if below (CF=1).
0F 86 cw JBE rel16 D N.S. Valid Jump near if below or equal (CF=1 or ZF=1). 
Not supported in 64-bit mode.
0F 86 cd JBE rel32 D Valid V alid Jump near if below or equal (CF=1 or ZF=1).
0F 82 cw JC rel16 D N.S. Valid Jump near  if carry (CF=1). Not supported in 
0F 82 cd JC rel32 D Valid Valid Jump near if carry (CF=1).
0F 84 cw JE rel16 D N.S. Valid Jump near  if equal (ZF=1). Not supported in 
0F 84 cd JE rel32 D Valid Valid Jump near if equal (ZF=1).
0F 84 cw JZ rel16 D N.S. Valid Jump near if 0 (ZF=1). Not supported in 64-bit 
mode.
0F 84 cd JZ rel32 D Valid Val id Jump near if 0 (ZF=1).
0F 8F cw JG rel16 D N.S. Valid Jump near  if greater (ZF=0 and SF=OF). Not 
0F 8F cd JG rel32 D Vali d Valid Jump near if greater (ZF=0 and SF=OF).
0F 8D cw JGE rel16 D N.S. Valid Jump near if greater or equal (SF=OF). Not 
0F 8D cd JGE rel32 D Valid Valid Jump near if greater or equal (SF=OF).
0F 8C cw JL rel16 D N.S. Va lid Jump near if less (SF ≠ OF). Not supported in 
0F 8C cd JL rel32 D Valid Val id Jump near if less (SF ≠ OF).
0F 8E cw JLE rel16 D N.S. Valid Jump ne ar if less or equal (ZF=1 or SF ≠ OF). 
0F 8E cd JLE rel32 D Valid Valid Jump near if less or equal (ZF=1 or SF ≠ OF).
0F 86 cw JNA rel16 D N.S. Valid Jump near if not above (CF=1 or ZF=1). Not 
0F 86 cd JNA rel32 D Vali d Valid Jump near if not above (CF=1 or ZF=1).
0F 82 cw JNAE rel16 D N.S. Valid Jump near if not above or equal (CF=1). Not 
0F 82 cd JNAE rel32 D Vali d Valid Jump near if not above or equal (CF=1).
0F 83 cw JNB rel16 D N.S. Valid Jump near if not below (CF=0). Not supported 
in 64-bit mode.
0F 83 cd JNB rel32 D Valid Valid Ju mp near if not below (CF=0).
0F 87 cw JNBE rel16 D N.S. Valid Jump near if not below or equal (CF=0 and 
ZF=0). Not supported in 64-bit mode.
0F 87 cd JNBE rel32 D Valid Valid Jump ne ar if not below or equal (CF=0 and 
ZF=0).
0F 83 cw JNC rel16 D N.S. Valid Jump near if not carry (CF=0). Not supported 
0F 83 cd JNC rel32 D Valid Valid Ju mp near if not carry (CF=0).
0F 85 cw JNE rel16 D N.S. Valid Jump near if not equal (ZF=0). Not supported 
in 64-bit mode.Opcode Instruction Op/ 
En64-Bit 
Leg ModeDescriptionJcc—Jump if Condition Is MetINSTRUCTION SET REFERENCE, A-L
3-550 Vol. 2A0F 85 cd JNE rel32 D Valid Valid Ju mp near if not equal (ZF=0).
0F 8E cw JNG rel16 D N.S. Valid Jump near if not greater (ZF=1 or SF ≠ OF). 
0F 8E cd JNG rel32 D Valid Valid Jump near if not greater (ZF=1 or SF ≠ OF).
0F 8C cw JNGE rel16 D N. S. Valid Jump near if not greater or equal (SF ≠ OF). 
0F 8C cd JNGE rel32 D Vali d Valid Jump near if no t greater or equal (SF ≠ OF).
0F 8D cw JNL rel16 D N.S. Valid Jump near  if not less (SF=OF). Not supported 
0F 8D cd JNL rel32 D Valid Valid Ju mp near if not less (SF=OF).
0F 8F cw JNLE rel16 D N.S. Valid Jump ne ar if not less or equal (ZF=0 and 
SF=OF). Not supported in 64-bit mode.
0F 8F cd JNLE rel32 D Valid Valid Jump near if not less or equal (ZF=0 and 
SF=OF).
0F 81 cw JNO rel16 D N.S. Valid Jump ne ar if not overflow (OF=0). Not 
0F 81 cd JNO rel32 D Valid Valid Jump  near if not overflow (OF=0).
0F 8B cw JNP rel16 D N.S. Valid Jump near if not parity (PF= 0). Not supported 
0F 8B cd JNP rel32 D Valid Valid Jump  near if not parity (PF=0).
0F 89 cw JNS rel16 D N.S. Valid Jump near if not sign (SF=0). Not supported in 
0F 89 cd JNS rel32 D Valid Valid Ju mp near if not sign (SF=0).
0F 85 cw JNZ rel16 D N.S. Valid Jump near if not zero (ZF=0) . Not supported in 
0F 85 cd JNZ rel32 D Valid Valid Ju mp near if not zero (ZF=0).
0F 80 cw JO rel16 D N.S. Valid Jump near  if overflow (OF=1). Not supported 
0F 80 cd JO rel32 D Valid Valid Ju mp near if overflow (OF=1).
0F 8A cw JP rel16 D N.S. Valid Jump near if parity (PF=1). Not supported in 
0F 8A cd JP rel32 D Valid Valid Ju mp near if parity (PF=1).
0F 8A cw JPE rel16 D N.S. Valid Jump ne ar if parity even (PF=1). Not 
0F 8A cd JPE rel32 D Valid Valid Jump  near if parity even (PF=1).
0F 8B cw JPO rel16 D N.S. Valid Jump near if parity odd (PF=0). Not supported 
0F 8B cd JPO rel32 D Valid Valid Jump  near if pari ty odd (PF=0).
0F 88 cw JS rel16 D N.S. Valid Jump near if sign (SF=1). Not supported in 64-
bit mode.
0F 88 cd JS rel32 D Valid Valid Jump near if sign (SF=1).
mode.
0F 84 cd JZ rel32 D Valid Val id Jump near if 0 (ZF=1).Opcode Instruction Op/ 
En64-Bit 
Vol. 2A 3-551Instruction Operand Encoding
Checks the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags 
are in the specified state (condition), performs a jump to the target instruction specified by the destination 
operand. A condition code ( cc) is associated with each instruction to indicate the condition being tested for. If the 
condition is not satisfied, the jump is not performed and execution continues with the instruction following the J cc 
The target instruction is specified with a relative offset (a  signed offset relative to the current value of the instruc-
tion pointer in the EIP regi ster). A relative offset ( rel8, rel16,  or rel32) is generally specified as a label in assembly 
code, but at the machine code level, it is encoded as a si gned, 8-bit or 32-bit immediate value, which is added to 
the instruction pointer. Instruction coding is most efficient for offsets of –128 to +127. If the operand-size attribute 
is 16, the upper two bytes of the EIP re gister are cleared, resulting in a maximum instruction pointer size of 16 bits. 
The conditions for each J cc mnemonic are given in the “Description” colu mn of the table on the preceding page. The 
terms “less” and “greater” are used for comparisons of si gned integers and the terms “above” and “below” are used 
for unsigned integers.
defined for some opcodes. For example, the JA (jump if above) instruction and the JNBE (jump if not below or 
equal) instruction are alternat e mnemonics for the opcode 77H.
The Jcc instruction does not support far jumps (jumps to othe r code segments). When the target for the conditional 
jump is in a different segment, use the opposite condition from the condition being tested for the J cc instruction, 
and then access the target with an unconditional far jump (JMP instruction) to the other segment. For example, the 
following conditional far jump is illegal:
JZ FARLABEL;
To accomplish this far jump, use the following two instructions:
JNZ BEYOND;
JMP FARLABEL;BEYOND:
The JRCXZ, JECXZ, and JCXZ instructions differ from other J cc instructions because they do not check status flags. 
Instead, they check RCX, ECX or CX for 0. The register ch ecked is determined by the address-size attribute. These 
instructions are useful when used at the beginning of a loop that terminates with a conditional loop instruction 
(such as LOOPNE). They can be used to prevent an instru ction sequence from entering a loop when RCX, ECX or 
CX is 0. This would cause the loop to execute 2
64, 232 or 64K times (not zero times).
All conditional jumps are converted to code fetches of one or two cache lines, regardless of jump address or cache-
ability.

ability.
In 64-bit mode, operand size is fixed at 64 bits. JMP Short is RIP = RIP + 8-bit offset sign extended to 64 bits. JMP 
Near is RIP = RIP + 32-bit offset sign extended to 64 bits.Op/En Operand 1 Operand 2 Operand 3 Operand 4
DO f f s e t N / A N / A N / AJcc—Jump if Condition Is MetINSTRUCTION SET REFERENCE, A-L
3-552 Vol. 2AOperation
IF condition
THEN
 tempEIP := EIP + SignExtend(DEST); IF OperandSize = 16
THEN tempEIP := tempEIP AND 0000FFFFH;
 FI;
IF tempEIP is not with in code segment limit
 ELSE EIP := tempEIP FI;FI;
None.
#GP(0) If the offset being jumped to is  beyond the limits of the CS segment.
#GP If the offset being jumped to is beyond the lim its of the CS segment or is outside of the effec-
tive address space from 0 to FFFFH. This conditio n can occur if a 32-bit address size override 
prefix is used.
#GP(0) If the memory address is in a non-canonical form.#UD If the LOCK prefix is used.JMP—JumpINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-553JMP—Jump
Transfers program control to a different point in the instruction stream without recording return information. The 
destination (target) operand specifies the address of th e instruction being jumped to. This operand can be an 
immediate value, a general-purpose register, or a memory location.
This instruction can be used to execute four different types of jumps:
•Near jump—A jump to an instruction within the current code segment (the segment currently pointed to by the 
CS register), sometimes referred to as an intrasegment jump.
•Short jump—A near jump where the jump range is limited to –128 to +127 from the current EIP value.
•Far jump—A jump to an instruction located in a differ ent segment than the current code segment but at the 
same privilege level, sometimes refe rred to as an intersegment jump.
•Task switch—A jump to an instruction located in a different task. 
A task switch can only be executed in pr otected mode (see Chapter 8, in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 3A, for information on  performing task switches with the JMP instruction).
Near and Short Jumps. When executing a near jump, the processor ju mps to the address (within the current code 
segment) that is specified with the targ et operand. The target operand specifies either an absolute offset (that is 
an offset from the base of the code segment) or a relati ve offset (a signed displacement relative to the current Opcode Instruction Op/ 
En64-Bit 
EB cb JMP rel8 D Valid Valid Jump short, RIP = RIP + 8-bit displacement sign 
extended to 64-bits.
E9 cw JMP rel16 D N.S. Valid Jump near, re lative, displaceme nt relative to 
next instruction. Not supported in 64-bit mode.
E9 cd JMP rel32 D Valid Valid Jump ne ar, relative, RIP = RIP + 32-bit 
displacement sign ex tended to 64-bits.
FF /4 JMP r/m16 M N.S. Valid Jump near, absolute indirect, address = zero-
extended r/m16. Not supported in 64-bit mode.
FF /4 JMP r/m32 M N.S. Valid Jump near, absolute indirect, address given in 
r/m32. Not supported in 64-bit mode.
FF /4 JMP r/m64 M Valid N.E. Jump near, absolute indirect, RIP = 64-Bit 
offset from register or memory.
EA cd JMP ptr16:16 S Inv. Valid Jump far, absolute, address given in operand.EA cp JMP ptr16:32 S Inv. Valid Jump far, absolute, address given in operand.FF /5 JMP m16:16 M Valid Valid Jump far, absolute indirect, address given in 
m16:16.
FF /5 JMP m16:32 M Valid Valid Jump far, absolute indirect, address given in 
m16:32.
REX.W FF /5 JMP m16:64 M Valid N.E. Jump far, absolute indirect, address given in 
m16:64.
SS e g m e n t  +  A b s o l u t e  A d d r e s s N / A N / A N / A
DO f f s e t N / A N / A N / A
M ModRM:r/m (r) N/A N/A N/AJMP—JumpINSTRUCTION SET REFERENCE, A-L
3-554 Vol. 2Avalue of the instruction pointer in the EIP register).  A near jump to a relative offset of 8-bits ( rel8) is referred to as 
a short jump. The CS register is not changed on near and short jumps.
An absolute offset is specified indirectly in a general-purpose register or a memory location ( r/m16  or r/m32 ). The 
operand-size attribute determines the size of the target  operand (16 or 32 bits). Absolute offsets are loaded 
directly into the EIP register. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared, 
resulting in a maximum instruction pointer size of 16 bits.
A relative offset ( rel8, rel16 , or rel32) is generally specified as a label in assembly code, but at the machine code 
level, it is encoded as a signed 8-, 16-, or 32-bit imme diate value. This value is added to the value in the EIP 
register. (Here, the EIP register contains the address of the instruction following the JMP instruction). When using relative offsets, the opcode (for short vs. near jumps) and the operand-size attribute (for near relative jumps) 
determines the size of the target operand (8, 16, or 32 bits).
Far Jumps in Real-Address or Virtual-8086 Mode.  When executing a far jump in real-address or virtual-8086 mode, 
the processor jumps to the code segment and offset specif ied with the target operand.  Here the target operand 
specifies an absolute far address either directly with a pointer ( ptr16:16  or ptr16:32 ) or indirectly with a memory 
location ( m16:16  or m16:32 ). With the pointer method, the segment and address of the called procedure is 
encoded in the instruction, using a 4-byte (16-bit operan d size) or 6-byte (32-bit operand size) far address imme-
diate. With the indirect method, the target operand specifies a memory location that contains a 4-byte (16-bit 
operand size) or 6-byte (32-bit operand size) far address. The far address is loaded directly into the CS and EIP 
registers. If the operand-size attribute is 16, th e upper two bytes of the EIP register are cleared.
Far Jumps in Protected Mode.  When the processor is operating in protected mode, the JMP instruction can be used 
to perform the following three types of far jumps:
•A far jump to a conforming or non-conforming code segment.
•A far jump through a call gate.
•A task switch.
(The JMP instruction cannot be used to perform inter-privilege-level far jumps.)
rights determine the type of jump to be performed.
If the selected descriptor is for a code segment, a far jump to a code segment at the same privilege level is 
a general-protection exception is generated.) A far jump to the same privilege level in protected mode is very 
similar to one carried out in real-address or virtual-8086  mode. The target operand specifies an absolute far 
address either directly with a pointer ( ptr16:16  or ptr16:32 ) or indirectly with a memory location ( m16:16  or 
m16:32 ). The operand-size attribute determines the size of th e offset (16 or 32 bits) in the far address. The new 
code segment selector and its descriptor are loaded into CS register, and the offset from the instruction is loaded 
into the EIP register. Note that a call gate (described in th e next paragraph) can also be used to perform far call to 
a code segment at the same privilege level. Using this mechanism provides an extra level of indirection and is the 
preferred method of making jumps betw een 16-bit and 32-bit code segments.
When executing a far jump through a call gate, the segment selector specified by the target operand identifies the 
call gate. (The offset part of the target operand is ig nored.) The processor then jump s to the code segment speci-
fied in the call gate descriptor and begins executing the in struction at the offset specified in the call gate. No stack 
switch occurs. Here again, the target operand can specify the far address of the call gate either directly with a 
pointer ( ptr16:16  or ptr16:32 ) or indirectly with a memory location ( m16:16  or m16:32 ).
Executing a task switch with the JMP instruction is somewhat similar to executing a jump through a call gate. Here 
the target operand specifies the segment selector of the task gate for the task  being switched to (and the offset 
part of the target operand is ignored). The task gate in  turn points to the TSS for the task, which contains the 
segment selectors for the task’s code and stack segments. The TSS also contains the EIP value for the next instruc-

tion that was to be executed before the task was suspende d. This instruction pointer va lue is loaded into the EIP 
register so that the task begins executing again at this next instruction. 
The JMP instruction can also specify the segment selector of  the TSS directly, which eliminates the indirection of the 
task gate. See Chapter 8 in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for 
detailed information on the mechanics of a task switch.JMP—JumpINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-555Note that when you execute at task swit ch with a JMP instruction, the nested ta sk flag (NT) is not set in the EFLAGS 
register and the new TSS’s previous task link field is not loaded with the old task’s TSS selector. A return to the previous task can thus not be carried out by executing th e IRET instruction. Switching tasks with the JMP instruc-
tion differs in this regard from the CALL instruction which does set the NT flag and save the previous task link infor-
mation, allowing a return to the calling task with an IRET instruction.
Refer to Chapter 6, “Procedure Calls,  Interrupts, and Exceptions” and Chapte r 17, “Control-flow Enforcement Tech-
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for CET details.
In 64-Bit Mode.  The instruction’s operation size is fixed at 64 bits. If a selector points to a gate, then RIP equals the 
64-bit displacement taken from gate; else RIP equals the zero-extended offset from the far pointer referenced in 
the instruction. 
See the summary chart at the beginning of this section for encoding data and limits. Instruction ordering. Instructions following a far jump may be fetched from memory before earlier instructions 
complete execution, but they will not execute (even speculat ively) until all instructions prior to the far jump have 
Instructions sequentially following a near indirect JMP instruction (i.e., those not at the target) may be executed 
speculatively. If software needs to prevent this (e.g., in order to prevent a speculative execution side channel), then an INT3 or LFENCE instruction opcode can be placed after the near indirect JMP in order to block speculative 
Operation
IF near jump
IF 64-bit Mode THEN 
IF near relative jump THEN
tempRIP := RIP + DEST; (* RIP is instruction following JMP instruction*)
 ELSE (* Near absolute jump *)
tempRIP := DEST;
FI;
ELSE
tempEIP := EIP + DEST; (* EIP is instruction following JMP instruction*)
tempEIP := DEST;
FI;
FI;IF (IA32_EFER.LMA 
= 0 or target mode = Compatibility mode) 
and tempEIP outside code segment limit 
THEN #GP(0); FI
IF 64-bit mode and tempRIP is not canonical
= 32
 THEN 
EIP := tempEIP; 
 ELSE 
THEN (* OperandSize = 16 *)
EIP := tempEIP AND 0000FFFFH;
 ELSE (* OperandSize = 64)
 RIP := tempRIP;JMP—JumpINSTRUCTION SET REFERENCE, A-L
3-556 Vol. 2AFI;
 FI;IF (JMP near indirect , absolute indirect)
IF CPL = 3
THEN
THEN
FI;
ELSE
THEN
FI;
FI;
FI;
FI;
FI;IF far jump and (PE 
= 0 or (PE = 1 AND VM = 1)) (* Real-address or  virtual-8086 mode *)
 THEN
 tempEIP := DEST(Offset); (* DEST is ptr16:32  or [m16:32 ] *)
 IF tempEIP is beyond  code segment limit 
 CS := DEST(segment se lector); (* DEST is ptr16:32  or [m16:32 ] *)
 IF OperandSize = 32
 THEN
EIP := tempEIP; (* DEST is ptr16:32  or [m16:32 ] *)
 ELSE (* OperandSize = 16 *)
EIP := tempEIP AND 0000FFFFH; (* Clear upper 16 bits *)
 FI;
= 1 and VM = 0) 
(* IA-32e mode or protected mode, not virtual-8086 mode *)
 THEN
 IF effective address in the CS, DS, ES, FS, GS, or SS segment is illegalor segment selector in  target operand NULL
 IF segment selector index not within descriptor table limits
THEN #GP(new selector); FI;
Read type and access rights of segment descriptor;IF (IA32_EFER.LMA 
= 0) 
THEN
IF segment type is not a conforming or nonconforming code 
segment, call gate, task gate, or TSS 
THEN #GP(segment selector); FI; 
ELSE
IF segment type is not a conforming or nonconforming code segment
call gate
GO TO CONFORMING-CODE-SEGMENT;GO TO NONCONFORMING-CODE-SEGMENT;JMP—JumpINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-557GO TO CALL-GATE;
GO TO TASK-GATE;GO TO TASK-STATE-SEGMENT;
 ELSE 
 #GP(segment selector);
FI;CONFORMING-CODE-SEGMENT:
IF L-Bit 
= 1 and D-BIT = 1 and IA32_EFER.LMA = 1
 IF DPL > CPL 
 IF segment not present
THEN #NP(segment selector); FI;
tempEIP := DEST(Offset);IF OperandSize 
= 16 
 THEN tempEIP := tempEIP AND 0000FFFFH; 
= 0 or target mode = Compatibility mode) and 
tempEIP outside co de segment limit 
IF tempEIP is non-canonical
IF (IA32_EFER.LMA and DEST(segment selector).L) = 0
FI;
FI;CS := DEST[segment selector]; (* Segment descriptor information also loaded *)CS(RPL) := CPLEIP := tempEIP;IF EndbranchEnabled(CPL)
IF CPL = 3
THEN
ELSE
FI;
FI;
END;NONCONFORMING-CODE-SEGMENT:
IF L-Bit 
IF (RPL > CPL) OR (DPL ≠ CPL)
THEN #GP(code segment selector); FI;
= 16 
 THEN tempEIP := tempEIP AND 0000FFFFH; FI;
IF (IA32_EFER.LMA = 0 OR target mode = Compatibility mode) JMP—JumpINSTRUCTION SET REFERENCE, A-L
3-558 Vol. 2Aand tempEIP outside code segment limit 
IF tempEIP is non-canonical THEN #GP(0); FI;IF ShadowStackEnabled(CPL)
FI;
FI;CS := DEST[segment selector]; (* Segment descriptor information also loaded *)CS(RPL) := CPL;EIP := tempEIP;IF EndbranchEnabled(CPL)
IF CPL = 3
THEN
ELSE
FI;
FI;
END;
IF call gate DPL < CPL 
or call gate DPL < call gate segmen t-selector RPL 
THEN #GP(call gate selector); FI;
IF call gate not present
THEN #NP(call gate selector); FI;
IF call gate code-seg ment select or is NULL
IF call gate code-segme nt selector index outsid e descriptor table limits
Read code segment descriptor;IF code-segment segment descriptor does not indicate a code segmentor code-segment segment descriptor is conforming and DPL > CPL
or code-segment segment descriptor is non-conforming and DPL
 ≠ CPL
IF IA32_EFER.LMA = 1 and (code-segment descriptor is not a 64-bit code segment 
or code-segment segment descriptor has both L-Bit and D-bit set)
IF code segment is not present
THEN #NP(code-segme nt selector); FI;
 tempEIP := DEST(Offset); IF GateSize 
= 16 
IF (IA32_EFER.LMA = 0 OR target mode = Compatibility mode) AND tempEIP 
outside code segment limit 
CS := DEST[SegmentSelector]; (* Segment descriptor information also loaded *)CS(RPL) := CPL;EIP := tempEIP;JMP—JumpINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-559IF EndbranchEnabled(CPL)
IF CPL = 3
THEN
IA32_U_CET.TRACKER = WAIT_FOR_ENDBRANCH;
ELSE
FI;
FI;
END;TASK-GATE:
IF task gate DPL < CPL 
or task gate DPL < task gate segment-selector RPL 
THEN #NP(gate selector); FI;
Read the TSS segment selector in the task-gate descriptor;
IF TSS segment select or local/global bi t is set to local
or index not within GDT limitsor descriptor is not a TSS segmentor TSS descriptor specif ies that the TSS is busy
 IF TSS not present 
 SWITCH-TASKS to TSS; IF EIP not within code segment limit 
END;TASK-STATE-SEGMENT:
IF TSS DPL < CPL
or TSS DPL < TSS segment-selector RPL
IF TSS is not present

IF CPL = 3
THEN
ELSE
FI;
FI;
SWITCH-TASKS to TSS;IF EIP not within code segment limit 
END;
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.
#GP(0) If offset in target operand, call gate , or TSS is beyond the code segment limits.
If the segment selector in the destination op erand, call gate, task gate, or TSS is NULL.
selector.
If target mode is compatibility mode and SSP is not in low 4GB.JMP—JumpINSTRUCTION SET REFERENCE, A-L
3-560 Vol. 2A#GP(selector) If the segment selector index is outside descriptor table limits. 
If the segment descriptor pointed to by the segm ent selector in the destination operand is not 
If the DPL for a nonconforming-code  segment is not equal to the CPL
(When not using a call gate.) If the RPL for the segment’s segment selector is greater than the 
CPL.
If the segment descriptor for selector in a call gate does not indicate it is a code segment.If the segment descriptor for the segment selector in a task gate does not indicate an available 
TSS.
If the segment selector for a TSS has its local/global bit set for local.If a TSS segment descriptor specifies that the TSS is busy or not available.
#NP (selector) If the code segment being accessed is not present.
If call gate, task gate, or TSS not present.
current privilege level is 3. (Only occu rs when fetching target from memory.)
#GP(0) If the target operand is beyond the code segment limits.
#AC(0) If alignment checking is enabled and an una ligned memory reference is made. (Only occurs 
when fetching target from memory.)
Same as 64-bit mode exceptions.
If target offset in destination operand is non-canonical.
If target offset in destination operand is beyond the new code segment limit.If the segment selector in th e destination operand is NULL.
If transitioning to compatibility mode and the SSP is beyond 4GB.JMP—JumpINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-561#GP(selector) If the code segment or 64-bit call gate is outside descriptor table limits. 
If the code segment or 64-bit call gate overlaps non-canonical space. If the segment descriptor from a 64-bit call gate is in non-canonical space. 
for a conforming-code segment, nonconfo rming-code segment, 64-bit call gate.
code segment, and has both the D-bit and the L-bit set.
If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.If the upper type field of a 64-bit call gate is not 0x0.
If the segment selector from a 64-bit call gate is beyond the descriptor table limits.
If the code segment is non-conforming and CPL ≠ DPL.
If the code segment is confirming and CPL < DPL.
#UD (64-bit mode only) If a far jump is direct to an absolute address in memory.
current privilege level is 3.KADDW/KADDB/KADDQ/KADDD—ADD Two MasksINSTRUCTION SET REFERENCE, A-L
3-562 Vol. 2AKADDW/KADDB/KADDQ/KADDD—ADD Two Masks
Adds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.
Operation
KADDW
DEST[15:0] := SRC1[15:0] + SRC2[15:0]DEST[MAX_KL-1:16] :=  0
KADDB
DEST[7:0] :=  SRC1[7:0] + SRC2[7:0]
DEST[MAX_KL-1:8]  := 0
KADDQ
DEST[63:0] :=  SRC1[63:0] + SRC2[63:0]
DEST[MAX_KL-1:64] := 0
KADDD
DEST[31:0]  := SRC1[31:0] + SRC2[31:0]
DEST[MAX_KL-1:32]  := 0
KADDW __mmask16 _kadd_mask16 (__mmask16 a, __mmask16 b);
KADDB __mmask8 _kadd_mask8 (__mmask8 a, __mmask8 b);
KADDQ __mmask64 _kadd_mask64 (__mmask64 a, __mmask64 b);
KADDD __mmask32 _kadd_mask32 (_ _mmask32 a, __m mask32 b);
None.
VEX.L1.0F.W0 4A /r 
KADDW k1, k2, k3RVR V/V AVX512DQ Add 16 bits masks in k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 4A /r 
KADDB k1, k2, k3RVR V/V AVX512DQ Add 8 bits masks in k2 and k3 and place result in k1.
VEX.L1.0F.W1 4A /r 
KADDQ k1, k2, k3RVR V/V AVX512BW Add 64 bits masks in k2 and k3 and place result in k1. 
VEX.L1.66.0F.W1 4A /r 
KADDD k1, k2, k3RVR V/V AVX512BW Add 32 bits masks in k2 and k3 and place result in k1.
RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)KADDW/KADDB/KADDQ/KADDD—ADD Two MasksINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-563Other Exceptions
See Table 2-63, “TYPE K20 Exception Definition (VEX -Encoded OpMask Instructions w/o Memory Arg).”KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND MasksINSTRUCTION SET REFERENCE, A-L
3-564 Vol. 2AKANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND Masks
Performs a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask 
k1.
Operation
KANDW
DEST[15:0] := SRC1[15:0] BITWISE AND SRC2[15:0]DEST[MAX_KL-1:16] := 0
KANDB
DEST[7:0]  := SRC1[7:0] BITWIS E AND SRC2[7:0]
DEST[MAX_KL-1:8] :=  0
KANDQ
DEST[63:0]  := SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[MAX_KL-1:64] :=  0
KANDD
DEST[31:0] :=  SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[MAX_KL-1:32] :=  0
KANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);
None.
None.
See Table 2-63, “TYPE K20 Exceptio n Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).”Opcode/
VEX.L1.0F.W0 41 /r 
KANDW k1, k2, k3RVR V/V AVX512F Bitwise AND 16 bits mask s k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 41 /r 
KANDB k1, k2, k3RVR V/V AVX512DQ Bitwise AND 8 bits masks k2 and k3 and place result in k1. 
VEX.L1.0F.W1 41 /r 
KANDQ k1, k2, k3RVR V/V AVX512BW Bitwise AND 64 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 41 /r 
KANDD k1, k2, k3RVR V/V AVX512BW Bitwise AND 32 bits masks k2 and k3 and place result in k1. 
RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r /m (r, ModRM:[7:6] must be 11b)KANDNW/KANDNB/KANDNQ/KANDND—Bi twise Logical AND NOT MasksINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-565KANDNW/KANDNB/KANDNQ/KANDND—Bit wise Logical AND NOT Masks
Performs a bitwise AND NOT between the vector mask k2 and the vector mask k3, and writes the result into vector 
mask k1.
Operation
KANDNW
DEST[15:0] := (BITWISE NOT SR C1[15:0]) BITWISE AND SRC2[15:0]
DEST[MAX_KL-1:16] := 0
KANDNB
DEST[7:0]  := (BITWISE NOT SRC1[7:0]) BITWISE AND SRC2[7:0]
KANDNQ
DEST[63:0]  := (BITWISE NOT SRC1[63:0]) BITWISE AND SRC2[63:0]
DEST[MAX_KL-1:64]  := 0
KANDND

mask k1.
Operation
KANDNW
KANDNB
KANDNQ
KANDND
DEST[31:0] :=  (BITWISE NOT SRC1[31:0]) BITWISE AND SRC2[31:0]
KANDNW __mmask16 _mm512_kandn (__mmask16 a, __mmask16 b);
None.
None.
See Table 2-63, “TYPE K20 Exception Definition (VEX -Encoded OpMask Instructions w/o Memory Arg).”Opcode/
VEX.L1.0F.W0 42 /r 
KANDNW k1, k2, k3RVR V/V AVX512F Bitwise AND NOT 16 bits mask s k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 42 /r 
KANDNB k1, k2, k3RVR V/V AVX512DQ Bitwise AND NOT 8 bits masks k1 and k2 and place result in k1.
VEX.L1.0F.W1 42 /r 
KANDNQ k1, k2, k3RVR V/V AVX512BW Bitwise AND NOT 64 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 42 /r 
KANDND k1, k2, k3RVR V/V AVX512BW Bitwise AND NOT 32 bits masks k2 and k3 and place result in k1.
RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r /m (r, ModRM:[7:6] must be 11b)KMOVW/KMOVB/KMOVQ/KMOVD—Move From and to Mask RegistersINSTRUCTION SET REFERENCE, A-L
3-566 Vol. 2AKMOVW/KMOVB/KMOVQ/KMOVD—Move From and to Mask Registers 
Copies values from the source operand (second operand) to the destination operand (first operand). The source 
and destination operands can be mask registers, memory location or general purpose. The instruction cannot be 
used to transfer data between general pu rpose registers and or memory locations.Opcode/
VEX.L0.0F.W0 90 /r
KMOVW k1, k2/m16RM V/V AVX512F Move 16 bits mask from  k2/m16 and store the result in k1.
VEX.L0.66.0F.W0 90 /r 
KMOVB k1, k2/m8RM V/V AVX512DQ Move 8 bits mask from k2/m8 and store the result in k1. 
VEX.L0.0F.W1 90 /r 
KMOVQ k1, k2/m64RM V/V AVX512BW Move 64 bits mask from  k2/m64 and store the result in k1.
VEX.L0.66.0F.W1 90 /r 
KMOVD k1, k2/m32RM V/V AVX512BW Move 32 bits mask from  k2/m32 and store the result in k1. 
VEX.L0.0F.W0 91 /r 
KMOVW m16, k1MR V/V AVX512F Move 16 bits mask from  k1 and store the result in m16.
VEX.L0.66.0F.W0 91 /r 
KMOVB m8, k1MR V/V AVX512DQ Move 8 bits mask from k1 and store the result in m8. 
VEX.L0.0F.W1 91 /r 
KMOVQ m64, k1MR V/V AVX512BW Move 64 bits mask from  k1 and store the result in m64.
VEX.L0.66.0F.W1 91 /r 
KMOVD m32, k1MR V/V AVX512BW Move 32 bits mask from  k1 and store the result in m32.
VEX.L0.0F.W0 92 /r 
KMOVW k1, r32RR V/V AVX512F Move 16 bits mask from r32 to k1.
VEX.L0.66.0F.W0 92 /r 
KMOVB k1, r32RR V/V AVX512DQ Move 8 bits mask from r32 to k1.
VEX.L0.F2.0F.W1 92 /r 
KMOVQ k1, r64RR V/I AVX512BW Move 64 bits mask from r64 to k1.
VEX.L0.F2.0F.W0 92 /r 
KMOVD k1, r32RR V/V AVX512BW Move 32 bits mask from r32 to k1.
VEX.L0.0F.W0 93 /r 
KMOVW r32, k1RR V/V AVX512F Move 16 bits mask from k1 to r32.
VEX.L0.66.0F.W0 93 /r 
KMOVB r32, k1RR V/V AVX512DQ Move 8 bits mask from k1 to r32.
VEX.L0.F2.0F.W1 93 /r 
KMOVQ r64, k1RR V/I AVX512BW Move 64 bits mask from k1 to r64.
VEX.L0.F2.0F.W0 93 /r 
KMOVD r32, k1RR V/V AVX512BW Move 32 bits mask from k1 to r32.
Op/En Operand 1 Operand 2
RM ModRM:reg (w) ModRM:r/m (r)MR ModRM:r/m (w, ModRM:[7:6] must not be 11b) ModRM:reg (r)
RR ModRM:reg (w) ModRM:r/m (r, ModRM:[7:6] must be 11b) KMOVW/KMOVB/KMOVQ/KMOVD—Move From and to Mask RegistersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-567When moving to a mask register, the result is zero extended  to MAX_KL size (i.e., 64 bits currently). When moving 
to a general-purpose register (GPR), the result is zero-ext ended to the size of the destination. In 32-bit mode, the 
default GPR destination’s size is 32 bits. In 64-bit mode, the default GPR destination’s size is 64 bits. Note that 
VEX.W can only be used to modify the size of the GPR operand in 64b mode.
Operation
KMOVW
IF *destination is a memory location*
DEST[15:0] := SRC[15:0]
IF *destination is a ma sk register or a GPR *
DEST := ZeroExtension(SRC[15:0])
KMOVB
DEST[7:0]  := SRC[7:0]
DEST := ZeroExtension(SRC[7:0])
KMOVQ
IF *destination is a me mory location or a GPR*
DEST[63:0] := SRC[63:0]
IF *destination is  a mask register*
DEST := ZeroExtension(SRC[63:0])
KMOVD
DEST[31:0] :=  SRC[31:0]
DEST := ZeroExtension(SRC[31:0])
KMOVW __mmask16 _mm512_kmov(__mmask16 a);
None.
None.
Instructions with RR operand encoding, see Table 2-63, “TYPE K20 Exception Definiti on (VEX-Encoded OpMask 
Instructions w/o Memory Arg).”
Instructions with RM or MR operand encoding, see Ta ble 2-64, “TYPE K21 Exception Definition (VEX-Encoded 
OpMask Instructions Addressing Memory).”KNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask RegisterINSTRUCTION SET REFERENCE, A-L
3-568 Vol. 2AKNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask Register
Performs a bitwise NOT of vector mask k2 an d writes the result into vector mask k1.
Operation
KNOTW
DEST[15:0] := BITWISE NOT SRC[15:0]DEST[MAX_KL-1:16] := 0
KNOTB
DEST[7:0] :=  BITWISE NOT SRC[7:0]
KNOTQ
DEST[63:0] := BITWISE NOT SRC[63:0]DEST[MAX_KL-1:64] :=  0
KNOTD
DEST[31:0] := BITWISE NOT SRC[31:0]DEST[MAX_KL-1:32] :=  0
KNOTW __mmask16 _mm512_knot(__mmask16 a);
None.
None.
VEX.L0.0F.W0 44 /r 
KNOTW k1, k2RR V/V AVX512F Bitwise NOT of 16 bits mask k2.
VEX.L0.66.0F.W0 44 /r 
KNOTB k1, k2RR V/V AVX512DQ Bitwise NOT of 8 bits mask k2.
VEX.L0.0F.W1 44 /r 
KNOTQ k1, k2RR V/V AVX512BW Bitwise NOT of 64 bits mask k2.
VEX.L0.66.0F.W1 44 /r 
KNOTD k1, k2RR V/V AVX512BW Bitwise NOT of 32 bits mask k2.
RR ModRM:reg (w) ModRM:r/m (r, ModRM:[7:6] must be 11b)KORW/KORB/KORQ/KORD—Bitwise Logical OR MasksINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-569KORW/KORB/KORQ/KORD—Bitw ise Logical OR Masks
Performs a bitwise OR between the vector mask k2 and the vector mask k3, and writes the result into vector mask 
k1 (three-operand form).
Operation
KORW
DEST[15:0] := SRC1[15:0] BITWISE OR SRC2[15:0]DEST[MAX_KL-1:16] := 0
KORB
DEST[7:0] :=  SRC1[7:0] BITWISE OR SRC2[7:0]
KORQ
DEST[63:0] :=  SRC1[63:0] BITWISE OR SRC2[63:0]
KORD
DEST[31:0] :=  SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[MAX_KL-1:32] := 0
KORW __mmask16 _mm512_kor(_ _mmask16 a, __mmask16 b);
None.
None.
VEX.L1.0F.W0 45 /r 
KORW k1, k2, k3RVR V/V AVX512F Bitwise OR 16 bits mask s k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 45 /r 
KORB k1, k2, k3RVR V/V AVX512DQ Bitwise OR 8 bits masks k2 and k3 and place result in k1.
VEX.L1.0F.W1 45 /r 
KORQ k1, k2, k3RVR V/V AVX512BW Bitwise OR 64 bits mask s k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 45 /r 
KORD k1, k2, k3RVR V/V AVX512BW Bitwise OR 32 bits mask s k2 and k3 and place result in k1.
RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks and Set FlagsINSTRUCTION SET REFERENCE, A-L
3-570 Vol. 2AKORTESTW/KORTESTB/KORTESTQ/KORT ESTD—OR Masks and Set Flags
Performs a bitwise OR between the vector mask register k2 , and the vector mask register k1, and sets CF and ZF 
based on the operation result. 
ZF flag is set if both sources are 0x0. CF is set if, afte r the OR operation is done, the operation result is all 1’s.
Operation
KORTESTW 
TMP[15:0] := DEST[15:0] BITWISE OR SRC[15:0]IF(TMP[15:0]=0)
THEN ZF := 1ELSE ZF := 0
FI;IF(TMP[15:0]=FFFFh)
THEN CF := 1ELSE CF := 0
FI;
KORTESTB 
TMP[7:0]  := DEST[7:0] BITWISE OR SRC[7:0]
IF(TMP[7:0]=0)
THEN ZF := 1ELSE ZF  := 0
FI;IF(TMP[7:0]==FFh)
THEN CF := 1ELSE CF  := 0
InstructionOp/E
n64/32 bit 
VEX.L0.0F.W0 98 /r 
KORTESTW k1, k2RR V/V AVX512F Bitwise OR 16 bits masks k1 and k2 and update ZF and CF accordingly.
VEX.L0.66.0F.W0 98 /r
KORTESTB k1, k2RR V/V AVX512DQ Bitwise OR 8 bits masks k1 and k2 and update ZF and CF accordingly.
VEX.L0.0F.W1 98 /r 
KORTESTQ k1, k2RR V/V AVX512BW Bitwise OR 64 bits masks k1 and k2 and update ZF and CF accordingly.
VEX.L0.66.0F.W1 98 /r 
KORTESTD k1, k2RR V/V AVX512BW Bitwise OR 32 bits masks k1 and k2 and update ZF and CF accordingly.

Operation
KORTESTW 
FI;
KORTESTB 
n64/32 bit 
RR ModRM:reg (w) ModRM:r/m (r, ModRM:[7:6] must be 11b)KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks and Set FlagsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-571KORTESTQ 
TMP[63:0] :=  DEST[63:0] BITWISE OR SRC[63:0]
IF(TMP[63:0]=0)
THEN ZF :=  1
ELSE ZF :=  0
FI;IF(TMP[63:0]==FFFFFFFF_FFFFFFFFh)
THEN CF  := 1
ELSE CF :=  0
FI;
KORTESTD 
TMP[31:0] :=  DEST[31:0] BITWISE OR SRC[31:0]
IF(TMP[31:0]=0)
THEN ZF  := 1
ELSE ZF :=  0
FI;IF(TMP[31:0]=FFFFFFFFh)
THEN CF :=  1
ELSE CF :=  0
FI;
KORTESTW __mmask16 _mm512_kortest [cz](__mmask16 a, __mmask16 b);
The ZF flag is set if the result of OR-ing both sources is all 0s.
The CF flag is set if the result of OR-ing both sources is all 1s.
The OF, SF, AF, and PF flags are set to 0.
See Table 2-63, “TYPE K20 Exception Definition (VEX -Encoded OpMask Instructions w/o Memory Arg).”KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIF TLD—Shift Left Mask RegistersINSTRUCTION SET REFERENCE, A-L
3-572 Vol. 2AKSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers 
Shifts 8/16/32/64 bits in the second operand (source operand) left by the count specified in immediate byte and 
place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination 
are zero-extended. The destination is set to zero if the coun t value is greater than 7 (for byte shift), 15 (for word 
shift), 31 (for doubleword shift) or 63 (for quadword shift).
Operation
KSHIFTLW
COUNT := imm8[7:0]DEST[MAX_KL-1:0] := 0IF COUNT <=15
THEN DEST[15:0] := SRC1[15:0] << COUNT;
FI;
KSHIFTLB
COUNT
 := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=7
THEN DEST[7:0] := SRC1[7:0] << COUNT;
FI;
KSHIFTLQ
COUNT  := imm8[7:0]
DEST[MAX_KL-1:0] :=  0
IF COUNT <=63
THEN DEST[63:0]  := SRC1[63:0] << COUNT;
VEX.L0.66.0F3A.W1 32 /r 
KSHIFTLW k1, k2, imm8RRI V/V AVX512F Shift left 16 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 32 /r 
KSHIFTLB k1, k2, imm8RRI V/V AVX512DQ Shift left 8 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W1 33 /r 
KSHIFTLQ k1, k2, imm8RRI V/V AVX512BW Shift left 64  bits in k2 by immediat e and write result in k1.
VEX.L0.66.0F3A.W0 33 /r 
KSHIFTLD k1, k2, imm8RRI V/V AVX512BW Shift left 32  bits in k2 by immediat e and write result in k1.
RRI ModRM:reg (w) ModRM:r/m (r , ModRM:[7:6] must be 11b) imm8KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask RegistersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-573KSHIFTLD
COUNT := imm8[7:0]
DEST[MAX_KL-1:0]  := 0
IF COUNT <=31
THEN DEST[31:0]  := SRC1[31:0] << COUNT;
FI;
Compiler auto generates KSHIFTLW when needed.
None.
None.
See Table 2-63, “TYPE K20 Exception Definition (VEX -Encoded OpMask Instructions w/o Memory Arg).”KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask RegistersINSTRUCTION SET REFERENCE, A-L
3-574 Vol. 2AKSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers 
Shifts 8/16/32/64 bits in the second operand (source oper and) right by the count specified in immediate and place 
the least significant 8/16/32/64 bits of the result in the de stination operand. The higher bits of the destination are 
zero-extended. The destination is set to ze ro if the count value is greater than 7 (for byte shift), 15 (for word shift), 
31 (for doubleword shift) or  63 (for quadword shift).
Operation
KSHIFTRW
THEN DEST[15:0] := SRC1[15:0] >> COUNT;
FI;
KSHIFTRB
COUNT
THEN DEST[7:0]  := SRC1[7:0] >> COUNT;
FI;
KSHIFTRQ
DEST[MAX_KL-1:0] := 0IF COUNT <=63
THEN DEST[63:0]
 := SRC1[63:0] >> COUNT;
VEX.L0.66.0F3A.W1 30 /r 
KSHIFTRW k1, k2, imm8RRI V/V AVX512F Shift right 16 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 30 /r 
KSHIFTRB k1, k2, imm8RRI V/V AVX512DQ Shift right 8 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W1 31 /r 
KSHIFTRQ k1, k2, imm8RRI V/V AVX512BW Shift right 64 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 31 /r 
KSHIFTRD k1, k2, imm8RRI V/V AVX512BW Shift right 32 bits in k2 by immediate and write result in k1.
RRI ModRM:reg (w) ModRM:r/m (r , ModRM:[7:6] must be 11b) imm8KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask RegistersINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-575KSHIFTRD
THEN DEST[31:0] :=  SRC1[31:0] >> COUNT;
FI;
Compiler auto generates KSHIFTRW when needed.
None.
None.
See Table 2-63, “TYPE K20 Exception Definition (VEX -Encoded OpMask Instructions w/o Memory Arg).”KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set FlagsINSTRUCTION SET REFERENCE, A-L
3-576 Vol. 2AKTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags
Performs a bitwise comparison of the bits of the first so urce operand and corresponding bits in the second source 
operand. If the AND operation produces all zeros, the ZF is set else the ZF is clear. If the bitwise AND operation of 
the inverted first source operand with the second source operand produces all zeros the CF is set else the CF is 
clear. Only the EFLAGS register is updated.
Operation
KTESTW 
TEMP[15:0] := SRC2[15:0] AND SRC1[15:0]IF (TEMP[15:0] = = 0)
THEN ZF :=1;ELSE ZF := 0;
FI;TEMP[15:0] :=  SRC2[15:0] AND NOT SRC1[15:0]
IF (TEMP[15:0] = = 0)
THEN CF  :=1;
ELSE CF :=  0;
FI;AF := OF := PF  := SF  := 0;
KTESTB  
TEMP[7:0]  := SRC2[7:0] AND SRC1[7:0]
IF (TEMP[7:0] = = 0)
THEN ZF :=1;ELSE ZF :=  0;
FI;TEMP[7:0] :=  SRC2[7:0] AND NOT SRC1[7:0]
ELSE CF := 0;
FI;AF :=  OF := PF  := SF  := 0;Opcode/
InstructionOp 
VEX.L0.0F.W0 99 /r
KTESTW k1, k2RR V/V AVX512DQ Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask 
register sources.
VEX.L0.66.0F.W0 99 /r
KTESTB k1, k2RR V/V AVX512DQ Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask reg-
ister sources.
VEX.L0.0F.W1 99 /r
KTESTQ k1, k2RR V/V AVX512BW Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask 
VEX.L0.66.0F.W1 99 /r
KTESTD k1, k2RR V/V AVX512BW Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask 
RR ModRM:reg (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set FlagsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-577KTESTQ 
TEMP[63:0] := SRC2[63:0] AND SRC1[63:0]IF (TEMP[63:0] = = 0)
FI;TEMP[63:0] :=  SRC2[63:0] AND NOT SRC1[63:0]
IF (TEMP[63:0] = = 0)
THEN CF :=1;ELSE CF := 0;
FI;AF :=  OF := PF  := SF  := 0;
KTESTD 
TEMP[31:0]  := SRC2[31:0] AND SRC1[31:0]
IF (TEMP[31:0] = = 0)
THEN ZF  :=1;
ELSE ZF :=  0;
FI;TEMP[31:0] := SRC2[31:0] AND NOT SRC1[31:0]IF (TEMP[31:0] = = 0)
FI;AF :=  OF := PF := SF  := 0;
None.
See Table 2-63, “TYPE K20 Exception Definition (VEX -Encoded OpMask Instructions w/o Memory Arg).”KUNPCKBW/KUNPCKWD/KUNPCKDQ—U npack for Mask RegistersINSTRUCTION SET REFERENCE, A-L
3-578 Vol. 2AKUNPCKBW/KUNPCKWD/KUNPCKDQ—Un pack for Mask Registers 
Unpacks the lower 8/16/32 bits of the second and third op erands (source operands) into the low part of the first 
operand (destination operand), starting from the low by tes. The result is zero-extended in the destination.
Operation
KUNPCKBW
DEST[7:0] := SRC2[7:0]DEST[15:8] := SRC1[7:0]DEST[MAX_KL-1:16] := 0
KUNPCKWD
DEST[15:0]
 := SRC2[15:0]
DEST[31:16] :=  SRC1[15:0]
KUNPCKDQ
DEST[31:0] :=  SRC2[31:0]
DEST[63:32]  := SRC1[31:0]
KUNPCKBW __mmask16 _mm512_kunpackb(__mmask16 a, __mmask16 b);
KUNPCKDQ __mmask64 _mm512_kunpackd(__mmask64 a, __mmask64 b);KUNPCKWD __mmask32 _mm512_kunpa ckw(__mmask32 a, __mmask32 b);
None.
None.
VEX.L1.66.0F.W0 4B /r
KUNPCKBW k1, k2, k3RVR V/V AVX512F Unpack 8-bit masks in k2 and k3 and write word result in k1.
VEX.L1.0F.W0 4B /r

Operation
KUNPCKBW
KUNPCKWD
KUNPCKDQ
None.
None.
VEX.L1.0F.W0 4B /r 
KUNPCKWD k1, k2, k3RVR V/V AVX512BW Unpack 16-bit masks in k2 and k3 and write doubleword result 
in k1.
VEX.L1.0F.W1 4B /r 
KUNPCKDQ k1, k2, k3RVR V/V AVX512BW Unpack 32-bit masks in k2 and k3 and write quadword result in 
k1.
RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r /m (r, ModRM:[7:6] must be 11b)KXNORW/KXNORB/KXNORQ/KXNORD— Bitwise Logical XNOR MasksINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-579KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks
Performs a bitwise XNOR between the vector mask k2 and the vector mask k3, and writes the result into vector 
mask k1 (three-operand form).
Operation
KXNORW
DEST[15:0] := NOT (SRC1[15:0] BITWISE XOR SRC2[15:0])DEST[MAX_KL-1:16] := 0
KXNORB
DEST[7:0]  := NOT (SRC1[7:0] BITWISE XOR SRC2[7:0])
KXNORQ
DEST[63:0] :=  NOT (SRC1[63:0] BITWISE XOR SRC2[63:0])
KXNORD
DEST[31:0]  := NOT (SRC1[31:0] BITWISE XOR SRC2[31:0])
KXNORW __mmask16 _mm512_kxnor (__mmask16 a, __mmask16 b);
None.
None.
VEX.L1.0F.W0 46 /r 
KXNORW k1, k2, k3RVR V/V AVX512F Bitwise XNOR 16-bit masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 46 /r 
KXNORB k1, k2, k3RVR V/V AVX512DQ Bitwise XNOR 8-bit masks k2 and k3 and place result in k1.
VEX.L1.0F.W1 46 /r 
KXNORQ k1, k2, k3RVR V/V AVX512BW Bitwise XNOR 64-bit masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 46 /r 
KXNORD k1, k2, k3RVR V/V AVX512BW Bitwise XNOR 32-bit masks k2 and k3 and place result in k1.
RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r /m (r, ModRM:[7:6] must be 11b)KXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR MasksINSTRUCTION SET REFERENCE, A-L
3-580 Vol. 2AKXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR Masks
Performs a bitwise XOR between the vector mask k2 and the vector mask k3, and writes th e result into vector mask 
Operation
KXORW
DEST[15:0] := SRC1[15:0] BITWISE XOR SRC2[15:0]DEST[MAX_KL-1:16] := 0
KXORB
DEST[7:0] := SRC1[7:0] BITWISE XOR SRC2[7:0]
DEST[MAX_KL-1:8] := 0
KXORQ
DEST[63:0] := SRC1[63:0] BITWISE XOR SRC2[63:0]DEST[MAX_KL-1:64] := 0
KXORD
DEST[31:0] := SRC1[31:0] BITWISE XOR SRC2[31:0]DEST[MAX_KL-1:32] := 0
KXORW __mmask16 _mm512_kxor(__mmask16 a, __mmask16 b);
None.
None.
VEX.L1.0F.W0 47 /r 
KXORW k1, k2, k3RVR V/V AVX512F Bitwise XOR 16-bit masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 47 /r
KXORB k1, k2, k3RVR V/V AVX512DQ Bitwise XOR 8-bit masks k2 and k3 and place result in k1.
VEX.L1.0F.W1 47 /r 
KXORQ k1, k2, k3RVR V/V AVX512BW Bitwise XOR 64-bit masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 47 /r 
KXORD k1, k2, k3RVR V/V AVX512BW Bitwise XOR 32-bit masks k2 and k3 and place result in k1.
RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r /m (r, ModRM:[7:6] must be 11b)LAHF—Load Status Flags Into AH RegisterINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-581LAHF—Load Status Flags Into AH Register
This instruction executes as described above in compatibilit y mode and legacy mode. It is valid in 64-bit mode only 
if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1. 
Operation
THEN
IF CPUID.80000001H:ECX.L AHF-SAHF[bit 0] = 1;
THEN AH := RFLAGS(SF:ZF:0:AF:0:PF:1:CF);
ELSE #UD; 
FI;
ELSE
AH := EFLAGS(SF:ZF:0:AF:0:PF:1:CF);
FI;
None. The state of the flags in the EFLAGS register is not affected.
#UD If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0.
If the LOCK prefix is used.Opcode Instruction Op/ 
En64-Bit 
9F LAHF ZO Invalid1
NOTES:
1. Valid in specific steppi ngs; see Description section.Valid Load: AH := EFLAGS(SF:ZF:0:AF:0:PF:1:CF).
ZO N/A N/A N/A N/ALAR—Load Access Rights ByteINSTRUCTION SET REFERENCE, A-L
3-582 Vol. 2ALAR—Load Access Rights Byte
Loads the access rights from the segment descriptor specif ied by the second operand (source operand) into the 
first operand (destination operand) and sets the ZF flag in the flag register. The source operand (which can be a 
register or a memory location) contains the segment se lector for the segment descriptor being accessed. If the 
source operand is a memory address, only 16 bits of data are accessed. The destination operand is a general-
purpose register.
The processor performs access checks as part of the loadin g process. Once loaded in the destination register, soft-
ware can perform additional checks on the access rights information. 
The access rights for a segment descriptor include fields located in the second doubleword (bytes 4–7) of the 
segment descriptor. The following fields are loaded by the LAR instruction:
•Bits 7:0 are returned as 0
•Bits 11:8 return the segment type.
•Bit 12 returns the S flag.
•Bits 14:13 return the DPL.
•Bit 15 returns the P flag.
•The following fields are returned only if the operand size is greater than 16 bits:
— Bits 19:16 are undefined.
— Bit 20 returns the software-available bit in the descriptor.— Bit 21 returns the L flag.
— Bit 22 returns the D/B flag.
— Bit 23 returns the G flag.— Bits 31:24 are returned as 0.
This instruction performs the following checks before it loads the access rights in the destination register: 
•Checks that the segment selector is not NULL.
•Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being 
accessed
•Checks that the descriptor type is valid for this instruct ion. All code and data segment descriptors are valid for 
(can be accessed with) the LAR instruction. The valid system segment and gate descriptor types are given in 
Table 3-53. 
•If the segment is not a conforming code segment, it ch ecks that the specified segment descriptor is visible at 
the CPL (that is, if the CPL and the RPL of the segment se lector are less than or equal to the DPL of the segment 
If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no 
access rights are loaded in the destination operand.Opcode Instruction Op/ 
En64-Bit 
0F 02 /r LAR r16, r16/m16 RM Valid Valid r16 := access rights referenced by r16/m16
0F 02 /r LAR reg, r32/m161RM Valid Valid reg := access rights referenced by r32/m16
NOTES:
1. For all loads (regardless of source  or destination sizing) only bits 16-0 are used. Other bits are ignored.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ALAR—Load Access Rights ByteINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-583The LAR instruction can only be executed  in protected mode and IA-32e mode.
Operation
IF Offset(SRC) > descriptor table limit
THEN 
ZF := 0; 
ELSE
SegmentDescriptor := descriptor referenced by SRC;IF SegmentDescriptor(Type) 
≠ conforming code segment
and (CPL > DPL) or (RPL > DPL)
or SegmentDescriptor(Type) is not valid for instruction
THEN
ZF := 0;
ELSE
DEST := access rights from SegmentDescriptor as given in Description section;ZF := 1;
FI;
FI;
The ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is cleared to 0.Table 3-53.  Segment and Gate Types
Type Protected Mode IA-32e Mode
Name Valid Name Valid
0 Reserved No Reserved No
1 Available 16-bit TSS Yes Reserved No
2 LDT Yes LDT Yes
3 Busy 16-bit TSS Yes Reserved No
4 16-bit call gate Yes Reserved No
5 16-bit/32-bit task gate Yes Reserved No
6 16-bit interrupt gate No Reserved No
7 16-bit trap gate No Reserved No
8 Reserved No Reserved No
9 Available 32-bit TSS Yes Available 64-bit TSS Yes
A Reserved No Reserved No
B Busy 32-bit TSS Yes Busy 64-bit TSS Yes
C 32-bit call gate Yes 64-bit call gate Yes
D Reserved No Reserved No
E 32-bit interrupt gate No 64-bit interrupt gate No
F 32-bit trap gate No 64-bit trap gate NoLAR—Load Access Rights ByteINSTRUCTION SET REFERENCE, A-L
3-584 Vol. 2AProtected Mode Exceptions

FI;
FI;
selector.
#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled and the me mory operand effective address is unaligned while 
the current privilege level is 3. 
#UD The LAR instruction is not recognized in real-address mode.
#UD The LAR instruction cannot be executed in virtual-8086 mode.
#SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical 
form.
#GP(0) If the memory operand effective address is in a non-canonical form.
#AC(0) If alignment checking is enabled and the me mory operand effective address is unaligned while 
the current privilege level is 3.
#UD If the LOCK prefix is used.LDDQU—Load Unaligned Integer 128 BitsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-585LDDQU—Load Unaligned Integer 128 Bits
The instruction is functionally similar to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is: 
32/16 bytes of data starting at an address specified by  the source memory operand (second operand) are fetched 
from memory and placed in a destination register (first  operand). The source operand need not be aligned on a 
32/16-byte boundary. Up to 64/32 bytes may be loaded  from memory; this is implementation dependent.
This instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line 
boundary. In situations that require the data loaded by (V )LDDQU be modified and stored to the same location, use 
(V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that 
are known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.
Implementation Notes
•If the source is aligned to a 32/16-byte boundary, based on the implementation, the 32/16 bytes may be loaded more than once. For that reason, the usage of  (V)LDDQU should be avoided when using uncached or 
write-combining (WC) memory regions. For uncached  or WC memory regions, keep using (V)MOVDQU.
•This instruction is a replacement for (V)MOVDQU (load) in  situations where cache line splits significantly affect 
performance. It should not be used in situations wh ere store-load forwarding is performance critical. If 
performance of store-load forwarding is critical to th e application, use (V)MOVDQA store-load pairs when data 
is 256/128-bit aligned or (V)MOVDQU store-load pairs when data is 256/128-bit unaligned.
•If the memory address is not aligned on 32/16-byte bo undary, some implementations may load up to 64/32 
bytes and return 32/16 bytes in the destination. Some processor implementations may issue multiple loads to 
access the appropriate 32/16 bytes. Developers of multi- threaded or multi-processor software should be aware 
that on these processors the loads w ill be performed in a non-atomic way.
•If alignment checking is enabled (CR0.AM = 1, RFLAGS .AC = 1, and CPL = 3), an alignment-check exception 
(#AC) may or may not be generated (depending on pr ocessor implementation) when the memory address is 
not aligned on an 8-byte boundary.
Note: In VEX-encoded versions, VEX.vvvv is reserved  and must be 1111b otherwise instructions will #UD.
Operation
LDDQU (128-bit Legacy SSE Version)
DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128 ] (Unmodified)Opcode/
ModeCPUID 
Feature 
F2 0F F0 /r
LDDQU xmm1, memRM V/V SSE3 Load unaligned data from mem and return 
double quadword in xmm1.
VEX.128.F2.0F.WIG F0 /r
VLDDQU xmm1, m128RM V/V AVX Load unaligned packed integer values from 
mem to xmm1.
VEX.256.F2.0F.WIG F0 /r
VLDDQU ymm1, m256RM V/V AVX Load unaligned packed integer values from 
mem to ymm1.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ALDDQU—Load Unaligned Integer 128 BitsINSTRUCTION SET REFERENCE, A-L
3-586 Vol. 2AVLDDQU (VEX.128 Encoded Version)
DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128] := 0
VLDDQU (VEX.256 Encoded Version)
DEST[255:0] := SRC[255:0]
LDDQU __m128i _mm_lddqu_si128 (__m128i * p);
VLDDQU __m256i _mm256_lddqu_si256 (__m256i * p);
None.
Note treatment of #AC varies.LDMXCSR—Load MXCSR RegisterINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-587LDMXCSR—Load MXCSR Register
Loads the source operand into the MXCSR control/status re gister. The source operand is a 32-bit memory location. 
See “MXCSR Control and Status Register” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 1, for a description of the MXCSR register and its contents.
The LDMXCSR instruction is typically used in conjunction  with the (V)STMXCSR instruction, which stores the 
contents of the MXCSR register in memory.
The default MXCSR value at reset is 1F80H.
If a (V)LDMXCSR instruction clears a SIMD floating-point  exception mask bit and sets the corresponding exception 
flag bit, a SIMD floating-point exception will not be i mmediately generated. The exception will be generated only 
upon the execution of the next instruct ion that meets both conditions below:
•the instruction must operate on an XMM or YMM register operand,
•the instruction causes that particular SIMD floating-point exception to be reported. 
If VLDMXCSR is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause 
Operation
MXCSR := m32;
_mm_setcsr(unsigned int i)
None.
See Table 2-22, “Type 5 Class Exce ption Conditions,” additionally:
#GP For an attempt to set reserved bits in MXCSR.
ModeCPUID 
Feature 
NP 0F AE /2
LDMXCSR m32M V/V SSE Load MXCSR register from m32.
VEX.LZ.0F.WIG AE /2
VLDMXCSR m32M V/V AVX Load MXCSR register from m32.
M ModRM:r/m (r) N/A N/A N/ALDS/LES/LFS/LGS/LSS—Load Far PointerINSTRUCTION SET REFERENCE, A-L
3-588 Vol. 2ALDS/LES/LFS/LGS/LSS—Load Far Pointer
Loads a far pointer (segment selector and offset) from  the second operand (source operand) into a segment 
register and the first operand (destination operand). The source operand specifies a 48-bit or a 32-bit pointer in 
memory depending on the current setting of the operand- size attribute (32 bits or 16 bits, respectively). The 
instruction opcode and the destination operand specify a segment register/general-purpose register pair. The 16-
bit segment selector from the source operand is loaded in to the segment register spec ified with the opcode (DS, 
SS, ES, FS, or GS). The 32-bit or 16-bit offset is loaded  into the register specified with the destination operand.
If one of these instructions is executed in protected mode, additional information from the segment descriptor 
pointed to by the segment selector in the source operan d is loaded in the hidden part of the selected segment 
register.
Also in protected mode, a NULL selector (values 0000 throug h 0003) can be loaded into DS, ES, FS, or GS registers 
without causing a protection exception. (Any subseque nt reference to a segment whose corresponding segment 
register is loaded with a NULL selector, causes a genera l-protection exception (#GP) and no memory reference to 
the segment occurs.)
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.W promotes 
operation to specify a source operand referencing an 80-bit  pointer (16-bit selector, 64-bit offset) in memory. Using 
a REX prefix in the form of REX.R permits access to addi tional registers (R8-R15). See the summary chart at the 
Operation
64-BIT_MODE
IF SS is loaded 
THEN 
IF SegmentSelector  = NULL and ( (RPL = 3) or 
(RPL ≠ 3 and RPL ≠ CPL) )
ELSE IF descriptor is in non-canonical spaceOpcode Instruction Op/ 
En64-Bit 
C5 /r LDS r16,m16:16 RM Invalid Valid Load DS:r16 with far pointer from memory.

Operation
THEN 
En64-Bit 
C5 /r LDS r32,m16:32 RM Invalid Valid Load DS:r32 with far pointer from memory.0F B2 /r LSS r16,m16:16 RM Valid Valid Load SS:r16 with far pointer from memory.0F B2 /r LSS r32,m16:32 RM Valid Valid Load SS:r32 with far pointer from memory.REX + 0F B2 /r LSS r64,m16:64 RM Valid N.E. Load SS:r64 with far pointer from memory.C4 /r LES r16,m16:16 RM Invalid Valid Load ES:r16 with far pointer from memory.C4 /r LES r32,m16:32 RM Invalid Valid Load ES:r32 with far pointer from memory.0F B4 /r LFS r16,m16:16 RM Valid Valid Load FS:r16 with far pointer from memory.0F B4 /r LFS r32,m16:32 RM Valid Valid Load FS:r32 with far pointer from memory.REX + 0F B4 /r LFS r64,m16:64 RM Valid N.E. Load FS:r64 with far pointer from memory.
0F B5 /r LGS r16,m16:16 RM Valid Valid Load GS:r16 with far pointer from memory.
0F B5 /r LGS r32,m16:32 RM Valid Valid Load GS:r32 with far pointer from memory.REX + 0F B5 /r LGS r64,m16:64 RM Valid N.E. L oad GS:r64 with far pointer from memory.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ALDS/LES/LFS/LGS/LSS—Load Far PointerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-589THEN #GP(selector); FI;
ELSE IF Segment selector index is not within descriptor table limits
or segment selector RPL ≠ CPL
or access rights indicate nonwritable data segmentor DPL
 ≠ CPL
THEN #GP(selector); FI;
ELSE IF Segment marked not present
THEN #SS(selector); FI;
FI;SS := SegmentSelector(SRC);SS := SegmentDes criptor([SRC]);
ELSE IF attempt to load DS, or ES 
THEN #UD;
ELSE IF FS, or GS is loaded with non-NULL segment selector
THEN IF Segment selector index is not within descri ptor table limits
or access rights indicate  segment neither data no r readable code segment
or segment is data or nonconforming-code segment and ( RPL > DPL or CPL > DPL)
THEN #NP(selector); FI;
FI;SegmentRegister := SegmentSelector(SRC) ;SegmentRegister := Segm entDescriptor([SRC]);
FI;
ELSE IF FS, or GS is load ed with a NULL selector:
THEN
SegmentRegister := NULLSelector;SegmentRegister(DescriptorValidBit) := 0; FI; (* Hidden flag; 
not accessible by software *)
FI;DEST := Offset(SRC);
PREOTECTED MODE OR COMPATIBILITY MODE;
THEN 
IF SegementSelector  
= NULL 
 ≠ CPL
ELSE IF DS, ES, FS, or GS is loaded with non-NULL segment selector
or segment is data or nonconforming-code segment and (RPL > DPL or CPL > DPL) 
ELSE IF Segment marked not presentLDS/LES/LFS/LGS/LSS—Load Far PointerINSTRUCTION SET REFERENCE, A-L
3-590 Vol. 2ATHEN #NP(selector); FI;
FI;SegmentRegister := SegmentSelector(SRC) AND RPL;SegmentRegister := Segm entDescriptor([SRC]);
FI;
ELSE IF DS, ES, FS, or GS is loaded with a NULL selector:
THEN
SegmentRegister := NULLSelector;SegmentRegister(DescriptorValidB it) := 0; FI; (* Hidden flag; 
Real-Address or Virtual-8086 Mode
SegmentRegister := SegmentSelector(SRC); FI;DEST := Offset(SRC);
None.
#UD If source operand is not a memory location.
#GP(0) If a NULL selector is loaded into the SS register.
selector.
#GP(selector) If the SS register is being loaded and an y of the following is true: the segment selector index 
is not within the descriptor table limits, the se gment selector RPL is not equal to CPL, the 
segment is a non-writable data segment, or DPL is not equal to CPL.
If the DS, ES, FS, or GS register is being load ed with a non-NULL segment selector and any of 
the following is true: the segment selector index is not within descriptor table limits, the 
segment is neither a data nor a readable code segment, or the segment is a data or noncon-forming-code segment and both RPL and CPL are greater than DPL.
#SS(selector) If the SS register is being loaded and the segment is marked not present.#NP(selector) If DS, ES, FS, or GS register is bein g loaded with a non-NULL segment selector and the 
segment is marked not present.
If the LOCK prefix is used.LDS/LES/LFS/LGS/LSS—Load Far PointerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-591Virtual-8086 Mode Exceptions
If a NULL selector is attempted to be loaded  into the SS register in compatibility mode.
If a NULL selector is attempted to be loaded into the SS register in CPL3 and 64-bit mode.
If a NULL selector is attempted to be loaded in to the SS register in non-CPL3 and 64-bit mode 
where its RPL is not equal to CPL.
#GP(Selector) If the FS, or GS register is being load ed with a non-NULL segment selector and any of the 
following is true: the segment selector index is  not within descriptor table limits, the memory 
address of the descriptor is non-canonical, the segment is neither a data nor a readable code 
segment, or the segment is a data or noncon forming-code segment and both RPL and CPL are 
greater than DPL.
If the SS register is being load ed and any of the following is true: the segment selector index 
is not within the descriptor table limits, the memory address of the descriptor is non-canon-ical, the segment selector RPL is not equal to CPL, the segment is a nonwritable data segment, 
or DPL is not equal to CPL.
#SS(0) If a memory operand effective address is non-canonical#SS(Selector) If the SS register is being loaded and the segment is marked not present.
#NP(selector) If FS, or GS register is being loaded with a non-NULL segment selector and the segment is 
If the LOCK prefix is used.LDTILECFG—Load Tile ConfigurationINSTRUCTION SET REFERENCE, A-L
3-592 Vol. 2ALDTILECFG—Load Tile Configuration
The LDTILECFG instruction takes an operand containing a pointer to a 64-byte memory location containing the 
description of the tiles to be supported. In order to config ure the tiles, the AMX-TILE bit in CPUID must be set and 
the operating system has to have enabled the tiles architecture.
The memory area contains the palette and describes how many tiles are being used and defines each tile in terms 
of rows and column bytes. Requests must be compatible with the restrictions provided by CPUID; see Table 3-10 
below. 
If a tile row and column pair is not used to specify tile parameters, they must have the value zero. All enabled tiles 
(based on the palette) must be configured. Specifying tile  parameters for more tiles than the implementation limit 
or the palette limit results in a #GP fault. 
If the palette_id is zero, that signifies the INIT state fo r both TILECFG and TILEDATA. Tiles are zeroed in the INIT 
state. The only legal non-INIT value for palette_id is 1.
Any attempt to execute the LDTILECFG instruction inside an Intel TSX transaction will result in a transaction abort.Opcode/
Mode 
VEX.128.NP.0F38.W0 49 !(11):000:bbb
LDTILECFG m512A V/N.E. AMX-TILE Load tile configuration as specified in m512.
A N/A ModRM:r/m (r) N/A N/A N/A
Table 3-10. Memory Area Layout

below. 
Mode 
Byte(s) Field Name Description0 palette Palette selects the su pported configuration of the tiles that will be used.
1 start_row start_row is used for storing the restart values for interrupted operations.2-15 reserved, must be zero
16-17 tile0.colsb Tile 0 bytes per row.
18-19 tile1.colsb Tile 1 bytes per row.20-21 tile2.colsb Tile 2 bytes per row.
... (sequence  continues)
30-31 tile7.colsb Tile 7 bytes per row.32-47 reserved, must be zero
48 tile0.rows Tile 0 rows.
49 tile1.rows Tile 1 rows.50 tile2.rows Tile 2 rows.
55 tile7.rows Tile 7 rows.56-63 reserved, must be zeroLDTILECFG—Load Tile ConfigurationINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-593Operation
LDTILECFG mem
error := Falsebuf := read_memory(mem, 64) temp_tilecfg.palette_id := buf.byte[0]if temp_tilecfg.pale tte_id > max_palette: 
error := True
if not xcr0_supports_palette(temp_tilecfg.palette_id): 
if temp_tilecfg.palette_id !=0: 
temp_tilecfg.start_r ow := buf.byte[1] 
if buf.byte[2..15] is nonzero:
p := 16# configure columns
for n in 0 ... palette_table[temp _tilecfg.palette_id].max_names-1:
temp_tilecfg.t[n].co lsb:= buf.word[p/2]
p := p + 2if temp_tilecfg.t[n].colsb > palette_table[temp_tilecfg. palette_id].bytes_per_row:
if nonzero(buf[p...47]):
# configure rows
p := 48for n in 0 ... palette_table[temp _tilecfg.palette_id].max_names-1:
temp_tilecfg.t[n].ro ws:= buf.byte[p]
if temp_tilecfg.t[n].rows > palette_t able[temp_tilecfg.pa lette_id].max_rows:
p := p + 1
if nonzero(buf[p...63]):
# validate each tile's row & col configs are reasonable and enable the valid tiles
if temp_tilecfg.t[n].rows !=0 an d temp_tilecfg.t[n].colsb != 0:
temp_tilecfg.t[n].valid := 1
elif temp_tilecfg.t[n].rows == 0 and temp_tilecfg.t[n].colsb == 0:
temp_tilecfg.t[n].valid := 0
else:
error := True// one of rows or colsbwas 0 but not both.
if error:
#GP
elif temp_tilecfg.palette_id == 0:
TILES_CONFIGURED := 0// init statetilecfg := 0// equivale nt to 64B of zeros
zero_all_tile_data()
else:
tilecfg := temp_tilecfgzero_all_tile_data()TILES_CONFIGURED := 1LDTILECFG—Load Tile ConfigurationINSTRUCTION SET REFERENCE, A-L
3-594 Vol. 2AIntel C/C++ Compiler Intrinsic Equivalent
LDTILECFG void _tile_loadconfig(const void *);
None.
AMX-E1; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.LEA—Load Effective AddressINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-595LEA—Load Effective Address
Computes the effective address of the second operand (the  source operand) and stores it in the first operand 
(destination operand). The source operand is a memory a ddress (offset part) specified with one of the processors 
addressing modes; the destination operand is a general-pu rpose register. The address-size and operand-size attri-
butes affect the action performed by this instruction, as shown in the following table. The operand-size attribute of 
the instruction is determined by the chosen register; the address-size attribute is dete rmined by the attribute of 
the code segment.
Different assemblers may use different algorithms based on the size attribute and symbolic reference of the source 
operand.
In 64-bit mode, the instruction’s destination operand is governed by operand size attribute, the default operand 
size is 32 bits. Address calculation is governed by addre ss size attribute, the default address size is 64-bits. In 64-
bit mode, address size of 16 bits is not encodable. See Table 3-55.Opcode Instruction Op/ 
En64-Bit 
8D /r LEA r16,m RM Valid Valid Store effective address for m in register r16.
8D /r LEA r32,m RM Valid Valid Store effective address for m in register r32.REX.W + 8D /r LEA r64,m RM Valid N.E. Store effective address for m in register r64. 
RM ModRM:reg (w) ModRM:r/m (r) N/A N/A
Table 3-54.  Non-64-bit Mode LEA Operation with Address and Operand Size Attributes
Operand Size Address Size Action Performed
16 16 16-bit effective address is calculated and stored in requested 16-bit register destination.
16 32 32-bit effective address is calculated. The lower 16 bits of the address are stored in the 
requested 16-bit register destination.
32 16 16-bit effective address is calculated. The 16-bit address is zero-extended and stored in the requested 32-bit register destination.
32 32 32-bit effective address is calculated and stored in the requested 32-bit register destination.
Table 3-55.  64-bit Mode LEA Operation with Address and Oper and Size Attributes
Operand Size Address Si ze Action Performed
16 32 32-bit effective address is calculated (using 67H prefix). The lower 16 bits of the address are 
stored in the requested 16-bit register destination (using 66H prefix).
16 64 64-bit effective address is calculated (default address size). The lower 16 bits of the address are stored in the requested 16-bit re gister destination (using 66H prefix).
32 32 32-bit effective address is calculated (using 67H prefix) and stored in the requested 32-bit 
register destination.
32 64 64-bit effective address is calculated (default address size) and the lower 32 bits of the address are stored in the requested 32-bit register destination.
64 32 32-bit effective address is calculated (using 67H prefix), zero-extended to 64-bits, and stored in the requested 64-bit register destination (using REX.W).
64 64 64-bit effective address is calculated (default address size) and all 64-bits of the address are stored in the requested 64-bit register destination (using REX.W).LEA—Load Effective AddressINSTRUCTION SET REFERENCE, A-L
3-596 Vol. 2AOperation
IF OperandSize  = 16 and AddressSize  = 16
THEN 
DEST := EffectiveAddress(S RC); (* 16-bit address *)
ELSE IF OperandSize  = 16 and AddressSize  = 32
THEN
temp := EffectiveAddress(SR C); (* 32-bit address *)
DEST := temp[0:15]; (* 16-bit address *)
FI;
ELSE IF OperandSize = 32 and AddressSize = 16
THEN
temp := EffectiveAddress(SR C); (* 16-bit address *)
DEST := ZeroExtend(temp); (* 32-bit address *)
FI;
ELSE IF OperandSize  = 32 and AddressSize  = 32
THEN 
DEST := EffectiveAddress(S RC); (* 32-bit address *)
FI;
ELSE IF OperandSize  = 16 and AddressSize  = 64
THEN 
temp := EffectiveAddress(SR C); (* 64-bit address *)
FI;
ELSE IF OperandSize  = 32 and AddressSize  = 64
THEN 
DEST := temp[0:31]; (* 16-bit address *)
FI;
ELSE IF OperandSize  = 64 and AddressSize  = 64
THEN 
DEST := EffectiveAddress(S RC); (* 64-bit address *)
FI;
FI;
None.
Same exceptions as in protected mode.LEAVE—High Level Procedure ExitINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-597LEAVE—High Level Procedure Exit
Releases the stack frame set up by an earlier ENTER instru ction. The LEAVE instruction copies the frame pointer (in 
the EBP register) into the stack pointer register (ESP), wh ich releases the stack space allocated to the stack frame. 
The old frame pointer (the frame pointer for the calling proc edure that was saved by the ENTER instruction) is then 
popped from the stack into the EBP register, restoring the calling procedure’s stack frame. 
A RET instruction is commonly executed following a LEAVE instruction to return program control to the calling 
See “Procedure Calls for Block-Structured  Languages” in Chapter 7 of the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 1, for detailed inform ation on the use of the ENTER and LEAVE instructions.
In 64-bit mode, the instruction’s default operation size is 64 bits; 32-bit operation cannot be encoded. See the 
summary chart at the beginning of this section for encoding data and limits.
Operation
IF StackAddressSize  = 32
THEN
ESP := EBP;
ELSE IF StackAddressSize  = 64
THEN RSP := RBP; FI;
ELSE IF StackAddressSize  = 16
THEN SP := BP; FI;
FI;
THEN EBP := Pop();ELSE IF OperandSize  
= 64
THEN RBP := Pop(); FI;
ELSE IF OperandSize = 16
THEN BP := Pop(); FI;
FI;
En64-Bit 
C9 LEAVE ZO Valid Valid Set SP to BP, then pop BP.
C9 LEAVE ZO N.E. Valid Set ESP to EBP, then pop EBP.C9 LEAVE ZO Valid N.E. Set RSP to RBP, then pop RBP.
ZO N/A N/A N/A N/ALEAVE—High Level Procedure ExitINSTRUCTION SET REFERENCE, A-L
3-598 Vol. 2AProtected Mode Exceptions
#SS(0) If the EBP register points to a location that is not within the limits of the current stack 
segment.

Operation
THEN
ESP := EBP;
FI;
= 64
FI;
En64-Bit 
segment.
#GP If the EBP register points to a location outside of the effective address space from 0 to FFFFH.#UD If the LOCK prefix is used.
#GP(0) If the EBP register points to a location ou tside of the effective address space from 0 to FFFFH.
#SS(0) If the stack address is in a non-canonical form.#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the 
#UD If the LOCK prefix is used.LFENCE—Load FenceINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-599LFENCE—Load Fence
Performs a serializing operation on al l load-from-memory instructions that were issued prior the LFENCE instruc-
tion. Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruc-
tion begins execution until LFENCE completes. In particular, an instruction that loads from memory and that 
precedes an LFENCE receives data from memory prior to  completion of the LFENCE. (An LFENCE that follows an 
instruction that stores to memory might complete before  the data being stored have  become globally visible.) 
Instructions following an LFENCE may be fetched from me mory before the LFENCE, but they will not execute (even 
speculatively) until the LFENCE completes. 
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as 
out-of-order issue and speculative reads. The degree to which a consumer of data recognizes or knows that the 
data is weakly ordered varies among applications and may be unknown to the producer of this data. The LFENCE 
instruction provides a performance-efficient way of ensuri ng load ordering between routines that produce weakly-
ordered results and routines that consume that data.
Processors are free to fetch and cache data speculativel y from regions of system memory that use the WB, WC, 
and WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. 
Thus, it is not ordered with respect to executions of the LFENCE instruction; data can be brought into the caches 
speculatively just before, during, or after the execution of an LFENCE instruction.
Specification of the instruction's opcode above indicates a ModR/M byte of E8. For this instruction, the processor 
ignores the r/m field of the ModR/M byte. Thus, LFENCE is encoded by any opcode of the form 0F AE Ex, where x is 
in the range 8-F.
Operation
Wait_On_Following_Instructions_Until(preceding_instructions_complete);
void _mm_lfence(void)
Exceptions (All Modes of Operation)
#UD If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.Opcode /
Mode 
Feature 
NP 0F AE E8
LFENCEZO V/V SSE2 Serializes load operations.
ZO N/A N/A N/A N/ALGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-L
3-600 Vol. 2ALGDT/LIDT—Load Global/Interru pt Descriptor Table Register
Loads the values in the source operand into the global de scriptor table register (GDTR) or the interrupt descriptor 
table register (IDTR). The source operand specifies a 6-by te memory location that contains the base address (a 
linear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor 
table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32-
bit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute 
is 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base  address (third, fourth, and fifth byte) are loaded. Here, 
the high-order byte of the operand is not used and the high -order byte of the base address in the GDTR or IDTR is 
filled with zeros.
The LGDT and LIDT instructions are used only in operat ing-system software; they are not used in application 
programs. They are the only instructions that directly load a linear address (that is, not a segment-relative 
address) and a limit in protected mode. They are commo nly executed in real-address mode to allow processor 
initialization prior to switching to protected mode.
In 64-bit mode, the instruction’s operand size is fixed at  8+2 bytes (an 8-byte base and a 2-byte limit). See the 
See “SGDT—Store Global Descriptor Table Register” in Chapter 4, of the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2B, for informatio n on storing the contents of the GDTR and IDTR.Opcode Instruction Op/ 
En64-Bit 
0F 01 /2 LGDT m16&32 M N.E. Valid Load m into GDTR.
0F 01 /3 LIDT m16&32 M N.E. Valid Load m into IDTR.0F 01 /2 LGDT m16&64 M Valid N.E. Load m into GDTR.0F 01 /3 LIDT m16&64 M Valid N.E. Load m into IDTR.
M ModRM:r/m (r) N/A N/A N/ALGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-601Operation
IF Instruction is LIDT
THEN
THEN 
IDTR(Limit) := SRC[0:15];IDTR(Base) := SRC[16:47] AND 00FFFFFFH; 
ELSE IF 32-bit Operand Size
THEN
IDTR(Limit) := SRC[0:15];IDTR(Base) := SRC[16:47]; 
FI;
ELSE IF 64-bit Operand Si ze (* In 64-Bit Mode *)
THEN
IDTR(Limit) := SRC[0:15];
IDTR(Base) := SRC[16:79]; 
FI;
FI;
ELSE (* Instruction is LGDT *)
= 16
THEN 
GDTR(Limit) := SRC[0:15];GDTR(Base) := SRC[16:47] AND 00FFFFFFH; 
THEN
GDTR(Limit) := SRC[0:15];GDTR(Base) := SRC[16:47]; 
FI;
THEN
GDTR(Limit) := SRC[0:15];GDTR(Base) := SRC[16:79]; 
FI;
FI; 
FI;
None.
selector.
#PF(fault-code) If a page fault occurs.LGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-L
3-602 Vol. 2AReal-Address Mode Exceptions
#UD If the LOCK prefix is used.#GP If the current privilege level is not 0.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#GP(0) If the current privilege level is not 0.
#UD If the LOCK prefix is used.#PF(fault-code) If a page fault occurs.LLDT—Load Local Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-603LLDT—Load Local Descriptor Table Register
Loads the source operand into the segment selector field of the local descriptor table register (LDTR). The source 
operand (a general-purpose register or a memory location) contains a segment selector that points to a local descriptor table (LDT). After the segmen t selector is loaded in the LDTR, the processor uses the segment selector 
to locate the segment descriptor for the LDT in the global  descriptor table (GDT). It then loads the segment limit 
and base address for the LDT from the segment descripto r into the LDTR. The segment registers DS, ES, SS, FS, 
GS, and CS are not affected by this instruction, nor is th e LDTR field in the task state segment (TSS) for the current 
task.
If bits 2-15 of the source operand are 0, LDTR is marked invalid and the LLDT instruction completes silently. 
However, all subsequent references to descriptors in the LDT (except by the LAR, VERR, VERW or LSL instructions) 
cause a general protection exception (#GP).
The operand-size attribute has no effect on this instruction. The LLDT instruction is provided for use in operating-sy stem software; it should not be used in application 
programs. This instruction can only be exec uted in protected mode or 64-bit mode.
In 64-bit mode, the operand size is fixed at 16 bits.
Operation

task.
Operation
IF SRC(Offset) > descriptor table limit 
IF segment selector is valid
Read segment descriptor;
IF SegmentDescriptor(Type) ≠ LDT 
IF segment descriptor is not present 
LDTR(SegmentSelector) := SRC;
LDTR(SegmentDescriptor) := GDTSegmentDescriptor;
ELSE LDTR := INVALIDFI;
En64-Bit 
0F 00 /2 LLDT r/m16 M Valid Valid Load segment selector r/m16 into LDTR.
M ModRM:r/m (r) N/A N/A N/ALLDT—Load Local Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-L
3-604 Vol. 2AProtected Mode Exceptions
#GP(selector) If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT 
is not a Local Descriptor Table.
Segment selector is beyond GDT limit.
#NP(selector) If the LDT descriptor is not present.#PF(fault-code) If a page fault occurs.
#UD The LLDT instruction is not recognized in real-address mode.
#UD The LLDT instruction is not recognized in virtual-8086 mode.
#NP(selector) If the LDT descriptor is not present.
#UD If the LOCK prefix is used.LMSW—Load Machine Status WordINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-605LMSW—Load Machine Status Word
Loads the source operand into the machine status word, bits  0 through 15 of register CR0. The source operand can 
be a 16-bit general-purpose register or a memory location . Only the low-order 4 bits of the source operand (which 
contains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are 
not affected. The operand-size attribute has no effect on this instruction.
If the PE flag of the source operand (bit 0) is set to 1,  the instruction causes the processor to switch to protected 
mode. While in protected mode, the LMSW  instruction cannot be used to clear the PE flag and force a switch back 
to real-address mode.
The LMSW instruction is provided for use in operating-sy stem software; it should not be used in application 
programs. In protected or virtual-8086 mo de, it can only be executed at CPL 0.
This instruction is provided for compatibility with the In tel 286 processor; programs and procedures intended to 
run on IA-32 and Intel 64 processors beginning with Inte l386 processors should use the MOV (control registers) 
instruction to load the whole CR0 register. The MOV CR0 instru ction can be used to set and clear the PE flag in CR0, 
allowing a procedure or program to switch between protected and real-address modes.
This instruction is a serializing instruction.
This instruction’s operation is the same in non-64-bit mode s and 64-bit mode. Note that the operand size is fixed 
at 16 bits.
Operation
CR0[0:3] := SRC[0:3];
None.
selector.
#PF(fault-code) If a page fault occurs.#UD If the LOCK prefix is used.
En64-Bit 
0F 01 /6 LMSW r/m16 M Valid Valid Loads r/ m16 in machine status word of CR0.
M ModRM:r/m (r) N/A N/A N/ALMSW—Load Machine Status WordINSTRUCTION SET REFERENCE, A-L
3-606 Vol. 2AVirtual-8086 Mode Exceptions
#GP(0) The LMSW instruction is not recognized in virtual-8086 mode.
#UD If the LOCK prefix is used.LOADIWKEY—Load Internal Wrapping Key With Key LockerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-607LOADIWKEY—Load Internal Wrapping Key With Key Locker
The LOADIWKEY1 instruction writes the Key Locker internal wrappi ng key, which is called IWKey. This IWKey is 
used by the ENCODEKEY* instructions to wrap keys in to handles. Conversely, the AESENC/DEC*KL instructions 
use IWKey to unwrap those keys from the handles and help verify the handle integrity. For security reasons, no 
instruction is designed to allow software to directly read the IWKey value.
IWKey includes two cryptographic keys as well as metadata . The two cryptographic keys are loaded from register 
sources so that LOADIWKEY can be executed without the keys ever being in memory.
The key input operands are:
•The 256-bit encryption key is loaded from the two explicit operands.
•The 128-bit integrity key is loaded from the implicit operand XMM0.
The implicit operand EAX specifies the KeySourc e and whether backing up the key is permitted:
•EAX[0] – When set, the wrapping key being initialized is not permitted to be backed up to platform-scoped 
storage.
•EAX[4:1] – This specifies the KeySource, which is the ty pe of key. Currently only two encodings are supported. 
A KeySource of 0 indicates that the key input operands  described above should be directly stored as the 
internal wrapping keys. LOADIWKEY with a KeySource of  1 will have random numbers from the on-chip random 
number generator XORed with the source registers (inclu ding XMM0) so that the software that executes the 
LOADIWKEY does not know the actual IWKey encryption and integrity keys. Software can choose to put 
additional random data into the source registers so th at other sources of random data are combined with the 
hardware random number generator supplied value. Software should always check ZF after executing 
LOADIWKEY with KeySource of 1 as this operation may fail due to it being unable to get sufficient full-entropy 
data from the on-chip random number generator. Both Ke ySource of 0 and 1 specify that IWKey be used with 
the AES-GCM-SIV algorithm. CPUID.19H .ECX[1] enumerates support for KeySource of 1. All other KeySource 
encodings are reserved.
•EAX[31:5] – Reserved.Opcode/
ModeCPUID 
Feature 
F3 0F 38 DC 11:rrr:bbb 
LOADIWKEY xmm1, xmm2, <EAX>, <XMM0>A V/V KL Load internal wrapping key from xmm1, xmm2, and 
XMM0.
A N/A ModRM:reg (r) ModRM:r/m (r) Implicit EAX (r) Implicit XMM0 (r)
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html .LOADIWKEY—Load Internal Wrapping Key With Key LockerINSTRUCTION SET REFERENCE, A-L
3-608 Vol. 2AOperation
LOADIWKEY 
IF CPL > 0 // LOADKWKEY only allowed at ring 0 (supervisor mode)
THEN #GP (0); FI;
IF EAX[4:1] > 1 // Reserved KeySource encoding used
IF EAX[31:5] != 0 // Rese rved bit in EAX is set
IF EAX[0] AND (CPUID.19H.ECX[0] == 0) // NoBackup is not supported on this part
IF (EAX[4:1] == 1) AND (CPUID.19H.ECX[1] == 0) // KeySource of 1 is not supported on this part
IF (EAX[4:1] == 0) // KeySource of 0
THEN
IWKey.Encryption  Key[127:0] := SRC2[127:0]:
IWKey.Encryption Key[255:128] := SRC1[127:0];
IWKey.IntegrityKey[127:0] := XMM0[127:0];IWKey.NoBackup = EAX [0];IWKey.KeySource = EAX [4:1];RFLAGS.ZF := 0; 
ELSE // KeySource of 1. See RDSEED definition for details of randomness

LOADIWKEY 
THEN
IF HW_NRND_GEN.ready == 1 // Full- entropy random data from RDSEED hardware block was received
THEN
IWKey.Encryption Key[127:0] := SRC2 [127:0] XOR HW_NRND_GEN.data[127:0];
IWKey.Encryption Key[255:128] := SRC1 [127:0] XOR HW_NRND_GEN.data[255:128];
IWKey.IntegrityKey[127:0] := XMM0[1 27:0] XOR HW_NRND_GEN.data[383:256];
IWKey.NoBackup = EAX [0];IWKey.KeySource = EAX [4:1];RFLAGS.ZF := 0; 
ELSE // Random data was not returned from RDSEED hardware block. IWKey was not loaded
RFLAGS.ZF := 1; 
FI;
ZF is set to 0 if the operation succeeded and set to 1 if  the operation failed due to full-entropy random data not 
being received from RDSEED. The other arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
LOADIWKEY void _mm_loadiwkey(unsign ed int ctl, __m128i intkey, __m128i enkey_lo, __m128i enkey_hi);LOADIWKEY—Load Internal Wrapping Key With Key LockerINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-609Exceptions (All Operating Modes)
#GP If CPL > 0. (Does not apply in real-address mode.)
If EAX[4:1] > 1.If EAX[31:5] != 0.
If (EAX[0] == 1) AND (C PUID.19H.ECX[0] == 0).
If (EAX[4:1] == 1) AND (CPUID.19H.ECX[1] == 0).
If CR4.KL = 0.If CR0.EM = 1.
#NM If CR0.TS = 1.LOCK—Assert LOCK# Signal PrefixINSTRUCTION SET REFERENCE, A-L
3-610 Vol. 2ALOCK—Assert LOCK# Signal Prefix
Causes the processor’s LOCK# signal to be asserted duri ng execution of the accompanying instruction (turns the 
instruction into an atomic instruction). In a multiprocessor environment, the LOCK# signal ensures that the processor has exclusive use of any shared memory while the signal is asserted.
In most IA-32 and all Intel 64 processors, locking may occur without the LOCK# signal being asserted. See the “IA-
32 Architecture Compatibility” section below for more details.
The LOCK prefix can be prepended only to the following instructions and only to those forms of the instructions 
where the destination operand is a memory operand: AD D, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B, 
CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If the LOCK prefix is used with one of 
these instructions and the source operand is a memory operand, an undefined opcode exception (#UD) may be 
generated. An undefined opcode exception will also be genera ted if the LOCK prefix is used with any instruction not 
in the above list. The XCHG instruction always asserts the LOCK# signal regardless of the presence or absence of the LOCK prefix.
The LOCK prefix is typically used with the BTS instruct ion to perform a read-modify-write operation on a memory 
location in shared memory environment.
The integrity of the LOCK prefix is no t affected by the alignment of the memo ry field. Memory locking is observed 
for arbitrarily misaligned fields.
Beginning with the P6 family processors, when the LOCK prefix is prefixed to an instruction and the memory area 
being accessed is cached internally in the processor, the LOCK# signal is generally not asserted. Instead, only the 
processor’s cache is locked. Here, the processor’s cache coherency mechanism ensures that the operation is 
carried out atomically with regards to memory. See “Effects of a Locked Operation on Internal Processor Caches” in Chapter 9 of Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, the for more informa-
tion on locking of caches.
Operation
AssertLOCK#(DurationOfAccompaningInstruction);
None.
#UD If the LOCK prefix is used with an instruction not listed: ADD, ADC, AND, BTC, BTR, BTS, 
CMPXCHG, CMPXCH8B, CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, 
XCHG.
Other exceptions can be generated by the instruction when the LOCK prefix is applied.Opcode1
NOTES:
1. See IA-32 Architecture Compatibility section below.Instruction Op/ 
En64-Bit 
F0 LOCK ZO Valid Valid Asserts LOCK# signal for duration of the 
accompanying instruction.
ZO N/A N/A N/A N/ALOCK—Assert LOCK# Signal PrefixINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-611Real-Address Mode Exceptions
Same exceptions as in protected mode.LODS/LODSB/LODSW/LODSD/LODSQ—Load StringINSTRUCTION SET REFERENCE, A-L
3-612 Vol. 2ALODS/LODSB/LODSW/LOD SD/LODSQ—Load String
Loads a byte, word, or doubleword from the source oper and into the AL, AX, or EAX register, respectively. The 
source operand is a memory location, the address of wh ich is read from the DS:ESI or the DS:SI registers 
(depending on the address-size attribute of the instructio n, 32 or 16, respectively). The DS segment may be over-
ridden with a segment override prefix.
operands” form. The explicit-operands form (specified with  the LODS mnemonic) allows the source operand to be 
specified explicitly. Here, the source operand should be a sy mbol that indicates the size and location of the source 
value. The destination operand is then automatically sele cted to match the size of the source operand (the AL 
register for byte operands, AX for word operands, and EA X for doubleword operands). This explicit-operands form 
is provided to allow documentation; however, note th at the documentation provided by this form can be 
misleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or 
doubleword), but it does not have to specify the correct location . The location is always specified by the DS:(E)SI 
registers, which must be loaded correctly before the load string instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the LODS instructions. 
Here also DS:(E)SI is assumed to be the source operand an d the AL, AX, or EAX register is assumed to be the desti-
nation operand. The size of the source and destinatio n operands is selected with the mnemonic: LODSB (byte 
loaded into register AL), LODSW (word loaded in to AX), or LODSD (doubleword loaded into EAX).
After the byte, word, or doubleword is transferred from th e memory location into the AL, AX, or EAX register, the 
(E)SI register is incremented or decrem ented automatically according to the se tting of the DF flag in the EFLAGS 
register. (If the DF flag is 0, the (E)SI register is incremen ted; if the DF flag is 1, the ESI register is decremented.) 
The (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for 
doubleword operations.Opcode Instruction Op/ 
En64-Bit 
AC LODS m8 ZO Valid Valid For legacy mode, Load byte at address DS:(E)SI 
into AL. For 64-bit mode  load byte at address 
(R)SI into AL.
AD LODS m16 ZO Valid Valid For legacy mode, Load word at address 
DS:(E)SI into AX. For 64-b it mode load word at 
address (R)SI into AX.
AD LODS m32 ZO Valid Valid For legacy mode, Load dword at address 
DS:(E)SI into EAX. For 64-bit mode load dword at address (R)SI into EAX.
REX.W + AD LODS m64 ZO Valid N.E. Load qword at address (R)SI into RAX.AC LODSB ZO Valid Valid For legacy mode, Load byte at address DS:(E)SI 
AD LODSW ZO Valid Valid For legacy mode, Load word at address 
AD LODSD ZO Valid Valid For legacy mode, Load dword at address 
DS:(E)SI into EAX. For 64-bit mode load dword 
at address (R)SI into EAX.
REX.W + AD LODSQ ZO Valid N.E. Load qword at address (R)SI into RAX.
ZO N/A N/A N/A N/ALODS/LODSB/LODSW/LODSD/LODSQ—Load StringINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-613In 64-bit mode, use of the REX.W prefix promotes operatio n to 64 bits. LODS/LODSQ load the quadword at address 
(R)SI into RAX. The (R)SI register is then incremented or decremented automatically according to the setting of 
the DF flag in the EFLAGS register. 
The LODS, LODSB, LODSW, and LODSD instructions can be  preceded by the REP pref ix for block loads of ECX 
bytes, words, or doublewords. More often, however, th ese instructions are used within a LOOP construct because 
further processing of the data moved into the register is  usually necessary before the next transfer can be made. 
See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” in Ch apter 4 of the Intel® 64 and IA-32

See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” in Ch apter 4 of the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volu me 2B, for a description of the REP prefix.
Operation
IF AL := SRC; (* Byte load *)
THEN AL := SRC; (* Byte load *)
IF DF = 0
THEN (E)SI := (E)SI + 1; 
ELSE (E)SI := (E)SI – 1; 
FI;
ELSE IF AX := SRC;  (* Word load *)
THEN (E)SI := (E)SI + 2; 
ELSE (E)SI := (E)SI – 2; 
IF;
FI;
ELSE IF EAX := SRC; (* Doubleword load *)
THEN (E)SI := (E)SI + 4; 
ELSE (E)SI := (E)SI – 4; 
FI;
FI;
ELSE IF RAX := SRC; (* Quadword load *)
THEN (R)SI := (R)SI + 8; 
ELSE (R)SI := (R)SI – 8; 
FI;
FI;
FI;
None.
#UD If the LOCK prefix is used.LODS/LODSB/LODSW/LODSD/LODSQ—Load StringINSTRUCTION SET REFERENCE, A-L
3-614 Vol. 2AVirtual-8086 Mode Exceptions
#UD If the LOCK prefix is used.LOOP/LOOPcc—Loop According to ECX CounterINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-615LOOP/LOOP cc—Loop According to ECX Counter
Performs a loop operation using the RCX, ECX or CX register as a counter (depending on whether address size is 64 
bits, 32 bits, or 16 bits). Note that the LOOP instruction ignores REX.W; but 64-bit address size can be over-ridden 
using a 67H prefix.
Each time the LOOP instruction is executed, the count register is decremented, then checked for 0. If the count is 
0, the loop is terminated and program execution continues with the instruction following the LOOP instruction. If 
the count is not zero, a near jump is performed to the destination (target) operand,  which is presumably the 
instruction at the beginning of the loop.
tion pointer in the IP/EIP/RIP register). This offset is generally specified as a label in assembly code, but at the 
machine code level, it is encoded as a signed, 8-bit imme diate value, which is added to the instruction pointer. 
Offsets of –128 to +127 are allowed with this instruction.
Some forms of the loop instruction (LOOP cc) also accept the ZF flag as a condition for terminating the loop before 
the count reaches zero. With these forms of the instruction, a condition code ( cc) is associated with each instruc-
tion to indicate the condition being tested for. Here, the LOOP cc instruction itself does not affect the state of the ZF 
flag; the ZF flag is changed by other instructions in the loop.
Operation
IF (AddressSize = 32)
THEN Count is ECX;
ELSE IF (AddressSize = 64)
Count is RCX;
ELSE Count is CX; FI;
Count := Count – 1;IF Instruction is not LOOP
THEN
IF (Instruction := LOOPE) or (Instruction := LOOPZ)
THEN IF (ZF 
= 1) and (Count  ≠ 0)
THEN BranchCond := 1;ELSE BranchCond := 0;
FI;
ELSE (Instruction 
= LOOPNE) or (Instruction = LOOPNZ)
IF (ZF = 0 ) and (Count ≠ 0)
En64-Bit 
E2 cb LOOP rel8 D Valid Valid Decreme nt count; jump short if count ≠ 0.
E1 cb LOOPE rel8 D Valid Valid Decrement count; jump short if count ≠ 0 and 
ZF = 1.
E0 cb LOOPNE rel8 D Valid Valid Decreme nt count; jump short if count ≠ 0 and 
ZF = 0.
D Offset N/A N/A N/ALOOP/LOOPcc—Loop According to ECX CounterINSTRUCTION SET REFERENCE, A-L
3-616 Vol. 2AFI;
ELSE (* Instruction = LOOP *)
IF (Count ≠ 0)
FI;
FI;
IF BranchCond 
= 1
THEN
IF in 64-bit mode (* OperandSize = 64 *)
THEN
tempRIP := RIP + SignExtend(DEST);IF tempRIP is not canonical
ELSE RIP := tempRIP;FI;
ELSE
tempEIP := EIP   SignExtend(DEST);IF OperandSize   16
FI;IF tempEIP is not with in code segment limit
THEN #GP(0);ELSE EIP := tempEIP;
FI;
FI;
ELSE
Terminate loop and continue program execution at (R/E)IP;
FI;
None.
Same exceptions as in protected mode.LOOP/LOOPcc—Loop According to ECX CounterINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-61764-Bit Mode Exceptions
#GP(0) If the offset being jumped to is in a non-canonical form.
#UD If the LOCK prefix is used.LSL—Load Segment LimitINSTRUCTION SET REFERENCE, A-L
3-618 Vol. 2ALSL—Load Segment Limit
Loads the unscrambled segment limit from the segment descriptor specified with the second operand (source 
operand) into the first operand (destination operand) an d sets the ZF flag in the EFLAGS register. The source 
operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. The destination oper and is a general-purpose register.
ware can compare the segment limit with the offset of a pointer. 
The segment limit is a 20-bit value contained in bytes 0 an d 1 and in the first 4 bits of byte 6 of the segment 
descriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination 
operand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the 
granularity flag is set to 1), the LSL instruction will transl ate the page granular limit (page limit) into a byte limit 
before loading it into the destination op erand. The translation is performed by sh ifting the 20-bit “raw” limit left 12 
bits and filling the low-order 12 bits with 1s.
When the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size 
is 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are truncated and only the low-order 16 bits are loaded into the destination operand.
This instruction performs the following checks before it  loads the segment limit into  the destination register: 
accessed
(can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the 
following table. 
•If the segment is not a conforming code segment, the instruction checks that the specified segment descriptor 
is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of 
the segment selector).
value is loaded in the destination operand.Opcode Instruction Op/ 
En64-Bit 
0F 03 /r LSL r16, r16/m16 RM Valid Valid Load: r16 := segment limit, selector r16/m16.
0F 03 /r LSL r32, r32/m161
NOTES:
1. For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored.RM Valid Valid Load: r32 := segm ent limit, selector r32/m16.

En64-Bit 
NOTES:
REX.W + 0F 03 /r LSL r64, r32/m161RM Valid Valid Load: r64 := segm ent limit, selector r32/m16
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ALSL—Load Segment LimitINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-619Operation
IF SRC(Offset) > descriptor table limit
THEN ZF := 0; FI;
IF SegmentDescriptor(Type) ≠ conforming co de segment
and (CPL > DPL) OR (RPL > DPL)
or Segment type is no t valid for instruction
THEN
ZF := 0;
ELSE
temp := SegmentLimit([SRC]);IF (SegmentDescriptor(G) = 1)
THEN temp := (temp << 12) OR 00000FFFH;
= 32 
THEN DEST := temp; FI;
ELSE IF OperandSize = 64 (* REX.W used *)
THEN DEST := temp(* Zero-extended *); FI;
DEST := temp AND FFFFH;
FI;
FI;
The ZF flag is set to 1 if the segment limit is  loaded successfully; otherwise, it is set to 0.Table 3-56.  Segment and Gate Descriptor Types
2 LDT Yes LDT1Yes
4 16-bit call gate No Reserved No
5 16-bit/32-bit task gate No Reserved No
9 Available 32-bit TSS Yes 64-bit TSS1Yes
B Busy 32-bit TSS Yes Busy 64-bit TSS1Yes
C 32-bit call gate No 64-bit call gate No
F 32-bit trap gate No 64-bit trap gate No
NOTES:
1. In this case, the descriptor comprises 16 bytes; bits 12:8 of the upper 4 bytes must be 0.LSL—Load Segment LimitINSTRUCTION SET REFERENCE, A-L
3-620 Vol. 2AProtected Mode Exceptions
selector.
#UD The LSL instruction cannot be executed in real-address mode.
#UD The LSL instruction cannot be executed in virtual-8086 mode.
form.
#UD If the LOCK prefix is used.LTR—Load Task RegisterINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-621LTR—Load Task Register
Loads the source operand into the segment selector fiel d of the task register. The source operand (a general-
purpose register or a memory location) contains a segment selector that points to a task state segment (TSS). After the segment selector is loaded in the task register , the processor uses the segment selector to locate the 
segment descriptor for the TSS in the global descriptor ta ble (GDT). It then loads the segment limit and base 
address for the TSS from the segment descriptor into the task  register. The task pointed to by the task register is 
marked busy, but a switch to the task does not occur.
The LTR instruction is provided for use in operating-system software; it should not be used in application programs. 
It can only be executed in protected mo de when the CPL is 0. It is commonly used in initialization code to establish 
the first task to be executed.
The operand-size attribute has no effect on this instruction. 
In 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the 
64-bit base.
Operation
IF SRC is a NULL selector
IF SRC(Offset) > descriptor table limit OR IF SRC(type) ≠ global
IF segment descriptor is not for an available TSS 
IF segment descript or is not present 
TSSsegmentDescriptor(busy) := 1; 
(* Locked read-modify-write operation on the entire descriptor when setting busy flag *)
TaskRegister(SegmentSelector) := SRC;
TaskRegister(SegmentDescriptor) := TSSSegmentDescriptor;
En64-Bit 
0F 00 /3 LTR r/m16 M Valid Valid Lo ad r/m16 into task register.
M ModRM:r/m (r) N/A N/A N/ALTR—Load Task RegisterINSTRUCTION SET REFERENCE, A-L
3-622 Vol. 2AProtected Mode Exceptions
If the source operand contains a NULL segment selector.
selector.
#GP(selector) If the source selector points to a segment th at is not a TSS or to one for a task that is already 
busy.
If the selector points to LDT or is beyond the GDT limit.
#NP(selector) If the TSS descriptor is marked not present.
#UD The LTR instruction is not recognized in real-address mode.
#UD  The LTR instruction is not recognized in virtual-8086 mode.
Same exceptions as in protected mode, as well as the following:#GP(selector) If the source selector points to a 16-bit TSS.
If the memory address is in a non-canonical form.If the source operand contains a NULL segment selector.
#GP(selector) If the source selector points to a segment that is not a TSS, to a 16-bit TSS, or to a TSS for a 
task that is already busy.
If the descriptor type of the upper 8-byte of the 16-byte descriptor is non-zero.
#NP(selector) If the TSS descriptor is marked not present.#PF(fault-code) If a page fault occurs.
#UD If the LOCK prefix is used.LZCNT—Count the Number of Leading Zero BitsINSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-623LZCNT—Count the Number of Leading Zero Bits
Counts the number of leading most significant zero bits in  a source operand (second operand) returning the result 
into a destination (first operand). 
LZCNT differs from BSR. For example,  LZCNT will produce the operand size when the input operand is zero. It 
should be noted that on processors that do not support LZ CNT, the instruction byte encoding is executed as BSR. 
In 64-bit mode 64-bit operand size requires REX.W=1. 
Operation
temp := OperandSize - 1
DEST := 0WHILE (temp >= 0) AND (Bit(SRC, temp) = 0)DO
temp := temp - 1DEST := DEST+ 1
OD
IF DEST = OperandSize
CF := 1
ELSE
CF := 0
FI
IF DEST = 0
ZF := 1
ELSE
ZF := 0
FI
ZF flag is set to 1 in case of zero output (most significant bit of the source is set), and to 0 otherwise, CF flag is set 
to 1 if input was zero and cleared otherwise. OF, SF, PF, and AF flags are undefined.
LZCNT unsigned __int32 _lzcnt _u32(unsigned __int32 src);
LZCNT unsigned __int64 _lzcnt _u64(unsigned __int64 src);Opcode/Instruction Op/ 
En64/32-
F3 0F BD /r
LZCNT r16, r/m16RM V/V LZCNT Count the number of leading zero  bits in r/m16, re turn result in r16.
F3 0F BD /r
LZCNT r32, r/m32RM V/V LZCNT Count the number of leading zero  bits in r/m32, re turn result in r32.
F3 REX.W 0F BD /r
LZCNT r64, r/m64RM V/N.E. LZCNT Count the number of leading ze ro bits in r/m64, return result in r64.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ALZCNT—Count the Number of Leading Zero BitsINSTRUCTION SET REFERENCE, A-L
3-624 Vol. 2AProtected Mode Exceptions
selector.
#PF (fault-code) For a page fault.#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the 
#UD If LOCK prefix is used.

selector.
#SS(0) For an illegal address in the SS segment.#PF (fault-code) For a page fault.
#UD If LOCK prefix is used.Vol. 2B 4-1CHAPTER 4
INSTRUCTION SET REFERENCE, M-U
4.1 IMM8 CONTROL BYTE OPERATIO N FOR PCMPESTRI / PCMPESTRM / 
PCMPISTRI / PCMPISTRM
The notations introduced in this section are referenced in the reference pages of PCMPESTRI, PCMPESTRM, PCMP-
ISTRI, PCMPISTRM. The operation of the immediate control byte is common to these four string text processing 
instructions of SSE4.2. This section describes the common operations. 
4.1.1 General Description
The operation of PCMPESTRI, PCMPESTRM, PCMPISTRI, PC MPISTRM is defined by the combination of the respec-
tive opcode and the interpretation of an immediate co ntrol byte that is part of the instruction encoding.
The opcode controls the relationship of input bytes/words to each other (determines whether the inputs terminated 
strings or whether lengths are expressed explicitly) as well as the desired output (index or mask).
The imm8 control byte for PCMPESTRM/PCMPESTRI/PCMP ISTRM/PCMPISTRI encodes a significant amount of 
programmable control over the functionality of those instructions. Some functionality is unique to each instruction 
while some is common across some or all of the four instructions. This section describes functionality which is 
common across the four instructions.
The arithmetic flags (ZF, CF, SF, OF, AF, PF) are set as a result of these instructions. However, the meanings of the 
flags have been overloaded from thei r typical meanings in order to provid e additional information regarding the 
relationships of the two inputs.
PCMPxSTRx instructions perform arithmetic comparisons be tween all possible pairs of bytes or words, one from 
each packed input source operand. The boolean results of those comparisons are then aggregated in order to 
produce meaningful results. The imm8 control byte is used to affect the interpretation of individual input elements 
as well as control the arithmetic comparison s used and the specific aggregation scheme. 
Specifically, the imm8 Control Byte consists of bit fields that control the following attributes:
•Source data format  — Byte/word data element granularity, signed or unsigned elements.
•Aggregation operation — Encodes the mode of per-element compar ison operation and the aggregation of 
per-element comparisons into an intermediate result.
•Polarity — Specifies intermediate processing to be  performed on the intermediate result.
•Output selection — Specifies final operation to produce the output (depending on index or mask) from the 
intermediate result.INSTRUCTION SET REFERENCE, M-U
4-2 Vol. 2B4.1.2 Source Data Format
If the imm8 control byte has bit[0] cleared, each source contains 16 packed bytes. If the bit is set each source 
contains 8 packed words. If the imm8 control byte has bit[ 1] cleared, each input contains unsigned data. If the bit 
is set each source contains signed data. 
4.1.3 Aggregation Operation
All 256 (64) possible comparisons are always performed. The individual Boolean results of those comparisons are 
referred by “BoolRes[ Reg/Mem element index, Reg element index ].” Comparisons evaluating to “True” are repre-
sented with a 1, False with a 0 (positive logic). The initia l results are then aggregated into a 16-bit (8-bit) interme-
diate result (IntRes1) using one of the modes described in  the table below, as determined by imm8 control byte 
bits[3:2]. Table 4-1.  Source Data Format
Imm8[1:0] Meaning Description
00b Unsigned bytes Both 128-bit sources are treated as packed, unsigned bytes.01b Unsigned words Both 128-bit sources are treated as packed, unsigned words.
10b Signed bytes Both 128-bit sources are treated as packed, signed bytes.
11b Signed words Both 128-bit sources are treated as packed, signed words.
Table 4-2.  Aggregation Operation
Imm8[3:2] Mod eC o m p a r i s o n
00b Equal any The arithmetic comparison is “equal.”01b Ranges Arithmetic comparison is “g reater than or equal” between even indexed bytes/words of reg and 
each byte/word of reg/mem. 
Arithmetic comparison is “less than or equal” between odd indexed bytes/words of reg and each 
byte/word of reg/mem.
(reg/mem[m] >= reg[n] for n = even, reg/mem[m] <= reg[n] for n = odd) 
10b Equal each The arithmetic comparison is “equal.”
11b Equal ordered The arithmetic comparison is “equal.”INSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-3See Section 4.1.6 for a description of the overrideIfDataInvalid() function used in Table 4-3.
4.1.4 Polarity
IntRes1 may then be further modified by performing a 1’ s complement, according to the value of the imm8 control 
byte bit[4]. Optionally, a mask may be used such that on ly those IntRes1 bits which correspond to “valid” reg/mem 
input elements are complemented (note that the definition  of a valid input element is dependant on the specific 
opcode and is defined in each opcode’s description). The re sult of the possible negation is referred to as IntRes2.Table 4-3.  Aggregation Operation 
Mode Pseudocode
Equal any
(find characters from a set)UpperBound = i mm8[0] ? 7 : 15;
IntRes1 = 0;
For j = 0 to UpperBound, j++
For i = 0 to UpperBound, i++
IntRes1[j] OR= overrideIf DataInvalid(BoolRes[j,i])
Ranges
(find characters from ranges)UpperBound = i mm8[0] ? 7 : 15;
For i = 0 to UpperBound, i+=2
IntRes1[j] OR= (overrideIfDat aInvalid(BoolRes[j,i]) AND  
overrideIfDataInvalid(BoolRes[j,i+1]))
Equal each
(string compare)UpperBound = i mm8[0] ? 7 : 15;
IntRes1 = 0;For i = 0 to UpperBound, i++
IntRes1[i] = overrideIfDa taInvalid(BoolRes[i,i])
Equal ordered
(substring search)UpperBound = imm8[0] ? 7 :15;
IntRes1 = imm8[0] ? FFH : FFFFH
For i = 0 to UpperBound-j, k=j to UpperBound, k++, i++
IntRes1[j] AND= overrideIf DataInvalid(BoolRes[k,i])
Table 4-4.  Polarity
Imm8[5:4] Operation Description
00b Positive Polarity (+) IntRes2 = IntRes1
01b Negative Polarity (-) I ntRes2 = -1 XOR IntRes1
10b Masked (+) IntRes2 = IntRes1
11b Masked (-) IntRes2[i] = IntRes1[i] if reg/mem[i] invalid, else = ~IntRes1[i]INSTRUCTION SET REFERENCE, M-U
4-4 Vol. 2B4.1.5 Output Selection
For PCMPESTRI/PCMPISTRI, the imm8 contro l byte bit[6] is used to determine if  the index is of the least significant 
or most significant bit of IntRes2.
Specifically for PCMPESTRM/PCMPISTRM, th e imm8 control byte bit[6] is used to  determine if the mask is a 16 (8) 
bit mask or a 128 bit byte/word mask.
4.1.6 Valid/Invalid Override of Comparisons
PCMPxSTRx instructions allow for the possibility that an end-of-string (EOS) situation may occur within the 128-bit packed data value (see the instruction descriptions below fo r details). Any data elements on either source that are 
determined to be past the EOS are considered to be invali d, and the treatment of invalid data within a comparison 
pair varies depending on the aggr egation function being performed.
In general, the individual comparison result for each elemen t pair BoolRes[i.j] can be forced true or false if one or 
more elements in the pair are invalid. See Table 4-7.Table 4-5.  Output Selection
Imm8[6] Operation Description
0b Least significant index The index returned to ECX is of the leas t significant set bit in IntRes2.
1b Most significant index The index returned to EC X is of the most signif icant set bit in IntRes2.
Table 4-6.  Output Selection
0b Bit mask IntRes2 is returned as the mask to the least significant bits of  XMM0 with zero extension to 128 
bits.
1b Byte/word mask IntRes2 is expanded into a byte/word mask (based on imm8[1]) and placed in XMM0. The expansion 
is performed by replicating each bit into all of the bits of the byte/word of the same index.
Table 4-7.  Comparison Result fo r Each Element Pair BoolRes[i.j]
xmm1 
byte/ wordxmm2/ m128 
byte/wordImm8[3:2] = 00b
(equal any)Imm8[3:2] = 01b 
(ranges)Imm8[3:2] = 10b 
(equal each)Imm8[3:2] = 11b 
(equal ordered)
Invalid Invalid Force false Force  false Force true Force true
Invalid Valid Force false Force false Force false Force true
Valid Invalid Force false Force false Force false Force false
Valid Valid Do not force Do not force Do not force Do not forceINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-54.1.7 Summary of Im8 Control byte
Table 4-8.  Summary of Imm8 Control Byte 
Imm8 Description

bits.
xmm1 
-------0b 128-bit sources trea ted as 16 packed bytes.
-------1b 128-bit sources tr eated as 8 packed words.
------0-b Packed bytes/words are unsigned.
------1-b Packed bytes/words are signed.----00--b Mode is equal any.
----01--b Mode is ranges.
----10--b Mode is equal each.----11--b Mode is equal ordered.---0----b IntRes1 is unmodified.
---1----b IntRes1 is nega ted (1’s complement).
--0-----b Negation of IntRes1 is for all 16 (8) bits.
--1-----b Negation of IntRes1 is masked by reg/mem validity.
-0------b Index of the least sign ificant, set, bit is used (regardless of  corresponding  input element validity). 
IntRes2 is returned in leas t significant bits of XMM0.
-1------b Index of the most sign ificant, set, bit is used (regardless of corresponding inpu t element validity).
Each bit of IntRes2 is expanded to byte/word.
0-------b This bit currently has no  defined effect , should be 0.
1-------b This bit currently has no  defined effect , should be 0.INSTRUCTION SET REFERENCE, M-U
4-6 Vol. 2B4.1.8 Diagram Comparison and Aggregation Process
4.2 COMMON TRANSFORMATION AND PRIMITIVE FUNCTI ONS FOR SHA1XXX 
AND SHA256XXX
The following primitive functions and transformations are used in the algorithmic descriptions of SHA1 and SHA256 
instruction extensions SHA1NEXTE, SHA1RNDS4, SHA1MSG1, SHA1MSG2, SHA256RNDS4, SHA256MSG1, and SHA256MSG2. The operands of these primitives and tr ansformation are generally 32-bit DWORD integers.
•f0(): A bit oriented logical operation that derives a new dword from three SHA1 state variables (dword). This 
function is used in SHA1 round 1 to 20 processing.
f0(B,C,D) := (B AND C) XOR ((NOT(B) AND D)
•f1(): A bit oriented logical operation that derives a new dword from three SHA1 state variables (dword). This 
function is used in SHA1 round 21 to 40 processing.
f1(B,C,D) := B XOR C XOR D
•f2(): A bit oriented logical operation that derives a new dword from three SHA1 state variables (dword). This 
function is used in SHA1 round 41 to 60 processing.
f2(B,C,D) := (B AND C) XOR (B AND D) XOR (C AND D)
•f3(): A bit oriented logical operation that derives a new dword from three SHA1 state variables (dword). This 
function is used in SHA1 round 61 to 80 processing. It is the same as f1().
f3(B,C,D) := B XOR C XOR D
•Ch(): A bit oriented logical operation that derives a new dword from three SHA256 state variables (dword).Figure 4-1.  Operation of PCMPSTRx and PCMPESTRx
Vol. 2B 4-7Ch(E,F,G) := (E AND F) XOR ((NOT E) AND G)
•Maj(): A bit oriented logical operation that derives a new dword from three SHA256 state variables (dword).
Maj(A,B,C) := (A AND B) XOR (A AND C) XOR (B AND C)
ROR is rotate right operation
 (A ROR N) := A[N-1:0] || A[Width-1:N]
ROL is rotate left operation
 (A ROL N) := A ROR (Width-N)
SHR is the right shift operation
(A SHR N) := ZEROES[N-1:0] || A[Width-1:N]
• Σ0( ): A bit oriented logical and rotational transfor mation performed on a dword SHA256 state variable.
Σ0(A) := (A ROR 2) XOR (A ROR 13) XOR (A ROR 22) 
• Σ1( ): A bit oriented logical and rotational transfor mation performed on a dword SHA256 state variable.
Σ1(E) := (E ROR 6) XOR (E ROR 11) XOR (E ROR 25) 
• σ0( ): A bit oriented logical and rotational transformati on performed on a SHA256 message dword used in the 
message scheduling.
σ0(W) := (W ROR 7) XOR (W ROR 18) XOR (W SHR 3) 
• σ1( ): A bit oriented logical and rotational transformati on performed on a SHA256 message dword used in the 
σ1(W) := (W ROR 17) XOR (W ROR 19) XOR (W SHR 10) 
•Ki: SHA1 Constants dependent on immediate i.
K0 = 0x5A827999K1 = 0x6ED9EBA1K2 = 0X8F1BBCDCK3 = 0xCA62C1D6
4.3 INSTRUCTIONS (M-U)
Chapter 4 continues an alphabetical discussion of Intel® 64 and IA-32 instructions (M-U). See also: Chapter 3, 
“Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2A; Chapter 5, “Instruction Se t Reference, V‚” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2C; and Chapter 6, “Instruc tion Set Reference, W-Z‚” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 2D.MASKMOVDQU—Store Selected Bytes of Double QuadwordINSTRUCTION SET REFERENCE, M-U
4-8 Vol. 2BMASKMOVDQU—Store Selected Bytes of Double Quadword
Stores selected bytes from the source operand (first op erand) into an 128-bit memory location. The mask operand 
(second operand) selects which bytes from the source op erand are written to memory. The source and mask oper-
ands are XMM registers. The memory lo cation specified by the effective addr ess in the DI/EDI/RDI register (the 
default segment register is DS, but this may be overridden  with a segment-override prefix). The memory location 
does not need to be aligned on a natural boundary. (The  size of the store address depends on the address-size 
attribute.)
The most significant bit in each byte of the mask operan d determines whether the corresp onding byte in the source 
operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write. 
The MASKMOVDQU instruction generates a non-temporal hint to the processor to minimize cache pollution. The 
non-temporal hint is implemented by using a write comb ining (WC) memory type protocol (see “Caching of 
Temporal vs. Non-Temporal Data” in Chapter 10, of the Intel® 64 and IA-32 Architectu res Software Developer’s 
Manual, Volume 1). Because the WC protocol uses a weak ly-ordered memory consistency model, a fencing opera-
tion implemented with the SFENCE or MFENCE instruct ion should be used in conjunction with MASKMOVDQU 
instructions if multiple processors might use different memory types to read/write the destination memory loca-tions.
Behavior with a mask of all 0s is as follows:
•No data will be written to memory. 
•Signaling of breakpoints (code or data) is not guarante ed; different processor implementations may signal or 
not signal these breakpoints.
•Exceptions associated with addressing memory and page faults may still be signaled (implementation 
dependent).
•If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these 
memory types is not guaranteed (that is, is reserved) and is implementation-specific. 
The MASKMOVDQU instruction can be used  to improve performance of algorithms that need to merge data on a 
byte-by-byte basis. MASKMOVDQU should not cause a read  for ownership; doing so generates unnecessary band-
width since data is to be written directly using the by te-mask without allocating old data prior to the store. 
Note: In VEX-encoded versions, VEX. vvvv is reserved and must be 1111b otherwise instructions will #UD.
If VMASKMOVDQU is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will 
cause an #UD exception.Opcode/
ModeCPUID 
Feature 
66 0F F7 /r
MASKMOVDQU xmm1, xmm2RM V/V SSE2 Selectively write bytes from xmm1 to memory location 
using the byte mask in xmm2. The default memory location 
is specified by DS:DI/EDI/RDI.
VEX.128.66.0F.WIG F7 /r
VMASKMOVDQU xmm1, xmm2RM V/V AVX Selectively write bytes fr om xmm1 to memory location 
using the byte mask in xmm2. The default memory location is specified by DS:DI/EDI/RDI.
1.ModRM.MOD = 011B requiredMASKMOVDQU—Store Selected Bytes of Double QuadwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-9Operation
IF (MASK[7] = 1)
THEN DEST[DI/EDI] := SRC[7:0] ELSE (* Memory location  unchanged *); FI;
IF (MASK[15]  = 1) 
THEN DEST[DI/EDI +1] := SRC[15:8] ELSE (* Memo ry location unchanged *); FI;
(* Repeat operation for 3rd throug h 14th bytes in source operand *)
IF (MASK[127] = 1) 
THEN DEST[DI/EDI +15] := SRC[127:120] ELSE (* Memory location unchanged *); FI;
void _mm_maskmoveu_si128(__m128i d, __m128i n, char * p)
#UD If VEX.L= 1
If VEX.vvvv ≠ 1111B.MASKMOVQ—Store Selected Bytes of QuadwordINSTRUCTION SET REFERENCE, M-U
4-10 Vol. 2BMASKMOVQ—Store Selected Bytes of Quadword
Stores selected bytes from the source operand (first op erand) into a 64-bit memory location. The mask operand 
ands are MMX technology registers. The memory location  specified by the effective address in the DI/EDI/RDI 
register (the default segment register is DS, but this may be overridden with a segment-override prefix). The 
memory location does not need to be aligned on a natura l boundary. (The size of the store address depends on the

memory location does not need to be aligned on a natura l boundary. (The size of the store address depends on the 
address-size attribute.)
The MASKMOVQ instruction generates a non-temporal hint to the processor to minimize cache pollution. The non-
temporal hint is implemented by using a write combining (WC) memory type protocol (see “Caching of Temporal 
vs. Non-Temporal Data” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1). Because the WC protocol uses a weakly-order ed memory consistency model, a fencing operation imple-
mented with the SFENCE or MFENCE instruction should be  used in conjunction with MASKMOVQ instructions if 
multiple processors might use different memory type s to read/write the destination memory locations.
This instruction causes a transition from x87 FPU to MMX technology state (that is, the x87 FPU top-of-stack pointer 
is set to 0 and the x87 FPU tag word is set to all 0s [valid]).
The behavior of the MASKMOVQ instruction with a mask of all 0s is as follows:
•Transition from x87 FPU to MM X technology state will occur.
•Signaling of breakpoints (code or data) is not guaranteed (implementation dependent).
The MASKMOVQ instruction can be used to improve performa nce for algorithms that need to merge data on a byte-
by-byte basis. It should not cause a read for ownership;  doing so generates unnecessary bandwidth since data is 
to be written directly using the byte-mask without allocating old data prior to the store. 
In 64-bit mode, the memory address is specified by DS:RDI.
Operation
IF (MASK[15] = 1) 
(* Repeat operation for 3rd through 6th bytes in source operand *)
IF (MASK[63] = 1) 
THEN DEST[DI/EDI +15] := SRC[63:56] ELSE (* Memo ry location unchanged *); FI;Opcode/
En64-Bit 
NP 0F F7 /r
MASKMOVQ mm1, mm2RM Valid Valid Selectively write bytes from mm1 to memory location using 
the byte mask in mm2. The default memory location is 
specified by DS:DI/EDI/RDI.
RM ModRM:reg (r) ModRM:r/m (r) N/A N/AMASKMOVQ—Store Selected Bytes of QuadwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-11Intel C/C ++ Compiler Intrinsic Equivalent
void _mm_maskmove_si64(__m64d, __m64n, char * p)
See Table 23-8, “Exception Conditions for Legacy SIMD/M MX Instructions without FP Exception,” in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 3B.MAXPD—Maximum of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-12 Vol. 2BMAXPD—Maximum of Packed Double Precision Floating-Point Values
Performs a SIMD compare of the packed double precision fl oating-point values in the first source operand and the 
second source operand and returns the maximum value fo r each pair of values to the destination operand. 
If the values being compared are both 0.0s (of either sign), the value in th e second operand (source operand) is 
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that is, a QNaN version of the SNaN is not returned). 
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN 
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source 
operand (from either the first or second operand) be returned, the action of MAXPD can be emulated using a 
sequence of instructions, such as a comparison followed by AND, ANDN, and OR. 
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of 
Mode 
Feature 
66 0F 5F /r
MAXPD xmm1, xmm2/m128A V/V SSE2 Return the maximum double precision floating-point 
values between xmm1 and xmm2/m128. 
VEX.128.66.0F.WIG 5F /r
VMAXPD xmm1, xmm2, xmm3/m128B V/V AVX Return the maximum double precision floating-point 
values between xmm2 and xmm3/m128. 
VEX.256.66.0F.WIG 5F /r
VMAXPD ymm1, ymm2, ymm3/m256B V/V AVX Return the maximum packed double precision floating-
point values between ymm2 and ymm3/m256.
EVEX.128.66.0F.W1 5F /r
VMAXPD xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcstCV / V A V X 5 1 2 V L
AVX512FReturn the maximum packed double precision floating-
point values between xmm2 and xmm3/m128/m64bcst 
and store result in xmm1 subject to writemask k1.
EVEX.256.66.0F.W1 5F /r
VMAXPD ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcstCV / V A V X 5 1 2 V L
point values between ymm2 and ymm3/m256/m64bcst 
and store result in ymm1 subject to writemask k1.
EVEX.512.66.0F.W1 5F /r
VMAXPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{sae}C V/V AVX512F Return the maximum packed double precision floating-
point values between zmm2 and zmm3/m512/m64bcst and store result in zmm1 subject to writemask k1.
CF u l l M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/AMAXPD—Maximum of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-13Operation
MAX(SRC1, SRC2)
{
IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST := SRC2;
ELSE IF (SRC1 = NaN) TH EN DEST := SRC2; FI;
ELSE IF (SRC2 = NaN) TH EN DEST := SRC2; FI;
ELSE IF (SRC1 > SRC2) THEN DEST := SRC1;ELSE DEST := SRC2; 
FI; 
}
VMAXPD (EVEX Encoded Versions)
THEN 
THEN
DEST[i+63:i] := MAX(SRC1[i+63:i], SRC2[63:0])
ELSE 
DEST[i+63:i] := MAX(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE 
THEN *DEST[i+63:i] remains unchanged*ELSE  DEST[i+63:i] := 0 ; zeroing-masking
FI
FI;
VMAXPD (VEX.256 Encoded Version)
DEST[63:0] := MAX(SRC1[63:0], SRC2[63:0])DEST[127:64] := MAX(SRC1 [127:64], SRC2[127:64])
DEST[191:128] := MAX(SRC1[191:128], SRC2[191:128])DEST[255:192] := MAX(SRC1[255:192], SRC2[255:192])DEST[MAXVL-1:256] := 0
VMAXPD (VEX.128 Encoded Version)
MAXPD (128-bit Legacy SSE Version)
DEST[63:0] := MAX(DEST[63:0], SRC[63:0])DEST[127:64] := MAX(DEST[127:64], SRC[127:64])DEST[MAXVL-1:128 ] (Unmodified)MAXPD—Maximum of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-14 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VMAXPD __m512d _mm512_max_pd( __m512d a, __m512d b);
VMAXPD __m512d _mm512_mask_max_pd(__m512d s, __mmask8 k, __m512d a, __m512d b,);
VMAXPD __m512d _mm512_maskz_max_pd( __mmask8 k, __m512d a, __m512d b);VMAXPD __m512d _mm512_max_round_ pd( __m512d a, __m512d b, int);
VMAXPD __m512d _mm512_mask_max_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);VMAXPD __m512d _mm512_maskz_max_round_pd( __mmask8 k, __m512d a, __m512d b, int);

VMAXPD __m256d _mm256_mask_max_pd(__m5256d s, __mmask8 k, __m256d a, __m256d b);VMAXPD __m256d _mm256_maskz_max_pd( __mmask8 k, __m256d a, __m256d b);VMAXPD __m128d _mm_mask_max_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);VMAXPD __m128d _mm_maskz_max_pd( __mmask8 k, __m128d a, __m128d b);VMAXPD __m256d _mm256_max_pd (__m256d a, __m256d b);(V)MAXPD __m128d _mm_max_pd (__m128d a, __m128d b);
Invalid (including QNaN Source Operand), Denormal.
Non-EVEX-encoded instruction, see Table 2-19, “Type 2 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”MAXPS—Maximum of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-15MAXPS—Maximum of Packed Single Precision Floating-Point Values
Performs a SIMD compare of the packed single precision fl oating-point values in the first source operand and the 
second source operand and returns the maximum value for each pair of values to the destination operand. 
If the values being compared are both 0.0s (of either si gn), the value in the second operand (source operand) is 
returned. If a value in the second operand is an SNaN, th en SNaN is forwarded unchanged to the destination (that 
is, a QNaN version of the SNaN is not returned). 
If only one value is a NaN (SNaN or QNaN) for this instru ction, the second operand (source operand), either a NaN 
or a valid floating-point value, is written to the result. If instead of this behavior, it is  required that the NaN source 
operand (from either the first or second operand) be returned, the action of MAXPS can be emulated using a 
sequence of instructions, such as, a comparison followed by AND, ANDN, and OR. 
the corresponding ZMM register destination are zeroed.Opcode/
Mode 
Feature 
NP 0F 5F /r
MAXPS xmm1, xmm2/m128A V/V SSE Return the maximum single precision floating-point values 
between xmm1 and xmm2/mem. 
VEX.128.0F.WIG 5F /r
VMAXPS xmm1, xmm2, 
xmm3/m128B V/V AVX Return the maximum single precision floating-point values 
between xmm2 and xmm3/mem. 
VEX.256.0F.WIG 5F /r
VMAXPS ymm1, ymm2, 
ymm3/m256B V/V AVX Return the maximum single precision floating-point values 
between ymm2 and ymm3/mem.
EVEX.128.0F.W0 5F /r
VMAXPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstC V/V AVX512VL
AVX512FReturn the maximum packed single precision floating-point 
values between xmm2 and xmm3/m128/m32bcst and store result in xmm1 subject to writemask k1.
EVEX.256.0F.W0 5F /r
VMAXPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstC V/V AVX512VL
values between ymm2 and ymm3/m256/m32bcst and store result in ymm1 subject to writemask k1.
EVEX.512.0F.W0 5F /r
VMAXPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst{sae}C V/V AVX512F Return the maximum packed single precision floating-point 
values between zmm2 and zmm3/m512/m32bcst and store 
result in zmm1 subj ect to writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMAXPS—Maximum of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-16 Vol. 2B128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
ZMM register destination are unmodified.
Operation
{
FI; 
}
VMAXPS (EVEX Encoded Versions)
THEN 
THEN
DEST[i+31:i] := MAX(SR C1[i+31:i], SRC2[31:0])
ELSE 
DEST[i+31:i] := MAX(SRC1[i+31:i], SRC2[i+31:i])
FI;
ELSE 
THEN *DEST[i+31:i] remains unchanged*ELSE  DEST[i+31:i] := 0 ; zeroing-masking
FI
FI;
VMAXPS (VEX.256 Encoded Version)
DEST[31:0] := MAX(SRC1[31:0], SRC2[31:0])DEST[63:32] := MAX(SR C1[63:32], SRC2[63:32])
DEST[95:64] := MAX(SR C1[95:64], SRC2[95:64])
DEST[127:96] := MAX(SRC1 [127:96], SRC2[127:96])
DEST[159:128] := MAX(SRC1[159:128], SRC2[159:128])DEST[191:160] := MAX(SRC1[191:160], SRC2[191:160])DEST[223:192] := MAX(SRC1[223:192], SRC2[223:192])DEST[255:224] := MAX(SRC1[255:224], SRC2[255:224])DEST[MAXVL-1:256] := 0
VMAXPS (VEX.128 Encoded Version)
DEST[MAXVL-1:128] := 0MAXPS—Maximum of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-17MAXPS (128-bit Legacy SSE Version)
DEST[31:0] := MAX(DEST[31:0], SRC[31:0])DEST[63:32] := MAX(DEST[63:32], SRC[63:32])DEST[95:64] := MAX(DEST[95:64], SRC[95:64])DEST[127:96] := MAX(DEST[127:96], SRC[127:96])DEST[MAXVL-1:128 ] (Unmodified)
VMAXPS __m512 _mm512_max_ps( __m512 a, __m512 b);
VMAXPS __m512 _mm512_mask_max_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);VMAXPS __m512 _mm512_maskz_max_ps( __mmask16 k, __m512 a, __m512 b);VMAXPS __m512 _mm512_max_round_ps( __m512 a, __m512 b, int);VMAXPS __m512 _mm512_mask_max_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);VMAXPS __m512 _mm512_maskz_max_round_ps(  __mmask16 k, __m512 a, __m512 b, int);
VMAXPS __m256 _mm256_mask_max_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VMAXPS __m256 _mm256_maskz_max_ps( __mmask8 k, __m256 a, __m256 b);VMAXPS __m128 _mm_mask_max_ps(__m128 s,  __mmask8 k, __m128 a, __m128 b);
VMAXPS __m128 _mm_maskz_max_ps( __mmask8 k, __m128 a, __m128 b);
VMAXPS __m256 _mm256_max_ps (__m256 a, __m256 b);MAXPS __m128 _mm_max_ps (__m128 a, __m128 b);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”MAXSD—Return Maximum Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-18 Vol. 2BMAXSD—Return Maximum Scalar Double  Precision Floating-Point Value
Compares the low double precision floating-point values in the first source operand and the second source operand, 
and returns the maximum value to the low quadword of th e destination operand. The second source operand can 
be an XMM register or a 64-bit memory location. The fi rst source and destination operands are XMM registers. 
When the second source operand is a memo ry operand, only 64 bits are accessed. 
If the values being compared are both 0.0s (of either sign ), the value in the second so urce operand is returned. If 
a value in the second source operand is an SNaN, that SN aN is returned unchanged to the destination (that is, a 
QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruct ion, the second source operand, either a NaN or a valid 
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN of either source 
operand be returned, the action of MAXS D can be emulated using a sequence of instructions, such as, a comparison 
followed by AND, ANDN, and OR. 
128-bit Legacy SSE version: The destination and first so urce operand are the same. Bits (MAXVL-1:64) of the 
VEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding 
bits in the first source operand. Bits (MAXVL -1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the 

Software should ensure VMAXSD is encoded with VEX.L= 0. Encoding VMAXSD with VEX.L=1 may encounter unpre-
Operation
{
FI; 
}Opcode/
Mode 
Feature 
F2 0F 5F /r
MAXSD xmm1, xmm2/m64A V/V SSE2 Return the maximum scal ar double precision floating-
point value between xmm2/m64 and xmm1.
VEX.LIG.F2.0F.WIG 5F /r
VMAXSD xmm1, xmm2, xmm3/m64B V/V AVX Return the maximum scalar double precision floating-
point value between xmm3/m64 and xmm2.
EVEX.LLIG.F2.0F.W1 5F /r
VMAXSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}C V/V AVX512F Return the maximum scalar double precision floating-
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMAXSD—Return Maximum Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-19VMAXSD (EVEX Encoded Version)
THEN DEST[63:0] := MAX( SRC1[63:0], SRC2[63:0])
ELSE 
DEST[63:0] := 0
FI;
VMAXSD (VEX.128 Encoded Version)
DEST[63:0] := MAX(SRC1[63:0], SRC2[63:0])DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
MAXSD (128-bit Legacy SSE Version)
DEST[63:0] := MAX(DEST[63:0], SRC[63:0])DEST[MAXVL-1:64] (Unmodified)
VMAXSD __m128d _mm_max_round_sd( __m128d a, __m128d b, int);VMAXSD __m128d _mm_mask_max_round_sd(__m128d s,  __mmask8 k, __m128d a, __m128d b, int);
VMAXSD __m128d _mm_maskz_max_round_sd( __mm ask8 k, __m128d a, __m128d b, int);
MAXSD __m128d _mm_max_sd(__m128d a, __m128d b)
Invalid (Including QNaN Source Operand), Denormal.
Non-EVEX-encoded instruction, see Table 2-20, “Type 3 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”MAXSS—Return Maximum Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-20 Vol. 2BMAXSS—Return Maximum Scalar Single  Precision Floating-Point Value
Compares the low single precision floating-point values in  the first source operand and the second source operand, 
and returns the maximum value to the low doubleword of the destination operand. 
floating-point value, is written to the result. If instead of th is behavior, it is required that the NaN from either source 
operand be returned, the action of MAXSS can be emulated using a sequence of instructions, such as, a comparison 
The second source operand can be an XMM register or a 32-bit memory location. The first source and destination 
128-bit Legacy SSE version: The destination and first sour ce operand are the same. Bits (MAXVL:32) of the corre-
sponding destination register remain unchanged.
VEX.128 and EVEX encoded version: The first source op erand is an xmm register encoded by VEX.vvvv. Bits 
(127:32) of the XMM register destination are copied from  corresponding bits in the first source operand. Bits 
(MAXVL:128) of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the 
Software should ensure VMAXSS is encoded with VEX.L=0. Encoding VMAXSS with VEX.L=1 may encounter unpre-
Operation
{
FI; Opcode/
Mode 
Feature 
F3 0F 5F /r
MAXSS xmm1, xmm2/m32A V/V SSE Return the maximum scalar single precision floating-point 
value between xmm2/m32 and xmm1.
VEX.LIG.F3.0F.WIG 5F /r
VMAXSS xmm1, xmm2, xmm3/m32B V/V AVX Return the maximum scalar single precision floating-point 
value between xmm3/m32 and xmm2.
EVEX.LLIG.F3.0F.W0 5F /r
VMAXSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae}C V/V AVX512F Return the maximum scalar single precision floating-point 
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMAXSS—Return Maximum Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-21}
VMAXSS (EVEX Encoded Version)
THEN DEST[31:0] := MAX( SRC1[31:0], SRC2[31:0])
ELSE 
FI;
VMAXSS (VEX.128 Encoded Version)
DEST[31:0] := MAX(SRC1[31:0], SRC2[31:0])DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
MAXSS (128-bit Legacy SSE Version)
DEST[31:0] := MAX(DEST[31:0], SRC[31:0])DEST[MAXVL-1:32] (Unmodified)
VMAXSS __m128 _mm_max_round_ss ( __m128 a, __m128 b, int);
VMAXSS __m128 _mm_mask_max_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMAXSS __m128 _mm_maskz_max_round_ss( __mmask8 k, __m128 a, __m128 b, int);MAXSS __m128 _mm_max_ss(__m128 a, __m128 b)
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”MFENCE—Memory FenceINSTRUCTION SET REFERENCE, M-U
4-22 Vol. 2BMFENCE—Memory Fence
Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior 
the MFENCE instruction. This serializing operation guarante es that every load and store instruction that precedes 
the MFENCE instruction in program order becomes globally vi sible before any load or store instruction that follows 
the MFENCE instruction.1 The MFENCE instruction is ordered with respect to all load and store instructions, other 
MFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID 
instruction). MFENCE does not serialize the instruction stream.
Weakly ordered memory types can be used to achieve hi gher processor performance through such techniques as 
out-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of 
data recognizes or knows that the data is weakly orde red varies among applications  and may be unknown to the 
producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store 
ordering between routines that produce weakly-ordered results and routines that consume that data.
Processors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC, and 
WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. Thus, it 
is not ordered with respect to executions of the MFENCE instruction; data can be brought into the caches specula-tively just before, during, or after the execution of an MFENCE instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.Specification of the instruction's opcode above indicates a ModR/M byte of F0. For this instruction, the processor 
ignores the r/m field of the ModR/M by te. Thus, MFENCE is encoded by any op code of the form 0F AE Fx, where x 
is in the range 0-7.
Operation
Wait_On_Following_Loads_And_St ores_Until(preceding_loads_a nd_stores_globally_visible);
void _mm_mfence(void)
Mode 
Feature 
NP 0F AE F0
MFENCEZO V/V SSE2 Serializes load and store operations.

Operation
Mode 
Feature 
NP 0F AE F0
1. A load instruction is considered  to become globally visible when  the value to be loaded into its destination register is dete rmined.MINPD—Minimum of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-23MINPD—Minimum of Packed Double Precision Floating-Point Values
second source operand and returns the minimum value for each pair of values to the destination operand. 
operand (from either the first or second operand) be returned, the action of MINPD can be emulated using a 
Mode 
Feature 
66 0F 5D /r
MINPD xmm1, xmm2/m128A V/V SSE2 Return the minimum double precision floating-point values 
between xmm1 and xmm2/mem 
VEX.128.66.0F.WIG 5D /r
VMINPD xmm1, xmm2, 
xmm3/m128B V/V AVX Return the minimum double precision floating-point values 
VEX.256.66.0F.WIG 5D /r
VMINPD ymm1, ymm2, 
ymm3/m256B V/V AVX Return the minimum packed double precision floating-point 
values between ymm2 and ymm3/mem.
EVEX.128.66.0F.W1 5D /r
VMINPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstC V/V AVX512VL
AVX512FReturn the minimum packed double precision floating-point 
values between xmm2 and xmm3/m128/m64bcst and store result in xmm1 subject to writemask k1.
EVEX.256.66.0F.W1 5D /r
VMINPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstC V/V AVX512VL
values between ymm2 and ymm3/m256/m64bcst and store result in ymm1 subject to writemask k1.
EVEX.512.66.0F.W1 5D /r
VMINPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst{sae}C V/V AVX512F Return the minimum packed double precision floating-point 
values between zmm2 and zmm3/m512/m64bcst and store 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMINPD—Minimum of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-24 Vol. 2B128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
Operation
MIN(SRC1, SRC2)
{
ELSE IF (SRC1 < SRC2) THEN DEST := SRC1;ELSE DEST := SRC2; 
FI; 
}
VMINPD (EVEX Encoded Version)
THEN 
THEN
DEST[i+63:i] := MIN(SRC1[i+63:i], SRC2[63:0])
ELSE 
DEST[i+63:i] := MIN(SRC1 [i+63:i], SRC2[i+63:i])
FI;
ELSE 
FI
FI;
VMINPD (VEX.256 Encoded Version)
DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])DEST[127:64] := MIN(SRC1[127:64], SRC2[127:64])DEST[191:128] := MIN(SRC1[191:128], SRC2[191:128])DEST[255:192] := MIN(SRC1[255:192], SRC2[255:192])
VMINPD (VEX.128 Encoded Version)
DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])DEST[127:64] := MIN(SRC1[127:64], SRC2[127:64])DEST[MAXVL-1:128] := 0
MINPD (128-bit Legacy SSE Version)
DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])DEST[127:64] := MIN(SRC1[127:64], SRC2[127:64])DEST[MAXVL-1:128] (Unmodified)MINPD—Minimum of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-25Intel C/C++ Compiler Intrinsic Equivalent
VMINPD __m512d _mm512_min_pd( __m512d a, __m512d b);
VMINPD __m512d _mm512_mask_min_pd(__m512 d s, __mmask8 k, __m512d a, __m512d b);
VMINPD __m512d _mm512_maskz_min_pd( __mmask8 k, __m512d a, __m512d b);VMINPD __m512d _mm512_min_round_pd( __m512d a, __m512d b, int);VMINPD __m512d _mm512_mask_min_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VMINPD __m512d _mm512_maskz_min_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VMINPD __m256d _mm256_mask_min_pd(__m256 d s, __mmask8 k, __m256d a, __m256d b);
VMINPD __m256d _mm256_maskz_min_pd( __mmask8 k, __m256d a, __m256d b);VMINPD __m128d _mm_mask_min_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VMINPD __m128d _mm_maskz_min_pd( __mmask8 k, __m128d a, __m128d b);VMINPD __m256d _mm256_min_pd (__m256d a, __m256d b);MINPD __m128d _mm_min_pd (__m128d a, __m128d b);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”MINPS—Minimum of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-26 Vol. 2BMINPS—Minimum of Packed Single Precision Floating-Point Values
second source operand and returns the minimum value fo r each pair of values to the destination operand. 
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that 
operand (from either the first or second operand) be returned, the action of MINPS can be emulated using a 
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.Opcode/
Mode 
Feature 
NP 0F 5D /r
MINPS xmm1, xmm2/m128A V/V SSE Return the minimum single precision floating-point values 
VEX.128.0F.WIG 5D /r
VMINPS xmm1, xmm2, 
xmm3/m128B V/V AVX Return the minimum single precision floating-point values 
between xmm2 and xmm3/mem.
VEX.256.0F.WIG 5D /r
VMINPS ymm1, ymm2, 
ymm3/m256B V/V AVX Return the minimum single double precision floating-point

Mode 
Feature 
NP 0F 5D /r
ymm3/m256B V/V AVX Return the minimum single double precision floating-point 
EVEX.128.0F.W0 5D /r
VMINPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstC V/V AVX512VL
AVX512FReturn the minimum packed single precision floating-point 
EVEX.256.0F.W0 5D /r
VMINPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstC V/V AVX512VL
EVEX.512.0F.W0 5D /r
VMINPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst{sae}C V/V AVX512F Return the minimum packed single precision floating-point 
result in zmm1 subject to writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMINPS—Minimum of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-27128-bit Legacy SSE version: The second source can be an  XMM register or an 128-bi t memory location. The desti-
Operation
{
FI; 
}
VMINPS (EVEX Encoded Version)
THEN 
THEN
DEST[i+31:i] := MIN(SR C1[i+31:i], SRC2[31:0])
ELSE 
DEST[i+31:i] := MIN(SRC1[i+31:i], SRC2[i+31:i])
FI;ELSE IF *merging-masking* ; merging-masking
FI
FI;
VMINPS (VEX.256 Encoded Version)
DEST[31:0] := MIN(SRC1[31:0], SRC2[31:0])DEST[63:32] := MIN(SRC1[63:32], SRC2[63:32])DEST[95:64] := MIN(SRC1[95:64], SRC2[95:64])DEST[127:96] := MIN(SRC1[127:96], SRC2[127:96])DEST[159:128] := MIN(SRC1[159:128], SRC2[159:128])DEST[191:160] := MIN(SRC1[191:160], SRC2[191:160])DEST[223:192] := MIN(SRC1[223:192], SRC2[223:192])DEST[255:224] := MIN(SRC1[255:224], SRC2[255:224])
VMINPS (VEX.128 Encoded Version)
DEST[31:0] := MIN(SRC1[31:0], SRC2[31:0])DEST[63:32] := MIN(SRC1[63:32], SRC2[63:32])DEST[95:64] := MIN(SRC1[95:64], SRC2[95:64])DEST[127:96] := MIN(SRC1[127:96], SRC2[127:96])DEST[MAXVL-1:128] := 0MINPS—Minimum of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-28 Vol. 2BMINPS (128-bit Legacy SSE Version)
DEST[31:0] := MIN(SRC1[31:0], SRC2[31:0])DEST[63:32] := MIN(SRC1[63:32], SRC2[63:32])DEST[95:64] := MIN(SRC1[95:64], SRC2[95:64])DEST[127:96] := MIN(SRC1[127:96], SRC2[127:96])DEST[MAXVL-1:128] (Unmodified)
VMINPS __m512 _mm512_min_ps( __m512 a, __m512 b);VMINPS __m512 _mm512_mask_min_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);VMINPS __m512 _mm512_maskz_min_ps( __mmask16 k, __m512 a, __m512 b);VMINPS __m512 _mm512_min_round_ps( __m512 a, __m512 b, int);VMINPS __m512 _mm512_mask_min_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VMINPS __m512 _mm512_maskz_min_round_ps( __mmask16 k, __m512 a, __m512 b, int);
VMINPS __m256 _mm256_mask_min_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);VMINPS __m256 _mm256_maskz_min_ps( __mmask8 k, __m256 a, __m25 b);VMINPS __m128 _mm_mask_min_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMINPS __m128 _mm_maskz_min_ps( __mmask8 k, __m128 a, __m128 b);
VMINPS __m256 _mm256_min_ps (__m256 a, __m256 b);MINPS __m128 _mm_min_ps (__m128 a, __m128 b);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”MINSD—Return Minimum Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-29MINSD—Return Minimum Scalar Double  Precision Floating-Point Value
Compares the low double precision floating-point values  in the first source operand and the second source 
operand, and returns the minimum value to the low quad word of the destination operand. When the source 
operand is a memory operand, only the 64 bits are accessed. 
If the values being compared are both 0.0s (of either sign ), the value in the second source operand is returned. If 
a value in the second source operand is an SNaN, then SN aN is returned unchanged to the destination (that is, a 
floating-point value, is written to the result. If instead of  this behavior, it is required that the NaN source operand 
(from either the first or second source) be returned, th e action of MINSD can be emulated using a sequence of 
instructions, such as, a comparison followed by AND, ANDN, and OR. 
bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.
Software should ensure VMINSD is encoded with VEX.L= 0. Encoding VMINSD with VEX.L=1 may encounter unpre-
Operation
{
Mode 
Feature 
F2 0F 5D /r
MINSD xmm1, xmm2/m64A V/V SSE2 Return the minimum scalar double precision floating-point 
value between xmm2/m64 and xmm1.
VEX.LIG.F2.0F.WIG 5D /r
VMINSD xmm1, xmm2, xmm3/m64B V/V AVX Return the minimum scalar double precision floating-point 
value between xmm3/m64 and xmm2.
EVEX.LLIG.F2.0F.W1 5D /r
VMINSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}C V/V AVX512F Return the minimum scalar double precision floating-point 
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMINSD—Return Minimum Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-30 Vol. 2B}
MINSD (EVEX Encoded Version)
THEN DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])ELSE 
FI;
MINSD (VEX.128 Encoded Version)
DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
MINSD (128-bit Legacy SSE Version)
DEST[63:0] := MIN(SRC1[63:0], SRC2[63:0])DEST[MAXVL-1:64] (Unmodified)
VMINSD __m128d _mm_min_round_sd(__m128d a, __m128d b, int);VMINSD __m128d _mm_mask_min_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VMINSD __m128d _mm_maskz_min_round_sd( __mmask8 k, __m128d a, __m128d b, int);MINSD __m128d _mm_min_sd(__m128d a, __m128d b)
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”MINSS—Return Minimum Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-31MINSS—Return Minimum Scalar Single  Precision Floating-Point Value
Compares the low single precision floating-point values in  the first source operand and the second source operand 
and returns the minimum value to the low doubleword of the destination operand.
a value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN 
version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruct ion, the second source operand, either a NaN or a valid

floating-point value, is written to the result. If instead of this behavior, it is required that the NaN in either source 
operand be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison 
VEX.128 and EVEX encoded version: The first source oper and is an xmm register enco ded by (E)VEX.vvvv. Bits 
Software should ensure VMINSS is encoded with VEX.L= 0. Encoding VMINSS with VEX.L=1 may encounter unpre-
Operation
{
Mode 
Feature 
F3 0F 5D /r
MINSS xmm1,xmm2/m32A V/V SSE Return the minimum scalar single precision floating-point 
VEX.LIG.F3.0F.WIG 5D /r
VMINSS xmm1,xmm2, xmm3/m32B V/V AVX Return the minimum scalar single precision floating-point 
EVEX.LLIG.F3.0F.W0 5D /r
VMINSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae}C V/V AVX512F Return the minimum scalar single precision floating-point 
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMINSS—Return Minimum Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-32 Vol. 2B}
MINSS (EVEX Encoded Version)
THEN DEST[31:0] := MIN(SRC1[31:0], SRC2[31:0])ELSE 
FI;
VMINSS (VEX.128 Encoded Version)
DEST[31:0] := MIN(SRC1[31:0], SRC2[31:0])DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
MINSS (128-bit Legacy SSE Version)
DEST[31:0] := MIN(SRC1[31:0], SRC2[31:0])DEST[MAXVL-1:128] (Unmodified)
VMINSS __m128 _mm_min_round_ss(  __m128 a, __m128 b, int);
VMINSS __m128 _mm_mask_min_r ound_ss(__m128 s, __mmask8 k,  __m128 a, __m128 b, int);
VMINSS __m128 _mm_maskz_min_round_ss( __mmask8 k, __m128 a, __m128 b, int);
MINSS __m128 _mm_min_ss(__m128 a, __m128 b)
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”MONITOR—Set Up Monitor AddressINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-33MONITOR—Set Up Monitor Address
The MONITOR instruction arms address monitoring hardware  using an address specified in EAX (the address range 
that the monitoring hardware checks for store operatio ns can be determined by using CPUID). A store to an 
address within the specified address range triggers the monitoring hardware. The state of monitor hardware is 
used by MWAIT. 
The address is specified in RAX/EAX/AX and the size is based on the effectiv e address size of the encoded instruc-
tion. By default, the DS segment is used to create a lin ear address that is monitored. Segment overrides can be 
used.
ECX and EDX are also used. They communicate other inform ation to MONITOR. ECX specifies optional extensions. 
EDX specifies optional hints; it does not change the arch itectural behavior of the instruction. For the Pentium 4 
processor (family 15, model 3), no extensions or hints are defined. Undefined hints in EDX are ignored by the 
processor; undefined extensions in ECX raises a general protection fault.
The address range must use memory of the write-back ty pe. Only write-back memory will correctly trigger the 
monitoring hardware. Additional information on determinin g what address range to use in order to prevent false 
wake-ups is described in Chapter 9, “Mul tiple-Processor Management‚” of the Intel® 64 and IA-32 Architectures 
The MONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruction 
is subject to the permission checking and faults associat ed with a byte load. Like a load, MONITOR sets the A-bit 
but not the D-bit in page tables. 
CPUID.01H:ECX.MONITOR[bit 3] indicate s the availability of MONITOR and MW AIT in the processor. When set, 
MONITOR may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode 
exception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE 
MSR; disabling MONITOR clears the CPUID feature flag an d causes execution to generate an invalid-opcode excep-
tion. 
The instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
MONITOR sets up an address range for the monitor hardware using the content of EAX (RAX in 64-bit mode) as an effective address  
and puts the monitor hardware in armed state. Always use memory  of the write-back caching type. A store to the specified addres s 
range will trigger the monitor hardware. The content of ECX and EDX are used to communicate other information to the monitor 
hardware.
MONITOR void _mm_monitor(void const *p, unsigned extensions,unsigned hints)
En64-Bit 
0F 01 C8 MONITOR ZO Valid Valid Sets up a linear address range to be monitored by 
hardware and activates the monitor. The address range 
should be a write-back memory caching type. The address is DS:RAX/EAX/AX.
ZO N/A N/A N/A N/AMONITOR—Set Up Monitor AddressINSTRUCTION SET REFERENCE, M-U
4-34 Vol. 2BProtected Mode Exceptions
#GP(0) If the value in EAX is outside the CS, DS, ES, FS, or GS segment limit.
selector.
If ECX ≠ 0.
#SS(0) If the value in EAX is outside the SS segment limit.#PF(fault-code) For a page fault.
#UD If CPUID.01H:ECX.MONITOR[bit 3] = 0.
If current privilege level is not 0.
Real Address Mode Exceptions
#GP If the CS, DS, ES, FS, or GS register is used  to access memory and the value in EAX is outside 
of the effective address space from 0 to FFFFH.
If ECX ≠ 0.
#SS If the SS register is used to access memory and the value in EAX is outside of the effective 
#UD The MONITOR instruction is not recognized in virtual-8086 mode (even if 
CPUID.01H:ECX.MONITOR[bit 3] = 1).
#GP(0) If the linear address of the operand in the CS, DS, ES, FS, or GS segment is in a non-canonical 
form.
If RCX ≠ 0.
#SS(0) If the SS register is used to access memory and the value in EAX is in a non-canonical form.
#UD If the current privilege level is not 0.
If CPUID.01H:ECX.MONITOR[bit 3] = 0.MOV—MoveINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-35MOV—Move
En64-Bit 
88 /r MOV r/m8, r8 MR Valid Valid Move r8 to r/m8.
REX + 88 /r MOV r/m81, r81
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH. MR Valid N.E. Move r8 to r/m8.
89 /r MOV r/m16, r16 MR Valid Valid Move r16 to r/m16.89 /r MOV r/m32, r32 MR Valid Valid Move r32 to r/m32.REX.W + 89 /r MOV r/m64, r64 MR Valid N.E. Move r64 to r/m64.8A /r MOV r8, r/m8 RM Valid Valid Move r/m8 to r8.REX + 8A /r MOV r8
1, r/m81RM Valid N.E. Move r/m8 to r8.
8B /r MOV r16, r/m16 RM Valid Valid Move r/m16 to r16.8B /r MOV r32, r/m32 RM Valid Valid Move r/m32 to r32.REX.W + 8B /r MOV r64, r/m64 RM Valid N.E. Move r/m64 to r64.8C /r MOV r/m16, Sreg
2MR Valid Valid Move segment register to r/m16.
8C /r MOV r16/r32/m16, Sreg2MR Valid Valid Move zero extended 16-bit segment register 
to r16/r32/m16.
REX.W + 8C /r MOV r64/m16, Sreg2MR Valid Valid Move zero extended 16-bit segment register 
to r64/m16.

NOTES:
8E /r MOV Sreg, r/m162RM Valid Valid Move r/m16 to segment register.
REX.W + 8E /r MOV Sreg, r/m642RM Valid Valid Move lower 16 bits of r/m64 to segment 
register.
A0 MOV AL, moffs83FD Valid Valid Move byte at  (seg:offset) to AL.
REX.W + A0 MOV AL, moffs83FD  Valid N.E. Move byte at (offset) to AL.
A1 MOV AX, moffs163FD Valid Valid Move word at (seg:offset) to AX.
A1 MOV EAX, moffs323FD Valid Valid Move doubleword  at (seg:offset) to EAX.
REX.W + A1 MOV RAX, moffs643FD Valid N.E. Move quadword at (offset) to RAX.
A2 MOV moffs8, AL TD  Valid Valid Move AL to (seg:offset).
REX.W + A2 MOV moffs81, AL TD Valid N.E. Move AL to (offset).
A3 MOV moffs163, AX TD Valid Valid Move AX to (seg:offset).
A3 MOV moffs323, EAX TD Valid Valid Move EAX to (seg:offset).
REX.W + A3 MOV moffs643, RAX TD Valid N.E. Move RAX to (offset).
B0+ rb ib MOV r8, imm8 OI Vali d Valid Move imm8 to r8.
REX + B0+ rb ib MOV r81, imm8 OI Valid N.E. Move imm8 to r8.
B8+ rw iw MOV r16, imm16 OI Valid Valid Move imm16 to r16.B8+ rd id MOV r32, imm32 OI Valid Valid Move imm32 to r32.REX.W + B8+ rd io MOV r64, imm64 OI Valid N.E. Move imm64 to r64.C6 /0 ib MOV r/m8, imm8 MI Valid Valid Move imm8 to r/m8.REX + C6 /0 ib MOV r/m8
1, imm8 MI Valid N.E. Move imm8 to r/m8.
C7 /0 iw MOV r/m16, imm16 MI Valid Valid Move imm16 to r/m16.C7 /0 id MOV r/m32, imm32 MI Valid Valid Move imm32 to r/m32.REX.W + C7 /0 id MOV r/m64, imm32 MI Valid N.E. Move imm32 sign extended to 64-bits to 
r/m64.MOV—MoveINSTRUCTION SET REFERENCE, M-U
4-36 Vol. 2BInstruction Operand Encoding
Copies the second operand (source operand) to the first operand (destination operand). The source operand can be 
an immediate value, general-purpose register, segment regi ster, or memory location; the destination register can 
be a general-purpose register, segment register, or memory  location. Both operands must be the same size, which 
can be a byte, a word, a doubleword, or a quadword.
The MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode excep-
tion (#UD). To load the CS register, us e the far JMP, CALL, or RET instruction.
If the destination operand is a segment register (DS, ES , FS, GS, or SS), the source operand must be a valid 
segment selector. In protected mode, moving a segment sele ctor into a segment register automatically causes the 
segment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part 
of the segment register. While loading this information, the segment selector and segment descriptor information 
is validated (see the “Operation” algorithm below). The segment descriptor data is obtained from the GDT or LDT 
entry for the specified segment selector. 
A NULL segment selector (values 0000-0003) can be loaded  into the DS, ES, FS, and GS registers without causing 
a protection exception. However, any subsequent atte mpt to reference a segment whose corresponding segment 
register is loaded with a NULL value causes a general pr otection exception (#GP) and no memory reference occurs.
Loading the SS register with a MOV instruction suppresses or inhibits some debug exceptions and inhibits inter-
rupts on the following instruction boundary. (The inhibition ends after delivery of an exception or the execution of the next instruction.) This behavior allows a stack pointer to be loaded into the ESP register with the next instruc-
tion (MOV ESP, stack-pointer value ) before an event can be delivered. See Section 6.8.3, “Masking Exceptions 
and Interrupts When Switching Stacks,” in the Intel
Volume 3A. Intel recommends that software use the LSS in struction to load the SS register and ESP together.
When executing MOV Reg, Sreg, the processor copies the co ntent of Sreg to the 16 least significant bits of the 
general-purpose register. The upper bits of the destinatio n register are zero for most IA-32 processors (Pentium 
Pro processors and later) and all Intel 64 processors, with  the exception that bits 31:16 are undefined for Intel 
Quark X1000 processors, Pentium, and earlier processors.
Operation
Loading a segment register while in protected mode results in special checks and actions, as described in the following listing . These 
checks are performed on the segment selector an d the segment descriptor to which it points.
IF SS is loaded2. In 32-bit mode, the assembler may insert  the 16-bit operand-size pref ix with this instruction (s ee the following “Descriptio n” section 
for further information).
3. The moffs8, moffs16, moffs32, and moffs64 operands specify a si mple offset relative to the segment base, where 8, 16, 32, an d 64 
refer to the size of the data. The address-size attribute of  the instruction determines the size of the offset, either 16, 32, or 64 bits.
MR ModRM:r/m (w) ModRM:reg (r) N/A N/A
FD AL/AX/EAX/RAX Moffs N/A N/A
TD Moffs (w) AL/AX/EAX/RAX N/A N/A
OI opcode + rd (w) imm8/16/32/64 N/A N/A
MI ModRM:r/m (w) imm8/16/32/64 N/A N/AMOV—MoveINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-37THEN
IF segment selector is NULL
IF segment selector index is ou tside descriptor table limits 
OR segment selector's RPL ≠ CPL
OR segment is not a writable data segment
OR DPL ≠ CPL
IF segment not marked present 
THEN #SS(selector); ELSE
SS := segment selector;SS := segment descriptor; FI;
FI;
IF DS, ES, FS, or GS is lo aded with non-NULL selector
THEN
IF segment selector index is outside descriptor table limits
OR segment is not a data or readable code segmentOR ((segment is a data or no nconforming code segment) AND ((RPL > DPL) or (CPL > DPL)))
IF segment not marked present
THEN #NP(selector);ELSE
SegmentRegister := segment selector;
SegmentRegister := se gment descriptor; FI;
FI;
IF DS, ES, FS, or GS is loaded with NULL selector
THEN
SegmentRegister := segment descriptor;
FI;
None.
#GP(0) If attempt is made to load SS register with NULL segment selector.
If the destination operand is in a non-writable segment.
#GP(selector) If segment selector index is outside descriptor table limits. 
If the SS register is being loaded and the se gment selector's RPL and the segment descriptor’s 
DPL are not equal to the CPL. 
If the SS register is being loaded  and the segment pointed to is a 
non-writable data segment.
If the DS, ES, FS, or GS register is being load ed and the segment pointed to is not a data or 
readable code segment.
If the DS, ES, FS, or GS register is being lo aded and the segment pointed to is a data or 
nonconforming code segment, and either the RPL or the CPL is greater than the DPL.
#SS(selector) If the SS register is being loaded and the segment pointed to is marked not present.MOV—MoveINSTRUCTION SET REFERENCE, M-U
4-38 Vol. 2B#NP If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not 
present.
#UD If attempt is made to load the CS register.
If an attempt is made to load SS register  with NULL segment selector when CPL = 3.
If an attempt is made to load SS register wi th NULL segment selector when CPL < 3 and CPL ≠ 
RPL.
#GP(selector) If segment selector index is outside descriptor table limits.

RPL.
If the memory access to the descriptor table is non-canonical.If the SS register is being loaded and the se gment selector's RPL and the segment descriptor’s 
DPL are not equal to the CPL.
If the SS register is being loaded and the segment pointed to is a nonwritable data segment.If the DS, ES, FS, or GS register is being load ed and the segment pointed to is not a data or 
nonconforming code segment, but both the RPL and the CPL are greater than the DPL.
#SS(0) If the stack address is in a non-canonical form.
#SS(selector) If the SS register is being loaded and the segment pointed to is marked not present.
If the LOCK prefix is used.MOV—Move to/from Control RegistersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-39MOV—Move to/from Control Registers
Moves the contents of a control register (CR0, CR2, CR3,  CR4, or CR8) to a general-purpose register or the 
contents of a general-purpose register to a control register. The operand size for these instructions is always 32 bits 
in non-64-bit modes, regardless of the operand-size attrib ute. On a 64-bit capable processor, an execution of MOV 
to CR outside of 64-bit mode zeros the upper 32 bits of the control register. (See “Control Registers” in Chapter 2 
of the Intel® 64 and IA-32 Architectures Software Developer’s Manua l, Volume 3A, for a detailed description of the 
flags and fields in the control registers.) This instruction can be executed only when the current privilege level is 0.
At the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read. 
The 2 bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read. Some 
of the bits in CR0, CR3, and CR4 are reserved and must be  written with zeros. Attempting to set any reserved bits 
in CR0[31:0] is ignored. Attempting to set any reserved bits in CR0[63:32] results in a general-protection excep-
tion, #GP(0). When PCIDs are not enabled, bits 2:0 and bi ts 11:5 of CR3 are not used and attempts to set them 
are ignored. Attempting to set any reserved bits in CR3[63:MAXPHYADDR] results in #GP(0). Attempting to set 
any reserved bits in CR4 results in #GP(0). On Pentium 4, Intel Xeon and P6 family processors, CR0.ET remains set 
after any load of CR0; attempts to clear this bit have no impact.
In certain cases, these instructions have the side effect of invalidating entries in the TLBs and the paging-structure 
caches. See Section 4.10.4.1, “Operations that Invalidat e TLBs and Paging-Structure Caches,” in the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 3A, for details.
The following side effects are implementation-specific for the Pentium 4, Intel Xeon, and P6 processor family: when 
modifying PE or PG in register CR0, or PSE or PAE in re gister CR4, all TLB entries are flushed, including global 
entries. Software should not depend on this f unctionality in all Intel 64 or IA-32 processors.
In 64-bit mode, the instruction’s default operation size is  64 bits. The REX.R prefix must be used to access CR8. 
Use of REX.B permits access to additional registers (R8-R15) . Use of the REX.W prefix or 66H prefix is ignored. Use Opcode/
En64-Bit 
0F 20/r
MOV r32, CR0–CR7MR N.E. Valid Move control register to r32.
0F 20/r
MOV r64, CR0–CR7MR Valid N.E. Move extended control register to r64. 
REX.R + 0F 20 /0
MOV r64, CR8MR Valid N.E. Move extended CR8 to r64.1
NOTES:
1. MOV CR* instructions, except for MOV CR8, are serializing instructions. MOV CR8 is not architecturally defined as a serializ ing instruc-
tion. For more information, see Chapter 9 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.0F 22 /r
MOV CR0–CR7, r32RM N.E. Valid Move r32 to control register.
0F 22 /r
MOV CR0–CR7, r64RM Valid N.E. Move r64 to extended control register.
REX.R + 0F 22 /0
MOV CR8, r64RM Valid N.E. Move r64 to extended CR8.1
MR ModRM:r/m (w) ModRM:reg (r) N/A N/ARM ModRM:reg (w) ModRM:r/m (r) N/A N/AMOV—Move to/from Control RegistersINSTRUCTION SET REFERENCE, M-U
4-40 Vol. 2Bof the REX.R prefix to specify a register other than CR8 causes an invalid-opcode exception. See the summary chart 
at the beginning of this sectio n for encoding data and limits.
If CR4.PCIDE = 1, bit 63 of the source operand to MOV to CR3 determines whether the instruction invalidates 
entries in the TLBs and the paging-structure caches (see  Section 4.10.4.1, “Operations that Invalidate TLBs and 
Paging-Structure Caches,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). The 
instruction does not modify bit 63 of CR3, which is reserved and always 0.
Operation
The OF, SF, ZF, AF, PF, and CF flags are undefined.
If an attempt is made to write invalid bit combin ations in CR0 (such as setting the PG flag to 1 
when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).
If an attempt is made to write a 1 to any reserved bit in CR4.If an attempt is made to write 1 to CR4.PCIDE.
If any of the reserved bits are set in the page -directory pointers table (PDPT) and the loading 
of a control register causes the PDPT to be loaded into the processor.
If an attempt is made to activate IA-32e mode  and either the current CS has the L-bit set or 
the TR references a 16-bit TSS.
If an attempt is made to access CR1, CR5, CR6, CR7, or CR9–CR15.
#GP If an attempt is made to write a 1 to any reserved bit in CR4.
If an attempt is made to write 1 to CR4.PCIDE.
when the PE flag is set to 0).
#GP(0) These instructions cannot be executed in virtual-8086 mode.
If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] ≠ 000H.
If an attempt is made to clear CR0.PG[bit 31] while CR4.PCIDE = 1.If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].MOV—Move to/from Control RegistersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-41#UD If the LOCK prefix is used.
If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1 
If an attempt is made to clear CR0.PG[bit 31].If an attempt is made to write a 1 to any reserved bit in CR4.
If an attempt is made to write a 1 to any reserved bit in CR8.
If an attempt is made to write a 1 to any reserved bit in CR3[63:MAXPHYADDR].
If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].
If the REX.R prefix is used to specify a register other than CR8.MOV—Move to/from Debug RegistersINSTRUCTION SET REFERENCE, M-U
4-42 Vol. 2BMOV—Move to/from Debug Registers
Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose 
register or vice versa. The operand size for these instructions is always 32 bits in non-64-bit modes, regardless of 
the operand-size attribute. (See Section 18.2, “Debug Registers”, of the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3A, for a detailed descrip tion of the flags and fields in the debug registers.)
The instructions must be executed at privilege level 0 or in real-address mode.

When the debug extension (DE) flag in register CR4 is cl ear, these instructions operate on debug registers in a 
manner that is compatible with Intel386 and Intel486 pr ocessors. In this mode, references to DR4 and DR5 refer 
to DR6 and DR7, respectively. When the DE flag in CR4 is  set, attempts to reference DR4 and DR5 result in an 
undefined opcode (#UD) exception. (The CR4 register wa s added to the IA-32 Architecture beginning with the 
Pentium processor.)
At the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read. 
The two bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.
In 64-bit mode, the instruction’s default operation size is  64 bits. Use of the REX.B pr efix permits access to addi-
tional registers (R8–R15). Use of the REX.W or 66H prefix is ignored. Use of the REX.R prefix causes an invalid-
opcode exception. See the summary chart at the beginni ng of this section for encoding data and limits. 
Operation
IF ((DE = 1) and (SRC or DEST = DR4 or DR5))
THEN
#UD;
ELSE 
FI;
The OF, SF, ZF, AF, PF, and CF flags are undefined.Opcode/
En64-Bit 
0F 21/r
MOV r32, DR0–DR7MR N.E. Valid Move debug register to r32.
0F 21/r
MOV r64, DR0–DR7MR Valid N.E. Move extended debug register to r64. 
0F 23 /r
MOV DR0–DR7, r32RM N.E. Valid Move r32 to debug register.
0F 23 /r
MOV DR0–DR7, r64RM Valid N.E. Move r64 to extended debug register. 
MR ModRM:r/m (w) ModRM:reg (r) N/A N/ARM ModRM:reg (w) ModRM:r/m (r) N/A N/AMOV—Move to/from Debug RegistersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-43Protected Mode Exceptions
#UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or 
DR5.
#DB If any debug register is accessed while the DR7.GD[bit 13] = 1.
DR5. 
#GP(0) The debug registers cannot be loaded or read when in virtual-8086 mode.
If an attempt is made to write a 1 to any of bits 63:32 in DR6.
If an attempt is made to write a 1 to any of bits 63:32 in DR7.
DR5.
If the REX.R prefix is used.
#DB If any debug register is accessed while the DR7.GD[bit 13] = 1.MOVAPD—Move Aligned Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-44 Vol. 2BMOVAPD—Move Aligned Packed Double Precision Floating-Point Values
Moves 2, 4 or 8 double precision floating-point values fr om the source operand (second operand) to the destination 
operand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit, 256-
bit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit or 
512-bit memory location, or to move data be tween two XMM, two YMM or two ZMM registers. 
When the source or destination operand is a memory oper and, the operand must be aligned on a 16-byte (128-bit 
versions), 32-byte (256-bit version) or 64-byte (EVEX.512 encoded version) boundary or a general-protection Opcode/
Mode 
Feature 
66 0F 28 /r
MOVAPD xmm1, xmm2/m128A V/V SSE2 Move aligned packed double precision floating-
point values from xmm2/mem to xmm1. 
66 0F 29 /r
MOVAPD xmm2/m128, xmm1B V/V SSE2 Move aligned packed double precision floating-
point values from xmm1 to xmm2/mem. 
VEX.128.66.0F.WIG 28 /r
VMOVAPD xmm1, xmm2/m128A V/V AVX Move aligned packed double precision floating-
VEX.128.66.0F.WIG 29 /r
VMOVAPD xmm2/m128, xmm1B V/V AVX Move aligned packed double precision floating-
VEX.256.66.0F.WIG 28 /r
VMOVAPD ymm1, ymm2/m256A V/V AVX Move aligned packed double precision floating-
point values from ymm2/mem to ymm1. 
VEX.256.66.0F.WIG 29 /r
VMOVAPD ymm2/m256, ymm1B V/V AVX Move aligned packed double precision floating-
point values from ymm1 to ymm2/mem. 
EVEX.128.66.0F.W1 28 /r
VMOVAPD xmm1 {k1}{z}, xmm2/m128CV / V A V X 5 1 2 V L
AVX512FMove aligned packed double precision floating-
point values from xmm2 /m128 to xmm1 using 
EVEX.256.66.0F.W1 28 /r
VMOVAPD ymm1 {k1}{z}, ymm2/m256 CV / V A V X 5 1 2 V L
point values from ymm2/m256 to ymm1 using 
EVEX.512.66.0F.W1 28 /r
VMOVAPD zmm1 {k1}{z}, zmm2/m512C V/V AVX512F Move aligned packed double precision floating-
point values from zmm2/m512 to zmm1 using writemask k1.
EVEX.128.66.0F.W1 29 /r
VMOVAPD xmm2/m12 8 {k1}{z}, xmm1DV / V A V X 5 1 2 V L
point values from xmm1  to xmm2/m128 using 
EVEX.256.66.0F.W1 29 /r
VMOVAPD ymm2/m256 {k1}{z}, ymm1DV / V A V X 5 1 2 V L
point values from ymm1 to ymm2/m256 using 
EVEX.512.66.0F.W1 29 /r
VMOVAPD zmm2/m512 {k1}{z}, zmm1D V/V AVX512F Move aligned packed double precision floating-
point values from zmm1 to zmm2/m512 using writemask k1.
B N/A ModRM:r/m (w) ModRM:reg (r) N/A N/A
C Full Mem ModRM:reg (w) ModRM:r/m (r) N/A N/A
D Full Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVAPD—Move Aligned Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-45exception (#GP) will be generated. For EVEX encoded vers ions, the operand must be aligned to the size of the 
memory operand. To move double precision floating-point values to and from unaligned memory locations, use the 
VMOVUPD instruction.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.EVEX.512 encoded version:Moves 512 bits of packed double precision floating-point values from the source operand (second operand) to the 
destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float64 
memory location, to store the contents of a ZMM register into a 512-bit float64 memory location, or to move data 
between two ZMM registers. When the so urce or destination operand is a memory operand, the operand must be 
aligned on a 64-byte boundary or a general-protection exce ption (#GP) will be generated. To move single precision 
floating-point values to and from unaligned memory locations, use the VMOVUPD instruction.
VEX.256 and EVEX.256 encoded versions:Moves 256 bits of packed double precision floating-point values from the source operand (second operand) to the 
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory 
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM 
registers. When the source or destination operand is a me mory operand, the operand must be aligned on a 32-byte 
boundary or a general-protection exception (#GP) will be  generated. To move double precision floating-point 
values to and from unaligned memory locations, use the VMOVUPD instruction.
128-bit versions:Moves 128 bits of packed double precision floating-point values from the source operand (second operand) to the 
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory 
location, to store the contents of an XMM register into  a 128-bit memory location, or to move data between two 
XMM registers. When the source or de stination operand is a memory operand, the operand must be aligned on a 
16-byte boundary or a general-protection exception (#GP) w ill be generated. To move single precision floating-
point values to and from unaligned memory locations, use the VMOVUPD instruction.
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding ZMM destination register remain 
unchanged. 
(E)VEX.128 encoded version: Bits (MAXVL-1:128) of the destination ZMM register destination are zeroed. 
Operation
VMOVAPD (EVEX Encoded Versions, Register-Copy Form)
THEN DEST[i+63:i] := SRC[i+63:i]ELSE 
FI
FI;

Operation
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0MOVAPD—Move Aligned Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-46 Vol. 2BVMOVAPD (EVEX Encoded Versions, Store-Form) 
THEN DEST[i+63:i] := SRC[i+63:i]ELSE ELSE *DEST[i+63:i] remains unchanged* ; merging-masking
FI;
ENDFOR;
VMOVAPD (EVEX Encoded Versions, Load-Form) 
FI
FI;
VMOVAPD (VEX.256 Encoded Version,  Load - and Register Copy)
DEST[255:0] := SRC[255:0]DEST[MAXVL-1:256] := 0
VMOVAPD (VEX.256 Encoded Version, Store-Form)
VMOVAPD (VEX.128 Encoded Version,  Load - and Register Copy)
MOVAPD (128-bit Load- and Register-Copy- Form Legacy SSE Version)
DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128] (Unmodified)
(V)MOVAPD (128-bit Store-Form Version)
DEST[127:0] := SRC[127:0]MOVAPD—Move Aligned Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-47Intel C/C++ Compiler Intrinsic Equivalent
VMOVAPD __m512d _mm512_load_pd( void * m);
VMOVAPD __m512d _mm512_mask_load_pd(__m512d s, __mmask8 k, void * m);VMOVAPD __m512d _mm512_maskz_load_pd( __mmask8 k, void * m);VMOVAPD void _mm512_store_pd( void * d, __m512d a);VMOVAPD void _mm512_mask_store_pd( void * d, __mmask8 k, __m512d a);VMOVAPD __m256d _mm256_mask_load_pd(__m256d s, __mmask8 k, void * m);VMOVAPD __m256d _mm256_maskz_load_pd( __mmask8 k, void * m);VMOVAPD void _mm256_mask_store_pd( void * d, __mmask8 k, __m256d a);VMOVAPD __m128d _mm_mask_load_pd(__m 128d s, __mmask8 k, void * m);
VMOVAPD __m128d _mm_maskz_load_pd( __mmask8 k, void * m);VMOVAPD void _mm_mask_store_pd( void * d, __mmask8 k, __m128d a);MOVAPD __m256d _mm256_load_pd (double * p);MOVAPD void _mm256_store_pd(double * p, __m256d a);MOVAPD __m128d _mm_load_pd (double * p);MOVAPD void _mm_store_pd(double * p, __m128d a);
None.
Non-EVEX-encoded instruction, see Exceptions Type1.SS E2 in Table 2-18, “Type 1 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-44, “Type E1 Class Exception Conditions.”
Additionally:#UD If EVEX.vvvv != 1111B  or VEX.vvvv != 1111B.MOVAPS—Move Aligned Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-48 Vol. 2BMOVAPS—Move Aligned Packed Single Precision Floating-Point Values
Moves 4, 8 or 16 single precision floating-point values fr om the source operand (second operand) to the destination 
version), 32-byte (VEX.256 encoded version) or 64-by te (EVEX.512 encoded version) boundary or a general-
protection exception (#GP) will be generated. For EVEX.5 12 encoded versions, the operand must be aligned to the 
size of the memory operand. To move single precision fl oating-point values to and from unaligned memory loca-
tions, use the VMOVUPS instruction.
Mode 
Feature 
NP 0F 28 /r
MOVAPS xmm1, xmm2/m128A V/V SSE Move aligned packed single precision floating-point 
values from xmm2/mem to xmm1. 
NP 0F 29 /r
MOVAPS xmm2/m128, xmm1B V/V SSE Move aligned packed single precision floating-point 
values from xmm1  to xmm2/mem. 
VEX.128.0F.WIG 28 /r
VMOVAPS xmm1, xmm2/m128A V/V AVX Move aligned packed single precision floating-point 
VEX.128.0F.WIG 29 /r
VMOVAPS xmm2/m128, xmm1B V/V AVX Move aligned packed single precision floating-point 
VEX.256.0F.WIG 28 /r
VMOVAPS ymm1, ymm2/m256A V/V AVX Move aligned packed single precision floating-point 
values from ymm2/mem to ymm1. 
VEX.256.0F.WIG 29 /r
VMOVAPS ymm2/m256, ymm1B V/V AVX Move aligned packed single precision floating-point 
values from ymm1 to ymm2/mem. 
EVEX.128.0F.W0 28 /r
VMOVAPS xmm1 {k1}{z}, xmm2/m128CV / V A V X 5 1 2 V L
AVX512FMove aligned packed single precision floating-point 
values from xmm2/m128 to xmm1 using writemask k1.
EVEX.256.0F.W0 28 /r
VMOVAPS ymm1 {k1}{z}, ymm2/m256CV / V A V X 5 1 2 V L
values from ymm2/m256 to ymm1 using writemask k1.
EVEX.512.0F.W0 28 /r
VMOVAPS zmm1 {k1}{z}, zmm2/m512C V/V AVX512F Move aligned packed single precision floating-point 
values from zmm2/m512 to zmm1 using writemask k1.
EVEX.128.0F.W0 29 /r
VMOVAPS xmm2/m128 {k1}{z}, xmm1DV / V A V X 5 1 2 V L
values from xmm1 to xmm2 /m128 using writemask k1.
EVEX.256.0F.W0 29 /r
VMOVAPS ymm2/m256 {k1}{z}, ymm1DV / V A V X 5 1 2 V L
values from ymm1 to ymm2/m256 using writemask k1.
EVEX.512.0F.W0 29 /r
VMOVAPS zmm2/m512 {k1}{z}, zmm1D V/V AVX512F Move aligned packed single precision floating-point 
values from zmm1 to zmm2 /m512 using writemask k1.
C Full Mem ModRM:reg (w ) ModRM:r/m (r) N/A N/A
D Full Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVAPS—Move Aligned Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-49EVEX.512 encoded version:
Moves 512 bits of packed single precision floating-point values from the source operand (second operand) to the 
destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32 
memory location, to store the contents of a ZMM register into a float32 memory location, or to move data between 
two ZMM registers. When the source or destination operan d is a memory operand, the operand must be aligned on 
a 64-byte boundary or a general-protection exception (#GP ) will be generated. To move single precision floating-
point values to and from unaligned memory locations, use the VMOVUPS instruction.
VEX.256 and EVEX.256 encoded version:Moves 256 bits of packed single precision floating-point values from the source operand (second operand) to the 
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers. When the source or destination operand is a me mory operand, the operand must be aligned on a 32-byte 
boundary or a general-protection exception (#GP) will be generated.
128-bit versions:Moves 128 bits of packed single precision floating-point values from the source operand (second operand) to the 
(E)VEX.128 encoded version: Bits (MAXVL-1:128 ) of the destination ZMM register are zeroed.
Operation
VMOVAPS (EVEX Encoded Versions, Register-Copy Form)
THEN DEST[i+31:i] := SRC[i+31:i]ELSE 
FI
FI;
VMOVAPS (EVEX Encoded Versions, Store Form) 
THEN DEST[i+31:i] := 
SRC[i+31:i]
ELSE *DEST[i+31:i] remains unchanged* ; merging-masking
FI;
ENDFOR;MOVAPS—Move Aligned Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-50 Vol. 2BVMOVAPS (EVEX Encoded Versions, Load Form) 
THEN DEST[i+31:i] := SRC[i+31:i]ELSE

Operation
FI
FI;
FI;
FI
FI;
VMOVAPS (VEX.256 Encoded Version, Load - and Register Copy)
VMOVAPS (VEX.256 Encoded Version, Store-Form)
VMOVAPS (VEX.128 Encoded Version, Load - and Register Copy)
MOVAPS (128-bit Load- and Register-Copy- Form Legacy SSE Version)
(V)MOVAPS (128-bit Store-Form Version)
DEST[127:0] := SRC[127:0]
VMOVAPS __m512 _mm512_load_ps( void * m);VMOVAPS __m512 _mm512_mask_load_ps(__ m512 s, __mmask16 k, void * m);
VMOVAPS __m512 _mm512_maskz_load_ps( __mmask16 k, void * m);VMOVAPS void _mm512_store_ps( void * d, __m512 a);VMOVAPS void _mm512_mask_store_ps( void * d, __mmask16 k, __m512 a);VMOVAPS __m256 _mm256_mask_load_ps(__ m256 a, __mmask8 k, void * s);
VMOVAPS __m256 _mm256_maskz_load_ps( __mmask8 k, void * s);VMOVAPS void _mm256_mask_store_ps( void * d, __mmask8 k, __m256 a);VMOVAPS __m128 _mm_mask_load_ps(__m 128 a, __mmask8 k, void * s);
VMOVAPS __m128 _mm_maskz_load_ps( __mmask8 k, void * s);VMOVAPS void _mm_mask_store_ps( void * d, __mmask8 k, __m128 a);MOVAPS __m256 _mm256_load_ps (float * p);MOVAPS void _mm256_store_ps(float * p, __m256 a);MOVAPS __m128 _mm_load_ps (float * p);MOVAPS void _mm_store_ps (float * p, __m128 a);
None.MOVAPS—Move Aligned Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-51Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SS E in Table 2-18, “Type 1 Class Exception Conditions,” 
additionally:
EVEX-encoded instruction, see Table 2-44, “Type E1 Class Exception Conditions.”MOVBE—Move Data After Swapping BytesINSTRUCTION SET REFERENCE, M-U
4-52 Vol. 2BMOVBE—Move Data After Swapping Bytes
Performs a byte swap operation on the data copied from the second operand (source operand) and store the result 
in the first operand (destination operand). The source operand can be a general-purpose register, or memory loca-
tion; the destination register can be a general-purpose regi ster, or a memory location; however, both operands can 
not be registers, and only one operand can be a memory lo cation. Both operands must be the same size, which can 
be a word, a doubleword or quadword. 
The MOVBE instruction is provided for swapping the bytes on a read from memory or on a write to memory; thus 
providing support for converting little-endian values to big-endian format and vice versa.
In 64-bit mode, the instruction's default operation size is  32 bits. Use of the REX.R prefix permits access to addi-
Operation
TEMP := SRC
IF ( OperandSize = 16)
THEN
DEST[7:0] := TEMP[15:8];
DEST[15:8] := TEMP[7:0];
ELES IF ( OperandSize = 32) 
DEST[7:0] := TEMP[31:24];DEST[15:8] := TEMP[23:16];DEST[23:16] := TEMP[15:8];DEST[31:23] := TEMP[7:0];
ELSE IF ( OperandSize 
= 64) 
DEST[7:0] := TEMP[63:56];DEST[15:8] := TEMP[55:48];Opcode/
Mode 
Feature 
0F 38 F0 /r
MOVBE r16, m16RM V/V MOVBE Reverse byte order in m16 and move to r16.
0F 38 F0 /r
MOVBE r32, m32RM V/V MOVBE Reverse byte order in m32 and move to r32.
REX.W + 0F 38 F0 /r
MOVBE r64, m64RM V/N.E. MOVBE Reverse byte orde r in m64 and move to r64. 
0F 38 F1 /r
MOVBE m16, r16MR V/V MOVBE Reverse byte order in r16 and move to m16.
0F 38 F1 /r
MOVBE m32, r32MR V/V MOVBE Reverse byte order in r32 and move to m32.
REX.W + 0F 38 F1 /r
MOVBE m64, r64MR V/N.E. MOVBE Reverse byte orde r in r64 and move to m64. 
MR ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVBE—Move Data After Swapping BytesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-53DEST[23:16] := TEMP[47:40];
DEST[31:24] := TEMP[39:32];DEST[39:32] := TEMP[31:24];DEST[47:40] := TEMP[23:16];DEST[55:48] := TEMP[15:8];DEST[63:56] := TEMP[7:0];
FI;
None.
#GP(0) If the destination operand is in a non-writable segment.
#UD If CPUID.01H:ECX.MOVBE[bit 22] = 0.
If the LOCK prefix is used.If REP (F3H) prefix is used.
If REPNE (F2H) prefix is used an d CPUID.01H:ECX.SSE4_2[bit 20] = 0.
Same exceptions as in protected mode.MOVBE—Move Data After Swapping BytesINSTRUCTION SET REFERENCE, M-U
4-54 Vol. 2B64-Bit Mode Exceptions
#SS(0) If the stack address is in a non-canonical form.#PF(fault-code) If a page fault occurs.
If REP (F3H) prefix is used.MOVD/MOVQ—Move Doubleword/Move QuadwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-55MOVD/MOVQ—Move Doubleword/Move Quadword
Instruction Operand EncodingOpcode/
InstructionOp/ En 64/32-bit 
ModeCPUID 
Feature 
NP 0F 6E /r
MOVD mm, r/m32A V/V MMX Move doubleword from r/m32 to mm.
NP REX.W + 0F 6E /r
MOVQ mm, r/m64A V/N.E. MMX Move quadword from r/m64 to mm.
NP 0F 7E /r
MOVD r/m32, mmB V/V MMX Move doubleword from mm to r/m32.
NP REX.W + 0F 7E /r
MOVQ r/m64, mmB V/N.E. MMX Move quadword  from mm to r/m64.
66 0F 6E /r
MOVD xmm, r/m32A V/V SSE2 Move doubleword from r/m32 to xmm.
66 REX.W 0F 6E /r
MOVQ xmm, r/m64A V/N.E. SSE2 Move quadword from r/m64 to xmm.
66 0F 7E /r
MOVD r/m32, xmmB V/V SSE2 Move doubleword fr om xmm register to r/m32.
 66 REX.W 0F 7E /r
MOVQ r/m64, xmmB V/N.E. SSE2 Move quadword from xmm register to r/m64.
VEX.128.66.0F.W0 6E /
VMOVD xmm1, r32/m32A V/V AVX Move doubleword from r/m32 to xmm1.
VEX.128.66.0F.W1 6E /r
VMOVQ xmm1, r64/m64AV / N . E1. AVX Move quadword from r/m64 to xmm1.
VEX.128.66.0F.W0 7E /r
VMOVD r32/m32, xmm1B V/V AVX Move doubleword from  xmm1 register to r/m32.
VEX.128.66.0F.W1 7E /r
VMOVQ r64/m64, xmm1BV / N . E1. AVX Move quadword from xmm1 register to r/m64.
EVEX.128.66.0F.W0 6E /r
VMOVD xmm1, r32/m32C V/V AVX512F Move doubleword from r/m32 to xmm1.
EVEX.128.66.0F.W1 6E /r
VMOVQ xmm1, r64/m64CV / N . E .1
NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is  ignored; the instruction behaves as if the W0 version is used.AVX512F Move quadword from r/m64 to xmm1.
EVEX.128.66.0F.W0 7E /r
VMOVD r32/m32, xmm1DV / V A V X 5 1 2 F M o v e  d o u b l e w o r d  f r om xmm1 register to r/m32.
EVEX.128.66.0F.W1 7E /r
VMOVQ r64/m64, xmm1DV / N . E .1AVX512F Move quadword from xmm1 register to r/m64.
C Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
D Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVD/MOVQ—Move Doubleword/Move QuadwordINSTRUCTION SET REFERENCE, M-U
4-56 Vol. 2BDescription
Copies a doubleword from the source operand (second op erand) to the destination operand (first operand). The 
source and destination operands can be general-purpose re gisters, MMX technology registers, XMM registers, or 
32-bit memory locations. This instruction can be used to move a doubleword to and from  the low doubleword of an 
MMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low doubleword of an XMM register and a general-purpose regi ster or a 32-bit memory location. The instruction cannot

MMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low doubleword of an XMM register and a general-purpose regi ster or a 32-bit memory location. The instruction cannot 
be used to transfer data between MMX technology registers, between X MM registers, between general-purpose 
registers, or between memory locations.
When the destination operand is an MMX technology regist er, the source operand is written to the low doubleword 
of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the 
source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.
MOVD/Q with XMM destination:Moves a dword/qword integer from the source operand and st ores it in the low 32/64-bits of the destination XMM 
register. The upper bits of the destination are zeroed. The source operand can be a 32/64-bit register or 32/64-bit 
memory location. 
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged. 
Qword operation requires the use of REX.W=1.
VEX.128 encoded version: Bits (MAXVL-1:128) of the destin ation register are zeroed. Qword operation requires the 
use of VEX.W=1.
EVEX.128 encoded version: Bits (MAXVL-1:128) of the de stination register are zeroed. Qword operation requires 
the use of EVEX.W=1.
MOVD/Q with 32/64 reg/mem destination:Stores the low dword/qword of the source XMM register to  32/64-bit memory location or general-purpose register. 
Qword operation requires the use of  REX.W=1, VEX.W=1, or EVEX.W=1.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.If VMOVD or VMOVQ is encoded with VEX.L= 1, an attemp t to execute the instruction encoded with VEX.L= 1 will 
cause an #UD exception.
Operation
MOVD (When Destination Operand is  an MMX Technology Register)
DEST[31:0] := SRC;DEST[63:32] := 00000000H;
MOVD (When Destination Oper and is an XMM Register)
DEST[31:0] := SRC;DEST[127:32] := 000000000000000000000000H;DEST[MAXVL-1:128] (Unmodified)
MOVD (When Source Operand is an MMX Technology or XMM Register)
DEST := SRC[31:0];
VMOVD (VEX-Encoded Version when Destination is an XMM Register)
DEST[31:0] := SRC[31:0]DEST[MAXVL-1:32] := 0
MOVQ (When Destination Oper and is an XMM Register)
DEST[63:0] := SRC[63:0];DEST[127:64] := 0000000000000000H;DEST[MAXVL-1:128] (Unmodified)MOVD/MOVQ—Move Doubleword/Move QuadwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-57MOVQ (When Destinatio n Operand is r/m64)
DEST[63:0] := SRC[63:0];
MOVQ (When Source Operand is  an XMM Register or r/m64)
DEST := SRC[63:0];
VMOVQ (VEX-Encoded Version When Destination is an XMM Register)
DEST[63:0] := SRC[63:0]DEST[MAXVL-1:64] := 0
VMOVD (EVEX-Encoded Version When Destination is an XMM Register)
VMOVQ (EVEX-Encoded Version When Destination is an XMM Register)
MOVD __m64 _mm_cvtsi32_si64 (int i )
MOVD int _mm_cvtsi64_si32 ( __m64m ) MOVD __m128i _mm_cvtsi32_si128 (int a) MOVD int _mm_cvtsi128_si32 ( __m128i a)MOVQ __int64 _mm_cvtsi128_si64(__m128i); MOVQ __m128i _mm_cvtsi64_si128(__int64);VMOVD __m128i _mm_cvtsi32_si128( int);VMOVD int _mm_cvtsi128_si32( __m128i );VMOVQ __m128i _mm_cvtsi64_si128 (__int64);VMOVQ __int64 _mm_cvtsi128_si64(__m128i );VMOVQ __m128i _mm_loadl_epi64( __m128i * s);VMOVQ void _mm_storel_epi64(  __m128i * d, __m128i s);
None.
None.
Non-EVEX-encoded instruction, see Table 2-22, “Type 5 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions.”Additionally:
#UD If VEX.L = 1.
If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.MOVDDUP—Replicate Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-58 Vol. 2BMOVDDUP—Replicate Double Prec ision Floating-Point Values
For 256-bit or higher versions: Duplicates even-indexed double precision floating-point values from the source 
operand (the second operand) and into adjacent pair an d store to the destination operand (the first operand).
For 128-bit versions: Duplicates the low double precision fl oating-point value from the source operand (the second 
operand) and store to the destination operand (the first operand).
128-bit Legacy SSE version: Bits (MAXVL-1:128) of th e corresponding destination register are unchanged. The 
source operand is XMM register  or a 64-bit memory location.
VEX.128 and EVEX.128 encoded version: Bits (MAXVL-1:128 ) of the destination register are zeroed. The source 
operand is XMM register or a 64-bit memory location. Th e destination is updated conditionally under the writemask 
for EVEX version.
VEX.256 and EVEX.256 encoded version: Bits (MAXVL-1:256 ) of the destination register are zeroed. The source 
operand is YMM register or a 256-bit memory location. Th e destination is updated conditionally under the write-
mask for EVEX version.
EVEX.512 encoded version: The destination is updated a ccording to the writemask. The source operand is ZMM 
register or a 512-bit memory location.
Mode 
Feature 
F2 0F 12 /r
MOVDDUP xmm1, xmm2/m64A V/V SSE3 Move double precision floating-point value from 
xmm2/m64 and duplicate into xmm1.
VEX.128.F2.0F.WIG 12 /r
VMOVDDUP xmm1, xmm2/m64A V/V AVX Move double precision floating-point value from 
VEX.256.F2.0F.WIG 12 /r
VMOVDDUP ymm1, ymm2/m256A V/V AVX Move even index double precision floating-point values 
from ymm2/mem and duplicate each element into ymm1.
EVEX.128.F2.0F.W1 12 /r
VMOVDDUP xmm1 {k1}{z}, 
xmm2/m64BV / V A V X 5 1 2 V L
AVX512FMove double precision floating-point value from 
xmm2/m64 and duplicate each element into xmm1 
EVEX.256.F2.0F.W1 12 /r
VMOVDDUP ymm1 {k1}{z}, 
ymm2/m256BV / V A V X 5 1 2 V L
AVX512FMove even index double precision floating-point values 
from ymm2/m256 and duplicate each element into 
ymm1 subject to writemask k1.
EVEX.512.F2.0F.W1 12 /r
VMOVDDUP zmm1 {k1}{z}, 
zmm2/m512B V/V AVX512F Move even index double precision floating-point values 
from zmm2/m512 and duplicate each element into 
zmm1 subject to writemask k1.
B MOVDDUP ModRM:reg (w) ModRM:r/m (r) N/A N/AMOVDDUP—Replicate Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-59Operation
VMOVDDUP (EVEX Encoded Versions) 
TMP_SRC[63:0] := SRC[63:0] TMP_SRC[127:64] := SRC[63:0]IF VL >= 256
TMP_SRC[191:128] := SRC[191:128]TMP_SRC[255:192] := SRC[191:128]
FI;IF VL >= 512
TMP_SRC[319:256] := SRC[319:256]TMP_SRC[383:320] := SRC[319:256]TMP_SRC[477:384] := SRC[477:384]TMP_SRC[511:484] := SRC[477:384]
THEN DEST[i+63:i] := TMP_SRC[i+63:i]ELSE 
DEST[i+63:i] := 0 ; zeroing-masking
FI
FI;
VMOVDDUP (VEX.256 Encoded Version)
DEST[63:0] := SRC[63:0]DEST[127:64] := SRC[63:0]DEST[191:128] := SRC[191:128]DEST[255:192] := SRC[191:128]DEST[MAXVL-1:256] := 0
VMOVDDUP (VEX.128 Encoded Version)
DEST[63:0] := SRC[63:0]DEST[127:64] := SRC[63:0]DEST[MAXVL-1:128] := 0Figure 4-2.  VMOVDDUP OperationX2 X2 X0 X0 DESTX3 X2 SRC X1 X0MOVDDUP—Replicate Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-60 Vol. 2BMOVDDUP (128-bit Legacy SSE Version)
DEST[63:0] := SRC[63:0]DEST[127:64] := SRC[63:0]DEST[MAXVL-1:128] (Unmodified)
VMOVDDUP __m512d _mm512_movedup_pd( __m512d a);VMOVDDUP __m512d _mm512_mask_movedup_pd(__m512d s, __mmask8 k, __m512d a);VMOVDDUP __m512d _mm512_maskz_movedup_pd( __mmask8 k, __m512d a);VMOVDDUP __m256d _mm256_mask_movedup_pd(__m256d s, __mmask8 k, __m256d a);VMOVDDUP __m256d _mm256_maskz_movedup_pd( __mmask8 k, __m256d a);VMOVDDUP __m128d _mm_mask_movedup_pd(__m128d s, __mmask8 k, __m128d a);VMOVDDUP __m128d _mm_maskz_movedup_pd( __mmask8 k, __m128d a);MOVDDUP __m256d _mm256_movedup_pd (__m256d a);MOVDDUP __m128d _mm_movedup_pd (__m128d a);
None.
EVEX-encoded instruction, see Table 2-52, “Type E5NF Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.MOVDIRI—Move Doubleword as Direct StoreINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-61MOVDIRI—Move Doubleword as Direct Store

None.
Moves the doubleword integer in the source operand (secon d operand) to the destination operand (first operand) 
using a direct-store operation. The source operand is a general purpose register. The destination operand is a 32-
bit memory location. In 64-bit mode, the instruction’s defa ult operation size is 32 bits. Use of the REX.R prefix 
permits access to additional registers (R8-R15). Use of  the REX.W prefix promotes operation to 64 bits. See 
The direct-store is implemented by us ing write combining (WC) memory type protocol for writing data. Using this 
protocol, the processor does not write the data into the ca che hierarchy, nor does it fetch the corresponding cache 
line from memory into the cache hierarchy. If the destinat ion address is cached, the line is written-back (if modi-
fied) and invalidated from the cache, before the direct-s tore. Unlike stores with non-temporal hint that allow 
uncached (UC) and write-protected (WP) memory-type fo r the destination to override the non-temporal hint, 
direct-stores always follow WC memory type protocol irrespective of the destination address memory type 
(including UC and WP types).
Unlike WC stores and stores with non-temporal hint, dire ct-stores are eligible for im mediate eviction from the 
write-combining buffer, and thus not combined with younger stores (including direct-stores) to the same address. Older WC and non-temporal stores held in the write-comb ing buffer may be combined with younger direct stores 
to the same address. Direct stores are weakly ordered re lative to other stores. Software that desires stronger 
ordering should use a fencing instruction (MFENCE or SFENCE ) before or after a direct store to enforce the ordering 
desired.
Direct-stores issued by MOVDIRI to a destination aligne d to a 4-byte boundary (8-byte boundary if used with 
REX.W prefix) guarantee 4-byte (8-byte with REX.W prefix) write-completion atomicity. This means that the data 
arrives at the destination in a single undivided 4-byte (or 8-byte) write transaction. If the destination is not aligned 
for the write size, the direct-stores issued by MOVDIRI are sp lit and arrive at the destination in two parts. Each part 
of such split direct-store will not merge with younger stores  but can arrive at the destination in either order. Avail-
ability of the MOVDIRI instruction is indicated by the pres ence of the CPUID feature flag MOVDIRI (bit 27 of the 
ECX register in leaf 07H, see “CPUID—CPU Identification” in the Intel
Operation
MOVDIRI void _directstoreu_u32(void *dst, uint32_t val)
MOVDIRI void _directstoreu_u64(void *dst, uint64_t val)Opcode/
Mode 
Feature 
NP 0F 38 F9 /r
MOVDIRI m32, r32A V/V MOVDIRI Move doubleword from r32 to m32 using direct store.
NP REX.W + 0F 38 F9 /r
MOVDIRI m64, r64AV / N . E . M O V D I R I M o v e  q u a d word from r64 to m64 using direct store. 
A N/A ModRM:r/m (w) ModRM:reg (r) N/A N/A
1. The Mod field of the ModR/M byte cannot have value 11B.MOVDIRI—Move Doubleword as Direct StoreINSTRUCTION SET REFERENCE, M-U
4-62 Vol. 2BProtected Mode Exceptions
#UD If CPUID.07H.0H:ECX.MOVDIRI[bit 27] = 0.
If LOCK prefix or operand-size (66H) prefix is used.
#AC If alignment checking is enabled and an unali gned memory reference made while in current 
privilege level 3.
Same exceptions as in real address mode.#PF (fault-code) For a page fault.
#SS(0) If memory address referencing the SS segment is in non-canonical form.
#PF (fault-code) For a page fault.#UD If CPUID.07H.0H:ECX.MOVDIRI[bit 27] = 0.
privilege level 3.MOVDIR64B—Move 64 Bytes as Direct StoreINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-63MOVDIR64B—Move 64 Bytes as Direct Store
Moves 64-bytes as direct-store with 64-byte write atomic ity from source memory address to destination memory 
address. The source operand is a norm al memory operand. The destination operand is a memory location specified 
in a general-purpose register. The register content is inte rpreted as an offset into ES segment without any segment 
override. In 64-bit mode, the register operand width is 64-b its (32-bits with 67H prefix). Outside of 64-bit mode, 
the register width is 32-bits when CS.D=1 (16-bits with 67H prefix), and 16-bits when CS.D=0 (32-bits with 67H 
prefix). MOVDIR64B requires the destin ation address to be 64-byte aligned. No alignment restriction is enforced 
for source operand.
MOVDIR64B first reads 64-bytes from the source memory address. It then performs a 64-byte direct-store opera-
tion to the destination address. The load operation follows  normal read ordering based on source address memory-
type. The direct-store is implemented by using the write combining (WC) memo ry type protocol for writing data. 
Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corre-sponding cache line from memory into the cache hierarchy. If the destination address is cached, the line is written-
back (if modified) and invalidated from the cache, before the direct-store.
Unlike stores with non-temporal hint which allow UC/WP me mory-type for destination to override the non-temporal 
hint, direct-stores always follow WC memory type prot ocol irrespective of destination address memory type 
(including UC/WP types). Unlike WC stor es and stores with non-temporal hint, direct-stores are eligible for imme-
diate eviction from the write-combining buffer, and thus not combined with younger stores (including direct-stores) 
to the same address. Older WC and non-temporal stores held in the write-combing buffer may be combined with 
younger direct stores to the same address. Direct stores are weakly ordered relative to other stores. Software that 
desires stronger ordering should use a fencing instructio n (MFENCE or SFENCE) before or after a direct store to 
enforce the ordering desired.
There is no atomicity guarantee provided for the 64-byte load operation from source address, and processor imple-
mentations may use multiple load operations to read th e 64-bytes. The 64-byte direct-store issued by MOVDIR64B 
guarantees 64-byte write-completion atomicity. This means that the data arrives at the destination in a single undivided 64-byte write transaction. 
Availability of the MOVDIR64B instruction is indicated by  the presence of the CPUID feature flag MOVDIR64B (bit 
28 of the ECX register in leaf 07H, see “CPUID—CPU Identifica tion” in the Intel
ware Developer’s Manual, Volume 2A).
Operation
MOVDIR64B void _movdir64b(void *dst, const void* src)Opcode/
Mode 
Feature 
66 0F 38 F8 /r
MOVDIR64B r16/r32/r64, m512A V/V MOVDIR64B Move 64-bytes as direct-store with guaranteed 64-
byte write atomicity from the source memory operand 
address to destination memo ry address specified as 
offset to ES segment in  the register operand.
1. The Mod field of the ModR/M byte cannot have value 11B.MOVDIR64B—Move 64 Bytes as Direct StoreINSTRUCTION SET REFERENCE, M-U
4-64 Vol. 2BProtected Mode Exceptions
If address in destination (register) oper and is not aligned to a 64-byte boundary.
#UD If CPUID.07H.0H:ECX.MOVDIR64B[bit 28] = 0.

#SS(0) If memory address referencing the SS segment is in non-canonical form.#GP(0) If the memory address is in non-canonical form.
If LOCK prefix is used.MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-65MOVDQA,VMOVDQA32/64—Move Al igned Packed Integer Values
Opcode/
Mode 
66 0F 6F /r
MOVDQA xmm1, xmm2/m128A V/V SSE2 Move aligned packed integer values from 
xmm2/mem to xmm1. 
66 0F 7F /r
MOVDQA xmm2/m128, xmm1B V/V SSE2 Move aligned packed integer values from xmm1 
to xmm2/mem. 
VEX.128.66.0F.WIG 6F /r
VMOVDQA xmm1, xmm2/m128A V/V AVX Move aligned packed integer values from 
VEX.128.66.0F.WIG 7F /r
VMOVDQA xmm2/m128, xmm1B V/V AVX Move aligned packed integer values from xmm1 
VEX.256.66.0F.WIG 6F /r
VMOVDQA ymm1, ymm2/m256A V/V AVX Move aligned packed integer values from 
ymm2/mem to ymm1. 
VEX.256.66.0F.WIG 7F /r
VMOVDQA ymm2/m256, ymm1B V/V AVX Move aligned packed integer values from ymm1 
to ymm2/mem.
EVEX.128.66.0F.W0 6F /r
VMOVDQA32 xmm1  {k1}{z}, 
xmm2/m128C V/V AVX512VL
AVX512FMove aligned packed doubleword integer values 
from xmm2/m128 to xmm1 using writemask k1.
EVEX.256.66.0F.W0 6F /r
VMOVDQA32 ymm1 {k1}{z}, 
ymm2/m256 C V/V AVX512VL
from ymm2/m256 to ymm1 using writemask k1.
EVEX.512.66.0F.W0 6F /r
VMOVDQA32 zmm1 {k1}{z}, zmm2/m512C V/V AVX512F Move aligned packed doubleword integer values 
from zmm2/m512 to zmm1 using writemask k1.
EVEX.128.66.0F.W0 7F /r
VMOVDQA32 xmm2/m 128 {k1}{z}, 
xmm1D V/V AVX512VL
from xmm1 to xmm2/m128  using writemask k1.
EVEX.256.66.0F.W0 7F /r
VMOVDQA32 ymm2/m 256 {k1}{z}, 
ymm1D V/V AVX512VL
from ymm1 to ymm2/m256 using writemask k1.
EVEX.512.66.0F.W0 7F /r
VMOVDQA32 zmm2/m512 {k1}{z}, zmm1D V/V AVX512F Move aligned packed doubleword integer values 
from zmm1 to zmm2/m512 using writemask k1.
EVEX.128.66.0F.W1 6F /r
VMOVDQA64 xmm1  {k1}{z}, 
xmm2/m128 C V/V AVX512VL
AVX512FMove aligned packed quadword integer values 
EVEX.256.66.0F.W1 6F /r
VMOVDQA64 ymm1 {k1}{z}, 
EVEX.512.66.0F.W1 6F /r
VMOVDQA64 zmm1 {k1}{z}, zmm2/m512 C V/V AVX512F Move aligned packed quadword integer values 
EVEX.128.66.0F.W1 7F /r
VMOVDQA64 xmm2/m 128 {k1}{z}, 
EVEX.256.66.0F.W1 7F /r
VMOVDQA64 ymm2/m 256 {k1}{z}, 
EVEX.512.66.0F.W1 7F /r
VMOVDQA64 zmm2/m512 {k1}{z}, zmm1D V/V AVX512F Move aligned packed quadword integer values 
from zmm1 to zmm2/m512 using writemask k1.MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
4-66 Vol. 2BInstruction Operand Encoding
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX encoded versions:Moves 128, 256 or 512 bits of packed doubleword/quadwor d integer values from the source operand (the second 
operand) to the destination operand (the first operand). This  instruction can be used to load a vector register from 
an int32/int64 memory location, to store the contents of a vector register into an int32/int64 memory location, or 
to move data between two ZMM regist ers. When the source or destination operand is a memory operand, the 
operand must be aligned on a 16 (EVEX.128)/32(EVEX.256 )/64(EVEX.512)-byte boundary or a general-protection 
exception (#GP) will be generated. To move integer da ta to and from unaligned memory locations, use the 
VMOVDQU instruction.
The destination operand is updated at 32-bit (VMOVDQA32)  or 64-bit (VMOVDQA64) granularity according to the 
VEX.256 encoded version:Moves 256 bits of packed integer values from the sour ce operand (second operand) to the destination operand 
(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the 
contents of a YMM register into a 256-bit memory loca tion, or to move data between two YMM registers. 
When the source or destination operand is a memory oper and, the operand must be aligned on a 32-byte boundary 
or a general-protection exception (#GP) will be generate d. To move integer data to and from unaligned memory 
locations, use the VMOVDQU instruction. Bits (MAX VL-1:256) of the destination register are zeroed.
128-bit versions:Moves 128 bits of packed integer values from the sour ce operand (second operand) to the destination operand 
(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the 
contents of an XMM register into a 128-bit memory lo cation, or to move data between two XMM registers. 
When the source or destination operand is a memory oper and, the operand must be aligned on a 16-byte boundary 
locations, use the VMOVDQU instruction.
VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed.
Operation
VMOVDQA32 (EVEX Encoded Versions, Register-Copy Form)
FI
FI;Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
D Full Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVDQA,VMOVDQA32/64—Move Aligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-67ENDFOR
VMOVDQA32 (EVEX Encoded Versions, Store-Form) 
THEN DEST[i+31:i] := SRC[i+31:i]ELSE *DEST[i+31:i] remains unchanged* ; merging-masking
FI;
ENDFOR;
VMOVDQA32 (EVEX Encoded Versions, Load-Form) 
FI
FI;
VMOVDQA64 (EVEX Encoded Versions, Register-Copy Form)
FI
FI;
VMOVDQA64 (EVEX Encoded Versions, Store-Form) 
THEN DEST[i+63:i] := SRC[i+63:i]ELSE *DEST[i+63:i] remains unchanged* ; merging-masking
FI;
ENDFOR;MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
4-68 Vol. 2BVMOVDQA64 (EVEX Encoded Versions, Load-Form) 
FI
FI;
VMOVDQA (VEX.256 Encoded Version,  Load - and Register Copy)
VMOVDQA (VEX.256 Encoded Version, Store-Form)
VMOVDQA (VEX.128 Encoded Version)
VMOVDQA (128-bit Load- and Register -Copy- Form Legacy SSE Version)
(V)MOVDQA (128-bit Store-Form Version)
VMOVDQA32 __m512i _mm512_load_epi32( void * sa); VMOVDQA32 __m512i _mm512_mask_load_epi32 (__m512i s, __mmask16 k, void * sa);

FI
FI;
VMOVDQA32 __m512i _mm512_load_epi32( void * sa); VMOVDQA32 __m512i _mm512_mask_load_epi32 (__m512i s, __mmask16 k, void * sa); 
VMOVDQA32 __m512i _mm512_maskz_load_epi32( __mmask16 k, void * sa); VMOVDQA32 void _mm512_store_epi32(void * d, __m512i a); VMOVDQA32 void _mm512_mask_store_epi32(void * d, __mmask16 k, __m512i a); VMOVDQA32 __m256i _mm256_mask_load_epi32 (__m256i s, __mmask8 k, void * sa); 
VMOVDQA32 __m256i _mm256_maskz_load_epi32( __mmask8 k, void * sa); VMOVDQA32 void _mm256_store_epi32(void * d, __m256i a); VMOVDQA32 void _mm256_mask_store_epi3 2(void * d, __mmask8 k, __m256i a); 
VMOVDQA32 __m128i _mm_mask_load_epi32(__m128i s, __mmask8 k, void * sa); VMOVDQA32 __m128i _mm_maskz_load_e pi32( __mmask8 k, void * sa); 
VMOVDQA32 void _mm_store_epi32(void * d, __m128i a); VMOVDQA32 void _mm_mask_store_epi32 (void * d, __mmask8 k, __m128i a); 
VMOVDQA64 __m512i _mm512_load_epi64( void * sa); VMOVDQA64 __m512i _mm512_mask_load_epi64 (__m512i s, __mmask8 k, void * sa); 
VMOVDQA64 __m512i _mm512_maskz_load_epi64( __mmask8 k, void * sa); VMOVDQA64 void _mm512_store_epi64(void * d, __m512i a); VMOVDQA64 void _mm512_mask_store_epi6 4(void * d, __mmask8 k, __m512i a); 
VMOVDQA64 __m256i _mm256_mask_load_epi64 (__m256i s, __mmask8 k, void * sa); MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-69VMOVDQA64 __m256i _mm256_maskz_load_epi64( __mmask8 k, void * sa); 
VMOVDQA64 void _mm256_store_epi64(void * d, __m256i a); VMOVDQA64 void _mm256_mask_store_epi64(void * d, __mmask8 k, __m256i a); VMOVDQA64 __m128i _mm_mask_load_epi64(__m 128i s, __mmask8 k, void * sa); 
VMOVDQA64 __m128i _mm_maskz_load_e pi64( __mmask8 k, void * sa); 
VMOVDQA64 void _mm_store_epi64(void * d, __m128i a); VMOVDQA64 void _mm_mask_store_epi64 (void * d, __mmask8 k, __m128i a); 
MOVDQA void __m256i _mm256_load_si256 (__m256i * p);MOVDQA _mm256_store_si256(_m256i *p, __m256i a);MOVDQA __m128i _mm_load_si128 (__m128i * p);MOVDQA void _mm_store_si128(__m128i *p, __m128i a);
None.
#UD If EVEX.vvvv != 1111B  or VEX.vvvv != 1111B.MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
4-70 Vol. 2BMOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values
Opcode/
Mode 
F3 0F 6F /r
MOVDQU xmm1, xmm2/m128A V/V SSE2 Move unaligned packed integer values from 
xmm2/m128 to xmm1. 
F3 0F 7F /r
MOVDQU xmm2/m128, xmm1B V/V SSE2 Move unaligned packed integer values from 
xmm1 to xmm2/m128. 
VEX.128.F3.0F.WIG 6F /r
VMOVDQU xmm1, xmm2/m128A V/V AVX Move unaligned packed integer values from 
VEX.128.F3.0F.WIG 7F /r
VMOVDQU xmm2/m128, xmm1B V/V AVX Move unaligned packed integer values from 
xmm1 to xmm2/m128.
VEX.256.F3.0F.WIG 6F /r
VMOVDQU ymm1, ymm2/m256A V/V AVX Move unaligned packed integer values from 
ymm2/m256 to ymm1.
VEX.256.F3.0F.WIG 7F /r
VMOVDQU ymm2/m256, ymm1B V/V AVX Move unaligned packed integer values from 
ymm1 to ymm2/m256.
EVEX.128.F2.0F.W0 6F /r
VMOVDQU8 xmm1 {k 1}{z}, xmm2/m128CV / V A V X 5 1 2 V L
AVX512BWMove unaligned packed byte integer values from 
xmm2/m128 to xmm1 using writemask k1.
EVEX.256.F2.0F.W0 6F /r
VMOVDQU8 ymm1 {k 1}{z}, ymm2/m256 CV / V A V X 5 1 2 V L
ymm2/m256 to ymm1 using writemask k1.
EVEX.512.F2.0F.W0 6F /r
VMOVDQU8 zmm1 {k1}{z}, zmm2/m512C V/V AVX512BW Move unaligned packed byte integer values from 
zmm2/m512 to zmm1 using writemask k1.
EVEX.128.F2.0F.W0 7F /r
VMOVDQU8 xmm2/m128 {k1}{z}, xmm1DV / V A V X 5 1 2 V L
xmm1 to xmm2/m128 using writemask k1.
EVEX.256.F2.0F.W0 7F /r
VMOVDQU8 ymm2/m256 {k1}{z}, ymm1DV / V A V X 5 1 2 V L
ymm1 to ymm2/m256 using writemask k1.
EVEX.512.F2.0F.W0 7F /r
VMOVDQU8 zmm2/m512 {k1}{z}, zmm1D V/V AVX512BW Move unaligned packed byte integer values from 
zmm1 to zmm2/m512 using writemask k1.
EVEX.128.F2.0F.W1 6F /r
VMOVDQU16 xmm1 {k 1}{z}, xmm2/m128 CV / V A V X 5 1 2 V L
AVX512BWMove unaligned packed word integer values 
EVEX.256.F2.0F.W1 6F /r
VMOVDQU16 ymm1 {k1}{z}, ymm2/m256CV / V A V X 5 1 2 V L
EVEX.512.F2.0F.W1 6F /r
VMOVDQU16 zmm1 {k1}{z}, zmm2/m512 C V/V AVX512BW Move unaligned packed word integer values 
EVEX.128.F2.0F.W1 7F /r
VMOVDQU16 xmm2/m128 {k1}{z}, xmm1DV / V A V X 5 1 2 V L
from xmm1 to xmm2/m128 using writemask k1.
EVEX.256.F2.0F.W1 7F /r
VMOVDQU16 ymm2/m256 {k1}{z}, ymm1DV / V A V X 5 1 2 V L
EVEX.512.F2.0F.W1 7F /r
VMOVDQU16 zmm2/m512 {k1}{z}, zmm1D V/V AVX512BW Move unaligned packed word integer values 
EVEX.128.F3.0F.W0 6F /r
VMOVDQU32 xmm1 {k1}{z}, xmm2/mm128CV / V A V X 5 1 2 V L
AVX512FMove unaligned packed doubleword integer 
values from xmm2/m 128 to xmm1 using 
EVEX.256.F3.0F.W0 6F /r
VMOVDQU32 ymm1 {k1}{z}, ymm2/m256 CV / V A V X 5 1 2 V L
values from ymm2/m256 to ymm1 using 
EVEX.512.F3.0F.W0 6F /r
VMOVDQU32 zmm1 {k1}{z}, zmm2/m512C V/V AVX512F Move unaligned packed doubleword integer 
values from zmm2/m512 to zmm1 using writemask k1.MOVDQU,VMOVDQU8/16/32/64—Move Un aligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-71Instruction Operand Encoding
EVEX encoded versions:Moves 128, 256 or 512 bits of packed byte/word/double word/quadword integer values from the source operand 
(the second operand) to the destination operand (first op erand). This instruction can be used to load a vector 
register from a memory location, to store the contents of a vector register into a memory location, or to move data 
between two vector registers. 
The destination operand is updated at 8-bit (VMOVDQU 8), 16-bit (VMOVDQU16), 32-bit (VMOVDQU32), or 64-bit 
(VMOVDQU64) granularity according to the writemask.
contents of a YMM register into a 256-bit memory lo cation, or to move data between two YMM registers. 
Bits (MAXVL-1:256) of the destination register are zeroed.EVEX.128.F3.0F.W0 7F /r
VMOVDQU32 xmm2/m128 {k1}{z}, xmm1D V/V AVX512VL
values from xmm1 to xmm2/m128 using 
EVEX.256.F3.0F.W0 7F /r
VMOVDQU32 ymm2/m256 {k1}{z}, ymm1D V/V AVX512VL
EVEX.512.F3.0F.W0 7F /r
VMOVDQU32 zmm2/m512 {k1}{z}, zmm1D V/V AVX512F Move unaligned packed doubleword integer 
values from zmm1 to zmm2/m512 using 
EVEX.128.F3.0F.W1 6F /r
VMOVDQU64 xmm1 {k1}{z}, xmm2/m128 C V/V AVX512VL
AVX512FMove unaligned packed quadword integer values 
EVEX.256.F3.0F.W1 6F /r
VMOVDQU64 ymm1 {k1}{z}, ymm2/m256C V/V AVX512VL
EVEX.512.F3.0F.W1 6F /r
VMOVDQU64 zmm1 {k 1}{z}, zmm2/m512C V/V AVX512F Move unaligned packed quadword integer values 
EVEX.128.F3.0F.W1 7F /r
VMOVDQU64 xmm2/m128 {k1}{z}, xmm1D V/V AVX512VL
EVEX.256.F3.0F.W1 7F /r
VMOVDQU64 ymm2/m256 {k1}{z}, ymm1D V/V AVX512VL
EVEX.512.F3.0F.W1 7F /r
VMOVDQU64 zmm2/m512 {k1}{z}, zmm1D V/V AVX512F Move unaligned packed quadword integer values 
D Full Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AOpcode/
Mode 
Feature FlagDescriptionMOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
4-72 Vol. 2B128-bit versions:
Moves 128 bits of packed integer values from the sour ce operand (second operand) to the destination operand

Mode 
Moves 128 bits of packed integer values from the sour ce operand (second operand) to the destination operand 
(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory lo cation, or to move data between two XMM registers. 
128-bit Legacy SSE version: Bits (MAXVL-1:128) of th e corresponding destination register remain unchanged.
When the source or destination operand is a memory op erand, the operand may be unaligned to any alignment 
without causing a general-protection exception (#GP) to be generated
Operation
VMOVDQU8 (EVEX Encoded Versions, Register-Copy Form)
(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1
i := j * 8IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SRC[i+7:i]ELSE 
THEN *DEST[i+7:i] remains unchanged*ELSE  DEST[i+7:i] := 0 ; zeroing-masking
FI
FI;
VMOVDQU8 (EVEX Encoded Versions, Store-Form) 
THEN DEST[i+7:i] := 
SRC[i+7:i]
ELSE *DEST[i+7:i] remains unchanged* ; merging-masking
FI;
ENDFOR;
VMOVDQU8 (EVEX Encoded Versions, Load-Form) 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0MOVDQU,VMOVDQU8/16/32/64—Move Un aligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-73VMOVDQU16 (EVEX Encoded Versions, Register-Copy Form)
(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1
i := j * 16IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SRC[i+15:i]ELSE 
THEN *DEST[i+15:i] remains unchanged*ELSE  DEST[i+15:i] := 0 ; zeroing-masking
FI
FI;
VMOVDQU16 (EVEX Encoded Versions, Store-Form) 
THEN DEST[i+15:i] := 
SRC[i+15:i]
ELSE *DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR;
VMOVDQU16 (EVEX Encoded Versions, Load-Form) 
FI
FI;
VMOVDQU32 (EVEX Encoded Versions, Register-Copy Form)
FI
FI;
ENDFORMOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
4-74 Vol. 2BDEST[MAXVL-1:VL] := 0
VMOVDQU32 (EVEX Encoded Versions, Store-Form) 
FI;
ENDFOR;
VMOVDQU32 (EVEX Encoded Versions, Load-Form) 
FI
FI;
VMOVDQU64 (EVEX Encoded Versions, Register-Copy Form)
FI
FI;
VMOVDQU64 (EVEX Encoded Versions, Store-Form) 
FI;
ENDFOR;MOVDQU,VMOVDQU8/16/32/64—Move Un aligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-75VMOVDQU64 (EVEX Encoded Versions, Load-Form) 
FI
FI;
VMOVDQU (VEX.256 Encoded Version, Load - and Register Copy)
VMOVDQU (VEX.256 Encoded Version, Store-Form)
VMOVDQU (VEX.128 encoded version)
VMOVDQU (128-bit Load- and Register -Copy- Form Legacy SSE Version)
DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128 ] (Unmodified)
(V)MOVDQU (128-bit Store-Form Version)
VMOVDQU16 __m512i _mm512_mask_loadu_epi16(__m512i s, __mmask32 k, void * sa); VMOVDQU16 __m512i _mm512_maskz_loadu_epi16( __mmask32 k, void * sa); VMOVDQU16 void _mm512_mask_storeu_epi16(void * d, __mmask32 k, __m512i a); VMOVDQU16 __m256i _mm256_mask_loadu_epi16(__m256i s, __mmask16 k, void * sa); VMOVDQU16 __m256i _mm256_maskz_loadu_epi16( __mmask16 k, void * sa); VMOVDQU16 void _mm256_mask_storeu_epi16(void * d, __mmask16 k, __m256i a); VMOVDQU16 __m128i _mm_mask_loadu_epi16 (__m128i s, __mmask8 k, void * sa); 
VMOVDQU16 __m128i _mm_maskz_loadu_epi16( __mmask8 k, void * sa); VMOVDQU16 void _mm_mask_storeu_epi16(void * d, __mmask8 k, __m128i a); VMOVDQU32 __m512i _mm512_loadu_epi32( void * sa); VMOVDQU32 __m512i _mm512_mask_loadu_epi32(__m512i s, __mmask16 k, void * sa); VMOVDQU32 __m512i _mm512_maskz_loadu_epi32( __mmask16 k, void * sa); VMOVDQU32 void _mm512_storeu_epi32(void * d, __m512i a); VMOVDQU32 void _mm512_mask_storeu_epi32(void * d, __mmask16 k, __m512i a); VMOVDQU32 __m256i _mm256_mask_loadu_epi32(__m256i s, __mmask8 k, void * sa); VMOVDQU32 __m256i _mm256_maskz_loadu_epi32( __mmask8 k, void * sa); VMOVDQU32 void _mm256_storeu_epi32(void * d, __m256i a); VMOVDQU32 void _mm256_mask_storeu_epi32(void * d, __mmask8 k, __m256i a); VMOVDQU32 __m128i _mm_mask_loadu_epi32 (__m128i s, __mmask8 k, void * sa); MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer ValuesINSTRUCTION SET REFERENCE, M-U
4-76 Vol. 2BVMOVDQU32 __m128i _mm_maskz_loadu_epi32( __mmask8 k, void * sa); 
VMOVDQU32 void _mm_storeu_epi32(void * d, __m128i a); VMOVDQU32 void _mm_mask_storeu_epi32(void * d, __mmask8 k, __m128i a); VMOVDQU64 __m512i _mm512_loadu_epi64( void * sa); VMOVDQU64 __m512i _mm512_mask_loadu_epi64(__m512i s, __mmask8 k, void * sa); VMOVDQU64 __m512i _mm512_maskz_loadu_epi64( __mmask8 k, void * sa); VMOVDQU64 void _mm512_storeu_epi64(void * d, __m512i a); VMOVDQU64 void _mm512_mask_storeu_epi64(void * d, __mmask8 k, __m512i a); VMOVDQU64 __m256i _mm256_mask_loadu_epi64(__m256i s, __mmask8 k, void * sa); VMOVDQU64 __m256i _mm256_maskz_loadu_epi64( __mmask8 k, void * sa); VMOVDQU64 void _mm256_storeu_epi64(void * d, __m256i a); VMOVDQU64 void _mm256_mask_storeu_epi64(void * d, __mmask8 k, __m256i a); VMOVDQU64 __m128i _mm_mask_loadu_epi64 (__m128i s, __mmask8 k, void * sa); 
VMOVDQU64 __m128i _mm_maskz_loadu_epi64( __mmask8 k, void * sa); VMOVDQU64 void _mm_storeu_epi64(void * d, __m128i a); VMOVDQU64 void _mm_mask_storeu_epi64(void * d, __mmask8 k, __m128i a); VMOVDQU8 __m512i _mm512_mask_loadu_epi8(__m512i s, __mmask64 k, void * sa); VMOVDQU8 __m512i _mm512_maskz_loadu_epi8( __mmask64 k, void * sa); VMOVDQU8 void _mm512_mask_storeu_epi 8(void * d, __mmask64 k, __m512i a); 
VMOVDQU8 __m256i _mm256_mask_loadu_epi8(__m256i s, __mmask32 k, void * sa); VMOVDQU8 __m256i _mm256_maskz_loadu_epi8( __mmask32 k, void * sa); VMOVDQU8 void _mm256_mask_storeu_epi 8(void * d, __mmask32 k, __m256i a); 
VMOVDQU8 __m128i _mm_mask_loadu_epi8(__m 128i s, __mmask16 k, void * sa); 
VMOVDQU8 __m128i _mm_maskz_loadu_ep i8( __mmask16 k, void * sa); 
VMOVDQU8 void _mm_mask_storeu_epi8(void * d, __mmask16 k, __m128i a); MOVDQU __m256i _mm256_loadu_si256 (__m256i * p);MOVDQU _mm256_storeu_si256(_m256i *p, __m256i a);MOVDQU __m128i _mm_loadu_si128 (__m128i * p);MOVDQU _mm_storeu_si128(__m128i *p, __m128i a);
None.
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.MOVDQ2Q—Move Quadword from XMM to MMX Technology RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-77MOVDQ2Q—Move Quadword from XMM to MMX Technology Register

None.
Moves the low quadword from the source operand (second op erand) to the destination operand (first operand). The 
source operand is an XMM register and the destination operand is an MMX technology register.
floating-point exception is pending, the exception is  handled before the MOVDQ2Q instruction is executed.
Operation
MOVDQ2Q __m64 _mm_movepi64_pi64 ( __m128i a)
None.
If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.
En64-Bit 
F2 0F D6 /r MOVDQ2Q mm, xmm RM Valid Valid Mov e low quadword from xmm to mmx register.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AMOVHLPS—Move Packed Single Precision Floating-Point Values High to LowINSTRUCTION SET REFERENCE, M-U
4-78 Vol. 2BMOVHLPS—Move Packed Single Precision Fl oating-Point Values High to Low
This instruction cannot be used for memory to register moves.
128-bit two-argument form:Moves two packed single precision floating-point values  from the high quadword of the second XMM argument 
(second operand) to the low quadword of the first XMM regi ster (first argument). The quadword at bits 127:64 of 
the destination operand is left unchanged. Bits (MAXVL-1 :128) of the corresponding destination register remain 
128-bit and EVEX three-argument form:Moves two packed single precision floating-point values fr om the high quadword of the third XMM argument (third 
operand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM 
argument (second operand) to the high quadword of the destination (first operand). Bits (MAXVL-1:128) of the 
corresponding destination register are zeroed.
If VMOVHLPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or 
EVEX.L’L= 1 will cause an #UD exception.
Operation
MOVHLPS (128-bit Two-Argument Form)
DEST[63:0] := SRC[127:64]DEST[MAXVL-1:64] (Unmodified)
VMOVHLPS (128-bit Three-Argument Form - VEX & EVEX)
DEST[63:0] := SRC2[127:64]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)
Mode 
Feature 
NP 0F 12 /r
MOVHLPS xmm1, xmm2RM V/V SSE Move two packed single precision floating-point values from 
high quadword of xmm2 to  low quadword of xmm1.
VEX.128.0F.WIG 12 /r
VMOVHLPS xmm1, xmm2, xmm3RVM V/V AVX Merge two packed single precision floating-point values 
from high quadword of xmm3 and low quadword of xmm2.
EVEX.128.0F.W0 12 /r
VMOVHLPS xmm1, xmm2, xmm3RVM V/V AVX512F Merge two packed single precision floating-point values 
RVM ModRM:reg (w)VEX.vvvv (r) /
EVEX.vvvv (r)ModRM:r/m (r) N/A
1. ModRM.MOD = 011B required.MOVHLPS—Move Packed Single Precision Floating-Point Values High to LowINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-79Other Exceptions
Non-EVEX-encoded instruction, see Table 2-24, “T ype 7 Class Exception Conditions,” additionally:
#UD If VEX.L = 1.EVEX-encoded instruction, see Exceptions Type E7NM.128  in Table 2-55, “Type E7NM Class Exception Conditions.”MOVHPD—Move High Packed Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-80 Vol. 2BMOVHPD—Move High Packed Double Precision Floating-Point Value
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:Moves a double precision floating-point value from the source 64-bit memory operand and stores it in the high 64-
bits of the destination XMM register. The lower 64bits of th e XMM register are preserved. Bits (MAXVL-1:128) of the 
corresponding destination register are preserved.
VEX.128 & EVEX encoded load:Loads a double precision floating-point value from the source 64-bit memory operand (the third operand) and 
stores it in the upper 64-bits of the destination XMM regist er (first operand). The low 64-bits from the first source 
operand (second operand) are copied to the low 64-bits of the destination. Bits (MAXVL-1:128) of the corre-
sponding destination register are zeroed.
128-bit store:Stores a double precision floating-point value from the hi gh 64-bits of the XMM register source (second operand) 
to the 64-bit memory location (first operand).
Note: VMOVHPD (store) (VEX.128.66.0F 17 /r ) is legal and has the same behavior as the existing 66 0F 17 store. 
For VMOVHPD (store) VEX.vvvv and EVEX.vvvv are reserved  and must be 1111b otherwise instruction will #UD.
If VMOVHPD is encoded with VEX.L or EVEX.L’L= 1, an a ttempt to execute the instruction encoded with VEX.L or 
EVEX.L’L= 1 will cause an #UD exception.Opcode/
Mode 
Feature 
66 0F 16 /r
MOVHPD xmm1, m64A V/V SSE2 Move double precision floating-point value from m64 to 
high quadword of xmm1.
VEX.128.66.0F.WIG 16 /r
VMOVHPD xmm2, xmm1, m64B V/V AVX Merge double precision floating-point value from m64 
and the low quadword of xmm1.
EVEX.128.66.0F.W1 16 /r
VMOVHPD xmm2, xmm1, m64D V/V AVX512F Merge double precision floating-point value from m64 
66 0F 17 /r
MOVHPD m64, xmm1C V/V SSE2 Move double precision floating-point value from high 
quadword of xmm1 to m64.
VEX.128.66.0F.WIG 17 /r
VMOVHPD m64, xmm1C V/V AVX Move double precision floating-point value from high 
EVEX.128.66.0F.W1 17 /r
VMOVHPD m64, xmm1E V/V AVX512F Move double precision floating-point value from high 
C N/A ModRM:r/m (w) ModRM:reg (r) N/A N/A
D Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
E Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVHPD—Move High Packed Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-81Operation
MOVHPD (128-bit Legacy SSE Load)
DEST[63:0] (Unmodified)DEST[127:64] := SRC[63:0]DEST[MAXVL-1:128 ] (Unmodified)
VMOVHPD (VEX.128 & EVEX Encoded Load)
DEST[63:0] := SRC1[63:0]DEST[127:64] := SRC2[63:0]DEST[MAXVL-1:128] := 0
VMOVHPD (Store)
DEST[63:0] := SRC[127:64]
MOVHPD __m128d _mm_loadh_pd ( __m128d a, double *p)MOVHPD void _mm_storeh_pd (double *p, __m128d a)
None.
Non-EVEX-encoded instruction, see Table 2-22, “T ype 5 Class Exception Conditions,” additionally:
EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions.”MOVHPS—Move High Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-82 Vol. 2BMOVHPS—Move High Packed Single Precision Floating-Point Values
128-bit Legacy SSE load:Moves two packed single precision floating-point values from the source 64-bit memory operand and stores them 
in the high 64-bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits 
(MAXVL-1:128) of the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:Loads two single precision floating-point values from th e source 64-bit memory operand (the third operand) and 
operand (the second operand) are copied to the lower 64-b its of the destination. Bits (MAXVL-1:128) of the corre-
128-bit store:Stores two packed single precision floating-point values from the high 64-bits of the XMM register source (second 
operand) to the 64-bit memory location (first operand).
Note: VMOVHPS (store) (VEX.128.0F 17 /r) is legal and has the same behavior as the existing 0F 17 store. For

Note: VMOVHPS (store) (VEX.128.0F 17 /r) is legal and has the same behavior as the existing 0F 17 store. For 
VMOVHPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVHPS is encoded with VEX.L or EVEX.L’L= 1, an a ttempt to execute the instruction encoded with VEX.L or 
Mode 
Feature 
NP 0F 16 /r
MOVHPS xmm1, m64A V/V SSE Move two packed single precision floating-point values 
from m64 to high quadword of xmm1.
VEX.128.0F.WIG 16 /r
VMOVHPS xmm2, xmm1, m64B V/V AVX Merge two packed single precision floating-point values 
from m64 and the low quadword of xmm1.
EVEX.128.0F.W0 16 /r
VMOVHPS xmm2, xmm1, m64D V/V AVX512F Merge two packed single precision floating-point values 
NP 0F 17 /r
MOVHPS m64, xmm1C V/V SSE Move two packed single precision floating-point values 
from high quadword of xmm1 to m64.
VEX.128.0F.WIG 17 /r
VMOVHPS m64, xmm1C V/V AVX Move two packed single precision floating-point values 
EVEX.128.0F.W0 17 /r
VMOVHPS m64, xmm1E V/V AVX512F Move two packed single precision floating-point values 
DT u p l e 2 M o d R M : r e g  ( w )E V E X . vvvv (r) ModRM:r/m (r) N/A
E Tuple2 ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVHPS—Move High Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-83Operation
MOVHPS (128-bit Legacy SSE Load)
VMOVHPS (VEX.128 and EVEX Encoded Load)
VMOVHPS (Store)
MOVHPS __m128 _mm_loadh_pi ( __m128 a, __m64 *p)MOVHPS void _mm_storeh_pi (__m64 *p, __m128 a)
None.
EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions.”MOVLHPS—Move Packed Single Precision Floating-Point Values Low to HighINSTRUCTION SET REFERENCE, M-U
4-84 Vol. 2BMOVLHPS—Move Packed Single Precision Floating-Point Values Low to High
128-bit two-argument form:Moves two packed single precision floating-point values  from the low quadword of the second XMM argument 
(second operand) to the high quadword of the first XMM re gister (first argument). The low quadword of the desti-
nation operand is left unchanged. Bits (MAXVL-1:128) of  the corresponding destination register are unmodified.
128-bit three-argument forms:Moves two packed single precision floating-point values from the low quadword of the third XMM argument (third 
operand) to the high quadword of the destination (first  operand). Copies the low quadword from the second XMM 
argument (second operand) to the low quadword of the destination (first operand). Bits (MAXVL-1:128) of the 
If VMOVLHPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or 
Operation
MOVLHPS (128-bit Two-Argument Form)
DEST[63:0] (Unmodified)DEST[127:64] := SRC[63:0]DEST[MAXVL-1:128] (Unmodified)
VMOVLHPS (128-bit Three-Argument Form - VEX & EVEX)
MOVLHPS __m128 _mm_movelh_ps(__m128 a, __m128 b)
Mode 
Feature 
NP 0F 16 /r
MOVLHPS xmm1, xmm2RM V/V SSE Move two packed single precision floating-point values from 
low quadword of xmm2 to high quadword of xmm1.
VMOVLHPS xmm1, xmm2, xmm3RVM V/V AVX Merge two packed single precision floating-point values from 
low quadword of xmm3 and low quadword of xmm2.
VMOVLHPS xmm1, xmm2, xmm3RVM V/V AVX512F Merge two packed single precision floating-point values from 
1. ModRM.MOD = 011B requiredMOVLHPS—Move Packed Single Precision Floating-Point Values Low to HighINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-85Other Exceptions
#UD If VEX.L = 1.EVEX-encoded instruction, see Exceptions Type E7NM.128  in Table 2-55, “Type E7NM Class Exception Conditions.”MOVLPD—Move Low Packed Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-86 Vol. 2BMOVLPD—Move Low Packed Double Pr ecision Floating-Point Value
128-bit Legacy SSE load:Moves a double precision floating-point value from the so urce 64-bit memory operand and stores it in the low 64-
bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits (MAXVL-1:128) of the 
VEX.128 & EVEX encoded load:Loads a double precision floating-point value from the so urce 64-bit memory operand (third operand), merges it 
with the upper 64-bits of the first source XMM register (second operand), and stores it in the low 128-bits of the 
destination XMM register (first operand). Bits (MAXVL-1:1 28) of the corresponding destination register are zeroed.
128-bit store:Stores a double precision floating-point value from the lo w 64-bits of the XMM register source (second operand) to 
the 64-bit memory location (first operand).
Note: VMOVLPD (store) (VEX.128.66.0F 13 /r ) is legal and has the same behavior as the existing 66 0F 13 store. 
For VMOVLPD (store) VEX.vvvv and EVEX.vvvv are reserved  and must be 1111b otherwise instruction will #UD.
If VMOVLPD is encoded with VEX.L or EVEX.L’L= 1, an a ttempt to execute the instruction encoded with VEX.L or 
Operation
MOVLPD (128-bit Legacy SSE Load)
DEST[63:0] := SRC[63:0]DEST[MAXVL-1:64] (Unmodified)Opcode/
Mode 
Feature 
66 0F 12 /r
MOVLPD xmm1, m64A V/V SSE2 Move double precision floating-point value from m64 to 
low quadword of xmm1.
VEX.128.66.0F.WIG 12 /r
VMOVLPD xmm2, xmm1, m64B V/V AVX Merge double precision floating-point value from m64 and 
the high quadword of xmm1.
EVEX.128.66.0F.W1 12 /r
VMOVLPD xmm2, xmm1, m64D V/V AVX512F Merge double precision floating-point value from m64 and 
66 0F 13/r
MOVLPD m64, xmm1C V/V SSE2 Move double precision floating-point value from low 
VEX.128.66.0F.WIG 13/r
VMOVLPD m64, xmm1C V/V AVX Move double precision floating-point value from low 
EVEX.128.66.0F.W1 13/r
VMOVLPD m64, xmm1E V/V AVX512F Move double precision floating-point value from low 
B N/A ModRM:r/m (r) VEX.vvvv (r) ModRM:r/m (r) N/A
E Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVLPD—Move Low Packed Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-87VMOVLPD (VEX.128 & EVEX Encoded Load)
DEST[63:0] := SRC2[63:0]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
VMOVLPD (Store)
MOVLPD __m128d _mm_loadl_pd ( __m128d a, double *p)MOVLPD void _mm_storel_pd (double *p, __m128d a)
None.
EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions.”MOVLPS—Move Low Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-88 Vol. 2BMOVLPS—Move Low Packed Single Pr ecision Floating-Point Values
in the low 64-bits of the destination XMM register. The upper 64bits of the XMM regi ster are preserved. Bits 

None.
VEX.128 & EVEX encoded load:Loads two packed single precision floating-point values  from the source 64-bit memory operand (the third 
operand), merges them with the upper 64-bits of the firs t source operand (the second operand), and stores them 
in the low 128-bits of the destination register (the firs t operand). Bits (MAXVL-1:128) of the corresponding desti-
128-bit store:Loads two packed single precision floating-point values from the low 64-bits of the XMM register source (second 
Note: VMOVLPS (store) (VEX.128.0F 13 /r) is legal and has the same behavior as the existing 0F 13 store. For 
VMOVLPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVLPS is encoded with VEX.L or EVEX.L’L= 1, an a ttempt to execute the instruction encoded with VEX.L or 
Mode 
Feature 
NP 0F 12 /r
MOVLPS xmm1, m64A V/V SSE Move two packed single precision floating-point values from 
m64 to low quadword of xmm1.
VMOVLPS xmm2, xmm1, m64B V/V AVX Merge two packed single precision floating-point values 
from m64 and the high quadword of xmm1.
VMOVLPS xmm2, xmm1, m64D V/V AVX512F Merge two packed single precision floating-point values 
0F 13/r
MOVLPS m64, xmm1C V/V SSE Move two packed single precision floating-point values from 
low quadword of xmm1 to m64.
VEX.128.0F.WIG 13/r
VMOVLPS m64, xmm1C V/V AVX Move two packed single precision floating-point values from 
EVEX.128.0F.W0 13/r
VMOVLPS m64, xmm1E V/V AVX512F Move two packed single precision floating-point values from 
D Tuple2 ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
E Tuple2 ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVLPS—Move Low Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-89Operation
MOVLPS (128-bit Legacy SSE Load)
DEST[63:0] := SRC[63:0]DEST[MAXVL-1:64] (Unmodified)
VMOVLPS (VEX.128 & EVEX Encoded Load)
VMOVLPS (Store)
MOVLPS __m128 _mm_loadl_pi ( __m128 a, __m64 *p)
MOVLPS void _mm_storel_pi (__m64 *p, __m128 a)
None.
#UD If VEX.L = 1.EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions.”MOVMSKPD—Extract Packed Double Pr ecision Floating-Point Sign MaskINSTRUCTION SET REFERENCE, M-U
4-90 Vol. 2BMOVMSKPD—Extract Packed Double Pr ecision Floating-Point Sign Mask
Extracts the sign bits from the packed double precisio n floating-point values in the source operand (second 
operand), formats them into a 2-bit mask, and stores th e mask in the destination op erand (first operand). The 
source operand is an XMM register, and the destination op erand is a general-purpose register. The mask is stored 
in the 2 low-order bits of the destination operan d. Zero-extend the upper bits of the destination.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R 
prefix. The default operand size is 64-bit in 64-bit mode.
128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.
VEX.256 encoded version: The source operand is a YMM register. The destination op erand is a general purpose 
register. 
Operation
(V)MOVMSKPD (128- bit Versions)
DEST[0] := SRC[63]DEST[1] := SRC[127]IF DEST = r32
THEN DEST[31:2] := 0;ELSE DEST[63:2] := 0;
FI
VMOVMSKPD (VEX.256 Encoded Version)
DEST[0] := SRC[63]DEST[1] := SRC[127]DEST[2] := SRC[191]DEST[3] := SRC[255]IF DEST = r32
THEN DEST[31:4] := 0;ELSE DEST[63:4] := 0;
FIOpcode/
ModeCPUID 
Feature 
66 0F 50 /r
MOVMSKPD reg, xmmRM V/V SSE2 Extract 2-bit sign mask from xmm and store in reg. The 
upper bits of r32 or r64 are filled with zeros.
VEX.128.66.0F.WIG 50 /r
VMOVMSKPD reg, xmm2RM V/V AVX Extract 2-bit sign mask from xmm2 and store in reg. 
The upper bits of r32 or r64 are zeroed.
VEX.256.66.0F.WIG 50 /r
VMOVMSKPD reg, ymm2RM V/V AVX Extract 4-bit sign mask from ymm2 and store in reg. 
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AMOVMSKPD—Extract Packed Double Precision Floating-Point Sign MaskINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-91Intel C/C ++ Compiler Intrinsic Equivalent
MOVMSKPD int _mm_movemask_pd ( __m128d a)
VMOVMSKPD _mm256_movemask_pd(__m256d a)
None.
See Table 2-24, “Type 7 Class Exception Conditions,” additionally:
#UD If VEX.vvvv ≠ 1111B.MOVMSKPS—Extract Packed Single Precision Floating-Point Sign MaskINSTRUCTION SET REFERENCE, M-U
4-92 Vol. 2BMOVMSKPS—Extract Packed Single Pr ecision Floating-Point Sign Mask
Extracts the sign bits from the packed single precisio n floating-point values in the source operand (second 
operand), formats them into a 4- or 8-bit mask, and stores the mask in the destination operand (first operand). The 
source operand is an XMM or YMM register, and the destin ation operand is a general-purpose register. The mask is 
stored in the 4 or 8 low-order bits of the destination oper and. The upper bits of the destination operand beyond the 
mask are filled with zeros.
128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register. 
register. 
Operation
DEST[0] := SRC[31]; 
DEST[1] := SRC[63]; DEST[2] := SRC[95]; DEST[3] := SRC[127]; 
IF DEST = r32
THEN DEST[31:4] := ZeroExtend;ELSE DEST[63:4] := ZeroExtend;
ModeCPUID 
Feature 
NP 0F 50 /r
MOVMSKPS reg, xmmRM V/V SSE Extract 4-bit sign mask from xmm and store in reg. 
The upper bits of r32 or r64 are filled with zeros.
VEX.128.0F.WIG 50 /r
VMOVMSKPS reg, xmm2RM V/V AVX Extract 4-bit sign mask from xmm2 and store in reg. 
VEX.256.0F.WIG 50 /r
VMOVMSKPS reg, ymm2RM V/V AVX Extract 8-bit sign mask from ymm2 and store in reg. 
1.ModRM.MOD = 011B requiredMOVMSKPS—Extract Packed Single Pr ecision Floating-Point Sign MaskINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-93(V)MOVMSKPS (128-bit version)
DEST[0] := SRC[31]DEST[1] := SRC[63]DEST[2] := SRC[95]DEST[3] := SRC[127]IF DEST = r32
FI
VMOVMSKPS (VEX.256 encoded version)
DEST[0] := SRC[31]DEST[1] := SRC[63]DEST[2] := SRC[95]DEST[3] := SRC[127]DEST[4] := SRC[159]DEST[5] := SRC[191]DEST[6] := SRC[223]DEST[7] := SRC[255]IF DEST = r32
THEN DEST[31:8] := 0;ELSE DEST[63:8] := 0;
FI
int _mm_movemask_ps(__m128 a)
int _mm256_movemask_ps(__m256 a)
None.
#UD If VEX.vvvv ≠ 1111B.MOVNTDQA—Load Double Quadword Non-Temporal Aligned HintINSTRUCTION SET REFERENCE, M-U
4-94 Vol. 2BMOVNTDQA—Load Double Quadword  Non-Temporal Aligned Hint
MOVNTDQA loads a double quadword from  the source operand (second operand)  to the destination operand (first 
operand) using a non-temporal hint if the memory source  is WC (write combining) memory type. For WC memory 
type, the nontemporal hint may be impl emented by loading a temporary internal  buffer with the equivalent of an 
aligned cache line without filling this data to the cache. Any memory-type aliased lines in the cache will be snooped 
and flushed. Subsequent MOVNTDQA re ads to unread portions of the WC cache line will receive data from the 
temporary internal buffer if data is av ailable. The temporary internal buffer ma y be flushed by the processor at any 
time for any reason, for example:

• A load operation other than a MOVNTDQA which referenc es memory already resident  in a temporary internal 
buffer.
• A non-WC reference to memory already re sident in a temporary internal buffer.
• Interleaving of reads and writes to  a single temporary internal buffer.
• Repeated (V)MOVNTDQA loads of a partic ular 16-byte item in a streaming line.
• Certain micro-architectural conditions including resource shortages, detection ofa mis-speculation condition, and various fault conditionsThe non-temporal hint is implemented by using a write combining (WC) memo ry type protocol when reading the 
data from memory. Using this protocol, the processor does not read the data into the cache hierarchy, nor does it 
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being 
read can override the non-temporal hint, if the memory address specified for the non-temporal read is not a WC 
memory region. Information on non-temporal reads and wr ites can be found in “Caching of Temporal vs. Non-
Temporal Data” in Chapter 10 in the Intel® 64 and IA-3 2 Architecture Software Developer’s Manual, Volume 3A.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with 
a MFENCE instruction should be used in conjunction with MOVNTDQA instructions if multiple processors might use 
different memory types for the referenced memory locations or to synchronize reads of a processor with writes by 
other agents in the system. A processor’s implementation of  the streaming load hint does not override the effective 
memory type, but the implementation of the hint is pr ocessor dependent. For example, a processor implementa-Opcode/
Mode 
66 0F 38 2A /r
MOVNTDQA xmm1, m128A V/V SSE4_1 Move double quadword from m128 to xmm1 using non-
temporal hint if WC memory type.
VEX.128.66.0F38.WIG 2A /r
VMOVNTDQA xmm1, m128A V/V AVX Move double quadword from m128 to xmm using non-
VEX.256.66.0F38.WIG 2A /r
VMOVNTDQA ymm1, m256A V/V AVX2 Move 256-bit data from m256 to ymm using non-temporal 
hint if WC memory type.
EVEX.128.66.0F38.W0 2A /r
VMOVNTDQA xmm1, m128B V/V AVX512VL
AVX512FMove 128-bit data from m128 to xmm using non-temporal 
EVEX.256.66.0F38.W0 2A /r
VMOVNTDQA ymm1, m256B V/V AVX512VL
AVX512FMove 256-bit data from m256 to ymm using non-temporal 
EVEX.512.66.0F38.W0 2A /r
VMOVNTDQA zmm1, m512B V/V AVX512F Move 512-bit data from m512 to zmm using non-temporal 
B Full Mem ModRM:reg (w) ModRM:r/m (r) N/A N/A
1. ModRM.MOD != 011BMOVNTDQA—Load Double Quadword Non-Temporal Aligned HintINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-95tion may choose to ignore the hint and process the instruction as a normal MOVDQA for any memory type. Alter-
natively, another implementation may optimize cache re ads generated by MOVNTDQA on WB memory type to 
reduce cache evictions.
The 128-bit (V)MOVNTDQA addresses must be 16-byte  aligned or the instruction will cause a #GP.
The 256-bit VMOVNTDQA addresses must be 32-byte aligned or the instruction will cause a #GP.The 512-bit VMOVNTDQA addresses must be 64-byte aligned or the instruction will cause a #GP.
Operation
MOVNTDQA (128bit- Legacy SSE Form)
DEST := SRCDEST[MAXVL-1:128 ] (Unmodified)
VMOVNTDQA (VEX.128 and EVEX.128 Encoded Form)
DEST := SRCDEST[MAXVL-1:128] := 0 
VMOVNTDQA (VEX.256 and EVEX.256 Encoded Forms)
VMOVNTDQA (EVEX.512 Encoded Form)
DEST[511:0] := SRC[511:0]DEST[MAXVL-1:512] := 0
VMOVNTDQA __m512i _mm512_stream_load_si512(__m512i const* p);MOVNTDQA __m128i _mm_stream_load_si128 (const __m128i *p);VMOVNTDQA __m256i _mm256_stream_load_si256 (__m256i const* p);
None.
Non-EVEX-encoded instruction, see Table 2-18, “Type 1 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-45, “Type E1NF Class Exception Conditions.”
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.MOVNTDQ—Store Packed Intege rs Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
4-96 Vol. 2BMOVNTDQ—Store Packed Integers  Using Non-Temporal Hint
Moves the packed integers in the source operand (second op erand) to the destination operand (first operand) using 
a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM register, YMM register or ZMM register, which is assumed to contain integer data (packed bytes, words, double-
words, or quadwords). The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory 
operand must be aligned on a 16-byte (128-bit version) , 32-byte (VEX.256 encoded version) or 64-byte (512-bit 
version) boundary otherwise a general-protection exception (#GP) will be generated. 
The non-temporal hint is implemented by using a write combining (WC) memo ry type protocol when writing the 
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it 
written to can override the non-temporal  hint, if the memory address specified for the non-temporal store is in an 
uncacheable (UC) or write protected (WP) memory regi on. For more information on non-temporal stores, see 
“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the IA-32 Intel Architecture Software Developer’s 
the SFENCE or MFENCE instruction should be used in conj unction with VMOVNTDQ instructions if multiple proces-
sors might use different memory types to re ad/write the destination memory locations.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will 
#UD.
Operation
VMOVNTDQ(EVEX Encoded Versions) 
VL = 128, 256, 512DEST[VL-1:0] := SRC[VL-1:0]DEST[MAXVL-1:VL] := 0Opcode/
Mode 
66 0F E7 /r
MOVNTDQ m128, xmm1A V/V SSE2 Move packed integer valu es in xmm1 to m128 using non-
temporal hint.
VEX.128.66.0F.WIG E7 /r
VMOVNTDQ m128, xmm1A V/V AVX Move packed integer values  in xmm1 to m128 using non-
VEX.256.66.0F.WIG E7 /r
VMOVNTDQ m256, ymm1A V/V AVX Move packed integer values  in ymm1 to m256 using non-
EVEX.128.66.0F.W0 E7 /r
VMOVNTDQ m128, xmm1BV / V A V X 5 1 2 V L
AVX512FMove packed integer values in xmm1 to m128 using non-
EVEX.256.66.0F.W0 E7 /r
VMOVNTDQ m256, ymm1BV / V A V X 5 1 2 V L
AVX512FMove packed integer values in zmm1 to m256 using non-
EVEX.512.66.0F.W0 E7 /r
VMOVNTDQ m512, zmm1B V/V AVX512F Move packed integer values in zmm1 to m512 using non-
B Full Mem ModRM:r/m (w) ModRM:reg (r) N/A N/A
1. ModRM.MOD != 011BMOVNTDQ—Store Packed Intege rs Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-97MOVNTDQ (Legacy and VEX Versions)
DEST := SRC
VMOVNTDQ void _mm512_stream_si512(void * p, __m512i a);VMOVNTDQ void _mm256_stream_si256 (__m256i * p, __m256i a);MOVNTDQ void _mm_stream_si128 (__m128i * p, __m128i a);
None.
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.MOVNTI—Store Doubleword Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
4-98 Vol. 2BMOVNTI—Store Doubleword Using Non-Temporal Hint
using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is a 
general-purpose register. The destination operand is a 32-bit memory location.
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being 
uncacheable (UC) or write protected (WP) memory regi on. For more information on non-temporal stores, see

“Caching of Temporal vs. Non-Temporal  Data” in Chapter 10 in the Intel
Developer’s Manual, Volume 1.
the SFENCE or MFENCE instruction should be used in conj unction with MOVNTI instructions if multiple processors 
might use different memory types to read /write the destination memory locations.
Operation
MOVNTI void _mm_stream_si32 (int *p, int a)
MOVNTI void _mm_stream_si64(__int64 *p, __int64 a)
None.
Mode 
Feature 
NP 0F C3 / r
MOVNTI m32 , r32MR V/V SSE2 Move doubleword from r32 to m32  using non-temporal 
hint.
NP REX.W + 0F C3 / r
MOVNTI m64,  r64MR V/N.E. SSE2 Move quadword from r64 to m64  using non-temporal 
hint.
MR ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVNTI—Store Doubleword Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-99Real-Address Mode Exceptions
#PF(fault-code) For a page fault.#UD If CPUID.01H:EDX.SSE2[bit 26] = 0.
current privilege level is 3.MOVNTPD—Store Packed Double Precision Floa ting-Point Values Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
4-100 Vol. 2BMOVNTPD—Store Packed Double Precision Floa ting-Point Values Us ing Non-Temporal Hint
Moves the packed double precision floating-point values in  the source operand (second operand) to the destination 
operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed double preci-
sion, floating-pointing data. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory 
operand must be aligned on a 16-byte (128-bit version) , 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512 
encoded version) boundary otherwise a general-pr otection exception (#GP) will be generated. 
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPD instructions if multiple processors 
#UD.
Operation
VMOVNTPD (EVEX Encoded Versions) 
Mode 
66 0F 2B /r
MOVNTPD m128, xmm1A V/V SSE2 Move packed double precisio n values in xmm1 to m128 using 
non-temporal hint.
VEX.128.66.0F.WIG 2B /r
VMOVNTPD m128, xmm1A V/V AVX Move packed double precision values in xmm1 to m128 using 
VEX.256.66.0F.WIG 2B /r
VMOVNTPD m256, ymm1A V/V AVX Move packed double precision values in ymm1 to m256 using 
EVEX.128.66.0F.W1 2B /r
VMOVNTPD m128, xmm1BV / V A V X 5 1 2 V L
AVX512FMove packed double precision va lues in xmm1 to m128 using 
EVEX.256.66.0F.W1 2B /r
VMOVNTPD m256, ymm1BV / V A V X 5 1 2 V L
AVX512FMove packed double precision va lues in ymm1 to m256 using 
EVEX.512.66.0F.W1 2B /r
VMOVNTPD m512, zmm1B V/V AVX512F Move packed double precision values in zmm1 to m512 using 
1. ModRM.MOD != 011BMOVNTPD—Store Packed Double Precision Floa ting-Point Values Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-101MOVNTPD (Legacy and VEX Versions)
DEST := SRC
VMOVNTPD void _mm512_stream_pd(double * p, __m512d a);VMOVNTPD void _mm256_stream_pd (double * p, __m256d a);MOVNTPD void _mm_stream_pd (double * p, __m128d a);
None.
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.MOVNTPS—Store Packed Single Precision Floa ting-Point Values Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
4-102 Vol. 2BMOVNTPS—Store Packed Single Precision Floati ng-Point Values Using Non-Temporal Hint
Moves the packed single precision floating-point values in  the source operand (second operand) to the destination 
operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed single preci-
sion, floating-pointing. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory 
the SFENCE or MFENCE instruction should be used in conj unction with MOVNTPS instructions if multiple processors 
Operation
VMOVNTPS (EVEX Encoded Versions) 
Mode 
NP 0F 2B /r
MOVNTPS m128, xmm1A V/V SSE Move packed single precision values xmm1 to mem using 
VEX.128.0F.WIG 2B /r
VMOVNTPS m128, xmm1A V/V AVX Move packed single precision values xmm1 to mem using 
VEX.256.0F.WIG 2B /r
VMOVNTPS m256, ymm1A V/V AVX Move packed single precision values ymm1 to mem using 
EVEX.128.0F.W0 2B /r
VMOVNTPS m128, xmm1BV / V A V X 5 1 2 V L
AVX512FMove packed single precision values in xmm1 to m128 using 
EVEX.256.0F.W0 2B /r

Operation
Mode 
NP 0F 2B /r
VMOVNTPS m256, ymm1BV / V A V X 5 1 2 V L
AVX512FMove packed single precision values in ymm1 to m256 using 
EVEX.512.0F.W0 2B /r
VMOVNTPS m512, zmm1B V/V AVX512F Move packed single precision values in zmm1 to m512 using 
1. ModRM.MOD != 011BMOVNTPS—Store Packed Single Precision Floa ting-Point Values Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-103MOVNTPS
DEST := SRC
VMOVNTPS void _mm512_stream_ps(float * p, __m512d a);MOVNTPS void _mm_stream_ps (float * p, __m128d a);
VMOVNTPS void _mm256_stream_ ps (float * p, __m256 a);
None.
Non-EVEX-encoded instruction, see Exceptions Type1.SS E in Table 2-18, “Type 1 Class Exception Conditions.”
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.MOVNTQ—Store of Quadword Using Non-Temporal HintINSTRUCTION SET REFERENCE, M-U
4-104 Vol. 2BMOVNTQ—Store of Quadword Using Non-Temporal Hint
Moves the quadword in the source operand (second operan d) to the destination operand (first operand) using a 
non-temporal hint to minimize cache pollution during the write to memory. The source operand is an MMX tech-
nology register, which is assumed to contain packed in teger data (packed bytes, wo rds, or doublewords). The 
destination operand is a 64-bit memory location.
“Caching of Temporal vs. Non-Temporal  Data” in Chapter 10 in the Intel® 64 and IA-32 Architectures Software 
the SFENCE or MFENCE instruction should  be used in conjunction with MOVNTQ instructions if multiple processors 
Operation
MOVNTQ void _mm_stream_pi(__m64 * p, __m64 a)
None.
and IA-32 Architectures Software Developer’s Manual, Volume 3B.Opcode Instruction Op/ 
En64-Bit 
NP 0F E7 /r MOVNTQ m64, mm MR Valid Valid Mo ve quadword from mm to m64 using non-
MR ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVQ—Move QuadwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-105MOVQ—Move Quadword
Copies a quadword from the source operand (second operand) to the destination operand (first operand). The 
source and destination operands can be MMX technology registers, XMM registers, or 64-bit memory locations. 
This instruction can be used to move a quadword between  two MMX technology registers or between an MMX tech-
nology register and a 64-bit memory location, or to mo ve data between two XMM re gisters or between an XMM 
register and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations. 
When the source operand is an XMM re gister, the low quadword is moved; wh en the destination operand is an XMM 
register, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s.
In 64-bit mode and if not encoded using VEX/EVEX, use of the REX prefix in th e form of REX.R permits this instruc-
tion to access additional registers (XMM8-XMM15).
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.If VMOVQ is encoded with VEX.L= 1, an attempt to exec ute the instruction encoded with VEX.L= 1 will cause an 
#UD exception.
Operation
MOVQ Instruction When Operating on MMX Te chnology Registers and Memory Locations
DEST := SRC;Opcode/
ModeCPUID 
Feature 
NP 0F 6F /r
MOVQ mm, mm/m64AV / VM M X M o v e  q u a d w o r d  from mm/m64 to mm.
NP 0F 7F /r
MOVQ mm/m64, mmBV / VM M X M o v e  q u a d w o r d  from mm to mm/m64.
F3 0F 7E /r
MOVQ xmm1, xmm2/m64A V/V SSE2 Move quadword from xmm2/mem64 to xmm1.
VEX.128.F3.0F.WIG 7E /r
VMOVQ xmm1, xmm2/m64A V/V AVX Move quadword from xmm2 to xmm1.
EVEX.128.F3.0F.W1 7E /r
VMOVQ xmm1, xmm2/m64C V/V AVX512F Move quadword from xmm2/m64 to xmm1.
66 0F D6 /r
MOVQ xmm2/m64, xmm1B V/V SSE2 Move quadword from xmm1 to xmm2/mem64.
VEX.128.66.0F.WIG D6 /r
VMOVQ xmm1/m64, xmm2B V/V AVX Move quadword from xmm2 register to xmm1/m64.
EVEX.128.66.0F.W1 D6 /r
VMOVQ xmm1/m64, xmm2D V/V AVX512F Move quadword from xmm2 register to xmm1/m64.
D Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVQ—Move QuadwordINSTRUCTION SET REFERENCE, M-U
4-106 Vol. 2BMOVQ Instruction When Source and De stination Operands are XMM Registers
DEST[63:0] := SRC[63:0];DEST[127:64] := 0000000000000000H;
MOVQ Instruction When Source Operan d is XMM Register and Destination
operand is memory location:
MOVQ Instruction When Source Operand is Memory Location and Destination
operand is XMM register:
DEST[63:0] := SRC;DEST[127:64] := 0000000000000000H;
VMOVQ (VEX.128.F3.0F 7E) With XMM Register Source and Destination
VMOVQ (VEX.128.66.0F D6) With XMM Register Source and Destination
VMOVQ (7E - EVEX Encoded Version) With  XMM Register Source and Destination
VMOVQ (D6 - EVEX Encoded Version) With XMM Register Source and Destination
VMOVQ (7E) With Memory Source
VMOVQ (7E - EVEX Encoded Version) With Memory Source
DEST[63:0] := SRC[63:0]DEST[:MAXVL-1:64] := 0
VMOVQ (D6) With Memory DEST
DEST[63:0] := SRC2[63:0]
None.
VMOVQ __m128i _mm_loadu_si64( void * s);
VMOVQ void _mm_storeu_si64( void * d, __m128i s);MOVQ m128i _mm_move_epi64(__m128i a)
None.MOVQ—Move QuadwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-107Other Exceptions
and IA-32 Architectures Software Developer’s Manual, Volume 3B.MOVQ2DQ—Move Quadword from MMX Technology to XMM RegisterINSTRUCTION SET REFERENCE, M-U
4-108 Vol. 2BMOVQ2DQ—Move Quadword from MMX Technology to XMM Register
Moves the quadword from the source operand (second oper and) to the low quadword of the destination operand 
(first operand). The source operand is an MMX technology register and the destination operand is an XMM register. 
floating-point exception is pending, the exception is  handled before the MOVQ2DQ instruction is executed.
Operation
DEST[127:64] := 00000000000000000H;
MOVQ2DQ__128i _mm_movpi64_epi64 ( __m64 a)
None.
Same exceptions as in protected mode.Opcode /
ModeCPUID 
Feature 
F3 0F D6 /r
MOVQ2DQ xmm, mmRM V/V SSE2 Move quadword from mmx to low quadword 
of xmm.

Operation
None.
ModeCPUID 
Feature 
F3 0F D6 /r
of xmm.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AMOVQ2DQ—Move Quadword from MMX Technology to XMM RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-10964-Bit Mode Exceptions
Same exceptions as in protected mode.MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—M ove Data From String to StringINSTRUCTION SET REFERENCE, M-U
4-110 Vol. 2BMOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data From String to String
\
Moves the byte, word, or doubleword specified with the se cond operand (source operand) to the location specified 
with the first operand (destination operand). Both the so urce and destination operands are located in memory. The 
address of the source operand is read from the DS:ESI or the DS:SI registers (depending on the address-size attri-
bute of the instruction, 32 or 16, respectively). The addr ess of the destination operand is read from the ES:EDI or 
the ES:DI registers (again depending on the address-size  attribute of the instruction). The DS segment may be 
overridden with a segment override prefix, but the ES segment cannot be overridden.
operands” form. The explicit-operands form (specified with  the MOVS mnemonic) allows the source and destination 
operands to be specified explicitly. He re, the source and destination operands should be symbols that indicate the 
size and location of the source value and the destination, respectively. This explicit-operands form is provided to 
allow documentation; however, note that the documentation provided by this form can be misleading. That is, the 
source and destination operand symbols must specify the correct type (size) of the operands (bytes, words, or 
doublewords), but they do not have to specify the correct location . The locations of the source and destination 
operands are always specified by the DS:(E)SI and ES:(E)DI regist ers, which must be loaded correctly before the 
move string instruction is executed. 
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the MOVS instructions. 
Here also DS:(E)SI and ES:(E)DI are assumed to be the sour ce and destination operands, respectively. The size of 
the source and destination operands is selected with  the mnemonic: MOVSB (byte move), MOVSW (word move), 
or MOVSD (doubleword move).
After the move operation, the (E)SI and (E)DI registers are incremented or decremented automatically according 
to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0,  the (E)SI and (E)DI register are incre-Opcode Instruction Op/ 
En64-Bit 
A4 MOVS m8, m8 ZO Valid Valid For legacy mode, Move byte from address 
DS:(E)SI to ES:(E)DI. For 64-bit mode move 
byte from address (R|E)SI to (R|E)DI.
A5 MOVS m16 , m16 ZO Valid Valid For legacy mode , move word from address 
word at address (R|E)SI to (R|E)DI.
A5 MOVS m32 , m32 ZO Valid Valid For legacy mode, move dword from address 
DS:(E)SI to ES:(E)DI. For 64-bit mode move dword from address (R|E)SI to (R|E)DI.
REX.W + A5 MOVS m64 , m64 ZO Valid N.E. Move qword from address (R|E)SI to (R|E)DI.
A4 MOVSB ZO Valid Valid For legacy mode, Move byte from address 
A5 MOVSW ZO Valid Valid For legacy mode, move word from address 
A5 MOVSD ZO Valid Valid For legacy mode, move dword from address 
dword from address (R|E)SI to (R|E)DI.
REX.W + A5 MOVSQ ZO Valid N.E. Move qwor d from address (R|E)SI to (R|E)DI.
ZO N/A N/A N/A N/AMOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data From String to StringINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-111mented; if the DF flag is 1, the (E)SI and (E)DI regi sters are decremented.) The registers are incremented or 
decremented by 1 for byte operations, by 2 for word  operations, or by 4 for doubleword operations.
NOTE
To improve performance, more recent processors support modifications to the processor’s 
operation during the string store operations init iated with MOVS and MOVSB. See Section 7.3.9.3 
in the Intel® 64 and IA-32 Architectures Software Develo per’s Manual, Volume 1, for additional 
information on fast-string operation.
The MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix (see “REP/REPE/REPZ 
/REPNE/REPNZ—Repeat String Operation Pr efix” for a description of the REP prefix) for block moves of ECX bytes, 
words, or doublewords.
In 64-bit mode, the instruction’s default address size is 64  bits, 32-bit address size is supported using the prefix 
67H. The 64-bit addresses are specified by RSI and RDI; 32 -bit address are specified by ESI and EDI. Use of the 
REX.W prefix promotes doubleword operation to 64 bits. Se e the summary chart at the beginning of this section for 
encoding data and limits.
Operation
Non-64-bit Mode:IF (Byte move)
THEN IF DF 
= 0
THEN 
ELSE 
FI;
ELSE IF (Word move)
THEN IF DF 
= 0
FI;
ELSE 
FI;
ELSE IF (Doubleword move)
THEN IF DF 
= 0
FI;
ELSE 
FI;
FI;64-bit Mode:IF (Byte move)
THEN IF DF 
= 0
THEN 
(R|E)DI := (R|E)DI + 1; MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—M ove Data From String to StringINSTRUCTION SET REFERENCE, M-U
4-112 Vol. 2BELSE 
FI;
THEN IF DF 
= 0
FI;
ELSE 
FI;
THEN IF DF 
= 0
FI;
ELSE 
FI;
ELSE IF (Quadword move)
THEN IF DF
 = 0
(R|E)DI := (R|E)DI + 8;
FI;
ELSE 
FI;
FI;
None.
#SS If a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data From String to StringINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-113Virtual-8086 Mode Exceptions
#UD If the LOCK prefix is used.MOVSD—Move or Merge Scalar Double  Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-114 Vol. 2BMOVSD—Move or Merge Scalar Double  Precision Floating-Point Value
Moves a scalar double precision floating-point value from the source operand (second operand) to the destination 
operand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations. 
This instruction can be used to move a double precision floating-point value to and from the low quadword of an 
XMM register and a 64-bit memory location, or to move a double precision floating-point value between the low 
quadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations.
Legacy version: When the source and destination operands are XMM registers, bits MAXVL:64 of the destination 
operand remains unchanged. When the source operand is a memory location and destination operand is an XMM Opcode/
Mode 
Feature 
F2 0F 10 /r
MOVSD xmm1, xmm2A V/V SSE2 Move scalar double precision floating-point value from

Mode 
Feature 
F2 0F 10 /r
MOVSD xmm1, xmm2A V/V SSE2 Move scalar double precision floating-point value from 
xmm2 to xmm1 register.
F2 0F 10 /r
MOVSD xmm1, m64A V/V SSE2 Load scalar double precision floating-point value from 
m64 to xmm1 register.
F2 0F 11 /r
MOVSD xmm1/m64, xmm2C V/V SSE2 Move scalar double precision floating-point value from 
xmm2 register to xmm1/m64.
VEX.LIG.F2.0F.WIG 10 /r
VMOVSD xmm1, xmm2, xmm3B V/V AVX Merge scalar double precision floating-point value 
from xmm2 and xmm3 to xmm1 register.
VMOVSD xmm1, m64D V/V AVX Load scalar double precision floating-point value from 
VEX.LIG.F2.0F.WIG 11 /r
VMOVSD xmm1, xmm2, xmm3E V/V AVX Merge scalar double precision floating-point value 
from xmm2 and xmm3 registers to xmm1.
VMOVSD m64, xmm1C V/V AVX Store scalar double precision floating-point value from 
xmm1 register to m64.
EVEX.LLIG.F2.0F.W1 10 /r
VMOVSD xmm1 {k1}{z}, xmm2, xmm3B V/V AVX512F Merge scalar double precision floating-point value 
from xmm2 and xmm3 registers to xmm1 under writemask k1.
VMOVSD xmm1 {k1}{z}, m64F V/V AVX512F Load scalar double precision floating-point value from 
m64 to xmm1 register under writemask k1.
EVEX.LLIG.F2.0F.W1 11 /r
VMOVSD xmm1 {k1}{z}, xmm2, xmm3E V/V AVX512F Merge scalar double precision floating-point value 
VMOVSD m64 {k1}, xmm1G V/V AVX512F Store scalar double precision floating-point value from 
xmm1 register to m64 under writemask k1.
D N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
E N/A ModRM:r/m (w) EVEX.vvvv (r) ModRM:reg (r) N/A
F Tuple1 Scalar ModRM:reg (r, w) ModRM:r/m (r) N/A N/A
G Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVSD—Move or Merge Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-115registers, the quadword at bits 127:64 of the destination operand is cleared to all 0s, bits MAXVL:128 of the desti-
nation operand remains unchanged. 
VEX and EVEX encoded register-register syntax: Moves a scalar double precision floating-point value from the 
second source operand (the third operand) to the low quadword element of the destination operand (the first 
operand). Bits 127:64 of the destination operand are copied  from the first source operand (the second operand). 
Bits (MAXVL-1:128) of the corresponding destination register are zeroed.
VEX and EVEX encoded memory store sy ntax: When the source operand is a memory location and destination 
operand is an XMM registers, bits MAXVL:64 of the destination operand is cleared to all 0s.
EVEX encoded versions: The low quadword of the de stination is updated according to the writemask.
Note: For VMOVSD (memory store and load forms), VEX. vvvv and EVEX.vvvv are rese rved and must be 1111b, 
Operation
VMOVSD (EVEX.LLIG.F2.0F 10 /r: VMOVSD xmm1, m64 With Support for 32 Registers)
THEN DEST[63:0] := SRC[63:0]ELSE 
FI;
FI;DEST[MAXVL-1:64] := 0
VMOVSD (EVEX.LLIG.F2.0F 11 /r: VMOVSD m64, xmm1 With Support for 32 Registers)
THEN DEST[63:0] := SRC[63:0]ELSE *DEST[63:0] remains unchanged* ; merging-masking
FI;
VMOVSD (EVEX.LLIG.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)
THEN DEST[63:0] := SRC2[63:0]ELSE 
FI;
MOVSD (128-bit Legacy SSE Version: MOVSD xmm1, xmm2)
VMOVSD (VEX.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)
DEST[63:0] := SRC2[63:0]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0MOVSD—Move or Merge Scalar Double  Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-116 Vol. 2BVMOVSD (VEX.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)
VMOVSD (VEX.128.F2.0F 10 /r: VMOVSD xmm1, m64)
MOVSD/VMOVSD (128-bit Versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)
MOVSD (128-bit Legacy SSE Version: MOVSD xmm1, m64)
DEST[63:0] := SRC[63:0]DEST[127:64] := 0DEST[MAXVL-1:128] (Unmodified)
VMOVSD __m128d _mm_mask_load_sd(__m 128d s, __mmask8 k, double * p); 
VMOVSD __m128d _mm_maskz_load_sd( __mmask8 k, double * p); VMOVSD __m128d _mm_mask_move_sd(__m128d sh, __mmask8 k, __m128d sl, __m128d a); 
VMOVSD __m128d _mm_maskz_move_sd( __mmask8 k, __m128d s, __m128d a); VMOVSD void _mm_mask_store_sd(double * p, __mmask8 k, __m128d s); MOVSD __m128d _mm_load_sd (double *p)MOVSD void _mm_store_sd (double *p, __m128d a)MOVSD __m128d _mm_move_sd ( __m128d a, __m128d b)
None.
EVEX-encoded instruction, see Table 2-58, “Type E10 Class Exception Conditions.”MOVSHDUP—Replicate Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-117MOVSHDUP—Replicate Single Prec ision Floating-Point Values
Duplicates odd-indexed single precision floating-point va lues from the source operand (the second operand) to 
adjacent element pair in the destination operand (the first operand). See Figure 4-3. The source operand is an XMM, YMM or ZMM register or 128, 256 or 512-bit memory  location and the destinatio n operand is an XMM, YMM 
or ZMM register.
VEX.128 encoded version: Bits (MAXVL-1:128 ) of the destination register are zeroed.
VEX.256 encoded version: Bits (MAXVL-1:256 ) of the destination register are zeroed.
EVEX encoded version: The destination operand is upda ted at 32-bit granularity according to the writemask.
Mode 
Feature 
F3 0F 16 /r
MOVSHDUP xmm1, xmm2/m128A V/V SSE3 Move odd index single precision floating-point values from 
xmm2/mem and duplicate each element into xmm1.
VEX.128.F3.0F.WIG 16 /r
VMOVSHDUP xmm1, xmm2/m128A V/V AVX Move odd index single precision floating-point values from 
VEX.256.F3.0F.WIG 16 /r
VMOVSHDUP ymm1, ymm2/m256A V/V AVX Move odd index single precision floating-point values from 
ymm2/mem and duplicate each element into ymm1.
EVEX.128.F3.0F.W0 16 /r
VMOVSHDUP xmm1 {k1}{z}, 
xmm2/m128B V/V AVX512VL
AVX512FMove odd index single precision floating-point values from 
xmm2/m128 and duplicate each element into xmm1 under 
EVEX.256.F3.0F.W0 16 /r
VMOVSHDUP ymm1 {k1}{z}, 
ymm2/m256B V/V AVX512VL
ymm2/m256 and duplicate each element into ymm1 under 
EVEX.512.F3.0F.W0 16 /r
VMOVSHDUP zmm1 {k1}{z}, zmm2/m512B V/V AVX512F Move odd index single precision floating-point values from 
zmm2/m512 and duplicate each element into zmm1 under writemask.
Figure 4-3.  MOVSHDUP OperationDESTSRC X4 X5 X6 X7
X1 X1 X3 X3 X5 X5 X7 X7X0 X1 X2 X3MOVSHDUP—Replicate Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-118 Vol. 2BOperation
VMOVSHDUP (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)TMP_SRC[31:0] := SRC[63:32]TMP_SRC[63:32] := SRC[63:32]TMP_SRC[95:64] := SRC[127:96]TMP_SRC[127:96] := SRC[127:96]IF VL >= 256
TMP_SRC[159:128] := SRC[191:160]TMP_SRC[191:160] := SRC[191:160]TMP_SRC[223:192] := SRC[255:224]TMP_SRC[255:224] := SRC[255:224]
TMP_SRC[287:256] := SRC[319:288]TMP_SRC[319:288] := SRC[319:288]TMP_SRC[351:320] := SRC[383:352]TMP_SRC[383:352] := SRC[383:352]TMP_SRC[415:384] := SRC[447:416]TMP_SRC[447:416] := SRC[447:416]TMP_SRC[479:448] := SRC[511:480]TMP_SRC[511:480] := SRC[511:480]
THEN DEST[i+31:i] := TMP_SRC[i+31:i]ELSE 
DEST[i+31:i] := 0 
FI
FI;
VMOVSHDUP (VEX.256 Encoded Version)
DEST[31:0] := SRC[63:32]DEST[63:32] := SRC[63:32]DEST[95:64] := SRC[127:96]DEST[127:96] := SRC[127:96]DEST[159:128] := SRC[191:160]DEST[191:160] := SRC[191:160]DEST[223:192] := SRC[255:224]DEST[255:224] := SRC[255:224]DEST[MAXVL-1:256] := 0

FI
FI;
VMOVSHDUP (VEX.128 Encoded Version)
DEST[31:0] := SRC[63:32]DEST[63:32] := SRC[63:32]DEST[95:64] := SRC[127:96]DEST[127:96] := SRC[127:96]DEST[MAXVL-1:128] := 0MOVSHDUP—Replicate Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-119MOVSHDUP (128-bit Legacy SSE Version)
DEST[31:0] := SRC[63:32]DEST[63:32] := SRC[63:32]DEST[95:64] := SRC[127:96]DEST[127:96] := SRC[127:96]DEST[MAXVL-1:128 ] (Unmodified)
VMOVSHDUP __m512 _mm512_movehdup_ps( __m512 a);
VMOVSHDUP __m512 _mm512_mask_movehdup_ps(__m512 s, __mmask16 k, __m512 a);VMOVSHDUP __m512 _mm512_maskz_movehdup_ps( __mmask16 k, __m512 a);VMOVSHDUP __m256 _mm256_mask_movehdup _ps(__m256 s, __mmask8 k, __m256 a);
VMOVSHDUP __m256 _mm256_maskz_movehdup_ps( __mmask8 k, __m256 a);VMOVSHDUP __m128 _mm_mask_movehdup_ ps(__m128 s, __mmask8 k, __m128 a);
VMOVSHDUP __m128 _mm_maskz_movehdup_ps( __mmask8 k, __m128 a);VMOVSHDUP __m256 _mm256_movehdup_ps (__m256 a);VMOVSHDUP __m128 _mm_movehdup_ps (__m128 a);
None.
EVEX-encoded instruction, see Exceptions Type E4NF.n b in Table 2-50, “Type E4NF Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B  or VEX.vvvv != 1111B.MOVSLDUP—Replicate Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-120 Vol. 2BMOVSLDUP—Replicate Single Prec ision Floating-Point Values
Duplicates even-indexed single precision floating-point va lues from the source operand (the second operand). See 
Figure 4-4. The source operand is an XMM, YMM or ZMM re gister or 128, 256 or 512-bit memory location and the 
destination operand is an XMM, YMM or ZMM register.
VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed.VEX.256 encoded version: Bits (MAXVL-1:256) of the destination register are zeroed.EVEX encoded version: The destination operand is upda ted at 32-bit granularity according to the writemask.
Mode 
Feature 
F3 0F 12 /r
MOVSLDUP xmm1, xmm2/m128A V/V SSE3 Move even index single precision floating-point values from 
VEX.128.F3.0F.WIG 12 /r
VMOVSLDUP xmm1, xmm2/m128A V/V AVX Move even index single precision floating-point values from 
VEX.256.F3.0F.WIG 12 /r
VMOVSLDUP ymm1, ymm2/m256A V/V AVX Move even index single precision floating-point values from 
EVEX.128.F3.0F.W0 12 /r
VMOVSLDUP xmm1 {k1}{z}, 
xmm2/m128BV / V A V X 5 1 2 V L
AVX512FMove even index single precision floating-point values from 
EVEX.256.F3.0F.W0 12 /r
VMOVSLDUP ymm1 {k1}{z}, 
EVEX.512.F3.0F.W0 12 /r
VMOVSLDUP zmm1 {k1}{z}, zmm2/m512B V/V AVX512F Move even index single precision floating-point values from 
Figure 4-4.  MO VSLDUP OperationDESTSRC X4 X5 X6 X7
X0 X0 X2 X2 X4 X4 X6 X6X0 X1 X2 X3MOVSLDUP—Replicate Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-121Operation
VMOVSLDUP (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)TMP_SRC[31:0] := SRC[31:0]TMP_SRC[63:32] := SRC[31:0]TMP_SRC[95:64] := SRC[95:64]TMP_SRC[127:96] := SRC[95:64]IF VL >= 256
TMP_SRC[159:128] := SRC[159:128]TMP_SRC[191:160] := SRC[159:128]TMP_SRC[223:192] := SRC[223:192]TMP_SRC[255:224] := SRC[223:192]
TMP_SRC[287:256] := SRC[287:256]TMP_SRC[319:288] := SRC[287:256]TMP_SRC[351:320] := SRC[351:320]TMP_SRC[383:352] := SRC[351:320]TMP_SRC[415:384] := SRC[415:384]TMP_SRC[447:416] := SRC[415:384]TMP_SRC[479:448] := SRC[479:448]TMP_SRC[511:480] := SRC[479:448]
FI
FI;
VMOVSLDUP (VEX.256 Encoded Version)
DEST[31:0] := SRC[31:0]DEST[63:32] := SRC[31:0]DEST[95:64] := SRC[95:64]DEST[127:96] := SRC[95:64]DEST[159:128] := SRC[159:128]DEST[191:160] := SRC[159:128]DEST[223:192] := SRC[223:192]DEST[255:224] := SRC[223:192]DEST[MAXVL-1:256] := 0
VMOVSLDUP (VEX.128 Encoded Version)
DEST[31:0] := SRC[31:0]DEST[63:32] := SRC[31:0]DEST[95:64] := SRC[95:64]DEST[127:96] := SRC[95:64]DEST[MAXVL-1:128] := 0MOVSLDUP—Replicate Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-122 Vol. 2BMOVSLDUP (128-bit Legacy SSE Version)
DEST[31:0] := SRC[31:0]DEST[63:32] := SRC[31:0]DEST[95:64] := SRC[95:64]DEST[127:96] := SRC[95:64]DEST[MAXVL-1:128] (Unmodified)
VMOVSLDUP __m512 _mm512_moveldup_ps( __m512 a);VMOVSLDUP __m512 _mm512_mask_moveldup_p s(__m512 s, __mmask16 k, __m512 a);
VMOVSLDUP __m512 _mm512_maskz_moveldup_ps( __mmask16 k, __m512 a);VMOVSLDUP __m256 _mm256_mask_moveldup_ps(__m256 s, __mmask8 k, __m256 a);VMOVSLDUP __m256 _mm256_maskz_moveldup_ps( __mmask8 k, __m256 a);VMOVSLDUP __m128 _mm_mask_moveldup_ps(__m128 s, __mmask8 k, __m128 a);VMOVSLDUP __m128 _mm_maskz_moveldup_ps( __mmask8 k, __m128 a);VMOVSLDUP __m256 _mm256_moveldup_ps (__m256 a);VMOVSLDUP __m128 _mm_moveldup_ps (__m128 a);
None.
#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.MOVSS—Move or Merge Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-123MOVSS—Move or Merge Scalar Single  Precision Floating-Point Value
Moves a scalar single precision floating-point value from the source operand (second operand) to the destination 
operand (first operand). The source and destination operan ds can be XMM registers or 32-bit memory locations. 
This instruction can be used to move a single precision fl oating-point value to and from the low doubleword of an 
XMM register and a 32-bit memory location, or to move a single precision floating-point value between the low 
doublewords of two XMM registers. The instruction cannot be used to transfer data  between memory locations.
Legacy version: When the source and destination operan ds are XMM registers, bits (MAXVL-1:32) of the corre-
sponding destination register are unmodified. When the source operand is a memory location and destination Opcode/
Mode 
Feature 
F3 0F 10 /r
MOVSS xmm1, xmm2A V/V SSE Merge scalar single precision floating-point value from 
F3 0F 10 /r
MOVSS xmm1, m32A V/V SSE Load scalar single precision floating-point value from 
m32 to xmm1 register.
VEX.LIG.F3.0F.WIG 10 /r
VMOVSS xmm1, xmm2, xmm3B V/V AVX Merge scalar single precision floating-point value from 
xmm2 and xmm3 to xmm1 register
VMOVSS xmm1, m32D V/V AVX Load scalar single precision floating-point value from 
F3 0F 11 /r
MOVSS xmm2/m32, xmm1C V/V SSE Move scalar single precision floating-point value from 
xmm1 register to xmm2/m32.
VEX.LIG.F3.0F.WIG 11 /r
VMOVSS xmm1, xmm2, xmm3E V/V AVX Move scalar single precision floating-point value from 
xmm2 and xmm3 to xmm1 register.
VMOVSS m32, xmm1C V/V AVX Move scalar single precision floating-point value from 
xmm1 register to m32.
EVEX.LLIG.F3.0F.W0 10 /r
VMOVSS xmm1 {k1}{z}, xmm2, xmm3B V/V AVX512F Move scalar single precision floating-point value from 
xmm2 and xmm3 to xmm1 register under writemask k1.
VMOVSS xmm1 {k1}{z}, m32F V/V AVX512F Move scalar single prec ision floating-point values from 
m32 to xmm1 under writemask k1.
EVEX.LLIG.F3.0F.W0 11 /r
VMOVSS xmm1 {k1}{z}, xmm2, xmm3E V/V AVX512F Move scalar single precision floating-point value from 
VMOVSS m32 {k1}, xmm1G V/V AVX512F Move scalar single prec ision floating-point values from 
xmm1 to m32 under writemask k1.

G Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVSS—Move or Merge Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-124 Vol. 2Boperand is an XMM registers, Bits (127:32) of the destin ation operand is cleared to all 0s, bits MAXVL:128 of the 
destination operand remains unchanged. 
VEX and EVEX encoded register-register syntax: Moves a scalar single precision floating-point value from the 
second source operand (the third operand) to the low do ubleword element of the destination operand (the first 
operand). Bits 127:32 of the destination operand are copied  from the first source operand (the second operand). 
VEX and EVEX encoded memory load syntax: When the so urce operand is a memory location and destination 
operand is an XMM registers, bits MAXVL:32 of the destination operand is cleared to all 0s.
EVEX encoded versions: The low doubleword of the destination is updated according to the writemask.
Note: For memory store form instruction “VMOVSS m32, xmm1”, VEX.vvvv is reserved and must be 1111b other-
wise instruction will #UD. For memory store form inst ruction “VMOVSS mv {k1}, xmm1”, EVEX.vvvv is reserved 
and must be 1111b otherwise instruction will #UD.
Software should ensure VMOVSS is encoded with VEX.L= 0. Encoding VMOVSS with VEX.L=1 may encounter unpre-
Operation
VMOVSS (EVEX.LLIG.F3.0F.W0 11 /r When the Source Operan d is Memory and the Destination is an XMM Register)
THEN DEST[31:0] := SRC[31:0]ELSE 
FI;
FI;DEST[MAXVL-1:32] := 0
VMOVSS (EVEX.LLIG.F3.0F.W0 10 /r When the Source Operand is an XMM Register and the Destination is Memory)
THEN DEST[31:0] := SRC[31:0]ELSE *DEST[31:0] remains unchanged* ; merging-masking
FI;
VMOVSS (EVEX.LLIG.F3.0F.W0 10/11 /r Where th e Source and Destination are XMM Registers)
THEN DEST[31:0] := SRC2[31:0]ELSE 
FI;
MOVSS (Legacy SSE Version When the Source and Destination Operands are Both XMM Registers)
DEST[31:0] := SRC[31:0]DEST[MAXVL-1:32] (Unmodified)MOVSS—Move or Merge Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-125VMOVSS (VEX.128.F3.0F 11 /r Where th e Destination is an XMM Register)
DEST[31:0] := SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
VMOVSS (VEX.128.F3.0F 10 /r Where the So urce and Destination are XMM Registers)
VMOVSS (VEX.128.F3.0F 10 /r When the Source Operand is Memory and the Destinat ion is an XMM Register)
MOVSS/VMOVSS (When the Source Op erand is an XMM Register and the Destination is Memory)
DEST[31:0] := SRC[31:0]
MOVSS (Legacy SSE Version when the Source Operand is Memory and the Destination is an XMM Register)
DEST[31:0] := SRC[31:0]DEST[127:32] := 0DEST[MAXVL-1:128 ] (Unmodified)
VMOVSS __m128 _mm_mask_load_ss(__m 128 s, __mmask8 k, float * p); 
VMOVSS __m128 _mm_maskz_load_ss( __mmask8 k, float * p); VMOVSS __m128 _mm_mask_move_ss(__m128 sh, __mmask8 k, __m128 sl, __m128 a); VMOVSS __m128 _mm_maskz_move_ss( __mmask8 k, __m128 s, __m128 a); VMOVSS void _mm_mask_store_ss(float * p, __mmask8 k, __m128 a); MOVSS __m128 _mm_load_ss(float * p)MOVSS void_mm_store_ss(float * p, __m128 a)MOVSS __m128 _mm_move_ss(__m128 a, __m128 b)
None.
EVEX-encoded instruction, see Table 2-58, “Type E10 Class Exception Conditions.”MOVSX/MOVSXD—Move With Sign-ExtensionINSTRUCTION SET REFERENCE, M-U
4-126 Vol. 2BMOVSX/MOVSXD—Move With Sign-Extension
Copies the contents of the source operand (register or me mory location) to the destination operand (register) and 
sign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 1). The size of the conver ted value depends on the operand-size attribute.
Operation
DEST := SignExtend(SRC);
None.
En64-Bit 
0F BE /r MOVSX r16, r/m8 RM Valid Valid Move  byte to word wi th sign-extension.
0F BE /r MOVSX r32, r/m8 RM Valid Valid Mo ve byte to doubleword with sign-
extension.
REX.W + 0F BE /r MOVSX r64, r/m8 RM Valid N.E. M ove byte to quadword with sign-extension.
0F BF /r MOVSX r32, r/m16 RM Valid Valid Move word to doubleword, with sign-
REX.W + 0F BF /r MOVSX r64, r/m16 RM Valid N.E. Move word to quadword with sign-extension.63 /r
1
NOTES:
1. The use of MOVSXD without REX.W in 64-b it mode is discouraged. Regular MOV should be used instead of using MOVSXD without 
REX.W. MOVSXD r16, r/m16 RM Valid N.E. Move word to word with sign-extension.
63 /r1MOVSXD r32, r/m32 RM Valid N.E. Move do ubleword to doubleword with sign-
REX.W + 63 /r MOVSXD r64, r/m32 RM Valid N.E. Move doubleword to quadword with sign-
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AMOVSX/MOVSXD—Move With Sign-ExtensionINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-127Real-Address Mode Exceptions
#UD If the LOCK prefix is used.MOVUPD—Move Unaligned Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-128 Vol. 2BMOVUPD—Move Unaligned Packed Double Precision Floating-Point Values
Note: VEX.vvvv and EVEX.vvvv is reserved and mu st be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:Moves 512 bits of packed double precision floating-point values from the source oper and (second operand) to the 
destination operand (first operand). This instruction can be used to load a ZMM register from a float64 memory 
location, to store the contents of a ZMM register into a memory. The destination operand is updated according to 
the writemask.Opcode/
Mode 
Feature 
66 0F 10 /r
MOVUPD xmm1, xmm2/m128A V/V SSE2 Move unaligned packed double precision floating-
point from xmm2/mem to xmm1.
66 0F 11 /r
MOVUPD xmm2/m128, xmm1B V/V SSE2 Move unaligned packed double precision floating-
point from xmm1  to xmm2/mem.
VEX.128.66.0F.WIG 10 /r
VMOVUPD xmm1, xmm2/m128A V/V AVX Move unaligned packed double precision floating-
VEX.128.66.0F.WIG 11 /r
VMOVUPD xmm2/m128, xmm1B V/V AVX Move unaligned packed double precision floating-
VEX.256.66.0F.WIG 10 /r
VMOVUPD ymm1, ymm2/m256A V/V AVX Move unaligned packed double precision floating-
point from ymm2/mem to ymm1.
VEX.256.66.0F.WIG 11 /r

Mode 
Feature 
66 0F 10 /r
66 0F 11 /r
VMOVUPD ymm2/m256, ymm1B V/V AVX Move unaligned packed double precision floating-
point from ymm1 to ymm2/mem.
EVEX.128.66.0F.W1 10 /r
VMOVUPD xmm1 {k1}{z}, xmm2/m128C V/V AVX512VL
AVX512FMove unaligned packed double precision floating-
point from xmm2/m128 to xmm1 using writemask 
k1.
EVEX.128.66.0F.W1 11 /r
VMOVUPD xmm2/m128 {k1}{z}, xmm1D V/V AVX512VL
point from xmm1 to xm m2/m128 using writemask 
k1.
EVEX.256.66.0F.W1 10 /r
VMOVUPD ymm1 {k1 }{z}, ymm2/m256C V/V AVX512VL
point from ymm2/m256 to ymm1 using writemask k1.
EVEX.256.66.0F.W1 11 /r
VMOVUPD ymm2/m256 {k1}{z}, ymm1D V/V AVX512VL
point from ymm1 to ym m2/m256 using writemask 
k1.
EVEX.512.66.0F.W1 10 /r
VMOVUPD zmm1 {k1} {z}, zmm2/m512C V/V AVX512F Move unaligned packed double precision floating-
point values from zmm2/m512 to zmm1 using 
EVEX.512.66.0F.W1 11 /r
VMOVUPD zmm2/m512 {k1}{z}, zmm1D V/V AVX512F Move unaligned packed double precision floating-
D Full Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVUPD—Move Unaligned Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-129VEX.256 encoded version:
Moves 256 bits of packed double precision floating-point values from the source operand (second operand) to the 
registers. Bits (MAXVL-1:256) of the destination register are zeroed.
128-bit versions:
Moves 128 bits of packed double precision floating-point values from the source operand (second operand) to the 
When the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte 
boundary without causing a general-protection exception (#GP) to be generated
VEX.128 and EVEX.128 encoded versions: Bits (MAXVL -1:128) of the destination register are zeroed.
Operation
VMOVUPD (EVEX Encoded Versions, Register-Copy Form)
FI
FI;
VMOVUPD (EVEX Encoded Versions, Store-Form) 
FI;
ENDFOR;MOVUPD—Move Unaligned Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-130 Vol. 2BVMOVUPD (EVEX Encoded Versions, Load-Form) 
FI
FI;
VMOVUPD (VEX.256 Encoded Version, Load - and Register Copy)
VMOVUPD (VEX.256 Encoded Version, Store-Form)
VMOVUPD (VEX.128 Encoded Version)
MOVUPD (128-bit Load- and Register -Copy- Form Legacy SSE Version)
(V)MOVUPD (128-bit Store-Form Version)
VMOVUPD __m512d _mm512_loadu_pd( void * s);VMOVUPD __m512d _mm512_mask_loadu_pd(__m512d a, __mmask8 k, void * s);VMOVUPD __m512d _mm512_maskz_loadu_pd( __mmask8 k, void * s);VMOVUPD void _mm512_storeu_pd( void * d, __m512d a);VMOVUPD void _mm512_mask_storeu_pd( void * d, __mmask8 k, __m512d a);VMOVUPD __m256d _mm256_mask_loadu_pd(__m256d s, __mmask8 k, void * m);VMOVUPD __m256d _mm256_maskz_loadu_pd( __mmask8 k, void * m);VMOVUPD void _mm256_mask_storeu_pd( void * d, __mmask8 k, __m256d a);VMOVUPD __m128d _mm_mask_loadu_pd(__m128d s, __mmask8 k, void * m);VMOVUPD __m128d _mm_maskz_loadu_pd( __mmask8 k, void * m);VMOVUPD void _mm_mask_storeu_pd( vo id * d, __mmask8 k, __m128d a);
MOVUPD __m256d _mm256_loadu_pd (double * p);MOVUPD void _mm256_storeu_pd( double *p, __m256d a);MOVUPD __m128d _mm_loadu_pd (double * p);MOVUPD void _mm_storeu_pd( double *p, __m128d a);
None.MOVUPD—Move Unaligned Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-131Other Exceptions
Note treatment of #AC varies; additionally:#UD If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”MOVUPS—Move Unaligned Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-132 Vol. 2BMOVUPS—Move Unaligned Packed Single  Precision Floating-Point Values
EVEX.512 encoded version:Moves 512 bits of packed single precision floating-point values from the source operand (second operand) to the 
memory location, to store the contents of a ZMM regi ster into memory. The destination operand is updated 
according to the writemask.Opcode/
Mode 
Feature 
NP 0F 10 /r
MOVUPS xmm1, xmm2/m128A V/V SSE Move unaligned packed single precision floating-
NP 0F 11 /r
MOVUPS xmm2/m128, xmm1B V/V SSE Move unaligned packed single precision floating-
point from xmm1 to xmm2/mem.
VEX.128.0F.WIG 10 /r
VMOVUPS xmm1, xmm2/m128A V/V AVX Move unaligned packed single precision floating-
VEX.128.0F.WIG 11 /r
VMOVUPS xmm2/m128, xmm1B V/V AVX Move unaligned packed single precision floating-
VEX.256.0F.WIG 10 /r
VMOVUPS ymm1, ymm2/m256A V/V AVX Move unaligned packed single precision floating-
VEX.256.0F.WIG 11 /r
VMOVUPS ymm2/m256, ymm1B V/V AVX Move unaligned packed single precision floating-
EVEX.128.0F.W0 10 /r
VMOVUPS xmm1 {k1} {z}, xmm2/m128C V/V AVX512VL
AVX512FMove unaligned packed single precision floating-
EVEX.256.0F.W0 10 /r
VMOVUPS ymm1 {k1}{z}, ymm2/m256C V/V AVX512VL
point values from ymm2 /m256 to ymm1 using 
EVEX.512.0F.W0 10 /r
VMOVUPS zmm1 {k1}{z}, zmm2/m512C V/V AVX512F Move unaligned packed single precision floating-
EVEX.128.0F.W0 11 /r
VMOVUPS xmm2/m1 28 {k1}{z}, xmm1D V/V AVX512VL
EVEX.256.0F.W0 11 /r
VMOVUPS ymm2/m256 {k1}{z}, ymm1D V/V AVX512VL
point values from ymm1  to ymm2/m256 using 
EVEX.512.0F.W0 11 /r
VMOVUPS zmm2/m512 {k1}{z}, zmm1D V/V AVX512F Move unaligned packed single precision floating-
point values from zmm1  to zmm2/m512 using 
D Full Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AMOVUPS—Move Unaligned Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-133VEX.256 and EVEX.256 encoded versions:
Moves 256 bits of packed single precision floating-point values from the source operand (second operand) to the 

When the source or destination operand is a memory op erand, the operand may be unaligned without causing a 
general-protection exception (#GP) to be generated.
Operation
VMOVUPS (EVEX Encoded Versions, Register-Copy Form)
FI
FI;
VMOVUPS (EVEX Encoded Versions, Store-Form) 
FI;
ENDFOR;MOVUPS—Move Unaligned Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-134 Vol. 2BVMOVUPS (EVEX Encoded Versions, Load-Form) 
FI
FI;
VMOVUPS (VEX.256 Encoded Version, Load - and Register Copy)
VMOVUPS (VEX.256 Encoded Version, Store-Form)
VMOVUPS (VEX.128 Encoded Version)
MOVUPS (128-bit Load- and Register -Copy- Form Legacy SSE Version)
(V)MOVUPS (128-bit Store-Form Version)
VMOVUPS __m512 _mm512_loadu_ps( void * s);VMOVUPS __m512 _mm512_mask_loadu_ps(__m512 a, __mmask16 k, void * s);VMOVUPS __m512 _mm512_maskz_loadu_ps( __mmask16 k, void * s);VMOVUPS void _mm512_storeu_ps( void * d, __m512 a);VMOVUPS void _mm512_mask_storeu_ps(  void * d, __mmask8 k, __m512 a);
VMOVUPS __m256 _mm256_mask_loadu_ps(__m256 a, __mmask8 k, void * s);VMOVUPS __m256 _mm256_maskz_loadu_ps( __mmask8 k, void * s);VMOVUPS void _mm256_mask_storeu_ps(  void * d, __mmask8 k, __m256 a);
VMOVUPS __m128 _mm_mask_loadu_ps(__ m128 a, __mmask8 k, void * s);
VMOVUPS __m128 _mm_maskz_loadu_ps( __mmask8 k, void * s);VMOVUPS void _mm_mask_storeu_ps( void * d, __mmask8 k, __m128 a);MOVUPS __m256 _mm256_loadu_ps ( float * p);MOVUPS void _mm256 _storeu_ps( float *p, __m256 a);MOVUPS __m128 _mm_loadu_ps ( float * p);MOVUPS void _mm_storeu_ps( float *p, __m128 a);
None.MOVUPS—Move Unaligned Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-135Other Exceptions
Note treatment of #AC varies. 
#UD If EVEX.vvvv != 1111B  or VEX.vvvv != 1111B.MOVZX—Move With Zero-ExtendINSTRUCTION SET REFERENCE, M-U
4-136 Vol. 2BMOVZX—Move With Zero-Extend
zero extends the value. The size of the conver ted value depends on the operand-size attribute.
tional registers (R8-R15). Use of the REX.W prefix promot es operation to 64 bit operands. See the summary chart 
Operation
DEST := ZeroExtend(SRC);
None.
#SS If a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.Opcode Instruction Op/ 
En64-Bit 
0F B6 /r MOVZX r16, r/m8 RM Valid Valid Move  byte to word wi th zero-extension.
0F B6 /r MOVZX r32, r/m8 RM Valid Valid Move  byte to doubleword, zero-extension.
REX.W + 0F B6 /r MOVZX r64, r/m8
1
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte registers if the REX prefix is used: AH, BH, CH, DH.RM Valid N.E. Move byte to quadword, zero-extension.
0F B7 /r MOVZX r32, r/m16 RM Valid Valid Move word to doubleword, zero-extension.REX.W + 0F B7 /r MOVZX r64, r/m16 RM Valid N. E. Move word to quadword, zero-extension.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AMOVZX—Move With Zero-ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-137Virtual-8086 Mode Exceptions
#UD If the LOCK prefix is used.MPSADBW—Compute Multiple Packed Sums of Absolute DifferenceINSTRUCTION SET REFERENCE, M-U
4-138 Vol. 2BMPSADBW—Compute Multiple Packed  Sums of Absolute Difference
(V)MPSADBW calculates packed word results of sum-absolu te-difference (SAD) of unsign ed bytes from two blocks 
of 32-bit dword elements, using two select fields in the imme diate byte to select the offsets of the two blocks within 
the first source operand and the second operand. Packed SA D word results are calculated within each 128-bit lane. 
Each SAD word result is calculated between a stationary block_2 (whose offset within the second source operand 
is selected by a two bit select control, multiplied by 32 bits) and a sliding block_1 at consecutive byte-granular posi-
tion within the first source operand. The offset of the firs t 32-bit block of block_1 is selectable using a one bit select 
control, multiplied by 32 bits.
128-bit Legacy SSE version: Imm8[1:0]*32 specifies the bi t offset of block_2 within the second source operand. 
Imm[2]*32 specifies the initial bit offset of the block_1 wi thin the first source operand. The first source operand 
and destination operand are the same. The first source an d destination operands are XMM registers. The second 
source operand is either an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding 
YMM destination register remain unchanged. Bits 7:3 of the immediate byte are ignored.
VEX.128 encoded version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand. 
Imm[2]*32 specifies the initial bit offset of the block_1 wi thin the first source operand. The first source and desti-
nation operands are XMM registers. The second source op erand is either an XMM register or a 128-bit memory 
location. Bits (127:128) of the corresponding YMM register  are zeroed. Bits 7:3 of the immediate byte are ignored.
VEX.256 encoded version: The sum-absolute-difference (SAD) operation is repeated 8 times for MPSADW between 
the same block_2 (fixed offset within the second source op erand) and a variable block_1 (offset is shifted by 8 bits 
for each SAD operation) in the first source operand. Ea ch 16-bit result of eight SAD operations between block_2 
and block_1 is written to the respective word in  the lower 128 bits of the destination operand. 
Additionally, VMPSADBW performs another eight SAD oper ations on block_4 of the second source operand and

Additionally, VMPSADBW performs another eight SAD oper ations on block_4 of the second source operand and 
block_3 of the first source operand. (Imm8[4:3]*32 + 128)  specifies the bit offset of block_4 within the second 
source operand. (Imm[5]*32+128) specifies the initial bit of fset of the block_3 within the first source operand. 
Each 16-bit result of eight SAD operations between block _4 and block_3 is written to the respective word in the 
upper 128 bits of the destination operand. Opcode/
ModeCPUID 
Feature 
66 0F 3A 42 /r ib
MPSADBW xmm1, xmm2/m128, imm8RMI V/V SSE4_1 Sums absolute 8-bit integer difference of 
adjacent groups of 4 byte integers in xmm1 
and xmm2/m128 and writes the results in 
xmm1. Starting offsets within xmm1 and xmm2/m128 are determined by imm8.
VEX.128.66.0F3A.WIG 42 /r ib
VMPSADBW xmm1, xmm2, xmm3/m128, imm8RVMI V/V AVX Sums absolute 8- bit integer difference of 
adjacent groups of 4 byte integers in xmm2 
and xmm3/m128 and writes the results in xmm1. Starting offsets within xmm2 and 
xmm3/m128 are determined by imm8.
VEX.256.66.0F3A.WIG 42 /r ib
VMPSADBW ymm1, ymm2, ymm3/m256, imm8RVMI V/V AVX2 Sums absolute 8- bit integer difference of 
and ymm3/m128 and writes the results in 
ymm1. Starting offsets within ymm2 and xmm3/m128 are determined by imm8.
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8MPSADBW—Compute Multiple Packed Sums of Absolute DifferenceINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-139The first source operand is a YMM register. The second sour ce register can be a YMM register or a 256-bit memory 
location. The destination operand is a YMM register. Bits 7:6 of the immediate byte are ignored.
Note: If VMPSADBW is encoded with VE X.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will 
Operation
VMPSADBW (VEX.256 Encoded Version)
BLK2_OFFSET :=  imm8[1:0]*32
BLK1_OFFSET :=  imm8[2]*32
SRC1_BYTE0 := SRC1[BLK1_OFFSET+7:BLK1_OFFSET]SRC1_BYTE1 := SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]SRC1_BYTE2 := SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]SRC1_BYTE3 := SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]SRC1_BYTE4 := SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]SRC1_BYTE5 := SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]Figure 4-5.  256-bit VMPSADBW OperationAbs. Diff.
SumImm[4:3]*32+128
Imm[5]*32+128Src2
Src1
128 255 144128 255 224 192
Abs. Diff.
Imm[2]*32Src2
Destination0 127 160 127 96 64Destination
Src1MPSADBW—Compute Multiple Packed Sums of Absolute DifferenceINSTRUCTION SET REFERENCE, M-U
4-140 Vol. 2BSRC1_BYTE6 := SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
SRC1_BYTE7 := SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]SRC1_BYTE8 := SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]SRC1_BYTE9 := SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]SRC1_BYTE10 := SRC1[BLK1_ OFFSET+87:BLK1_OFFSET+80]
SRC2_BYTE0 := SRC2[BLK2_OFFSET+7:BLK2_OFFSET]SRC2_BYTE1 := SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]SRC2_BYTE2 := SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]SRC2_BYTE3 := SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]
TEMP0 := ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 := ABS(SRC1_BYTE1 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE2 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE3 - SRC2_BYTE3)DEST[15:0] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 := ABS(SRC1_BYTE2 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE3 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE4 - SRC2_BYTE3)DEST[31:16] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 := ABS(SRC1_BYTE3 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE4 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE5 - SRC2_BYTE3)DEST[47:32] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 := ABS(SRC1_BYTE4 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE5 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE6 - SRC2_BYTE3)DEST[63:48] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 := ABS(SRC1_BYTE5 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE6 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE7 - SRC2_BYTE3)DEST[79:64] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 := ABS(SRC1_BYTE6 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE7 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE8 - SRC2_BYTE3)DEST[95:80] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 := ABS(SRC1_BYTE7 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE8 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE9 - SRC2_BYTE3)DEST[111:96] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 := ABS(SRC1_BYTE8 - SRC2_BYTE1)MPSADBW—Compute Multiple Packed Sums of Absolute DifferenceINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-141TEMP2 := ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 := ABS(SRC1_BYTE10 - SRC2_BYTE3)DEST[127:112] := TEMP0 + TEMP1 + TEMP2 + TEMP3
BLK2_OFFSET := imm8[4:3]*32 + 128
BLK1_OFFSET := im m8[5]*32 + 128
SRC1_BYTE0 := SRC1[BLK1_OFFSET+7:BLK1_OFFSET]SRC1_BYTE1 := SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]SRC1_BYTE2 := SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]SRC1_BYTE3 := SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]SRC1_BYTE4 := SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]SRC1_BYTE5 := SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]SRC1_BYTE6 := SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]SRC1_BYTE7 := SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]SRC1_BYTE8 := SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]SRC1_BYTE9 := SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]SRC1_BYTE10 := SRC1[BLK1_ OFFSET+87:BLK1_OFFSET+80]
SRC2_BYTE0 := SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
SRC2_BYTE1 := SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]SRC2_BYTE2 := SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]SRC2_BYTE3 := SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]
TEMP1 := ABS(SRC1_BYTE1 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE2 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE3 - SRC2_BYTE3)DEST[143:128] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP1 := ABS(SRC1_BYTE2 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE3 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE4 - SRC2_BYTE3)DEST[159:144] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP1 := ABS(SRC1_BYTE3 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE4 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE5 - SRC2_BYTE3)DEST[175:160] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP1 := ABS(SRC1_BYTE4 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE5 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE6 - SRC2_BYTE3)DEST[191:176] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP1 := ABS(SRC1_BYTE5 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE6 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE7 - SRC2_BYTE3)DEST[207:192] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS(SRC1_BYTE5 - SRC2_BYTE0)MPSADBW—Compute Multiple Packed Sums of Absolute DifferenceINSTRUCTION SET REFERENCE, M-U
4-142 Vol. 2BTEMP1 := ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 := ABS(SRC1_BYTE7 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE8 - SRC2_BYTE3)DEST[223:208] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP1 := ABS(SRC1_BYTE7 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE8 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE9 - SRC2_BYTE3)DEST[239:224] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP1 := ABS(SRC1_BYTE8 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE9 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE10 - SRC2_BYTE3)DEST[255:240] := TEMP0 + TEMP1 + TEMP2 + TEMP3
VMPSADBW (VEX.128 Encoded Version)
TEMP1 := ABS(SRC1_BYTE3 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE4 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE5 - SRC2_BYTE3)DEST[47:32] := TEMP0 + TEMP1 + TEMP2 + TEMP3MPSADBW—Compute Multiple Packed Sums of Absolute DifferenceINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-143TEMP0 := ABS(SRC1_BYTE3 - SRC2_BYTE0)

TEMP1 := ABS(SRC1_BYTE8 - SRC2_BYTE1)TEMP2 := ABS(SRC1_BYTE9 - SRC2_BYTE2)TEMP3 := ABS(SRC1_BYTE10 - SRC2_BYTE3)DEST[127:112] := TEMP0 + TEMP1 + TEMP2 + TEMP3DEST[MAXVL-1:128] := 0
MPSADBW (128-bit Legacy SSE Version)
SRC_OFFSET := imm8[1:0]*32DEST_OFFSET := imm8[2]*32DEST_BYTE0 := DEST[DEST_OFFSET+7:DEST_OFFSET]DEST_BYTE1 := DEST[DEST_OFFSET+15:DEST_OFFSET+8]DEST_BYTE2 := DEST[DEST_OFFSET+23:DEST_OFFSET+16]DEST_BYTE3 := DEST[DEST_OFFSET+31:DEST_OFFSET+24]DEST_BYTE4 := DEST[DEST_OFFSET+39:DEST_OFFSET+32]DEST_BYTE5 := DEST[DEST_OFFSET+47:DEST_OFFSET+40]DEST_BYTE6 := DEST[DEST_OFFSET+55:DEST_OFFSET+48]DEST_BYTE7 := DEST[DEST_OFFSET+63:DEST_OFFSET+56]DEST_BYTE8 := DEST[DEST_OFFSET+71:DEST_OFFSET+64]DEST_BYTE9 := DEST[DEST_OFFSET+79:DEST_OFFSET+72]DEST_BYTE10 := DEST[DEST_OFFSET+87:DEST_OFFSET+80]
SRC_BYTE0 := SRC[SRC_OFFSET+7:SRC_OFFSET]
SRC_BYTE1 := SRC[SRC_OFFSET+15:SRC_OFFSET+8]SRC_BYTE2 := SRC[SRC_OFFSET+23:SRC_OFFSET+16]SRC_BYTE3 := SRC[SRC_OFFSET+31:SRC_OFFSET+24]
TEMP0 := ABS( DEST_BYTE0 - SRC_BYTE0) 
TEMP1 := ABS( DEST_BYTE1 - SRC_BYTE1) TEMP2 := ABS( DEST_BYTE2 - SRC_BYTE2) MPSADBW—Compute Multiple Packed Sums of Absolute DifferenceINSTRUCTION SET REFERENCE, M-U
4-144 Vol. 2BTEMP3 := ABS( DEST_BYTE3 - SRC_BYTE3) 
DEST[15:0] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS( DEST_BYTE1 - SRC_BYTE0) 
TEMP1 := ABS( DEST_BYTE2 - SRC_BYTE1) TEMP2 := ABS( DEST_BYTE3 - SRC_BYTE2) TEMP3 := ABS( DEST_BYTE4 - SRC_BYTE3) DEST[31:16] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS( DEST_BYTE2 - SRC_BYTE0) 
TEMP1 := ABS( DEST_BYTE3 - SRC_BYTE1) TEMP2 := ABS( DEST_BYTE4 - SRC_BYTE2) TEMP3 := ABS( DEST_BYTE5 - SRC_BYTE3) DEST[47:32] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS( DEST_BYTE3 - SRC_BYTE0) 
TEMP1 := ABS( DEST_BYTE4 - SRC_BYTE1) TEMP2 := ABS( DEST_BYTE5 - SRC_BYTE2) TEMP3 := ABS( DEST_BYTE6 - SRC_BYTE3) DEST[63:48] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS( DEST_BYTE4 - SRC_BYTE0) 
TEMP1 := ABS( DEST_BYTE5 - SRC_BYTE1) TEMP2 := ABS( DEST_BYTE6 - SRC_BYTE2) TEMP3 := ABS( DEST_BYTE7 - SRC_BYTE3) DEST[79:64] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS( DEST_BYTE5 - SRC_BYTE0) 
TEMP1 := ABS( DEST_BYTE6 - SRC_BYTE1) TEMP2 := ABS( DEST_BYTE7 - SRC_BYTE2) TEMP3 := ABS( DEST_BYTE8 - SRC_BYTE3) DEST[95:80] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS( DEST_BYTE6 - SRC_BYTE0) 
TEMP1 := ABS( DEST_BYTE7 - SRC_BYTE1) TEMP2 := ABS( DEST_BYTE8 - SRC_BYTE2) TEMP3 := ABS( DEST_BYTE9 - SRC_BYTE3) DEST[111:96] := TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 := ABS( DEST_BYTE7 - SRC_BYTE0) 
TEMP1 := ABS( DEST_BYTE8 - SRC_BYTE1) TEMP2 := ABS( DEST_BYTE9 - SRC_BYTE2) TEMP3 := ABS( DEST_BYTE10 - SRC_BYTE3) DEST[127:112] := TEMP0 + TEMP1 + TEMP2 + TEMP3DEST[MAXVL-1:128] (Unmodified)
(V)MPSADBW __m128i _mm_mpsadbw_epu8 (__m128i s1, __m128i s2, const int mask);VMPSADBW __m256i _mm256_mpsadbw_epu8 (__m256i s1, __m256i s2, const int mask);
None.MPSADBW—Compute Multiple Packed Sums of Absolute DifferenceINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-145Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions.”MUL—Unsigned MultiplyINSTRUCTION SET REFERENCE, M-U
4-146 Vol. 2BMUL—Unsigned Multiply
Performs an unsigned multiplication of the first operand (destination operand) and the second operand (source 
operand) and stores the result in the destination operand.  The destination operand is an implied operand located in 
register AL, AX or EAX (depending on the size of the op erand); the source operand is located in a general-purpose 
register or a memory location. The action of this instruct ion and the location of the re sult depends on the opcode 
and the operand size as shown in Table 4-9.
The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size), 
with the high-order bits of the product contained in register  AH, DX, or EDX, respectively. If the high-order bits of 
the product are 0, the CF and OF flags are cleared; otherwise, the flags are set.
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. 
Operation
IF (Byte operation)
THEN 
AX := AL ∗ SRC;
ELSE (* Word or doubleword operation *)
IF OperandSize =  16
THEN 
DX:AX := AX ∗ SRC;
THEN EDX:EAX := EAX ∗ SRC; FI;
RDX:RAX := RAX ∗ SRC;Opcode Instruction Op/ 
En64-Bit 
F6 /4 MUL r/m8 M Valid Valid Uns igned multiply (AX := AL ∗ r/m8).
REX + F6 /4 MUL r/m81
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix  is used: AH, BH, CH, DH. M Valid N.E. Unsigned multiply (AX := AL ∗ r/m8).
F7 /4 MUL r/m16 M Valid Valid Unsigned multiply (DX:AX := AX ∗ r/m16).
F7 /4 MUL r/m32 M Valid Valid Unsign ed multiply (EDX:EAX := EAX ∗ r/m32).
REX.W + F7 /4 MUL r/m64 M Valid N.E. Unsigned multiply (RDX:RAX := RAX ∗ r/m64).
Table 4-9.  MUL Results
Operand Size Source 1 Source 2 Destination
Byte AL r/m8 AX
Word AX r/m16 DX:AX
Doubleword EAX r/m32 EDX:EAX
Quadword RAX r/m64 RDX:RAXMUL—Unsigned MultiplyINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-147FI;
FI;
The OF and CF flags are set to 0 if the upper half of the resu lt is 0; otherwise, they are set to 1. The SF, ZF, AF, and 
current privilege level is 3.MULPD—Multiply Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-148 Vol. 2BMULPD—Multiply Packed Double Pr ecision Floating-Point Values
Multiply packed double precision floating-point values from the first source operand with corresponding values in 
the second source operand, and stores the packed double precision floating-point results in the destination 
operand.
register or a 256-bit memory location. The destination op erand is a YMM register. Bits (MAXVL-1:256) of the corre-
sponding destination ZMM register are zeroed.
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the destination YMM register destination are zeroed.
InstructionOp /

Mode 
Feature 
66 0F 59 /r
MULPD xmm1, xmm2/m128A V/V SSE2 Multiply packed double precision floating-point values in 
xmm2/m128 with xmm1 and store result in xmm1.
VEX.128.66.0F.WIG 59 /r
VMULPD xmm1,xmm2, xmm3/m128B V/V AVX Multiply packed double precision floating-point values in 
xmm3/m128 with xmm2 and store result in xmm1.
VEX.256.66.0F.WIG 59 /r
VMULPD ymm1, ymm2, ymm3/m256B V/V AVX Multiply packed double precision floating-point values in 
ymm3/m256 with ymm2 and store result in ymm1.
EVEX.128.66.0F.W1 59 /r
VMULPD xmm1 {k1}{z}, xmm2, 
AVX512FMultiply packed double precision floating-point values 
from xmm3/m128/m64bcst to xmm2 and store result in 
xmm1.
EVEX.256.66.0F.W1 59 /r
VMULPD ymm1 {k1}{z}, ymm2, 
from ymm3/m256/m64bcst to ymm2 and store result in 
ymm1.
EVEX.512.66.0F.W1 59 /r
VMULPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}C V/V AVX512F Multiply packed double precision floating-point values in 
zmm3/m512/m64bcst with zmm2 and store result in zmm1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMULPD—Multiply Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-149Operation
VMULPD (EVEX Encoded Versions)
THEN
ELSE 
THEN 
THEN
DEST[i+63:i] := SRC1 [i+63:i] * SRC2[63:0]
ELSE 
DEST[i+63:i] := SRC1[i +63:i] * SRC2[i+63:i]
FI;
ELSE 
FI
FI;
VMULPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] * SRC2[63:0]DEST[127:64] := SRC1[127:64] * SRC2[127:64]DEST[191:128] := SRC1[1 91:128] * SRC2[191:128]
DEST[255:192] := SRC1[2 55:192] * SRC2[255:192]
DEST[MAXVL-1:256] := 0;.VMULPD (VEX.128 Encoded Version)DEST[63:0] := SRC1[63:0] * SRC2[63:0]DEST[127:64] := SRC1[127:64] * SRC2[127:64]DEST[MAXVL-1:128] := 0
MULPD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] * SRC[63:0]DEST[127:64] := DEST[127:64] * SRC[127:64]DEST[MAXVL-1:128 ] (Unmodified)MULPD—Multiply Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-150 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VMULPD __m512d _mm512_mul_pd( __m512d a, __m512d b);
VMULPD __m512d _mm512_mask_mul_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VMULPD __m512d _mm512_maskz_mul_pd( __mmask8 k, __m512d a, __m512d b);VMULPD __m512d _mm512_mul_round_p d( __m512d a, __m512d b, int);
VMULPD __m512d _mm512_mask_mul_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);VMULPD __m512d _mm512_maskz_mul_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VMULPD __m256d _mm256_mul_pd (__m256d a, __m256d b);MULPD __m128d _mm_mul_pd (__m128d a, __m128d b);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”MULPS—Multiply Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-151MULPS—Multiply Packed Single Pr ecision Floating-Point Values
Multiply the packed single precision floating-point values from the first source operand with the corresponding 
values in the second source operand, and stores the packed double precision floating-point results in the destina-
tion operand.
the destination YMM register destination are zeroed.
Mode 
Feature 
NP 0F 59 /r
MULPS xmm1, xmm2/m128A V/V SSE Multiply packed single precision floating-point values in 
VEX.128.0F.WIG 59 /r
VMULPS xmm1,xmm2, xmm3/m128B V/V AVX Multiply packed single precision floating-point values in 
VEX.256.0F.WIG 59 /r
VMULPS ymm1, ymm2, ymm3/m256B V/V AVX Multiply packed single precision floating-point values in 
EVEX.128.0F.W0 59 /r
VMULPS xmm1 {k1}{z}, xmm2, 
AVX512FMultiply packed single precisio n floating-point values from 
xmm1.
EVEX.256.0F.W0 59 /r
VMULPS ymm1 {k1}{z}, ymm2, 
ymm1.
EVEX.512.0F.W0 59 /r
VMULPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst {er}C V/V AVX512F Multiply packed single precision floating-point values in 
zmm3/m512/m32bcst with zmm2 and store result in zmm1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMULPS—Multiply Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-152 Vol. 2BOperation
VMULPS (EVEX Encoded Version)
THEN
ELSE 
THEN 
THEN
DEST[i+31:i] := SRC1[i+31:i] * SRC2[31:0]
ELSE 
DEST[i+31:i] := SRC1[i+31:i] * SRC2[i+31:i]
FI;
ELSE 
FI
FI;
VMULPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] * SRC2[31:0]DEST[63:32] := SRC1[63:32] * SRC2[63:32]DEST[95:64] := SRC1[95:64] * SRC2[95:64]DEST[127:96] := SRC1[127:96] * SRC2[127:96]DEST[159:128] := SRC1[1 59:128] * SRC2[159:128]
DEST[191:160] := SRC1[1 91:160] * SRC2[191:160]
DEST[223:192] := SRC1[2 23:192] * SRC2[223:192]
DEST[255:224] := SRC1[2 55:224] * SRC2[255:224].
VMULPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] * SRC2[31:0]DEST[63:32] := SRC1[63:32] * SRC2[63:32]DEST[95:64] := SRC1[95:64] * SRC2[95:64]DEST[127:96] := SRC1[127:96] * SRC2[127:96]DEST[MAXVL-1:128] := 0
MULPS (128-bit Legacy SSE Version)
DEST[31:0] := SRC1[31:0] * SRC2[31:0]DEST[63:32] := SRC1[63:32] * SRC2[63:32]DEST[95:64] := SRC1[95:64] * SRC2[95:64]DEST[127:96] := SRC1[127:96] * SRC2[127:96]DEST[MAXVL-1:128] (Unmodified)MULPS—Multiply Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-153Intel C/C++ Compiler Intrinsic Equivalent
VMULPS __m512 _mm512_mul_ps( __m512 a, __m512 b);
VMULPS __m512 _mm512_mask_mul_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);VMULPS __m512 _mm512_maskz_mul_ps(__mmask16 k, __m512 a, __m512 b);VMULPS __m512 _mm512_mul_round_ps( __m512 a, __m512 b, int);VMULPS __m512 _mm512_mask_mul_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);VMULPS __m512 _mm512_maskz_mul_round_ps(__mmask16 k, __m512 a, __m512 b, int);VMULPS __m256 _mm256_mask_mul_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);

VMULPS __m256 _mm256_maskz_mul_ps(__mmask8 k, __m256 a, __m256 b);VMULPS __m128 _mm_mask_mul_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);VMULPS __m128 _mm_maskz_mul_ps(__mmask8 k, __m128 a, __m128 b);VMULPS __m256 _mm256_mul_ps (__m256 a, __m256 b);MULPS __m128 _mm_mul_ps (__m128 a, __m128 b);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”MULSD—Multiply Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-154 Vol. 2BMULSD—Multiply Scalar Double Precision Floating-Point Value
Multiplies the low double precision floating-point value in  the second source operand by the low double precision 
floating-point value in the first source operand, and stores  the double precision floating-point result in the destina-
tion operand. The second source operand can be an XMM register or a 64-bit memory location. The first source operand and the destination operands are XMM registers. 
1:64) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: The quadword at bits  127:64 of the destination operand is copied from the 
same bits of the first source operand. Bits (MAX VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the write-
mask.
Software should ensure VMULSD is encoded with VEX.L= 0. Encoding VMULSD with VEX.L=1 may encounter unpre-
Operation
VMULSD (EVEX Encoded Version)
THEN
ELSE 
THEN DEST[63:0] := SRC1[63:0] * SRC2[63:0]ELSE 
FIOpcode/
Mode 
Feature 
F2 0F 59 /r
MULSD xmm1,xmm2/m64A V/V SSE2 Multiply the lo w double precision floating-point value in 
xmm2/m64 by low double precision floating-point value 
in xmm1.
VEX.LIG.F2.0F.WIG 59 /r
VMULSD xmm1,xmm2, xmm3/m64B V/V AVX Multiply the low double precision floating-point value in 
xmm3/m64 by low double precision floating-point value in xmm2.
EVEX.LLIG.F2.0F.W1 59 /r
VMULSD xmm1 {k1}{z}, xmm2, 
xmm3/m64 {er}C V/V AVX512F Multiply the low double precision floating-point value in 
xmm3/m64 by low double precision floating-point value 
in xmm2.
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMULSD—Multiply Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-155FI;
ENDFORDEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
VMULSD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] * SRC2[63:0]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
MULSD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] * SRC[63:0]DEST[MAXVL-1:64] (Unmodified)
VMULSD __m128d _mm_mask_mul_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);VMULSD __m128d _mm_maskz_mul_sd( __m mask8 k, __m128d a, __m128d b);
VMULSD __m128d _mm_mul_round_sd ( __m128d a, __m128d b, int);
VMULSD __m128d _mm_mask_mul_round_sd(__m128d s,  __mmask8 k, __m128d a, __m128d b, int);
VMULSD __m128d _mm_maskz_mul_round_sd( __mmask8 k, __m128d a, __m128d b, int);MULSD __m128d _mm_mul_sd (__m128d a, __m128d b)
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”MULSS—Multiply Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-156 Vol. 2BMULSS—Multiply Scalar Single Precision Floating-Point Values
Multiplies the low single precision floating-point value fr om the second source operand by the low single precision 
floating-point value in the first source operand, and stores  the single precision floating-point result in the destina-
tion operand. The second source operand can be an XMM register or a 32-bit memory location. The first source operand and the destination operands are XMM registers. 
1:32) of the corresponding YMM dest ination register remain unchanged.
VEX.128 and EVEX encoded version: The first source oper and is an xmm register encoded by VEX.vvvv. The three 
high-order doublewords of the destination operand are copi ed from the first source operand. Bits (MAXVL-1:128) 
EVEX encoded version: The low doubleword element of th e destination operand is updated according to the write-
mask.
Software should ensure VMULSS is encoded with VEX.L=0. Encoding VMUL SS with VEX.L=1 may encounter unpre-
Operation
VMULSS (EVEX Encoded Version)
THEN
ELSE 
THEN DEST[31:0] := SRC1[31:0] * SRC2[31:0]ELSE 
THEN DEST[31:0] := 0Opcode/
Mode 
Feature 
F3 0F 59 /r
MULSS xmm1,xmm2/m32A V/V SSE Multiply the low single precision floating-point value in 
xmm2/m32 by the low single precision floating-point 
VEX.LIG.F3.0F.WIG 59 /r
VMULSS xmm1,xmm2, xmm3/m32B V/V AVX Multiply the low single pr ecision floating-point value in 
xmm3/m32 by the low single precision floating-point value in xmm2.
EVEX.LLIG.F3.0F.W0 59 /r
VMULSS xmm1 {k1}{z}, xmm2, 
xmm3/m32 {er}C V/V AVX512F Multiply the low single precision floating-point value in 
xmm3/m32 by the low single precision floating-point 
value in xmm2.
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AMULSS—Multiply Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-157FI
FI;
ENDFORDEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
VMULSS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] * SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
MULSS (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0] * SRC[31:0]DEST[MAXVL-1:32] (Unmodified)
VMULSS __m128 _mm_mask_mul_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMULSS __m128 _mm_maskz_mul_ss( __mmask8 k, __m128 a, __m128 b);VMULSS __m128 _mm_mul_round_ss( __m128 a, __m128 b, int);VMULSS __m128 _mm_mask_mul_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMULSS __m128 _mm_maskz_mul_round_ss( __mmask8 k, __m128 a, __m128 b, int);MULSS __m128 _mm_mul_ss(__m128 a, __m128 b)
Underflow, Overflow, Invalid, Precision, Denormal.
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”MULX—Unsigned Multiply Without Affecting FlagsINSTRUCTION SET REFERENCE, M-U
4-158 Vol. 2BMULX—Unsigned Multiply Without Affecting Flags
Performs an unsigned multiplication of the implicit sour ce operand (EDX/RDX) and th e specified source operand 
(the third operand) and stores the low half of the result in the second destination (second operand), the high half 
of the result in the first destination operand (first operan d), without reading or writing the arithmetic flags. This 
enables efficient programming where the software can inte rleave add with carry operations and multiplications. 
If the first and second operand are identical, it will  contain the high half of the multiplication result.
Operation
// DEST1: ModRM:reg
// DEST2: VEX.vvvvIF (OperandSize = 32)
SRC1 := EDX;DEST2 := (SRC1*SRC2)[31:0];DEST1 := (SRC1*SRC2)[63:32];
ELSE IF (OperandSize = 64)
SRC1 := RDX;
DEST2 := (SRC1*SRC2)[63:0];DEST1 := (SRC1*SRC2)[127:64];

Operation
FI
Auto-generated from high-level language when possible.unsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);unsigned __int64 mulx_u64(unsig ned __int64 a, unsigned __int64 b, unsigned __int64 * hi);
None.
InstructionOp/ En 64/32-
VEX.LZ.F2.0F38.W0 F6 /r
MULX r32a, r32b, r/m32RVM V/V BMI2 Unsigned multiply of r/m32 with EDX without affecting arithmetic 
flags.
VEX.LZ.F2.0F38.W1 F6 /r
MULX r64a, r64b, r/m64RVM V/N.E. BMI2 Unsigned multiply of r/m64 with RDX without affecting arithmetic 
flags.
RVM ModRM:reg (w) VEX.vvvv (w) ModRM:r/m (r)RDX/EDX is implied 64/32 bits 
sourceMULX—Unsigned Multiply Without Affecting FlagsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-159Other Exceptions
See Table 2-29, “Type 13 Class Exception Conditions.”MWAIT—Monitor WaitINSTRUCTION SET REFERENCE, M-U
4-160 Vol. 2BMWAIT—Monitor Wait
MWAIT instruction provides hints to allow the processor to enter an implementation-dependent optimized state. 
There are two principal targeted usages: address-range monitor and advanced power management. Both usages 
of MWAIT require the use of the MONITOR instruction.
MWAIT may be executed only at privilege level 0 (use at  any other privilege level results in an invalid-opcode 
MSR; disabling MWAIT clears the CPUID feature flag and causes execution to generate an invalid-opcode excep-
tion. 
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.ECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized 
state the processor should enter. The first processors to  implement MWAIT supported only the zero value for EAX 
and ECX. Later processors allowed setting ECX[0] to en able masked interrupts as break events for MWAIT (see 
below). Software can use the CPUID instruction to determ ine the extensions and hints supported by the processor.
MWAIT for Address Range Monitoring
For address-range monitoring, the MWAIT instruction operates with the MONITOR instruction. The two instructions 
allow the definition of an address at which to wait (MONITOR) and a implementation-dependent-optimized opera-tion to commence at the wait address (MWAIT). The execution of MWAIT is a hint to the processor that it can enter 
an implementation-dependent-optimized state while waiting for an event or a store operation to the address range 
armed by MONITOR.
The following cause the processor to exit the implementa tion-dependent-optimized state: a store to the address 
range armed by the MONITOR instruction, an NMI or SM I, a debug exception, a machine check exception, the 
BINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events may also cause 
the processor to exit the implementation-dependent-optimized state.
In addition, an external interrupt causes the processo r to exit the implementation-dependent-optimized state 
either (1) if the interrupt would be delivered to software (e .g., as it would be if HLT had been executed instead of 
MWAIT); or (2) if ECX[0] = 1. Software can execute MWAI T with ECX[0] = 1 only if CPUID.05H:ECX[bit 1] = 1. 
(Implementation-specific conditions may result in an in terrupt causing the processor to exit the implementation-
dependent-optimized state even if interrupts are masked and ECX[0] = 0.)
Following exit from the implementation -dependent-optimized state, control passes to the instruction following the 
MWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before 
execution of that instruction. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the MWAIT instruction following the handling of an SMI. 
If the preceding MONITOR instruction did not successfully arm an address range or if the MONITOR instruction has 
not been executed prior to executing MWAIT, then the processor will not enter the implementation-dependent-opti-
mized state. Execution will resume at the instruction following the MWAIT.Opcode Instruction Op/ 
En64-Bit 
0F 01 C9 MWAIT ZO Valid Valid A hint that a llows the processor to stop instruction 
execution and enter an implementation-dependent 
optimized state until occurre nce of a class of events.
ZO N/A N/A N/A N/AMWAIT—Monitor WaitINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-161MWAIT for Power Management
MWAIT accepts a hint and optional extension to the proce ssor that it can enter a specified target C state while 
waiting for an event or a store operation to the addre ss range armed by MONITOR. Support for MWAIT extensions 
for power management is indicated by CPUID.05H:ECX[bit 0] reporting 1. 
EAX and ECX are used to communicate the additional inform ation to the MWAIT instruction, such as the kind of 
optimized state the processor should enter. ECX specifies optional extensions for the MWAIT instruction. EAX may 
contain hints such as the preferred optimized state the processor should enter. Implementation-specific conditions may cause a processor to ignore the hint and enter a different optimized state. Future processor implementations 
may implement several optimized “waiting” states and will select among those states based on the hint argument.
Table 4-10 describes the meaning of ECX and EAX registers for MWAIT extensions.
Note that if MWAIT is used to enter any of the C-states that are numerically higher than C1, a store to the address 
range armed by the MONITOR instruction will cause the proce ssor to exit MWAIT only if the store was originated by 
other processor agents. A store from non-processor agent might not cause the processor to exit MWAIT in such 
cases.
For additional details of MWAIT extensions, see Chap ter 15, “Power and Thermal Management,” of Intel
® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 3A.
Operation
(* MWAIT takes the argument in EA X as a hint extension and is arch itected to take the argument in  ECX as an inst ruction extensi on 
MWAIT EAX, ECX *)
{WHILE ( (“Monitor Hardware is in armed state”)) {
implementation_dependent_optimized_state(EAX, ECX); }
Set the state of Monitor Hardware as triggered;
}
MWAIT void _mm_mwait(unsigned extensions, unsigned hints)Table 4-10.  MWAIT Extension Register (ECX)
0 Treat interrupts as break events even if masked (e.g., even if EFLAGS.IF=0). May be set only if 
CPUID.05H:ECX[bit 1] = 1.
31: 1 Reserved
Table 4-11.  MWAIT Hints Register (EAX)
3 : 0 Sub C-state within a C-state,  indicated by bits [7:4]
7 : 4 Target C-state*
Value of 0 means C1; 1 means C2 and so onValue of 01111B means C0
Note: Target C states for MWAIT extensions are processor-specif ic C-states, not ACPI C-states
31: 8 ReservedMWAIT—Monitor WaitINSTRUCTION SET REFERENCE, M-U
4-162 Vol. 2BExample
MONITOR/MWAIT instruction pair must be coded in the same loop because execution of the MWAIT instruction will 
trigger the monitor hardware. It is not a proper usage to execute MONITOR once and then execute MWAIT in a 
loop. Setting up MONITOR without executing MWAIT has no adverse effects.
Typically the MONITOR/MWAIT pair is used in a sequence, such as:
EAX = Logical Address(Trigger)
ECX = 0 (*Hints *)EDX = 0 (* Hints *)
IF ( !trigger_store_happened) {
MONITOR EAX, ECX, EDXIF ( !trigger_store_happened ) {
MWAIT EAX, ECX
}
}
The above code sequence makes sure that a triggering stor e does not happen between the first check of the trigger 
and the execution of the monitor instruction. Without the second check that triggering store would go un-noticed. 
Typical usage of MONITOR and MWAIT would have  the above code sequence within a loop.
None.
#GP(0) If ECX[31:1] ≠ 0.
If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.
#GP If ECX[31:1] ≠ 0.
#UD The MWAIT instruction is not recognized in virtual-8086 mode (even if 
#GP(0) If RCX[63:1] ≠ 0.
If RCX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.
If CPUID.01H:ECX.MONITOR[bit 3] = 0.NEG—Two's Complement NegationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-163NEG—Two's Complement Negation

None.
Replaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent 
to subtracting the operand from 0.) The destination operan d is located in a general-purpose register or a memory 
location.
Operation
IF DEST = 0 
THEN CF := 0;ELSE CF := 1; 
FI;DEST := [– (DEST)]
The CF flag set to 0 if the source operand is 0; otherwis e it is set to 1. The OF, SF, ZF, AF, and PF flags are set 
according to the result. 
En64-Bit 
F6 /3 NEG r/m8 M Valid Valid Two's complement negate r/m8.
REX + F6 /3 NEG r/m8
1
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.M Valid N.E. Two's complement negate r/m8.
F7 /3 NEG r/m16 M Valid Valid Two's complement negate r/m16.F7 /3 NEG r/m32 M Valid Valid Two's complement negate r/m32.REX.W + F7 /3 NEG r/m64 M Valid N.E. Two's complement negate r/m64.
M ModRM:r/m (r, w) N/A N/A N/ANEG—Two's Complement NegationINSTRUCTION SET REFERENCE, M-U
4-164 Vol. 2BReal-Address Mode Exceptions
Same as for protected mode exceptions.
#UD If the LOCK prefix is used but the destination is not a memory operand.NOP—No OperationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-165NOP—No Operation
This instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction 
stream but does not impact machine context, except for the EIP register.
The multi-byte form of NOP is available on processors with model encoding:
•CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B
The multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The 
instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
The one-byte NOP instruction is an alias mnem onic for the XCHG (E)AX, (E)AX instruction.
The multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode 
exception on processors that do not support the multi-byte NOP instruction.
The memory operand form of the instruction allows software  to create a byte sequence of “no operation” as one 
instruction. For situations where multiple-byte NOPs ar e needed, the recommended operations (32-bit mode and 
64-bit mode) are: 
None.
En64-Bit 
NP 90 NOP ZO Valid Valid One byte no-operation instruction.
NP 0F 1F /0 NOP r/m16 M Valid Valid Mu lti-byte no-operation instruction.
NP 0F 1F /0 NOP r/m32 M Valid Valid Mu lti-byte no-operation instruction.
Table 4-12.  Recommended Multi-By te Sequence of NOP Instruction
Length Assembly Byte Sequence
2 bytes 66 NOP 66 90H
3 bytes NOP DWORD ptr [EAX] 0F 1F 00H4 bytes NOP DWORD ptr [EAX + 00H] 0F 1F 40 00H
5 bytes NOP DWORD ptr [EAX + EAX*1 + 00H] 0F 1F 44 00 00H
6 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00H] 66 0F 1F 44 00 00H7 bytes NOP DWORD ptr [EAX + 00000000H] 0F 1F 80 00 00 00 00H
8 bytes NOP DWORD ptr [EAX + EAX*1 + 00000000H] 0F 1F 84 00 00 00 00 00H
9 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00000000H] 66 0F 1F 84 00 00 00 00 00HNOT—One's Complement NegationINSTRUCTION SET REFERENCE, M-U
4-166 Vol. 2BNOT—One's Complement Negation
Performs a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the destination operand and stores 
the result in the destination operand location. The destination operand can be a register or a memory location.
Operation
DEST := NOT DEST;
None.
#UD If the LOCK prefix is used but the destination is not a memory operand.Opcode Instruction Op/ 
En64-Bit 
F6 /2 NOT r/m8 M Valid Valid Reverse each bit of r/m8.
REX + F6 /2 NOT r/m81
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.M Valid N.E. Reverse each bit of r/m8.
F7 /2 NOT r/m16 M Valid Valid Reverse each bit of r/m16.F7 /2 NOT r/m32 M Valid Valid Reverse each bit of r/m32.REX.W + F7 /2 NOT r/m64 M Valid N.E. Reverse each bit of r/m64.
M ModRM:r/m (r, w) N/A N/A N/ANOT—One's Complement NegationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-167Virtual-8086 Mode Exceptions
#UD If the LOCK prefix is used but th e destination is not a memory operand.OR—Logical Inclusive ORINSTRUCTION SET REFERENCE, M-U
4-168 Vol. 2BOR—Logical Inclusive OR
Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores 
the result in the destination operand location. The source  operand can be an immediat e, a register, or a memory

the result in the destination operand location. The source  operand can be an immediat e, a register, or a memory 
location; the destination operand can be a register or a memory location. (However, two memory operands cannot 
be used in one instruction.) Each bit of the result of the OR  instruction is set to 0 if both corresponding bits of the 
first and second operands are 0; otherwise, each bit is set to 1.
This instruction can be used with a LOCK prefix to  allow the instruction to be executed atomically.Opcode Instruction Op/ 
En64-Bit 
0C ib OR AL, imm8 I Valid Valid AL OR imm8.
0D iw OR AX, imm16 I Valid Valid AX OR imm16.0D id OR EAX, imm32 I Va lid Valid EAX OR imm32.
REX.W + 0D id OR RAX, imm32 I Valid N .E. RAX OR imm32 (sign-extended).
80 /1 ib OR r/m8, imm8 MI Valid Valid r/m8 OR imm8.REX + 80 /1 ib OR r/m8
1, imm8 MI Valid N.E. r/m8 OR imm8.
81 /1 iw OR r/m16, imm16 MI Valid Valid  r/m16 OR imm16.81 /1 id OR r/m32, imm32 MI Valid Valid  r/m32 OR imm32.REX.W + 81 /1 id OR r/m64, imm32 MI Valid N.E.  r/m64 OR imm32 (sign-extended).83 /1 ib OR r/m16, imm8 MI Valid Valid r/m16 OR imm8 (sign-extended).83 /1 ib OR r/m32, imm8 MI Valid Valid r/m32 OR imm8 (sign-extended).REX.W + 83 /1 ib OR r/m64, imm8 MI Valid N.E. r/m64 OR imm8 (sign-extended).08 /r OR r/m8, r8 MR Valid Valid r/m8 OR r8.REX + 08 /r OR r/m8
1, r81
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.MR Valid N.E. r/m8 OR r8.
09 /r OR r/m16, r16 MR Valid Valid r/m16 OR r16.09 /r OR r/m32, r32 MR Valid Valid r/m32 OR r32.REX.W + 09 /r OR r/m64, r6 4M R V a l i d N . E . r / m 6 4  O R  r 6 4 .
0A /r OR r8, r/m8 RM Valid Valid r8 OR r/m8.REX + 0A /r OR r8
1, r/m81RM Valid N.E. r8 OR r/m8.
0B /r OR r16, r/m16 RM Valid Valid r16 OR r/m16.0B /r OR r32, r/m32 RM Valid Valid r32 OR r/m32.REX.W + 0B /r OR r64, r/m6 4 RM Valid N.E. r64 OR r/m64.
I AL/AX/EAX/RAX imm8/16/32 N/A N/A
MR ModRM:r/m (r, w) ModRM:reg (r) N/A N/ARM ModRM:reg (r, w) ModRM:r/m (r) N/A N/AOR—Logical Inclusive ORINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-169In 64-bit mode, the instruction’s default operation size is  32 bits. Using a REX prefix in  the form of REX.R permits 
Operation
DEST := DEST OR SRC;
#UD If the LOCK prefix is used but th e destination is not a memory operand.ORPD—Bitwise Logical OR of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-170 Vol. 2BORPD—Bitwise Logical OR of Packed Dou ble Precision Floating-Point Values
Performs a bitwise logical OR of the two, four or eight packed double precision floating-point values from the first 
32-bit memory location. The destination operand is a Z MM/YMM/XMM register conditionally updated with write-
mask k1.
Mode 
Feature 
66 0F 56/r
ORPD xmm1, xmm2/m128A V/V SSE2 Return the bitwise logical OR of packed double precision 
VEX.128.66.0F 56 /r
VORPD xmm1,xmm2, xmm3/m128B V/V AVX Return the bitwise logical OR of packed double precision 
floating-point values in xmm2 and xmm3/mem.
VEX.256.66.0F 56 /r
VORPD ymm1, ymm2, ymm3/m256B V/V AVX Return the bitwise logical OR of packed double precision 
EVEX.128.66.0F.W1 56 /r
VORPD xmm1 {k1}{z}, xmm2, 
AVX512DQReturn the bitwise logical OR of packed double precision 
EVEX.256.66.0F.W1 56 /r
VORPD ymm1 {k1}{z}, ymm2, 
EVEX.512.66.0F.W1 56 /r
VORPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512DQ Return the bitwise logical OR of packed double precision 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AORPD—Bitwise Logical OR of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-171Operation
VORPD (EVEX Encoded Versions)
THEN 
THEN
DEST[i+63:i] := SRC1[i+63:i] BITWISE OR SRC2[63:0]
ELSE 
DEST[i+63:i] := SRC1[i+63:i] BITWISE OR SRC2[i+63:i]
FI;
ELSE 
THEN *DEST[i+63:i] remains unchanged*ELSE *zeroing-masking* ; zeroing-masking
FI
FI;
VORPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] BITWISE OR SRC2[63:0]DEST[127:64] := SRC1[127:64] BITWISE OR SRC2[127:64]DEST[191:128] := SRC1[191:128 ] BITWISE OR SRC2[191:128]
DEST[255:192] := SRC1[255:192 ] BITWISE OR SRC2[255:192]
VORPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] BITWISE OR SRC2[63:0]DEST[127:64] := SRC1[127:64] BITWISE OR SRC2[127:64]DEST[MAXVL-1:128] := 0
ORPD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] BITWISE OR SRC[63:0]DEST[127:64] := DEST[127:64] BITWISE OR SRC[127:64]DEST[MAXVL-1:128 ] (Unmodified)
VORPD __m512d _mm512_or_pd ( __m512d a, __m512d  b);
VORPD __m512d _mm512_mask_or_pd ( __m512d s, __mmask8 k, __m512d a, __m512d b);
VORPD __m512d _mm512_maskz_or_pd (__mmask8 k, __m512d a, __m512d b);VORPD __m256d _mm256_mask_or_pd (__m256d s, ___mmask8 k, __m256d a, __m256d b);
VORPD __m256d _mm256_maskz_or_pd (__mmask8 k, __m256d a, __m256d b);VORPD __m128d _mm_mask_or_pd ( __m128d s,  __mmask8 k, __m128d a, __m128d b);

VORPD __m128d _mm_maskz_or_pd (__m mask8 k, __m128d a, __m128d b);
VORPD __m256d _mm256_or_pd (__m256d a, __m256d b);ORPD __m128d _mm_or_pd (__m128d a, __m128d b);ORPD—Bitwise Logical OR of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-172 Vol. 2BSIMD Floating-Point Exceptions
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-173ORPS—Bitwise Logical OR of Packed Sing le Precision Floating-Point Values
Performs a bitwise logical OR of the four, eight or sixteen pa cked single precision floating-point values from the first 
source operand and the second so urce operand, and stores the result in the destination operand
32-bit memory location. The destination operand is a Z MM/YMM/XMM register conditio nally updated with write-
mask k1.
Mode 
Feature 
NP 0F 56 /r
ORPS xmm1, xmm2/m128A V/V SSE Return the bitwise logical OR of packed single precision 
VEX.128.0F 56 /r
VORPS xmm1,xmm2, xmm3/m128B V/V AVX Return the bitwise logical OR of packed single precision 
VEX.256.0F 56 /r
VORPS ymm1, ymm2, ymm3/m256B V/V AVX Return the bitwise logical OR of packed single precision 
EVEX.128.0F.W0 56 /r
VORPS xmm1 {k1}{z}, xmm2, 
AVX512DQReturn the bitwise logical OR of packed single precision 
floating-point values in xmm2 and xmm3/m128/m32bcst 
EVEX.256.0F.W0 56 /r
VORPS ymm1 {k1}{z}, ymm2, 
floating-point values in ymm2 and ymm3/m256/m32bcst 
EVEX.512.0F.W0 56 /r
VORPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstC V/V AVX512DQ Return the bitwise logical OR of packed single precision 
floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1.
CF u l l M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/AORPS—Bitwise Logical OR of Packed Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-174 Vol. 2BOperation
VORPS (EVEX Encoded Versions)
THEN 
THEN
DEST[i+31:i] := SRC1[i+31: i] BITWISE OR SRC2[31:0]
ELSE 
DEST[i+31:i] := SRC1[i+31: i] BITWISE OR SRC2[i+31:i]
FI;
ELSE 
THEN *DEST[i+31:i] remains unchanged*ELSE *zeroing-masking* ; zeroing-masking
FI
FI;
VORPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] BITWISE OR SRC2[31:0]DEST[63:32] := SRC1[63:32] BITWISE OR SRC2[63:32]DEST[95:64] := SRC1[95:64] BITWISE OR SRC2[95:64]DEST[127:96] := SRC1[127:96] BITWISE OR SRC2[127:96]DEST[159:128] := SRC1[159:128] BITWISE OR SRC2[159:128]DEST[191:160] := SRC1[191:160] BITWISE OR SRC2[191:160]DEST[223:192] := SRC1[223:192] BITWISE OR SRC2[223:192]DEST[255:224] := SRC1[255:224] BITWISE OR SRC2[255:224].DEST[MAXVL-1:256] := 0
VORPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] BITWISE OR SRC2[31:0]DEST[63:32] := SRC1[63:32] BITWISE OR SRC2[63:32]DEST[95:64] := SRC1[95:64] BITWISE OR SRC2[95:64]DEST[127:96] := SRC1[127:96] BITWISE OR SRC2[127:96]DEST[MAXVL-1:128] := 0
ORPS (128-bit Legacy SSE Version)
DEST[31:0] := SRC1[31:0] BITWISE OR SRC2[31:0]DEST[63:32] := SRC1[63:32] BITWISE OR SRC2[63:32]DEST[95:64] := SRC1[95:64] BITWISE OR SRC2[95:64]DEST[127:96] := SRC1[127:96] BITWISE OR SRC2[127:96]DEST[MAXVL-1:128] (Unmodified)ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-175Intel C/C++ Compiler Intrinsic Equivalent
VORPS __m512 _mm512_or_ps ( __m512 a, __m512 b);
VORPS __m512 _mm512_mask_or_ps ( __m512 s, __mmask16 k, __m512 a, __m512 b);VORPS __m512 _mm512_maskz_or_ps (__mmask16 k, __m512 a, __m512 b);VORPS __m256 _mm256_mask_or_ps (__m256 s, ___mmask8 k, __m256 a, __m256 b);VORPS __m256 _mm256_maskz_or_ps (__mmask8 k, __m256 a, __m256 b);VORPS __m128 _mm_mask_or_ps ( __m128 s, __mmask8 k, __m128 a, __m128 b);VORPS __m128 _mm_maskz_or_ps (_ _mmask8 k, __m128 a, __m128 b);
VORPS __m256 _mm256_or_ps (__m256 a, __m256 b);ORPS __m128 _mm_or_ps (__m128 a, __m128 b);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”OUT—Output to PortINSTRUCTION SET REFERENCE, M-U
4-176 Vol. 2BOUT—Output to Port
Copies the value from the second operand (source operand)  to the I/O port specified with the destination operand 
(first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being 
accessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register. 
Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source operand allows I/O ports from 0 to 65,535 to be accessed.
The size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size 
attribute of the instruction for a 16- or 32-bit I/O port.
At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits 
of the port address will be 0.
“Input/Output,” in the Intel
® 64 and IA-32 Architectures Software Deve loper’s Manual, Volume 1, for more infor-
After executing an OUT instruction, the Pentium® processor ensures that the EWBE# pin has been sampled active 
before it begins to execute the next instruction. (Note that  the instruction can be prefetched if EWBE# is not active, 
but it will not be executed until the EWBE# pin is samp led active.) Only the Pentium processor family has the 
EWBE# pin.Opcode1
NOTES:
En64-Bit 
E6 ib OUT imm8, AL I Valid Valid Output byte in AL to I/O port address imm8.
E7 ib OUT imm8, AX I Valid Valid Output word  in AX to I/O po rt address imm8. 
E7 ib OUT imm8, EAX I Valid Valid Output double word in EAX to I/O port address imm8.
EE OUT DX, AL ZO Valid Valid Output byte in AL to I/O port address in DX.
EF OUT DX, AX ZO Valid Valid Output word in AX to I/O port address in DX.
EF OUT DX, EAX ZO Valid Valid Output doubleword in EAX to I/O port address in DX.
ZO N/A N/A N/A N/AOUT—Output to PortINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-177Operation
#GP(0);
DEST := SRC; (* Writes to selected I/O port *)
FI;
FI;
None.
#GP(0) If the CPL is greater than (has less privileg e) the I/O privilege level (IOPL) and any of the

#GP(0);
FI;
FI;
None.
Same as protected mode exceptions.
Same as protected mode exceptions.OUTS/OUTSB/OUTSW/OUTSD—Output String to PortINSTRUCTION SET REFERENCE, M-U
4-178 Vol. 2BOUTS/OUTSB/OUTSW/OUTSD—Output String to Port
Copies data from the source operand (second operand) to the I/O port specified with the destination operand (first 
operand). The source operand is a memory location, the addr ess of which is read from either the DS:SI, DS:ESI or 
the RSI registers (depending on the address-size attribute of  the instruction, 16, 32 or 64, respectively). (The DS 
segment may be overridden with a segment override prefix.)  The destination operand is an I/O port address (from 
0 to 65,535) that is read from the DX register. The size of the I/O port being accessed (that is, the size of the source 
and destination operands) is determined by the opcode for an  8-bit I/O port or by the operand-size attribute of the 
instruction for a 16- or 32-bit I/O port.
operands” form. The explicit-operands form (specified with  the OUTS mnemonic) allows the source and destination 
operands to be specified explicitly. Here, the source operan d should be a symbol that indicates the size of the I/O 
port and the source address, and the destination operand mu st be DX. This explicit-operands form is provided to 
allow documentation; however, note that the documentation provided by this form can be misleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does 
not have to specify the correct location . The location is always specified by the DS:(E)SI or RSI registers, which 
must be loaded correctly before the OUTS instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the OUTS instructions. 
Here also DS:(E)SI is assumed to be the source operand an d DX is assumed to be the destination operand. The size 
of the I/O port is specified with the choice of mnem onic: OUTSB (byte), OUTSW (word), or OUTSD (doubleword).
After the byte, word, or doubleword is transferred from  the memory location to the I/O port, the SI/ESI/RSI 
register is incremented or decremented automatically according to the setting of  the DF flag in the EFLAGS register. 
(If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the SI/ESI/RSI register is decremented.) 
The SI/ESI/RSI register is incremented or decremented by 1 for byte operatio ns, by 2 for word operations, and by 
4 for doubleword operations.
The OUTS, OUTSB, OUTSW, and OUTSD instructions can be pr eceded by the REP prefix fo r block input of ECX bytes, 
words, or doublewords. See “REP/REPE/REPZ /REPNE/REPNZ —Repeat String Operation Prefix” in this chapter for a Opcode
1
NOTES:
En64-Bit 
6E OUTS DX, m8 ZO Valid Valid Output byte from memory location specified in 
DS:(E)SI or RSI to I/O port specified in DX2.
2. In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) address size s are supported. In non-64-bit mode, only 32-bit (ESI) and 16 -bit (SI) 
address sizes are supported.6F OUTS DX, m16 ZO Valid Valid Output word from memory location specified in 
6F OUTS DX, m32 ZO Valid Valid Output doubleword from memory location specified in 
6E OUTSB ZO Valid Valid Output byte from memory location specified in 
6F OUTSW ZO Valid Valid Output word from memory location specified in 
6F OUTSD ZO Valid Valid Output doubleword from memory location specified in 
ZO N/A N/A N/A N/AOUTS/OUTSB/OUTSW/OUTSD—Output String to PortINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-179description of the REP prefix. This instruction is only us eful for accessing I/O ports located in the processor’s I/O 
address space. See Chapter 19, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.
In 64-bit mode, the default operand size is 32 bits; oper and size is not promoted by the use of REX.W. In 64-bit 
mode, the default address size is 64 bits, and 64-bit address is specified using RSI by de fault. 32-bit address using 
ESI is support using the prefix 67H, but 16-b it address is not supported in 64-bit mode.
After executing an OUTS, OUTSB, OUTSW, or OUTSD inst ruction, the Pentium processor ensures that the EWBE# 
pin has been sampled active before it begins to execute the next instruction. (Note that the instruction can be prefetched if EWBE# is not active, but it will not be executed until the EWBE# pin is sampled active.) Only the 
Pentium processor family has the EWBE# pin.
For the Pentium 4, Intel
® Xeon®, and P6 processor family, upon executio n of an OUTS, OUTSB, OUTSW, or OUTSD 
instruction, the processor will not execute the next instruction until the data phase of the transaction is complete.
Operation
#GP(0);
DEST := SRC; (* Writes to I/O port *)
FI;
ELSE (Real Mode or Protected Mo de or 64-Bit Mode with CPL ≤ IOPL *)
FI;
Byte transfer:
Then
IF 64-Bit Address Size 
THEN 
IF DF = 0
THEN RSI := RSI RSI + 1; 
ELSE RSI := RSI or – 1; 
FI;
ELSE (* 32-Bit Address Size *)
IF DF = 0
THEN ESI := ESI + 1; 
ELSE ESI := ESI – 1; 
FI;
FI;
ELSE 
IF DF = 0
FI;
FI;
Word transfer:
Then
IF 64-Bit Address Size OUTS/OUTSB/OUTSW/OUTSD—Output String to PortINSTRUCTION SET REFERENCE, M-U
4-180 Vol. 2BTHEN 
IF DF = 0
THEN RSI := RSI RSI + 2; 
ELSE RSI := RSI or – 2; 
FI;
IF DF = 0
THEN ESI := ESI + 2; 
ELSE ESI := ESI – 2; 
FI;
FI;
ELSE 
IF DF = 0
FI;
FI;
Doubleword transfer:
Then
THEN 
IF DF = 0
THEN RSI := RSI RSI + 4; 
ELSE RSI := RSI or – 4; 
FI;
IF DF = 0
THEN ESI := ESI + 4; 
ELSE ESI := ESI – 4; 
FI;
FI;
ELSE 
IF DF = 0
FI;
FI;
None.
If a memory operand effective address is outs ide the limit of the CS, DS, ES, FS, or GS 
segment.
If the segment register contains a NULL segment selector.
#UD If the LOCK prefix is used.OUTS/OUTSB/OUTSW/OUTSD—Output String to PortINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-181Real-Address Mode Exceptions

#UD If the LOCK prefix is used.PABSB/PABSW/PABSD/PABSQ—Packed Absolute ValueINSTRUCTION SET REFERENCE, M-U
4-182 Vol. 2BPABSB/PABSW/PABSD/PABSQ—Packed Absolute Value 
Opcode/
NP 0F 38 1C /r
1
PABSB mm1, mm2/m64 A V/V SSSE3 Compute the absolute  value of bytes in mm2/m64 
and store UNSIGNED result in mm1.
66 0F 38 1C /r 
PABSB xmm1, xmm2/m128 A V/V SSSE3 Compute the abso lute value of bytes in 
xmm2/m128 and store UNSIGNED result in xmm1. 
NP 0F 38 1D /r1
PABSW mm1, mm2/m64 A V/V SSSE3 Compute the absolute value of 16-bit integers in 
mm2/m64 and store UNSIGNED result in mm1.
66 0F 38 1D /r
PABSW xmm1, xmm2/m128A V/V SSSE3 Compute the absolute value of 16-bit integers in 
xmm2/m128 and store UNSIGNED result in xmm1.
NP 0F 38 1E /r1 
PABSD mm1, mm2/m64 A V/V SSSE3 Compute the absolute value of 32-bit integers in 
mm2/m64 and store UNSIGNED result in mm1. 
66 0F 38 1E /r 
PABSD xmm1, xmm2/m128 A V/V SSSE3 Compute the absolute value of 32-bit integers in 
VEX.128.66.0F38.WIG 1C /r
VPABSB xmm1, xmm2/m128AV / V A V X C o m p u t e  t h e  a b s o l u te value of bytes in 
VEX.128.66.0F38.WIG 1D /r
VPABSW xmm1, xmm2/m128A V/V AVX Compute the absolute va lue of 16- bit integers in 
VEX.128.66.0F38.WIG 1E /r
VPABSD xmm1, xmm2/m128A V/V AVX Compute the absolute va lue of 32- bit integers in 
VEX.256.66.0F38.WIG 1C /r
VPABSB ymm1, ymm2/m256A V/V AVX2 Compute the absolute value of bytes in 
ymm2/m256 and store UNSI GNED result in ymm1.
VEX.256.66.0F38.WIG 1D /r
VPABSW ymm1, ymm2/m256AV / V A V X 2 C o m p u t e  t h e  a b s o l u t e  value of 16-bit integers in 
VEX.256.66.0F38.WIG 1E /r
VPABSD ymm1, ymm2/m256AV / V A V X 2 C o m p u t e  t h e  a b s o l u t e  value of 32-bit integers in 
EVEX.128.66.0F38.WIG 1C /r
VPABSB xmm1 {k1}{z}, xmm2/m128B V/V AVX512VL
AVX512BWCompute the absolute value of bytes in 
xmm2/m128 and store UNSIGNED result in xmm1 
using writemask k1.
EVEX.256.66.0F38.WIG 1C /r
VPABSB ymm1 {k1}{z}, ymm2/m256B V/V AVX512VL
ymm2/m256 and store UNSI GNED result in ymm1 
EVEX.512.66.0F38.WIG 1C /r
VPABSB zmm1 {k1}{z}, zmm2/m512BV / V A V X 5 1 2 B W C o m p u t e  t h e  a b s o lute value of bytes in 
zmm2/m512 and store UNSIGNED result in zmm1 
EVEX.128.66.0F38.WIG 1D /r 
VPABSW xmm1 {k1}{z}, xmm2/m128B V/V AVX512VL
AVX512BWCompute the absolute valu e of 16-bit integers in 
EVEX.256.66.0F38.WIG 1D /r 
VPABSW ymm1 {k1}{z}, ymm2/m256 B V/V AVX512VL
EVEX.512.66.0F38.WIG 1D /r 
VPABSW zmm1 {k1}{z}, zmm2/m512BV / V A V X 5 1 2 B W C o m p u t e  t h e  a b s o l u t e  value of 16-bit integers in 
using writemask k1.PABSB/PABSW/PABSD/PABSQ—Packed Absolute ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-183Instruction Operand Encoding
PABSB/W/D computes the absolute value of each data el ement of the source operand (the second operand) and 
stores the UNSIGNED results in the destination operand (the first operand). PABSB op erates on signed bytes, 
PABSW operates on signed 16-bit words, and PABSD operates on signed 32-bit integers. 
EVEX encoded VPABSD/Q: The source operand is a ZMM/ YMM/XMM register, a 512/256/128-bit memory location, 
or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a 
ZMM/YMM/XMM register updated according to the writemask. 
EVEX encoded VPABSB/W: The source operand is a ZMM/ YMM/XMM register, or a 512/ 256/128-bit memory loca-
tion. The destination operand is a ZMM/YMM/XMM register updated according to the writemask. 
VEX.256 encoded versions: The source operand is a YMM re gister or a 256-bit memory  location. The destination 
operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding register destination are zeroed.
VEX.128 encoded versions: The source operand is an XMM register or 128-bit memory location. The destination 
operand is an XMM register. The upper bits (MAXVL-1:128 ) of the corresponding register destination are zeroed.
128-bit Legacy SSE version: The source operand can be an  XMM register or an 128-bi t memory location. The desti-
nation is an XMM register. The upper bits (VL_MAX-1:128)  of the corresponding register destination are unmodi-
fied.
VEX.vvvv and EVEX.vvvv ar e reserved and must be 1111b otherwise instructions will #UD.EVEX.128.66.0F38.W0 1E /r
VPABSD xmm1 {k1}{z},  xmm2/m128/m32bcstC V/V AVX512VL
AVX512FCompute the absolute valu e of 32-bit integers in 
xmm2/m128/m32bcst and store UNSIGNED result 
in xmm1 using writemask k1. 
EVEX.256.66.0F38.W0 1E /r
VPABSD ymm1 {k1}{z}, ymm2/m256/m32bcstC V/V AVX512VL
ymm2/m256/m32bcst and store UNSIGNED result in ymm1 using writemask k1. 
EVEX.512.66.0F38.W0 1E /r
VPABSD zmm1 {k1}{z},  zmm2/m512/m32bcst C V/V AVX512F Compute the absolute value of 32-bit integers in 
zmm2/m512/m32bcst and store UNSIGNED result 
in zmm1 using writemask k1. 
EVEX.128.66.0F38.W1 1F /r
VPABSQ xmm1 {k1}{z}, xmm2/m128/m64bcstC V/V AVX512VL
AVX512FCompute the absolute valu e of 64-bit integers in 
xmm2/m128/m64bcst and store UNSIGNED result 
EVEX.256.66.0F38.W1 1F /r
VPABSQ ymm1 {k1}{z},  ymm2/m256/m64bcstC V/V AVX512VL
ymm2/m256/m64bcst and store UNSIGNED result 
in ymm1 using writemask k1. 
EVEX.512.66.0F38.W1 1F /r
VPABSQ zmm1 {k1}{z}, zmm2/m512/m64bcst C V/V AVX512F Compute the absolute value of 64-bit integers in 
zmm2/m512/m64bcst and store UNSIGNED result in zmm1 using writemask k1. 
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX 
Registers,” in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.
C Full ModRM:reg (w) ModRM:r/m (r) N/A N/AOpcode/
Mode 
Feature 
FlagDescriptionPABSB/PABSW/PABSD/PABSQ—Packed Absolute ValueINSTRUCTION SET REFERENCE, M-U
4-184 Vol. 2BOperation
PABSB With 128-bit Operands:
Unsigned DEST[7:0] := ABS(SRC[7: 0]) Repeat operation for 2nd through 15th bytes Unsigned DEST[127:120] := ABS(SRC[127:120])
VPABSB With 128-bit Operands:
VPABSB With 256-bit Operands:
Unsigned DEST[7:0] := ABS(SRC[7: 0]) Repeat operation for 2nd through 31st bytes Unsigned DEST[255:248] := ABS(SRC[255:248]) 
VPABSB (EVEX Encoded Versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
THEN 
Unsigned DEST[i+7:i] := ABS(SRC[i+7:i])
ELSE 
THEN *DEST[i+7:i] remains unchanged*ELSE *zeroing-masking* ; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
PABSW With 128-bit Operands:
Unsigned DEST[15:0] := ABS(SRC[15:0]) Repeat operation for 2nd through 7th 16-bit words Unsigned DEST[127:112] := ABS(SRC[127:112]) 
VPABSW With 128-bit Operands:
VPABSW With 256-bit Operands:
Unsigned DEST[15:0] := ABS(SRC[15:0]) Repeat operation for 2nd through 15th 16-bit words Unsigned DEST[255:240] := ABS(SRC[255:240]) PABSB/PABSW/PABSD/PABSQ—Packed Absolute ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-185VPABSW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
THEN 
Unsigned DEST[i+15:i] := ABS(SRC[i+15:i])
ELSE 
THEN *DEST[i+15:i] remains unchanged*ELSE *zeroing-masking* ; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
PABSD With 128-bit Operands:
Unsigned DEST[31:0] := ABS(SRC[31:0]) Repeat operation for 2nd through 3rd 32-bit double words Unsigned DEST[127:96] := ABS(SRC[127:96]) 
VPABSD With 128-bit Operands:
VPABSD With 256-bit Operands:

THEN 
ELSE 
FI
FI;
Unsigned DEST[31:0] := ABS(SRC[31:0]) Repeat operation for 2nd through 7th 32-bit double words Unsigned DEST[255:224] := ABS(SRC[255:224]) 
VPABSD (EVEX Encoded Versions)
THEN 
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
Unsigned DEST[i+31:i] := ABS(SRC[31:0])
ELSE 
Unsigned DEST[i+31:i] := ABS(SRC[i+31:i])
FI;
ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PABSB/PABSW/PABSD/PABSQ—Packed Absolute ValueINSTRUCTION SET REFERENCE, M-U
4-186 Vol. 2BVPABSQ (EVEX Encoded Versions)
THEN 
THEN
Unsigned DEST[i+63:i] := ABS(SRC[63:0])
ELSE 
Unsigned DEST[i+63:i] := ABS(SRC[i+63:i])
FI;
ELSE 
FI
FI;
Intel C/C++ Compiler Intrinsic Equivalents
VPABSB__m512i _mm512_abs_epi8 ( __m512i a)VPABSW__m512i _mm512_abs_epi16 ( __m512i a)VPABSB__m512i _mm512_mask_abs_epi8 ( __m512i s, __mmask64 m, __m512i a)VPABSW__m512i _mm512_mask_abs_epi16 ( __m512i s, __mmask32 m, __m512i a)VPABSB__m512i _mm512_maskz_abs _epi8 (__mmask64 m, __m512i a)
VPABSW__m512i _mm512_maskz_abs_epi16 (__mmask32 m, __m512i a)VPABSB__m256i _mm256_mask_abs_epi8 (__m256i s, __mmask32 m, __m256i a)VPABSW__m256i _mm256_mask_abs_epi16 (__m256i s, __mmask16 m, __m256i a)VPABSB__m256i _mm256_maskz_abs _epi8 (__mmask32 m, __m256i a)
VPABSW__m256i _mm256_maskz_abs_epi16 (__mmask16 m, __m256i a)VPABSB__m128i _mm_mask _abs_epi8 (__m128i s, __mmask16 m, __m128i a)
VPABSW__m128i _mm_mask_abs_epi16 (__m128i s, __mmask8 m, __m128i a)VPABSB__m128i _mm_maskz_abs_ep i8 (__mmask16 m, __m128i a)
VPABSW__m128i _mm_maskz_abs_epi16 (__mmask8 m, __m128i a)VPABSD __m256i _mm256_mask_abs_epi32( __m256i s, __mmask8 k, __m256i a);
VPABSD __m256i _mm256_maskz_abs_epi32( __mmask8 k, __m256i a);VPABSD __m128i _mm_mask_abs_epi32(__m 128i s, __mmask8 k, __m128i a);
VPABSD __m128i _mm_maskz_abs_ep i32( __mmask8 k, __m128i a);
VPABSD  __m512i _mm512_abs_epi32( __m512i a);VPABSD  __m512i _mm512_mask_abs_epi32 (__m512i s, __mmask 16 k, __m512i a);
VPABSD  __m512i _mm512_maskz_abs_epi32( __mmask16 k, __m512i a);VPABSQ __m512i _mm512_abs_epi64( __m512i a);VPABSQ __m512i _mm512_mask_abs_epi64( __m512i s, __mmask8 k, __m512i a);
VPABSQ __m512i _mm512_maskz_abs _epi64( __mmask8 k, __m512i a);
VPABSQ __m256i _mm256_mask_abs_epi64( __m256i s, __mmask8 k, __m256i a);
VPABSQ __m256i _mm256_maskz_abs _epi64( __mmask8 k, __m256i a);
VPABSQ __m128i _mm_mask_abs_epi64( __m128i s, __mmask8 k, __m128i a);
VPABSQ __m128i _mm_maskz_abs_epi64( __mmask8 k, __m128i a);PABSB __m128i _mm_abs_epi8 (__m128i a)PABSB/PABSW/PABSD/PABSQ—Packed Absolute ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-187VPABSB __m128i _mm_abs_epi8 (__m128i a)
VPABSB __m256i _mm256 _abs_epi8 (__m256i a)
PABSW __m128i _mm_abs_epi16 (__m128i a)VPABSW __m128i _mm_abs_epi16 (__m128i a)VPABSW __m256i _mm256_abs_epi16 (__m256i a)PABSD __m128i _mm_abs_epi32 (__m128i a)VPABSD __m128i _mm_abs_epi32 (__m128i a)VPABSD __m256i _mm256_abs_epi32 (__m256i a)
None.
EVEX-encoded VPABSD/Q, see Table 2-49, “Type E4 Class Exception Conditions.”
EVEX-encoded VPABSB/W, see Exceptions Type E4.nb in  Table 2-49, “Type E4 Class Exception Conditions.”PACKSSWB/PACKSSDW—Pack With Signed SaturationINSTRUCTION SET REFERENCE, M-U
4-188 Vol. 2BPACKSSWB/PACKSSDW—Pack Wi th Signed Saturation
Opcode/
NP 0F 63 /r1
PACKSSWB mm1, mm2/m64A V/V MMX Converts 4 packed signed word integers from mm1 
and from mm2/m64 into 8 packed signed byte integers in mm1 using signed saturation.
66 0F 63 /r
PACKSSWB xmm1, xmm2/m128A V/V SSE2 Converts 8 packed signed word integers from 
xmm1 and from xmm2/m128 into 16 packed 
signed byte integers in xmm1 using signed saturation.
NP 0F 6B /r
1
PACKSSDW mm1, mm2/m64A V/V MMX Converts 2 packed signed doubleword integers 
from mm1 and from mm2/m64 into 4 packed 
signed word integers in mm1 using signed saturation.
66 0F 6B /r
PACKSSDW xmm1, xmm2/m128A V/V SSE2 Converts 4 packed signed doubleword integers 
from xmm1 and from xmm2/m128 into 8 packed signed word integers in xmm1 using signed 
saturation.
VEX.128.66.0F.WIG 63 /r
VPACKSSWB xmm1,xmm2, xmm3/m128B V/V AVX Converts 8 packed signed word integers from 
xmm2 and from xmm3/m128 into 16 packed signed byte integers in xmm1 using signed 
VEX.128.66.0F.WIG 6B /r
VPACKSSDW xmm1,xmm2, xmm3/m128B V/V AVX Converts 4 packed signed doubleword integers 
from xmm2 and from xmm3/m128 into 8 packed signed word integers in xmm1 using signed 
VEX.256.66.0F
.WIG 63 /r
VPACKSSWB ymm1, ymm2, ymm3/m256B V/V AVX2 Converts 16 packed signed word integers from 
ymm2 and from ymm3/m 256 into 32 packed 
signed byte integers in ymm1 using signed 
VEX.256.66.0F .WIG 6B /r
VPACKSSDW ymm1, ymm2, ymm3/m256B V/V AVX2 Converts 8 packed signed doubleword integers 
from ymm2 and from ymm3/m256 into 16 packed signed word integers in ymm1using signed 
EVEX.128.66.0F.WIG 63 /r
VPACKSSWB xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWConverts packed signed word integers from xmm2 
and from xmm3/m128 into packed signed byte integers in xmm1 using signed saturation under 
EVEX.256.66.0F.WIG 63 /r
VPACKSSWB ymm1 {k1}{z}, ymm2, 
ymm3/m256C V/V AVX512VL
AVX512BWConverts packed signed word integers from ymm2 
and from ymm3/m256 into packed signed byte integers in ymm1 using signed saturation under 
EVEX.512.66.0F.WIG 63 /r
VPACKSSWB zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Converts packed signed word integers from zmm2 
and from zmm3/m512 into packed signed byte integers in zmm1 using signed saturation under 
EVEX.128.66.0F.W0 6B /r
VPACKSSDW xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstD V/V AVX512VL
AVX512BWConverts packed signed doubleword integers from 
xmm2 and from xmm3/m128/m32bcst into packed signed word integers in xmm1 using signed 
saturation under writemask k1.PACKSSWB/PACKSSDW—Pack With Signed SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-189Instruction Operand Encoding
Converts packed signed word integers into packed signed  byte integers (PACKSSWB) or converts packed signed 
doubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow condi-
tions. See Figure 4-6 for an example of the packing operation.
PACKSSWB converts packed signed word integers in the fi rst and second source operands into packed signed byte 
integers using signed saturation to handle overflow cond itions beyond the range of si gned byte integers. If the 
signed word value is beyond the range of a signed byte value (i.e., greater than 7FH or less than 80H), the satu-
rated signed byte integer value of 7FH or 80H, respecti vely, is stored in the destination. PACKSSDW converts 
packed signed doubleword integers in the first and second source operands into packed signed word integers using 
signed saturation to handle overflow conditions beyond 7FFFH and 8000H.
EVEX encoded PACKSSWB: The first source operand is a ZMM/YMM/XMM register. The second source operand is a 
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM 
register, updated conditional under the writemask k1.
EVEX encoded PACKSSDW: The first source operand is a ZMM/YMM/XMM register. The second source operand is a 
ZMM/YMM/XMM register, a 512/256/128-bit memory location , or a 512/256/128-bit vector broadcasted from a 32-EVEX.256.66.0F.W0 6B /r
VPACKSSDW ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcstD V/V AVX512VL
AVX512BWConverts packed signed do ubleword integers from 
ymm2 and from ymm3/m256/m32bcst into packed 
signed word integers in ymm1 using signed 
saturation under writemask k1.
EVEX.512.66.0F.W0 6B /r
VPACKSSDW zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstD V/V AVX512BW Converts packed sign ed doubleword integers from 
zmm2 and from zmm3/m512/m32bcst into packed 
signed word integers in zmm1 using signed 
NOTES:
ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception  Conditions of Legacy SIMD Instructions Operating on MMX Reg -
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

NOTES:
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
D Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Figure 4-6.  Operation of the PACK SSDW Instruction Usin g 64-Bit OperandsOpcode/
Mode 
D C64-Bit SRC
64-Bit DESTD’ C’ B’ A’64-Bit DEST
B APACKSSWB/PACKSSDW—Pack With Signed SaturationINSTRUCTION SET REFERENCE, M-U
4-190 Vol. 2Bbit memory location. The destination operand is a ZMM/ YMM/XMM register, updated conditional under the write-
mask k1.
corresponding ZMM register destination are zeroed. 
128-bit Legacy SSE version: The first source operand is  an XMM register. The second operand can be an XMM 
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the 
upper bits (MAXVL-1:128) of the corresponding ZM M destination register destination are unmodified.
Operation
PACKSSWB Instruction (128- bit Legacy SSE Version)
DEST[7:0] := SaturateSignedWo rdToSignedByte (DEST[15:0]);
DEST[15:8] := SaturateSignedWo rdToSignedByte (DEST[31:16]); 
DEST[23:16] := SaturateSignedWo rdToSignedByte (DEST[47:32]);
DEST[31:24] := SaturateSignedWo rdToSignedByte (DEST[63:48]);
DEST[39:32] := SaturateSignedWo rdToSignedByte (DEST[79:64]);
DEST[47:40] := SaturateSignedWo rdToSignedByte (DEST[95:80]);
DEST[55:48] := SaturateSignedWo rdToSignedByte (DEST[111:96]);
DEST[63:56] := SaturateSignedWo rdToSignedByte (DEST[127:112]);
DEST[71:64] := SaturateSignedWordToSignedByte (SRC[15:0]);DEST[79:72] := SaturateSignedWordToSignedByte (SRC[31:16]);DEST[87:80] := SaturateSignedWordToSignedByte (SRC[47:32]);DEST[95:88] := SaturateSignedWordToSignedByte (SRC[63:48]);DEST[103:96] := SaturateSigned WordToSignedByte (SRC[79:64]);
DEST[111:104] := SaturateSignedWordToSignedByte (SRC[95:80]);DEST[119:112] := SaturateSignedWordToSignedByte (SRC[111:96]);DEST[127:120] := SaturateSignedWordToSignedByte (SRC[127:112]);DEST[MAXVL-1:128] (Unmodified)
PACKSSDW Instruction (128-bit Legacy SSE Version)
DEST[15:0] := SaturateSignedDwordToSignedWord (DEST[31:0]);DEST[31:16] := SaturateSignedDwordToSignedWord (DEST[63:32]);DEST[47:32] := SaturateSignedDwordToSignedWord (DEST[95:64]);DEST[63:48] := SaturateSignedDw ordToSignedWord (DEST[127:96]);
DEST[79:64] := SaturateSignedDwordToSignedWord (SRC[31:0]);DEST[95:80] := SaturateSignedDwordToSignedWord (SRC[63:32]);DEST[111:96] := SaturateSignedDwordToSignedWord (SRC[95:64]);DEST[127:112] := SaturateSigned DwordToSignedWord (SRC[127:96]);
DEST[MAXVL-1:128] (Unmodified)PACKSSWB/PACKSSDW—Pack With Signed SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-191VPACKSSWB Instruction (VEX.128 Encoded Version)
DEST[7:0] := SaturateSignedWo rdToSignedByte (SRC1[15:0]);
DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]); DEST[23:16] := SaturateSignedWordToSignedByte (SRC1[47:32]);DEST[31:24] := SaturateSignedWordToSignedByte (SRC1[63:48]);DEST[39:32] := SaturateSignedWordToSignedByte (SRC1[79:64]);DEST[47:40] := SaturateSignedWordToSignedByte (SRC1[95:80]);DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);DEST[71:64] := SaturateSignedWordToSignedByte (SRC2[15:0]);DEST[79:72] := SaturateSignedWordToSignedByte (SRC2[31:16]);DEST[87:80] := SaturateSignedWordToSignedByte (SRC2[47:32]);DEST[95:88] := SaturateSignedWordToSignedByte (SRC2[63:48]);DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);DEST[MAXVL-1:128] := 0;
VPACKSSDW Instruction (VEX.128 Encoded Version)
DEST[15:0] := SaturateSignedDwordToSignedWord (SRC1[31:0]);DEST[31:16] := SaturateSignedDwordToSignedWord (SRC1[63:32]);DEST[47:32] := SaturateSignedDwordToSignedWord (SRC1[95:64]);DEST[63:48] := SaturateSignedDw ordToSignedWord (SRC1[127:96]);
DEST[79:64] := SaturateSignedDwordToSignedWord (SRC2[31:0]);DEST[95:80] := SaturateSignedDwordToSignedWord (SRC2[63:32]);DEST[111:96] := SaturateSigned DwordToSignedWord (SRC2[95:64]);
DEST[127:112] := SaturateSignedDwordToSignedWord (SRC2[127:96]);DEST[MAXVL-1:128] := 0;
VPACKSSWB Instruction (VEX.256 Encoded Version)
DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]); DEST[23:16] := SaturateSignedWordToSignedByte (SRC1[47:32]);DEST[31:24] := SaturateSignedWordToSignedByte (SRC1[63:48]);DEST[39:32] := SaturateSignedWordToSignedByte (SRC1[79:64]);DEST[47:40] := SaturateSignedWordToSignedByte (SRC1[95:80]);DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);DEST[71:64] := SaturateSignedWordToSignedByte (SRC2[15:0]);DEST[79:72] := SaturateSignedWordToSignedByte (SRC2[31:16]);DEST[87:80] := SaturateSignedWordToSignedByte (SRC2[47:32]);DEST[95:88] := SaturateSignedWordToSignedByte (SRC2[63:48]);DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);DEST[135:128] := SaturateSignedWordToSignedByte (SRC1[143:128]);DEST[143:136] := SaturateSignedWordToSignedByte (SRC1[159:144]); DEST[151:144] := SaturateSignedWordToSignedByte (SRC1[175:160]);DEST[159:152] := SaturateSignedWordToSignedByte (SRC1[191:176]);DEST[167:160] := SaturateSignedWordToSignedByte (SRC1[207:192]);DEST[175:168] := SaturateSignedWordToSignedByte (SRC1[223:208]);DEST[183:176] := SaturateSignedWordToSignedByte (SRC1[239:224]);PACKSSWB/PACKSSDW—Pack With Signed SaturationINSTRUCTION SET REFERENCE, M-U
4-192 Vol. 2BDEST[191:184] := SaturateSignedWordToSignedByte (SRC1[255:240]);
DEST[199:192] := SaturateSignedWordToSignedByte (SRC2[143:128]);DEST[207:200] := SaturateSignedWordToSignedByte (SRC2[159:144]);DEST[215:208] := SaturateSignedWordToSignedByte (SRC2[175:160]);DEST[223:216] := SaturateSignedWordToSignedByte (SRC2[191:176]);DEST[231:224] := SaturateSignedWordToSignedByte (SRC2[207:192]);DEST[239:232] := SaturateSignedWordToSignedByte (SRC2[223:208]);DEST[247:240] := SaturateSignedWordToSignedByte (SRC2[239:224]);DEST[255:248] := SaturateSignedWordToSignedByte (SRC2[255:240]);DEST[MAXVL-1:256] := 0;
VPACKSSDW Instruction (VEX.256 Encoded Version)
DEST[79:64] := SaturateSignedDwordToSignedWord (SRC2[31:0]);DEST[95:80] := SaturateSignedDwordToSignedWord (SRC2[63:32]);DEST[111:96] := SaturateSignedDwordToSignedWord (SRC2[95:64]);DEST[127:112] := SaturateSignedDwordToSignedWord (SRC2[127:96]);DEST[143:128] := SaturateSignedDwordToSignedWord (SRC1[159:128]);DEST[159:144] := SaturateSignedDwordToSignedWord (SRC1[191:160]);DEST[175:160] := SaturateSignedDwordToSignedWord (SRC1[223:192]);DEST[191:176] := SaturateSignedDwordToSignedWord (SRC1[255:224]);DEST[207:192] := SaturateSignedDwordToSignedWord (SRC2[159:128]);DEST[223:208] := SaturateSignedDwordToSignedWord (SRC2[191:160]);DEST[239:224] := SaturateSignedDwordToSignedWord (SRC2[223:192]);DEST[255:240] := SaturateSignedDwordToSignedWord (SRC2[255:224]);DEST[MAXVL-1:256] := 0;
VPACKSSWB (EVEX Encoded Versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)TMP_DEST[7:0] := SaturateSigned WordToSignedByte (SRC1[15:0]);
TMP_DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]); TMP_DEST[23:16] := SaturateSigned WordToSignedByte (SRC1[47:32]);
TMP_DEST[31:24] := SaturateSigned WordToSignedByte (SRC1[63:48]);
TMP_DEST[39:32] := SaturateSigned WordToSignedByte (SRC1[79:64]);
TMP_DEST[47:40] := SaturateSigned WordToSignedByte (SRC1[95:80]);
TMP_DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);TMP_DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);TMP_DEST[71:64] := SaturateSigned WordToSignedByte (SRC2[15:0]);
TMP_DEST[79:72] := SaturateSigned WordToSignedByte (SRC2[31:16]);
TMP_DEST[87:80] := SaturateSigned WordToSignedByte (SRC2[47:32]);
TMP_DEST[95:88] := SaturateSigned WordToSignedByte (SRC2[63:48]);

TMP_DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);TMP_DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);TMP_DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);TMP_DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);IF VL >= 256
TMP_DEST[135:128] := SaturateSignedWordToSignedByte (SRC1[143:128]);TMP_DEST[143:136] := SaturateSignedWordToSignedByte (SRC1[159:144]); TMP_DEST[151:144] := SaturateSignedWordToSignedByte (SRC1[175:160]);TMP_DEST[159:152] := SaturateSignedWordToSignedByte (SRC1[191:176]);TMP_DEST[167:160] := SaturateSignedWordToSignedByte (SRC1[207:192]);PACKSSWB/PACKSSDW—Pack With Signed SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-193TMP_DEST[175:168] := SaturateSignedWordToSignedByte (SRC1[223:208]);
TMP_DEST[183:176] := SaturateSignedWordToSignedByte (SRC1[239:224]);TMP_DEST[191:184] := SaturateSignedWordToSignedByte (SRC1[255:240]);TMP_DEST[199:192] := SaturateSignedWordToSignedByte (SRC2[143:128]);TMP_DEST[207:200] := SaturateSignedWordToSignedByte (SRC2[159:144]);TMP_DEST[215:208] := SaturateSignedWordToSignedByte (SRC2[175:160]);TMP_DEST[223:216] := SaturateSignedWordToSignedByte (SRC2[191:176]);TMP_DEST[231:224] := SaturateSignedWordToSignedByte (SRC2[207:192]);TMP_DEST[239:232] := SaturateSignedWordToSignedByte (SRC2[223:208]);TMP_DEST[247:240] := SaturateSignedWordToSignedByte (SRC2[239:224]);TMP_DEST[255:248] := SaturateSignedWordToSignedByte (SRC2[255:240]);
TMP_DEST[263:256] := SaturateSignedWordToSignedByte (SRC1[271:256]);TMP_DEST[271:264] := SaturateSignedWordToSignedByte (SRC1[287:272]); TMP_DEST[279:272] := SaturateSignedWordToSignedByte (SRC1[303:288]);TMP_DEST[287:280] := SaturateSignedWordToSignedByte (SRC1[319:304]);TMP_DEST[295:288] := SaturateSignedWordToSignedByte (SRC1[335:320]);TMP_DEST[303:296] := SaturateSignedWordToSignedByte (SRC1[351:336]);TMP_DEST[311:304] := SaturateSignedWordToSignedByte (SRC1[367:352]);TMP_DEST[319:312] := SaturateSignedWordToSignedByte (SRC1[383:368]);
TMP_DEST[327:320] := SaturateSignedWordToSignedByte (SRC2[271:256]);
TMP_DEST[335:328] := SaturateSignedWordToSignedByte (SRC2[287:272]); TMP_DEST[343:336] := SaturateSignedWordToSignedByte (SRC2[303:288]);TMP_DEST[351:344] := SaturateSignedWordToSignedByte (SRC2[319:304]);TMP_DEST[359:352] := SaturateSignedWordToSignedByte (SRC2[335:320]);TMP_DEST[367:360] := SaturateSignedWordToSignedByte (SRC2[351:336]);TMP_DEST[375:368] := SaturateSignedWordToSignedByte (SRC2[367:352]);TMP_DEST[383:376] := SaturateSignedWordToSignedByte (SRC2[383:368]);
TMP_DEST[391:384] := SaturateSignedWordToSignedByte (SRC1[399:384]);
TMP_DEST[399:392] := SaturateSignedWordToSignedByte (SRC1[415:400]);TMP_DEST[407:400] := SaturateSignedWordToSignedByte (SRC1[431:416]);TMP_DEST[415:408] := SaturateSignedWordToSignedByte (SRC1[447:432]);TMP_DEST[423:416] := SaturateSignedWordToSignedByte (SRC1[463:448]);TMP_DEST[431:424] := SaturateSignedWordToSignedByte (SRC1[479:464]);TMP_DEST[439:432] := SaturateSignedWordToSignedByte (SRC1[495:480]);TMP_DEST[447:440] := SaturateSignedWordToSignedByte (SRC1[511:496]);
TMP_DEST[455:448] := SaturateSignedWordToSignedByte (SRC2[399:384]);
TMP_DEST[463:456] := SaturateSignedWordToSignedByte (SRC2[415:400]);TMP_DEST[471:464] := SaturateSignedWordToSignedByte (SRC2[431:416]);TMP_DEST[479:472] := SaturateSignedWordToSignedByte (SRC2[447:432]);TMP_DEST[487:480] := SaturateSignedWordToSignedByte (SRC2[463:448]);TMP_DEST[495:488] := SaturateSignedWordToSignedByte (SRC2[479:464]);TMP_DEST[503:496] := SaturateSignedWordToSignedByte (SRC2[495:480]);TMP_DEST[511:504] := SaturateSignedWordToSignedByte (SRC2[511:496]);
THEN 
DEST[i+7:i] := TMP_DEST[i+7:i]PACKSSWB/PACKSSDW—Pack With Signed SaturationINSTRUCTION SET REFERENCE, M-U
4-194 Vol. 2BELSE 
FI
FI;
VPACKSSDW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO ((KL/2) - 1)
i := j * 32
THEN
TMP_SRC2[i+31:i] := SRC2[31:0]
ELSE 
TMP_SRC2[i+31:i] := SRC2[i+31:i]
FI;
ENDFOR;
TMP_DEST[15:0] := SaturateSign edDwordToSignedWord (SRC1[31:0]);
TMP_DEST[31:16] := SaturateSignedDwordToSignedWord (SRC1[63:32]);TMP_DEST[47:32] := SaturateSignedDwordToSignedWord (SRC1[95:64]);TMP_DEST[63:48] := SaturateSignedDwordToSignedWord (SRC1[127:96]);TMP_DEST[79:64] := SaturateSignedDwordToSignedWord (TMP_SRC2[31:0]);TMP_DEST[95:80] := SaturateSignedDw ordToSignedWord (TMP_SRC2[63:32]);
TMP_DEST[111:96] := SaturateSigned DwordToSignedWord (TMP_SRC2[95:64]);
TMP_DEST[127:112] := SaturateSignedDw ordToSignedWord (T MP_SRC2[127:96]);
IF VL >= 256
TMP_DEST[143:128] := SaturateSignedDwordToSignedWord (SRC1[159:128]);TMP_DEST[159:144] := SaturateSignedDwordToSignedWord (SRC1[191:160]);TMP_DEST[175:160] := SaturateSignedDwordToSignedWord (SRC1[223:192]);TMP_DEST[191:176] := SaturateSignedDwordToSignedWord (SRC1[255:224]);TMP_DEST[207:192] := SaturateSignedDw ordToSignedWord (TMP_SRC2[159:128]);
TMP_DEST[223:208] := SaturateSignedDw ordToSignedWord (TMP_SRC2[191:160]);
TMP_DEST[239:224] := SaturateSignedDw ordToSignedWord (TMP_SRC2[223:192]);
TMP_DEST[255:240] := SaturateSignedDw ordToSignedWord (TMP_SRC2[255:224]);
TMP_DEST[271:256] := SaturateSignedDwordToSignedWord (SRC1[287:256]);TMP_DEST[287:272] := SaturateSignedDwordToSignedWord (SRC1[319:288]);TMP_DEST[303:288] := SaturateSignedDwordToSignedWord (SRC1[351:320]);TMP_DEST[319:304] := SaturateSignedDwordToSignedWord (SRC1[383:352]);TMP_DEST[335:320] := SaturateSignedDw ordToSignedWord (TMP_SRC2[287:256]);
TMP_DEST[351:336] := SaturateSignedDw ordToSignedWord (TMP_SRC2[319:288]);
TMP_DEST[367:352] := SaturateSignedDw ordToSignedWord (TMP_SRC2[351:320]);
TMP_DEST[383:368] := SaturateSignedDw ordToSignedWord (TMP_SRC2[383:352]);
TMP_DEST[399:384] := SaturateSignedDwordToSignedWord (SRC1[415:384]);
TMP_DEST[415:400] := SaturateSignedDwordToSignedWord (SRC1[447:416]);TMP_DEST[431:416] := SaturateSignedDwordToSignedWord (SRC1[479:448]);PACKSSWB/PACKSSDW—Pack With Signed SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-195TMP_DEST[447:432] := SaturateSigned DwordToSignedWord (SRC1[511:480]);
TMP_DEST[463:448] := SaturateSignedDw ordToSignedWord (TMP_SRC2[415:384]);
TMP_DEST[479:464] := SaturateSignedDw ordToSignedWord (TMP_SRC2[447:416]);
TMP_DEST[495:480] := SaturateSignedDw ordToSignedWord (TMP_SRC2[479:448]);
TMP_DEST[511:496] := SaturateSignedDw ordToSignedWord (TMP_SRC2[511:480]);
THEN DEST[i+15:i] := TMP_DEST[i+15:i]ELSE 
FI
FI;
VPACKSSDW__m512i _mm512_packs_epi32(__m512i m1, __m512i m2) ;
VPACKSSDW__m512i _mm512_mask_packs_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2) ;
VPACKSSDW__m512i _mm512_maskz_packs_epi32( __mmask32 k, __m512i m1, __m512i m2) ;
VPACKSSDW__m256i _mm256_mask_packs_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2) ;
VPACKSSDW__m256i _mm256_maskz_packs_epi32( __mmask16 k, __m256i m1, __m256i m2) ;
VPACKSSDW__m128i _mm_mask_packs_epi32( __m12 8i s, __mmask8 k, __m128i m1, __m128i m2) ;
VPACKSSDW__m128i _mm_maskz_packs_epi32(  __mmask8 k, __m128i m1, __m128i m2) ;
VPACKSSWB__m512i _mm512_packs_epi16(__m512i m1, __m512i m2) ;
VPACKSSWB__m512i _mm512_mask_packs_epi16(__m512i s, __mmask32 k, __m512i m1, __m512i m2) ;
VPACKSSWB__m512i _mm512_maskz_packs_epi16 ( __mmask32 k, __m512i m1, __m512i m2) ;
VPACKSSWB__m256i _mm256_mask_packs_epi16( __m256i s, __mmask16 k, __m256i m1, __m256i m2) ;
VPACKSSWB__m256i _mm256_maskz_packs_epi16 ( __mmask16 k, __m256i m1, __m256i m2) ;
VPACKSSWB__m128i _mm_mask_packs_epi16( __m128 i s, __mmask8 k, __m128i m1, __m128i m2) ;
VPACKSSWB__m128i _mm_maskz_packs_epi16(  __mmask8 k, __m128i m1, __m128i m2) ;
PACKSSWB __m128i _mm_packs_epi16(__m128i m1, __m128i m2)
PACKSSDW __m128i _mm_packs_epi32(__m128i m1, __m128i m2)VPACKSSWB __m256i _mm256_packs_epi16(__m256i m1, __m256i m2)VPACKSSDW __m256i _mm256_packs_epi32(__m256i m1, __m256i m2)
None.
EVEX-encoded VPACKSSDW, see Table 2-50, “Type E4NF Class Exception Conditions.”EVEX-encoded VPACKSSWB, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”PACKUSDW—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-196 Vol. 2BPACKUSDW—Pack With Unsigned Saturation 
Converts packed signed doubleword integers in the first and second source operands into packed unsigned word 
integers using unsigned saturation to handle overflow co nditions. If the signed doub leword value is beyond the

None.
integers using unsigned saturation to handle overflow co nditions. If the signed doub leword value is beyond the 
range of an unsigned word (that is, greater than FFFFH or  less than 0000H), the saturated unsigned word integer 
value of FFFFH or 0000H, respectively, is stored in the destination.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a 
ZMM/YMM/XMM register, a 512/256/128-bit memory location , or a 512/256/128-bit vector broadcasted from a 32-
bit memory location. The destination operand is a ZMM register, updated conditionally under the writemask k1.
Mode 
66 0F 38 2B /r
PACKUSDW xmm1, xmm2/m128A V/V SSE4_1 Convert 4 packed signed doubleword integers from xmm1 
and 4 packed signed doubleword integers from xmm2/m128 
into 8 packed unsigned word integers in xmm1 using 
VEX.128.66.0F38 2B /r
VPACKUSDW xmm1,xmm2, 
xmm3/m128B V/V AVX Convert 4 packed signed doubleword integers from xmm2 
and 4 packed signed doubleword integers from xmm3/m128 
VEX.256.66.0F38 2B /r
VPACKUSDW ymm1, ymm2, 
ymm3/m256B V/V AVX2 Convert 8 packed signed doubleword integers from ymm2 
and 8 packed signed doubleword integers from ymm3/m256 
into 16 packed unsigned word  integers in ymm1 using 
EVEX.128.66.0F38.W0 2B /r
VPACKUSDW xmm1{k1}{z}, xmm2, 
xmm3/m128/m32bcstCV / V A V X 5 1 2 V L
AVX512BWConvert packed signed doubleword integers from xmm2 and 
packed signed doubleword integers from 
xmm3/m128/m32bcst into packed unsigned word integers in xmm1 using unsigned saturation under writemask k1.
EVEX.256.66.0F38.W0 2B /r
VPACKUSDW ymm1{k1}{z}, ymm2, 
ymm3/m256/m32bcstCV / V A V X 5 1 2 V L
AVX512BWConvert packed signed doubleword integers from ymm2 and 
ymm3/m256/m32bcst into packed unsigned word integers in ymm1 using unsigned saturation under writemask k1.
EVEX.512.66.0F38.W0 2B /r
VPACKUSDW zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512BW Convert packed signed doubleword integers from zmm2 and 
zmm3/m512/m32bcst into packed unsigned word integers in zmm1 using unsigned saturation under writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APACKUSDW—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-197128-bit Legacy SSE version: The first source operand is  an XMM register. The second operand can be an XMM 
upper bits (MAXVL-1:128) of the corresponding de stination register destination are unmodified.
Operation
PACKUSDW (Legacy SSE Instruction)
TMP[15:0] := (DEST[31:0] < 0) ? 0 : DEST[15:0];DEST[15:0] := (DEST[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;TMP[31:16] := (DEST[63:32] < 0) ? 0 : DEST[47:32];DEST[31:16] := (DEST[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;TMP[47:32] := (DEST[95:64] < 0) ? 0 : DEST[79:64];DEST[47:32] := (DEST[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;TMP[63:48] := (DEST[127:96] < 0) ? 0 : DEST[111:96];DEST[63:48] := (DEST[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;TMP[79:64] := (SRC[31:0] < 0) ? 0 : SRC[15:0];
DEST[79:64] := (SRC[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] := (SRC[63:32] < 0) ? 0 : SRC[47:32];DEST[95:80] := (SRC[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;TMP[111:96] := (SRC[95:64] < 0) ? 0 : SRC[79:64];DEST[111:96] := (SRC[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;TMP[127:112] := (SRC[127:96] < 0) ? 0 : SRC[111:96];DEST[127:112] := (SRC[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;DEST[MAXVL-1:128 ] (Unmodified)
PACKUSDW (VEX.128 Encoded Version)
TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;TMP[79:64] := (SRC2[31:0] < 0) ? 0 : SRC2[15:0];DEST[79:64] := (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;TMP[95:80] := (SRC2[63:32] < 0) ? 0 : SRC2[47:32];DEST[95:80] := (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;TMP[111:96] := (SRC2[95:64] < 0) ? 0 : SRC2[79:64];DEST[111:96] := (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;TMP[127:112] := (SRC2[127:96] < 0) ? 0 : SRC2[111:96];DEST[127:112] := (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112];DEST[MAXVL-1:128] := 0;
VPACKUSDW (VEX.256 Encoded Version)
TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;TMP[79:64] := (SRC2[31:0] < 0) ? 0 : SRC2[15:0];DEST[79:64] := (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;PACKUSDW—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-198 Vol. 2BTMP[95:80] := (SRC2[63:32] < 0) ? 0 : SRC2[47:32];
DEST[95:80] := (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;TMP[111:96] := (SRC2[95:64] < 0) ? 0 : SRC2[79:64];DEST[111:96] := (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;TMP[127:112] := (SRC2[127:96] < 0) ? 0 : SRC2[111:96];DEST[127:112] := (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;TMP[143:128] := (SRC1[159:128] < 0) ? 0 : SRC1[143:128];DEST[143:128] := (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;TMP[159:144] := (SRC1[191:160] < 0) ? 0 : SRC1[175:160];DEST[159:144] := (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;TMP[175:160] := (SRC1[223:192] < 0) ? 0 : SRC1[207:192];DEST[175:160] := (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;TMP[191:176] := (SRC1[255:224] < 0) ? 0 : SRC1[239:224];DEST[191:176] := (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;TMP[207:192] := (SRC2[159:128] < 0) ? 0 : SRC2[143:128];DEST[207:192] := (SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;TMP[223:208] := (SRC2[191:160] < 0) ? 0 : SRC2[175:160];DEST[223:208] := (SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;TMP[239:224] := (SRC2[223:192] < 0) ? 0 : SRC2[207:192];DEST[239:224] := (SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;TMP[255:240] := (SRC2[255:224] < 0) ? 0 : SRC2[239:224];DEST[255:240] := (SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;DEST[MAXVL-1:256] := 0;
VPACKUSDW (EVEX Encoded Versions)
i := j * 32
THEN
ELSE 
FI;
ENDFOR;
TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;TMP[79:64] := (TMP_SRC2[31:0] < 0) ? 0 : TMP_SRC2[15:0];DEST[79:64] := (TMP_SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;TMP[95:80] := (TMP_SRC2[63:32]  < 0) ? 0 : TMP_SRC2[47:32];
DEST[95:80] := (TMP_SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;TMP[111:96] := (TMP_SRC2[95:64] < 0) ? 0 : TMP_SRC2[79:64];DEST[111:96] := (TMP_SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;TMP[127:112] := (TMP_SRC2[127:96]  < 0) ? 0 : TMP_SRC2[111:96];
DEST[127:112] := (TMP_SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
IF VL >= 256PACKUSDW—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-199TMP[143:128] := (SRC1[159:128] < 0) ? 0 : SRC1[143:128];
DEST[143:128] := (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;
TMP[159:144] := (SRC1[191:160] < 0) ? 0 : SRC1[175:160];DEST[159:144] := (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;
TMP[175:160] := (SRC1[223:192] < 0) ? 0 : SRC1[207:192];DEST[175:160] := (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;
TMP[191:176] := (SRC1[255:224] < 0) ? 0 : SRC1[239:224];DEST[191:176] := (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;

TMP[207:192] := (TMP_SRC2[159:128]  < 0) ? 0 : TMP_SRC2[143:128];
DEST[207:192] := (TMP_SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;TMP[223:208] := (TMP_SRC2[191:160]  < 0) ? 0 : TMP_SRC2[175:160];
DEST[223:208] := (TMP_SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;TMP[239:224] := (TMP_SRC2[223:192]  < 0) ? 0 : TMP_SRC2[207:192];
DEST[239:224] := (TMP_SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;TMP[255:240] := (TMP_SRC2[255:224]  < 0) ? 0 : TMP_SRC2[239:224];
DEST[255:240] := (TMP_SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;
TMP[271:256] := (SRC1[287:256] < 0) ? 0 : SRC1[271:256];DEST[271:256] := (SRC1[287:256] > FFFFH) ? FFFFH : TMP[271:256] ;
TMP[287:272] := (SRC1[319:288] < 0) ? 0 : SRC1[303:288];DEST[287:272] := (SRC1[319:288] > FFFFH) ? FFFFH : TMP[287:272] ;
TMP[303:288] := (SRC1[351:320] < 0) ? 0 : SRC1[335:320];DEST[303:288] := (SRC1[351:320] > FFFFH) ? FFFFH : TMP[303:288] ;
TMP[319:304] := (SRC1[383:352] < 0) ? 0 : SRC1[367:352];DEST[319:304] := (SRC1[383:352] > FFFFH) ? FFFFH : TMP[319:304] ;
TMP[335:320] := (TMP_SRC2[287:256]  < 0) ? 0 : TMP_SRC2[271:256];
DEST[335:304] := (TMP_SRC2[287:256] > FFFFH) ? FFFFH : TMP[79:64] ;TMP[351:336] := (TMP_SRC2[319:288]  < 0) ? 0 : TMP_SRC2[303:288];
DEST[351:336] := (TMP_SRC2[319:288] > FFFFH) ? FFFFH : TMP[351:336] ;TMP[367:352] := (TMP_SRC2[351:320]  < 0) ? 0 : TMP_SRC2[315:320];
DEST[367:352] := (TMP_SRC2[351:320] > FFFFH) ? FFFFH : TMP[367:352] ;TMP[383:368] := (TMP_SRC2[383:352]  < 0) ? 0 : TMP_SRC2[367:352];
DEST[383:368] := (TMP_SRC2[383:352] > FFFFH) ? FFFFH : TMP[383:368] ;TMP[399:384] := (SRC1[415:384] < 0) ? 0 : SRC1[399:384];DEST[399:384] := (SRC1[415:384] > FFFFH) ? FFFFH : TMP[399:384] ;
TMP[415:400] := (SRC1[447:416] < 0) ? 0 : SRC1[431:416];DEST[415:400] := (SRC1[447:416] > FFFFH) ? FFFFH : TMP[415:400] ;
TMP[431:416] := (SRC1[479:448] < 0) ? 0 : SRC1[463:448];DEST[431:416] := (SRC1[479:448] > FFFFH) ? FFFFH : TMP[431:416] ;
TMP[447:432] := (SRC1[511:480] < 0) ? 0 : SRC1[495:480];DEST[447:432] := (SRC1[511:480] > FFFFH) ? FFFFH : TMP[447:432] ;
TMP[463:448] := (TMP_SRC2[415:384]  < 0) ? 0 : TMP_SRC2[399:384];
DEST[463:448] := (TMP_SRC2[415:384] > FFFFH) ? FFFFH : TMP[463:448] ;TMP[475:464] := (TMP_SRC2[447:416]  < 0) ? 0 : TMP_SRC2[431:416];
DEST[475:464] := (TMP_SRC2[447:416] > FFFFH) ? FFFFH : TMP[475:464] ;TMP[491:476] := (TMP_SRC2[479:448]  < 0) ? 0 : TMP_SRC2[463:448];
DEST[491:476] := (TMP_SRC2[479:448] > FFFFH) ? FFFFH : TMP[491:476] ;TMP[511:492] := (TMP_SRC2[511:480]  < 0) ? 0 : TMP_SRC2[495:480];
DEST[511:492] := (TMP_SRC2[511:480] > FFFFH) ? FFFFH : TMP[511:492] ;
i := j * 16IF k1[j] OR *no writemask*PACKUSDW—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-200 Vol. 2BTHEN 
DEST[i+15:i] := TMP_DEST[i+15:i]
ELSE 
FI
FI;
VPACKUSDW__m512i _mm512_packus_epi32(__m512i m1, __m512i m2) ;
VPACKUSDW__m512i _mm512_mask_packus_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2) ;
VPACKUSDW__m512i _mm512_maskz_packus_epi32( __mmask32 k, __m512i m1, __m512i m2) ;
VPACKUSDW__m256i _mm256_mask_packus_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2) ;
VPACKUSDW__m256i _mm256_maskz_packus_epi32( __mmask16 k, __m256i m1, __m256i m2) ;
VPACKUSDW__m128i _mm_mask_packus_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2) ;
VPACKUSDW__m128i _mm_maskz_packus_epi32( __mmask8 k, __m128i m1, __m128i m2) ;
PACKUSDW__m128i _mm_packus_epi 32(__m128i m1, __m128i m2) ;
VPACKUSDW__m256i _mm256_packus_epi32(__m256i m1, __m256i m2) ;
None.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”PACKUSWB—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-201PACKUSWB—Pack With Unsigned Saturation
Converts 4, 8, 16, or 32 signed word integers from th e destination operand (first operand) and 4, 8, 16, or 32 
signed word integers from the source operand (second oper and) into 8, 16, 32 or 64 unsigned byte integers and 
stores the result in the destination operand. (See Figure 4- 6 for an example of the pack ing operation.) If a signed 
word integer value is beyond the range of an unsigned byte  integer (that is, greater than FFH or less than 00H), the 
saturated unsigned byte integer value of FFH or 00H, respectively, is stored in the destination.
EVEX.512 encoded version: The first source operand is  a ZMM register. The second source operand is a ZMM 
register or a 512-bit memory location. The destination operand is a ZMM register.Opcode/
Mode 
NP 0F 67 /r1
PACKUSWB mm, mm/m64
NOTES:
Registers,” in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.A V/V MMX Converts 4 signed word integers from mm and 
4 signed word integers from mm/m64 into 8 
unsigned byte integers in mm using unsigned 
66 0F 67 /r
PACKUSWB xmm1, xmm2/m128A V/V SSE2 Converts 8 signed word integers from xmm1 
and 8 signed word integers from xmm2/m128 
into 16 unsigned byte integers in xmm1 using 
VEX.128.66.0F.WIG 67 /r
VPACKUSWB xmm1, xmm2, xmm3/m128B V/V AVX Converts 8 signed word integers from xmm2 
and 8 signed word integers from xmm3/m128 
VEX.256.66.0F.WIG 67 /r
VPACKUSWB ymm1, ymm2, ymm3/m256B V/V AVX2 Converts 16 signed word integers from ymm2 
and 16signed word integers from ymm3/m256 
into 32 unsigned byte integers in ymm1 using 
EVEX.128.66.0F.WIG 67 /r
VPACKUSWB xmm1{k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWConverts signed word in tegers from xmm2 and 
signed word integers from xmm3/m128 into 
unsigned byte integers in xmm1 using unsigned saturation unde r writemask k1.
EVEX.256.66.0F.WIG 67 /r
VPACKUSWB ymm1{k1}{z }, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWConverts signed word in tegers from ymm2 and 
signed word integers from ymm3/m256 into 
unsigned byte integers in ymm1 using unsigned saturation unde r writemask k1.
EVEX.512.66.0F.WIG 67 /r
VPACKUSWB zmm1{k1}{z }, zmm2, zmm3/m512C V/V AVX512BW Converts signed wo rd integers from zmm2 and 
signed word integers from zmm3/m512 into 
unsigned byte integers in zmm1 using unsigned saturation unde r writemask k1.
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APACKUSWB—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-202 Vol. 2BVEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand 
is a YMM register or a 256-bit memory location. The dest ination operand is a YMM register. The upper bits (MAXVL-
1:256) of the corresponding ZMM register destination are zeroed. 
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand 
is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-
1:128) of the corresponding register destination are zeroed.
Operation
PACKUSWB (With 64-bit Operands)
DEST[7:0] := SaturateSignedWordToUnsignedByte DEST[15:0]; DEST[15:8] := SaturateSignedWordToUnsignedByte DEST[31:16];DEST[23:16] := SaturateSignedWordToUnsignedByte DEST[47:32];DEST[31:24] := SaturateSignedWordToUnsignedByte DEST[63:48];DEST[39:32] := SaturateSignedWordToUnsignedByte SRC[15:0];DEST[47:40] := SaturateSignedWordToUnsignedByte SRC[31:16];DEST[55:48] := SaturateSignedWordToUnsignedByte SRC[47:32];DEST[63:56] := SaturateSignedWordToUnsignedByte SRC[63:48];
PACKUSWB (Legacy SSE Instruction)
DEST[7:0] := SaturateSignedWordToUnsignedByte (DEST[15:0]);DEST[15:8] := SaturateSignedWordToUnsignedByte (DEST[31:16]);DEST[23:16] := SaturateSignedWo rdToUnsignedByte (DEST[47:32]);
DEST[31:24] := SaturateSignedWo rdToUnsignedByte (DEST[63:48]);
DEST[39:32] := SaturateSignedWo rdToUnsignedByte (DEST[79:64]);
DEST[47:40] := SaturateSignedWo rdToUnsignedByte (DEST[95:80]);
DEST[55:48] := SaturateSignedWo rdToUnsignedByte (DEST[111:96]);

Operation
DEST[63:56] := SaturateSignedWord ToUnsignedByte (DEST[127:112]);
DEST[71:64] := SaturateSignedWordToUnsignedByte (SRC[15:0]);DEST[79:72] := SaturateSignedWo rdToUnsignedByte (SRC[31:16]);
DEST[87:80] := SaturateSignedWo rdToUnsignedByte (SRC[47:32]);
DEST[95:88] := SaturateSignedWo rdToUnsignedByte (SRC[63:48]);
DEST[103:96] := SaturateSigned WordToUnsignedByte (SRC[79:64]);
DEST[111:104] := SaturateSignedWo rdToUnsignedByte (SRC[95:80]);
DEST[119:112] := SaturateSignedWo rdToUnsignedByte (SRC[111:96]);
DEST[127:120] := SaturateSignedWo rdToUnsignedByte (SRC[127:112]);
PACKUSWB (VEX.128 Encoded Version)
DEST[7:0] := SaturateSignedWord ToUnsignedByte (SRC1[15:0]);
DEST[15:8] := SaturateSignedWordToUnsignedByte (SRC1[31:16]);DEST[23:16] := SaturateSignedWordToUnsignedByte (SRC1[47:32]);DEST[31:24] := SaturateSignedWordToUnsignedByte (SRC1[63:48]);DEST[39:32] := SaturateSignedWordToUnsignedByte (SRC1[79:64]);DEST[47:40] := SaturateSignedWordToUnsignedByte (SRC1[95:80]);DEST[55:48] := SaturateSignedWordToUnsignedByte (SRC1[111:96]);DEST[63:56] := SaturateSignedWordToUnsignedByte (SRC1[127:112]);DEST[71:64] := SaturateSignedWordToUnsignedByte (SRC2[15:0]);DEST[79:72] := SaturateSignedWordToUnsignedByte (SRC2[31:16]);DEST[87:80] := SaturateSignedWordToUnsignedByte (SRC2[47:32]);DEST[95:88] := SaturateSignedWordToUnsignedByte (SRC2[63:48]);DEST[103:96] := SaturateSignedWordToUnsignedByte (SRC2[79:64]);DEST[111:104] := SaturateSignedWordToUnsignedByte (SRC2[95:80]);PACKUSWB—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-203DEST[119:112] := SaturateSignedWordToUnsignedByte (SRC2[111:96]);
DEST[127:120] := SaturateSignedWordToUnsignedByte (SRC2[127:112]);DEST[MAXVL-1:128] := 0;
VPACKUSWB (VEX.256 Encoded Version)
DEST[15:8] := SaturateSignedWordToUnsignedByte (SRC1[31:16]);DEST[23:16] := SaturateSignedWordToUnsignedByte (SRC1[47:32]);DEST[31:24] := SaturateSignedWordToUnsignedByte (SRC1[63:48]);DEST[39:32] := SaturateSignedWordToUnsignedByte (SRC1[79:64]);DEST[47:40] := SaturateSignedWordToUnsignedByte (SRC1[95:80]);DEST[55:48] := SaturateSignedWordToUnsignedByte (SRC1[111:96]);DEST[63:56] := SaturateSignedWordToUnsignedByte (SRC1[127:112]);DEST[71:64] := SaturateSignedWordToUnsignedByte (SRC2[15:0]);DEST[79:72] := SaturateSignedWordToUnsignedByte (SRC2[31:16]);DEST[87:80] := SaturateSignedWordToUnsignedByte (SRC2[47:32]);DEST[95:88] := SaturateSignedWordToUnsignedByte (SRC2[63:48]);DEST[103:96] := SaturateSignedWordToUnsignedByte (SRC2[79:64]);DEST[111:104] := SaturateSignedWordToUnsignedByte (SRC2[95:80]);DEST[119:112] := SaturateSignedWordToUnsignedByte (SRC2[111:96]);DEST[127:120] := SaturateSignedWordToUnsignedByte (SRC2[127:112]);DEST[135:128] := SaturateSignedWordToUnsignedByte (SRC1[143:128]);DEST[143:136] := SaturateSignedWordToUnsignedByte (SRC1[159:144]);DEST[151:144] := SaturateSignedWordToUnsignedByte (SRC1[175:160]);DEST[159:152] := SaturateSignedWordToUnsignedByte (SRC1[191:176]);DEST[167:160] := SaturateSignedWordToUnsignedByte (SRC1[207:192]);DEST[175:168] := SaturateSignedWordToUnsignedByte (SRC1[223:208]);DEST[183:176] := SaturateSignedWordToUnsignedByte (SRC1[239:224]);DEST[191:184] := SaturateSignedWordToUnsignedByte (SRC1[255:240]);DEST[199:192] := SaturateSignedWordToUnsignedByte (SRC2[143:128]);DEST[207:200] := SaturateSignedWordToUnsignedByte (SRC2[159:144]);DEST[215:208] := SaturateSignedWordToUnsignedByte (SRC2[175:160]);DEST[223:216] := SaturateSignedWordToUnsignedByte (SRC2[191:176]);DEST[231:224] := SaturateSignedWordToUnsignedByte (SRC2[207:192]);DEST[239:232] := SaturateSignedWordToUnsignedByte (SRC2[223:208]);DEST[247:240] := SaturateSignedWordToUnsignedByte (SRC2[239:224]);DEST[255:248] := SaturateSignedWordToUnsignedByte (SRC2[255:240]);
VPACKUSWB (EVEX Encoded Versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)TMP_DEST[7:0] := SaturateSignedWo rdToUnsignedByte (SRC1[15:0]);
TMP_DEST[15:8] := SaturateSigned WordToUnsignedByte (SRC1[31:16]); 
TMP_DEST[23:16] := SaturateSigned WordToUnsignedByte (SRC1[47:32]);
TMP_DEST[31:24] := SaturateSigned WordToUnsignedByte (SRC1[63:48]);
TMP_DEST[39:32] := SaturateSigned WordToUnsignedByte (SRC1[79:64]);
TMP_DEST[47:40] := SaturateSigned WordToUnsignedByte (SRC1[95:80]);
TMP_DEST[55:48] := SaturateSignedWo rdToUnsignedByte (SRC1[111:96]);
TMP_DEST[63:56] := SaturateSignedWordToUnsignedByte (SRC1[127:112]);TMP_DEST[71:64] := SaturateSigned WordToUnsignedByte (SRC2[15:0]);
TMP_DEST[79:72] := SaturateSigned WordToUnsignedByte (SRC2[31:16]);
TMP_DEST[87:80] := SaturateSigned WordToUnsignedByte (SRC2[47:32]);
TMP_DEST[95:88] := SaturateSigned WordToUnsignedByte (SRC2[63:48]);
TMP_DEST[103:96] := SaturateSigned WordToUnsignedByte (SRC2[79:64]);
TMP_DEST[111:104] := SaturateSignedWordToUnsignedByte (SRC2[95:80]);PACKUSWB—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-204 Vol. 2BTMP_DEST[119:112] := SaturateSignedWordToUnsignedByte (SRC2[111:96]);
TMP_DEST[127:120] := SaturateSignedWordToUnsignedByte (SRC2[127:112]);IF VL >= 256
TMP_DEST[135:128] := SaturateSignedWordToUnsignedByte (SRC1[143:128]);TMP_DEST[143:136] := SaturateSignedWordToUnsignedByte (SRC1[159:144]); TMP_DEST[151:144] := SaturateSignedWordToUnsignedByte (SRC1[175:160]);TMP_DEST[159:152] := SaturateSignedWordToUnsignedByte (SRC1[191:176]);TMP_DEST[167:160] := SaturateSignedWordToUnsignedByte (SRC1[207:192]);TMP_DEST[175:168] := SaturateSignedWordToUnsignedByte (SRC1[223:208]);TMP_DEST[183:176] := SaturateSignedWordToUnsignedByte (SRC1[239:224]);TMP_DEST[191:184] := SaturateSignedWordToUnsignedByte (SRC1[255:240]);TMP_DEST[199:192] := SaturateSignedWordToUnsignedByte (SRC2[143:128]);TMP_DEST[207:200] := SaturateSignedWordToUnsignedByte (SRC2[159:144]);TMP_DEST[215:208] := SaturateSignedWordToUnsignedByte (SRC2[175:160]);TMP_DEST[223:216] := SaturateSignedWordToUnsignedByte (SRC2[191:176]);TMP_DEST[231:224] := SaturateSignedWordToUnsignedByte (SRC2[207:192]);TMP_DEST[239:232] := SaturateSignedWordToUnsignedByte (SRC2[223:208]);TMP_DEST[247:240] := SaturateSignedWordToUnsignedByte (SRC2[239:224]);TMP_DEST[255:248] := SaturateSignedWordToUnsignedByte (SRC2[255:240]);
TMP_DEST[263:256] := SaturateSignedWordToUnsignedByte (SRC1[271:256]);TMP_DEST[271:264] := SaturateSignedWordToUnsignedByte (SRC1[287:272]); TMP_DEST[279:272] := SaturateSignedWordToUnsignedByte (SRC1[303:288]);TMP_DEST[287:280] := SaturateSignedWordToUnsignedByte (SRC1[319:304]);TMP_DEST[295:288] := SaturateSignedWordToUnsignedByte (SRC1[335:320]);TMP_DEST[303:296] := SaturateSignedWordToUnsignedByte (SRC1[351:336]);TMP_DEST[311:304] := SaturateSignedWordToUnsignedByte (SRC1[367:352]);TMP_DEST[319:312] := SaturateSignedWordToUnsignedByte (SRC1[383:368]);
TMP_DEST[327:320] := SaturateSignedWordToUnsignedByte (SRC2[271:256]);
TMP_DEST[335:328] := SaturateSignedWordToUnsignedByte (SRC2[287:272]); TMP_DEST[343:336] := SaturateSignedWordToUnsignedByte (SRC2[303:288]);TMP_DEST[351:344] := SaturateSignedWordToUnsignedByte (SRC2[319:304]);TMP_DEST[359:352] := SaturateSignedWordToUnsignedByte (SRC2[335:320]);TMP_DEST[367:360] := SaturateSignedWordToUnsignedByte (SRC2[351:336]);TMP_DEST[375:368] := SaturateSignedWordToUnsignedByte (SRC2[367:352]);TMP_DEST[383:376] := SaturateSignedWordToUnsignedByte (SRC2[383:368]);
TMP_DEST[391:384] := SaturateSignedWordToUnsignedByte (SRC1[399:384]);
TMP_DEST[399:392] := SaturateSignedWordToUnsignedByte (SRC1[415:400]);TMP_DEST[407:400] := SaturateSignedWordToUnsignedByte (SRC1[431:416]);TMP_DEST[415:408] := SaturateSignedWordToUnsignedByte (SRC1[447:432]);TMP_DEST[423:416] := SaturateSignedWordToUnsignedByte (SRC1[463:448]);TMP_DEST[431:424] := SaturateSignedWordToUnsignedByte (SRC1[479:464]);TMP_DEST[439:432] := SaturateSignedWordToUnsignedByte (SRC1[495:480]);TMP_DEST[447:440] := SaturateSignedWordToUnsignedByte (SRC1[511:496]);
TMP_DEST[455:448] := SaturateSignedWordToUnsignedByte (SRC2[399:384]);
TMP_DEST[463:456] := SaturateSignedWordToUnsignedByte (SRC2[415:400]);TMP_DEST[471:464] := SaturateSignedWordToUnsignedByte (SRC2[431:416]);TMP_DEST[479:472] := SaturateSignedWordToUnsignedByte (SRC2[447:432]);TMP_DEST[487:480] := SaturateSignedWordToUnsignedByte (SRC2[463:448]);TMP_DEST[495:488] := SaturateSignedWordToUnsignedByte (SRC2[479:464]);PACKUSWB—Pack With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-205TMP_DEST[503:496] := SaturateSignedWordToUnsignedByte (SRC2[495:480]);
TMP_DEST[511:504] := SaturateSignedWordToUnsignedByte (SRC2[511:496]);
THEN 
DEST[i+7:i] := TMP_DEST[i+7:i]
ELSE 
FI
FI;
VPACKUSWB __m512i _mm512_packus_epi16(__m512i m1, __m512i m2) ;

THEN 
ELSE 
FI
FI;
VPACKUSWB __m512i _mm512_mask_packus_epi16(__m51 2i s, __mmask64 k, __m512i m1, __m512i m2) ;
VPACKUSWB __m512i _mm512_mas kz_packus_epi16(__mmask64 k, __m512i m1, __m512i m2) ;
VPACKUSWB __m256i _mm256_mask_packus_epi16(__m25 6i s, __mmask32 k, __m256i m1, __m256i m2) ;
VPACKUSWB __m256i _mm256_mas kz_packus_epi16(__mmask32 k, __m256i m1, __m256i m2) ;
VPACKUSWB __m128i _mm_mask_packus_epi16(__m128i  s, __mmask16 k, __m128i m1, __m128i m2) ;
VPACKUSWB __m128i _mm_mask z_packus_epi16(__mmask16 k, __m128i m1, __m128i m2) ;
PACKUSWB __m64 _mm_packs_pu16(__m64 m1, __m64 m2)
(V)PACKUSWB __m128i _mm_packus _epi16(__m128i m1, __m128i m2)
VPACKUSWB __m256i _mm256_packus_epi16(__m256i m1, __m256i m2);
None.
None.
EVEX-encoded instruction, see Exceptions Type E4NF.n b in Table 2-50, “Type E4NF Class Exception Conditions.”PADDB/PADDW/PADDD/PADDQ—Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-206 Vol. 2BPADDB/PADDW/PADDD/PADD Q—Add Packed Integers
Opcode/
Mode 
NP 0F FC /r1
PADDB mm, mm/m64A V/V MMX Add packed byte integers from mm/m64 and mm.
NP 0F FD /r1
PADDW mm, mm/m64A V/V MMX Add packed word inte gers from mm/m64 and mm.
NP 0F FE /r1
PADDD mm, mm/m64A V/V MMX Add packed doubleword integers from mm/m64 and 
mm.
NP 0F D4 /r1
PADDQ mm, mm/m64A V/V MMX Add packed quadword in tegers from mm/m64 and mm.
66 0F FC /r
PADDB xmm1, xmm2/m128A V/V SSE2 Add packed byte integers from xmm2/m128 and 
xmm1.
66 0F FD /r
PADDW xmm1, xmm2/m128A V/V SSE2 Add packed word integers from xmm2/m128 and 
xmm1.
66 0F FE /r
PADDD xmm1, xmm2/m128A V/V SSE2 Add packed doubleword integers from xmm2/m128 
and xmm1.
66 0F D4 /r
PADDQ xmm1, xmm2/m128A V/V SSE2 Add packed quadword integers from xmm2/m128 and 
xmm1.
VEX.128.66.0F.WIG FC /r
VPADDB xmm1, xmm2, xmm3/m128B V/V AVX Add packed byte integers from xmm2, and 
xmm3/m128 and store in xmm1.
VEX.128.66.0F.WIG FD /r
VPADDW xmm1, xmm2, xmm3/m128B V/V AVX Add packed word integers from xmm2, xmm3/m128 
and store in xmm1.
VEX.128.66.0F.WIG FE /r
VPADDD xmm1, xm m2, xmm3/m128B V/V AVX Add packed doubleword integers from xmm2, 
VEX.128.66.0F.WIG D4 /r
VPADDQ xmm1, xmm2, xmm3/m128B V/V AVX Add packed quadwo rd integers from xmm2, 
VEX.256.66.0F.WIG FC /r
VPADDB ymm1, ymm2, ymm3/m256B V/V AVX2 Add packed byte integers from ymm2, and 
ymm3/m256 and store in ymm1.
VEX.256.66.0F.WIG FD /r
VPADDW ymm1, ymm2, ymm3/m256B V/V AVX2 Add packed word integers from ymm2, ymm3/m256 
and store in ymm1.
VEX.256.66.0F.WIG FE /r
VPADDD ymm1, ymm2, ymm3/m256B V/V AVX2 Add packed doubleword integers from ymm2, 
VEX.256.66.0F.WIG D4 /r
VPADDQ ymm1, ymm2, ymm3/m256B V/V AVX2 Add packed quadword integers from ymm2, 
EVEX.128.66.0F.WIG FC /r
VPADDB xmm1 {k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWAdd packed byte integers from xmm2, and 
xmm3/m128 and store in xmm1 using writemask k1.
EVEX.128.66.0F.WIG FD /r
VPADDW xmm1 {k1}{z}, xmm2, 
xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWAdd packed word integers from xmm2, and 
EVEX.128.66.0F.W0 FE /r
VPADDD xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcstDV / V A V X 5 1 2 V L
AVX512FAdd packed doubleword integers from xmm2, and 
xmm3/m128/m32bcst and store in xmm1 using 
EVEX.128.66.0F.W1 D4 /r
VPADDQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstDV / V A V X 5 1 2 V L
AVX512FAdd packed quadword integers from xmm2, and 
xmm3/m128/m64bcst and store in xmm1 using writemask k1.PADDB/PADDW/PADDD/PADDQ—Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-207Instruction Operand Encoding
Performs a SIMD add of the packed integers from th e source operand (second operand) and the destination 
operand (first operand), and stores the packed integer re sults in the destination operand. See Figure 9-4 in the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation. 
Overflow is handled with wraparound, as described in the following paragraphs.
The PADDB and VPADDB instructions add packed byte integers from the firs t source operand and second source 
operand and store the packed integer results in the destinat ion operand. When an individual result is too large to 
be represented in 8 bits (overflow), the result is wrappe d around and the low 8 bits are written to the destination 
operand (that is, the carry is ignored).
The PADDW and VPADDW instructions add packed word inte gers from the first source operand and second source 
operand and store the packed integer results in the destinat ion operand. When an individual result is too large to EVEX.256.66.0F.WIG FC /r
VPADDB ymm1 {k1}{z}, ymm2, 
AVX512BWAdd packed byte integers from ymm2, and 
ymm3/m256 and store in ymm1 using writemask k1.
EVEX.256.66.0F.WIG FD /r
VPADDW ymm1 {k1}{z}, ymm2, ymm3/m256C V/V AVX512VL
AVX512BWAdd packed word integers from ymm2, and 
EVEX.256.66.0F.W0 FE /r
VPADDD ymm1 {k1}{z}, ymm2, 
AVX512FAdd packed doubleword integers from ymm2, 
ymm3/m256/m32bcst and store in ymm1 using 
EVEX.256.66.0F.W1 D4 /r
VPADDQ ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcstD V/V AVX512VL
AVX512FAdd packed quadword integers from ymm2, 
ymm3/m256/m64bcst and store in ymm1 using 
EVEX.512.66.0F.WIG FC /r
VPADDB zmm1 {k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Add packed byte integers from zmm2, and zmm3/m512 
and store in zmm1 using writemask k1.
EVEX.512.66.0F.WIG FD /r
VPADDW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Add packed word  integers from zmm2, and 
zmm3/m512 and store in zmm1 using writemask k1.
EVEX.512.66.0F.W0 FE /r
VPADDD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst D V/V AVX512F Add packed doubleword integers from zmm2, 
zmm3/m512/m32bcst and store in zmm1 using 
EVEX.512.66.0F.W1 D4 /r
VPADDQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstD V/V AVX512F Add packed quadword integers from zmm2, 
zmm3/m512/m64bcst and store in zmm1 using 
NOTES:
ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg -
CF u l l  M e m M o d R M : r e g  ( w ) E V E X.vvvv (r) ModRM:r/m (r) N/A
D Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AOpcode/
Mode 
Feature FlagDescriptionPADDB/PADDW/PADDD/PADDQ—Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-208 Vol. 2Bbe represented in 16 bits (overflow), the result is wrapped around and the low 16 bits are written to the destination 
The PADDD and VPADDD instructions add packed doubleword  integers from the first source operand and second 
source operand and store the packed integer results in the destination operand. When an individual result is too 
large to be represented in 32 bits (overflow), the result is wrapped around and the low 32 bits are written to the 
destination operand (that is, the carry is ignored).
The PADDQ and VPADDQ instructions ad d packed quadword integers from the first source operand and second 
source operand and store the packed integer results in th e destination operand. When a quadword result is too 
large to be represented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the 
Note that the (V)PADDB, (V)PADDW, (V )PADDD and (V)PADDQ instructions can operate on either unsigned or 
signed (two's complement notation) packed integers; however,  it does not set bits in the EFLAGS register to indi-
cate overflow and/or a carry. To prevent undetected over flow conditions, software must control the ranges of 
values operated on.
EVEX encoded VPADDD/Q: The first source operand is a ZMM/YMM/XMM register. The second source operand is a 
ZMM/YMM/XMM register, a 512/256/128-bit memory locati on or a 512/256/128-bit vector broadcasted from a 
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the write-
mask.
EVEX encoded VPADDB/W: The first sour ce operand is a ZMM/YMM/XMM register. The second source operand is a 
ZMM/YMM/XMM register, a 512/256/128-bit memory lo cation. The destination operand is a ZMM/YMM/XMM 
register updated according to the writemask.

mask.
or a 256-bit memory location. The destination operand is a YMM register. the upper bits (MAXVL-1:256) of the 
destination are cleared.
upper bits (MAXVL-1:128) of the correspondi ng ZMM register destination are unmodified.
Operation
PADDB (With 64-bit Operands)
DEST[7:0] := DEST[7:0] + SRC[7:0]; 
(* Repeat add operation for 2nd through 7th byte *)DEST[63:56] := DEST[63:56] + SRC[63:56];
PADDW (With 64-bit Operands)
DEST[15:0] := DEST[15:0] + SRC[15:0];
(* Repeat add operation for 2nd and 3th word *)DEST[63:48] := DEST[63:48] + SRC[63:48];
PADDD (With 64-bit Operands)
DEST[31:0] := DEST[31:0] + SRC[31:0];
DEST[63:32] := DEST[63:32] + SRC[63:32];
PADDQ (With 64-Bit Operands)
DEST[63:0] := DEST[63:0] + SRC[63:0];PADDB/PADDW/PADDD/PADDQ—Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-209PADDB (Legacy SSE Instruction)
DEST[7:0] := DEST[7:0] + SRC[7:0]; (* Repeat add operation for 2nd through 15th byte *)DEST[127:120] := DEST[127:120] + SRC[127:120];DEST[MAXVL-1:128] (Unmodified)
PADDW (Legacy SSE Instruction)
DEST[15:0] := DEST[15:0] + SRC[15:0];(* Repeat add operation for 2nd through 7th word *)DEST[127:112] := DEST[127:112] + SRC[127:112];DEST[MAXVL-1:128] (Unmodified)
PADDD (Legacy SSE Instruction)
DEST[31:0] := DEST[31:0] + SRC[31:0];(* Repeat add operation for 2nd and 3th doubleword *)DEST[127:96] := DEST[127:96] + SRC[127:96];DEST[MAXVL-1:128] (Unmodified)
PADDQ (Legacy SSE Instruction)
DEST[63:0] := DEST[63:0] + SRC[63:0];DEST[127:64] := DEST[127:64] + SRC[127:64];DEST[MAXVL-1:128] (Unmodified)
VPADDB (VEX.128 Encoded Instruction)
DEST[7:0] := SRC1[7:0] + SRC2[7:0]; (* Repeat add operation for 2nd through 15th byte *)DEST[127:120] := SRC1[127:120] + SRC2[127:120];DEST[MAXVL-1:128] := 0;
VPADDW (VEX.128 Encoded Instruction)
DEST[15:0] := SRC1[15:0] + SRC2[15:0];(* Repeat add operation for 2nd through 7th word *)DEST[127:112] := SRC1[127:112] + SRC2[127:112];DEST[MAXVL-1:128] := 0;
VPADDD (VEX.128 Encoded Instruction)
DEST[31:0] := SRC1[31:0] + SRC2[31:0];(* Repeat add operation for 2nd and 3th doubleword *)DEST[127:96] := SRC1[127:96] + SRC2[127:96];DEST[MAXVL-1:128] := 0;
VPADDQ (VEX.128 Encoded Instruction)
DEST[63:0] := SRC1[63:0] + SRC2[63:0];DEST[127:64] := SRC1[127:64] + SRC2[127:64];DEST[MAXVL-1:128] := 0;
VPADDB (VEX.256 Encoded Instruction)
DEST[7:0] := SRC1[7:0] + SRC2[7:0]; (* Repeat add operation for 2nd through 31th byte *)DEST[255:248] := SRC1[255:248] + SRC2[255:248];PADDB/PADDW/PADDD/PADDQ—Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-210 Vol. 2BVPADDW (VEX.256 Encoded Instruction)
DEST[15:0] := SRC1[15:0] + SRC2[15:0];(* Repeat add operation for 2nd through 15th word *)DEST[255:240] := SRC1[255:240] + SRC2[255:240];
VPADDD (VEX.256 Encoded Instruction)
DEST[31:0] := SRC1[31:0] + SRC2[31:0];(* Repeat add operation for 2nd and 7th doubleword *)DEST[255:224] := SRC1[255:224] + SRC2[255:224];
VPADDQ (VEX.256 Encoded Instruction)
DEST[63:0] := SRC1[63:0] + SRC2[63:0];DEST[127:64] := SRC1[127:64] + SRC2[127:64];DEST[191:128] := SRC1[191:128] + SRC2[191:128];DEST[255:192] := SRC1[255:192] + SRC2[255:192];
VPADDB (EVEX Encoded Versions)
THEN DEST[i+7:i] := SRC1[i+7:i] + SRC2[i+7:i]ELSE 
DEST[i+7:i] = 0
FI
FI;
VPADDW (EVEX Encoded Versions)
THEN DEST[i+15:i] := SR C1[i+15:i] + SRC2[i+15:i]
ELSE 
DEST[i+15:i] = 0
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PADDB/PADDW/PADDD/PADDQ—Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-211VPADDD (EVEX Encoded Versions) 
THEN 
THEN DEST[i+31:i] := SRC1[i+31:i] + SRC2[31:0]ELSE DEST[i+31:i] := SR C1[i+31:i] + SRC2[i+31:i]
FI;
ELSE 
FI
FI;
VPADDQ (EVEX Encoded Versions) 
THEN 
THEN DEST[i+63:i] := SRC1[i+63:i] + SRC2[63:0]ELSE DEST[i+63:i] := SR C1[i+63:i] + SRC2[i+63:i]
FI;
ELSE 
FI
FI;
VPADDB__m512i _mm512_add_epi8 ( __m512i a, __m512i b)VPADDW__m512i _mm512_add_epi16 ( __m512i a, __m512i b)VPADDB__m512i _mm512_mask_add_epi8 ( __m512 i s, __mmask64 m, __m512i a, __m512i b)
VPADDW__m512i _mm512_mask_add_epi16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)VPADDB__m512i _mm512_maskz_add_epi8 ( __mmask64 m, __m512i a, __m512i b)
VPADDW__m512i _mm512_maskz_add_epi16  (__mmask32 m, __m512i a, __m512i b)
VPADDB__m256i _mm256_mask_add_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b)VPADDW__m256i _mm256_mask_add_epi16 (__m256i s, __mmask16 m, __m256i a, __m256i b)VPADDB__m256i _mm256_maskz_add_epi8 ( __mmask32 m, __m256i a, __m256i b)
VPADDW__m256i _mm256_maskz_add_epi16  (__mmask16 m, __m256i a, __m256i b)
VPADDB__m128i _mm_mask_add_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b)VPADDW__m128i _mm_mask_add_epi16 (__m128i  s, __mmask8 m, __m128i a, __m128i b)PADDB/PADDW/PADDD/PADDQ—Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-212 Vol. 2BVPADDB__m128i _mm_maskz_add_epi8 ( __mmask16 m, __m128i a, __m128i b)
VPADDW__m128i _mm_maskz_add_epi16 (__mmask8 m, __m128i a, __m128i b)VPADDD __m512i _mm512_add_epi 32( __m512i a, __m512i b);
VPADDD __m512i _mm512_mask_ad d_epi32(__m512i s, __mmask16 k, __m512i  a, __m512i b);
VPADDD __m512i _mm512_maskz _add_epi32( __mmask16 k, __m512i a, __m512i b);
VPADDD __m256i _mm256_mask_ad d_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPADDD __m256i _mm256_maskz _add_epi32( __mmask8 k, __m256i a, __m256i b);
VPADDD __m128i _mm_mask_add_epi32(__m128i s, __mmask8 k, __m1 28i a, __m128i b);
VPADDD __m128i _mm_maskz_ad d_epi32( __mmask8 k, __m128i a, __m128i b);
VPADDQ __m512i _mm512_add_epi64( __m512i a, __m512i b);VPADDQ __m512i _mm512_mask_add_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPADDQ __m512i _mm512_maskz_add_epi64( __mmask8 k, __m512i a, __m512i b);VPADDQ __m256i _mm256_mask_add_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);VPADDQ __m256i _mm256_maskz_add_epi64( __mmask8 k, __m256i a, __m256i b);VPADDQ __m128i _mm_mask_add_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);VPADDQ __m128i _mm_maskz_add_epi64( __mmask8 k, __m128i a, __m128i b);PADDB __m128i _mm_add_epi8 (__m128i a,__m128i b );PADDW __m128i _mm_add_epi16 ( __m128i a, __m128i b);PADDD  __m128i _mm_add_epi32 ( __m128i a, __m128i b);PADDQ __m128i _mm_add_epi64 ( __m128i a, __m128i b);VPADDB __m256i _mm256_add_epi8 (__m256ia,__m256i b );VPADDW __m256i _mm256_add_epi16 ( __m256i a, __m256i b);VPADDD __m256i _mm256_add_epi 32 ( __m256i a, __m256i b);
VPADDQ __m256i _mm256_add_epi64 ( __m256i a, __m256i b);PADDB __m64 _mm_add_pi8(__m64 m1, __m64 m2)PADDW __m64 _mm_add_pi16(__m64 m1, __m64 m2)PADDD __m64 _mm_add_pi32(__m64 m1, __m64 m2)PADDQ __m64 _mm_add_si64(__m64 m1, __m64 m2)
None.
EVEX-encoded VPADDD/Q, see Table 2-49, “Type E4 Class Exception Conditions.”EVEX-encoded VPADDB/W, see Exceptio ns Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PADDSB/PADDSW—Add Packed Signed Integers with Signed SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-213PADDSB/PADDSW—Add Packed Signed In tegers with Signed Saturation
Opcode/
Mode 
Feature 
NP 0F EC /r1
PADDSB mm, mm/m64
NOTES:

None.
Opcode/
Mode 
Feature 
NP 0F EC /r1
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V MMX Add packed signed byte integers from 
mm/m64 and mm and sa turate the results.
66 0F EC /r
PADDSB xmm1, xmm2/m128A V/V SSE2 Add packed signed byte integers from 
xmm2/m128 and xmm1 sa turate the results.
NP 0F ED /r1
PADDSW mm, mm/m64A V/V MMX Add packed signed word integers from 
66 0F ED /r
PADDSW xmm1, xmm2/m128A V/V SSE2 Add packed signed word integers from 
xmm2/m128 and xmm1 and saturate the 
results.
VEX.128.66.0F.WIG EC /r
VPADDSB xmm1, xmm2, xmm3/m128B V/V AVX Add packed signed byte integers from 
xmm3/m128 and xmm2 sa turate the results.
VEX.128.66.0F.WIG ED /r
VPADDSW xmm1, xmm2, xmm3/m128B V/V AVX Add packed signed word integers from 
xmm3/m128 and xmm2 and saturate the 
results.
VEX.256.66.0F .WIG EC /r
VPADDSB ymm1, ymm2, ymm3/m256B V/V AVX2 Add packed signed byte integers from ymm2, 
and ymm3/m256 and st ore the saturated 
results in ymm1.
VEX.256.66.0F .WIG ED /r
VPADDSW ymm1, ymm2, ymm3/m256B V/V AVX2 Add packed signed word integers from ymm2, 
EVEX.128.66.0F.WIG EC /r
VPADDSB xmm1 {k1}{z }, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWAdd packed signed byte integers from xmm2, 
and xmm3/m128 and st ore the saturated 
results in xmm1 under writemask k1.
EVEX.256.66.0F.WIG EC /r
VPADDSB ymm1 {k1}{z}, ymm2, ymm3/m256C V/V AVX512VL
AVX512BWAdd packed signed byte integers from ymm2, 
results in ymm1 under writemask k1.
EVEX.512.66.0F.WIG EC /r
VPADDSB zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Add packed signed byte integers from zmm2, 
and zmm3/m512 and st ore the saturated 
results in zmm1 under writemask k1.
EVEX.128.66.0F.WIG ED /r
VPADDSW xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWAdd packed signed word integers from xmm2, 
EVEX.256.66.0F.WIG ED /r
VPADDSW ymm1 {k1}{z }, ymm2, ymm3/m256C V/V AVX512VL
AVX512BWAdd packed signed word integers from ymm2, 
EVEX.512.66.0F.WIG ED /r
VPADDSW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Add packed signed word integers from zmm2, 
results in zmm1 under writemask k1.PADDSB/PADDSW—Add Packed Signed Integers with Signed SaturationINSTRUCTION SET REFERENCE, M-U
4-214 Vol. 2BInstruction Operand Encoding
Performs a SIMD add of the packed signed integers from  the source operand (second operand) and the destination 
Overflow is handled with signed saturation , as described in the following paragraphs.
(V)PADDSB performs a SIMD add of the packed signed inte gers with saturation from the first source operand and 
second source operand and stores the packed integer result s in the destination operand. When an individual byte 
result is beyond the range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value 
of 7FH or 80H, respectively, is written to the destination operand.
(V)PADDSW performs a SIMD add of the packed signed word integers with saturation from the first source operand 
and second source operand and stores the packed integer results in the destination operand. When an individual 
word result is beyond the range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the satu-
rated value of 7FFFH or 8000H, respectively , is written to the destination operand.
EVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The seco nd source operand is an 
ZMM/YMM/XMM register or a memory location. The destination operand is an ZMM/YMM/XMM register.
or a 256-bit memory location. The destination operand is a YMM register. 
register or 128-bit memory location. The destinat ion operand is an XMM register. The upper bits ( MAXVL-1 :128) of 
the corresponding register destination are zeroed.
Operation
PADDSB (With 64-bit Operands)
DEST[7:0] := SaturateToSignedByte(DEST[7:0] + SRC (7:0]);
(* Repeat add operation for 2nd through 7th bytes *)DEST[63:56] := SaturateToSignedByte(DEST[63:56] + SRC[63:56] );
PADDSB (With 128-bit Operands)
DEST[7:0] := SaturateToSignedByte (DEST[7:0] + SRC[7:0]);
(* Repeat add operation for 2nd through 14th bytes *)DEST[127:120] := SaturateToSignedByte (DEST[111:120] + SRC[127:120]);
VPADDSB (VEX.128 Encoded Version)
DEST[7:0] := SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);(* Repeat subtract operation for 2nd through 14th bytes *)DEST[127:120] := SaturateToSignedByte (SRC1[111:120] + SRC2[127:120]);DEST[MAXVL-1:128] := 0
VPADDSB (VEX.256 Encoded Version)
DEST[7:0] := SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);(* Repeat add operation for 2nd through 31st bytes *)DEST[255:248] := SaturateToSignedByte (SRC1[255:248] + SRC2[255:248]);Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/APADDSB/PADDSW—Add Packed Signed Integers with Signed SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-215VPADDSB (EVEX Encoded Versions)
THEN DEST[i+7:i] := SaturateToSign edByte (SRC1[i+7:i] + SRC2[i+7:i])
ELSE 
FI
FI;
PADDSW (with 64-bit operands)
DEST[15:0] := Saturate ToSignedWord(DEST[15:0] + SRC[15:0] );
(* Repeat add operation for 2nd and 7th words *)DEST[63:48] := SaturateToSignedWord(DEST[63:48] + SRC[63:48] );
PADDSW (with 128-bit operands)
DEST[15:0] := SaturateTo SignedWord (DEST[15:0] + SRC[15:0]);
(* Repeat add operation for 2nd through 7th words *)DEST[127:112] := SaturateToSignedWord (DEST[127:112] + SRC[127:112]);
VPADDSW (VEX.128 Encoded Version)
DEST[15:0] := SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);(* Repeat subtract operation for 2nd through 7th words *)DEST[127:112] := SaturateToSignedWord (SRC1[127:112] + SRC2[127:112]);DEST[MAXVL-1:128] := 0
VPADDSW (VEX.256 Encoded Version)
DEST[15:0] := SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);(* Repeat add operation for 2nd through 15th words *)DEST[255:240] := SaturateToSignedWord (SRC1[255:240] + SRC2[255:240])
VPADDSW (EVEX Encoded Versions)
THEN DEST[i+15:i] := SaturateToSignedWord (SRC1[i+15:i] + SRC2[i+15:i])ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PADDSB/PADDSW—Add Packed Signed Integers with Signed SaturationINSTRUCTION SET REFERENCE, M-U
4-216 Vol. 2BIntel C/C ++ Compiler Intrinsic Equivalents
PADDSB __m64 _mm_adds_pi8(__m64 m1, __m64 m2)
(V)PADDSB  __m128i _mm_adds_epi8 ( __m128i a, __m128i b)VPADDSB __m256i _mm256_adds_epi8 ( __m256i a, __m256i b)PADDSW __m64 _mm_adds_pi16(__m64 m1, __m64 m2)(V)PADDSW __m128i _mm_adds_epi16 ( __m128i a, __m128i b)VPADDSW __m256i _mm256_adds_epi16 ( __m256i a, __m256i b)VPADDSB __m512i _mm512_adds_epi8 ( __m512i a, __m512i b)VPADDSW __m512i _mm512_adds_epi16 ( __m512i a, __m512i b)VPADDSB __m512i _mm512_mask_adds_epi8 ( __m512i  s, __mmask64 m, __m512i a, __m512i b)
VPADDSW __m512i _mm512_mask_adds_epi16 ( __m 512i s, __mmask32 m, __m512i a, __m512i b)
VPADDSB __m512i _mm512_maskz_adds_epi8 (_ _mmask64 m, __m512i a, __m512i b)
VPADDSW __m512i _mm512_maskz_adds_epi16 (__mmask32 m, __m512i a, __m512i b)VPADDSB __m256i _mm256_mask_adds_epi8 (__m256i  s, __mmask32 m, __m256i a, __m256i b)
VPADDSW __m256i _mm256_mask_adds_epi16 (__m 256i s, __mmask16 m, __m256i a, __m256i b)
VPADDSB __m256i _mm256_maskz_adds_epi8 (_ _mmask32 m, __m256i a, __m256i b)

VPADDSW __m256i _mm256_maskz_adds_epi16 (__mmask16 m, __m256i a, __m256i b)VPADDSB __m128i _mm_mask_adds_epi8 (__m128i  s, __mmask16 m, __m128i a, __m128i b)
VPADDSW __m128i _mm_mask_adds_epi16 (__m 128i s, __mmask8 m, __m128i a, __m128i b)
VPADDSB __m128i _mm_maskz_adds_epi8 (__mmask16 m, __m128i a, __m128i b)VPADDSW __m128i _mm_maskz_adds_epi16  (__mmask8 m, __m128i a, __m128i b)
None.
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-217PADDUSB/PADDUSW—Add Packe d Unsigned Integers With Unsigned Saturation
Opcode/
Mode 
NP 0F DC /r1
PADDUSB mm, mm/m64
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SS E Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel
® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.A V/V MMX Add packed unsigned byte integers from 
mm/m64 and mm and saturate the results.
66 0F DC /r
PADDUSB xmm1, xmm2/m128A V/V SSE2 Add packed unsigned byte integers from 
NP 0F DD /r1
PADDUSW mm, mm/m64A V/V MMX Add packed unsigned word integers from 
66 0F DD /r
PADDUSW xmm1, xmm2/m128A V/V SSE2 Add packed unsigned word integers from 
xmm2/m128 to xmm1 and saturate th e results.
VEX.128.660F.WIG DC /r
VPADDUSB xmm1, xmm2, xmm3/m128B V/V AVX Add packed unsigned byte integers from 
xmm3/m128 to xmm2 and saturate th e results.
VEX.128.66.0F.WIG DD /r
VPADDUSW xmm1, xmm2, xmm3/m128B V/V AVX Add packed unsigned word integers from 
VEX.256.66.0F .WIG DC /r
VPADDUSB ymm1, ymm2, ymm3/m256B V/V AVX2 Add packed unsigned byte integers from ymm2, 
VEX.256.66.0F .WIG DD /r
VPADDUSW ymm1, ymm2, ymm3/m256B V/V AVX2 Add packed unsigned word integers from ymm2, 
EVEX.128.66.0F.WIG DC /r
VPADDUSB xmm1 {k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWAdd packed unsigned byte integers from xmm2, 
EVEX.256.66.0F.WIG DC /r
VPADDUSB ymm1 {k1}{z }, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWAdd packed unsigned byte integers from ymm2, 
EVEX.512.66.0F.WIG DC /r
VPADDUSB zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Add packed unsigned byte integers from zmm2, 
and zmm3/m512 and store the saturated 
EVEX.128.66.0F.WIG DD /r
VPADDUSW xmm1 {k1}{z }, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWAdd packed unsigned word integers from xmm2, 
EVEX.256.66.0F.WIG DD /r
VPADDUSW ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWAdd packed unsigned word integers from ymm2, 
EVEX.512.66.0F.WIG DD /r
VPADDUSW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Add packed unsigned word integers from zmm2, 
results in zmm1 under writemask k1.PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-218 Vol. 2BInstruction Operand Encoding
Performs a SIMD add of the packed unsigned integers fr om the source operand (second operand) and the destina-
tion operand (first operand), and stores  the packed integer results in the dest ination operand. See Figure 9-4 in the 
Overflow is handled with unsigned saturation, as described in the following paragraphs.
(V)PADDUSB performs a SIMD add of the packed unsigned in tegers with saturation from the first source operand 
byte result is beyond the range of an unsigned byte inte ger (that is, greater than FFH), the saturated value of FFH 
is written to the destination operand.
(V)PADDUSW performs a SIMD add of the packed unsigned word integers with saturation from the first source 
operand and second source operand and stores the packed  integer results in the destination operand. When an 
individual word result is beyond the range of an unsigne d word integer (that is, greater than FFFFH), the saturated 
value of FFFFH is written to the destination operand.
ZMM/YMM/XMM register or a 512/256/128-bit memory lo cation. The destination is an ZMM/YMM/XMM register.
the corresponding destination register destination are zeroed.
Operation
PADDUSB (With 64-bit Operands)
DEST[7:0] := SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] );
(* Repeat add operation for 2nd through 7th bytes *)DEST[63:56] := SaturateTo UnsignedByte(DEST[63:56] + SRC[63:56] 
PADDUSB (With 128-bit Operands)
DEST[7:0] := SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]);
(* Repeat add operation for 2nd through 14th bytes *)DEST[127:120] := SaturateToUnSignedByte (DEST[127:120] +
 SRC[127:120]);
VPADDUSB (VEX.128 Encoded Version)
DEST[7:0] := SaturateToUnsigned Byte (SRC1[7:0] + SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)DEST[127:120] := SaturateToUnsignedByte (SRC1[111:120] + SRC2[127:120]);DEST[MAXVL-1:128] := 0Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/APADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-219VPADDUSB (VEX.256 Encoded Version)
DEST[7:0] := Saturate ToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
(* Repeat add operation for 2nd through 31st bytes *)DEST[255:248] := SaturateToUnsignedByte (SRC1[255:248] + SRC2[255:248]);
PADDUSW (With 64-bit Operands)
DEST[15:0] := SaturateToUnsignedWord(DEST[15:0] + SRC[15:0] );
(* Repeat add operation for 2nd and 3rd words *)DEST[63:48] := SaturateToUnsignedWord(DEST[63:48] + SRC[63:48] );
PADDUSW (With 128-bit Operands)
DEST[15:0] := SaturateToUnsignedWord (DEST[15:0] + SRC[15:0]);
(* Repeat add operation for 2nd through 7th words *)DEST[127:112] := SaturateToUnSignedWord (DEST[127:112] + SRC[127:112]);
VPADDUSW (VEX.128 Encoded Version)
DEST[15:0] := SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);(* Repeat subtract operation for 2nd through 7th words *)DEST[127:112] := SaturateToUnsignedWord (SRC1[127:112] + SRC2[127:112]);DEST[MAXVL-1:128] := 0
VPADDUSW (VEX.256 Encoded Version)
DEST[15:0] := SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);(* Repeat add operation for 2nd through 15th words *)DEST[255:240] := SaturateToUnsignedWord (SRC1[255:240] + SRC2[255:240])
VPADDUSB (EVEX Encoded Versions)
THEN DEST[i+7:i] := SaturateToUnsign edByte (SRC1[i+7:i] + SRC2[i+7:i])
ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-220 Vol. 2BVPADDUSW (EVEX Encoded Versions)
THEN DEST[i+15:i] := SaturateToUnsign edWord (SRC1[i+15:i] + SRC2[i+15:i])
ELSE 
FI
FI;

ELSE 
FI
FI;
ELSE 
FI
FI;
PADDUSB __m64 _mm_adds_pu8(__m64 m1, __m64 m2)
PADDUSW __m64 _mm_adds_pu16(__m64 m1, __m64 m2)(V)PADDUSB __m128i _mm_adds_epu8 ( __m128i a, __m128i b)(V)PADDUSW __m128i _mm_adds_epu16 ( __m128i a, __m128i b)VPADDUSB __m256i _mm256_adds_epu8 ( __m256i a, __m256i b)VPADDUSW __m256i _mm256_adds_epu16 ( __m256i a, __m256i b)VPADDUSB __m512i _mm512_adds_epu8 ( __m512i a, __m512i b)VPADDUSW __m512i _mm512_adds_epu16 ( __m512i a, __m512i b)VPADDUSB __m512i _mm512_mask_adds_epu8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)VPADDUSW __m512i _mm512_mask_adds_epu16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)VPADDUSB __m512i _mm512_maskz_adds_epu8 (__mmask64 m, __m512i a, __m512i b)VPADDUSW __m512i _mm512_maskz_adds_epu16 (__mmask32 m, __m512i a, __m512i b)VPADDUSB __m256i _mm256_mask_adds_epu8 (__m256i s, __mmask32 m, __m256i a, __m256i b)VPADDUSW __m256i _mm256_mask_adds_epu16 (__m256i s, __mmask16 m, __m256i a, __m256i b)VPADDUSB __m256i _mm256_maskz_adds_epu8 (__mmask32 m, __m256i a, __m256i b)VPADDUSW __m256i _mm256_maskz_adds_epu16 (__mmask16 m, __m256i a, __m256i b)VPADDUSB __m128i _mm_mask_adds_epu8 (__m128i s, __mmask16 m, __m128i a, __m128i b)VPADDUSW __m128i _mm_mask_adds_epu16 (__m128i s, __mmask8 m, __m128i a, __m128i b)VPADDUSB __m128i _mm_maskz_adds_epu8 (__mmask16 m, __m128i a, __m128i b)
VPADDUSW __m128i _mm_maskz_adds_epu16 (__mmask8 m, __m128i a, __m128i b)
None.
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PALIGNR—Packed Align RightINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-221PALIGNR—Packed Align Right 
(V)PALIGNR concatenates the destination operand (the first operand) and the source operand (the second 
operand) into an intermediate composite, shifts the compos ite at byte granularity to the right by a constant imme-
diate, and extracts the right-aligned result into the dest ination. The first and the seco nd operands can be an MMX, 
XMM or a YMM register. The immediate value is considered  unsigned. Immediate shift counts larger than the 2L 
(i.e., 32 for 128-bit operands, or 16 for 64-bit operands) produce a zero result. Both operands can be MMX regis-
ters, XMM registers or YMM registers. When the source operand is a 128-bit memory operand, the operand must 
be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. Opcode/
Mode 
Feature 
NP 0F 3A 0F /r ib1
PALIGNR mm1, mm2/m64, imm8
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSSE3 Concatenate destination and source operands, extract 
byte-aligned result  shifted to the right by constant 
value in imm8 into mm1. 
66 0F 3A 0F /r ib
PALIGNR xmm1, xmm2/m128, imm8A V/V SSSE3 Concatenate destination and source operands, extract 
value in imm8 into xmm1.
VEX.128.66.0F3A.WIG 0F /r ib
VPALIGNR xmm1, xmm2, xmm3/m128, 
imm8B V/V AVX Concatenate xmm2 an d xmm3/m128, extract byte 
aligned result shifted to the right by constant value in 
imm8 and result is stored in xmm1.
VEX.256.66.0F3A.WIG 0F /r ib
VPALIGNR ymm1, ymm2, ymm3/m256, 
imm8BV / V A V X 2 C o n c a t e n a t e  p a i r s  of 16 bytes in ymm2 and 
ymm3/m256 into 32-byte inte rmediate result, extract 
byte-aligned, 16-byte result  shifted to the right by 
constant values in imm8 from each intermediate result, 
and two 16-byte results are stored in ymm1.
EVEX.128.66.0F3A.WIG 0F /r ib
VPALIGNR xmm1 {k1}{z}, xmm2, xmm3/m128, imm8C V/V AVX512VL
AVX512BWConcatenate xmm2 and xmm3/m128 into a 32-byte 
intermediate result, extract byte aligned result shifted 
to the right by constant va lue in imm8 and result is 
stored in xmm1.
EVEX.256.66.0F3A.WIG 0F /r ib
VPALIGNR ymm1 {k1}{z}, ymm2, ymm3/m256, imm8C V/V AVX512VL
AVX512BWConcatenate pairs of 16 bytes in ymm2 and 
EVEX.512.66.0F3A.WIG 0F /r ib
VPALIGNR zmm1 {k1}{z}, zmm2, 
zmm3/m512, imm8C V/V AVX512BW Concatenate pairs of 16 bytes in zmm2 and 
zmm3/m512 into 32 -byte intermediate  result, extract 
constant values in imm8 from each intermediate result, and four 16-byte results are stored in zmm1.
C Full Mem ModRM:reg (w) EVEX. vvvv (r) ModRM:r/m (r) imm8PALIGNR—Packed Align RightINSTRUCTION SET REFERENCE, M-U
4-222 Vol. 2BIn 64-bit mode and not encoded by VEX/EVEX prefix , use the REX prefix to access additional registers.
EVEX.512 encoded version: The first source operand is a ZMM register and contains four 16-byte blocks. The 
second source operand is a ZMM register or a 512-bit memo ry location containing four 16-byte block. The destina-
tion operand is a ZMM register and contain four 16-byte results. The imm8[7:0] is the common shift count
used for each of the four successive 16-byte block sour ces. The low 16-byte block of the two source operands 
produce the low 16-byte result of the destination operand, the high 16-byte block of the two source operands 
produce the high 16-byte result of the destinatio n operand and so on for the blocks in the middle.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register and contains two 16-byte 
blocks. The second source operand is a YMM register or a 256-bit memory location containing two 16-byte block. 
The destination operand is a YMM register and contain tw o 16-byte results. The imm8[7:0] is the common shift 
count used for the two lower 16-byte block sources and the two upper 16-byte block sources. The low 16-byte 
block of the two source operands produce the low 16-byte re sult of the destination operand, the high 16-byte block 
of the two source operands produce th e high 16-byte result of the destination operand. The upper bits (MAXVL-
1:256) of the corresponding ZMM register destination are zeroed.
1:128) of the corresponding ZMM register destination are zeroed.
Concatenation is done with 128-bit data in the first and second source operand for both 128-bit and 256-bit 
instructions. The high 128-bits of the intermediate composite 256-bit result came from the 128-bit data from the 
first source operand; the low 128-bits of the intermediate result came from the 128-bit data of the second source 
operand.
Figure 4-7.  256-bit VPALIGN Instruction Operation
Operation
PALIGNR (With 64-bit Operands)
temp1[127:0] = CONCATENATE(DEST,SRC)>>(imm8*8) 
DEST[63:0] = temp1[63:0] 
PALIGNR (With 128-bit Operands)
temp1[255:0] := ((DEST[127:0] << 128) OR SRC[127:0])>>(imm8*8);DEST[127:0] := temp1[127:0]DEST[MAXVL-1:128] (Unmodified)127 0
SRC1
Imm8[7:0]*8
Imm8[7:0]*8127 0
SRC2
255 128
SRC1255 128
SRC2
255 128
DEST127 0
DESTPALIGNR—Packed Align RightINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-223VPALIGNR (VEX.128 Encoded Version)
temp1[255:0] := ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8*8);
DEST[127:0] := temp1[127:0]DEST[MAXVL-1:128] := 0
VPALIGNR (VEX.256 Encoded Version)
temp1[255:0] := ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8[7:0]*8);DEST[127:0] := temp1[127:0]temp1[255:0] := ((SRC1[255:128] << 128 ) OR SRC2[255:128 ])>>(imm8[7:0]*8);
DEST[MAXVL-1:128] := temp1[127:0]
VPALIGNR (EVEX Encoded Versions)
FOR l := 0 TO VL-1 wi th increments of 128
temp1[255:0] := ((SRC1[l+127:l] << 128) OR SRC2[l+127:l])>>(imm8[7:0]*8);
TMP_DEST[l+127:l] := temp1[127:0]
ENDFOR;
THEN DEST[i+7:i] := TMP_DEST[i+7:i]ELSE 
FI
FI;
PALIGNR __m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)
(V)PALIGNR __m128i _mm_alignr_epi 8 (__m128i a, __m128i b, int n)

ENDFOR;
FI
FI;
VPALIGNR __m256i _mm256_alignr_epi8 (__m256i a, __m256i b, const int n)VPALIGNR __m512i _mm512_alignr_epi8 (__m512i a, __m512i b, const int n)VPALIGNR __m512i _mm512_mask_alignr_epi8 (__m512i s, __mmask64 m, __m512i a, __m512i b, const int n)
VPALIGNR __m512i _mm512_maskz_alignr_epi8 ( __mmask64 m, __m512i a, __m512i b, const int n)
VPALIGNR __m256i _mm256_mask_alignr_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b, const int n)
VPALIGNR __m256i _mm256_maskz_alignr_epi8 ( __mmask32 m, __m256i a, __m256i b, const int n)
VPALIGNR __m128i _mm_mask_alignr_epi8 (__m128i s,  __mmask16 m, __m128i a, __m128i b, const int n)
VPALIGNR __m128i _mm_maskz_alig nr_epi8 (__mmask16 m, __m128 i a, __m128i b, const int n)
SIMD Floating-Point Exceptions 
None. 
EVEX-encoded instruction, see Exceptions Type E4NF.n b in Table 2-50, “Type E4NF Class Exception Conditions.”PAND—Logical ANDINSTRUCTION SET REFERENCE, M-U
4-224 Vol. 2BPAND—Logical AND
Performs a bitwise logical AND operation on the first so urce operand and second source operand and stores the 
result in the destination operand. Each bit of the result is  set to 1 if the corresponding bits of the first and second 
operands are 1, otherwise it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX pr efix in the form of REX.R permits this instruction to 
access additional registers (XMM8-XMM15).Opcode/
Mode 
NP 0F DB /r1
PAND mm, mm/m64
NOTES:
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V MMX Bitwise AND mm/m64 and mm.
66 0F DB /r
PAND xmm1, xmm2/m128AV / V S S E 2 B i t w i s e  A N D  o f  xmm2/m128 and xmm1.
VEX.128.66.0F.WIG DB /r
VPAND xmm1, xmm2, xmm3/m128B V/V AVX Bitwise AND of xmm3/m128 and xmm.
VEX.256.66.0F .WIG DB /r
VPAND ymm1, ymm2, ymm3/.m256B V/V AVX2 Bitwise AND of ymm2, and ymm3/m256 and store 
EVEX.128.66.0F.W0 DB /r
VPANDD xmm1 {k1}{z}, xmm2, 
AVX512FBitwise AND of packed doubleword integers in 
xmm2 and xmm3/m128/m32bcst and store result 
EVEX.256.66.0F.W0 DB /r
VPANDD ymm1 {k1}{z}, ymm2, 
ymm2 and ymm3/m256/m32bcst and store result 
EVEX.512.66.0F.W0 DB /r
VPANDD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512F Bitwise AND of packed doubleword integers in 
zmm2 and zmm3/m512/m32bcst and store result 
EVEX.128.66.0F.W1 DB /r
VPANDQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV / V A V X 5 1 2 V L
AVX512FBitwise AND of packed quadword integers in xmm2 
and xmm3/m128/m64bcst and store result in 
xmm1 using writemask k1. 
EVEX.256.66.0F.W1 DB /r
VPANDQ ymm1 {k1}{z}, ymm2, 
AVX512FBitwise AND of packed quadword integers in ymm2 
and ymm3/m256/m64bcst and store result in 
ymm1 using writemask k1. 
EVEX.512.66.0F.W1 DB /r
VPANDQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Bitwise AND of packed quadword integers in zmm2 
and zmm3/m512/m64bcst and store result in 
zmm1 using writemask k1. 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APAND—Logical ANDINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-225Legacy SSE instructions: The source operand can be an MM X technology register or a 64-bit memory location. The 
destination operand can be an MMX technology register.
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register condit ionally updated with write-
mask k1 at 32/64-bit granularity.
VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM 
VEX.128 encoded versions: The first source operand is an  XMM register. The second source operand is an XMM 
Operation
PAND (64-bit Operand)
DEST := DEST AND SRC
PAND (128-bit Legacy SSE Version)
DEST := DEST AND SRCDEST[MAXVL-1:128 ] (Unmodified)
VPAND (VEX.128 Encoded Version)
DEST := SRC1 AND SRC2DEST[MAXVL-1:128] := 0
VPAND (VEX.256 Encoded Instruction)
DEST[255:0] := (SRC1[255:0] AND SRC2[255:0])DEST[MAXVL-1:256] := 0
VPANDD (EVEX Encoded Versions) 
THEN 
THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE AND SRC2[31:0]ELSE DEST[i+31:i] := SRC1[i+3 1:i] BITWISE AND SRC2[i+31:i]
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0PAND—Logical ANDINSTRUCTION SET REFERENCE, M-U
4-226 Vol. 2BVPANDQ (EVEX Encoded Versions) 
THEN 
THEN DEST[i+63:i] := SRC1[i+63:i] BITWISE AND SRC2[63:0]ELSE DEST[i+63:i] := SRC1[i+6 3:i] BITWISE AND SRC2[i+63:i]
FI;
ELSE 
FI
FI;
VPANDD __m512i _mm512_and_epi32( __m512i a, __m512i b);VPANDD __m512i _mm512_mask_and_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);VPANDD __m512i _mm512_maskz_and_epi32( __mmask16 k, __m512i a, __m512i b);VPANDQ __m512i _mm512_and_epi 64( __m512i a, __m512i b);
VPANDQ __m512i _mm512_mask_and_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPANDQ __m512i _mm512_maskz_and_epi64 ( __mmask8 k, __m512i a, __m512i b);
VPANDND __m256i _mm256_mask_and_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);VPANDND __m256i _mm256_maskz_and_epi32( __mmask8 k, __m256i a, __m256i b);VPANDND __m128i _mm_mask_and_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);VPANDND __m128i _mm_maskz_and_epi32( __mmask8 k, __m128i a, __m128i b);VPANDNQ __m256i _mm256_mask_and_epi64(__m256i  s, __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m256i _mm256_maskz_and_epi64( __mmask8 k, __m256i a, __m256i b);VPANDNQ __m128i _mm_mask_and_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);VPANDNQ __m128i _mm_maskz_and_epi64( __mmask8 k, __m128i a, __m128i b);PAND __m64 _mm_and_si64 (__m64 m1, __m64 m2)(V)PAND __m128i _mm_and_si128 ( __m128i a, __m128i b)VPAND __m256i _mm256_and_si2 56 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PANDN—Logical AND NOTINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-227PANDN—Logical AND NOT
Performs a bitwise logical NOT operation on the first so urce operand, then performs bitwise AND with second 
source operand and stores the result in the destination op erand. Each bit of the result is set to 1 if the corre-
sponding bit in the first operand is 0 and the corresponding bit in the second operand is 1, otherwise it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to 
Mode 
Feature 
NP 0F DF /r1
PANDN mm, mm/m64
NOTES:

Mode 
Feature 
NP 0F DF /r1
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.AV / V M M X B i t w i s e  A N D  N O T of mm/m64 and mm.
66 0F DF /r
PANDN xmm1, xmm2/m128A V/V SSE2 Bitwise AND NOT of xmm2/m128 and xmm1.
VEX.128.66.0F.WIG DF /r
VPANDN xmm1, xmm2, xmm3/m128B V/V AVX Bitwise AND NOT of xmm3/m128 and xmm2.
VEX.256.66.0F .WIG DF /r
VPANDN ymm1, ymm2, ymm3/m256BV / V A V X 2 B i t w i s e  A N D  N O T  of ymm2, and ymm3/m256 
EVEX.128.66.0F.W0 DF /r
VPANDND xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcst C V/V AVX512VL
AVX512FBitwise AND NOT of packed doubleword 
integers in xmm2 and xmm3/m128/m32bcst 
and store result in xmm1 using writemask k1. 
EVEX.256.66.0F.W0 DF /r
VPANDND ymm1 {k1}{z}, ymm2, 
integers in ymm2 and ymm3/m256/m32bcst 
and store result in ymm1 using writemask k1. 
EVEX.512.66.0F.W0 DF /r
VPANDND zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst C V/V AVX512F Bitwise AND NOT of packed doubleword 
integers in zmm2 and zmm3/m512/m32bcst 
and store result in zmm1 using writemask k1. 
EVEX.128.66.0F.W1 DF /r
VPANDNQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst C V/V AVX512VL
AVX512FBitwise AND NOT of packed quadword 
integers in xmm2 and xmm3/m128/m64bcst and store result in xmm1 using writemask k1. 
EVEX.256.66.0F.W1 DF /r
VPANDNQ ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcst C V/V AVX512VL
integers in ymm2 and ymm3/m256/m64bcst 
EVEX.512.66.0F.W1 DF /r
VPANDNQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst C V/V AVX512F Bitwise AND NOT of packed quadword 
integers in zmm2 and zmm3/m512/m64bcst 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APANDN—Logical AND NOTINSTRUCTION SET REFERENCE, M-U
4-228 Vol. 2BLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The 
Operation
PANDN (64-bit Operand)
DEST := NOT(DEST) AND SRC
PANDN (128-bit Legacy SSE Version)
DEST := NOT(DEST) AND SRCDEST[MAXVL-1:128] (Unmodified)
VPANDN (VEX.128 Encoded Version)
DEST := NOT(SRC1) AND SRC2DEST[MAXVL-1:128] := 0
VPANDN (VEX.256 Encoded Instruction)
DEST[255:0] := ((NOT SRC1 [255:0]) AND SRC2[255:0])
VPANDND (EVEX Encoded Versions) 
THEN 
THEN DEST[i+31:i] := ((NOT SRC1[i+31:i]) AND SRC2[31:0])
ELSE DEST[i+31:i] := ((NOT SRC1[i+31:i]) AND SRC2[i+31:i])
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0PANDN—Logical AND NOTINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-229VPANDNQ (EVEX Encoded Versions) 
THEN 
THEN DEST[i+63:i] := ((NOT SRC1[i+63:i]) AND SRC2[63:0])
ELSE DEST[i+63:i] := ((NOT SRC1[i+63:i]) AND SRC2[i+63:i])
FI;
ELSE 
FI
FI;
VPANDND __m512i _mm512_andnot_ep i32( __m512i a, __m512i b);
VPANDND __m512i _mm512_mask_andnot_epi32(__m51 2i s, __mmask16 k, __m512i a, __m512i b);
VPANDND __m512i _mm512_maskz_andnot_epi32( __mmask16 k, __m512i a, __m512i b);VPANDND __m256i _mm256_mask_andnot_epi32(__m 256i s, __mmask8 k, __m256i a, __m256i b);
VPANDND __m256i _mm256_maskz_andnot_epi32( __mmask8 k, __m256i a, __m256i b);VPANDND __m128i _mm_mask_andnot_epi32(__m128 i s, __mmask8 k, __m128i a, __m128i b);
VPANDND __m128i _mm_maskz_andnot_epi32 ( __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m512i _mm512_andnot_epi64( __m512i a, __m512i b);VPANDNQ __m512i _mm512_mask_andnot_epi64(__m51 2i s, __mmask8 k, __m512i a, __m512i b);
VPANDNQ __m512i _mm512_maskz _andnot_epi64( __mmask8 k, __m512i a, __m512i b);
VPANDNQ __m256i _mm256_mask_andnot_epi64(__m25 6i s, __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m256i _mm256_maskz _andnot_epi64( __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m128i _mm_mask_andno t_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m128i _mm_maskz_ andnot_epi64( __mmask8 k, __m128i a, __m128i b);
PANDN __m64 _mm_andnot_si64 (__m64 m1, __m64 m2)(V)PANDN __m128i _mm_andnot_si128 ( __m128i a, __m128i b)VPANDN __m256i _mm256_andnot_ si256 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PAUSE—Spin Loop HintINSTRUCTION SET REFERENCE, M-U
4-230 Vol. 2BPAUSE—Spin Loop Hint
Improves the performance of spin-wait l oops. When executing a “spin-wait loop,” processors will suffer a severe 
performance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE 
instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint 
to avoid the memory order violation in most situations, which greatly improves processor performance. For this 
reason, it is recommended that a PAUSE inst ruction be placed in all spin-wait loops.
An additional function of the PAUSE instruction is to re duce the power consumed by a processor while executing a 
spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of 
power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-wait loop greatly reduces the processor’s power consumption.
This instruction was introduced in the Pentium 4 processors , but is backward compatible with all IA-32 processors. 
In earlier IA-32 processors, the PAUSE instruction operat es like a NOP instruction. The Pentium 4 and Intel Xeon 
processors implement the PAUSE instruction as a delay. Th e delay is finite and can be zero for some processors. 
This instruction does not change the architectural state of the processor (that is, it performs essentially a delaying no-op operation).
Operation
Execute_Next_Instruction(DELAY);
None.
En64-Bit 
F3 90 PAUSE ZO Valid Valid Gives hint  to processor that improves 
performance of spin-wait loops.
ZO N/A N/A N/A N/APAVGB/PAVGW—Average Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-231PAVGB/PAVGW—Average Packed Integers
Opcode/
Mode 
Feature 
NP 0F E0 /r1
PAVGB mm1, mm2/m64
NOTES:
ware Developer’s Manual, Volume 2B, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg -

Operation
None.
En64-Bit 
Opcode/
Mode 
Feature 
NP 0F E0 /r1
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSE Average packed unsigned byte integers from 
mm2/m64 and mm1 with rounding.
66 0F E0, /r
PAVGB xmm1, xmm2/m128A V/V SSE2 Average packed unsigned byte integers from 
xmm2/m128 and xmm1 with rounding.
NP 0F E3 /r1
PAVGW mm1, mm2/m64AV / V  S S E A v e r a g e  p a c k e d  u n s i gned word in tegers from 
66 0F E3 /r
PAVGW xmm1, xmm2/m128A V/V SSE2 Average packed unsigned word integers from 
VEX.128.66.0F.WIG E0 /r
VPAVGB xmm1, xmm2, xmm3/m128B V/V AVX Average packed unsigned byte integers from 
xmm3/m128 and xmm2 with rounding.
VEX.128.66.0F.WIG E3 /r
VPAVGW xmm1, xmm2, xmm3/m128BV / V  A V X A v e r a g e  p a c k e d  u n s i gned word in tegers from 
VEX.256.66.0F .WIG E0 /r
VPAVGB ymm1, ymm2, ymm3/m256B V/V AVX2 Average packed unsigned byte integers from 
ymm2, and ymm3/m256 with rounding and 
store to ymm1.
VEX.256.66.0F .WIG E3 /r
VPAVGW ymm1, ymm2, ymm3/m256B V/V AVX2 Average packed unsigned word integers from 
ymm2, ymm3/m256 with  rounding to ymm1.
EVEX.128.66.0F.WIG E0 /r
VPAVGB xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWAverage packed unsigned byte integers from 
xmm2, and xmm3/m128 with rounding and 
store to xmm1 under writemask k1.
EVEX.256.66.0F.WIG E0 /r
VPAVGB ymm1 {k1}{z}, ymm2, ymm3/m256C V/V AVX512VL
store to ymm1 under writemask k1.
EVEX.512.66.0F.WIG E0 /r
VPAVGB zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Average packed unsigned byte integers from 
zmm2, and zmm3/m512 with rounding and store to zmm1 under writemask k1.
EVEX.128.66.0F.WIG E3 /r
VPAVGW xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWAverage packed unsigned word integers from 
xmm2, xmm3/m128 with rounding to xmm1 
under writemask k1.
EVEX.256.66.0F.WIG E3 /r
VPAVGW ymm1 {k1}{z}, ymm2, ymm3/m256C V/V AVX512VL
ymm2, ymm3/m256 with  rounding to ymm1 
EVEX.512.66.0F.WIG E3 /r
VPAVGW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Average packed un signed word in tegers from 
zmm2, zmm3/m512 with rounding to zmm1 under writemask k1.PAVGB/PAVGW—Average Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-232 Vol. 2BInstruction Operand Encoding
Performs a SIMD average of the packed unsigned intege rs from the source operand (second operand) and the 
destination operand (first operand), and stores the results in the destination operand. For each corresponding pair 
of data elements in the first and second operands, the el ements are added together, a 1 is added to the temporary 
sum, and that result is shifted right one bit position. 
The (V)PAVGB instruction operates on packed unsigned bytes and the (V)PAVGW instruction operates on packed 
unsigned words.
access additional registers (XMM8-XMM15).
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The 
register or a 512-bit memory location. Th e destination operand is a ZMM register.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand 
is a YMM register or a 256-bit memory location. The destination operand is a YMM register. 
is an XMM register or 128-bit memory location. The de stination operand is an XMM register. The upper bits ( MAXVL-
Operation
PAVGB (With 64-bit Operands)
DEST[7:0] := (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
(* Repeat operation performed for bytes 2 through 6 *)DEST[63:56] := (SRC[63:56] + DEST[63:56] + 1) >> 1;
PAVGW (With 64-bit Operands)
DEST[15:0] := (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
(* Repeat operation performed for words 2 and 3 *)DEST[63:48] := (SRC[63:48] + DEST[63:48] + 1) >> 1;
PAVGB (With 128-bit Operands)
DEST[7:0] := (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before sh ifting is 9 bits *)
(* Repeat operation performed for bytes 2 through 14 *)DEST[127:120] := (SRC[127:120] + DEST[127:120] + 1) >> 1;
PAVGW (With 128-bit Operands)
(* Repeat operation performed for words 2 through 6 *)DEST[127:112] := (SRC[127:112] + DEST[127:112] + 1) >> 1;Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APAVGB/PAVGW—Average Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-233VPAVGB (VEX.128 Encoded Version)
DEST[7:0] := (SRC1[7:0] + SRC2[7:0] + 1) >> 1; (* Repeat operation performed for bytes 2 through 15 *)DEST[127:120] := (SRC1[127:120] + SRC2[127:120] + 1) >> 1DEST[MAXVL-1:128] := 0
VPAVGW (VEX.128 Encoded Version)
DEST[15:0] := (SRC1[15:0] + SRC2[15:0] + 1) >> 1; (* Repeat operation performed for 16-bit words 2 through 7 *)
DEST[127:112] := (SRC1[127:112] + SRC2[127:112] + 1) >> 1DEST[MAXVL-1:128] := 0
VPAVGB (VEX.256 Encoded Instruction)
DEST[7:0] := (SRC1[7:0] + SRC2[7:0] + 1) >> 1;  (* Temp sum before shifting is 9 bits *)
(* Repeat operation performed for bytes 2 through 31)DEST[255:248] := (SRC1[255:248] + SRC2[255:248] + 1) >> 1;
VPAVGW (VEX.256 Encoded Instruction)
DEST[15:0] := (SRC1[15:0] + SRC2[15:0] + 1) >> 1;  (* Temp sum before shifting is 17 bits *)
(* Repeat operation performed for words 2 through 15)DEST[255:14]) := (SRC1[255:240] + SRC2[255:240] + 1) >> 1;
VPAVGB (EVEX encoded versions)(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1
THEN DEST[i+7:i] := (SRC1[i+7:i] + SRC2[i+7:i] + 1)  >> 1; (* Temp sum before  shifting is 9 bits *)
ELSE 
FI
FI;
VPAVGW (EVEX Encoded Versions)
THEN DEST[i+15:i] := (SRC1[i+15:i] + SRC2[i+15:i] + 1) >> 1
; (* Temp sum before shifting is 17 bits *)
ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PAVGB/PAVGW—Average Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-234 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalents
VPAVGB __m512i _mm512_avg_epu8( __m512i a, __m512i b);
VPAVGW __m512i _mm512_avg_epu16( __m512i a, __m512i b);VPAVGB __m512i _mm512_mask_avg_epu8(__m512i  s, __mmask64 m, __m512i a, __m512i b);
VPAVGW __m512i _mm512_mask_avg_epu16(__m512i  s, __mmask32 m, __m512i a, __m512i b);
VPAVGB __m512i _mm512_maskz_avg_epu8(  __mmask64 m, __m512i a, __m512i b);
VPAVGW __m512i _mm512_maskz_avg_epu16(  __mmask32 m, __m512i a, __m512i b);
VPAVGB __m256i _mm256_mask_avg_epu8(__m256i  s, __mmask32 m, __m256i a, __m256i b);
VPAVGW __m256i _mm256_mask_avg_epu16(__m256i  s, __mmask16 m, __m256i a, __m256i b);
VPAVGB __m256i _mm256_maskz_avg_epu8(  __mmask32 m, __m256i a, __m256i b);
VPAVGW __m256i _mm256_maskz_avg_epu16(  __mmask16 m, __m256i a, __m256i b);
VPAVGB __m128i _mm_mask_avg_epu8(__m128i s, __mmask16 m, __m128i a, __m128i b);
VPAVGW __m128i _mm_mask_avg_epu16(__m128i  s, __mmask8 m, __m128i a, __m128i b);
VPAVGB __m128i _mm_maskz_avg_epu8( __m mask16 m, __m128i a, __m128i b);
VPAVGW __m128i _mm_maskz_avg_epu16( __mmask8 m, __m128i a, __m128i b);PAVGB __m64 _mm_avg_pu8 (__m64 a, __m64 b)PAVGW __m64 _mm_avg_pu16 (__m64 a, __m64 b)(V)PAVGB __m128i _mm_avg_epu8 ( __m128i a, __m128i b)(V)PAVGW __m128i _mm_avg_epu16 ( __m128i a, __m128i b)VPAVGB __m256i _mm256_avg_epu8 ( __m256i a, __m256i b)VPAVGW __m256i _mm256_avg_epu16 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PBLENDVB—Variable Blend Packed BytesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-235PBLENDVB—Variable Blend Packed Bytes

None.
None.
Conditionally copies byte elements from the source oper and (second operand) to the destination operand (first 
operand) depending on mask bits defined in the implicit  third register argument, XMM0. The mask bits are the 
most significant bit in each byte element of the XMM0 register.
If a mask bit is “1", then the corresponding byte element in the source operand is copied to the destination, else 
the byte element in the destination operand is left unchanged.
The register assignment of the implicit third operan d is defined to be the architectural register XMM0.
to be the architectural register XMM0. An attempt to  execute PBLENDVB with a VEX prefix will cause #UD.
source operand is an XMM register or 128-bit memory loca tion. The mask operand is the third source register, and 
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is ignored. The upper bits (MAXVL-1:128) of the corresponding  YMM register (destination register) are zeroed. VEX.L 
must be 0, otherwise the instruction will #UD. VEX. W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and the destination operand are YMM registers. The second 
source operand is an YMM register or 256-bit memory loca tion. The third source register is an YMM register and 
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is 
ignored. 
VPBLENDVB permits the mask to be any XMM or YMM register . In contrast, PBLENDVB treats XMM0 implicitly as the 
mask and do not support non-destructive destination oper ation. An attempt to execute PBLENDVB encoded with a 
VEX prefix will cause a #UD exception.
Operation
PBLENDVB (128-bit Legacy SSE Version)
MASK := XMM0IF (MASK[7] = 1) THEN DEST[7:0] := SRC[7:0];ELSE DEST[7:0] := DEST[7:0];IF (MASK[15] = 1) THEN DEST[15:8] := SRC[15:8];ELSE DEST[15:8] := DEST[15:8];IF (MASK[23] = 1) THEN DEST[23:16] := SRC[23:16]Opcode/
Mode 
Feature 
66 0F 38 10 /r
PBLENDVB xmm1, xmm2/m128, <XMM0>RM V/V SSE4_1 Select byte values from xmm1 and xmm2/m128 
from mask specified in the high bit of each byte 
VEX.128.66.0F3A.W0 4C /r /is4
VPBLENDVB xmm1, xmm2, xmm3/m128, xmm4RVMR V/V AVX Select byte values from xmm2 and xmm3/m128 
using mask bits in the specified mask register, xmm4, and store the values into xmm1.
VEX.256.66.0F3A.W0 4C /r /is4
VPBLENDVB ymm1, ymm2, ymm3/m256, ymm4RVMR V/V AVX2 Select byte values from ymm2 and ymm3/m256 
in ymm4 and store the values into ymm1.
RM ModRM:reg (r, w) ModRM:r/m (r) <XMM0> N/A
RVMR ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8[7:4]PBLENDVB—Variable Bl end Packed BytesINSTRUCTION SET REFERENCE, M-U
4-236 Vol. 2BELSE DEST[23:16] := DEST[23:16];
IF (MASK[31] = 1) THEN DEST[31:24] := SRC[31:24]ELSE DEST[31:24] := DEST[31:24];IF (MASK[39] = 1) THEN DEST[39:32] := SRC[39:32]ELSE DEST[39:32] := DEST[39:32];IF (MASK[47] = 1) THEN DEST[47:40] := SRC[47:40]ELSE DEST[47:40] := DEST[47:40];IF (MASK[55] = 1) THEN DEST[55:48] := SRC[55:48]ELSE DEST[55:48] := DEST[55:48];IF (MASK[63] = 1) THEN DEST[63:56] := SRC[63:56]ELSE DEST[63:56] := DEST[63:56];IF (MASK[71] = 1) THEN DEST[71:64] := SRC[71:64]ELSE DEST[71:64] := DEST[71:64];IF (MASK[79] = 1) THEN DEST[79:72] := SRC[79:72]ELSE DEST[79:72] := DEST[79:72];IF (MASK[87] = 1) THEN DEST[87:80] := SRC[87:80]ELSE DEST[87:80] := DEST[87:80];IF (MASK[95] = 1) THEN DEST[95:88] := SRC[95:88]ELSE DEST[95:88] := DEST[95:88];IF (MASK[103] = 1) THEN DE ST[103:96] := SRC[103:96]
ELSE DEST[103:96] := DEST[103:96];IF (MASK[111] = 1) THEN DEST[111:104] := SRC[111:104]ELSE DEST[111:104] := DEST[111:104];IF (MASK[119] = 1) THEN DEST[119:112] := SRC[119:112]ELSE DEST[119:112] := DEST[119:112];IF (MASK[127] = 1) THEN DEST[127:120] := SRC[127:120]ELSE DEST[127:120] := DEST[127:120])DEST[MAXVL-1:128] (Unmodified)
VPBLENDVB (VEX.128 Encoded Version)
MASK := SRC3IF (MASK[7] = 1) THEN DEST[7:0] := SRC2[7:0];
ELSE DEST[7:0] := SRC1[7:0];
IF (MASK[15] = 1) THEN DEST[15:8] := SRC2[15:8];ELSE DEST[15:8] := SRC1[15:8];IF (MASK[23] = 1) THEN DEST[23:16] := SRC2[23:16]ELSE DEST[23:16] := SRC1[23:16];IF (MASK[31] = 1) THEN DEST[31:24] := SRC2[31:24]ELSE DEST[31:24] := SRC1[31:24];IF (MASK[39] = 1) THEN DEST[39:32] := SRC2[39:32]ELSE DEST[39:32] := SRC1[39:32];IF (MASK[47] = 1) THEN DEST[47:40] := SRC2[47:40]ELSE DEST[47:40] := SRC1[47:40];IF (MASK[55] = 1) THEN DEST[55:48] := SRC2[55:48]ELSE DEST[55:48] := SRC1[55:48];IF (MASK[63] = 1) THEN DEST[63:56] := SRC2[63:56]ELSE DEST[63:56] := SRC1[63:56];IF (MASK[71] = 1) THEN DEST[71:64] := SRC2[71:64]ELSE DEST[71:64] := SRC1[71:64];IF (MASK[79] = 1) THEN DEST[79:72] := SRC2[79:72]ELSE DEST[79:72] := SRC1[79:72];IF (MASK[87] = 1) THEN DEST[87:80] := SRC2[87:80]ELSE DEST[87:80] := SRC1[87:80];IF (MASK[95] = 1) THEN DEST[95:88] := SRC2[95:88]PBLENDVB—Variable Blend Packed BytesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-237ELSE DEST[95:88] := SRC1[95:88];
IF (MASK[103] = 1) THEN DEST[103:96] := SRC2[103:96]ELSE DEST[103:96] := SRC1[103:96];IF (MASK[111] = 1) THEN DEST[111:104] := SRC2[111:104]ELSE DEST[111:104] := SRC1[111:104];IF (MASK[119] = 1) THEN DEST[119:112] := SRC2[119:112]ELSE DEST[119:112] := SRC1[119:112];IF (MASK[127] = 1) THEN DEST[127:120] := SRC2[127:120]ELSE DEST[127:120] := SRC1[127:120])DEST[MAXVL-1:128] := 0
VPBLENDVB (VEX.256 Encoded Version)
MASK := SRC3IF (MASK[7] == 1) THEN DEST[7:0] := SRC2[7:0];
ELSE DEST[7:0] := SRC1[7:0];IF (MASK[15] == 1) THEN DEST[15:8] := SRC2[15:8];ELSE DEST[15:8] := SRC1[15:8];IF (MASK[23] == 1) THEN DEST[23:16] := SRC2[23:16]ELSE DEST[23:16] := SRC1[23:16];IF (MASK[31] == 1) THEN DEST[31:24] := SRC2[31:24]ELSE DEST[31:24] := SRC1[31:24];IF (MASK[39] == 1) THEN DEST[39:32] := SRC2[39:32]ELSE DEST[39:32] := SRC1[39:32];IF (MASK[47] == 1) THEN DEST[47:40] := SRC2[47:40]ELSE DEST[47:40] := SRC1[47:40];IF (MASK[55] == 1) THEN DEST[55:48] := SRC2[55:48]ELSE DEST[55:48] := SRC1[55:48];IF (MASK[63] == 1) THEN DEST[63:56] := SRC2[63:56]ELSE DEST[63:56] := SRC1[63:56];IF (MASK[71] == 1) THEN DEST[71:64] := SRC2[71:64]ELSE DEST[71:64] := SRC1[71:64];IF (MASK[79] == 1) THEN DEST[79:72] := SRC2[79:72]ELSE DEST[79:72] := SRC1[79:72];IF (MASK[87] == 1) THEN DEST[87:80] := SRC2[87:80]ELSE DEST[87:80] := SRC1[87:80];IF (MASK[95] == 1) THEN DEST[95:88] := SRC2[95:88]ELSE DEST[95:88] := SRC1[95:88];IF (MASK[103] == 1) THEN DEST[103:96] := SRC2[103:96]ELSE DEST[103:96] := SRC1[103:96];IF (MASK[111] == 1) THEN DEST[111:104] := SRC2[111:104]ELSE DEST[111:104] := SRC1[111:104];IF (MASK[119] == 1) THEN DEST[119:112] := SRC2[119:112]ELSE DEST[119:112] := SRC1[119:112];IF (MASK[127] == 1) THEN DEST[127:120] := SRC2[127:120]ELSE DEST[127:120] := SRC1[127:120])IF (MASK[135] == 1) THEN DEST[135:128] := SRC2[135:128];ELSE DEST[135:128] := SRC1[135:128];IF (MASK[143] == 1) THEN DEST[143:136] := SRC2[143:136];ELSE DEST[[143:136] := SRC1[143:136];IF (MASK[151] == 1) THEN DEST[151:144] := SRC2[151:144]ELSE DEST[151:144] := SRC1[151:144];IF (MASK[159] == 1) THEN DEST[159:152] := SRC2[159:152]ELSE DEST[159:152] := SRC1[159:152];IF (MASK[167] == 1) THEN DEST[167:160] := SRC2[167:160]PBLENDVB—Variable Bl end Packed BytesINSTRUCTION SET REFERENCE, M-U
4-238 Vol. 2BELSE DEST[167:160] := SRC1[167:160];
IF (MASK[175] == 1) THEN DEST[175:168] := SRC2[175:168]ELSE DEST[175:168] := SRC1[175:168];
IF (MASK[183] == 1) THEN DEST[183:176] := SRC2[183:176]ELSE DEST[183:176] := SRC1[183:176];
IF (MASK[191] == 1) THEN DEST[191:184] := SRC2[191:184]ELSE DEST[191:184] := SRC1[191:184];
IF (MASK[199] == 1) THEN DEST[199:192] := SRC2[199:192]ELSE DEST[199:192] := SRC1[199:192];
IF (MASK[207] == 1) THEN DEST[207:200] := SRC2[207:200]ELSE DEST[207:200] := SRC1[207:200]IF (MASK[215] == 1) THEN DEST[215:208] := SRC2[215:208]ELSE DEST[215:208] := SRC1[215:208];
IF (MASK[223] == 1) THEN DEST[223:216] := SRC2[223:216]ELSE DEST[223:216] := SRC1[223:216];
IF (MASK[231] == 1) THEN DEST[231:224] := SRC2[231:224]ELSE DEST[231:224] := SRC1[231:224];
IF (MASK[239] == 1) THEN DEST[239:232] := SRC2[239:232]ELSE DEST[239:232] := SRC1[239:232];
IF (MASK[247] == 1) THEN DEST[247:240] := SRC2[247:240]ELSE DEST[247:240] := SRC1[247:240];
IF (MASK[255] == 1) THEN DEST[255:248] := SRC2[255:248]ELSE DEST[255:248] := SRC1[255:248]
(V)PBLENDVB __m128i _mm_blendv_epi8 (__m128i v1, __m128i v2, __m128i mask);
VPBLENDVB __m256i _mm256_blendv_epi8 (__m256i v1, __m256i v2, __m256i mask);

None.
None.
#UD If VEX.W = 1.PBLENDW—Blend Packed WordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-239PBLENDW—Blend Packed Words
Words from the source operand (second operand) are co nditionally written to the destination operand (first 
operand) depending on bits in the immediate operand (thi rd operand). The immediate bits (bits 7:0) form a mask 
that determines whether the corresponding word in the dest ination is copied from the source. If a bit in the mask, 
corresponding to a word, is “1", then the word is copi ed, else the word element in the destination operand is 
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The 
first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination 
register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The 
first source and destination operands are XMM registers.  Bits (MAXVL-1:128) of the corresponding YMM register 
are zeroed.
Operation
PBLENDW (128-bit Legacy SSE Version)
IF (imm8[0] = 1) THEN DEST[15:0] := SRC[15:0]ELSE DEST[15:0] := DEST[15:0]IF (imm8[1] = 1) THEN DEST[31:16] := SRC[31:16]ELSE DEST[31:16] := DEST[31:16]IF (imm8[2] = 1) THEN DEST[47:32] := SRC[47:32]ELSE DEST[47:32] := DEST[47:32]IF (imm8[3] = 1) THEN DEST[63:48] := SRC[63:48]ELSE DEST[63:48] := DEST[63:48]IF (imm8[4] = 1) THEN DEST[79:64] := SRC[79:64]ELSE DEST[79:64] := DEST[79:64]IF (imm8[5] = 1) THEN DEST[95:80] := SRC[95:80]ELSE DEST[95:80] := DEST[95:80]IF (imm8[6] = 1) THEN DEST[111:96] := SRC[111:96]ELSE DEST[111:96] := DEST[111:96]IF (imm8[7] = 1) THEN DEST[127:112] := SRC[127:112]Opcode/
Mode 
Feature 
66 0F 3A 0E /r ib
PBLENDW xmm1, xmm2/m128, imm8RMI V/V SSE4_1 Select words from xmm1 and xmm2/m128 from 
mask specified in imm8 and store the values into 
xmm1.
VEX.128.66.0F3A.WIG 0E /r ib
VPBLENDW xmm1, xmm2, xmm3/m128, imm8RVMI V/V AVX Select words from xmm2 and xmm3/m128 from 
mask specified in imm8 and store the values into xmm1.
VEX.256.66.0F3A.WIG 0E /r ib
VPBLENDW ymm1, ymm2, ymm3/m256, imm8RVMI V/V AVX2 Select words from  ymm2 and ymm3/m256 from 
ymm1.
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8PBLENDW—Blend Packed WordsINSTRUCTION SET REFERENCE, M-U
4-240 Vol. 2BELSE DEST[127:112] := DEST[127:112]
VPBLENDW (VEX.128 Encoded Version)
IF (imm8[0] = 1) THEN DEST[15:0] := SRC2[15:0]
ELSE DEST[15:0] := SRC1[15:0]IF (imm8[1] = 1) THEN DEST[31:16] := SRC2[31:16]ELSE DEST[31:16] := SRC1[31:16]IF (imm8[2] = 1) THEN DEST[47:32] := SRC2[47:32]ELSE DEST[47:32] := SRC1[47:32]IF (imm8[3] = 1) THEN DEST[63:48] := SRC2[63:48]ELSE DEST[63:48] := SRC1[63:48]IF (imm8[4] = 1) THEN DEST[79:64] := SRC2[79:64]ELSE DEST[79:64] := SRC1[79:64]IF (imm8[5] = 1) THEN DEST[95:80] := SRC2[95:80]ELSE DEST[95:80] := SRC1[95:80]IF (imm8[6] = 1) THEN DEST[111:96] := SRC2[111:96]ELSE DEST[111:96] := SRC1[111:96]IF (imm8[7] = 1) THEN DEST [127:112] := SRC2[127:112]
ELSE DEST[127:112] := SRC1[127:112]DEST[MAXVL-1:128] := 0
VPBLENDW (VEX.256 Encoded Version)
IF (imm8[0] == 1) THEN DEST[15:0] := SRC2[15:0]ELSE DEST[15:0] := SRC1[15:0]IF (imm8[1] == 1) THEN DE ST[31:16] := SRC2[31:16]
ELSE DEST[31:16] := SRC1[31:16]IF (imm8[2] == 1) THEN DE ST[47:32] := SRC2[47:32]
ELSE DEST[47:32] := SRC1[47:32]IF (imm8[3] == 1) THEN DE ST[63:48] := SRC2[63:48]
ELSE DEST[63:48] := SRC1[63:48]IF (imm8[4] == 1) THEN DE ST[79:64] := SRC2[79:64]
ELSE DEST[79:64] := SRC1[79:64]IF (imm8[5] == 1) THEN DE ST[95:80] := SRC2[95:80]
ELSE DEST[95:80] := SRC1[95:80]IF (imm8[6] == 1) THEN DEST[111:96] := SRC2[111:96]ELSE DEST[111:96] := SRC1[111:96]IF (imm8[7] == 1) THEN DE ST[127:112] := SRC2[127:112]
ELSE DEST[127:112] := SRC1[127:112]IF (imm8[0] == 1) THEN DE ST[143:128] := SRC2[143:128]
ELSE DEST[143:128] := SRC1[143:128]IF (imm8[1] == 1) THEN DE ST[159:144] := SRC2[159:144]
ELSE DEST[159:144] := SRC1[159:144]IF (imm8[2] == 1) THEN DE ST[175:160] := SRC2[175:160]
ELSE DEST[175:160] := SRC1[175:160]IF (imm8[3] == 1) THEN DE ST[191:176] := SRC2[191:176]
ELSE DEST[191:176] := SRC1[191:176]IF (imm8[4] == 1) THEN DE ST[207:192] := SRC2[207:192]
ELSE DEST[207:192] := SRC1[207:192]IF (imm8[5] == 1) THEN DE ST[223:208] := SRC2[223:208]
ELSE DEST[223:208] := SRC1[223:208]IF (imm8[6] == 1) THEN DE ST[239:224] := SRC2[239:224]
ELSE DEST[239:224] := SRC1[239:224]IF (imm8[7] == 1) THEN DE ST[255:240] := SRC2[255:240]
ELSE DEST[255:240] := SRC1[255:240]PBLENDW—Blend Packed WordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-241Intel C/C++ Compiler Intrinsic Equivalent
(V)PBLENDW __m128i _mm_blend_epi16 (__m128i v1, __m128i v2, const int mask);
VPBLENDW __m256i _mm256_blend_epi16 (__m256i v1, __m256i v2, const int mask)
None.
None.
#UD If VEX.L = 1 and AVX2 = 0.PCLMULQDQ—Carry-Less Multiplication QuadwordINSTRUCTION SET REFERENCE, M-U
4-242 Vol. 2BPCLMULQDQ—Carry-Less Mu ltiplication Quadword
Performs a carry-less multiplication of two quadwords, se lected from the first source and second source operand 
according to the value of the immediate byte. Bits 4 and 0 ar e used to select which 64-bit half of each operand to 
use according to Table 4-13, other bits of the immediate byte are ignored. 
Mode 
66 0F 3A 44 /r ib
PCLMULQDQ xmm1, xmm2/m128, imm8A V/V PCLMULQDQ Carry-less multipli cation of one quadword of 
xmm1 by one quadword of xmm2/m128, 
stores the 128-bit result in xmm1. The imme-
diate is used to determine which quadwords of xmm1 and xmm2/m128 should be used.
VEX.128.66.0F3A.WIG 44 /r ib
VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8B V/V PCLMULQDQ 
AVXCarry-less multiplication  of one quadword of 
xmm2 by one quadword of xmm3/m128, 
stores the 128-bit result in xmm1. The imme-diate is used to determine which quadwords 
of xmm2 and xmm3/m128 should be used.
VEX.256.66.0F3A.WIG 44 /r /ib 
VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8BV / V V P C L M U L Q D Q
AVX Carry-less multiplication  of one quadword of 
ymm2 by one quadword of ymm3/m256, 
stores the 128-bit result in ymm1. The imme-
diate is used to determine which quadwords of ymm2 and ymm3/m256  should be used.
EVEX.128.66.0F3A.WIG 44 /r /ib
VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8CV / V V P C L M U L Q D Q
AVX512VLCarry-less multiplication  of one quadword of 
EVEX.256.66.0F3A.WIG 44 /r /ib
VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8CV / V V P C L M U L Q D Q
ymm2 by one quadword of ymm3/m256, stores the 128-bit result in ymm1. The imme-
diate is used to determine which quadwords 
of ymm2 and ymm3/m256  should be used.
EVEX.512.66.0F3A.WIG 44 /r /ib
VPCLMULQDQ zmm1, zmm2, zmm3/m512, imm8CV / V V P C L M U L Q D Q
AVX512FCarry-less multiplication  of one quadword of 
zmm2 by one quadword of zmm3/m512, 
stores the 128-bit result in zmm1. The imme-
diate is used to determine which quadwords of zmm2 and zmm3/m512 should be used.
C Full Mem ModRM:reg (w) EVEX.vv vv (r) ModRM:r/m (r) imm8 (r)PCLMULQDQ—Carry-Less Multiplication QuadwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-243The first source operand and the destination operand ar e the same and must be a ZMM/YMM/XMM register. The 
second source operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location. Bits (VL_MAX-
1:128) of the corresponding YMM dest ination register remain unchanged.
Compilers and assemblers may implement the following ps eudo-op syntax to simplify  programming and emit the 
required encoding for imm8.
Operation
define PCLMUL128(X,Y) : // helper function
FOR i := 0 to 63:
TMP [ i ] := X[ 0 ] and Y[ i ]FOR j := 1 to i:
TMP [ i ] := TMP [ i ] xo r (X[ j ] and Y[ i - j ])
DEST[ i ] := TMP[ i ]
FOR i := 64 to 126:
TMP [ i ] := 0FOR j := i - 63 to 63:

Operation
DEST[127] := 0;RETURN DEST // 128b vectorTable 4-13.  PCLMULQDQ Quadword Selection of Immediate Byte
Imm[4] Imm[0] PCLMULQDQ Operation
00C L _ M U L (  S R C 21[63:0], SRC1[63:0] )
NOTES:
1. SRC2 denotes the second source operand, which can be a register or memory; SRC1 denotes the first source and destination ope r-
and.0 1 CL_MUL( SRC2[63:0], SRC1[127:64] )
1 0 CL_MUL( SRC2[127:64], SRC1[63:0] )
1 1 CL_MUL( SRC2[127:64], SRC1[127:64] )
Table 4-14.  Pseudo-Op and PCLMULQDQ Implementation
Pseudo-Op Imm8 Encoding
PCLMULLQLQDQ  xmm1, xmm2 0000_0000B
PCLMULHQLQDQ  xmm1, xmm2 0000_0001B
PCLMULLQHQDQ  xmm1, xmm2 0001_0000B
PCLMULHQHQDQ  xmm1, xmm2 0001_0001BPCLMULQDQ—Carry-Less Multiplication QuadwordINSTRUCTION SET REFERENCE, M-U
4-244 Vol. 2BPCLMULQDQ (SSE Version)
IF imm8[0] = 0:
TEMP1 := SRC1.qword[0]
ELSE:
TEMP1 := SRC1.qword[1]
IF imm8[4] = 0:
TEMP2 := SRC2.qword[0]
ELSE:
TEMP2 := SRC2.qword[1]
DEST[127:0] := PCLMUL128(TEMP1, TEMP2)DEST[MAXVL-1:128] (Unmodified)
VPCLMULQDQ (128b and 256b VEX Encoded Versions)
(KL,VL) = (1,128), (2,256)FOR i= 0 to KL-1:
TEMP1 := SRC1.xmm[i].qword[0]
ELSE:
TEMP1 := SRC1.xmm[i].qword[1]
TEMP2 := SRC2.xmm[i].qword[0]
ELSE:
TEMP2 := SRC2.xmm[i].qword[1]
DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)
VPCLMULQDQ (EVEX Encoded Version)
ELSE:
ELSE:
(V)PCLMULQDQ __m128i  _mm_clmulepi64_si128 (__m128i, __m128i, const int)VPCLMULQDQ __m256i _mm256_clmulepi64_epi128(__m256i, __m256i, const int);VPCLMULQDQ __m512i _mm512_clmulepi64_epi128(__m512i, __m512i, const int);
None.
EVEX-encoded: See Table 2-50, “Typ e E4NF Class Exception Conditions.”PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-245PCMPEQB/PCMPEQW/PCMPEQD— Comp are Packed Data for Equal
Opcode/
InstructionOp/ En 64/32 bit 
Mode 
Feature 
NP 0F 74 /r1
PCMPEQB mm, mm/m64A V/V MMX Compare packed bytes in mm/m64 and mm for 
equality.
66 0F 74 /r
PCMPEQB xmm1, xmm2/m128A V/V SSE2 Compare packed bytes in xmm2/m128 and 
xmm1 for equality.
NP 0F 75 /r1
PCMPEQW mm, mm/m64A V/V MMX Compare packed words in mm/m64 and mm 
for equality.
66 0F 75 /r
PCMPEQW xmm1, xmm2/m128A V/V SSE2 Compare packed words in xmm2/m128 and 
NP 0F 76 /r1
PCMPEQD mm, mm/m64A V/V MMX Compare packed doublewords in mm/m64 and 
mm for equality.
66 0F 76 /r
PCMPEQD xmm1, xmm2/m128A V/V SSE2 Compare packed doublewords in xmm2/m128 
and xmm1 for equality.
VEX.128.66.0F.WIG 74 /r
VPCMPEQB xmm1, xmm2, xmm3/m128B V/V AVX Compare packed bytes in xmm3/m128 and 
xmm2 for equality.
VEX.128.66.0F.WIG 75 /r
VPCMPEQW xmm1, xmm2, xmm3/m128B V/V AVX Compare packed words in xmm3/m128 and 
VEX.128.66.0F.WIG 76 /r
VPCMPEQD xmm1, xmm2, xmm3/m128B V/V AVX Compare packed doublewords in xmm3/m128 
and xmm2 for equality.
VEX.256.66.0F.WIG 74 /r
VPCMPEQB ymm1, ymm2, ymm3 /m256B V/V AVX2 Compare packed bytes in ymm3/m256 and 
ymm2 for equality.
VEX.256.66.0F.WIG 75 /r
VPCMPEQW ymm1, ymm2, ymm3 /m256B V/V AVX2 Compare packed words in ymm3/m256 and 
VEX.256.66.0F.WIG 76 /r
VPCMPEQD ymm1, ymm2, ymm3 /m256B V/V AVX2 Compare packed doublewords in ymm3/m256 
and ymm2 for equality.
EVEX.128.66.0F.W0 76 /r
VPCMPEQD k1 {k2}, xmm2, xmm3/m128/m32bcstC V/V AVX512VL
AVX512FCompare Equal between int32 vector xmm2 
and int32 vector xmm3/m128/m32bcst, and 
set vector mask k1 to reflect the zero/nonzero status of each element of the 
result, under writemask.
EVEX.256.66.0F.W0 76 /r
VPCMPEQD k1 {k2}, ymm2, ymm3/m256/m32bcstC V/V AVX512VL
AVX512FCompare Equal between int32 vector ymm2 
and int32 vector ymm3/m256/m32bcst, and set vector mask k1 to reflect the 
zero/nonzero status of each element of the 
EVEX.512.66.0F.W0 76 /r
VPCMPEQD k1 {k2}, zmm2, zmm3/m512/m32bcstC V/V AVX512F Compare Equal between int32 vectors in 
zmm2 and zmm3/m512/m32bcst, and set 
destination k1 according to the comparison 
results under writemask k2.
EVEX.128.66.0F.WIG 74 /r
VPCMPEQB k1 {k2}, xmm2, xmm3 /m128D V/V AVX512VL
AVX512BWCompare packed bytes in xmm3/m128 and 
xmm2 for equality and se t vector mask k1 to 
reflect the zero/nonzero status of each 
element of the result, under writemask.PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualINSTRUCTION SET REFERENCE, M-U
4-246 Vol. 2BInstruction Operand Encoding
Performs a SIMD compare for equality of the packed bytes, words, or doublewords in th e destination operand (first 
operand) and the source operand (second operand). If a pa ir of data elements is equal, the corresponding data 
element in the destination operand is set to all 1s; otherwise, it is set to all 0s. 
The (V)PCMPEQB instruction compares the corresponding  bytes in the destination and source operands; the 
(V)PCMPEQW instruction compares the corresponding wo rds in the destination and source operands; and the 
(V)PCMPEQD instruction compares th e corresponding doublewords in the destination and source operands.
128-bit Legacy SSE version: The second source operand ca n be an XMM register or a 128-bit memory location. The 
register remain unchanged.EVEX.256.66.0F.WIG 74 /r
VPCMPEQB k1 {k2}, ymm2, ymm3 /m256D V/V AVX512VL
AVX512BWCompare packed bytes in ymm3/m256 and 
ymm2 for equality and se t vector mask k1 to 
element of the result, under writemask.
EVEX.512.66.0F.WIG 74 /r
VPCMPEQB k1 {k2}, zmm2, zmm3 /m512D V/V AVX512BW Compare packed bytes in zmm3/m512 and 
zmm2 for equality and se t vector mask k1 to 
EVEX.128.66.0F.WIG 75 /r
VPCMPEQW k1 {k2}, xmm2, xmm3 /m128D V/V AVX512VL
AVX512BWCompare packed words in xmm3/m128 and 
xmm2 for equality and set vector mask k1 to 
EVEX.256.66.0F.WIG 75 /r
VPCMPEQW k1 {k2}, ymm2, ymm3 /m256D V/V AVX512VL
AVX512BWCompare packed words in ymm3/m256 and 
reflect the zero/nonzero status of each element of the result, under writemask.
EVEX.512.66.0F.WIG 75 /r
VPCMPEQW k1 {k2}, zmm2, zmm3 /m512D V/V AVX512BW Compare packed words in zmm3/m512 and 
NOTES:
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
D Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AOpcode/
Mode 
Feature 
FlagDescriptionPCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-247VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The 
or a 256-bit memory location. The destination operand is a YMM register.
EVEX encoded VPCMPEQD: The first source operand (sec ond operand) is a ZMM/YMM/XMM register. The second 
broadcasted from a 32-bit memory location. The destinatio n operand (first operand) is a mask register updated 
according to the writemask k2.
EVEX encoded VPCMPEQB/W: The first so urce operand (second operand) is a ZMM/YMM/XMM register. The second

EVEX encoded VPCMPEQB/W: The first so urce operand (second operand) is a ZMM/YMM/XMM register. The second 
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.
Operation
PCMPEQB (With 64-bit Operands)
IF DEST[7:0]  = SRC[7:0]
THEN DEST[7:0) := FFH; ELSE DEST[7:0] := 0; FI;
(* Continue comparison of 2nd thro ugh 7th bytes in DEST and SRC *)
IF DEST[63:56]
 = SRC[63:56]
THEN DEST[63:56] := FFH;ELSE DEST[63:56] := 0; FI;
COMPARE_BYTES_EQUAL (SRC1, SRC2)
IF SRC1[7:0] = SRC2[7:0]
THEN DEST[7:0] := FFH;ELSE DEST[7:0] := 0; FI;
(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)
IF SRC1[127:120] = SRC2[127:120]THEN DEST[127:120] := FFH;ELSE DEST[127:120] := 0; FI;
COMPARE_WORDS_EQUAL (SRC1, SRC2)
IF SRC1[15:0] = SRC2[15:0]THEN DEST[15:0] := FFFFH;ELSE DEST[15:0] := 0; FI;
(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)
IF SRC1[127:112] = SRC2[127:112]THEN DEST[127:112] := FFFFH;ELSE DEST[127:112] := 0; FI;
COMPARE_DWORDS_EQU AL (SRC1, SRC2)
IF SRC1[31:0] = SRC2[31:0]THEN DEST[31:0] := FFFFFFFFH;ELSE DEST[31:0] := 0; FI;
(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)
IF SRC1[127:96] = SRC2[127:96]THEN DEST[127:96] := FFFFFFFFH;ELSE DEST[127:96] := 0; FI;
PCMPEQB (With 128-bit Operands)
DEST[127:0] := COMPARE_BYTES_ EQUAL(DEST[127:0],SRC[127:0])
DEST[MAXVL-1:128 ] (Unmodified)PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualINSTRUCTION SET REFERENCE, M-U
4-248 Vol. 2BVPCMPEQB (VEX.128 Encoded Version)
DEST[127:0] := COMPARE_BYTES_ EQUAL(SRC1[127:0],SRC2[127:0])
VPCMPEQB (VEX.256 Encoded Version)
DEST[255:128] := COMPARE_BYTES_EQUAL(SRC1[255:128],SRC2[255:128])DEST[MAXVL-1:256] := 0
VPCMPEQB (EVEX Encoded Versions)
i := j * 8IF k2[j] OR *no writemask*
THEN 
/* signed comparison */CMP := SRC1[i+7:i ] == SRC2[i+7:i];
IF CMP = TRUE
FI;
PCMPEQW (With 64-bit Operands)
IF DEST[15:0]
 = SRC[15:0] 
THEN DEST[15:0] := FFFFH;ELSE DEST[15:0] := 0; FI;
(* Continue comparison of 2nd and 3rd words in DEST and SRC *)IF DEST[63:48] 
= SRC[63:48]
THEN DEST[63:48] := FFFFH;ELSE DEST[63:48] := 0; FI;
PCMPEQW (With 128-bit Operands)
DEST[127:0] := COMPARE_WORDS_EQUAL(DEST[127:0],SRC[127:0])DEST[MAXVL-1:128] (Unmodified)
VPCMPEQW (VEX.128 Encoded Version)
DEST[127:0] := COMPARE_WORDS_ EQUAL(SRC1[127:0 ],SRC2[127:0])
VPCMPEQW (VEX.256 Encoded Version)
DEST[255:128] := COMPARE_WORDS_EQUAL(SRC1[255:128],SRC2[255:128])DEST[MAXVL-1:256] := 0PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-249VPCMPEQW (EVEX Encoded Versions)
i := j * 16IF k2[j] OR *no writemask*
THEN 
/* signed comparison */CMP := SRC1[i+15:i] == SRC2[i+15:i];IF CMP = TRUE
ELSE DEST[j] := 0 ; ze roing-masking onlyFI;
FI;
PCMPEQD (With 64-bit Operands)
IF DEST[31:0]
 = SRC[31:0]
THEN DEST[31:0] := FFFFFFFFH; ELSE DEST[31:0] := 0; FI;
IF DEST[63:32]
 = SRC[63:32]
THEN DEST[63:32] := FFFFFFFFH;ELSE DEST[63:32] := 0; FI;
PCMPEQD (With 128-bit Operands)
DEST[127:0] := COMPARE_DWORDS _EQUAL(DEST[127:0],SRC[127:0])
VPCMPEQD (VEX.128 Encoded Version)
DEST[127:0] := COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])DEST[MAXVL-1:128] := 0
VPCMPEQD (VEX.256 Encoded Version)
DEST[127:0] := COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])DEST[255:128] := COMPARE_DWORDS_EQUAL(SRC1[255:128],SRC2[255:128])DEST[MAXVL-1:256] := 0
VPCMPEQD (EVEX Encoded Versions)
THEN 
/* signed comparison */IF (EVEX.b = 1) AN D (SRC2 *is memory*)
THEN CMP := SRC1[i+31:i] = SRC2[31:0];ELSE CMP := SRC1[i+31:i] = SRC2[i+31:i];
FI;
ENDFORPCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualINSTRUCTION SET REFERENCE, M-U
4-250 Vol. 2BDEST[MAX_KL-1:KL] := 0
VPCMPEQB __mmask64 _mm512_cmpeq_ep i8_mask(__m512i a, __m512i b);
VPCMPEQB __mmask64 _mm512_mask_cmpeq_epi8_mask(__mmask64 k, __m512i a, __m512i b);VPCMPEQB __mmask32 _mm256_cmpeq_ep i8_mask(__m256i a, __m256i b);
VPCMPEQB __mmask32 _mm256_mask_cmpeq_epi8_mask(__mmask32 k, __m256i a, __m256i b);VPCMPEQB __mmask16 _mm_cmpeq_ep i8_mask(__m128i a, __m128i b);
VPCMPEQB __mmask16 _mm_mask_cmpeq_epi8_ma sk(__mmask16 k, __m128i a, __m128i b);
VPCMPEQW __mmask32 _mm512_cmpeq_epi16_mask(__m512i a, __m512i b);VPCMPEQW __mmask32 _mm512_mask_cmpeq_epi16_mask(__mmask32 k, __m512i a, __m512i b);VPCMPEQW __mmask16 _mm256_cmpeq_epi16_mask(__m256i a, __m256i b);VPCMPEQW __mmask16 _mm256_mask_cmpeq_epi16_mask(__mmask16 k, __m256i a, __m256i b);VPCMPEQW __mmask8 _mm_cmpeq_epi16_mask(__m128i a, __m128i b);VPCMPEQW __mmask8 _mm_mask_cmpeq_epi16_m ask(__mmask8 k, __m128i a, __m128i b);
VPCMPEQD __mmask16 _mm512_cmpeq_epi32_mask( __m512i a, __m512i b);VPCMPEQD __mmask16 _mm512_mask_cmpeq_epi32_mask(__mmask16 k, __m512i a, __m512i b);VPCMPEQD __mmask8 _mm256_cmpeq_epi32_mask(__m256i a, __m256i b);VPCMPEQD __mmask8 _mm256_mask_cmpeq_epi32_mask(__mmask8 k, __m256i a, __m256i b);VPCMPEQD __mmask8 _mm_cmpeq_epi32_mask(__m128i a, __m128i b);VPCMPEQD __mmask8 _mm_mask_cmpeq_epi32_mask(__mmask8 k, __m128i a, __m128i b);PCMPEQB __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)PCMPEQW  __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)PCMPEQD __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)(V)PCMPEQB __m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b)(V)PCMPEQW __m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b)(V)PCMPEQD __m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b)VPCMPEQB __m256i _mm256_cmpeq_epi8 ( __m256i a, __m256i b)VPCMPEQW __m256i _mm256_cmpeq_epi16 ( __m256i a, __m256i b)VPCMPEQD __m256i _mm256_cmpeq_epi32 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded VPCMPEQD, see Table 2-49, “Type E4 Class Exception Conditions.”
EVEX-encoded VPCMPEQB/W, see Except ions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PCMPEQQ—Compare Packed Qword Data for EqualINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-251PCMPEQQ—Compare Packed Qword Data for Equal
Performs an SIMD compare for equality of the packed quadwords in the destin ation operand (first operand) and the 
source operand (second operand).  If a pair of data elements is equal, the corresponding data element in the desti-
nation is set to all 1s; otherwise, it is set to 0s.
EVEX encoded VPCMPEQQ: The first source operand (sec ond operand) is a ZMM/YMM/XMM register. The second 
broadcasted from a 64-bit memory location. The destinatio n operand (first operand) is a mask register updated 
according to the writemask k2.Opcode/
Mode 
Feature 
66 0F 38 29 /r
PCMPEQQ xmm1, xmm2/m128A V/V SSE4_1 Compare packed qwords in xmm2/m128 and 
VEX.128.66.0F38.WIG 29 /r
VPCMPEQQ xmm1, xmm2, xmm3/m128B V/V AVX Compare packed quadwords in xmm3/m128 
VEX.256.66.0F38.WIG 29 /r
VPCMPEQQ ymm1, ymm2, ymm3 /m256B V/V AVX2 Compare packed quadwords in ymm3/m256 
EVEX.128.66.0F38.W1 29 /r
VPCMPEQQ k1 {k2}, xmm2, xmm3/m128/m64bcstCV / V A V X 5 1 2 V L
AVX512FCompare Equal between int64 vector xmm2 
and int64 vector xmm3/m128/m64bcst, and 
set vector mask k1 to reflect the zero/nonzero 
status of each element of the result, under writemask.
EVEX.256.66.0F38.W1 29 /r
VPCMPEQQ k1 {k2}, ymm2, ymm3/m256/m64bcstCV / V A V X 5 1 2 V L
AVX512FCompare Equal between int64 vector ymm2 
and int64 vector ymm3/m256/m64bcst, and set vector mask k1 to reflect the zero/nonzero

Mode 
Feature 
and int64 vector ymm3/m256/m64bcst, and set vector mask k1 to reflect the zero/nonzero 
status of each element of the result, under 
EVEX.512.66.0F38.W1 29 /r
VPCMPEQQ k1 {k2}, zmm2, zmm3/m512/m64bcstC V/V AVX512F Compare Equal between int64 vector zmm2 
and int64 vector zmm3/m512/m64bcst, and 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APCMPEQQ—Compare Packed Qword Data for EqualINSTRUCTION SET REFERENCE, M-U
4-252 Vol. 2BOperation
PCMPEQQ (With 128-bit Operands)
IF (DEST[63:0] = SRC[63:0]) 
THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0; FI;
IF (DEST[127:64] = SRC[127:64]) 
THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;ELSE DEST[127:64] := 0; FI;
COMPARE_QWORDS_EQUAL (SRC1, SRC2)
IF SRC1[63:0] = SRC2[63:0]THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0; FI;IF SRC1[127:64] = SRC2[127:64]THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;ELSE DEST[127:64] := 0; FI;
VPCMPEQQ (VEX.128 Encoded Version)
DEST[127:0] := COMPARE_QWORDS_EQUAL(SRC1,SRC2)DEST[MAXVL-1:128] := 0
VPCMPEQQ (VEX.256 Encoded Version)
DEST[127:0] := COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])DEST[255:128] := COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])DEST[MAXVL-1:256] := 0
VPCMPEQQ (EVEX Encoded Versions)
THEN 
THEN CMP := SRC1[i+63:i] = SRC2[63:0];ELSE CMP := SRC1[i+63:i] = SRC2[i+63:i];
FI;
ENDFORDEST[MAX_KL-1:KL] := 0PCMPEQQ—Compare Packed Qword Data for EqualINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-253Intel C/C++ Compiler Intrinsic Equivalent
VPCMPEQQ __mmask8 _mm512_cmpeq_epi64_mask( __m512i a, __m512i b);
VPCMPEQQ __mmask8 _mm512_mask_cmpeq_epi64_ mask(__mmask8 k, __m512i a, __m512i b);
VPCMPEQQ __mmask8 _mm256_cmpeq_epi64_mask( __m256i a, __m256i b);VPCMPEQQ __mmask8 _mm256_mask_cmpeq_epi64_ mask(__mmask8 k, __m256i a, __m256i b);
VPCMPEQQ __mmask8 _mm_cmpeq_epi64_mask( __m128i a, __m128i b);VPCMPEQQ __mmask8 _mm_mask_cmpeq_epi64_m ask(__mmask8 k, __m128i a, __m128i b);
(V)PCMPEQQ __m128i _mm_cmpeq_epi64(__m128i a, __m128i b);VPCMPEQQ __m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);
None.
None.
EVEX-encoded VPCMPEQQ, see Table 2-49, “Type E4 Class Exception Conditions.”PCMPESTRI—Packed Compare Explicit Length Strings, Return IndexINSTRUCTION SET REFERENCE, M-U
4-254 Vol. 2BPCMPESTRI—Packed Compare Explicit Length Strings, Return Index
The instruction compares and processes data from two st ring fragments based on the encoded value in the imm8 
control byte (see Section 4.1, “Imm8 Control Byte Op eration for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMP-
ISTRM”), and generates an index st ored to the count register (ECX).
Each string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second 
operand) which contains the data elements of the string (byt e or word data). The second value is stored in an input 
length register. The input length register is EAX/RA X (for xmm1) or EDX/RDX (for xmm2/m128). The length 
represents the number of bytes/words which are valid for the respective xmm/m128 data. 
The length of each input is interpreted as being the absolu te-value of the value in the length register. The absolute-
value computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value 
in the length register is greater than 16 (8) or less than -16 (-8).
The comparison and aggregation operations are performed a ccording to the encoded value of imm8 bit fields (see 
Section 4.1). The index of the first (or last, according to i mm8[6]) set bit of IntRes2 (see Section 4.1.4) is returned 
in ECX. If no bits are set in IntRes2, ECX is set to 16 (8).
Note that the Arithmetic Flags are written in a non-standa rd manner in order to supply the most relevant informa-
tion:
CFlag – Reset if IntRes2 is equal to zero, set otherwise
ZFlag – Set if absolute-value of EDX is < 16 (8), reset otherwise
SFlag – Set if absolute -value of EAX is < 16 (8), reset otherwise
OFlag – IntRes2[0]AFlag – ResetPFlag – Reset
Effective Operand SizeOpcode/
Mode 
Feature 
66 0F 3A 61 /r imm8
PCMPESTRI xmm1, xmm2/m128, imm8RMI V/V SSE4_2 Perform a packed comparison of string data with 
explicit lengths, generating an index, and storing the 
result in ECX.
VEX.128.66.0F3A 61 /r ib
VPCMPESTRI xmm1, xmm2/m128, imm8RMI V/V AVX Perform a packed comp arison of string data with 
explicit lengths, generating an index, and storing the result in ECX.
RMI ModRM:reg (r) ModRM:r/m (r) imm8 N/A
Operating mode/size Operand 1 Ope rand 2 Length 1 Length 2 Result
16 bit xmm xmm/m128 EAX EDX ECX32 bit xmm xmm/m128 EAX EDX ECX64 bit xmm xmm/m128 EAX EDX ECX64 bit + REX.W xmm xmm/m128 RAX RDX ECXPCMPESTRI—Packed Compare Explicit Length Strings, Return IndexINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-255Intel C/C++ Compiler Intrinsic Equivalent For Returning Index 
int _mm_cmpestri (__m128i a, int la , __m128i b, int lb, const int mode);
Intel C/C++ Compiler Intrinsi cs For Reading EFlag Results
int _mm_cmpestra (__m128i a, int la , __m128i b, int lb, const int mode);
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);int _mm_cmpestro (__m128i a, int la , __m128i b, int lb , const int mode);
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode);int _mm_cmpestrz (__m128i a, int la , __m128i b, int lb, const int mode);
None.
See Table 2-21, “Type 4 Class Exception Conditions,” additionally, this instruction does not cause #GP if the 
memory operand is not aligned to 16 Byte boundary, and:
If VEX.vvvv ≠ 1111B.PCMPESTRM—Packed Compare Explicit Length Strings, Return MaskINSTRUCTION SET REFERENCE, M-U
4-256 Vol. 2BPCMPESTRM—Packed Compare Explicit  Length Strings, Return Mask
The instruction compares data from two string fragments ba sed on the encoded value in the imm8 contol byte (see 
Section 4.1, “Imm8 Control Byte Operation for PCMPES TRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and gener-
ates a mask stored to XMM0.
represents the number of bytes/words which are valid for the respective xmm/m128 data.  
Section 4.1). As defined by imm8[6], IntRes2 is then eith er stored to the least significant bits of XMM0 (zero 
extended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.
tion:
OFlag –IntRes2[0]AFlag – ResetPFlag – Reset
Note: In VEX.128 encoded versions, bits (MAXVL-1:128) of  XMM0 are zeroed. VEX.vvvv is reserved and must be 
1111b, VEX.L must be 0, otherwise the instruction will #UD.Opcode/
Mode 
Feature 
66 0F 3A 60 /r imm8
PCMPESTRM xmm1, xmm2/m128, imm8RMI V/V SSE4_2 Perform a packed comparison of string data 
with explicit lengths, generating a mask, and 
storing the resu lt in XMM0.
VEX.128.66.0F3A 60 /r ib
VPCMPESTRM xmm1, xmm2/m128, imm8RMI V/V AVX Perform a packed co mparison of string data 
with explicit lengths, generating a mask, and storing the resu lt in XMM0.
RMI ModRM:reg (r) ModRM:r/m (r) imm8 N/APCMPESTRM—Packed Compare Explicit Length Strings, Return MaskINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-257Effective Operand Size
Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask

Mode 
Feature 
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode);
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);
int _mm_cmpestro (__m128i a, int la , __m128i b, int lb , const int mode);
None.
If VEX.vvvv ≠ 1111B.Operating mode/size Operand 1 Operand 2 Length 1 Length 2 Result
16 bit xmm xmm/m128 EAX EDX XMM032 bit xmm xmm/m128 EAX EDX XMM0
64 bit xmm xmm/m128 EAX EDX XMM0
64 bit + REX.W xmm xmm/m128 RAX RDX XMM0PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed  Signed Integers for Greater ThanINSTRUCTION SET REFERENCE, M-U
4-258 Vol. 2BPCMPGTB/PCMPGTW/PCMPGTD—Compare Packe d Signed Integers for Greater Than
Opcode/
Mode 
Feature 
NP 0F 64 /r1
PCMPGTB mm, mm/m64A V/V MMX Compare packed signed byte integers in mm and 
mm/m64 for greater than.
66 0F 64 /r
PCMPGTB xmm1, xmm2/m128A V/V SSE2 Compare packed signed byte integers in xmm1 
and xmm2/m128 for greater than.
NP 0F 65 /r1
PCMPGTW mm, mm/m64A V/V MMX Compare packed signed word integers in mm and 
66 0F 65 /r
PCMPGTW xmm1, xmm2/m128A V/V SSE2 Compare packed signed word integers in xmm1 
NP 0F 66 /r1
PCMPGTD mm, mm/m64A V/V MMX Compare packed signed doubleword integers in 
mm and mm/m64 for greater than.
66 0F 66 /r
PCMPGTD xmm1, xmm2/m128A V/V SSE2 Compare packed signed doubleword integers in 
xmm1 and xmm2/m128 for greater than.
VEX.128.66.0F.WIG 64 /r
VPCMPGTB xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed byte integers in xmm2 
and xmm3/m128 for greater than.
VEX.128.66.0F.WIG 65 /r
VPCMPGTW xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed word integers in xmm2 
VEX.128.66.0F.WIG 66 /r
VPCMPGTD xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed doubleword integers in 
xmm2 and xmm3/m128 for greater than.
VEX.256.66.0F.WIG 64 /r
VPCMPGTB ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed byte integers in ymm2 
and ymm3/m256 for greater than.
VEX.256.66.0F.WIG 65 /r
VPCMPGTW ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed word integers in ymm2 
VEX.256.66.0F.WIG 66 /r
VPCMPGTD ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed doubleword integers in 
ymm2 and ymm3/m256 for greater than.
EVEX.128.66.0F.W0 66 /r
VPCMPGTD k1 {k2}, xmm2, 
AVX512FCompare Greater between int32 vector xmm2 and 
int32 vector xmm3/m128/m32bcst, and set 
vector mask k1 to reflec t the zero/nonzero status 
of each element of the result, under writemask.
EVEX.256.66.0F.W0 66 /r
VPCMPGTD k1 {k2}, ymm2, 
AVX512FCompare Greater between int32 vector ymm2 and 
int32 vector ymm3/m256/m32bcst, and set 
EVEX.512.66.0F.W0 66 /r
VPCMPGTD k1 {k2}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512F Compare Greater between int32 elements in 
destination k1 according to the comparison results under writemask. k2.
EVEX.128.66.0F.WIG 64 /r
VPCMPGTB k1 {k2} , xmm2, xmm3/m128DV / V A V X 5 1 2 V L
AVX512BWCompare packed signed byte integers in xmm2 
and xmm3/m128 for greater than, and set vector 
mask k1 to reflect the zero /nonzero status of each 
EVEX.256.66.0F.WIG 64 /r
VPCMPGTB k1 {k2}, ymm2, ymm3/m256DV / V A V X 5 1 2 V L
AVX512BWCompare packed signed byte integers in ymm2 
and ymm3/m256 for greate r than, and set vector 
element of the result, under writemask.PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed  Signed Integers for Greater ThanINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-259Instruction Operand Encoding
Performs an SIMD signed compare for the greater value of  the packed byte, word, or doubleword integers in the 
destination operand (first operand) and the source operan d (second operand). If a data element in the destination 
operand is greater than the corresponding date element in  the source operand, the corresponding data element in 
the destination operand is set to all 1s; otherwise, it is set to all 0s.
The PCMPGTB instruction compares the corresponding signed byte integers in the destination and source oper-
ands; the PCMPGTW instruction compares the corresponding signed word integers in the destination and source 
operands; and the PCMPGTD instruction compares the corre sponding signed doubleword integers in the destina-
tion and source operands.
Legacy SSE instructions: The source operand can be an MM X technology register or a 64-bit memory location. The 
first source operand and destination operand are XMM re gisters. Bits (MAXVL-1:128) of the corresponding YMM 
destination register remain unchanged. 
register are zeroed.EVEX.512.66.0F.WIG 64 /r
VPCMPGTB k1 {k2}, zmm2, zmm3/m512D V/V AVX512BW Compare packed signed byte integers in zmm2 and 
zmm3/m512 for greater than, and set vector 
EVEX.128.66.0F.WIG 65 /r
VPCMPGTW k1 {k2} , xmm2, xmm3/m128DV / V A V X 5 1 2 V L
AVX512BWCompare packed signed word integers in xmm2 
and xmm3/m128 for greate r than, and set vector 
EVEX.256.66.0F.WIG 65 /r
VPCMPGTW k1 {k2}, ymm2, ymm3/m256DV / V A V X 5 1 2 V L
AVX512BWCompare packed signed word integers in ymm2 
and ymm3/m256 for greater than, and set vector 
EVEX.512.66.0F.WIG 65 /r
VPCMPGTW k1 {k2}, zmm2, zmm3/m512D V/V AVX512BW Compare packed signed word integers in zmm2 
and zmm3/m512 for greate r than, and set vector 
NOTES:
D Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/AOpcode/
Mode 
Feature 
FlagDescriptionPCMPGTB/PCMPGTW/PCMPGTD—Compare Packed  Signed Integers for Greater ThanINSTRUCTION SET REFERENCE, M-U
4-260 Vol. 2BVEX.256 encoded version: The first source operand is a YM M register. The second source operand is a YMM register 
EVEX encoded VPCMPGTD: The first so urce operand (second operand) is a ZMM/YMM/XMM register. The second 
EVEX encoded VPCMPGTB/W: The first source operand (sec ond operand) is a ZMM/YMM/XMM register. The second 
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand 
(first operand) is a mask register updated according to the writemask k2.
Operation
PCMPGTB (With 64-bit Operands)
IF DEST[7:0] > SRC[7:0]
(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)IF DEST[63:56] > SRC[63:56]
COMPARE_BYTES_GREA TER (SRC1, SRC2)
IF SRC1[7:0] > SRC2[7:0]THEN DEST[7:0] := FFH;ELSE DEST[7:0] := 0; FI;

Operation
IF SRC1[127:120] > SRC2[127:120]THEN DEST[127:120] := FFH;ELSE DEST[127:120] := 0; FI;
COMPARE_WORDS_GREATER (SRC1, SRC2)
IF SRC1[15:0] > SRC2[15:0]THEN DEST[15:0] := FFFFH;ELSE DEST[15:0] := 0; FI;
IF SRC1[127:112] > SRC2[127:112]THEN DEST[127:112] := FFFFH;ELSE DEST[127:112] := 0; FI;
COMPARE_DWORDS_GREAT ER (SRC1, SRC2)
IF SRC1[31:0] > SRC2[31:0]THEN DEST[31:0] := FFFFFFFFH;ELSE DEST[31:0] := 0; FI;
IF SRC1[127:96] > SRC2[127:96]THEN DEST[127:96] := FFFFFFFFH;ELSE DEST[127:96] := 0; FI;
PCMPGTB (With 128-bit Operands)
DEST[127:0] := COMPARE_BYTES_GREATER(DEST[127:0],SRC[127:0])DEST[MAXVL-1:128] (Unmodified)PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed  Signed Integers for Greater ThanINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-261VPCMPGTB (VEX.128 Encoded Version)
DEST[127:0] := COMPARE_BYTES_GREATER(SRC1,SRC2)DEST[MAXVL-1:128] := 0
VPCMPGTB (VEX.256 Encoded Version)
DEST[127:0] := COMPARE_BYTES_GR EATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] := COMPARE_BYTES_GREATER(SRC1[255:128],SRC2[255:128])DEST[MAXVL-1:256] := 0
VPCMPGTB (EVEX Encoded Versions)
THEN 
/* signed comparison */CMP := SRC1[i+7:i ] > SRC2[i+7:i];
FI;
PCMPGTW (With 64-bit Operands)
IF DEST[15:0] > SRC[15:0]
 
(* Continue comparison of 2nd an d 3rd words in DEST and SRC *)
IF DEST[63:48] > SRC[63:48]
PCMPGTW (With 128-bit Operands)
DEST[127:0] := COMPARE_WORDS_GR EATER(DEST[127:0],SRC[127:0])
VPCMPGTW (VEX.128 Encoded Version)
DEST[127:0] := COMPARE_WORDS_GREATER(SRC1,SRC2)DEST[MAXVL-1:128] := 0
VPCMPGTW (VEX.256 Encoded Version)
DEST[127:0] := COMPARE_WORDS_GR EATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] := COMPARE_WORDS_GRE ATER(SRC1[255:128],SRC2[255:128])
DEST[MAXVL-1:256] := 0PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed  Signed Integers for Greater ThanINSTRUCTION SET REFERENCE, M-U
4-262 Vol. 2BVPCMPGTW (EVEX Encoded Versions)
THEN 
/* signed comparison */CMP := SRC1[i+15:i] > SRC2[i+15:i];IF CMP = TRUE
FI;
PCMPGTD (With 64-bit Operands)
IF DEST[31:0] > SRC[31:0]
IF DEST[63:32] > SRC[63:32]
PCMPGTD (With 128-bit Operands)
DEST[127:0] := COMPARE_DWORDS_GREATER(DEST[127:0],SRC[127:0])DEST[MAXVL-1:128] (Unmodified)
VPCMPGTD (VEX.128 Encoded Version)
DEST[127:0] := COMPARE_DWORDS_GREATER(SRC1,SRC2)DEST[MAXVL-1:128] := 0
VPCMPGTD (VEX.256 Encoded Version)
DEST[127:0] := COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0])DEST[255:128] := COMPARE_DWORDS_GR EATER(SRC1[255:128],SRC2[255:128])
VPCMPGTD (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (8, 512)FOR j := 0 TO KL-1
THEN 
THEN CMP := SRC1[i+3 1:i] > SRC2[31:0];
ELSE CMP := SRC1[i+31:i] > SRC2[i+31:i];
FI;
ENDFORPCMPGTB/PCMPGTW/PCMPGTD—Compare Packed  Signed Integers for Greater ThanINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-263DEST[MAX_KL-1:KL] := 0
VPCMPGTB __mmask64 _mm512_cmpgt_epi8_mask(__m512i a, __m512i b);
VPCMPGTB __mmask64 _mm512_mask_cmpgt_epi8 _mask(__mmask64 k, __m512i a, __m512i b);
VPCMPGTB __mmask32 _mm256_cmpgt_epi8_mask(__m256i a, __m256i b);VPCMPGTB __mmask32 _mm256_mask_cmpgt_epi8 _mask(__mmask32 k, __m256i a, __m256i b);
VPCMPGTB __mmask16 _mm_cmpgt_ep i8_mask(__m128i a, __m128i b);
VPCMPGTB __mmask16 _mm_mask_cmpgt_epi8_ma sk(__mmask16 k, __m128i a, __m128i b);
VPCMPGTD __mmask16 _mm512_cmpgt_epi32_mask(__m512i a, __m512i b);VPCMPGTD __mmask16 _mm512_mask_cmpgt_epi32_ mask(__mmask16 k, __m512i a, __m512i b);
VPCMPGTD __mmask8 _mm256_cmpgt_epi32_mask(__m256i a, __m256i b);VPCMPGTD __mmask8 _mm256_mask_cmpgt_epi32_mask(__mmask8 k, __m256i a, __m256i b);VPCMPGTD __mmask8 _mm_cmpgt_epi32_mask(__m128i a, __m128i b);VPCMPGTD __mmask8 _mm_mask _cmpgt_epi32_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPGTW __mmask32 _mm512_cmpgt_epi16_mask(__m512i a, __m512i b);VPCMPGTW __mmask32 _mm512_mask_cmpgt_epi16_ mask(__mmask32 k, __m512i a, __m512i b);
VPCMPGTW __mmask16 _mm256_cmpgt_epi16_mask(__m256i a, __m256i b);VPCMPGTW __mmask16 _mm256_mask_cmpgt_epi16_ mask(__mmask16 k, __m256i a, __m256i b);
VPCMPGTW __mmask8 _mm_cmpgt_epi16_mask(__m128i a, __m128i b);VPCMPGTW __mmask8 _mm_mask_cmpgt_epi16_mask(__mmask8 k, __m128i a, __m128i b);PCMPGTB __m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)PCMPGTW __m64 _mm_cmpgt_pi16 (__m64 m1, __m64 m2)PCMPGTD __m64 _mm_cmpgt_pi32 (__m64 m1, __m64 m2)(V)PCMPGTB __m128i _mm_cmpgt_epi8 ( __m128i a, __m128i b)(V)PCMPGTW __m128i _mm_cmpgt_epi16 ( __m128i a, __m128i b)(V)DCMPGTD __m128i _mm_cmpgt_e pi32 ( __m128i a, __m128i b)
VPCMPGTB __m256i _mm256_cmpgt_epi8 ( __m256i a, __m256i b)VPCMPGTW __m256i _mm256_cmpgt_epi16 ( __m256i a, __m256i b)VPCMPGTD __m256i _mm256_cmpgt_epi32 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded VPCMPGTD, see Table 2-49, “Type E4 Class Exception Conditions.”EVEX-encoded VPCMPGTB/W, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PCMPGTQ—Compare Packed Data for Greater ThanINSTRUCTION SET REFERENCE, M-U
4-264 Vol. 2BPCMPGTQ—Compare Packed Data for Greater Than
Performs an SIMD signed compare for the packed quadwo rds in the destination operand (first operand) and the 
source operand (second operand). If the data element in  the first (destination) operand is greater than the 
corresponding element in the second (source) operand, th e corresponding data element in the destination is set 
to all 1s; otherwise, it is set to 0s.
destination register remain unchanged.
register are zeroed.
EVEX encoded VPCMPGTD/Q: The first source operand (sec ond operand) is a ZMM/YMM/XMM register. The second 
Mode 
Feature 
66 0F 38 37 /r
PCMPGTQ xmm1,xmm2/m128A V/V SSE4_2 Compare packed signed qwords in xmm2/m128 
and xmm1 for greater than.
VEX.128.66.0F38.WIG 37 /r
VPCMPGTQ xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed qwords in xmm2 and 
xmm3/m128 for greater than.
VEX.256.66.0F38.WIG 37 /r
VPCMPGTQ ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed qwords in ymm2 and 
ymm3/m256 for greater than.
EVEX.128.66.0F38.W1 37 /r
VPCMPGTQ k1 {k2}, xmm2, 
AVX512FCompare Greater between int64 vector xmm2 and 
int64 vector xmm3/m128/m64bcst, and set 
vector mask k1 to reflect the zero/nonzero status 
EVEX.256.66.0F38.W1 37 /r
VPCMPGTQ k1 {k2}, ymm2, 
AVX512FCompare Greater between int64 vector ymm2 and 
int64 vector ymm3/m256/m64bcst, and set 
vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.
EVEX.512.66.0F38.W1 37 /r
VPCMPGTQ k1 {k2}, zmm2, zmm3/m512/m64bcstC V/V AVX512F Compare Greater betw een int64 vector zmm2 and 
int64 vector zmm3/m512/m64bcst, and set 

C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APCMPGTQ—Compare Packed Data for Greater ThanINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-265Operation
COMPARE_QWORDS_GREAT ER (SRC1, SRC2)
IF SRC1[63:0] > SRC2[63:0]THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;ELSE DEST[63:0] := 0; FI;IF SRC1[127:64] > SRC2[127:64]THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;ELSE DEST[127:64] := 0; FI;
VPCMPGTQ (VEX.128 Encoded Version)
DEST[127:0] := COMPARE_QW ORDS_GREATER(SRC1,SRC2)
VPCMPGTQ (VEX.256 Encoded Version)
DEST[127:0] := COMPARE_QWORDS_G REATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] := COMPARE_QWORDS_GR EATER(SRC1[255:128 ],SRC2[255:128])
VPCMPGTQ (EVEX Encoded Versions)
THEN 
THEN CMP := SRC1[i+63:i] > SRC2[63:0];ELSE CMP := SRC1[i+63:i] > SRC2[i+63:i];
FI;
VPCMPGTQ __mmask8 _mm512_cmpgt_epi64_mask( __m512i a, __m512i b);VPCMPGTQ __mmask8 _mm512_mask_cmpgt_epi64_ mask(__mmask8 k, __m512i a, __m512i b);
VPCMPGTQ __mmask8 _mm256_cmpgt_epi64_mask( __m256i a, __m256i b);VPCMPGTQ __mmask8 _mm256_mask_cmpgt_epi64_ mask(__mmask8 k, __m256i a, __m256i b);
VPCMPGTQ __mmask8 _mm_cmpgt_epi64 _mask( __m128i a, __m128i b);
VPCMPGTQ __mmask8 _mm_mask_cmpgt_epi64_mas k(__mmask8 k, __m128i a, __m128i b);
(V)PCMPGTQ __m128i _mm_cmpgt_epi64(__m128i a, __m128i b)VPCMPGTQ __m256i _mm256_cmpgt_epi64( __m256i a, __m256i b);
None.
None.PCMPGTQ—Compare Packed Data for Greater ThanINSTRUCTION SET REFERENCE, M-U
4-266 Vol. 2BOther Exceptions
EVEX-encoded VPCMPGTQ, see Table 2-49, “Type E4 Class Exception Conditions.”PCMPISTRI—Packed Compare Implicit  Length Strings, Return Index INSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-267PCMPISTRI—Packed Compare Implicit Length Strings, Return Index 
The instruction compares data from two strings based on the encoded value in the imm8 control byte (see Section 
4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and generates an 
index stored to ECX.
Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which 
contains the data elements of the string (byte or wo rd data). Each input byte/word is augmented with a 
valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null 
byte/word. (The least significant null by te/word is also considered invalid.) 
The comparison and aggregation operatio ns are performed according to the encoded value of imm8 bit fields (see 
Section 4.1). The index of the first (or last, according to i mm8[6]) set bit of IntRes2 is returned in ECX. If no bits 
are set in IntRes2, ECX is set to 16 (8).
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-
tion:
ZFlag – Set if any byte/word of xmm2/mem128 is null, reset otherwiseSFlag – Set if any by te/word of xmm1 is null, reset otherwise
Note: In VEX.128 encoded version, VEX.vvvv is reserved  and must be 1111b, VEX.L must be 0, otherwise the 
instruction will #UD.
Effective Operand Size
Intel C/C++ Compiler Intrinsic Equivalent For Returning Index
int _mm_cmpistri (__m128i a, __m128i b, const int mode);Opcode/
Mode 
Feature 
66 0F 3A 63 /r imm8
PCMPISTRI xmm1, xmm2/m128, imm8RM V/V SSE4_2 Perform a packed comparison of string data 
with implicit lengths, ge nerating an index, and 
storing the result in ECX.
VEX.128.66.0F3A.WIG 63 /r ib
VPCMPISTRI xmm1, xmm2/m128, imm8RM V/V AVX Perform a packed comparison of string data 
RM ModRM:reg (r) ModRM:r/m (r) imm8 N/A
Operating mode/s ize Operand 1 Operand 2 Result
16 bit xmm xmm/m128 ECX
32 bit xmm xmm/m128 ECX
64 bit xmm xmm/m128 ECXPCMPISTRI—Packed Compare Implicit  Length Strings, Return Index INSTRUCTION SET REFERENCE, M-U
4-268 Vol. 2BIntel C/C++ Compiler Intrinsi cs For Reading EFlag Results
int _mm_cmpistra (__m128i a, __m128i b, const int mode);
int _mm_cmpistrc (__m128i a, __m128i b, const int mode);int _mm_cmpistro (__m128i a,  __m128i b, const int mode);
int _mm_cmpistrs (__m128i a, __m128i b, const int mode);int _mm_cmpistrz (__m128i a, __m128i b, const int mode);
None.
If VEX.vvvv ≠ 1111B.PCMPISTRM—Packed Compare Implicit  Length Strings, Return MaskINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-269PCMPISTRM—Packed Compare Implicit  Length Strings, Return Mask
The instruction compares data from two strings based on  the encoded value in the imm8 byte (see Section 4.1, 
“Imm8 Control Byte Operation for PCMPESTRI / PCMPES TRM / PCMPISTRI / PCMPISTR M”) generating a mask 
stored to XMM0.
The comparison and aggregation operation are performed a ccording to the encoded value of imm8 bit fields (see 
tion:
1111b, VEX.L must be 0, otherwise the instruction will #UD.
__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode);Opcode/
Mode 
Feature 
66 0F 3A 62 /r imm8
PCMPISTRM xmm1, xmm2/m128, imm8RM V/V SSE4_2 Perform a packed comparison of string data 
with implicit lengths, generating a mask, and 
storing the result in XMM0.
VEX.128.66.0F3A.WIG 62 /r ib
VPCMPISTRM xmm1, xmm2/m128, imm8RM V/V AVX Perform a packed co mparison of string data 
with implicit lengths, generating a Mask, and storing the result in XMM0.
Operating mode/size Operand 1 Operand 2 Result
16 bit xmm xmm/m128 XMM032 bit xmm xmm/m128 XMM064 bit xmm xmm/m128 XMM0PCMPISTRM—Packed Compare Implicit Length Strings, Return MaskINSTRUCTION SET REFERENCE, M-U
4-270 Vol. 2BIntel C/C++ Compiler Intrinsi cs For Reading EFlag Results
None.
If VEX.vvvv ≠ 1111B.PCONFIG—Platform ConfigurationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-271PCONFIG—Platform Configuration
The PCONFIG instruction allows software to configure cert ain platform features. It supports these features with 
multiple leaf functions, selecting a leaf function using the value in EAX.
Depending on the leaf function, the registers RBX, RCX, and RDX may be used to provide input information or for 
the instruction to report output information. Addresses an d operands are 32 bits outside 64-bit mode and are 64 
bits in 64-bit mode. The value of CS.D does  not affect operand size or address size.

None.
Executions of PCONFIG may fail for platform-specific reasons. An execution reports failure by setting the ZF flag 
and loading EAX with a non-zero failure reason; a successful execution clears ZF and EAX.
Each PCONFIG leaf function applies to a specific hardwa re block called a PCONFIG target. The leaf function is 
supported only if the processor supports that target. Each target is associated with a numerical target identifier, 
and CPUID leaf 1BH (PCONFIG information) enumerates the identifiers of the supported targets. An attempt to 
execute an undefined leaf function, or a leaf function that  applies to an unsupported target identifier, results in a 
general-protection exception (#GP).
Leaf Function MKTME_KEY_PROGRAM
As of this writing, the only defined PCONFIG leaf functi on is used for key programming for total memory encryp-
tion-multi-key (TME-MK).1 This leaf function is called MKTME_KEY_PROGRAM and it pertains to the TME-MK target, 
which has target identifier 1. The leaf function is sele cted by loading EAX with value 0. The MKTME_KEY_PROGRAM 
leaf function uses the EBX (or RBX) register for additional input information.
Software uses the MKTME_KEY_PROGRAM leaf function to ma nage the encryption key associated with a particular 
key identifier (KeyID). The leaf function uses a data structure called the TME-MK key programming structure  
(MKTME_KEY_PROGRAM_STRUCT). Software provides the ad dress of the structure (as an offset in the DS 
segment) in EBX (or RBX). The format of  the structure is given in Table 4-15.Opcode/
Mode 
NP 0F 01 C5
PCONFIG A V/V PCONFIG This instruction is used to execute functions for 
configuring platform features.
A N/A N/A N/A N/A N/A
1. Further details on TME-MK can be found here:
https://software.intel.com /sites/default/files/manag ed/a5/16/Multi-Key-Total-Memory-Encryption-Spec.pdf  Table 4-15.  MKTME_KEY_PROGRAM_STRUCT Format
Field Offset (bytes) Size (bytes) Comments
KEYID 0 2 Key Identifier.
KEYID_CTRL 2 4 KeyID control:
• Bits 7:0: key-programming command (COMMAND)
•B i t s  2 3 : 8 :  e n c r y p t i o n  algorithm (ENC_ALG)
• Bits 31:24: Reserved, must be zero (RSVD)
Ignored 6 58 Not used.
KEY_FIELD_1 64 64 Software supplied da ta key or entropy for data key.
KEY_FIELD_2 128 64 Software supplied tw eak key or entropy for tweak key.PCONFIG—Platform ConfigurationINSTRUCTION SET REFERENCE, M-U
4-272 Vol. 2BA description of each of the fields in MK TME_KEY_PROGRAM_STRUCT  is provided below:
•KEYID: The key identifier (KeyID) being programmed to the MKTME engine. PCONFIG causes a general-
protection exception (#GP) if the KeyID is zero. KeyID zero always uses the current behavior configured for 
TME (total memory encryption), either to encrypt with platform TME key or to bypa ss TME encryption. PCONFIG 
also causes a #GP if the KeyID exceeds the maximu m enumerated in IA32_TME_CAPABILITY.MK_TME_MAX-
_KEYS[bits 50:36] or configured by the setting of IA32_TME_ACTIVATE.MK_TME_KEYID_BITS[bits 35:32].
•KEYID_CTRL: The KEYID_CTRL field comprises two sub-fields used by software to control the encryption 
performed for the selected KeyID:
— Key-programming command (COMMAND; bits 7:0). This 8-bit field should contain one of the following 
values:
•KEYID_SET_KEY_DIRECT (value 0). With this command , software programs directly the encryption key 
to be used for the selected KeyID.
•KEYID_SET_KEY_RANDOM (value 1). With this command , software has the CPU generate and assign an 
encryption key to be used for the selected KeyID using a hardware random-number generator.
If this command is used and there is insufficient  entropy for the random-number generator, PCONFIG 
will fail and report the failure by lo ading EAX with value 2 (ENTROPY_ERROR).
Because the keys programed by PCONFIG are disca rded on reset and software cannot read the 
programmed keys, the keys programmed with this command are ephemeral.
•KEYID_CLEAR_KEY (value 2). With this command, soft ware indicates that the selected KeyID should 
use the current behavior configured for TME (see above).
•KEYID_NO_ENCRYPT (value 3). With this command, so ftware indicates that no encryption should be 
used for the selected KeyID.
If any other value is used, PCONFIG causes a #GP.
— Encryption algorithm (ENC_ALG, bits 23:8). Bits 63: 48 of the IA32_TME_ACTIVATE MSR (MSR index 982H) 
indicate which encryption algorithms are supporte d by the platform. The 16-bit ENC_ALG field should 
specify one of the algorithms indicated in IA32_TME _ACTIVATE. PCONFIG causes a #GP if ENC_ALG does 
not set exactly one bit or if it sets a bit whose co rresponding bit is not set in IA32_TME_ACTIVATE[63:48].
•KEY_FIELD_1:  Use of this field depends upon selected key-programming command:
— If the direct key-programming command is used (KEY ID_SET_KEY_DIRECT), this field carries the software 
supplied data key to be used for the KeyID.
— If the random key-programming command is used (KEYID_SET_KEY_RANDOM), this field carries the 
software supplied entropy to be mixed in the CPU generated random data key.
— This field is ignored when one of the other key-programming commands is used.
It is software’s responsibility to ensure that the ke y supplied for the direct key-programming option or the
entropy supplied for the random key-programming option does not result in weak keys. There are no explicit
checks in the instruction to detect or prevent weak keys.
•KEY_FIELD_2:  Use of this field depends upon selected key-programming command:
supplied tweak key to be used for the KeyID.
software supplied entropy to be mixed in the CPU generated random tweak key.
All KeyIDs default to TME behavior (encrypt with TME key or bypass encryption) on activation of TME-MK. Software 
can at any point decide to change the key for a KeyI D using the MKTME_KEY_PROGRAM leaf function of the 
PCONFIG instruction. Changing the key for a KeyID does not change the state of the TLB caches or memory pipe-
line. Software is responsible for taking appropriate actions to ensure correct behavior.PCONFIG—Platform ConfigurationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-273The key table used by TME-MK is shared by all logical pr ocessors in a platform. For this reason, execution of the 
MKTME_KEY_PROGRAM leaf function must gain exclusive acce ss to the key table before updating it. The leaf func-
tion does this by acquiring lock (implemented in th e platform) and retaining that lock until the execution 
completes. An execution of the leaf function may fail to acquir e the lock if it is already in use. In this situation, the 
leaf function will load EAX with failure reason 5 (DEVIC E_BUSY) indicating that software must retry. When this 
happens, the key table is not updated, and so ftware should retry execution of PCONFIG.
NOTES
Earlier versions of this manual specified that  bytes 63:6 of MKTME_KEY_PROGRAM_STRUCT were 
reserved and that PCONFIG would cause a #GP if they were not all zero. This is not the case. As 
indicated in Table 4-15, PCONFIG ignores those bytes.
They also specified that PCONFI G would cause a #GP if the upper 48 bytes of each of the 64-byte 
key fields were not all 0. This is not the case. From each of these fields, PCONFIG uses the number 
of bytes required by the selected encryption algorithm (e.g., 32 bytes for AES-XTS 256) and 
ignores the upper bytes.
They also specified that PCONFIG would complete an d report a failure reason in EAX if the structure 
specified an incorrect KeyID, and unsupported  key-programming command, or an incorrect 
selection of an encryption algorithm. This is not the case. As indicated above (and in the Operation 
section), those conditions cause #GP.
Operation
(* #UD if PCONFIG is not enumerated or CPL > 0 *)
IF CPUID.7.0:EDX[18] = 0 OR CPL > 0
(* #GP(0) for an unsupported leaf function *)
IF EAX != 0
CASE (EAX) (* operation based on  selected leaf function *)
0 (MKTME_KEY_PROGRAM):(* Confirm that TME-MK is properly enabled by the IA32_TME_ACTIVATE MSR *)
(* The MSR must be locked, encryp tion enabled, and a non-zero number of KeyID bits specified *)
IF IA32_TME_ACTIVATE[0] = 0 OR IA32_TME_ACT IVATE[1] = 0 OR IA32_TME_ACTIVATE[35:32] = 0
IF DS:RBX is not 256-byte aligned
Load TMP_KEY_PROGRAM_STRUCT from 192 bytes at linear address DS:RBX;IF TMP_KEY_PROGRAM_STR UCT.KEYID_CTRL sets  any reserved bits

Operation
IF EAX != 0
(* Check for a valid command *)
IF TMP_KEY_PROGRAM_STRUCT.  KEYID_CTRL.COMMAND > 3
(* Check that the KEYID being operated upon is a valid KEYID *)
IF TMP_KEY_PROGRAM_S TRUCT.KEYID = 0 OR
TMP_KEY_PROGRAM_STRUCT.KEY ID > 2^IA32_TME_ACTIVATE.MK_TME_KEYID_BITS – 1 OR
TMP_KEY_PROGRAM_STRUCT.KEYID > IA 32_TME_CAPABILITY.MK_TME_MAX_KEYS 
THEN #GP(0); FI;PCONFIG—Platform ConfigurationINSTRUCTION SET REFERENCE, M-U
4-274 Vol. 2B(* Check that only one encryption algo rithm is requested fo r the KeyID and it is one of  the activated algorithms *)
IF TMP_KEY_PROGRAM_ STRUCT.KEYID_CTRL.ENC_ALG does not set exactly one bit OR
(TMP_KEY_PROGRAM_STRUCT.KEYID_CTRL.ENC_ALG & IA32_TME_ACTIVATE[63:48]) = 0
THEN #GP(0); FI:
Attempt to acquire lock to gain exclusive access  to platform key table;
IF attempt is unsuccessful
THEN (* PCONFIG failure *)
RFLAGS.ZF := 1;RAX := DEVICE_BUSY; (*  failure reason 5 *)
GOTO EXIT;
FI;
CASE (TMP_KEY_PROGRAM_STRUCT.KEYID_CTRL.COMMAND) OF
0 (KEYID_SET_KEY_DIRECT):Update TME-MK table for TMP_KEY_ PROGRAM_STRUCT.KEYID as follows:
Encrypt with the selected keyUse the encryption algorithm selected by TMP_KEY_PROGRAM_STRUCT.KEYID_CTRL.ENC_ALG(* The number of bytes used by  the next two lines depends on selected encryption algorithm *)
DATA_KEY is TMP_KEY_PROGRAM_STRUCT.KEY_FIELD_1TWEAK_KEY is TMP_KEY_PR OGRAM_STRUCT.KEY_FIELD_2
BREAK;
1 (KEYID_SET_K EY_RANDOM):
Load TMP_RND_DATA_KEY with a random key using hardware RNG;  (* key size depends on sele cted encryption algorithm *)
IF there was insufficient entropy
RFLAGS.ZF := 1;RAX := ENTROPY_ERROR; (* failure reason 2 *)Release lock on pl atform key table;
GOTO EXIT;
FI;Load TMP_RND_TWEAK_KEY with a random ke y using hardware RNG; (* key size depends on selected encryption algorithm *)
GOTO EXIT;
FI;(* Combine software-supplied entrop y to the data key and tweak key *)
(* The number of bytes used by  the next two lines depends on selected encryption algorithm *)
TMP_RND_DATA_KEY := TMP_RND_KEY XOR TMP_KEY_PROGRAM_STRUCT.KEY_FIELD_1;TMP_RND_TWEAK_KEY := TMP_RND_TWEAK_KEY XOR TMP_KEY_PROGRAM_ STRUCT.KEY_FIELD_2;
Update TME-MK table for TMP_KEY_ PROGRAM_STRUCT.KEYID as follows:
DATA_KEY is TMP_RND_DATA_KEYTWEAK_KEY is TMP_RND_TWEAK_KEY
BREAK;
2 (KEYID_CLEAR_KEY):PCONFIG—Platform ConfigurationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-275Update TME-MK table for TMP_KEY_ PROGRAM_STRUCT.KEYID as follows:
Encrypt (or not) using the current configuration for TMEThe specified encryption algorithm and key values are not used.
BREAK;
3 (KEYID_NO_ENCRYPT):
Do not encryptThe specified encryption algorithm and key values are not used.
BREAK;
ESAC;Release lock on pl atform key table;
ESAC;
RAX := 0;
RFLAGS.ZF := 0;
EXIT:
RFLAGS.CF := 0;RFLAGS.PF := 0;RFLAGS.AF := 0;RFLAGS.OF := 0;RFLAGS.SF := 0;
#GP(0) If input value in EAX enco des an unsupported leaf function.
If a memory operand effective address is outside the relevant segment limit.MKTME_KEY_PROGRAM leaf function:
If IA32_TME_ACTIVATE MSR is not locked.
If hardware encryption and TME-MK capabilit y are not enabled in IA32_TME_ACTIVATE MSR.
If the memory operand is not 256B aligned.
If any of the reserved bits in the KEYID_CT RL field of the MKTME_KEY_PROGRAM_STRUCT are 
set or that field indicates an unsupported Ke yID, key-programming command, or encryption 
#PF(fault-code) If a page fault occurs in accessing memory operands.
#UD If any of the LOCK/REP/Opera nd Size/VEX prefixes are used.
If CPUID.7.0:EDX[bit 18] = 0
#GP If input value in EAX encode s an unsupported leaf function.
MKTME_KEY_PROGRAM leaf function:
If IA32_TME_ACTIVATE MSR is not locked.If hardware encryption and TME-MK capabilit y are not enabled in IA32_TME_ACTIVATE MSR.
If a memory operand is not 256B aligned.
If CPUID.7.0:EDX.PCONFIG[bit 18] = 0PCONFIG—Platform ConfigurationINSTRUCTION SET REFERENCE, M-U
4-276 Vol. 2BVirtual-8086 Mode Exceptions
#UD PCONFIG instruction is not recognized in virtual-8086 mode.
#GP(0) If input value in EAX encode s an unsupported leaf function.
If a memory operand is non-canonical form.
MKTME_KEY_PROGRAM leaf function:If IA32_TME_ACTIVATE MSR is not locked.
If a memory operand is not 256B aligned.If any of the reserved bits in the KEYID_CT RL field of the MKTME_KEY_PROGRAM_STRUCT are 
#UD If any of the LOCK/REP/Operand  Size/VEX prefixes are used.
If CPUID.7.0:EDX.PCONFIG[bit 18] = 0.PDEP—Parallel Bits DepositINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-277PDEP—Parallel Bits Deposit
PDEP uses a mask in the second source operand (the thir d operand) to transfer/scatter contiguous low order bits 
in the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits from the first source operand and deposit them in the de stination operand at the corresponding bit locations that 
are set in the second source operand (mask). All other bits  (bits not set in mask) in destination are set to zero.
Figure 4-8.  PDEP Example
Operation
TEMP := SRC1;
MASK := SRC2;DEST := 0 ;m := 0, k := 0;DO WHILE m < OperandSize
IF MASK[ m] = 1 THEN
DEST[ m] := TEMP[ k];
    k := k+ 1;FIm := m+ 1;
ODOpcode/
En64/32-
VEX.LZ.F2.0F38.W0 F5 /r
PDEP r32a, r32b, r/m32RVM V/V BMI2 Parallel deposit of bits from r32b using mask in r/m32, result is written 
to r32a.
VEX.LZ.F2.0F38.W1 F5 /r
PDEP r64a, r64b, r/m64RVM V/N.E. BMI2 Parallel deposit of bits from r64b using mask in r/m64, result is written 
to r64a.
001001 01 0100 0
00 00 0 0 0 00 DESTSRC1
SRC2
(mask)S31S30S29S28S27 S7S6S5 S3 S4 S2S1S0
S0S1 S2S3
bit 0 bit 31PDEP—Parallel Bits DepositINSTRUCTION SET REFERENCE, M-U
4-278 Vol. 2BFlags Affected
None.
PDEP unsigned __int32 _pdep_u32(unsigned __int32 src, unsigned __int32 mask);
PDEP unsigned __int64 _pdep_u64(unsigned __int64 src, unsigned __int32 mask);
None.
See Table 2-29, “Type 13 Class Exception Conditions.”PEXT—Parallel Bits ExtractINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-279PEXT—Parallel Bits Extract
PEXT uses a mask in the second source operand (the thir d operand) to transfer either contiguous or non-contig-
uous bits in the first source operand (the second operand)  to contiguous low order bit positions in the destination 
(the first operand). For each bit set in the MASK, PEXT extr acts the corresponding bits from the first source operand 
and writes them into contiguous lower bits of destinat ion operand. The remaining upper bits of destination are 
zeroed.
Figure 4-9.  PEXT Example
attempt to execute this instruction with  VEX.L not equal to 0 will cause #UD.Opcode/
En64/32-
VEX.LZ.F3.0F38.W0 F5 /r
PEXT r32a, r32b, r/m32RVM V/V BMI2 Parallel extract of bi ts from r32b using mask in r/m32, result is written 
to r32a.
VEX.LZ.F3.0F38.W1 F5 /r
PEXT r64a, r64b, r/m64RVM V/N.E. BMI2 Parallel extract of  bits from r64b using mask in r/m64, result is written 
to r64a.

zeroed.
En64/32-
to r32a.
to r64a.
DESTSRC1
SRC2
001 01 01 0100 0
S2 S5 S7 00 00 0000 00
S28
bit 0 bit 31PEXT—Parallel Bits ExtractINSTRUCTION SET REFERENCE, M-U
4-280 Vol. 2BOperation
DEST[ k] := TEMP[ m];
OD
None.
PEXT unsigned __int32 _pext_u32(unsigned __int32 src, unsigned __int32 mask);
PEXT unsigned __int64 _pext_u64(unsigned __int64 src, unsigned __int32 mask);
None.
See Table 2-29, “Type 13 Class Exception Conditions.”PEXTRB/PEXTRD/PEXTRQ—Extract Byte/Dword/QwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-281PEXTRB/PEXTRD/PEXTRQ—Extract Byte/Dword/Qword
Extract a byte/dword/qword integer value from the source XMM register at a byte/dword /qword offset determined 
from imm8[3:0]. The destination can be  a register or byte/dword/qword memory location. If the destination is a 
register, the upper bits of the register are zero extended.
In legacy non-VEX encoded vers ion and if the destination operand is a register, the default operand size in 64-bit 
mode for PEXTRB/PEXTRD is 64 bits, the bits above the le ast significant byte/dword data are filled with zeros. 
PEXTRQ is not encodable in non-64-bit mo des and requires REX.W in 64-bit mode.
Note: In VEX.128 encoded versions, VEX.vvvv is reserved  and must be 1111b, VEX.L must be 0, otherwise the 
instruction will #UD. In EVEX.128 encoded versions, EVEX.v vvv is reserved and must be 1111b, EVEX.L”L must be 
0, otherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit 
mode for VPEXTRB/VPEXTRD is 64 bits, the bits above th e least significant byte/word/dword data are filled with 
zeros. Opcode/
Mode 
Feature 
66 0F 3A 14 /r ib
PEXTRB reg/m8, xmm2, imm8A V/V SSE4_1 Extract a byte inte ger value from xmm2 at the 
source byte offset specif ied by imm8 into reg or 
m8. The upper bits of r32 or r64 are zeroed.
66 0F 3A 16 /r ib
PEXTRD r/m32, xmm2, imm8A V/V SSE4_1 Extract a dword inte ger value from xmm2 at the 
source dword offset specified by imm8 into r/m32.
66 REX.W 0F 3A 16 /r ib
PEXTRQ r/m64, xmm2, imm8A V/N.E. SSE4_1 Extract a qword integer value from xmm2 at the 
source qword offset specified by imm8 into r/m64.
VEX.128.66.0F3A.W0 14 /r ib
VPEXTRB reg/m8, xmm2, imm8AV1/V
NOTES:
1. In 64-bit mode, VEX.W1 is ignored for VPEXTRB (similar to legacy REX.W=1 prefix in PEXTRB).AVX Extract a byte integer value from xmm2 at the 
m8. The upper bits of r64/r32 is filled with zeros.
VEX.128.66.0F3A.W0 16 /r ib
VPEXTRD r32/m32, xmm2, imm8A V/V AVX Extract a dword integer value from xmm2 at the 
source dword offset specified by imm8 into 
r32/m32.
VEX.128.66.0F3A.W1 16 /r ib
VPEXTRQ r64/m64, xmm2, imm8AV / I2
2. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVX Extract a qword integer value from xmm2 at the 
r64/m64.
EVEX.128.66.0F3A.WIG 14 /r ib
VPEXTRB reg/m8, xmm2, imm8B V/V AVX512BW Extract a byte inte ger value from xmm2 at the 
EVEX.128.66.0F3A.W0 16 /r ib
VPEXTRD r32/m32, xmm2, imm8B V/V AVX512DQ Extract a dword integer value from xmm2 at the 
r32/m32.
EVEX.128.66.0F3A.W1 16 /r ib
VPEXTRQ r64/m64, xmm2, imm8BV / N . E .2AVX512DQ Extract a qword integer value from xmm2 at the 
r64/m64.
B Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) imm8 N/APEXTRB/PEXTRD/PEXTRQ—Extract Byte/Dword/QwordINSTRUCTION SET REFERENCE, M-U
4-282 Vol. 2BOperation
CASE of
PEXTRB: SEL := COUNT[3:0];
TEMP := (Src >> SEL*8) AND FFH;IF (DEST = Mem8)
THENMem8 := TEMP[7:0];
ELSE IF (64-Bit Mode and 64-bit register selected)
THEN
R64[7:0] := TEMP[7:0];
r64[63:8] := ZERO_FILL; };
ELSE
R32[7:0] := TEMP[7:0];
r32[31:8] := ZERO_FILL; };
FI;
PEXTRD:SEL := COUNT[1:0];
TEMP := (Src >> SEL*32) AND FFFF_FFFFH;DEST := TEMP;
PEXTRQ: SEL := COUNT[0];
TEMP := (Src >> SEL*64);DEST := TEMP;
EASC:
VPEXTRTD/VPEXTRQ
IF (64-Bit Mode and 64-bit dest operand)THEN
Src_Offset := imm8[0]r64/m64 := (Src >> Src_Offset * 64)
ELSE
Src_Offset := imm8[1:0]r32/m32 := ((Src >> Src_Offset *32) AND 0FFFFFFFFh);
FI
VPEXTRB ( dest=m8)
SRC_Offset := imm8[3:0]Mem8 := (Src >> Src_Offset*8)
VPEXTRB ( dest=reg)
IF (64-Bit Mode )THEN
SRC_Offset := imm8[3:0] DEST[7:0] := ((Src >> Src_Offset*8) AND 0FFh)DEST[63:8] := ZERO_FILL;
ELSE
SRC_Offset := imm8[3:0];DEST[7:0] := ((Src >> Src_Offset*8) AND 0FFh);DEST[31:8] := ZERO_FILL;
FI
PEXTRB int _mm_extract_epi8 (__m128i src, const int ndx);PEXTRD int _mm_extract_epi32 ( __m128i src, const int ndx);
PEXTRQ __int64 _mm_extract_epi64 (__m128i src, const int ndx);PEXTRB/PEXTRD/PEXTRQ—Extract Byte/Dword/QwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-283Flags Affected
None.
None.
#UD If VEX.L = 1 or EVEX.L’L > 0.
If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.PEXTRW—Extract WordINSTRUCTION SET REFERENCE, M-U
4-284 Vol. 2BPEXTRW—Extract Word
Copies the word in the source operand (second operand) specified by the count operand (third operand) to the 
destination operand (first operand). The source operand can be an MMX technology register or an XMM register. 
The destination operand can be the low word of a general- purpose register or a 16-bit memory address. The count 
operand is an 8-bit immediate. When specifying a word lo cation in an MMX technology register, the 2 least-signifi-
cant bits of the count operand specify the location; for an XMM register, the 3 least-significant bits specify the loca-
tion. The content of the destination register above bit 16 is cleared (set to all 0s).
(XMM8-XMM15, R8-15). If the destination operand is a gene ral-purpose register, the default operand size is 64-bits 
in 64-bit mode. Opcode/
Mode 
NP 0F C5 /r ib1
PEXTRW reg, mm, imm8 
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SS E Instruction Exception Clas sification,” in the Intel® 64 and IA-32 Architectures Soft-
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSE Extract the word specified by imm8 from mm and 
move it to reg, bits 15-0 . The upper bits of r32 or 
r64 is zeroed.
66 0F C5 /r ib
PEXTRW reg, xmm, imm8 A V/V SSE2 Extract the word specified by imm8 from xmm 
and move it to reg, bits 15-0. The upper bits of r32 or r64 is zeroed.
66 0F 3A 15 /r ib
PEXTRW reg/m16, xmm, imm8B V/V SSE4_1 Extract the word specified by imm8 from xmm 
and copy it to lowest 16 bits of reg or m16. Zero-
extend the result in the destination, r32 or r64.
VEX.128.66.0F.W0 C5 /r ib
VPEXTRW reg, xmm1, imm8AV
2/V
2. In 64-bit mode, VEX.W1 is ig nored for VPEXTRW (similar to legacy REX.W=1 prefix in PEXTRW).AVX Extract the word specif ied by imm8 from xmm1 
and move it to reg, bits 15:0. Zero-extend the 
result. The upper bits of r64/r32 is filled with 
zeros.
VEX.128.66.0F3A.W0 15 /r ib
VPEXTRW reg/m16, xmm2, imm8B V/V AVX Extract a word integer value from xmm2 at the 
source word offset specified by imm8 into reg or 
m16. The upper bits of r64/r32 is filled with zeros.
EVEX.128.66.0F.WIG C5 /r ib
VPEXTRW reg, xmm1, imm8A V/V AVX512BW Extract the word specified by imm8 from xmm1 
zeros.
EVEX.128.66.0F3A.WIG 15 /r ib
VPEXTRW reg/m16, xmm2, imm8C V/V AVX512BW Extract a word inte ger value from xmm2 at the 
A N/A ModRM:reg (w) ModRM:r/m (r) imm8 N/A
B N/A ModRM:r/m (w) ModRM:reg (r) imm8 N/A
C Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) imm8 N/APEXTRW—Extract WordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-285Note: In VEX.128 encoded versions, VEX.vvvv is reserved  and must be 1111b, VEX.L must be 0, otherwise the

zeros.
Vol. 2B 4-285Note: In VEX.128 encoded versions, VEX.vvvv is reserved  and must be 1111b, VEX.L must be 0, otherwise the 
instruction will #UD. In EVEX.128 enco ded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L must be 0, 
otherwise the instruction will #UD. If th e destination operand is a register, th e default operand size in 64-bit mode 
for VPEXTRW is 64 bits, the bits above the least sign ificant byte/word/dword data are filled with zeros.
Operation
IF (DEST = Mem16)
THEN
SEL := COUNT[2:0];TEMP := (Src >> SEL*16) AND FFFFH;
Mem16 := TEMP[15:0];
ELSE IF (64-Bit Mode and destination is a general-purpose register)
THEN
FOR (PEXTRW instruction with 64-bit source operand)
{ SEL := COUNT[1:0];
TEMP := (SRC >> (SEL 
∗ 16)) AND FFFFH;
r64[15:0] := TEMP[15:0];
r64[63:16] := ZERO_FILL; };
FOR (PEXTRW instruction with 128-bit source operand) { SEL := COUNT[2:0];
r64[15:0] := TEMP[15:0];r64[63:16] := ZERO_FILL; }
ELSE
r32[15:0] := TEMP[15:0];r32[31:16] := ZERO_FILL; };
FOR (PEXTRW instruction with 128-bit source operand)
{ SEL := COUNT[2:0];
FI;
FI;
VPEXTRW ( dest=m16)
SRC_Offset := imm8[2:0]Mem16 := (Src >> Src_Offset*16)
VPEXTRW ( dest=reg)
SRC_Offset := imm8[2:0]DEST[15:0] := ((Src >> Src_Offset*16) AND 0FFFFh)DEST[63:16] := ZERO_FILL;
ELSE
SRC_Offset := imm8[2:0]DEST[15:0] := ((Src >> Src_Offset*16) AND 0FFFFh)DEST[31:16] := ZERO_FILL;
FIPEXTRW—Extract WordINSTRUCTION SET REFERENCE, M-U
4-286 Vol. 2BIntel C/C ++ Compiler Intrinsic Equivalent
PEXTRW int _mm_extract_pi16 (__m64 a, int n)
PEXTRW int _mm_extract_epi1 6 ( __m128i a, int imm) 
None.
None.
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.PHADDW/PHADDD—Packed Horizontal AddINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-287PHADDW/PHADDD—Packed Horizontal Add
(V)PHADDW adds two adjacent 16-bit signed integers hori zontally from the source and destination operands and 
packs the 16-bit signed results to the destination operan d (first operand). (V)PHADDD adds two adjacent 32-bit 
signed integers horizontally from the source and destination operands and packs the 32-bit signed results to the destination operand (first operand). When the source oper and is a 128-bit memory operand, the operand must be 
aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
Note that these instructions can operate on either unsigned or signed (two’s complement notation) integers; 
however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected over-
flow conditions, software must control the ranges of the values operated on. 
Legacy SSE instructions: Both operands can be MMX regist ers. The second source operand can be an MMX register 
or a 64-bit memory location.
128-bit Legacy SSE version: The first source and destin ation operands are XMM registers. The second source 
operand can be an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM 
In 64-bit mode, use the REX prefix to access additional registers. Opcode/
Mode 
Feature 
NP 0F 38 01 /r
1
PHADDW mm1, mm2/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.RM V/V SSSE3 Add 16-bit integers horizontally, pack to mm1. 
66 0F 38 01 /r
PHADDW xmm1, xmm2/m128RM V/V SSSE3 Add 16-bit integers horizontally, pack to 
xmm1.
NP 0F 38 02 /r 
PHADDD mm1, mm2/m64RM V/V SSSE3 Add 32-bit integers horizontally, pack to mm1. 
66 0F 38 02 /r
PHADDD xmm1, xmm2/m128RM V/V SSSE3 Add 32-bit integers horizontally, pack to 
xmm1. 
VEX.128.66.0F38.WIG 01 /r
VPHADDW xmm1, xmm2, xmm3/m128RVM V/V AVX Add 16-bit integers horizontally, pack to 
xmm1.
VEX.128.66.0F38.WIG 02 /r
VPHADDD xmm1, xmm2, xmm3/m128RVM V/V AVX Add 32-bit integers horizontally, pack to 
xmm1.
VEX.256.66.0F38.WIG 01 /r
VPHADDW ymm1, ymm2, ymm3/m256RVM V/V AVX2 Add 16-bit signed integers horizontally, pack 
to ymm1.
VEX.256.66.0F38.WIG 02 /r
VPHADDD ymm1, ymm2, ymm3/m256RVM V/V AVX2 Add 32-bit signed integers horizontally, pack 
to ymm1.
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/APHADDW/PHADDD—Packed Horizontal AddINSTRUCTION SET REFERENCE, M-U
4-288 Vol. 2BVEX.128 encoded version: The first source and destinat ion operands are XMM registers. The second source 
VEX.256 encoded version: Horizontal addition of two adjace nt data elements of the low 16-bytes of the first and 
second source operands are packed into the low 16-bytes of the destination operand. Horizontal addition of two 
adjacent data elements of the high 16-bytes of the first and second source operands are packed into the high 16-
bytes of the destination operand. The first source and de stination operands are YMM registers. The second source 
operand can be an YMM register or a 256-bit memory location. 
Figure 4-10.  25 6-bit VPHADDD Instru ction Operation
Operation 
PHADDW (With 64-bit Operands)
mm1[15-0]  = mm1[31-16] + mm1[15-0]; mm1[31-16] = mm1[63-48] + mm1[47-32]; mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0]; mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32]; 
PHADDW (With 128-bit Operands)
xmm1[15-0] = xmm1[31-16] + xmm1[15-0]; xmm1[31-16] = xmm1[63-48] + xmm1[47-32]; xmm1[47-32] = xmm1[95-80] + xmm1[79-64]; xmm1[63-48] = xmm1[127-112] + xmm1[111-96]; xmm1[79-64] = xmm2/m128[31-16] + xmm2/m128[15-0]; xmm1[95-80] = xmm2/m128[63-48] + xmm2/m128[47-32]; xmm1[111-96] = xmm2/m128[95-80] + xmm2/m128[79-64]; xmm1[127-112] = xmm2/m128[127-112] + xmm2/m128[111-96]; 
VPHADDW (VEX.128 Encoded Version)
DEST[15:0] := SRC1[31:16] + SRC1[15:0]DEST[31:16] := SRC1[63:48] + SRC1[47:32]DEST[47:32] := SRC1[95:80] + SRC1[79:64]DEST[63:48] := SRC1[127:112] + SRC1[111:96]DEST[79:64] := SRC2[31:16] + SRC2[15:0]DEST[95:80] := SRC2[63:48] + SRC2[47:32]DEST[111:96] := SRC2[95:80] + SRC2[79:64]DEST[127:112] := SRC2[1 27:112] + SRC2[111:96]
DEST[MAXVL-1:128] := 0X0 X3 X2 X1 Y0 Y3 Y2 Y1 X4 X7 X6 X5 Y4 Y7 Y6 Y5 SRC2
S0
DestS3 S4
0 255SRC1
S7 S2 S1 S3 S3PHADDW/PHADDD—Packed Horizontal AddINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-289VPHADDW (VEX.256 Encoded Version)
DEST[143:128] := SRC1[1 59:144] + SRC1[143:128]
DEST[159:144] := SRC1[1 91:176] + SRC1[175:160]
DEST[175:160] := SRC1[2 23:208] + SRC1[207:192]
DEST[191:176] := SRC1[2 55:240] + SRC1[239:224]
DEST[207:192] := SRC2[1 27:112] + SRC2[143:128]
DEST[223:208] := SRC2[1 59:144] + SRC2[175:160]
DEST[239:224] := SRC2[1 91:176] + SRC2[207:192]
DEST[255:240] := SRC2[2 23:208] + SRC2[239:224]
PHADDD (With 64-bit Operands)
mm1[31-0]  = mm1[63-32] + mm1[31-0]; mm1[63-32] = mm2/m64[63-32] + mm2/m64[31-0]; 
PHADDD (With 128-bit Operands)
xmm1[31-0] = xmm1[63-32] + xmm1[31-0]; xmm1[63-32] = xmm1[127-96] + xmm1[95-64]; xmm1[95-64] = xmm2/m128[63-32] + xmm2/m128[31-0]; xmm1[127-96] = xmm2/m128[127-96] + xmm2/m128[95-64]; 
VPHADDD (VEX.128 Encoded Version)
DEST[31-0] := SRC1[63-32] + SRC1[31-0]DEST[63-32] := SRC1[1 27-96] + SRC1[95-64]
DEST[95-64] := SRC2[63-32] + SRC2[31-0]DEST[127-96] := SRC2[127-96] + SRC2[95-64]DEST[MAXVL-1:128] := 0
VPHADDD (VEX.256 Encoded Version)
DEST[95-64] := SRC2[63-32] + SRC2[31-0]DEST[127-96] := SRC2[127-96] + SRC2[95-64]DEST[159-128] := SRC1[1 91-160] + SRC1[159-128]
DEST[191-160] := SRC1[2 55-224] + SRC1[223-192]
DEST[223-192] := SRC2[1 91-160] + SRC2[159-128]
DEST[255-224] := SRC2[2 55-224] + SRC2[223-192]
PHADDW __m64 _mm_hadd_pi16 (__m64 a, __m64 b)
PHADDD __m64 _mm_ha dd_pi32 (__m64 a, __m64 b)
(V)PHADDW __m128i _mm_hadd_epi16 (__m128i a, __m128i b)(V)PHADDD __m128i _ mm_hadd_epi32 (__m1 28i a, __m128i b)

VPHADDW __m256i _mm256_hadd_epi16 (__m256i a, __m256i b)VPHADDD __m256i _mm256_hadd_epi32 (__m256i a, __m256i b)PHADDW/PHADDD—Packed Horizontal AddINSTRUCTION SET REFERENCE, M-U
4-290 Vol. 2BSIMD Floating-Point Exceptions 
None. 
#UD If VEX.L = 1.PHADDSW—Packed Horizontal Add and SaturateINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-291PHADDSW—Packed Horizontal Add and Saturate
(V)PHADDSW adds two adjacent signed 16-bit integers hori zontally from the source and destination operands and 
saturates the signed results; packs the signed, saturated 16-bit results to the destination operand (first operand) 
When the source operand is a 128-bit memory operand, th e operand must be aligned on a 16-byte boundary or a 
general-protection exception (#GP) will be generated. 
Legacy SSE version: Both operands can be MMX registers.  The second source operand can be an MMX register or 
a 64-bit memory location.
operand is an XMM register or a 128-bit memory locati on. Bits (MAXVL-1:128) of the corresponding YMM destina-
tion register remain unchanged. 
In 64-bit mode, use the REX prefix to access additional registers.
VEX.128 encoded version: The first source and destinat ion operands are XMM registers. The second source 
operand is an XMM register or a 128-bit memory location . Bits (MAXVL-1:128) of the destination YMM register are 
zeroed. 
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source 
operand can be an YMM register or a 256-bit memory location.
Operation 
PHADDSW (With 64-bit Operands)
mm1[15-0]  = SaturateToSignedWord((mm1[31-16] + mm1[15-0]); mm1[31-16] = SaturateToSignedWord(mm1[63-48] + mm1[47-32]);mm1[47-32] = SaturateToSignedWord(mm2/m64[31-16] + mm2/m64[15-0]); mm1[63-48] = SaturateToSignedWord(mm2/m64[63-48] + mm2/m64[47-32]); Opcode/
Mode 
Feature 
NP 0F 38 03 /r
1 
PHADDSW mm1, mm2/m64 
NOTES:
Registers,” in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.RM V/V SSSE3 Add 16-bit signed integers horizontally, pack 
saturated integers to mm1.
66 0F 38 03 /r
PHADDSW xmm1, xmm2/m128RM V/V SSSE3 Add 16-bit signed integers horizontally, pack 
saturated integers to xmm1.
VEX.128.66.0F38.WIG 03 /r
VPHADDSW xmm1, xmm2, xmm3/m128RVM V/V AVX Add 16-bit signed integers horizontally, pack 
VEX.256.66.0F38.WIG 03 /r
VPHADDSW ymm1, ymm2, ymm3/m256RVM V/V AVX2 Add 16-bit signed integers horizontally, pack 
saturated integers to ymm1.
RVM ModRM:reg (w) VEX.vv vv (r) ModRM:r/m (r) N/APHADDSW—Packed Horizontal Add and SaturateINSTRUCTION SET REFERENCE, M-U
4-292 Vol. 2BPHADDSW (With 128-bit Operands)
xmm1[15-0]= SaturateToSignedWord(xmm1[31-16] + xmm1[15-0]);
xmm1[31-16] = SaturateToSignedWord(xmm1[63-48] + xmm1[47-32]);xmm1[47-32] = SaturateToSignedWord(xmm1[95-80] + xmm1[79-64]);xmm1[63-48] = SaturateToSignedWord(xmm1[127-112] + xmm1[111-96]); xmm1[79-64] = SaturateToSignedWord(xmm2/m128[31-16] + xmm2/m128[15-0]);xmm1[95-80]
 = SaturateToSignedWord(xmm2/m128[63-48]  + xmm2/m128[47-32]);
xmm1[111-96] = SaturateToSignedWord(xmm2/m128[95-80] + xmm2/m128[79-64]);xmm1[127-112] = SaturateToSignedWord(xmm2/m128[127-112] + xmm2/m128[111-96]); 
VPHADDSW (VEX.128 Encoded Version)
DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])DEST[MAXVL-1:128] := 0
VPHADDSW (VEX.256 Encoded Version)
DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])DEST[143:128]= SaturateToSignedWord(SRC1[159:144] + SRC1[143:128])DEST[159:144] = SaturateToSignedWord(SRC1[191:176] + SRC1[175:160])DEST[175:160] = SaturateToSignedWord( SRC1[223:208] + SRC1[207:192])DEST[191:176] = SaturateToSignedWord(SRC1[255:240] + SRC1[239:224])DEST[207:192] = SaturateToSignedWord(SRC2[127:112] + SRC2[143:128])DEST[223:208] = SaturateToSignedWord(SRC2[159:144] + SRC2[175:160])DEST[239:224] = SaturateToSignedWord(SRC2[191-160] + SRC2[159-128])DEST[255:240] = SaturateToSignedWord(SRC2[255:240] + SRC2[239:224])
PHADDSW __m64 _mm_hadds_pi16 (__m64 a, __m64 b)(V)PHADDSW __m128i _mm_hadds_epi16 (__m128i a, __m128i b)VPHADDSW __m256i _mm256_hadds_e pi16 (__m256i a, __m256i b)
None. 
#UD If VEX.L = 1.PHMINPOSUW—Packed Hori zontal Word MinimumINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-293PHMINPOSUW—Packed Horizontal Word Minimum
Determine the minimum unsigned word value in the sour ce operand (second operand) and place the unsigned 
word in the low word (bits 0-15) of the destination oper and (first operand). The word index of the minimum value 
is stored in bits 16-18 of the destination operand. The remaining upper bits of the destination are set to zero. 
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding XMM destination register remain 
VEX.128 encoded version: Bits (MAXVL-1:128) of the dest ination XMM register are zero ed. VEX.vvvv is reserved 
and must be 1111b, VEX.L must be 0,  otherwise the instruction will #UD.
Operation
PHMINPOSUW (128-bit Legacy SSE Version)
INDEX := 0;MIN := SRC[15:0]IF (SRC[31:16] < MIN) 
THEN INDEX := 1;  MIN := SRC[31:16]; FI;
IF (SRC[47:32] < MIN) 
THEN INDEX := 2;  MIN := SRC[47:32]; FI;
* Repeat operation fo r words 3 through 6
IF (SRC[127:112] < MIN) 
THEN INDEX := 7;  MIN := SRC[127:112]; FI;
DEST[15:0] := MIN;DEST[18:16] := INDEX;DEST[127:19] := 0000000000000000000000000000H;
VPHMINPOSUW (VEX.128 Encoded Version)
INDEX := 0MIN := SRC[15:0]IF (SRC[31:16] < MIN) THEN IN DEX := 1; MIN := SRC[31:16]
IF (SRC[47:32] < MIN) THEN IN DEX := 2; MIN := SRC[47:32]
IF (SRC[127:112] < MIN) THEN INDEX := 7; MIN := SRC[127:112]DEST[15:0] := MINDEST[18:16] := INDEXDEST[127:19] := 0000000000000000000000000000HDEST[MAXVL-1:128] := 0Opcode/
Mode 
Feature 
66 0F 38 41 /r
PHMINPOSUW xmm1, xmm2/m128RM V/V SSE4_1 Find the minimum unsigned word in xmm2/m128 and 
place its value in the low word of xmm1 and its index 
in the second-lowest word of xmm1.
VEX.128.66.0F38.WIG 41 /r
VPHMINPOSUW xmm1, xmm2/m128RM V/V AVX Find the minimum unsigned word in xmm2/m128 and 
place its value in the low word of xmm1 and its index in the second-lowest word of xmm1.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/APHMINPOSUW—Packed Hori zontal Word MinimumINSTRUCTION SET REFERENCE, M-U
4-294 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
PHMINPOSUW __m128i _mm_minpos _epu16( __m128i packed_words);
None.
None.
If VEX.vvvv ≠ 1111B.PHSUBW/PHSUBD—Packed Horizontal SubtractINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-295PHSUBW/PHSUBD—Packed Horizontal Subtract
(V)PHSUBW performs horizontal subtract ion on each adjacent pair of 16-bit signed integers by subtracting the 
most significant word from the least significant word of ea ch pair in the source and destination operands, and packs 
the signed 16-bit results to the destination operand (first  operand). (V)PHSUBD performs horizontal subtraction on 
each adjacent pair of 32-bit signed integers by subtract ing the most significant double word from the least signifi-
cant doubleword of each pair, and packs the signed 32-b it result to the destination operand. When the source

None.
None.
cant doubleword of each pair, and packs the signed 32-b it result to the destination operand. When the source 
operand is a 128-bit memory operand, the operand must be  aligned on a 16-byte boundary or a general-protection 
exception (#GP) will be generated. 
tion register remain unchanged.
zeroed. Opcode/
Mode 
Feature 
NP 0F 38 05 /r1
PHSUBW mm1, mm2/m64
NOTES:
Registers,” in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.RM V/V SSSE3 Subtract 16-bit signed integers horizontally, 
pack to mm1. 
66 0F 38 05 /r 
PHSUBW xmm1, xmm2/m128RM V/V SSSE3 Subtract 16-bit signed integers horizontally, 
pack to xmm1. 
NP 0F 38 06 /r 
PHSUBD mm1, mm2/m64RM V/V SSSE3 Subtract 32-bit signed integers horizontally, 
66 0F 38 06 /r
PHSUBD xmm1, xmm2/m128 RM V/V SSSE3 Subtract 32-bit signed integers horizontally, 
VEX.128.66.0F38.WIG 05 /r
VPHSUBW xmm1, xmm2, xmm3/m128RVM V/V AVX Subtract 16-bit sign ed integers horizontally, 
pack to xmm1.
VEX.128.66.0F38.WIG 06 /r
VPHSUBD xmm1, xmm2, xmm3/m128RVM V/V AVX Subtract 32-bit sign ed integers horizontally, 
VEX.256.66.0F38.WIG 05 /r
VPHSUBW ymm1, ymm2, ymm3/m256RVM V/V AVX2 Subtract 16-bit signed integers horizontally, 
pack to ymm1.
VEX.256.66.0F38.WIG 06 /r
VPHSUBD ymm1, ymm2, ymm3/m256RVM V/V AVX2 Subtract 32-bit signed integers horizontally, 
RVM ModRM:reg (r, w) VEX. vvvv (r) ModRM:r/m (r) N/APHSUBW/PHSUBD—Packed Horizontal SubtractINSTRUCTION SET REFERENCE, M-U
4-296 Vol. 2BVEX.256 encoded version: The first source and destination operands are YMM registers. The second source 
Operation
PHSUBW (With 64-bit Operands) 
mm1[15-0] = mm1[15-0] - mm1[31-16]; mm1[31-16] = mm1[47-32] - mm1[63-48]; mm1[47-32] = mm2/m64[15-0] - mm2/m64[31-16];mm1[63-48] = mm2/m64[47-32] - mm2/m64[63-48]; 
PHSUBW (With 128-bit Operands)
xmm1[15-0] = xmm1[15-0] - xmm1[31-16]; xmm1[31-16] = xmm1[47- 32] - xmm1[63-48]; 
xmm1[47-32] = xmm1[79- 64] - xmm1[95-80]; 
xmm1[63-48] = xmm1[111-96] - xmm1[127-112]; xmm1[79-64] = xmm2/m128[15-0] - xmm2/m128[31-16]; xmm1[95-80] = xmm2/m128[47-32] - xmm2/m128[63-48]; xmm1[111-96] = xmm2/m128[79-64] - xmm2/m128[95-80]; xmm1[127-112] = xmm2/m128[111-96] - xmm2/m128[127-112];
VPHSUBW (VEX.128 Encoded Version)
DEST[15:0] := SRC1[15:0] - SRC1[31:16]DEST[31:16] := SRC1[47:32] - SRC1[63:48]DEST[47:32] := SRC1[79:64] - SRC1[95:80]DEST[63:48] := SRC1[111:96] - SRC1[127:112]DEST[79:64] := SRC2[15:0] - SRC2[31:16]DEST[95:80] := SRC2[47:32] - SRC2[63:48]DEST[111:96] := SRC2[79:64] - SRC2[95:80]DEST[127:112] := SRC2[111:96] - SRC2[127:112]DEST[MAXVL-1:128] := 0
VPHSUBW (VEX.256 Encoded Version)
DEST[15:0] := SRC1[15:0] - SRC1[31:16]DEST[31:16] := SRC1[47:32] - SRC1[63:48]DEST[47:32] := SRC1[79:64] - SRC1[95:80]DEST[63:48] := SRC1[111:96] - SRC1[127:112]DEST[79:64] := SRC2[15:0] - SRC2[31:16]DEST[95:80] := SRC2[47:32] - SRC2[63:48]DEST[111:96] := SRC2[79:64] - SRC2[95:80]DEST[127:112] := SRC2[111:96] - SRC2[127:112]DEST[143:128] := SRC1[143:128] - SRC1[159:144]DEST[159:144] := SRC1[175:160] - SRC1[191:176]DEST[175:160] := SRC1[207:192] - SRC1[223:208]DEST[191:176] := SRC1[239:224] - SRC1[255:240]DEST[207:192] := SRC2[143:128] - SRC2[159:144]DEST[223:208] := SRC2[175:160] - SRC2[191:176]DEST[239:224] := SRC2[207:192] - SRC2[223:208]DEST[255:240] := SRC2[239:224] - SRC2[255:240]
PHSUBD (With 64-bit Operands)
mm1[31-0] = mm1[31-0] - mm1[63-32];mm1[63-32] = mm2/m64[31-0] - mm2/m64[63-32];PHSUBW/PHSUBD—Packed Horizontal SubtractINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-297PHSUBD (With 128-bit Operands)
xmm1[31-0] = xmm1[31-0] - xmm1[63-32]; xmm1[63-32] = xmm1[95- 64] - xmm1[127-96]; 
xmm1[95-64] = xmm2/m128[31-0] - xmm2/m128[63-32]; xmm1[127-96] = xmm2/m128[95-64] - xmm2/m128[127-96]; 
VPHSUBD (VEX.128 Encoded Version)
DEST[31-0] := SRC1[31-0] - SRC1[63-32]DEST[63-32] := SRC1[95-64] - SRC1[127-96]DEST[95-64] := SRC2[31-0] - SRC2[63-32]DEST[127-96] := SRC2[95-64] - SRC2[127-96]DEST[MAXVL-1:128] := 0
VPHSUBD (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC1[63:32]DEST[63:32] := SRC1[95:64] - SRC1[127:96]DEST[95:64] := SRC2[31:0] - SRC2[63:32]DEST[127:96] := SRC2[95:64] - SRC2[127:96]DEST[159:128] := SRC1[1 59:128] - SRC1[191:160]
PHSUBW __m64 _mm_hsub_pi16 (__m64 a, __m64 b)
PHSUBD __m64 _mm_hsub_pi32 (__m64 a, __m64 b)(V)PHSUBW __m128i _mm_hsub_epi16 (__m128i a, __m128i b)(V)PHSUBD __m128i _mm_hsub_epi32 (__m128i a, __m128i b)VPHSUBW __m256i _mm256_hsub_epi16 (__m256i a, __m256i b)VPHSUBD __m256i _mm256_hsub_epi32 (__m256i a, __m256i b)
None. 
#UD If VEX.L = 1.PHSUBSW—Packed Horizontal Subtract and SaturateINSTRUCTION SET REFERENCE, M-U
4-298 Vol. 2BPHSUBSW—Packed Horizontal Subtract and Saturate
(V)PHSUBSW performs horizontal subtraction on each adjace nt pair of 16-bit signed integers by subtracting the 
signed, saturated 16-bit results are packed to the destinat ion operand (first operand). When the source operand is 
a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception 
(#GP) will be generated. 
Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a 
64-bit memory location.
In 64-bit mode, use the REX prefix to access additional registers. 
zeroed.
Operation
PHSUBSW (With 64-bit Operands)
mm1[15-0] = SaturateToSignedWord(mm1[15-0] - mm1[31-16]); mm1[31-16] = SaturateToSignedWord(mm1[47-32] - mm1[63-48]);mm1[47-32] = SaturateToSignedWord(mm2/m64[15-0] - mm2/m64[31-16]); mm1[63-48] = SaturateToSignedWord(mm2/m64[47-32] - mm2/m64[63-48]);Opcode/
Mode 
Feature 
NP 0F 38 07 /r
1 
PHSUBSW mm1, mm2/m64 
NOTES:
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.RM V/V SSSE3 Subtract 16-bit signed integer horizontally, 
pack saturated integers to mm1.
66 0F 38 07 /r
PHSUBSW xmm1, xmm2/m128 RM V/V SSSE3 Subtract 16-bit signed integer horizontally, 
pack saturated integers to xmm1.
VEX.128.66.0F38.WIG 07 /r
VPHSUBSW xmm1, xmm2, xmm3/m128RVM V/V AVX Subtract 16-bit si gned integer horizontally, 
VEX.256.66.0F38.WIG 07 /r
VPHSUBSW ymm1, ymm2, ymm3/m256RVM V/V AVX2 Subtract 16-bit signed integer horizontally, 
pack saturated integers to ymm1.
RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/APHSUBSW—Packed Horizontal Subtract and SaturateINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-299PHSUBSW (With 128-bit Operands)

xmm1[15-0] = SaturateToSignedWord(xmm1[15-0] - xmm1[31-16]); xmm1[31-16] = SaturateToSignedWord(xmm1[47-32] - xmm1[63-48]);xmm1[47-32] = SaturateToSignedWord(xmm1[79-64] - xmm1[95-80]);xmm1[63-48] = SaturateToSignedWord(xmm1[111-96] - xmm1[127-112]);xmm1[79-64] = SaturateToSignedWord(xmm2/m128[15-0] - xmm2/m128[31-16]); xmm1[95-80] =SaturateToSignedWord(xmm2 /m128[47-32] - xmm2/m128[63-48]); 
xmm1[111-96] =SaturateToSignedWord(xmm2/m128[79-64] - xmm2/m128[95-80]);xmm1[127-112]= SaturateToSignedWord(xmm2/m128[111-96] - xmm2/m128[127-112]);
VPHSUBSW (VEX.128 Encoded Version)
DEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])DEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])DEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])DEST[63:48] = Saturate ToSignedWord(SRC1[111:96] - SRC1[127:112])
DEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])DEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])DEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])DEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])DEST[MAXVL-1:128] := 0
VPHSUBSW (VEX.256 Encoded Version)
DEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])DEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])DEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])DEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])DEST[143:128]= SaturateToSignedWord(SRC1[143:128] - SRC1[159:144])DEST[159:144] = SaturateToSignedWord(SRC1[175:160] - SRC1[191:176])DEST[175:160] = SaturateToSignedWord(SRC1[207:192] - SRC1[223:208])DEST[191:176] = SaturateToSignedWord(SRC1[239:224] - SRC1[255:240])DEST[207:192] = SaturateToSignedWord(SRC2[143:128] - SRC2[159:144])DEST[223:208] = SaturateToSignedWord(SRC2[175:160] - SRC2[191:176])DEST[239:224] = SaturateToSignedWord(SRC2[207:192] - SRC2[223:208])DEST[255:240] = SaturateToSignedWord(SRC2[239:224] - SRC2[255:240])
PHSUBSW __m64 _mm_hsubs_pi16 (__m64 a, __m64 b)(V)PHSUBSW __m128i _mm_hsubs_epi16 (__m128i a, __m128i b)VPHSUBSW __m256i _mm256_hsubs_epi16 (__m256i a, __m256i b)
None. 
#UD If VEX.L = 1.PINSRB/PINSRD/PINSRQ—Insert Byte/Dword/QwordINSTRUCTION SET REFERENCE, M-U
4-300 Vol. 2BPINSRB/PINSRD/PINSRQ—Insert Byte/Dword/Qword
Copies a byte/dword/qword from the source operand (sec ond operand) and inserts it in the destination operand 
(first operand) at the location specified with the count operand (third operand). (The other elements in the desti-
nation register are left untouched.) The source operand can be a general-purpose regi ster or a memory location. 
(When the source operand is a general-purpose register, PI NSRB copies the low byte of the register.) The destina-
tion operand is an XMM register. The count operand is an 8-bit immediate. When specifying a qword[dword, byte] 
location in an XMM register, the [2, 4] least-signific ant bit(s) of the count operand specify the location.Opcode/
Mode 
Feature 
66 0F 3A 20 /r ib
PINSRB xmm1, r32/m8, imm8A V/V SSE4_1 Insert a byte integer value from r32/m8 into 
xmm1 at the destination element in xmm1 
specified by imm8.
66 0F 3A 22 /r ib
PINSRD xmm1, r/m32, imm8A V/V SSE4_1 Insert a dword integer value from r/m32 into 
the xmm1 at the destination element specified by imm8.
66 REX.W 0F 3A 22 /r ib
PINSRQ xmm1, r/m64, imm8A V/N. E. SSE4_1 Insert a qword integer value from r/m64 into 
the xmm1 at the destination element 
VEX.128.66.0F3A.W0 20 /r ib
VPINSRB xmm1, xmm2, r32/m8, imm8BV
1/V
NOTES:
1. In 64-bit mode, VEX.W1 is ignored for VPINSRB (similar to legacy REX.W=1 prefix with PINSRB).AVX Merge a byte integer value from r32/m8 and 
rest from xmm2 into xmm1 at the byte offset 
in imm8.
VEX.128.66.0F3A.W0 22 /r ib
VPINSRD xmm1, xmm2, r/m32, imm8B V/V AVX Insert a dword integer value from r32/m32 
and rest from xmm2 in to xmm1 at the dword 
offset in imm8.
VEX.128.66.0F3A.W1 22 /r ib
VPINSRQ xmm1, xmm2, r/m64, imm8BV / I2
2. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVX Insert a qword integer value from r64/m64 
and rest from xmm2 in to xmm1 at the qword 
EVEX.128.66.0F3A.WIG 20 /r ib
VPINSRB xmm1, xmm2, r32/m8, imm8C V/V AVX512BW Merge a byte inte ger value from r32/m8 and 
in imm8.
EVEX.128.66.0F3A.W0 22 /r ib
VPINSRD xmm1, xmm2, r32/m32, imm8C V/V AVX512DQ Insert a dword integer value from r32/m32 
EVEX.128.66.0F3A.W1 22 /r ib
VPINSRQ xmm1, xmm2, r64/m64, imm8CV / N . E .2AVX512DQ Insert a qword integer value from r64/m64 
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8PINSRB/PINSRD/PINSRQ—Insert Byte/Dword/QwordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-301In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to 
access additional registers (XMM8-XMM15, R8-15). Use of REX.W permits the use of 64 bit general purpose regis-
ters.
VEX.128 encoded version: Bits (MAXVL-1:128) of the destin ation register are zeroed. VEX.L must be 0, otherwise 
the instruction will #UD. Attempt to execute VPINSRQ in non-64-bit mode will cause #UD.
EVEX.128 encoded version: Bits (MAXVL-1:128) of the dest ination register are zeroed. EVEX.L’L must be 0, other-
wise the instruction will #UD. 
Operation
CASE OF
PINSRB: SEL := COUNT[3:0];
MASK := (0FFH << (SEL * 8)); TEMP := (((SRC[7:0] << (SEL *8)) AND MASK);
PINSRD: SEL := COUNT[1:0];
MASK := (0FFFFFFFFH << (SEL * 32)); TEMP := (((SRC << (SEL *32)) AND MASK) ;
PINSRQ: SEL := COUNT[0]
MASK := (0FFFFFFFFFFFFFFFFH << (SEL * 64)); TEMP := (((SRC << (SEL *64)) AND MASK) ;
ESAC;
DEST := ((DEST AND NOT MASK) OR TEMP); 
VPINSRB (VEX/EVEX Encoded Version)
SEL := imm8[3:0]DEST[127:0] := write_b_element(SEL, SRC2, SRC1)DEST[MAXVL-1:128] := 0
VPINSRD (VEX/EVEX Encoded Version)
SEL := imm8[1:0]DEST[127:0] := write_d_element(SEL, SRC2, SRC1)DEST[MAXVL-1:128] := 0
VPINSRQ (VEX/EVEX Encoded Version)
SEL := imm8[0]DEST[127:0] := write_q_element(SEL, SRC2, SRC1)DEST[MAXVL-1:128] := 0
PINSRB __m128i _mm_insert_epi8 (__m 128i s1, int s2, const int ndx);
PINSRD __m128i _mm_insert_epi32 ( __m128i s2, int s, const int ndx);
PINSRQ __m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx);
None.
None.PINSRB/PINSRD/PINSRQ—Insert Byte/Dword/QwordINSTRUCTION SET REFERENCE, M-U
4-302 Vol. 2BOther Exceptions
EVEX-encoded instruction, see Table 2-22, “Type 5 Class Exception Conditions.”
#UD If VEX.L = 1 or EVEX.L’L > 0.PINSRW—Insert WordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-303PINSRW—Insert Word
Three operand MMX and SSE instructions:
Copies a word from the source operand and inserts it in the destination operand at the location specified with the 
count operand. (The other words in the destination register are left untouched.) The source operand can be a 
general-purpose register or a 16-bit memory location. (Whe n the source operand is a general-purpose register, the 
low word of the register is copied.) The destination operan d can be an MMX technology register or an XMM register. 
The count operand is an 8-bit immediate. When specifying  a word location in an MMX technology register, the 2 
least-significant bits of the count operand specify the lo cation; for an XMM register, the 3 least-significant bits 
specify the location.
Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.Four operand AVX and AVX-512 instructions: 
Combines a word from the first source operand with the se cond source operand, and inserts it in the destination 
operand at the location specified with the count operan d. The second source operand can be a general-purpose 
register or a 16-bit memory location. (When the source op erand is a general-purpose register, the low word of the 
register is copied.) The first source and destination op erands are XMM registers. The count operand is an 8-bit

register is copied.) The first source and destination op erands are XMM registers. The count operand is an 8-bit 
immediate. When specifying a word location, th e 3 least-significant bits specify the location.
Bits (MAXVL-1:128) of the destination YMM register are ze roed. VEX.L/EVEX.L’L must be 0, otherwise the instruc-
tion will #UD. Opcode/
Mode 
Feature 
NP 0F C4 / r ib
1
PINSRW mm, r32/m16, imm8A V/V SSE Insert the low word from r32 or from m16 
into mm at the word position specified by 
imm8.
66 0F C4 / r ib
PINSRW xmm, r32/m16, imm8A V/V SSE2 Move the low word of r32 or from m16 into 
xmm at the word position specified by imm8.
VEX.128.66.0F.W0 C4 /r ib
VPINSRW xmm1, xmm2, r32/m16, imm8BV2/V AVX Insert the word from r32/m16 at the offset 
indicated by imm8 into  the value from xmm2 
EVEX.128.66.0F.WIG C4 /r ib
VPINSRW xmm1, xmm2, r32/m16, imm8C V/V AVX512BW Insert the word from r32/m16 at the offset 
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX  
2. In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar to legacy REX.W=1 prefix in PINSRW).
A N/A ModRM:reg (w) Mod RM:r/m (r) imm8 N/A
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8PINSRW—Insert WordINSTRUCTION SET REFERENCE, M-U
4-304 Vol. 2BOperation
PINSRW dest, src, imm8 (MMX)
SEL := imm8[1:0]
     DEST.word[SEL] := src.word[0]
PINSRW dest, src, imm8 (SSE)
SEL := imm8[2:0]
VPINSRW dest, src1, sr c2, imm8 (AVX/AVX512)
SEL := imm8[2:0]DEST := src1
     DEST.word[SEL] := src2.word[0]     DEST[MAXVL-1:128] := 0
PINSRW __m64 _mm_insert_pi1 6 (__m64 a, int d, int n)
PINSRW __m128i _mm_insert_epi16 ( __m128i a, int b, int imm)
None.
None.
EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions.”
#UD If VEX.L = 1 or EVEX.L’L > 0.PMADDUBSW—Multiply and Add Packed Signed and Unsigned BytesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-305PMADDUBSW—Multiply an d Add Packed Signed and Unsigned Bytes
(V)PMADDUBSW multiplies vertically each unsigned byte of  the destination operand (first operand) with the corre-
sponding signed byte of the source operand (second op erand), producing intermediate signed 16-bit integers. 
Each adjacent pair of signed words is added and the satu rated result is packed to the destination operand. For 
example, the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the interme-
diate signed word result is added with  the corresponding intermediate result from the 2nd lowest-order bytes (bits 
15-8) of the operands; the sign-saturated result is stored in the lowest word of the de stination register (15-0). The 
same operation is performed on the other pairs of adjace nt bytes. Both operands can be MMX register or XMM 
registers. When the source operand is a 128-bit memory  operand, the operand must be aligned on a 16-byte 
boundary or a general-protection exception (#GP) will be generated. 
In 64-bit mode and not encoded with VEX/EV EX, use the REX prefix to access XMM8-XMM15. Opcode/
Mode 
Feature 
NP 0F 38 04 /r1 
PMADDUBSW mm1, mm2/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSSE3 Multiply signed and unsigned bytes, add 
horizontal pair of signed words, pack 
saturated signed-words to mm1. 
66 0F 38 04 /r 
PMADDUBSW xmm1, xmm2/m128 A V/V SSSE3 Multiply signed and unsigned bytes, add 
saturated signed-words to xmm1.
VEX.128.66.0F38.WIG 04 /r
VPMADDUBSW xmm1, xmm2, xmm3/m128B V/V AVX Multiply signed and unsigned bytes, add 
VEX.256.66.0F38.WIG 04 /r
VPMADDUBSW ymm1, ymm2, ymm3/m256B V/V AVX2 Multiply signed and unsigned bytes, add 
saturated signed-words to ymm1.
EVEX.128.66.0F38.WIG 04 /r
VPMADDUBSW xmm1 {k1 }{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWMultiply signed and unsigned bytes, add 
saturated signed-words to xmm1 under 
EVEX.256.66.0F38.WIG 04 /r
VPMADDUBSW ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
saturated signed-words to ymm1 under 
EVEX.512.66.0F38.WIG 04 /r
VPMADDUBSW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Multiply signed and unsigned bytes, add 
saturated signed-words to zmm1 under 
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMADDUBSW—Multiply and Add Packed Signed and Unsigned BytesINSTRUCTION SET REFERENCE, M-U
4-306 Vol. 2B128-bit Legacy SSE version: The first source and destin ation operands are XMM registers. The second source 
operand is an XMM register or a 128-bit memory location. Bits ( MAXVL-1 :128) of the corresponding destination 
VEX.128 and EVEX.128 encoded versions: The first source an d destination operands are XMM registers. The second 
source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding desti-
VEX.256 and EVEX.256 encoded versions: The second source  operand can be an YMM register or a 256-bit memory 
location. The first source and destination operands are YMM registers. Bits (MAXVL-1 :256) of the corresponding 
ZMM register are zeroed.
EVEX.512 encoded version: The second source operand ca n be an ZMM register or a 512-bit memory location. The 
first source and destination operands are ZMM registers.
Operation
PMADDUBSW (With 64-bit Operands)
DEST[15-0] = SaturateToSignedWord(SRC [15-8]*DEST[15-8]+SRC[7-0]*DEST[7-0]);
DEST[31-16] = SaturateToSignedWord(SRC[31- 24]*DEST[31-24]+SRC[23-16]*DEST[23-16]);
DEST[47-32] = SaturateToSignedWord(SRC[47- 40]*DEST[47-40]+SRC[39-32]*DEST[39-32]);
DEST[63-48] = SaturateToSignedWord(SRC[63- 56]*DEST[63-56]+SRC[55-48]*DEST[55-48]);
PMADDUBSW (With 128-bit Operands)
DEST[15-0] = SaturateToSignedWord(SRC[1 5-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);
// Repeat operation for 2nd through 7th word SRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-1 20]*DEST[127-120]+ SRC[11 9-112]* DEST[119-112]);
VPMADDUBSW (VEX.128 Encoded Version)
DEST[15:0] := SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])// Repeat operation for 2nd through 7th word DEST[127:112] := SaturateToSignedWord(SRC2[127:12 0]*SRC1[127:120]+ SRC2[119:112]* SRC1[119:112])
VPMADDUBSW (VEX.256 Encoded Version)
DEST[15:0] := SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])// Repeat operation for 2nd through 15th word DEST[255:240] := SaturateToSignedWord(SRC2[255:24 8]*SRC1[255:248]+ SRC2[247:240]* SRC1[247:240])
VPMADDUBSW (EVEX Encoded Versions)
THEN DEST[i+15:i] := SaturateToSignedWord(SRC2[i+ 15:i+8]* SRC1[i+15:i+8] + SRC2[i+7:i]* SRC1[i+7:i])
ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PMADDUBSW—Multiply and Add Packed Signed and Unsigned BytesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-307Intel C/C++ Compiler Intrinsic Equivalents
VPMADDUBSW __m512i _mm512_maddubs_epi16( __m512i a, __m512i b);
VPMADDUBSW __m512i _mm512_mask_maddubs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPMADDUBSW __m512i _mm512_maskz_maddubs_epi16( __mmask32 k, __m512i a, __m512i b);VPMADDUBSW __m256i _mm256_mask_maddubs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMADDUBSW __m256i _mm256_maskz_maddubs_epi16( __mmask16 k, __m256i a, __m256i b);VPMADDUBSW __m128i _mm_mask_maddubs_epi16(__m 128i s, __mmask8 k, __m128i a, __m128i b);

ELSE 
FI
FI;
VPMADDUBSW __m128i _mm_maskz_maddubs_epi16( __mmask8 k, __m128i a, __m128i b);PMADDUBSW __m64 _mm_maddubs_pi16 (__m64 a, __m64 b)(V)PMADDUBSW __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)VPMADDUBSW __m256i _mm256_maddubs_epi16 (__m256i a, __m256i b)
None.
EVEX-encoded instruction, see Exceptions Type E4NF.n b in Table 2-50, “Type E4NF Class Exception Conditions.”PMADDWD—Multiply and Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-308 Vol. 2BPMADDWD—Multiply and Add Packed Integers
Multiplies the individual signed words of the destination operand (first operand) by the corresponding signed words 
of the source operand (second operand), producing tempor ary signed, doubleword results. The adjacent double-
word results are then summed and stored in the destinat ion operand. For example, the corresponding low-order 
words (15-0) and (31-16) in the source and destination operands are multiplied by one another and the double-
word results are added together and stored in the low do ubleword of the destination register (31-0). The same 
operation is performed on the other pairs of adjacent wo rds. (Figure 4-11 shows this operation when using 64-bit 
operands).Opcode/
Mode 
Feature 
NP 0F F5 /r1
PMADDWD mm, mm/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V MMX Multiply the packed words in mm by the packed 
words in mm/m64, add adjacent doubleword 
results, and store in mm.
66 0F F5 /r
PMADDWD xmm1, xmm2/m128A V/V SSE2 Multiply the packed word integers in xmm1 by 
the packed word intege rs in xmm2/m128, add 
adjacent doubleword re sults, and store in 
xmm1.
VEX.128.66.0F.WIG F5 /r
VPMADDWD xmm1, xmm2, xmm3/m128B V/V AVX Multiply the packed word integers in xmm2 by 
the packed word intege rs in xmm3/m128, add 
xmm1.
VEX.256.66.0F.WIG F5 /r
VPMADDWD ymm1, ymm2, ymm3/m256B V/V AVX2 Multiply the packed word integers in ymm2 by 
the packed word integers in ymm3/m256, add 
ymm1.
EVEX.128.66.0F.WIG F5 /r
VPMADDWD xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWMultiply the packed word integers in xmm2 by 
xmm1 under writemask k1.
EVEX.256.66.0F.WIG F5 /r
VPMADDWD ymm1 {k1}{z}, ymm2, ymm3/m256C V/V AVX512VL
AVX512BWMultiply the packed word integers in ymm2 by 
ymm1 under writemask k1.
EVEX.512.66.0F.WIG F5 /r
VPMADDWD zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Multiply the packed word integers in zmm2 by 
the packed word integers in zmm3/m512, add 
zmm1 under writemask k1.
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMADDWD—Multiply and Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-309The (V)PMADDWD instruction wraps around  only in one situation: when the 2 pairs of words being operated on in 
a group are all 8000H. In this case, the result wraps around to 80000000H.
Legacy SSE version: The first source and destination operan ds are MMX registers. The second source operand is an 
MMX register or a 64-bit memory location. 
zeroed. 
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The 
first source and destination operands are YMM registers.
EVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The 
Operation
PMADDWD (With 64-bit Operands)
DEST[31:0] := (DEST[15:0] ∗ SRC[15:0]) + (DEST[31:16] ∗ SRC[31:16]);
DEST[63:32] := (DEST[47:32] ∗ SRC[47:32]) + (DEST[63:48] ∗ SRC[63:48]);
PMADDWD (With 128-bit Operands)
DEST[95:64] := (DEST[79:64] ∗ SRC[79:64]) + (DEST[95:80] ∗ SRC[95:80]);
DEST[127:96] := (DEST[111:96] ∗ SRC[111:96]) + (DEST[127:112] ∗ SRC[127:112]);
VPMADDWD (VEX.128 Encoded Version)
DEST[31:0] := (SRC1[15:0] * SRC2[ 15:0]) + (SRC1[31:16] * SRC2[31:16])
DEST[63:32] := (SRC1[47:32] * SRC2[4 7:32]) + (SRC1[63:48] * SRC2[63:48])
DEST[95:64] := (SRC1[79:64] * SRC2[7 9:64]) + (SRC1[95:80] * SRC2[95:80])
DEST[127:96] := (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])DEST[MAXVL-1:128] := 0Figure 4-11.  PMADDWD Execution Model Using 64-bit OperandsX3 X2 X1 X0
X3 ∗ Y3 X2 ∗ Y2 X1 ∗ Y1 X0 ∗ Y0SRC
DEST
DESTY3 Y2 Y1 Y0
(X1∗Y1) + (X0∗Y0) (X3∗Y3) + (X2∗Y2) TEMPPMADDWD—Multiply and Add Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-310 Vol. 2BVPMADDWD (VEX.256 Encoded Version)
DEST[31:0] := (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])DEST[63:32] := (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])DEST[95:64] := (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])DEST[127:96] := (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])DEST[159:128] := (SRC1[143:128] * SRC2[143 :128]) + (SRC1[159:144] * SRC2[159:144])
DEST[191:160] := (SRC1[175:160] * SRC2[175 :160]) + (SRC1[191:176] * SRC2[191:176])
DEST[223:192] := (SRC1[207:192] * SRC2[207 :192]) + (SRC1[223:208] * SRC2[223:208])
DEST[255:224] := (SRC1[239:224] * SRC2[239 :224]) + (SRC1[255:240] * SRC2[255:240])
VPMADDWD (EVEX Encoded Versions)
THEN DEST[i+31:i] := (SRC2[i+31:i+16]* SR C1[i+31:i+16]) + (SRC2[i+15:i]*SRC1[i+15:i])
ELSE 
FI
FI;
VPMADDWD __m512i _mm512_madd_epi16( __m512i a, __m512i b);
VPMADDWD __m512i _mm512_mask_madd_epi16(__m51 2i s, __mmask32 k, __m512i a, __m512i b);
VPMADDWD __m512i _mm512_maskz_madd_epi16( __mmask32 k, __m512i a, __m512i b);VPMADDWD __m256i _mm256_mask_madd_epi16(__m25 6i s, __mmask16 k, __m256i a, __m256i b);
VPMADDWD __m256i _mm256_maskz_madd_epi16( __mmask16 k, __m256i a, __m256i b);VPMADDWD __m128i _mm_mask_madd_epi16(__m128 i s, __mmask8 k, __m128i a, __m128i b);
VPMADDWD __m128i _mm_maskz_madd_epi16(  __mmask8 k, __m128i a, __m128i b);
PMADDWD __m64 _mm_madd_pi16(__m64 m1, __m64 m2)(V)PMADDWD __m128i _mm_madd_epi16 ( __m128i a, __m128i b)VPMADDWD __m256i _mm256_madd_epi16 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Except ions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-311PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers
Opcode/
Mode 
NP 0F EE /r1
PMAXSW mm1, mm2/m64A V/V SSE Compare signed word integers in mm2/m64 and mm1 
and return maximum values.
66 0F 38 3C /r
PMAXSB xmm1, xmm2/m128A V/V SSE4_1 Compare packed signed  byte integers in xmm1 and 
xmm2/m128 and store packed maximum values in 
xmm1.
66 0F EE /r
PMAXSW xmm1, xmm2/m128A V/V SSE2 Compare packed signed word integers in xmm2/m128 
and xmm1 and stores maximum packed values in 
xmm1.
66 0F 38 3D /r
PMAXSD xmm1, xmm2/m128A V/V SSE4_1 Compare packed signed dword integers in xmm1 and 
xmm2/m128 and store packed maximum values in xmm1.
VEX.128.66.0F38.WIG 3C /r

Opcode/
Mode 
NP 0F EE /r1
xmm1.
66 0F EE /r
xmm1.
VPMAXSB xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed byte integers in xmm2 and 
xmm3/m128 and store packed maximum values in xmm1.
VEX.128.66.0F.WIG EE /r
VPMAXSW xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed word integers in xmm3/m128 
and xmm2 and store packed maximum values in 
xmm1.
VEX.128.66.0F38.WIG 3D /r
VPMAXSD xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed dword integers in xmm2 and 
xmm3/m128 and store packed maximum values in 
xmm1.
VEX.256.66.0F38.WIG 3C /r
VPMAXSB ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed byte integers in ymm2 and 
ymm3/m256 and store packed maximum values in ymm1.
VEX.256.66.0F.WIG EE /r
VPMAXSW ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed word integers in ymm3/m256 
and ymm2 and store packed maximum values in 
ymm1.
VEX.256.66.0F38.WIG 3D /r
VPMAXSD ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed dword integers in ymm2 and 
ymm3/m256 and store packed maximum values in 
ymm1.
EVEX.128.66.0F38.WIG 3C /r
VPMAXSB xmm1{k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWCompare packed signed byte  integers in xmm2 and 
xmm3/m128 and store packed maximum values in xmm1 under writemask k1.
EVEX.256.66.0F38.WIG 3C /r
VPMAXSB ymm1{k1}{z}, ymm2, 
ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWCompare packed signed byte  integers in ymm2 and 
EVEX.512.66.0F38.WIG 3C /r
VPMAXSB zmm1{k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Compare packed signed  byte integers in zmm2 and 
zmm3/m512 and store packed maximum values in 
EVEX.128.66.0F.WIG EE /r
VPMAXSW xmm1{k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWCompare packed signed word  integers in xmm2 and 
EVEX.256.66.0F.WIG EE /r
VPMAXSW ymm1{k1}{z}, ymm2, 
AVX512BWCompare packed signed word  integers in ymm2 and 
EVEX.512.66.0F.WIG EE /r
VPMAXSW zmm1{k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Compare packed signed word integers in zmm2 and 
zmm1 under writemask k1.PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maxi mum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
4-312 Vol. 2BInstruction Operand Encoding
Performs a SIMD compare of the packed signed byte, word , dword or qword integers in the second source operand 
and the first source operand and returns the maximum value for each pair of integers to the destination operand. 
Legacy SSE version PMAXSW: The source operand can be an  MMX technology register or a 64-bit memory location. 
The destination operand can be an MMX technology register.
operand is an XMM register or a 128-bit memory locati on. Bits (MAXVL-1:128) of the corresponding destination 
first source and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.
EVEX encoded VPMAXSD/Q: The first source operand is a ZMM/YMM/XMM register; The second source operand is 
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
EVEX encoded VPMAXSB/W: The first so urce operand is a ZMM/YMM/XMM register; The second source operand is 
a ZMM/YMM/XMM register, a 512/256/128-bit memory locati on. The destination operand is conditionally updated 
based on writemask k1.EVEX.128.66.0F38.W0 3D /r
VPMAXSD xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcstD V/V AVX512VL
AVX512FCompare packed signed dword integers in xmm2 and 
xmm3/m128/m32bcst and store packed maximum 
values in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 3D /r
VPMAXSD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstD V/V AVX512VL
AVX512FCompare packed signed dword integers in ymm2 and 
ymm3/m256/m32bcst and store packed maximum values in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 3D /r
VPMAXSD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstD V/V AVX512F Compare packed signed dword integers in zmm2 and 
zmm3/m512/m32bcst and store packed maximum 
values in zmm1 using writemask k1.
EVEX.128.66.0F38.W1 3D /r
VPMAXSQ xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcstD V/V AVX512VL
AVX512FCompare packed signed qword integers in xmm2 and 
xmm3/m128/m64bcst and store packed maximum 
EVEX.256.66.0F38.W1 3D /r
VPMAXSQ ymm1 {k1}{z}, ymm2, 
AVX512FCompare packed signed qword integers in ymm2 and 
ymm3/m256/m64bcst and store packed maximum 
values in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 3D /r
VPMAXSQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstD V/V AVX512F Compare packed signed qword integers in zmm2 and 
zmm3/m512/m64bcst and store packed maximum values in zmm1 using writemask k1.
Mode 
Feature FlagDescriptionPMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-313Operation
PMAXSW (64-bit Operands)
IF DEST[15:0] > SRC[15:0]) THEN
DEST[15:0] := DEST[15:0];
ELSE
DEST[15:0] := SRC[15:0]; FI;
(* Repeat operation for 2nd and 3rd words in source and destination operands *)IF DEST[63:48] > SRC[63:48]) THEN
DEST[63:48] := DEST[63:48];
ELSE
DEST[63:48] := SRC[63:48]; FI;
PMAXSB (128-bit Legacy SSE Version)
IF DEST[7:0] > SRC[7:0] THEN
DEST[7:0] := DEST[7:0];
ELSE
DEST[7:0] := SRC[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)IF DEST[127:120] >SRC[127:120] THEN
DEST[127:120] := DEST[127:120];
ELSE
DEST[127:120] := SRC[127:120]; FI;
VPMAXSB (VEX.128 Encoded Version)
IF SRC1[7:0] > SRC2[7:0] THEN
DEST[7:0] := SRC1[7:0];
ELSE
DEST[7:0] := SRC2[7:0]; FI;
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)IF SRC1[127:120] >SRC2[127:120] THEN
DEST[127:120] := SRC1[127:120];
ELSE
DEST[127:120] := SRC2[127:120]; FI;
VPMAXSB (VEX.256 Encoded Version)
ELSE
(* Repeat operation for 2nd through 31st bytes in source and destination operands *)IF SRC1[255:248] >SRC2[255:248] THEN
DEST[255:248] := SRC1[255:248];
ELSE
DEST[255:248] := SRC2[255:248]; FI;
DEST[MAXVL-1:256] := 0PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maxi mum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
4-314 Vol. 2BVPMAXSB (EVEX Encoded Versions)
i := j * 8IF k1[j] OR *no writemask* THEN
IF SRC1[i+7:i] > SRC2[i+7:i] 
THEN DEST[i+7:i] := SRC1[i+7:i];
ELSE DEST[i+7:i] := SRC2[i+7:i]; 
FI;ELSE 
THEN *DEST[i+7:i] remains unchanged*ELSE ; zeroing-masking
FI
FI;
PMAXSW (128-bit Legacy SSE Version)
IF DEST[15:0] >SRC[15:0] THEN
ELSE
(* Repeat operation for 2nd through 7th words in source and destination operands *)IF DEST[127:112] >SRC[127:112] THEN
DEST[127:112] := DEST[127:112];
ELSE
DEST[127:112] := SRC[127:112]; FI;
VPMAXSW (VEX.128 Encoded Version)
IF SRC1[15:0] > SRC2[15:0] THEN
DEST[15:0] := SRC1[15:0];
ELSE
DEST[15:0] := SRC2[15:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)IF SRC1[127:112] >SRC2[127:112] THEN
DEST[127:112] := SRC1[127:112];
ELSE
DEST[127:112] := SRC2[127:112]; FI;
VPMAXSW (VEX.256 Encoded Version)
ELSE
(* Repeat operation for 2nd through 15th words in source and destination operands *)IF SRC1[255:240] >SRC2[255:240] THEN
DEST[255:240] := SRC1[255:240];
ELSE
DEST[255:240] := SRC2[255:240]; FI;
DEST[MAXVL-1:256] := 0PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-315VPMAXSW (EVEX Encoded Versions)
i := j * 16IF k1[j] OR *no writemask* THEN
IF SRC1[i+15:i] > SRC2[i+15:i] 
THEN DEST[i+15:i] := SRC1[i+15:i];ELSE DEST[i+15:i] := SRC2[i+15:i]; 
FI;ELSE

ELSE
ELSE
ELSE
ELSE
FI;ELSE 
THEN *DEST[i+15:i] remains unchanged*ELSE ; zeroing-masking
FI
FI;
PMAXSD (128-bit Legacy SSE Version)
IF DEST[31:0] >SRC[31:0] THEN
DEST[31:0] := DEST[31:0];
ELSE
DEST[31:0] := SRC[31:0]; FI;
(* Repeat operation for 2nd through 7th words in source and destination operands *)IF DEST[127:96] >SRC[127:96] THEN
DEST[127:96] := DEST[127:96];
ELSE
DEST[127:96] := SRC[127:96]; FI;
VPMAXSD (VEX.128 Encoded Version)
IF SRC1[31:0] > SRC2[31:0] THEN
DEST[31:0] := SRC1[31:0];
ELSE
DEST[31:0] := SRC2[31:0]; FI;
(* Repeat operation for 2nd through 3rd dwor ds in source and destination operands *)
IF SRC1[127:96] > SRC2[127:96] THEN
DEST[127:96] := SRC1[127:96];
ELSE
DEST[127:96] := SRC2[127:96]; FI;
VPMAXSD (VEX.256 Encoded Version)
ELSE
(* Repeat operation for 2nd through 7th dwords in source and destination operands *)IF SRC1[255:224] > SRC2[255:224] THEN
DEST[255:224] := SRC1[255:224];
ELSE
DEST[255:224] := SRC2[255:224]; FI;
4-316 Vol. 2BVPMAXSD (EVEX Encoded Versions)
i := j * 32IF k1[j] OR *no writemask*THEN
THEN 
IF SRC1[i+31:i] > SRC2[31:0] 
THEN DEST[i+31:i] := SRC1[i+31:i];ELSE DEST[i+31:i] := SRC2[31:0]; 
FI;
ELSE 
IF SRC1[i+31:i] > SRC2[i+31:i] 
THEN DEST[i+31:i] := SRC1[i+31:i];ELSE DEST[i+31:i] := SRC2[i+31:i]; 
FI;
FI;ELSE 
FI
FI;
VPMAXSQ (EVEX Encoded Versions)
i := j * 64IF k1[j] OR *no writemask* THEN
THEN 
IF SRC1[i+63:i] > SRC2[63:0] 
THEN DEST[i+63:i] := SRC1[i+63:i];ELSE DEST[i+63:i] := SRC2[63:0]; 
FI;
ELSE 
IF SRC1[i+63:i] > SRC2[i+63:i] 
THEN DEST[i+63:i] := SRC1[i+63:i];ELSE DEST[i+63:i] := SRC2[i+63:i]; 
FI;
FI;ELSE 
THEN DEST[i+63:i] := 0
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-317Intel C/C++ Compiler Intrinsic Equivalent
VPMAXSB __m512i _mm512_max_epi8( __m512i a, __m512i b);
VPMAXSB __m512i _mm512_mask_max_epi8(__m512 i s, __mmask64 k, __m512i a, __m512i b);
VPMAXSB __m512i _mm512_maskz_max_epi8( __mmask64 k, __m512i a, __m512i b);
VPMAXSW __m512i _mm512_max_epi16( __m512i a, __m512i b);VPMAXSW __m512i _mm512_mask_max_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPMAXSW __m512i _mm512_maskz_max_epi16( __mmask32 k, __m512i a, __m512i b);VPMAXSB __m256i _mm256_mask_max_epi8(__m256 i s, __mmask32 k, __m256i a, __m256i b);
VPMAXSB __m256i _mm256_maskz_max_epi8( __mmask32 k, __m256i a, __m256i b);
VPMAXSW __m256i _mm256_mask_max_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMAXSW __m256i _mm256_maskz_max_epi16( __mmask16 k, __m256i a, __m256i b);VPMAXSB __m128i _mm_mask_max _epi8(__m128i s, __mmask16 k,  __m128i a, __m128i b);
VPMAXSB __m128i _mm_maskz_max_epi8( __m mask16 k, __m128i a, __m128i b);
VPMAXSW __m128i _mm_mask_max_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXSW __m128i _mm_maskz_max_epi16( __mmask8 k, __m128i a, __m128i b);
VPMAXSD __m256i _mm256_mask_max_epi32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMAXSD __m256i _mm256_maskz_max_epi32( __mmask16 k, __m256i a, __m256i b);
VPMAXSQ __m256i _mm256_mask_max_epi64(__m256 i s, __mmask8 k, __m256i a, __m256i b);
VPMAXSQ __m256i _mm256_maskz_max_epi64( __mmask8 k, __m256i a, __m256i b);VPMAXSD __m128i _mm_mask_max_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXSD __m128i _mm_maskz_max_epi32( __mmask8 k, __m128i a, __m128i b);VPMAXSQ __m128i _mm_mask_max_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMAXSQ __m128i _mm_maskz_max_epu64( __mmask8 k, __m128i a, __m128i b);VPMAXSD __m512i _mm512_max_epi32( __m512i a, __m512i b);VPMAXSD __m512i _mm512_mask_max_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMAXSD __m512i _mm512_maskz_max_epi32( __mmask16 k, __m512i a, __m512i b);
VPMAXSQ __m512i _mm512_max_epi64( __m512i a, __m512i b);VPMAXSQ __m512i _mm512_mask_max_epi64(__m512 i s, __mmask8 k, __m512i a, __m512i b);
VPMAXSQ __m512i _mm512_maskz_max_epi64( __mmask8 k, __m512i a, __m512i b);(V)PMAXSB __m128i _mm_max_epi8 ( __m128i a, __m128i b);(V)PMAXSW __m128i _mm_max_epi16 ( __m128i a, __m128i b)(V)PMAXSD __m128i _mm_max_epi32 ( __m128i a, __m128i b);VPMAXSB __m256i _mm256_max_epi8 ( __m256i a, __m256i b);VPMAXSW __m256i _mm256_max_epi16 ( __m256i a, __m256i b)VPMAXSD __m256i _mm256_max_epi32 ( __m256i a, __m256i b);PMAXSW:__m64 _mm_max_pi16(__m64 a, __m64 b)
None.
EVEX-encoded VPMAXSD/Q, see Table 2-49, “Type E4 Class Exception Conditions.”
EVEX-encoded VPMAXSB/W, see Except ions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PMAXUB/PMAXUW—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-318 Vol. 2BPMAXUB/PMAXUW—Maximum of Packed Unsigned Integers
Opcode/
Mode 
NP 0F DE /r1
PMAXUB mm1, mm2/m64
NOTES:
ware Developer’s Manual, Volume 2A, and Sect ion 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg -
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V  SSE Compare unsigned byte integers in mm2/m64 and 
mm1 and returns maximum values.
66 0F DE /r
PMAXUB xmm1, xmm2/m128A V/V SSE2 Compare packed unsigned byte integers in xmm1 and 
xmm1.
66 0F 38 3E/r
PMAXUW xmm1, xmm2/m128A V/V SSE4_1 Compare packed unsigned word integers in 
xmm2/m128 and xmm1 and stores maximum packed 
VEX.128.66.0F DE /r
VPMAXUB xmm1, xmm2, xmm3/m128B V/V AVX Compare packed unsigned byte integers in xmm2 and 
VEX.128.66.0F38 3E/r
VPMAXUW xmm1, xmm2, xmm3/m128B V/V AVX Compare packed unsigned word integers in 
xmm3/m128 and xmm2 and store maximum packed values in xmm1.
VEX.256.66.0F DE /r
VPMAXUB ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed unsigned byte integers in ymm2 and 
ymm1.
VEX.256.66.0F38 3E/r
VPMAXUW ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed unsigned word integers in 
ymm3/m256 and ymm2 and store maximum packed 
values in ymm1.
EVEX.128.66.0F.WIG DE /r
VPMAXUB xmm1{k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWCompare packed unsigned byte integers in xmm2 and 
EVEX.256.66.0F.WIG DE /r
VPMAXUB ymm1{k1}{z}, ymm2, 
AVX512BWCompare packed unsigned byte integers in ymm2 and 
EVEX.512.66.0F.WIG DE /r
VPMAXUB zmm1{k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Compare packed unsigned byte integers in zmm2 and 
EVEX.128.66.0F38.WIG 3E /r
VPMAXUW xmm1{k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWCompare packed unsigned word integers in xmm2 
and xmm3/m128 and store packed maximum values in xmm1 under writemask k1.
EVEX.256.66.0F38.WIG 3E /r
VPMAXUW ymm1{k1}{z}, ymm2, 
AVX512BWCompare packed unsigned word integers in ymm2 
and ymm3/m256 and store packed maximum values 
in ymm1 under writemask k1.
EVEX.512.66.0F38.WIG 3E /r
VPMAXUW zmm1{k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Compare packed unsigned word integers in zmm2 
and zmm3/m512 and store packed maximum values 
in zmm1 under writemask k1.PMAXUB/PMAXUW—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-319Instruction Operand Encoding
Performs a SIMD compare of the packed unsigned byte, word  integers in the second source operand and the first 
source operand and returns the maximum value for each pair of integers to the destination operand. 
Legacy SSE version PMAXUB: The source operand can be an  MMX technology register or a 64-bit memory location. 

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a 
ZMM/YMM/XMM register or a 512/256/128-bit memory loca tion. The destination operand is conditionally updated 
based on writemask k1.
Operation
PMAXUB (64-bit Operands)
IF DEST[7:0] > SRC[17:0]) THEN
ELSE
(* Repeat operation for 2nd through 7th by tes in source and destination operands *)
IF DEST[63:56] > SRC[63:56]) THEN
DEST[63:56] := DEST[63:56];
ELSE
DEST[63:56] := SRC[63:56]; FI;
PMAXUB (128-bit Legacy SSE Version)
IF DEST[7:0] >SRC[7:0] THEN
ELSE
DEST[15:0] := SRC[7:0]; FI;
ELSE
DEST[MAXVL-1:128 ] (Unmodified)Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMAXUB/PMAXUW—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-320 Vol. 2BVPMAXUB (VEX.128 Encoded Version)
IF SRC1[7:0] >SRC2[7:0] THEN
ELSE
ELSE
VPMAXUB (VEX.256 Encoded Version)
ELSE
DEST[15:0] := SRC2[7:0]; FI;
ELSE
VPMAXUB (EVEX Encoded Versions)
FI;ELSE 
FI
FI;
PMAXUW (128-bit Legacy SSE Version)
ELSE
ELSE
DEST[MAXVL-1:128] (Unmodified)PMAXUB/PMAXUW—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-321VPMAXUW (VEX.128 Encoded Version)
ELSE
ELSE
VPMAXUW (VEX.256 Encoded Version)
ELSE
ELSE
VPMAXUW (EVEX Encoded Versions)
FI;ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PMAXUB/PMAXUW—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-322 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VPMAXUB __m512i _mm512_max_epu8( __m512i a, __m512i b);
VPMAXUB __m512i _mm512_mask_max_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMAXUB __m512i _mm512_maskz_max_epu8( __mmask64 k, __m512i a, __m512i b);VPMAXUW __m512i _mm512_max_epu16( __m512i a, __m512i b);VPMAXUW __m512i _mm512_mask_max_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPMAXUW __m512i _mm512_maskz_max_epu16( __mmask32 k, __m512i a, __m512i b);VPMAXUB __m256i _mm256_mask_max_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMAXUB __m256i _mm256_maskz_max_epu8( __mmask32 k, __m256i a, __m256i b);VPMAXUW __m256i _mm256_mask_max_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMAXUW __m256i _mm256_maskz_max_epu16( __mmask16 k, __m256i a, __m256i b);VPMAXUB __m128i _mm_mask_max_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMAXUB __m128i _mm_maskz_max_epu8( __mmask16 k, __m128i a, __m128i b);VPMAXUW __m128i _mm_mask_max_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMAXUW __m128i _mm_maskz_max_epu16( __mmask8 k, __m128i a, __m128i b);(V)PMAXUB __m128i _mm_max_epu8 ( __m128i a, __m128i b);(V)PMAXUW __m128i _mm_max_epu16 ( __m128i a, __m128i b)VPMAXUB __m256i _mm256_max_epu8 ( __m256i a, __m256i b);VPMAXUW __m256i _mm256_max_epu16 ( __m256i a, __m256i b);PMAXUB __m64 _mm_max_pu8(__m64 a, __m64 b);
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PMAXUD/PMAXUQ—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-323PMAXUD/PMAXUQ—Maximum of Pa cked Unsigned Integers
Performs a SIMD compare of the packed  unsigned dword or qword integers in the second source operand and the 
first source operand and returns the maximum value for each pair of integers to the destination operand. 
VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register 
or 256-bit memory location. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.Opcode/
Mode 
Feature 
66 0F 38 3F /r
PMAXUD xmm1, xmm2/m128A V/V SSE4_1 Compare packed unsigned dword integers in xmm1 and 
xmm1.
VEX.128.66.0F38.WIG 3F /r
VPMAXUD xmm1, xmm2, xmm3/m128B V/V AVX Compare packed unsigned dword integers in xmm2 and 
VEX.256.66.0F38.WIG 3F /r
VPMAXUD ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed unsigned dword integers in ymm2 and 
ymm1.
EVEX.128.66.0F38.W0 3F /r
VPMAXUD xmm1 {k1}{z}, xmm2, 
AVX512FCompare packed unsigned dword integers in xmm2 and 
values in xmm1 under writemask k1.
EVEX.256.66.0F38.W0 3F /r
VPMAXUD ymm1 {k1}{z}, ymm2, 
AVX512FCompare packed unsigned dword integers in ymm2 and 
ymm3/m256/m32bcst and store packed maximum 
values in ymm1 under writemask k1.
EVEX.512.66.0F38.W0 3F /r
VPMAXUD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstC V/V AVX512F Compare packed unsigned dword integers in zmm2 and 
zmm3/m512/m32bcst and store packed maximum values in zmm1 under writemask k1.
EVEX.128.66.0F38.W1 3F /r
VPMAXUQ xmm1 {k1}{z}, xmm2, 
AVX512FCompare packed unsigned qword integers in xmm2 and 
EVEX.256.66.0F38.W1 3F /r
VPMAXUQ ymm1 {k1}{z}, ymm2, 
AVX512FCompare packed unsigned qword integers in ymm2 and 
EVEX.512.66.0F38.W1 3F /r
VPMAXUQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512F Compare packed unsigned qword integers in zmm2 and 
zmm3/m512/m64bcst and store packed maximum values in zmm1 under writemask k1.

B N/A ModRM:reg (w) VEX.vvvv ModRM:r/m (r) N/A
C Full ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) N/APMAXUD/PMAXUQ—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-324 Vol. 2BEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a 
Operation
PMAXUD (128-bit Legacy SSE Version)
ELSE
ELSE
VPMAXUD (VEX.128 Encoded Version)
ELSE
ELSE
VPMAXUD (VEX.256 Encoded Version)
ELSE
ELSE
DEST[MAXVL-1:256] := 0PMAXUD/PMAXUQ—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-325VPMAXUD (EVEX Encoded Versions)
i := j * 32IF k1[j] OR *no writemask* THEN
THEN 
FI;
ELSE 
FI;
FI;ELSE 
THEN DEST[i+31:i] := 0
FI
FI;
VPMAXUQ (EVEX Encoded Versions)
THEN 
FI;
ELSE 
FI;
FI;ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PMAXUD/PMAXUQ—Maximum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-326 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VPMAXUD __m512i _mm512_max_epu32( __m512i a, __m512i b);
VPMAXUD __m512i _mm512_mask_max_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b);VPMAXUD __m512i _mm512_maskz_max_epu32(  __mmask16 k, __m512i a, __m512i b);
VPMAXUQ __m512i _mm512_max_epu64( __m512i a, __m512i b);VPMAXUQ __m512i _mm512_mask_max_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPMAXUQ __m512i _mm512_maskz_max_epu64( __mmask8 k, __m512i a, __m512i b);VPMAXUD __m256i _mm256_mask_max_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMAXUD __m256i _mm256_maskz_max_epu32(  __mmask16 k, __m256i a, __m256i b);
VPMAXUQ __m256i _mm256_mask_max_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b);VPMAXUQ __m256i _mm256_maskz_max_epu64( __mmask8 k, __m256i a, __m256i b);VPMAXUD __m128i _mm_mask_max _epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXUD __m128i _mm_maskz_max_epu32(  __mmask8 k, __m128i a, __m128i b);
VPMAXUQ __m128i _mm_mask_max_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXUQ __m128i _mm_maskz_max_epu64( __mmask8 k, __m128i a, __m128i b);(V)PMAXUD __m128i _mm_max_epu32 ( __m128i a, __m128i b);VPMAXUD __m256i _mm256_max_epu32 ( __m256i a, __m256i b);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PMINSB/PMINSW—Minimum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-327PMINSB/PMINSW—Minimum of Packed Signed Integers
Mode 
NP 0F EA /r1
PMINSW mm1, mm2/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSE Compare signed word integers in mm2/m64 and mm1 
and return minimum values.
66 0F 38 38 /r
PMINSB xmm1, xmm2/m128A V/V SSE4_1 Compare packed signed byte integers in xmm1 and 
xmm2/m128 and store packed minimum values in 
xmm1.
66 0F EA /r
PMINSW xmm1, xmm2/m128A V/V SSE2 Compare packed signed word integers in xmm2/m128 
and xmm1 and store packed minimum values in xmm1.
VEX.128.66.0F38 38 /r
VPMINSB xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed byte integers in xmm2 and 
xmm3/m128 and store packed minimum values in 
xmm1.
VEX.128.66.0F EA /r
VPMINSW xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed word integers in xmm3/m128 
and xmm2 and return packed minimum values in xmm1.
VEX.256.66.0F38 38 /r
VPMINSB ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed byte integers in ymm2 and 
ymm3/m256 and store packed minimum values in ymm1.
VEX.256.66.0F EA /r
VPMINSW ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed word integers in ymm3/m256 
and ymm2 and return packed minimum values in ymm1.
EVEX.128.66.0F38.WIG 38 /r
VPMINSB xmm1{k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWCompare packed signed byte integers in xmm2 and 
xmm3/m128 and store packed minimum values in xmm1 under writemask k1.
EVEX.256.66.0F38.WIG 38 /r
VPMINSB ymm1{k1}{z}, ymm2, 
AVX512BWCompare packed signed byte integers in ymm2 and 
ymm3/m256 and store packed minimum values in ymm1 
EVEX.512.66.0F38.WIG 38 /r
VPMINSB zmm1{k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Compare packed signed byte integers in zmm2 and 
zmm3/m512 and store packed minimum values in zmm1 
EVEX.128.66.0F.WIG EA /r
VPMINSW xmm1{k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
EVEX.256.66.0F.WIG EA /r
VPMINSW ymm1{k1}{z}, ymm2, 
EVEX.512.66.0F.WIG EA /r
VPMINSW zmm1{k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Compare packed signed  word integers in zmm2 and 
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMINSB/PMINSW—Minimum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
4-328 Vol. 2BDescription
Performs a SIMD compare of the packed signed byte, word , or dword integers in the second source operand and 
the first source operand and returns the minimum value fo r each pair of integers to the destination operand. 
Legacy SSE version PMINSW: The source operand can be an MMX technology register or a 64-bit memory location. 
Operation
PMINSW (64-bit Operands)
IF DEST[15:0] < SRC[15:0] THEN
ELSE
(* Repeat operation for 2nd and 3rd word s in source and destination operands *)
IF DEST[63:48] < SRC[63:48] THEN

Operation
ELSE
ELSE
PMINSB (128-bit Legacy SSE Version)
IF DEST[7:0] < SRC[7:0] THEN
ELSE
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)IF DEST[127:120] < SRC[127:120] THEN
ELSE
VPMINSB (VEX.128 Encoded Version)
IF SRC1[7:0] < SRC2[7:0] THEN
ELSE
(* Repeat operation for 2nd through 15th bytes in source and destination operands *)IF SRC1[127:120] < SRC2[127:120] THEN
ELSE
DEST[MAXVL-1:128] := 0PMINSB/PMINSW—Minimum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-329VPMINSB (VEX.256 Encoded Version)
ELSE
(* Repeat operation for 2nd through 31st bytes in source and destination operands *)IF SRC1[255:248] < SRC2[255:248] THEN
ELSE
VPMINSB (EVEX Encoded Versions)
IF SRC1[i+7:i] < SRC2[i+7:i] 
FI;ELSE 
FI
FI;
PMINSW (128-bit Legacy SSE Version)
ELSE
(* Repeat operation for 2nd through 7th words in source and destination operands *)IF DEST[127:112] < SRC[127:112] THEN
ELSE
VPMINSW (VEX.128 Encoded Version)
IF SRC1[15:0] < SRC2[15:0] THEN
ELSE
(* Repeat operation for 2nd through 7th words in source and destination operands *)IF SRC1[127:112] < SRC2[127:112] THEN
ELSE
4-330 Vol. 2BVPMINSW (VEX.256 Encoded Version)
ELSE
(* Repeat operation for 2nd through 15th words in source and destination operands *)IF SRC1[255:240] < SRC2[255:240] THEN
ELSE
VPMINSW (EVEX Encoded Versions)
IF SRC1[i+15:i] < SRC2[i+15:i] 
FI;ELSE 
FI
FI;
VPMINSB __m512i _mm512_min_epi8( __m512i a, __m512i b);VPMINSB __m512i _mm512_mask_min_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);VPMINSB __m512i _mm512_maskz_min_epi8( __mmask64 k, __m512i a, __m512i b);
VPMINSW __m512i _mm512_min_epi16( __m512i a, __m512i b);VPMINSW __m512i _mm512_mask_min_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPMINSW __m512i _mm512_maskz_min_epi16( __mmask32 k, __m512i a, __m512i b);VPMINSB __m256i _mm256_mask_min_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);VPMINSB __m256i _mm256_maskz_min_epi8( __mmask32 k, __m256i a, __m256i b);
VPMINSW __m256i _mm256_mask_min_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMINSW __m256i _mm256_maskz_min_epi16( __mmask16 k, __m256i a, __m256i b);VPMINSB __m128i _mm_mask_min_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);VPMINSB __m128i _mm_maskz_min_epi8( __mmask16 k, __m128i a, __m128i b);
VPMINSW __m128i _mm_mask_min _epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINSW __m128i _mm_maskz_min_epi16( __mmask8 k, __m128i a, __m128i b);(V)PMINSB __m128i _mm_min_epi8 ( __m128i a, __m128i b);(V)PMINSW __m128i _mm_min_epi16 ( __m128i a, __m128i b)VPMINSB __m256i _mm256_min_epi8 ( __m256i a, __m256i b);VPMINSW __m256i _mm256_min_epi16 ( __m256i a, __m256i b)PMINSW__m64 _mm_min_pi16 (__m64 a, __m64 b)PMINSB/PMINSW—Minimum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-331SIMD Floating-Point Exceptions
None.
#MF (64-bit operations only) If there is a pending x87 FPU exception.PMINSD/PMINSQ—Minimum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
4-332 Vol. 2BPMINSD/PMINSQ—Minimum of Packed Signed Integers
Performs a SIMD compare of the packed signed dword or qw ord integers in the second source operand and the first 
source operand and returns the minimum value for each pair of integers to the destination operand. 
first source and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding destination 
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.Opcode/
n64/32 bit 
Mode 
Feature 
66 0F 38 39 /r
PMINSD xmm1, xmm2/m128A V/V SSE4_1 Compare packed signed dword integers in xmm1 and 
xmm2/m128 and store packed minimum values in xmm1.
VEX.128.66.0F38.WIG 39 /r
VPMINSD xmm1, xmm2, xmm3/m128B V/V AVX Compare packed signed dword integers in xmm2 and 
xmm3/m128 and store packed minimum values in xmm1.
VEX.256.66.0F38.WIG 39 /r
VPMINSD ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed signed dword integers in ymm2 and 
ymm3/m128 and store packed minimum values in ymm1.
EVEX.128.66.0F38.W0 39 /r
VPMINSD xmm1 {k1}{z}, xmm2, 
xmm3/m128 and store packed minimum values in xmm1 
EVEX.256.66.0F38.W0 39 /r
VPMINSD ymm1 {k1}{z}, ymm2, 
EVEX.512.66.0F38.W0 39 /r
VPMINSD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstC V/V AVX512F Compare packed signed dword integers in zmm2 and 
zmm3/m512/m32bcst and store packed minimum values in zmm1 under writemask k1.
EVEX.128.66.0F38.W1 39 /r
VPMINSQ xmm1 {k1}{z}, xmm2, 
EVEX.256.66.0F38.W1 39 /r
VPMINSQ ymm1 {k1}{z}, ymm2, 
EVEX.512.66.0F38.W1 39 /r
VPMINSQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512F Compare packed signed qword integers in zmm2 and 
zmm3/m512/m64bcst and store packed minimum values in zmm1 under writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMINSD/PMINSQ—Minimum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-333Operation
PMINSD (128-bit Legacy SSE Version)
IF DEST[31:0] < SRC[31:0] THEN
ELSE
(* Repeat operation for 2nd through 7th words in source and destination operands *)IF DEST[127:96] < SRC[127:96] THEN
ELSE
VPMINSD (VEX.128 Encoded Version)
IF SRC1[31:0] < SRC2[31:0] THEN
ELSE
IF SRC1[127:96] < SRC2[127:96] THEN

ELSE
ELSE
ELSE
ELSE
VPMINSD (VEX.256 Encoded Version)
ELSE
(* Repeat operation for 2nd through 7th dwords in source and destination operands *)IF SRC1[255:224] < SRC2[255:224] THEN
ELSE
DEST[MAXVL-1:256] := 0PMINSD/PMINSQ—Minimum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
4-334 Vol. 2BVPMINSD (EVEX Encoded Versions)
THEN 
IF SRC1[i+31:i] < SRC2[31:0] 
FI;
ELSE 
IF SRC1[i+31:i] < SRC2[i+31:i] 
FI;
FI;ELSE 
FI
FI;
VPMINSQ (EVEX Encoded Versions)
THEN 
IF SRC1[i+63:i] < SRC2[63:0] 
FI;
ELSE 
IF SRC1[i+63:i] < SRC2[i+63:i] 
FI;
FI;ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PMINSD/PMINSQ—Minimum of Packed Signed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-335Intel C/C++ Compiler Intrinsic Equivalent
VPMINSD __m512i _mm512_min_epi32( __m512i a, __m512i b);
VPMINSD __m512i _mm512_mask_min_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);VPMINSD __m512i _mm512_maskz_min_epi32( __mmask16 k, __m512i a, __m512i b);VPMINSQ __m512i _mm512_min_epi64( __m512i a, __m512i b);VPMINSQ __m512i _mm512_mask_min_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPMINSQ __m512i _mm512_maskz_min_epi64( __mmask8 k, __m512i a, __m512i b);VPMINSD __m256i _mm256_mask_min_epi32(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMINSD __m256i _mm256_maskz_min_epi32( __mmask16 k, __m256i a, __m256i b);VPMINSQ __m256i _mm256_mask_min_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);VPMINSQ __m256i _mm256_maskz_min_epi64( __mmask8 k, __m256i a, __m256i b);VPMINSD __m128i _mm_mask_min_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMINSD __m128i _mm_maskz_min_epi32( __mmask8 k, __m128i a, __m128i b);VPMINSQ __m128i _mm_mask_min_epi64(__m128i  s, __mmask8 k, __m128i a, __m128i b);
VPMINSQ __m128i _mm_maskz_min_epu64( __mmask8 k, __m128i a, __m128i b);(V)PMINSD __m128i _mm_min_epi32 ( __m128i a, __m128i b);VPMINSD __m256i _mm256_min_epi32 (__m256i a, __m256i b);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PMINUB/PMINUW—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-336 Vol. 2BPMINUB/PMINUW—Minimum of Packed Unsigned Integers
Opcode/
Mode 
NP 0F DA /r1
PMINUB mm1, mm2/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSE Compare unsigned byte integers in mm2/m64 and 
mm1 and returns minimum values.
66 0F DA /r
PMINUB xmm1, xmm2/m128A V/V SSE2 Compare packed unsigned byte integers in xmm1 and 
xmm1.
66 0F 38 3A/r
PMINUW xmm1, xmm2/m128A V/V SSE4_1 Compare packed unsigned word integers in 
xmm2/m128 and xmm1 and store packed minimum 
VEX.128.66.0F DA /r
VPMINUB xmm1, xmm2, xmm3/m128B V/V AVX Compare packed unsigned byte integers in xmm2 and 
VEX.128.66.0F38 3A/r
VPMINUW xmm1, xmm2, xmm3/m128B V/V AVX Compare packed unsigned word integers in 
xmm3/m128 and xmm2 and return packed minimum values in xmm1.
VEX.256.66.0F DA /r
VPMINUB ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed unsigned byte integers in ymm2 and 
ymm3/m256 and store packed minimum values in 
ymm1.
VEX.256.66.0F38 3A/r
VPMINUW ymm1, ymm2, ymm3/m256B V/V AVX2 Compare packed unsigned word integers in 
ymm3/m256 and ymm2 and return packed minimum 
EVEX.128.66.0F DA /r
VPMINUB xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
EVEX.256.66.0F DA /r
VPMINUB ymm1 {k1}{z}, ymm2, 
EVEX.512.66.0F DA /r
VPMINUB zmm1 {k1}{z}, zmm2, 
zmm3/m512 and store packed minimum values in 
EVEX.128.66.0F38 3A/r
VPMINUW xmm1{k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWCompare packed unsigned word integers in 
xmm3/m128 and xmm2 and return packed minimum values in xmm1 under writemask k1.
EVEX.256.66.0F38 3A/r
VPMINUW ymm1{k1}{z}, ymm2, 
EVEX.512.66.0F38 3A/r
VPMINUW zmm1{k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Compare packed unsigned word integers in 
zmm3/m512 and zmm2 and return packed minimum 
values in zmm1 under writemask k1.PMINUB/PMINUW—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-337Instruction Operand Encoding
Performs a SIMD compare of the packed unsigned byte or wo rd integers in the second source operand and the first 
Legacy SSE version PMINUB: The source operand can be an  MMX technology register or a 64-bit memory location. 
Operation
PMINUB (64-bit Operands)
IF DEST[7:0] < SRC[17:0] THEN
ELSE
IF DEST[63:56] < SRC[63:56] THEN
ELSE
PMINUB (128-bit Operands)
ELSE
ELSE
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/APMINUB/PMINUW—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-338 Vol. 2BVPMINUB (VEX.128 Encoded Version)
ELSE
ELSE
VPMINUB (VEX.256 Encoded Version)
ELSE
ELSE

ELSE
ELSE
ELSE
ELSE
ELSE
VPMINUB (EVEX Encoded Versions)
FI;ELSE 
FI
FI;
PMINUW (128-bit Operands)
ELSE
ELSE
DEST[MAXVL-1:128] (Unmodified)PMINUB/PMINUW—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-339VPMINUW (VEX.128 Encoded Version)
ELSE
ELSE
VPMINUW (VEX.256 Encoded Version)
ELSE
ELSE
VPMINUW (EVEX Encoded Versions)
FI;ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PMINUB/PMINUW—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-340 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VPMINUB __m512i _mm512_min_epu8( __m512i a, __m512i b);
VPMINUB __m512i _mm512_mask_min_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);VPMINUB __m512i _mm512_maskz_min_epu8(  __mmask64 k, __m512i a, __m512i b);
VPMINUW __m512i _mm512_min_epu16( __m512i a, __m512i b);VPMINUW __m512i _mm512_mask_min_epu16(__m512i  s, __mmask32 k, __m512i a, __m512i b);
VPMINUW __m512i _mm512_maskz_min_epu16 ( __mmask32 k, __m512i a, __m512i b);
VPMINUB __m256i _mm256_mask_min_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);VPMINUB __m256i _mm256_maskz_min_epu8(  __mmask32 k, __m256i a, __m256i b);
VPMINUW __m256i _mm256_mask_min_epu16(__m256i  s, __mmask16 k, __m256i a, __m256i b);
VPMINUW __m256i _mm256_maskz_min_epu16 ( __mmask16 k, __m256i a, __m256i b);
VPMINUB __m128i _mm_mask_min _epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMINUB __m128i _mm_maskz_min_epu8( __mmask16 k, __m128i a, __m128i b);VPMINUW __m128i _mm_mask_min_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUW __m128i _mm_maskz_min_epu16( __mmask8 k, __m128i a, __m128i b);(V)PMINUB __m128i _mm_min_epu8 ( __m128i a, __m128i b)(V)PMINUW __m128i _mm_min_epu16 ( __m128i a, __m128i b);VPMINUB __m256i _mm256_min_epu8 ( __m256i a, __m256i b)VPMINUW __m256i _mm256_min_epu16 ( __m256i a, __m256i b);PMINUB __m64 _m_min_pu8 (__m64 a, __m64 b)
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PMINUD/PMINUQ—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-341PMINUD/PMINUQ—Minimum of Packed Unsigned Integers
Performs a SIMD compare of the packed unsigned dword/qw ord integers in the second source operand and the first 
first source and destination operands are YMM registers.  Bits (MAXVL-1:256) of th e corresponding destination 
register are zeroed.Opcode/
n64/32 bit 
Mode 
Feature 
66 0F 38 3B /r
PMINUD xmm1, xmm2/m128A V/V SSE4_1 Compare packed unsigned dword integers in xmm1 and 
VEX.128.66.0F38.WIG 3B /r
VPMINUD xmm1, xmm2, 
xmm3/m128B V/V AVX Compare packed unsigned dword integers in xmm2 and 
VEX.256.66.0F38.WIG 3B /r
VPMINUD ymm1, ymm2, 
ymm3/m256B V/V AVX2 Compare packed unsigned dword integers in ymm2 and 
EVEX.128.66.0F38.W0 3B /r
VPMINUD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV / V A V X 5 1 2 V L
xmm3/m128/m32bcst and store packed minimum values in xmm1 under writemask k1.
EVEX.256.66.0F38.W0 3B /r
VPMINUD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV / V A V X 5 1 2 V L
ymm3/m256/m32bcst and store packed minimum values in ymm1 under writemask k1.
EVEX.512.66.0F38.W0 3B /r
VPMINUD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512F Compare packed unsigned dword integers in zmm2 and 
zmm3/m512/m32bcst and store packed minimum values in 
EVEX.128.66.0F38.W1 3B /r
VPMINUQ xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcst and store packed minimum values in 
EVEX.256.66.0F38.W1 3B /r
VPMINUQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV / V A V X 5 1 2 V L
ymm3/m256/m64bcst and store packed minimum values in ymm1 under writemask k1.
EVEX.512.66.0F38.W1 3B /r
VPMINUQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Compare packed unsigned qword integers in zmm2 and 
zmm3/m512/m64bcst and store packed minimum values in 
CF u l l M o d R M : r e g  ( w )E V E X . vvvv (r) ModRM:r/m (r) N/APMINUD/PMINUQ—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-342 Vol. 2BEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a 
Operation
PMINUD (128-bit Legacy SSE Version)
PMINUD instruction for 128-bit operands:
ELSE
ELSE
VPMINUD (VEX.128 Encoded Version)
VPMINUD instruction for 128-bit operands:
ELSE
ELSE
VPMINUD (VEX.256 Encoded Version)
ELSE
ELSE
DEST[MAXVL-1:256] := 0PMINUD/PMINUQ—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-343VPMINUD (EVEX Encoded Versions)
THEN 
FI;
ELSE 
FI;

ELSE
ELSE
ELSE
THEN 
FI;
ELSE 
FI;
FI;ELSE 
FI
FI;
VPMINUQ (EVEX Encoded Versions)
THEN 
FI;
ELSE 
FI;
FI;ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PMINUD/PMINUQ—Minimum of Packed Unsigned IntegersINSTRUCTION SET REFERENCE, M-U
4-344 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VPMINUD __m512i _mm512_min_epu32( __m512i a, __m512i b);
VPMINUD __m512i _mm512_mask_min_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b);VPMINUD __m512i _mm512_maskz_min_epu32( __mmask16 k, __m512i a, __m512i b);VPMINUQ __m512i _mm512_min_epu64( __m512i a, __m512i b);VPMINUQ __m512i _mm512_mask_min_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPMINUQ __m512i _mm512_maskz_min_epu64 ( __mmask8 k, __m512i a, __m512i b);
VPMINUD __m256i _mm256_mask_min_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMINUD __m256i _mm256_maskz_min_epu32( __mmask16 k, __m256i a, __m256i b);VPMINUQ __m256i _mm256_mask_min_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b);VPMINUQ __m256i _mm256_maskz_min_epu64 ( __mmask8 k, __m256i a, __m256i b);
VPMINUD __m128i _mm_mask_min_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUD __m128i _mm_maskz_min_epu32( __mmask8 k, __m128i a, __m128i b);VPMINUQ __m128i _mm_mask_min_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUQ __m128i _mm_maskz_min_epu64( __mmask8 k, __m128i a, __m128i b);(V)PMINUD __m128i _mm_min_epu32 ( __m128i a, __m128i b);VPMINUD __m256i _mm256_min_epu32 ( __m256i a, __m256i b);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PMOVMSKB—Move Byte MaskINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-345PMOVMSKB—Move Byte Mask
Creates a mask made up of the most significant bit of each  byte of the source operand (second operand) and stores 
the result in the low byte or word of the destination operand (first operand).
The byte mask is 8 bits for 64-bit source operand, 16 bits  for 128-bit source operand and 32 bits for 256-bit source 
operand. The destination operand is a general-purpose register. 
Legacy SSE version: The source operand is an MMX technology register.128-bit Legacy SSE version: The source operand is an XMM register.
VEX.128 encoded version: The source operand is an XMM register.
VEX.256 encoded version: The source operand is a YMM register.Note: VEX.vvvv is reserved and must be 1111b. 
Operation
PMOVMSKB (With 64-bit Source Operand and r32)
r32[0] := SRC[7];r32[1] := SRC[15];(* Repeat operation for bytes 2 through 6 *)r32[7] := SRC[63]; r32[31:8] := ZERO_FILL;Opcode/
Mode 
Feature 
NP 0F D7 /r
1
PMOVMSKB reg, mm
NOTES:
Registers,” in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.RM V/V SSE Move a byte mask of mm to reg. The upper 
bits of r32 or r64 are zeroed
66 0F D7 /r
PMOVMSKB reg, xmmRM V/V SSE2 Move a byte mask of xmm to reg. The upper 
VEX.128.66.0F.WIG D7 /r
VPMOVMSKB reg, xmm1RM V/V AVX Move a byte mask of  xmm1 to reg. The upper 
bits of r32 or r64 are filled with zeros.
VEX.256.66.0F.WIG D7 /r
VPMOVMSKB reg, ymm1RM V/V AVX2 Move a 32-bit mask of ymm1 to reg. The 
upper bits of r64 are filled with zeros.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/APMOVMSKB—Move Byte MaskINSTRUCTION SET REFERENCE, M-U
4-346 Vol. 2B(V)PMOVMSKB (With 128-bit Source Operand and r32)
r32[0] := SRC[7];r32[1] := SRC[15];(* Repeat operation for bytes 2 through 14 *)r32[15] := SRC[127]; r32[31:16] := ZERO_FILL;
VPMOVMSKB (With 256-bit Source Operand and r32)
r32[0] := SRC[7];r32[1] := SRC[15];(* Repeat operation for bytes 3rd through 31*)r32[31] := SRC[255];
PMOVMSKB (With 64-bit Source Operand and r64)
r64[0] := SRC[7];r64[1] := SRC[15];(* Repeat operation for bytes 2 through 6 *)r64[7] := SRC[63]; r64[63:8] := ZERO_FILL;
(V)PMOVMSKB (With 128-bit Source Operand and r64)
r64[0] := SRC[7];r64[1] := SRC[15];(* Repeat operation for bytes 2 through 14 *)r64[15] := SRC[127]; r64[63:16] := ZERO_FILL;
VPMOVMSKB (With 256-bit Source Operand and r64)
r64[0] := SRC[7];r64[1] := SRC[15];(* Repeat operation for bytes 2 through 31*)r64[31] := SRC[255];r64[63:32] := ZERO_FILL;
PMOVMSKB int _mm_movemask_pi8(__m64 a)
(V)PMOVMSKB int _mm_move mask_epi8 ( __m128i a)
VPMOVMSKB int _mm256_movemask_epi8 ( __m256i a)
None.
None.
#UD If VEX.vvvv ≠ 1111B.PMOVSX—Packed Move With Sign ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-347PMOVSX—Packed Move With Sign Extend 
Opcode/
Mode 
66 0f 38 20 /r
PMOVSXBW xmm1, xmm2/m64A V/V SSE4_1 Sign extend 8 packed 8-bit integers in the low 8 bytes of 
xmm2/m64 to 8 packed 16-bit integers in xmm1.
66 0f 38 21 /r
PMOVSXBD xmm1, xmm2/m32A V/V SSE4_1 Sign extend 4 packed 8-bit integers in the low 4 bytes of 
xmm2/m32 to 4 packed 32-bit integers in xmm1.
66 0f 38 22 /r
PMOVSXBQ xmm1, xmm2/m16A V/V SSE4_1 Sign extend 2 packed 8-bit integers in the low 2 bytes of 
xmm2/m16 to 2 packed 64-bit integers in xmm1.
66 0f 38 23/r
PMOVSXWD xmm1, xmm2/m64A V/V SSE4_1 Sign extend 4 packed 16-bit integers in the low 8 bytes 
of xmm2/m64 to 4 packed 32-bit integers in xmm1.
66 0f 38 24 /r
PMOVSXWQ xmm1, xmm2/m32A V/V SSE4_1 Sign extend 2 packed 16-bit integers in the low 4 bytes 
of xmm2/m32 to 2 packed 64-bit integers in xmm1.
66 0f 38 25 /r
PMOVSXDQ xmm1, xmm2/m64A V/V SSE4_1 Sign extend 2 packed 32-bit integers in the low 8 bytes 
of xmm2/m64 to 2 packed 64-bit integers in xmm1.
VEX.128.66.0F38.WIG 20 /r
VPMOVSXBW xmm1, xmm2/m64A V/V AVX Sign extend 8 packed 8-bit integers in the low 8 bytes of 
VEX.128.66.0F38.WIG 21 /r
VPMOVSXBD xmm1, xmm2/m32A V/V AVX Sign extend 4 packed 8-bit integers in the low 4 bytes of 
VEX.128.66.0F38.WIG 22 /r
VPMOVSXBQ xmm1, xmm2/m16A V/V AVX Sign extend 2 packed 8-bit integers in the low 2 bytes of 
VEX.128.66.0F38.WIG 23 /r
VPMOVSXWD xmm1, xmm2/m64A V/V AVX Sign extend 4 packed 16-bit integers in the low 8 bytes 
VEX.128.66.0F38.WIG 24 /r
VPMOVSXWQ xmm1, xmm2/m32A V/V AVX Sign extend 2 packed 16-bit integers in the low 4 bytes 
VEX.128.66.0F38.WIG 25 /r
VPMOVSXDQ xmm1, xmm2/m64A V/V AVX Sign extend 2 packed 32-bit integers in the low 8 bytes 
VEX.256.66.0F38.WIG 20 /r
VPMOVSXBW ymm1, xmm2/m128A V/V AVX2 Sign extend 16 packed 8-bit integers in xmm2/m128 to 
16 packed 16-bit integers in ymm1.
VEX.256.66.0F38.WIG 21 /r
VPMOVSXBD ymm1, xmm2/m64A V/V AVX2 Sign extend 8 packed 8-bit integers in the low 8 bytes of 
xmm2/m64 to 8 packed 32-bit integers in ymm1.
VEX.256.66.0F38.WIG 22 /r
VPMOVSXBQ ymm1, xmm2/m32A V/V AVX2 Sign extend 4 packed 8-bit integers in the low 4 bytes of 
xmm2/m32 to 4 packed 64-bit integers in ymm1.
VEX.256.66.0F38.WIG 23 /r
VPMOVSXWD ymm1, xmm2/m128A V/V AVX2 Sign extend 8 packed 16-b it integers in the low 16 bytes 
of xmm2/m128 to 8 packed 32-bit integers in ymm1.
VEX.256.66.0F38.WIG 24 /r
VPMOVSXWQ ymm1, xmm2/m64A V/V AVX2 Sign extend 4 packed 16-bit integers in the low 8 bytes 
of xmm2/m64 to 4 packed 64-bit integers in ymm1.
VEX.256.66.0F38.WIG 25 /r
VPMOVSXDQ ymm1, xmm2/m128A V/V AVX2 Sign extend 4 packed 32-b it integers in the low 16 bytes 
of xmm2/m128 to 4 packed 64-bit integers in ymm1.
EVEX.128.66.0F38.WIG 20 /r
VPMOVSXBW xmm1 {k1}{z}, 
xmm2/m64B V/V AVX512VL
AVX512BWSign extend 8 packed 8-bit integers in xmm2/m64 to 8 
packed 16-bit integers in zmm1.
EVEX.256.66.0F38.WIG 20 /r
VPMOVSXBW ymm1 {k1}{z},

VPMOVSXBW ymm1 {k1}{z}, 
AVX512BWSign extend 16 packed 8-bit integers in xmm2/m128 to 
EVEX.512.66.0F38.WIG 20 /r
VPMOVSXBW zmm1 {k1}{z}, 
ymm2/m256B V/V AVX512BW Sign extend 32 packed 8-bit integers in ymm2/m256 to 
32 packed 16-bit in tegers in zmm1.PMOVSX—Packed Move With Sign ExtendINSTRUCTION SET REFERENCE, M-U
4-348 Vol. 2BEVEX.128.66.0F38.WIG 21 /r
VPMOVSXBD xmm1 {k1}{z}, 
xmm2/m32CV / V A V X 5 1 2 V L
AVX512FSign extend 4 packed 8-bit in tegers in the low 4 bytes of 
xmm2/m32 to 4 packed 32-bit integers in xmm1 subject 
to writemask k1.
EVEX.256.66.0F38.WIG 21 /r
VPMOVSXBD ymm1 {k1}{z}, xmm2/m64CV / V A V X 5 1 2 V L
AVX512FSign extend 8 packed 8-bit in tegers in the low 8 bytes of 
xmm2/m64 to 8 packed 32-bit integers in ymm1 subject to writemask k1.
EVEX.512.66.0F38.WIG 21 /r
VPMOVSXBD zmm1 {k1}{z}, 
xmm2/m128C V/V AVX512F Sign extend 16 packed 8- bit integers in the low 16 bytes 
of xmm2/m128 to 16 packed 32-bit integers in zmm1 
EVEX.128.66.0F38.WIG 22 /r
VPMOVSXBQ xmm1 {k1}{z}, 
xmm2/m16DV / V A V X 5 1 2 V L
AVX512FSign extend 2 packed 8-bit in tegers in the low 2 bytes of 
xmm2/m16 to 2 packed 64-bit integers in xmm1 subject 
EVEX.256.66.0F38.WIG 22 /r
VPMOVSXBQ ymm1 {k1}{z}, 
xmm2/m32DV / V A V X 5 1 2 V L
xmm2/m32 to 4 packed 64-bit integers in ymm1 subject 
EVEX.512.66.0F38.WIG 22 /r
VPMOVSXBQ zmm1 {k1}{z}, xmm2/m64D V/V AVX512F Sign extend 8 packed 8-bi t integers in the low 8 bytes of 
xmm2/m64 to 8 packed 64-bit integers in zmm1 subject to writemask k1.
EVEX.128.66.0F38.WIG 23 /r
VPMOVSXWD xmm1 {k1}{z}, 
AVX512FSign extend 4 packed 16-bit integers in the low 8 bytes 
of ymm2/mem to 4 packed 32-bit integers in xmm1 
EVEX.256.66.0F38.WIG 23 /r
VPMOVSXWD ymm1 {k1}{z}, 
AVX512FSign extend 8 packed 16-bit integers in the low 16 bytes 
of ymm2/m128 to 8 packed 32-bit integers in ymm1 
EVEX.512.66.0F38.WIG 23 /r
VPMOVSXWD zmm1 {k1}{z}, ymm2/m256B V/V AVX512F Sign extend 16 packed 16-bit integers in the low 32 
bytes of ymm2/m256 to 16 pa cked 32-bit integers in 
zmm1 subject to writemask k1. 
EVEX.128.66.0F38.WIG 24 /r
VPMOVSXWQ xmm1 {k1}{z}, 
AVX512FSign extend 2 packed 16-bit integers in the low 4 bytes 
of xmm2/m32 to 2 packed 64-bit integers in xmm1 
EVEX.256.66.0F38.WIG 24 /r
VPMOVSXWQ ymm1 {k1}{z}, 
xmm2/m64CV / V A V X 5 1 2 V L
of xmm2/m64 to 4 packed 64-bit integers in ymm1 
EVEX.512.66.0F38.WIG 24 /r
VPMOVSXWQ zmm1 {k1}{z}, xmm2/m128C V/V AVX512F Sign extend 8 packed 16-bit integers in the low 16 bytes 
of xmm2/m128 to 8 packed 64-bit integers in zmm1 subject to writemask k1.
EVEX.128.66.0F38.W0 25 /r
VPMOVSXDQ xmm1 {k1}{z}, 
AVX512FSign extend 2 packed 32-bit integers in the low 8 bytes 
of xmm2/m64 to 2 packed 64-bit integers in zmm1 using 
EVEX.256.66.0F38.W0 25 /r
VPMOVSXDQ ymm1 {k1}{z}, 
AVX512FSign extend 4 packed 32-bit integers in the low 16 bytes 
of xmm2/m128 to 4 packed 64-bit integers in zmm1 
EVEX.512.66.0F38.W0 25 /r
VPMOVSXDQ zmm1 {k1}{z}, ymm2/m256B V/V AVX512F Sign extend 8 packed 32-bit integers in the low 32 bytes 
of ymm2/m256 to 8 packed 64-bit integers in zmm1 using writemask k1. Opcode/
Mode 
Feature FlagDescriptionPMOVSX—Packed Move With Sign ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-349Instruction Operand Encoding
Legacy and VEX encoded versions: Packed  byte, word, or dword integers in the low bytes of the source operand 
(second operand) are sign extended to word, dword, or qu adword integers and stored in packed signed bytes the 
VEX.128 and EVEX.128 encoded versions: Bits (MAXVL-1:128) of the corresponding destination register are 
zeroed.
VEX.256 and EVEX.256 encoded versions: Bits (MAXVL-1:256) of the corresponding destination register are 
zeroed. 
EVEX encoded versions: Packed byte, word or dword intege rs starting from the low bytes of the source operand 
(second operand) are sign extended to word, dword or qu adword integers and stored to the destination operand 
under the writemask. The destination register is XMM, YMM or ZMM Register.
Operation
Packed_Sign_Extend_BYT E_to_WORD(DEST, SRC)
DEST[15:0] := SignExtend(SRC[7:0]);DEST[31:16] := SignExtend(SRC[15:8]);DEST[47:32] := SignExtend(SRC[23:16]);DEST[63:48] := SignExtend(SRC[31:24]);DEST[79:64] := SignExtend(SRC[39:32]);DEST[95:80] := SignExtend(SRC[47:40]);DEST[111:96] := SignExtend(SRC[55:48]);DEST[127:112] := SignExtend(SRC[63:56]);
Packed_Sign_Extend_BYT E_to_DWORD(DEST, SRC)
DEST[31:0] := SignExtend(SRC[7:0]);DEST[63:32] := SignExtend(SRC[15:8]);DEST[95:64] := SignExtend(SRC[23:16]);DEST[127:96] := SignExtend(SRC[31:24]);
Packed_Sign_Extend_BYTE_to_QWORD(DEST, SRC)
DEST[63:0] := SignExtend(SRC[7:0]);DEST[127:64] := SignExtend(SRC[15:8]);
Packed_Sign_Extend_WORD_to_DWORD(DEST, SRC)
DEST[31:0] := SignExtend(SRC[15:0]);DEST[63:32] := SignExtend(SRC[31:16]);DEST[95:64] := SignExtend(SRC[47:32]);DEST[127:96] := SignExtend(SRC[63:48]);
Packed_Sign_Extend_WORD_to_QWORD(DEST, SRC)
DEST[63:0] := SignExtend(SRC[15:0]);DEST[127:64] := SignExtend(SRC[31:16]);Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
B Half Mem ModRM:reg (w) ModRM:r/m (r) N/A N/A
C Quarter Mem ModRM:reg (w) ModRM:r/m (r) N/A N/A
D Eighth Mem ModRM:reg (w) ModRM:r/m (r) N/A N/APMOVSX—Packed Move With Sign ExtendINSTRUCTION SET REFERENCE, M-U
4-350 Vol. 2BPacked_Sign_Extend_DWORD_to_QWORD(DEST, SRC)
DEST[63:0] := SignExtend(SRC[31:0]);DEST[127:64] := SignExtend(SRC[63:32]);
VPMOVSXBW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)Packed_Sign_Extend_BYTE_to_WOR D(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[255:128], SRC[127:64])
Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[383:256], SRC[191:128])Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[511:384], SRC[255:192])
THEN DEST[i+15:i] := TEMP_DEST[i+15:i]ELSE 
FI
FI;
VPMOVSXBD (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)Packed_Sign_Extend_BYTE_to_DWO RD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
Packed_Sign_Extend_BYTE_to_DWORD (TMP_DEST[255:128], SRC[63:32])
Packed_Sign_Extend_BYTE_to_DWORD (TMP_DEST[383:256], SRC[95:64])
Packed_Sign_Extend_BYTE_to_DWORD (TMP_DEST[511:384], SRC[127:96])
THEN DEST[i+31:i] := TEMP_DEST[i+31:i]ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0PMOVSX—Packed Move With Sign ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-351VPMOVSXBQ (EVEX Encoded Versions)
Packed_Sign_Extend_BYTE_to_QWO RD(TMP_DEST[127:0], SRC[15:0])
IF VL >= 256
Packed_Sign_Extend_BYTE_to_QWORD (TMP_DEST[255:128], SRC[31:16])
Packed_Sign_Extend_BYTE_to_QWORD (TMP_DEST[383:256], SRC[47:32])
Packed_Sign_Extend_BYTE_to_QWORD (TMP_DEST[511:384], SRC[63:48])
THEN DEST[i+63:i] := TEMP_DEST[i+63:i]ELSE 
FI
FI;
VPMOVSXWD (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)Packed_Sign_Extend_WORD_to_DWO RD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Sign_Extend_WORD_to_DWORD (TMP_DEST[255:128], SRC[127:64])
Packed_Sign_Extend_WORD_to_DWORD (TMP_DEST[383:256], SRC[191:128])
Packed_Sign_Extend_WORD_to_DWORD (TMP_DEST[511:384], SRC[256:192])
FI
FI;
4-352 Vol. 2BVPMOVSXWQ (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)Packed_Sign_Extend_WORD_to_QWO RD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256

FI
FI;
IF VL >= 256
FI
FI;
IF VL >= 256
Packed_Sign_Extend_WORD_to_QWORD (TMP_DEST[255:128], SRC[63:32])
Packed_Sign_Extend_WORD_to_QWORD (TMP_DEST[383:256], SRC[95:64])
Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[511:384], SRC[127:96])
FI
FI;
VPMOVSXDQ (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)Packed_Sign_Extend_DWORD_to_QWOR D(TEMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Sign_Extend_DWORD_to_QWORD( TEMP_DEST[255:128], SRC[127:64])
Packed_Sign_Extend_DWORD_to_QWORD( TEMP_DEST[383:256], SRC[191:128])
Packed_Sign_Extend_DWORD_to_QWORD( TEMP_DEST[511:384], SRC[255:192])
FI
FI;
VPMOVSXBW (VEX.256 Encoded Version)
Packed_Sign_Extend_BYTE_to_W ORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_BYTE_to_WOR D(DEST[255:128], SRC[127:64])
DEST[MAXVL-1:256] := 0PMOVSX—Packed Move With Sign ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-353VPMOVSXBD (VEX.256 Encoded Version)
Packed_Sign_Extend_BYTE_to_D WORD(DEST[127:0], SRC[31:0])
Packed_Sign_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])DEST[MAXVL-1:256] := 0
VPMOVSXBQ (VEX.256 Encoded Version)
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])Packed_Sign_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])DEST[MAXVL-1:256] := 0
VPMOVSXWD (VEX.256 Encoded Version)
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])Packed_Sign_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])DEST[MAXVL-1:256] := 0
VPMOVSXWQ (VEX.256 Encoded Version)
Packed_Sign_Extend_WORD_to_Q WORD(DEST[127:0], SRC[31:0])
Packed_Sign_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])DEST[MAXVL-1:256] := 0
VPMOVSXDQ (VEX.256 Encoded Version)
Packed_Sign_Extend_DWORD_to_ QWORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])DEST[MAXVL-1:256] := 0
VPMOVSXBW (VEX.128 Encoded Version)
Packed_Sign_Extend_BYTE_to_WORDDEST[127:0], SRC[127:0]()DEST[MAXVL-1:128] := 0
VPMOVSXBD (VEX.128 Encoded Version)
Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0])DEST[MAXVL-1:128] := 0
VPMOVSXBQ (VEX.128 Encoded Version)
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0])DEST[MAXVL-1:128] := 0
VPMOVSXWD (VEX.128 Encoded Version)
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0])DEST[MAXVL-1:128] := 0
VPMOVSXWQ (VEX.128 Encoded Version)
Packed_Sign_Extend_WORD_to_QWO RD(DEST[127:0], SRC[127:0])
VPMOVSXDQ (VEX.128 Encoded Version)
Packed_Sign_Extend_DWORD_to_ QWORD(DEST[127:0], SRC[127:0])
PMOVSXBW
Packed_Sign_Extend_BYTE_to_WOR D(DEST[127:0], SRC[127:0])
DEST[MAXVL-1:128 ] (Unmodified)PMOVSX—Packed Move With Sign ExtendINSTRUCTION SET REFERENCE, M-U
4-354 Vol. 2BPMOVSXBD
Packed_Sign_Extend_BYTE_to_DWO RD(DEST[127:0], SRC[127:0])
PMOVSXBQ
Packed_Sign_Extend_BYTE_to_QWO RD(DEST[127:0], SRC[127:0])
PMOVSXWD
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0])DEST[MAXVL-1:128] (Unmodified)
PMOVSXWQ
PMOVSXDQ
VPMOVSXBW __m512i _mm512_cvtepi8_epi16(__m512i a);VPMOVSXBW __m512i _mm512_mask_cvtepi8_epi 16(__m512i a, __mmask32 k, __m512i b);
VPMOVSXBW __m512i _mm512_maskz_cvtepi8_epi16( __mmask32 k, __m512i b);VPMOVSXBD __m512i _mm512_cvtepi8_epi32(__m512i a);VPMOVSXBD __m512i _mm512_mask_cvtepi8_ep i32(__m512i a, __mmask16 k, __m512i b);
VPMOVSXBD __m512i _mm512_maskz_cvtep i8_epi32( __mmask16 k, __m512i b);
VPMOVSXBQ __m512i _mm512_cvtepi8_epi64(__m512i a);VPMOVSXBQ __m512i _mm512_mask_cvtepi8_epi64(__m512i a, __mmask8 k, __m512i b);VPMOVSXBQ __m512i _mm512_maskz_cvtepi8_epi64( __mmask8 k, __m512i a);VPMOVSXDQ __m512i _mm512_cvtepi32_epi64(__m512i a);VPMOVSXDQ __m512i _mm512_mask_cvtepi32_epi64(__m512i a, __mmask8 k, __m512i b);VPMOVSXDQ __m512i _mm512_maskz_cvtepi32_epi64( __mmask8 k, __m512i a);VPMOVSXWD __m512i _mm512_cvtepi16_epi32(__m512i a);VPMOVSXWD __m512i _mm512_mask_cvtepi16_epi32(__m512i a, __mmask16 k, __m512i b);VPMOVSXWD __m512i _mm512_maskz_cvtepi16_epi32(__mmask16 k, __m512i a);VPMOVSXWQ __m512i _mm512_cvtepi16_epi64(__m512i a);VPMOVSXWQ __m512i _mm512_mask_cvtepi16_e pi64(__m512i a, __mmask8 k, __m512i b);
VPMOVSXWQ __m512i _mm512_maskz_cvtepi16_epi64( __mmask8 k, __m512i a);VPMOVSXBW __m256i _mm256_cvtepi8_epi16(__m256i a);VPMOVSXBW __m256i  _mm256_mask_cvtepi8_epi 16(__m256i a, __mmask16 k, __m256i b);
VPMOVSXBW __m256i _mm256_maskz_cvtepi8_epi16( __mmask16 k, __m256i b);VPMOVSXBD __m256i _mm256_cvtepi8_epi32(__m256i a);VPMOVSXBD __m256i _mm256_mask_cvtepi8_ep i32(__m256i a, __mmask8 k, __m256i b);
VPMOVSXBD __m256i _mm256_maskz_cvtep i8_epi32( __mmask8 k, __m256i b);
VPMOVSXBQ __m256i _mm256_cvtepi8_epi64(__m256i a);VPMOVSXBQ __m256i _mm256_mask_cvtepi8_epi64(__m256i a, __mmask8 k, __m256i b);VPMOVSXBQ __m256i _mm256_maskz_cvtepi8_epi64( __mmask8 k, __m256i a);VPMOVSXDQ __m256i _mm256_cvtepi32_epi64(__m256i a);VPMOVSXDQ __m256i _mm256_mask_cvtepi32_epi64(__m256i a, __mmask8 k, __m256i b);VPMOVSXDQ __m256i _mm256_maskz_cvtepi32_epi64( __mmask8 k, __m256i a);VPMOVSXWD __m256i _mm256_cvtepi16_epi32(__m256i a);VPMOVSXWD __m256i _mm256_mask_cvtepi16_epi32(__m256i a, __mmask16 k, __m256i b);PMOVSX—Packed Move With Sign ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-355VPMOVSXWD __m256i _mm256_maskz_cvtepi16_epi32(__mmask16 k, __m256i a);
VPMOVSXWQ __m256i _mm256_cvtepi16_epi64(__m256i a);VPMOVSXWQ __m256i _mm256_mask_cvtepi16_epi 64(__m256i a, __mmask8 k, __m256i b);
VPMOVSXWQ __m256i _mm256_maskz_cvtepi1 6_epi64( __mmask8 k, __m256i a);
VPMOVSXBW __m128i  _mm_mask_cvtepi8_epi 16(__m128i a, __mmask8 k, __m128i b);
VPMOVSXBW __m128i _mm_maskz_cvtepi8_epi16( __mmask8 k, __m128i b);VPMOVSXBD __m128i _mm_mask _cvtepi8_epi32(__m128i a,  __mmask8 k, __m128i b);
VPMOVSXBD __m128i _mm_maskz_cvtepi8_epi32( __mmask8 k, __m128i b);VPMOVSXBQ __m128i _mm_mask_cvtepi8_epi64(__m128i a, __mmask8 k, __m128i b);VPMOVSXBQ __m128i _mm_maskz_cvtepi8_epi64( __mmask8 k, __m128i a);VPMOVSXDQ __m128i _mm_mask_cvtepi32_epi64(__m128i a, __mmask8 k, __m128i b);VPMOVSXDQ __m128i _mm_maskz_cvtepi 32_epi64( __mmask8 k, __m128i a);
VPMOVSXWD __m128i _mm_mask_cvtepi16_epi32(__m128i a, __mmask16 k, __m128i b);VPMOVSXWD __m128i _mm_maskz_cvtepi16_epi32(__mmask16 k, __m128i a);VPMOVSXWQ __m128i _mm_mask_cvtepi16_epi 64(__m128i a, __mmask8 k, __m128i b);
VPMOVSXWQ __m128i _mm_maskz_cvtepi16 _epi64( __mmask8 k, __m128i a);
PMOVSXBW __m128i _mm_ cvtepi8_epi16 ( __m128i a);PMOVSXBD __m128i _mm_ cvtepi8_epi32 ( __m128i a);PMOVSXBQ __m128i _mm_ cvtepi8_epi64 ( __m128i a);PMOVSXWD __m128i _mm_ cvtepi16_epi32 ( __m128i a);PMOVSXWQ __m128i _mm_ cvtepi16_epi64 ( __m128i a);PMOVSXDQ __m128i _mm_ cvtepi32_epi64 ( __m128i a);
None.
EVEX-encoded instruction, see Table 2-51, “Type E5 Class Exception Conditions.”
#UD If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.PMOVZX—Packed Move With Zero ExtendINSTRUCTION SET REFERENCE, M-U
4-356 Vol. 2BPMOVZX—Packed Move With Zero Extend 
Opcode/
Mode 
66 0f 38 30 /r
PMOVZXBW xmm1, xmm2/m64A V/V SSE4_1 Zero extend 8 packed  8-bit integers in the low 8 
bytes of xmm2/m64 to 8 pa cked 16-bit integers in 
xmm1.
66 0f 38 31 /r
PMOVZXBD xmm1, xmm2/m32A V/V SSE4_1 Zero extend 4 packed  8-bit integers in the low 4 
bytes of xmm2/m32 to 4 pa cked 32-bit integers in 
xmm1.
66 0f 38 32 /r
PMOVZXBQ xmm1, xmm2/m16A V/V SSE4_1 Zero extend 2 packed  8-bit integers in the low 2 
bytes of xmm2/m16 to 2 pa cked 64-bit integers in 
xmm1.
66 0f 38 33 /r
PMOVZXWD xmm1, xmm2/m64A V/V SSE4_1 Zero extend 4 packed 16-bit integers in the low 8 
bytes of xmm2/m64 to 4 pa cked 32-bit integers in 
xmm1.
66 0f 38 34 /r
PMOVZXWQ xmm1, xmm2/m32A V/V SSE4_1 Zero extend 2 packed 16-bit integers in the low 4 
bytes of xmm2/m32 to 2 pa cked 64-bit integers in 
xmm1.
66 0f 38 35 /r
PMOVZXDQ xmm1, xmm2/m64A V/V SSE4_1 Zero extend 2 packed 32-bit integers in the low 8 
bytes of xmm2/m64 to 2 pa cked 64-bit integers in 
xmm1.
VEX.128.66.0F38.WIG 30 /r
VPMOVZXBW xmm1, xmm2/m64A V/V AVX Zero extend 8 packed 8-bit integers in the low 8 
xmm1.
VEX.128.66.0F38.WIG 31 /r

xmm1.
xmm1.
xmm1.
xmm1.
xmm1.
xmm1.
xmm1.
VPMOVZXBD xmm1, xmm2/m32A V/V AVX Zero extend 4 packed 8-bit integers in the low 4 
xmm1.
VEX.128.66.0F38.WIG 32 /r
VPMOVZXBQ xmm1, xmm2/m16A V/V AVX Zero extend 2 packed 8-bit integers in the low 2 
xmm1.
VEX.128.66.0F38.WIG 33 /r
VPMOVZXWD xmm1, xmm2/m64A V/V AVX Zero extend 4 packed 16 -bit integers in the low 8 
xmm1.
VEX.128.66.0F38.WIG 34 /r
VPMOVZXWQ xmm1, xmm2/m32A V/V AVX Zero extend 2 packed 16 -bit integers in the low 4 
xmm1.
VEX.128.66.0F 38.WIG 35 /r
VPMOVZXDQ xmm1, xmm2/m64A V/V AVX Zero extend 2 packed 32 -bit integers in the low 8 
xmm1.
VEX.256.66.0F38.WIG 30 /r
VPMOVZXBW ymm1, xmm2/m128A V/V AVX2 Zero extend 16 packed 8-bit integers in xmm2/m128 
to 16 packed 16-bit  integers in ymm1.
VEX.256.66.0F38.WIG 31 /r
VPMOVZXBD ymm1, xmm2/m64A V/V AVX2 Zero extend 8 packed 8-bit integers in the low 8 
bytes of xmm2/m64 to 8 pa cked 32-bit integers in 
ymm1.
VEX.256.66.0F38.WIG 32 /r
VPMOVZXBQ ymm1, xmm2/m32A V/V AVX2 Zero extend 4 packed 8-bit integers in the low 4 
bytes of xmm2/m32 to 4 pa cked 64-bit integers in 
ymm1.
VEX.256.66.0F38.WIG 33 /r
VPMOVZXWD ymm1, xmm2/m128A V/V AVX2 Zero extend 8 packed 16-bit integers xmm2/m128 to 
8 packed 32-bit integers in ymm1.PMOVZX—Packed Move With Zero ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-357VEX.256.66.0F38.WIG 34 /r
VPMOVZXWQ ymm1, xmm2/m64A V/V AVX2 Zero extend 4 packed 16-bit integers in the low 8 
bytes of xmm2/m64 to 4 packed 64-bit integers in 
xmm1.
VEX.256.66.0F38.WIG 35 /r
VPMOVZXDQ ymm1, xmm2/m128A V/V AVX2 Zero extend 4 packed 32-bit integers in xmm2/m128 
to 4 packed 64-bit integers in ymm1.
EVEX.128.66.0F38 30.WIG /r
VPMOVZXBW xmm1 {k 1}{z}, xmm2/m64B V/V AVX512VL
AVX512BWZero extend 8 packed 8-bi t integers in the low 8 
bytes of xmm2/m64 to 8 packed 16-bit integers in 
xmm1.
EVEX.256.66.0F38.WIG 30 /r
VPMOVZXBW ymm1 {k1}{z}, xmm2/m128B V/V AVX512VL
AVX512BWZero extend 16 packed 8- bit integers in xmm2/m128 
EVEX.512.66.0F38.WIG 30 /r
VPMOVZXBW zmm1 {k1}{z}, ymm2/m256B V/V AVX512BW Zero extend 32 packed 8-bit integers in ymm2/m256 
to 32 packed 16-bit  integers in zmm1.
EVEX.128.66.0F38.WIG 31 /r
VPMOVZXBD xmm1 {k1}{z}, xmm2/m32C V/V AVX512VL
AVX512FZero extend 4 packed 8-bi t integers in the low 4 
bytes of xmm2/m32 to 4 packed 32-bit integers in xmm1 subject to writemask k1.
EVEX.256.66.0F38.WIG 31 /r
VPMOVZXBD ymm1 {k1}{z}, xmm2/m64C V/V AVX512VL
AVX512FZero extend 8 packed 8-bi t integers in the low 8 
bytes of xmm2/m64 to 8 packed 32-bit integers in 
EVEX.512.66.0F38.WIG 31 /r
VPMOVZXBD zmm1 {k1}{z}, xmm2/m128C V/V AVX512F Zero extend 16 packed 8-bit integers in xmm2/m128 
to 16 packed 32-bit inte gers in zmm1 subject to 
EVEX.128.66.0F38.WIG 32 /r
VPMOVZXBQ xmm1 {k1}{z}, xmm2/m16D V/V AVX512VL
AVX512FZero extend 2 packed 8-bi t integers in the low 2 
bytes of xmm2/m16 to 2 packed 64-bit integers in xmm1 subject to writemask k1.
EVEX.256.66.0F38.WIG 32 /r
VPMOVZXBQ ymm1 {k1}{z}, xmm2/m32D V/V AVX512VL
bytes of xmm2/m32 to 4 packed 64-bit integers in 
EVEX.512.66.0F38.WIG 32 /r
VPMOVZXBQ zmm1 {k1}{z}, xmm2/m64D V/V AVX512F Zero extend 8 packed  8-bit integers in the low 8 
bytes of xmm2/m64 to 8 packed 64-bit integers in 
EVEX.128.66.0F38.WIG 33 /r
VPMOVZXWD xmm1 {k1}{z}, xmm2/m64B V/V AVX512VL
AVX512FZero extend 4 packed 16-b it integers in the low 8 
bytes of xmm2/m64 to 4 packed 32-bit integers in xmm1 subject to writemask k1.
EVEX.256.66.0F38.WIG 33 /r
VPMOVZXWD ymm1 {k1}{z}, xmm2/m128B V/V AVX512VL
AVX512FZero extend 8 packed 16-bit integers in xmm2/m128 
to 8 packed 32-bit intege rs in zmm1 subject to 
EVEX.512.66.0F38.WIG 33 /r
VPMOVZXWD zmm1 {k1}{z}, ymm2/m256B V/V AVX512F Zero extend 16 pa cked 16-bit integers in 
ymm2/m256 to 16 packed 32-bit integers in zmm1 
EVEX.128.66.0F38.WIG 34 /r
VPMOVZXWQ xmm1 {k1}{z}, xmm2/m32C V/V AVX512VL
AVX512F
Zero extend 2 packed 16-b it integers in the low 4 
bytes of xmm2/m32 to 2 packed 64-bit integers in xmm1 subject to writemask k1.
EVEX.256.66.0F38.WIG 34 /r
VPMOVZXWQ ymm1 {k1}{z}, xmm2/m64C V/V AVX512VL
EVEX.512.66.0F38.WIG 34 /r
VPMOVZXWQ zmm1 {k1}{z}, xmm2/m128C V/V AVX512F Zero extend 8 packed 16-bit integers in xmm2/m128 
to 8 packed 64-bit intege rs in zmm1 subject to 
writemask k1.Opcode/
Mode 
Feature FlagDescriptionPMOVZX—Packed Move With Zero ExtendINSTRUCTION SET REFERENCE, M-U
4-358 Vol. 2BInstruction Operand Encoding
Legacy, VEX, and EVEX encoded versions : Packed byte, word, or dword integers  starting from the low bytes of the 
source operand (second operand) are zero extended to wo rd, dword, or quadword integers and stored in packed 
signed bytes the destination operand.
VEX.128 encoded version: Bits (MAXVL-1:128) of th e corresponding destination register are zeroed.
VEX.256 encoded version: Bits (MAXVL-1:256) of th e corresponding destination register are zeroed. 
EVEX encoded versions: Packed dword integers starting  from the low bytes of th e source operand (second 
operand) are zero extended to quadword integers and st ored to the destination operand under the writemask.The 
destination register is XMM, YMM or ZMM Register.
Operation
Packed_Zero_Extend_BYTE_to_WORD(DEST, SRC)
DEST[15:0] := ZeroExtend(SRC[7:0]);DEST[31:16] := ZeroExtend(SRC[15:8]);DEST[47:32] := Zero Extend(SRC[23:16]);
DEST[63:48] := Zero Extend(SRC[31:24]);
DEST[79:64] := Zero Extend(SRC[39:32]);
DEST[95:80] := Zero Extend(SRC[47:40]);
DEST[111:96] := ZeroExtend(SRC[55:48]);DEST[127:112] := ZeroExtend(SRC[63:56]);
Packed_Zero_Extend_BYT E_to_DWORD(DEST, SRC)
DEST[31:0] := ZeroExtend(SRC[7:0]);DEST[63:32] := ZeroExtend(SRC[15:8]);DEST[95:64] := Zero Extend(SRC[23:16]);
DEST[127:96] := ZeroExtend(SRC[31:24]);EVEX.128.66.0F38.W0 35 /r
VPMOVZXDQ xmm1 {k1}{z}, xmm2/m64BV / V A V X 5 1 2 V L
AVX512FZero extend 2 packed 32-b it integers in the low 8 
zmm1 using writemask k1.
EVEX.256.66.0F38.W0 35 /r
VPMOVZXDQ ymm1 {k1}{z}, xmm2/m128BV / V A V X 5 1 2 V L
AVX512FZero extend 4 packed 32-bit integers in xmm2/m128 
to 4 packed 64-bit integers in zmm1 using writemask 
k1.
EVEX.512.66.0F38.W0 35 /r
VPMOVZXDQ zmm1 {k1}{z}, ymm2/m256B V/V AVX512F Zero extend 8 packed 32-bit integers in ymm2/m256 
to 8 packed 64-bit integers in zmm1 using writemask 
k1.
D Eighth Mem ModRM:reg (w) ModRM:r/m (r) N/A N/AOpcode/
Mode 
Vol. 2B 4-359Packed_Zero_Extend_BYTE_to_QWORD(DEST, SRC)
DEST[63:0] := Zero Extend(SRC[7:0]);
DEST[127:64] := ZeroExtend(SRC[15:8]);
Packed_Zero_Extend_WOR D_to_DWORD(DEST, SRC)
DEST[31:0] := ZeroExtend(SRC[15:0]);DEST[63:32] := Zero Extend(SRC[31:16]);
DEST[95:64] := Zero Extend(SRC[47:32]);
DEST[127:96] := ZeroExtend(SRC[63:48]);
Packed_Zero_Extend_WOR D_to_QWORD(DEST, SRC)
DEST[63:0] := ZeroExtend(SRC[15:0]);DEST[127:64] := ZeroExtend(SRC[31:16]);
Packed_Zero_Extend_DWO RD_to_QWORD(DEST, SRC)
DEST[63:0] := ZeroExtend(SRC[31:0]);DEST[127:64] := ZeroExtend(SRC[63:32]);
VPMOVZXBW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[127:0], SRC[63:0])IF VL >= 256
Packed_Zero_Extend_BYTE_to_WORD( TMP_DEST[255:128], SRC[127:64])
Packed_Zero_Extend_BYTE_to_WORD(TM P_DEST[383:256], SRC[191:128])
Packed_Zero_Extend_BYTE_to_WORD(TM P_DEST[511:384], SRC[255:192])
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0PMOVZX—Packed Move With Zero ExtendINSTRUCTION SET REFERENCE, M-U
4-360 Vol. 2BVPMOVZXBD (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)Packed_Zero_Extend_BYTE_to_DWO RD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256

FI
FI;
IF VL >= 256
Packed_Zero_Extend_BYTE_to_DWORD (TMP_DEST[255:128], SRC[63:32])
Packed_Zero_Extend_BYTE_to_DWORD (TMP_DEST[383:256], SRC[95:64])
Packed_Zero_Extend_BYTE_to_DWORD (TMP_DEST[511:384], SRC[127:96])
FI
FI;
VPMOVZXBQ (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)Packed_Zero_Extend_BYTE_to_QWO RD(TMP_DEST[127:0], SRC[15:0])
IF VL >= 256
Packed_Zero_Extend_BYTE_to_QWORD (TMP_DEST[255:128], SRC[31:16])
Packed_Zero_Extend_BYTE_to_QWORD (TMP_DEST[383:256], SRC[47:32])
Packed_Zero_Extend_BYTE_to_QWORD (TMP_DEST[511:384], SRC[63:48])
FI
FI;
Vol. 2B 4-361VPMOVZXWD (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)Packed_Zero_Extend_WORD_to_DWO RD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Zero_Extend_WORD_to_DWORD (TMP_DEST[255:128], SRC[127:64])
Packed_Zero_Extend_WORD_to_DWORD(T MP_DEST[383:256], SRC[191:128])
Packed_Zero_Extend_WORD_to_DWORD(T MP_DEST[511:384], SRC[256:192])
FI
FI;
VPMOVZXWQ (EVEX Encoded Versions)
Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[127:0], SRC[31:0])IF VL >= 256
Packed_Zero_Extend_WORD_to_QWORD (TMP_DEST[255:128], SRC[63:32])
Packed_Zero_Extend_WORD_to_QWORD (TMP_DEST[383:256], SRC[95:64])
Packed_Zero_Extend_WORD_to_QWORD (TMP_DEST[511:384], SRC[127:96])
FI
FI;
4-362 Vol. 2BVPMOVZXDQ (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)Packed_Zero_Extend_DWORD_to_QWOR D(TEMP_DEST[127:0], SRC[63:0])
IF VL >= 256
Packed_Zero_Extend_DWORD_to_QWORD( TEMP_DEST[255:128], SRC[127:64])
Packed_Zero_Extend_DWORD_to_QWORD( TEMP_DEST[383:256], SRC[191:128])
Packed_Zero_Extend_DWORD_to_QWORD( TEMP_DEST[511:384], SRC[255:192])
FI
FI;
VPMOVZXBW (VEX.256 Encoded Version)
Packed_Zero_Extend_BYTE_to_W ORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_BYTE_to_WOR D(DEST[255:128], SRC[127:64])
VPMOVZXBD (VEX.256 Encoded Version)
Packed_Zero_Extend_BYTE_to_D WORD(DEST[127:0], SRC[31:0])
Packed_Zero_Extend_BYTE_to_DWO RD(DEST[255:128], SRC[63:32])
VPMOVZXBQ (VEX.256 Encoded Version)
Packed_Zero_Extend_BYTE_to_Q WORD(DEST[127:0], SRC[15:0])
Packed_Zero_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])DEST[MAXVL-1:256] := 0
VPMOVZXWD (VEX.256 Encoded Version)
Packed_Zero_Extend_WORD_to_D WORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])DEST[MAXVL-1:256] := 0
VPMOVZXWQ (VEX.256 Encoded Version)
Packed_Zero_Extend_WORD_to_Q WORD(DEST[127:0], SRC[31:0])
Packed_Zero_Extend_WORD_to_QWO RD(DEST[255:128], SRC[63:32])
VPMOVZXDQ (VEX.256 Encoded Version)
Packed_Zero_Extend_D WORD_to_QWORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_DWORD_to_QWOR D(DEST[255:128], SRC[127:64])
DEST[MAXVL-1:256] := 0PMOVZX—Packed Move With Zero ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-363VPMOVZXBW (VEX.128 Encoded Version)
Packed_Zero_Extend_BYTE_to_WORD()DEST[MAXVL-1:128] := 0
VPMOVZXBD (VEX.128 Encoded Version)
Packed_Zero_Extend_BYTE_to_DWORD()DEST[MAXVL-1:128] := 0
VPMOVZXBQ (VEX.128 Encoded Version)
Packed_Zero_Extend_BYTE_to_QWORD()DEST[MAXVL-1:128] := 0
VPMOVZXWD (VEX.128 Encoded Version)
Packed_Zero_Extend_WORD_to_DWORD()DEST[MAXVL-1:128] := 0
VPMOVZXWQ (VEX.128 Encoded Version)
Packed_Zero_Extend_WORD_to_QWORD()DEST[MAXVL-1:128] := 0
VPMOVZXDQ (VEX.128 Encoded Version )
Packed_Zero_Extend _DWORD_to_QWORD()
PMOVZXBW
Packed_Zero_Extend_BYTE_to_WORD()DEST[MAXVL-1:128 ] (Unmodified)
PMOVZXBD
Packed_Zero_Extend_BYTE_to_DWORD()DEST[MAXVL-1:128 ] (Unmodified)
PMOVZXBQ
Packed_Zero_Extend_BYTE_to_QWORD()DEST[MAXVL-1:128 ] (Unmodified)
PMOVZXWD
Packed_Zero_Extend_WORD_to_DWORD()DEST[MAXVL-1:128 ] (Unmodified)
PMOVZXWQ
Packed_Zero_Extend_WORD_to_QWORD()DEST[MAXVL-1:128 ] (Unmodified)
PMOVZXDQ
VPMOVZXBW __m512i _mm512_cvtepu8_epi16(__m256i a);
VPMOVZXBW __m512i _mm512_mask_cvtepu8_epi16(__m512i a, __mmask32 k, __m256i b);VPMOVZXBW __m512i _mm512_maskz_cvtep u8_epi16( __mmask32 k, __m256i b);
VPMOVZXBD __m512i _mm512_cvtepu8_epi32(__m128i a);PMOVZX—Packed Move With Zero ExtendINSTRUCTION SET REFERENCE, M-U
4-364 Vol. 2BVPMOVZXBD __m512i _mm512_mask_cvtepu8_ep i32(__m512i a, __mmask16 k, __m128i b);
VPMOVZXBD __m512i _mm512_maskz_cvtepu8 _epi32( __mmask16 k, __m128i b);
VPMOVZXBQ __m512i _mm512_cvtepu8_epi64(__m128i a);VPMOVZXBQ __m512i _mm512_mask_cvtepu8_ep i64(__m512i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m512i _mm512_maskz_cvtep u8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m512i _mm512_cvtepu32_epi64(__m256i a);VPMOVZXDQ __m512i _mm512_mask_cvtepu32_epi64(__m512i a, __mmask8 k, __m256i b);VPMOVZXDQ __m512i _mm512_maskz_cvtep u32_epi64( __mmask8 k, __m256i a);
VPMOVZXWD __m512i _mm512_cvtepu16_epi32(__m128i a);VPMOVZXWD __m512i _mm512_mask_cvtepu16_epi 32(__m512i a, __mmask16 k, __m128i b);
VPMOVZXWD __m512i _mm512_maskz_cvtep u16_epi32(__mmask16 k, __m128i a);
VPMOVZXWQ __m512i _mm512_cvtepu16_epi64(__m256i a);VPMOVZXWQ __m512i _mm512_mask_cvtepu16_epi64(__m512i a, __mmask8 k, __m256i b);VPMOVZXWQ __m512i _mm512_maskz_cvtepu16_epi64( __mmask8 k, __m256i a);VPMOVZXBW __m256i _mm256_cvtepu8_epi16(__m256i a);VPMOVZXBW __m256i  _mm256_mask_cvtepu8_epi16(__m256i a, __mmask16 k, __m128i b);VPMOVZXBW __m256i _mm256_maskz_cvtep u8_epi16( __mmask16 k, __m128i b);
VPMOVZXBD __m256i _mm256_cvtepu8_epi32(__m128i a);VPMOVZXBD __m256i _mm256_mask_cvtepu8_ep i32(__m256i a, __mmask8 k, __m128i b);
VPMOVZXBD __m256i _mm256_maskz_cvtepu8 _epi32( __mmask8 k, __m128i b);
VPMOVZXBQ __m256i _mm256_cvtepu8_epi64(__m128i a);VPMOVZXBQ __m256i _mm256_mask_cvtepu8_ep i64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m256i _mm256_maskz_cvtep u8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m256i _mm256_cvtepu32_epi64(__m128i a);VPMOVZXDQ __m256i _mm256_mask_cvtepu32_epi64(__m256i a, __mmask8 k, __m128i b);VPMOVZXDQ __m256i _mm256_maskz_cvtep u32_epi64( __mmask8 k, __m128i a);
VPMOVZXWD __m256i _mm256_cvtepu16_epi32(__m128i a);VPMOVZXWD __m256i _mm256_mask_cvtepu16_epi 32(__m256i a, __mmask16 k, __m128i b);
VPMOVZXWD __m256i _mm256_maskz_cvtep u16_epi32(__mmask16 k, __m128i a);
VPMOVZXWQ __m256i _mm256_cvtepu16_epi64(__m128i a);VPMOVZXWQ __m256i _mm256_mask_cvtepu16_epi64(__m256i a, __mmask8 k, __m128i b);VPMOVZXWQ __m256i _mm256_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);VPMOVZXBW __m128i  _mm_mask_cvtepu8_e pi16(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBW __m128i _mm_maskz_cvtepu 8_epi16( __mmask8 k, __m128i b);
VPMOVZXBD __m128i _mm_mask_cvtepu8_epi32 (__m128i a, __mmask8 k, __m128i b);
VPMOVZXBD __m128i _mm_mask z_cvtepu8_epi32( __mmask8 k, __m128i b);
VPMOVZXBQ __m128i _mm_mask_cvtepu8_epi 64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m128i _mm_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);VPMOVZXDQ __m128i _mm_mask_cvtepu32_epi6 4(__m128i a, __mmask8 k, __m128i b);
VPMOVZXDQ __m128i _mm_maskz_cvtepu 32_epi64( __mmask8 k, __m128i a);
VPMOVZXWD __m128i _mm_mask_cvtepu16_epi32(__m128i a, __mmask16 k, __m128i b);VPMOVZXWD __m128i _mm_maskz_cvte pu16_epi32(__mmask8 k, __m128i a);

VPMOVZXWQ __m128i _mm_mask_cvtepu16_epi64(__m128i a, __mmask8 k, __m128i b);VPMOVZXWQ __m128i _mm_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);PMOVZXBW __m128i _mm_ cvtepu8_epi16 ( __m128i a);PMOVZXBD __m128i _mm_ cvtepu8_epi32 ( __m128i a);PMOVZXBQ __m128i _mm_ cvtepu8_epi64 ( __m128i a);PMOVZXWD __m128i _mm_ cvtepu16_epi32 ( __m128i a);PMOVZXWQ __m128i _mm_ cvtepu16_epi64 ( __m128i a);PMOVZXDQ __m128i _mm_ cvtepu32_epi64 ( __m128i a);
None.PMOVZX—Packed Move With Zero ExtendINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-365Other Exceptions
EVEX-encoded instruction, see Table 2-51, “Type E5 Class Exception Conditions.”Additionally:
#UD If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.PMULDQ—Multiply Packed Doubleword IntegersINSTRUCTION SET REFERENCE, M-U
4-366 Vol. 2BPMULDQ—Multiply Packed Doubleword Integers
Multiplies packed signed doubleword integers in the ev en-numbered (zero-based reference) elements of the first 
source operand with the packed signed  doubleword integers in the correspon ding elements of the second source 
operand and stores packed signed quadwo rd results in the destination operand. 
128-bit Legacy SSE version: The input signed doubleword integers are taken from the even-numbered elements of 
the source operands, i.e., the first (low) and third double word element. For 128-bit memory operands, 128 bits are 
fetched from memory, but only the first and third doublewords are used in the computation. The first source 
operand and the destination XMM operand is the same. The second source operand can be an XMM register or 128-
bit memory location. Bits (MAXVL-1:128) of the co rresponding destination register remain unchanged.
VEX.128 encoded version: The input signed doubleword in tegers are taken from the even-numbered elements of 
fetched from memory, but only the first and third doublewords are used in the computation.The first source 
operand and the destination operand are XMM registers. Th e second source operand can be an XMM register or 
128-bit memory location. Bits (MAXVL-1:128) of th e corresponding destination register are zeroed.
VEX.256 encoded version: The input signed doubleword in tegers are taken from the even-numbered elements of 
the source operands, i.e., the first, 3rd, 5th, 7th doub leword element. For 256-bit memory operands, 256 bits are 
fetched from memory, but only the four even-numbered doub lewords are used in the computation. The first source 
operand and the destination operand are YMM registers. Th e second source operand can be a YMM register or 256-
bit memory location. Bits (MAXVL-1:256) of the co rresponding destination ZMM register are zeroed.Opcode/
Mode 
Feature 
66 0F 38 28 /r
PMULDQ xmm1, xmm2/m128A V/V SSE4_1 Multiply packed signed doubleword integers in xmm1 by 
packed signed doubleword integers in xmm2/m128, and 
store the quadword results in xmm1.
VEX.128.66.0F38.WIG 28 /r
VPMULDQ xmm1, xmm2, xmm3/m128B V/V AVX Multiply packed signed doubleword integers in xmm2 by 
packed signed doubleword integers in xmm3/m128, and store the quadword results in xmm1.
VEX.256.66.0F38.WIG 28 /r
VPMULDQ ymm1, ymm2, 
ymm3/m256B V/V AVX2 Multiply packed signed do ubleword integers in ymm2 by 
packed signed doubleword integers in ymm3/m256, and 
store the quadword results in ymm1.
EVEX.128.66.0F38.W1 28 /r
VPMULDQ xmm1 {k1}{z}, xmm2, 
AVX512FMultiply packed sign ed doubleword inte gers in xmm2 by 
packed signed doubleword integers in 
xmm3/m128/m64bcst, and store the quadword results in 
xmm1 using writemask k1.
EVEX.256.66.0F38.W1 28 /r
VPMULDQ ymm1 {k1}{z}, ymm2, 
AVX512FMultiply packed sign ed doubleword inte gers in ymm2 by 
ymm3/m256/m64bcst, and store the quadword results in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 28 /r
VPMULDQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Multiply packed signed doubleword integers in zmm2 by 
packed signed doubleword integers in zmm3/m512/m64bcst, 
and store the quadword results in zmm1 using writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMULDQ—Multiply Packed Doubleword IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-367EVEX encoded version: The input signed doubleword inte gers are taken from the even-numbered elements of the 
source operands. The first source operand is a ZMM/YMM/ XMM registers. The second source operand can be an 
ZMM/YMM/XMM register, a 512/256/128-bit memory location  or a 512/256/128-bit vector broadcasted from a 64-
bit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64-
bit granularity. 
Operation
VPMULDQ (EVEX Encoded Versions)
THEN 
THEN DEST[i+63:i] := SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[31:0])ELSE DEST[i+63:i] := SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[i+31:i])
FI;
ELSE 
FI
FI;
VPMULDQ (VEX.256 Encoded Version)
DEST[63:0] := SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])DEST[127:64] := SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])DEST[191:128] := SignExtend64( SRC1[159:128]) * SignExtend64( SRC2[159:128])DEST[255:192] := SignExtend64( SRC1[223:192]) * SignExtend64( SRC2[223:192])DEST[MAXVL-1:256] := 0
VPMULDQ (VEX.128 Encoded Version)
DEST[63:0] := SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])DEST[127:64] := SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])DEST[MAXVL-1:128] := 0
PMULDQ (128-bit Legacy SSE Version)
DEST[63:0] := SignExtend64( DEST[31:0]) * SignExtend64( SRC[31:0])DEST[127:64] := SignExtend64( DEST[95:64]) * SignExtend64( SRC[95:64])DEST[MAXVL-1:128 ] (Unmodified)
VPMULDQ __m512i _mm512_mul_epi32(__m512i a, __m512i b);
VPMULDQ __m512i _mm512_mask_mul_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);VPMULDQ __m512i _mm512_maskz_mul_epi32( __mmask8 k, __m512i a, __m512i b);VPMULDQ __m256i _mm256_mask_mul_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);VPMULDQ __m256i _mm256_mask_mul_epi32( __mmask8 k, __m256i a, __m256i b);VPMULDQ __m128i _mm_mask_mul_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMULDQ __m128i _mm_mask_mul_epi32( __mmask8 k, __m128i a, __m128i b);(V)PMULDQ __m128i _mm_mul_epi32( __m128i a, __m128i b);PMULDQ—Multiply Packed Doubleword IntegersINSTRUCTION SET REFERENCE, M-U
4-368 Vol. 2BVPMULDQ __m256i _mm256_mul_epi32( __m256i a, __m256i b);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PMULHRSW—Packed Multiply High With Round and ScaleINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-369PMULHRSW—Packed Multiply High With Round and Scale 
PMULHRSW multiplies vertically each si gned 16-bit integer from the destination operand (first operand) with the 
corresponding signed 16-bit integer of the source operan d (second operand), producing intermediate, signed 32-
bit integers. Each intermediate 32-bit integer is truncate d to the 18 most significant bits. Rounding is always 
performed by adding 1 to the least significant bit of the 18 -bit intermediate result. The final result is obtained by 
selecting the 16 bits immediately to the right of the most  significant bit of each 18-bit intermediate result and 
packed to the destination operand. 
In 64-bit mode and not encoded with VEX/EVEX, us e the REX prefix to access XMM8-XMM15 registers. 
Legacy SSE version 64-bit operand: Both operands can be  MMX registers. The second source operand is an MMX 
register or a 64-bit memory location.Opcode/
Mode 
Feature 
NP 0F 38 0B /r1 
PMULHRSW mm1, mm2/m64
NOTES:

Mode 
Feature 
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSSE3 Multiply 16-bit signed words, scale and round 
signed doublewords, pack high 16 bits to 
mm1.
66 0F 38 0B /r
PMULHRSW xmm1, xmm2/m128 A V/V SSSE3 Multiply 16-bit signed words, scale and round 
signed doublewords, pack high 16 bits to xmm1.
VEX.128.66.0F38.WIG 0B /r
VPMULHRSW xmm1, xmm2, xmm3/m128B V/V AVX Multiply 16-bit signed words, scale and round 
xmm1.
VEX.256.66.0F38.WIG 0B /r
VPMULHRSW ymm1, ymm2, ymm3/m256B V/V AVX2 Multiply 16-bit signed words, scale and round 
ymm1.
EVEX.128.66.0F38.WIG 0B /r
VPMULHRSW xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWMultiply 16-bit signed words, scale and round 
EVEX.256.66.0F38.WIG 0B /r
VPMULHRSW ymm1 {k1}{z}, ymm2, ymm3/m256C V/V AVX512VL
signed doublewords, pack high 16 bits to ymm1 under writemask k1.
EVEX.512.66.0F38.WIG 0B /r
VPMULHRSW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Multiply 16-bit signed words, scale and round 
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMULHRSW—Packed Multiply High With Round and ScaleINSTRUCTION SET REFERENCE, M-U
4-370 Vol. 2B128-bit Legacy SSE version: The first source and destin ation operands are XMM registers. The second source 
zeroed. 
a ZMM/YMM/XMM register, a 512/256/128-bit memory lo cation. The destination operand is a ZMM/YMM/XMM 
register conditionally updated with writemask k1.
Operation
PMULHRSW (With 64-bit Operands)
temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >> 14) + 1;temp3[31:0] = INT32 ((DEST[63:48] * SRc[63:48]) >> 14) + 1;DEST[15:0] = temp0[16:1];DEST[31:16] = temp1[16:1];DEST[47:32] = temp2[16:1];DEST[63:48] = temp3[16:1];
PMULHRSW (With 128-bit Operands)
temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >>14) + 1;temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) >>14) + 1;temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) >>14) + 1;temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) >>14) + 1;temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) >>14) + 1;temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) >>14) + 1;DEST[15:0] = temp0[16:1];DEST[31:16] = temp1[16:1];DEST[47:32] = temp2[16:1];DEST[63:48] = temp3[16:1];DEST[79:64] = temp4[16:1];DEST[95:80] = temp5[16:1];DEST[111:96] = temp6[16:1];DEST[127:112] = temp7[16:1];
VPMULHRSW (VEX.128 Encoded Version)
temp0[31:0] := INT32 ((SRC1[15 :0] * SRC2[15:0]) >>14) + 1
temp1[31:0] := INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1temp2[31:0] := INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1temp3[31:0] := INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1temp4[31:0] := INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1temp5[31:0] := INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1temp6[31:0] := INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1temp7[31:0] := INT32 ((SRC1[127: 112] * SRC2[127:112) >>14) + 1
DEST[15:0] := temp0[16:1]DEST[31:16] := temp1[16:1]DEST[47:32] := temp2[16:1]PMULHRSW—Packed Multiply High With Round and ScaleINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-371DEST[63:48] := temp3[16:1]
DEST[79:64] := temp4[16:1]DEST[95:80] := temp5[16:1]DEST[111:96] := temp6[16:1]DEST[127:112] := temp7[16:1]DEST[MAXVL-1:128] := 0
VPMULHRSW (VEX.256 Encoded Version)
temp0[31:0] := INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1temp1[31:0] := INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1temp2[31:0] := INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1temp3[31:0] := INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1temp4[31:0] := INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1temp5[31:0] := INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1temp6[31:0] := INT32 ((SRC1[111: 96] * SRC2[111:96]) >>14) + 1
temp7[31:0] := INT32 ((SRC1[127: 112] * SRC2[127:112) >>14) + 1
temp8[31:0] := INT32 ((SRC1[143:12 8] * SRC2[143:128]) >>14) + 1
temp9[31:0] := INT32 ((SRC1[159:14 4] * SRC2[159:144]) >>14) + 1
temp10[31:0] := INT32 ((SRC1[75:160] * SRC2[175:160]) >>14) + 1temp11[31:0] := INT32 ((SRC1[191:176] * SRC2[191:176]) >>14) + 1temp12[31:0] := INT32 ((SRC1[207:192] * SRC2[207:192]) >>14) + 1temp13[31:0] := INT32 ((SRC1[223:208] * SRC2[223:208]) >>14) + 1temp14[31:0] := INT32 ((SRC1[239:224] * SRC2[239:224]) >>14) + 1temp15[31:0] := INT32 ((SRC1[255:240] * SRC2[255:240) >>14) + 1
DEST[15:0] := temp0[16:1]
DEST[31:16] := temp1[16:1]DEST[47:32] := temp2[16:1]DEST[63:48] := temp3[16:1]DEST[79:64] := temp4[16:1]DEST[95:80] := temp5[16:1]DEST[111:96] := temp6[16:1]DEST[127:112] := temp7[16:1]DEST[143:128] := temp8[16:1]DEST[159:144] := temp9[16:1]DEST[175:160] := temp10[16:1]DEST[191:176] := temp11[16:1]DEST[207:192] := temp12[16:1]DEST[223:208] := temp13[16:1]DEST[239:224] := temp14[16:1]DEST[255:240] := temp15[16:1]DEST[MAXVL-1:256] := 0PMULHRSW—Packed Multiply High With Round and ScaleINSTRUCTION SET REFERENCE, M-U
4-372 Vol. 2BVPMULHRSW (EVEX Encoded Version)
THEN 
temp[31:0] := ((SRC1[i+15:i] * SRC2[i+15:i]) >>14) + 1DEST[i+15:i] := tmp[16:1]
ELSE 
FI
FI;
VPMULHRSW __m512i _mm512_mulhrs_epi16(__m512i a, __m512i b);VPMULHRSW __m512i _mm512_mask_mulhrs_epi16(__m 512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHRSW __m512i _mm512_maskz_mulhrs_epi16( __mmask32 k, __m512i a, __m512i b);VPMULHRSW __m256i _mm256_mask_mulhrs_epi16(__m 256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHRSW __m256i _mm256_maskz_mulhrs_epi16( __mmask16 k, __m256i a, __m256i b);VPMULHRSW __m128i _mm_mask_mulhrs_epi16(__m128 i s, __mmask8 k, __m128i a, __m128i b);
VPMULHRSW __m128i _mm_maskz_mulhrs_epi16 ( __mmask8 k, __m128i a, __m128i b);
PMULHRSW __m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)(V)PMULHRSW __m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)VPMULHRSW __m256i _mm256_mulhrs_epi16 (__m256i a, __m256i b)
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PMULHUW—Multiply Packed Unsigned  Integers and Store High ResultINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-373PMULHUW—Multiply Packed Unsigned Integers and Store High Result
Performs a SIMD unsigned multiply of the packed unsigned wo rd integers in the destination operand (first operand) 
and the source operand (second operand), and stores the hi gh 16 bits of each 32-bit intermediate results in the 
destination operand. (Figure 4-12 shows this operation when using 64-bit operands.)
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory 
location. The destination operand is an MMX technology register.
tion register remain unchanged.Opcode/
Mode 
Feature 
NP 0F E4 /r1
PMULHUW mm1, mm2/m64
NOTES:

Mode 
Feature 
NP 0F E4 /r1
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSE Multiply the packed unsigned word integers in 
mm1 register and mm2/m64, and store the 
high 16 bits of th e results in mm1. 
66 0F E4 /r
PMULHUW xmm1, xmm2/m128A V/V SSE2 Multiply the packed unsigned word integers in 
xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1.
VEX.128.66.0F.WIG E4 /r
VPMULHUW xmm1, xmm2, xmm3/m128B V/V AVX Multiply the packed un signed word integers in 
xmm2 and xmm3/m128, and store the high 
16 bits of the results in xmm1.
VEX.256.66.0F.WIG E4 /r
VPMULHUW ymm1, ymm2, ymm3/m256B V/V AVX2 Multiply the packed unsigned word integers in 
ymm2 and ymm3/m256, and store the high 
16 bits of the results in ymm1.
EVEX.128.66.0F.WIG E4 /r
VPMULHUW xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWMultiply the packed unsigned word integers in 
16 bits of the results in xmm1 under 
EVEX.256.66.0F.WIG E4 /r
VPMULHUW ymm1 {k1}{z }, ymm2, ymm3/m256C V/V AVX512VL
16 bits of the results in ymm1 under 
EVEX.512.66.0F.WIG E4 /r
VPMULHUW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Multiply the packed unsigned word integers in 
zmm2 and zmm3/m512, and store the high 16 
bits of the results in  zmm1 under writemask 
k1.
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMULHUW—Multiply Packed Unsigned Integers and Store High ResultINSTRUCTION SET REFERENCE, M-U
4-374 Vol. 2BVEX.128 encoded version: The first source and destinat ion operands are XMM registers. The second source 
zeroed. VEX.L must be 0, othe rwise the instruction will #UD.
Operation
PMULHUW (With 64-bit Operands)
TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Unsign ed multiplication *)
TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];
DEST[15:0] := TEMP0[31:16];DEST[31:16] := TEMP1[31:16];
DEST[47:32] := TEMP2[31:16];
DEST[63:48] := TEMP3[31:16];
PMULHUW (With 128-bit Operands)
TEMP0[31:0] := DEST[15:0] 
∗ SRC[15:0]; (* Unsign ed multiplication *)
TEMP4[31:0] := DEST[79:64] ∗ SRC[79:64];
TEMP5[31:0] := DEST[95:80] ∗ SRC[95:80];
TEMP6[31:0] := DEST[111:96] ∗ SRC[111:96];
TEMP7[31:0] := DEST[127:112] ∗ SRC[127:112];
DEST[15:0] := TEMP0[31:16];DEST[31:16] := TEMP1[31:16];DEST[47:32] := TEMP2[31:16];DEST[63:48] := TEMP3[31:16];DEST[79:64] := TEMP4[31:16];DEST[95:80] := TEMP5[31:16];DEST[111:96] := TEMP6[31:16];DEST[127:112] := TEMP7[31:16];Figure 4-12.  PMULHUW and PMULHW Inst ruction Operation Us ing 64-bit OperandsX3 X2 X1 X0
Z3 = X3 ∗ Y3 Z2 = X2 ∗ Y2 Z1 = X1 ∗ Y1 Z0 = X0 ∗ Y0SRC
DEST
TEMP
Z3[31:16] Z2[31:16] Z1[31:16] Z0[31:16]PMULHUW—Multiply Packed Unsigned  Integers and Store High ResultINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-375VPMULHUW (VEX.128 Encoded Version)
TEMP0[31:0] := SRC1[15:0] * SRC2[15:0]TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]DEST[15:0] := TEMP0[31:16]DEST[31:16] := TEMP1[31:16]DEST[47:32] := TEMP2[31:16]DEST[63:48] := TEMP3[31:16]DEST[79:64] := TEMP4[31:16]DEST[95:80] := TEMP5[31:16]DEST[111:96] := TEMP6[31:16]DEST[127:112] := TEMP7[31:16]DEST[MAXVL-1:128] := 0
PMULHUW (VEX.256 Encoded Version)
TEMP0[31:0] := SRC1[15:0] * SRC2[15:0]TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]TEMP8[31:0] := SRC1[143:128] * SRC2[143:128]TEMP9[31:0] := SRC1[159:144] * SRC2[159:144]TEMP10[31:0] := SRC1[175:160] * SRC2[175:160]TEMP11[31:0] := SRC1[191:176] * SRC2[191:176]TEMP12[31:0] := SRC1[207:192] * SRC2[207:192]TEMP13[31:0] := SRC1[223:208] * SRC2[223:208]TEMP14[31:0] := SRC1[239:224] * SRC2[239:224]TEMP15[31:0] := SRC1[255:240] * SRC2[255:240]DEST[15:0] := TEMP0[31:16]DEST[31:16] := TEMP1[31:16]DEST[47:32] := TEMP2[31:16]DEST[63:48] := TEMP3[31:16]DEST[79:64] := TEMP4[31:16]DEST[95:80] := TEMP5[31:16]DEST[111:96] := TEMP6[31:16]DEST[127:112] := TEMP7[31:16]DEST[143:128] := TEMP8[31:16]DEST[159:144] := TEMP9[31:16]DEST[175:160] := TEMP10[31:16]DEST[191:176] := TEMP11[31:16]DEST[207:192] := TEMP12[31:16]DEST[223:208] := TEMP13[31:16]DEST[239:224] := TEMP14[31:16]DEST[255:240] := TEMP15[31:16]DEST[MAXVL-1:256] := 0PMULHUW—Multiply Packed Unsigned Integers and Store High ResultINSTRUCTION SET REFERENCE, M-U
4-376 Vol. 2BPMULHUW (EVEX Encoded Versions)
THEN 
temp[31:0] := SRC1[i+15:i] * SRC2[i+15:i]DEST[i+15:i] := tmp[31:16]
ELSE 
FI
FI;
VPMULHUW __m512i _mm512_mulhi_epu16(__m512i a, __m512i b);
VPMULHUW __m512i _mm512_mask_mulhi_epu16(__m51 2i s, __mmask32 k, __m512i a, __m512i b);
VPMULHUW __m512i _mm512_maskz_mulhi_epu 16( __mmask32 k, __m512i a, __m512i b);
VPMULHUW __m256i _mm256_mask_mulhi_epu16(__m25 6i s, __mmask16 k, __m256i a, __m256i b);
VPMULHUW __m256i _mm256_maskz_mulhi_epu 16( __mmask16 k, __m256i a, __m256i b);
VPMULHUW __m128i _mm_mask_mulhi_epu16(__m1 28i s, __mmask8 k, __m128i a, __m128i b);
VPMULHUW __m128i _mm_maskz_mulhi_epu16( __mmask8 k, __m128i a, __m128i b);PMULHUW __m64 _mm_mulhi_pu16(__m64 a, __m64 b)(V)PMULHUW __m128i _mm_mulhi_epu16 ( __m128i a, __m128i b)VPMULHUW __m256i _mm256_mulhi_epu16 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PMULHW—Multiply Packed Signed Integers and Store High ResultINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-377PMULHW—Multiply Packed Signed Integers and Store High Result
Performs a SIMD signed multiply of the packed signed word  integers in the destination operand (first operand) and 
the source operand (second operand), and stores the high 16 bits of each intermediate 32 -bit result in the destina-
tion operand. (Figure 4-12 shows this operation when using 64-bit operands.) 
n 64-bit mode and not encoded with VEX/EVEX, using a REX pr efix in the form of REX.R permits this instruction to 
Mode 
Feature 
NP 0F E5 /r1
PMULHW mm, mm/m64
NOTES:
ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Excepti on Conditions of Legacy SIMD Instructions Operating on MMX Reg -
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V MMX Multiply the packed signed word integers in mm1 
register and mm2/m64, and store the high 16 
bits of the results in mm1. 
66 0F E5 /r
PMULHW xmm1, xmm2/m128A V/V SSE2 Multiply the packed signed word integers in 
xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1. 
VEX.128.66.0F.WIG E5 /r
VPMULHW xmm1, xmm2, xmm3/m128B V/V AVX Multiply the packed signed word integers in

Mode 
Feature 
NP 0F E5 /r1
NOTES:
66 0F E5 /r
VPMULHW xmm1, xmm2, xmm3/m128B V/V AVX Multiply the packed signed word integers in 
xmm2 and xmm3/m128, and store the high 16 
bits of the results in xmm1.
VEX.256.66.0F.WIG E5 /r
VPMULHW ymm1, ymm2, ymm3/m256B V/V AVX2 Multiply the packed signed word integers in 
ymm2 and ymm3/m256, an d store the high 16 
bits of the results in ymm1.
EVEX.128.66.0F.WIG E5 /r
VPMULHW xmm1 {k1}{z }, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWMultiply the packed signed word integers in 
bits of the results in xmm1 under writemask k1.
EVEX.256.66.0F.WIG E5 /r
VPMULHW ymm1 {k1}{z}, ymm2, ymm3/m256C V/V AVX512VL
bits of the results in ymm1 under writemask k1.
EVEX.512.66.0F.WIG E5 /r
VPMULHW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Multiply the packed  signed word integers in 
bits of the results in zmm1 under writemask k1.
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMULHW—Multiply Packed Signed Integers and Store High ResultINSTRUCTION SET REFERENCE, M-U
4-378 Vol. 2BVEX.128 encoded version: The first source and destinat ion operands are XMM registers. The second source 
Operation
PMULHW (With 64-bit Operands)
TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
DEST[15:0] := TEMP0[31:16];
DEST[31:16] := TEMP1[31:16];DEST[47:32] := TEMP2[31:16];DEST[63:48] := TEMP3[31:16];
PMULHW (With 128-bit Operands)
∗ SRC[15:0]; (* Signed multiplication *)
DEST[15:0] := TEMP0[31:16];DEST[31:16] := TEMP1[31:16];DEST[47:32] := TEMP2[31:16];DEST[63:48] := TEMP3[31:16];DEST[79:64] := TEMP4[31:16];DEST[95:80] := TEMP5[31:16];DEST[111:96] := TEMP6[31:16];DEST[127:112] := TEMP7[31:16];
VPMULHW (VEX.128 Encoded Version)
TEMP0[31:0] := SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]DEST[15:0] := TEMP0[31:16]DEST[31:16] := TEMP1[31:16]DEST[47:32] := TEMP2[31:16]DEST[63:48] := TEMP3[31:16]DEST[79:64] := TEMP4[31:16]DEST[95:80] := TEMP5[31:16]PMULHW—Multiply Packed Signed Integers and Store High ResultINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-379DEST[111:96] := TEMP6[31:16]
DEST[127:112] := TEMP7[31:16]DEST[MAXVL-1:128] := 0
PMULHW (VEX.256 Encoded Version)
TEMP0[31:0] := SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]TEMP8[31:0] := SRC1[143:128] * SRC2[143:128]TEMP9[31:0] := SRC1[159:144] * SRC2[159:144]TEMP10[31:0] := SRC1[175:160] * SRC2[175:160]TEMP11[31:0] := SRC1[191:176] * SRC2[191:176]TEMP12[31:0] := SRC1[207:192] * SRC2[207:192]TEMP13[31:0] := SRC1[223:208] * SRC2[223:208]TEMP14[31:0] := SRC1[239:224] * SRC2[239:224]TEMP15[31:0] := SRC1[255:240] * SRC2[255:240]DEST[15:0] := TEMP0[31:16]DEST[31:16] := TEMP1[31:16]DEST[47:32] := TEMP2[31:16]DEST[63:48] := TEMP3[31:16]DEST[79:64] := TEMP4[31:16]DEST[95:80] := TEMP5[31:16]DEST[111:96] := TEMP6[31:16]DEST[127:112] := TEMP7[31:16]DEST[143:128] := TEMP8[31:16]DEST[159:144] := TEMP9[31:16]DEST[175:160] := TEMP10[31:16]DEST[191:176] := TEMP11[31:16]DEST[207:192] := TEMP12[31:16]DEST[223:208] := TEMP13[31:16]DEST[239:224] := TEMP14[31:16]DEST[255:240] := TEMP15[31:16]DEST[MAXVL-1:256] := 0PMULHW—Multiply Packed Signed Integers and Store High ResultINSTRUCTION SET REFERENCE, M-U
4-380 Vol. 2BPMULHW (EVEX Encoded Versions)
THEN 
ELSE 
FI
FI;
VPMULHW __m512i _mm512_mulhi_epi16(__m512i a, __m512i b);
VPMULHW __m512i _mm512_mask_mulhi_epi16(__m512i  s, __mmask32 k, __m512i a, __m512i b);
VPMULHW __m512i _mm512_maskz_mulhi_epi16( __mmask32 k, __m512i a, __m512i b);VPMULHW __m256i _mm256_mask_mulhi_epi16(__m256i  s, __mmask16 k, __m256i a, __m256i b);
VPMULHW __m256i _mm256_maskz_mulhi_epi16( __mmask16 k, __m256i a, __m256i b);VPMULHW __m128i _mm_mask_mulhi_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHW __m128i _mm_maskz_mulhi_epi16( __mmask8 k, __m128i a, __m128i b);
PMULHW __m64 _mm_mulhi_pi16 (__m64 m1, __m64 m2)(V)PMULHW __m128i _mm_mulhi_epi16 ( __m128i a, __m128i b)VPMULHW __m256i _mm256_mulhi_epi16 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PMULLD/PMULLQ—Multiply Packed Integers and Store Low ResultINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-381PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result
Performs a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source 
operand with the corresponding element in the second so urce operand. The low 32/64 bits of each 64/128-bit 
intermediate results are stored to the destination operand. 
operand is an XMM register or a 128-bit memory locati on. Bits (MAXVL-1:128) of the corresponding ZMM destina-
operand is an XMM register or a 128-bit memory location . Bits (MAXVL-1:128) of the corresponding ZMM register 
or 256-bit memory location. Bits (M AXVL-1:256) of the corresponding destination ZMM register are zeroed.Opcode/
Mode 
Feature 
66 0F 38 40 /r
PMULLD xmm1, xmm2/m128A V/V SSE4_1 Multiply the packed dword signed integers in xmm1 and 
xmm2/m128 and store the low 32  bits of each product in 
xmm1.
VEX.128.66.0F38.WIG 40 /r
VPMULLD xmm1, xmm2, xmm3/m128B V/V AVX Multiply the packed dword signed integers in xmm2 and 
xmm3/m128 and store the low 32  bits of each product in 
xmm1.
VEX.256.66.0F38.WIG 40 /r
VPMULLD ymm1, ymm2, 
ymm3/m256B V/V AVX2 Multiply the packed dword signed integers in ymm2 and 
ymm3/m256 and store the low 32 bits of each product in 
ymm1.
EVEX.128.66.0F38.W0 40 /r
VPMULLD xmm1 {k1}{z}, xmm2, 
AVX512FMultiply the packed dword signed integers in xmm2 and 
xmm3/m128/m32bcst and store the low 32 bits of each 
product in xmm1 under writemask k1.
EVEX.256.66.0F38.W0 40 /r
VPMULLD ymm1 {k1}{z}, ymm2, 
AVX512FMultiply the packed dword signed integers in ymm2 and 
ymm3/m256/m32bcst and store the low 32 bits of each 
product in ymm1 under writemask k1.
EVEX.512.66.0F38.W0 40 /r
VPMULLD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstC V/V AVX512F Multiply the packed dword signed integers in zmm2 and 
zmm3/m512/m32bcst and store the low 32 bits of each product in zmm1 under writemask k1.
EVEX.128.66.0F38.W1 40 /r
VPMULLQ xmm1 {k1}{z}, xmm2, 
AVX512DQMultiply the packed qword signed integers in xmm2 and 
xmm3/m128/m64bcst and store the low 64 bits of each

ymm1.
xmm3/m128/m64bcst and store the low 64 bits of each 
EVEX.256.66.0F38.W1 40 /r
VPMULLQ ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcstC V/V AVX512VLA
VX512DQMultiply the packed qword signed integers in ymm2 and 
ymm3/m256/m64bcst and store the low 64 bits of each 
EVEX.512.66.0F38.W1 40 /r
VPMULLQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512DQ Multiply the packed qword signed integers in zmm2 and 
zmm3/m512/m64bcst and store the low 64 bits of each product in zmm1 under writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMULLD/PMULLQ—Multiply Packed Integers and Store Low ResultINSTRUCTION SET REFERENCE, M-U
4-382 Vol. 2BEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a 
Operation
VPMULLQ (EVEX Encoded Versions)
THEN Temp[127:0] := SR C1[i+63:i] * SRC2[63:0]
ELSE Temp[127:0] := SRC1[i+63:i] * SRC2[i+63:i]
FI;DEST[i+63:i] := Temp[63:0]
ELSE 
FI
FI;
VPMULLD (EVEX Encoded Versions)
THEN Temp[63:0] := SRC1[i+31:i] * SRC2[31:0]ELSE Temp[63:0] := SRC1 [i+31:i] * SRC2[i+31:i]
FI;DEST[i+31:i] := Temp[31:0]
ELSE 
*DEST[i+31:i] remains unchanged*ELSE ; zeroing-masking
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0PMULLD/PMULLQ—Multiply Packed Integers and Store Low ResultINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-383VPMULLD (VEX.256 Encoded Version)
Temp0[63:0] := SRC1[31:0] * SRC2[31:0]Temp1[63:0] := SRC1[63:32] * SRC2[63:32]Temp2[63:0] := SRC1[95:64] * SRC2[95:64]Temp3[63:0] := SRC1[127:96] * SRC2[127:96]Temp4[63:0] := SRC1[159:128] * SRC2[159:128]Temp5[63:0] := SRC1[191:160] * SRC2[191:160]Temp6[63:0] := SRC1[223:192] * SRC2[223:192]Temp7[63:0] := SRC1[255:224] * SRC2[255:224]
DEST[31:0] := Temp0[31:0]
DEST[63:32] := Temp1[31:0]DEST[95:64] := Temp2[31:0]DEST[127:96] := Temp3[31:0]DEST[159:128] := Temp4[31:0]DEST[191:160] := Temp5[31:0]DEST[223:192] := Temp6[31:0]DEST[255:224] := Temp7[31:0]DEST[MAXVL-1:256] := 0
VPMULLD (VEX.128 Encoded Version)
Temp0[63:0] := SRC1[31:0] * SRC2[31:0]Temp1[63:0] := SRC1[63:32] * SRC2[63:32]Temp2[63:0] := SRC1[95:64] * SRC2[95:64]Temp3[63:0] := SRC1[127:96] * SRC2[127:96]DEST[31:0] := Temp0[31:0]DEST[63:32] := Temp1[31:0]DEST[95:64] := Temp2[31:0]DEST[127:96] := Temp3[31:0]DEST[MAXVL-1:128] := 0
PMULLD (128-bit Legacy SSE Version)
Temp0[63:0] := DEST[31:0] * SRC[31:0]Temp1[63:0] := DEST[63:32] * SRC[63:32]Temp2[63:0] := DEST[95:64] * SRC[95:64]Temp3[63:0] := DEST[127:96] * SRC[127:96]DEST[31:0] := Temp0[31:0]DEST[63:32] := Temp1[31:0]DEST[95:64] := Temp2[31:0]DEST[127:96] := Temp3[31:0]DEST[MAXVL-1:128 ] (Unmodified)PMULLD/PMULLQ—Multiply Packed Integers and Store Low ResultINSTRUCTION SET REFERENCE, M-U
4-384 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VPMULLD __m512i _mm512_mullo_e pi32(__m512i a, __m512i b);
VPMULLD __m512i _mm512_mask_mullo_epi32(__m512i  s, __mmask16 k, __m512i a, __m512i b);
VPMULLD __m512i _mm512_maskz_mullo_epi32 ( __mmask16 k, __m512i a, __m512i b);
VPMULLD __m256i _mm256_mask_mullo_epi32(__m25 6i s, __mmask8 k, __m256i a, __m256i b);
VPMULLD __m256i _mm256_maskz_mullo_epi32 ( __mmask8 k, __m256i a, __m256i b);
VPMULLD __m128i _mm_mask_mullo _epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);
VPMULLD __m256i _mm256_mullo_e pi32(__m256i a, __m256i b);
PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);VPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);VPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i  s, __mmask8 k, __m512i a, __m512i b);
VPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);VPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);VPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i  s, __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);VPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);VPMULLQ __m128i _mm_mask_mullo_epi64(__m128i  s, __mmask8 k, __m128i a, __m128i b);
VPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PMULLW—Multiply Packed Signed Integers and Store Low ResultINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-385PMULLW—Multiply Packed Signed Integers and Store Low Result
the source operand (second operand), and stores the low 16 bits of each intermediate 32-bit result in the destina-
tion operand. (Figure 4-12 shows this operation when using 64-bit operands.)
Mode 
Feature 
NP 0F D5 /r1
PMULLW mm, mm/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V MMX Multiply the packed signed word integers in 
mm1 register and mm2/m64, and store the low 
16 bits of the results in mm1. 
66 0F D5 /r
PMULLW xmm1, xmm2/m128A V/V SSE2 Multiply the packed signed word integers in 
xmm1 and xmm2/m128, and store the low 16 bits of the results in xmm1. 
VEX.128.66.0F.WIG D5 /r
VPMULLW xmm1, xmm2, xmm3/m128B V/V AVX Multiply the packed dword signed integers in 
xmm2 and xmm3/m128 and store the low 32 
bits of each product in xmm1.
VEX.256.66.0F.WIG D5 /r
VPMULLW ymm1, ymm2, ymm3/m256B V/V AVX2 Multiply the packed signed word integers in 
ymm2 and ymm3/m256, and store the low 16 
EVEX.128.66.0F.WIG D5 /r
VPMULLW xmm1 {k1}{z }, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWMultiply the packed sign ed word integers in 
xmm2 and xmm3/m128, and store the low 16 
EVEX.256.66.0F.WIG D5 /r
VPMULLW ymm1 {k1}{z }, ymm2, ymm3/m256C V/V AVX512VL
ymm2 and ymm3/m256, and store the low 16 bits of the results in ymm1 under writemask k1.
EVEX.512.66.0F.WIG D5 /r
VPMULLW zmm1 {k1}{z }, zmm2, zmm3/m512C V/V AVX512BW Multiply the packed  signed word integers in 
zmm2 and zmm3/m512, and store the low 16 
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APMULLW—Multiply Packed Signed Integers and Store Low ResultINSTRUCTION SET REFERENCE, M-U
4-386 Vol. 2BVEX.128 encoded version: The first source and destinat ion operands are XMM registers. The second source 
ZMM/YMM/XMM register, a 512/256/128-bit memory locati on. The destination operand is conditionally updated 
Operation
PMULLW (With 64-bit Operands)

Operation
DEST[15:0] := TEMP0[15:0];DEST[31:16] := TEMP1[15:0];DEST[47:32] := TEMP2[15:0];DEST[63:48] := TEMP3[15:0];
PMULLW (With 128-bit Operands)
DEST[15:0] := TEMP0[15:0];DEST[31:16] := TEMP1[15:0];DEST[47:32] := TEMP2[15:0];DEST[63:48] := TEMP3[15:0];DEST[79:64] := TEMP4[15:0];DEST[95:80] := TEMP5[15:0];DEST[111:96] := TEMP6[15:0];DEST[127:112] := TEMP7[15:0];
DEST[MAXVL-1:256] := 0Figure 4-13.  PMULLU Instruction Operation Using 64-bit OperandsX3 X2 X1 X0
DEST
TEMP
Z3[15:0] Z2[15:0] Z1[15:0] Z0[15:0]PMULLW—Multiply Packed Signed Integers and Store Low ResultINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-387VPMULLW (VEX.128 Encoded Version)
Temp0[31:0] := SRC1[15:0] * SRC2[15:0]Temp1[31:0] := SRC1[31:16] * SRC2[31:16]Temp2[31:0] := SRC1[47:32] * SRC2[47:32]Temp3[31:0] := SRC1[63:48] * SRC2[63:48]Temp4[31:0] := SRC1[79:64] * SRC2[79:64]Temp5[31:0] := SRC1[95:80] * SRC2[95:80]Temp6[31:0] := SRC1[111:96] * SRC2[111:96]Temp7[31:0] := SRC1[127:112] * SRC2[127:112]DEST[15:0] := Temp0[15:0]DEST[31:16] := Temp1[15:0]DEST[47:32] := Temp2[15:0]DEST[63:48] := Temp3[15:0]DEST[79:64] := Temp4[15:0]DEST[95:80] := Temp5[15:0]DEST[111:96] := Temp6[15:0]DEST[127:112] := Temp7[15:0]DEST[MAXVL-1:128] := 0
PMULLW (EVEX Encoded Versions)
THEN 
temp[31:0] := SRC1[i+15:i] * SRC2[i+15:i]DEST[i+15:i] := temp[15:0]
ELSE 
FI
FI;
VPMULLW __m512i _mm512_mullo_epi16(__m512i a, __m512i b);
VPMULLW __m512i _mm512_mask_mullo_epi16(__m512 i s, __mmask32 k, __m512i a, __m512i b);
VPMULLW __m512i _mm512_maskz_mullo_epi16( __mmask32 k, __m512i a, __m512i b);VPMULLW __m256i _mm256_mask_mullo_epi16(__m256 i s, __mmask16 k, __m256i a, __m256i b);
VPMULLW __m256i _mm256_maskz_mullo_epi16( __mmask16 k, __m256i a, __m256i b);VPMULLW __m128i _mm_mask_mullo_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMULLW __m128i _mm_maskz_mullo_epi16( __mmask8 k, __m128i a, __m128i b);PMULLW __m64 _mm_mullo_pi16(__m64 m1, __m64 m2)(V)PMULLW __m128i _mm_mullo_epi16 ( __m128i a, __m128i b)VPMULLW __m256i _mm256_mullo_epi16 ( __m256i a, __m256i b);
None.PMULLW—Multiply Packed Signed Integers and Store Low ResultINSTRUCTION SET REFERENCE, M-U
4-388 Vol. 2BSIMD Floating-Point Exceptions
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PMULUDQ—Multiply Packed Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-389PMULUDQ—Multiply Packed Unsigned Doubleword Integers
Multiplies the first operand (destination operand) by the second operand (source operand) and stores the result in 
the destination operand. 
Legacy SSE version 64-bit operand: The source operand can be an unsigned doubleword integer stored in the low 
doubleword of an MMX technology register or a 64-bit  memory location. The destination operand can be an 
unsigned doubleword integer stored in the low doubleword an MMX technology register. The result is an unsigned Opcode/
Mode 
Feature 
NP 0F F4 /r1
PMULUDQ mm1, mm2/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSE2 Multiply unsigned do ubleword integer in mm1 by 
unsigned doubleword integer in mm2/m64, and 
store the quadword result in mm1. 
66 0F F4 /r
PMULUDQ xmm1, xmm2/m128A V/V SSE2 Multiply packed unsign ed doubleword integers in 
xmm1 by packed unsigned doubleword integers in xmm2/m128, and store the quadword results 
in xmm1. 
VEX.128.66.0F.WIG F4 /r
VPMULUDQ xmm1, xmm2, xmm3/m128B V/V AVX Multiply packed unsigned doubleword integers in 
xmm2 by packed unsigned doubleword integers in xmm3/m128, and store the quadword results 
in xmm1.
VEX.256.66.0F.WIG F4 /r
VPMULUDQ ymm1, ymm2, ymm3/m256B V/V AVX2 Multiply packed unsign ed doubleword integers in 
ymm2 by packed unsigned doubleword integers 
in ymm3/m256, and store the quadword results 
in ymm1.
EVEX.128.66.0F.W1 F4 /r
VPMULUDQ xmm1 {k1}{z}, xmm2, 
AVX512FMultiply packed unsigned doubleword integers in 
xmm2 by packed unsigned doubleword integers 
in xmm3/m128/m64bcst, and store the 
quadword results in xmm1 under writemask k1.
EVEX.256.66.0F.W1 F4 /r
VPMULUDQ ymm1 {k1}{z}, ymm2, 
in ymm3/m256/m64bcst, and store the 
quadword results in ymm1 under writemask k1.
EVEX.512.66.0F.W1 F4 /r
VPMULUDQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Multiply packed unsigned doubleword integers in 
zmm2 by packed unsigned doubleword integers 
in zmm3/m512/m64bcst, and store the 
quadword results in zmm1 under writemask k1.
CF u l l M o d R M : r e g  ( w )E V E X . vvvv (r) ModRM:r/m (r) N/APMULUDQ—Multiply Packed Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, M-U
4-390 Vol. 2Bquadword integer stored in the destinat ion an MMX technology register. When a quadword result is too large to be 
represented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the destination 
element (that is, the carry is ignored).
For 64-bit memory operands, 64 bits are fetched from memo ry, but only the low doubleword is used in the compu-
tation.
128-bit Legacy SSE version: The second source operand is  two packed unsigned doubleword integers stored in the 
first (low) and third doublewords of an XMM register or  a 128-bit memory location. For 128-bit memory operands, 
128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first 
source operand is two packed unsigned  doubleword integers stored in the first and third doublewords of an XMM 
register. The destination contains two packed unsigned quadword integers stor ed in an XMM register. Bits (MAXVL-
1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is two packed unsigned doubleword integers stored in the 
1:128) of the destination YMM register are zeroed. 
VEX.256 encoded version: The second source operand is fo ur packed unsigned doubleword integers stored in the 
first (low), third, fifth, and seventh doublewords of a YMM register or a 256-bit memory location. For 256-bit 
memory operands, 256 bits are fetched from memory, but on ly the first, third, fifth, and seventh doublewords are 
used in the computation. The first source operand is four packed unsigned doubleword integers stored in the first, 
third, fifth, and seventh doublewords of an YMM register. The destination contains four packed unaligned quadword 
integers stored in an YMM register.
EVEX encoded version: The input unsigned doubleword in tegers are taken from the even-numbered elements of 
the source operands. The first source operand is a ZMM/YMM/XMM registers. Th e second source operand can be an

the source operands. The first source operand is a ZMM/YMM/XMM registers. Th e second source operand can be an 
Operation
PMULUDQ (With 64-Bit Operands)
DEST[63:0] := DEST[31:0] ∗ SRC[31:0];
PMULUDQ (With 128-Bit Operands)
DEST[127:64] := DEST[95:64] ∗ SRC[95:64];
VPMULUDQ (VEX.128 Encoded Version)
DEST[63:0] := SRC1[31:0] * SRC2[31:0]DEST[127:64] := SRC1[95:64] * SRC2[95:64]DEST[MAXVL-1:128] := 0
VPMULUDQ (VEX.256 Encoded Version)
DEST[63:0] := SRC1[31:0] * SRC2[31:0]DEST[127:64] := SRC1[95:64] * SRC2[95:64DEST[191:128] := SRC1[1 59:128] * SRC2[159:128]
DEST[255:192] := SRC1[2 23:192] * SRC2[223:192]
DEST[MAXVL-1:256] := 0PMULUDQ—Multiply Packed Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-391VPMULUDQ (EVEX Encoded Versions)
THEN DEST[i+63:i] := ZeroExtend64( SRC1 [i+31:i]) * ZeroExtend64( SRC2[31:0] )
ELSE DEST[i+63:i] := ZeroExtend64( SRC1 [i+31:i]) * ZeroExtend64( SRC2[i+31:i] )
FI;
ELSE 
FI
FI;
VPMULUDQ __m512i _mm512_mul_epu32(__m512i a, __m512i b);
VPMULUDQ __m512i _mm512_mask_mul_epu32(__m512i s, __mmask8 k, __m512i a, __m512i b);VPMULUDQ __m512i _mm512_maskz_mul_epu32( __mmask8 k, __m512i a, __m512i b);VPMULUDQ __m256i _mm256_mask_mul_epu32(__m256i s, __mmask8 k, __m256i a, __m256i b);VPMULUDQ __m256i _mm256_maskz_mul_epu32( __mmask8 k, __m256i a, __m256i b);VPMULUDQ __m128i _mm_mask_mul_epu32(__m128 i s, __mmask8 k, __m128i a, __m128i b);
VPMULUDQ __m128i _mm_maskz_mul_epu32( __mmask8 k, __m128i a, __m128i b);PMULUDQ __m64 _mm_mul_su32 (__m64 a, __m64 b)(V)PMULUDQ __m128i _mm_mul_epu32 ( __m128i a, __m128i b)VPMULUDQ __m256i _mm256_mul_epu32( __m256i a, __m256i b);
None.
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”POP—Pop a Value From the StackINSTRUCTION SET REFERENCE, M-U
4-392 Vol. 2BPOP—Pop a Value From the Stack
Loads the value from the top of the stack to the location specified with the destination operand (or explicit opcode) 
and then increments the stack pointer. The destination operand can be a general-purpose register, memory loca-
tion, or segment register.
Address and operand sizes are determined and used as follows:
•Address size. The D flag in the current code-segment de scriptor determines the defaul t address size; it may be 
overridden by an instruction prefix (67H).
The address size is used only when writ ing to a destination operand in memory.
•Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may 
be overridden by instruction prefixes (66H or REX.W).
The operand size (16, 32, or 64 bits) determines the am ount by which the stack pointer is incremented (2, 4
or 8).
•Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the 
size of the stack pointer (16 or 32 bits); in 64-bit mode, the size of the stack pointer is always 64 bits.
The stack-address size determines the width of the stac k pointer when reading from the stack in memory and
when incrementing the stack pointer. (As stated above,  the amount by which the stack pointer is incremented
is determined by the operand size.)
If the destination operand is one of the segment registers DS, ES, FS, GS, or SS, the value loaded into the register 
must be a valid segment selector. In protected mode, popp ing a segment selector into a segment register automat-Opcode Instruction Op/ 
En64-Bit 
8F /0 POP r/m16 M Valid Valid Pop top of st ack into m16; increment stack pointer.
8F /0 POP r/m32 M N.E. Valid Pop top of st ack into m32; increment stack pointer.
8F /0 POP r/m64 M Valid N.E. Pop top of stack into m64; increment stack pointer. Cannot 
encode 32-bit operand size.
58+ rw POP r16 O Valid Valid Pop top of stac k into r16; increment stack pointer.
58+ rd POP r32 O N.E. Valid Pop top of stac k into r32; increment stack pointer.
58+ rd POP r64 O Valid N.E. Pop top of stack in to r64; increment stack pointer. Cannot 
1F POP DS ZO Invalid Valid Pop top of stac k into DS; increment stack pointer.
07 POP ES ZO Invalid Valid Pop top of stack into ES; increment stack pointer.17 POP SS ZO Invalid Valid Pop top of stack into SS; increment stack pointer.0F A1 POP FS ZO Valid Valid Pop top of stack in to FS; increment stack pointer by 16 bits. 
0F A1 POP FS ZO N.E. Valid Pop top of stack in to FS; increment stack pointer by 32 bits. 
0F A1 POP FS ZO Valid N.E. Pop top of stack in to FS; increment stack pointer by 64 bits. 
0F A9 POP GS ZO Valid Valid Pop top of stack into GS; increment stack pointer by 16 bits. 0F A9 POP GS ZO N.E. Valid Pop top of stack into GS; increment stack pointer by 32 bits. 0F A9 POP GS ZO Valid N.E. Pop top of stack into GS; increment stack pointer by 64 bits. 
O opcode + rd (w) N/A N/A N/A
ZO N/A N/A N/A N/APOP—Pop a Value From the StackINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-393ically causes the descriptor information associated with that segment selector to be loaded into the hidden 
(shadow) part of the segment register and causes the selector and the descriptor information to be validated (see the “Operation” section below).
A NULL value (0000-0003) may be popped into the DS, ES, FS , or GS register without causing a general protection 
fault. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded 
with a NULL value causes a general protection exception (# GP). In this situation, no memory reference occurs and 
the saved value of the segment register is NULL.
The POP instruction cannot pop a value into the CS register . To load the CS register from the stack, use the RET 
If the ESP register is used as a base register for addr essing a destination operand in  memory, the POP instruction 
computes the effective address of the operand after it incr ements the ESP register. For the case of a 16-bit stack 
where ESP wraps to 0H as a result of the POP instruction,  the resulting location of the memory write is processor-
family-specific.
The POP ESP instruction in crements the stack pointer (ESP) before data at the old top of stack is written into the 
destination.
Loading the SS register with a POP instruction suppresses or inhibits some debug exceptions and inhibits interrupts 
on the following instruction boundary. (The inhibition ends  after delivery of an exception or the execution of the 
next instruction.) This behavior allows a stack pointer to be loaded into the ESP register with the next instruction 
(POP ESP) before an event can be delivered. See Sect ion 6.8.3, “Masking Exceptions and Interrupts When 
Switching Stacks,” in the Intel
® 64 and IA-32 Architectures Software Deve loper’s Manual, Volume 3A. Intel recom-
mends that software use the LSS instruction to load the SS register and ESP together.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). When in 
64-bit mode, POPs using 32-bit operands are not encoda ble and POPs to DS, ES, SS are not valid. See the 
Operation
IF StackAddrSize = 32
THEN
THEN
DEST := SS:ESP; (* Copy a doubleword *)ESP := ESP + 4;
= 16*)
DEST := SS:ESP; (* Copy a word *)ESP := ESP + 2;
FI;
ELSE IF StackAddrSize = 64
THEN
 = 64
THEN
DEST := SS:RSP; (* Copy quadword *)RSP := RSP + 8;
ELSE (* OperandSize = 16*)
DEST := SS:RSP; (* Copy a word *)RSP := RSP + 2;
FI;
FI;
ELSE StackAddrSize
 = 16
THEN
IF OperandSize  = 16
THEN
DEST := SS:SP; (* Copy a word *)SP := SP + 2;POP—Pop a Value From the StackINSTRUCTION SET REFERENCE, M-U
4-394 Vol. 2BELSE (* OperandSize = 32 *)
DEST := SS:SP; (* Copy a doubleword *)
SP := SP + 4;
FI;
FI;
Loading a segment register while in protected mode results in  special actions, as described in the following listing. 
These checks are performed on the segment sele ctor and the segment descriptor it points to.
IF FS, or GS is  loaded with no n-NULL selector;
THEN
OR segment is not a data or readable code segmentOR ((segment is a data or nonconforming code segment)

= 16*)
FI;
THEN
 = 64
THEN
FI;
FI;
 = 16
THEN
THEN
SP := SP + 4;
FI;
FI;
THEN
AND ((RPL > DPL) or (CPL > DPL))
THEN #GP(selector);
THEN #NP(selector);
ELSE
FI;
FI;IF FS, or GS is loaded  with a NULL selector;
THEN
FI;
IF SS is loaded;
THEN
THEN #GP(0); 
FI;IF segment selector index is ou tside descriptor table limits 
or segment selector's RPL 
≠ CPL
or segment is not a wr itable data segment
or DPL  ≠ CPL
THEN #GP(selector); 
FI;IF segment not marked present 
SS := segment selector;SS := segment descriptor; 
FI;
FI;
IF DS, ES, FS, or GS is load ed with non-NULL selector;
THENPOP—Pop a Value From the StackINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-395IF segment selector index is outside descriptor table limits
or segment is not a data or readable code segmentor ((segment is a data or nonconforming code segment)and ((RPL > DPL) or (CPL > DPL))
FI;IF segment not marked present
 FI;
FI;
IF DS, ES, FS, or GS is lo aded with a NULL selector
THEN
FI;
None.
If the destination operand is in a non-writable segment.If a memory operand effective address is outs ide the CS, DS, ES, FS, or GS segment limit.
selector.
If the SS register is being loaded  and the segment pointed to is a
#SS(0) If the current top of stack is not within the stack segment.
#SS(selector) If the SS register is being loaded and the segment pointed to is marked not present.#NP If the DS, ES, FS, or GS register is being lo aded and the segment pointed to is marked not 
present.
#PF(fault-code) If a page fault occurs.#AC(0) If an unaligned memory reference is made wh ile the current privilege level is 3 and alignment 
#UD If the LOCK prefix is used.POP—Pop a Value From the StackINSTRUCTION SET REFERENCE, M-U
4-396 Vol. 2BReal-Address Mode Exceptions
#PF(fault-code) If a page fault occurs.#AC(0) If an unaligned memory reference is made while alignment checking is enabled.
#GP(0) If the memory address is in a non-canonical form.#SS(0) If the stack address is in a non-canonical form.
#GP(selector) If the descriptor is outside the descriptor table limit.
If the FS or GS register is being loaded and th e segment pointed to is not a data or readable 
code segment.
If the FS or GS register is being loaded and th e segment pointed to is a data or nonconforming 
code segment, but both the RPL an d the CPL are greater than the DPL.
#AC(0) If an unaligned memory reference is made while alignment checking is enabled.
#PF(fault-code) If a page fault occurs.#NP If the FS or GS register is being loaded and the segment pointed to is marked not present.
If the DS, ES, or SS register is being loaded.POPA/POPAD—Pop All General-Purpose RegistersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-397POPA/POPAD—Pop All General-Purpose Registers
Pops doublewords (POPAD) or words (POPA) from the stack into the general-purpose registers. The registers are 
loaded in the following order: EDI, ESI, EBP, EBX, EDX, ECX, and EAX (if the operand-size attribute is 32) and DI, 
SI, BP, BX, DX, CX, and AX (if the operand-size attribute is  16). (These instructions reverse the operation of the 
PUSHA/PUSHAD instructions.) The value on  the stack for the ESP or SP register is ignored. Instead, the ESP or SP 
register is incremented after each register is loaded.
The POPA (pop all) and POPAD (pop all double) mnemonic s reference the same opcode. The POPA instruction is 
intended for use when the operand-size attribute is 16 and the POPAD instruction for when the operand-size attri-
bute is 32. Some assemblers may force the operand size to 16 when POPA is used and to 32 when POPAD is used 
(using the operand-size override prefix [66H] if nece ssary). Others may treat these mnemonics as synonyms 
(POPA/POPAD) and use the current setting of the operand-si ze attribute to determine the size of values to be 
popped from the stack, regardless of the mnemonic used . (The D flag in the current code segment’s segment 
descriptor determines the operand-size attribute.)
This instruction executes as described in non-64-bit modes. It is not valid in 64-bit mode.
Operation
THEN
#UD;
ELSE
IF OperandSize = 32 (* Instruction =  POPAD *)
THEN
EDI := Pop();ESI := Pop();EBP := Pop();Increment ESP by 4; (* Skip  next 4 bytes of stack *)
EBX := Pop();EDX := Pop();ECX := Pop();EAX := Pop();
ELSE (* OperandSize = 16, instruction = POPA *)
DI := Pop();SI := Pop();BP := Pop();Increment ESP by 2; (* Skip  next 2 bytes of stack *)
BX := Pop();DX := Pop();CX := Pop();AX := Pop();
FI;
En64-Bit 
61 POPA ZO Invalid Valid Pop DI, SI, BP, BX, DX, CX, and AX.
61 POPAD ZO Invalid Valid Pop EDI, ESI,  EBP, EBX, EDX, ECX, and EAX.
ZO N/A N/A N/A N/APOPA/POPAD—Pop All General-Purpose RegistersINSTRUCTION SET REFERENCE, M-U
4-398 Vol. 2BFlags Affected
None.
#SS(0) If the starting or ending stack a ddress is not within the stack segment. 
#SS If the starting or ending stack address is not within the stack segment.#UD If the LOCK prefix is used.
#SS(0) If the starting or ending stack address is not within the stack segment.
#UD If in 64-bit mode.POPCNT—Return the Count of Number of Bits Set to 1INSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-399POPCNT—Return the Count of Number of Bits Set to 1
This instruction calculates the number of bits set to 1 in the second operand (source) and returns the count in the 
first operand (a destination register).
Operation
Count = 0;
For (i=0; i < OperandSize; i++) {  IF (SRC[ i] = 1) // i’th bit
THEN Count++; FI;
}DEST := Count;
OF, SF, ZF, AF, CF, PF are all cleared. ZF is set if SRC = 0, otherwise ZF is cleared.
POPCNT int _mm_popcnt_u32(unsigned int a);POPCNT int64_t _mm_popcnt _u64(unsigned __int64 a);
#AC(0) If an unaligned memory reference is made wh ile the current privilege level is 3 and alignment 
#UD If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
If LOCK prefix is used.Opcode Instruction Op/ 
En64-Bit 
F3 0F B8 /r POPCNT r16, r/m16 RM Valid Valid POPCNT on r/m16
F3 0F B8 /r POPCNT r32, r/m32 RM Valid Valid POPCNT on r/m32F3 REX.W 0F B8 /r POPCNT r64, r/m64 RM Valid N.E. POPCNT on r/m64

En64-Bit 
RM ModRM:reg (w) ModRM:r/m (r) N/A N/APOPCNT—Return the Count of Number of Bits Set to 1INSTRUCTION SET REFERENCE, M-U
4-400 Vol. 2BVirtual 8086 Mode Exceptions
If LOCK prefix is used.POPF/POPFD/POPFQ—Pop Stack Into EFLAGS RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-401POPF/POPFD/POPFQ—Pop Stac k Into EFLAGS Register
Pops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the 
value in the EFLAGS register, or pops a word from the to p of the stack (if the operand-size attribute is 16) and 
stores it in the lower 16 bits of the EFLAGS register (t hat is, the FLAGS register). These instructions reverse the 
operation of the PUSHF/PU SHFD/PUSHFQ instructions. 
The POPF (pop flags) and POPFD (pop flags double) mnem onics reference the same opcode. The POPF instruction 
is intended for use when the operand-size attribute is 16; the POPFD instruction is intended for use when the 
operand-size attribute is 32. Some assemblers may force the operand size to 16 for POPF and to 32 for POPFD. 
Others may treat the mnemonics as synonyms (POPF/POPFD)  and use the setting of the operand-size attribute to 
determine the size of values to pop from the stack.
The effect of POPF/POPFD on the EFLAGS register change s, depending on the mode of operation. See Table 4-16 
and the key below for details.
When operating in protected, compatibility, or 64-bit mode  at privilege level 0 (or in real-address mode, the equiv-
alent to privilege level 0), all non-reserved flags in the EFLAGS register except RF1, VIP, VIF, and VM may be modi-
fied. VIP, VIF, and VM remain unaffected.
When operating in protected, compatibility, or 64-bit mode  with a privilege level greater than 0, but less than or 
equal to IOPL, all flags can be modified except the IOPL fi eld and RF, IF, VIP, VIF, and VM; these remain unaffected. 
The AC and ID flags can only be modified  if the operand-size attribute is 32. The interrupt flag (IF) is altered only 
when executing at a level at least as privileged as the IO PL. If a POPF/POPFD instruction is executed with insuffi-
cient privilege, an exception does not occur but privileged bits do not change.
When operating in virtual-8086 mode (EFLAGS.VM = 1) wi thout the virtual-8086 mode extensions (CR4.VME = 0), 
the POPF/POPFD instructions can be used only if IOPL  = 3; otherwise, a general-protection exception (#GP) 
occurs. If the virtual-8086 mode extensions are enabled (C R4.VME = 1), POPF (but not POPFD) can be executed in 
virtual-8086 mode with IOPL < 3.
(The protected-mode virtual-interrupt feature — enabled by  setting CR4.PVI — affects the CLI and STI instructions 
in the same manner as the virtual-8086 mode extensions. POPF, however, is not affected by CR4.PVI.)
In 64-bit mode, the mnemonic assigned is POPFQ (note th at the 32-bit operand is not encodable). POPFQ pops 64 
bits from the stack. Reserved bits of RFLAGS (inclu ding the upper 32 bits of  RFLAGS) are not affected.
See Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more informa-
tion about the EFLAGS registers.Opcode Instruction Op/ 
En64-Bit 
9D POPF ZO Valid Valid Pop top of stac k into lower 16 bits of EFLAGS.
9D POPFD ZO N.E. Valid Pop top of stack into EFLAGS.
9D POPFQ ZO Valid N.E. Pop top of stack and zero-extend into RFLAGS. 
1. RF is always zero after the execution of POPF. This is because POPF, like all instructions, clears  RF as it begins to execute .POPF/POPFD/POPFQ—Pop Stack Into EFLAGS RegisterINSTRUCTION SET REFERENCE, M-U
4-402 Vol. 2BOperation
IF EFLAGS.VM = 0 (* Not in Virtual-8086 Mode *)
THEN IF CPL = 0 OR CR0.PE = 0
THEN
IF OperandSize = 32;
THEN 
EFLAGS := Pop(); (* 32-bit pop *)(* All non-reserved flags except RF, VIP, VIF, and VM can be modified; 
VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)
ELSE IF (Operandsize = 64)
RFLAGS = Pop(); (* 64-bit pop *)(* All non-reserved flags except RF, VIP, VIF, and VM can be modified; 
VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)Table 4-16.  Effect of POPF/P OPFD on the EFLAGS Register 
ModeOperand
SizeCPL IOPLFlags
Notes21 20 19 18 17 16 14 13:12 11 10 9 8 7 6 4 2 0
ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF
Real-Address 
Mode
(CR0.PE = 0)16 0 0-3 N N N N N0 S S S S S S S S S S S
32 0 0-3 S N N S N0 S S S S S S S S S S S
Protected, 
Compatibility, 
and 64-Bit 
Modes
(CR0.PE = 1 
EFLAGS.VM = 0)16 0 0-3 N N N N N0 S S S S S S S S S S S
16 1-3 <CPL N N N N N0 S N S S N S S S S S S
16 1-3 ≥CPL N N N N N0 S N S S S S S S S S S
32, 64 0 0-3 S N N S N0 S S S S S S S S S S S
32, 64 1-3 <CPL S N N S N0 S N S S N S S S S S S
32, 64 1-3 ≥CPL S N N S N0 S N S S S S S S S S S
(CR0.PE = 1
EFLAGS.VM = 1
CR4.VME = 0)16 3 0-2 X X X X X X X X X X X X X X X X X1
16 3 3 N N N N N0 S N S S S S S S S S S
32 3 0-2 X X X X X X X X X X X X X X X X X1
32 3 3 S N N S N0 S N S S S S S S S S S
VME
(CR0.PE = 1
CR4.VME = 1)16 3 0-2 N/
XN/
XSV/
XN/
XN/
X0/
XS/
XN/X S/
XS/
XN/
XS/
XS/
XS/
XS/
XS/
XS/
X2,3
NOTES:
1. #GP fault - no flag update
2. #GP fault with no flag update  if VIP=1 in EFLAGS register and IF=1 in FLAGS value on stack
3. #GP fault with no fl ag update if TF=1 in FLAGS value on stack
Key
S Updated from stack
SV Updated from IF (bit 9) in FLAGS value on stack
N No change in value
X No EFLAGS update
0 Value is clearedPOPF/POPFD/POPFQ—Pop Stack Into EFLAGS RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-403ELSE (* OperandSize = 16 *)
EFLAGS[15:0] := Pop(); (* 16-bit pop *)(* All non-reserved flags can be modified. *)
FI;
ELSE (* CPL > 0 *)
IF OperandSize =
 32
THEN 
IF CPL > IOPL
THEN
EFLAGS := Pop(); (* 32-bit pop *)(* All non-reserved bits except IF, IOPL , VIP, VIF, VM, and RF can be modified; 
IF, IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
ELSE
EFLAGS := Pop(); (* 32-bit pop *)(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified; 
IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
FI;
THEN
RFLAGS := Pop(); (* 64-bit pop *)(* All non-reserved bits except IF, IOPL , VIP, VIF, VM, and RF can be modified; 
ELSE
RFLAGS := Pop(); (* 64-bit pop *)(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified; 
FI;
ELSE (* OperandSize =
 16 *)
EFLAGS[15:0] := Pop(); (* 16-bit pop *)(* All non-reserved bits except IOPL can be modified; IOPL and all
reserved bits are unaffected. *)
FI;
FI;
ELSE (* In virt ual-8086 mode *)
IF IOPL = 3
THEN
= 32 
THEN 
EFLAGS := Pop();(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified; 
VIP, VIF, VM, IOPL, and all reserved bi ts are unaffected. RF is cleared. *)
ELSE 
EFLAGS[15:0] := Pop(); FI;(* All non-reserved bits except IOPL can be modified; IOPL and all reserved bits are unaffected. *)
FI;
ELSE (* IOPL < 3 *)
IF (Operandsize = 32 ) OR (CR4.VME = 0)
THEN #GP(0); (* Trap to virtual-8086 monitor. *)ELSE (* Operandsize = 16 and CR4.VME = 1 *)
tempFLAGS := Pop();IF (EFLAGS.VIP = 1 AND tempFLAGS[9] = 1) OR tempFLAGS[8] = 1
      THEN #GP(0);      ELSEPOPF/POPFD/POPFQ—Pop Stack Into EFLAGS RegisterINSTRUCTION SET REFERENCE, M-U
4-404 Vol. 2B                  EFLAGS.VIF := tempFLAGS[9];
                  EFLAGS[15:0] := tempFLAGS;                  (* All non-rese rved bits except IOPL and IF can be modified;
IOPL, IF, and all reserved bits are unaffected. *)
FI;
FI;
FI;
FI;
All flags may be affected; see the Operation section for details.
#SS(0) If the top of stack is not within the stack segment.

ELSE 
FI;
FI;
FI;
FI;
FI;
#AC(0) If an unaligned memory reference is made while CPL = 3 and alignment checking is enabled.
#SS If the top of stack is not within the stack segment.#UD If the LOCK prefix is used.
#GP(0) If IOPL < 3 and VME is not enabled.
If IOPL < 3 and the 32-bit operand size is used.
If IOPL < 3, EFLAGS.VIP = 1, and bit 9 (IF)  is set in the FLAGS value on the stack.
If IOPL < 3 and bit 8 (TF) is set in the FLAGS value on the stack.
If an attempt is made to execute the POPF/POPFD instruction with an operand-size override 
prefix.
#SS(0) If the stack address is in a non-canonical form.#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the 
#UD If the LOCK prefix is used.POR—Bitwise Logical ORINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-405POR—Bitwise Logical OR
Performs a bitwise logical OR operation on the source op erand (second operand) and the destination operand (first 
operand) and stores the result in the destination operand. Each  bit of the result is set to 1 if either or both of the 
corresponding bits of the first and second operands are 1; otherwise, it is set to 0.
Mode 
Feature 
NP 0F EB /r1
POR mm, mm/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V MMX Bitwise OR of mm/m64 and mm.
66 0F EB /r
POR xmm1, xmm2/m128A V/V SSE2 Bitwise OR of xmm2/m128 and xmm1.
VEX.128.66.0F.WIG EB /r
VPOR xmm1, xmm2, xmm3/m128BV / V A V X B i t w i s e  O R  o f  xmm2/m128 and xmm3.
VEX.256.66.0F.WIG EB /r
VPOR ymm1, ymm2, ymm3/m256B V/V AVX2 Bitwise OR of ymm2/m256 and ymm3.
EVEX.128.66.0F.W0 EB /r
VPORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst C V/V AVX512VL
AVX512FBitwise OR of packed doubleword integers in 
xmm2 and xmm3/m128/m32bcst using 
EVEX.256.66.0F.W0 EB /r
VPORD ymm1 {k1}{z}, ym m2, ymm3/m256/m32bcst C V/V AVX512VL
ymm2 and ymm3/m256/m32bcst using 
EVEX.512.66.0F.W0 EB /r
VPORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst C V/V AVX512F Bitwise OR of packed doubleword integers in 
zmm2 and zmm3/m512/m32bcst using 
EVEX.128.66.0F.W1 EB /r
VPORQ xmm1 {k1}{z}, xm m2, xmm3/m128/m64bcstC V/V AVX512VL
AVX512FBitwise OR of packed quadword integers in 
xmm2 and xmm3/m128/m64bcst using writemask k1. 
EVEX.256.66.0F.W1 EB /r
VPORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstC V/V AVX512VL
ymm2 and ymm3/m256/m64bcst using 
EVEX.512.66.0F.W1 EB /r
VPORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512F Bitwise OR of pack ed quadword integers in 
zmm2 and zmm3/m512/m64bcst using 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/APOR—Bitwise Logical ORINSTRUCTION SET REFERENCE, M-U
4-406 Vol. 2BLegacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The 
destination operand is an MMX technology register.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first 
source and destination operands can be XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination 
VEX.128 encoded version: The second source operand is an  XMM register or a 128-bit memory location. The first 
source and destination operands can be XMM registers. Bits (MAXVL-1:128) of the destination YMM register are 
zeroed. 
VEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first 
source and destination operands can be YMM registers.
EVEX encoded version: The first source operand is a Z MM/YMM/XMM register. The second source operand can be a 
Operation
POR (64-bit Operand)
DEST := DEST OR SRC
POR (128-bit Legacy SSE Version)
DEST := DEST OR SRCDEST[MAXVL-1:128] (Unmodified)
VPOR (VEX.128 Encoded Version)
DEST := SRC1 OR SRC2DEST[MAXVL-1:128] := 0
VPOR (VEX.256 Encoded Version)
DEST := SRC1 OR SRC2DEST[MAXVL-1:256] := 0
VPORD (EVEX Encoded Versions) 
THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE OR SRC2[31:0]ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE OR SRC2[i+31:i]
FI;
ELSE 
FI;
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0POR—Bitwise Logical ORINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-407Intel C/C ++ Compiler Intrinsic Equivalent
VPORD __m512i _mm512_or_epi32(__m512i a, __m512i b);
VPORD __m512i _mm512_mask_or_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPORD __m512i _mm512_maskz_or_epi32( __mmask16 k, __m512i a, __m512i b);
VPORD __m256i _mm256_or_epi32(__m256i a, __m256i b);VPORD __m256i _mm256_mask_or_epi32(__m256i  s, __mmask8 k, __m256i a, __m256i b,);
VPORD __m256i _mm256_maskz_or_epi32( __mmask8 k, __m256i a, __m256i b);
VPORD __m128i _mm_or_epi 32(__m128i a, __m128i b);
VPORD __m128i _mm_mask_or_epi32(__m128i s,  __mmask8 k, __m128i a, __m128i b);
VPORD __m128i _mm_maskz_or_epi32( __m mask8 k, __m128i a, __m128i b);
VPORQ __m512i _mm512_or_epi64(__m512i a, __m512i b);VPORQ __m512i _mm512_mask_or_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPORQ __m512i _mm512_maskz_or_epi64(__mmask8 k, __m512i a, __m512i b);VPORQ __m256i _mm256_or_epi64(__m256i a, int imm);VPORQ __m256i _mm256_mask_or_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPORQ __m256i _mm256_maskz_or_epi64( __mmask8 k, __m256i a, __m256i b);VPORQ __m128i _mm_or_epi64(__m128i a, __m128i b);VPORQ __m128i _mm_mask_or_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPORQ __m128i _mm_maskz_or_epi64( __mmask8 k, __m128i a, __m128i b);POR __m64 _mm_or_si64(__m64 m1, __m64 m2)(V)POR __m128i _mm_or_si128(__m128i m1, __m128i m2)VPOR __m256i _mm256_or_si256 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PREFETCHh—Prefetch Data Into CachesINSTRUCTION SET REFERENCE, M-U
4-408 Vol. 2BPREFETCH h—Prefetch Data  Into Caches
Fetches the line of data from memory that contains the byte specified with the source operand to a location in the 
cache hierarchy specified by a locality hint:
•T0 (temporal data)—prefetch data into all levels of the cache hierarchy.
•T1 (temporal data with respect to first level cache misses)—prefetch data into level 2 cache and higher.
•T2 (temporal data with respect to second level cache misses)—prefetch data into level 3 cache and higher, or 
an implementation-specific choice.
•NTA (non-temporal data with respect to all cache levels)—prefetch data into non-temporal cache structure and into a location close to the processor, minimizing cache pollution.
The source operand is a byte memory location. (The loca lity hints are encoded into the machine level instruction 
using bits 3 through 5 of the ModR/M byte.)
If the line selected is already present in the cache hierar chy at a level closer to the processor, no data movement 
occurs. Prefetches from uncacheable or WC memory are ignored.
The PREFETCH h instruction is merely a hint and does not affect  program behavior. If executed, this instruction 
moves data closer to the processor in anticipation of future use.
The implementation of prefetch locality  hints is implementation-dependent, an d can be overloaded or ignored by a

The implementation of prefetch locality  hints is implementation-dependent, an d can be overloaded or ignored by a 
processor implementation. The amount of data prefetched  is also processor implementation-dependent. It will, 
however, be a minimum of 32 bytes. Additional deta ils of the implementation-dependent locality hints are 
described in Section 7.4 of Intel® 64 and IA-32 Architectures Optimization Reference Manual.
It should be noted that processors are free to speculativ ely fetch and cache data from system memory regions that 
are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A 
PREFETCH h instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur 
at any time and is not tied to instruction execution, a PREFETCH h instruction is not ordered with respect to the 
fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCH h instruction is also 
unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCH h instructions, or any other 
general instruction. It is ordered with respect to serializ ing instructions such as CPUID, WRMSR, OUT, and MOV CR.
Operation
FETCH (m8);Opcode Instruction Op/ 
En64-Bit 
0F 18 /1 PREFETCHT0 m8 M Valid Valid Move da ta from m8 closer  to the processor 
using T0 hint.
0F 18 /2 PREFETCHT1 m8 M Valid Valid Move da ta from m8 closer  to the processor 
using T1 hint.
0F 18 /3 PREFETCHT2 m8 M Valid Valid Move da ta from m8 closer  to the processor 
using T2 hint.
0F 18 /0 PREFETCHNTA m8 M Valid Valid Move da ta from m8 closer  to the processor 
using NTA hint.
M ModRM:r/m (r) N/A N/A N/APREFETCHh—Prefetch Data Into CachesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-409Intel C/C ++ Compiler Intrinsic Equivalent
void _mm_prefetch(char *p, int i)
The argument “*p” gives the address of the byte (and corresponding cache line) to be prefetched. The value “i” gives a constant  
(_MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2, or  _MM_HINT_NTA) that specifies the type of prefetch operation to be performed.
None.
#UD If the LOCK prefix is used.PREFETCHW—Prefetch Data Into Cach es in Anticipation of a WriteINSTRUCTION SET REFERENCE, M-U
4-410 Vol. 2BPREFETCHW—Prefetch Data Into Cach es in Anticipation of a Write
Fetches the cache line of data from memory that contains the byte specified with the source operand to a location 
in the 1st or 2nd level cache and invalidates other cached instances of the line.
The source operand is a byte memory location. If the line selected is already present in the lowest level cache and 
is already in an exclusively owned state, no data move ment occurs. Prefetches from non-writeback memory are 
ignored.
The PREFETCHW instruction is merely a hint and does not affect program behavior. If executed, this instruction 
moves data closer to the processor and invalidates other cached copies in anticipation of the line being written to 
in the future.
The characteristic of prefetch locality hints is implemen tation-dependent, and can be overloaded or ignored by a 
It should be noted that processors are free to speculat ively fetch and cache data with exclusive ownership from 
system memory regions that permit such accesses (that is, the WB memory type). A PREFETCHW instruction is 
considered a hint to this speculative behavior. Because th is speculative fetching can occur at any time and is not 
tied to instruction execution, a PREFETCHW instruction is not ordered with respect to the fence instructions 
(MFENCE, SFENCE, and LFENCE) or locked memory refere nces. A PREFETCHW instructio n is also unordered with 
respect to CLFLUSH and CLFLUSHOPT instructions, other PR EFETCHW instructions, or any other general instruction
It is ordered with respect to serializing instru ctions such as CPUID, WRMSR, OUT, and MOV CR.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
Operation
FETCH_WITH_EXCLUSIVE_OWNERSHIP (m8);
None.
void _m_prefetchw( void * );
#UD If the LOCK prefix is used.Opcode/
0F 0D /1
PREFETCHW m8M V/V PREFETCHW Move data from m8 closer to the processor in anticipation of a 
write.
M ModRM:r/m (r) N/A N/A N/APREFETCHW—Prefetch Data Into Cach es in Anticipation of a WriteINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-411Virtual-8086 Mode Exceptions
#UD If the LOCK prefix is used.PSADBW—Compute Sum of Absolute DifferencesINSTRUCTION SET REFERENCE, M-U
4-412 Vol. 2BPSADBW—Compute Sum of Absolute Differences
Mode 
NP 0F F6 /r1
PSADBW mm1, mm2/m64
NOTES:
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSE Computes the absolu te differences of the 
packed unsigned byte integers from mm2 
/m64 and mm1; differences are then summed 
to produce an unsigned word integer result.
66 0F F6 /r
PSADBW xmm1, xmm2/m128A V/V SSE2 Computes the absolu te differences of the 
packed unsigned byte integers from xmm2 
/m128 and xmm1; the 8 low differences and 8 
high differences are then summed separately to produce two unsigned word integer results.
VEX.128.66.0F.WIG F6 /r
VPSADBW xmm1, xmm2, xmm3/m128B V/V AVX Computes the absolu te differences of the 
packed unsigned byte integers from xmm3 
/m128 and xmm2; the 8 low differences and 8 
high differences are then summed separately 
to produce two unsigned word integer results.
VEX.256.66.0F.WIG F6 /r
VPSADBW ymm1, ymm2, ymm3/m256B V/V AVX2 Computes the absolu te differences of the 
packed unsigned byte integers from ymm3 
/m256 and ymm2; then each consecutive 8 
differences are summed separately to produce four unsigned word integer results.
EVEX.128.66.0F.WIG F6 /r
VPSADBW xmm1, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWComputes the absolute differences of the 
/m128 and xmm2; then each consecutive 8 differences are summed separately to produce 
two unsigned word integer results.
EVEX.256.66.0F.WIG F6 /r
VPSADBW ymm1, ymm2, ymm3/m256C V/V AVX512VL
packed unsigned byte integers from ymm3 /m256 and ymm2; then each consecutive 8 
differences are summed separately to produce 
four unsigned word integer results.
EVEX.512.66.0F.WIG F6 /r
VPSADBW zmm1, zmm2, zmm3/m512C V/V AVX512BW Computes the abso lute differences of the 
packed unsigned byte integers from zmm3 
/m512 and zmm2; then each consecutive 8 
differences are summed separately to produce eight unsigned word integer results.
C Full Mem ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) N/APSADBW—Compute Sum of Absolute DifferencesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-413Description
Computes the absolute value of the difference of 8 uns igned byte integers from the source operand (second 
operand) and from the destination operand (first operan d). These 8 differences are then summed to produce an 
unsigned word integer result that is stored in the destination operand. Figure 4-14 shows the operation of the 
PSADBW instruction when using 64-bit operands.
When operating on 64-bit operands, the word integer result is stored in the low word of the destination operand, 
and the remaining bytes in the destin ation operand are cleared to all 0s.
When operating on 128-bit operands, two packed results are computed. Here, the 8 low-order bytes of the source 
and destination operands are operated on to produce a word result that is stored in the low word of the destination 
operand, and the 8 high-order bytes are operated on to prod uce a word result that is stored in bits 64 through 79 
of the destination operand. The remaining by tes of the destination operand are cleared.

For 256-bit version, the third group of 8 differences are summed to produce an unsigned word in bits[143:128] of 
the destination register and the fourth group of 8 di fferences are summed to produce an unsigned word in 
bits[207:192] of the destination register. The re maining words of the destination are set to 0. 
For 512-bit version, the fifth group result is stored in bits [271:256] of the destination. The result from the sixth 
group is stored in bits [335:320]. The results for the se venth and eighth group are stored respectively in bits 
[399:384] and bits [463:447], respectively. The remaining bits in the destination are set to 0.
In 64-bit mode and not encoded by VEX/ EVEX prefix, using a REX prefix in th e form of REX.R permits this instruc-
Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The 
128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second 
source operand is an XMM register or a 128-bit memory  location. Bits (MAXVL-1:128) of the corresponding ZMM 
VEX.128 and EVEX.128 encoded versions: The first source operand and destination register are XMM registers. The 
second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding 
VEX.256 and EVEX.256 encoded versions: The first source op erand and destination register are YMM registers. The 
second source operand is an YMM register or a 256-bit memory location. Bits (MAXVL-1:256) of the corresponding 
EVEX.512 encoded version: The first source operand an d destination register are ZMM registers. The second 
source operand is a ZMM register or a 512-bit memory location.
Figure 4-14.  PSADBW Instructio n Operation Using 64-bit OperandsX3 X2 X1 X0 SRC
DEST
TEMPX4 X5 X6 X7
Y3 Y2 Y1 Y0 Y4 Y5 Y6 Y7
ABS(X0:Y0) ABS(X7:Y7) ABS(X6:Y6) ABS(X5:Y5) ABS(X4:Y4) ABS(X3:Y3) ABS(X2:Y2) ABS(X1:Y1)
DEST 00H 00H 00H 00H 00H 00H SUM(TEMP7...TEMP0)PSADBW—Compute Sum of Absolute DifferencesINSTRUCTION SET REFERENCE, M-U
4-414 Vol. 2BOperation
VPSADBW (EVEX Encoded Versions)
VL = 128, 256, 512TEMP0 := ABS(SRC1 [7:0] - SRC2[7:0])
(* Repeat operation for bytes 1 through 15 *)TEMP15 := ABS(SRC1[127:120] - SRC2[127:120])DEST[15:0] := SUM(TEMP0:TEMP7)DEST[63:16] := 000000000000HDEST[79:64] := SUM(TEMP8:TEMP15)DEST[127:80] := 00000000000H
IF VL >= 256
(* Repeat operation for bytes 16 through 31*)TEMP31 := ABS(SRC1[255:248] - SRC2[255:248])DEST[143:128] := SUM(TEMP16:TEMP23)DEST[191:144] := 000000000000HDEST[207:192] := SUM(TEMP24:TEMP31)DEST[223:208] := 00000000000H
FI;IF VL >= 512(* Repeat operation for bytes 32 through 63*)
TEMP63 := ABS(SRC1[511:504] - SRC2[511:504])DEST[271:256] := SUM(TEMP0:TEMP7)DEST[319:272] := 000000000000HDEST[335:320] := SUM(TEMP8:TEMP15)DEST[383:336] := 00000000000HDEST[399:384] := SUM(TEMP16:TEMP23)DEST[447:400] := 000000000000HDEST[463:448] := SUM(TEMP24:TEMP31)DEST[511:464] := 00000000000H
FI;DEST[MAXVL-1:VL] := 0
VPSADBW (VEX.256 Encoded Version)
TEMP0 := ABS(SRC1 [7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 30*)TEMP31 := ABS(SRC1[255:248] - SRC2[255:248])DEST[15:0] := SUM(TEMP0:TEMP7)DEST[63:16] := 000000000000HDEST[79:64] := SUM(TEMP8:TEMP15)DEST[127:80] := 00000000000HDEST[143:128] := SUM(TEMP16:TEMP23)DEST[191:144] := 000000000000HDEST[207:192] := SUM(TEMP24:TEMP31)DEST[223:208] := 00000000000HDEST[MAXVL-1:256] := 0PSADBW—Compute Sum of Absolute DifferencesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-415VPSADBW (VEX.128 Encoded Version)
(* Repeat operation for bytes 2 through 14 *)TEMP15 := ABS(SRC1[127:120] - SRC2[127:120])DEST[15:0] := SUM(TEMP0:TEMP7)DEST[63:16] := 000000000000HDEST[79:64] := SUM(TEMP8:TEMP15)DEST[127:80] := 00000000000HDEST[MAXVL-1:128] := 0
PSADBW (128-bit Legacy SSE Version)
TEMP0 := ABS(DEST[7:0] - SRC[7:0])(* Repeat operation for bytes 2 through 14 *)TEMP15 := ABS(DEST[127:120] - SRC[127:120])DEST[15:0] := SUM(TEMP0:TEMP7)DEST[63:16] := 000000000000HDEST[79:64] := SUM(TEMP8:TEMP15)DEST[127:80] := 00000000000DEST[MAXVL-1:128 ] (Unmodified)
PSADBW (64-bit Operand)
TEMP0 := ABS(DEST[7:0] - SRC[7:0])(* Repeat operation for bytes 2 through 6 *)TEMP7 := ABS(DEST[63:56] - SRC[63:56])DEST[15:0] := SUM(TEMP0:TEMP7)DEST[63:16] := 000000000000H
VPSADBW __m512i _mm512_sad_epu8( __m512i a, __m512i b)PSADBW __m64 _mm_sad_pu8(__m64 a,__m64 b)(V)PSADBW __m128i _mm_sad_epu8(__m128i a, __m128i b)VPSADBW __m256i _mm256_sad_epu8( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Exceptions Type E4NF.n b in Table 2-50, “Type E4NF Class Exception Conditions.”PSHUFB—Packed Shuffle BytesINSTRUCTION SET REFERENCE, M-U
4-416 Vol. 2BPSHUFB—Packed Shuffle Bytes
PSHUFB performs in-place shuffles of bytes in the destination operand (the fi rst operand) according to the shuffle 
control mask in the source operand (the second operand). The instruction permutes the data in the destination operand, leaving the shuffle mask unaffected. If the most si gnificant bit (bit[7]) of each byte of the shuffle control 
mask is set, then constant zero is written in the result byte. Each byte in the shuffle control mask forms an index 
to permute the corresponding byte in the destination operand.  The value of each index is the least significant 4 bits 
(128-bit operation) or 3 bits (64-bit operation) of the shuffle control byte. When the source operand is a 128-bit 
memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will 
be generated. 
Legacy SSE version 64-bit operand: Both operands can be MMX registers.
VEX.128 encoded version: The destination operand is the first operand, the first source operand is the second 
operand, the second source operand is the third operand.  Bits (MAXVL-1:128) of the destination YMM register are 
zeroed. 
VEX.256 encoded version: Bits (255:128) of the destinatio n YMM register stores the 16-byte shuffle result of the 
upper 16 bytes of the first source operand, using the uppe r 16-bytes of the second source operand as control mask. Opcode/
Mode 
Feature 
NP 0F 38 00 /r
1 
PSHUFB mm1, mm2/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSSE3 Shuffle bytes in mm1 according to contents of 
mm2/m64. 
66 0F 38 00 /r 
PSHUFB xmm1, xmm2/m128A V/V SSSE3 Shuffle bytes in xmm1 according to contents of 
VEX.128.66.0F38.WIG 00 /r
VPSHUFB xmm1, xmm2, xmm3/m128B V/V AVX Shuffle bytes in xmm2  according to contents of 
xmm3/m128.
VEX.256.66.0F38.WIG 00 /r
VPSHUFB ymm1, ymm2, ymm3/m256B V/V AVX2 Shuffle bytes in ymm2 according to contents of 
ymm3/m256.
EVEX.128.66.0F38.WIG 00 /r
VPSHUFB xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWShuffle bytes in xmm2 ac cording to contents of 
xmm3/m128 under write mask k1.
EVEX.256.66.0F38.WIG 00 /r
VPSHUFB ymm1 {k1}{z }, ymm2, ymm3/m256C V/V AVX512VL
AVX512BWShuffle bytes in ymm2 according to contents of 
ymm3/m256 under write mask k1.
EVEX.512.66.0F38.WIG 00 /r
VPSHUFB zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Shuffle bytes in zm m2 according to contents of 
zmm3/m512 under write mask k1.
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/APSHUFB—Packed Shuffle BytesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-417The value of each index is for the high 128-bit lane is th e least significant 4 bits of the respective shuffle control 
byte. The index value selects a source data element within each 128-bit lane.
EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory 
location. The first source operand and destination operan ds are ZMM/YMM/XMM registers. The destination is condi-
tionally updated with writemask k1.
EVEX and VEX encoded version: Four/two in-lane 128-bit shuffles.
Operation 
PSHUFB (With 64-bit Operands)
TEMP := DESTfor i = 0 to 7 { 
if (SRC[(i * 8)+7] = 1 ) then

Operation 
DEST[(i*8)+7...(i*8)+0] := 0;
else 
index[2..0] := SRC[(i*8)+2 .. (i*8)+0];DEST[(i*8)+7...(i*8)+0] := TE MP[(index*8+7)..(index*8+0)];
endif;
}PSHUFB (with 128 bit operands)TEMP := DESTfor i = 0 to 15 { 
DEST[(i*8)+7..(i*8)+0] := 0;
 else 
index[3..0] := SRC[(i*8)+3 .. (i*8)+0];
DEST[(i*8)+7..(i*8)+0] := TE MP[(index*8+7)..(index*8+0)];
endif
}
VPSHUFB (VEX.128 Encoded Version)
for i = 0 to 15 {
if (SRC2[(i * 8)+7] = 1) then
DEST[(i*8)+7..(i*8)+0] := 0;elseindex[3..0] := SRC2[(i*8)+3 .. (i*8)+0];DEST[(i*8)+7..(i*8)+0] := SRC1[(index*8+7)..(index*8+0)];
endif
}DEST[MAXVL-1:128] := 0
VPSHUFB (VEX.256 Encoded Version)
if (SRC2[(i * 8)+7] == 1 ) then
endifif (SRC2[128 + (i * 8)+7] == 1 ) then
DEST[128 + (i*8)+7..(i*8)+0] := 0;elseindex[3..0] := SRC2[128 + (i*8)+3 .. (i*8)+0];
DEST[128 + (i*8)+7..(i*8)+0] := SR C1[128 + (index*8+7)..(index*8+0)];
endifPSHUFB—Packed Shuffle BytesINSTRUCTION SET REFERENCE, M-U
4-418 Vol. 2B}
VPSHUFB (EVEX Encoded Versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)jmask := (KL-1) & ~0xF // 0x00, 0x10, 0x30 depending on the VLFOR j = 0 TO KL-1 // dest
IF kl[ i ] or no_masking
index := src.byte[ j ];IF index & 0x80
Dest.byte[ j ] := 0;
ELSE
index := (index & 0xF) + (j & jm ask); // 16-element in-lane lookup
Dest.byte[ j ] := src.byte[ index ];
ELSE if zeroing
DEST[MAXVL-1:VL] := 0;
VPSHUFB __m512i _mm512_shuffle_epi8(__m512i a, __m512i b);VPSHUFB __m512i _mm512_mask_shuffle_epi8(__m5 12i s, __mmask64 k, __m512i a, __m512i b);
VPSHUFB __m512i _mm512_maskz_shuffle_epi 8( __mmask64 k, __m512i a, __m512i b);
VPSHUFB __m256i _mm256_mask_shuffle_epi8(__m2 56i s, __mmask32 k, __m256i a, __m256i b);
VPSHUFB __m256i _mm256_maskz_shuffle_epi 8( __mmask32 k, __m256i a, __m256i b);
VPSHUFB __m128i _mm_mask_shuffle_epi8(__m128i  s, __mmask16 k, __m128i a, __m128i b);
VPSHUFB __m128i _mm_maskz_ shuffle_epi8( __mmask16 k, __m128i a, __m128i b);
PSHUFB: __m64 _mm_shuffle_pi8 (__m64 a, __m64 b)(V)PSHUFB: __m128i _mm_shuffle_epi8 (__m128i a, __m128i b)VPSHUFB:__m256i _mm256_shuffle_epi8(__m256i a, __m256i b)
None.Figure 4-15.  PSHUFB with 64-Bit Operands07H         07H              FFH               80H               01H           00H               00H            00H
04H         01H              07H               03H               02H           02H               FFH            01H
04H         04H              00H               00H               FFH           01H               01H            01HMM2
MM1
MM1PSHUFB—Packed Shuffle BytesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-419Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4NF.n b in Table 2-50, “Type E4NF Class Exception Conditions.”PSHUFD—Shuffle Packed DoublewordsINSTRUCTION SET REFERENCE, M-U
4-420 Vol. 2BPSHUFD—Shuffle Packed Doublewords
Copies doublewords from source oper and (second operand) and inserts them  in the destination operand (first 
operand) at the locations selected with the order operand (third operand). Figure 4-16 shows the operation of the 
256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects 
the contents of one doubleword location within a 128-bit lane and copy to the target element in the destination 
operand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high 
128-bit lane of the destination operan d for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand 
(see the field encoding in Figure 4-16) determines which doubleword element (from the respective 128-bit lane) of 
the source operand will be copied to doubleword 0 of the destination operand. 
For 128-bit operation, only the low 128-bit lane are oper ative. The source operand can be an XMM register or a 
128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate. 
Note that this instruction permits a doubleword in the so urce operand to be copied to more than one doubleword 
location in the destination operand.Opcode/
Mode 
Feature 
66 0F 70 /r ib
PSHUFD xmm1, xmm2/m128, imm8A V/V  SSE2 Shuffle the doublewords in xmm2/m128 based on 
the encoding in imm8 and store the result in xmm1.
VEX.128.66.0F.WIG 70 /r ib
VPSHUFD xmm1, xmm2/m128, imm8A V/V AVX Shuffle the doublewords in xmm2/m128 based on 
VEX.256.66.0F.WIG 70 /r ib
VPSHUFD ymm1, ymm2/m256, imm8A V/V AVX2 Shuffle the doublewords in ymm2/m256 based on 
the encoding in imm8 and store the result in ymm1.
EVEX.128.66.0F.W0 70 /r ib
VPSHUFD xmm1 {k1}{z},  xmm2/m128/m32bcst, 
imm8BV / V A V X 5 1 2 V L
AVX512FShuffle the doublewords in xmm2/m128/m32bcst 
based on the encoding in imm8 and store the result 
in xmm1 using writemask k1.
EVEX.256.66.0F.W0 70 /r ib
VPSHUFD ymm1 {k1}{z},  ymm2/m256/m32bcst, 
AVX512FShuffle the doublewords in ymm2/m256/m32bcst 
in ymm1 using writemask k1.
EVEX.512.66.0F.W0 70 /r ib
VPSHUFD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8B V/V AVX512F Shuffle the doublewords in zmm2/m512/m32bcst 
based on the encoding in imm8 and store the result in zmm1 using writemask k1.
B Full ModRM:reg (w) ModRM:r/m (r) imm8 N/APSHUFD—Shuffle Packed DoublewordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-421Figure 4-16.  256-bit VPSHUFD Instruction Operation
The source operand can be an XMM register or a 128-bit  memory location. The destination operand is an XMM 
register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source 
operand to be copied to more than one doubleword location in the destination operand.
In 64-bit mode and not encoded in VEX/EVEX, using REX.R permits this instruction to access XMM8-XMM15.
VEX.128 encoded version: The source operand can be an XMM register or a 128-bit memory location. The destina-
tion operand is an XMM register. Bits (MAXVL-1: 128) of the corresponding ZMM register are zeroed.
VEX.256 encoded version: The source operand can be an YMM register or a 256-bit memory location. The destina-
tion operand is an YMM register. Bits (MAXVL-1:256) of  the corresponding ZMM register are zeroed. Bits (255-
1:128) of the destination stores the shuffled results of  the upper 16 bytes of the source operand using the imme-
diate byte as the order operand.
EVEX encoded version: The source operand can be an ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a 
Each 128-bit lane of the destination st ores the shuffled results of the respective lane of the source operand using 
the immediate byte as the order operand.
Note: EVEX.vvvv and VEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFD (128-bit Legacy SSE Version)
DEST[31:0] := (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] := (SRC >> (O RDER[3:2] * 32))[31:0];
DEST[95:64] := (SRC >> (O RDER[5:4] * 32))[31:0];
DEST[127:96] := (SRC >> (ORDER[7:6] * 32))[31:0];DEST[MAXVL-1:128 ] (Unmodified)
VPSHUFD (VEX.128 Encoded Version)
DEST[127:96] := (SRC >> (ORDER[7:6] * 32))[31:0];DEST[MAXVL-1:128] := 0X7 X6 X5 X4 SRC
DEST Y7 Y6 Y5 Y4
ORDER00B - X0
01B - X1
10B - X2
11B - X3Encoding
of Fields in
ORDER01234567OperandY3 Y2 Y1 Y0X3 X2 X1 X0
00B - X4
01B - X510B - X611B - X7Encoding
ORDER
OperandPSHUFD—Shuffle Packed DoublewordsINSTRUCTION SET REFERENCE, M-U
4-422 Vol. 2BVPSHUFD (VEX.256 Encoded Version)
DEST[31:0] := (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];DEST[63:32] := (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] := (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] := (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];DEST[159:128] := (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];DEST[191:160] := (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];DEST[223:192] := (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];DEST[255:224] := (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];DEST[MAXVL-1:256] := 0
VPSHUFD (EVEX Encoded Versions)
i := j * 32IF (EVEX.b = 1) AND (SRC *is memory*)

01B - X1
10B - X2
00B - X4
ORDER
THEN TMP_SRC[i+31:i] := SRC[31:0]ELSE TMP_SRC[i+31:i] := SRC[i+31:i]
FI;
ENDFOR;IF VL >= 128
TMP_DEST[31:0] := (TMP_SRC[127:0] >> (ORDER[1:0] * 32))[31:0];TMP_DEST[63:32] := (TMP_SRC[127:0] >> (ORDER[3:2] * 32))[31:0];TMP_DEST[95:64] := (TMP_SRC[127:0] >> (ORDER[5:4] * 32))[31:0];TMP_DEST[127:96] := (T MP_SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
FI;IF VL >= 256
TMP_DEST[159:128] := (TMP_SRC[255:128] >> (ORDER[1:0] * 32))[31:0];TMP_DEST[191:160] := (TMP_SRC[255:128] >> (ORDER[3:2] * 32))[31:0];TMP_DEST[223:192] := (TMP_SRC[255:128] >> (ORDER[5:4] * 32))[31:0];TMP_DEST[255:224] := (TMP_SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
TMP_DEST[287:256] := (TMP_SRC[383:256] >> (ORDER[1:0] * 32))[31:0];TMP_DEST[319:288] := (TMP_SRC[383:256] >> (ORDER[3:2] * 32))[31:0];TMP_DEST[351:320] := (TMP_SRC[383:256] >> (ORDER[5:4] * 32))[31:0];TMP_DEST[383:352] := (TMP_SRC[383:256] >> (ORDER[7:6] * 32))[31:0];TMP_DEST[415:384] := (TMP_SRC[511:384] >> (ORDER[1:0] * 32))[31:0];TMP_DEST[447:416] := (TMP_SRC[511:384] >> (ORDER[3:2] * 32))[31:0];TMP_DEST[479:448] := (TMP_SRC[511:384] >> (ORDER[5:4] * 32))[31:0];TMP_DEST[511:480] := (TMP_SRC[511:384] >> (ORDER[7:6] * 32))[31:0];
THEN DEST[i+31:i] := TMP_DEST[i+31:i]ELSE 
FI
FI;
ENDFORPSHUFD—Shuffle Packed DoublewordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-423DEST[MAXVL-1:VL] := 0 
VPSHUFD __m512i _mm512_shuffle_epi32(__m512i a, int n );
VPSHUFD __m512i _mm512_mask_shuffle_epi32(__m512i s, __mmask16 k, __m512i a, int n );VPSHUFD __m512i _mm512_maskz_shuffle_epi32( __mmask16 k, __m512i a, int n );VPSHUFD __m256i _mm256_mask_shuffle_epi32(__m256i s, __mmask8 k, __m256i a, int n );VPSHUFD __m256i _mm256_maskz_shuffle_epi32( __mmask8 k, __m256i a, int n );VPSHUFD __m128i _mm_mask_shuffle_epi32(__m1 28i s, __mmask8 k, __m128i a, int n );
VPSHUFD __m128i _mm_maskz_shuffle_epi32( __mmask8 k, __m128i a, int n );(V)PSHUFD __m128i _mm_shuffle_epi32(__m128i a, int n)VPSHUFD __m256i _mm256_shuffle_epi32(__m256i a, const int n)
None.
None.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”Additionally:
#UD If VEX.vvvv ≠ 1111B or EVEX.vvvv ≠ 1111B.PSHUFHW—Shuffle Packed High WordsINSTRUCTION SET REFERENCE, M-U
4-424 Vol. 2BPSHUFHW—Shuffle Packed High Words
Copies words from the high quadword of a 128-bit lane of the source operand and inserts them in the high quad-
word of the destination operand at wo rd locations (of the respective lane) selected with the immediate operand. 
This 256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illus-
trated in Figure 4-16. For 128-bit operation, only the low 1 28-bit lane is operative. Each 2-bit field in the immediate 
operand selects the contents of one word location in th e high quadword of the destination operand. The binary 
encodings of the immediate operand fields select words (0, 1, 2 or 3, 4) from the high quadword of the source 
operand to be copied to the destination operand. The lo w quadword of the source op erand is copied to the low 
quadword of the destination operand, for each 128-bit lane.
Note that this instruction permits a word in the high quadwo rd of the source operand to be copied to more than one 
word location in the high quad word of the destination operand.
128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM 
register or a 128-bit memory location. Bits (MAXVL-1:128 ) of the corresponding YMM destination register remain 
VEX.128 encoded version: The destination operand is an X MM register. The source operand can be an XMM register 
or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed. VEX.vvvv is 
reserved and must be 1111b, VEX.L must be  0, otherwise the instruction will #UD.
VEX.256 encoded version: The destination operand is an Y MM register. The source operand can be an YMM register 
or a 256-bit memory location. Opcode/
Mode 
Feature 
F3 0F 70 /r ib
PSHUFHW xmm1, xmm2/m128, imm8A V/V SSE2 Shuffle the high words in xmm2/m128 based 
on the encoding in imm8 and store the result in 
xmm1.
VEX.128.F3.0F.WIG 70 /r ib
VPSHUFHW xmm1, xmm2/m128, imm8A V/V AVX Shuffle the high words in xmm2/m128 based 
on the encoding in imm8 and store the result in xmm1.
VEX.256.F3.0F.WIG 70 /r ib
VPSHUFHW ymm1, ymm2/m256, imm8A V/V AVX2 Shuffle the high words in ymm2/m256 based 
ymm1.
EVEX.128.F3.0F.WIG 70 /r ib
VPSHUFHW xmm1 {k1}{z}, xmm2/m128, imm8BV / V A V X 5 1 2 V L
AVX512BWShuffle the high words in xmm2/m128 based 
xmm1 under write mask k1.
EVEX.256.F3.0F.WIG 70 /r ib
VPSHUFHW ymm1 {k1}{z}, ymm2/m256, imm8BV / V A V X 5 1 2 V L
AVX512BWShuffle the high words in ymm2/m256 based 
ymm1 under write mask k1.
EVEX.512.F3.0F.WIG 70 /r ib
VPSHUFHW zmm1 {k1}{z }, zmm2/m512, imm8B V/V AVX512BW Shuffle the high words in zmm2/m512 based 
on the encoding in imm8 and store the result in zmm1 under write mask k1.
B Full Mem ModRM:reg (w) ModRM:r/m (r) imm8 N/APSHUFHW—Shuffle Packed High WordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-425EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a 
ZMM/YMM/XMM register, a 512/256/128-bit memory location . The destination is updated according to the write-
mask.
Note: In VEX encoded versions, VEX. vvvv is reserved and must be 1111b  otherwise instructions will #UD.
Operation
PSHUFHW (128-bit Legacy SSE Version)
DEST[63:0] := SRC[63:0]DEST[79:64] := (SRC >> (imm[1:0] *16))[79:64]DEST[95:80] := (SRC >> (imm[3:2] * 16))[79:64]DEST[111:96] := (SRC >> (imm[5:4] * 16))[79:64]DEST[127:112] := (SRC >> (imm[7:6] * 16))[79:64]DEST[MAXVL-1:128 ] (Unmodified)
VPSHUFHW (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0]
DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]DEST[MAXVL-1:128] := 0
VPSHUFHW (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0]DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]DEST[191:128] := SRC1[191:128]DEST[207192] := (SRC1 >> (imm[1:0] *16))[207:192]DEST[223:208] := (SRC1 >> (imm[3:2] * 16))[207:192]DEST[239:224] := (SRC1 >> (imm[5:4] * 16))[207:192]DEST[255:240] := (SRC1 >> (imm[7:6] * 16))[207:192]DEST[MAXVL-1:256] := 0
VPSHUFHW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)IF VL >= 128
TMP_DEST[63:0] := SRC1[63:0]TMP_DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]TMP_DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]TMP_DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]TMP_DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]
TMP_DEST[191:128] := SRC1[191:128]TMP_DEST[207:192] := (SRC1 >> (imm[1:0] *16))[207:192]TMP_DEST[223:208] := (SRC1 >> (imm[3:2] * 16))[207:192]TMP_DEST[239:224] := (SRC1 >> (imm[5:4] * 16))[207:192]TMP_DEST[255:240] := (SRC1 >> (imm[7:6] * 16))[207:192]
TMP_DEST[319:256] := SRC1[319:256]TMP_DEST[335:320] := (SRC1 >> (imm[1:0] *16))[335:320]PSHUFHW—Shuffle Packed High WordsINSTRUCTION SET REFERENCE, M-U
4-426 Vol. 2BTMP_DEST[351:336] := (SRC1 >> (imm[3:2] * 16))[335:320]
TMP_DEST[367:352] := (SRC1 >> (imm[5:4] * 16))[335:320]TMP_DEST[383:368] := (SRC1 >> (imm[7:6] * 16))[335:320]TMP_DEST[447:384] := SRC1[447:384]TMP_DEST[463:448] := (SRC1 >> (imm[1:0] *16))[463:448]TMP_DEST[479:464] := (SRC1 >> (imm[3:2] * 16))[463:448]TMP_DEST[495:480] := (SRC1 >> (imm[5:4] * 16))[463:448]TMP_DEST[511:496] := (SRC1 >> (imm[7:6] * 16))[463:448]
FI;
THEN DEST[i+15:i] := TMP_DEST[i+15:i];ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0 
VPSHUFHW __m512i _mm512_shuff lehi_epi16(__m512i a, int n);

FI;
FI
FI;
VPSHUFHW __m512i _mm512_mask_shufflehi_epi16(__m512i s, __mmask16 k, __m512i a, int n );VPSHUFHW __m512i _mm512_mas kz_shufflehi_epi16( __mmask 16 k, __m512i a, int n );
VPSHUFHW __m256i _mm256_mask_shufflehi_epi16(__m256i s, __mmask8 k, __m256i a, int n );VPSHUFHW __m256i _mm256_mas kz_shufflehi_epi16( __mmask 8 k, __m256i a, int n );
VPSHUFHW __m128i _mm_mask_shufflehi_epi16(__m128i s, __mmask8 k, __m128i a, int n );VPSHUFHW __m128i _mm_maskz_shufflehi_epi16( __mmask8 k, __m128i a, int n );(V)PSHUFHW __m128i _mm_shufflehi_epi16(__m128i a, int n)VPSHUFHW __m256i _mm256_shufflehi_epi16(__m256i a, const int n)
None.
None.
#UD If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.PSHUFLW—Shuffle Packed Low WordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-427PSHUFLW—Shuffle Packed Low Words
Copies words from the low quadword of a 128-bit lane of the source operand and insert s them in the low quadword 
of the destination operand at word locations (of the resp ective lane) selected with the immediate operand. The 
256-bit operation is similar to the in-lane operation used  by the 256-bit VPSHUFD instruction, which is illustrated 
in Figure 4-16. For 128-bit operation, only the low 128-bit  lane is operative. Each 2-bit field in the immediate 
operand selects the contents of one word location in th e low quadword of the destination operand. The binary 
encodings of the immediate operand fields select words (0, 1, 2 or 3) from the low quadword of the source operand 
to be copied to the destination operan d. The high quadword of the source operand is copied to the high quadword 
of the destination operand, for each 128-bit lane.
Note that this instruction permits a word in the low quadwo rd of the source operand to be copied to more than one 
word location in the low quadword of the destination operand.
128-bit Legacy SSE version: The destination operand is  an XMM register. The source operand can be an XMM 
register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destination register remain 
VEX.128 encoded version: The destinatio n operand is an XMM register. The source operand can be an XMM register 
or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed. 
VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register 
or a 256-bit memory location. 
EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a 
mask.Opcode/
Mode 
Feature 
F2 0F 70 /r ib
PSHUFLW xmm1, xmm2/m128, imm8A V/V SSE2 Shuffle the low words in xmm2/m128 based on 
the encoding in imm8 and store the result in 
xmm1.
VEX.128.F2.0F.WIG 70 /r ib
VPSHUFLW xmm1, xmm2/m128, imm8A V/V AVX Shuffle the low words in xmm2/m128 based on 
VEX.256.F2.0F.WIG 70 /r ib
VPSHUFLW ymm1, ymm2/m256, imm8A V/V AVX2 Shuffle the low words in ymm2/m256 based on 
ymm1.
EVEX.128.F2.0F.WIG 70 /r ib
VPSHUFLW xmm1 {k1}{z}, xmm2/m128, imm8BV / V A V X 5 1 2 V L
AVX512BWShuffle the low words in xmm2/m128 based on 
EVEX.256.F2.0F.WIG 70 /r ib
VPSHUFLW ymm1 {k1}{z }, ymm2/m256, imm8BV / V A V X 5 1 2 V L
AVX512BWShuffle the low words in ymm2/m256 based on 
EVEX.512.F2.0F.WIG 70 /r ib
VPSHUFLW zmm1 {k1}{z}, zmm2/m512, imm8B V/V AVX512BW Shuffle the low words in zmm2/m512 based on 
the encoding in imm8 and store the result in zmm1 under write mask k1.
B Full Mem ModRM:reg (w ) ModRM:r/m (r) imm8 N/APSHUFLW—Shuffle Packed Low WordsINSTRUCTION SET REFERENCE, M-U
4-428 Vol. 2BNote: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFLW (128-bit Legacy SSE Version)
DEST[15:0] := (SRC >> (imm[1:0] *16))[15:0]DEST[31:16] := (SRC >> (imm[3:2] * 16))[15:0]DEST[47:32] := (SRC >> (imm[5:4] * 16))[15:0]DEST[63:48] := (SRC >> (imm[7:6] * 16))[15:0]DEST[127:64] := SRC[127:64]DEST[MAXVL-1:128] (Unmodified)
VPSHUFLW (VEX.128 Encoded Version)
DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]DEST[127:64] := SRC[127:64]DEST[MAXVL-1:128] := 0
VPSHUFLW (VEX.256 Encoded Version)
DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]DEST[127:64] := SRC1[127:64]DEST[143:128] := (SRC1 >> (imm[1:0] *16))[143:128]DEST[159:144] := (SRC1 >> (imm[3:2] * 16))[143:128]DEST[175:160] := (SRC1 >> (imm[5:4] * 16))[143:128]DEST[191:176] := (SRC1 >> (imm[7:6] * 16))[143:128]DEST[255:192] := SRC1[255:192]DEST[MAXVL-1:256] := 0
VPSHUFLW (EVEX.U1.512 Encoded Version)
TMP_DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]TMP_DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]TMP_DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]TMP_DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]TMP_DEST[127:64] := SRC1[127:64]
TMP_DEST[143:128] := (SRC1 >> (imm[1:0] *16))[143:128]TMP_DEST[159:144] := (SRC1 >> (imm[3:2] * 16))[143:128]TMP_DEST[175:160] := (SRC1 >> (imm[5:4] * 16))[143:128]TMP_DEST[191:176] := (SRC1 >> (imm[7:6] * 16))[143:128]TMP_DEST[255:192] := SRC1[255:192]
TMP_DEST[271:256] := (SRC1 >> (imm[1:0] *16))[271:256]TMP_DEST[287:272] := (SRC1 >> (imm[3:2] * 16))[271:256]TMP_DEST[303:288] := (SRC1 >> (imm[5:4] * 16))[271:256]TMP_DEST[319:304] := (SRC1 >> (imm[7:6] * 16))[271:256]TMP_DEST[383:320] := SRC1[383:320]PSHUFLW—Shuffle Packed Low WordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-429TMP_DEST[399:384] := (SRC1 >> (imm[1:0] *16))[399:384]
TMP_DEST[415:400] := (SRC1 >> (imm[3:2] * 16))[399:384]TMP_DEST[431:416] := (SRC1 >> (imm[5:4] * 16))[399:384]TMP_DEST[447:432] := (SRC1 >> (imm[7:6] * 16))[399:384]TMP_DEST[511:448] := SRC1[511:448]
FI;
FI
FI;
VPSHUFLW __m512i _mm512_shuff lelo_epi16(__m512i a, int n);
VPSHUFLW __m512i _mm512_mask_shufflelo_epi16(__m512i s, __mmask16 k, __m512i a, int n );VPSHUFLW __m512i _mm512_mas kz_shufflelo_epi16( __mmask16 k, __m512i a, int n );
VPSHUFLW __m256i _mm256_mask_shufflelo_epi1 6(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFLW __m256i _mm256_maskz_shufflelo_epi16( __mmask8 k, __m256i a, int n );VPSHUFLW __m128i _mm_mask_shufflelo_epi16( __m128i s, __mmask8 k, __m128i a, int n );
VPSHUFLW __m128i _mm_maskz_shufflelo_epi16( __mmask8 k, __m128i a, int n );(V)PSHUFLW:__m128i _mm_shuffl elo_epi16(__m128i a, int n)
VPSHUFLW:__m256i _mm256_shufflelo_epi16(__m256i a, const int n)
None.
None.
#UD If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.PSHUFW—Shuffle Packed WordsINSTRUCTION SET REFERENCE, M-U
4-430 Vol. 2BPSHUFW—Shuffle Packed Words
Copies words from the source operand (second operand)  and inserts them in the destination operand (first 
operand) at word locations selected with the order operan d (third operand). This operation is similar to the opera-
tion used by the PSHUFD instruction, which is illustrated  in Figure 4-16. For the PSHUFW instruction, each 2-bit 
field in the order operand selects the contents of one word location in the destination operand. The encodings of the 
order operand fields select words from the source operand to be copied to the destination operand.
The source operand can be an MMX technology register or  a 64-bit memory location. The destination operand is an

MMX technology register. The order operand is an 8-bit imme diate. Note that this instruction permits a word in the 
source operand to be copied to more than one word location in the destination operand.
Operation
DEST[15:0] := (SRC >> (ORDER[1:0] * 16))[15:0];
DEST[31:16] := (SRC >> (ORDER[3:2] * 16))[15:0];DEST[47:32] := (SRC >> (ORDER[5:4] * 16))[15:0];DEST[63:48] := (SRC >> (ORDER[7:6] * 16))[15:0];
PSHUFW __m64 _mm_shuffle_pi16(__m64 a, int n)
None.
None.
See Table 23-7, “Exception Conditions for SIMD/MMX Instructions with Memory Reference,” in the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 3B.Opcode/
En64-Bit 
NP 0F 70 /r ib
PSHUFW mm1, mm2/m64, imm8RMI Valid Valid Shuffle the words in mm2/m64 based on the 
encoding in imm8 and st ore the result in mm1.
RMI ModRM:reg (w) ModRM:r/m (r) imm8 N/APSIGNB/PSIGNW/PSIGND—Packed SIGNINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-431PSIGNB/PSIGNW/PSIGND—Packed SIGN 
NP 0F 38 08 /r
1 
PSIGNB mm1, mm2/m64
NOTES:
Registers,” in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.RM V/V SSSE3 Negate/zero/preserve packed byte integers in 
mm1 depending on the corresponding sign in mm2/m64.
66 0F 38 08 /r 
PSIGNB xmm1, xmm2/m128RM V/V SSSE3 Negate/zero/preserve packed byte integers in 
xmm1 depending on the corresponding sign in 
NP 0F 38 09 /r
1 
PSIGNW mm1, mm2/m64RM V/V SSSE3 Negate/zero/preserve packed word integers 
in mm1 depending on the corresponding sign 
in mm2/m128.
66 0F 38 09 /r 
PSIGNW xmm1, xmm2/m128RM V/V SSSE3 Negate/zero/preserve packed word integers 
in xmm1 depending on the corresponding sign 
in xmm2/m128.
NP 0F 38 0A /r1
PSIGND mm1, mm2/m64RM V/V SSSE3 Negate/zero/preserve packed doubleword 
integers in mm1 depending on the corresponding sign in mm2/m128.
66 0F 38 0A /r 
PSIGND xmm1, xmm2/m128 RM V/V SSSE3 Negate/zero/preserve packed doubleword 
integers in xmm1 depending on the 
corresponding sign in xmm2/m128. 
VEX.128.66.0F38.WIG 08 /r
VPSIGNB xmm1, xmm2, xmm3/m128RVM V/V AVX Negate/zero/preserve packed byte integers in 
xmm2 depending on the corresponding sign in 
VEX.128.66.0F38.WIG 09 /r
VPSIGNW xmm1, xmm2, xmm3/m128RVM V/V AVX Negate/zero/preserve packed word integers 
in xmm2 depending on the corresponding sign in xmm3/m128.
VEX.128.66.0F38.WIG 0A /r
VPSIGND xmm1, xmm2, xmm3/m128RVM V/V AVX Negate/zero/preserve packed doubleword 
integers in xmm2 depending on the 
corresponding sign in xmm3/m128.
VEX.256.66.0F38.WIG 08 /r
VPSIGNB ymm1, ymm2, ymm3/m256RVM V/V AVX2 Negate packed byte  integers in ymm2 if the 
corresponding sign in ymm3/m256 is less 
than zero.
VEX.256.66.0F38.WIG 09 /r
VPSIGNW ymm1, ymm2, ymm3/m256RVM V/V AVX2 Negate packed 16-bit integers in ymm2 if the 
corresponding sign in ymm3/m256 is less than zero.
VEX.256.66.0F38.WIG 0A /r
VPSIGND ymm1, ymm2, ymm3/m256RVM V/V AVX2 Negate packed doub leword integers in ymm2 
if the corresponding sign in ymm3/m256 is 
less than zero.
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/APSIGNB/PSIGNW/PSIGND—Packed SIGNINSTRUCTION SET REFERENCE, M-U
4-432 Vol. 2BDescription 
(V)PSIGNB/(V)PSIGNW/(V)PSIGND negates each data element of the destination operand (the first operand) if the 
signed integer value of the corresponding data element in the source operand (the second operand) is less than 
zero. If the signed integer value of a data element in the source operand is positive, the corresponding data 
element in the destination operand is unchanged. If a da ta element in the source operand is zero, the corre-
sponding data element in the destination operand is set to zero.
(V)PSIGNB operates on signed bytes. (V)PSIGNW operates on 16-bit signed words. (V)PSIGND operates on signed 
32-bit integers.
Legacy SSE instructions: Both operands can be MMX regist ers. In 64-bit mode, use the REX prefix to access addi-
tional registers. 
zeroed. VEX.L must be 0, otherwise instructions will #UD.
operand is an YMM register or a 256-bit memory location.
Operation 
def byte_sign(control, input_val):
   if control<0:      return negate(input_val)   elif control==0:      return 0   return input_val   def word_sign(control, input_val):   if control<0:      return negate(input_val)   elif control==0:      return 0   return input_val   def dword_sign(control, input_val):   if control<0:      return negate(input_val)   elif control==0:      return 0   return input_val
PSIGNB srcdest, src // MMX 64-bit Operands
VL=64KL := VL/8for i in 0...KL-1:   srcdest.byte[i] := byte_sig n(src.byte[i], srcdest.byte[i])
PSIGNW srcdest, src   // MMX 64-bit Operands
VL=64KL := VL/16FOR i in 0...KL-1:   srcdest.word[i] := word_sign(src.word [i], srcdest.word[i])PSIGNB/PSIGNW/PSIGND—Packed SIGNINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-433PSIGND srcdest, src   // MMX 64-bit Operands
VL=64KL := VL/32FOR i in 0...KL-1:   srcdest.dword[i] := dword_sign(src.dword[i], srcdest.dword[i])
PSIGNB srcdest, src   // SSE 128-bit Operands
VL=128KL := VL/8FOR i in 0...KL-1:   srcdest.byte[i] := byte_sig n(src.byte[i], srcdest.byte[i])
PSIGNW srcdest,  src   // SSE 128-bit Operands
VL=128KL := VL/16FOR i in 0...KL-1:   srcdest.word[i] := word_sign(src.word [i], srcdest.word[i])
PSIGND srcdest, src   // SSE 128-bit Operands
VL=128KL := VL/32FOR i in 0...KL-1:   srcdest.dword[i] := dword_sign(src.dword[i], srcdest.dword[i])
VPSIGNB dest, src1, src2   // AVX 128-bit or 256-bit Operands
VL=(128,256)KL := VL/8FOR i in 0...KL-1:   dest.byte[i] := byte_sig n(src2.byte[i], src1.byte[i])
VPSIGNW dest, src1, src2   // AVX 128-bit or 256-bit Operands
VL=(128,256)KL := VL/16FOR i in 0...KL-1:   dest.word[i] := word_sig n(src2.word[i], src1.word[i])
VPSIGND dest, src1, src2    // AVX 128-bit or 256-bit Operands
VL=(128,256)KL := VL/32FOR i in 0...KL-1:   dest.dword[i] := dword_sign(src2.dword[i], src1.dword[i])DEST[MAXVL-1:VL] := 0PSIGNB/PSIGNW/PSIGND—Packed SIGNINSTRUCTION SET REFERENCE, M-U
4-434 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
PSIGNB __m64 _mm_sign_pi8 (__m64 a, __m64 b)
(V)PSIGNB __m128i _mm_sign_epi8 (__m128i a, __m128i b)VPSIGNB __m256i _mm256_sign_epi8 (__m256i a, __m256i b)PSIGNW __m64 _mm_sign_pi16 (__m64 a, __m64 b)(V)PSIGNW __m128i _mm_sign_epi16 (__m128i a, __m128i b)VPSIGNW __m256i _mm256_sign_epi16 (__m256i a, __m256i b)PSIGND __m64 _mm_sign_pi32 (__m64 a, __m64 b)(V)PSIGND __m128i _mm_sign_epi32 (__m128i a, __m128i b)VPSIGND __m256i _mm256_sign_epi32 (__m256i a, __m256i b)
None.
#UD If VEX.L = 1.PSLLDQ—Shift Double Quadword Left LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-435PSLLDQ—Shift Double Quadword Left Logical
Shifts the destination operand (first op erand) to the left by the number of bytes specified in the count operand 
(second operand). The empty low-order bytes are cleared (set to all 0s). If the value specified by the count operand 
is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.
128-bit Legacy SSE version: The source and destination operands are the same. Bits (MAXVL-1:128) of the corre-
sponding YMM destination register remain unchanged.
VEX.128 encoded version: The source and destination op erands are XMM registers. Bits (MAXVL-1:128) of the 
destination YMM register are zeroed. 
VEX.256 encoded version: The source operand is YMM regi ster. The destination operand is an YMM register. Bits 
(MAXVL-1:256) of the corresponding ZMM register are zero ed. The count operand applies to both the low and high

(MAXVL-1:256) of the corresponding ZMM register are zero ed. The count operand applies to both the low and high 
128-bit lanes.
EVEX encoded versions: The source operand is a ZMM/YM M/XMM register or a 512/256/128-bit memory location. 
The destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.
Operation
VPSLLDQ (EVEX.U1.512 Encoded Version)
TEMP := COUNTIF (TEMP > 15) THEN TEMP := 16; FIDEST[127:0] := SRC[127:0] << (TEMP * 8)DEST[255:128] := SRC[255:128] << (TEMP * 8)DEST[383:256] := SRC[383:256] << (TEMP * 8)DEST[511:384] := SRC[511:384] << (TEMP * 8)DEST[MAXVL-1:512] := 0Opcode/
Mode 
Feature 
66 0F 73 /7 ib
PSLLDQ xmm1, imm8 A V/V SSE2 Shift xmm1 left by imm8 bytes while shifting 
in 0s.
VEX.128.66.0F.WIG 73 /7 ib
VPSLLDQ xmm1, xmm2, imm8B V/V AVX Shift xmm2 left by imm8 bytes while shifting 
in 0s and store result in xmm1.
VEX.256.66.0F.WIG 73 /7 ib
VPSLLDQ ymm1, ymm2, imm8B V/V AVX2 Shift ymm2 left by imm8 bytes while shifting 
in 0s and store result in ymm1.
EVEX.128.66.0F.WIG 73 /7 ib
VPSLLDQ xmm1,xmm2/ m128, imm8CV / V A V X 5 1 2 V L
AVX512BWShift xmm2/m128 left by imm8 bytes while 
shifting in 0s and store result in xmm1.
EVEX.256.66.0F.WIG 73 /7 ib
VPSLLDQ ymm1, ymm2/m256, imm8CV / V A V X 5 1 2 V L
AVX512BWShift ymm2/m256 left by imm8 bytes while 
shifting in 0s and store result in ymm1.
EVEX.512.66.0F.WIG 73 /7 ib
VPSLLDQ zmm1, zmm2/m512, imm8C V/V AVX512BW Shift zmm2/m512 left by imm8 bytes while 
shifting in 0s and store result in zmm1.
A N/A ModRM:r/m (r, w) imm8 N/A N/A
B N/A VEX.vvvv (w) ModRM:r/m (r) imm8 N/A
C Full Mem EVEX.vvvv (w) ModRM:r/m (r) imm8 N/APSLLDQ—Shift Double Quadword Left LogicalINSTRUCTION SET REFERENCE, M-U
4-436 Vol. 2BVPSLLDQ (VEX.256 and EVEX.256 Encoded Version)
TEMP := COUNTIF (TEMP > 15) THEN TEMP := 16; FIDEST[127:0] := SRC[127:0] << (TEMP * 8)DEST[255:128] := SRC[255:128] << (TEMP * 8)DEST[MAXVL-1:256] := 0
VPSLLDQ (VEX.128 and EVEX.128 Encoded Version)
TEMP := COUNTIF (TEMP > 15) THEN TEMP := 16; FIDEST := SRC << (TEMP * 8)DEST[MAXVL-1:128] := 0
PSLLDQ(128-bit Legacy SSE Version)
TEMP := COUNT
IF (TEMP > 15) THEN TEMP := 16; FI
DEST := DEST << (TEMP * 8)DEST[MAXVL-1:128] (Unmodified)
(V)PSLLDQ __m128i _mm_slli_si128 ( __m128i a, int imm)
VPSLLDQ __m256i _mm256_slli_si256 ( __m256i a, const int imm)VPSLLDQ __m512i _mm512_bslli_epi 128 ( __m512i a, const int imm)
None.
None.
Non-EVEX-encoded instruction, see Table 2-24, “Type 7 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4NF.n b in Table 2-50, “Type E4NF Class Exception Conditions.”PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-437PSLLW/PSLLD/PSLLQ—Shift Pa cked Data Left Logical
Opcode/
NP 0F F1 /r
1
PSLLW mm, mm/m64A V/V MMX Shift words in mm left mm/m64 while shifting in 
0s.
66 0F F1 /r
PSLLW xmm1, xmm2/m128A V/V SSE2 Shift words in xmm1 left by xmm2/m128 while 
shifting in 0s.
NP 0F 71 /6 ib
PSLLW mm1, imm8B V/V MMX Shift words in mm left by imm8 while shifting in 
0s.
66 0F 71 /6 ib
PSLLW xmm1, imm8B V/V SSE2 Shift words in xmm1 left by imm8 while shifting 
in 0s.
NP 0F F2 /r1
PSLLD mm, mm/m64A V/V MMX Shift doublewords in mm left by mm/m64 while 
66 0F F2 /r
PSLLD xmm1, xmm2/m128A V/V SSE2 Shift doublewords in xmm1 left by xmm2/m128 
while shifting in 0s.
NP 0F 72 /6 ib1
PSLLD mm, imm8BV / V M M X S h i f t  d o u b l e w o r d s  i n  mm left by imm8 while 
66 0F 72 /6 ib
PSLLD xmm1, imm8B V/V SSE2 Shift doublewords in xmm1 left by imm8 while 
NP 0F F3 /r1
PSLLQ mm, mm/m64A V/V MMX Shift quadword in mm left by mm/m64 while 
66 0F F3 /r
PSLLQ xmm1, xmm2/m128A V/V SSE2 Shift quadwords in xmm1 left by xmm2/m128 
NP 0F 73 /6 ib1
PSLLQ mm, imm8B V/V MMX Shift quadword in mm left by imm8 while 
66 0F 73 /6 ib
PSLLQ xmm1, imm8B V/V SSE2 Shift quadwords in xmm1 left by imm8 while 
VEX.128.66.0F.WIG F1 /r
VPSLLW xmm1, xmm2, xmm3/m128C V/V AVX Shift words in xmm2 left by amount specified in 
VEX.128.66.0F.WIG 71 /6 ib
VPSLLW xmm1, xmm2, imm8D V/V AVX Shift words in xmm2 left by imm8 while shifting 
in 0s.
VEX.128.66.0F.WIG F2 /r
VPSLLD xmm1, xmm2, xmm3/m128CV / V A V X S h i f t  d o u b l e w o r d s  i n  xmm2 left by amount 
specified in xmm3/m128 while shifting in 0s.
VEX.128.66.0F.WIG 72 /6 ib
VPSLLD xmm1, xmm2, imm8DV / V A V X S h i f t  d o u b l e w o r d s  i n  xmm2 left by imm8 while 
VEX.128.66.0F.WIG F3 /r
VPSLLQ xmm1, xmm2, xmm3/m128CV / V A V X S h i f t  q u a d w o r d s  i n  xmm2 left by amount 
VEX.128.66.0F.WIG 73 /6 ib
VPSLLQ xmm1, xmm2, imm8DV / V A V X S h i f t  q u a d w o r d s  i n  xmm2 left by imm8 while 
VEX.256.66.0F.WIG F1 /r
VPSLLW ymm1, ymm2, xmm3/m128C V/V AVX2 Shift words in ymm2 left by amount specified in 
VEX.256.66.0F.WIG 71 /6 ib
VPSLLW ymm1, ymm2, imm8D V/V AVX2 Shift words in ymm2 left by imm8 while shifting 
in 0s.PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
4-438 Vol. 2BVEX.256.66.0F.WIG F2 /r
VPSLLD ymm1, ymm2, xmm3/m128C V/V AVX2 Shift doublewords in ymm2 left by amount 
VEX.256.66.0F.WIG 72 /6 ib
VPSLLD ymm1, ymm2, imm8D V/V AVX2 Shift doublewords in ymm2 left by imm8 while 
VEX.256.66.0F.WIG F3 /r
VPSLLQ ymm1, ymm2, xmm3/m128C V/V AVX2 Shift quadwords in ymm2 left by amount 
VEX.256.66.0F.WIG 73 /6 ib
VPSLLQ ymm1, ymm2, imm8D V/V AVX2 Shift quadwords in ymm2 left by imm8 while 
EVEX.128.66.0F.WIG F1 /r
VPSLLW xmm1 {k1}{z}, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512BWShift words in xmm2 left by amount specified in 
xmm3/m128 while shifting in 0s using 
EVEX.256.66.0F.WIG F1 /r
VPSLLW ymm1 {k1}{z}, ymm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512BWShift words in ymm2 left by amount specified in 
EVEX.512.66.0F.WIG F1 /r
VPSLLW zmm1 {k1}{z}, zmm2, xmm3/m128G V/V AVX512BW Shift words in zmm2 left by amount specified in 
EVEX.128.66.0F.WIG 71 /6 ib
VPSLLW xmm1 {k1}{z}, xmm2/m128, imm8EV / V A V X 5 1 2 V L
AVX512BWShift words in xmm2/m128 left by imm8 while 
shifting in 0s using writemask k1.
EVEX.256.66.0F.WIG 71 /6 ib
VPSLLW ymm1 {k1}{z}, ymm2/m256, imm8EV / V A V X 5 1 2 V L
AVX512BWShift words in ymm2/m25 6 left by imm8 while 
EVEX.512.66.0F.WIG 71 /6 ib
VPSLLW zmm1 {k1}{z}, zmm2/m512, imm8E V/V AVX512BW Shift words in z mm2/m512 left by imm8 while 
shifting in 0 using writemask k1.
EVEX.128.66.0F.W0 F2 /r
VPSLLD xmm1 {k1}{z}, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512FShift doublewords in xmm2 left by amount 
specified in xmm3/m128 while shifting in 0s under writemask k1.
EVEX.256.66.0F.W0 F2 /r
VPSLLD ymm1 {k1}{z}, ymm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512FShift doublewords in ymm2 left by amount 
specified in xmm3/m128 while shifting in 0s 
EVEX.512.66.0F.W0 F2 /r
VPSLLD zmm1 {k1}{z }, zmm2, xmm3/m128G V/V AVX512F Shift doublewords in zmm2 left by amount 
EVEX.128.66.0F.W0 72 /6 ib
VPSLLD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8FV / V A V X 5 1 2 V L
AVX512FShift doublewords in xmm2/m128/m32bcst left 
by imm8 while shifting in 0s using writemask k1.
EVEX.256.66.0F.W0 72 /6 ib
VPSLLD ymm1 {k1}{z}, ymm2/m256/m32bcst, 
imm8FV / V A V X 5 1 2 V L
AVX512FShift doublewords in ymm2/m256/m32bcst left 
EVEX.512.66.0F.W0 72 /6 ib
VPSLLD zmm1 {k1}{z}, zmm2/m512/m32bcst, 
imm8F V/V AVX512F Shift doublewords in zmm2/m512/m32bcst left 
EVEX.128.66.0F.W1 F3 /r
VPSLLQ xmm1 {k1}{z}, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512FShift quadwords in xm m2 left by amount 
specified in xmm3/m128 while shifting in 0s using writemask k1.
EVEX.256.66.0F.W1 F3 /r
VPSLLQ ymm1 {k1}{z}, ymm2, xmm3/m128
GV / V A V X 5 1 2 V L
AVX512FShift quadwords in ymm2 left by amount 
using writemask k1.Opcode/
Mode 
Feature 
FlagDescriptionPSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-439Instruction Operand Encoding
Shifts the bits in the individual data elements (words, do ublewords, or quadword) in the destination operand (first 
operand) to the left by the number of bits specified in th e count operand (second operand). As the bits in the data

Mode 
Feature 
operand) to the left by the number of bits specified in th e count operand (second operand). As the bits in the data 
elements are shifted left, the empty low-order bits are cl eared (set to 0). If the value specified by the count 
operand is greater than 15 (for words), 31 (for doublewords) , or 63 (for a quadword), then the destination operand 
is set to all 0s. Figure 4-17 gives an exampl e of shifting words in a 64-bit operand. EVEX.512.66.0F.W1 F3 /r
VPSLLQ zmm1 {k1}{z}, zmm2, xmm3/m128G V/V AVX512F Shift quadwords in zmm2 left by amount 
EVEX.128.66.0F.W1 73 /6 ib
VPSLLQ xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8FV / V A V X 5 1 2 V L
AVX512FShift quadwords in xmm2/m128/m64bcst left 
EVEX.256.66.0F.W1 73 /6 ib
VPSLLQ ymm1 {k1}{z}, ymm2/m256/m64bcst, 
AVX512FShift quadwords in ymm2/m256/m64bcst left 
EVEX.512.66.0F.W1 73 /6 ib
VPSLLQ zmm1 {k1}{z}, zmm2/m512/m64bcst, 
imm8F V/V AVX512F Shift quadwords in zmm2/m512/m64bcst left 
NOTES:
B N/A ModRM:r/m (r, w) imm8 N/A N/A
C N/A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
D N/A VEX.vvvv (w) ModRM:r/m (r) imm8 N/A
E Full Mem EVEX.vvvv (w) ModRM:r/m (r) imm8 N/A
F Full EVEX.vvvv (w) ModRM:r/m (r) imm8 N/A
G Mem128 ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Figure 4-17.  PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit OperandOpcode/
Mode 
Feature 
DESTDESTPre-Shift
Post-ShiftShift LeftX0
X0 << COUNTX3 X2 X1
X1 << COUNT X2 << COUNT X3 << COUNTwith Zero
ExtensionPSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
4-440 Vol. 2BThe (V)PSLLW instruction shifts each of the words in the destination operand to the left by the number of bits spec-
ified in the count operand; the (V)PSLLD  instruction shifts each of the doublewords in the destination operand; and 
the (V)PSLLQ instruction shifts the quadword  (or quadwords) in the destination operand.
Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count operand 
can be either an MMX technology register or an 64-bit memory location.
128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (MAXVL-1:128) of 
the corresponding YMM destination register remain unchan ged. The count operand can be either an XMM register 
or a 128-bit memory location or an 8-bit immediate. If th e count operand is a memory address, 128 bits are loaded 
but the upper 64 bits are ignored.
VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (MAXVL-1:128) of the 
destination YMM register are zeroed. The count operand ca n be either an XMM register or a 128-bit memory loca-
tion or an 8-bit immediate. If the count operand is a memo ry address, 128 bits are loaded but the upper 64 bits are 
ignored.
VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a 
memory location. The count operand can come either from an  XMM register or a memory location or an 8-bit imme-
diate. Bits (MAXVL-1:256) of the co rresponding ZMM register are zeroed.
EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count 
operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a 
memory location (the variable count version). For the im mediate count version, the source operand (the second 
operand) can be a ZMM register, a 512-bit memory locati on or a 512-bit vector broadcasted from a 32/64-bit 
memory location. For the variable count version, the first source operand (the second operand) is a ZMM register, 
the second source operand (the third operand, 8-bit variab le count) can be an XMM register or a memory location.
Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination 
register, and VEX.B/EVEX.B + ModRM. r/m encodes the source register.
Note: For shifts with an immediate count (VEX. 128.66.0F 71-73 /6, or EVEX.128.66.0F 71-73 /6), 
VEX.vvvv/EVEX.vvvv encodes the destination register. 
Operation
PSLLW (With 64-bit Operand)
IF (COUNT > 15)
THEN 
DEST[64:0] := 0000000000000000H;
ELSE
DEST[15:0] := ZeroExtend(DEST[15:0] << COUNT);
(* Repeat shift operation for 2nd and 3rd words *)DEST[63:48] := ZeroExtend(DEST[63:48] 
<< COUNT);
FI;
PSLLD (with 64-bit operand)
IF (COUNT > 31)
THEN 
ELSE
DEST[31:0] := ZeroExtend(DEST[31:0] << COUNT);
DEST[63:32] := ZeroExtend(DEST[63:32] << COUNT);
FI;PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-441PSLLQ (With 64-bit Operand)
IF (COUNT > 63)
THEN 
ELSE
DEST := ZeroExtend(DEST << COUNT);
FI;
LOGICAL_LEFT_SHIFT_WORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC[63:0];IF (COUNT > 15)THEN
DEST[127:0] := 00000000000000000000000000000000H
ELSE
DEST[15:0] := ZeroExtend(SRC[15:0] << COUNT);(* Repeat shift operation for 2nd through 7th words *)DEST[127:112] := ZeroExtend(SRC[127:112] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_DWORDS1(SRC, COUNT_SRC)
COUNT := COUNT_SRC[63:0];IF (COUNT > 31)THEN
DEST[31:0] := 0
ELSE
DEST[31:0] := ZeroExtend(SRC[31:0] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_DWORDS(SRC, COUNT_SRC)
ELSE
DEST[31:0] := ZeroExtend(SRC[31:0] << COUNT);(* Repeat shift operation for 2nd through 3rd words *)DEST[127:96] := ZeroExtend(SRC[127:96] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_QWORDS1(SRC, COUNT_SRC)
COUNT := COUNT_SRC[63:0];IF (COUNT > 63)THEN
ELSE
DEST[63:0] := ZeroExtend(SRC[63:0] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_QWO RDS(SRC, COUNT_SRC)
ELSEPSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
4-442 Vol. 2BDEST[63:0] := ZeroExtend(SRC[63:0] << COUNT);
DEST[127:64] := ZeroExtend(SRC[127:64] << COUNT);
FI;LOGICAL_LEFT_SHIFT_WORDS _256b(SRC, COUNT_SRC)
DEST[127:0] := 00000000000000000000000000000000HDEST[255:128] := 00000000000000000000000000000000H
ELSE
DEST[15:0] := ZeroExtend(SRC[15:0] << COUNT);(* Repeat shift operation for 2nd through 15th words *)DEST[255:240] := ZeroExtend(SRC[255:240] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_DWORD S_256b(SRC, COUNT_SRC)
ELSE
DEST[31:0] := ZeroExtend(SRC[31:0] << COUNT);(* Repeat shift operation for 2nd through 7th words *)DEST[255:224] := ZeroExtend(SRC[255:224] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)
ELSE
DEST[63:0] := ZeroExtend(SRC[63:0] << COUNT);DEST[127:64] := ZeroExtend(SRC[127:64] << COUNT)DEST[191:128] := ZeroExtend(SRC[191:128] << COUNT);DEST[255:192] := ZeroExtend(SRC[255:192] << COUNT);
FI;
VPSLLW (EVEX Versions, xmm/m128)
(KL, VL) = (8, 128), (16, 256), (32, 512)IF VL = 128
TMP_DEST[127:0] := LOGICAL_LEFT_SHI FT_WORDS_128b(SRC1[127:0], SRC2)
FI;IF VL = 256
TMP_DEST[255:0] := LOGICAL_LEFT_SHI FT_WORDS_256b(SRC1[255:0], SRC2)
FI;IF VL = 512
TMP_DEST[511:256] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;
FOR j := 0 TO KL-1PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-443i := j * 16
IF k1[j] OR *no writemask*
THEN *DEST[i+15:i] remains unchanged*ELSE *zeroing-masking* ; zeroing-masking 
FI
FI;
VPSLLW (EVEX Versions, imm8)
TMP_DEST[127:0] := LOGICAL_LEFT_SHI FT_WORDS_128b(SRC1[127:0], imm8)
TMP_DEST[255:0] := LOGICAL_RIGHT_SH IFT_WORDS_256b(SRC1[255:0], imm8)
TMP_DEST[255:0] := LOGICAL_LEFT_SHI FT_WORDS_256b(SRC1[255:0], imm8)

FI;
FI
FI;
TMP_DEST[511:256] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;
FI
FI;
VPSLLW (ymm, ymm, xmm/m128) - VEX.256 Encoding
DEST[255:0] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0;
VPSLLW (ymm, imm8) - VEX.256 Encoding
DEST[255:0] := LOGICAL_LEFT_SHIFT_WORD_256b(SRC1, imm8)DEST[MAXVL-1:256] := 0;
VPSLLW (xmm, xmm, xmm/m128) - VEX.128 Encoding
DEST[127:0] := LOGICAL_LEFT_SHIFT_WORDS(SRC1, SRC2)DEST[MAXVL-1:128] := 0PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
4-444 Vol. 2BVPSLLW (xmm, imm8) - VEX.128 Encoding
DEST[127:0] := LOGICAL_LEFT _SHIFT_WORDS(SRC1, imm8)
PSLLW (xmm, xmm, xmm/m128) 
DEST[127:0] := LOGICAL_L EFT_SHIFT_WORDS(DEST, SRC)
PSLLW (xmm, imm8)
DEST[127:0] := LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)DEST[MAXVL-1:128] (Unmodified)
VPSLLD (EVEX versions, imm8)
IF (EVEX.b = 1) AN D (SRC1 *is memory*)
THEN DEST[i+31:i] := LOGICAL_LEFT _SHIFT_DWORDS1(SRC1[31:0], imm8)
ELSE DEST[i+31:i] := LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
FI;
ELSE 
THEN *DEST[i+31:i] remains unchanged*ELSE *zeroing-masking* ; zeroing-masking 
FI
FI;
VPSLLD (EVEX Versions, xmm/m128)
(KL, VL) = (4, 128), (8, 256), (16, 512)IF VL = 128
TMP_DEST[127:0] := LOGICAL_LEFT_SHI FT_DWORDS_128b(SRC1[127:0], SRC2)
TMP_DEST[255:0] := LOGICAL_LEFT_SHI FT_DWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] := LOGICAL_LEFT_SHI FT_DWORDS_256b(SRC1[511:256], SRC2)
FI;
FIPSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-445FI;
VPSLLD (ymm, ymm, xmm/m128) - VEX.256 Encoding
DEST[255:0] := LOGICAL_LEFT_S HIFT_DWORDS_256b(SRC1, SRC2)
VPSLLD (ymm, imm8) - VEX.256 Encoding
DEST[255:0] := LOGICAL_LEFT_S HIFT_DWORDS_256b(SRC1, imm8)
VPSLLD (xmm, xmm, xmm/m128) - VEX.128 Encoding
DEST[127:0] := LOGICAL_LEFT _SHIFT_DWORDS(SRC1, SRC2)
VPSLLD (xmm, imm8) - VEX.128 Encoding
DEST[127:0] := LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)DEST[MAXVL-1:128] := 0
PSLLD (xmm, xmm, xmm/m128)
DEST[127:0] := LOGICAL_L EFT_SHIFT_DWORDS(DEST, SRC)
PSLLD (xmm, imm8)
DEST[127:0] := LOGICAL_LEFT _SHIFT_DWORDS(DEST, imm8)
VPSLLQ (EVEX Versions, imm8)
THEN DEST[i+63:i] := LOGICAL_LEFT _SHIFT_QWORDS1(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := LOGICAL_LEFT _SHIFT_QWORDS1(SRC1[i+63:i], imm8)
FI;
ELSE 
THEN *DEST[i+63:i] remains unchanged*ELSE *zeroing-masking* ; zeroing-masking 
FI
FI;
ENDFOR
VPSLLQ (EVEX Versions, xmm/m128)
IF VL = 128
TMP_DEST[127:0] := LOGICAL_LEFT_SHI FT_QWORDS_128b(SRC1[127:0], SRC2)
TMP_DEST[255:0] := LOGICAL_LEFT_SHI FT_QWORDS_256b(SRC1[255:0], SRC2)
4-446 Vol. 2BIF VL = 512
TMP_DEST[511:256] := LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)
FI;
THEN DEST[i+63:i] := TMP_DEST[i+63:i]ELSE 
FI
FI;
VPSLLQ (ymm, ymm, xmm/m128) - VEX.256 Encoding
DEST[255:0] := LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0;
VPSLLQ (ymm, imm8) - VEX.256 Encoding
DEST[255:0] := LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, imm8)DEST[MAXVL-1:256] := 0;
VPSLLQ (xmm, xmm, xmm/m128) - VEX.128 Encoding
DEST[127:0] := LOGICAL_LEFT_SHIFT_QWORDS(SRC1, SRC2)DEST[MAXVL-1:128] := 0
VPSLLQ (xmm, imm8) - VEX.128 Encoding
DEST[127:0] := LOGICAL_LEFT_SHIFT_QWORDS(SRC1, imm8)DEST[MAXVL-1:128] := 0
PSLLQ (xmm, xm m, xmm/m128)
DEST[127:0] := LOGICAL_LEFT_SHIFT_QWORDS(DEST, SRC)DEST[MAXVL-1:128] (Unmodified)
PSLLQ (xmm, imm8)
DEST[127:0] := LOGICAL_LEFT _SHIFT_QWORDS(DEST, imm8)
VPSLLD __m512i _mm512_slli_epi32( __m512i a, unsigned int imm);
VPSLLD __m512i _mm512_mask_slli_epi32(__m512i s,  __mmask16 k, __m512i a, unsigned int imm);
VPSLLD __m512i _mm512_maskz_slli_epi32( __ mmask16 k, __m512i a, unsigned int imm);
VPSLLD __m256i _mm256_mask_slli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSLLD __m256i _mm256_maskz_slli_epi32( __ mmask8 k, __m256i a, unsigned int imm);
VPSLLD __m128i _mm_mask_slli_epi32(__m128i s,  __mmask8 k, __m128i a, unsigned int imm);
VPSLLD __m128i _mm_maskz_slli_epi32( __mmask8 k, __m128i a, unsigned int imm);VPSLLD __m512i _mm512_sll_epi32(__m512i a, __m128i cnt);VPSLLD __m512i _mm512_mask_sll_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-447VPSLLD __m512i _mm512_maskz_sll_epi32( __mmask16 k, __m512i a, __m128i cnt);
VPSLLD __m256i _mm256_mask_sll_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);VPSLLD __m256i _mm256_maskz_sll_epi32( __mmask8 k, __m256i a, __m128i cnt);VPSLLD __m128i _mm_mask_sll_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);VPSLLD __m128i _mm_maskz_sll_epi32( __mmask8 k, __m128i a, __m128i cnt);VPSLLQ __m512i _mm512_mask_slli_epi 64(__m512i a, unsigned int imm);
VPSLLQ __m512i _mm512_mask_slli_epi64(__m512i s,  __mmask8 k, __m512i a, unsigned int imm);
VPSLLQ __m512i _mm512_maskz_slli_epi64( __m mask8 k, __m512i a, unsigned int imm);
VPSLLQ __m256i _mm256_mask_slli_epi64(__m256i s,  __mmask8 k, __m256i a, unsigned int imm);
VPSLLQ __m256i _mm256_maskz_slli_epi64( __m mask8 k, __m256i a, unsigned int imm);
VPSLLQ __m128i _mm_mask_slli_e pi64(__m128i s, __mmask8 k, __ m128i a, unsigned int imm);
VPSLLQ __m128i _mm_maskz_s lli_epi64( __mmask8 k, __m12 8i a, unsigned int imm);
VPSLLQ __m512i _mm512_mask_sll_epi64(__m512i a, __m128i cnt);VPSLLQ __m512i _mm512_mask_sll_epi64(__m512i  s, __mmask8 k, __m512i a, __m128i cnt);
VPSLLQ __m512i _mm512_maskz_sll_epi64(  __mmask8 k, __m512i a, __m128i cnt);
VPSLLQ __m256i _mm256_mask_sll_epi64(__m256i  s, __mmask8 k, __m256i a, __m128i cnt);
VPSLLQ __m256i _mm256_maskz_sll_epi64(  __mmask8 k, __m256i a, __m128i cnt);
VPSLLQ __m128i _mm_mask_sll_epi64(__m128i s,  __mmask8 k, __m128i a, __m128i cnt);
VPSLLQ __m128i _mm_maskz_sll_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSLLW __m512i _mm512_slli_epi16 (__m512i a, unsigned int imm);
VPSLLW __m512i _mm512_mask_slli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);
VPSLLW __m512i _mm512_maskz_slli_epi16( __mma sk32 k, __m512i a, unsigned int imm);
VPSLLW __m256i _mm256_mask_slli_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);
VPSLLW __m256i _mm256_maskz_slli_epi16( __mma sk16 k, __m256i a, unsigned int imm);
VPSLLW __m128i _mm_mask_slli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSLLW __m128i _mm_maskz_slli_epi16( __m mask8 k, __m128i a, unsigned int imm);
VPSLLW __m512i _mm512_sll_epi16(__m512i a, __m128i cnt);VPSLLW __m512i _mm512_mask_sll_epi16(__m512i  s, __mmask32 k, __m512i a, __m128i cnt);
VPSLLW __m512i _mm512_maskz_sll_epi16(  __mmask32 k, __m512i a, __m128i cnt);
VPSLLW __m256i _mm256_mask_sll_epi16(__m256i  s, __mmask16 k, __m256i a, __m128i cnt);
VPSLLW __m256i _mm256_maskz_sll_epi16(  __mmask16 k, __m256i a, __m128i cnt);
VPSLLW __m128i _mm_mask_sll_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLW __m128i _mm_maskz_sll_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSLLW __m64 _mm_slli_pi16 (__m64 m, int count)PSLLW __m64 _mm_sll_pi16(__m64 m, __m64 count)(V)PSLLW __m128i _mm_slli_epi16(__m64 m, int count)(V)PSLLW __m128i _mm_sll_epi16(__m128i m, __m128i count)VPSLLW __m256i _mm256_slli_epi 16 (__m256i m, int count)
VPSLLW __m256i _mm256_sll_epi16 (__m256i m, __m128i count)PSLLD __m64 _mm_slli_pi32(__m64 m, int count)PSLLD __m64 _mm_sll_pi32(__m64 m, __m64 count)(V)PSLLD __m128i _mm_slli_e pi32(__m128i m, int count)

(V)PSLLD __m128i _mm_sll_epi3 2(__m128i m, __m128i count)
VPSLLD __m256i _mm256_slli_epi 32 (__m256i m, int count)
VPSLLD __m256i _mm256_sll_epi32 (__m256i m, __m128i count)PSLLQ __m64 _mm_slli_si64(__m64 m, int count)PSLLQ __m64 _mm_sll_si64(__m64 m, __m64 count)(V)PSLLQ __m128i _mm_slli_e pi64(__m128i m, int count)
(V)PSLLQ __m128i _mm_sll_epi6 4(__m128i m, __m128i count)
VPSLLQ __m256i _mm256_slli_epi64 (__m256i m, int count)VPSLLQ __m256i _mm256_sll_epi64 (__m256i m, __m128i count)PSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, M-U
4-448 Vol. 2BFlags Affected
None.
None.
•VEX-encoded instructions:
— Syntax with RM/RVM operand encoding (A/C in the op erand encoding table), see Table 2-21, “Type 4 Class 
Exception Conditions.”
— Syntax with MI/VMI operand encoding (B/D in the op erand encoding table), see Table 2-24, “Type 7 Class 
•EVEX-encoded VPSLLW (E in the operand encoding table), see Exceptions Type E4NF.nb in Table 2-50, “Type 
E4NF Class Exception Conditions.”
•EVEX-encoded VPSLLD/Q:
— Syntax with Mem128 tuple type (G in the operand encoding table), see Exceptions Type E4NF.nb in 
Table 2-50, “Type E4NF Class Exception Conditions.”
— Syntax with Full tuple type (F in the operand enco ding table), see Table 2-49, “Type E4 Class Exception 
Conditions.”PSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-449PSRAW/PSRAD/PSRAQ— Shift Packed Data  Right Arithmetic
Opcode/
NP 0F E1 /r
1
PSRAW mm, mm/m64A V/V MMX Shift words in mm right by mm/m64 while shifting 
in sign bits.
66 0F E1 /r
PSRAW xmm1, xmm2/m128A V/V SSE2 Shift words in xmm1 right by xmm2/m128 while 
shifting in sign bits.
NP 0F 71 /4 ib1
PSRAW mm, imm8B V/V MMX Shift words in mm right by imm8 while shifting in 
sign bits
66 0F 71 /4 ib
PSRAW xmm1, imm8B V/V SSE2 Shift words in xmm1 right by imm8 while shifting 
in sign bits
NP 0F E2 /r1
PSRAD mm, mm/m64A V/V MMX Shift doublewords in mm right by mm/m64 while 
66 0F E2 /r
PSRAD xmm1, xmm2/m128A V/V SSE2 Shift doubleword in xmm1 right by xmm2 /m128 
while shifting in sign bits.
NP 0F 72 /4 ib1
PSRAD mm, imm8BV / V M M X S h i f t  d o u b l e w o r d s  i n  mm right by imm8 while 
66 0F 72 /4 ib
PSRAD xmm1, imm8B V/V SSE2 Shift doublewords in xmm1 right by imm8 while 
VEX.128.66.0F.WIG E1 /r
VPSRAW xmm1, xmm2, xmm3/m128C V/V AVX Shift words in xmm2 ri ght by amount specified in 
xmm3/m128 while shifting in sign bits.
VEX.128.66.0F.WIG 71 /4 ib
VPSRAW xmm1, xmm2, imm8D V/V AVX Shift words in xmm2 ri ght by imm8 while shifting 
VEX.128.66.0F.WIG E2 /r
VPSRAD xmm1, xmm2, xmm3/m128C V/V AVX Shift doublewords in xmm2 right by amount 
specified in xmm3/m128 while shifting in sign 
bits.
VEX.128.66.0F.WIG 72 /4 ib
VPSRAD xmm1, xmm2, imm8D V/V AVX Shift doublewords in xmm2 right by imm8 while 
VEX.256.66.0F.WIG E1 /r
VPSRAW ymm1, ymm2, xmm3/m128C V/V AVX2 Shift words in ymm2 right by amount specified in 
VEX.256.66.0F.WIG 71 /4 ib
VPSRAW ymm1, ymm2, imm8D V/V AVX2 Shift words in ymm2 right by imm8 while shifting 
VEX.256.66.0F.WIG E2 /r
VPSRAD ymm1, ymm2, xmm3/m128C V/V AVX2 Shift doublewords in ymm2 right by amount 
bits.
VEX.256.66.0F.WIG 72 /4 ib
VPSRAD ymm1, ymm2, imm8D V/V AVX2 Shift doublewords in ymm2 right by imm8 while 
EVEX.128.66.0F.WIG E1 /r
VPSRAW xmm1 {k1}{z}, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512BWShift words in xmm2 right by amount specified in 
xmm3/m128 while shifting in sign bits using 
EVEX.256.66.0F.WIG E1 /r
VPSRAW ymm1 {k1}{z}, ymm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512BWShift words in ymm2 right by amount specified in 
xmm3/m128 while shifting in sign bits using writemask k1.
EVEX.512.66.0F.WIG E1 /r
VPSRAW zmm1 {k1}{z}, zmm2, xmm3/m128G V/V AVX512BW Shift words in zmm2 right by amount specified in 
writemask k1.PSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
4-450 Vol. 2BEVEX.128.66.0F.WIG 71 /4 ib
VPSRAW xmm1 {k1}{z}, xmm2/m128, imm8EV / V A V X 5 1 2 V L
AVX512BWShift words in xmm2/m128 right by imm8 while 
shifting in sign bits using writemask k1.
EVEX.256.66.0F.WIG 71 /4 ib
VPSRAW ymm1 {k1}{z}, ymm2/m256, imm8EV / V A V X 5 1 2 V L
AVX512BWShift words in ymm2/m256 right by imm8 while 
EVEX.512.66.0F.WIG 71 /4 ib
VPSRAW zmm1 {k1}{z}, zmm2/m512, imm8E V/V AVX512BW Shift words in zmm2/m512 right by imm8 while 
EVEX.128.66.0F.W0 E2 /r
VPSRAD xmm1 {k1}{z }, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512FShift doublewords in xmm2 right by amount 
specified in xmm3/m128 while shifting in sign bits 
EVEX.256.66.0F.W0 E2 /r
VPSRAD ymm1 {k1}{z}, ymm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512FShift doublewords in ymm2 right by amount 
specified in xmm3/m128 while shifting in sign bits using writemask k1.
EVEX.512.66.0F.W0 E2 /r
VPSRAD zmm1 {k1}{z}, zmm2, xmm3/m128G V/V AVX512F Shift doublewords in zmm2 right by amount 
EVEX.128.66.0F.W0 72 /4 ib
VPSRAD xmm1 {k1}{z},  xmm2/m128/m32bcst, 
AVX512FShift doublewords in xmm2/m128/m32bcst right 
by imm8 while shifting in sign bits using 
EVEX.256.66.0F.W0 72 /4 ib
VPSRAD ymm1 {k1}{z},  ymm2/m256/m32bcst, 
AVX512FShift doublewords in ymm2/m256/m32bcst right 
EVEX.512.66.0F.W0 72 /4 ib
VPSRAD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8F V/V AVX512F Shift doublewords in zmm2/m512/m32bcst right 
by imm8 while shifting in sign bits using writemask k1.
EVEX.128.66.0F.W1 E2 /r
VPSRAQ xmm1 {k1}{z}, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512FShift quadwords in xmm2 right by amount 
EVEX.256.66.0F.W1 E2 /r
VPSRAQ ymm1 {k1}{z}, ymm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512FShift quadwords in ymm2 right by amount 
EVEX.512.66.0F.W1 E2 /r
VPSRAQ zmm1 {k1}{z }, zmm2, xmm3/m128G V/V AVX512F Shift quadwords in zmm2 right by amount 
EVEX.128.66.0F.W1 72 /4 ib
VPSRAQ xmm1 {k1}{z}, xmm2/m128/m64bcst, 
AVX512FShift quadwords in xmm2/m128/m64bcst right by 
imm8 while shifting in sign bits using writemask 
k1.
EVEX.256.66.0F.W1 72 /4 ib
VPSRAQ ymm1 {k1}{z}, ymm2/m256/m64bcst, 
AVX512FShift quadwords in ymm2/m256/m64bcst right by 
k1.
EVEX.512.66.0F.W1 72 /4 ib
VPSRAQ zmm1 {k1}{z},  zmm2/m512/m64bcst, 
imm8F V/V AVX512F Shift quadwords in zmm2/m512/m64bcst right by 
imm8 while shifting in sign bits using writemask k1.
NOTES:
ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception  Conditions of Legacy SIMD Instructions Operating on MMX Reg is-
ters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.Opcode/
Mode 
Feature 
FlagDescriptionPSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-451Instruction Operand Encoding
Shifts the bits in the individual data elements (words, do ublewords or quadwords) in the destination operand (first 
operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data 
elements are shifted right, the empty high-order bits are filled with the initial value of the sign bit of the data 
element. If the value specified by the count operand is greate r than 15 (for words), 31 (f or doublewords), or 63 (for 
quadwords), each destination data element is filled with the initial value of the sign bit of the element. (Figure 4-18 
gives an example of shifting words in a 64-bit operand.)
Note that only the first 64-bits of a 128-bit count operan d are checked to compute the count. If the second source 
operand is a memory address, 128 bits are loaded.
The (V)PSRAW instruction shifts each of the words in the destination operand to the right by the number of bits 
specified in the count operand, and the (V)PSRAD instruct ion shifts each of the doublewords in the destination 
operand.
Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count

operand.
Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count 
operand can be either an MMX technology register or an 64-bit memory location. 
tion or an 8-bit immediate. If the count operand is a memo ry address, 128 bits are load ed but the upper 64 bits are 
ignored.
VEX.256 encoded version: The destination operand is a Y MM register. The source operand is a YMM register or a 
memory location. The count operand can come either from  an XMM register or a memory location or an 8-bit 
immediate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
E Full Mem EVEX.vvvv (w) ModRM:r/m (r) imm8 N/AF Full EVEX.vvvv (w) ModRM:r/m (r) imm8 N/A
GM e m 1 2 8 M o d R M : r e g  ( w )E V E X . vvvv (r) ModRM:r/m (r) N/A
Figure 4-18.  PSRAW and PSRAD Instruct ion Operation Using a 64-bit OperandDESTDESTPre-Shift
Post-ShiftShift RightX0
X0 >> COUNTX3 X2 X1
X1 >> COUNT X2 >> COUNT X3 >> COUNTwith Sign
ExtensionPSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
4-452 Vol. 2BEVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count 
Note: For shifts with an immediate count (VEX. 128.66.0F 71-73 /4, EVEX.128.66.0F 71-73 /4), 
VEX.vvvv/EVEX.vvvv encodes the destination register.
Operation
PSRAW (With 64-bit Operand)
THEN COUNT := 16;
FI;DEST[15:0] := SignExtend(DEST[15:0] 
>> COUNT);
(* Repeat shift operation for 2nd and 3rd words *)DEST[63:48] := SignExtend(DEST[63:48] 
>> COUNT);
PSRAD (with 64-bit operand)
THEN COUNT := 32;
FI;DEST[31:0] := SignExtend(DEST[31:0] 
>> COUNT);
DEST[63:32] := SignExtend(DEST[63:32] >> COUNT);
ARITHMETIC_RIGHT_SHIFT_DW ORDS1(SRC, COUNT_SRC)
DEST[31:0] := SignBit
ELSE
DEST[31:0] := SignExtend(SRC[31:0] >> COUNT);
FI;
ARITHMETIC_RIGHT_SHIFT_QW ORDS1(SRC, COUNT_SRC)
DEST[63:0] := SignBit
ELSE
DEST[63:0] := SignExtend(SRC[63:0] >> COUNT);
FI;
ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)
COUNT := COUNT_SRC[63:0];IF (COUNT > 15)
FI;DEST[15:0] := SignExtend(SRC[15:0] >> COUNT);
(* Repeat shift operation for 2nd through 15th words *)
DEST[255:240] := SignExtend(SRC[255:240] >> COUNT);PSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-453ARITHMETIC_RIGHT_SHIFT_DW ORDS_256b(SRC, COUNT_SRC)
COUNT := COUNT_SRC[63:0];IF (COUNT > 31)
FI;DEST[31:0] := SignExtend(SRC[31:0] >> COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[255:224] := SignExtend(SRC[255:224] >> COUNT);
ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC, VL) ; VL: 128b, 256b or 512b
COUNT := COUNT_SRC[63:0];IF (COUNT > 63)
THEN COUNT := 64;
FI;DEST[63:0] := SignExtend(SRC[63:0] >> COUNT);
DEST[VL-1:VL-64] := SignExtend(SRC[VL-1:VL-64] >> COUNT);
ARITHMETIC_RIGHT_SHIFT_ WORDS(SRC, COUNT_SRC)
DEST[127:112] := SignExtend(SRC[127:112] >> COUNT);
ARITHMETIC_RIGHT_SHIFT_ DWORDS(SRC, COUNT_SRC)
(* Repeat shift operation for 2nd through 3rd words *)
DEST[127:96] := SignExtend(SRC[127:96] >> COUNT);
VPSRAW (EVEX versions, xmm/m128)
TMP_DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)TMP_DEST[511:256] := ARITHMETIC_RIGHT _SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;
THEN DEST[i+15:i] := TMP_DEST[i+15:i]PSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
4-454 Vol. 2BELSE 
FI
FI;
VPSRAW (EVEX Versions, imm8)
TMP_DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)TMP_DEST[511:256] := ARITHMETIC_RIGHT _SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;
FI
FI;
VPSRAW (ymm, ymm, xmm/m128) - VEX
DEST[255:0] := ARITHMETIC_RIGH T_SHIFT_WORDS_256b(SRC1, SRC2)
VPSRAW (ymm, imm8) - VEX
DEST[255:0] := ARITHMETIC_RIGH T_SHIFT_WORDS_256b(SRC1, imm8)
VPSRAW (xmm, xmm, xmm/m128) - VEX
DEST[127:0] := ARITHMETIC_RI GHT_SHIFT_WORDS(SRC1, SRC2)
VPSRAW (xmm, imm8) - VEX
DEST[127:0] := ARITHMETIC_RI GHT_SHIFT_WORDS(SRC1, imm8)
DEST[MAXVL-1:128] := 0PSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-455PSRAW (xmm, xmm, xmm/m128)
DEST[127:0] := ARITHMETIC_RI GHT_SHIFT_WORDS(DEST, SRC)
PSRAW (xmm, imm8)
DEST[127:0] := ARITHMETIC_RI GHT_SHIFT_WORDS(DEST, imm8)
VPSRAD (EVEX Versions, imm8)
THEN DEST[i+31:i] := ARITHMETIC_RI GHT_SHIFT_DWORDS1(SRC1[31:0], imm8)
ELSE DEST[i+31:i] := ARITHMETIC_RIG HT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
FI;
ELSE 
FI
FI;
VPSRAD (EVEX Versions, xmm/m128)
TMP_DEST[127:0] := ARITHMETIC_RIGHT_S HIFT_DWORDS_128b(SRC1[127:0], SRC2)
TMP_DEST[255:0] := ARITHMETIC_RIGHT_S HIFT_DWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] := ARIT HMETIC_RIGHT_SHIFT_DWORDS_ 256b(SRC1[511:256], SRC2)
FI;
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0PSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
4-456 Vol. 2BVPSRAD (ymm, ymm, xmm/m128) - VEX
DEST[255:0] := ARITHMETIC_RIGHT_ SHIFT_DWORDS_256 b(SRC1, SRC2)
VPSRAD (ymm, imm8) - VEX
DEST[255:0] := ARITHMETIC_RIGHT_ SHIFT_DWORDS_256 b(SRC1, imm8)
VPSRAD (xmm, xmm, xmm/m128) - VEX
DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, SRC2)DEST[MAXVL-1:128] := 0
VPSRAD (xmm, imm8) - VEX
DEST[127:0] := ARITHMETIC_RIGH T_SHIFT_DWORDS(SRC1, imm8)
PSRAD (xmm, xmm, xmm/m128)
DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, SRC)DEST[MAXVL-1:128] (Unmodified)

FI;
FI
FI;
PSRAD (xmm, imm8)
DEST[127:0] := ARITHMETIC_RIGH T_SHIFT_DWORDS(DEST, imm8)
VPSRAQ (EVEX Versions, imm8)
THEN DEST[i+63:i] := ARITHMETIC_RI GHT_SHIFT_QWORDS1(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := ARITHMETIC_RIG HT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
FI;
ELSE 
FI
FI;
VPSRAQ (EVEX Versions, xmm/m128)
(KL, VL) = (2, 128), (4, 256), (8, 512)TMP_DEST[VL-1:0] := ARITHMETIC_RIGHT _SHIFT_QWORDS(SRC1[VL-1:0], SRC2, VL)
FOR j := 0 TO 7
THEN *DEST[i+63:i] remains unchanged*PSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-457ELSE *zeroing-masking* ; zeroing-masking 
FI
FI;
VPSRAD __m512i _mm512_srai_epi3 2(__m512i a, unsigned int imm);
VPSRAD __m512i _mm512_mask_srai_epi32(__m512i s,  __mmask16 k, __m512i a,  unsigned int imm);
VPSRAD __m512i _mm512_maskz_srai_epi32( __ mmask16 k, __m512i a, unsigned int imm);
VPSRAD __m256i _mm256_mask_srai_epi32(__m256i s,  __mmask8 k, __m256i a, unsigned int imm);
VPSRAD __m256i _mm256_maskz_srai_epi32( __ mmask8 k, __m256i a,  unsigned int imm);
VPSRAD __m128i _mm_mask_srai_epi32(__m128i s,  __mmask8 k, __m128i a, unsigned int imm);
VPSRAD __m128i _mm_maskz_srai_epi32( __mma sk8 k, __m128i a, unsigned int imm);
VPSRAD __m512i _mm512_sra_e pi32(__m512i a, __m128i cnt);
VPSRAD __m512i _mm512_mask_sra_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);VPSRAD __m512i _mm512_maskz_sra_epi32( __mmask16 k, __m512i a, __m128i cnt);
VPSRAD __m256i _mm256_mask_sra_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);VPSRAD __m256i _mm256_maskz_sra_epi32( __mmask8 k, __m256i a, __m128i cnt);
VPSRAD __m128i _mm_mask_sra_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRAD __m128i _mm_maskz_sra_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRAQ __m512i _mm512_srai_epi64(__m512i a, unsigned int imm);VPSRAQ __m512i _mm512_mask_srai _epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm)
VPSRAQ __m512i _mm512_maskz_srai_epi64( __mmask8 k, __m512i a, unsigned int imm)
VPSRAQ __m256i _mm256_mask_srai _epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRAQ __m256i _mm256_maskz_srai_epi64( __mmask8 k, __m256i a, unsigned int imm);
VPSRAQ __m128i _mm_mask_srai_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);VPSRAQ __m128i _mm_maskz_srai_epi64( __m mask8 k, __m128i a, unsigned int imm);
VPSRAQ __m512i _mm512_sra_epi64(__m512i a, __m128i cnt);VPSRAQ __m512i _mm512_mask_sra_epi64(__m512i  s, __mmask8 k, __m512i a, __m128i cnt)
VPSRAQ __m512i _mm512_maskz_sra_epi64( __mmask8 k, __m512i a, __m128i cnt)VPSRAQ __m256i _mm256_mask_sra_epi64(__m256i  s, __mmask8 k, __m256i a, __m128i cnt);
VPSRAQ __m256i _mm256_maskz_sra_epi64( __mmask8 k, __m256i a, __m128i cnt);VPSRAQ __m128i _mm_mask_sra_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);VPSRAQ __m128i _mm_maskz_sra_epi64( __mmask8 k, __m128i a, __m128i cnt);VPSRAW __m512i _mm512_srai_epi16( __m512i a, unsigned int imm);
VPSRAW __m512i _mm512_mask_srai_epi16(__m512i s,  __mmask32 k, __m512i a, unsigned int imm);
VPSRAW __m512i _mm512_maskz_srai_epi16( __m mask32 k, __m512i a,  unsigned int imm);
VPSRAW __m256i _mm256_mask_srai_epi16(__m256i s,  __mmask16 k, __m256i a, unsigned int imm);
VPSRAW __m256i _mm256_maskz_srai_epi16( __m mask16 k, __m256i a,  unsigned int imm);
VPSRAW __m128i _mm_mask_srai_epi16(__m128i s,  __mmask8 k, __m128i a,  unsigned int imm);
VPSRAW __m128i _mm_maskz_srai_epi16( __m mask8 k, __m128i a, unsigned int imm);
VPSRAW __m512i _mm512_sra_epi16(__m512i a, __m128i cnt);VPSRAW __m512i _mm512_mask_sra_epi16(__m512i s, __mmask16 k, __m5 12i a, __m128i cnt);
VPSRAW __m512i _mm512_maskz_sra_epi16( __mmask16 k, __m512i a, __m128i cnt);
VPSRAW __m256i _mm256_mask_sra_epi16(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRAW __m256i _mm256_maskz_sra_epi16( __mmask8 k, __m256i a, __m128i cnt);
VPSRAW __m128i _mm_mask_sra_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRAW __m128i _mm_maskz_sra_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSRAW __m64 _mm_srai_pi 16 (__m64 m, int count)
PSRAW __m64 _mm_sra_pi16 (__m64 m, __m64 count)(V)PSRAW __m128i _mm_srai_epi16(__m128i m, int count)PSRAW/PSRAD/PSRAQ—Shift Packed Data Right ArithmeticINSTRUCTION SET REFERENCE, M-U
4-458 Vol. 2B(V)PSRAW __m128i _mm_sra_epi16(__m128i m, __m128i count)
VPSRAW __m256i _mm256_srai_epi16 (__m256i m, int count)VPSRAW __m256i _mm256_sra_epi16 (__m256i m, __m128i count)PSRAD __m64 _mm_srai_pi32 (__m64 m, int count)PSRAD __m64 _mm_sra_pi32 (__m64 m, __m64 count)(V)PSRAD __m128i _mm_srai_epi32 (__m128i m, int count)(V)PSRAD __m128i _mm_sra_epi32 (__m128i m, __m128i count)VPSRAD __m256i _mm256_srai_epi32 (__m256i m, int count)VPSRAD __m256i _mm256_sra_epi32 (__m256i m, __m128i count)
None.
None.
•EVEX-encoded VPSRAW (E in the operand encoding table), see Exceptions Type E4NF.nb in Table 2-50, “Type 
•EVEX-encoded VPSRAD/Q:
Conditions.”PSRLDQ—Shift Double Quadword Right LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-459PSRLDQ—Shift Double Quadword Right Logical
Shifts the destination operand (first operand) to the righ t by the number of bytes specified in the count operand 
(second operand). The empty high-order bytes are cleared (set to all 0s). If the value specified by the count 
operand is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.
VEX.256 encoded version: The source operand is a YMM register. The destination operand is a YMM register. The 
count operand applies to both the low and high 128-bit lanes.
Note: VEX.vvvv/EVEX.vvvv encodes the destination register.Opcode/
Mode 
Feature 
66 0F 73 /3 ib
PSRLDQ xmm1, imm8A V/V SSE2 Shift xmm1 right by imm8 while shifting in 0s.
VEX.128.66.0F.WIG 73 /3 ib
VPSRLDQ xmm1, xmm2, imm8B V/V AVX Shift xmm2 right by imm8 bytes while shifting in 
0s.
VEX.256.66.0F.WIG 73 /3 ib
VPSRLDQ ymm1, ymm2, imm8B V/V AVX2 Shift ymm1 right by imm8 bytes while shifting in 
0s.
EVEX.128.66.0F.WIG 73 /3 ib
VPSRLDQ xmm1, xmm2/m128, imm8C V/V AVX512VL
AVX512BWShift xmm2/m128 right by imm8 bytes while 
EVEX.256.66.0F.WIG 73 /3 ib
VPSRLDQ ymm1, ymm2/m256, imm8C V/V AVX512VL
AVX512BWShift ymm2/m256 right by imm8 bytes while 
EVEX.512.66.0F.WIG 73 /3 ib
VPSRLDQ zmm1, zmm2/m512, imm8C V/V AVX512BW Shift zmm2/m512 right by imm8 bytes while 
C Full Mem EVEX.vvvv (w) M odRM:r/m (r) imm8 N/APSRLDQ—Shift Double Quadword Right LogicalINSTRUCTION SET REFERENCE, M-U
4-460 Vol. 2BOperation
VPSRLDQ (EVEX.512 Encoded Version)

0s.
0s.
TEMP := COUNTIF (TEMP > 15) THEN TEMP := 16; FIDEST[127:0] := SRC[127:0] >> (TEMP * 8)DEST[255:128] := SRC[255:128] >> (TEMP * 8)DEST[383:256] := SRC[383:256] >> (TEMP * 8)DEST[511:384] := SRC[511:384] >> (TEMP * 8)DEST[MAXVL-1:512] := 0;
VPSRLDQ (VEX.256 and EVEX.256 Encoded Version)
TEMP := COUNTIF (TEMP > 15) THEN TEMP := 16; FIDEST[127:0] := SRC[127:0] >> (TEMP * 8)DEST[255:128] := SRC[255:128] >> (TEMP * 8)DEST[MAXVL-1:256] := 0;
VPSRLDQ (VEX.128 and EVEX.128 Encoded Version)
TEMP := COUNTIF (TEMP > 15) THEN TEMP := 16; FIDEST := SRC >> (TEMP * 8)DEST[MAXVL-1:128] := 0;
PSRLDQ (128-bit Legacy SSE Version)
TEMP := COUNTIF (TEMP > 15) THEN TEMP := 16; FIDEST := DEST >> (TEMP * 8)DEST[MAXVL-1 :128] (Unmodified)
(V)PSRLDQ __m128i _mm_srli_si128 ( __m128i a, int imm)
VPSRLDQ __m256i _mm256_bsrli_e pi128 ( __m256i, const int)
VPSRLDQ __m512i _mm512_bsrli_epi128 ( __m512i, int)
None.
None.
EVEX-encoded instruction, see Exceptions Type E4NF.n b in Table 2-50, “Type E4NF Class Exception Conditions.”PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-461PSRLW/PSRLD/PSRLQ—Shift Pa cked Data Right Logical
Opcode/
NP 0F D1 /r
1
PSRLW mm, mm/m64A V/V MMX Shift words in mm right by amount specified in 
mm/m64 while shifting in 0s.
66 0F D1 /r
PSRLW xmm1, xmm2/m128A V/V SSE2 Shift words in xmm1 right by amount specified 
in xmm2/m128 while shifting in 0s.
NP 0F 71 /2 ib1
PSRLW mm, imm8B V/V MMX Shift words in mm right by imm8 while shifting 
in 0s.
66 0F 71 /2 ib
PSRLW xmm1, imm8B V/V SSE2 Shift words in xmm1 right by imm8 while 
NP 0F D2 /r1
PSRLD mm, mm/m64A V/V MMX Shift doublewords in mm right by amount 
specified in mm/m64 while shifting in 0s.
66 0F D2 /r
PSRLD xmm1, xmm2/m128A V/V SSE2 Shift doublewords in xmm1 right by amount 
specified in xmm2 /m128 while shifting in 0s.
NP 0F 72 /2 ib1
PSRLD mm, imm8B V/V MMX Shift doublewords in mm right by imm8 while 
66 0F 72 /2 ib
PSRLD xmm1, imm8B V/V SSE2 Shift doublewords in xmm1 right by imm8 
NP 0F D3 /r1
PSRLQ mm, mm/m64A V/V MMX Shift mm right by amount specified in 
66 0F D3 /r
PSRLQ xmm1, xmm2/m128A V/V SSE2 Shift quadwords in xmm1 right by amount 
specified in xmm2/m128 while shifting in 0s.
NP 0F 73 /2 ib1
PSRLQ mm, imm8B V/V MMX Shift mm right by imm8 while shifting in 0s.
66 0F 73 /2 ib
PSRLQ xmm1, imm8B V/V SSE2 Shift quadwords in xmm1 right by imm8 while 
VEX.128.66.0F.WIG D1 /r
VPSRLW xmm1, xmm2, xmm3/m128C V/V AVX Shift words in xmm2 right by amount specified 
in xmm3/m128 while shifting in 0s.
VEX.128.66.0F.WIG 71 /2 ib
VPSRLW xmm1, xmm2, imm8DV / V A V X S h i f t  w o r d s  i n  x m m2 right by imm8 while 
VEX.128.66.0F.WIG D2 /r
VPSRLD xmm1, xmm2, xmm3/m128C V/V AVX Shift doublewords in xmm2 right by amount 
VEX.128.66.0F.WIG 72 /2 ib
VPSRLD xmm1, xmm2, imm8D V/V AVX Shift doublewords in xmm2 right by imm8 
VEX.128.66.0F.WIG D3 /r
VPSRLQ xmm1, xmm2, xmm3/m128C V/V AVX Shift quadwords in xmm2 right by amount 
VEX.128.66.0F.WIG 73 /2 ib
VPSRLQ xmm1, xmm2, imm8D V/V AVX Shift quadwords in xmm2 right by imm8 while 
VEX.256.66.0F.WIG D1 /r
VPSRLW ymm1, ymm2, xmm3/m128C V/V AVX2 Shift words in ymm2 right by amount specified 
VEX.256.66.0F.WIG 71 /2 ib
VPSRLW ymm1, ymm2, imm8D V/V AVX2 Shift words in ymm2 right by imm8 while 
shifting in 0s.PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
4-462 Vol. 2BVEX.256.66.0F.WIG D2 /r
VPSRLD ymm1, ymm2, xmm3/m128C V/V AVX2 Shift doublewords in ymm2 right by amount 
VEX.256.66.0F.WIG 72 /2 ib
VPSRLD ymm1, ymm2, imm8D V/V AVX2 Shift doublewords in ymm2 right by imm8 
VEX.256.66.0F.WIG D3 /r
VPSRLQ ymm1, ymm2, xmm3/m128C V/V AVX2 Shift quadwords in ymm2 right by amount 
VEX.256.66.0F.WIG 73 /2 ib
VPSRLQ ymm1, ymm2, imm8D V/V AVX2 Shift quadwords in ymm2 right by imm8 while 
EVEX.128.66.0F.WIG D1 /r
VPSRLW xmm1 {k1}{z}, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512BWShift words in xmm2 right by amount specified 
in xmm3/m128 while shifting in 0s using 
EVEX.256.66.0F.WIG D1 /r
VPSRLW ymm1 {k1}{z}, ymm2, xmm3/m128GV / V A V X 5 1 2 V L
AVX512BWShift words in ymm2 right by amount specified 
EVEX.512.66.0F.WIG D1 /r
VPSRLW zmm1 {k1}{z}, zmm2, xmm3/m128G V/V AVX512BW Shift words in zmm2 right by amount specified 
EVEX.128.66.0F.WIG 71 /2 ib
VPSRLW xmm1 {k1}{z}, xmm2/m128, imm8EV / V A V X 5 1 2 V L
AVX512BWShift words in xmm2/m128 right by imm8 
while shifting in 0s using writemask k1.
EVEX.256.66.0F.WIG 71 /2 ib
VPSRLW ymm1 {k1}{z}, ymm2/m256, imm8EV / V A V X 5 1 2 V L
AVX512BWShift words in ymm2/m256 right by imm8 
EVEX.512.66.0F.WIG 71 /2 ib
VPSRLW zmm1 {k1}{z}, zmm2/m512, imm8E V/V AVX512BW Shift words in zmm2/m512 right by imm8 
EVEX.128.66.0F.W0 D2 /r
VPSRLD xmm1 {k1}{z}, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
EVEX.256.66.0F.W0 D2 /r
VPSRLD ymm1 {k1}{z}, ymm2, xmm3/m128GV / V A V X 5 1 2 V L
EVEX.512.66.0F.W0 D2 /r
VPSRLD zmm1 {k1}{z }, zmm2, xmm3/m128G V/V AVX512F Shift doublewords in zmm2 right by amount 
EVEX.128.66.0F.W0 72 /2 ib
VPSRLD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8FV / V A V X 5 1 2 V L
AVX512FShift doublewords in xmm2/m128/m32bcst 
right by imm8 while shifting in 0s using writemask k1.
EVEX.256.66.0F.W0 72 /2 ib
VPSRLD ymm1 {k1}{z},  ymm2/m256/m32bcst, 
AVX512FShift doublewords in ymm2/m256/m32bcst 
right by imm8 while shifting in 0s using 
EVEX.512.66.0F.W0 72 /2 ib
VPSRLD zmm1 {k1}{z}, zmm2/m512/m32bcst, 
imm8F V/V AVX512F Shift doublewo rds in zmm2/m512/m32bcst 
EVEX.128.66.0F.W1 D3 /r
VPSRLQ xmm1 {k1}{z}, xmm2, xmm3/m128GV / V A V X 5 1 2 V L
EVEX.256.66.0F.W1 D3 /r
VPSRLQ ymm1 {k1}{z}, ymm2, xmm3/m128GV / V A V X 5 1 2 V L
Mode 
Feature 
FlagDescriptionPSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-463Instruction Operand Encoding
elements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count 
operand is greater than 15 (for words), 31 (for doubleword s), or 63 (for a quadword), then the destination operand 
is set to all 0s. Figure 4-19 gives an exampl e of shifting words in a 64-bit operand. 
Note that only the low 64-bits of a 128-bit count operand are checked to compute the count.EVEX.512.66.0F.W1 D3 /r
VPSRLQ zmm1 {k1}{z}, zmm2, xmm3/m128GV / V A V X 5 1 2 F S h i f t  q u a d w o r d s  in zmm2 righ t by amount 
EVEX.128.66.0F.W1 73 /2 ib
VPSRLQ xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8FV / V A V X 5 1 2 V L
AVX512FShift quadwords in xmm2/m128/m64bcst 
EVEX.256.66.0F.W1 73 /2 ib
VPSRLQ ymm1 {k1}{z}, ymm2/m256/m64bcst, 
AVX512FShift quadwords in ymm2/m256/m64bcst 
EVEX.512.66.0F.W1 73 /2 ib
VPSRLQ zmm1 {k1}{z}, zmm2/m512/m64bcst, 
imm8F V/V AVX512F Shift quadwords in zmm2/m512/m64bcst 
NOTES:

NOTES:
G Mem128 ModRM:reg (w) EVEX. vvvv (r) ModRM:r/m (r) N/A
Figure 4-19.  PSRLW, PSRLD, and PSRLQ In struction Operation Us ing 64-bit OperandOpcode/
Mode 
Feature 
X1 >> COUNT X2 >> COUNT X3 >> COUNTwith Zero
ExtensionPSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
4-464 Vol. 2BThe (V)PSRLW instruction shifts each of the words in th e destination operand to the right by the number of bits 
specified in the count operand; the (V)PSRLD instruction sh ifts each of the doublewords in the destination operand; 
and the PSRLQ instruction shifts the quadword  (or quadwords) in the destination operand.
Legacy SSE instruction 64-bit operand: The destination op erand is an MMX technology register; the count operand 
128-bit Legacy SSE version: The destination operand is an  XMM register; the count operand can be either an XMM 
register or a 128-bit memory location, or an 8-bit immedi ate. If the count operand is a memory address, 128 bits 
are loaded but the upper 64 bits are ignored. Bits (MAX VL-1:128) of the corresponding YMM destination register 
remain unchanged.
VEX.128 encoded version: The destination operand is an XMM register; the count operand can be either an XMM 
are loaded but the upper 64 bits are ignored. Bits (M AXVL-1:128) of the destination YMM register are zeroed.
Note: For shifts with an immediate count (VEX. 128.66.0F 71-73 /2, or EVEX.128.66.0F 71-73 /2), 
Operation
PSRLW (With 64-bit Operand)
THEN 
DEST[64:0] := 0000000000000000H
ELSE
DEST[15:0] := ZeroExtend(DEST[15:0] >> COUNT);
>> COUNT);
FI;
PSRLD (With 64-bit Operand)
THEN 
ELSE
DEST[31:0] := ZeroExtend(DEST[31:0] >> COUNT);
DEST[63:32] := ZeroExtend(DEST[63:32] >> COUNT);
FI;
PSRLQ (With 64-bit Operand)
THEN 
ELSEPSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-465DEST := ZeroExtend(DEST >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)COUNT := COUNT_SRC[63:0];IF (COUNT > 31)THEN
ELSE
DEST[31:0] := ZeroExtend(SRC[31:0] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_QW ORDS1(SRC, COUNT_SRC)
ELSE
DEST[63:0] := ZeroExtend(SRC[63:0] >> COUNT);
FI;LOGICAL_RIGHT_SHIFT_WORD S_256b(SRC, COUNT_SRC)
DEST[255:0] := 0
ELSE
DEST[15:0] := ZeroExtend(SRC[15:0] >> COUNT);(* Repeat shift operation for 2nd through 15th words *)DEST[255:240] := ZeroExtend(SRC[255:240] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)
ELSE
DEST[15:0] := ZeroExtend(SRC[15:0] >> COUNT);(* Repeat shift operation for 2nd through 7th words *)DEST[127:112] := ZeroExtend(SRC[127:112] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_DWOR DS_256b(SRC, COUNT_SRC)
ELSE
DEST[31:0] := ZeroExtend(SRC[31:0] >> COUNT);(* Repeat shift operation for 2nd through 3rd words *)DEST[255:224] := ZeroExtend(SRC[255:224] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_DW ORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC[63:0];PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
4-466 Vol. 2BIF (COUNT > 31)
THEN
ELSE
DEST[31:0] := ZeroExtend(SRC[31:0] >> COUNT);(* Repeat shift operation for 2nd through 3rd words *)DEST[127:96] := ZeroExtend(SRC[127:96] >> COUNT);
FI;LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)COUNT := COUNT_SRC[63:0];IF (COUNT > 63)THEN
ELSE
DEST[63:0] := ZeroExtend(SRC[63:0] >> COUNT);DEST[127:64] := ZeroExtend(SRC[127:64] >> COUNT);DEST[191:128] := ZeroExtend(SRC[191:128] >> COUNT);DEST[255:192] := ZeroExtend(SRC[255:192] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC)
ELSE
DEST[63:0] := ZeroExtend(SRC[63:0] >> COUNT);DEST[127:64] := ZeroExtend(SRC[127:64] >> COUNT);
FI;
VPSRLW (EVEX Versions, xmm/m128)
TMP_DEST[127:0] := LOGICAL_RIGHT_SH IFT_WORDS_128b(SRC1 [127:0], SRC2)
TMP_DEST[255:0] := LOGICAL_RIGHT_SH IFT_WORDS_256b(SRC1 [255:0], SRC2)
TMP_DEST[511:256] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;
FI
FI;PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-467ENDFOR
VPSRLW (EVEX Versions, imm8)
TMP_DEST[127:0] := LOGICAL_RIGHT_SH IFT_WORDS_128b(SRC1[127:0], imm8)
TMP_DEST[511:256] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;
FI
FI;
VPSRLW (ymm, ymm, xmm/m128) - VEX.256 Encoding
DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0;
VPSRLW (ymm, imm8) - VEX.256 Encoding
DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)DEST[MAXVL-1:256] := 0;
VPSRLW (xmm, xmm, xmm/m128) - VEX.128 Encoding
DEST[127:0] := LOGICAL_RIGHT_SHIFT_WORDS(SRC1, SRC2)DEST[MAXVL-1:128] := 0
VPSRLW (xmm, imm8) - VEX.128 Encoding
DEST[127:0] := LOGICAL_RIGH T_SHIFT_WORDS(SRC1, imm8)
PSRLW (xmm, xmm, xmm/m128)
DEST[127:0] := LOGICAL_RIGHT_SHIFT_WORDS(DEST, SRC)DEST[MAXVL-1:128 ] (Unmodified)
PSRLW (xmm, imm8)
DEST[127:0] := LOGICAL_RIGH T_SHIFT_WORDS(DEST, imm8)
DEST[MAXVL-1:128 ] (Unmodified)PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
4-468 Vol. 2BVPSRLD (EVEX Versions, xmm/m128)
TMP_DEST[127:0] := LOGICAL_RIGHT_SH IFT_DWORDS_128b(SR C1[127:0], SRC2)
TMP_DEST[255:0] := LOGICAL_RIGHT_SH IFT_DWORDS_256b(SR C1[255:0], SRC2)
TMP_DEST[511:256] := LOGICAL_RIGHT_SH IFT_DWORDS_256b(SRC1[511:256], SRC2)
FI;

FI;
FI
FI;
VPSRLD (EVEX Versions, imm8)
THEN DEST[i+31:i] := LOGICAL_RIGH T_SHIFT_DWORDS1(SRC1[31:0], imm8)
ELSE DEST[i+31:i] := LOGICAL_RIGH T_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
FI;
ELSE 
FI
FI;
VPSRLD (ymm, ymm, xmm/m128) - VEX.256 Encoding
DEST[255:0] := LOGICAL_RIGHT_ SHIFT_DWORDS_256b(SRC1, SRC2)
VPSRLD (ymm, imm8) - VEX.256 Encoding
DEST[255:0] := LOGICAL_RIGHT_ SHIFT_DWORDS_256 b(SRC1, imm8)
DEST[MAXVL-1:256] := 0;PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-469VPSRLD (xmm, xmm, xmm/m128) - VEX.128 Encoding
DEST[127:0] := LOGICAL_RIGH T_SHIFT_DWORDS(SRC1, SRC2)
VPSRLD (xmm, imm8) - VEX.128 Encoding
DEST[127:0] := LOGICAL_RIGH T_SHIFT_DWORDS(SRC1, imm8)
PSRLD (xmm, xmm, xmm/m128)
DEST[127:0] := LOGICAL_RIGHT_SHIFT_DWORDS(DEST, SRC)DEST[MAXVL-1:128 ] (Unmodified)
PSRLD (xmm, imm8)
DEST[127:0] := LOGICAL_RIGHT_SHIFT_DWORDS(DEST, imm8)DEST[MAXVL-1:128 ] (Unmodified)
VPSRLQ (EVEX Versions, xmm/m128)
TMP_DEST[255:0] := LOGICAL_RIGHT_SH IFT_QWORDS_256b(SR C1[255:0], SRC2)
TMP_DEST[511:256] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)IF VL = 128
TMP_DEST[127:0] := LOGICAL_RIGHT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)
TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)TMP_DEST[511:256] := LOGICAL_RIGHT_SH IFT_QWORDS_256b(SRC1[511:256], SRC2)
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
4-470 Vol. 2BVPSRLQ (EVEX Versions, imm8)
THEN DEST[i+63:i] := LOGICAL_RIGH T_SHIFT_QWORDS1(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
FI;
ELSE 
FI
FI;
VPSRLQ (ymm, ymm, xmm/m128) - VEX.256 Encoding
DEST[255:0] := LOGICAL_RIGHT_ SHIFT_QWORDS_256b(SRC1, SRC2)
VPSRLQ (ymm, imm8) - VEX.256 Encoding
DEST[255:0] := LOGICAL_RIGHT_ SHIFT_QWORDS_256b(SRC1, imm8)
DEST[MAXVL-1:256] := 0;VPSRLQ (xmm, xmm, xmm/m128) - VEX.128 EncodingDEST[127:0] := LOGICAL_RIGH T_SHIFT_QWORDS(SRC1, SRC2)
VPSRLQ (xmm, imm8) - VEX.128 Encoding
DEST[127:0] := LOGICAL_RIGH T_SHIFT_QWORDS(SRC1, imm8)
PSRLQ (xmm, xmm, xmm/m128)
DEST[127:0] := LOGICAL_RIGH T_SHIFT_QWORDS(DEST, SRC)
PSRLQ (xmm, imm8)
DEST[127:0] := LOGICAL_RIGH T_SHIFT_QWORDS(DEST, imm8)
VPSRLD __m512i _mm512_srli_epi32( __m512i a, unsigned int imm);
VPSRLD __m512i _mm512_mask_srli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);VPSRLD __m512i _mm512_maskz_srli_epi32( __mma sk16 k, __m512i a, unsigned int imm);
VPSRLD __m256i _mm256_mask_srli_epi32(__m256i s,  __mmask8 k, __m256i a,  unsigned int imm);
VPSRLD __m256i _mm256_maskz_srli_epi32( __mmask8 k, __m256i a, unsigned int imm);VPSRLD __m128i _mm_mask_srli_epi32(__m128i s,  __mmask8 k, __m128i a, unsigned int imm);
VPSRLD __m128i _mm_maskz_srli_epi32( __m mask8 k, __m128i a, unsigned int imm);
VPSRLD __m512i _mm512_srl_epi32(__m512i a, __m128i cnt);VPSRLD __m512i _mm512_mask_srl_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);VPSRLD __m512i _mm512_maskz_srl_epi32( __mmask16 k, __m512i a, __m128i cnt);PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-471VPSRLD __m256i _mm256_mask_srl_epi32(__m256i  s, __mmask8 k, __m256i a, __m128i cnt);
VPSRLD __m256i _mm256_maskz_srl_epi32( __mmask8 k, __m256i a, __m128i cnt);
VPSRLD __m128i _mm_mask_srl_epi32(__m128i  s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLD __m128i _mm_maskz_srl_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRLQ __m512i _mm512_srli_epi64( __m512i a, unsigned int imm);
VPSRLQ __m512i _mm512_mask_srli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);
VPSRLQ __m512i _mm512_mask_srli_epi64( __m mask8 k, __m512i a, unsigned int imm);
VPSRLQ __m256i _mm256_mask_srli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRLQ __m256i _mm256_maskz_srli_epi64( __ mmask8 k, __m256i a, unsigned int imm);
VPSRLQ __m128i _mm_mask_srli_epi64(__m128i s,  __mmask8 k, __m128i a,  unsigned int imm);
VPSRLQ __m128i _mm_maskz_sr li_epi64( __mmask8 k, __m128i a, unsigned int imm);
VPSRLQ __m512i _mm512_srl_epi 64(__m512i a, __m128i cnt);
VPSRLQ __m512i _mm512_mask_srl_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);VPSRLQ __m512i _mm512_mask_srl_epi64(  __mmask8 k, __m512i a, __m128i cnt);
VPSRLQ __m256i _mm256_mask_srl_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);VPSRLQ __m256i _mm256_maskz_srl_epi64( __mmask8 k, __m256i a, __m128i cnt);VPSRLQ __m128i _mm_mask_srl_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLQ __m128i _mm_maskz_srl_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRLW __m512i _mm512_srli_epi16(__m512i a, unsigned int imm);VPSRLW __m512i _mm512_mask_srli_epi16(__m512i s,  __mmask32 k, __m512i a, unsigned int imm);
VPSRLW __m512i _mm512_maskz_srli_epi16( __ mmask32 k, __m512i a, unsigned int imm);
VPSRLW __m256i _mm256_mask_srli_epi16(__m256i s,  __mmask16 k, __m256i a, unsigned int imm);
VPSRLW __m256i _mm256_maskz_srli_epi16( __ mmask16 k, __m256i a, unsigned int imm);
VPSRLW __m128i _mm_mask_srli_epi16(__m128i s,  __mmask8 k, __m128i a, unsigned int imm);
VPSRLW __m128i _mm_maskz_sr li_epi16( __mmask8 k, __m128i a, unsigned int imm);
VPSRLW __m512i _mm512_srl_epi 16(__m512i a, __m128i cnt);
VPSRLW __m512i _mm512_mask_srl_epi16(__m512 i s, __mmask32 k, __m512i a, __m128i cnt);
VPSRLW __m512i _mm512_maskz_srl_epi16( __mmask32 k, __m512i a, __m128i cnt);
VPSRLW __m256i _mm256_mask_srl_epi16(__m256 i s, __mmask16 k, __m256i a, __m128i cnt);
VPSRLW __m256i _mm256_maskz_srl_epi16( __mmask8 k, __mmask16 a, __m128i cnt);
VPSRLW __m128i _mm_mask_srl _epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLW __m128i _mm_maskz_srl_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSRLW __m64 _mm_srli_pi16(__m64 m, int count)PSRLW __m64 _mm_srl_pi16 (__m64 m, __m64 count)(V)PSRLW __m128i _mm_srli_epi16 (__m128i m, int count)(V)PSRLW __m128i _mm_srl_epi16 (__m128i m, __m128i count)VPSRLW __m256i _mm256_srli_epi16 (__m256i m, int count)VPSRLW __m256i _mm256_srl_epi 16 (__m256i m, __m128i count)
PSRLD __m64 _mm_srli_pi 32 (__m64 m, int count)
PSRLD __m64 _mm_srl_pi32 (__m64 m, __m64 count)(V)PSRLD __m128i _mm_srli_epi32 (__m128i m, int count)(V)PSRLD __m128i _mm_srl_epi32 (__m128i m, __m128i count)VPSRLD __m256i _mm256_srli_epi32 (__m256i m, int count)VPSRLD __m256i _mm256_srl_epi32 (__m256i m, __m128i count)PSRLQ __m64 _mm_srli_si64 (__m64 m, int count)PSRLQ __m64 _mm_srl_si64 (__m64 m, __m64 count)(V)PSRLQ __m128i _mm_srli_epi64 (__m128i m, int count)(V)PSRLQ __m128i _mm_srl_epi6 4 (__m128i m, __m128i count)
VPSRLQ __m256i _mm256_srli_ep i64 (__m256i m, int count)
VPSRLQ __m256i _mm256_srl_epi64 (__m256i m, __m128i count)
None.PSRLW/PSRLD/PSRLQ—Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, M-U
4-472 Vol. 2BNumeric Exceptions
None.
•EVEX-encoded VPSRLW (E in the operand encoding table), see Exceptions Type E4NF.nb in Table 2-50, “Type 
•EVEX-encoded VPSRLD/Q:
Conditions.”PSUBB/PSUBW/PSUBD—Subt ract Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-473PSUBB/PSUBW/PSUBD—Subt ract Packed Integers
Opcode/
En64/32 bit

None.
Opcode/
NP 0F F8 /r
1
PSUBB mm, mm/m64A V/V MMX Subtract packed by te integers in mm/m64 
from packed byte  integers in mm.
66 0F F8 /r
PSUBB xmm1, xmm2/m128A V/V SSE2 Subtract packed byte  integers in xmm2/m128 
from packed byte integers in xmm1.
NP 0F F9 /r1
PSUBW mm, mm/m64A V/V MMX Subtract packed wo rd integers in mm/m64 
from packed word  integers in mm.
66 0F F9 /r
PSUBW xmm1, xmm2/m128A V/V SSE2 Subtract packed  word integers in 
xmm2/m128 from packed word integers in xmm1.
NP 0F FA /r
1
PSUBD mm, mm/m64A V/V MMX Subtract packed do ubleword integers in 
mm/m64 from packed doubleword integers in 
mm.
66 0F FA /r
PSUBD xmm1, xmm2/m128A V/V SSE2 Subtract packed do ubleword integers in 
xmm2/mem128 from packed doubleword 
VEX.128.66.0F.WIG F8 /r
VPSUBB xmm1, xmm2, xmm3/m128B V/V AVX Subtract packed byte  integers in xmm3/m128 
from xmm2.
VEX.128.66.0F.WIG F9 /r
VPSUBW xmm1, xmm2, xmm3/m128B V/V AVX Subtract packed  word integers in 
xmm3/m128 from xmm2.
VEX.128.66.0F.WIG FA /r
VPSUBD xmm1, xmm2, xmm3/m128B V/V AVX Subtract packed do ubleword integers in 
VEX.256.66.0F.WIG F8 /r
VPSUBB ymm1, ym m2, ymm3/m256B V/V AVX2 Subtract packed byte  integers in ymm3/m256 
from ymm2.
VEX.256.66.0F.WIG F9 /r
VPSUBW ymm1, ymm2, ymm3/m256B V/V AVX2 Subtract packed  word integers in 
ymm3/m256 from ymm2.
VEX.256.66.0F.WIG FA /r
VPSUBD ymm1, ymm2, ymm3/m256B V/V AVX2 Subtract packed do ubleword integers in 
EVEX.128.66.0F.WIG F8 /r
VPSUBB xmm1 {k1}{z}, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWSubtract packed byte in tegers in xmm3/m128 
from xmm2 and stor e in xmm1 using 
EVEX.256.66.0F.WIG F8 /r
VPSUBB ymm1 {k1}{z }, ymm2, ymm3/m256C V/V AVX512VL
AVX512BWSubtract packed byte in tegers in ymm3/m256 
from ymm2 and store in ymm1 using writemask k1.
EVEX.512.66.0F.WIG F8 /r
VPSUBB zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Subtract packed by te integers in zmm3/m512 
from zmm2 and store in zmm1 using 
EVEX.128.66.0F.WIG F9 /r
VPSUBW xmm1 {k1}{z }, xmm2, xmm3/m128C V/V AVX512VL
AVX512BWSubtract packed wo rd integers in 
xmm3/m128 from xmm2 and store in xmm1 
EVEX.256.66.0F.WIG F9 /r
VPSUBW ymm1 {k1}{z}, ymm2, ymm3/m256C V/V AVX512VL
ymm3/m256 from ymm2 and store in ymm1 using writemask k1.
EVEX.512.66.0F.WIG F9 /r
VPSUBW zmm1 {k1}{z }, zmm2, zmm3/m512C V/V AVX512BW Subtract pack ed word integers in 
zmm3/m512 from zmm2 and store in zmm1 
using writemask k1.PSUBB/PSUBW/PSUBD—Subt ract Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-474 Vol. 2BInstruction Operand Encoding
Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed integers 
of the destination operand (first operand), and stores th e packed integer results in the destination operand. See 
Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a 
SIMD operation. Overflow is handled with wrapar ound, as described in the following paragraphs.
The (V)PSUBB instruction subtracts packed byte integers. When  an individual result is too large or too small to be 
represented in a byte, the result is wrapped around an d the low 8 bits are written to the destination element.
The (V)PSUBW instruction subtracts packed word integers. When  an individual result is too large or too small to be 
represented in a word, the result is wrapped around and the low 16 bits are written to the destination element.
The (V)PSUBD instruction subtra cts packed doubleword integers. When an in dividual result is too large or too small 
to be represented in a doubleword, the result is wrapped around and the low 32 bits are written to the destination 
element.
Note that the (V)PSUBB, (V)PSUBW, and (V)PSUBD instructions can operate on  either unsigned or signed (two's 
complement notation) packed integers; however, it does no t set bits in the EFLAGS register to indicate overflow 
and/or a carry. To prevent undetected overflow conditions, software must control the ranges of values upon which 
it operates.
Legacy SSE version 64-bit operand: The destination operan d must be an MMX technology register and the source 
operand can be either an MMX technology register or a 64-bit memory location.
source operand and destination operands are XMM register s. Bits (MAXVL-1:128) of the corresponding YMM desti-
nation register remain unchanged.EVEX.128.66.0F.W0 FA /r
VPSUBD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst D V/V AVX512VL
AVX512FSubtract packed double word integers in 
xmm3/m128/m32bcst from xmm2 and store 
EVEX.256.66.0F.W0 FA /r
VPSUBD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstD V/V AVX512VL
ymm3/m256/m32bcst from ymm2 and store in ymm1 using writemask k1.
EVEX.512.66.0F.W0 FA /r
VPSUBD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst D V/V AVX512F Subtract packed doubleword integers in 
zmm3/m512/m32bcst from zmm2 and store 
in zmm1 using writemask k1
NOTES:
ware Developer’s Manual, Vo lume 2A, and Section 23.25.3, “Exc eption Conditions of Legacy SIMD Instructions Operating on MMX Reg -
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/A
Mode 
Feature 
FlagDescriptionPSUBB/PSUBW/PSUBD—Subt ract Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-475VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first 
source operand and destination operands  are XMM registers. Bits (MAXVL-1:128) of the destination YMM register 
are zeroed. 
VEX.256 encoded versions: The second source operand is an  YMM register or an 256-bit memory location. The first 
source operand and destination operands are YMM regi sters. Bits (MAXVL-1:256) of the corresponding ZMM 
EVEX encoded VPSUBD: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and 
destination operands are ZMM/YMM/XMM registers. The de stination is conditionally updated with writemask k1.
EVEX encoded VPSUBB/W: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory 
Operation
PSUBB (With 64-bit Operands)
DEST[7:0] := DEST[7:0] − SRC[7:0]; 
(* Repeat subtract operation for 2nd through 7th byte *)DEST[63:56] := DEST[63:56] 
− SRC[63:56];
PSUBW (With 64-bit Operands)
DEST[15:0] := DEST[15:0] − SRC[15:0];
(* Repeat subtract operation for 2nd and 3rd word *)DEST[63:48] := DEST[63:48] 
− SRC[63:48];
PSUBD (With 64-bit Operands)
DEST[31:0] := DEST[31:0] − SRC[31:0];
DEST[63:32] := DEST[63:32] − SRC[63:32];
PSUBD (With 128-bit Operands)
(* Repeat subtract operation for 2nd and 3rd doubleword *)DEST[127:96] := DEST[127:96] 
− SRC[127:96];
VPSUBB (EVEX Encoded Versions) 
THEN DEST[i+7:i] := SR C1[i+7:i] - SRC2[i+7:i]
ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PSUBB/PSUBW/PSUBD—Subt ract Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-476 Vol. 2BVPSUBW (EVEX Encoded Versions) 
THEN DEST[i+15:i] := SR C1[i+15:i] - SRC2[i+15:i]
ELSE 
FI
FI;
VPSUBD (EVEX Encoded Versions)
THEN DEST[i+31:i] := SRC1[i+31:i] - SRC2[31:0]ELSE DEST[i+31:i] := SRC1[i+31:i] - SRC2[i+31:i]
FI;
ELSE 
FI

FI
FI;
ELSE 
FI
FI;
FI;
ELSE 
FI
FI;
VPSUBB (VEX.256 Encoded Version)
DEST[7:0] := SRC1[7:0]-SRC2[7:0]DEST[15:8] := SRC1[15:8]-SRC2[15:8]DEST[23:16] := SRC1[23:16]-SRC2[23:16]DEST[31:24] := SRC1[31:24]-SRC2[31:24]DEST[39:32] := SRC1[39:32]-SRC2[39:32]DEST[47:40] := SRC1[47:40]-SRC2[47:40]DEST[55:48] := SRC1[55:48]-SRC2[55:48]DEST[63:56] := SRC1[63:56]-SRC2[63:56]DEST[71:64] := SRC1[71:64]-SRC2[71:64]DEST[79:72] := SRC1[79:72]-SRC2[79:72]DEST[87:80] := SRC1[87:80]-SRC2[87:80]DEST[95:88] := SRC1[95:88]-SRC2[95:88]DEST[103:96] := SRC1[103:96]-SRC2[103:96]DEST[111:104] := SRC1[111:104]-SRC2[111:104]DEST[119:112] := SRC1[119:112]-SRC2[119:112]DEST[127:120] := SRC1[127:120]-SRC2[127:120]DEST[135:128] := SRC1[135:128]-SRC2[135:128]DEST[143:136] := SRC1[143:136]-SRC2[143:136]PSUBB/PSUBW/PSUBD—Subt ract Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-477DEST[151:144] := SRC1[1 51:144]-SRC2[151:144]
DEST[159:152] := SRC1[1 59:152]-SRC2[159:152]
DEST[167:160] := SRC1[1 67:160]-SRC2[167:160]
DEST[175:168] := SRC1[1 75:168]-SRC2[175:168]
DEST[183:176] := SRC1[1 83:176]-SRC2[183:176]
DEST[191:184] := SRC1[1 91:184]-SRC2[191:184]
DEST[199:192] := SRC1[1 99:192]-SRC2[199:192]
DEST[207:200] := SRC1[2 07:200]-SRC2[207:200]
DEST[215:208] := SRC1[2 15:208]-SRC2[215:208]
DEST[223:216] := SRC1[2 23:216]-SRC2[223:216]
DEST[231:224] := SRC1[2 31:224]-SRC2[231:224]
DEST[239:232] := SRC1[2 39:232]-SRC2[239:232]
DEST[247:240] := SRC1[2 47:240]-SRC2[247:240]
DEST[255:248] := SRC1[2 55:248]-SRC2[255:248]
VPSUBB (VEX.128 Encoded Version)
DEST[7:0] := SRC1[7:0]-SRC2[7:0]DEST[15:8] := SRC1[15:8]-SRC2[15:8]DEST[23:16] := SRC1[23:16]-SRC2[23:16]DEST[31:24] := SRC1[31:24]-SRC2[31:24]DEST[39:32] := SRC1[39:32]-SRC2[39:32]DEST[47:40] := SRC1[47:40]-SRC2[47:40]DEST[55:48] := SRC1[55:48]-SRC2[55:48]DEST[63:56] := SRC1[63:56]-SRC2[63:56]DEST[71:64] := SRC1[71:64]-SRC2[71:64]DEST[79:72] := SRC1[79:72]-SRC2[79:72]DEST[87:80] := SRC1[87:80]-SRC2[87:80]DEST[95:88] := SRC1[95:88]-SRC2[95:88]DEST[103:96] := SRC1[103:96]-SRC2[103:96]DEST[111:104] := SRC1[1 11:104]-SRC2[111:104]
DEST[119:112] := SRC1[1 19:112]-SRC2[119:112]
DEST[127:120] := SRC1[1 27:120]-SRC2[127:120]
PSUBB (128-bit Legacy SSE Version)
DEST[7:0] := DEST[7:0]-SRC[7:0]DEST[15:8] := DEST[15:8]-SRC[15:8]DEST[23:16] := DEST[23:16]-SRC[23:16]DEST[31:24] := DEST[31:24]-SRC[31:24]DEST[39:32] := DEST[39:32]-SRC[39:32]DEST[47:40] := DEST[47:40]-SRC[47:40]DEST[55:48] := DEST[55:48]-SRC[55:48]DEST[63:56] := DEST[63:56]-SRC[63:56]DEST[71:64] := DEST[71:64]-SRC[71:64]DEST[79:72] := DEST[79:72]-SRC[79:72]DEST[87:80] := DEST[87:80]-SRC[87:80]DEST[95:88] := DEST[95:88]-SRC[95:88]DEST[103:96] := DEST[103:96]-SRC[103:96]DEST[111:104] := DEST[111:104]-SRC[111:104]DEST[119:112] := DEST[119:112]-SRC[119:112]DEST[127:120] := DEST[127:120]-SRC[127:120]DEST[MAXVL-1:128 ] (Unmodified)PSUBB/PSUBW/PSUBD—Subt ract Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-478 Vol. 2BVPSUBW (VEX.256 Encoded Version)
DEST[15:0] := SRC1[15:0]-SRC2[15:0]DEST[31:16] := SRC1[31:16]-SRC2[31:16]DEST[47:32] := SRC1[47:32]-SRC2[47:32]DEST[63:48] := SRC1[63:48]-SRC2[63:48]DEST[79:64] := SRC1[79:64]-SRC2[79:64]DEST[95:80] := SRC1[95:80]-SRC2[95:80]DEST[111:96] := SRC1[111:96]-SRC2[111:96]DEST[127:112] := SRC1[127:112]-SRC2[127:112]DEST[143:128] := SRC1[143:128]-SRC2[143:128]DEST[159:144] := SRC1[159:144]-SRC2[159:144]DEST[175:160] := SRC1[175:160]-SRC2[175:160]DEST[191:176] := SRC1[191:176]-SRC2[191:176]DEST[207:192] := SRC1207:192]-SRC2[207:192]DEST[223:208] := SRC1[223:208]-SRC2[223:208]DEST[239:224] := SRC1[239:224]-SRC2[239:224]DEST[255:240] := SRC1[255:240]-SRC2[255:240]DEST[MAXVL-1:256] := 0
VPSUBW (VEX.128 Encoded Version)
DEST[15:0] := SRC1[15:0]-SRC2[15:0]DEST[31:16] := SRC1[31:16]-SRC2[31:16]DEST[47:32] := SRC1[47:32]-SRC2[47:32]DEST[63:48] := SRC1[63:48]-SRC2[63:48]DEST[79:64] := SRC1[79:64]-SRC2[79:64]DEST[95:80] := SRC1[95:80]-SRC2[95:80]DEST[111:96] := SRC1[111:96]-SRC2[111:96]DEST[127:112] := SRC1[127:112]-SRC2[127:112]DEST[MAXVL-1:128] := 0
PSUBW (128-bit Legacy SSE Version)
DEST[15:0] := DEST[15:0]-SRC[15:0]DEST[31:16] := DEST[31:16]-SRC[31:16]DEST[47:32] := DEST[47:32]-SRC[47:32]DEST[63:48] := DEST[63:48]-SRC[63:48]DEST[79:64] := DEST[79:64]-SRC[79:64]DEST[95:80] := DEST[95:80]-SRC[95:80]DEST[111:96] := DEST[111:96]-SRC[111:96]DEST[127:112] := DEST[127:112]-SRC[127:112]DEST[MAXVL-1:128] (Unmodified)
VPSUBD (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0]-SRC2[31:0]DEST[63:32] := SRC1[63:32]-SRC2[63:32]DEST[95:64] := SRC1[95:64]-SRC2[95:64]DEST[127:96] := SRC1[127:96]-SRC2[127:96]DEST[159:128] := SRC1[159:128]-SRC2[159:128]DEST[191:160] := SRC1[191:160]-SRC2[191:160]DEST[223:192] := SRC1[223:192]-SRC2[223:192]DEST[255:224] := SRC1[255:224]-SRC2[255:224]DEST[MAXVL-1:256] := 0PSUBB/PSUBW/PSUBD—Subt ract Packed IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-479VPSUBD (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0]-SRC2[31:0]DEST[63:32] := SRC1[63:32]-SRC2[63:32]DEST[95:64] := SRC1[95:64]-SRC2[95:64]DEST[127:96] := SRC1[127:96]-SRC2[127:96]DEST[MAXVL-1:128] := 0
PSUBD (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0]-SRC[31:0]DEST[63:32] := DEST[63:32]-SRC[63:32]DEST[95:64] := DEST[95:64]-SRC[95:64]DEST[127:96] := DEST[127:96]-SRC[127:96]DEST[MAXVL-1:128 ] (Unmodified)
VPSUBB __m512i _mm512_sub_epi8(__m512i a, __m512i b);
VPSUBB __m512i _mm512_mask_sub_epi8(__m512i  s, __mmask64 k, __ m512i a, __m512i b);
VPSUBB __m512i _mm512_maskz_sub_epi8( __mmask64 k, __m512i a, __m512i b);VPSUBB __m256i _mm256_mask_sub_epi8(__m256i  s, __mmask32 k, __ m256i a, __m256i b);
VPSUBB __m256i _mm256_maskz_sub_epi8( __mmask32 k, __m256i a, __m256i b);VPSUBB __m128i _mm_mask_sub_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSUBB __m128i _mm_maskz_sub_epi8( __mmask16 k, __m128i a, __m128i b);VPSUBW __m512i _mm512_sub_epi16(__m512i a, __m512i b);VPSUBW __m512i _mm512_mask_sub_epi16(__m512 i s, __mmask32 k, __m512i a, __m512i b);
VPSUBW __m512i _mm512_maskz_sub_epi16( __mmask32 k, __m512i a, __m512i b);
VPSUBW __m256i _mm256_mask_sub_epi16(__m256 i s, __mmask16 k, __m256i a, __m256i b);
VPSUBW __m256i _mm256_maskz_sub_epi16( __mmask16 k, __m256i a, __m256i b);
VPSUBW __m128i _mm_mask_sub_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);VPSUBW __m128i _mm_maskz_sub_epi16( __mmask8 k, __m128i a, __m128i b);VPSUBD __m512i _mm512_sub_e pi32(__m512i a, __m512i b);
VPSUBD __m512i _mm512_mask_sub_epi32(__m512i  s, __mmask16 k, __m512i a, __m512i b);
VPSUBD __m512i _mm512_maskz_sub_epi32 ( __mmask16 k, __m512i a, __m512i b);
VPSUBD __m256i _mm256_mask_sub_epi32(__m2 56i s, __mmask8 k, __m256i a, __m256i b);
VPSUBD __m256i _mm256_maskz_sub_epi32 ( __mmask8 k, __m256i a, __m256i b);
VPSUBD __m128i _mm_mask_sub_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBD __m128i _mm_maskz_sub_epi32( __mmask8 k, __m128i a, __m128i b);
PSUBB __m64 _mm_sub_pi8(__m64 m1, __m64 m2)(V)PSUBB __m128i _mm_sub_epi8 ( __m128i a, __m128i b)VPSUBB __m256i _mm256_sub_epi8 ( __m256i a, __m256i b)PSUBW __m64 _mm_sub_pi16(__m64 m1, __m64 m2)(V)PSUBW __m128i _mm_sub_epi1 6 ( __m128i a, __m128i b)
VPSUBW __m256i _mm256_sub_epi16 ( __m256i a, __m256i b)PSUBD __m64 _mm_sub_pi32(__m64 m1, __m64 m2)(V)PSUBD __m128i _mm_sub_epi32 ( __m128i a, __m128i b)VPSUBD __m256i _mm256_sub_e pi32 ( __m256i a, __m256i b)
None.
None.PSUBB/PSUBW/PSUBD—Subt ract Packed IntegersINSTRUCTION SET REFERENCE, M-U
4-480 Vol. 2BOther Exceptions
EVEX-encoded VPSUBD, see Table 2-49, “Type E4 Class Exception Conditions.”
EVEX-encoded VPSUBB/W, see Exceptions Type E4.nb in  Table 2-49, “Type E4 Class Exception Conditions.”PSUBQ—Subtract Packed Quadword IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-481PSUBQ—Subtract Packed Quadword Integers 
Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result 
in the destination operand. When packed quadword oper ands are used, a SIMD subtract is performed. When a 
quadword result is too large to be represented in 64 bits  (overflow), the result is wrapped around and the low 64 
bits are written to the destination element (that is, the carry is ignored).
Note that the (V)PSUBQ instruction can operate on either  unsigned or signed (two’s complement notation) inte-
gers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected 
overflow conditions, software must control the ranges of the values upon which it operates.
Legacy SSE version 64-bit operand: The source operand ca n be a quadword integer stored in an MMX technology 
register or a 64-bit memory location.

register or a 64-bit memory location. 
nation register remain unchanged.Opcode/
Mode 
Feature 
NP 0F FB /r1
PSUBQ mm1, mm2/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V SSE2 Subtract quadword integer in mm1 from mm2 
/m64.
66 0F FB /r
PSUBQ xmm1, xmm2/m128A V/V SSE2 Subtract packed quad word integers in xmm1 
from xmm2 /m128.
VEX.128.66.0F.WIG FB/r
VPSUBQ xmm1, xmm2, xmm3/m128B V/V AVX Subtract packed quadword integers in 
VEX.256.66.0F.WIG FB /r
VPSUBQ ymm1, ymm2, ymm3/m256B V/V AVX2 Subtract packed quadword integers in 
EVEX.128.66.0F.W1 FB /r
VPSUBQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstC V/V AVX512VL
AVX512FSubtract packed quadword integers in 
xmm3/m128/m64bcst from xmm2 and store 
EVEX.256.66.0F.W1 FB /r
VPSUBQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstC V/V AVX512VL
ymm3/m256/m64bcst from ymm2 and store 
EVEX.512.66.0F.W1 FB/r
VPSUBQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512F Subtract packed quadword integers in 
zmm3/m512/m64bcst from zmm2 and store 
in zmm1 using writemask k1.
CF u l l M o d R M : r e g  ( w ) E V E X . v vvv (r) ModRM:r/m (r) N/APSUBQ—Subtract Packed Quadword IntegersINSTRUCTION SET REFERENCE, M-U
4-482 Vol. 2BVEX.128 encoded version: The second source operand is an  XMM register or a 128-bit memory location. The first 
source operand and destination operands  are XMM registers. Bits (MAXVL-1:1 28) of the destination YMM register 
EVEX encoded VPSUBQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32/ 64-bit memory location. The first source operand and 
Operation
PSUBQ (With 64-Bit Operands)
DEST[63:0]  := DEST[63:0] − SRC[63:0];
PSUBQ (With 128-Bit Operands)
DEST[63:0] := DEST[63:0] − SRC[63:0];
DEST[127:64] := DEST[127:64] − SRC[127:64];
VPSUBQ (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0]-SRC2[63:0]DEST[127:64] := SRC1[127:64]-SRC2[127:64]DEST[MAXVL-1:128] := 0
VPSUBQ (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0]-SRC2[63:0]DEST[127:64] := SRC1[127:64]-SRC2[127:64]DEST[191:128] := SRC1[191:128]-SRC2[191:128]DEST[255:192] := SRC1[255:192]-SRC2[255:192]DEST[MAXVL-1:256] := 0
VPSUBQ (EVEX Encoded Versions)
THEN DEST[i+63:i] := SRC1[i+63:i] - SRC2[63:0]ELSE DEST[i+63:i] := SRC1[i+63:i] - SRC2[i+63:i]
FI;
ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PSUBQ—Subtract Packed Quadword IntegersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-483Intel C/C ++ Compiler Intrinsic Equivalents
VPSUBQ __m512i _mm512_sub_epi64(__m512i a, __m512i b);
VPSUBQ __m512i _mm512_mask_sub_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPSUBQ __m512i _mm512_maskz_sub_epi64( __mmask8 k, __m512i a, __m512i b);VPSUBQ __m256i _mm256_mask_sub_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);VPSUBQ __m256i _mm256_maskz_sub_epi64( __mmask8 k, __m256i a, __m256i b);VPSUBQ __m128i _mm_mask_sub_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBQ __m128i _mm_maskz_sub_epi64( __mmask8 k, __m128i a, __m128i b);PSUBQ __m64 _mm_sub_si64(__m64 m1, __m64 m2)(V)PSUBQ __m128i _mm_sub_epi64(__m128i m1, __m128i m2)VPSUBQ __m256i _mm256_sub_epi64(__m256i m1, __m256i m2)
None.
None.
EVEX-encoded VPSUBQ, see Table 2-49, “Type E4 Class Exception Conditions.”PSUBSB/PSUBSW—Subtract Packed Signed Integers With Signed SaturationINSTRUCTION SET REFERENCE, M-U
4-484 Vol. 2BPSUBSB/PSUBSW—Subtract Packed Signed  Integers With Signed Saturation
Opcode/
Mode 
Feature 
NP 0F E8 /r1
PSUBSB mm, mm/m64A V/V MMX Subtract signed packed bytes in mm/m64 from 
signed packed bytes in mm and saturate results.
66 0F E8 /r
PSUBSB xmm1, xmm2/m128A V/V SSE2 Subtract packed signed byte integers in 
xmm2/m128 from packed signed byte integers in 
xmm1 and saturate results.
NP 0F E9 /r1
PSUBSW mm, mm/m64A V/V MMX Subtract signed packed words in mm/m64 from 
signed packed words in mm and saturate results.
66 0F E9 /r
PSUBSW xmm1, xmm2/m128A V/V SSE2 Subtract packed signed word integers in 
xmm2/m128 from packed signed word integers in 
VEX.128.66.0F.WIG E8 /r
VPSUBSB xmm1, xmm2, xmm3/m128B V/V AVX Subtract packed signed byte integers in 
xmm3/m128 from packed signed byte integers in 
xmm2 and saturate results.
VEX.128.66.0F.WIG E9 /r
VPSUBSW xmm1, xmm2, xmm3/m128B V/V AVX Subtract packed signed word integers in 
xmm3/m128 from packed signed word integers in 
VEX.256.66.0F.WIG E8 /r
VPSUBSB ymm1, ymm2, ymm3/m256B V/V AVX2 Subtract packed signed byte integers in 
ymm3/m256 from packed signed byte integers in ymm2 and saturate results.
VEX.256.66.0F.WIG E9 /r
VPSUBSW ymm1, ymm2, ymm3/m256B V/V AVX2 Subtract packed signed word integers in 
ymm3/m256 from packed si gned word integers in 
ymm2 and saturate results.
EVEX.128.66.0F.WIG E8 /r
VPSUBSB xmm1 {k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWSubtract packed signed byte integers in 
xmm2 and saturate resu lts and store in xmm1 
EVEX.256.66.0F.WIG E8 /r
VPSUBSB ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
ymm3/m256 from packed signed byte integers in 
ymm2 and saturate results and store in ymm1 
EVEX.512.66.0F.WIG E8 /r
VPSUBSB zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Subtract packed signed byte integers in 
zmm3/m512 from packed si gned byte integers in 
zmm2 and saturate results and store in zmm1 using 
EVEX.128.66.0F.WIG E9 /r
VPSUBSW xmm1 {k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWSubtract packed signed word integers in 
EVEX.256.66.0F.WIG E9 /r
VPSUBSW ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
EVEX.512.66.0F.WIG E9 /r
VPSUBSW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Subtract packed signed word integers in 
zmm3/m512 from packed si gned word integers in 
writemask k1.PSUBSB/PSUBSW—Subtract Packed Signed Integers With Signed SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-485Instruction Operand Encoding
Performs a SIMD subtract of the packed signed integers of the source operand (second operand) from the packed 
signed integers of the destination operand (first operand) , and stores the packed integer results in the destination 
operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an 
illustration of a SIMD operation. Overflow is handled wi th signed saturation, as described in the following para-
graphs.
The (V)PSUBSB instruction subtracts packed signed byte in tegers. When an individual byte result is beyond the 
range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value of 7FH or 80H, 
respectively, is written to the destination operand.
The (V)PSUBSW instruction subtracts packed signed word integers. When an individual word result is beyond the 
range of a signed word integer (that is, greater than 7F FFH or less than 8000H), the saturated value of 7FFFH or 
8000H, respectively, is written to the destination operand.

graphs.
Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source 
nation register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first 
Operation
PSUBSB (With 64-bit Operands)
DEST[7:0] := SaturateToSignedByte (DEST[7:0] − SRC (7:0]);
(* Repeat subtract operation for 2nd through 7th bytes *)DEST[63:56] := SaturateToSignedByte (DEST[63:56] 
− SRC[63:56] );NOTES:
® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3B.
C Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/APSUBSB/PSUBSW—Subtract Packed Signed Integers With Signed SaturationINSTRUCTION SET REFERENCE, M-U
4-486 Vol. 2BPSUBSW (With 64-bit Operands)
DEST[15:0] := SaturateToSignedWord (DEST[15:0] − SRC[15:0] );
(* Repeat subtract operation for 2nd and 7th words *)DEST[63:48] := SaturateToSignedWord (DEST[63:48] 
− SRC[63:48] );
VPSUBSB (EVEX Encoded Versions) 
i := j * 8;IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateToSign edByte (SRC1[i+7:i] - SRC2[i+7:i])
ELSE 
DEST[i+7:i] := 0;
FI
FI;
VPSUBSW (EVEX Encoded Versions) 
THEN DEST[i+15:i] := SaturateToSign edWord (SRC1[i+15:i] - SRC2[i+15:i])
ELSE 
DEST[i+15:i] := 0;
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0;
VPSUBSB (VEX.256 Encoded Version)
DEST[7:0] := Saturate ToSignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 31th bytes *)DEST[255:248] := SaturateToSignedByte (SRC1[255:248] - SRC2[255:248]);DEST[MAXVL-1:256] := 0;
VPSUBSB (VEX.128 Encoded Version)
(* Repeat subtract operation for 2nd through 14th bytes *)DEST[127:120] := SaturateToSignedByte (SRC1[127:120] - SRC2[127:120]);DEST[MAXVL-1:128] := 0;
PSUBSB (128-bit Legacy SSE Version)
DEST[7:0] := Satura teToSignedByte (DEST[7:0] - SRC[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)DEST[127:120] := SaturateToSignedByte (DEST[127:120] - SRC[127:120]);DEST[MAXVL-1:128 ] (Unmodified);PSUBSB/PSUBSW—Subtract Packed Signed Integers With Signed SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-487VPSUBSW (VEX.256 Encoded Version)
DEST[15:0] := SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);(* Repeat subtract operation for 2nd through 15th words *)DEST[255:240] := SaturateToSignedWord (SRC1[255:240] - SRC2[255:240]);DEST[MAXVL-1:256] := 0;
VPSUBSW (VEX.128 Encoded Version)
DEST[15:0] := SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);(* Repeat subtract operation for 2nd through 7th words *)DEST[127:112] := SaturateToSignedWord (SRC1[127:112] - SRC2[127:112]);DEST[MAXVL-1:128] := 0;
PSUBSW (128-bit Legacy SSE Version) 
DEST[15:0] := SaturateToSignedWord (DEST[15:0] - SRC[15:0]);(* Repeat subtract operation for 2nd through 7th words *)DEST[127:112] := SaturateToSignedWo rd (DEST[127:112] - SRC[127:112]);
DEST[MAXVL-1:128 ] (Unmodified);
VPSUBSB __m512i _mm512_subs_epi8(__m512i a, __m512i b);
VPSUBSB __m512i _mm512_mask_subs_epi8(__m512 i s, __mmask64 k, __m512i a, __m512i b);
VPSUBSB __m512i _mm512_mas kz_subs_epi8( __mmask64 k, __m512i a, __m512i b);
VPSUBSB __m256i _mm256_mask_subs_epi8(__m256 i s, __mmask32 k, __m256i a, __m256i b);
VPSUBSB __m256i _mm256_mas kz_subs_epi8( __mmask32 k, __m256i a, __m256i b);
VPSUBSB __m128i _mm_mask_subs_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);VPSUBSB __m128i _mm_maskz_subs_epi8( __mmask16 k, __m128i a, __m128i b);
VPSUBSW __m512i _mm512_subs_epi16(__m512i a, __m512i b);VPSUBSW __m512i _mm512_mask_subs_epi16(__m5 12i s, __mmask32 k, __m512i a, __m512i b);
VPSUBSW __m512i _mm512_maskz_subs_epi16(  __mmask32 k, __m512i a, __m512i b);
VPSUBSW __m256i _mm256_mask_subs_epi16(__m2 56i s, __mmask16 k, __m256i a, __m256i b);
VPSUBSW __m256i _mm256_maskz_subs_epi16(  __mmask16 k, __m256i a, __m256i b);
VPSUBSW __m128i _mm_mask_subs_epi16(__m128i  s, __mmask8 k, __m128i a, __m128i b);
VPSUBSW __m128i _mm_maskz_subs_epi16(  __mmask8 k, __m128i a, __m128i b);
PSUBSB __m64 _mm_subs_pi8(__m64 m1, __m64 m2)(V)PSUBSB __m128i _mm_subs_e pi8(__m128i m1, __m128i m2)
VPSUBSB __m256i _mm256_subs_epi8(__m256i m1, __m256i m2)PSUBSW __m64 _mm_subs_pi16(__m64 m1, __m64 m2)(V)PSUBSW __m128i _mm_subs_epi16(__m128i m1, __m128i m2)VPSUBSW __m256i _mm256_subs_epi16(__m256i m1, __m256i m2)
None.
None.
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”PSUBUSB/PSUBUSW—Subtract Packed Unsigned  Integers With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-488 Vol. 2BPSUBUSB/PSUBUSW—Subtract Packed Unsigned  Integers With Unsigned Saturation
Opcode/
Mode 
Feature 
NP 0F D8 /r1
PSUBUSB mm, mm/m64A V/V MMX Subtract unsigned packed bytes in mm/m64 
from unsigned packed by tes in mm and saturate 
result.
66 0F D8 /r
PSUBUSB xmm1, xmm2/m128A V/V SSE2 Subtract packed unsigned byte integers in 
xmm2/m128 from packed unsigned byte integers in xmm1 an d saturate result.
NP 0F D9 /r
1
PSUBUSW mm, mm/m64A V/V MMX Subtract unsigned packed words in mm/m64 
from unsigned packed wo rds in mm and saturate 
result.
66 0F D9 /r
PSUBUSW xmm1, xmm2/m128A V/V SSE2 Subtract packed unsigned word integers in 
xmm2/m128 from packed unsigned word 
integers in xmm1 an d saturate result.
VEX.128.66.0F.WIG D8 /r
VPSUBUSB xmm1, xmm2, xmm3/m128B V/V AVX Subtract packed unsigned byte integers in 
xmm3/m128 from packed unsigned byte 
integers in xmm2 an d saturate result.
VEX.128.66.0F.WIG D9 /r
VPSUBUSW xmm1, xmm2, xmm3/m128B V/V AVX Subtract packed unsigned word integers in 
xmm3/m128 from packed unsigned word integers in xmm2 an d saturate result.
VEX.256.66.0F.WIG D8 /r
VPSUBUSB ymm1, ymm2, ymm3/m256B V/V AVX2 Subtract packed unsigned byte integers in 
ymm3/m256 from pack ed unsigned byte 
integers in ymm2 and saturate result.
VEX.256.66.0F.WIG D9 /r
VPSUBUSW ymm1, ymm2, ymm3/m256B V/V AVX2 Subtract packed unsigned word integers in 
ymm3/m256 from pack ed unsigned word 
EVEX.128.66.0F.WIG D8 /r
VPSUBUSB xmm1 {k1}{z }, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWSubtract packed unsigned byte integers in 
xmm3/m128 from packed unsigned byte integers in xmm2, satura te results and store in 
EVEX.256.66.0F.WIG D8 /r
VPSUBUSB ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
integers in ymm2, satura te results and store in 
ymm1 using writemask k1.
EVEX.512.66.0F.WIG D8 /r
VPSUBUSB zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Subtract packed unsigned byte integers in 
zmm3/m512 from packed unsigned byte integers in zmm2, satura te results and store in 
EVEX.128.66.0F.WIG D9 /r
VPSUBUSW xmm1 {k1}{z }, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWSubtract packed unsigned word integers in

AVX512BWSubtract packed unsigned word integers in 
xmm3/m128 from packed unsigned word integers in xmm2 and sa turate results and store 
EVEX.256.66.0F.WIG D9 /r
VPSUBUSW ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
EVEX.512.66.0F.WIG D9 /r
VPSUBUSW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Subtract packed unsigned word integers in 
zmm3/m512 from packed unsigned word integers in zmm2, satura te results and store in 
zmm1 using writemask k1.PSUBUSB/PSUBUSW—Subtract Packed Unsigned  Integers With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-489Instruction Operand Encoding
Performs a SIMD subtract of the packed unsigned intege rs of the source operand (second operand) from the 
packed unsigned integers of the destination operand (fir st operand), and stores the packed unsigned integer 
results in the destination operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, for an illustration of a SIMD operatio n. Overflow is handled with unsigned saturation, as 
described in the following paragraphs.
These instructions can operate on either 64-bit or 128-bit operands.
The (V)PSUBUSB instruction subtracts packed unsigned byte integers. When an individual byte result is less than 
zero, the saturated value of 00H is written to the destination operand.
The (V)PSUBUSW instruction subtracts packed unsigned word integers. When an individual word result is less than 
zero, the saturated value of 0000H is  written to the destination operand.
operand can be either an MMX technology register or a 64-bit memory location. 
Operation
PSUBUSB (With 64-bit Operands)
DEST[7:0] := SaturateToUn signedByte (DEST[7:0] − SRC (7:0] );
(* Repeat add operation for 2nd through 7th bytes *)DEST[63:56] := SaturateToUnsignedByte (DEST[63:56] 
− SRC[63:56]; 
PSUBUSW (With 64-bit Operands)
DEST[15:0] := SaturateToUnsignedWord (DEST[15:0] − SRC[15:0] );
(* Repeat add operation for 2nd and 3rd words *)DEST[63:48] := SaturateToUnsignedWord (DEST[63:48] 
− SRC[63:48] );NOTES:
CF u l l  M e mM o d R M : r e g  ( w ) E V E X.vvvv (r) ModRM:r/m (r) N/APSUBUSB/PSUBUSW—Subtract Packed Unsigned  Integers With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
4-490 Vol. 2BVPSUBUSB (EVEX Encoded Versions) 
THEN DEST[i+7:i] := SaturateToUnsign edByte (SRC1[i+7:i] - SRC2[i+7:i])
ELSE 
FI
FI;
VPSUBUSW (EVEX Encoded Versions) 
i := j * 16;IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateToUnsignedWord (SRC1[i+15:i] - SRC2[i+15:i])ELSE 
FI
FI;
VPSUBUSB (VEX.256 Encoded Version)
DEST[7:0] := SaturateToUnsigned Byte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 31st bytes *)DEST[255:148] := SaturateToUnsignedByte (SRC1[255:248] - SRC2[255:248]);DEST[MAXVL-1:256] := 0;
VPSUBUSB (VEX.128 Encoded Version)
(* Repeat subtract operation for 2nd through 14th bytes *)DEST[127:120] := SaturateToUnsignedByte (SRC1[127:120] - SRC2[127:120]);DEST[MAXVL-1:128] := 0
PSUBU
SB (128-bit Legacy SSE Version)
DEST[7:0] := SaturateToUnsigned Byte (DEST[7:0] - SRC[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)DEST[127:120] := SaturateToUnsignedByte (DEST[127:120] - SRC[127:120]);DEST[MAXVL-1:128] (Unmodified)PSUBUSB/PSUBUSW—Subtract Packed Unsigned  Integers With Unsigned SaturationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-491VPSUBUSW (VEX.256 Encoded Version)
DEST[15:0] := SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);(* Repeat subtract operation for 2nd through 15th words *)DEST[255:240] := SaturateToUnsignedWord (SRC1[255:240] - SRC2[255:240]);DEST[MAXVL-1:256] := 0;
VPSUBUSW (VEX.128 Encoded Version)
DEST[15:0] := SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);(* Repeat subtract operation for 2nd through 7th words *)DEST[127:112] := SaturateToUnsignedWord (SRC1[127:112] - SRC2[127:112]);DEST[MAXVL-1:128] := 0
PSUBUSW (128-bit Legacy SSE Version)
DEST[15:0] := SaturateToUnsigned Word (DEST[15:0] - SRC[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)DEST[127:112] := SaturateToUnsignedWord (DEST[127:112] - SRC[127:112]);DEST[MAXVL-1:128 ] (Unmodified)
VPSUBUSB __m512i _mm512_subs_epu8(__m512i a, __m512i b);
VPSUBUSB __m512i _mm512_mask_subs_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);VPSUBUSB __m512i _mm512_maskz_subs_epu8( __mmask64 k, __m512i a, __m512i b);VPSUBUSB __m256i _mm256_mask_subs_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);VPSUBUSB __m256i _mm256_maskz_subs_epu8( __mmask32 k, __m256i a, __m256i b);VPSUBUSB __m128i _mm_mask_subs_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);VPSUBUSB __m128i _mm_maskz_subs_epu8( __mmask16 k, __m128i a, __m128i b);
VPSUBUSW __m512i _mm512_subs_epu16(__m512i a, __m512i b);VPSUBUSW __m512i _mm512_mask_subs_epu16(__m512 i s, __mmask32 k, __m512i a, __m512i b);
VPSUBUSW __m512i _mm512_maskz_subs_epu16( __mmask32 k, __m512i a, __m512i b);
VPSUBUSW __m256i _mm256_mask_subs_epu16(__m256 i s, __mmask16 k, __m256i a, __m256i b);
VPSUBUSW __m256i _mm256_maskz_subs_epu16( __mmask16 k, __m256i a, __m256i b);
VPSUBUSW __m128i _mm_mask_subs_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);VPSUBUSW __m128i _mm_maskz_subs_epu16( __mmask8 k, __m128i a, __m128i b);
PSUBUSB __m64 _mm_subs_pu8(__m64 m1, __m64 m2)(V)PSUBUSB __m128i _mm_subs_epu8(__m128i m1, __m128i m2)VPSUBUSB __m256i _mm256_subs_epu8(__m256i m1, __m256i m2)PSUBUSW __m64 _mm_subs_pu16(__m64 m1, __m64 m2)(V)PSUBUSW __m128i _mm_subs_e pu16(__m128i m1, __m128i m2)
VPSUBUSW __m256i _mm256_subs_epu16(__m256i m1, __m256i m2)
None.
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”PTEST—Logical CompareINSTRUCTION SET REFERENCE, M-U
4-492 Vol. 2BPTEST—Logical Compare
PTEST and VPTEST set the ZF flag if all bits in the result are 0 of the bitwise AND of th e first source operand (first 
operand) and the second source operand (second operand). VPTE ST sets the CF flag if all bits in the result are 0 of 
the bitwise AND of the second source operand (second op erand) and the logical NOT of the destination operand.
The first source register is specified by the ModR/M reg field.
128-bit versions: The first source register is an XMM regist er. The second source register can be an XMM register or 
a 128-bit memory location. The dest ination register is not modified.

None.
None.
VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM 
register or a 256-bit memory location. The destination register is not modified.
Operation
(V)PTEST (128-bit Version)
IF (SRC[127:0] BITWISE AND DEST[127:0] = 0) 
THEN ZF := 1;ELSE ZF := 0;
IF (SRC[127:0] BITWISE AN D NOT DEST[127:0] = 0) 
THEN CF := 1;ELSE CF := 0;
DEST (unmodified)AF := OF := PF := SF := 0;
VPTEST (VEX.256 Encoded Version)
IF (SRC[255:0] BITWIS E AND DEST[255:0] = 0) THEN ZF := 1;
ELSE ZF := 0;
IF (SRC[255:0] BITWISE AND NOT DEST[255:0] = 0) THEN CF := 1;
DEST (unmodified)AF := OF := PF := SF := 0;Opcode/
Mode 
Feature 
66 0F 38 17 /r
PTEST xmm1, xmm2/m128RM V/V SSE4_1 Set ZF if xmm2/m128 AND xmm1 result is all 
0s. Set CF if xmm2/m128 AND NOT xmm1 
result is all 0s.
VEX.128.66.0F38.WIG 17 /r
VPTEST xmm1, xmm2/m128RM V/V AVX Set ZF and CF depending on bitwise AND and 
ANDN of sources.
VEX.256.66.0F38.WIG 17 /r
VPTEST ymm1, ymm2/m256RM V/V AVX Set ZF and CF depending on bitwise AND and 
RM ModRM:reg (r) ModRM:r/m (r) N/A N/APTEST—Logical CompareINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-493Intel C/C++ Compiler Intrinsic Equivalent
PTEST int _mm_testz_si128 (__m128i s1, __m128i s2);
PTEST int _mm_testc_si128 (__m128i s1, __m128i s2);PTEST int _mm_testnzc_si128 (__m128i s1, __m128i s2);VPTEST int _mm256_testz_si256 (__m256i s1, __m256i s2);VPTEST int _mm256_testc_si256 (__m256i s1, __m256i s2);VPTEST int _mm256_testnzc_si2 56 (__m256i s1, __m256i s2);
VPTEST int _mm_testz_si128 (__m128i s1, __m128i s2);VPTEST int _mm_testc_si12 8 (__m128i s1, __m128i s2);
VPTEST int _mm_testnzc_si128 (__m128i s1, __m128i s2);
The OF, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.
None.
#UD If VEX.vvvv ≠ 1111B.PTWRITE—Write Data to a Processor Trace PacketINSTRUCTION SET REFERENCE, M-U
4-494 Vol. 2BPTWRITE—Write Data to a Processor Trace Packet
This instruction reads data in the source operand and send s it to the Intel Processor Trace hardware to be encoded 
in a PTW packet if TriggerEn, ContextE n, FilterEn, and PTWEn are all set to 1. For more details on these values, see 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, Section 33.2.2, “Software Trace 
Instrumentation with PTWRITE.” The size of data is 64-bit  if using REX.W in 64-bit mode, otherwise 32-bits of data 
are copied from the source operand.
Note: The instruction will #UD if prefix 66H is used.
Operation
IF (IA32_RTIT_STATUS.TriggerEn & IA32_RTIT_STATUS.ContextEn  & IA32_RTIT_STATUS.FilterEn & IA32_RTIT_CTL.PTWEn) = 1
PTW.PayloadBytes := Encoded payload size;
PTW.IP := IA32_R TIT_CTL.FUPonPTW 
IF IA32_RTIT_CTL.FUPonPTW = 1
Insert FUP packet wi th IP of PTWRITE;
FI;
FI;
None.
#UD If CPUID.(EAX=14H, ECX=0H ):EBX.PTWRITE [Bit 4] = 0.
If LOCK prefix is used.If 66H prefix is used.Opcode/
Mode 
Feature 
F3 REX.W 0F AE /4
PTWRITE r64/m64RM V/N.E PTWRITE Reads the data from r64/m64 to encode into a PTW 
packet if dependencies are met (see details below).
F3 0F AE /4
PTWRITE r32/m32RM V/V PTWRITE Reads the data from r32/m32 to encode into a PTW 
RM ModRM:rm (r) N/A N/A N/APTWRITE—Write Data to a Processor Trace PacketINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-495Real-Address Mode Exceptions
If 66H prefix is used.
If 66H prefix is used.PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
4-496 Vol. 2BPUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/ PUNPCKHQDQ— Unpack High Data
Opcode/
Mode 
Feature 
NP 0F 68 /r1
PUNPCKHBW mm, mm/m64A V/V MMX Unpack and interleave high-order bytes from 
mm and mm/m64 into mm.
66 0F 68 /r
PUNPCKHBW xmm1, xmm2/m128A V/V SSE2 Unpack and interleave high-order bytes from 
xmm1 and xmm2/m128 into xmm1.
NP 0F 69 /r1
PUNPCKHWD mm, mm/m64A V/V MMX Unpack and interleave high-order words from 
66 0F 69 /r
PUNPCKHWD xmm1, xmm2/m128A V/V SSE2 Unpack and interleave high-order words from 
NP 0F 6A /r1
PUNPCKHDQ mm, mm/m64A V/V MMX Unpack and interleave high-order 
doublewords from mm and mm/m64 into mm.
66 0F 6A /r
PUNPCKHDQ xmm1, xmm2/m128A V/V SSE2 Unpack and interleave high-order 
doublewords from xmm1 and xmm2/m128 
into xmm1.
66 0F 6D /r
PUNPCKHQDQ xmm1, xmm2/m128A V/V SSE2 Unpack and interleave high-order quadwords 
from xmm1 and xmm2/m128 into xmm1.
VEX.128.66.0F.WIG 68/r
VPUNPCKHBW xmm1,xmm2, xmm3/m128B V/V AVX Interleave high-order bytes from xmm2 and 
xmm3/m128 into xmm1.
VEX.128.66.0F.WIG 69/r
VPUNPCKHWD xmm1,xmm2, xmm3/m128B V/V AVX Interleave high-order words from xmm2 and 
VEX.128.66.0F.WIG 6A/r
VPUNPCKHDQ xmm1, xmm2, xmm3/m128B V/V AVX Interleave high-order doublewords from 
xmm2 and xmm3/m128 into xmm1.
VEX.128.66.0F.WIG 6D/r
VPUNPCKHQDQ xmm1, xmm2, xmm3/m128B V/V AVX Interleave high-order quadword from xmm2 
and xmm3/m128 into xmm1 register.
VEX.256.66.0F.WIG 68 /r
VPUNPCKHBW ymm1, ymm2, ymm3/m256B V/V AVX2 Interleave high-order bytes from ymm2 and 
ymm3/m256 into ymm1 register.
VEX.256.66.0F.WIG 69 /r
VPUNPCKHWD ymm1, ymm2, ymm3/m256B V/V AVX2 Interleave high-ord er words from  ymm2 and 
VEX.256.66.0F.WIG 6A /r
VPUNPCKHDQ ymm1, ymm2, ymm3/m256B V/V AVX2 Interleave high-o rder doublewords from 
ymm2 and ymm3/m256 in to ymm1 register.
VEX.256.66.0F.WIG 6D /r
VPUNPCKHQDQ ymm1, ymm2, ymm3/m256B V/V AVX2 Interleave high-ord er quadword from ymm2 
and ymm3/m256 into ymm1 register.
EVEX.128.66.0F.WIG 68 /r
VPUNPCKHBW xmm1 {k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWInterleave high-order bytes from xmm2 and 
xmm3/m128 into xmm1 register using k1 write mask.
EVEX.128.66.0F.WIG 69 /r
VPUNPCKHWD xmm1 {k1 }{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWInterleave high-order words from xmm2 and 
EVEX.128.66.0F.W0 6A /r
VPUNPCKHDQ xmm1 {k1}{z}, xmm2, 
AVX512FInterleave high-order  doublewords from 
xmm2 and xmm3/m128/m32bcst into xmm1 
register using k1 write mask.
EVEX.128.66.0F.W1 6D /r
VPUNPCKHQDQ xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcstDV / V A V X 5 1 2 V L
AVX512FInterleave high-order quadword from xmm2 
and xmm3/m128/m64bcst into xmm1 
register using k1 write mask.PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-497Instruction Operand Encoding
Unpacks and interleaves the high-order data elements (byt es, words, doublewords, or quadwords) of the destina-
tion operand (first operand) and source operand (second operand) into the destination operand. Figure 4-20 shows 
the unpack operation for bytes in 64-bit operands. The low-order data elements are ignored. EVEX.256.66.0F.WIG 68 /r
VPUNPCKHBW ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWInterleave high-order bytes from ymm2 and 
ymm3/m256 into ymm1 register using k1

ymm3/m256 into ymm1 register using k1 
write mask.
EVEX.256.66.0F.WIG 69 /r
VPUNPCKHWD ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWInterleave high-order words from ymm2 and 
ymm3/m256 into ymm1 register using k1 write mask.
EVEX.256.66.0F.W0 6A /r
VPUNPCKHDQ ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcstDV / V A V X 5 1 2 V L
ymm2 and ymm3/m256/m32bcst into ymm1 
EVEX.256.66.0F.W1 6D /r
VPUNPCKHQDQ ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcstDV / V A V X 5 1 2 V L
AVX512FInterleave high-order quadword from ymm2 
and ymm3/m256/m64bcst into ymm1 
EVEX.512.66.0F.WIG 68/r
VPUNPCKHBW zmm1 {k1 }{z}, zmm2, zmm3/m512C V/V AVX512BW Interleave high-o rder bytes from zmm2 and 
zmm3/m512 into zmm1 register.
EVEX.512.66.0F.WIG 69/r
VPUNPCKHWD zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Interleave high-o rder words from zmm2 and 
EVEX.512.66.0F.W0 6A /r
VPUNPCKHDQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstD V/V AVX512F Interleave high-order doublewords from 
zmm2 and zmm3/m512/m32bcst into zmm1 
EVEX.512.66.0F.W1 6D /r
VPUNPCKHQDQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstD V/V AVX512F Interleave high-order quadword from zmm2 
and zmm3/m512/m64bcst into zmm1 register using k1 write mask.
NOTES:
1.  See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
Mode 
Feature 
FlagDescriptionPUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
4-498 Vol. 2BFigure 4-21.  256-bit VPUNPCKHDQ Instruction Operation
When the source data comes from a 64-bit memory operand,  the full 64-bit operand is accessed from memory, but 
the instruction uses only the high-order 32 bits. When th e source data comes from a 128-bit memory operand, an 
implementation may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.
The (V)PUNPCKHBW instruction interleaves the high-order  bytes of the source and destination operands, the 
(V)PUNPCKHWD instruction interleaves the high-order word s of the source and destination operands, the (V)PUNP-
CKHDQ instruction interleaves the high-order doubleword (or doublewords) of the source and destination oper-
ands, and the (V)PUNPCKHQDQ instructio n interleaves the high-order quadwo rds of the source and destination 
operands.
These instructions can be used to convert bytes to word s, words to doublewords, doublewords to quadwords, and 
quadwords to double quadwords, respectively, by placing al l 0s in the source operand. Here, if the source operand 
contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data 
elements from the original value in the destination operand. For example, with the (V)PUNPCKHBW instruction the 
high-order bytes are zero extended (that is, unpacked in to unsigned word integers),  and with the (V)PUNPCKHWD 
instruction, the high-order words are zero extend ed (unpacked into unsigned doubleword integers).
Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory 
128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The first 
VEX.128 encoded versions: The second source operand is an  XMM register or a 128-bit memory location. The first 
VEX.256 encoded version: The second source operand is an  YMM register or an 256-bit memory location. The first 
source operand and destination operands are YMM registers. Figure 4-20.  PUNPCKHBW Instructio n Operation Using 64-bit OperandsX4 X7 X6 X5 Y4 Y7 Y6 Y5X0 X3 X2 X1 Y0 Y3 Y2 Y1 X4 X7 X6 X5 Y4 Y7 Y6 Y5 SRC DEST
DEST
X2 X7 X6 X3 Y2 Y7 Y6 Y3X0 X3 X2 X1 Y0 Y3 Y2 Y1 X4 X7 X6 X5 Y4 Y7 Y6 Y5 SRC
DEST0 255 31
00 255
25531PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-499EVEX encoded VPUNPCKHDQ/QDQ: The second source op erand is a ZMM/YMM/XMM register, a 512/256/128-bit 
memory location or a 512/256/128-bit vector broadcaste d from a 32/64-bit memory location. The first source 
operand and destination operands are ZMM/YMM/XMM regist ers. The destination is co nditionally updated with 
EVEX encoded VPUNPCKHWD/BW: The second source op erand is a ZMM/YMM/XMM register, a 512/256/128-bit 
memory location. The first source operand and destinatio n operands are ZMM/YMM/XMM registers. The destination 
is conditionally updated with writemask k1.
Operation
PUNPCKHBW Instruction With 64-bit Operands:
DEST[7:0] := DEST[39:32];DEST[15:8] := SRC[39:32];DEST[23:16] := DEST[47:40];DEST[31:24] := SRC[47:40];DEST[39:32] := DEST[55:48];
DEST[47:40] := SRC[55:48];
DEST[55:48] := DEST[63:56];DEST[63:56] := SRC[63:56];
PUNPCKHW Instruction With 64-bit Operands:
DEST[15:0] := DEST[47:32]; DEST[31:16] := SRC[47:32];DEST[47:32] := DEST[63:48];DEST[63:48] := SRC[63:48];
PUNPCKHDQ Instruction With 64-bit Operands:
DEST[31:0] := DEST[63:32];DEST[63:32] := SRC[63:32];
INTERLEAVE_HIGH_BYTES_512b (SRC1, SRC2)
TMP_DEST[255:0] := INTE RLEAVE_HIGH_BYTES_256b(SR C1[255:0], SRC[255:0])
TMP_DEST[511:256] := INTERLEAVE_HIGH_BYTES_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_HIGH_BYTES_256b (SRC1, SRC2) 
DEST[7:0] := SRC1[71:64]DEST[15:8] := SRC2[71:64]DEST[23:16] := SRC1[79:72]DEST[31:24] := SRC2[79:72]DEST[39:32] := SRC1[87:80]DEST[47:40] := SRC2[87:80]DEST[55:48] := SRC1[95:88]DEST[63:56] := SRC2[95:88]DEST[71:64] := SRC1[103:96]DEST[79:72] := SRC2[103:96]DEST[87:80] := SRC1[111:104]DEST[95:88] := SRC2[111:104]DEST[103:96] := SRC1[119:112]DEST[111:104] := SRC2[119:112]DEST[119:112] := SRC1[127:120]DEST[127:120] := SRC2[127:120]DEST[135:128] := SRC1[199:192]DEST[143:136] := SRC2[199:192]DEST[151:144] := SRC1[207:200]DEST[159:152] := SRC2[207:200]PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
4-500 Vol. 2BDEST[167:160] := SRC1[215:208]
DEST[175:168] := SRC2[215:208]DEST[183:176] := SRC1[223:216]DEST[191:184] := SRC2[223:216]DEST[199:192] := SRC1[231:224]DEST[207:200] := SRC2[231:224]DEST[215:208] := SRC1[239:232]DEST[223:216] := SRC2[239:232]DEST[231:224] := SRC1[247:240]DEST[239:232] := SRC2[247:240]DEST[247:240] := SRC1[255:248]DEST[255:248] := SRC2[255:248]
INTERLEAVE_HIGH_BY TES (SRC1, SRC2) 
DEST[7:0] := SRC1[71:64]DEST[15:8] := SRC2[71:64]DEST[23:16] := SRC1[79:72]DEST[31:24] := SRC2[79:72]DEST[39:32] := SRC1[87:80]DEST[47:40] := SRC2[87:80]DEST[55:48] := SRC1[95:88]DEST[63:56] := SRC2[95:88]DEST[71:64] := SRC1[103:96]DEST[79:72] := SRC2[103:96]DEST[87:80] := SRC1[111:104]DEST[95:88] := SRC2[111:104]DEST[103:96] := SRC1[119:112]DEST[111:104] := SRC2[119:112]DEST[119:112] := SRC1[127:120]DEST[127:120] := SRC2[127:120]
INTERLEAVE_HIGH_WORDS_ 512b (SRC1, SRC2)
TMP_DEST[255:0] := INTE RLEAVE_HIGH_WORDS_256b(S RC1[255:0], SRC[255:0])
TMP_DEST[511:256] := INTERLEAVE_HIGH_WO RDS_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_HIGH_WORD S_256b(SRC1, SRC2)
DEST[15:0] := SRC1[79:64]DEST[31:16] := SRC2[79:64]DEST[47:32] := SRC1[95:80]DEST[63:48] := SRC2[95:80]DEST[79:64] := SRC1[111:96]DEST[95:80] := SRC2[111:96]DEST[111:96] := SRC1[127:112]DEST[127:112] := SRC2[127:112]DEST[143:128] := SRC1[207:192]DEST[159:144] := SRC2[207:192]DEST[175:160] := SRC1[223:208]DEST[191:176] := SRC2[223:208]DEST[207:192] := SRC1[239:224]DEST[223:208] := SRC2[239:224]DEST[239:224] := SRC1[255:240]DEST[255:240] := SRC2[255:240]
INTERLEAVE_HIGH_WORDS (SRC1, SRC2)PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-501DEST[15:0] := SRC1[79:64]
DEST[31:16] := SRC2[79:64]DEST[47:32] := SRC1[95:80]DEST[63:48] := SRC2[95:80]DEST[79:64] := SRC1[111:96]DEST[95:80] := SRC2[111:96]DEST[111:96] := SRC1[127:112]DEST[127:112] := SRC2[127:112]
INTERLEAVE_HIGH_DWORDS _512b (SRC1, SRC2)
TMP_DEST[255:0] := INTERLEAVE_HIGH_DW ORDS_256b(SRC1[255 :0], SRC2[255:0])

TMP_DEST[511:256] := INTERLEAVE_HIGH_DW ORDS_256b(SRC1[511:256], SRC2[511:256])
INTERLEAVE_HIGH_DWOR DS_256b(SRC1, SRC2)
DEST[31:0] := SRC1[95:64]DEST[63:32] := SRC2[95:64]DEST[95:64] := SRC1[127:96]DEST[127:96] := SRC2[127:96]DEST[159:128] := SRC1[223:192]DEST[191:160] := SRC2[223:192]DEST[223:192] := SRC1[255:224]DEST[255:224] := SRC2[255:224]
INTERLEAVE_HIGH_DW ORDS(SRC1, SRC2)
DEST[31:0] := SRC1[95:64]DEST[63:32] := SRC2[95:64]DEST[95:64] := SRC1[127:96]DEST[127:96] := SRC2[127:96]
INTERLEAVE_HIGH_QWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] := INTE RLEAVE_HIGH_QWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] := INTERL EAVE_HIGH_QWORDS_256b(SRC1 [511:256], SRC2[511:256])
INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)
DEST[63:0] := SRC1[127:64]DEST[127:64] := SRC2[127:64]DEST[191:128] := SRC1[255:192]DEST[255:192] := SRC2[255:192]
INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)
DEST[63:0] := SRC1[127:64]DEST[127:64] := SRC2[127:64]
PUNPCKHBW (128-bit Legacy SSE Version)
DEST[127:0] := INTERLEA VE_HIGH_BYTES(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKHBW (VEX.128 Encoded Version)
DEST[127:0] := INTERLEAVE_HIGH_BYTES(SRC1, SRC2)DEST[MAXVL-1:127] := 0
VPUNPCKHBW (VEX.256 Encoded Version)
DEST[255:0] := INTERLEAVE_HIGH_BYTES_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
4-502 Vol. 2BVPUNPCKHBW (EVEX Encoded Versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)IF VL = 128
TMP_DEST[VL-1:0] := INTERLEAVE_HIG H_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
FI
FI;
PUNPCKHWD (128-bit Legacy SSE Version)
DEST[127:0] := INTERLEAVE_HIGH_WORDS(DEST, SRC)DEST[255:127] (Unmodified)
VPUNPCKHWD (VEX.128 Encoded Version)
DEST[127:0] := INTERLEAVE_HIGH_WORDS(SRC1, SRC2)DEST[MAXVL-1:127] := 0
VPUNPCKHWD (VEX.256 Encoded Version)
DEST[255:0] := INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0
VPUNPCKHWD (EVEX Encoded Versions)
TMP_DEST[VL-1:0] := INTERLEAVE_HIG H_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
i := j * 16IF k1[j] OR *no writemask*PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-503THEN DEST[i+15:i] := TMP_DEST[i+15:i]
ELSE 
FI
FI;
PUNPCKHDQ (128-bit Legacy SSE Version)
DEST[127:0] := INTERLEAVE _HIGH_DWORDS(DEST, SRC)
VPUNPCKHDQ (VEX.128 Encoded Version)
DEST[127:0] := INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)DEST[MAXVL-1:127] := 0
VPUNPCKHDQ (VEX.256 Encoded Version)
DEST[255:0] := INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0
VPUNPCKHDQ (EVEX.512 Encoded Version)
i := j * 32IF (EVEX.b = 1) AN D (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] := SRC2[31:0]ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]
FI;
ENDFOR;IF VL = 128
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_DW ORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_DWOR DS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_DWOR DS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FI
FI;
ENDFORPUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
4-504 Vol. 2BDEST[MAXVL-1:VL] := 0
PUNPCKHQDQ (128-bit Legacy SSE Version)
DEST[127:0] := INTERLEAVE_HIGH_QWORDS(DEST, SRC)DEST[MAXVL-1:128] (Unmodified)
VPUNPCKHQDQ (VEX.128 Encoded Version)
DEST[127:0] := INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)DEST[MAXVL-1:128] := 0
VPUNPCKHQDQ (VEX.256 Encoded Version)
DEST[255:0] := INTERLEAVE_H IGH_QWORDS_256b(SRC1, SRC2)
VPUNPCKHQDQ (EVEX Encoded Versions)
i := j * 64IF (EVEX.b = 1) AN D (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] := SRC2[63:0]ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i]
FI;
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_QW ORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_QWOR DS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_QWOR DS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FI
FI;
VPUNPCKHBW __m512i _mm512_unpackhi_epi8(__m512i a, __m512i b);
VPUNPCKHBW __m512i _mm512_mask_unpackhi_epi8(__ m512i s, __mmask64 k, __m512i a, __m512i b);
VPUNPCKHBW __m512i _mm512_maskz_unpackhi_ epi8( __mmask64 k, __m512i a, __m512i b);
VPUNPCKHBW __m256i _mm256_mask_unpackhi_epi8(__ m256i s, __mmask32 k, __m256i a, __m256i b);
VPUNPCKHBW __m256i _mm256_maskz_unpackhi_ epi8( __mmask32 k, __m256i a, __m256i b);PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-505VPUNPCKHBW __m128i _mm_mask_unpackhi_epi8(v  s, __mmask16 k, __ m128i a, __m128i b);
VPUNPCKHBW __m128i _mm_mask z_unpackhi_epi8( __mmask16 k, __m128i a, __m128i b);
VPUNPCKHWD __m512i _mm512_unpackhi_epi16(__m512i a, __m512i b);VPUNPCKHWD __m512i _mm512_mask_unpackhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPUNPCKHWD __m512i _mm512_maskz_unpackhi_epi16( __mmask32 k, __m512i a, __m512i b);VPUNPCKHWD __m256i _mm256_mask_unpackhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPUNPCKHWD __m256i _mm256_maskz_unpackhi_epi16( __mmask16 k, __m256i a, __m256i b);VPUNPCKHWD __m128i _mm_mask_unpackhi_epi16( v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKHWD __m128i _mm_maskz_unpackhi_epi 16( __mmask8 k, __m128i a, __m128i b);
VPUNPCKHDQ __m512i _mm512_unpackh i_epi32(__m512i a, __m512i b);
VPUNPCKHDQ __m512i _mm512_mask_unpackhi_epi32(__ m512i s, __mmask16 k, __m512i a, __m512i b);
VPUNPCKHDQ __m512i _mm512_maskz_unpackhi_epi32( __mmask16 k, __m512i a, __m512i b);VPUNPCKHDQ __m256i _mm256_mask_unpackhi_epi32(__ m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m256i _mm256_maskz_unpackhi_ep i32( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m128i _mm_mask_unpackhi_epi32(__m 512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m128i _mm_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);VPUNPCKHQDQ __m512i _mm512_unpackhi_epi64(__m512i a, __m512i b);VPUNPCKHQDQ __m512i _mm512_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPUNPCKHQDQ __m512i _mm512_maskz_unpackhi_e pi64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m256i _mm256_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPUNPCKHQDQ __m256i _mm256_maskz_unpackhi_e pi64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m128i _mm_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPUNPCKHQDQ __m128i _mm_maskz_unpackhi_epi 64( __mmask8 k, __m512i a, __m512i b);
PUNPCKHBW __m64 _mm_unpackhi _pi8(__m64 m1, __m64 m2)
(V)PUNPCKHBW __m128i _mm_unpack hi_epi8(__m128i m1, __m128i m2)
VPUNPCKHBW __m256i _mm256_unpackhi_epi8(__m256i m1, __m256i m2)PUNPCKHWD __m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)(V)PUNPCKHWD __m128i _mm_unpack hi_epi16(__m128i m1,__m128i m2)
VPUNPCKHWD __m256i _mm256_unpackhi_epi16(__m256i m1,__m256i m2)PUNPCKHDQ __m64 _mm_unpack hi_pi32(__m64 m1, __m64 m2)
(V)PUNPCKHDQ __m128i _mm_unpackhi _epi32(__m128i m1, __m128i m2)
VPUNPCKHDQ __m256i _mm256_unpackhi_epi32(__m256i m1, __m256i m2)(V)PUNPCKHQDQ __m128i _mm_unpackhi_epi64 ( __m128i a, __m128i b)VPUNPCKHQDQ __m256i _mm256_unpackhi_epi64 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded VPUNPCKHQDQ/QDQ, see Table 2-5 0, “Type E4NF Class Exception Conditions.”
EVEX-encoded VPUNPCKHBW/WD, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Condi-
tions.”PUNPCKLBW/PUNPCKLWD/PUNPCKLD Q/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U

None.
None.
4-506 Vol. 2BPUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/ PUNPCKLQDQ—Unpack Low Data
Opcode/
Mode 
Feature 
NP 0F 60 /r1
PUNPCKLBW mm, mm/m32A V/V MMX Interleave low-order bytes from mm and 
mm/m32 into mm.
66 0F 60 /r
PUNPCKLBW xmm1, xmm2/m128A V/V SSE2 Interleave low-order bytes from xmm1 and 
xmm2/m128 into xmm1.
NP 0F 61 /r1
PUNPCKLWD mm, mm/m32A V/V MMX Interleave low-order words from mm and 
66 0F 61 /r
PUNPCKLWD xmm1, xmm2/m128A V/V SSE2 Interleave low-order words from xmm1 and 
NP 0F 62 /r1
PUNPCKLDQ mm, mm/m32A V/V MMX Interleave low-order doublewords from mm 
and mm/m32 into mm.
66 0F 62 /r
PUNPCKLDQ xmm1, xmm2/m128A V/V SSE2 Interleave low-order doublewords from xmm1 
and xmm2/m128 into xmm1.
66 0F 6C /r
PUNPCKLQDQ xmm1, xmm2/m128A V/V SSE2 Interleave low-order quadword from xmm1 
and xmm2/m128 into xmm1 register.
VEX.128.66.0F.WIG 60/r
VPUNPCKLBW xmm1,xmm2, xmm3/m128B V/V AVX Interleave low-order bytes from xmm2 and 
VEX.128.66.0F.WIG 61/r
VPUNPCKLWD xmm1,xmm2, xmm3/m128B V/V AVX Interleave low-order words from xmm2 and 
VEX.128.66.0F.WIG 62/r
VPUNPCKLDQ xmm1, xmm2, xmm3/m128B V/V AVX Interleave low-order doublewords from xmm2 
and xmm3/m128 into xmm1.
VEX.128.66.0F.WIG 6C/r
VPUNPCKLQDQ xmm1, xmm2, xmm3/m128B V/V AVX Interleave low-order quadword from xmm2 
VEX.256.66.0F.WIG 60 /r
VPUNPCKLBW ymm1, ymm2, ymm3/m256B V/V AVX2 Interleave low-order bytes from ymm2 and 
VEX.256.66.0F.WIG 61 /r
VPUNPCKLWD ymm1, ymm2, ymm3/m256B V/V AVX2 Interleave low-order words from ymm2 and 
VEX.256.66.0F.WIG 62 /r
VPUNPCKLDQ ymm1, ymm2, ymm3/m256B V/V AVX2 Interleave low-order doublewords from ymm2 
VEX.256.66.0F.WIG 6C /r
VPUNPCKLQDQ ymm1, ymm2, ymm3/m256B V/V AVX2 Interleave low-order quadword from ymm2 
EVEX.128.66.0F.WIG 60 /r
VPUNPCKLBW xmm1 {k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWInterleave low-order bytes from xmm2 and 
xmm3/m128 into xmm1 register subject to 
write mask k1.
EVEX.128.66.0F.WIG 61 /r
VPUNPCKLWD xmm1 {k1 }{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWInterleave low-order words from xmm2 and 
EVEX.128.66.0F.W0 62 /r
VPUNPCKLDQ xmm1 {k1}{z}, xmm2, 
AVX512FInterleave low-order doublewords from xmm2 
and xmm3/m128/m32bcst into xmm1 register subject to write mask k1.
EVEX.128.66.0F.W1 6C /r
VPUNPCKLQDQ xmm1 {k1}{z}, xmm2, 
AVX512FInterleave low-order quadword from zmm2 
and zmm3/m512/m64bcst into zmm1 
register subject to write mask k1.PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-507Instruction Operand Encoding
Unpacks and interleaves the low-order data elements (byt es, words, doublewords, and quadwords) of the destina-
tion operand (first operand) and source operand (secon d operand) into the destination operand. (Figure 4-22 
shows the unpack operation for bytes in 64-bit operan ds.). The high-order data elements are ignored.EVEX.256.66.0F.WIG 60 /r
VPUNPCKLBW ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWInterleave low-order bytes from ymm2 and 
ymm3/m256 into ymm1 register subject to 
EVEX.256.66.0F.WIG 61 /r
VPUNPCKLWD ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWInterleave low-order words from ymm2 and 
EVEX.256.66.0F.W0 62 /r
VPUNPCKLDQ ymm1 {k1}{z}, ymm2, 
AVX512FInterleave low-order doublewords from ymm2 
and ymm3/m256/m32bcst into ymm1 
register subject to write mask k1.
EVEX.256.66.0F.W1 6C /r
VPUNPCKLQDQ ymm1 {k1}{z}, ymm2, 
AVX512FInterleave low-order quadword from ymm2 
EVEX.512.66.0F.WIG 60/r
VPUNPCKLBW zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Interleave low-order bytes from zmm2 and 
zmm3/m512 into zmm1 register subject to 
EVEX.512.66.0F.WIG 61/r
VPUNPCKLWD zmm1 {k1}{z}, zmm2, zmm3/m512C V/V AVX512BW Interleave low-order words from zmm2 and 
EVEX.512.66.0F.W0 62 /r
VPUNPCKLDQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstD V/V AVX512F Interleave low-or der doublewords from zmm2 
and zmm3/m512/m32bcst into zmm1 
EVEX.512.66.0F.W1 6C /r
VPUNPCKLQDQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstD V/V AVX512F Interleave low-order quadword from zmm2 
NOTES:
Mode 
Feature 
FlagDescriptionPUNPCKLBW/PUNPCKLWD/PUNPCKLD Q/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U
4-508 Vol. 2BFigure 4-23.  256-bit VPUNPCKLDQ Instruction Operation
When the source data comes from a 128-bit memory operan d, an implementation may fetch only the appropriate 
64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.
The (V)PUNPCKLBW instruction interleaves the low-orde r bytes of the source and destination operands, the 
(V)PUNPCKLWD instruction interleaves the low-order word s of the source and destination operands, the (V)PUNP-
CKLDQ instruction interleaves the low-or der doubleword (or doublewords) of the source and destination operands, 
and the (V)PUNPCKLQDQ instruction interleaves the low-or der quadwords of the source and destination operands.
elements from the original value in the destination oper and. For example, with the (V)PUNPCKLBW instruction the 
high-order bytes are zero extended (that is, unpacked in to unsigned word integers), and with the (V)PUNPCKLWD 
Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 32-bit memory 
location. The destination operand is an MMX technology register. 
EVEX encoded VPUNPCKLDQ/QDQ: The second source op erand is a ZMM/YMM/XMM register, a 512/256/128-bit 
memory location or a 512/256/128-bit vector broadcaste d from a 32/64-bit memory location. The first source Figure 4-22.  PUNPCKLBW Instructio n Operation Using 64-bit OperandsX0 X3 X2 X1 Y0 Y3 Y2 Y1X0 X3 X2 X1 Y0 Y3 Y2 Y1 X4 X7 X6 X5 Y4 Y7 Y6 Y5 SRC DEST
DEST
X0 X5 X4 X1 Y0 Y5 Y4 Y1X0 X3 X2 X1 Y0 Y3 Y2 Y1 X4 X7 X6 X5 Y4 Y7 Y6 Y5 SRC
00 255
25531PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-509operand and destination operands are ZMM/YMM/XMM regist ers. The destination is co nditionally updated with 
EVEX encoded VPUNPCKLWD/BW: The second source op erand is a ZMM/YMM/XMM register, a 512/256/128-bit

DEST
00 255
EVEX encoded VPUNPCKLWD/BW: The second source op erand is a ZMM/YMM/XMM register, a 512/256/128-bit 
Operation
PUNPCKLBW Instruction With 64-bit Operands:
DEST[63:56] := SRC[31:24];DEST[55:48] := DEST[31:24];DEST[47:40] := SRC[23:16];DEST[39:32] := DEST[23:16];DEST[31:24] := SRC[15:8];DEST[23:16] := DEST[15:8];DEST[15:8] := SRC[7:0];DEST[7:0] := DEST[7:0];
PUNPCKLWD Instruction With 64-bit Operands:
DEST[63:48] := SRC[31:16];DEST[47:32] := DEST[31:16];DEST[31:16] := SRC[15:0];DEST[15:0] := DEST[15:0];
PUNPCKLDQ Instruction With 64-bit Operands:
DEST[63:32] := SRC[31:0];DEST[31:0] := DEST[31:0];
INTERLEAVE_BYTES_512b (SRC1, SRC2)TMP_DEST[255:0] := INTE RLEAVE_BYTES_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] := IN TERLEAVE_BYTES_256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_BYTES_256b (SRC1, SRC2) 
DEST[7:0] := SRC1[7:0]DEST[15:8] := SRC2[7:0]DEST[23:16] := SRC1[15:8]DEST[31:24] := SRC2[15:8]DEST[39:32] := SRC1[23:16]DEST[47:40] := SRC2[23:16]DEST[55:48] := SRC1[31:24]DEST[63:56] := SRC2[31:24]DEST[71:64] := SRC1[39:32]DEST[79:72] := SRC2[39:32]DEST[87:80] := SRC1[47:40]DEST[95:88] := SRC2[47:40]DEST[103:96] := SRC1[55:48]DEST[111:104] := SRC2[55:48]DEST[119:112] := SRC1[63:56]DEST[127:120] := SRC2[63:56]DEST[135:128] := SRC1[135:128]DEST[143:136] := SRC2[135:128]DEST[151:144] := SRC1[143:136]DEST[159:152] := SRC2[143:136]DEST[167:160] := SRC1[151:144]DEST[175:168] := SRC2[151:144]PUNPCKLBW/PUNPCKLWD/PUNPCKLD Q/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U
4-510 Vol. 2BDEST[183:176] := SRC1[159:152]
DEST[191:184] := SRC2[159:152]DEST[199:192] := SRC1[167:160]DEST[207:200] := SRC2[167:160]DEST[215:208] := SRC1[175:168]DEST[223:216] := SRC2[175:168]DEST[231:224] := SRC1[183:176]DEST[239:232] := SRC2[183:176]DEST[247:240] := SRC1[191:184]DEST[255:248] := SRC2[191:184]
INTERLEAVE_BYTES (SRC1, SRC2) 
DEST[7:0] := SRC1[7:0]DEST[15:8] := SRC2[7:0]DEST[23:16] := SRC1[15:8]DEST[31:24] := SRC2[15:8]DEST[39:32] := SRC1[23:16]DEST[47:40] := SRC2[23:16]DEST[55:48] := SRC1[31:24]DEST[63:56] := SRC2[31:24]DEST[71:64] := SRC1[39:32]DEST[79:72] := SRC2[39:32]DEST[87:80] := SRC1[47:40]DEST[95:88] := SRC2[47:40]DEST[103:96] := SRC1[55:48]DEST[111:104] := SRC2[55:48]DEST[119:112] := SRC1[63:56]DEST[127:120] := SRC2[63:56]
INTERLEAVE_WORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] := INTERLEAVE_WORDS_256b(SRC1[255:0], SRC[255:0])TMP_DEST[511:256] := INTERLEAVE_WORDS _256b(SRC1[511:256], SRC[511:256])
INTERLEAVE_WORDS_256b(SRC1, SRC2)
DEST[15:0] := SRC1[15:0]DEST[31:16] := SRC2[15:0]DEST[47:32] := SRC1[31:16]DEST[63:48] := SRC2[31:16]DEST[79:64] := SRC1[47:32]DEST[95:80] := SRC2[47:32]DEST[111:96] := SRC1[63:48]DEST[127:112] := SRC2[63:48]DEST[143:128] := SRC1[143:128]DEST[159:144] := SRC2[143:128]DEST[175:160] := SRC1[159:144]DEST[191:176] := SRC2[159:144]DEST[207:192] := SRC1[175:160]DEST[223:208] := SRC2[175:160]DEST[239:224] := SRC1[191:176]DEST[255:240] := SRC2[191:176]
INTERLEAVE_WORDS (SRC1, SRC2)
DEST[15:0] := SRC1[15:0]DEST[31:16] := SRC2[15:0]PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-511DEST[47:32] := SRC1[31:16]
DEST[63:48] := SRC2[31:16]DEST[79:64] := SRC1[47:32]DEST[95:80] := SRC2[47:32]DEST[111:96] := SRC1[63:48]DEST[127:112] := SRC2[63:48]
INTERLEAVE_DWORDS_51 2b (SRC1, SRC2)
TMP_DEST[255:0] := INTERLEAVE_DWO RDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] := INTE RLEAVE_DWORDS_256b(SRC1[5 11:256], SRC2[511:256])
INTERLEAVE_DWORDS_ 256b(SRC1, SRC2)
DEST[31:0] := SRC1[31:0]DEST[63:32] := SRC2[31:0]DEST[95:64] := SRC1[63:32]DEST[127:96] := SRC2[63:32]DEST[159:128] := SRC1[159:128]DEST[191:160] := SRC2[159:128]DEST[223:192] := SRC1[191:160]DEST[255:224] := SRC2[191:160]
INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[31:0] := SRC1[31:0]DEST[63:32] := SRC2[31:0]DEST[95:64] := SRC1[63:32]DEST[127:96] := SRC2[63:32]INTERLEAVE_QWORDS_512b (SRC1, SRC2)TMP_DEST[255:0] := INTERLEAVE_QWORDS_256b(SRC1[255:0], SRC2[255:0])TMP_DEST[511:256] := INTE RLEAVE_QWORDS_256b(SRC1[ 511:256], SRC2[511:256])
INTERLEAVE_QWORDS_256b(SRC1, SRC2)
DEST[63:0] := SRC1[63:0]DEST[127:64] := SRC2[63:0]DEST[191:128] := SRC1[191:128]DEST[255:192] := SRC2[191:128]
INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[63:0] := SRC1[63:0]DEST[127:64] := SRC2[63:0]
PUNPCKLBW
DEST[127:0] := INTERLEAVE_BYTES(DEST, SRC)DEST[255:127] (Unmodified)
VPUNPCKLBW (VEX.128 Encoded Instruction)
DEST[127:0] := INTERLEAVE_BYTES(SRC1, SRC2)DEST[MAXVL-1:127] := 0
VPUNPCKLBW (VEX.256 Encoded Instruction)
DEST[255:0] := INTERLEAVE_BYTES_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0PUNPCKLBW/PUNPCKLWD/PUNPCKLD Q/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U
4-512 Vol. 2BVPUNPCKLBW (EVEX.512 Encoded Instruction)
TMP_DEST[VL-1:0] := INTERLEAVE_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_BYT ES_256b(SRC1[VL-1:0], SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_BYT ES_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0DEST[511:0] := INTERLEAVE_BYTES_512b(SRC1, SRC2)
PUNPCKLWD
DEST[127:0] := INTERLEAVE_WORDS(DEST, SRC)DEST[255:127] (Unmodified)
VPUNPCKLWD (VEX.128 Encoded Instruction)
DEST[127:0] := INTERLEAVE_WORDS(SRC1, SRC2)DEST[MAXVL-1:127] := 0
VPUNPCKLWD (VEX.256 Encoded Instruction)
DEST[255:0] := INTERLEAVE _WORDS_256b(SRC1, SRC2)
VPUNPCKLWD (EVEX.512 Encoded Instruction)
TMP_DEST[VL-1:0] := INTERLEAVE_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_WOR DS_256b(SRC1[VL-1:0], SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_WOR DS_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
i := j * 16IF k1[j] OR *no writemask*PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-513THEN DEST[i+15:i] := TMP_DEST[i+15:i]
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0DEST[511:0] := INTERLEAVE _WORDS_512b(SRC1, SRC2)
PUNPCKLDQ
DEST[127:0] := INTERLEAVE_DWORDS(DEST, SRC)DEST[MAXVL-1:128 ] (Unmodified)
VPUNPCKLDQ (VEX.128 Encoded Instruction)
DEST[127:0] := INTERLEAVE_DWORDS(SRC1, SRC2)DEST[MAXVL-1:128] := 0
VPUNPCKLDQ (VEX.256 Encoded Instruction)
DEST[255:0] := INTERLEAVE_DWORDS_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0
VPUNPCKLDQ (EVEX Encoded Instructions)
FI;
TMP_DEST[VL-1:0] := INTERLEAVE_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_DWORD S_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_DWORD S_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FI
FI;PUNPCKLBW/PUNPCKLWD/PUNPCKLD Q/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U
4-514 Vol. 2BENDFOR
DEST511:0] := INTERLEAVE_DWORDS_512b(SRC1, SRC2)DEST[MAXVL-1:VL] := 0
PUNPCKLQDQ
DEST[127:0] := INTERLEAVE_QWORDS(DEST, SRC)DEST[MAXVL-1:128] (Unmodified)
VPUNPCKLQDQ (VEX.128 Encoded Instruction)
DEST[127:0] := INTERLEAVE_QWORDS(SRC1, SRC2)DEST[MAXVL-1:128] := 0
VPUNPCKLQDQ (VEX.256 Encoded Instruction)
DEST[255:0] := INTERLEAVE_QWORDS_256b(SRC1, SRC2)DEST[MAXVL-1:256] := 0
VPUNPCKLQDQ (EVEX Encoded Instructions)
FI;
TMP_DEST[VL-1:0] := INTERLEAVE_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
TMP_DEST[VL-1:0] := INTERLEAVE_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
FI
FI;
VPUNPCKLBW __m512i _mm512_unpacklo_epi8(__m512i a, __m512i b);
VPUNPCKLBW __m512i _mm512_mask_unpacklo_epi8( __m512i s, __mmask64 k, __m512i a, __m512i b);
VPUNPCKLBW __m512i _mm512_maskz_unpacklo_ep i8( __mmask64 k, __m512i a, __m512i b);PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low DataINSTRUCTION SET REFERENCE, M-U

FI;
FI;
FI
FI;
Vol. 2B 4-515VPUNPCKLBW __m256i _mm256_mask_unpacklo_epi8( __m256i s, __mmask32 k, __m256i a, __m256i b);
VPUNPCKLBW __m256i _mm256_maskz_unpacklo_ep i8( __mmask32 k, __m256i a, __m256i b);
VPUNPCKLBW __m128i _mm_mask_unpacklo_epi8(v  s, __mmask16 k, __m128i a, __m128i b);
VPUNPCKLBW __m128i _mm_mask z_unpacklo_epi8( __mmask16 k, __m128i a, __m128i b);
VPUNPCKLWD __m512i _mm512_unpacklo_epi16(__m512i a, __m512i b);VPUNPCKLWD __m512i _mm512_mask_unpacklo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPUNPCKLWD __m512i _mm512_maskz_unpacklo_e pi16( __mmask32 k, __m512i a, __m512i b);
VPUNPCKLWD __m256i _mm256_mask_unpacklo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPUNPCKLWD __m256i _mm256_maskz_unpacklo_e pi16( __mmask16 k, __m256i a, __m256i b);
VPUNPCKLWD __m128i _mm_mask_unpacklo_epi1 6(v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLWD __m128i _mm_maskz_unpacklo_epi16( __mmask8 k, __m128i a, __m128i b);VPUNPCKLDQ __m512i _mm512_unpacklo_epi32(__m512i a, __m512i b);VPUNPCKLDQ __m512i _mm512_mask_unpacklo_epi32(__m 512i s, __mmask16 k, __m512i a, __m512i b);
VPUNPCKLDQ __m512i _mm512_maskz_unpacklo_epi32( __mmask16 k, __m512i a, __m512i b);VPUNPCKLDQ __m256i _mm256_mask_unpacklo_epi32(__m 256i s, __mmask8 k, __m256i a, __m256i b);
VPUNPCKLDQ __m256i _mm256_maskz_unpacklo_epi32( __mmask8 k, __m256i a, __m256i b);VPUNPCKLDQ __m128i _mm_mask_unpacklo_epi32( v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLDQ __m128i _mm_mask z_unpacklo_epi32( __mmask8 k, __m128i a, __m128i b);
VPUNPCKLQDQ __m512i _mm512_unpacklo_epi64(__m512i a, __m512i b);VPUNPCKLQDQ __m512i _mm512_mask_unpacklo_epi64( __m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKLQDQ __m512i _mm512_maskz_unpacklo_epi 64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKLQDQ __m256i _mm256_mask_unpacklo_epi64( __m256i s, __mmask8 k, __m256i a, __m256i b);
VPUNPCKLQDQ __m256i _mm256_maskz_unpacklo_epi 64( __mmask8 k, __m256i a, __m256i b);
VPUNPCKLQDQ __m128i _mm_mask_unpacklo_epi64(__m 128i s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLQDQ __m128i _mm_maskz_unpacklo_epi 64( __mmask8 k, __m128i a, __m128i b);
PUNPCKLBW __m64 _mm_unpack lo_pi8 (__m64 m1, __m64 m2)
(V)PUNPCKLBW __m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)VPUNPCKLBW __m256i _mm256_unpacklo_epi8 (__m256i m1, __m256i m2)PUNPCKLWD __m64 _mm_unpacklo_pi16 (__m64 m1, __m64 m2)(V)PUNPCKLWD __m128i _mm_unpack lo_epi16 (__m128i m1, __m128i m2)
VPUNPCKLWD __m256i _mm256_unpacklo_epi16 (__m256i m1, __m256i m2)PUNPCKLDQ __m64 _mm_unpacklo_pi32 (__m64 m1, __m64 m2)(V)PUNPCKLDQ __m128i _mm_unpacklo_epi32 (__m128i m1, __m128i m2)VPUNPCKLDQ __m256i _mm256_unpacklo_epi32 (__m256i m1, __m256i m2)(V)PUNPCKLQDQ __m128i _mm_unpacklo_epi64 (__m128i m1, __m128i m2)VPUNPCKLQDQ __m256i _mm256_unpacklo_epi64 (__m256i m1, __m256i m2)
None.
None.
EVEX-encoded VPUNPCKLDQ/QDQ, see Table 2-5 0, “Type E4NF Class Exception Conditions.”
EVEX-encoded VPUNPCKLBW/WD, see Ex ceptions Type E4NF.nb in Table 2-5 0, “Type E4NF Class Exception Condi-
tions.”PUSH—Push Word, Doubleword, or Quadword Onto the StackINSTRUCTION SET REFERENCE, M-U
4-516 Vol. 2BPUSH—Push Word, Doubleword, or  Quadword Onto the Stack
Decrements the stack pointer and then stores the source  operand on the top of the stack. Address and operand 
sizes are determined and used as follows:
The address size is used only when referencing a source operand in memory.
The operand size (16, 32, or 64 bits) determines the am ount by which the stack pointer is decremented (2, 4
or 8).
If the source operand is an immediate of size less th an the operand size, a sign-extended value is pushed on
the stack. If the source operand is a segment register  (16 bits) and the operand size is 64-bits, a zero-
extended value is pushed on the stack; if the operand size is 32-bits, either a zero-extended value is pushed
on the stack or the segment selector is written on the stack using a 16-bit move. For the last case, all recent
Intel Core and Intel Atom processors perform a 16-bit move, leaving the upper portion of the stack location
unmodified.Opcode1
NOTES:
En64-Bit 
FF /6 PUSH r/m16 M Valid Valid Push r/m16.
FF /6 PUSH r/m32 M N.E. Valid Push r/m32.FF /6 PUSH r/m64 M Valid N.E. Push r/m64. 50+rw PUSH r16 O Vali d Valid Push r16.
50+rd PUSH r32 O N.E. Valid Push r32.50+rd PUSH r64 O Valid N.E. Push r64.6A ib PUSH imm8 I Valid Valid Push imm8.68 iw PUSH imm16 I Valid Valid Push imm16.68 id PUSH imm32 I Valid Valid Push imm32.0E PUSH CS ZO Invalid Valid Push CS.16 PUSH SS ZO Invalid Valid Push SS.1E PUSH DS ZO Invalid Valid Push DS.06 PUSH ES ZO Invalid Valid Push ES.0F A0 PUSH FS ZO Valid Valid Push FS.0F A8 PUSH GS ZO Valid Valid Push GS.
O opcode + rd (r) N/A N/A N/A
I imm8/16/32 N/A N/A N/A
ZO N/A N/A N/A N/APUSH—Push Word, Doubleword, or Quadword Onto the StackINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-517•Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the 
The stack-address size determines the width of the stack pointer when writing to the stack in memory and
when decrementing the stack pointer. (As stated above, the amount by which the stack pointer is
decremented is determined by the operand size.)
If the operand size is less than the stack-address size, the PUSH instruction may result in a misaligned stack
pointer (a stack pointer that is not aligne d on a doubleword or quadword boundary).
The PUSH ESP instruction pushes the valu e of the ESP register as it existed be fore the instruction was executed. If 
a PUSH instruction uses a memory operand in which the ES P register is used for computing the operand address, 
the address of the operand is computed be fore the ESP register is decremented. 
If the ESP or SP register is 1 when the PUSH instruction is executed in real-address mode, a stack-fault exception 
(#SS) is generated (because the limit of the stack segmen t is violated). Its delivery encounters a second stack-
fault exception (for the same reason), causing generation  of a double-fault exception (#DF). Delivery of the 
double-fault exception encounters a third stack-fault exception, and the logical processor enters shutdown mode. See the discussion of the double-fault exception in Chapter 6 of the Intel
For IA-32 processors from the Intel 286 on, the PUSH ESP instruction pushes the value of the ESP register as it 
existed before the instruction was executed. (This is also true for Intel 64 architecture, real-address and virtual-
8086 modes of IA-32 architecture.) For the Intel® 8086 processor, the PUSH SP in struction pushes the new value 
of the SP register (that is the value after it has been decremented by 2).
Operation
(* See Description section for possi ble sign-extension or zero-extension of source operand and for *)
(* a case in which the size of the memory store ma y be smaller than the inst ruction’s operand size *)
IF StackAddrSize = 64
THEN
THEN
RSP := RSP – 8;
Memory[SS:RSP] := SRC; (* push quadword *)
THEN
RSP := RSP – 4;
Memory[SS:RSP] := SRC; (* push dword *)
RSP := RSP – 2;
Memory[SS:RSP] := SRC; (* push word *)
FI;
ELSE IF StackAddrSize = 32
THEN
THEN
ESP := ESP – 8;
Memory[SS:ESP] := SRC; (* push quadword *)
THEN
ESP := ESP – 4;
Memory[SS:ESP] := SRC; (* push dword *)
ESP := ESP – 2;
Memory[SS:ESP] := SRC; (* push word *)PUSH—Push Word, Doubleword, or Quadword Onto the StackINSTRUCTION SET REFERENCE, M-U
4-518 Vol. 2BFI;
ELSE (* StackAddrSize = 16 *)
THEN
SP := SP – 4;
Memory[SS:SP] := SRC; (* push dword *)
SP := SP – 2;
Memory[SS:SP] := SRC; (* push word *)
FI;
FI;
None.
selector.

FI;
THEN
THEN
THEN
THEN
SP := SP – 4;
SP := SP – 2;
FI;
FI;
None.
selector.
If the new value of the SP or ESP register is outside the stack segment limit.
If the PUSH is of CS, SS, DS, or ES.PUSHA/PUSHAD—Push All General-Purpose RegistersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-519PUSHA/PUSHAD—Push All General-Purpose Registers
Pushes the contents of the general-purpose registers onto the stack. The registers are stored on the stack in the 
following order: EAX, ECX, EDX, EBX, ESP (original value), EBP, ESI, and EDI (if the current operand-size attribute 
is 32) and AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). These instruc-
tions perform the reverse operation of the POPA/POPAD inst ructions. The value pushed for the ESP or SP register 
is its value before prior to pushing the first register (see the “Operation” section below).
The PUSHA (push all) and PUSHAD (p ush all double) mnemonics reference the same opcode. The PUSHA instruc-
tion is intended for use when the operand-size attribut e is 16 and the PUSHAD instruction for when the operand-
size attribute is 32. Some assemblers may force the oper and size to 16 when PUSHA is used and to 32 when 
PUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD) and use the current setting 
of the operand-size attribute to dete rmine the size of values to be push ed from the stack, regardless of the 
mnemonic used.
In the real-address mode, if the ESP or SP register is 1,  3, or 5 when PUSHA/PUSHAD executes: an #SS exception 
is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates a 
#DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel® 64 and 
Operation
IF 64-bit Mode 
THEN #UD
 = 32 (* PUSHAD instruction *)
THEN
Temp := (ESP);Push(EAX);Push(ECX);Push(EDX);Push(EBX);Push(Temp);Push(EBP);Push(ESI);Push(EDI);
 = 16, PUSHA instruction *)
Temp := (SP);Push(AX);Push(CX);Push(DX);Push(BX);Push(Temp);Opcode Instruction Op/ 
En64-Bit 
60 PUSHA ZO Invalid Valid Push AX, CX, DX, BX, original SP, BP, SI, and DI.
60 PUSHAD ZO Invalid Valid Push EAX, ECX, EDX, EBX, original ESP, EBP, 
ESI, and EDI.
ZO N/A N/A N/A N/APUSHA/PUSHAD—Push All General-Purpose RegistersINSTRUCTION SET REFERENCE, M-U
4-520 Vol. 2BPush(BP);
Push(SI);Push(DI);
FI;
None.
#SS(0) If the starting or ending stack a ddress is outside the stack segment limit.
#GP If the ESP or SP register contains 7, 9, 11, 13, or 15.
#GP(0) If the ESP or SP register contains 7, 9, 11, 13, or 15.#PF(fault-code) If a page fault occurs.#AC(0) If an unaligned memory reference is made while alignment checking is enabled.
#UD If in 64-bit mode.PUSHF/PUSHFD/PUSHFQ—Push EFLAGS Register Onto the StackINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-521PUSHF/PUSHFD/PUSHFQ—Push EFLAG S Register Onto the Stack
Decrements the stack pointer by 4 (if the current operand-si ze attribute is 32) and pushes the entire contents of 
the EFLAGS register onto the stack, or decrements the st ack pointer by 2 (if the operand-size attribute is 16) and 
pushes the lower 16 bits of the EFLAGS register (that is , the FLAGS register) onto the stack. These instructions 
reverse the operation of the POPF/POPFD instructions. 
When copying the entire EFLAGS register to the stack, th e VM and RF flags (bits 16 and 17) are not copied; instead, 
the values for these flags are cleared in the EFLAGS im age stored on the stack. See Chapter 3 of the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume  1, for more information about the EFLAGS register. 
The PUSHF (push flags) and PUSHFD (push flags doub le) mnemonics reference the same opcode. The PUSHF 
instruction is intended for use when the operand-size attribute is 16 and the PUSHFD instruction for when the 
operand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHF is used and to 32 
when PUSHFD is used. Others may treat these mnemon ics as synonyms (PUSHF/PUSHFD) and use the current 
setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the 
In 64-bit mode, the instruction’s default operation is to decrement the stack pointer (RSP) by 8 and pushes RFLAGS 
on the stack. 16-bit operation is supported using the op erand size override prefix 66H. 32-bit operand size cannot 
be encoded in this mode. When copying RFLAGS to the stack, the VM and RF flags (bits 16 and 17) are not copied; 
instead, values for these flags are cleared in the RFLAGS image stored on the stack.
the PUSHF/PUSHFD instructions can be used only if IOPL = 3; otherwise, a general-protection exception (#GP) 
occurs. If the virtual-8086 mode extensions are enabled (CR4.VME = 1), PUSHF (but no t PUSHFD) can be executed 
in virtual-8086 mode with IOPL < 3.
in the same manner as the virtual-8086 mode extensio ns. PUSHF, however, is not affected by CR4.PVI.)
In the real-address mode, if the ESP or SP register is 1 when PUSHF/PUSHFD instruct ion executes: an #SS excep-
tion is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates a #DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel
® 64 and 
Operation
IF (PE  = 0) or (PE  = 1 and ((VM  = 0) or (VM = 1 and IOPL = 3)))
(* Real-Address Mode, Protected mode, or Virtual-8086 mode with IOPL equal to 3 *)
THEN
IF OperandSize =  32
THEN 
push (EFLAGS AND 00FCFFFFH);(* VM and RF bits are cleared in image stored on the stack *)
ELSE 
push (EFLAGS); (* Lo wer 16 bits only *)Opcode Instruction Op/ 
En64-Bit 
9C PUSHF ZO Valid Valid Push lower 16 bits of EFLAGS.
9C PUSHFD ZO N.E. Valid Push EFLAGS.9C PUSHFQ ZO Valid N.E. Push RFLAGS.
ZO N/A N/A N/A N/APUSHF/PUSHFD/PUSHFQ—Push EFLAGS Register Onto the StackINSTRUCTION SET REFERENCE, M-U
4-522 Vol. 2BFI;
ELSE IF 64-bit MODE (* In 64-bit Mode *)
THEN 
push (RFLAGS AND 00000000_00FCFFFFH);(* VM and RF bits are cleared in  image stored on the stack; *)
ELSE 
push (EFLAGS); (* Lo wer 16 bits only *)
FI;
ELSE (* In Virtual-8086 Mo de with IOPL less than 3 *)
IF (CR4.VME = 0) OR  (OperandSize = 32)
THEN #GP(0); (* Trap to virtual-8086 monitor *)
ELSE
tempFLAGS = EFLAGS[15:0];tempFLAGS[9] = tempFLAGS[19]; (* VIF replaces IF *)
tempFlags[13:12] = 3; (* IOPL is set to 3 in image stored on the stack *)
push (tempFLAGS);
FI;
FI;
None.
#SS(0) If the new value of the ESP register  is outside the stack segment boundary. 

THEN 
ELSE 
FI;
ELSE
FI;
FI;
None.
#GP(0) If the I/O privilege level is less than 3.#PF(fault-code) If a page fault occurs.#AC(0) If an unaligned memory reference is made while alignment checking is enabled.
#UD If the LOCK prefix is used.PXOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-523PXOR—Logical Exclusive OR
Performs a bitwise logical exclusive-OR (XOR) operation on the source operand (second operand) and the destina-
tion operand (first operand) and stores the result in the de stination operand. Each bit of the result is 1 if the corre-
sponding bits of the two operands are different; each bi t is 0 if the corresponding bits of the operands are the 
same.
Legacy SSE instructions 64-bit operand: The source operand can be an MMX technology register or a 64-bit 
memory location. The destination oper and is an MMX technology register.Opcode/
Mode 
Feature 
NP 0F EF /r1
PXOR mm, mm/m64
NOTES:
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.A V/V MMX Bitwise XOR of mm/m64 and mm.
66 0F EF /r
PXOR xmm1, xmm2/m128A V/V SSE2 Bitwise XOR of xmm2/m128 and xmm1.
VEX.128.66.0F.WIG EF /r
VPXOR xmm1, xmm2, xmm3/m128B V/V AVX Bitwise XOR of xmm3/m128 and xmm2.
VEX.256.66.0F.WIG EF /r
VPXOR ymm1, ymm2, ymm3/m256B V/V AVX2 Bitwise XOR of ymm3/m256 and ymm2.
EVEX.128.66.0F.W0 EF /r
VPXORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst C V/V AVX512VL
AVX512FBitwise XOR of packed do ubleword integers in 
xmm2 and xmm3/m128 using writemask k1. 
EVEX.256.66.0F.W0 EF /r
VPXORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst C V/V AVX512VL
ymm2 and ymm3/m256 using writemask k1. 
EVEX.512.66.0F.W0 EF /r
VPXORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst C V/V AVX512F Bitwise XOR of packed doubleword integers in 
EVEX.128.66.0F.W1 EF /r
VPXORQ xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcst C V/V AVX512VL
AVX512FBitwise XOR of packed quadword integers in 
EVEX.256.66.0F.W1 EF /r
VPXORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst C V/V AVX512VL
EVEX.512.66.0F.W1 EF /r
VPXORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst C V/V AVX512F Bitwise XOR of packed quadword integers in 
CF u l l M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/APXOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, M-U
4-524 Vol. 2B128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first 
corresponding register destination are zeroed.
mask k1.
Operation
PXOR (64-bit Operand)
DEST := DEST XOR SRC
PXOR (128-bit Legacy SSE Version)
DEST := DEST XOR SRCDEST[MAXVL-1:128] (Unmodified)
VPXOR (VEX.128 En coded Version)
DEST := SRC1 XOR SRC2DEST[MAXVL-1:128] := 0
VPXOR (VEX.256 En coded Version)
DEST := SRC1 XOR SRC2DEST[MAXVL-1:256] := 0
VPXORD (EVEX Encoded Versions) 
THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE XOR SRC2[31:0]ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE XOR SRC2[i+31:i]
FI;
ELSE 
FI;
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0PXOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-525VPXORQ (EVEX Encoded Versions) 
THEN DEST[i+63:i] := SRC1[i+63:i] BITWISE XOR SRC2[63:0]ELSE DEST[i+63:i] := SRC1[i+63:i] BITWISE XOR SRC2[i+63:i]
FI;
ELSE 
FI;
FI;
VPXORD __m512i _mm512_xor_e pi32(__m512i a, __m512i b)
VPXORD __m512i _mm512_mask_xor_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b)VPXORD __m512i _mm512_maskz_xor_epi 32( __mmask16 m, __m512i a, __m512i b)
VPXORD __m256i _mm256_xor_e pi32(__m256i a, __m256i b)
VPXORD __m256i _mm256_mask_xor_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b)VPXORD __m256i _mm256_maskz_xor_epi 32( __mmask8 m, __m256i a, __m256i b)
VPXORD __m128i _mm_xor_epi32(__m128i a, __m128i b)VPXORD __m128i _mm_mask_xor_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b)VPXORD __m128i _mm_maskz_xor_epi32(  __mmask16 m, __m128i a, __m128i b)
VPXORQ __m512i _mm512_xor_epi64( __m512i a, __m512i b);VPXORQ __m512i _mm512_mask_xor_epi64(__m512 i s, __mmask8 m, __m512i a, __m512i b);
VPXORQ __m512i _mm512_maskz_xor_epi64 (__mmask8 m, __m512i a, __m512i b);
VPXORQ __m256i _mm256_xor_epi64( __m256i a, __m256i b);VPXORQ __m256i _mm256_mask_xor_epi64(__m256 i s, __mmask8 m, __m256i a, __m256i b);
VPXORQ __m256i _mm256_maskz_xor_epi64 (__mmask8 m, __m256i a, __m256i b);
VPXORQ __m128i _mm_xor_epi64( __m128i a, __m128i b);VPXORQ __m128i _mm_mask_xor_epi64(__m128i  s, __mmask8 m, __m128i a, __m128i b);
VPXORQ __m128i _mm_maskz_xor_epi64( __mmask8 m, __m128i a, __m128i b);
PXOR:__m64 _mm_xor_si64 (__m64 m1, __m64 m2)(V)PXOR:__m128i _mm_xor_si128 ( __m128i a, __m128i b)VPXOR:__m256i _mm256_xor_si256 ( __m256i a, __m256i b)
None.
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”RCL/RCR/ROL/ROR—RotateINSTRUCTION SET REFERENCE, M-U
4-526 Vol. 2BRCL/RCR/ROL/ROR—Rotate
Opcode1Instruction Op/ 
En64-Bit 
D0 /2 RCL r/m8, 1 M1 Valid Valid Rotate 9 bits (CF, r/m8) left once.
REX + D0 /2 RCL r/m82, 1 M1 Valid N.E. Rotate 9 bits (CF, r/m8) left once. 
D2 /2 RCL r/m8, CL MC Valid Valid Rotate 9 bits (CF, r/m8) left CL times. 
REX + D2 /2 RCL r/m82, CL MC Valid N.E. Rotate 9 bits (CF, r/m8) left CL times. 
C0 /2 ib RCL r/m8, imm8 MI Valid Valid Rotate 9 bits (CF, r/m8) left imm8 times.REX + C0 /2 ib RCL r/m8
2, imm8 MI Valid N.E. Rotate 9 bits (CF, r/m8) left imm8 times.
D1 /2 RCL r/m16, 1 M1 Valid Valid Rotat e 17 bits (CF, r/m16) left once.
D3 /2 RCL r/m16, CL MC Valid Valid Rotate 17 bits (CF, r/m16) left CL times.
C1 /2 ib RCL r/m16, imm8 MI Valid Valid Rotat e 17 bits (CF, r/m16) left imm8 times.
D1 /2 RCL r/m32, 1 M1 Valid Valid Rotat e 33 bits (CF, r/m32) left once.
REX.W + D1 /2 RCL r/m64, 1 M1 Valid N.E. Rotate 65 bits (CF, r/m64) left once. Uses a 6 
bit count.
D3 /2 RCL r/m32, CL MC Valid Valid Rotate 33 bits (CF, r/m32) left CL times.
REX.W + D3 /2 RCL r/m64, CL MC Valid N.E. Rotate 65 bits (CF, r/m64) left CL times. Uses a 
6 bit count.

bit count.
C1 /2 ib RCL r/m32, imm8 MI Valid Valid Rotat e 33 bits (CF, r/m32) left imm8 times.
REX.W + C1 /2 ib RCL r/m64, imm8 MI Valid N.E. Rot ate 65 bits (CF, r/m6 4) left imm8 times. 
Uses a 6 bit count.
D0 /3 RCR r/m8, 1 M1 Valid Valid Rotate 9 bits (CF, r/m8) right once. REX + D0 /3 RCR r/m8
2, 1 M1 Valid N.E. Rotate 9 bits (CF, r/m8) right once. 
D2 /3 RCR r/m8, CL MC Valid Valid Rotate 9 bits (CF, r/m8) right CL times. REX + D2 /3 RCR r/m8
2, CL MC Valid N.E. Rotate 9 bits (CF, r/m8) right CL times. 
C0 /3 ib RCR r/m8, imm8 MI Valid Valid Rotate 9 bits (CF, r/m8) right imm8 times. REX + C0 /3 ib RCR r/m8
2, imm8 MI Valid N.E. Rotate 9 bits (CF, r/m8) right imm8 times. 
D1 /3 RCR r/m16, 1 M1 Valid Valid Rotat e 17 bits (CF, r/m16) right once.
D3 /3 RCR r/m16, CL MC Valid Valid Rotate 17 bits (CF, r/m16) right CL times.
C1 /3 ib RCR r/m16, imm8 MI Valid Valid Rotat e 17 bits (CF, r/m16) right imm8 times.
D1 /3 RCR r/m32, 1 M1 Valid Valid Rotate 33 bits (CF, r/m32) right once. Uses a 6 
bit count.
REX.W + D1 /3 RCR r/m64, 1 M1 Valid N.E. Rotate 65 bits (CF, r/m64) right once. Uses a 6 
bit count.
D3 /3 RCR r/m32, CL MC Valid Valid Rotate 33 bits (CF, r/m32) right CL times.
REX.W + D3 /3 RCR r/m64, CL MC Valid N.E. Rotate 65 bits (CF, r/m64) right CL times. Uses 
a 6 bit count.
C1 /3 ib RCR r/m32, imm8 MI Valid Valid Rotat e 33 bits (CF, r/m32) right imm8 times.
REX.W + C1 /3 ib RCR r/m64, imm8 MI Valid N.E. Rot ate 65 bits (CF, r/m64) right imm8 times. 
D0 /0 ROL r/m8, 1 M1 Valid Valid Rotate 8 bits r/m8 left once.REX + D0 /0 ROL r/m8
2, 1 M1 Valid N.E. Rotate 8 bits r/m8 left once
D2 /0 ROL r/m8, CL MC Valid Valid Rot ate 8 bits r/m8 left CL times.
REX + D2 /0 ROL r/m82, CL MC Valid N.E. Rotate 8 bits r/m8 left CL times.
C0 /0 ib ROL r/m8, imm8 MI Valid Valid Rotate 8 bits r/m8 left imm8 times.RCL/RCR/ROL/ROR—RotateINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-527Instruction Operand EncodingREX + C0 /0 ib ROL r/m82, imm8 MI Valid N.E. Rotate 8 bits r/m8 left imm8 times.
D1 /0 ROL r/m16, 1 M1 Valid Valid R otate 16 bits r/m16 left once.
D3 /0 ROL r/m16, CL MC Valid Valid Rot ate 16 bits r/m16 left CL times.
C1 /0 ib ROL r/m16, imm8 MI Valid Valid R otate 16 bits r/m16 left imm8 times.
D1 /0 ROL r/m32, 1 M1 Valid Valid R otate 32 bits r/m32 left once.
REX.W + D1 /0 ROL r/m64, 1 M1 Valid N.E. Rotate  64 bits r/m64 left once. Uses a 6 bit 
count.
D3 /0 ROL r/m32, CL MC Valid Valid Rot ate 32 bits r/m32 left CL times.
REX.W + D3 /0 ROL r/m64, CL MC Valid N.E. Rotate 64 bits r/m64 left CL times. Uses a 6 
bit count.
C1 /0 ib ROL r/m32, imm8 MI Valid Valid R otate 32 bits r/m32 left imm8 times.
REX.W + C1 /0 ib ROL r/m64, imm8 MI Valid N.E. Rot ate 64 bits r/m64 left  imm8 times. Uses a 
D0 /1 ROR r/m8, 1 M1 Valid Valid Rotate 8 bits r/m8 right once.REX + D0 /1 ROR r/m8
2, 1 M1 Valid N.E. Rotate 8 bits r/m8 right once.
D2 /1 ROR r/m8, CL MC Valid Valid Rotate 8 bits r/m8 right CL times.REX + D2 /1 ROR r/m8
2, CL MC Valid N.E. Rotate 8 bits r/m8 right CL times.
C0 /1 ib ROR r/m8, imm8 MI Valid Valid Rotate 8 bits r/m16 right imm8 times.REX + C0 /1 ib ROR r/m8
2, imm8 MI Valid N.E. Rotate 8 bits r/m16 right imm8 times.
D1 /1 ROR r/m16, 1 M1 Valid Valid Rotate 16 bits r/m16 right once.D3 /1 ROR r/m16, CL MC Valid Valid Rot ate 16 bits r/m16 right CL times.
C1 /1 ib ROR r/m16, imm8 MI Valid Valid Rotate 16 bits r/m16 right imm8 times.D1 /1 ROR r/m32, 1 M1 Valid Valid Rotate 32 bits r/m32 right once.REX.W + D1 /1 ROR r/m64, 1 M1 Valid N.E. Rotate  64 bits r/m64 right once. Uses a 6 bit 
count.
D3 /1 ROR r/m32, CL MC Valid Valid Rot ate 32 bits r/m32 right CL times.
REX.W + D3 /1 ROR r/m64, CL MC Valid N.E. Rotate 64 bits r/m64 right CL times. Uses a 6 
bit count.
C1 /1 ib ROR r/m32, imm8 MI Valid Valid Rotate 32 bits r/m32 right imm8 times.REX.W + C1 /1 ib ROR r/m64, imm8 MI Valid N.E. Ro tate 64 bits r/m64 righ t imm8 times. Uses a 
NOTES:
1. See the IA-32 Architecture  Compatibility section below.
2. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.
M1 ModRM:r/m (w) 1 N/A N/A
MC ModRM:r/m (w) CL N/A N/A
MI ModRM:r/m (w) imm8 N/A N/AOpcode1Instruction Op/ 
En64-Bit 
Leg ModeDescriptionRCL/RCR/ROL/ROR—RotateINSTRUCTION SET REFERENCE, M-U
4-528 Vol. 2BDescription
Shifts (rotates) the bits of the first operand (destinati on operand) the number of bit positions specified in the 
second operand (count operand) and stores the result in  the destination operand. The destination operand can be 
a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in 
the CL register. The count is masked to 5 bits  (or 6 bits if in 64-bit mode and REX.W = 1).
The rotate left (ROL) and rotate through carry left (RCL) in structions shift all the bits toward more-significant bit 
positions, except for the most-significant bit, which is rotated to the least-significant bit location. The rotate right (ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except 
for the least-significant bit, which is rotated to the most-significant bit location.
The RCL and RCR instructions include the CF flag in the ro tation. The RCL instruction shifts the CF flag into the 
least-significant bit and shifts the most-significant bit into the CF flag. The RCR instruction shifts the CF flag into the 
most-significant bit and shifts the least-significant bit in to the CF flag. For the ROL and ROR instructions, the orig-
inal value of the CF flag is not a part of the result, but th e CF flag receives a copy of the bit that was shifted from 
one end to the other.
The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except RCL and RCR instructions 
only: a zero-bit rotate does nothing, that is affects no flag s). For left rotates, the OF flag is set to the exclusive OR 
of the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the 
exclusive OR of the two most-significant bits of the result.
In 64-bit mode, using a REX prefix in the form of REX. R permits access to additional registers (R8-R15). Use of 
REX.W promotes the first operand to 64 bits and causes the count operand to become a 6-bit counter.
The 8086 does not mask the rotation count. However, a ll other IA-32 processors (starting with the Intel 286 
processor) do mask the rotation count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes (including the virtual-8086 mode) to re duce the maximum execution time of the instructions.
Operation
(* RCL and RCR Instructions *)
SIZE := OperandSize;CASE (determine count) OF
SIZE := 8: tempCOUNT := (COUNT AND 1FH) MOD 9;
SIZE := 16: tempCOUNT := (COUNT AND 1FH) MOD 17;SIZE := 32: tempCOUNT := COUNT AND 1FH;SIZE := 64: tempCOUNT := COUNT AND 3FH;
ESAC;IF OperandSize = 64
THEN COUNTMASK = 3FH;ELSE COUNTMASK = 1FH;
FI;
(* RCL Instruction Operation *)
WHILE (tempCOUNT 
≠ 0)
DO
tempCF := MSB(DEST);DEST := (DEST 
∗ 2) + CF;
CF := tempCF;tempCOUNT := tempCOUNT – 1;
OD;
ELIHW;IF (COUNT & COUNTMASK) = 1
THEN OF := MSB(DEST) XOR CF;ELSE OF is undefined;
FI;RCL/RCR/ROL/ROR—RotateINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-529(* RCR Instruction Operation *)
IF (COUNT & COUNTMASK) = 1
FI;WHILE (tempCOUNT 
≠ 0)
DO
tempCF := LSB(SRC);DEST := (DEST / 2) + (CF * 2
SIZE);
OD;
(* ROL Instruction Operation *)
tempCOUNT := (COUNT & COUNTMASK) MOD SIZE
≠ 0)
DO
∗ 2) + tempCF;
tempCOUNT := tempCOUNT – 1;
OD;
ELIHW;IF (COUNT & COUNTMASK) ≠ 0
THEN CF := LSB(DEST);
FI;IF (COUNT & COUNTMASK) = 1
FI;
(* ROR Instruction Operation *)
tempCOUNT := (COUNT & COUNTMASK) MOD SIZEWHILE (tempCOUNT 
≠ 0)
DO
tempCF := LSB(SRC);DEST := (DEST / 2) + (tempCF 
∗ 2SIZE);
OD;
THEN CF := MSB(DEST);
FI;IF (COUNT & COUNTMASK) =
 1
THEN OF := MSB(DEST) XOR MSB − 1(DEST);
ELSE OF is undefined;
FI;
For RCL and RCR instructions, a zero-bit rotate does nothing,  i.e., affects no flags. For ROL and ROR instructions, if 
the masked count is 0, the flags are not affected. If the ma sked count is 1, then the OF flag is affected, otherwise 
(masked count is greater than 1) the OF flag is undefined. RCL/RCR/ROL/ROR—RotateINSTRUCTION SET REFERENCE, M-U
4-530 Vol. 2BFor all instructions, the CF flag is affected when the masked count is non-zero. The SF, ZF, AF, and PF flags are 
always unaffected.
#GP(0) If the source operand is located in a non-writable segment.

FI;
≠ 0)
DO
∗ 2SIZE);
OD;
 1
FI;
#GP(0) If the source operand is located in a nonwritable segment.
#UD If the LOCK prefix is used.RCPPS—Compute Reciprocals of Packed Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-531RCPPS—Compute Reciprocals of Packed Si ngle Precision Floating-Point Values
Performs a SIMD computation of the approximate reciprocal s of the four packed single precision floating-point 
values in the source operand (second operand) stores the pa cked single precision floating-point results in the desti-
nation operand. The source operand can be an XMM re gister or a 128-bit memory location. The destination 
operand is an XMM register. See Figure 10-5 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1, for an illustration of a SIMD single precision floating-point operation.
The relative error for this approximation is:
|Relative Error| ≤ 1.5 ∗ 2−12 
The RCPPS instruction is not affected by  the rounding control bits in the MXCSR register. When a source value is a 
0.0, an ∞ of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign). 
Tiny results (see Section 4.9.1.5, “Numeric Underflow Exception (#U)” in Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 1) are always flushed to 0.0, with the sign of the operand. (Input values greater than or equal to |1.11111111110100000000000B ∗2
125| are guaranteed to not produce tiny results; input values 
less than or equal to |1.00000000000110000000001B*2126| are guaranteed to produce tiny results, which are in 
turn flushed to 0.0; and input values in between this ra nge may or may not produce tiny results, depending on the 
implementation.) When a source value is an SNaN or QNaN , the SNaN is converted to a QNaN or the source QNaN 
zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.Opcode*/
Mode 
Feature 
NP 0F 53 /r
RCPPS xmm1, xmm2/m128RM V/V SSE Computes the approximate reciprocals of the 
packed single precision floating-point values in 
xmm2/m128 and stores the results in xmm1.
VEX.128.0F.WIG 53 /r
VRCPPS xmm1, xmm2/m128RM V/V AVX Computes the approximate reciprocals of 
packed single precision values in xmm2/mem and stores the results in xmm1.
VEX.256.0F.WIG 53 /r
VRCPPS ymm1, ymm2/m256RM V/V AVX Computes the approximate reciprocals of 
packed single precision values in ymm2/mem 
and stores the results in ymm1.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ARCPPS—Compute Reciprocals of Packed Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-532 Vol. 2BOperation
RCPPS (128-bit Legacy SSE Version)
DEST[31:0] := APPROXIMATE(1/SRC[31:0])DEST[63:32] := APPROXIMATE(1/SRC[63:32])DEST[95:64] := APPROXIMATE(1/SRC[95:64])DEST[127:96] := APPROXIMATE(1/SRC[127:96])DEST[MAXVL-1:128] (Unmodified)
VRCPPS (VEX.128 Encoded Version)
DEST[31:0] := APPROXIMATE(1/SRC[31:0])DEST[63:32] := APPROXIMATE(1/SRC[63:32])DEST[95:64] := APPROXIMATE(1/SRC[95:64])DEST[127:96] := APPROXIMATE(1/SRC[127:96])DEST[MAXVL-1:128] := 0
VRCPPS (VEX.256 Encoded Version)
DEST[31:0] := APPROXIMATE(1/SRC[31:0])DEST[63:32] := APPROXIMATE(1/SRC[63:32])DEST[95:64] := APPROXIMATE(1/SRC[95:64])DEST[127:96] := APPROXIMATE(1/SRC[127:96])DEST[159:128] := APPROX IMATE(1/SRC[159:128])
DEST[191:160] := APPROX IMATE(1/SRC[191:160])
DEST[223:192] := APPROX IMATE(1/SRC[223:192])
DEST[255:224] := APPROX IMATE(1/SRC[255:224])
RCCPS __m128 _mm_rcp_ps(__m128 a)
RCPPS __m256 _mm256_rcp_ps (__m256 a);
None.
#UD If VEX.vvvv ≠ 1111B.RCPSS—Compute Reciprocal of Scalar Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-533RCPSS—Compute Reciprocal of Scalar Si ngle Precision Floating-Point Values  
Computes of an approximate reciprocal of the low single precision floating-point value in the source operand 
(second operand) and stores the single precision floating -point result in the destination operand. The source 
operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The three high-order doublewords of the destination oper and remain unchanged. See Figure 10-6 in the Intel
® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a scalar single precision floating-
point operation.
The RCPSS instruction is not affected by the rounding cont rol bits in the MXCSR register. When a source value is a 
1:32) of the corresponding YMM destination register remain unchanged.
Operation
RCPSS (128-bit Legacy SSE Version)
DEST[31:0] := APPROXIMATE(1/SRC[31:0])DEST[MAXVL-1:32] (Unmodified)Opcode*/
Mode 
Feature 
F3 0F 53 /r
RCPSS xmm1, xmm2/m32RM V/V SSE Computes the approximate reciprocal of the scalar single 
precision floating-point value in xmm2/m32 and stores 
the result in xmm1.
VEX.LIG.F3.0F.WIG 53 /r
VRCPSS xmm1, xmm2, xmm3/m32RVM V/V AVX Computes the approximate reciprocal of the scalar single 
precision floating-point value in xmm3/m32 and stores the result in xmm1. Also, upper single precision floating-
point values (bits[127:32]) from xmm2 are copied to 
xmm1[127:32].

Operation
Mode 
Feature 
F3 0F 53 /r
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/ARCPSS—Compute Reciprocal of Scalar Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-534 Vol. 2BVRCPSS (VEX.128 Encoded Version)
DEST[31:0] := APPROXIMATE(1/SRC2[31:0])DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
RCPSS __m128 _mm_rcp_ss(__m128 a)
None.
See Table 2-22, “Type 5 Class Exception Conditions.”RDFSBASE/RDGSBASE—Read FS/GS Segment BaseINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-535RDFSBASE/RDGSBASE—Read FS/GS Segment Base
Loads the general-purpose register indicated by the ModR /M:r/m field with the FS or GS segment base address.
The destination operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the 
operand size is 64 bits. If no REX.W prefix is used, the oper and size is 32 bits; the upper 32 bits of the source base 
address (for FS or GS) are ignored and upper 32 bits of the destination register are cleared. 
This instruction is supported only in 64-bit mode.
Operation
DEST := FS/GS segment base address;
None.
RDFSBASE unsigned int _readfsbase_u32(void );
RDFSBASE unsigned __int64 _readfsbase_u64(void );RDGSBASE unsigned int _readgsbase_u32(void );RDGSBASE unsigned __int64 _readgsbase_u64(void );
#UD The RDFSBASE and RDGSBASE instructions  are not recognized in protected mode.
#UD The RDFSBASE and RDGSBASE instructions  are not recognized in real-address mode.
#UD The RDFSBASE and RDGSBASE instructions  are not recognized in virtual-8086 mode.
#UD The RDFSBASE and RDGSBASE instructions  are not recognized in compatibility mode.Opcode/
En64/32-
bit 
ModeCPUID Fea-
ture FlagDescription
F3 0F AE /0
RDFSBASE r32M V/I FSGSBASE Load the 32-bit destination register with the FS 
F3 REX.W 0F AE /0
RDFSBASE r64M V/I FSGSBASE Load the 64-bit destination register with the FS 
F3 0F AE /1
RDGSBASE r32M V/I FSGSBASE Load the 32-bit destination register with the GS 
F3 REX.W 0F AE /1
RDGSBASE r64M V/I FSGSBASE Load the 64-bit destination register with the GS 
M ModRM:r/m (w) N/A N/A N/ARDFSBASE/RDGSBASE—Read FS/GS Segment BaseINSTRUCTION SET REFERENCE, M-U
4-536 Vol. 2B64-Bit Mode Exceptions
If CR4.FSGSBASE[bit 16] = 0.If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0.RDMSR—Read From Model Specific RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-537RDMSR—Read From Model Specific Register
Reads the contents of a 64-bit model specific register (M SR) specified in the ECX register into registers EDX:EAX. 
(On processors that support the Intel 64 architecture, the hi gh-order 32 bits of RCX are ignored.) The EDX register 
is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On 
processors that support the Intel 64 architecture, the high-o rder 32 bits of each of RAX and RDX are cleared.) If 
fewer than 64 bits are implemented in the MSR being read , the values returned to EDX:EAX in unimplemented bit 
locations are undefined.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection 
exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.
The MSRs control functions for testability, execution trac ing, performance-monitoring, and machine check errors. 
Chapter 2, “Model-Specific Registers (MSRs)” of the Intel
Manual, Volume 4, lists all the MSRs that can be read with this instruction and their addresses. Note that each processor family has its own set of MSRs.
The CPUID instruction should be used to determ ine whether MSRs are supp orted (CPUID.01H:EDX[5] = 1) before 
using this instruction.
The MSRs and the ability to read them with the RDMSR inst ruction were introduced into the IA-32 Architecture with 
the Pentium processor. Execution of this instruction by  an IA-32 processor earlier than the Pentium processor 
results in an invalid opcode exception #UD.
Operation
EDX:EAX := MSR[ECX];
None.
If the value in ECX specifies a rese rved or unimplemented MSR address.
#UD If the LOCK prefix is used.Opcode1
NOTES:
1. See the IA-32 Architecture  Compatibility section below.Instruction Op/ 
En64-Bit 
0F 32 RDMSR ZO Valid Valid Read MSR specified by ECX into EDX:EAX.
ZO N/A N/A N/A N/ARDMSR—Read From Model Specific RegisterINSTRUCTION SET REFERENCE, M-U
4-538 Vol. 2BReal-Address Mode Exceptions
#GP If the value in ECX specifies a reserved or unimplemented MSR address.
#GP(0)  The RDMSR instruction is not recognized in virtual-8086 mode.
Same exceptions as in protected mode.RDPID—Read Processor IDINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-539RDPID—Read Processor ID
Reads the value of the IA32_TSC_AUX MSR (address C000010 3H) into the destination register. The value of CS.D 
and operand-size prefixes (66H and REX.W) do no t affect the behavior of the RDPID instruction.
Operation
DEST := IA32_TSC_AUX 
None.
If CPUID.7H.0:ECX.RDPID[bit 22] = 0.
En64/32-
bit 
ModeCPUID
F3 0F C7 /7
RDPID r32R N.E./V RDPID Read IA32_TSC_AUX into r32.
F3 0F C7 /7
RDPID r64R V/N.E. RDPID Read IA32 _TSC_AUX into r64.
R ModRM:r/m (w) N/A N/A N/A
1.ModRM.MOD = 011B requiredRDPKRU—Read Protection Key Rights for User PagesINSTRUCTION SET REFERENCE, M-U
4-540 Vol. 2BRDPKRU—Read Protection Ke y Rights for User Pages
Reads the value of PKRU into EAX and clears EDX. ECX mu st be 0 when RDPKRU is executed; otherwise, a general-
protection exception (#GP) occurs.
RDPKRU can be executed only if CR4.PKE = 1; otherwise,  an invalid-opcode exception (#UD) occurs. Software can 
discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].
On processors that support the Intel 64 Architecture, the high-order 32-bits of RCX are ignored and the high-order 
32-bits of RDX and RAX are cleared.
Operation
IF (ECX = 0) 
THEN
EAX := PKRU;EDX := 0;
ELSE #GP(0); 
FI;
None.
RDPKRU uint32_t _rdpkru_u32(void);
#GP(0) If ECX ≠ 0. 
If CR4.PKE = 0.
Same exceptions as in protected mode.Opcode* Instruction Op/ 
NP 0F 01 EE RDPKRU ZO V/V OSPKE Reads PKRU into EAX.
ZO N/A N/A N/A N/ARDPKRU—Read Protection Key Rights for User PagesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-54164-Bit Mode Exceptions
Same exceptions as in protected mode.RDPMC—Read Performance-Monitoring CountersINSTRUCTION SET REFERENCE, M-U
4-542 Vol. 2BRDPMC—Read Performance-Monitoring Counters
Reads the contents of the performance monitoring counter (PMC) specified in ECX register into registers EDX:EAX. 
(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register 
is loaded with the high-order 32 bits of the PMC and the EAX register is loaded with the low-order 32 bits. (On 
processors that support the Intel 64 architecture, the high -order 32 bits of each of RAX and RDX are cleared.) If 
fewer than 64 bits are implemented in the PMC being re ad, unimplemented bits returned to EDX:EAX will have

fewer than 64 bits are implemented in the PMC being re ad, unimplemented bits returned to EDX:EAX will have 
value zero. 
The width of PMCs on processors supporting archit ectural performance monitoring (CPUID.0AH:EAX[7:0] ≠ 0) are 
reported by CPUID.0AH:EAX[23:16]. On processors that  do not support architectural performance monitoring 
(CPUID.0AH:EAX[7:0]=0), the width of ge neral-purpose performance PMCs is 40 bits, while the widths of special-
purpose PMCs are implementation specific.
Use of ECX to specify a PMC depends on whether the pr ocessor supports architectural performance monitoring:
•If the processor does not support architectural perf ormance monitoring (CPUID.0AH:EAX[7:0]=0), ECX[30:0] 
specifies the index of the PMC to be re ad. Setting ECX[31] selects “fast” read  mode if supported. In this mode, 
RDPMC returns bits 31:0 of the PMC in EAX while clearing EDX to zero.
•If the processor does support architectural performance monitoring (CPUID.0AH:EAX[7:0] ≠ 0), ECX[31:16] 
specifies type of PMC while ECX[15:0] specifies the index of the PMC to be read within that type. The following 
PMC types are currently defined:
— General-purpose counters use type 0. The index x (to read IA32_PMCx) must be less than the value 
enumerated by CPUID.0AH.EAX[15:8] (thus ECX[15:8] must be zero).
— Fixed-function counters use type 4000H. The index x (t o read IA32_FIXED_CTRx) can be used if either 
CPUID.0AH.EDX[4:0] > x or CPUID.0AH.EC X[x] = 1 (thus ECX[15:5] must be 0).
— Performance metrics use type 2000H. This type can be used only if IA32_PERF_CAPABILITIES.PERF_MET-
RICS_AVAILABLE[bit 15]=1. For this type, the in dex in ECX[15:0] is implementation specific.
Specifying an unsupported PMC encodi ng will cause a general protection exception #GP(0). For PMC details see 
Chapter 20, “Performance Monitoring,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 3B.
When in protected or virtual 8086 mode, the Performance-monitoring  Counters Enabled  (PCE) flag in register 
CR4 restricts the use of the RDPMC instruction. When the PC E flag is set, the RDPMC instruction can be executed at 
any privilege level; when the flag is clear, the instruction can only be executed at privilege level 0. (When in real-
address mode, the RDPMC instruction is always enabled.) Th e PMCs can also be read with the RDMSR instruction, 
when executing at privilege level 0.
The RDPMC instruction is not a serializing instruction; that is, it does not imply that all the events caused by the 
preceding instructions have been comple ted or that events caused by subsequent instructions have not begun. If 
an exact event count is desired, software must insert a serializing instruction (such as the CPUID instruction) 
before and/or after the RDPMC instruction.
Performing back-to-back fast reads are not guaranteed to be monotonic. To guarantee monotonicity on back-to-
back reads, a serializing instruction must be  placed between the two RDPMC instructions.
The RDPMC instruction can execute in 16-bit addressing mo de or virtual-8086 mode; however, the full contents of 
the ECX register are used to select the PMC, and the even t count is stored in the full EAX and EDX registers. The Opcode* Instruction Op/ 
En64-Bit 
0F 33 RDPMC ZO Valid Valid Read performance-monitoring counter 
specified by ECX into EDX:EAX.
ZO N/A N/A N/A N/ARDPMC—Read Performance-Monitoring CountersINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-543RDPMC instruction was introduced into the IA-32 Architecture in the Pentium Pro processor and the Pentium 
processor with MMX technology. The earlier Pentium processo rs have PMCs, but they must  be read with the RDMSR 
Operation
MSCB = Most Significant Count er Bit (* Model-specific *)
IF (((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0)) and (ECX indicates a supported counter))
THEN
EAX := counter[31:0];EDX := ZeroExtend(counter[MSCB:32]); 
ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
#GP(0); 
FI;
None.
#GP(0) If the current privilege level is not 0 an d the PCE flag in the CR4 register is clear.
If an invalid performance counter index is specified.
#GP If an invalid performance counter index is specified.#UD If the LOCK prefix is used.
#GP(0) If the PCE flag in the CR4 register is clear.
#UD If the LOCK prefix is used.RDRAND—Read Random NumberINSTRUCTION SET REFERENCE, M-U
4-544 Vol. 2BRDRAND—Read Random Number
Loads a hardware generated random value and store it in th e destination register. The size of the random value is 
determined by the destination register  size and operating mode. The Carry Fl ag indicates whether a random value 
is available at the time the instruction is executed. CF=1 indicates that the data in the destination is valid. Other-
wise CF=0 and the data in the destination operand will be returned as zeros for the specified width. All other flags 
are forced to 0 in either situation. Software must check the state of CF=1 for determining if a valid random value 
has been returned, otherwise it is expected to loop and retry execution of RDRAND (see Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1, Sect ion 7.3.17, “Random Number Generator Instructions”).
This instruction is available at all privilege levels.In 64-bit mode, the instruction's default operand size is 32 bits. Using a REX prefix in the form of REX.B permits 
Operation
IF HW_RND_GEN.ready = 1
THEN 
CASE of
operand size is 64: DEST[63:0] := HW_RND_GEN.data;operand size is 32: DEST[31:0] := HW_RND_GEN.data;operand size is 16: DEST[15:0] := HW_RND_GEN.data;
ESACCF := 1;
ELSE
CASE of
operand size is 64: DEST[63:0] := 0;operand size is 32: DEST[31:0] := 0;operand size is 16: DEST[15:0] := 0;
ESACCF := 0;
FIOF, SF, ZF, AF, PF := 0;
The CF flag is set according to the result (see the “Ope ration” section above). The OF, SF, ZF, AF, and PF flags are 
set to 0.Opcode*/
Mode 
Feature 
NFx 0F C7 /6
RDRAND r16M V/V RDRAND Read a 16-bit random number and store in the destination 
register.
NFx 0F C7 /6
RDRAND r32M V/V RDRAND Read a 32-bit random number and store in the destination 
register.
NFx REX.W + 0F C7 /6
RDRAND r64M V/I RDRAND Read a 64-bit random number and store in the destination 
register.
M ModRM:r/m (w) N/A N/A N/ARDRAND—Read Random NumberINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-545Intel C/C ++ Compiler Intrinsic Equivalent
RDRAND int _rdrand16_step( unsigned short * );
RDRAND int _rdrand32_step( unsigned int * );RDRAND int _rdrand64_step( unsigned __int64 *);
If CPUID.01H:ECX.RDRAND[bit 30] = 0.
Same exceptions as in protected mode.RDSEED—Read Random SEEDINSTRUCTION SET REFERENCE, M-U
4-546 Vol. 2BRDSEED—Read Random SEED
Loads a hardware generated random value and store it in the destination register. The random value is generated 
from an Enhanced NRBG (Non Deterministic Random Bit Ge nerator) that is compliant to NIST SP800-90B and NIST 
SP800-90C in the XOR construction mode. The size of the ra ndom value is determined by the destination register 
size and operating mode. The Carry Flag indicates whether a random value is available at the time the instruction 
is executed. CF=1 indicates that the data in the destinatio n is valid. Otherwise CF=0 and the data in the destination 
operand will be returned as zeros for th e specified width. All other flags are forced to 0 in either situation. Software 
must check the state of CF=1 for determining if a valid random seed value has been returned, otherwise it is 
expected to loop and retry execution of RDSEED (see Section 1.2).
The RDSEED instruction is available at all privilege levels . The RDSEED instruction executes normally either inside 
or outside a transaction region.
In 64-bit mode, the instruction's default operand size is 32 bits. Using a REX prefix in the form of REX.B permits

In 64-bit mode, the instruction's default operand size is 32 bits. Using a REX prefix in the form of REX.B permits 
Operation
IF HW_NRND_GEN.ready = 1
THEN 
CASE of
operand size is 64: DEST[63:0] := HW_NRND_GEN.data;operand size is 32: DEST[31:0] := HW_NRND_GEN.data;operand size is 16: DEST[15:0] := HW_NRND_GEN.data;
ESAC;CF := 1;
ELSE
CASE of
ESAC;CF := 0;
FI;
OF, SF, ZF, AF, PF := 0;Opcode/
NFx 0F C7 /7
RDSEED r16M V/V RDSEED Read a 16-bit NIST SP800-90B & C compliant random value and 
store in the destination register.
NFx 0F C7 /7
RDSEED r32M V/V RDSEED Read a 32-bit NIST SP800-90B & C compliant random value and 
NFx REX.W + 0F C7 /7
RDSEED r64M V/I RDSEED Read a 64-bit NIST SP800-90B & C compliant random value and 
M ModRM:r/m (w) N/A N/A N/ARDSEED—Read Random SEEDINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-547Flags Affected
The CF flag is set according to the re sult (see the “Operation” section above). The OF, SF, ZF, AF, and PF flags are 
set to 0.
RDSEED int _rdseed16_step( unsigned short * );
RDSEED int _rdseed32_step( unsigned int * );RDSEED int _rdseed64_step( unsigned __int64 *);
If CPUID.(EAX=07H, ECX=0H ):EBX.RDSEED[bit 18] = 0.
If CPUID.(EAX=07H, ECX=0H ):EBX.RDSEED[bit 18] = 0.RDSSPD/RDSSPQ—Read Shadow Stack PointerINSTRUCTION SET REFERENCE, M-U
4-548 Vol. 2BRDSSPD/RDSSPQ—Read Shadow Stack Pointer
Copies the current shadow stack pointer (SSP) register to the register destination. This opcode is a NOP when CET 
shadow stacks are not enabled and on processors that do not support CET.
Operation
IF CPL = 3
IF CR4.CET & IA32_U_CET.SH_STK_EN
IF (operand size is 64 bit)
THEN
Dest := SSP;
ELSE
Dest := SSP[31:0];
FI;
FI;
ELSE
IF CR4.CET & IA32_S_CET.SH_STK_EN
THEN
ELSE
FI;
FI;
FI;
None.
RDSSPD__int32 _rdsspd_i32(void);
RDSSPQ__int64 _rdsspq_i64(void);
F3 0F 1E /1 (mod=11)
RDSSPD r32R V/V CET_SS Copy low 32 bits of shadow stack pointer (SSP) to r32.
F3 REX.W 0F 1E  /1 (mod=11)
RDSSPQ r64R V/N.E. CET_SS Copies shadow stack pointer (SSP) to r64.
R ModRM:r/m (w) N/A N/A N/ARDSSPD/RDSSPQ—Read Shadow Stack PointerINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-549Real-Address Mode Exceptions
None.
None.
None.
None.RDTSC—Read Time-Stamp CounterINSTRUCTION SET REFERENCE, M-U
4-550 Vol. 2BRDTSC—Read Time-Stamp Counter
Reads the current value of the processor’s time-stamp counter (a 64-bit MSR) into the EDX:EAX registers. The EDX 
register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. 
(On processors that support the Intel 64 architecture, the hi gh-order 32 bits of each of RAX and RDX are cleared.)
The processor monotonically increments the time-stamp coun ter MSR every clock cycle and resets it to 0 whenever 
the processor is reset. See “Time Stamp Counter” in Chapter 18 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3B, for specific details of the time stamp counter behavior.
The time stamp disable (TSD) flag in register CR4 restrict s the use of the RDTSC instruction as follows. When the 
flag is clear, the RDTSC instruction can be executed at any privilege level; when the flag is set, the instruction can 
only be executed at privilege level 0.
The time-stamp counter can also be read with the RDMSR instruction, when executing at privilege level 0.The RDTSC instruction is not a serializing instruction. It does not necessarily wait until all previous instructions 
have been executed before reading the counter. Similarly,  subsequent instructions may begin execution before the 
read operation is performed. The following items may guide software seeking to order executions of RDTSC:
•If software requires RDTSC to be executed only after a ll previous instructions have executed and all previous 
loads are globally visible,1 it can execute LFENCE immediately before RDTSC.
loads and stores are globally visible, it can execut e the sequence MFENCE;LFENC E immediately before RDTSC.
•If software requires RDTSC to be executed prior to execution of any subsequent instruction (including any 
memory accesses), it can execute the sequence LFENCE immediately after RDTSC.
This instruction was introduced by the Pentium processor.See “Changes to Instruction Behavior in VMX No n-Root Operation” in Chapter 26 of the Intel
Operation
IF (CR4.TSD = 0) or (CPL  = 0) or (CR0.PE = 0) 
THEN EDX:EAX := TimeStampCounter;ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
#GP(0);
FI;
None.Opcode* Instruction Op/ 
En64-Bit 
0F 31 RDTSC ZO Valid Valid Read ti me-stamp counte r into EDX:EAX.
1. A load is considered to become  globally visible when the value to be loaded is determined.RDTSC—Read Time-Stamp CounterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-551Protected Mode Exceptions
#GP(0) If the TSD flag in register CR4 is set and the CPL is greater than 0.
#GP(0) If the TSD flag in register CR4 is set.
Same exceptions as in protected mode.RDTSCP—Read Time-Stamp Counter and Processor IDINSTRUCTION SET REFERENCE, M-U
4-552 Vol. 2BRDTSCP—Read Time-Stamp Counter and Processor ID
Reads the current value of the processor’s time-stamp coun ter (a 64-bit MSR) into the EDX:EAX registers and also 
reads the value of the IA32_TSC_AUX MSR (address C0000103H) into the ECX register. The EDX register is loaded 
with the high-order 32 bits of the IA32_TSC MSR; the EAX register is loaded with the low-order 32 bits of the 
IA32_TSC MSR; and the ECX register is loaded with th e low-order 32-bits of IA32_TSC_AUX MSR. On processors 
that support the Intel 64 architecture, the high-order 32 bits of each of RAX, RDX, and RCX are cleared.
The time stamp disable (TSD) flag in register CR4 restrict s the use of the RDTSCP instruction as follows. When the 
flag is clear, the RDTSCP instruction can be executed at an y privilege level; when the flag  is set, the instruction can 
The RDTSCP instruction is not a serializing instruction, but it  does wait until all previous instructions have executed 
and all previous loads are globally visible.1 But it does not wait for previous stores to be globally visible, and subse-
quent instructions may begin execution before the read operation is performed. The following items may guide 
software seeking to order executions of RDTSCP:
•If software requires RDTSCP to be executed only after all previous stores are globally visible, it can execute 
MFENCE immediately before RDTSCP.
•If software requires RDTSCP to be executed prior to execution of any subsequent instruction (including any 
memory accesses), it can execute LFENCE immediately after RDTSCP.

Operation
THEN 
EDX:EAX := TimeStampCounter;ECX := IA32_TSC_AUX[31:0];
ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
#GP(0);
FI;
En64-Bit 
0F 01 F9 RDTSCP ZO Valid Valid Read 64-bit time-stamp counter and 
IA32_TSC_AUX value into EDX:EAX and ECX.
1. A load is considered to become  globally visible when the value to be loaded is determined.RDTSCP—Read Time-Stamp Counter and Processor IDINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-553Protected Mode Exceptions
If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.
#GP(0) If the TSD flag in register CR4 is set.#UD If the LOCK prefix is used.
Same exceptions as in protected mode.REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation PrefixINSTRUCTION SET REFERENCE, M-U
4-554 Vol. 2BREP/REPE/REPZ/REPNE/REPNZ—Rep eat String Operation Prefix
En64-Bit 
F3 6C REP INS m8, DX ZO Valid Valid Input (E)C X bytes from port DX into ES:[(E)DI].
F3 6C REP INS m8, DX ZO Valid N.E. Input RCX bytes from port DX into [RDI].
F3 6D REP INS m16, DX ZO Valid Valid Input (E)CX words from port DX into ES:[(E)DI.]
F3 6D REP INS m32, DX ZO Valid Valid Input (E)CX doublewords from port DX into 
ES:[(E)DI].
F3 6D REP INS r/m32, DX ZO Valid N.E. Input RC X default size from port DX into [RDI].
F3 A4 REP MOVS m8, m8 ZO Valid Valid Move (E)C X bytes from DS:[(E)SI] to ES:[(E)DI].
F3 REX.W A4 REP MOVS m8, m8 ZO Valid N.E . Move RCX bytes from [RSI] to [RDI].
F3 A5 REP MOVS m16, m16 ZO Valid Valid Move (E )CX words from DS:[(E)SI] to ES:[(E)DI].
F3 A5 REP MOVS m32, m32 ZO Valid Valid Mov e (E)CX doublewords fr om DS:[(E)SI] to 
F3 REX.W A5 REP MOVS m64, m64 ZO Valid N.E. Move RCX quadwords fr om [RSI] to [RDI].
F3 6E REP OUTS DX, r/m8 ZO Vali d Valid Output (E)CX bytes from  DS:[(E)SI] to port DX.
F3 REX.W 6E REP OUTS DX, r/m81ZO Valid N.E. Output RCX bytes from [RSI] to port DX.
F3 6F REP OUTS DX, r/m16 ZO Valid Valid Output (E)CX words from DS:[(E)SI] to port DX.
F3 6F REP OUTS DX, r/m32 ZO Valid Valid Outpu t (E)CX doublewords fr om DS:[(E)SI] to 
port DX.
F3 REX.W 6F REP OUTS DX, r/m32 ZO Valid N.E. Output  RCX default size from  [RSI] to port DX.
F3 AC REP LODS AL ZO Valid Valid Load (E)CX bytes from DS:[(E)SI] to AL.F3 REX.W AC REP LODS AL ZO Valid N.E. L oad RCX bytes from [RSI] to AL.
F3 AD REP LODS AX ZO Valid Valid Load (E )CX words from DS:[(E)SI] to AX.
F3 AD REP LODS EAX ZO Valid Valid Load (E )CX doublewords from DS:[(E)SI] to 
EAX.
F3 REX.W AD REP LODS RAX ZO Valid N.E. Lo ad RCX quadwords fr om [RSI] to RAX.
F3 AA REP STOS m8 ZO Valid Valid Fill (E)CX bytes at  ES:[(E)DI] with AL.
F3 REX.W AA REP STOS m8 ZO Valid N.E. F ill RCX bytes at [RDI] with AL.
F3 AB REP STOS m16 ZO Valid  Valid Fill (E)CX words at  ES:[(E)DI] with AX.
F3 AB REP STOS m32 ZO Valid Valid Fill (E)CX doublewords at ES:[(E)DI] with EAX.
F3 REX.W AB REP STOS m64 ZO Valid N.E. Fill RCX quadwords at [RDI] with RAX.F3 A6 REPE CMPS m8, m8 ZO Valid Valid Find nonmatching bytes in ES:[(E)DI] and 
DS:[(E)SI].
F3 REX.W A6 REPE CMPS m8, m8 ZO Valid N.E. Fin d non-matching bytes in [RDI] and [RSI].
F3 A7 REPE CMPS m16, m16 ZO Valid Valid Find nonmatching words in ES:[(E)DI] and 
F3 A7 REPE CMPS m32, m32 ZO Valid Valid Find nonmatching doublewords in ES:[(E)DI] 
and DS:[(E)SI].
F3 REX.W A7 REPE CMPS m64, m64 ZO Valid N.E. Find non-matching quadwords in [RDI] and 
[RSI].
F3 AE REPE SCAS m8 ZO Valid Valid Find no n-AL byte starting at ES:[(E)DI].
F3 REX.W AE REPE SCAS m8 ZO Valid N.E. F ind non-AL byte starting at [RDI].
F3 AF REPE SCAS m16 ZO Valid Valid Find non-AX word starting at ES:[(E)DI].
F3 AF REPE SCAS m32 ZO Valid Valid Fin d non-EAX doubleword starting at 
ES:[(E)DI].REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation PrefixINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-555Instruction Operand Encoding
Repeats a string instruction the number of times specified in the count register or until the indicated condition of 
the ZF flag is no longer met. The REP (repeat), REPE (repeat while equal), REPNE (repeat while not equal), REPZ 
(repeat while zero), and REPNZ (repeat while not zero) mn emonics are prefixes that can be added to one of the 
string instructions. The REP prefix can be added to the INS, OUTS, MOVS, LODS, and STOS instructions, and the REPE, REPNE, REPZ, and REPNZ prefixes  can be added to the CMPS and SCAS instructions. (The REPZ and REPNZ 
prefixes are synonymous forms of the REPE and REPNE prefixes, respectively.)  The F3H prefix is defined for the 
following instructions and undefined for the rest:
•F3H as REP/REPE/REPZ for string and input/output instruction.
•F3H is a mandatory prefix for POPCNT, LZCNT, and ADOX.
The REP prefixes apply only to one string instruction at a time. To repeat a block of instructions, use the LOOP 
instruction or another looping construct. All of these repeat prefixes cause the associated instruction to be 
repeated until the count in register is decremented to 0. See Table 4-17.F3 REX.W AF REPE SCAS m64 ZO Valid N.E. Find  non-RAX quadword starting at [RDI].
F2 A6 REPNE CMPS m8, m8 ZO Valid Valid Find matc hing bytes in ES:[(E )DI] and DS:[(E)SI].
F2 REX.W A6 REPNE CMPS m8, m8 ZO Valid N.E. F ind matching bytes in [RDI] and [RSI].
F2 A7 REPNE CMPS m16, m16 ZO Valid Valid Find matching words in ES:[(E)DI] and 
F2 A7 REPNE CMPS m32, m32 ZO Valid Valid Find matching doublewords in ES:[(E)DI] and 
F2 REX.W A7 REPNE CMPS m64, m64 ZO Valid N.E. Fi nd matching doubleword s in [RDI] and [RSI].
F2 AE REPNE SCAS m8 ZO Valid Valid Find AL, starting at ES:[(E)DI].F2 REX.W AE REPNE SCAS m8 ZO Valid N.E. Find AL, starting at [RDI].F2 AF REPNE SCAS m16 ZO Valid Valid Find AX, starting at ES:[(E)DI].F2 AF REPNE SCAS m32 ZO Valid Valid F ind EAX, starting at ES:[(E)DI].
F2 REX.W AF REPNE SCAS m64 ZO Valid N.E. Find RAX, starting at [RDI].
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.
Table 4-17.  Repeat Prefixes
Repeat Prefix Termination Condit ion 1* Termination Condition 2
REP RCX or (E)CX = 0 None
REPE/REPZ RCX or (E)CX = 0Z F  = 0
REPNE/REPNZ RCX or (E)CX = 0 ZF = 1
NOTES:
* Count register is CX, ECX or RCX by default, depending on attributes of the operating modes.Opcode Instruction Op/ 
En64-Bit 
Leg ModeDescriptionREP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation PrefixINSTRUCTION SET REFERENCE, M-U
4-556 Vol. 2BThe REPE, REPNE, REPZ, and RE PNZ prefixes also check the state of the ZF flag after each iteration and terminate 
the repeat loop if the ZF flag is not in the specified st ate. When both termination conditions are tested, the cause 
of a repeat termination can be determined either by testin g the count register with a JECXZ instruction or by testing 
the ZF flag (with a JZ, JNZ, or JNE instruction).
When the REPE/REPZ and REPNE/REPNZ pref ixes are used, the ZF flag does not require initialization because both 
the CMPS and SCAS instructions affect  the ZF flag according to the results of the comparisons they make.
A repeating string operation can be suspended by an exce ption or interrupt. When this happens, the state of the 
registers is preserved to allow the string operation to be  resumed upon a return from  the exception or interrupt 
handler. The source and destination registers point to the ne xt string elements to be operated on, the EIP register 
points to the string instruction, and the ECX register has the value it held following the last successful iteration of 
the instruction. This mechanism allows long string operations to proceed wi thout affecting the interrupt response 
time of the system.
When a fault occurs during the execution of a CMPS or SC AS instruction that is prefixed with REPE or REPNE, the 
EFLAGS value is restored to the state prior to the execut ion of the instruction. Since the SCAS and CMPS instruc-
tions do not use EFLAGS as an input, the processor ca n resume the instruction after the page fault handler.
Use the REP INS and REP OUTS instructions with caution.  Not all I/O ports can handle the rate at which these

Use the REP INS and REP OUTS instructions with caution.  Not all I/O ports can handle the rate at which these 
instructions execute. Note that a REP STOS instruction is the fastest way to initialize a large block of memory.
In 64-bit mode, the operand size of the count register is a ssociated with the address size attribute. Thus the default 
count register is RCX; REX.W has no effect on the address size and the count register. In 64-bit mode, if 67H is used 
to override address size attribute, the count register is ECX and any implicit source/destination operand will use the 
corresponding 32-bit index register. See the summary chart at the beginning of this section for encoding data and 
limits.
REP INS may read from the I/O port without writing to the memory location if an exception or VM exit occurs due 
to the write (e.g., #PF). If this would be problematic, fo r example because the I/O port read has side-effects, soft-
ware should ensure the write to the memory loca tion does not cause an exception or VM exit.
Operation
IF AddressSize = 16
    THEN        Use CX for CountReg;        Implicit Source/Des t operand for memory use of SI/DI;
    ELSE IF AddressSize = 64        THEN Use RCX for CountReg;         Implicit Source/Dest operand for memory use of RSI/RDI;
    ELSE        Use ECX for CountReg;        Implicit Source/Dest operand for memory use of ESI/EDI;
FI;WHILE CountReg 
≠ 0
DO
Service pending interrupts (if any);Execute associated string instruction;CountReg := (CountReg – 1);IF CountReg =
 0
THEN exit WHILE loop; FI;
IF (Repeat prefix is REPZ or REPE) and (ZF  = 0)
or (Repeat prefix is RE PNZ or REPNE) and (ZF = 1)
OD;
None; however, the CMPS and SCAS instructions do  set the status flags in the EFLAGS register.REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation PrefixINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-557Exceptions (All Operating Modes)
Exceptions may be generated by an instruction associated with the prefix.
#GP(0) If the memory address is in a non-canonical form.RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
4-558 Vol. 2BRET—Return From Procedure
Transfers program control to a return address located on th e top of the stack. The address is usually placed on the 
stack by a CALL instruction, and the return is made to the instruction that follows the CALL instruction.
The optional source operand specifies the number of stack by tes to be released after the return address is popped; 
the default is none. This operand can be used to release pa rameters from the stack that were passed to the called 
procedure and are no longer needed. It must be used when  the CALL instruction used to switch to a new procedure 
uses a call gate with a non-zero word count to access the new procedure. Here, the source operand for the RET 
instruction must specify the same number of bytes as is  specified in the word count field of the call gate.
The RET instruction can be used to execute three different types of returns:
•Near return  — A return to a calling procedure within the current code segment (the segment currently pointed 
to by the CS register), sometimes referred to as an intrasegment return.
•Far return  — A return to a calling procedure located in a different segment than the current code segment, 
sometimes referred to as an intersegment return.
•Inter-privilege-level far return  — A far return to a different privile ge level than that of the currently 
executing program or procedure.
The inter-privilege-level return type can only be executed  in protected mode. See the section titled “Calling Proce-
dures Using Call and RET” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1, for detailed information on near, far, and inter-privilege-level returns.
When executing a near return, the processor pops the return instruction pointer (offset) from the top of the stack 
into the EIP register and begins program execution at th e new instruction pointer. Th e CS register is unchanged. 
When executing a far return, the processor pops the return instruction pointer from the top of the stack into the EIP 
register, then pops the segment selector from the top of the stack into the CS register. The processor then begins 
program execution in the new code segment at the new instruction pointer.
The mechanics of an inter-privilege-level far return are sim ilar to an intersegment return, except that the processor 
examines the privilege levels and access rights of the code  and stack segments being returned to determine if the 
control transfer is allowed to be made. The DS, ES, FS, an d GS segment registers are cleared by the RET instruction 
during an inter-privilege-level return if they refer to se gments that are not allowed to be accessed at the new priv-
ilege level. Since a stack switch also occurs on an inter- privilege level return, the ESP and SS registers are loaded 
from the stack. 
If parameters are passed to the called procedure during an  inter-privilege level call, the optional source operand 
must be used with the RET instruction to release the para meters on the return. Here, the parameters are released 
both from the called procedure’s stack and the calling procedure’s stack (that is, the stack being returned to).
In 64-bit mode, the default operation size of this instruct ion is the stack-address size, i.e., 64 bits. This applies to 
near returns, not far returns; the default operation size of far returns is 32 bits.Opcode* Instruction Op/
En64-Bit 
C3 RET ZO Valid Valid Near retu rn to calling procedure.
CB RET ZO Valid Valid Far retu rn to calling procedure.
C2 iw RET imm16 I Valid Valid Near return to calling procedure and pop 
imm16 bytes from stack.
CA iw RET imm16 I Valid Valid Far return to calling procedure and pop imm16 
bytes from stack.
Ii m m 1 6 N / A N / A N / ARET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-559Refer to Chapter 6, “Procedure Call s, Interrupts, and Exceptions‚” and Chapter 17, “Control-flow Enforcement 
details.
Instruction ordering.  Instructions following a far return may be fe tched from memory before earlier instructions 
complete execution, but they will not execute (even speculatively) until all instructions prior to the far return have 
Unlike near indirect CALL and near indirect JMP, the processor will not speculatively execute the next sequential 
instruction after a near RET unless that instruction is also th e target of a jump or is a target in a branch predictor.
Operation
(* Near return *)
IF instruction =  near return 
THEN;
THEN
IF top 4 bytes of stack not within stack limits
EIP := Pop();IF ShadowStackEnabled(CPL)
tempSsEIP = ShadowStackPop4B();IF EIP != TempSsEIP
THEN #CP(NEAR_RET); FI;
FI;
ELSE
THEN
IF top 8 bytes of stack not within stack limits
RIP := Pop();IF ShadowStackEnabled(CPL)
tempSsEIP = ShadowStackPop8B();IF RIP != tempSsEIP
FI;
 = 16 *)
IF top 2 bytes of stack not within stack limits
tempEIP := Pop();tempEIP := tempEIP AND 0000FFFFH;IF tempEIP not within  code segment limits
EIP := tempEIP;IF ShadowStackEnabled(CPL)
tempSsEip = ShadowStackPop4B();IF EIP != tempSsEIP
FI;
FI;
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
IF StackAddressSize
 = 32RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
4-560 Vol. 2BTHEN 
ESP := ESP + SRC;
ELSE
IF StackAddressSize = 64
THEN 
RSP := RSP + SRC;
ELSE (* StackAddressSize = 16 *)
SP := SP + SRC;
FI;
FI;
FI;
FI;
(* Real-address mode or virtual-8086 mode *)
IF ((PE = 0) or (PE = 1 AND VM = 1)) and instruction =  far return
THEN
THEN
EIP := Pop(); CS := Pop(); (* 32-bit pop, high-order 16 bits discarded *)
tempEIP := Pop(); tempEIP := tempEIP AND 0000FFFFH;IF tempEIP not within  code segment limits
EIP := tempEIP;CS := Pop(); (* 16-bit pop *)
FI;
IF instruction has immediate operand 
SP := SP + (SRC AND FFFFH);
FI;
FI;
(* Protected mode, not virtual-8086 mode *)
IF (PE = 1 and VM
 = 0 and IA32_EFER.LMA = 0) and instruction =  far return
THEN
THEN 
IF second doubleword on stac k is not within stack limits
IF second word on stack is not within stack limits
FI;
IF return code segm ent selector is NULL

THEN
THEN
FI;
FI;
FI;
THEN
THEN 
FI;
IF return code segment sele ctor addresses descriptor be yond descriptor table limit 
Obtain descriptor to which return code segment selector points from descriptor table;RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-561IF return code segment descriptor is not a code segment
IF return code segment selector RPL < CPL
IF return code segment descriptor is conformingand return code segment DPL > return code segment selector RPL
IF return code segment descriptor is non-conforming and return code 
segment DPL 
≠ return code segm ent selector RPL
IF return code segment descriptor is not present
THEN #NP(selector); FI:
IF return code segment selector RPL > CPL 
ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL;
FI;
FI; 
RETURN-TO-SAME-PRIVILEGE-LEVEL:
IF the return instruction pointer is no t within the return code segment limit 
THEN
EIP := Pop();CS := Pop(); (* 32-bit pop, high-order 16 bits discarded *)
= 16 *)
EIP := Pop();EIP := EIP AND 0000FFFFH;CS := Pop(); (* 16-bit pop *)
FI;IF instruction has immediate operand
 = 32
THEN 
FI;
(* SSP must be 8 byte aligned *)IF SSP AND 0x7 != 0
prevSSP = shadow_stack_l oad 8 bytes from SSP;
SSP = SSP + 24;(* do a 64 bit-compare to check if any bits beyond bit 15 are set *)tempCS = CS; (* zero pad to 64 bit *)IF tempCS != tempSsCS
(* do a 64 bit-compare; pad CSBASE+RIP with 0 for 32 bit LIP*)IF CSBASE + RIP != tempSsLIP
THEN #CP(FAR-RET/IRET); FI;RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
4-562 Vol. 2B(* prevSSP must be 4 byte aligned *)
IF prevSSP AND 0x3 != 0
(* In legacy mode SSP must be in low 4GB *)IF prevSSP[63:32] != 0
SSP := prevSSP
FI;
IF top (16 + SRC) bytes of stack are not wi thin stack limits (OperandSize 
= 32) 
or top (8 + SRC) bytes of stack are not wi thin stack limits (OperandSize = 16)
Read return segment selector;IF stack segment selector is NULL
IF return stack segment selector index is  not within its descriptor table limits
Read segment descriptor pointed to by return segment selector;IF stack segment selector RPL 
≠ RPL of the return code segment selector
or stack segment is not a writable data segment
or stack segment descriptor DPL ≠ RPL of the return code segment selector
IF stack segment not present
THEN #SS(StackSegmentSelector); FI;
IF the return instruction pointer is no t within the return code segment limit
THEN
EIP := Pop();CS := Pop(); (* 32-bit pop, high-order 16 bits discarded; segment descriptor loaded *)
CS(RPL) := ReturnCodeSegmentSelector(RPL);IF instruction has immediate operand
THEN (* Release parameters from called procedure’s stack *)
 = 32
THEN 
FI;
FI;tempESP := Pop();tempSS := Pop(); (* 32-bit pop, high-order 16 bits discarded; seg. descriptor loaded *)
= 16 *)
EIP := Pop();EIP := EIP AND 0000FFFFH;CS := Pop(); (* 16-bit pop; segment descriptor loaded *)CS(RPL) := ReturnCodeSegmentSelector(RPL);IF instruction has immediate operand
 = 32
THEN 
ELSE (* StackAddressSize = 16 *)RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-563SP := SP + SRC;
FI;
FI;tempESP := Pop();tempSS := Pop(); (* 16-bit pop; segment descriptor loaded *)
FI;
IF ReturnCodeSegmentSelector(RPL) !=3
THEN
tempCS = CS; (* zero extended to 64 bit *)IF tempCS != tempSsCS
(* Do 64 bit compare; pad CSBASE +RIP with 0 for 32 bit LA *)
IF CSBASE + RIP != tempSsLIP
FI;
FI;
tempOldCPL = CPL;
CPL := ReturnCodeSegmentSelector(RPL);
ESP := tempESP;SS := tempSS;tempOldSSP = SSP;IF ShadowStackEnabled(CPL)
IF CPL = 3
IF tempSSP[63:32] != 0
SSP := tempSSP
FI;(* Now past all faulting points; safe to free th e token. The token free is  done using the old SSP
new_token_value = tempOldSSP                      (* clear the busy bit *)
FI;
FI;
FOR each SegReg in (ES, FS, GS, and DS)
DO
tempDesc := descriptor cache for SegReg (* hidden part of segment register *)IF (SegmentSelector == NULL) OR (tempDesc(DPL) < CPL AND tempDesc(Type) is (data or non-conforming code)))RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
4-564 Vol. 2BTHEN (* Segment register invalid *)
FI;
OD;
THEN (* Release parameters fr om calling procedure’s stack *)
THEN 
FI;
FI;
(* IA-32e Mode *)
IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 1) and instruction = far return
THEN
THEN 
IF first or second doubleword on  stack is not in canonical space
ELSE 
THEN
IF first or second word on stack is not in canonical space
ELSE (* OperandSize  = 64 *)
IF first or second quadword on stack is not in canonical space 
FI
FI;
IF return code segment selector addresses descriptor beyond descriptor table limit 
THEN GP(selector); FI;
IF return code segment selector addresses descriptor in non-canonical space
Obtain descriptor to which return code segment selector points from descriptor table;IF return code segment descri ptor is not a code segment 
IF return code segment descriptor has L-bit = 1 and D-bit = 1 
IF return code segment selector RPL < CPL 
IF return code segment descriptor is non-conformingand return code segment DPL 
≠ return code segment selector RPLRET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-565THEN #GP(selector); FI;
IF return code segment de scriptor is not present 
THEN GOTO IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL;ELSE GOTO IA-32E-MODE-RETU RN-TO-SAME-PRIVILEGE-LEVEL;
FI; 
FI;
IA-32E-MODE-RETURN-TO- SAME-PRIVILEGE-LEVEL:
IF the return instruction pointer is not within canonical address space
 = 32
THEN
ELSE 
THEN
= 64 *)
RIP := Pop();CS := Pop(); (* 64-bit pop, high-order 48 bits discarded *)
FI;
FI; IF instruction has immediate operand
 = 32
THEN 
ELSE
IF StackAddressSize = 16
THEN
ELSE (* StackAddressSize = 64 *)
FI;
FI;
IF tempCS != tempSsCS (*  64 bit compare; CS zero  padded to 64 bits *)

 = 32
THEN
ELSE 
THEN
= 64 *)
FI;
 = 32
THEN 
ELSE
THEN
FI;
FI;
IF CSBASE + RIP != tempSs LIP (* 64 bit compare *)RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
4-566 Vol. 2BTHEN #CP(FAR-RET/IRET); FI;
IF (CS.L = 0 AND tempSSP[63:32] != 0) OR
(CS.L = 1 AND tempSSP is not canonical relative to the cu rrent paging mode)
FI;
IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL:
IF top (16 + SRC) bytes of stack are not with in stack limits (OperandSize =  32) 
or top (8 + SRC) bytes of stack are not with in stack limits (OperandSize =  16)
IF top (16 + SRC) bytes of stack are not in canonical address space (OperandSize =32) 
or top (8 + SRC) bytes of stack are not in cano nical address space (OperandSize = 16)
or top (32 + SRC) bytes of stack are not in canonical address space (OperandSize = 64)
Read return stack segment selector;IF stack segment selector is NULL
THEN
IF new CS descriptor L-bit = 0 
IF stack segment selector RPL = 3
FI;IF return stack segment descriptor is  not within descri ptor table limits
IF return stack segment descriptor is in non-canonical address space
IF stack segment not present 
IF the return instruction pointer is not within canonical address space 
THEN
EIP := Pop();CS := Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
 = 32
THEN 
ELSE
THEN
SP := SP + SRC;RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-567ELSE (* StackAddressSize = 64 *)
FI;
FI;
FI;tempESP := Pop();tempSS := Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
ELSE 
THEN
EIP := Pop();EIP := EIP AND 0000FFFFH;CS := Pop(); (* 16-bit pop;  segment descriptor loaded *)
 = 32
THEN 
ELSE
THEN
FI;
FI;
= 64 *)
RIP := Pop();CS := Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. descriptor loaded *)CS(RPL) := ReturnCodeSegmentSelector(RPL);IF instruction has immediate operand
FI;tempESP := Pop();tempSS := Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. desc. loaded *)
FI;
FI;
THEN
tempSSP = shadow_stack_load 8 bytes from SSP;SSP = SSP + 24;(* Do 64 bit compare to detect bits beyond 15 being set *)RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
4-568 Vol. 2BtempCS = CS; (* zero padded to 64 bit *)
FI;
FI;tempOldCPL = CPL;CPL := ReturnCodeSegmentSelector(RPL);ESP := tempESP;SS := tempSS;tempOldSSP = SSP;IF ShadowStackEnabled(CPL)
IF CPL = 3
FI;(* Now past all faulting points; safe to free th e token. The token free is done using the old SSP
* and using a supervisor override as old CPL was a supervisor privilege level *)IF ShadowStackEnabled(tempOldCPL)
expected_token_value = tempOldSSP | BUSY_BIT  (* busy bit - bit positi on 0 - must be set *)
shadow_stack_lock_cm pxchg8b(tempOldSSP, new_token_value, expected_token_value)
FI;
FOR each of segment register (ES, FS, GS, and DS)
DO
IF segment register poin ts to data or non-co nforming code segment
and CPL > segment descriptor DPL; (* DPL in hidden part of segment register *)
THEN SegmentSelector := 0; (* SegmentSelector invalid *)
FI;
OD;
 = 32
THEN 
ELSE
THEN
FI;
FI;
FI;RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-569Flags Affected
None.
If the return instruction pointer is not within the return code segment limit.If returning to 32-bit or compatibility mode and the previous SSP from shadow stack (when 
#GP(selector) If the RPL of the return code segment selector is less then the CPL.
If the return code or stack segment selector index is not within its descriptor table limits.
If the return code segment descripto r does not indicate a code segment.
If the return code segment is non-conforming and the segment selector’s DPL is not equal to 
the RPL of the code segment’s segment selector
If the return code segment is conforming and the segment selector’s DPL greater than the RPL 
of the code segment’s segment selector
If the stack segment is not a writable data segment.
If the stack segment descriptor DPL is not eq ual to the RPL of the return code segment 
selector.
#NP(selector) If the return code segment is not present.
#PF(fault-code) If a page fault occurs.#AC(0) If an unaligned memory access occurs when the CPL is 3 and alignment checking is enabled.
#CP(Far-RET/IRET) If the previous SSP from shadow st ack (when returning to CPL <3) or from IA32_PL3_SSP 
#GP If the return instruction pointer is not within the return code segment limit #SS If the top bytes of stack are not within stack limits.
#GP(0) If the return instruction pointer is not within the return code segment limit #SS(0) If the top bytes of stack are not within stack limits.
#AC(0) If an unaligned memory access occurs  when alignment checking is enabled.
Same as 64-bit mode exceptions.RET—Return From ProcedureINSTRUCTION SET REFERENCE, M-U
4-570 Vol. 2B64-Bit Mode Exceptions
#GP(0) If the return instruction pointer is non-canonical.
If a NULL stack segment selector RPL is not equal to CPL going back to non-CPL3 64-bit mode.If the return code segment selector is NULL.
#GP(selector) If the proposed segment descriptor for a code  segment does not indicate it is a code segment. 
If the proposed new code segment descriptor has both the D-bit and L-bit set.
selector.
If CPL is greater than the RPL of the code segment selector.
RPL.
If a segment selector index is outside its descriptor table limits.If a segment descriptor memory address is non-canonical.
selector.

selector.
RPL.
selector.
If the stack segment selector RPL is not equal to  the RPL of the return code segment selector. 
#NP(selector) If the return code or stack segment is not present.
If return instruction pointer from stack and shadow stack do not match.RORX — Rotate Right Logical Without Affecting FlagsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-571RORX — Rotate Right Logical Without Affecting Flags
Rotates the bits of second operand right by the count valu e specified in imm8 without affecting arithmetic flags. 
The RORX instruction does not read or write the arithmetic flags.
Operation
IF (OperandSize = 32)
y := imm8 AND 1FH;DEST := (SRC >> y) | (SRC << (32-y));
ELSEIF (OperandSize = 64 ) 
y := imm8 AND 3FH;DEST := (SRC >> y) | (SRC << (64-y));
FI;
None.
None.
See Table 2-29, “Type 13 Class Exception Conditions.”Opcode/
En64/32-
VEX.LZ.F2.0F3A.W0 F0 /r ib
RORX r32, r/m32, imm8RMI V/V BMI2 Rotate 32-bit r/m32 right im m8 times without affecting arithmetic 
flags.
VEX.LZ.F2.0F3A.W1 F0 /r ib
RORX r64, r/m64, imm8RMI V/N.E. BMI2 Rotate 64-bit r/m64 right imm8 times without affecting arithmetic 
flags.
RMI ModRM:reg (w) ModRM:r/m (r) imm8 N/AROUNDPD—Round Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-572 Vol. 2BROUNDPD—Round Packed Double Pr ecision Floating-Point Values
Round the 2 double precision floating-point values in the source operand (second operand) using the rounding 
mode specified in the immediate operan d (third operand) and place the results in the destination operand (first 
operand). The rounding process rounds each input floating-point value to an integer value and returns the integer 
result as a double precision floating-point value. 
The immediate operand specifies control fields for the roundi ng operation, three bit fields are defined and shown in 
Figure 4-24. Bit 3 of the immediate byte controls processo r behavior for a precision exception, bit 2 selects the 
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded 
values for rounding-mode field). 
The Precision Floating-Point Exception is signaled accordin g to the immediate operand. If any source operand is an 
SNaN then it will be converted to a QNaN. If DAZ is se t to ‘1 then denormals will be converted to zero before 
rounding.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-
tion is not distinct from the first source XMM register and the upper bits (MAXVL-1:1 28) of the corresponding YMM 
register destination are unmodified.
VEX.128 encoded version: the source operand second so urce operand or a 128-bit memory location. The destina-
tion operand is an XMM register. The upper bits (MAXVL-1 :128) of the corresponding YMM register destination are 
zeroed.
VEX.256 encoded version: The source operand is a YMM re gister or a 256-bit memory  location. The destination 
Note: In VEX-encoded versions, VEX.v vvv is reserved and must be 1111b, otherwise instructions will #UD.Opcode*/
Mode 
Feature 
66 0F 3A 09 /r ib
ROUNDPD xmm1, xmm2/m128, imm8RMI V/V SSE4_1 Round packed double precision floating-point 
values in xmm2/m128 and place the result in 
xmm1. The rounding mode is determined by 
imm8.
VEX.128.66.0F3A.WIG 09 /r ib
VROUNDPD xmm1, xmm2/m128, imm8RMI V/V AVX Round packed double precision floating-point 
imm8.
VEX.256.66.0F3A.WIG 09 /r ib
VROUNDPD ymm1, ymm2/m256, imm8RMI V/V AVX Round packed double precision floating-point 
values in ymm2/m256 and place the result in 
ymm1. The rounding mode is determined by 
imm8.
Vol. 2B 4-573Operation
IF (imm[2] = ‘1) 
THEN // rounding mode is determined by MXCSR.RC 
DEST[63:0] := ConvertDPFPToInteger_M(SRC[63:0]);DEST[127:64] := ConvertDPFPToInteger_M(SRC[127:64]);
ELSE // rounding mode is determined by IMM8.RC
DEST[63:0] := ConvertDPFPToInteger_Imm(SRC[63:0]);DEST[127:64] := ConvertDPFPToInteger_Imm(SRC[127:64]);
FI
ROUNDPD (128-bit Legacy SSE Version)
DEST[63:0] := RoundToInteger (SRC[63:0]], ROUND_CONTROL)
DEST[127:64] := RoundToInteger (SRC[127:64]], ROUND_CONTROL)
VROUNDPD (VEX.128 Encoded Version)
VROUNDPD (VEX.256 Encoded Version)
DEST[63:0] := RoundToInteger(SRC[63:0], ROUND_CONTROL)
DEST[191:128] := RoundToInteger(SRC[191:128]], ROUND_CONTROL)DEST[255:192] := RoundToInteger(SRC[255:192] ], ROUND_CONTROL)Figure 4-24.  Bit Control Fields of Immediate Byte for ROUNDxx Instruction
Table 4-18.  Rounding Modes and Encodi ng of Rounding Control (RC) Field
Rounding 
ModeRC Field 
Round to 
nearest (even)00B Rounded result is the closest to the infinitely precise result. If two values are equally close, the result is 
the even value (i.e., the integer value wi th the least- significant bit of zero). 
Round down 
(toward −∞)01B Rounded result is closes t to but no greater than th e infinitely precise result.
Round up 
zero (Truncate)11B Rounded result is closest to bu t no greater in absolute value th an the infinitely precise result.8
RS — Rounding select; 1: MXCSR.RC, 0: Imm8.RC
RC — Rounding mode3210
P — Precision Mask; 0: normal, 1: inexactReservedROUNDPD—Round Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-574 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
__m128 _mm_round_pd(__m128d s1, int iRoundMode);
__m128 _mm_floor_pd(__m128d s1);__m128 _mm_ceil_pd(__m128d s1)__m256 _mm256_round_pd(__m256d s1, int iRoundMode);__m256 _mm256_floor_pd(__m256d s1);__m256 _mm256_ceil_pd(__m256d s1)
Invalid (signaled only if SRC = SNaN).
Precision (signaled only if imm[3] = ‘0 ; if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and preci-
sion exception is not signaled.)
Note that Denormal is not signaled by ROUNDPD.
See Table 2-19, “Type 2 Class Exception Conditions,” additionally:
#UD If VEX.vvvv ≠ 1111B.ROUNDPS—Round Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-575ROUNDPS—Round Packed Single Pr ecision Floating-Point Values
Round the 4 single precision floating-point values in the source operand (second operan d) using the rounding mode 
specified in the immediate operand (third operand) and plac e the results in the destination operand (first operand). 
The rounding process rounds each input floating-point valu e to an integer value and returns the integer result as a 
single precision floating-point value. 
The immediate operand specifies control fields for the round ing operation, three bit fields are defined and shown in 
rounding.
tion is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM

rounding.
tion is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM 
zeroed.
VEX.256 encoded version: The source operand is a YMM re gister or a 256-bit memory location. The destination 
Operation
DEST[31:0] := ConvertSPFPToInteger_M(SRC[31:0]);DEST[63:32] := ConvertSPF PToInteger_M(SRC[63:32]);
DEST[95:64] := ConvertSPF PToInteger_M(SRC[95:64]);
DEST[127:96] := ConvertSPFPToInteger_M(SRC[127:96]);
ELSE // rounding mode is determined by IMM8.RCOpcode*/
Mode 
Feature 
66 0F 3A 08
/r ib
ROUNDPS xmm1, xmm2/m128, imm8RMI V/V SSE4_1 Round packed single precision floating-point 
imm8.
VEX.128.66.0F3A.WIG 08 /r ib
VROUNDPS xmm1, xmm2/m128, imm8RMI V/V AVX Round packed single precision floating-point 
imm8.
VEX.256.66.0F3A.WIG 08 /r ib
VROUNDPS ymm1, ymm2/m256, imm8RMI V/V AVX Round packed single precision floating-point 
imm8.
RMI ModRM:reg (w) ModRM:r/m (r) imm8 N/AROUNDPS—Round Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-576 Vol. 2BDEST[31:0] := ConvertSPFPToInteger_Imm(SRC[31:0]);
DEST[63:32] := ConvertSPFPToInteger_Imm(SRC[63:32]);DEST[95:64] := ConvertSPFPToInteger_Imm(SRC[95:64]);DEST[127:96] := ConvertSPFPToInteger_Imm(SRC[127:96]);
FI;
ROUNDPS(128-bit Lega cy SSE Version)
DEST[31:0] := RoundToInteger(SRC[31:0], ROUND_CONTROL)DEST[63:32] := RoundToInteger(SRC[63:32], ROUND_CONTROL)DEST[95:64] := RoundToInteger(SRC[95:64]], ROUND_CONTROL)DEST[127:96] := RoundToInteger (SRC[127:96]], ROUND_CONTROL)
VROUNDPS (VEX.128 Encoded Version)
DEST[31:0] := RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] := RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] := RoundToInteger(SRC[95:64]], ROUND_CONTROL)DEST[127:96] := RoundToInteger (SRC[127:96]], ROUND_CONTROL)
VROUNDPS (VEX.256 Encoded Version)
DEST[159:128] := RoundToInteger (SRC[159:128]], ROUND_CONTROL)
DEST[191:160] := RoundToInteger (SRC[191:160]], ROUND_CONTROL)
DEST[223:192] := RoundToInteger (SRC[223:192] ], ROUND_CONTROL)
DEST[255:224] := RoundToInteger (SRC[255:224] ], ROUND_CONTROL)
__m128 _mm_round_ps(__m128 s1, int iRoundMode);
__m128 _mm_floor_ps(__m128 s1);__m128 _mm_ceil_ps(__m128 s1)__m256 _mm256_round_ps(__m256 s1, int iRoundMode);__m256 _mm256_floor_ps(__m256 s1);__m256 _mm256_ceil_ps(__m256 s1)
Note that Denormal is not signaled by ROUNDPS.
#UD If VEX.vvvv ≠ 1111B.ROUNDSD—Round Scalar Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-577ROUNDSD—Round Scalar Double Pr ecision Floating-Point Values
Round the double precision floating-point value in the lo wer qword of the source operand (second operand) using 
the rounding mode specified in the immediate operand (thi rd operand) and place the result in the destination 
operand (first operand). The rounding process rounds a doub le precision floating-point input to an integer value 
and returns the integer result as a double precision floati ng-point value in the lowest position. The upper double 
precision floating-point value in the destination is retained. 
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded values for rounding-mode field). 
rounding.
1:64) of the corresponding YMM destination register remain unchanged.
Operation
DEST[63:0] := ConvertDPFPToInteger_M(SRC[63:0]);
DEST[63:0] := ConvertDPFPToInteger_Imm(SRC[63:0]);
FI;DEST[127:63] remains unchanged ;
ROUNDSD (128-bit Legacy SSE Version)
DEST[63:0] := RoundToInteger(SRC[63:0], ROUND_CONTROL)DEST[MAXVL-1:64] (Unmodified)Opcode*/
Mode 
Feature 
66 0F 3A 0B /r ib
ROUNDSD xmm1, xmm2/m64, imm8RMI V/V SSE4_1 Round the low packed double precision 
floating-point value in xmm2/m64 and place 
the result in xmm1. The rounding mode is 
determined by imm8.
VEX.LIG.66.0F3A.WIG 0B /r ib
VROUNDSD xmm1, xmm2, xmm3/m64, imm8RVMI V/V AVX Round the low packed double precision 
floating-point value in xmm3/m64 and place 
determined by imm8. Upper packed double precision floating-point value (bits[127:64]) 
from xmm2 is copi ed to xmm1[127:64].
RMI ModRM:reg (w) ModRM:r/m (r) imm8 N/A
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8ROUNDSD—Round Scalar Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-578 Vol. 2BVROUNDSD (VEX.128 Encoded Version)
DEST[63:0] := RoundToInteger(SRC2[63:0], ROUND_CONTROL)DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
ROUNDSD __m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode);
ROUNDSD __m128d mm_floor_sd(__m128d dst, __m128d s1);ROUNDSD __m128d mm_ceil_sd(__m128d dst, __m128d s1);
Note that Denormal is not signaled by ROUNDSD.
See Table 2-20, “Type 3 Class Exception Conditions.”ROUNDSS—Round Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-579ROUNDSS—Round Scalar Single Pr ecision Floating-Point Values
Round the single precision floating-point value in the lo west dword of the source operand (second operand) using 
operand (first operand). The rounding process rounds a single  precision floating-point input to an integer value and 
returns the result as a single precision floating-point valu e in the lowest position. The upper three single precision 
floating-point values in the destination are retained. 
rounding.
Operation
DEST[31:0] := ConvertSPFPToInteger_M(SRC[31:0]);
DEST[31:0] := ConvertSPFPToInteger_Imm(SRC[31:0]);
FI;DEST[127:32] remains unchanged ;

rounding.
Operation
ROUNDSS (128-bit Legacy SSE Version)
DEST[31:0] := RoundToInteger(SRC[31:0], ROUND_CONTROL)DEST[MAXVL-1:32] (Unmodified)Opcode*/
Mode 
Feature 
66 0F 3A 0A /r ib
ROUNDSS xmm1, xmm2/m32, imm8RMI V/V SSE4_1 Round the low packed single precision floating-
point value in xmm2/m32 and place the result in 
xmm1. The rounding mode is determined by imm8.
VEX.LIG.66.0F3A.WIG 0A /r ib
VROUNDSS xmm1, xmm2, xmm3/m32, imm8RVMI V/V AVX Round the low packed single precision floating-
point value in xmm3/m32 and place the result in xmm1. The rounding mode is determined by imm8. 
Also, upper packed single precision floating-point 
values (bits[127:32]) from xmm2 are copied to xmm1[127:32].
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8ROUNDSS—Round Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-580 Vol. 2BVROUNDSS (VEX.128 Encoded Version)
DEST[31:0] := RoundToInteger(SRC2[31:0], ROUND_CONTROL)DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
ROUNDSS __m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode);
ROUNDSS __m128 mm_floor_ss(__m128 dst, __m128 s1);ROUNDSS __m128 mm_ceil_ss(__m128 dst, __m128 s1);
Note that Denormal is not signaled by ROUNDSS.
See Table 2-20, “Type 3 Class Exception Conditions.”RSM—Resume From System Management ModeINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-581RSM—Resume From System Management Mode
Returns program control from system management mode (SMM) to the application program or operating-system 
procedure that was interrupted when the processor receiv ed an SMM interrupt. The processor’s state is restored 
from the dump created upon entering SMM. If the proce ssor detects invalid state information during state resto-
ration, it enters the shutdown state. The foll owing invalid information can cause a shutdown:
•Any reserved bit of CR4 is set to 1.
•Any illegal combination of bits in CR0, such as (PG =1 and PE =0) or (NW =1 and CD =0).
•(Intel Pentium and Intel486™ processors only.) The value stored in the state dump base field is not a 32-KByte 
aligned address.
The contents of the model-specific register s are not affected by a return from SMM.
The SMM state map used by RSM supports resuming proc essor context for non-64-bit modes and 64-bit mode. 
See Chapter 32, “System Management Mode,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3C, for more information about SMM and the behavior of the RSM instruction.
Operation
ReturnFromSMM;
IF (IA-32e mode supported) or (CPUID DisplayFamily_ DisplayModel = 06H_0CH )
THEN
ProcessorState := Restore(SM MDump(IA-32e SMM STATE MAP));
Else
ProcessorState := Rest ore(SMMDump(Non-32-Bit-Mode SMM STATE MAP));
FI
All.
#UD If an attempt is made to execute this instruction when the processor is not in SMM.
En64-Bit 
0F AA RSM ZO Valid Valid Resume operation of interrupted program.
ZO N/A N/A N/A N/ARSM—Resume From System Management ModeINSTRUCTION SET REFERENCE, M-U
4-582 Vol. 2B64-Bit Mode Exceptions
Same exceptions as in protected mode.RSQRTPS—Compute Reciprocals of Square Roots of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-583RSQRTPS—Compute Reciprocals of Square Roots of Packed Single Precision Floating-Point 
Values
Performs a SIMD computation of the approximate reciprocals of the square roots of the four packed single precision 
floating-point values in the source operand (second operan d) and stores the packed single precision floating-point 
results in the destination operand. The source operand ca n be an XMM register or a 128-bit memory location. The 
destination operand is an XMM register. See Figure 10-5 in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 1, for an illustration of a SIMD single precision floating-point operation.
The RSQRTPS instruction is not affected by the rounding cont rol bits in the MXCSR register. When a source value is 
a 0.0, an ∞ of the sign of the source value is returned. A deno rmal source value is treated as a 0.0 (of the same 
sign). When a source value is a negative value (other than −0.0), a floating-point indefinite is returned. When a 
source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned. 
zeroed.
Mode 
Feature 
NP 0F 52 /r
RSQRTPS xmm1, xmm2/m128RM V/V SSE Computes the approximate reciprocals of the square 
roots of the packed single precision floating-point 
values in xmm2/m128 and stores the results in xmm1.
VEX.128.0F.WIG 52 /r
VRSQRTPS xmm1, xmm2/m128RM V/V AVX Computes the approximate reciprocals of the square 
roots of packed single precision values in xmm2/mem 
and stores the results in xmm1.
VEX.256.0F.WIG 52 /r
VRSQRTPS ymm1, ymm2/m256RM V/V AVX Computes the approximate reciprocals of the square 
roots of packed single precision values in ymm2/mem 
RM ModRM:reg (w) ModRM:r/m (r) N/A N/ARSQRTPS—Compute Reciprocals of Sq uare Roots of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-584 Vol. 2BOperation
RSQRTPS (128-bit Legacy SSE Version)
DEST[31:0] := APPROXIMATE(1/SQRT(SRC[31:0]))DEST[63:32] := APPROXIMATE(1/SQRT(SRC1[63:32]))DEST[95:64] := APPROXIMATE(1/SQRT(SRC1[95:64]))DEST[127:96] := APPROXIM ATE(1/SQRT(SRC2[127:96]))
VRSQRTPS (VEX.128 Encoded Version)
VRSQRTPS (VEX.256 Encoded Version)
DEST[159:128] := APPROXIM ATE(1/SQRT(SRC2[159:128]))
DEST[191:160] := APPROXIM ATE(1/SQRT(SRC2[191:160]))
DEST[223:192] := APPROXIM ATE(1/SQRT(SRC2[223:192]))
DEST[255:224] := APPROXIM ATE(1/SQRT(SRC2[255:224]))
RSQRTPS __m128 _mm_rsqrt_ps(__m128 a)
RSQRTPS __m256 _mm256_rsqrt_ps (__m256 a);
None.
#UD If VEX.vvvv ≠ 1111B.RSQRTSS—Compute Reciprocal of Square Root of Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-585RSQRTSS—Compute Reciprocal of Square Root of Sc alar Single Precision Floating-Point Value
Computes an approximate reciprocal of the square root of the low single precision floating-point value in the source 
operand (second operand) stores the single precision floati ng-point result in the destination operand. The source 
operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The 
three high-order doublewords of the destination oper and remain unchanged. See Figure 10-6 in the Intel® 64 and 

None.
The RSQRTSS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is 
Operation
RSQRTSS (128-bit Legacy SSE Version)
DEST[31:0] := APPROXIMATE(1/SQRT(SRC2[31:0]))DEST[MAXVL-1:32] (Unmodified)
VRSQRTSS (VEX.128 Encoded Version)
DEST[31:0] := APPROXIMATE(1/SQRT(SRC2[31:0]))DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0Opcode*/
Mode 
Feature 
F3 0F 52 /r
RSQRTSS xmm1, xmm2/m32RM V/V SSE Computes the approximate reciprocal of the square 
root of the low single precision floating-point value in 
xmm2/m32 and stores the results in xmm1.
VEX.LIG.F3.0F.WIG 52 /r
VRSQRTSS xmm1, xmm2, xmm3/m32RVM V/V AVX Computes the approximate reciprocal of the square 
root of the low single precision floating-point value in xmm3/m32 and stores the results in xmm1. Also, 
upper single precision floating-point values 
(bits[127:32]) from xmm2 are copied to 
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/ARSQRTSS—Compute Reciprocal of Square Root of Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-586 Vol. 2BIntel C/C ++ Compiler Intrinsic Equivalent
RSQRTSS __m128 _mm_rsqrt_ss(__m128 a)
None.
See Table 2-22, “Type 5 Class Exception Conditions.”RSTORSSP—Restore Saved Shadow Stack PointerINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-587RSTORSSP—Restore Saved Shadow Stack Pointer
Restores SSP from the shadow-stack-restore token pointed to by m64. If the SSP restore was successful then the 
instruction replaces the shadow-stack-restore token with a previous-ssp token. The instruction sets the CF flag to 
indicate whether the SSP address recorded in the shadow-stack-restore token that was processed was 4 byte aligned, i.e., whether an alignment hole was created wh en the restore-shadow-stack token was pushed on this 
shadow stack. 
Following RSTORSSP if a restore-shadow-stack token need s to be saved on the previous shadow stack, use the 
SAVEPREVSSP instruction. 
If pushing a restore-shadow-stack token on the previous shadow stack is not required, the previous-ssp token can 
be popped using the INCSSPQ instruction. If the CF flag was set to indicate presence of an alignment hole, an addi-
tional INCSSPD instruction is needed to advance the SSP past the alignment hole.
Operation
IF CPL = 3
ELSE
FI;
previous_ssp_token = SSP | (IA32_EFER.LMA AND CS.L) | 0x02
Start Atomic Executionrestore_ssp_token = Locked shadow _stack_load 8 bytes from SSP_LA
fault = 0
IF ((restore_ssp_token & 0x03) != (IA32_EFER.LMA & CS.L))
THEN fault = 1; FI; (* If L flag in token does no t match IA32_EFER.LMA & CS.L or bit 1 is not 0 *)
IF ((IA32_EFER.LMA AND CS.L) = 0 AND restore_ssp_token[63:32] != 0)
THEN fault = 1; FI; (* If compatibility/legacy mode and SSP to be restored not below 4G *)
TMP = restore_ssp_token & ~0x01
TMP = (TMP - 8)TMP = TMP & ~0x07IF TMP != SSP_LAOpcode/
F3 0F 01 /5 (mod!=11, /5, memory only)
RSTORSSP m64M V/V CET_SS Restore SSP.
M ModRM:r/m (r, w) N/A N/A N/ARSTORSSP—Restore Saved Shadow Stack PointerINSTRUCTION SET REFERENCE, M-U
4-588 Vol. 2BTHEN fault = 1; FI; (* If address in token does not match the requested top of stack *)
TMP = (fault == 0) ? previous _ssp_token : restore_ssp_token
shadow_stack_store 8 bytes of TMP to SSP_LA and release lock
End Atomic Execution
IF fault == 1
    THEN #CP(RSTORSSP); FI;
SSP = SSP_LA// Set the CF if the SSP in the re store token was 4 byte aligned, i.e., there is an alignment hole
RFLAGS.CF = (restore_ssp_token & 0x04) ? 1 : 0;RFLAGS.ZF,PF,AF,OF,SF := 0;
CF is set to indicate if the shadow stack pointer in the rest ore token was 4 byte aligned, else it is cleared. ZF, PF, AF, 
OF, and SF are cleared.
RSTORSSP void _r storssp(void *);
IF CPL = 3 and IA32_U_CET.SH_STK_EN = 0.
#GP(0) If linear address of memory operand not 8 byte aligned.
If destination is located in a non-writeable segment.If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment 
selector.
#CP(rstorssp) If L bit in token does not match (IA32_EFER.LMA & CS.L).
If address in token does not match linear address of memory operand.
If in 32-bit or compatibility mode and the address in token is not below 4G.
#UD The RSTORSSP instruction is no t recognized in real-address mode. 
#UD The RSTORSSP instruction is not recognized in virtual-8086 mode. 
Same as protected mode exceptions.RSTORSSP—Restore Saved Shadow Stack PointerINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-58964-Bit Mode Exceptions
If CR4.CET = 0.If CPL = 3 and IA32_U_CET.SH_STK_EN = 0.
If CPL < 3 and IA32_S_CET.SH_STK_EN = 0.
#GP(0) If linear address of memo ry operand not 8 byte aligned.
If a memory address is in a non-canonical form.
#PF(fault-code) If a page fault occurs.SAHF—Store AH Into FlagsINSTRUCTION SET REFERENCE, M-U
4-590 Vol. 2BSAHF—Store AH Into Flags
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS regist er with values from the corresponding bits in the AH 
register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3,  and 5 of register AH are igno red; the corresponding reserved 
bits (1, 3, and 5) in the EFLAGS register re main as shown in the “Operation” section below.
This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only 
if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.
Operation
IF IA-64 Mode
THEN
IF CPUID.80000001H.ECX[0] = 1;
THEN
RFLAGS(SF:ZF:0:AF:0:PF:1:CF) := AH;
ELSE
#UD;
FI
ELSE
EFLAGS(SF:ZF:0:AF:0:PF:1:CF) := AH;
FI;
The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register 
are unaffected, with the values remaining 1, 0, and 0, respectively.
None.
None.
None.
NOTES:
1. Valid in specific steppings. See Description section.Instruction Op/ 
En64-Bit 
9E SAHF ZO Invalid* Valid Loads SF, ZF, AF, PF, and CF from AH into the EFLAGS 
register.
ZO N/A N/A N/A N/ASAHF—Store AH Into FlagsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-59164-Bit Mode Exceptions
#UD If CPUID.80000001H.ECX[0] = 0.
If the LOCK prefix is used.SAL/SAR/SHL/SHR—ShiftINSTRUCTION SET REFERENCE, M-U
4-592 Vol. 2BSAL/SAR/SHL/SHR—Shift
En64-Bit 
D0 /4 SAL r/m8, 1 M1 Valid Valid Multiply r/m8 by 2, once. 
REX + D0 /4 SAL r/m82, 1 M1 Valid N.E. Multiply r/m8 by 2, once. 
D2 /4 SAL r/m8, CL MC Valid Valid Multiply r/m8 by 2, CL times.REX + D2 /4 SAL r/m8
2, CL MC Valid N.E. Multiply r/m8 by 2, CL times.
C0 /4 ib SAL r/m8, imm8 MI Valid Valid Multiply r/m8 by 2, imm8 times.REX + C0 /4 ib SAL r/m8
2, imm8 MI Valid N.E. Multiply r/m8 by 2, imm8 times.

NOTES:
En64-Bit 
register.
En64-Bit 
D1 /4 SAL r/m16, 1 M1 Valid Valid Multiply r/m16 by 2, once.D3 /4 SAL r/m16, CL MC Valid Valid Multiply r/m16 by 2, CL times.C1 /4 ib SAL r/m16, imm8 MI Valid Valid Multiply r/m16 by 2, imm8 times.D1 /4 SAL r/m32, 1 M1 Valid Valid Multiply r/m32 by 2, once.REX.W + D1 /4 SAL r/m64, 1 M1 Valid N.E. Multiply r/m64 by 2, once.
D3 /4 SAL r/m32, CL MC Valid Valid Multiply r/m32 by 2, CL times.REX.W + D3 /4 SAL r/m64, CL MC Valid N .E. Multiply r/m64 by 2, CL times.
C1 /4 ib SAL r/m32, imm8 MI Valid Valid Multiply r/m32 by 2, imm8 times.REX.W + C1 /4 ib SAL r/m64, imm8 MI Valid N.E. Multiply r/m64 by 2, imm8 times.D0 /7 SAR r/m8, 1 M1 Valid Valid Signed divide
3 r/m8 by 2, once.
REX + D0 /7 SAR r/m82, 1 M1 Valid N.E. Signed divide3 r/m8 by 2, once.
D2 /7 SAR r/m8, CL MC Valid Valid Signed divide3 r/m8 by 2, CL times.
REX + D2 /7 SAR r/m82, CL MC Valid N.E. Signed divide3 r/m8 by 2, CL times.
C0 /7 ib SAR r/m8, imm8 MI Valid Valid Signed divide3 r/m8 by 2, imm8 times.
REX + C0 /7 ib SAR r/m82, imm8 MI Valid N.E. Signed divide3 r/m8 by 2, imm8 times.
D1 /7 SAR r/m16,1 M1 Valid Valid Signed divide3 r/m16 by 2, once.
D3 /7 SAR r/m16, CL MC Valid Valid Signed divide3 r/m16 by 2, CL times.
C1 /7 ib SAR r/m16, imm8 MI Valid Valid Signed divide3 r/m16 by 2, imm8 times.
D1 /7 SAR r/m32, 1 M1 Valid Valid Signed divide3 r/m32 by 2, once.
REX.W + D1 /7 SAR r/m64, 1 M1 Valid N.E. Signed divide3 r/m64 by 2, once.
D3 /7 SAR r/m32, CL MC Valid Valid Signed divide3 r/m32 by 2, CL times.
REX.W + D3 /7 SAR r/m64, CL MC Valid N.E. Signed divide3 r/m64 by 2, CL times.
C1 /7 ib SAR r/m32, imm8 MI Valid Valid Signed divide3 r/m32 by 2, imm8 times.
REX.W + C1 /7 ib SAR r/m64, imm8 MI Valid N.E. Signed divide3 r/m64 by 2, imm8 times
D0 /4 SHL r/m8, 1 M1 Valid Valid Multiply r/m8 by 2, once.REX + D0 /4 SHL r/m8
2, 1 M1 Valid N.E. Multiply r/m8 by 2, once.
D2 /4 SHL r/m8, CL MC Valid Valid Multiply r/m8 by 2, CL times.REX + D2 /4 SHL r/m8
C0 /4 ib SHL r/m8, imm8 MI Valid Valid Multiply r/m8 by 2, imm8 times.REX + C0 /4 ib SHL r/m8
D1 /4 SHL r/m16,1 M1 Valid Valid Multiply r/m16 by 2, once.D3 /4 SHL r/m16, CL MC Valid Valid Multiply r/m16 by 2, CL times.C1 /4 ib SHL r/m16, imm8 MI Valid Valid Multiply r/m16 by 2, imm8 times.D1 /4 SHL r/m32,1 M1 Valid Valid Multiply r/m32 by 2, once.SAL/SAR/SHL/SHR—ShiftINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-593Instruction Operand Encoding
Shifts the bits in the first operand (destination operand) to  the left or right by the num ber of bits specified in the 
second operand (count operand). Bits shifted beyond the de stination operand boundary are first shifted into the CF 
flag, then discarded. At the end of the shift operation, the CF  flag contains the last bit shifted out of the destination 
operand. 
The destination operand can be a register or a memory lo cation. The count operand can be an immediate value or 
the CL register. The count is masked to 5 bits (or 6 bits with a 64-bit operand). The count range is limited to 0 to 
31 (or 63 with a 64-bit operand). A special opcode encoding is provided for a count of 1.
The shift arithmetic left (SAL) and shift logical left (SHL ) instructions perform the same operation; they shift the 
bits in the destination operand to the left (toward more significant bit locations). For each shift count, the most 
significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see 
Figure 7-7 in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 1).REX.W + D1 /4 SHL r/m64,1 M1 Valid N. E. Multiply r/m64 by 2, once.
D3 /4 SHL r/m32, CL MC Valid Valid Multiply r/m32 by 2, CL times.REX.W + D3 /4 SHL r/m64, CL MC Valid N .E. Multiply r/m64 by 2, CL times.
C1 /4 ib SHL r/m32, imm8 MI Valid Vali d Multiply r/m32 by 2, imm8 times.
REX.W + C1 /4 ib SHL r/m64, imm8 MI Vali d N.E. Multiply r/m64 by 2, imm8 times.
D0 /5 SHR r/m8,1 M1 Valid Valid Unsigned divide r/m8 by 2, once.REX + D0 /5 SHR r/m8
2, 1 M1 Valid N.E. Unsigned divide r/m8 by 2, once.
D2 /5 SHR r/m8, CL MC Valid Valid Unsigned divide r/m8 by 2, CL times.REX + D2 /5 SHR r/m8
2, CL MC Valid N.E. Unsigned divide r/m8 by 2, CL times.
C0 /5 ib SHR r/m8, imm8 MI Valid Valid Unsigned divide r/m8 by 2, imm8 times.REX + C0 /5 ib SHR r/m8
2, imm8 MI Valid N.E. Unsigned divide r/m8 by 2, imm8 times.
D1 /5 SHR r/m16, 1 M1 Valid Valid Unsigned divide r/m16 by 2, once.
D3 /5 SHR r/m16, CL MC Valid Valid Unsigned divide r/m16 by 2, CL timesC1 /5 ib SHR r/m16, imm8 MI Valid Valid Unsigned divide r/m16 by 2, imm8 times.
D1 /5 SHR r/m32, 1 M1 Valid Valid Unsigned divide r/m32 by 2, once.REX.W + D1 /5 SHR r/m64, 1 M1 Valid N.E. Unsigned divide r/m64 by 2, once.D3 /5 SHR r/m32, CL MC Valid Valid Unsigned divide r/m32 by 2, CL times.REX.W + D3 /5 SHR r/m64, CL MC Valid N.E. U nsigned divide r/m64 by 2, CL times.
C1 /5 ib SHR r/m32, imm8 MI Valid Valid Unsigned divide r/m32 by 2, imm8 times.
REX.W + C1 /5 ib SHR r/m64, imm8 MI Valid N.E. Unsigned divide r/m64 by 2, imm8 times.
NOTES:
3. Not the same form of di vision as IDIV; rounding is  toward negati ve infinity.
M1 ModRM:r/m (r, w) 1 N/A N/A
MC ModRM:r/m (r, w) CL N/A N/A
MI ModRM:r/m (r, w) imm8 N/A N/AOpcode1Instruction Op/ 
En64-Bit 
Leg ModeDescriptionSAL/SAR/SHL/SHR—ShiftINSTRUCTION SET REFERENCE, M-U
4-594 Vol. 2BThe shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to 
the right (toward less significant bit locations). For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significan t bit is either set or cleared depending on the instruction 
type. The SHR instruction clears the most significant bit (see Figure 7-8 in the Intel
Software Developer’s Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond to the sign (most significant bit) of the original value in the destination operand. In effect, the SAR instruction fills 
the empty bit position’s shifted value with the sign of the unshifted value (see Figure 7-9 in the Intel
Architectures Software Developer’s Manual, Volume 1).
The SAR and SHR instructions can be used to perform sign ed or unsigned division, respectively, of the destination 
operand by powers of 2. For example, using the SAR instru ction to shift a signed intege r 1 bit to the right divides 
the value by 2.
Using the SAR instruction to perform a division operation do es not produce the same result as the IDIV instruction. 
The quotient from the IDIV instruction is rounded toward zero, whereas the “quotient” of the SAR instruction is 
rounded toward negative infinity. This difference is appa rent only for negative numbers. For example, when the 
IDIV instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR instruction is used to 
shift -9 right by two bits, the result is -3 and the “remainder” is +3; however, the SAR instruction stores only the 
most significant bit of the remainder (in the CF flag). 
The OF flag is affected only on 1-bit shifts. For left shifts , the OF flag is set to 0 if the most-significant bit of the 
result is the same as the CF flag (that is, the top two bits  of the original operand were  the same); otherwise, it is 
set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag is set 
to the most-significant bit of the original operand.
In 64-bit mode, the instruction’s default operation size is  32 bits and the mask width for CL is 5 bits. Using a REX 
prefix in the form of REX.R permits a ccess to additional registers (R8-R15). Us ing a REX prefix in the form of REX.W 
promotes operation to 64-bits and sets the mask width for CL to 6 bits. See the summary chart at the beginning of 
this section for encoding data and limits.
The 8086 does not mask the shift count. However, all othe r IA-32 processors (starting with the Intel 286 processor) 
do mask the shift count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes 
(including the virtual-8086 mode) to reduce th e maximum execution time of the instructions.
Operation
THEN
countMASK := 3FH;
ELSE
countMASK := 1FH;
FI
tempCOUNT := (COUNT AND countMASK);
tempDEST := DEST;WHILE (tempCOUNT 
≠ 0)
DO
IF instruction is SAL or SHL
THEN 
CF := MSB(DEST);
ELSE (* Instruction is SAR or SHR *)
CF := LSB(DEST);
FI;IF instruction is SAL or SHL
THEN 
DEST := DEST 
∗ 2;
ELSE

Operation
THEN
ELSE
FI
≠ 0)
DO
THEN 
THEN 
∗ 2;
ELSE 
IF instruction is SARSAL/SAR/SHL/SHR—ShiftINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-595THEN 
DEST := DEST  / 2; (* Signed divide, rounding toward negative infinity *)
ELSE (* Instruction is SHR *)
DEST := DEST / 2 ; (* Unsigned divide *)
FI;
FI;tempCOUNT := tempCOUNT – 1;
OD;
(* Determine overflow for the various instructions *)
IF (COUNT and countMASK) =
 1
THEN
THEN 
OF := MSB(DEST) XOR CF;
ELSE 
IF instruction is SAR
THEN 
OF := 0;
OF := MSB(tempDEST);
FI;
FI;
ELSE IF (COUNT AND countMASK) =  0
THEN
All flags unchanged;
ELSE (* COUNT not 1 or 0 *)
OF := undefined;
FI;
FI;
The CF flag contains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR 
instructions where the count is greater than or equal to the size (in bits) of the destination operand. The OF flag is 
affected only for 1-bit shifts (see “Description” above); ot herwise, it is undefined. The SF, ZF, and PF flags are set 
according to the result. If the count is 0, the flags are no t affected. For a non-zero count, the AF flag is undefined.
#SS If a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.SAL/SAR/SHL/SHR—ShiftINSTRUCTION SET REFERENCE, M-U
4-596 Vol. 2BVirtual-8086 Mode Exceptions
#UD If the LOCK prefix is used.SARX/SHLX/SHRX—Shift Without Affecting FlagsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-597SARX/SHLX/SHRX—Shift Without Affecting Flags 
Shifts the bits of the first source operand (the second oper and) to the left or right by a COUNT value specified in the 
second source operand (the third operand). The result is  written to the destination operand (the first operand).
The shift arithmetic right (SARX) and sh ift logical right (SHRX) instructions sh ift the bits of the destination operand 
to the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit) while shifting.
The logical shift left (SHLX) shifts the bits of the destin ation operand to the left (toward more significant bit loca-
tions). 
If the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked.
SARX,SHRX, and SHLX  instructions do not update flags. 
Operation
IF VEX.W1 an d CS.L = 1
THEN
countMASK  := 3FH;
ELSE
countMASK  := 1FH;
FICOUNT := (SRC2 AND countMASK)
DEST[OperandSize -1] = TEMP[OperandSize -1];
DO WHILE (COUNT ≠ 0)
IF instruction is SHLX
THENOpcode/
En64/32-
VEX.LZ.F3.0F38.W0 F7 /r
SARX r32a, r/m32, r32bRMV V/V BMI2 Shift r/m32 arithmetically right with count specified in r32b.
VEX.LZ.66.0F38.W0 F7 /r
SHLX r32a, r/m32, r32bRMV V/V BMI2 Shift r/m32 logically left  with count specified in r32b.
VEX.LZ.F2.0F38.W0 F7 /r
SHRX r32a, r/m32, r32bRMV V/V BMI2 Shift r/m32 lo gically right with count  specified in r32b.
VEX.LZ.F3.0F38.W1 F7 /r
SARX r64a, r/m64, r64bRMV V/N.E. BMI2 Shift r/m64 arithmetically right with count specified in r64b.
VEX.LZ.66.0F38.W1 F7 /r
SHLX r64a, r/m64, r64bRMV V/N.E. BMI2 Shift r/m64 logically le ft with count specified in r64b.
VEX.LZ.F2.0F38.W1 F7 /r
SHRX r64a, r/m64, r64bRMV V/N.E. BMI2 Shift r/m64 logically right with co unt specified in r64b.
RMV ModRM:reg (w) ModRM:r/m (r) VEX.vvvv (r) N/ASARX/SHLX/SHRX—Shift Without Affecting FlagsINSTRUCTION SET REFERENCE, M-U
4-598 Vol. 2BDEST[] := DEST *2;
ELSE IF instruction is SHRX
THEN
DEST[]  := DEST /2; //unsigned divide
ELSE // SARX
DEST[] := DEST /2; // signed divide, round toward negative infinity
FI;COUNT := COUNT - 1;
OD
None.
None.
See Table 2-29, “Type 13 Class Exception Conditions.”SAVEPREVSSP—Save Previous Shadow Stack PointerINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-599SAVEPREVSSP—Save Previous Shadow Stack Pointer
Push a restore-shadow-stack token on the previous sh adow stack at the next 8 byte aligned boundary. The 
previous SSP is obtained from the previous-ssp  token at the top of the current shadow stack.
Operation
IF CPL = 3
ELSE
FI;
IF SSP not aligned to 8 bytes
(* Pop the “previous- ssp” token from current shadow stack *)
previous_ssp_token = ShadowStackPop8B(SSP)
(* If the CF flag indicates there was a alignment hole on current shadow stack then  pop that alignment hole *)
(* Note that the alignment hole must be zero and can be present only when in legacy/compatibility mode *)
IF RFLAGS.CF == 1 AND (IA32_EFER.LMA AND CS.L)
#GP(0)
FI;IF RFLAGS.CF == 1
must_be_zero = ShadowStackPop4B(SSP)IF must_be_zero != 0 THEN #GP(0)
FI;
(* Previous SSP token mu st have the bit 1 set *)
IF ((previous_ssp_token & 0x02) == 0)
THEN #GP(0); (* bit 1 was 0 *)
IF ((IA32_EFER.LMA AND CS.L) = 0 AND previous_ssp_token [63:32] != 0)
THEN #GP(0); FI; (* If compatibilit y/legacy mode and SSP not in 4G *)
(* Save Prev SSP from previous_s sp_token to the old shadow stack at next 8 byte aligned address *)
old_SSP = previous_ ssp_token & ~0x03
temp := (old_SSP | (IA32_EFER.LMA & CS.L));Shadow_stack_store 4 bytes of 0 to (old_SSP - 4)old_SSP := old_SSP & ~0x07;Opcode/
F3 0F 01 EA (mod!=11, /5, RM=010)
SAVEPREVSSPZO V/V CET_SS Save a restore-shadow-stack token on previous shadow stack.
ZO N/A N/A N/A N/ASAVEPREVSSP—Save Previous Shadow Stack PointerINSTRUCTION SET REFERENCE, M-U
4-600 Vol. 2BShadow_stack_store 8 bytes of temp to (old_SSP - 8)
None.
SAVEPREVSSP void _saveprevssp(void);
IF CPL = 3 and IA32_U_CET.SH_STK_EN = 0.IF CPL < 3 and IA32_S_CET.SH_STK_EN = 0.
#GP(0) If SSP not 8 byte aligned.
If alignment hole on shadow stack is not 0.
If bit 1 of the previous-ssp token is not set to 1.
If in 32-bit/compatibility mode and SSP reco rded in previous-ssp token is beyond 4G.
#UD The SAVEPREVSSP instruction is not recognized in real-address mode. 
#UD The SAVEPREVSSP instruction is not recognized in virtual-8086 mode. 
If CPL = 3 and IA32_U_CET.SH_STK_EN = 0.
If carry flag is set.
#PF(fault-code) If a page fault occurs.SBB—Integer Subtraction With BorrowINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-601SBB—Integer Subtraction With Borrow
Adds the source operand (second operand) and the carry (C F) flag, and subtracts the result from the destination 
operand (first operand). The result of the subtraction is stored in the destination operand. The destination operand

operand (first operand). The result of the subtraction is stored in the destination operand. The destination operand 
can be a register or a memory location; the source operan d can be an immediate, a regi ster, or a memory location. Opcode Instruction Op/ 
En64-Bit 
1C ib SBB AL, imm8 I Valid Valid Subtr act with borrow imm8 from AL.
1D iw SBB AX, imm16 I Valid Valid Subtr act with borrow imm16 from AX.
1D id SBB EAX, imm32 I Valid Valid Sub tract with borrow imm32 from EAX.
REX.W + 1D id SBB RAX, imm32 I Valid N.E. Sub tract with borrow sign-extended imm.32 
to 64-bits from RAX.
80 /3 ib SBB r/m8, imm8 MI Valid Valid Subtract with borrow imm8 from r/m8.REX + 80 /3 ib SBB r/m8
1, imm8
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.MI Valid N.E. Subtract with borrow imm8 from r/m8.
81 /3 iw SBB r/m16, imm16 MI Valid Valid Subtract with borrow imm16 from r/m16.81 /3 id SBB r/m32, imm32 MI Valid Valid Subtract with borrow imm32 from r/m32.REX.W + 81 /3 id SBB r/m64, imm32 MI Valid N.E. Subtract with borrow sign-extended imm32 to 
64-bits from r/m64.
83 /3 ib SBB r/m16, imm8 MI Valid Valid Subtract with borrow sign-extended imm8 
from r/m16.
83 /3 ib SBB r/m32, imm8 MI Valid Valid Subtract with borrow sign-extended imm8 
from r/m32.
REX.W + 83 /3 ib SBB r/m64, imm8 MI Valid N.E . Subtract with borrow  sign-extended imm8 
from r/m64.
18 /r SBB r/m8, r8 MR Valid Valid Subtr act with borrow r8 from r/m8.
REX + 18 /r SBB r/m8
1, r8 MR Valid N.E. Subtract with  borrow r8 from r/m8.
19 /r SBB r/m16, r16 MR Valid Valid Sub tract with borrow  r16 from r/m16.
19 /r SBB r/m32, r32 MR Valid Valid Sub tract with borrow  r32 from r/m32.
REX.W + 19 /r SBB r/m64, r64 MR Valid N.E. Subtract with borrow r64 from r/m64.
1A /r SBB r8, r/m8 RM Valid Valid Subtract with borrow r/m8 from r8.REX + 1A /r SBB r8
1, r/m81RM Valid N.E. Subtract with borrow r/m8 from r8.
1B /r SBB r16, r/m16 RM Valid Valid Sub tract with borrow  r/m16 from r16.
1B /r SBB r32, r/m32 RM Valid Valid Sub tract with borrow  r/m32 from r32.
REX.W + 1B /r SBB r64, r/m64 RM Valid N.E. Subtract with borrow r/m64 from r64.
MI ModRM:r/m (w) imm8/16/32 N/A N/A
MR ModRM:r/m (w) ModRM:reg (r) N/A N/ARM ModRM:reg (w) ModRM:r/m (r) N/A N/ASBB—Integer Subtraction With BorrowINSTRUCTION SET REFERENCE, M-U
4-602 Vol. 2B(However, two memory operands cannot be used in one in struction.) The state of the CF flag represents a borrow 
from a previous subtraction.
When an immediate value is used as an operand, it is  sign-extended to the length of the destination operand 
format.
The SBB instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates 
the result for both data types and sets  the OF and CF flags to indicate a borrow in the signed or unsigned result, 
The SBB instruction is usually executed as part of a mult ibyte or multiword subtraction in which a SUB instruction 
is followed by a SBB instruction.
Operation
DEST := (DEST – (SRC + CF));
SBB extern unsigned char _subborrow_u8(unsi gned char c_in, unsigned ch ar src1, unsigned char src2 , unsigned char *diff_out);
SBB extern unsigned char _subborrow_u16(uns igned char c_in, unsigned sh ort src1, unsigned short src2 , unsigned short *diff_out) ;
SBB extern unsigned char _subborrow_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *diff_out);SBB extern unsigned char _subborrow_u64(u nsigned char c_in, unsigned __int64 src1, unsigned __in t64 src2, unsigned __int64 
*diff_out);
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.
#UD If the LOCK prefix is used but the destination is not a memory operand.SBB—Integer Subtraction With BorrowINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-603Compatibility Mode Exceptions
#UD If the LOCK prefix is used but th e destination is not a memory operand.SCAS/SCASB/SCASW/SCASD—Scan StringINSTRUCTION SET REFERENCE, M-U
4-604 Vol. 2BSCAS/SCASB/SCASW/S CASD—Scan String 
In non-64-bit modes and in default 64-bit mode: this inst ruction compares a byte, word, doubleword or quadword 
specified using a memory operand with the value in AL, AX, or EAX. It then sets status  flags in EFLAGS recording 
the results. The memory operand address is read from ES :(E)DI register (depending on the address-size attribute 
of the instruction and the current operational mode). Note  that ES cannot be overridden with a segment override 
prefix.
At the assembly-code level, two forms of this instructio n are allowed. The explicit-operand form and the no-oper-
ands form. The explicit-operand form (specified using the SCAS mnemonic) allows a memory operand to be speci-
fied explicitly. The memory operand must be a symbol that indicates the size and location  of the operand value. The 
register operand is then automatically selected to matc h the size of the memory operand (AL register for byte 
comparisons, AX for word comparisons, EAX for doubleword  comparisons). The explicit-operand form is provided 
to allow documentation. Note that the documentation provided by this form can be misleading. That is, the memory operand symbol must specify the correct type (siz e) of the operand (byte, word, or doubleword) but it 
does not have to specify the correct location. The location is always specified by ES:(E)DI.
The no-operands form of the instruction uses a short form  of SCAS. Again, ES:(E)DI is assumed to be the memory 
operand and AL, AX, or EAX is assumed to be the register  operand. The size of operands is selected by the 
mnemonic: SCASB (byte comparison), SCASW (word comparison), or SCASD (doubleword comparison).
After the comparison, the (E)DI register is incremented or  decremented automatically according to the setting of 
the DF flag in the EFLAGS register. If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI 
register is decremented. The register is incremented or decremented by 1 for byte operations, by 2 for word oper-
ations, and by 4 for doubleword operations.Opcode Instruction Op/ 
En64-Bit 
AE SCAS m8 ZO Valid Valid Compa re AL with byte at ES:( E)DI or RDI, then set 
status flags.
1
NOTES:
address sizes are supported.AF SCAS m16 ZO Valid Valid Compare AX with  word at ES:(E)DI or RDI, then set 
status flags.1
AF SCAS m32 ZO Valid Valid Compare EAX with doubleword at ES(E)DI or RDI then 
set status flags.1
REX.W + AF SCAS m64 ZO Valid N.E. Compare RAX with quadword at RDI or EDI then set 
AE SCASB ZO Valid Valid Compare AL with byte at ES:(E)DI or RDI then set 
AF SCASW ZO Valid Valid Compare AX with word at ES:(E)DI or RDI then set 

En64-Bit 
1
NOTES:
AF SCASD ZO Valid Valid Compare EAX with doubleword at ES:(E)DI or RDI 
then set status flags.1
REX.W + AF SCASQ ZO Valid N.E. Compare RAX with quadword at RDI or EDI then set 
ZO N/A N/A N/A N/ASCAS/SCASB/SCASW/SCASD—Scan StringINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-605SCAS, SCASB, SCASW, SCASD, and SCASQ can be preceded by  the REP prefix for block comparisons of ECX bytes, 
words, doublewords, or quadwords. Often, however, these instructions will be used in a LOOP construct that takes 
some action based on the setting of status flags. Se e “REP/REPE/REPZ /REPNE/REP NZ—Repeat String Operation 
Prefix” in this chapter for a description of the REP prefix.
In 64-bit mode, the instruction’s default address size is 64-bits, 32-bit address size is supported using the prefix 
67H. Using a REX prefix in the form of REX.W promotes op eration on doubleword operand to 64 bits. The 64-bit no-
operand mnemonic is SCASQ. Address of the memory operand is specified in either RDI or EDI, and 
AL/AX/EAX/RAX may be used as the register operand. Afte r a comparison, the destination register is incremented 
or decremented by the current operand size (depending on the value of the DF flag). See the summary chart at the 
Operation
THEN
temp := AL − SRC;
THEN IF DF = 0 
THEN
temp := AX − SRC;
SetStatusFlags(temp);IF DF = 0
FI;
THEN
temp := EAX – SRC;SetStatusFlags(temp);IF DF
 = 0
FI;
FI;
64-bit Mode:
THEN
THEN (R|E)DI := (R|E)DI + 1; 
ELSE (R|E)DI := (R|E)DI – 1; FI;
THEN
THEN (R|E)DI := (R|E)DI + 2; 
ELSE (R|E)DI := (R|E)DI – 2; FI;
FI;SCAS/SCASB/SCASW/SCASD—Scan StringINSTRUCTION SET REFERENCE, M-U
4-606 Vol. 2BELSE IF (Doubleword comparison)
THEN
 = 0
THEN (R|E)DI := (R|E)DI + 4; 
ELSE (R|E)DI := (R|E)DI – 4; FI;
FI;
ELSE IF (Quadword comparison using REX.W )
THEN
temp := RAX − SRC;
THEN (R|E)DI := (R|E)DI + 8; 
ELSE (R|E)DI := (R|E)DI – 8; 
FI;
FI;
FI;
The OF, SF, ZF, AF, PF, and CF flags are set according to the temporary result of the comparison.
#GP(0) If a memory operand effective addre ss is outside the limit of the ES segment.
If the ES register contains a NULL segment selector.If an illegal memory operand effectiv e address in the ES segment is given.
Same exceptions as in protected mode.SCAS/SCASB/SCASW/SCASD—Scan StringINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-60764-Bit Mode Exceptions
#UD If the LOCK prefix is used.SENDUIPI—Send User Interprocessor InterruptINSTRUCTION SET REFERENCE, M-U
4-608 Vol. 2BSENDUIPI—Send User Interprocessor Interrupt
The SENDUIPI instruction sends the user interprocessor in terrupt (IPI) indicated by its register operand. (The 
operand always has 64 bits; operand-size overrides such as the prefix 66 are ignored.)
SENDUIPI uses a data structure called the user-interrupt target table (UITT). This table is located at the linear 
address UITTADDR (in the IA32_UINTR_TT MSR); it comprises UITTSZ+1 16-byte entries, where UITTSZ = 
IA32_UINT_MISC[31:0]. SENDUIPI uses the UITT entry (U ITTE) indexed by the instruction's register operand. 
Each UITTE has the following format:
•Bit 0: V, a valid bit.
•Bits 7:1 are reserved and must be 0.
•Bits 15:8: UV, the user-interrupt vector (in the range 0–63, so bits 15:14 must be 0).
•Bits 63:16 are reserved.
•Bits 127:64: UPIDADDR, the linear address of a user posted-interrupt descriptor (UPID). (UPIDADDR is 64-
byte aligned, so bits 69:64 of each UITTE must be 0.)
Each UPID has the following format (field s and bits not referenced are reserved):
•Bit 0 (ON) indicates an outstanding notification. If this bi t is set, there is a notification outstanding for one or 
more user interrupts in PIR.
•Bit 1 (SN) indicates that notifications should be suppre ssed. If this bit is set, agents (including SENDUIPI) 
should not send notifications when posting user interrupts in this descriptor.
•Bits 23:16 (NV) contain the notification vector. This is  used by agents sending user-interrupt notifications 
(including SENDUIPI).
•Bits 63:32 (NDST) contain the notification destination. This is the target physical APIC ID (in xAPIC mode, 
bits 47:40 are the 8-bit APIC ID; in x2APIC mo de, the entire field forms the 32-bit APIC ID).
•Bits 127:64 (PIF) contain posted-interrupt requests. There is one bit for each user-interrupt vector. There is a 
user-interrupt request for a vector if the corresponding bit is 1.
Although SENDUIPI may be executed at any privilege leve l, all of the instruction’s memory accesses (to a UITTE 
and a UPID) are performed with supervisor privilege.
SENDUIPI sends a user interrupt by posting a user interrupt  with vector V in the UPID referenced by UPIDADDR and 
then sending, as an ordinary IPI, any notification interrupt specified in that UPID.
Operation
IF reg > UITTSZ;
FI;read tempUITTE from 16 bytes at UITTADDR+ (reg « 4);IF tempUITTE.V = 0 or temp UITTE sets any reserved bit
Mode 
F3 0F C7 /6 
SENDUIPI regA V/I UINTR Send interprocessor user interrupt.
A N/A ModRM:reg (r) N/A N/A N/ASENDUIPI—Send User Interprocessor InterruptINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-609read tempUPID from 16 bytes at  tempUITTE.UPIDA DDR;// under lock
IF tempUPID sets any reserved bi ts or bits that must be zero
THEN #GP(0); // release lock
FI;tempUPID.PIR[tempUITTE.UV] := 1;IF tempUPID.SN = tempUPID.ON = 0
THEN
tempUPID.ON := 1;sendNotify := 1;
ELSE sendNotify := 0;
FI;write tempUPID to 16 bytes at tempUITTE.UPIDADDR;// release lock
IF sendNotify = 1
THEN
IF local APIC is in x2APIC mode
THEN send ordinary IPI with vector tempUPID.NV
to 32-bit physical APIC ID tempUPID.NDST;
ELSE send ordinary IPI with vector tempUPID.NV
to 8-bit physical APIC ID tempUPID.NDST[15:8];
FI;
FI;
None.
#UD The SENDUIPI instruction is not recognized in protected mode.
#UD The SENDUIPI instruction is no t recognized in real-address mode.
#UD The SENDUIPI instruction is not recognized in virtual-8086 mode.
#UD The SENDUIPI instruction is no t recognized in compatibility mode.
If executed inside an enclave.If CR4.UINTR = 0.
If IA32_UINTR_TT[0] = 0.
If CPUID.07H.0H:EDX.UINTR[bit 5] = 0.
#PF If a page fault occurs.
#GP If the value of the register operand exceeds UITTSZ.
If the selected UITTE is not valid or sets any reserved bits.If the selected UPID sets any reserved bits.
If there is an attempt to access memory using a linear address that is not canonical relative to 
the current paging mode.SERIALIZE—Serialize Instruction ExecutionINSTRUCTION SET REFERENCE, M-U
4-610 Vol. 2BSERIALIZE—Serialize Instruction Execution 
Serializes instruction execution. Before the next instru ction is fetched and executed, the SERIALIZE instruction 
ensures that all modifications to flags,  registers, and memory by previous in structions are completed, draining all 
buffered writes to memory. This instruction is also a seri alizing instruction as defined in the section “Serializing

buffered writes to memory. This instruction is also a seri alizing instruction as defined in the section “Serializing 
Instructions” in Chapter 9 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
SERIALIZE does not modify registers, arithmetic flags, or memory. 
Operation
Wait_On_Fetch_And_Execution_Of_Next_Instruction_Until(precedin g_instructions_complete_and_prec eding_stores_globally_visible);
SERIALIZE void _serialize(void);
None.
If CPUID.07H.0H:EDX.S ERIALIZE[bit 14] = 0.Opcode/
Mode 
NP 0F 01 E8
SERIALIZEZO V/V SERIALIZE Serialize instruction fetch and execution.
ZO N/A N/A N/A N/A N/ASETcc—Set Byte on ConditionINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-611SETcc—Set Byte on Condition
En64-Bit 
0F 97 SETA r/m8 M Valid Valid Set byte if above (CF=0 and ZF=0).
REX + 0F 97 SETA r/m81M Valid N.E. Set byte if above (CF=0 and ZF=0).
0F 93 SETAE r/m8 M Valid Valid Set byte if above or equal (CF=0).
REX + 0F 93 SETAE r/m81M Valid N.E. Set byte if above or equal (CF=0).
0F 92 SETB r/m8 M Valid Valid S et byte if below (CF=1).
REX + 0F 92 SETB r/m81M Valid N.E. Set byte if below (CF=1).
0F 96 SETBE r/m8 M Valid Valid Set byte  if below or equa l (CF=1 or ZF=1).
REX + 0F 96 SETBE r/m81M Valid N.E. Set byte if belo w or equal (CF=1 or ZF=1).
0F 92 SETC r/m8 M Valid Valid Set byte if carry (CF=1).REX + 0F 92 SETC r/m8
1M Valid N.E. Set byte if carry (CF=1).
0F 94 SETE r/m8 M Valid Valid S et byte if equal (ZF=1).
REX + 0F 94 SETE r/m81M Valid N.E. Set byte if equal (ZF=1).
0F 9F SETG r/m8 M Valid Valid Set byte if greater (ZF=0 and SF=OF).REX + 0F 9F SETG r/m8
1M Valid N.E. Set byte if greater (ZF=0 and SF=OF).
0F 9D SETGE r/m8 M Valid Valid Set byte if greater or equal (SF=OF).REX + 0F 9D SETGE r/m8
1M Valid N.E. Set byte if gr eater or equal (SF=OF).
0F 9C SETL r/m8 M Valid Valid Set byte if less (SF ≠ OF).
REX + 0F 9C SETL r/m81M Valid N.E. Set byte if less (SF ≠ OF).
0F 9E SETLE r/m8 M Valid Valid Set by te if less or equal (ZF=1 or SF ≠ OF).
REX + 0F 9E SETLE r/m81M Valid N.E. Set byte if less or equal (ZF=1 or SF ≠ OF).
0F 96 SETNA r/m8 M Valid Valid Set byte if not above (CF=1 or ZF=1).REX + 0F 96 SETNA r/m8
1M Valid N.E. Set byte if not above (CF=1 or ZF=1).
0F 92 SETNAE r/m8 M Valid Valid Set by te if not above or equal (CF=1).
REX + 0F 92 SETNAE r/m81M Valid N.E. Set byte if not above or equal (CF=1).
0F 93 SETNB r/m8 M Valid Valid Set byte if not below (CF=0).REX + 0F 93 SETNB r/m8
1M Valid N.E. Set byte if not below (CF=0).
0F 97 SETNBE r/m8 M Valid Valid Set byte if not below or equal (CF=0 and ZF=0).
REX + 0F 97 SETNBE r/m81M Valid N.E. Set byte if not below or equal (CF=0 and ZF=0).
0F 93 SETNC r/m8 M Valid Valid Set  byte if not carry (CF=0).
REX + 0F 93 SETNC r/m81M Valid N.E. Set byte if not carry (CF=0).
0F 95 SETNE r/m8 M Valid Valid Set  byte if not equal (ZF=0).
REX + 0F 95 SETNE r/m81M Valid N.E. Set byte if not equal (ZF=0).
0F 9E SETNG r/m8 M Valid Valid Set byte if not greater (ZF=1 or SF ≠ OF)
REX + 0F 9E SETNG r/m81M Valid N.E. Set byte if not greater (ZF=1 or SF ≠ OF).
0F 9C SETNGE r/m8 M Valid Valid Set byte if not greater or equal (SF ≠ OF).
REX + 0F 9C SETNGE r/m81M Valid N.E. Set byte if no t greater or equal (SF ≠ OF).
0F 9D SETNL r/m8 M Valid Valid Set byte if not less (SF=OF).REX + 0F 9D SETNL r/m8
1M Valid N.E. Set byte if not less (SF=OF).
0F 9F SETNLE r/m8 M Valid Valid Set byte if not less or equal (ZF=0 and SF=OF).
REX + 0F 9F SETNLE r/m81M Valid N.E. Set byte if not less or equal (ZF=0 and SF=OF).SETcc—Set Byte on ConditionINSTRUCTION SET REFERENCE, M-U
4-612 Vol. 2BInstruction Operand Encoding
Sets the destination operand to 0 or 1 depending on the se ttings of the status flags (CF, SF, OF, ZF, and PF) in the 
EFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix 
(cc) indicates the condition being tested for. 
The terms “above” and “below” are associated with the CF flag and refer to the relati onship between two unsigned 
integer values. The terms “greater” and “less” are associated  with the SF and OF flags and refer to the relationship 
between two signed integer values.
Many of the SET cc instruction opcodes have alternate mnemonics. For example, SETG (set byte if greater) and 
SETNLE (set if not less or equal) have the same opcode an d test for the same condition: ZF equals 0 and SF equals 
OF. These alternate mnemonics are provided to make co de more intelligible. Append ix B, “EFLAGS Condition 
Codes,” in the Intel® 64 and IA-32 Architectures Software Develo per’s Manual, Volume 1, shows the alternate 
mnemonics for various test conditions.
Some languages represent a logical one as an integer with all bits set. This representation can be obtained by 
choosing the logically opposite condition for the SET cc instruction, then decrementing the result. For example, to 
test for overflow, use the SETNO instruction, then decrement the result.0F 91 SETNO r/m8 M Valid Valid Set byte if not overflow (OF=0).
REX + 0F 91 SETNO r/m81M Valid N.E. Set byte if not overflow (OF=0).
0F 9B SETNP r/m8 M Valid Valid Set byte if not parity (PF=0).REX + 0F 9B SETNP r/m8
1M Valid N.E. Set byte if not parity (PF=0).
0F 99 SETNS r/m8 M Valid Valid Set  byte if not sign (SF=0).
REX + 0F 99 SETNS r/m81M Valid N.E. Set byte if not sign (SF=0).
0F 95 SETNZ r/m8 M Valid Valid Set byte if not zero (ZF=0).REX + 0F 95 SETNZ r/m8
1M Valid N.E. Set byte if not zero (ZF=0).
0F 90 SETO r/m8 M Valid Valid S et byte if overflow (OF=1)
REX + 0F 90 SETO r/m81M Valid N.E. Set byte if overflow (OF=1).
0F 9A SETP r/m8 M Valid Valid S et byte if parity (PF=1).
REX + 0F 9A SETP r/m81M Valid N.E. Set byte if parity (PF=1).
0F 9A SETPE r/m8 M Valid Valid Set byte if parity even (PF=1).
REX + 0F 9A SETPE r/m81M Valid N.E. Set byte if parity even (PF=1).
0F 9B SETPO r/m8 M Valid Valid Set  byte if parity odd (PF=0).
REX + 0F 9B SETPO r/m81M Valid N.E. Set byte if parity odd (PF=0).
0F 98 SETS r/m8 M Valid Valid S et byte if sign (SF=1).
REX + 0F 98 SETS r/m81M Valid N.E. Set byte if sign (SF=1).
0F 94 SETZ r/m8 M Valid Valid S et byte if zero (ZF=1).
REX + 0F 94 SETZ r/m81M Valid N.E. Set byte if zero (ZF=1).
NOTES:
M ModRM:r/m (w) N/A N/A N/AOpcode Instruction Op/ 
En64-Bit 
Leg ModeDescriptionSETcc—Set Byte on ConditionINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-613The reg field of the ModR/M byte is not used for the SE TCC instruction and those opcode bits are ignored by the 
In IA-64 mode, the operand size is fixed at 8 bits. Use of REX prefix enable uniform addressing to additional byte 
registers. Otherwise, this instruction’s operation is the same as in legacy mode and compatibility mode. 
Operation
THEN DEST := 1; ELSE DEST := 0; 
FI;
None.
#UD If the LOCK prefix is used.SETSSBSY—Mark Shadow Stack BusyINSTRUCTION SET REFERENCE, M-U
4-614 Vol. 2BSETSSBSY—Mark Shadow Stack Busy
The SETSSBSY instruction verifies the presence of a non-bu sy supervisor shadow stack token at the address in the 
IA32_PL0_SSP MSR and marks it busy. Following successful execution of the instruction, the SSP is set to the value 
of the IA32_PL0_SSP MSR.
Operation
IF CPL > 0
SSP_LA = IA32_PL0_SSP
If SSP_LA not aligned to 8 bytes

Operation
IF CPL > 0
expected_token_value = SSP_LA (*  busy bit must not be set *)
new_token_value          = SSP_LA | BUSY_BIT (* set busy bit; bit position 0 *)
IF shadow_stack_lock_cmpx chg8B(SSP_LA, new_token_value, expected_token_value) != expected_token_value
THEN #CP(SETSSBSY); FI;
SSP = SSP_LA
None.
SETSSBSYvoid _setssbsy(void);
#GP(0) If IA32_PL0_SSP not aligned to 8 bytes.
#CP(setssbsy) If busy bit in token is set.
If in 32-bit or compatibility mode, and the address in token is not below 4G.Opcode/
F3 0F 01 E8
SETSSBSYZO V/V CET_SS Set busy flag in supervi sor shadow stack token reference by 
IA32_PL0_SSP.
ZO N/A N/A N/A N/ASETSSBSY—Mark Shadow Stack BusyINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-615#PF(fault-code) If a page fault occurs.
#UD The SETSSBSY instruction is not recognized in real-address mode. 
#UD The SETSSBSY instruction is not recognized in virtual-8086 mode. 
Same as protected mode exceptions.SFENCE—Store FenceINSTRUCTION SET REFERENCE, M-U
4-616 Vol. 2BSFENCE—Store Fence
Orders processor execution relative to all memory stores prior to the SFENCE instruction. The processor ensures 
that every store prior to SFENCE is globally visible befo re any store after SFENCE becomes globally visible. The 
SFENCE instruction is ordered with respect to memory stores, other SFENCE instructions, MFENCE instructions, 
and any serializing instructions (such as the CPUID instruction). It is not ordered with respect to memory loads or 
the LFENCE instruction. 
out-of-order issue, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or 
knows that the data is weakly ordered varies among applic ations and may be unknown to the producer of this data. 
The SFENCE instruction provides a performance-efficient way of ensuring store ordering between routines that 
produce weakly-ordered results and routines that consume this data.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.Specification of the instruction's opcode above indicates a ModR/M byte of F8. For this instruction, the processor 
ignores the r/m field of the ModR/M byte. Thus, SFENCE is encoded by any opcode of the form 0F AE Fx, where x is 
Operation
Wait_On_Following_Stores_Until(pre ceding_stores_gl obally_visible);
void _mm_sfence(void)
#UD If CPUID.01H:EDX.SSE[bit 25] = 0.
If the LOCK prefix is used.Opcode* Instruction Op/ 
En64-Bit 
NP 0F AE F8 SFENCE ZO Valid Valid Serializes store operations.
ZO N/A N/A N/A N/ASGDT—Store Global Descriptor Table RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-617SGDT—Store Global Desc riptor Table Register
Stores the content of the global descriptor table regist er (GDTR) in the destination operand. The destination 
operand specifies a memory location. 
In legacy or compatibility mode, the destination operand is a 6-byte memory location. If the operand-size attribute 
is 16 or 32 bits, the 16-bit limit field of the register is stored in the low 2 bytes of the memory location and the 32-
bit base address is stored in the high 4 bytes.
In 64-bit mode, the operand size is fixed at 8+2 bytes. The instruction stores an 8-byte base and a 2-byte limit.
SGDT is useful only by operating-system software. However,  it can be used in application programs without causing 
an exception to be generated if CR4.UMIP = 0. See “LGD T/LIDT—Load Global/Interrupt Descriptor Table Register” 
in Chapter 3, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for information on 
loading the GDTR and IDTR.
The 16-bit form of the SGDT is compatible with the Inte l 286 processor if the upper 8 bits are not referenced. The 
Intel 286 processor fills these bits with 1s; processor gene rations later than the Intel 2 86 processor fill these bits 
with 0s.
Operation
IF instruction is SGDT
IF OperandSize =16 or OperandSize = 32 (* Legacy or Compatibility Mode *)
THEN 
DEST[0:15] := GDTR(Limit);DEST[16:47] := GDTR(Base); (* Fu ll 32-bit base address stored *)
FI;
ELSE (* 64-bit Mode *)
DEST[0:15] := GDTR(Limit);DEST[16:79] := GDTR(Base); (* Fu ll 64-bit base address stored *)
FI; 
FI;
NOTES:
En64-Bit 
0F 01 /0 SGDT m M Valid Valid Store GDTR to m.
M ModRM:r/m (w) N/A N/A N/ASGDT—Store Global Descriptor Table RegisterINSTRUCTION SET REFERENCE, M-U
4-618 Vol. 2BProtected Mode Exceptions
selector.
If CR4.UMIP = 1 and CPL > 0.
#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled and an una ligned memory reference is made while CPL = 3.
If CR4.UMIP = 1.
#UD If the LOCK prefix is used.#GP(0) If the memory address is in a non-canonical form.
#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled and an una ligned memory reference is made while CPL = 3.SHA1RNDS4—Perform Four Rounds of SHA1 OperationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-619SHA1RNDS4—Perform Four Rounds of SHA1 Operation
The SHA1RNDS4 instruction performs four rounds of SHA1 op eration using an initial SHA1 state (A,B,C,D) from the 
first operand (which is a source operand and the destination operand) and some pre-computed sum of the next 4 
round message dwords, and state variable E from the seco nd operand (a source operand). The updated SHA1 state 
(A,B,C,D) after four rounds of processing  is stored in the destination operand.
Operation
SHA1RNDS4 
The function f() and Constant K are dependent on the value of the immediate.
IF ( imm8[1:0] = 0 )
THEN f() := f0(), K := K0; 
ELSE IF ( imm8[1:0] = 1 ) 
THEN f() := f1(), K := K1; 
ELSE IF ( imm8[1:0] = 2 ) 
THEN f() := f2(), K := K2; 
ELSE IF ( imm8[1:0] = 3 ) 
THEN f() := f3(), K := K3; 
FI;
A := SRC1[127:96]; 
B := SRC1[95:64]; C := SRC1[63:32]; D := SRC1[31:0]; W
0E := SRC2[127:96]; 
W1 := SRC2[95:64]; 
W2 := SRC2[63:32]; 
W3 := SRC2[31:0]; 
Round i = 0 operation:
A_1 := f (B, C, D) + (A ROL 5) +W0E +K; 
B_1 := A; C_1 := B ROL 30; D_1 := C; E_1 := D; 
FOR i = 1 to 3
A_(i +1) := f (B_i, C_i, D_i) + (A_i ROL 5) +W
i+ E_i +K; Opcode/
NP 0F 3A CC /r ib
SHA1RNDS4 xmm1, 
xmm2/m128, imm8RMI V/V SHA Performs four rounds of SHA1 operation operating on SHA1 state 
(A,B,C,D) from xmm1, with a pre-computed sum of the next 4 round 
message dwords and state variable E from xmm2/m128. The immediate byte controls logic functions and round constants.
RMI ModRM:reg (r, w) ModRM:r/m (r) imm8SHA1RNDS4—Perform Four Roun ds of SHA1 OperationINSTRUCTION SET REFERENCE, M-U
4-620 Vol. 2BB_(i +1) := A_i; 
C_(i +1) := B_i ROL 30; D_(i +1) := C_i; E_(i +1) := D_i; 
ENDFOR
DEST[127:96] := A_4; 
DEST[95:64] := B_4; DEST[63:32] := C_4; DEST[31:0] := D_4; 
SHA1RNDS4 __m128i _mm_sha1rnds4_epu32(__m128i, __m128i, const int);
None.
None.

FOR i = 1 to 3
ENDFOR
None.
None.
See Table 2-21, “Type 4 Class Exception Conditions.”SHA1NEXTE—Calculate SHA1 State Variable E After Four RoundsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-621SHA1NEXTE—Calculate SHA1 State Variable E After Four Rounds
The SHA1NEXTE calculates the SHA1 state variable E afte r four rounds of operation from the current SHA1 state 
variable A in the destination operand. The calculated valu e of the SHA1 state variable E is added to the source 
operand, which contains the scheduled dwords.
Operation
SHA1NEXTE 
TMP := (SRC1[127:96] ROL 30); 
DEST[127:96] := SRC2[127:96] + TMP; 
DEST[95:64] := SRC2[95:64]; DEST[63:32] := SRC2[63:32]; DEST[31:0] := SRC2[31:0]; 
SHA1NEXTE __m128i _mm_sha1ne xte_epu32(__m128i, __m128i);
None.
None.
See Table 2-21, “Type 4 Class Exception Conditions.”Opcode/
NP 0F 38 C8 /r 
SHA1NEXTE xmm1, 
xmm2/m128RM V/V SHA Calculates SHA1 state variable E after four rounds of operation 
from the current SHA1 state variable A in xmm1. The calculated 
value of the SHA1 state variable E is added to the scheduled dwords in xmm2/m128, and stored  with some of the scheduled 
dwords in xmm1.
RM ModRM:reg (r, w) ModRM:r/m (r) N/ASHA1MSG1—Perform an Intermediate Calculat ion for the Next Four SHA1 Message DwordsINSTRUCTION SET REFERENCE, M-U
4-622 Vol. 2BSHA1MSG1—Perform an Intermediate Calculatio n for the Next Four SHA1 Message Dwords
The SHA1MSG1 instruction is one of two SHA1 message sch eduling instructions. The instruction performs an inter-
mediate calculation for the next four SHA1 message dwords.
Operation
SHA1MSG1 
W0 := SRC1[127:96] ; W1 := SRC1[95:64] ; W2 := SRC1[63: 32] ; W3 := SRC1[31: 0] ; W4 := SRC2[127:96] ; W5 := SRC2[95:64] ; 
DEST[127:96] := W2 XOR W0; 
DEST[95:64] := W3 XOR W1; DEST[63:32] := W4 XOR W2; DEST[31:0] := W5 XOR W3; 
SHA1MSG1 __m128i _mm_sha1msg1_epu32(__m128i, __m128i);
None.
None.
NP 0F 38 C9 /r 
SHA1MSG1 xmm1, 
xmm2/m128RM V/V SHA Performs an intermediate calculation for the next four SHA1 mes-
sage dwords using previous message dwords from xmm1 and 
xmm2/m128, storing the result in xmm1.
RM ModRM:reg (r, w) ModRM:r/m (r) N/ASHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message DwordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-623SHA1MSG2—Perform a Final Calculation for  the Next Four SHA1 Message Dwords
The SHA1MSG2 instruction is one of two SHA1 message scheduling instructions. The instruction performs the final 
calculation to derive the next four SHA1 message dwords.
Operation
SHA1MSG2 
W13 := SRC2[95:64] ; W14 := SRC2[63: 32] ; W15 := SRC2[31: 0] ; W16 := (SRC1[127:96] XOR W13 ) ROL 1; W17 := (SRC1[95:64] XOR W14) ROL 1; W18 := (SRC1[63: 32] XOR W15) ROL 1; W19 := (SRC1[31: 0] XOR W16) ROL 1; 
DEST[127:96] := W16; 
DEST[95:64] := W17; DEST[63:32] := W18; DEST[31:0] := W19; 
SHA1MSG2 __m128i _mm_sha1msg2_epu32(__m128i, __m128i);
None.
None.
NP 0F 38 CA /r 
SHA1MSG2 xmm1, 
xmm2/m128RM V/V SHA Performs the final calculation for the next four SHA1 message 
dwords using intermediate results from xmm1 and the previous 
message dwords from xmm2/m128, storing the result in xmm1.
RM ModRM:reg (r, w) ModRM:r/m (r) N/ASHA256RNDS2—Perform Two Ro unds of SHA256 OperationINSTRUCTION SET REFERENCE, M-U
4-624 Vol. 2BSHA256RNDS2—Perform Two Rounds of SHA256 Operation
The SHA256RNDS2 instruction performs 2 rounds of SHA2 56 operation using an initial SHA256 state (C,D,G,H) 
from the first operand, an initial SHA256 state (A,B,E,F) from the second operand, and a pre-computed sum of the 
next 2 round message dwords and the corresponding round constants from the implicit operand xmm0. Note that 
only the two lower dwords of XMM0 are used by the instruction.
The updated SHA256 state (A,B,E,F) is written to the firs t operand, and the second operand can be used as the 
updated state (C,D,G,H) in later rounds.
Operation
SHA256RNDS2 
A_0 := SRC2[127:96]; B_0 := SRC2[95:64]; C_0 := SRC1[127:96]; D_0 := SRC1[95:64]; E_0 := SRC2[63:32]; F_0 := SRC2[31:0]; G_0 := SRC1[63:32]; H_0 := SRC1[31:0]; WK
0 := XMM0[31: 0]; 
WK1 := XMM0[63: 32]; 
FOR i = 0 to 1
A_(i +1) := Ch (E_i, F_i, G_i) + Σ1( E_i) +WKi+ H_i + Maj(A_i , B_i, C_i) + Σ0( A_i); 
B_(i +1) := A_i; C_(i +1) := B_i ; D_(i +1) := C_i; E_(i +1) := Ch (E_i, F_i, G_i) + Σ
1( E_i) +WKi+ H_i + D_i; 
F_(i +1) := E_i ; G_(i +1) := F_i; H_(i +1) := G_i; 
ENDFOR
DEST[127:96] := A_2; 
DEST[95:64] := B_2; DEST[63:32] := E_2; DEST[31:0] := F_2; Opcode/
NP 0F 38 CB /r 
SHA256RNDS2 xmm1, 
xmm2/m128, <XMM0>RMI V/V SHA Perform 2 rounds of SHA256 operation using an initial SHA256 
state (C,D,G,H) from xmm1, an initial SHA256 state (A,B,E,F) from 
xmm2/m128, and a pre-computed sum of the next 2 round mes-sage dwords and the corresponding round constants from the 
implicit operand XMM0, storing the updated SHA256 state 
(A,B,E,F) result in xmm1.
RMI ModRM:reg (r, w) ModRM:r/m (r) Implicit XMM0 (r)SHA256RNDS2—Perform Two Rounds of SHA256 OperationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-625Intel C/C++ Compiler Intrinsic Equivalent
SHA256RNDS2 __m128i _mm_sha256rnds2_epu32(__m128i, __m128i, __m128i);
None.
None.
See Table 2-21, “Type 4 Class Exception Conditions.”SHA256MSG1—Perform an Intermediate Calculat ion for the Next Four SHA256 Message DwordsINSTRUCTION SET REFERENCE, M-U
4-626 Vol. 2BSHA256MSG1—Perform an Intermediate Calcul ation for the Next Four SHA256 Message 
Dwords
The SHA256MSG1 instruction is one of two SHA256 message  scheduling instructions. The instruction performs an 
intermediate calculation for the next four SHA256 message dwords.
Operation
SHA256MSG1 
W4 := SRC2[31: 0] ; W3 := SRC1[127:96] ; W2 := SRC1[95:64] ; W1 := SRC1[63: 32] ; W0 := SRC1[31: 0] ; 
DEST[127:96] := W3 + σ
0( W4); 
DEST[95:64] := W2 + σ0( W3); 
DEST[63:32] := W1 + σ0( W2); 
DEST[31:0] := W0 + σ0( W1); 
SHA256MSG1 __m128i _mm_sha256msg1_epu32(__m128i, __m128i);
None.
None.
Mode 
Feature 
NP 0F 38 CC /r 
SHA256MSG1 xmm1, xmm2/m128RM V/V SHA Performs an intermediate calculation for the next four SHA256 
message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.
RM ModRM:reg (r, w) ModRM:r/m (r) N/ASHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message DwordsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-627SHA256MSG2—Perform a Final Calculation for  the Next Four SHA256 Message Dwords
The SHA256MSG2 instruction is one of two SHA2 message  scheduling instructions. The instruction performs the 
final calculation for the next four SHA256 message dwords.
Operation
SHA256MSG2 
W14 := SRC2[95:64] ; W15 := SRC2[127:96] ; W16 := SRC1[31: 0] + σ
1( W14) ; 
W17 := SRC1[63: 32] + σ1( W15) ; 
W18 := SRC1[95: 64] + σ1( W16) ; 
W19 := SRC1[127: 96] + σ1( W17) ; 
DEST[127:96] := W19 ; 
DEST[95:64] := W18 ; DEST[63:32] := W17 ; DEST[31:0] := W16; 
SHA256MSG2 __m128i _mm_sha256msg2_epu32(__m128i, __m128i);
None.
None.
NP 0F 38 CD /r 
SHA256MSG2 xmm1, 
xmm2/m128RM V/V SHA Performs the final calculation for the next four SHA256 message 
dwords using previous message dwords from xmm1 and 
RM ModRM:reg (r, w) ModRM:r/m (r) N/ASHLD—Double Precision Shift LeftINSTRUCTION SET REFERENCE, M-U
4-628 Vol. 2BSHLD—Double Precision Shift Left
The SHLD instruction is used for multi- precision shifts of 64 bits or more.

None.
None.
The instruction shifts the first operand (destination operan d) to the left the number of bits specified by the third 
operand (count operand). The second operand (source operan d) provides bits to shift in from the right (starting 
with bit 0 of the destination operand). 
The destination operand can be a register or a memory location; the source operand is a register. The count 
operand is an unsigned integer that can be stored in an immediate byte or in the CL register. If the count operand 
is CL, the shift count is the logical AND of CL and a co unt mask. In non-64-bit modes and default 64-bit mode; only 
bits 0 through 4 of the count are used. This masks the coun t to a value between 0 and 31. If a count is greater than 
the operand size, the result is undefined.
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit 
shift, the OF flag is set if a sign change occurred; otherwis e, it is cleared. If the count operand is 0, flags are not 
affected.
access to additional registers (R8-R15). Using a REX prefix  in the form of REX.W promotes operation to 64 bits 
(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and 
limits.
Operation
IF (In 64-Bit Mode and REX.W = 1) 
THEN COUNT := COUNT MOD 64;ELSE COUNT := COUNT MOD 32;
FISIZE := OperandSize;IF COUNT =
 0
THEN 
No operation;
ELSEOpcode* Instruction Op/ 
En64-Bit 
0F A4 /r ib SHLD r/m16, r16, imm8 MRI Valid Valid Shift r/m16 to left imm8 places while shifting 
bits from r16 in from the right.
0F A5 /r SHLD r/m16, r16, CL MRC Valid Valid Shift r/m16 to left CL places while shifting bits 
from r16 in from the right.
0F A4 /r ib SHLD r/m32, r32, imm8 MRI Valid Valid Shift r/m32 to left imm8 places while shifting 
bits from r32 in from the right.
REX.W + 0F A4 /r ib SHLD r/m64, r64, imm8 MRI Valid N. E. Shift r/m64 to left imm8 places while shifting 
bits from r64 in from the right.
0F A5 /r SHLD r/m32, r32, CL MRC Valid Valid Shift r/m32 to left CL places while shifting bits 
from r32 in from the right.
REX.W + 0F A5 /r SHLD r/m64, r64, CL MRC Valid N.E. Shi ft r/m64 to left CL places while shifting bits 
from r64 in from the right.
MRI ModRM:r/m (w) ModRM:reg (r) imm8 N/A
MRC ModRM:r/m (w) ModRM:reg (r) CL N/ASHLD—Double Precision Shift LeftINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-629IF COUNT > SIZE
THEN (* Bad parameters *)
DEST is undefined;CF, OF, SF, ZF, AF, PF are undefined;
ELSE (* Perform the shift *)
CF := BIT[DEST, SIZE – COUNT];(* Last bit shifted out on exit *)FOR i := SIZE – 1 DOWN TO COUNT
DO
Bit(DEST, i) := Bit(DEST, i – COUNT);
OD;
FOR i := COUNT – 1 DOWN TO 0
DO
BIT[DEST, i] := BIT[SRC, i – COUNT + SIZE];
OD;
FI;
FI;
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, 
ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change 
occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag 
is undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the 
Same exceptions as in protected mode.SHLD—Double Precision Shift LeftINSTRUCTION SET REFERENCE, M-U
4-630 Vol. 2B64-Bit Mode Exceptions
#UD If the LOCK prefix is used.SHRD—Double Precision Shift RightINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-631SHRD—Double Precision Shift Right
The SHRD instruction is useful for multi-precision shifts of 64 bits or more.
The instruction shifts the first operand (destination operan d) to the right the number of bits specified by the third 
operand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with 
the most significant bit of the destination operand). 
operand is an unsigned integer that can be stored in an im mediate byte or the CL register. If the count operand is 
CL, the shift count is the logical AND of CL and a count  mask. In non-64-bit modes and default 64-bit mode, the 
width of the count mask is 5 bits. Only bits 0 through 4 of the count register are used (masking the count to a value 
between 0 and 31). If the count is greater th an the operand size, the result is undefined.
affected.
limits.
Operation
FISIZE := OperandSize;IF COUNT
 = 0
THEN 
En64-Bit 
0F AC /r ib SHRD r/m16, r16, imm8 MRI Valid Valid Shift r/m16 to right imm8 places while 
shifting bits from r16 in from the left.
0F AD /r SHRD r/m16, r16, CL MRC Valid Valid Shi ft r/m16 to right CL places while shifting 
bits from r16 in from the left.
0F AC /r ib SHRD r/m32, r32, imm8 MRI Valid Valid Shift r/m32 to right imm8 places while 
shifting bits from r32 in from the left.
REX.W + 0F AC /r ib SHRD r/m64, r64, imm8 MRI V alid N.E. Shift r/m64 to right imm8 places while 
shifting bits from r64 in from the left.
0F AD /r SHRD r/m32, r32, CL MRC Valid Valid Shi ft r/m32 to right CL places while shifting 
bits from r32 in from the left.
REX.W + 0F AD /r SHRD r/m64, r64, CL MRC Valid N. E. Shift r/m64 to right CL  places while shifting 
bits from r64 in from the left.
MRC ModRM:r/m (w) ModRM:reg (r) CL N/ASHRD—Double Precision Shift RightINSTRUCTION SET REFERENCE, M-U
4-632 Vol. 2BIF COUNT > SIZE
CF := BIT[DEST, COUNT – 1]; (* Last bit shifted out on exit *)FOR i := 0 TO SIZE – 1 – COUNT
DO
BIT[DEST, i] := BIT[DEST, i + COUNT];
OD;
FOR i := SIZE – COUNT TO SIZE – 1
DO
BIT[DEST,i] := BIT[SRC, i + COUNT – SIZE];
OD;
FI;
FI;
If the count is 1 or greater, the CF flag is filled with th e last bit shifted out of the destination operand and the SF, ZF, 
and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred; 
otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shif t occurs, the AF flag is unde-
fined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags 

DO
OD;
DO
OD;
FI;
FI;
Same exceptions as in protected mode.SHRD—Double Precision Shift RightINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-63364-Bit Mode Exceptions
#UD If the LOCK prefix is used.SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-634 Vol. 2BSHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point Values
Selects a double precision floating-point value of an input pair using a bit control and move to a designated element 
of the destination operand. The low-to-high order of doub le precision element of the destination operand is inter-
leaved between the first source operand and the second sour ce operand at the granularity of input pair of 128 bits. 
Each bit in the imm8 byte, starting from bit 0, is the se lect control of the corresponding element of the destination 
to received the shuffled result of an input pair. 
64-bit memory location The destination operand is a ZMM/ YMM/XMM register updated according to the writemask. 
The select controls are the lowe r 8/4/2 bits of the imm8 byte.
register or a 256-bit memory location. The destination operan d is a YMM register. The select controls are the bit 3:0 
of the imm8 byte, imm8[7:4) are ignored.
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of Opcode/
Mode 
Feature 
66 0F C6 /r ib
SHUFPD xmm1, xmm2/m128, imm8A V/V SSE2 Shuffle two pairs of double precision floating-point 
values from xmm1 and xmm2/m128 using imm8 to 
select from each pair, interleaved result is stored in 
xmm1.
VEX.128.66.0F.WIG C6 /r ib
VSHUFPD xmm1, xmm2, xmm3/m128, 
imm8B V/V AVX Shuffle two pairs of double precision floating-point 
values from xmm2 and xmm3/m128 using imm8 to 
xmm1.
VEX.256.66.0F.WIG C6 /r ib
VSHUFPD ymm1, ymm2, ymm3/m256, 
imm8B V/V AVX Shuffle four pairs of double precision floating-point 
values from ymm2 and ym m3/m256 using imm8 to 
xmm1.
EVEX.128.66.0F.W1 C6 /r ib
VSHUFPD xmm1{k1}{z}, xmm2, 
AVX512FShuffle two pairs of double precision floating-point 
values from xmm2 and xmm3/m128/m64bcst using 
imm8 to select from each pair. store interleaved results in xmm1 subject to writemask k1.
EVEX.256.66.0F.W1 C6 /r ib
VSHUFPD ymm1{k1}{z}, ymm2, 
AVX512FShuffle four pairs of double precision floating-point 
values from ymm2 and ymm3/m256/m64bcst using 
imm8 to select from each pair. store interleaved results in ymm1 subject to writemask k1.
EVEX.512.66.0F.W1 C6 /r ib
VSHUFPD zmm1{k1}{z}, zmm2, 
zmm3/m512/m64bcst, imm8C V/V AVX512F Shuffle eight pairs of double precision floating-point 
values from zmm2 and zmm3/m512/m64bcst using 
imm8 to select from each pair. store interleaved results in zmm1 subject to writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-635the corresponding ZMM register destination are zeroed. Th e select controls are the bit 1:0 of the imm8 byte, 
imm8[7:2) are ignored.
nation operand and the first source operand is the same and is an XMM register. The upper bits (MAXVL-1:128) of 
the corresponding ZMM register destination are unmodified. The select controls are the bit 1:0 of the imm8 byte, 
Operation
VSHUFPD (EVEX Encoded Versions Wh en SRC2 is a Vector Register)
IF IMM0[0] = 0
THEN TMP_DEST[63:0] := SRC1[63:0]ELSE TMP_DEST[63:0] := SRC1[127:64] FI;
IF IMM0[1] = 0
THEN TMP_DEST[127:64] := SRC2[63:0]ELSE TMP_DEST[127:64]  := SRC2[127:64] FI;
IF VL >= 256
IF IMM0[2] = 0
THEN TMP_DEST[191:128] := SRC1[191:128]ELSE TMP_DEST[191:128] := SRC1[255:192] FI;
IF IMM0[3] = 0
THEN TMP_DEST[255:192] := SRC2[191:128]ELSE TMP_DEST[255:192] := SRC2[255:192] FI;
IF IMM0[4] = 0
THEN TMP_DEST[319:256] := SRC1[319:256]ELSE TMP_DEST[319:256] := SRC1[383:320] FI;
IF IMM0[5] = 0
THEN TMP_DEST[383:320] := SRC2[319:256]ELSE TMP_DEST[383:320] := SRC2[383:320] FI;
IF IMM0[6] = 0
THEN TMP_DEST[447:384] := SRC1[447:384]ELSE TMP_DEST[447:384] := SRC1[511:448] FI;
IF IMM0[7] = 0
THEN TMP_DEST[511:448] := SRC2[447:384]ELSE TMP_DEST[511:448] := SRC2[511:448] FI;
i := j * 64Figure 4-25.  256-bit VSHUFPD Operation of Four Pairs of Double Precision Floating-Point ValuesY2 or Y3 X2 or X3 Y0 or Y1 X0 or X1 DESTX3 X2 SRC1 X1 X0
Y3 Y2 Y1 Y0 SRC2SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-636 Vol. 2BIF k1[j] OR *no writemask*
FI
FI;
VSHUFPD (EVEX Encoded Versions When SRC2 is Memory)
i := j * 64IF (EVEX.b = 1) 
FI;
ENDFOR;IF IMM0[0] = 0
THEN TMP_DEST[127:64] := TMP_SRC2[63:0]ELSE TMP_DEST[127:64] := TMP_SRC2[127:64] FI;
IF VL >= 256
THEN TMP_DEST[255:192] := TMP_SRC2[191:128]ELSE TMP_DEST[255:192] :=  TMP_SRC2[255:192] FI;
THEN TMP_DEST[383:320] := TMP_SRC2[319:256]ELSE TMP_DEST[383:320] :=  TMP_SRC2[383:320] FI;
THEN TMP_DEST[511:448] := TMP_SRC2[447:384]ELSE TMP_DEST[511:448] :=  TMP_SRC2[511:448] FI;
THEN DEST[i+63:i] := TMP_DEST[i+63:i]SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-637ELSE 
FI
FI;
VSHUFPD (VEX.256 Encoded Version)
THEN DEST[63:0] := SRC1[63:0]ELSE DEST[63:0] := SRC1[127:64] FI;
THEN DEST[127:64] := SRC2[63:0]ELSE DEST[127:64] := SRC2[127:64] FI;
THEN DEST[191:128] := SRC1[191:128]ELSE DEST[191:128] :=  SRC1[255:192] FI;
THEN DEST[255:192] := SRC2[191:128]ELSE DEST[255:192] :=  SRC2[255:192] FI;

FI
FI;
DEST[MAXVL-1:256 ] (Unmodified)
VSHUFPD (VEX.128 Encoded Version)
VSHUFPD (128-bit Legacy SSE Version)
VSHUFPD __m512d _mm512_shuffle_pd(__m512d a, __m512d b, int imm);
VSHUFPD __m512d _mm512_mask_shuffle_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);
VSHUFPD __m512d _mm512_maskz_shuffle_pd( __mmask8 k, __m512d a, __m512d b, int imm);VSHUFPD __m256d _mm256_shuffle_pd (__m256d a, __m256d b, const int select);VSHUFPD __m256d _mm256_mask_shuffle_pd(__m256d s, __mmask8 k, __m256d a, __m256d b, int imm);
VSHUFPD __m256d _mm256_maskz_shuffle_pd( __mmask8 k, __m256d a, __m256d b, int imm);SHUFPD __m128d _mm_shuffle_pd (__m128d  a, __m128d b, const int select);
VSHUFPD __m128d _mm_mask_shuffle_pd(__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);
VSHUFPD __m128d _mm_maskz_shuffle_pd( __mmask8 k, __m128d a, __m128d b, int imm);SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-638 Vol. 2BSIMD Floating-Point Exceptions
None.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”SHUFPS—Packed Interleave Shuffle of Quadruplets of Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-639SHUFPS—Packed Interleave Shuffle of Quadrupl ets of Single Precision Floating-Point Values
Selects a single precision floating-point value of an inpu t quadruplet using a two-bit control and move to a desig-
nated element of the destination operand. Each 64-bit elem ent-pair of a 128-bit lane of the destination operand is 
interleaved between the corresponding lane of the first so urce operand and the second source operand at the gran-
ularity 128 bits. Each two bits in the imm8 byte, starting  from bit 0, is the select control of the corresponding 
element of a 128-bit lane of the destination to received the shuffled result of an input quadruplet. The two lower 
elements of a 128-bit lane in the destination receives shuf fle results from the quadruple of the first source operand. 
The next two elements of the destination receives shuffle results from the quadruple of the second source operand. 
32-bit memory location. The destinatio n operand is a ZMM/YMM/XMM register updated according to the writemask. 
imm8[7:0] provides 4 select controls for each  applicable 128-bit lane of the destination.
register or a 256-bit memory location. The destination op erand is a YMM register. Imm8[7:0] provides 4 select 
controls for the high and low 128-bit of the destination.
the corresponding ZMM register destination are zeroed. Imm8 [7:0] provides 4 select controls for each element of 
the destination.Opcode/
Mode 
Feature 
NP 0F C6 /r ib
SHUFPS xmm1, xmm3/m128, imm8A V/V SSE Select from quadruplet of single precision floating-point 
values in xmm1 and xmm2/m128 using imm8, 
interleaved result pair s are stored in xmm1.
VEX.128.0F.WIG C6 /r ib
VSHUFPS xmm1, xmm2, xmm3/m128, imm8B V/V AVX Select from quadruplet of single precision floating-point 
values in xmm1 and xmm2/m128 using imm8, interleaved result pair s are stored in xmm1.
VEX.256.0F.WIG C6 /r ib
VSHUFPS ymm1, ymm2, ymm3/m256, 
imm8B V/V AVX Select from quadruplet of single precision floating-point 
values in ymm2 and ymm3/m256 using imm8, 
interleaved result pair s are stored in ymm1.
EVEX.128.0F.W0 C6 /r ib
VSHUFPS xmm1{k1}{z}, xmm2, 
xmm3/m128/m32bcst, imm8C V/V AVX512VL
AVX512FSelect from quadruplet of single precision floating-point 
interleaved result pairs are stored in xmm1, subject to 
EVEX.256.0F.W0 C6 /r ib
VSHUFPS ymm1{k1}{z}, ymm2, 
ymm3/m256/m32bcst, imm8C V/V AVX512VL
interleaved result pairs are stored in ymm1, subject to 
EVEX.512.0F.W0 C6 /r ib
VSHUFPS zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcst, imm8C V/V AVX512F Select from quadruplet of single precision floating-point 
values in zmm2 and zmm3/m512 using imm8, 
interleaved result pairs are stored in zmm1, subject to 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8SHUFPS—Packed Interleave Shuffle of Quadruplet s of Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-640 Vol. 2B128-bit Legacy SSE version: The source can be an XMM register or an 128-bit memory location. The destination is 
not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM 
register destination are unmodified. Imm8[7:0] provides 4 select controls for each element of the destination.
Operation
Select4(SRC, control) {
CASE (control[1:0]) OF
0: TMP := SRC[31:0];1: TMP := SRC[63:32];2: TMP := SRC[95:64];3: TMP := SRC[127:96];
ESAC;RETURN TMP}
VPSHUFPS (EVEX Encoded Versions When SRC2 is a Vector Register)
TMP_DEST[31:0] := Select4( SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] := Select4( SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] := Select4( SRC2[127:0], imm8[5:4]);
TMP_DEST[127:96] := Select4(SRC2[127:0], imm8[7:6]);IF VL >= 256
TMP_DEST[159:128] := Select4( SRC1[255:128], imm8[1:0]);
TMP_DEST[191:160] := Select4( SRC1[255:128], imm8[3:2]);
TMP_DEST[223:192] := Select4( SRC2[255:128], imm8[5:4]);
TMP_DEST[255:224] := Select4( SRC2[255:128], imm8[7:6]);
TMP_DEST[287:256] := Select4( SRC1[383:256], imm8[1:0]);
TMP_DEST[319:288] := Select4( SRC1[383:256], imm8[3:2]);
TMP_DEST[351:320] := Select4( SRC2[383:256], imm8[5:4]);
TMP_DEST[383:352] := Select4( SRC2[383:256], imm8[7:6]);
TMP_DEST[415:384] := Select4( SRC1[511:384], imm8[1:0]);
TMP_DEST[447:416] := Select4( SRC1[511:384], imm8[3:2]);
TMP_DEST[479:448] := Select4( SRC2[511:384], imm8[5:4]);
TMP_DEST[511:480] := Select4( SRC2[511:384], imm8[7:6]);
i := j * 32IF k1[j] OR *no writemask*Figure 4-26.  256-bit VSHUFPS Operation of Selection from Input Quadruplet and Pair-wise Interleaved ResultY7 .. Y4 X7 .. X4 Y3 ..Y0 X3 .. X0 DESTSRC1 X0
X3 .. X0 Y7 .. Y4 X7 .. X4 Y3 ..Y0SHUFPS—Packed Interleave Shuffle of Quadruplets of Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-641THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE 
FI
FI;
VPSHUFPS (EVEX Encoded Versions When SRC2 is Memory)
i := j * 32IF (EVEX.b = 1) 
FI;
ENDFOR;TMP_DEST[31:0] := Select4( SRC1[127:0], imm8[1:0]);
TMP_DEST[95:64] := Select4( TMP_SRC2[127:0], imm8[5:4]);
TMP_DEST[127:96] := Select4( TMP_SRC2[127:0], imm8[7:6]);
IF VL >= 256
TMP_DEST[223:192] := Select4(TMP_SRC2[255:128], imm8[5:4]);TMP_DEST[255:224] := Select4(TMP_SRC2[255:128], imm8[7:6]);
TMP_DEST[351:320] := Select4(TMP_SRC2[383:256], imm8[5:4]);TMP_DEST[383:352] := Select4(TMP_SRC2[383:256], imm8[7:6]);TMP_DEST[415:384] := Select4( SRC1[511:384], imm8[1:0]);
TMP_DEST[479:448] := Select4(TMP_SRC2[511:384], imm8[5:4]);TMP_DEST[511:480] := Select4(TMP_SRC2[511:384], imm8[7:6]);

IF VL >= 256
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0SHUFPS—Packed Interleave Shuffle of Quadruplet s of Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-642 Vol. 2BVSHUFPS (VEX.256 Encoded Version)
DEST[31:0] := Select4( SRC1[127:0], imm8[1:0]);
DEST[63:32] := Select4(SR C1[127:0], imm8[3:2]);
DEST[95:64] := Select4(SR C2[127:0], imm8[5:4]);
DEST[127:96] := Select4( SRC2[127:0], imm8[7:6]);
DEST[159:128] := Select4( SRC1[255:128], imm8[1:0]);
DEST[191:160] := Select4( SRC1[255:128], imm8[3:2]);
DEST[223:192] := Select4( SRC2[255:128], imm8[5:4]);
DEST[255:224] := Select4( SRC2[255:128], imm8[7:6]);
VSHUFPS (VEX.128 Encoded Version)
SHUFPS (128-bit Legacy SSE Version)
VSHUFPS __m512 _mm512_shuffle_ps( __m512 a, __m512 b, int imm);
VSHUFPS __m512 _mm512_mask_shuffle_ps(__m512 s,  __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFPS __m512 _mm512_maskz_shuffle_ps(__mma sk16 k, __m512 a, __m512 b, int imm);
VSHUFPS __m256 _mm256_shuffle_ps (__m 256 a, __m256 b, const int select);
VSHUFPS __m256 _mm256_mask_shuffle_ps(__m256 s,  __mmask8 k, __m256 a, __m256 b, int imm);
VSHUFPS __m256 _mm256_maskz_shuffle_ps(__mmask8 k, __m256 a, __m256 b, int imm);SHUFPS __m128 _mm_shuffle_ps (__m12 8 a, __m128 b, const int select);
VSHUFPS __m128 _mm_mask_shuffle_ps(__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VSHUFPS __m128 _mm_maskz_shuffle_ps(__mma sk8 k, __m128 a, __m128 b, int imm);
None.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”SIDT—Store Interrupt De scriptor Table RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-643SIDT—Store Interrupt Descriptor Table Register
Stores the content the interrupt descriptor table regist er (IDTR) in the destination operand. The destination 
operand specifies a 6-by te memory location. 
In non-64-bit modes, the 16-bit limit field of the register is stored in the low 2 bytes of the memory location and 
the 32-bit base address is stored in the high 4 bytes.
In 64-bit mode, the operand size fixed at 8+2 bytes. The instruction stores 8-byte ba se and 2-byte limit values.
SIDT is only useful in operating-system software; however,  it can be used in application programs without causing 
The 16-bit form of SIDT is compatible  with the Intel 286 processor if the upper 8 bits are not referenced. The Intel 
286 processor fills these bits with 1s; processor generation s later than the Intel 286 processor fill these bits with 
0s.
Operation
IF instruction is SIDT
THEN
THEN 
DEST[0:15] := IDTR(Limit);DEST[16:47] := IDTR(Base); FI; (* Full 32-bit base address stored *)
DEST[0:15] := IDTR(Limit);DEST[16:79] := IDTR(Base); (* Fu ll 64-bit base address stored *)
FI;
FI;
NOTES:
En64-Bit 
0F 01 /1 SIDT m MV a l i d V a l i d S t o r e  I D T R  t o  m.
M ModRM:r/m (w) N/A N/A N/ASIDT—Store Interrupt Descriptor Table RegisterINSTRUCTION SET REFERENCE, M-U
4-644 Vol. 2BProtected Mode Exceptions
selector.
#AC(0) If alignment checking is enabled and an una ligned memory reference is made while CPL = 3.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#UD If the LOCK prefix is used.#GP(0) If the memory address is in a non-canonical form.
#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled and an una ligned memory reference is made while CPL = 3.SLDT—Store Local Descriptor Table RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-645SLDT—Store Local Descriptor Table Register
Stores the segment selector from the local descriptor tabl e register (LDTR) in the destination operand. The desti-
nation operand can be a general-purpose register or a me mory location. The segment selector stored with this 
instruction points to the segment descriptor (located in th e GDT) for the current LDT. This instruction can only be 
executed in protected mode.
Outside IA-32e mode, when the destination operand is a 32- bit register, the 16-bit segment selector is copied into 
the low-order 16 bits of the register. The high-order 16 bits  of the register are cleared for the Pentium 4, Intel Xeon, 
and P6 family processors. They are undefined for Pentium, Intel486, and Intel386 processors. When the destina-
tion operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of 
the operand size.
In compatibility mode, when the destination operand is a 32- bit register, the 16-bit segment selector is copied into 
the low-order 16 bits of the register. The high-order 16 bits of the register are cleared. When the destination 
operand is a memory location, the segment selector is wr itten to memory as a 16-bit quantity, regardless of the 
operand size.
In 64-bit mode, using a REX prefix in the form of RE X.R permits access to additional registers (R8-R15). The 
behavior of SLDT with a 64-bit register is to zero-extend th e 16-bit selector and store it in the register. If the desti-
nation is memory and operand size is 64, SLDT will writ e the 16-bit selector to memory as a 16-bit quantity, 
regardless of the operand size.
Operation
DEST := LDTR(SegmentSelector);
None.
selector.
#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled and an un aligned memory reference is made while CPL = 3.
#UD The SLDT instruction is not recognized in real-address mode.Opcode* Instruction Op/ 
En64-Bit 
0F 00 /0 SLDT r/m16 M Valid Valid Stores segment selector from LDTR in r/m16 .
M ModRM:r/m (w) N/A N/A N/ASLDT—Store Local Descriptor Table RegisterINSTRUCTION SET REFERENCE, M-U
4-646 Vol. 2BVirtual-8086 Mode Exceptions
#UD The SLDT instruction is not recognized in virtual-8086 mode.

En64-Bit 
#UD If the LOCK prefix is used.SMSW—Store Machine Status WordINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-647SMSW—Store Machine Status Word
Stores the machine status word (bits 0 through 15 of contro l register CR0) into the destination operand. The desti-
nation operand can be a general-purpose register or a memory location.
In non-64-bit modes, when the destination operand is a 32 -bit register, the low-order 16 bits of register CR0 are 
copied into the low-order 16 bits of the register and th e high-order 16 bits are undefined. When the destination 
operand is a memory location, the low-order 16 bits of re gister CR0 are written to memory as a 16-bit quantity, 
In 64-bit mode, the behavior of the SMSW inst ruction is defined by the following examples:
•SMSW r16 operand size 16, store CR0[15:0] in r16
•SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32
•SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64
•SMSW m16 operand size 16, store CR0[15:0] in m16
•SMSW m16 operand size 32, store CR0[15:0] in m16 (not m32)
•SMSW m16 operands size 64, store CR0[15:0] in m16 (not m64)
SMSW is only useful in operating-system software. However,  it is not a privileged instruction and can be used in 
application programs if CR4.UMIP = 0. It is provided for compatibility with the Intel 286 processor. Programs and 
procedures intended to run on IA-32 and Intel 64 processo rs beginning with the Intel386 processors should use the 
MOV CR instruction to load the machine status word.
Operation
DEST := CR0[15:0]; 
(* Machine status word *)
En64-Bit 
0F 01 /4 SMSW r/m16 M Valid Valid Sto re machine status word to r/m16.
0F 01 /4 SMSW r32/m16 M Valid Valid Store machine status word in low-order 16 
bits of r32/m16; high-order 16 bits of r32 are 
REX.W + 0F 01 /4 SMSW r64/m16 M Valid Valid Store machine status word in low-order 16 
bits of r64/m16; high-order 16 bits of r32 are 
M ModRM:r/m (w) N/A N/A N/ASMSW—Store Machine Status WordINSTRUCTION SET REFERENCE, M-U
4-648 Vol. 2BProtected Mode Exceptions
selector.
#UD If the LOCK prefix is used.SQRTPD—Square Root of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-649SQRTPD—Square Root of Double Pr ecision Floating-Point Values
Performs a SIMD computation of the square roots of the tw o, four or eight packed double precision floating-point 
values in the source operand (the second operand) stores the packed double precision floating-point results in the 
destination operand (the first operand). 
ZMM/YMM/XMM register updated according to the writemask.
operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are 
zeroed.
tion operand is an XMM register. The upper bits (MAXVL-1 :128) of the corresponding ZMM register destination are 
zeroed.
tion is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM 
Mode 
Feature 
66 0F 51 /r
SQRTPD xmm1, xmm2/m128A V/V SSE2 Computes Square Roots of the packed double precision 
floating-point values in xmm2/m128 and stores the result in 
xmm1.
VEX.128.66.0F.WIG 51 /r
VSQRTPD xmm1, xmm2/m128A V/V AVX Computes Square Roots of the packed double precision 
floating-point values in xmm2/m128 and stores the result in xmm1.
VEX.256.66.0F.WIG 51 /r
VSQRTPD ymm1, ymm2/m256A V/V AVX Computes Square Roots of the packed double precision 
floating-point values in ymm2/m256 and stores the result in 
ymm1.
EVEX.128.66.0F.W1 51 /r
VSQRTPD xmm1 {k1}{z}, 
AVX512FComputes Square Roots of the packed double precision 
floating-point values in xmm2/m128/m64bcst and stores 
the result in xmm1 su bject to writemask k1.
EVEX.256.66.0F.W1 51 /r
VSQRTPD ymm1 {k1}{z}, 
ymm2/m256/m64bcstBV / V A V X 5 1 2 V L
floating-point values in ymm2/m256/m64bcst and stores 
the result in ymm1 subject to writemask k1.
EVEX.512.66.0F.W1 51 /r
VSQRTPD zmm1 {k1}{z}, zmm2/m512/m64bcst{er}B V/V AVX512F Computes Square Roots of the packed double precision 
floating-point values in zmm2/m512/m64bcst and stores the result in zmm1 su bject to writemask k1.
B Full ModRM:reg (w) ModRM:r/m (r) N/A N/ASQRTPD—Square Root of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-650 Vol. 2BOperation
VSQRTPD (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)
THEN
ELSE 
THEN DEST[i+63:i] := SQRT(SRC[63:0])ELSE DEST[i+63:i] := SQRT(SRC[i+63:i])
FI;
ELSE 
FI
FI;
VSQRTPD (VEX.256 Encoded Version)
DEST[63:0] := SQRT(SRC[63:0])DEST[127:64] := SQRT(SRC[127:64])DEST[191:128] := SQRT(SRC[191:128])DEST[255:192] := SQRT(SRC[255:192])DEST[MAXVL-1:256] := 0.VSQRTPD (VEX.128 Encoded Version)
DEST[63:0] := SQRT(SRC[63:0])DEST[127:64] := SQRT(SRC[127:64])DEST[MAXVL-1:128] := 0
SQRTPD (128-bit Legacy SSE Version)
DEST[63:0] := SQRT(SRC[63:0])DEST[127:64] := SQRT(SRC[127:64])DEST[MAXVL-1:128] (Unmodified)
VSQRTPD __m512d _mm512_sqrt_round_pd(__m512d a, int r);VSQRTPD __m512d _mm512_mask_sqrt_round_pd(__ m512d s, __mmask8 k, __m512d a, int r);
VSQRTPD __m512d _mm512_maskz_sqrt_roun d_pd( __mmask8 k, __m512d a, int r);
VSQRTPD __m256d _mm256_sqrt_pd (__m256d a);VSQRTPD __m256d _mm256_mask_sqrt_pd(__m256 d s, __mmask8 k, __m256d a, int r);
VSQRTPD __m256d _mm256_maskz_sqrt_pd ( __mmask8 k, __m256d a, int r);
SQRTPD __m128d _mm_sqrt_pd (__m128d a);VSQRTPD __m128d _mm_mask_sqrt_pd(__m12 8d s, __mmask8 k, __m128d a, int r);

VSQRTPD __m128d _mm_maskz_sqrt_pd(  __mmask8 k, __m128d a, int r);SQRTPD—Square Root of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-651SIMD Floating-Point Exceptions
Invalid, Precision, Denormal.
Non-EVEX-encoded instruction, see Table 2-19, “T ype 2 Class Exception Conditions,” additionally:
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions,” additionally:
#UD If EVEX.vvvv != 1111B.SQRTPS—Square Root of Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-652 Vol. 2BSQRTPS—Square Root of Single Pr ecision Floating-Point Values
Performs a SIMD computation of the square roots of the four , eight or sixteen packed single precision floating-point 
nation operand. 
EVEX.512 encoded versions: The source operand is a Z MM/YMM/XMM register, a 512/256/128-bit memory location 
zeroed.
zeroed.
Mode 
NP 0F 51 /r
SQRTPS xmm1, xmm2/m128A V/V SSE Computes Square Roots of the packed single precision 
xmm1.
VEX.128.0F.WIG 51 /r
VSQRTPS xmm1, xmm2/m128A V/V AVX Computes Square Roots of  the packed single precision 
VEX.256.0F.WIG 51/r
VSQRTPS ymm1, ymm2/m256A V/V AVX Computes Square Roots of  the packed single precision 
floating-point values in ymm2/m 256 and stores the result in 
ymm1.
EVEX.128.0F.W0 51 /r
VSQRTPS xmm1 {k1}{z}, 
xmm2/m128/m32bcstBV / V A V X 5 1 2 V L
AVX512FComputes Square Roots of the packed single precision 
floating-point values in xmm2/m128/m32bcst and stores the 
result in xmm1 subj ect to writemask k1.
EVEX.256.0F.W0 51 /r
VSQRTPS ymm1 {k1}{z}, 
ymm2/m256/m32bcstBV / V A V X 5 1 2 V L
floating-point values in ymm2/m256/m32bcst and stores the 
result in ymm1 subject to writemask k1.
EVEX.512.0F.W0 51/r
VSQRTPS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}B V/V AVX512F Computes Square Roots of the packed single precision 
floating-point values in zmm2/m512/m32bcst and stores the result in zmm1 subj ect to writemask k1.
B Full ModRM:reg (w) ModRM:r/m (r) N/A N/ASQRTPS—Square Root of Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-653Operation
VSQRTPS (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)
THEN
ELSE 
THEN DEST[i+31:i] := SQRT(SRC[31:0])ELSE DEST[i+31:i] := SQRT(SRC[i+31:i])
FI;
ELSE 
FI
FI;
VSQRTPS (VEX.256 Encoded Version)
DEST[31:0] := SQRT(SRC[31:0])DEST[63:32] := SQRT(SRC[63:32])
DEST[95:64] := SQRT(SRC[95:64])
DEST[127:96] := SQRT(SRC[127:96])DEST[159:128] := SQRT(SRC[159:128])DEST[191:160] := SQRT(SRC[191:160])DEST[223:192] := SQRT(SRC[223:192])DEST[255:224] := SQRT(SRC[255:224])
VSQRTPS (VEX.128 Encoded Version)
DEST[127:96] := SQRT(SRC[127:96])DEST[MAXVL-1:128] := 0
SQRTPS (128-bit Le gacy SSE Version)
DEST[127:96] := SQRT(SRC[127:96])DEST[MAXVL-1:128 ] (Unmodified)SQRTPS—Square Root of Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-654 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VSQRTPS __m512 _mm512_sqrt_round_ps(__m512 a, int r);
VSQRTPS __m512 _mm512_mask_sqrt_round_ps(__ m512 s, __mmask16 k, __m512 a, int r);
VSQRTPS __m512 _mm512_maskz_sqrt_round_ ps( __mmask16 k, __m512 a, int r);
VSQRTPS __m256 _mm256_sqrt_ps (__m256 a);VSQRTPS __m256 _mm256_mask_sqrt_ps(__m256 s, __mmask8 k, __m256 a, int r);VSQRTPS __m256 _mm256_maskz_sqrt_ps( __mmask8 k, __m256 a, int r);SQRTPS __m128 _mm_sqrt_ps (__m128 a);VSQRTPS __m128 _mm_mask_sqrt_ps(__m12 8 s, __mmask8 k, __m128 a, int r);
VSQRTPS __m128 _mm_maskz_sqrt_ps(  __mmask8 k, __m128 a, int r);
Non-EVEX-encoded instruction, see Table 2-19, “Type 2 Class Exception Conditions,” additionally:
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions,” additionally:#UD If EVEX.vvvv != 1111B.SQRTSD—Compute Square Root of Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-655SQRTSD—Compute Square Root of Scalar Do uble Precision Floating-Point Value 
Computes the square root of the low double precision floa ting-point value in the second source operand and stores 
the double precision floating-point result in the destin ation operand. The second source operand can be an XMM 
register or a 64-bit memory location. The first so urce and destination operands are XMM registers. 
128-bit Legacy SSE version: The first source operand an d the destination operand are the same. The quadword at 
bits 127:64 of the destination operand remains unchange d. Bits (MAXVL-1:64) of the corresponding destination 
VEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding 
bits of the first source operand. Bits (MAXVL -1:128) of the destination register are zeroed.
mask.
Software should ensure VSQRTSD is encoded with VE X.L=0. Encoding VSQRTSD with VEX.L=1 may encounter 
Operation
VSQRTSD (EVEX Encoded Version)
IF (EVEX.b = 1) AND (SRC2 *is register*)
THEN
ELSE 
THEN DEST[63:0] := SQRT(SRC2[63:0])ELSE 
THEN *DEST[63:0] remains unchanged*ELSE ; zeroing-maskingOpcode/
Mode 
Feature 
F2 0F 51/r
SQRTSD xmm1,xmm2/m64A V/V SSE2 Computes square root of the low double precision floating-
point value in xmm2/m64 and stores the results in xmm1.
VEX.LIG.F2.0F.WIG 51/r
VSQRTSD xmm1,xmm2, xmm3/m64B V/V AVX Computes square root of the low double precision floating-
point value in xmm3/m64 and stores the results in xmm1. 
Also, upper double precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64].
EVEX.LLIG.F2.0F.W1 51/r
VSQRTSD xmm1 {k1}{z}, xmm2, 
xmm3/m64{er}C V/V AVX512F Computes square root of the low double precision floating-
point value in xmm3/m64 and stores the results in xmm1 
under writemask k1. Also, upper double precision floating-point value (bits[127:64]) from xmm2 is copied to 
xmm1[127:64].
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ASQRTSD—Compute Square Root of Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-656 Vol. 2BTHEN DEST[63:0] := 0
FI;
VSQRTSD (VEX.128 Encoded Version)
DEST[63:0] := SQRT(SRC2[63:0])DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
SQRTSD (128-bit Legacy SSE Version)
DEST[63:0] := SQRT(SRC[63:0])DEST[MAXVL-1:64] (Unmodified)

FI;
VSQRTSD __m128d _mm_sqrt_round_sd(__m128d a, __m128d b, int r);VSQRTSD __m128d _mm_mask_sqrt_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int r);
VSQRTSD __m128d _mm_maskz_sqrt_round_sd(__ mmask8 k, __m128d a, __m128d b, int r);
SQRTSD __m128d _mm_sqrt_sd (__m128d a, __m128d b)
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”SQRTSS—Compute Square Root of Scalar Single Precision ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-657SQRTSS—Compute Square Root of Sc alar Single Precision Value 
Computes the square root of the low single precision floa ting-point value in the second source operand and stores 
the single precision floating-point result in the destin ation operand. The second source operand can be an XMM 
register or a 32-bit memory location. The first sour ce and destination operands is an XMM register. 
VEX.128 and EVEX encoded versions: Bits 127:32 of the destination operand are copied from the corresponding 
bits of the first source operand. Bits (MAXVL-1 :128) of the destination ZMM register are zeroed.
mask.
Software should ensure VSQRTSS is encoded with VEX.L=0. Encoding VSQRTSS with VEX.L=1 may encounter 
Operation
VSQRTSS (EVEX Encoded Version)
THEN
ELSE 
THEN DEST[31:0] := SQRT(SRC2[31:0])ELSE 
Mode 
Feature 
F3 0F 51 /r
SQRTSS xmm1, xmm2/m32A V/V SSE Computes square root of the low single precision floating-point 
value in xmm2/m32 and stores the results in xmm1.
VEX.LIG.F3.0F.WIG 51 /r
VSQRTSS xmm1, xmm2, 
xmm3/m32B V/V AVX Computes square root of the low single precision floating-point 
value in xmm3/m32 and stores th e results in xmm1. Also, upper 
single precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32].
EVEX.LLIG.F3.0F.W0 51 /r
VSQRTSS xmm1 {k1}{z}, xmm2, 
xmm3/m32{er}C V/V AVX512F Computes square root of the low single precision floating-point 
value in xmm3/m32 and stores the results in xmm1 under 
writemask k1. Also, upper single precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32].
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ASQRTSS—Compute Square Root of Scalar Single Precision ValueINSTRUCTION SET REFERENCE, M-U
4-658 Vol. 2BFI;
DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
VSQRTSS (VEX.128 Encoded Version)
DEST[31:0] := SQRT(SRC2[31:0])DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
SQRTSS (128-bit Legacy SSE Version)
DEST[31:0] := SQRT(SRC2[31:0])DEST[MAXVL-1:32] (Unmodified)
VSQRTSS __m128 _mm_sqrt_round_s s(__m128 a, __m128 b, int r);
VSQRTSS __m128 _mm_mask_sqrt_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int r);VSQRTSS __m128 _mm_maskz_sqrt_round_ss( __mmask8 k, __m128 a, __m128 b, int r);SQRTSS __m128 _mm_sqrt_ss(__m128 a)
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions.”STAC—Set AC Flag in EFLAGS RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-659STAC—Set AC Flag in EFLAGS Register
Sets the AC flag bit in EFLAGS register. This may enab le alignment checking of user-mode data accesses. This 
allows explicit supervisor-mode data accesses to user-mode pages even if the SMAP bit is set in the CR4 register.
This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute STAC when 
Operation
EFLAGS.AC := 1;
AC set. Other flags are unaffected.
If the CPL > 0.
#UD The STAC instruction is not recognized in virtual-8086 mode.
If CPUID.(EAX=07H, ECX= 0H):EBX.SMAP[bit 20] = 0.Opcode/
Mode 
Feature 
NP 0F 01 CB
STACZO V/V SMAP Set the AC flag in the EFLAGS register.
ZO N/A N/A N/A N/ASTC—Set Carry FlagINSTRUCTION SET REFERENCE, M-U
4-660 Vol. 2BSTC—Set Carry Flag
Sets the CF flag in the EFLAGS register. Operation is the same in all modes.
Operation
CF := 1;
The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.
En64-Bit 
F9 STC ZO Valid Valid Set CF flag.
ZO N/A N/A N/A N/ASTD—Set Direction FlagINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-661STD—Set Direction Flag
Sets the DF flag in the EFLAGS register. When the DF flag  is set to 1, string operations decrement the index regis-
Operation
DF := 1;
The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
En64-bit 
FD STD ZO Valid Valid Set DF flag.
ZO N/A N/A N/A N/ASTI—Set Interrupt FlagINSTRUCTION SET REFERENCE, M-U
4-662 Vol. 2BSTI—Set Interrupt Flag
In most cases, STI sets the interrupt flag (IF) in the EFLAGS register. This allows the processor to respond to 
maskable hardware interrupts.
If IF = 0, maskable hardware interrupts remain inhibited on  the instruction boundary following an execution of STI. 
(The delayed effect of this instruction is provided to a llow interrupts to be enabled just before returning from a 
procedure or subroutine. For instance, if an STI instruction is followed by an RET instruction, the RET instruction is 
allowed to execute before external interrupts are recognized . No interrupts can be recognized if an execution of CLI 
immediately follow such an execution of STI.) The inhibition  ends after delivery of another event (e.g., exception) 
or the execution of the next instruction.
The IF flag and the STI and CLI instructions do not prohibit the generation of exceptions and nonmaskable inter-
rupts (NMIs). However, NMIs (and system-management in terrupts) may be inhibited on the instruction boundary 
following an execution of STI that begins with IF = 0.
If IOPL < 3, EFLAGS.VIP = 1, and either VME mode or PVI mode is active, STI sets the VIF flag in the EFLAGS 
register, leaving IF unaffected.
Table 4-19 indicates the action of the STI instruction de pending on the processor operating mode, IOPL, CPL, and 
EFLAGS.VIP.Opcode Instruction Op/ 
En64-Bit 
FB STI ZO Valid Valid Set interrupt flag; external, maskable 
interrupts enabled at the end of the next 
Table 4-19.  Decision Table for STI Results 
Mode IOPL EFLAGS.VIP STI Result
NOTES:
1. X = This setting has no ef fect on instruction operation.XI F  = 1
Protected, not PVI2≥ CPL X IF = 1
< CPL X #GP fault
Protected, PVI33X I F  = 1
0–20V I F  = 1
1# G P  f a u l t
Virtual-8086, not VME33X I F  = 1
0–2 X #GP fault
Virtual-8086, VME33X I F  = 1
0–20V I F  = 1

En64-Bit 
NOTES:
0–20V I F  = 1
1# G P  f a u l t
0–20V I F  = 1
1# G P  f a u l tSTI—Set Interrupt FlagINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-663Operation
IF CR0.PE = 0  (* Execut ing in real-address mode *)
THEN IF := 1; (* Set Interrupt Flag *)ELSE
THEN
IF EFLAGS.VIP = 0
THEN VIF := 1; (* Set Virtual Interrupt Flag *)
FI;
FI;
FI;
FI;
Either the IF flag or the VIF flag is set to 1. Other flags are unaffected.
If CPL is greater than IOPL and EFLAGS.VIP = 1.
#GP(0) If IOPL is less than 3 and VME mode is not active.
If IOPL is less than 3 and EFLAGS.VIP = 1.
Same exceptions as in protected mode.2. For this table, “protected mode” applies whenever CR0.PE = 1 and EFLAGS.VM = 0; it includes compatibility mode and 64-bit mode .
3. PVI mode and virtual-8086 mode each imply CPL = 3.STMXCSR—Store MXCSR Register StateINSTRUCTION SET REFERENCE, M-U
4-664 Vol. 2BSTMXCSR—Store MXCSR Register State
Stores the contents of the MXCSR control and status regi ster to the destination operand. The destination operand 
is a 32-bit memory location. The reserved bits  in the MXCSR register are stored as 0s.
VEX.L must be 0, otherwise instructions will #UD.
Operation
m32 := MXCSR;
_mm_getcsr(void)
None.
See Table 2-22, “Type 5 Class Exception Conditions,” additionally:
#UD If VEX.L= 1,
If VEX.vvvv ≠ 1111B.Opcode*/
Mode 
Feature 
NP 0F AE /3
STMXCSR m32M V/V SSE Store contents of MXCSR register to m32 .
VEX.LZ.0F.WIG AE /3
VSTMXCSR m32M V/V AVX Store contents of MXCSR register to m32 .
M ModRM:r/m (w) N/A N/A N/ASTOS/STOSB/STOSW/STOSD/STOSQ—Store StringINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-665STOS/STOSB/STOSW/STOSD /STOSQ—Store String
In non-64-bit and default 64-bit mode; stores a byte, wo rd, or doubleword from the AL, AX, or EAX register 
(respectively) into the destination operand. The destinatio n operand is a memory location, the address of which is 
read from either the ES:EDI or ES:DI register (depending  on the address-size attribute of the instruction and the 
mode of operation). The ES segment cannot be  overridden with a segment override prefix.
At the assembly-code level, two forms of the instructio n are allowed: the “explicit-operands” form and the “no-
operands” form. The explicit-operands fo rm (specified with the STOS mnemonic) allows the destination operand to 
be specified explicitly. Here, the destin ation operand should be a symbol that indicates the size and location of the 
destination value. The source operand is then automaticall y selected to match the size of the destination operand 
(the AL register for byte operands, AX for word operands, EAX for doublewo rd operands). The explicit-operands 
form is provided to allow documentation; however, note  that the documentation prov ided by this form can be 
misleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte, 
word, or doubleword), but it does not have to specify the correct location . The location is always specified by the 
ES:(E)DI register. These must be loaded correctly before the store string instruction is executed.
The no-operands form provides “short forms” of the byte , word, doubleword, and quadword versions of the STOS 
instructions. Here also ES:(E)DI is assu med to be the destination operand and AL, AX, or EAX is assumed to be the 
source operand. The size of the destination and source operands is selected by the mnemonic: STOSB (byte read 
from register AL), STOSW (word from  AX), STOSD (doubleword from EAX).
After the byte, word, or doubleword is transferred from th e register to the memory location, the (E)DI register is 
incremented or decremented according to the setting of the DF  flag in the EFLAGS register. If the DF flag is 0, the 
register is incremented; if the DF flag is 1, the register  is decremented (the register is incremented or decremented 
by 1 for byte operations, by 2 for word op erations, by 4 for doubleword operations).
NOTE
operation during the string store operations initia ted with STOS and STOSB. See Section 7.3.9.3 in 
the Intel® 64 and IA-32 Architectures Software Develo per’s Manual, Volume 1, for additional 
information on fast-string operation.Opcode Instruction Op/ 
En64-Bit 
AA STOS m8 ZO Valid Valid For legacy mode, store AL at address ES:(E)DI; For 64-
bit mode store AL at address RDI or EDI.
AB STOS m16 ZO Valid Valid For  legacy mode, store AX at address ES:(E)DI; For 64-
bit mode store AX at address RDI or EDI.
AB STOS m32 ZO Valid Valid For legacy mode, store EAX at address ES:(E)DI; For 
64-bit mode store EAX at address RDI or EDI.
REX.W + AB STOS m64 ZO Valid N.E. Store RAX at address RDI or EDI.AA STOSB ZO Valid Valid For legacy mode, store AL at address ES:(E)DI; For 64-
AB STOSW ZO Valid Valid For legacy mode, store AX at address ES:(E)DI; For 64-
AB STOSD ZO Valid Valid For legacy mode, store EAX at address ES:(E)DI; For 
REX.W + AB STOSQ ZO Valid N.E. Store RAX at address RDI or EDI.
ZO N/A N/A N/A N/ASTOS/STOSB/STOSW/STOSD/STOSQ—Store StringINSTRUCTION SET REFERENCE, M-U
4-666 Vol. 2BIn 64-bit mode, the default address size is 64 bits, 32-bi t address size is supported using the prefix 67H. Using a 
REX prefix in the form of REX.W promotes operation on doubleword operand to 64 bits. The promoted no-operand 
mnemonic is STOSQ. STOSQ (and its explicit operands va riant) store a quadword from the RAX register into the 
destination addressed by RDI or EDI. See the summary chart at the beginning of this section for encoding data and 
limits.
The STOS, STOSB, STOSW, STOSD, STOSQ instructions can be  preceded by the REP prefix  for block stores of ECX 
bytes, words, or doublewords. More of ten, however, these instructions are used within a LOOP construct because 
data needs to be moved into the AL, AX, or EAX regi ster before it can be stored. See “REP/REPE/REPZ 
/REPNE/REPNZ—Repeat String Operation Prefix” in th is chapter for a description of the REP prefix.
Operation
IF (Byte store)
THEN
DEST := AL;
THEN IF DF =  0
ELSE (E)DI := (E)DI – 1; 
FI;
ELSE IF (Word store)
THEN
DEST := AX;
ELSE (E)DI := (E)DI – 2; 
FI;
FI;
ELSE IF (Doubleword store)
THEN
DEST := EAX;
ELSE (E)DI := (E)DI – 4; 
FI;
FI;
FI;
THEN
DEST := AL;
ELSE (R|E)DI := (R|E)DI – 1; 
FI;
THEN
DEST := AX;
ELSE (R|E)DI := (R|E)DI – 2; 
FI;
FI;
ELSE IF (Doubleword store)STOS/STOSB/STOSW/STOSD/STOSQ—Store StringINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-667THEN
ELSE (R|E)DI := (R|E)DI – 4; 
FI;
FI;
ELSE IF (Quadword store using REX.W )
THEN
DEST := RAX;
FI;
FI;
FI;
None.
If a memory operand effective address is  outside the limit of the ES segment.
If the ES register contains a NULL segment selector.
#GP If a memory operand effective addr ess is outside the ES segment limit.
#GP(0) If a memory operand effective a ddress is outside the ES segment limit.

FI;
FI;
FI;
None.
#GP(0) If the memory address is in a non-canonical form.#PF(fault-code) If a page fault occurs.#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the 
#UD If the LOCK prefix is used.STR—Store Task RegisterINSTRUCTION SET REFERENCE, M-U
4-668 Vol. 2BSTR—Store Task Register
Stores the segment selector from the task register (TR) in the destination operand. The destination operand can be 
a general-purpose register or a memory location. The segment selector stored with this instruction points to the 
task state segment (TSS) for the currently running task.
When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower 16 bits of the 
register and the upper 16 bits of the register are cleare d. When the destination operan d is a memory location, the 
segment selector is written to memory as a 16-bit quantity, regardless of operand size.
In 64-bit mode, operation is the same. The size of the memo ry operand is fixed at 16 bits. In register stores, the 2-
byte TR is zero extended if stored to a 64-bit register.
The STR instruction is useful only in  operating-system software. It can only be executed in protected mode.
Operation
DEST := TR(SegmentSelector);
None.
#GP(0) If the destination is a memory operand that is located in a non-writable segment or if the 
effective address is outside the CS, DS, ES, FS, or GS segment limit.
selector.
#UD The STR instruction is not recognized in real-address mode.
#UD The STR instruction is not recognized in virtual-8086 mode.
En64-Bit 
0F 00 /1 STR r/m16 M Valid Valid Stores segment selector from TR in r/m16.
M ModRM:r/m (w) N/A N/A N/ASTR—Store Task RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-66964-Bit Mode Exceptions
#UD If the LOCK prefix is used.STTILECFG—Store Tile ConfigurationINSTRUCTION SET REFERENCE, M-U
4-670 Vol. 2BSTTILECFG—Store Tile Configuration
The STTILECFG instruction takes a pointer to a 64-byte me mory location (described in Table 3-10 in the “LDTI-
LECFG—Load Tile Configuration” entry) that will, after su ccessful execution of this instruction, contain the descrip-
tion of the tiles that were configured. In order to config ure tiles, the AMX-TILE bit in CPUID must be set and the 
operating system has to have enabled the tiles architecture.
If the tiles are not configured, then STTILECFG stor es 64B of zeros to the indicated memory location. 
Any attempt to execute the STTILECFG instruction inside an Intel TSX transaction will result in a transaction abort.
Operation
STTILECFG mem
if TILES_CONFIGURED == 0:
//write 64 bytes of zeros at mem pointer buf[0..63] := 0write_memory(mem, 64, buf) 
else:
buf.byte[0] := ti lecfg.palette_id 
buf.byte[1] := ti lecfg.start_row 
buf.byte[2..15] := 0
p := 16
for n in 0 ... palette_table[ti lecfg.palette_id] .max_names-1: 
buf.word[p/2] := tilecfg.t[n].colsb
p := p + 2 
if p < 47:
buf.byte[p..47] := 0
p := 48for n in 0 ... palette_table[ti lecfg.palette_id] .max_names-1: 
buf.byte[p++] := tilecfg.t[n].rows
if p < 63:
buf.byte[p..63] := 0
write_memory(mem, 64, buf)
STTILECFGvoid _tile_storeconfig(void *);
Mode 
VEX.128.66.0F38.W0 49 !(11):000:bbb
STTILECFG m512A V/N.E. AMX-TILE Store tile configuration in m512.
A N/A ModRM:r/m (w) N/A N/A N/ASTTILECFG—Store Tile ConfigurationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-671Exceptions
AMX-E2; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.STUI—Set User Interrupt FlagINSTRUCTION SET REFERENCE, M-U
4-672 Vol. 2BSTUI—Set User Interrupt Flag
STUI sets the user interrupt flag (UIF). Its effect takes place immediately; a user interrupt may be delivered on the 
instruction boundary following STUI. (This is in contrast with STI, whose effect is delayed by one instruction).
An execution of STUI inside a transactional region causes  a transactional abort; the abort loads EAX as it would 
have had it been due to an execution of STI.
Operation
UIF := 1;
None.
#UD The STUI instruction is not recognized in protected mode.
#UD The STUI instruction is not recognized in real-address mode.
#UD The STUI instruction is not recognized in virtual-8086 mode.
#UD The STUI instruction is not recognized in compatibility mode.
If CR4.UINTR = 0.If CPUID.07H.0H:EDX.UINTR[bit 5] = 0.Opcode/
Mode 
F3 0F 01 EF
STUIZO V/I UINTR Set user interrupt flag.
ZO N/A N/A N/A N/A N/ASUB—SubtractINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-673SUB—Subtract
can be an immediate, register, or memory location. (However, two memory operands cannot be used in one 
operand format.Opcode Instruction Op/ 
En64-Bit 
2C ib SUB AL, imm8 I Valid Valid Subtract imm8 from AL.
2D iw SUB AX, imm16 I Valid Valid Subtract imm16 from AX.2D id SUB EAX, imm32 I Valid Valid Subtract imm32 from EAX.REX.W + 2D id SUB RAX, imm32 I Valid N.E. Subtract imm32 sign-extended to 64-bits 
from RAX.
80 /5 ib SUB r/m8, imm8 MI Valid Valid Subtract imm8 from r/m8.REX + 80 /5 ib SUB r/m8
1, imm8
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.MI Valid N.E. Subtract imm8 from r/m8.
81 /5 iw SUB r/m16, imm16 MI Valid Valid Subtract imm16 from r/m16.81 /5 id SUB r/m32, imm32 MI Valid Valid Subtract imm32 from r/m32.REX.W + 81 /5 id SUB r/m64, imm32 MI Valid N.E. Subtract imm32 sign-extended to 64-bits 
83 /5 ib SUB r/m16, imm8 MI Valid Valid Subtract sign-extended imm8 from r/m16.83 /5 ib SUB r/m32, imm8 MI Valid Valid Subtract sign-extended imm8 from r/m32.REX.W + 83 /5 ib SUB r/m64, imm8 MI Valid N.E. Subtract sign-extended imm8 from r/m64.28 /r SUB r/m8, r8 MR Valid Valid Subtract r8 from r/m8.REX + 28 /r SUB r/m8
1, r81MR Valid N.E. Subtract r8 from r/m8.
29 /r SUB r/m16, r16 MR Valid Valid Subtract r16 from r/m16.29 /r SUB r/m32, r32 MR Valid Valid Subtract r32 from r/m32.REX.W + 29 /r SUB r/m64, r64 MR Valid N.E. Subtract r64 from r/m64.2A /r SUB r8, r/m8 RM Valid Valid Subtract r/m8 from r8.REX + 2A /r SUB r8
1, r/m81RM Valid N.E. Subtract r/m8 from r8.
2B /r SUB r16, r/m16 RM Valid Valid Subtract r/m16 from r16.
2B /r SUB r32, r/m32 RM Valid Valid Subtract r/m32 from r32.
REX.W + 2B /r SUB r64, r/m64 RM Val id N.E. Subtract r/m64 from r64.
RM ModRM:reg (r, w) ModRM:r/m (r) N/A N/ASUB—SubtractINSTRUCTION SET REFERENCE, M-U
4-674 Vol. 2BThe SUB instruction performs integer subtraction. It eval uates the result for both signed and unsigned integer 
operands and sets the OF and CF flags to indicate an over flow in the signed or unsigned result, respectively. The SF 
flag indicates the sign of the signed result.
In 64-bit mode, the instruction’s default operation size is  32 bits. Using a REX prefix in  the form of REX.R permits

Operation
DEST := (DEST – SRC);
#UD If the LOCK prefix is used but the destination is not a memory operand.SUBPD—Subtract Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-675SUBPD—Subtract Packed Double Precision Floating-Point Values
Performs a SIMD subtract of the two, four or eight pack ed double precision floating-point values of the second 
Source operand from the first Source operand, and stores the packed double precision floating-point results in the 
VEX.128 and EVEX.128 encoded versions: The second source  operand is an XMM register or an 128-bit memory 
location. The first source operand and destination operan ds are XMM registers. Bits (MAXVL-1:128) of the corre-
VEX.256 and EVEX.256 encoded versions: The second source  operand is an YMM register or an 256-bit memory 
location. The first source operand and destination operan ds are YMM registers. Bits (MAXVL-1:256) of the corre-
EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit 
vector broadcasted from a 64-bit memory location. The first source operand and destination operands are ZMM 
registers. The destination operand is condit ionally updated according to the writemask.
n64/32 bit 
Mode 
Feature 
66 0F 5C /r
SUBPD xmm1, xmm2/m128A V/V SSE2 Subtract packed double precision floating-point values in 
xmm2/mem from xmm1 and store result in xmm1.
VEX.128.66.0F.WIG 5C /r
VSUBPD xmm1,xmm2, xmm3/m128B V/V AVX Subtract packed double prec ision floating-point values in 
xmm3/mem from xmm2 and store result in xmm1.
VEX.256.66.0F.WIG 5C /r
VSUBPD ymm1, ymm2, ymm3/m256B V/V AVX Subtract packed double prec ision floating-point values in 
ymm3/mem from ymm2 and store result in ymm1.
EVEX.128.66.0F.W1 5C /r
VSUBPD xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcst CV / V A V X 5 1 2 V L
AVX512FSubtract packed double precision floating-point values 
EVEX.256.66.0F.W1 5C /r
VSUBPD ymm1 {k1}{z}, ymm2, 
EVEX.512.66.0F.W1 5C /r
VSUBPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}C V/V AVX512F Subtract packed double precision floating-point values 
from zmm3/m512/m64bcst to zmm2 and store result in zmm1 with writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ASUBPD—Subtract Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-676 Vol. 2BOperation
VSUBPD (EVEX Encoded Versions When SRC2 Operand is a Vector Register)
THEN
ELSE 
FI;
THEN DEST[i+63:i] := SR C1[i+63:i] - SRC2[i+63:i]
ELSE 
FI;
FI;
VSUBPD (EVEX Encoded Versions When SRC2 Operand is a Memory Source)
IF (EVEX.b = 1)
THEN DEST[i+63:i] := SR C1[i+63:i] - SRC2[63:0];
ELSE EST[i+63:i] := SRC1 [i+63:i] - SRC2[i+63:i];
FI;
ELSE 
FI;
FI;
VSUBPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] - SRC2[63:0]DEST[127:64] := SRC1[127:64] - SRC2[127:64]DEST[191:128] := SRC1[191:128] - SRC2[191:128]DEST[255:192] := SRC1[255:192] - SRC2[255:192]DEST[MAXVL-1:256] := 0SUBPD—Subtract Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-677VSUBPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] - SRC2[63:0]DEST[127:64] := SRC1[127:64] - SRC2[127:64]DEST[MAXVL-1:128] := 0
SUBPD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] - SRC[63:0]DEST[127:64] := DEST[127:64] - SRC[127:64]DEST[MAXVL-1:128 ] (Unmodified)
VSUBPD __m512d _mm512_sub_pd (__m512d a, __m512d b);
VSUBPD __m512d _mm512_mask_sub_pd (__m512d  s, __mmask8 k, __m512d a, __m512d b);
VSUBPD __m512d _mm512_maskz_sub_pd (__mmask8 k, __m512d a, __m512d b);VSUBPD __m512d _mm512_sub_round_p d (__m512d a, __m512d b, int);
VSUBPD __m512d _mm512_mask_sub_round_pd (__m5 12d s, __mmask8 k, __m512d a, __m512d b, int);
VSUBPD __m512d _mm512_maskz_sub_round_pd (__mmask8 k, __m512d a, __m512d b, int);
VSUBPD __m256d _mm256_sub_pd (__m256d a, __m256d b);VSUBPD __m256d _mm256_mask_sub_pd (__m256d  s, __mmask8 k, __m256d a, __m256d b);
VSUBPD __m256d _mm256_maskz_sub_pd (__mmask8 k, __m256d a, __m256d b);SUBPD __m128d _mm_sub_pd (__m128d a, __m128d b);VSUBPD __m128d _mm_mask_sub_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VSUBPD __m128d _mm_maskz_sub_pd ( __mmask8 k, __m128d a, __m128d b);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”SUBPS—Subtract Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-678 Vol. 2BSUBPS—Subtract Packed Single Precision Floating-Point Values
Performs a SIMD subtract of the packed single precision floating-point values in the second Source operand from 
the First Source operand, and stores the packed single pr ecision floating-point results in the destination operand.
EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit

vector broadcasted from a 32-bit memory location. The first source operand and destination operands are ZMM 
registers. The destination operand is conditionally updated according to the writemask.
Operation
VSUBPS (EVEX Encoded Versions When SRC2 Operand is a Vector Register)
THEN
ELSE 
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);Opcode/
n64/32 bit 
Mode 
NP 0F 5C /r
SUBPS xmm1, xmm2/m128A V/V SSE Subtract packed single precision floating-point values in 
VEX.128.0F.WIG 5C /r
VSUBPS xmm1,xmm2, xmm3/m128B V/V AVX Subtract packed single precision floating-point values in 
xmm3/mem from xmm2 and stores result in xmm1.
VEX.256.0F.WIG 5C /r
VSUBPS ymm1, ymm2, ymm3/m256B V/V AVX Subtract packed single precision floating-point values in 
ymm3/mem from ymm2 and stores result in ymm1.
EVEX.128.0F.W0 5C /r
VSUBPS xmm1 {k1}{z}, xmm2, 
AVX512FSubtract packed single precision floating-point values 
from xmm3/m128/m32bcst to xmm2 and stores result 
in xmm1 with writemask k1.
EVEX.256.0F.W0 5C /r
VSUBPS ymm1 {k1}{z}, ymm2, 
from ymm3/m256/m32bcst to ymm2 and stores result 
in ymm1 with writemask k1.
EVEX.512.0F.W0 5C /r
VSUBPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er} C V/V AVX512F Subtract packed single precision floating-point values in 
zmm3/m512/m32bcst from zmm2 and stores result in zmm1 with writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ASUBPS—Subtract Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-679FI;
THEN DEST[i+31:i] := SRC1[i+31:i] - SRC2[i+31:i]
ELSE 
FI;
FI;
VSUBPS (EVEX Encoded Versions When SRC2 Operand is a Memory Source)
(KL, VL) = (4, 128), (8, 256),(16, 512)FOR j := 0 TO KL-1
THEN DEST[i+31:i] := SRC1[i+31:i] - SRC2[31:0];ELSE DEST[i+31:i] := SRC1[i+31:i] - SRC2[i+31:i];
FI;
ELSE 
FI;
FI;
VSUBPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[63:32] := SRC1[63:32] - SRC2[63:32]DEST[95:64] := SRC1[95:64] - SRC2[95:64]DEST[127:96] := SRC1[127:96] - SRC2[127:96]DEST[159:128] := SRC1[1 59:128] - SRC2[159:128]
DEST[191:160] := SRC1[1 91:160] - SRC2[191:160]
DEST[255:224] := SRC1[2 55:224] - SRC2[255:224].
VSUBPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[63:32] := SRC1[63:32] - SRC2[63:32]DEST[95:64] := SRC1[95:64] - SRC2[95:64]DEST[127:96] := SRC1[127:96] - SRC2[127:96]DEST[MAXVL-1:128] := 0SUBPS—Subtract Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-680 Vol. 2BSUBPS (128-bit Legacy SSE Version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[63:32] := SRC1[63:32] - SRC2[63:32]DEST[95:64] := SRC1[95:64] - SRC2[95:64]DEST[127:96] := SRC1[127:96] - SRC2[127:96]DEST[MAXVL-1:128] (Unmodified)
VSUBPS __m512 _mm512_sub_ps (__m512 a, __m512 b);VSUBPS __m512 _mm512_mask_sub_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);VSUBPS __m512 _mm512_maskz_sub_ps ( __mmask16 k, __m512 a, __m512 b);
VSUBPS __m512 _mm512_sub_round_ps (__m512 a, __m512 b, int);VSUBPS __m512 _mm512_mask_sub_round_ps (__m 512 s, __mmask16 k, __m51 2 a, __m512 b, int);
VSUBPS __m512 _mm512_maskz_sub_round_ps (__mmask16 k, __m512 a, __m512 b, int);
VSUBPS __m256 _mm256_sub_ps (__m256 a, __m256 b);VSUBPS __m256 _mm256_mask_sub_ps (__m 256 s, __mmask8 k, __m256 a, __m256 b);
VSUBPS __m256 _mm256_maskz_sub_ps ( __mmask16 k, __m256 a, __m256 b);
SUBPS __m128 _mm_sub_ps (__m128 a, __m128 b);VSUBPS __m128 _mm_mask_sub_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VSUBPS __m128 _mm_maskz_sub_ps (_ _mmask16 k, __m128 a, __m128 b);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”SUBSD—Subtract Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-681SUBSD—Subtract Scalar Double Precision Floating-Point Value
Subtract the low double precision floating-point value in the second source operand from the first source operand 
and stores the double precision floating-point resu lt in the low quadword of the destination operand.
VEX.128 and EVEX encoded versions: Bits (127:64) of the XMM register destination are copied from corresponding 
mask.
Software should ensure VSUBSD is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-
Operation
VSUBSD (EVEX Encoded Version)
THEN
ELSE 
THEN DEST[63:0] := SRC1[63:0] - SRC2[63:0]ELSE 
FI;
Mode 
Feature 
F2 0F 5C /r
SUBSD xmm1, xmm2/m64A V/V SSE2 Subtract the low double precision floating-point value in 
xmm2/m64 from xmm1 and st ore the result in xmm1.
VEX.LIG.F2.0F.WIG 5C /r
VSUBSD xmm1,xmm2, xmm3/m64B V/V AVX Subtract the low double pr ecision floating-point value in 
xmm3/m64 from xmm2 and st ore the result in xmm1.
EVEX.LLIG.F2.0F.W1 5C /r
VSUBSD xmm1 {k1}{z}, xmm2, xmm3/m64{er}C V/V AVX512F Subtract the low double precision floating-point value in 
xmm3/m64 from xmm2 and st ore the result in xmm1 
C Tuple1 Scalar ModRM:reg (w) E VEX.vvvv (r) ModRM:r/m (r) N/ASUBSD—Subtract Scalar Double Pr ecision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-682 Vol. 2BDEST[127:64] := SRC1[127:64]
VSUBSD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] - SRC2[63:0]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
SUBSD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] - SRC[63:0]DEST[MAXVL-1:64] (Unmodified)
VSUBSD __m128d _mm_mask_sub_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);VSUBSD __m128d _mm_maskz_sub_sd (__mmask8 k, __m128d a, __m128d b);VSUBSD __m128d _mm_sub_round_sd (__m128d a, __m128d b, int);VSUBSD __m128d _mm_mask_sub_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VSUBSD __m128d _mm_maskz_sub_round_sd (__m mask8 k, __m128d a, __m128d b, int);
SUBSD __m128d _mm_sub_sd (__m128d a, __m128d b);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”SUBSS—Subtract Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-683SUBSS—Subtract Scalar Single Precision Floating-Point Value
Subtract the low single precision floating-point value from the second source operand and the first source operand 
and store the double precision floa ting-point result in the low doubleword of the destination operand.

128-bit Legacy SSE version: The destination and first so urce operand are the same. Bits (MAXVL-1:32) of the 
VEX.128 and EVEX encoded versions: Bits (127:32) of the XMM register destination are copied from corresponding 
mask.
Software should ensure VSUBSS is encoded with VEX.L= 0. Encoding VSUBSD with VEX.L=1 may encounter unpre-
Operation
VSUBSS (EVEX Encoded Version)
THEN
ELSE 
THEN DEST[31:0] := SRC1[31:0] - SRC2[31:0]ELSE 
FI;
Mode 
Feature 
F3 0F 5C /r
SUBSS xmm1, xmm2/m32A V/V SSE Subtract the low single precision floating-point value in 
xmm2/m32 from xmm1 and store the result in xmm1.
VEX.LIG.F3.0F.WIG 5C /r
VSUBSS xmm1,xmm2, xmm3/m32B V/V AVX Subtract the low single precision floating-point value in 
xmm3/m32 from xmm2 and store the result in xmm1.
EVEX.LLIG.F3.0F.W0 5C /r
VSUBSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}C V/V AVX512F Subtract the low single precision floating-point value in 
xmm3/m32 from xmm2 and store the result in xmm1 under writemask k1.
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/ASUBSS—Subtract Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, M-U
4-684 Vol. 2BDEST[127:32] := SRC1[127:32]
VSUBSS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0
SUBSS (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0] - SRC[31:0]DEST[MAXVL-1:32] (Unmodified)
VSUBSS __m128 _mm_mask_sub_ss (__m128 s,  __mmask8 k, __m128 a, __m128 b);
VSUBSS __m128 _mm_maskz_sub_ss (__m mask8 k, __m128 a, __m128 b);
VSUBSS __m128 _mm_sub_round_ss (__m128 a, __m128 b, int);
VSUBSS __m128 _mm_mask_sub_rou nd_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VSUBSS __m128 _mm_maskz_su b_round_ss (__mmask8 k, __m128 a, __m128 b, int);
SUBSS __m128 _mm_sub_ss (__m128 a, __m128 b);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”SWAPGS—Swap GS Base RegisterINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-685SWAPGS—Swap GS Base Register
SWAPGS exchanges the current GS base register valu e with the value contained in MSR address C0000102H 
(IA32_KERNEL_GS_BASE). The SWAPGS instruction is a priv ileged instruction intended for use by system soft-
ware. 
When using SYSCALL to implement system calls, there is no  kernel stack at the OS entry point. Neither is there a 
straightforward method to obtain a pointer to kernel stru ctures from which the kernel stack pointer could be read. 
Thus, the kernel cannot save general purpose registers or reference memory. 
By design, SWAPGS does not require any general purpose re gisters or memory operands. No registers need to be 
saved before using the instruction. SWAPGS exchanges the CPL 0 data pointer from the IA32_KERNEL_GS_BASE 
MSR with the GS base register. The kernel can then use the GS prefix on normal memory references to access 
kernel data structures. Similarly, when the OS kernel is entered using an interrupt or exception (where the kernel 
stack is already set up), SWAPGS can be used to quickly get a pointer to the kernel data structures.
The IA32_KERNEL_GS_BASE MSR itself is only accessible  using RDMSR/WRMSR instructions. Those instructions 
are only accessible at privilege level 0. The WRMSR instruction ensures that the IA32_KERNEL_GS_BASE MSR 
contains a canonical address.
Operation
IF CS.L ≠ 1 (* Not in 64-Bit Mode *)
THEN
#UD; FI;
IF CPL ≠ 0
tmp := GS.base;
GS.base := IA32_KERNEL_GS_BASE;IA32_KERNEL_GS_BASE := tmp;
None.
#UD If Mode ≠ 64-Bit.
#UD If Mode ≠ 64-Bit.Opcode Instruction Op/ 
En64-Bit 
0F 01 F8 SWAPGS ZO Valid Invalid Exchanges the current GS base register value with 
the value contained in MSR address C0000102H.
ZO N/A N/A N/A N/ASWAPGS—Swap GS Base RegisterINSTRUCTION SET REFERENCE, M-U
4-686 Vol. 2BCompatibility Mode Exceptions
#GP(0) If CPL ≠ 0.
#UD If the LOCK prefix is used.SYSCALL—Fast System CallINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-687SYSCALL—Fast System Call
SYSCALL invokes an OS system-call hand ler at privilege level 0. It does so  by loading RIP from the IA32_LSTAR 
MSR (after saving the address of the instruction followi ng SYSCALL into RCX). (The WRMSR instruction ensures 
that the IA32_LSTAR MSR always contain a canonical address.)
SYSCALL also saves RFLAGS into R11 and then mask s RFLAGS using the IA32_FMASK MSR (MSR address 
C0000084H); specifically, the processor clears in RFLAGS every bit corresponding to a bit that is set in the 
IA32_FMASK MSR.
SYSCALL loads the CS and SS selectors with values deri ved from bits 47:32 of the IA32_STAR MSR. However, the 
CS and SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors. 
Instead, the descriptor caches are loaded with fixed values . See the Operation section for details. It is the respon-
sibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values corre-
spond to the fixed values loaded into the descriptor caches; the SYSCALL instruction does not ensure this 
correspondence.
The SYSCALL instruction does not save the stack pointer (RSP ). If the OS system-call handler will change the stack 
pointer, it is the responsibility of software to save the pr evious value of the stack pointer. This might be done prior 
to executing SYSCALL, with software restoring the stack po inter with the instruction following SYSCALL (which will 
be executed after SYSRET). Alternatively, the OS system -call handler may save the stack pointer and restore it 
before executing SYSRET.
When shadow stacks are enabled at a privilege level where the SYSCALL instruction is invoked, the SSP is saved to 
the IA32_PL3_SSP MSR. If shadow stacks  are enabled at privilege level 0, the SSP is loaded with 0. Refer to 
Chapter 6, “Procedure Calls, Interrupt s, and Exceptions‚” and Chapter 17, “Control-flow Enforcement Technology 
(CET)‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for additional CET details.
Instruction ordering. Instructions following a SYSCALL may be fetche d from memory before earlier instructions 
complete execution, but they will not execute (even specul atively) until all instructions prior to the SYSCALL have 
Operation
IF (CS.L ≠ 1 ) or (IA32_EFER.LMA ≠ 1) or (IA32_EFER.SCE ≠ 1)
(* Not in 64-Bit Mode or SYSCALL/ SYSRET not enabled in IA32_EFER *)
THEN #UD;
FI;
RCX := RIP; (* Will contain address of next instruction *)
RIP := IA32_LSTAR;R11 := RFLAGS;RFLAGS := RFLAGS AND NOT(IA32_FMASK);
CS.Selector := IA32_STAR[47:32] AND FFFCH (* Operating system provides CS; RPL forced to 0 *)
(* Set rest of CS to a fixed value *)CS.Base := 0; (* Flat segment *)CS.Limit := FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)CS.Type := 11; (* Execute/read code, accessed *)Opcode Instruction Op/ 
En64-Bit 
0F 05 SYSCALL ZO Valid Invalid Fast call to privilege level 0 system procedures.
Z O N / AN / A N / AN / ASYSCALL—Fast System CallINSTRUCTION SET REFERENCE, M-U
4-688 Vol. 2BCS.S := 1;
CS.DPL := 0;CS.P := 1;CS.L := 1; (* Entry is to 64-bit mode *)CS.D := 0; (* Requir ed if CS.L = 1 *)
CS.G := 1; (* 4-KByte granularity *)
THEN (* adjust so bits 63:N get the value of bit N–1, where N is the CPU’s maximum linear-address width *)
(* With shadow stacks enabled the system ca ll is supported from Ring 3 to Ring 0 *)

En64-Bit 
(* OS supporting Ring 0 to Ring 0 system calls or Ring 1/2 to ring 0 system call *)
(* Must preserve the conten ts of IA32_PL3_SSP to avoid losing ring 3 state *)
FI;
CPL := 0;IF ShadowStackEnabled(CPL)
SSP := 0;
IA32_S_CET.TRACKER = WAIT_FOR_ENDBRANCHIA32_S_CET.SUPPRESS = 0
FI;
SS.Selector := IA32_STAR[47:32] + 8; (* SS just above CS *)
(* Set rest of SS to a fixed value *)SS.Base := 0; (* Flat segment *)SS.Limit := FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)SS.Type := 3; (* Read/write data, accessed *)SS.S := 1;SS.DPL := 0;SS.P := 1;SS.B := 1; (* 32-bit stack segment *)SS.G := 1; (* 4-KByte granularity *)
All.
#UD The SYSCALL instruction is not recognized in protected mode.
#UD The SYSCALL instruction is not recognized in real-address mode.
#UD The SYSCALL instruction is not recognized in virtual-8086 mode.
#UD The SYSCALL instruction is not recognized in compatibility mode.SYSCALL—Fast System CallINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-68964-Bit Mode Exceptions
#UD If IA32_EFER.SCE = 0.
If the LOCK prefix is used.SYSENTER—Fast System CallINSTRUCTION SET REFERENCE, M-U
4-690 Vol. 2BSYSENTER—Fast System Call
Executes a fast call to a level 0 system procedure or rout ine. SYSENTER is a companion instruction to SYSEXIT. The 
instruction is optimized to provide the maximum performanc e for system calls from user code running at privilege 
level 3 to operating system or executive procedures running at privilege level 0.
When executed in IA-32e mode, the SYSENTER instruction transitions the logical processor to 64-bit mode; other-
wise, the logical processor remains in protected mode.
Prior to executing the SYSENTER instruction, software mu st specify the privilege leve l 0 code segment and code 
entry point, and the privilege level 0 stack segment and stack pointer by writing values to the following MSRs:
•IA32_SYSENTER_CS  (MSR address 174H) — The lower 16 bits of this MSR are the segment selector for the 
privilege level 0 code segment. This value is also used to determine the segment selector of the privilege level 
0 stack segment (see the Operation section). This value cannot indicate a null selector.
•IA32_SYSENTER_EIP  (MSR address 176H) — The value of this MSR is loaded into RIP (thus, this value 
references the first instruction of the selected oper ating procedure or routine). In protected mode, only 
bits 31:0 are loaded.
•IA32_SYSENTER_ESP  (MSR address 175H) — The value of this MSR is loaded into RSP (thus, this value 
contains the stack pointer for the privilege level 0 stac k). This value cannot represent a non-canonical address. 
In protected mode, only bits 31:0 are loaded.
These MSRs can be read from and written to using RDMSR/WRMSR. The WRMSR instruction ensures that the 
IA32_SYSENTER_EIP and IA32_SYSENTER_ESP MS Rs always contain canonical addresses.
While SYSENTER loads the CS and SS selectors with valu es derived from the IA32_SYSENTER_CS MSR, the CS and 
SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors. Instead, 
the descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the 
fixed values loaded into the descriptor caches; the SYSENTER instruction does not ensure this correspondence.
The SYSENTER instruction can be invoked from all operating modes except real-address mode. 
The SYSENTER and SYSEXIT instructions are companion instructions, but they do not constitute a call/return pair. 
When executing a SYSENTER instruction, the processor does not save state information for the user code (e.g., the 
instruction pointer), and neither the SYSENTER nor the SY SEXIT instruction supports passing parameters on the 
stack.
To use the SYSENTER and SYSEXIT instructions as companio n instructions for transitions between privilege level 3 
code and privilege level 0 operating system procedures, the following conventions must be followed:
•The segment descriptors for the privilege level 0 code an d stack segments and for the privilege level 3 code and 
stack segments must be contiguous in a descriptor table. This convention allows the processor to compute the 
segment selectors from the value en tered in the SYSE NTER_CS_MSR MSR.
•The fast system call “stub” routines executed by user co de (typically in shared libraries or DLLs) must save the 
required return IP and processor state information if a re turn to the calling procedure is required. Likewise, the 
operating system or executive procedures called with SYSENTER instructions must have access to and use this 
saved return and state information when returning to the user code.
The SYSENTER and SYSEXIT instructions were introduced in to the IA-32 architecture in the Pentium II processor. 
The availability of these instructions on a processor is indicated with the SYSENTER/S YSEXIT present (SEP) feature Opcode Instruction Op/ 
En64-Bit 
0F 34 SYSENTER ZO Valid Valid Fast call to privilege level 0 system procedures.
ZO N/A N/A N/A N/ASYSENTER—Fast System CallINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-691flag returned to the EDX register by the CPUID instructio n. An operating system that qualifies the SEP flag must 
also qualify the processor family and model to ensure that the SYSENTER/SYSEXIT instructions are actually 
present. For example:
IF CPUID SEP bit is set
THEN IF (Family = 6) and (Model < 3) and (Stepping < 3) 
THEN
SYSENTER/SYSEXIT_Not_Supported; FI;
ELSE 
SYSENTER/SYSEXIT_Supported; FI;
FI;
When the CPUID instruction is executed  on the Pentium Pro processor (model  1), the processor returns a the SEP 
flag as set, but does not support the SYSENTER/SYSEXIT instructions.
When shadow stacks are enabled at privilege level where SY SENTER instruction is invoked, the SSP is saved to the 
IA32_PL3_SSP MSR. If shadow stacks are enabled at privile ge level 0, the SSP is loaded with 0. Refer to Chapter 
6, “Procedure Calls, Interrupts, and Exceptions‚” and Ch apter 17, “Control-flow Enforcement Technology (CET)‚” in 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for additional CET details.
Instruction ordering. Instructions following a SYSENTER may be fetc hed from memory before earlier instructions 
complete execution, but they will not execute (even speculatively) until all instructions prior to the SYSENTER have completed execution (the later instructions may execute before data stored by the earlier instructions have 
Operation
IF CR0.PE = 0 OR IA32_SYSENTER_CS[15:2]  = 0 THEN #GP(0); FI;
RFLAGS.VM := 0; (* Ensures protected mode execution *)
RFLAGS.IF := 0; (* Mask interrupts *)IF in IA-32e mode
THEN
RSP := IA32_SYSENTER_ESP;RIP := IA32_SYSENTER_EIP;
ELSE
ESP := IA32_SYSENTER_ESP[31:0];EIP := IA32_SYSENTER_EIP[31:0];
FI;
CS.Selector := IA32_SYSENTER_CS[15:0] AND FFFCH;
(* Operating system provides CS; RPL forced to 0 *)
(* Set rest of CS to a fixed value *)CS.Base := 0; (* Flat segment *)CS.Limit := FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)CS.Type := 11; (* Execute/read code, accessed *)CS.S := 1;CS.DPL := 0;CS.P := 1;IF in IA-32e mode
THEN
CS.L := 1; (* Entry is to 64-bit mode *)CS.D := 0; (* Requir ed if CS.L = 1 *)
ELSE
CS.L := 0;CS.D := 1; (* 32-b it code segment*)
FI;CS.G := 1; (* 4-KByte granularity *)SYSENTER—Fast System CallINSTRUCTION SET REFERENCE, M-U
4-692 Vol. 2BIF ShadowStackEnabled(CPL)
THEN
FI;
FI;
SSP := 0;
FI;
SS.Selector := CS.Selector + 8; (* SS just above CS *)
(* Set rest of SS to a fixed value *)SS.Base := 0; (* Flat segment *)SS.Limit := FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)SS.Type := 3; (* Read/write data, accessed *)SS.S := 1;SS.DPL := 0;SS.P := 1;SS.B := 1; (* 32-bit stack segment*)SS.G := 1; (* 4-KByte granularity *)
VM, IF (see Operation above).
#GP(0) If IA32_SYSENTER_CS[15:2] = 0.
#GP The SYSENTER instruction is no t recognized in real-address mode.

FI;
FI;
SSP := 0;
FI;
Same exceptions as in protected mode.SYSEXIT—Fast Return from Fast System CallINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-693SYSEXIT—Fast Return from Fast System Call
Executes a fast return to privilege level 3 user code. SY SEXIT is a companion instruction to the SYSENTER instruc-
tion. The instruction is optimized to provide the maxi mum performance for returns from system procedures 
executing at protections levels 0 to user procedures executin g at protection level 3. It must be executed from code 
executing at privilege level 0. 
With a 64-bit operand size, SYSEXIT remains in 64-bit mode ; otherwise, it either enters compatibility mode (if the 
logical processor is in IA-32e mode) or remains in protected mode (if it is not).
Prior to executing SYSEXIT, software must specify the priv ilege level 3 code segment and code entry point, and the 
privilege level 3 stack segment and stack pointer by writ ing values into the follow ing MSR and general-purpose 
•IA32_SYSENTER_CS  (MSR address 174H) — Contains a 32-bit value that is used to determine the segment 
selectors for the privilege level 3 code and stack segments (see the Operation section)
•RDX — The canonical address in this register is loaded in to RIP (thus, this value references the first instruction 
to be executed in the user code). If the return  is not to 64-bit mode, only bits 31:0 are loaded.
•ECX — The canonical address in this register is loaded into RSP (thus, this value contains the stack pointer for 
the privilege level 3 stack). If the return is not to 64-bit mode, only bits 31:0 are loaded.
The IA32_SYSENTER_CS MSR can be read fr om and written to using RDMSR and WRMSR.
While SYSEXIT loads the CS and SS selectors with values  derived from the IA32_SYSENTER_CS MSR, the CS and 
SS descriptor caches are not loaded from the descriptors (in GDT or LDT)  referenced by those selectors. Instead, 
the descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of 
OS software to ensure that the descriptors (in GDT or LD T) referenced by those select or values correspond to the 
fixed values loaded into the descriptor caches; the SYSEXIT instruction does not ensure this correspondence.
The SYSEXIT instruction can be invoked from all operating modes except real-address mode and virtual-8086 
mode. 
The availability of these instructions on a processor is indicated with the SYSENTER/S YSEXIT present (SEP) feature 
flag returned to the EDX register by the CPUID instructio n. An operating system that qualifies the SEP flag must 
THEN
ELSE 
FI;
flag as set, but does not support the SYSENTER/SYSEXIT instructions.Opcode Instruction Op/ 
En64-Bit 
0F 35 SYSEXIT ZO Valid Valid Fast return  to privilege level 3 user code.
REX.W + 0F 35 SYSEXIT ZO Valid Valid Fast return to 64-bit mode privilege level 3 user code.
ZO N/A N/A N/A N/ASYSEXIT—Fast Return from Fast System CallINSTRUCTION SET REFERENCE, M-U
4-694 Vol. 2BWhen shadow stacks are enabled at privilege level 3 the instruction loads SSP with value from IA32_PL3_SSP MSR. 
Refer to Chapter 6, “Interrupt and Exception Handling‚ ” and Chapter 17, “Control-flow Enforcement Technology 
Instruction ordering. Instructions following a SYSEXIT may be fetche d from memory before earlier instructions 
complete execution, but they will not execute (even specul atively) until all instructions prior to the SYSEXIT have 
completed execution (the later instructions may execute befo re data stored by the earlier instructions have become 
globally visible).
Operation
IF IA32_SYSENTER_CS[15:2]  = 0 OR CR0.PE = 0 OR CPL ≠ 0 THEN #GP(0); FI;
IF operand size is 64-bit
THEN (* Return to 64-bit mode *)
RSP := RCX;RIP := RDX;
ELSE (* Return to protected mode or compatibility mode *)
RSP := ECX;RIP := EDX;
FI;
IF operand size is 64-bit (* Operating system provides CS; RPL forced to 3 *)
THEN CS.Selector := IA32_SYSENTER_CS[15:0] + 32;ELSE CS.Selector := IA32_SYSENTER_CS[15:0] + 16;
FI;CS.Selector := CS.Selector OR 3; (* RPL forced to 3 *)(* Set rest of CS to a fixed value *)CS.Base := 0; (* Flat segment *)CS.Limit := FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)CS.Type := 11; (* Execute/read code, accessed *)CS.S := 1;CS.DPL := 3;CS.P := 1;IF operand size is 64-bit
THEN (* return to 64-bit mode *)
CS.L := 1; (* 64-bit code segment *)CS.D := 0; (* Requir ed if CS.L = 1 *)
ELSE (* return to protected mode or compatibility mode *)
CS.L := 0;CS.D := 1; (* 32-bit code segment*)
FI;CS.G := 1; (* 4-KByte granularity *)CPL := 3;
THEN SSP := IA32_PL3_SSP;
FI;
(* Set rest of SS to a fixed value *)SS.Base := 0; (* Flat segment *)SS.Limit := FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)SS.Type := 3; (* Read/write data, accessed *)SS.S := 1;SS.DPL := 3;SS.P := 1;SS.B := 1; (* 32-bit stack segment*)SYSEXIT—Fast Return from Fast System CallINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-695SS.G := 1; (* 4-KByte granularity *)
None.
If CPL ≠ 0.
#GP The SYSEXIT instruction is not recognized in real-address mode.#UD If the LOCK prefix is used.
#GP(0) The SYSEXIT instruction is not recognized in virtual-8086 mode.
#GP(0) If IA32_SYSENTER_CS = 0.
If CPL ≠ 0.
If RCX or RDX contains a non-canonical address.
#UD If the LOCK prefix is used.SYSRET—Return From Fast System CallINSTRUCTION SET REFERENCE, M-U
4-696 Vol. 2BSYSRET—Return From Fast System Call
SYSRET is a companion instruction to the SYSCALL instructio n. It returns from an OS system-call handler to user 
code at privilege level 3. It does so by lo ading RIP from RCX and loading RFLAGS from R11.1 With a 64-bit operand 
size, SYSRET remains in 64-bit mode; otherwise, it enters compatibility mode and only th e low 32 bits of the regis-
ters are loaded.
SYSRET loads the CS and SS selectors with values derive d from bits 63:48 of the IA32_STAR MSR. However, the CS 
and SS descriptor caches are not loaded from the descriptors (in GDT or  LDT) referenced by those selectors. 
sibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values corre-spond to the fixed values loaded into the descriptor caches; the SYSRET instruction does not ensure this 
The SYSRET instruction does not modify the stack pointer (ESP or RSP). For that reason, it is necessary for software 
to switch to the user stack. The OS may load the user st ack pointer (if it was saved after SYSCALL) before executing 
SYSRET; alternatively, user code may load the stack pointer (if it was saved before SYSCALL) after receiving control from SYSRET.
If the OS loads the stack pointer before executing SYSRET, it must ensure that the handler of any interrupt or 
exception delivered between restoring the stack pointer and successful execution of SYSRET is not invoked with the 
user stack. It can do so using approaches such as the following:
•External interrupts. The OS can prevent an external interrupt from being delivered by clearing EFLAGS.IF 
before loading the user stack pointer.
•Nonmaskable interrupts (NMIs). The OS can ensure that the NMI handler is invoked with the correct stack by 
using the interrupt stack table (IST) mechanism for gate  2 (NMI) in the IDT (see Section 6.14.5, “Interrupt 
Stack Table,” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).
•General-protection exceptions (#GP). The SYSRET inst ruction generates #GP(0) if the value of RCX is not 
canonical. The OS can address this possibility us ing one or more of the following approaches:
— Confirming that the value of RCX is canonical before executing SYSRET.
— Using paging to ensure that the SYSCALL instruction will never save a non-canonical value into RCX.
— Using the IST mechanism for gate 13 (#GP) in the IDT.

When shadow stacks are enabled at privilege level 3 the instruction loads SSP with value from IA32_PL3_SSP MSR. 
Refer to Chapter 6, “Procedure Calls, Interrupts, and Exceptions‚” and Chapter 17 , “Control-flow Enforcement 
Technology (CET)‚” in the Intel® 64 and IA-32 Architectures Software Deve loper’s Manual, Volume 1, for additional 
CET details.Opcode Instruction Op/ 
En64-Bit 
0F 07 SYSRET ZO Valid Invalid Return to compatibility mode from fast 
system call.
REX.W + 0F 07 SYSRET ZO Valid Invalid Return to 64-bit mode from fast system call.
1. Regardless of the value of R11, the RF and VM flags are always 0 in RFLAGS after execution of SYSRET. In addition, all reserv ed bits 
in RFLAGS retain the fixed values.SYSRET—Return From Fast System CallINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-697Instruction ordering.  Instructions following a SYSRET may be fetc hed from memory before earlier instructions 
complete execution, but they will not execute (even specul atively) until all instructions prior to the SYSRET have 
Operation
IF (CPL ≠ 0) THEN #GP(0); FI;
IF (operand si ze is 64-bit) 
THEN (* Return to 64-Bit Mode *)
IF (RCX is not canonical) THEN #GP(0);RIP := RCX;
ELSE (* Return to Compatibility Mode *)
RIP := ECX;
FI;RFLAGS := (R11 & 3C7FD7H) | 2; (* Clear RF, VM, reserved bits; set bit 1 *)
THEN CS.Selector := IA32_STAR[63:48]+16;
ELSE CS.Selector := IA32_STAR[63:48];
FI;CS.Selector := CS.Selector OR 3; (* RPL forced to 3 *)(* Set rest of CS to a fixed value *)CS.Base := 0; (* Flat segment *)CS.Limit := FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)CS.Type := 11; (* Execute/read code, accessed *)CS.S := 1;CS.DPL := 3;CS.P := 1;IF (operand si ze is 64-bit) 
CS.L := 0; (* Compatibility mode *)CS.D := 1; (* 32-b it code segment *)
FI;CS.G := 1; (* 4-KByte granularity *)CPL := 3;IF ShadowStackEnabled(CPL)
SSP := IA32_PL3_SSP;
FI;
SS.Selector := (IA32_STAR[63:48]+8) OR 3; (* RPL forced to 3 *)
(* Set rest of SS to a fixed value *)SS.Base := 0; (* Flat segment *)SS.Limit := FFFFFH; (* With 4-KByte gr anularity, implies a 4-GByte limit *)
SS.Type := 3; (* Read/w rite data, accessed *)
SS.S := 1;SS.DPL := 3;SS.P := 1;SS.B := 1; (* 32-bit stack segment*)SS.G := 1; (* 4-KByte granularity *)SYSRET—Return From Fast System CallINSTRUCTION SET REFERENCE, M-U
4-698 Vol. 2BFlags Affected
All.
#UD The SYSRET instruction is not recognized in protected mode.
#UD The SYSRET instruction is not recognized in real-address mode.
#UD The SYSRET instruction is not recognized in virtual-8086 mode.
#UD The SYSRET instruction is not recognized in compatibility mode.
If the return is to 64-bit mode and RCX contains a non-canonical address.TDPBF16PS—Dot Product of BF16 Tiles Accumulated into Packed Single Precision TileINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-699TDPBF16PS—Dot Product of BF16 Tiles Accumula ted into Packed Single Precision Tile
This instruction performs a set of SIMD dot-products of  two BF16 elements and accumulates the results into a 
packed single precision tile. Each dword element in input tiles tmm2 and tmm3 is interpreted as a BF16 pair. For each possible combination of (row of tmm2, column of tmm3 ), the instruction performs a set of SIMD dot-products 
on all corresponding BF16 pairs (one pair from tmm2 and one pair from tmm3), adds the results of those dot-prod-
ucts, and then accumulates the result into the corresponding row and column of tmm1.
“Round to nearest even” rounding mode is used when doin g each accumulation of the FMA. Output denormals are 
always flushed to zero and input denormals are always treated as zero. MXCSR is not consulted nor updated. 
Any attempt to execute the TDPBF16PS instruction inside a TSX transaction will result in a transaction abort.
Operation
define make_fp32(x):
// The x parameter is bfloat16. Pack  it in to upper 16b of a dword.
// The bit pattern is a legal fp32 value. Return that bit pattern. 
dword: = 0dword[31:16] := x 
return dword
TDPBF16PS tsrcdest, tsrc1, tsrc2
// C = m x n (tsrcdest), A = m x k (tsrc1), B = k x n (tsrc2)
# src1 and src2 elements are pairs of bfloat16
elements_src1 := tsrc1.colsb / 4elements_src2 := tsrc2.colsb / 4elements_dest := tsrcdest.colsb / 4elements_temp := tsrcdest.colsb / 2 // Co unt is in bfloat16 prior to horizontal
for m in 0 ... tsrcdest.rows-1:
temp1[ 0 ... elements_temp-1 ] := 0for k in 0 ... elements_src1-1:
for n in 0 ... elements_dest-1:
// FP32 FMA with DAZ=FTZ=1, RNE rounding.
// MXCSR is neither consulted nor updated.// No exceptions raised or denoted.
temp1.fp32[2*n+0] += make_fp32(tsrc1.row[m].bfloat16[2*k+0]) * make_fp32(tsrc2.row[k].bfloat16[2*n+0])
temp1.fp32[2*n+1] += make_fp32(tsrc1.row[m].bfloat16[2*k+1]) * make_fp32(tsrc2.row[k].bfloat16[2*n+1])Opcode/
Mode 
VEX.128.F3.0F38.W0 5C 11:rrr:bbb
TDPBF16PS tmm1, tmm2, tmm3A V/N.E. AMX-BF16 Matrix multiply BF16 elements from tmm2 and 
tmm3, and accumulate the packed single 
precision elements in tmm1.
A N/A ModRM:reg (r, w) ModRM:r/m (r) VEX.vvvv (r) N/ATDPBF16PS—Dot Product of BF16 Tiles Accumulated into Packed Single Precision TileINSTRUCTION SET REFERENCE, M-U
4-700 Vol. 2Bfor n in 0 ... elements_dest-1:
// DAZ=FTZ=1, RNE rounding.// MXCSR is neither consulted nor updated.// No exceptions raised or denoted.tmpf32 := temp1.fp32[2*n] + temp1.fp32[2*n+1]tsrcdest.row[m].fp32[n] := ts rcdest.row[m].fp32[n] + tmpf32
write_row_and_zero(tsrcdest,  m, tmp, tsrcdest.colsb)
zero_upper_rows(tsrcdest, tsrcdest.rows)
zero_tilecfg_start()
TDPBF16PS void _tile_dpbf16ps(__tile dst, __tile src1, __tile src2);
None.
AMX-E4; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.TDPBSSD/TDPBSUD/TDPBUSD/TDPBUUD—Dot Product of Signed/Unsigned Bytes with Dword AccumulationINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-701TDPBSSD/TDPBSUD/TDPB USD/TDPBUUD—Dot Product of Sign ed/Unsigned Bytes with Dword 
Accumulation 
For each possible combination of (row of tmm2, column of tmm3), the instruction performs a set of SIMD dot-prod-
ucts on all corresponding four byte elements, one from tmm2 and one from tmm3, adds the results of those dot-
products, and then accumulates the result into the corre sponding row and column of tmm1. Each dword in input 
tiles tmm2 and tmm3 is interpreted as four byte elemen ts. These may be signed or unsigned. Each letter in the 
two-letter pattern SU, US, SS, UU indicates the signed/uns igned nature of the values in tmm2 and tmm3, respec-
tively.
Any attempt to execute the TDPBSSD/TDPBSUD/TDPBUSD/TD PBUUD instructions inside an Intel TSX transaction 
will result in a transaction abort.
Operation
define DPBD(c,x,y):// arguments are dwords 
if *x operand is signed*:
extend_src1 := SIGN_EXTEND 
else:
extend_src1 := ZERO_EXTEND
if *y operand is signed*: 
extend_src2 := SIGN_EXTEND
else:
extend_src2 := ZERO_EXTEND
p0dword := extend_src1(x.byte[0]) * extend_src2(y.byte[0]) 
p1dword := extend_src1(x.byte[1]) * extend_src2(y.byte[1]) p2dword := extend_src1(x.byte[2]) * extend_src2(y.byte[2]) p3dword := extend_src1(x.byte[3]) * extend_src2(y.byte[3])
c := c + p0dword + p1dword + p2dword + p3dwordOpcode/
Mode 
VEX.128.F2.0F38.W0 5E 11:rrr:bbb
TDPBSSD tmm1, tmm2, tmm3A V/N.E. AMX-INT8 Matrix multiply signed byte elements from tmm2 
by signed byte elements from tmm3 and 
accumulate the dword elements in tmm1.
VEX.128.F3.0F38.W0 5E 11:rrr:bbb
TDPBSUD tmm1, tmm2, tmm3A V/N.E. AMX-INT8 Matrix multiply signed byte elements from tmm2 
by unsigned byte elements from tmm3 and 
VEX.128.66.0F38.W0 5E 11:rrr:bbb
TDPBUSD tmm1, tmm2, tmm3A V/N.E. AMX-INT8 Matrix multiply unsigned byte elements from 
tmm2 by signed byte elements from tmm3 and accumulate the dword elements in tmm1.
VEX.128.NP.0F38.W0 5E 11:rrr:bbb
TDPBUUD tmm1, tmm2, tmm3A V/N.E. AMX-INT8 Matrix multiply unsigned byte elements from 
tmm2 by unsigned byte elements from tmm3 
and accumulate the dword elements in tmm1.

Mode 
A N/A ModRM:reg (r, w) ModRM:r/m (r) VEX.vvvv (r) N/ATDPBSSD/TDPBSUD/TDPBUSD/TDPBUUD—Dot Product of Signed/Unsigned Bytes with Dword AccumulationINSTRUCTION SET REFERENCE, M-U
4-702 Vol. 2BTDPBSSD, TDPBSUD, TDPBUSD, TDPBUUD tsrcdest, tsrc1, tsrc2 (Register Only Version)
tsrc1_elements_per_row := tsrc1.colsb / 4 
tsrc2_elements_per_row := tsrc2.colsb / 4 tsrcdest_elements_per_row := tsrcdest.colsb / 4
for m in 0 ... tsrcdest.rows-1: 
tmp := tsrcdest.row[m]for k in 0 ... tsrc1_elements_per_row-1:
for n in 0 ... tsrcdest_elements_per_row-1: 
DPBD( tmp.dword[n], tsrc1.row[m].d word[k], tsrc2.ro w[k].dword[n] ) 
zero_upper_rows(tsrcdest, tsrcdest.rows) 
TDPBSSD void _tile_dpbssd(__til e dst, __tile src1, __tile src2);
TDPBSUD void _tile_dpbsud(__tile dst, __tile src1, __tile src2);
TDPBUSD void _tile_dpbusd(__tile dst, __tile src1, __tile src2);
TDPBUUD void _tile_dpbuud(__tile ds t, __tile src1, __tile src2);
None.
AMX-E4; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.TEST—Logical CompareINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-703TEST—Logical Compare
Computes the bit-wise logical AND of first operand (sourc e 1 operand) and the second operand (source 2 operand) 
and sets the SF, ZF, and PF status flags according to the result. The result is then discarded.
In 64-bit mode, using a REX prefix in the form of REX. R permits access to additional registers (R8-R15). Using a 
REX prefix in the form of REX.W prom otes operation to 64 bits. See the summary chart at the beginning of this 
section for encoding data and limits.
Operation
TEMP := SRC1 AND SRC2;
SF := MSB(TEMP);
IF TEMP  = 0
FI:
PF := BitwiseXNOR(TEMP[0:7]);Opcode Instruction Op/ 
En64-Bit 
A8 ib TEST AL, imm8 I Valid Valid AND imm8 with  AL; set SF, ZF, PF according to result.
A9 iw TEST AX, imm16 I Valid Valid AND imm16 with AX; set SF, ZF, PF according to result.A9 id TEST EAX, imm32 I Valid Valid AND imm32 with EAX; se t SF, ZF, PF according to 
result.
REX.W + A9 id TEST RAX, imm32 I Valid N.E. AND imm32 sign-extended to 64-bits with RAX; set SF, 
ZF, PF according to result.
F6 /0 ib TEST r/m8, imm8 MI Valid Valid AND imm8 with r/m8; set SF, ZF, PF according to result.REX + F6 /0 ib TEST r/m8
1, imm8
NOTES:
1. In 64-bit mode, r/m8 can not be encode d to access the following byte  registers if a REX prefix is used: AH, BH, CH, DH.MI Valid N.E. AND imm8 with r/m8; set SF, ZF, PF according to result.
F7 /0 iw TEST r/m16, imm16 MI Valid Valid AND im m16 with r/m16; set SF, ZF, PF according to 
result.
F7 /0 id TEST r/m32, imm32 MI Valid Valid AND im m32 with r/m32; set SF, ZF, PF according to 
result.
REX.W + F7 /0 id TEST r/ m64, imm32 MI Valid N.E. AND imm32 sign-e xtended to 64-bits with r/m64; set 
SF, ZF, PF according to result.
84 /r TEST r/m8, r8 MR Valid Valid AND r8 with  r/m8; set SF, ZF, PF according to result.
REX + 84 /r TEST r/m81, r81MR Valid N.E. AND r8 with r/m8; set SF, ZF, PF according to result.
85 /r TEST r/m16, r16 MR Valid Valid AND r16 with r/m16; set SF, ZF, PF according to result.85 /r TEST r/m32, r32 MR Valid Valid AND r32 with r/m32; set SF, ZF, PF according to result.REX.W + 85 /r TEST r/m64, r64 MR Val id N.E. AND r64 with r/m64; set SF, ZF, PF according to result.
MR ModRM:r/m (r) ModRM:reg (r) N/A N/ATEST—Logical CompareINSTRUCTION SET REFERENCE, M-U
4-704 Vol. 2BCF := 0;
OF := 0;(* AF is undefined *)
The OF and CF flags are set to 0. The SF, ZF, and PF flags are set according to the result (see the “Operation” section 
above). The state of the AF flag is undefined.
#UD If the LOCK prefix is used.TESTUI—Determine User Interrupt FlagINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-705TESTUI—Determine User Interrupt Flag
TESTUI copies the current value of the user interrupt flag  (UIF) into EFLAGS.CF. This instruction can be executed 
regardless of CPL.
TESTUI may be executed normally  inside a transactional region.
Operation
CF := UIF;
ZF := AF := OF := PF := SF := 0;
The ZF, OF, AF, PF, SF flags are cleared and the CF flags to the value of the user interrupt flag.
#UD The TESTUI instruction is not recognized in protected mode.
#UD The TESTUI instruction is not recognized in real-address mode.
#UD The TESTUI instruction is not recognized in virtual-8086 mode.
#UD The TESTUI instruction is not recognized in compatibility mode.
Mode 
F3 0F 01 ED
TESTUIZO V/I UINTR Copies the current value of UIF into EFLAGS.CF.
ZO N/A N/A N/A N/A N/ATILELOADD/TILELOADDT1—Load TileINSTRUCTION SET REFERENCE, M-U
4-706 Vol. 2BTILELOADD/TILELOADDT1—Load Tile
This instruction is required to use SI B addressing. The index register serves  as a stride indicator. If the SIB 
encoding omits an index register, the value zero is assumed for the content of the index register.
This instruction loads a tile destination with rows and co lumns as specified by the t ile configuration. The “T1” 
version provides a hint to the implementation that the data would be reused but does not need to be resident in the 
nearest cache levels.
The TILECFG.start_row in the TILECFG data should be initialized  to '0' in order to load the entire tile and is set to 
zero on successful completion of the TILELOADD instru ction. TILELOADD is a restartable instruction and the 
TILECFG.start_row will be non-zero when restartabl e events occur during the instruction execution. 
Only memory operands are supported and they can only be accessed using a SIB addressing mode, similar to the 
V[P]GATHER*/V[P]SCATTER* instructions.
Any attempt to execute the TILELOADD/TILELOADDT1 instructio ns inside an Intel TSX transaction will result in a 
transaction abort.
Operation
TILELOADD[,T1] tdest, tsib 
start := tilecfg.start_rowzero_upper_rows(tdest,start)membegin := tsib.base + displacement
// if no index register in the SIB encoding, the value zero is used. stride := tsib.ind ex << tsib.scale
nbytes := tdest.colsb while start < tdest.rows:
memptr := membegin + start * stride write_row_and_zero(tdest, start, re ad_memory(memptr, nbytes), nbytes)
start := start + 1 
zero_tilecfg_start()// In the case of a memory fault in the middle of  an instruction, the ti lecfg.start_row := start
TILELOADD void _tile_loadd(__tile ds t, const void *base, int stride);
TILELOADDT1 void _tile_stream_loadd(__til e dst, const void *base, int stride);Opcode/
Mode 
VEX.128.F2.0F38.W0 4B !(11):rrr:100
TILELOADD tmm1, sibmemA V/N.E. AMX-TILE Load data into tm m1 as specified by information 
in sibmem.
VEX.128.66.0F38.W0 4B !(11):rrr:100

Operation
Mode 
in sibmem.
TILELOADDT1 tmm1, sibmemA V/N.E. AMX-TILE Load data into tm m1 as specified by information 
in sibmem with hint to  optimize data caching.
A N/A ModRM:reg (w) ModRM:r/m (r) N/A N/ATILELOADD/TILELOADDT1—Load TileINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-707Flags Affected
None.
AMX-E3; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.TILERELEASE—Release TileINSTRUCTION SET REFERENCE, M-U
4-708 Vol. 2BTILERELEASE—Release Tile
This instruction returns TILECFG and TILEDATA to the INIT state.
Any attempt to execute the TILERELEASE instruction inside  an Intel TSX transaction will result in a transaction 
abort.
Operation
tilecfg := 0// equivale nt to 64B of zeros 
TILES_CONFIGURED := 0
TILERELEASE void _t ile_release(void);
None.
AMX-E6; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.Opcode/
Mode 
VEX.128.NP.0F38.W0 49 C0 
TILERELEASEA V/N.E. AMX-TILE Initialize TILECFG and TILEDATA.
A N/A N/A N/A N/A N/ATILESTORED—Store TileINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-709TILESTORED—Store Tile
This instruction is required to use SIB addressing. The in dex register serves as a stride indicator. If the SIB 
This instruction stores a tile source of rows and columns as specified by the tile configuration.The TILECFG.start_row in the TILECFG data should be initialized to '0' in order to store the entire tile and are set to 
zero on successful completion of the TILESTORED instru ction. TILESTORED is a restartable instruction and the 
TILECFG.start_row will be non-zero when restartabl e events occur during the instruction execution.
V[P]GATHER*/V[P]SCATTER* instructions. 
Any attempt to execute the TILESTORED instruction inside an Intel TSX transaction will result in a transaction 
abort.
Operation
TILESTORED tsib, tsrc
start := tilecfg.start_rowmembegin := tsib.base + displacement
while start < tdest.rows:
memptr := membegin + start * stride write_memory(memptr, tsrc.colsb, tsrc.row[start]) start := start + 1
TILESTORED void _tile_stored(__tile src, void *base, int stride);
None.
AMX-E3; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.Opcode/
Mode 
VEX.128.F3.0F38.W0 4B !(11):rrr:100
TILESTORED sibmem, tmm1A V/N.E. AMX-TILE Store a tile in sibmem as specified in tmm1.
A N/A ModRM:r/m (w) ModRM:reg (r) N/A N/ATILEZERO—Zero TileINSTRUCTION SET REFERENCE, M-U
4-710 Vol. 2BTILEZERO—Zero Tile
This instruction zeroes the destination tile.
Any attempt to execute the TILEZERO instruction inside an Intel TSX transaction will result in a transaction abort.
Operation
TILEZERO tdest
nbytes := palette_table[palette_id].bytes_per_row for i in 0 ... palette_tab le[palette_id].max_rows-1:
for j in 0 ... nbytes-1: 
tdest.row[i].byte[j] := 0
TILEZERO void _tile_zero(__tile dst);
None.
AMX-E5; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.Opcode/
Mode 
VEX.128.F2.0F38.W0 49 11:rrr:000
TILEZERO tmm1A V/N.E. AMX-TILE Zero the destination tile.
A N/A ModRM:reg (w) N/A N/A N/ATPAUSE—Timed PAUSEINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-711TPAUSE—Timed PAUSE
TPAUSE instructs the processor to enter an implementati on-dependent optimized state.  There are two such opti-
mized states to choose from: light-weight power/performa nce optimized state, and improved power/performance 
optimized state. The selection between the two is governed  by the explicit input register bit[0] source operand.
TPAUSE is available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. TPAUSE may be executed at any 
privilege level. This instruction’s operation is the same in non-64-bit modes and in 64-bit mode.
Unlike PAUSE, the TPAUSE instruction will not cause an abort when used inside a transactional region, described in 
the chapter Chapter 16, “Programming with Intel® Tran sactional Synchronization Extensions,” of the Intel® 64 and 
The input register contains information such as the preferred optimized state the processor should enter as 
described in the following table. Bits other than bit 0 are reserved and will result in #GP if non-zero.
The instruction execution wakes up when the time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit 
input value.
Prior to executing the TPAUSE instru ction, an operating system may specify the maximum delay it allows the 
processor to suspend its operation. It can do so by writing TSC-quanta value to the following 32-bit MSR 
(IA32_UMWAIT_CONTROL at MSR index E1H):
•IA32_UMWAIT_CONTROL[31:2] — Determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. A zero va lue indicates no maximum time. The maximum time value is a 32-bit value 
where the upper 30 bits come from this  field and the lower two bits are zero.
•IA32_UMWAIT_CONTROL[1] — Reserved.
•IA32_UMWAIT_CONTROL[0] — C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert to 
C0.1.
If the processor that executed a TPAUSE instruction wakes due to the expiration of the operating system time-limit, 
the instructions sets RFLAGS.CF; otherwise, that flag is cleared.
The following additional events cause the processor to ex it the implementation-dependent optimized state: a store 
to the read-set range within the transactional region, an  NMI or SMI, a debug exception, a machine check excep-
tion, the BINIT# signal, the INIT# signal, and the RESET# signal.Opcode /
Mode 
Feature 
66 0F AE /6
TPAUSE r32, <edx>, <eax>A V/V WAITPKG Directs the processor to enter an implementation-dependent 
optimized state until the TSC reaches the value in EDX:EAX.
1. The Mod field of the ModR/M byte must have value 11B.Table 4-20.  TPAUSE Input Register Bit Definitions
Bit Value State Name Wakeup Time Power Savings Other Benefits
bit[0] = 0 C0.2 Slower Larger Improves performance of the other SMT thread(s) 
on the same core.
bit[0] = 1 C0.1 Faster Smaller N/Abits[31:1] N/A N/A N/A ReservedTPAUSE—Timed PAUSEINSTRUCTION SET REFERENCE, M-U
4-712 Vol. 2BOther implementation-dependent events may cause the pr ocessor to exit the implementation-dependent opti-
mized state proceeding to the instruction following TPAUSE. In addition, an external interrupt causes the processor 
to exit the implementation-dependent optimized state regardless of whether maskable-interrupts are inhibited 
(EFLAGS.IF =0). It should be noted that if maskable-int errupts are inhibited execution will proceed to the instruc-
tion following TPAUSE.
Operation
os_deadline := TSC+(IA32_UMWAIT_CONTROL[31:2]<<2)
instr_deadline := UINT64(EDX:EAX)
IF os_deadline < instr_deadline:
deadline := os_deadlineusing_os_deadline := 1
ELSE:
deadline := instr_deadlineusing_os_deadline := 0
WHILE TSC < deadline:
implementation_dependent_optimized_state(Source register, deadline, IA32_UMWAIT_CONTROL[0])
IF using_os_deadline AND TSC 
≥ deadline:
RFLAGS.CF := 1
ELSE:
RFLAGS.CF := 0
RFLAGS.AF,PF,SF,ZF,OF := 0
TPAUSE uint8_t _tpause(uint32_t control, uint64_t counter);
None.
#GP(0) If src[31:1] != 0.
If CR4.TSD = 1 and CPL != 0.
#UD If CPUID.7.0:ECX.WAITPKG[bit 5]=0. TZCNT—Count the Number of Trailing Zero BitsINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-713TZCNT—Count the Number of Trailing Zero Bits
TZCNT counts the number of trailing least significant zero  bits in source operand (second operand) and returns the 
result in destination operand (first operand). TZCNT is an extension of the BSF instruction. The key difference

ELSE:
ELSE:
None.
result in destination operand (first operand). TZCNT is an extension of the BSF instruction. The key difference 
between TZCNT and BSF instruction is that TZCNT provides operand size as output when source operand is zero 
while in the case of BSF instruction, if source operand is  zero, the content of destination operand are undefined. On 
processors that do not support TZCNT, the instruction byte encoding is executed as BSF.
Operation
temp := 0
DEST := 0DO WHILE ( (temp < OperandSiz e) and (SRC[ temp] = 0) )
temp := temp +1
DEST := DEST+ 1
OD
CF := 1
ELSE
CF := 0
FI
IF DEST = 0
ZF := 1
ELSE
ZF := 0
FI
ZF is set to 1 in case of zero output (least significant bit of the source is set), and to 0 otherwise, CF is set to 1 if 
the input was zero and cleared otherwise. OF, SF, PF, and AF flags are undefined.
TZCNT unsigned __int32 _tzcnt _u32(unsigned __int32 src);
TZCNT unsigned __int64 _tzcnt _u64(unsigned __int64 src);Opcode/
En64/32-
F3 0F BC /r
TZCNT r16, r/m16A V/V BMI1 Count the number of trailing zero bits in r/m1 6, return result in r16.
F3 0F BC /r
TZCNT r32, r/m32A V/V BMI1 Count the number of trailing zero bits in r/m3 2, return result in r32.
F3 REX.W 0F BC /r
TZCNT r64, r/m64A V/N.E. BMI1 Count the number of trailing ze ro bits in r/m64, return result in r64.
A ModRM:reg (w) ModRM:r/m (r) N/A N/ATZCNT—Count the Number of Trailing Zero BitsINSTRUCTION SET REFERENCE, M-U
4-714 Vol. 2BProtected Mode Exceptions
selector.
#SS(0) For an illegal address in the SS segment.#UD If LOCK prefix is used.
#UD If LOCK prefix is used.UCOMISD—Unordered Compare Scalar Double Prec ision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-715UCOMISD—Unordered Compare Scalar  Double Precision Floating-P oint Values and Set EFLAGS 
Performs an unordered compare of the double precision fl oating-point values in the low quadwords of operand 1 
(first operand) and operand 2 (second operand), and sets th e ZF, PF, and CF flags in the EFLAGS register according 
to the result (unordered, greater than, less than, or equal) . The OF, SF, and AF flags in the EFLAGS register are set 
to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memorylocation. The UCOMISD instruction differs from the COMISD instruction in that it signals a SIMD floating-point invalid oper-
ation exception (#I) only when a source operand is an SNaN. The COMISD instruction signals an invalid operation 
exception only if a source operan d is either an SNaN or a QNaN.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCOMISD is encoded with VE X.L=0. Encoding VCOMISD with VEX.L=1 may encounter 
Operation
(V)UCOMISD (All Versions)
RESULT := UnorderedCompare(DEST[63:0] <> SRC[63:0]) {(* Set EFLAGS *) CASE (RESULT) OF
Mode 
Feature 
66 0F 2E /r
UCOMISD xmm1, xmm2/m64A V/V SSE2 Compare low double precision floating-point values in xmm1 
and xmm2/mem64 and set the EFLAGS flags accordingly.
VEX.LIG.66.0F.WIG 2E /r
VUCOMISD xmm1, xmm2/m64A V/V AVX Compare low double precision floating-point values in xmm1 
EVEX.LLIG.66.0F.W1 2E /r
VUCOMISD xmm1, xmm2/m64{sae}B V/V AVX512F Compare low double precision floating-point values in xmm1 
and xmm2/m64 and set the EFLAGS flags accordingly.
A N/A ModRM:reg (r) ModRM:r/m (r) N/A N/A
B Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AUCOMISD—Unordered Compare Scalar Double Prec ision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, M-U
4-716 Vol. 2BIntel C/C++ Compiler Intrinsic Equivalent
VUCOMISD int _mm_comi_rou nd_sd(__m128d a, __m128d b, int imm, int sae); 
UCOMISD int _mm_ucomieq_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomilt_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomile_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomigt_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomige_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomineq_sd(__m128d a, __m128d b)
Invalid (if SNaN operands), Denormal.
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”UCOMISS—Unordered Compare Scalar Single Prec ision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-717UCOMISS—Unordered Compare Scalar Single Prec ision Floating-Point Va lues and Set EFLAGS 
Compares the single precision floating-point values in  the low doublewords of operand 1 (first operand) and 
operand 2 (second operand), and sets the ZF, PF, and CF flag s in the EFLAGS register according to the result (unor-
dered, greater than, less than, or equal). The OF, SF, and AF  flags in the EFLAGS register are set to 0. The unor-
dered result is returned if either so urce operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location. The UCOMISS instruction differs from the COMISS instruction in that it signals a SIMD floating-point invalid opera-
tion exception (#I) only if a source operand is an SNaN . The COMISS instruction signals an invalid operation excep-
tion when a source operand is either a QNaN or SNaN.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCOMISS is encoded with VE X.L=0. Encoding VCOMISS with VEX.L=1 may encounter 
Operation
(V)UCOMISS (All Versions)
RESULT := UnorderedCompare(DEST[31:0] <> SRC[31:0]) {(* Set EFLAGS *) CASE (RESULT) OF
ESAC;OF, AF, SF := 0; }
VUCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae); 
UCOMISS int _mm_ucomieq_ss(__m128 a, __m128 b);UCOMISS int _mm_ucomilt_ss(__m128 a, __m128 b);UCOMISS int _mm_ucomile_ss(__m128 a, __m128 b);UCOMISS int _mm_ucomigt_ ss(__m128 a, __m128 b);
UCOMISS int _mm_ucomige_ss(__m128 a, __m128 b);UCOMISS int _mm_ucomineq_ss(__m128 a, __m128 b);Opcode/
Mode 
Feature 
NP 0F 2E /r
UCOMISS xmm1, xmm2/m32A V/V SSE Compare low single precision floating-point values in xmm1 
and xmm2/mem32 and set the EFLAGS flags accordingly.
VEX.LIG.0F.WIG 2E /r
VUCOMISS xmm1, xmm2/m32A V/V AVX Compare low single precision floating-point values in xmm1 
EVEX.LLIG.0F.W0 2E /r
VUCOMISS xmm1, xmm2/m32{sae}B V/V AVX512F Compare low single precision floating-point values in xmm1 

Mode 
Feature 
NP 0F 2E /r
B Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AUCOMISS—Unordered Compare Scalar Single Prec ision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, M-U
4-718 Vol. 2BSIMD Floating-Point Exceptions
Invalid (if SNaN Operands), Denormal.
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”UD—Undefined InstructionINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-719UD—Undefined Instruction
Generates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an 
invalid opcode exception. The opcodes for this instruction are reserved for this purpose.
Other than raising the invalid opcode exception, this in struction has no effect on processor state or memory.
Even though it is the execution of th e UD instruction that causes the invalid opcode exception, the instruction 
pointer saved by delivery of the exception references th e UD instruction (and not the following instruction).
Operation
#UD (* Generates invalid opcode exception *);
None.
#UD Raises an invalid opcode exception in all operating modes.Opcode Instruction Op/ 
En64-Bit 
0F FF /r UD01 r32, r/m32
NOTES:
1. Some processors decode the UD0 instruction without a ModR/M byte. As a result, those processors would deliver an invalid-opc ode 
exception instead of a fault on instruction fetch when the instru ction with a ModR/M byte (and any implied bytes) would cross a  page 
or segment boundary.RM Valid Valid Raise invalid opcode exception.
0F B9 /r UD1 r32, r/m32 RM Valid Valid Raise invalid opcode exception.0F 0B UD2 ZO Valid Valid Raise invalid opcode exception.
RM ModRM:reg (r) ModRM:r/m (r) N/A N/AUIRET—User-Interrupt ReturnINSTRUCTION SET REFERENCE, M-U
4-720 Vol. 2BUIRET—User-Interrupt Return
UIRET returns from the handling of a user in terrupt. It can be executed regardless of CPL.
Execution of UIRET inside a transactional region causes a transactional abort; the abort loads EAX as it would have 
had it been due to an execution of IRET.
UIRET can be tracked by Architectural Last Branch Record s (LBRs), Intel Processor Trace (Intel PT), and Perfor-
mance Monitoring. For both Intel PT and LBRs, UIRET is recorded in precisely the same manner as IRET. Hence for LBRs, UIRETs fall into the OTHER_BRANCH category, wh ich implies that IA32_LBR_CTL.OTHER_BRANCH[bit 22] 
must be set to record user-interrupt delivery, and that the IA32_LBR_x_INFO.BR_TYPE field will indicate 
OTHER_BRANCH for any recorded user interrupt. For Intel PT, control flow tracing mu st be enabled by setting 
IA32_RTIT_CTL.BranchEn[bit 13].
UIRET will also increment performance counters for wh ich counting BR_INST_RETIRED.FAR_BRANCH is enabled.
Operation
Pop tempRIP;
Pop tempRFLAGS; // see below for ho w this is used to load RFLAGS
Pop tempRSP;IF tempRIP is not canonical in current paging mode
THEN
PopShadowStack SSRIP;IF SSRIP 
≠ tempRIP
THEN #CP (FAR-RET/IRET);
FI;
FI;RIP := tempRIP;// update in RFLA GS only CF, PF, AF, ZF, SF, TF, DF, OF, NT, RF, AC, and ID
RFLAGS := (RFLAGS & ~254DD5H) | (tempRFLAGS & 254DD5H);RSP := tempRSP;UIF := 1;Clear any cache-line monitoring established by MONITOR or UMONITOR;
See the Operation section.
#UD The UIRET instruction is not recognized in protected mode.Opcode/
Mode 
F3 0F 01 EC
UIRET ZO V/I UINTR Return from handling a user interrupt.
ZO N/A N/A N/A N/A N/AUIRET—User-Interrupt ReturnINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-721Real-Address Mode Exceptions
#UD The UIRET instruction is not recognized in real-address mode.
#UD The UIRET instruction is not recognized in virtual-8086 mode.
#UD The UIRET instruction is not re cognized in compatibility mode.
#SS(0) If an attempt to pop a value off the stack causes a non-canonical address to be referenced.
current privilege level is 3. 
#CP If return instruction pointer from stack and shadow stack do not match.#UD If the LOCK prefix is used.
If CR4.UINTR = 0.If CPUID.07H.0H:EDX.UINTR[bit 5] = 0.UMONITOR—User Level Set Up Monitor AddressINSTRUCTION SET REFERENCE, M-U
4-722 Vol. 2BUMONITOR—User Level Set Up Monitor Address
The UMONITOR instruction arms address monitoring hardwa re using an address specified in the source register 
(the address range that the monitoring hardware checks  for store operations can be determined by using the 
CPUID monitor leaf function, EAX=05H) . A store to an address within the specified address range triggers the 
monitoring hardware. The state of monitor hardware is used by UMWAIT.
The content of the source register is an effective address.  By default, the DS segment is used to create a linear 
address that is monitored. Segment overrides can be used . The address range must use memory of the write-back 
type. Only write-back memory is guaranteed to correctly  trigger the monitoring hardware. Additional information 
on determining what address range to use in order to prev ent false wake-ups is described in Chapter 9, “Multiple-
Processor Management‚” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
The UMONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruc-
tion is subject to the permission checking and faults asso ciated with a byte load. Like a load, UMONITOR sets the 
A-bit but not the D-bit in page tables.
UMONITOR and UMWAIT are available when CPUID.7.0:ECX. WAITPKG[bit 5] is enumerated as 1. UMONITOR and 
UMWAIT may be executed at any privilege level. Except fo r the width of the source register, the instruction’s oper-
ation is the same in non-64-bit modes and in 64-bit mode.
UMONITOR does not interoperate with the legacy MWAIT in struction. If UMONITOR was executed prior to executing 
MWAIT and following the most recent execution of the le gacy MONITOR instruction, MWAIT will not enter an opti-
mized state. Execution will continue to the instruction following MWAIT.
The UMONITOR instruction causes a transactional abort when used inside a transactional region.
The width of the source register (16b, 32b or 64b) is determined by the effective addressing width, which is 
affected in the standard way by the machine mode settings and 67 prefix.
Operation
UMONITOR sets up an address range for the monitor hardware using the content of source register as an effective 
address and puts the monitor hardware in armed state. A store to the specified address range will trigger the 
monitor hardware.
UMONITOR void _umonitor(void *address);
None.Opcode /
Mode 
Feature 
F3 0F AE /6
UMONITOR r16/r32/r64A V/V WAITPKG Sets up a linear address range to be monitored by 
should be a write-back memory caching type. The 
address is contained in r16/r32/r64.
1. The Mod field of the ModR/M byte must have value 11B.UMONITOR—User Level Set Up Monitor AddressINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-723Protected Mode Exceptions
#GP(0) If the specified segment is not SS and the source register is outside the specified segment 
limit.
If the specified segment register contains a NULL segment selector.
#SS(0) If the specified segment is SS and the so urce register is outside the SS segment limit.
#PF(fault-code) For a page fault.#UD If CPUID.7.0:ECX.WAITPKG[bit 5]=0.
#GP If the specified segment is not SS and the source register is outside of the effective address 
space from 0 to FFFFH.
#SS If the specified segment is SS and the source register is outside of the effective address space 
from 0 to FFFFH.
#UD If CPUID.7.0:ECX.WAITPKG[bit 5]=0.
Same exceptions as in real address mode; additionally:#PF(fault-code) For a page fault.

limit.
#GP(0) If the specified segment is not SS and the linear address is in non-canonical form.#SS(0) If the specified segment is SS and the source register is in non-canonical form.
#UD If CPUID.7.0:ECX.WAITPKG[bit 5]=0.UMWAIT—User Level Monitor WaitINSTRUCTION SET REFERENCE, M-U
4-724 Vol. 2BUMWAIT—User Level Monitor Wait 
UMWAIT instructs the processor to enter an implementati on-dependent optimized state while monitoring a range 
of addresses. The optimized state may be either a light-w eight power/performance optimized state or an improved 
power/performance optimized state. The selection between the two states is governed by the explicit input register 
bit[0] source operand.
UMWAIT is available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. UMWAIT may be executed at any 
described in the following table. Bits other than bi t 0 are reserved and will result in #GP if nonzero.
The instruction wakes up when the time-stamp counter reac hes or exceeds the implicit EDX:EAX 64-bit input value 
(if the monitoring hardware did not trigger beforehand).
Prior to executing the UMWAIT instruction, an operatin g system may specify the maximum delay it allows the 
processor to suspend its operation. It can do so by writ ing TSC-quanta value to the following 32bit MSR (IA32_UM-
WAIT_CONTROL at MSR index E1H):
•IA32_UMWAIT_CONTROL[31:2] — Determines the maximum ti me in TSC-quanta that the processor can reside 
in either C0.1 or C0.2. A zero value indicates no ma ximum time. The maximum time value is a 32-bit value 
C0.1.
If the processor that executed a UMWAIT instruction wake s due to the expiration of the operating system time-
limit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.
The UMWAIT instruction causes a transactional ab ort when used inside a transactional region.
The UMWAIT instruction operates with the UMONITOR instru ction. The two instructions allow the definition of an 
address at which to wait (UMONITOR) and an implemen tation-dependent optimized operation to perform while 
waiting (UMWAIT). The execution of UMWAIT is a hint to the processor that it can enter an implementation-depen-
dent-optimized state while waiting for an event or a stor e operation to the address range armed by UMONITOR. The 
UMWAIT instruction will not wait (will not enter an impl ementation-dependent optimized state) if any of the Opcode /
Mode 
Feature 
F2 0F AE /6
UMWAIT r32, <edx>, <eax>A V/V WAITPKG A hint that allows th e processor to stop instruction 
optimized state until occurrence of a class of events.
1. The Mod field of the ModR/M byte must have value 11B.Table 4-21.  UMWAIT Input Register Bit Definitions
Bit Value State Name Wakeup Time Power Savings Other Benefitsbit[0] = 0 C0.2 Slower Larger Improves performance of the other SMT thread (s) on the same core.
bit[0] = 1 C0.1 Faster Smaller N/A
bits[31:1] N/A N/A N/A ReservedUMWAIT—User Level Monitor WaitINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-725following instructions were executed before UMWAIT an d after the most recent execution of UMONITOR: IRET, 
MONITOR, SYSEXIT, SYSRET, and far RET (the last if it is changing CPL).
to the address range armed by the UMONITOR instruction, an NMI or SMI, a debug exception, a machine check 
exception, the BINIT# signal, the INIT# signal, and the RESET# signal. Other implem entation-dependent events 
may also cause the processor to exit the implementation-dependent optimized state.
In addition, an external interrupt causes the processo r to exit the implementation-dependent optimized state 
regardless of whether maskable-interrupts are inhibited (EFLAGS.IF =0).
Following exit from the implementation-dependent-optimiz ed state, control passes to the instruction after the 
UMWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before 
execution of that instruction.
Unlike the HLT instruction, the UMWAIT instruction does  not restart at the UMWAIT instruction following the 
handling of an SMI.
If the preceding UMONITOR instruction did not successf ully arm an address range or if UMONITOR was not 
executed prior to executing UMWAIT and following the mo st recent execution of the legacy MONITOR instruction 
(UMWAIT does not interoperate with MONITOR), then the processor will not enter an optimized state. Execution 
will continue to the inst ruction following UMWAIT.
A store to the address range armed by the UMONITOR instruction will cause the processor to exit UMWAIT if either 
the store was originated by other processor agents or  the store was originated by a non-processor agent.
Operation
ELSE:
WHILE monitor hardware armed AND TSC < deadline:
implementation_dependent_optimized_state(Source register, deadline, IA32_UMWAIT_CONTROL[0] )
ELSE:
UMWAIT uint8_t _umwait(uint32_t control, uint64_t counter);
None.
#UD If CPUID.7.0:ECX.WAITPKG[bit 5]=0.UNPCKHPD—Unpack and Interleave High Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-726 Vol. 2BUNPCKHPD—Unpack and Interleave High Packed  Double Precision Floating-Point Values
Performs an interleaved unpack of the high double precisio n floating-point values from the first source operand and 
the second source operand. See Figure 4-15 in the In tel® 64 and IA-32 Architectures Software Developer’s 
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch 
only the appropriate 64 bits; however, alignment to 16 -byte boundary and normal segment checking will still be 
enforced.
the corresponding ZMM register destination are zeroed. 
register or a 256-bit memory location. Th e destination operand is a YMM register.
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a ZMM register, conditionally updated using writemask k1. 
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM 
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a YMM register, cond itionally updated using writemask k1. Opcode/
Mode 
66 0F 15 /r
UNPCKHPD xmm1, xmm2/m128A V/V SSE2 Unpacks and Interleaves double precision floating-point 
values from high quadword s of xmm1 and xmm2/m128.
VEX.128.66.0F.WIG 15 /r
VUNPCKHPD xmm1,xmm2, 
xmm3/m128B V/V AVX Unpacks and Interleaves double precision floating-point 
values from high quadword s of xmm2 and xmm3/m128.
VEX.256.66.0F.WIG 15 /r
VUNPCKHPD ymm1,ymm2, 
ymm3/m256B V/V AVX Unpacks and Interleaves double precision floating-point 
values from high quadwords of ymm2 and ymm3/m256.
EVEX.128.66.0F.W1 15 /r
VUNPCKHPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstC V/V AVX512VL
AVX512FUnpacks and Interleaves double precision floating-point 
values from high qu adwords of xmm2 and 
xmm3/m128/m64bcst subject to writemask k1.
EVEX.256.66.0F.W1 15 /r
VUNPCKHPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstC V/V AVX512VL

Mode 
66 0F 15 /r
values from high quadwords of ymm2 and ymm3/m256/m64bcst subject to writemask k1.
EVEX.512.66.0F.W1 15 /r
VUNPCKHPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Unpacks and Interleaves double precision floating-point 
values from high qu adwords of zmm2 and 
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AUNPCKHPD—Unpack and Interleave High Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-727EVEX.128 encoded version: The first source operand is  a XMM register. The second source operand is a XMM 
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a XMM register, conditionally updated using writemask k1. 
Operation
VUNPCKHPD (EVEX Encoded Versions When SRC2 is a Register)
IF VL >= 128
TMP_DEST[63:0] := SRC1[127:64]TMP_DEST[127:64] := SRC2[127:64]
TMP_DEST[191:128] := SRC1[255:192]TMP_DEST[255:192] := SRC2[255:192]
FI;
IF VL >= 512
TMP_DEST[319:256] := SRC1[383:320]TMP_DEST[383:320] := SRC2[383:320]TMP_DEST[447:384] := SRC1[511:448]TMP_DEST[511:448] := SRC2[511:448]
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0UNPCKHPD—Unpack and Interleave High Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-728 Vol. 2BVUNPCKHPD (EVEX Encoded Version When SRC2 is Memory)
i := j * 64IF (EVEX.b = 1)
FI;
TMP_DEST[63:0] := SRC1[127:64]TMP_DEST[127:64] := TMP_SRC2[127:64]
TMP_DEST[191:128] := SRC1[255:192]TMP_DEST[255:192] := TMP_SRC2[255:192]
TMP_DEST[319:256] := SRC1[383:320]TMP_DEST[383:320] := TMP_SRC2[383:320]TMP_DEST[447:384] := SRC1[511:448]TMP_DEST[511:448] := TMP_SRC2[511:448]
FI;
FI
FI;
VUNPCKHPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[127:64]DEST[127:64] := SRC2[127:64]DEST[191:128] := SRC1[255:192]DEST[255:192] := SRC2[255:192]DEST[MAXVL-1:256] := 0
VUNPCKHPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[127:64]DEST[127:64] := SRC2[127:64]DEST[MAXVL-1:128] := 0
UNPCKHPD (128-bit Legacy SSE Version)
DEST[63:0] := SRC1[127:64]DEST[127:64] := SRC2[127:64]DEST[MAXVL-1:128] (Unmodified)UNPCKHPD—Unpack and Interleave High Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-729Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKHPD __m512d _mm512_unpackhi_pd( __m512d a, __m512d b);
VUNPCKHPD __m512d _mm512_mask_unpackhi_pd(__m5 12d s, __mmask8 k, __m512d a, __m512d b);
VUNPCKHPD __m512d _mm512_maskz_unpackhi_ pd(__mmask8 k, __m512d a, __m512d b);
VUNPCKHPD __m256d _mm256_unpackhi_pd(__m256d a, __m256d b)VUNPCKHPD __m256d _mm256_mask_unpackhi_pd(__m2 56d s, __mmask8 k, __m256d a, __m256d b);
VUNPCKHPD __m256d _mm256_maskz_unpackhi_ pd(__mmask8 k, __m256d a, __m256d b);
UNPCKHPD __m128d _mm_unpackhi_pd(__m128d a, __m128d b)VUNPCKHPD __m128d _mm_mask_unpackhi_pd(__m128 d s, __mmask8 k, __m128d a, __m128d b);
VUNPCKHPD __m128d _mm_maskz_unpackhi_p d(__mmask8 k, __m128d a, __m128d b);
None.
Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions.”UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-730 Vol. 2BUNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point Values
Performs an interleaved unpack of the high single precisio n floating-point values from the first source operand and 
the second source operand. 
enforced.
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.
source operand and destination operands are YMM registers.Opcode/
Mode 
Feature 
NP 0F 15 /r
UNPCKHPS xmm1, xmm2/m128A V/V SSE Unpacks and Interleaves single precision floating-point 
VEX.128.0F.WIG 15 /r
VUNPCKHPS xmm1, xmm2, 
xmm3/m128B V/V AVX Unpacks and Interleaves single precision floating-point 
VEX.256.0F.WIG 15 /r
VUNPCKHPS ymm1, ymm2, 
ymm3/m256B V/V AVX Unpacks and Interleaves single precision floating-point 
values from high quadword s of ymm2 and ymm3/m256.
EVEX.128.0F.W0 15 /r
VUNPCKHPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstC V/V AVX512VL
AVX512FUnpacks and Interleaves single precision floating-point 
xmm3/m128/m32bcst and write re sult to xmm1 subject to 
EVEX.256.0F.W0 15 /r
VUNPCKHPS ymm1 {k1}{z}, ymm2, 
values from high qu adwords of ymm2 and 
ymm3/m256/m32bcst and write result to ymm1 subject to 
EVEX.512.0F.W0 15 /r
VUNPCKHPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512F Unpacks and Interleaves single precision floating-point 
zmm3/m512/m32bcst and write re sult to zmm1 subject to 
CF u l lM o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/AUNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-731EVEX.512 encoded version: The first source operand is  a ZMM register. The second source operand is a ZMM 
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destina-
EVEX.256 encoded version: The first source operand is  a YMM register. The second source operand is a YMM 
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a YMM register, cond itionally updated using writemask k1. 
EVEX.128 encoded version: The first source operand is  a XMM register. The second source operand is a XMM 
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-
Operation
VUNPCKHPS (EVEX Encoded Version When SRC2 is a Register)
(KL, VL) = (4, 128), (8, 256), (16, 512)IF VL >= 128
TMP_DEST[31:0] := SRC1[95:64]TMP_DEST[63:32] := SRC2[95:64]TMP_DEST[95:64] := SRC1[127:96]TMP_DEST[127:96] := SRC2[127:96]
TMP_DEST[159:128] := SRC1[223:192]TMP_DEST[191:160] := SRC2[223:192]TMP_DEST[223:192] := SRC1[255:224]TMP_DEST[255:224] := SRC2[255:224]
TMP_DEST[287:256] := SRC1[351:320]TMP_DEST[319:288] := SRC2[351:320]TMP_DEST[351:320] := SRC1[383:352]TMP_DEST[383:352] := SRC2[383:352]TMP_DEST[415:384] := SRC1[479:448]TMP_DEST[447:416] := SRC2[479:448]TMP_DEST[479:448] := SRC1[511:480]TMP_DEST[511:480] := SRC2[511:480]
FI;Figure 4-27.  VUNPCKHPS OperationDESTSRC1
SRC2X0 X1 X2 X3
Y0 Y1 Y2 Y3
X2 Y2 X3 Y3 X6 Y6 X7 Y7X4 X5 X6 X7
Y4 Y5 Y6 Y7UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-732 Vol. 2BFOR j := 0 TO KL-1
THEN DEST[i+31:i] := TMP_DEST[i+31:i]ELSE

Y0 Y1 Y2 Y3
FI
FI;
VUNPCKHPS (EVEX Encoded Version When SRC2 is Memory)
i := j * 32IF (EVEX.b = 1)
FI;
TMP_DEST[31:0] := SRC1[95:64]TMP_DEST[63:32] := TMP_SRC2[95:64]TMP_DEST[95:64] := SRC1[127:96]TMP_DEST[127:96] := TMP_SRC2[127:96]
TMP_DEST[159:128] := SRC1[223:192]TMP_DEST[191:160] := TMP_SRC2[223:192]TMP_DEST[223:192] := SRC1[255:224]TMP_DEST[255:224] := TMP_SRC2[255:224]
TMP_DEST[287:256] := SRC1[351:320]TMP_DEST[319:288] := TMP_SRC2[351:320]TMP_DEST[351:320] := SRC1[383:352]TMP_DEST[383:352] := TMP_SRC2[383:352]TMP_DEST[415:384] := SRC1[479:448]TMP_DEST[447:416] := TMP_SRC2[479:448]TMP_DEST[479:448] := SRC1[511:480]TMP_DEST[511:480] := TMP_SRC2[511:480]
DEST[i+31:i] := 0UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-733FI;
FI;
VUNPCKHPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[95:64]DEST[63:32] := SRC2[95:64]DEST[95:64] := SRC1[127:96]DEST[127:96] := SRC2[127:96]DEST[159:128] := SRC1[223:192]DEST[191:160] := SRC2[223:192]DEST[223:192] := SRC1[255:224]DEST[255:224] := SRC2[255:224]DEST[MAXVL-1:256] := 0
VUNPCKHPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[95:64]DEST[63:32] := SRC2[95:64]DEST[95:64] := SRC1[127:96]DEST[127:96] := SRC2[127:96]DEST[MAXVL-1:128] := 0
UNPCKHPS (128-bit Legacy SSE Version)
DEST[31:0] := SRC1[95:64]DEST[63:32] := SRC2[95:64]DEST[95:64] := SRC1[127:96]DEST[127:96] := SRC2[127:96]DEST[MAXVL-1:128 ] (Unmodified)
VUNPCKHPS __m512 _mm512_unpackhi_ps( __m512 a, __m512 b);
VUNPCKHPS __m512 _mm512_mask_unpackhi_ps( __m512 s, __mmask16 k, __m512 a, __m512 b);
VUNPCKHPS __m512 _mm512_maskz_unpackh i_ps(__mmask16 k, __m512 a, __m512 b);
VUNPCKHPS __m256 _mm256_unpackhi_ps (__m256 a, __m256 b);VUNPCKHPS __m256 _mm256_mask_unpackhi_ps(__ m256 s, __mmask8 k, __m256 a, __m256 b);
VUNPCKHPS __m256 _mm256_maskz_unpackhi_ ps(__mmask8 k, __m256 a, __m256 b);
UNPCKHPS __m128 _mm_unpackhi_ps (__m128 a, __m128 b);VUNPCKHPS __m128 _mm_mask_unpackhi_ps(__m12 8 s, __mmask8 k, __m128 a, __m128 b);
VUNPCKHPS __m128 _mm_maskz_unpackhi_p s(__mmask8 k, __m128 a, __m128 b);
None.
EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions.”UNPCKLPD—Unpack and Interleave Low Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-734 Vol. 2BUNPCKLPD—Unpack and Interleave Low Packed Double Precision Floating-Point Values
Performs an interleaved unpack of the low double precision floating-point values from the first source operand and 
the second source operand.
enforced.
EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM 
tion operand is a XMM register, conditionally updated using writemask k1. Opcode/
Mode 
66 0F 14 /r
UNPCKLPD xmm1, xmm2/m128A V/V SSE2 Unpacks and Interleaves double precision floating-point 
values from low quadwords of xmm1 and xmm2/m128.
VEX.128.66.0F.WIG 14 /r
VUNPCKLPD xmm1,xmm2, 
values from low quadwords of xmm2 and xmm3/m128.
VEX.256.66.0F.WIG 14 /r
VUNPCKLPD ymm1,ymm2, 
values from low quadword s of ymm2 and ymm3/m256.
EVEX.128.66.0F.W1 14 /r
VUNPCKLPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstC V/V AVX512VL
values from low quadwords of xmm2 and xmm3/m128/m64bcst subject to write mask k1.
EVEX.256.66.0F.W1 14 /r
VUNPCKLPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstC V/V AVX512VL
values from low quad words of ymm2 and 
ymm3/m256/m64bcst subject to write mask k1.
EVEX.512.66.0F.W1 14 /r
VUNPCKLPD zmm1 {k1}{z}, zmm2, 
values from low quad words of zmm2 and 
zmm3/m512/m64bcst subject to write mask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AUNPCKLPD—Unpack and Interleave Low Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-735Operation
VUNPCKLPD (EVEX Encoded Versions  When SRC2 is a Register)
IF VL >= 128
TMP_DEST[63:0] := SRC1[63:0]TMP_DEST[127:64] := SRC2[63:0]
TMP_DEST[191:128] := SRC1[191:128]TMP_DEST[255:192] := SRC2[191:128]
TMP_DEST[319:256] := SRC1[319:256]TMP_DEST[383:320] := SRC2[319:256]TMP_DEST[447:384] := SRC1[447:384]TMP_DEST[511:448] := SRC2[447:384]
FI;
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0UNPCKLPD—Unpack and Interleave Low Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-736 Vol. 2BVUNPCKLPD (EVEX Encoded Version When SRC2 is Memory)
FI;
TMP_DEST[63:0] := SRC1[63:0]TMP_DEST[127:64] := TMP_SRC2[63:0]
TMP_DEST[191:128] := SRC1[191:128]TMP_DEST[255:192] := TMP_SRC2[191:128]
TMP_DEST[319:256] := SRC1[319:256]TMP_DEST[383:320] := TMP_SRC2[319:256]TMP_DEST[447:384] := SRC1[447:384]TMP_DEST[511:448] := TMP_SRC2[447:384]
FI
FI;
VUNPCKLPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0]DEST[127:64] := SRC2[63:0]DEST[191:128] := SRC1[191:128]DEST[255:192] := SRC2[191:128]DEST[MAXVL-1:256] := 0
VUNPCKLPD (VEX.128 Encoded Version)
UNPCKLPD (128-bit Legacy SSE Version)
DEST[63:0] := SRC1[63:0]DEST[127:64] := SRC2[63:0]DEST[MAXVL-1:128] (Unmodified)UNPCKLPD—Unpack and Interleave Low Packed  Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-737Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKLPD __m512d _mm512_unpacklo_pd( __m512d a, __m512d b);

FI
FI;
VUNPCKLPD __m512d _mm512_mask_unpacklo_pd(__m 512d s, __mmask8 k, __m512d a, __m512d b);
VUNPCKLPD __m512d _mm512_maskz_unpacklo_ pd(__mmask8 k, __m512d a, __m512d b);
VUNPCKLPD __m256d _mm256_unpacklo_pd(__m256d a, __m256d b)VUNPCKLPD __m256d _mm256_mask_unpacklo_pd(__m 256d s, __mmask8 k, __m256d a, __m256d b);
VUNPCKLPD __m256d _mm256_maskz_unpacklo_ pd(__mmask8 k, __m256d a, __m256d b);
UNPCKLPD __m128d _mm_unpacklo_pd(__m128d a, __m128d b)VUNPCKLPD __m128d _mm_mask_unpacklo_pd(__m128 d s, __mmask8 k, __m128d a, __m128d b);
VUNPCKLPD __m128d _mm_maskz_unpacklo_pd( __mmask8 k, __m128d a, __m128d b);
None.
EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions.”UNPCKLPS—Unpack and Interleave Low Packed  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-738 Vol. 2BUNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values
Performs an interleaved unpack of the low single precision floating-point values from the first source operand and 
enforced.
Mode 
NP 0F 14 /r
UNPCKLPS xmm1, xmm2/m128A V/V SSE Unpacks and Interleaves single precision floating-point 
values from low quadword s of xmm1 and xmm2/m128.
VEX.128.0F.WIG 14 /r
VUNPCKLPS xmm1,xmm2, 
values from low quadword s of xmm2 and xmm3/m128.
VEX.256.0F.WIG 14 /r
VUNPCKLPS 
ymm1,ymm2,ymm3/m256B V/V AVX Unpacks and Interleaves single precision floating-point 
values from low quadwords of ymm2 and ymm3/m256.
EVEX.128.0F.W0 14 /r
VUNPCKLPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV / V A V X 5 1 2 V L
values from low quadwords of xmm2 and xmm3/mem and write result to xmm1 subject to write mask k1.
EVEX.256.0F.W0 14 /r
VUNPCKLPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV / V A V X 5 1 2 V L
values from low quadwords of ymm2 and ymm3/mem and write result to ymm1 su bject to write mask k1.
EVEX.512.0F.W0 14 /r
VUNPCKLPS zmm1 {k1}{z}, zmm2, 
values from low quadwords of zmm2 and 
zmm3/m512/m32bcst and write result to zmm1 subject to write mask k1.
CF u l l M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/AUNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-739EVEX.512 encoded version: The first source operand is  a ZMM register. The second source operand is a ZMM 
Operation
VUNPCKLPS (EVEX Encoded Version When SRC2 is a ZMM Register)
TMP_DEST[31:0] := SRC1[31:0]TMP_DEST[63:32] := SRC2[31:0]TMP_DEST[95:64] := SRC1[63:32]TMP_DEST[127:96] := SRC2[63:32]
TMP_DEST[159:128] := SRC1[159:128]TMP_DEST[191:160] := SRC2[159:128]TMP_DEST[223:192] := SRC1[191:160]TMP_DEST[255:224] := SRC2[191:160]
TMP_DEST[287:256] := SRC1[287:256]TMP_DEST[319:288] := SRC2[287:256]TMP_DEST[351:320] := SRC1[319:288]TMP_DEST[383:352] := SRC2[319:288]TMP_DEST[415:384] := SRC1[415:384]TMP_DEST[447:416] := SRC2[415:384]TMP_DEST[479:448] := SRC1[447:416]TMP_DEST[511:480] := SRC2[447:416]
FI;FOR j := 0 TO KL-1Figure 4-28.  VUNPCKLPS OperationDESTSRC1
Y0 Y1 Y2 Y3
X0 Y0 X1 Y1 X4 Y4 X5 Y5X4 X5 X6 X7
Y4 Y5 Y6 Y7UNPCKLPS—Unpack and Interleave Low Packed  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
4-740 Vol. 2Bi := j * 32
FI
FI;
VUNPCKLPS (EVEX Encoded Version When SRC2 is Memory)
i := j * 31IF (EVEX.b = 1)
FI;
ENDFOR;IF VL >= 128TMP_DEST[31:0] := SRC1[31:0]TMP_DEST[63:32] := TMP_SRC2[31:0]TMP_DEST[95:64] := SRC1[63:32]TMP_DEST[127:96] := TMP_SRC2[63:32]FI;IF VL >= 256
TMP_DEST[159:128] := SRC1[159:128]TMP_DEST[191:160] := TMP_SRC2[159:128]TMP_DEST[223:192] := SRC1[191:160]TMP_DEST[255:224] := TMP_SRC2[191:160]
TMP_DEST[287:256] := SRC1[287:256]TMP_DEST[319:288] := TMP_SRC2[287:256]TMP_DEST[351:320] := SRC1[319:288]TMP_DEST[383:352] := TMP_SRC2[319:288]TMP_DEST[415:384] := SRC1[415:384]TMP_DEST[447:416] := TMP_SRC2[415:384]TMP_DEST[479:448] := SRC1[447:416]TMP_DEST[511:480] := TMP_SRC2[447:416]
FIUNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, M-U
Vol. 2B 4-741FI;
UNPCKLPS (VEX.256 Encoded Version)
DEST[31:0] := SRC1[31:0]DEST[63:32] := SRC2[31:0]DEST[95:64] := SRC1[63:32]DEST[127:96] := SRC2[63:32]DEST[159:128] := SRC1[159:128]DEST[191:160] := SRC2[159:128]DEST[223:192] := SRC1[191:160]DEST[255:224] := SRC2[191:160]DEST[MAXVL-1:256] := 0
VUNPCKLPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0]DEST[63:32] := SRC2[31:0]DEST[95:64] := SRC1[63:32]DEST[127:96] := SRC2[63:32]DEST[MAXVL-1:128] := 0
UNPCKLPS (128-bit Legacy SSE Version)
DEST[31:0] := SRC1[31:0]DEST[63:32] := SRC2[31:0]DEST[95:64] := SRC1[63:32]DEST[127:96] := SRC2[63:32]DEST[MAXVL-1:128 ] (Unmodified)
VUNPCKLPS __m512 _mm512_unpacklo_ps(__m512 a, __m512 b);
VUNPCKLPS __m512 _mm512_mask_unpacklo_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);VUNPCKLPS __m512 _mm512_maskz_unpacklo_ ps(__mmask16 k, __m512 a, __m512 b);
VUNPCKLPS __m256 _mm256_unpacklo_ps (__m256 a, __m256 b);VUNPCKLPS __m256 _mm256_mask_unpacklo_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);VUNPCKLPS __m256 _mm256_maskz_unpacklo_ps(__mmask8 k, __m256 a, __m256 b);UNPCKLPS __m128 _mm_unpacklo_ps (__m128 a, __m128 b);VUNPCKLPS __m128 _mm_mask_unpacklo_ps(__m 128 s, __mmask8 k, __m128 a, __m128 b);
VUNPCKLPS __m128 _mm_maskz_unpacklo _ps(__mmask8 k, __m128 a, __m128 b);
None.
4-742 Vol. 2BVol. 2C 5-1CHAPTER 5
INSTRUCTION SET REFERENCE, V
5.1 TERNARY BIT VECTOR LOGIC TABLE
VPTERNLOGD/VPTERNLOGQ instructions operate on dword/ qword elements and take three bit vectors of the 
respective input data elements to form a set of 32/64 indi ces, where each 3-bit value provides an index into an 8-

None.
bit lookup table represented by the imm8 byte of the in struction. The 256 possible values of the imm8 byte is 
constructed as a 16x16 boolean logic table. The 16 rows of  the table uses the lower 4 bi ts of imm8 as row index. 
The 16 columns are referenced by imm8[7:4]. The 16 co lumns of the table are present in two halves, with 8 
columns shown in Table 5-11 for the column index valu e between 0:7, followed by Table 5-12 showing the 8 
columns corresponding to column index 8:15. This section presents the two-halves of the 256-entry table using a 
short-hand notation representing simple or compound b oolean logic expressions with three input bit source data. 
The three input bit source data will be denoted with the capital letters: A, B, C; where A represents a bit from the 
first source operand (also the destination operand), B and C represent a bit from the 2nd and 3rd source operands. 
Each map entry takes the form of a logic expression co nsisting of one of more component expressions. Each 
component expression consists of either a unary or binary  boolean operator and associated operands. Each binary 
boolean operator is expressed in lowercase letters, and op erands concatenated after the logic operator. The unary 
operator ‘not’ is expressed using ‘!’. Additionally, the co nditional expression “A?B:C” expresses a result returning B 
if A is set, returning C otherwise.
A binary boolean operator is followed by two operands, e.g. , andAB. For a compound binary expression that contain 
commutative components and comprising the same logic operator, the 2nd logic operator is omitted and three 
operands can be concatenated in sequence, e.g., andA BC. When the 2nd operand of the first binary boolean 
expression comes from the result of another boolean expr ession, the 2nd boolean expression is concatenated after 
the uppercase operand of the first logic expression, e.g. , norBnandAC. When the result is independent of an 
operand, that operand is omitted in th e logic expression, e.g., zeros or norCB.
The 3-input expression “majorABC” returns 0 if two or more input bits are 0, returns 1 if two or more input bits are 
1. The 3-input expression “minorABC” returns 1 if two or mo re input bits are 0, returns 0 if two or more input bits 
are 1.
The building-block bit logic functions used in Table 5-11 and Table 5-12 include:
•Constants: TRUE (1), FALSE (0);
•Unary function: Not (!);
•Binary functions: and, nand, or, nor, xor, xnor;
•Conditional function: Select (?:);
•Tertiary functions: major, minor.INSTRUCTION SET REFERENCE, V
5-2 Vol. 2C:
Table 5-12 shows the half of 256-entry map co rresponding to column index values 8:15.Table 5-11. Lower 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations
Imm [7:4]
[3:0] 0H 1H 2H 3H 4H 5H 6H 7H
00H FALSE andAnorBC norBnandAC andA!B no rCnandBA andA!C andAxorBC andAnandBC
01H norABC norCB norBxorAC A?!B:norBC norCxorBA A?!C:norBC A?xorBC:norB
CA?nandBC:no
rBC
02H andCnorBA norBxnorAC andC!B norBnorAC C?norBA:and
BAC?norBA:A C?!B:andBA C?!B:A
03H norBA norBandAC C?!B:norBA !B C?norBA:xnor
BAA?!C:!B A?xorBC:!B A?nandBC:!B
04H andBnorAC norCxnorBA B?norAC:and
ACB?norAC:A andB!C norCn orBA B?!C:andAC B?!C:A
05H norCA norCandBA B?norAC:xnor
ACA?!B:!C B?!C:norAC !C A?xorBC:!C A?nandBC:!C
06H norAxnorBC A?norBC:xorB
CB?norAC:C xorBorAC C?norBA :B xorCorBA xorCB B?!C:orAC
07H norAandBC minorABC C?!B:!A nandBo rAC B?!C:!A nandCorBA A?xorBC:nan
dBCnandCB
08H norAnandBC A?norBC:and
BCandCxorBA A?!B:andBC andBxor AC A?!C:andBC A?xorBC:and
BCxorAandBC
09H norAxorBC A?norBC:xnor
BCC?xorBA:norB
AA?!B:xnorBC B?xorAC:norA
CA?!C:xnorBC xnorABC A?nandBC:xn
orBC
0AH andC!A A?norBC:C andCnandBA A?!B:C C?!A:andBA xorCA xorCandBA A?nandBC:C
0BH C?!A:norBA C?!A:!B C?nandBA:no
rBAC?nandBA:!B B?xorAC:!A B?xorAC:nan
dACC?nandBA:xn
orBAnandBxnorAC
0CH andB!A A?norBC:B B?!A:andAC xorBA a ndBnandAC A?!C:B xorBandAC A?nandBC:B
0DH B?!A:norAC B?!A:!C B?!A:xnorAC C?xorBA:nan
dBAB?nandAC:no
rACB?nandAC:!C B?nandAC:xn
orACnandCxnorBA
0EH norAnorBC xorAorBC B?!A:C A?!B:orBC C ?!A:B A?!C:orBC B?nandAC:C A?nandBC:or
BC
0FH !A nandAorBC C?nandBA:!A nandBA B?n andAC:!A nandCA nandAxnorBC nandABCINSTRUCTION SET REFERENCE, V
Vol. 2C 5-3:
Table 5-11 and Table 5-12 translate each of the possible value of the imm8 byte to a Boolean expression. These 
tables can also be used by software to translate Boolean expressions to numerical constants to form the imm8 
value needed to construct the VPTERNLO G syntax. There is a unique set of th ree byte constants (F0H, CCH, AAH) 
that can be used for this purpose as input operands in conjunction with the Boolean expressions defined in those 
tables. The reverse mapping can be expressed as:
Result_imm8 = Table_Lookup_Entry( 0F0H, 0CCH, 0AAH)Table_Lookup_Entry is the Boolean expressi on defined in Table 5-11 and Table 5-12.Table 5-12. Upper 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations
Imm [7:4]
[3:0] 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
00H andABC andAxnorBC andCA B?an dAC:A andBA C?andBA:A andAorBC A
01H A?andBC:nor
BCB?andAC:!C A?C:norBC C?A:!B A?B:norBC B?A:!C xnorAorBC orAnorBC
02H andCxnorBA B?andAC:xor
ACB?andAC:C B?andAC:orA
CC?xnorBA:an
dBAB?A:xorAC B?A:C B?A:orAC
03H A?andBC:!B xnorBandAC A?C:!B nandBnandA
CxnorBA B?A:nandAC A?orBC:!B orA!B
04H andBxnorAC C?andBA:xor
BAB?xnorAC:an
dACB?xnorAC:A C?andBA:B C?andBA:orB
AC?A:B C?A:orBA
05H A?andBC:!C xnorCandBA xnorCA C?A:nandBA A?B:!C nandCnandB
AA?orBC:!C orA!C
06H A?andBC:xor
BCxorABC A?C:xorBC B?xnorAC:orA
CA?B:xorBC C?xnorBA:orB
AA?orBC:xorBC orAxorBC
07H xnorAandBC A?xnorBC:na
ndBCA?C:nandBC nandBxor AC A?B:nandBC nandCx orBA A?orBCnandB
CorAnandBC
08H andCB A?xnorBC:an
dBCandCorAB B?C:A andBorAC C ?B:A majorABC orAandBC
09H B?C:norAC xnorCB xnorCorBA C?orBA:!B xnorBorAC B?orAC:!C A?orBC:xnorB
CorAxnorBC
0AH A?andBC:C A?xnorBC:C C B?C:orAC A?B:C B?orAC:xorAC orCandBA orCA
0BH B?C:!A B?C:nandAC orCnorBA orC!B B?orAC:!A B?orAC:nand
ACorCxnorBA nandBnorAC
0CH A?andBC:B A?xnorBC:B A?C:B C?orBA:xorBA B C?B:orBA orBandAC orBA
0DH C?B!A C?B:nandBA C?orBA:!A C?orBA:nand
BAorBnorAC orB!C orBxnorAC nandCnorBA
0EH A?andBC:orB
CA?xnorBC:orB
CA?C:orBC orCxorBA A?B:orBC orBxorAC orCB orABC
0FH nandAnandB
CnandAxorBC orC!A orCnandBA or B!A orBnandAC nandAnorBC TRUEINSTRUCTION SET REFERENCE, V
5-4 Vol. 2C5.2 INSTRUCTIONS (V)
Chapter 5 continues an alphabetical discussion of Intel® 64 and IA-32 instructions (V). See also: Chapter 3, 
2A; Chapter 4, “Instruction Set Reference, M-U‚” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2B; and Chapter 6, “Instruction Set Reference, W-Z,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 2D.VADDPH—Add Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-5VADDPH—Add Packed FP16 Values
This instruction adds packed FP16 values from source op erands and stores the packed FP16 result in the destina-
tion operand. The destination elements are updated according to the writemask.
Operation
VADDPH (EVEX Encoded Versions) When SRC2 Operand is a Register 
VL = 128, 256 or 512KL := VL/16IF (VL = 512) AND (EVEX.b = 1): 
SET_RM(EVEX.RC)
ELSE
SET_RM(MXCSR.RC)
DEST.fp16[j] := SRC1.fp16[j] + SRC2.fp16[j]
ELSEIF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
VADDPH (EVEX Encoded Versions) When SRC2 Operand is a Memory Source
VL = 128, 256 or 512KL := VL/16FOR j := 0 TO KL-1:
IF EVEX.b = 1:
DEST.fp16[j] := SRC1.fp16[j] + SRC2.fp16[0]
ELSE:
DEST[MAXVL-1:VL] := 0Opcode/
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W0 58 /r
VADDPH xmm1{k1}{z}, xmm2, 
xmm3/m128/m16bcstA V/V AVX512-FP16 
AVX512VLAdd packed FP16 value from xmm3/m128/
m16bcst to xmm2, and store result in xmm1 
EVEX.256.NP.MAP5.W0 58 /r
VADDPH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstA V/V AVX512-FP16 
AVX512VLAdd packed FP16 va lue from ymm3/m256/
m16bcst to ymm2, and st ore result in ymm1 
EVEX.512.NP.MAP5.W0 58 /r
VADDPH zmm1{k1}{z}, zmm2, zmm3/
m512/m16bcst {er}A V/V AVX512-FP16 Add packed FP16 value from zmm3/m512/
m16bcst to zmm2, and store result in zmm1 
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVADDPH—Add Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-6 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VADDPH __m128h _mm_add_ph (__m128h a, __m128h b);
VADDPH __m128h _mm_mask_add_ph (__m128h sr c, __mmask8 k, __m128h a, __m128h b);
VADDPH __m128h _mm_maskz_add_ph (__m mask8 k, __m128h a, __m128h b);

VADDPH __m256h _mm256_add_ph (__m256h a, __m256h b);VADDPH __m256h _mm256_mask_add_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);VADDPH __m256h _mm256_maskz_add_ph (__mmask16 k, __m256h a, __m256h b);VADDPH __m512h _mm512_add_ph (__m512h a, __m512h b);VADDPH __m512h _mm512_add_ph (__m512h a, __m512h b);VADDPH __m512h _mm512_mask_add_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);VADDPH __m512h _mm512_maskz_add_ph (__mmask32 k, __m512h a, __m512h b);VADDPH __m512h _mm512_add_round_ph (__m 512h a, __m512h b, int rounding);
VADDPH __m512h _mm512_mask_add_round_p h (__m512h src, __mmask32 k, __m5 12h a, __m512h b, int rounding);
VADDPH __m512h _mm512_maskz_add_round_ph (__mmask 32 k, __m512h a, __m512h b, int rounding);
Invalid, Underflow, Overflow, Precision, Denormal.
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VADDSH—Add Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-7VADDSH—Add Scalar FP16 Values
This instruction adds the low FP16 value from the source operands and stores the FP16 result in the destination 
operand.
Bits 127:16 of the destination operand are copied from th e corresponding bits of the first source operand. Bits 
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according 
to the writemask.
Operation
VADDSH (EVEX Encoded Versions) 
IF EVEX.b = 1 and SRC2 is a register: 
ELSE
IF k1[0] OR *no writemask*:
DEST.fp16[0] := SRC1.fp16[0] + SRC2.fp16[0]
DEST.fp16[0] := 0
// else dest.fp16[0]  remains unchanged
DEST[127:16] := SRC1[127:16] DEST[MAXVL-1:128] := 0
VADDSH __m128h _mm_add_round_sh (__m 128h a, __m128h b, int rounding);
VADDSH ___m128h _mm_mask_a dd_round_sh (__m128h src,  __mmask8 k, __m128h a, __m128h b, int rounding);
VADDSH ___m128h _mm_maskz_add_round_sh (__mma sk8 k, __m128h a, __m128h b, int rounding);
VADDSH ___m128h _mm_add_sh (__m128h a, __m128h b);VADDSH ___m128h _mm_mask_add_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VADDSH ___m128h _mm_maskz_add_sh ( __mmask8 k, __m128h a, __m128h b);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 58 /r
VADDSH xmm1{k1}{z}, xmm2, 
xmm3/m16 {er}A V/V AVX512-FP16 Add the low FP16 value from xmm3/m16 to 
xmm2, and store the result in xmm1 subject to 
writemask k1. Bits 127:16 of xmm2 are copied 
to xmm1[127:16].
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVALIGND/VALIGNQ—Align Doubleword/Quadword VectorsINSTRUCTION SET REFERENCE, V
5-8 Vol. 2CVALIGND/VALIGNQ—Align Doub leword/Quadword Vectors
Concatenates and shifts right doubleword/quadword elemen ts of the first source operand (the second operand) 
and the second source operand (the third operand) into a 1024/512/256-bit intermediate vector. The low 
512/256/128-bit of the intermediate vector is written to  the destination operand (the first operand) using the 
writemask k1. The destination and first source operands are ZMM/YMM/XMM registers. The second source operand 
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted 
from a 32/64-bit memory location.
This instruction is writemasked, so only those elements wi th the corresponding bit set in vector mask register k1 
are computed and stored into zmm1. Elements in zmm1 with  the corresponding bit clear in k1 retain their previous 
values (merging-masking) or are set to 0 (zeroing-masking).Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F3A.W0 03 /r ib
VALIGND xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcst, imm8AV / V A V X 5 1 2 V L
AVX512FShift right and merge vectors xmm2 and 
xmm3/m128/m32bcst with double-word granularity 
using imm8 as number of el ements to shift, and store 
the final result in xmm1, under writemask.
EVEX.128.66.0F3A.W1 03 /r ib
VALIGNQ xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcst, imm8AV / V A V X 5 1 2 V L
xmm3/m128/m64bcst with quad-word granularity 
EVEX.256.66.0F3A.W0 03 /r ib
VALIGND ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcst, imm8AV / V A V X 5 1 2 V L
AVX512FShift right and merge vectors ymm2 and 
ymm3/m256/m32bcst with double-word granularity 
the final result in ymm1, under writemask.
EVEX.256.66.0F3A.W1 03 /r ib
VALIGNQ ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcst, imm8AV / V A V X 5 1 2 V L
ymm3/m256/m64bcst with quad-word granularity 
EVEX.512.66.0F3A.W0 03 /r ib
VALIGND zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst, imm8A V/V AVX512F Shift right and merge vectors zmm2 and 
zmm3/m512/m32bcst with double-word granularity 
the final result in zmm1, under writemask.
EVEX.512.66.0F3A.W1 03 /r ib
VALIGNQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst, imm8A V/V AVX512F Shift right and merge vectors zmm2 and 
zmm3/m512/m64bcst with quad-word granularity 
A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVALIGND/VALIGNQ—Align Doubleword/Quadword VectorsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-9Operation
VALIGND (EVEX Encoded Versions) 
IF (SRC2 *is memory*) (AND EVEX.b = 1)
THEN 
i := j * 32src[i+31:i] := SRC2[31:0]
ENDFOR;
ELSE src := SRC2
FI; Concatenate sourcestmp[VL-1:0] := src[VL-1:0]tmp[2VL-1:VL] := SRC1[VL-1:0]
; Shift right doubleword elements
IF VL = 128
THEN SHIFT = imm8[1:0]ELSE 
IF VL = 256
THEN SHIFT = imm8[2:0]ELSE SHIFT = imm8[3:0]
FI
FI;tmp[2VL-1:0] := tmp[2VL-1:0] >> (32*SHIFT); Apply writemaskFOR j := 0 TO KL-1
THEN DEST[i+31:i] := tmp[i+31:i]ELSE 
FI
FI;
VALIGNQ (EVEX Encoded Versions) 
(KL, VL) = (2, 128), (4, 256),(8, 512)IF (SRC2 *is memory*) (AND EVEX.b = 1)
THEN 
i := j * 64src[i+63:i] := SRC2[63:0]
ENDFOR;
FI; Concatenate sourcestmp[VL-1:0] := src[VL-1:0]tmp[2VL-1:VL] := SRC1[VL-1:0]; Shift right quadword elementsVALIGND/VALIGNQ—Align Doubleword/Quadword VectorsINSTRUCTION SET REFERENCE, V
5-10 Vol. 2CIF VL = 128
THEN SHIFT = imm8[0]ELSE 
IF VL = 256
THEN SHIFT = imm8[1:0]ELSE SHIFT = imm8[2:0]
FI
FI;tmp[2VL-1:0] := tmp[2VL-1:0] >> (64*SHIFT); Apply writemaskFOR j := 0 TO KL-1
THEN DEST[i+63:i] := tmp[i+63:i]ELSE 
FI
FI;
VALIGND __m512i _mm512_alignr_epi32( __m512i a, __m512i b, int cnt);
VALIGND __m512i _mm512_mask_alignr_epi32(__m512i s,  __mmask16 k, __m512i a,  __m512i b, int cnt);
VALIGND __m512i _mm512_maskz_alignr_epi32( __m mask16 k, __m512i a, __m512i b, int cnt);
VALIGND __m256i _mm256_mask_alignr_epi32(__m256i s,  __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGND __m256i _mm256_maskz_alignr_epi32( __m mask8 k, __m256i a, __m256i b, int cnt);
VALIGND __m128i _mm_mask_alignr_epi32(__m128i s,  __mmask8 k, __m128i a, __m128i b, int cnt);
VALIGND __m128i _mm_maskz_alignr_epi32( __mma sk8 k, __m128i a, __m128i b, int cnt);
VALIGNQ __m512i _mm512_alignr_epi64(  __m512i a, __m512i b, int cnt);
VALIGNQ __m512i _mm512_mask_alignr_epi64(__m512i s, __mmask8 k, __m512i a,  __m512i b, int cnt);
VALIGNQ __m512i _mm512_maskz_alignr_epi64( __mmask8 k, __m512i a, __m512i b, int cnt);
VALIGNQ __m256i _mm256_mask_alignr_epi64(__m256i s, __mmask8 k, __m256i a,  __m256i b, int cnt);
VALIGNQ __m256i _mm256_maskz_alignr_epi64( __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGNQ __m128i _mm_mask_alignr_epi64(__m128i s,  __mmask8 k, __m128i a, __m128i b, int cnt);
VALIGNQ __m128i _mm_maskz_alignr_epi64( __mma sk8 k, __m128i a, __m128i b, int cnt);
See Table 2-50, “Type E4NF Class Exception Conditions.”VBLENDMPD/VBLENDMPS—Blend Float64/Floa t32 Vectors Using an OpMask ControlINSTRUCTION SET REFERENCE, V
Vol. 2C 5-11VBLENDMPD/VBLENDMPS— Blend Float64/Float32 Vector s Using an OpMask Control

Performs an element-by-element blending between float 64/float32 elements in the first source operand (the 
second operand) with the elements in the second source operand (the third operand) using an opmask register as 
select control. The blended result is written to the destination register.
The destination and first source operands are ZMM/YMM/ XMM registers. The second source operand can be a 
bit memory location.
The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element 
selector: every element of the destination is conditionally selected between first source or second source using the 
value of the related mask bit (0 for first so urce operand, 1 for second source operand).
If EVEX.z is set, the elements with  corresponding mask bit value of 0 in the destination operand are zeroed.
Operation
VBLENDMPD (EVEX Encoded Versions)
i := j * 64IF k1[j] OR *no controlmask*
THEN
THEN
DEST[i+63:i] := SRC2[63:0]
ELSE 
DEST[i+63:i] := SRC2[i+63:i]Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W1 65 /r
VBLENDMPD xmm1 {k1}{z}, 
xmm2, xmm3/m128/m64bcstA V/V AVX512VL
AVX512FBlend double precision vector xmm2 and double precision 
vector xmm3/m128/m64bcst and store the result in xmm1, 
under control mask.
EVEX.256.66.0F38.W1 65 /r
VBLENDMPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstA V/V AVX512VL
AVX512FBlend double precision vector ymm2 and double precision 
vector ymm3/m256/m64bcst and store the result in ymm1, under control mask.
EVEX.512.66.0F38.W1 65 /r
VBLENDMPD zmm1 {k1}{z}, 
zmm2, zmm3/m512/m64bcstA V/V AVX512F Blend double precision vector zmm2 and double precision 
vector zmm3/m512/m64bcst and store the result in zmm1, 
EVEX.128.66.0F38.W0 65 /r
VBLENDMPS xmm1 {k1}{z}, 
xmm2, xmm3/m128/m32bcstA V/V AVX512VL
AVX512FBlend single precision vector xmm2 and single precision 
vector xmm3/m128/m32bcst and store the result in xmm1, 
EVEX.256.66.0F38.W0 65 /r
VBLENDMPS ymm1 {k1}{z}, 
ymm2, ymm3/m256/m32bcstA V/V AVX512VL
AVX512FBlend single precision vector ymm2 and single precision 
vector ymm3/m256/m32bcst and store the result in ymm1, 
EVEX.512.66.0F38.W0 65 /r
VBLENDMPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstA V/V AVX512F Blend single precision vector zmm2 and single precision 
vector zmm3/m512/m32bcst using k1 as select control and store the result in zmm1.
AF u l l M o d R M : r e g  ( w )E V E X . vvvv (r) ModRM:r/m (r) N/AVBLENDMPD/VBLENDMPS—Blend Float64/Floa t32 Vectors Using an OpMask ControlINSTRUCTION SET REFERENCE, V
5-12 Vol. 2CFI;
ELSE 
THEN DEST[i+63:i] := SRC1[i+63:i]ELSE ; zeroing-masking
FI;
FI;
VBLENDMPS (EVEX Encoded Versions)
i := j * 32IF k1[j] OR *no controlmask*
THEN
THEN
DEST[i+31:i] := SRC2[31:0]
ELSE 
DEST[i+31:i] := SRC2[i+31:i]
FI;
ELSE 
THEN DEST[i+31:i] := SRC1[i+31:i]ELSE ; zeroing-masking
FI;
FI;
VBLENDMPD __m512d _mm512_mask_blend_pd( __mmask8 k, __m512d a, __m512d b);
VBLENDMPD __m256d _mm256_mask_blend_pd( __mmask8 k, __m256d a, __m256d b);
VBLENDMPD __m128d _mm_mask_blend_pd(__mmask8 k, __m128d a, __m128d b);VBLENDMPS __m512 _mm512_mask_blend_ps(__mmask16 k, __m512 a, __m512 b);VBLENDMPS __m256 _mm256_mask_blend_ps(__mmask8 k, __m256 a, __m256 b);VBLENDMPS __m128 _mm_mask_blend_ps(__mmask8 k, __m128 a, __m128 b);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VBROADCAST—Load with Broadcast Floating-Point DataINSTRUCTION SET REFERENCE, V
Vol. 2C 5-13VBROADCAST—Load with Broa dcast Floating-Point Data
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W0 18 /r
VBROADCASTSS xmm1, m32A V/V AVX Broadcast single precision floating-point element in 
mem to four locations in xmm1.
VEX.256.66.0F38.W0 18 /r
VBROADCASTSS ymm1, m32A V/V AVX Broadcast single precision floating-point element in 
mem to eight loca tions in ymm1.
VEX.256.66.0F38.W0 19 /r
VBROADCASTSD ymm1, m64A V/V AVX Broadcast double precision floating-point element in 
mem to four locations in ymm1.
VEX.256.66.0F38.W0 1A /r
VBROADCASTF128 ymm1, m128A V/V AVX Broadcast 128 bits of fl oating-point data in mem to 
low and high 128-bits in ymm1.
VEX.128.66.0F38.W0 18/r
VBROADCASTSS xmm1, xmm2A V/V AVX2 Broadcast th e low single precision floating-point 
element in the source oper and to four locations in 
xmm1.
VBROADCASTSS ymm1, xmm2A V/V AVX2 Broadcast low single precision floating-point element 
in the source operand to eight location s in ymm1.
VBROADCASTSD ymm1, xmm2A V/V AVX2 Broadcast low double precision floating-point element 
in the source operand to four locations in ymm1.
EVEX.256.66.0F38.W1 19 /r
VBROADCASTSD ymm1 {k1}{z}, 
AVX512FBroadcast low double precision floating-point element 
in xmm2/m64 to four locations in ymm1 using 
EVEX.512.66.0F38.W1 19 /r
VBROADCASTSD zmm1 {k1}{z}, xmm2/m64B V/V AVX512F Broadcast low double precision floating-point element 
in xmm2/m64 to eight lo cations in zmm1 using 
EVEX.256.66.0F38.W0 19 /r
VBROADCASTF32X2 ymm1 {k1}{z}, 
AVX512DQBroadcast two single precision floating-point elements 
in xmm2/m64 to locations in ymm1 using writemask 
k1.
EVEX.512.66.0F38.W0 19 /r
VBROADCASTF32X2 zmm1 {k1}{z}, 
xmm2/m64C V/V AVX512DQ Broadcast two single precision floating-point elements 
in xmm2/m64 to locations in zmm1 using writemask 
k1.
EVEX.128.66.0F38.W0 18 /r
VBROADCASTSS xmm1 {k1}{z}, xmm2/m32BV / V A V X 5 1 2 V L
AVX512FBroadcast low single precision floating-point element 
in xmm2/m32 to all locations in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 18 /r
VBROADCASTSS ymm1 {k1}{z}, 
xmm2/m32BV / V A V X 5 1 2 V L
in xmm2/m32 to all locations in ymm1 using 
EVEX.512.66.0F38.W0 18 /r
VBROADCASTSS zmm1 {k1}{z}, 
xmm2/m32B V/V AVX512F Broadcast low single precision floating-point element 
in xmm2/m32 to all loca tions in zmm1 using 
EVEX.256.66.0F38.W0 1A /r
VBROADCASTF32X4 ymm1 {k1}{z}, m128DV / V A V X 5 1 2 V L
AVX512FBroadcast 128 bits of 4 single precision floating-point 
data in mem to locations in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 1A /r
VBROADCASTF32X4 zmm1 {k1}{z}, 
m128D V/V AVX512F Broadcast 128 bits of 4 single precision floating-point 
data in mem to locations in  zmm1 using writemask k1.
EVEX.256.66.0F38.W1 1A /r
VBROADCASTF64X2 ymm1 {k1}{z}, 
m128CV / V A V X 5 1 2 V L
AVX512DQBroadcast 128 bits of 2 double precision floating-point 
data in mem to locations in ymm1 using writemask k1.VBROADCAST—Load with Broadcast Floating-Point DataINSTRUCTION SET REFERENCE, V
5-14 Vol. 2CInstruction Operand Encoding
VBROADCASTSD/VBROADCASTSS/VBROADCASTF128 load floati ng-point values as one tuple from the source 
operand (second operand) in memory and broadcast to all elements of the destination operand (first operand). 
VEX256-encoded versions: The destination operand is a YMM re gister. The source operand is either a 32-bit, 64-bit, 
or 128-bit memory location. Register source encodings ar e reserved and will #UD. Bits (MAXVL-1:256) of the desti-
EVEX-encoded versions: The destination operand is a ZMM/YMM/XMM register and updated according to the 
writemask k1. The source operand is either a 32-bit, 64 -bit memory location or the low doubleword/quadword 
element of an XMM register. 
VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF 64X2/VBROADCASTF32X8/VBROADCASTF64X4 load 
floating-point values as tuples from the source operand (t he second operand) in memory or register and broadcast 
to all elements of the destination operand (the first operand). The destination operand is a YMM/ZMM register 
updated according to the writemask k1. The source operand is either a register or 64-bit/128-bit/256-bit memory 
location.
VBROADCASTSD and VBROADCASTF128,F32x4 and F64x2 ar e only supported as 256-bit and 512-bit wide 
versions and up. VBROADCASTSS is supported in 128-bit,  256-bit and 512-bit wide versions. F32x8 and F64x4 are 
only supported as 512-bit wide versions.
VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF32X8 have 32-bit granularity. VBROADCASTF64X2 and 
VBROADCASTF64X4 have 64-bit granularity.

location.
VBROADCASTF64X4 have 64-bit granularity. 
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.If VBROADCASTSD or VBROADCASTF128 is encoded with VE X.L= 0, an attempt to execute the instruction encoded 
with VEX.L= 0 will cause an #UD exception.EVEX.512.66.0F38.W1 1A /r
VBROADCASTF64X2 zmm1 {k1}{z}, 
m128C V/V AVX512DQ Broadcast 128 bits of 2 double precision floating-point 
EVEX.512.66.0F38.W0 1B /r
VBROADCASTF32X8 zmm1 {k1}{z}, m256E V/V AVX512DQ Broadcast 256 bits of 8 single precision floating-point 
EVEX.512.66.0F38.W1 1B /r
VBROADCASTF64X4 zmm1 {k1}{z}, 
m256D V/V AVX512F Broadcast 256 bits of 4 double precision floating-point 
B Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
C Tuple2 ModRM:reg (w) ModRM:r/m (r) N/A N/A
D Tuple4 ModRM:reg (w) ModRM:r/m (r) N/A N/A
E Tuple8 ModRM:reg (w) ModRM:r/m (r) N/A N/AOpcode/
En64/32 
Bit Mode 
Feature 
FlagDescriptionVBROADCAST—Load with Broadcast Floating-Point DataINSTRUCTION SET REFERENCE, V
Vol. 2C 5-15Figure 5-1.  VBROADCASTSS Oper ation (VEX.256 encoded version)
Figure 5-2.  VBROADCASTSS Op eration (VEX.128-bit version)
Figure 5-3.  VBROADCASTSD Operation (VEX.256-bit version)
Figure 5-4.  VBROADCASTF128 Operation (VEX.256-bit version)DESTm32 X0
X0 X0 X0 X0 X0 X0 X0 X0
DESTm32 X0
X0 X0 X0 0 X0 0 0 0
DESTm64 X0
X0 X0 X0 X0
DESTm128 X0
X0 X0VBROADCAST—Load with Broadcast Floating-Point DataINSTRUCTION SET REFERENCE, V
5-16 Vol. 2COperation
VBROADCASTSS (128-bit Version VEX and Legacy)
temp := SRC[31:0]DEST[31:0] := tempDEST[63:32] := tempDEST[95:64] := tempDEST[127:96] := tempDEST[MAXVL-1:128] := 0
VBROADCASTSS (VEX.256 Encoded Version)
temp := SRC[31:0]DEST[31:0] := tempDEST[63:32] := tempDEST[95:64] := tempDEST[127:96] := tempDEST[159:128] := tempDEST[191:160] := tempDEST[223:192] := tempDEST[255:224] := tempDEST[MAXVL-1:256] := 0
VBROADCASTSS (EVEX Encoded Versions)
(KL, VL) (4, 128), (8 , 256),= (16, 512)
THEN DEST[i+31:i] := SRC[31:0]ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0Figure 5-5.  VBROADCASTF64 X4 Operation (512-bit vers ion with writemask all 1s)DESTm256 X0
Vol. 2C 5-17VBROADCASTSD (VEX.256 Encoded Version)
temp := SRC[63:0]DEST[63:0] := tempDEST[127:64] := tempDEST[191:128] := tempDEST[255:192] := tempDEST[MAXVL-1:256] := 0
VBROADCASTSD (EVEX Encoded Versions)
(KL, VL) = (4, 256), (8, 512)FOR j := 0 TO KL-1
THEN DEST[i+63:i] := SRC[63:0]ELSE 
FI
FI;
VBROADCASTF32x2 (EVEX Encoded Versions)
(KL, VL) = (8, 256), (16, 512)FOR j := 0 TO KL-1
i := j * 32n := (j mod 2) * 32IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SRC[n+31:n]ELSE 
FI
FI;
VBROADCASTF128 (VEX.256 Encoded Version)
temp := SRC[127:0]DEST[127:0] := tempDEST[255:128] := tempDEST[MAXVL-1:256] := 0VBROADCAST—Load with Broadcast Floating-Point DataINSTRUCTION SET REFERENCE, V
5-18 Vol. 2CVBROADCASTF32X4 (EVEX Encoded Versions)
i := j* 32n := (j modulo 4) * 32IF k1[j] OR *no writemask*
FI
FI;
VBROADCASTF64X2 (EVEX Encoded Versions)
i := j * 64n := (j modulo 2) * 64IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := SRC[n+63:n]ELSE 
FI
FI;
ENDFOR;
VBROADCASTF32X8 (EVEX.U1.512 Encoded Version)
i := j * 32n := (j modulo 8) * 32IF k1[j] OR *no writemask*
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VBROADCAST—Load with Broadcast Floating-Point DataINSTRUCTION SET REFERENCE, V
Vol. 2C 5-19VBROADCASTF64X4 (EVEX.512 Encoded Version)
i := j * 64n := (j modulo 4) * 64IF k1[j] OR *no writemask*
FI
FI;
VBROADCASTF32x2 __m512 _mm512_broadcast_f32x2( __m128 a);
VBROADCASTF32x2 __m512 _mm512_mask_broadcas t_f32x2(__m512 s, __mmask16 k, __m128 a);
VBROADCASTF32x2 __m512 _mm512_maskz_broadcast_f32x2( __mmask16 k, __m128 a);VBROADCASTF32x2 __m256 _mm256_broadcast_f32x2( __m128 a);VBROADCASTF32x2 __m256 _mm256_mask_broadcas t_f32x2(__m256 s, __mmask8 k, __m128 a);
VBROADCASTF32x2 __m256 _mm256_maskz_bro adcast_f32x2( __mmask8 k, __m128 a);
VBROADCASTF32x4 __m512 _mm512_broadcast_f32x4( __m128 a);VBROADCASTF32x4 __m512 _mm512_mask_broadcas t_f32x4(__m512 s, __mmask16 k, __m128 a);
VBROADCASTF32x4 __m512 _mm512_maskz_broadcast_f32x4( __mmask16 k, __m128 a);VBROADCASTF32x4 __m256 _mm256_broadcast_f32x4( __m128 a);VBROADCASTF32x4 __m256 _mm256_mask_broadcas t_f32x4(__m256 s, __mmask8 k, __m128 a);
VBROADCASTF32x4 __m256 _mm256_maskz_bro adcast_f32x4( __mmask8 k, __m128 a);
VBROADCASTF32x8 __m512 _mm512_broadcast_f32x8( __m256 a);VBROADCASTF32x8 __m512 _mm512_mask_broadcas t_f32x8(__m512 s, __mmask16 k, __m256 a);
VBROADCASTF32x8 __m512 _mm512_maskz_broadcast_f32x8( __mmask16 k, __m256 a);VBROADCASTF64x2 __m512d _mm512_broadcast_f64x2( __m128d a);VBROADCASTF64x2 __m512d _mm512_mask_broadcast_f 64x2(__m512d s, __mmask8 k, __m128d a);
VBROADCASTF64x2 __m512d _mm512_maskz_broadcast_f64x2( __mmask8 k, __m128d a);VBROADCASTF64x2 __m256d _mm256_broadcast_f64x2( __m128d a);VBROADCASTF64x2 __m256d _mm256_mask_broadcast_f 64x2(__m256d s, __mmask8 k, __m128d a);
VBROADCASTF64x2 __m256d _mm256_maskz_broadcast_f64x2( __mmask8 k, __m128d a);VBROADCASTF64x4 __m512d _mm512_broadcast_f64x4( __m256d a);VBROADCASTF64x4 __m512d _mm512_mask_broadcast_f 64x4(__m512d s, __mmask8 k, __m256d a);
VBROADCASTF64x4 __m512d _mm512_maskz_broadcast_f64x4( __mmask8 k, __m256d a);VBROADCASTSD __m512d _mm512_broadcastsd_pd( __m128d a); VBROADCASTSD __m512d _mm512_mask_broadcasts d_pd(__m512d s, __mmask8 k, __m128d a); 
VBROADCASTSD __m512d _mm512_maskz_bro adcastsd_pd(__mmask8 k, __m128d a); 
VBROADCASTSD __m256d _mm256_broadcastsd_pd(__m128d a);VBROADCASTSD __m256d _mm256_mask_broadcasts d_pd(__m256d s, __mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_maskz_bro adcastsd_pd( __mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256 _broadcast_sd(double *a);
VBROADCASTSS __m512 _mm512_broadcastss_ps( __m128 a); VBROADCASTSS __m512 _mm512_mask_broadcastss_ps(__m512 s, __mmask16 k, __m128 a); VBROADCASTSS __m512 _mm512_maskz_broad castss_ps( __mmask16 k, __m128 a); 
VBROADCASTSS __m256 _mm256_broadcastss_ps(__m128 a);VBROADCASTSS __m256 _mm256_mask_broadcas tss_ps(__m256 s, __mmask8 k, __m128 a);
VBROADCASTSS __m256 _mm256_maskz_bro adcastss_ps( __mmask8 k, __m128 a);VBROADCAST—Load with Broadcast Floating-Point DataINSTRUCTION SET REFERENCE, V
5-20 Vol. 2CVBROADCASTSS __m128 _mm_br oadcastss_ps(__m128 a);
VBROADCASTSS __m128 _mm_mask_broadcast ss_ps(__m128 s, __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_maskz_broa dcastss_ps( __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_broadcast_ss(float *a);VBROADCASTSS __m256 _mm256_broadcast_ss(float *a);VBROADCASTF128 __m256 _mm256_broadcast_ps(__m128 * a);VBROADCASTF128 __m256d _mm256_broadcast_pd(__m128d * a);
VEX-encoded instructions, see Table 2-23, “Type 6 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-53, “Type E6 Class Exception Conditions.”
#UD If VEX.L = 0 for VBROADCASTSD or VBROADCASTF128.
If EVEX.L’L = 0 for VBROADCASTSD/VBROADCASTF32X2/VBROADCASTF32X4/VBROAD-
CASTF64X2.
If EVEX.L’L < 10b for VBROADCASTF32X8/VBROADCASTF64X4.VCMPPH—Compare Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-21VCMPPH—Compare Packed FP16 Values
This instruction compares packed FP16 values from source  operands and stores the result in the destination mask 
operand. The comparison predicate operand (immediate byte  bits 4:0) specifies the type of comparison performed

operand. The comparison predicate operand (immediate byte  bits 4:0) specifies the type of comparison performed 
on each of the pairs of packed values. The destinat ion elements are updated according to the writemask.
Operation
CASE (imm8 & 0x1F) OF
0: CMP_OPERATOR := EQ_OQ;1: CMP_OPERATOR := LT_OS;2: CMP_OPERATOR := LE_OS;3: CMP_OPERATOR := UNORD_Q;4: CMP_OPERATOR := NEQ_UQ;5: CMP_OPERATOR := NLT_US;6: CMP_OPERATOR := NLE_US;7: CMP_OPERATOR := ORD_Q;8: CMP_OPERATOR := EQ_UQ;9: CMP_OPERATOR := NGE_US;10: CMP_OPERATOR := NGT_US;11: CMP_OPERATOR := FALSE_OQ;12: CMP_OPERATOR := NEQ_OQ;13: CMP_OPERATOR := GE_OS;14: CMP_OPERATOR := GT_OS;15: CMP_OPERATOR := TRUE_UQ;16: CMP_OPERATOR := EQ_OS;17: CMP_OPERATOR := LT_OQ;18: CMP_OPERATOR := LE_OQ;19: CMP_OPERATOR := UNORD_S;20: CMP_OPERATOR := NEQ_US;21: CMP_OPERATOR := NLT_UQ;22: CMP_OPERATOR := NLE_UQ;23: CMP_OPERATOR := ORD_S;Opcode/
En64/32 
Bit Mode 
EVEX.128.NP.0F3A.W0 C2 /r /ib
VCMPPH k1{k2}, xmm2, xmm3/
m128/m16bcst, imm8A V/V AVX512-FP16 
AVX512VLCompare packed FP16 values in xmm3/m128/
m16bcst and xmm2 using bi ts 4:0 of imm8 as a 
comparison predicate subject to writemask k2, and 
store the result in mask register k1.
EVEX.256.NP.0F3A.W0 C2 /r /ib
VCMPPH k1{k2} , ymm2, ymm3/
m256/m16bcst, imm8A V/V AVX512-FP16 
AVX512VLCompare packed FP16 values in ymm3/m256/
m16bcst and ymm2 using bits 4:0 of imm8 as a 
EVEX.512.NP.0F3A.W0 C2 /r /ib
VCMPPH k1{k2}, zmm2, zmm3/
m512/m16bcst {sae}, imm8A V/V AVX512-FP16 Compare packed FP16 values in zmm3/m512/
m16bcst and zmm2 using bits 4:0 of imm8 as a 
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)VCMPPH—Compare Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-22 Vol. 2C24: CMP_OPERATOR := EQ_US;
25: CMP_OPERATOR := NGE_UQ;26: CMP_OPERATOR := NGT_UQ;27: CMP_OPERATOR := FALSE_OS;28: CMP_OPERATOR := NEQ_OS;29: CMP_OPERATOR := GE_OQ;30: CMP_OPERATOR := GT_OQ;31: CMP_OPERATOR := TRUE_US;ESAC
VCMPPH (EVEX Encoded Versions)
VL = 128, 256 or 512KL := VL/16
IF k2[j] OR *no writemask*:
tsrc2 := SRC2.fp16[0]
ELSE:
tsrc2 := SRC2.fp16[j]
DEST.bit[j] := SRC1.fp16[ j] CMP_OPERATOR tsrc2
ELSE
DEST.bit[j] := 0
DEST[MAXKL-1:KL] := 0
VCMPPH ___mmask8 _mm_cmp_ph_mask (__m1 28h a, __m128h b, const int imm8);
VCMPPH ___mmask8 _mm_mask_cmp_ph_ mask (__mmask8 k1, __m128h a,  __m128h b, const int imm8);
VCMPPH ___mmask16 _mm256_cmp_ph_mask ( __m256h a, __m256h b, const int imm8);
VCMPPH ___mmask16 _mm256_mask_cmp_ph_mask (__mma sk16 k1, __m256h a, __m256h b, const int imm8);
VCMPPH ___mmask32 _mm512_cmp_ph_mask ( __m512h a, __m512h b, const int imm8);
VCMPPH ___mmask32 _mm512_mask_cmp_ph_mask (__mma sk32 k1, __m512h a, __m512h b, const int imm8);
VCMPPH ___mmask32 _mm512_cmp_round _ph_mask (__m512h a, __m512h b,  const int imm8, const int sae);
VCMPPH ___mmask32 _mm512_mask_cmp_round_ ph_mask (__mmask32 k1, __m512h a, __m512h b, const int imm8, const int sae);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCMPSH—Compare Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-23VCMPSH—Compare Scalar FP16 Values
This instruction compares the FP16 values from the lowest element of the source operands and stores the result in 
the destination mask operand. The comparison predicate op erand (immediate byte bits 4:0) specifies the type of 
comparison performed on the pair of packed FP16 values . The low destination bit is updated according to the 
writemask. Bits MAXKL-1:1 of the destination operand are zeroed.
Operation
0: CMP_OPERATOR := EQ_OQ;1: CMP_OPERATOR := LT_OS;2: CMP_OPERATOR := LE_OS;3: CMP_OPERATOR := UNORD_Q;4: CMP_OPERATOR := NEQ_UQ;5: CMP_OPERATOR := NLT_US;6: CMP_OPERATOR := NLE_US;7: CMP_OPERATOR := ORD_Q;8: CMP_OPERATOR := EQ_UQ;9: CMP_OPERATOR := NGE_US;10: CMP_OPERATOR := NGT_US;11: CMP_OPERATOR := FALSE_OQ;12: CMP_OPERATOR := NEQ_OQ;13: CMP_OPERATOR := GE_OS;14: CMP_OPERATOR := GT_OS;15: CMP_OPERATOR := TRUE_UQ;16: CMP_OPERATOR := EQ_OS;17: CMP_OPERATOR := LT_OQ;18: CMP_OPERATOR := LE_OQ;19: CMP_OPERATOR := UNORD_S;20: CMP_OPERATOR := NEQ_US;21: CMP_OPERATOR := NLT_UQ;22: CMP_OPERATOR := NLE_UQ;23: CMP_OPERATOR := ORD_S;24: CMP_OPERATOR := EQ_US;25: CMP_OPERATOR := NGE_UQ;26: CMP_OPERATOR := NGT_UQ;27: CMP_OPERATOR := FALSE_OS;28: CMP_OPERATOR := NEQ_OS;29: CMP_OPERATOR := GE_OQ;30: CMP_OPERATOR := GT_OQ;Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.F3.0F3A.W0 C2 /r /ib
VCMPSH k1{k2}, xmm2, xmm3/m16 
{sae}, imm8A V/V AVX512-FP16 Compare low FP16 values in xmm3/m16 and 
xmm2 using bits 4:0 of imm8 as a comparison 
predicate subject to writemask k2, and store the 
result in mask  register k1.
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)VCMPSH—Compare Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
5-24 Vol. 2C31: CMP_OPERATOR := TRUE_US;
ESAC 
VCMPSH (EVEX Encoded Versions)
IF k2[0] OR *no writemask*:
DEST.bit[0] := SRC1.fp16[0] CMP_OPERATOR SRC2.fp16[0]
ELSE
DEST.bit[0] := 0
DEST[MAXKL-1:1] := 0
VCMPSH __mmask8 _mm_cmp_round_sh_mask (__m128h a, __m128h b, const int imm8, const int sae);
VCMPSH __mmask8 _mm_mask_cmp_round_sh_mask (__mmask8 k1 , __m128h a, __m128h b, const int imm8, const int sae);
VCMPSH __mmask8 _mm_cmp_sh_mask (__m128h a, __m128h b, const int imm8);VCMPSH __mmask8 _mm_mask_cmp_s h_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VCOMISH—Compare Scalar Ordere d FP16 Values and Set EFLAGSINSTRUCTION SET REFERENCE, V
Vol. 2C 5-25VCOMISH—Compare Scalar Ordered FP16 Values and Set EFLAGS
This instruction compares the FP16 values in the low wo rd of operand 1 (first oper and) and operand 2 (second 
operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, 
less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned 
if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 16-bit memory location.
The VCOMISH instruction differs from the VUCOMISH instructio n in that it signals a SIMD floating-point invalid oper-
ation exception (#I) when a source operand is either a QN aN or SNaN. The VUCOMISH instruction signals an invalid 
numeric exception only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD  floating-point exception is generated. EVEX.vvvv is 
reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCOMISH SRC1, SRC2 
RESULT := OrderedCompare(SRC1.fp16[0],SRC2.fp16[0])IF RESULT is UNORDERED:
ZF, PF, CF := 1, 1, 1
ELSE IF RESULT is GREATER_THAN:
ZF, PF, CF := 0, 0, 0
ELSE IF RESULT is LESS_THAN:
ZF, PF, CF := 0, 0, 1
ELSE: // RESULT is EQUALS
ZF, PF, CF := 1, 0, 0
OF, AF, SF := 0, 0, 0 
VCOMISH int _mm_comi_round_sh (__m128h a, __m128h b, const int imm8, const int sae);
VCOMISH int _mm_comi_sh (__m128h a, __m128h b, const int imm8);
VCOMISH int _mm_comieq_sh (__m128h a, __m128h b);VCOMISH int _mm_comige_sh (__m128h a, __m128h b);VCOMISH int _mm_comigt_sh (__m128h a, __m128h b);VCOMISH int _mm_comile_sh (__m128h a, __m128h b);VCOMISH int _mm_comilt_sh (__m128h a, __m128h b);VCOMISH int _mm_comineq_sh (__m128h a, __m128h b);
Invalid, Denormal.Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.NP.MAP5.W0 2F /r
VCOMISH xmm1, xmm2/m16 {sae}A V/V AVX512-FP16 Compare low FP16 values in xmm1 and xmm2/
m16, and set the EFLAGS flags accordingly.
A Scalar ModRM:reg (r) ModRM:r/m (r) N/A N/AVCOMISH—Compare Scalar Ordered FP16 Values and Set EFLAGSINSTRUCTION SET REFERENCE, V
5-26 Vol. 2COther Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”VCOMPRESSPD—Store Sparse Packed Double Precis ion Floating-Point Values Into Dense MemoryINSTRUCTION SET REFERENCE, V
Vol. 2C 5-27VCOMPRESSPD—Store Sparse Packed Double Prec ision Floating-Point Values Into Dense 
Memory
Compress (store) up to 8 double precision floating-point va lues from the source operand (the second operand) as 
a contiguous vector to the destination operand (the firs t operand) The source operand is a ZMM/YMM/XMM register,

En64/32 
Bit Mode 
Memory
a contiguous vector to the destination operand (the firs t operand) The source operand is a ZMM/YMM/XMM register, 
the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active 
elements) from the source operand to compress into a cont iguous vector. The contiguous vector is written to the 
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z 
Register destination version: If the vector length of the cont iguous vector is less than that of the input vector in the 
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper 
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Note that the compressed displacement assumes a pre-scalin g (N) corresponding to the size of one single element 
instead of the size of the full vector.
Operation
VCOMPRESSPD (EVEX Encoded Versions) Store Form
SIZE := 64k := 0FOR j := 0 TO KL-1
THEN 
DEST[k+SIZE-1:k] := SRC[i+63:i]k := k + SIZE
FI;
ENDFOROpcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W1 8A /r
VCOMPRESSPD xmm1/m128 {k1}{z}, 
xmm2AV / V A V X 5 1 2 V L
AVX512FCompress packed double precision floating-point 
values from xmm2 to xmm1/m128 using writemask 
k1.
EVEX.256.66.0F38.W1 8A /r
VCOMPRESSPD ymm1/m256 {k1}{z}, 
ymm2AV / V A V X 5 1 2 V L
values from ymm2 to ym m1/m256 using writemask 
k1.
EVEX.512.66.0F38.W1 8A /r
VCOMPRESSPD zmm1/m512 {k1}{z}, zmm2A V/V AVX512F Compress packed double precision floating-point 
values from zmm2 usin g control mask k1 to 
zmm1/m512.
A Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AVCOMPRESSPD—Store Sparse Packed Double Precis ion Floating-Point Values Into Dense MemoryINSTRUCTION SET REFERENCE, V
5-28 Vol. 2CVCOMPRESSPD (EVEX Encoded Versions) Reg-Reg Form
(KL, VL) = (2, 128), (4, 256), (8, 512)SIZE := 64k := 0FOR j := 0 TO KL-1
THEN 
FI;
ENDFOR
IF *merging-masking* 
THEN *DEST[VL-1:k] remains unchanged*ELSE DEST[VL-1:k] := 0
FI
VCOMPRESSPD __m512d _mm512_mask_compress_pd( __m512d s, __mmask8 k, __m512d a);
VCOMPRESSPD __m512d _mm512_maskz_compress_pd( __mmask8 k, __m512d a);VCOMPRESSPD void _mm512_mask_compressstoreu _pd( void * d, __mmask8 k, __m512d a);
VCOMPRESSPD __m256d _mm256_mask_compress_pd( __m256d s, __mmask8 k, __m256d a);VCOMPRESSPD __m256d _mm256_maskz_compress_pd( __mmask8 k, __m256d a);VCOMPRESSPD void _mm256_mask_compressstoreu _pd( void * d, __mmask8 k, __m256d a);
VCOMPRESSPD __m128d _mm_mask_compress_pd(  __m128d s, __mmask8 k, __m128d a);
VCOMPRESSPD __m128d _mm_maskz_compress_pd( __mmask8 k, __m128d a);VCOMPRESSPD void _mm_mask_compressstoreu_p d( void * d, __mmask8 k, __m128d a);
None.
EVEX-encoded instructions, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B.VCOMPRESSPS—Store Sparse Packed Single Precis ion Floating-Point Values Into Dense MemoryINSTRUCTION SET REFERENCE, V
Vol. 2C 5-29VCOMPRESSPS—Store Sparse  Packed Single Precision Floating -Point Values Into Dense Memory
Compress (stores) up to 16 single precision floating-point values from the source operand (the second operand) to 
the destination operand (the first operand). The source  operand is a ZMM/YMM/XMM register, the destination 
operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (a pa rtial vector or possibly non-contiguous if less than 16 
active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to 
the destination starting from the low element of the destination operand.
Operation
VCOMPRESSPS (EVEX Encoded Versions) Store Form
(KL, VL) = (4, 128), (8, 256), (16, 512)SIZE := 32k := 0FOR j := 0 TO KL-1
THEN 
DEST[k+SIZE-1:k] := SRC[i+31:i]k := k + SIZE 
FI;
ENDFOR;Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W0 8A /r
VCOMPRESSPS xmm1/m128 {k1}{z}, 
AVX512FCompress packed single precision floating-point 
values from xmm2 to xm m1/m128 using writemask 
k1.
EVEX.256.66.0F38.W0 8A /r
VCOMPRESSPS ymm1/m256 {k1}{z}, ymm2AV / V A V X 5 1 2 V L
values from ymm2 to ymm1/m256 using writemask k1.
EVEX.512.66.0F38.W0 8A /r
VCOMPRESSPS zmm1/m512 {k1}{z}, 
zmm2A V/V AVX512F Compress packed single precision floating-point 
A Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AVCOMPRESSPS—Store Sparse Packed Single Precis ion Floating-Point Values Into Dense MemoryINSTRUCTION SET REFERENCE, V
5-30 Vol. 2CVCOMPRESSPS (EVEX Encoded Versions) Reg-Reg Form
THEN 
DEST[k+SIZE-1:k] := SRC[i+31:i]k := k + SIZE
FI;
ENDFORIF *merging-masking* 
THEN *DEST[VL-1:k] remains unchanged*ELSE DEST[VL-1:k]  := 0
FIDEST[MAXVL-1:VL] := 0
VCOMPRESSPS __m512 _mm512_mask_compress _ps( __m512 s, __mmask16 k, __m512 a);
VCOMPRESSPS __m512 _mm512_maskz_com press_ps( __mmask16 k, __m512 a);
VCOMPRESSPS void _mm512_mask_compressstoreu _ps( void * d, __mmask16 k, __m512 a);
VCOMPRESSPS __m256 _mm256_mask_compress_p s( __m256 s, __mmask8 k, __m256 a);
VCOMPRESSPS __m256 _mm256_maskz_com press_ps( __mmask8 k, __m256 a);
VCOMPRESSPS void _mm256_mask_compressstoreu _ps( void * d, __mmask8 k, __m256 a);
VCOMPRESSPS __m128 _mm_mask_compress_ps ( __m128 s, __mmask8 k, __m128 a);
VCOMPRESSPS __m128 _mm_maskz_comp ress_ps( __mmask8 k, __m128 a);
VCOMPRESSPS void _mm_mask_compressstoreu _ps( void * d, __mmask8 k, __m128 a);
None.
EVEX-encoded instructions, see Exceptions Type E4.nb.  in Table 2-49, “Type E4 Class Exception Conditions.”
Additionally:#UD If EVEX.vvvv != 1111B.VCVTDQ2PH—Convert Packed Signed Doubleword Integers to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-31VCVTDQ2PH—Convert Packed Signed Double word Integers to Packed FP16 Values
This instruction converts four, eight, or sixteen packed si gned doubleword integers in the source operand to four, 
eight, or sixteen packed FP16 values in the destination operand.
EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcast from a 32-bi t memory location. The destination operand is a YMM/XMM 
EVEX.vvvv is reserved and must be 1 111b, otherwise instructions will #UD.
If the result of the convert operation is overflow and MXCS R.OM=0 then a SIMD exception will be raised with OE=1, 
PE=1.
Operation
VCVTDQ2PH DEST, SRC 
VL = 128, 256 or 512KL := VL / 32
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
ELSE:
IF *SRC is memory * and EVEX.b = 1:
tsrc := SRC.dword[0]
ELSE
tsrc := SRC.dword[j]
DEST.fp16[j] := Convert_ integer32_to_fp16(tsrc)
// else dest.fp16[j] remains unchangedOpcode/
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W0 5B /r
VCVTDQ2PH xmm1{k1}{z}, xmm2/
m128/m32bcstA V/V AVX512-FP16 
AVX512VLConvert four packed signed doubleword integers 
from xmm2/m128/m32bcst to four packed FP16 
values, and store the resu lt in xmm1 subject to 
EVEX.256.NP.MAP5.W0 5B /r
VCVTDQ2PH xmm1{k1}{z}, ymm2/
m256/m32bcstA V/V AVX512-FP16 
AVX512VLConvert eight packed signed doubleword integers

PE=1.
Operation
ELSE:
ELSE
En64/32 
Bit Mode 
AVX512VLConvert eight packed signed doubleword integers 
from ymm2/m256/m32bcst to eight packed 
FP16 values, and store the result in xmm1 
EVEX.512.NP.MAP5.W0 5B /r
VCVTDQ2PH ymm1{k1}{z}, zmm2/
m512/m32bcst {er}A V/V AVX512-FP16 Convert sixteen packed signed doubleword 
integers from zmm2/m512/m32bcst to sixteen 
packed FP16 values, and store the result in 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTDQ2PH—Convert Packed Signed Doubleword Integers to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-32 Vol. 2CDEST[MAXVL-1:VL/2] := 0 
VCVTDQ2PH __m256h _mm512_cvt_roundepi32_ph (__m512i a, int rounding);
VCVTDQ2PH __m256h _mm512_mask_cvt_rou ndepi32_ph (__m256h src, __mmask16 k, __m512i a, int rounding);
VCVTDQ2PH __m256h _mm512_maskz_cvt_roundepi32_ph (__mmask16 k, __m512i a, int rounding);VCVTDQ2PH __m128h _mm_cvtepi32_ph (__m128i a);VCVTDQ2PH __m128h _mm_mask_cvtepi32_ph (__m128h src, __mmask8 k, __m128i a);VCVTDQ2PH __m128h _mm_maskz_cvtepi32_ph (__mmask8 k, __m128i a);VCVTDQ2PH __m128h _mm256_cvtepi32_ph (__m256i a);VCVTDQ2PH __m128h _mm256_mask_cvtepi32_ph (__m128h src, __mmask8 k, __m256i a);VCVTDQ2PH __m128h _mm256_maskz_cvte pi32_ph (__mmask8 k, __m256i a);
VCVTDQ2PH __m256h _mm512_cvtepi32_ph (__m512i a);VCVTDQ2PH __m256h _mm512_mask_cvtepi32_ph (__m256h src, __mmask16 k, __m512i a);VCVTDQ2PH __m256h _mm512_maskz_cvtepi32_ph (__mmask16 k, __m512i a);
Overflow, Precision.
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 DataINSTRUCTION SET REFERENCE, V
Vol. 2C 5-33VCVTNE2PS2BF16—Convert Two Packed Si ngle Data to One Packed BF16 Data
Converts two SIMD registers of packed single data  into a single register of packed BF16 data.
This instruction does not support memory fault suppression.This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and 
input denormals are always treated as zero. MXCSR is not consulted nor updated. No floating-point exceptions are 
Operation
VCVTNE2PS2BF16 dest, src1, src2
VL = (128, 256, 512)KL = VL/16
origdest 
:= dest
IF k1[ i ] or *no writemask*:
IF i < KL/2:
IF src2 is memory and evex.b == 1:
t := src2.fp32[0]
ELSE:
t := src2.fp32[ i ]
ELSE:
t := src1.fp32[ i-KL/2]
// See VCVTNEPS2BF16 for definition of convert helper function 
dest.word[i] := convert_fp32_to_bfloat16(t)
dest.word[ i ] := 0
ELSE:  // Merge ma sking, dest element unchanged
dest.word[ i ] := origdest.word[ i ]
En64/32 
Bit Mode 
EVEX.128.F2.0F38.W0 72 /r
VCVTNE2PS2BF16 xmm1{k1}{z}, 
xmm2, xmm3/m128/m32bcstAV / VA V X 5 1 2 V L
AVX512_BF16Convert packed single data from xmm2 and 
xmm3/m128/m32bcst to packed BF16 data in 
EVEX.256.F2.0F38.W0 72 /r
VCVTNE2PS2BF16 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcstAV / VA V X 5 1 2 V L
AVX512_BF16Convert packed single data from ymm2 and 
ymm3/m256/m32bcst to packed BF16 data in ymm1 with writemask k1.
EVEX.512.F2.0F38.W0 72 /r
VCVTNE2PS2BF16 zmm1{k1}{z}, 
zmm2, zmm3/m512/m32bcstAV / VA V X 5 1 2 F
AVX512_BF16Convert packed single data from zmm2 and 
zmm3/m512/m32bcst to packed BF16 data in 
zmm1 with writemask k1.
AF u l lM o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/AVCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 DataINSTRUCTION SET REFERENCE, V
5-34 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VCVTNE2PS2BF16 __m128bh _mm_cvtne2ps_pbh (__m128, __m128);
VCVTNE2PS2BF16 __m128bh _mm_mask_cvtne2ps_pbh (__m128bh, __mmask8, __m128, __m128);VCVTNE2PS2BF16 __m128bh _mm_maskz_cvtne2ps_pbh (__mmask8, __m128, __m128);VCVTNE2PS2BF16 __m256bh _mm256_cvtne2ps_pbh (__m256, __m256);VCVTNE2PS2BF16 __m256bh _mm256_mask_cvtne2ps_pbh (__m256bh, __mmask16, __m256, __m256);VCVTNE2PS2BF16 __m256bh _mm256_maskz_cvtne2ps_ pbh (__mmask16, __m256, __m256);VCVTNE2PS2BF16 __m512bh _mm512_cvtne2ps_pbh (__m512, __m512);VCVTNE2PS2BF16 __m512bh _mm512_mask_cvtne2ps_pbh (__m512bh, __mmask32, __m512, __m512);VCVTNE2PS2BF16 __m512bh _mm512_maskz_cvtne2ps_pbh (__mmask32, __m512, __m512);
None.
See Table 2-50, “Type E4NF Class Exception Conditions.”VCVTNEPS2BF16—Convert Packed Single Data to Packed BF16 DataINSTRUCTION SET REFERENCE, V
Vol. 2C 5-35VCVTNEPS2BF16—Convert Packed Sing le Data to Packed BF16 Data
Converts one SIMD register of packed single da ta into a single register of packed BF16 data.
This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and 
input denormals are always treated as zero. MXCSR is not consulted nor updated. 
As the instruction operand encoding table shows, the EV EX.vvvv field is not used for encoding an operand. 
EVEX.vvvv is reserved and must be 0b 1111 otherwise instructions will #UD.
Operation
Define convert_fp32_to_bfloat16(x):
IF x is zero or denormal:
dest[15] := x[31] // sign preserving ze ro (denormal go to zero)
dest[14:0] := 0
ELSE IF x is infinity:
dest[15:0] := x[31:16]
ELSE IF x is NAN:
dest[15:0] := x[31:16] // truncate and set MS B of the mantissa to force QNAN
dest[6] := 1
ELSE // normal number
LSB := x[16]
rounding_bias := 0x00007FFF + LSB
temp[31:0] := x[31:0] + rounding_bias // integer add
dest[15:0] := temp[31:16]
RETURN destOpcode/
En64/32 
Bit Mode 
EVEX.128.F3.0F38.W0 72 /r
VCVTNEPS2BF16 xmm1{k1}{z}, 
xmm2/m128/m32bcstAV / VA V X 5 1 2 V L
AVX512_BF16Convert packed single data from xmm2/m128 
to packed BF16 data in  xmm1 with writemask 
k1.
EVEX.256.F3.0F38.W0 72 /r
VCVTNEPS2BF16 xmm1{k1}{z}, ymm2/m256/m32bcstAV / VA V X 5 1 2 V L
AVX512_BF16Convert packed single data from ymm2/m256 
k1.
EVEX.512.F3.0F38.W0 72 /r
VCVTNEPS2BF16 ymm1{k1}{z}, 
zmm2/m512/m32bcstAV / VA V X 5 1 2 F
AVX512_BF16Convert packed single data from zmm2/m512 
to packed BF16 data in  ymm1 with writemask 
k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTNEPS2BF16—Convert Packed Single Data to Packed BF16 DataINSTRUCTION SET REFERENCE, V
5-36 Vol. 2CVCVTNEPS2BF16 dest, src
origdest 
:= dest
FOR i := 0 to KL/2-1:
IF src is memory and evex.b == 1:
t := src.fp32[0]
ELSE:
t := src.fp32[ i ]
ELSE:  // Merge masking, dest element unchanged
DEST[MAXVL-1:VL/2] := 0
VCVTNEPS2BF16 __m128bh _mm_cvtneps_pbh (__m128);
VCVTNEPS2BF16 __m128bh _mm_mask_cvtne ps_pbh (__m128bh, __mmask8, __m128);
VCVTNEPS2BF16 __m128bh _mm_maskz_cvtneps_pbh (__mmask8, __m128);VCVTNEPS2BF16 __m128bh _mm256_cvtneps_pbh (__m256);VCVTNEPS2BF16 __m128bh _mm256_mask_cvtn eps_pbh (__m128bh, __mmask8, __m256);
VCVTNEPS2BF16 __m128bh _mm256_maskz_cvtneps_pbh (__mmask8, __m256);VCVTNEPS2BF16 __m256bh _mm512_cvtneps_pbh (__m512);VCVTNEPS2BF16 __m256bh _mm512_mask_cv tneps_pbh (__m256bh, __mmask16, __m512);
VCVTNEPS2BF16 __m256bh _mm512_maskz_cvtneps_pbh (__mmask16, __m512);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VCVTPD2PH—Convert Packed Double Precision FP Values to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-37VCVTPD2PH—Convert Packed Double Precis ion FP Values to Packed FP16 Values
This instruction converts two, four, or eight packed doub le precision floating-point values in the source operand 
(second operand) to two, four, or eight packed FP16 va lues in the destination operand (first operand). When a 
conversion is inexact, the value return ed is rounded according to the rounding control bits in the MXCSR register or 
the embedded rounding control bits.
a 512/256/128-bit vector broadcasts from a 64-bit memory  location. The destination operand is a XMM register 
conditionally updated with writemask k1. The upper bits  (MAXVL-1:128/64/32) of the corresponding destination 
EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
This instruction uses MXCSR.DAZ for handling FP64 inputs . FP16 outputs can be normal or denormal, and are not 
conditionally flushed to zero.Opcode/
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W1 5A /r
VCVTPD2PH xmm1{k1}{z}, xmm2/
m128/m64bcstA V/V AVX512-FP16 
AVX512VLConvert two packed double precision floating-
point values in xmm2/m128/m64bcst to two

En64/32 
Bit Mode 
point values in xmm2/m128/m64bcst to two 
packed FP16 values, and store the result in xmm1 
EVEX.256.66.MAP5.W1 5A /r
VCVTPD2PH xmm1{k1}{z}, ymm2/
m256/m64bcstA V/V AVX512-FP16 
AVX512VLConvert four packed double precision floating-
point values in ymm2/m256/m64bcst to four 
EVEX.512.66.MAP5.W1 5A /r
VCVTPD2PH xmm1{k1}{z}, zmm2/
m512/m64bcst {er}A V/V AVX512-FP16 Convert eight packed double precision floating-
point values in zmm2/m 512/m64bcst to eight 
packed FP16 values, and store the result in ymm1 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPD2PH—Convert Packed Double Precision FP Values to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-38 Vol. 2COperation
VCVTPD2PH DEST, SRC 
VL = 128, 256 or 512KL := VL / 64
ELSE:
tsrc := SRC.double[0]
ELSE
tsrc := SRC.double[j]
DEST.fp16[j] := Convert_fp64_to_fp16(tsrc)
DEST[MAXVL-1:VL/4] := 0 
VCVTPD2PH __m128h _mm512_cvt_round pd_ph (__m512d a, int rounding);
VCVTPD2PH __m128h _mm512_mask_cvt_roundpd_ph ( __m128h src, __mmask8 k, __m512d a, int rounding);
VCVTPD2PH __m128h _mm512_mas kz_cvt_roundpd_ph (__mmask8 k, __m512d a, int rounding);
VCVTPD2PH __m128h _mm_cvtpd_ph (__m128d a);VCVTPD2PH __m128h _mm_mask_cvtpd_ph (_ _m128h src, __mmask8 k, __m128d a);
VCVTPD2PH __m128h _mm_maskz_cvtp d_ph (__mmask8 k, __m128d a);
VCVTPD2PH __m128h _mm256 _cvtpd_ph (__m256d a);
VCVTPD2PH __m128h _mm256_mask_cvtpd_ph (__m128h src, __mmask8 k, __m256d a);
VCVTPD2PH __m128h _mm256_maskz_cvt pd_ph (__mmask8 k, __m256d a);
VCVTPD2PH __m128h _mm512 _cvtpd_ph (__m512d a);
VCVTPD2PH __m128h _mm512_mask_cvtpd_ph (__m128h src, __mmask8 k, __m512d a);
VCVTPD2PH __m128h _mm512_maskz_cvt pd_ph (__mmask8 k, __m512d a);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTPD2QQ—Convert Packed Double Precision Floati ng-Point Values to Packed Quadword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-39VCVTPD2QQ—Convert Packed Double Precision Floating-Point Values to Packed Quadword 
Integers
Converts packed double precision floating-point values in the source operand (second operand) to packed quad-
word integers in the destination operand (first operand). 
The destination operation is a ZMM/YMM/XMM regi ster conditionally updated with writemask k1. 
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPD2QQ (EVEX Encoded Version) When SRC Operand is a Register
IF (VL == 512) AND (EVEX.b == 1) 
THEN
ELSE 
FI;
Convert_Double_Precision_Floating_P oint_To_QuadInteger(SRC[i+63:i])
ELSE 
FIOpcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F.W1 7B /r
VCVTPD2QQ xmm1 {k1}{z}, 
xmm2/m128/m64bcstA V/V AVX512VL
AVX512DQConvert two packed double precision floating-point values from 
xmm2/m128/m64bcst to two packed quadword integers in 
EVEX.256.66.0F.W1 7B /r
VCVTPD2QQ ymm1 {k1}{z}, 
ymm2/m256/m64bcst A V/V AVX512VL
AVX512DQConvert four packed double precision floating-point values from 
ymm2/m256/m64bcst to four packed quadword integers in 
EVEX.512.66.0F.W1 7B /r
VCVTPD2QQ zmm1 {k1}{z}, zmm2/m512/m64bcst{er}A V/V AVX512DQ Convert eight packed double precision floating-point values 
from zmm2/m512/m64bcst to eight packed quadword integers in zmm1 with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPD2QQ—Convert Packed Double Precision Floati ng-Point Values to Packed Quadword IntegersINSTRUCTION SET REFERENCE, V
5-40 Vol. 2CFI;
VCVTPD2QQ (EVEX Encoded Version) When SRC Operand is a Memory Source
THEN 
IF (EVEX.b == 1) 
THEN
DEST[i+63:i] := Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[63:0])
ELSE 
DEST[i+63:i] := Convert_Doub le_Precision_Floating_Point_ To_QuadInteger(SRC[i+63:i])
FI;
ELSE 
FI
FI;
VCVTPD2QQ __m512i _mm512_cvtpd_epi64( __m512d a);
VCVTPD2QQ __m512i _mm512_mask_cvtpd_epi6 4( __m512i s, __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_maskz_cvtpd _epi64( __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_cvt_rou ndpd_epi64( __m512d a, int r);
VCVTPD2QQ __m512i _mm512_mask_cvt_roundpd_epi64(  __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m512i _mm512_maskz_cvt_roundpd _epi64( __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m256i _mm256_mask_cvtpd_epi6 4( __m256i s, __mmask8 k, __m256d a);
VCVTPD2QQ __m256i _mm256_maskz_cvtpd _epi64( __mmask8 k, __m256d a);
VCVTPD2QQ __m128i _mm_mask_cvtpd_epi64(  __m128i s, __mmask8 k, __m128d a);
VCVTPD2QQ __m128i _mm_maskz_cvtpd_epi64( __mmask8 k, __m128d a);VCVTPD2QQ __m256i _mm256_cvtpd_epi64 (__m256d src)VCVTPD2QQ __m128i _mm_cvtpd_epi64 (__m128d src)
Additionally:#UD If EVEX.vvvv != 1111B.VCVTPD2UDQ—Convert Packed Double Precision Floating-P oint Values to Packed Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-41VCVTPD2UDQ—Convert Packed Doub le Precision Floating-Point Values to Packed Unsigned 
Doubleword Integers
Converts packed double precision floating-point values in the source operand (the second operand) to packed 
unsigned doubleword integers in the de stination operand (the first operand). 
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is 
returned, where w represents the number  of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256 /128-bit memory location, or a 512/256/128-bit vector 
updated with writemask k1. The uppe r bits (MAXVL-1:256) of the corresponding destination are zeroed.
Operation
VCVTPD2UDQ (EVEX Encoded Versions) When SRC2 Operand is a Register
THEN
ELSE 
FI;
THEN 
DEST[i+31:i] :=Convert_Double_Precision_Floating _Point_To_UInteger(SRC[k+63:k])
ELSE 
THEN *DEST[i+31:i] remains unchanged*Opcode
En64/32 
Bit Mode 
Feature 
EVEX.128.0F.W1 79 /r
VCVTPD2UDQ xmm1 {k1}{z}, 
xmm2/m128/m64bcstAV / V A V X 5 1 2 V L
values in xmm2/m128/m64bcst to two unsigned 
EVEX.256.0F.W1 79 /r
ymm2/m256/m64bcstAV / V A V X 5 1 2 V L
values in ymm2/m256/m64bcst to four unsigned 
EVEX.512.0F.W1 79 /r

THEN
ELSE 
FI;
THEN 
ELSE 
En64/32 
Bit Mode 
Feature 
VCVTPD2UDQ ymm1 {k1}{z}, zmm2/m512/m64bcst{er}A V/V AVX512F Convert eight packed double precision floating-point 
values in zmm2/m512/m64bcst to eight unsigned doubleword integers in ymm1 subject to writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPD2UDQ—Convert Packed Double Precision Floating-P oint Values to Packed Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, V
5-42 Vol. 2CELSE ; zeroing-masking
FI
FI;
VCVTPD2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Double_Precision_Floating _Point_To_UInteger(SRC[63:0])
ELSE 
Convert_Double_Precision_Floating _Point_To_UInteger(SRC[k+63:k])
FI;
ELSE 
FI
FI;
VCVTPD2UDQ __m256i _mm512_cvtpd_epu32( __m512d a);
VCVTPD2UDQ __m256i _mm512_mask_cvtpd_epu3 2( __m256i s, __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_maskz_cvt pd_epu32( __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_cvt_rou ndpd_epu32( __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_mask_cvt_roundpd_epu 32( __m256i s, __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_maskz_cvt_round pd_epu32( __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m128i _mm256_mask_cvtpd_epu3 2( __m128i s, __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm256_maskz_cvt pd_epu32( __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm_mask_cvtpd_epu3 2( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UDQ __m128i _mm_maskz_cvtpd_epu32( __mmask8 k, __m128d a);
#UD If EVEX.vvvv != 1111B.VCVTPD2UQQ—Convert Packed Double Precision Floating-P oint Values to Packed Unsigned Quadword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-43VCVTPD2UQQ—Convert Packed Doub le Precision Floating-Point Values to Packed Unsigned 
Quadword Integers
Converts packed double precision floating-point values in  the source operand (second operand) to packed unsigned 
quadword integers in the destination operand (first operand). 
The source operand is a ZMM/YMM/XMM register or a 512/ 256/128-bit memory location. The destination operation 
is a ZMM/YMM/XMM register conditionally updated with writemask k1. 
Operation
VCVTPD2UQQ (EVEX Encoded Versions) When SRC Operand is a Register
THEN
ELSE 
FI;
Convert_Double_Precision_Floating_P oint_To_UQuadInteger(SRC[i+63:i])
ELSE 
FIOpcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F.W1 79 /r
VCVTPD2UQQ xmm1 {k1}{z}, 
xmm2/m128/m64bcst A V/V AVX512VL
xmm2/mem to two packed unsigned quadword integers in 
EVEX.256.66.0F.W1 79 /r
VCVTPD2UQQ ymm1 {k1}{z}, 
ymm2/m256/m64bcstA V/V AVX512VL
AVX512DQConvert fourth packed double precision floating-point values 
from ymm2/mem to four packed unsigned quadword integers 
EVEX.512.66.0F.W1 79 /r
VCVTPD2UQQ zmm1 {k1}{z}, zmm2/m512/m64bcst{er} A V/V AVX512DQ Convert eight packed double precision floating-point values 
from zmm2/mem to eight packed unsigned quadword integers in zmm1 with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPD2UQQ—Convert Packed Double Precision Floating-P oint Values to Packed Unsigned Quadword IntegersINSTRUCTION SET REFERENCE, V
5-44 Vol. 2CFI;
VCVTPD2UQQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Double_Precision_Floating_P oint_To_UQuadInteger(SRC[63:0])
ELSE 
FI;
ELSE 
FI
FI;
VCVTPD2UQQ __m512i _mm512_cvtpd_epu64( __m512d a);
VCVTPD2UQQ __m512i _mm512_mask_cvtpd_epu64( __m512i s, __mmask8 k, __m512d a);VCVTPD2UQQ __m512i _mm512_maskz_cvtpd_epu64( __mmask8 k, __m512d a);VCVTPD2UQQ __m512i _mm512_cvt_roundpd_epu64( __m512d a, int r);VCVTPD2UQQ __m512i _mm512_mask_cvt_roundpd_epu64(  __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_maskz_cvt_roundpd_ epu64( __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m256i _mm256_mask_cvtpd_epu64( __m256i s, __mmask8 k, __m256d a);VCVTPD2UQQ __m256i _mm256_maskz_cvtpd_epu64( __mmask8 k, __m256d a);VCVTPD2UQQ __m128i _mm_mask_cvtpd_epu64 ( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UQQ __m128i _mm_maskz_cvtpd_ epu64( __mmask8 k, __m128d a);
VCVTPD2UQQ __m256i _mm256_cvtpd_epu64 (__m256d src)VCVTPD2UQQ __m128i _mm_cvtpd_epu64 (__m128d src)
Additionally:#UD If EVEX.vvvv != 1111B.VCVTPH2DQ—Convert Packed FP16 Values to Signed Doubleword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-45VCVTPH2DQ—Convert Packed FP16 Values  to Signed Doubleword Integers
This instruction converts packed FP16 values in the source operand to signed doubleword integers in destination 
operand.
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2DQ DEST, SRC 
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
ELSE:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.dword[j] := Convert _fp16_to_integer32(tsrc)
DEST.dword[j] := 0
// else dest.dword[j ] remains unchanged
DEST[MAXVL-1:VL] := 0 Opcode/
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W0 5B /r
VCVTPH2DQ xmm1{k1}{z}, xmm2/
m64/m16bcstA V/V AVX512-FP16 
AVX512VLConvert four packed FP16  values in xmm2/m64/
m16bcst to four signed doubleword integers, and 
store the result in xmm1 subject to writemask 
k1.
EVEX.256.66.MAP5.W0 5B /r
VCVTPH2DQ ymm1{k1}{z}, xmm2/
m128/m16bcstA V/V AVX512-FP16 
AVX512VLConvert eight packed FP16 values in xmm2/
m128/m16bcst to eight signed doubleword 
integers, and store the resu lt in ymm1 subject to 
EVEX.512.66.MAP5.W0 5B /r
VCVTPH2DQ zmm1{k1}{z}, ymm2/
m256/m16bcst {er}A V/V AVX512-FP16 Convert sixteen packed FP16 values in ymm2/
m256/m16bcst to sixteen signed doubleword 
integers, and store the resu lt in zmm1 subject to 
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPH2DQ—Convert Packed FP16 Values to Signed Doubleword IntegersINSTRUCTION SET REFERENCE, V
5-46 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VCVTPH2DQ __m512i _mm512_cvt_roundph_epi32 (__m256h a, int rounding);
VCVTPH2DQ __m512i _mm512_mask_cvt_r oundph_epi32 (__m512i src, __mmask 16 k, __m256h a, int rounding);
VCVTPH2DQ __m512i _mm512_maskz_cvt_roundph_ep i32 (__mmask16 k, __m256h a, int rounding);

k1.
VCVTPH2DQ __m128i _mm_cvtph_epi32 (__m128h a);VCVTPH2DQ __m128i _mm_mask_cvtph_epi32 (__m128i src, __mmask8 k, __m128h a);VCVTPH2DQ __m128i _mm_maskz_cvtp h_epi32 (__mmask8 k, __m128h a);
VCVTPH2DQ __m256i _mm256_cvtph_epi32 (__m128h a);VCVTPH2DQ __m256i _mm256_mask_cvtph_epi32 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2DQ __m256i _mm256_maskz_cvtph_epi32 (__mmask8 k, __m128h a);VCVTPH2DQ __m512i _mm512_cvtph_epi32 (__m256h a);VCVTPH2DQ __m512i _mm512_mask_cvtph_epi32 (__m512i src, __mmask16 k, __m256h a);
VCVTPH2DQ __m512i _mm512_maskz_cvtph_epi32 (__mmask16 k, __m256h a);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTPH2PD—Convert Packed FP16 Values to FP64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-47VCVTPH2PD—Convert Packed FP16 Values to FP64 Values
This instruction converts packed FP16 values to FP64 values in the destination register. The destination elements 
are updated according to the writemask.
This instruction handles both normal and denormal FP16 inputs.
Operation
VCVTPH2PD DEST, SRC 
VL = 128, 256, or 512KL := VL/64
ELSE
DEST.fp64[j] := Convert_fp16_to_fp64(tsrc)
DEST.fp64[j] := 0
// else dest.fp64[j] remains unchanged
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W0 5A /r
VCVTPH2PD xmm1{k1}{z}, xmm2/
m32/m16bcstA V/V AVX512-FP16 
AVX512VLConvert packed FP16 values in xmm2/m32/
m16bcst to FP64 values, and store result in 
EVEX.256.NP.MAP5.W0 5A /r
VCVTPH2PD ymm1{k1}{z}, xmm2/m64/m16bcstA V/V AVX512-FP16 
AVX512VLConvert packed FP16 values in xmm2/m64/
m16bcst to FP64 values, and store result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5A /r
VCVTPH2PD zmm1{k1}{z}, xmm2/
m128/m16bcst {sae}A V/V AVX512-FP16 Convert packed FP16 values in xmm2/m128/
A Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPH2PD—Convert Packed FP16 Values to FP64 ValuesINSTRUCTION SET REFERENCE, V
5-48 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VCVTPH2PD __m512d _mm512_cvt_roundph_pd (__m128h a, int sae);
VCVTPH2PD __m512d _mm512_mask_cvt_roundph_pd (__m512d src, __mmask8 k, __m128h a, int sae);
VCVTPH2PD __m512d _mm512_mas kz_cvt_roundph_pd (__mmask8 k, __m128h a, int sae);
VCVTPH2PD __m128d _mm_cvtph_pd (__m128h a);VCVTPH2PD __m128d _mm_mask_cvtph_pd (_ _m128d src, __mmask8 k, __m128h a);
VCVTPH2PD __m128d _mm_maskz_cvtp h_pd (__mmask8 k, __m128h a);
VCVTPH2PD __m256d _mm256_cvtph_pd (__m128h a);VCVTPH2PD __m256d _mm256_mask_cvtph_pd (_ _m256d src, __mmask8 k, __m128h a);
VCVTPH2PD __m256d _mm256_maskz_cvt ph_pd (__mmask8 k, __m128h a);
VCVTPH2PD __m512d _mm512_cvtph_pd (__m128h a);VCVTPH2PD __m512d _mm512_mask_cvtph_pd (_ _m512d src, __mmask8 k, __m128h a);
VCVTPH2PD __m512d _mm512_maskz_cvt ph_pd (__mmask8 k, __m128h a);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Values  to Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-49VCVTPH2PS/VCVTPH2PSX—Convert Pa cked FP16 Values to Single Precision Floating-Point 
Values
This instruction converts packed half precision (16-bits) fl oating-point values in the low-order bits of the source 
operand (the second operand) to packed single precision fl oating-point values and writes the converted values into 
the destination operand (the first operand).
If case of a denormal operand, the correct normal result is returned. MXCSR.DAZ is ignored and is treated as if it 
0. No denormal exception is reported on MXCSR.
VEX.128 version: The source operand is a XMM register or  64-bit memory location. The destination operand is a 
XMM register. The upper bits (MAX VL-1:128) of the corresponding destination register are zeroed.
VEX.256 version: The source operand is a XMM register or  128-bit memory location. The destination operand is a 
YMM register. Bits (MAXVL-1:256) of the corre sponding destination register are zeroed.
EVEX encoded versions: The source operand is a YMM/X MM/XMM (low 64-bits) register or a 256/128/64-bit 
memory location. The destination oper and is a ZMM/YMM/XMM regi ster conditionally updated with writemask k1. Opcode/
En64/32 
Bit Mode 
VEX.128.66.0F38.W0 13 /r 
VCVTPH2PS xmm1, xmm2/m64A V/V F16C Convert four packed FP16 values in xmm2/m64 to 
packed single precision floating-point value in xmm1. 
VEX.256.66.0F38.W0 13 /r 
VCVTPH2PS ymm1, xmm2/m128A V/V F16C Convert eight packed FP16 values in xmm2/m128 to 
packed single precision floating-point value in ymm1. 
EVEX.128.66.0F38.W0 13 /r 
VCVTPH2PS xmm1 {k1}{z}, 
AVX512FConvert four packed FP16 values in xmm2/m64 to 
packed single precision floating-point values in xmm1 
subject to writemask k1. 
EVEX.256.66.0F38.W0 13 /r 
VCVTPH2PS ymm1 {k1}{z}, xmm2/m128B V/V AVX512VL
AVX512FConvert eight packed FP16 values in xmm2/m128 to 
packed single precision floating-point values in ymm1 subject to writemask k1. 
EVEX.512.66.0F38.W0 13 /r 
VCVTPH2PS zmm1 {k1}{z}, ymm2/m256 {sae}B V/V AVX512F Convert sixteen packed FP16 values in ymm2/m256 
to packed single precision floating-point values in zmm1 subject to writemask k1. 
EVEX.128.66.MAP6.W0  13 /r
VCVTPH2PSX  xmm1{k1}{z},  
xmm2/m64/m16bcstC V/V AVX512-FP16 
AVX512VLConvert four packed FP16 values in 
xmm2/m64/m16bcst to four packed single precision 
floating-point values, and store result in xmm1 subject to writemask k1.
EVEX.256.66.MAP6.W0  13 /r
VCVTPH2PSX  ymm1{k1}{z},  
xmm2/m128/m16bcstC V/V AVX512-FP16 
AVX512VLConvert eight packed FP16 values in 
xmm2/m128/m16bcst to eight packed single 
precision floating-point values, and store result in ymm1 subject to writemask k1.
EVEX.512.66.MAP6.W0  13 /r
VCVTPH2PSX  zmm1{k1}{z},  
ymm2/m256/m16bcst  {sae}C V/V AVX512-FP16 Convert sixteen packed FP16 values in 
ymm2/m256/m16bcst to sixteen packed single 
precision floating-point values, and store result in zmm1 subject to writemask k1.
C Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Valu es to Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-50 Vol. 2CThe diagram below illustrates how data is converted from four packed half precision (in 64 bits) to four single preci-
sion (in 128 bits) floating-point values.
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).
The VCVTPH2PSX instruction is a new form of the PH to PS  conversion instruction, encoded in map 6. The previous 
version of the instruction, VCVTPH2PS, that is present in AVX512F (encoded in map 2, 0F38) does not support 
embedded broadcasting. The VCVTPH2PSX instruction has the embedded broadcasting option available.
The instructions associated with AVX512_FP16 always hand le FP16 denormal number inputs; denormal inputs are 
not treated as zero.
Operation
vCvt_h2s(SRC1[15:0])
{RETURN Cvt_Half_Precision_To_ Single_Precision(SRC1[15:0]);
}
VCVTPH2PS (EVEX Encoded Versions) 
i := j * 32k := j * 16IF k1[j] OR *no writemask*
vCvt_h2s(SRC[k+15:k])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0Figure 5-6.  VCVTPH 2PS (128-bit Version)VH0 VH1 VH2 VH315             0 31           16 47           32 63           48 95                                64 127                              96
VS0 VS1 VS2 VS331                                  0 63                                32 95                                64 127                              96convert convert
convert convertxmm2/mem64
xmm1VCVTPH2PS xmm1, xmm2/mem64,  imm8VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Values  to Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-51VCVTPH2PS (VEX.256 Encoded Version)
DEST[31:0] := vCvt_h2s(SRC1[15:0]);DEST[63:32] := vCvt_h2s(SRC1[31:16]);DEST[95:64] := vCvt_h2s(SRC1[47:32]);DEST[127:96] := vCvt_h2s(SRC1[63:48]);DEST[159:128] := vCvt_h2s(SRC1[79:64]);DEST[191:160] := vCvt_h2s(SRC1[95:80]);DEST[223:192] := vCvt_h2s(SRC1[111:96]);DEST[255:224] := vCvt_h2s(SRC1[127:112]);
VCVTPH2PS (VEX.128 Encoded Version)

FI;
VCVTPH2PS (VEX.128 Encoded Version) 
DEST[31:0] := vCvt_h2s(SRC1[15:0]);DEST[63:32] := vCvt_h2s(SRC1[31:16]);DEST[95:64] := vCvt_h2s(SRC1[47:32]);DEST[127:96] := vCvt_h2s(SRC1[63:48]);
VCVTPH2PSX DEST, SRC 
VL = 128, 256, or 512KL := VL/32
ELSE
DEST.fp32[j] := Convert_fp16_to_fp32(tsrc)
DEST.fp32[j] := 0
// else dest.fp32[j] remains unchanged
DEST[MAXVL-1:VL] := 0 
None.
VCVTPH2PS __m512 _mm512_cvtph_ps( __m256i a);
VCVTPH2PS __m512 _mm512_mask_cvtph_ps (__m512 s, __mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_maskz_c vtph_ps(__mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_cvt_roundph_ps( __m256i a, int sae);VCVTPH2PS __m512 _mm512_mask_cvt_roundph_ps( __m512 s, __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m512 _mm512_maskz_cvt_roundph _ps( __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m256 _mm256_mask_cvtph_ps (__m256 s, __mmask8 k, __m128i a);
VCVTPH2PS __m256 _mm256_maskz_cvtph_ps(__mmask8 k, __m128i a);VCVTPH2PS __m128 _mm_mask_cvtph_ps( __m128 s, __mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_maskz_cvtp h_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_cvtph_ps ( __m128i m1);VCVTPH2PS __m256 _mm256_cvtph_ps ( __m128i m1)
VCVTPH2PSX __m512 _mm512_cvtx_roundph_ps (__m256h a, int sae);
VCVTPH2PSX __m512 _mm512_mask_cvtx_roundph_ps ( __m512 src, __mmask16 k, __m256h a, int sae);VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Valu es to Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-52 Vol. 2CVCVTPH2PSX __m512 _mm512_maskz_cvtx_roundph _ps (__mmask16 k, __m256h a, int sae);
VCVTPH2PSX __m128 _mm_cvtxph_ps (__m128h a);VCVTPH2PSX __m128 _mm_mask_cvtxph_ps (__m128 src, __mmask8 k, __m128h a);
VCVTPH2PSX __m128 _mm_maskz_cvtx ph_ps (__mmask8 k, __m128h a);
VCVTPH2PSX __m256 _mm256_cvtxph_ps (__m128h a);VCVTPH2PSX __m256 _mm256_mask_cvtxph_p s (__m256 src, __mmask8 k, __m128h a);
VCVTPH2PSX __m256 _mm256_maskz_cvt xph_ps (__mmask8 k, __m128h a);
VCVTPH2PSX __m512 _mm512_cvtxph_ps (__m256h a);VCVTPH2PSX __m512 _mm512_mask_cvtxph_ps (__m512 src, __mmask16 k, __m256h a);
VCVTPH2PSX __m512 _mm512_maskz_cvt xph_ps (__mmask16 k, __m256h a);
VEX-encoded instructions: Invalid.EVEX-encoded instructions: Invalid.
EVEX-encoded instructions with broa dcast (VCVTPH2PSX): Invalid, Denormal.
VEX-encoded instructions, see Table 2-26, “Type 11 Class Exception Conditions” (do not report #AC).
EVEX-encoded instructions, see Table 2-60, “Type E11 Class Exception Conditions.”
EVEX-encoded instructions with broadcast (VCVTPH2PSX), see Table 2-46, “Type E2 Class Exception Conditions.”Additionally:
#UD If VEX.W=1.#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.VCVTPH2QQ—Convert Packed FP16 Values to Signed Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-53VCVTPH2QQ—Convert Packed FP16 Values to Signed Quadword Integer Values
This instruction converts packed FP16 values in the sour ce operand to signed quadword integers in destination 
operand.
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is 
returned.
Operation
VCVTPH2QQ DEST, SRC 
ELSE:
ELSE
DEST.qword[j] := Convert _fp16_to_integer64(tsrc)
DEST.qword[j] := 0
// else dest.qword[j ] remains unchanged
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W0 7B /r
VCVTPH2QQ xmm1{k1}{z}, xmm2/
AVX512VLConvert two packed FP16 values in xmm2/m32/
m16bcst to two signed quadword integers, and 
store the result in xmm1 subject to writemask k1.
EVEX.256.66.MAP5.W0 7B /r
VCVTPH2QQ ymm1{k1}{z}, xmm2/m64/m16bcstA V/V AVX512-FP16 
AVX512VLConvert four packed FP16 values in xmm2/m64/
m16bcst to four signed quadword integers, and store the result in ymm1 subject to writemask k1.
EVEX.512.66.MAP5.W0 7B /r
VCVTPH2QQ zmm1{k1}{z}, xmm2/
m128/m16bcst {er}A V/V AVX512-FP16 Convert eight packed FP16 values in xmm2/
m128/m16bcst to eight signed quadword 
A Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPH2QQ—Convert Packed FP16 Values to Signed Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
5-54 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VCVTPH2QQ __m512i _mm512_cvt_roundph_epi64 (__m128h a, int rounding);
VCVTPH2QQ __m512i _mm512_mask_cvt_roundph_epi64 (__m512i src, __mmask8 k, __m128h a, int rounding);VCVTPH2QQ __m512i _mm512_maskz _cvt_roundph_epi64 (__mmask8 k, __m128h a, int rounding);
VCVTPH2QQ __m128i _mm_cvtph_epi64 (__m128h a);VCVTPH2QQ __m128i _mm_mask_c vtph_epi64 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m128i _mm_maskz_cvtph_epi64 (__mmask8 k, __m128h a);VCVTPH2QQ __m256i _mm256_cvtph_epi64 (__m128h a);VCVTPH2QQ __m256i _mm256_mask_cvtph_epi64 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m256i _mm256_maskz_cvtph_epi64 (__mmask8 k, __m128h a);VCVTPH2QQ __m512i _mm512_cvtph_epi64 (__m128h a);VCVTPH2QQ __m512i _mm512_mask_cvtph_epi64 (__m512i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m512i _mm512_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTPH2UDQ—Convert Packed FP16 Values to Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-55VCVTPH2UDQ—Convert Packed FP16 Values to Unsigned Doubleword Integers
This instruction converts packed FP16 values in the sour ce operand to unsigned doubleword integers in destination 
operand.
Operation
VCVTPH2UDQ DEST, SRC 
ELSE:
ELSE
tsrc := SRC.fp16[j]DEST.dword[j] := Con vert_fp16_to_unsigned_integer32(tsrc)
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W0 79 /r
VCVTPH2UDQ xmm1{k1}{z}, xmm2/
m16bcst to four unsigned doubleword integers, 
and store the result in xmm1 subject to 
EVEX.256.NP.MAP5.W0 79 /r
VCVTPH2UDQ ymm1{k1}{z}, xmm2/
m128/m16bcst to eight unsigned doubleword 
EVEX.512.NP.MAP5.W0 79 /r
VCVTPH2UDQ zmm1{k1}{z}, ymm2/
m256/m16bcst to sixteen unsigned doubleword 
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPH2UDQ—Convert Packed FP16 Values to Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, V
5-56 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UDQ __m512i _mm512_cvt_roundph_epu32 (__m256h a, int rounding);
VCVTPH2UDQ __m512i _mm512_mask_cvt_ roundph_epu32 (__m512i src, __mmask 16 k, __m256h a,  int rounding);
VCVTPH2UDQ __m512i _mm512_maskz_cvt_roundph_epu 32 (__mmask16 k, __m256h a, int rounding);
VCVTPH2UDQ __m128i _mm_cvtph_epu32 (__m128h a);VCVTPH2UDQ __m128i _mm_mask_cvtph_epu32 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2UDQ __m128i _mm_maskz_cvtph_epu32 (__mmask8 k, __m128h a);VCVTPH2UDQ __m256i _mm256_cvtph_epu32 (__m128h a);VCVTPH2UDQ __m256i _mm256_mask_cvtph_epu3 2 (__m256i src, __mma sk8 k, __m128h a);

VCVTPH2UDQ __m256i _mm256_maskz_cvtph_epu32 (__mmask8 k, __m128h a);VCVTPH2UDQ __m512i _mm512_cvtph_epu32 (__m256h a);VCVTPH2UDQ __m512i _mm512_mask_cvtph_epu3 2 (__m512i src, __mma sk16 k, __m256h a);
VCVTPH2UDQ __m512i _mm512_maskz_cvtph_epu32 (__mmask16 k, __m256h a);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTPH2UQQ—Convert Packed FP16 Values  to Unsigned Quadword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-57VCVTPH2UQQ—Convert Packed FP16 Values  to Unsigned Quadword Integers
This instruction converts packed FP16 values in the sour ce operand to unsigned quadwo rd integers in destination 
operand.
returned.
Operation
VCVTPH2UQQ DEST, SRC 
ELSE:
ELSE
DEST.qword[j] := Con vert_fp16_to_unsigned_integer64(tsrc)
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W0 79 /r
VCVTPH2UQQ xmm1 {k1}{z}, xmm2/
m16bcst to two unsigned quadword integers, and 
EVEX.256.66.MAP5.W0 79 /r
VCVTPH2UQQ ymm1{k1}{z}, xmm2/m64/m16bcstA V/V AVX512-FP16 
m16bcst to four unsign ed quadword integers, 
and store the result in ymm1 subject to 
EVEX.512.66.MAP5.W0 79 /r
VCVTPH2UQQ zmm1{k1}{z}, xmm2/m128/m16bcst {er}A V/V AVX512-FP16 Convert eight packed FP16 values in xmm2/
m128/m16bcst to eight unsigned quadword integers, and store the resu lt in zmm1 subject to 
A Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPH2UQQ—Convert Packed FP16 Values to Unsigned Quadword IntegersINSTRUCTION SET REFERENCE, V
5-58 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UQQ __m512i _mm512_cvt_roundph _epu64 (__m128h a, int rounding);
VCVTPH2UQQ __m512i _mm512_mask_cvt_roundph_epu64 (__m 512i src, __mmask8 k, __m128h a, int rounding);
VCVTPH2UQQ __m512i _mm512_maskz _cvt_roundph_epu64 (__mmask8 k, __m128h a, int rounding);
VCVTPH2UQQ __m128i _mm_cvtph_epu64 (__m128h a);VCVTPH2UQQ __m128i _mm_mask_cvtph_epu64  (__m128i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m128i _mm_maskz_cvtph_ epu64 (__mmask8 k, __m128h a);
VCVTPH2UQQ __m256i _mm256_cvtph_epu64 (__m128h a);VCVTPH2UQQ __m256i _mm256_mask_cvtph_epu6 4 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m256i _mm256_maskz_cvt ph_epu64 (__mmask8 k, __m128h a);
VCVTPH2UQQ __m512i _mm512_cvtph_epu64 (__m128h a);VCVTPH2UQQ __m512i _mm512_mask_cvtph_epu6 4 (__m512i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m512i _mm512_maskz_cvt ph_epu64 (__mmask8 k, __m128h a);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTPH2UW—Convert Packed FP16 Values to Unsigned Word IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-59VCVTPH2UW—Convert Packed FP16 Valu es to Unsigned Word Integers
This instruction converts packed FP16 values in the sour ce operand to unsigned word integers in the destination 
operand.
Operation
VCVTPH2UW DEST, SRC 
VL = 128, 256 or 512KL := VL / 16
ELSE:
ELSE
DEST.word[j] := Convert_fp16_to_unsigned_integer16(tsrc)
DEST.word[j] := 0
// else dest.word[j] remains unchanged
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W0 7D /r
VCVTPH2UW xmm1{k1}{z}, xmm2/
AVX512VLConvert packed FP16 values in xmm2/m128/
m16bcst to unsigned word  integers, and store the 
EVEX.256.NP.MAP5.W0 7D /r
VCVTPH2UW ymm1{k1}{z}, ymm2/m256/m16bcstA V/V AVX512-FP16 
AVX512VLConvert packed FP16 values in ymm2/m256/
EVEX.512.NP.MAP5.W0 7D /r
VCVTPH2UW zmm1{k1}{z}, zmm2/
m512/m16bcst {er}A V/V AVX512-FP16 Convert packed FP16 values in zmm2/m512/
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPH2UW—Convert Packed FP16 Values to Unsigned Word IntegersINSTRUCTION SET REFERENCE, V
5-60 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UW __m512i _mm512_cvt_round ph_epu16 (__m512h a, int sae);
VCVTPH2UW __m512i _mm512_mask_cvt_roundph_epu16 (_ _m512i src, __mmask32 k, __m512h a, int sae);
VCVTPH2UW __m512i _mm512_maskz_cvt_roundph_e pu16 (__mmask32 k, __m512h a, int sae);
VCVTPH2UW __m128i _mm_cvtph_epu16 (__m128h a);VCVTPH2UW __m128i _mm_mask_cvtph_epu16 ( __m128i src, __mmask8 k, __m128h a);
VCVTPH2UW __m128i _mm_maskz_cvtph_epu16 (__mmask8 k, __m128h a);VCVTPH2UW __m256i _mm256_cvtph_epu16 (__m256h a);VCVTPH2UW __m256i _mm256_mask_cvtph_epu16 (__m256i src, __mmask16 k, __m256h a);
VCVTPH2UW __m256i _mm256_maskz_cvtph _epu16 (__mmask16 k, __m256h a);
VCVTPH2UW __m512i _mm512_cvtph_epu16 (__m512h a);VCVTPH2UW __m512i _mm512_mask_cvtph_epu16 (__m512i src, __mmask32 k, __m512h a);
VCVTPH2UW __m512i _mm512_maskz_cvtph _epu16 (__mmask32 k, __m512h a);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTPH2W—Convert Packed FP16 Values to Signed Word IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-61VCVTPH2W—Convert Packed FP16 Valu es to Signed Word Integers
This instruction converts packed FP16 values in the source operand to signed word integers in the destination 
operand.
Operation
VCVTPH2W DEST, SRC
ELSE:
ELSE
DEST.word[j] := Convert_fp16_to_integer16(tsrc)
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W0 7D /r
VCVTPH2W xmm1{k1}{z}, xmm2/
m16bcst to signed word integers, and store the 
EVEX.256.66.MAP5.W0 7D /r
VCVTPH2W ymm1{k1}{z}, ymm2/m256/m16bcstA V/V AVX512-FP16 
EVEX.512.66.MAP5.W0 7D /r
VCVTPH2W zmm1{k1}{z}, zmm2/
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPH2W—Convert Packed FP16 Values to Signed Word IntegersINSTRUCTION SET REFERENCE, V
5-62 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VCVTPH2W __m512i _mm512_cvt_roundph _epi16 (__m512h a, int rounding);
VCVTPH2W __m512i _mm512_mask_cvt_ro undph_epi16 (__m512i src, __mmask 32 k, __m512h a, int rounding);

VCVTPH2W __m512i _mm512_maskz_cvt_roundph_epi 16 (__mmask32 k, __m512h a, int rounding);
VCVTPH2W __m128i _mm_cvtph_epi16 (__m128h a);VCVTPH2W __m128i _mm_mask_cvtph_epi16 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2W __m128i _mm_maskz_cvtph_epi16 (__mmask8 k, __m128h a);VCVTPH2W __m256i _mm256_cvtph_epi16 (__m256h a);VCVTPH2W __m256i _mm256_mask_cvtph_epi16 (__m256i src, __mmask16 k, __m256h a);
VCVTPH2W __m256i _mm256_maskz_cvtph_epi16 (__mmask16 k, __m256h a);VCVTPH2W __m512i _mm512_cvtph_epi16 (__m512h a);VCVTPH2W __m512i _mm512_mask_cvtph_epi16 (__m512i src, __mmask32 k, __m512h a);
VCVTPH2W __m512i _mm512_maskz_cvtph_epi16 (__mmask32 k, __m512h a);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-63VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP Value
Convert packed single-precision floating values in the so urce operand to half-precision (16-bit) floating-point 
values and store to the destination operand. The round ing mode is specified using the immediate field (imm8).
Underflow results (i.e., tiny results) are converted to de normals. MXCSR.FTZ is ignored. If a source element is 
denormal relative to the input format with DM masked an d at least one of PM or UM unmasked; a SIMD exception 
will be raised with DE, UE and PE set.
The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC 
field are listed in Table 5-13.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m64, xmm2, 
imm8A V/V F16C Convert four packed single-precision floating-point values 
in xmm2 to packed half-preci sion (16-bit) floating-point 
values in xmm1/m64.  Imm8 provides rounding controls.
VEX.256.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m128, ymm2, imm8A V/V F16C Convert eight packed single-precision floating-point values 
in ymm2 to packed half-preci sion (16-bit) floating-point 
values in xmm1/m128. Imm8 provides rounding controls.
EVEX.128.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m64 {k1}{z}, 
xmm2, imm8BV / V A V X 5 1 2 V L
AVX512FConvert four packed single-precision floating-point values 
EVEX.256.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m128 {k1}{z}, 
ymm2, imm8BV / V A V X 5 1 2 V L
AVX512FConvert eight packed single-precision floating-point values 
EVEX.512.66.0F3A.W0 1D /r ib
VCVTPS2PH ymm1/m256 {k1}{z}, 
zmm2{sae}, imm8B V/V AVX512F Convert sixteen packed single-precision floating-point 
values in zmm2 to packed half -precision (16-bit) floating-
point values in ymm1/m256. Imm8 provides rounding 
controls.
B Half Mem ModRM:r/m (w) ModRM:reg (r) imm8 N/A
Figure 5-7.  VCVTPS 2PH (128-bit Version)VH0 VH1 VH2 VH315             0 31           16 47           32 63           48 95                                64 127                              96VS0 VS1 VS2 VS331                                  0 63                                32 95                                64 127                              96
xmm1/mem64xmm2VCVTPS2PH xmm1/mem64, xmm2,  imm8
convertconvertconvertconvertVCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP ValueINSTRUCTION SET REFERENCE, V
5-64 Vol. 2CVEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit 
memory location. If the destination operand is a regist er then the upper bits (MAX VL-1:64) of corresponding 
VEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit 
memory location. If the destination operand is a register , the upper bits (MAXVL-1:128) of the corresponding desti-
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).EVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a 
YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask 
k1. Bits (MAXVL-1:256/128/64) of the corresponding destination register are zeroed.
Operation
vCvt_s2h(SRC1[31:0])
{IF Imm[2] = 0THEN ; using Imm[1:0] for rounding control, see Table 5-13
RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);
ELSE ; using MXCSR.RC for rounding control
RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);
FI;}
VCVTPS2PH (EVEX Encoded Versions) When DEST is a Register
i := j * 16k := j * 32IF k1[j] OR *no writemask*
THEN DEST[i+15:i] :=
vCvt_s2h(SRC[k+31:k])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0Table 5-13. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions
Imm[7:3] Ignored Ignored by processorVCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-65VCVTPS2PH (EVEX Encoded Versions) When DEST is Memory
ELSE 
*DEST[i+15:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VCVTPS2PH (VEX.256 Encoded Version)
DEST[15:0] := vCvt_s2h(SRC1[31:0]);DEST[31:16] := vCvt_s2h(SRC1[63:32]);DEST[47:32] := vCvt_s2h(SRC1[95:64]);DEST[63:48] := vCvt_s2h(SRC1[127:96]);DEST[79:64] := vCvt_s2h(SRC1[159:128]);DEST[95:80] := vCvt_s2h(SRC1[191:160]);DEST[111:96] := vCvt_s2h(SRC1[223:192]);DEST[127:112] := vCvt_s2h(SRC1[255:224]);DEST[MAXVL-1:128] := 0
VCVTPS2PH (VEX.128 Encoded Version) 
DEST[15:0] := vCvt_s2h(SRC1[31:0]);DEST[31:16] := vCvt_s2h(SRC1[63:32]);DEST[47:32] := vCvt_s2h(SRC1[95:64]);DEST[63:48] := vCvt_s2h(SRC1[127:96]);DEST[MAXVL-1:64] := 0
None.
VCVTPS2PH __m256i _mm512_cvtps_ph(__m512 a);
VCVTPS2PH __m256i _mm512_mask_cvtps_ ph(__m256i s, __mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_maskz_c vtps_ph(__mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_cvt_round ps_ph(__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_mask_cvt_roundps_ph(__m2 56i s, __mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_maskz_cvt_roundps _ph(__mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m128i _mm256_mask_cvtps_ph(__m128i s, __mmask8 k,__m256 a);VCVTPS2PH __m128i _mm256_maskz_cvtps_ph(__mmask8 k,__m256 a);VCVTPS2PH __m128i _mm_mask_cvtps_p h(__m128i s, __mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_maskz_cv tps_ph(__mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_cvtps_ph  ( __m128 m1, const int imm);
VCVTPS2PH __m128i _mm256_cvtps_ph(__m256 m1, const int imm);
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0).VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP ValueINSTRUCTION SET REFERENCE, V
5-66 Vol. 2COther Exceptions
VEX-encoded instructions, see Table 2-26, “Type 11 Class Exception Conditions” (do not report #AC); 
#UD If VEX.W=1.
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.VCVTPS2PHX—Convert Packed Single Precision Floating-Point Values to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-67VCVTPS2PHX—Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
This instruction converts packed single precision floating va lues in the source operand to FP16 values and stores to 
The VCVTPS2PHX instruction supports broadcasting. This instruction uses MXCSR.DAZ for handling FP32 inputs. FP16 outputs can be normal or denormal numbers, and 
are not conditionally flushed based on MXCSR settings.
Operation
VCVTPS2PHX DEST, SRC (AVX512_FP16 Load Version With Broadcast Support)
VL = 128, 256, or 512KL := VL / 32
IF *SRC is a register* and (VL == 512) and (EVEX.b = 1):
ELSE:
tsrc := SRC.fp32[0]
ELSE
tsrc := SRC.fp32[j]
DEST.fp16[j] := Convert_fp32_to_fp16(tsrc)
DEST[MAXVL-1:VL/2] := 0 Opcode/

Operation
ELSE:
ELSE
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W0  1D /r
VCVTPS2PHX  xmm1{k1}{z},  
xmm2/m128/m32bcstA V/V AVX512-FP16
AVX512VLConvert four packed single precision floating-
point values in xmm2/m128/m32bcst to packed 
EVEX.256.66.MAP5.W0  1D /r
ymm2/m256/m32bcstA V/V AVX512-FP16
AVX512VLConvert eight packed sing le precision floating-
point values in ymm2/m256/m32bcst to packed 
EVEX.512.66.MAP5.W0  1D /r
VCVTPS2PHX  ymm1{k1}{z},  
zmm2/m512/m32bcst  {er}A V/V AVX512-FP16 Convert sixteen packed single precision floating-
point values in zmm2 /m512/m32bcst to packed 
FP16 values, and store the result in ymm1 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPS2PHX—Convert Packed Single Precision Floating-Point Values to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-68 Vol. 2CFlags Affected
None.
VCVTPS2PHX __m256h _mm512_cvtx_roundps_ph (__m512 a, int rounding);
VCVTPS2PHX __m256h _mm512_mask_cvtx_roundps_ph (__m 256h src, __mmask16 k, __m512 a, int rounding);
VCVTPS2PHX __m256h _mm512_maskz_cvtx_roundps _ph (__mmask16 k, __m512 a, int rounding);
VCVTPS2PHX __m128h _mm_cvtxps_ph (__m128 a);VCVTPS2PHX __m128h _mm_mask_cvtxps_ph (__m128h src, __mmask8 k, __m128 a);
VCVTPS2PHX __m128h _mm_maskz_cvtxps_ph (__mmask8 k, __m128 a);VCVTPS2PHX __m128h _mm256_cvtxps_ph (__m256 a);VCVTPS2PHX __m128h _mm256_mask_cvtxps_ph  (__m128h src, __mmask8 k, __m256 a);
VCVTPS2PHX __m128h _mm256_maskz_cvtxps_ph (__mmask8 k, __m256 a);VCVTPS2PHX __m256h _mm512_cvtxps_ph (__m512 a);VCVTPS2PHX __m256h _mm512_mask_cvtxps_ph (__m256h src, __mmask16 k, __m512 a);
VCVTPS2PHX __m256h _mm512_maskz_cvtxps_ph (__mmask16 k, __m512 a);
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0).
#UD If VEX.W=1.#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.VCVTPS2QQ—Convert Packed Single Precision Floating-Poi nt Values to Packed Signed Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-69VCVTPS2QQ—Convert Packed Sing le Precision Floating-Point Values to Packed Signed 
Quadword Integer Values
Converts eight packed single precision floating-point valu es in the source operand to eight signed quadword inte-
gers in the destination operand.
The source operand is a YMM/XMM/XMM (low 64- bits) regi ster or a 256/128/64-bit memory location. The destina-
tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1. 
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Register
THEN
ELSE 
Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
ELSE 
FIOpcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F.W0 7B /r
VCVTPS2QQ xmm1 {k1}{z}, 
xmm2/m64/m32bcstAV / V A V X 5 1 2 V L
AVX512DQConvert two packed single precision floating-point values from 
xmm2/m64/m32bcst to two packed signed quadword values in 
EVEX.256.66.0F.W0 7B /r
VCVTPS2QQ ymm1 {k1}{z}, 
xmm2/m128/m32bcstAV / V A V X 5 1 2 V L
AVX512DQConvert four packed single precision floating-point values from 
xmm2/m128/m32bcst to four packed signed quadword values 
in ymm1 subject to writemask k1.
EVEX.512.66.0F.W0 7B /r
VCVTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er}A V/V AVX512DQ Convert eight packed single precision floating-point values from 
ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 subject to writemask k1.
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPS2QQ—Convert Packed Single Precision Floating-Poi nt Values to Packed Signed Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
5-70 Vol. 2CFI;
ENDFOR
VCVTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Single_Precision_To_QuadInteger(SRC[31:0])
ELSE 
Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])FI;
ELSE 
FI
FI;
ENDFOR
VCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a);
VCVTPS2QQ __m512i _mm512_mask_cvtps_epi 64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a);VCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r);VCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r);VCVTPS2QQ __m512i _mm512_maskz_cvt_roundps _epi64( __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a);VCVTPS2QQ __m256i _mm256_mask_cvtps_epi 64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a);VCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a);VCVTPS2QQ __m128i _mm_mask_cvtps_epi64 ( __m128i s, __mmask8 k, __m128 a);
VCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
Additionally:#UD If EVEX.vvvv != 1111B.VCVTPS2UDQ—Convert Packed Single Precision Floating-Point  Values to Packed Unsigned Doubleword Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-71VCVTPS2UDQ—Convert Packed Sing le Precision Floating-Point Values to Packed Unsigned 
Converts sixteen packed single precision floating-point values in the source operand to sixteen unsigned double-
word integers in the destination operand.
updated with writemask k1. 
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.0F.W0 79 /r
VCVTPS2UDQ xmm1 {k1}{z}, 
xmm2/m128/m32bcstA V/V AVX512VL
unsigned doubleword valu es in xmm1 subject to 
EVEX.256.0F.W0 79 /r
VCVTPS2UDQ ymm1 {k1}{z}, 
ymm2/m256/m32bcstA V/V AVX512VL
values from ymm2/m256/m32bcst to eight packed 
unsigned doubleword valu es in ymm1 subject to 
EVEX.512.0F.W0 79 /r
VCVTPS2UDQ zmm1 {k1}{z}, 
zmm2/m512/m32bcst{er}A V/V AVX512F Convert sixteen packed single precision floating-point 
unsigned doubleword valu es in zmm1 subject to 
AF u l l M o d R M : r e g  ( w )M odRM:r/m (r) N/A N/AVCVTPS2UDQ—Convert Packed Single Precision Floating-Point  Values to Packed Unsigned Doubleword Integer ValuesINSTRUCTION SET REFERENCE, V
5-72 Vol. 2COperation
VCVTPS2UDQ (EVEX Encoded Versions) When SRC Operand is a Register
THEN
ELSE

THEN
ELSE 
FI;
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
ELSE 
FI
FI;
ENDFOR
VCVTPS2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
i := j * 32IF k1[j] OR *no *
THEN 
THEN
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0])
ELSE 
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])FI;
ELSE 
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] :=  0VCVTPS2UDQ—Convert Packed Single Precision Floating-Point  Values to Packed Unsigned Doubleword Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-73Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UDQ __m512i _mm512 _cvtps_epu32( __m512 a);
VCVTPS2UDQ __m512i _mm512_mask_cvtps_epu 32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_maskz_cvt ps_epu32( __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_cvt_roundps_epu32( __m512 a, int r);VCVTPS2UDQ __m512i _mm512_mask_cvt_roundps_epu32 ( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_maskz_cvt_round ps_epu32( __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m256i _mm256_cvtps_epu32( __m256d a);VCVTPS2UDQ __m256i _mm256_mask_cvtps_ep u32( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UDQ __m256i _mm256_maskz_cvtps_epu32( __mmask8 k, __m256 a);VCVTPS2UDQ __m128i _mm_cvtps_epu32( __m128 a);VCVTPS2UDQ __m128i _mm_mask_cvtps_epu 32( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UDQ __m128i _mm_maskz_cvtps_epu32( __mmask8 k, __m128 a);
#UD If EVEX.vvvv != 1111B.VCVTPS2UQQ—Convert Packed Single Precision Floating-Poi nt Values to Packed Unsigned Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
5-74 Vol. 2CVCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned 
Converts up to eight packed single precision floating-p oint values in the source operand to unsigned quadword 
integers in the destination operand.
Operation
VCVTPS2UQQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)IF (VL == 512) AND (EVEX.b == 1) 
THEN
ELSE 
Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
ELSE 
FIOpcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F.W0 79 /r
VCVTPS2UQQ xmm1 {k1}{z}, 
xmm2/m64/m32bcstA V/V AVX512VL
zmm2/m64/m32bcst to two packed unsigned quadword values 
in zmm1 subject to writemask k1.
EVEX.256.66.0F.W0 79 /r
VCVTPS2UQQ ymm1 {k1}{z}, 
xmm2/m128/m32bcst to four packed unsigned quadword 
values in ymm1 subj ect to writemask k1.
EVEX.512.66.0F.W0 79 /r
VCVTPS2UQQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er}A V/V AVX512DQ Convert eight packed single precision floating-point values from 
ymm2/m256/m32bcst to eight packed unsigned quadword values in zmm1 subject to writemask k1.
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTPS2UQQ—Convert Packed Single Prec ision Floating-Point Values to Pack ed Unsigned Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-75FI;
ENDFOR
VCVTPS2UQQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Single_Precision_To _UQuadInteger(SRC[31:0])
ELSE 
Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])FI;
ELSE 
FI
FI;
ENDFOR
VCVTPS2UQQ __m512i _mm512_cvtps_epu64( __m512 a);
VCVTPS2UQQ __m512i _mm512_mask_cvtps_epu6 4( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_maskz_c vtps_epu64( __mmask 16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_cvt_r oundps_epu64( __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_mask_cvt_roundps_epu6 4( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_maskz_cvt_roundps _epu64( __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m256i _mm256_cvtps_epu64( __m256 a);VCVTPS2UQQ __m256i _mm256_mask_cvtps_epu64( __m256i s, __mmask8 k, __m256 a);VCVTPS2UQQ __m256i _mm256_maskz_cvt ps_epu64( __mmask8 k, __m256 a);
VCVTPS2UQQ __m128i _mm_cvtps_epu64( __m128 a);VCVTPS2UQQ __m128i _mm_mask_cvtps_epu 64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UQQ __m128i _mm_maskz_cvtp s_epu64( __mmask8 k, __m128 a);
Additionally:#UD If EVEX.vvvv != 1111B.VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-76 Vol. 2CVCVTQQ2PD—Convert Packed Quadword Integers to Packed Double Precision Floating-Point 
Values
Converts packed quadword integers in the source operan d (second operand) to packed double precision floating-
point values in the destination operand (first operand). 
The source operand is a ZMM/YMM/XMM register or a 512 /256/128-bit memory location. The destination operation 
Operation
VCVTQQ2PD (EVEX2 Encoded Versions) When SRC Operand is a Register
THEN
ELSE 
FI;
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.F3.0F.W1 E6 /r
VCVTQQ2PD xmm1 {k1}{z}, 
AVX512DQConvert two packed quadword integers from 
xmm2/m128/m64bcst to packed double precision floating-
point values in xmm1  with writemask k1.
EVEX.256.F3.0F.W1 E6 /r
VCVTQQ2PD ymm1 {k1}{z}, 
AVX512DQConvert four packed quadword integers from 
ymm2/m256/m64bcst to packed double precision floating-
EVEX.512.F3.0F.W1 E6 /r
VCVTQQ2PD zmm1 {k1}{z}, zmm2/m512/m64bcst{er}A V/V AVX512DQ Convert eight pack ed quadword in tegers from 
zmm2/m512/m64bcst to eight packed double precision floating-point values in zmm1 with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTQQ2PD—Convert Packed Quadword Integers to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-77VCVTQQ2PD (EVEX Encoded Versions) when SRC Operand is a Memory Source
THEN 
THEN
Convert_QuadInteger_To_Double_Pre cision_Floating_ Point(SRC[63:0])
ELSE 

THEN 
THEN
ELSE 
Convert_QuadInteger_To_Double_Preci sion_Floating_Point(SRC[i+63:i])
FI;
ELSE 
FI
FI;
VCVTQQ2PD __m512d _mm512_cvtepi64_pd( __m512i a);
VCVTQQ2PD __m512d _mm512_mask_cvtepi64_pd( __m512d s, __mmask16 k, __m512i a);VCVTQQ2PD __m512d _mm512_maskz_cvtepi64_pd( __mmask16 k, __m512i a);VCVTQQ2PD __m512d _mm512_cvt_roundepi64_pd( __m512i a, int r);VCVTQQ2PD __m512d _mm512_mask_cvt_roundepi64_pd(  __m512d s, __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m512d _mm512_maskz_cvt_roundep i64_pd( __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m256d _mm256_mask_cvtepi64_pd( __m256d s, __mmask8 k, __m256i a);VCVTQQ2PD __m256d _mm256_maskz_cvtep i64_pd( __mmask8 k, __m256i a);
VCVTQQ2PD __m128d _mm_mask_cvtepi64_pd ( __m128d s, __mmask8 k, __m128i a);
VCVTQQ2PD __m128d _mm_maskz_cvte pi64_pd( __mmask8 k, __m128i a);
Additionally:#UD If EVEX.vvvv != 1111B.VCVTQQ2PH—Convert Packed Signed Quadword Integers to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-78 Vol. 2CVCVTQQ2PH—Convert Packed Signed Quad word Integers to Packed FP16 Values
This instruction converts packed signed quadword integers in the source operand to packed FP16 values in the desti-
nation operand. The destination elements  are updated according to the writemask.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.If the result of the convert operation is overflow and MX CSR.OM=0 then a SIMD exception will be raised with OE=1, 
PE=1.
Operation
VCVTQQ2PH DEST, SRC 
ELSE:
tsrc := SRC.qword[0]
ELSE
tsrc := SRC.qword[j]
DEST.fp16[j] := Convert_ integer64_to_fp16(tsrc)
DEST[MAXVL-1:VL/4] := 0 Opcode/
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W1 5B /r
VCVTQQ2PH xmm1{k1}{z}, xmm2/
AVX512VLConvert two packed signed  quadword integers in 
xmm2/m128/m64bcst to packed FP16 values, 
EVEX.256.NP.MAP5.W1 5B /r
VCVTQQ2PH xmm1{k1}{z}, ymm2/
AVX512VLConvert four packed signed quadword integers in 
ymm2/m256/m64bcst to packed FP16 values, 
EVEX.512.NP.MAP5.W1 5B /r
VCVTQQ2PH xmm1{k1}{z}, zmm2/
m512/m64bcst {er}A V/V AVX512-FP16 Convert eight packed signed quadword integers in 
zmm2/m512/m64bcst to packed FP16 values, 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTQQ2PH—Convert Packed Signed Quadword Integers to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-79Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PH __m128h _mm512_cvt_roundepi64_ph (__m512i a, int rounding);
VCVTQQ2PH __m128h _mm512_mask_cvt_roundepi64_ph (__m128h src, __mmask8 k, __m512i a, int rounding);VCVTQQ2PH __m128h _mm512_maskz_cvt_roundepi6 4_ph (__mmask8 k, __m512i a, int rounding);
VCVTQQ2PH __m128h _mm_cvtepi64_ph (__m128i a);VCVTQQ2PH __m128h _mm_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m128i a);VCVTQQ2PH __m128h _mm_maskz_cvtepi64_ph (__mmask8 k, __m128i a);VCVTQQ2PH __m128h _mm256_cvtepi64_ph (__m256i a);VCVTQQ2PH __m128h _mm256_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m256i a);
VCVTQQ2PH __m128h _mm256_maskz_cvtepi64_ph (__mmask8 k, __m256i a);VCVTQQ2PH __m128h _mm512_cvtepi64_ph (__m512i a);VCVTQQ2PH __m128h _mm512_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m512i a);
VCVTQQ2PH __m128h _mm512_maskz_cvtepi64_ph (__mmask8 k, __m512i a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-80 Vol. 2CVCVTQQ2PS—Convert Packed Quadword Integers to Packed Single Precision Floating-Point 
Values
Converts packed quadword integers in the source operan d (second operand) to packed single precision floating-
is a YMM/XMM/XMM (lower 64 bits) register  conditionally updated with writemask k1. 
Operation
VCVTQQ2PS (EVEX Encoded Versions) When SRC Operand is a Register
THEN DEST[k+31:k] :=
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
ELSE 
THEN *DEST[k+31:k] remains unchanged*ELSE ; zeroing-masking
DEST[k+31:k] := 0
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.0F.W1 5B /r
VCVTQQ2PS xmm1 {k1}{z}, 
AVX512DQConvert two packed quadword integers from xmm2/mem to 
packed single precision floating-point values in xmm1 with 
EVEX.256.0F.W1 5B /r
AVX512DQConvert four packed quadword integers from ymm2/mem to 
EVEX.512.0F.W1 5B /r
VCVTQQ2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er}A V/V AVX512DQ Convert eight packed quad word integers from zmm2/mem to 
eight packed single precision floating-point values in ymm1 with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTQQ2PS—Convert Packed Quadword Integers to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-81VCVTQQ2PS (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
DEST[k+31:k] :=
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE 
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])FI;
ELSE 
FI
FI;
VCVTQQ2PS __m256 _mm512_cvtepi64_ps( __m512i a);
VCVTQQ2PS __m256 _mm512_mask_cvtepi64_p s( __m256 s, __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_maskz_cvt epi64_ps( __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_cvt_rou ndepi64_ps( __m512i a, int r);
VCVTQQ2PS __m256 _mm512_mask_cvt_roundepi_ps( __m256 s, __mmask8 k, __m512i a, int r);VCVTQQ2PS __m256 _mm512_maskz_cvt_roundep i64_ps( __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m128 _mm256_cvtepi64_ps( __m256i a);VCVTQQ2PS __m128 _mm256_mask_cvtepi64_p s( __m128 s, __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm256_maskz_cvt epi64_ps( __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm_cvtepi64_ps( __m128i a);VCVTQQ2PS __m128 _mm_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m128i a);VCVTQQ2PS __m128 _mm_maskz_cvtepi 64_ps( __mmask8 k, __m128i a);
Additionally:#UD If EVEX.vvvv != 1111B.VCVTSD2SH—Convert Low FP64 Value to an FP16 ValueINSTRUCTION SET REFERENCE, V
5-82 Vol. 2CVCVTSD2SH—Convert Low FP64 Value to an FP16 Value
This instruction converts the low FP64 value in the second so urce operand to an FP16 value, and stores the result in 
the low element of the destination operand.
When the conversion is inexact, the value returned is ro unded according to the rounding control bits in the MXCSR 
register.
MAXVL-1:128 of the destination operand are zeroed. The lo w FP16 element of the destin ation is updated according 
Operation
VCVTSD2SH dest, src1, src2 
IF *SRC2 is a register* and (EVEX.b = 1):
ELSE:
DEST.fp16[0] := Convert_ fp64_to_fp16(SRC2.fp64[0])
// else dest.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0 

register.
Operation
ELSE:
VCVTSD2SH __m128h _mm_cvt_roundsd_sh (__m128h a, __m128d b, const int rounding);
VCVTSD2SH __m128h _mm_mask_cvt_roundsd_sh (__m128h src, __ mmask8 k, __m128h a, __m128d b, const int rounding);
VCVTSD2SH __m128h _mm_maskz_cvt_roundsd_sh (__mmask8 k, __m128h a, __m128d b, const int rounding);VCVTSD2SH __m128h _mm_cvtsd_sh (__m128h a, __m128d b);VCVTSD2SH __m128h _mm_mask_cvtsd_sh (__m128h src, __mmask8 k, __m128h a, __m128d b);
VCVTSD2SH __m128h _mm_maskz_cvtsd_sh (__mmask8 k, __m128h a, __m128d b);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.F2.MAP5.W1 5A /r
VCVTSD2SH xmm1{k1}{z}, xmm2, 
xmm3/m64 {er}A V/V AVX512-FP16 Convert the low FP64 value in xmm3/m64 to an 
FP16 value and store the result in the low 
element of xmm1 subject to writemask k1. Bits 
127:16 of xmm2 are copied to xmm1[127:16].
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVCVTSD2USI—Convert Scalar Double Precision Floati ng-Point Value to Unsigned Doubleword IntegerINSTRUCTION SET REFERENCE, V
Vol. 2C 5-83VCVTSD2USI—Convert Scalar Double  Precision Floating-Point Va lue to Unsigned Doubleword 
Integer
Converts a double precision floating-point value in th e source operand (the second operand) to an unsigned 
doubleword integer in the destination operand (the first operand). The source operand can be an XMM register or 
a 64-bit memory location. Th e destination operand is a general-purpose register. When the source operand is an 
XMM register, the double precision floating-point value is contained in the low quadword of the register.
Operation
VCVTSD2USI (EVEX Encoded Version)
THEN
ELSE 
THEN DEST[63:0] := Convert_Double_Precisi on_Floating_Point_To_UInteger(SRC[63:0]);
ELSE DEST[31:0] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
FI
VCVTSD2USI unsigned int _mm_cvtsd_u32(__m128d);
VCVTSD2USI unsigned int _mm_cvt_roundsd_u32(__m128d, int r);VCVTSD2USI unsigned __int64 _mm_cvtsd_u64(__m128d);VCVTSD2USI unsigned __int64 _mm_cvt_roundsd_u64(__m128d, int r);
Invalid, Precision.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.F2.0F.W0 79 /r
VCVTSD2USI r32, xmm1/m64{er}A V/V AVX512F Convert one double precision floating-point value from 
xmm1/m64 to one unsigned doubleword integer r32.
EVEX.LLIG.F2.0F.W1 79 /r
VCVTSD2USI r64, xmm1/m64{er}AV / N . E .
1
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instruction behaves as if the W0 version is used.AVX512F Convert one double precision floating-point value from 
xmm1/m64 to one unsigned quadword integer zero-extended into r64.
A Tuple1 Fixed ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTSD2USI—Convert Scalar Double Precision Floati ng-Point Value to Unsigned Doubleword IntegerINSTRUCTION SET REFERENCE, V
5-84 Vol. 2COther Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”VCVTSH2SD—Convert Low FP16 Value to an FP64 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-85VCVTSH2SD—Convert Low FP16 Value to an FP64 Value
This instruction converts the low FP16 element in the seco nd source operand to a FP64 element in the low element 
of the destination operand.
Bits 127:64 of the destination operand are copied from th e corresponding bits of the first source operand. Bits 
MAXVL-1:128 of the destination operand are zeroed. The low FP64 element of the destination is updated according 
Operation
VCVTSH2SD dest, src1, src2 
DEST.fp64[0] := Convert_fp16_to_fp64(SRC2.fp16[0])
DEST.fp64[0] := 0
// else dest.fp64[0]  remains unchanged
DEST[127:64] := SRC1[127:64]
VCVTSH2SD __m128d _mm_cvt_roundsh_sd ( __m128d a, __m128h b, const int sae);
VCVTSH2SD __m128d _mm_mask_cvt_roundsh_sd (__m128d src, __mmask8 k, __m128d a, __m128h b, const int sae);
VCVTSH2SD __m128d _mm_maskz_cvt_roundsh_sd (__mmask8 k, __m128d a, __m128h b, const int sae);VCVTSH2SD __m128d _mm_cvtsh_sd (__m128d a, __m128h b);VCVTSH2SD __m128d _mm_mask_cvtsh_sd (__m128d  src, __mmask8 k, __m128d a, __m128h b);
VCVTSH2SD __m128d _mm_maskz_cvtsh_sd (__mmask8 k, __m128d a, __m128h b);
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 5A /r
VCVTSH2SD xmm1{k 1}{z}, xmm2, 
xmm3/m16 {sae}A V/V AVX512-FP16 Convert  the low FP16 value in  xmm3/m16 to an 
FP64 value and store the result in the low 
127:64 of xmm2 are copied to xmm1[127:64].
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVCVTSH2SI—Convert Low FP16 Value to Signed IntegerINSTRUCTION SET REFERENCE, V
5-86 Vol. 2CVCVTSH2SI—Convert Low FP16 Value to Signed Integer
This instruction converts the low FP16 element in the source operand to a signed integer in the destination general 
format, the floating-point invalid exception is raised, and if  this exception is masked, the integer indefinite value is 
returned.
Operation
VCVTSH2SI dest, src 
IF *SRC is a register* and (EVEX.b = 1):
ELSE:
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16 _to_integer64(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16 _to_integer32(SRC.fp16[0]) 
VCVTSH2SI int _mm_cvt_roundsh_i32 (__m128h a, int rounding);
VCVTSH2SI __int64 _mm_cvt_roundsh_i64 (__m128h a, int rounding);VCVTSH2SI int _mm_cvtsh_i32 (__m128h a);VCVTSH2SI __int64 _mm_cvtsh_i64 (__m128h a);
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 2D /r
VCVTSH2SI r32, xmm1/m16 {er}AV / V
1
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.AVX512-FP16 Convert the low FP16 element in xmm1/m16 to a 
signed integer and store the result in r32.
EVEX.LLIG.F3.MAP5.W1 2D /r
VCVTSH2SI r64, xmm1/m16 {er}A V/N.E. AVX512-FP16 Convert the low FP16 element in xmm1/m16 to a 
signed integer and store the result in r64.
A Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTSH2SS—Convert Low FP16 Value to FP32 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-87VCVTSH2SS—Convert Low FP16 Value to FP32 Value
This instruction converts the low FP16 element in the seco nd source operand to the low FP32 element of the desti-
Bits 127:32 of the destination operand are copied from th e corresponding bits of the first source operand. Bits 
Operation
VCVTSH2SS dest, src1, src2 
DEST.fp32[0] := Convert_fp16_to_fp32(SRC2.fp16[0])
DEST.fp32[0] := 0
// else dest.fp32[0]  remains unchanged
DEST[127:32] := SRC1[127:32]
VCVTSH2SS __m128 _mm_cvt_roundsh_ss ( __m128 a, __m128h b, const int sae);
VCVTSH2SS __m128 _mm_mask_cvt_roundsh_ss (__m128 src, __mmask8 k, __m128 a, __m128h b, const int sae);

Operation
VCVTSH2SS __m128 _mm_maskz_cvt_roundsh_ss (__mmask8 k, __m128 a, __m128h b, const int sae);VCVTSH2SS __m128 _mm_cvtsh_ss (__m128 a, __m128h b);VCVTSH2SS __m128 _mm_mask_cvtsh_ss (__m128 src, __mmask8 k, __m128 a, __m128h b);VCVTSH2SS __m128 _mm_maskz_cvtsh_ss ( __mmask8 k, __m128 a, __m128h b);
En64/32 
Bit Mode 
EVEX.LLIG.NP.MAP6.W0 13 /r
VCVTSH2SS xmm1{k1}{z}, xmm2, 
xmm3/m16 {sae}A V/V AVX512-FP16 Convert the low FP16 element in xmm3/m16 to 
an FP32 value and store in the low element of 
xmm1 subject to writemas k k1. Bits 127:32 of 
xmm2 are copied to xmm1[127:32].
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVCVTSH2USI—Convert Low FP16 Value to Unsigned IntegerINSTRUCTION SET REFERENCE, V
5-88 Vol. 2CVCVTSH2USI—Convert Low FP16 Value to Unsigned Integer
This instruction converts the low FP16 element in the so urce operand to an unsigned integer in the destination 
general purpose register.
returned.
Operation
VCVTSH2USI dest, src
// SET_RM() sets the rounding mode used for this instruction.IF *SRC is a register* and (EVEX.b = 1):
ELSE:
DEST.qword := Convert_fp16_to_ unsigned_integer64(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_ unsigned_integer32(SRC.fp16[0]) 
VCVTSH2USI unsigned int _mm_cvt_roundsh_u32 (__m128h a, int sae);
VCVTSH2USI unsigned __int64 _mm_cvt_roundsh_u64 (__m128h a, int rounding);VCVTSH2USI unsigned int _mm_cvtsh_u32 (__m128h a);VCVTSH2USI unsigned __int64 _mm_cvtsh_u64 (__m128h a);
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 79 /r
VCVTSH2USI r32, xmm1/m16 {er}AV / V
1
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.AVX512-FP16 Convert the low FP16 element in xmm1/m16 to 
an unsigned integer and store the result in r32.
EVEX.LLIG.F3.MAP5.W1 79 /r
VCVTSH2USI r64, xmm1/m16 {er}A V/N.E. AVX512-FP16 Convert the low FP16 element in xmm1/m16 to 
an unsigned integer and store the result in r64.
A Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTSI2SH—Convert a Signed Doubleword/Quadword Integer to an FP16 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-89VCVTSI2SH—Convert a Signed Doubleword /Quadword Integer to an FP16 Value
This instruction converts a signed doubleword integer (or si gned quadword integer if operand size is 64 bits) in the 
second source operand to an FP16 value in the destination op erand. The result is stored in the low word of the desti-
nation operand. When conversion is inexact, the value re turned is rounded according to the rounding control bits 
in the MXCSR register or embedded rounding controls.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and 
destination operands are XMM registers. Bits 127:16 of  the XMM register destination are copied from corre-
sponding bits in the first source operand. Bits MAXVL-1:128 of the destination register are zeroed.
PE=1.
Operation
VCVTSI2SH dest, src1, src2
ELSE:
DEST.fp16[0] := Convert_in teger64_to_fp1 6(SRC2.qword)
ELSE:
DEST.fp16[0] := Convert_in teger32_to_fp1 6(SRC2.dword)
VCVTSI2SH __m128h _mm_cvt_roundi32_sh (__m128h a, int b, int rounding);
VCVTSI2SH __m128h _mm_cvt_roundi64_sh ( __m128h a, __int64 b, int rounding);
VCVTSI2SH __m128h _mm_cvti32_sh (__m128h a, int b);VCVTSI2SH __m128h _mm_cvti64_sh (__m128h a, __int64 b);Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 2A /r
VCVTSI2SH xmm1, xmm2, r32/m32 
{er}AV / V
1
NOTES:
1. Outside of 64b mode, the EVEX.W field is igno red. The instruction behaves as if W=0 was used.AVX512-FP16 Convert the signed doubleword integer in r32/
m32 to an FP16 value and store the result in 
xmm1. Bits 127:16 of xmm2 are copied to 
xmm1[127:16].
EVEX.LLIG.F3.MAP5.W1 2A /r
VCVTSI2SH xmm1, xmm2, r64/m64 
{er}A V/N.E. AVX512-FP16 Convert the signed quadword integer in r64/m64 
to an FP16 value and stor e the result in xmm1. 
Bits 127:16 of xm m2 are copied to 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVCVTSI2SH—Convert a Signed Doubleword/Quadword Integer to an FP16 ValueINSTRUCTION SET REFERENCE, V
5-90 Vol. 2CSIMD Floating-Point Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”VCVTSS2SH—Convert Low FP32 Value to an FP16 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-91VCVTSS2SH—Convert Low FP32 Value to an FP16 Value
This instruction converts the low FP32 value in the second  source operand to a FP16 value in the low element of the 
register.
Operation
VCVTSS2SH dest, src1, src2
ELSE:
DEST.fp16[0] := Convert_fp32_to_fp16(SRC2.fp32[0])
VCVTSS2SH __m128h _mm_cvt_roundss_sh (__m 128h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_mask_cvt_roundss_ sh (__m128h src, __mmask8 k, __m128 h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_maskz_cvt_ro undss_sh (__mmask8 k, __m128h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_cvtss_sh (__m128h a, __m128 b);VCVTSS2SH __m128h _mm_mask_cvtss_sh (__m128h  src, __mmask8 k, __m128h a, __m128 b);
VCVTSS2SH __m128h _mm_mask z_cvtss_sh (__mmask8 k, __m128h a, __m128 b);
En64/32 
Bit Mode 
EVEX.LLIG.NP.MAP5.W0 1D /r
VCVTSS2SH xmm1{k1}{z}, xmm2, 
xmm3/m32 {er}A V/V AVX512-FP16 Convert low FP32 value in xmm3/m32 to an 
FP16 value and store in the low element of 
xmm1 subject to writemask k1. Bits 127:16 from 
xmm2 are copied to xmm1[127:16].
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVCVTSS2USI—Convert Scalar Single Precision Floati ng-Point Value to Unsigned Doubleword IntegerINSTRUCTION SET REFERENCE, V
5-92 Vol. 2CVCVTSS2USI—Convert Scalar Single Precision Fl oating-Point Value to Unsigned Doubleword 
Integer
Converts a single precision floating-poi nt value in the source operand (the second operand) to an unsigned double-
word integer (or unsigned quadword inte ger if operand size is 64 bits) in the destination operand (the first 
operand). The source operand can be an XMM register or a memory location. The destination operand is a general-
purpose register. When the source operand is an XMM regist er, the single precision floating-point value is contained 
in the low doubleword of the register.

Integer
Note: EVEX.vvvv is reserved and must be  1111b, otherwise instructions will #UD.
Operation
VCVTSS2USI (EVEX Encoded Version)
THEN
ELSE 
DEST[63:0] := Convert_Single_Precision _Floating_Point_To_UInteger(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision _Floating_Point_To_UInteger(SRC[31:0]);
FI;
VCVTSS2USI unsigned _mm_cvtss_u32( __m128 a);
VCVTSS2USI unsigned _mm_cvt_roundss_u32( __m128 a, int r);VCVTSS2USI unsigned __int64 _mm_cvtss_u64( __m128 a);VCVTSS2USI unsigned __int64 _mm_cvt_roundss_u64( __m128 a, int r);Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.F3.0F.W0 79 /r
VCVTSS2USI r32, xmm1/m32{er}A V/V AVX512F Convert one single precision floating-point value from 
xmm1/m32 to one unsigned doubleword integer in r32.
EVEX.LLIG.F3.0F.W1 79 /r
VCVTSS2USI r64, xmm1/m32{er}AV / N . E .
1
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instruction behaves as if the W0 version is used.AVX512F Convert one single precision floating-point value from 
xmm1/m32 to one unsigned quadword integer in r64.
A Tuple1 Fixed ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTSS2USI—Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword IntegerINSTRUCTION SET REFERENCE, V
Vol. 2C 5-93SIMD Floating-Point Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”VCVTTPD2QQ—Convert With Truncation Packed Double Precis ion Floating-Point Values to Packed Quadword IntegersINSTRUCTION SET REFERENCE, V
5-94 Vol. 2CVCVTTPD2QQ—Convert With Truncation Packed Do uble Precision Floating-Point Values to 
Packed Quadword Integers
Converts with truncation packed double precision floating-p oint values in the source operand (second operand) to 
packed quadword integers in the de stination operand (first operand). 
EVEX encoded versions: The source operand is a ZMM/Y MM/XMM register or a 512/256/128-bit memory location. 
The destination operand is a Z MM/YMM/XMM register conditionall y updated with writemask k1. 
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be 
represented in the destination format, the floating-point inva lid exception is raised, and if this exception is masked, 
the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.
Operation
VCVTTPD2QQ (EVEX Encoded Version) When SRC Operand is a Register
Convert_Double_Precision_Floating_Point _To_QuadInteger_Trun cate(SRC[i+63:i])
ELSE 
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F.W1 7A /r
VCVTTPD2QQ xmm1 {k1}{z}, 
zmm2/m128/m64bcst to two packed quadword integers in 
zmm1 using truncation  with writemask k1.
EVEX.256.66.0F.W1 7A /r
VCVTTPD2QQ ymm1 {k1}{z}, 
ymm2/m256/m64bcst to four pa cked quadword integers in 
ymm1 using truncation  with writemask k1.
EVEX.512.66.0F.W1 7A /r
VCVTTPD2QQ zmm1 {k1}{z}, zmm2/m512/m64bcst{sae}A V/V AVX512DQ Convert eight packed double precision floating-point values 
from zmm2/m512 to eight packed quadword integers in zmm1 using truncation wi th writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPD2QQ—Convert With Truncation Packed Double Precis ion Floating-Point Values to Packed Quadword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-95VCVTTPD2QQ (EVEX Encoded Version) When SRC Operand is a Memory Source
THEN 
THEN
DEST[i+63:i] := Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[63:0])
ELSE 
DEST[i+63:i] := Convert_Double _Precision_Floating_Point_To_Qua dInteger_Truncate(SRC[i+63:i])
FI;
ELSE 
FI
FI;
VCVTTPD2QQ __m512i _mm512_cvttpd_epi64( __m512d a);
VCVTTPD2QQ __m512i _mm512_mask_cvttpd_epi64( __m512i s, __mmask8 k, __m512d a);VCVTTPD2QQ __m512i _mm512_maskz_cvttpd_epi64( __mmask8 k, __m512d a);VCVTTPD2QQ __m512i _mm512_cvtt_roundpd_epi64( __m512d a, int sae);VCVTTPD2QQ __m512i _mm512_mask_cvtt_roundpd_epi64 ( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_maskz_cvtt_roundpd_epi64( __mmask8 k, __m512d a, int sae);VCVTTPD2QQ __m256i _mm256_mask_cvttpd_epi64( __m256i s, __mmask8 k, __m256d a);VCVTTPD2QQ __m256i _mm256_maskz_cvttpd_epi64( __mmask8 k, __m256d a);VCVTTPD2QQ __m128i _mm_mask_cvttpd_epi64(  __m128i s, __mmask8 k, __m128d a);
VCVTTPD2QQ __m128i _mm_maskz_cvttpd_epi64( __mmask8 k, __m128d a);
Additionally:#UD If EVEX.vvvv != 1111B.VCVTTPD2UDQ—Convert With Truncation Packed Double Precision Fl oating-Point Values to Packed Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, V
5-96 Vol. 2CVCVTTPD2UDQ—Convert With Truncation Packed Do uble Precision Floating-Point Values to 
Packed Unsigned Doubleword Integers
Converts with truncation packed double precision floating-p oint values in the source operand (the second operand) 
to packed unsigned doubleword integers in the destination operand (the first operand). 
the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/ 128-bit memory location, or a 512/256/128-bit vector 
broadcasted from a 64-bit memory location. The destinat ion operand is a YMM/XMM/XMM (low 64 bits) register 
conditionally updated with writemask k1. The upper bits  (MAXVL-1:256) of the corresponding destination are 
zeroed.
Operation
VCVTTPD2UDQ (EVEX Encoded Versions) When SRC2 Operand is a Register
THEN 
DEST[i+31:i] :=Convert_Double_Precision_Floating_Poi nt_To_UInteger_Truncate(SRC[k+63:k])
ELSE 
FI
FI;Opcode
En64/32 
Bit Mode 
Feature 
EVEX.128.0F.W1 78 /r
VCVTTPD2UDQ xmm1 {k1}{z}, 
AVX512FConvert two packed double precision floating-point values 
in xmm2/m128/m64bcst to two unsigned doubleword 
integers in xmm1 using trun cation subject to writemask 
k1.
EVEX.256.0F.W1 78 02 /r
EVEX.512.0F.W1 78 /r
VCVTTPD2UDQ ymm1 {k1}{z}, 
zmm2/m512/m64bcst{sae}A V/V AVX512F Convert eight packed double precision floating-point 
values in zmm2/m512/m64bcst to eight unsigned 
doubleword integers in ymm1 using truncation subject to 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPD2UDQ—Convert With Truncation Packed Double Precision Fl oating-Point Values to Packed Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-97ENDFOR
VCVTTPD2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256),(8, 512)
THEN 
THEN

THEN 
THEN
Convert_Double_Precision_Floating_Poi nt_To_UInteger_Truncate(SRC[63:0])
ELSE 
Convert_Double_Precision_Floating_Poi nt_To_UInteger_Truncate(SRC[k+63:k])
FI;
ELSE 
FI
FI;
VCVTTPD2UDQ __m256i _mm512_cvttpd_epu32( __m512d a);
VCVTTPD2UDQ __m256i _mm512_mask_cvttpd_epu32( __m256i s, __mmask8 k, __m512d a);VCVTTPD2UDQ __m256i _mm512_maskz_cvttpd_epu32( __mmask8 k, __m512d a);VCVTTPD2UDQ __m256i _mm512_cvtt_roundpd_epu32( __m512d a, int sae);VCVTTPD2UDQ __m256i _mm512_mask_cvtt_roundpd_epu 32( __m256i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_maskz_cvtt_roundpd_ epu32( __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m128i _mm256_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m256d a);VCVTTPD2UDQ __m128i _mm256_maskz_cvttpd_epu32( __mmask8 k, __m256d a);VCVTTPD2UDQ __m128i _mm_mask_cvttpd_epu 32( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UDQ __m128i _mm_maskz_cvttpd_epu32( __mmask8 k, __m128d a);
Additionally:#UD If EVEX.vvvv != 1111B.VCVTTPD2UQQ—Convert With Truncation Packed Double Precision Fl oating-Point Values to Packed Unsigned Quadword IntegersINSTRUCTION SET REFERENCE, V
5-98 Vol. 2CVCVTTPD2UQQ—Convert With Truncation Packed Do uble Precision Floating-Point Values to 
Packed Unsigned Quadword Integers
packed unsigned quadword integers in the destination operand (first operand). 
Operation
VCVTTPD2UQQ (EVEX Encoded Versions ) When SRC Operand is a Register
Convert_Double_Precision_Floating_Point _To_UQuadInteger_Truncate(SRC[i+63:i])
ELSE 
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F.W1 78 /r
VCVTTPD2UQQ xmm1 {k1}{z}, 
AVX512DQConvert two packed double precision floating-point values 
from xmm2/m128/m64bcst to two packed unsigned 
quadword integers in xmm1 using truncation with writemask k1.
EVEX.256.66.0F.W1 78 /r
VCVTTPD2UQQ ymm1 {k1}{z}, 
AVX512DQConvert four packed double precision floating-point values 
from ymm2/m256/m64bcst to four packed unsigned 
quadword integers in ymm1  using truncation with 
EVEX.512.66.0F.W1 78 /r
VCVTTPD2UQQ zmm1 {k1}{z}, 
zmm2/m512/m64bcst{sae}A V/V AVX512DQ Convert eight packed double precision floating-point values 
from zmm2/mem to eight packed unsigned quadword 
integers in zmm1 using truncation with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPD2UQQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Quadword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-99VCVTTPD2UQQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Double_Precision_Floating_Point _To_UQuadInteger_Truncate(SRC[63:0])
ELSE 
FI;
ELSE 
FI
FI;
VCVTTPD2UQQ _mm<size>[_mask[z]]_cvtt[_round]pd_epu64
VCVTTPD2UQQ __m512i _mm512_cvttpd_epu64( __m512d a);VCVTTPD2UQQ __m512i _mm512_mask_cvttpd_epu64( __m512i s, __mmask8 k, __m512d a);VCVTTPD2UQQ __m512i _mm512_maskz_cvttp d_epu64( __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_cvtt_roun dpd_epu64( __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_mask_cvtt_roundpd_epu64(  __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_maskz_cvtt_roundpd _epu64( __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m256i _mm256_mask_cvttpd_epu64( __m256i s, __mmask8 k, __m256d a);VCVTTPD2UQQ __m256i _mm256_maskz_cvttp d_epu64( __mmask8 k, __m256d a);
VCVTTPD2UQQ __m128i _mm_mask_cvttpd_epu6 4( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UQQ __m128i _mm_maskz_cvttpd_epu64( __mmask8 k, __m128d a);
Additionally:#UD If EVEX.vvvv != 1111B.VCVTTPH2DQ—Convert with Truncation Packed FP16 Values to Signed Doubleword IntegersINSTRUCTION SET REFERENCE, V
5-100 Vol. 2CVCVTTPH2DQ—Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
operand.
When a conversion is inexact, a truncate d (round toward zero) value is returned. If a converted result is larger than 
masked, the indefinite integer value is returned.
The destination elements are upda ted according to the writemask.
Operation
VCVTTPH2DQ dest, src 
ELSE
DEST.fp32[j] := Convert_fp16 _to_integer32_truncate(tsrc)
En64/32 
Bit Mode 
EVEX.128.F3.MAP5.W0 5B /r
VCVTTPH2DQ xmm1 {k1}{z}, xmm2/
store the result in xmm1 using truncation subject 
EVEX.256.F3.MAP5.W0 5B /r
VCVTTPH2DQ ymm1{k1}{z}, xmm2/
integers, and store the result in ymm1 using 
truncation subject to writemask k1.
EVEX.512.F3.MAP5.W0 5B /r
VCVTTPH2DQ zmm1{k1}{z}, ymm2/
m256/m16bcst {sae}A V/V AVX512-FP16 Convert sixteen packed FP16 values in ymm2/
integers, and store the result in zmm1 using 
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPH2DQ—Convert with Truncation Packed FP16 Values to Signed Doubleword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-101Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2DQ __m512i _mm512_cvtt_roundph_epi32 (__m256h a, int sae);
VCVTTPH2DQ __m512i _mm512_mask_cvtt_roundph_epi32 (_ _m512i src, __mmask16 k, __m256h a, int sae);
VCVTTPH2DQ __m512i _mm512_maskz _cvtt_roundph_epi32 (__mmask 16 k, __m256h a, int sae);
VCVTTPH2DQ __m128i _mm_cvttph_epi32 (__m128h a);VCVTTPH2DQ __m128i _mm_mask_cvttph_epi32 (__m128i src, __mmask8 k, __m128h a);VCVTTPH2DQ __m128i _mm_maskz_cvttph _epi32 (__mmask8 k, __m128h a);
VCVTTPH2DQ __m256i _mm256_cvttph_epi32 (__m128h a);VCVTTPH2DQ __m256i _mm256_mask_cvttph_epi3 2 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2DQ __m256i _mm256_maskz_cvttph_epi32 (__mmask8 k, __m128h a);VCVTTPH2DQ __m512i _mm512_cvttph_epi32 (__m256h a);VCVTTPH2DQ __m512i _mm512_mask_cvttph_epi32 (__m512i src, __mmask16 k, __m256h a);
VCVTTPH2DQ __m512i _mm512_maskz_cvttp h_epi32 (__mmask16 k, __m256h a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTTPH2QQ—Convert with Truncation Packed FP16 Values to Signed Quadword IntegersINSTRUCTION SET REFERENCE, V

5-102 Vol. 2CVCVTTPH2QQ—Convert with Truncation Packed FP16 Values to Signed Quadword Integers
This instruction converts packed FP16 values in the source  operand to signed quadword integers in the destination 
operand.
the indefinite integer value is returned.
Operation
VCVTTPH2QQ dest, src
ELSE
DEST.qword[j] := Con vert_fp16_to_integer64_truncate(tsrc)
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W0 7A /r
VCVTTPH2QQ xmm1{k1}{z}, xmm2/
EVEX.256.66.MAP5.W0 7A /r
VCVTTPH2QQ ymm1{k1}{z}, xmm2/
m16bcst to four signed quadword integers, and 
store the result in ymm1 using truncation subject 
EVEX.512.66.MAP5.W0 7A /r
VCVTTPH2QQ zmm1{k1}{z}, xmm2/
m128/m16bcst {sae}A V/V AVX512-FP16 Convert eight packed FP16 values in xmm2/
A Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPH2QQ—Convert with Truncation Packed FP16 Values to Signed Quadword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-103Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2QQ __m512i _mm512_cvtt_roun dph_epi64 (__m128h a, int sae);
VCVTTPH2QQ __m512i _mm512_mask_cvtt_roundph_epi64 (__m512i src, __mmask8 k, __m128h a, int sae);VCVTTPH2QQ __m512i _mm512_maskz_cvtt_roundph_ epi64 (__mmask8 k, __m128h a, int sae);
VCVTTPH2QQ __m128i _mm_cvttph_epi64 (__m128h a);VCVTTPH2QQ __m128i _mm_mask_cvttph_epi64 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2QQ __m128i _mm_maskz_cvttph_epi64 (__mmask8 k, __m128h a);VCVTTPH2QQ __m256i _mm256_cvttph_epi64 (__m128h a);VCVTTPH2QQ __m256i _mm256_mask_cvttph_epi64 (__m256i src, __mmask8 k, __m128h a);VCVTTPH2QQ __m256i _mm256_maskz_cvttph_epi64 (__mmask8 k, __m128h a);VCVTTPH2QQ __m512i _mm512_cvttph_epi64 (__m128h a);VCVTTPH2QQ __m512i _mm512_mask_cvttph_epi64 (__m512i src, __mmask8 k, __m128h a);VCVTTPH2QQ __m512i _mm512_maskz_cvttph_epi64 (__mmask8 k, __m128h a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTTPH2UDQ—Convert with Truncation Packed FP16 Values to Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, V
5-104 Vol. 2CVCVTTPH2UDQ—Convert with Truncation Packed  FP16 Values to Unsigned Doubleword 
Integers
This instruction converts packed FP16 values in the sour ce operand to unsigned doublewo rd integers in the destina-
the integer indefinite value is returned.
Operation
VCVTTPH2UDQ dest, src
ELSE
DEST.dword[j] := Convert_fp16_to_unsigned_integer32_truncate(tsrc)
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W0 78 /r
VCVTTPH2UDQ xmm1{k1}{z}, xmm2/
and store the result in xmm1 using truncation subject to writemask k1.
EVEX.256.NP.MAP5.W0 78 /r
VCVTTPH2UDQ ymm1{k1}{z}, xmm2/
integers, and store the result in ymm1 using truncation subject to writemask k1.
EVEX.512.NP.MAP5.W0 78 /r
VCVTTPH2UDQ zmm1{k1}{z}, ymm2/
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPH2UDQ—Convert with Truncation Packed FP16 Values to Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-105Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UDQ __m512i _mm512_cvtt_roun dph_epu32 (__m256h a, int sae);
VCVTTPH2UDQ __m512i _mm512_mask_cvtt_roundph_epu32 (__m512i src, __mmask16 k, __m256h a, int sae);
VCVTTPH2UDQ __m512i _mm512_maskz_cvtt_roundp h_epu32 (__mmask16 k, __m256h a, int sae);
VCVTTPH2UDQ __m128i _mm_cvttph_epu32 (__m128h a);VCVTTPH2UDQ __m128i _mm_mask_cvttph_epu32 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2UDQ __m128i _mm_maskz_cvttph_epu32 (__mmask8 k, __m128h a);VCVTTPH2UDQ __m256i _mm256_cvttph_epu32 (__m128h a);VCVTTPH2UDQ __m256i _mm256_mask_cvttph_epu 32 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2UDQ __m256i _mm256_maskz_cvttph_epu32 (__mmask8 k, __m128h a);VCVTTPH2UDQ __m512i _mm512_cvttph_epu32 (__m256h a);VCVTTPH2UDQ __m512i _mm512_mask_cvttph_epu32 (__m512i src, __mmask16 k, __m256h a);VCVTTPH2UDQ __m512i _mm512_maskz_cvttp h_epu32 (__mmask16 k, __m256h a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTTPH2UQQ—Convert with Truncation Packed FP16 Values to Unsigned Quadword IntegersINSTRUCTION SET REFERENCE, V
5-106 Vol. 2CVCVTTPH2UQQ—Convert with Truncation Packed FP 16 Values to Unsigned Quadword Integers
This instruction converts packed FP16 values in the sour ce operand to unsigned quadword integers in the destina-
Operation
VCVTTPH2UQQ dest, src
ELSE
DEST.qword[j] := Convert_fp16_to_unsigned_integer64_truncate(tsrc)
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W0 78 /r
VCVTTPH2UQQ xmm1{k1}{z}, 
xmm2/m32/m16bcstA V/V AVX512-FP16 
m16bcst to two unsigned  quadword integers, 
and store the result in xmm1 using truncation 
EVEX.256.66.MAP5.W0 78 /r
VCVTTPH2UQQ ymm1{k1}{z}, 
xmm2/m64/m16bcstA V/V AVX512-FP16 
and store the result in ymm1 using truncation 
EVEX.512.66.MAP5.W0 78 /r
VCVTTPH2UQQ zmm1{k1}{z}, xmm2/
m128/m16bcst to eight unsigned quadword 
A Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPH2UQQ—Convert with Truncation Packed FP16 Values to Unsigned Quadword IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-107Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UQQ __m512i _mm512_cvtt_ro undph_epu64 (__m128h a, int sae);
VCVTTPH2UQQ __m512i _mm512_mask_cv tt_roundph_epu64 (__m512i src, __mmask8 k, __m128h a, int sae);
VCVTTPH2UQQ __m512i _mm512_mas kz_cvtt_roundph_epu64 (__mmask8 k, __m128h a, int sae);
VCVTTPH2UQQ __m128i _mm_cv ttph_epu64 (__m128h a);
VCVTTPH2UQQ __m128i _mm_mask_cvttph_epu64 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2UQQ __m128i _mm_maskz_cvttp h_epu64 (__mmask8 k, __m128h a);

VCVTTPH2UQQ __m256i _mm256_cvttph_epu64 (__m128h a);VCVTTPH2UQQ __m256i _mm256_mask_cvttph_epu64 (__m256i src, __mmask8 k, __m128h a);VCVTTPH2UQQ __m256i _mm256_maskz_cv ttph_epu64 (__mmask8 k, __m128h a);
VCVTTPH2UQQ __m512i _mm512_cvttph_epu64 (__m128h a);VCVTTPH2UQQ __m512i _mm512_mask_cvttph_epu64 (__m512i src, __mmask8 k, __m128h a);VCVTTPH2UQQ __m512i _mm512_maskz_cv ttph_epu64 (__mmask8 k, __m128h a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTTPH2UW—Convert Packed FP16 Values to Unsigned Word IntegersINSTRUCTION SET REFERENCE, V
5-108 Vol. 2CVCVTTPH2UW—Convert Packed FP16 Va lues to Unsigned Word Integers
This instruction converts packed FP16 values in the source operand to unsigned word integers in the destination 
operand.
Operation
VCVTTPH2UW dest, src
ELSE
DEST.word[j] := Convert_fp16_to_unsigned_integer16_truncate(tsrc)
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W0 7C /r
VCVTTPH2UW xmm1{k1}{z}, xmm2/
m128/m16bcst to eight un signed word integers, 
EVEX.256.NP.MAP5.W0 7C /r
VCVTTPH2UW ymm1{k1}{z}, ymm2/
m256/m16bcstA V/V AVX512-FP16 
AVX512VLConvert sixteen packed FP16 values in ymm2/
m256/m16bcst to sixteen unsigned word 
EVEX.512.NP.MAP5.W0 7C /r
VCVTTPH2UW zmm1{k1}{z}, zmm2/
m512/m16bcst {sae}A V/V AVX512-FP16 Convert thirty-two packed FP16 values in zmm2/
m512/m16bcst to thirty -two unsigned word 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPH2UW—Convert Packed FP16 Values to Unsigned Word IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-109Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UW __m512i _mm512_cvtt_ro undph_epu16 (__m512h a, int sae);
VCVTTPH2UW __m512i _mm512_mask_cvtt_roundph_epu16 (__m512i src, __mmask32 k, __m512h a, int sae);
VCVTTPH2UW __m512i _mm512_maskz_cvtt_roundph_ epu16 (__mmask32 k, __m512h a, int sae);
VCVTTPH2UW __m128i _mm_cvttph_epu16 (__m128h a);VCVTTPH2UW __m128i _mm_mask_cvttph_epu16 (__m128i src, __mmask8 k, __m128h a);VCVTTPH2UW __m128i _mm_maskz_cvttph_epu16 (__mmask8 k, __m128h a);VCVTTPH2UW __m256i _mm256_cvttph_epu16 (__m256h a);VCVTTPH2UW __m256i _mm256_mask_cvttph_epu16 (__m256i src, __mmask16 k, __m256h a);VCVTTPH2UW __m256i _mm256_maskz_cvttph_epu16 (__mmask16 k, __m256h a);VCVTTPH2UW __m512i _mm512_cvttph_epu16 (__m512h a);VCVTTPH2UW __m512i _mm512_mask_cvttph_epu16 (__m512i src, __mmask32 k, __m512h a);VCVTTPH2UW __m512i _mm512_maskz_cvttph_epu16 (__mmask32 k, __m512h a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTTPH2W—Convert Packed FP16 Values to Signed Word IntegersINSTRUCTION SET REFERENCE, V
5-110 Vol. 2CVCVTTPH2W—Convert Packed FP16 Va lues to Signed Word Integers
operand.
Operation
VCVTTPH2W dest, src
ELSE
DEST.word[j] := Convert_fp16 _to_integer16_truncate(tsrc)
En64/32 
Bit Mode 
EVEX.128.66.MAP5.W0 7C /r
VCVTTPH2W xmm1{k1}{z}, xmm2/
m128/m16bcst to eight signed word integers, 
EVEX.256.66.MAP5.W0 7C /r
VCVTTPH2W ymm1{k1}{z}, ymm2/
m256/m16bcst to sixteen signed word integers, 
EVEX.512.66.MAP5.W0 7C /r
VCVTTPH2W zmm1{k1}{z}, zmm2/
m512/m16bcst {sae}A V/V AVX512-FP16 Convert thirty-two packed FP16 va lues in zmm2/
m512/m16bcst to thirty-two signed word 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPH2W—Convert Packed FP16 Values to Signed Word IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-111Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2W __m512i _mm512_cvtt_roundph_epi16 (__m512h a, int sae);
VCVTTPH2W __m512i _mm512_mask_cvtt_roundph_epi16 (__m512i src, __mmask32 k, __m512h a, int sae);VCVTTPH2W __m512i _mm512_maskz_cvtt_roundph_epi16 (__mmask32 k, __m512h a, int sae);VCVTTPH2W __m128i _mm_cvttph_epi16 (__m128h a);VCVTTPH2W __m128i _mm_mask_cvttph_epi16 (__m128i src, __mmask8 k, __m128h a);VCVTTPH2W __m128i _mm_maskz_cvttph_epi16 (__mmask8 k, __m128h a);VCVTTPH2W __m256i _mm256_cvttph_epi16 (__m256h a);VCVTTPH2W __m256i _mm256_mask_cvttph_epi16 (__m256i src, __mmask16 k, __m256h a);VCVTTPH2W __m256i _mm256_maskz_cvttph_epi16 (__mmask16 k, __m256h a);VCVTTPH2W __m512i _mm512_cvttph_epi16 (__m512h a);VCVTTPH2W __m512i _mm512_mask_cvttph_epi16 (__m512i src, __mmask32 k, __m512h a);VCVTTPH2W __m512i _mm512_maskz_cvttph_epi16 (__mmask32 k, __m512h a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTTPS2QQ—Convert With Truncation Packed Single Precision Floa ting-Point Values to Packed Signed Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
5-112 Vol. 2CVCVTTPS2QQ—Convert With Truncation Packed Si ngle Precision Floating-Point Values to 
Packed Signed Quadword Integer Values
Converts with truncation packed single precision floating-p oint values in the source operand to eight signed quad-
EVEX encoded versions: The source operand is a YMM/ XMM/XMM (low 64 bits) register or a 256/128/64-bit 
memory location. The destination operation is a vector  register conditionally updated with writemask k1. 
Operation
VCVTTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Register
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
ELSE 
FI
FI;
ENDFOR
DEST[MAXVL-1:VL]  := 0Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F.W0 7A /r
VCVTTPS2QQ xmm1 {k1}{z}, 
xmm1 using truncation su bject to writemask k1.
EVEX.256.66.0F.W0 7A /r
VCVTTPS2QQ ymm1 {k1}{z}, 
in ymm1 using truncation subject to writemask k1.
EVEX.512.66.0F.W0 7A /r

ELSE 
FI
FI;
ENDFOR
En64/32 
Bit Mode 
Feature 
VCVTTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{sae}A V/V AVX512DQ Convert eight packed single precision floating-point values from 
ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 using truncation subject to writemask k1.
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPS2QQ—Convert With Truncation Packed Single Precision Floa ting-Point Values to Packed Signed Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-113VCVTTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[31:0])
ELSE 
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])FI;
ELSE 
FI
FI;
ENDFOR
VCVTTPS2QQ __m512i _mm512_cvttps_epi64( __m256 a);
VCVTTPS2QQ __m512i _mm512_mask_cvttps_epi64( __m512i s, __mmask16 k, __m256 a);VCVTTPS2QQ __m512i _mm512_maskz_cvttps_epi64( __mmask16 k, __m256 a);VCVTTPS2QQ __m512i _mm512_cvtt_roundps_epi64( __m256 a, int sae);VCVTTPS2QQ __m512i _mm512_mask_cvtt_roundps_epi64( __m512i s, __mmask16 k, __m256 a, int sae);VCVTTPS2QQ __m512i _mm512_maskz_cvtt_roundps_epi64( __mmask16 k, __m256 a, int sae);VCVTTPS2QQ __m256i _mm256_mask_cvttps_epi64( __m256i s, __mmask8 k, __m128 a);VCVTTPS2QQ __m256i _mm256_maskz_cvttps_epi64( __mmask8 k, __m128 a);VCVTTPS2QQ __m128i _mm_mask_cvttps_epi64( __m128i s, __mmask8 k, __m128 a);VCVTTPS2QQ __m128i _mm_maskz_cvttps_epi64( __mmask8 k, __m128 a);
#UD If EVEX.vvvv != 1111B.VCVTTPS2UDQ—Convert With Truncation Packed Single Precision Floa ting-Point Values to Packed Unsigned Doubleword Integer Val-INSTRUCTION SET REFERENCE, V
5-114 Vol. 2CVCVTTPS2UDQ—Convert With Truncation Packed Si ngle Precision Floating-Point Values to 
Packed Unsigned Doubleword Integer Values
Converts with truncation packed single precision floating-point values in the source operand to sixteen unsigned 
doubleword integers in the destination operand.
Operation
VCVTTPS2UDQ (EVEX Encoded Versions) When SRC Operand is a Register
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
ELSE 
FI
FI;
ENDFOR
En64/32 
Bit Mode 
Feature 
EVEX.128.0F.W0 78 /r
VCVTTPS2UDQ xmm1 {k1}{z}, 
unsigned doubleword va lues in xmm1 using 
EVEX.256.0F.W0 78 /r
VCVTTPS2UDQ ymm1 {k1}{z}, 
AVX512FConvert eight packed single  precision floating-point 
unsigned doubleword values in ymm1 using truncation subject to writemask k1.
EVEX.512.0F.W0 78 /r
VCVTTPS2UDQ zmm1 {k1}{z}, 
zmm2/m512/m32bcst{sae}A V/V AVX512F Convert sixteen packed single precision floating-
point values from zmm2/m512/m32bcst to sixteen 
packed unsigned doubleword  values in zmm1 using 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPS2UDQ—Convert With Truncation Packed Single Precision Floa ting-Point Values to Packed Unsigned Doubleword Integer Val-INSTRUCTION SET REFERENCE, V
Vol. 2C 5-115VCVTTPS2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Single_Precision_Floating_Poi nt_To_UInteger_Truncate(SRC[31:0])
ELSE 
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])FI;
ELSE 
FI
FI;
ENDFOR
VCVTTPS2UDQ __m512i _mm512_cvttps_epu32( __m512 a);
VCVTTPS2UDQ __m512i _mm512_mask_cvttps_epu32( __m512i s, __mmask16 k, __m512 a);VCVTTPS2UDQ __m512i _mm512_maskz_cvttp s_epu32( __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_cvtt_roundps_epu32( __m512 a, int sae);VCVTTPS2UDQ __m512i _mm512_mask_cvtt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int sae);VCVTTPS2UDQ __m512i _mm512_maskz_cvtt_roundps_epu32( __mmask16 k, __m512 a, int sae);VCVTTPS2UDQ __m256i _mm256_mask_cvttps_epu3 2( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2UDQ __m256i _mm256_maskz_cvttps_epu32( __mmask8 k, __m256 a);VCVTTPS2UDQ __m128i _mm_mask_cvttps_epu3 2( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UDQ __m128i _mm_maskz_cvttps_epu32( __mmask8 k, __m128 a);
#UD If EVEX.vvvv != 1111B.VCVTTPS2UQQ—Convert With Truncation Packed Single Precision Floa ting-Point Values to Packed Unsigned Quadword Integer ValuesINSTRUCTION SET REFERENCE, V
5-116 Vol. 2CVCVTTPS2UQQ—Convert With Truncation Packed Si ngle Precision Floating-Point Values to 
Packed Unsigned Quadword Integer Values
Converts with truncation up to eight packed single precisio n floating-point values in the source operand to unsigned 
quadword integers in the destination operand.
Operation
VCVTTPS2UQQ (EVEX Encoded Versions) When SRC Operand is a Register
Convert_Single_Precision_To_UQuad Integer_Truncate (SRC[k+31:k])
ELSE 
FI
FI;
ENDFOR
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F.W0 78 /r
VCVTTPS2UQQ xmm1 {k1}{z}, 
AVX512DQConvert two packed single precision floating-point values 
from xmm2/m64/m32bcst to two packed unsigned quadword 
values in xmm1 using truncati on subject to writemask k1.
EVEX.256.66.0F.W0 78 /r
VCVTTPS2UQQ ymm1 {k1}{z}, 
AVX512DQConvert four packed single precision floating-point values 
from xmm2/m128/m32bcst to four packed unsigned 
quadword values in ymm1 us ing truncation subject to 
EVEX.512.66.0F.W0 78 /r
VCVTTPS2UQQ zmm1 {k1}{z}, 
ymm2/m256/m32bcst{sae}A V/V AVX512DQ Convert eight packed sing le precision floating-point values 
from ymm2/m256/m32bcst to eight packed unsigned 
quadword values in zmm1 using truncation subject to 
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTPS2UQQ—Convert With Truncation Packed Single Precision Floa ting-Point Values to Packed Unsigned Quadword Integer ValuesINSTRUCTION SET REFERENCE, V

Vol. 2C 5-117VCVTTPS2UQQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[31:0])
ELSE 
Convert_Single_Precision_To_UQuad Integer_Truncate(SRC[k+31:k])
FI;
ELSE 
FI
FI;
ENDFOR
VCVTTPS2UQQ _mm<size>[_mas k[z]]_cvtt[_round]ps_epu64
VCVTTPS2UQQ __m512i _mm512_cvttps_epu64( __m256 a);VCVTTPS2UQQ __m512i _mm512_mask_cvttps_e pu64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_maskz_cvttp s_epu64( __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_cvtt_ro undps_epu64( __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_mask_cvtt_roundps_epu64 ( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_maskz_cvtt_roundps_epu64( __mmask16 k, __m256 a, int sae);VCVTTPS2UQQ __m256i _mm256_mask_cvttps_epu64( __m256i s, __mmask8 k, __m128 a);VCVTTPS2UQQ __m256i _mm256_maskz_cvttps_epu64( __mmask8 k, __m128 a);VCVTTPS2UQQ __m128i _mm_mask_cvttps_epu6 4( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_maskz_cvttp s_epu64( __mmask8 k, __m128 a);
#UD If EVEX.vvvv != 1111B.VCVTTSD2USI—Convert With Truncation Scalar Double Precision Floating-Point Value to Unsigned IntegerINSTRUCTION SET REFERENCE, V
5-118 Vol. 2CVCVTTSD2USI—Convert With Truncation Scalar Double Precision Floating-Point Value to 
Unsigned Integer
Converts with truncation a double precision floating-point value in the source operand (t he second operand) to an 
unsigned doubleword integer (or unsigne d quadword integer if operand size is  64 bits) in the destination operand 
(the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination 
operand is a general-purpose register. When the source op erand is an XMM register, the double precision floating-
point value is contained in the low quadword of the register.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.
Operation
VCVTTSD2USI (EVEX Encoded Version)
THEN DEST[63:0] := Convert_Double_Precision_F loating_Point_To_UInte ger_Truncate(SRC[63:0]);
ELSE DEST[31:0] := Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
FI
VCVTTSD2USI unsigned in t _mm_cvttsd_u32(__m128d);
VCVTTSD2USI unsigned int _mm_cv tt_roundsd_u32(__ m128d, int sae);
VCVTTSD2USI unsigned __int64  _mm_cvttsd_u64(__m128d);
VCVTTSD2USI unsigned __int64 _mm_cv tt_roundsd_u64(__m128d, int sae);
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.F2.0F.W0 78 /r
VCVTTSD2USI r32, xmm1/m64{sae}A V/V AVX512F Convert one double precision floating-point value from 
xmm1/m64 to one unsigned doubleword integer r32 
EVEX.LLIG.F2.0F.W1 78 /r
VCVTTSD2USI r64, xmm1/m64{sae}AV / N . E .1
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.AVX512F Convert one double precision floating-point value from 
xmm1/m64 to one unsigned quadword integer zero-
extended into r64 using truncation.
AT u p l e 1  F i x e d M o d R M : r e g  (w) ModRM:r/m (r) N/A N/AVCVTTSH2SI—Convert with Truncation Low FP16 Value to a Signed IntegerINSTRUCTION SET REFERENCE, V
Vol. 2C 5-119VCVTTSH2SI—Convert with Truncation Lo w FP16 Value to a Signed Integer
This instruction converts the low FP16 element in the source  operand to a signed integer in the destination general 
Operation
VCVTTSH2SI dest, src
DEST.qword := Convert_fp16_to_ integer64_trunca te(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_ integer32_truncate(SRC.fp16[0]) 
VCVTTSH2SI int _mm_cvtt_roundsh _i32 (__m128h a, int sae);
VCVTTSH2SI __int64 _mm_cvtt_ro undsh_i64 (__m128h a, int sae);
VCVTTSH2SI int _mm_cvttsh_i32 (__m128h a);VCVTTSH2SI __int64 _mm_cvttsh_i64 (__m128h a);
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 2C /r
VCVTTSH2SI r32, xmm1/m16 {sae}AV / V
1
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.AVX512-FP16 Convert FP16 value in the low element of xmm1/
m16 to a signed integer and store the result in 
r32 using truncation.
EVEX.LLIG.F3.MAP5.W1 2C /r
VCVTTSH2SI r64, xmm1/m16 {sae}A V/N.E. AVX512-FP16 Convert FP16 value in the low element of xmm1/
m16 to a signed integer and store the result in r64 using truncation.
A Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTSH2USI—Convert with Truncation Low FP16 Value to an Unsigned IntegerINSTRUCTION SET REFERENCE, V
5-120 Vol. 2CVCVTTSH2USI—Convert with Truncation Lo w FP16 Value to an Unsigned Integer
Operation
VCVTTSH2USI dest, src 
DEST.qword := Convert_fp16_to_unsigned_integer64_truncate(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_unsigned_integer32_truncate(SRC.fp16[0]) 
VCVTTSH2USI unsigned int _mm_cvtt_roundsh_u32 (__m128h a, int sae);
VCVTTSH2USI unsigned __int64 _mm_cvtt_roundsh_u64 (__m128h a, int sae);VCVTTSH2USI unsigned int _mm_cvttsh_u32 (__m128h a);VCVTTSH2USI unsigned __int64 _mm_cvttsh_u64 (__m128h a);
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 78 /r
VCVTTSH2USI r32, xmm1/m16 {sae}AV / V
1
NOTES:
m16 to an unsigned inte ger and store the result 
in r32 using truncation.
EVEX.LLIG.F3.MAP5.W1 78 /r
VCVTTSH2USI r64, xmm1/m16 {sae}A V/N.E. AVX512-FP16 Convert FP16 value in the low element of xmm1/
in r64 using truncation.
A Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTTSS2USI—Convert With Truncation Scalar Single Precision Floating-Point Value to Unsigned IntegerINSTRUCTION SET REFERENCE, V
Vol. 2C 5-121VCVTTSS2USI—Convert With Truncation Scalar Single Precision Floating-Point Value to 
Converts with truncation a single precision floating-point value in the source operand (the second operand) to an 
unsigned doubleword integer (or unsigne d quadword integer if operand size is 64 bits) in the destination operand 
(the first operand). The source operand can be an XMM register or a memory location. The destination operand is 
a general-purpose register. When the source operand is an XMM register, the single precision floating-point value 
is contained in the low doubleword of the register.

EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.Note: EVEX.vvvv is reserved and must be  1111b, otherwise instructions will #UD.
Operation
VCVTTSS2USI (EVEX Encoded Version)
DEST[63:0] := Convert_Single _Precision_Floating_Point_To_U Integer_Truncate(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single _Precision_Floating_Point_To_U Integer_Truncate(SRC[31:0]);
FI;
VCVTTSS2USI unsigned int _mm_cvttss_u32( __m128 a);
VCVTTSS2USI unsigned in t _mm_cvtt_roundss_u32(  __m128 a, int sae);
VCVTTSS2USI unsigned __int64 _mm_cvttss_u64( __m128 a);VCVTTSS2USI unsigned __int64 _mm_cvtt_roundss_u64( __m128 a, int sae);
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.F3.0F.W0 78 /r
VCVTTSS2USI r32, xmm1/m32{sae}A V/V AVX512F Convert one single precision floating-point value from 
xmm1/m32 to one unsigned doubleword integer in 
EVEX.LLIG.F3.0F.W1 78 /r
VCVTTSS2USI r64, xmm1/m32{sae}AV / N . E .
1
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.AVX512F Convert one single precision floating-point value from 
xmm1/m32 to one unsigned quadword integer in r64 
A Tuple1 Fixed ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTUDQ2PD—Convert Packed Unsigned Doubleword Intege rs to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-122 Vol. 2CVCVTUDQ2PD—Convert Packed Unsigned Double word Integers to Packed Double Precision 
Converts packed unsigned doubleword integers in the sour ce operand (second operand) to packed double precision 
floating-point values in the destination operand (first operand). 
The source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a 
256/128/64-bit vector broadcasted from a 32-bit memory  location. The destination operand is a ZMM/YMM/XMM 
register conditionally updated with writemask k1. 
Attempt to encode this instruction wi th EVEX embedded rounding is ignored.
Operation
VCVTUDQ2PD (EVEX Encoded Versions) When SRC Operand is a Register
Convert_UInteger_To_Double_Precis ion_Floating_Point(SRC[k+31:k])
ELSE 
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.128.F3.0F.W0 7A /r
VCVTUDQ2PD xmm1 {k1}{z}, 
AVX512FConvert two packed unsigned doubleword integers 
from ymm2/m64/m32bcst to packed double precision 
EVEX.256.F3.0F.W0 7A /r
VCVTUDQ2PD ymm1 {k1}{z}, 
AVX512FConvert four packed unsigned doubleword integers 
from xmm2/m128/m32bcst to packed double precision 
EVEX.512.F3.0F.W0 7A /r
VCVTUDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcstA V/V AVX512F Convert eight packed unsigned doubleword integers 
from ymm2/m256/m32bcst to eight packed double precision floating-point values in zmm1 with 
A Half ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTUDQ2PD—Convert Packed Unsigned Doubleword Intege rs to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-123VCVTUDQ2PD (EVEX Encoded Versions) When SRC Operand is a Memory Source
THEN 
THEN
Convert_UInteger_To_Double_Precis ion_Floating_Point(SRC[31:0])
ELSE 
FI;
ELSE 
FI
FI;
VCVTUDQ2PD __m512d _mm512_cvtepu32_pd( __m256i a);
VCVTUDQ2PD __m512d _mm512_mask_cvtepu32_pd( __m512d s, __mmask8 k, __m256i a);VCVTUDQ2PD __m512d _mm512_maskz_cvt epu32_pd( __mmask8 k, __m256i a);
VCVTUDQ2PD __m256d _mm256_cvtepu32_pd( __m128i a);VCVTUDQ2PD __m256d _mm256_mask_cvtepu32_pd( __m256d s, __mmask8 k, __m128i a);VCVTUDQ2PD __m256d _mm256_maskz_cvt epu32_pd( __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_cvtepu32_pd( __m128i a);VCVTUDQ2PD __m128d _mm_mask_cvtepu32_ pd( __m128d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
None.
Additionally:#UD If EVEX.vvvv != 1111B.VCVTUDQ2PH—Convert Packed Unsigned Doubleword Integers to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-124 Vol. 2CVCVTUDQ2PH—Convert Packed Unsigned Double word Integers to Packed FP16 Values
This instruction converts packed unsigned doubleword intege rs in the source operand to packed FP16 values in the 
destination operand. The destination elements are updated according to the writemask.
PE=1.
Operation
VCVTUDQ2PH dest, src
ELSE:
ELSE
DEST.fp16[j] := Convert_unsigned_integer32_to_fp16(tsrc)
En64/32 
Bit Mode 
EVEX.128.F2.MAP5.W0 7A /r
VCVTUDQ2PH xmm1{k1}{z}, xmm2/
AVX512VLConvert four packed unsigned doubleword 
integers from xmm2/m12 8/m32bcst to packed 
EVEX.256.F2.MAP5.W0 7A /r
VCVTUDQ2PH xmm1{k1}{z}, ymm2/
AVX512VLConvert eight packed unsigned doubleword 
integers from ymm2/m256/m32bcst to packed 
EVEX.512.F2.MAP5.W0 7A /r
VCVTUDQ2PH ymm1{k1}{z}, zmm2/
m512/m32bcst {er}A V/V AVX512-FP16 Convert sixteen packed unsigned doubleword 
integers from zmm2/m512/m32bcst to packed 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTUDQ2PH—Convert Packed Unsigned Doub leword Integers to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-125Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PH __m256h _mm512_cvt_roundepu32_ph (__m512i a, int rounding);
VCVTUDQ2PH __m256h _mm512_mask_cvt_roundepu32_ph (__m256h src, __mmask16 k, __m512i a, int rounding);VCVTUDQ2PH __m256h _mm512_maskz_cvt_roundepu32_ ph (__mmask16 k, __m512i a, int rounding);
VCVTUDQ2PH __m128h _mm_cvtepu32_ph (__m128i a);VCVTUDQ2PH __m128h _mm_mask_cvtepu32_ph (__m128h src, __mmask8 k, __m128i a);VCVTUDQ2PH __m128h _mm_maskz_cvtepu32_ph (__mmask8 k, __m128i a);VCVTUDQ2PH __m128h _mm256_cvtepu32_ph (__m256i a);VCVTUDQ2PH __m128h _mm256_mask_cvtepu32_ph (__m128h src, __mmask8 k, __m256i a);VCVTUDQ2PH __m128h _mm256_maskz_cvtepu32_ph (__mmask8 k, __m256i a);VCVTUDQ2PH __m256h _mm512_cvtepu32_ph (__m512i a);VCVTUDQ2PH __m256h _mm512_mask_cvtepu32_ph (__m256h src, __mmask16 k, __m512i a);VCVTUDQ2PH __m256h _mm512_maskz_cvtepu32_ph (__mmask16 k, __m512i a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTUDQ2PS—Convert Packed Unsigned Doubleword Intege rs to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-126 Vol. 2CVCVTUDQ2PS—Convert Packed Unsigned Double word Integers to Packed Single Precision

5-126 Vol. 2CVCVTUDQ2PS—Convert Packed Unsigned Double word Integers to Packed Single Precision 
Converts packed unsigned doubleword integers in the source operand (second operand) to single precision 
The source operand is a ZMM/YMM/XMM register, a 512/256/ 128-bit memory location or a 512/256/128-bit vector 
Operation
VCVTUDQ2PS (EVEX Encoded Version) When SRC Operand is a Register
THEN
ELSE 
FI;
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
ELSE 
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.128.F2.0F.W0 7A /r
VCVTUDQ2PS xmm1 {k1}{z}, 
xmm2/m128/m32bcst A V/V AVX512VL
AVX512FConvert four packed unsigned doubleword integers from 
xmm2/m128/m32bcst to packed single precision floating-
EVEX.256.F2.0F.W0 7A /r
VCVTUDQ2PS ymm1 {k1}{z}, 
AVX512FConvert eight packed unsigned doubleword integers from 
ymm2/m256/m32bcst to packed single precision floating-
point values in zmm1 with writemask k1.
EVEX.512.F2.0F.W0 7A /r
VCVTUDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er} A V/V AVX512F Convert sixteen packed unsigned doubleword integers 
from zmm2/m512/m32bcst to sixteen packed single precision floating-point values in zmm1 with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-127VCVTUDQ2PS (EVEX Encoded Version) When SRC Operand is a Memory Source
THEN 
THEN
Convert_UInteger_To_Single_Precis ion_Floating_Point(SRC[31:0])
ELSE 
Convert_UInteger_To_Single_Precis ion_Floating_Point(SRC[i+31:i])
FI;
ELSE 
FI
FI;
VCVTUDQ2PS __m512 _mm512_cvtepu32_ps( __m512i a);
VCVTUDQ2PS __m512 _mm512_mask_cvtepu32_ps( __m512 s, __mmask16 k, __m512i a);VCVTUDQ2PS __m512 _mm512_maskz_cvtepu32_ps( __mmask16 k, __m512i a);VCVTUDQ2PS __m512 _mm512_cvt_roundepu32_ps( __m512i a, int r);VCVTUDQ2PS __m512 _mm512_mask_cvt_roundepu32_ps(  __m512 s, __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_maskz_cvt_roundep u32_ps( __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m256 _mm256_cvtepu32_ps( __m256i a);VCVTUDQ2PS __m256 _mm256_mask_cvtepu32 _ps( __m256 s, __mmask8 k, __m256i a);
VCVTUDQ2PS __m256 _mm256_maskz_cvtepu32_ps( __mmask8 k, __m256i a);VCVTUDQ2PS __m128 _mm_cvtepu32_ps( __m128i a);VCVTUDQ2PS __m128 _mm_mask_cvtepu32_ps( __m128 s, __mmask8 k, __m128i a);VCVTUDQ2PS __m128 _mm_maskz_cvtepu32_ps( __mmask8 k, __m128i a);
Additionally:#UD If EVEX.vvvv != 1111B.VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers  to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-128 Vol. 2CVCVTUQQ2PD—Convert Packed Unsigned Quadwo rd Integers to Packed Double Precision 
Converts packed unsigned quadword integers in the source  operand (second operand) to packed double precision 
Operation
VCVTUQQ2PD (EVEX Encoded Version) When SRC Operand is a Register
THEN
ELSE 
FI;
Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
ELSE 
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.128.F3.0F.W1 7A /r
VCVTUQQ2PD xmm1 {k1}{z}, 
xmm2/m128/m64bcst AV / V A V X 5 1 2 V L
AVX512DQConvert two packed unsigned  quadword integers from 
xmm2/m128/m64bcst to two packed double precision 
EVEX.256.F3.0F.W1 7A /r
VCVTUQQ2PD ymm1 {k1}{z}, 
AVX512DQConvert four packed unsigned quadword integers from 
EVEX.512.F3.0F.W1 7A /r
VCVTUQQ2PD zmm1 {k1}{z}, zmm2/m512/m64bcst{er} A V/V AVX512DQ Convert eight packed unsigned quadword integers from 
AF u l lM o d R M : r e g  ( w ) M odRM:r/m (r) N/A N/AVCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-129VCVTUQQ2PD (EVEX Encoded Version) When SRC Operand is a Memory Source
THEN 
THEN
Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
ELSE 
Convert_UQuadInteger_To_Double_Prec ision_Floating_Point(SRC[i+63:i])
FI;
ELSE 
FI
FI;
VCVTUQQ2PD __m512d _mm512_cvtepu64_ps( __m512i a);
VCVTUQQ2PD __m512d _mm512_mask_cvtepu64_ps( __m512d s, __mmask8 k, __m512i a);VCVTUQQ2PD __m512d _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);VCVTUQQ2PD __m512d _mm512_cvt_roundepu64_ps( __m512i a, int r);VCVTUQQ2PD __m512d _mm512_mask_cvt_roundepu64_ps( __m512d s, __mmask8 k, __m512i a, int r);VCVTUQQ2PD __m512d _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);VCVTUQQ2PD __m256d _mm256_cvtepu64_ps( __m256i a);VCVTUQQ2PD __m256d _mm256_mask_cvtepu64_ps( __m256d s, __mmask8 k, __m256i a);VCVTUQQ2PD __m256d _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);VCVTUQQ2PD __m128d _mm_cvtepu64_ps( __m128i a);VCVTUQQ2PD __m128d _mm_mask_cvtepu64_ps( __m128d s, __mmask8 k, __m128i a);VCVTUQQ2PD __m128d _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);
#UD If EVEX.vvvv != 1111B.VCVTUQQ2PH—Convert Packed Unsigned Quadword Integers to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-130 Vol. 2CVCVTUQQ2PH—Convert Packed Unsigned Quad word Integers to Packed FP16 Values
This instruction converts packed unsigned quadword integers  in the source operand to packed FP16 values in the 
PE=1.
Operation
VCVTUQQ2PH dest, src
ELSE:
ELSE
DEST.fp16[j] := Convert_unsigned_integer64_to_fp16(tsrc)
En64/32 
Bit Mode 
EVEX.128.F2.MAP5.W1 7A /r
VCVTUQQ2PH xmm1{k1}{z}, xmm2/
m128/m64bcstA V/V AVX512-FP16

PE=1.
Operation
ELSE:
ELSE
En64/32 
Bit Mode 
AVX512VLConvert two packed unsigned doubleword 
integers from xmm2/m128/m64bcst to packed 
EVEX.256.F2.MAP5.W1 7A /r
VCVTUQQ2PH xmm1{k1}{z}, ymm2/
integers from ymm2/m256/m64bcst to packed 
EVEX.512.F2.MAP5.W1 7A /r
VCVTUQQ2PH xmm1{k1}{z}, zmm2/
m512/m64bcst {er}A V/V AVX512-FP16 Convert eight packed unsigned doubleword 
integers from zmm2/m512/m64bcst to packed 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTUQQ2PH—Convert Packed Unsigned Qu adword Integers to Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-131Intel C/C++ Compiler Intrinsic Equivalent
VCVTUQQ2PH __m128h _mm512_cvt_roundep u64_ph (__m512i a, int rounding);
VCVTUQQ2PH __m128h _mm512_mask_cvt_ roundepu64_ph (__m128h src, __mmask8 k, __m512i a, int rounding);
VCVTUQQ2PH __m128h _mm512_maskz_cvt_roundepu64_ ph (__mmask8 k, __m5 12i a, int rounding);
VCVTUQQ2PH __m128h _mm_cvtepu64_ph (__m128i a);VCVTUQQ2PH __m128h _mm_mask_cvtepu64_ph  (__m128h src, __mmask8 k, __m128i a);
VCVTUQQ2PH __m128h _mm_maskz_cvtepu 64_ph (__mmask8 k, __m128i a);
VCVTUQQ2PH __m128h _mm256_cvtepu64_ph (__m256i a);VCVTUQQ2PH __m128h _mm256_mask_cvtepu64_p h (__m128h src, __mmask8 k, __m256i a);
VCVTUQQ2PH __m128h _mm256_maskz_cvt epu64_ph (__mmask8 k, __m256i a);
VCVTUQQ2PH __m128h _mm512_cvtepu64_ph (__m512i a);VCVTUQQ2PH __m128h _mm512_mask_cvtepu64_p h (__m128h src, __mmask8 k, __m512i a);
VCVTUQQ2PH __m128h _mm512_maskz_cvt epu64_ph (__mmask8 k, __m512i a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTUSI2SH—Convert Unsigned Doubleword Integer to an FP16 ValueINSTRUCTION SET REFERENCE, V
5-132 Vol. 2CVCVTUSI2SH—Convert Unsigned Doub leword Integer to an FP16 Value
This instruction converts an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) 
in the second source operand to a FP16 value in the destinat ion operand. The result is stored in the low word of the 
destination operand. When conversion is inexact, the va lue returned is rounded according to the rounding control 
bits in the MXCSR register or embedded rounding controls.
destination operands are XMM registers. Bits 127:16 of th e XMM register destination are copied from corresponding 
bits in the first source operand. Bits MAXVL- 1:128 of the destination register are zeroed.
If the result of the convert operation is overflow and MX CSR.OM=0 then a SIMD exception will be raised with OE=1, 
PE=1.
Operation
VCVTUSI2SH dest, src1, src2
ELSE:
DEST.fp16[0] := Convert_unsign ed_integer64_to_fp16(SRC2.qword)
ELSE:
DEST.fp16[0] := Convert_unsign ed_integer32_to_fp16(SRC2.dword)
DEST[MAXVL-1:128] := 0 Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 7B /r
VCVTUSI2SH xmm1, xmm2, r32/m32 
{er}AV / V1
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.AVX512-FP16 Convert an unsigned doubleword integer from 
r32/m32 to an FP16 value, and store the result in 
xmm1. Bits 127:16 from xmm2 are copied to 
EVEX.LLIG.F3.MAP5.W1 7B /r
VCVTUSI2SH xmm1, xmm2, r64/m64 
{er}A V/N.E. AVX512-FP16 Convert an unsigned quadword integer from r64/
m64 to an FP16 value, and store the result in 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVCVTUSI2SH—Convert Unsigned Doubleword Integer to an FP16 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-133Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SH __m128h _mm_cvt_roundu32_sh (__m128h a, unsigned int b, int rounding);
VCVTUSI2SH __m128h _mm_cvt_roundu64_sh (__m 128h a, unsigned __int64 b, int rounding);
VCVTUSI2SH __m128h _mm_cvtu32_sh (__m128h a, unsigned int b);
VCVTUSI2SH __m128h _mm_cvtu64_sh (__m128h a, unsigned __int64 b);
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers  to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-134 Vol. 2CVCVTUQQ2PS—Convert Packed Un signed Quadword Integers to Packed Single Precision 
Converts packed unsigned quadword integers in the source  operand (second operand) to single precision floating-
The destination operand is a YMM/XMM/XMM (low 64 bits ) register conditionally updated with writemask k1. 
Operation
VCVTUQQ2PS (EVEX Encoded Version)  When SRC Operand is a Register
THEN
ELSE 
FI;
Convert_UQuadInteger_To_Single_Prec ision_Floating_Point(SRC[k+63:k])
ELSE 
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.128.F2.0F.W1 7A /r
VCVTUQQ2PS xmm1 {k1}{z}, 
AVX512DQConvert two packed unsigned quadword integers from 
xmm2/m128/m64bcst to packed single precision floating-
EVEX.256.F2.0F.W1 7A /r
ymm2/m256/m64bcst to packed single precision floating-
EVEX.512.F2.0F.W1 7A /r
VCVTUQQ2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er}A V/V AVX512DQ Convert eight packed unsigned quadword integers from 
zmm2/m512/m64bcst to eight packed single precision floating-point values in zmm1 with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTUQQ2PS—Convert Packed Unsigned Quadword Integers  to Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-135VCVTUQQ2PS (EVEX Encoded Version) When SRC Operand is a Memory Source
THEN 
THEN
Convert_UQuadInteger_To_Single_Prec ision_Floating_Point(SRC[63:0])
ELSE 
FI;
ELSE 
FI
FI;
VCVTUQQ2PS __m256 _mm512_cvtepu64_ps( __m512i a);
VCVTUQQ2PS __m256 _mm512_mask_cvtepu64_ ps( __m256 s, __mmask8 k, __m512i a);
VCVTUQQ2PS __m256 _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);VCVTUQQ2PS __m256 _mm512_cvt_rou ndepu64_ps( __m512i a, int r);
VCVTUQQ2PS __m256 _mm512_mask_cvt_roundepu64_p s( __m256 s, __mmask8 k, __m512i a, int r);
VCVTUQQ2PS __m256 _mm512_maskz_cvt_roundep u64_ps( __mmask8 k, __m512i a, int r);
VCVTUQQ2PS __m128 _mm256_cvtepu64_ps( __m256i a);VCVTUQQ2PS __m128 _mm256_mask_cvtepu64_ ps( __m128 s, __mmask8 k, __m256i a);
VCVTUQQ2PS __m128 _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);VCVTUQQ2PS __m128 _mm_cvtepu64_ps( __m128i a);VCVTUQQ2PS __m128 _mm_mask_cvtepu64_ ps( __m128 s, __mmask8 k, __m128i a);
VCVTUQQ2PS __m128 _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);
#UD If EVEX.vvvv != 1111B.VCVTUSI2SD—Convert Unsigned Integer to Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, V
5-136 Vol. 2CVCVTUSI2SD—Convert Unsigned Integer to Scal ar Double Precision Floating-Point Value
Converts an unsigned doubleword integer (or unsigned quad word integer if operand size is 64 bits) in the second

Converts an unsigned doubleword integer (or unsigned quad word integer if operand size is 64 bits) in the second 
quadword of the destination operand. When conversion is inexact, the value returned is rounded according to the 
rounding control bits in the MXCSR register.
destination operands are XMM registers. Bits (127:64) of  the XMM register destination are copied from corre-
sponding bits in the first source operand. Bits (M AXVL-1:128) of the destination register are zeroed.
EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.EVEX.W0 version: attempt to encode this instru ction with EVEX embedded  rounding is ignored.
Operation
VCVTUSI2SD (EVEX Encoded Version)
THEN
ELSE 
DEST[63:0] := Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
DEST[63:0] := Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[31:0]);
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.F2.0F.W0 7B /r
VCVTUSI2SD xmm1, xmm2, r/m32A V/V AVX512F Convert one unsign ed doubleword integer from 
r/m32 to one double precision floating-point value in 
xmm1.
EVEX.LLIG.F2.0F.W1 7B /r
VCVTUSI2SD xmm1, xmm2, r/m64{er}AV / N . E .
1
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.AVX512F Convert one unsigned quadword integer from r/m64 
A Tuple1 Scalar ModRM:reg (w) E VEX.vvvv (r) ModRM:r/m (r) N/AVCVTUSI2SD—Convert Unsigned Integer to Scalar Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-137Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SD __m128d _mm_cvtu32_s d( __m128d s, unsigned a); 
VCVTUSI2SD __m128d _mm_cvtu64_sd( __m128d s, unsigned __int64 a);
VCVTUSI2SD __m128d _mm_cvt_roundu64_sd( __ m128d s, unsigned __int64 a, int r);
See Table 2-48, “Type E3NF Class Exception Conditions” if W1; otherwise, see Table 2-59, “Type E10NF Class 
Exception Conditions.”VCVTUSI2SS—Convert Unsigned Integer to Scal ar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, V
5-138 Vol. 2CVCVTUSI2SS—Convert Unsigned Integer to Scal ar Single Precision Floating-Point Value
Converts a unsigned doubleword integer (or unsigned quadwo rd integer if operand size is 64 bits) in the source 
operand (second operand) to a single precision floating-point value in the destination operand (first operand). The 
source operand can be a general-purpose register or a memory location. The destination operand is an XMM 
register. The result is stored in the low doubleword of th e destination operand. When a conversion is inexact, the 
value returned is rounded according to the rounding cont rol bits in the MXCSR register or the embedded rounding 
control bits.
destination operands are XMM registers. Bits (127:32) of  the XMM register destination are copied from corre-
EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.
Operation
VCVTUSI2SS (EVEX Encoded Version)
THEN
ELSE 
DEST[31:0] := Convert_UInteger_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0] := Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0]);
VCVTUSI2SS __m128 _mm_cvtu32_ss( __m128 s, unsigned a);
VCVTUSI2SS __m128 _mm_cvt_roundu32_ ss( __m128 s, unsigned a, int r);
VCVTUSI2SS __m128 _mm_cvtu64_ss( __m128 s, unsigned __int64 a);VCVTUSI2SS __m128 _mm_cvt_roundu64_ss( __m128 s, unsigned __int64 a, int r);Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.F3.0F.W0 7B /r
VCVTUSI2SS xmm1, xmm2, r/m32{er}A V/V AVX512F Convert one signed do ubleword integer from r/m32 to 
EVEX.LLIG.F3.0F.W1 7B /r
VCVTUSI2SS xmm1, xmm2, r/m64{er}AV / N . E .
1
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.AVX512F Convert one signed quad word integer from r/m64 to 
A Tuple1 Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVCVTUSI2SS—Convert Unsigned Integer to Scalar Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-139SIMD Floating-Point Exceptions
See Table 2-48, “Type E3NF Class Exception Conditions.”VCVTUW2PH—Convert Packed Unsigned Word Integers to FP16 ValuesINSTRUCTION SET REFERENCE, V
5-140 Vol. 2CVCVTUW2PH—Convert Packed Unsigned Word Integers to FP16 Values
This instruction converts packed unsigned word integers in the source operand to FP16 values in the destination 
operand. When conversion is inexact, the value returned is rounded according to the rounding control bits in the 
MXCSR register or embedded rounding controls.
PE=1.
Operation
VCVTUW2PH dest, src
ELSE:
tsrc := SRC.word[0]
ELSE
tsrc := SRC.word[j]
DEST.fp16[j] := Convert_unsignd_integer16_to_fp16(tsrc)
En64/32 
Bit Mode 
EVEX.128.F2.MAP5.W0 7D /r
VCVTUW2PH xmm1{k1}{z}, xmm2/
AVX512VLConvert eight packed unsigned word integers 
from xmm2/m128/m16bcst to FP16 values, and 
EVEX.256.F2.MAP5.W0 7D /r
VCVTUW2PH ymm1{k1}{z}, ymm2/m256/m16bcstA V/V AVX512-FP16 
AVX512VLConvert sixteen packed unsigned word integers 
from ymm2/m256/m16bcst to FP16 values, and store the result in ymm1 subject to writemask k1.
EVEX.512.F2.MAP5.W0 7D /r
VCVTUW2PH zmm1{k1}{z}, zmm2/
m512/m16bcst {er}A V/V AVX512-FP16 Conve rt thirty-two packed unsigned word 
integers from zmm2/m512/m16bcst to FP16 
values, and store the resu lt in zmm1 subject to 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTUW2PH—Convert Packed Unsigned  Word Integers to FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-141Intel C/C++ Compiler Intrinsic Equivalent
VCVTUW2PH __m512h _mm512_cvt_roundep u16_ph (__m512i a, int rounding);
VCVTUW2PH __m512h _mm512_mask_cvt_roundepu16_ph (__m 512h src, __mmask32 k, __m512i a, int rounding);
VCVTUW2PH __m512h _mm512_maskz_cvt_roundepu16_ ph (__mmask32 k, __m5 12i a, int rounding);
VCVTUW2PH __m128h _mm_cv tepu16_ph (__m128i a);
VCVTUW2PH __m128h _mm_mask_cvtepu16_ph (__m128h src, __mmask8 k, __m128i a);VCVTUW2PH __m128h _mm_maskz_cvtepu16_ph (__mmask8 k, __m128i a);VCVTUW2PH __m256h _mm256_cvtepu16_ph (__m256i a);VCVTUW2PH __m256h _mm256_mask_cvtepu16_ph (__m256h src, __mmask16 k, __m256i a);
VCVTUW2PH __m256h _mm256_maskz_cvtep u16_ph (__mmask16 k, __m256i a);
VCVTUW2PH __m512h _mm512_cvtepu16_ph (__m512i a);VCVTUW2PH __m512h _mm512_mask_cvtepu16_ph (__m512h src, __mmask32 k, __m512i a);
VCVTUW2PH __m512h _mm512_maskz_cvtep u16_ph (__mmask32 k, __m512i a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VCVTW2PH—Convert Packed Signed Word Integers to FP16 ValuesINSTRUCTION SET REFERENCE, V
5-142 Vol. 2CVCVTW2PH—Convert Packed Signed Word Integers to FP16 Values
This instruction converts packed signed word integers in the source operand to FP16 values in the destination 

Operation
VCVTW2PH dest, src
ELSE:
ELSE
DEST.fp16[j] := Convert_ integer16_to_fp16(tsrc)
En64/32 
Bit Mode 
EVEX.128.F3.MAP5.W0 7D /r
VCVTW2PH xmm1{k1}{z}, xmm2/
AVX512VLConvert eight packed signed word integers from 
xmm2/m128/m16bcst to FP16 values, and store 
the result in xmm1 subject to writemask k1.
EVEX.256.F3.MAP5.W0 7D /r
VCVTW2PH ymm1{k1}{z}, ymm2/m256/m16bcstA V/V AVX512-FP16 
AVX512VLConvert sixteen packed signed word integers 
EVEX.512.F3.MAP5.W0 7D /r
VCVTW2PH zmm1{k1}{z}, zmm2/
m512/m16bcst {er}A V/V AVX512-FP16 Convert thirty-two packed signed word integers 
from zmm2/m512/m16bcst to FP16 values, and 
store the result in zmm1 subject to writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVCVTW2PH—Convert Packed Signed Word Integers to FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-143Intel C/C++ Compiler Intrinsic Equivalent
VCVTW2PH __m512h _mm512_cvt_roundepi16_ph (__m512i a, int rounding);
VCVTW2PH __m512h _mm512_mask_cvt_roundepi16_ph (__m 512h src, __mmask32 k, __m512i a, int rounding);
VCVTW2PH __m512h _mm512_maskz_cvt_roundepi16_ ph (__mmask32 k, __m512i a, int rounding);
VCVTW2PH __m128h _mm_cvtepi16_ph (__m128i a);VCVTW2PH __m128h _mm_mask_cvtepi16_ph (__m128h src, __mmask8 k, __m128i a);VCVTW2PH __m128h _mm_maskz_cvtepi 16_ph (__mmask8 k, __m128i a);
VCVTW2PH __m256h _mm256_cvtepi16_ph (__m256i a);VCVTW2PH __m256h _mm256_mask_cvtepi16_ph (__m256h src, __mmask16 k, __m256i a);VCVTW2PH __m256h _mm256_maskz_cvtepi16_ph (__mmask16 k, __m256i a);VCVTW2PH __m512h _mm512_cvtepi16_ph (__m512i a);VCVTW2PH __m512h _mm512_mask_cvtepi16_ph (__m512h src, __mmask32 k, __m512i a);VCVTW2PH __m512h _mm512_maskz_cvtepi16_ph (__mmask32 k, __m512i a);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned BytesINSTRUCTION SET REFERENCE, V
5-144 Vol. 2CVDBPSADBW—Double Block Packed Sum-Absolute -Differences (SAD) on Unsigned Bytes
Compute packed SAD (sum of absolute differences) wo rd results of unsigned bytes from two 32-bit dword 
elements. Packed SAD word results are calculated in mult iples of qword superblocks, producing 4 SAD word results 
in each 64-bit superblock of the destination register. 
Within each super block of packed word results, the SAD results from two 32-bit dword elements are calculated as 
follows:
•The lower two word results are calculated each from the SAD operation between a sliding dword element within 
a qword superblock from an intermediate vector with a stationary dword element in the corresponding qword 
superblock of the first source operand. The intermediate  vector, see “Tmp1” in Figure 5-8, is constructed from 
the second source operand the imm8 byte as shuffle cont rol to select dword elements within a 128-bit lane of 
the second source operand. The two sliding dword elements  in a qword superblock of Tmp1 are located at byte 
offset 0 and 1 within the superblock, respectively. The stationary dword element in the qword superblock from 
the first source operand is located at byte offset 0.
•The next two word results are calculated each from th e SAD operation between a sliding dword element within 
a qword superblock from the intermediate vector Tmp1 with a second stationary dword element in the corre-
sponding qword superblock of the firs t source operand. The two sliding dw ord elements in a qword superblock 
of Tmp1 are located at byte offset 2and 3 within the superblock, respecti vely. The stationary dword element in 
the qword superblock from the first source  operand is located at byte offset 4.
•The intermediate vector is constructed in 128-bits lane s. Within each 128-bit lane , each dword element of the 
intermediate vector is selected by a two-bit field with in the imm8 byte on the corresponding 128-bits of the 
second source operand. The imm8 byte serves as dwor d shuffle control within each 128-bit lanes of the inter-
mediate vector and the second source operand, similarly to PSHUFD.
The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, or 
a 512/256/128-bit memory location. The destination operan d is conditionally updated based on writemask k1 at 
16-bit word granularity.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F3A.W0 42 /r ib
VDBPSADBW xmm1 {k1}{z}, xmm2, 
xmm3/m128, imm8AV / V A V X 5 1 2 V L
AVX512BWCompute packed SAD word results of unsigned bytes in 
dword block from xmm2 with unsigned bytes of dword 
blocks transformed from xmm3/m128 using the shuffle 
controls in imm8. Results are written to xmm1 under the writemask k1.
EVEX.256.66.0F3A.W0 42 /r ib
VDBPSADBW ymm1 {k1}{z}, ymm2, 
ymm3/m256, imm8AV / V A V X 5 1 2 V L
dword block from ymm2 with unsigned bytes of dword 
blocks transformed from ymm3/m256 using the shuffle controls in imm8. Results are written to ymm1 under the 
EVEX.512.66.0F3A.W0 42 /r ib
VDBPSADBW zmm1 {k1}{z}, zmm2, 
zmm3/m512, imm8A V/V AVX512BW Compute packed SAD word results of unsigned bytes in 
dword block from zmm2 with unsigned bytes of dword 
blocks transformed from zmm3/m512 using the shuffle 
controls in imm8. Results are written to zmm1 under the writemask k1.
A Full Mem ModRM:reg (w) EVEX. vvvv (r) ModRM:r/m (r) imm8VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned BytesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-145Operation
VDBPSADBW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)Selection of quadruplets:FOR I = 0 to VL step 128
TMP1[I+31:I] := select (S RC2[I+127: I], imm8[1:0])
TMP1[I+63: I+32] := select (SRC2[I+127: I], imm8[3:2])
TMP1[I+95: I+64] := select (SRC2[I+127: I], imm8[5:4])
TMP1[I+127: I+96]  := select  (SRC2[I+127: I], imm8[7:6])
END FOR
SAD of quadruplets:FOR I =0 to VL step 64
TMP_DEST[I+15:I] := ABS(SRC1[I+7: I] - TMP1[I+7: I]) +
ABS(SRC1[I+15: I+8]- TMP1[I+15: I+8]) +Figure 5-8.  64-bit Super Bloc k of SAD Operation in VDBPSADBW 63 0 15 31 47Src1 stationary dword 0Tmp1 sliding dword 
+_
abs_
abs_
abs_
abs
+0 15 31
Src1 stationary dword 0Tmp1 sliding dword 
_
abs_
abs_
abs_
absSrc1 stationary dword 1Tmp1 sliding dword
_
abs_
abs_
abs_
absSrc1 stationary dword 1Tmp1 sliding dword 
_
abs_
abs_
abs_
abs
+ +
Destination qword superblock7 23
0 15 31 7 238 23 39 15 31
0 15 31 7 23 32 47 63 39 5524 39 55 31 47
32 47 63 39 5516 31 47 23 39127+128*n 128*n 31+128*n 63+128*n 95+128*n
128-bit Lane of Src2
0 3 71 500B: DW0
01B: DW110B: DW2
11B: DW3DW3 DW2 DW1 DW0
127+128*n 128*n 31+128*n 63+128*n 95+128*n
128-bit Lane of Tmp1imm8 shuffle control
Tmp1 qword superblockVDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned BytesINSTRUCTION SET REFERENCE, V
5-146 Vol. 2CABS(SRC1[I+23: I+16]- TMP1[I+23: I+16]) +
ABS(SRC1[I+31: I+24]- TMP1[I+31: I+24]) 
TMP_DEST[I+31: I+16] := ABS(SRC1[I+7: I] - TMP1[I+15: I+8]) +
ABS(SRC1[I+15: I+8]- TMP1[I+23: I+16]) +ABS(SRC1[I+23: I+16]- TMP1[I+31: I+24]) +ABS(SRC1[I+31: I+24]- TMP1[I+39: I+32])
TMP_DEST[I+47: I+32] := ABS(SRC1[I+39: I+32] - TMP1[I+23: I+16]) +
ABS(SRC1[I+47: I+40]- TMP1[I+31: I+24]) +ABS(SRC1[I+55: I+48]- TMP1[I+39: I+32]) +ABS(SRC1[I+63: I+56]- TMP1[I+47: I+40]) 
TMP_DEST[I+63: I+48] := ABS(SRC1[I+39: I+32] - TMP1[I+31: I+24]) +
ABS(SRC1[I+47: I+40] - TMP1[I+39: I+32]) +ABS(SRC1[I+55: I+48] - TMP1[I+47: I+40]) +ABS(SRC1[I+63: I+56] - TMP1[I+55: I+48])
ENDFOR
FOR j :=  0 TO KL-1
i :=  j * 16IF k1[j] OR *no writemask*
THEN DEST[i+15:i] :=  TMP_DEST[i+15:i]ELSE 
DEST[i+15:i] :=  0
FI
FI;
ENDFORDEST[MAXVL-1:VL] :=  0
VDBPSADBW __m512i _mm512_dbsad_epu 8(__m512i a, __m512i b int imm8);
VDBPSADBW __m512i _mm512_mask_dbsad_epu8(__m512i s, __mmask32 m, __m512i a, __m512i b int imm8);
VDBPSADBW __m512i _mm512_maskz_dbsad_epu8(__m mask32 m, __m512i a, __m512i b int imm8);
VDBPSADBW __m256i _mm256_dbsad_epu 8(__m256i a, __m256i b int imm8);
VDBPSADBW __m256i _mm256_mask_dbsad_epu8(__m256i s, __mmask16 m, __m256i a, __m256i b int imm8);
VDBPSADBW __m256i _mm256_maskz_dbsad_epu8(__m mask16 m, __m256i a, __m256i b int imm8);

ENDFOR
FI
FI;
VDBPSADBW __m128i _mm_dbsad_epu8(__m128i a, __m128i b int imm8);VDBPSADBW __m128i _mm_mask_dbs ad_epu8(__m128i s, __m mask8 m, __m128i a, __m128i b int imm8);
VDBPSADBW __m128i _mm_maskz_ dbsad_epu8(__mmask8 m, __m128i a, __m128i b int imm8);
None.
See Exceptions Type E4NF.nb in Table 2-50,  “Type E4NF Class Exception Conditions.”VDIVPH—Divide Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-147VDIVPH—Divide Packed FP16 Values
This instruction divides packed FP16 values from the fi rst source operand by the corresponding elements in the 
second source operand, storing the packed FP16 result in  the destination operand. Th e destination elements are 
updated according to the writemask.
Operation
VDIVPH (EVEX Encoded Versions) Wh en SRC2 Operand is a Register
IF (VL = 512) AND (EVEX.b = 1):
ELSE
DEST.fp16[j] := SRC1.fp16[j] / SRC2.fp16[j]
En64/32 
Bit Mode 
EVEX.128.NP.MAP5.W0 5E /r
VDIVPH xmm1{k1}{z}, xmm2, xmm3/
AVX512VLDivide packed FP16 valu es in xmm2 by packed 
FP16 values in xmm3/m128/m16bcst, and store 
EVEX.256.NP.MAP5.W0 5E /r
VDIVPH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstA V/V AVX512-FP16 
AVX512VLDivide packed FP16 valu es in ymm2 by packed 
FP16 values in ymm3/m256/m16bcst, and store the result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5E /r
VDIVPH zmm1{k1}{z}, zmm2, zmm3/
m512/m16bcst {er}A V/V AVX512-FP16 Divide packed FP16  values in zmm2 by packed 
FP16 values in zmm3/m512/m16bcst, and store 
the result in zmm1 su bject to writemask k1.
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVDIVPH—Divide Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-148 Vol. 2CVDIVPH (EVEX Encoded Versions) When SRC2 Operand is a Memory Source
DEST.fp16[j] := SRC1.fp16[j] / SRC2.fp16[0]
ELSE:
VDIVPH __m128h _mm_div_ph (__m128h a, __m128h b);
VDIVPH __m128h _mm_mask_div_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);VDIVPH __m128h _mm_maskz_div_ph (__mmask8 k, __m128h a, __m128h b);VDIVPH __m256h _mm256_div_ph (__m256h a, __m256h b);VDIVPH __m256h _mm256_mask_div_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);VDIVPH __m256h _mm256_maskz_div_ph (__mmask16 k, __m256h a, __m256h b);VDIVPH __m512h _mm512_div_ph (__m512h a, __m512h b);VDIVPH __m512h _mm512_mask_div_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);VDIVPH __m512h _mm512_maskz_div_ph (__mmask32 k, __m512h a, __m512h b);VDIVPH __m512h _mm512_div_round_ph ( __m512h a, __m512h b, int rounding);
VDIVPH __m512h _mm512_mask_div_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int rounding);VDIVPH __m512h _mm512_maskz_div_round_ph (__mma sk32 k, __m512h a, __m512h b, int rounding);
Invalid, Underflow, Overflow, Precision, Denormal, Zero.
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VDIVSH—Divide Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-149VDIVSH—Divide Scalar FP16 Values
This instruction divides the low FP16 value from the first source operand by the corresponding value in the second 
source operand, storing the FP16 result  in the destination operand. Bits 127:16 of the destination operand are 
copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are 
zeroed. The low FP16 element of the destination is updated according to the writemask.
Operation
VDIVSH (EVEX Encoded Versions)
IF EVEX.b = 1 and SRC2 is a register:
ELSE
DEST.fp16[0] := SRC1.fp16[0] / SRC2.fp16[0]
VDIVSH __m128h _mm_div_round_sh ( __m128h a, __m128h b, int rounding);
VDIVSH __m128h _mm_mask_div_round _sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);
VDIVSH __m128h _mm_maskz_div_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);VDIVSH __m128h _mm_div_sh (__m128h a, __m128h b);VDIVSH __m128h _mm_mask_div_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VDIVSH __m128h _mm_maskz_div_sh ( __mmask8 k, __m128h a, __m128h b);
En64/32 
Bit Mode 
EVEX.LLIG.F3.MAP5.W0 5E /r
VDIVSH xmm1{k1}{z}, xmm2, xmm3/
m16 {er}A V/V AVX512-FP16 Divide low FP16 value in xmm2 by low FP16 
value in xmm3/m16, and store the result in xmm1 
subject to writemask k1. Bits 127:16 of xmm2 
are copied to xmm1[127:16].
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVDPBF16PS—Dot Product of BF16 Pairs Accu mulated Into Packed Single PrecisionINSTRUCTION SET REFERENCE, V
5-150 Vol. 2CVDPBF16PS—Dot Product of BF16 Pairs Accumu lated Into Packed Single Precision
This instruction performs a SIMD dot-product of two BF16 pairs and accumulates into a packed single precision 
register.
“Round to nearest even” rounding mode is used when do ing each accumulation of the FMA. Output denormals are 
NaN propagation priorities are described in Table 5-1. 
Operation
Define make_fp32(x):
// The x parameter is bfloat16. Pack it in  to upper 16b of a dword. The bit pattern is a legal fp32 value. Return that bit patt ern.
dword := 0
dword[31:16] := x
RETURN dwordOpcode/
En64/32 
Bit Mode 
EVEX.128.F3.0F38.W0 52 /r
VDPBF16PS xmm1{k1}{z}, xmm2, 
xmm3/m128/m32bcstAV / VA V X 5 1 2 V L
AVX512_BF16Multiply BF16 pair s from xmm2 and 
xmm3/m128, and accumulate the resulting 
packed single precision results in xmm1 with 
EVEX.256.F3.0F38.W0 52 /r
VDPBF16PS ymm1{k1}{z}, ymm2, 
ymm3/m256/m32bcstAV / VA V X 5 1 2 V L
AVX512_BF16Multiply BF16 pair s from ymm2 and 
ymm3/m256, and accumulate the resulting 
packed single precision results in ymm1 with 
EVEX.512.F3.0F38.W0 52 /r
VDPBF16PS zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcstAV / VA V X 5 1 2 F
AVX512_BF16Multiply BF16 pairs from zmm2 and 
zmm3/m512, and accumulate the resulting 
packed single precision results in zmm1 with 
AF u l lM o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/A
Table 5-1.  NaN Propagation Priorities
NaN Priority Description Comments
1s r c 1  l o w  i s  N a N
Lower part has priority over upper part, i.e., it overrides the upper part.
2s r c 2  l o w  i s  N a N
3s r c 1  h i g h  i s  N a N
Upper part may be overridden if lower has NaN.
4s r c 2  h i g h  i s  N a N
5 srcdest is NaN Dest is propagated if no NaN is encountered by src2.VDPBF16PS—Dot Product of BF16 Pairs Accumulated Into Packed Single PrecisionINSTRUCTION SET REFERENCE, V
Vol. 2C 5-151VDPBF16PS srcdest, src1, src2
VL = (128, 256, 512)KL = VL/32
origdest 
:= srcdest
t := src2.dword[0]
ELSE:
t := src2.dword[ i ]
// FP32 FMA with daz in, ftz out and RNE rounding. MXCSR neither consulted nor updated.srcdest.fp32[ i ] += make_fp32(src1.bfloat16[2*i+1]) * make_fp32(t.bfloat[1])
srcdest.fp32[ i ] += make_fp32(src1.bfloat16[2*i+0]) * make_fp32(t.bfloat[0])
srcdest.dword[ i ] 
:= 0
ELSE: // merge masking, dest element unchanged
srcdest.dword[ i ] := origdest.dword[ i ]
srcdest[MAXVL-1:VL] := 0
VDPBF16PS __m128 _mm_dpbf16_ps(__m128, __m128bh, __m128bh);
VDPBF16PS __m128 _mm_mask_dpbf16_ps( __ m128, __mmask8, __m128bh, __m128bh);
VDPBF16PS __m128 _mm_maskz_dpbf16_ps( __mmask8, __m128, __m128bh, __m128bh);
VDPBF16PS __m256 _mm256_dpbf16_ps(__m256, __m256bh, __m256bh);VDPBF16PS __m256 _mm256_mask_dpbf16_ps(__m256, __mmask8, __m256bh, __m256bh);VDPBF16PS __m256 _mm256_maskz_dpbf16_ps (__mmask8, __m256, __m256bh, __m256bh);

ELSE:
:= 0
VDPBF16PS __m512 _mm512_dpbf16_ps(__m512, __m512bh, __m512bh);VDPBF16PS __m512 _mm512_mask_dpbf16_ps(__m512, __mmask16, __m512bh, __m512bh);VDPBF16PS __m512 _mm512_maskz_dpbf16_ps (__mmask16, __m512, __m512bh, __m512bh);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VERR/VERW—Verify a Segment for Reading or WritingINSTRUCTION SET REFERENCE, V
5-152 Vol. 2CVERR/VERW—Verify a Segment for Reading or Writing
Verifies whether the code or data segment specified with th e source operand is readable (VERR) or writable (VERW) 
from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that contains 
the segment selector for the segment to be verified. If the segment is accessi ble and readable (VERR) or writable 
(VERW), the ZF flag is set; otherwise, the ZF flag is cl eared. Code segments are never verified as writable. This 
check cannot be performed on system segments. 
To set the ZF flag, the following conditions must be met:
•The segment selector is not NULL.
•The selector must denote a descriptor within the bounds of the descriptor table (GDT or LDT).
•The selector must denote the descriptor of a code or data segment (not that of a system segment or gate).
•For the VERR instruction, the segment must be readable.
•For the VERW instruction, the segment must be a writable data segment.
•If the segment is not a conforming code segment, the segment’s DPL must be greater than or equal to (have 
less or the same privilege as) both the CPL and the segment selector's RPL.
The validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS 
register, and the indicated access (read or write) is performed. The segment selector's value cannot result in a 
protection exception, enabling the software to anticipate possible segment access problems.
This instruction’s operation is the same in non-64-bit mo des and 64-bit mode. The operand size is fixed at 16 bits.
Operation
IF SRC(Offset) > (GDTR(Limit) or (LDTR(Limit))
IF SegmentDescriptor(DescriptorType) = 0 (* System segment *)
or (SegmentDescriptor(Type) ≠ conforming co de segment) 
THEN
ZF := 0;
ELSE
IF ((Instruction  = VERR) and (Segment readable))
or ((Instruction = VERW) and (Segment writable))
THEN 
ZF := 1;
ELSE
ZF := 0;Opcode/
En64-Bit 
Leg 
ModeDescription
0F 00 /4
VERR r/m16M Valid Valid Set ZF=1 if segment specified with r/m16 can be read.
0F 00 /5
VERW r/m16M Valid Valid Set ZF=1 if segment specified with r/m16 can be written.
M ModRM:r/m (r) N/A N/A N/AVERR/VERW—Verify a Segment for Reading or WritingINSTRUCTION SET REFERENCE, V
Vol. 2C 5-153FI;
FI;
The ZF flag is set to 1 if the segment is accessible and read able (VERR) or writable (VERW); otherwise, it is set to 0.
The only exceptions generated for these instructions are those related to illegal addressing of the source operand.
selector.
#UD The VERR and VERW instructions are not recognized in real-address mode.
#UD The VERR and VERW instructions are not recognized in virtual-8086 mode.
#UD If the LOCK prefix is used.VEXPANDPD—Load Sparse Packed Double Precis ion Floating-Point Values From Dense MemoryINSTRUCTION SET REFERENCE, V
5-154 Vol. 2CVEXPANDPD—Load Sparse Packed Double Precis ion Floating-Point Values From Dense Memory
Expand (load) up to 8/4/2, contiguous, double precision floating-point values of the input vector in the source 
operand (the second operand) to sparse elements in the destination operand (the first operand) selected by the 
The destination operand is a ZMM/YMM/ XMM register, the source operand ca n be a ZMM/YMM/XMM register or a 
512/256/128-bit memory location.
The input vector starts from the lowest element in the so urce operand. The writemask register k1 selects the desti-
nation elements (a partial vector or sparse elements if  less than 8 elements) to be replaced by the ascending 
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or 
zeroed, depending on EVEX.z.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Note that the compressed displacement assumes a pre-scaling  (N) corresponding to the size of one single element 
Operation
VEXPANDPD (EVEX Encoded Versions) 
(KL, VL) = (2, 128), (4, 256), (8, 512)k := 0FOR j := 0 TO KL-1
THEN 
DEST[i+63:i] := SRC[k+63:k];k := k + 64
ELSE 
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W1 88 /r
VEXPANDPD xmm1 {k1}{z}, 
xmm2/m128A V/V AVX512VL
AVX512FExpand packed double precision floating-point values 
EVEX.256.66.0F38.W1 88 /r
VEXPANDPD ymm1 {k1}{z}, ymm2/m256A V/V AVX512VL
EVEX.512.66.0F38.W1 88 /r
VEXPANDPD zmm1 {k1}{z}, zmm2/m512A V/V AVX512F Expand packed double precision floating-point values 
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVEXPANDPD—Load Sparse Packed Double Precis ion Floating-Point Values From Dense MemoryINSTRUCTION SET REFERENCE, V
Vol. 2C 5-155Intel C/C++ Compiler Intrinsic Equivalent
VEXPANDPD __m512d _mm512_mask_expand_pd( __m512d s, __mmask8 k, __m512d a);
VEXPANDPD __m512d _mm512_maskz_exp and_pd( __mmask8 k, __m512d a);
VEXPANDPD __m512d _mm512_mask_expandloadu_pd( __m512d s, __mmask8 k, void * a);VEXPANDPD __m512d _mm512_maskz_expan dloadu_pd( __mmask8 k, void * a);
VEXPANDPD __m256d _mm256_mask_expand_pd( __m256d s, __mmask8 k, __m256d a);VEXPANDPD __m256d _mm256_maskz_exp and_pd( __mmask8 k, __m256d a);
VEXPANDPD __m256d _mm256_mask_expandloadu_pd( __m256d s, __mmask8 k, void * a);VEXPANDPD __m256d _mm256_maskz_expan dloadu_pd( __mmask8 k, void * a);
VEXPANDPD __m128d _mm_mask_expand_pd( __m128d s, __mmask8 k, __m128d a);VEXPANDPD __m128d _mm_maskz_expand_pd( __mmask8 k, __m128d a);VEXPANDPD __m128d _mm_mask_expandloadu_p d( __m128d s, __mmask8 k, void * a);
VEXPANDPD __m128d _mm_maskz_expand loadu_pd( __mmask8 k, void * a);
None.
See Exceptions Type E4.nb in Table 2-49,  “Type E4 Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B.VEXPANDPS—Load Sparse Packed Single Precis ion Floating-Point Values From Dense MemoryINSTRUCTION SET REFERENCE, V
5-156 Vol. 2CVEXPANDPS—Load Sparse Packed Single Precis ion Floating-Point Values From Dense Memory
Expand (load) up to 16/8/4, contiguous, single precision floating-point values of the input vector in the source 
operand (the second operand) to sparse elements of the destination operand (the first operand) selected by the 
The input vector starts from the lowest element in the source operand. The writemask k1 selects the destination 
elements (a partial vector or sparse elements if less th an 16 elements) to be replaced by the ascending elements 
in the input vector. Destination elements not selected by the writemask k1 are either unmodified or zeroed, 
depending on EVEX.z.

Operation
VEXPANDPS (EVEX Encoded Versions) 
(KL, VL) = (4, 128), (8, 256), (16, 512)k := 0FOR j := 0 TO KL-1
THEN 
DEST[i+31:i] := SRC[k+31:k];k := k + 32
ELSE 
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W0 88 /r
VEXPANDPS xmm1 {k1}{z}, xmm2/m128A V/V AVX512VL
AVX512FExpand packed single precision floating-point values 
EVEX.256.66.0F38.W0 88 /r
VEXPANDPS ymm1 {k1}{z}, ymm2/m256A V/V AVX512VL
EVEX.512.66.0F38.W0 88 /r
VEXPANDPS zmm1 {k1}{z}, zmm2/m512A V/V AVX512F Expand packed single precision floating-point values 
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVEXPANDPS—Load Sparse Packed Single Precis ion Floating-Point Values From Dense MemoryINSTRUCTION SET REFERENCE, V
Vol. 2C 5-157Intel C/C++ Compiler Intrinsic Equivalent
VEXPANDPS __m512 _mm512_mask_expand_p s( __m512 s, __mmask16 k, __m512 a);
VEXPANDPS __m512 _mm512_maskz_expand_ps( __mmask16 k, __m512 a);VEXPANDPS __m512 _mm512_mask_expandloadu_ps ( __m512 s, __mmask16 k, void * a);
VEXPANDPS __m512 _mm512_maskz_expandl oadu_ps( __mmask16 k, void * a);
VEXPANDPD __m256 _mm256_mask_expand_ps( __m256 s, __mmask8 k, __m256 a);VEXPANDPD __m256 _mm256_maskz_expand_ps( __mmask8 k, __m256 a);VEXPANDPD __m256 _mm256_mask_expandloadu_ps( __m256 s, __mmask8 k, void * a);VEXPANDPD __m256 _mm256_maskz_expandloadu_ps( __mmask8 k, void * a);VEXPANDPD __m128 _mm_mask_expand_ps ( __m128 s, __mmask8 k, __m128 a);
VEXPANDPD __m128 _mm_maskz_expand_ps( __mmask8 k, __m128 a);VEXPANDPD __m128 _mm_mask_expandloadu_p s( __m128 s, __mmask8 k, void * a);
VEXPANDPD __m128 _mm_maskz_expandloadu_ps( __mmask8 k, void * a);
None.
#UD If EVEX.vvvv != 1111B.VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/ VEXTRACTF64x4— Extract Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-158 Vol. 2CVEXTRACTF128/VEXTRACTF32x4/VEXTRACTF 64x2/VEXTRACTF32x8/VEXTRACTF64x4— 
Extract Packed Floating-Point Values
VEXTRACTF128/VEXTRACTF32x4 and VEXTRACTF64x2 extract 128- bits of single precision floating-point values 
from the source operand (the second operand) and store to the low 128-bit of the destination operand (the first 
operand). The 128-bit data extraction occurs at an 128- bit granular offset specified by imm8[0] (256-bit) or 
imm8[1:0] as the multiply factor. The destination may be ei ther a vector register or an 128-bit memory location.
VEXTRACTF32x4: The low 128-bit of the destination oper and is updated at 32-bit granularity according to the 
VEXTRACTF32x8 and VEXTRACTF64x4 extract 256-bits of doub le precision floating-point values from the source 
operand (second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit 
data extraction occurs at an 256-bit granular offset sp ecified by imm8[0] (256-bit) or imm8[0] as the multiply 
factor The destination may be either a vector register or a 256-bit memory location.
VEXTRACTF64x4: The low 256-bit of the destination oper and is updated at 64-bit granularity according to the 
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
The high 6 bits of the immediate are ignored.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.256.66.0F3A.W0 19 /r ib
imm8A V/V AVX Extract 128 bits of pa cked floating-point values 
from ymm2 and store results in xmm1/m128.
EVEX.256.66.0F3A.W0 19 /r ib
VEXTRACTF32X4 xmm1/m128 {k1}{z}, 
ymm2, imm8CV / V A V X 5 1 2 V L
AVX512FExtract 128 bits of packed single precision floating-
point values from ymm2  and store results in 
xmm1/m128 subject to writemask k1.
EVEX.512.66.0F3A.W0 19 /r ib
VEXTRACTF32x4 xmm1 /m128 {k1}{z}, 
zmm2, imm8C V/V AVX512F Extract 128 bits of packed single precision floating-
point values from zmm2 and store results in xmm1/m128 subject to writemask k1.
EVEX.256.66.0F3A.W1 19 /r ib
VEXTRACTF64X2 xmm1/m128 {k1}{z}, 
AVX512DQExtract 128 bits of packed double precision 
floating-point values from ymm2 and store results 
in xmm1/m128 subject to writemask k1.
EVEX.512.66.0F3A.W1 19 /r ib
zmm2, imm8B V/V AVX512DQ Extract 128 bits of packed double precision 
floating-point values from  zmm2 and store results 
EVEX.512.66.0F3A.W0 1B /r ib
VEXTRACTF32X8 ymm1/m256 {k1}{z}, 
zmm2, imm8D V/V AVX512DQ Extract 256 bits of packed single precision floating-
point values from zmm2 and store results in 
ymm1/m256 subject to writemask k1.
EVEX.512.66.0F3A.W1 1B /r ib
VEXTRACTF64x4 ymm1/m256 {k1}{z}, zmm2, imm8C V/V AVX512F Extract 256 bits of packed double precision 
in ymm1/m256 subject to writemask k1.
B Tuple2 ModRM:r/m (w) M odRM:reg (r) imm8 N/A
C Tuple4 ModRM:r/m (w) M odRM:reg (r) imm8 N/A
D Tuple8 ModRM:r/m (w) M odRM:reg (r) imm8 N/AVEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/ VEXTRACTF64x4— Extract Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-159If VEXTRACTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will 
Operation
VEXTRACTF32x4 (EVEX Encoded Versions) When Destination is a Register
VL = 256, 512IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC1[127:0]1: TMP_DEST[127:0] := SRC1[255:128]
ESAC.
FI;IF VL = 512 
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC1[127:0]01: TMP_DEST[127:0] := SRC1[255:128]10: TMP_DEST[127:0] := SRC1[383:256]11: TMP_DEST[127:0] := SRC1[511:384]
ESAC.
FI;FOR j := 0 TO 3
FI
FI;
ENDFORDEST[MAXVL-1:128] := 0
VEXTRACTF32x4 (EVEX Encoded Versions) When Destination is Memory
ESAC.
ESAC.
FI;
FOR j := 0 TO 3
i := j * 32IF k1[j] OR *no writemask*VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/ VEXTRACTF64x4— Extract Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-160 Vol. 2CTHEN DEST[i+31:i] := TMP_DEST[i+31:i]
FI;
ENDFOR
VEXTRACTF64x2 (EVEX Encoded Versions) When Destination is a Register
ESAC.
ESAC.
FI;
FOR j := 0 TO 1
FI
FI;
VEXTRACTF64x2 (EVEX Encoded Versions) When Destination is Memory
ESAC.
ESAC.
FI;
FOR j := 0 TO 1VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/ VEXTRACTF64x4— Extract Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-161i := j * 64
THEN DEST[i+63:i] := TMP_DEST[i+63:i]ELSE *DEST[i+63:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VEXTRACTF32x8 (EVEX.U1.512 Encoded Vers ion) When Destination is a Register
VL = 512CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC1[255:0]1: TMP_DEST[255:0] := SRC1[511:256]
ESAC.

FI
FI;
ESAC.
ESAC.
FI;
FI;
ENDFOR
ESAC.
FI
FI;
ENDFORDEST[MAXVL-1:256] := 0
VEXTRACTF32x8 (EVEX.U1.512 Encoded Ve rsion) When Destination is Memory
ESAC.
THEN DEST[i+31:i] := TMP_DEST[i+31:i]ELSE *DEST[i+31:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VEXTRACTF64x4 (EVEX.512 Encoded Version) When Destination is a Register
ESAC.
THEN DEST[i+63:i] := TMP_DEST[i+63:i]ELSE VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/ VEXTRACTF64x4— Extract Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-162 Vol. 2CIF *merging-masking* ; merging-masking
FI
FI;
VEXTRACTF64x4 (EVEX.512 Encoded Version) When Destination is Memory
ESAC.
THEN DEST[i+63:i] := TMP_DEST[i+63:i]ELSE ; merging-masking
*DEST[i+63:i] remains unchanged*
FI;
ENDFOR
VEXTRACTF128 (Memory Destination Form)
0: DEST[127:0] := SRC1[127:0]1: DEST[127:0] := SRC1[255:128]
ESAC.
VEXTRACTF128 (Register Destination Form)
ESAC.DEST[MAXVL-1:128] := 0
VEXTRACTF32x4 __m128 _mm512_extractf3 2x4_ps(__m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm512_mask_extractf32x4_ps( __m128 s, __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm512_maskz_extractf32x 4_ps( __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_extractf3 2x4_ps(__m256 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_mask_extractf32x4_ps( __m128 s, __mmask8 k, __m256 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_maskz_extractf32x 4_ps( __mmask8 k, __m256 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_extractf3 2x8_ps(__m512 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_mask_extractf32x8_ps( __m256 s, __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_maskz_extractf32x 8_ps( __mmask8 k, __m512 a, const int nidx);
VEXTRACTF64x2 __m128d _mm512_extractf64x2_pd(__m512d a, const int nidx);VEXTRACTF64x2 __m128d _mm512_mask_extractf64x2_pd( __m128d s, __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x2 __m128d _mm512_maskz_extractf64x 2_pd( __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x2 __m128d _mm256_extractf64x2_pd(__m256d a, const int nidx);VEXTRACTF64x2 __m128d _mm256_mask_extractf64x2_pd( __m128d s, __mmask8 k, __m256d a, const int nidx);
VEXTRACTF64x2 __m128d _mm256_maskz_extractf64x 2_pd( __mmask8 k, __m256d a, const int nidx);
VEXTRACTF64x4 __m256d _mm512_extractf64x4_pd( __m512d a, const int nidx);VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/ VEXTRACTF64x4— Extract Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-163VEXTRACTF64x4 __m256d _mm512_mask_extractf64x4_pd(__m 256d s, __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x4 __m256d _mm512_mas kz_extractf64x4_pd( __mmask8 k, __m512d a, const int nidx);
VEXTRACTF128 __m128 _mm256_extractf128_ps (__m256 a, int offset);VEXTRACTF128 __m128d _mm256_extractf128_pd (__m256d a, int offset);VEXTRACTF128 __m128i_mm256_extractf1 28_si256(__m256i a, int offset);
None.
EVEX-encoded instructions, see Table 2-54, “Type E6NF Class Exception Conditions.”
Additionally:#UD IF VEX.L = 0.
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract Packed Integer ValuesINSTRUCTION SET REFERENCE, V
5-164 Vol. 2CVEXTRACTI128/VEXTRACTI32x4/ VEXTRACTI64x2/VEXTRACTI32x 8/VEXTRACTI64x4—Extract 
Packed Integer Values
VEXTRACTI128/VEXTRACTI32x4 and VEXTRACTI64x2 extract 128-bits of doubleword integer values from the 
source operand (the second operand) and store to the lo w 128-bit of the destination operand (the first operand). 
The 128-bit data extraction occurs at an 128-bit granular  offset specified by imm8[0] (256-bit) or imm8[1:0] as 
the multiply factor. The destination may be either a vector register or an 128-bit memory location.
VEXTRACTI32x4: The low 128-bit of the destination oper and is updated at 32-bit granularity according to the 
VEXTRACTI64x2: The low 128-bit of the destination oper and is updated at 64-bit granularity according to the 
VEXTRACTI32x8 and VEXTRACTI64x4 extract 256-bits of qu adword integer values from the source operand (the 
second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit data extraction occurs at an 256-bit granular offset specifie d by imm8[0] (256-bit) or imm8[0] as the multiply factor 
The destination may be either a vector register or a 256-bit memory location.
VEXTRACTI32x8: The low 256-bit of the destination oper and is updated at 32-bit granularity according to the 
writemask.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.256.66.0F3A.W0 39 /r ib
VEXTRACTI128 xmm1/m128, ymm2, 
imm8A V/V AVX2 Extract 128 bits of integer data fr om ymm2 and 
store results in xmm1/m128.
EVEX.256.66.0F3A.W0 39 /r ib
VEXTRACTI32X4 xmm1/m128 {k1}{z}, 
ymm2, imm8C V/V AVX512VL
AVX512FExtract 128 bits of doub le-word integer values 
from ymm2 and store results in xmm1/m128 
EVEX.512.66.0F3A.W0 39 /r ib
VEXTRACTI32x4 xmm1/m128 {k1}{z}, zmm2, imm8C V/V AVX512F Extract 128 bits of double-word integer values 
from zmm2 and store results in xmm1/m128 subject to writemask k1.
EVEX.256.66.0F3A.W1 39 /r ib
VEXTRACTI64X2 xmm1/m128 {k1}{z}, 
ymm2, imm8B V/V AVX512VL
AVX512DQExtract 128 bits of quad-w ord integer values from 
ymm2 and store results in xmm1/m128 subject to 
EVEX.512.66.0F3A.W1 39 /r ib
zmm2, imm8B V/V AVX512DQ Extract 128 bits of quad-word integer values from 
zmm2 and store results in xmm1/m128 subject to 
EVEX.512.66.0F3A.W0 3B /r ib
VEXTRACTI32X8 ymm1/m256 {k1}{z}, 
zmm2, imm8D V/V AVX512DQ Extract 256 bits of double-word integer values 
from zmm2 and store results in ymm1/m256 
EVEX.512.66.0F3A.W1 3B /r ib
VEXTRACTI64x4 ymm1/m256 {k1}{z}, zmm2, imm8C V/V AVX512F Extract 256 bits of quad-word integer values from 
zmm2 and store results in ymm1/m256 subject to writemask k1.
B Tuple2 ModRM:r/m (w) ModRM:reg (r) imm8 N/A
C Tuple4 ModRM:r/m (w) ModRM:reg (r) imm8 N/A
D Tuple8 ModRM:r/m (w) ModRM:reg (r) imm8 N/AVEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI 32x8/VEXTRACTI64x4—Extract Packed Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-165VEXTRACTI64x4: The low 256-bit of the destination oper and is updated at 64-bit granularity according to the 
VEX.vvvv and EVEX.vvvv ar e reserved and must be 1111b otherwise instructions will #UD.
The high 7 bits (6 bits in EVEX.512) of the immediate are ignored.If VEXTRACTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will 
Operation
VEXTRACTI32x4 (EVEX encoded versions ) when destination is a register
ESAC.
ESAC.
FI
FI;
VEXTRACTI32x4 (EVEX encoded versions) when destination is memory
ESAC.
ESAC.VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract Packed Integer ValuesINSTRUCTION SET REFERENCE, V
5-166 Vol. 2CFI;
FI;
ENDFOR

ESAC.
FI
FI;
ESAC.
FI;
ENDFOR
VEXTRACTI64x2 (EVEX encoded versions ) when destination is a register
ESAC.
ESAC.
FI;
FI
FI;
VEXTRACTI64x2 (EVEX encoded versions) when destination is memory
ESAC.
00: TMP_DEST[127:0] := SRC1[127:0]01: TMP_DEST[127:0] := SRC1[255:128]10: TMP_DEST[127:0] := SRC1[383:256]VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI 32x8/VEXTRACTI64x4—Extract Packed Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-16711: TMP_DEST[127:0] := SRC1[511:384]
ESAC.
FI;
FI;
ENDFOR
VEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is a register
ESAC.
FI
FI;
VEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is memory
ESAC.
FI;
ENDFOR
VEXTRACTI64x4 (EVEX.512 encoded versio n) when destination is a register
5-168 Vol. 2CFOR j := 0 TO 3
FI
FI;
VEXTRACTI64x4 (EVEX.512 encoded vers ion) when destination is memory
ESAC.FOR j := 0 TO 3
FI;
ENDFOR
VEXTRACTI128 (memory destination form)
ESAC.
VEXTRACTI128 (register destination form)
VEXTRACTI32x4 __m128i _mm512_extracti32x4_epi32(__m512i a, const int nidx);
VEXTRACTI32x4 __m128i _mm512_mask_extracti32x4_epi32 (__m128i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI32x4 __m128i _mm512_maskz_extracti32x4_epi32( __mmask8 k, __m512i a, const int nidx);VEXTRACTI32x4 __m128i _mm256_extracti32x4_epi32(__m256i a, const int nidx);VEXTRACTI32x4 __m128i _mm256_mask_extracti32x4_epi32 (__m128i s, __mmask8 k, __m256i a, const int nidx);
VEXTRACTI32x4 __m128i _mm256_maskz_extracti32x4_epi32( __mmask8 k, __m256i a, const int nidx);VEXTRACTI32x8 __m256i _mm512_extracti32x8_epi32(__m512i a, const int nidx);VEXTRACTI32x8 __m256i _mm512_mask_extracti32x8_epi32 (__m256i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI32x8 __m256i _mm512_maskz_extracti32x8_epi32( __mmask8 k, __m512i a, const int nidx);VEXTRACTI64x2 __m128i _mm512_extracti64x2_epi64(__m512i a, const int nidx);VEXTRACTI64x2 __m128i _mm512_mask_extracti64x2_epi64 (__m128i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm512_maskz_extracti64x2_epi64( __mmask8 k, __m512i a, const int nidx);VEXTRACTI64x2 __m128i _mm256_extracti64x2_epi64(__m256i a, const int nidx);VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI 32x8/VEXTRACTI64x4—Extract Packed Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-169VEXTRACTI64x2 __m128i _mm256_mask_extracti64x2_epi64 (__m128i s, __mmask8 k, __m256i a, const int nidx);
VEXTRACTI64x2 __m128i _mm256_maskz_extracti64x2_epi64( __mmask8 k, __m256i a, const int nidx);VEXTRACTI64x4 __m256i _mm512_extracti6 4x4_epi64(__m512i a, const int nidx);
VEXTRACTI64x4 __m256i _mm512_mask_extracti64x4_epi64 (__m256i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x4 __m256i _mm512_maskz_extracti64x4_epi64( __mmask8 k, __m512i a, const int nidx);VEXTRACTI128 __m128i _mm256_extract i128_si256(__m256i a, int offset);
None
#UD If VEX.vvvv != 1111B or  EVEX.vvvv != 1111B.VFCMADDCPH/VFMADDCPH—Complex Multiply and Accumulate FP16 ValuesINSTRUCTION SET REFERENCE, V
5-170 Vol. 2CVFCMADDCPH/VFMADDCPH—Complex Mult iply and Accumulate FP16 Values
This instruction performs a complex mu ltiply and accumulate operation. There are normal and complex conjugate 
forms of the operation.
The broadcasting and masking for this operation is done on 32-bit quantities representing a pair of FP16 values.Rounding is performed at every FMA (fused multiply and add) boundary. Execution occurs as if all MXCSR excep-
tions are masked. MXCSR status bits are up dated to reflect exceptional conditions.Opcode/
En64/32 
Bit Mode 
EVEX.128.F2.MAP6.W0 56 /r
VFCMADDCPH xmm1{k1}{z}, xmm2, 
xmm3/m128/m32bcstA V/V AVX512-FP16 
AVX512VLComplex multiply a pair  of FP16 values from 
xmm2 and complex conjugate of 
xmm3/m128/m32bcst, add to xmm1 and store 
EVEX.256.F2.MAP6.W0 56 /r
VFCMADDCPH ymm1{k1}{z}, ymm2, 
ymm3/m256/m32bcstA V/V AVX512-FP16 
ymm2 and complex conjugate of 
ymm3/m256/m32bcst, add to ymm1 and store 
the result in ymm1 su bject to writemask k1.
EVEX.512.F2.MAP6.W0 56 /r
VFCMADDCPH zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcst {er}A V/V AVX512-FP16 Complex multiply a pair of FP16 values from 
zmm2 and complex conjugate of 
zmm3/m512/m32bcst, add to zmm1 and store 
the result in zmm1 subject to writemask k1.
EVEX.128.F3.MAP6.W0 56 /r
VFMADDCPH xmm1{k1}{z}, xmm2, 
xmm2 and xmm3/m128/m32bcst, add to xmm1 
EVEX.256.F3.MAP6.W0 56 /r
VFMADDCPH ymm1{k1}{z}, ymm2, 
ymm2 and ymm3/m256/m32bcst, add to ymm1 
EVEX.512.F3.MAP6.W0 56 /r
VFMADDCPH zmm1{k1}{z}, zmm2, 
zmm2 and zmm3/m512/m32bcst, add to zmm1 
and store the result in zmm1 subject to writemask k1.
A Full ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/AVFCMADDCPH/VFMADDCPH—Complex Multiply and Accumulate FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-171Operation
VFCMADDCPH dest{k1}, src1, src2 (AVX512)
VL = 128, 256, 512KL := VL / 32
IF k1[i] or *no writemask*:
IF broadcasting and src2 is memory:
tsrc2.fp16[2*i+0] := src2.fp16[0]tsrc2.fp16[2*i+1] := src2.fp16[1]
ELSE:
tsrc2.fp16[2*i+0] := src2.fp16[2*i+0]tsrc2.fp16[2*i+1] := src2.fp16[2*i+1]
tmp[2*i+0] := dest.fp16[2*i+0] + sr c1.fp16[2*i+0] * tsrc2.fp16[2*i+0]
tmp[2*i+1] := dest.fp16[2*i+1] + sr c1.fp16[2*i+1] * tsrc2.fp16[2*i+0]
// conjugate version subtracts odd final termdest.fp16[2*i+0] := tmp[2*i+0] + src1.fp16[2*i+1] * tsrc2.fp16[2*i+1]dest.fp16[2*i+1] := tmp[2*i+1] - src1.fp16[2*i+0] * tsrc2.fp16[2*i+1]
dest.fp16[2*i+0] := 0dest.fp16[2*i+1] := 0
DEST[MAXVL-1:VL] := 0VFMADDCPH dest{k1}, src1, src2 (AVX512)
ELSE:

ELSE:
ELSE:
// non-conjugate version subtracts even termdest.fp16[2*i+0] := tmp[2*i+0] - src1.fp16[2*i+1] * tsrc2.fp16[2*i+1]dest.fp16[2*i+1] := tmp[2*i+1] + src1.fp16[2*i+0] * tsrc2.fp16[2*i+1]
ELSE IF *zeroing*:VFCMADDCPH/VFMADDCPH—Complex Multiply and Accumulate FP16 ValuesINSTRUCTION SET REFERENCE, V
5-172 Vol. 2Cdest.fp16[2*i+0] := 0
dest.fp16[2*i+1] := 0
VFCMADDCPH __m128h _mm_fcmadd_pch (__m128h a, __m128h b, __m128h c);
VFCMADDCPH __m128h _mm_mask_fcmadd_pch (__m1 28h a, __mmask8 k, __ m128h b, __m128h c);
VFCMADDCPH __m128h _mm_mask3_fcmadd_pch (__m 128h a, __m128h b, __m128h c, __mmask8 k);
VFCMADDCPH __m128h _mm_maskz_fcmadd_pch (__mmask8 k, __m128h a, __m128h b, __m128h c);VFCMADDCPH __m256h _mm256_fcmadd_pch (__m256h a, __m256h b, __m256h c);
VFCMADDCPH __m256h _mm256_mask_fcmadd_pch (__m256h a, __mmask8 k, __m256h b, __m256h c);VFCMADDCPH __m256h _mm256_mask3_fcmadd_pch (__m256h a, __m256h b, __m256h c, __mmask8 k);VFCMADDCPH __m256h _mm256_maskz_fcmadd_pch (__mmask8 k, __m256h a, __m256h b, __m256h c);VFCMADDCPH __m512h _mm512_fcmadd_pch (__m512h a, __m512h b, __m512h c);
VFCMADDCPH __m512h _mm512_mask_fcmadd_pch (__m 512h a, __mmask16 k, __m512h b, __m512h c);
VFCMADDCPH __m512h _mm512_mask3_fcmadd_pch (__m512h a, __m512h b, __m512h c, __mmask16 k);VFCMADDCPH __m512h _mm512_maskz_fcmadd_pch (__mmask16 k, __m512h a, __m512h b, __m512h c);VFCMADDCPH __m512h _mm512_fcmadd_round_pch (__m512h a, __m512h b, __m512h c, const int rounding);VFCMADDCPH __m512h _mm512_mask_fcmadd_round_pch (__m512h a, __mmask16 k, __m512h b, __m512h c, const int rounding);VFCMADDCPH __m512h _mm512_mask3_fcmadd_r ound_pch (__m512h a, __m512h b, __m512 h c, __mmask16 k, const int rounding);
VFCMADDCPH __m512h _mm512_maskz_fcmadd_round_pch (__mmask16 k, __m512h a, __m512h b, __m512h c, const int rounding);
VFMADDCPH __m128h _mm_fmadd_pch (_ _m128h a, __m128h b, __m128h c);
VFMADDCPH __m128h _mm_mask_fmadd_pch (__m12 8h a, __mmask8 k, __m128h b, __m128h c);
VFMADDCPH __m128h _mm_mask3_fmadd_pch (__m1 28h a, __m128h b, __m128h c, __mmask8 k);
VFMADDCPH __m128h _mm_maskz_fmadd_pch (__mma sk8 k, __m128h a, __m128h b, __m128h c);
VFMADDCPH __m256h _mm256_fmadd_pch (_ _m256h a, __m256h b, __m256h c);
VFMADDCPH __m256h _mm256_mask_fmadd_pch (__m 256h a, __mmask8 k, __m256h b, __m256h c);
VFMADDCPH __m256h _mm256_mask3_fmadd_pch (__m 256h a, __m256h b, __m256h c, __mmask8 k);
VFMADDCPH __m256h _mm256_maskz_fmadd_pch (__m mask8 k, __m256h a, __m256h b, __m256h c);
VFMADDCPH __m512h _mm512_fmadd_pch (_ _m512h a, __m512h b, __m512h c);
VFMADDCPH __m512h _mm512_mask_fmadd_pch (__m512h a, __mmask16 k, __m512h b, __m512h c);VFMADDCPH __m512h _mm512_mask3_fmadd_pch (__m51 2h a, __m512h b, __m512h c, __mmask16 k);
VFMADDCPH __m512h _mm512_maskz_fmadd_pch (__m mask16 k, __m512h a, __m512h b, __m512h c);
VFMADDCPH __m512h _mm512_fmadd_round_pch (__m512h a, __m512h b, __m512h c, const int rounding);
VFMADDCPH __m512h _mm512_mask_fmadd_round_pch (__m512h a, __mmask16 k, __m512h b, __m5 12h c, const int rounding);
VFMADDCPH __m512h _mm512_mask3_fmadd_round_pch (__m512h a,  __m512h b, __m512h c, __mmask 16 k, const int rounding);
VFMADDCPH __m512h _mm512_maskz_fmadd_rou nd_pch (__mmask16 k, __m512h a, __m512h b, __m512h c, const int rounding);
EVEX-encoded instructions, see Table 2-49, “Type E4 Class Exception Conditions.”
#UD If (dest_reg == src1_reg) or (dest_reg == src2_reg).VFCMADDCSH/VFMADDCSH—Complex Multiply  and Accumulate Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-173VFCMADDCSH/VFMADDCSH—Complex Multiply  and Accumulate Scalar FP16 Values
This instruction performs a complex multiply and accumu late operation. There are normal and complex conjugate 
The masking for this operation is done on 32-bit quantities representing a pair of FP16 values.
Rounding is performed at every FMA (fused multiply and add) boundary. Execution occurs as if all MXCSR excep-
tions are masked. MXCSR status bits are up dated to reflect exceptional conditions.
Operation
VFCMADDCSH dest{k1}, src1, src2 (AVX512)
IF k1[0] or *no writemask*:
tmp[0] := dest.fp16[0] + src1.fp16[0] * src2.fp16[0]tmp[1] := dest.fp16[1] + src1.fp16[1] * src2.fp16[0]
// conjugate version subtracts odd final term
dest.fp16[0] := tmp[0] + src1.fp16[1] * src2.fp16[1]dest.fp16[1] := tmp[1] - src1.fp16[0] * src2.fp16[1]
dest.fp16[0] := 0dest.fp16[1] := 0
DEST[127:32] := src1[127:32] // copy upper part of src1
En64/32 
Bit Mode 
EVEX.LLIG.F2.MAP6.W0 57 /r
VFCMADDCSH xmm1{k1}{z}, xmm2, 
xmm3/m32 {er}A V/V AVX512-FP16 Complex multiply a pair of FP16 values from 
xmm2 and complex conjugate of xmm3/m32, add 
to xmm1 and store the resu lt in xmm1 subject to 
writemask k1. Bits 127:32 of xmm2 are copied to xmm1[127:32].
EVEX.LLIG.F3.MAP6.W0 57 /r
VFMADDCSH xmm1{k1}{z}, xmm2, 
xmm2 and xmm3/m32, add to xmm1 and store 
the result in xmm1 subjec t to writemask k1. Bits 
127:32 of xmm2 are copied to xmm1[127:32].
AS c a l a r M o d R M : r e g  ( r ,  w ) V E X . vvvv (r) ModRM:r/m (r) N/AVFCMADDCSH/VFMADDCSH—Complex Multiply  and Accumulate Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
5-174 Vol. 2CVFMADDCSH dest{k1}, src1, src2 (AVX512)
// non-conjugate version subtracts last even term
dest.fp16[0] := tmp[0] - src1.fp16[1] * src2.fp16[1]dest.fp16[1] := tmp[1] + src1.fp16[0] * src2.fp16[1]
VFCMADDCSH __m128h _mm_fcmadd_round_sch (__m128h  a, __m128h b, __m128h c, const int rounding);
VFCMADDCSH __m128h _mm_mask_fcmadd_round_sch (__m128h a,  __mmask8 k, __m128h b, __m1 28h c, const int rounding);
VFCMADDCSH __m128h _mm_mask3_fcmadd_round_sch (__m128h a,  __m128h b, __m128h c, __mmask8 k, const int rounding);
VFCMADDCSH __m128h _mm_maskz_fcmadd_rou nd_sch (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);
VFCMADDCSH __m128h _mm_fcmadd_sch (__m128h a, __m128h b, __m128h c);
VFCMADDCSH __m128h _mm_mask_fcmadd_sch (__m12 8h a, __mmask8 k, __m 128h b, __m128h c);
VFCMADDCSH __m128h _mm_mask3_ fcmadd_sch (__m128h a, __m128 h b, __m128h c, __mmask8 k);
VFCMADDCSH __m128h _mm_maskz_fcmadd_sch (__m mask8 k, __m128h a, __m128h b, __m128h c);
VFMADDCSH __m128h _mm_fmadd_round_sch (__m128h a, __m128h b, __m128h c, const int rounding);
VFMADDCSH __m128h _mm_mask_fmadd_round _sch (__m128h a, __mmask8 k, __m128h b, __m128h c, const int rounding);
VFMADDCSH __m128h _mm_mask3_fmadd_round _sch (__m128h a, __m128h b, __m128 h c, __mmask8 k, const int rounding);
VFMADDCSH __m128h _mm_maskz_fmadd_round_sch (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);VFMADDCSH __m128h _mm_fmadd_sch (__m128h a, __m128h b, __m128h c);VFMADDCSH __m128h _mm_mask_fmadd_sch (__m12 8h a, __mmask8 k, __m128h b, __m128h c);
VFMADDCSH __m128h _mm_mask3_fmadd_sch (__m12 8h a, __m128h b, __m128h c, __mmask8 k);
VFMADDCSH __m128h _mm_maskz_fmadd_sch (__mma sk8 k, __m128h a, __m128h b, __m128h c);
EVEX-encoded instructions, see Table 2-58, “Type E10 Class Exception Conditions.”
#UD If (dest_reg == src1_reg) or (dest_reg == src2_reg).VFCMULCPH/VFMULCPH—Complex Multiply FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-175VFCMULCPH/VFMULCPH—Complex Multiply FP16 Values
This instruction performs a complex multiply operation. There are normal and complex conjugate forms of the oper-
ation. The broadcasting and masking for this operation is done on 32-bit quantities representing a pair of FP16 
values.
Operation
VFCMULCPH dest{k1}, src1, src2 (AVX512)
VL = 128, 256 or 512KL := VL/32

values.
Operation
ELSE:
FOR i := 0 to KL-1:Opcode/
En64/32 
Bit Mode 
EVEX.128.F2.MAP6.W0  D6 /r
VFCMULCPH xmm1{k1}{z}, xmm2, 
AVX512VLComplex multiply a pair of FP16 values from 
xmm3/m128/m32bcst, and store the result in 
EVEX.256.F2.MAP6.W0  D6 /r
VFCMULCPH ymm1{k1}{z}, ymm2, 
ymm3/m256/m32bcst, and store the result in 
EVEX.512.F2.MAP6.W0  D6 /r
VFCMULCPH  zmm1{k1}{z},  zmm2,  
zmm3/m512/m32bcst  {er}A V/V AVX512-FP16 Complex  multiply a pair of FP16 values from 
zmm3/m512/m32bcst, and store the result in 
EVEX.128.F3.MAP6.W0  D6 /r
VFMULCPH xmm1{k1}{z}, xmm2, xmm3/m128/m32bcstA V/V AVX512-FP16 
xmm2 and xmm3/m128/m32bcst, and store the 
result in xmm1 subject to writemask k1.
EVEX.256.F3.MAP6.W0  D6 /r
VFMULCPH ymm1{k1}{z}, ymm2, 
ymm2 and ymm3/m256/m32bcst, and store the 
EVEX.512.F3.MAP6.W0  D6 /r
VFMULCPH  zmm1{k1}{z},  zmm2,  
zmm2 and zmm3/m512/m32bcst, and store the result in zmm1 subject to writemask k1.
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVFCMULCPH/VFMULCPH—Complex Multiply FP16 ValuesINSTRUCTION SET REFERENCE, V
5-176 Vol. 2CIF k1[i] or *no writemask*:
tmp.fp16[2*i+0] := src1.fp16[2*i+0] * tsrc2.fp16[2*i+0]tmp.fp16[2*i+1] := src1.fp16[2*i+1] * tsrc2.fp16[2*i+0]
// conjugate version subtracts odd final termdest.fp16[2*i] := tmp.fp16[2*i+0] +src1.fp16[2*i+1] * tsrc2.fp16[2*i+1]dest.fp16[2*i+1] := tmp.fp16[2*i+1] - src1.fp16[2*i+0] * tsrc2.fp16[2*i+1]
DEST[MAXVL-1:VL] := 0 VFMULCPH dest{k1}, src1, src2 (AVX512)
ELSE:
FOR i := 0 to kl-1:
// non-conjugate version subtracts last even termdest.fp16[2*i+0] := tmp.fp16[2*i+0] - src1.fp16[2*i+1] * tsrc2.fp16[2*i+1]
dest.fp16[2*i+1] := tmp.fp16[2*i+1] + src1.fp16[2*i+0] * tsrc2.fp16[2*i+1]
VFCMULCPH __m128h _mm_cmul_pch (__m128h a, __m128h b);
VFCMULCPH __m128h _mm_mask_cmul_pch (__m128h src, __mmask8 k, __m128h a, __m128h b);VFCMULCPH __m128h _mm_maskz_cmul_pch (__mmask8 k, __m128h a, __m128h b);VFCMULCPH __m256h _mm256_cmul_pch (__m256h a, __m256h b);VFCMULCPH __m256h _mm256_mask_cmul_pch (__m256h src, __mmask8 k, __m256h a, __m256h b);VFCMULCPH __m256h _mm256_maskz_cmul_pch (__mmask8 k, __m256h a, __m256h b);VFCMULCPH __m512h _mm512_cmul_pch (__m512h a, __m512h b);VFCMULCPH __m512h _mm512_mask_cmul_pch (__m512h src, __mmask16 k, __m512h a, __m512h b);VFCMULCPH __m512h _mm512_maskz_cmul_pch (__mmask16 k, __m512h a, __m512h b);VFCMULCPH/VFMULCPH—Complex Multiply FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-177VFCMULCPH __m512h _mm512_cmul_round_pch (__m512h a, __m512h b, const int rounding);
VFCMULCPH __m512h _mm512_mask_cmul_round_pch (__m512h src, __mmask16 k, __m512h a, __m512h b, const int rounding);
VFCMULCPH __m512h _mm512_maskz_cmul_round_pch (__mmask 16 k, __m512h a, __m512h  b, const int rounding);
VFCMULCPH __m128h _mm_fcmul_pch (__m128h a, __m128h b);VFCMULCPH __m128h _mm_mask_fcmul_pch (__m128h  src, __mmask8 k, __m 128h a, __m128h b);
VFCMULCPH __m128h _mm_maskz_fcmul_pch (__mmask8 k, __m128h a, __m128h b);VFCMULCPH __m256h _mm256_fcmul_pch (__m256h a, __m256h b);VFCMULCPH __m256h _mm256_mask_fcmul_pch (__m256h src, __mmask8 k, __m256h a, __m256h b);VFCMULCPH __m256h _mm256_maskz_fcmul_pch (__mmask8 k, __m256h a, __m256h b);VFCMULCPH __m512h _mm512_fcmul_pch (__m512h a, __m512h b);VFCMULCPH __m512h _mm512_mask_fcmul_pch (__m512 h src, __mmask16 k, __m512h a, __m512h b);
VFCMULCPH __m512h _mm512_maskz_fcmul_pch (__mmask16 k, __m512h a, __m512h b);
VFCMULCPH __m512h _mm512_fcmul_round_pch (_ _m512h a, __m512h b, const int rounding);
VFCMULCPH __m512h _mm512_mask_fcmul_round_pch (__m512h src,  __mmask16 k, __m512h a, __m512h b, const int rounding);
VFCMULCPH __m512h _mm512_maskz_fcmul_round_pch (__mma sk16 k, __m512h a, __m512h b, const int rounding);
VFMULCPH __m128h _mm_fmul_pch (__m128h a, __m128h b);
VFMULCPH __m128h _mm_mask_fmul_pch (__m128 h src, __mmask8 k, __m128h a, __m128h b);
VFMULCPH __m128h _mm_maskz_fmul_pch (__mmask8 k, __m128h a, __m128h b);
VFMULCPH __m256h _mm256_fmul_pch (__m256h a, __m256h b);VFMULCPH __m256h _mm256_mask_fmul_pch (__m256h src, __mmask8 k, __m256h a, __m256h b);VFMULCPH __m256h _mm256_maskz_fmul_pc h (__mmask8 k, __m256h a, __m256h b);
VFMULCPH __m512h _mm512_fmul_pch (__m512h a, __m512h b);VFMULCPH __m512h _mm512_mask_fmul_pch (__m512h src, __mmask16 k, __m512h a, __m512h b);VFMULCPH __m512h _mm512_maskz_fmul_pch (__mmask16 k, __m512h a, __m512h b);
VFMULCPH __m512h _mm512_fmul_round_pch (_ _m512h a, __m512h b, const int rounding);
VFMULCPH __m512h _mm512_mask_fmul_round_pch (__m512h src,  __mmask16 k, __m512h a, __m512h b, const int rounding);
VFMULCPH __m512h _mm512_maskz_fmul_round_pch (__mma sk16 k, __m512h a, __m512h b, const int rounding);
VFMULCPH __m128h _mm_mask_mul_pch (__m128h  src, __mmask8 k, __m128h a, __m128h b);
VFMULCPH __m128h _mm_maskz_mul_pch (__mmask8 k, __m128h a, __m128h b);VFMULCPH __m128h _mm_mul_pch (__m128h a, __m128h b);VFMULCPH __m256h _mm256_mask_mul_pch (__m256h src, __mmask8 k, __m256h a, __m256h b);VFMULCPH __m256h _mm256_maskz_mul_pch (__mmask8 k, __m256h a, __m256h b);VFMULCPH __m256h _mm256_mul_pch (__m256h a, __m256h b);VFMULCPH __m512h _mm512_mask_mul_pch (__m512h  src, __mmask16 k, __m512h a, __m512h b);
VFMULCPH __m512h _mm512_maskz_mul_pch (__mmask16 k, __m512h a, __m512h b);
VFMULCPH __m512h _mm512_mul_pch (__m512h a, __m512h b);VFMULCPH __m512h _mm512_mask_mul_round_pch (__m512h src,  __mmask16 k, __m512h a, __m512h b, const int rounding);
VFMULCPH __m512h _mm512_maskz_mul_round_pch (__mma sk16 k, __m512h a, __m512h b, const int rounding);
VFMULCPH __m512h _mm512_mul_round_pch (__m 512h a, __m512h b, const int rounding);
EVEX-encoded instructions, see Table 2-49,  “Type E4 Class Exception Conditions.”
Additionally:#UD If (dest_reg == src1_reg) or (dest_reg == src2_reg).VFCMULCSH/VFMULCSH—Complex Multiply Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
5-178 Vol. 2CVFCMULCSH/VFMULCSH—Complex Mu ltiply Scalar FP16 Values
ation. The masking for this operation is done on 32- bit quantities representing a pair of FP16 values.
Operation
VFCMULCSH dest{k1}, src1, src2 (AVX512)
KL := VL / 32
tmp.fp16[0] := src1.fp16[0] * src2.fp16[0]tmp.fp16[1] := src1.fp16[1] * src2.fp16[0]
dest.fp16[0] := tmp.fp16[0] + src1.fp16[1] * src2.fp16[1]dest.fp16[1] := tmp.fp16[1] - src1.fp16[0] * src2.fp16[1]
En64/32 
Bit Mode 
EVEX.LLIG.F2.MAP6.W0 D7 /r
VFCMULCSH xmm1{k1}{z}, xmm2, 
xmm2 and complex conjugate of xmm3/m32, and 

Operation
KL := VL / 32
En64/32 
Bit Mode 
store the result in xmm1 subject to writemask k1. 
Bits 127:32 of xmm2 are copied to xmm1[127:32].
EVEX.LLIG.F3.MAP6.W0 D7 /r
VFMULCSH xmm1{k1}{z}, xmm2, 
xmm2 and xmm3/m32, and store the result in 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVFCMULCSH/VFMULCSH—Complex Multiply Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-179VFMULCSH dest{k1}, src1, src2 (AVX512)
KL := VL / 32
// non-conjugate version subtracts last even termtmp.fp16[0] := src1.fp16[0] * src2.fp16[0]tmp.fp16[1] := src1.fp16[1] * src2.fp16[0]dest.fp16[0] := tmp.fp16[0] - src1.fp16[1] * src2.fp16[1]dest.fp16[1] := tmp.fp16[1] + src1.fp16[0] * src2.fp16[1]
VFCMULCSH __m128h _mm_cmul_round_sch (__m 128h a, __m128h b, const int rounding);
VFCMULCSH __m128h _mm_mask_cmul_round_sch (__m128h src, __mmask8 k, __m128h a, __m12 8h b, const int rounding);
VFCMULCSH __m128h _mm_maskz_cmul_round_sch (__mmask 8 k, __m128h a, __m128h b, const int rounding);
VFCMULCSH __m128h _mm_cmul_sch (__m128h a, __m128h b);VFCMULCSH __m128h _mm_mask_cmul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);VFCMULCSH __m128h _mm_maskz_cmul_sch (_ _mmask8 k, __m128h a, __m128h b);
VFCMULCSH __m128h _mm_fcmul_round_sch (__m128h a, __m128h b, const int rounding);VFCMULCSH __m128h _mm_mask_fcmul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);
VFCMULCSH __m128h _mm_maskz_fcmul_round_sch (__mmask 8 k, __m128h a, __m128h b, const int rounding);
VFCMULCSH __m128h _mm_fcmul_sch (__m128h a, __m128h b);VFCMULCSH __m128h _mm_mask_fcmul_sch (__m128h  src, __mmask8 k, __m128h a, __m128h b);
VFCMULCSH __m128h _mm_maskz_fcmul_sch ( __mmask8 k, __m128h a, __m128h b);
VFMULCSH __m128h _mm_fmul_round_sch (__m 128h a, __m128h b, const int rounding);
VFMULCSH __m128h _mm_mask_fmul_round_ sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);
VFMULCSH __m128h _mm_maskz_fmul_round_sch (__mmask 8 k, __m128h a, __m128h b, const int rounding);
VFMULCSH __m128h _mm_fmul_sch (__m128h a, __m128h b);VFMULCSH __m128h _mm_mask_fmul_sch (__m128h  src, __mmask8 k, __m128h a, __m128h b);
VFMULCSH __m128h _mm_maskz_fmul_sch (__mmask8 k, __m128h a, __m128h b);VFMULCSH __m128h _mm_mask_mul_round_s ch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);
VFMULCSH __m128h _mm_maskz_mul_round_sch (__mmask 8 k, __m128h a, __m128h b, const int rounding);
VFMULCSH __m128h _mm_mul_round_sch (__m128h a, __m128h b, const int rounding);VFMULCSH __m128h _mm_mask_mul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);VFMULCSH __m128h _mm_maskz_mul_sch (__mmask8 k, __m128h a, __m128h b);VFMULCSH __m128h _mm_mul_sch (__m128h a, __m128h b);
#UD If (dest_reg == src1_reg) or (dest_reg == src2_reg).VFIXUPIMMPD—Fix Up Special Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
5-180 Vol. 2CVFIXUPIMMPD—Fix Up Specia l Packed Float64 Values
Perform fix-up of quad-word elements encoded in double pr ecision floating-point format in the first source operand 
(the second operand) using a 32-bit, two-level look-up table specified in the corresponding quadword element of 
the second source operand (the third operand) with ex ception reporting specifier imm8. The elements that are 
fixed-up are selected by mask bits of  1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table 
response action of 0000b preserves the corresponding elem ent of the first operand. The fixed-up elements from 
the first source operand and the preserved element in the first operand are combined as the final results in the 
The destination and the first source operands are ZMM/YM M/XMM registers. The second source operand can be a 
The two-level look-up table perform a fix-up of each double  precision floating-point input data in the first source 
operand by decoding the input data encoding into 8 token types. A response table is defined for each token type 
that converts the input encoding in the first source operand with one of 16 response actions. 
This instruction is specifically intended for use in fixing up  the results of arithmetic calculations involving one source 
so that they match the spec, although it is generally us eful for fixing up the results of multiple-instruction 
sequences to reflect special-number inputs. For example, co nsider rcp(0). Input 0 to rcp, and you should get INF 
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-
rect result. To deal with this, VFIXUPIMMPD can be used af ter the N-R reciprocal sequence to set the result to the 
correct value (i.e., INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and 
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR mask bits are ignored and are treated as if all mask  bits are set to masked response). If any of the imm8 
bits is set and the condition met for fault repo rting, MXCSR.IE or MXCSR.ZE might be updated.
are computed and stored into zmm1. Elements in the destin ation with the corresponding bit clear in k1 retain their 
previous values or are set to 0.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F3A.W1 54 /r ib
VFIXUPIMMPD xmm1 {k1}{z}, xmm2, 
AVX512FFix up special numbers in float64 vector xmm1, float64 
vector xmm2 and int64 vector xmm3/m128/m64bcst 
and store the result in xmm1, under writemask.
EVEX.256.66.0F3A.W1 54 /r ib
VFIXUPIMMPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst, imm8AV / V A V X 5 1 2 V L
AVX512FFix up special numbers in float64 vector ymm1, float64 
vector ymm2 and int64 ve ctor ymm3/m256/m64bcst 
and store the result in ymm1, under writemask.
EVEX.512.66.0F3A.W1 54 /r ib
VFIXUPIMMPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst{sae}, imm8A V/V AVX512F Fix up elements of fl oat64 vector in zmm2 using int64 
vector table in zmm3/m512/m64bcst, combine with 
preserved elements from zmm1, and store the result in zmm1.
A Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) imm8VFIXUPIMMPD—Fix Up Special Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-181Operation
enum TOKEN_TYPE
{
QNAN_TOKEN := 0,SNAN_TOKEN := 1,ZERO_VALUE_TOKEN := 2,POS_ONE_VALUE_TOKEN := 3,NEG_INF_TOKEN := 4,POS_INF_TOKEN := 5,NEG_VALUE_TOKEN := 6,POS_VALUE_TOKEN := 7
}
FIXUPIMM _DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0] ){
tsrc[63:0] := ((src1[62:52] = 0) AN D (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]
CASE(tsrc[63:0] of TOKEN_TYPE) {
QNAN_TOKEN: j := 0;SNAN_TOKEN: j := 1;ZERO_VALUE_TOKEN: j := 2;POS_ONE_VALUE_TOKEN: j := 3;NEG_INF_TOKEN: j := 4;POS_INF_TOKEN: j := 5;NEG_VALUE_TOKEN: j := 6;POS_VALUE_TOKEN: j := 7;
} ; end source special CASE(tsrc…)
; The required response from src3 table is extracted
token_response[3:0] = tbl3[3+4*j:4*j];
CASE(token_response[3:0]) {
0000: dest[63:0] := dest[63:0];  ; preserve content of DEST0001: dest[63:0] := tsrc[63:0];   ; pass thro ugh src1 normal input value, denormal as zero
0010: dest[63:0] := QNaN(tsrc[63:0]);0011: dest[63:0] := QNAN_Indefinite;0100: dest[63:0] := -INF;0101: dest[63:0] := +INF;0110: dest[63:0] := tsrc.sign? –INF : +INF;0111: dest[63:0] := -0;1000: dest[63:0] := +0;1001: dest[63:0] := -1;1010: dest[63:0] := +1;1011: dest[63:0] := ½;1100: dest[63:0] := 90.0;1101: dest[63:0] := PI/2;1110: dest[63:0] := MAX_FLOAT;1111: dest[63:0] := -MAX_FLOAT;
} ; end of token_response CASE
; The required fault reporting from imm8 is extracted
; TOKENs are mutually exclusive and TOKENs priority defines the order.   
; Multiple faults related to a si ngle token can occur simultaneously
.
IF (tsrc[63:0] of TOKEN_TYPE: ZERO_V ALUE_TOKEN) AND imm8 [0] then set #ZE;
IF (tsrc[63:0] of TOKEN_TYPE: ZERO_V ALUE_TOKEN) AND imm8 [1] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: ONE_VA LUE_TOKEN) AND imm8[2] then set #ZE;VFIXUPIMMPD—Fix Up Special Packed Float64 ValuesINSTRUCTION SET REFERENCE, V

.
5-182 Vol. 2CIF (tsrc[63:0] of TOKEN_TYPE: ONE_VA LUE_TOKEN) AND imm8[3] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: SNAN _TOKEN) AND imm8[4 ] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: NEG_IN F_TOKEN) AND imm8[5] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: NEG_VA LUE_TOKEN) AND imm8[6] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
; end fault reporting 
return dest[63:0];
} ; end of FIXUPIMM_DP()
VFIXUPIMMPD 
THEN 
THEN
DEST[i+63:i] := FIXUPIMM_DP(DEST[i+63:i] , SRC1[i+63:i], SRC2[63:0], imm8 [7:0])
ELSE 
DEST[i+63:i] := FIXUPIMM_DP(DEST[i+63:i] , SRC1[i+63:i], SRC2[i +63:i], imm8 [7:0])
FI;
ELSE 
FI
FI;
Immediate Control Description:
Figure 5-9.  VFIXUPIMMPD Immediate Control Description76543210
+I N F  #IE
-I N F  #IE
SNaN #IE- VE  #IE
ONE  #IE
ONE  #ZE
ZERO #IE
ZERO #ZEVFIXUPIMMPD—Fix Up Special Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-183Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMPD __m512d _mm512_fixupimm_pd ( __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_mask_fixupimm_pd(__m512d s,  __mmask8 k, __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_maskz_fixupimm_pd( __m mask8 k, __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_fixupimm_round_pd( __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m512d _mm512_mask_fixupimm_r ound_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m512d _mm512_maskz_fixupimm_round_pd( __mma sk8 k, __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m256d _mm256_fixupimm_pd( __m2 56d a, m256d b, __m256i c, int imm8);
VFIXUPIMMPD __m256d _mm256_mask_fixupimm_pd(__m256d a, __mmask8 k, __m256d b, __m256i c, int imm8);
VFIXUPIMMPD __m256d _mm256_maskz_fixupimm_pd( __mmask 8 k, __m256d a, __m256d b, __m256i c, int imm8);
VFIXUPIMMPD __m128d _mm_fixupimm_pd( __m128 d a, __m128d b, __m128i c, int imm8);
VFIXUPIMMPD __m128d _mm_mask_fixupimm_pd(__m128d a,  __mmask8 k, __m128d b, __m128i c, int imm8);
VFIXUPIMMPD __m128d _mm_maskz_fixupimm_pd( __mmask 8 k, __m128d a, __m128d b, 128ic, int imm8);
Zero, Invalid.
See Table 2-46, “Type E2 Class Exception Conditions.”VFIXUPIMMPS—Fix Up Special Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
5-184 Vol. 2CVFIXUPIMMPS—Fix Up Specia l Packed Float32 Values
Perform fix-up of doubleword elements encoded in single pr ecision floating-point format in the first source operand 
(the second operand) using a 32-bit, two-level look-up ta ble specified in the corresponding doubleword element of 
The two-level look-up table perform a fix-up of each single  precision floating-point input data in the first source 
rect result. To deal with this, VFIXUPIMMPS can be used af ter the N-R reciprocal sequence to set the result to the 
MXCSR.DAZ is used and refer to zmm2 only (i.e., zmm1 is not considered as zero in case MXCSR.DAZ is set).MXCSR mask bits are ignored and are treated as if all mask  bits are set to masked response). If any of the imm8 
bits is set and the condition met for fault repo rting, MXCSR.IE or MXCSR.ZE might be updated.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F3A.W0 54 /r
VFIXUPIMMPS xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcst, imm8A V/V AVX512VL
AVX512FFix up special numbers in float32 vector xmm1, float32 
vector xmm2 and int32 vector xmm3/m128/m32bcst 
EVEX.256.66.0F3A.W0 54 /r
VFIXUPIMMPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst, imm8A V/V AVX512VL
AVX512FFix up special numbers in float32 vector ymm1, float32 
vector ymm2 and int32 vector ymm3/m256/m32bcst and store the result in ymm1, under writemask.
EVEX.512.66.0F3A.W0 54 /r ib
VFIXUPIMMPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst{sae}, imm8A V/V AVX512F Fix up elements of float32 vector in zmm2 using int32 
vector table in zmm3/m512/m32bcst, combine with 
A Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) imm8VFIXUPIMMPS—Fix Up Special Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-185Operation
{
}
FIXUPIMM _SP ( dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0] ){
tsrc[31:0] := ((src1[30:23] = 0) AN D (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]
CASE(tsrc[31:0] of TOKEN_TYPE) {
} ; end source special CASE(tsrc…) 
0000: dest[31:0] := dest[31:0];  ; preserve content of DEST0001: dest[31:0] := tsrc[31:0];   ; pass thro ugh src1 normal input value, denormal as zero
0010: dest[31:0] := QNaN(tsrc[31:0]);0011: dest[31:0] := QNAN_Indefinite;0100: dest[31:0] := -INF;0101: dest[31:0] := +INF;0110: dest[31:0] := tsrc.sign? –INF : +INF;0111: dest[31:0] := -0;1000: dest[31:0] := +0;1001: dest[31:0] := -1;1010: dest[31:0] := +1;1011:  dest[31:0] := ½;1100: dest[31:0] := 90.0;1101: dest[31:0] := PI/2;1110: dest[31:0] := MAX_FLOAT;1111: dest[31:0] := -MAX_FLOAT;
} ; end of token_response CASE 
; The required fault reporting from imm8 is extracted 
.
IF (tsrc[31:0] of TOKEN_TYPE: ZERO_V ALUE_TOKEN) AND imm8 [0] then set #ZE;
IF (tsrc[31:0] of TOKEN_TYPE: ZERO_V ALUE_TOKEN) AND imm8 [1] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: ONE_VA LUE_TOKEN) AND imm8[2] then set #ZE;VFIXUPIMMPS—Fix Up Special Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
5-186 Vol. 2CIF (tsrc[31:0] of TOKEN_TYPE: ONE_VA LUE_TOKEN) AND imm8[3] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: SNAN _TOKEN) AND imm8[4 ] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: NEG_IN F_TOKEN) AND imm8[5] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: NEG_VA LUE_TOKEN) AND imm8[6] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
return dest[31:0];
} ; end of FIXUPIMM_SP()
VFIXUPIMMPS (EVEX)
THEN 
THEN
DEST[i+31:i] := FIXUPIMM_S P(DEST[i+31:i], SRC1[i+31:i] , SRC2[31:0], imm8 [7:0])
ELSE 
DEST[i+31:i] := FIXUPIMM_S P(DEST[i+31:i], SRC1[i+31:i] , SRC2[i+31:i], imm8 [7:0])
FI;
ELSE 
FI
FI;
Figure 5-10.  VFIXUPIMMPS Immediate Control Description76543210

THEN 
THEN
ELSE 
FI;
ELSE 
FI
FI;
+I N F  #IE
-I N F  #IE
ONE  #IE
ONE  #ZE
ZERO #IE
ZERO #ZEVFIXUPIMMPS—Fix Up Special Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-187Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMPS __m512 _mm512_fixupimm_ps( __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_mask_fixupimm_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_maskz_fixupimm_ps( __mmask16 k, __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_fixupimm_round_ps ( __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m512 _mm512_mask_fixupimm_round_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m512 _mm512_maskz_fixupimm_round_ps( __mma sk16 k, __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m256 _mm256_fixupimm_ps( __m256 a, __m256 b, __m256i c, int imm8);VFIXUPIMMPS __m256 _mm256_mask_fixupimm_ps(__m256 a, __mmask8 k, __m256 b, __m256i c, int imm8);
VFIXUPIMMPS __m256 _mm256_maskz_fixupimm_ps( __mmask 8 k, __m256 a, __m256b, __m256i c, int imm8);
VFIXUPIMMPS __m128 _mm_fixupimm_ps( __m1 28 a, __m128 b, 128i c, int imm8);
VFIXUPIMMPS __m128 _mm_mask_fixupimm_ps(__m128 a, __mmask8 k, __m128 b, __m128i c, int imm8);VFIXUPIMMPS __m128 _mm_maskz_fixupimm_ps( __mmask8 k, __m128 a, __m128 b, __m128i c, int imm8);
See Table 2-46, “Type E2 Class Exception Conditions.”VFIXUPIMMSD—Fix Up Special Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
5-188 Vol. 2CVFIXUPIMMSD—Fix Up Special Scalar Float64 Value
Perform a fix-up of the low quadword element encoded in do uble precision floating-point format in the first source 
operand (the second operand) using a 32-bit, two-level l ook-up table specified in the low quadword element of the 
second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-up is 
selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the op mask k1 or table response action of 
0000b preserves the corresponding element of the first operand. The fixed-up element from the first source 
operand or the preserved element in the first operand becomes the low quadword element of the destination 
operand (the first operand). Bits 127:64 of the destination op erand is copied from the corresponding bits of the first 
source operand. The destination and first source operands  are XMM registers. The second source operand can be a 
XMM register or a 64- bit memory location.
Operation
{
}Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W1 55 /r ib
VFIXUPIMMSD xmm1 {k1}{z}, 
xmm2, xmm3/m64{sae}, imm8A V/V AVX512F Fix up a float64 number in the low quadword element of 
xmm2 using scalar int32 table in xmm3/m64 and store the 
AT u p l e 1  S c a l a r M o d R M : r e g  ( r ,  w ) E V EX.vvvv (r) ModRM:r/m (r) imm8VFIXUPIMMSD—Fix Up Special Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-189FIXUPIMM _DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0] ){
0000: dest[63:0] := dest[63:0]  ; preserve content of DEST0001: dest[63:0] := tsrc[63:0];   ; pass thro ugh src1 normal input value, denormal as zero
0010: dest[63:0] := QNaN(tsrc[63:0]);0011: dest[63:0] := QNAN_Indefinite;0100:dest[63:0] := -INF;0101: dest[63:0] := +INF;0110: dest[63:0] := tsrc.sign? –INF : +INF;0111: dest[63:0] := -0;1000: dest[63:0] := +0;1001: dest[63:0] := -1;1010: dest[63:0] := +1;1011: dest[63:0] := ½;1100: dest[63:0] := 90.0;1101: dest[63:0] := PI/2;1110: dest[63:0] := MAX_FLOAT;1111: dest[63:0] := -MAX_FLOAT;
.
IF (tsrc[63:0] of TOKEN_TYPE: ONE_VA LUE_TOKEN) AND imm8[2] then set #ZE;
IF (tsrc[63:0] of TOKEN_TYPE: ONE_VA LUE_TOKEN) AND imm8[3] then set #IE;
IF (tsrc[63:0] of TOKEN_TYPE: POS_IN F_TOKEN) AND imm8[7] then set #IE;
} ; end of FIXUPIMM_DP()VFIXUPIMMSD—Fix Up Special Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
5-190 Vol. 2CVFIXUPIMMSD (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[63:0] := FIXUPIMM_DP(DEST[63: 0], SRC1[63:0], SRC2[63:0], imm8 [7:0])
ELSE 
THEN *DEST[63:0] remains unchanged*ELSE  DEST[63:0] := 0 ; zeroing-masking
FI
VFIXUPIMMSD __m128d _mm_fixupimm_sd(  __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_ma sk_fixupimm_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_maskz_fixupimm_sd( __mm ask8 k, __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_fixupi mm_round_sd( __m128d a, __m12 8i tbl, int imm, int sae);
VFIXUPIMMSD __m128d _mm_mask_fixupimm_round_sd(__m128d s,  __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);
VFIXUPIMMSD __m128d _mm_mask z_fixupimm_round_sd( __mmask8 k, __m128 d a, __m128i tbl, int imm, int sae);
Zero, Invalid
See Table 2-47, “Type E3 Class Exception Conditions.”Figure 5-11.  VFIXUPIMMSD Im mediate Control Description76543210
+I N F  #IE
-I N F  #IE
ONE  #IE
ONE  #ZE
ZERO #IE
ZERO #ZEVFIXUPIMMSS—Fix Up Special Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-191VFIXUPIMMSS—Fix Up Specia l Scalar Float32 Value
Perform a fix-up of the low doubleword element encoded in si ngle precision floating-point format in the first source 
operand (the second operand) using a 32-bit, two-level l ook-up table specified in the low doubleword element of 
the second source operand (the third operand) with exce ption reporting specifier imm8. The element that is fixed-
up is selected by mask bit of 1 specif ied in the opmask k1. Mask bit of 0 in the opmask k1 or table response action 
of 0000b preserves the corresponding element of the firs t operand. The fixed-up element from the first source 
operand or the preserved element in the first operand becomes the low doubleword element of the destination

+I N F  #IE
-I N F  #IE
ONE  #IE
ONE  #ZE
ZERO #IE
operand or the preserved element in the first operand becomes the low doubleword element of the destination 
operand (the first operand) Bits 127:32 of the destination op erand is copied from the corresponding bits of the first 
XMM register or a 32-bit memory location.
that converts the input encoding in the first so urce operand with one of 16 response actions. 
MXCSR.DAZ is used and refer to zmm2 only (i.e., zmm1 is not considered as zero in case MXCSR.DAZ is set).
Operation
{
}Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W0 55 /r ib
VFIXUPIMMSS xmm1 {k1}{z}, xmm2, 
xmm3/m32{sae}, imm8A V/V AVX512F Fix up a float32 number in the low doubleword element 
in xmm2 using scalar int32 table in xmm3/m32 and store 
A Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) imm8VFIXUPIMMSS—Fix Up Special Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
5-192 Vol. 2CFIXUPIMM _SP (dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0] ){
; The required response from src3 table is extracted 
0010: dest[31:0] := QNaN(tsrc[31:0]);0011: dest[31:0] := QNAN_Indefinite;0100: dest[31:0] := -INF;0101: dest[31:0] := +INF;0110: dest[31:0] := tsrc.sign? –INF : +INF;0111: dest[31:0] := -0;1000: dest[31:0] := +0;1001: dest[31:0] := -1;1010: dest[31:0] := +1;1011: dest[31:0] := ½;1100: dest[31:0] := 90.0;1101: dest[31:0] := PI/2;1110: dest[31:0] := MAX_FLOAT;1111: dest[31:0] := -MAX_FLOAT;
.
IF (tsrc[31:0] of TOKEN_TYPE: ZERO_V ALUE_TOKEN) AND imm8[0] then set #ZE;
IF (tsrc[31:0] of TOKEN_TYPE: ZERO_V ALUE_TOKEN) AND imm8[1] then set #IE;
IF (tsrc[31:0] of TOKEN_TYPE: ONE_VA LUE_TOKEN) AND imm8[2] then set #ZE;
IF (tsrc[31:0] of TOKEN_TYPE: ONE_VA LUE_TOKEN) AND imm8[3] then set #IE;
} ; end of FIXUPIMM_SP()VFIXUPIMMSS—Fix Up Special Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-193VFIXUPIMMSS (EVEX encoded version)
THEN DEST[31:0] := FIXUPIMM_SP(DEST[31: 0], SRC1[31:0], SRC2[31:0], imm8 [7:0])
ELSE 
THEN *DEST[31:0] remains unchanged*ELSE  DEST[31:0] :=  0 ; zeroing-masking
FI
VFIXUPIMMSS __m128 _mm_ fixupimm_ss( __m128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_mask_fixup imm_ss(__m128 s, __mmask8 k, __m 128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_maskz_fi xupimm_ss( __mmask8 k, __m128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_ fixupimm_round_ss( __m128 a, __m128i tbl, int imm, int sae);
VFIXUPIMMSS __m128 _mm_mask_fix upimm_round_ss(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm, int sae);
VFIXUPIMMSS __m128 _mm_maskz_ fixupimm_round_ss( __mmask8 k, __m128 a, __m128i tbl, int imm, int sae);
See Table 2-47, “Type E3 Class Exception Conditions.”Figure 5-12.  VFIXUPIMMSS Immediate Control Description76543210
+ INF #IE
- INF #IE
ONE  #IE
ONE  #ZE
ZERO #IE
ZERO #ZEVFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-194 Vol. 2CVFMADD132PD/VFMADD213PD/VF MADD231PD—Fused Multiply-Add of Packed Double 
Precision Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W1 98 /r 
VFMADD132PD xmm1, xmm2, 
xmm3/m128A V/V FMA Multiply packed double precision floating-point 
values from xmm1 and xmm3/mem, add to xmm2 
and put result in xmm1.
VEX.128.66.0F38.W1 A8 /r 
VFMADD213PD xmm1, xmm2, 
xmm3/m128 A V/V FMA Multiply packed double precision floating-point 
values from xmm1 and xmm2, add to xmm3/mem 
VEX.128.66.0F38.W1 B8 /r 
VFMADD231PD xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed double precision floating-point 
values from xmm2 and xmm3/mem, add to xmm1 and put result in xmm1.
VEX.256.66.0F38.W1 98 /r
VFMADD132PD ymm1, ymm2, 
ymm3/m256A V/V FMA Multiply packed double precision floating-point 
values from ymm1 and ymm3/mem, add to ymm2 
and put result in ymm1.
VEX.256.66.0F38.W1 A8 /r 
VFMADD213PD ymm1, ymm2, 
values from ymm1 and ymm2, add to ymm3/mem 
VEX.256.66.0F38.W1 B8 /r 
VFMADD231PD ymm1, ymm2, 
values from ymm2 and ymm3/mem, add to ymm1 
EVEX.128.66.0F38.W1 98 /r 
VFMADD132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstB V/V AVX512VL
AVX512FMultiply packed double precision floating-point 
values from xmm1 and xmm3/m128/m64bcst, add to xmm2 and put result in xmm1.
EVEX.128.66.0F38.W1 A8 /r 
VFMADD213PD xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcstB V/V AVX512VL
values from xmm1 and xmm2, add to 
xmm3/m128/m64bcst and put result in xmm1.
EVEX.128.66.0F38.W1 B8 /r 
VFMADD231PD xmm1 {k1}{z}, xmm2, 
values from xmm2 and xmm3/m128/m64bcst, add 
to xmm1 and put result in xmm1.
EVEX.256.66.0F38.W1 98 /r 
VFMADD132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstB V/V AVX512VL
values from ymm1 and ymm3/m256/m64bcst, add to ymm2 and put result in ymm1.
EVEX.256.66.0F38.W1 A8 /r 
VFMADD213PD ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcstB V/V AVX512VL
values from ymm1 and ymm2, add to 
ymm3/m256/m64bcst and put result in ymm1.
EVEX.256.66.0F38.W1 B8 /r 
VFMADD231PD ymm1 {k1}{z}, ymm2, 
values from ymm2 and ymm3/m256/m64bcst, add 
to ymm1 and put result in ymm1.
EVEX.512.66.0F38.W1 98 /r 
VFMADD132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}B V/V AVX512F Multiply packed double precision floating-point 
values from zmm1 and zmm3/m512/m64bcst, add to zmm2 and put result in zmm1.
EVEX.512.66.0F38.W1 A8 /r 
VFMADD213PD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst{er}B V/V AVX512F Multiply packed double precision floating-point 
values from zmm1 and zmm2, add to 
zmm3/m512/m64bcst and put result in zmm1.
EVEX.512.66.0F38.W1 B8 /r

EVEX.512.66.0F38.W1 B8 /r 
VFMADD231PD zmm1 {k1}{z}, zmm2, 
values from zmm2 and zmm3/m512/m64bcst, add 
to zmm1 and put result in zmm1.VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-195Instruction Operand Encoding
Performs a set of SIMD multiply-add computation on pack ed double precision floating-point values using three 
source operands and writes the multiply-add results in the destination operand. The destination operand is also the 
first source operand. The second operand must be a SI MD register. The third source operand can be a SIMD 
register or a memory location. 
VFMADD132PD: Multiplies the two, four or eight packed doub le precision floating-point values from the first source 
operand to the two, four or eight packed double precision floating-point values in the third source operand, adds 
the infinite precision intermediate result to the two, four or eight packed double precision floating-point values in 
the second source operand, performs ro unding and stores the resulting two, four or eight packed double precision 
floating-point values to the destination operand (first source operand).
VFMADD213PD: Multiplies the two, four or eight packed do uble precision floating-point values from the second 
source operand to the two, four or eight packed double pr ecision floating-point values in the first source operand, 
adds the infinite precision intermediate result to the tw o, four or eight packed double precision floating-point 
values in the third source operand, performs rounding an d stores the resulting two, four or eight packed double 
precision floating-point values to the destination operand (first source operand).
VFMADD231PD: Multiplies the two, four or eight packed do uble precision floating-point values from the second 
source to the two, four or eight packed double precision fl oating-point values in the third source operand, adds the 
infinite precision intermediate result to the two, four or eight packed double precision floating-point values in the 
first source operand, performs rounding and stores the resulting two, four or eight packed double precision 
EVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in 
reg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a 
ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The 
destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also fi rst source operand) is a YMM register and encoded in 
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a 
YMM register or a 256-bit memory location and encoded in rm_field. 
VEX.128 encoded version: The destination operand (also fi rst source operand) is a XMM register and encoded in 
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a 
XMM register or a 128-bit memory loca tion and encoded in rm_field. The u pper 128 bits of the YMM destination 
register are zeroed.Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-196 Vol. 2COperation
In the operations below, “*” an d “+” symbols represent multiplica tion and addition  with infinite precisio n inputs and outputs ( no 
rounding).
VFMADD132PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN 
MAXNUM := 2
ELSEIF (VEX.256)
MAXNUM := 4
FIFor i = 0 to MAXNUM-1 {
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] + SRC2[n+63:n])
}IF (VEX.128) THEN
FI
VFMADD213PD DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] + SRC3[n+63:n])
FI
VFMADD231PD DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] + DEST[n+63:n])
FIVFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-197VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
IF (VL = 512) AND (EVEX.b = 1)
THEN
ELSE 
THEN DEST[i+63:i] := 
RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
ELSE 
FI
FI;
VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded versio n, when src3 operand is a memory source)
THEN 
THEN
DEST[i+63:i] := 
RoundFPControl_MXCSR(DEST[i+63: i]*SRC3[63:0] + SRC2[i+63:i])
ELSE 
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of  Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-198 Vol. 2CVFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)IF (VL = 512) AND (EVEX.b = 1)
THEN
ELSE 
RoundFPControl(SRC2[i+63:i]*D EST[i+63:i] + SRC3[i+63:i])
ELSE 
FI
FI;
VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+63: i]*DEST[i+63:i] + SRC3[63:0])
ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i] *DEST[i+63:i] + SRC3[i+63:i])
FI;
ELSE 
FI
FI;
Vol. 2C 5-199VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(SRC2[i+63:i]*SR C3[i+63:i] + DEST[i+63:i])
ELSE 
FI
FI;
VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded versio n, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])
ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i ]*SRC3[i+63:i] + DEST[i+63:i])
FI;
ELSE 
FI
FI;
5-200 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxPD __m512d _mm512_fmadd_pd(__m512d a, __m512d b, __m512d c);
VFMADDxxxPD __m512d _mm512_fmadd_round_pd( __m512d a, __m512d b, __m512d c, int r);

FI
FI;
THEN 
THEN
ELSE 
FI;
ELSE 
FI
FI;
VFMADDxxxPD __m512d _mm512_mask_fmadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);VFMADDxxxPD __m512d _mm512_maskz_fmadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);VFMADDxxxPD __m512d _mm512_mask3_fmadd_pd(__m 512d a, __m512d b, __m512d c, __mmask8 k);
VFMADDxxxPD __m512d _mm512_mask_fmadd_round_pd(__m5 12d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMADDxxxPD __m512d _mm512_maskz_fmadd_round_pd(__mma sk8 k, __m512d a, __m512d b, __m512d c, int r);
VFMADDxxxPD __m512d _mm512_mask3_fmadd_round_pd(__m512 d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMADDxxxPD __m256d _mm256_mask_fmadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);VFMADDxxxPD __m256d _mm256_maskz_fmadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);VFMADDxxxPD __m256d _mm256_mask3_fmadd_pd(__m 256d a, __m256d b, __m256d c, __mmask8 k);
VFMADDxxxPD __m128d _mm_mask_fmadd_pd(__m128 d a, __mmask8 k, __m128d b, __m128d c);
VFMADDxxxPD __m128d _mm_maskz_fmadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);VFMADDxxxPD __m128d _mm_mask3_fmadd_pd(__m1 28d a, __m128d b, __m128d c, __mmask8 k);
VFMADDxxxPD __m128d _mm_fmadd_pd (__m128d a, __m128d b, __m128d c);VFMADDxxxPD __m256d _mm256_fmadd_pd (__m256d a, __m256d b, __m256d c);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VF[,N]MADD[132,213,231]PH—Fused Multiply-Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-201VF[,N]MADD[132,213,231]PH—Fused Mult iply-Add of Packed FP16 Values
Opcode/
En64/32 
Bit Mode 
EVEX.128.66.MAP6.W0  98 /r
VFMADD132PH xmm1{k1}{z}, xmm2, 
AVX512VLMultiply packed FP16 values from xmm1 and 
xmm3/m128/m16bcst, add to xmm2, and store 
EVEX.256.66.MAP6.W0  98 /r
VFMADD132PH ymm1{k1}{z}, ymm2, 
ymm3/m256/m16bcstA V/V AVX512-FP16 
AVX512VLMultiply packed FP16 values from ymm1 and 
ymm3/m256/m16bcst, add to ymm2, and store the result in ymm1.
EVEX.512.66.MAP6.W0  98 /r
VFMADD132PH  zmm1{k1}{z},  zmm2,  
zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed FP16 values from zmm1 and 
zmm3/m512/m16bcst, add to zmm2, and store 
the result in zmm1.
EVEX.128.66.MAP6.W0  A8 /r
VFMADD213PH xmm1{k1}{z}, xmm2, 
xmm2, add to xmm3/m128/m16bcst, and store 
EVEX.256.66.MAP6.W0  A8 /r
VFMADD213PH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstA V/V AVX512-FP16 
ymm2, add to ymm3/m256/m16bcst, and store 
the result in ymm1.
EVEX.512.66.MAP6.W0  A8 /r
VFMADD213PH  zmm1{k1}{z},  zmm2,  
zmm2, add to zmm3/m512/m16bcst, and store the result in zmm1.
EVEX.128.66.MAP6.W0  B8 /r
VFMADD231PH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcstA V/V AVX512-FP16 
AVX512VLMultiply packed FP16 values from xmm2 and 
xmm3/m128/m16bcst, add to xmm1, and store 
EVEX.256.66.MAP6.W0  B8 /r
VFMADD231PH ymm1{k1}{z}, ymm2, 
AVX512VLMultiply packed FP16 values from ymm2 and 
ymm3/m256/m16bcst, add to ymm1, and store 
EVEX.512.66.MAP6.W0  B8 /r
VFMADD231PH  zmm1{k1}{z},  zmm2,  
zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed FP16 values from zmm2 and 
zmm3/m512/m16bcst, add to zmm1, and store the result in zmm1.
EVEX.128.66.MAP6.W0  9C /r
VFNMADD132PH  xmm1{k1}{z},  
xmm2,  xmm3/m128/m16bcstA V/V AVX512-FP16 
xmm3/m128/m16bcst, and negate the value. 
Add this value to xmm2, and store the result in xmm1.
EVEX.256.66.MAP6.W0  9C /r
VFNMADD132PH  ymm1{k1}{z},  
ymm2,  ymm3/m256/m16bcstA V/V AVX512-FP16 
ymm3/m256/m16bcst, and negate the value. 
Add this value to ymm2, and store the result in 
ymm1.
EVEX.512.66.MAP6.W0  9C /r
VFNMADD132PH  zmm1{k1}{z},  
zmm2,  zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed FP16 values from zmm1 and 
zmm3/m512/m16bcst, and negate the value. 
Add this value to zmm2, and store the result in 
zmm1.
EVEX.128.66.MAP6.W0  AC /r
VFNMADD213PH  xmm1{k1}{z},  
xmm2, and negate the value. Add this value to 
xmm3/m128/m16bcst, and store the result in xmm1.
EVEX.256.66.MAP6.W0  AC /r
VFNMADD213PH  ymm1{k1}{z},  
ymm2, and negate the valu e. Add this value to 
ymm3/m256/m16bcst, and store the result in ymm1.VF[,N]MADD[132,213,231]PH—Fused Multiply-Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-202 Vol. 2CInstruction Operand Encoding
This instruction performs a packed multiply-add or negated multiply-add computation on FP16 values using three 
source operands and writes the results in the destination operand. The destination operand is also the first source operand. The “N” (negated) forms of this instruction add th e negated infinite precision intermediate product to the 
corresponding remaining operand. The notation’ “132”, “213”  and “231” indicate the use of the operands in ±A * B 
+ C, where each digit corresponds to the operand number,  with the destination being operand 1; see Table 5-2.
The destination elements are upda ted according to the writemask.EVEX.512.66.MAP6.W0  AC /r
VFNMADD213PH  zmm1{k1}{z},  
zmm2,  zmm3/m512/m16bcst  {er}AV / V A V X 5 1 2 - F P 1 6 M u l t i p l y  p a c k e d  FP16 values from zmm1 and 
zmm2, and negate the valu e. Add this value to 
zmm3/m512/m16bcst, and store the result in 
zmm1.
EVEX.128.66.MAP6.W0  BC /r
VFNMADD231PH  xmm1{k1}{z},  
Add this value to xmm1, and store the result in 
xmm1.
EVEX.256.66.MAP6.W0  BC /r
VFNMADD231PH  ymm1{k1}{z},  
AVX512VLMultiply packed FP16 values from  ymm2 and 
Add this value to ymm1, and store the result in 
ymm1.
EVEX.512.66.MAP6.W0  BC /r
VFNMADD231PH  zmm1{k1}{z},  
zmm2,  zmm3/m512/m16bcst  {er}AV / V A V X 5 1 2 - F P 1 6 M u l t i p l y  p a c k e d  FP16 values from zmm2 and 
Add this value to zmm1, and store the result in zmm1.
A Full ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Table 5-2.  VF[,N]MADD[132,213,231]PH Notation for Operands
Notation Operands
132 dest =  ± dest*src3+src2
231 dest =  ± src2*src3+dest
213 dest =  ± src2*dest+src3Opcode/
En64/32 
Bit Mode 
FlagDescriptionVF[,N]MADD[132,213,231]PH—Fused Multiply-Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-203Operation
VF[,N]MADD132PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
ELSE
IF *negative form*:
DEST.fp16[j] := RoundFPControl(-DEST .fp16[j]*SRC3.fp16[j] + SRC2.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(DEST. fp16[j]*SRC3.fp16[j] + SRC2.fp16[j])
DEST[MAXVL-1:VL] := 0VF[,N]MADD132PH DEST, SRC2, SRC3 (EVEX encoded vers ions) when src3 operand is a memory source 
t3 := SRC3.fp16[0]
ELSE:
t3 := SRC3.fp16[j]
DEST.fp16[j] := RoundFPControl(-DEST.fp16[j] * t3 + SRC2.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(D EST.fp16[j] * t3 + SRC2.fp16[j])
DEST[MAXVL-1:VL] := 0 VF[,N]MADD[132,213,231]PH—Fused Multiply-Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-204 Vol. 2CVF[,N]MADD213PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
ELSE
DEST.fp16[j] := RoundFPControl(-SRC2 .fp16[j]*DEST.fp16[j] + SRC3.fp16[j])
ELSE
DEST.fp16[j] := RoundFPControl(SRC2. fp16[j]*DEST.fp16[j] + SRC3.fp16[j])
DEST[MAXVL-1:VL] := 0VF[,N]MADD213PH DEST, SRC2, SRC3 (EVEX encoded vers ions) when src3 operand is a memory source 
ELSE:

ELSE
ELSE
ELSE:
DEST.fp16[j] := RoundFPControl(-SR C2.fp16[j] * DEST.fp16[j] + t3 )
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * DEST.fp16[j] + t3 )
Vol. 2C 5-205VF[,N]MADD231PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
ELSE
IF *negative form:
DEST.fp16[j] := RoundFPControl(-SRC2.fp16[j]*SRC3.fp16[j] + DEST.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2. fp16[j]*SRC3.fp16[j] + DEST.fp16[j])
DEST[MAXVL-1:VL] := 0 VF[,N]MADD231PH DEST, SRC2, SRC3 (EVEX encoded vers ions) when src3 operand is a memory source 
ELSE:
DEST.fp16[j] := RoundFPControl(-SRC2.fp16[j] * t3 + DEST.fp16[j] )
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * t3 + DEST.fp16[j] )
DEST[MAXVL-1:VL] := 0VF[,N]MADD[132,213,231]PH—Fused Multiply-Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-206 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VFMADD132PH, VFMADD213PH  , and VFMADD231PH:
__m128h _mm_fmadd_ph (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fmadd_ph (__m128h a, __mmask8 k, __m128h b, __m128h c);__m128h _mm_mask3_fmadd_ph (__m128h a, __m128h b, __m128h c, __mmask8 k);
__m128h _mm_maskz_fmadd_ph (__mmask8 k, __m128h a, __m128h b, __m128h c);__m256h _mm256_fmadd_ph (__m256h a, __m256h b, __m256h c);__m256h _mm256_mask_fmadd_ph (__m256h a,  __mmask16 k, __m256h b, __m256h c);
__m256h _mm256_mask3_fmadd_ph (__m256h a, __m256h b, __m256h c, __mmask16 k);
__m256h _mm256_maskz_fmadd_ph (__mmask16  k, __m256h a, __m256h b, __m256h c);
__m512h _mm512_fmadd_ph (__m512h a, __m512h b, __m512h c);__m512h _mm512_mask_fmadd_ph (__m512h a,  __mmask32 k, __m512h b, __m512h c);
__m512h _mm512_mask3_fmadd_ph (__m512h a, __m512h b, __m512h c, __mmask32 k);
__m512h _mm512_maskz_fmadd_ph (__mmask32  k, __m512h a, __m512h b, __m512h c);
__m512h _mm512_fmadd_round_ph (__m512h a, __m512h b, __m512h c, const int rounding);__m512h _mm512_mask_fmadd_round_ph (__m512h a, __mma sk32 k, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask3_fmadd_round_ph (__m512h a, __m5 12h b, __m512h c, __mmask32 k, const int rounding);
__m512h _mm512_maskz_fmadd_round_ph (__mmask32 k, __m 512h a, __m512h b, __m512h c, const int rounding);
VFNMADD132PH, VFNMADD213 PH, and VFNMADD231PH:
__m128h _mm_fnmadd_ph (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fnmadd_ph (__m128h a, __mmask8 k, __m128h b, __m128h c);__m128h _mm_mask3_fnmadd_ph (__m128h a, __m128h b, __m128h c, __mmask8 k);__m128h _mm_maskz_fnmadd_ph (__mmask8 k, __m128h a, __m128h b, __m128h c);__m256h _mm256_fnmadd_ph (__m256h a, __m256h b, __m256h c);__m256h _mm256_mask_fnmadd_ph (__m256h a,  __mmask16 k, __m256h b, __m256h c);
__m256h _mm256_mask3_fnmadd_ph (__m256h a, __m256h b, __m256h c, __mmask16 k);__m256h _mm256_maskz_fnmadd_ph (__mmask16 k, __m256h a, __m256h b, __m256h c);__m512h _mm512_fnmadd_ph (__m512h a, __m512h b, __m512h c);__m512h _mm512_mask_fnmadd_ph (__m512h a,  __mmask32 k, __m512h b, __m512h c);
__m512h _mm512_mask3_fnmadd_ph (__m512h a, __m512h b, __m512h c, __mmask32 k);__m512h _mm512_maskz_fnmadd_ph (__mmask32 k, __m512h a, __m512h b, __m512h c);__m512h _mm512_fnmadd_round_ph (__m512h a, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask_fnmadd_round_ph (__m512h a, __mma sk32 k, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask3_fnmadd_round_ph (__m512h a, __m 512h b, __m512h c, __mmask32 k, const int rounding);
__m512h _mm512_maskz_fnmadd_round_ph (__mmask32 k, __m512h a, __m512h b, __m512h c, const int rounding);
Invalid, Underflow, Overflow, Precision, Denormal
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VFMADDRND231PD - Fused Multiply-Add of Packed Double-Pre cision Floating-Point Values with rounding controlINSTRUCTION SET REFERENCE, V
Vol. 2C 5-207VFMADDRND231PD - Fused Multiply -Add of Packed Double-Precisi on Floating-Point Values 
with rounding control
Multiplies the two or four packed double-precision floating -point values from the second source operand to the two 
or four packed double-precision floating-point values in the third source operand, adds the infinite precision inter-
mediate result to the two or four packed double-precisi on floating-point values in the first source operand, 
performs rounding and stores the resulting two or four pack ed double-precision floating-point values to the desti-
nation operand (first source operand). 
The immediate byte defines several bit fields that co ntrol rounding, DAZ, FTZ, and exception suppression 
(SeeTable 5-3).The rounding mode specified in MXCSR.RC  may be bypassed if the immediate bit called MS1 
(MXCSR.RC Override) is set. Likewise , the MXCSR.FTZ and MXCSR.DAZ may also  be bypassed if the immediate bit 
called MS2 (MXCSR.FTZ/DAZ Override) is set. In case SA E (Suppress All Exceptions) bit is set (i.e. imm8[3] = 1), 
the status flags in MXCSR are not updated and no SIMD fl oating-point exceptions are raised. When SAE bit is not 
set (i.e. imm8[3] = 0) then SIMD floating-point exceptio ns are signaled according to the MXCSR. If any result 
operand is an SNaN then it will be converted to a QNaN. 
InstructionMode 
Feature 
VEX.DDS.128.66.0F3A.W1 B8 /r /ib V/V FMA Multiply packed double-precision 
floating-point values from xmm1 
and xmm2/mem, add to xmm0 and 
put result in xmm0.VFMADDRND231PD xmm0, 
xmm1, xmm2/m128, imm8
VEX.DDS.256.66.0F3A.W1 B8 /r /ib V/V FMA Multiply packed double-precision 
floating-point values from ymm1 
and ymm2/mem, add to ymm0 and 
put result in ymm0.VFMADDRND231PD ymm0, 
ymm1, ymm2/m256, imm8VFMADDRND231PD - Fused Multiply-Add of Packed Double-Preci sion Floating-Point Values with rounding controlINSTRUCTION SET REFERENCE, V
5-208 Vol. 2CTable 5-3.  Immediate Byte Encoding
Compiler tools may optionally support the complement ary mnemonic VMADDRND321PD. The behavior of the 
complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic 
defined in the opcode/instruction column. See also Sectio n 2.3.1, “FMA Instruction Operand Order and Arithmetic 
Behavior”
Operation
In the operations below, “+” and “*” sym bols represent multipli cation and addition with  infinite precisi on inputs and outputs ( no rounding)
VFMADDRND231PD DEST, SRC2, SRC3, imm8
MAXVL =2
MAXVL = 4
FIIF (imm8[3] = 1) THEN
Suppress_SIMD_Excepti on_Signaling_Reporting();
FIFor i = 0 to MAXVL-1 {
n = 64*i;DEST[n+63:n]  RoundFPControl_Imm((SRC2[n+63:n]*SRC3 [n+63:n] + DEST[n+63:n]), imm8)
}IF (VEX.128) THENDEST[255:128]  0
FIBits Field Name/value Description Comment
Imm8[1:0
]RC=0 Round to nearest
evenIf Imm8[2] =
1
RC=1 Round downRC=2 Round up
RC=3 Truncate
Imm8[2] MS1=0 Use MXCSR.RC for
rounding
MS1=1 Use Imm8[1:0] for
roundingIgnore MXC-
SR.RC 
Imm8[3] SAE=0 Use MXCSR Excep-
tion Mask settings
SAE=1 Suppress all Excep-
tion signalingNumerical re-
sult is comput-
ed as if FPexceptions are
masked.
Imm8[4] MS2=0 Use MXCSR.DAZ and
MXCSR.FTZ
MS2=1 Use Imm8[6:5] to
control DAZ/FTZ op-erationIgnore MXC-
SR.DAZ andMXCSR.FTZ
Imm8[5] DAZ Control DAZ IF MS2 = 1
Imm8[6] FTZ Control FTZ IF MS2 = 1Imm8[7] MBZ Must be zeroVFMADDRND231PD - Fused Multiply-Add of Packed Double-Pre cision Floating-Point Values with rounding controlINSTRUCTION SET REFERENCE, V
Vol. 2C 5-209IF (imm8[3] = 1) THEN
Resume_SIMD_Excepti on_Signaling_Reporting();
FI
VFMADDRND231PD __m128d _mm_fmaddround_pd (__m128d a, __m128d b, __m128d c,  const int ctrl);
VFMADDRND231PD __m256d _mm256_fmaddround_pd (__m256d a, __m256d b, __m256d c,  const int ctrl);
IF imm[3] = 1 Then 
None
Else

rounding
SR.RC 
masked.
MXCSR.FTZ
FI
None
Else
Overflow, Underflow, Inva lid, Precision, Denormal
FI
See Exceptions Type 2VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-210 Vol. 2CVFMADD132PS/VFMADD213PS/VFMADD231PS—Fu sed Multiply-Add of Packed Single 
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W0 98 /r 
VFMADD132PS xmm1, xmm2, 
xmm3/m128A V/V FMA Multiply packed single precision floating-point values 
from xmm1 and xmm3/mem, add to xmm2 and put 
VEX.128.66.0F38.W0 A8 /r 
VFMADD213PS xmm1, xmm2, 
from xmm1 and xmm2, add to xmm3/mem and put 
VEX.128.66.0F38.W0 B8 /r 
VFMADD231PS xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed single precision floating-point values 
from xmm2 and xmm3/mem, add to xmm1 and put result in xmm1.
VEX.256.66.0F38.W0 98 /r 
VFMADD132PS ymm1, ymm2, 
ymm3/m256A V/V FMA Multiply packed single precision floating-point values 
from ymm1 and ymm3/mem, add to ymm2 and put 
VEX.256.66.0F38.W0 A8 /r 
VFMADD213PS ymm1, ymm2, 
from ymm1 and ymm2, add to ymm3/mem and put 
VEX.256.66.0F38.0 B8 /r 
VFMADD231PS ymm1, ymm2, 
from ymm2 and ymm3/mem, add to ymm1 and put 
EVEX.128.66.0F38.W0 98 /r 
VFMADD132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstB V/V AVX512VL
AVX512FMultiply packed single prec ision floating-point values 
from xmm1 and xmm3/m128/m32bcst, add to xmm2 and put result in xmm1.
EVEX.128.66.0F38.W0 A8 /r 
VFMADD213PS xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcstB V/V AVX512VL
from xmm1 and xmm2, add to 
xmm3/m128/m32bcst and put result in xmm1.
EVEX.128.66.0F38.W0 B8 /r 
VFMADD231PS xmm1 {k1}{z}, xmm2, 
from xmm2 and xmm3/m128/m32bcst, add to 
xmm1 and put result in xmm1.
EVEX.256.66.0F38.W0 98 /r 
VFMADD132PS ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcstB V/V AVX512VL
from ymm1 and ymm3/m256/m32bcst, add to ymm2 and put result in ymm1.
EVEX.256.66.0F38.W0 A8 /r 
VFMADD213PS ymm1 {k1}{z}, ymm2, 
from ymm1 and ymm2, add to 
ymm3/m256/m32bcst and put result in ymm1.
EVEX.256.66.0F38.W0 B8 /r 
VFMADD231PS ymm1 {k1}{z}, ymm2, 
from ymm2 and ymm3/m256/m32bcst, add to 
ymm1 and put result in ymm1.
EVEX.512.66.0F38.W0 98 /r 
VFMADD132PS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst{er}B V/V AVX512F Multiply pack ed single precision floating-point values 
from zmm1 and zmm3/m512/m32bcst, add to zmm2 and put result in zmm1.
EVEX.512.66.0F38.W0 A8 /r 
VFMADD213PS zmm1 {k1}{z}, zmm2, 
from zmm1 and zmm2, add to 
zmm3/m512/m32bcst and put result in zmm1.
EVEX.512.66.0F38.W0 B8 /r 
VFMADD231PS zmm1 {k1}{z}, zmm2, 
from zmm2 and zmm3/m512/m32bcst, add to 
zmm1 and put result in zmm1.VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-211Instruction Operand Encoding
Performs a set of SIMD multiply-add computation on pack ed single precision floating-point values using three 
VFMADD132PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the first 
source operand to the four, eight or sixteen packed single precision floating-point values in the third source operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single precision floating-
point values in the second source operand, performs roundi ng and stores the resulting fo ur, eight or sixteen packed 
single precision floating-point values to the destination operand (first source operand).
VFMADD213PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the second 
source operand to the four, eight or sixteen packed single precision floating-point values in the first source 
operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single precision floating-
point values in the third source operand, performs round ing and stores the resulting the four, eight or sixteen 
packed single precision floating-point values to the destination operand (first source operand).
VFMADD231PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the second 
point values in the first source operand, performs roundin g and stores the resulting four, eight or sixteen packed 
ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The 
Operation
VFMADD132PS DEST, SRC2, SRC3 
MAXNUM := 4
MAXNUM := 8
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(DES T[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])
DEST[MAXVL-1:128] := 0Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-212 Vol. 2CELSEIF (VEX.256)
FI
VFMADD213PS DEST, SRC2, SRC3 
MAXNUM := 4
MAXNUM := 8
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] + SRC3[n+31:n])
FI
VFMADD231PS DEST, SRC2, SRC3 
MAXNUM := 4
MAXNUM := 8
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])
FI
VFMADD132PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)IF (VL = 512) AND (EVEX.b = 1)
THEN
ELSE 
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
ELSE 
DEST[i+31:i] := 0VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-213FI
FI;
VFMADD132PS DEST, SRC2, SRC3 (EVEX encoded versio n, when src3 operand is a memory source)

FI
THEN
ELSE 
ELSE 
FI;
THEN 
THEN
DEST[i+31:i] := 
RoundFPControl_MXCSR(DEST[i+31: i]*SRC3[31:0] + SRC2[i+31:i])
ELSE 
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])FI;
ELSE 
FI
FI;
VFMADD213PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(SRC2[i+31:i]*DE ST[i+31:i] + SRC3[i+31:i])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-214 Vol. 2CVFMADD213PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+31: i]*DEST[i+31:i] + SRC3[31:0])
ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i] *DEST[i+31:i] + SRC3[i+31:i])
FI;
ELSE 
FI
FI;
VFMADD231PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(SRC2[i+31:i]*S RC3[i+31:i] + DEST[i+31:i])
ELSE 
FI
FI;
VFMADD231PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
i := j * 32IF k1[j] OR *no writemask*VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of  Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-215THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])
ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i ]*SRC3[i+31:i] + DEST[i+31:i])
FI;
ELSE 
FI
FI;
VFMADDxxxPS __m512 _mm512_fmadd_ps(__m512 a, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_fmadd_round_ps(__m512 a, __m512 b, __m512 c, int r);VFMADDxxxPS __m512 _mm512_mask_fmadd_ps( __m512 a, __mmask16 k, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_maskz_fmadd_ps(__mma sk16 k, __m512 a, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_mask3_fmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);VFMADDxxxPS __m512 _mm512_mask_fmadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);VFMADDxxxPS __m512 _mm512_maskz_fmadd_round_ps(__ mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMADDxxxPS __m512 _mm512_mask3_fmadd_round_ps(__m 512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMADDxxxPS __m256 _mm256_mask_fmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);VFMADDxxxPS __m256 _mm256_maskz_fmadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);VFMADDxxxPS __m256 _mm256_mask3_fmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);VFMADDxxxPS __m128 _mm_mask_fmadd_ps(__m128  a, __mmask8 k, __m128 b, __m128 c);
VFMADDxxxPS __m128 _mm_maskz_fmadd_ps(__m mask8 k, __m128 a, __m128 b, __m128 c);
VFMADDxxxPS __m128 _mm_mask3_fmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);VFMADDxxxPS __m128 _mm_fmadd_ps (__m128 a, __m128 b, __m128 c);VFMADDxxxPS __m256 _mm256_fmadd_ps (__m256 a, __m256 b, __m256 c);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of  Scalar Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-216 Vol. 2CVFMADD132SD/VFMADD213SD/VFMA DD231SD—Fused Multiply-A dd of Scalar Double 
Performs a SIMD multiply-add computation on the low doub le precision floating-point values using three source 
operands and writes the multiply-add re sult in the destination operand. The destination operand is also the first 
source operand. The first and second operand are XMM regi sters. The third source operand can be an XMM register 
or a 64-bit memory location. 
VFMADD132SD: Multiplies the low double precision floating-point value from the first source operand to the low 
double precision floating-point value in the third source op erand, adds the infinite precision intermediate result to 
the low double precision floating-point values in the se cond source operand, performs rounding and stores the 
resulting double precision floating-point value to the destination operand (first source operand).
VFMADD213SD: Multiplies the low double precision floating-p oint value from the second source operand to the low 
double precision floating-point value in the first source op erand, adds the infinite precision intermediate result to 
the low double precision floating-point value in the th ird source operand, performs rounding and stores the 
VFMADD231SD: Multiplies the low double precision floating-point value from the second source to the low double 
precision floating-point value in the third source operand, adds the infinite precision intermediate result to the low 
double precision floating-point value in the first source operand, performs rounding and stores the resulting double 
precision floating-point value to the destination operand (first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. 
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third sour ce operand is encoded in rm_field. 
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
EVEX encoded version: The low quadword element of th e destination is updated according to the writemask.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.LIG.66.0F38.W1 99 /r 
VFMADD132SD xmm1, xmm2, 
xmm3/m64A V/V FMA Multiply scalar double precision floating-point value 
from xmm1 and xmm3/m64, add to xmm2 and put 
VEX.LIG.66.0F38.W1 A9 /r 
VFMADD213SD xmm1, xmm2, 
from xmm1 and xmm2, add to xmm3/m64 and put 
VEX.LIG.66.0F38.W1 B9 /r
VFMADD231SD xmm1, xmm2, xmm3/m64A V/V FMA Multiply scalar double precision floating-point value 
from xmm2 and xmm3/m64, add to xmm1 and put result in xmm1.
EVEX.LLIG.66.0F38.W1 99 /r 
VFMADD132SD xmm1 {k1}{z}, xmm2, 
xmm3/m64{er}B V/V AVX512F Multiply scalar double precision floating-point value 
EVEX.LLIG.66.0F38.W1 A9 /r 
VFMADD213SD xmm1 {k1}{z}, xmm2, 
xmm3/m64{er} B V/V AVX512F Multiply scalar double precision floating-point value 
EVEX.LLIG.66.0F38.W1 B9 /r 
VFMADD231SD xmm1 {k1}{z}, xmm2, 
from xmm2 and xmm3/m64, add to xmm1 and put 
B Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of  Scalar Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-217Operation
VFMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(DEST[63:0]*SRC3[63:0] + SRC2[63:0])ELSE 

THEN
ELSE 
FI;
FI;DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0
VFMADD213SD DEST, SRC2, SRC3 (EVEX encoded version) 
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(S RC2[63:0]*DEST[63:0] + SRC3[63:0])
ELSE 
FI;
FI;DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of  Scalar Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-218 Vol. 2CVFMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(SRC2[63:0]*SRC3[63:0] + DEST[63:0])ELSE 
FI;
VFMADD132SD DEST, SRC2, SRC3 (VEX encoded version) 
DEST[63:0] := MAXVL-1:128RoundFPControl_M XCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
DEST[127:63] := DEST[127:63]DEST[MAXVL-1:128] := 0
VFMADD213SD DEST, SRC2, SRC3 (VEX encoded version) 
DEST[63:0] := RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])DEST[127:63] := DEST[127:63]DEST[MAXVL-1:128] := 0
VFMADD231SD DEST, SRC2, SRC3 (VEX encoded version) 
DEST[63:0] := RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])DEST[127:63] := DEST[127:63]DEST[MAXVL-1:128] := 0
VFMADDxxxSD __m128d _mm_fmadd_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFMADDxxxSD __m128d _mm_mask_fmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);VFMADDxxxSD __m128d _mm_maskz_fmadd_sd(__mma sk8 k, __m128d a, __m128d b, __m128d c);
VFMADDxxxSD __m128d _mm_mask3_fmadd_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);VFMADDxxxSD __m128d _mm_mask_fmadd_round_sd(__m128 d a, __mmask8 k, __m128d  b, __m128d c, int r);
VFMADDxxxSD __m128d _mm_maskz_fmadd_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);VFMADDxxxSD __m128d _mm_mask3_fmadd_round_sd(__m12 8d a, __m128d b, __m128d c, __mmask8 k, int r);
VFMADDxxxSD __m128d _mm_fmadd_sd (__m128d a, __m128d b, __m128d c);
Overflow, Underflow, Invalid, Precision, Denormal
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VF[,N]MADD[132,213,231]SH—Fused Mult iply-Add of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-219VF[,N]MADD[132,213,231]SH—Fused Mult iply-Add of Scalar FP16 Values
Performs a scalar multiply-add or negated multiply-add co mputation on the low FP16 values using three source 
operands and writes the result in the destination operand. The destination operand is also the first source operand. 
The “N” (negated) forms of this instruction add the negated infinite precision intermediate product to the corre-
sponding remaining operand. The notati on’ “132”, “213” and “231” indicate the use of the operands in ±A * B + C, 
where each digit corresponds to the operand number, with the destination being operand 1; see Table 5-4.
Bits 127:16 of the destination operand are preserved. Bi ts MAXVL-1:128 of the destination operand are zeroed. The 
low FP16 element of the destination is  updated according to the writemask.Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.66.MAP6.W0  99 /r
VFMADD132SH xmm1{k1}{z}, xmm2, 
xmm3/m16 {er}A V/V AVX512-FP16 Multiply FP16 values from xmm1 and xmm3/
m16, add to xmm2, and store the result in xmm1.
EVEX.LLIG.66.MAP6.W0  A9 /r
VFMADD213SH xmm1{k1}{z}, xmm2, xmm3/m16 {er}A V/V AVX512-FP16 Multiply FP16 values from xmm1 and xmm2, add 
to xmm3/m16, and store the result in xmm1.
EVEX.LLIG.66.MAP6.W0  B9 /r
VFMADD231SH xmm1{k1}{z}, xmm2, xmm3/m16 {er}A V/V AVX512-FP16 Multiply FP16 values from xmm2 and xmm3/
m16, add to xmm1, and store the result in xmm1.
EVEX.LLIG.66.MAP6.W0  9D /r
VFNMADD132SH  xmm1{k1}{z},  
xmm2,  xmm3/m16  {er}A V/V AVX512-FP16 Multiply FP16 values from xmm1 and xmm3/
m16, and negate the valu e. Add this value to 
xmm2, and store the result in xmm1.
EVEX.LLIG.66.MAP6.W0  AD /r
VFNMADD213SH  xmm1{k1}{z},  
xmm2,  xmm3/m16  {er}A V/V AVX512-FP16 Multiply FP16 values from xmm1 and xmm2, and 
negate the value. Add th is value to xmm3/m16, 
and store the result in xmm1.
EVEX.LLIG.66.MAP6.W0  BD /r
VFNMADD231SH  xmm1{k1}{z},  
xmm2,  xmm3/m16  {er}A V/V AVX512-FP16 Multiply FP16 values from xmm2 and xmm3/
xmm1, and store the result in xmm1.
AS c a l a r M o d R M : r e g  ( r ,  w ) V E X . vvvv (r) ModRM:r/m (r) N/A
Table 5-4.  VF[,N]MADD[132,213,231]SH Notation for Operands
213 dest = ± src2*dest+src3VF[,N]MADD[132,213,231]SH—Fused Multiply-Add of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
5-220 Vol. 2COperation
VF[,N]MADD132SH DEST, SRC2, SRC3 (EVEX encoded versions) 
IF EVEX.b = 1 and SRC3 is a register:
ELSE
DEST.fp16[0] := RoundFPControl(-DEST.fp16[0]*SRC3.fp16[0] + SRC2.fp16[0])
ELSE:
DEST.fp16[0] := RoundFPControl(DEST. fp16[0]*SRC3.fp16[0] + SRC2.fp16[0])
// else DEST.fp16[0] remains unchanged
//DEST[127:16] re mains unchanged
VF[,N]MADD213SH DEST, SRC2, SRC3 (EVEX encoded versions) 
ELSE
DEST.fp16[0] := RoundFPControl(-SRC2 .fp16[0]*DEST.fp16[0] + SRC3.fp16[0])
ELSE:
DEST.fp16[0] := RoundFPControl(SRC2. fp16[0]*DEST.fp16[0] + SRC3.fp16[0])
VF[,N]MADD231SH DEST, SRC2, SRC3 (EVEX encoded versions) 
ELSE
DEST.fp16[0] := RoundFPControl(-SRC2 .fp16[0]*SRC3.fp16[0] + DEST.fp16[0])
ELSE:
DEST.fp16[0] := RoundFPControl(SRC2. fp16[0]*SRC3.fp16[0] + DEST.fp16[0])
DEST[MAXVL-1:128] := 0VF[,N]MADD[132,213,231]SH—Fused Mult iply-Add of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-221Intel C/C++ Compiler Intrinsic Equivalent
VFMADD132SH, VFMADD213 SH, and VFMADD231SH:
__m128h _mm_fmadd_round_sh (__m128h a, __m128h b, __m128h c, const int rounding);__m128h _mm_mask_fmadd_round_sh (__m128h a, __mmas k8 k, __m128h b, __m128h c, const int rounding);
__m128h _mm_mask3_fmadd_round_sh (__m128h a, __m128 h b, __m128h c, __mmask8 k, const int rounding);
__m128h _mm_maskz_fmadd_round_sh (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);
__m128h _mm_fmadd_sh (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fmadd_sh (__m128h a,  __mmask8 k, __m128h b, __m128h c);
__m128h _mm_mask3_fmadd_sh (__m128h a, __m128h b, __m128h c, __mmask8 k);__m128h _mm_maskz_fmadd_sh (__mmask8 k, __m128h a, __m128h b, __m128h c);
VFNMADD132SH, VFNMADD213SH, and VFNMADD231SH:
__m128h _mm_fnmadd_round_sh (__m128h a, __m128h b, __m128h c, const int rounding);
__m128h _mm_mask_fnmadd_round_sh (__m128h a, __mmask8 k, __m128h b, __m128h c, const int rounding);__m128h _mm_mask3_fnmadd_round_sh (__m128h a, __m128 h b, __m128h c, __mmask8 k, const int rounding);
__m128h _mm_maskz_fnmadd_round_sh (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);__m128h _mm_fnmadd_sh (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fnmadd_sh (__m128h a, __mmask8 k, __m128h b, __m128h c);__m128h _mm_mask3_fnmadd_sh (__m128h a, __m128h b, __m128h c, __mmask8 k);
__m128h _mm_maskz_fnmadd_sh (__mmask8 k, __m128h a, __m128h b, __m128h c);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of  Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-222 Vol. 2CVFMADD132SS/VFMADD213SS/VFMADD 231SS—Fused Multiply-Add of Scalar Single Precision 
Performs a SIMD multiply-add computation on single prec ision floating-point values using three source operands

Performs a SIMD multiply-add computation on single prec ision floating-point values using three source operands 
and writes the multiply-add results in the destination op erand. The destination operand is also the first source 
operand. The first and second operands are XMM registers. The third source operand can be a XMM register or a 32-
bit memory location. 
VFMADD132SS: Multiplies the low single precision floating -point value from the first source operand to the low 
single precision floating-point value in the third source op erand, adds the infinite precision intermediate result to 
the low single precision floating-point value in the seco nd source operand, performs rounding and stores the 
resulting single precision floating-point value to  the destination operand (first source operand).
VFMADD213SS: Multiplies the low single precision floating -point value from the second source operand to the low 
single precision floating-point value in the first source oper and, adds the infinite precision intermediate result to the 
low single precision floating-point value in the third sour ce operand, performs rounding and stores the resulting 
single precision floating-point value to the destination operand (first source operand).
VFMADD231SS: Multiplies the low single precision floating-point value from the second source operand to the low 
the low single precision floating-point value in the first source operand, performs rounding and stores the resulting 
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.LIG.66.0F38.W0 99 /r 
VFMADD132SS xmm1, xmm2, 
xmm3/m32A V/V FMA Multiply scalar single precision floating-point value 
from xmm1 and xmm3/m32, add to xmm2 and put 
VEX.LIG.66.0F38.W0 A9 /r 
VFMADD213SS xmm1, xmm2, 
from xmm1 and xmm2, add to xmm3/m32 and put 
VEX.LIG.66.0F38.W0 B9 /r 
VFMADD231SS xmm1, xmm2, xmm3/m32A V/V FMA Multiply scalar single precision floating-point value 
from xmm2 and xmm3/m32, add to xmm1 and put result in xmm1.
EVEX.LLIG.66.0F38.W0 99 /r 
VFMADD132SS xmm1 {k1}{z}, xmm2, 
xmm3/m32{er}B V/V AVX512F Multiply scalar single precision floating-point value 
EVEX.LLIG.66.0F38.W0 A9 /r 
VFMADD213SS xmm1 {k1}{z}, xmm2, 
EVEX.LLIG.66.0F38.W0 B9 /r 
VFMADD231SS xmm1 {k1}{z}, xmm2, 
from xmm2 and xmm3/m32, add to xmm1 and put 
B Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of  Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-223EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mn emonic for each instruction mnemonic listed in the 
opcode/instruction column of the summary table. The be havior of the complementary mnemonic in situations 
involving NANs are governed by the de finition of the instruction mnemonic defined in the opcode/instruction 
column.
Operation
VFMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
FI;
THEN DEST[31:0] := RoundFPControl(DEST[31:0]*SRC3[31:0] + SRC2[31:0])ELSE 
FI;
FI;DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(S RC2[31:0]*DEST[31:0] + SRC3[31:0])
ELSE 
FI;
FI;DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of  Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-224 Vol. 2CVFMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(SRC2[31:0]*SRC3[31:0] + DEST[31:0])ELSE 
THEN *DEST[31:0]] remains unchanged*ELSE ; zeroing-masking
FI;
VFMADD132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] + SRC2[31:0])DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFMADD213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] + SRC3[31:0])DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFMADD231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] + DEST[31:0])DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFMADDxxxSS __m128 _mm_fmadd_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_mask_fmadd_ss(__m1 28 a, __mmask8 k, __m128 b, __m128 c);
VFMADDxxxSS __m128 _mm_maskz_fmadd_ss(__mmask 8 k, __m128 a, __m128 b, __m128 c);
VFMADDxxxSS __m128 _mm_mask3_fmadd_ss(__m 128 a, __m128 b, __m128 c, __mmask8 k);
VFMADDxxxSS __m128 _mm_mask_fmadd _round_ss(__m128 a, __mmask8 k,  __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_maskz_fmad d_round_ss(__mmask8 k, __m128 a,  __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_mask3_fmadd_round_ss(__m128  a, __m128 b, __m128 c, __mmask8 k, int r);
VFMADDxxxSS __m128 _mm_fmadd_ss (__m128 a, __m128 b, __m128 c);
VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD— Fused Multiply-Alternating Add/Subt ract of Packed Double Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-225VFMADDSUB132PD/VFMADDSUB213PD/VFMADDS UB231PD—Fused Multiply-Alternating 
Add/Subtract of Packed Double Precision Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W1 96 /r 
VFMADDSUB132PD xmm1, xmm2, 
xmm3/m128A V/V FMA Multiply packed double precision floating-point values 
from xmm1 and xmm3/mem, add/subtract elements in 
xmm2 and put result in xmm1.
VEX.128.66.0F38.W1 A6 /r 
VFMADDSUB213PD xmm1, xmm2, 
xmm3/m128 A V/V FMA Multiply packed double precision floating-point values 
from xmm1 and xmm2, add/subtract elements in 
xmm3/mem and put result in xmm1.
VEX.128.66.0F38.W1 B6 /r 
VFMADDSUB231PD xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed double precision floating-point values 
from xmm2 and xmm3/mem, add/subtract elements in xmm1 and put result in xmm1.
VEX.256.66.0F38.W1 96 /r 
VFMADDSUB132PD ymm1, ymm2, 
ymm3/m256A V/V FMA Multiply packed double precision floating-point values 
from ymm1 and ymm3/mem, add/subtract elements in 
ymm2 and put result in ymm1.
VEX.256.66.0F38.W1 A6 /r 
VFMADDSUB213PD ymm1, ymm2, 
from ymm1 and ymm2, add/subtract elements in 
ymm3/mem and put result in ymm1.
VEX.256.66.0F38.W1 B6 /r 
VFMADDSUB231PD ymm1, ymm2, 
from ymm2 and ymm3/mem, add/subtract elements in 
EVEX.128.66.0F38.W1 A6 /r 
VFMADDSUB213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
AVX512FMultiply packed double precision floating-point values

from xmm1 and xmm2, add/subtract elements in xmm3/m128/m64bcst and put result in xmm1 subject 
EVEX.128.66.0F38.W1 B6 /r
VFMADDSUB231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
from xmm2 and xmm3/m128/m64bcst, add/subtract elements in xmm1 and put result in xmm1 subject to 
EVEX.128.66.0F38.W1 96 /r 
VFMADDSUB132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
from xmm1 and xmm3/m128/m64bcst, add/subtract elements in xmm2 and put result in xmm1 subject to 
EVEX.256.66.0F38.W1 A6 /r 
VFMADDSUB213PD ym m1 {k1}{z}, 
ymm2, ymm3/m256/m64bcstBV / V A V X 5 1 2 V L
from ymm1 and ymm2, add/subtract elements in ymm3/m256/m64bcst and put result in ymm1 subject 
EVEX.256.66.0F38.W1 B6 /r 
VFMADDSUB231PD ym m1 {k1}{z}, 
from ymm2 and ymm3/m256/m64bcst, add/subtract elements in ymm1 and put result in ymm1 subject to 
EVEX.256.66.0F38.W1 96 /r 
VFMADDSUB132PD ym m1 {k1}{z}, 
from ymm1 and ymm3/m256/m64bcst, add/subtract elements in ymm2 and put result in ymm1 subject to 
writemask k1.VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231P D—Fused Multiply-Alternating Add/Sub tract of Packed Double PrecisionINSTRUCTION SET REFERENCE, V
5-226 Vol. 2CInstruction Operand Encoding
VFMADDSUB132PD: Multiplies the two, four , or eight packed double precision floating-point values from the first 
source operand to the two or four packed double precision floating-point values in the third source operand. From 
the infinite precision intermediate result, adds the odd do uble precision floating-point elements and subtracts the 
even double precision floating-point values in the se cond source operand, performs rounding and stores the 
resulting two or four packed double precision floating-point values to the destination operand (first source 
operand).
VFMADDSUB213PD: Multiplies the two, four, or eight packed double precision floating-point values from the second 
source operand to the two or four packed double precision floating-point values in the first source operand. From 
even double precision floating-point values in the third source operand, performs rounding and stores the resulting 
two or four packed double precision floating-point valu es to the destination operand (first source operand).
VFMADDSUB231PD: Multiplies the two, four, or eight packed double precision floating-point values from the second 
even double precision floating-point values in the first source operand, performs rounding and stores the resulting 
EVEX encoded versions: The destination operand (also firs t source operand) and the second source operand are 
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 64-bit  memory location. The destination operand is condition-
ally updated with write mask k1.
YMM register or a 256-bit memory location and encoded in rm_field. EVEX.512.66.0F38.W1 A6 /r 
VFMADDSUB213PD zmm1 {k1}{z}, 
zmm2, zmm3/m512/m64bcst{er}B V/V AVX512F Multiply packed double precision floating-point values 
from zmm1and zmm2, add/subtract elements in 
zmm3/m512/m64bcst and put result in zmm1 subject 
EVEX.512.66.0F38.W1 B6 /r 
VFMADDSUB231PD zmm1 {k1}{z}, 
from zmm2 and zmm3/m512/m64bcst, add/subtract 
elements in zmm1 and put re sult in zmm1 subject to 
EVEX.512.66.0F38.W1 96 /r 
VFMADDSUB132PD zmm1 {k1}{z}, 
from zmm1 and zmm3/m512/m64bcst, add/subtract 
elements in zmm2 and put re sult in zmm1 subject to 
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AOpcode/
En64/32 
Bit Mode 
Feature 
FlagDescriptionVFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD— Fused Multiply-Alternating Add/Subt ract of Packed Double Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-227VEX.128 encoded version: The destination operand (also fi rst source operand) is a XMM register and encoded in 
column.
Operation
In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and output s (no 
VFMADDSUB132PD DEST, SRC2, SRC3 
DEST[63:0] := RoundFPControl_MXCSR( DEST[63:0]*SRC3[63:0] - SRC2[63:0])
DEST[127:64] := RoundFPControl_MXCSR(DES T[127:64]*SRC3[127:64] + SRC2[127:64])
DEST[191:128] := RoundFPControl_MXCSR(DES T[191:128]*SRC3[191:128] - SRC2[191:128])
DEST[255:192] := RoundFPControl_MXCSR(DES T[255:192]*SRC3[255:192] + SRC2[255:192]
FI
VFMADDSUB213PD DEST, SRC2, SRC3 
DEST[63:0] := RoundFPControl_MXCSR( SRC2[63:0]*DEST[63:0] - SRC3[63:0])
DEST[127:64] := RoundFPControl_MXCSR(SRC 2[127:64]*DEST[127:64] + SRC3[127:64])
DEST[191:128] := RoundFPControl_MXCSR(SRC 2[191:128]*DEST[191:128] - SRC3[191:128])
DEST[255:192] := RoundFPControl_MXCSR(SRC 2[255:192]*DEST[255:192] + SRC3[255:192]
FI
VFMADDSUB231PD DEST, SRC2, SRC3 
DEST[63:0] := RoundFPControl_MXCSR( SRC2[63:0]*SRC3[63:0] - DEST[63:0])
DEST[127:64] := RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])DEST[MAXVL-1:128] := 0
DEST[127:64] := RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])DEST[191:128] := RoundFPControl_MXCSR(SRC 2[191:128]*SRC3[191:128] - DEST[191:128])
DEST[255:192] := RoundFPControl_MXCSR(SRC 2[255:192]*SRC3[255:192] + DEST[255:192]
FI
VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231P D—Fused Multiply-Alternating Add/Sub tract of Packed Double PrecisionINSTRUCTION SET REFERENCE, V
5-228 Vol. 2CELSE 
THEN 
IF j *is even*
RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
ELSE DEST[i+63:i] := 
FI
ELSE 
FI
FI;
VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operan d is a memory source)
THEN 
THEN 
THEN
RoundFPControl_MXCSR(DEST[i+63: i]*SRC3[63:0] - SRC2[i+63:i])
ELSE 

THEN 
FI
ELSE 
FI
FI;
THEN 
THEN 
THEN
ELSE 
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
FI;ELSE 
THEN
ELSE 
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
FI;
FI
ELSE 
THEN *DEST[i+63:i] remains unchanged*VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD— Fused Multiply-Alternating Add/Subt ract of Packed Double Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-229ELSE ; zeroing-masking
FI
FI;
VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
THEN 
RoundFPControl(SRC2[i+63:i]*DE ST[i+63:i] - SRC3[i+63:i])
RoundFPControl(SRC2[i+63:i]*DE ST[i+63:i] + SRC3[i+63:i])
FI
ELSE 
FI
FI;
VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])
ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])FI;
ELSE 
IF (EVEX.b = 1) VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231P D—Fused Multiply-Alternating Add/Sub tract of Packed Double PrecisionINSTRUCTION SET REFERENCE, V
5-230 Vol. 2CTHEN
ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])FI;
FI
ELSE 
FI
FI;
VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 op erand is a register)
THEN
ELSE 
THEN 
RoundFPControl(SRC2[i+63:i]*S RC3[i+63:i] - DEST[i+63:i])
RoundFPControl(SRC2[i+63:i]*S RC3[i+63:i] + DEST[i+63:i])
FI
ELSE 
FI
FI;
VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operan d is a memory source)
THEN 
IF j *is even*VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD— Fused Multiply-Alternating Add/Subt ract of Packed Double Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-231THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i] *SRC3[i+63:i] - DEST[i+63:i])
FI;
ELSE 
THEN
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i] *SRC3[i+63:i] + DEST[i+63:i])
FI;
FI
ELSE 
FI
FI;
VFMADDSUBxxxPD __m512d _mm512_fmaddsub_pd(__m512d a, __m512d b, __m512d c);
VFMADDSUBxxxPD __m512d _mm512_fmaddsub_round_pd(__m512d a, __m512d b, __m512d c, int r);VFMADDSUBxxxPD __m512d _mm512_mask_fmaddsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);VFMADDSUBxxxPD __m512d _mm512_maskz_fmaddsub_pd( __mmask8 k, __m512d a, __m512d b, __m512d c);
VFMADDSUBxxxPD __m512d _mm512_mask3_fmaddsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);VFMADDSUBxxxPD __m512d _mm512_mask_fmaddsub_round_pd(__m 512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMADDSUBxxxPD __m512d _mm512_maskz_fmaddsub_round_pd(__m mask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMADDSUBxxxPD __m512d _mm512_mask3_fmaddsub_round_pd(__ m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMADDSUBxxxPD __m256d _mm256_mask_fmaddsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);VFMADDSUBxxxPD __m256d _mm256_maskz_fmaddsub_pd( __mmask8 k, __m256d a, __m256d b, __m256d c);
VFMADDSUBxxxPD __m256d _mm256_mask3_fmaddsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);VFMADDSUBxxxPD __m128d _mm_mask_fmaddsub_pd(__m1 28d a, __mmask8 k, __m128d b, __m128d c);
VFMADDSUBxxxPD __m128d _mm_maskz_fmaddsub_pd(__m mask8 k, __m128d a, __m128d b, __m128d c);
VFMADDSUBxxxPD __m128d _mm_mask3_fmaddsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);VFMADDSUBxxxPD __m128d _mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c);VFMADDSUBxxxPD __m256d _mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VFMADDSUB132PH/VFMADDSUB213PH/ VFMADDSUB231PH—Fused Multiply-Alternating  Add/Subtract of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-232 Vol. 2CVFMADDSUB132PH/VFMADDSUB 213PH/VFMADDSUB231PH—Fused Multiply-Alternating 
Add/Subtract of Packed FP16 Values
This instruction performs a packed multiply-add (odd el ements) or multiply-subtract (even elements) computation 
on FP16 values using three source operands and writes the results in the destination operand. The destination 
operand is also the first source operand. The notation’ “132 ”, “213” and “231” indicate the use of the operands in A 
* B ± C, where each digit corresponds to the operand number,  with the destination being operand 1; see Table 5-8.
The destination elements are upda ted according to the writemask.Opcode/
En64/32 
Bit Mode 
EVEX.128.66.MAP6.W0  96 /r
VFMADDSUB132PH  xmm1{k1}{z},  
AVX512VLMultiply packed FP16 va lues from xmm1 and 
xmm3/m128/m16bcst , add/subtract elements in 
xmm2, and store the result  in xmm1 subject to 
EVEX.256.66.MAP6.W0  96 /r
VFMADDSUB132PH  ymm1{k1}{z},  
AVX512VLMultiply packed FP16 va lues from ymm1 and 
ymm3/m256/m16bcst, add/subtract elements in 
ymm2, and store the result in ymm1 subject to writemask k1.
EVEX.512.66.MAP6.W0  96 /r
VFMADDSUB132PH  zmm1{k1}{z},  
zmm2,  zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed  FP16 values from zmm1 and 
zmm3/m512/m16bcst, add/subtract elements in 
zmm2, and store the result  in zmm1 subject to 
EVEX.128.66.MAP6.W0  A6 /r
VFMADDSUB213PH  xmm1{k1}{z},  
xmm2, add/subtract elements in xmm3/m128/m16bcst, and store the resu lt in xmm1 subject to 
EVEX.256.66.MAP6.W0  A6 /r
VFMADDSUB213PH  ymm1{k1}{z},  
ymm2, add/subtract elements in ymm3/m256/m16bcst, and store the resu lt in ymm1 subject to 
EVEX.512.66.MAP6.W0  A6 /r
VFMADDSUB213PH  zmm1{k1}{z},  
zmm2, add/subtract elements in zmm3/m512/m16bcst, and store the resu lt in zmm1 subject to 
EVEX.128.66.MAP6.W0  B6 /r
VFMADDSUB231PH  xmm1{k1}{z},  
AVX512VLMultiply packed FP16 va lues from xmm2 and 
xmm3/m128/m16bcst, add/subtract elements in xmm1, and store the result  in xmm1 subject to 
EVEX.256.66.MAP6.W0  B6 /r
VFMADDSUB231PH  ymm1{k1}{z},  
AVX512VLMultiply packed FP16 va lues from ymm2 and 
ymm3/m256/m16bcst, add/subtract elements in ymm1, and store the result in ymm1 subject to 
EVEX.512.66.MAP6.W0  B6 /r
VFMADDSUB231PH  zmm1{k1}{z},  
zmm2,  zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed  FP16 values from zmm2 and 
zmm3/m512/m16bcst, add/subtract elements in zmm1, and store the result  in zmm1 subject to 
A Full ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/AVFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH—Fused Multiply -Alternating Add/Subtract  of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-233Operation
VFMADDSUB132PH DEST, SRC2, SRC3 (EVEX encoded ve rsions) when src3 operand is a register 

ELSE
IF *j is even*:
DEST.fp16[j] := RoundFPControl(DEST.fp 16[j] * SRC3.fp16[j] - SRC2.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(DEST.fp 16[j] * SRC3.fp16[j] + SRC2.fp16[j])
DEST[MAXVL-1:VL] := 0 VFMADDSUB132PH DEST, SRC2, SRC3 (E VEX encoded versions) when src3 operand is a memory source 
ELSE:
DEST.fp16[j] := RoundFPControl(D EST.fp16[j] * t3 - SRC2.fp16[j])
ELSE:
DEST[MAXVL-1:VL] := 0Table 5-5.  VFMADDSUB[132,213,231]PH Notation for Odd and Even Elements
Notation Odd Elements Even Elements
132 dest = dest*src3+src2 dest = dest*src3-src2
231 dest = src2*src3+dest dest = src2*src3-dest213 dest = src2*dest+src3 dest = src2*dest-src3VFMADDSUB132PH/VFMADDSUB213PH/ VFMADDSUB231PH—Fused Multiply-Alternating  Add/Subtract of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-234 Vol. 2CVFMADDSUB213PH DEST, SRC2, SRC3 (EVEX encoded ve rsions) when src3 operand is a register 
ELSE
DEST.fp16[j] := RoundFPControl(SRC2. fp16[j]*DEST.fp16[j] - SRC3.fp16[j])
ELSE
DEST[MAXVL-1:VL] := 0 VFMADDSUB213PH DEST, SRC2, SRC3 (EVEX encoded vers ions) when src3 operand is a memory source
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * DEST.fp16[j] - t3)
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * DEST.fp16[j] + t3)
DEST[MAXVL-1:VL] := 0 VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH—Fused Multiply -Alternating Add/Subtract  of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-235VFMADDSUB231PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
ELSE
IF *j is even:
DEST.fp16[j] := RoundFPControl(SRC2.fp 16[j] * SRC3.fp16[j] - DEST.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp 16[j] * SRC3.fp16[j] + DEST.fp16[j])
DEST[MAXVL-1:VL] := 0 VFMADDSUB231PH DEST, SRC2, SRC3 (E VEX encoded versions) when src3  operand is a memory source
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * t3 - DEST.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * t3 + DEST.fp16[j])
DEST[MAXVL-1:VL] := 0 VFMADDSUB132PH/VFMADDSUB213PH/ VFMADDSUB231PH—Fused Multiply-Alternating  Add/Subtract of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-236 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VFMADDSUB132PH, VFMADDSUB213PH, and VFMADDSUB231PH:
__m128h _mm_fmaddsub_ph (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fmaddsub_ph (__m128h a, __mmask8 k, __m128h b, __m128h c);__m128h _mm_mask3_fmaddsub_ph (__m128h a, __m128h b, __m128h c, __mmask8 k);
__m128h _mm_maskz_fmaddsub_ph (__mmask8 k, __m128h a, __m128h b, __m128h c);__m256h _mm256_fmaddsub_ph (__m256h a, __m256h b, __m256h c);__m256h _mm256_mask_fmaddsub_ph (__m256h a, __mmask16 k, __m256h b, __m256h c);__m256h _mm256_mask3_fmaddsub_ph (__m256h a, __m256h b, __m256h c, __mmask16 k);
__m256h _mm256_maskz_fmaddsub_ph (__mmask16  k, __m256h a, __m256h b, __m256h c);
__m512h _mm512_fmaddsub_ph (__m512h a, __m512h b, __m512h c);__m512h _mm512_mask_fmaddsub_ph (__m512h a, __mmask32 k, __m512h b, __m512h c);__m512h _mm512_mask3_fmaddsub_ph (__m512h a, __m512h b, __m512h c, __mmask32 k);
__m512h _mm512_maskz_fmaddsub_ph (__mmask32  k, __m512h a, __m512h b, __m512h c);
__m512h _mm512_fmaddsub_round_ph (__m512h a,  __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask_fmaddsub_round_ph (__m512h a, __mma sk32 k, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask3_fmaddsub_round_ph (__m512h a, __ m512h b, __m512h c, __mmask32 k, const int rounding); 
__m512h _mm512_maskz_fmaddsub_round_ph (__mmask32 k, __m 512h a, __m512h b, __m512h c, const int rounding);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS— Fused Multiply-Alternating Add/Subtract of Packed Single Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-237VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSU B231PS—Fused Multiply-Alternating 
Add/Subtract of Packed Single Precision Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W0 96 /r 
VFMADDSUB132PS xmm1, xmm2, 
xmm3/m128A V/V FMA Multiply packed single precision floating-point values from 
xmm1 and xmm3/mem, add/subtract elements in xmm2 
VEX.128.66.0F38.W0 A6 /r 
VFMADDSUB213PS xmm1, xmm2, 
xmm3/m128 A V/V FMA Multiply packed single precision floating-point values from 
xmm1 and xmm2, add/subtract elements in xmm3/mem 
VEX.128.66.0F38.W0 B6 /r 
VFMADDSUB231PS xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed single precision floating-point values from 
xmm2 and xmm3/mem, add/subtract elements in xmm1 and put result in xmm1.
VEX.256.66.0F38.W0 96 /r 
VFMADDSUB132PS ymm1, ymm2, 
ymm3/m256A V/V FMA Multiply packed single precision floating-point values from 
ymm1 and ymm3/mem, add/subtract elements in ymm2 
VEX.256.66.0F38.W0 A6 /r 
VFMADDSUB213PS ymm1, ymm2, 
ymm1 and ymm2, add/subtract elements in ymm3/mem 
VEX.256.66.0F38.W0 B6 /r 
VFMADDSUB231PS ymm1, ymm2, 
ymm2 and ymm3/mem, add/subtract elements in ymm1 
EVEX.128.66.0F38.W0 A6 /r 
VFMADDSUB213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstBV / V A V X 5 1 2 V L
xmm1 and xmm2, add/subtract elements in xmm3/m128/m32bcst and put result in xmm1 subject to 
EVEX.128.66.0F38.W0 B6 /r 
VFMADDSUB231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstBV / V A V X 5 1 2 V L
xmm2 and xmm3/m128/m32bcst, add/subtract elements in xmm1 and put result in xmm1 subject to writemask k1.
EVEX.128.66.0F38.W0 96 /r
VFMADDSUB132PS xmm1 {k1}{z}, 
xmm2, xmm3/m128/m32bcstBV / V A V X 5 1 2 V L
xmm1 and xmm3/m128/m32bcst, add/subtract elements 
in zmm2 and put result in xm m1 subject to writemask k1.
EVEX.256.66.0F38.W0 A6 /r 
VFMADDSUB213PS ymm1 {k1}{z}, 
ymm2, ymm3/m256/m32bcstBV / V A V X 5 1 2 V L
ymm1 and ymm2, add/subtract elements in 
ymm3/m256/m32bcst and put result in ymm1 subject to 
EVEX.256.66.0F38.W0 B6 /r
VFMADDSUB231PS ymm1 {k1}{z}, 
ymm2 and ymm3/m256/m32bcst, add/subtract elements 
in ymm1 and put result in ymm1 subject to writemask k1.
EVEX.256.66.0F38.W0 96 /r 
VFMADDSUB132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstBV / V A V X 5 1 2 V L
ymm1 and ymm3/m256/m32bcst, add/subtract elements in ymm2 and put result in ymm1 subject to writemask k1.
EVEX.512.66.0F38.W0 A6 /r 
VFMADDSUB213PS zmm1 {k1}{z}, 
zmm2, zmm3/m512/m32bcst{er}B V/V AVX512F Multiply packed single precision floating-point values from 
zmm1 and zmm2, add/subtract elements in 
zmm3/m512/m32bcst and put re sult in zmm1 subject to 
EVEX.512.66.0F38.W0 B6 /r 
VFMADDSUB231PS zmm1 {k1}{z}, 
zmm2 and zmm3/m512/m32bcst, add/subtract elements 
in zmm1 and put result in zm m1 subject to writemask k1.
EVEX.512.66.0F38.W0 96 /r 
VFMADDSUB132PS zmm1 {k1}{z},

VFMADDSUB132PS zmm1 {k1}{z}, 
zmm1 and zmm3/m512/m32bcst, add/subtract elements 
in zmm2 and put result in zm m1 subject to writemask k1.VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alt ernating Add/Subtract of Packed Single PrecisionINSTRUCTION SET REFERENCE, V
5-238 Vol. 2CInstruction Operand Encoding
VFMADDSUB132PS: Multiplies the four, eight or sixteen packed  single precision floating-point values from the first 
source operand to the corresponding packed single precis ion floating-point values in the third source operand. 
From the infinite precision intermediate result, adds the odd single precision floating-point elements and subtracts 
the even single precision floating-point values in the second source operand, performs rounding and stores the 
resulting packed single precision floating-point values  to the destination operand (first source operand).
VFMADDSUB213PS: Multiplies the four, eight or sixteen pack ed single precision floating-point values from the 
second source operand to the corresponding packed single  precision floating-point values in the first source 
operand. From the infinite precision intermediate result, adds the odd single precision floating-point elements and 
subtracts the even single precision floating-point values in the third source operand, performs rounding and stores 
the resulting packed single precision floating-point valu es to the destination operand (first source operand).
VFMADDSUB231PS: Multiplies the four, eight or sixteen pack ed single precision floating-point values from the 
second source operand to the corresponding packed single  precision floating-point values in the third source 
subtracts the even single precision floating-point values in the first source operand, performs rounding and stores 
tion or a 512/256/128-bit vector broadcasted from a 32-bit  memory location. The destination operand is condition-
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in 
column.
Operation
VFMADDSUB132PS DEST, SRC2, SRC3 
MAXNUM :=2
MAXNUM := 4
FIFor i = 0 to MAXNUM -1{
n := 64*i;DEST[n+31:n] := RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])DEST[n+63:n+32] := RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] + SRC2[n+63:n+32])
}IF (VEX.128) THENOp/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS— Fused Multiply-Alternating Add/Subtract of Packed Single Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-239DEST[MAXVL-1:128] := 0
FI
VFMADDSUB213PS DEST, SRC2, SRC3 
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+31:n] := RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])DEST[n+63:n+32] := RoundFPControl_MXCSR(SRC2[n +63:n+32]*DEST[n+63:n+ 32] + SRC3[n+63:n+32])
FI
VFMADDSUB231PS DEST, SRC2, SRC3 
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+31:n] := RoundFPControl_MXCSR(SRC 2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])
DEST[n+63:n+32] :=RoundFPControl_MXCSR(SRC2[n +63:n+32]*SRC3[n+63:n+ 32] + DEST[n+63:n+32])
FI
VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
THEN 
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alt ernating Add/Subtract of Packed Single PrecisionINSTRUCTION SET REFERENCE, V
5-240 Vol. 2CELSE DEST[i+31:i] := 
FI
ELSE 
FI
FI;
VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN 
THEN
RoundFPControl_MXCSR(DEST[i+31: i]*SRC3[31:0] - SRC2[i+31:i])
ELSE 
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])FI;
ELSE 
THEN
ELSE 
FI
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS— Fused Multiply-Alternating Add/Subtract of Packed Single Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-241VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
THEN 
RoundFPControl(SRC2[i+31:i]*DE ST[i+31:i] - SRC3[i+31:i])
ELSE DEST[i+31:i] := 
FI
ELSE 
FI
FI;
VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])
ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])FI;
ELSE 
THEN
RoundFPControl_MXCSR(SRC2[i+31:i ]*DEST[i+31:i] + SRC3[31:0])
ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i ]*DEST[i+31:i] + SRC3[i+31:i])
FI;VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alt ernating Add/Subtract of Packed Single PrecisionINSTRUCTION SET REFERENCE, V
5-242 Vol. 2CFI
ELSE 
FI
FI;
VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
THEN 
RoundFPControl(SRC2[i+31:i]*S RC3[i+31:i] - DEST[i+31:i])
FI
ELSE 

ELSE 
ELSE 
FI
FI;
THEN
ELSE 
THEN 
FI
ELSE 
FI
FI;
VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])
ELSE 
DEST[i+31:i] := VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS— Fused Multiply-Alternating Add/Subtract of Packed Single Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-243RoundFPControl_MXCSR(SRC2[i+31:i ]*SRC3[i+31:i] - DEST[i+31:i])
FI;
ELSE 
THEN
ELSE 
FI;
FI
ELSE 
FI
FI;
VFMADDSUBxxxPS __m512 _mm512_fmaddsub_ps(__m512 a, __m512 b, __m512 c);
VFMADDSUBxxxPS __m512 _mm512_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, int r);VFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);VFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);VFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_ps( __m512 a, __m512 b, __m512 c, __mmask16 k);
VFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);VFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);VFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_round_ps(__m5 12 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMADDSUBxxxPS __m256 _mm256_mask_fmaddsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);VFMADDSUBxxxPS __m256 _mm256_maskz_fmaddsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);VFMADDSUBxxxPS __m256 _mm256_mask3_fmaddsub_ps( __m256 a, __m256 b, __m256 c, __mmask8 k);
VFMADDSUBxxxPS __m128 _mm_mask_fmaddsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);VFMADDSUBxxxPS __m128 _mm_maskz_fmaddsub_ps(__m mask8 k, __m128 a, __m128 b, __m128 c);
VFMADDSUBxxxPS __m128 _mm_mask3_fmaddsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);VFMADDSUBxxxPS __m128 _mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c);VFMADDSUBxxxPS __m256 _mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-244 Vol. 2CVFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double 
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W1 9A /r 
VFMSUB132PD xmm1, xmm2, 
from xmm1 and xmm3/mem, subtract xmm2 and put 
VEX.128.66.0F38.W1 AA /r 
VFMSUB213PD xmm1, xmm2, 
from xmm1 and xmm2, subtract xmm3/mem and put 
VEX.128.66.0F38.W1 BA /r 
VFMSUB231PD xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed double precision floating-point values 
from xmm2 and xmm3/mem, subtract xmm1 and put result in xmm1.
VEX.256.66.0F38.W1 9A /r 
VFMSUB132PD ymm1, ymm2, 
from ymm1 and ymm3/mem, subtract ymm2 and put 
VEX.256.66.0F38.W1 AA /r 
VFMSUB213PD ymm1, ymm2, 
from ymm1 and ymm2, subtract ymm3/mem and put 
VEX.256.66.0F38.W1 BA /r 
VFMSUB231PD ymm1, ymm2, 
from ymm2 and ymm3/mem, subtract ymm1 and put 
result in ymm1.S
EVEX.128.66.0F38.W1 9A /r 
VFMSUB132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstB V/V AVX512VL
AVX512FMultiply packed double prec ision floating-point values 
from xmm1 and xmm3/m128/m64bcst, subtract xmm2 and put result in xmm1 subject to writemask k1.
EVEX.128.66.0F38.W1 AA /r 
VFMSUB213PD xmm1 {k1}{z}, 
xmm2, xmm3/m128/m64bcstB V/V AVX512VL
from xmm1 and xmm2, subtract   xmm3/m128/m64bcst 
and put result in xmm1 subject to writemask k1.
EVEX.128.66.0F38.W1 BA /r
VFMSUB231PD xmm1 {k1}{z}, 
from xmm2 and xmm3/m128/m64bcst, subtract   xmm1 
EVEX.256.66.0F38.W1 9A /r 
VFMSUB132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstB V/V AVX512VL
from ymm1 and ymm3/m256/m64bcst, subtract ymm2 and put result in ymm1 subject to writemask k1.
EVEX.256.66.0F38.W1 AA /r 
VFMSUB213PD ymm1 {k1}{z}, 
ymm2, ymm3/m256/m64bcstB V/V AVX512VL
from ymm1 and ymm2, subtract ymm3/m256/m64bcst 
and put result in ymm1 subject to writemask k1.
EVEX.256.66.0F38.W1 BA /r
VFMSUB231PD ymm1 {k1}{z}, 
from ymm2 and ymm3/m256/m64bcst, subtract ymm1 
EVEX.512.66.0F38.W1 9A /r
VFMSUB132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}B V/V AVX512F Multiply packed double precision floating-point values 
from zmm1 and zmm3/m512/m64bcst, subtract zmm2 
and put result in zmm1 subject to writemask k1.
EVEX.512.66.0F38.W1 AA /r
VFMSUB213PD zmm1 {k1}{z}, 
from zmm1 and zmm2, subtract zmm3/m512/m64bcst 
EVEX.512.66.0F38.W1 BA /r 
VFMSUB231PD zmm1 {k1}{z}, 
from zmm2 and zmm3/m512/m64bcst, subtract zmm1 
and put result in zmm1 subject to writemask k1.VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-245Instruction Operand Encoding
Performs a set of SIMD multiply-subtract computation on pa cked double precision floating-point values using three 
source operands and writes the multiply-subtract results in the destination operand. The destination operand is 
also the first source operand. The second operand must be a SIMD register. The third source operand can be a 
SIMD register or a memory location. 
VFMSUB132PD: Multiplies the two, four or eight packed double  precision floating-point values from the first source 
operand to the two, four or eight packed double precision floating-point values in the third source operand. From 
the infinite precision intermediate result, subtracts the tw o, four or eight packed double precision floating-point 
values in the second source operand, performs rounding an d stores the resulting two, four or eight packed double 
VFMSUB213PD: Multiplies the two, four or eight packed do uble precision floating-point values from the second 
source operand to the two, four or eight packed double pr ecision floating-point values in the first source operand. 
From the infinite precision intermediate result, subtracts the two, four or eight packed double precision floating-
point values in the third source operand, performs round ing and stores the resulting two, four or eight packed 
double precision floating-point values to th e destination operand (first source operand).
VFMSUB231PD: Multiplies the two, four or eight packed do uble precision floating-point values from the second 
source to the two, four or eight packed double precision fl oating-point values in the third source operand. From the 
infinite precision intermediate result, subtracts the two, fo ur or eight packed double precision floating-point values 
in the first source operand, performs rounding and stores the resulting two, four or eight packed double precision 
tion or a 512/256/128-bit vector broadcasted from a 64-b it memory location. The dest ination operand is condition-

Operation
VFMSUB132PD DEST, SRC2, SRC3 (VEX encoded versions)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(DES T[n+63:n]*SRC3[n+63:n] - SRC2[n+63:n])
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-246 Vol. 2CELSEIF (VEX.256)
FI
VFMSUB213PD DEST, SRC2, SRC3 (VEX encoded versions)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] - SRC3[n+63:n])
FI
VFMSUB231PD DEST, SRC2, SRC3 (VEX encoded versions)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] - DEST[n+63:n])
FI
VFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded ve rsions, when src3 op erand is a register)
THEN
ELSE 
SET_ROUNDING_MODE_FOR_THIS _INSTRUCTION(MXCSR.RC);
ELSE 
DEST[i+63:i] := 0VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-247FI
FI;
VFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded vers ions, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])
ELSE 
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])FI;ELSE IF *merging-masking* ; merging-masking
FI
FI;
VFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded ve rsions, when src3 op erand is a register)
THEN
ELSE 
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-248 Vol. 2CVFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded vers ions, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+63: i]*DEST[i+63:i] - SRC3[63:0])
+31:i])
ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i] *DEST[i+63:i] - SRC3[i+63:i])
FI;
ELSE 
FI
FI;
VFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded ve rsions, when src3 op erand is a register)
THEN
ELSE 
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-249VFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded vers ions, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])
ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i ]*SRC3[i+63:i] - DEST[i+63:i])
FI;
ELSE 
FI
FI;
VFMSUBxxxPD __m512d _mm512_fmsub_pd(__m512d a, __m512d b, __m512d c);
VFMSUBxxxPD __m512d _mm512_fmsub_round_pd( __m512d a, __m512d b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_mask_fmsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);VFMSUBxxxPD __m512d _mm512_maskz_fmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);VFMSUBxxxPD __m512d _mm512_mask3_fmsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);VFMSUBxxxPD __m512d _mm512_mask_fmsub_round_pd(__m51 2d a, __mmask8 k, __m512d  b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_maskz_fmsub_round_pd(__mma sk8 k, __m512d a, __m512d b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_mask3_fmsub_round_pd(__m5 12d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMSUBxxxPD __m256d _mm256_mask_fmsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);VFMSUBxxxPD __m256d _mm256_maskz_fmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);VFMSUBxxxPD __m256d _mm256_mask3_fmsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);VFMSUBxxxPD __m128d _mm_mask_fmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);VFMSUBxxxPD __m128d _mm_maskz_fmsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);VFMSUBxxxPD __m128d _mm_mask3_fmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);VFMSUBxxxPD __m128d _mm_fmsub_pd (__m128d a, __m128d b, __m128d c);VFMSUBxxxPD __m256d _mm256_fmsub_pd (__m256d a, __m256d b, __m256d c);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VF[,N]MSUB[132,213,231]PH—Fused Multiply-Subtract of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-250 Vol. 2CVF[,N]MSUB[132,213,231] PH—Fused Multiply-Subtract of Packed FP16 Values
Opcode/
En64/32 
Bit Mode 
EVEX.128.66.MAP6.W0  9A /r
VFMSUB132PH xmm1 {k1}{z}, xmm2, 
xmm3/m128/m16bcst, subtract xmm2, and store 
EVEX.256.66.MAP6.W0  9A /r
VFMSUB132PH ymm1{k1}{z}, ymm2, 
ymm3/m256/m16bcst, subtract ymm2, and store the result in ymm1 su bject to writemask k1.
EVEX.512.66.MAP6.W0  9A /r
VFMSUB132PH  zmm1{k1}{z},  zmm2,  
zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed  FP16 values from zmm1 and 
zmm3/m512/m16bcst, subtract zmm2, and store 
EVEX.128.66.MAP6.W0  AA /r
VFMSUB213PH xmm1 {k1}{z}, xmm2, 
xmm2, subtract xmm3/m128/m16bcst, and store 
EVEX.256.66.MAP6.W0  AA /r
VFMSUB213PH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstA V/V AVX512-FP16 
ymm2, subtract ymm3/m256/m16bcst, and store 
EVEX.512.66.MAP6.W0  AA /r

VFMSUB213PH  zmm1{k1}{z},  zmm2,  
zmm2, subtract zmm3/m512/m16bcst, and store the result in zmm1 subject to writemask k1.
EVEX.128.66.MAP6.W0  BA /r
VFMSUB231PH xmm1 {k1}{z}, xmm2, 
xmm3/m128/m16bcst, subtract xmm1, and store 
EVEX.256.66.MAP6.W0  BA /r
VFMSUB231PH ymm1{k1}{z}, ymm2, 
ymm3/m256/m16bcst, subtract ymm1, and store 
EVEX.512.66.MAP6.W0  BA /r
VFMSUB231PH  zmm1{k1}{z},  zmm2,  
zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed  FP16 values from zmm2 and 
zmm3/m512/m16bcst, subtract zmm1, and store the result in zmm1 subject to writemask k1.
EVEX.128.66.MAP6.W0  9E /r
VFNMSUB132PH  xmm1{k1}{z},  
Subtract xmm2 from this  value, and store the 
EVEX.256.66.MAP6.W0  9E /r
VFNMSUB132PH  ymm1{k1}{z},  
Subtract ymm2 from this  value, and store the 
EVEX.512.66.MAP6.W0  9E /r
VFNMSUB132PH  zmm1{k1}{z},  
Subtract zmm2 from this  value, and store the 
EVEX.128.66.MAP6.W0  AE /r
VFNMSUB213PH  xmm1{k1}{z},  
xmm2, and negate the value. Subtract xmm3/
m128/m16bcst from this value, and store the result in xmm1 subject to writemask k1.
EVEX.256.66.MAP6.W0  AE /r
VFNMSUB213PH  ymm1{k1}{z},  
ymm2, and negate the value. Subtract ymm3/
m256/m16bcst from this value, and store the result in ymm1 subject to writemask k1.VF[,N]MSUB[132,213,231]PH—Fused Multip ly-Subtract of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-251Instruction Operand Encoding
This instruction performs a packed multiply-subtract or  a negated multiply-subtract computation on FP16 values 
using three source operands and writes the results in the destination operand. The destination operand is also the 
first source operand. The “N” (negated) forms of this in struction subtract the remaining operand from the negated 
infinite precision intermediate product. The notation’ “132” , “213” and “231” indicate the use of the operands in ±A 
* B − C, where each digit corresponds to the operand number,  with the destination being operand 1; see Table 5-6.
The destination elements are updated according to the writemask.EVEX.512.66.MAP6.W0  AE /r
VFNMSUB213PH  zmm1{k1}{z},  
zmm2, and negate the va lue. Subtract zmm3/
m512/m16bcst from this value, and store the 
EVEX.128.66.MAP6.W0  BE /r
VFNMSUB231PH  xmm1{k1}{z},  
Subtract xmm1 from this  value, and store the 
EVEX.256.66.MAP6.W0  BE /r
VFNMSUB231PH  ymm1{k1}{z},  
Subtract ymm1 from this  value, and store the 
EVEX.512.66.MAP6.W0  BE /r
VFNMSUB231PH  zmm1{k1}{z},  
zmm2,  zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed FP16 values from zmm2 and 
zmm3/m512/m16bcst, an d negate the value. 
Subtract zmm1 from this  value, and store the 
Table 5-6.  VF[,N]MSUB[132,213,231]PH Notation for Operands
132 dest =  ± dest*src3-src2
231 dest =  ± src2*src3-dest
213 dest = ± src2*dest-src3Opcode/
En64/32 
Bit Mode 
FlagDescriptionVF[,N]MSUB[132,213,231]PH—Fused Multiply-Subtract of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-252 Vol. 2COperation
VF[,N]MSUB132PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register 
ELSE
DEST.fp16[j] := RoundFPControl(-DEST .fp16[j]*SRC3.fp16[j] - SRC2.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(DEST. fp16[j]*SRC3.fp16[j] - SRC2.fp16[j])
DEST[MAXVL-1:VL] := 0 VF[,N]MSUB132PH DEST, SRC2, SRC3 (EVEX encoded ve rsions) when src3 operand is a memory source
ELSE:
DEST.fp16[j] := RoundFPControl(-DEST.fp16[j] * t3 - SRC2.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(DEST.fp16[j] * t3 - SRC2.fp16[j])
DEST[MAXVL-1:VL] := 0VF[,N]MSUB[132,213,231]PH—Fused Multip ly-Subtract of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-253VF[,N]MSUB213PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register 
ELSE
DEST.fp16[j] := RoundFPControl(-SRC2 .fp16[j]*DEST.fp16[j] - SRC3.fp16[j])
ELSE
DEST[MAXVL-1:VL] := 0 VF[,N]MSUB213PH DEST, SRC2, SRC3 (EVEX encoded vers ions) when src3 operand is a memory source 
ELSE:
DEST.fp16[j] := RoundFPControl(-SRC2.fp16[j] * DEST.fp16[j] - t3 )
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * DEST.fp16[j] - t3 )
DEST[MAXVL-1:VL] := 0VF[,N]MSUB[132,213,231]PH—Fused Multiply-Subtract of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-254 Vol. 2CVF[,N]MSUB231PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register 
ELSE
DEST.fp16[j] := RoundFPControl(-SRC2.fp16[j]*SRC3.fp16[j] - DEST.fp16[j])
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2. fp16[j]*SRC3.fp16[j] - DEST.fp16[j])
DEST[MAXVL-1:VL] := 0VF[,N]MSUB231PH DEST, SRC2, SRC3 (EVEX encoded ve rsions) when src3 operand is a memory source
ELSE:
DEST.fp16[j] := RoundFPControl(-SR C2.fp16[j] * t3 - DEST.fp16[j] )
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j] * t3 - DEST.fp16[j] )
Vol. 2C 5-255Intel C/C++ Compiler Intrinsic Equivalent
VFMSUB132PH, VFMSUB213PH, and VFMSUB231PH:
__m128h _mm_fmsub_ph (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fmsub_ph (__m128h a, __mmask8 k, __m128h b, __m128h c);__m128h _mm_mask3_fmsub_ph (__m128h a, __m128h b, __m128h c, __mmask8 k);__m128h _mm_maskz_fmsub_ph (__mmask8 k, __m128h a, __m128h b, __m128h c);
__m256h _mm256_fmsub_ph (__m256h a, __m256h b, __m256h c);__m256h _mm256_mask_fmsub_ph (__m256h a, __mmask16 k, __m2 56h b, __m256h c);
__m256h _mm256_mask3_fmsub_ph (__m256h a, __m256h b, __m256h c, __mmask16 k);__m256h _mm256_maskz_fmsub_ph (__mmask16 k, __m256h a, __m256h b, __m256h c);__m512h _mm512_fmsub_ph (__m512h a, __m512h b, __m512h c);__m512h _mm512_mask_fmsub_ph (__m512h a, __mmask32 k, __m5 12h b, __m512h c);

__m512h _mm512_mask3_fmsub_ph (__m512h a, __m512h b, __m512h c, __mmask32 k);__m512h _mm512_maskz_fmsub_ph (__mmask32 k, __m512h a, __m512h b, __m512h c);__m512h _mm512_fmsub_round_ph (__m512h a, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask_fmsub_round_ph (__m512h a, __mmask32 k, __m512h b, __m512h c, const int rounding);__m512h _mm512_mask3_fmsub_round_ph (__m512h a, __m 512h b, __m512h c, __mmask32 k, const int rounding);
__m512h _mm512_maskz_fmsub_round_ph (__mmask32 k, __ m512h a, __m512h b, __m512h c, const int rounding);
VFNMSUB132PH, VFNMSUB213PH, and VFNMSUB231PH:
__m128h _mm_fnmsub_ph (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fnmsub_ph (__m128h a,  __mmask8 k, __m128h b, __m128h c);
__m128h _mm_mask3_fnmsub_ph (__m128h a,  __m128h b, __m128h c, __mmask8 k);
__m128h _mm_maskz_fnmsub_ph (__mmask8 k, __m128h a, __m128h b, __m128h c);
__m256h _mm256_fnmsub_ph (__m256h a, __m256h b, __m256h c);__m256h _mm256_mask_fnmsub_ph (__m256h a, __mmask16 k, __m256h b, __m256h c);__m256h _mm256_mask3_fnmsub_ph (__m256h  a, __m256h b, __m256h c, __mmask16 k);
__m256h _mm256_maskz_fnmsub_ph (__mmask16 k, __m256h a, __m256h b, __m256h c);__m512h _mm512_fnmsub_ph (__m512h a, __m512h b, __m512h c);__m512h _mm512_mask_fnmsub_ph (__m512h a, __mmask32 k, __m512h b, __m512h c);__m512h _mm512_mask3_fnmsub_ph (__m512h  a, __m512h b, __m512h c, __mmask32 k);
__m512h _mm512_maskz_fnmsub_ph (__mmask32 k, __m512h a, __m512h b, __m512h c);__m512h _mm512_fnmsub_round_ph (__m512h a,  __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask_fnmsub_round_ph (__m512h a, __m mask32 k, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask3_fnmsub_round_ph (__m512h a, __m5 12h b, __m512h c, __mmask32 k, const int rounding);
__m512h _mm512_maskz_fnmsub_round_ph (__mmask32 k, __m 512h a, __m512h b, __m512h c, const int rounding);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-256 Vol. 2CVFMSUB132PS/VFMSUB213PS/VFMS UB231PS—Fused Multiply-S ubtract of Packed Single 
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W0 9A /r 
VFMSUB132PS xmm1, xmm2, 
VEX.128.66.0F38.W0 AA /r 
VFMSUB213PS xmm1, xmm2, 
VEX.128.66.0F38.W0 BA /r 
VFMSUB231PS xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed single precision floating-point values 
VEX.256.66.0F38.W0 9A /r 
VFMSUB132PS ymm1, ymm2, 
VEX.256.66.0F38.W0 AA /r 
VFMSUB213PS ymm1, ymm2, 
VEX.256.66.0F38.0 BA /r 
VFMSUB231PS ymm1, ymm2, 
EVEX.128.66.0F38.W0 9A /r 
VFMSUB132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstB V/V AVX512VL
from xmm1 and xmm3/m128/m32bcst, subtract   xmm2 and put result in xmm1.
EVEX.128.66.0F38.W0 AA /r 
VFMSUB213PS xmm1 {k1}{z}, 
xmm2, xmm3/m128/m32bcstB V/V AVX512VL
from xmm1 and xmm2, subtract   
EVEX.128.66.0F38.W0 BA /r
VFMSUB231PS xmm1 {k1}{z}, 
from xmm2 and xmm3/m128/m32bcst, subtract   
EVEX.256.66.0F38.W0 9A /r
VFMSUB132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512VL
from ymm1 and ymm3/m256/m32bcst, subtract   ymm2 and put result in ymm1.
EVEX.256.66.0F38.W0 AA /r 
VFMSUB213PS ymm1 {k1}{z}, 
ymm2, ymm3/m256/m32bcstB V/V AVX512VL
from ymm1 and ymm2, subtract   
EVEX.256.66.0F38.W0 BA /r
VFMSUB231PS ymm1 {k1}{z}, 
from ymm2 and ymm3/m256/m32bcst, subtract   
EVEX.512.66.0F38.W0 9A /r 
VFMSUB132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}B V/V AVX512F Multiply pack ed single precision floating-point values 
from zmm1 and zmm3/m512/ m32bcst, subtract zmm2 
and put result in zmm1.
EVEX.512.66.0F38.W0 AA /r 
VFMSUB213PS zmm1 {k1}{z}, 
zmm2, zmm3/m512/m32bcst{er}B V/V AVX512F Multiply pack ed single precision floating-point values 
from zmm1 and zmm2, subtract zmm3/m512/m32bcst 
EVEX.512.66.0F38.W0 BA /r 
VFMSUB231PS zmm1 {k1}{z}, 
from zmm2 and zmm3/m512/ m32bcst, subtract zmm1 
and put result in zmm1.VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-257Instruction Operand Encoding
Performs a set of SIMD multiply-subtract computation on pa cked single precision floating-point values using three 
VFMSUB132PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the first 
source operand to the four, eight or sixteen packed single precision floating-point values in the third source operand. From the infinite precision intermediate result, su btracts the four, eight or sixteen packed single precision 
floating-point values in the second source operand, pe rforms rounding and stores the resulting four, eight or 
sixteen packed single precision floating-point values to the destination operand (first source operand).
VFMSUB213PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the second 
operand. From the infinite precision intermediate result, su btracts the four, eight or sixteen packed single precision 
floating-point values in the third source operand, perfor ms rounding and stores the resulting four, eight or sixteen 
VFMSUB231PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the second 
source to the four, eight or sixteen packed single precisio n floating-point values in the third source operand. From 
the infinite precision intermediate result, subtracts the four, eight or sixteen packed single precision floating-point 
values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed single 
tion or a 512/256/128-bit vector broadcasted from a 32-b it memory location. The dest ination operand is condition-
Operation

Operation
VFMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(DES T[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])
B Full ModRM:reg (r, w) EVEX .vvvv (r) ModRM:r/m (r) N/AVFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-258 Vol. 2CELSEIF (VEX.256)
FI
VFMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])
FI
VFMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])
FI
VFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
ELSE 
DEST[i+31:i] := 0VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-259FI
FI;
VFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])
ELSE 
ELSE 
FI
FI;
VFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
THEN
ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-260 Vol. 2CVFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+31: i]*DEST[i+31:i] - SRC3[31:0])
ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i] *DEST[i+31:i] - SRC3[i+31:i])
FI;
ELSE 
FI
FI;
VFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
THEN
ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i] *SRC3[i+31:i] - DEST[i+31:i])
ELSE 
FI
FI;
VFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
i := j * 32IF k1[j] OR *no writemask*VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-261THEN 
THEN
ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i ]*SRC3[i+31:i] - DEST[i+31:i])
FI;
ELSE 
FI
FI;
VFMSUBxxxPS __m512 _mm512_fmsub_ps(__m512 a, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_fmsub_round_ps( __m512 a, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_mask_fmsub_ps(__m5 12 a, __mmask16 k, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_maskz_fmsub_ps(__ mmask16 k, __m512 a, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_mask3_fmsub_ps(__m 512 a, __m512 b, __m512 c, __mmask16 k);
VFMSUBxxxPS __m512 _mm512_mask_fmsub_round_ps(__m 512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_maskz_fmsub_round_ps(__mmask 16 k, __m512 a, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_mask3_fmsub_round_ps(__m5 12 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMSUBxxxPS __m256 _mm256_mask_fmsub_ps(__m 256 a, __mmask8 k, __m256 b, __m256 c);
VFMSUBxxxPS __m256 _mm256_maskz_fmsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);VFMSUBxxxPS __m256 _mm256_mask3_fmsub_ps(__m 256 a, __m256 b, __m256 c, __mmask8 k);
VFMSUBxxxPS __m128 _mm_mask_fmsub_ps(__m1 28 a, __mmask8 k, __m128 b, __m128 c);
VFMSUBxxxPS __m128 _mm_maskz_fm sub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBxxxPS __m128 _mm_mask3_ fmsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMSUBxxxPS __m128 _mm_fmsub_ps (__m128 a, __m128 b, __m128 c);VFMSUBxxxPS __m256 _mm256_fmsub_ps (__m256 a, __m256 b, __m256 c);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtrac t of Scalar Double Precis ion Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-262 Vol. 2CVFMSUB132SD/VFMSUB213SD/VFMS UB231SD—Fused Multiply-Subtract of Scalar Double 
Performs a SIMD multiply-subtract computation on the lo w packed double precision floating-point values using 
three source operands and writes the multiply-subtract re sult in the destination operand. The destination operand 
is also the first source operand. The second operand mu st be a XMM register. The third source operand can be a 
XMM register or a 64-bit memory location. 
VFMSUB132SD: Multiplies the low packed double precision floa ting-point value from the first source operand to the 
low packed double precision floating-point value in the th ird source operand. From the infinite precision interme-
diate result, subtracts the low packed double precision floating-point values in the second source operand, 
performs rounding and stores the resulting packed double precision floating-point value to the destination operand 
(first source operand).
VFMSUB213SD: Multiplies the low packed double precision fl oating-point value from the second source operand to 
the low packed double precision floating-point value in th e first source operand. From the infinite precision inter-
mediate result, subtracts the low packed double precisio n floating-point value in the third source operand, 
VFMSUB231SD: Multiplies the low packed double precision floating-point value from the second source to the low 
packed double precision floating-point value in the third source operand. From the infinite precision intermediate 
result, subtracts the low packed double precision floati ng-point value in the first source operand, performs 
rounding and stores the resulting packed double precisio n floating-point value to the destination operand (first 
source operand).Opcode/
En64/32 
Bit Mode 
Feature 
VEX.LIG.66.0F38.W1 9B /r 
VFMSUB132SD xmm1, xmm2, 
xmm3/m64A V/V FMA Multiply scalar double precision floating-point value from 
xmm1 and xmm3/m64, subtract xmm2 and put result in

En64/32 
Bit Mode 
Feature 
xmm1 and xmm3/m64, subtract xmm2 and put result in 
xmm1.
VEX.LIG.66.0F38.W1 AB /r 
VFMSUB213SD xmm1, xmm2, 
xmm1 and xmm2, subtract xmm3/m64 and put result in 
xmm1.
VEX.LIG.66.0F38.W1 BB /r 
VFMSUB231SD xmm1, xmm2, xmm3/m64A V/V FMA Multiply scalar double precision floating-point value from 
xmm2 and xmm3/m64, subtract xmm1 and put result in xmm1.
EVEX.LLIG.66.0F38.W1 9B /r
VFMSUB132SD xmm1 {k1}{z}, 
xmm2, xmm3/m64{er}B V/V AVX512F Multiply scalar double precision floating-point value from 
xmm1.
EVEX.LLIG.66.0F38.W1 AB /r
VFMSUB213SD xmm1 {k1}{z}, 
xmm1.
EVEX.LLIG.66.0F38.W1 BB /r 
VFMSUB231SD xmm1 {k1}{z}, 
xmm2 and xmm3/m64, subtract xmm1 and put result in 
xmm1.
B Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double  Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-263VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. 
EVEX encoded version: The low quadword element of th e destination is updated according to the writemask.
column.
Operation
VFMSUB132SD DEST, SRC2, SR C3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(DEST[63:0]*SRC3[63:0] - SRC2[63:0])ELSE 
FI;
VFMSUB213SD DEST, SRC2, SR C3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(S RC2[63:0]*DEST[63:0] - SRC3[63:0])
ELSE 
FI;
FI;DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtrac t of Scalar Double Precis ion Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-264 Vol. 2CVFMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(SRC2[63:0]*SRC3[63:0] - DEST[63:0])ELSE 
FI;
VFMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0
VFMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0
VFMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0
VFMSUBxxxSD __m128d _mm_fmsub_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_mask_fmsub_sd(__m128 d a, __mmask8 k, __m128d b, __m128d c);
VFMSUBxxxSD __m128d _mm_maskz_fmsub_sd(__mma sk8 k, __m128d a, __m128d b, __m128d c);
VFMSUBxxxSD __m128d _mm_mask3_fmsub_sd(__m12 8d a, __m128d b, __m128d c, __mmask8 k);
VFMSUBxxxSD __m128d _mm_mask_fmsub _round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_maskz_fmsub_round_sd(__mma sk8 k, __m128d a, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_mask3_fmsub_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);VFMSUBxxxSD __m128d _mm_fmsub_sd ( __m128d a, __m128d b, __m128d c);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VF[,N]MSUB[132,213,231]SH—Fused Multiply-Subtract of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-265VF[,N]MSUB[132,213,231]SH—Fused Mult iply-Subtract of Scalar FP16 Values
This instruction performs a scalar multiply-subtract or  negated multiply-subtract computation on the low FP16 
values using three source operands and writes the result in  the destination operand. The destination operand is also 
the first source operand. The “N” (negated) forms of th is instruction subtract the remaining operand from the 
negated infinite precision intermediate product. The nota tion’ “132”, “213” and “231” in dicate the use of the oper-
ands in ±A * B − C, where each digit corresponds to the operand number, with the destination being operand 1; 
see Table 5-7.
En64/32 
Bit Mode 
EVEX.LLIG.66.MAP6.W0  9B /r
VFMSUB132SH xmm1{k1}{z}, xmm2, 
m16, subtract xmm2, an d store the result in 
EVEX.LLIG.66.MAP6.W0  AB /r
VFMSUB213SH xmm1{k1}{z}, xmm2, 
xmm3/m16 {er}A V/V AVX512-FP16 Multiply FP16 values from xmm1 and xmm2, 
subtract xmm3/m16, and store the result in xmm1 subject to writemask k1.
EVEX.LLIG.66.MAP6.W0  BB /r
VFMSUB231SH xmm1{k1}{z}, xmm2, xmm3/m16 {er}A V/V AVX512-FP16 Multiply FP16 values from xmm2 and xmm3/
m16, subtract xmm1, an d store the result in 
EVEX.LLIG.66.MAP6.W0  9F /r
VFNMSUB132SH  xmm1{k1}{z},  
m16, and negate the valu e. Subtract xmm2 from 
this value, and store the result in xmm1 subject 
EVEX.LLIG.66.MAP6.W0  AF /r
VFNMSUB213SH  xmm1{k1}{z},  
negate the value. Subtra ct xmm3/m16 from this 
value, and store the result in xmm1 subject to writemask k1.
EVEX.LLIG.66.MAP6.W0  BF /r
VFNMSUB231SH  xmm1{k1}{z},  
m16, and negate the valu e. Subtract xmm1 from 
this value, and store the result in xmm1 subject to writemask k1.
Table 5-7.  VF[,N]MSUB[132,213 ,231]SH Notation for Operands
213 dest = ± src2*dest-src3VF[,N]MSUB[132,213,231]SH—Fused Multip ly-Subtract of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
5-266 Vol. 2COperation
VF[,N]MSUB132SH DEST, SRC2, SRC3 (EVEX encoded versions)
ELSE
DEST.fp16[0] := RoundFPControl(-DEST.fp16[0]*SRC3.fp16[0] - SRC2.fp16[0])
ELSE:
DEST.fp16[0] := RoundFPControl(DEST. fp16[0]*SRC3.fp16[0] - SRC2.fp16[0])
VF[,N]MSUB213SH DEST, SRC2, SRC3 (EVEX encoded versions) 
ELSE
DEST.fp16[0] := RoundFPControl(-SRC2 .fp16[0]*DEST.fp16[0] - SRC3.fp16[0])
ELSE:

ELSE
ELSE:
ELSE
ELSE:
DEST.fp16[0] := RoundFPControl(SRC2. fp16[0]*DEST.fp16[0] - SRC3.fp16[0])
VF[,N]MSUB231SH DEST, SRC2, SRC3 (EVEX encoded versions) 
ELSE
DEST.fp16[0] := RoundFPControl(-SRC2 .fp16[0]*SRC3.fp16[0] - DEST.fp16[0])
ELSE:
DEST.fp16[0] := RoundFPControl(SRC2. fp16[0]*SRC3.fp16[0] - DEST.fp16[0])
DEST[MAXVL-1:128] := 0 VF[,N]MSUB[132,213,231]SH—Fused Multiply-Subtract of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-267Intel C/C++ Compiler Intrinsic Equivalent
VFMSUB132SH, VFMSUB213SH, and VFMSUB231SH:
__m128h _mm_fmsub_round_sh (__m128h a, __ m128h b, __m128h c, const int rounding);
__m128h _mm_mask_fmsub_round_sh (__m128h a, __mmask8 k, __m128h b, __m128h c, const int rounding);__m128h _mm_mask3_fmsub_round_sh (__m128h a, __m1 28h b, __m128h c, __mmask8 k, const int rounding);
__m128h _mm_maskz_fmsub_round_sh (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);__m128h _mm_fmsub_sh (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fmsub_sh (__m128h a, __mmask8 k, __m128h b, __m128h c);__m128h _mm_mask3_fmsub_sh (__m128h a, __m128h b, __m128h c, __mmask8 k);__m128h _mm_maskz_fmsub_sh (__mmask8 k, __m128h a, __m128h b, __m128h c);
VFNMSUB132SH, VFNMSUB213SH, and VFNMSUB231SH:
__m128h _mm_fnmsub_round_sh (__m128h a, __m128h b, __m128h c, const int rounding);
__m128h _mm_mask_fnmsub_round_sh (__m128h a, __mmask8 k, __m128h b, __m128h c, const int rounding);__m128h _mm_mask3_fnmsub_round_sh (__m128h a, __m128h b, __m128h c, __mmask8 k, const int rounding);__m128h _mm_maskz_fnmsub_round_sh (__mmask8 k, __m12 8h a, __m128h b, __m128h c, const int rounding);
__m128h _mm_fnmsub_sh (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fnmsub_sh (__m128h a, __mmask8 k, __m128h b, __m128h c);__m128h _mm_mask3_fnmsub_sh (__m128h a, __m128h b, __m128h c, __mmask8 k);
__m128h _mm_maskz_fnmsub_sh (__mmask8 k, __m128h a, __m128h b, __m128h c);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-268 Vol. 2CVFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single 
Performs a SIMD multiply-subtract computation on the lo w packed single precision floating-point values using 
XMM register or a 32-bit memory location. 
VFMSUB132SS: Multiplies the low packed single precision floa ting-point value from the first source operand to the 
low packed single precision floating-point value in the th ird source operand. From the infinite precision interme-
diate result, subtracts the low packed single precision floati ng-point values in the second source operand, performs 
rounding and stores the resulting packed single precisio n floating-point value to the destination operand (first 
source operand).
VFMSUB213SS: Multiplies the low packed single precision fl oating-point value from the second source operand to 
the low packed single precision floating-point value in the first source operand. From the infinite precision interme-
diate result, subtracts the low packed single precision floa ting-point value in the third source operand, performs 
VFMSUB231SS: Multiplies the low packed single precision fl oating-point value from the second source to the low 
packed single precision floating-point value in the third source operand. From the infi nite precision intermediate 
result, subtracts the low packed single precision floating-p oint value in the first source operand, performs rounding 
and stores the resulting packed single precision floating-point value to the destination operand (first source 
operand).Opcode/
En64/32 
Bit Mode 
Feature 
VEX.LIG.66.0F38.W0 9B /r 
VFMSUB132SS xmm1, xmm2, 
xmm3/m32A V/V FMA Multiply scalar single precision floating-point value from 
xmm1 and xmm3/m32, subtract xmm2 and put result in 
xmm1.
VEX.LIG.66.0F38.W0 AB /r
VFMSUB213SS xmm1, xmm2, 
xmm3/m32 A V/V FMA Multiply scalar single precision floating-point value from 
xmm1 and xmm2, subtract xmm3/m32 and put result in 
xmm1.
VEX.LIG.66.0F38.W0 BB /r 
VFMSUB231SS xmm1, xmm2, xmm3/m32A V/V FMA Multiply scalar single precision floating-point value from 
xmm2 and xmm3/m32, subtract xmm1 and put result in xmm1.
EVEX.LLIG.66.0F38.W0 9B /r 
VFMSUB132SS xmm1 {k1}{z}, 
xmm2, xmm3/m32{er}B V/V AVX512F Multiply scalar single pr ecision floating-point value from 
xmm1.
EVEX.LLIG.66.0F38.W0 AB /r 
VFMSUB213SS xmm1 {k1}{z}, 
xmm2, xmm3/m32{er} B V/V AVX512F Multiply scalar single pr ecision floating-point value from 
xmm1.
EVEX.LLIG.66.0F38.W0 BB /r 
VFMSUB231SS xmm1 {k1}{z}, 
xmm2 and xmm3/m32, subtract xmm1 and put result in 
xmm1.
B Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-269VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. 
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
column.
Operation
VFMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(DEST[31:0]*SRC3[31:0] - SRC2[31:0])ELSE 
FI;
VFMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(S RC2[31:0]*DEST[31:0] - SRC3[31:0])
ELSE 
FI;
FI;DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-270 Vol. 2CVFMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(SRC2[31:0]*SRC3[63:0] - DEST[31:0])ELSE 
FI;
VFMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] - SRC2[31:0])DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] - SRC3[31:0])DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0

THEN
ELSE 
FI;
VFMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] - DEST[31:0])DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFMSUBxxxSS __m128 _mm_fmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFMSUBxxxSS __m128 _mm_mask_fmsub_ss(__m128  a, __mmask8 k, __m128 b, __m128 c);
VFMSUBxxxSS __m128 _mm_maskz_fmsub_ss(__m mask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBxxxSS __m128 _mm_mask3_fmsub_ss(__m128  a, __m128 b, __m128 c, __mmask8 k);
VFMSUBxxxSS __m128 _mm_mask_fmsub_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);VFMSUBxxxSS __m128 _mm_maskz_fmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);VFMSUBxxxSS __m128 _mm_mask3_fmsu b_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFMSUBxxxSS __m128 _mm_fmsub_ss ( __m128 a, __m128 b, __m128 c);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD 231PD—Fused Multiply-Alternating Subtrac t/Add of Packed Double Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-271VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBAD D231PD—Fused Multiply-Alternating 
Subtract/Add of Packed Double Precision Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W1 97 /r 
VFMSUBADD132PD xmm1, xmm2, 
from xmm1 and xmm3/mem, subtract/add elements 
in xmm2 and put result in xmm1.
VEX.128.66.0F38.W1 A7 /r 
VFMSUBADD213PD xmm1, xmm2, 
from xmm1 and xmm2, subtract/add elements in 
VEX.128.66.0F38.W1 B7 /r 
VFMSUBADD231PD xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed double precision floating-point values 
from xmm2 and xmm3/mem, subtract/add elements in xmm1 and put result in xmm1.
VEX.256.66.0F38.W1 97 /r 
VFMSUBADD132PD ymm1, ymm2, 
from ymm1 and ymm3/mem, subtract/add elements 
in ymm2 and put result in ymm1.
VEX.256.66.0F38.W1 A7 /r 
VFMSUBADD213PD ymm1, ymm2, 
from ymm1 and ymm2, subtract/add elements in 
VEX.256.66.0F38.W1 B7 /r 
VFMSUBADD231PD ymm1, ymm2, 
from ymm2 and ymm3/mem, subtract/add elements 
in ymm1 and put result in ymm1.
EVEX.128.66.0F38.W1 97 /r 
VFMSUBADD132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
from xmm1 and xmm3/m128/m64bcst, subtract/add elements in xmm2 and put re sult in xmm1 subject to 
EVEX.128.66.0F38.W1 A7 /r 
VFMSUBADD213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
from xmm1 and xmm2, subtract/add elements in xmm3/m128/m64bcst and put result in xmm1 
EVEX.128.66.0F38.W1 B7 /r 
VFMSUBADD231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
from xmm2 and xmm3/m128/m64bcst, subtract/add elements in xmm1 and put re sult in xmm1 subject to 
EVEX.256.66.0F38.W1 97 /r 
VFMSUBADD132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstBV / V A V X 5 1 2 V L
from ymm1 and ymm3/m256/m64bcst, subtract/add elements in ymm2 and put re sult in ymm1 subject to 
EVEX.256.66.0F38.W1 A7 /r 
VFMSUBADD213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstBV / V A V X 5 1 2 V L
from ymm1 and ymm2, subtract/add elements in ymm3/m256/m64bcst and put result in ymm1 
EVEX.256.66.0F38.W1 B7 /r
VFMSUBADD231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstBV / V A V X 5 1 2 V L
from ymm2 and ymm3/m256/m64bcst, subtract/add elements in ymm1 and put re sult in ymm1 subject to 
writemask k1.VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply -Alternating Subtract/Add of Packed Double PrecisionINSTRUCTION SET REFERENCE, V
5-272 Vol. 2CInstruction Operand Encoding
VFMSUBADD132PD: Multiplies the two, four, or eight packed double precision floating-point values from the first 
the infinite precision intermediate result, subtracts the odd double precision floating-point elements and adds the even double precision floating-point values in the se cond source operand, performs rounding and stores the 
operand).
VFMSUBADD213PD: Multiplies the two, four, or eight packed double precision floating-point values from the second 
the infinite precision intermediate result, subtracts the odd double precision floating-point elements and adds the 
VFMSUBADD231PD: Multiplies the two, four, or eight packed double precision floating-point values from the second 
the infinite precision intermediate result, subtracts the odd double precision floating-point elements and adds the even double precision floating-point values in the first source operand, performs rounding and stores the resulting 
opcode/instruction column of the summary table. The be havior of the complementary mnemonic in situations EVEX.512.66.0F38.W1 97 /r 
VFMSUBADD132PD zmm1 {k1}{z}, 
from zmm1 and zmm3/m512/m64bcst, subtract/add 
EVEX.512.66.0F38.W1 A7 /r 
VFMSUBADD213PD zmm1 {k1}{z}, 
from zmm1 and zmm2, subtract/add elements in 
EVEX.512.66.0F38.W1 B7 /r
VFMSUBADD231PD zmm1 {k1}{z}, 
from zmm2 and zmm3/m512/m64bcst, subtract/add 
En64/32 
Bit Mode 
Feature 
FlagDescriptionVFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD 231PD—Fused Multiply-Alternating Subtrac t/Add of Packed Double Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-273involving NANs are governed by the de finition of the instruction mnemonic defined in the opcode/instruction 
column.
Operation
VFMSUBADD132PD DEST, SRC2, SRC3 
IF (VEX.128) THEN

En64/32 
Bit Mode 
Feature 
column.
Operation
DEST[63:0] := RoundFPControl_MXCSR( DEST[63:0]*SRC3[63:0] + SRC2[63:0])
DEST[127:64] := RoundFPControl_MXCSR(DES T[127:64]*SRC3[127:64] - SRC2[127:64])
DEST[191:128] := RoundFPControl_MXCSR(DES T[191:128]*SRC3[191:128] + SRC2[191:128])
DEST[255:192] := RoundFPControl_MXCSR(DES T[255:192]*SRC3[255:192] - SRC2[255:192]
FI
VFMSUBADD213PD DEST, SRC2, SRC3 
DEST[63:0] := RoundFPControl_MXCSR( SRC2[63:0]*DEST[63:0] + SRC3[63:0])
DEST[127:64] := RoundFPControl_MXCSR(SRC 2[127:64]*DEST[127:64] - SRC3[127:64])
DEST[191:128] := RoundFPControl_MXCSR(SRC 2[191:128]*DEST[191:128] + SRC3[191:128])
DEST[255:192] := RoundFPControl_MXCSR(SRC 2[255:192]*DEST[255:192] - SRC3[255:192]
FI
VFMSUBADD231PD DEST, SRC2, SRC3 
DEST[63:0] := RoundFPControl_MXCSR( SRC2[63:0]*SRC3[63:0] + DEST[63:0])
DEST[127:64] := RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])DEST[MAXVL-1:128] := 0
DEST[127:64] := RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])DEST[191:128] := RoundFPControl_MXCSR(SRC 2[191:128]*SRC3[191:128] + DEST[191:128])
DEST[255:192] := RoundFPControl_MXCSR(SRC 2[255:192]*SRC3[255:192] - DEST[255:192]
FI
VFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
THEN
ELSE 
i := j * 64IF k1[j] OR *no writemask*VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply -Alternating Subtract/Add of Packed Double PrecisionINSTRUCTION SET REFERENCE, V
5-274 Vol. 2CTHEN 
FI
ELSE 
FI
FI;
VFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operan d is a memory source)
THEN 
THEN 
THEN
ELSE 
ELSE 
THEN
ELSE 
RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])FI;
FI
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD 231PD—Fused Multiply-Alternating Subtrac t/Add of Packed Double Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-275VFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
THEN
ELSE 
THEN 
FI
ELSE 
FI
FI;
VFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+63:i ]*DEST[i+63:i] + SRC3[63:0])
ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i ]*DEST[i+63:i] + SRC3[i+63:i])
FI;
ELSE 
THEN
ELSE 
RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])FI;VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply -Alternating Subtract/Add of Packed Double PrecisionINSTRUCTION SET REFERENCE, V
5-276 Vol. 2CFI
ELSE 
FI
FI;
VFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 op erand is a register)
THEN
ELSE 
THEN 
FI
ELSE 
FI
FI;
VFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operan d is a memory source)
THEN 
THEN 
THEN
ELSE 
DEST[i+63:i] := VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD 231PD—Fused Multiply-Alternating Subtrac t/Add of Packed Double Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-277RoundFPControl_MXCSR(SRC2[i+63:i ]*SRC3[i+63:i] + DEST[i+63:i])
FI;
ELSE 
THEN
ELSE 
FI;
FI
ELSE 
FI
FI;
VFMSUBADDxxxPD __m512d _mm512_fmsubadd_pd (__m512d a, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_fmsubadd_round_pd (__m512d a, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_mask_fmsubadd_pd(__m 512d a, __mmask8 k, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_maskz_fmsubadd_pd( __mmask8 k, __m512d a, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_mask3_fmsubadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);VFMSUBADDxxxPD __m512d _mm512_mask_fm subadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_maskz_fmsubadd_round_pd(__m mask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_mask3_fmsubadd_round_pd(__ m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMSUBADDxxxPD __m256d _mm256_mask_fmsubadd_pd(__m 256d a, __mmask8 k, __m256d b, __m256d c);
VFMSUBADDxxxPD __m256d _mm256_maskz_fmsubadd_pd( __mmask8 k, __m256d a, __m256d b, __m256d c);
VFMSUBADDxxxPD __m256d _mm256_mask3_fmsubadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);VFMSUBADDxxxPD __m128d _mm_mask_fmsubadd_pd(__m1 28d a, __mmask8 k, __m128d b, __m128d c);
VFMSUBADDxxxPD __m128d _mm_maskz_fmsubadd_pd(__m mask8 k, __m128d a, __m128d b, __m128d c);
VFMSUBADDxxxPD __m128d _mm_mask3_fmsubadd_pd(__m12 8d a, __m128d b, __m128d c, __mmask8 k);
VFMSUBADDxxxPD __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);VFMSUBADDxxxPD __m256d _mm256_fmsubadd_pd  (__m256d a, __m256d b, __m256d c);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VFMSUBADD132PH/VFMSUBADD213P H/VFMSUBADD231PH—Fused Multiply-Alternati ng Subtract/Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-278 Vol. 2CVFMSUBADD132PH/VFMSUBADD213PH/VFMSUBAD D231PH—Fused Multiply-Alternating 
Subtract/Add of Packed FP16 Values
This instruction performs a packed multiply-add (even el ements) or multiply-subtract (odd elements) computation 
operand is also the first source operand. The notation “132 ”, “213” and “231” indicate the use of the operands in A

operand is also the first source operand. The notation “132 ”, “213” and “231” indicate the use of the operands in A 
En64/32 
Bit Mode 
EVEX.128.66.MAP6.W0  97 /r
VFMSUBADD132PH  xmm1{k1}{z},  
xmm3/m128/m16bcst, subtra ct/add elements in 
xmm2, and store the result in xmm1 subject to writemask k1.
EVEX.256.66.MAP6.W0  97 /r
VFMSUBADD132PH  ymm1{k1}{z},  
ymm3/m256/m16bcst, subtract/add elements in 
EVEX.512.66.MAP6.W0  97 /r
VFMSUBADD132PH  zmm1{k1}{z},  
zmm3/m512/m16bcst, subtract/add elements in 
EVEX.128.66.MAP6.W0  A7 /r
VFMSUBADD213PH  xmm1{k1}{z},  
xmm2, subtract/add elements in xmm3/m128/m16bcst, and store the resu lt in xmm1 subject to 
EVEX.256.66.MAP6.W0  A7 /r
VFMSUBADD213PH  ymm1{k1}{z},  
ymm2, subtract/add elements in ymm3/m256/m16bcst, and store the result in ymm1 subject to 
EVEX.512.66.MAP6.W0  A7 /r
VFMSUBADD213PH  zmm1{k1}{z},  
zmm2, subtract/add elements in zmm3/m512/m16bcst, and store the resu lt in zmm1 subject to 
EVEX.128.66.MAP6.W0  B7 /r
VFMSUBADD231PH  xmm1{k1}{z},  
xmm1, and store the result in xmm1 subject to 
EVEX.256.66.MAP6.W0  B7 /r
VFMSUBADD231PH  ymm1{k1}{z},  
ymm3/m256/m16bcst, subtract/add elements in ymm1, and store the result in ymm1 subject to 
EVEX.512.66.MAP6.W0  B7 /r
VFMSUBADD231PH  zmm1{k1}{z},  
zmm3/m512/m16bcst, subtract/add elements in zmm1, and store the result  in zmm1 subject to 
A Full ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/AVFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH—Fused Mult iply-Alternating Subtract/ Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-279Operation
VFMSUBADD132PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
ELSE
ELSE:
DEST[MAXVL-1:VL] := 0 VFMSUBADD132PH DEST, SRC2, SRC3 (EVEX encoded ve rsions) when src3 operand is a memory source
ELSE:
ELSE:
DEST[MAXVL-1:VL] := 0:Table 5-8.  VFMSUBADD[132,213,231]PH  Notation for Odd and Even Elements
132 dest = dest*src3-src2 dest = dest*src3+src2
231 dest = src2*src3-dest dest = src2*src3+dest213 dest = src2*dest-src3 dest = src2*dest+src3VFMSUBADD132PH/VFMSUBADD213P H/VFMSUBADD231PH—Fused Multiply-Alternati ng Subtract/Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-280 Vol. 2CVFMSUBADD213PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
ELSE
ELSE
DEST[MAXVL-1:VL] := 0VFMSUBADD213PH DEST, SRC2, SRC3 (EVEX encoded ve rsions) when src3 operand is a memory source
ELSE:
ELSE:
DEST[MAXVL-1:VL] := 0:VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH—Fused Mult iply-Alternating Subtract/ Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-281VFMSUBADD231PH DEST, SRC2, SRC3 (EVEX encoded versions) when src3 operand is a register
ELSE
ELSE:
DEST.fp16[j] := RoundFPControl(SRC2.fp16[j]*SRC3.fp16[j] - DEST.fp16[j])
DEST[MAXVL-1:VL] := 0VFMSUBADD231PH DEST, SRC2, SRC3 (EVEX encoded ve rsions) when src3 operand is a memory source
ELSE:
ELSE:
DEST[MAXVL-1:VL] := 0VFMSUBADD132PH/VFMSUBADD213P H/VFMSUBADD231PH—Fused Multiply-Alternati ng Subtract/Add of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-282 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VFMSUBADD132PH, VFMSUBADD2 13PH, and VFMSUBADD231PH:
__m128h _mm_fmsubadd_ph (__m128h a, __m128h b, __m128h c);__m128h _mm_mask_fmsubadd_ph (__m128h a, __mmask8 k, __m128h b, __m128h c);__m128h _mm_mask3_fmsubadd_ph (__m128h a, __m128h b, __m128h c, __mmask8 k);
__m128h _mm_maskz_fmsubadd_ph (__mmask8 k, __m128h a, __m128h b, __m128h c);__m256h _mm256_fmsubadd_ph (__m256h a, __m256h b, __m256h c);__m256h _mm256_mask_fmsubadd_ph (__m256h a, __mmask16 k, __m256h b, __m256h c);__m256h _mm256_mask3_fmsubadd_ph (__m256h a, __m256h b, __m256h c, __mmask16 k);
__m256h _mm256_maskz_fmsubadd_ph (__mmask 16 k, __m256h a, __m256h b, __m256h c);
__m512h _mm512_fmsubadd_ph (__m512h a, __m512h b, __m512h c);__m512h _mm512_mask_fmsubadd_ph (__m512h a, __mmask32 k, __m512h b, __m512h c);__m512h _mm512_mask3_fmsubadd_ph (__m512h a, __m512h b, __m512h c, __mmask32 k);
__m512h _mm512_maskz_fmsubadd_ph (__mmask 32 k, __m512h a, __m512h b, __m512h c);
__m512h _mm512_fmsubadd_round_ph (__m512h a,  __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask_fmsubadd_round_ph (__m512h a, __mma sk32 k, __m512h b, __m512h c, const int rounding);
__m512h _mm512_mask3_fmsubadd_round_ph (__m512h a, __ m512h b, __m512h c, __mmask32 k, const int rounding);
__m512h _mm512_maskz_fmsubadd_round_ph (__mmask32 k, __m 512h a, __m512h b, __m512h c, const int rounding);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD 231PS—Fused Multiply-Alternating Subtract/Add of Packed Single Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-283VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBAD D231PS—Fused Multiply-Alternating 
Subtract/Add of Packed Single Precision Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W0 97 /r 
VFMSUBADD132PS xmm1, xmm2, 
from xmm1 and xmm3/mem, subtract/add elements in 
VEX.128.66.0F38.W0 A7 /r 
VFMSUBADD213PS xmm1, xmm2, 
xmm3/m128 A V/V FMA Multiply packed single precision floating-point values 
VEX.128.66.0F38.W0 B7 /r 
VFMSUBADD231PS xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed single precision floating-point values 

Opcode/
En64/32 
Bit Mode 
Feature 
VEX.256.66.0F38.W0 97 /r 
VFMSUBADD132PS ymm1, ymm2, 
from ymm1 and ymm3/mem, subtract/add elements in 
VEX.256.66.0F38.W0 A7 /r 
VFMSUBADD213PS ymm1, ymm2, 
VEX.256.66.0F38.W0 B7 /r 
VFMSUBADD231PS ymm1, ymm2, 
from ymm2 and ymm3/mem, subtract/add elements in 
EVEX.128.66.0F38.W0 97 /r 
VFMSUBADD132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstB V/V AVX512VL
AVX512FMultiply packed single precision floating-point values 
from xmm1 and xmm3/m128/m32bcst, subtract/add elements in xmm2 and put re sult in xmm1 subject to 
EVEX.128.66.0F38.W0 A7 /r 
VFMSUBADD213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstB V/V AVX512VL
from xmm1 and xmm2, subtract/add elements in xmm3/m128/m32bcst and put result in xmm1 subject to 
EVEX.128.66.0F38.W0 B7 /r 
VFMSUBADD231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstB V/V AVX512VL
from xmm2 and xmm3/m128/m32bcst, subtract/add elements in xmm1 and put re sult in xmm1 subject to 
EVEX.256.66.0F38.W0 97 /r 
VFMSUBADD132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512VL
from ymm1 and ymm3/m256/m32bcst, subtract/add elements in ymm2 and put re sult in ymm1 subject to 
EVEX.256.66.0F38.W0 A7 /r 
VFMSUBADD213PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512VL
from ymm1 and ymm2, subtract/add elements in ymm3/m256/m32bcst and put result in ymm1 subject to 
EVEX.256.66.0F38.W0 B7 /r 
VFMSUBADD231PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512VL
from ymm2 and ymm3/m256/m32bcst, subtract/add elements in ymm1 and put re sult in ymm1 subject to 
writemask k1.VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply -Alternating Subtract/Add of  Packed Single PrecisionINSTRUCTION SET REFERENCE, V
5-284 Vol. 2CInstruction Operand Encoding
VFMSUBADD132PS: Multiplies the four, eight or sixteen packed  single precision floating-point values from the first 
From the infinite precision intermediate result, subtracts the odd single precision floating-point elements and adds the even single precision floating-point values in the second source operand, performs rounding and stores the 
VFMSUBADD213PS: Multiplies the four, eight or sixteen pack ed single precision floating-point values from the 
operand. From the infinite precision intermediate result, subtracts the odd single precision floating-point elements 
and adds the even single precision floating-point values in the third source operand, performs rounding and stores 
VFMSUBADD231PS: Multiplies the four, eight or sixteen pack ed single precision floating-point values from the 
and adds the even single precision floating-point values in the first source operand, performs rounding and stores 
column.EVEX.512.66.0F38.W0 97 /r 
VFMSUBADD132PS zmm1 {k1}{z}, 
zmm2, zmm3/m512/m32bcst{er}B V/V AVX512F Multiply packed single precision floating-point values 
from zmm1 and zmm3/m512/m32bcst, subtract/add 
EVEX.512.66.0F38.W0 A7 /r 
VFMSUBADD213PS zmm1 {k1}{z}, 
from zmm1 and zmm2, subt ract/add elements in 
zmm3/m512/m32bcst and put result in zmm1 subject to 
EVEX.512.66.0F38.W0 B7 /r 
VFMSUBADD231PS zmm1 {k1}{z}, 
from zmm2 and zmm3/m512/m32bcst, subtract/add 
En64/32 
Bit Mode 
Feature 
FlagDescriptionVFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD 231PS—Fused Multiply-Alternating Subtract/Add of Packed Single Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-285Operation
VFMSUBADD132PS DEST, SRC2, SRC3 
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+31:n] := RoundFPControl_MXCSR(DES T[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])
DEST[n+63:n+32] := RoundFPControl_MXCSR(DEST[n +63:n+32]*SRC3[n+63:n+32] -SRC2[n+63:n+32])
FI
VFMSUBADD213PS DEST, SRC2, SRC3 
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+31:n] := RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] +SRC3[n+31:n])DEST[n+63:n+32] := RoundFPControl_MXCSR(SRC2[n +63:n+32]*DEST[n+63:n+32] -SRC3[n+63:n+32])
FI
VFMSUBADD231PS DEST, SRC2, SRC3 
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+31:n] := RoundFPControl_MXCSR(SRC 2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])
DEST[n+63:n+32] := RoundFPControl_MXCSR(SRC2[n +63:n+32]*SRC3[n+63:n+32] -DEST[n+63:n+32])
FIVFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply -Alternating Subtract/Add of  Packed Single PrecisionINSTRUCTION SET REFERENCE, V
5-286 Vol. 2CVFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
THEN
ELSE 
THEN 
FI
ELSE 
FI
FI;
VFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN 
THEN

THEN
ELSE 
THEN 
FI
ELSE 
FI
FI;
THEN 
THEN 
THEN
ELSE 
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
FI;
ELSE 
THEN
ELSE 
RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD 231PS—Fused Multiply-Alternating Subtract/Add of Packed Single Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-287FI;
FI
ELSE 
FI
FI;
VFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
THEN
ELSE 
THEN 
FI
ELSE 
FI
FI;
VFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+31:i ]*DEST[i+31:i] + SRC3[31:0])VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply -Alternating Subtract/Add of  Packed Single PrecisionINSTRUCTION SET REFERENCE, V
5-288 Vol. 2CELSE 
RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
FI;ELSE 
THEN
ELSE 
FI;
FI
ELSE 
FI
FI;
VFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
THEN
ELSE 
THEN 
FI
ELSE 
FI
FI;
VFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD 231PS—Fused Multiply-Alternating Subtract/Add of Packed Single Precision INSTRUCTION SET REFERENCE, V
Vol. 2C 5-289FOR j := 0 TO KL-1
THEN 
THEN 
THEN
RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])ELSE 
RoundFPControl_MXCSR(SRC2[i+31:i] *SRC3[i+31:i] + DEST[i+31:i])
FI;
ELSE 
THEN
ELSE 
FI;
FI
ELSE 
FI
FI;
VFMSUBADDxxxPS __m512 _mm512_fmsubadd_ps(__m512 a, __m512 b, __m512 c);
VFMSUBADDxxxPS __m512 _mm512_fmsubadd_round_p s(__m512 a, __m512 b, __m512 c, int r);
VFMSUBADDxxxPS __m512 _mm512_mask_fmsubadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);VFMSUBADDxxxPS __m512 _mm512_maskz_fmsubadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);VFMSUBADDxxxPS __m512 _mm512_mask3_fmsubadd_ps( __m512 a, __m512 b, __m512 c, __mmask16 k);
VFMSUBADDxxxPS __m512 _mm512_mask_fmsubadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);VFMSUBADDxxxPS __m512 _mm512_maskz_fmsubadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);VFMSUBADDxxxPS __m512 _mm512_mask3_fmsubadd_round_ps(__m5 12 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMSUBADDxxxPS __m256 _mm256_mask_fmsubadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);VFMSUBADDxxxPS __m256 _mm256_maskz_fmsubadd_ps(__m mask8 k, __m256 a, __m256 b, __m256 c);
VFMSUBADDxxxPS __m256 _mm256_mask3_fmsubadd_ps( __m256 a, __m256 b, __m256 c, __mmask8 k);
VFMSUBADDxxxPS __m128 _mm_mask_fmsubadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);VFMSUBADDxxxPS __m128 _mm_maskz_fmsubadd_ps(__m mask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBADDxxxPS __m128 _mm_mask3_fmsubadd_ps( __m128 a, __m128 b, __m128 c, __mmask8 k);
VFMSUBADDxxxPS __m128 _mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c);VFMSUBADDxxxPS __m256 _mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c);VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply -Alternating Subtract/Add of  Packed Single PrecisionINSTRUCTION SET REFERENCE, V
5-290 Vol. 2CSIMD Floating-Point Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VFNMADD132PD/VFNMADD213PD/ VFNMADD231PD—Fused Negative Multiply-Add of Pa cked Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-291VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fu sed Negative Multiply-Add of Packed 
Double Precision Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W1 9C /r 
VFNMADD132PD xmm1, xmm2, 
xmm3/m128A V/V FMA Multiply packed double precision floating-point values from 
xmm1 and xmm3/mem, negate the multiplica tion result 
and add to xmm2 and put result in xmm1.
VEX.128.66.0F38.W1 AC /r 
VFNMADD213PD xmm1, xmm2, 
xmm1 and xmm2, negate the mu ltiplication result and add 
to xmm3/mem and put result in xmm1.
VEX.128.66.0F38.W1 BC /r 
VFNMADD231PD xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed double precision floating-point values from 
xmm2 and xmm3/mem, negate the multiplica tion result 
and add to xmm1 and put result in xmm1.
VEX.256.66.0F38.W1 9C /r 
VFNMADD132PD ymm1, ymm2, 
ymm3/m256A V/V FMA Multiply packed double precision floating-point values from 
ymm1 and ymm3/mem, negate th e multiplication result and 
add to ymm2 and put result in ymm1.
VEX.256.66.0F38.W1 AC /r 
VFNMADD213PD ymm1, ymm2, 
ymm1 and ymm2, negate the mu ltiplication result and add 
to ymm3/mem and put result in ymm1.
VEX.256.66.0F38.W1 BC /r 
VFNMADD231PD ymm1, ymm2, 
ymm2 and ymm3/mem, negate th e multiplication result and 
add to ymm1 and put result in ymm1.
EVEX.128.66.0F38.W1 9C /r 
VFNMADD132PD xmm0 {k1}{z}, xmm1, xmm2/m128/m64bcstBV / V A V X 5 1 2 V L
AVX512FMultiply packed doub le precision floating-point values from 
xmm1 and xmm3/m128/m64bcst, negate the multiplication result and add to xmm2 and put result in 
xmm1.
EVEX.128.66.0F38.W1 AC /r
VFNMADD213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
to xmm3/m128/m64bcst and put result in xmm1.
EVEX.128.66.0F38.W1 BC /r 
VFNMADD231PD xmm1 {k1}{z}, 
xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
xmm2 and xmm3/m128/m64bcst, negate the 
multiplication result and add to xmm1 and put result in 
xmm1.
EVEX.256.66.0F38.W1 9C /r 
VFNMADD132PD ymm1 {k1}{z}, 
ymm1 and ymm3/m256/m6 4bcst, negate the 
multiplication result and add to ymm2 and put result in 
ymm1.
EVEX.256.66.0F38.W1 AC /r 
VFNMADD213PD ymm1 {k1}{z}, 
ymm1 and ymm2, negate the mu ltiplication re sult and add 
to ymm3/m256/m64bcst and put result in ymm1.
EVEX.256.66.0F38.W1 BC /r 
VFNMADD231PD ymm1 {k1}{z}, 
ymm2 and ymm3/m256/m6 4bcst, negate the 
multiplication result and add to ymm1 and put result in

xmm1.
ymm1.
multiplication result and add to ymm1 and put result in 
ymm1.VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply -Add of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-292 Vol. 2CInstruction Operand Encoding
VFNMADD132PD: Multiplies the two, four or eight packed double precision fl oating-point values from the first 
source operand to the two, four or eight packed double pr ecision floating-point values in the third source operand, 
adds the negated infinite precision intermediate result to the two, four or eight packed  double precision floating-
point values in the second source operand, performs round ing and stores the resulting two, four or eight packed 
VFNMADD213PD: Multiplies the two, four or eight packed do uble precision floating-point values from the second 
VFNMADD231PD: Multiplies the two, four or eight packed do uble precision floating-point values from the second 
source to the two, four or eight packed double precisio n floating-point values in the third source operand, the 
negated infinite precision intermediate result to the two, fo ur or eight packed double precision floating-point values 
Operation
In the operations below, “*” an d “-” symbols represent multiplication and subtra ction with infinite precision inputs and output s (no 
rounding).EVEX.512.66.0F38.W1 9C /r 
VFNMADD132PD zmm1 {k1}{z}, 
zmm2, zmm3/m512/m64bcst{er}B V/V AVX512F Multiply packed double precision floating-point values from 
zmm1 and zmm3/m512/m64bcst, negate the mu ltiplication 
result and add to zmm2 and put result in zmm1.
EVEX.512.66.0F38.W1 AC /r 
VFNMADD213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}B V/V AVX512F Multiply packed double precision floating-point values from 
zmm1 and zmm2, negate the mu ltiplication re sult and add 
to zmm3/m512/m64bcst and put result in zmm1.
EVEX.512.66.0F38.W1 BC /r 
VFNMADD231PD zmm1 {k1}{z}, 
zmm2 and zmm3/m512/m64bcst, negate the mu ltiplication 
result and add to zmm1 and put result in zmm1.
En64/32 
Bit Mode 
Feature 
FlagDescriptionVFNMADD132PD/VFNMADD213PD/ VFNMADD231PD—Fused Negative Multiply-Add of Pa cked Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-293VFNMADD132PD DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(-(D EST[n+63:n]*SRC3[n+63:n]) + SRC2[n+63:n])
FI
VFNMADD213PD DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(-(SRC2[n+63:n]*DEST[n+63:n]) + SRC3[n+63:n])
FI
VFNMADD231PD DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR(-(S RC2[n+63:n]*SRC3[n+63:n]) + DEST[n+63:n])
FIVFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply -Add of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-294 Vol. 2CVFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(-(DEST[i+63:i]*S RC3[i+63:i]) + SRC2[i+63:i])
ELSE 
FI
FI;
VFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) + SRC2[i+63:i])
ELSE 
RoundFPControl_MXCSR(-(DEST[i+63: i]*SRC3[i+63:i]) + SRC2[i+63:i])
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFNMADD132PD/VFNMADD213PD/ VFNMADD231PD—Fused Negative Multiply-Add of Pa cked Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-295VFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(-(SRC2[i+63:i]*D EST[i+63:i]) + SRC3[i+63:i])
ELSE 
FI
FI;
VFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(SRC2[i+63: i]*DEST[i+63:i]) + SRC3[63:0])
ELSE 
RoundFPControl_MXCSR(-(SRC2[i+63: i]*DEST[i+63:i]) + SRC3[i+63:i])
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply -Add of Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-296 Vol. 2CVFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(-(SRC2[i+63:i]*S RC3[i+63:i]) + DEST[i+63:i])
ELSE 
FI
FI;
VFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) + DEST[i+63:i])
ELSE 
RoundFPControl_MXCSR(-(SRC2[i+63:i] *SRC3[i+63:i]) + DEST[i+63:i])
FI;
ELSE 
FI
FI;

THEN
ELSE 
ELSE 
FI
FI;
THEN 
THEN
ELSE 
FI;
ELSE 
FI
FI;
Vol. 2C 5-297Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxPD __m512d _mm512_fnmadd_p d(__m512d a, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_fnmadd_round_pd( __m512d a, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_mask_fnmadd_pd(__m 512d a, __mmask8 k, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_maskz_fnmadd_pd(__m mask8 k, __m512d a, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_mask3_fnmadd_pd(__m 512d a, __m512d b, __m512d c, __mmask8 k);
VFNMADDxxxPD __m512d _mm512_mask_fnmadd_round_pd(__m51 2d a, __mmask8 k, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_maskz_fnmadd_round_pd(__ mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_mask3_fnmadd_round_pd(__m51 2d a, __m512d b, __m512d c, __mmask8 k, int r);
VFNMADDxxxPD __m256d _mm256_mask_fnmadd_pd(__m 256d a, __mmask8 k, __m256d b, __m256d c);
VFNMADDxxxPD __m256d _mm256_maskz_fnmadd_pd(__m mask8 k, __m256d a, __m256d b, __m256d c);
VFNMADDxxxPD __m256d _mm256_mask3_fnmadd_pd(__m 256d a, __m256d b, __m256d c, __mmask8 k);
VFNMADDxxxPD __m128d _mm_mask_fnmadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);VFNMADDxxxPD __m128d _mm_maskz_fnmadd_pd(__m mask8 k, __m128d a, __m128d b, __m128d c);
VFNMADDxxxPD __m128d _mm_mask3_fnmadd_pd(__ m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMADDxxxPD __m128d _mm_fnmadd_pd (__m128d a, __m128d b, __m128d c);VFNMADDxxxPD __m256d _mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multip ly-Add of Packed Single Prec ision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-298 Vol. 2CVFNMADD132PS/VFNMADD213PS/VFNMADD231PS— Fused Negative Multiply-Add of Packed 
Single Precision Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W0 9C /r
VFNMADD132PS xmm1, xmm2, 
xmm1 and xmm3/mem, negate the multiplication result 
VEX.128.66.0F38.W0 AC /r 
VFNMADD213PS xmm1, xmm2, 
xmm1 and xmm2, negate the multiplication result and add 
VEX.128.66.0F38.W0 BC /r 
VFNMADD231PS xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed single precision floating-point values from 
xmm2 and xmm3/mem, negate the multiplication result and add to xmm1 and put result in xmm1.
VEX.256.66.0F38.W0 9C /r 
VFNMADD132PS ymm1, ymm2, 
ymm1 and ymm3/mem, negate the multiplica tion result 
and add to ymm2 and put result in ymm1.
VEX.256.66.0F38.W0 AC /r 
VFNMADD213PS ymm1, ymm2, 
VEX.256.66.0F38.0 BC /r 
VFNMADD231PS ymm1, ymm2, 
ymm2 and ymm3/mem, negate th e multiplication  result and 
EVEX.128.66.0F38.W0 9C /r
VFNMADD132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstB V/V AVX512VL
AVX512FMultiply packed single precision floating-point values from 
xmm1 and xmm3/m128/m32bcst, negate the mu ltiplication 
result and add to xmm2 and put result in xmm1.
EVEX.128.66.0F38.W0 AC /r 
VFNMADD213PS xmm1 {k1}{z}, 
to xmm3/m128/m32bcst and put result in xmm1.
EVEX.128.66.0F38.W0 BC /r 
VFNMADD231PS xmm1 {k1}{z}, 
xmm2 and xmm3/m128/m32bcst, negate the mu ltiplication 
result and add to xmm1 and put result in xmm1.
EVEX.256.66.0F38.W0 9C /r 
VFNMADD132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512VL
ymm1 and ymm3/m256/m32bcst, negate the multiplication result and add to ymm2 and put result in ymm1.
EVEX.256.66.0F38.W0 AC /r 
VFNMADD213PS ymm1 {k1}{z}, 
to ymm3/m256/m32bcst and put result in ymm1.
EVEX.256.66.0F38.W0 BC /r 
VFNMADD231PS ymm1 {k1}{z}, 
ymm2 and ymm3/m256/m32bcst, negate the multiplication 
result and add to ymm1 and put result in ymm1.
EVEX.512.66.0F38.W0 9C /r 
VFNMADD132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}B V/V AVX512VL
zmm1 and zmm3/m512/m32bcst, negate the multiplication result and add to zmm2 and put result in zmm1.
EVEX.512.66.0F38.W0 AC /r 
VFNMADD213PS zmm1 {k1}{z}, 
zmm1 and zmm2, negate the mu ltiplication result and add 
to zmm3/m512/m32bcst and put result in zmm1.
EVEX.512.66.0F38.W0 BC /r 
VFNMADD231PS zmm1 {k1}{z}, 
zmm2 and zmm3/m512/m32bcst, negate the multiplication 
result and add to zmm1 and put result in zmm1.VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fuse d Negative Multiply-Add of Packed Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-299Instruction Operand Encoding
VFNMADD132PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the first 
source operand to the four, eight or sixteen packed single precision floating-point values in the third source operand, adds the negated infinite precision intermediate re sult to the four, eight or sixteen packed single precision 
VFNMADD213PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the second 
operand, adds the negated infinite precision intermediate re sult to the four, eight or sixteen packed single precision 
floating-point values in the third source operand, perf orms rounding and stores the resulting the four, eight or 
VFNMADD231PS: Multiplies the four, eight or sixteen packed single precision floating-point values from the second 
floating-point values in the first source operand, performs  rounding and stores the resulting four, eight or sixteen 
Operation

Operation
VFNMADD132PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(- (D EST[n+31:n]*SRC3[n+31:n]) + SRC2[n+31:n])
FIOp/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (r, w) VEX. vvvv (r) ModRM:r/m (r) N/A
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multip ly-Add of Packed Single Prec ision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-300 Vol. 2CVFNMADD213PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(- (S RC2[n+31:n]*DEST[n+31:n]) + SRC3[n+31:n])
FI
VFNMADD231PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR(- (S RC2[n+31:n]*SRC3[n+31:n]) + DEST[n+31:n])
FI
VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(-(DEST[i+31:i]*S RC3[i+31:i]) + SRC2[i+31:i])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fuse d Negative Multiply-Add of Packed Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-301VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) + SRC2[i+31:i])
ELSE 
RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i])FI;
ELSE 
FI
FI;
VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(-(SRC2[i+31:i]*D EST[i+31:i]) + SRC3[i+31:i])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multip ly-Add of Packed Single Prec ision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-302 Vol. 2CVFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(SRC2[i+31: i]*DEST[i+31:i]) + SRC3[31:0])
ELSE 
RoundFPControl_MXCSR(-(SRC2[i+31: i]*DEST[i+31:i]) + SRC3[i+31:i])
FI;
ELSE 
FI
FI;
VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(-(SRC2[i+31:i]*S RC3[i+31:i]) + DEST[i+31:i])
ELSE 
FI
FI;
Vol. 2C 5-303VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(SRC2[i+31: i]*SRC3[31:0]) + DEST[i+31:i])
ELSE 
RoundFPControl_MXCSR(-(SRC2[i+31:i] *SRC3[i+31:i]) + DEST[i+31:i])
FI;
ELSE 
FI
FI;
VFNMADDxxxPS __m512 _mm512_fnmadd_ps(__m512 a, __m512 b, __m512 c);
VFNMADDxxxPS __m512 _mm512_fnmadd_round_ps (__m512 a, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_mask_fnmadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);VFNMADDxxxPS __m512 _mm512_maskz_fnmadd_ps(__mma sk16 k, __m512 a, __m512 b, __m512 c);
VFNMADDxxxPS __m512 _mm512_mask3_fnmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);VFNMADDxxxPS __m512 _mm512_mask_fn madd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_maskz_fnmadd_round_ps(__ mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_mask3_fnmadd_round_ps(__m 512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFNMADDxxxPS __m256 _mm256_mask_fnmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);VFNMADDxxxPS __m256 _mm256_maskz_fnmadd_ps( __mmask8 k, __m256 a, __m256 b, __m256 c);
VFNMADDxxxPS __m256 _mm256_mask3_fnmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);VFNMADDxxxPS __m128 _mm_mask_f nmadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMADDxxxPS __m128 _mm_maskz_fnmadd_ps(__m mask8 k, __m128 a, __m128 b, __m128 c);
VFNMADDxxxPS __m128 _mm_mask 3_fnmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMADDxxxPS __m128 _mm_fnmadd_ps (__m128 a, __m128 b, __m128 c);
VFNMADDxxxPS __m256 _mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multip ly-Add of Scalar Double Prec ision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-304 Vol. 2CVFNMADD132SD/VFNMADD213SD/VF NMADD231SD—Fused Negative Multiply-Add of Scalar 
VFNMADD132SD: Multiplies the low packed double precision floating-point value from the first source operand to 
the low packed double precision floating-point value in the third source operand, adds the negated infinite precision 
intermediate result to the low packed double precision floating-point values in the second source operand, 
VFNMADD213SD: Multiplies the low packed double precision floating-point value from the second source operand 
to the low packed double precision floating-point value in the first source operand, adds the negated infinite preci-
sion intermediate result to the low packed double prec ision floating-point value in the third source operand, 
VFNMADD231SD: Multiplies the low packed  double precision floating-point valu e from the second source to the low 
packed double precision floating-point value in the third source operand, adds the negated infinite precision inter-
mediate result to the low packed double precision floati ng-point value in the first source operand, performs 
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.LIG.66.0F38.W1 9D /r 
VFNMADD132SD xmm1, xmm2,

En64/32 
Bit Mode 
Feature 
VFNMADD132SD xmm1, xmm2, 
xmm1 and xmm3/mem, negate th e multiplication result and 
add to xmm2 and put result in xmm1.
VEX.LIG.66.0F38.W1 AD /r
VFNMADD213SD xmm1, xmm2, 
xmm1 and xmm2, negate the multiplication result and add to 
VEX.LIG.66.0F38.W1 BD /r 
VFNMADD231SD xmm1, xmm2, xmm3/m64A V/V FMA Multiply scalar double precision floating-point value from 
xmm2 and xmm3/mem, negate th e multiplication result and 
add to xmm1 and put result in xmm1.
EVEX.LLIG.66.0F38.W1 9D /r
VFNMADD132SD xmm1 {k1}{z}, 
xmm1 and xmm3/m64, negate th e multiplication result and 
EVEX.LLIG.66.0F38.W1 AD /r 
VFNMADD213SD xmm1 {k1}{z}, 
xmm2, xmm3/m64{er} B V/V AVX512F Multiply scalar double precision floating-point value from 
xmm3/m64 and put result in xmm1.
EVEX.LLIG.66.0F38.W1 BD /r 
VFNMADD231SD xmm1 {k1}{z}, 
xmm2 and xmm3/m64, negate th e multiplication result and 
B Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFNMADD132SD/VFNMADD213SD/ VFNMADD231SD—Fused Negative Multiply-Add of Sc alar Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-305EVEX encoded version: The low quadword element of th e destination is updated according to the writemask.
column.
Operation
VFNMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
FI;
THEN DEST[63:0] := RoundFPControl(-(D EST[63:0]*SRC3[63:0]) + SRC2[63:0])
ELSE 
FI;
VFNMADD213SD DEST, SRC2, SRC3 (EVEX encoded version) 
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(-(S RC2[63:0]*DEST[63:0]) + SRC3[63:0])
ELSE 
FI;
FI;DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multip ly-Add of Scalar Double Prec ision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-306 Vol. 2CVFNMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) + DEST[63:0])ELSE 
FI;
VFNMADD132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) + SRC2[63:0])DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0
VFNMADD213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) + SRC3[63:0])
DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0
VFNMADD231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) + DEST[63:0])
VFNMADDxxxSD __m128d _mm_fnmadd_round_sd(__m 128d a, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_mask_fnmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);VFNMADDxxxSD __m128d _mm_maskz_fnmadd_sd(__mma sk8 k, __m128d a, __m128d b, __m128d c);
VFNMADDxxxSD __m128d _mm_mask3_fnmadd_sd(__m128 d a, __m128d b, __m128d c, __mmask8 k);
VFNMADDxxxSD __m128d _mm_mask_fnmadd_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_maskz_fnmadd_round_sd(__mmask 8 k, __m128d a, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_mask3_fnmadd_round_sd(__m128 d a, __m128d b, __m128d c, __mmask8 k, int r);
VFNMADDxxxSD __m128d _mm_fnmadd_sd (__m128d a, __m128d b, __m128d c);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multip ly-Add of Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-307VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fuse d Negative Multiply-Add of Scalar 
VFNMADD132SS: Multiplies the low packed single-precision floating-point value from the first source operand to 
the low packed single-precision floating-point value in the third source operand, adds th e negated infinite precision 
intermediate result to the low packed single-precision floating-point value in the second source operand, performs 
rounding and stores the resulting packed single-precision  floating-point value to the destination operand (first 
VFNMADD213SS: Multiplies the low packed single-precision fl oating-point value from the second source operand to 
the low packed single-precision floating-point value in the first source operand, adds the negated infinite precision 
intermediate result to the low packed single-precision fl oating-point value in the third source operand, performs 
VFNMADD231SS: Multiplies the low packed  single-precision floating-point value from the second source operand 
to the low packed single-precision floating-point value in the third source operand, adds the negated infinite preci-
sion intermediate result to the low packed single-precision floating-point value in the first source operand, 
performs rounding and stores the resulting packed single-p recision floating-point value to the destination operand 
En64/32 
Bit Mode 
Feature 
VEX.LIG.66.0F38.W0 9D /r 
VFNMADD132SS xmm1, xmm2, 
xmm3/m32A V/V FMA Multiply scalar single-precision floating-point value from 
xmm1 and xmm3/m32, negate the multiplica tion result 
VEX.LIG.66.0F38.W0 AD /r 
VFNMADD213SS xmm1, xmm2, 
xmm1 and xmm2, negate the multiplication result and 
add to xmm3/m32 and put result in xmm1.
VEX.LIG.66.0F38.W0 BD /r 
VFNMADD231SS xmm1, xmm2, xmm3/m32A V/V FMA Multiply scalar single-precision floating-point value from 
xmm2 and xmm3/m32, negate the multiplica tion result 
EVEX.LLIG.66.0F38.W0 9D /r 
VFNMADD132SS xmm1 {k1}{z}, 
xmm2, xmm3/m32{er}B V/V AVX512F Multiply scalar single-precision floating-point value from 
EVEX.LLIG.66.0F38.W0 AD /r 
VFNMADD213SS xmm1 {k1}{z}, 
EVEX.LLIG.66.0F38.W0 BD /r 
VFNMADD231SS xmm1 {k1}{z}, 

B Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fuse d Negative Multiply-Add of Scalar Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-308 Vol. 2CEVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
column.
Operation
VFNMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
FI;
THEN DEST[31:0] := RoundFPControl(-(DEST[31:0]*SRC3[31:0]) + SRC2[31:0])ELSE 
FI;
VFNMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(-(SRC2[31:0]*DEST[31:0]) + SRC3[31:0])ELSE 
FI;
FI;DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multip ly-Add of Scalar Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-309VFNMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(-(S RC2[31:0]*SRC3[63:0]) + DEST[31:0])
ELSE 
FI;
VFNMADD132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) + SRC2[31:0])
DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFNMADD213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) + SRC3[31:0])DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFNMADD231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) + DEST[31:0])
VFNMADDxxxSS __m128 _mm_fnmadd_round_ss( __m128 a, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_mask_fnmadd_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);VFNMADDxxxSS __m128 _mm_maskz_fnmadd_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);VFNMADDxxxSS __m128 _mm_mask3_fnmadd_ss(__m128  a, __m128 b, __m128 c, __mmask8 k);
VFNMADDxxxSS __m128 _mm_mask_fnmadd_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_maskz_fnmadd_round_ss(__mma sk8 k, __m128 a, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_mask3_fnmadd_round_ss(__m128  a, __m128 b, __m128 c, __mmask8 k, int r);
VFNMADDxxxSS __m128 _mm_fnmadd_ss (__m128 a, __m128 b, __m128 c);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fu sed Negative Multiply-Subtract of Packed Double Precision Floating-PointINSTRUCTION SET REFERENCE, V
5-310 Vol. 2CVFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD— Fused Negative Multiply-Subtract of 
Packed Double Precisio n Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W1 9E /r
VFNMSUB132PD xmm1, xmm2, 
and subtract xmm2 and put result in xmm1.
VEX.128.66.0F38.W1 AE /r
VFNMSUB213PD xmm1, xmm2, 
subtract xmm3/mem and put result in xmm1.
VEX.128.66.0F38.W1 BE /r 
VFNMSUB231PD xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed double precision floating-point values from 
xmm2 and xmm3/mem, negate the multiplication result and subtract xmm1 and put result in xmm1.
VEX.256.66.0F38.W1 9E /r
VFNMSUB132PD ymm1, ymm2, 
subtract ymm2 and pu t result in ymm1.
VEX.256.66.0F38.W1 AE /r 
VFNMSUB213PD ymm1, ymm2, 
ymm1 and ymm2, negate the multiplication result and 
subtract ymm3/mem and put result in ymm1.
VEX.256.66.0F38.W1 BE /r 
VFNMSUB231PD ymm1, ymm2, 
subtract ymm1 and pu t result in ymm1.
EVEX.128.66.0F38.W1 9E /r 
VFNMSUB132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
xmm1 and xmm3/m128/m64bcst, negate the multiplication result and subt ract xmm2 and put result in 
xmm1.
EVEX.128.66.0F38.W1 AE /r
VFNMSUB213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstBV / V A V X 5 1 2 V L
xmm1 and xmm2, negate the multiplication result and subtract xmm3/m128/m64bcst and put result in xmm1.
EVEX.128.66.0F38.W1 BE /r 
VFNMSUB231PD xmm1 {k1}{z}, 
multiplication result and subt ract xmm1 and put result in 
xmm1.
EVEX.256.66.0F38.W1 9E /r 
VFNMSUB132PD ymm1 {k1}{z}, 
ymm1 and ymm3/m256/m64bcst, negate the 
multiplication result and subt ract ymm2 and put result in 
ymm1.
EVEX.256.66.0F38.W1 AE /r 
VFNMSUB213PD ymm1 {k1}{z}, 
subtract ymm3/m256/m64bcst and put result in ymm1.
EVEX.256.66.0F38.W1 BE /r 
VFNMSUB231PD ymm1 {k1}{z}, 
ymm2 and ymm3/m256/m64bcst, negate the 
multiplication result and subt ract ymm1 and put result in 
ymm1.VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fuse d Negative Multiply-Subtract of Packed Double Precision Floating-Point INSTRUCTION SET REFERENCE, V
Vol. 2C 5-311Instruction Operand Encoding
VFNMSUB132PD: Multiplies the two, four  or eight packed double precision floating-point values from the first 
source operand to the two, four or eight packed double pr ecision floating-point values in the third source operand. 
From negated infinite precision intermediate results, su btracts the two, four or eight packed double precision 
floating-point values in the second source operand, perfor ms rounding and stores the resulting two, four or eight 
packed double precision floating-point values to the destination operand (first source operand).
VFNMSUB213PD: Multiplies the two, four  or eight packed double precision floating-point values from the second 
floating-point values in the third source operand, perfor ms rounding and stores the resulting two, four or eight 
VFNMSUB231PD: Multiplies the two, four  or eight packed double precision floating-point values from the second 
source to the two, four or eight packed double precision floating-point values in the third source operand. From

source to the two, four or eight packed double precision floating-point values in the third source operand. From 
negated infinite precision intermediate results, subtracts the two, four or eight packed double precision floating-
point values in the first source operand, performs round ing and stores the resulting two, four or eight packed 
Operation
rounding).EVEX.512.66.0F38.W1 9E /r 
VFNMSUB132PD zmm1 {k1}{z}, 
result and subtract zmm2 and put result in zmm1.
EVEX.512.66.0F38.W1 AE /r 
VFNMSUB213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}B V/V AVX512F Multiply packed double precision floating-point values from 
zmm1 and zmm2, negate the multiplication result and subtract zmm3/m512/m64bcst and put result in zmm1.
EVEX.512.66.0F38.W1 BE /r 
VFNMSUB231PD zmm1 {k1}{z}, 
result and subtract zmm1 and put result in zmm1.
B Full ModRM:reg (r, w) EVEX .vvvv (r) ModRM:r/m (r) N/AOpcode/
En64/32 
Bit Mode 
Feature 
FlagDescriptionVFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fu sed Negative Multiply-Subtract of Packed Double Precision Floating-PointINSTRUCTION SET REFERENCE, V
5-312 Vol. 2CVFNMSUB132PD DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR( - (D EST[n+63:n]*SRC3[n+63:n]) - SRC2[n+63:n])
FI
VFNMSUB213PD DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR( - (S RC2[n+63:n]*DEST[n+63:n]) - SRC3[n+63:n])
FI
VFNMSUB231PD DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 64*i;DEST[n+63:n] := RoundFPControl_MXCSR( - (SRC2[n+63:n]*SRC3[n+63:n]) - DEST[n+63:n])
FIVFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fuse d Negative Multiply-Subtract of Packed Double Precision Floating-Point INSTRUCTION SET REFERENCE, V
Vol. 2C 5-313VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 op erand is a register)
THEN
ELSE 
RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])
ELSE 
FI
FI;
VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operan d is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) - SRC2[i+63:i])
ELSE 
RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fu sed Negative Multiply-Subtract of Packed Double Precision Floating-PointINSTRUCTION SET REFERENCE, V
5-314 Vol. 2CVFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 op erand is a register)
THEN
ELSE 
RoundFPControl(-(SRC2[i+63:i]*D EST[i+63:i]) - SRC3[i+63:i])
ELSE 
FI
FI;
VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[63:0])
ELSE 
RoundFPControl_MXCSR(-(SRC2[i+63: i]*DEST[i+63:i]) - SRC3[i+63:i])
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fuse d Negative Multiply-Subtract of Packed Double Precision Floating-Point INSTRUCTION SET REFERENCE, V
Vol. 2C 5-315VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 op erand is a register)
THEN
ELSE 
RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])
ELSE 
FI
FI;
VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operan d is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) - DEST[i+63:i])
ELSE 
RoundFPControl_MXCSR(-(SRC2[i+63:i] *SRC3[i+63:i]) - DEST[i+63:i])
FI;
ELSE 
FI
FI;
5-316 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxPD __m512d _mm512_fnmsub_pd(__m512d a, __m512d b, __m512d c);
VFNMSUBxxxPD __m512d _mm512_fnmsub_round_pd(__ m512d a, __m512d b, __m512d c, int r);
VFNMSUBxxxPD __m512d _mm512_mask_fnmsub_pd(__m5 12d a, __mmask8 k, __m512d b, __m512d c);
VFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);VFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_pd(__m512 d a, __m512d b, __m512d c, __mmask8 k);
VFNMSUBxxxPD __m512d _mm512_mask_fnmsub_round_pd(__m51 2d a, __mmask8 k, __m512d b, __m512d c, int r);
VFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);VFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_round_pd(__m5 12d a, __m512d b, __m512d c, __mmask8 k, int r);
VFNMSUBxxxPD __m256d _mm256_mask_fnmsub_pd(__m2 56d a, __mmask8 k, __m256d b, __m256d c);
VFNMSUBxxxPD __m256d _mm256_maskz_fnmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);VFNMSUBxxxPD __m256d _mm256_mask3_fnmsub_pd(__m256 d a, __m256d b, __m256d c, __mmask8 k);
VFNMSUBxxxPD __m128d _mm_mask_fnmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);VFNMSUBxxxPD __m128d _mm_maskz_fnmsub_pd(__mma sk8 k, __m128d a, __m128d b, __m128d c);

VFNMSUBxxxPD __m128d _mm_mask3_fnmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);VFNMSUBxxxPD __m128d _mm_fnmsub_pd (__m128d a, __m128d b, __m128d c);VFNMSUBxxxPD __m256d _mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply -Subtract of Packed Single Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
Vol. 2C 5-317VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS— Fused Negative Multiply-Subtract of 
Packed Single Precision Floating-Point Values
Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W0 9E /r
VFNMSUB132PS xmm1, xmm2, 
xmm3/m128A V/V FMA Multiply packed single-precision floating-point values from 
subtract xmm2 and put result in xmm1.
VEX.128.66.0F38.W0 AE /r 
VFNMSUB213PS xmm1, xmm2, 
xmm3/m128 A V/V FMA Multiply packed single-precision floating-point values from 
VEX.128.66.0F38.W0 BE /r 
VFNMSUB231PS xmm1, xmm2, xmm3/m128A V/V FMA Multiply packed single-precision floating-point values from 
subtract xmm1 and put result in xmm1.
VEX.256.66.0F38.W0 9E /r 
VFNMSUB132PS ymm1, ymm2, 
ymm3/m256A V/V FMA Multiply packed single-precision floating-point values from 
ymm1 and ymm3/mem, negate the multiplication result and 
subtract ymm2 and put result in ymm1.
VEX.256.66.0F38.W0 AE /r 
VFNMSUB213PS ymm1, ymm2, 
VEX.256.66.0F38.0 BE /r 
VFNMSUB231PS ymm1, ymm2, 
ymm2 and ymm3/mem, negate the multiplication result and 
subtract ymm1 and put result in ymm1.
EVEX.128.66.0F38.W0 9E /r 
VFNMSUB132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstBV / V A V X 5 1 2 V L
AVX512FMultiply packed sing le-precision floating-point values from 
xmm1 and xmm3/m128/m32bcst, negate the multiplication result and subtract xmm2 and put result in xmm1.
EVEX.128.66.0F38.W0 AE /r
VFNMSUB213PS xmm1 {k1}{z}, 
subtract xmm3/m128/m32bcst and put result in xmm1.
EVEX.128.66.0F38.W0 BE /r 
VFNMSUB231PS xmm1 {k1}{z}, 
xmm2 and xmm3/m128/m32bcst, negate the multiplication 
result subtract add to xmm1 and put result in xmm1.
EVEX.256.66.0F38.W0 9E /r 
VFNMSUB132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstBV / V A V X 5 1 2 V L
ymm1 and ymm3/m256/m32bcst, negate the multiplication result and subtract ymm2 and put result in ymm1.
EVEX.256.66.0F38.W0 AE /r
VFNMSUB213PS ymm1 {k1}{z}, 
subtract ymm3/m256/m32bcst and put result in ymm1.
EVEX.256.66.0F38.W0 BE /r 
VFNMSUB231PS ymm1 {k1}{z}, 
result subtract add to ymm1 and put result in ymm1.
EVEX.512.66.0F38.W0 9E /r 
VFNMSUB132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}B V/V AVX512F Multiply packed single-precision floating-point values from 
zmm1 and zmm3/m512/m32bcst, negate the multiplication result and subtract zmm2 and put result in zmm1.
EVEX.512.66.0F38.W0 AE /r 
VFNMSUB213PS zmm1 {k1}{z}, 
zmm2, zmm3/m512/m32bcst{er}B V/V AVX512F Multiply packed single-precision floating-point values from 
zmm1 and zmm2, negate the multiplication result and 
subtract zmm3/m512/m32bcst and put result in zmm1.
EVEX.512.66.0F38.W0 BE /r 
VFNMSUB231PS zmm1 {k1}{z}, 
result subtract add to zmm1 and put result in zmm1.VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fuse d Negative Multiply-Subtract of Packed  Single Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
5-318 Vol. 2CInstruction Operand Encoding
VFNMSUB132PS: Multiplies the four, eight or sixteen packed  single-precision floating-point values from the first 
source operand to the four, eight or sixteen packed sing le-precision floating-point values in the third source 
operand. From negated infinite precision intermediate resu lts, subtracts the four, eight or sixteen packed single-
precision floating-point values in the second source operan d, performs rounding and stores the resulting four, eight 
or sixteen packed single-precision floating-point valu es to the destination operand (first source operand).
VFNMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second 
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source 
precision floating-point values in the third source operan d, performs rounding and stores the resulting four, eight 
VFNMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second 
source to the four, eight or sixteen packed single-precision  floating-point values in the third source operand. From 
negated infinite precision intermediate results, subtracts th e four, eight or sixteen packed single-precision floating-
point values in the first source operand, performs roundi ng and stores the resulting four, eight or sixteen packed 
single-precision floating-point values to the destination operand (first source operand).
Operation
VFNMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR( - (D EST[n+31:n]*SRC3[n+31:n]) - SRC2[n+31:n])
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply -Subtract of Packed Single Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
Vol. 2C 5-319VFNMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR( - (SRC2[n+31:n]*DEST[n+31:n]) - SRC3[n+31:n])
FI
VFNMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)
MAXNUM := 2
MAXNUM := 4
n := 32*i;DEST[n+31:n] := RoundFPControl_MXCSR( - (SRC2[n+31:n]*SRC3[n+31:n]) - DEST[n+31:n])
FI

MAXNUM := 2
MAXNUM := 4
FI
MAXNUM := 2
MAXNUM := 4
FI
VFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fuse d Negative Multiply-Subtract of Packed  Single Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
5-320 Vol. 2CVFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) - SRC2[i+31:i])
ELSE 
RoundFPControl_MXCSR(-(DEST[i+31: i]*SRC3[i+31:i]) - SRC2[i+31:i])
FI;
ELSE 
FI
FI;
VFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl_MXCSR(-(SRC2[i+31: i]*DEST[i+31:i]) - SRC3[i+31:i])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply -Subtract of Packed Single Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
Vol. 2C 5-321VFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(SRC2[i+31: i]*DEST[i+31:i]) - SRC3[31:0])
ELSE 
FI;
ELSE 
FI
FI;
VFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded ve rsion, when src3 operand is a register)
THEN
ELSE 
RoundFPControl_MXCSR(-(SRC2[i+31:i] *SRC3[i+31:i]) - DEST[i+31:i])
ELSE 
FI
FI;
5-322 Vol. 2CVFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded vers ion, when src3 operand is a memory source)
THEN 
THEN
RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) - DEST[i+31:i])
ELSE 
FI;
ELSE 
FI
FI;
VFNMSUBxxxPS __m512 _mm512_fnmsub_ps(__m512 a, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_fnmsub_round_ps( __m512 a, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_mask_fnmsub_ps(__m5 12 a, __mmask16 k, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_maskz_fnmsub_ps(__ mmask16 k, __m512 a, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_mask3_fnmsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);VFNMSUBxxxPS __m512 _mm512_mask_fnmsub_round_ps(__m 512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_maskz_fnmsub_round_ps(__mmask 16 k, __m512 a, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_mask3_fnmsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);VFNMSUBxxxPS __m256 _mm256_mask_fnmsub_ps(__m 256 a, __mmask8 k, __m256 b, __m256 c);
VFNMSUBxxxPS __m256 _mm256_maskz_fnmsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);VFNMSUBxxxPS __m256 _mm256_mask3_fnmsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);VFNMSUBxxxPS __m128 _mm_mask_fnmsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);VFNMSUBxxxPS __m128 _mm_maskz_fnmsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);VFNMSUBxxxPS __m128 _mm_mask3_fnmsub_ps(__m 128 a, __m128 b, __m128 c, __mmask8 k);
VFNMSUBxxxPS __m128 _mm_fnmsub_ps (__m128 a, __m128 b, __m128 c);VFNMSUBxxxPS __m256 _mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply -Subtract of Scalar Double Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
Vol. 2C 5-323VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD— Fused Negative Multiply-Subtract of 
Scalar Double Precision Floating-Point Values
VFNMSUB132SD: Multiplies the low packed double precision floating-point value from the first source operand to 
the low packed double precision floating-point value in th e third source operand. From negated infinite precision 
intermediate result, subtracts the low double precision floa ting-point value in the second source operand, performs 
VFNMSUB213SD: Multiplies the low packed double precisio n floating-point value from the second source operand 
to the low packed double precision floating-point value in the first source operand. From negated infinite precision 
intermediate result, subtracts the low double precision floa ting-point value in the third source operand, performs 
VFNMSUB231SD: Multiplies the low packed double precision fl oating-point value from the second source to the low 
packed double precision floating-point value in the third source operand. From negated infinite precision interme-
diate result, subtracts the low double precision floating-poi nt value in the first source operand, performs rounding 
and stores the resulting packed double precision floating -point value to the destination operand (first source 
operand).
En64/32 
Bit Mode 
Feature 
VEX.LIG.66.0F38.W1 9F /r 
VFNMSUB132SD xmm1, xmm2, 
VEX.LIG.66.0F38.W1 AF /r 
VFNMSUB213SD xmm1, xmm2, 
VEX.LIG.66.0F38.W1 BF /r 
VFNMSUB231SD xmm1, xmm2, xmm3/m64A V/V FMA Multiply scalar double precision floating-point value from 
EVEX.LLIG.66.0F38.W1 9F /r 
VFNMSUB132SD xmm1 {k1}{z}, 
xmm2, xmm3/m64{er}B V/V AVX512F Multiply scalar double pr ecision floating-point value from 
EVEX.LLIG.66.0F38.W1 AF /r 
VFNMSUB213SD xmm1 {k1}{z}, 
xmm2, xmm3/m64{er} B V/V AVX512F Multiply scalar double pr ecision floating-point value from 
subtract xmm3/m64 and put result in xmm1.
EVEX.LLIG.66.0F38.W1 BF /r 
VFNMSUB231SD xmm1 {k1}{z}, 
xmm2, xmm3/m64{er}B V/V AVX512F Multiply scalar double pr ecision floating-point value from

B Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFNMSUB132SD/VFNMSUB213SD/VFNMSU B231SD—Fused Negative Multiply-Subtract of Sc alar Double Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
5-324 Vol. 2CEVEX encoded version: The low quadword element of th e destination is updated according to the writemask.
column.
Operation
VFNMSUB132SD DEST, SRC2, SR C3 (EVEX encoded version)
THEN
ELSE 
FI;
THEN DEST[63:0] := RoundFPControl(-(DEST[63:0]*SRC3[63:0]) - SRC2[63:0])ELSE 
FI;
VFNMSUB213SD DEST, SRC2, SR C3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(-(SRC2[63:0]*DEST[63:0]) - SRC3[63:0])ELSE 
FI;
FI;DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply -Subtract of Scalar Double Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
Vol. 2C 5-325VFNMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[63:0] := RoundFPControl(-(S RC2[63:0]*SRC3[63: 0]) - DEST[63:0])
ELSE 
FI;
VFNMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) - SRC2[63:0])
VFNMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) - SRC3[63:0])DEST[127:64] := DEST[127:64]DEST[MAXVL-1:128] := 0
VFNMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] := RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) - DEST[63:0])
VFNMSUBxxxSD __m128d _mm_fnmsub_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_mask_fnmsub_sd(__m12 8d a, __mmask8 k, __m128d b, __m128d c);
VFNMSUBxxxSD __m128d _mm_maskz_fnmsub_sd(__mma sk8 k, __m128d a, __m128d b, __m128d c);
VFNMSUBxxxSD __m128d _mm_mask3_fnmsub_sd(__m1 28d a, __m128d b, __m128d c, __mmask8 k);
VFNMSUBxxxSD __m128d _mm_mask_fnmsub_round_sd(__m128d  a, __mmask8 k, __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_maskz_fnms ub_round_sd(__mmask8 k, __m128d a,  __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_mask3_fnmsub_round_sd(__m128d a, __m128d b, __m128d c,  __mmask8 k, int r);
VFNMSUBxxxSD __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”VFNMSUB132SS/VFNMSUB213SS/VFNMSU B231SS—Fused Negative Multiply-Subtract of Sc alar Single Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
5-326 Vol. 2CVFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS— Fused Negative Multiply-Subtract of 
Scalar Single Precision Floating-Point Values
VFNMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to 
the low packed single-precision floating-point value in th e third source operand. From negated infinite precision 
intermediate result, the low si ngle-precision floating-point value in the second source operand, performs rounding 
and stores the resulting packed single-precision floating -point value to the destination operand (first source 
operand).
VFNMSUB213SS: Multiplies the low packed single-precision floating-point value from th e second source operand to 
the low packed single-precision floating-point value in th e first source operand. From negated infinite precision 
intermediate result, the low single-precision floating-poi nt value in the third source operand, performs rounding 
operand).
VFNMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low 
packed single-precision floating-point value in the third source operand. From negated infinite precision interme-
diate result, the low single-precision floating-point value in the first source operand, performs rounding and stores 
the resulting packed single-precision floating-point va lue to the destination operand (first source operand).
opcode/instruction column of the summary table. The be havior of the complementary mnemonic in situations Opcode/
En64/32 
Bit Mode 
Feature 
VEX.LIG.66.0F38.W0 9F /r 
VFNMSUB132SS xmm1, xmm2, 
xmm1 and xmm3/m32, negate th e multiplication result and 
VEX.LIG.66.0F38.W0 AF /r 
VFNMSUB213SS xmm1, xmm2, 
subtract xmm3/m32 and put result in xmm1.
VEX.LIG.66.0F38.W0 BF /r 
VFNMSUB231SS xmm1, xmm2, xmm3/m32A V/V FMA Multiply scalar single-precision floating-point value from 
xmm2 and xmm3/m32, negate th e multiplication result and 
EVEX.LLIG.66.0F38.W0 9F /r 
VFNMSUB132SS xmm1 {k1}{z}, 
EVEX.LLIG.66.0F38.W0 AF /r 
VFNMSUB213SS xmm1 {k1}{z}, 
xmm2, xmm3/m32{er} B V/V AVX512F Multiply scalar single-precision floating-point value from 
EVEX.LLIG.66.0F38.W0 BF /r 
VFNMSUB231SS xmm1 {k1}{z}, 
B Tuple1 Scalar ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply -Subtract of Scalar Single Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
Vol. 2C 5-327involving NANs are governed by the de finition of the instruction mnemonic defined in the opcode/instruction 
column.
Operation
VFNMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(-(D EST[31:0]*SRC3[31:0]) - SRC2[31:0])
ELSE 

column.
Operation
THEN
ELSE 
ELSE 
FI;
VFNMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(-(S RC2[31:0]*DEST[31:0]) - SRC3[31:0])
ELSE 
FI;
FI;DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0VFNMSUB132SS/VFNMSUB213SS/VFNMSU B231SS—Fused Negative Multiply-Subtract of Sc alar Single Precision Floating-Point Val-INSTRUCTION SET REFERENCE, V
5-328 Vol. 2CVFNMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) - DEST[31:0])ELSE 
FI;
VFNMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) - SRC2[31:0])DEST[127:32] := DEST[127:32]DEST[MAXVL-1:128] := 0
VFNMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) - SRC3[31:0])
VFNMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] := RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) - DEST[31:0])
VFNMSUBxxxSS __m128 _mm_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFNMSUBxxxSS __m128 _mm_mask_fnmsub_ss(__m128  a, __mmask8 k, __m128 b, __m128 c);
VFNMSUBxxxSS __m128 _mm_maskz_fnmsub_ss(__m mask8 k, __m128 a, __m128 b, __m128 c);
VFNMSUBxxxSS __m128 _mm_mask3_fnmsub_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);VFNMSUBxxxSS __m128 _mm_mask_fnmsub_round_ss(__m1 28 a, __mmask8 k, __m128 b, __m128 c, int r);
VFNMSUBxxxSS __m128 _mm_maskz_fnmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);VFNMSUBxxxSS __m128 _mm_mask3_fnmsub_round_ss(__m 128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFNMSUBxxxSS __m128 _mm_fnmsub_ss (__m128 a, __m128 b, __m128 c);
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VFPCLASSPD—Tests Types of Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-329VFPCLASSPD—Tests Types of Packed Float64 Values
The FPCLASSPD instruction checks the packed double precision floating-point values for special categories, speci-
fied by the set bits in the imm8 byte. Each set bit in i mm8 specifies a category of floating-point values that the 
input data element is classified against. The classified resu lts of all specified categories of an input value are ORed 
together to form the final boolean result for the input elem ent. The result of each element is written to the corre-
sponding bit in a mask register k2 according to the writemask k1. Bits [ MAX_KL -1:8/4/2] of the destination are 
cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category 
is listed in Table 5-14.
broadcasted from a 64-bit memory location.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F3A.W1 66 /r ib
VFPCLASSPD k2 {k1}, 
xmm2/m128/m64bcst, imm8AV / V A V X 5 1 2 V L
AVX512DQTests the input for the followi ng categories:  NaN, +0, -0, 
+Infinity, -Infinity, denormal, finite negative. The immediate 
field provides a mask bit for each of these category tests. 
The masked test results are OR -ed together to form a mask 
result.
EVEX.256.66.0F3A.W1 66 /r ib
ymm2/m256/m64bcst, imm8AV / V A V X 5 1 2 V L
result.
EVEX.512.66.0F3A.W1 66 /r ib
zmm2/m512/m64bcst, imm8A V/V AVX512DQ Tests the in put for the following ca tegories:  NaN, +0, -0, 
result.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Figure 5-13.  Imm8 Byte Specifier of Special Ca se Floating-Point Values  for VFPCLASSPD/SD/PS/SS
Table 5-14. Classifier Operations for VFPCLASSPD/SD/PS/SS
Bits Imm8[0] Imm8[1] Imm8[2] Imm8[3] Imm8[4] Imm8[5] Imm8[6] Imm8[7]
Category QNAN PosZero NegZero PosINF NegINF Denormal Negative SNAN
Classifier Checks for 
QNaNChecks for 
+0Checks for -
0Checks for 
+INFChecks for -
INFChecks for 
DenormalChecks for 
Negative finiteChecks for 
SNaN7 0 2 4 6 531
QNaN SNaN Neg. Finite Denormal Neg. INF +INF Neg. 0 +0VFPCLASSPD—Tests Types of Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
5-330 Vol. 2CEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
CheckFPClassDP (tsrc[63:0], imm8[7:0]){
//* Start checking the source operand for special type *//
NegNum  := tsrc[63];
IF (tsrc[62:52]=07FFh) Then ExpAllOnes := 1; FI;
IF (tsrc[62:52]=0h) Then ExpAllZeros := 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then 
MantAllZeros := 1;
ELSIF ( tsrc[51:0]=0h) Then
FI;ZeroNumber := ExpAllZeros AND MantAllZeros
SignalingBit := 
tsrc[51];
sNaN_res := ExpAllOnes AND NOT(MantA llZeros) AND NOT(SignalingBit); // sNaN
qNaN_res := ExpAllOnes AND NOT(Ma ntAllZeros) AND SignalingBit; // qNaN
Pzero_res := NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0Nzero_res := NegNum AND ExpA llZeros AND MantAllZeros; // -0
PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +InfNInf_res := NegNum AND ExpA llOnes AND MantA llZeros; // -Inf
Denorm_res := ExpAllZeros AND NOT(MantAllZeros); // denormFinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR  ( imm8[7] AND sNaN_res );
Return bResult;
} //* end of CheckFPClassDP() *//
VFPCLASSPD (EVEX Encoded versions)
THEN 
IF (EVEX.b == 1) AND (SRC *is memory*)
THEN
DEST[j] := CheckFPClassDP( SRC1[63:0], imm8[7:0]);
ELSE 
DEST[j] := CheckFPClassDP( SRC1[i+63:i], imm8[7:0]);
FI;
FI;
ENDFORDEST[MAX_KL-1:KL] := 0VFPCLASSPD—Tests Types of Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-331Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSPD __mmask8 _mm512_fpclass_pd_mask( __m512d a, int c);
VFPCLASSPD __mmask8 _mm512_mask_fpclass_pd _mask( __mmask8 m, __m512d a, int c)
VFPCLASSPD __mmask8 _mm256_fpclass_pd_mask( __m256d a, int c)VFPCLASSPD __mmask8 _mm256_mask_fpclass_pd _mask( __mmask8 m, __m256d a, int c)
VFPCLASSPD __mmask8 _mm_fpclass_pd_mask( __m128d a, int c)VFPCLASSPD __mmask8 _mm_mask_fpclass_pd_ mask( __mmask8 m, __m128d a, int c)
None.
See Table 2-49, “Type E4 Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B.VFPCLASSPH—Test Types of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-332 Vol. 2CVFPCLASSPH—Test Types of Packed FP16 Values
This instruction checks the packed FP16 values in the so urce operand for special categories, specified by the set 
bits in the imm8 byte. Each set bit in imm8 specifies a cate gory of floating-point values that the input data element 
is classified against; see Table 5-9 for the categories. The classified results of all specified categories of an input 
value are ORed together to form the final boolean result for the input element. The result is written to the corre-
sponding bits in the destination mask register according to the writemask.Opcode/
En64/32 
Bit Mode 
EVEX.128.NP.0F3A.W0 66 /r /ib
VFPCLASSPH  k1{k2},  xmm1/m128/
m16bcst,  imm8A V/V AVX512-FP16 
AVX512VLTest the input for the fo llowing categories:  NaN,

En64/32 
Bit Mode 
AVX512VLTest the input for the fo llowing categories:  NaN, 
+0, -0, +Infinity, -Infinity, denormal, finite 
negative. The immediate field provides a mask 
bit for each of these cate gory tests. The masked 
test results are OR-ed to gether to form a mask 
result.
EVEX.256.NP.0F3A.W0 66 /r /ib
VFPCLASSPH  k1{k2},  ymm1/m256/
+0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask 
result.
EVEX.512.NP.0F3A.W0 66 /r /ib
VFPCLASSPH  k1{k2},  zmm1/m512/
m16bcst,  imm8A V/V AVX512-FP16 Test the input for the following ca tegories:  NaN, 
result.
A Full ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/A
Table 5-9.  Classifier Operations for VFPCLASSPH/VFPCLASSSH
Bits Category Classifier
imm8[0] QNAN Checks for QNANimm8[1] PosZero Checks +0
imm8[2] NegZero Checks for -0
imm8[3] PosINF Checks for +∞
imm8[4] NegINF Checks for −∞
imm8[5] Denormal Checks for Denormal
imm8[6] Negative Checks for Negative finiteimm8[7] SNAN Checks for SNANVFPCLASSPH—Test Types of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-333Operation
def check_fp_class_fp16(tsrc, imm8):
negative := tsrc[15]exponent_all_ones := (tsrc[14:10] == 0x1F)exponent_all_zeros :=  (tsrc[14:10] == 0)
mantissa_all_zeros := (tsrc[9:0] == 0)zero := exponent_all_zeros and mantissa_all_zerossignaling_bit := tsrc[9]
snan := exponent_all_ones and not(mantissa_all_zeros) and not(signaling_bit)
qnan := exponent_all_ones and not(mantissa_all_zeros) and signaling_bitpositive_zero := no t(negative) and zero
negative_zero := negative and zeropositive_infinity := not(negative) and exponent_all_ones and mantissa_all_zerosnegative_infinity := negative and exponent_all_ones and mantissa_all_zerosdenormal := exponent_all_zeros and not(mantissa_all_zeros)finite_negative := negative and not(exponent_all_ones) and not(zero)
return (imm8[0] and qnan) OR
(imm8[1] and positive_zero) OR(imm8[2] and negative_zero) OR(imm8[3] and positive_infinity) OR(imm8[4] and negative_infinity) OR(imm8[5] and denormal) OR(imm8[6] and finite_negative) OR(imm8[7] and snan)
VFPCLASSPH dest{k2}, src, imm8
IF k2[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
ELSE:
tsrc := SRC.fp16[i]
DEST.bit[i] := check_fp _class_fp16(tsrc, imm8)
ELSE:
DEST.bit[i] := 0
DEST[MAXKL-1:kl] := 0
VFPCLASSPH __mmask8 _mm_fpclass_ph _mask (__m128h a, int imm8);
VFPCLASSPH __mmask8 _mm_mask_fpclass_ph_ma sk (__mmask8 k1, __m128h a, int imm8);
VFPCLASSPH __mmask16 _mm256_fpclass_ph_mask (__m256h a, int imm8);VFPCLASSPH __mmask16 _mm256_mask_fpclass_ph _mask (__mmask16 k1, __m256h a, int imm8);
VFPCLASSPH __mmask32 _mm512_fpclass_ph_mask (__m512h a, int imm8);VFPCLASSPH __mmask32 _mm512_mask_fpclass_ph _mask (__mmask32 k1, __m512h a, int imm8);
None.VFPCLASSPH—Test Types of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-334 Vol. 2COther Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E4 Class Exception Conditions.”VFPCLASSPS—Tests Types of Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-335VFPCLASSPS—Tests Types of Packed Float32 Values
The FPCLASSPS instruction checks the packed single-precisi on floating-point values for special categories, speci-
sponding bit in a mask register k2 according to the writemask k1. Bits [ MAX_KL -1:16/8/4] of the destination are 
cleared.
broadcasted from a 32-bit memory location.
Operation
CheckFPClassSP (tsrc[31:0], imm8[7:0]){
NegNum  := tsrc[31];
IF (tsrc[30:23]=0FFh) Then Ex pAllOnes := 1; FI;
IF (tsrc[30:23]=0h) Then ExpAllZeros := 1;
ELSIF ( tsrc[22:0]=0h) Then
FI;ZeroNumber= ExpAllZer os AND MantAllZeros
SignalingBit= 
tsrc[22];
sNaN_res := ExpAllOnes AN D NOT(MantAllZeros) AND NO T(SignalingBit); // sNaN
qNaN_res := ExpAllOnes AND NOT(Mant AllZeros) AND SignalingBit; // qNaN
Pzero_res := NOT(NegNum) AND ExpA llZeros AND MantAllZeros; // +0Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F3A.W0 66 /r ib
VFPCLASSPS k2 {k1}, 
xmm2/m128/m32bcst, imm8A V/V AVX512VL
field provides a mask bit for each of these category tests. The 
masked test results are OR-ed to gether to form a mask result.
EVEX.256.66.0F3A.W0 66 /r ib
ymm2/m256/m32bcst, imm8A V/V AVX512VL
EVEX.512.66.0F3A.W0 66 /r ib
zmm2/m512/m32bcst, imm8A V/V AVX512DQ Tests the input for the following categories:  NaN, +0, -0, 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVFPCLASSPS—Tests Types of Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
5-336 Vol. 2CNzero_res := NegNum AND ExpA llZeros AND MantAllZeros; // -0
} //* end of CheckSPClassSP() *//
VFPCLASSPS (EVEX encoded versions)
THEN 
THEN
DEST[j] := CheckFPClassDP( SRC1[31:0], imm8[7:0]);
ELSE 
DEST[j] := CheckFPClassDP( SRC1[i+31:i], imm8[7:0]);
FI;
ELSE  DEST[j] := 0 ;  zeroing-masking only
FI;
VFPCLASSPS __mmask16 _mm512_fpc lass_ps_mask( __m512 a, int c);
VFPCLASSPS __mmask16 _mm512_mask_fpclass_ ps_mask( __mmask16 m, __m512 a, int c)
VFPCLASSPS __mmask8 _mm256_fpcla ss_ps_mask( __m256 a, int c)
VFPCLASSPS __mmask8 _mm256_mask_fpclass_ ps_mask( __mmask8 m, __m256 a, int c)
VFPCLASSPS __mmask8 _mm_fpclass_ps_mask( __m128 a, int c)VFPCLASSPS __mmask8 _mm_mask_fpclass_ps _mask( __mmask8 m, __m128 a, int c)
None.
#UD If EVEX.vvvv != 1111B.VFPCLASSSD—Tests Type of a Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-337VFPCLASSSD—Tests Type of a Scalar Float64 Value
The FPCLASSSD instruction checks the low double precision floating-point value in the source operand for special 
categories, specified by the set bits in the imm8 byte. Each  set bit in imm8 specifies a category of floating-point 
values that the input data element is classified against. Th e classified results of all specified categories of an input 
value are ORed together to form the final boolean result fo r the input element. The result is written to the low bit 
in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.

Operation
CheckFPClassDP (tsr c[63:0], imm8[7:0]){
FI;ZeroNumber := ExpAllZeros AND MantAllZerosSignalingBit := 
tsrc[51];
Pzero_res := NOT(NegNum) AND ExpA llZeros AND MantAllZeros; // +0
Nzero_res := NegNum AND ExpA llZeros AND MantAllZeros; // -0
PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +InfNInf_res := NegNum AND ExpAllOnes AND MantAllZeros; // -InfDenorm_res := ExpAllZeros AND NOT(MantAllZeros); // denormFinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite
} //* end of CheckFPClassDP() *//Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W1 67 /r ib
VFPCLASSSD k2 {k1}, 
xmm2/m64, imm8A V/V AVX512DQ Tests the input for the following categories: NaN, +0, -0, 
masked test results are OR-ed to gether to form a mask result. 
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVFPCLASSSD—Tests Type of a Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
5-338 Vol. 2CVFPCLASSSD (EVEX encoded version)
THEN DEST[0] := 
CheckFPClassDP(SRC1[63:0], imm8[7:0])
ELSE  DEST[0] := 0 ;  zeroing-masking only
FI;
DEST[MAX_KL-1:1] := 0
VFPCLASSSD __mmask8 _mm_fpclass_sd_mask( __m128d a, int c)
VFPCLASSSD __mmask8 _mm_mask_fpclass_sd _mask( __mmask8 m, __m128d a, int c)
None.
See Table 2-53, “Type E6 Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B.VFPCLASSSH—Test Types of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-339VFPCLASSSH—Test Types of Scalar FP16 Values
This instruction checks the low FP16 value in the source op erand for special categories, specified by the set bits in 
the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is clas-
sified against; see Table 5-9 for the categories. The classified  results of all specified categories of an input value are 
ORed together to form the final boolean result for the input element. The result is written to the low bit in the desti-
nation mask register according to the writemask. The ot her bits in the destination mask register are zeroed.
Operation
VFPCLASSSH dest{k2}, src, imm8 
IF k2[0] or *no writemask*:
DEST.bit[0] := check_fp _class_fp16(src.fp16[0], imm8) // see VFPCLASSPH
ELSE:
DEST[MAXKL-1:1] := 0 
VFPCLASSSH __mmask8 _mm_fpclass_sh_mask (__m128h a, int imm8);
VFPCLASSSH __mmask8 _mm_mask_fpclass_sh_mas k (__mmask8 k1, __m128h a, int imm8);
None.
EVEX-encoded instructions, see Table 2-58, “Type E10 Class Exception Conditions.”Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.NP.0F3A.W0 67 /r /ib
VFPCLASSSH k1{k2}, xmm1/m16, 
imm8A V/V AVX512-FP16 Test th e input for the followi ng categories:  NaN, 
result.
A Scalar ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/AVFPCLASSSS—Tests Type of a Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
5-340 Vol. 2CVFPCLASSSS—Tests Type of a Scalar Float32 Value
The FPCLASSSS instruction checks the low single-precision floating-point value in the source operand for special 
value are ORed together to form the final boolean result for the input element. The result is written to the low bit in 
a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.
Operation
CheckFPClassSP (tsrc[ 31:0], imm8[7:0]){
tsrc[22];
Return bResult;Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W0 67 /r
VFPCLASSSS k2 {k1}, 
xmm2/m32, imm8A V/V AVX512DQ Tests the input for the following categories: NaN, +0, -0, 
field provides a mask bit for each  of these category tests. The 
masked test results ar e OR-ed together to form a mask result.
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVFPCLASSSS—Tests Type of a Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-341} //* end of CheckSPClassSP() *//
VFPCLASSSS (EVEX encoded version)
CheckFPClassSP(SRC1 [31:0], imm8[7:0])
FI;
VFPCLASSSS __mmask8 _mm_fpclass_ss_mask( __m128 a, int c)
VFPCLASSSS __mmask8 _mm_mask_fpclass_ss_mask( __mmask8 m, __m128 a, int c)
None.
#UD If EVEX.vvvv != 1111B.VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Fl oating-Point Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
5-342 Vol. 2CVGATHERDPD/VGATHERQPD—Gather Packed Double  Precision Floating-Point Values Using 
Signed Dword/Qword Indices 
The instruction conditionally loads up to 2 or 4 double pr ecision floating-point values from memory addresses spec-
ified by the memory operand (the second operand) and using qword indices. The memory operand uses the VSIB 
form of the SIB byte to specify a general purpose register operand as the common base, a vector register for an array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the condit ional load operation from each memory address and the 
corresponding update of each data element of the destinat ion operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of th e mask register. If an element’s mask bit is not set, the 
corresponding element of the destination register is left  unchanged. The width of data element in the destination 
register and mask register are identical. The entire mask re gister will be set to zero by this instruction unless the 
instruction causes an exception. 
Using dword indices in the lower half of  the mask register, the instruction conditionally loads up to 2 or 4 double 
precision floating-point values from the VSIB addressing  memory operand, and updates the destination register.

precision floating-point values from the VSIB addressing  memory operand, and updates the destination register. 
This instruction can be suspended by an exception if at le ast one element is already gathered (i.e., if the exception 
is triggered by an element other than the rightmost one wi th its mask bit set). When this happens, the destination 
register and the mask operand are partia lly updated; those elements that have  been gathered are placed into the 
destination register and have their mask bits set to zero . If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exceptio n; in this case, EFLAG.RF is set to one so an instruction 
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are diff erent, part of the destination register and part of the mask register do not 
correspond to any elements being gathered. This instruction se ts those parts to zero. It may do this to one or both 
of those registers even if the instruction triggers an exce ption, and even if the instru ction triggers the exception 
before gathering any elements.
VEX.128 version: The instruction will gather two double pr ecision floating-point values. For dword indices, only the 
lower two indices in the vector index register are used.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W1 92 /r
VGATHERDPD xmm1, vm32x, xmm2RMV V/V AVX2 Using dword indices specified in vm32x, gather double 
precision floating-point values from memory conditioned on mask specified by xmm2. Conditionally gathered ele-
ments are merged into xmm1.
VEX.128.66.0F38.W1 93 /r
VGATHERQPD xmm1, vm64x, xmm2RMV V/V AVX2 Using qword indices specified in vm64x, gather double 
VEX.256.66.0F38.W1 92 /r
VGATHERDPD ymm1, vm32x, ymm2RMV V/V AVX2 Using dword indices specified in vm32x, gather double 
precision floating-point values from memory conditioned 
on mask specified by ymm2. Conditionally gathered ele-
ments are merged into ymm1.
VEX.256.66.0F38.W1 93 /r
VGATHERQPD ymm1, vm64y, ymm2RMV V/V AVX2 Using qword indices specified in vm64y, gather double 
RMV ModRM:reg (r,w) BaseReg (R): VSIB:base,
VectorReg(R): VSIB:indexVEX.vvvv (r, w) N/AVGATHERDPD/VGATHERQPD—Gather Packed Double Precision Fl oating-Point Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-343VEX.256 version: The instruction will gather four double pr ecision floating-point values. For dword indices, only the 
lower four indices in the vector index register are used.
Note that:
•If any pair of the index, mask, or destination registers are the same, this instruction results a #UD fault.
•The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
•Faults are delivered in a right-to-left manner. That is, if  a fault is triggered by an  element and delivered, all 
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer 
to the MSB may or may not be completed. If a given elem ent triggers multiple faults, they are delivered in the 
conventional order.
•Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to 
the left of a faulting one may be gathered before th e fault is delivered. A given implementation of this 
instruction is repeatable - given the same input values an d architectural state, the same set of elements to the 
left of the faulting one will be gathered.
•This instruction does not perform AC chec ks, and so will never deliver an AC fault.
•This instruction will cause a #UD if the address size attribute is 16-bit.
•This instruction will cause a #UD if the memo ry operand is encoded without the SIB byte.
•This instruction should not be used to access memory mapp ed I/O as the ordering of the individual loads it does 
is implementation specific, and some implementations may use loads larger than the data element size or load 
elements an indeterminate number of times.
•The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
bit mode, if the scale is greater than one). In this case , the most significant bits beyond the number of address 
bits are ignored.
Operation
DEST := SRC1;
BASE_ADDR: base register encoded in VSIB addressing;VINDEX: the vector index register encoded by VSIB addressing;SCALE: scale factor encoded by SIB:[7:6];DISP: optional 1, 4 byte displacement;MASK := SRC3;
VGATHERDPD (VEX.128 version)
MASK[MAXVL-1:128] := 0;FOR j := 0 to 1
i := j * 64;IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFORFOR j := 0 to 1
k := j * 32;i := j * 64;DATA_ADDR := BASE_ADDR + (SignExt end(VINDEX[k+31:k])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;MASK[i +63: i] := 0;
ENDFORDEST[MAXVL-1:128] := 0;VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Fl oating-Point Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
5-344 Vol. 2CVGATHERQPD (VEX.128 version)
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most  significant bit
ELSE
FI;
ENDFORFOR j := 0 to 1 
i := j * 64;DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits this instruction
ENDFORDEST[MAXVL-1:128] := 0;
VGATHERQPD (VEX.256 version)
MASK[MAXVL-1:256] := 0;FOR j := 0 to 3
ELSE
FI;
ENDFORFOR j := 0 to 3
ENDFORDEST[MAXVL-1:256] := 0;
VGATHERDPD (VEX.256 version)
ELSE
FI;
k := j * 32;i := j * 64;DATA_ADDR := BASE_ADDR + (SignExten d(VINDEX1[k+31:k])*SCALE + DISP;VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Fl oating-Point Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-345IF MASK[63+i] THEN
FI;MASK[i +63:i] := 0;
VGATHERDPD: __m128d _mm_i32gather_pd (double const * base, __m128i index, const int scale);
VGATHERDPD: __m128d _mm_mask_i32gather_pd (__m128d src, do uble const * base, __m128i index, __m128d mask, const int 
scale);
VGATHERDPD: __m256d _mm256_i32gather_pd (double const * base, __m128i index, const int scale);
VGATHERDPD: __m256d _mm256_mask_i32gather_pd (__m256d src, double const * base, __m128i index, __m256d mask, const int 
scale);
VGATHERQPD: __m128d _mm_i64gather_pd (double co nst * base, __m128i index, const int scale);
VGATHERQPD: __m128d _mm_mask_i64gather_pd  (__m128d src, double const * base, __m128i index, __m128d mask, const int 
scale);
VGATHERQPD: __m256d _mm256_i64gather_pd (double const * base, __m256i inde x, const int scale);
VGATHERQPD: __m256d _mm256_mask_ i64gather_pd (__m256d src, double const * base, __m256i index, __m256d mask, const int 
scale);
None.
See Table 2-27, “Type 12 Class Exception Conditions.”VGATHERDPS/VGATHERQPS—Gather Packed Single Precision Fl oating-Point Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
5-346 Vol. 2CVGATHERDPS/VGATHERQPS—Gather  Packed Single Precision Floating-Point Values Using 
The instruction conditionally loads up to 4 or 8 single-pre cision floating-point values from memory addresses spec-
ified by the memory operand (the second operand) and using dword indices. The memory operand uses the VSIB 
corresponding element of the destination register is left  unchanged. The width of data element in the destination

Using qword indices, the instruction conditionally loads up to  2 or 4 single-precision floating-point values from the 
VSIB addressing memory operand, and updates the lower half  of the destination register. The upper 128 or 256 bits 
of the destination register ar e zero’ed with qword indices.
before gathering any elements.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.128.66.0F38.W0 92 /r
VGATHERDPS xmm1, vm32x, xmm2A V/V AVX2 Using dword indices specified in vm32x, gather single-
VEX.128.66.0F38.W0 93 /r
VGATHERQPS xmm1, vm64x, xmm2A V/V AVX2 Using qword indices specified in vm64x, gather single-
VEX.256.66.0F38.W0 92 /r
VGATHERDPS ymm1, vm32y, ymm2A V/V AVX2 Using dword indices specified in vm32y, gather single-
VEX.256.66.0F38.W0 93 /r
VGATHERQPS xmm1, vm64y, xmm2A V/V AVX2 Using qword indices specified in vm64y, gather single-
on mask specified by xmm2. Conditionally gathered ele-
A ModRM:reg (r,w) BaseReg (R): VSIB:base,
VectorReg(R): VSIB:indexVEX.vvvv (r, w) N/AVGATHERDPS/VGATHERQPS—Gather Packed Single Precision Fl oating-Point Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-347VEX.128 version: For dword indices, the instruction will gather four single-precision floating-point values. For 
qword indices, the instruction will gather two valu es and zero the upper 64 bits of the destination.
VEX.256 version: For dword indices, the instruction will gather eight single-precision floating-point values. For 
qword indices, the instruction will gather four valu es and zero the upper 128 bits of the destination.
Note that:
•If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer to the MSB may or may not be completed. If a given elem ent triggers multiple faults, they are delivered in the 
Operation
VGATHERDPS (VEX.128 version)
MASK[MAXVL-1:128] := 0;FOR j := 0 to 3
i := j * 32;IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFORFOR j := 0 to 3 
i := j * 32;DATA_ADDR := BASE_ADDR + (SignExt end(VINDEX[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;MASK[i +31:i] := 0;
ENDFORVGATHERDPS/VGATHERQPS—Gather Packed Single Precision Fl oating-Point Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
5-348 Vol. 2CDEST[MAXVL-1:128] := 0;
VGATHERQPS (VEX.128 version)
MASK[MAXVL-1:64] := 0;FOR j := 0 to 3
ELSE
FI;
k := j * 64;i := j * 32;DATA_ADDR := BASE_ADDR + (SignExten d(VINDEX1[k+63:k])*SCALE + DISP;
ENDFORDEST[MAXVL-1:64] := 0;
VGATHERDPS (VEX.256 version)
MASK[MAXVL-1:256] := 0;FOR j := 0 to 7
ELSE
FI;
ENDFORFOR j := 0 to 7
i := j * 32;DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;IF MASK[31+i] THEN
VGATHERQPS (VEX.256 version)
MASK[MAXVL-1:128] := 0;FOR j := 0 to 7
ELSE
FI;
ENDFORFOR j := 0 to 3VGATHERDPS/VGATHERQPS—Gather Packed Single Precision Fl oating-Point Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-349k := j * 64;
i := j * 32;DATA_ADDR := BASE_ADDR + (SignExten d(VINDEX1[k+63:k])*SCALE + DISP;
VGATHERDPS: __m128 _mm_i32gather_ps (float const * base, __m128i index, const int scale);
VGATHERDPS: __m128 _mm_mask_i32gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);VGATHERDPS: __m256 _mm256_i32gather_ps (float const * base, __m256i index, const int scale);
VGATHERDPS: __m256 _mm256_mask_i32gather_ps (__m256 src, float const * base, __m256i index, __m256 mask, const int 
scale);
VGATHERQPS: __m128 _mm_i64gather_ps (float const * base, __m128i index, const int scale);
VGATHERQPS: __m128 _mm_mask_i64gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);VGATHERQPS: __m128 _mm256_i64gather_ps (float const * base, __m256i index, const int scale);
VGATHERQPS: __m128 _mm256_mask_i64gather_ps (__m128 src, float const * base, __m256i index, __m128 mask, const int 
scale);
None.
See Table 2-27, “Type 12 Class Exception Conditions.”VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword IndicesINSTRUCTION SET REFERENCE, V
5-350 Vol. 2CVGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword Indices
A set of single-precision/double precision faulting-point  memory locations pointed by base address BASE_ADDR 
and index vector V_INDEX with scale SCALE are gathered. The result is written into a vector register. The elements 
are specified via the VSIB (i.e., the index register is a vect or register, holding packed indices). Elements will only be

scale);
None.
are specified via the VSIB (i.e., the index register is a vect or register, holding packed indices). Elements will only be 
loaded if their corresponding mask bit is one. If an elem ent’s mask bit is not set, the corresponding element of the 
destination register is left unchanged. The entire mask regist er will be set to zero by this instruction unless it trig-
gers an exception.
is triggered by an element other than the right most one with its mask bit se t). When this happens, the destination 
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into 
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already 
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size , the higher part of the destination register and the mask 
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may 
update these unused elements to one or both of those regi sters even if the instruction triggers an exception, and 
even if the instruction triggers the ex ception before gathering any elements.
Note that:
•Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all 
elements closer to the LSB of the destination zmm will be completed (and non-faulti ng). Individual elements 
closer to the MSB may or may not be completed. If a gi ven element triggers multiple faults, they are delivered 
in the conventional order.
•Elements may be gathered in any order, but faults must be  delivered in a right-to left order; thus, elements to 
the left of a faulting one may be gathered before th e fault is delivered. A given implementation of this Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W0 92 /vsib 
VGATHERDPS xmm1 {k1}, vm32xA V/V AVX512VL
AVX512FUsing signed dword indices, gather single-precision floating-
point values from memory us ing k1 as completion mask.
EVEX.256.66.0F38.W0 92 /vsib 
VGATHERDPS ymm1 {k1}, vm32yA V/V AVX512VL
EVEX.512.66.0F38.W0 92 /vsib 
VGATHERDPS zmm1 {k1}, vm32zA V/V AVX512F Using signed dword indices,  gather single-pre cision floating-
EVEX.128.66.0F38.W1 92 /vsib 
VGATHERDPD xmm1 {k1}, 
vm32xA V/V AVX512VL
AVX512FUsing signed dword indices, gather float64 vector into 
float64 vector xmm1 using k1 as completion mask.
EVEX.256.66.0F38.W1 92 /vsib 
VGATHERDPD ymm1 {k1}, 
float64 vector ymm1 using k1 as completion mask.
EVEX.512.66.0F38.W1 92 /vsib 
VGATHERDPD zmm1 {k1}, vm32yA V/V AVX512F Using signed dword indices, gather float64 vector into 
float64 vector zmm1 using k1 as completion mask.
AT u p l e 1  S c a l a r M o d R M : r e g  ( w )BaseReg (R): VSIB:base,
VectorReg(R): VSIB:indexN/A N/AVGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-351instruction is repeatable - given the same input values an d architectural state, the same set of elements to the 
•Not valid with 16-bit effective addresses. Will deliver a #UD fault.
Note that the presence of VSIB byte is enforced in th is instruction. Hence, the instruction will #UD fault if 
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is  considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit 
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are 
ignored.
The instruction will #UD fault if the destination vector zm m1 is the same as index vector VINDEX. The instruction 
will #UD fault if the k0 ma sk register is specified.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand ve ctor of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)DISP is the optional 1 or 4 byte displacement
VGATHERDPS (EVEX encoded version)
i := j * 32IF k1[j] 
MEM[BASE_ADDR +
SignExtend(VINDEX[i+31:i]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+31:i] :=  remains unchanged*
FI;
ENDFORk1[MAX_KL-1:KL] := 0DEST[MAXVL-1:VL] := 0
VGATHERDPD (EVEX encoded version)
i := j * 64k := j * 32IF k1[j] 
THEN DEST[i+63:i] := MEM[BASE_ADDR +
SignExtend(VINDEX[k+31:k]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+63:i] :=  remains unchanged*
FI;
ENDFORk1[MAX_KL-1:KL] := 0DEST[MAXVL-1:VL] := 0VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword IndicesINSTRUCTION SET REFERENCE, V
5-352 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VGATHERDPD __m512d _mm512_i32gather_pd( __m256i vdx, void * base, int scale);
VGATHERDPD __m512d _mm512_mask_i32gather_pd(__m512d s, __mmask8 k, __m256i vdx, void * base, int scale);VGATHERDPD __m256d _mm256_mmask_i32gather_pd(__m256d s,  __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPD __m128d _mm_mmask_i32gather_pd(__m128d s,  __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_i32gather_ps( __ m512i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_mask_i32gather_ps(__m512 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERDPS __m256 _mm256_mmask_i32gather_ps(__m256 s, __mmask8 k, __m256i vdx, void * base, int scale);
GATHERDPS __m128 _mm_mmask_i32gather_ps(__m128 s, __m mask8 k, __m128i vdx, void * base, int scale);
None.
See Table 2-61, “Type E12 Class Exception Conditions.”VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-353VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
A set of 8 single-precision/double precision faulting-poi nt memory locations pointed by base address BASE_ADDR 
and index vector V_INDEX with scale SCAL E are gathered. The result is written into vector a register. The elements 
are specified via the VSIB (i.e., the index register is a ve ctor register, holding packed indices). Elements will only 
be loaded if their corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of 
the destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it 
triggers an exception.
is triggered by an element other than the rightmost one wi th its mask bit set). When th is happens, the destination 
gathered elements, they will be delivered in lieu of the except ion; in this case, EFLAG.RF is set to one so an instruc-
If the data element size is less than the index element size, the higher part of the destination register and the mask 
Note that:
•Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements 
in the conventional order.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W0 93 /vsib 
VGATHERQPS xmm1 {k1}, vm64xA V/V AVX512VL

Note that:
En64/32 
Bit Mode 
Feature 
AVX512FUsing signed qword indices, gather single-precision 
floating-point values from memory using k1 as completion 
mask.
EVEX.256.66.0F38.W0 93 /vsib 
VGATHERQPS xmm1 {k1}, vm64yA V/V AVX512VL
floating-point values from memory using k1 as completion mask.
EVEX.512.66.0F38.W0 93 /vsib 
VGATHERQPS ymm1 {k1}, vm64zA V/V AVX512F Using signed qword in dices, gather single-precision 
mask.
EVEX.128.66.0F38.W1 93 /vsib 
VGATHERQPD xmm1 {k1}, vm64xA V/V AVX512VL
AVX512FUsing signed qword indices, gather float64 vector into 
EVEX.256.66.0F38.W1 93 /vsib 
VGATHERQPD ymm1 {k1}, vm64yA V/V AVX512VL
EVEX.512.66.0F38.W1 93 /vsib 
VGATHERQPD zmm1 {k1}, vm64zA V/V AVX512F Using signed qword indices, gather float64 vector into 
A Tuple1 Scalar ModRM:reg (w)BaseReg (R): VSIB:base,
VectorReg(R): VSIB:indexN/A N/AVGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword IndicesINSTRUCTION SET REFERENCE, V
5-354 Vol. 2C•Elements may be gathered in any order, but faults must be  delivered in a right-to left order; thus, elements to 
•This instruction does not perform AC checks, and so will never deliver an AC fault.
ignored.
Operation
VINDEX stands for the memory operand vector of indices (a ZMM register)SCALE stands for the memory operand scalar (1, 2, 4 or 8)DISP is the optional 1 or 4 byte displacement
VGATHERQPS (EVEX encoded version)
i := j * 32
k := j * 64IF k1[j] OR *no writemask*
MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]k1[j] := 0
FI;
ENDFORk1[MAX_KL-1:KL] := 0DEST[MAXVL-1:VL/2] := 0
VGATHERQPD (EVEX encoded version)
THEN DEST[i+63:i] := MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]
k1[j] := 0
FI;
ENDFORk1[MAX_KL-1:KL] := 0DEST[MAXVL-1:VL] := 0VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-355Intel C/C++ Compiler Intrinsic Equivalent
VGATHERQPD __m512d _mm512_i64gather_pd( __m512i vdx, void * base, int scale);
VGATHERQPD __m512d _mm512_mask_i64gather_pd(__m512d s, __mmask8 k, __m512i vdx, void * base, int scale);
VGATHERQPD __m256d _mm256_mask_i64gather_pd(__m256d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPD __m128d _mm_mask_i64gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_i64gather_ps( __m512i vdx, void * base, int scale);VGATHERQPS __m256 _mm512_mask_i64gather_ps(__m256 s, __mmask16 k, __m512i vdx, void * base, int scale);VGATHERQPS __m128 _mm256_mask_i64gather_ps(__m128 s, __mmask8 k, __m256i vdx, void * base, int scale);VGATHERQPS __m128 _mm_mask_i64gather_ps(__m128 s, __ mmask8 k, __m128i vdx, vo id * base, int scale);
None.
See Table 2-61, “Type E12 Class Exception Conditions.”VGETEXPPD—Convert Exponents of Packed Double Precision Floati ng-Point Values to Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-356 Vol. 2CVGETEXPPD—Convert Exponents of Packed Double Precision Floating-Point Values to Double 
Extracts the biased exponents from the normalized double  precision floating-point representation of each qword 
data element of the source operand (the second operan d) as unbiased signed integer value, or convert the 
denormal representation of input data to unbiased nega tive integer values. Each in teger value of the unbiased 
exponent is converted to double precision floating-point value and written to the corresponding qword elements of 
the destination operand (the first operand) as double precision floating-point numbers. 
The destination operand is a ZMM/YMM/ XMM register and updated under the writemask. The source operand can 
be a ZMM/YMM/XMM register, a 512/256/128-bit memory lo cation, or a 512/256/128-bit vector broadcasted from 
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in 
denormal representation). Special cases of input values are listed in Table 5-15.
The formula is:GETEXP(x) = floor(log
2(|x|)) 
Notation floor(x)  stands for the greatest integer not exceeding real number x. Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W1 42 /r
VGETEXPPD xmm1 {k1}{z}, 
AVX512FConvert the exponent of packed double precision floating-point 
values in the source operand to double precision floating-point 
results representing unbiased integer exponents and stores the results in the dest ination register.
EVEX.256.66.0F38.W1 42 /r
VGETEXPPD ymm1 {k1}{z}, 
EVEX.512.66.0F38.W1 42 /r
VGETEXPPD zmm1 {k1}{z}, 
zmm2/m512/m64bcst{sae}A V/V AVX512F Convert the exponent of packed double precision floating-point 
results representing unbiased integer exponents and stores the 
results in the destination under writemask k1.
Table 5-15. VGETEXPPD/SD Special Cases
Input Operand Result Comments
src1 = NaN QNaN(src1)
If (SRC = SN aN) then #IE
If (SRC = denormal) then #DE0 < |src1| < INF floor(log2(|src1|)) 
| src1| = +INF +INF
| src1| = 0 -INFVGETEXPPD—Convert Exponents of Packed Double Precision Floati ng-Point Values to Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-357Operation
NormalizeExpTinyDPFP(SRC[63:0])
{
// Jbit is the hidden integral bit of a floati ng-point number. In case of denormal  number it has the value of ZERO.
Src.Jbit := 0;Dst.exp := 1; Dst.fraction := SRC[51:0];WHILE(Src.Jbit = 0){
Src.Jbit := Dst.fraction[5 1]; // Get the fraction MSB
Dst.fraction := Dst.fraction << 1 ; // One bit shift leftDst.exp-- ; // Decrement the exponent
}Dst.fraction := 0; // zero out fraction bitsDst.sign := 1; // Return negative signTMP[63:0] := MXCSR.DAZ? 0 : (Dst.sign << 63 ) OR (Dst.exp << 52) OR (Dst.fraction) ;
Return (TMP[63:0]);
}
ConvertExpDPFP(SRC[63:0])
{
Src.sign := 0; // Zero out sign bitSrc.exp := SRC[62:52];Src.fraction := SRC[51:0];// Check for NaNIF (SRC = NaN) {
IF ( SRC = SNAN ) SET IE;Return QNAN(SRC);
}// Check for +INFIF (Src = +INF) RETURN (Src);
// check if zero operand
IF ((Src.exp = 0) AND ((Src.fraction = 0)  OR (MXCSR.DAZ = 1))) Return (-INF);
}ELSE // check if denormal operand (notice that MXCSR.DAZ = 0){
IF ((Src.exp = 0) AND (Src.fraction != 0)) 
{
TMP[63:0] := NormalizeExpTinyDPFP(SRC[63:0]) ; // Get Normalized ExponentSet #DE
}ELSE // exponent value is correct{
TMP[63:0] := (Src.sign << 63) OR (Src.exp << 52) OR (Src.fraction) ;
}TMP := SAR(TMP, 52) ; // Shift Arithmetic RightTMP := TMP – 1023; // Subtract BiasReturn CvtI2D(TMP); // Convert INT to double precision floating-point number
}
}VGETEXPPD—Convert Exponents of Packed Double Precision Floati ng-Point Values to Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V

}
{
{
}
5-358 Vol. 2CVGETEXPPD (EVEX encoded versions)
THEN 
THEN
ELSE 
ConvertExpDPFP(SRC[i+63:i])FI;
ELSE 
FI
FI;
VGETEXPPD __m512d _mm512 _getexp_pd(__m512d a);
VGETEXPPD __m512d _mm512_m ask_getexp_pd(__m512d s, __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_maskz_get exp_pd( __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm 512_getexp_round_pd(__m512d a, int sae);
VGETEXPPD __m512d _mm512_mask_ge texp_round_pd(__m512d s, __mma sk8 k, __m512d a, int sae);
VGETEXPPD __m512d _mm512_mas kz_getexp_round_pd( __mmask8 k, __m512d a, int sae);
VGETEXPPD __m256d _mm256 _getexp_pd(__m256d a);
VGETEXPPD __m256d _mm256_m ask_getexp_pd(__m256d s, __mmask8 k, __m256d a);
VGETEXPPD __m256d _mm256_maskz_get exp_pd( __mmask8 k, __m256d a);
VGETEXPPD __m128d _mm_ getexp_pd(__m128d a);
VGETEXPPD __m128d _mm_mask_getexp_pd (__m128d s, __mmask8 k, __m128d a);
VGETEXPPD __m128d _mm_maskz_gete xp_pd( __mmask8 k, __m128d a);
See Table 2-46, “Type E2 Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B.VGETEXPPH—Convert Exponents of Packed FP16 Values to FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-359VGETEXPPH—Convert Exponents of Packed FP16 Values to FP16 Values
This instruction extracts the biased exponents from the no rmalized FP16 representation of each word element of 
the source operand (the second operand) as unbiased si gned integer value, or convert the denormal representa-
tion of input data to unbiased negative integer values. Ea ch integer value of the unbiased exponent is converted to 
an FP16 value and written to the corresponding word elemen ts of the destination operand (the first operand) as 
FP16 numbers.
The destination elements are updated according to the writemask.Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in 
denormal representation). Special cases of input values are listed in Table 5-6.
2(|x|))
Notation floor(x)  stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions  generally involve a combination of GETEXP operation 
and GETMANT operation (see VGETMANTPH). Thus, the VG ETEXPPH instruction does not require software to 
handle SIMD floating-point exceptions.Opcode/
En64/32 
Bit Mode 
EVEX.128.66.MAP6.W0  42 /r
VGETEXPPH  xmm1{k1}{z},  xmm2/
AVX512VLConvert the exponent of FP16 values in the source 
operand to FP16 results representing unbiased 
integer exponents and stor es the results in the 
destination register subject to writemask k1.
EVEX.256.66.MAP6.W0  42 /r
VGETEXPPH  ymm1{k1}{z},  ymm2/
EVEX.512.66.MAP6.W0  42 /r
VGETEXPPH  zmm1{k1}{z},  zmm2/
m512/m16bcst  {sae}A V/V AVX512-FP16 Convert the exponent of FP16 values in the source 
Table 5-16. VGETEXPPH/VGETEXPSH Special Cases
If (SRC = SNaN), then #IE.
If (SRC = denormal), then #DE.0 < |src1| < INF floor(log2(|src1|)) 
| src1| = 0 -INFVGETEXPPH—Convert Exponents of Packed FP16 Values to FP16 ValuesINSTRUCTION SET REFERENCE, V
5-360 Vol. 2COperation
def normalize_exponent_tiny_fp16(src):
jbit := 0// src & dst are FP16 numbers with sign (1b), exp(5b) and fraction (10b) fields
dst.exp := 1 // write bits 14:10dst.fraction := src.frac tion // copy bits 9:0
while jbit == 0:
jbit := dst.fraction[9 ] // msb of the fraction
dst.fraction := dst.fraction << 1dst.exp := dst.exp - 1
dst.fraction := 0return dst
def getexp_fp16(src):
src.sign := 0 // make positiveexponent_all_ones := (src[14:10] == 0x1F)
exponent_all_zeros :=  (src[14:10] == 0)
mantissa_all_zeros := (src[9:0] == 0)zero := exponent_all_zeros and mantissa_all_zerossignaling_bit := src[9]
nan := exponent_all_ones and not(mantissa_all_zeros)
snan := nan and not(signaling_bit)qnan := nan and signaling_bitpositive_infinity := not(negative) and exponent_all_ones and mantissa_all_zerosdenormal := exponent_all_zeros and not(mantissa_all_zeros)
if nan:
if snan:
MXCSR.IE := 1
return qnan(src) // convert snan to a qnan
if positive_infinity:
return src
if zero:
return -INF
if denormal:
tmp := normalize_exponent_tiny_fp16(src)MXCSR.DE := 1
else:
tmp := src
tmp := SAR(tmp, 10) // shift arithmetic right
tmp := tmp - 15 // subtract biasreturn convert_integer_to_fp16(tmp)VGETEXPPH—Convert Exponents of Packed FP16 Values to FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-361VGETEXPPH dest{k1}, src
tsrc := src.fp16[0]
ELSE:
tsrc := src.fp16[i]
DEST.fp16[i] := getexp_fp16(tsrc)
DEST.fp16[i] := 0
//else DEST.fp16[i]  remains unchanged
VGETEXPPH __m128h _mm_ge texp_ph (__m128h a);
VGETEXPPH __m128h _mm_mask _getexp_ph (__m128h src,  __mmask8 k, __m128h a);
VGETEXPPH __m128h _mm_maskz_gete xp_ph (__mmask8 k, __m128h a);
VGETEXPPH __m256h _mm256_g etexp_ph (__m256h a);
VGETEXPPH __m256h _mm256_mas k_getexp_ph (__m256h src, __mmask16 k, __m256h a);
VGETEXPPH __m256h _mm256_maskz_get exp_ph (__mmask16  k, __m256h a);
VGETEXPPH __m512h _mm512_g etexp_ph (__m512h a);
VGETEXPPH __m512h _mm512_mas k_getexp_ph (__m512h src, __mmask32 k, __m512h a);
VGETEXPPH __m512h _mm512_maskz_get exp_ph (__mmask32  k, __m512h a);
VGETEXPPH __m512h _mm512 _getexp_round_ph (__m51 2h a, const int sae);
VGETEXPPH __m512h _mm512_mask_gete xp_round_ph (__m512h sr c, __mmask32 k, __m512h a, const int sae);
VGETEXPPH __m512h _mm512_maskz_g etexp_round_ph (__mmask32 k,  __m512h a, const int sae);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VGETEXPPS—Convert Exponents of Packed Si ngle Precision Floating-Point Values to Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-362 Vol. 2CVGETEXPPS—Convert Exponents of Packed Single Precision Floating-Point Values to Single 
Extracts the biased exponents from the normalized single -precision floating-point representation of each dword 
element of the source operand (the second operand) as unbiased signed integer value, or convert the denormal 
representation of input data to unbiased negative integer values. Each integer value of the unbiased exponent is 
converted to single-precision floating-point value and wr itten to the corresponding dword elements of the destina-
tion operand (the first operand) as si ngle-precision floating-point numbers. 
a 32-bit memory location.
denormal representation). Special cases of input values are listed in Table 5-17.
2(|x|)) 
Notation floor(x)  stands for maximal integer not exceeding real number x. 
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD 
floating-point exceptions.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F38.W0 42 /r
VGETEXPPS xmm1 {k1}{z}, 
AVX512FConvert the exponent of packed single-precision floating-point 
values in the source operand to single-precision floating-point 
EVEX.256.66.0F38.W0 42 /r
VGETEXPPS ymm1 {k1}{z}, 
ymm2/m256/m32bcstAV / V A V X 5 1 2 V L

2(|x|)) 
En64/32 
Bit Mode 
Feature 
EVEX.512.66.0F38.W0 42 /r
VGETEXPPS zmm1 {k1}{z}, 
zmm2/m512/m32bcst{sae}A V/V AVX512F Convert the exponent of packed single-precision floating-point 
results in the dest ination register.
Table 5-17. VGETEXPPS/SS Special Cases
Input Operand Result Commentssrc1 = NaN QNaN(src1)
If (SRC = SNaN) then #IE
If (SRC = denormal) then #DE0 < |src1| < INF floor(log
2(|src1|)) 
| src1| = 0 -INFVGETEXPPS—Convert Exponents of Packed Si ngle Precision Floating-Point Values to Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-363Figure 5-14 illustrates the VGETEXPPS functionality on  input values with normalized representation.
Operation
NormalizeExpTiny SPFP(SRC[31:0])
{
Src.Jbit := 0;Dst.exp := 1; Dst.fraction := SRC[22:0];WHILE(Src.Jbit = 0){
Src.Jbit := Dst.fraction[2 2]; // Get the fraction MSB
Dst.fraction := Dst.fraction  << 1 ; // One bit shift left
Dst.exp-- ; // Decrement the exponent
}Dst.fraction := 0; // zero out fraction bitsDst.sign := 1; // Return negative signTMP[31:0] := MXCSR.DAZ? 0 : (Dst.sign << 31 ) OR (Dst.exp << 23) OR (Dst.fraction) ;
Return (TMP[31:0]);
}ConvertExpSPFP(SRC[31:0]){
Src.sign := 0; // Zero out sign bitSrc.exp := SRC[30:23];Src.fraction := SRC[22:0];// Check for NaNIF (SRC = NaN) {
}ELSE // check if denormal operand (notice that MXCSR.DAZ = 0){Figure 5-14.  VGETEXPPS Functionality On Normal Input values31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
S r c  =  2 ^ 1 01000000000000000000000000000000
SAR Src, 23 = 080h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0- B i a s 11111111111111111111111110000001T m p  -  B i a s  =  1 00000000000000000000000000000001Cvt_PI2PS(01h) = 2^0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0exp FractionVGETEXPPS—Convert Exponents of Packed Si ngle Precision Floating-Point Values to Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-364 Vol. 2CIF ((Src.exp = 0) AND (Src.fraction != 0)) 
{
TMP[31:0] := NormalizeExpTinySPFP(SRC[31:0]) ; // Get Normalized ExponentSet #DE
TMP[31:0] := (Src.sign << 31) OR (Src.exp << 23) OR (Src.fraction) ;
}TMP := SAR(TMP, 23) ; // Shift Arithmetic RightTMP := TMP – 127; // Subtract BiasReturn CvtI2S(TMP); // Convert INT to si ngle precision floating-point number
}
}
VGETEXPPS (EVEX encoded versions)
THEN 
THEN
ConvertExpSPFP(SRC[31:0])
ELSE 
ConvertExpSPFP(SRC[i+31:i])FI;
ELSE 
FI
FI;
VGETEXPPS __m512 _mm512 _getexp_ps( __m512 a);
VGETEXPPS __m512 _mm512_m ask_getexp_ps(__m512 s, __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_maskz_get exp_ps( __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512 _getexp_round_ps( __m512 a, int sae);
VGETEXPPS __m512 _mm512_mask_ge texp_round_ps(__m512  s, __mmask16 k, __m512 a, int sae);
VGETEXPPS __m512 _mm512_maskz _getexp_round_ps( __mmask16 k, __m512 a, int sae);
VGETEXPPS __m256 _mm256 _getexp_ps(__m256 a);
VGETEXPPS __m256 _mm256_m ask_getexp_ps(__m256 s, __mmask8 k, __m256 a);
VGETEXPPS __m256 _mm256_maskz_get exp_ps( __mmask8 k, __m256 a);
VGETEXPPS __m128 _mm_ getexp_ps(__m128 a);
VGETEXPPS __m128 _mm_mask _getexp_ps(__m128 s, __mmask8 k, __m128 a);
VGETEXPPS __m128 _mm_maskz_gete xp_ps( __mmask8 k, __m128 a);VGETEXPPS—Convert Exponents of Packed Si ngle Precision Floating-Point Values to Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-365SIMD Floating-Point Exceptions
#UD If EVEX.vvvv != 1111B.VGETEXPSD—Convert Exponents of Scalar Do uble Precision Floating-Point Value to Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, V
5-366 Vol. 2CVGETEXPSD—Convert Exponents of Scalar Double Precision Floating-Point Value to Double 
Precision Floating-Point Value
Extracts the biased exponent from the normalized double precision floating-point representation of the low qword 
data element of the source operand (the third operand) as  unbiased signed integer value, or convert the denormal 
representation of input data to unbiased negative intege r values. The integer value of the unbiased exponent is 
converted to double precision floating-point value and wr itten to the destination operand (the first operand) as 
double precision floating-point numbers. Bits (127:64) of the XMM register destination are copied from corre-
sponding bits in the first source operand.
The destination must be a XMM register, the source operan d can be a XMM register or a float64 memory location.
If writemasking is used, the low quadword element of th e destination operand is cond itionally updated depending 
on the value of writemask register k1. If writemasking is not used, the low quadword element of the destination 
operand is unconditionally updated.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in 
2(|x|)) 
Operation
// NormalizeExpTinyDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD
// ConvertExpDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPDVGETEXPSD (EVEX encoded version) 
THEN DEST[63:0] :=
ConvertExpDPFP(SRC2[63:0])
ELSE 
FI
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.66.0F38.W1 43 /r
VGETEXPSD xmm1 {k1}{z}, 
xmm2, xmm3/m64{sae}A V/V AVX512F Convert the biased exponent (bits 62:52) of the low double 
precision floating-point value in xmm3/m64 to a double 
precision floating-point value representing unbiased integer exponent. Stores the result to the low 64-bit of xmm1 under 
the writemask k1 and merge with the other elements of 
xmm2.
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVGETEXPSD—Convert Exponents of Scalar Double Precision Floa ting-Point Value to Double Precision Floating-Point ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-367Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSD __m128d _mm_getexp_sd( __m128d a, __m128d b);
VGETEXPSD __m128d _mm_mask_getexp_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);VGETEXPSD __m128d _mm_maskz_getexp_sd(  __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_getexp_round_sd( __m128d a, __m128d b, int sae);VGETEXPSD __m128d _mm_mask_getexp_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_maskz_getexp_round_sd( __ mmask8 k, __m128d a, __m128d b, int sae);
Invalid, Denormal
See Table 2-47, “Type E3 Class Exception Conditions.”VGETEXPSH—Convert Exponents of Scalar FP16 Values to FP16 ValuesINSTRUCTION SET REFERENCE, V
5-368 Vol. 2CVGETEXPSH—Convert Exponents of Sc alar FP16 Values to FP16 Values
This instruction extracts the biased exponents from the normalized FP16 representation of the low word element of 
the source operand (the second operand) as unbiased sign ed integer value, or convert the denormal representation 
of input data to an unbiased negative integer value. The integer value of the unbiased exponent is converted to an 
FP16 value and written to the low word element of the de stination operand (the first operand) as an FP16 number.
Bits 127:16 of the destination operand are copied from th e corresponding bits of the first source operand. Bits

denormal representation). Special cases of input values are listed in Table 5-16.
2(|x|))
and GETMANT operation (see VGETMANTSH). Thus, the VG ETEXPSH instruction does not require software to 
handle SIMD floating-point exceptions.
Operation
VGETEXPSH dest{k1}, src1, src2 
DEST.fp16[0] := getexp_fp16( src2.fp16[0]) // see VGETEXPPH
//else DEST.fp16[0] remains unchanged
DEST[127:16] := src1[127:16]
VGETEXPSH __m128h _mm_getexp_round_sh (__m 128h a, __m128h b, const int sae);
VGETEXPSH __m128h _mm_mask_getexp_round_sh (__m128h src,  __mmask8 k, __m128h a, __m128h b, const int sae);
VGETEXPSH __m128h _mm_maskz_getexp_round_sh (__mmask8 k, __m128h a, __m128h b, const int sae);VGETEXPSH __m128h _mm_getexp_sh (__m128h a, __m128h b);VGETEXPSH __m128h _mm_mask_getexp_sh (__m128h  src, __mmask8 k, __m128h a, __m128h b);
VGETEXPSH __m128h _mm_maskz_getexp_sh (__mmask8 k, __m128h a, __m128h b);Opcode/
En64/32 
Bit Mode 
EVEX.LLIG.66.MAP6.W0 43 /r
VGETEXPSH xmm1{k1}{z}, xmm2, 
xmm3/m16 {sae}A V/V AVX512-FP16 Convert the exponent of FP16 values in the low 
word of the source operand to FP16 results 
representing unbiased integer exponents, and stores 
the results in the low wo rd of the destination 
register subject to writemask k1. Bits 127:16 of 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVGETEXPSH—Convert Exponents of Scalar FP16 Values to FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-369SIMD Floating-Point Exceptions
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”VGETEXPSS—Convert Exponents of Scalar Single Precision Floa ting-Point Value to Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, V
5-370 Vol. 2CVGETEXPSS—Convert Exponents of Scalar Single Precision Floating-Point Value to Single 
Extracts the biased exponent from the normalized single-p recision floating-point representation of the low double-
word data element of the source operand (the third oper and) as unbiased signed integer value, or convert the 
denormal representation of input data to unbiased negati ve integer values. The integer value of the unbiased expo-
nent is converted to single-precision floating-point value and written to the destination operand (the first operand) 
as single-precision floating-point numbers. Bits (127:32) of the XMM register destination are copied from corre-
The destination must be a XMM register, the source operan d can be a XMM register or a float32 memory location.
If writemasking is used, the low doub leword element of the destination operand is conditionally updated depending 
on the value of writemask register k1. If writemasking is  not used, the low doubleword element of the destination 
2(|x|)) 
Operation
// NormalizeExpTinySPFP(SRC[31:0]) is defi ned in the Operation section of VGETEXPPS
// ConvertExpSPFP(SRC [31:0]) is defined in the Op eration section of VGETEXPPS
VGETEXPSS (EVEX encoded version) 
THEN DEST[31:0] :=
ConvertExpDPFP(SRC2[31:0])
ELSE 
DEST[31:0]:= 0
FI
FI;
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.66.0F38.W0 43 /r
VGETEXPSS xmm1 {k1}{z}, xmm2, 
xmm3/m32{sae}A V/V AVX512F Convert the biased exponent (bits 30:23) of the low single-
precision floating-point value in xmm3/m32 to a single-
precision floating-point value representing unbiased integer exponent. Stores the result to xmm1 under the writemask 
k1 and merge with the other elements of xmm2.
A Tuple1 Scalar ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/AVGETEXPSS—Convert Exponents of Scalar Single Precision Floa ting-Point Value to Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-371DEST[127:32] := SRC1[127:32]
VGETEXPSS __m128 _mm_getexp_ss( __m128 a, __m128 b);
VGETEXPSS __m128 _mm_mask_getexp_ss(__m128  s, __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_maskz_getexp_ss(  __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_getexp_round_s s( __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_mask_getexp_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_maskz_getexp_round_ss( __mmask8 k, __m128 a, __m128 b, int sae);
See Table 2-47, “Type E3 Class Exception Conditions.”VGETMANTPD—Extract Float64 Vector of No rmalized Mantissas From Float64 VectorINSTRUCTION SET REFERENCE, V
5-372 Vol. 2CVGETMANTPD—Extract Float64 Vector of No rmalized Mantissas From Float64 Vector
Convert double precision floating values in the source op erand (the second operand) to double precision floating-
point values with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The 
converted results are written to the destination operand (the first operand) using writemask k1. The normalized 
mantissa is specified by interv (imm8[1:0]) and the sign co ntrol (sc) is specified by bits 3:2 of the immediate byte. 
The destination operand is a ZMM/YMM/XMM register upda ted under the writemask. The source operand can be a 
ZMM/YMM/XMM register, a 512/256/128-bit memory location , or a 512/256/128-bit vector broadcasted from a 64-
For each input double precision floating-point value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on  the interval range defined by interv, the range of the 
significand and whether the exponent of th e source is even or odd. The sign of  the final result is determined by sc Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F3A.W1 26 /r ib
VGETMANTPD xmm1 {k1}{z}, 
AVX512FGet Normalized Mantissa from float64 vector 
xmm2/m128/m64bcst and store the result in xmm1, using 
imm8 for sign control and mantissa interval normalization, 
under writemask.
EVEX.256.66.0F3A.W1 26 /r ib
VGETMANTPD ymm1 {k1}{z}, 
ymm2/m256/m64bcst and store the result in ymm1, using 
EVEX.512.66.0F3A.W1 26 /r ib
VGETMANTPD zmm1 {k1}{z}, 
zmm2/m512/m64bcst{sae}, 
imm8AV / V A V X 5 1 2 F G e t  N o r m a l i z e d  M a ntissa from float64 vector 
zmm2/m512/m64bcst and store the result in zmm1, using 
A Full ModRM:reg (w) ModRM:r/m (r) imm8 N/A
Figure 5-15.  Imm8 Controls for VGETMANTPD/SD/PS/SS7 0 2 4 65 3 1
Normaiization Interval Must Be Zero
Imm8[3:2] = 00b : sign(SRC)Sign Control (SC)
Imm8[3:2] = 01b : 0
Imm8[3] = 1b : qNan_Indefinite if sign(SRC) != 0, regardless of imm8[2].Imm8[1:0] = 00b : Interval is [ 1, 2)
Imm8[1:0] = 01b : Interval is [1/2, 2)Imm8[1:0] = 10b : Interval is [ 1/2, 1)
Imm8[1:0] = 11b : Interval is [3/4, 3/2)imm8VGETMANTPD—Extract Float64 Vector of No rmalized Mantissas From Float64 VectorINSTRUCTION SET REFERENCE, V
Vol. 2C 5-373and the source sign. The encoded value of imm8 [1:0] and sign control are shown in Figure 5-15.

Each converted double precision floating-point result is encoded according to the sign control, the unbiased expo-
nent k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.This instruction is writemasked, so only those elements wi th the corresponding bit set in vector mask register k1 
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their 
previous values.
Note: EVEX.vvvv is reserved  and must be 1111b; otherwise instructions will #UD.
Operation
def getmant_fp64(src, sign_contr ol, normalization_interval): 
bias := 1023dst.sign := sign_control[0] ? 0 : src.signsigned_one := sign_con trol[0] ? +1.0 : -1.0
dst.exp := src.expdst.fraction := src.fractionzero := (dst.exp = 0) and ((dst. fraction = 0) or (MXCSR.DAZ=1))
denormal := (dst.exp = 0) and (dst .fraction != 0) and (MXCSR.DAZ=0)
infinity := (dst.exp = 0x 7FF) and (dst.fraction = 0)
nan := (dst.exp = 0x7FF) and (dst.fraction != 0)src_signaling := src.fraction[51]
snan := nan and (src_signaling = 0)positive := (src.sign = 0)negative := (src.sign = 1)if nan:
if snan:
return qnan(src)
if positive and (zero or infinity):
return 1.0
if negative:
if zero:
return signed_oneTable 5-18. GetMant() Spec ial Float Values Behavior
Input Result Exceptions / Comments
NaN QNaN(SRC) Ignore interv
+∞ 1.0 Ignore interv
+0 1.0 Ignore interv
-0 IF (SC[0]) THEN +1.0
                  ELSE -1.0Ignore interv
-∞ IF (SC[1]) THEN {QNaN_Indefinite} 
ELSE {
   IF (SC[0]) THEN +1.0
                     ELSE -1.0Ignore interv
If (SC[1]) then #IE
negative SC[1] ? QNaN_Indefinite : Getmant(SRC)1
NOTES:
1. In case SC[1]==0, the si gn of Getmant(SRC) is de clared according to SC[0].If (SC[1]) then #IEVGETMANTPD—Extract Float64 Vector of No rmalized Mantissas From Float64 VectorINSTRUCTION SET REFERENCE, V
5-374 Vol. 2Cif infinity:
if sign_control[1]:
MXCSR.IE := 1return QNaN_Indefinite
return signed_one
jbit := 0dst.exp := bias while jbit = 0:
jbit := dst.fraction[51]dst.fraction := dst.fraction << 1dst.exp : = dst.exp - 1
MXCSR.DE := 1
unbiased_exp := dst.exp - bias
odd_exp := unbiased_exp[0]signaling_bit := dst.fraction[51]if normalization_interval = 0b00:
dst.exp := bias
else if normalization_interval = 0b01:
dst.exp := odd_exp ? bias-1 : bias 
else if normalization_interval = 0b10:
dst.exp := bias-1 
else if normalization_interval = 0b11:
dst.exp := signaling_bit ? bias-1 : bias
return dst
VGETMANTPD (EVEX Encoded Versions)
VGETMANTPD dest{k1}, src, imm8VL = 128, 256, or 512KL := VL / 64sign_control := imm8[3:2] normalization_interval := imm8[1:0]
tsrc := src.double[0]
ELSE:
tsrc := src.double[i]
DEST.double[i] := getmant_fp64(tsrc, sign_control, normalization_interval)
DEST.double[i] := 0
//else DEST.double[i] remains unchanged
DEST[MAX_VL-1:VL] := 0VGETMANTPD—Extract Float64 Vector of No rmalized Mantissas From Float64 VectorINSTRUCTION SET REFERENCE, V
Vol. 2C 5-375Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPD __m512d _mm512_getmant_pd( __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_mask_getmant_pd(__m512d s,  __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_maskz_getmant_pd( __ mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_getmant_round_pd( __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_mask_getmant _round_pd(__m512d s, __mmask8 k, __m512 d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_maskz_getmant_round_pd( __m mask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m256d _mm256_getmant_pd( __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_mask_getmant_pd(__m256d s,  __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_maskz_getmant_pd( __ mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_getmant_pd( __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_mask_getmant_pd(__m128d s, __mmask8 k, __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_maskz_getmant_pd( __mma sk8 k, __m128d a, enum intv, enum sgn);
Denormal, Invalid.
Additionally:#UD If EVEX.vvvv != 1111B.VGETMANTPH—Extract FP16 Vector of No rmalized Mantissas from FP16 VectorINSTRUCTION SET REFERENCE, V
5-376 Vol. 2CVGETMANTPH—Extract FP16 Vector of No rmalized Mantissas from FP16 Vector
This instruction converts the FP16 values in the source operand (the second operand) to FP16 values with the 
mantissa normalization and sign control specified by th e imm8 byte, see Table 5-19. The converted results are 
written to the destination operand (the first operand) usin g writemask k1. The normalized mantissa is specified by 
interv (imm8[1:0]) and the sign control (SC) is  specified by bits 3:2 of the immediate byte.
For each input FP16 value x, The conversion operation is:
where:
1 ≤ |x.significand| < 2Opcode/
En64/32 
Bit Mode 
EVEX.128.NP.0F3A.W0 26 /r /ib
VGETMANTPH xmm1{k1}{z}, xmm2/
AVX512VLGet normalized mantissa from FP16 vector 
xmm2/m128/m16bcst and store the result in 
xmm1, using imm8 for sign control and mantissa 
interval normalization, subject to writemask k1.
EVEX.256.NP.0F3A.W0 26 /r /ib
VGETMANTPH ymm1{k1}{z}, ymm2/
ymm2/m256/m16bcst and store the result in 
ymm1, using imm8 for sign control and mantissa 
EVEX.512.NP.0F3A.W0 26 /r /ib
VGETMANTPH zmm1 {k1}{z}, zmm2/
m512/m16bcst {sae}, imm8A V/V AVX512-FP16 Get normalized mantissa from FP16 vector 
zmm2/m512/m16bcst and store the result in 
zmm1, using imm8 for sign control and mantissa 
Table 5-19. imm8 Controls for VGETMANTPH/VGETMANTSH
imm8 Bits Definition
imm8[7:4] Must be zero.
imm8[3:2] Sign Control (SC)
0b00: Sign(SRC) 
0b01: 00b1x: QNaN_Indefinite if sign(SRC)!=0
imm8[1:0] Interv
0b00: Interval is [1, 2) 
0b01: Interval is [1/2, 2) 
0b10: Interval is [1/2, 1)0b11: Interval is [3/4, 3/2)VGETMANTPH—Extract FP16 Vector of No rmalized Mantissas from FP16 VectorINSTRUCTION SET REFERENCE, V
Vol. 2C 5-377Unbiased exponent k depends on the interval range define d by interv and whether the exponent of the source is 
even or odd. The sign of the final result is determined by  the sign control and the source sign and the leading frac-
tion bit.
The encoded value of imm8[1:0] and si gn control are shown in Table 5-19.
Each converted FP16 result is encoded according to the sign control, the unbiased exponent k (adding bias) and a 
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-20 when dealing with floating-point special numbers.
Operation
def getmant_fp16(src, sign_con trol, normalization_interval):
bias := 15dst.sign := sign_control[0] ? 0 : src.signsigned_one := sign_con trol[0] ? +1.0 : -1.0
dst.exp := src.expdst.fraction := src.fractionzero := (dst.exp = 0)  and (dst.fraction = 0)
denormal := (dst.exp = 0)  and (dst.fraction != 0)
infinity := (dst.exp = 0x 1F) and (dst.fraction = 0)
nan := (dst.exp = 0x1F) and (dst.fraction != 0)src_signaling := src.fraction[9]snan := nan and (src_signaling = 0)positive := (src.sign = 0)negative := (src.sign = 1)if nan:
if snan:
return 1.0
if zero:
if infinity:Table 5-20. GetMant() Spec ial Float Values Behavior
NaN QNaN(SRC) Ignore interv.
If (SRC = SNaN ), then #IE.
+∞ 1.0 Ignore interv.
+0 1.0 Ignore interv.
                  ELSE -1.0Ignore interv.
ELSE {
                     ELSE -1.0Ignore interv.
If (SC[1]), then #IE.
NOTES:
1. In case SC[1]==0, the si gn of Getmant(SRC) is de clared according to SC[0].If (SC[1]), then #IE.VGETMANTPH—Extract FP16 Vector of No rmalized Mantissas from FP16 VectorINSTRUCTION SET REFERENCE, V
5-378 Vol. 2Cif sign_control[1]:
jbit := 0dst.exp := bias // set exponent to bias valuewhile jbit = 0:

return 1.0
if zero:
ELSE {
NOTES:
jbit := dst.fraction[9]dst.fraction := dst.fraction << 1dst.exp : = dst.exp - 1
unbaiased_exp := dst.exp - bias
odd_exp := unbaiased_exp[0]signaling_bit := dst.fraction[9]if normalization_interval = 0b00:
dst.exp := odd_exp ? bias-1 : bias
dst.exp := bias-1
return dst
VGETMANTPH dest{k1}, src, imm8 
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
ELSE:
DEST.fp16[i] := getmant_fp16(tsrc, sign_control, normalization_interval)
//else DEST.fp16[i] remains unchanged
DEST[MAXVL-1:VL] := 0VGETMANTPH—Extract FP16 Vector of No rmalized Mantissas from FP16 VectorINSTRUCTION SET REFERENCE, V
Vol. 2C 5-379Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPH __m128h _mm_getmant_ph (__m128h a, _MM_MA NTISSA_NORM_ENUM norm, _MM_ MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m128h _mm_mask_getmant_p h (__m128h src, __mmask8 k, __m128 h a, _MM_MANTISSA_NORM_ENUM norm, 
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m128h _mm_maskz_getmant_ph (__mmask 8 k, __m128h a, _MM_MA NTISSA_NORM_ENUM norm, 
VGETMANTPH __m256h _mm256_getmant_ph (__m256h a, _MM_MA NTISSA_NORM_ENUM norm, _MM_ MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m256h _mm256_mask_getmant_ph (__m256h src, __mmask16 k, __m256h a, _MM_ MANTISSA_NORM_ENUM norm, 
VGETMANTPH __m256h _mm256_maskz_getmant_ph (__mmask 16 k, __m256h a, _MM_MANTISSA_NORM_ENUM norm, 
VGETMANTPH __m512h _mm512_getmant_ph (__m512h a, _MM_MA NTISSA_NORM_ENUM norm, _MM_ MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_mask_getmant_ph (__m512h src, __mmask32 k, __m512h a, _MM_ MANTISSA_NORM_ENUM norm, 
VGETMANTPH __m512h _mm512_maskz_getmant_ph (__mmask 32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm, 
VGETMANTPH __m512h _mm512_getmant_round_ph ( __m512h a, _MM_MANTIS SA_NORM_ENUM norm, 
_MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTPH __m512h _mm512_mask_getmant_round_ph (__m512h sr c, __mmask32 k, __m512h a,  _MM_MANTISSA_NORM_ENUM 
norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTPH __m512h _mm512_maskz_getmant_round_ph (__mma sk32 k, __m512h a, _MM_ MANTISSA_NORM_ENUM norm, 
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VGETMANTPS—Extract Float32 Vector of No rmalized Mantissas From Float32 VectorINSTRUCTION SET REFERENCE, V
5-380 Vol. 2CVGETMANTPS—Extract Float32 Vector of No rmalized Mantissas From Float32 Vector
Convert single-precision floating values in the source op erand (the second operand) to single-precision floating-
For each input single-precision floating-point value x, The conversion operation is:
GetMant (x) = ±2k|x.significand|
where:
significand and whether the exponent of th e source is even or odd. The sign of  the final result is determined by sc 
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
Each converted single-precision floating-point result is encoded according to the sign control, the unbiased expo-
The GetMant() function follows Table 5-18 when  dealing with floating-point special numbers.
Note: EVEX.vvvv is reserved and must be 1111b, VE X.L must be 0; otherwise instructions will #UD.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.128.66.0F3A.W0 26 /r ib
VGETMANTPS xmm1 {k1}{z}, 
xmm2/m128/m32bcst, imm8AV / V A V X 5 1 2 V L
AVX512FGet normalized mantissa from float32 vector 
xmm2/m128/m32bcst and store the result in xmm1, using 
EVEX.256.66.0F3A.W0 26 /r ib
VGETMANTPS ymm1 {k1}{z}, 
ymm2/m256/m32bcst, imm8AV / V A V X 5 1 2 V L
ymm2/m256/m32bcst and store the result in ymm1, using 
EVEX.512.66.0F3A.W0 26 /r ib
VGETMANTPS zmm1 {k1}{z}, 
zmm2/m512/m32bcst{sae}, 
imm8A V/V AVX512F Get normalized mantissa from float32 vector 
zmm2/m512/m32bcst and store the result in zmm1, using 
A Full ModRM:reg (w) ModRM:r/m (r) imm8 N/AVGETMANTPS—Extract Float32 Vector of No rmalized Mantissas From Float32 VectorINSTRUCTION SET REFERENCE, V
Vol. 2C 5-381Operation
def getmant_fp32(src, sign_con trol, normalization_interval):
bias := 127dst.sign := sign_control[0] ? 0 : src.signsigned_one := sign_con trol[0] ? +1.0 : -1.0
infinity := (dst.exp = 0x FF) and (dst.fraction = 0)
nan := (dst.exp = 0xFF) and (dst.fraction != 0)src_signaling := src.fraction[22]
if snan:
return 1.0
if zero:
if infinity:
jbit := 0dst.exp := biaswhile jbit = 0:
jbit := dst.fraction[22]dst.fraction := dst.fraction << 1dst.exp : = dst.exp - 1
odd_exp  := unbiased_exp[0]signaling_bit := dst.fraction[22]if normalization_interval = 0b00:
dst.exp := signaling_bit ? bias-1 : biasVGETMANTPS—Extract Float32 Vector of No rmalized Mantissas From Float32 VectorINSTRUCTION SET REFERENCE, V
5-382 Vol. 2Creturn dst
VGETMANTPS (EVEX encoded versions)
VGETMANTPS dest {k1}, src, imm8
VL = 128, 256, or 512KL := VL / 32sign_control := imm8[3:2] normalization_interval := imm8[1:0]
tsrc := src.float[0]
ELSE:
tsrc := src.float[i]
DEST.float[i] := getmant_ fp32(tsrc, sign_control, normalization_interval)
DEST.float[i] := 0
//else DEST.float[i ] remains unchanged
VGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a,  enum intv, enum sgn;
VGETMANTPS __m512 _mm512_maskz_getmant_ps(__m mask16 k, __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_mask_getmant_ro und_ps(__m512 s, __mmask16 k, __m512  a, enum intv, en um sgn, int r);
VGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask 16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s,  __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_maskz_getmant_ps( __m mask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_getmant_ps( __ m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_maskz_getmant_ps( __mma sk8 k, __m128 a, en um intv, enum sgn);

#UD If EVEX.vvvv != 1111B.VGETMANTSD—Extract Float64 of Normal ized Mantissa From Float64 ScalarINSTRUCTION SET REFERENCE, V
Vol. 2C 5-383VGETMANTSD—Extract Float64 of Normal ized Mantissa From Float64 Scalar
Convert the double precision floating values in the low qu adword element of the second source operand (the third 
operand) to double precision floating-point value with th e mantissa normalization and sign control specified by the 
imm8 byte, see Figure 5-15 . The converted result is written to the low quadword element of the destination 
operand (the first operand) using writemask k1. Bits (127 :64) of the XMM register destination are copied from 
corresponding bits in the first source operand. The norma lized mantissa is specified by interv (imm8[1:0]) and the 
sign control (sc) is specified by  bits 3:2 of the immediate byte. 
The conversion operation is:
where:
significand and whether the exponent of the source is even or odd. The sign of the fina l result is determined by sc 
and the source sign. The encoded value of imm8 [1:0] and sign control are shown in Figure 5-15.
The converted double precision floating-point result is encoded according to the sign control, the unbiased expo-
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.
If writemasking is used, the low quadword element of th e destination operand is conditionally updated depending 
operand is unconditionally updated.Opcode/
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W1 27 /r ib
VGETMANTSD xmm1 {k1}{z}, xmm2, 
xmm3/m64{sae}, imm8A V/V AVX512F Extract the normalized  mantissa of the low float64 
element in xmm3/m64 using imm8 for sign control and 
mantissa interval normalization. Store the mantissa to 
xmm1 under the writemask k1 and merge with the other elements of xmm2.
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVGETMANTSD—Extract Float64 of Normalized Mantissa From Float64 ScalarINSTRUCTION SET REFERENCE, V
5-384 Vol. 2COperation
// getmant_fp64(src, sign_control, norm alization_interval) is defined in the operation section of VGETMANTPD
VGETMANTSD (EVEX encoded version) 
SignCtrl[1:0] := IMM8[3:2];Interv[1:0] := IMM8[1:0];IF k1[0] OR *no writemask*
getmant_fp64(src, si gn_control, normalization_interval)
ELSE 
FI
FI;DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0
VGETMANTSD __m128d _mm_getmant_sd( __m128d a, __m128 b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_mask_getmant_sd(__m128d s, __mma sk8 k, __m128d a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_maskz_getmant_sd( __mmask8 k, __m128 a, __m128d b, enum intv, enum sgn);VGETMANTSD __m128d _mm_getmant_round_sd( __m128d a, __m128 b, enum intv, enum sgn, int r);VGETMANTSD __m128d _mm_mask_getmant_round_sd(__m128d s, __mmask 8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_maskz_getmant_round_sd( __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
Denormal, Invalid
See Table 2-47, “Type E3 Class Exception Conditions.”VGETMANTSH—Extract FP16 of Normal ized Mantissa from FP16 ScalarINSTRUCTION SET REFERENCE, V
Vol. 2C 5-385VGETMANTSH—Extract FP16 of Normal ized Mantissa from FP16 Scalar
This instruction converts the FP16 value in the low elemen t of the second source operand to FP16 values with the 
mantissa normalization and sign control specified by the imm8 byte, see Table 5-19. The converted result is written 
to the low element of the destination operand using writem ask k1. The normalized manti ssa is specified by interv 
(imm8[1:0]) and the sign control (SC) is sp ecified by bits 3:2 of the immediate byte.
where:
1 ≤ |x.significand| < 2
Unbiased exponent k depends on the interval range define d by interv and whether the exponent of the source is 
tion bit.
Operation
VGETMANTSH dest{k1}, src1, src2, imm8
sign_control := imm8[3:2]normalization_interval := imm8[1:0]
dest.fp16[0] := getmant_fp16( src2.fp16[0], // see VGETMANTPH
sign_control,normalization_interval)
dest.fp16[0] := 0
//else dest.fp16[0] remains unchanged
En64/32 
Bit Mode 
EVEX.LLIG.NP.0F3A.W0 27 /r /ib
VGETMANTSH xmm1{k1}{z}, xmm2, 
xmm3/m16 {sae}, imm8A V/V AVX512-FP16 Extract the normal ized mantissa of the low FP16 
element in xmm3/m16 using imm8 for sign 
control and mantissa interval normalization. Store 
the mantissa to xmm1 su bject to writemask k1 
and merge with the other elements of xmm2. Bits 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)VGETMANTSH—Extract FP16 of Normalized Mantissa from FP16 ScalarINSTRUCTION SET REFERENCE, V
5-386 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VGETMANTSH __m128h _mm_getmant_round_sh (__m128h  a, __m128h b, _MM_MANTISSA_NORM_ENUM norm, 
VGETMANTSH __m128h _mm_mask_getma nt_round_sh (__m128h src, __mma sk8 k, __m128h a, __m128h b, 
_MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTSH __m128h _mm_maskz_getmant_ro und_sh (__mmask8 k, __m128h a, __m1 28h b, _MM_MANTISSA_NORM_ENUM norm, 
VGETMANTSH __m128h _mm_getmant_sh (__m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm, 
VGETMANTSH __m128h _mm_mask_getmant_s h (__m128h src, __mmask8 k, __m128h a, __m128h b, _MM_MA NTISSA_NORM_ENUM 
norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTSH __m128h _mm_maskz_getman t_sh (__mmask8 k, __m128h a, __m128 h b, _MM_MANTISSA_NORM_ENUM norm, 
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VGETMANTSS—Extract Float32 Vector of No rmalized Mantissa From Float32 ScalarINSTRUCTION SET REFERENCE, V
Vol. 2C 5-387VGETMANTSS—Extract Float32 Vector of No rmalized Mantissa From Float32 Scalar
Convert the single-precision floating values in the low do ubleword element of the second source operand (the third 
operand) to single-precision floating-point value with the mantissa normalization and sign control specified by the 
imm8 byte, see Figure 5-15 . The converted result is written to the low doubleword element of the destination 
operand (the first operand) using writemask k1. Bits (127 :32) of the XMM register destination are copied from 
where:
The converted single-precision floating-point result is encoded according to the sign control, the unbiased expo-

where:
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.If writemasking is used, the low doubleword element of the destination operand is conditionally updated depending 
En64/32 
Bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W0 27 /r ib
VGETMANTSS xmm1 {k1}{z}, xmm2, 
xmm3/m32{sae}, imm8A V/V AVX512F Extract the normalized  mantissa from the low float32 
element of xmm3/m32 using imm8 for sign control and 
mantissa interval normalizatio n, store the mantissa to 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVGETMANTSS—Extract Float32 Vector of No rmalized Mantissa From Float32 ScalarINSTRUCTION SET REFERENCE, V
5-388 Vol. 2COperation
// getmant_fp32(src, sign_control, norm alization_interval) is defined in the operation section of VGETMANTPS
VGETMANTSS (EVEX encoded version) 
getmant_fp32(src, si gn_control, normalization_interval)
ELSE 
FI
FI;DEST[127:32] := SRC1[127:32] DEST[MAXVL-1:128] := 0
VGETMANTSS __m128 _mm_getmant_ss( __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_mask_getmant_s s(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum in tv, enum sgn, int r);
VGETMANTSS __m128 _mm_mask_getma nt_round_ss(__m128 s, __mmask8 k, __m128 a,  __m128 b, enum intv , enum sgn, int r);
VGETMANTSS __m128 _mm_maskz_getmant_ro und_ss( __mmask8 k, __m128 a, __m128  b, enum intv, en um sgn, int r);
See Table 2-47, “Type E3 Class Exception Conditions.”VINSERTF128/VINSERTF32x4/VINSERTF64x 2/VINSERTF32x8/VINSERTF64x4—Insert  Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-389VINSERTF128/VINSERTF32x4/VINSERTF64x2/VI NSERTF32x8/VINSERTF64x4—Insert Packed 
VINSERT F128/V INSERT F32x4 and VINSERTF64x2 insert 128-bits of packed floating-point values from the second 
source operand (the third operand) into the destination oper and (the first operand) at an 128-bit granularity offset 
multiplied by imm8[0] (256-bit) or imm8[1:0]. The remainin g portions of the destination operand are copied from 
the corresponding fields of the first source operand (the second operand). The second source operand can be either an XMM register or a 128-bit memory location. The destin ation and first source operands are vector registers.
VINSERTF32x4: The destination operand is a ZMM/YMM register and updated at 32-bit granularity according to the 
writemask. The high 6/7 bits of the immediate are ignored. 
VINSERTF64x2: The destination operand is a ZMM/YMM register and updated at 64-bit granularity according to the 
VINSERTF32x8 and V INSERT F64x4 inserts 256-bits of packed floating-poi nt values from the second source operand 
(the third operand) into the destination operand (the firs t operand) at a 256-bit granular offset multiplied by 
imm8[0]. The remaining portions of the destination are co pied from the corresponding fields of the first source 
operand (the second operand). The second source operan d can be either an YMM register or a 256-bit memory 
location. The high 7 bits of the immediate are ignored. The destination operand is a ZMM register and updated at 
32/64-bit granularity according to the writemask.Opcode/
En64/32 
Bit Mode 
Feature 
VEX.256.66.0F3A.W0 18 /r ib
xmm3/m128, imm8A V/V AVX Insert 128 bits of packed  floating-point values from 
xmm3/m128 and the remaining values from ymm2 
into ymm1.
EVEX.256.66.0F3A.W0 18 /r ib
VINSERTF32X4 ymm1 {k1}{z}, ymm2, 
xmm3/m128, imm8C V/V AVX512VL
AVX512FInsert 128 bits of packed single-precision floating-
point values from xmm3 /m128 and the remaining 
values from ymm2 into ymm1 under writemask k1.
EVEX.512.66.0F3A.W0 18 /r ib
VINSERTF32X4 zmm1  {k1}{z}, zmm2, 
xmm3/m128, imm8C V/V AVX512F Insert 128 bits of packed single-precision floating-
values from zmm2 into zmm1 under writemask k1.
EVEX.256.66.0F3A.W1 18 /r ib
VINSERTF64X2 ymm1 {k1}{z}, ymm2, 
xmm3/m128, imm8B V/V AVX512VL
AVX512DQInsert 128 bits of packed double precision floating-
EVEX.512.66.0F3A.W1 18 /r ib
VINSERTF64X2 zmm1  {k1}{z}, zmm2, 
xmm3/m128, imm8B V/V AVX512DQ Insert 128 bits of packed double precision floating-
EVEX.512.66.0F3A.W0 1A /r ib
VINSERTF32X8 zmm1  {k1}{z}, zmm2, 
ymm3/m256, imm8D V/V AVX512DQ Insert 256 bits of packed single-precision floating-
point values from ymm3/m256 and the remaining 
EVEX.512.66.0F3A.W1 1A /r ib
VINSERTF64X4 zmm1  {k1}{z}, zmm2, 
ymm3/m256, imm8C V/V AVX512F Insert 256 bits of packed double precision floating-
point values from ymm3/m256 and the remaining values from zmm2 into zmm1 under writemask k1.
A N/A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8
BT u p l e 2 M o d R M : r e g  ( w )E V E X . vvvv (r) ModRM:r/m (r) imm8
CT u p l e 4 M o d R M : r e g  ( w )E V E X . vvvv (r) ModRM:r/m (r) imm8
DT u p l e 8 M o d R M : r e g  ( w )E V E X . vvvv (r) ModRM:r/m (r) imm8VINSERTF128/VINSERTF32x4/VINSERTF64x 2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-390 Vol. 2COperation
VINSERTF32x4 (EVEX encoded versions) 
(KL, VL) = (8, 256), (16, 512)TEMP_DEST[VL-1:0] := SRC1[VL-1:0]IF VL = 256
0: TMP_DEST[127:0] := SRC2[127:0]1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
00: TMP_DEST[127:0] := SRC2[127:0]01: TMP_DEST[255:128] := SRC2[127:0]10: TMP_DEST[383:256] := SRC2[127:0]11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI
FI;
VINSERTF64x2 (EVEX encoded versions) 
(KL, VL) = (4, 256), (8, 512)TEMP_DEST[VL-1:0] := SRC1[VL-1:0]IF VL = 256
ESAC.
ESAC.
THEN DEST[i+63:i] := TMP_DEST[i+63:i]ELSE VINSERTF128/VINSERTF32x4/VINSERTF64x 2/VINSERTF32x8/VINSERTF64x4—Insert  Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-391IF *merging-masking* ; merging-masking
FI
FI;
VINSERTF32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FI
FI;
VINSERTF64x4 (EVEX.512 encoded version) 
VL = 512TEMP_DEST[VL-1:0] := SRC1[VL-1:0]CASE (imm8[0]) OF
ESAC.
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VINSERTF128/VINSERTF32x4/VINSERTF64x 2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-392 Vol. 2CVINSERTF128 (VEX encoded version)
TEMP[255:0] := SRC1[255:0]CASE (imm8[0]) OF
0: TEMP[127:0] := SRC2[127:0]1: TEMP[255:128] := SRC2[127:0]
ESACDEST := TEMP
VINSERTF32x4 __m512 _mm512_insertf32x4( __m512 a, __m128 b, int imm);

FI
FI;
ESAC.
FI
FI;
VINSERTF32x4 __m512 _mm512_mask_insertf32x4(__m512 s, __mmask16 k, __m512 a, __m128 b, int imm);VINSERTF32x4 __m512 _mm512_maskz_insertf32x4( __mmask16 k, __m512 a, __m128 b, int imm);VINSERTF32x4 __m256 _mm256_insertf32x4( __m256 a, __m128 b, int imm);VINSERTF32x4 __m256 _mm256_mask_insertf32x4(__m256 s, __mmask8 k, __m256 a, __m128 b, int imm);VINSERTF32x4 __m256 _mm256_maskz_insertf32x4( __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x8 __m512 _mm512_insertf32x8( __m512 a, __m256 b, int imm);VINSERTF32x8 __m512 _mm512_mask_insertf32x8(__m512 s, __mmask16 k, __m512 a, __m256 b, int imm);VINSERTF32x8 __m512 _mm512_maskz_insertf32x8( __mmask16 k, __m512 a, __m256 b, int imm);VINSERTF64x2 __m512d _mm512_insertf64x2( __m512d a, __m128d b, int imm);VINSERTF64x2 __m512d _mm512_mask_insertf64x2(__m512d  s, __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_maskz_insertf64x2 ( __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_insertf64x2( __m256d a, __m128d b, int imm);VINSERTF64x2 __m256d _mm256_mask_insertf64x2(__m256d  s, __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_maskz_insertf64x2 ( __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x4 __m512d _mm512_insertf64x4( __m512d a, __m256d b, int imm);VINSERTF64x4 __m512d _mm512_mask_insertf64x4(__m512d  s, __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_maskz_insertf64x4 ( __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF128 __m256 _mm256_insertf128_ps (__m256 a, __m128 b, int offset);VINSERTF128 __m256d _mm256_insertf128_pd (__m256d a, __m128d b, int offset);VINSERTF128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);
None
VEX-encoded instruction, see Table 2-23,  “Type 6 Class Exception Conditions.”
#UD If VEX.L = 0.
EVEX-encoded instruction, see Table 2-54, “Type E6NF Class Exception Conditions.”VINSERTI128/VINSERTI32x4/VINSERTI 64x2/VINSERTI32x8/VINSERTI64x4—In sert Packed Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-393VINSERTI128/VINSERTI32x4/VI NSERTI64x2/VINSERTI32x8/VI NSERTI64x4—Insert Packed 
Integer Values
VINSERTI32x4 and VINSERTI64x2 inserts 128-bits of packed  integer values from the second source operand (the 
third operand) into the destination operand (the first operan d) at an 128-bit granular offset multiplied by imm8[0] 
(256-bit) or imm8[1:0]. The remaining portions of the dest ination are copied from the corresponding fields of the 
first source operand (the second operand). The second sour ce operand can be either an XMM register or a 128-bit 
memory location. The high 6/7bits of the immediate are ignored. The destination oper and is a ZMM/YMM register 
and updated at 32 and 64-bit gran ularity according to the writemask.
VINSERTI32x8 and VINSERTI64x4 inserts 256-bits of packed  integer values from the second source operand (the 
third operand) into the destination operand (the first oper and) at a 256-bit granular offset multiplied by imm8[0]. 
The remaining portions of the destination are copied from the corresponding fields of the first source operand (the 
second operand). The second source operand can be eith er an YMM register or a 256-bit memory location. The 
upper bits of the immediate are ignored. The destination operand is a ZMM register and updated at 32 and 64-bit granularity according to the writemask.
VINSERTI128 inserts 128-bits of packed integer data from the second source operand (the third operand) into the 
destination operand (the first operand) at a 128-bit granul ar offset multiplied by imm8 [0]. The remaining portions 
of the destination are copied from the corresponding fields  of the first source operand (the second operand). The Opcode/
En64/32 
Bit Mode 
Feature 
VEX.256.66.0F3A.W0 38 /r ib
VINSERTI128 ymm1, ymm2, 
xmm3/m128, imm8A V/V AVX2 Insert 128 bits of integer data from xmm3/m128 and 
the remaining values from ymm2 into ymm1.
EVEX.256.66.0F3A.W0 38 /r ib
VINSERTI32X4 ymm1 {k1}{z}, ymm2, 
xmm3/m128, imm8CV / V A V X 5 1 2 V L
AVX512FInsert 128 bits of packed doubleword integer values 
from xmm3/m128 and the remaining values from 
ymm2 into ymm1 under writemask k1.
EVEX.512.66.0F3A.W0 38 /r ib
VINSERTI32X4 zmm1 {k1}{z}, zmm2, xmm3/m128, imm8C V/V AVX512F Insert 128 bits of pa cked doubleword integer values 
from xmm3/m128 and the remaining values from zmm2 into zmm1 under writemask k1.
EVEX.256.66.0F3A.W1 38 /r ib
VINSERTI64X2 ymm1 {k1}{z}, ymm2, 
xmm3/m128, imm8BV / V A V X 5 1 2 V L
AVX512DQInsert 128 bits of packed quadword integer values 
EVEX.512.66.0F3A.W1 38 /r ib
VINSERTI64X2 zmm1 {k1}{z}, zmm2, 
xmm3/m128, imm8B V/V AVX512DQ Insert 128 bits of packed quadword integer values 
zmm2 into zmm1 under writemask k1.
EVEX.512.66.0F3A.W0 3A /r ib
VINSERTI32X8 zmm1 {k1}{z}, zmm2, 
ymm3/m256, imm8D V/V AVX512DQ Insert 256 bits of pa cked doubleword integer values 
from ymm3/m256 and the remaining values from 
EVEX.512.66.0F3A.W1 3A /r ib
VINSERTI64X4 zmm1 {k1}{z}, zmm2, ymm3/m256, imm8C V/V AVX512F Insert 256 bits of packed quadword integer values 
from ymm3/m256 and the remaining values from zmm2 into zmm1 under writemask k1.
BT u p l e 2 M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) imm8
CT u p l e 4M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) imm8
DT u p l e 8 M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) imm8VINSERTI128/VINSERTI32x4/ VINSERTI64x2/VINSERTI32x8/VINSERTI64x 4—Insert Packed Integer ValuesINSTRUCTION SET REFERENCE, V
5-394 Vol. 2Csecond source operand can be either an XMM register or a 128-bit memory location. The high 7 bits of the imme-
diate are ignored. VEX.L must be 1, otherwise attempt to execute this instruction with VEX.L=0 will cause #UD.
Operation
VINSERTI32x4 (EVEX encoded versions) 
ESAC.
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI
FI;
VINSERTI64x2 (EVEX encoded versions) 
ESAC.
ESAC.
i := j * 64VINSERTI128/VINSERTI32x4/VINSERTI 64x2/VINSERTI32x8/VINSERTI64x4—In sert Packed Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-395IF k1[j] OR *no writemask*
FI
FI;
VINSERTI32x8 (EVEX.U1.512 encoded version)
ESAC.
FI
FI;
VINSERTI64x4 (EVEX.512 encoded version) 
ESAC.
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VINSERTI128/VINSERTI32x4/ VINSERTI64x2/VINSERTI32x8/VINSERTI64x 4—Insert Packed Integer ValuesINSTRUCTION SET REFERENCE, V
5-396 Vol. 2CVINSERTI128
VINSERTI32x4 _mm512i _inserti32x4( __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _mask_inserti32x4(__m512i s,  __mmask16 k, __m512i a, __m128i b, int imm);

FI
FI;
ESAC.
FI
FI;
VINSERTI32x4 _mm512i _maskz_inserti32x4( __mmask16 k, __m512i a, __m128i b, int imm);VINSERTI32x4 __m256i _mm256_inserti32x4( __m256i a, __m128i b, int imm);VINSERTI32x4 __m256i _mm256_mask_inserti32x4(__m256i  s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_maskz_inserti32x4( __mmask8 k, __m256i a, __m128i b, int imm);VINSERTI32x8 __m512i _mm512_inserti32x8( __m512i a, __m256i b, int imm);VINSERTI32x8 __m512i _mm512_mask_inserti32x8(__m512i s, __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_maskz_inserti32x8( __mmask16 k, __m512i a, __m256i b, int imm);VINSERTI64x2 __m512i _mm512_inserti64x2( __m512i a, __m128i b, int imm);VINSERTI64x2 __m512i _mm512_mask_inserti64x2(__m512i  s, __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_maskz_inserti64x2( __mmask8 k, __m512i a, __m128i b, int imm);VINSERTI64x2 __m256i _mm256_inserti64x2( __m256i a, __m128i b, int imm);VINSERTI64x2 __m256i _mm256_mask_inserti64x2(__m256i  s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_maskz_inserti64x2( __mmask8 k, __m256i a, __m128i b, int imm);VINSERTI64x4 _mm512_inserti64x4( __ m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_mask_inserti64x4(__m512i s, __mmask8 k, __m512i a, __m256i b, int imm);VINSERTI64x4 _mm512_maskz_inserti64x4( __mmask m, __m512i a, __m256i b, int imm);VINSERTI128 __m256i _mm256_insertf128_si25 6 (__m256i a, __m128i b, int offset);
None.
EVEX-encoded instruction, see Table 2-54, “Type E6NF Class Exception Conditions.”VMASKMOV—Conditional SIMD Packed Loads and StoresINSTRUCTION SET REFERENCE, V
Vol. 2C 5-397VMASKMOV—Conditional SIMD Packed Loads and Stores
Conditionally moves packed data elements from the seco nd source operand into the corresponding data element 
of the destination operand, depending on the mask bits associated with each data element. The mask bits are 
specified in the first source operand. 
The mask bit for each data element is the most significant bi t of that element in the first source operand. If a mask 
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the 
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in 
the store form. 
The second source operand is a memory address for the load  form of these instruction. The destination operand is 
a memory address for the store form of these instruct ions. The other operands are both XMM registers (for 
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory acce sses that caused the faults. Faults will not occur due to 
referencing any memory location if th e corresponding mask bit for that memo ry location is 0. For example, no 
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and M ASKMOVDQU), a nontemporal hint is not applied to 
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits 
of all 1s.
VMASKMOV should not be used to access memory mapped I/O and un-cached memory as the access and the 
ordering of the individual loads or stores it does is implementation specific. Opcode/
En64/32-
Feature 
VEX.128.66.0F38.W0 2C /r
VMASKMOVPS xmm1, xmm2, m128RV
MV/V AVX Conditionally load packed single-precision values from 
m128 using mask in xmm2 and store in xmm1.
VEX.256.66.0F38.W0 2C /r
VMASKMOVPS ymm1, ymm2, m256RV
m256 using mask in ym m2 and store in ymm1.
VEX.128.66.0F38.W0 2D /r
VMASKMOVPD xmm1, xmm2, m128RV
MV/V AVX Conditionally load packed double precision values from 
VEX.256.66.0F38.W0 2D /r
VMASKMOVPD ym m1, ymm2, m256RV
VEX.128.66.0F38.W0 2E /r
VMASKMOVPS m128, xmm1, xmm2MV
RV/V AVX Conditionally store packed single-precision  values from 
xmm2 using mask in xmm1.
VEX.256.66.0F38.W0 2E /r
VMASKMOVPS m256, ymm1, ymm2MV
ymm2 using mask in ymm1.
VEX.128.66.0F38.W0 2F /r
VMASKMOVPD m128, xmm1, xmm2MV
RV/V AVX Conditionally store packed double precision values from 
VEX.256.66.0F38.W0 2F /r
VMASKMOVPD m256, ymm1, ymm2MV
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AMVR ModRM:r/m (w) VEX.vvvv (r) ModRM:reg (r) N/AVMASKMOV—Conditional SIMD Packed Loads and StoresINSTRUCTION SET REFERENCE, V
5-398 Vol. 2CIn cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-
mentation dependent way. However, A and D bits are alwa ys set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encode d in VEX.vvvv; the second source is encoded in rm_field, 
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encode d in VEX.vvvv; the second source register is encoded in 
reg_field, and the destination memory location is encoded in rm_field.
Operation
VMASKMOVPS -128-bit load 
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0 DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0 DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0 DEST[127:97] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0 DEST[MAXVL-1:128] := 0
VMASKMOVPS - 256-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0 DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0 DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0 DEST[127:96] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0 DEST[159:128] := IF (SRC1[159]) Load_32(mem + 16) ELSE 0 DEST[191:160] := IF (SRC1[191]) Load_32(mem + 20) ELSE 0 DEST[223:192] := IF (SRC1[223]) Load_32(mem + 24) ELSE 0 DEST[255:224] := IF (SRC1[255]) Load_32(mem + 28) ELSE 0 
VMASKMOVPD - 128-bit load 
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0 DEST[127:64] := IF (SRC1[127]) Load_64(mem + 16) ELSE 0DEST[MAXVL-1:128] := 0
VMASKMOVPD - 256-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0 DEST[127:64] := IF (SRC1[127]) Load_64(mem + 8) ELSE 0 DEST[195:128] := IF (SRC1[191]) Load_64(mem + 16) ELSE 0 DEST[255:196] := IF (SRC1[255]) Load_64(mem + 24) ELSE 0 
VMASKMOVPS - 128-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0] IF (SRC1[63]) DEST[63:32] := SRC2[63:32] IF (SRC1[95]) DEST[95:64] := SRC2[95:64] IF (SRC1[127]) DEST[127:96] := SRC2[127:96] 
VMASKMOVPS - 256-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0] IF (SRC1[63]) DEST[63:32] := SRC2[63:32] IF (SRC1[95]) DEST[95:64] := SRC2[95:64] IF (SRC1[127]) DEST[127:96] := SRC2[127:96] IF (SRC1[159]) DEST[159:128] :=SRC2[159:128] IF (SRC1[191]) DEST[191:160] := SRC2[191:160] IF (SRC1[223]) DEST[223:192] := SRC2[223:192] IF (SRC1[255]) DEST[255:224] := SRC2[255:224] VMASKMOV—Conditional SIMD Packed Loads and StoresINSTRUCTION SET REFERENCE, V
Vol. 2C 5-399VMASKMOVPD - 128-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0] IF (SRC1[127]) DEST[127:64] := SRC2[127:64] 
VMASKMOVPD - 256-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0] IF (SRC1[127]) DEST[127:64] := SRC2[127:64] IF (SRC1[191]) DEST[191:128] := SRC2[191:128] IF (SRC1[255]) DEST[255:192] := SRC2[255:192] 
__m256  _mm256_maskload_ps(float const *a, __m256i mask)
void    _mm256_maskstore_ps(float *a, __m256i mask, __m256 b)
__m256d _mm256_maskload_pd(double *a, __m256i mask);
void    _mm256_maskstore_pd(double *a, __m256i mask, __m256d b);
__m128 _mm_maskload_ps(float const *a, __m128i mask)void    _mm_maskstore_ps(flo at *a, __m128i mask, __m128 b)
__m128d _mm_maskload_pd(double const *a, __m128i mask);
void    _mm_maskstore_pd(doubl e *a, __m128i mask, __m128d b);
None.
See Table 2-23, “Type 6 Class Exception Conditions” (No AC# reported for any mask bit combinations).
#UD If VEX.W = 1.VMAXPH—Return Maximum of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-400 Vol. 2CVMAXPH—Return Maximum of Packed FP16 Values
This instruction performs a SIMD compare of the packed FP16 values in the first source operand and the second 
source operand and returns the maximum value for ea ch pair of values to the destination operand.
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that

None.
is, a QNaN version of the SNaN is not returned).
operand (from either the first or second operand) be re turned, the action of VMAXPH can be emulated using a 
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
broadcast from a 16-bit memory location. The destinat ion operand is a ZMM/YMM/XMM register conditionally 
Operation
def MAX(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
ELSE IF (SRC2 = NaN):
ELSE IF (SRC1 > SRC2):
DEST := SRC1
ELSE:
DEST := SRC2 Opcode/
En64/32 
bit Mode 
EVEX.128.NP.MAP5.W0 5F /r
VMAXPH xmm1{k1}{z}, xmm2, 
AVX512VLReturn the maximum packed FP16 values 
between xmm2 and xmm3/m128/m16bcst and 
EVEX.256.NP.MAP5.W0 5F /r
VMAXPH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcstA V/V AVX512-FP16 
between ymm2 and ymm3/m256/m16bcst and store the result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5F /r
VMAXPH zmm1{k 1}{z}, zmm2, 
zmm3/m512/m16bcst {sae}A V/V AVX512-FP16 Return the maximum packed FP16 values 
between zmm2 and zmm3/m512/m16bcst and 
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVMAXPH—Return Maximum of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-401VMAXPH dest, src1, src2
ELSE:
DEST.fp16[j] := MAX(SRC1.fp16[j], tsrc2)
VMAXPH __m128h _mm_mask_max_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMAXPH __m128h _mm_maskz_max_ph (__mmask8 k, __m128h a, __m128h b);VMAXPH __m128h _mm_max_ph (__m128h a, __m128h b);VMAXPH __m256h _mm256_mask_max_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);VMAXPH __m256h _mm256_maskz_max_ph (__mmask16 k, __m256h a, __m256h b);VMAXPH __m256h _mm256_max_ph (__m256h a, __m256h b);VMAXPH __m512h _mm512_mask_max_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);VMAXPH __m512h _mm512_maskz_max_ph (__mmask32 k, __m512h a, __m512h b);VMAXPH __m512h _mm512_max_ph (__m512h a, __m512h b);VMAXPH __m512h _mm512_mask_max_round_ph (__m512h sr c, __mmask32 k, __m512h a, __m512h b, int sae);
VMAXPH __m512h _mm512_maskz_max_round_ph (__mmask32 k, __m512h a, __m512h b, int sae);VMAXPH __m512h _mm512_max_round_ph (__m512h a, __m512h b, int sae);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VMAXSH—Return Maximum of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
5-402 Vol. 2CVMAXSH—Return Maximum of Scalar FP16 Values
This instruction performs a compare of the low packed FP16 values in the first source operand and the second source 
operand and returns the maximum value for the pair of values to the destination operand.
operand (from either the first or second operand) be re turned, the action of VMAXSH can be emulated using a 
sequence of instructions, such as, a comparison followed by AND, ANDN, and OR.
Operation
ELSE:
VMAXSH dest, src1, src2
DEST.fp16[0] := MAX(SRC1 .fp16[0], SRC2.fp16[0])
En64/32 
bit Mode 
EVEX.LLIG.F3.MAP5.W0 5F /r
VMAXSH xmm1{k1}{z}, xmm2, 
xmm3/m16 {sae}A V/V AVX512-FP16 Return the maximum low FP16 value between 
xmm3/m16 and xmm2 and store the result in 
xmm1 subject to writemask k1. Bits 127:16 of 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVMAXSH—Return Maximum of Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-403Intel C/C++ Compiler Intrinsic Equivalent
VMAXSH __m128h _mm_mask_max_round_sh (__m128h src,  __mmask8 k, __m128h a, __m128h b, int sae);
VMAXSH __m128h _mm_maskz_max_round_sh (__mmask8 k, __m128h a, __m128h b, int sae);VMAXSH __m128h _mm_max_round_sh ( __m128h a, __m128h b, int sae);
VMAXSH __m128h _mm_mask_max_sh (__m128h sr c, __mmask8 k, __m128h a, __m128h b);
VMAXSH __m128h _mm_maskz_max_sh ( __mmask8 k, __m128h a, __m128h b);
VMAXSH __m128h _mm_max_sh (__m128h a, __m128h b);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”VMINPH—Return Minimum of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-404 Vol. 2CVMINPH—Return Minimum of Packed FP16 Values
source operand and returns the minimum value for each pair of values to the destination operand.
operand (from either the first or second operand) be re turned, the action of VMINPH can be emulated using a 
Operation
def MIN(SRC1, SRC2):
ELSE IF (SRC1 < SRC2):
ELSE:
En64/32 
bit Mode 
EVEX.128.NP.MAP5.W0  5D /r
VMINPH xmm1{k1}{z}, xmm2, xmm3/
AVX512VLReturn the minimum packed  FP16 values between 
xmm2 and xmm3/m128/m16bcst and store the 
EVEX.256.NP.MAP5.W0  5D /r
VMINPH ymm1{k1}{z}, ymm2, ymm3/
ymm2 and ymm3/m256/m16bcst and store the result in ymm1 subj ect to writemask k1.
EVEX.512.NP.MAP5.W0  5D /r
VMINPH  zmm1{k1}{z},  zmm2,  zmm3/
m512/m16bcst  {sae}A V/V AVX512-FP16 Return the minimum packed FP16 values between 
zmm2 and zmm3/m512/m16bcst and store the 
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVMINPH—Return Minimum of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-405VMINPH dest, src1, src2
ELSE:
DEST.fp16[j] := MIN(SRC1.fp16[j], tsrc2)

ELSE:
VMINPH __m128h _mm_mask_min_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMINPH __m128h _mm_maskz_min_ph (__mmask8 k, __m128h a, __m128h b);VMINPH __m128h _mm_min_ph (__m128h a, __m128h b);VMINPH __m256h _mm256_mask_min_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);VMINPH __m256h _mm256_maskz_min_ph ( __mmask16 k, __m256h a, __m256h b);
VMINPH __m256h _mm256_min_ph (__m256h a, __m256h b);VMINPH __m512h _mm512_mask_min_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);VMINPH __m512h _mm512_maskz_min_ph ( __mmask32 k, __m512h a, __m512h b);
VMINPH __m512h _mm512_min_ph (__m512h a, __m512h b);VMINPH __m512h _mm512_mask_min_roun d_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int sae);
VMINPH __m512h _mm512_maskz_min_round_ph (__ mmask32 k, __m512h a, __m512h b, int sae);
VMINPH __m512h _mm512_min_round_ph (__m512h a, __m512h b, int sae);
EVEX-encoded instructions, see Table 2-46,  “Type E2 Class Exception Conditions.”VMINSH—Return Minimum Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
5-406 Vol. 2CVMINSH—Return Minimum Scalar FP16 Value
operand and returns the minimum value for the pair of values to the destination operand.
operand (from either the first or second operand) be re turned, the action of VMINSH can be emulated using a 
Operation
ELSE:
DEST := SRC2Opcode/
En64/32 
bit Mode 
EVEX.LLIG.F3.MAP5.W0 5D /r
VMINSH xmm1{k1}{z}, xmm2, xmm3/
m16 {sae}A V/V AVX512-FP16 Return the minimum low FP16 value between 
xmm3/m16 and xmm2. Stores the result in 
xmm1 subject to writemas k k1. Bits 127:16 of 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVMINSH—Return Minimum Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-407VMINSH dest, src1, src2 
DEST.fp16[0] := MIN(SRC1.fp16[0], SRC2.fp16[0])
VMINSH __m128h _mm_mask_min_round_sh (__m128h sr c, __mmask8 k, __m128h a,  __m128h b, int sae);
VMINSH __m128h _mm_maskz_min_round_sh (__m mask8 k, __m128h a, __m128h b, int sae);
VMINSH __m128h _mm_min_round_sh (__m128h a, __m128h b, int sae);VMINSH __m128h _mm_mask_min_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMINSH __m128h _mm_maskz_min_sh (__mmask8 k, __m128h a, __m128h b);VMINSH __m128h _mm_min_sh (__m128h a, __m128h b);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”VMOVSH—Move Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
5-408 Vol. 2CVMOVSH—Move Scalar FP16 Value
This instruction moves a FP16 value to a register or memory location.The two register-only forms are aliases and differ only in wher e their operands are encoded; this is a side effect of 
the encodings selected.
Operation
VMOVSH dest, src (two operand load)
IF k1[0] or no writemask:
DEST.fp16[0] := SRC.fp16[0]
// ELSE DEST.fp16[0] remains unchanged
DEST[MAXVL:16] := 0VMOVSH dest, src (two operand store)
// ELSE DEST.fp16[0] remains unchanged Opcode/
En64/32 
bit Mode 
EVEX.LLIG.F3.MAP5.W0  10 /r
VMOVSH xmm1{k1}{z}, m16A V/V AVX512-FP16 Move FP16 value from m16 to xmm1 subject to 
EVEX.LLIG.F3.MAP5.W0  11 /r
VMOVSH m16{k1}, xmm1B V/V AVX512-FP16 Move low FP16 va lue from xmm1 to m16 subject 
VMOVSH xmm1{k1}{z}, xmm2, xmm3C V/V AVX512-FP16 Move low FP16 values from xmm3 to xmm1 
subject to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].
VMOVSH xmm1{k1}{z}, xmm2, xmm3D V/V AVX512-FP16 Move low FP16 values from xmm3 to xmm1 
A Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
B Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/A
D N/A ModRM:r/m (w) VEX.vvvv (r) ModRM:reg (r) N/AVMOVSH—Move Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-409VMOVSH dest, src1, src2 (three operand copy)
DEST.fp16[0] := SRC2.fp16[0]
DEST[MAXVL:128] := 0 
VMOVSH __m128h _mm_load_sh (void const* mem_addr);
VMOVSH __m128h _mm_mask_load_sh (__m128h src, __mmask8 k, void const* mem_addr);VMOVSH __m128h _mm_maskz_load_sh (__mmask8 k, void const* mem_addr);VMOVSH __m128h _mm_mask_move_sh (__m128h  src, __mmask8 k, __m128h a, __m128h b);
VMOVSH __m128h _mm_maskz_move_sh (__mmask8 k, __m128h a, __m128h b);VMOVSH __m128h _mm_move_sh (__m128h a, __m128h b);VMOVSH void _mm_mask_store_sh (void * mem_addr, __mmask8 k, __m128h a);VMOVSH void _mm_store_sh (void * mem_addr, __m128h a);
None
EVEX-encoded instruction, see Table 2-51, “Type E5 Class Exception Conditions.”VMOVW—Move WordINSTRUCTION SET REFERENCE, V
5-410 Vol. 2CVMOVW—Move Word 
This instruction either (a) copies one word element from an XMM register to a general-purpose register or memory 
location or (b) copies one word element from a general-purpose register or memory location to an XMM register. 
When writing a general-purpose register, the lower 16-bits of the register will contain the word value. The upper bits 
of the general-purpose register are written with zeros.
Operation
VMOVW dest, src (two operand load)
DEST.word[0] := SRC.word[0]DEST[MAXVL:16] := 0 
VMOVW dest, src (two operand store)
DEST.word[0] := SRC.word[0]// upper bits of GPR DEST are zeroed 
VMOVW short _mm_cvtsi128_si16 (__m128i a);
VMOVW __m128i _mm_cvtsi16_si128 (short a);
None
EVEX-encoded instructions, see Table 2-57, “Type E9NF Class Exception Conditions.”Opcode/
En64/32 
bit Mode 
EVEX.128.66.MAP5.WIG  6E /r
VMOVW xmm1, reg/m16A V/V AVX512-FP16 Copy word from reg/m16 to xmm1.
EVEX.128.66.MAP5.WIG  7E /r
VMOVW reg/m16, xmm1B V/V AVX512-FP16 Copy word from xmm1 to reg/m16.
B Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AVMULPH—Multiply Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-411VMULPH—Multiply Packed FP16 Values
This instruction multiplies packed FP16 values from source operands and stores the packed FP16 result in the desti-
nation operand. The destination elements are updated according to the writemask.
Operation
VMULPH (EVEX encoded versions) when src2 operand is a register
ELSE
DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]

bit Mode 
Operation
ELSE
En64/32 
bit Mode 
EVEX.128.NP.MAP5.W0  59 /r
VMULPH xmm1{k1}{z}, xmm2, xmm3/
AVX512VLMultiply packed FP16 values from xmm3/m128/
m16bcst to xmm2 and stor e the result in xmm1 
EVEX.256.NP.MAP5.W0  59 /r
VMULPH ymm1{k1}{z}, ymm2, ymm3/
AVX512VLMultiply packed FP16 values from ymm3/m256/
m16bcst to ymm2 and stor e the result in ymm1 
EVEX.512.NP.MAP5.W0  59 /r
VMULPH  zmm1{k1}{z},  zmm2,  zmm3/
m512/m16bcst  {er}A V/V AVX512-FP16 Multiply packed FP16 values in zmm3/m512/
m16bcst with zmm2 and store the result in 
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVMULPH—Multiply Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-412 Vol. 2CVMULPH (EVEX encoded versions) when src2 operand is a memory source
DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[0]
ELSE:
VMULPH __m128h _mm_mask_mul_ph (__m128h sr c, __mmask8 k, __m128h a, __m128h b);
VMULPH __m128h _mm_maskz_mul_ph (_ _mmask8 k, __m128h a, __m128h b);
VMULPH __m128h _mm_mul_ph (__m128h a, __m128h b);VMULPH __m256h _mm256_mask_mul_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VMULPH __m256h _mm256_maskz_mul_ph (_ _mmask16 k, __m256h a, __m256h b);
VMULPH __m256h _mm256_mul_ph (__m256h a, __m256h b);VMULPH __m512h _mm512_mask_mul_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VMULPH __m512h _mm512_maskz_mul_ph (_ _mmask32 k, __m512h a, __m512h b);
VMULPH __m512h _mm512_mul_ph (__m512h a, __m512h b);VMULPH __m512h _mm512_mask_mul_round_ph (__m512h sr c, __mmask32 k, __m512h a, __m512h b, int rounding);
VMULPH __m512h _mm512_maskz_mul_round_ph (__mma sk32 k, __m512h a, __m512h b, int rounding);
VMULPH __m512h _mm512_mul_round_ph (_ _m512h a, __m512h b, int rounding);
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”VMULSH—Multiply Scalar FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-413VMULSH—Multiply Scalar FP16 Values
This instruction multiplies the low FP16 value from the so urce operands and stores the FP16 result in the destina-
tion operand. Bits 127:16 of the destination operand are copied from the corresponding bits of the first source 
operand. Bits MAXVL-1:128 of the destination operand ar e zeroed. The low FP16 element of the destination is 
Operation
VMULSH (EVEX encoded versions)
ELSE
DEST.fp16[0] := SRC1.fp16[0] * SRC2.fp16[0]
VMULSH __m128h _mm_mask_mul_round_s h (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);
VMULSH __m128h _mm_maskz_mul_round_sh (__mma sk8 k, __m128h a, __m128h b, int rounding);
VMULSH __m128h _mm_mul_round_sh (__m128h a, __m128h b, int rounding);VMULSH __m128h _mm_mask_mul_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMULSH __m128h _mm_maskz_mul_sh ( __mmask8 k, __m128h a, __m128h b);
VMULSH __m128h _mm_mul_sh (__m128h a, __m128h b);
En64/32 
bit Mode 
EVEX.LLIG.F3.MAP5.W0 59 /r
VMULSH xmm1{k1}{z}, xmm2, 
xmm3/m16 {er}A V/V AVX512-FP16 Multiply the low FP 16 value in xmm3/m16 by low 
FP16 value in xmm2, and store the result in 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVP2INTERSECTD/VP2INTERSECTQ—Compute Intersection Betw een DWORDS/QUADWORDS to a Pair of Mask RegistersINSTRUCTION SET REFERENCE, V
5-414 Vol. 2CVP2INTERSECTD/VP2INTERSECTQ—Compute Inters ection Between DWORDS/QUADWORDS to a 
Pair of Mask Registers 
This instruction writes an even/odd pair of mask regi sters. The mask register destination indicated in the 
MODRM.REG field is used to form the basis of the register pa ir. The low bit of that field is masked off (set to zero) 
to create the first register of the pair.
EVEX.aaa and EVEX.z must be zero.Opcode/
En64/32 
bit Mode 
SupportCPUID Feature Flag Description
EVEX.NDS.128.F2.0F38.W0 68 /r 
VP2INTERSECTD k1+1, xmm2, 
xmm3/m128/m32bcstAV / V A V X 5 1 2 V L
AVX512_VP2INTERSECTStore, in an even/odd pa ir of mask registers, 
the indicators of th e locations of value 
matches between dwords in xmm3/m128/m32bcst and xmm2.
EVEX.NDS.256.F2.0F38.W0 68 /r
VP2INTERSECTD k1+1, ymm2, 
ymm3/m256/m32bcstAV / V A V X 5 1 2 V L
matches between dwords in ymm3/m256/m32bcst and ymm2.
EVEX.NDS.512.F2.0F38.W0 68 /r
VP2INTERSECTD k1+1, zmm2, 
zmm3/m512/m32bcstAV / V A V X 5 1 2 F
matches between dwords in 
zmm3/m512/m32bcst and zmm2.
EVEX.NDS.128.F2.0F38.W1 68 /r
VP2INTERSECTQ k1+1, xmm2, xmm3/m128/m64bcstAV / V A V X 5 1 2 V L
matches between quadwords in 
xmm3/m128/m64bcst and xmm2.
EVEX.NDS.256.F2.0F38.W1 68 /r
VP2INTERSECTQ k1+1, ymm2, ymm3/m256/m64bcstAV / V A V X 5 1 2 V L
ymm3/m256/m64bcst and ymm2.
EVEX.NDS.512.F2.0F38.W1 68 /r
VP2INTERSECTQ k1+1, zmm2, zmm3/m512/m64bcstAV / V A V X 5 1 2 F
zmm3/m512/m64bcst and zmm2.
A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVP2INTERSECTD/VP2INTERSECTQ—Compute Intersection Between DWORDS/QUADWOR DS to a Pair of Mask RegistersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-415Operation
VP2INTERSECTD destmask, src1, src2
// dest_mask_reg_id is the register id specified in the instruction for destmask
dest_base := dest_mask_reg_id & ~1
// maskregs[ ] is an array representing the mask registers
maskregs[dest_base +0][MAX_KL-1:0] := 0
maskregs[dest_base +1][MAX_KL-1:0] := 0
FOR j := 0 to KL-1:
match := (src1.dword[i] == src2.dword[j])
maskregs[dest_base+0].bit[i] |= matchmaskregs[dest_base+1].bit[j] |= match
VP2INTERSECTQ destmask, src1, src2
dest_base 
:= dest_mask_reg_id & ~1
FOR j = 0 to KL-1:
match := (src1.qword[i] == src2.qword[j])
maskregs[dest_base+0].bit[i] |=  matchmaskregs[dest_base+1].bit[j] |=  match
VP2INTERSECTD void _mm_2intersect_epi32(__ m128i, __m128i, __mmask8 *, __mmask8 *);
VP2INTERSECTD void _mm256_2intersect_epi32( __m256i, __m256i, __mmask8 *, __mmask8 *);
VP2INTERSECTD void _mm512_2intersect_epi32( __m512i, __m512i, __mmask16 *, __mmask16 *);
VP2INTERSECTQ void _mm_2intersect_epi64( __m128i, __m128i, __mmask8 *, __mmask8 *);
VP2INTERSECTQ void _mm256_2intersect_epi64 (__m256i, __m256i, __mma sk8 *, __mmask8 *);
VP2INTERSECTQ void _mm512_2intersect_epi64 (__m512i, __m512i, __mma sk8 *, __mmask8 *);
None.
See Table 2-50, “Type E4NF Class Exception Conditions.”VPBLENDD—Blend Packed DwordsINSTRUCTION SET REFERENCE, V
5-416 Vol. 2CVPBLENDD—Blend Packed Dwords
Dword elements from the source operand (second operand)  are conditionally written to the destination operand 
(first operand) depending on bits in the immediate operan d (third operand). The immediate bits (bits 7:0) form a

None.
(first operand) depending on bits in the immediate operan d (third operand). The immediate bits (bits 7:0) form a 
mask that determines whether the corresponding dword in th e destination is copied from the source. If a bit in the 
mask, corresponding to a dword, is “1", then th e dword is copied, else the dword is unchanged.
first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register 
Operation
VPBLENDD (VEX.256 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] := SRC2[31:0]ELSE DEST[31:0] := SRC1[31:0]IF (imm8[1] == 1) THEN DE ST[63:32] := SRC2[63:32]
ELSE DEST[63:32] := SRC1[63:32]IF (imm8[2] == 1) THEN DE ST[95:64] := SRC2[95:64]
ELSE DEST[95:64] := SRC1[95:64]IF (imm8[3] == 1) THEN DEST[127:96] := SRC2[127:96]ELSE DEST[127:96] := SRC1[127:96]IF (imm8[4] == 1) THEN DEST[159:128] := SRC2[159:128]ELSE DEST[159:128] := SRC1[159:128]IF (imm8[5] == 1) THEN DEST[191:160] := SRC2[191:160]ELSE DEST[191:160] := SRC1[191:160]IF (imm8[6] == 1) THEN DEST[223:192] := SRC2[223:192]ELSE DEST[223:192] := SRC1[223:192]IF (imm8[7] == 1) THEN DEST[255:224] := SRC2[255:224]ELSE DEST[255:224] := SRC1[255:224]Opcode/
En64/32
-bit ModeCPUID 
VEX.128.66.0F3A.W0 02 /r ib
VPBLENDD xmm1, xmm2, xmm3/m128, imm8RVMI V/V AVX2 Select dwords from xmm2 and xmm3/m128 from 
xmm1.
VEX.256.66.0F3A.W0 02 /r ib
VPBLENDD ymm1, ymm2, ymm3/m256, imm8RVMI V/V AVX2 Select dwords from ymm2 and ymm3/m256 from 
ymm1.
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8VPBLENDD—Blend Packed DwordsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-417VPBLENDD (VEX.128 encoded version)
ELSE DEST[95:64] := SRC1[95:64]IF (imm8[3] == 1) THEN DEST[127:96] := SRC2[127:96]ELSE DEST[127:96] := SRC1[127:96]DEST[MAXVL-1:128] := 0
VPBLENDD: __m128i _mm_blend_epi32 (__m128i v1, __m128i v2, const int mask)
VPBLENDD: __m256i _mm256_blend_epi32 ( __m256i v1, __m256i v2, const int mask)
None.
#UD If VEX.W = 1.VPBLENDMB/VPBLENDMW—Blend Byte/Wor d Vectors Using an Opmask ControlINSTRUCTION SET REFERENCE, V
5-418 Vol. 2CVPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control
Performs an element-by-element blendi ng of byte/word elements between th e first source operand byte vector 
register and the second source operand byte vector fr om memory or register, using the instruction mask as 
selector. The result is written into the destination byte vector register.
ZMM/YMM/XMM register, a 512/256/128-bit memory lo cation or a 512/256/128-bit memory location.
The mask is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every 
element of the destination is conditiona lly selected between first source or second source using the value of the 
related mask bit (0 for first source, 1 for second source).Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 66 /r
VPBLENDMB xmm1 {k1}{z}, 
xmm2, xmm3/m128A V/V AVX512VL
AVX512BWBlend byte integer vector xmm2 and byte vector 
xmm3/m128 and store the result in xmm1, under control 
mask.
EVEX.256.66.0F38.W0 66 /r 
VPBLENDMB ymm1 {k1}{z}, ymm2, ymm3/m256A V/V AVX512VL
AVX512BWBlend byte integer vector ymm2 and byte vector 
ymm3/m256 and store the result in ymm1, under control mask.
EVEX.512.66.0F38.W0 66 /r
VPBLENDMB zmm1 {k1}{z}, 
zmm2, zmm3/m512A V/V AVX512BW Blend byte integer vector zmm2 and byte vector 
zmm3/m512 and store the result in zmm1, under control 
mask.
EVEX.128.66.0F38.W1 66 /r
VPBLENDMW xmm1 {k1}{z}, 
AVX512BWBlend word integer vector xmm2 and word vector 
mask.
EVEX.256.66.0F38.W1 66 /r
VPBLENDMW ymm1 {k1}{z}, 
ymm2, ymm3/m256A V/V AVX512VL
AVX512BWBlend word integer vector  ymm2 and word vector 
ymm3/m256 and store the result in ymm1, under control 
mask.
EVEX.512.66.0F38.W1 66 /r
VPBLENDMW zmm1 {k1}{z}, zmm2, zmm3/m512A V/V AVX512BW Blend word integer vector zmm2 and word vector 
zmm3/m512 and store the result in zmm1, under control mask.
A Full Mem ModRM:reg (w) EVEX. vvvv (r) ModRM:r/m (r) N/AVPBLENDMB/VPBLENDMW—Blend Byte/Wor d Vectors Using an Opmask ControlINSTRUCTION SET REFERENCE, V
Vol. 2C 5-419Operation
VPBLENDMB (EVEX encoded versions)
THEN DEST[i+7:i] := SRC2[i+7:i]
ELSE 
THEN DEST[i+7:i] := SRC1[i+7:i]
FI;
FI;
VPBLENDMW (EVEX encoded versions)
THEN DEST[i+15:i] := SRC2[i+15:i]ELSE 
THEN DEST[i+15:i] := SRC1[i+15:i]ELSE ; zeroing-masking
FI;
FI;
VPBLENDMB __m512i _mm512_mask_blend_epi8 (__mmask64 m, __m512i a, __m512i b);
VPBLENDMB __m256i _mm256_mask_blend_epi8 (__mmask32 m, __m256i a, __m256i b);
VPBLENDMB __m128i _mm_mask _blend_epi8(__mmask16 m, __m128i a, __m128i b);
VPBLENDMW __m512i _mm512_mask_blend_epi1 6(__mmask32 m, __m512i a, __m512i b);
VPBLENDMW __m256i _mm256_mask_blend_epi1 6(__mmask16 m, __m256i a, __m256i b);
VPBLENDMW __m128i _mm_mask_blend_epi16 (__mmask8 m, __m128i a, __m128i b);
None
See Table 2-49, “Type E4 Class Exception Conditions.”VPBLENDMD/VPBLENDMQ—Blend Int32/Int 64 Vectors Using an OpMask ControlINSTRUCTION SET REFERENCE, V
5-420 Vol. 2CVPBLENDMD/VPBLENDMQ—Blend  Int32/Int64 Vectors Using an OpMask Control
Performs an element-by-element blending of dword/qword elements between the first source operand (the second 
operand) and the elements of the second source operand (t he third operand) using an opmask register as select 
control. The blended result is written into the destination. 
The destination and first source operands are ZMM registers. The second source operand can be a ZMM register, a 
512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location.
value of the related mask bit (0 for the first so urce operand, 1 for the second source operand).
If EVEX.z is set, the elements with corresponding mask  bit value of 0 in the destination operand are zeroed.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 64 /r 
VPBLENDMD xmm1 {k1}{z}, 
AVX512FBlend doubleword integer vector xmm2 and doubleword 
vector xmm3/m128/m32bcst and store the result in 
xmm1, under control mask.
EVEX.256.66.0F38.W0 64 /r 
VPBLENDMD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstA V/V AVX512VL
AVX512FBlend doubleword integer vector ymm2 and doubleword 
vector ymm3/m256/m32bcst and store the result in ymm1, under control mask.
EVEX.512.66.0F38.W0 64 /r 
VPBLENDMD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstA V/V AVX512F Blend doubleword integer vector zmm2 and doubleword 
vector zmm3/m512/m32bcst and store the result in 
zmm1, under control mask.
EVEX.128.66.0F38.W1 64 /r
VPBLENDMQ xmm1 {k1}{z}, 
AVX512FBlend quadword integer ve ctor xmm2 and quadword 
vector xmm3/m128/m64bcst and store the result in 
EVEX.256.66.0F38.W1 64 /r
VPBLENDMQ ymm1 {k1}{z}, 
ymm2, ymm3/m256/m64bcstA V/V AVX512VL
AVX512FBlend quadword integer ve ctor ymm2 and quadword 
vector ymm3/m256/m64bcst and store the result in 
ymm1, under control mask.
EVEX.512.66.0F38.W1 64 /r
VPBLENDMQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstA V/V AVX512F Blend quadword integer vector zmm2 and quadword 
vector zmm3/m512/m64bcst and store the result in 

A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPBLENDMD/VPBLENDMQ—Blend Int32/Int 64 Vectors Using an OpMask ControlINSTRUCTION SET REFERENCE, V
Vol. 2C 5-421Operation
VPBLENDMD (EVEX encoded versions)
THEN
THEN
ELSE 
FI;
ELSE 
FI;
FI;
THEN
THEN
ELSE 
FI;
ELSE 
FI;
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPBLENDMD/VPBLENDMQ—Blend Int32/Int 64 Vectors Using an OpMask ControlINSTRUCTION SET REFERENCE, V
5-422 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPBLENDMD __m512i _mm512_mask_blend_epi32(__mmask16 k, __m512i a, __m512i b);
VPBLENDMD __m256i _mm256_mask_blend_epi 32(__mmask8 m, __m256i a, __m256i b);
VPBLENDMD __m128i _mm_mask_blend_epi32( __mmask8 m, __m128i a, __m128i b);
VPBLENDMQ __m512i _mm512_mask_blend_epi64(__mmask8 k, __m512i a, __m512i b);VPBLENDMQ __m256i _mm256_mask_blend_epi64(__mmask8 m, __m256i a, __m256i b);VPBLENDMQ __m128i _mm_mask_blend_epi64 (__mmask8 m, __m128i a, __m128i b);
None
See Table 2-49, “Type E4 Class Exception Conditions.”VPBROADCASTB/W/D/Q—Load With Broadcast In teger Data From General Purpose RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-423VPBROADCASTB/W/D/Q—Load With Broadcast In teger Data From Gene ral Purpose Register
Broadcasts a 8-bit, 16-bit, 32-bit or 64-bit value from a general-purpose register (the second operand) to all the 
locations in the destination vector register (the first operand) using the writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/
En64/32 
bit 
Feature 
EVEX.128.66.0F38.W0 7A /r
VPBROADCASTB xmm1 {k1}{z}, regAV / V A V X 5 1 2 V L
AVX512BWBroadcast an 8-bit value from  a GPR to all bytes in the 
128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W0 7A /r
VPBROADCASTB ymm1 {k1}{z}, regAV / V A V X 5 1 2 V L
256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W0 7A /r
VPBROADCASTB zmm1 {k1}{z}, regA V/V AVX512BW Broadcast an 8-bit valu e from a GPR to all bytes in the 
512-bit destination subject to writemask k1.
EVEX.128.66.0F38.W0 7B /r
VPBROADCASTW xmm1 {k1}{z}, regAV / V A V X 5 1 2 V L
AVX512BWBroadcast a 16-bit value from a GPR to all words in the 
EVEX.256.66.0F38.W0 7B /r
VPBROADCASTW ymm1 {k1}{z}, regAV / V A V X 5 1 2 V L
EVEX.512.66.0F38.W0 7B /r
VPBROADCASTW zmm1 {k1}{z}, regA V/V AVX512BW Broadcast a 16-bit valu e from a GPR to all words in the 
EVEX.128.66.0F38.W0 7C /r
VPBROADCASTD xmm1 {k1}{z}, r32AV / V A V X 5 1 2 V L
AVX512FBroadcast a 32-bit value from  a GPR to all doublewords 
in the 128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W0 7C /r
VPBROADCASTD ymm1 {k1}{z}, r32AV / V A V X 5 1 2 V L
in the 256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W0 7C /r
VPBROADCASTD zmm1 {k1}{z}, r32A V/V AVX512F Broadcast a 32-bit valu e from a GPR to all doublewords 
in the 512-bit destination subject to writemask k1.
EVEX.128.66.0F38.W1 7C /r
VPBROADCASTQ xmm1 {k1}{z}, r64AV / N . E .1AVX512VL
AVX512FBroadcast a 64-bit value from a GPR to all quadwords in 
the 128-bit destination su bject to writemask k1.
EVEX.256.66.0F38.W1 7C /r
VPBROADCASTQ ymm1 {k1}{z}, r64AV / N . E .1AVX512VL
the 256-bit destination su bject to writemask k1.
EVEX.512.66.0F38.W1 7C /r
VPBROADCASTQ zmm1 {k1}{z}, r64AV / N . E .1
NOTES:
1. EVEX.W in non-64 bit is ig nored; the instruction behaves as if the W0 version is used.AVX512F Broadcast a 64-bit value from a GPR to all quadwords in 
the 512-bit destination su bject to writemask k1.
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVPBROADCASTB/W/D/Q—Load With Broadcast In teger Data From General Purpose RegisterINSTRUCTION SET REFERENCE, V
5-424 Vol. 2COperation
VPBROADCASTB (EVEX encoded versions)
THEN DEST[i+7:i] := SRC[7:0]ELSE 
FI
FI;
VPBROADCASTW (EVEX encoded versions)
THEN DEST[i+15:i] := SRC[15:0]ELSE 
FI
FI;
VPBROADCASTD (EVEX encoded versions)
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPBROADCASTB/W/D/Q—Load With Broadcast In teger Data From General Purpose RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-425VPBROADCASTQ (EVEX encoded versions)
FI
FI;
VPBROADCASTB __m512i _mm512_mask_set1_e pi8(__m512i s, __mmask64 k, int a);
VPBROADCASTB __m512i _mm512_maskz_set1_epi8( __mmask64 k, int a);VPBROADCASTB __m256i _mm256_mask_set1_e pi8(__m256i s, __mmask32 k, int a);
VPBROADCASTB __m256i _mm256_maskz_set1_epi8( __mmask32 k, int a);VPBROADCASTB __m128i _mm_mask_set1_ep i8(__m128i s, __mmask16 k, int a);
VPBROADCASTB __m128i _mm_maskz_se t1_epi8( __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_mask_set1_epi 32(__m512i s, __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_maskz_s et1_epi32( __mmask16 k, int a);
VPBROADCASTD __m256i _mm256_mask_set1_e pi32(__m256i s, __m mask8 k, int a);
VPBROADCASTD __m256i _mm256_maskz_s et1_epi32( __mmask8 k, int a);
VPBROADCASTD __m128i _mm_mask_set1_ep i32(__m128i s, __mmask8 k, int a);
VPBROADCASTD __m128i _mm_maskz_se t1_epi32( __mmask8 k, int a);
VPBROADCASTQ __m512i _mm512_mask_set1_e pi64(__m512i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m512i _mm512_maskz_s et1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_mask_set1_e pi64(__m256i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_maskz_s et1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_mask_set1_ep i64(__m128i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_maskz_set1_epi64( __mmask8 k, __int64 a);VPBROADCASTW __m512i _mm512_mask_set1 _epi16(__m512i s, __ mmask32 k, int a);
VPBROADCASTW __m512i _mm512_maskz_s et1_epi16( __mmask32 k, int a);
VPBROADCASTW __m256i _mm256_mask_set1 _epi16(__m256i s, __ mmask16 k, int a);
VPBROADCASTW __m256i _mm256_maskz_s et1_epi16( __mmask16 k, int a);
VPBROADCASTW __m128i _mm_mask_set1_ epi16(__m128i s, __mmask8 k, int a);
VPBROADCASTW __m128i _mm_maskz_ set1_epi16( __mmask8 k, int a);
EVEX-encoded instructions, see Table 2-55,  “Type E7NM Class Exception Conditions.”
Additionally:#UD If EVEX.vvvv != 1111B.VPBROADCAST—Load Integer and BroadcastINSTRUCTION SET REFERENCE, V
5-426 Vol. 2CVPBROADCAST—Load Integer and Broadcast
Opcode/
En64/32 
bit Mode 
Feature 
VEX.128.66.0F38.W0 78 /r
VPBROADCASTB xmm1, xmm2/m8A V/V AVX2 Broadcast a byte integer in the source operand 
to sixteen loca tions in xmm1.
VEX.256.66.0F38.W0 78 /r
VPBROADCASTB ymm1, xmm2/m8A V/V AVX2 Broadcast a byte integer in the source operand 
to thirty-two locations in ymm1.
EVEX.128.66.0F38.W0 78 /r
VPBROADCASTB xmm1{k1}{z}, xmm2/m8B V/V AVX512VL
AVX512BWBroadcast a byte integer in the source operand 
to locations in xmm1 su bject to writemask k1.
EVEX.256.66.0F38.W0 78 /r
VPBROADCASTB ymm1{k1}{z}, xmm2/m8B V/V AVX512VL
AVX512BWBroadcast a byte integer in the source operand

Opcode/
En64/32 
bit Mode 
Feature 
to locations in ymm1 su bject to writemask k1.
EVEX.512.66.0F38.W0 78 /r
VPBROADCASTB zmm1{k1}{z}, xmm2/m8B V/V AVX512BW Broadcast a byte integer in the source operand 
to 64 locations in zmm1  subject to writemask 
k1.
VEX.128.66.0F38.W0 79 /r
VPBROADCASTW xmm1, xmm2/m16AV / V A V X 2 B r o a d c a s t  a  w o r d  integer in the source 
operand to eight lo cations in xmm1.
VEX.256.66.0F38.W0 79 /r
VPBROADCASTW ymm1, xmm2/m16AV / V A V X 2 B r o a d c a s t  a  w o r d  integer in the source 
operand to sixteen locations in ymm1.
EVEX.128.66.0F38.W0 79 /r
VPBROADCASTW xmm1{k1}{z}, xmm2/m16B V/V AVX512VL
AVX512BWBroadcast a word inte ger in the source 
operand to locations in xmm1 subject to 
EVEX.256.66.0F38.W0 79 /r
VPBROADCASTW ymm1 {k1}{z}, xmm2/m16B V/V AVX512VL
operand to locations in ymm1 subject to 
EVEX.512.66.0F38.W0 79 /r
VPBROADCASTW zmm1{k1}{z}, xmm2/m16B V/V AVX512BW Broadcast a word integer in the source 
operand to 32 location s in zmm1 subject to 
VEX.128.66.0F38.W0 58 /r
VPBROADCASTD xmm1, xmm2/m32A V/V AVX2 Broadcast a dword integer in the source 
operand to four lo cations in xmm1.
VEX.256.66.0F38.W0 58 /r
VPBROADCASTD ymm1, xmm2/m32A V/V AVX2 Broadcast a dword integer in the source 
operand to eight lo cations in ymm1.
EVEX.128.66.0F38.W0 58 /r
VPBROADCASTD xmm1 {k1}{z}, xmm2/m32B V/V AVX512VL
AVX512FBroadcast a dword inte ger in the source 
EVEX.256.66.0F38.W0 58 /r
VPBROADCASTD ymm1 {k1}{z}, xmm2/m32B V/V AVX512VL
EVEX.512.66.0F38.W0 58 /r
VPBROADCASTD zmm1 {k1}{z}, xmm2/m32B V/V AVX512F Broadcast a dwor d integer in the source 
operand to locations in zmm1 subject to 
VEX.128.66.0F38.W0 59 /r
VPBROADCASTQ xmm1, xmm2/m64A V/V AVX2 Broadcast a qword element in source operand 
to two locations in xmm1.
VEX.256.66.0F38.W0 59 /r
VPBROADCASTQ ymm1, xmm2/m64A V/V AVX2 Broadcast a qword element in source operand 
to four locations in ymm1.
EVEX.128.66.0F38.W1 59 /r
VPBROADCASTQ xmm1 {k1}{z}, xmm2/m64B V/V AVX512VL
AVX512FBroadcast a qword element in source operand 
EVEX.256.66.0F38.W1 59 /r
VPBROADCASTQ ymm1 {k1}{z}, xmm2/m64B V/V AVX512VL
EVEX.512.66.0F38.W1 59 /r
VPBROADCASTQ zmm1 {k1}{z}, xmm2/m64B V/V AVX512F Broadcast a qword element in source operand 
to locations in zmm1 su bject to writemask k1.VPBROADCAST—Load Integer and BroadcastINSTRUCTION SET REFERENCE, V
Vol. 2C 5-427Instruction Operand Encoding
Load integer data from the source operand (the second op erand) and broadcast to all elements of the destination 
operand (the first operand).
VEX256-encoded VPBROADCASTB/W/D/Q: The source operand is  8-bit, 16-bit, 32-bit, 64-bit memory location or 
the low 8-bit, 16-bit 32-bit, 64-bit data in an XMM re gister. The destination operand is a YMM register. VPBROAD-
CASTI128 support the source operand of 128-bit memory location. Register source encodings for VPBROADCAS-
TI128 is reserved and will #UD. Bits (MAXVL-1:256) of the destination register are zeroed.EVEX.128.66.0F38.W0 59 /r
VBROADCASTI32x2 xmm1 {k1}{z}, xmm2/m64CV / V A V X 5 1 2 V L
AVX512DQBroadcast two dword elements in source 
EVEX.256.66.0F38.W0 59 /r
VBROADCASTI32x2 ymm1 {k1}{z}, xmm2/m64CV / V A V X 5 1 2 V L
EVEX.512.66.0F38.W0 59 /r
VBROADCASTI32x2 zmm1  {k1}{z}, xmm2/m64C V/V AVX512DQ Broadcast two dword elements in source 
VEX.256.66.0F38.W0 5A /r
VBROADCASTI128 ymm1, m128A V/V AVX2 Broadcast 128 bits of integer data in mem to 
EVEX.256.66.0F38.W0 5A /r
VBROADCASTI32X4 ymm1 {k1}{z}, m128DV / V A V X 5 1 2 V L
AVX512FBroadcast 128 bits of 4 doubleword integer 
data in mem to loca tions in ymm1 using 
EVEX.512.66.0F38.W0 5A /r
VBROADCASTI32X4 zmm1 {k1}{z}, m128D V/V AVX512F Broadcast 128 bits of 4 doubleword integer 
data in mem to loca tions in zmm1 using 
EVEX.256.66.0F38.W1 5A /r
VBROADCASTI64X2 ymm1 {k1}{z}, m128CV / V A V X 5 1 2 V L
AVX512DQBroadcast 128 bits of 2 quadword integer data 
in mem to locations in ymm1 using writemask 
k1.
EVEX.512.66.0F38.W1 5A /r
VBROADCASTI64X2 zmm1 {k1}{z}, m128C V/V AVX512DQ Broadcast 128 bits of 2 quadword integer data 
in mem to locations in zmm1 using writemask k1.
EVEX.512.66.0F38.W0 5B /r
VBROADCASTI32X8 zmm1 {k1}{z}, m256E V/V AVX512DQ Broadcast 256 bits of 8 doubleword integer 
EVEX.512.66.0F38.W1 5B /r
VBROADCASTI64X4 zmm1 {k1}{z}, m256D V/V AVX512F Broadcast 256 bits of 4 quadword integer data 
in mem to locations in zmm1 using writemask 
k1.
En64/32 
bit Mode 
Feature 
FlagDescriptionVPBROADCAST—Load Integer and BroadcastINSTRUCTION SET REFERENCE, V
5-428 Vol. 2CEVEX-encoded VPBROADCASTD/Q: The source operand is a 32- bit, 64-bit memory location or the low 32-bit, 64-
bit data in an XMM register. The destination operand is a ZMM/YMM/XMM register and updated according to the writemask k1. 
VPBROADCASTI32X4 and VPBROADCASTI64X4:  The destination operand is a ZMM register and updated according 
to the writemask k1. The source operand is 128-bit or 256-bit memory location. Register source encodings for 
VBROADCASTI32X4 and VBROADCASTI64X4 are reserved and will #UD.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.If VPBROADCASTI128 is encoded with VEX.L= 0, an attemp t to execute the instruction encoded with VEX.L= 0 will 
Figure 5-16.  VPBROADCASTD Oper ation (VEX.256 encoded version)
Figure 5-17.  VPBROADCASTD Operation (128 -bit version)
Figure 5-18.  VPBROADCASTQ Operation (256-bit version)DESTm32 X0
DESTm32 X0
DESTm64 X0
X0 X0 X0 X0VPBROADCAST—Load Integer and BroadcastINSTRUCTION SET REFERENCE, V
Vol. 2C 5-429Operation
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0Figure 5-19.  VBROADCASTI128  Operation (256 -bit version)
Figure 5-20.  VBROADCASTI256  Operation (512 -bit version)DESTm128 X0
X0 X0
DESTm256 X0
X0 X0VPBROADCAST—Load Integer and BroadcastINSTRUCTION SET REFERENCE, V
5-430 Vol. 2CVPBROADCASTW (EVEX encoded versions)
FI
FI;
VPBROADCASTD (128 bit version)
VPBROADCASTD (VEX.256 encoded version)
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPBROADCAST—Load Integer and BroadcastINSTRUCTION SET REFERENCE, V
Vol. 2C 5-431VPBROADCASTQ (VEX.256 encoded version)
VPBROADCASTQ (EVEX encoded versions)
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VBROADCASTI32x2 (EVEX encoded versions)(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1
THEN DEST[i+31:i] := SRC[n+31:n]ELSE

FI
FI;
FI
FI;
FI
FI;
VBROADCASTI128 (VEX. 256 encoded version)
temp := SRC[127:0]DEST[127:0] := tempDEST[255:128] := tempDEST[MAXVL-1:256] := 0VPBROADCAST—Load Integer and BroadcastINSTRUCTION SET REFERENCE, V
5-432 Vol. 2CVBROADCASTI32X4 (EVEX encoded versions)
FI
FI;
VBROADCASTI64X2 (EVEX encoded versions)
FI
FI;
ENDFOR;
VBROADCASTI32X8 (EVEX.U1.512 encoded version)
FI
FI;
Vol. 2C 5-433VBROADCASTI64X4 (EVEX.512 encoded version)
FI
FI;
VPBROADCASTB __m512i _mm512_broadcastb_epi8( __m128i a);
VPBROADCASTB __m512i _mm512_mask_broadcastb_epi8(__m512i s, __mmask64 k, __m128i a);VPBROADCASTB __m512i _mm512_maskz_broadcastb_epi8( __mmask64 k, __m128i a);VPBROADCASTB __m256i _mm256_broadcastb_epi8(__m128i a);VPBROADCASTB __m256i _mm256_mask_broadcastb_epi8(__m256i s, __mmask32 k, __m128i a);VPBROADCASTB __m256i _mm256_maskz_broadcastb_epi8( __mmask32 k, __m128i a);VPBROADCASTB __m128i _mm_mask_broadcastb_epi8(__m128i s, __mmask16 k, __m128i a);VPBROADCASTB __m128i _mm_maskz_broadc astb_epi8( __mmask16 k, __m128i a);
VPBROADCASTB __m128i _mm_broadcastb_epi8(__m128i a);VPBROADCASTD __m512i _mm512_broadcastd_epi32( __m128i a);VPBROADCASTD __m512i _mm512_mask_broadcastd _epi32(__m512i s, __mmask16 k, __m128i a);
VPBROADCASTD __m512i _mm512_maskz_broadca std_epi32( __mmask16 k, __m128i a);
VPBROADCASTD __m256i _mm256_broadcastd_epi32( __m128i a);VPBROADCASTD __m256i _mm256_mask_broadcastd _epi32(__m256i s, __mmask8 k, __m128i a);
VPBROADCASTD __m256i _mm256_maskz_broad castd_epi32( __mmask8 k, __m128i a);
VPBROADCASTD __m128i _mm_broadcastd_epi32(__m128i a);VPBROADCASTD __m128i _mm_mask_broadcastd_ epi32(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTD __m128i _mm_maskz_broadcas td_epi32( __mmask8 k, __m128i a);
VPBROADCASTQ __m512i _mm512_b roadcastq_epi64( __m128i a);
VPBROADCASTQ __m512i _mm512_mask_broadcastq _epi64(__m512i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m512i _mm512_maskz_broad castq_epi64( __mmask8 k, __m128i a);
VPBROADCASTQ __m256i _mm256_b roadcastq_epi64(__m128i a);
VPBROADCASTQ __m256i _mm256_mask_broadcastq _epi64(__m256i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m256i _mm256_maskz_broad castq_epi64( __mmask8 k, __m128i a);
VPBROADCASTQ __m128i _mm_br oadcastq_epi64(__m128i a);
VPBROADCASTQ __m128i _mm_mask_broadcastq_ epi64(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m128i _mm_maskz_broadc astq_epi64( __mmask8 k, __m128i a);
VPBROADCASTW __m512i _mm512_broadcastw_epi16(__m128i a);VPBROADCASTW __m512i _mm512_mask_broadcastw_epi16(__m512i s, __mmask32 k, __m128i a);VPBROADCASTW __m512i _mm512_maskz_broadcastw_epi16( __mmask32 k, __m128i a);VPBROADCASTW __m256i _mm256_broadcastw_epi16(__m128i a);VPBROADCASTW __m256i _mm256_mask_broadcastw_epi16(__m256i s, __mmask16 k, __m128i a);VPBROADCASTW __m256i _mm256_maskz_broadcastw_epi16( __mmask16 k, __m128i a);VPBROADCASTW __m128i _mm_broadcastw_epi16(__m128i a);VPBROADCASTW __m128i _mm_mask_broadcastw_ep i16(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTW __m128i _mm_maskz_broadc astw_epi16( __mmask8 k, __m128i a);
VBROADCASTI32x2 __m512i _mm512_broadcast_i32x2( __m128i a);VPBROADCAST—Load Integer and BroadcastINSTRUCTION SET REFERENCE, V
5-434 Vol. 2CVBROADCASTI32x2 __m512i _mm512_mask_broadcas t_i32x2(__m512i s, __mmask16 k, __m128i a);
VBROADCASTI32x2 __m512i _mm512_maskz_bro adcast_i32x2( __mmask16 k, __m128i a);
VBROADCASTI32x2 __m256i _mm256_broadcast_i32x2( __m128i a);VBROADCASTI32x2 __m256i _mm256_mask_broadcast_i32x2(__m256i s, __mmask8 k, __m128i a);VBROADCASTI32x2 __m256i _mm256_maskz_b roadcast_i32x2( __mmask8 k, __m128i a);
VBROADCASTI32x2 __m128i _mm_broadcast_i32x2(__m128i a);VBROADCASTI32x2 __m128i _mm_mask_broadcast _i32x2(__m128i s, __mmask8 k, __m128i a);
VBROADCASTI32x2 __m128i _mm_maskz_broa dcast_i32x2( __mmask8 k, __m128i a);
VBROADCASTI32x4 __m512i _mm512_broadcast_i32x4( __m128i a);VBROADCASTI32x4 __m512i _mm512_mask_broadcas t_i32x4(__m512i s, __mmask16 k, __m128i a);
VBROADCASTI32x4 __m512i _mm512_maskz_bro adcast_i32x4( __mmask16 k, __m128i a);
VBROADCASTI32x4 __m256i _mm256_broadcast_i32x4( __m128i a);VBROADCASTI32x4 __m256i _mm256_mask_broadcast_i32x4(__m256i s, __mmask8 k, __m128i a);VBROADCASTI32x4 __m256i _mm256_maskz_b roadcast_i32x4( __mmask8 k, __m128i a);
VBROADCASTI32x8 __m512i _mm512_broadcast_i32x8( __m256i a);VBROADCASTI32x8 __m512i _mm512_mask_broadcas t_i32x8(__m512i s, __mmask16 k, __m256i a);
VBROADCASTI32x8 __m512i _mm512_maskz_bro adcast_i32x8( __mmask16 k, __m256i a);
VBROADCASTI64x2 __m512i _mm512_broadcast_i64x2( __m128i a);VBROADCASTI64x2 __m512i _mm512_mask_broadcast_i64x2(__m512i s, __mmask8 k, __m128i a);VBROADCASTI64x2 __m512i _mm512_maskz_b roadcast_i64x2( __mmask8 k, __m128i a);
VBROADCASTI64x2 __m256i _mm256_broadcast_i64x2( __m128i a);VBROADCASTI64x2 __m256i _mm256_mask_broadcast_i64x2(__m256i s, __mmask8 k, __m128i a);VBROADCASTI64x2 __m256i _mm256_maskz_b roadcast_i64x2( __mmask8 k, __m128i a);
VBROADCASTI64x4 __m512i _mm512_broadcast_i64x4( __m256i a);VBROADCASTI64x4 __m512i _mm512_mask_broadcast_i64x4(__m512i s, __mmask8 k, __m256i a);VBROADCASTI64x4 __m512i _mm512_maskz_b roadcast_i64x4( __mmask8 k, __m256i a);
None.
EVEX-encoded instructions, see Table 2-23, “Type 6 Class Exception Conditions.”
EVEX-encoded instructions, syntax with reg/mem operand,  see Table 2-53, “Type E6 Class Exception Conditions.”
#UD If VEX.L = 0 for VPBROADCASTQ, VPBROADCASTI128.
If EVEX.L’L = 0 for VBROADCASTI32X4 /VBROADCASTI64X2 .
If EVEX.L’L < 10b for VBROADCASTI32X8 /VBROADCASTI64X4 .VPBROADCASTM—Broadcast Mask to Vector RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-435VPBROADCASTM—Broadcast Mask to Vector Register 
Broadcasts the zero-extended 64/32 bit value of the low by te/word of the source operand (the second operand) to 
each 64/32 bit element of the destination operand (the fi rst operand). The source operand is an opmask register. 
The destination operand is a ZMM register (EVEX.512), YMM register (EVEX.256), or XMM register (EVEX.128).
Operation
VPBROADCASTMB2Q
i := j*64DEST[i+63:i] := Ze roExtend(SRC[7:0])
VPBROADCASTMW2D
i := j*32DEST[i+31:i] := ZeroExtend(SRC[15:0])
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W1 2A /r
VPBROADCASTMB2Q xmm1, k1RM V/V AVX512VL
AVX512CDBroadcast low byte value in k1  to two locations in xmm1.
EVEX.256.F3.0F38.W1 2A /r
VPBROADCASTMB2Q ymm1, k1RM V/V AVX512VL
AVX512CDBroadcast low byte value in k1  to four locations in ymm1.
EVEX.512.F3.0F38.W1 2A /r
VPBROADCASTMB2Q zmm1, k1RM V/V AVX512CD Broadcast low byte valu e in k1 to eight locations in zmm1.
EVEX.128.F3.0F38.W0 3A /r
VPBROADCASTMW2D xmm1, k1RM V/V AVX512VL
AVX512CDBroadcast low word value in k1  to four locations in xmm1.
EVEX.256.F3.0F38.W0 3A /r
VPBROADCASTMW2D ymm1, k1RM V/V AVX512VL
AVX512CDBroadcast low word value in k1  to eight locations in ymm1.
EVEX.512.F3.0F38.W0 3A /r
VPBROADCASTMW2D zmm1, k1RM V/V AVX512CD Broadcast low word va lue in k1 to sixteen locations in 
zmm1.
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AVPBROADCASTM—Broadcast Mask to Vector RegisterINSTRUCTION SET REFERENCE, V
5-436 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTMB2Q __m512i _mm512 _broadcastmb_epi64( __mmask8);

zmm1.
VPBROADCASTMW2D __m512i _mm512_broadcastmw_epi32( __mmask16);VPBROADCASTMB2Q __m256i _mm256 _broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m256i _mm256_broadcastmw_epi32( __mmask8);
VPBROADCASTMB2Q __m128i _mm_broadcastmb_epi64( __mmask8);VPBROADCASTMW2D __m128i _mm_broadcastmw_epi32( __mmask8);
None
EVEX-encoded instruction, see Table 2-54, “Type E6NF Class Exception Conditions.”VPCMPB/VPCMPUB—Compare Packed Byte Values Into MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-437VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
Performs a SIMD compare of the packed byte values in th e second source operand and the first source operand and 
returns the results of the comparison to the mask dest ination operand. The comparison predicate operand (imme-
diate byte) specifies the type of compar ison performed on each pair of packed values in the two source operands. 
The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPB performs a comparison between pairs of signed byte values.VPCMPUB performs a comparison betw een pairs of unsigned byte values.
The first source operand (second operand) is a ZMM/Y MM/XMM register. The second source operand can be a 
ZMM/YMM/XMM register or a 512/256/128-bit memory locati on. The destination operand (first operand) is a mask 
register k1. Up to 64/32/16 comparison s are performed with results written to the destination operand under the 
writemask k2.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W0 3F /r ib
VPCMPB k1 {k2}, xmm2, 
AVX512BWCompare packed signed byte values in xmm3/m128 and 
xmm2 using bits 2:0 of imm8 as a comparison predicate 
with writemask k2 and leave th e result in ma sk register 
k1.
EVEX.256.66.0F3A.W0 3F /r ib
VPCMPB k1 {k2}, ymm2, 
AVX512BWCompare packed signed byte values in ymm3/m256 and 
ymm2 using bits 2:0 of imm8 as a comparison predicate 
k1.
EVEX.512.66.0F3A.W0 3F /r ib
VPCMPB k1 {k2}, zmm2, 
zmm3/m512, imm8A V/V AVX512BW Compare packed signed byte values in zmm3/m512 and 
zmm2 using bits 2:0 of imm8  as a comparison predicate 
k1.
EVEX.128.66.0F3A.W0 3E /r ib
VPCMPUB k1 {k2}, xmm2, 
AVX512BWCompare packed unsigned byte values in xmm3/m128 
and xmm2 using bits 2:0 of  imm8 as a comparison 
EVEX.256.66.0F3A.W0 3E /r ib
VPCMPUB k1 {k2}, ymm2, 
AVX512BWCompare packed unsigned byte values in ymm3/m256 
and ymm2 using bits 2:0 of imm8 as a comparison 
EVEX.512.66.0F3A.W0 3E /r ib
VPCMPUB k1 {k2}, zmm2, 
zmm3/m512, imm8A V/V AVX512BW Compare packed unsigned byte values in zmm3/m512 
and zmm2 using bits 2:0 of imm8 as a comparison 
A Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPCMPB/VPCMPUB—Compare Packed Byte Values Into MaskINSTRUCTION SET REFERENCE, V
5-438 Vol. 2CThe comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed. 
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table 
5-21.
:
Operation
0: OP := EQ; 1: OP := LT; 2: OP := LE; 3: OP := FALSE;4: OP := NEQ;5: OP := NLT; 6: OP := NLE; 7: OP := TRUE;
ESAC;
VPCMPB (EVEX encoded versions) 
THEN 
CMP := SRC1[i+7:i ] OP SRC2[i+7:i];
ELSE DEST[j] = 0 ; zeroing-masking onlyFI;
FI;
ENDFORDEST[MAX_KL-1:KL] := 0Table 5-21. Pseudo-Op and VPCMP* Implementation
Pseudo-Op PCMPM Implementation
VPCMPEQ*  reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 0
VPCMPLT*  reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 1
VPCMPLE* reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 2
VPCMPNEQ* reg1, reg2, reg3 VPCMP*  reg1, reg2, reg3, 4
VPPCMPNLT*  reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 5
VPCMPNLE* reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 6VPCMPB/VPCMPUB—Compare Packed Byte Values Into MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-439VPCMPUB (EVEX encoded versions) 
THEN 
ELSE DEST[j] = 0 ; ze roing-masking onlyFI;
FI;
VPCMPB __mmask64 _mm512_cmp_epi8_mask ( __m512i a, __m512i b, int cmp);
VPCMPB __mmask64 _mm512_mask_cmp_epi8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPB __mmask32 _mm256_cmp_epi8_mask ( __m256i a, __m256i b, int cmp);
VPCMPB __mmask32 _mm256_mask_cmp_epi8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPB __mmask16 _mm_cmp_epi8_mask( __m128i a, __m128i b, int cmp);VPCMPB __mmask16 _mm_mask_cmp_epi8_mask( __m mask16 m, __m128i a, __m128i b, int cmp);
VPCMPB __mmask64 _mm512_cmp[eq|ge|gt|le|l t|neq]_epi8_mask( __m512i a, __m512i b);
VPCMPB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq ]_epi8_mask( __mmask64 m, __m512i a, __m512i b);
VPCMPB __mmask32 _mm256_cmp[eq|ge|gt|le|l t|neq]_epi8_mask( __m256i a, __m256i b);
VPCMPB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq ]_epi8_mask( __mmask32 m, __m256i a, __m256i b);
VPCMPB __mmask16 _mm_cmp[eq|ge|gt|le|lt|n eq]_epi8_mask( __m128i a, __m128i b);
VPCMPB __mmask16 _mm_mask_cmp[eq| ge|gt|le|lt|neq]_epi8_mask( __mma sk16 m, __m128i a, __m128i b);
VPCMPUB __mmask64 _mm512_cmp_epu8_ma sk( __m512i a, __m512i b, int cmp);
VPCMPUB __mmask64 _mm512_mask_cmp_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPUB __mmask32 _mm256_cmp_epu8_ma sk( __m256i a, __m256i b, int cmp);
VPCMPUB __mmask32 _mm256_mask_cmp_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPUB __mmask16 _mm_cmp_epu8_mask( __m128i a, __m128i b, int cmp);VPCMPUB __mmask16 _mm_mask_cmp_epu8_mask( __mma sk16 m, __m128i a, __m128i b, int cmp);
VPCMPUB __mmask64 _mm512_cmp[eq| ge|gt|le|lt|neq]_epu8_mask( __m512i a, __m512i b, int cmp);
VPCMPUB __mmask64 _mm512_mask_cmp[eq|g e|gt|le|lt|neq]_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPUB __mmask32 _mm256_cmp[eq| ge|gt|le|lt|neq]_epu8_mask( __m256i a, __m256i b, int cmp);
VPCMPUB __mmask32 _mm256_mask_cmp[eq|g e|gt|le|lt|neq]_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPUB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_ epu8_mask( __m128i a, __m128i b, int cmp);
VPCMPUB __mmask16 _mm_mask_cmp[eq|ge |gt|le|lt|neq]_epu8_mask ( __mmask16 m, __m128i a, __m128i b, int cmp);
None
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”VPCMPD/VPCMPUD—Compare Packed Integer Values Into MaskINSTRUCTION SET REFERENCE, V
5-440 Vol. 2CVPCMPD/VPCMPUD—Compare Packed Integer Values Into Mask
Performs a SIMD compare of the packed integer values in  the second source operand and the first source operand 
and returns the results of the compar ison to the mask destination operand. The comparison predicate operand 
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-
ands. The result of each comparison is a single mask bi t result of 1 (comparison true) or 0 (comparison false).
VPCMPD/VPCMPUD performs a comparison between pair s of signed/unsigned doubleword integer values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a 
ZMM/YMM/XMM register or a 512/256/128-bit memory loca tion or a 512-bit vector broadcasted from a 32-bit 
memory location. The destination operan d (first operand) is a mask register k1. Up to 16/8/4 comparisons are 
performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed. 
5-21.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W0 1F /r ib
VPCMPD k1 {k2}, xmm2, 
AVX512FCompare packed signed doubleword integer values in 
xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8 
as a comparison predicate with writemask k2 and leave 
the result in mask register k1.
EVEX.256.66.0F3A.W0 1F /r ib

En64/32 
bit Mode 
Feature 
VPCMPD k1 {k2}, ymm2, 
ymm3/m256/m32bcst, imm8A V/V AVX512VL
ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8 
EVEX.512.66.0F3A.W0 1F /r ib
VPCMPD k1 {k2}, zmm2, 
zmm3/m512/m32bcst, imm8A V/V AVX512F Compare packed signed doubleword integer values in 
zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8 
as a comparison predicate. The comparison results are 
written to the destination k1 under writemask k2.
EVEX.128.66.0F3A.W0 1E /r ib
VPCMPUD k1 {k2}, xmm2, 
AVX512FCompare packed unsigned doubleword integer values in 
as a comparison predicate with writemask k2 and leave the result in mask register k1.
EVEX.256.66.0F3A.W0 1E /r ib
VPCMPUD k1 {k2}, ymm2, 
EVEX.512.66.0F3A.W0 1E /r ib
VPCMPUD k1 {k2}, zmm2, 
zmm3/m512/m32bcst, imm8A V/V AVX512F Compare packed unsigned doubleword integer values in 
as a comparison predicate. The comparison results are written to the destination k1 under writemask k2.
AF u l l M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) imm8VPCMPD/VPCMPUD—Compare Packed Integer Values Into MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-441Operation
ESAC;
VPCMPD (EVEX encoded versions) 
THEN 
THEN CMP := SRC1[i+31:i] OP SRC2[31:0];ELSE CMP := SRC1[i+31:i] OP SRC2[i+31:i];
FI;
VPCMPUD (EVEX encoded versions) 
THEN 
FI;
ENDFORDEST[MAX_KL-1:KL] := 0VPCMPD/VPCMPUD—Compare Packed Integer Values Into MaskINSTRUCTION SET REFERENCE, V
5-442 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPCMPD __mmask16 _mm512_cmp_epi32_mas k( __m512i a, __m512i b, int imm);
VPCMPD __mmask16 _mm512_mask_cmp_epi32_mask(_ _mmask16 k, __m512i a, __m512i b, int imm);
VPCMPD __mmask16 _mm512_cmp[e q|ge|gt|le|lt|neq]_epi32_mask( __m512i a, __m512i b);
VPCMPD __mmask16 _mm512_mask_cmp[eq |ge|gt|le|lt|neq]_epi32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPUD __mmask16 _mm512_cmp_epu32_mas k( __m512i a, __m512i b, int imm);
VPCMPUD __mmask16 _mm512_mask_cmp_epu32_mask( __mmask16 k, __m512i a, __m512i b, int imm);
VPCMPUD __mmask16 _mm512_cmp[eq|ge|gt|le|l t|neq]_epu32_mask( __m512i a, __m512i b);
VPCMPUD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask16 k, __m512i a, __m512i b);VPCMPD __mmask8 _mm256_cmp_epi32_mask(  __m256i a, __m256i b, int imm);
VPCMPD __mmask8 _mm256_mask_cmp_epi32_mask(__m mask8 k, __m256i a, __m256i b, int imm);
VPCMPD __mmask8 _mm256_cmp[eq|ge|gt|le|lt| neq]_epi32_mask( __m256i a, __m256i b);
VPCMPD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m256i a, __m256i b);VPCMPUD __mmask8 _mm256_cmp_epu32_mask ( __m256i a, __m256i b, int imm);
VPCMPUD __mmask8 _mm256_mask_cmp_epu32_mask(__mmask8 k, __m256i a, __m256i b, int imm);VPCMPUD __mmask8 _mm256_cmp[eq|ge|gt|le|lt| neq]_epu32_mask( __m256i a, __m256i b);
VPCMPUD __mmask8 _mm256_mask_cmp[eq |ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPD __mmask8 _mm_cmp_epi32_mask ( __m128i a, __m128i b, int imm);
VPCMPD __mmask8 _mm_mask_cmp_epi32_mask(__mma sk8 k, __m128i a, __m128i b, int imm);
VPCMPD __mmask8 _mm_cmp[eq|ge|gt|le|lt|n eq]_epi32_mask( __m128i a, __m128i b);
VPCMPD __mmask8 _mm_mask_cmp[eq| ge|gt|le|lt|neq]_epi32_mask(__mma sk8 k, __m128i a, __m128i b);
VPCMPUD __mmask8 _mm_cmp_epu32_mask( __m128i a, __m128i b, int imm);VPCMPUD __mmask8 _mm_mask_cmp_epu32_mask(__ mmask8 k, __m128i a, __m128i b, int imm);
VPCMPUD __mmask8 _mm_cmp[eq|ge|gt|le|lt|n eq]_epu32_mask( __m128i a, __m128i b);
VPCMPUD __mmask8 _mm_mask_cmp[eq| ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m128i a, __m128i b);
None
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-443VPCMPQ/VPCMPUQ—Compare Packed  Integer Values Into Mask
ands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPQ/VPCMPUQ performs a comparison between pa irs of signed/unsigned quadword integer values.
ZMM/YMM/XMM register or a 512/256/128-bit memory loca tion or a 512-bit vector broadcasted from a 64-bit 
memory location. The destination operan d (first operand) is a mask register k1. Up to 8/4/2 comparisons are 
The comparison predicate operand is an 8-bit immediate: bi ts 2:0 define the type of comparison to be performed. 
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W1 1F /r ib
VPCMPQ k1 {k2}, xmm2, 
xmm3/m128/m64bcst, imm8A V/V AVX512VL
AVX512FCompare packed signed quadword integer values in 
xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8 
EVEX.256.66.0F3A.W1 1F /r ib
VPCMPQ k1 {k2}, ymm2, 
ymm3/m256/m64bcst, imm8A V/V AVX512VL
ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8 
EVEX.512.66.0F3A.W1 1F /r ib
VPCMPQ k1 {k2}, zmm2, 
zmm3/m512/m64bcst, imm8A V/V AVX512F Compare packed signed quadword integer values in 
zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8 
EVEX.128.66.0F3A.W1 1E /r ib
VPCMPUQ k1 {k2}, xmm2, 
AVX512FCompare packed unsigned quadword integer values in 
EVEX.256.66.0F3A.W1 1E /r ib
VPCMPUQ k1 {k2}, ymm2, 
EVEX.512.66.0F3A.W1 1E /r ib
VPCMPUQ k1 {k2}, zmm2, 
zmm3/m512/m64bcst, imm8A V/V AVX512F Compare packed unsigned quadword integer values in 
A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into MaskINSTRUCTION SET REFERENCE, V
5-444 Vol. 2COperation
ESAC;
VPCMPQ (EVEX encoded versions)
THEN 
THEN CMP := SRC1[i+6 3:i] OP SRC2[63:0];
ELSE CMP := SRC1[i+63:i] OP SRC2[i+63:i];
FI;
VPCMPUQ (EVEX encoded versions)
THEN 

ESAC;
THEN 
FI;
THEN 
FI;
ENDFORDEST[MAX_KL-1:KL] := 0VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-445Intel C/C++ Compiler Intrinsic Equivalent
VPCMPQ __mmask8 _mm512_cmp_epi64_mask ( __m512i a, __m512i b, int imm);
VPCMPQ __mmask8 _mm512_mask_cmp_epi64_mask(__mm ask8 k, __m512i a, __m512i b, int imm);
VPCMPQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m512i a, __m512i b);VPCMPQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|ne q]_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPUQ __mmask8 _mm512_cmp_epu64_mask( __m512i a, __m512i b, int imm);VPCMPUQ __mmask8 _mm512_mask_cmp_epu64_mask( __mmask8 k, __m512i a, __m512i b, int imm);
VPCMPUQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt| neq]_epu64_mask( __m512i a, __m512i b);
VPCMPUQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq ]_epu64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPQ __mmask8 _mm256_cmp_epi64_mask ( __m256i a, __m256i b, int imm);
VPCMPQ __mmask8 _mm256_mask_cmp_epi64_mask(__mm ask8 k, __m256i a, __m256i b, int imm);
VPCMPQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m256i a, __m256i b);VPCMPQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|ne q]_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPUQ __mmask8 _mm256_cmp_epu64_mask( __m256i a, __m256i b, int imm);VPCMPUQ __mmask8 _mm256_mask_cmp_epu64_mask( __mmask8 k, __m256i a, __m256i b, int imm);
VPCMPUQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt| neq]_epu64_mask( __m256i a, __m256i b);
VPCMPUQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq ]_epu64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPQ __mmask8 _mm_cmp_epi64_mask( __m128i a, __m128i b, int imm);VPCMPQ __mmask8 _mm_mask_cmp_epi64_mask(__mma sk8 k, __m128i a, __m128i b, int imm);
VPCMPQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|n eq]_epi64_mask( __m128i a, __m128i b);
VPCMPQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_e pi64_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPUQ __mmask8 _mm_cmp_epu64_mask( __m128i a, __m128i b, int imm);VPCMPUQ __mmask8 _mm_mask_cmp_epu64_mask(__m mask8 k, __m128i a, __m128i b, int imm);
VPCMPUQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|n eq]_epu64_mask( __m128i a, __m128i b);
VPCMPUQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq] _epu64_mask(__mmask8 k, __m128i a, __m128i b);
None
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”VPCMPW/VPCMPUW—Compare Packed Word Values Into MaskINSTRUCTION SET REFERENCE, V
5-446 Vol. 2CVPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
Performs a SIMD compare of the packed integer word in the second source operand and the first source operand 
VPCMPW performs a comparison between pairs of signed word values.VPCMPUW performs a comparison betwee n pairs of unsigned word values.
ZMM/YMM/XMM register or a 512/256/128-bit memory locati on. The destination operand (f irst operand) is a mask 
register k1. Up to 32/16/8 comparisons are performed wi th results written to the destination operand under the 
writemask k2.
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W1 3F /r ib
VPCMPW k1 {k2}, xmm2, 
xmm3/m128, imm8A V/V AVX512VL
AVX512BWCompare packed signed word integers in xmm3/m128 
and xmm2 using bits 2:0 of imm8 as a comparison 
predicate with writemask k2 and leave the result in 
mask register k1.
EVEX.256.66.0F3A.W1 3F /r ib
VPCMPW k1 {k2}, ymm2, 
ymm3/m256, imm8A V/V AVX512VL
AVX512BWCompare packed signed word integers in ymm3/m256 
and ymm2 using bits 2:0 of  imm8 as a comparison 
EVEX.512.66.0F3A.W1 3F /r ib
VPCMPW k1 {k2}, zmm2, 
zmm3/m512, imm8A V/V AVX512BW Compare packed signed word integers in zmm3/m512 
EVEX.128.66.0F3A.W1 3E /r ib
VPCMPUW k1 {k2}, xmm2, 
AVX512BWCompare packed unsigned word integers in xmm3/m128 
EVEX.256.66.0F3A.W1 3E /r ib
VPCMPUW k1 {k2}, ymm2, 
AVX512BWCompare packed unsigned word integers in ymm3/m256 
EVEX.512.66.0F3A.W1 3E /r ib
VPCMPUW k1 {k2}, zmm2, 
zmm3/m512, imm8A V/V AVX512BW Compare packed unsigned word integers in zmm3/m512 
A Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPCMPW/VPCMPUW—Compare Packed Word Values Into MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-447Operation
ESAC;
VPCMPW (EVEX encoded versions)
THEN 
ICMP := SRC1[i+15:i]  OP SRC2[i+15:i];
ELSE DEST[j] = 0 ; zeroing-masking only
FI;
VPCMPUW (EVEX encoded versions)
THEN 
CMP := SRC1[i+15:i] OP SRC2[i+15:i];IF CMP = TRUE
FI;
ENDFORDEST[MAX_KL-1:KL] := 0VPCMPW/VPCMPUW—Compare Packed Word Values Into MaskINSTRUCTION SET REFERENCE, V
5-448 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPCMPW __mmask32 _mm512_cmp_epi16_mask( __m512i a, __m512i b, int cmp);
VPCMPW __mmask32 _mm512_mask_cmp_epi16_mask( __m mask32 m, __m512i a, __m512i b, int cmp);
VPCMPW __mmask16 _mm256_cmp_epi16_mask( __m256i a, __m256i b, int cmp);VPCMPW __mmask16 _mm256_mask_cmp_epi16_mask( __m mask16 m, __m256i a, __m256i b, int cmp);
VPCMPW __mmask8 _mm_cmp_epi16_mask( __m128i a, __m128i b, int cmp);VPCMPW __mmask8 _mm_mask_cmp_epi16_mask( __ mmask8 m, __m128i a, __m128i b, int cmp);
VPCMPW __mmask32 _mm512_cmp[eq|ge|gt|le|lt| neq]_epi16_mask( __m512i a, __m512i b);
VPCMPW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|n eq]_epi16_mask( __mmask32 m, __m512i a, __m512i b);
VPCMPW __mmask16 _mm256_cmp[eq|ge|gt|le|lt| neq]_epi16_mask( __m256i a, __m256i b);
VPCMPW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|n eq]_epi16_mask( __mmask16 m, __m256i a, __m256i b);
VPCMPW __mmask8 _mm_cmp[eq|ge|gt|le|lt|n eq]_epi16_mask( __m128i a, __m128i b);
VPCMPW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq] _epi16_mask( __mmask8 m, __m128i a, __m128i b);
VPCMPUW __mmask32 _mm512_cmp_epu16_mask( __m512i a, __m512i b, int cmp);VPCMPUW __mmask32 _mm512_mask_cmp_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);VPCMPUW __mmask16 _mm256_cmp_epu16_mask( __m256i a, __m256i b, int cmp);VPCMPUW __mmask16 _mm256_mask_cmp_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);VPCMPUW __mmask8 _mm_cmp_epu16_mask( __m128i a, __m128i b, int cmp);VPCMPUW __mmask8 _mm_mask_cmp_epu16_mask( __m mask8 m, __m128i a, __m128i b, int cmp);
VPCMPUW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|ne q]_epu16_mask( __m512i a, __m512i b, int cmp);
VPCMPUW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu 16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPUW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|ne q]_epu16_mask( __m256i a, __m256i b, int cmp);
VPCMPUW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu 16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPUW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m128i a, __m128i b, int cmp);VPCMPUW __mmask8 _mm_mask_cmp[eq|ge|g t|le|lt|neq]_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
None
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”VPCOMPRESSB/VCOMPRESSW—Store Sparse Packed Byte /Word Integer Values Into Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-449VPCOMPRESSB/VCOMPRESSW—Store Sparse Packe d Byte/Word Integer Values Into Dense 
Memory/Register 

None
Compress (stores) up to 64 byte values or 32 word valu es from the source operand (second operand) to the desti-
nation operand (first operand), based on the active elements determined by the writemask operand. Note: 
Moves up to 512 bits of packed byte values from the so urce operand (second operand) to the destination operand 
(first operand). This instruction is used to store partial contents of a vector register into a byte vector or single memory location using the active elements in operand writemask.
This instruction supports memory fault suppression.Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F38.W0 63 /r
VPCOMPRESSB m128{k1}, xmm1AV / VA V X 5 1 2 _ V B M I 2
AVX512VLCompress up to 128 bits of packed byte values 
from xmm1 to m128 with writemask k1.
VPCOMPRESSB xmm1{k1}{z}, xmm2BV / VA V X 5 1 2 _ V B M I 2
from xmm2 to xmm1 with writemask k1.
EVEX.256.66.0F38.W0 63 /r
VPCOMPRESSB m256{k1}, ymm1AV / VA V X 5 1 2 _ V B M I 2
AVX512VLCompress up to 256 bits of packed byte values 
from ymm1 to m256 with writemask k1.
VPCOMPRESSB ymm1{k1}{z}, ymm2BV / VA V X 5 1 2 _ V B M I 2
from ymm2 to ymm1 with writemask k1.
EVEX.512.66.0F38.W0 63 /r
VPCOMPRESSB m512{k1}, zmm1A V/V AVX512_VBMI2 Compress up to 512 bits of packed byte values 
from zmm1 to m512 with writemask k1.
VPCOMPRESSB zmm1{k1}{z}, zmm2B V/V AVX512_VBMI2 Compress up to 512 bits of packed byte values 
from zmm2 to zmm1 with writemask k1.
EVEX.128.66.0F38.W1 63 /r
VPCOMPRESSW m128{k1}, xmm1AV / VA V X 5 1 2 _ V B M I 2
AVX512VLCompress up to 128 bits of packed word values 
VPCOMPRESSW xmm1{k1}{z}, xmm2BV / VA V X 5 1 2 _ V B M I 2
EVEX.256.66.0F38.W1 63 /r
VPCOMPRESSW m256{k1}, ymm1AV / VA V X 5 1 2 _ V B M I 2
AVX512VLCompress up to 256 bits of packed word values 
VPCOMPRESSW ymm1{k1}{z}, ymm2BV / VA V X 5 1 2 _ V B M I 2
EVEX.512.66.0F38.W1 63 /r
VPCOMPRESSW m512{k1}, zmm1A V/V AVX512_VBMI2 Compress up to 512 bits of packed word values 
VPCOMPRESSW zmm1{k1}{z}, zmm2B V/V AVX512_VBMI2 Compress up to 512 bits of packed word values 
A Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/A
B N/A ModRM:r/m (w) ModRM:reg (r) N/A N/AVPCOMPRESSB/VCOMPRESSW—Store Sparse Packed Byte/W ord Integer Values Into Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
5-450 Vol. 2CNote that the compressed displacement assumes a pre-scaling  (N) corresponding to the size of one single element 
Operation
VPCOMPRESSB store form
(KL, VL) = (16, 128), (32, 256), (64, 512)k := 0FOR j := 0 TO KL-1:
DEST.byte[k] := SRC.byte[j]k := k +1
VPCOMPRESSB reg-reg form
DEST.byte[k] := SRC.byte[j]k := k + 1
IF *merging-masking*:
*DEST[VL-1:k*8] re mains unchanged*
ELSE DEST[VL-1:k*8] := 0
VPCOMPRESSW store form
(KL, VL) = (8, 128), (16, 256), (32, 512)k := 0FOR j := 0 TO KL-1:
DEST.word[k] := SRC.word[j]k := k + 1
VPCOMPRESSW reg-reg form
*DEST[VL-1:k*16] remains unchanged*
ELSE DEST[VL-1:k*16] := 0
DEST[MAX_VL-1:VL] := 0VPCOMPRESSB/VCOMPRESSW—Store Sparse Packed Byte /Word Integer Values Into Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-451Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSB __m128i _mm_mask_compress_epi8(__m128i, __mmask16, __m128i);
VPCOMPRESSB __m128i _mm_maskz_compress_epi8(__mmask16, __m128i);VPCOMPRESSB __m256i _mm256_mask_compress_epi8(__m256i, __mmask32, __m256i);VPCOMPRESSB __m256i _mm256_maskz_compress_epi8(__mmask32, __m256i);VPCOMPRESSB __m512i _mm512_mask_compress_epi8(__m512i, __mmask64, __m512i);VPCOMPRESSB __m512i _mm512_maskz_compress_epi8(__mmask64, __m512i);VPCOMPRESSB  void _mm_mask_compressst oreu_epi8(void*, __mmask16, __m128i);
VPCOMPRESSB  void _mm256_mask_compressst oreu_epi8(void*, __ mmask32, __m256i);
VPCOMPRESSB  void _mm512_mask_compressst oreu_epi8(void*, __ mmask64, __m512i);
VPCOMPRESSW  __m128i  _mm_mask_compre ss_epi16(__m128i, __mmask8, __m128i);
VPCOMPRESSW  __m128i  _mm_maskz_compress_epi16(__mmask8, __m128i); VPCOMPRESSW  __m256i  _mm256_mask_compress_epi16(__m256i, __mmask16, __m256i);VPCOMPRESSW  __m256i  _mm256_maskz_compress_epi16(__mmask16, __m256i);VPCOMPRESSW  __m512i  _mm512_mask_compress_epi16(__m512i, __mmask32, __m512i);VPCOMPRESSW  __m512i  _mm512_maskz_compress_epi16(__mmask32, __m512i);VPCOMPRESSW  void  _mm_mask_compresss toreu_epi16(void*, __mmask8, __m128i);
VPCOMPRESSW  void  _mm256_mask_compre ssstoreu_epi16(void* , __mmask16, __m256i);
VPCOMPRESSW  void  _mm512_mask_compre ssstoreu_epi16(void* , __mmask32, __m512i);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values Into Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
5-452 Vol. 2CVPCOMPRESSD—Store Sparse Packed Doubleword Integer Values Into Dense Memory/Register
Compress (store) up to 16/8/4 doubleword integer values from the source operand (second operand) to the desti-
nation operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a 
ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial  vector or possibly non-contiguous if less than 16 active 
source operand, the upper bits of the destination register  are unmodified if EVEX.z is not set, otherwise the upper 
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Note that the compressed displacement assumes a pre-scaling  (N) corresponding to the size of one single element 
Operation
VPCOMPRESSD (EVEX encoded versions) store form
THEN 
FI;
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 8B /r
VPCOMPRESSD xmm1/m128 {k1}{z}, xmm2AV / V A V X 5 1 2 V L
AVX512FCompress packed doubleword integer values from 
xmm2 to xmm1/m128 using control mask k1.
EVEX.256.66.0F38.W0 8B /r
VPCOMPRESSD ymm1/m256 {k1}{z}, ymm2AV / V A V X 5 1 2 V L
ymm2 to ymm1/m256 using control mask k1.
EVEX.512.66.0F38.W0 8B /r
VPCOMPRESSD zmm1/m512 {k1}{z}, zmm2A V/V AVX512F Compress packed doubleword integer values from 
zmm2 to zmm1/m512 using control mask k1.
A Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AVPCOMPRESSD—Store Sparse Packed Doubleword Integer Values Into Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-453VPCOMPRESSD (EVEX encoded versions) reg-reg form
THEN 
FI;
ENDFOR
FI
VPCOMPRESSD __m512i _mm512_mask_compress _epi32(__m512i s, __mmask16 c, __m512i a);

THEN 
FI;
ENDFOR
FI
VPCOMPRESSD __m512i _mm512_maskz_compr ess_epi32( __mmask16 c, __m512i a);
VPCOMPRESSD void _mm512_mask_compressstoreu_e pi32(void * a, __mmask16 c, __m512i s);
VPCOMPRESSD __m256i _mm256_mask_compress_e pi32(__m256i s, __mma sk8 c, __m256i a);
VPCOMPRESSD __m256i _mm256_maskz_compr ess_epi32( __mmask8 c, __m256i a);
VPCOMPRESSD void _mm256_mask_compressstoreu _epi32(void * a, __mmask8 c, __m256i s);
VPCOMPRESSD __m128i _mm_mask_compress_ep i32(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSD __m128i _mm_maskz_compress_epi32( __mmask8 c, __m128i a);VPCOMPRESSD void _mm_mask_compressstoreu_e pi32(void * a, __mmask8 c, __m128i s);
None
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values Into Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
5-454 Vol. 2CVPCOMPRESSQ—Store Sparse Pa cked Quadword Integer Values Into Dense Memory/Register
Compress (stores) up to 8/4/2 quadword integer values fr om the source operand (second operand) to the destina-
tion operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a 
Operation
VPCOMPRESSQ (EVEX encoded versions) store form
THEN 
FI;
ENFOROpcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W1 8B /r
VPCOMPRESSQ xmm1/m128 {k1}{z}, xmm2A V/V AVX512VL
AVX512FCompress packed quadword integer values from 
EVEX.256.66.0F38.W1 8B /r
VPCOMPRESSQ ymm1/m256 {k1}{z}, ymm2A V/V AVX512VL
ymm2 to ymm1/m256 us ing control mask k1.
EVEX.512.66.0F38.W1 8B /r
VPCOMPRESSQ zmm1/m512 {k1}{z}, zmm2A V/V AVX512F Compress packed quadword integer values from 
zmm2 to zmm1/m512 using control mask k1. 
A Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/AVPCOMPRESSQ—Store Sparse Packed Quadword Integer Values Into Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-455VPCOMPRESSQ (EVEX encoded versions) reg-reg form
THEN 
FI;
ENDFOR
IF *merging-mas king* 
FI
VPCOMPRESSQ __m512i _mm512_mask_compress_ep i64(__m512i s, __mmask8 c, __m512i a);
VPCOMPRESSQ __m512i _mm512_maskz_compr ess_epi64( __mmask8 c, __m512i a);
VPCOMPRESSQ void _mm512_mask_compressstoreu _epi64(void * a, __mmask8 c, __m512i s);
VPCOMPRESSQ __m256i _mm256_mask_compress_ep i64(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSQ __m256i _mm256_maskz_compr ess_epi64( __mmask8 c, __m256i a);
VPCOMPRESSQ void _mm256_mask_compressstoreu _epi64(void * a, __mmask8 c, __m256i s);
VPCOMPRESSQ __m128i _mm_mask_compress_ep i64(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSQ __m128i _mm_maskz_compress_epi64( __mmask8 c, __m128i a);VPCOMPRESSQ void _mm_mask_compressstoreu_ epi64(void * a, __mmask8 c, __m128i s);
None
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”VPCONFLICTD/Q—Detect Conflicts Within a Vector of Pa cked Dword/Qword Values Into Dense Memory/ RegisterINSTRUCTION SET REFERENCE, V
5-456 Vol. 2CVPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values Into Dense 
Memory/ Register
Test each dword/qword element of the source operand (the second operand) for equality with all other elements in 
the source operand closer to the least significant elemen t. Each element’s comparison results form a bit vector, 
which is then zero extended and written to  the destination according to the writemask.
EVEX.512 encoded version: The source operand is a ZMM re gister, a 512-bit memory location, or a 512-bit vector 
broadcasted from a 32/64-bit memory location. The destin ation operand is a ZMM register, conditionally updated 
using writemask k1. 
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector 
broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1. 
EVEX.128 encoded version: The source operand is a XMM re gister, a 128-bit memory location, or a 128-bit vector 
broadcasted from a 32/64-bit memory location. The destin ation operand is a XMM register, conditionally updated 
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 C4 /r
VPCONFLICTD xmm1 {k1}{z}, 
xmm2/m128/m32bcstAV / V  A V X 5 1 2 V L
AVX512CDDetect duplicate double-word values in 
xmm2/m128/m32bcst using writemask k1.
EVEX.256.66.0F38.W0 C4 /r
VPCONFLICTD ymm1 {k1}{z}, 
ymm2/m256/m32bcstAV / V  A V X 5 1 2 V L
ymm2/m256/m32bcst using writemask k1.
EVEX.512.66.0F38.W0 C4 /r
VPCONFLICTD zmm1 {k1}{z}, zmm2/m512/m32bcstA V/V AVX512CD Detect duplicate double-word values in 
zmm2/m512/m32bcst using writemask k1.
EVEX.128.66.0F38.W1 C4 /r
VPCONFLICTQ xmm1 {k1}{z}, 
xmm2/m128/m64bcstAV / V  A V X 5 1 2 V L
AVX512CDDetect duplicate quad-word values in 
xmm2/m128/m64bcst using writemask k1.
EVEX.256.66.0F38.W1 C4 /r
VPCONFLICTQ ymm1 {k1}{z}, 
ymm2/m256/m64bcstAV / V  A V X 5 1 2 V L
ymm2/m256/m64bcst using writemask k1.
EVEX.512.66.0F38.W1 C4 /r
VPCONFLICTQ zmm1 {k1}{z}, 
zmm2/m512/m64bcstA V/V AVX512CD Detect duplicate quad-word values in 
zmm2/m512/m64bcst using writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVPCONFLICTD/Q—Detect Conflicts Within a Vector of Pa cked Dword/Qword Values Into Dense Memory/ RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-457Operation
VPCONFLICTD
(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j :=  0 TO KL-1
i := j*32
IF MaskBit(j) OR *no writemask*THEN 
FOR k :=  0 TO j-1
m := k*32
IF ((SRC[i+31:i] = SRC[m+31:m])) THEN 
DEST[i+k]  := 1
ELSE 
DEST[i+k] :=  0
FI
ENDFORDEST[i+31:i+j]  := 0
ELSE
IF *merging-masking* THEN 
*DEST[i+31:i] remains unchanged*
ELSE 
DEST[i+31:i]  := 0
FI
FI
ENDFOR
DEST[MAXVL-1:VL]
 := 0
VPCONFLICTQ
FOR j  := 0 TO KL-1
i := j*64
m := k*64
IF ((SRC[i+63:i] = SRC[m+63:m])) THEN 
DEST[i+k] :=  1
ELSE 
DEST[i+k]  := 0
FI
ENDFOR
DEST[i+63:i+j]  := 0
ELSE
ELSE
DEST[i+63:i]  := 0
 FI
FI
ENDFORDEST[MAXVL-1:VL] := 0VPCONFLICTD/Q—Detect Conflicts Within a Vector of Pa cked Dword/Qword Values Into Dense Memory/ RegisterINSTRUCTION SET REFERENCE, V
5-458 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPCONFLICTD __m512i _mm512_conflict_epi32( __m512i a);
VPCONFLICTD __m512i _mm512_mask_conflict_epi32(__m512i s, __mmask16 m, __m512i a);VPCONFLICTD __m512i _mm512_maskz_conflict_epi32(__mmask16 m, __m512i a);
VPCONFLICTQ __m512i _mm512_conflict_epi64( __m512i a);
VPCONFLICTQ __m512i _mm512_mask_conflict_e pi64(__m512i s, __mmask8 m, __m512i a);
VPCONFLICTQ __m512i _mm512_maskz_conflict_epi64(__mmask8 m, __m512i a);VPCONFLICTD __m256i _mm256_conflict_epi32( __m256i a);VPCONFLICTD __m256i _mm256_mask_conflict_epi32(__m256i s, __mmask8 m, __m256i a);VPCONFLICTD __m256i _mm256_maskz_conflict_epi32(__mmask8 m, __m256i a);
VPCONFLICTQ __m256i _mm256_conflict_epi64( __m256i a);
VPCONFLICTQ __m256i _mm256_mask_conflict_e pi64(__m256i s, __mmask8 m, __m256i a);

FI
FI
VPCONFLICTQ __m256i _mm256_maskz_conflict_epi64(__mmask8 m, __m256i a);VPCONFLICTD __m128i _mm_conflict_epi32( __m128i a);VPCONFLICTD __m128i _mm_mask_conflict_epi32(__m128i s, __mmask8 m, __m128i a);
VPCONFLICTD __m128i _mm_maskz_conflict_epi32(__mmask8 m, __m128i a);
VPCONFLICTQ __m128i _mm_conflict_epi64( __m128i a);VPCONFLICTQ __m128i _mm_mask_conflict_ep i64(__m128i s, __mmask8 m, __m128i a);
VPCONFLICTQ __m128i _mm_maskz_conf lict_epi64(__mmask8 m, __m128i a);
None
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”VPDPBUSD—Multiply and Add Unsigned and Signed BytesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-459VPDPBUSD—Multiply and Add Un signed and Signed Bytes
Multiplies the individual unsigned bytes of the first source  operand by the corresponding signed bytes of the second 
source operand, producing intermediate signed word resu lts. The word results are then summed and accumulated 
in the destination dword element size operand.
This instruction supports memory fault suppression.
Operation
VPDPBUSD dest, src1, src2 (VEX encoded versions)
VL=(128, 256)KL=VL/32
ORIGDEST := DEST
FOR i := 0 TO KL-1:
// Extending to 16b 
// src1extend := ZERO_EXTEND// src2extend := SIGN_EXTEND
p1word := src1extend(SRC1.byte[4*i +0]) * src2extend (SRC2.byte[4*i+0])Opcode/
En64/32 
bit Mode 
VEX.128.66.0F38.W0 50 /r 
VPDPBUSD xmm1, xmm2, 
xmm3/m128A V/V AVX-VNNI Multiply groups of 4 pairs of signed bytes in 
xmm3/m128 with corresponding unsigned bytes of 
xmm2, summing those products and adding them 
to doubleword result in xmm1.
VEX.256.66.0F38.W0 50 /r
VPDPBUSD ymm1, ymm2, 
ymm3/m256A V/V AVX-VNNI Multiply groups of 4 pairs of signed bytes in 
ymm3/m256 with corresponding unsigned bytes of 
ymm2, summing those products and adding them 
to doubleword result in ymm1.
EVEX.128.66.0F38.W0 50 /r
VPDPBUSD xmm1{k1}{z}, xmm2, 
xmm3/m128/m32bcstB V/V AVX512_VNNI
AVX512VLMultiply groups of 4 pairs of signed bytes in 
xmm3/m128/m32bcst with corresponding 
unsigned bytes of xmm2, summing those products 
and adding them to doub leword result in xmm1 
EVEX.256.66.0F38.W0 50 /r
VPDPBUSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512_VNNI
ymm3/m256/m32bcst with corresponding unsigned bytes of ymm2, summing those products 
and adding them to doub leword result in ymm1 
EVEX.512.66.0F38.W0 50 /r
VPDPBUSD zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512_VNNI Multiply groups of 4 pairs of signed bytes in 
zmm3/m512/m32bcst with corresponding 
unsigned bytes of zmm2, summing those products 
and adding them to doub leword result in zmm1 
B Full ModRM:reg (r, w) EVEX .vvvv (r) ModRM:r/m (r) N/AVPDPBUSD—Multiply and Add Unsigned and Signed BytesINSTRUCTION SET REFERENCE, V
5-460 Vol. 2Cp2word := src1extend(SRC1.byte[4*i +1]) * src2extend (SRC2.byte[4*i+1])
p3word := src1extend(SRC1.byte[4*i +2]) * src2extend (SRC2.byte[4*i+2])
p4word := src1extend(SRC1.byte[4*i +3]) * src2extend (SRC2.byte[4*i+3])
DEST.dword[i] := OR IGDEST.dword[i] + p1word + p2word + p3word + p4word
DEST[MAX_VL-1:VL] := 0VPDPBUSD dest, src1, src2 (EVEX encoded versions)
(KL,VL)=(4,128), (8,256), (16,512)
ORIGDEST := DESTFOR i := 0 TO KL-1:
// Byte elements of SRC1 are zero-extended to 16b and// byte elements of SRC2 are sign extended to 16b before multiplication.IF SRC2 is memory and EVEX.b == 1:
t := SRC2.dword[0]
ELSE:
t := SRC2.dword[i]
p1word := ZERO_EXTEND(SRC1.byte[4*i]) * SIGN_EXTEND(t.byte[0])p2word := ZERO_EXTEND(SRC1.byte[4*i+1]) * SIGN_EXTEND(t.byte[1])p3word := ZERO_EXTEND(SRC1.byte[4*i+2]) * SIGN_EXTEND(t.byte[2])p4word := ZERO_EXTEND(SRC1.byte[4*i+3]) * SIGN_EXTEND(t.byte[3])DEST.dword[i] := OR IGDEST.dword[i] + p1word + p2word + p3word + p4word
DEST.dword[i] := 0
ELSE: // Merge masking, dest element unchanged
DEST.dword[i] := ORIGDEST.dword[i]
VPDPBUSD __m128i _mm_dpbusd_avx_epi32(__m128i, __m128i, __m128i);
VPDPBUSD __m128i _mm_dpbusd_epi32(__m128i, __m128i, __m128i);VPDPBUSD __m128i _mm_mask_dpbusd_epi 32(__m128i, __mmask8,  __m128i, __m128i);
VPDPBUSD __m128i _mm_maskz_dpbusd_epi32( __mmask8, __m128i, __m128i, __m128i);
VPDPBUSD __m256i _mm256_dpbusd_avx_epi32(__m256i, __m256i, __m256i);VPDPBUSD __m256i _mm256_dpbusd_ep i32(__m256i, __m256i, __m256i);
VPDPBUSD __m256i _mm256_mask_dpbusd_epi 32(__m256i, __mmask8, __m256i, __m256i);
VPDPBUSD __m256i _mm256_maskz_dpbusd_epi32(__mmask8, __m256i, __m256i, __m256i);VPDPBUSD __m512i _mm512_dpbusd_ep i32(__m512i, __m512i, __m512i);
VPDPBUSD __m512i _mm512_mask_dpbusd_epi 32(__m512i, __mmask16, __m512i, __m512i);
VPDPBUSD __m512i _mm512_maskz_dpbusd_epi32(__mmask16, __m512i, __m512i, __m512i);
None.
Non-EVEX-encoded instruction, see Table 2 -21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-49,  “Type E4 Class Exception Conditions.”VPDPBUSDS—Multiply and Add Unsigned  and Signed Bytes With SaturationINSTRUCTION SET REFERENCE, V
Vol. 2C 5-461VPDPBUSDS—Multiply and Ad d Unsigned and Signed Bytes With Saturation 
in the destination dword element size operand. If the in termediate sum overflows a 32b signed number the result 
is saturated to either 0x7FFF_FFFF for positi ve numbers of 0x8000_0000 for negative numbers.
Operation
VPDPBUSDS dest, src1, src2 (VEX encoded versions)
FOR i := 0 TO KL-1:Opcode/
En64/32 
bit Mode 
VEX.128.66.0F38.W0 51 /r
VPDPBUSDS xmm1, xmm2, 
xmm3/m128A V/V AVX-VNNI Multiply groups of 4 pairs signed bytes in 
xmm3/m128 with corresponding unsigned 
bytes of xmm2, summing those products and 
adding them to doubleword result, with signed saturation in xmm1.
VEX.256.66.0F38.W0 51 /r
VPDPBUSDS ymm1, ymm2, 
ymm3/m256A V/V AVX-VNNI Multiply groups of 4 pairs signed bytes in 
ymm3/m256 with corresponding unsigned 
bytes of ymm2, summin g those products and 
adding them to doubleword result, with signed 
saturation in ymm1.
EVEX.128.66.0F38.W0 51 /r
VPDPBUSDS xmm1{k1}{z}, xmm2, 
AVX512VLMultiply groups of 4 pairs signed bytes in 
unsigned bytes of xmm2, summing those 
products and adding them to doubleword 
result, with signed satu ration in xmm1, under 
EVEX.256.66.0F38.W0 51 /r
VPDPBUSDS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512_VNNI
ymm3/m256/m32bcst with corresponding unsigned bytes of ymm2, summing those 
result, with signed satu ration in ymm1, under 
EVEX.512.66.0F38.W0 51 /r
VPDPBUSDS zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512_VNNI Multiply groups of 4 pairs signed bytes in 
unsigned bytes of zmm2, summing those products and adding them to doubleword 
result, with signed satu ration in zmm1, under 
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPDPBUSDS—Multiply and Add Unsigned and Signed Bytes With SaturationINSTRUCTION SET REFERENCE, V
5-462 Vol. 2C// Extending to 16b 
p1word := src1extend(SRC1.byte[4*i +0]) * src2extend (SRC2.byte[4*i+0])
p2word := src1extend(SRC1.byte[4*i +1]) * src2extend (SRC2.byte[4*i+1])
DEST.dword[i] := SIGNED_DWORD_SATURATE(ORIGDEST.d word[i] + p1word + p2wo rd + p3word + p4word)
DEST[MAX_VL-1:VL] := 0VPDPBUSDS dest, src1, src2 (EVEX encoded versions)
ELSE:

ELSE:
p1word := ZERO_EXTEND(SRC1.byte[4*i]) * SIGN_EXTEND(t.byte[0])p2word := ZERO_EXTEND(SRC1.byte[4*i+1]) * SIGN_EXTEND(t.byte[1])p3word := ZERO_EXTEND(SRC1.byte[4*i+2]) * SIGN_EXTEND(t.byte[2])p4word := ZERO_EXTEND(SRC1.byte[ 4*i+3]) *SIGN_EXTEND(t.byte[3])
VPDPBUSDS __m128i _mm_dpbusds_av x_epi32(__m128i, __m128i, __m128i);
VPDPBUSDS __m128i _mm_dpbusds_epi32(__m128i, __m128i, __m128i);VPDPBUSDS __m128i _mm_mask_dpbusds_epi32( __m128i, __mmask8, __m128i, __m128i);
VPDPBUSDS __m128i _mm_maskz_dpbusds_epi32(__mmask8, __m128i, __m128i, __m128i);VPDPBUSDS __m256i _mm256_dpbusds_avx_epi32(__m256i, __m256i, __m256i);VPDPBUSDS __m256i _mm256_dpbusds_ epi32(__m256i, __m256i, __m256i);
VPDPBUSDS __m256i _mm256_mask_dpbusds_epi3 2(__m256i, __mmask8, __m256i, __m256i);
VPDPBUSDS __m256i _mm256_maskz_dpbusds_e pi32(__mmask8, __m256i, __m256i, __m256i);
VPDPBUSDS __m512i _mm512_dpbusds_ epi32(__m512i, __m512i, __m512i);
VPDPBUSDS __m512i _mm512_mask_dpbusds_epi32(__m512i, __mmask16, __m512i, __m512i);VPDPBUSDS __m512i _mm512_maskz_dpbusds_epi 32(__mmask16, __m512i, __m512i, __m512i);
None.
EVEX-encoded instruction, see Table 2-49,  “Type E4 Class Exception Conditions.”VPDPWSSD—Multiply and Add Signed Word IntegersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-463VPDPWSSD—Multiply and Add Signed Word Integers
Multiplies the individual signed words of the first source  operand by the corresponding signed words of the second 
source operand, producing intermediate signed, doublewo rd results. The adjacent doubleword results are then 
summed and accumulated in the destination operand.
Operation
VPDPWSSD dest, src1, src2 (VEX encoded versions)
VL=(128, 256)KL=VL/32ORIGDEST := DESTFOR i := 0 TO KL-1:
p1dword := SIGN_EXTEND(SRC1.word[2*i+ 0]) * SIGN_EXTEND(SRC2.word[2*i+0] )
p2dword := SIGN_EXTEND(SRC1.word[2*i+ 1]) * SIGN_EXTEND(SRC2.word[2*i+1] )
DEST.dword[i] := OR IGDEST.dword[i] + p1dword + p2dword
DEST[MAX_VL-1:VL] := 0Opcode/
En64/32 
bit Mode 
VEX.128.66.0F38.W0 52 /r 
VPDPWSSD xmm1, xmm2, 
xmm3/m128A V/V AVX-VNNI Multiply groups of 2 pairs signed words in 
xmm3/m128 with corresponding signed words 
of xmm2, summing those products and adding 
them to doubleword  result in xmm1.
VEX.256.66.0F38.W0 52 /r
VPDPWSSD ymm1, ymm2, 
ymm3/m256A V/V AVX-VNNI Multiply groups of 2 pairs signed words in 
ymm3/m256 with corresponding signed words 
of ymm2, summing those products and adding 
them to doubleword  result in ymm1.
EVEX.128.66.0F38.W0 52 /r
VPDPWSSD xmm1{k1}{z}, xmm2, 
AVX512VLMultiply groups of 2 pairs signed words in 
signed words of xmm2, summing those 
products and adding them to doubleword result 
in xmm1, under writemask k1.
EVEX.256.66.0F38.W0 52 /r
VPDPWSSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512_VNNI
ymm3/m256/m32bcst with corresponding signed words of ymm2, summing those 
in ymm1, under writemask k1.
EVEX.512.66.0F38.W0 52 /r
VPDPWSSD zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512_VNNI Multiply groups of 2 pairs signed words in 
signed words of zmm2, summing those 
products and adding them to doubleword result in zmm1, under writemask k1.
AN / A M o d R M : r e g  ( r ,  w ) V E X . v vvv (r) ModRM:r/m (r) N/A
B Full ModRM:reg (r, w) EVEX .vvvv (r) ModRM:r/m (r) N/AVPDPWSSD—Multiply and Add Signed Word IntegersINSTRUCTION SET REFERENCE, V
5-464 Vol. 2CVPDPWSSD dest, src1, src2 (EVEX encoded versions)
IF SRC2 is memory and EVEX.b == 1:
ELSE:
p1dword := SIGN_EXTEND(SRC1.word[2*i]) * SIGN_EXTEND(t.word[0])p2dword := SIGN_EXTEND(SRC1.word[ 2*i+1]) * SIGN_EXTEND(t.word[1])
VPDPWSSD __m128i _mm_dpwssd_avx_e pi32(__m128i, __m128i, __m128i);
VPDPWSSD __m128i _mm_dpwssd_epi 32(__m128i, __m128i, __m128i);
VPDPWSSD __m128i _mm_mask_dpwssd_epi32( __m128i, __mmask8, __m128i, __m128i);
VPDPWSSD __m128i _mm_maskz_dpwssd_epi 32(__mmask8, __m128i, __m128i, __m128i);
VPDPWSSD __m256i _mm256_dpwssd_avx_epi32(__m256i, __m256i, __m256i);VPDPWSSD __m256i _mm256_dpwssd_e pi32(__m256i, __m256i, __m256i);
VPDPWSSD __m256i _mm256_mask_dpwssd_epi 32(__m256i, __mmask8, __m256i, __m256i);
VPDPWSSD __m256i _mm256_maskz_dpwssd_epi 32(__mmask8, __m256i, __m256i, __m256i);
VPDPWSSD __m512i _mm512_dpwssd_e pi32(__m512i, __m512i, __m512i);
VPDPWSSD __m512i _mm512_mask_dpwssd_epi 32(__m512i, __mmask16, __m512i, __m512i);
VPDPWSSD __m512i _mm512_maskz_dpwssd_epi32(__mmask16, __m512i, __m512i, __m512i);
None.
EVEX-encoded instruction, see Table 2-49,  “Type E4 Class Exception Conditions.”VPDPWSSDS—Multiply and Add Signed Word Integers With SaturationINSTRUCTION SET REFERENCE, V
Vol. 2C 5-465VPDPWSSDS—Multiply and Add Signed Word Integers With Saturation 
summed and accumulated in the destination operand. If the intermediate sum overflow s a 32b signed number, the 
result is saturated to either 0x7FFF_FFFF for po sitive numbers of 0x8000_0000 for negative numbers.
En64/32 
bit Mode 
VEX.128.66.0F38.W0 53 /r
VPDPWSSDS xmm1, xmm2, 
xmm3/m128A V/V AVX-VNNI Multiply groups of  2 pairs of signed words in 
them to doubleword re sult in xmm1, with 
signed saturation.
VEX.256.66.0F38.W0 53 /r
VPDPWSSDS ymm1, ymm2, 
ymm3/m256A V/V AVX-VNNI Multiply groups of  2 pairs of signed words in 
of ymm2, summing those products and adding them to doubleword re sult in ymm1, with 
EVEX.128.66.0F38.W0 53 /r
VPDPWSSDS xmm1{k1}{z}, xmm2, 
AVX512VLMultiply groups of 2 pa irs of signed words in 
products and adding them to doubleword result in xmm1, with signed saturation, under 
EVEX.256.66.0F38.W0 53 /r
VPDPWSSDS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512_VNNI
in ymm1, with signed  saturation, under 
EVEX.512.66.0F38.W0 53 /r
VPDPWSSDS zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512_VNNI Multiply groups of  2 pairs of signed words in 
signed words of zmm2, summing those products and adding them to doubleword result 
in zmm1, with signed  saturation, under 
B Full ModRM:reg (r, w) EVEX .vvvv (r) ModRM:r/m (r) N/AVPDPWSSDS—Multiply and Add Signed Word Integers With SaturationINSTRUCTION SET REFERENCE, V
5-466 Vol. 2COperation
VPDPWSSDS dest, src1, src2 (VEX encoded versions)
p1dword := SIGN_EXTEND(SRC1.word[2*i+ 0]) * SIGN_EXTEND(SRC2.word[2*i+0])
p2dword := SIGN_EXTEND(SRC1.word[2*i+ 1]) * SIGN_EXTEND(SRC2.word[2*i+1])
DEST.dword[i] := SIGNED_DWORD_SATURATE( ORIGDEST.dword[i] + p1dword + p2dword)
VPDPWSSDS dest, src1, src2 (EVEX encoded versions)
ELSE:

ELSE:
VPDPWSSDS __m128i _mm_dpwssds_avx_ep i32(__m128i, __m128i, __m128i);
VPDPWSSDS __m128i _mm_dpwssds_epi32(__m128i, __m128i, __m128i);VPDPWSSDS __m128i _mm_mask_dpwssd_epi 32(__m128i, __mmask8, __m128i, __m128i);
VPDPWSSDS __m128i _mm_maskz_dpwssd_epi 32(__mmask8, __m128i, __m128i, __m128i);
VPDPWSSDS __m256i _mm256_dpwssds_avx _epi32(__m256i, __m256i, __m256i);
VPDPWSSDS __m256i _mm256_dpwssd_epi32(__m256i, __m256i, __m256i);VPDPWSSDS __m256i _mm256_mask_dpwssd_epi 32(__m256i, __mmask8, __m256i, __m256i);
VPDPWSSDS __m256i _mm256_maskz_dpwssd_epi 32(__mmask8, __m256i, __m256i, __m256i);
VPDPWSSDS __m512i _mm512_dpwssd_epi32(__m512i, __m512i, __m512i);VPDPWSSDS __m512i _mm512_mask_dpwssd_epi32 (__m512i, __mmask16, __m512i, __m512i);
VPDPWSSDS __m512i _mm512_maskz_dpwssd_epi 32(__mmask16, __m512i,  __m512i, __m512i);
None.
EVEX-encoded instruction, see Table 2-49,  “Type E4 Class Exception Conditions.”VPERM2F128—Permute Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-467VPERM2F128—Permute Floating-Point Values
Permute 128 bit floating-point-containing fields from the first source operand (second operand) and second source 
operand (third operand) using bits in the 8-bit immedi ate and store results in the destination operand (first 
operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit 
memory location, and the destination operand is a YMM register.
Figure 5-21.  VPERM2F128 Operation
Imm8[1:0] select the source for the first destination 128- bit field, imm8[5:4] select the source for the second 
destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.Opcode/
En64/32 
bit Mode 
Feature 
VEX.256.66.0F3A.W0 06 /r ib
VPERM2F128 ymm1, ymm2, ymm3/m256, imm8RV
MIV/V AVX Permute 128-bit floating-point fields in 
ymm2 and ymm3/mem using controls from 
imm8 and store result in ymm1.
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8
DESTSRC1 X0 X1
X0, X1, Y0, or Y1Y0 Y1
X0, X1, Y0, or Y1SRC2VPERM2F128—Permute Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-468 Vol. 2COperation
VPERM2F128
CASE IMM8[1:0] of 0: DEST[127:0] := SRC1[127:0]1: DEST[127:0] := SRC1[255:128]2: DEST[127:0] := SRC2[127:0]3: DEST[127:0] := SRC2[255:128]ESAC
CASE IMM8[5:4] of 
0: DEST[255:128] := SRC1[127:0]1: DEST[255:128] := SRC1[255:128]2: DEST[255:128] := SRC2[127:0]3: DEST[255:128] := SRC2[255:128]ESACIF (imm8[3])DEST[127:0] := 0FI
IF (imm8[7])
DEST[MAXVL-1:128] := 0FI
VPERM2F128:  __m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int control)
VPERM2F128:  __m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int control)
VPERM2F128:  __m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int control)
None.
See Table 2-23, “Type 6 Class Exception Conditions.”
#UD If VEX.L = 0
If VEX.W = 1.VPERM2I128—Permute Integer ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-469VPERM2I128—Permute Integer Values
Permute 128 bit integer data from the first source oper and (second operand) and second source operand (third 
operand) using bits in the 8-bit immediate and store resu lts in the destination operand (first operand). The first 
source operand is a YMM register, the second source oper and is a YMM register or a 256-bit memory location, and 
the destination operand is a YMM register.
Figure 5-22.  VPERM2I128 Operation
En64/32
VEX.256.66.0F3A.W0 46 /r ib
VPERM2I128 ymm1, ymm2, ymm3/m256, imm8RVMI V/V AVX2 Permute 128-bit integer data in ymm2 and 
ymm3/mem using controls from imm8 and 
store result in ymm1.
RVMI ModRM:reg (w) VEX.vvv v (r) ModRM:r/m (r) imm8
X0, X1, Y0, or Y1SRC2VPERM2I128—Permute Integer ValuesINSTRUCTION SET REFERENCE, V
5-470 Vol. 2COperation
VPERM2I128
CASE IMM8[1:0] of 0: DEST[127:0] := SRC1[127:0]1: DEST[127:0] := SRC1[255:128]2: DEST[127:0] := SRC2[127:0]3: DEST[127:0] := SRC2[255:128]ESACCASE IMM8[5:4] of 0: DEST[255:128] := SRC1[127:0]1: DEST[255:128] := SRC1[255:128]2: DEST[255:128] := SRC2[127:0]3: DEST[255:128] := SRC2[255:128]ESACIF (imm8[3])DEST[127:0] := 0FI
DEST[255:128] := 0FI
VPERM2I128: __m256i _mm256_permute2x128_si256 (__m256i a, __m256i b, int control)
None
#UD If VEX.L = 0,
If VEX.W = 1.VPERMB—Permute Packed Bytes ElementsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-471VPERMB—Permute Packed Bytes Elements 
Copies bytes from the second source operand (the third operand) to the destination operand (the first operand) 
according to the byte indices in the first source operand (t he second operand). Note that this instruction permits a 
byte in the source operand to be copied to more than one location in the destination operand. 
Only the low 6(EVEX.512)/5(EVEX.256)/4(EVE X.128) bits of each byte index is us ed to select the location of the 
source byte from the second source operand.
The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM reg-
ister, a 512/256/128-bit memory location. The destinatio n operand is a ZMM/YMM/XMM register updated at byte 
granularity by the writemask k1.
Operation
VPERMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)IF VL = 128:
n := 3;
ELSE IF VL = 256:
n := 4;
ELSE IF VL = 512:
n := 5;
FI;FOR j := 0 TO KL-1:
id := SRC1[j*8 + n : j*8] ; // location of the source byteIF k1[j] OR *no writemask* THEN
DEST[j*8 + 7: j*8] := SRC2[id*8 +7: id*8];
ELSE IF zeroing-masking THEN
DEST[j*8 + 7: j*8] := 0;
*ELSE 
DEST[j*8 + 7: j*8] remains unchanged*
FI
ENDFORDEST[MAX_VL-1:VL] := 0;Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F38.W0 8D /r
VPERMB xmm1 {k1}{z}, xmm2, 
xmm3/m128AV / V A V X 5 1 2 V L
AVX512_VBMIPermute bytes in xmm3/m128 using byte indexes in 
xmm2 and store the result in xmm1 using writemask 
k1.
EVEX.256.66.0F38.W0 8D /r
VPERMB ymm1 {k1}{z}, ymm2, ymm3/m256AV / V A V X 5 1 2 V L
AVX512_VBMIPermute bytes in ymm3/m256 using byte indexes in 
ymm2 and store the result in ymm1 using writemask 
k1.
EVEX.512.66.0F38.W0 8D /r
VPERMB zmm1 {k1}{z}, zmm2, 
zmm3/m512A V/V AVX512_VBMI Permute bytes in zmm3/m512 using byte indexes in 
zmm2 and store the result in zmm1 using writemask 
k1.
A Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPERMB—Permute Packed Bytes ElementsINSTRUCTION SET REFERENCE, V
5-472 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPERMB __m512i _mm512_permutexvar _epi8( __m512i idx, __m512i a);
VPERMB __m512i _mm512_mask_permutexvar_epi8(__m51 2i s, __mmask64 k, __ m512i idx, __m512i a);
VPERMB __m512i _mm512_maskz_permutexvar_epi8( __mmask64 k, __m512i idx, __m512i a);VPERMB __m256i _mm256_permutexvar _epi8( __m256i idx, __m256i a);
VPERMB __m256i _mm256_mask_permutexvar_epi8(__m25 6i s, __mmask32 k, __ m256i idx, __m256i a);
VPERMB __m256i _mm256_maskz_permutexvar_epi8( __mmask32 k, __m256i idx, __m256i a);VPERMB __m128i _mm_permutexvar_epi8( __m128i idx, __m128i a);VPERMB __m128i _mm_mask_permute xvar_epi8(__m128i s, __mmask16 k, __m128i idx, __m128i a);
VPERMB __m128i _mm_maskz_permutexvar_epi8( __mmask16 k, __m128i idx, __m128i a);
None.
See Exceptions Type E4NF.nb in Table 2-50,  “Type E4NF Class Exception Conditions.”VPERMD/VPERMW—Permute Packed Doubleword/Word ElementsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-473VPERMD/VPERMW—Permute Packed Doubleword/Word Elements
Copies doublewords (or words) from the second source operand (the third operand) to the destination operand 
(the first operand) according to the indices in the first source operand (the second operand). Note that this instruc-
tion permits a doubleword (word) in the source operand to be copied to more than one location in the destination 
operand.

None.
operand.
VEX.256 encoded VPERMD: The first and second operands  are YMM registers, the third operand can be a YMM 
register or memory location. Bits (MAXVL-1:256) of  the corresponding destination register are zeroed. 
EVEX encoded VPERMD: The first and second operands are ZMM/YMM registers, the third operand can be a 
ZMM/YMM register, a 512/256-bit memory location or a 512/256-bit vector broadcasted from a 32-bit memory 
location. The elements in the destinat ion are updated using the writemask k1.
VPERMW: first and second operands are ZMM/YMM/XMM registers, the third operand can be a ZMM/YMM/XMM 
register, or a 512/256/128-bit memory location. The destination is updated using the writemask k1.
EVEX.128 encoded versions: Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.Opcode/
En64/32 
bit Mode 
Feature 
VEX.256.66.0F38.W0 36 /r
VPERMD ymm1, ymm2, ymm3/m256A V/V AVX2 Permute doublewords in ymm3/m256 using indices in 
ymm2 and store the result in ymm1.
EVEX.256.66.0F38.W0 36 /r
VPERMD ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcstBV / V A V X 5 1 2 V L
AVX512FPermute doublewords in ymm3/m256/m32bcst using 
indexes in ymm2 and store the result in ymm1 using 
EVEX.512.66.0F38.W0 36 /r
VPERMD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512F Permute doublewords in zmm3/m512/m32bcst using 
indices in zmm2 and store the result in zmm1 using 
EVEX.128.66.0F38.W1 8D /r
VPERMW xmm1 {k1}{z}, xmm2, xmm3/m128CV / V A V X 5 1 2 V L
AVX512BWPermute word integers in xmm3/m128 using indexes 
in xmm2 and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 8D /r
VPERMW ymm1 {k1}{z}, ymm2, ymm3/m256CV / V A V X 5 1 2 V L
AVX512BWPermute word integers in  ymm3/m256 using indexes 
in ymm2 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 8D /r
VPERMW zmm1 {k1}{z}, zmm2, 
zmm3/m512C V/V AVX512BW Permute word integers in zmm3/m512 using indexes 
in zmm2 and store the result in zmm1 using writemask 
k1.
A N/A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
B Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
C Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPERMD/VPERMW—Permute Packed Doubleword/Word ElementsINSTRUCTION SET REFERENCE, V
5-474 Vol. 2COperation
VPERMD (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)IF VL = 256 THEN n := 2; FI;IF VL = 512 THEN n := 3; FI;FOR j := 0 TO KL-1
i := j * 32id := 32*SRC1[i+n:i]IF k1[j] OR *no writemask*
THEN 
THEN DEST[i+31:i] := SRC2[31:0];ELSE DEST[i+31:i] := SRC2[id+31:id];
FI;
ELSE 
FI
FI;
VPERMD (VEX.256 encoded version)
DEST[31:0] := (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];DEST[63:32] := (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];DEST[95:64] := (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];DEST[127:96] := (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];DEST[159:128] := (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];DEST[191:160] := (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];DEST[223:192] := (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];DEST[255:224] := (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];DEST[MAXVL-1:256] := 0
VPERMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)IF VL = 128 THEN n := 2; FI;IF VL = 256 THEN n := 3; FI;IF VL = 512 THEN n := 4; FI;FOR j := 0 TO KL-1
i := j * 16id := 16*SRC1[i+n:i]IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SRC2[id+15:id]ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPERMD/VPERMW—Permute Packed Doubleword/Word ElementsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-475Intel C/C++ Compiler Intrinsic Equivalent
VPERMD __m512i _mm512_permutexvar_epi32( __m512i idx, __m512i a);
VPERMD __m512i _mm512_mask_permutexvar_epi32(__m5 12i s, __mmask16 k, __m512i idx, __m512i a);
VPERMD __m512i _mm512_maskz_permutexvar_epi32( __mmask16 k, __m512i idx, __m512i a);VPERMD __m256i _mm256_permutexvar_epi32( __m256i idx, __m256i a);VPERMD __m256i _mm256_mask_permutexvar_epi32(__m 256i s, __mmask8 k, __m256i idx, __m256i a);
VPERMD __m256i _mm256_maskz_permutexvar_epi32( __mmask8 k, __m256i idx, __m256i a);VPERMW __m512i _mm512_permutexvar _epi16( __m512i idx, __m512i a);
VPERMW __m512i _mm512_mask_permutexvar_epi16(__m512i s, __mmask32 k, __m512i idx, __m512i a);VPERMW __m512i _mm512_maskz_permutexvar_epi 16( __mmask32 k, __m512i idx, __m512i a);
VPERMW __m256i _mm256_permutexvar _epi16( __m256i idx, __m256i a);
VPERMW __m256i _mm256_mask_permutexvar_epi16(__m256i s, __mmask16 k, __m256i idx, __m256i a);VPERMW __m256i _mm256_maskz_permutexvar_epi 16( __mmask16 k, __m256i idx, __m256i a);
VPERMW __m128i _mm_permutexvar_epi16( __m128i idx, __m128i a);VPERMW __m128i _mm_mask_permutexvar_epi16(__m 128i s, __mmask8 k, __m128i idx, __m128i a);
VPERMW __m128i _mm_maskz_permutexvar_ep i16( __mmask8 k, __m128i idx, __m128i a);
None
EVEX-encoded VPERMD , see Table 2-50, “Type E4NF Class Exception Conditions.”
EVEX-encoded VPERMW , see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”
If EVEX.L’L = 0 for VPERMD.VPERMI2B—Full Permute of Bytes From  Two Tables Overwriting the IndexINSTRUCTION SET REFERENCE, V
5-476 Vol. 2CVPERMI2B—Full Permute of Bytes From Two Tables Overwriting the Index
Permutes byte values in the second operand (the first source operand) and the third operand (the second source 
operand) using the byte indices in the first operand (the destination operand) to select byte elements from the 
second or third source operands. The selected byte elem ents are written to the destination at byte granularity 
under the writemask k1. 
The first and second operands are ZMM/YMM/XMM registers.  The first operand contains input indices to select 
elements from the two input tables in the 2nd and 3rd op erands. The first operand is also the destination of the 
result. The third operand can be a ZMM/YMM/XMM register , or a 512/256/128-bit memory location. In each index 
byte, the id bit for table selection is bit 6/5/4, and bits [5:0]/[4:0]/[3:0] selects element within each input table.
Note that these instructions permit a byte value in the sour ce operands to be copied to more than one location in 
the destination operand. Also, the same tables can be reused in subsequent iterations, but the index elements are 
Bits (MAX_VL-1:256/128) of the destination are zeroed for VL=256,128.Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F38.W0 75 /r
VPERMI2B xmm1 {k1}{z}, xmm2, 
AVX512_VBMIPermute bytes in xmm3/m128 and xmm2 using 
byte indexes in xmm1 and store the byte results 
EVEX.256.66.0F38.W0 75 /r
VPERMI2B ymm1 {k1}{z}, ymm2, ymm3/m256AV / V A V X 5 1 2 V L
AVX512_VBMIPermute bytes in ymm3/m256 and ymm2 using 
byte indexes in ymm1 an d store the byte results 
EVEX.512.66.0F38.W0 75 /r
VPERMI2B zmm1 {k1}{z}, zmm2, 
zmm3/m512A V/V AVX512_VBMI Permute bytes in zmm3/m512 and zmm2 using 
byte indexes in zmm1 an d store the byte results 
A Full Mem ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPERMI2B—Full Permute of Bytes From  Two Tables Overwriting the IndexINSTRUCTION SET REFERENCE, V
Vol. 2C 5-477Operation
VPERMI2B (EVEX encoded versions)
id := 3;
id := 4;
id := 5;
FI;TMP_DEST[VL-1:0] := DEST[VL-1:0];FOR j := 0 TO KL-1
off := 8*SRC1[j*8 + id: j*8] ;IF k1[j] OR *no writemask*:
DEST[j*8 + 7: j*8] := TMP_DEST[j*8+i d+1]? SRC2[off+7:off ] : SRC1[off+7:off];
ELSE IF *zeroing-masking*
*ELSE 
FI;
ENDFORDEST[MAX_VL-1:VL] := 0;
VPERMI2B __m512i _mm512_permutex2var_epi8(__m512i a, __m512i idx, __m512i b);

id := 3;
id := 4;
id := 5;
*ELSE 
FI;
VPERMI2B __m512i _mm512_mask2_permutex2var_epi8(__m512i a, __m512i idx, __mmask64 k, __m512i b);VPERMI2B __m512i _mm512_maskz_permutex2var_epi8(__mmask64 k, __m512i a, __m512i idx, __m512i b);VPERMI2B __m256i _mm256_permutex2var_epi8(__m256i a, __m256i idx, __m256i b);VPERMI2B __m256i _mm256_mask2_permutex2var_epi8(__m256i a, __m256i idx, __mmask32 k, __m256i b);VPERMI2B __m256i _mm256_maskz_permutex2var_epi8(__mmask32 k, __m256i a, __m256i idx, __m256i b);VPERMI2B __m128i _mm_permutex2var_epi8(__m128i a, __m128i idx, __m128i b);VPERMI2B __m128i _mm_mask2_permutex2var_epi8(__m128 i a, __m128i idx, __mmask16 k, __m128i b);
VPERMI2B __m128i _mm_maskz_permutex2var_epi8(__mmask16 k, __m128i a, __m128i idx, __m128i b);
None.
See Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the IndexINSTRUCTION SET REFERENCE, V
5-478 Vol. 2CVPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W1 75 /r
VPERMI2W xmm1 {k1}{z}, xmm2, 
xmm3/m128A V/V AVX512VL
AVX512BWPermute word integers from two tables in 
xmm3/m128 and xmm2 using indexes in xmm1 and 
store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 75 /r
VPERMI2W ymm1 {k1}{z}, ymm2, ymm3/m256A V/V AVX512VL
ymm3/m256 and ymm2 using indexes in ymm1 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 75 /r
VPERMI2W zmm1 {k1}{z}, zmm2, 
zmm3/m512AV / V A V X 5 1 2 B W P e r m u t e  w o r d  i n t e gers from two tables in 
zmm3/m512 and zmm2 using indexes in zmm1 and 
store the result in zmm1 using writemask k1.
EVEX.128.66.0F38.W0 76 /r
VPERMI2D xmm1 {k1}{z}, xmm2, 
AVX512FPermute double-words from two tables in 
xmm3/m128/m32bcst and xmm2 using indexes in 
xmm1 and store the result in xmm1 using writemask 
k1.
EVEX.256.66.0F38.W0 76 /r
VPERMI2D ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcst and ymm2 using indexes in 
ymm1 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 76 /r
VPERMI2D zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512F Permute double-w ords from two tables in 
zmm3/m512/m32bcst and zmm2 using indices in 
zmm1 and store the result in zmm1 using writemask 
k1.
EVEX.128.66.0F38.W1 76 /r
VPERMI2Q xmm1 {k1}{z}, xmm2, 
AVX512FPermute quad-words from two tables in 
xmm3/m128/m64bcst and xmm2 using indexes in 
xmm1 and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 76 /r
VPERMI2Q ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcst and ymm2 using indexes in 
EVEX.512.66.0F38.W1 76 /r
VPERMI2Q zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstB V/V AVX512F Permute quad-wor ds from two tables in 
zmm3/m512/m64bcst and zmm2 using indices in 
k1.
EVEX.128.66.0F38.W0 77 /r
VPERMI2PS xmm1 {k1}{z}, xmm2, 
AVX512FPermute single-precision floating-point values from 
two tables in xmm3/m128/m32bcst and xmm2 using 
indexes in xmm1 and store the result in xmm1 using 
EVEX.256.66.0F38.W0 77 /r
VPERMI2PS ymm1 {k1}{z}, ymm2, 
two tables in ymm3/m256/m32bcst and ymm2 using 
indexes in ymm1 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 77 /r
VPERMI2PS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512F Permute single-precision floating-point values from 
two tables in zmm3/m512/m32bcst and zmm2 using 
indices in zmm1 and store the result in zmm1 using writemask k1.VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the IndexINSTRUCTION SET REFERENCE, V
Vol. 2C 5-479Instruction Operand Encoding
Permutes 16-bit/32-bit/64-bit values in the second operan d (the first source operand) and the third operand (the 
second source operand) using indices in the first operand to select elements from the second and third operands. 
The selected elements are written to the destination oper and (the first operand) according to the writemask k1. 
result. 
D/Q/PS/PD element versions: The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit 
memory location or a 512/256/128-bit vector broadcaste d from a 32/64-bit memory location. Broadcast from the 
low 32/64-bit memory location is perfor med if EVEX.b and the id bit for table selection are set (selecting table_2).
Dword/PS versions: The id bit for table selection is bit 4/3/2, depending on VL=512, 256, 128. Bits 
[3:0]/[2:0]/[1:0] of each element in the input index vector select an element within the two source operands, If 
the id bit is 0, table_1 (the first source) is selected; otherwise the second source operand is selected.
Qword/PD versions: The id bit for table selection is bit 3/2/ 1, and bits [2:0]/[1:0] /bit 0 selects element within each 
input table.
Word element versions: The second source operand can be a ZMM/YMM/XMM register, or a 512/256/128-bit 
memory location. The id bit for table selection is bit 5/ 4/3, and bits [4:0]/[3:0]/[2:0] selects element within each 
input table. 
Note that these instructions permit a 16-bit/32-bit/64-bit value in the source operands to be copied to more than 
one location in the destination operand. Note also that in  this case, the same table can be reused for example for a 
second iteration, while the index elements are overwritten.
Bits (MAXVL-1:256/128) of the destination are zeroed for VL=256,128. EVEX.128.66.0F38.W1 77 /r
VPERMI2PD xmm1 {k1}{z}, xmm2, 
AVX512FPermute double precision floating-point values from 
two tables in xmm3/m128/m64bcst and xmm2 using 
EVEX.256.66.0F38.W1 77 /r
VPERMI2PD ymm1 {k1}{z}, ymm2, 
two tables in ymm3/m256/ m64bcst and ymm2 using 
indexes in ymm1 and store the result in ymm1 using 
EVEX.512.66.0F38.W1 77 /r
VPERMI2PD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstB V/V AVX512F Permute double precision floating-point values from 
two tables in zmm3/m512/m64bcst and zmm2 using 
indices in zmm1 and store the result in zmm1 using 
AF u l l  M e mM o d R M : r e g  ( r , w ) E V E X.vvvv (r) ModRM:r/m (r) N/A
En64/32 
bit Mode 
Feature 
FlagDescriptionVPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the IndexINSTRUCTION SET REFERENCE, V
5-480 Vol. 2COperation
VPERMI2W (EVEX encoded versions)
id := 2
id := 3
id := 4
FI;TMP_DEST := DESTFOR j := 0 TO KL-1
i := j * 16off := 16*TMP_DEST[i+id:i]IF k1[j] OR *no writemask*
THEN 
DEST[i+15:i]=TMP_DEST[i+id +1] ? SRC2[off+15:off] 
       : SRC1[off+15:off]
ELSE 
FI
FI;
VPERMI2D/VPERMI2PS (EVEX encoded versions)
id := 1
id := 2
id := 3
i := j * 32off := 32*TMP_DEST[i+id:i]IF k1[j] OR *no writemask*
THEN 
THEN 
DEST[i+31:i]  := TMP_DEST[i+id+1] ? SRC2[31:0] 
       : SRC1[off+31:off]
ELSE 
DEST[i+31:i] := TMP_DEST[i +id+1] ? SRC2[off+31:off] 
       : SRC1[off+31:off]VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the IndexINSTRUCTION SET REFERENCE, V
Vol. 2C 5-481FI 
ELSE 
FI
FI;
VPERMI2Q/VPERMI2PD (EVEX encoded versions)
(KL, VL) = (2, 128),  (4, 256), (8 512)
IF VL = 128
id := 0
id := 1
id := 2
FI;TMP_DEST:= DESTFOR j := 0 TO KL-1
i := j * 64off := 64*TMP_DEST[i+id:i]IF k1[j] OR *no writemask*
THEN 
THEN 
DEST[i+63:i] := TMP_DEST[i+id+1] ? SRC2[63:0] 
       : SRC1[off+63:off]
ELSE 
DEST[i+63:i] := TMP_DEST[i +id+1] ? SRC2[off+63:off] 
FI 
ELSE 

THEN 
THEN 
ELSE 
ELSE 
FI
FI;
IF VL = 128
id := 0
id := 1
id := 2
THEN 
THEN 
ELSE 
FI 
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the IndexINSTRUCTION SET REFERENCE, V
5-482 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPERMI2D __m512i _mm512_permutex2var_epi32(__m512i a, __m512i idx, __m512i b);
VPERMI2D __m512i _mm512_mask_permutex2var_epi32(__ m512i a, __mmask16 k, __m512i idx, __m512i b);
VPERMI2D __m512i _mm512_mask2_permutex2var_epi32( __m512i a, __m512i idx, __mmask16 k, __m512i b);
VPERMI2D __m512i _mm512_maskz_permutex2var_epi32( __mmask16 k, __m512i a, __m512i idx, __m512i b);
VPERMI __m256i _mm256_permutex2var_epi32(__m256i a, __m256i idx, __m256i b);VPERMI2D __m256i _mm256_mask_permutex2var_epi32(__ m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMI2D __m256i _mm256_mask2_permutex2var_epi32( __m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMI2D __m256i _mm256_maskz_permutex2var_epi32( __mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMI2D __m128i _mm_permutex2var_epi 32(__m128i a, __m128i idx, __m128i b);
VPERMI2D __m128i _mm_mask_permu tex2var_epi32(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2D __m128i _mm_mask2_permutex2var_epi32(__m 128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2D __m128i _mm_maskz_permutex2var_epi32(__m mask8 k, __m128i a, __m128i idx, __m128i b);
VPERMI2PD __m512d _mm512_permutex2var_pd(__m512d a, __m512i idx, __m512d b);VPERMI2PD __m512d _mm512_mask_permutex2var_pd(__m512d a, __mmask8 k, __m512i idx, __m512d b);
VPERMI2PD __m512d _mm512_mask2_permutex2var_pd(__m 512d a, __m512i idx, __mmask8 k, __m512d b);
VPERMI2PD __m512d _mm512_maskz_permutex2var_pd(__mmask8 k, __m512d a, __m512i idx, __m512d b);VPERMI2PD __m256d _mm256_permutex2var_pd(__m256d a, __m256i idx, __m256d b);VPERMI2PD __m256d _mm256_mask_permutex2var_pd(__m256d a, __mmask8 k, __m256i idx, __m256d b);VPERMI2PD __m256d _mm256_mask2_permutex2var_pd(__m 256d a, __m256i idx, __mmask8 k, __m256d b);
VPERMI2PD __m256d _mm256_maskz_permutex2var_pd(__mmask8 k, __m256d a, __m256i idx, __m256d b);
VPERMI2PD __m128d _mm_permutex2var_pd(__m128d a, __m128i idx, __m128d b);
VPERMI2PD __m128d _mm_mask_permutex2var_pd(__m1 28d a, __mmask8 k, __m128i idx, __m128d b);
VPERMI2PD __m128d _mm_mask2_permutex2var_pd(__m128 d a, __m128i idx, __mmask8 k, __m128d b);
VPERMI2PD __m128d _mm_maskz_permutex2var_pd(__ mmask8 k, __m128d a, __m128i idx, __m128d b);
VPERMI2PS __m512 _mm512_permutex2var_ps(__m512 a, __m512i idx, __m512 b);
VPERMI2PS __m512 _mm512_mask_permutex2var_ps(__m 512 a, __mmask16 k, __m512i idx, __m512 b);
VPERMI2PS __m512 _mm512_mask2_permutex2var_ps(__m512 a, __m512i idx, __mmask16 k, __m512 b);VPERMI2PS __m512 _mm512_maskz_permutex2var_ps(_ _mmask16 k, __m512 a, __m512i idx, __m512 b);
VPERMI2PS __m256 _mm256_permutex2var_ps(__m256 a, __m256i idx, __m256 b);VPERMI2PS __m256 _mm256_mask_permutex2var_ps( __m256 a, __mmask8 k, __m256i idx, __m256 b);
VPERMI2PS __m256 _mm256_mask2_permutex2var_ps(__m256 a, __m256i idx, __mmask8 k, __m256 b);
VPERMI2PS __m256 _mm256_maskz_permutex2var_ps(__mmask8 k, __m256 a, __m256i idx, __m256 b);
VPERMI2PS __m128 _mm_permutex2var_ps( __m128 a, __m128i idx, __m128 b);
VPERMI2PS __m128 _mm_mask_permutex2var_ps(__m 128 a, __mmask8 k, __m128i idx, __m128 b);
VPERMI2PS __m128 _mm_mask2_permutex2var_ps(__m 128 a, __m128i idx, __mmask8 k, __m128 b);
VPERMI2PS __m128 _mm_maskz_permutex2var_ps(__mmask8 k, __m128 a, __m128i idx, __m128 b);
VPERMI2Q __m512i _mm512_permutex2var_epi64(__m512i a, __m512i idx, __m512i b);
VPERMI2Q __m512i _mm512_mask_permutex2var_epi64( __m512i a, __mmask8 k, __ m512i idx, __m512i b);
VPERMI2Q __m512i _mm512_mask2_permutex2var_epi64( __m512i a, __m512i idx, __mmask8 k, __m512i b);
VPERMI2Q __m512i _mm512_maskz_permutex2var_epi64(__mmask8 k, __m512i a, __m512i idx, __m512i b);VPERMI2Q __m256i _mm256_permutex2var_epi64(__m256i a, __m256i idx, __m256i b);VPERMI2Q __m256i _mm256_mask_permutex2var_epi64( __m256i a, __mmask8 k, __ m256i idx, __m256i b);
VPERMI2Q __m256i _mm256_mask2_permutex2var_epi64( __m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMI2Q __m256i _mm256_maskz_permutex2var_epi64(__mmask8 k, __m256i a, __m256i idx, __m256i b);VPERMI2Q __m128i _mm_permutex2var_epi64(__m128i a, __m128i idx, __m128i b);VPERMI2Q __m128i _mm_mask_permu tex2var_epi64(__m128i a, __mmask 8 k, __m128i idx, __m128i b);
VPERMI2Q __m128i _mm_mask2_permutex2var_epi64( __m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2Q __m128i _mm_maskz_permutex2var_epi64(__ mmask8 k, __m128i a, __m128i idx, __m128i b);VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the IndexINSTRUCTION SET REFERENCE, V
Vol. 2C 5-483VPERMI2W __m512i _mm512_permutex2var_epi1 6(__m512i a, __m512i idx, __m512i b);
VPERMI2W __m512i _mm512_mask_permutex2var_epi16( __m512i a, __mmask32 k, __m512i idx, __m512i b);
VPERMI2W __m512i _mm512_mask2_permutex2var_epi16(__ m512i a, __m512i idx, __mmask32 k, __m512i b);
VPERMI2W __m512i _mm512_maskz_permutex2var_epi16(__m mask32 k, __m512i a, __m512i idx, __m512i b);
VPERMI2W __m256i _mm256_permutex2var_epi1 6(__m256i a, __m256i idx, __m256i b);
VPERMI2W __m256i _mm256_mask_permutex2var_epi16( __m256i a, __mmask16 k, __m256i idx, __m256i b);
VPERMI2W __m256i _mm256_mask2_permutex2var_epi16(__ m256i a, __m256i idx, __mmask16 k, __m256i b);
VPERMI2W __m256i _mm256_maskz_permutex2var_epi16(__m mask16 k, __m256i a, __m256i idx, __m256i b);
VPERMI2W __m128i _mm_permutex2var_epi16(__m128i a, __m128i idx, __m128i b);
VPERMI2W __m128i _mm_mask_permute x2var_epi16(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2W __m128i _mm_mask2_permutex2var_epi16(__m1 28i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2W __m128i _mm_maskz_permutex2var_epi16(__mm ask8 k, __m128i a, __m128i idx, __m128i b);
None.
VPERMI2D/Q/PS/PD: See Table 2-50, “Type E4NF Class Exception Conditions.”
VPERMI2W: See Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-484 Vol. 2CVPERMILPD—Permute In-Lane of Pairs of Do uble Precision Floating-Point Values
InstructionOp / En 64/32 
bit Mode 
Feature 
VEX.128.66.0F38.W0 0D /r
VPERMILPD xmm1, xmm2, xmm3/m128A V/V AVX Permute double precision floating-point values in 
xmm2 using controls from xmm3/m128 and store 
VEX.256.66.0F38.W0 0D /r
VPERMILPD ymm1, ymm2, ymm3/m256A V/V AVX Permute double precision floating-point values in 
ymm2 using controls fr om ymm3/m256 and store 
EVEX.128.66.0F38.W1 0D /r
VPERMILPD xmm1 {k1}{z}, xmm2, 
AVX512FPermute double precision floating-point values in 
xmm2 using control from xmm3/m128/m64bcst 
and store the result in xmm1 using writemask k1. 
EVEX.256.66.0F38.W1 0D /r
VPERMILPD ymm1 {k1}{z}, ymm2, 
ymm2 using control from ymm3/m256/m64bcst 
and store the result in ymm1 using writemask k1. 
EVEX.512.66.0F38.W1 0D /r 
VPERMILPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Permute double precision floating-point values in 
zmm2 using control from zmm3/m512/m64bcst 
and store the result in zmm1 using writemask k1. 
VEX.128.66.0F3A.W0 05 /r ib
VPERMILPD xmm1, xmm2/m128, imm8B V/V AVX Permute double precision floating-point values in 
xmm2/m128 using controls from imm8.
VEX.256.66.0F3A.W0 05 /r ib
VPERMILPD ymm1, ymm2/m256, imm8B V/V AVX Permute double precision floating-point values in 
ymm2/m256 using controls from imm8.
EVEX.128.66.0F3A.W1 05 /r ib
VPERMILPD xmm1 {k1}{z}, 
xmm2/m128/m64bcst, imm8DV / V A V X 5 1 2 V L
xmm2/m128/m64bcst using controls from imm8 
EVEX.256.66.0F3A.W1 05 /r ib
VPERMILPD ymm1 {k1}{z}, 
ymm2/m256/m64bcst, imm8DV / V A V X 5 1 2 V L
ymm2/m256/m64bcst using controls from imm8 
EVEX.512.66.0F3A.W1 05 /r ib
VPERMILPD zmm1 {k1}{z}, zmm2/m512/m64bcst, imm8D V/V AVX512F Permute double precision floating-point values in 
zmm2/m512/m64bcst using controls from imm8 and store the result in zmm1 using writemask k1. 
B N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
D Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-485Description
(variable control version)Permute pairs of double precision floating-point values in  the first source operand (second operand), each using a

(variable control version)Permute pairs of double precision floating-point values in  the first source operand (second operand), each using a 
1-bit control field residing in the corresponding quadword  element of the second source operand (third operand). 
Permuted results are stored in the destination operand (first operand). 
The control bits are located at bit 0 of each quadword el ement (see Figure 5-24). Each control determines which of 
the source element in an input pair is selected for the dest ination element. Each pair of source elements must lie in 
the same 128-bit region as the destination.
EVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit 
memory location or a 512/256/128-bit vector broadcaste d from a 64-bit memory location. Permuted results are 
written to the destination under the writemask.
VEX.256 encoded version: Bits (MAXVL-1:256) of  the corresponding ZMM register are zeroed. 
Immediate control version: Permute pairs of double precision floating-point values in the first source operand 
(second operand), each pair using a 1-bit control field in  the imm8 byte. Each element in the destination operand 
(first operand) use a separate control bit of the imm8 byte.
VEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination 
operand is a YMM/XMM register. Imm8 byte provides the lower 4/2 bit as permute control fields.
EVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory 
location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are written to 
the destination under the writemask.  Imm8 byte provides the lower 8/4/2 bit as permute control fields.
Note: For the imm8 versions, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will 
#UD.Figure 5-23.  VPERMILPD Operation
Figure 5-24.  VPERMILPD Shuffle ControlX2..X3 X2..X3 X0..X1 X0..X1 DESTX3 X2 SRC1 X1 X0
1
sel Bit
. . .ignored
Control Field1 Control Field 2 Control Field 4
ignored65
sel 
ignored194 193
sel 
ignored255
ignored66 127
ignored2 63VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-486 Vol. 2COperation
VPERMILPD (EVEX immediate versions)
(KL, VL) = (8, 512)FOR j := 0 TO KL-1
i := j * 64IF (EVEX.b = 1) AN D (SRC1 *is memory*)
THEN TMP_SRC1[i+63:i] := SRC1[63:0];ELSE TMP_SRC1[i+63:i] := SRC1[i+63:i];
FI;
ENDFOR;IF (imm8[0] = 0) THEN TMP_DE ST[63:0] := SRC1[63:0]; FI;
IF (imm8[0] = 1) THEN TMP_DEST[63:0] := TMP_SRC1[127:64]; FI;IF (imm8[1] = 0) THEN TMP_DEST [127:64] := TMP_SRC1[63:0]; FI;
IF (imm8[1] = 1) THEN TMP_DEST [127:64] := TMP_SRC1[127:64]; FI;
IF VL >= 256
IF (imm8[2] = 0) THEN TMP_DEST[191:128] := TMP_SRC1[191:128]; FI;IF (imm8[2] = 1) THEN TMP_DEST[191:128] := TMP_SRC1[255:192]; FI;IF (imm8[3] = 0) THEN TMP_DEST[255:192] := TMP_SRC1[191:128]; FI;IF (imm8[3] = 1) THEN TMP_DEST[255:192] := TMP_SRC1[255:192]; FI;
IF (imm8[4] = 0) THEN TMP_DEST[319:256] := TMP_SRC1[319:256]; FI;IF (imm8[4] = 1) THEN TMP_DEST[319:256] := TMP_SRC1[383:320]; FI;IF (imm8[5] = 0) THEN TMP_DEST[383:320] := TMP_SRC1[319:256]; FI;IF (imm8[5] = 1) THEN TMP_DEST[383:320] := TMP_SRC1[383:320]; FI;IF (imm8[6] = 0) THEN TMP_DEST[447:384] := TMP_SRC1[447:384]; FI;IF (imm8[6] = 1) THEN TMP_DEST[447:384] := TMP_SRC1[511:448]; FI;IF (imm8[7] = 0) THEN TMP_DEST[511:448] := TMP_SRC1[447:384]; FI;IF (imm8[7] = 1) THEN TMP_DEST[511:448] := TMP_SRC1[511:448]; FI;
FI
FI;
VPERMILPD (256-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0] := SRC1[63:0]
IF (imm8[0] = 1) THEN DE ST[63:0] := SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64] := SRC1[63:0]IF (imm8[1] = 1) THEN DEST[127:64] := SRC1[127:64]IF (imm8[2] = 0) THEN DEST [191:128] := SRC1[191:128]
IF (imm8[2] = 1) THEN DEST [191:128] := SRC1[255:192]
IF (imm8[3] = 0) THEN DEST [255:192] := SRC1[191:128]
IF (imm8[3] = 1) THEN DEST [255:192] := SRC1[255:192]
DEST[MAXVL-1:256] := 0VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-487VPERMILPD (128-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0] := SRC1[63:0]IF (imm8[0] = 1) THEN DEST[63:0] := SRC1[127:64]IF (imm8[1] = 0) THEN DEST[127:64] := SRC1[63:0]IF (imm8[1] = 1) THEN DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
VPERMILPD (EVEX variable versions)
THEN TMP_SRC2[i+63:i] := SRC2[63:0];ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i];
FI;
ENDFOR;
IF (TMP_SRC2[1] = 0) THEN TMP_DEST[63:0] := SRC1[63:0]; FI;
IF (TMP_SRC2[1] = 1) THEN TMP_DEST[63:0] := SRC1[127:64]; FI;IF (TMP_SRC2[65] = 0) THEN TMP_DEST[127:64] := SRC1[63:0]; FI;IF (TMP_SRC2[65] = 1) THEN TMP_DEST[127:64] := SRC1[127:64]; FI;IF VL >= 256
IF (TMP_SRC2[129] = 0) THEN TMP_ DEST[191:128] := SRC1[191:128]; FI;
IF (TMP_SRC2[129] = 1) THEN TMP_ DEST[191:128] := SRC1[255:192]; FI;
IF (TMP_SRC2[193] = 0) THEN TMP_ DEST[255:192] := SRC1[191:128]; FI;
IF (TMP_SRC2[193] = 1) THEN TMP_ DEST[255:192] := SRC1[255:192]; FI;
IF (TMP_SRC2[257] = 0) THEN TMP_ DEST[319:256] := SRC1[319:256]; FI;
IF (TMP_SRC2[257] = 1) THEN TMP_ DEST[319:256] := SRC1[383:320]; FI;
IF (TMP_SRC2[321] = 0) THEN TMP_ DEST[383:320] := SRC1[319:256]; FI;
IF (TMP_SRC2[321] = 1) THEN TMP_ DEST[383:320] := SRC1[383:320]; FI;
IF (TMP_SRC2[385] = 0) THEN TMP_ DEST[447:384] := SRC1[447:384]; FI;
IF (TMP_SRC2[385] = 1) THEN TMP_ DEST[447:384] := SRC1[511:448]; FI;
IF (TMP_SRC2[449] = 0) THEN TMP_ DEST[511:448] := SRC1[447:384]; FI;
IF (TMP_SRC2[449] = 1) THEN TMP_ DEST[511:448] := SRC1[511:448]; FI;
FI;
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-488 Vol. 2CVPERMILPD (256-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0] := SRC1[63:0]IF (SRC2[1] = 1) THEN DEST[63:0] := SRC1[127:64]IF (SRC2[65] = 0) THEN DEST[127:64] := SRC1[63:0]IF (SRC2[65] = 1) THEN DEST[127:64] := SRC1[127:64]IF (SRC2[129] = 0) THEN DE ST[191:128] := SRC1[191:128]
IF (SRC2[129] = 1) THEN DE ST[191:128] := SRC1[255:192]
IF (SRC2[193] = 0) THEN DE ST[255:192] := SRC1[191:128]
IF (SRC2[193] = 1) THEN DE ST[255:192] := SRC1[255:192]
VPERMILPD (128-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0] := SRC1[63:0]IF (SRC2[1] = 1) THEN DEST[63:0] := SRC1[127:64]IF (SRC2[65] = 0) THEN DEST[127:64] := SRC1[63:0]IF (SRC2[65] = 1) THEN DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0
VPERMILPD __m512d _mm512_permute_pd( __m512d a, int imm);
VPERMILPD __m512d _mm512_mask_permute_pd(__m5 12d s, __mmask8 k, __m512d a, int imm);
VPERMILPD __m512d _mm512_maskz_permute_p d( __mmask8 k, __m512d a, int imm);
VPERMILPD __m256d _mm256_mask_permute_pd(__m2 56d  s, __mmask8 k, __m256d a, int imm);
VPERMILPD __m256d _mm256_maskz_permute_p d( __mmask8 k, __m256d a, int imm);
VPERMILPD __m128d _mm_mask_permute_pd(__m128d s, __mmask8 k, __m128d a, int imm);VPERMILPD __m128d _mm_maskz_permute_pd( __mmask8 k, __m128d a, int imm);VPERMILPD __m512d _mm512_permutevar_pd( __m512i i, __m512d a);VPERMILPD __m512d _mm512_mask_permutevar_pd(__m512d s, __mmask8 k, __m512i i, __m512d a);VPERMILPD __m512d _mm512_mas kz_permutevar_pd( __mmask8 k, __m512i i, __m512d a);
VPERMILPD __m256d _mm256_mask_permutevar_pd(__m256d s, __mmask8 k, __m256d i, __m256d a);VPERMILPD __m256d _mm256_mas kz_permutevar_pd( __mmask8 k, __m256d i, __m256d a);
VPERMILPD __m128d _mm_mask_permutevar_pd(__m128d s, __mmask8 k, __m128d i, __m128d a);VPERMILPD __m128d _mm_maskz_permutevar_p d( __mmask8 k, __m128d i, __m128d a);
VPERMILPD __m128d _mm_permute_pd (__m128d a, int control)VPERMILPD __m256d _mm256_permute_pd (__m256d a, int control)VPERMILPD __m128d _mm_permutevar_pd (__m128d a, __m128i control);VPERMILPD __m256d _mm256_permutevar_pd (__m256d a, __m256i control);
None.
#UD If VEX.W = 1.
#UD If either (E)VEX.vvvv != 1111B and with imm8.VPERMILPS—Permute In-Lane of Quadruples of  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-489VPERMILPS—Permute In-Lane of Quadruples of Single Precision Floating-Point Values
bit Mode 
Feature 
VEX.128.66.0F38.W0 0C /r

None.
bit Mode 
Feature 
VEX.128.66.0F38.W0 0C /r 
VPERMILPS xmm1, xmm2, xmm3/m128AV / V A V XP e r m u t e  s i n g l e - p r e c i s i o n  floating-point values in 
xmm2 using controls from xmm3/m128 and 
store result in xmm1.
VEX.128.66.0F3A.W0 04 /r ib
VPERMILPS xmm1, xmm2/m128, imm8BV / V A V XP e r m u t e  s i n g l e - p r e c i s i o n  floating-point values in 
xmm2/m128 using controls from imm8 and store result in xmm1.
VEX.256.66.0F38.W0 0C /r 
VPERMILPS ymm1, ymm2, ymm3/m256AV / V A V XP e r m u t e  s i n g l e - p r e c i s i o n  floating-point values in 
ymm2 using controls from ymm3/m256 and 
VEX.256.66.0F3A.W0 04 /r ib
VPERMILPS ymm1, ymm2/m256, imm8BV / V A V XP e r m u t e  s i n g l e - p r e c i s i o n  floating-point values in 
ymm2/m256 using controls from imm8 and store 
EVEX.128.66.0F38.W0 0C /r
VPERMILPS xmm1 {k1}{z}, xmm2, 
AVX512FPermute single-precision floating-point values 
xmm2 using control from xmm3/m128/m32bcst 
and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 0C /r 
VPERMILPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV / V A V X 5 1 2 V L
ymm2 using control from ymm3/m256/m32bcst and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 0C /r 
VPERMILPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstCV / V A V X 5 1 2 F P e r m u t e  s i n g l e - p r e c i sion floating-point values 
zmm2 using control from zmm3/m512/m32bcst 
and store the result in zmm1 using writemask k1.
EVEX.128.66.0F3A.W0 04 /r ib
VPERMILPS xmm1 {k1}{z}, 
xmm2/m128/m32bcst, imm8DV / V A V X 5 1 2 V L
xmm2/m128/m32bcst using controls from imm8 
EVEX.256.66.0F3A.W0 04 /r ib
VPERMILPS ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8DV / V A V X 5 1 2 V L
ymm2/m256/m32bcst using controls from imm8 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F3A.W0 04 /r 
ibVPERMILPS zmm1 {k1}{z}, 
zmm2/m512/m32bcst, imm8DV / V A V X 5 1 2 F P e r m u t e  s i n g l e - p r e c i sion floating-point values 
zmm2/m512/m32bcst using controls from imm8 
D Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVPERMILPS—Permute In-Lane of Quadruples of  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-490 Vol. 2CDescription
Variable control version:Permute quadruples of single-precision  floating-point values in the first source operand (second operand), each 
quadruplet using a 2-bit control field in the corresponding  dword element of the second source operand. Permuted 
results are stored in the destination operand (first operand). 
The 2-bit control fields are located at the low two bits of  each dword element (see Figure 5-26). Each control deter-
mines which of the source element in an input quadruple is  selected for the destination element. Each quadruple of 
source elements must lie in the same 128-bit region as the destination.
memory location or a 512/256/128-bit vector broadcaste d from a 32-bit memory location. Permuted results are 
(immediate control version)
Permute quadruples of single-precision  floating-point values in the first source operand (second operand), each 
quadruplet using a 2-bit control field in the imm8 byte. Ea ch 128-bit lane in the destination operand (first operand) 
use the four control fields of the same imm8 byte.
operand is a YMM/XMM register. 
location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are written to 
the destination under the writemask.
Note: For the imm8 version, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will 
#UD.Figure 5-25.  VPERMILPS Operation
Figure 5-26.  VPERMILPS Shuffle ControlX7 .. X4 X7 .. X4 X3 ..X0 X3 .. X0 DESTSRC1 X0 X1 X2 X3 X4 X5 X6 X7
X3 .. X0 X7 .. X4 X7 .. X4 X3 ..X0
sel Bit
34 33 32
sel . . .226 225 224
sel ignored
Control Field 1 Control Field 2 Control Field 710 255
ignored ignored63 31VPERMILPS—Permute In-Lane of Quadruples of  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-491Operation
VPERMILPS (EVEX immediate versions)
i := j * 32IF (EVEX.b = 1) AN D (SRC1 *is memory*)
THEN TMP_SRC1[i+31:i] := SRC1[31:0];ELSE TMP_SRC1[i+31:i] := SRC1[i+31:i];
FI;
ENDFOR;
TMP_DEST[31:0] := Select4(TM P_SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] := Select4( TMP_SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] := Select4( TMP_SRC1[127:0], imm8[5:4]);
TMP_DEST[127:96] := Select4(TM P_SRC1[127:0], imm8[7:6]); FI;
IF VL >= 256
TMP_DEST[159:128] := Select4(TMP_SRC1[255:128], imm8[1:0]); FI;TMP_DEST[191:160] := Select4(TMP_SRC1[255:128], imm8[3:2]); FI;TMP_DEST[223:192] := Select4(TMP_SRC1[255:128], imm8[5:4]); FI;TMP_DEST[255:224] := Select4(TMP_SRC1[255:128], imm8[7:6]); FI; 
TMP_DEST[287:256] := Select4(TMP_SRC1[383:256], imm8[1:0]); FI;TMP_DEST[319:288] := Select4(TMP_SRC1[383:256], imm8[3:2]); FI;TMP_DEST[351:320] := Select4(TMP_SRC1[383:256], imm8[5:4]); FI;TMP_DEST[383:352] := Select4(TMP_SRC1[383:256], imm8[7:6]); FI;TMP_DEST[415:384] := Select4(TMP_SRC1[511:384], imm8[1:0]); FI;TMP_DEST[447:416] := Select4(TMP_SRC1[511:384], imm8[3:2]); FI;TMP_DEST[479:448] := Select4(TMP_SRC1[511:384], imm8[5:4]); FI;TMP_DEST[511:480] := Select4(TMP_SRC1[511:384], imm8[7:6]); FI;
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*ELSE DEST[i+31:i] := 0 ;zeroing-masking
FI;
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPERMILPS—Permute In-Lane of Quadruples of  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
5-492 Vol. 2CVPERMILPS (256-bit immediate version)
DEST[95:64] := Select4(SR C1[127:0], imm8[5:4]);
DEST[127:96] := Select4( SRC1[127:0], imm8[7:6]);
DEST[223:192] := Select4( SRC1[255:128], imm8[5:4]);
DEST[255:224] := Select4( SRC1[255:128], imm8[7:6]);
VPERMILPS (128-bit immediate version)
VPERMILPS (EVEX variable versions)
(KL, VL) = (16, 512)FOR j := 0 TO KL-1
THEN TMP_SRC2[i+31:i] := SRC2[31:0];ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i];
FI;
ENDFOR;TMP_DEST[31:0] := Select4(SR C1[127:0], TM P_SRC2[1:0]);
TMP_DEST[63:32] := Select4(SR C1[127:0], TMP_ SRC2[33:32]);
TMP_DEST[95:64] := Select4(SR C1[127:0], TMP_ SRC2[65:64]);
TMP_DEST[127:96] := Select4(SRC1[127:0], TMP_SRC2[97:96]);IF VL >= 256
TMP_DEST[159:128] := Select4(SRC1 [255:128], TMP_ SRC2[129:128]);
TMP_DEST[191:160] := Select4(SRC1 [255:128], TMP_ SRC2[161:160]);
TMP_DEST[223:192] := Select4(SRC1 [255:128], TMP_ SRC2[193:192]);
TMP_DEST[255:224] := Select4(SRC1 [255:128], TMP_ SRC2[225:224]);
TMP_DEST[287:256] := Select4(SRC1 [383:256], TMP_ SRC2[257:256]);
TMP_DEST[319:288] := Select4(SRC1 [383:256], TMP_ SRC2[289:288]);
TMP_DEST[351:320] := Select4(SRC1 [383:256], TMP_ SRC2[321:320]);
TMP_DEST[383:352] := Select4(SRC1 [383:256], TMP_ SRC2[353:352]);
TMP_DEST[415:384] := Select4(SRC1 [511:384], TMP_ SRC2[385:384]);
TMP_DEST[447:416] := Select4(SRC1 [511:384], TMP_ SRC2[417:416]);
TMP_DEST[479:448] := Select4(SRC1 [511:384], TMP_ SRC2[449:448]);
TMP_DEST[511:480] := Select4(SRC1 [511:384], TMP_ SRC2[481:480]);
THEN *DEST[i+31:i] remains unchanged*ELSE DEST[i+31:i] := 0 ;zeroing-maskingVPERMILPS—Permute In-Lane of Quadruples of  Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-493FI;
FI;
VPERMILPS (256-bit variable version)
DEST[31:0] := Select4(SR C1[127:0], SRC2[1:0]);
DEST[63:32] := Select4(SR C1[127:0], SRC2[33:32]);
DEST[95:64] := Select4(SR C1[127:0], SRC2[65:64]);

FI;
DEST[127:96] := Select4(SRC1[127:0], SRC2[97:96]);DEST[159:128] := Select4(SRC1 [255:128], SRC2[129:128]);
DEST[191:160] := Select4(SRC1 [255:128], SRC2[161:160]);
DEST[223:192] := Select4(SRC1 [255:128], SRC2[193:192]);
DEST[255:224] := Select4(SRC1 [255:128], SRC2[225:224]);
VPERMILPS (128-bit variable version)
DEST[95:64] :=Select4(SRC1 [127:0], SRC2[65:64]);
DEST[127:96] := Select4(SRC1[127:0], SRC2[97:96]);DEST[MAXVL-1:128] := 0
VPERMILPS __m512 _mm512_permute_ps( __m512 a, int imm);
VPERMILPS __m512 _mm512_mask_permute_ps(__m 512 s, __mmask16 k, __m512 a, int imm);
VPERMILPS __m512 _mm512_maskz_permute_p s( __mmask16 k, __m512 a, int imm);
VPERMILPS __m256 _mm256_mask_permute_ps(__m256 s, __mmask8 k, __m256 a, int imm);VPERMILPS __m256 _mm256_maskz_permute_p s( __mmask8 k, __m256 a, int imm);
VPERMILPS __m128 _mm_mask_permute_ps(__m128  s, __mmask8 k, __m128 a, int imm);
VPERMILPS __m128 _mm_maskz_permute_ps ( __mmask8 k, __m128 a, int imm);
VPERMILPS __m512 _mm512_permutevar_ps( __m512i i, __m512 a);VPERMILPS __m512 _mm512_mask_permutevar_ps(__ m512 s, __mmask16 k, __m512i i, __m512 a);
VPERMILPS __m512 _mm512_maskz_permutevar_ ps( __mmask16 k, __m512i i, __m512 a);
VPERMILPS __m256 _mm256_mask_permutevar_ps(__m2 56 s, __mmask8 k, __m256 i, __m256 a);
VPERMILPS __m256 _mm256_maskz_permutevar_ ps( __mmask8 k, __m256 i, __m256 a);
VPERMILPS __m128 _mm_mask_permutevar_ps(__m 128 s, __mmask8 k, __m128 i, __m128 a);
VPERMILPS __m128 _mm_maskz_ permutevar_ps( __mmask8 k, __m128 i, __m128 a);
VPERMILPS __m128 _mm_permute_ps (__m128 a, int control);VPERMILPS __m256 _mm256_permute_ps (__m256 a, int control);VPERMILPS __m128 _mm_permutevar_p s (__m128 a, __m128i control);
VPERMILPS __m256 _mm256_permutevar_ ps (__m256 a, __m256i control);
None.
#UD If either (E)VEX.vvvv != 1111B and with imm8.VPERMPD—Permute Double Precision Floating-Point ElementsINSTRUCTION SET REFERENCE, V
5-494 Vol. 2CVPERMPD—Permute Double Precision Floating-Point Elements 
The imm8 version: Copies quadword elements of double precision floating-point values from the source operand 
(the second operand) to the destination operand (the firs t operand) according to the indices specified by the imme-
diate operand (the third operand). Each two-bit value in the immediate byte selects a qword element in the source 
operand. 
VEX version: The source operand can be a YMM register or a memory location. Bits (MAXVL-1:256) of the corre-
In EVEX.512 encoded version, The elements in the destin ation are updated using the writemask k1 and the imm8 
bits are reused as control bits for the upper 256-bit half  when the control bits are coming from immediate. The 
source operand can be a ZMM register, a 512-bit memory lo cation or a 512-bit vector broadcasted from a 64-bit 
memory location.
The imm8 versions: VEX.vvvv and EVEX.vvvv are reserved  and must be 1111b otherwise instructions will #UD.
The vector control version: Copies quadword elements of double precision floating-point values from the second 
source operand (the third operand) to the destination oper and (the first operand) according to the indices in the 
first source operand (the second operand). The first 3 bits of each 64 bit element in the index operand selects which 
quadword in the second source operand to copy. The fi rst and second operands are ZMM registers, the third 
operand can be a ZMM register, a 512-bit memory location  or a 512-bit vector broadcasted from a 64-bit memory 
location. The elements in the destination are updated using the writemask k1.
Note that this instruction permits a qword in the source oper and to be copied to multiple locations in the destination 
operand. 
If VPERMPD is encoded with VEX.L= 0, an attempt to execute the instru ction encoded with VEX.L= 0 will cause an 
bit Mode 
Feature 
VEX.256.66.0F3A.W1 01 /r ib
VPERMPD ymm1, ymm2/m256, imm8A V/V AVX2 Permute double precision floating-point elements in 
ymm2/m256 using indices in imm8 and store the 
EVEX.256.66.0F3A.W1 01 /r ib
VPERMPD ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8B V/V AVX512VL
AVX512FPermute double precision floating-point elements in 
ymm2/m256/m64bcst using indexes in imm8 and store the result in ymm1 subject to writemask k1.
EVEX.512.66.0F3A.W1 01 /r ib
VPERMPD zmm1 {k1}{z}, 
zmm2/m512/m64bcst, imm8B V/V AVX512F Permute double precision floating-point elements in 
zmm2/m512/m64bcst using indices in imm8 and 
EVEX.256.66.0F38.W1 16 /r
VPERMPD ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcst using indexes in ymm2 and 
store the result in ymm1 subject to writemask k1.
EVEX.512.66.0F38.W1 16 /r 
VPERMPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Permute double precision floating-point elements in 
zmm3/m512/m64bcst using indices in zmm2 and 
B Full ModRM:reg (w) ModRM:r/m (r) imm8 N/A
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPERMPD—Permute Double Precision Floating-Point ElementsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-495Operation
VPERMPD (EVEX - imm8 control forms)
i := j * 64IF (EVEX.b = 1) AND (SRC *is memory*)
THEN TMP_SRC[i+63:i] := SRC[63:0];ELSE TMP_SRC[i+63:i] := SRC[i+63:i];
FI;
ENDFOR;
TMP_DEST[63:0] := (TMP_SRC[256:0] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[127:64] := (TMP_SRC[256:0] >> (IMM8[3:2] * 64))[63:0];TMP_DEST[191:128] := (TMP_SRC[256:0] >> (IMM8[5:4] * 64))[63:0];TMP_DEST[255:192] := (TMP_SRC[256:0] >> (IMM8[7:6] * 64))[63:0];IF VL >= 512
TMP_DEST[319:256] := (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];TMP_DEST[383:320] := (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];TMP_DEST[447:384] := (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];TMP_DEST[511:448] := (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];
DEST[i+63:i] := 0 ;zeroing-masking
FI;
FI;
VPERMPD (EVEX - vector control forms)
FI;
ENDFOR;
IF VL = 256
TMP_DEST[63:0] := (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];TMP_DEST[127:64] := (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];TMP_DEST[191:128] := (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];TMP_DEST[255:192] := (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];
TMP_DEST[63:0] := (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];VPERMPD—Permute Double Precision Floating-Point ElementsINSTRUCTION SET REFERENCE, V
5-496 Vol. 2CTMP_DEST[127:64] := (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];
TMP_DEST[191:128] := (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];TMP_DEST[255:192] := (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];TMP_DEST[319:256] := (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];TMP_DEST[383:320] := (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];TMP_DEST[447:384] := (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];TMP_DEST[511:448] := (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];
FI;
FI;
VPERMPD (VEX.256 encoded version)
DEST[63:0] := (SRC[255:0] >> (IMM8[1:0] * 64))[63:0];DEST[127:64] := (SRC[255:0] >> (IMM8[3:2] * 64))[63:0];DEST[191:128] := (SRC[255:0] >> (IMM8[5:4] * 64))[63:0];DEST[255:192] := (SRC[255:0] >> (IMM8[7:6] * 64))[63:0];DEST[MAXVL-1:256] := 0
VPERMPD __m512d _mm512_permutex_pd( __m512d a, int imm);
VPERMPD __m512d _mm512_mask_permutex_pd(__m 512d s, __mmask16 k, __m512d a, int imm);
VPERMPD __m512d _mm512_maskz_permutex_pd ( __mmask16 k, __m512d a, int imm);
VPERMPD __m512d _mm512_permutexvar_pd( __m512i i, __m512d a);VPERMPD __m512d _mm512_mask_permutexvar_pd(__m 512d s, __mmask16 k, __m512i i, __m512d a);

FI;
FI;
VPERMPD __m512d _mm512_maskz_permutexvar_p d( __mmask16 k, __m512i i, __m512d a);
VPERMPD __m256d _mm256_permutex_epi64( __m256d a, int imm);VPERMPD __m256d _mm256_mask_permutex_epi64(__m2 56i s, __mmask8 k, __m256d a, int imm);
VPERMPD __m256d _mm256_maskz_permutex_ep i64( __mmask8 k, __m256d a, int imm);
VPERMPD __m256d _mm256_permutexvar _epi64( __m256i i, __m256d a);
VPERMPD __m256d _mm256_mask_permutexvar_epi64( __m256i s, __mmask8 k, __m256i i, __m256d a);
VPERMPD __m256d _mm256_maskz_permutexvar_e pi64( __mmask8 k, __m256i i, __m256d a);
None.
Non-EVEX-encoded instruction, see Table 2-21, “T ype 4 Class Exception Conditions”; additionally:
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions”; additionally:
#UD If encoded with EVEX.128.
If EVEX.vvvv != 1 111B and with imm8.VPERMPS—Permute Single Precision Floating-Point ElementsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-497VPERMPS—Permute Single Precis ion Floating-Point Elements 
Copies doubleword elements of single-precision floating-p oint values from the second source operand (the third 
operand) to the destination operand (the first operand) a ccording to the indices in the first source operand (the 
second operand). Note that this instruction permits a doubleword in the source operand to be copied to more than 
one location in the destination operand.
VEX.256 versions: The first and second operands are YMM registers, the third operand can be a YMM register or 
memory location. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.
EVEX encoded version: The first and second operands are ZMM registers, the third operand can be a ZMM register, 
a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The elements in the 
destination are updated using the writemask k1.
If VPERMPS is encoded with VEX.L= 0, an attempt to ex ecute the instruction encoded with VEX.L= 0 will cause an 
Operation
VPERMPS (EVEX forms)
(KL, VL) (8, 256),= (16, 512)FOR j := 0 TO KL-1
FI;
ENDFOR;
IF VL = 256
TMP_DEST[31:0] := (TMP_SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];TMP_DEST[63:32] := (TMP_SRC2[255:0]  >> (SRC1[34:32] * 32))[31:0];
TMP_DEST[95:64] := (TMP_SRC2[255:0]  >> (SRC1[66:64] * 32))[31:0];
TMP_DEST[127:96] := (TMP_SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];TMP_DEST[159:128] := (TMP_SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];TMP_DEST[191:160] := (TMP_SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];TMP_DEST[223:192] := (TMP_SRC2[255:0] >> (SRC1[193:192] * 32))[31:0];Opcode/
En64/32 
bit Mode 
Feature 
VEX.256.66.0F38.W0 16 /r
VPERMPS ymm1, ymm2, 
ymm3/m256A V/V AVX2 Permute single-precision floating-point elements in 
ymm3/m256 using indices in ymm2 and store the result in 
ymm1.
EVEX.256.66.0F38.W0 16 /r
VPERMPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstB V/V AVX512VL
AVX512FPermute single-precision floating-point elements in 
ymm3/m256/m32bcst using indexes in ymm2 and store the result in ymm1 subject to write mask k1.
EVEX.512.66.0F38.W0 16 /r
VPERMPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512F Permute single-precision floating-point values in 
zmm3/m512/m32bcst using indices in zmm2 and store the 
result in zmm1 subject to write mask k1.
B Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPERMPS—Permute Single Precision Floating-Point ElementsINSTRUCTION SET REFERENCE, V
5-498 Vol. 2CTMP_DEST[255:224] := (TMP_SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
TMP_DEST[31:0] := (TMP_SRC2[511:0] >> (SRC1[3:0] * 32))[31:0];TMP_DEST[63:32] := (TMP_SRC2[511:0] >> (SRC1[35:32] * 32))[31:0];TMP_DEST[95:64] := (TMP_SRC2[511:0] >> (SRC1[67:64] * 32))[31:0];TMP_DEST[127:96] := (TMP_SRC2[511:0] >> (SRC1[99:96] * 32))[31:0];TMP_DEST[159:128] := (TMP_SRC2[511:0] >> (SRC1[131:128] * 32))[31:0];TMP_DEST[191:160] := (TMP_SRC2[511:0] >> (SRC1[163:160] * 32))[31:0];TMP_DEST[223:192] := (TMP_SRC2[511:0] >> (SRC1[195:192] * 32))[31:0];TMP_DEST[255:224] := (TMP_SRC2[511:0] >> (SRC1[227:224] * 32))[31:0];TMP_DEST[287:256] := (TMP_SRC2[511:0] >> (SRC1[259:256] * 32))[31:0];TMP_DEST[319:288] := (TMP_SRC2[511:0] >> (SRC1[291:288] * 32))[31:0];TMP_DEST[351:320] := (TMP_SRC2[511:0] >> (SRC1[323:320] * 32))[31:0];TMP_DEST[383:352] := (TMP_SRC2[511:0] >> (SRC1[355:352] * 32))[31:0];TMP_DEST[415:384] := (TMP_SRC2[511:0] >> (SRC1[387:384] * 32))[31:0];TMP_DEST[447:416] := (TMP_SRC2[511:0] >> (SRC1[419:416] * 32))[31:0];TMP_DEST[479:448] :=(TMP_SRC2[511:0] >> (SRC1[451:448] * 32))[31:0];TMP_DEST[511:480] := (TMP_SRC2[511:0] >> (SRC1[483:480] * 32))[31:0];
DEST[i+31:i] := 0 ;zeroing-masking
FI;
FI;
VPERMPS (VEX.256 encoded version)
VPERMPS __m512 _mm512_permute xvar_ps(__m512i i, __m512 a);
VPERMPS __m512 _mm512_mask_permutexvar_ps(__m 512 s, __mmask16 k, __m512i i, __m512 a);
VPERMPS __m512 _mm512_maskz_permutexvar_p s( __mmask16 k, __m512i i, __m512 a);
VPERMPS __m256 _mm256_permute xvar_ps(__m256 i, __m256 a);
VPERMPS __m256 _mm256_mask_permutexvar_ps( __m256 s, __mmask8 k, __m256 i, __m256 a);
VPERMPS __m256 _mm256_maskz_permutexvar _ps( __mmask8 k, __m256 i, __m256 a);VPERMPS—Permute Single Precision Floating-Point ElementsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-499SIMD Floating-Point Exceptions
None.
#UD If VEX.L = 0.EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”VPERMQ—Qwords Element PermutationINSTRUCTION SET REFERENCE, V
5-500 Vol. 2CVPERMQ—Qwords Element Permutation 
The imm8 version: Copies quadwords from the source operand (the second operand) to the destination operand 
(the first operand) according to the indices specified by  the immediate operand (the third operand). Each two-bit 
value in the immediate byte selects a qword element in the source operand. 
Immediate control versions: VEX.vvvv and EVEX.vvvv are rese rved and must be 1111b otherwise instructions will 
#UD.
The vector control version: Copies quadwords from the se cond source operand (the third operand) to the destina-
tion operand (the first operand) according to the indices in the first source operand (the second operand). The first 3 bits of each 64 bit element in the index operand select s which quadword in the second source operand to copy. 
The first and second operands are ZMM registers, the thir d operand can be a ZMM register, a 512-bit memory loca-
tion or a 512-bit vector broadcasted from a 64-bit memory  location. The elements in the destination are updated 
using the writemask k1.
operand. 
If VPERMPQ is encoded with VEX.L= 0 or EVEX.128, an attempt to execute th e instruction will cause an #UD excep-
tion.Opcode/
bit Mode 
Feature 
VEX.256.66.0F3A.W1 00 /r ib
VPERMQ ymm1, ymm2/m256, imm8A V/V AVX2 Permute qwords in ymm2/m256 using indices in 
imm8 and store the result in ymm1.
EVEX.256.66.0F3A.W1 00 /r ib
VPERMQ ymm1 {k1}{z}, 
ymm2/m256/m64bcst, imm8BV / V A V X 5 1 2 V L
AVX512FPermute qwords in ymm2/m256/m64bcst using 
indexes in imm8 and store the result in ymm1.
EVEX.512.66.0F3A.W1 00 /r ib
VPERMQ zmm1 {k1}{z},

operand. 
bit Mode 
Feature 
VPERMQ zmm1 {k1}{z}, 
zmm2/m512/m64bcst, imm8B V/V AVX512F Permute qwords in zmm2/m512/m64bcst using 
indices in imm8 and store the result in zmm1.
EVEX.256.66.0F38.W1 36 /r
VPERMQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV / V A V X 5 1 2 V L
AVX512FPermute qwords in ymm3/m256/m64bcst using 
indexes in ymm2 and stor e the result in ymm1.
EVEX.512.66.0F38.W1 36 /r 
VPERMQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512F Permute qwords in zmm3/m512/m64bcst using 
indices in zmm2 and store the result in zmm1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPERMQ—Qwords Element PermutationINSTRUCTION SET REFERENCE, V
Vol. 2C 5-501Operation
VPERMQ (EVEX - imm8 control forms)
FI;
ENDFOR;
TMP_DEST[63:0] := (TMP_SRC[255:0] >> (IMM8[1:0] * 64))[63:0];TMP_DEST[127:64] := (TMP_SRC[255:0] >> (IMM8[3:2] * 64))[63:0];TMP_DEST[191:128] := (TMP_SRC[255:0] >> (IMM8[5:4] * 64))[63:0];TMP_DEST[255:192] := (TMP_SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
IF VL >= 512
FI;
FI;
VPERMQ (EVEX - vector control forms)
FI;
ENDFOR;IF VL = 256
TMP_DEST[63:0] := (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];TMP_DEST[127:64] := (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];TMP_DEST[191:128] := (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];TMP_DEST[255:192] := (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];VPERMQ—Qwords Element PermutationINSTRUCTION SET REFERENCE, V
5-502 Vol. 2CTMP_DEST[319:256] := (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];
TMP_DEST[383:320] := (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];TMP_DEST[447:384] := (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];TMP_DEST[511:448] := (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];
FI;
FI;
VPERMQ (VEX.256 encoded version)
VPERMQ __m512i _mm512_permutex_epi64( __m512i a, int imm);
VPERMQ __m512i _mm512_mask_permutex_epi64( __m512i s, __mmask8 k, __m512i a, int imm);
VPERMQ __m512i _mm512_maskz_permutex_ep i64( __mmask8 k, __m512i a, int imm);
VPERMQ __m512i _mm512_permutexv ar_epi64( __m512i a, __m512i b);
VPERMQ __m512i _mm512_mask_permutexvar_epi64( __m512i s, __mmask8 k, __m512i a, __m512i b);
VPERMQ __m512i _mm512_maskz_permutexvar_epi 64( __mmask8 k, __m512i a, __m512i b);
VPERMQ __m256i _mm256_permutex_epi64( __m256i a, int imm);VPERMQ __m256i _mm256_mask_permutex_epi64( __m256i s, __mmask8 k, __m256i a, int imm);
VPERMQ __m256i _mm256_maskz_permutex_ep i64( __mmask8 k, __m256i a, int imm);
VPERMQ __m256i _mm256_permutexv ar_epi64( __m256i a, __m256i b);
VPERMQ __m256i _mm256_mask_permutexvar_epi64( __m256i s, __mmask8 k, __m256i a, __m256i b);
VPERMQ __m256i _mm256_maskz_permutexvar_epi 64( __mmask8 k, __m256i a, __m256i b);
None.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”
Additionally:#UD If encoded with EVEX.128.
If EVEX.vvvv != 1 111B and with imm8.VPERMT2B—Full Permute of Bytes From  Two Tables Overwriting a TableINSTRUCTION SET REFERENCE, V
Vol. 2C 5-503VPERMT2B—Full Permute of Bytes From Two Tables Overwriting a Table
Permutes byte values from two tables, comprising of the first operand (also the destination operand) and the third 
operand (the second source operand). The second operand (the first source operand) provides byte indices to 
select byte results from the two tables. The selected byte  elements are written to the destination at byte granu-
larity under the writemask k1. 
The first and second operands are ZMM/YMM/XMM registers.  The second operand contains input indices to select 
elements from the two input tables in the 1st and 3rd op erands. The first operand is also the destination of the 
result. The second source operand can be a ZMM/YMM/X MM register, or a 512/256/128-bit memory location. In 
each index byte, the id bit for table selection is bit 6/ 5/4, and bits [5:0]/[4:0]/[3:0] selects element within each 
the destination operand. Also, the second table and the indices can be reused in subsequent iterations, but the first 
table is overwritten.
InstructionOp
/
En64/32 
bit Mode 
EVEX.128.66.0F38.W0 7D /r
VPERMT2B xmm1 {k1}{z}, xmm2, 
AVX512_VBMIPermute bytes in xmm3/m128 and xmm1 using byte 
indexes in xmm2 and store the byte results in xmm1 
EVEX.256.66.0F38.W0 7D /r
VPERMT2B ymm1 {k1}{z}, ymm2, ymm3/m256A V/V AVX512VL
AVX512_VBMIPermute bytes in ymm3/m256 and ymm1 using byte 
indexes in ymm2 and store the byte results in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 7D /r
VPERMT2B zmm1 {k1}{z}, zmm2, 
zmm3/m512A V/V AVX512_VBMI Permute bytes in zmm3/m512 and zmm1 using byte 
indexes in zmm2 and store the byte results in zmm1 
A Full Mem ModRM:reg (r, w) EV EX.vvvv (r) ModRM:r/m (r) N/AVPERMT2B—Full Permute of  Bytes From Two Tables  Overwriting a TableINSTRUCTION SET REFERENCE, V
5-504 Vol. 2COperation
VPERMT2B (EVEX encoded versions)
id := 3;
id := 4;
id := 5;
DEST[j*8 + 7: j*8] := SR C1[j*8+id+1]? SRC2[off+7:o ff] : TMP_DEST [off+7:off];
*ELSE 
FI;
VPERMT2B __m512i _mm512_permutex2var_epi8(__m512i a, __m512i idx, __m512i b);
VPERMT2B __m512i _mm512_mask_permutex2var_epi8(__m512i a, __mmask64 k, __m512i idx, __m512i b);VPERMT2B __m512i _mm512_maskz_per mutex2var_epi8(__mmask64 k, __m512i a, __m512i idx, __m512i b);
VPERMT2B __m256i _mm256_permutex2var_epi8(__m256i a, __m256i idx, __m256i b);VPERMT2B __m256i _mm256_mask_permutex2var_epi8(__m256i a, __mmask32 k, __m256i idx, __m256i b);VPERMT2B __m256i _mm256_maskz_per mutex2var_epi8(__mmask32 k, __m256i a, __m256i idx, __m256i b);
VPERMT2B __m128i _mm_permutex2var_epi8(__m128i a, __m128i idx, __m128i b);VPERMT2B __m128i _mm_mask_permute x2var_epi8(__m128i a, __mmask16 k, __m128i idx, __m128i b);
VPERMT2B __m128i _mm_maskz_permutex2var_epi8(__m mask16 k, __m128i a, __m128i idx, __m128i b);
None.
See Exceptions Type E4NF.nb in Table 2-50,  “Type E4NF Class Exception Conditions.”VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One TableINSTRUCTION SET REFERENCE, V
Vol. 2C 5-505VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One Table
Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W1 7D /r
VPERMT2W xmm1 {k1}{z}, xmm2, 
AVX512BWPermute word integers from  two tables in xmm3/m128

None.
Opcode/
En64/32 
bit Mode 
Feature 
AVX512BWPermute word integers from  two tables in xmm3/m128 
and xmm1 using indexes in xmm2 and store the result in 
EVEX.256.66.0F38.W1 7D /r
VPERMT2W ymm1 {k1}{z}, ymm2, ymm3/m256A V/V AVX512VL
AVX512BWPermute word integers from  two tables in ymm3/m256 
and ymm1 using indexes in ymm2 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 7D /r
VPERMT2W zmm1 {k1}{z}, zmm2, 
zmm3/m512A V/V AVX512BW Permute word integers from two tables in zmm3/m512 
and zmm1 using indexes in zmm2 and store the result in 
EVEX.128.66.0F38.W0 7E /r
VPERMT2D xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcst and xmm1 using indexes in xmm2 
EVEX.256.66.0F38.W0 7E /r
VPERMT2D ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcst and ymm1 using indexes in ymm2 
and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 7E /r
VPERMT2D zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstB V/V AVX512F Permute double-words from two tables in 
zmm3/m512/m32bcst and zmm1 using indices in zmm2 and store the result in zmm1 using writemask k1.
EVEX.128.66.0F38.W1 7E /r
VPERMT2Q xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcst and xmm1 using indexes in xmm2 
EVEX.256.66.0F38.W1 7E /r
VPERMT2Q ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcst and ymm1 using indexes in ymm2 
EVEX.512.66.0F38.W1 7E /r
VPERMT2Q zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstB V/V AVX512F Permute quad-words from two tables in 
zmm3/m512/m64bcst and zmm1 using indices in zmm2 and store the result in zmm1 using writemask k1.
EVEX.128.66.0F38.W0 7F /r
VPERMT2PS xmm1 {k1}{z}, 
AVX512FPermute single-precision floating-point values from two 
tables in xmm3/m128/m32bcst and xmm1 using indexes in 
xmm2 and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 7F /r
VPERMT2PS ymm1 {k1}{z}, 
tables in ymm3/m256/m32bcst and ymm1 using indexes in 
ymm2 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 7F /r
VPERMT2PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstB V/V AVX512F Permute single-precision floating-point values from two 
tables in zmm3/m512/m32bcst and zmm1 using indices in zmm2 and store the result in  zmm1 using writemask k1.
EVEX.128.66.0F38.W1 7F /r
VPERMT2PD xmm1 {k1}{z}, 
AVX512FPermute double precision floating-point values from two 
tables in xmm3/m128/m64bcst and xmm1 using indexes in 
EVEX.256.66.0F38.W1 7F /r
VPERMT2PD ymm1 {k1}{z}, 
tables in ymm3/m256/m64bcst and ymm1 using indexes in 
EVEX.512.66.0F38.W1 7F /r
VPERMT2PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstB V/V AVX512F Permute double precision floating-point values from two 
tables in zmm3/m512/m64bcst and zmm1 using indices in zmm2 and store the result in  zmm1 using writemask k1.VPERMT2W/D/Q/PS/PD—Full Permute From  Two Tables Overwriting One TableINSTRUCTION SET REFERENCE, V
5-506 Vol. 2CInstruction Operand Encoding
Permutes 16-bit/32-bit/64-bit values in the first operand and the third operand (the second source operand) using 
indices in the second operand (the first source operand) to select elements from the first and third operands. The 
selected elements are written to the destination operan d (the first operand) according to the writemask k1. 
The first and second operands are ZMM/YMM/XMM registers. The second operand contains input indices to select 
result. 
D/Q/PS/PD element versions: The second source operan d can be a ZMM/YMM/XMM register, a 512/256/128-bit 
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. Broadcast from the 
the id bit is 0, table_1 (the first source) is select ed; otherwise the second source operand is selected.
Qword/PD versions: The id bit for table selection is bit 3/2/1, and bits [2:0]/[1:0] /bit 0 selects element within each 
Note that these instructions permit a 16-bit/32-bit/64-bit va lue in the source operands to be copied to more than 
one location in the destination operand. Note also that in  this case, the same index can be reused for example for 
a second iteration, while the table elements being permuted are overwritten.
Bits (MAXVL-1:256/128) of the destination are zeroed for VL=256,128. 
Operation
VPERMT2W (EVEX encoded versions)
id := 2
id := 3
id := 4
i := j * 16off := 16*SRC1[i+id:i]IF k1[j] OR *no writemask*
THEN 
DEST[i+15:i]=SRC1[i+id+1 ] ? SRC2[off+15:off] 
       : TMP_DEST[off+15:off]
ELSE 
THEN *DEST[i+15:i] remains unchanged*ELSE ; zeroing-maskingOp/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A Full Mem ModRM:reg (r,w) EVE X.vvvv (r) ModRM:r/m (r) N/A
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One TableINSTRUCTION SET REFERENCE, V
Vol. 2C 5-507DEST[i+15:i] := 0
FI
FI;
VPERMT2D/VPERMT2PS (EVEX encoded versions)
id := 1
id := 2
id := 3
i := j * 32off := 32*SRC1[i+id:i]IF k1[j] OR *no writemask*
THEN 
THEN 
DEST[i+31:i] := SRC1[i+id+1] ? SRC2[31:0] 
       : TMP_DEST[off+31:off]
ELSE 
DEST[i+31:i] := SRC1[i+id+1] ? SRC2[off+31:off]        : TMP_DEST[off+31:off]
FI
ELSE 
FI
FI;
VPERMT2Q/VPERMT2PD (EVEX encoded versions)
IF VL = 128
id := 0
id := 1
id := 2
FI;TMP_DEST:= DESTFOR j := 0 TO KL-1VPERMT2W/D/Q/PS/PD—Full Permute From  Two Tables Overwriting One TableINSTRUCTION SET REFERENCE, V
5-508 Vol. 2Ci := j * 64
off := 64*SRC1[i+id:i]IF k1[j] OR *no writemask*
THEN 
THEN 
DEST[i+63:i] := SRC1[i +id+1] ? SRC2[63:0] 
       : TMP_DEST[off+63:off]
ELSE 
DEST[i+63:i] := SRC1[i+id+1] ? SRC2[off+63:off]        : TMP_DEST[off+63:off]
FI
ELSE 
FI
FI;
VPERMT2D __m512i _mm512_permutex2var_epi32(__m512i a, __m512i idx, __m512i b);
VPERMT2D __m512i _mm512_mask_permutex2var_epi32(__m512i a, __mmask16 k, __m512i idx, __m512i b);VPERMT2D __m512i _mm512_mask2_permutex2var_epi32(__ m512i a, __m512i idx, __m mask16 k, __m512i b);
VPERMT2D __m512i _mm512_maskz_permutex2var_epi32(__m mask16 k, __m512i a, __m512i idx, __m512i b);
VPERMT2D __m256i _mm256_permutex2var_epi32(__m256i a, __m256i idx, __m256i b);VPERMT2D __m256i _mm256_mask_permutex2var_epi32(__m 256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMT2D __m256i _mm256_mask2_permutex2var_epi32(__ m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMT2D __m256i _mm256_maskz_permutex2var_epi32( __mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMT2D __m128i _mm_permutex2var_epi32(__m128i a, __m128i idx, __m128i b);VPERMT2D __m128i _mm_mask_permute x2var_epi32(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMT2D __m128i _mm_mask2_permut ex2var_epi32(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMT2D __m128i _mm_maskz_permutex2var_epi32(__m mask8 k, __m128i a, __m128i idx, __m128i b);
VPERMT2PD __m512d _mm512_permutex2var_ pd(__m512d a, __m512i idx, __m512d b);
VPERMT2PD __m512d _mm512_mask_permutex2var_pd(__ m512d a, __mmask8 k, __m512i idx, __m512d b);
VPERMT2PD __m512d _mm512_mask2_permutex2var_pd(__m 512d a, __m512i idx, __mmask8 k, __m512d b);

VPERMT2PD __m512d _mm512_maskz_permutex2var_pd(__m mask8 k, __m512d a, __m512i idx, __m512d b);
VPERMT2PD __m256d _mm256_permutex2var_ pd(__m256d a, __m256i idx, __m256d b);
VPERMT2PD __m256d _mm256_mask_permutex2var_pd(__ m256d a, __mmask8 k, __m256i idx, __m256d b);
VPERMT2PD __m256d _mm256_mask2_permutex2var_pd(__m 256d a, __m256i idx, __mmask8 k, __m256d b);
VPERMT2PD __m256d _mm256_maskz_permutex2var_pd(__m mask8 k, __m256d a, __m256i idx, __m256d b);
VPERMT2PD __m128d _mm_permutex2var_pd( __m128d a, __m128i idx, __m128d b);
VPERMT2PD __m128d _mm_mask_permutex2var_pd(__m 128d a, __mmask8 k, __m128i idx, __m128d b);
VPERMT2PD __m128d _mm_mask2_permutex2var_pd(__m 128d a, __m128i idx, __mmask8 k, __m128d b);
VPERMT2PD __m128d _mm_maskz_perm utex2var_pd(__mmask8 k, __m128d a, __m128i idx, __m128d b);
VPERMT2PS __m512 _mm512_permutex2var_ps(__m512 a, __m512i idx, __m512 b);VPERMT2PS __m512 _mm512_mask_permutex2var_ps(__ m512 a, __mmask16 k, __m512i idx, __m512 b);
VPERMT2PS __m512 _mm512_mask2_permutex2var_ps(__m 512 a, __m512i idx, __mmask16 k, __m512 b);
VPERMT2PS __m512 _mm512_maskz_permutex2var_ps( __mmask16 k, __m512 a, __m512i idx, __m512 b);VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One TableINSTRUCTION SET REFERENCE, V
Vol. 2C 5-509VPERMT2PS __m256 _mm256_permutex2var_ps(__m256 a, __m256i idx, __m256 b);
VPERMT2PS __m256 _mm256_mask_permutex2var_ps(__ m256 a, __mmask8 k, __m256i idx, __m256 b);
VPERMT2PS __m256 _mm256_mask2_permutex2var_ps( __m256 a, __m256i idx, __mmask8 k, __m256 b);
VPERMT2PS __m256 _mm256_maskz_permutex2var_ps(__mmask8 k, __m256 a, __m256i idx, __m256 b);
VPERMT2PS __m128 _mm_permutex2var_ps(__m128 a, __m128i idx, __m128 b);VPERMT2PS __m128 _mm_mask_permutex2var_ps(__m128 a, __mmask8 k, __m128i idx, __m128 b);VPERMT2PS __m128 _mm_mask2_pe rmutex2var_ps(__m128 a, __m128i  idx, __mmask8 k, __m128 b);
VPERMT2PS __m128 _mm_maskz_permutex2var_ps(__m mask8 k, __m128 a, __m128i idx, __m128 b);
VPERMT2Q __m512i _mm512_permutex2var_epi64(__m512i a, __m512i idx, __m512i b);
VPERMT2Q __m512i _mm512_mask_permutex2var_epi64(__m512i a, __mmask8 k, __m512i idx, __m512i b);
VPERMT2Q __m512i _mm512_mask2_permutex2var_epi64(__m 512i a, __m512i idx, __mmask8 k, __m512i b);
VPERMT2Q __m512i _mm512_maskz_permutex2var_epi64( __mmask8 k, __m512i a, __m512i idx, __m512i b);
VPERMT2Q __m256i _mm256_permutex2var_epi64(__m256i a, __m256i idx, __m256i b);VPERMT2Q __m256i _mm256_mask_permutex2var_epi64(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMT2Q __m256i _mm256_mask2_permutex2var_epi64(__m 256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMT2Q __m256i _mm256_maskz_permutex2var_epi64( __mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMT2Q __m128i _mm_permutex2var_epi 64(__m128i a, __m128i idx, __m128i b);
VPERMT2Q __m128i _mm_mask_permu tex2var_epi64(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMT2Q __m128i _mm_mask2_permutex2var_epi64(__m128i a, __m128i idx, __mmask8 k, __m128i b);VPERMT2Q __m128i _mm_maskz_permutex2var_epi64( __mmask8 k, __m128i a, __m128i idx, __m128i b);
VPERMT2W __m512i _mm512_permutex2var_epi16(__m512i a, __m512i idx, __m512i b);
VPERMT2W __m512i _mm512_mask_permutex2var_epi16(_ _m512i a, __mmask32 k, __m 512i idx, __m512i b);
VPERMT2W __m512i _mm512_mask2_permutex2var_epi16(__m512i a, __m512i idx, __mmask32 k, __m512i b);VPERMT2W __m512i _mm512_maskz_permutex2var_epi16(__mmask32 k, __m512i a, __m512i idx, __m512i b);VPERMT2W __m256i _mm256_permutex2var_epi16(__m256i a, __m256i idx, __m256i b);
VPERMT2W __m256i _mm256_mask_permutex2var_epi16(_ _m256i a, __mmask16 k, __m 256i idx, __m256i b);
VPERMT2W __m256i _mm256_mask2_permutex2var_epi16(__m256i a, __m256i idx, __mmask16 k, __m256i b);VPERMT2W __m256i _mm256_maskz_permutex2var_epi16(__mmask16 k, __m256i a, __m256i idx, __m256i b);VPERMT2W __m128i _mm_permutex2var_epi16(__m128i a, __m128i idx, __m128i b);VPERMT2W __m128i _mm_mask_permutex2var_epi16(__m128i a, __mmask8 k, __m128i idx, __m128i b);VPERMT2W __m128i _mm_mask2_permutex2var_epi16(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMT2W __m128i _mm_maskz_permutex2var_epi16( __mmask8 k, __m128i a, __m128i idx, __m128i b);
None.
VPERMT2D/Q/PS/PD: See Table 2-50, “T ype E4NF Class Exception Conditions.”
VPERMT2W: See Exceptions Type E4NF.nb in Tabl e 2-50, “Type E4NF Class Exception Conditions.”VPEXPANDB/VPEXPANDW—Expand Byte/Word ValuesINSTRUCTION SET REFERENCE, V
5-510 Vol. 2CVPEXPANDB/VPEXPANDW—Expand Byte/Word Values
Expands (loads) up to 64 byte integer values or 32 word integer values from the source operand (memory operand) 
to the destination operand (register operand), based on th e active elements determined by the writemask operand.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Moves 128, 256 or 512 bits of packed byte integer values  from the source operand (memory operand) to the desti-
nation operand (register operand). This in struction is used to load from an int8 vector register or memory location 
while inserting the data into sparse elements of destinat ion vector register using the active elements pointed out 
by the operand writemask.
This instruction supports memory fault suppression.Note that the compressed displacement assumes a pre-scaling  (N) corresponding to the size of one single element 
instead of the size of the full vector.Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F38.W0 62 /r
VPEXPANDB xmm1{k1}{z}, m128AV / VA V X 5 1 2 _ V B M I 2
AVX512VLExpands up to 128 bits of packed byte values 
from m128 to xmm1 with writemask k1.
VPEXPANDB xmm1{k1}{z}, xmm2BV / VA V X 5 1 2 _ V B M I 2
EVEX.256.66.0F38.W0 62 /r
VPEXPANDB ymm1{k1}{z}, m256AV / VA V X 5 1 2 _ V B M I 2
AVX512VLExpands up to 256 bits of packed byte values 
from m256 to ymm1 with writemask k1.
VPEXPANDB ymm1{k1}{z}, ymm2BV / VA V X 5 1 2 _ V B M I 2
EVEX.512.66.0F38.W0 62 /r
VPEXPANDB zmm1{k1}{z}, m512A V/V AVX512_VBMI2 Expands up to 51 2 bits of packed byte values 
from m512 to zmm1 with writemask k1.
VPEXPANDB zmm1{k1}{z}, zmm2B V/V AVX512_VBMI2 Expands up to 51 2 bits of packed byte values 
EVEX.128.66.0F38.W1 62 /r
VPEXPANDW xmm1{k1}{z}, m128AV / VA V X 5 1 2 _ V B M I 2
AVX512VLExpands up to 128 bits of packed word values 
VPEXPANDW xmm1{k1}{z}, xmm2BV / VA V X 5 1 2 _ V B M I 2
EVEX.256.66.0F38.W1 62 /r
VPEXPANDW ymm1{k1}{z}, m256AV / VA V X 5 1 2 _ V B M I 2
AVX512VLExpands up to 256 bits of packed word values 
VPEXPANDW ymm1{k1}{z}, ymm2BV / VA V X 5 1 2 _ V B M I 2
EVEX.512.66.0F38.W1 62 /r
VPEXPANDW zmm1{k1}{z}, m512A V/V AVX512_VBMI2 Expands up to 51 2 bits of packed word values 
VPEXPANDW zmm1{k1}{z}, zmm2B V/V AVX512_VBMI2 Expands up to 512  bits of packed byte integer 
values from zmm2 to zmm1 with writemask 
k1.
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
B N/A ModRM:reg (w) ModRM:r/m (r) N/A N/AVPEXPANDB/VPEXPANDW—Expand Byte/Word ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-511Operation
VPEXPANDB
DEST.byte[j] := SRC.byte[k];k := k + 1ELSE:
*DEST.byte[j] re mains unchanged*
ELSE: ; zeroing-masking
VPEXPANDW
(KL, VL) = (8,128), (16,256), (32, 512)k := 0FOR j := 0 TO KL-1:
DEST.word[j] := SRC.word[k];k := k + 1ELSE:
*DEST.word[j] remains unchanged*ELSE:  ; zeroing-masking
VPEXPAND __m128i _mm_mask_expand_ep i8(__m128i, __mmask16, __m128i);
VPEXPAND __m128i _mm_maskz_expand_epi8(__mmask16, __m128i);VPEXPAND __m128i _mm_mask _expandloadu_epi8(__m128i,  __mmask16, const void*);
VPEXPAND __m128i _mm_maskz_expandlo adu_epi8(__mmask16, const void*);
VPEXPAND __m256i _mm256_mask_expa nd_epi8(__m256i, __mmask32, __m256i);
VPEXPAND __m256i _mm256_maskz_e xpand_epi8(__mmask32, __m256i);
VPEXPAND __m256i _mm256_mask_expandload u_epi8(__m256i, __mmask32, const void*);
VPEXPAND __m256i _mm256_maskz_expan dloadu_epi8(__mmask 32, const void*);

VPEXPANDW
VPEXPAND __m512i _mm512_mask_expa nd_epi8(__m512i, __mmask64, __m512i);
VPEXPAND __m512i _mm512_maskz_e xpand_epi8(__mmask64, __m512i);
VPEXPAND __m512i _mm512_mask_expandload u_epi8(__m512i, __mmask64, const void*);
VPEXPAND __m512i _mm512_maskz_expan dloadu_epi8(__mmask 64, const void*);
VPEXPANDW __m128i _mm_mask_expand_ep i16(__m128i, __mmask8, __m128i);
VPEXPANDW __m128i _mm_maskz_expa nd_epi16(__mmask8, __m128i);
VPEXPANDW __m128i _mm_mask_e xpandloadu_epi16(__m128i, __mmask8, const void*);
VPEXPANDW __m128i _mm_maskz_expandloadu_epi16(__mmask8, const void *);VPEXPANDW __m256i _mm256_mask_expand_epi16(__m256i, __mmask16, __m256i);VPEXPANDW __m256i _mm256_maskz_ex pand_epi16(__mmask16, __m256i);
VPEXPANDW __m256i _mm256_mask _expandloadu_epi16 (__m256i, __mmask16, const void*);
VPEXPANDW __m256i _mm256_maskz_expandloadu_epi16(__mmask16, const void*);VPEXPANDW __m512i _mm512_mask_expand_epi16(__m512i, __mmask32, __m512i);VPEXPANDW __m512i _mm512_maskz_ex pand_epi16(__mmask32, __m512i);
VPEXPANDW __m512i _mm512_mask _expandloadu_epi16 (__m512i, __mmask32, const void*);
VPEXPANDW __m512i _mm512_maskz_expandloadu_epi16(__mmask32, const void*);VPEXPANDB/VPEXPANDW—Expand Byte/Word ValuesINSTRUCTION SET REFERENCE, V
5-512 Vol. 2CSIMD Floating-Point Exceptions
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPEXPANDD—Load Sparse Packed Doubleword Integer Values From Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-513VPEXPANDD—Load Sparse Packed  Doubleword Integer Values From Dense Memory/Register
Expand (load) up to 16 contiguous doubleword integer values  of the input vector in the source operand (the second 
operand) to sparse elements in the destination operand (the first operand), selected by the writemask k1. The 
destination operand is a ZMM register, the source operand can be a ZMM register or memory location.
The input vector starts from the lowest element in the so urce operand. The opmask register k1 selects the desti-
elements in the input vector. Destinat ion elements not selected by the writemask k1 are either unmodified or 
Note that the compressed displacement assumes a pre-scalin g (N) corresponding to the size of one single element 
Operation
VPEXPANDD (EVEX encoded versions) 
THEN 
ELSE 
FI
FI;
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 89 /r
VPEXPANDD xmm1 {k1}{z}, 
AVX512FExpand packed double-word integer values from 
EVEX.256.66.0F38.W0 89 /r
VPEXPANDD ymm1 {k1}{z}, ymm2/m256A V/V AVX512VL
EVEX.512.66.0F38.W0 89 /r
VPEXPANDD zmm1 {k1}{z}, 
zmm2/m512A V/V AVX512F Expand packed double-word integer values from 
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVPEXPANDD—Load Sparse Packed Doubleword Integer Values From Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
5-514 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPEXPANDD __m512i _mm512_mask_expandloadu_ep i32(__m512i s, __mmask16 k, void * a);
VPEXPANDD __m512i _mm512_maskz_expandloadu_epi32( __mmask16 k, void * a);VPEXPANDD __m512i _mm512_mask_expand_epi 32(__m512i s, __mmask16 k, __m512i a);
VPEXPANDD __m512i _mm512_maskz_expan d_epi32( __mmask16 k, __m512i a);
VPEXPANDD __m256i _mm256_mask_expandloadu_ epi32(__m256i s, __mmask8 k, void * a);
VPEXPANDD __m256i _mm256_maskz_expandl oadu_epi32( __mmask8 k, void * a);
VPEXPANDD __m256i _mm256_mask_expand_epi 32(__m256i s, __mmask8 k, __m256i a);
VPEXPANDD __m256i _mm256_maskz_expand_epi32( __mmask8 k, __m256i a);VPEXPANDD __m128i _mm_mask_expandloadu_epi 32(__m128i s, __mmask8 k, void * a);
VPEXPANDD __m128i _mm_maskz_expandloadu_epi32( __mmask8 k, void * a);VPEXPANDD __m128i _mm_mask_expand_epi3 2(__m128i s, __mmask8 k, __m128i a);
VPEXPANDD __m128i _mm_maskz_expand_epi32( __mmask8 k, __m128i a);
None.
Additionally:#UD If EVEX.vvvv != 1111B.VPEXPANDQ—Load Sparse Packed Quadword In teger Values From Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-515VPEXPANDQ—Load Sparse Packed Quadword Integer Values From Dense Memory/Register
Expand (load) up to 8 quadword integer values from the source operand (the second operand) to sparse elements 
in the destination operand (the first operand), selected  by the writemask k1. The destination operand is a ZMM 
register, the source operand can be a ZMM register or memory location.
Operation
VPEXPANDQ (EVEX encoded versions) 
k := 0FOR j := 0 TO KL-1
THEN 
ELSE 
FI
FI;
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W1 89 /r
VPEXPANDQ xmm1 {k 1}{z}, xmm2/m128A V/V AVX512VL
AVX512FExpand packed quad-word integer values from 
EVEX.256.66.0F38.W1 89 /r
VPEXPANDQ ymm1 {k1}{z}, ymm2/m256A V/V AVX512VL
EVEX.512.66.0F38.W1 89 /r
VPEXPANDQ zmm1 {k1}{z}, zmm2/m512A V/V AVX512F Expand packed quad-word integer values from 
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVPEXPANDQ—Load Sparse Packed Quadword In teger Values From Dense Memory/RegisterINSTRUCTION SET REFERENCE, V
5-516 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPEXPANDQ __m512i _mm512_mas k_expandloadu_epi64(__m512i s, __mmask8 k, void * a);
VPEXPANDQ __m512i _mm512_maskz_expandl oadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m512i _mm512_mask_expand_epi 64(__m512i s, __mmask8 k, __m512i a);
VPEXPANDQ __m512i _mm512_maskz_expand_epi64( __mmask8 k, __m512i a);VPEXPANDQ __m256i _mm256_mas k_expandloadu_epi64(__m256i s, __mmask8 k, void * a);
VPEXPANDQ __m256i _mm256_maskz_expandl oadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m256i _mm256_mask_expand_epi 64(__m256i s, __mmask8 k, __m256i a);
VPEXPANDQ __m256i _mm256_maskz_expand_epi64( __mmask8 k, __m256i a);VPEXPANDQ __m128i _mm_mask_expandloadu_e pi64(__m128i s, __mmask8 k, void * a);
VPEXPANDQ __m128i _mm_maskz_expandloadu_epi64( __mmask8 k, void * a);VPEXPANDQ __m128i _mm_mask_expand_epi6 4(__m128i s, __mmask8 k, __m128i a);
VPEXPANDQ __m128i _mm_maskz_expand_epi64( __mmask8 k, __m128i a);
None.
Additionally:#UD If EVEX.vvvv != 1111B.VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-517VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword Indices 
The instruction conditionally loads up to 4 or 8 dword values from memory addresses specified by the memory 
operand (the second operand) and using dword indices. Th e memory operand uses the VS IB form of the SIB byte 
to specify a general purpose register operand as the common base, a vector register for an array of indices relative 
to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the

None.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the 
corresponding element of the destination register is left unchanged. The width of data element in the destination 
Using qword indices, the instruction conditionally loads up to 2 or 4 qword values from the VSIB addressing 
memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits of the destina-
tion register are zero’ed with qword indices.
register and the mask operand are partially updated; those elements that have been gathered are placed into the 
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both of those registers even if the instruction triggers an exce ption, and even if the instru ction triggers the exception 
VEX.128 version: For dword indices, the instruction will gather four dword values. For qword indices, the instruc-
tion will gather two values and zero the upper 64 bits of the destination.
VEX.256 version: For dword indices, the instruction will gather eight dword values. Fo r qword indices, the instruc-
tion will gather four values and zero the upper 128 bits of the destination.
Note that:Opcode/
En64/32
VEX.128.66.0F38.W0 90 /r
VPGATHERDD xmm1, vm32x, xmm2RMV V/V AVX2 Using dword indices specified in vm32x, gather dword val-
ues from memory conditioned on mask specified by xmm2. 
Conditionally gathered elements are merged into xmm1.
VEX.128.66.0F38.W0 91 /r
VPGATHERQD xmm1, vm64x, xmm2RMV V/V AVX2 Using qword indices specified in vm64x, gather dword val-
VEX.256.66.0F38.W0 90 /r
VPGATHERDD ymm1, vm32y, ymm2RMV V/V AVX2 Using dword indices specified in vm32y, gather dword 
from memory conditioned on mask specified by ymm2. Conditionally gathered elements are merged into ymm1.
VEX.256.66.0F38.W0 91 /r
VPGATHERQD xmm1, vm64y, xmm2RMV V/V AVX2 Using qword indices specified in vm64y, gather dword val-
VectorReg(R): VSIB:indexVEX.vvvv (r, w) N/AVPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
5-518 Vol. 2C•If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
•Faults are delivered in a right-to-left manner. That is, if  a fault is triggered by an element and delivered, all 
•This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does 
Operation
BASE_ADDR: base register en coded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;SCALE: scale factor encoded by SIB:[7:6];DISP: optional 1, 4 byte displacement;
MASK := SRC3;
VPGATHERDD (VEX.128 version)
ELSE
FI;
i := j * 32;DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;IF MASK[31+i] THEN
ENDFORDEST[MAXVL-1:128] := 0;VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-519VPGATHERQD (VEX.128 version)
ELSE
FI;
VPGATHERDD (VEX.256 version)
ELSE
FI;
i := j * 32;DATA_ADDR := BASE_ADDR + (SignExten d(VINDEX1[i+31:i])*SCALE + DISP;
ENDFORDEST[MAXVL-1:256] := 0;VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
5-520 Vol. 2CVPGATHERQD (VEX.256 version)
ELSE
FI;
VPGATHERDD: __m128i _mm_i32gather_epi32 (int const * base, __m128i index, const int scale);
VPGATHERDD: __m128i _mm_mask_i32gather_epi32 (__m128i src, in t const * base, __m128i index, __m128i mask, const int scale);
VPGATHERDD: __m256i _mm256_i32gather_epi32 ( int const * base, __m256i index, const int scale);
VPGATHERDD: __m256i _mm256_mask_i32gather_ epi32 (__m256i src, int co nst * base, __m256i index, __m256i mask, const int 
scale);
VPGATHERQD: __m128i _mm_i64gather_epi32 (int const * base, __m128i index, const int scale);
VPGATHERQD: __m128i _mm_mask_i64g ather_epi32 (__m128i src, int const * base, __m 128i index, __m128i mask, const int scale);
VPGATHERQD: __m128i _mm256_i64gather_epi32 (int const * base, __m256i index, const int scale);
VPGATHERQD: __m128i _mm256_mask_i64gather_epi32 (__m128i src,  int const * base, __m256i in dex, __m128i ma sk, const int 
scale);
None.
See Table 2-27, “Type 12 Class Exception Conditions.”VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With Signed Dword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-521VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword Wi th Signed Dword Indices
A set of 16 or 8 doubleword/quadword memory locations pointed to by base  address BASE_ADDR and index vector 
VINDEX with scale SCALE are gathered. The result is wri tten into vector zmm1. The elements are specified via the

scale);
None.
VINDEX with scale SCALE are gathered. The result is wri tten into vector zmm1. The elements are specified via the 
VSIB (i.e., the index register is a zmm, holding packed indi ces). Elements will only be loaded if their corresponding 
mask bit is one. If an element’s mask bit is not set, the corresponding element of the destination register (zmm1) 
is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an exception.
Note that:
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements 
•Not valid with 16-bit effective addresses. Will deliver a #UD fault.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 90 /vsib 
VPGATHERDD xmm1 {k1}, vm32xAV / V A V X 5 1 2 V L
AVX512FUsing signed dword indices, gather dword values from 
memory using writemask k1 for merging-masking.
EVEX.256.66.0F38.W0 90 /vsib 
VPGATHERDD ymm1 {k1}, vm32yAV / V A V X 5 1 2 V L
EVEX.512.66.0F38.W0 90 /vsib 
VPGATHERDD zmm1 {k1}, vm32zA V/V AVX512F Using signed dword indices, gather dword values from 
EVEX.128.66.0F38.W1 90 /vsib 
VPGATHERDQ xmm1 {k1}, vm32xAV / V A V X 5 1 2 V L
AVX512FUsing signed dword indices, gather quadword values from 
EVEX.256.66.0F38.W1 90 /vsib 
VPGATHERDQ ymm1 {k1}, vm32xAV / V A V X 5 1 2 V L
EVEX.512.66.0F38.W1 90 /vsib 
VPGATHERDQ zmm1 {k1}, vm32yA V/V AVX512F Using signed dword indices, gather quadword values from 
VectorReg(R): VSIB:indexN/A N/AVPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With Signed Dword IndicesINSTRUCTION SET REFERENCE, V
5-522 Vol. 2C•These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.
This instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).The instruction will #UD fault if the destination vector zm m1 is the same as index vector VINDEX. The instruction 
ignored.
Operation
VPGATHERDD (EVEX encoded version)
i := j * 32IF k1[j]
THEN DEST[i+31:i] := MEM[BASE_ADDR +
k1[j] := 0
ELSE *DEST[i+31:i] := remains unchanged*  ; Only merging masking is allowed
FI;
VPGATHERDQ (EVEX encoded version)
i := j * 64k := j * 32IF k1[j]
MEM[BASE_ADDR + SignExtend(VIN DEX[k+31:k]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+63:i] := remains unchanged*  ; Only merging masking is allowed
FI;
ENDFORk1[MAX_KL-1:KL] := 0DEST[MAXVL-1:VL] := 0VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With Signed Dword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-523Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDD __m512i _mm512_i32gather_epi32( __m512i vdx, void * base, int scale);
VPGATHERDD __m512i _mm512_mask_i32gather_epi32(__m512i s,  __mmask16 k, __m512i vdx, void * base, int scale);
VPGATHERDD __m256i _mm256_mmask_i32ga ther_epi32(__m256i s, __mmask8 k, __m 256i vdx, void * base, int scale);
VPGATHERDD __m128i _mm_mmask_i32gather_epi32(__m128i s,  __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERDQ __m512i _mm512_i32logather_epi64 ( __m256i vdx, void * base, int scale);
VPGATHERDQ __m512i _mm512_mask_i32logather_epi64(__m512i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERDQ __m256i _mm256_mmask_i32loga ther_epi64(__m256i s, __mma sk8 k, __m128i vdx, void * base, int scale);
VPGATHERDQ __m128i _mm_mmask_i32gather_epi64(__m128i s,  __mmask8 k, __m128i vdx, void * base, int scale);
None.
See Table 2-61, “Type E12 Class Exception Conditions.”VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
5-524 Vol. 2CVPGATHERDQ/VPGATHERQQ—Gather Packed Qword Va lues Using Signed Dword/Qword Indices 
The instruction conditionally loads up to 2 or 4 qword values from memory addresses specified by the memory 
operand (the second operand) and using qword indices. Th e memory operand uses the VSIB form of the SIB byte 
Using dword indices in the lower half of  the mask register, the instruction conditionally loads up to 2 or 4 qword 
values from the VSIB addressing memory op erand, and updates the destination register. 
If the data size and index size are diff erent, part of the destination register and part of the mask register do not

VEX.128 version: The instruction will gather two qword valu es. For dword indices, only the lower two indices in the 
vector index register are used.Opcode/
En64/32
VEX.128.66.0F38.W1 90 /r
VPGATHERDQ xmm1, vm32x, xmm2A V/V AVX2 Using dword indices specified in vm32x, gather qword val-
ues from memory conditioned on mask specified by 
xmm2. Conditionally gathered elements are merged into xmm1.
VEX.128.66.0F38.W1 91 /r
VPGATHERQQ xmm1, vm64x, xmm2A V/V AVX2 Using qword indices specified in vm64x, gather qword val-
VEX.256.66.0F38.W1 90 /r
VPGATHERDQ ymm1, vm32x, ymm2A V/V AVX2 Using dword indices specified in vm32x, gather qword val-
ymm2. Conditionally gathered elements are merged into ymm1.
VEX.256.66.0F38.W1 91 /r
VPGATHERQQ ymm1, vm64y, ymm2A V/V AVX2 Using qword indices specified in vm64y, gather qword val-
ues from memory conditioned on mask specified by ymm2. Conditionally gathered elements are merged into 
ymm1.
VectorReg(R): VSIB:indexVEX.vvvv (r, w) N/AVPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-525VEX.256 version: The instruction will gather four qword valu es. For dword indices, only the lower four indices in the 
vector index register are used.
Note that:
Operation
VPGATHERDQ (VEX.128 version)
ELSE
FI;
k := j * 32;i := j * 64;DATA_ADDR := BASE_ADDR + (SignExt end(VINDEX[k+31:k])*SCALE + DISP);
ENDFORDEST[MAXVL-1:128] := 0;VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
5-526 Vol. 2CVPGATHERQQ (VEX.128 version)
ELSE
FI;
i := j * 64;DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP);IF MASK[63+i] THEN
VPGATHERQQ (VEX.256 version)
ELSE
FI;
VPGATHERDQ (VEX.256 version)
ELSE
FI;
k := j * 32;i := j * 64;DATA_ADDR := BASE_ADDR + (SignExten d(VINDEX1[k+31:k])*SCALE + DISP);VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-527IF MASK[63+i] THEN
VPGATHERDQ: __m128i _mm_i32gathe r_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERDQ: __m128i _mm_mask_i32gather_ep i64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int 
scale);
VPGATHERDQ: __m256i _mm256_i32gather_epi64 (__int64  const * base, __m128i in dex, const int scale);
VPGATHERDQ: __m256i _mm256_mask_i32gather_epi64 (__m256i sr c, __int64 const * base, __m128i index, __m256i mask, const 
int scale);
VPGATHERQQ: __m128i _mm_i64gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERQQ: __m128i _mm_mask_i64gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int 
scale);
VPGATHERQQ: __m256i _mm256_i64gather_epi64 __(int64 const * base, __m256i index, const int scale);
VPGATHERQQ: __m256i _mm256_mask_i64gather_epi64 (__m256i src, __int64 const * base, __m256i index, __m256i mask, const 
None.
See Table 2-27, “Type 12 Class Exception Conditions.”VPGATHERQD/VPGATHERQQ—Gather Packed Dword,  Packed Qword with Signed Qword IndicesINSTRUCTION SET REFERENCE, V
5-528 Vol. 2CVPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
A set of 8 doubleword/quadword memory locations poin ted to by base address BASE_ADDR and index vector 
VINDEX with scale SCALE are gathered. Th e result is written into a vector register. The elements are specified via 
the VSIB (i.e., the index register is a vector register, hold ing packed indices). Elements will only be loaded if their 
corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of the destination 
register is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an excep-
tion.
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may update these unused elements to one or both of those regi sters even if the instruction triggers an exception, and 
Note that:

Note that:
•Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all elements closer to the LSB of the destination zmm will be completed (and non-faulti ng). Individual elements 
left of the faulting one will be gathered.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 91 /vsib 
VPGATHERQD xmm1 {k1}, vm64xA V/V AVX512VL
AVX512FUsing signed qword indices, gather dword values from 
EVEX.256.66.0F38.W0 91 /vsib 
VPGATHERQD xmm1 {k1}, vm64yA V/V AVX512VL
EVEX.512.66.0F38.W0 91 /vsib 
VPGATHERQD ymm1 {k1}, vm64zA V/V AVX512F Using signed qword indices, gather dword values from 
EVEX.128.66.0F38.W1 91 /vsib 
VPGATHERQQ xmm1 {k1}, vm64xA V/V AVX512VL
AVX512FUsing signed qword indices, gather quadword values from 
EVEX.256.66.0F38.W1 91 /vsib 
VPGATHERQQ ymm1 {k1}, vm64yA V/V AVX512VL
EVEX.512.66.0F38.W1 91 /vsib 
VPGATHERQQ zmm1 {k1}, vm64zA V/V AVX512F Using signed qword indices, gather quadword values from 
VectorReg(R): VSIB:indexN/A N/AVPGATHERQD/VPGATHERQQ—Gather Packed Dword,  Packed Qword with Signed Qword IndicesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-529•This instruction does not perform AC chec ks, and so will never deliver an AC fault.
•These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.
ignored.
Operation
VINDEX stands for the memory operand vector of indices (a ZMM register)
VPGATHERQD (EVEX encoded version)
i := j * 32k := j * 64IF k1[j]
THEN DEST[i+31:i] := MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]
k1[j] := 0
FI;
VPGATHERQQ (EVEX encoded version)
(KL, VL) = (2, 64), (4, 128), (8, 256)FOR j := 0 TO KL-1
i := j * 64IF k1[j]
MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]k1[j] := 0
FI;
ENDFORk1[MAX_KL-1:KL] := 0DEST[MAXVL-1:VL] := 0VPGATHERQD/VPGATHERQQ—Gather Packed Dword,  Packed Qword with Signed Qword IndicesINSTRUCTION SET REFERENCE, V
5-530 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPGATHERQD __m256i _mm512_i64 gather_epi32(__m512i vdx, void * base, int scale);
VPGATHERQD __m256i _mm512_mask_i64gather_epi32lo(__m256i s, __mmask8 k, __m512i vdx, void * base, int scale);
VPGATHERQD __m128i _mm256_mask_i64gather_epi32lo(__m128i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERQD __m128i _mm_mask_i64gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERQQ __m512i _mm512_i64gather_epi64( __m512i vdx, void * base, int scale);
VPGATHERQQ __m512i _mm512_mask_i64gather_epi64(__m512i s, __mmask8 k, __m512i vdx, void * base, int scale);
VPGATHERQQ __m256i _mm256_mask_i64gather_epi64(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERQQ __m128i _mm_mask_i64gather_epi64(__m128i s,  __mmask8 k, __m128i vdx, void * base, int scale);
None.
See Table 2-61, “Type E12 Class Exception Conditions.”VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-531VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
Counts the number of leading most significant zero bits in  each dword or qword element of the source operand (the 
second operand) and stores the results in the destination register (the first operand) according to the writemask. 
If an element is zero, the result for that element is the operand size of the element.  
EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector 
EVEX.256 encoded version: The source operand is a YMM re gister, a 256-bit memory location, or a 256-bit vector 
broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated 
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector 
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 44 /r
VPLZCNTD xmm1 {k1}{z}, 
AVX512CDCount the number of  leading zero bits in each dword 
element of xmm2/m128/m32bcst using writemask k1.
EVEX.256.66.0F38.W0 44 /r
VPLZCNTD ymm1 {k1}{z}, ymm2/m256/m32bcstA V/V AVX512VL
element of ymm2/m256/m32bcst using writemask k1.
EVEX.512.66.0F38.W0 44 /r
VPLZCNTD zmm1 {k1}{z}, 
zmm2/m512/m32bcstA V/V AVX512CD Count the number of leading zero bits in each dword 
element of zmm2/m512/m32bcst using writemask k1.
EVEX.128.66.0F38.W1 44 /r
VPLZCNTQ xmm1 {k1}{z}, 
AVX512CDCount the number of  leading zero bits in each qword 
element of xmm2/m128/m64bcst using writemask k1.
EVEX.256.66.0F38.W1 44 /r
VPLZCNTQ ymm1 {k1}{z}, 
element of ymm2/m256/m64bcst using writemask k1.
EVEX.512.66.0F38.W1 44 /r
VPLZCNTQ zmm1 {k1}{z}, zmm2/m512/m64bcstA V/V AVX512CD Count the number of leading zero bits in each qword 
element of zmm2/m512/m64bcst using writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword ValuesINSTRUCTION SET REFERENCE, V
5-532 Vol. 2COperation
VPLZCNTD
i := j*32IF MaskBit(j) OR *no writemask*
THEN 
   temp := 32   DEST[i+31:i] := 0   WHILE (temp > 0) AND (SRC[i+temp-1] = 0)
   DO
temp := temp – 1DEST[i+31:i] := DEST[i+31:i] + 1
   ODELSE   IF *merging-masking* 
THEN *DEST[i+31:i] remains unchanged*ELSE DEST[i+31:i] := 0
   FI
FI
VPLZCNTQ
i := j*64IF MaskBit(j) OR *no writemask*
THEN
   temp := 64   DEST[i+63:i] := 0   WHILE (temp > 0) AND (SRC[i+temp-1] = 0)
  DO
temp := temp – 1DEST[i+63:i] := DEST[i+63:i] + 1
THEN *DEST[i+63:i] remains unchanged*ELSE DEST[i+63:i] := 0
   FI
FI
ENDFORDEST[MAXVL-1:VL] := 0VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-533Intel C/C++ Compiler Intrinsic Equivalent
VPLZCNTD __m512i _mm512_lzcnt_epi32(__m512i a);

VPLZCNTD
THEN 
   DO
   FI
FI
VPLZCNTQ
THEN
  DO
   FI
FI
VPLZCNTD __m512i _mm512_mask_lzcnt_epi32(__m512i s, __mmask16 m, __m512i a);VPLZCNTD __m512i _mm512_maskz_lzcnt_epi32( __mmask16 m, __m512i a);
VPLZCNTQ __m512i _mm512_lzc nt_epi64(__m512i a);
VPLZCNTQ __m512i _mm512_mask_lzcnt_epi64( __m512i s, __mmask8 m, __m512i a);
VPLZCNTQ __m512i _mm512_maskz_lzc nt_epi64(__mmask8 m, __m512i a);
VPLZCNTD __m256i _mm256_lzcnt_epi32(__m256i a);VPLZCNTD __m256i _mm256_mask_lzcnt_epi32(__m256i s, __mmask8 m, __m256i a);VPLZCNTD __m256i _mm256_maskz_lzcnt _epi32( __mmask8 m, __m256i a);
VPLZCNTQ __m256i _mm256_lzc nt_epi64(__m256i a);
VPLZCNTQ __m256i _mm256_mask_lzcnt_epi64( __m256i s, __mmask8 m, __m256i a);
VPLZCNTQ __m256i _mm256_maskz_lzc nt_epi64(__mmask8 m, __m256i a);
VPLZCNTD __m128i _mm_lzcnt_epi32(__m128i a);VPLZCNTD __m128i _mm_mask_lzcnt_epi32( __m128i s, __mmask8 m, __m128i a);
VPLZCNTD __m128i _mm_maskz_lzcnt_ epi32( __mmask8 m, __m128i a);
VPLZCNTQ __m128i _mm_lzcnt_epi64(__m128i a);VPLZCNTQ __m128i _mm_mask_lzcnt_epi64(__ m128i s, __mmask8 m, __m128i a);
VPLZCNTQ __m128i _mm_maskz_lzcnt_ epi64(__mmask8 m, __m128i a);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”VPMADD52HUQ—Packed Multiply of Unsigned 52-Bit Unsigned In tegers and Add High 52-Bit Products to 64-Bit AccumulatorsINSTRUCTION SET REFERENCE, V
5-534 Vol. 2CVPMADD52HUQ—Packed Multiply of Unsigned 52-Bi t Unsigned Integers and Add High 52-Bit 
Products to 64-Bit Accumulators
Multiplies packed unsigned 52-bit integers in each qwor d element of the first source operand (the second oper-
and) with the packed unsigned 52-bit integers in the co rresponding elements of the second source operand (the 
third operand) to form packed 104-bit intermediate re sults. The high 52-bit, unsigned integer of each 104-bit 
product is added to the corresponding qword unsigned in teger of the destination operand (the first operand) 
under the writemask k1.
ister, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory loca-
tion. The destination operand is a ZMM/YMM/XMM register  conditionally updated with writemask k1 at 64-bit 
granularity.Opcode/
En64/32 
Bit Mode 
SupportCPUID Description
EVEX.128.66.0F38.W1 B5 /r
VPMADD52HUQ xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcstAV / V  A V X 5 1 2 _ I F M A
AVX512VLMultiply unsigned 52-bit integers in xmm2 and 
xmm3/m128 and add the high 52 bits of the 104-
bit product to the qword unsigned integers in 
EVEX.256.66.0F38.W1 B5 /r
VPMADD52HUQ ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcstAV / V  A V X 5 1 2 _ I F M A
AVX512VLMultiply unsigned 52-bit integers in ymm2 and 
ymm3/m256 and add the high 52 bits of the 104-
EVEX.512.66.0F38.W1 B5 /r
VPMADD52HUQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstA V/V AVX512_IFMA Multiply unsigned 52-bit integers in zmm2 and 
zmm3/m512 and add the high 52 bits of the 104-
A Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m(r) N/AVPMADD52HUQ—Packed Multiply of Unsigned 52-Bit Unsigned In tegers and Add High 52-Bit Products to 64-Bit AccumulatorsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-535Operation
VPMADD52HUQ (EVEX encoded)
i := j * 64;IF k1[j] OR *no writemask* THEN
IF src2 is Memory  AND EVEX.b=1 THEN
tsrc2[63:0] := ZeroExtend64(src2[51:0]);
ELSE
tsrc2[63:0] := ZeroExtend64(src2[i+51:i];
FI;Temp128[127:0] := ZeroExtend64(src1[i+51:i]) * tsrc2[63:0];Temp2[63:0] := DEST[i+63:i] + ZeroExtend64(temp128[103:52]) ;DEST[i+63:i] := Temp2[63:0];
ELSE 
IF *zeroing-masking* THEN
DEST[i+63:i] := 0;
ELSE *merge-masking*
DEST[i+63:i] is unchanged;
FI;
FI;
ENDFORDEST[MAX_VL-1:VL] := 0
VPMADD52HUQ __m512i _mm512_madd52hi_epu64( __m512i a, __m512i b, __m512i c);VPMADD52HUQ __m512i _mm512_mask_madd52hi_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b, __m512i c);VPMADD52HUQ __m512i _mm512_maskz_madd52hi_epu64( __mmask8 k, __m512i a, __m512i b, __m512i c);VPMADD52HUQ __m256i _mm256_madd52hi_epu64( __m256i a, __m256i b, __m256i c);VPMADD52HUQ __m256i _mm256_mask_madd52hi_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b, __m256i c);VPMADD52HUQ __m256i _mm256_maskz_madd52hi_epu64( __mmask8 k, __m256i a, __m256i b, __m256i c);VPMADD52HUQ __m128i _mm_madd52hi_epu64( __m128i a, __m128i b, __m128i c);VPMADD52HUQ __m128i _mm_mask_madd52hi_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b, __m128i c);
VPMADD52HUQ __m128i _mm_maskz_madd52hi_epu64( __mmask8 k, __m128i a, __m128i b, __m128i c);
None.
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPMADD52LUQ—Packed Multiply of Unsigned 52-Bit Integers  and Add the Low 52-Bit Products to Qword AccumulatorsINSTRUCTION SET REFERENCE, V
5-536 Vol. 2CVPMADD52LUQ—Packed Multiply of Unsigned 52-Bi t Integers and Add the Low 52-Bit Products 
to Qword Accumulators
third operand) to form packed 104-bit intermediate resu lts. The low 52-bit, unsigned integer of each 104-bit 
En64/32 
Bit Mode 
EVEX.128.66.0F38.W1 B4 /r
VPMADD52LUQ xmm1 {k1}{z}, 
xmm2,xmm3/m128/m64bcstA V/V AVX512_IFMA
xmm3/m128 and add the low 52 bits of the 104-bit 
product to the qword unsigned integers in xmm1 using 
EVEX.256.66.0F38.W1 B4 /r
VPMADD52LUQ ymm1 {k1}{z}, 
ymm2, ymm3/m256/m64bcstA V/V AVX512_IFMA
ymm3/m256 and add the low 52 bits of the 104-bit 
product to the qword unsigned integers in ymm1 using 
EVEX.512.66.0F38.W1 B4 /r
VPMADD52LUQ zmm1 {k1}{z}, 
zmm2,zmm3/m512/m64bcstA V/V AVX512_IFMA Multiply unsigned 52-bit integers in zmm2 and 
zmm3/m512 and add the low 52 bits of the 104-bit 
product to the qword unsigned  integers in zmm1 using 
A Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m(r) N/AVPMADD52LUQ—Packed Multiply of Unsigned 52-Bit Integers  and Add the Low 52-Bit Products to Qword AccumulatorsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-537Operation
VPMADD52LUQ (EVEX encoded)
ELSE
FI;Temp128[127:0] := ZeroExtend64(src1[i+51:i]) * tsrc2[63:0];Temp2[63:0] := DEST[i+63:i] + ZeroExtend64(temp128[51:0]) ;DEST[i+63:i] := Temp2[63:0];
ELSE 
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL]
 := 0;
VPMADD52LUQ __m512i _mm512_madd52lo_epu64( __m512i a, __m512i b, __m512i c);VPMADD52LUQ __m512i _mm512_mask_madd52lo_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b, __m512i c);VPMADD52LUQ __m512i _mm512_maskz_madd52lo_epu64(  __mmask8 k, __m512i a, __m512i b, __m512i c);
VPMADD52LUQ __m256i _mm256_madd52lo_epu64( __m256i a, __m256i b, __m256i c);VPMADD52LUQ __m256i _mm256_mask_madd52lo_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b, __m256i c);VPMADD52LUQ __m256i _mm256_maskz_madd52lo_epu64(  __mmask8 k, __m256i a, __m256i b, __m256i c);
VPMADD52LUQ __m128i _mm_madd52lo_epu64( __m128i a, __m128i b, __m128i c);VPMADD52LUQ __m128i _mm_mask_madd52lo_epu64(__m128i s,  __mmask8 k, __m128i a, __m128i b, __m128i c);
VPMADD52LUQ __m128i _mm_maskz_madd52lo_epu64( __ mmask8 k, __m128i a, __m128i b, __m128i c);
None.
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPMASKMOV—Conditional SIMD In teger Packed Loads and StoresINSTRUCTION SET REFERENCE, V
5-538 Vol. 2CVPMASKMOV—Conditional SIMD Integer Packed Loads and Stores

None.
None.
Conditionally moves packed data elements from the second  source operand into the corresponding data element of 
the destination operand, depending on the mask bits associ ated with each data elemen t. The mask bits are speci-
fied in the first source operand. 
The second source operand is a memory address for the load  form of these instructions. The destination operand is 
a memory address for the store form of these instructio ns. The other operands are either XMM registers (for 
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to 
referencing any memory location if the corresponding mask  bit for that memory location is 0. For example, no 
of all 1s.Opcode/
En64/32
VEX.128.66.0F38.W0 8C /r
VPMASKMOVD xmm1, xmm2, m128RVM V/V AVX2 Conditionally load dword values from m128 using mask 
in xmm2 and store in xmm1.
VEX.256.66.0F38.W0 8C /r
VPMASKMOVD ymm1, ymm2, m256RVM V/V AVX2 Conditionally load dword values from m256 using mask 
in ymm2 and store in ymm1.
VEX.128.66.0F38.W1 8C /r
VPMASKMOVQ xmm1, xmm2, m128RVM V/V AVX2 Conditionally load qword values from m128 using mask 
VEX.256.66.0F38.W1 8C /r
VPMASKMOVQ ymm1, ymm2, m256RVM V/V AVX2 Conditionally load qword values from m256 using mask 
VEX.128.66.0F38.W0 8E /r
VPMASKMOVD m128, xmm1, xmm2MVR V/V AVX2 Conditionally store dword values from xmm2 using 
mask in xmm1.
VEX.256.66.0F38.W0 8E /r
VPMASKMOVD m256, ymm1, ymm2MVR V/V AVX2 Conditionally store dword values from ymm2 using 
mask in ymm1.
VEX.128.66.0F38.W1 8E /r
VPMASKMOVQ m128, xmm1, xmm2MVR V/V AVX2 Conditionally store qword values from xmm2 using 
VEX.256.66.0F38.W1 8E /r
VPMASKMOVQ m256, ymm1, ymm2MVR V/V AVX2 Conditionally store qword values from ymm2 using 
RVM ModRM:reg (w) VEX.vvv v (r) ModRM:r/m (r) N/A
MVR ModRM:r/m (w) VEX.vvvv (r) ModRM:reg (r) N/AVPMASKMOV—Conditional SIMD Integer Packed Loads and StoresINSTRUCTION SET REFERENCE, V
Vol. 2C 5-539VMASKMOV should not be used to access memory mapped I/O as the ordering of the individual loads or stores it 
does is implementation specific. 
In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-
reg_field, and the destination memory  location is encoded in rm_field.
Operation
VPMASKMOVD - 256-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0 DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0 DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0 DEST[127:96] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0 
DEST[159:128] := IF (SRC1[159]) Load_32(mem + 16) ELSE 0 
DEST[191:160] := IF (SRC1[191]) Load_32(mem + 20) ELSE 0 DEST[223:192] := IF (SRC1[223]) Load_32(mem + 24) ELSE 0 DEST[255:224] := IF (SRC1[255]) Load_32(mem + 28) ELSE 0 
VPMASKMOVD -128-bit load 
VPMASKMOVQ - 256-bit load
VPMASKMOVQ - 128-bit load 
VPMASKMOVD - 256-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0] IF (SRC1[63]) DEST[63:32] := SRC2[63:32] IF (SRC1[95]) DEST[95:64] := SRC2[95:64] IF (SRC1[127]) DEST[127:96] := SRC2[127:96] IF (SRC1[159]) DEST[159:128] :=SRC2[159:128] IF (SRC1[191]) DEST[191:160] := SRC2[191:160] IF (SRC1[223]) DEST[223:192] := SRC2[223:192] IF (SRC1[255]) DEST[255:224] := SRC2[255:224] VPMASKMOV—Conditional SIMD In teger Packed Loads and StoresINSTRUCTION SET REFERENCE, V
5-540 Vol. 2CVPMASKMOVD - 128-bit store
VPMASKMOVQ - 256-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0] IF (SRC1[127]) DEST[127:64] :=SRC2[127:64] IF (SRC1[191]) DEST[191:128] := SRC2[191:128] IF (SRC1[255]) DEST[255:192] := SRC2[255:192] 
VPMASKMOVQ - 128-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0] IF (SRC1[127]) DEST[127:64] :=SRC2[127:64] 
VPMASKMOVD: __m256i _mm256_maskload_ epi32(int const *a, __m256i mask)
VPMASKMOVD: void    _mm256_maskstore _epi32(int *a, __m256i mask, __m256i b)
VPMASKMOVQ: __m256i _mm256_maskload_epi64(__int64 const *a, __m256i mask);
VPMASKMOVQ: void    _mm256_maskstore_epi64(__int64 *a, __m256i mask, __m256d b);
VPMASKMOVD: __m128i _mm_maskload_epi 32(int const *a, __m128i mask)
VPMASKMOVD: void    _mm_maskstore_ epi32(int *a, __m128i mask, __m128 b)
VPMASKMOVQ: __m128i _mm_maskload_epi64(__int cont *a, __m128i mask);
VPMASKMOVQ: void    _mm_maskstore_epi6 4(__int64 *a, __m128i mask, __m128i b);
None.
See Table 2-23, “Type 6 Class Exception Conditions” (No AC# reported for any mask bit combinations).VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-541VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Conv ert a Vector Register to a Mask 
Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on 
the value of most significant bit of the corresponding element in the source register.
The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register.
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W0 29 /r 
VPMOVB2M k1, xmm1RM V/V AVX512VL
AVX512BWSets each bit in k1 to 1 or 0 based on the value of the most 
significant bit of the corresponding byte in XMM1. 
EVEX.256.F3.0F38.W0 29 /r 
VPMOVB2M k1, ymm1RM V/V AVX512VL
significant bit of the corresponding byte in YMM1. 
EVEX.512.F3.0F38.W0 29 /r 
VPMOVB2M k1, zmm1 RM V/V AVX512BW Sets each bit in k1 to 1 or 0 based on the value of the most 
significant bit of the corresponding byte in ZMM1. 
EVEX.128.F3.0F38.W1 29 /r 
VPMOVW2M k1, xmm1 RM V/V AVX512VL
significant bit of the corresponding word in XMM1. 
EVEX.256.F3.0F38.W1 29 /r 
VPMOVW2M k1, ymm1RM V/V AVX512VL
significant bit of the corresponding word in YMM1. 
EVEX.512.F3.0F38.W1 29 /r 
VPMOVW2M k1, zmm1RM V/V AVX512BW Sets each bit in k1 to 1 or 0 based on the value of the most 
significant bit of the corresponding word in ZMM1. 
EVEX.128.F3.0F38.W0 39 /r 
VPMOVD2M k1, xmm1 RM V/V AVX512VL
AVX512DQSets each bit in k1 to 1 or 0 based on the value of the most 
significant bit of the corresponding doubleword in XMM1. 
EVEX.256.F3.0F38.W0 39 /r 
VPMOVD2M k1, ymm1 RM V/V AVX512VL
significant bit of the corresponding doubleword in YMM1. 
EVEX.512.F3.0F38.W0 39 /r 
VPMOVD2M k1, zmm1RM V/V AVX512DQ Sets each bit in k1 to 1 or 0 based on the value of the most 
significant bit of the corresponding doubleword in ZMM1. 
EVEX.128.F3.0F38.W1 39 /r 
VPMOVQ2M k1, xmm1 RM V/V AVX512VL
significant bit of the corresponding quadword in XMM1. 
EVEX.256.F3.0F38.W1 39 /r 
VPMOVQ2M k1, ymm1 RM V/V AVX512VL
AVX512DQSets each bit in k1 to 1 or 0 based on the value of the most

significant bit of the corresponding quadword in YMM1. 
EVEX.512.F3.0F38.W1 39 /r 
VPMOVQ2M k1, zmm1 RM V/V AVX512DQ Sets each bit in k1 to 1 or 0 based on the value of the most 
significant bit of the corresponding quadword in ZMM1. 
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AVPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a MaskINSTRUCTION SET REFERENCE, V
5-542 Vol. 2COperation
VPMOVB2M (EVEX encoded versions) 
i := j * 8IF SRC[i+7]
THEN DEST[j] := 1 ELSE DEST[j] := 0
FI;
VPMOVW2M (EVEX encoded versions) 
i := j * 16IF SRC[i+15]
FI;
VPMOVD2M (EVEX encoded versions) 
i := j * 32IF SRC[i+31]
FI;
VPMOVQ2M (EVEX encoded versions) 
i := j * 64IF SRC[i+63]
FI;
ENDFORDEST[MAX_KL-1:KL] := 0VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-543Intel C/C++ Compiler Intrinsic Equivalents
VPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );
VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );VPMPOVQ2M __mmask8 _mm512_m ovepi64_mask( __m512i );
VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );VPMPOVQ2M __mmask8 _mm256_m ovepi64_mask( __m256i );
VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );
None.
EVEX-encoded instruction, see Table 2-55, “Type E7NM Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B.VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to ByteINSTRUCTION SET REFERENCE, V
5-544 Vol. 2CVPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
VPMOVDB down converts 32-bit integer elements in the so urce operand (the second operand) into packed bytes 
using truncation. VPMOVSDB converts signed 32-bit intege rs into packed signed bytes using signed saturation. 
VPMOVUSDB convert unsigned double-word values into unsigned byte values using unsigned saturation. 
The source operand is a ZMM/YMM/XMM register. The dest ination operand is a XMM register or a 128/64/32-bit 
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant 
byte. Byte elements of the destination operand are updated according to the writemask. Bits ( MAXVL-1 :128/64/32) 
of the register destination are zeroed.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W0 31 /r
VPMOVDB xmm1/m32 {k1}{z}, xmm2A V/V AVX512VL
AVX512FConverts 4 packed double-word integers from xmm2 
into 4 packed byte inte gers in xmm1/m32 with 
truncation unde r writemask k1.
EVEX.128.F3.0F38.W0 21 /r
VPMOVSDB xmm1/m32 {k1}{z}, xmm2A V/V AVX512VL
AVX512FConverts 4 packed signed double-word integers from 
xmm2 into 4 packed signed byte integers in xmm1/m32 using signed saturation under writemask 
k1.
EVEX.128.F3.0F38.W0 11 /r
VPMOVUSDB xmm1/m32 {k1}{z}, xmm2A V/V AVX512VL
AVX512FConverts 4 packed unsigned double-word integers 
from xmm2 into 4 packed unsigned byte integers in 
xmm1/m32 using unsigned saturation under 
EVEX.256.F3.0F38.W0 31 /r
VPMOVDB xmm1/m64 {k1}{z}, ymm2A V/V AVX512VL
AVX512FConverts 8 packed double-word integers from ymm2 
into 8 packed byte inte gers in xmm1/m64 with 
EVEX.256.F3.0F38.W0 21 /r
VPMOVSDB xmm1/m64 {k1}{z}, ymm2A V/V AVX512VL
AVX512FConverts 8 packed signed double-word integers from 
ymm2 into 8 packed sign ed byte integers in 
xmm1/m64 using signed saturation under writemask 
k1.
EVEX.256.F3.0F38.W0 11 /r
VPMOVUSDB xmm1/m64 {k1}{z}, ymm2A V/V AVX512VL
AVX512FConverts 8 packed unsigned double-word integers 
from ymm2 into 8 packed unsigned byte integers in xmm1/m64 using unsigned saturation under 
EVEX.512.F3.0F38.W0 31 /r
VPMOVDB xmm1/m128 {k1}{z}, zmm2A V/V AVX512F Converts 16 packed double-word integers from zmm2 
into 16 packed byte inte gers in xmm1/m128 with 
EVEX.512.F3.0F38.W0 21 /r
VPMOVSDB xmm1/m128 {k1}{z}, zmm2A V/V AVX512F Converts 16 packed signed double-word integers 
from zmm2 into 16 packed signed byte integers in 
xmm1/m128 using signed saturation under writemask k1.
EVEX.512.F3.0F38.W0 11 /r
VPMOVUSDB xmm1/m128 {k1}{z}, 
zmm2A V/V AVX512F Converts 16 packed unsigned double-word integers 
from zmm2 into 16 packed un signed byte integers in 
xmm1/m128 using unsigned saturation under writemask k1.
A Quarter Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AVPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to ByteINSTRUCTION SET REFERENCE, V
Vol. 2C 5-545EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVDB instruction (EVEX encoded versions) when dest is a register
i := j * 8m := j * 32IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateDo ubleWordToByte (SRC[m+31:m])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/4] := 0;
VPMOVDB instruction (EVEX encoded versions) when dest is memory
FI;
ENDFOR
VPMOVSDB instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+7:i] := SaturateSign edDoubleWordToByte  (SRC[m+31:m])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/4] := 0;VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to ByteINSTRUCTION SET REFERENCE, V
5-546 Vol. 2CVPMOVSDB instruction (EVEX encoded versions) when dest is memory
FI;
ENDFOR
VPMOVUSDB instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+7:i] := SaturateUnsign edDoubleWordToByte  (SRC[m+31:m])
ELSE 
FI
FI;
VPMOVUSDB instruction (EVEX encoded versions) when dest is memory
FI;
ENDFORVPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to ByteINSTRUCTION SET REFERENCE, V
Vol. 2C 5-547Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDB __m128i _mm512_cvtepi32_epi8( __m512i a);
VPMOVDB __m128i _mm512_mask_cvtepi32_epi 8(__m128i s, __mmask16 k, __m512i a);
VPMOVDB __m128i _mm512_maskz_cvtepi32_epi8( __mmask16 k, __m512i a);VPMOVDB void _mm512_mask_cvtepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);VPMOVSDB __m128i _mm512_cvtsepi32_epi8( __m512i a);VPMOVSDB __m128i _mm512_mask_cvtsepi32_epi8(__m128i s, __mmask16 k, __m512i a);VPMOVSDB __m128i _mm512_maskz_cvtsepi 32_epi8( __mmask16 k, __m512i a);
VPMOVSDB void _mm512_mask_cvtsepi32_storeu _epi8(void * d, __mma sk16 k, __m512i a);
VPMOVUSDB __m128i _mm512_cvtusepi32_epi8( __m512i a);VPMOVUSDB __m128i _mm512_mask_cvtusepi32 _epi8(__m128i s, __mma sk16 k, __m512i a);
VPMOVUSDB __m128i _mm512_maskz_cvtusepi32_epi8( __mmask16 k, __m512i a);VPMOVUSDB void _mm512_mask_cvtusepi32_store u_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm256_cvtusepi32_epi8(__m256i a);VPMOVUSDB __m128i _mm256_mask_cvtusepi32_e pi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm256_maskz_cvtusepi32_epi8( __mmask8 k, __m256i b);VPMOVUSDB void _mm256_mask_cvtusepi32_sto reu_epi8(void * , __mmask8 k, __m256i b);

VPMOVUSDB __m128i _mm_cvtusepi32_epi8(__m128i a);VPMOVUSDB __m128i _mm_mask_cvtusepi32_ep i8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDB __m128i _mm_maskz_cvtusepi32_epi8( __mmask8 k, __m128i b);VPMOVUSDB void _mm_mask_cvtusepi32_storeu _epi8(void * , __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm256_cvtsepi32_epi8(__m256i a);VPMOVSDB __m128i _mm256_mask_cvtsepi32_ep i8(__m128i a, __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm256_maskz_cvtse pi32_epi8( __mmask8 k, __m256i b);
VPMOVSDB void _mm256_mask_cvtsepi32_storeu _epi8(void * , __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm_cvtsepi32_epi8(__m128i a);VPMOVSDB __m128i _mm_mask_cvtsepi32_epi 8(__m128i a, __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm_maskz_cvtsepi32_epi8( __mmask8 k, __m128i b);VPMOVSDB void _mm_mask_cvtsepi32_store u_epi8(void * , __mmask8 k, __m128i b);
VPMOVDB __m128i _mm256_cvtepi32_epi8(__m256i a);VPMOVDB __m128i _mm256_mask_cvtepi32_epi 8(__m128i a, __mmask8 k, __m256i b);
VPMOVDB __m128i _mm256_maskz_cvtepi32_epi8( __mmask8 k, __m256i b);VPMOVDB void _mm256_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m256i b);VPMOVDB __m128i _mm_cvtepi32_epi8(__m128i a);VPMOVDB __m128i _mm_mask_cvtepi32_epi8 (__m128i a, __mmask8 k, __m128i b);
VPMOVDB __m128i _mm_maskz_cvtepi32 _epi8( __mmask8 k, __m128i b);
VPMOVDB void _mm_mask_cvtepi32_storeu _epi8(void * , __mmask8 k, __m128i b);
None.
EVEX-encoded instruction, see Table 2-53, “Type E6 Class Exception Conditions.”
#UD If EVEX.vvvv != 1111B.VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to WordINSTRUCTION SET REFERENCE, V
5-548 Vol. 2CVPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
VPMOVDW down converts 32-bit integer elements in the so urce operand (the second operand) into packed words 
using truncation. VPMOVSDW converts signed 32-bit intege rs into packed signed words using signed saturation. 
VPMOVUSDW convert unsigned double-word values into unsigned word values using unsigned saturation. 
The source operand is a ZMM/YMM/XMM register. The de stination operand is a YMM/XMM/XMM register or a 
256/128/64-bit memory location.
Down-converted word elements are written to the destinatio n operand (the first operand) from the least-significant 
word. Word elements of the destination operand are updated according to the writemask. Bits ( MAXVL-
1:256/128/64) of the register destination are zeroed.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W0 33 /r
VPMOVDW xmm1/m64 {k1}{z}, xmm2A V/V AVX512VL
AVX512FConverts 4 packed double-word integers from 
xmm2 into 4 packed word integers in xmm1/m64 
with truncation under writemask k1.
EVEX.128.F3.0F38.W0 23 /r
VPMOVSDW xmm1/m64 {k1}{z}, xmm2A V/V AVX512VL
AVX512FConverts 4 packed signed double-word integers 
from xmm2 into 4 packed signed word integers in 
ymm1/m64 using signed saturation under 
EVEX.128.F3.0F38.W0 13 /r
VPMOVUSDW xmm1/m64 {k1}{z}, xmm2A V/V AVX512VL
from xmm2 into 4 packed unsigned word integers 
in xmm1/m64 using unsigned saturation under 
EVEX.256.F3.0F38.W0 33 /r
VPMOVDW xmm1/m128 {k1}{z}, ymm2A V/V AVX512VL
AVX512FConverts 8 packed double-word integers from 
ymm2 into 8 packed word integers in xmm1/m128 
EVEX.256.F3.0F38.W0 23 /r
VPMOVSDW xmm1/m1 28 {k1}{z}, ymm2A V/V AVX512VL
AVX512FConverts 8 packed signed double-word integers 
from ymm2 into 8 packed signed word integers in 
xmm1/m128 using signed saturation under 
EVEX.256.F3.0F38.W0 13 /r
VPMOVUSDW xmm1/m128 {k1}{z}, ymm2A V/V AVX512VL
from ymm2 into 8 packed unsigned word integers in xmm1/m128 using unsigned saturation under 
EVEX.512.F3.0F38.W0 33 /r
VPMOVDW ymm1/m256 {k1}{z}, zmm2A V/V AVX512F Converts 16 packed double-word integers from 
zmm2 into 16 packed  word integers in 
ymm1/m256 with truncation under writemask k1.
EVEX.512.F3.0F38.W0 23 /r
VPMOVSDW ymm1/m256 {k1}{z}, zmm2A V/V AVX512F Converts 16 packed signed double-word integers 
from zmm2 into 16 packed signed word integers in 
ymm1/m256 using signed saturation under writemask k1.
EVEX.512.F3.0F38.W0 13 /r
VPMOVUSDW ymm1/m256 {k1}{z}, 
from zmm2 into 16 packed unsigned word integers 
in ymm1/m256 using unsigned saturation under writemask k1.
A Half Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AVPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to WordINSTRUCTION SET REFERENCE, V
Vol. 2C 5-549EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVDW instruction (EVEX encoded versions) when dest is a register
i := j * 16m := j * 32IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateDoubleWordToWord (SRC[m+31:m])ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0;
VPMOVDW instruction (EVEX encoded versions) when dest is memory
FI;
ENDFOR
VPMOVSDW instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+15:i] := SaturateSignedDoubleWordToWord (SRC[m+31:m])ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0;VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to WordINSTRUCTION SET REFERENCE, V
5-550 Vol. 2CVPMOVSDW instruction (EVEX encoded versions) when dest is memory
THEN DEST[i+15:i] := SaturateSign edDoubleWordToWord (SRC[m+31:m])
ELSE 
*DEST[i+15:i] remains uncha nged* ; merging-masking
FI;
ENDFOR
VPMOVUSDW instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+15:i] := SaturateUnsi gnedDoubleWordToWord (SRC[m+31:m])
ELSE 
FI
FI;
VPMOVUSDW instruction (EVEX encode d versions) when dest is memory
ELSE 
FI;
ENDFORVPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to WordINSTRUCTION SET REFERENCE, V
Vol. 2C 5-551Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDW __m256i _mm512_cvtepi32_epi16( __m512i a);
VPMOVDW __m256i _mm512_mask_cvtepi32_epi16 (__m256i s, __mmask16 k, __m512i a);
VPMOVDW __m256i _mm512_maskz_cvtepi32_epi16( __mmask16 k, __m512i a);VPMOVDW void _mm512_mask_cvtepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);VPMOVSDW __m256i _mm512_cvtsepi32_epi16( __m512i a);VPMOVSDW __m256i _mm512_mask_cvtsepi32_ep i16(__m256i s, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_maskz_cvtse pi32_epi16( __mmask16 k, __m512i a);
VPMOVSDW void _mm512_mask_cvtsepi32_storeu _epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_cvtusepi32_epi16 __m512i a);VPMOVUSDW __m256i _mm512_mask_cvtusepi32_epi16(__m256i s, __mmask16 k, __m512i a);VPMOVUSDW __m256i _mm512_maskz_cvtusepi32_epi16( __mmask16 k, __m512i a);VPMOVUSDW void _mm512_mask_cv tusepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m128i _mm256_cvtusepi32_epi16(__m256i a);VPMOVUSDW __m128i _mm256_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m256i b);VPMOVUSDW __m128i _mm256_maskz_cvtusepi32_epi16( __mmask8 k, __m256i b);VPMOVUSDW void _mm256_mask_cvtusepi32_store u_epi16(void * , __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm_cvtusepi32_epi16(__m128i a);VPMOVUSDW __m128i _mm_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m128i b);VPMOVUSDW __m128i _mm_maskz_cvtusepi32_epi16( __mmask8 k, __m128i b);VPMOVUSDW void _mm_mask_cvtusepi32_storeu _epi16(void * , __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm256_cvt sepi32_epi16(__m256i a);
VPMOVSDW __m128i _mm256_mask_cvtsepi32_ep i16(__m128i a, __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm256_maskz_cvtse pi32_epi16( __mmask8 k, __m256i b);
VPMOVSDW void _mm256_mask_cvtsepi32_stor eu_epi16(void * , __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm_cvtsepi32_epi16(__m128i a);VPMOVSDW __m128i _mm_mask_cvtsepi32_e pi16(__m128i a, __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm_maskz_cvtsepi32_epi16( __mmask8 k, __m128i b);VPMOVSDW void _mm_mask_cvtsepi32_store u_epi16(void * , __mmask8 k, __m128i b);

VPMOVDW __m128i _mm256_cvtepi32_epi16(__m256i a);VPMOVDW __m128i _mm256_mask_cvtepi32_epi 16(__m128i a, __mmask8 k, __m256i b);
VPMOVDW __m128i _mm256_maskz_cvtepi3 2_epi16( __mmask8 k, __m256i b);
VPMOVDW void _mm256_mask_cvtepi32_storeu _epi16(void * , __mmask8 k, __m256i b);
VPMOVDW __m128i _mm_cvtepi32_epi16(__m128i a);VPMOVDW __m128i _mm_mask_cvtepi32_epi1 6(__m128i a, __mmask8 k, __m128i b);
VPMOVDW __m128i _mm_maskz_cvtepi32 _epi16( __mmask8 k, __m128i b);
VPMOVDW void _mm_mask_cvtepi32_storeu_e pi16(void * , __mmask8 k, __m128i b);
None.
#UD If EVEX.vvvv != 1111B.VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert  a Mask Register to a Vector RegisterINSTRUCTION SET REFERENCE, V
5-552 Vol. 2CVPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector 
Register
Converts a mask register to a vector register. Each elemen t in the destination register is set to all 1’s or all 0’s 
depending on the value of the correspondi ng bit in the source mask register.
The source operand is a mask register. The de stination operand is a ZMM/YMM/XMM register.
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W0 28 /r 
VPMOVM2B xmm1, k1RM V/V AVX512VL
AVX512BWSets each byte in XMM1 to all 1’s or all 0’s based on the value 
of the corresponding bit in k1. 
EVEX.256.F3.0F38.W0 28 /r 
VPMOVM2B ymm1, k1RM V/V AVX512VL
AVX512BWSets each byte in YMM1 to all 1’s or all 0’s based on the value 
EVEX.512.F3.0F38.W0 28 /r 
VPMOVM2B zmm1, k1RM V/V AVX512BW Sets each byte in ZMM1 to all 1’s or all 0’s based on the value 
EVEX.128.F3.0F38.W1 28 /r 
VPMOVM2W xmm1, k1 RM V/V AVX512VL
AVX512BWSets each word in XMM1 to all 1’s or all 0’s ba sed on the value 
EVEX.256.F3.0F38.W1 28 /r
VPMOVM2W ymm1, k1 RM V/V AVX512VL
AVX512BWSets each word in YMM1 to all 1’s or all 0’s based on the value 
EVEX.512.F3.0F38.W1 28 /r 
VPMOVM2W zmm1, k1 RM V/V AVX512BW Sets each word in ZMM1 to all 1’s or all 0’s based on the value 
EVEX.128.F3.0F38.W0 38 /r 
VPMOVM2D xmm1, k1RM V/V AVX512VL
AVX512DQSets each doubleword in XMM1 to  all 1’s or all 0’s based on the 
value of the corresponding bit in k1. 
EVEX.256.F3.0F38.W0 38 /r 
VPMOVM2D ymm1, k1RM V/V AVX512VL
AVX512DQSets each doubleword in YMM1 to  all 1’s or all 0’s based on the 
EVEX.512.F3.0F38.W0 38 /r 
VPMOVM2D zmm1, k1RM V/V AVX512DQ Sets each doubleword in ZM M1 to all 1’s or a ll 0’s based on the 
EVEX.128.F3.0F38.W1 38 /r 
VPMOVM2Q xmm1, k1 RM V/V AVX512VL
AVX512DQSets each quadword in  XMM1 to all 1’s or all 0’s based on the 
EVEX.256.F3.0F38.W1 38 /r 
VPMOVM2Q ymm1, k1 RM V/V AVX512VL
AVX512DQSets each quadword in  YMM1 to all 1’s or all 0’s based on the 
EVEX.512.F3.0F38.W1 38 /r 
VPMOVM2Q zmm1, k1 RM V/V AVX512DQ Sets each quadword in ZMM1  to all 1’s or all 0’s based on the 
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AVPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert  a Mask Register to a Vector RegisterINSTRUCTION SET REFERENCE, V
Vol. 2C 5-553Operation
VPMOVM2B (EVEX encoded versions) 
i := j * 8IF SRC[j]
THEN DEST[i+7:i] := -1 ELSE DEST[i+7:i] := 0
FI;
VPMOVM2W (EVEX encoded versions) 
i := j * 16IF SRC[j]
THEN DEST[i+15:i] := -1 ELSE DEST[i+15:i] := 0
FI;
VPMOVM2D (EVEX encoded versions) 
i := j * 32IF SRC[j]
THEN DEST[i+31:i] := -1 ELSE DEST[i+31:i] := 0
FI;
VPMOVM2Q (EVEX encoded versions) 
i := j * 64IF SRC[j]
THEN DEST[i+63:i] := -1 ELSE DEST[i+63:i] := 0
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert  a Mask Register to a Vector RegisterINSTRUCTION SET REFERENCE, V
5-554 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalents
VPMOVM2B __m512i _mm512_movm_epi8(__mmask64 );
VPMOVM2D __m512i _mm512_movm_epi32(__mmask8 );VPMOVM2Q __m512i _mm512_movm_epi64(__mmask16 );VPMOVM2W __m512i _mm512_movm_epi16(__mmask32 );VPMOVM2B __m256i _mm256_movm_epi8(__mmask32 );VPMOVM2D __m256i _mm256_movm_epi32(__mmask8 );VPMOVM2Q __m256i _mm256_movm_epi64(__mmask8 );VPMOVM2W __m256i _mm256_movm_epi16(__mmask16 );VPMOVM2B __m128i _mm_movm_epi8(__mmask16 );VPMOVM2D __m128i _mm_movm_epi32(__mmask8 );VPMOVM2Q __m128i _mm_movm_epi64(__mmask8 );VPMOVM2W __m128i _mm_movm_epi16(__mmask8 );
None.
EVEX-encoded instruction, see Table 2-55,  “Type E7NM Class Exception Conditions.”
Additionally:#UD If EVEX.vvvv != 1111B.VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to ByteINSTRUCTION SET REFERENCE, V
Vol. 2C 5-555VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
VPMOVQB down converts 64-bit integer elements in the so urce operand (the second operand) into packed byte 
elements using truncation. VPMOVSQB converts signed 64-bit  integers into packed signed bytes using signed satu-
ration. VPMOVUSQB convert unsigned quad -word values into unsigned byte values using unsigned saturation. The 
source operand is a vector register. The destination operand is an XMM register or a memory location.
Down-converted byte elements are written to the destinatio n operand (the first operand) from the least-significant 
byte. Byte elements of the destination operand are updated according to the writemask. Bits ( MAXVL-1 :64) of the 
destination are zeroed.
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W0 32 /r
VPMOVQB xmm1/m16 {k1}{z}, xmm2A V/V AVX512VL
AVX512FConverts 2 packed quad-word integers from xmm2 
into 2 packed byte inte gers in xmm1/m16 with 
truncation under writemask k1.
EVEX.128.F3.0F38.W0 22 /r
VPMOVSQB xmm1/m16 {k1}{z}, xmm2A V/V AVX512VL
AVX512FConverts 2 packed signed quad-word integers from 
xmm2 into 2 pack ed signed byte integers in 
xmm1/m16 using signed satu ration under writemask 
k1.
EVEX.128.F3.0F38.W0 12 /r
VPMOVUSQB xmm1/m16 {k1}{z}, xmm2A V/V AVX512VL
AVX512FConverts 2 packed unsigned quad-word integers 
from xmm2 into 2 packed unsigned byte integers in xmm1/m16 using unsigned saturation under 
EVEX.256.F3.0F38.W0 32 /r
VPMOVQB xmm1/m32 {k1}{z}, ymm2A V/V AVX512VL
AVX512FConverts 4 packed quad-word integers from ymm2 
EVEX.256.F3.0F38.W0 22 /r
VPMOVSQB xmm1/m32 {k1}{z}, ymm2A V/V AVX512VL
AVX512FConverts 4 packed signed quad-word integers from 
ymm2 into 4 packed signed byte integers in xmm1/m32 using signed satu ration under writemask 
k1.
EVEX.256.F3.0F38.W0 12 /r
VPMOVUSQB xmm1/m32 {k1}{z}, ymm2A V/V AVX512VL
AVX512FConverts 4 packed unsigned quad-word integers 
from ymm2 into 4 packed unsigned byte integers in xmm1/m32 using unsigned saturation under 
EVEX.512.F3.0F38.W0 32 /r
VPMOVQB xmm1/m64 {k1}{z}, zmm2A V/V AVX512F Converts 8 packed quad-word integers from zmm2 
EVEX.512.F3.0F38.W0 22 /r
VPMOVSQB xmm1/m64 {k1}{z}, zmm2A V/V AVX512F Converts 8 packed signed quad-word integers from 
zmm2 into 8 packed sign ed byte integers in 
xmm1/m64 using signed satu ration under writemask 
k1.
EVEX.512.F3.0F38.W0 12 /r
VPMOVUSQB xmm1/m64 {k1}{z}, zmm2A V/V AVX512F Converts 8 packed unsigned quad-word integers 
from zmm2 into 8 packed un signed byte integers in 
xmm1/m64 using unsigned saturation under writemask k1.
A Eighth Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AVPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to ByteINSTRUCTION SET REFERENCE, V
5-556 Vol. 2COperation
VPMOVQB instruction (EVEX encoded versions) when dest is a register
i := j * 8m := j * 64IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := Truncate QuadWordToByte (SRC[m+63:m])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/8] := 0;
VPMOVQB instruction (EVEX encoded versions) when dest is memory
ELSE

ELSE 
FI
FI;
ELSE 
*DEST[i+7:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VPMOVSQB instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+7:i] := SaturateSign edQuadWordToByte (SRC[m+63:m])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/8] := 0;VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to ByteINSTRUCTION SET REFERENCE, V
Vol. 2C 5-557VPMOVSQB instruction (EVEX encoded versions) when dest is memory
ELSE 
FI;
ENDFOR
VPMOVUSQB instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+7:i] := SaturateUnsi gnedQuadWordToByte  (SRC[m+63:m])
ELSE 
FI
FI;
VPMOVUSQB instruction (EVEX encoded versions) when dest is memory
ELSE 
FI;
ENDFORVPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to ByteINSTRUCTION SET REFERENCE, V
5-558 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalents
VPMOVQB __m128i _mm512_cvtepi64_epi8( __m512i a);
VPMOVQB __m128i _mm512_mask_cvtepi64_e pi8(__m128i s, __mmask8 k, __m512i a);
VPMOVQB __m128i _mm512_maskz_cvtepi6 4_epi8( __mmask8 k, __m512i a);
VPMOVQB void _mm512_mask_cvtepi64_storeu_ epi8(void * d, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_cvtsepi64_epi8( __m512i a);VPMOVSQB __m128i _mm512_mask_cvtsepi64_epi8(__m128i s, __mmask8 k, __m512i a);VPMOVSQB __m128i _mm512_maskz_cvtse pi64_epi8( __mmask8 k, __m512i a);
VPMOVSQB void _mm512_mask_cvtsepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);VPMOVUSQB __m128i _mm512_cvtusepi64_epi8( __m512i a);VPMOVUSQB __m128i _mm512_mask_cvtusepi64_epi8(__m128i s, __mmask8 k, __m512i a);VPMOVUSQB __m128i _mm512_maskz_cvtusepi64_epi8( __mmask8 k, __m512i a);VPMOVUSQB void _mm512_mask_cvtusepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);VPMOVUSQB __m128i _mm256_cvtusepi64_epi8(__m256i a);VPMOVUSQB __m128i _mm256_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m256i b);VPMOVUSQB __m128i _mm256_maskz_cvtusepi64_epi8( __mmask8 k, __m256i b);VPMOVUSQB void _mm256_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m256i b);VPMOVUSQB __m128i _mm_cvtusepi64_epi8(__m128i a);VPMOVUSQB __m128i _mm_mask_cvtusepi64_ep i8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQB __m128i _mm_maskz_cvtuse pi64_epi8( __mmask8 k, __m128i b);
VPMOVUSQB void _mm_mask_cvtusepi64_storeu _epi8(void * , __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm256_cvtsepi64_epi8(__m256i a);VPMOVSQB __m128i _mm256_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m256i b);VPMOVSQB __m128i _mm256_maskz_cvtse pi64_epi8( __mmask8 k, __m256i b);
VPMOVSQB void _mm256_mask_cvtsepi64_stor eu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm_cvtsepi64_epi8(__m128i a);VPMOVSQB __m128i _mm_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m128i b);VPMOVSQB __m128i _mm_maskz_cvtsepi64_epi8( __mmask8 k, __m128i b);VPMOVSQB void _mm_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m128i b);VPMOVQB __m128i _mm256_cvtepi64_epi8(__m256i a);VPMOVQB __m128i _mm256_mask_cvtepi64_e pi8(__m128i a, __mmask8 k, __m256i b);
VPMOVQB __m128i _mm256_maskz_cvtepi64_epi8( __mmask8 k, __m256i b);VPMOVQB void _mm256_mask_cvtepi64_store u_epi8(void * , __mmask8 k, __m256i b);
VPMOVQB __m128i _mm_cvtepi64_epi8(__m128i a);VPMOVQB __m128i _mm_mask_cvtepi64_epi8 (__m128i a, __mmask8 k, __m128i b);
VPMOVQB __m128i _mm_maskz_cvtepi 64_epi8( __mmask8 k, __m128i b);
VPMOVQB void _mm_mask_cvtepi64_storeu_e pi8(void * , __mmask8 k, __m128i b);
None.
#UD If EVEX.vvvv != 1111B.VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWordINSTRUCTION SET REFERENCE, V
Vol. 2C 5-559VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
VPMOVQW down converts 64-bit integer elements in the so urce operand (the second operand) into packed double-
words using truncation. VPMOVSQW converts signed 64-bit integers into packed signed doublewords using signed 
saturation. VPMOVUSQW convert unsigned quad-word values  into unsigned double-wor d values using unsigned 
saturation. 
The source operand is a ZMM/YMM/X MM register. The destination operand is a YMM/XMM/XMM register or a 
256/128/64-bit memory location.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W0 35 /r
VPMOVQD xmm1/m128 {k1}{z}, xmm2AV / V A V X 5 1 2 V L
into 2 packed double-word integers in xmm1/m128 
with truncation subject to writemask k1.
EVEX.128.F3.0F38.W0 25 /r
VPMOVSQD xmm1/m64 {k1}{z}, xmm2AV / V A V X 5 1 2 V L
xmm2 into 2 packed signed double-word integers in xmm1/m64 using signed saturation subject to 
EVEX.128.F3.0F38.W0 15 /r
VPMOVUSQD xmm1/m64 {k1}{z}, xmm2AV / V A V X 5 1 2 V L
from xmm2 into 2 packed unsigned double-word integers in xmm1/m64 us ing unsigned saturation 
EVEX.256.F3.0F38.W0 35 /r
VPMOVQD xmm1/m128 {k1}{z}, ymm2AV / V A V X 5 1 2 V L
into 4 packed double-word integers in xmm1/m128 
EVEX.256.F3.0F38.W0 25 /r
VPMOVSQD xmm1/m128 {k1}{z}, ymm2AV / V A V X 5 1 2 V L
ymm2 into 4 packed signed double-word integers in xmm1/m128 using signed saturation subject to 
EVEX.256.F3.0F38.W0 15 /r
VPMOVUSQD xmm1/m128 {k1}{z}, ymm2AV / V A V X 5 1 2 V L
from ymm2 into 4 packed unsigned double-word integers in xmm1/m128 using unsigned saturation 
EVEX.512.F3.0F38.W0 35 /r
VPMOVQD ymm1/m256 {k1}{z}, zmm2A V/V AVX512F Converts 8 packed quad-word integers from zmm2 
into 8 packed double-word integers in ymm1/m256 with truncation subject to writemask k1.
EVEX.512.F3.0F38.W0 25 /r
VPMOVSQD ymm1/m256 {k1}{z}, zmm2A V/V AVX512F Converts 8 packed signed quad-word integers from 
zmm2 into 8 packed signed double-word integers in 
ymm1/m256 using signed saturation subject to 
EVEX.512.F3.0F38.W0 15 /r
VPMOVUSQD ymm1/m256 {k1}{z}, zmm2A V/V AVX512F Converts 8 packed unsigned quad-word integers 
from zmm2 into 8 packed unsigned double-word 
integers in ymm1/m256 us ing unsigned saturation 
A Half Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AVPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWordINSTRUCTION SET REFERENCE, V
5-560 Vol. 2CDown-converted doubleword elements are written to the destination operand (the first operand) from the least-
significant doubleword. Doubleword elem ents of the destination operand are updated according to the writemask. 
Bits ( MAXVL-1 :256/128/64) of the register destination are zeroed.
Operation
VPMOVQD instruction (EVEX encoded version) reg-reg form
i := j * 32m := j * 64IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TruncateQuadWordToDWord (SRC[m+63:m])ELSE *zeroing-masking* ; zeroing-masking
FI
FI;
VPMOVQD instruction (EVEX encoded version) memory form
THEN DEST[i+31:i] := TruncateQuadWordToDWord (SRC[m+63:m])ELSE *DEST[i+31:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VPMOVSQD instruction (EVEX encoded version) reg-reg form
THEN DEST[i+31:i] := SaturateSi gnedQuadWordToDWord (SRC[m+63:m])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0;VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWordINSTRUCTION SET REFERENCE, V
Vol. 2C 5-561VPMOVSQD instruction (EVEX encoded version) memory form

FI
FI;
FI;
ENDFOR
ELSE 
FI
FI;
THEN DEST[i+31:i] := SaturateSignedQuadWordToDWord (SRC[m+63:m])ELSE *DEST[i+31:i] remains unchanged* ; merging-masking
FI;
ENDFOR
VPMOVUSQD instruction (EVEX en coded version) reg-reg form
THEN DEST[i+31:i] := SaturateUnsi gnedQuadWordToDWord (SRC[m+63:m])
ELSE 
FI
FI;
VPMOVUSQD instruction (EVEX encoded version) memory form
FI;
ENDFORVPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWordINSTRUCTION SET REFERENCE, V
5-562 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalents
VPMOVQD __m256i _mm512_cvtepi64_epi32( __m512i a);
VPMOVQD __m256i _mm512_mask_cvtepi64_epi32(__m256i s, __mmask8 k, __m512i a);VPMOVQD __m256i _mm512_maskz_cvtepi64_epi32( __mmask8 k, __m512i a);VPMOVQD void _mm512_mask_cvtepi64_storeu_ epi32(void * d, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_cvtsepi64_epi32( __m512i a);VPMOVSQD __m256i _mm512_mask_cvtsepi64_epi32(__m256i s, __mmask8 k, __m512i a);VPMOVSQD __m256i _mm512_maskz_cvtse pi64_epi32( __mmask8 k, __m512i a);
VPMOVSQD void _mm512_mask_cvtsepi64_storeu _epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_cvtusepi64_epi32( __m512i a);VPMOVUSQD __m256i _mm512_mask_cvtusepi64_epi32(__m256i s, __mmask8 k, __m512i a);VPMOVUSQD __m256i _mm512_maskz_cvtusepi64_epi32( __mmask8 k, __m512i a);VPMOVUSQD void _mm512_mask_cvtusepi64_stor eu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);VPMOVUSQD __m128i _mm_mask_cvtusepi64_ep i32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_ epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);VPMOVSQD __m128i _mm256_maskz_cvtse pi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_stor eu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);VPMOVSQD __m128i _mm_mask_cvtsepi64_epi 32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);VPMOVSQD void _mm_mask_cvt sepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);VPMOVQD void _mm256_mask_cvtepi64_storeu_ epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);VPMOVQD __m128i _mm_maskz_cvtepi64 _epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu _epi32(void * , __mmask8 k, __m128i b);
None.
#UD If EVEX.vvvv != 1111B.VPMOVQW/VPMOVSQW/VPMOVUSQW—D own Convert QWord to WordINSTRUCTION SET REFERENCE, V
Vol. 2C 5-563VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
VPMOVQW down converts 64-bit integer elements in the so urce operand (the second operand) into packed words 
using truncation. VPMOVSQW converts signed 64-bit integers into packed signed words using signed saturation. VPMOVUSQW convert unsigned quad-word values into unsigned word values using unsigned saturation. 
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit 
Down-converted word elements are written to the destination operand (the first operand) from the least-significant 
1:128/64/32) of the register destination are zeroed.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W0 34 /r
VPMOVQW xmm1/m32 {k1}{z}, xmm2AV / V A V X 5 1 2 V L
into 2 packed word integers in xmm1/m32 with 
EVEX.128.F3.0F38.W0 24 /r
VPMOVSQW xmm1/m32 {k1}{z}, xmm2AV / V A V X 5 1 2 V L
AVX512FConverts 8 packed signed quad-word integers from 
zmm2 into 8 packed signed word integers in xmm1/m32 using signed saturation under writemask 
k1.
EVEX.128.F3.0F38.W0 14 /r
VPMOVUSQW xmm1/m32 {k1}{z}, xmm2AV / V A V X 5 1 2 V L
AVX512FConverts 2 packed unsigned quad-word integers from 
xmm2 into 2 packed unsigned word integers in xmm1/m32 using unsigned saturation under 
EVEX.256.F3.0F38.W0 34 /r
VPMOVQW xmm1/m64 {k1}{z}, ymm2AV / V A V X 5 1 2 V L
into 4 packed word integers in xmm1/m64 with 
EVEX.256.F3.0F38.W0 24 /r
VPMOVSQW xmm1/m64 {k1}{z}, ymm2AV / V A V X 5 1 2 V L
ymm2 into 4 packed sign ed word integers in 
k1.
EVEX.256.F3.0F38.W0 14 /r
VPMOVUSQW xmm1/m64 {k1}{z}, ymm2AV / V A V X 5 1 2 V L
AVX512FConverts 4 packed unsigned quad-word integers from 
ymm2 into 4 packed unsigned word integers in xmm1/m64 using unsigned saturation under 
EVEX.512.F3.0F38.W0 34 /r
VPMOVQW xmm1/m128 {k1}{z}, zmm2A V/V AVX512F Converts 8 packed quad-word integers from zmm2 
into 8 packed word integers in xmm1/m128 with truncation unde r writemask k1.
EVEX.512.F3.0F38.W0 24 /r
VPMOVSQW xmm1/m128 {k1}{z}, zmm2A V/V AVX512F Converts 8 packed signed quad-word integers from 
zmm2 into 8 packed signed word integers in 
EVEX.512.F3.0F38.W0 14 /r
VPMOVUSQW xmm1/m128 {k1}{z}, 
zmm2A V/V AVX512F Converts 8 packed unsigned quad-word integers from 
zmm2 into 8 pack ed unsigned word integers in 
A Quarter Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AVPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to WordINSTRUCTION SET REFERENCE, V
5-564 Vol. 2CEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVQW instruction (EVEX encoded versions) when dest is a register
i := j * 16m := j * 64IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateQuadWordToWord (SRC[m+63:m])ELSE 
FI
FI;
VPMOVQW instruction (EVEX encoded versions) when dest is memory
FI;
ENDFOR
VPMOVSQW instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+15:i] := SaturateSi gnedQuadWordToWord (SRC[m+63:m])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/4] := 0;VPMOVQW/VPMOVSQW/VPMOVUSQW—D own Convert QWord to WordINSTRUCTION SET REFERENCE, V
Vol. 2C 5-565VPMOVSQW instruction (EVEX encoded versions) when dest is memory
THEN DEST[i+15:i] := SaturateSignedQuadWordToWord (SRC[m+63:m])ELSE 
FI;
ENDFOR
VPMOVUSQW instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+15:i] := SaturateUnsignedQuadWordToWord (SRC[m+63:m])ELSE 
FI
FI;
VPMOVUSQW instruction (EVEX encoded versions) when dest is memory

FI
FI;
FI;
ENDFOR
FI
FI;
FI;
ENDFORVPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to WordINSTRUCTION SET REFERENCE, V
5-566 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalents
VPMOVQW __m128i _mm512_cvtepi64_epi16( __m512i a);
VPMOVQW __m128i _mm512_mask_cvtepi64_epi 16(__m128i s, __mmask8 k, __m512i a);
VPMOVQW __m128i _mm512_maskz_cvtep i64_epi16( __mmask8 k, __m512i a);
VPMOVQW void _mm512_mask_cvtepi64_storeu _epi16(void * d, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_cvtsepi64_epi16( __m512i a);VPMOVSQW __m128i _mm512_mask_cvtsepi64_epi16(__m128i s, __mmask8 k, __m512i a);VPMOVSQW __m128i _mm512_maskz_cvtsepi64_epi16( __mmask8 k, __m512i a);VPMOVSQW void _mm512_mask_cvtsepi64_storeu _epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_cvtusepi64_epi16( __m512i a);VPMOVUSQW __m128i _mm512_mask_cvtusepi64_epi16(__m128i s, __mmask8 k, __m512i a);VPMOVUSQW __m128i _mm512_maskz_cvtusepi64_epi16( __mmask8 k, __m512i a);VPMOVUSQW void _mm512_mask_cvtusepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);VPMOVUSQD __m128i _mm_mask_cvtusepi64_ep i32(__m128i a, __mmask8 k, __m128i b);
None.
#UD If EVEX.vvvv != 1111B.VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to ByteINSTRUCTION SET REFERENCE, V
Vol. 2C 5-567VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
VPMOVWB down converts 16-bit integers into packed by tes using truncation. VPMOVSWB converts signed 16-bit 
integers into packed signed bytes using signed satu ration. VPMOVUSWB convert unsigned word values into 
unsigned byte values using unsigned saturation. 
byte. Byte elements of the destination operand are updated according to the writemask. Bits ( MAXVL-
1:256/128/64) of the register destination are zeroed.
En64/32 
bit Mode 
Feature 
EVEX.128.F3.0F38.W0 30 /r
VPMOVWB xmm1/m64 {k1}{z}, xmm2A V/V AVX512VL
AVX512BWConverts 8 packed word in tegers from xmm2 into 8 
packed bytes in xmm1/m64  with trunca tion under 
EVEX.128.F3.0F38.W0 20 /r
VPMOVSWB xmm1/m64 {k1}{z}, xmm2A V/V AVX512VL
AVX512BWConverts 8 packed signed word integers from xmm2 
into 8 packed signed bytes in xmm1/m64 using signed saturation under writemask k1.
EVEX.128.F3.0F38.W0 10 /r
VPMOVUSWB xmm1/m64 {k1}{z}, 
xmm2A V/V AVX512VL
AVX512BWConverts 8 packed unsigned word integers from 
xmm2 into 8 packed unsigned bytes in 8mm1/m64 
using unsigned saturation under writemask k1.
EVEX.256.F3.0F38.W0 30 /r
VPMOVWB xmm1/m128 {k1}{z}, 
ymm2A V/V AVX512VL
AVX512BWConverts 16 packed word integers from ymm2 into 
16 packed bytes in xmm1 /m128 with truncation 
EVEX.256.F3.0F38.W0 20 /r
VPMOVSWB xmm1/m128 {k1}{z}, 
AVX512BWConverts 16 packed signed word integers from ymm2 
into 16 packed signed bytes in xmm1/m128 using 
signed saturation under writemask k1.
EVEX.256.F3.0F38.W0 10 /r
VPMOVUSWB xmm1/m128 {k1}{z}, ymm2A V/V AVX512VL
AVX512BWConverts 16 packed unsigned word integers from 
ymm2 into 16 packed unsigned bytes in xmm1/m128 using unsigned saturation under writemask k1.
EVEX.512.F3.0F38.W0 30 /r
VPMOVWB ymm1/m256 {k1}{z}, 
zmm2A V/V AVX512BW Converts 32 packed wo rd integers from zmm2 into 
32 packed bytes in y mm1/m256 with truncation 
EVEX.512.F3.0F38.W0 20 /r
VPMOVSWB ymm1/m256 {k1}{z}, 
zmm2A V/V AVX512BW Converts 32 packed signed word integers from zmm2 
into 32 packed signed bytes in ymm1/m256 using 
EVEX.512.F3.0F38.W0 10 /r
VPMOVUSWB ymm1/m256 {k1}{z}, zmm2A V/V AVX512BW Converts 32 packed unsigned word integers from 
zmm2 into 32 packed unsigned bytes in ymm1/m256 
A Half Mem ModRM:r/m (w) ModRM:reg (r) N/A N/AVPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to ByteINSTRUCTION SET REFERENCE, V
5-568 Vol. 2COperation
VPMOVWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO Kl-1
i := j * 8m := j * 16IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := Trunca teWordToByte (SRC[m+15:m])
ELSE 
FI
FI;
VPMOVWB instruction (EVEX encoded versions) when dest is memory
ELSE 
FI;
ENDFOR
VPMOVSWB instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+7:i] := SaturateSi gnedWordToByte (SRC[m+15:m])
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL/2] := 0;VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to ByteINSTRUCTION SET REFERENCE, V
Vol. 2C 5-569VPMOVSWB instruction (EVEX encode d versions) when dest is memory
ELSE 
FI;
ENDFOR
VPMOVUSWB instruction (EVEX encoded versions) when dest is a register
THEN DEST[i+7:i] := SaturateUn signedWordToByte (SRC[m+15:m])
ELSE 
FI
FI;
VPMOVUSWB instruction (EVEX encoded versions) when dest is memory
ELSE 
FI;
ENDFORVPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to ByteINSTRUCTION SET REFERENCE, V
5-570 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalents
VPMOVUSWB __m256i _mm512_cvtusepi16_epi8(__m512i a);
VPMOVUSWB __m256i _mm512_mask_cvtusepi16_epi8(__m256i a, __mmask32 k, __m512i b);VPMOVUSWB __m256i _mm512_maskz_cvtus epi16_epi8( __mmask32 k, __m512i b);
VPMOVUSWB void _mm512_mask_cvtusepi16_store u_epi8(void * , __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_cvtsepi16_epi8(__m512i a);VPMOVSWB __m256i _mm512_mask_cvtsepi16_ep i8(__m256i a, __mma sk32 k, __m512i b);
VPMOVSWB __m256i _mm512_maskz_cvt sepi16_epi8( __mmask32 k, __m512i b);

FI
FI;
ELSE 
FI;
VPMOVSWB void _mm512_mask_cvtsepi16_storeu_epi8(void * , __mmask32 k, __m512i b);VPMOVWB __m256i _mm512_cvtepi16_epi8(__m512i a);VPMOVWB __m256i _mm512_mask_cvtepi16_epi8(__m256i a, __mmask32 k, __m512i b);VPMOVWB __m256i _mm512_maskz_cvtepi16_epi8( __mmask32 k, __m512i b);VPMOVWB void _mm512_mask_cvtepi16_store u_epi8(void * , __mmask32 k, __m512i b);
VPMOVUSWB __m128i _mm256_cvtusepi16_epi8(__m256i a);VPMOVUSWB __m128i _mm256_mask_cvtusepi16_epi8(__m128i a, __mmask16 k, __m256i b);VPMOVUSWB __m128i _mm256_maskz_cvtus epi16_epi8( __mmask16 k, __m256i b);
VPMOVUSWB void _mm256_mask_cvtusepi16_store u_epi8(void * , __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm_cvtusepi16_epi8(__m128i a);VPMOVUSWB __m128i _mm_mask_cvtusepi16_ep i8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSWB __m128i _mm_maskz_cvtusepi 16_epi8( __mmask8 k, __m128i b);
VPMOVUSWB void _mm_mask_cvtusepi16_stor eu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm256_cvtsepi16_epi8(__m256i a);VPMOVSWB __m128i _mm256_mask_cvtsepi16_ep i8(__m128i a, __mma sk16 k, __m256i b);
VPMOVSWB __m128i _mm256_maskz_cvt sepi16_epi8( __mmask16 k, __m256i b);
VPMOVSWB void _mm256_mask_cvtsepi16_storeu_epi8(void * , __mmask16 k, __m256i b);VPMOVSWB __m128i _mm_cvtsepi16_epi8(__m128i a);VPMOVSWB __m128i _mm_mask_cvtsepi16_epi 8(__m128i a, __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm_maskz_cvtsep i16_epi8( __mmask8 k, __m128i b);
VPMOVSWB void _mm_mask_cvtsepi16_store u_epi8(void * , __mmask8 k, __m128i b);
VPMOVWB __m128i _mm256_cvtepi16_epi8(__m256i a);VPMOVWB __m128i _mm256_mask_cvtepi16_epi8(__m128i a, __mmask16 k, __m256i b);VPMOVWB __m128i _mm256_maskz_cvtepi16_epi8( __mmask16 k, __m256i b);VPMOVWB void _mm256_mask_cvtepi16_store u_epi8(void * , __mmask16 k, __m256i b);
VPMOVWB __m128i _mm_cvtepi16_epi8(__m128i a);VPMOVWB __m128i _mm_mask_cvtepi16_epi8(__m128i a, __mmask8 k, __m128i b);VPMOVWB __m128i _mm_maskz_cvtepi16_epi8( __mmask8 k, __m128i b);VPMOVWB void _mm_mask_cvtepi16_storeu_e pi8(void * , __mmask8 k, __m128i b);
None.
#UD If EVEX.vvvv != 1111B.VPMULTISHIFTQB—Select Packed Unalig ned Bytes From Quadword SourcesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-571VPMULTISHIFTQB—Select Packed Unaligned Bytes From Quadword Sources
This instruction selects eight unaligned bytes from each input qword element of the second source operand (the 
third operand) and writes eight assembled bytes for each  qword element in the destination operand (the first 
operand). Each byte result is selected using a byte-gra nular shift control within the corresponding qword element 
of the first source operand (the second operand). Each by te result in the destination operand is updated under the 
Only the low 6 bits of each control byte are used to select  an 8-bit slot to extract the output byte from the qword 
data in the second source operand. The starting bit of th e 8-bit slot can be unaligned relative to any byte boundary 
and is extracted from the input qword source at the location  specified in the low 6-bit of the control byte. If the 8-
bit slot would exceed the qword boundary, the out-of-bound portion of the 8-bit slot is wrapped back to start from 
bit 0 of the input qword element.
ister, a 512/256/128-bit memory location or a 512/256/12 8-bit vector broadcasted from a 64-bit memory loca-
tion. The destination operand is a ZMM/YMM/XMM register.Opcode / 
En64/32 
bit Mode SupportCPUID Feature 
EVEX.128.66.0F38.W1 83 /r
VPMULTISHIFTQB xmm1 {k1}{z}, 
xmm2,xmm3/m128/m64bcstA V/V AVX512_VBMI
AVX512VLSelect unaligned bytes from qwords in 
xmm3/m128/m64bcst using control bytes in 
xmm2, write byte results to xmm1 under k1.
EVEX.256.66.0F38.W1 83 /r
VPMULTISHIFTQB ymm1 {k1}{z}, 
ymm2,ymm3/m256/m64bcstA V/V AVX512_VBMI
ymm3/m256/m64bcst using control bytes in 
ymm2, write byte results to ymm1 under k1.
EVEX.512.66.0F38.W1 83 /r
VPMULTISHIFTQB zmm1 {k1}{z}, zmm2,zmm3/m512/m64bcstA V/V AVX512_VBMI Select unaligned bytes from qwords in 
zmm3/m512/m64bcst using control bytes in zmm2, write byte results to zmm1 under k1.
A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPMULTISHIFTQB—Select Packed Unaligned Bytes From Quadword SourcesINSTRUCTION SET REFERENCE, V
5-572 Vol. 2COperation
VPMULTISHIFTQB DEST, SRC1, SRC2 (EVEX encoded version)
(KL, VL) = (2, 128),(4, 256), (8, 512)
FOR i := 0 TO KL-1
IF EVEX.b=1 AND src2 is memory THEN
tcur := src2.qword[0]; //broadcasting
ELSE
tcur := src2.qword[i];
FI;FOR j := 0 to 7 
ctrl := src1.qword[i].byte[j] & 63;FOR k := 0 to 7 
res.bit[k] := tcur.bit[ (ctrl+k) mod 64 ];
ENDFORIF k1[i*8+j] or no writemask THEN
DEST.qword[i].by te[j] := res;
DEST.qword[i]. byte[j] := 0;
ENDFOR
ENDFORDEST.qword[MAX_VL-1:VL] := 0;
VPMULTISHIFTQB __m512i _mm512_multishif t_epi64_epi8( __m512i a, __m512i b);
VPMULTISHIFTQB __m512i _mm512_mask_multishift_epi64_e pi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMULTISHIFTQB __m512i _mm512_maskz_multishift_ep i64_epi8( __mmask64 k, __m512i a, __m512i b);
VPMULTISHIFTQB __m256i _mm256_multishif t_epi64_epi8( __m256i a, __m256i b);
VPMULTISHIFTQB __m256i _mm256_mask_multishift_epi64_e pi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMULTISHIFTQB __m256i _mm256_maskz_multishift_ep i64_epi8( __mmask32 k, __m256i a, __m256i b);
VPMULTISHIFTQB __m128i _m m_multishift_epi64_epi8( __m128i a, __m128i b);
VPMULTISHIFTQB __m128i _mm_mask_multishift_epi64_ep i8(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULTISHIFTQB __m128i _m m_maskz_multishift_epi64_epi8( __mmask8 k, __m128i a, __m128i b);
None.
See Table 2-50, “Type E4NF Class Exception Conditions.”VPOPCNT—Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORDINSTRUCTION SET REFERENCE, V
Vol. 2C 5-573VPOPCNT—Return the Count of Number of Bits  Set to 1 in BYTE/WORD/DWORD/QWORD
This instruction counts the number of bits set to one in each  byte, word, dword or qword element of its source (e.g., 
zmm2 or memory) and places the results in the destinat ion register (zmm1). This instruction supports memory 
fault suppression.Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F38.W0 54 /r
VPOPCNTB xmm1{k1}{z}, 
xmm2/m128AV / V A V X 5 1 2 _ B I T A L G
AVX512VLCounts the number of bits set to one in 
xmm2/m128 and puts the result in xmm1 with 
EVEX.256.66.0F38.W0 54 /r
VPOPCNTB ymm1{k1}{z}, ymm2/m256AV / V A V X 5 1 2 _ B I T A L G
ymm2/m256 and puts the result in ymm1 with 
EVEX.512.66.0F38.W0 54 /r
VPOPCNTB zmm1{k1}{z}, 
zmm2/m512A V/V AVX512_BITALG Counts the numb er of bits set to one in 
zmm2/m512 and puts the result in zmm1 with 
EVEX.128.66.0F38.W1 54 /r
VPOPCNTW xmm1{k1}{z}, 
EVEX.256.66.0F38.W1 54 /r
VPOPCNTW ymm1{k1}{z}, 
ymm2/m256AV / V A V X 5 1 2 _ B I T A L G
EVEX.512.66.0F38.W1 54 /r
VPOPCNTW zmm1{k1}{z}, zmm2/m512A V/V AVX512_BITALG Counts the numb er of bits set to one in 
EVEX.128.66.0F38.W0 55 /r
VPOPCNTD xmm1{k1}{z}, 
xmm2/m128/m32bcstB V/V AVX512_VPOPCNTDQ
xmm2/m128/m32bcst and puts the result in 
EVEX.256.66.0F38.W0 55 /r
VPOPCNTD ymm1{k1}{z}, 
ymm2/m256/m32bcstB V/V AVX512_VPOPCNTDQ
ymm2/m256/m32bcst and puts the result in 
EVEX.512.66.0F38.W0 55 /r
VPOPCNTD zmm1{k1}{z}, zmm2/m512/m32bcstB V/V AVX512_VPOPCNTDQ Counts the nu mber of bits set to one in 
zmm2/m512/m32bcst and puts the result in zmm1 with writemask k1.
EVEX.128.66.0F38.W1 55 /r
VPOPCNTQ xmm1{k1}{z}, 
xmm2/m128/m64bcstB V/V AVX512_VPOPCNTDQ
EVEX.256.66.0F38.W1 55 /r
VPOPCNTQ ymm1{k1}{z}, 
ymm2/m256/m64bcstB V/V AVX512_VPOPCNTDQ
EVEX.512.66.0F38.W1 55 /r
VPOPCNTQ zmm1{k1}{z}, zmm2/m512/m64bcstB V/V AVX512_VPOPCNTDQ Counts the nu mber of bits set to one in

VPOPCNTQ zmm1{k1}{z}, zmm2/m512/m64bcstB V/V AVX512_VPOPCNTDQ Counts the nu mber of bits set to one in 
zmm2/m512/m64bcst and puts the result in zmm1 with writemask k1.
A Full Mem ModRM:reg (w ) ModRM:r/m (r) N/A N/A
B Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVPOPCNT—Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORDINSTRUCTION SET REFERENCE, V
5-574 Vol. 2COperation
VPOPCNTB
(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.byte[j] := POPCNT(SRC.byte[j])
ELSE IF *merging-masking*:
ELSE:
VPOPCNTW
(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1:
DEST.word[j] := POPCNT(SRC.word[j])
*DEST.word[j] remains unchanged*
ELSE:
VPOPCNTD
(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1:
IF SRC is broadcast memop:
t := SRC.dword[0]
ELSE:
t := SRC.dword[j]
DEST.dword[j] := POPCNT(t)
*DEST..dword[j] remains unchanged*
ELSE:
DEST..dword[j] := 0
VPOPCNTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1:
t := SRC.qword[0]
ELSE:
t := SRC.qword[j]
DEST.qword[j] := POPCNT(t)
*DEST..qword[j] remains unchanged*
ELSE:
DEST..qword[j] := 0
DEST[MAX_VL-1:VL] := 0VPOPCNT—Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORDINSTRUCTION SET REFERENCE, V
Vol. 2C 5-575Intel C/C++ Compiler Intrinsic Equivalent
VPOPCNTW __m128i _mm_popcnt_epi16(__m128i);
VPOPCNTW __m128i _mm_mask_popcnt_epi16(__m128i, __mmask8, __m128i);VPOPCNTW __m128i _mm_maskz_popcnt_epi16(__mmask8, __m128i);VPOPCNTW __m256i _mm256_popcnt_epi16(__m256i);VPOPCNTW __m256i _mm256_mask_popcnt_ epi16(__m256i, __mmask16, __m256i);
VPOPCNTW __m256i _mm256_maskz_popcnt_epi16(__mmask16, __m256i);VPOPCNTW __m512i _mm512_popcnt_epi16(__m512i);VPOPCNTW __m512i _mm512_mask_popcnt_ epi16(__m512i, __mmask32, __m512i);
VPOPCNTW __m512i  _mm512_maskz_popcnt_epi16(__mmask32, __m512i);VPOPCNTQ __m128i  _mm_popcnt_epi64(__m128i);VPOPCNTQ __m128i  _mm_mask_popcnt_ epi64(__m128i, __mmask8, __m128i);
VPOPCNTQ __m128i  _mm_maskz_po pcnt_epi64(__mmask8, __m128i);
VPOPCNTQ __m256i  _mm256_popcnt_epi64(__m256i);VPOPCNTQ __m256i  _mm256_mask_popcnt _epi64(__m256i, __mmask8, __m256i);
VPOPCNTQ __m256i  _mm256_maskz_popcnt_epi64(__mmask8, __m256i);VPOPCNTQ __m512i  _mm512_popcnt_epi64(__m512i);VPOPCNTQ __m512i  _mm512_mask_popcnt _epi64(__m512i, __mmask8, __m512i);
VPOPCNTQ __m512i  _mm512_maskz_popcnt_epi64(__mmask8, __m512i);VPOPCNTD __m128i  _mm_popcnt_epi32(__m128i);VPOPCNTD __m128i  _mm_mask_popcn t_epi32(__m128i, __mmask8, __m128i);
VPOPCNTD __m128i  _mm_maskz_ popcnt_epi32(__mmask8, __m128i);
VPOPCNTD __m256i  _mm256_popcnt_epi32(__m256i);VPOPCNTD __m256i  _mm256_mask_popcnt _epi32(__m256i, __mmask8, __m256i);
VPOPCNTD __m256i  _mm256_maskz_popcnt_epi32(__mmask8, __m256i);VPOPCNTD __m512i  _mm512_popcnt_epi32(__m512i);VPOPCNTD __m512i  _mm512_mask_popcnt_epi32(__m512i, __mmask16, __m512i);VPOPCNTD __m512i  _mm512_maskz_popcnt_epi32(__mmask16, __m512i);VPOPCNTB __m128i  _mm_ popcnt_epi8(__m128i);
VPOPCNTB __m128i  _mm_mask_popcnt_epi8(__m128i, __mmask16, __m128i);VPOPCNTB __m128i  _mm_maskz_popcnt_epi8(__mmask16, __m128i);VPOPCNTB __m256i  _mm256_popcnt_epi8(__m256i);VPOPCNTB __m256i  _mm256_mask_popcnt_epi8(__m256i, __mmask32, __m256i);VPOPCNTB __m256i  _mm256_maskz_popcnt_epi8(__mmask32, __m256i);VPOPCNTB __m512i  _mm512_popcnt_epi8(__m512i);VPOPCNTB __m512i  _mm512_mask_popcnt_epi8(__m512i, __mmask64, __m512i);VPOPCNTB __m512i  _mm512_maskz_popcnt_epi8(__mmask64, __m512i);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate LeftINSTRUCTION SET REFERENCE, V
5-576 Vol. 2CVPROLD/VPROLVD/VPROLQ/VPROL VQ—Bit Rotate Left 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 15 /r
VPROLVD xmm1 {k1}{z}, xmm2, 
AVX512FRotate doublewords in xmm2 left by count in the 
corresponding element of xmm3/m128/m32bcst. 
Result written to xmm1 under writemask k1.
EVEX.128.66.0F.W0 72 /1 ib
VPROLD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8A V/V AVX512VL
AVX512FRotate doublewords in xmm2/m128/m32bcst left 
by imm8. Result written to xmm1 using writemask k1.
EVEX.128.66.0F38.W1 15 /r
VPROLVQ xmm1 {k1}{z}, xmm2, 
AVX512FRotate quadwords in xmm2  left by count in the 
corresponding element of xmm3/m128/m64bcst. 
EVEX.128.66.0F.W1 72 /1 ib
VPROLQ xmm1 {k1}{z}, 
xmm2/m128/m64bcst, imm8A V/V AVX512VL
AVX512FRotate quadwords in xmm2/m128/m64bcst left 
by imm8. Result written to xmm1 using 
EVEX.256.66.0F38.W0 15 /r
VPROLVD ymm1 {k1}{z}, ymm2, 
AVX512FRotate doublewords in ymm2  left by count in the 
corresponding element of ymm3/m256/m32bcst. 
Result written to ymm1 under writemask k1.
EVEX.256.66.0F.W0 72 /1 ib
VPROLD ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8A V/V AVX512VL
AVX512FRotate doublewords in ymm2/m256/m32bcst left 
by imm8. Result written to ymm1 using writemask k1.
EVEX.256.66.0F38.W1 15 /r
VPROLVQ ymm1 {k1}{z}, ymm2, 
AVX512FRotate quadwords in ymm2  left by count in the 
corresponding element of ymm3/m256/m64bcst. 
EVEX.256.66.0F.W1 72 /1 ib
VPROLQ ymm1 {k1}{z}, 
ymm2/m256/m64bcst, imm8A V/V AVX512VL
AVX512FRotate quadwords in ymm2/m256/m64bcst left 
by imm8. Result written to ymm1 using 
EVEX.512.66.0F38.W0 15 /r
VPROLVD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstB V/V AVX512F Rotate left of doub lewords in zmm2 by count in 
the corresponding element of zmm3/m512/m32bcst. Resu lt written to zmm1 
EVEX.512.66.0F.W0 72 /1 ib
VPROLD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8A V/V AVX512F Rotate left of doublewords in 
zmm3/m512/m32bcst by i mm8. Result written to 
EVEX.512.66.0F38.W1 15 /r
VPROLVQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstB V/V AVX512F Rotate quadwords in zmm2 left by count in the 
corresponding element of zmm3/m512/m64bcst. 
Result written to z mm1under writemask k1.
EVEX.512.66.0F.W1 72 /1 ib
VPROLQ zmm1 {k1}{z}, 
zmm2/m512/m64bcst, imm8A V/V AVX512F Rotate quadwords in zmm2/m512/m64bcst left 
by imm8. Result written to zmm1 using 
A Full VEX.vvvv (w) ModRM:r/m (R) imm8 N/A
B Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate LeftINSTRUCTION SET REFERENCE, V
Vol. 2C 5-577Description
Rotates the bits in the individual data elements (doublewor ds, or quadword) in the first source operand to the left 
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31 
(for doublewords), or 63 (for a quadword), then the co unt operand modulo the data size (32 or 64) is used. 
EVEX.128 encoded version: The destination operand is a X MM register. The source operand is a XMM register or a 
memory location (for immediate form). The count operan d can come either from an XMM register or a memory 
location or an 8-bit immediate. Bits (MAXVL-1: 128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YM M register. The source operand is a YMM register or a 
location or an 8-bit immediate. Bits (MAXVL-1: 256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a Z MM register updated according to the writemask. For the 
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count 
operand in variable form, the first source operand (the se cond operand) is a ZMM register and the counter operand 
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit 
Operation
LEFT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 32;DEST[31:0] := (SRC << COUN T) | (SRC >> (32 - COUNT));
LEFT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 64;DEST[63:0] := (SRC << COUN T) | (SRC >> (64 - COUNT));
VPROLD (EVEX encoded versions)
THEN DEST[i+31:i] := LEFT_ROT ATE_DWORDS(SRC1[31:0], imm8)
ELSE DEST[i+31:i] := LEFT_ROT ATE_DWORDS(SRC1[i+31:i], imm8)
FI;
ELSE 

Operation
FI;
ELSE 
FI
FI;
VPROLVD (EVEX encoded versions)
THEN DEST[i+31:i] := LEFT_ROTATE_ DWORDS(SRC1[i+31:i], SRC2[31:0])
ELSE DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[ i+31:i], SRC2[i+31:i])
FI;VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate LeftINSTRUCTION SET REFERENCE, V
5-578 Vol. 2CELSE 
FI
FI;
VPROLQ (EVEX encoded versions)
THEN DEST[i+63:i] := LEFT_ROT ATE_QWORDS(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := LEFT_ROT ATE_QWORDS(SRC1[i+63:i], imm8)
FI;
ELSE 
FI
FI;
VPROLVQ (EVEX encoded versions)
THEN DEST[i+63:i] := LEFT_ROTAT E_QWORDS(SRC1[i+63:i], SRC2[63:0])
ELSE DEST[i+63:i] := LEFT_ROTATE_ QWORDS(SRC1[i+63:i ], SRC2[i+63:i])
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate LeftINSTRUCTION SET REFERENCE, V
Vol. 2C 5-579Intel C/C++ Compiler Intrinsic Equivalent
VPROLD __m512i _mm512_rol_epi32(__m512i a, int imm);
VPROLD __m512i _mm512_mask_rol_epi32(__m512i  a, __mmask16 k, __m512i b, int imm);
VPROLD __m512i _mm512_maskz_rol_epi32 ( __mmask16 k, __m512i a, int imm);
VPROLD __m256i _mm256_rol_epi32(__m256i a, int imm);VPROLD __m256i _mm256_mask_rol_epi32(__m25 6i a, __mmask8 k, __m256i b, int imm);
VPROLD __m256i _mm256_maskz_rol_epi32( __mmask8 k, __m256i a, int imm);VPROLD __m128i _mm_rol_epi32(__m128i a, int imm);VPROLD __m128i _mm_mask_rol_epi32(__m128i a, __mmask8 k, __m 128i b, int imm);
VPROLD __m128i _mm_maskz_rol_epi32(  __mmask8 k, __m128i a, int imm);
VPROLQ __m512i _mm512_rol_e pi64(__m512i a, int imm);
VPROLQ __m512i _mm512_mask_rol_epi64(__m5 12i a, __mmask8 k, __m512i b, int imm);
VPROLQ __m512i _mm512_maskz_rol_epi64 (__mmask8 k, __m512i a, int imm);
VPROLQ __m256i _mm256_rol_e pi64(__m256i a, int imm);
VPROLQ __m256i _mm256_mask_rol_epi64(__m2 56i a, __mmask8 k, __m256i b, int imm);
VPROLQ __m256i _mm256_maskz_rol_epi64 ( __mmask8 k, __m256i a, int imm);
VPROLQ __m128i _mm_rol_epi64(__m128i a, int imm);VPROLQ __m128i _mm_mask_r ol_epi64(__m128i a, __mmask 8 k, __m128i b, int imm);
VPROLQ __m128i _mm_maskz_rol_epi64(  __mmask8 k, __m128i a, int imm);
VPROLVD __m512i _mm512_rolv_epi 32(__m512i a, __m512i cnt);
VPROLVD __m512i _mm512_mask_rolv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPROLVD __m512i _mm512_maskz_rolv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPROLVD __m256i _mm256_rolv_epi 32(__m256i a, __m256i cnt);
VPROLVD __m256i _mm256_mask_ro lv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVD __m256i _mm256_maskz_rolv_epi32( __mmask8 k, __m256i a, __m256i cnt);
VPROLVD __m128i _mm_rolv_epi32 (__m128i a, __m128i cnt);
VPROLVD __m128i _mm_mask_rolv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVD __m128i _mm_maskz_rolv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPROLVQ __m512i _mm512_rolv_ep i64(__m512i a, __m512i cnt);
VPROLVQ __m512i _mm512_mask_rolv_epi64(__m512i  a, __mmask8 k, __m512i b, __m512i cnt);
VPROLVQ __m512i _mm512_maskz_rolv_epi64( __mmask8 k, __m512i a, __m512i cnt);VPROLVQ __m256i _mm256_rolv_ep i64(__m256i a, __m256i cnt);
VPROLVQ __m256i _mm256_mask_rolv_epi64(__m256i  a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVQ __m256i _mm256_maskz_rolv_epi64(__mmask8 k, __m256i a, __m256i cnt);VPROLVQ __m128i _mm_rolv_epi 64(__m128i a, __m128i cnt);
VPROLVQ __m128i _mm_mask_rolv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVQ __m128i _mm_maskz_rolv_epi64(__mmask8 k, __m128i a, __m128i cnt);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate RightINSTRUCTION SET REFERENCE, V
5-580 Vol. 2CVPRORD/VPRORVD/VPRORQ/VPROR VQ—Bit Rotate Right 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 14 /r
VPRORVD xmm1 {k1}{z}, xmm2, 
AVX512FRotate doublewords in xm m2 right by count in 
the corresponding element of 
xmm3/m128/m32bcst, store result using 
EVEX.128.66.0F.W0 72 /0 ib
VPRORD xmm1 {k1}{z}, 
AVX512FRotate doublewords in xmm2/m128/m32bcst 
right by imm8, store result using writemask k1.
EVEX.128.66.0F38.W1 14 /r
VPRORVQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstB V/V AVX512VL
AVX512FRotate quadwords in xmm2  right by count in the 
corresponding element of xmm3/m128/m64bcst, store result using writemask k1.
EVEX.128.66.0F.W1 72 /0 ib
VPRORQ xmm1 {k1}{z}, 
AVX512FRotate quadwords in xm m2/m128/m64bcst right 
by imm8, store result using writemask k1.
EVEX.256.66.0F38.W0 14 /r
VPRORVD ymm1 {k1}{z}, ymm2, 
AVX512FRotate doublewords in ym m2 right by count in 
ymm3/m256/m32bcst, store using result writemask k1.
EVEX.256.66.0F.W0 72 /0 ib
VPRORD ymm1 {k1}{z}, 
AVX512FRotate doublewords in ymm2/m256/m32bcst 
EVEX.256.66.0F38.W1 14 /r
VPRORVQ ymm1 {k1}{z}, ymm2, 
AVX512FRotate quadwords in ymm2  right by count in the 
corresponding element of ymm3/m256/m64bcst, 
store result using writemask k1.
EVEX.256.66.0F.W1 72 /0 ib
VPRORQ ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8A V/V AVX512VL
AVX512FRotate quadwords in ymm2/m256/m64bcst right 
EVEX.512.66.0F38.W0 14 /r
VPRORVD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512F Rotate doublewords in zmm2 right by count in 
zmm3/m512/m32bcst, store result using writemask k1.
EVEX.512.66.0F.W0 72 /0 ib
VPRORD zmm1 {k1}{z}, 
zmm2/m512/m32bcst, imm8A V/V AVX512F Rotate doublewords in zmm2/m512/m32bcst 
EVEX.512.66.0F38.W1 14 /r
VPRORVQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstB V/V AVX512F Rotate quadwords in zmm2 right by count in the 
corresponding element of zmm3/m512/m64bcst, 
EVEX.512.66.0F.W1 72 /0 ib
VPRORQ zmm1 {k1}{z}, zmm2/m512/m64bcst, imm8A V/V AVX512F Rotate quadwords in zmm2/m512/m64bcst right 
B Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPRORD/VPRORVD/VPRORQ/VP RORVQ—Bit Rotate RightINSTRUCTION SET REFERENCE, V
Vol. 2C 5-581Description
Rotates the bits in the individual data elements (doublewor ds, or quadword) in the first source operand to the right 
Operation
RIGHT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 32;DEST[31:0] := (SRC >> COUN T) | (SRC << (32 - COUNT));
RIGHT_ROTATE_QWORDS(SRC, COUNT_SRC)

Operation
COUNT := COUNT_SRC modulo 64;DEST[63:0] := (SRC >> COUN T) | (SRC << (64 - COUNT));
VPRORD (EVEX encoded versions)
THEN DEST[i+31:i] := RIGHT_ROTATE_DWORDS( SRC1[31:0], imm8)ELSE DEST[i+31:i] := RIGHT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
FI;
ELSE 
FI
FI;
VPRORVD (EVEX encoded versions)
THEN DEST[i+31:i] := RIGHT_ROTATE _DWORDS(SRC1[i+31:i], SRC2[31:0])
ELSE DEST[i+31:i] := RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
FI;VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate RightINSTRUCTION SET REFERENCE, V
5-582 Vol. 2CELSE 
FI
FI;
VPRORQ (EVEX encoded versions)
THEN DEST[i+63:i] := RIGHT_RO TATE_QWORDS(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[i+63:i], imm8])
FI;
ELSE 
FI
FI;
VPRORVQ (EVEX encoded versions)
THEN DEST[i+63:i] := RIGHT_ROTATE _QWORDS(SRC1[i+63:i], SRC2[63:0])
ELSE DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0VPRORD/VPRORVD/VPRORQ/VP RORVQ—Bit Rotate RightINSTRUCTION SET REFERENCE, V
Vol. 2C 5-583Intel C/C++ Compiler Intrinsic Equivalent
VPRORD __m512i _mm512_ror_epi32(__m512i a, int imm);
VPRORD __m512i _mm512_mask_ror_epi32(__m51 2i a, __mmask16 k, __m512i b, int imm);
VPRORD __m512i _mm512_maskz_ror_epi32(  __mmask16 k, __m512i a, int imm);
VPRORD __m256i _mm256_ror_epi32(__m256i a, int imm);VPRORD __m256i _mm256_mask_ror_epi32(__m25 6i a, __mmask8 k, __m256i b, int imm);
VPRORD __m256i _mm256_maskz_ror_epi32(  __mmask8 k, __m256i a, int imm);
VPRORD __m128i _mm_ror_epi32(__m128i a, int imm);VPRORD __m128i _mm_mask_ror_epi32(__m128i  a, __mmask8 k, __m128i b, int imm);
VPRORD __m128i _mm_maskz_ror_epi32(  __mmask8 k, __m128i a, int imm);
VPRORQ __m512i _mm512_ror_e pi64(__m512i a, int imm);
VPRORQ __m512i _mm512_mask_ror_epi64(__m51 2i a, __mmask8 k, __m512i b, int imm);
VPRORQ __m512i _mm512_maskz_ror_epi 64(__mmask8 k, __m512i a, int imm);
VPRORQ __m256i _mm256_ror_e pi64(__m256i a, int imm);
VPRORQ __m256i _mm256_mask_ror_epi64(__m25 6i a, __mmask8 k, __m256i b, int imm);
VPRORQ __m256i _mm256_maskz_ror_epi 64( __mmask8 k, __m256i a, int imm);
VPRORQ __m128i _mm_ror_epi64(__m128i a, int imm);VPRORQ __m128i _mm_mask_ror _epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORQ __m128i _mm_maskz_ror_epi64(  __mmask8 k, __m128i a, int imm);
VPRORVD __m512i _mm512_rorv_epi32(__m512i a, __m512i cnt);VPRORVD __m512i _mm512_mask_rorv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPRORVD __m512i _mm512_maskz_rorv_epi32(__ mmask16 k, __m512i a, __m512i cnt);
VPRORVD __m256i _mm256_rorv_epi32(__m256i a, __m256i cnt);VPRORVD __m256i _mm256_mask_rorv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVD __m256i _mm256_maskz_rorv_epi32(__ mmask8 k, __m256i a, __m256i cnt);
VPRORVD __m128i _mm_rorv_epi32(__m128i a, __m128i cnt);VPRORVD __m128i _mm_mask_rorv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVD __m128i _mm_maskz_ro rv_epi32(__mmask8 k, __m 128i a, __m128i cnt);
VPRORVQ __m512i _mm512_rorv_epi64(__m512i a, __m512i cnt);VPRORVQ __m512i _mm512_mask_rorv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);VPRORVQ __m512i _mm512_maskz_rorv_epi64( __mmask8 k, __m512i a, __m512i cnt);VPRORVQ __m256i _mm256_rorv_epi64(__m256i a, __m256i cnt);VPRORVQ __m256i _mm256_mask_rorv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);VPRORVQ __m256i _mm256_maskz_rorv_epi64(__mmask8 k, __m256i a, __m256i cnt);VPRORVQ __m128i _mm_rorv_epi64 (__m128i a, __m128i cnt);
VPRORVQ __m128i _mm_mask_rorv_epi64(__m128i  a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVQ __m128i _mm_maskz_rorv_epi64(__mmask8 k, __m128i a, __m128i cnt);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Pa cked Dword, Packed Qword with Signed Dword, SignedINSTRUCTION SET REFERENCE, V
5-584 Vol. 2CVPSCATTERDD/VPSCATTERDQ/VPSCA TTERQD/VPSCATTERQQ—Scatte r Packed Dword, Packed 
Qword with Signed Dword, Signed Qword Indices
Stores up to 16 elements (8 elements for qword indices) in doubleword vector or 8 elements in quadword vector to 
the memory locations pointed by base address BASE_A DDR and index vector VINDEX , with scale SCALE. The 
elements are specified via the VSIB (i.e., the index register  is a vector register, holding packed indices). Elements 
will only be stored if their corresponding mask bit is one. Th e entire mask register will be set to zero by this instruc-
tion unless it triggers an exception.
This instruction can be suspended by an exception if at le ast one element is already scattered (i.e., if the exception 
register and the mask register are part ially updated. If any traps or interru pts are pending from already scattered 
elements, they will be delivered in lieu of the exception; in  this case, EFLAG.RF is set to one so an instruction break-
point is not re-triggered when the instruction is continued.
Note that:
•Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to 
MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not 
overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 A0 /vsib 
VPSCATTERDD vm32x {k1}, xmm1A V/V AVX512VL
AVX512FUsing signed dword indices, scatter dword values to 
memory using writemask k1.
EVEX.256.66.0F38.W0 A0 /vsib
VPSCATTERDD vm32y {k1}, ymm1A V/V AVX512VL
EVEX.512.66.0F38.W0 A0 /vsib 
VPSCATTERDD vm32z {k1}, zmm1A V/V AVX512F Using signed dword indices, scatter dword values to 
EVEX.128.66.0F38.W1 A0 /vsib 
VPSCATTERDQ vm32x {k1}, xmm1A V/V AVX512VL
AVX512FUsing signed dword indices, scatter qword values to 
EVEX.256.66.0F38.W1 A0 /vsib 
VPSCATTERDQ vm32x {k1}, ymm1A V/V AVX512VL
EVEX.512.66.0F38.W1 A0 /vsib 
VPSCATTERDQ vm32y {k1}, zmm1A V/V AVX512F Using signed dword indices, scatter qword values to 
EVEX.128.66.0F38.W0 A1 /vsib 
VPSCATTERQD vm64x {k1}, xmm1A V/V AVX512VL
AVX512FUsing signed qword indices, scatter dword values to 
EVEX.256.66.0F38.W0 A1 /vsib 
VPSCATTERQD vm64y {k1}, xmm1A V/V AVX512VL
EVEX.512.66.0F38.W0 A1 /vsib 
VPSCATTERQD vm64z {k1}, ymm1A V/V AVX512F Using signed qword indices, scatter dword values to 
EVEX.128.66.0F38.W1 A1 /vsib 
VPSCATTERQQ vm64x {k1}, xmm1A V/V AVX512VL
AVX512FUsing signed qword indices, scatter qword values to 
EVEX.256.66.0F38.W1 A1 /vsib 
VPSCATTERQQ vm64y {k1}, ymm1A V/V AVX512VL
EVEX.512.66.0F38.W1 A1 /vsib
VPSCATTERQQ vm64z {k1}, zmm1A V/V AVX512F Using signed qword indices, scatter qword values to 
A Tuple1 ScalarBaseReg (R): VSIB:base,
VectorReg(R): VSIB:indexModRM:reg (r) N/A N/AVPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Pa cked Dword, Packed Qword with Signed Dword, Signed INSTRUCTION SET REFERENCE, V
Vol. 2C 5-585ordering model. Note that this does not account for non-overlapping indices that map into the same physical 
address locations.

•If two or more destination indices completely overlap, the “earlier” write(s) may be skipped.
elements closer to the LSB of the destination ZMM will be completed (and non-faulting). Individual elements 
•Elements may be scattered in any order, but faults must be  delivered in a right-to left order; thus, elements to 
•If this instruction overwrites itself and then takes a fa ult, only a subset of elements may be completed before 
the fault is delivered (as described above). If the faul t handler completes and attempts to re-execute this 
instruction, the new instruction will be executed, and the scatter will not complete.
ignored.
The instruction will #UD fault if the k0 mask register is specified.The instruction will #UD fault if EVEX.Z = 1. 
Operation
VPSCATTERDD (EVEX encoded versions)
(KL, VL)= (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1
THEN MEM[BASE_ADDR +SignExtend(VINDEX[i +31:i]) * SCALE + DISP] := SRC[i+31:i]
k1[j] := 0
FI;
ENDFORk1[MAX_KL-1:KL] := 0
VPSCATTERDQ (EVEX encoded versions)
(KL, VL)= (2, 128),  (4, 256), (8, 512)
THEN MEM[BASE_ADDR +SignExtend(VINDEX[k +31:k]) * SCALE + DISP] := SRC[i+63:i]
k1[j] := 0
FI;VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Pa cked Dword, Packed Qword with Signed Dword, SignedINSTRUCTION SET REFERENCE, V
5-586 Vol. 2CENDFOR
k1[MAX_KL-1:KL] := 0VPSCATTERQD (EVEX encoded versions)(KL, VL)= (2, 128) , (4, 256), (8, 512)
THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] := SRC[i+31:i]
k1[j] := 0
FI;
VPSCATTERQQ (EVEX encoded versions)
(KL, VL)= (2, 128) , (4, 256), (8, 512)
THEN MEM[BASE_ADDR + (VINDEX[j+63:j ]) * SCALE + DISP] := SRC[i+63:i]
FI;
VPSCATTERDD void _mm512_i32scatter_epi32(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_i32scatter_epi32(void * base, __m256i vdx, __m256i a, int scale);VPSCATTERDD void _mm_i32scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);VPSCATTERDD void _mm512_mask_i32scatter_epi32(void * base, __mmask16 k, __m512i vdx, __m512i a, int scale);VPSCATTERDD void _mm256_mask_i32scatter_epi32(void * ba se, __mmask8 k, __m256i vd x, __m256i a, int scale);
VPSCATTERDD void _mm_mask_i32scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);VPSCATTERDQ void _mm512_i32scatter_epi64(void * base, __m256i vdx, __m512i a, int scale);VPSCATTERDQ void _mm256_i32scatter_epi64(void * base, __m128i vdx, __m256i a, int scale);VPSCATTERDQ void _mm_i32scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);VPSCATTERDQ void _mm512_mask_i32scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m512i a, int scale);VPSCATTERDQ void _mm256_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m256i a, int scale);VPSCATTERDQ void _mm_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);VPSCATTERQD void _mm512_i64scatter_epi32(void * base, __m512i vdx, __m256i a, int scale);VPSCATTERQD void _mm256_i64scatter_epi32(void * base, __m256i vdx, __m128i a, int scale);VPSCATTERQD void _mm_i64scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);VPSCATTERQD void _mm512_mask_i64scatter_epi32(void * base, __mmask8 k, __m512i vdx, __m256i a, int scale);VPSCATTERQD void _mm256_mask_i64scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m128i a, int scale);VPSCATTERQD void _mm_mask_i64scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);VPSCATTERQQ void _mm512_i64scatter_epi64(void * base, __m512i vdx, __m512i a, int scale);VPSCATTERQQ void _mm256_i64scatter_epi64(void * base, __m256i vdx, __m256i a, int scale);VPSCATTERQQ void _mm_i64scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);VPSCATTERQQ void _mm512_mask_i64scatter_epi64(void * base, __mmask8 k, __m512i vdx, __m512i a, int scale);VPSCATTERQQ void _mm256_mask_i64scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);VPSCATTERQQ void _mm_mask_i64scatter_epi64(void * ba se, __mmask8 k, __m128i vdx, __m128i a, int scale);
None.VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Pa cked Dword, Packed Qword with Signed Dword, Signed INSTRUCTION SET REFERENCE, V
Vol. 2C 5-587Other Exceptions
See Table 2-61, “Type E12 Class Exception Conditions.”VPSHLD—Concatenate and Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, V
5-588 Vol. 2CVPSHLD—Concatenate and Shift Packed Data Left Logical
Concatenate packed data, extract result shifted to the left by constant value.This instruction supports memory fault suppression.Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F3A.W1 70 /r /ib
VPSHLDW xmm1{k1}{z}, xmm2, 
xmm3/m128, imm8AV / VA V X 5 1 2 _ V B M I 2
AVX512VLConcatenate destination and source operands, 
extract result shifted to  the left by constant 
EVEX.256.66.0F3A.W1 70 /r /ib
VPSHLDW ymm1{k1}{z}, ymm2, ymm3/m256, imm8AV / VA V X 5 1 2 _ V B M I 2
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 70 /r /ib
VPSHLDW zmm1{k1}{z}, zmm2, 
zmm3/m512, imm8A V/V AVX512_VBMI2 Concatenate dest ination and source operands, 
value in imm8 into zmm1.
EVEX.128.66.0F3A.W0 71 /r /ib
VPSHLDD xmm1{k1}{z}, xmm2, 
xmm3/m128/m32bcst, imm8BV / VA V X 5 1 2 _ V B M I 2
EVEX.256.66.0F3A.W0 71 /r /ib
VPSHLDD ymm1{k1}{z}, ymm2, 
ymm3/m256/m32bcst, imm8BV / VA V X 5 1 2 _ V B M I 2
EVEX.512.66.0F3A.W0 71 /r /ib
VPSHLDD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst, imm8B V/V AVX512_VBMI2 Concatenate dest ination and source operands, 
EVEX.128.66.0F3A.W1 71 /r /ib
VPSHLDQ xmm1{k1}{z}, xmm2, 
xmm3/m128/m64bcst, imm8BV / VA V X 5 1 2 _ V B M I 2
EVEX.256.66.0F3A.W1 71 /r /ib
VPSHLDQ ymm1{k1}{z}, ymm2, 
ymm3/m256/m64bcst, imm8BV / VA V X 5 1 2 _ V B M I 2
EVEX.512.66.0F3A.W1 71 /r /ib
VPSHLDQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8B V/V AVX512_VBMI2 Concatenate dest ination and source operands, 
A Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8 (r)
B Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8 (r)VPSHLD—Concatenate and Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-589Operation
VPSHLDW DEST, SRC2, SRC3, imm8
tmp := concat(SRC2.word[j], SRC3.word[j]) << (imm8 & 15)
DEST.word[j] := tmp.word[1]
*ELSE DEST.word[j] remains unchanged*
VPSHLDD DEST, SRC2, SRC3, imm8

IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
tmp := concat(SRC2.dword[j], tsrc3) << (imm8 & 31)DEST.dword[j] := tmp.dword[1]
*ELSE DEST.dword[j] remains unchanged*
VPSHLDQ DEST, SRC2, SRC3, imm8
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
tmp := concat(SRC2.qword[j], tsrc3) << (imm8 & 63)DEST.qword[j] := tmp.qword[1]
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0VPSHLD—Concatenate and Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, V
5-590 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPSHLDD __m128i _mm_shldi_epi32(__m128i, __m128i, int);
VPSHLDD __m128i _mm_mask_shldi_epi32(__m1 28i, __mmask8, __m128i, __m128i, int);
VPSHLDD __m128i _mm_maskz_shldi_epi32( __mmask8, __m128i, __m128i, int);
VPSHLDD __m256i _mm256_shldi_epi32(__m256i, __m256i, int);VPSHLDD __m256i _mm256_mask_shldi_epi32(__m2 56i, __mmask8, __m256i, __m256i, int);
VPSHLDD __m256i _mm256_maskz_shldi_epi32(__mmask8, __m256i, __m256i, int);VPSHLDD __m512i _mm512_shldi_epi32(__m512i, __m512i, int);VPSHLDD __m512i _mm512_mask_shldi_epi32(__m512i, __mmask16, __m512i, __m512i, int);VPSHLDD __m512i _mm512_maskz_shldi_epi3 2(__mmask16, __m512i, __m512i, int);
VPSHLDQ __m128i _mm_shldi_epi64(__m128i, __m128i, int);VPSHLDQ __m128i _mm_mask_shldi_epi64(__m 128i, __mmask8, __m128i, __m128i, int);
VPSHLDQ __m128i _mm_maskz_shldi_epi 64(__mmask8, __m128i, __m128i, int);
VPSHLDQ __m256i _mm256_shldi_epi64(__m256i, __m256i, int);VPSHLDQ __m256i _mm256_mask_shldi_epi64( __m256i, __mmask8, __m256i, __m256i, int);
VPSHLDQ __m256i _mm256_maskz_shldi_e pi64(__mmask8, __m256i, __m256i, int);
VPSHLDQ __m512i _mm512_shldi_epi64(__m512i, __m512i, int);VPSHLDQ __m512i _mm512_mask_shldi_epi64( __m512i, __mmask8, __m512i, __m512i, int);
VPSHLDQ __m512i _mm512_maskz_shldi_e pi64(__mmask8, __m512i, __m512i, int);
VPSHLDW __m128i _mm_shldi_epi16(__m128i, __m128i, int);VPSHLDW __m128i _mm_mask_shldi_epi16(__m128i, __mmask8, __m128i, __m128i, int);VPSHLDW __m128i _mm_maskz_shldi_epi 16(__mmask8, __m128i, __m128i, int);
VPSHLDW __m256i _mm256_shldi_epi16(__m256i, __m256i, int);VPSHLDW __m256i _mm256_mask_shldi_epi16( __m256i, __mmask16, __m256i, __m256i, int);
VPSHLDW __m256i _mm256_maskz_shldi_epi16 (__mmask16, __m256i, __m256i, int);
VPSHLDW __m512i _mm512_shldi_epi16(__m512i, __m512i, int);VPSHLDW __m512i _mm512_mask_shldi_epi16( __m512i, __mmask32, __m512i, __m512i, int);
VPSHLDW __m512i _mm512_maskz_shldi_epi16 (__mmask32, __m512i, __m512i, int);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPSHLDV—Concatenate and Variable Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-591VPSHLDV—Concatenate and Variable Shift Packed Data Left Logical 
Concatenate packed data, extract result shifted to the left by variable value.This instruction supports memory fault suppression.Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F38.W1 70 /r
VPSHLDVW xmm1{k1}{z}, xmm2, 
xmm3/m128AV / VA V X 5 1 2 _ V B M I 2
AVX512VLConcatenate xmm1 and xmm2, extract result 
shifted to the left by value in xmm3/m128 into 
xmm1.
EVEX.256.66.0F38.W1 70 /r
VPSHLDVW ymm1{k1}{z}, ymm2, ymm3/m256AV / VA V X 5 1 2 _ V B M I 2
AVX512VLConcatenate ymm1 and ymm2, extract result 
shifted to the left by value in xmm3/m256 into 
ymm1.
EVEX.512.66.0F38.W1 70 /r
VPSHLDVW zmm1{k1}{z}, zmm2, 
zmm3/m512A V/V AVX512_VBMI2 Concatenate zmm1 and zmm2, extract result 
shifted to the left by value in zmm3/m512 into 
zmm1.
EVEX.128.66.0F38.W0 71 /r
VPSHLDVD xmm1{k1}{z}, xmm2, 
xmm3/m128/m32bcstBV / VA V X 5 1 2 _ V B M I 2
xmm1.
EVEX.256.66.0F38.W0 71 /r
VPSHLDVD ymm1{k1}{z}, ymm2, 
ymm3/m256/m32bcstBV / VA V X 5 1 2 _ V B M I 2
ymm1.
EVEX.512.66.0F38.W0 71 /r
VPSHLDVD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcstB V/V AVX512_VBMI2 Concatenate zmm1 and zmm2, extract result 
zmm1.
EVEX.128.66.0F38.W1 71 /r
VPSHLDVQ xmm1{k1}{z}, xmm2, 
xmm3/m128/m64bcstBV / VA V X 5 1 2 _ V B M I 2
xmm1.
EVEX.256.66.0F38.W1 71 /r
VPSHLDVQ ymm1{k1}{z}, ymm2, 
ymm3/m256/m64bcstBV / VA V X 5 1 2 _ V B M I 2
ymm1.
EVEX.512.66.0F38.W1 71 /r
VPSHLDVQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcstB V/V AVX512_VBMI2 Concatenate zmm1 and zmm2, extract result 
zmm1.
A Full Mem ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPSHLDV—Concatenate and Variable Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, V
5-592 Vol. 2COperation
FUNCTION concat(a,b):
IF words:
d.word[1] := ad.word[0] := breturn d
ELSE IF dwords:
q.dword[1] := aq.dword[0] := breturn q
ELSE IF qwords:
o.qword[1] := ao.qword[0] := breturn o
VPSHLDVW DEST, SRC2, SRC3
tmp := concat(DEST.word[j], SRC2 .word[j]) << (SRC3.word[j] & 15)
VPSHLDVD DEST, SRC2, SRC3
ELSE:
tmp := concat(DEST.dword[j], SR C2.dword[j]) << (tsrc3 & 31)
DEST.dword[j] := tmp.dword[1]
*ELSE DEST.dwo rd[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0VPSHLDV—Concatenate and Variable Shift Packed Data Left LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-593VPSHLDVQ DEST, SRC2, SRC3
ELSE:
tmp := concat(DEST.qword[j], SR C2.qword[j]) << (tsrc3 & 63)
DEST.qword[j] := tmp.qword[1]
VPSHLDVW __m128i _mm_shldv_epi16(__m128i, __m128i, __m128i);
VPSHLDVW __m128i _mm_mask_shldv_epi16 (__m128i, __mmask8, __m128i, __m128i);
VPSHLDVW __m128i _mm_maskz_shldv_epi16(__mmask8, __m128i, __m128i, __m128i);VPSHLDVW __m256i _mm256_shldv_epi16(__m256i, __m256i, __m256i);VPSHLDVW __m256i _mm256_mask_shldv_epi16(__m256i, __mmask16, __m256i, __m256i);VPSHLDVW __m256i _mm256_maskz_shldv_epi16(__mmask16, __m256i, __m256i, __m256i);VPSHLDVQ __m512i  _mm512_shldv_epi 64(__m512i, __m512i, __m512i);
VPSHLDVQ __m512i  _mm512_mask_shldv_epi 64(__m512i, __mmask8, __m512i, __m512i);
VPSHLDVQ __m512i  _mm512_maskz_shldv_epi 64(__mmask8, __m512i, __m512i, __m512i);
VPSHLDVW __m128i  _mm_shldv_epi16(__m128i, __m128i, __m128i);VPSHLDVW __m128i  _mm_mask_shldv_epi16 (__m128i, __mmask8, __m128i, __m128i);
VPSHLDVW __m128i  _mm_maskz_shldv_epi16(__mmask8, __m128i, __m128i, __m128i);VPSHLDVW __m256i  _mm256_shldv_epi16(__m256i, __m256i, __m256i);VPSHLDVW __m256i  _mm256_mask_shldv_epi16(__m256i, __mmask16, __m256i, __m256i);VPSHLDVW __m256i  _mm256_maskz_shldv_epi16(__mmask16, __m256i, __m256i, __m256i);VPSHLDVW __m512i  _mm512_shldv_epi16(__m512i, __m512i, __m512i);VPSHLDVW __m512i  _mm512_mask_shldv_epi16(__m512i, __mmask32, __m512i, __m512i);VPSHLDVW __m512i  _mm512_maskz_shldv_epi16(__mmask32, __m512i, __m512i, __m512i);VPSHLDVD __m128i  _mm_shldv_epi32(__m128i, __m128i, __m128i);VPSHLDVD __m128i  _mm_mask_shldv_epi32 (__m128i, __mmask8, __m128i, __m128i);
VPSHLDVD __m128i  _mm_maskz_shldv_ep i32(__mmask8, __m128i, __m128i, __m128i);
VPSHLDVD __m256i  _mm256_shldv _epi32(__m256i, __m256i, __m256i);
VPSHLDVD __m256i  _mm256_mask_shldv_epi32(__m256i, __mmask8, __m256i, __m256i);VPSHLDVD __m256i  _mm256_maskz_shldv_epi 32(__mmask8, __m256i, __m256i, __m256i);
VPSHLDVD __m512i  _mm512_shldv _epi32(__m512i, __m512i, __m512i);
VPSHLDVD __m512i  _mm512_mask_shldv_epi32(__m512i, __mmask16, __m512i, __m512i);VPSHLDVD __m512i  _mm512_maskz_shldv_epi32(__mmask16, __m512i, __m512i, __m512i);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPSHRD—Concatenate and Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, V

None.
5-594 Vol. 2CVPSHRD—Concatenate and Shift Packed Data Right Logical 
Concatenate packed data, extract result shifted to the right by constant value.This instruction supports memory fault suppression.Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F3A.W1 72 /r /ib
VPSHRDW xmm1{k1}{z}, xmm2, 
extract result shifted to  the right by constant 
EVEX.256.66.0F3A.W1 72 /r /ib
VPSHRDW ymm1{k1}{z}, ymm2, ymm3/m256, imm8AV / VA V X 5 1 2 _ V B M I 2
EVEX.512.66.0F3A.W1 72 /r /ib
VPSHRDW zmm1{k1}{z}, zmm2, 
EVEX.128.66.0F3A.W0 73 /r /ib
VPSHRDD xmm1{k1}{z}, xmm2, 
EVEX.256.66.0F3A.W0 73 /r /ib
VPSHRDD ymm1{k1}{z}, ymm2, 
EVEX.512.66.0F3A.W0 73 /r /ib
VPSHRDD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst, imm8B V/V AVX512_VBMI2 Concatenate dest ination and source operands, 
EVEX.128.66.0F3A.W1 73 /r /ib
VPSHRDQ xmm1{k1}{z}, xmm2, 
EVEX.256.66.0F3A.W1 73 /r /ib
VPSHRDQ ymm1{k1}{z}, ymm2, 
EVEX.512.66.0F3A.W1 73 /r /ib
VPSHRDQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8B V/V AVX512_VBMI2 Concatenate dest ination and source operands, 
B Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8 (r)VPSHRD—Concatenate and Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-595Operation
VPSHRDW DEST, SRC2, SRC3, imm8
DEST.word[j] := concat(SRC3.word[j], SRC2.word[j]) >> (imm8 & 15)
VPSHRDD DEST, SRC2, SRC3, imm8
ELSE:
DEST.dword[j] := conc at(tsrc3, SRC2.dword[j ]) >> (imm8 & 31)
VPSHRDQ DEST, SRC2, SRC3, imm8
ELSE:
DEST.qword[j] := conc at(tsrc3, SRC2.qword[j ]) >> (imm8 & 63)
DEST[MAX_VL-1:VL] := 0VPSHRD—Concatenate and Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, V
5-596 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPSHRDQ __m128i  _mm_shrdi_ep i64(__m128i, __m128i, int);
VPSHRDQ __m128i  _mm_mask_s hrdi_epi64(__m128i,  __mmask8, __m128i, __m128i, int);
VPSHRDQ __m128i  _mm_maskz_shrdi_epi6 4(__mmask8, __m128i, __m128i, int);
VPSHRDQ __m256i  _mm256_shrdi_e pi64(__m256i, __m256i, int);
VPSHRDQ __m256i  _mm256_mask_shrdi_epi64( __m256i, __mmask8, __m256i, __m256i, int);
VPSHRDQ __m256i  _mm256_maskz_shrdi_epi 64(__mmask8, __m256i, __m256i, int);
VPSHRDQ __m512i  _mm512_shrdi_e pi64(__m512i, __m512i, int);
VPSHRDQ __m512i  _mm512_mask_shrdi_epi64( __m512i, __mmask8, __m512i, __m512i, int);
VPSHRDQ __m512i  _mm512_maskz_shrdi_epi 64(__mmask8, __m512i, __m512i, int);
VPSHRDD __m128i _mm_shrdi_epi32(__m128i, __m128i, int);VPSHRDD __m128i _mm_mask_shrdi_epi32(__m128 i, __mmask8, __m128i, __m128i, int);
VPSHRDD __m128i _mm_maskz_shrdi_epi3 2(__mmask8, __m128i, __m128i, int);
VPSHRDD __m256i _mm256_shrdi_epi32(__m256i, __m256i, int);VPSHRDD __m256i _mm256_mask_shrdi_epi32(__m256 i, __mmask8, __m256i, __m256i, int);
VPSHRDD __m256i _mm256_maskz_shrdi_epi32(__mmask8, __m256i, __m256i, int);VPSHRDD __m512i _mm512_shrdi_epi32(__m512i, __m512i, int);VPSHRDD __m512i _mm512_mask_shrdi_epi32(__m 512i, __mmask16, __m512i, __m512i, int);
VPSHRDD __m512i _mm512_maskz_shrdi_epi32(__mmask16, __m512i, __m512i, int);VPSHRDW __m128i _mm_shrdi_epi16(__m128i, __m128i, int);VPSHRDW __m128i _mm_mask_s hrdi_epi16(__m128i, __mmask 8, __m128i, __m128i, int);
VPSHRDW __m128i _mm_maskz_shrdi_epi16(__mmask8, __m128i, __m128i, int);VPSHRDW __m256i _mm256_shrdi_epi16(__m256i, __m256i, int);VPSHRDW __m256i _mm256_mask_shrdi_epi16(__m256i, __mmask16, __m256i, __m256i, int);VPSHRDW __m256i _mm256_maskz_shrdi_epi 16(__mmask16, __m256 i, __m256i, int);
VPSHRDW __m512i _mm512_shrdi_epi16(__m512i, __m512i, int);VPSHRDW __m512i _mm512_mask_shrdi_epi16(__m512i, __mmask32, __m512i, __m512i, int);VPSHRDW __m512i _mm512_maskz_shrdi_epi 16(__mmask32, __m512 i, __m512i, int);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPSHRDV—Concatenate and Variable Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-597VPSHRDV—Concatenate and Variable Shift Packed Data Right Logical
Concatenate packed data, extract result shifted to the right by variable value.This instruction supports memory fault suppression.Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F38.W1 72 /r
VPSHRDVW xmm1{k1}{z}, xmm2, 
shifted to the right by  value in xmm3/m128 
into xmm1.
EVEX.256.66.0F38.W1 72 /r
VPSHRDVW ymm1{k1}{z}, ymm2, ymm3/m256AV / VA V X 5 1 2 _ V B M I 2
shifted to the right by  value in xmm3/m256 
into ymm1.
EVEX.512.66.0F38.W1 72 /r
VPSHRDVW zmm1{k1}{z}, zmm2, 
shifted to the right by  value in zmm3/m512 
into zmm1.
EVEX.128.66.0F38.W0 73 /r
VPSHRDVD xmm1{k1}{z}, xmm2, 
into xmm1.
EVEX.256.66.0F38.W0 73 /r
VPSHRDVD ymm1{k1}{z}, ymm2, 
into ymm1.
EVEX.512.66.0F38.W0 73 /r
VPSHRDVD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcstB V/V AVX512_VBMI2 Concatenate zmm1 and zmm2, extract result 
into zmm1.
EVEX.128.66.0F38.W1 73 /r
VPSHRDVQ xmm1{k1}{z}, xmm2, 
into xmm1.
EVEX.256.66.0F38.W1 73 /r
VPSHRDVQ ymm1{k1}{z}, ymm2, 
into ymm1.
EVEX.512.66.0F38.W1 73 /r
VPSHRDVQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcstB V/V AVX512_VBMI2 Concatenate zmm1 and zmm2, extract result 
into zmm1.
B Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPSHRDV—Concatenate and Variable Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, V
5-598 Vol. 2COperation
VPSHRDVW DEST, SRC2, SRC3
DEST.word[j] := concat(SRC2.word[j],  DEST.word[j]) >> (SRC3.word[j] & 15)
VPSHRDVD DEST, SRC2, SRC3
ELSE:
DEST.dword[j] := concat(SRC2.dword[ j], DEST.dword[j]) >> (tsrc3 & 31)
VPSHRDVQ DEST, SRC2, SRC3
ELSE:

ELSE:
ELSE:
DEST.qword[j] := concat(SRC2.qword[ j], DEST.qword[j]) >> (tsrc3 & 63)
*ELSE DEST.qwo rd[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0VPSHRDV—Concatenate and Variable Shift Packed Data Right LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-599Intel C/C++ Compiler Intrinsic Equivalent
VPSHRDVQ __m128i  _mm_shrdv_ep i64(__m128i, __m128i, __m128i);
VPSHRDVQ __m128i  _mm_mask_shrdv_epi64( __m128i, __mmask8, __m128i, __m128i);
VPSHRDVQ __m128i  _mm_maskz_shrdv_epi6 4(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVQ __m256i  _mm256_shrdv_e pi64(__m256i, __m256i, __m256i);
VPSHRDVQ __m256i  _mm256_mask_shrdv_epi64(__m256i, __mmask8, __m256i, __m256i);VPSHRDVQ __m256i  _mm256_maskz_shrdv_epi64(__mmask8, __m256i, __m256i, __m256i);VPSHRDVQ __m512i  _mm512_shrdv_e pi64(__m512i, __m512i, __m512i);
VPSHRDVQ __m512i  _mm512_mask_shrdv_epi64(__m512i, __mmask8, __m512i, __m512i);VPSHRDVQ __m512i  _mm512_maskz_shrdv_epi64(__mmask8, __m512i, __m512i, __m512i);VPSHRDVD __m128i _mm_shrdv_epi32(__m128i, __m128i, __m128i);VPSHRDVD __m128i _mm_mask_shrdv_epi32(__m128i, __mmask8, __m128i, __m128i);VPSHRDVD __m128i _mm_maskz_shrdv_epi 32(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVD __m256i _mm256_shrdv_epi32(__m256i, __m256i, __m256i);VPSHRDVD __m256i _mm256_mask_shrdv_epi3 2(__m256i, __mmask8, __m256i, __m256i);
VPSHRDVD __m256i _mm256_maskz_shrdv_e pi32(__mmask8, __m256i, __m256i, __m256i);
VPSHRDVD __m512i _mm512_shrdv_epi32(__m512i, __m512i, __m512i);VPSHRDVD __m512i _mm512_mask_shrdv_epi32(__m512i, __mmask16, __m512i, __m512i);VPSHRDVD __m512i _mm512_maskz_shrdv_epi 32(__mmask16, __m512i, __m512i, __m512i);
VPSHRDVW __m128i _mm_shrdv_epi16(__m128i, __m128i, __m128i);VPSHRDVW __m128i _mm_mask_shrdv_epi16(__m128i, __mmask8, __m128i, __m128i);VPSHRDVW __m128i _mm_maskz_shrdv_epi16(__mmask8, __m128i, __m128i, __m128i);VPSHRDVW __m256i _mm256_shrdv_epi16(__m256i, __m256i, __m256i);VPSHRDVW __m256i _mm256_mask_shrdv_epi16( __m256i, __mmask16,  __m256i, __m256i);
VPSHRDVW __m256i _mm256_maskz_shrdv_epi16(__mmask16, __m256i, __m256i, __m256i);VPSHRDVW __m512i _mm512_shrdv_epi16(__m512i, __m512i, __m512i);VPSHRDVW __m512i _mm512_mask_shrdv_epi16( __m512i, __mmask32,  __m512i, __m512i);
VPSHRDVW __m512i _mm512_maskz_shrdv_epi16(__mmask32, __m512i, __m512i, __m512i);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPSHUFBITQMB—Shuffle Bits From Quadword  Elements Using Byte Indexes Into MaskINSTRUCTION SET REFERENCE, V
5-600 Vol. 2CVPSHUFBITQMB—Shuffle Bits From Quadword El ements Using Byte Indexes Into Mask 
The VPSHUFBITQMB instruction performs a bit gather select using second source as control and first source as 
data. Each bit uses 6 control bits (2nd source operand) to select which data bit is going to be gathered (first source 
operand). A given bit can only access 64 different bits of data (first 64 destination bits can access first 64 data bits, 
second 64 destination bits can access second 64 data bits, etc.).
Control data for each output bit is stored in 8 bit elemen ts of SRC2, but only the 6 least significant bits of each 
element are used.
This instruction uses write masking (zeroing only). This instruction supports memory fault suppression.
The first source operand is a ZMM register. The second source operand is a ZMM register or a memory location. The 
destination operand is a mask register.
Operation
VPSHUFBITQMB DEST, SRC1, SRC2
(KL, VL) = (16,128), (32,256), (64, 512)FOR i := 0 TO KL/8-1: //Qword
FOR j := 0 to 7: // Byte
IF k2[i*8+j] or *no writemask*:
m := SRC2.qword[i ].byte[j] & 0x3F
k1[i*8+j] := SRC1 .qword[i].bit[m]
ELSE:
k1[i*8+j] := 0
k1[MAX_KL-1:KL] := 0
VPSHUFBITQMB __mmask16 _mm_bitshu ffle_epi64_mask(__m128i, __m128i);
VPSHUFBITQMB __mmask16 _mm_mask_bitshuffle_ epi64_mask(__mmask16, __m128i, __m128i);
VPSHUFBITQMB __mmask32 _mm256_bitsh uffle_epi64_mask(__m256i, __m256i);
VPSHUFBITQMB __mmask32 _mm256_mask_bitshuffle_epi64_mask(__mmask32, __m256i, __m256i);VPSHUFBITQMB __mmask64 _mm512_bitsh uffle_epi64_mask(__m512i, __m512i);
VPSHUFBITQMB __mmask64 _mm512_mask_bitshuffl e_epi64_mask(__mmask64, __m512i, __m512i);Opcode/
En64/32 
bit Mode 
EVEX.128.66.0F38.W0 8F /r
VPSHUFBITQMB k1{k2}, xmm2, 
xmm3/m128A V/V AVX512_BITALG
AVX512VLExtract values in xmm2 using control bits of 
xmm3/m128 with writemask k2 and leave the 
result in mask register k1.
EVEX.256.66.0F38.W0 8F /r
VPSHUFBITQMB k1{k2}, ymm2, ymm3/m256A V/V AVX512_BITALG
AVX512VLExtract values in ymm2 using control bits of 
ymm3/m256 with writemask k2 and leave the result in mask register k1.
EVEX.512.66.0F38.W0 8F /r
VPSHUFBITQMB k1{k2}, zmm2, 
zmm3/m512A V/V AVX512_BITALG Extract values in zmm2 using control bits of 
zmm3/m512 with writemask k2 and leave the 
A Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-601VPSLLVW/VPSLLVD/VPSLLVQ—Varia ble Bit Shift Left Logical 
En64/32 
bit Mode 
Feature 
VEX.128.66.0F38.W0 47 /r
VPSLLVD xmm1, xmm2, xmm3/m128A V/V AVX2 Shift doublewords in xmm2 left by amount specified in 
the corresponding element of xmm3/m128 while 
VEX.128.66.0F38.W1 47 /r
VPSLLVQ xmm1, xmm2, xmm3/m128A V/V AVX2 Shift quadwords in xmm2 left by amount specified in 
the corresponding element of xmm3/m128 while shifting in 0s.
VEX.256.66.0F38.W0 47 /r
VPSLLVD ymm1, ymm2, ymm3/m256A V/V AVX2 Shift doublewords in ymm2 left by amount specified in 
the corresponding element of ymm3/m256 while 
VEX.256.66.0F38.W1 47 /r
VPSLLVQ ymm1, ymm2, ymm3/m256A V/V AVX2 Shift quadwords in ymm2 left by amount specified in 
EVEX.128.66.0F38.W1 12 /r
VPSLLVW xmm1 {k1}{z}, xmm2, 
xmm3/m128B V/V AVX512VL
AVX512BWShift words in xmm2 left by amount specified in the 
corresponding element of xmm3/m128 while shifting 
in 0s using writemask k1.
EVEX.256.66.0F38.W1 12 /r
VPSLLVW ymm1 {k1}{z}, ymm2, ymm3/m256B V/V AVX512VL
AVX512BWShift words in ymm2 left by amount specified in the 
corresponding element of ymm3/m256 while shifting in 0s using writemask k1.
EVEX.512.66.0F38.W1 12 /r
VPSLLVW zmm1 {k1}{z}, zmm2, 
zmm3/m512B V/V AVX512BW Shift words in zmm2 left by amount specified in the 
corresponding element of zmm3/m512 while shifting 
EVEX.128.66.0F38.W0 47 /r
VPSLLVD xmm1 {k1}{z}, xmm2, 
AVX512FShift doublewords in xmm2 left by amount specified in 
the corresponding element of xmm3/m128/m32bcst 
EVEX.256.66.0F38.W0 47 /r
VPSLLVD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstC V/V AVX512VL
AVX512FShift doublewords in ymm2 left by amount specified in 
the corresponding element of ymm3/m256/m32bcst while shifting in 0s using writemask k1.
EVEX.512.66.0F38.W0 47 /r
VPSLLVD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512F Shift doublewords in zmm2 left by amount specified in 
the corresponding element of zmm3/m512/m32bcst 
EVEX.128.66.0F38.W1 47 /r
VPSLLVQ xmm1 {k1}{z}, xmm2, 
AVX512FShift quadwords in xmm2 left by amount specified in 
the corresponding element of xmm3/m128/m64bcst 
EVEX.256.66.0F38.W1 47 /r
VPSLLVQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstC V/V AVX512VL
AVX512FShift quadwords in ymm2 left by amount specified in 
the corresponding element of ymm3/m256/m64bcst while shifting in 0s using writemask k1.
EVEX.512.66.0F38.W1 47 /r
VPSLLVQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Shift quadwords in zmm2 left by amount specified in 
the corresponding element of zmm3/m512/m64bcst 
B Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left LogicalINSTRUCTION SET REFERENCE, V
5-602 Vol. 2CDescription
Shifts the bits in the individual data elements (words, do ublewords or quadword) in the first source operand to the 
left by the count value of respective data elements in the second source operand. As the bits in the data elements 
are shifted left, the empty low-order bits are cleared (set to 0). 
The count values are specified individually in each data  element of the second source operand. If the unsigned 
integer value specified in the respective data element of th e second source operand is greater than 15 (for word), 
31 (for doublewords), or 63 (for a quadword), then  the destination data element are written with 0.

31 (for doublewords), or 63 (for a quadword), then  the destination data element are written with 0. 
VEX.128 encoded version: The destination and first source  operands are XMM registers. The count operand can be 
either an XMM register or a 128-bit memory location. Bits  (MAXVL-1:128) of the corresponding destination register 
VEX.256 encoded version: The destination and first source  operands are YMM registers. The count operand can be 
either an YMM register or a 256-bit memory. Bits (MAX VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded VPSLLVD/Q: The destination and first so urce operands are ZMM/YMM/XMM registers. The count 
operand can be either a ZMM/YMM/XMM register, a 512/256 /128-bit memory location or a 512-bit vector broad-
casted from a 32/64-bit memory location. The destin ation is conditionally updated with writemask k1.
EVEX encoded VPSLLVW: The destination and first sour ce operands are ZMM/YMM/XMM registers. The count 
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is condition-
ally updated with writemask k1.
Operation
VPSLLVW (EVEX encoded version) 
THEN DEST[i+15:i] := ZeroExtend(SRC1[i+15:i] << SRC2[i+15:i])ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0;VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-603VPSLLVD (VEX.128 version)
COUNT_0 := SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 := SRC2[127 : 96];IF COUNT_0 < 32 THENDEST[31:0] := ZeroExtend(SRC1[31:0] << COUNT_0);ELSEDEST[31:0] := 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THENDEST[127:96] := ZeroExtend(SRC1[127:96] << COUNT_3);ELSEDEST[127:96] := 0;DEST[MAXVL-1:128] := 0;
VPSLLVD (VEX.256 version)
COUNT_0 := SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 := SRC2[255 : 224];IF COUNT_0 < 32 THENDEST[31:0] := ZeroExtend(SRC1[31:0] << COUNT_0);ELSEDEST[31:0] := 0;
(* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THENDEST[255:224] := ZeroExtend(SRC1[255:224] << COUNT_7);ELSEDEST[255:224] := 0;DEST[MAXVL-1:256] := 0;
VPSLLVD (EVEX encoded version) 
THEN DEST[i+31:i] := ZeroExte nd(SRC1[i+31:i] << SRC2[31:0])
ELSE DEST[i+31:i] := ZeroExtend(SRC1[i+31:i] << SRC2[i+31:i])
FI;
ELSE 
FI
FI;
5-604 Vol. 2CVPSLLVQ (VEX.128 version)
COUNT_0 := SRC2[63 : 0];COUNT_1 := SRC2[127 : 64];IF COUNT_0 < 64THENDEST[63:0] := ZeroExtend(SRC1[63:0] << COUNT_0);ELSEDEST[63:0] := 0;IF COUNT_1 < 64 THENDEST[127:64] := ZeroExtend (SRC1[127:64] << COUNT_1);
ELSEDEST[127:96] := 0;DEST[MAXVL-1:128] := 0;
VPSLLVQ (VEX.256 version)
COUNT_0 := SRC2[63 : 0];
COUNT_3 := SRC2[255 : 192];IF COUNT_0 < 64THENDEST[63:0] := ZeroExtend(SRC1[63:0] << COUNT_0);ELSEDEST[63:0] := 0;
IF COUNT_3 < 64 THENDEST[255:192] := ZeroExtend(SRC1[255:192] << COUNT_3);ELSEDEST[255:192] := 0;DEST[MAXVL-1:256] := 0;
VPSLLVQ (EVEX encoded version) 
THEN DEST[i+63:i] := ZeroExte nd(SRC1[i+63:i] << SRC2[63:0])
ELSE DEST[i+63:i] := ZeroExte nd(SRC1[i+63:i] << SRC2[i+63:i])
FI;
ELSE 
FI
FI;
Vol. 2C 5-605Intel C/C++ Compiler Intrinsic Equivalent
VPSLLVW __m512i _mm512_sllv_epi16(__m512i a, __m512i cnt);
VPSLLVW __m512i _mm512_mask_sllv_epi16(__m512 i s, __mmask32 k, __ m512i a, __m512i cnt);
VPSLLVW __m512i _mm512_maskz_sllv_epi16(  __mmask32 k, __m512i a, __m512i cnt);
VPSLLVW __m256i _mm256_mask_sllv_epi16(__m256 i s, __mmask16 k, __ m256i a, __m256i cnt);
VPSLLVW __m256i _mm256_maskz_sllv_epi16(  __mmask16 k, __m256i a, __m256i cnt);
VPSLLVW __m128i _mm_mask_sllv_epi16(__m128i  s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVW __m128i _mm_maskz_sllv_epi16( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m512i _mm512_sllv_e pi32(__m512i a, __m512i cnt);
VPSLLVD __m512i _mm512_mask_sllv_epi32(__m512 i s, __mmask16 k, __m512i a, __m512i cnt);
VPSLLVD __m512i _mm512_maskz_sllv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPSLLVD __m256i _mm256_mask_sllv_epi32(__m256i s, __mmask8 k, __m2 56i a, __m256i cnt);
VPSLLVD __m256i _mm256_maskz_sllv_epi32( __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m128i _mm_mask_sllv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m128i _mm_maskz_sllv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVQ __m512i _mm512_sllv_epi64(__m512i a, __m512i cnt);VPSLLVQ __m512i _mm512_mask_sllv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);VPSLLVQ __m512i _mm512_maskz_sllv_epi64( __mmask8 k, __m512i a, __m512i cnt);VPSLLVD __m256i _mm256_mask_sllv_epi64(__m256i s, __mmask8 k, __m2 56i a, __m256i cnt);
VPSLLVD __m256i _mm256_maskz_sllv_epi64( __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m128i _mm_mask_sllv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m128i _mm_maskz_sllv_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m256i _mm256_sllv_epi 32 (__m256i m, __m256i count)
VPSLLVQ __m256i _mm256_sllv_epi64 (__m256i m, __m256i count)
None.
VEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded VPSLLVD/VPSLLVQ, see Table 2-49, “Type E4 Class Exception Conditions.”EVEX-encoded VPSLLVW, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right ArithmeticINSTRUCTION SET REFERENCE, V
5-606 Vol. 2CVPSRAVW/VPSRAVD/VPSRAVQ—Variable  Bit Shift Right Arithmetic 
En64/32 
bit Mode 
Feature 
VEX.128.66.0F38.W0 46 /r
VPSRAVD xmm1, xmm2, xmm3/m128A V/V AVX2 Shift doublewords in xmm2 right by amount specified 
in the corresponding element of xmm3/m128 while 
VEX.256.66.0F38.W0 46 /r
VPSRAVD ymm1, ymm2, ymm3/m256A V/V AVX2 Shift doublewords in ymm2 right by amount specified 
in the corresponding element of ymm3/m256 while shifting in sign bits.
EVEX.128.66.0F38.W1 11 /r
VPSRAVW xmm1 {k1}{z}, xmm2, 
xmm3/m128BV / V A V X 5 1 2 V L
AVX512BWShift words in xmm2 right by amount specified in the 
in sign bits using writemask k1.
EVEX.256.66.0F38.W1 11 /r
VPSRAVW ymm1 {k1}{z}, ymm2, 
ymm3/m256BV / V A V X 5 1 2 V L
AVX512BWShift words in ymm2 right by amount specified in the 
corresponding element of ymm3/m256 while shifting 
EVEX.512.66.0F38.W1 11 /r
VPSRAVW zmm1 {k1}{z}, zmm2, 
zmm3/m512B V/V AVX512BW Shift words in zmm2 right by amount specified in the 
EVEX.128.66.0F38.W0 46 /r
VPSRAVD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV / V A V X 5 1 2 V L
AVX512FShift doublewords in xmm2 right by amount specified 
in the corresponding element of xmm3/m128/m32bcst while shifting in sign bits 
EVEX.256.66.0F38.W0 46 /r
VPSRAVD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV / V A V X 5 1 2 V L
AVX512FShift doublewords in ymm2 right by amount specified 
in the corresponding element of ymm3/m256/m32bcst while shifting in sign bits 
EVEX.512.66.0F38.W0 46 /r
VPSRAVD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstC V/V AVX512F Shift doublewords in zmm2 right by amount specified 
in the corresponding element of zmm3/m512/m32bcst while shifting in sign bits using 
EVEX.128.66.0F38.W1 46 /r
VPSRAVQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV / V A V X 5 1 2 V L
AVX512FShift quadwords in xmm2 right by amount specified 
in the corresponding element of xmm3/m128/m64bcst while shifting in sign bits 
EVEX.256.66.0F38.W1 46 /r
VPSRAVQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV / V A V X 5 1 2 V L
AVX512FShift quadwords in ymm2 right by amount specified 
in the corresponding element of ymm3/m256/m64bcst while shifting in sign bits 
EVEX.512.66.0F38.W1 46 /r
VPSRAVQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcstC V/V AVX512F Shift quadwords in zmm2 right by amount specified in 
the corresponding element of zmm3/m512/m64bcst

while shifting in sign bits using writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right ArithmeticINSTRUCTION SET REFERENCE, V
Vol. 2C 5-607Description
Shifts the bits in the individual data elements (word/ doublewords/quadword) in the first source operand (the 
second operand) to the right by the number of bits specifie d in the count value of respective data elements in the 
second source operand (the third operand). As the bits in the data elements are shifted right, the empty high-order 
bits are set to the MSB (sign extension). 
integer value specified in the respective data element of th e second source operand is greater than 15 (for words), 
31 (for doublewords), or 63 (for a quadword), then the de stination data element is filled with the corresponding 
sign bit of the source element.
either an YMM register or a 256-bit memory. Bits (MAXVL -1:256) of the corresponding destination register are 
zeroed.
EVEX.512/256/128 encoded VPSRAVD/W: The destination an d first source operands are ZMM/YMM/XMM registers. 
The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 
512/256/128-bit vector broadcasted from a 32/64-bit memo ry location. The destination is conditionally updated 
EVEX.512/256/128 encoded VPSRAVQ: The destination and first source operands are ZMM/YMM/XMM registers. 
The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination 
Operation
VPSRAVW (EVEX encoded version) 
THEN 
COUNT := SRC2[i+3:i]IF COUNT < 16
THEN DEST[i+15:i] := Sign Extend(SRC1[i+15:i] >> COUNT)
ELSE 
FOR k := 0 TO 15 
DEST[i+k] := SRC1[i+15]
ENDFOR;
FI
ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0;VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right ArithmeticINSTRUCTION SET REFERENCE, V
5-608 Vol. 2CVPSRAVD (VEX.128 version)
COUNT_3 := SRC2[127 : 96];DEST[31:0] := SignExtend(SRC1[31:0] >> COUNT_0);
DEST[127:96] := SignExtend(SRC1[127:96] >> COUNT_3);DEST[MAXVL-1:128] := 0;
VPSRAVD (VEX.256 version)
(* Repeat Each COUNT_i for the 2nd through 8th dwords of SRC2*)
COUNT_7 := SRC2[255 : 224];DEST[31:0] := SignExtend(SRC1[31:0] >> COUNT_0);
DEST[255:224] := SignExtend(SRC1[255:224] >> COUNT_7);DEST[MAXVL-1:256] := 0;
VPSRAVD (EVEX encoded version) 
THEN 
COUNT := SRC2[4:0]IF COUNT < 32
THEN DEST[i+31:i] := Sign Extend(SRC1[i+31:i] >> COUNT)
ELSE 
FOR k := 0 TO 31 
DEST[i+k] := SRC1[i+31]
ENDFOR;
FI
ELSE 
COUNT := SRC2[i+4:i]IF COUNT < 32
ELSE 
ENDFOR;
FI
FI;
ELSE 
FI
FI;
Vol. 2C 5-609VPSRAVQ (EVEX encoded version) 
THEN 
COUNT := SRC2[5:0]IF COUNT < 64
THEN DEST[i+63:i] := Sign Extend(SRC1[i+63:i] >> COUNT)
ELSE 
FOR k := 0 TO 63 
DEST[i+k] := SRC1[i+63]
ENDFOR;
FI
ELSE 
COUNT := SRC2[i+5:i]IF COUNT < 64
ELSE 
ENDFOR;
FI
FI;
ELSE 
FI
FI;
5-610 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VPSRAVD __m512i _mm512_srav_ep i32(__m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_mask_sr av_epi32(__m512i s, __mmask16  m, __m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_maskz_srav_epi3 2(__mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m256i _mm256_srav_ep i32(__m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_mask_sr av_epi32(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_maskz_srav_epi3 2(__mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m128i _mm_srav_epi 32(__m128i a, __m128i cnt);
VPSRAVD __m128i _mm_mask_srav_epi32(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m128i _mm_maskz_ srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m512i _mm512_srav_epi64(__m512i a, __m512i cnt);VPSRAVQ __m512i _mm512_mask_srav_epi64(__m512i s, __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_maskz_srav_epi64( __mmask8 m, __m512i a, __m512i cnt);VPSRAVQ __m256i _mm256_srav_epi64(__m256i a, __m256i cnt);VPSRAVQ __m256i _mm256_mask_srav_epi64(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_maskz_srav_epi64( __mmask8 m, __m256i a, __m256i cnt);VPSRAVQ __m128i _mm_srav_epi64(__m128i a, __m128i cnt);VPSRAVQ __m128i _mm_mask_srav_epi64(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_maskz_sr av_epi64( __mmask8 m, __ m128i a, __m128i cnt);
VPSRAVW __m512i _mm512_srav_epi16(__m512i a, __m512i cnt);VPSRAVW __m512i _mm512_mask_srav_epi16(__m512i s, __mmask32 m, __m512i a, __m512i cnt);VPSRAVW __m512i _mm512_maskz_srav_epi16(__mmask32 m, __m512i a, __m512i cnt);VPSRAVW __m256i _mm256_srav_epi16(__m256i a, __m256i cnt);VPSRAVW __m256i _mm256_mask_srav_epi16(__m256i s, __mmask16 m, __m256i a, __m256i cnt);VPSRAVW __m256i _mm256_maskz_srav_epi16(__mmask16 m, __m256i a, __m256i cnt);VPSRAVW __m128i _mm_srav_epi16(__m128i a, __m128i cnt);VPSRAVW __m128i _mm_mask_srav_epi16(__m128i s, __mmask8 m, __m128i a, __m128i cnt);VPSRAVW __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);VPSRAVD __m256i _mm256_srav_ep i32 (__m256i m, __m256i count)
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-611VPSRLVW/VPSRLVD/VPSRLVQ—Varia ble Bit Shift Right Logical 
En64/32 
bit Mode 
Feature 
VEX.128.66.0F38.W0 45 /r
VPSRLVD xmm1, xmm2, xmm3/m128A V/V AVX2 Shift doublewords in xmm2 right by amount specified 
VEX.128.66.0F38.W1 45 /r
VPSRLVQ xmm1, xmm2, xmm3/m128A V/V AVX2 Shift quadwords in xmm2 right by amount specified in 
VEX.256.66.0F38.W0 45 /r
VPSRLVD ymm1, ymm2, ymm3/m256A V/V AVX2 Shift doublewords in ymm2 right by amount specified 
in the corresponding element of ymm3/m256 while 
VEX.256.66.0F38.W1 45 /r
VPSRLVQ ymm1, ymm2, ymm3/m256A V/V AVX2 Shift quadwords in ymm2 right by amount specified in 
EVEX.128.66.0F38.W1 10 /r
VPSRLVW xmm1 {k1}{z}, xmm2, 
EVEX.256.66.0F38.W1 10 /r
VPSRLVW ymm1 {k1}{z}, ymm2, ymm3/m256BV / V A V X 5 1 2 V L
EVEX.512.66.0F38.W1 10 /r
VPSRLVW zmm1 {k1}{z}, zmm2, 
EVEX.128.66.0F38.W0 45 /r
VPSRLVD xmm1 {k1}{z}, xmm2, 
AVX512FShift doublewords in xmm2 right by amount specified

in the corresponding element of xmm3/m128/m32bcst 
EVEX.256.66.0F38.W0 45 /r
VPSRLVD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV / V A V X 5 1 2 V L
in the corresponding element of ymm3/m256/m32bcst while shifting in 0s using writemask k1.
EVEX.512.66.0F38.W0 45 /r
VPSRLVD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcstC V/V AVX512F Shift doublewords in zmm2 right by amount specified 
in the corresponding element of zmm3/m512/m32bcst 
EVEX.128.66.0F38.W1 45 /r
VPSRLVQ xmm1 {k1}{z}, xmm2, 
AVX512FShift quadwords in xmm2 right by amount specified in 
EVEX.256.66.0F38.W1 45 /r
VPSRLVQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV / V A V X 5 1 2 V L
AVX512FShift quadwords in ymm2 right by amount specified in 
EVEX.512.66.0F38.W1 45 /r
VPSRLVQ zmm1 {k1}{z}, zmm2, 
A N/A ModRM:reg (w) VEX.vv vv (r) ModRM:r/m (r) N/A
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right LogicalINSTRUCTION SET REFERENCE, V
5-612 Vol. 2CDescription
right by the count value of respective data elements in the second source operand. As the bits in the data elements 
are shifted right, the empty high-order bits are cleared (set to 0). 
EVEX encoded VPSRLVD/Q: The destination and first so urce operands are ZMM/YMM/XMM registers. The count 
EVEX encoded VPSRLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count 
Operation
VPSRLVW (EVEX encoded version) 
THEN DEST[i+15:i] := ZeroExtend(SRC1[i+15:i] >> SRC2[i+15:i])ELSE 
FI
FI;
VPSRLVD (VEX.128 version)
COUNT_3 := SRC2[127 : 96];IF COUNT_0 < 32 THEN
DEST[31:0] := ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
DEST[31:0] := 0;(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] := ZeroExtend(SRC1[127:96] >> COUNT_3);
ELSE
DEST[127:96] := 0;
DEST[MAXVL-1:128] := 0;VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-613VPSRLVD (VEX.256 version)
COUNT_7 := SRC2[255 : 224];IF COUNT_0 < 32 THENDEST[31:0] := ZeroExtend(SRC1[31:0] >> COUNT_0);ELSEDEST[31:0] := 0;
IF COUNT_7 < 32 THEN
DEST[255:224] := ZeroExtend(SRC1[255:224] >> COUNT_7);
ELSE
DEST[255:224] := 0;
VPSRLVD (EVEX encoded version) 
THEN DEST[i+31:i] := ZeroExte nd(SRC1[i+31:i] >> SRC2[31:0])
ELSE DEST[i+31:i] := ZeroExtend(SRC1[i+31:i] >> SRC2[i+31:i])
FI;
ELSE 
FI
FI;
VPSRLVQ (VEX.128 version)
COUNT_0 := SRC2[63 : 0];COUNT_1 := SRC2[127 : 64];IF COUNT_0 < 64 THEN
DEST[63:0] := ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
DEST[63:0] := 0;
IF COUNT_1 < 64 THEN
DEST[127:64] := ZeroExtend(SRC1[127:64] >> COUNT_1);
ELSE
DEST[127:64] := 0;
5-614 Vol. 2CVPSRLVQ (VEX.256 version)
COUNT_3 := SRC2[255 : 192];IF COUNT_0 < 64 THENDEST[63:0] := ZeroExtend(SRC1[63:0] >> COUNT_0);ELSEDEST[63:0] := 0;
IF COUNT_3 < 64 THEN
DEST[255:192] := ZeroExtend(S RC1[255:192] >> COUNT_3);
ELSE
DEST[255:192] := 0;
VPSRLVQ (EVEX encoded version) 
THEN DEST[i+63:i] := ZeroExte nd(SRC1[i+63:i] >> SRC2[63:0])
ELSE DEST[i+63:i] := ZeroExte nd(SRC1[i+63:i] >> SRC2[i+63:i])
FI;
ELSE 
FI
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0;VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right LogicalINSTRUCTION SET REFERENCE, V
Vol. 2C 5-615Intel C/C++ Compiler Intrinsic Equivalent
VPSRLVW __m512i _mm512_srlv_epi16(__m512i a, __m512i cnt);
VPSRLVW __m512i _mm512_mask_srlv _epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);
VPSRLVW __m512i _mm512_maskz_srlv_epi16(  __mmask32 k, __m512i a, __m512i cnt);
VPSRLVW __m256i _mm256_mask_srlv _epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);
VPSRLVW __m256i _mm256_maskz_srlv_epi16(  __mmask16 k, __m256i a, __m256i cnt);
VPSRLVW __m128i _mm_mask_srlv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);VPSRLVW __m128i _mm_maskz_srlv_epi16( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVW __m256i _mm256_srlv_epi32 (__m256i m, __m256i count)VPSRLVD __m512i _mm512_srlv_epi32(__m512i a, __m512i cnt);VPSRLVD __m512i _mm512_mask_srlv_epi32(__m512 i s, __mmask16 k, __m512i a, __m512i cnt);
VPSRLVD __m512i _mm512_maskz_srlv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPSRLVD __m256i _mm256_mask_srlv_epi32(__m256 i s, __mmask8 k, __m2 56i a, __m256i cnt);
VPSRLVD __m256i _mm256_maskz_srlv_epi32( __mmask8 k, __m256i a, __m256i cnt);VPSRLVD __m128i _mm_mask_srlv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVD __m128i _mm_maskz_ srlv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m512i _mm512_srlv_epi64(__m512i a, __m512i cnt);VPSRLVQ __m512i _mm512_mask_srlv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);VPSRLVQ __m512i _mm512_maskz_srlv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPSRLVQ __m256i _mm256_mask_srlv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);VPSRLVQ __m256i _mm256_maskz_srlv_epi64( __mmask8 k, __m256i a, __m256i cnt);
VPSRLVQ __m128i _mm_mask_srlv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);VPSRLVQ __m128i _mm_maskz_srlv_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m256i _mm256_srlv_epi64 (__m256i m, __m256i count)VPSRLVD __m128i _mm_srlv_epi32( __m128i a, __m128i cnt);VPSRLVQ __m128i _mm_srlv_epi64(  __m128i a, __m128i cnt);
None.
VEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”EVEX-encoded VPSRLVD/Q, see Table 2-49,  “Type E4 Class Exception Conditions.”
EVEX-encoded VPSRLVW, see Exceptions Type E4.nb in  Table 2-49, “Type E4 Class Exception Conditions.”VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary LogicINSTRUCTION SET REFERENCE, V
5-616 Vol. 2CVPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
VPTERNLOGD/Q takes three bit vectors of 512-bit length (in the first, second, and third operand) as input data to

None.
VPTERNLOGD/Q takes three bit vectors of 512-bit length (in the first, second, and third operand) as input data to 
form a set of 512 indices, each index is comprised of on e bit from each input vector. The imm8 byte specifies a 
boolean logic table producing a binary value for each 3-bit index value. The final 512-bit boolean result is written 
to the destination operand (the first operand) using the writemask k1 with the granularity of doubleword element 
or quadword element into the destination.
The destination operand is a ZMM (EVE X.512)/YMM (EVEX.256)/XMM (EVEX.128) register. The first source operand 
is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcas ted from a 32/64-bit memory location The destination 
operand is a ZMM register conditionally updated with writemask k1.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W0 25 /r ib
VPTERNLOGD xmm1 {k1}{z}, xmm2, 
AVX512FBitwise ternary logic ta king xmm1, xmm2, and 
xmm3/m128/m32bcst as source operands and writing 
the result to xmm1 under writemask k1 with dword 
granularity. The immediate value determines the specific binary function being implemented.
EVEX.256.66.0F3A.W0 25 /r ib
VPTERNLOGD ymm1 {k1}{z}, ymm2, 
AVX512FBitwise ternary logic ta king ymm1, ymm2, and 
ymm3/m256/m32bcst as source operands and writing 
the result to ymm1 under writemask k1 with dword 
granularity. The immediate value determines the specific 
binary function being implemented.
EVEX.512.66.0F3A.W0 25 /r ib
VPTERNLOGD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst, imm8A V/V AVX512F Bitwise ternary logic taking zmm1, zmm2, and 
zmm3/m512/m32bcst as source operands and writing 
the result to zmm1 under writemask k1 with dword 
EVEX.128.66.0F3A.W1 25 /r ib
VPTERNLOGQ xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcst as source operands and writing 
the result to xmm1 under writemask k1 with qword 
binary function being implemented. 
EVEX.256.66.0F3A.W1 25 /r ib
VPTERNLOGQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst, imm8A V/V AVX512VL
ymm3/m256/m64bcst as source operands and writing the result to ymm1 under writemask k1 with qword 
EVEX.512.66.0F3A.W1 25 /r ib
VPTERNLOGQ zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst, imm8A V/V AVX512F Bitwise ternary logic taking zmm1, zmm2, and 
zmm3/m512/m64bcst as source operands and writing 
the result to zmm1 under writemask k1 with qword 
granularity. The immediate value determines the specific binary function being implemented. 
A Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) imm8VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary LogicINSTRUCTION SET REFERENCE, V
Vol. 2C 5-617Table 5-22 shows two examples of Boolean functions specif ied by immediate values 0xE2  and 0xE4, with the look 
up result listed in the fourth column following the three columns containing all possible values of the 3-bit index.
Specifying different values in imm8 will allow any arbitr ary three-input Boolean functi ons to be implemented in 
software using VPTERNLOGD/Q. Table 5-11 and Table 5-12 provide a mapping of all 256  possible imm8 values to 
various Boolean expressions.
Operation
VPTERNLOGD (EVEX encoded versions) 
THEN 
THEN DEST[j][k] := imm[(DEST[i+k] << 2)  + (SRC1[ i+k ] << 1) + SRC2[ k ]]
ELSE DEST[j][k] := imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]
FI;
; table lookup of immediate bellow;
ELSE 
THEN *DEST[31+i:i] remains unchanged*ELSE ; zeroing-masking
DEST[31+i:i] := 0
FI;
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0Table 5-22. Examples of VPTERNLOGD/Q Imm8  Boolean Function and Input Index Values
VPTERNLOGD reg1, reg2, src3, 0xE2 Bit Result with 
Imm8=0xE2VPTERNLOGD reg1, reg2, src3, 0xE4 Bit Result with 
Imm8=0xE4Bit(reg1) Bit(reg2) Bit(src3) B it(reg1) Bit(reg2) Bit(src3)
0000 0000
0011 00100100 0101
0110 0110
1000 10001011 1011
1101 1101
1111 1111VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary LogicINSTRUCTION SET REFERENCE, V
5-618 Vol. 2CVPTERNLOGQ (EVEX encoded versions) 
THEN 
FI; ; table lookup of immediate bellow;
ELSE 
THEN *DEST[63+i:i] remains unchanged*ELSE ; zeroing-masking
DEST[63+i:i] := 0
FI;
FI;
VPTERNLOGD __m512i _mm512_ternarylogic_ epi32(__m512i a, __m512i b, int imm);
VPTERNLOGD __m512i _mm512_mask_tern arylogic_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b, int imm);
VPTERNLOGD __m512i _mm512_maskz_ternarylogic_epi32(__mmask m, __m512i a, __m512i b, int imm);VPTERNLOGD __m256i _mm256_ternarylogic_ epi32(__m256i a, __m256i b, int imm);
VPTERNLOGD __m256i _mm256_mask_tern arylogic_epi32(__m256i s, __mmask8 m,  __m256i a, __m256i b, int imm);
VPTERNLOGD __m256i _mm256_maskz_ternarylogic_epi32( __mmask8 m, __m256i a, __m256i b, int imm);VPTERNLOGD __m128i _mm_ternarylogic_epi 32(__m128i a, __m128i b, int imm);
VPTERNLOGD __m128i _mm_mask_ternarylogic_epi32(__m12 8i s, __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGD __m128i _mm_maskz_ternarylogic_epi32 ( __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGQ __m512i _mm512_ternarylogic_ epi64(__m512i a, __m512i b, int imm);
VPTERNLOGQ __m512i _mm512_mask_tern arylogic_epi64(__m512i s, __mmask8 m,  __m512i a, __m512i b, int imm);
VPTERNLOGQ __m512i _mm512_maskz_t ernarylogic_epi64( __m mask8 m, __m512i a, __m512i b, int imm);
VPTERNLOGQ __m256i _mm256_ternarylogic_ epi64(__m256i a, __m256i b, int imm);
VPTERNLOGQ __m256i _mm256_mask_tern arylogic_epi64(__m256i s, __mmask8 m,  __m256i a, __m256i b, int imm);
VPTERNLOGQ __m256i _mm256_maskz_t ernarylogic_epi64( __m mask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGQ __m128i _mm_ternarylogic_epi 64(__m128i a, __m128i b, int imm);
VPTERNLOGQ __m128i _mm_mask _ternarylogic_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGQ __m128i _mm_maskz_te rnarylogic_epi64( __mmask8 m, __m128i a, __m128i b, int imm);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-619VPTESTMB/VPTESTMW/VPTESTMD/VPTES TMQ—Logical AND and Set Mask
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 26 /r 
VPTESTMB k2 {k1}, xmm2, 
xmm3/m128 A V/V AVX512VL
AVX512BWBitwise AND of packed byte  integers in xmm2 and 
xmm3/m128 and set mask k2 to reflect the zero/non-zero 
status of each element of the result, under writemask k1. 
EVEX.256.66.0F38.W0 26 /r 
VPTESTMB k2 {k1}, ymm2, ymm3/m256A V/V AVX512VL
AVX512BWBitwise AND of packed byte  integers in ymm2 and 
ymm3/m256 and set mask k2 to  reflect the zero/non-zero 
EVEX.512.66.0F38.W0 26 /r 
VPTESTMB k2 {k1}, zmm2, 
zmm3/m512A V/V AVX512BW Bitwise AND of packed  byte integers in zmm2 and 
zmm3/m512 and set mask k2 to  reflect the zero/non-zero 
EVEX.128.66.0F38.W1 26 /r 
VPTESTMW k2 {k1}, xmm2, 
AVX512BWBitwise AND of packed word  integers in xmm2 and 
EVEX.256.66.0F38.W1 26 /r 
VPTESTMW k2 {k1}, ymm2, 
ymm3/m256A V/V AVX512VL
AVX512BWBitwise AND of packed word  integers in ymm2 and 
EVEX.512.66.0F38.W1 26 /r 
VPTESTMW k2 {k1}, zmm2, zmm3/m512A V/V AVX512BW Bitwise AND of packed  word integers  in zmm2 and 
EVEX.128.66.0F38.W0 27 /r 
VPTESTMD k2 {k1}, xmm2, 
xmm3/m128/m32bcst B V/V AVX512VL
AVX512FBitwise AND of packed doubleword integers in xmm2 and 
xmm3/m128/m32bcst and set mask k2 to reflect the 
zero/non-zero status of each element of the result, under writemask k1. 
EVEX.256.66.0F38.W0 27 /r 
VPTESTMD k2 {k1}, ymm2, 
ymm3/m256/m32bcst B V/V AVX512VL

AVX512FBitwise AND of packed doubleword integers in ymm2 and 
ymm3/m256/m32bcst and set mask k2 to reflect the 
EVEX.512.66.0F38.W0 27 /r 
VPTESTMD k2 {k1}, zmm2, 
zmm3/m512/m32bcst B V/V AVX512F Bitwise AND of packed doubleword integers in zmm2 and 
zmm3/m512/m32bcst and set mask k2 to reflect the 
EVEX.128.66.0F38.W1 27 /r 
VPTESTMQ k2 {k1}, xmm2, 
xmm3/m128/m64bcst B V/V AVX512VL
AVX512FBitwise AND of packed quadwo rd integers in xmm2 and 
xmm3/m128/m64bcst and set mask k2 to reflect the 
EVEX.256.66.0F38.W1 27 /r 
VPTESTMQ k2 {k1}, ymm2, 
ymm3/m256/m64bcst B V/V AVX512VL
AVX512FBitwise AND of packed quadwo rd integers in ymm2 and 
ymm3/m256/m64bcst and set mask k2 to reflect the 
EVEX.512.66.0F38.W1 27 /r 
VPTESTMQ k2 {k1}, zmm2, 
zmm3/m512/m64bcst B V/V AVX512F Bitwise AND of packed quadword integers in zmm2 and 
zmm3/m512/m64bcst and set mask k2 to reflect the 
A Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
B Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set MaskINSTRUCTION SET REFERENCE, V
5-620 Vol. 2CDescription 
Performs a bitwise logical AND operation on the first source operand (the second operand) and second source 
operand (the third operand) and stores the result in th e destination operand (the first operand) under the write-
mask. Each bit of the result is set to 1 if the bitwise AN D of the corresponding elements of the first and second src 
operands is non-zero; otherwise it is set to 0.
VPTESTMD/VPTESTMQ: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a 
32/64-bit memory location. The destination operand is a mask register updated under the writemask.
VPTESTMB/VPTESTMW: The first source operand is a ZMM/YMM/XMM re gister. The second source operand can be a 
ZMM/YMM/XMM register or a 512/256/128-bit memory lo cation. The destination operand is a mask register 
updated under the writemask.
Operation
VPTESTMB (EVEX encoded versions) 
THEN DEST[j] := (SRC1[i+7:i] BITW ISE AND SRC2[i+7:i] != 0)? 1 : 0;
FI;
VPTESTMW (EVEX encoded versions) 
THEN DEST[j] := (SRC1[i+15:i] BITW ISE AND SRC2[i+15:i] != 0)? 1 : 0;
FI;
VPTESTMD (EVEX encoded versions) 
THEN 
THEN DEST[j] := (SRC1[ i+31:i] BITWISE AND SRC2[31:0] != 0)? 1 : 0;
ELSE DEST[j] := (SRC1[i+31:i] BITW ISE AND SRC2[i+31:i] != 0)? 1 : 0;
FI;
FI;
ENDFORDEST[MAX_KL-1:KL] := 0VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set MaskINSTRUCTION SET REFERENCE, V
Vol. 2C 5-621VPTESTMQ (EVEX encoded versions) 
THEN 
THEN DEST[j] := (SRC1[i+63:i] BITW ISE AND SRC2[63:0] != 0)? 1 : 0;
ELSE DEST[j] := (SRC1[i+63:i] BITW ISE AND SRC2[i+63:i] != 0)? 1 : 0;
FI;
FI;
VPTESTMB __mmask64 _mm512_test_epi8_mask( __m512i a, __m512i b);
VPTESTMB __mmask64 _mm512_mask_test_epi 8_mask(__mmask64, __m512i a, __m512i b);
VPTESTMW __mmask32 _mm512_test_epi16_mask( __m512i a, __m512i b);VPTESTMW __mmask32 _mm512_mask_test_epi16 _mask(__mmask32, __m512i a, __m512i b);
VPTESTMD __mmask16 _mm512_test_epi 32_mask( __m512i a, __m512i b);
VPTESTMD __mmask16 _mm512_mask_test_epi32_mask(__mmask16, __m512i a, __m512i b);VPTESTMQ __mmask8 _mm512_test_epi64_mask(__m512i a, __m512i b);VPTESTMQ __mmask8 _mm512_mask_test_epi64_mask(__mmask8, __m512i a, __m512i b);
None.
VPTESTMD/Q: See Table 2-49, “Type E4 Class Exception Conditions.”
VPTESTMB/W: See Exceptions Type E4.nb in Tabl e 2-49, “Type E4 Class Exception Conditions.”VPTESTNMB/W/D/Q—Logical NAND and SetINSTRUCTION SET REFERENCE, V
5-622 Vol. 2CVPTESTNMB/W/D/Q—Logical NAND and Set
Opcode/
En64/32 
bit Mode 
EVEX.128.F3.0F38.W0 26 /r
VPTESTNMB k2 {k1 }, xmm2, 
xmm3/m128AV / V  A V X 5 1 2 V L
AVX512BWBitwise NAND of packed by te integers in xmm2 and 
xmm3/m128 and set mask k2 to  reflect the zero/non-zero 
status of each element of the result, under writemask k1.
EVEX.256.F3.0F38.W0 26 /r
VPTESTNMB k2 {k1 }, ymm2, 
ymm3/m256AV / V  A V X 5 1 2 V L
AVX512BWBitwise NAND of packed by te integers in ymm2 and 
EVEX.512.F3.0F38.W0 26 /r
VPTESTNMB k2 {k1 }, zmm2, 
zmm3/m512AV / V  A V X 5 1 2 F
AVX512BWBitwise NAND of packed by te integers in zmm2 and 
zmm3/m512 and set mask k2 to reflect the zero/non-zero 
EVEX.128.F3.0F38.W1 26 /r
VPTESTNMW k2 {k1 }, xmm2, 
AVX512BWBitwise NAND of packed wo rd integers in xmm2 and 
EVEX.256.F3.0F38.W1 26 /r
VPTESTNMW k2 {k1 }, ymm2, 
AVX512BWBitwise NAND of packed wo rd integers in ymm2 and 
EVEX.512.F3.0F38.W1 26 /r
VPTESTNMW k2 {k1 }, zmm2, 
AVX512BWBitwise NAND of packed wo rd integers in zmm2 and 
EVEX.128.F3.0F38.W0 27 /r
VPTESTNMD k2 {k1}, xmm2, 
xmm3/m128/m32bcstBV / V  A V X 5 1 2 V L
AVX512FBitwise NAND of packed doubleword integers in xmm2 and 
zero/non-zero status of each element of the result, under writemask k1.
EVEX.256.F3.0F38.W0 27 /r
VPTESTNMD k2 {k1}, ymm2, 
ymm3/m256/m32bcstBV / V  A V X 5 1 2 V L
AVX512FBitwise NAND of packed doubleword integers in ymm2 and 
EVEX.512.F3.0F38.W0 27 /r
VPTESTNMD k2 {k1}, zmm2, 
zmm3/m512/m32bcstB V/V AVX512F Bitwise NAND of packed doubleword integers in zmm2 and 
zero/non-zero status of each element of the result, under 
EVEX.128.F3.0F38.W1 27 /r
VPTESTNMQ k2 {k1}, xmm2, 
xmm3/m128/m64bcstBV / V  A V X 5 1 2 V L
AVX512FBitwise NAND of packed quad word integers in xmm2 and 
EVEX.256.F3.0F38.W1 27 /r
VPTESTNMQ k2 {k1}, ymm2, 
ymm3/m256/m64bcstBV / V  A V X 5 1 2 V L
AVX512FBitwise NAND of packed quad word integers in ymm2 and 
EVEX.512.F3.0F38.W1 27 /r
VPTESTNMQ k2 {k1}, zmm2, 
zmm3/m512/m64bcstBV / V  A V X 5 1 2 F B i t w i s e  N A N D  of packed quadword integers in zmm2 and 
zero/non-zero status of each element of the result, under writemask k1.VPTESTNMB/W/D/Q—Logical NAND and SetINSTRUCTION SET REFERENCE, V
Vol. 2C 5-623Instruction Operand Encoding
Performs a bitwise logical NAND operation on the byte /word/doubleword/quadword element of the first source 
operand (the second operand) with the corresponding elem ent of the second source operand (the third operand) 
and stores the logical comparison result into each bit of the destination operand (the first operand) according to the 
writemask k1. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and 
second src operands is zero; otherwise it is set to 0.
EVEX encoded VPTESTNMD/Q: The first source operand is a ZMM/YMM/XMM registers. The second source operand 
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted

can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted 
from a 32/64-bit memory location. The destin ation is updated according to the writemask.
EVEX encoded VPTESTNMB/W: The first source operand is  a ZMM/YMM/XMM registers. The second source operand 
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the 
Operation
VPTESTNMB
i := j*8IF MaskBit(j) OR *no writemask*
THEN 
   DEST[j] := (SRC1[i+7:i] BI TWISE AND SRC2[i+7:i] == 0)? 1 : 0
ELSE DEST[j] := 0; zeroing masking only
FI
VPTESTNMW
i := j*16IF MaskBit(j) OR *no writemask*
THEN 
   DEST[j] := (SRC1[i+15:i] BITW ISE AND SRC2[i+15:i] == 0)? 1 : 0
FI
VPTESTNMD
THEN 
   THEN DEST[i+31:i] := (SRC1[i+31:i] BITWISE AND SRC2[31:0] == 0)? 1 : 0
ELSE DEST[j] := (SRC1[i+31:i] BITW ISE AND SRC2[i+31:i] == 0)? 1 : 0
A Full Mem ModRM:reg (w) EVE X.vvvv (r) ModRM:r/m (r) N/A
B Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVPTESTNMB/W/D/Q—Logical NAND and SetINSTRUCTION SET REFERENCE, V
5-624 Vol. 2CELSE DEST[j] := 0; zeroing masking only
FI
VPTESTNMQ
THEN 
THEN DEST[j] := (SRC1[i+63:i] BI TWISE AND SRC2[63:0] == 0)? 1 : 0;
ELSE DEST[j] := (SRC1[i+63:i] BITW ISE AND SRC2[i+63:i] == 0)? 1 : 0;
FI;
FI
VPTESTNMB __mmask64 _mm512_testn_epi8_mask( __m512i a, __m512i b);
VPTESTNMB __mmask64 _mm512_mask_testn_epi8_mask(__mmask64, __m512i a, __m512i b);VPTESTNMB __mmask32 _mm256_testn_e pi8_mask(__m256i a, __m256i b);
VPTESTNMB __mmask32 _mm256_mask_testn_epi8_mask(__mmask32, __m256i a, __m256i b);VPTESTNMB __mmask16 _mm_testn_epi8_mask(__m128i a, __m128i b);VPTESTNMB __mmask16 _mm_mask_testn_epi8_mask(__mmask16, __m128i a, __m128i b);VPTESTNMW __mmask32 _mm512_testn_epi16_mask( __m512i a, __m512i b);VPTESTNMW __mmask32 _mm512_mask_testn_epi16_mask(__mmask32, __m512i a, __m512i b);VPTESTNMW __mmask16 _mm256_testn_epi16_mask(__m256i a, __m256i b);VPTESTNMW __mmask16 _mm256_mask_testn_epi16_mask(__mmask16, __m256i a, __m256i b);VPTESTNMW __mmask8 _mm_testn_epi16_mask(__m128i a, __m128i b);VPTESTNMW __mmask8 _mm_mask _testn_epi16_mask(__mmask8, __m128i a, __m128i b);
VPTESTNMD __mmask16 _mm512_testn_epi32_mask( __m512i a, __m512i b);VPTESTNMD __mmask16 _mm512_mask_testn_epi 32_mask(__mmask16, __m512i a, __m512i b);
VPTESTNMD __mmask8 _mm256_testn_epi32_mask(__m256i a, __m256i b);VPTESTNMD __mmask8 _mm256_mask_testn_epi32_mask(__mmask8, __m256i a, __m256i b);VPTESTNMD __mmask8 _mm_testn_epi32_mask(__m128i a, __m128i b);VPTESTNMD __mmask8 _mm_mask_testn_epi32_mask(__mmask8, __m128i a, __m128i b);VPTESTNMQ __mmask8 _mm512_testn_epi 64_mask(__m512i a, __m512i b);
VPTESTNMQ __mmask8 _mm512_mask_testn_epi64_ mask(__mmask8, __m512i a, __m512i b);
VPTESTNMQ __mmask8 _mm256_testn_epi 64_mask(__m256i a, __m256i b);
VPTESTNMQ __mmask8 _mm256_mask_testn_epi64_ mask(__mmask8, __m256i a, __m256i b);
VPTESTNMQ __mmask8 _mm_testn_epi6 4_mask(__m128i a, __m128i b);
VPTESTNMQ __mmask8 _mm_mask _testn_epi64_mask( __mmask8, __m128i a, __m128i b);
None.
VPTESTNMD/VPTESTNMQ: See Table 2-49, “Type E4 Class Exception Conditions.”
VPTESTNMB/VPTESTNMW: See Exceptions Type E4.nb in Table 2-49,  “Type E4 Class Exception Conditions.”VRANGEPD—Range Restriction Calculatio n for Packed Pairs of Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-625VRANGEPD—Range Restriction Calculatio n for Packed Pairs of Float64 Values
This instruction calculates 2/4/8 range operation outputs fr om two sets of packed input double precision floating-
point values in the first source operand (the second oper and) and the second source operand (the third operand). 
The range outputs are written to the destination op erand (the first operand) under the writemask k1. 
Bits7:4 of imm8 byte must be zero. The range operation ou tput is performed in two parts, each configured by a 
two-bit control field within imm8[3:0]:
•Imm8[1:0] specifies the initial comparison operation to  be one of max, min, max absolute value or min 
absolute value of the input value pair. Each comparison of two input values produces an intermediate result 
that combines with the sign selection control (imm8 [3:2]) to determine the final range operation output.
•Imm8[3:2] specifies the sign of the range operation outp ut to be one of the following: from the first input 
value, from the comparison result, set or clear.
The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W1 50 /r ib
VRANGEPD xmm1 {k1}{z}, xmm2, 
AVX512DQCalculate two RANGE operation output value from 2 pairs 
of double precision floating-point values in xmm2 and 
xmm3/m128/m32bcst, store the results to xmm1 under 
the writemask k1. Imm8 specifies the comparison and sign of the range operation.
EVEX.256.66.0F3A.W1 50 /r ib
VRANGEPD ymm1 {k1}{z}, ymm2, 
AVX512DQCalculate four RANGE operatio n output value from 4pairs 
of double precision floating-point values in ymm2 and 
ymm3/m256/m32bcst, store the results to ymm1 under the writemask k1. Imm8 specifies the comparison and sign 
of the range operation.
EVEX.512.66.0F3A.W1 50 /r ib
VRANGEPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst{sae}, imm8A V/V AVX512DQ Calculate eight RANGE operation output value from 8 
pairs of double precision floating-point values in zmm2 
and zmm3/m512/m32bcst, store the results to zmm1 
under the writemask k1. Imm8 specifies the comparison and sign of the range operation.
A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8
Figure 5-27.  Imm8 Controls for VRANGEPD/SD/PS/SS7 0 2 4 65 3 1
Compare Operation Select Must Be Zero
Imm8[3:2] = 00b : Select sign(SRC1)Sign Control (SC)
Imm8[3:2] = 01b : Select sign(Compare_Result)
Imm8[3:2] = 10b : Set sign to 0Imm8[1:0] = 00b : Select Min value
Imm8[1:0] = 01b : Select Max valueImm8[1:0] = 10b : Select Min-Abs valueImm8[1:0] = 11b : Select Max-Abs valueimm8
Imm8[3:2] = 11b : Set sign to 1VRANGEPD—Range Restriction Calculatio n for Packed Pairs of Float64 ValuesINSTRUCTION SET REFERENCE, V
5-626 Vol. 2CWhen one or more of the input value is a NAN, the compar ison operation may signal invalid exception (IE). Details 
with one of more input value is NAN is listed in Table 5-23.  If the comparison raises an IE, the sign select control 
(imm8[3:2]) has no effect to the range operation output; this is indicated also in Table 5-23.
When both input values are zeros of opposite signs, th e comparison operation of MIN/MAX in the range compare 
operation is slightly different from th e conceptually similar floating-point MIN/MAX operation that are found in the 
instructions VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magnitude-0, opposite-signed input cases are listed in Table 5-24.
Additionally, non-zero, equal-magnitude with opposite-s ign input values perform MIN_ABS or MAX_ABS compar-
ison operation with result listed in Table 5-25.
Operation
RangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-23IF (SRC1 = SNAN) THEN RETU RN (QNAN(SRC1), set IE);
IF (SRC2 = SNAN) THEN RETU RN (QNAN(SRC2), set IE);
Src1.exp := SRC1[62:52];
Src1.fraction := SRC1[51:0];IF ((Src1.exp = 0 ) and (Src1.fraction !=  0)) THEN// Src1 is a denormal number
IF DAZ THEN Src1.fraction := 0;ELSE IF (SRC2 <> QNAN) Set DE; FI;
FI;Table 5-23. Signaling of Comparison Operation of One or More NaN Inpu t Values and Effect of Imm8[3:2]
Src1 Src2 Result IE Signaling Due to Comparison Imm8[3:2] Effect to Range Output
sNaN1 sNaN2 Quiet(sNaN1) Yes Ignored
sNaN1 qNaN2 Quiet( sNaN1) Yes Ignored
sNaN1 Norm2 Quiet( sNaN1) Yes Ignored
qNaN1 sNaN2 Quiet(sNaN2) Yes Ignored
qNaN1 qNaN2 qNaN1 No Applicable
qNaN1 Norm2 Norm2 No ApplicableNorm1 sNaN2 Quiet(sNaN2) Yes Ignored
Norm1 qNaN2 Norm1 No Applicable
Table 5-24. Comparison Result fo r Opposite-Signed Zero Cases for MIN, MIN_ABS, and MAX, MAX_ABS
MIN and MIN_ABS MAX and MAX_ABS
Src1 Src2 Result Src1 Src2 Result
+0 -0 -0 +0 -0 +0
-0 +0 -0 -0 +0 +0
Table 5-25. Comparison Result  of Equal-Magnitude Input Cases for MIN_ ABS and MAX_ABS, (|a|  = |b|, a>0, b<0)

MIN_ABS (|a| = |b|, a>0, b<0) MAX_ABS (|a| = |b|, a>0, b<0)
ab b ab aba b ba aVRANGEPD—Range Restriction Calculatio n for Packed Pairs of Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-627Src2.exp := SRC2[62:52];
Src2.fraction := SRC2[51:0];IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number
IF DAZ THEN Src2.fraction := 0;ELSE IF (SRC1 <> QNAN) Set DE; FI;
FI;
IF (SRC2 = QNAN) THEN{TMP[63:0] := SRC1[63:0]}
ELSE IF(SRC1 = QNAN) THEN{T MP[63:0] := SRC2[63:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] := from Table 5-24
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-s igned and CmpOpCtl[1:0] > 01) TMP[63:0] := from Table 5-25
ELSE 
Case(CmpOpCtl[1:0])00: TMP[63:0] := (SRC1[63:0] ≤ SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];
01: TMP[63:0] := (SRC1[63:0] ≤ SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];
10: TMP[63:0] := (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];
11: TMP[63:0] := (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];
ESAC;
FI;
Case(SignSelCtl[1:0])
00: dest := (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit01: dest := TMP[63:0];// Preserve sign of compare result10: dest := (0 << 63) OR (TMP [62:0]);// Zero out sign bit
11: dest := (1 << 63) OR (TMP [62:0]);// Set the sign bit
ESAC;RETURN dest[63:0];
}
CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];
VRANGEPD (EVEX encoded versions) 
THEN DEST[i+63:i] := RangeDP (SRC1[i+63:i], SRC2[63:0], CmpO pCtl[1:0], SignSelCtl[1:0]);
ELSE DEST[i+63:i] := RangeDP (SRC1[i+63:i], SRC2[i+63:i], CmpOpCtl[1 :0], SignSelCtl[1:0]);
FI;
ELSE 
FI;
FI;
The following example describes a common usage of this  instruction for checking that the input operand is
bounded between ±1023.VRANGEPD—Range Restriction Calculatio n for Packed Pairs of Float64 ValuesINSTRUCTION SET REFERENCE, V
5-628 Vol. 2CVRANGEPD zmm_dst, zmm_src, zmm_1023, 02h;
Where:
zmm_dst is the destination operand.
zmm_src is the input operand to compare against ±1023 (this is SRC1).
zmm_1023 is the reference operand, contains the value of 1023 (and this is SRC2).IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of SRC1.sign.
In case |zmm_src| < 1023 (i.e., SRC1 is smaller than 1023 in magnitude), then its value will be written into
zmm_dst. Otherwise, the value stored  in zmm_dst will get the value of 1023 (received on zmm_1023, which is
SRC2).
However, the sign control (imm8[3:2]='00) instructs to se lect the sign of SRC1 received from zmm_src. So, even
in the case of |zmm_src| ≥ 1023, the selected sign of SRC1 is kept. 
Thus, if zmm_src < -1023, the result of VRANGEPD will be the minimal valu e of -1023 while if zmm_src > +1023,
the result of VRANGE will be the maximal value of +1023.
VRANGEPD __m512d _mm512_range_pd ( __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_range_round_pd ( __ m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_mask_range_pd (__m512 ds , __mmask8 k, __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_mask_range_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_maskz_r ange_pd ( __mmask8 k, __m512d  a, __m512d b, int imm);
VRANGEPD __m512d _mm512_maskz_range _round_pd ( __mmask8 k, __m512d a,  __m512d b, int imm, int sae);
VRANGEPD __m256d _mm256_range_pd ( __m256d a, __m256d b, int imm);VRANGEPD __m256d _mm256_mask_range_pd (__m256d s,  __mmask8 k, __m256d a, __m256d b, int imm);
VRANGEPD __m256d _mm256_maskz_r ange_pd ( __mmask8 k, __m256d  a, __m256d b, int imm);
VRANGEPD __m128d _mm_range_pd ( __m128 a, __m128d b, int imm);VRANGEPD __m128d _mm_mask_range _pd (__m128 s, __mmask8 k, __m128d a, __m128d b, int imm);
VRANGEPD __m128d _mm_maskz_range_pd ( __mma sk8 k, __m128d a, __m128d b, int imm);
See Table 2-46, “Type E2 Class Exception Conditions.”VRANGEPS—Range Restriction Calculatio n for Packed Pairs of Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-629 VRANGEPS—Range Restriction Calculat ion for Packed Pairs of Float32 Values
This instruction calculates 4/8/16 range operation outputs from two sets of packed input single-precision floating-
The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.When one or more of the input value is a NAN, the compar ison operation may signal invalid exception (IE). Details 
When both input values are zeros of opposite signs, th e comparison operation of MI N/MAX in the range compare 
operation is slightly different from the conceptually sim ilar floating-point MIN/MAX operation that are found in the 
instructions VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS 
for magnitude-0, opposite-signed input cases are listed in Table 5-24.
ison operation with result listed in Table 5-25.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W0 50 /r ib
VRANGEPS xmm1 {k1}{z}, xmm2, 
AVX512DQCalculate four RANGE operation output value from 4 pairs 
of single-precision floating-point values in xmm2 and 
EVEX.256.66.0F3A.W0 50 /r ib
VRANGEPS ymm1 {k1}{z}, ymm2, 
AVX512DQCalculate eight RANGE operation output value from 8 pairs 
of single-precision floating-point values in ymm2 and 
ymm3/m256/m32bcst, store th e results to ymm1 under 
the writemask k1. Imm8 specifies the comparison and sign 
EVEX.512.66.0F3A.W0 50 /r ib
VRANGEPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst{sae}, imm8A V/V AVX512DQ Calculate 16 RANGE operation output value from 16 pairs 
of single-precision floating-point values in zmm2 and 
zmm3/m512/m32bcst, store the results to zmm1 under 
A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8VRANGEPS—Range Restriction Calculatio n for Packed Pairs of Float32 ValuesINSTRUCTION SET REFERENCE, V
5-630 Vol. 2COperation
RangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-23IF (SRC1=SNAN) THEN RETU RN (QNAN(SRC1), set IE);
IF (SRC2=SNAN) THEN RETU RN (QNAN(SRC2), set IE);
Src1.exp := SRC1[30:23];
Src1.fraction := SRC1[22:0];IF ((Src1.exp = 0 ) and (Src1.fraction !=  0 )) THEN// Src1 is a denormal number
FI;Src2.exp := SRC2[30:23];Src2.fraction := SRC2[22:0];IF ((Src2.exp = 0 ) and (Src2.fraction !=  0 )) THEN// Src2 is a denormal number
FI;
IF (SRC2 = QNAN) THEN{TMP[31:0] := SRC1[31:0]}
ELSE IF(SRC1 = QNAN) THEN{T MP[31:0] := SRC2[31:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] := from Table 5-24
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] := from Table 5-25ELSE 
Case(CmpOpCtl[1:0])00: TMP[31:0] := (SRC1[31:0] ≤ SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];
01: TMP[31:0] := (SRC1[31:0] ≤ SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];
10: TMP[31:0] := (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];

FI;
11: TMP[31:0] := (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];
ESAC;
FI;Case(SignSelCtl[1:0])00: dest := (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit01: dest := TMP[31:0];// Preserve sign of compare result10: dest := (0 << 31) OR (TMP [30:0]);// Zero out sign bit
11: dest := (1 << 31) OR (TMP [30:0]);// Set the sign bit
ESAC;RETURN dest[31:0];
}
VRANGEPS 
THEN DEST[i+31:i] := RangeSP (SRC1[i+31:i], SRC2[31:0], CmpOpCtl[1:0 ], SignSelCtl[1:0]);
ELSE DEST[i+31:i] := RangeSP (SRC1[i+31:i], SR C2[i+31:i], CmpOpCtl[1:0 ], SignSelCtl[1:0]);
FI;VRANGEPS—Range Restriction Calculatio n for Packed Pairs of Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-631ELSE 
FI;
FI;
bounded between ±150.
VRANGEPS zmm_dst, zmm_src, zmm_150, 02h;
Where:
zmm_src is the input operand to compare against ±150.zmm_150 is the reference operand, contains the value of 150.
IMM=02(imm8[1:0]=’10) selects the Min Absolute value operation with selection of src1.sign.
In case |zmm_src| < 150, then its value will be writte n into zmm_dst. Otherwise, the value stored in zmm_dst
will get the value of 150 (received on zmm_150).
However, the sign control (imm8[3:2]=’00) instructs to se lect the sign of SRC1 received from zmm_src. So, even
in the case of |zmm_src| ≥ 150, the selected sign of SRC1 is kept. 
Thus, if zmm_src < -150, the result of VRANGEPS will be  the minimal value of -150 while if zmm_src > +150,
the result of VRANGE will be the maximal value of +150.
VRANGEPS  __m512 _mm512_range_ps ( __m512 a, __m512 b, int imm);
VRANGEPS  __m512 _mm512_range_round_ps ( __m512 a, __m512 b, int imm, int sae);
VRANGEPS  __m512 _mm512_mask_range_ps (__m512 s, __mma sk16 k, __m512 a, __m512 b, int imm);
VRANGEPS  __m512 _mm512_mask_range_round_ps (__m512 s, __mma sk16 k, __m512 a, __m512 b, int imm, int sae);
VRANGEPS  __m512 _mm512_maskz_range_ps ( __mmask16 k, __m512 a, __m512 b, int imm);
VRANGEPS  __m512 _mm512_maskz_range_round_ps ( __mmask16 k, __m512 a, __m512 b, int imm, int sae);
VRANGEPS  __m256 _mm256_range_ps ( __m256 a, __m256 b, int imm);
VRANGEPS  __m256 _mm256_mask_range_ps (__m256 s, __m mask8 k, __m256 a, __m256 b, int imm);
VRANGEPS  __m256 _mm256_maskz_range_ps ( __mmask8 k, __m256 a, __m256 b, int imm);
VRANGEPS  __m128 _mm_range_ps ( __m128 a, __m128 b, int imm);
VRANGEPS  __m128 _mm_mask_range_ps (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRANGEPS  __m128 _mm_maskz_range_ps ( __mmask8 k, __m128 a, __m128 b, int imm);
See Table 2-46, “Type E2 Class Exception Conditions.”VRANGESD—Range Restriction Calculation From a Pair of Scalar Float64 ValuesINSTRUCTION SET REFERENCE, V
5-632 Vol. 2CVRANGESD—Range Restriction Calculation From a Pair of Scalar Float64 Values
This instruction calculates a range operation output from tw o input double precision floating-point values in the low 
qword element of the first source operand (the second op erand) and second source operand (the third operand). 
The range output is written to the low qword element of  the destination operand (the first operand) under the 
absolute value of the input value pair. Each comparison of two input values pr oduces an intermediate result that 
combines with the sign selection control (imm8[3:2]) to determine the final range operation output.
The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.Bits 128:63 of the destination operand are copied from  the respective element of the first source operand.
When one or more of the input value is a NAN, the compar ison operation may signal invalid exception (IE). Details 
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W1 51 /r
VRANGESD xmm1 {k1}{z}, 
xmm2, xmm3/m64{sae}, imm8A V/V AVX512DQ Calculate a RANGE operation output value from 2 double 
precision floating-point values in xmm2 and xmm3/m64, 
store the output to xmm1 under writemask. Imm8 specifies 
the comparison and sign of the range operation.
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8VRANGESD—Range Restriction Calculation From a Pair of Scalar Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-633Operation
{
// Check if SNAN and report IE, see also Table 5-23IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);
IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);
FI;
Src2.exp := SRC2[62:52];
FI;
ELSE 
ESAC;
FI;
}
SignSelCtl[1:0]=imm8[3:2];VRANGESD—Range Restriction Calculation From a Pair of Scalar Float64 ValuesINSTRUCTION SET REFERENCE, V
5-634 Vol. 2CVRANGESD 
THEN DEST[63:0] := RangeDP (SRC1[63:0], SR C2[63:0], CmpOpCtl[1:0 ], SignSelCtl[1:0]);
ELSE 
DEST[63:0] = 0
FI;
The following example describes a common usage of this in struction for checking that the input operand is bound-
ed between ±1023.
VRANGESD xmm_dst, xmm_src, xmm_1023, 02h;
Where:
xmm_dst is the destination operand.xmm_src is the input operand to compare against ±1023.
xmm_1023 is the reference operand, contains the value of 1023.
In case |xmm_src| < 1023, then its value will be writte n into xmm_dst. Otherwise, the value stored in xmm_dst
will get the value of 1023 (received on xmm_1023).
However, the sign control (imm8[3:2]=’00) instructs to se lect the sign of SRC1 received from xmm_src. So, even
in the case of |xmm_src| ≥ 1023, the selected sign of SRC1 is kept. 
Thus, if xmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023while if xmm_src > +1023,

FI;
Where:
VRANGESD  __m128d _mm_range_sd ( __m128d a, __m128d b, int imm);
VRANGESD  __m128d _mm_range_round_sd ( __m128d a, __m128d b, int imm, int sae);
VRANGESD  __m128d _mm_mask_range_sd (__m128d s, __mma sk8 k, __m128d a, __m128d b, int imm);
VRANGESD  __m128d _mm_mask_range_round_sd (__m128d s, __mma sk8 k, __m128d a, __m128d b, int imm, int sae);
VRANGESD  __m128d _mm_maskz_range_sd ( __mmask 8 k, __m128d a, __m128d b, int imm);
VRANGESD  __m128d _mm_maskz_range_round_sd ( __mmask8 k, __m128d a, __m128d b, int imm, int sae);
See Table 2-47, “Type E3 Class Exception Conditions.”VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-635VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values
This instruction calculates a range operation output from tw o input single-precision floating-point values in the low 
dword element of the first source operand (the second op erand) and second source operand (the third operand). 
The range output is written to the low dword element of the destination operand (the first operand) under the 
The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.Bits 128:31 of the destination operand are copied from the respective elements of the first source operand.
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W0 51 /r
VRANGESS xmm1 {k1}{z}, 
xmm2, xmm3/m32{sae}, imm8A V/V AVX512DQ Calculate a RANGE operation output value from 2 single-
precision floating-point values in xmm2 and xmm3/m32, 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 ValuesINSTRUCTION SET REFERENCE, V
5-636 Vol. 2COperation
{
FI;
ESAC;
}
SignSelCtl[1:0]=imm8[3:2];VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-637VRANGESS 
THEN DEST[31:0] := RangeSP (SRC1[31:0], SR C2[31:0], CmpOpCtl[1:0 ], SignSelCtl[1:0]);
ELSE 
DEST[31:0] = 0
FI;
VRANGESS zmm_dst, zmm_src, zmm_150, 02h;
Where:
xmm_dst is the destination operand.xmm_src is the input operand to compare against ±150.
xmm_150 is the reference operand, contains the value of 150.
In case |xmm_src| < 150, then its value will be writte n into zmm_dst. Otherwise, the value stored in xmm_dst
However, the sign control (imm8[3:2]=’00) instructs to se lect the sign of SRC1 rece ived from xmm_src. So, even
in the case of |xmm_src| ≥ 150, the selected sign of SRC1 is kept. 
Thus, if xmm_src < -150, the result of VRANGESS will be  the minimal value of -150 while if xmm_src > +150,
VRANGESS  __m128 _mm_range_ss ( __m128 a, __m128 b, int imm);
VRANGESS  __m128 _mm_range_round_ss ( __m128 a, __m128 b, int imm, int sae);
VRANGESS  __m128 _mm_mask_range_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRANGESS  __m128 _mm_mask_range_round_ss (__m128 s, __mmask8 k, __m128 a,  __m128 b, int imm, int sae);
VRANGESS  __m128 _mm_maskz_range_ss ( __mmask8 k, __m128 a, __m128 b, int imm);
VRANGESS  __m128 _mm_maskz_range_round_ss ( __mmask8 k, __m128 a, __m128 b,  int imm, int sae);
See Table 2-47, “Type E3 Class Exception Conditions.”VRCP14PD—Compute Approximate Reciprocals of Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
5-638 Vol. 2CVRCP14PD—Compute Approximate Reci procals of Packed Float64 Values
This instruction performs a SIMD computation of the ap proximate reciprocals of eight/four/two packed double 
precision floating-point values in the source operand (the  second operand) and stores the packed double precision 
floating-point results in the destination operand. The maxi mum relative error for this approximation is less than 2-
14. 
The source operand can be a ZMM register, a 512-bit memory  location, or a 512-bit vector broadcasted from a 64-
bit memory location. The destination operand is a ZMM re gister conditionally updated according to the writemask.
The VRCP14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source value 
is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in 
case of DAZ bit set in MXCSR.  Otherwise it is treated correctly (i.e., no t as a 0.0). Underflow results are flushed to 
zero only in case of FTZ bit set in MX CSR. Otherwise it will be treated correct ly (i.e., correct underflow result is 
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN or 
the source QNaN is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
* in this case the mantissa is shifted right by one or two bits
A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-inst ructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2 .Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W1 4C /r
VRCP14PD xmm1 {k1}{z}, 
AVX512FComputes the approximate reciprocals of the packed double 
precision floating-point values in xmm2/m128/m64bcst and 
stores the results in xmm1. Under writemask.
EVEX.256.66.0F38.W1 4C /r
VRCP14PD ymm1 {k1}{z}, ymm2/m256/m64bcstAV / V A V X 5 1 2 V L
precision floating-point values in ymm2/m256/m64bcst and stores the results in ymm1. Under writemask.
EVEX.512.66.0F38.W1 4C /r
VRCP14PD zmm1 {k1}{z}, 
zmm2/m512/m64bcstA V/V AVX512F Computes the approximate reciprocals of the packed double 
precision floating-point values in zmm2/m512/m64bcst and 
stores the results in zmm1. Under writemask.
Table 5-26. VRCP14PD/VRCP14SD Special Cases
Input value Result value Comments
0 ≤ X ≤ 2-1024INF Very small denormal
-2-1024 ≤ X ≤ -0 -INF Very small denormal
X > 21022Underflow Up to 18 bits of  fractions are returned*
X < -21022-Underflow Up to 18 bits of  fractions are returned*
X = 2-n2n
X = -2-n-2nVRCP14PD—Compute Approximate Reciprocals of Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-639Operation
VRCP14PD ((EVEX encoded versions) 
THEN DEST[i+63:i] := AP PROXIMATE(1.0/SRC[63:0]);
ELSE DEST[i+63:i] := APPR OXIMATE(1.0/SRC[i+63:i]);
FI;
ELSE 
FI;
FI;
ENDFOR;
VRCP14PD __m512d _mm512_rcp14_pd( __m512d a);
VRCP14PD __m512d _mm512_mask_rcp14_pd(__m512d s, __mmask8 k, __m512d a);
VRCP14PD __m512d _mm512_maskz_rcp14_pd( __mmask8 k, __m512d a);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
5-640 Vol. 2CVRCP14SD—Compute Approximate Reci procal of Scalar Float64 Value
This instruction performs a SIMD computation of the approximate reciprocal of the low double precision floating-
point value in the second source operand (the third operan d) stores the result in the low quadword element of the 
destination operand (the first operand) according to the writemask k1. Bits (127:64) of the XMM register destina-
tion are copied from corresponding bits in the first so urce operand (the second operand). The maximum relative 
error for this approximation is less than 2-14. The source operand can be an XMM register or a 64-bit memory loca-
tion. The destination oper and is an XMM register.
The VRCP14SD instruction is not affected by the rounding co ntrol bits in the MXCSR register. When a source value 
the source QNaN is returned. See Table 5-26 for special-case input values.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.A numerically exact implementation of VRCP14xx can be found at:
h
ttps://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-
vrsqrt14-vrcp28-vrsqrt28-vexp2 .
Operation
VRCP14SD (EVEX version)
THEN DEST[63:0] := APPR OXIMATE(1.0/SRC2[63:0]);
ELSE 
FI;
/ En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W1 4D /r
VRCP14SD xmm1 {k1}{z}, xmm2, 
xmm3/m64A V/V AVX512F Computes the approximate reciprocal of the scalar double 
precision floating-point value in xmm3/m64 and stores the 
result in xmm1 using writemask k1. Also, upper double 
precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVRCP14SD—Compute Approximate Recipr ocal of Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-641Intel C/C++ Compiler Intrinsic Equivalent
VRCP14SD __m128d _mm_rcp14_sd( __m128d a, __m128d b);
VRCP14SD __m128d _mm_mask_rcp14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VRCP14SD __m128d _mm_maskz_rcp14_sd( __mmask8 k, __m128d a, __m128d b);
None.
See Table 2-51, “Type E5 Class Exception Conditions.”VRCP14PS—Compute Approximate Reciprocals of Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
5-642 Vol. 2CVRCP14PS—Compute Approximate Reci procals of Packed Float32 Values
This instruction performs a SIMD computation of the approximate reciprocals of the packed single-precision 
floating-point values in the source operand (the second operand) and stores the packed single-precision floating-
point results in the destination operand (the first operan d). The maximum relative error for this approximation is 
less than 2-14. 
The source operand can be a ZMM register, a 512-bit memo ry location or a 512-bit vector broadcasted from a 32-
The VRCP14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source value 
A numerically exact implementation of VRCP14xx can be found at:
h
vrsqrt14-vrcp28-vrsqrt28-vexp2 .Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 4C /r
VRCP14PS xmm1 {k1}{z}, 
AVX512FComputes the approximate reciprocals of the packed single-
precision floating-point values in xmm2/m128/m32bcst and 
EVEX.256.66.0F38.W0 4C /r
VRCP14PS ymm1 {k1}{z}, ymm2/m256/m32bcstAV / V A V X 5 1 2 V L
precision floating-point values in ymm2/m256/m32bcst and stores the results in ymm1. Under writemask.
EVEX.512.66.0F38.W0 4C /r
VRCP14PS zmm1 {k1}{z}, 
zmm2/m512/m32bcstA V/V AVX512F Computes the approximate reciprocals of the packed single-
precision floating-point values in zmm2/m512/m32bcst and 
Table 5-27. VRCP14PS/VRCP14SS Special Cases
0 ≤ X ≤ 2-128INF Very sma ll denormal
-2-128 ≤ X ≤ -0 -INF Very small denormal
X > 2126Underflow Up to 18 bits of fractions are returned1
NOTES:
1. In this case, the mantissa is shifted right by one or two bits.X < -2126-Underflow Up to 18 bits of fractions are returned1
X = 2-n2n
X = -2-n-2nVRCP14PS—Compute Approximate Recipr ocals of Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-643Operation
VRCP14PS (EVEX encoded versions) 
THEN DEST[i+31:i] := AP PROXIMATE(1.0/SRC[31:0]);
ELSE DEST[i+31:i] := APPR OXIMATE(1.0/SRC[i+31:i]);
FI;
ELSE 
FI;
FI;
ENDFOR;

NOTES:
X = 2-n2n
FI;
ELSE 
FI;
FI;
ENDFOR;
VRCP14PS __m512 _mm512_rcp14_ps( __m512 a);
VRCP14PS __m512 _mm512_mask_rcp14_ps(__m512 s, __mmask16 k, __m512 a);
VRCP14PS __m512 _mm512_maskz_rcp14_ps( __mmask16 k, __m512 a);VRCP14PS __m256 _mm256_rcp14_ps( __m256 a);
VRCP14PS __m256 _mm512_mask_rcp14_ps(__m256 s, __mmask8 k, __m256 a);
VRCP14PS __m256 _mm512_maskz_rcp14_ps( __mmask8 k, __m256 a);VRCP14PS __m128 _mm_rcp14_ps( __m128 a);
VRCP14PS __m128 _mm_mask_rcp14_ps(__m128 s, __mmask8 k, __m128 a);
VRCP14PS __m128 _mm_maskz_rcp14_ps( __mmask8 k, __m128 a);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”VRCP14SS—Compute Approximate Recipr ocal of Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
5-644 Vol. 2CVRCP14SS—Compute Approximate Reci procal of Scalar Float32 Value
This instruction performs a SIMD computation of the approximate reciprocal of the low single-precision floating-
point value in the second source operand (the third operan d) and stores the result in the low quadword element of 
the destination operand (the first operand) according to th e writemask k1. Bits (127:32) of the XMM register desti-
nation are copied from corresponding bits in the first source operand (the second operand). The maximum relative 
error for this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory loca-
The VRCP14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source value 
the source QNaN is returned. See Table 5-27 for special-case input values.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-inst ructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2 .
Operation
VRCP14SS (EVEX version)
THEN DEST[31:0] := APPR OXIMATE(1.0/SRC2[31:0]);
ELSE 
FI;
FI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0Opcode/
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W0 4D /r
VRCP14SS xmm1 {k1}{z}, xmm2, 
xmm3/m32A V/V AVX512F Computes the approximate reciprocal of the scalar single-
precision floating-point value in xmm3/m32 and stores the 
results in xmm1 using writemask k1. Also, upper double 
precision floating-point value (bits[127:32]) from xmm2 is copied to xmm1[127:32]. 
A Tuple1 Scalar ModRM:reg (w) E VEX.vvvv (r) ModRM:r/m (r) N/AVRCP14SS—Compute Approximate Recipr ocal of Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-645Intel C/C++ Compiler Intrinsic Equivalent
VRCP14SS __m128 _mm_rcp14_ss( __m128 a, __m128 b);
VRCP14SS __m128 _mm_mask_rcp14_ss(__m128  s, __mmask8 k, __m128 a, __m128 b);
VRCP14SS __m128 _mm_maskz_rcp14_ss( __mmask8 k, __m128 a, __m128 b);
None.
See Table 2-51, “Type E5 Class Exception Conditions.”VRCPPH—Compute Reciprocals of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-646 Vol. 2CVRCPPH—Compute Reciprocals of Packed FP16 Values
This instruction performs a SIMD computation of the appr oximate reciprocals of 8/16/32 packed FP16 values in the 
source operand (the second operand) and stores the pack ed FP16 results in the destination operand. The maximum 
relative error for this approximation is less than 2−11 + 2−14.
For special cases, see Table 5-28.
Operation
VRCPPH dest{k1}, src 
ELSE:
DEST.fp16[i] := APPROXIMATE(1.0 / tsrc)
En64/32 
bit Mode 
EVEX.128.66.MAP6.W0  4C /r
VRCPPH xmm1{k1}{z}, xmm2/m128/
m16bcstA V/V AVX512-FP16 
AVX512VLCompute the approximate reciprocals of packed 
FP16 values in xmm2/m128/m16bcst and store 
EVEX.256.66.MAP6.W0  4C /r
VRCPPH ymm1{k1}{z}, ymm2/m256/
FP16 values in ymm2/m256/m16bcst and store the result in ymm1 subject to writemask k1.
EVEX.512.66.MAP6.W0  4C /r
VRCPPH zmm1{k1}{z}, zmm2/m512/m16bcstA V/V AVX512-FP16 Compute the approximate reciprocals of packed 
FP16 values in zmm2/m512/m16bcst and store 
Table 5-28. VRCPPH/VRCPSH Special Cases
Input Value Result Value Comments0 ≤ X ≤ 2
-16INF Very small denormal
−2-16 ≤ X ≤ -0 −INF Very small denormal
X > +∞ +0
X < −∞ − 0
X = 2-n2n
X = −2-n−2nVRCPPH—Compute Reciprocal s of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-647Intel C/C++ Compiler Intrinsic Equivalent
VRCPPH __m128h _mm_mask_rcp_ph (__m12 8h src, __mmask8 k, __m128h a);
VRCPPH __m128h _mm_maskz_rcp_ph (__mmask8 k, __m128h a);VRCPPH __m128h _mm_rcp_ph (__m128h a);VRCPPH __m256h _mm256_mask_rcp_ph (__m 256h src, __mmask16 k, __m256h a);
VRCPPH __m256h _mm256_maskz_rcp_ph (__mmask16 k, __m256h a);VRCPPH __m256h _mm256_rcp_ph (__m256h a);VRCPPH __m512h _mm512_mask_rcp_ph (__m 512h src, __mmask32 k, __m512h a);
VRCPPH __m512h _mm512_maskz_rcp_ph (__mmask32 k, __m512h a);VRCPPH __m512h _mm512_rcp_ph (__m512h a);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”VRCPSH—Compute Reciprocal of Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
5-648 Vol. 2CVRCPSH—Compute Reciprocal of Scalar FP16 Value
This instruction performs a SIMD computation of the appr oximate reciprocal of the low FP16 value in the second 
source operand (the third operand) and stores the result in the low word element of the destination operand (the 
first operand) according to the writemask k1. Bits 127:16  of the XMM register destination are copied from corre-
sponding bits in the first source operand (the second op erand). The maximum relative error for this approximation 
is less than 2−11 + 2−14.
Operation
VRCPSH dest{k1}, src1, src2 
DEST.fp16[0] := APPROXIMATE(1.0 / src2.fp16[0])
VRCPSH __m128h _mm_mask_rcp_sh (__m128h sr c, __mmask8 k, __m128h a, __m128h b);
VRCPSH __m128h _mm_maskz_rcp_sh (_ _mmask8 k, __m128h a, __m128h b);
VRCPSH __m128h _mm_rcp_sh (__m128h a, __m128h b);
None.
EVEX-encoded instruction, see Table 2-58, “Type E10 Class Exception Conditions.”Opcode/
En64/32 
bit Mode 
EVEX.LLIG.66.MAP6.W0 4D /r
VRCPSH xmm1{k1}{z}, xmm2, xmm3/
m16A V/V AVX512-FP16 Compute the approximate reciprocal of the low 
FP16 value in xmm3/m16 and store the result in 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVREDUCEPD—Perform Reduction Transfor mation on Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-649VREDUCEPD—Perform Reduct ion Transformation on Packed Float64 Values
Perform reduction transformation of the packed binary enco ded double precision floating-point values in the source 
operand (the second operand) and store the reduced result s in binary floating-point format to the destination 
operand (the first operand) under the writemask k1.

En64/32 
bit Mode 
operand (the first operand) under the writemask k1. 
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-
point source value, where M is a unsigned integer specif ied by imm8[7:4], see Figure 5-28. Specifically, the reduc-
tion transformation can be expressed as:
dest = src – (ROUND(2M*src))*2-M;
where “Round()” treats “src”, “2M”, and their product as binary floating -point numbers with normalized signifi-
cand and biased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where ‘man2’ is the normalized signif icand and ‘p’ is the unbiased exponent 
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC ≠ RNE: 0<=|Reduced Result|<2p-M
This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision 
Exception, which is imm8[3]=1), no precision exception is reported.
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W1 56 /r ib
VREDUCEPD xmm1 {k1}{z}, 
AVX512DQPerform reduction transformation on packed double precision 
floating-point values in xmm2/m128/m32bcst by subtracting 
a number of fraction bits specified by the imm8 field. Stores 
the result in xmm1 register under writemask k1.
EVEX.256.66.0F3A.W1 56 /r ib
VREDUCEPD ymm1 {k1}{z}, 
floating-point values in ymm2/m256/m32bcst by subtracting 
the result in ymm1 register under writemask k1.
EVEX.512.66.0F3A.W1 56 /r ib
VREDUCEPD zmm1 {k1}{z}, 
imm8A V/V AVX512DQ Perform reduction transformation on double precision 
floating-point values in zmm2/m512/m32bcst by subtracting 
the result in zmm1 register under writemask k1.
Figure 5-28.  Imm8 Contro ls for VREDUCEPD/SD/PS/SS7 0 2 4 6 531
Round Control Override Fixed point length
Imm8[7:4] : Number of fixed points to subtractRS
Imm8[1:0] = 00b : Round nearest even
Imm8[1:0] = 01b : Round downImm8[1:0] = 10b : Round upImm8[1:0] = 11b : Truncateimm8
SPE
Round Select: Imm8[2] 
Imm8[2] = 0b : Use Imm8[1:0]Imm8[2] = 1b : Use MXCSRSuppress Precision Exception: Imm8[3] 
Imm8[3] = 0b : Use MXCSR exception mask
Imm8[3] = 1b : SuppressVREDUCEPD—Perform Reduction Transfor mation on Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
5-650 Vol. 2CHandling of special case of input values are listed in Table 5-29.
* Round control = (imm8.MS1)? MXCSR.RC: imm8.RC
Operation
ReduceArgumentDP(SRC [63:0], imm8[7:0])
{
// Check for NaNIF (SRC [63:0] = NAN) THEN
RETURN (Convert SRC[63:0] to QNaN); FI;
M := imm8[7:4]; // Number of fraction bits of the normalized  significand to be subtracted
RC := imm8[1:0];// Round Co ntrol for ROUND() operation
RC source := imm[2];SPE := imm[3];// Suppress Precision ExceptionTMP[63:0] := 2
-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
TMP[63:0] := SRC[63:0] – TMP[63:0]; // su btraction under the same RC,SPE controls
RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
}
VREDUCEPD 
THEN DEST[i+63:i] := ReduceAr gumentDP(SRC[63:0], imm8[7:0]);
ELSE DEST[i+63:i] := ReduceArgu mentDP(SRC[i+63:i], imm8[7:0]);
FI;
ELSE 
FI;
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0Table 5-29. VREDUCEPD/SD/PS/SS Special Cases
Round Mode Returned value 
|Src1| < 2-M-1RNE Src1
|Src1| < 2-MRPI, Src1 > 0 Round (Src1-2-M) *
RPI, Src1 ≤ 0S r c 1
RNI, Src1 ≥ 0S r c 1
RNI, Src1 < 0 Round (Src1+2-M) *
Src1 = ±0, or
Dest = ±0 (Src1!=INF)NOT RNI +0.0
RNI -0.0
Src1 = ±INF any +0.0
Src1= ±NAN n/a QNaN(Src1)VREDUCEPD—Perform Reduction Transfor mation on Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-651Intel C/C++ Compiler Intrinsic Equivalent
VREDUCEPD __m512d _mm512_mask_reduce _pd( __m512d a, int imm, int sae)
VREDUCEPD __m512d _mm512_mask_reduce_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae)VREDUCEPD __m512d _mm512_maskz_reduce_pd( __mmask8 k, __m512d a, int imm, int sae)
VREDUCEPD __m256d _mm256_mask_reduce_pd( __m256d a, int imm)VREDUCEPD __m256d _mm256_mask_reduce_pd(__m256d s, __mmask8 k, __m256d a, int imm)VREDUCEPD __m256d _mm256_maskz_reduce_ pd(__mmask8 k, __m256d a, int imm)
VREDUCEPD __m128d _mm_mask_reduce_pd( __m128d a, int imm)VREDUCEPD __m128d _mm_mask_reduce_pd(__m128d s, __mmask8 k, __m128d a, int imm)VREDUCEPD __m128d _mm_maskz_reduce _pd(__mmask8 k, __m128d a, int imm)
If SPE is enabled, precision ex ception is not reported (regardless of MXCSR exception mask).
Additionally:#UD If EVEX.vvvv != 1111B.VREDUCEPH—Perform Reduction Transformation on Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-652 Vol. 2CVREDUCEPH—Perform Reduction Trans formation on Packed FP16 Values
This instruction performs a reduction transformation of  the packed binary encoded FP16 values in the source 
operand (the second operand) and store the reduced result s in binary FP format to the destination operand (the 
first operand) under the writemask k1.
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source 
value, where M is a unsigned integer specified by imm8[7 :4]. Specifically, the reduction transformation can be 
expressed as:
dest = src − (ROUND(2M * src)) * 2−M
where ROUND() treats src, 2M, and their product as binary FP numbers with normalized sign ificand and biased 
exponents.
The magnitude of the reduced result can be expressed by considering src = 2p * man2, where ‘man2’ is the normal-
ized significand and ‘p’ is the unbiased exponent.
Then if RC=RNE: 0 ≤ |ReducedResult| ≤ 2−M−1.
Then if RC ≠ RNE: 0 ≤ |ReducedResult| < 2−M.
This instruction might end up with a precision exception se t. However, in case of SPE set (i.e., Suppress Precision 
This instruction may generate tiny non-zero result. If it does so, it does not report underflow exception, even if 
underflow exceptions are unmasked (UM flag in MXCSR register is 0).
For special cases, see Table 5-30.Opcode/
En64/32 
bit Mode 
EVEX.128.NP.0F3A.W0 56 /r /ib
VREDUCEPH  xmm1{k1}{z},  xmm2/
m128/m16bcst,  imm8A V/V AVX512-FP16 
AVX512VLPerform reduction transformation on packed 
FP16 values in xmm2/m128/m16bcst by 
subtracting a number of fraction bits specified by 
the imm8 field. Store the result in xmm1 subject to writemask k1.
EVEX.256.NP.0F3A.W0 56 /r /ib
VREDUCEPH  ymm1{k1}{z},  ymm2/
m256/m16bcst,  imm8A V/V AVX512-FP16 
FP16 values in ymm2/m256/m16bcst by 
subtracting a number of fraction bits specified by the imm8 field. Store the result in ymm1 subject 
EVEX.512.NP.0F3A.W0 56 /r /ib
VREDUCEPH  zmm1{k1}{z},  zmm2/
m512/m16bcst  {sae},  imm8A V/V AVX512-FP16 Perform reduction transformation on packed 
FP16 values in zmm2/m512/m16bcst by 
the imm8 field. Store the result in zmm1 subject to writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/AVREDUCEPH—Perform Reduction Transf ormation on Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-653Operation
def reduce_fp16(src, imm8):
nan := (src.exp = 0x1F) and (src.fraction != 0)if nan:
return QNAN(src)
m := imm8[7:4]rc := imm8[1:0]
rc_source := imm8[2]
spe := imm[3] // suppress precision exceptiontmp := 2^(-m) * ROUND(2^m * src, spe, rc_source, rc)tmp := src - tmp // using same RC, SPE controlsreturn tmp
VREDUCEPH dest{k1}, src, imm8 
ELSE:
DEST.fp16[i] := reduce_fp16(tsrc, imm8)
DEST[MAXVL-1:VL] := 0 Table 5-30. VREDUCEPH/VREDUCESH Special Cases
Input value Round Mode Returned Value
|Src1| < 2−M−1RNE Src1
|Src1|  < 2−MRU, Src1 > 0R o u n d ( S r c 1  − 2−M)1
RU, Src1  ≤ 0S r c 1
RD, Src1 ≥ 0S r c 1
RD, Src1  < 0R o u n d ( S r c 1  + 2−M)
Src1 =  ±0 or
Dest =  ±0 (Src1 ≠ ∞)NOT RD +0.0
RD −0.0
Src1 =  ±∞ Any +0.0
Src1 =  ±NAN Any QNaN (Src1)
NOTES:

ELSE:
Src1 =  ±0 or
RD −0.0
NOTES:
1. The Round(.) function uses rounding contro ls specified by (imm8[2]?  MXCSR.RC: imm8[1:0]).VREDUCEPH—Perform Reduction Transformation on Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-654 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VREDUCEPH __m128h _mm_mask_reduce_ph (__m12 8h src, __mmask8 k, __m128h a, int imm8);
VREDUCEPH __m128h _mm_maskz_reduce_ph (__mmask8 k, __m128h a, int imm8);
VREDUCEPH __m128h _mm_reduce_ph (__m128h a, int imm8);VREDUCEPH __m256h _mm256_mask_reduce_ph (__m256h src, __mmask16 k, __m256h a, int imm8);VREDUCEPH __m256h _mm256_maskz_reduce_ph (__mmask16 k, __m256h a, int imm8);VREDUCEPH __m256h _mm256_reduce_ph (__m256h a, int imm8);VREDUCEPH __m512h _mm512_mask_reduce_ph (__m512h src, __mmask32 k, __m512h a, int imm8);VREDUCEPH __m512h _mm512_maskz_reduce_ph (__mmask32 k, __m512h a, int imm8);VREDUCEPH __m512h _mm512_reduce_ph (__m512h a, int imm8);VREDUCEPH __m512h _mm512_mask_reduce_round_ph (__m512h sr c, __mmask32 k, __m512h a, int imm8, const int sae);
VREDUCEPH __m512h _mm512_maskz_reduce_round_ph (__m mask32 k, __m512h a, int imm8, const int sae);
VREDUCEPH __m512h _mm512_reduce_round_ph (__m512h a, int imm8, const int sae);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”VREDUCEPS—Perform Reduction Transfor mation on Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-655VREDUCEPS—Perform Reduction Transfor mation on Packed Float32 Values
Perform reduction transformation of the packed binary enco ded single-precision floating-point values in the source 
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Handling of special case of input values are listed in Table 5-29.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W0 56 /r ib
VREDUCEPS xmm1 {k1}{z}, 
AVX512DQPerform reduction transformation on packed single-precision 
a number of fraction bits specif ied by the imm8 field. Stores 
the result in xmm1 regi ster under writemask k1.
EVEX.256.66.0F3A.W0 56 /r ib
VREDUCEPS ymm1 {k1}{z}, 
EVEX.512.66.0F3A.W0 56 /r ib
VREDUCEPS zmm1 {k1}{z}, 
imm8A V/V AVX512DQ Perform reduction transformation on packed single-precision 
A Full ModRM:reg (w) ModRM:r/m (r) imm8 N/AVREDUCEPS—Perform Reduction Transfor mation on Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
5-656 Vol. 2COperation
ReduceArgumentSP(SRC[31:0], imm8[7:0])
{
// Check for NaNIF (SRC [31:0] = NAN) THEN
RETURN (Convert SRC[31:0] to QNaN); FI
RC source := imm[2];SPE := imm[3];// Suppress Precision ExceptionTMP[31:0] := 2
-M *{ROUND(2M*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
TMP[31:0] := SRC[31:0] – TMP[31:0]; // su btraction under the same RC,SPE controls
RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand}
VREDUCEPS 
THEN DEST[i+31:i] := ReduceAr gumentSP(SRC[31:0], imm8[7:0]);
ELSE DEST[i+31:i] := ReduceArgu mentSP(SRC[i+31:i], imm8[7:0]);
FI;
ELSE 
FI;
FI;
VREDUCEPS __m512 _mm512_mask_reduce_ps( __m512 a, int imm, int sae)
VREDUCEPS __m512 _mm512_mask_reduce_ps(__m512 s,  __mmask16 k, __m512 a, int imm, int sae)
VREDUCEPS __m512 _mm512_maskz_reduce_ps(__m mask16 k, __m512 a, int imm, int sae)
VREDUCEPS __m256 _mm256_mask_reduce_ps( __m256 a, int imm)VREDUCEPS __m256 _mm256_mask_reduce_ps(__m 256 s, __mmask8 k, __m256 a, int imm)
VREDUCEPS __m256 _mm256_maskz_reduce_ps(__mmask8 k, __m256 a, int imm)VREDUCEPS __m128 _mm_mask_reduce_ps( __m128 a, int imm)VREDUCEPS __m128 _mm_mask_reduce_ps(__m 128 s, __mmask8 k, __m128 a, int imm)
VREDUCEPS __m128 _mm_maskz_reduce_p s(__mmask8 k, __m128 a, int imm)
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).
See Table 2-46, “Type E2 Class Exception Conditions”; additionally:
#UD If EVEX.vvvv != 1111B.VREDUCESD—Perform a Reduction Transfor mation on a Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-657 VREDUCESD—Perform a Reduction Transfor mation on a Scalar Float64 Value  
Perform a reduction transformation of the binary encoded double precision floating-point value in the low qword 
element of the second source operand (the third operand)  and store the reduced result in binary floating-point 
format to the low qword element of the destination oper and (the first operand) under the writemask k1. Bits 
127:64 of the destination operand are copied from respec tive qword elements of the first source operand (the 
second operand). 
The operation is write masked.Handling of special case of input values are listed in Table 5-29.
Operation
{
TMP[63:0] := SRC[63:0] – TMP[63:0]; // subtraction under the same RC,SPE controlsRETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
}Opcode/
Mode 
Feature 
EVEX.LLIG.66.0F3A.W1 57
VREDUCESD xmm1 {k1}{z}, 
xmm2, xmm3/m64{sae}, 
imm8/r A V/V AVX512D
QPerform a reduction transformation on a scalar double precision 
floating-point value in xmm3/m64 by subtracting a number of 
fraction bits specified by the imm8 field. Also, upper double 
precision floating-point value (bits[127:64]) from xmm2 are copied to xmm1[127:64]. Stores the result in xmm1 register.

}Opcode/
Mode 
Feature 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVREDUCESD—Perform a Reduction Transfor mation on a Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
5-658 Vol. 2CVREDUCESD 
THEN DEST[63:0] := ReduceArgumentDP(SRC2[63:0], imm8[7:0])ELSE 
FI;
VREDUCESD __m128d _mm_mask_reduce_sd( __m128d a, __m128d b, int imm, int sae)
VREDUCESD __m128d _mm_mask_reduce_sd(__m128d s, __mma sk16 k, __m128d a, __m1 28d b, int imm, int sae)
VREDUCESD __m128d _mm_maskz_reduce_sd(__mmask16 k,  __m128d a, __m128d b, int imm, int sae)
See Table 2-47, “Type E3 Class Exception Conditions.”VREDUCESH—Perform Reduction Transf ormation on Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-659VREDUCESH—Perform Reduction Transf ormation on Scalar FP16 Value
This instruction performs a reduction transformation of the low binary encoded FP16 value in the source operand 
(the second operand) and store the reduced result in bi nary FP format to the low element of the destination 
operand (the first operand) under the writemask k1. For further details see the description of VREDUCEPH.
For special cases, see Table 5-30.
Operation
VREDUCESH dest{k1}, src, imm8 
dest.fp16[0] := reduce_fp16(src2.fp16[0], imm8) // see VREDUCEPH
VREDUCESH __m128h _mm_mask_reduce_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int imm8, const int sae);
VREDUCESH __m128h _mm_maskz_reduce_round_sh (__mmask8 k, __m128h a, __m128h b, int imm8, const int sae);
VREDUCESH __m128h _mm_reduce_round_sh (__m1 28h a, __m128h b, int imm8, const int sae);
VREDUCESH __m128h _mm_mask_reduce_sh (__m128h sr c, __mmask8 k, __m128h a, __m128h b, int imm8);
VREDUCESH __m128h _mm_maskz_reduce_sh (__mma sk8 k, __m128h a, __m128h b, int imm8);
VREDUCESH __m128h _mm_reduce_sh (__m128h a, __m128h b, int imm8);
En64/32 
bit Mode 
EVEX.LLIG.NP.0F3A.W0 57 /r /ib
VREDUCESH xmm1{k1}{z}, xmm2, 
xmm3/m16 {sae}, imm8A V/V AVX512-FP16 Perform a reduct ion transformation on the low 
binary encoded FP16 value in xmm3/m16 by 
the imm8 field. Store the result in xmm1 subject to writemask k1. Bits 127:16 from xmm2 are 
copied to xmm1[127:16]. 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)VREDUCESH—Perform Reduction Transf ormation on Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
5-660 Vol. 2COther Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”VREDUCESS—Perform a Reduction Transfor mation on a Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-661VREDUCESS—Perform a Reduction Transfor mation on a Scalar Float32 Value
Perform a reduction transformation of the binary encoded single-precision floating-point value in the low dword 
format to the low dword element of the destination oper and (the first operand) under the writemask k1. Bits 
127:32 of the destination operand are copied from respec tive dword elements of the first source operand (the 
Handling of special case of input values are listed in Table 5-29.
Operation
{
TMP[31:0] := SRC[31:0] – TMP[31:0]; // subtraction under the same RC,SPE controls
RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand}Opcode/
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W0 57 /r 
/ib
VREDUCESS xmm1 {k1}{z}, 
xmm2, xmm3/m32{sae}, imm8A V/V AVX512DQ Perform a reduction transformation on a scalar single-precision 
floating-point value in xmm3/m32 by subtracting a number of 
fraction bits specified by the imm8 field. Also, upper single-
precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32]. Stores the result in xmm1 register.
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVREDUCESS—Perform a Reduction Transfor mation on a Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
5-662 Vol. 2CVREDUCESS 
THEN DEST[31:0] := ReduceArgu mentSP(SRC2[31:0 ], imm8[7:0])
ELSE 
THEN DEST[31:0] = 0
FI;
VREDUCESS __m128 _mm_mask_reduce_ss( __m128 a, __m128 b, int imm, int sae)
VREDUCESS __m128 _mm_mask_reduce_ss(__m128 s, __m mask16 k, __m128 a, __m128 b, int imm, int sae)
VREDUCESS __m128 _mm_maskz_reduce_ss(__mmask16 k, __m128 a, __m128 b, int imm, int sae)
See Table 2-47, “Type E3 Class Exception Conditions.”VRNDSCALEPD—Round Packed Float64 Values to  Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-663VRNDSCALEPD—Round Packed Float64 Values to  Include a Given Number of Fraction Bits
Round the double precision floating-point values in th e source operand by the rounding mode specified in the 
immediate operand (see Figure 5-29) and places the result in the destination operand.
The destination operand (the first operand) is a ZMM/YM M/XMM register conditionally updated according to the 
writemask. The source operand (the second operan d) can be a ZMM/YMM/XMM register, a 512/256/128-bit 
memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.
The rounding process rounds the input to an integral valu e, plus number bits of fraction that are specified by 
imm8[7:4] (to be included in the result) and returns th e result as a double precision floating-point value.
It should be noticed that no overflow is induced while ex ecuting this instruction (although the source is scaled by 
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and

The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and 
shown in the “Immediate Control Description” figure belo w. Bit 3 of the immediate byte controls the processor 
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky 
rounding-mode value (immediate control table below li sts the encoded values for rounding-mode field).
rounding. 
The sign of the result of this instruction is preserved, including the sign of zero.The formula of the operation on ea ch data element for VRNDSCALEPD is
ROUND(x) = 2
-M*Round_to_INT(x*2M, round_ctrl), 
round_ctrl = imm[3:0];
M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W1 09 /r ib
VRNDSCALEPD xmm1 {k1}{z}, 
AVX512FRounds packed double precision floating-point values in 
xmm2/m128/m64bcst to a nu mber of fraction bits 
specified by the imm8 field. Stores the result in xmm1 
register. Under writemask.
EVEX.256.66.0F3A.W1 09 /r ib
VRNDSCALEPD ymm1 {k1}{z}, 
ymm2/m256/m64bcst to a nu mber of fraction bits 
specified by the imm8 field. Stores the result in ymm1 
EVEX.512.66.0F3A.W1 09 /r ib
VRNDSCALEPD zmm1 {k1}{z}, 
zmm2/m512/m64bcst{sae}, imm8A V/V AVX512F Rounds packed double precision floating-point values in 
zmm2/m512/m64bcst to a number of fraction bits 
specified by the imm8 field. Stores the result in zmm1 
register using writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) imm8 N/AVRNDSCALEPD—Round Packed Float64 Values to  Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
5-664 Vol. 2CVRNDSCALEPD is a more general form of the VEX-encode d VROUNDPD instruction. In  VROUNDPD, the formula of 
the operation on each element is
ROUND(x) = Round_to_INT(x, round_ctrl), 
Handling of special case of input values are listed in Table 5-31.
Operation
RoundToIntegerDP(SRC[6 3:0], imm8[7:0]) {
if (imm8[2] = 1)
rounding_direction := MXCSR:RC ; get round control from MXCSR
else
rounding_direction := imm8[1:0] ; get round control from imm8[1:0]
FIM := imm8[7:4] ; get the scaling factor
case (rounding_direction)
00: TMP[63:0] := round_to_nearest_even_integer(2
M*SRC[63:0])
01: TMP[63:0] := round_to_ equal_or_smalle r_integer(2M*SRC[63:0])
10: TMP[63:0] := round_to_equal_or_larger_integer(2M*SRC[63:0])
11: TMP[63:0] := round_to_nearest_smallest_magnitude_integer(2M*SRC[63:0])
ESAC
Dest[63:0] := 2-M* TMP[63:0] ; scale down back to 2-M
if (imm8[3] = 0) Then ; check SPE
if (SRC[63:0] != Dest[63:0]) Then ; check precision lost
set_precision() ; set #PE
FI;
FI;Figure 5-29.  Imm8 Controls for VRNDSCALEPD/SD/PS/SS
Table 5-31. VRNDSCALEPD/SD/PS/SS Special Cases
Returned value 
Src1=±inf Src1
Src1=±NAN Src1 converted to QNAN
Src1=±0 Src17 0 2 4 65 3 1
Imm8[7:4] : Number of fixed points to preserveRS
Imm8[1:0] = 01b : Round down
Imm8[1:0] = 10b : Round up
Imm8[1:0] = 11b : Truncateimm8 SPE
Imm8[2] = 0b : Use Imm8[1:0]Imm8[2] = 1b : Use MXCSRSuppress Precision Exception: Imm8[3] Imm8[3] = 0b : Use MXCSR exception maskImm8[3] = 1b : SuppressVRNDSCALEPD—Round Packed Float64 Values to  Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-665return(Dest[63:0])
}
VRNDSCALEPD (EVEX encoded versions) 
IF *src is a memory operand*
THEN TMP_SRC := BROADCAST64(SRC, VL, k1)ELSE TMP_SRC := SRC
FI;
THEN DEST[i+63:i] := RoundToInt egerDP((TMP_SRC[i+ 63:i], imm8[7:0])
ELSE 
FI;
FI;
VRNDSCALEPD __m512d _mm512_roundscale_pd( __m512d a, int imm);
VRNDSCALEPD __m512d _mm512_roundscale_round_pd( __m512d a, int imm, int sae);VRNDSCALEPD __m512d _mm512_mask_roundscale_pd( __m512d s, __mmask8 k, __m512d a, int imm);
VRNDSCALEPD __m512d _mm512_mask_roundscale_round_pd(__m5 12d s, __mmask8 k, __m512d  a, int imm, int sae);
VRNDSCALEPD __m512d _mm512_maskz_roundscale_pd( __mmask8 k, __m512d a, int imm);VRNDSCALEPD __m512d _mm512_maskz_roundscale_round_p d( __mmask8 k, __m512d a, int imm, int sae);
VRNDSCALEPD __m256d _mm256_roundscale_pd( __m256d a, int imm);VRNDSCALEPD __m256d _mm256_mask_roundscale_pd( __m256d s, __mmask8 k, __m256d a, int imm);
VRNDSCALEPD __m256d _mm256_maskz_roundscale_pd( __mmask8 k, __m256d a, int imm);VRNDSCALEPD __m128d _mm_roundscale_pd( __m128d a, int imm);VRNDSCALEPD __m128d _mm_mask_roundscale_pd( __m128d s, __mmask8 k, __m128d a, int imm);
VRNDSCALEPD __m128d _mm_maskz_roundscale_p d( __mmask8 k, __m128d a, int imm);
See Table 2-46, “Type E2 Class Exception Conditions.”VRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
5-666 Vol. 2CVRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of Fraction Bits
This instruction rounds the FP16 values in the source op erand by the rounding mode specified in the immediate 
operand (see Table 5-32) and places the result in the dest ination operand. The destination operand is conditionally 
imm8[7:4] (to be included in the result), and returns the result as an FP16 value.
Note that no overflow is induced while executing this in struction (although the source is scaled by the imm8[7:4] 
value).
The immediate operand also specifies control fields for the rounding operation. Three bit fields are defined and 
shown in Table 5-32, “Imm8 Controls for VRNDSCALEPH/VR NDSCALESH.” Bit 3 of the i mmediate byte controls the 
processor behavior for a precision exception, bit 2 selects the source of rounding mode control, and bits 1:0 specify a non-sticky rounding-mode value.
SNaN then it will be converted to a QNaN.
The sign of the result of this instruction is preserved, in cluding the sign of zero. Special cases are described in Table 
5-33.
The formula of the operation on each  data element for VRNDSCALEPH is 
−M *Round_to_INT(x * 2M, round_ctrl),
round_ctrl = imm[3:0];M=imm[7:4];
The operation of x * 2
M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).
If this instruction encoding’s SPE bit (bit 3) in th e immediate operand is 1, VRNDSCALEPH can set MXCSR.UE 
without MXCSR.PE.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.Opcode/
En64/32 
bit Mode 
EVEX.128.NP.0F3A.W0 08 /r /ib
VRNDSCALEPH  xmm1{k1}{z},  xmm2/
AVX512VLRound packed FP16 values in xmm2/m128/
m16bcst to a number of fr action bits specified by 
the imm8 field. Store the result in xmm1 subject 
EVEX.256.NP.0F3A.W0 08 /r /ib
VRNDSCALEPH  ymm1{k1}{z},  ymm2/
AVX512VLRound packed FP16 va lues in ymm2/m256/
the imm8 field. Store the result in ymm1 subject 
EVEX.512.NP.0F3A.W0 08 /r /ib
VRNDSCALEPH  zmm1{k1}{z},  zmm2/
m512/m16bcst  {sae},  imm8A V/V AVX512-FP16 Round packed FP16 values in zmm2/m512/
the imm8 field. Store the result in zmm1 subject 
A Full ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/AVRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-667Operation
def round_fp16_to_integer(src, imm8):
if imm8[2] = 1:
rounding_direction := MXCSR.RC
else:
rounding_direction := imm8[1:0]
m := imm8[7:4] // scaling factor
tsrc1 := 2^m * srcif rounding_direction = 0b00:
tmp := round_to_nearest_even_integer(trc1)
else if rounding_direction = 0b01:
tmp := round_to_equal_or_smaller_integer(trc1)

else:
else if rounding_direction = 0b10:
tmp := round_to_equal_or_larger_integer(trc1)
else if rounding_direction = 0b11:
tmp := round_to_smallest _magnitude_i nteger(trc1)
dst := 2^(-m) * tmpif imm8[3]==0: // check SPE
if src != dst:
MXCSR.PE := 1
return dst Table 5-32. Imm8 Controls for VRNDSCALEPH/VRNDSCALESH
Imm8 Bits Description
imm8[7:4] Number of fixed points to preserve.
imm8[3] Suppress Precision Exception (SPE)
0b00: Implies use of MXCSR exception mask.
0b01: Implies suppress.
imm8[2] Round Select (RS)
0b00: Implies use of imm8[1:0].
0b01: Implies use of MXCSR.
imm8[1:0] Round Control Override:
0b00: Round nearest even.0b01: Round down.
0b10: Round up.
0b11: Truncate.
Table 5-33. VRNDSCALEPH/VRNDSCALESH Special Cases
Input Value Returned Value
Src1 = ±∞ Src1
Src1 = ±NaN Src1 converted to QNaN
Src1 = ±0S r c 1VRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
5-668 Vol. 2CVRNDSCALEPH dest{k1}, src, imm8
ELSE:
DEST.fp16[i] := round_fp16_to_integer(tsrc, imm8)
VRNDSCALEPH __m128h _mm_mask_roundscale_ph (__m128h src, __mmask8 k, __m128h a, int imm8);
VRNDSCALEPH __m128h _mm_maskz_roundscale_ph (__mmask8 k, __m128h a, int imm8);VRNDSCALEPH __m128h _mm_roundscale_ph (__m128h a, int imm8);VRNDSCALEPH __m256h _mm256_mask_roundscale_ph (__m 256h src, __mmask16 k, __m256h a, int imm8);
VRNDSCALEPH __m256h _mm256_maskz_roundscale_ph (__mmask16 k, __m256h a, int imm8);VRNDSCALEPH __m256h _mm256_roundscale_ph (__m256h a, int imm8);VRNDSCALEPH __m512h _mm512_mask_roundscale_ph (__m 512h src, __mmask32 k, __m512h a, int imm8);
VRNDSCALEPH __m512h _mm512_maskz_roundscale_ph (__mmask32 k, __m512h a, int imm8);VRNDSCALEPH __m512h _mm512_roundscale_ph (__m512h a, int imm8);VRNDSCALEPH __m512h _mm512_mask_roundscale_round_ph (__m512h  src, __mmask32 k, __m512h a, int imm8, const int sae);
VRNDSCALEPH __m512h _mm512_maskz_roundscale_round_ph (__mmask32 k, __m512h a, int imm8, const int sae);
VRNDSCALEPH __m512h _mm512_roundscale_round_ ph (__m512h a, int imm8, const int sae);
Invalid, Underflow, Precision.
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”VRNDSCALEPS—Round Packed Float32 Values to  Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-669VRNDSCALEPS—Round Packed Float32 Values to  Include a Given Number of Fraction Bits
Round the single-precision floating-point values in th e source operand by the rounding mode specified in the 
The destination operand (the first operand) is a ZMM regi ster conditionally updated according to the writemask. 
The source operand (the second operand) can be a ZMM register, a 512-bit memory location, or a 512-bit vector 
imm8[7:4] (to be included in the result) and returns th e result as a single-precision floating-point value.
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.
The formula of the operation on ea ch data element for VRNDSCALEPS is
ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl), 
The operation of x*2M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).
VRNDSCALEPS is a more general form of the VEX-encode d VROUNDPS instruction. In VROUNDPS, the formula of 
ROUND(x) = Round_to_INT(x, round_ctrl), round_ctrl = imm[3:0];Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F3A.W0 08 /r ib
VRNDSCALEPS xmm1 {k1}{z}, 
AVX512FRounds packed single-precision  floating-point values in 
xmm2/m128/m32bcst to a nu mber of fraction bits 
EVEX.256.66.0F3A.W0 08 /r ib
VRNDSCALEPS ymm1 {k1}{z}, 
ymm2/m256/m32bcst to a nu mber of fraction bits 
EVEX.512.66.0F3A.W0 08 /r ib
VRNDSCALEPS zmm1 {k1}{z}, 
zmm2/m512/m32bcst{sae}, imm8A V/V AVX512F Rounds packed single-pre cision floating-point values in 
zmm2/m512/m32bcst to a number of fraction bits 
register using writemask.
A Full ModRM:reg (w) ModRM:r/m (r) imm8 N/AVRNDSCALEPS—Round Packed Float32 Values to  Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
5-670 Vol. 2CNote: EVEX.vvvv is reserved and must be  1111b, otherwise instructions will #UD.
Operation
RoundToIntegerSP(SRC[31:0], imm8[7:0]) {
else
00: TMP[31:0] := round_to_nearest_even_integer(2
M*SRC[31:0])
01: TMP[31:0] := round_to_ equal_or_smalle r_integer(2M*SRC[31:0])
10: TMP[31:0] := round_to_equal_or_larger_integer(2M*SRC[31:0])
11: TMP[31:0] := round_to_nearest_smallest_magnitude_integer(2M*SRC[31:0])
ESAC;
Dest[31:0] := 2-M* TMP[31:0] ; scale down back to 2-M
if (SRC[31:0] != Dest[31:0]) Then ; check precision lost
FI;
FI;return(Dest[31:0])
}
VRNDSCALEPS (EVEX encoded versions) 
(KL, VL) = (4, 128), (8, 256), (16, 512)IF *src is a memory operand*
THEN TMP_SRC := BROADCAST32(SRC, VL, k1)ELSE TMP_SRC := SRC
FI;
THEN DEST[i+31:i] := RoundToInteg erSP(TMP_SRC[i+31: i]), imm8[7:0])
ELSE 
FI;
FI;
ENDFOR;DEST[MAXVL-1:VL] := 0VRNDSCALEPS—Round Packed Float32 Values to  Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-671Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALEPS __m512 _mm512_roundscale_ps( __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_roundscale_ro und_ps( __m512 a, int imm, int sae);
VRNDSCALEPS __m512 _mm512_mask_roundscale_ps(__m 512 s, __mmask16 k, __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_mask_roun dscale_round_ps(__m512 s,  __mmask16 k, __m512 a,  int imm, int sae);
VRNDSCALEPS __m512 _mm512_maskz_roundscale_ ps( __mmask16 k, __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_maskz_roundscale_round_ ps( __mmask16 k, __m512 a,  int imm, int sae);
VRNDSCALEPS __m256 _mm256_roundscale_ps( __m256 a, int imm);VRNDSCALEPS __m256 _mm256_mask_roundscale_ps( __m256 s, __mmask8 k, __m256 a, int imm);
VRNDSCALEPS __m256 _mm256_maskz_roundscal e_ps( __mmask8 k, __m256 a, int imm);
VRNDSCALEPS __m128 _mm_roundsca le_ps( __m256 a, int imm);
VRNDSCALEPS __m128 _mm_mask_roundscale_ps(__m 128 s, __mmask8 k, __m128 a, int imm);
VRNDSCALEPS __m128 _mm_maskz_roundscale_p s( __mmask8 k, __m128 a, int imm);
See Table 2-46, “Type E2 Class Exception Conditions.”VRNDSCALESD—Round Scalar Float64 Value to Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
5-672 Vol. 2CVRNDSCALESD—Round Scalar Fl oat64 Value to Include a Given Number of Fraction Bits

Rounds a double precision floating-point value in the low quadword (see Figure 5-29) element of the second source 
operand (the third operand) by the rounding mode specifie d in the immediate operand and places the result in the 
corresponding element of the destination operand (the fi rst operand) according to the writemask. The quadword 
element at bits 127:64 of the destination is copied from the first source operand (the second operand).
The destination and first source operands are XMM register s, the 2nd source operand can be an XMM register or 
memory location. Bits MAXVL-1:128 of the destination register are cleared.
rounding.
The formula of the operation for VRNDSCALESD is
VRNDSCALESD is a more general form of the VEX-encode d VROUNDSD instruction. In VROUNDSD, the formula of 
the operation is
ROUND(x) = Round_to_INT(x, round_ctrl), round_ctrl = imm[3:0];
EVEX encoded version: The source operand is a XMM regist er or a 64-bit memory location. The destination operand 
is a XMM register.
Handling of special case of input values are listed in Table 5-31.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W1 0B /r ib
VRNDSCALESD xmm1 {k1}{z}, xmm2, 
xmm3/m64{sae}, imm8A V/V AVX512F Rounds scalar double precision floating-point value in 
xmm3/m64 to a number of fraction bits specified by the 
imm8 field. Stores the re sult in xmm1 register.
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) imm8VRNDSCALESD—Round Scalar Float64 Value to Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-673Operation
else
11: TMP[63:0] := round_to_neares t_smallest_magni tude_integer(2M*SRC[63:0])
ESAC
FI;
FI;return(Dest[63:0])
}
VRNDSCALESD (EVEX encoded version)
THEN DEST[63:0] := RoundToIntegerDP(SRC2[63:0], Zero_upper_imm[7:0])ELSE 
FI;
VRNDSCALESD __m128d _mm_roundscale_sd ( __m128d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_roundscale_round_sd ( __m128d a, __m128d b, int imm, int sae);
VRNDSCALESD __m128d _mm_mask_roundsc ale_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_mask_rou ndscale_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm, int sae);
VRNDSCALESD __m128d _mm_maskz_ro undscale_sd ( __mmask8 k, __m1 28d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_maskz_roundsca le_round_sd ( __mmask8 k, __m128d a, __m128d b, int imm, int sae);
See Table 2-47, “Type E3 Class Exception Conditions.”VRNDSCALESH—Round Scalar FP16 Value to In clude a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
5-674 Vol. 2CVRNDSCALESH—Round Scalar FP16 Value to Include a Given Number of Fraction Bits
This instruction rounds the low FP16 value in the second  source operand by the rounding mode specified in the 
immediate operand (see Table 5-32) and places the result in the destination operand.
imm8[7:4] (to be included in the result), and returns the result as a FP16 value.
value).
processor behavior for a precision exception, bit 2 selects the source of rounding mode control, and bits 1:0 specify 
a non-sticky rounding-mode value.
5-33.
If this instruction encoding’s SPE bit (bit 3) in th e immediate operand is 1, VRNDSCALESH can set MXCSR.UE 
The formula of the operation on ea ch data element for VRNDSCALESH is:
ROUND(x) = 2−M *Round_to_INT(x * 2M, round_ctrl), 
The operation of x * 2M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).
Operation
VRNDSCALESH dest{k1}, src1, src2, imm8
DEST.fp16[0] := round_fp16_to_integer( src2.fp16[0], imm8) // see VRNDSCALEPH
DEST[127:16] = src1[127:16]
En64/32 
bit Mode 
EVEX.LLIG.NP.0F3A.W0 0A /r /ib
VRNDSCALESH xmm1{k1}{z}, xmm2, 
xmm3/m16 {sae}, imm8A V/V AVX512-FP16 Round the low FP16 value in xmm3/m16 to a 
number of fraction bits  specified by the imm8 
field. Store the result in xmm1 subject to 
writemask k1. Bits 127:16 from xmm2 are copied to xmm1[127:16]. 
A Scalar ModRM:reg (w) VEX.vvvv  (r) ModRM:r/m (r) imm8 (r)VRNDSCALESH—Round Scalar FP16 Value to In clude a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-675Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALESH __m128h _mm_ma sk_roundscale_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int imm8, const int 
sae);
VRNDSCALESH __m128h _mm_mask z_roundscale_round_sh (__mma sk8 k, __m128h a, __m128h b, int imm8, const int sae);
VRNDSCALESH __m128h _mm_roundsca le_round_sh (__m128h a, __m128h b, int imm8, const int sae);
VRNDSCALESH __m128h _mm_mask _roundscale_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int imm8);
VRNDSCALESH __m128h _mm_ maskz_roundscale_sh (__m mask8 k, __m128h a, __m128h b, int imm8);
VRNDSCALESH __m128h _mm_roundscale_sh (__m128h a, __m128h b, int imm8);
EVEX-encoded instructions, see Table 2-47,  “Type E3 Class Exception Conditions.”VRNDSCALESS—Round Scalar Float32 Value to Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
5-676 Vol. 2CVRNDSCALESS—Round Scalar Float32 Value to  Include a Given Number of Fraction Bits
Rounds the single-precision floating-point value in the lo w doubleword element of the second source operand (the 
third operand) by the rounding mode sp ecified in the immediate operand (see Figure 5-29) and places the result in

third operand) by the rounding mode sp ecified in the immediate operand (see Figure 5-29) and places the result in 
the corresponding element of the destination operand (the first operand) according to the writemask. The double-
word elements at bits 127:32 of the destination are copi ed from the first source operand (the second operand).
rounding-mode value (immediate control tables below lists the encoded values for rounding-mode field).
rounding.
The formula of the operation for VRNDSCALESS is
The operation of x*2
VRNDSCALESS is a more general form of the VEX-encode d VROUNDSS instruction. In VROUNDSS, the formula of 
EVEX encoded version: The source operand is a XMM regist er or a 32-bit memory location. The destination operand 
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F3A.W0 0A /r ib
VRNDSCALESS xmm1 {k1}{z}, xmm2, 
xmm3/m32{sae}, imm8A V/V AVX512F Rounds scalar single-precision floating-point value in 
xmm3/m32 to a number of fraction bits specified by the 
imm8 field. Stores the resu lt in xmm1 re gister under 
A Tuple1 Scalar ModRM:reg (w) E VEX.vvvv (r) ModRM:r/m (r) N/AVRNDSCALESS—Round Scalar Float32 Value to Include a Given Number of Fraction BitsINSTRUCTION SET REFERENCE, V
Vol. 2C 5-677Operation
RoundToIntegerSP(SRC[ 31:0], imm8[7:0]) {
else
11: TMP[31:0] := round_to_neares t_smallest_magni tude_integer(2M*SRC[31:0])
ESAC;
FI;
}
VRNDSCALESS (EVEX encoded version)
THEN DEST[31:0] := RoundToIntegerSP (SRC2[31:0], Zero_upper_imm[7:0])
ELSE 
FI;
VRNDSCALESS __m128 _mm_roundscale_ss ( __m128 a, __m128 b, int imm);
VRNDSCALESS __m128 _mm_roundscale_round_ss ( __m128 a, __m128 b, int imm, int sae);
VRNDSCALESS __m128 _mm_mask_round scale_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRNDSCALESS __m128 _mm_mask_roundscal e_round_ss (__m128 s, __mmask8 k, __m 128 a, __m128 b, int imm, int sae);
VRNDSCALESS __m128 _mm_maskz_roundscale_ss ( __mmask8 k, __m128 a, __m128 b, int imm);VRNDSCALESS __m128 _mm_maskz_roundscale_round_ss ( __ mmask8 k, __m128 a, __m128 b, int imm, int sae);
Invalid, Precision.If SPE is enabled, precision ex ception is not reported (regardless of MXCSR exception mask).
See Table 2-47, “Type E3 Class Exception Conditions.”VRSQRT14PD—Compute Approximate Reciprocals of  Square Roots of Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
5-678 Vol. 2CVRSQRT14PD—Compute Approximate Reciprocal s of Square Roots of Packed Float64 Values
This instruction performs a SIMD computation of the ap proximate reciprocals of the square roots of the eight 
packed double precision floating-point values in the sour ce operand (the second operand) and stores the packed 
double precision floating-point results in the destination operand (the first operand) according to the writemask. 
The maximum relative error for this approximation is less than 2-14. 
EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit 
vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally 
updated using writemask k1. 
broadcasted from a 64-bit memory location. The destinatio n operand is a YMM register, conditionally updated using 
broadcasted from a 64-bit memory location. The destinatio n operand is a XMM register, conditionally updated using 
The VRSQRT14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source 
value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an + ∞ then +ZERO 
value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated 
correctly and performs the approximatio n with the specified masked response. When a source value is a negative 
value (other than 0.0) a floating-point QNaN_indefinite is  returned. When a source value is an SNaN or QNaN, the 
SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.Note: EVEX.vvvv is reserved and must be  1111b, otherwise instructions will #UD.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2 .Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W1 4E /r
VRSQRT14PD xmm1 {k1}{z}, 
AVX512FComputes the approximate reciprocal square roots of the 
packed double precision floating-point values in 
xmm2/m128/m64bcst and stores the results in xmm1. 
Under writemask.
EVEX.256.66.0F38.W1 4E /r
VRSQRT14PD ymm1 {k1}{z}, 
ymm2/m256/m64bcst and stores the results in ymm1. 
EVEX.512.66.0F38.W1 4E /r
VRSQRT14PD zmm1 {k1}{z}, 
zmm2/m512/m64bcstA V/V AVX512F Computes the approximate reciprocal square roots of the 
zmm2/m512/m64bcst and stores the results in zmm1 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVRSQRT14PD—Compute Approximate Reciprocals of  Square Roots of Packed Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-679Operation
VRSQRT14PD (EVEX encoded versions) 
THEN DEST[i+63:i] := APPROX IMATE(1.0/ SQRT(SRC[63:0]));
ELSE DEST[i+63:i] := APPROX IMATE(1.0/ SQRT(SRC[i+63:i]));
FI;
ELSE 
FI;
FI;
ENDFOR;
VRSQRT14PD __m512d _mm512_rsqrt14_pd( __m512d a);
VRSQRT14PD __m512d _mm512_mask_rsqrt14_pd(__m512d s, __mmask8 k, __m512d a);VRSQRT14PD __m512d _mm512_maskz_rsq rt14_pd( __mmask8 k, __m512d a);

FI;
ELSE 
FI;
FI;
ENDFOR;
VRSQRT14PD __m256d _mm256_rsqrt14_pd( __m256d a);VRSQRT14PD __m256d _mm512_mask_rsqrt14_pd(__m256d s, __mmask8 k, __m256d a);VRSQRT14PD __m256d _mm512_maskz_rsq rt14_pd( __mmask8 k, __m256d a);
VRSQRT14PD __m128d _mm_rsqrt14_pd( __m128d a);VRSQRT14PD __m128d _mm_mask_rsqrt14_p d(__m128d s, __mmask8 k, __m128d a);
VRSQRT14PD __m128d _mm_maskz_rsqrt14_pd( __mmask8 k, __m128d a);
None.
See Table 2-49, “Type E4 Class Exception Conditions.”Table 5-34. VRSQRT14PD Special Cases
Any denormal Normal Cannot generate overflowX = 2
-2n2n
X < 0 QNaN_Indefinite Including -INFX = -0 -INFX = +0 +INF
X = +INF +0VRSQRT14SD—Compute Approximate Reciprocal of  Square Root of Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
5-680 Vol. 2CVRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value
Computes the approximate reciprocal of the square roots of  the scalar double precision floating-point value in the 
low quadword element of the source operand (the second  operand) and stores the result in the low quadword 
element of the destination operand (the first operand) a ccording to the writemask. The maximum relative error for 
this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory location. The 
destination operand is an XMM register. 
Bits (127:64) of the XMM register destination are copied fr om corresponding bits in the first source operand. Bits 
The VRSQRT14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source 
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2 .
Operation
VRSQRT14SD (EVEX version)
THEN DEST[63:0] := APPROXIMATE(1.0/ SQRT(SRC2[63:0]))ELSE 
FI;
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W1 4F /r
VRSQRT14SD xmm1 {k1}{z}, 
xmm2, xmm3/m64A V/V AVX512F Computes the approximate reciprocal square root of the 
scalar double precision floating-point value in xmm3/m64 
and stores the result in the low quadword element of xmm1 
using writemask k1. Bits[127:64] of xmm2 is copied to xmm1[127:64]. 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVRSQRT14SD—Compute Approximate Reciprocal of  Square Root of Scalar Float64 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-681Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14SD __m128d _mm_rsqrt14_sd( __m128d a, __m128d b);
VRSQRT14SD __m128d _mm_mask_rsqrt14_sd(__m128 d s, __mmask8 k, __m128d a, __m128d b);
VRSQRT14SD __m128d _mm_maskz_rsqrt14_sd( __mmask8d m, __m128d a, __m128d b);
None.
See Table 2-51, “Type E5 Class Exception Conditions.”Table 5-35. VRSQRT14SD Special Cases
Any denormal Normal Cannot generate overflow
X = 2-2n2n
X < 0 QNaN_Indefinite Including -INF
X = -0 -INF
X = +0 +INFX = +INF +0VRSQRT14PS—Compute Approximate Reciprocals of  Square Roots of Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
5-682 Vol. 2CVRSQRT14PS—Compute Approximat e Reciprocals of Square Root s of Packed Float32 Values
This instruction performs a SIMD computation of the appr oximate reciprocals of the square roots of 16 packed 
single-precision floating-point values in the source operand (the second operand) and stores the packed single-
precision floating-point results in the destination operan d (the first operand) according to the writemask. The 
maximum relative error for this approximation is less than 2-14. 
EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location or a 512-bit 
vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally 
broadcasted from a 32-bit memory location. The destinatio n operand is a YMM register, conditionally updated using 
broadcasted from a 32-bit memory location. The destinatio n operand is a XMM register, conditionally updated using 
The VRSQRT14PS instruction is not affected by the roundi ng control bits in the MXCSR register. When a source 
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 4E /r
VRSQRT14PS xmm1 {k1}{z}, 
packed single-precision floating-point values in 
xmm2/m128/m32bcst and stores the results in xmm1. 
EVEX.256.66.0F38.W0 4E /r
VRSQRT14PS ymm1 {k1}{z}, 
ymm2/m256/m32bcst and stores the results in ymm1. 
EVEX.512.66.0F38.W0 4E /r
VRSQRT14PS zmm1 {k1}{z}, 
zmm2/m512/m32bcstA V/V AVX512F Computes the approximate reciprocal square roots of the 
zmm2/m512/m32bcst and stores the results in zmm1. Under 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVRSQRT14PS—Compute Approximate Reciprocals of  Square Roots of Packed Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-683Operation
VRSQRT14PS (EVEX encoded versions) 
THEN DEST[i+31:i] := APPROX IMATE(1.0/ SQRT(SRC[31:0]));
ELSE DEST[i+31:i] := APPROX IMATE(1.0/ SQRT(SRC[i+31:i]));
FI;
ELSE 
FI;
FI;
ENDFOR;
VRSQRT14PS __m512 _mm512_rsqrt14_ps( __m512 a);
VRSQRT14PS __m512 _mm512_mask_rsqrt14_ps(__m512 s, __mmask16 k, __m512 a);VRSQRT14PS __m512 _mm512_maskz_rsqrt14_ps( __mmask16 k, __m512 a);VRSQRT14PS __m256 _mm256_rsqrt14_ps( __m256 a);VRSQRT14PS __m256 _mm256_mask_rsqrt14_ps(__m256 s, __mmask8 k, __m256 a);VRSQRT14PS __m256 _mm256_maskz_rsqrt14_ps( __mmask8 k, __m256 a);VRSQRT14PS __m128 _mm_rsqrt14_ps( __m128 a);VRSQRT14PS __m128 _mm_mask_rsqrt14_ps(__m128 s, __mmask8 k, __m128 a);VRSQRT14PS __m128 _mm_maskz_rsqrt14_ps( __mmask8 k, __m128 a);
None.
See Table 2-21, “Type 4 Class Exception Conditions.”Table 5-36. VRSQRT14PS Special Cases
-2n2n

FI;
FI;
ENDFOR;
None.
-2n2n
X = +INF +0VRSQRT14SS—Compute Approximate Reciprocal of  Square Root of Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
5-684 Vol. 2CVRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value
Computes of the approximate reciprocal of the square root of the scalar single-precision floating-point value in the 
low doubleword element of the source operand (the second  operand) and stores the result in the low doubleword 
Bits (127:32) of the XMM register destination are copied fr om corresponding bits in the first source operand. Bits 
The VRSQRT14SS instruction is not affected by the roundin g control bits in the MXCSR register. When a source 
value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an ∞, zero with the 
sign of the source value is returned. A denormal source va lue is treated as zero only if DAZ bit is set in MXCSR. 
Otherwise it is treated correctly and performs the appr oximation with the specified masked response. When a 
source value is a negative value (other than 0.0) a floating -point indefinite is returned. When a source value is an 
SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.
Operation
VRSQRT14SS (EVEX version)
THEN DEST[31:0] := APPROXIMATE(1.0/ SQRT(SRC2[31:0]))ELSE 
FI;
FI;DEST[127:32] := SRC1[127:32]
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W0 4F /r
VRSQRT14SS xmm1 {k1}{z}, 
xmm2, xmm3/m32A V/V AVX512F Computes the approximate reciprocal square root of the 
scalar single-precision floa ting-point value in xmm3/m32 
and stores the result in th e low doubleword element of 
xmm1 using writemask k1. Bits[127:32] of xmm2 is copied to xmm1[127:32]. 
A Tuple1 Scalar ModRM:reg (w) V EX.vvvv (r) ModRM:r/m (r) N/AVRSQRT14SS—Compute Approximate Reciprocal of  Square Root of Scalar Float32 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-685Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14SS __m128 _mm_rsqrt14_ss( __m128 a, __m128 b);
VRSQRT14SS __m128 _mm_mask_rsqrt14_ss(__m 128 s, __mmask8 k, __m128 a, __m128 b);
VRSQRT14SS __m128 _mm_maskz_rsqrt14_ ss( __mmask8 k, __m128 a, __m128 b);
None.
See Table 2-51, “Type E5 Class Exception Conditions.”Table 5-37. VRSQRT14SS Special Cases
X = 2-2n2n
X = -0 -INF
X = +0 +INFX = +INF +0VRSQRTPH—Compute Reciprocals of Square Roots of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-686 Vol. 2CVRSQRTPH—Compute Reciprocals of Squa re Roots of Packed FP16 Values
This instruction performs a SIMD computation of the a pproximate reciprocals square-root of 8/16/32 packed FP16 
floating-point values in the source operand (the second op erand) and stores the packed FP16 floating-point results 
in the destination operand.
The maximum relative error for this approximation is less than 2−11 + 2−14. For special cases, see Table 5-38.
En64/32 
bit Mode 
EVEX.128.66.MAP6.W0  4E /r
VRSQRTPH  xmm1{k1}{z},  xmm2/
AVX512VLCompute the approximate reciprocals of the 
square roots of packed FP16 values in xmm2/
m128/m16bcst and store the result in xmm1 
EVEX.256.66.MAP6.W0  4E /r
VRSQRTPH  ymm1{k1}{z},  ymm2/
square roots of packed FP16 values in ymm2/
m256/m16bcst and store the result in ymm1 
EVEX.512.66.MAP6.W0  4E /r
VRSQRTPH  zmm1{k1}{z},  zmm2/
m512/m16bcstA V/V AVX512-FP16 Compute the approximate reciprocals of the 
square roots of packed FP16 values in zmm2/
m512/m16bcst and store the result in zmm1 
Table 5-38. VRSQRTPH/VRSQRTSH Special Cases
Input value Reset Value CommentsAny denormal Normal Cannot generate overflow
X = 2
−2n2n
X < 0 QNaN_Indefinite Including −∞
X = −0 −∞
X = +0 +∞
X = +∞ +0VRSQRTPH—Compute Reciprocals of Sq uare Roots of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-687Operation
VRSQRTPH dest{k1}, src 
ELSE:
DEST.fp16[i] := APPROXIM ATE(1.0 / SQRT(tsrc) )
VRSQRTPH __m128h _mm_mask_rsqrt_ph ( __m128h src, __mmask8 k, __m128h a);
VRSQRTPH __m128h _mm_maskz_rsqr t_ph (__mmask8 k, __m128h a);
VRSQRTPH __m128h _mm_rsqrt_ph (__m128h a);VRSQRTPH __m256h _mm256_mask_rsqrt_ph (__m256h src, __mmask16 k, __m256h a);VRSQRTPH __m256h _mm256_maskz_rsqrt _ph (__mmask16 k, __m256h a);
VRSQRTPH __m256h _mm256_rsqrt_ph (__m256h a);VRSQRTPH __m512h _mm512_mask_rsqrt_ph (__m512h src, __mmask32 k, __m512h a);VRSQRTPH __m512h _mm512_maskz_rsqrt _ph (__mmask32 k, __m512h a);
VRSQRTPH __m512h _mm512_rsqrt_ph (__m512h a);
None.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”VRSQRTSH—Compute Approximate Reciprocal of Square Root of Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
5-688 Vol. 2CVRSQRTSH—Compute Approximate Reciprocal  of Square Root of Scalar FP16 Value
This instruction performs the computation of the approxim ate reciprocal square-root of the low FP16 value in the 
second source operand (the third operand) and stores the result in the low word elemen t of the destination operand 
(the first operand) according to the writemask k1.
The maximum relative error for this approximation is less than 2−11 + 2−14.
MAXVL−1:128 of the destination operand are zeroed.
For special cases, see Table 5-38.
Operation
VRSQRTSH dest{k1}, src1, src2
DEST.fp16[0] := APPROXIMATE(1.0 / SQRT(src2.fp16[0]))
VRSQRTSH __m128h _mm_mask_rsqrt_sh (__m128h  src, __mmask8 k, __m128h a, __m128h b);
VRSQRTSH __m128h _mm_maskz_rsqrt_sh (__mmask8 k, __m128h a, __m128h b);
VRSQRTSH __m128h _mm_rsqrt_sh (__m128h a, __m128h b);
None.
En64/32 
bit Mode 
EVEX.LLIG.66.MAP6.W0 4F /r
VRSQRTSH xmm1{k1}{z}, xmm2, 
xmm3/m16A V/V AVX512-FP16 Compute  the approximate reciprocal square root 
of the FP16 value in xmm3/m16 and store the 
result in the low word element of xmm1 subject 
to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVSCALEFPD—Scale Packed Float64 Values With Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-689VSCALEFPD—Scale Packed Float64 Values With Float64 Values
Performs a floating-point scale of the packed double precis ion floating-point values in the first source operand by 
multiplying them by 2 to the power of the double prec ision floating-point values in second source operand.
The equation of this operation is given by:
zmm1 := zmm2*2floor(zmm3).
Floor(zmm3) means maximum integer value ≤ zmm3.
If the result cannot be represented in double precision, then the proper overflow response (for positive scaling

If the result cannot be represented in double precision, then the proper overflow response (for positive scaling 
operand), or the proper underflow response (for negative  scaling operand) is issued. The overflow and underflow 
responses are dependent on the rounding mode (for IEEE -compliant rounding), as well as on other settings in 
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
The first source operand is a ZMM/YMM/XMM register. Th e second source operand is a ZMM/YMM/XMM register, a 
512/256/128-bit memory location or a 512/256/128-bit ve ctor broadcasted from a 64-bit memory location. The 
destination operand is a ZMM/YMM/XMM register  conditionally updated with writemask k1.
Handling of special-case input values are listed in Table 5-39 and Table 5-40.
Table 5-39. VSCALEFPD/SD/PS/SS Special CasesOpcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W1 2C /r 
VSCALEFPD xmm1 {k1}{z}, xmm2, 
xmm3/m128/m64bcstAV / V A V X 5 1 2 V L
AVX512FScale the packed double precision floating-point values in 
xmm2 using values from xmm3/m128/m64bcst. Under 
EVEX.256.66.0F38.W1 2C /r 
VSCALEFPD ymm1 {k1}{z}, ymm2, 
ymm3/m256/m64bcstAV / V A V X 5 1 2 V L
ymm2 using values from ymm3/m256/m64bcst. Under writemask k1.
EVEX.512.66.0F38.W1 2C /r 
VSCALEFPD zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst{er}A V/V AVX512F Scale the packed double precision floating-point values in 
zmm2 using values from zmm3/m512/m64bcst. Under 
A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Src2 Set IE
±NaN +Inf -Inf 0/Denorm/Norm
Src1 ±QNaN QNaN(Src1) +INF +0 QNaN(Src1) IF either source is SNAN
±SNaN QNaN(Src1) QNaN(Src1) QNaN(Src1) QNaN(Src1) YES
±Inf QNaN(Src2) Src1 QNaN_Indefinite Src1 IF Src2 is SNAN or -INF
±0 QNaN(Src2) QNaN_Indefinite Src1 Src1 IF Src2 is SNAN or +INFDenorm/Norm QNaN(Src2) ±INF (Src1 sign) ±0 (S rc1 sign) Compute Result IF Src2 is SNANVSCALEFPD—Scale Packed Float64 Values With Float64 ValuesINSTRUCTION SET REFERENCE, V
5-690 Vol. 2COperation
SCALE(SRC1, SRC2)
{TMP_SRC2 := SRC2TMP_SRC1 := SRC1IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0/* SRC2 is a 64 bits floating-point value */DEST[63:0] := TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))}VSCALEFPD (EVEX encoded versions)(KL, VL) = (2, 128), (4, 256), (8, 512)IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)
THEN
ELSE 
THEN DEST[i+63:i] := SCALE(SRC1[i+63:i], SRC2[63:0]);ELSE DEST[i+63:i] := SCALE(SRC1[i+63:i], SRC2[i+63:i]);
FI;
ELSE 
FI
FI;
ENDFORDEST[MAXVL-1:VL] := 0Table 5-40. Additional VSCALEFPD/SD Special Cases
Special Case  Returned value Faults
|result| < 2-1074±0 or ±Min-Denormal (Src1 sign) Underflow
|result| ≥ 21024±INF (Src1 sign) or ±Max-n ormal (Src1 sign) OverflowVSCALEFPD—Scale Packed Float64 Values With Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-691Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFPD __m512d _mm512_scalef_round_pd(__m512d a, __m512d b, int rounding);
VSCALEFPD __m512d _mm512_mask_scalef_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int rounding);
VSCALEFPD __m512d _mm512_maskz_scalef_round_pd(__ mmask8 k, __m512d a, __m512d b, int rounding);
VSCALEFPD __m512d _mm512_scalef_pd(__m512d a, __m512d b);VSCALEFPD __m512d _mm512_mask_scalef_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);VSCALEFPD __m512d _mm512_maskz_scalef_pd(__mmask8 k, __m512d a, __m512d b);VSCALEFPD __m256d _mm256_scalef_pd(__m256d a, __m256d b);VSCALEFPD __m256d _mm256_mask_scalef_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);VSCALEFPD __m256d _mm256_maskz_scalef_pd(__mmask8 k, __m256d a, __m256d b);VSCALEFPD __m128d _mm_scalef_pd(__m128d a, __m128d b);VSCALEFPD __m128d _mm_mask_scalef_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);VSCALEFPD __m128d _mm_maskz_scalef_pd(__mmask8 k, __m128d a, __m128d b);
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.
See Table 2-46, “Type E2 Class Exception Conditions.”VSCALEFPH—Scale Packed FP16 Values with FP16 ValuesINSTRUCTION SET REFERENCE, V
5-692 Vol. 2CVSCALEFPH—Scale Packed FP 16 Values with FP16 Values
This instruction performs a floating-point scale of the pack ed FP16 values in the first source operand by multiplying 
it by 2 to the power of the FP16 values in second sour ce operand. The destination elements are updated according 
zmm1 := zmm2 * 2floor(zmm3).
If the result cannot be represented in FP16, then the proper  overflow response (for positive scaling operand), or the 
proper underflow response (for negative scaling operand) , is issued. The overflow and underflow responses are 
dependent on the rounding mode (for IEEE-compliant round ing), as well as on other se ttings in MXCSR (exception 
mask bits), and on the SAE bit.
Handling of special-case input values are listed in Table 5-41 and Table 5-42.
Table 5-41. VSCALEFPH/VSCALEFSH Special CasesOpcode/
En64/32 
bit Mode 
EVEX.128.66.MAP6.W0  2C /r
VSCALEFPH xmm1{k1}{z}, xmm2, 
AVX512VLScale the packed FP16 values in xmm2 using 
values from xmm3/m128/m16bcst, and store 
EVEX.256.66.MAP6.W0  2C /r
VSCALEFPH ymm1{k1}{z}, ymm2, 
AVX512VLScale the packed FP16 values in ymm2 using 
values from ymm3/m256/m16bcst, and store the result in ymm1 subject to writemask k1.
EVEX.512.66.MAP6.W0  2C /r
VSCALEFPH  zmm1{k1}{z},  zmm2,  
zmm3/m512/m16bcst  {er}A V/V AVX512-FP16 Scale the packed FP16 values in zmm2 using 
values from zmm3/m512/m16bcst, and store the 
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Src1Src2
Set IE
±NaN +INF −INF 0/Denorm/Norm
±QNaN QNaN(Src1) +INF +0 QNaN(Src1) IF either source is SNaN
±SNaN QNaN(Src1) QNaN(Src1) QNaN(Src1) QNaN(Src1) YES±INF QNaN(Src2) Src1 QNaN_Indefinite Src1 IF Src2 is SNaN or −INF
±0 QNaN(Src2) QNaN_Indefinite Src1 Src1 IF Src2 is SNaN or +INF
Denorm/Norm QNaN(Src2) ±INF (Src1 sign) ±0 (Src1 sign) Compute Result IF Src2 is SNaN
Table 5-42. Additional VSCALEFPH/VSCALEFSH Special Cases
Special Case  Returned Value Faults
|result| < 2-24±0 or ±Min -Denormal (Src1 sign) Underflow
|result| ≥ 216±INF (Src1 sign) or ±Max -Denormal (Src1 sign) OverflowVSCALEFPH—Scale Packed FP16 Values with FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-693Operation
def scale_fp16(src1,src2):
tmp1 := src1tmp2 := src2return tmp1 * POW(2, FLOOR(tmp2)) 
VSCALEFPH dest{k1}, src1, src2
VL = 128, 256, or 512KL := VL / 16
IF (VL = 512) AND (EVEX.b = 1) and no memory operand:
ELSE
IF SRC2 is memory and (EVEX.b = 1):
tsrc := src2.fp16[0]
ELSE:
tsrc := src2.fp16[i]
dest.fp16[i] := scale_fp16(src1.fp16[i],tsrc)
dest.fp16[i] := 0
//else dest.fp16[i] remains unchanged
VSCALEFPH __m128h _mm_mask_scalef_ph (__m128 h src, __mmask8 k, __m128h a, __m128h b);
VSCALEFPH __m128h _mm_maskz_scalef_ph (__mmask8 k, __m128h a, __m128h b);VSCALEFPH __m128h _mm_scalef_ph (__m128h a, __m128h b);VSCALEFPH __m256h _mm256_mask_scalef_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);VSCALEFPH __m256h _mm256_maskz_scalef_ph (__mmask16 k, __m256h a, __m256h b);VSCALEFPH __m256h _mm256_scalef_ph (__m256h a, __m256h b);VSCALEFPH __m512h _mm512_mask_scalef_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);VSCALEFPH __m512h _mm512_maskz_scalef_ph (__mmask32 k, __m512h a, __m512h b);VSCALEFPH __m512h _mm512_scalef_ph (__m512h a, __m512h b);VSCALEFPH __m512h _mm512_mask_scalef_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, const int rounding);VSCALEFPH __m512h _mm512_maskz_scalef_round_ph (__mmask32 k, __m512h a, __m512h b, const int;VSCALEFPH __m512h _mm512_scalef_round_ph (__m 512h a, __m512h b, const int rounding);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions”.
Denormal-operand exception (#D) is checked and signaled for src1 operand, but not for src2 operand. The 
denormal-operand exception is checked for src1 operand only if the src2 operand is not NaN. If the src2 operand is

denormal-operand exception is checked for src1 operand only if the src2 operand is not NaN. If the src2 operand is 
NaN, the processor generates NaN and does not signal de normal-operand exception, even if src1 operand is 
denormal.VSCALEFPS—Scale Packed Float32 Values With Float32 ValuesINSTRUCTION SET REFERENCE, V
5-694 Vol. 2CVSCALEFPS—Scale Packed Float32 Values With Float32 Values
Performs a floating-point scale of the packed single-precisi on floating-point values in the first source operand by 
multiplying them by 2 to the power of the float32 values in second source operand.
If the result cannot be represented in single-precision, then the proper overflow response (for positive scaling 
operand), or the proper underflow resp onse (for negative scaling operand) is  issued. The overflow and underflow 
responses are dependent on the rounding mode (for IEEE- compliant rounding), as well as on other settings in 
register, a 512-bit memory location or a 512-bit vector br oadcasted from a 32-bit memory location. The destination 
operand is a ZMM register conditionally updated with writemask k1.
Handling of special-case input values are listed in Table 5-39 and Table 5-43.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 2C /r 
VSCALEFPS xmm1 {k1}{z}, xmm2, 
xmm3/m128/m32bcstA V/V AVX512VL
AVX512FScale the packed single-precision floating-point values in 
xmm2 using values from xmm3/m128/m32bcst. Under 
EVEX.256.66.0F38.W0 2C /r 
VSCALEFPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstA V/V AVX512VL
AVX512FScale the packed single-preci sion values in ymm2 using 
floating-point values from ymm3/m256/m32bcst. Under writemask k1.
EVEX.512.66.0F38.W0 2C /r 
VSCALEFPS zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst{er}A V/V AVX512F Scale the packed single-precision floating-point values in 
zmm2 using floating-point values from 
zmm3/m512/m32bcst. Under writemask k1.
AF u l l M o d R M : r e g  ( w ) E V E X . vvvv (r) ModRM:r/m (r) N/A
Table 5-43. Additional VSCALEFPS/SS Special Cases
|result| < 2-149±0 or ±Min-Denormal (Src1 sign) Underflow
|result| ≥ 2128±INF (Src1 sign) or ±Max-n ormal (Src1 sign) OverflowVSCALEFPS—Scale Packed Float 32 Values With Float32 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-695Operation
{ ; Check for denormal operandsTMP_SRC2 := SRC2TMP_SRC1 := SRC1IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0/* SRC2 is a 32 bits floating-point value */DEST[31:0] := TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))}
VSCALEFPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)
THEN
ELSE 
THEN DEST[i+31:i] := SCALE(SRC1[i+31:i], SRC2[31:0]);ELSE DEST[i+31:i] := SCALE(SRC1[i+31:i], SRC2[i+31:i]);
FI;
ELSE 
FI
FI;
ENDFOR
VSCALEFPS __m512 _mm512_scalef_round_ps (__m512 a, __m512 b, int rounding);
VSCALEFPS __m512 _mm512_mask_scalef_round_ps(__m512 s,  __mmask16 k, __m512 a, __m512 b, int rounding);
VSCALEFPS __m512 _mm512_maskz_scalef_round_ps(__ mmask16 k, __m512 a, __m512 b, int rounding);
VSCALEFPS __m512 _mm512_scalef_ps(__m512 a, __m512 b);VSCALEFPS __m512 _mm512_mask_scalef_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);VSCALEFPS __m512 _mm512_maskz_scalef_ps(__mmask16 k, __m512 a, __m512 b);VSCALEFPS __m256 _mm256_scalef_ps(__m256 a, __m256 b);VSCALEFPS __m256 _mm256_mask_scalef_ps(__m2 56 s, __mmask8 k, __m256 a, __m256 b);
VSCALEFPS __m256 _mm256_maskz_scalef_ps(__mmask8 k, __m256 a, __m256 b);VSCALEFPS __m128 _mm_scalef_ps(__m128 a, __m128 b);VSCALEFPS __m128 _mm_mask_scalef_ps(__m12 8 s, __mmask8 k, __m128 a, __m128 b);
VSCALEFPS __m128 _mm_maskz_scalef_ps(__mmask8 k, __m128 a, __m128 b);
Denormal is not reported for Src2.VSCALEFPS—Scale Packed Float32 Values With Float32 ValuesINSTRUCTION SET REFERENCE, V
5-696 Vol. 2COther Exceptions
See Table 2-46, “Type E2 Class Exception Conditions.”VSCALEFSD—Scale Scalar Float64 Values With Float64 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-697VSCALEFSD—Scale Scalar Float 64 Values With Float64 Values
Performs a floating-point scale of the scalar double precis ion floating-point value in the first source operand by 
multiplying it by 2 to the power of the double prec ision floating-point value in second source operand.
xmm1 := xmm2*2floor(xmm3).
Floor(xmm3) means maximum integer value ≤ xmm3.
EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register 
or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.
Operation
{
; Check for denormal operands
TMP_SRC2 := SRC2TMP_SRC1 := SRC1IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0/* SRC2 is a 64 bits floating-point value */DEST[63:0] := TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))}Opcode/
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W1 2D /r 
VSCALEFSD xmm1 {k1}{z}, xmm2, 
xmm3/m64{er}A V/V AVX512F Scale the scalar double precision floating-point values in 
xmm2 using the value from xmm3/m64. Under writemask 
k1.
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVSCALEFSD—Scale Scalar Float64 Values With Float64 ValuesINSTRUCTION SET REFERENCE, V
5-698 Vol. 2CVSCALEFSD (EVEX encoded version)
IF (EVEX.b= 1) and SRC2 *is a register*
THEN
ELSE 
FI;IF k1[0] OR *no writemask*
THEN DEST[63:0] := SCAL E(SRC1[63:0], SRC2[63:0])
ELSE 
FI
VSCALEFSD __m128d _mm_scalef_round_s d(__m128d a, __m128d b, int);
VSCALEFSD __m128d _mm_mask_scalef_round_sd(__m128d  s, __mmask8 k, __m128d a, __m128d b, int);
VSCALEFSD __m128d _mm_maskz_scalef_round_sd( __mmask8 k, __m128d a, __m128d b, int);
See Table 2-47, “Type E3 Class Exception Conditions.”VSCALEFSH—Scale Scalar FP16 Values with FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-699VSCALEFSH—Scale Scalar FP 16 Values with FP16 Values
This instruction performs a floating-point scale of the low FP16 element in the first source operand by multiplying it 
by 2 to the power of the low FP16 element in second source  operand, storing the result in the low element of the 
xmm1 := xmm2 * 2floor(xmm3).
If the result cannot be represented in FP16, then the prop er overflow response (for positive scaling operand), or 
the proper underflow response (for negative scaling oper and), is issued. The overflow and underflow responses are 
dependent on the rounding mode (for IEEE-compliant roundi ng), as well as on other settings in MXCSR (exception 
mask bits, FTZ bit), and on the SAE bit.
Operation

Operation
VSCALEFSH dest{k1}, src1, src2
IF (EVEX.b = 1) and no memory operand:
ELSE
dest.fp16[0] := scale_fp16(src1.fp16 [0], src2.fp16[0] ) // see VSCALEFPH
En64/32 
bit Mode 
EVEX.LLIG.66.MAP6.W0 2D /r
VSCALEFSH xmm1{k1}{z}, xmm2, 
xmm3/m16 {er}A V/V AVX512-FP16 Scale the FP16 va lues in xmm2 using the value 
from xmm3/m16 and store the result in xmm1 
subject to writemask k1. Bits 127:16 from xmm2 
are copied to xmm1[127:16]. 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVSCALEFSH—Scale Scalar FP16 Values with FP16 ValuesINSTRUCTION SET REFERENCE, V
5-700 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VSCALEFSH __m128h _mm_mask_scalef_roun d_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);
VSCALEFSH __m128h _mm_maskz_scalef_round_sh (__mma sk8 k, __m128h a, __m128h b, const int rounding);
VSCALEFSH __m128h _mm_scalef_round_sh (__m 128h a, __m128h b, const int rounding);
VSCALEFSH __m128h _mm_mask_scalef_sh (__m1 28h src, __mmask8 k, __m128h a, __m128h b);
VSCALEFSH __m128h _mm_maskz_scalef_sh (__mmask8 k, __m128h a, __m128h b);
VSCALEFSH __m128h _mm_scalef_sh (__m128h a, __m128h b);
Denormal-operand exception (#D) is checked and signal ed for src1 operand, but not for src2 operand. The 
denormal-operand exception is checked for src1 operand only if the src2 operand is not Na N. If the src2 operand is 
denormal.VSCALEFSS—Scale Scalar Float 32 Value With Float32 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-701VSCALEFSS—Scale Scalar Float 32 Value With Float32 Value
Performs a floating-point scale of the scalar single-precisi on floating-point value in the first source operand by 
multiplying it by 2 to the power of the float32 value in second source operand.
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W0 2D /r 
VSCALEFSS xmm1 {k1}{z}, xmm2, 
xmm3/m32{er}A V/V AVX512F Scale the scalar single-p recision floating-point value in 
xmm2 using floating-point value from xmm3/m32. Under 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVSCALEFSS—Scale Scalar Float32 Value With Float32 ValueINSTRUCTION SET REFERENCE, V
5-702 Vol. 2COperation
{
TMP_SRC2 := SRC2TMP_SRC1 := SRC1IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0/* SRC2 is a 32 bits floating-point value */DEST[31:0] := TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))}
VSCALEFSS (EVEX encoded version)
THEN
ELSE 
THEN DEST[31:0] := SCAL E(SRC1[31:0], SRC2[31:0])
ELSE 
FI
VSCALEFSS __m128 _mm_scalef_round _ss(__m128 a, __m128 b, int);
VSCALEFSS __m128 _mm_mask_scalef_round_ss(__m12 8 s, __mmask8 k, __m128 a, __m128 b, int);
VSCALEFSS __m128 _mm_maskz_scalef_round_s s(__mmask8 k, __m128 a, __m128 b, int);
See Table 2-47, “Type E3 Class Exception Conditions.”VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Pack ed Single, Packed Double with Signed Dword and Qword INSTRUCTION SET REFERENCE, V
Vol. 2C 5-703VSCATTERDPS/VSCATTERDPD/VS CATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed 
Double with Signed Dword and Qword Indices
Stores up to 16 elements (or 8 elements) in doubleword /quadword vector zmm1 to the memory locations pointed 
by base address BASE_ADDR and index vector VINDEX, with  scale SCALE. The elements are specified via the VSIB 
(i.e., the index register is a vector register, holding pack ed indices). Elements will only be stored if their corre-
sponding mask bit is one. The entire mask register will be set to zero by this instruction unless it triggers an excep-
tion.
This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception 
register and the mask register (k1) are partially updated.  If any traps or interrupts are pending from already scat-
tered elements, they will be delivered in lieu of the exceptio n; in this case, EFLAG.RF is set to one so an instruction 
Note that:
n64/32 
bit Mode 
Feature 
EVEX.128.66.0F38.W0 A2 /vsib 
VSCATTERDPS vm32x {k1}, xmm1A V/V AVX512VL
AVX512FUsing signed dword indices,  scatter single-precision 
floating-point values to memory using writemask k1.
EVEX.256.66.0F38.W0 A2 /vsib 
VSCATTERDPS vm32y {k1}, ymm1A V/V AVX512VL
EVEX.512.66.0F38.W0 A2 /vsib 
VSCATTERDPS vm32z {k1}, zmm1A V/V AVX512F Using signed dword in dices, scatter single-precision 
EVEX.128.66.0F38.W1 A2 /vsib
VSCATTERDPD vm32x {k1}, xmm1A V/V AVX512VL
AVX512FUsing signed dword indices, scatter double precision 
EVEX.256.66.0F38.W1 A2 /vsib 
VSCATTERDPD vm32x {k1}, ymm1A V/V AVX512VL
EVEX.512.66.0F38.W1 A2 /vsib 
VSCATTERDPD vm32y {k1}, zmm1A V/V AVX512F Using signed dword indices, scatter double precision 
EVEX.128.66.0F38.W0 A3 /vsib
VSCATTERQPS vm64x {k1}, xmm1A V/V AVX512VL
AVX512FUsing signed qword indices,  scatter single-precision 
EVEX.256.66.0F38.W0 A3 /vsib 
VSCATTERQPS vm64y {k1}, xmm1A V/V AVX512VL
EVEX.512.66.0F38.W0 A3 /vsib 
VSCATTERQPS vm64z {k1}, ymm1A V/V AVX512F Using signed qword in dices, scatter single-precision 
EVEX.128.66.0F38.W1 A3 /vsib 
VSCATTERQPD vm64x {k1}, xmm1A V/V AVX512VL
AVX512FUsing signed qword indices, scatter double precision 
EVEX.256.66.0F38.W1 A3 /vsib 
VSCATTERQPD vm64y {k1}, ymm1A V/V AVX512VL
EVEX.512.66.0F38.W1 A3 /vsib 
VSCATTERQPD vm64z {k1}, zmm1A V/V AVX512F Using signed qword indices, scatter double precision 

VectorReg(R): VSIB:indexModRM:reg (r) N/A N/AVSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Pack ed Single, Packed Double with Signed Dword and QwordINSTRUCTION SET REFERENCE, V
5-704 Vol. 2Cordering model. Note that this does not account for no n-overlapping indices that map into the same physical 
the left of a faulting one may be scattered before the fault is delivered. A given implementation of this 
left of the faulting one will be scattered.
ignored.
The instruction will #UD fault if the k0 mask register is specified.
Operation
VSCATTERDPS (EVEX encoded versions)
THEN MEM[BASE_ADDR +S ignExtend(VINDEX[i+31:i]) * SCALE + DISP] :=
SRC[i+31:i]k1[j] := 0
FI;
VSCATTERDPD (EVEX encoded versions)
THEN MEM[BASE_ADDR +S ignExtend(VINDEX[k+31:k]) * SCALE + DISP] :=
SRC[i+63:i]k1[j] := 0
FI;VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Pack ed Single, Packed Double with Signed Dword and Qword INSTRUCTION SET REFERENCE, V
Vol. 2C 5-705ENDFOR
k1[MAX_KL-1:KL] := 0VSCATTERQPS (EVEX encoded versions)(KL, VL)= (2, 128),  (4, 256), (8, 512)
THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] :=
FI;
VSCATTERQPD (EVEX encoded versions)
THEN MEM[BASE_ADDR + (VINDEX[ i+63:i]) * SCALE + DISP] :=
FI;
VSCATTERDPD void _mm512_i32sc atter_pd(void * base, __m256i vdx, __m512d a, int scale);
VSCATTERDPD void _mm512_m ask_i32scatter_pd(void * base, __mmask8 k, __m256i vdx, __m512d a, int scale);
VSCATTERDPS void _mm512_i32scatter_ps(void * base, __m512i vdx, __m512 a, int scale);
VSCATTERDPS void _mm512_mask_i32scatter_ps(void * base , __mmask16 k, __m512i vdx, __m512 a, int scale);
VSCATTERQPD void _mm512_i64scatter_pd(void * base, __m512i vdx, __m512d a, int scale);
VSCATTERQPD void _mm512_mask_i64sca tter_pd(void * base, __mmask8 k, __m 512i vdx, __m512d a, int scale);
VSCATTERQPS void _mm512_i64sc atter_ps(void * base, __m512i vd x, __m256 a, int scale);
VSCATTERQPS void _mm512_m ask_i64scatter_ps(void * base, __mmask8 k,  __m512i vdx, __m256 a, int scale);
VSCATTERDPD void _mm256_i32sc atter_pd(void * base, __m128i vdx, __m256d a, int scale);
VSCATTERDPD void _mm256_m ask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m256d a, int scale);
VSCATTERDPS void _mm256_i32scatter_ps(void * base, __m256i vdx, __m256 a, int scale);
VSCATTERDPS void _mm256_mask_i32scatter_ps(void * ba se, __mmask8 k, __m256i vdx, __m256 a, int scale);
VSCATTERQPD void _mm256_i64scatter_pd(void * base, __m256i vdx, __m256d a, int scale);
VSCATTERQPD void _mm256_mask_i64sca tter_pd(void * base, __mmask8 k, __m 256i vdx, __m256d a, int scale);
VSCATTERQPS void _mm256_i64sc atter_ps(void * base, __m256i vd x, __m128 a, int scale);
VSCATTERQPS void _mm256_m ask_i64scatter_ps(void * base, __mmask8 k,  __m256i vdx, __m128 a, int scale);
VSCATTERDPD void _mm_i32scatter_pd(void * ba se, __m128i vdx, __m128d a, int scale);
VSCATTERDPD void _mm_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);
VSCATTERDPS void _mm_i32scatter_ps(void * base, __m128i vdx, __m128 a, int scale);VSCATTERDPS void _mm_mask_i32scatte r_ps(void * base, __mmask8 k, __m 128i vdx, __m128 a, int scale);
VSCATTERQPD void _mm_i64scatter_pd(void * base, __m128i vdx, __m128d a, int scale);
VSCATTERQPD void _mm_mask_i64scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);
VSCATTERQPS void _mm_i64sca tter_ps(void * base, __m128i vdx, __m128 a, int scale);
VSCATTERQPS void _mm_mask_i64scatte r_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Pack ed Single, Packed Double with Signed Dword and QwordINSTRUCTION SET REFERENCE, V
5-706 Vol. 2CSIMD Floating-Point Exceptions
Invalid, Overflow, Underflow, Precision, Denormal.
See Table 2-61, “Type E12 Class Exception Conditions.”VSHUFF32x4/VSHUFF64x2/VSHUFI32x 4/VSHUFI64x2—Shuffle Packed Va lues at 128-Bit GranularityINSTRUCTION SET REFERENCE, V
Vol. 2C 5-707VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x 2—Shuffle Packed Values at 128-Bit 
256-bit Version: Moves one of the two 128-bit packed single -precision floating-point values from the first source 
operand (second operand) into the low 128-bit of the de stination operand (first operand); moves one of the two 
packed 128-bit floating-point values from the second sour ce operand (third operand) into the high 128-bit of the 
destination operand. The selector operand (third operand)  determines which values are moved to the destination 
operand.
512-bit Version: Moves two of the four 128-bit packed single-precision floating-point values from the first source 
operand (second operand) into the low 256-bit of each do uble qword of the destinatio n operand (first operand); 
moves two of the four packed 128-bit floating-point values  from the second source operand (third operand) into 
the high 256-bit of the destination operand. The selector  operand (third operand) determines which values are 
moved to the destination operand.
The first source operand is a vector register. The second source operand can be a ZMM register, a 512-bit memory 
location or a 512-bit vector broadcasted from a 32/64-bit  memory location. The destination operand is a vector 
register.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.256.66.0F3A.W0 23 /r ib
VSHUFF32X4 ymm1{k1}{z}, ymm2, 
AVX512FShuffle 128-bit packed single-precision floating-point 
values selected by imm8 from ymm2 and 
ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1.
EVEX.512.66.0F3A.W0 23 /r ib
VSHUFF32x4 zmm1 {k1}{z}, zmm2, 
zmm3/m512/m32bcst, imm8A V/V AVX512F Shuffle 128-bit packed single-precision floating-point 
values selected by imm8 from zmm2 and 
zmm3/m512/m32bcst and place results in zmm1 subject to writemask k1.
EVEX.256.66.0F3A.W1 23 /r ib
VSHUFF64X2 ymm1{k1}{z}, ymm2, 
AVX512FShuffle 128-bit packed double precision floating-point 
ymm3/m256/m64bcst and place results in ymm1 
EVEX.512.66.0F3A.W1 23 /r ib
VSHUFF64x2 zmm1 {k1}{z}, zmm2, 
zmm3/m512/m64bcst, imm8A V/V AVX512F Shuffle 128-bit packed double precision floating-point 
zmm3/m512/m64bcst and place results in zmm1 
EVEX.256.66.0F3A.W0 43 /r ib
VSHUFI32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8A V/V AVX512VL

AVX512FShuffle 128-bit packed double -word values selected by 
imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1.
EVEX.512.66.0F3A.W0 43 /r ib
VSHUFI32x4 zmm1{k1}{z}, zmm2, 
zmm3/m512/m32bcst, imm8A V/V AVX512F Shuffle 128-bit packed double-word values selected by 
imm8 from zmm2 and zmm3/m512/m32bcst and place 
results in zmm1 subject to writemask k1.
EVEX.256.66.0F3A.W1 43 /r ib
VSHUFI64X2 ymm1{k1}{z}, ymm2, 
AVX512FShuffle 128-bit packed quad-word values selected by 
imm8 from ymm2 and ymm3/m256/m64bcst and place 
results in ymm1 subject to writemask k1.
EVEX.512.66.0F3A.W1 43 /r ib
VSHUFI64x2 zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8A V/V AVX512F Shuffle 128-bit packed quad-word values selected by 
imm8 from zmm2 and zmm3/m512/m64bcst and place results in zmm1 subject to writemask k1.
A Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuf fle Packed Values at  128-Bit GranularityINSTRUCTION SET REFERENCE, V
5-708 Vol. 2CThe writemask updates the destination operand with  the granularity of 32/64-bit data elements.
Operation
Select2(SRC, control) {
CASE (control[0]) OF
0: TMP := SRC[127:0];1: TMP := SRC[255:128];
0: TMP := SRC[127:0];1: TMP := SRC[255:128];2: TMP := SRC[383:256];3: TMP := SRC[511:384];
VSHUFF32x4 (EVEX versions)
FI;
TMP_DEST[127:0] := Select 2(SRC1[255:0], imm8[0]);
TMP_DEST[255:128] := Select 2(SRC2[255:0], imm8[1]);
TMP_DEST[127:0] := Select 4(SRC1[511:0], imm8[1:0]);
TMP_DEST[255:128] := Select 4(SRC1[511:0], imm8[3:2]);
TMP_DEST[383:256] := Select4(TMP_SRC2[511:0], imm8[5:4]);TMP_DEST[511:384] := Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FI;
ENDFORDEST[MAXVL-1:VL] := 0VSHUFF32x4/VSHUFF64x2/VSHUFI32x 4/VSHUFI64x2—Shuffle Packed Va lues at 128-Bit GranularityINSTRUCTION SET REFERENCE, V
Vol. 2C 5-709VSHUFF64x2 (EVEX 512-bit version)
FI;
FI
FI;
VSHUFI32x4 (EVEX 512-bit version)
FI;
i := j * 32VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuf fle Packed Values at  128-Bit GranularityINSTRUCTION SET REFERENCE, V
5-710 Vol. 2CIF k1[j] OR *no writemask*
FI
FI;
VSHUFI64x2 (EVEX 512-bit version)
FI;
FI
FI;
Vol. 2C 5-711Intel C/C++ Compiler Intrinsic Equivalent
VSHUFI32x4 __m512i _mm512_shuffle_i32x4(__m512i a, __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_mask_shuffle_i32x4(__m512i s, __mmask16 k, __m512i a, __m512i b, int imm);VSHUFI32x4 __m512i _mm512_maskz_shuffle_i32x4( __mmask16 k, __m512i a, __m512i b, int imm);VSHUFI32x4 __m256i _mm256_shuffle_i32x4(__m256i a, __m256i b, int imm);VSHUFI32x4 __m256i _mm256_mask_shuffle_i32x4(__m256i s, __mmask8 k, __m256i a, __m256i b, int imm);VSHUFI32x4 __m256i _mm256_maskz_shuffle_i32x4( __mmask8 k, __m256i a, __m256i b, int imm);VSHUFF32x4 __m512 _mm512_shuffle_f32x4(__m512 a, __m512 b, int imm);VSHUFF32x4 __m512 _mm512_mask_shuffle_f32x4(__m51 2 s, __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_maskz_shuffle_f32x4 ( __mmask16 k, __m512 a,  __m512 b, int imm);
VSHUFI64x2 __m512i _mm512_shuffle_i64x2(__m512i a, __m512i b, int imm);VSHUFI64x2 __m512i _mm512_mask_shuffle_i64x2(__m512i s, __mmask8 k, __m512i b, __m512i b, int imm);VSHUFI64x2 __m512i _mm512_maskz_shuffle_i64x2( __mmask8 k, __m512i a, __m512i b, int imm);VSHUFF64x2 __m512d _mm512_shuffle_f64x2(__m512d a, __m512d b, int imm);VSHUFF64x2 __m512d _mm512_mask_shuffle_f64x2(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);VSHUFF64x2 __m512d _mm512_maskz_shuffle_f64x2( __mmask8 k, __m512d a, __m512d b, int imm);
None.
See Table 2-50, “Type E4NF Class Exception Conditions.”
Additionally:#UD If EVEX.L’L = 0 for VSHUFF32x4 /VSHUFF64x2 .VSQRTPH—Compute Square Root of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-712 Vol. 2CVSQRTPH—Compute Square R oot of Packed FP16 Values
This instruction performs a packed FP16 square-root comp utation on the values from source operand and stores 
the packed FP16 result in the destination operand. The destination elements are updated according to the write-
mask.
Operation
VSQRTPH dest{k1}, src
ELSE:
DEST.fp16[i] := SQRT(tsrc)
En64/32 
bit Mode 
EVEX.128.NP.MAP5.W0  51 /r
VSQRTPH  xmm1{k1}{z},  xmm2/m128/
AVX512VLCompute square roots of the packed FP16 values 
in xmm2/m128/m16bcst, an d store the result in 
EVEX.256.NP.MAP5.W0  51 /r
VSQRTPH  ymm1{k1}{z},  ymm2/m256/
in ymm2/m256/m16bcst, and store the result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0  51 /r
VSQRTPH  zmm1{k1}{z},  zmm2/m512/
m16bcst  {er}A V/V AVX512-FP16 Compute square roots of the packed FP16 values 
in zmm2/m512/m16bcst, and store the result in 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVSQRTPH—Compute Square Root of Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-713Intel C/C++ Compiler Intrinsic Equivalent
VSQRTPH __m128h _mm_mask_sqrt_ph (__m 128h src, __mmask8 k, __m128h a);
VSQRTPH __m128h _mm_maskz_sqrt_ph (__mmask8 k, __m128h a);VSQRTPH __m128h _mm_sqrt_ph (__m128h a);VSQRTPH __m256h _mm256_mask_sqrt_ph (__m256h src, __mmask16 k, __m256h a);VSQRTPH __m256h _mm256_maskz_sqr t_ph (__mmask16 k, __m256h a);
VSQRTPH __m256h _mm256_sqrt_ph (__m256h a);VSQRTPH __m512h _mm512_mask_sqrt_ph (__m512h src, __mmask32 k, __m512h a);VSQRTPH __m512h _mm512_maskz_sqr t_ph (__mmask32 k, __m512h a);

VSQRTPH __m512h _mm512_sqrt_ph (__m512h a);VSQRTPH __m512h _mm512_mask_sqrt_round_ph (__m512h src, __mmask32 k, __m512h  a, const int rounding);
VSQRTPH __m512h _mm512_maskz_sqrt_round_ph ( __mmask32 k, __m512h a, const int rounding);
VSQRTPH __m512h _mm512_sqrt_round_ph (__m512h a, const int rounding);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”VSQRTSH—Compute Square Root of Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
5-714 Vol. 2CVSQRTSH—Compute Square R oot of Scalar FP16 Value
This instruction performs a scalar FP16 square-root computation on the source operand and stores the FP16 result 
in the destination operand. Bits 127:16 of the destination operand are copied from the corresponding bits of the first 
source operand. Bits MAXVL-1:128 of the destination op erand are zeroed. The low FP16 element of the destination 
is updated according to the writemask.
Operation
VSQRTSH dest{k1}, src1, src2
DEST.fp16[0] := SQRT(src2.fp16[0])
VSQRTSH __m128h _mm_mask_sqrt_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);
VSQRTSH __m128h _mm_maskz_sqrt_round_sh (__mmask8 k, __m128h a, __m128h b, const int rounding);VSQRTSH __m128h _mm_sqrt_round_sh (__m1 28h a, __m128h b, const int rounding);
VSQRTSH __m128h _mm_mask_sqrt_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VSQRTSH __m128h _mm_maskz_sqrt_sh (__mmask8 k, __m128h a, __m128h b);VSQRTSH __m128h _mm_sqrt_sh (__m128h a, __m128h b);
Invalid, Precision, Denormal
En64/32 
bit Mode 
EVEX.LLIG.F3.MAP5.W0 51 /r
VSQRTSH xmm1{k 1}{z}, xmm2, 
xmm3/m16 {er}A V/V AVX512-FP16 Compute square root of the low FP16 value in 
xmm3/m16 and store the result in xmm1 subject 
to writemask k1. Bits 127:16 from xmm2 are 
copied to xmm1[127:16].
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVSUBPH—Subtract Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
Vol. 2C 5-715VSUBPH—Subtract Packed FP16 Values
This instruction subtracts packed FP16 values from second  source operand from the corresponding elements in the 
first source operand, storing the packed FP16 result in  the destination operand. Th e destination elements are 
Operation
VSUBPH (EVEX encoded versions) wh en src2 operand is a register
ELSE
DEST.fp16[j] := SRC1.fp16[j] - SRC2.fp16[j]
En64/32 
bit Mode 
EVEX.128.NP.MAP5.W0  5C /r
VSUBPH xmm1{k1}{z}, xmm2, xmm3/
AVX512VLSubtract packed FP16 values from xmm3/m128/
m16bcst to xmm2, and stor e the result in xmm1 
EVEX.256.NP.MAP5.W0  5C /r
VSUBPH ymm1{k1}{z}, ymm2, ymm3/
AVX512VLSubtract packed FP16 values from ymm3/m256/
m16bcst to ymm2, and store the result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0  5C /r
VSUBPH  zmm1{k1}{z},  zmm2,  zmm3/
m512/m16bcst  {er}A V/V AVX512-FP16 Subtract packed FP16 values from zmm3/m512/
m16bcst to zmm2, and stor e the result in zmm1 
A Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVSUBPH—Subtract Packed FP16 ValuesINSTRUCTION SET REFERENCE, V
5-716 Vol. 2CVSUBPH (EVEX encoded versions) when src2 operand is a memory source 
DEST.fp16[j] := SRC1.fp16[j] - SRC2.fp16[0]
ELSE:
VSUBPH  __m128h _mm_mask_sub_ph (__m128h src,  __mmask8 k, __m128h a, __m128h b);
VSUBPH  __m128h _mm_maskz_sub_ph (__mma sk8 k, __m128h a, __m128h b);
VSUBPH  __m128h _mm_sub_ph (__m128h a, __m128h b);
VSUBPH  __m256h _mm256_mask_sub_ph (__m256h sr c, __mmask16 k, __m256h a, __m256h b);
VSUBPH  __m256h _mm256_maskz_sub_ph (__mma sk16 k, __m256h a, __m256h b);
VSUBPH  __m256h _mm256_sub_ph (__m256h a, __m256h b);
VSUBPH  __m512h _mm512_mask_sub_ph (__m512h sr c, __mmask32 k, __m512h a, __m512h b);
VSUBPH  __m512h _mm512_maskz_sub_ph (__mma sk32 k, __m512h a, __m512h b);
VSUBPH  __m512h _mm512_sub_ph (__m512h a, __m512h b);
VSUBPH  __m512h _mm512_mask_sub_round_ph (__m512h src, __mma sk32 k, __m512h a, __m512h b, int rounding);
VSUBPH  __m512h _mm512_maskz_sub_round_ph (__mmask32  k, __m512h a, __m512h b, int rounding);
VSUBPH  __m512h _mm512_sub_round_ph (__m512h a, __m512h b, int rounding);
EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions.”VSUBSH—Subtract Scalar FP16 ValueINSTRUCTION SET REFERENCE, V
Vol. 2C 5-717VSUBSH—Subtract Scalar FP16 Value
This instruction subtracts the low FP16 value from the seco nd source operand from the corresponding value in the 
first source operand, storing the FP16 result in the dest ination operand. Bits 127:16 of the destination operand are 
Operation
VSUBSH (EVEX encoded versions)
ELSE
DEST.fp16[0] := SRC1.fp16[0] - SRC2.fp16[0]
VSUBSH __m128h _mm_mask_sub_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);
VSUBSH __m128h _mm_maskz_sub_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);VSUBSH __m128h _mm_sub_round_sh ( __m128h a, __m128h b, int rounding);
VSUBSH __m128h _mm_mask_sub_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VSUBSH __m128h _mm_maskz_sub_sh ( __mmask8 k, __m128h a, __m128h b);
VSUBSH __m128h _mm_sub_sh (__m128h a, __m128h b);
En64/32 
bit Mode 
EVEX.LLIG.F3.MAP5.W0 5C /r
VSUBSH xmm1{k1}{z}, xmm2, 
xmm3/m16 {er}A V/V AVX512-FP16 Subtract the low FP16 value in xmm3/m16 from 
xmm2 and store the result  in xmm1 subject to 
writemask k1. Bits 127:16 from xmm2 are 
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/AVTESTPD/VTESTPS—Packed Bit TestINSTRUCTION SET REFERENCE, V
5-718 Vol. 2CVTESTPD/VTESTPS—Packed Bit Test
VTESTPS performs a bitwise comparison of all the sign bits  of the packed single-precision elements in the first 
source operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with 
the dest sign bits produces all zeros, the ZF is set else th e ZF is clear. If the AND of the source sign bits with the 
inverted dest sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with 
VEX.W=1 will cause #UD.
VTESTPD performs a bitwise comparison of all the sign bits  of the double precision elements in the first source 
operation and corresponding sign bits in the second source op erand. If the AND of the sour ce sign bits with the dest 
sign bits produces all zeros, the ZF is set else the ZF is cl ear. If the AND the source sign bits with the inverted dest 
sign bits produces all zeros the CF is set else the CF is  clear. An attempt to execute VTESTPS with VEX.W=1 will 
cause #UD.
128-bit version: The first source register is an XMM register. The second source register can be an XMM register or 
VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM

cause #UD.
Note: In VEX-encoded versions, VEX.v vvv is reserved and must be 1111b, otherwise instructions will #UD.Opcode/
/ 
En64/32 
bit Mode 
Feature 
VEX.128.66.0F38.W0 0E /r
VTESTPS xmm1, xmm2/m128RM V/V AVX Set ZF and CF depending on sign bit AND and 
ANDN of packed single-precision floating-point 
sources.
VEX.256.66.0F38.W0 0E /r
VTESTPS ymm1, ymm2/m256RM V/V AVX Set ZF and CF depending on sign bit AND and 
ANDN of packed single-precision floating-point sources.
VEX.128.66.0F38.W0 0F /r
VTESTPD xmm1, xmm2/m128RM V/V AVX Set ZF and CF depending on sign bit AND and 
ANDN of packed double precision floating-point 
sources.
VEX.256.66.0F38.W0 0F /r
VTESTPD ymm1, ymm2/m256RM V/V AVX Set ZF and CF depending on sign bit AND and 
sources.
RM ModRM:reg (r) ModRM:r/m (r) N/A N/AVTESTPD/VTESTPS—Packed Bit TestINSTRUCTION SET REFERENCE, V
Vol. 2C 5-719Operation
VTESTPS (128-bit version)
TEMP[127:0] := SRC[127:0] AND DEST[127:0]IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)
TEMP[127:0] := SRC[127:0] AND NOT DEST[127:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)
VTESTPS (VEX.256 encoded version)
TEMP[255:0] := SRC[255:0] AND DEST[255:0]IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)
TEMP[255:0] := SRC[255:0] AND NOT DEST[255:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)
VTESTPD (128-bit version)
TEMP[127:0] := SRC[127:0] AND DEST[127:0]IF ( TEMP[63] = TEMP[127] = 0)
IF ( TEMP[63] = TEMP[127] = 0)
VTESTPD (VEX.256 encoded version)
TEMP[255:0] := SRC[255:0] AND DEST[255:0]IF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)
IF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)
DEST (unmodified)AF := OF := PF := SF := 0;VTESTPD/VTESTPS—Packed Bit TestINSTRUCTION SET REFERENCE, V
5-720 Vol. 2CIntel C/C++ Compiler Intrinsic Equivalent
VTESTPS
int _mm256_testz_ps (__m256 s1, __m256 s2);
int _mm256_testc_ps (__m256 s1, __m256 s2);
int _mm256_testnzc_ps (__m256 s1, __m128 s2);int _mm_testz_ps (__m128 s1, __m128 s2);
int _mm_testc_ps (__m128 s1, __m128 s2);
int _mm_testnzc_ps (__m128 s1, __m128 s2);
VTESTPD
int _mm256_testz_pd (__m256d s1, __m256d s2);
int _mm256_testc_pd (__m256d s1, __m256d s2);
int _mm256_testnzc_pd (__m256d s1, __m256d s2);
int _mm_testz_pd (__m128d s1, __m128d s2);int _mm_testc_pd (__m128d s1, __m128d s2);
int _mm_testnzc_pd (__m128d s1, __m128d s2);
None.
#UD If VEX.vvvv ≠ 1111B.
If VEX.W = 1 for VTESTPS or VTESTPD.VUCOMISH—Unordered Compare Scalar FP16 Values and Set EFLAGSINSTRUCTION SET REFERENCE, V
Vol. 2C 5-721VUCOMISH—Unordered Compare Scal ar FP16 Values and Set EFLAGS
The VUCOMISH instruction differs from the VCOMISH instructio n in that it signals a SIMD floating-point invalid oper-
ation exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid numeric excep-
The EFLAGS register is not updated if an unmasked SIMD  floating-point exception is generated. EVEX.vvvv are 
Operation
VUCOMISH
RESULT := UnorderedCompare(SRC1.fp16[0],SRC2.fp16[0])if RESULT is UNORDERED:
else if RESULT is GREATER_THAN:
else if RESULT is LESS_THAN:
else: // RESULT is EQUALS
VUCOMISH int _mm_ucomieq_sh (__m128h a, __m128h b);
VUCOMISH int _mm_ucomige_sh (__m128h a, __m128h b);VUCOMISH int _mm_ucomigt_sh (__m128h a, __m128h b);VUCOMISH int _mm_ucomile_sh (__m128h a, __m128h b);VUCOMISH int _mm_ucomilt_sh (__m128h a, __m128h b);VUCOMISH int _mm_ucomineq_sh (__m128h a, __m128h b);
En64/32 
bit Mode 
EVEX.LLIG.NP.MAP5.W0 2E /r
VUCOMISH xmm1, xmm2/m16 {sae}A V/V AVX512-FP16 Compare low FP16 values in xmm1 and xmm2/
m16 and set the EFLAGS flags accordingly.
A Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/AVZEROALL—Zero XMM, YMM, and ZMM RegistersINSTRUCTION SET REFERENCE, V
5-722 Vol. 2CVZEROALL—Zero XMM, YMM, and ZMM Registers
In 64-bit mode, the instruction zeroes XMM0-XMM15, YMM0-YMM15, and ZMM0-ZMM15. Outside 64-bit mode, it 
zeroes only XMM0-XMM7, YMM0-YMM7, and ZMM0-Z MM7. VZEROALL does not modify ZMM16-ZMM31.
Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.  In Compatibility and legacy 32-bit 
mode only the lower 8 registers are modified.
Operation
simd_reg_file[][] is a two dimensio nal array representing the SIMD register file contai ning all the overlapp ing xmm, ymm, and z mm 
registers present in that implem entation. The major dimension is the register number: 0 for xmm0, ymm0, and zmm0; 1 for xmm1, 
ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits. On a machine supporting Intel AVX-512, the width is 512.
VZEROALL (VEX.256 encoded version)
IF (64-bit mode)
limit :=15
ELSE
limit := 7
FOR i in 0 .. limit:
simd_reg_file[i][MAXVL-1:0] := 0
VZEROALL:  _mm256_zeroall()
None.
See Table 2-25, “Type 8 Class Exception Conditions.”Opcode/
/ 
En64/32 
bit Mode 
Feature 
VEX.256.0F.WIG 77
VZEROALLZO V/V AVX Zero some of the XMM, YMM, and ZMM 
ZO N/A N/A N/A N/AVZEROUPPER—Zero Upper Bits of YMM and ZMM RegistersINSTRUCTION SET REFERENCE, V
Vol. 2C 5-723VZEROUPPER—Zero Upper Bits of YMM and ZMM Registers
In 64-bit mode, the instruction zeroes the bits in positions 128 and higher in YMM0-YMM15 and ZMM0-ZMM15. 
Outside 64-bit mode, it zeroes those bits only in YM M0-YMM7 and ZMM0-ZMM7. VZEROUPPER does not modify the 
lower 128 bits of these registers an d it does not modify ZMM16-ZMM31.
This instruction is recommended when transitioning betw een AVX and legacy SSE code; it will eliminate perfor-
mance penalties caused by false dependencies.
Note: VEX.vvvv is reserved and must be 1111b otherwise inst ructions will #UD. In Compatibility and legacy 32-bit 
Operation
simd_reg_file[][] is a two dimensio nal array representing the SIMD register file co ntaining all the overla pping xmm, ymm, and z mm 
registers present in that implementation. The major dimension is the register number: 0 for xmm0, ymm0, and zmm0; 1 for xmm1, 
ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits. 
VZEROUPPER 
limit :=15
ELSE
limit := 7
simd_reg_file[i][MAXVL-1:128] := 0
VZEROUPPER:  _mm256_zeroupper()
None.
/ 
En64/32 
bit Mode 
Feature 
VEX.128.0F.WIG 77
VZEROUPPERZO V/V AVX Zero bits in positions 128 and higher of 
some YMM and ZMM registers.
5-724 Vol. 2CVol. 2D 6-1CHAPTER 6

limit :=15
ELSE
limit := 7
None.
/ 
En64/32 
bit Mode 
Feature 
6.1 INSTRUCTIONS (W-Z)
Chapter 6 continues an alphabetical discussion of Intel® 64 and IA-32 instructions (W-Z). See also: Chapter 3, 
“Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Soft ware Developer’s Manual, Volume 
Manual, Volume 2B; and Chapter 5, “Instruction Set Reference, V‚” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2D.WAIT/FWAIT—WaitINSTRUCTION SET REFERENCE, W-Z
6-2 Vol. 2DWAIT/FWAIT—Wait
Causes the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding. 
(FWAIT is an alternate mnemonic for WAIT.)
This instruction is useful for synchronizing exceptions in cr itical sections of code. Coding a WAIT instruction after a 
floating-point instruction ensures that any unmasked floating-point exceptions the instruction may raise are handled before the processor can modify the instruction’s results. See the section titled “Floating-Point Exception 
Synchronization” in Chapter 8 of the Intel
® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 1, for 
more information on using the WAIT/FWAIT instruction.
Operation
CheckForPendingUnmaskedFloatingPointExceptions;
None. 
#NM If CR0.MP[bit 1] = 1 and CR0.TS[bit 3] = 1.
En64-Bit 
9B WAIT ZO Valid Valid Check pending unmasked floating-point 
9B FWAIT ZO Valid Valid Check pending unmasked floating-point 
ZO N/A N/A N/A N/AWBINVD—Write Back and Invalidate CacheINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-3WBINVD—Write Back and Invalidate Cache
Writes back all modified cache lines in the processor’s internal cache to main memory and invalidates (flushes) the 
internal caches. The instruction then issues a special-functi on bus cycle that directs external caches to also write 
back modified data and another bus cycle to indicate  that the external caches should be invalidated.
After executing this instruction, the processor does not wa it for the external caches to complete their write-back 
and flushing operations before proceeding with instruction ex ecution. It is the responsibility of hardware to respond 
to the cache write-back and flush signals. The amount of ti me or cycles for WBINVD to complete will vary due to 
size and other factors of different cache hierarchies. As a consequence, the use of the WBINVD instruction can have 
an impact on logical processor interrupt/event response time. Additional information of WBINVD behavior in a 
cache hierarchy with hierarchical sharing topology can be found in Chapter 2 of the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 3A.
The WBINVD instruction is a privileged instruction. When the processor is ru nning in protected mode, the CPL of a 
program or procedure must be 0 to execute this instructio n. This instruction is also a serializing instruction (see 
“Serializing Instructions” in Chapter 9 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 3A).
In situations where cache coherency with main memory is not a concern, software can use the INVD instruction. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
The WBINVD instruction is implementation dependent, and its function may be implemented differently on future 
Intel 64 and IA-32 processors. The instruction is not su pported on IA-32 processors earlier than the Intel486 
Operation
WriteBack(InternalCaches);
Flush(InternalCaches);SignalWriteBack(ExternalCaches);SignalFlush(ExternalCaches);Continue; (* Continue execution *)
WBINVD void _wbinvd(void);
En64-Bit 
0F 09 WBINVD ZO Valid Valid Write back and flush Internal caches; initiate 
writing-back and flushing of external caches.
6-4 Vol. 2DProtected Mode Exceptions
#GP(0) WBINVD cannot be executed at the virtual-8086 mode.
Same exceptions as in protected mode.WBNOINVD—Write Back and Do Not Invalidate CacheINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-5WBNOINVD—Write Back and Do Not Invalidate Cache
The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory 
but does not invalidate (flush) the internal caches.
operation before proceeding with instruction execution. It is  the responsibility of hardware to respond to the cache 
write-back signal. The amount of time or cycles for WBNOIN VD to complete will vary due to size and other factors 
of different cache hierarchies. As a consequence, the us e of the WBNOINVD instruction can have an impact on 
logical processor interrupt/event response time. 
The WBNOINVD instruction is a privilege d instruction. When the processor is running in protected mode, the CPL of 
a program or procedure must be 0 to execute this instructio n. This instruction is also a serializing instruction (see 
Operation
WBNOINVD void _wbnoinvd(void);
None.
#GP(0) WBNOINVD cannot be executed at the virtual-8086 mode.
Mode 
Feature 
F3 0F 09
WBNOINVDZO V/V WBNOINVD Write back and do not flush internal caches; 
initiate writing-back without flushing of external 
caches.
ZO N/A N/A N/A N/A N/AWBNOINVD—Write Back and Do Not Invalidate CacheINSTRUCTION SET REFERENCE, W-Z
6-6 Vol. 2D64-Bit Mode Exceptions
Same exceptions as in protected mode.WRFSBASE/WRGSBASE—Write FS/GS Segment BaseINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-7WRFSBASE/WRGSBASE—Write FS/GS Segment Base
Loads the FS or GS segment base address with the gene ral-purpose register indicated by the modR/M:r/m field.
The source operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the 
operand size is 64 bits. If no REX.W prefix is used, the op erand size is 32 bits; the upper 32 bits of the source 
register are ignored and upper 32 bits of the base address (for FS or GS) are cleared. 
Operation
FS/GS segment base address := SRC;
None.
WRFSBASE  void _writefsbase_u32( unsigned int );
WRFSBASE  _writefsbase_u64( unsigned __int64 );WRGSBASE  void _writegsbase_u32( unsigned int );WRGSBASE  _writegsbase_u 64( unsigned __int64 );
#UD The WRFSBASE and WRGSBASE instructions  are not recognized in protected mode.
#UD The WRFSBASE and WRGSBASE instructions  are not recognized in real-address mode.
#UD The WRFSBASE and WRGSBASE instructions  are not recognized in virtual-8086 mode.
#UD The WRFSBASE and WRGSBASE  instructions are not recognized in compatibility mode.Opcode/
En64/32-
bit 
F3 0F AE /2
WRFSBASE r32M V/I FSGSBASE Load the FS base addr ess with the 32-bit value in the 
source register.
F3 REX.W 0F AE /2

Operation
None.
En64/32-
bit 
F3 0F AE /2
WRFSBASE r64M V/I FSGSBASE Load the FS base addr ess with the 64-bit value in the 
F3 0F AE /3
WRGSBASE r32M V/I FSGSBASE Load the GS base addr ess with the 32-bit value in the 
F3 REX.W 0F AE /3
WRGSBASE r64M V/I FSGSBASE Load the GS base addr ess with the 64-bit value in the 
M ModRM:r/m (r) N/A N/A N/AWRFSBASE/WRGSBASE—Write FS/GS Segment BaseINSTRUCTION SET REFERENCE, W-Z
6-8 Vol. 2D64-Bit Mode Exceptions
If CR4.FSGSBASE[bit 16] = 0.If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0
#GP(0) If the source register contains a non-canonical address.WRMSR—Write to Model Specific RegisterINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-9WRMSR—Write to Model Specific Register
Writes the contents of registers EDX:EAX into the 64-bit mo del specific register (MSR) sp ecified in the ECX register. 
(On processors that support the Intel 64 architecture, the hi gh-order 32 bits of RCX are ignored.) The contents of 
the EDX register are copied to high-order 32 bits of th e selected MSR and the contents of the EAX register are 
copied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32 
bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously 
read.
exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception. The processor will also genera te a general protection exception if software attempts 
to write to bits in a reserved MSR.
When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated. This includes global entries 
(see “Translation Lookaside Buffers (TLBs)” in Chapter 3 of the Intel
oper’s Manual, Volume 3A).
MSRs control functions for testability, execution tracin g, performance-monitoring and machine check errors. 
Chapter 2, “Model-Specific Registers (MSRs),” of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 4, lists all MSRs that can be written with  this instruction and their addresses. Note that each 
processor family has its own set of MSRs.
The WRMSR instruction is a serializing instruction (see “Serializing Instructions” in Chapter 9 of the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume  3A). Note that WRMSR to  the IA32_TSC_DEADLINE MSR 
(MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.
The MSRs and the ability to read them with the WRMSR instru ction were introduced into the IA-32 architecture with 
Operation
MSR[ECX] := EDX:EAX;
En64-Bit 
0F 30 WRMSR ZO Valid Valid Write the value in EDX:EAX to MSR specified 
by ECX.
ZO N/A N/A N/A N/AWRMSR—Write to Model Specific RegisterINSTRUCTION SET REFERENCE, W-Z
6-10 Vol. 2DProtected Mode Exceptions
If the value in ECX specifies a reserved or unimplemented MSR address.If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.
If the source register contains a non-canonical address and ECX specifies one of the following 
MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_L-STAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.
If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.
MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_L-
STAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.
#GP(0)  The WRMSR instruction is not recognized in virtual-8086 mode.
Same exceptions as in protected mode.WRPKRU—Write Data to User Page Key RegisterINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-11WRPKRU—Write Data to User Page Key Register
Writes the value of EAX into PKRU. ECX and EDX must be 0 when WRPKRU is executed; otherwise, a general-
WRPKRU can be executed only if CR4.PKE = 1; otherwise,  an invalid-opcode exception (#UD) occurs. Software can 
discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H ):ECX.OSPKE [bit 4].
On processors that support the Intel 64 Architecture, th e high-order 32-bits of RCX, RDX, and RAX are ignored.
WRPKRU will never execute speculatively. Memory accesses affected by PKRU register will not execute (even 
speculatively) until all prior executions of WRPKRU ha ve completed execution and updated the PKRU register.
Operation
IF (ECX = 0 AND EDX = 0) 
THEN PKRU := EAX;ELSE #GP(0); 
FI;
None.
WRPKRU void _wrpkru(uint32_t);
#GP(0) If ECX ≠ 0.
If EDX ≠ 0.
NP 0F 01 EF
WRPKRUZO V/V OSPKE Writes EAX into PKRU.
ZO N/A N/A N/A N/AWRPKRU—Write Data to User Page Key RegisterINSTRUCTION SET REFERENCE, W-Z
6-12 Vol. 2D64-Bit Mode Exceptions
Same exceptions as in protected mode.WRSSD/WRSSQ—Write to Shadow StackINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-13WRSSD/WRSSQ—Write to Shadow Stack
Writes bytes in register source to the shadow stack.
Operation
IF CPL = 3
IF (IA32_U_CET.WR_SHSTK_EN) = 0
ELSE
IF (IA32_S_CET.WR_SHSTK_EN) = 0
FI;DEST_LA = Linear_Address(mem operand)IF (operand si ze is 64 bit)
THEN
(* Destination not 8B aligned *)IF DEST_LA[2:0]
Shadow_stack_store 8 by tes of SRC to DEST_LA;
ELSE
(* Destination not 4B aligned *)IF DEST_LA[1:0]
Shadow_stack_store 4 bytes of SRC[31:0] to DEST_LA;
FI;
None.
WRSSD void _wrssd(__int32, void *);
WRSSQ void _wrssq(__int64, void *);Opcode/
0F 38 F6 !(11):rrr:bbb
WRSSD m32, r32MR V/V CET_SS Write 4 bytes to shadow stack.
REX.W 0F 38 F6 !(11):rrr:bbb
WRSSQ m64, r64MR V/N.E. CET_SS Write 8 bytes to shadow stack.
MR ModRM:r/m (w) ModRM:reg (r) N/A N/AWRSSD/WRSSQ—Write to Shadow StackINSTRUCTION SET REFERENCE, W-Z
6-14 Vol. 2DProtected Mode Exceptions
If CPL = 3 and IA32_U_CET.WR_SHSTK_EN = 0.If CPL < 3 and IA32_S_CET.WR_SHSTK_EN = 0.
selector.
If linear address of destinat ion is not 4 byte aligned.
#PF(fault-code) If a page fault occurs if destination is not a user shadow stack when CPL3 and not a supervisor 
shadow stack when CPL < 3.
Other terminal and non-terminal faults.
#UD The WRSS instruction is not recognized in real-address mode. 
#UD The WRSS instruction is not recognized in virtual-8086 mode. 

selector.
If CPL < 3 and IA32_S_CET.SH_STK_EN = 0.If CPL = 3 and IA32_U_CET.WR_SHSTK_EN = 0.
If CPL < 3 and IA32_S_CET.WR_SHSTK_EN = 0.
#GP(0) If a memory address is in a non-canonical form.
Other terminal and non-terminal faults.WRUSSD/WRUSSQ—Write to User Shadow StackINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-15WRUSSD/WRUSSQ—Write to  User Shadow Stack
Writes bytes in register source to a user shadow stack page. The WRUSS instruction can be executed only if CPL = 
0, however the processor treats its shadow-stack accesses as user accesses.
Operation
IF CR4.CET = 0
IF CPL > 0
DEST_LA = Linear_Address(mem operand)IF (operand si ze is 64 bit)
THEN
Shadow_stack_store 8 bytes of SRC to DEST_LA as user-mode access;
ELSE
Shadow_stack_store 4 bytes of SRC[31 :0] to DEST_LA as user-mode access;
FI;
None.
WRUSSD void _wrussd(__int32, void *);
WRUSSQ void _wrussq(__int64, void *);Opcode/
66 0F 38 F5 !(11):rrr:bbb
WRUSSD m32, r32MR V/V CET_SS Write 4 bytes to shadow stack.
66 REX.W 0F 38 F5 !(11):rrr:bbb
WRUSSQ m64, r64MR V/N.E. CET_SS Write 8 bytes to shadow stack.
MR ModRM:r/m (w) ModRM:reg (r) N/A N/AWRUSSD/WRUSSQ—Write to  User Shadow StackINSTRUCTION SET REFERENCE, W-Z
6-16 Vol. 2DProtected Mode Exceptions
selector.
#PF(fault-code) If destination is not a user shadow stack.
#UD The WRUSS instruction is not recognized in real-address mode. 
#UD The WRUSS instruction is not recognized in virtual-8086 mode. 
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#PF(fault-code) If destination is not a user shadow stack.
Other terminal and non-terminal faults.XABORT—Transactional AbortINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-17XABORT—Transactional Abort
XABORT forces an RTM abort. Following an RTM abort, the logical processor resumes execution at the fallback 
address computed through the outermost XBEGIN instructio n. The EAX register is updated to reflect an XABORT 
instruction caused the abort, and the imm8 argume nt will be provided in bits 31:24 of EAX. 
Operation
XABORT
IF RTM_ACTIVE = 0
THEN 
Treat as NOP;
ELSE
GOTO RTM_ABORT_PROCESSING;
FI;
(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
Restore architectural register state;Discard memory updates performed in transaction;Update EAX with status and XABORT argument;RTM_NEST_COUNT:= 0;RTM_ACTIVE:= 0;SUSLDTRK_ACTIVE := 0;IF 64-bit Mode
THEN
RIP:= fallbackRIP;
ELSE
EIP := fallbackEIP;
FI;
END
None.
XABORT void _xabor t( unsigned int);
None.Opcode/Instruction Op/ 
C6 F8 ib
XABORT imm8A V/V RTM Causes an RTM abort if in RTM execution.
Op/En Operand 1 Operand2 Operand3 Operand4
Ai m m 8 N / A N / A N / AXABORT—Transactional AbortINSTRUCTION SET REFERENCE, W-Z
6-18 Vol. 2DOther Exceptions
#UD CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.
If LOCK prefix is used.XACQUIRE/XRELEASE—Hardware Lock Elision Prefix HintsINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-19XACQUIRE/XRELEASE—Hardware Lock Elision Prefix Hints
The XACQUIRE prefix is a hint to start lock elision on  the memory address specified by the instruction and the 
XRELEASE prefix is a hint to end lock elision on  the memory address specified by the instruction.
The XACQUIRE prefix hint can only be used with the follow ing instructions (these instructions are also referred to 
as XACQUIRE-enabled when used with the XACQUIRE prefix):
•Instructions with an explicit LOCK prefix (F0H) prep ended to forms of the instru ction where the destination 
operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. 
•The XCHG instruction either with or without the presence of the LOCK prefix. 
The XRELEASE prefix hint can only be used with the follo wing instructions (also referred to as XRELEASE-enabled 
when used with the XRELEASE prefix):
operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT, 
OR, SBB, SUB, XOR, XADD, and XCHG. 
•The “MOV mem, reg” (Opcode 88H/89H) and “MOV mem,  imm” (Opcode C6H/C7H) instructions. In these 
cases, the XRELEASE is recognized without the presence of the LOCK prefix.
The lock variables must satisfy the guidelines described in Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, Section 16.3.3, for elision to be  successful, otherwise an HLE abort may be signaled.
If an encoded byte sequence that me ets XACQUIRE/XRELEASE requirements in cludes both prefixes, then the HLE 
semantic is determined by the prefix byte that is placed  closest to the instruction opcode. For example, an F3F2C6 
will not be treated as a XRELEASE-enabled instruction si nce the F2H (XACQUIRE) is closest to the instruction 
opcode C6. Similarly, an F2F3F0 prefixed instruction wi ll be treated as a XRELEASE-enabled instruction since F3H 
(XRELEASE) is closest to the instruction opcode.Opcode/Instruction 64/32bit 
F2
XACQUIREV/V HLE
1
NOTES:
1. Software is not required to check the HLE feature flag to use XACQUIRE or XRELEASE, as they are treated as regular prefix if  HLE
feature flag reports 0.A hint used with an “XACQUIRE-en abled“ instruction to start lock 
elision on the instruction memory operand address.
F3
XRELEASEV/V HLE A hint used with an “XRELEAS E-enabled“ instruction to end lock 
elision on the instruction memory operand address.XACQUIRE/XRELEASE—Hardware Lock Elision Prefix HintsINSTRUCTION SET REFERENCE, W-Z
6-20 Vol. 2DIntel 64 and IA -32 Compatibility
The effect of the XACQUIRE/XRELEAS E prefix hint is the same in non-64-bit modes and in 64-bit mode.
For instructions that do not support the XACQUIRE hint, the presence of the F2H prefix behaves the same way as 
prior hardware, according to
•REPNE/REPNZ semantics for string instructions,
•Serve as SIMD prefix for legacy SIMD instructions operating on XMM register
•Cause #UD if prepending the VEX prefix.
•Undefined for non-string instructions or other situations.
For instructions that do not support the XRELEASE hint, th e presence of the F3H prefix behaves the same way as in 
•REP/REPE/REPZ semantics for string instructions,
Operation
XACQUIRE
IF XACQUIRE-enabled instruction
THEN
IF (HLE_NEST_COUNT  < MAX_HLE_NEST_COUNT) THEN
HLE_NEST_COUNT++IF (HLE_NEST_COUNT = 1) THEN
HLE_ACTIVE  := 1
THEN 
restartRIP  := instruction pointer of the XACQUIRE-enabled instruction
ELSE
restartEIP  := instruction pointer of the XACQUIRE-enabled instruction
FI;Enter HLE Execution (* record register state, start tracking memory state *)
FI; (* HLE_NEST_COUNT = 1*)IF ElisionBufferAvailable 
THEN
Allocate elision bufferRecord address and data for forwarding and commit checkingPerform elision
ELSE

Operation
XACQUIRE
THEN
THEN 
ELSE
THEN
ELSE 
Perform lock acquire operation tr ansactionally but without elision
FI;
ELSE (* HLE_NEST_COUNT  = MAX_HLE_NEST_COUNT*)
GOTO HLE_ABORT_PROCESSING
FI;
ELSE
Treat instruction as non-XACQUIRE F2H prefixed legacy instruction
FI;XACQUIRE/XRELEASE—Hardware Lock Elision Prefix HintsINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-21XRELEASE
IF XRELEASE-enabled instruction 
THEN
IF (HLE_NEST_COUNT  > 0) 
THEN
HLE_NEST_COUNT--IF lock address matches in elision buffer THEN
IF lock satisfies address and value requirements THEN
Deallocate elision buffer
ELSE
FI;
FI;IF (HLE_NEST_COUNT = 0) 
THEN
IF NoAllocatedE lisionBuffer 
THEN
Try to commit transactional executionIF fail to commit transactional execution 
THEN
GOTO HLE_ABORT_PROCESSING;
ELSE (* commit success *)
HLE_ACTIVE  := 0
FI;
ELSE
FI;
FI;
FI; (* HLE_NEST_COUNT  > 0 *)
ELSE 
Treat instruction as non-XRELEASE F3H prefixed legacy instruction
FI;
(* For any HLE abort condition encountered during HLE execution *)
HLE_ABORT_PROCESSING: HLE_ACTIVE  := 0
HLE_NEST_COUNT := 0Restore architectural register stateDiscard memory updates performed in transactionFree any allocated lock elision buffersIF 64-bit mode
THEN 
RIP := restartRIP
ELSE
EIP := restartEIP
FI;Execute and retire instruction at RIP (or EIP) and ignore any HLE hint
ENDXACQUIRE/XRELEASE—Hardware Lock Elision Prefix HintsINSTRUCTION SET REFERENCE, W-Z
6-22 Vol. 2DSIMD Floating-Point Exceptions
None.
#GP(0) If the use of prefix causes in struction length to exceed 15 bytes.XADD—Exchange and AddINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-23XADD—Exchange and Add
Exchanges the first operand (destination operand) with the second operand (source operand), then loads the sum 
of the two values into the destination operand. The destin ation operand can be a register or a memory location; the 
source operand is a register.
IA-32 processors earlier than the Intel486 processor do not recognize this instruction. If this instruction is used, 
you should provide an equivalent code sequence that runs on earlier processors.
Operation
TEMP := SRC + DEST;
SRC := DEST;DEST := TEMP;
The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination 
operand. 
En64-Bit 
0F C0 /r XADD r/m8, r8 MR Valid Valid Excha nge r8 and r/m8; load sum into r/m8.
REX + 0F C0 /r XADD r/m8*, r8* MR Valid N.E. Ex change r8 and r/m8; load sum into r/m8.
0F C1 /r XADD r/m16, r16 MR Valid Valid Exchange r16 and r/m16; load sum into r/m16.0F C1 /r XADD r/m32, r32 MR Valid Valid Exchange r32 and r/m32; load sum into r/m32.REX.W + 0F C1 /r XADD r/m64, r64 MR Valid N.E. Ex change r64 and r/m64; load sum into r/m64.
NOTES:
MR ModRM:r/m (r, w) ModRM:reg (r, w) N/A N/AXADD—Exchange and AddINSTRUCTION SET REFERENCE, W-Z
6-24 Vol. 2DReal-Address Mode Exceptions
#UD If the LOCK prefix is used but the destination is not a memory operand.XBEGIN—Transactional BeginINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-25XBEGIN—Transactional Begin
The XBEGIN instruction specifies the start of an RTM code region. If the logical processor was not already in trans-
actional execution, then the XBEGIN instruction causes the logical processor to transition into transactional execu-tion. The XBEGIN instruction that transitions the logical processor into transactional execution is referred to as the 
outermost XBEGIN instruction. The instruction also specifies a relative offset to compute the address of the fallback 
code path following a transactional abort. (Use of the 16 -bit operand size does not cause this address to be trun-
cated to 16 bits, unlike a near jump to a relative offset.)
On an RTM abort, the logical processor discards all arch itectural register and memory updates performed during 
the RTM execution and restores architectural state to that  corresponding to the outermost XBEGIN instruction. The 
fallback address following an abort is comp uted from the outermost XBEGIN instruction.
Execution of XBEGIN while in a suspend read addr ess tracking region causes a transactional abort.
Operation
XBEGIN
IF RTM_NEST_COUNT < MAX_RTM_NEST_COUNT AND SUSLDTRK_ACTIVE = 0
THEN
RTM_NEST_COUNT++IF RTM_NEST_COUNT = 1 THEN
IF 64-bit Mode
THEN
THEN fallbackRIP := RI P + SignExtend64(rel16);
ELSE fallbackRIP := RIP + SignExtend64(rel32);
FI;IF fallbackRIP is not canonical
FI;
ELSE
THEN fallbackEIP := EIP + SignExtend32(rel16);ELSE fallbackEIP := EIP + rel32;
FI;IF fallbackEIP outsid e code segment limit
FI;
FI;Opcode/Instruction Op/ 
C7 F8
XBEGIN rel16A V/V RTM Specifies the start of an RTM region. Provides a 16-bit relative offset 
to compute the address of the fallb ack instruction address at which 
execution resumes following an RTM abort.
C7 F8
XBEGIN rel32A V/V RTM Specifies the start of an RTM region. Provides a 32-bit relative offset 
A Offset N/A N/A N/AXBEGIN—Transactional BeginINSTRUCTION SET REFERENCE, W-Z
6-26 Vol. 2DRTM_ACTIVE  := 1
Enter RTM Execution (* record register state, start tracking memory state*)
FI; (* RTM_NEST_COUNT = 1 *)
ELSE (* RTM_NEST_COUNT = MAX_RTM_NE ST_COUNT OR SUSLDTRK_ACTIVE = 1 *)
GOTO RTM_ABORT_PROCESSING
FI;
Restore architectura l register state
Discard memory updates performed in transactionUpdate EAX with statusRTM_NEST_COUNT  := 0
RTM_ACTIVE := 0SUSLDTRK_ACTIVE := 0IF 64-bit mode
THEN
RIP := fallbackRIP
ELSE
EIP := fallbackEIP
FI;
END
None.
XBEGIN unsigned int _xbegin( void );
None.
#UD CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.
#GP(0) If the fallback address is outside the CS segment.
#GP(0) If the fallback address is ou tside the address space 0000H and FFFFH.
Same exceptions as in protected mode.XBEGIN—Transactional BeginINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-2764-bit Mode Exceptions

THEN
ELSE
FI;
END
None.
None.
#GP(0) If the fallback address is non-canonical.XCHG—Exchange Register/Memory With RegisterINSTRUCTION SET REFERENCE, W-Z
6-28 Vol. 2DXCHG—Exchange Register/Memory With Register
Exchanges the contents of the destination (first) and source (second) operands. The operands can be two general-
purpose registers or a register and a memory location. If  a memory operand is referenced, the processor’s locking 
protocol is automatically implemented for the duration of the exchange operation, regardless of the presence or 
absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description  in this chapter for more 
information on the locking protocol.)
This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See 
“Bus Locking” in Chapter 9 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for 
more information on bus locking.) 
The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.
En64-Bit 
90+rw XCHG AX, r16 O Valid Valid Exchange r16 with AX.
90+rw XCHG r16, AX O Valid Valid Exchange AX with r16.90+rd XCHG EAX, r32 O Valid Va lid Exchange r32 with EAX.
REX.W + 90+rd XCHG RAX, r64 O Valid N.E. Exchange r64 with RAX.90+rd XCHG r32, EAX O Valid Valid Exchange EAX with r32.REX.W + 90+rd XCHG r64, RAX O Valid N.E. Exchange RAX with r64.86 /r XCHG r/m8, r8 MR Valid Valid Exchange r8 (byte register) with byte from 
r/m8.
REX + 86 /r XCHG r/m8*, r8* MR Valid N.E. Exch ange r8 (byte register) with byte from 
r/m8.
86 /r XCHG r8, r/m8 RM Valid Valid Excha nge byte from r/m8 with r8 (byte 
REX + 86 /r XCHG r8*, r/m8* RM Valid N.E. Ex change byte from r/m8 with r8 (byte 
87 /r XCHG r/m16, r16 MR Valid Valid E xchange r16 with word from r/m16.
87 /r XCHG r16, r/m16 RM Valid Valid Exchange word from r/m16 with r16.87 /r XCHG r/m32, r32 MR Valid Valid Exc hange r32 with doubleword from r/m32.
REX.W + 87 /r XCHG r/m64, r64 MR Valid N.E. Exchange r64 with quadword from r/m64.87 /r XCHG r32, r/m32 RM Valid Valid Exchange doubleword from r/m32 with r32.REX.W + 87 /r XCHG r64, r/m64 RM Valid N.E. Exchange quadword from r/m64 with r64.
NOTES:
O AX/EAX/RAX (r, w) opcode + rd (r, w) N/A N/AO opcode + rd (r, w) AX/EAX/RAX (r, w) N/A N/A
RM ModRM:reg (w) ModRM:r/m (r) N/A N/AXCHG—Exchange Register/Memory With RegisterINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-29NOTE
XCHG (E)AX, (E)AX (encoded instru ction byte is 90H) is an alias for NOP regardless of data size 
prefixes, including REX.W.
Operation
TEMP := DEST;
DEST := SRC;SRC := TEMP;
None.
#GP(0) If either operand is in a non-writable segment.
#UD If the LOCK prefix is used but th e destination is not a memory operand.XEND—Transactional EndINSTRUCTION SET REFERENCE, W-Z
6-30 Vol. 2DXEND—Transactional End
The instruction marks the end of an RTM code region. If this corresponds to the outermost scope (that is, including 
this XEND instruction, the number of XBEGIN instructions is the same as number of XEND instructions), the logical 
processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will 
rollback all architectural register and memory updates pe rformed during the RTM execution. The logical processor 
will resume execution at the fallback address computed fr om the outermost XBEGIN instruction. The EAX register 
is updated to reflect RTM abort information.
Execution of XEND outside a transactional region causes a general-protection exception (#GP). Execution of XEND 
while in a suspend read address tracking region causes a transactional abort.
Operation
XEND
IF (RTM_ACTIVE = 0) THEN
SIGNAL #GP
ELSE
IF SUSLDTRK_ACTIVE = 1
THEN GOTO RTM_ABORT_PROCESSING;
FI;RTM_NEST_COUNT--IF (RTM_NEST_COUNT = 0) THEN
Try to commit transactionIF fail to commit transactional execution
THEN
RTM_ACTIVE  := 0
FI;
FI;
FI;
Discard memory updates performed in transactionUpdate EAX with statusRTM_NEST_COUNT := 0RTM_ACTIVE  := 0
SUSLDTRK_ACTIVE := 0IF 64-bit Mode
THENOpcode/Instruction Op/ 
NP 0F 01 D5
XENDA V/V RTM Specifies the end of an RTM code region.
A N/A N/A N/A N/AXEND—Transactional EndINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-31RIP := fallbackRIP
ELSE
FI;
END
None.
XEND void _xend( void );
None.
#GP(0) If RTM_ACTIVE = 0.XGETBV—Get Value of Extended Control RegisterINSTRUCTION SET REFERENCE, W-Z
6-32 Vol. 2DXGETBV—Get Value of Extended Control Register
Reads the contents of the extended control register (XCR) specified in the ECX register into registers EDX:EAX. (On 
processors that support the Intel 64 architecture, the high -order 32 bits of RCX are ignored.) The EDX register is 
loaded with the high-order 32 bits of the XCR and the EAX register is loaded with the low-order 32 bits. (On proces-
sors that support the Intel 64 architecture, the high-order  32 bits of each of RAX and RDX are cleared.) If fewer 
than 64 bits are implemented in the XCR being read, the values returned to  EDX:EAX in unimplemented bit loca-
tions are undefined.
XCR0 is supported on any processor that supports the XGETBV instruction. If 
CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 1, executing XGETBV with ECX = 1 returns in EDX:EAX the logical-
AND of XCR0 and the current value of the XINUSE state-component bitmap. This allows software to discover the state of the init optimization used by XSAVEOPT and XSAVES. See Chapter 13, “Managing State Using the XSAVE 
Feature Set‚” in Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Use of any other value for ECX results in a general-protection (#GP) exception.
Operation
EDX:EAX := XCR[ECX];
None.
XGETBV unsigned __int64 _xgetbv( unsigned int);
#GP(0) If an invalid XCR is specified in ECX (includes ECX = 1 if 
CPUID.(EAX=0DH,ECX=1):E AX.XG1[bit 2] = 0).
#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.
If CR4.OSXSAVE[bit 18] = 0.If the LOCK prefix is used.

Operation
None.
En64-Bit 
NP 0F 01 D0 XGETBV ZO Valid Valid Reads an  XCR specified by ECX into EDX:EAX.
ZO N/A N/A N/A N/AXGETBV—Get Value of Extended Control RegisterINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-33Compatibility Mode Exceptions
Same exceptions as in protected mode.XLAT/XLATB—Table Look-up TranslationINSTRUCTION SET REFERENCE, W-Z
6-34 Vol. 2DXLAT/XLATB—Table Look-up Translation
Locates a byte entry in a table in memory, using the contents  of the AL register as a table index, then copies the 
contents of the table entry back into the AL register. The in dex in the AL register is treated as an unsigned integer. 
The XLAT and XLATB instructions get the base address of the table in memory from either the DS:EBX or the DS:BX 
registers (depending on the address-size attribute of the in struction, 32 or 16, respecti vely). (The DS segment may 
be overridden with a segment override prefix.)
At the assembly-code level, two forms of this instructio n are allowed: the “explicit-operand” form and the “no-
operand” form. The explicit-operand form (specified with the XLAT mnemonic) allows the base address of the table 
to be specified explicitly with a symb ol. This explicit-operands form is provided to allow documentation; however, 
note that the documentation provided by this form can be misleading. That is, the symbol does not have to specify 
the correct base address. The base address is always sp ecified by the DS:(E)BX regist ers, which must be loaded 
correctly before the XLAT instruction is executed.
The no-operands form (XLATB) provides a “short form” of the XLAT instructions. Here also the processor assumes 
that the DS:(E)BX registers contain the base address of the table.
In 64-bit mode, operation is similar to that in legacy or  compatibility mode. AL is used to specify the table index 
(the operand size is fixed at 8 bits). RBX, however, is used to specify the table’s base address. See the summary 
chart at the beginning of this section for encoding data and limits.
Operation
THEN
AL := (DS:BX + ZeroExtend(AL));
ELSE IF (AddressSize = 32)
AL := (DS:EBX + ZeroExtend(AL)); FI;
ELSE (AddressSize = 64)
AL := (RBX + ZeroExtend(AL));
FI;
En64-Bit 
D7 XLAT m8 ZO Valid Valid Set AL to me mory byte DS:[(E)BX + unsigned 
AL].
D7 XLATB ZO Valid Valid Set AL to me mory byte DS:[(E)BX + unsigned 
AL].
REX.W + D7 XLATB ZO Valid N.E. Set AL to memory byte [RBX + unsigned AL].
ZO N/A N/A N/A N/AXLAT/XLATB—Table L ook-up TranslationINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-35Protected Mode Exceptions
#UD If the LOCK prefix is used.XOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, W-Z
6-36 Vol. 2DXOR—Logical Exclusive OR
Performs a bitwise exclusive OR (XOR) operation on the destination (first) and source (second) operands and 
stores the result in the destination operand location. Th e source operand can be an immediate, a register, or a 
memory location; the destination operand can be a regist er or a memory location. (However, two memory oper-
ands cannot be used in one instruction.) Each bit of the result is 1 if the corresponding bits of the operands are 
different; each bit is 0 if the corresponding bits are the same.
En64-Bit 
34 ib XOR AL, imm8 I Valid Valid AL XOR imm8.
35 iw XOR AX, imm16 I Valid Valid AX XOR imm16.35 id XOR EAX, imm32 I Valid Valid EAX XOR imm32.REX.W + 35 id XOR RAX, imm32 I Valid N.E. RAX XOR imm32 (sign-extended).80 /6 ib XOR r/m8, imm8 MI Valid Valid r/m8 XOR imm8.REX + 80 /6 ib XOR r/m8*, imm8 MI Valid N.E. r/m8 XOR imm8.81 /6 iw XOR r/m16, imm16 MI Valid Valid r/m16 XOR imm16.81 /6 id XOR r/m32, imm32 MI Valid Valid r/m32 XOR imm32.REX.W + 81 /6 id XOR r/m64, imm32 MI Valid N.E. r/m64 XOR imm32 (sign-extended).83 /6 ib XOR r/m16, imm8 MI Valid Valid r/m16 XOR imm8 (sign-extended).83 /6 ib XOR r/m32, imm8 MI Valid Valid r/m32 XOR imm8 (sign-extended).REX.W + 83 /6 ib XOR r/m64, imm8 MI Vali d N.E. r/m64 XOR imm8 (sign-extended).
30 /r XOR r/m8, r8 MR Valid Valid r/m8 XOR r8.REX + 30 /r XOR r/m8*, r8* MR Valid N.E. r/m8 XOR r8.31 /r XOR r/m16, r16 MR Valid Valid r/m16 XOR r16.31 /r XOR r/m32, r32 MR Valid Valid r/m32 XOR r32.REX.W + 31 /r XOR r/m64, r64 MR Valid N.E. r/m64 XOR r64.32 /r XOR r8, r/m8 RM Valid Valid r8 XOR r/m8.REX + 32 /r XOR r8*, r/m8* RM Valid N.E. r8 XOR r/m8.33 /r XOR r16, r/m16 RM Valid Valid r16 XOR r/m16.33 /r XOR r32, r/m32 RM Valid Valid r32 XOR r/m32.REX.W + 33 /r XOR r64, r/m64 RM Valid N.E. r64 XOR r/m64.NOTES:
MR ModRM:r/m (r, w) ModRM:reg (r) N/A N/ARM ModRM:reg (r, w) ModRM:r/m (r) N/A N/AXOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-37In 64-bit mode, using a REX prefix in the form of REX. R permits access to additional registers (R8-R15). Using a 
Operation
DEST := DEST XOR SRC;
#UD If the LOCK prefix is used but th e destination is not a memory operand.XORPD—Bitwise Logical XOR of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, W-Z
6-38 Vol. 2DXORPD—Bitwise Logical XOR of Packed Do uble Precision Floating-Point Values

Performs a bitwise logical XOR of the two, four or eight pa cked double precision floating-point values from the first 
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand can be a ZMM 
register or a vector memory location. The destination op erand is a ZMM register cond itionally updated with write-
mask k1.
is a YMM register or a 256-bit memory location. The destination operand is a YMM register (conditionally updated 
with writemask k1 in case of EVEX). The upper bits (M AXVL-1:256) of the corresponding ZMM register destination 
is an XMM register or 128-bit memory location. The destin ation operand is an XMM register (conditionally updated 
with writemask k1 in case of EVEX). The upper bits (M AXVL-1:128) of the corresponding ZMM register destination 
Mode 
66 0F 57/r
XORPD xmm1, xmm2/m128A V/V SSE2 Return the bitwise logical XOR of packed double precision 
floating-point values in xmm1 and xmm2/mem.
VEX.128.66.0F.WIG 57 /r
VXORPD xmm1,xmm2, xmm3/m128B V/V AVX Return the bitwise logical XOR of packed double precision 
VEX.256.66.0F.WIG 57 /r
VXORPD ymm1, ymm2, ymm3/m256B V/V AVX Return the bitwise logical XOR of packed double precision 
EVEX.128.66.0F.W1 57 /r
VXORPD xmm1 {k1}{z}, xmm2, 
AVX512DQReturn the bitwise logical XOR of packed double precision 
EVEX.256.66.0F.W1 57 /r
VXORPD ymm1 {k1}{z}, ymm2, 
EVEX.512.66.0F.W1 57 /r
VXORPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstC V/V AVX512DQ Return the bitwise logical XOR of packed double precision 
BN / A M o d R M : r e g  ( w ) V E X . v v vv (r) ModRM:r/m (r) N/A
CF u l l M o d R M : r e g  ( w ) E V E X . v vvv (r) ModRM:r/m (r) N/AXORPD—Bitwise Logical XOR of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-39Operation
VXORPD (EVEX Encoded Versions)
THEN DEST[i+63:i] := SRC1[i+63:i] BITWISE XOR SRC2[63:0];ELSE DEST[i+63:i] := SRC1[i+63:i] BITWISE XOR SRC2[i+63:i];
FI;
ELSE 
FI
FI;
VXORPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0] BITWISE XOR SRC2[63:0]DEST[127:64] := SRC1[127:64] BITWISE XOR SRC2[127:64]DEST[191:128] := SRC1[191:128] BITWISE XOR SRC2[191:128]DEST[255:192] := SRC1[255:192] BITWISE XOR SRC2[255:192]DEST[MAXVL-1:256] := 0
VXORPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0] BITWISE XOR SRC2[63:0]DEST[127:64] := SRC1[127:64] BITWISE XOR SRC2[127:64]DEST[MAXVL-1:128] := 0
XORPD (128-bit Legacy SSE Version)
DEST[63:0] := DEST[63:0] BITWISE XOR SRC[63:0]DEST[127:64] := DEST[127:64] BITWISE XOR SRC[127:64]DEST[MAXVL-1:128 ] (Unmodified)
VXORPD __m512d _mm512_xor_pd (__m512d a, __m512d b);
VXORPD __m512d _mm512_mask_xor_pd (__m512d a, __mmask8 m, __m512d b);VXORPD __m512d _mm512_maskz_xor_pd (__mmask8 m, __m512d a);VXORPD __m256d _mm256_xor_pd (__m256d a, __m256d b);VXORPD __m256d _mm256_mask_xor_pd (__m256d a, __mmask8 m, __m256d b);VXORPD __m256d _mm256_maskz_xor_pd (__mmask8 m, __m256d a);XORPD __m128d _mm_xor_pd (__m128d a, __m128d b);VXORPD __m128d _mm_mask_xor_pd ( __m128d a, __mmask8 m, __m128d b);
VXORPD __m128d _mm_maskz_xor_pd (__mmask8 m, __m128d a);
None.XORPD—Bitwise Logical XOR of Packed Do uble Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, W-Z
6-40 Vol. 2DOther Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E4 Class Exception Conditions.”XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-41XORPS—Bitwise Logical XOR of Packed Si ngle Precision Floating-Point Values
Performs a bitwise logical XOR of the four, eight or sixteen  packed single-precision floating-point values from the 
first source operand and the second source operand,  and stores the result in the destination operand
register or a vector memory location. The destination op erand is a ZMM register conditionally updated with write-
mask k1.
is a YMM register or a 256-bit memory location. The destin ation operand is a YMM register (conditionally updated 
VEX.128 and EVEX.128 encoded versions: The first source op erand is an XMM register. The second source operand 
Mode 
NP 0F 57 /r
XORPS xmm1, xmm2/m128A V/V SSE Return the bitwise logical XOR of packed single-
precision floating-point values in xmm1 and 
xmm2/mem.
VEX.128.0F.WIG 57 /r
VXORPS xmm1,xmm2, xmm3/m128B V/V AVX Return the bitwise logical XOR of packed single-
precision floating-point values in xmm2 and xmm3/mem.
VEX.256.0F.WIG 57 /r
VXORPS ymm1, ymm2, ymm3/m256B V/V AVX Return the bitwise logical XOR of packed single-
precision floating-point values in ymm2 and 
ymm3/mem.
EVEX.128.0F.W0 57 /r
VXORPS xmm1 {k1}{z}, xmm2, 
AVX512DQReturn the bitwise logica l XOR of packed single-
precision floating-point values in xmm2 and 
xmm3/m128/m32bcst subject to writemask k1.
EVEX.256.0F.W0 57 /r
VXORPS ymm1 {k1}{z}, ymm2, 
ymm3/m256/m32bcst subject to writemask k1.
EVEX.512.0F.W0 57 /r
VXORPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstC V/V AVX512DQ Return the bitwise logical XOR of packed single-
precision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1.
C Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AXORPS—Bitwise Logical XOR of Packed Si ngle Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, W-Z
6-42 Vol. 2DOperation
VXORPS (EVEX Encoded Versions)
THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE XOR SRC2[31:0];ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE XOR SRC2[i+31:i];
FI;
ELSE 
FI
FI;
VXORPS (VEX.256 Encoded Version)

FI;
ELSE 
FI
FI;
DEST[31:0] := SRC1[31:0] BITWISE XOR SRC2[31:0]DEST[63:32] := SRC1[63:32] BITWISE XOR SRC2[63:32]DEST[95:64] := SRC1[95:64] BITWISE XOR SRC2[95:64]DEST[127:96] := SRC1[127:96] BITWISE XOR SRC2[127:96]DEST[159:128] := SRC1[159:128] BITWISE XOR SRC2[159:128]DEST[191:160] := SRC1[191:160] BITWISE XOR SRC2[191:160]DEST[223:192] := SRC1[223:192] BITWISE XOR SRC2[223:192]DEST[255:224] := SRC1[255:224] BITWISE XOR SRC2[255:224].DEST[MAXVL-1:256] := 0
VXORPS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] BITWISE XOR SRC2[31:0]DEST[63:32] := SRC1[63:32] BITWISE XOR SRC2[63:32]DEST[95:64] := SRC1[95:64] BITWISE XOR SRC2[95:64]DEST[127:96] := SRC1[127:96] BITWISE XOR SRC2[127:96]DEST[MAXVL-1:128] := 0
XORPS (128-bit Lega cy SSE Version)
DEST[31:0] := SRC1[31:0] BITWISE XOR SRC2[31:0]DEST[63:32] := SRC1[63:32] BITWISE XOR SRC2[63:32]DEST[95:64] := SRC1[95:64] BITWISE XOR SRC2[95:64]DEST[127:96] := SRC1[127:96] BITWISE XOR SRC2[127:96]DEST[MAXVL-1:128] (Unmodified)XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-43Intel C/C++ Compiler Intrinsic Equivalent
VXORPS __m512 _mm512_xor_ps (__m512 a, __m512 b);
VXORPS __m512 _mm512_mask_xor_ps ( __m512 a, __mmask16 m, __m512 b);
VXORPS __m512 _mm512_maskz_xor _ps (__mmask16 m, __m512 a);
VXORPS __m256 _mm256_xor_ps (__m256 a, __m256 b);VXORPS __m256 _mm256_mask_xor_ps (__m256 a, __mmask8 m, __m256 b);
VXORPS __m256 _mm256_maskz_xor_ps (__mmask8 m, __m256 a);XORPS __m128 _mm_xor_ps (__m128 a, __m128 b);VXORPS __m128 _mm_mask_xor_ps ( __m128 a, __mmask8 m, __m128 b);
VXORPS __m128 _mm_maskz_xor_ ps (__mmask8 m, __m128 a);
None.
EVEX-encoded instructions, see Table 2-49,  “Type E4 Class Exception Conditions.”XRESLDTRK—Resume Trac king Load AddressesINSTRUCTION SET REFERENCE, W-Z
6-44 Vol. 2DXRESLDTRK—Resume Tracking Load Addresses
The instruction marks the end of an Inte l TSX (RTM) suspend load address tracking region. If the instruction is used 
inside a suspend load address tracking region it will end the suspend region and all following load addresses will be 
added to the transaction read set. If this instruction is us ed inside an active transaction but not in a suspend region 
it will cause transaction abort.
If the instruction is used outside of a transactional region it behaves like a NOP.Chapter 16, “Programming with Intel® Transactio nal Synchronization Extensions‚” in the Intel
Architectures Software Developer’s Manual, Volume 1 provides additional information on Intel® TSX Suspend Load 
Address Tracking.
Operation
XRESLDTRK
IF RTM_ACTIVE = 1:
IF SUSLDTRK_ACTIVE = 1:
SUSLDTRK_ACTIVE := 0
ELSE:
RTM_ABORT
ELSE:
NOP
None.
XRESLDTRK void _xresldtrk(void);
None.
#UD If CPUID.(EAX=7, ECX=0):EDX.TSXLDTRK[bit 16] = 0.
If the LOCK prefix is used.Opcode/
Mode 
F2 0F 01 E9
XRESLDTRKZO V/V TSXLDTRK Specifies the end of an Intel TSX suspend read 
address tracking region.
ZO N/A N/A N/A N/A N/AXRSTOR—Restore Processor Extended StatesINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-45XRSTOR—Restore Processor Extended States
Performs a full or partial restore of processor state components from the XSAVE area located at the memory 
address specified by the source operan d. The implicit EDX:EAX register pair  specifies a 64-bit instruction mask. 
The specific state components restored correspond to th e bits set in the requested-feature bitmap (RFBM), which 
is the logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 1. Like FXRSTOR and FXSAVE, the memory format used for x87 state depends 
on a REX.W prefix; see Section 13.5.1, “x87 State” of Intel® 64 and IA-32 Architectures Software Developer’s 
Section 13.8, “Operation of XRSTOR,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a high-
level outline:
•Execution of XRSTOR may take one of two forms: standa rd and compacted. Bit 63 of the XCOMP_BV field in the 
XSAVE header determines which form is used: value 0 sp ecifies the standard form, while value 1 specifies the 
compacted form.
•If RFBM[ i] = 0, XRSTOR does not update state component i.1
•If RFBM[ i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header, XRSTOR initializes state 
component i.
•If RFBM[ i]=  1  a n d  X S T A T E _ B V [ i] = 1, XRSTOR loads state component i from the XSAVE area.
•The standard form of XRSTOR treats MXCSR (which is part of state component 1 — SSE) differently from the 
XMM registers. If either form attempts to load MXCS R with an illegal value, a general-protection exception 
(#GP) occurs.
•XRSTOR loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of XSAVEOPT or XSAVES.
•Immediately following an execution of XRSTOR, the processo r tracks as in-use (not in initial configuration) any 
state component i for which RFBM[ i] = 1 and XSTATE_BV[ i] = 1; it tracks as modified any state component 
ifor which RFBM[ i]=  0 .
Use of a source operand not aligned to 64-byte boundary (f or 64-bit and 32-bit modes) results in a general-protec-
tion (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.
See Section 13.6, “Processor Tracking of XSAVE-Managed State,” of Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1 for discussion of the bitmaps XINUSE and XMODIFIED and of the quantity 
XRSTOR_INFO.Opcode /
Mode 
Feature 
NP 0F AE /5
XRSTOR memM V/V XSAVE Restore state componen ts specified by EDX:EAX from 
mem.
NP REX.W + 0F AE /5
XRSTOR64 memM V/N.E. XSAVE Restore state components specified by EDX:EAX from 
mem.
1. There is an exception if RFBM[1] = 0 and RFBM[2] = 1. In this case, th e standard form of XRSTOR will load MXCSR from memory, 
even though MXCSR is part of state component 1 — SSE. Th e compacted form of XRSTOR do es not make this exception.XRSTOR—Restore Processor Extended StatesINSTRUCTION SET REFERENCE, W-Z
6-46 Vol. 2DOperation
RFBM := XCR0 AND EDX:EAX; /* bitwise logical AND */
COMPMASK := XCOMP_BV fi eld from XSAVE header;
RSTORMASK := XSTATE_BV field from XSAVE header;
IF COMPMASK[63] = 0
THEN
/* Standard form  of XRSTOR */
TO_BE_RESTORED := RFBM AND RSTORMASK;TO_BE_INITIALIZED := RFBM AND NOT RSTORMASK;
IF TO_BE_RESTORED[0] = 1
THEN
XINUSE[0] := 1;load x87 state from legacy region of XSAVE area;
ELSIF TO_BE_INITIALIZED[0] = 1
THEN
XINUSE[0] := 0;initialize x87 state;
FI;
IF RFBM[1] = 1 OR RFBM[2] = 1
THEN load MXCSR from legacy region of XSAVE area;
FI;
IF TO_BE_RESTORED[1] = 1
THEN
XINUSE[1] := 1;load XMM registers from legacy  region of XSAVE area; // th is step does not load MXCSR
ELSIF TO_BE_INITIALIZED[1] = 1
THEN
XINUSE[1] := 0;set all XMM registers to 0; // this  step does not initialize MXCSR
FI;
FOR i := 2 TO 62 
IF TO_BE_RESTORED[i] = 1
THEN
XINUSE[i] := 1;load XSAVE state component i at offset n from base of XSAVE area;
// n enumerated by CPUID(EAX=0DH,ECX=i):EBX)
ELSIF TO_BE_INITIALIZED[i] = 1
THEN
XINUSE[i] := 0;initialize XSAVE state component i;
FI;
ENDFOR;
ELSE
/* Compacted form of XRSTOR */IF CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0
THEN /* compacted fo rm not supported */
#GP(0);
FI;XRSTOR—Restore Processor Extended StatesINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-47FORMAT = COMPMASK AND 7FFFFFFF_FFFFFFFFH;
RESTORE_FEATURES = FORMAT AND RFBM;TO_BE_RESTORED := RESTORE_FEATURES AND RSTORMASK;FORCE_INIT := RFBM AND NOT FORMAT;TO_BE_INITIALIZED = (RFBM AND NO T RSTORMASK) OR FORCE_INIT;
THEN
THEN
FI;
THEN
XINUSE[1] := 1;load SSE state from legacy region of XSAVE area ; // this step loads the XMM registers and MXCSR
THEN
set all XMM registers to 0;XINUSE[1] := 0;MXCSR := 1F80H;
FI;
NEXT_FEATURE_OFFSET = 576; // Legacy area and XSAVE header consume 576 bytes
FOR i := 2 TO 62  
IF FORMAT[i] = 1
THEN
THEN
XINUSE[i] := 1;load XSAVE state component i at offset NEXT _FEATURE_OFFSET from base of XSAVE area;
FI;NEXT_FEATURE_OFFSET = NEXT_FEATURE_OFFSET + n (n enumerated by CPUID(EAX=0DH,ECX=i):EAX);
FI;IF TO_BE_INITIALIZED[i] = 1
THEN
FI;
ENDFOR;

THEN
THEN
FI;
THEN
THEN
FI;
THEN
THEN
THEN
FI;
ENDFOR;
FI;
XMODIFIED := NOT RFBM;IF in VMX non-root operation
THEN VMXNR := 1;ELSE VMXNR := 0;
FI;LAXA := linear address of XSAVE area;XRSTOR—Restore Processor Extended StatesINSTRUCTION SET REFERENCE, W-Z
6-48 Vol. 2DXRSTOR_INFO := CPL,VMXNR,LAXA,COMPMASK ;
None.
XRSTOR void _xrstor( void * , unsigned __int64);
XRSTOR void _xrstor64( void * , unsigned __int64);
If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and 
CPUID.(EAX=0DH,ECX=1):E AX.XSAVEC[bit 1] = 0.
If the standard form is executed and a bit in  XCR0 is 0 and the corresponding bit in the 
XSTATE_BV field of the XSAVE header is 1.
If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.
If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the 
XCOMP_BV field of the XSAVE header is 1.
If the compacted form is executed and a bit in  the XCOMP_BV field in the XSAVE header is 0 
and the corresponding bit in the XSTATE_BV field is 1.
If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.
If attempting to write any reserved bits of the MXCSR register with 1.
If CR4.OSXSAVE[bit 18] = 0.
operand is not aligned on a 64-byte boundary, as described above. If the alignment check 
vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place. In addition, the width of the alignment 
#GP If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
XCOMP_BV field of the XSAVE header is 1.XRSTOR—Restore Processor Extended StatesINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-49If the compacted form is executed and a bit in  the XCOMP_BV field in the XSAVE header is 0 
#NM If CR0.TS[bit 3] = 1.#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.
CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
If the compacted form is executed and a bit in  XCR0 is 0 and the corresponding bit in the 
#PF(fault-code) If a page fault occurs.#NM If CR0.TS[bit 3] = 1.
misalignments).XRSTORS—Restore Processor Extended States SupervisorINSTRUCTION SET REFERENCE, W-Z
6-50 Vol. 2DXRSTORS—Restore Processor Ex tended States Supervisor
address specified by the source operand. The implicit EDX: EAX register pair specifies a 64-bit instruction mask. The 
specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the 
logical-AND of EDX:EAX and the logical-OR of XCR0 with  the IA32_XSS MSR. XRSTORS may be executed only if 
CPL = 0.
Section 13.12, “Operation of XRSTORS,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a 
high-level outline:
•Execution of XRSTORS is similar to that of the comp acted form of XRSTOR; XRST ORS cannot restore from an 
XSAVE area in which the extended region is in the standa rd format (see Section 13.4.3, “Extended Region of an 
XSAVE Area” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
•XRSTORS differs from XRSTOR in that it can restore state components corresponding to bits set in the 
IA32_XSS MSR.
•If RFBM[ i] = 0, XRSTORS does not update state component i.
•If RFBM[ i] = 1 and bit i is clear in the XSTATE_BV field in th e XSAVE header, XRSTORS initializes state 
•If RFBM[ i]=  1  a n d  X S T A T E _ B V [ i] = 1, XRSTORS loads state component i from the XSAVE area.
•If XRSTORS attempts to load MXCSR with an illegal value, a general-protection exception (#GP) occurs.
•XRSTORS loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of 
XSAVEOPT or XSAVES.
•Immediately following an execution of XRSTORS, the proce ssor tracks as in-use (not in initial configuration) 
any state component i for which RFBM[ i] = 1 and XSTATE_BV[ i] = 1; it tracks as modified any state component 
Mode 
Feature 
NP 0F C7 /3
XRSTORS memM V/V XSS Restore state components  specified by EDX:EAX from 
mem.
NP REX.W + 0F C7 /3
XRSTORS64 memM V/N.E. XSS Restore state components specified by EDX:EAX from 
mem.
M ModRM:r/m (r) N/A N/A N/AXRSTORS—Restore Processor Ex tended States SupervisorINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-51Operation
RFBM := (XCR0 OR IA32_XSS) AND EDX: EAX; /* bitwise logi cal OR and AND */
FORMAT = COMPMASK AND 7FFFFFFF_FFFFFFFFH;

Mode 
Feature 
NP 0F C7 /3
mem.
mem.
RESTORE_FEATURES = FORMAT AND RFBM;TO_BE_RESTORED := RESTORE_FEATURES AND RSTORMASK;FORCE_INIT := RFBM AND NOT FORMAT;TO_BE_INITIALIZED = (RFBM AND NOT RSTORMASK) OR FORCE_INIT;
THEN
THEN
FI;
THEN
THEN
FI;
NEXT_FEATURE_OFFSET = 576; // Legacy ar ea and XSAVE header consume 576 bytes
THEN
THEN
FI;NEXT_FEATURE_OFFSET = NEXT_FEATURE_OFFSET + n (n enumerated by CPUI D(EAX=0DH,ECX=i):EAX);
THEN
FI;
ENDFOR;
THEN VMXNR := 1;XRSTORS—Restore Processor Extended States SupervisorINSTRUCTION SET REFERENCE, W-Z
6-52 Vol. 2DELSE VMXNR := 0;
FI;LAXA := linear addr ess of XSAVE area;
XRSTOR_INFO := 
CPL,VMXNR,LAXA,COMPMASK ;
None.
XRSTORS void _xrstors( void * , unsigned __int64);XRSTORS64 void _xrstors64( void * , unsigned __int64);
#GP(0) If CPL > 0.
If bit 63 of the XCOMP_BV field of the XSAVE header is 0.
If a bit in XCR0|IA32_XSS is 0 and the correspon ding bit in the XCOMP_BV field of the XSAVE 
header is 1.
If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the 
XSTATE_BV field is 1.
If bytes 63:16 of the XSAVE header are not all zero.
#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or  CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
If bit 63 of the XCOMP_BV field of the XSAVE header is 0.If a bit in XCR0|IA32_XSS is 0 and the correspon ding bit in the XCOMP_BV field of the XSAVE 
Same exceptions as in protected mode.XRSTORS—Restore Processor Ex tended States SupervisorINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-53Compatibility Mode Exceptions
If bytes 63:16 of the XSAVE header are not all zero.If attempting to write any reserved bits of the MXCSR register with 1.
#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
If the LOCK prefix is used.XSAVE—Save Processor Extended StatesINSTRUCTION SET REFERENCE, W-Z
6-54 Vol. 2DXSAVE—Save Processor Extended States
Performs a full or partial save of processor state comp onents to the XSAVE area lo cated at the memory address 
specified by the destination operand. The implicit EDX:EA X register pair specifies a 64-bit instruction mask. The 
specific state components saved correspond to the bits se t in the requested-feature bitmap (RFBM), which is the 
logical-AND of EDX:EAX and XCR0.
Section 13.7, “Operation of XSAVE,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 
provides a detailed description of the operation of the XS AVE instruction. The following items provide a high-level 
outline:
•XSAVE saves state component i if and only if RFBM[ i]=  1 .1
•XSAVE does not modify bytes 511:464 of the legacy re gion of the XSAVE area (see Section 13.4.1, “Legacy 
Region of an XSAVE Area” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
•XSAVE reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2, “XSAVE Header” of Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 1) and writes a modified value back to memory as 
follows. If RFBM[ i] = 1, XSAVE writes XSTATE_BV[ i] with the value of XINUSE[ i]. (XINUSE is a bitmap by which 
the processor tracks the status of various state components. See Section 13.6, “Processor Tracking of XSAVE-
Managed State” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.) If RFBM[ i]=  0 ,  
XSAVE writes XSTATE_BV[ i] with the value that it read from memory  (it does not modify the bit). XSAVE does 
not write to any part of the XSAVE he ader other than the XSTATE_BV field.
•XSAVE always uses the standard format of the exte nded region of the XSAVE area (see Section 13.4.3, 
“Extended Region of an XSAVE Area” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1).
Use of a destination operand not alig ned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a 
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.Opcode /
Mode 
Feature 
NP 0F AE /4
XSAVE memM V/V XSAVE Save state components specified by EDX:EAX to mem.
NP REX.W + 0F AE /4
XSAVE64 memM V/N.E. XSAVE Save state components specified by EDX:EAX to mem.
1. An exception is made for MXCSR and MXCSR_MASK, which belong to state component 1 — SSE. XSAVE saves these values to mem-
ory if either RFBM[1 ] or RFBM[2] is 1.XSAVE—Save Processor Extended StatesINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-55Operation
OLD_BV := XSTATE_BV field from XSAVE header;
IF RFBM[0] = 1
THEN store x87 state into legacy region of XSAVE area;
FI;
IF RFBM[1] = 1
THEN store XMM registers into legacy region of XSAVE area; // this step does no t save MXCSR or MXCSR_MASK
FI;
THEN store MXCSR and MX CSR_MASK into legacy region of XSAVE area;
FI;
FOR i := 2 TO 62
IF RFBM[i] = 1
THEN save XSAVE state component i at offset n from base of XSAVE area (n enumerated by CPUID(EAX=0DH,ECX=i):EBX);
FI;
ENDFOR;
XSTATE_BV field in XSAVE header := (OLD_BV AND NOT RFBM) OR (XINUSE AND RFBM);
None.
XSAVE void _xsave( void * , unsigned __int64);
XSAVE void _xsave64( void * , unsigned __int64);
vary with implementation, as follows. In all implementations where #AC is not signaled, a

None.
misalignments).XSAVE—Save Processor Extended StatesINSTRUCTION SET REFERENCE, W-Z
6-56 Vol. 2DReal-Address Mode Exceptions
misalignments).XSAVEC—Save Processor Extended States With CompactionINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-57XSAVEC—Save Processor Extended States With Compaction
Section 13.10, “Operation of XSAVEC,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
1 provides a detailed description of the operation of the XSAVEC instruction. The following items provide a high-
•Execution of XSAVEC is similar to that  of XSAVE. XSAVEC differs from XSAVE in that it uses compaction and that 
it may use the init optimization.
•XSAVEC saves state component i if and only if RFBM[ i]=  1  a n d  X I N U S E [ i]=  1 .1 (XINUSE is a bitmap by which 
the processor tracks the status of various state components. See Section 13.6, “Processor Tracking of XSAVE-Managed State” of Intel
® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 1.)
•XSAVEC does not modify bytes 511:464 of the legacy re gion of the XSAVE area (see Section 13.4.1, “Legacy 
Region of an XSAVE Area” of Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 1).
•XSAVEC writes the logical AND of RFBM and XINU SE to the XSTATE_BV field of the XSAVE header.2,3 (See 
Section 13.4.2, “XSAVE Header” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.) 
XSAVEC sets bit 63 of the XCOMP_BV field and sets bits 62:0 of that field to RFBM[62:0]. XSAVEC does not 
write to any parts of the XSAVE header othe r than the XSTATE_BV and XCOMP_BV fields.
•XSAVEC always uses the compacted format of the exte nded region of the XSAVE area (see Section 13.4.3, 
Volume 1).
Use of a destination operand not aligned to 64-byte bound ary (in either 64-bit or 32-bit modes) results in a 
general-protection (#GP) exception. In 64-bit mo de, the upper 32 bits of RDX and RAX are ignored.Opcode /
Mode 
Feature 
NP 0F C7 /4
XSAVEC memM V/V XSAVEC Save state components specified by EDX:EAX to mem with 
compaction.
NP REX.W + 0F C7 /4
XSAVEC64 memM V/N.E. XSAVEC Save state components specified by EDX:EAX to mem with 
1. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not 
have its initial value of 1F80H. In this case , XSAVEC saves SSE state as long as RFBM[1] = 1.
2. Unlike XSAVE and XSAVEO PT, XSAVEC clears bits in the XS TATE_BV field that correspond to bits that are clear in RFBM.
3. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not 
have its initial value of 1F80H. In this case, XSAV EC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.XSAVEC—Save Processor Extended States With CompactionINSTRUCTION SET REFERENCE, W-Z
6-58 Vol. 2DOperation
TO_BE_SAVED := RFBM AND XINU SE; /* bitwise logical AND */
If MXCSR ≠ 1F80H AND RFBM[1]
TO_BE_SAVED[1] = 1;
FI;
IF TO_BE_SAVED[0] = 1
FI;
IF TO_BE_SAVED[1] = 1
THEN store SSE state into legacy region  of XSAVE area; // this step saves th e XMM registers, MXCSR, and MXCSR_MASK
FI;
THEN
IF TO_BE_SAVED[i]
THEN save XSAVE state component i at offset NEXT_FEATURE_OFFSET from base of XSAVE area;
FI;
ENDFOR;
XSTATE_BV field in XSAVE header := TO_BE_SAVED;
XCOMP_BV field in XSAVE header := RFBM OR 80000000_00000000H;
None.
XSAVEC void _xsavec( void  * , unsigned __int64);
XSAVEC64 void _xsavec64( vo id * , unsigned __int64);
#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
If CR4.OSXSAVE[bit 18] = 0.If the LOCK prefix is used.XSAVEC—Save Processor Extended States With CompactionINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-59#AC If this exception is disabled a general protec tion exception (#GP) is signaled if the memory 
If any part of the operand lies outside th e effective address space from 0 to FFFFH.

misalignments).XSAVEOPT—Save Processor Extended States OptimizedINSTRUCTION SET REFERENCE, W-Z
6-60 Vol. 2DXSAVEOPT—Save Processor Extended States Optimized
Section 13.9, “Operation of XSAVEOPT,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
1 provides a detailed description of the operation of the XSAVEOPT instruction. The following items provide a high-
•Execution of XSAVEOPT is similar to that of XSAVE. XSAVEOPT differs from XSAVE in that it may use the init and 
modified optimizations. The performance of XSAVEOPT  will be equal to or better than that of XSAVE.
•XSAVEOPT saves state component i only if RFBM[ i]=  1  a n d  X I N U S E [ i]=  1 .1 (XINUSE is a bitmap by which the 
processor tracks the status of various state components. See Section 13.6, “Processor Tracking of XSAVE-Managed State,” of the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.) Even if both 
bits are 1, XSAVEOPT may optimize and not save state component i if (1) state component i has not been 
modified since the last execution of XRSTOR or XRSTORS; and (2) this execution of XSAVES corresponds to that last execution of XRSTOR or XRSTORS as dete rmined by the internal value XRSTOR_INFO (see the 
Operation section below).
•XSAVEOPT does not modify bytes 511:464 of the legacy re gion of the XSAVE area (see Section 13.4.1, “Legacy 
•XSAVEOPT reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2, “XSAVE Header,” of the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 1) and writes a modified value back to 
memory as follows. If RFBM[ i] = 1, XSAVEOPT writes XSTATE_BV[ i] with the value of XINUSE[ i]. If RFBM[ i]=  
0, XSAVEOPT writes XSTATE_BV[ i] with the value that it read from memory (it does not modify the bit). 
XSAVEOPT does not write to any part of the XSAVE header other than the XSTATE_BV field.
•XSAVEOPT always uses the standard format of the extended region of the XSAVE area (see Section 13.4.3, 
Volume 1).
Use of a destination operand not aligne d to 64-byte boundary (in either 64-bit or 32-bit modes) will result in a 
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.Opcode/
Mode 
Feature 
NP 0F AE /6
XSAVEOPT memM V/V XSAVEOPT Save state compon ents specified by EDX:EAX 
to mem, optimizi ng if possible.
NP REX.W + 0F AE /6
XSAVEOPT64 memM V/V XSAVEOPT Save state compon ents specified by EDX:EAX 
1. There is an exception made for MXCSR and MXCSR_MASK, which belong to state component 1 — SSE. XSAVEOPT always saves 
these to memory if RFBM[1] =  1 or RFBM[2] = 1,  regardless of the value of XINUSE.XSAVEOPT—Save Processor Extended States OptimizedINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-61See Section 13.6, “Processor Tracking of XSAVE-Managed State,” of Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1 for discussion of the bitmap XMODIFIED and of the quantity XRSTOR_INFO.
Operation
OLD_BV := XSTATE_BV field from XSAVE header;TO_BE_SAVED := RFBM AND XINUSE;
IF in VMX non-root operation
FI;LAXA := linear address of XSAVE area;IF XRSTOR_INFO = 
CPL,VMXNR,LAXA,00000000_00000000H 
THEN TO_BE_SAVED := TO_BE_SAVED AND XMODIFIED;
FI;
FI;
IF TO_BE_SAVED[1]
FI;
IF RFBM[1] = 1 or RFBM[2] = 1
FI;
IF TO_BE_SAVED[i] = 1
FI;
ENDFOR;
None.
XSAVEOPT void _xsaveopt( void * , unsigned __int64);
XSAVEOPT void _xsaveopt64( void * , unsigned __int64);
#PF(fault-code) If a page fault occurs.#NM If CR0.TS[bit 3] = 1.XSAVEOPT—Save Processor Extended States OptimizedINSTRUCTION SET REFERENCE, W-Z
6-62 Vol. 2D#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] = 
0.
#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] = 
0.
#NM If CR0.TS[bit 3] = 1.#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] = 
0.

0.
misalignments).XSAVES—Save Processor Extended States SupervisorINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-63XSAVES—Save Processor Exte nded States Supervisor
specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), the logical-
AND of EDX:EAX and the logical-OR of XCR0 with the IA 32_XSS MSR. XSAVES may be executed only if CPL = 0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 1. Like FXRSTO R and FXSAVE, the memory format used for x87 state 
depends on a REX.W prefix; see Section 13.5.1, “x87 State,” of the Intel® 64 and IA-32 Architectures Software 
Section 13.11, “Operation of XSAVES,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1 provides a detailed description  of the operation of the XSAVES instruction. The following items provide a 
•Execution of XSAVES is similar to that of XSAVEC. XSAVES differs from XSAVEC in that it can save state 
components corresponding to bits set in the IA32_XSS  MSR and that it may use the modified optimization.
•XSAVES saves state component i only if RFBM[ i]=  1  a n d  X I N U S E [ i]=  1 .1 (XINUSE is a bitmap by which the 
processor tracks the status of various state compon ents. See Section 13.6, “Processor Tracking of XSAVE-
Managed State,” of the Intel® 64 and IA-32 Architectures Software De veloper’s Manual, Volume 1.) Even if 
both bits are 1, XSAVES may optimize and not save state component i if (1) state component i has not been 
modified since the last execution of XRSTOR or XRSTOR S; and (2) this execution of XSAVES correspond to that 
last execution of XRSTOR or XRSTORS as determined  by XRSTOR_INFO (see the Operation section below).
•XSAVES does not modify bytes 511:464 of the legacy re gion of the XSAVE area (see Section 13.4.1, “Legacy 
Region of an XSAVE Area,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
•XSAVES writes the logical AND of RFBM and XINU SE to the XSTATE_BV field of the XSAVE header.2 (See Section 
13.4.2, “XSAVE Header,” of the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 1.) 
XSAVES sets bit 63 of the XCOMP_BV field and sets bits 62:0 of that field to RFBM[62:0]. XSAVES does not 
•XSAVES always uses the compacted format of the exte nded region of the XSAVE area (see Section 13.4.3, 
“Extended Region of an XSAVE Area,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1).
Mode 
Feature 
NP 0F C7 /5
XSAVES memM V/V XSS Save state components specified by EDX:EAX to 
mem with compaction, optimizing if possible.
NP REX.W + 0F C7 /5
XSAVES64 memM V/N.E. XSS Save state components specified by EDX:EAX to 
have its initial value of 1F80H. In this case, the init optimization does not apply and XSAVEC will save SSE state as long as R FBM[1] = 
1 and the modified optimization is not being applied.
2. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not 
have its initial value of 1F80H. In this case, XSAV ES sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.XSAVES—Save Processor Extended States SupervisorINSTRUCTION SET REFERENCE, W-Z
6-64 Vol. 2DSee Section 13.6, “Processor Tracking of XSAVE-Managed State,” of Intel® 64 and IA-32 Architectures Software 
Operation
RFBM := (XCR0 OR IA32_XSS) AND EDX:EAX; /* bitwise logical OR and AND */
COMPMASK := RFBM OR 80000000_00000000H;TO_BE_SAVED := RFBM AND XINUSE;IF XRSTOR_INFO = 
CPL,VMXNR,LAXA,COMPMASK 
FI;IF MXCSR ≠ 1F80H AND RFBM[1]
THEN TO_BE_SAVED[1] = 1;
FI;
FI;
FI;
THEN
THEN
save XSAVE state component i at offset NEXT_FEATURE_OFFSET from base of XSAVE area;IF i = 8 // state component 8 is for PT state
THEN IA32_RTIT_CTL.TraceEn[bit 0] := 0;
FI;
FI;
ENDFOR;
NEW_HEADER := RFBM AND XINUSE;
IF MXCSR ≠ 1F80H AND RFBM[1]
THEN NEW_HEADER[1] = 1;
FI;XSTATE_BV field in XSAVE header := NEW_HEADER;XCOMP_BV field in XSAV E header := COMPMASK;
None.XSAVES—Save Processor Extended States SupervisorINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-65Intel C/C++ Compiler Intrinsic Equivalent
XSAVES void _xsaves( vo id * , unsigned __int64);
XSAVES64 void _xsaves64( vo id * , unsigned __int64);
#NM If CR0.TS[bit 3] = 1.#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.#PF(fault-code) If a page fault occurs.
If the LOCK prefix is used.XSETBV—Set Extended Control RegisterINSTRUCTION SET REFERENCE, W-Z
6-66 Vol. 2DXSETBV—Set Extended Control Register
Writes the contents of registers EDX:EAX into the 64-bit  extended control register (XCR) specified in the ECX 
register. (On processors that support the Intel 64 architec ture, the high-order 32 bits of RCX are ignored.) The 
contents of the EDX register are copied to high-order 32  bits of the selected XCR and the contents of the EAX 
register are copied to low-order 32 bits of the XCR. (On processors that support the Intel 64 architecture, the high-
order 32 bits of each of RAX and RDX are ignored.) Undefine d or reserved bits in an XCR should be set to values 
previously read.
exception #GP(0) is generated. Specifying a reserved or unimplemented XCR in ECX will also cause a general 
protection exception. The processor will also generate a ge neral protection exception if software attempts to write 
to reserved bits in an XCR.
Currently, only XCR0 is supported. Thus, all other values of ECX are reserved and will cause a #GP(0). Note that 
bit 0 of XCR0 (corresponding to x87 state) must be set to  1; the instruction will cause a #GP(0) if an attempt is 
made to clear this bit. In addition, the instruction causes a #GP(0) if an attempt is made to set XCR0[2] (AVX state) 
while clearing XCR0[1] (SSE state); it is necessary to set both bits to use AVX instructions; Section 13.3, “Enabling

while clearing XCR0[1] (SSE state); it is necessary to set both bits to use AVX instructions; Section 13.3, “Enabling 
the XSAVE Feature Set and XSAVE-Enabled Features,” of Intel® 64 and IA-32 Architectures Software Developer’s 
Operation
XCR[ECX] := EDX:EAX;
None.
XSETBV void _xsetbv( unsign ed int, unsigned __int64);
If an invalid XCR is specified in ECX.If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.
If an attempt is made to clear bit 0 of XCR0.
If an attempt is made to set XCR0[2:1] to 10b.
En64-Bit 
NP 0F 01 D1 XSETBV ZO Valid Valid Write the value in EDX:EAX to the XCR 
specified by ECX.
ZO N/A N/A N/A N/AXSETBV—Set Extended Control RegisterINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-67Real-Address Mode Exceptions
#GP If an invalid XCR is specified in ECX.
If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.
#GP(0) The XSETBV instruction is not recognized in virtual-8086 mode.
Same exceptions as in protected mode.XSUSLDTRK—Suspend Tracking Load AddressesINSTRUCTION SET REFERENCE, W-Z
6-68 Vol. 2DXSUSLDTRK—Suspend Tracking Load Addresses
The instruction marks the start of an Intel TSX (RTM) susp end load address tracking region. If the instruction is 
used inside a transactional region, subsequent loads are not added to the read set of the transaction. If the instruc-
tion is used inside a suspend load address tracking region it will cause transaction abort.
Operation
XSUSLDTRK
IF SUSLDTRK_ACTIVE = 0:
SUSLDTRK_ACTIVE := 1
ELSE:
RTM_ABORT
ELSE:
NOP
None.
XSUSLDTRK void _xsusldtrk(void);
None.
Mode 
F2 0F 01 E8
XSUSLDTRKZO V/V TSXLDTRK Specifies the start of an Intel TSX suspend read 
ZO N/A N/A N/A N/A N/AXTEST—Test if in Transactional ExecutionINSTRUCTION SET REFERENCE, W-Z
Vol. 2D 6-69XTEST—Test if in Transactional Execution 
The XTEST instruction queries the transactional execution st atus. If the instruction executes inside a transaction-
ally executing RTM region or a transactionally executing HL E region, then the ZF flag is cleared, else it is set.
Operation
XTEST
IF (RTM_ACTIVE = 1 OR HLE_ACTIVE = 1)
THEN
ZF := 0
ELSE
ZF := 1
FI;
The ZF flag is cleared if the instruction is executed transa ctionally; otherwise it is set to 1. The CF, OF, SF, PF, and 
AF, flags are cleared.
XTEST int _xtest( void );
None.
#UD CPUID.(EAX=7, ECX=0):EBX.HLE[bit 4] = 0 and CPUID.(EAX=7, ECX= 0):EBX.RTM[bit 11] = 
0.
If LOCK prefix is used.Opcode/Instruction Op/ 
NP 0F 01 D6
XTESTZO V/V HLE or 
RTMTest if executing in a transactional region.
ZO N/A N/A N/A N/AXTEST—Test if in Transactional ExecutionINSTRUCTION SET REFERENCE, W-Z
6-70 Vol. 2DVol. 2D 7-1CHAPTER 7
SAFER MODE EXTENSIONS REFERENCE
7.1 OVERVIEW
This chapter describes the Safer Mode Extensions (SMX) for the Intel 64 and IA-32 architectures. Safer Mode 
Extensions (SMX) provide a programming interface for sy stem software to establish a measured environment 
within the platform to support trust decisions by  end users. The measured environment includes:
•Measured launch of a system executive, referre d to as a Measured Launched Environment (MLE)1. The system 
executive may be based on a Virtual Machine Monitor (VMM), a measured VMM is referred to as MVMM2.
•Mechanisms to ensure the above measurement is protecte d and stored in a secure location in the platform.
•Protection mechanisms that allow the VMM to control attempts to modify the VMM.
The measurement and protection mechanisms used by a me asured environment are supported by the capabilities 
of an Intel® Trusted Execution Technology (Intel® TXT) platform: 
•The SMX are the processor’s programming interface in an Intel TXT platform. 
•The chipset in an Intel TXT platform provides enforcement of the protection mechanisms.
•Trusted Platform Module (TPM) 1.2 in the platform provides platform configuration registers (PCRs) to store 
software measurement values.
7.2 SMX FUNCTIONALITY
SMX functionality is provided in an Intel 64 processor through the GETSEC instruction via leaf functions. The 
GETSEC instruction supports multiple leaf functions. Leaf  functions are selected by the value in EAX at the time 
GETSEC is executed. Each GETSEC leaf function is docu mented separately in the reference pages with a unique 
mnemonic (even though these mnemonics share the same opcode, 0F 37).
7.2.1 Detecting and Enabling SMX
Software can detect support for SMX operation using the CPUID instruction. If software executes CPUID with 1 in 
EAX, a value of 1 in bit 6 of ECX indicates support for SMX operation (GETSEC is available), see CPUID instruction 
for the layout of feature flags of reported by CPUID.01H:ECX.
System software enables SMX operation by setting CR4.SM XE[Bit 14] = 1 before attempting to execute GETSEC. 
Otherwise, execution of GETSEC results in the proc essor signaling an invalid opcode exception (#UD). 
If the CPUID SMX feature flag is clear (CPUID.01H.ECX[Bit 6] = 0), attempting to set CR4.SMXE[Bit 14] results in 
a general protection exception. 
The IA32_FEATURE_CONTROL MSR (at address 03AH) provides  feature control bits that configure operation of 
VMX and SMX. These bits are documented in Table 7-1.
1. See the Intel® Trusted Execution Technology Measured Launched Environment Programming Guide.
2. An MVMM is sometimes referred to as a me asured launched environment (MLE). See the Intel® Trusted Execution Technology Mea-
sured Launched Environment Programming Guide. SAFER MODE EXTENSIONS REFERENCE
7-2 Vol. 2D•Bit 0 is a lock bit. If the lock bit is clear, an attempt to execute VMXON will cause a general-protection exception. 
Attempting to execute GETSEC[SENTER] when the lock bit is clear will also cause a general-protection 
exception. If the lock bit is set, WRMSR to the IA 32_FEATURE_CONTROL MSR will cause a general-protection 
exception. Once the lock bit is set, the MSR cannot be  modified until a power-on reset. System BIOS can use 
this bit to provide a setup option for BIOS to di sable support for VMX, SMX or both VMX and SMX. 
•Bit 1 enables VMX in SMX operation (between executing the SENTER and SEXIT leaves of GETSEC). If this bit is 
clear, an attempt to execute VMXON in SMX will cause a general-protection exception if executed in SMX operation. Attempts to set this bit on logical processo rs that do not support both VMX operation (Chapter 7, 
“Safer Mode Extensions Reference”) and SMX operation cause general-protection exceptions.
•Bit 2 enables VMX outside SMX operation. If this bit is clear, an attempt to execute VMXON will cause a general-
protection exception if executed outside SMX operation. A ttempts to set this bit on logical processors that do 
not support VMX operation cause general-protection exceptions.
•Bits 8 through 14 specify enabled functionality of the SENT ER leaf function. Each bit in the field represents an 
enable control for a corresponding SENTER function. Only  enabled SENTER leaf functionality can be used when 
executing SENTER. 
•Bits 15 specify global enable of all SENTER functionalities. 
7.2.2 SMX Instruction Summary
System software must first query for available GETSEC leaf functions by executing GETSEC[CAPABILITIES]. The 
CAPABILITIES leaf function returns a bit map of availabl e GETSEC leaves. An attempt to execute an unsupported 
leaf index results in an undef ined opcode (#UD) exception. Table 7-1.  Layout of IA32_FEATURE_CONTROL
0 Lock bit (0 = unlocked, 1 = locked). When set to '1' further writes to this MSR are blocked.
1 Enable VMX in SMX operation.

2 Enable VMX outside SMX operation.
7:3 Reserved14:8 SENTER Local Function Enables: When  set, each bit in the field represents an enable control for a corresponding 
SENTER function.
15 SENTER Global Enable: Must  be set to ‘1’ to enable operation of GETSEC[SENTER].
16 Reserved17 SGX Launch Control Enable: Must be set to ‘1’ to enable runtime re-configuration of SGX Launch Control via the 
IA32_SGXLEPUBKEYHASHn MSR. 
18 SGX Global Enable: Must be set to ‘1 ’ to enable Intel SGX leaf functions. 
19 Reserved
20 LMCE On: When set, system software can program the MSRs associated with LMCE to configure delivery of some 
machine check exceptions to a single logica l processor. 
63:21 ReservedSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-37.2.2.1  GETSEC[CAPABILITIES]
The SMX functionality provides an architectural interface for newer processor generations to extend SMX capabili-
ties. Specifically, the GETSEC instruction provides a capa bility leaf function for system software to discover the 
available GETSEC leaf functions that are supported in a processor. Table 7-2 lists the currently available GETSEC 
leaf functions.
.
7.2.2.2  GETSEC[ENTERACCS]
The GETSEC[ENTERACCS] leaf enables authenticated co de execution mode. The ENTERACCS leaf function 
performs an authenticated code module load using the ch ipset public key as the signature verification. ENTERACCS 
requires the existence of an Intel® Trusted Execution Technology capable chipset since it unlocks the chipset 
private configuration register space after successful auth entication of the loaded module. The physical base 
address and size of the authenticated code module are spec ified as input register valu es in EBX and ECX, respec-
tively. 
While in the authenticated code execution mode, certain processor state properties change. For this reason, the 
time in which the processor operates in authenticated code  execution mode should be limited to minimize impact 
on external system events. 
Upon entry into , the previous paging context is disabled  (since the authenticated code  module image is specified 
with physical addresses and can no longer rely up on external memory-based page-table structures).
Prior to executing the GETSEC[ENTERACCS] leaf, system software must ensure the logical processor issuing 
GETSEC[ENTERACCS] is the boot-strap processor (BSP), as indicated by IA32_APIC_BASE.BSP = 1. System soft-
ware must ensure other logical processors are in a suitable idle state and not marked as BSP.
The GETSEC[ENTERACCS] leaf may be used  by different agents to load diffe rent authenticated code modules to 
perform functions related to different  aspects of a measured environment,  for example system software and 
Intel® TXT enabled BIOS may use more than one authenticated code modules.
7.2.2.3  GETSEC[EXITAC]
GETSEC[EXITAC] takes the processor out of authenticated code execution mode. When this instruction leaf is 
executed, the contents of the authenticated code execut ion area are scrubbed and control is transferred to the 
non-authenticated context defined by a near pointer passed with the GETSEC[EXITAC] instruction. 
The authenticated code execution area is no longer acce ssible after completion of GE TSEC[EXITAC]. RBX (or EBX) 
holds the address of the near absolu te indirect target to be taken. Table 7-2.  GETSEC Leaf Functions 
Index (EAX) Leaf function Description
0 CAPABILITIES Returns the av ailable leaf functions of the GETSEC instruction.
1 Undefined Reserved
2 ENTERACCS Enter 
3E X I T A C E x i t  4 SENTER Launch an MLE.5 SEXIT Exit the MLE.
6 PARAMETERS Return SMX related parameter information.
7S M C T R L S M X  m o d e  c o n t r o l .8 WAKEUP Wake up sleeping pr ocessors in safer mode.
9 - (4G-1) Undefined ReservedSAFER MODE EXTENSIONS REFERENCE
7-4 Vol. 2D7.2.2.4  GETSEC[SENTER]
The GETSEC[SENTER] leaf function is  used by the initiating logical pr ocessor (ILP) to launch an MLE. 
GETSEC[SENTER] can be considered a superset of the ENTE RACCS leaf, because it enters as part of the measured 
environment launch. 
Measured environment startup consists of the following steps:
•the ILP rendezvous the responding logical processors (RLPs) in the platform into a controlled state (At the 
completion of this handshake, all the RLPs except fo r the ILP initiating the measured environment launch are 
placed in a newly defined SENTER sleep state).
•Load and authenticate the authenticated code module  required by the measured environment, and enter 
authenticated code execution mode.
•Verify and lock certain system configuration parameters.
•Measure the dynamic root of trust and store into the PCRs in TPM. 
•Transfer control to the MLE with interrupts disabled.
Prior to executing the GETSEC[SENTER] leaf, system softwa re must ensure the platform’s TPM is ready for access 
and the ILP is the boot-strap processor (BSP), as indica ted by IA32_APIC_BASE.BSP. System software must ensure 
other logical processors (RLPs) are in a su itable idle state and not marked as BSP.
System software launching a measurement environment is responsible for providing a proper authenticate code 
module address when execut ing GETSEC[SENTER]. The AC module responsible for the launch of a measured envi-
ronment and loaded by GETSEC[SENTE R] is referred to as SINIT. See Intel® Trusted Execution Technology 
Measured Launched Environment Programming Guide for additional information on system software requirements 
prior to executing GETSEC[SENTER].
7.2.2.5  GETSEC[SEXIT]
System software exits the measured environment by exec uting the instruction GETSEC[SEXIT] on the ILP. This 
instruction rendezvous the responding logical processors in the platform for exiting from the measured environ-
ment. External events (if left masked) are unmasked and Intel® TXT-capable chipset’s private configuration space 
is re-locked. 
7.2.2.6  GETSEC[PARAMETERS]
The GETSEC[PARAMETERS] leaf function is used to report attributes, option s, and limitations of SMX operation. 
Software uses this leaf to identify operating limits or additional options. 
The information reported by GETSEC[PAR AMETERS] may require executing the le af multiple times using EBX as an 
index. If the GETSEC[PARAMETERS] instruction leaf or if a specific parameter field is no t available, then SMX oper-
ation should be interpreted to use the default limits of resp ective GETSEC leaves or parameter fields defined in the 
GETSEC[PARAMETERS] leaf.
7.2.2.7  GETSEC[SMCTRL]
The GETSEC[SMCTRL] leaf function is used for providing addi tional control over specific conditions associated with 
the SMX architecture. An input register is supported for selecting the control operation to be performed. See the 
specific leaf description for details on the type of control provided.
7.2.2.8  GETSEC[WAKEUP]
Responding logical processors (RLPs) are placed in the SENTER sleep state after the initiating logical processor 
executes GETSEC[SENTER]. The ILP can wake up RL Ps to join the measured environment by using 
GETSEC[WAKEUP]. When the RLPs in SENTER sleep state wa ke up, these logical processors begin execution at the 
entry point defined in a data structure held in system memo ry (pointed to by an chipset register LT.MLE.JOIN) in 
TXT configuration space.SAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-57.2.3 Measured Environment and SMX
This section gives a simplified view of a representative li fe cycle of a measured environment that is launched by a 
system executive using SMX leaf functions. The Intel® Trusted Execution Techno logy Measured Launched Environ-
ment Programming Guide provides more detailed examples of using SMX and chipset resources (including chipset 
registers, Trusted Platform Module) to launch an MVMM.
The life cycle starts with the system executive (an OS, an  OS loader, and so forth) loading the MLE and SINIT AC 
module into available system memory. The system exec utive must validate and prepare the platform for the 
measured launch. When the platform is properly config ured, the system executive executes GETSEC[SENTER] on 
the initiating logical processor (ILP) to rendezvous the re sponding logical processors in to an SENTER sleep state, 
the ILP then enters into using the SINIT AC module. In a multi-threaded or multi-processing environment, the 
system executive must ensure that other logical processors  are already in an idle loop, or asleep (such as after 
executing HLT) before executing GETSEC[SENTER].
After the GETSEC[SENTER] rendezvous handshake is perfor med between all logical proce ssors in the platform, the 
ILP loads the chipset authenticated code module (SINIT) and performs an authentication check. If the check 
passes, the processor hashes the SINIT AC module and stor es the result into TPM PCR 17. It then switches execu-
tion context to the SINIT AC module. The SINIT AC mo dule will perform a number of platform operations, 
including: verifying the system configuration, protecting  the system memory used by the MLE from I/O devices

including: verifying the system configuration, protecting  the system memory used by the MLE from I/O devices 
capable of DMA, producing a hash of the MLE, storing th e hash value in TPM PCR 18, and various other operations. 
When SINIT completes execution, it executes the GETSEC[E XITAC] instruction and transfers control the MLE at the 
designated entry point. 
Upon receiving control from the SINIT AC module, the ML E must establish its protection and isolation controls 
before enabling DMA and interrupts and transferring control to other software modules. It must also wake up the 
RLPs from their SENTER sleep state using the GETSEC[WAKEU P] instruction and bring them  into its protection and 
isolation environment.
While executing in a measured environment, the MVMM can a ccess the Trusted Platform Module (TPM) in locality 2. 
The MVMM has complete access to all TPM commands and may use the TPM to report current measurement values or use the measurement values to protect information such  that only when the platform configuration registers 
(PCRs) contain the same value is the information released  from the TPM. This protection mechanism is known as 
sealing. 
A measured environment shutdown is ultimately completed by executing GETSEC[SEXIT]. Prior to this step system 
software is responsible for scrubbing sensitive information left in the processor caches, system memory.
7.3 GETSEC LEAF FUNCTIONS
This section provides detailed descriptions of each leaf func tion of the GETSEC instruction. GETSEC is available only 
if CPUID.01H:ECX[Bit 6] = 1. This indicates the availabili ty of SMX and the GETSEC instruction. Before GETSEC can 
be executed, SMX must be enabled by setting CR4.SMXE[Bit 14] = 1.
A GETSEC leaf can only be used if it is shown to be av ailable as reported by the GE TSEC[CAPABILITIES] function. 
Attempts to access a GETSEC leaf index not supported by the processor, or if CR 4.SMXE is 0, results in the signaling 
of an undefined opcode exception.
All GETSEC leaf functions are available in protected mode , including the compatibility sub-mode of IA-32e mode 
and the 64-bit sub-mode of IA-32e mode. Unless otherwise no ted, the behavior of all GETSEC functions and inter-
actions related to the measured environment are independen t of IA-32e mode. This also applies to the interpreta-
tion of register widths1 passed as input parameters to GETSEC functions and to register results returned as output 
parameters.
1.  This chapter uses the 64-bit  notation RAX, RIP, RSP, RFLAGS, etc. for proce ssor registers beca use processors that support SM X also 
support Intel 64 Architecture. The MV MM can be launched in IA-32e mode or outside IA-32e mode. The 64-bit notation of processor  
registers also refer to its 32-bit forms if SMX is used in 32-bit environment. In some  places, notation such  as EAX is used to refer 
specifically to lower 32 bits of the indicated register.SAFER MODE EXTENSIONS REFERENCE
7-6 Vol. 2DThe GETSEC functions ENTERACCS, SENTER , SEXIT, and WAKEUP require a Intel® TXT capable-chipset to be 
present in the platform. The GETSEC[CAPABILITIES] retu rned bit vector in position 0 indicates an Intel® TXT-
capable chipset has been sampled present1 by the processor.
The processor's operating mode also affects the execution of the following GETSEC leaf  functions: SMCTRL, ENTER-
ACCS, EXITAC, SENTER, SEXIT, and WAKEUP. These functions are only allowed in protected mode at CPL = 0. They 
are not allowed while in SMM in order to prevent potentia l intra-mode conflicts. Further execution qualifications 
exist to prevent potential architectural conflicts (for example: nesting of the measured environment or authenti-cated code execution mode). See the definitions of th e GETSEC leaf functions for specific requirements.
For the purpose of performance monitor counting, the execution of GETSEC functions is counted as a single instruc-
tion with respect to retired instructions. The response by  a responding logical processor (RLP) to messages associ-
ated with GETSEC[SENTER] or GTSEC[SEXIT] is tran sparent to the retired instruction count on the ILP.
1. Sampled present means that  the processor sent a message to the chipset and the chipset respon ded that it (a) knows about the 
message and (b) is capable of executing SENTER. This means that the chipset CAN support Intel® TXT, and is configured and WILLI NG 
to support it.GETSEC[CAPABILITIES]—Report the SMX CapabilitiesSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-7GETSEC[CAPABILITIES]—Repo rt the SMX Capabilities
The GETSEC[CAPABILITIES] function returns a bit vector of supported GETSEC leaf functions. The CAPABILITIES 
leaf of GETSEC is selected with EAX set to 0 at entry. EBX is used as the selector for returning the bit vector field in 
EAX. GETSEC[CAPABILITIES] may be executed at all privile ge levels, but the CR4.SMXE bit must be set or an unde-
fined opcode exception (#UD) is returned.
With EBX = 0 upon execution of GETSEC[CAPABILITIES], EA X returns the a bit vector representing status on the 
presence of a Intel® TXT-capable chipset and the first 30 available GETSEC leaf functions. The format of the 
returned bit vector is provided in Table 7-3. 
If bit 0 is set to 1, then an Intel® TXT-capable chipset has been sampled presen t by the processor. If bits in the range 
of 1-30 are set, then the corresponding GETSEC leaf function  is available. If the bit value at a given bit index is 0, 
then the GETSEC leaf function corresponding to that in dex is unsupported and attempted execution results in a 
#UD. 
Bit 31 of EAX indicates if further leaf indexes are supported.  If the Extended Leafs bit 31 is set, then additional leaf 
functions are accessed by repeating GETSEC[CAPABILITIES]  with EBX incremented by one. When the most signifi-
cant bit of EAX is not set, then additi onal GETSEC leaf functions are not supported; indexing EBX to a higher value 
results in EAX returning zero.Opcode Instruction Description
NP 0F 37 
(EAX = 0)GETSEC[CAPABILITIES] Report the SMX capabilities. 
The capabilities index is input in EBX with the result returned in EAX.
Table 7-3.  GETSEC Capability  Result Encoding (EBX = 0) 
Field Bit position Description
Chipset Present 0 Intel® TXT-capable chipset is present.
Undefined 1 ReservedENTERACCS 2 GETSEC[ENTERACCS] is available.
EXITAC 3 GETSEC[EXITAC] is available.
SENTER 4 GETSEC[SENTER] is available.SEXIT 5 GETSEC[SEXIT ] is available.
PARAMETERS 6 GETSEC[PARA METERS] is available.
SMCTRL 7 GETSEC[SMCTRL] is available.WAKEUP 8 GETSEC[WAKEUP] is available.
Undefined 30:9 Reserved
Extended Leafs 31 Reserved for extended info rmation reporting of GETSEC capabilities.GETSEC[CAPABILITIES]—Report the SMX CapabilitiesSAFER MODE EXTENSIONS REFERENCE
7-8 Vol. 2DOperation
IF (CR4.SMXE=0)
THEN #UD;
ELSIF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
IF (EBX=0) THEN
BitVector := 0;IF (TXT chipset present)
BitVector[Chipset present] := 1;
IF (ENTERACCS Available)
THEN BitVector[ENTERACCS] := 1;
IF (EXITAC Available)
THEN BitVector[EXITAC] := 1;
IF (SENTER Available)
THEN BitVector[SENTER] := 1;
IF (SEXIT Available)
THEN BitVector[SEXIT] := 1;
IF (PARAMETERS Available)
THEN BitVector[PARAMETERS] := 1;
IF (SMCTRL Available)
THEN BitVector[SMCTRL] := 1;
IF (WAKEUP Available)
THEN BitVector[WAKEUP] := 1;
EAX := BitVector;
ELSE
EAX := 0;
END;;
None.
Use of Prefixes
LOCK Causes #UD.
REP* Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).Operand size Causes #UD.
NP 66/F2/F3 prefixes are not allowed.
Segment overrides Ignored.Address size Ignored.
REX Ignored.
#UD If CR4.SMXE = 0.
#UD If CR4.SMXE = 0.GETSEC[CAPABILITIES]—Report the SMX CapabilitiesSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-964-Bit Mode Exceptions
VM-exit Condition
Reason (GETSEC) If in VMX non-root operation.GETSEC[ENTERACCS]—Execute Authenticated Chipset CodeSAFER MODE EXTENSIONS REFERENCE
7-10 Vol. 2DGETSEC[ENTERACCS]—Execute Authenticated Chipset Code
The GETSEC[ENTERACCS] function loads,  authenticates, and executes an au thenticated code module using an 
Intel® TXT platform chipset's public key. The ENTERACCS leaf of GETSEC is se lected with EAX set to 2 at entry.
There are certain restrictions enforced by the processor for the execution of the GETSEC[ENTERACCS] instruction: 
•Execution is not allowed unless the processor is in protected mode or IA-32e mode with CPL = 0 and 
EFLAGS.VM = 0. 
•Processor cache must be available and not disabled , that is, CR0.CD and CR0.NW bits must be 0. 
•For processor packages containing more than one logica l processor, CR0.CD is checked to ensure consistency 
between enabled logical processors. 
•For enforcing consistency of operation with numeric ex ception reporting using Interrupt 16, CR0.NE must be 
set. 
•An Intel TXT-capable chipset must be present as communi cated to the processor by sampling of the power-on 
configuration capability field after reset.

set. 
configuration capability field after reset. 
•The processor can not already be in authenticated code execution mode as launched by a previous 
GETSEC[ENTERACCS] or GETS EC[SENTER] instruction without a subsequent exiting using GETSEC[EXITAC]). 
•To avoid potential operability conflicts between modes, th e processor is not allowed to execute this instruction 
if it currently is in SMM or VMX operation. 
•To ensure consistent handling of SIPI messages, th e processor executing the GETSEC[ENTERACCS] instruction 
must also be designated the BSP (boot-strap proce ssor) as defined by IA32_APIC_BASE.BSP (Bit 8). 
Failure to conform to the above conditions results in the processor signaling a general protection exception.
Prior to execution of the ENTERACCS leaf, other logical processors, i.e., RLPs, in the platform must be:
•Idle in a wait-for-SIPI state (as initiated by an INIT assertion or through reset for non-BSP designated 
processors), or 
•In the SENTER sleep state as initiated by a GETSEC[S ENTER] from the initiating logical processor (ILP). 
If other logical processor(s) in the same package are no t idle in one of these states, execution of ENTERACCS 
signals a general protection exception. The same requiremen t and action applies if the other logical processor(s) of 
the same package do not have CR0.CD = 0. 
A successful execution of ENTERACCS results in the ILP entering an authenticated code execution mode. Prior to 
reaching this point, the processor performs several checks. These include: 
•Establish and check the location and size of the specified authenticated code module to be executed by the processor.
•Inhibit the ILP’s response to the exte rnal events: INIT, A20M, NMI, and SMI.
•Broadcast a message to enable protection of memory and I/O from other processor agents.
•Load the designated code module into an authenticated code execution area.
•Isolate the contents of the authenticated code executio n area from further state modification by external 
agents.
•Authenticate the authenticated code module.
•Initialize the initiating logical processor state based on  information contained in the authenticated code module 
header.
•Unlock the Intel® TXT-capable chipset private configuration space and TPM locality 3 space.Opcode Instruction Description
NP 0F 37 
(EAX = 2)GETSEC[ENTERACCS] Enter authen ticated code execution mode.
EBX holds the authen ticated code module physical base address. ECX holds the authenticated 
code module size (bytes).GETSEC[ENTERACCS]—Execute Authenticated Chipset CodeSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-11•Begin execution in the authenticated code module at the defined entry point.
The GETSEC[ENTERACCS] function requir es two additional input parameters in the general purpose registers EBX 
and ECX. EBX holds the authenticated co de (AC) module physical base addres s (the AC module must reside below 
4 GBytes in physical address space) and ECX holds the AC  module size (in bytes). The physical base address and 
size are used to retrieve the code module from system memory and load it into the internal authenticated code 
execution area. The base physical address is checked to ve rify it is on a modulo-4096 byte boundary. The size is 
verified to be a multiple of 64, that it does not exceed the internal authenticated code execution area capacity (as reported by GETSEC[CAPABILITIES]), and that the top addr ess of the AC module does not exceed 32 bits. An error 
condition results in an abort of the authenticated code execution launch and the signaling of a general protection 
As an integrity check for proper processor hardware oper ation, execution of GETSEC[E NTERACCS] will also check 
the contents of all the machine check status registers (as reported by the MSRs IA32_MCi_STATUS) for any valid 
uncorrectable error condition. In addition, the global machine check status register IA32_MCG_STATUS MCIP bit 
must be cleared and the IERR processor package pin (or its equivalent) must not be asserted, indicating that no 
machine check exception processing is currently in progre ss. These checks are performed prior to initiating the 
load of the authenticated code module. Any outstanding valid uncorrectable machine check error condition present 
in these status registers at this point will result in the processor signaling a general protection violation.
The ILP masks the response to the assertion of the exte rnal signals INIT#, A20M, NMI#, and SMI#. This masking 
remains active until optionally un masked by GETSEC[EXITAC] (this de fined unmasking behavior assumes 
GETSEC[ENTERACCS] was not executed by a prior GETSEC[S ENTER]). The purpose of this masking control is to 
prevent exposure to existing external event handlers that  may not be under the control of the authenticated code 
module. 
The ILP sets an internal flag to indicate it has entere d authenticated code execution mode. The state of the A20M 
pin is likewise masked and forced internally to a de-asserted state so that any external assertion is not recognized during authenticated code execution mode. 
To prevent other (logical) processors from interfering with  the ILP operating in authenticated code execution mode, 
memory (excluding implicit write-back transactions) a ccess and I/O originating from other processor agents are 
blocked. This protection starts when the ILP enters into  authenticated code execution mode. Only memory and I/O 
transactions initiated from the ILP are allowed to proceed. Exiting authenticated code execution mode is done by executing GETSEC[EXITAC]. The protection of memory and I/O activities remains in effect until the ILP executes 
GETSEC[EXITAC].
Prior to launching the authenticated execution modu le using GETSEC[ENTERACCS] or GETSEC[SENTER], the 
processor’s MTRRs (Memory Type Range Registers) must first be initialized to map out the authenticated RAM 
addresses as WB (writeback). Failure to do so may affect  the ability for the processor to maintain isolation of the 
loaded authenticated code module. If the processor detected  this requirement is not met, it will signal an Intel® 
TXT reset condition with an error code during the loading of the authenticated code module.
While physical addresses within the load module must be mapped as WB, the memory type for locations outside of 
the module boundaries must be mapped to one of the supported memory types as returned by GETSEC[PARAME-
TERS] (or UC as default).
To conform to the minimum granularity of MTRR MSRs fo r specifying the memory type, authenticated code RAM 
(ACRAM) is allocated to the processor in 4096 byte granular blocks. If an AC module size as specified in ECX is not 
a multiple of 4096 then the processor will allocate up to  the next 4096 byte boundary for mapping as ACRAM with 
indeterminate data. This pad area will not be visible to th e authenticated code module as external memory nor can 
it depend on the value of the data used to fill the pad area.
At the successful completion of GETSEC[E NTERACCS], the architectural state of the processor is partially initialized 
from contents held in the header of the authenticated code module. The processor GDTR, CS, and DS selectors are 
initialized from fields within the authenticated code modu le. Since the authenticated code module must be relocat-
able, all address references must be relative to the auth enticated code module base address in EBX. The processor 
GDTR base value is initialized to the AC module header field GDTBasePtr + module base address held in EBX and 
the GDTR limit is set to the value in the GDTLimit field. The CS selector is initialize d to the AC module header 
SegSel field, while the DS selector is initialized to CS + 8. The segment descriptor fields are implicitly initialized to 
BASE=0, LIMIT=FFFFFh, G=1, D=1, P=1, S=1, read/write access for DS, and execute/read access for CS. The 
processor begins the authenticated code module execution with the EIP set to the AC module header EntryPoint 
field + module base address (EBX). The AC module based fields used for initializing the processor state are checked 
for consistency and any failure results in a shutdown condition.GETSEC[ENTERACCS]—Execute Authenticated Chipset CodeSAFER MODE EXTENSIONS REFERENCE
7-12 Vol. 2DA summary of the register state initialization after succ essful completion of GETSEC [ENTERACCS] is given for the 
processor in Table 7-4. The paging is disabled upon entr y into authenticated code execution mode. The authenti-
cated code module is loaded and initially executed using ph ysical addresses. It is up to the system software after 
execution of GETSEC[ENTERACCS] to establish a new (or restore its previous) paging environment with an appro-
priate mapping to meet new protection requirements. EBP is initialized to the authenticated code module base physical address for initial execution in the authenticate d environment. As a result, the authenticated code can

priate mapping to meet new protection requirements. EBP is initialized to the authenticated code module base physical address for initial execution in the authenticate d environment. As a result, the authenticated code can 
reference EBP for relative address base d references, given that the authenticated code module must be position 
independent.
The segmentation related processor state that has not been initialized by GETSEC [ENTERACCS] requires appro-
priate initialization before use. Since a new GDT context has been established, the previous state of the segment 
selector values held in ES, SS, FS, GS, TR, and LDTR might not be valid. Table 7-4.  Register State Initialization After GETSEC[ENTERACCS] 
Register State Initialization Status Comment
CR0 PG ←0, AM←0, WP←0: Others unchanged Paging, Alignment Check, Write-protection are 
disabled.
CR4 MCE ←0, CET ←0, PCIDE ←0: Others unchanged Machine Check Exceptions, Control-flow 
Enforcement Technology, and Process-context 
Identifiers disabled.
EFLAGS 00000002HIA32_EFER 0H IA-32e mode disabled.
EIP AC.base + EntryPoint AC.base is in EBX as input to GETSEC[ENTERACCS].
[E|R]BX Pre-ENTERACCS state:  Next [E|R]IP prior to 
GETSEC[ENTERACCS]Carry forward 64-bit processor state across 
GETSEC[ENTERACCS].
ECX Pre-ENTERACCS state: [31:16]=GDTR.limit; 
[15:0]=CS.selCarry forward processor state across 
[E|R]DX Pre-ENTERACCS state: 
GDTR baseCarry forward 64-bit processor state across 
EBP AC.base
CS Sel=[SegSel], base=0, limit=FFFFFh, G=1, D=1, 
AR=9BH
DS Sel=[SegSel] +8, base=0, limit=FFFFFh, G=1, D=1, 
AR=93H
GDTR Base= AC.base (EBX) + [GDTBasePtr], 
Limit=[GDTLimit]
DR7 00000400H
IA32_DEBUGCTL 0H
IA32_MISC_ENABLE See Table 7-5 for example. The number of initialized fields may change due to 
processor implementation.
Performance 
counters and 
counter control 
registers0HGETSEC[ENTERACCS]—Execute Authenticated Chipset CodeSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-13The MSR IA32_EFER is also unconditionally cleared as part  of the processor state init ialized by ENTERACCS. Since 
paging is disabled upon entering authenticated code ex ecution mode, a new paging environment will have to be 
reestablished in order to establish IA-32e mode while operating in authenticated code execution mode.
Debug exception and trap related signaling is also disabled  as part of GETSEC[ENTERACCS]. This is achieved by 
resetting DR7, TF in EFLAGs, and the MSR IA32_DEBUGCTL. These debug functions are free to be re-enabled once 
supporting exception handler(s), descriptor tables, and debu g registers have been properly initialized following 
entry into authenticated code execution mode. Also, any pe nding single-step trap condition will have been cleared 
upon entry into this mode.
Performance related counters and counter control registers are cleared as part of execution of ENTERACCS. This 
implies any active performance counters at any time of  ENTERACCS execution will be disabled. To reactive the 
processor performance counters, this state must be re-initialized and re-enabled.
The IA32_MISC_ENABLE MSR is initialize d upon entry into authenticated execut ion mode. Certain bits of this MSR 
are preserved because preserving these bits may be import ant to maintain previously established platform settings 
(See the footnote for Table 7-5.). The remaining bits are cl eared for the purpose of establishing a more consistent 
environment for the execution of authenticated code module s. One of the impacts of in itializing this MSR is any 
previous condition established by the MONITOR instruction will be cleared. 
To support the possible return to the processor architec tural state prior to execution of GETSEC[ENTERACCS], 
certain critical processor state is captured and stored in the general- purpose registers at instruction completion. [E|R]BX holds effective address ([E|R]IP) of the instruct ion that would execute next after GETSEC[ENTERACCS], 
ECX[15:0] holds the CS selector value, ECX[31:16] holds the GDTR limit field, and [E|R]DX holds the GDTR base 
field. The subsequent authenticated code can preserve the contents of these registers so that this state can be manually restored if needed, prior to exiting authenti cated code execution mode with GETSEC[EXITAC]. For the 
processor state after exiting authenticated code ex ecution mode, see the description of GETSEC[SEXIT].
The IDTR will also require reloading with a new IDT co ntext after entering authenti cated code execution mode, 
before any exceptions or the external interrupts INTR an d NMI can be handled. Since external interrupts are re-
enabled at the completion of authenticated code executio n mode (as terminated with EXITAC), it is recommended Table 7-5.  IA32_MISC_E NABLE MSR Initialization1 by ENTERACCS and SENTER
NOTES:
1. The number of IA32_MISC_ENABLE fields that are initialized may vary due to processor implementations.Field Bit position Description
Fast strings enable 0 Clear to 0.FOPCODE compatibility mode 
enable2C l e a r  t o  0 .
Thermal monitor enable 3 Set to 1 if other thermal monitor capability is not enabled.
2
2. ENTERACCS (and SENTER) initialize the state of processor ther mal throttling such that at leas t a minimum level is enabled. I f thermal 
throttling is already enabled when executing one of these GETSEC leaves, then no change in th e thermal throttling control setti ngs 
will occur. If thermal thro ttling is disabled, then it will be enabled via setting of the thermal throttle control bit 3 as a r esult of execut-
ing these GETSEC leaves.Split-lock disable 4 Clear to 0.
Bus lock on cach e line splits 
disable8C l e a r  t o  0 .
Hardware prefetch disable 9 Clear to 0.
GV1/2 legacy enable 15 Clear to 0.
MONITOR/MWAIT s/m enable 18 Clear to 0.
Adjacent sector prefetch  disable 19 Clear to 0.GETSEC[ENTERACCS]—Execute Authenticated Chipset CodeSAFER MODE EXTENSIONS REFERENCE
7-14 Vol. 2Dthat a new IDT context be established before this poin t. Until such a new IDT context is established, the 
programmer must take care in not executing an INT n instruction or any other operation that would result in an exception or trap signaling.
Prior to completion of the GETSEC[ENTERACCS] instructio n and after successful authentication of the AC module, 
the private configuration space of the Intel TXT chipset is  unlocked. The authenticated code module alone can gain 
access to this normally restricted chipset state for the purpose of securing the platform. 
Once the authenticated code module is launched at the co mpletion of GETSEC[ENTERACCS], it is free to enable 
interrupts by setting EFLAGS.IF and enable NMI by execut ion of IRET. This presumes that it has re-established 
interrupt handling support through init ialization of the IDT, GDT, and corresponding interrupt handling code.
Operation in a Uni- Processor Platform
(* The state of the internal flag ACMODEFL AG persists across instruction boundary *)
THEN #UD;
ELSIF (GETSEC leaf unsupported)
THEN #UD;
ELSIF ((in VMX operation) or
(CR0.PE=0) or (CR0.CD=1) or (CR0.NW=1) or (CR0.NE=0) or
(CPL>0) or (EFLAGS.VM=1) or(IA32_APIC_BASE.BSP=0) or(TXT chipset not present) or(ACMODEFLAG=1) or (IN_SMM=1))
IF (GETSEC[PARAMETERS].Parameter_Typ e = 5, MCA_Handling (bit 6) = 0)
FOR I = 0 to IA32_MCG_CAP.COUNT-1 DO
IF (IA32_MC[I]_STATUS  = uncorrectable error)
OD;
FI;IF (IA32_MCG_STATUS.MCIP=1) or (IERR pin is asserted)
ACBASE := EBX;ACSIZE := ECX;IF (((ACBASE MOD 4096) ≠ 0) or ((ACSIZE MOD 64 ) ≠ 0 ) or (ACSIZE < minimum module si ze) OR (ACSIZE > authenticated RAM 
capacity)) or ((ACBASE+A CSIZE) > (2^32 -1)))
IF (secondary thread(s) CR0.CD = 1) or ((s econdary thread(s) NOT(wait-for-SIPI)) and
(secondary thread(s) not in SENTER sleep state)THEN #GP(0);
Mask SMI, INIT, A20M, and NMI external pin events;
IA32_MISC_ENABLE := (IA32_ MISC_ENABLE & MASK_CONST*)
(* The hexadecimal value of MASK_CONST may vary due to processor implementations *)A20M := 0;IA32_DEBUGCTL := 0;Invalidate processor TLB(s);Drain Outgoing Transactions;ACMODEFLAG := 1;SignalTXTMessage(ProcessorHold);Load the internal ACRAM based on the AC module size;
(* Ensure that all ACRAM loads hit Write Back memory space *)
IF (ACRAM memory type ≠ WB)GETSEC[ENTERACCS]—Execute Authenticated Chipset CodeSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-15THEN TXT-SHUTDOWN(#BadACMMType);
IF (AC module header version isnot supported) OR (ACRAM[ModuleType] ≠ 2)
THEN TXT-SHUTDOWN (#UnsupportedACM);
 (* Authenticate the AC Module and shutdown with an error if it fails *)
KEY := GETKEY(ACRAM, ACBASE);KEYHASH := HASH(KEY);CSKEYHASH := READ(TXT.PUBLIC.KEY);IF (KEYHASH ≠ CSKEYHASH)
THEN TXT-SHUTDOWN(#AuthenticateFail);
SIGNATURE := DECRYPT(ACRAM, ACBASE, KEY);(* The value of SIGNATURE_LEN_CO NST is implementa tion-specific*)
FOR I=0 to SIGNATURE_LEN_CONST - 1 DO
ACRAM[SCRATCH.I] := SIGNATURE[I];
COMPUTEDSIGNATURE := HASH(ACRAM, ACBASE, ACSIZE);FOR I=0 to SIGNATURE_LEN_CONST - 1 DO
ACRAM[SCRATCH.SIGNATURE_LEN_CONST+I] := COMPUTEDSIGNATURE[I];
IF (SIGNATURE ≠ COMPUTEDSIGNATURE)

ACMCONTROL := ACRAM[CodeControl];IF ((ACMCONTROL.0 = 0) and (ACMCONTROL.1 = 1) and (s noop hit to modified line  detected on ACRAM load))
THEN TXT-SHUTDOWN(#UnexpectedHITM);
IF (ACMCONTROL reserved bits are set)
THEN TXT-SHUTDOWN(#BadACMFormat);
IF ((ACRAM[GDTBasePtr] < (ACRAM[HeaderLen] * 4 + Scratch_size)) OR
((ACRAM[GDTBasePtr] + ACRA M[GDTLimit]) >= ACSIZE))
IF ((ACMCONTROL.0 = 1) and (ACMCONTROL.1 = 1) and (s noop hit to modified line  detected on ACRAM load))
THEN ACEntryPoint := ACBASE+ACRAM[ErrorEntryPoint];
ELSE
ACEntryPoint := ACBASE+ACRAM[EntryPoint];
IF ((ACEntryPoint >= ACSIZE) OR (ACEntryPoint < (ACRAM[HeaderLen] * 4 + Scratch_size)))THEN TXT-SHUTDOWN(#BadACMFormat);
IF (ACRAM[GDTLimit] & FFFF0000h)
IF ((ACRAM[SegSel] > (ACRAM[GDTLimi t] - 15)) OR (ACRAM[SegSel] < 8))
IF ((ACRAM[SegSel].TI=1) OR (ACRAM[SegSel].RPL ≠0))
CR0.[PG.AM.WP] := 0;CR4.MCE := 0;EFLAGS := 00000002h;IA32_EFER := 0h;[E|R]BX := [E|R]IP of the inst ruction after GETSEC[ENTERACCS];
ECX := Pre-GETSEC[ENTERACCS] GDT.limit:CS.sel;[E|R]DX := Pre-GETSEC [ENTERACCS] GDT.base;
EBP := ACBASE;GDTR.BASE := ACBASE+ACRAM[GDTBasePtr];GDTR.LIMIT := ACRAM[GDTLimit];
CS.SEL := ACRAM[SegSel];CS.BASE := 0;CS.LIMIT := FFFFFh;CS.G := 1;CS.D := 1;CS.AR := 9Bh;DS.SEL := ACRAM[SegSel]+8;GETSEC[ENTERACCS]—Execute Authenticated Chipset CodeSAFER MODE EXTENSIONS REFERENCE
7-16 Vol. 2DDS.BASE := 0;
DS.LIMIT := FFFFFh;DS.G := 1;DS.D := 1;DS.AR := 93h;DR7 := 00000400h;IA32_DEBUGCTL := 0;SignalTXTMsg(OpenPrivate);SignalTXTMsg(OpenLocality3);EIP := ACEntryPoint;END;
All flags are cleared.
REP* Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).
Operand size Causes #UD.NP 66/F2/F3 prefixes are not allowed.
Segment overrides Ignored.
Address size Ignored.REX Ignored.
If GETSEC[ENTERACCS] is not reported as supported by GETSEC[CAPABILITIES].
#GP(0) If CR0.CD = 1 or CR0.NW = 1 or CR0.NE = 0 or CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.
If a Intel® TXT-capable chipset is not present.If in VMX root operation.
If the initiating processor is not designated as the bootstrap processor via the MSR bit 
IA32_APIC_BASE.BSP.
If the processor is already in au thenticated code execution mode.
If the processor is in SMM.
If a valid uncorrectable machine check error is logged in IA32_MC[I]_STATUS.
If the authenticated code base is not on a 4096 byte boundary.
If the authenticated code size > processor internal authenticated code area capacity.
If the authenticated code size is not modulo 64.If other enabled logical processor(s) of the same package CR0.CD = 1.
If other enabled logical processor(s) of the same package are not in the wait-for-SIPI or 
SENTER sleep state.
#GP(0) GETSEC[ENTERACCS] is not re cognized in real-address mode.GETSEC[ENTERACCS]—Execute Authenticated Chipset CodeSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-17Virtual-8086 Mode Exceptions
#GP(0) GETSEC[ENTERACCS] is not re cognized in virtual-8086 mode.
All protected mode exceptions apply.
#GP  If AC code module does not resi de in physical address below 2^32 -1.
Reason (GETSEC) If in VMX non-root operation.GETSEC[EXITAC]—Exit Authenticated Code Execution ModeSAFER MODE EXTENSIONS REFERENCE
7-18 Vol. 2DGETSEC[EXITAC]—Exit Authenticated Code Execution Mode
The GETSEC[EXITAC] leaf function exits the ILP out of  authenticated code execution mode established by 
GETSEC[ENTERACCS] or GETSEC[SENTER]. The EXITAC leaf of GETSEC is selected with EA X set to 3 at entry. EBX 
(or RBX, if in 64-bit mode) holds the near jump target  offset for where the processor execution resumes upon 
exiting authenticated code execution mode. EDX contains a dditional parameter control information. Currently only 
an input value of 0 in EDX is supported. All other EDX se ttings are considered reserved and result in a general 
protection violation.
GETSEC[EXITAC] can only be executed if the processor is  in protected mode with CPL = 0 and EFLAGS.VM = 0. The 
processor must also be in authenticated code executio n mode. To avoid potential operability conflicts between 
modes, the processor is not allowed to execute this instruct ion if it is in SMM or in VMX operation. A violation of 
these conditions results in a general protection violation.
Upon completion of the GETSEC[EXITAC] operation, the processor unmasks responses to external event signals 
INIT#, NMI#, and SMI#. This unmasking is performed co nditionally, based on whether the authenticated code 
execution mode was entered via execution of GETSEC[SEN TER] or GETSEC[ENTERACCS]. If the processor is in 
authenticated code execution mode due to the execution of GETSEC[SENTER], then these external event signals 
will remain masked. In this case, A20M  is kept disabled in the measured environment until the measured environ-
ment executes GETSEC[SEXIT]. INIT# is unconditionally unmasked by EXITAC. Note that any events that are 
pending, but have been blocked while in  authenticated code execution mode, will be recognized at the completion 
of the GETSEC[EXITAC] instruction if the pin event is unmasked.
The intent of providing the ability to optionally leave the pin events SMI#, and NMI# masked is to support the 
completion of a measured environment bring-up that makes use of VMX. In this envisioned security usage 
scenario, these events will remain masked until an appr opriate virtual machine has been established in order to 
field servicing of these events in a safer manner. Detail s on when and how events are masked and unmasked in 
VMX operation are described in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C. It 
should be cautioned that if no VMX environment is to be activated following GETSEC[EXITAC], that these events 
will remain masked until the measured environment is exited  with GETSEC[SEXIT]. If this is not desired then the 
GETSEC function SMCTRL(0) can be used for unmasking SMI# in this context. NMI# can be correspondingly 
unmasked by execution of IRET.
A successful exit of the authenticated code execution mode requires the ILP to perform additional steps as outlined 
below:
•Invalidate the contents of the internal authenticated code execution area. 
•Invalidate processor TLBs. 
•Clear the internal processor AC Mode indicator flag. 
•Re-lock the TPM locality 3 space. 
•Unlock the Intel® TXT-capable chipset memory and I/O protection s to allow memory and I/O activity by other 
processor agents. 
•Perform a near absolute indirect jump to the designated instruction location.
The content of the authenticated code execution area is inva lidated by hardware in order to protect it from further 
use or visibility. This internal processor storage area ca n no longer be used or relied upon after GETSEC[EXITAC]. 
Data structures need to be re-established outside of the authenticated code execution area if they are to be refer-
enced after EXITAC. Since addressed memory content form erly mapped to the authenticated code execution area 
may no longer be coherent with external system memory af ter EXITAC, processor TLBs in support of linear to phys-
ical address translation are also invalidated.Opcode Instruction Description
NP 0F 37
(EAX=3)GETSEC[EXITAC] Exit authenti cated code execution mode.
RBX holds the Near Absolute In direct jump target and EDX hold the exit parameter flags.GETSEC[EXITAC]—Exit Authenticated Code Execution ModeSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-19Upon completion of GETSEC[EXITAC] a near absolute indi rect transfer is performed with EIP loaded with the 
contents of EBX (based on the current operating mode size).  In 64-bit mode, all 64 bits of RBX are loaded into RIP 
if REX.W precedes GETSEC[EXITAC]. Otherwise RBX is treated as 32 bits even while in 64-bit mode. Conventional 
CS limit checking is performed as part of this control tr ansfer. Any exception conditions generated as part of this 
control transfer will be directed to the existing IDT; thus it is recommended that an IDTR should also be established 
prior to execution of the EXITAC function if there is a n eed for fault handling. In addition, any segmentation related 
(and paging) data structures to be used after EXITAC sh ould be re-established or validated by the authenticated 
code prior to EXITAC. 
In addition, any segmentation related (and paging) data st ructures to be used after EXITAC need to be re-estab-

lished and mapped outside of the authenticated RAM design ated area by the authenticated code prior to EXITAC. 
Any data structure held within the authenticated RAM alloca ted area will no longer be accessible after completion 
by EXITAC.
Operation
(* The state of the internal flag ACMODEFLAG and SENTERFLAG persist across instruction boundary *)
THEN #UD;
ELSIF ( in VMX non-root operation)
THEN #UD;
ELSIF ((in VMX operation) or ( (in 64-bit mode) and ( RBX is non-canonical) )
(CR0.PE=0) or (CPL>0) or (EFLAGS.VM=1) or(ACMODEFLAG=0) or (IN_SMM=1)) or (EDX ≠ 0))
THEN tempEIP := EBX;
ELSIF (OperandSize = 64)
THEN tempEIP := RBX;
ELSE
tempEIP := EBX AND 0000FFFFH;
IF (tempEIP > code segment limit)
Invalidate ACRAM contents;Invalidate processor TLB(s);Drain outgoing messages;SignalTXTMsg(CloseLocality3);SignalTXTMsg (LockSMRAM);
SignalTXTMsg(ProcessorRelease);Unmask INIT;IF (SENTERFLAG=0)
THEN Unmask SMI,  INIT, NMI, and A20M pin event;
ELSEIF (IA32_SMM_MONITOR_CTL[0] = 0)
THEN Unmask SMI pin event;
ACMODEFLAG := 0;IF IA32_EFER.LMA == 1
THEN CR3 := R8;
EIP := tempEIP;END;
None.GETSEC[EXITAC]—Exit Authenticated Code Execution ModeSAFER MODE EXTENSIONS REFERENCE
7-20 Vol. 2DUse of Prefixes
REX.W Sets 64-bit mode Operand size attribute.
If GETSEC[EXITAC] is not reported as  supported by GETSEC[CAPABILITIES].
#GP(0) If CR0.PE = 0 or CPL>0 or EFLAGS.VM =1.
If in VMX root operation.
If the processor is not currently in authenticated code execution mode.
If any reserved bit position is set in the EDX parameter register.
#GP(0) GETSEC[EXITAC] is not recognized in real-address mode.
#GP(0) GETSEC[EXITAC] is not recognized in virtual-8086 mode.
All protected mode exceptions apply.#GP(0) If the target address in RBX is not in a canonical form.
VM-Exit Condition
Reason (GETSEC) If in VMX non-root operation.GETSEC[SENTER]—Enter a Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-21GETSEC[SENTER]—Enter a Measured Environment
The GETSEC[SENTER] instruction initiate s the launch of a measured environment and places the initiating logical 
processor (ILP) into the authenticated code execution mode . The SENTER leaf of GETSEC is selected with EAX set 
to 4 at execution. The physical base address of the AC mo dule to be loaded and authen ticated is specified in EBX. 
The size of the module in bytes is specified in ECX. EDX controls the le vel of functionality supported by the 
measured environment launch. To enable the full function ality of the protected environment launch, EDX must be 
initialized to zero.
The authenticated code base address and size parameters  (in bytes) are passed to the GETSEC[SENTER] instruc-
tion using EBX and ECX respectively. The ILP evaluates the contents of these registers according to the rules for the 
AC module address in GETSEC[ENTER ACCS]. AC module execution follows the same rules, as set by 
The launching software must ensure that the TPM.ACCE SS_0.activeLocality bit is clear before executing the 
GETSEC[SENTER] instruction.
There are restrictions enforced by the processor for execution of the GETSEC[SENTER] instruction: 
•Processor cache must be available and not disabled using the CR0.CD and NW bits. 
set. 
•An Intel TXT-capable chipset must be present as commu nicated to the processor by sampling of the power-on 
•The processor can not be in authenticated code execut ion mode or already in a measured environment (as 
launched by a previous GETSEC[ENTERACCS] or GETSEC[SENTER] instruction). 
•To ensure consistent handling of SIPI messages, th e processor executing the GETSEC[SENTER] instruction 
•EDX must be initialized to a setting supportable by th e processor. Unless enumeration by the GETSEC[PARAM-
ETERS] leaf reports otherwise, on ly a value of zero is supported.
Failure to abide by the above conditions results in the processor signaling a general protection violation.This instruction leaf starts the launch of a measured enviro nment by initiating a rendezvous sequence for all logical 
processors in the platform. The rendezvous sequence invo lves the initiating logical processor sending a message 
(by executing GETSEC[SENTER]) and other responding lo gical processors (RLPs) acknowledging the message, 
thus synchronizing the RLP(s) with the ILP.
In response to a message signaling the completion of rendezvous, RLPs clear the bootstrap processor indicator flag 
(IA32_APIC_BASE.BSP) and enter an SENTER sleep state. In this sleep state, RLPs enter an idle processor condi-
tion while waiting to be activated after a measured envi ronment has been established by the system executive. 
RLPs in the SENTER sleep state can only be activated by the GETSEC leaf function WAKEUP in a measured environ-
ment.Opcode Instruction Description
NP 0F 37
(EAX=4)GETSEC[SENTER] Launch a measured environment.
EBX holds the SINIT authenticated code module physical base address.
ECX holds the SINIT authenticate d code module size (bytes).
EDX controls the level of functionality supported by the measured environment launch.GETSEC[SENTER]—Enter a Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
7-22 Vol. 2DA successful launch of the measured environment results in  the initiating logical processor entering the authenti-
cated code execution mode. Prior to reaching this po int, the ILP performs the following steps internally: 
•Inhibit processor response to the extern al events: INIT, A20M, NMI, and SMI. 
•Establish and check the location and size of the authenticated code module to be executed by the ILP. 
•Check for the existence of an Intel® TXT-capable chipset. 
•Verify the current power manageme nt configuration is acceptable. 
•Broadcast a message to enable protection of memory and I/O from activities from other processor agents. 
•Load the designated AC module into authenticated code execution area. 
•Isolate the content of authenticated code execution area  from further state modification by external agents.
•Authenticate the AC module.
•Updated the Trusted Platform Module (TPM) wi th the authenticated code module's hash. 
•Initialize processor state based on the authenticated code module header information. 
•Unlock the Intel® TXT-capable chipset private configuration register space and TPM locality 3 space. 
•Begin execution in the authenticated code module at the defined entry point.
As an integrity check for proper processor hardware oper ation, execution of GETSEC[SENTER] will also check the 
contents of all the machine check status registers (as reported by the MSRs IA32_MCi_STATUS) for any valid 
must be cleared and the IERR processor package pin (or its equivalent) must be not asserted, indicating that no machine check exception processing is currently in-progre ss. These checks are performed twice: once by the ILP 
prior to the broadcast of the rendezvous message to RLPs, and later in response to RL Ps acknowledging the rendez-
vous message. Any outstanding valid uncorrectable machine check error condition present in the machine check status registers at the first check point will result in the ILP signaling a general protection violation. If an 
outstanding valid uncorrectable machine check error condition is present at the second check point, then this will 
result in the corresponding logical processor signaling the more severe TXT-shutdown condition with an error code 
of 12.
Before loading and authentication of the target code mo dule is performed, the processor also checks that the 
current voltage and bus ratio encodings correspond to know n good values supportable by the processor. The MSR

of 12.
current voltage and bus ratio encodings correspond to know n good values supportable by the processor. The MSR 
IA32_PERF_STATUS values are compared against either  the processor supported maximum operating target 
setting, system reset setting, or the thermal monitor operat ing target. If the current settings do not meet any of 
these criteria then the SENTER function will attempt to change the voltage and bus ratio select controls in a 
processor-specific manner. This adjustment may be to the thermal monitor, minimum (if different), or maximum 
operating target depending on the processor.
This implies that some thermal operating target paramete rs configured by BIOS may be overridden by SENTER. 
The measured environment software may need to take resp onsibility for restoring such settings that are deemed 
to be safe, but not necessarily recognized by SENTER. If an  adjustment is not possible when an out of range setting 
is discovered, then the processor will abort the measured  launch. This may be the case for chipset controlled 
settings of these values or if the controllability is not enabled on the processor. In this case it is the responsibility of 
the external software to program the chipset voltage ID and/or bus ratio select settings to known good values 
recognized by the processor, prior to executing SENTER.
NOTE
For a mobile processor, an adjustment can be made according to the thermal monitor operating target. For a quad-core processor the SENTER adjustment mechanism may result in a more conser-
vative but non-uniform voltage setting, depe nding on the pre-SENTER settings per core.
The ILP and RLPs mask the response to the assertion of  the external signals INIT#,  A20M, NMI#, and SMI#. The 
purpose of this masking control is to prevent exposure to existing external event handlers until a protected handler 
has been put in place to directly handle these events. Masked external pin events may be unmasked conditionally or unconditionally via the GETSEC[EXITAC], GETSEC[SEXIT ], GETSEC[SMCTRL] or for specific VMX related opera-
tions such as a VM entry or the VMXOFF instruction (see respective GETSEC leaves and Intel
tectures Software Developer’s Manual, Volume 3C, for more details). The state of the A20M pin is masked and forced internally to a de-asserted state so that extern al assertion is not recognized. A20M masking as set by GETSEC[SENTER]—Enter a Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-23GETSEC[SENTER] is undone only after taking down th e measured environment with the GETSEC[SEXIT] instruc-
tion or processor reset. INTR is masked by simply clearing  the EFLAGS.IF bit. It is the responsibility of system soft-
ware to control the processor response to IN TR through appropriate management of EFLAGS.
memory (excluding implicit write-back transactions) and I/ O activities originating from other processor agents are 
Once the authenticated code module has been loaded into  the authenticated code execution area, it is protected 
against further modification from external bus snoops. Th ere is also a requirement that the memory type for the 
authenticated code module address range be WB (via initialization of the MTRRs prior to execution of this instruc-
tion). If this condition is not satisfied, it is a violatio n of security and the processor will force a TXT system reset 
(after writing an error code to the chipset LT.ERRORCODE regi ster). This action is referred to as a Intel® TXT reset 
condition. It is performed when it is considered unrelia ble to signal an error through the conventional exception 
reporting mechanism. 
Once successful authentication has been completed by the ILP, the computed hash is stored in a trusted storage 
facility in the platform. The following tr usted storage facility are supported: 
•If the platform register FTM_INTERFACE_ID.[bits 3:0] = 0, the computed hash is stored to the platform’s TPM 
at PCR17 after this register is implicitly reset. PCR17 is a dedicated register for holding the computed hash of 
the authenticated code module loaded and subsequently  executed by the GETSEC[SENTER]. As part of this 
process, the dynamic PCRs 18-22 are reset so they can be utilized by subsequently software for registration of 
code and data modules. 
•If the platform register FTM_INTERFACE_ID.[bits 3:0] = 1, the computed hash is stored in a firmware trusted 
module (FTM) using a modified protocol similar to  the protocol used to write to TPM’s PCR17. 
After successful execution of SENTER, either PCR17 (if FTM is not enabled) or the FTM (if enabled) contains the 
measurement of AC code and the SENTER launching parameters. 
After authentication is completed successfully, the private configuration space of the Intel® TXT-capable chipset is 
unlocked so that the authenticated code module and measured environment software can gain access to this 
normally restricted chipset state. The Intel® TXT-capabl e chipset private configuration space can be locked later 
by software writing to the chipset LT.CMD.CLOSE-PRIVATE  register or unconditionally using the GETSEC[SEXIT] 
The SENTER leaf function also initializes some processor architecture state for the ILP from contents held in the 
header of the authenticated code module. Since the authen ticated code module is relocatable, all address refer-
ences are relative to the base address passed in via EB X. The ILP GDTR base value is initialized to EBX + 
[GDTBasePtr] and GDTR limit set to [GDTLimit]. The CS sele ctor is initialized to the value held in the AC module 
header field SegSel, while the DS, SS, and ES selectors ar e initialized to CS+8. The segment descriptor fields are 
initialized implicitly with BASE=0, LIMIT=FFFFFh, G=1, D= 1, P=1, S=1, read/write/accessed for DS, SS, and ES, 
while execute/read/accessed for CS. Execution in the authenti cated code module for the ILP begins with the EIP set 
to EBX + [EntryPoint]. AC module defined fields used fo r initializing processor state are consistency checked with 
a failure resulting in an TXT-shutdown condition.
Table 7-6 provides a summary of processor state initializat ion for the ILP and RLP(s) after successful completion of 
GETSEC[SENTER]. For both ILP and RLP(s), paging is disabled  upon entry to the measured environment. It is up to 
the ILP to establish a trusted paging environment, with appropriate mappings, to meet protection requirements 
established during the launch of the measured environment.  RLP state initialization is not completed until a subse-
quent wake-up has been signaled by execution of the GETSEC[WAKEUP] function by the ILP.GETSEC[SENTER]—Enter a Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
7-24 Vol. 2DSegmentation related processor state that has not been  initialized by GETSEC[SENTER] requires appropriate 
initialization before use. Since a new GDT context has been  established, the previous state of the segment selector 
values held in FS, GS, TR, and LDTR may no longer be valid. The IDTR will also require reloading with a new IDT 
context after launching the measured environment before exceptions or the external interrupts INTR and NMI can 
be handled. In the meantime, the programmer must take ca re in not executing an INT n instruction or any other 
condition that would result in an exception or trap signaling.
Debug exception and trap related signaling is also disabl ed as part of execution of  GETSEC[SENTER]. This is 
achieved by clearing DR7, TF in EFLAGs, and the MSR IA32_DEBUGCTL as defined in Table 7-6. These can be re-
enabled once supporting exception handler(s), descriptor ta bles, and debug registers have been properly re-initial-
ized following SENTER. Also, any pending single-step trap co ndition will be cleared at the completion of SENTER for 
both the ILP and RLP(s).
Performance related counters and counter control registers are cleared as part of execution of SENTER on both the 
ILP and RLP. This implies any active performance counters at the time of SENTER execution will be disabled. To 
reactive the processor performance counters, this state must be re-initialized and re-enabled.
Since MCE along with all other state bits (with the exception of SMXE) are cleared in CR4 upon execution of SENTER

Since MCE along with all other state bits (with the exception of SMXE) are cleared in CR4 upon execution of SENTER 
processing, any enabled machine check error condition that occurs will result in the processor performing the TXT-
shutdown action. This also applies to an RLP while in th e SENTER sleep state. For each logical processor CR4.MCE Table 7-6.  Register State Initialization  After GETSEC[SENTER] and GETSEC[WAKEUP]
Register State ILP after GETSEC [SENTER] RLP after GETSEC[WAKEUP]
CR0 PG ←0, AM←0, WP←0; Others unchanged PG ←0, CD←0, NW ←0, AM←0, WP←0; PE←1, NE←1
CR4 00004000H 00004000H
EFLAGS 00000002H 00000002H
IA32_EFER 0H 0EIP [EntryPoint from MLE header
1] [LT.MLE.JOIN + 12]
EBX Unchanged [SINIT.BASE] Unchanged
EDX SENTER control flags UnchangedEBP SINIT.BASE UnchangedCS Sel=[SINIT SegSel], ba se=0, limit=FFFFFh, G=1, 
D=1, AR=9BHSel = [LT.MLE.JOIN + 8], base  = 0, limit = FFFFFH, G = 
1, D = 1, AR = 9BH
DS, ES, SS Sel=[SINIT SegSel] +8 , base=0, limit=FFFFFh, G=1, 
D=1, AR=93HSel = [LT.MLE.JOIN + 8] +8, base = 0, limit = FFFFFH, 
G = 1, D = 1, AR = 93H
GDTR Base= SINIT.base (EBX) + [SINIT.GDTBasePtr], 
Limit=[SINIT.GDTLimit]Base = [LT.MLE.JOIN + 4], Limit = [LT.MLE.JOIN]
DR7 00000400H 00000400H
IA32_DEBUGCTL 0H 0H
counters and counter 
control registers0H 0H
IA32_MISC_ENABLE See Table 7-5 See Table 7-5
IA32_SMM_MONITOR
_CTLBit 2 ←0 Bit 2 ←0
NOTES:
1. See the Intel® Trusted Execution Technology Measur ed Launched Environment Programming Guide for MLE header format .GETSEC[SENTER]—Enter a Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-25must be reestablished with a valid machine check exception handler to otherwise avoid an TXT-shutdown under 
such conditions.
The MSR IA32_EFER is also unconditionally cleared as part of the processor state initialized by SENTER for both the 
ILP and RLP. Since paging is disabled upon entering authenticated code execution mode, a new paging environ-
ment will have to be re-established if it is desired to enable IA-32e mode while operating in authenticated code 
execution mode. 
The miscellaneous feature control MSR, IA32_MISC_ENABLE, is initialized as part of the measured environment 
launch. Certain bits of this MSR are preserved because preserving these bits may be important to maintain previ-
ously established platform settings. See the footnote for Table 7-5 The remaining bits are cleared for the purpose 
of establishing a more consistent environment for the ex ecution of authenticated code modules. Among the impact 
of initializing this MSR, any prev ious condition established by the MONITOR instruction will be cleared. 
Effect of MSR IA32_FEATURE_CONTROL MSR
Bits 15:8 of the IA32_FEATURE_CONTROL MSR affect the ex ecution of GETSEC[SENTER]. These bits consist of two 
fields: 
•Bit 15: a global enable control for execution of SENTER.
•Bits 14:8: a parameter control field providing the ability to qualify SENTER execution based on the level of functionality specified with corresponding EDX parameter bits 6:0. 
The layout of these fields in the IA32_F EATURE_CONTROL MSR is shown in Table 7-1. 
Prior to the execution of GETSEC[SENTER], the lock bit of IA32_FEATURE_CONTROL MSR mu st be bit set to affirm 
the settings to be used. Once the lock bit is set, only a power-up reset condition will clear this MSR. The IA32_FEA-
TURE_CONTROL MSR must be configured in accordance to th e intended usage at platform initialization. Note that 
this MSR is only available on SMX or VMX enabled proc essors. Otherwise, IA32_FEATURE_CONTROL is treated as 
reserved.
The Intel® Trusted Execution Technology Measured La unched Environment Programming Guide provides addi-
tional details and requirements for programming measured environment software to launch in an Intel TXT plat-
form.
GETSEC[SENTER] (ILP Only):
THEN #UD;
ELSE IF (in VMX non-root operation)
ELSE IF (GETSEC leaf unsupported)
THEN #UD;
ELSE IF ((in VMX root operation) or
(CR0.PE=0) or (CR0.CD=1) or (CR0.NW=1) or (CR0.NE=0) or(CPL>0) or (EFLAGS.VM=1) or(IA32_APIC_BASE.BSP=0) or (TXT chipset not present) or(SENTERFLAG=1) or (ACMODEF LAG=1) or (IN_SMM=1) or
(TPM interface is not present) or(EDX ≠ (SENTER_EDX_support_mask & EDX)) or
(IA32_FEATURE_CONTROL[0]=0) or (IA32_FEATURE_CONTROL[15]=0) or((IA32_FEATURE_CONTROL[14:8] & EDX[6:0]) ≠ EDX[6:0]))
IF IA32_MC[I]_STATUS = uncorrectable error
FI;
OD;GETSEC[SENTER]—Enter a Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
7-26 Vol. 2DFI;
IF (IA32_MCG_STATUS.MCIP=1) or (IERR pin is asserted)
ACBASE := EBX;ACSIZE := ECX;IF (((ACBASE MOD 4096) ≠ 0) or ((ACSIZE MOD 64) ≠ 0 ) or (ACSIZE < minimum 
module size) or (ACSIZE > AC RAM capacity) or ((ACBASE+ACSIZE) > (2^32 -1)))
SignalTXTMsg(SENTER);DOWHILE (no SignalSENTER message);
TXT_SENTER__MSG_EV ENT (ILP & RLP):
Mask and clear SignalSENTER event;Unmask SignalSEXIT event;IF (in VMX operation)
THEN TXT-SHUTDOWN(#IllegalEvent);
THEN TXT-SHUTDOWN(#UnrecovMCError);
FI;
OD;IF (IA32_MCG_STATUS.MCIP=1) or (IERR pin is asserted)
IF (Voltage or bus ratio status are NOT at a known good state)
THEN IF (Voltage select and bus ratio are interna lly adjustable)
THEN 
Make product-specific adjustment on operating parameters;
ELSE
TXT-SHUTDOWN(#IIlegalVIDBRatio);
FI;
(* The hexadecimal value of MASK_CONST may vary due to processor implementations *)A20M := 0;IA32_DEBUGCTL := 0;Invalidate processor TLB(s);Drain outgoing transactions;Clear performance monitor counters and control;SENTERFLAG := 1;SignalTXTMsg(SENTERAck);IF (logical processor is not ILP)
THEN GOTO RLP_SENTER_ROUTINE;
(* ILP waits for all logi cal processors to ACK *)
DO
DONE := TXT.READ(LT.STS);
WHILE (not DONE);SignalTXTMsg(SENTERContinue);SignalTXTMsg(ProcessorHold);FOR I=ACBASE to ACBASE+ACSIZE-1 DO
ACRAM[I-ACBASE].ADDR := I;ACRAM[I-ACBASE].DATA := LOAD(I);
Vol. 2D 7-27IF (ACRAM memory type ≠ WB)
THEN TXT-SHUTDOWN(#BadACMMType);
IF (AC module header version is not supported) OR (ACRAM[ModuleType] ≠ 2)
KEY := GETKEY(ACRAM, ACBASE);KEYHASH := HASH(KEY);CSKEYHASH := LT.READ(LT.PUBLIC.KEY);IF (KEYHASH ≠ CSKEYHASH)
IF ((ACRAM[GDTBasePtr] < (ACRAM[HeaderLen] * 4 + Scratch_size)) OR 
IF ((ACMCONTROL.0 = 1) and (ACMCONTROL.1 = 1) and (snoop hit to modified 
line detected on ACRAM load)) 
ELSE
IF ((ACEntryPoint >= ACSIZE) or (ACEntryPoi nt < (ACRAM[HeaderLen] * 4 + Scratch_size)))
IF ((ACRAM[SegSel] > (ACRAM[GDTLimi t] - 15)) or (ACRAM[SegSel] < 8))
IF ((ACRAM[SegSel].TI=1) or (ACRAM[SegSel].RPL ≠0))
IF (FTM_INTERFACE_ID.[3:0] = 1 ) (* Alternate FTM Interface has been enabled *)
THEN (* TPM_LOC_CTRL_4 is loca ted at 0FED44008H, TMP_DATA_BUFFER_4 is located at 0FED44080H *)
WRITE(TPM_LOC_CTRL_4) := 01H; (* Modified HASH.START protocol *)
(* Write to firmware storage *)WRITE(TPM_DATA_BUFFER_4) := SIGNATURE_LEN_CONST + 4;FOR I=0 to SIGNATURE_LEN_CONST - 1 DO
WRITE(TPM_DATA_BUFFER_4 + 2 + I ) := ACRAM[SCRATCH.I];
WRITE(TPM_DATA_BUFFER_4 + 2 + SIGNATURE_LEN_CONST) := EDX;
WRITE(FTM.LOC_CTRL) := 06H; (* Modified pr otocol combining HASH.DATA and HASH.END *)
ELSE IF (FTM_INTERFACE_ID.[3:0] = 0 ) (* Use standard TPM Interface *)
ACRAM[SCRATCH.SIGNATURE_LEN_CONST] := EDX;WRITE(TPM.HASH.START) := 0;FOR I=0 to SIGNATURE_LEN_CONST + 3 DO
WRITE(TPM.HASH.DATA) := ACRAM[SCRATCH.I];
WRITE(TPM.HASH.END) := 0;
FI;GETSEC[SENTER]—Enter a Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
7-28 Vol. 2DACMODEFLAG := 1;

CR0.[PG.AM.WP] := 0;CR4 := 00004000h;EFLAGS := 00000002h;IA32_EFER := 0;EBP := ACBASE;GDTR.BASE := ACBASE+ACRAM[GDTBasePtr];GDTR.LIMIT := ACRAM[GDTLimit];CS.SEL := ACRAM[SegSel];CS.BASE := 0;CS.LIMIT := FFFFFh;CS.G := 1;CS.D := 1;CS.AR := 9Bh;DS.SEL := ACRAM[SegSel]+8;DS.BASE := 0;DS.LIMIT := FFFFFh;DS.G := 1;DS.D := 1;DS.AR := 93h;SS := DS;ES := DS;DR7 := 00000400h;IA32_DEBUGCTL := 0;SignalTXTMsg(UnlockSMRAM);SignalTXTMsg(OpenPrivate);SignalTXTMsg(OpenLocality3);EIP := ACEntryPoint;END;
RLP_SENTER_ROUTINE: (RLP Only)
Mask SMI, INIT, A20M, an d NMI external pin events
Unmask SignalWAKEUP event;Wait for SignalSENTERContinue message;IA32_APIC_BASE.BSP := 0;GOTO SENTER sleep state;END;
REX Ignored.GETSEC[SENTER]—Enter a Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-29Protected Mode Exceptions
If GETSEC[SENTER] is not reported as  supported by GETSEC[CAPABILITIES].
If the initiating processor is not designated  as the bootstrap processor via the MSR bit 
If an Intel® TXT-capable chipset is not present.
If an Intel® TXT-capable chipset interface to TPM is not detected as present.
If a protected partition is already active or the processor is already in authenticated code 
mode.
If the processor is in SMM.If a valid uncorrectable machine check error is logged in IA32_MC[I]_STATUS.
If the authenticated code size > processor's authenticated code execution area storage 
capacity.
If the authenticated code size is not modulo 64.
#GP(0) GETSEC[SENTER] is not recognized in real-address mode.
#GP(0) GETSEC[SENTER] is not recognized in virtual-8086 mode.
All protected mode exceptions apply.#GP  If AC code module does not resi de in physical address below 2^32 -1.
Reason (GETSEC) If in VMX non-root operation.GETSEC[SEXIT]—Exit Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
7-30 Vol. 2DGETSEC[SEXIT]—Exit Measured Environment
The GETSEC[SEXIT] instruction initiates an exit of a me asured environment establis hed by GETSEC[SENTER]. The 
SEXIT leaf of GETSEC is selected with EAX set to 5 at exec ution. This instruction leaf sends a message to all logical 
processors in the platform to signal the measured environment exit. 
There are restrictions enforced by the processor fo r the execution of the GETSEC[SEXIT] instruction: 
•Execution is not allowed unless the processor is in pr otected mode (CR0.PE = 1) with CPL = 0 and EFLAGS.VM 
= 0. 
•The processor must be in a measured environment as launched by a previous GETS EC[SENTER] instruction, 
but not still in authenticated code execution mode. 
•To avoid potential interoperability conflicts between modes, the processor is not allowed to execute this 
instruction if it currently is in SMM or in VMX operation. 
•To ensure consistent handling of SIPI messages, the processor executing the GETSEC[SEXIT] instruction must 
also be designated the BSP (bootstrap processor) as de fined by the register bit IA32_APIC_BASE.BSP (bit 8). 
Failure to abide by the above conditions results in the processor signaling a general protection violation.
This instruction initiates a sequence to rendezvous the RLPs with the ILP. It then clears the internal processor flag 
indicating the processor is operating in a measured environment.
In response to a message signaling the completion of re ndezvous, all RLPs restart execution with the instruction 
that was to be executed at the time GETSEC[SEXIT] was re cognized. This applies to all processor conditions, with 
the following exceptions: 
•If an RLP executed HLT and was in this halt state at th e time of the message initia ted by GETSEC[SEXIT], then 
execution resumes in the halt state. 
•If an RLP was executing MWAIT, then a message initiated by GETSEC[SEXIT] causes an exit of the MWAIT state, 
falling through to the next instruction. 
•If an RLP was executing an intermediate iteration of a string instruction, then the processor resumes execution 
of the string instruction at the point which the message initiated by GETSEC[SEXIT] was recognized. 
•If an RLP is still in the SENTER sleep state (never awaken ed with GETSEC[WAKEUP]), it will be sent to the wait-
for-SIPI state after first clearing the bootstrap processor indicator flag (IA32_APIC_BASE.BSP) and any 
pending SIPI state. In this case, such RLPs are initialized to an architectural state consistent with having taken 
a soft reset using the INIT# pin. 
Prior to completion of the GETSEC[SEXIT] operation, both the ILP and any active RLPs unmask the response of the 
external event signals INIT#, A20M, NMI#, and SMI#. This unmasking is performed unconditionally to recognize 
pin events which are masked after a GETSEC[SENTER]. The state of A20M is unmasked, as the A20M pin is not 
recognized while the measured environment is active.
On a successful exit of the measured environment, the IL P re-locks the Intel® TXT-capable chipset private config-
uration space. GETSEC[SEXIT] does not affect the content of any PCR.
At completion of GETSEC[SEXIT] by the ILP, execution pr oceeds to the next instruction. Since EFLAGS and the 
debug register state are not modified by this instruction, a pending trap condition is free to  be signaled if previously 
enabled.Opcode Instruction Description
NP 0F 37
(EAX=5)GETSEC[SEXIT] Exit me asured environment.GETSEC[SEXIT]—Exit Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-31Operation in a Uni- Processor Platform
GETSEC[SEXIT] (ILP Only):
THEN #UD;
THEN #UD;
(CR0.PE=0) or (CPL>0) or (EFLAGS.VM=1) or(IA32_APIC_BASE.BSP=0) or(TXT chipset not present) or(SENTERFLAG=0) or (ACMOD EFLAG=1) or (IN_SMM=1))
SignalTXTMsg(SEXIT);DOWHILE (no SignalSEXIT message);
TXT_SEXIT_MSG_EVENT (ILP & RLP):
Mask and clear SignalSEXIT event;Clear MONITOR FSM;Unmask SignalSENTER event;IF (in VMX operation)
SignalTXTMsg(SEXITAck);IF (logical processor is not ILP)
THEN GOTO RLP_SEXIT_ROUTINE;
DO
DONE := READ(LT.STS);
WHILE (NOT DONE);SignalTXTMsg(SEXITContinue);SignalTXTMsg(ClosePrivate);SENTERFLAG := 0;Unmask SMI, INIT, A20M, an d NMI external pin events;
END;
RLP_SEXIT_ROUTINE (RLPs Only):
Wait for SignalSEXITContinue message;Unmask SMI, INIT, A20M, an d NMI external pin events;
IF (prior execution state = HLT)
THEN reenter HLT state;
IF (prior execution state = SENTER sleep)
THEN
IA32_APIC_BASE.BSP := 0;Clear pending SIPI state;Call INIT_PRO CESSOR_STATE;
Unmask SIPI event;GOTO WAIT-FOR-SIPI;
FI;END;GETSEC[SEXIT]—Exit Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
7-32 Vol. 2DFlags Affected
ILP: None. 
RLPs: All flags are modified for an RLP. return ing to wait-for-SIPI state, none otherwise. 
If GETSEC[SEXIT] is not reported as  supported by GETSEC[CAPABILITIES].
#GP(0) If CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.
If the initiating processor is not design ated via the MSR bit IA32_APIC_BASE.BSP.
If a protected partition is not already active or  the processor is already in authenticated code 
mode.
#GP(0) GETSEC[SEXIT] is not recognized in real-address mode.
#GP(0) GETSEC[SEXIT] is not recognized in virtual-8086 mode.

mode.
Reason (GETSEC) If in VMX non-root operation.GETSEC[PARAMETERS]—Report the SMX ParametersSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-33GETSEC[PARAMETERS]—Report the SMX Parameters
The GETSEC[PARAMETERS] instruction re turns specific parameter information for SMX features supported by the 
processor. Parameter information is returned in EAX, EB X, and ECX, with the input parameter selected using EBX.
Software retrieves parameter information by searching with an input index for EBX starting at 0, and then reading 
the returned results in EAX, EBX, and EC X. EAX[4:0] is designated to return a parameter type field indicating if a 
parameter is available and what type it is. If EAX[4:0] is returned with 0, this designates a null parameter and indi-
cates no more parameters are available. 
Table 7-7 defines the parameter types suppor ted in current and future implementations.Opcode Instruction Description
NP 0F 37
(EAX=6)GETSEC[PARAMETERS] Repor t the SMX parameters.
The parameters index is input in EBX with the result returned in  EAX, EBX, and ECX.
Table 7-7.  SMX Reporting Parameters Format 
Parameter 
Type EAX[4:0] Parameter Description EAX[31:5] EBX[31:0] ECX[31:0]
0 NULL Reserved (0 returned) Reserved (unmodified) Reserved (unmodified)1 Supported AC module 
versionsReserved (0 returned) Version co mparison mask Version numbers 
supported
2 Max size of authenticated 
code execution areaMultiply by 32 for size in 
bytesReserved (unmodified) Reserved (unmodified)
3 External memory types 
supported during AC modeMemory type bit mask Reserved (unmodified) Reserved (unmodified)
4S e l e c t i v e  S E N T E R  
functionality controlEAX[14:8] correspond to 
available SENTER function disable controlsReserved (unmodified) Reserved (unmodified)
5 TXT extensions support TXT Feature Extensions 
Flags (see Table )Reserved Reserved 
6-31 Undefined Reserved (unmodified) Reserved (unmodified) Reserved (unmodified)GETSEC[PARAMETERS]—Report the SMX ParametersSAFER MODE EXTENSIONS REFERENCE
7-34 Vol. 2DSupported AC module versions (as defined by the AC modu le HeaderVersion field) can be determined for a partic-
ular SMX capable processor by the type 1 parameter. Usin g EBX to index through the available parameters reported 
by GETSEC[PARAMETERS] for each unique parameter set retu rned for type 1, software can determine the complete 
list of AC module version(s) supported. 
For each parameter set, EBX returns the comparison ma sk and ECX returns the available HeaderVersion field 
values supported, after AND'ing the target HeaderVersion with the comparison mask. Software can then determine 
if a particular AC module version is supported by following the pseudo-code search routine given below:
parameter_search_index= 0
do {
EBX= parameter_search_index++
EAX= 6GETSEC
if (EAX[4:0] = 1) {
if ((version_query & EBX) = ECX) {
version_is_supported= 1
break
}
}
} while (EAX[4:0] ≠ 0)
If only AC modules with a HeaderVersion of 0 are supporte d by the processor, then only one parameter set of type 
1 will be returned, as follows: EAX = 00000001H, 
EBX = FFFFFFFFH and ECX = 00000000H.The maximum capacity for an authenticated code execution area supported by the processor is reported with the 
parameter type of 2. The maximum supported size in byte s is determined by multiplying the returned size in 
EAX[31:5] by 32. Thus, for a maximum supported auth enticated RAM size of 32KBytes, EAX returns with 
00008002H. 
Supportable memory types for memory mapped outside of  the authenticated code execution area are reported 
with the parameter type of 3. While is active, as init iated by the GETSEC function s SENTER and ENTERACCS and 
terminated by EXITAC, there are restrictions on what memo ry types are allowed for the rest of system memory. It 
is the responsibility of the system software to initialize  the memory type range register (MTRR) MSRs and/or the 
page attribute table (PAT) to only map memory types consistent with the reporting of this parameter. The reporting 
of supportable memory types of external memory is in dicated using a bit map returned in EAX[31:8]. These bit 
positions correspond to the memory type encoding s defined for the MTRR MSR and PAT programming. See 
Table 7-9.Table 7-8.  TXT Feature Extensions Flags 
Bit Definition Description
5 Processor based S-CRTM 
supportReturns 1 if this processor implements a processor-rooted S-CRTM capability and 0 
if not (S-CRTM is rooted in BIOS).
This flag cannot be used to infer whethe r the chipset supports  TXT or whether the 
processor support SMX.
6 Machine Check Handling Returns 1 if it machine check status registers can be preserved through ENTERACCS 
and SENTER. If this bit is 1,  the caller of ENTERACCS and SENTER is not required to 
clear machine check error status bits before invoking these GETSEC leaves.
If this bit returns 0, the caller of ENTERACCS and SENTER must clear all machine 
check error status bits before invoking these GETSEC leaves.
31:7 Reserved Reserved for future use. Will return 0.GETSEC[PARAMETERS]—Report the SMX ParametersSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-35The parameter type of 4 is used for enumerating the av ailability of selective GETSEC[SENTER] function disable 
controls. If a 1 is reported in bits 14:8 of the returned  parameter EAX, then this indicates a disable control capa-
bility exists with SENTER for a partic ular function. The enumerated field in bits 14:8 corresponds to use of the EDX 
input parameter bits 6:0 for SENTER. If an enumerated fi eld bit is set to 1, then the corresponding EDX input 
parameter bit of EDX may be set to 1 to disable that design ated function. If the enumerated field bit is 0 or this 
parameter is not reported, then no disable capability exists with the corresponding EDX input parameter for 
SENTER, and EDX bit(s) must be cleared to 0 to enable ex ecution of SENTER. If no selective disable capability for 
SENTER exists as enumerated, then the corresponding bits in the IA32_FEATURE_CONTROL MSR bits 14:8 must 
also be programmed to 1 if the SENTER global enable bit 15 of the MSR is set. This is required to enable future 
extensibility of SENTER selective disable capability with resp ect to potentially separate software initialization of the 
MSR.
If the GETSEC[PARAMETERS] leaf or specific parameter is not present for a given SMX capable processor, then 
default parameter values should be assumed. These are defined in Table 7-10.
Operation
(* example of a processor supporting only a 0.0 Head erVersion, 32K ACRAM size, memory types UC and WC *)
THEN #UD;
THEN #UD;(* example of a processor supporting a 0.0 HeaderVersion *)
EAX := 00000001h;EBX := FFFFFFFFh;Table 7-9.  External Memo ry Types Using Parameter 3
EAX Bit Position Parameter Description
8 Uncacheable (UC)
9 Write Combining (WC)11:10 Reserved12 Write-through (WT)
13 Write-protected (WP)
14 Write-back (WB)31:15 Reserved
Table 7-10.  Default Parameter Values
Parameter Type EAX[4:0] Default Setting Parameter Description1 0.0 only Supported AC module versions. 2 32 KBytes Authenticated code execution area size.
3 UC only External memory types supported during AC execution mode.
4N o n e A v a i l a b l e  S E N T E R  s e lective disable controls.GETSEC[PARAMETERS]—Report the SMX ParametersSAFER MODE EXTENSIONS REFERENCE
7-36 Vol. 2DECX := 00000000h;
ELSE IF (EBX=1)
(* example of a processor supporting a 32K ACRAM size *)THEN EAX := 00008002h;
ESE IF (EBX= 2)
(* example of a processor supporting external memory types of UC and WC *)THEN EAX := 00000303h;
ESE IF (EBX= other value(s) less  than unsupported index value)
(* EAX value varies. Consult Table 7-7 and Table *)
ELSE (* unsupported index*)
EAX := 00000000h;
END;
None.
If GETSEC[PARAMETERS] is not reported as supported by GETSEC[CAPABILITIES].
Reason (GETSEC) If in VMX non-root operation.GETSEC[SMCTRL]—SMX Mode ControlSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-37GETSEC[SMCTRL]—SMX Mode Control
The GETSEC[SMCTRL] instruction is available for performi ng certain SMX specific mode control operations. The 
operation to be performed is selected through the input register EBX. Currently  only an input value in EBX of 0 is

operation to be performed is selected through the input register EBX. Currently  only an input value in EBX of 0 is 
supported. All other EBX settings will result in th e signaling of a general protection violation. 
If EBX is set to 0, then the SMCTRL leaf is used to re -enable SMI events. SMI is masked by the ILP executing the 
GETSEC[SENTER] instruction (SMI is also masked in the responding logical processors in response to SENTER 
rendezvous messages .). The determination of when this instructio n is allowed and the events that are unmasked 
is dependent on the processor context (See Table 7-11). For brevity, the usage of SMCTRL where EBX=0 will be 
referred to as GETSEC[SMCTRL(0)].
As part of support for launching a measured environmen t, the SMI, NMI, and INIT events are masked after 
GETSEC[SENTER], and remain masked after exiting au thenticated execution mode. Unmasking these events 
should be accompanied by securely enabling these event handlers. These security concerns can be addressed in 
VMX operation by a MVMM. 
The VM monitor can choose two approaches:
•In a dual monitor approach, the executive software will set up an SMM monitor in parallel to the executive VMM 
(i.e., the MVMM), see Chapter 32, “S ystem Management Mode‚” of Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3C. The SMM monitor is dedi cated to handling SMI events without compromising 
the security of the MVMM. This usage model of handling SMI while a measured environment is active does not 
require the use of GETSEC[SMCTRL(0)] as event re-e nabling after the VMX environment launch is handled 
implicitly and through separate VMX based controls. 
•If a dedicated SMM monitor will not be established and SMIs are to be hand led within the measured 
environment, then GETSEC[SMCTRL(0)] can be used by the executive software to re-enable SMI that has been 
masked as a result of SENTER.
Table 7-11 defines the processor context in which GETS EC[SMCTRL(0)] can be used and which events will be 
unmasked. Note that the events that are unmasked are dependent upon the currently operating processor context.Opcode Instruction Description
NP 0F 37 (EAX = 7) GETSEC[SMCTRL] Perform specified SMX mode control as selected with the input EBX.
Table 7-11.  Supported Actions for GETSEC[SMCTRL(0)]
ILP Mode of Operation SMCTRL execution action
In VMX non-root operation VM exit
SENTERFLAG = 0 #GP(0 ), illegal context
In authenticated co de execution mode 
(ACMODEFLAG = 1)#GP(0), illegal context
SENTERFLAG = 1, not in VMX operation, not in 
SMM Unmask SMI 
SENTERFLAG = 1, in VMX root operation, not in 
SMM Unmask SMI if SMM monitor is not configured, otherwise #GP(0)
SENTERFLAG = 1, In VMX root operat ion, in SMM #GP(0), illegal contextGETSEC[SMCTRL]—SMX Mode ControlSAFER MODE EXTENSIONS REFERENCE
7-38 Vol. 2DOperation
(* The state of the internal flag ACMODEFLAG an d SENTERFLAG persist acro ss instruction boundary *)
THEN #UD;
THEN #UD;
ELSE IF ((CR0.PE=0) or (CPL>0) OR (EFLAGS.VM=1))
ELSE IF((EBX=0) and (SENTERFLAG=1) an d (ACMODEFLAG=0) and (IN_SMM=0) and
 (((in VMX root operation) an d (SMM monitor not configured)) or (not in VMX operation)) )
THEN unmask SMI;
ELSE
#GP(0);
END
None.
If GETSEC[SMCTRL] is not reported as  supported by GETSEC[CAPABILITIES].
If a protected partition is not already active or the processor is currently in authenticated code 
mode.
If the SMM monitor is not configured.
#GP(0) GETSEC[SMCTRL] is not re cognized in real-address mode.
#GP(0) GETSEC[SMCTRL] is not re cognized in virtual-8086 mode.GETSEC[SMCTRL]—SMX Mode ControlSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-39Compatibility Mode Exceptions
Reason (GETSEC) If in VMX non-root operation.GETSEC[WAKEUP]—Wake Up Sleeping Proc essors in Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
7-40 Vol. 2DGETSEC[WAKEUP]—Wake Up Sleeping Proc essors in Measured Environment
The GETSEC[WAKEUP] leaf function broadcasts a wake-u p message to all logical processors currently in the 
SENTER sleep state. This GETSEC leaf must be executed on ly by the ILP, in order to wake-up the RLPs. Responding 
logical processors (RLPs) enter the SENTER sleep state after completion of the SENTER rendezvous sequence. 
The GETSEC[WAKEUP] instruction may only be executed: 
•In a measured environment as initia ted by execution of GETSEC[SENTER]. 
•Outside of authenticated code execution mode. 
•Execution is not allowed unless the processor is in protected mode with CPL = 0 and EFLAGS.VM = 0. 
•In addition, the logical processor must be designated as the boot-strap processor as configured by setting 
IA32_APIC_BASE.BSP = 1. 
If these conditions are not met, attempts to execute GE TSEC[WAKEUP] result in a general protection violation.
An RLP exits the SENTER sleep state and start execution in response to a WAKEUP signal initiated by ILP’s execution 
of GETSEC[WAKEUP]. The RLP retrieves a pointer to a data structure that contains information to enable execution 
from a defined entry point. This data structure is located using a physical address held in the Intel® TXT-capable 
chipset configuration register LT.MLE.JOIN. The register is publicly writable in the chipset by all processors and is 
not restricted by the Intel® TXT-capable chipset configuration register lock status. The format of this data structure 
is defined in Table 7-12.
The MLE JOIN data structure contains the information necessary to initialize RLP processor state and permit the 
processor to join the measured environment. The GDTR, LIP,  and CS, DS, SS, and ES selector values are initialized 
using this data structure. The CS selector index is derived directly from the segment selector initializer field; DS, 
SS, and ES selectors are initialized to CS+8. The segment de scriptor fields are initialized implicitly with BASE = 0, 
LIMIT = FFFFFH, G = 1, D = 1, P = 1, S = 1; read/wri te/access for DS, SS, and ES; and execute/read/access for 
CS. It is the responsibility of external software to esta blish a GDT pointed to by the MLE JOIN data structure that 
contains descriptor entries consistent with the implicit se ttings initialized by the processor (see Table 7-6). Certain 
states from the content of Table 7-12 are checked for consis tency by the processor prior to execution. A failure of 
any consistency check results in the RLP aborting entry in to the protected environment and signaling an Intel® TXT 
shutdown condition. The specific checks performed are do cumented later in this section. After successful comple-
tion of processor consistency checks and subsequent initialization, RLP execution in the measured environment 
begins from the entry point at offset 12 (as indicated in Table 7-12).Opcode Instruction Description
NP 0F 37
(EAX=8)GETSEC[WAKEUP] Wake up the responding logical processors from the SENTER sleep state.
Table 7-12.  RLP MVMM JOIN Data Structure
Offset Field
0G D T  l i m i t
4G D T  b a s e  p o i n t e r8 Segment selector initializer
12 EIPGETSEC[WAKEUP]—Wake Up Sleeping Processors in Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
Vol. 2D 7-41Operation
THEN #UD;
THEN #UD;
ELSE IF ((CR0.PE=0) or (CPL>0) or (EFLAGS.VM=1) or (SENTERFLAG= 0) or (ACMODEFLAG=1) or (IN_SM M=0) or (in VMX operation) or 
(IA32_APIC_BASE.BS P=0) or (TXT chipset not present))
ELSE
SignalTXTMsg(WAKEUP);
END;
RLP_SIPI_WAKEUP_FROM_SENTER_ROUTINE: (RLP Only)
WHILE (no SignalWAKEUP event);IF (IA32_SMM_MONITOR_CTL[0] ≠ ILP.IA32_SMM_MONITOR_CTL[0])
THEN TXT-SHUTDOWN(#IllegalEvent)
IF (IA32_SMM_MONITOR_CTL[0] = 0)
ELSE
Mask SMI pin event;
Mask A20M, and NMI external pin events (unmask INIT);Mask SignalWAKEUP event;Invalidate processor TLB(s);Drain outgoing transactions;TempGDTRLIMIT := LOAD(LT.MLE.JOIN);TempGDTRBASE := LOAD(LT.MLE.JOIN+4);TempSegSel := LOAD(LT.MLE.JOIN+8);TempEIP := LOAD(LT.MLE.JOIN+12);IF (TempGDTLimit & FFFF0000h)
THEN TXT-SHUTDOWN(#BadJOINFormat);
IF ((TempSegSel > TempGDTRLIMIT-15) or (TempSegSel < 8))

THEN #UD;
ELSE
END;
ELSE
IF ((TempSegSel.TI=1) or (TempSegSel.RPL ≠0))
CR0.[PG,CD,NW,AM,WP] := 0;CR0.[NE,PE] := 1;CR4 := 00004000h;EFLAGS := 00000002h;IA32_EFER := 0;GDTR.BASE := TempGDTRBASE;GDTR.LIMIT := TempGDTRLIMIT;CS.SEL := TempSegSel;CS.BASE := 0;CS.LIMIT := FFFFFh;CS.G := 1;CS.D := 1;CS.AR := 9Bh;DS.SEL := TempSegSel+8;DS.BASE := 0;DS.LIMIT := FFFFFh;DS.G := 1;GETSEC[WAKEUP]—Wake Up Sleeping Proc essors in Measured EnvironmentSAFER MODE EXTENSIONS REFERENCE
7-42 Vol. 2DDS.D := 1;
DS.AR := 93h;SS := DS;ES := DS;DR7 := 00000400h;IA32_DEBUGCTL := 0;EIP := TempEIP;END;
None.
Operand size Causes #UD.
If GETSEC[WAKEUP] is not reported as supported by GETSEC[CAPABILITIES].
If in VMX operation.
mode.
#GP(0) GETSEC[WAKEUP] is not re cognized in real-address mode.
#GP(0) GETSEC[WAKEUP] is not recognized in virtual-8086 mode.
Reason (GETSEC) If in VMX non-root operation.Vol. 2D 8-1CHAPTER 8
INSTRUCTION SET REFERENCE UN IQUE TO INTEL® XEON PHI™
PROCESSORS
This chapter describes the instruction set that is unique to Intel® Xeon Phi™ Processors based on the Knights 
Landing and Knights Mill microarchitectures. The set is no t supported in any other Intel processors. Included are 
Intel® AVX-512 instructions. For additional instructions supported on these processors, see Chapter 3, “Instruction 
Set Reference, A-L”; Chapter 4, “Instr uction Set Reference, M-U”; Chapter 5,  “Instruction Set Reference, V”; and 
Chapter 6, “Instruction Set Reference, W-Z.”PREFETCHWT1—Prefetch Vector Data Into Ca ches With Intent to Write and T1 HintINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-2 Vol. 2DPREFETCHWT1—Prefetch Vector Data Into Ca ches With Intent to Write and T1 Hint
cache hierarchy specified by an intent to write hint (so that data is brought into ‘Exclusive’ state via a request for 
ownership) and a locality hint:
• T1 (temporal data with respect to first level cache)—prefetch data into the second level cache.The source operand is a byte memory location. (The loca lity hints are encoded into the machine level instruction 
using bits 3 through 5 of the ModR/M byte. Use of any Mo dR/M value other than the specified ones will lead to 
unpredictable behavior.)
The PREFETCHWT1 instruction is merely a hint and does not affect program behavior. If executed, this instruction 
described in Section 9.5, “Memory Opti mization Using Prefetch” of the Intel®  64 and IA-32 Architectures Optimi-
zation Reference Manual.
PREFETCHWT1 instruction is considered a hint to this sp eculative behavior. Because this speculative fetching can 
occur at any time and is not tied to instruction execution, a PREFETCHWT1 instruction is not ordered with respect 
to the fence instructions (MFENCE, SFENCE, and LFENCE ) or locked memory references. A PREFETCHWT1 instruc-
tion is also unordered with respect to CLFLUSH and CLFL USHOPT instructions, other PREFETCHWT1 instructions, or 
any other general instruction. It is ordered with respect to  serializing instructions such as CPUID, WRMSR, OUT, and 
MOV CR.
Operation
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a req uest 
for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore  cache line splits. Th is operation is cons idered a 
hint for the processor and may be skipped depending on implementation.
Prefetch (m8, Level = 1, EXCLUSIVE=1);
All flags are affected.
void _mm_prefetch( char const *, int hint= _MM_HINT_ET1);Opcode/
0F 0D /2
PREFETCHWT1 m8M V/V PREFETCHWT1 Move data from m8 clos er to the processor using T1 hint 
with intent to write.
M ModRM:r/m (r) N/A N/A N/APREFETCHWT1—Prefetch Vector Data Into Ca ches With Intent to Write and T1 HintINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-3Protected Mode Exceptions
#UD If the LOCK prefix is used.V4FMADDPS/V4FNMADDPS—Packed Single Precision Fl oating-Point Fused Multiply-Add (4-Iterations)INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-4 Vol. 2DV4FMADDPS/V4FNMADDPS—Packed Single Precis ion Floating-Point Fused Multiply-Add 
(4-Iterations)
This instruction computes 4 sequential packed fused single-precision floating-point multiply-add instructions with a 
sequentially selected memory operand in each of the four steps.
In the above box, the notation of “+3” is used to denote  that the instruction accesses 4 source registers based on 
that operand; sources are consecutive, start in a multiple  of 4 boundary, and contain the encoded register operand.
This instruction supports memory fault suppression. The enti re memory operand is loaded if any of the 16 lowest 
significant mask bits is set to 1 or if a “no masking” encoding is used.
The tuple type Tuple1_4X implies that four 32-bit elemen ts (16 bytes) are referenced by the memory operation 
portion of this instruction.
Rounding is performed at every FMA (fused multiply and add) boundary. Exceptions are also taken sequentially. 
Pre- and post-computational exceptions of the first FMA ta ke priority over the pre- and post-computational excep-
tions of the second FMA, etc.Opcode/
En64/32 
bit Mode 
EVEX.512.F2.0F38.W0 9A /r
V4FMADDPS zmm1{k 1}{z}, zmm2+3, 
m128A V/V AVX512_4FMAPS Multiply packed single-precision floating-point 
values from source register block indicated by 
zmm2 by values from m128 and accumulate the result in zmm1.
EVEX.512.F2.0F38.W0 AA /r
V4FNMADDPS zmm1{k1}{z}, 
zmm2+3, m128A V/V AVX512_4FMAPS Multiply and negate packed single-precision 
floating-point values from source register block 
indicated by zmm2 by values from m128 and 
accumulate the re sult in zmm1.
A Tuple1_4X ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AV4FMADDPS/V4FNMADDPS—Packed Single Precision Fl oating-Point Fused Multiply-Add (4-Iterations)INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-5Operation
src_reg_id is the 5 bit index of the vector register  specified in the instruction as the src1 register.
define NFMA_PS(kl, vl, dest, k1, msrc, regs_loaded, src_base, posneg):
tmpdest := dest
// reg[] is an array represen ting the SIMD register file.
FOR j := 0 to regs_loaded-1:
IF posneg = 0:
tmpdest.single[i] := RoundFPControl_MXCSR(tmpdest.single[i] - reg[ src_base + j ].single[i] * msrc.single[j])
ELSE:
tmpdest.single[i] := RoundFPControl_MXCSR(tmpdest.single[i] + reg[ src_base + j ].single[i] * msrc.single[j])
tmpdest.single[i] := 0
dest := tmpdst
dest[MAX_VL-1:VL] := 0

ELSE:
V4FMADDPS and V4FN MADDPS dest{k1}, src1, msrc (AVX512)
KL, VL = (16,512)
regs_loaded := 4
src_base := src_reg_id & ~3 // for src1 operand
posneg := 0 if negative form, 1 otherwise
NFMA_PS(kl, vl, dest, k1, msrc, regs_loaded, src_base, posneg)
V4FMADDPS __m512 _mm512_4fmadd_ps( __m512, __m512x4, __m128 *);
V4FMADDPS __m512 _mm512_mask_4fmadd_ps(__m512, __mmask16, __m512x4, __m128 *);V4FMADDPS __m512 _mm512_maskz_4fmadd_ps(__mmask16, __m512, __m512x4, __m128 *);V4FNMADDPS __m512 _mm512_4fnmadd_ps(__m512, __m512x4, __m128 *);V4FNMADDPS __m512 _mm512_mask_4fnmadd_ps(__m512, __mmask16, __m512x4, __m128 *);V4FNMADDPS __m512 _mm512_maskz_4fnmadd_p s(__mmask16, __m512, __m512x4, __m128 *);
See Type E2; additionally:
#UD If the EVEX broadcast bit is set to 1.
#UD If the MODRM.mod = 0b11.V4FMADDSS/V4FNMADDSS—Scalar Single Precision Fl oating-Point Fused Multiply-Add (4-Iterations)INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-6 Vol. 2DV4FMADDSS/V4FNMADDSS—Scalar Single Prec ision Floating-Point Fused Multiply-Add 
(4-Iterations) 
This instruction computes 4 sequential scalar fused single-precision floating-point multiply-add instructions with a 
In the above box, the notation of “+3” is used to denote  that the instruction accesses 4 source registers based that 
operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.
This instruction supports memory fault suppression. The en tire memory operand is loaded if the least significant 
mask bit is set to 1 or if a “no masking” encoding is used.
Rounding is performed at every FMA boundary. Exceptions  are also taken sequentially. Pre- and post-computa-
tional exceptions of the first FMA take priority over the pre- and post-computational exceptions of the second FMA, 
etc.
Operation
src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.
define NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg):
FOR j := 0 to regs_loaded - 1:
tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.si ngle[0] - reg[src_base + j ]. single[0] * msrc.single[j])
ELSE:
tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.si ngle[0] + reg[src_base + j ]. single[0] * msrc.single[j])
tmpdest.single[0] := 0
dest[MAX_VL-1:VL] := 0Opcode/
En64/32 
bit Mode 
EVEX.LLIG.F2.0F38.W0 9B /r
V4FMADDSS xmm1{k1}{z}, 
xmm2+3, m128A V/V AVX512_4FMAPS Multiply scalar single-precision floating-point 
xmm2 by values from m1 28 and accumulate the 
EVEX.LLIG.F2.0F38.W0 AB /r
V4FNMADDSS xmm1{k1}{z}, 
xmm2+3, m128A V/V AVX512_4FMAPS Multiply and ne gate scalar single-precision 
indicated by xmm2 by values from m128 and accumulate the result in xmm1.
AT u p l e 1 _ 4 X M o d R M : r e g  ( r ,  w ) E V EX.vvvv (r) ModRM:r/m (r) N/AV4FMADDSS/V4FNMADDSS—Scalar Single Precision Fl oating-Point Fused Multiply-Add (4-Iterations)INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-7V4FMADDSS and V4FNMADDSS dest{k1}, src1, msrc (AVX512)
VL = 128
NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg)
V4FMADDSS __m128 _mm_4fmadd_ss(__m128, __m128x4, __m128 *);
V4FMADDSS __m128 _mm_mask_4fmadd_ss(__m128, __mmask8, __m128x4, __m128 *);V4FMADDSS __m128 _mm_maskz_4fmadd_ss( __mmask8, __m128, __m128x4, __m128 *);
V4FNMADDSS __m128 _mm_4fnmadd_ss(__m128, __m128x4, __m128 *);V4FNMADDSS __m128 _mm_mask_4fnmadd_ss(__m128, __mmask8, __m128x4, __m128 *);V4FNMADDSS __m128 _mm_maskz_4fnmadd_ss(__mmask8, __m128, __m128x4, __m128 *);
#UD If the EVEX broadcast bit is set to 1.#UD If the MODRM.mod = 0b11.VEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point Values With Less Than 2^-23 RelativeINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-8 Vol. 2DVEXP2PD—Approximation to the Exponential 2^x of Packed Double Prec ision Floating-Point 
Values With Less Than 2^-23 Relative Error
Computes the approximate base-2 exponential evaluation of the double precision floating-point values in the 
source operand (the second operand) and stores the resu lts to the destination operand (the first operand) using 
the writemask k1. The approximate base -2 exponential is evaluated with less than 2^-23 of relative error. 
Denormal input values are treated as zeros and do not si gnal #DE, irrespective of MXCSR.DAZ. Denormal results 
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.
The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit 
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1. 
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-
Operation
VEXP2PD 
THEN DEST[i+63:i] := EXP2_23_DP(SRC[63:0])ELSE DEST[i+63:i] := EXP2_23_DP(SRC[i+63:i])
FI;
ELSE 
FI;
FI;
En64/32 
bit Mode 
Feature 
EVEX.512.66.0F38.W1 C8 /r
VEXP2PD zmm1 {k1}{z}, 
zmm2/m512/m64bcst {sae}A V/V AVX512ER Computes approximations to the exponential 2^x (with less 
than 2^-23 of maximum relative error) of the packed double 
precision floating-point values from zmm2/m512/m64bcst and 
stores the floating-point resu lt in zmm1with writemask k1.
A Full ModRM:reg (r, w) ModRM:r/m (r) N/A N/AVEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point Values With Less Than 2^-23 Relative INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-9Intel C/C++ Compiler Intrinsic Equivalent
VEXP2PD __m512d _mm512_exp2a23_r ound_pd (__m512d a, int sae);
VEXP2PD __m512d _mm512_mask_exp2a23_round_pd (__m512d a, __mmask8 m, __m512d b, int sae);VEXP2PD __m512d _mm512_maskz_exp2a23_rou nd_pd ( __mmask8 m, __m512d b, int sae);
Invalid (if SNaN input), Overflow.
See Table 2-46, “Type E2 Class Exception Conditions.”Table 6-44. Special Values Behavior
Source Input Result Comments
NaN QNaN(src) If (SRC = SNaN) then #I+∞ +∞
+/-0 1.0f Exact result
-∞ +0.0f
Integral value N 2^ (N) Exact resultVEXP2PS—Approximation to the Exponential 2^x of Packed Single Prec ision Floating-Point Values With Less Than 2^-23 Relative Er-INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-10 Vol. 2DVEXP2PS—Approximation to the Exponential 2^ x of Packed Single Precision Floating-Point 
Computes the approximate base-2 exponential evaluation of the single-precision floating-point values in the source 
operand (the second operand) and store the results in the destination operand (the first operand) using the write-mask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error. 
The source operand is a ZMM register, a 512-bit memory lo cation, or a 512-bit vector broadcasted from a 32-bit 

Operation
VEXP2PS 
THEN DEST[i+31:i] := EXP2_23_SP(SRC[31:0])ELSE DEST[i+31:i] := EXP2_23_SP(SRC[i+31:i])
FI;
ELSE 
FI;
FI;
En64/32 
bit Mode 
Feature 
EVEX.512.66.0F38.W0 C8 /r
VEXP2PS zmm1 {k1}{z}, 
zmm2/m512/m32bcst {sae}A V/V AVX512ER Computes approximations to the exponential 2^x (with less 
than 2^-23 of maximum relative error) of the packed single-
precision floating-point values from zmm2/m512/m32bcst and 
A Full ModRM:reg (r, w) ModRM:r/m (r) N/A N/AVEXP2PS—Approximation to the Exponential 2^x of Packed Single Prec ision Floating-Point Values With  Less Than 2^-23 Relative Er-INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-11Intel C/C++ Compiler Intrinsic Equivalent
VEXP2PS __m512 _mm512_exp2a23_round_ps (__m512 a, int sae);
VEXP2PS __m512 _mm512_mask_exp2a23_round_ps (__m512 a, __mmask16 m, __m512 b, int sae);
VEXP2PS __m512 _mm512_maskz_exp2a23_round _ps (__mmask16 m, __m512 b, int sae);
See Table 2-46, “Type E2 Class Exception Conditions.”Table 6-45. Special Values Behavior
-∞ +0.0f
Integral value N 2^ (N) Exact resultVGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sp arse Prefetch Packed SP/DP Data Values With SignedINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-12 Vol. 2DVGATHERPF0DPS/VGATHERPF0QPS/VGATHERP F0DPD/VGATHERPF0QPD—Sparse Prefetch 
Packed SP/DP Data Values With Signed Dw ord, Signed Qword Indices Using T0 Hint
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The 
elements are specified via the VSIB (i.e., the index register  is an zmm, holding packed indices). Elements will only 
be prefetched if their corresponding mask bit is one. 
Lines prefetched are loaded into to a location in th e cache hierarchy specified by a locality hint (T0):
• T0 (temporal data)—prefetch data into the first level cache.[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
tion will prefetch eight values.
[PD data] For dword and qword indices, the instru ction will prefetch eight memory locations. 
Note that:(1) The prefetches may happen in any order (or not at all). The instruction is a hint.(2) The mask is left unchanged.(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.(4) No FP nor memory faults may be produced by this instruction.(5) Prefetches do not handle cache line splits(6) A #UD is signaled if the memory operand is encoded without the SIB byte.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist.
VINDEX stands for the memory operand ve ctor of indices (a  vector register).
SCALE stands for the memory operand scalar (1, 2, 4 or 8).DISP is the optional 1, 2 or 4 byte displacement.PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a req uest 
hint for the processor and may be skipped depending on implementation.Opcode/
En64/32 
bit Mode 
Feature 
EVEX.512.66.0F38.W0 C6 /1 /vsib
VGATHERPF0DPS vm32z {k1}A V/V AVX512PF Using signed dword indices, prefetch sparse byte 
memory locations containing  single-precision data 
using opmask k1 and T0 hint.
EVEX.512.66.0F38.W0 C7 /1 /vsib 
VGATHERPF0QPS vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte 
EVEX.512.66.0F38.W1 C6 /1 /vsib 
VGATHERPF0DPD vm32y {k1}A V/V AVX512PF Using signed dword indices, prefetch sparse byte 
memory locations containing double precision data using opmask k1 and T0 hint.
EVEX.512.66.0F38.W1 C7 /1 /vsib 
VGATHERPF0QPD vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte 
memory locations containing double precision data 
AT u p l e 1  S c a l a r B a s e R e g (R): VSIB:base,
VectorReg(R): VSIB:indexN/A N/A N/AVGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sp arse Prefetch Packed SP/DP Data Values With Signed INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-13VGATHERPF0DPS (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 0)
FI;
ENDFOR
VGATHERPF0DPD (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 0)
FI;
ENDFOR
VGATHERPF0QPS (EVEX Encoded Version)
(KL, VL) = (8, 256)FOR j := 0 TO KL-1
i := j * 64IF k1[j] 
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 0)
FI;
ENDFOR
VGATHERPF0QPD (EVEX Encoded Version)
i := j * 64k := j * 64IF k1[j] 
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 0)
FI;
ENDFOR
VGATHERPF0DPD void _mm5 12_mask_prefetch_i32gather_pd(__m256i vdx, __m mask8 m, void * base, int scale, int hint);
VGATHERPF0DPS void _mm512_mask_prefetch_i32gather_ps(__m512 i vdx, __mmask16 m, void * base, int scale, int hint);
VGATHERPF0QPD void _mm512_mask _prefetch_i64gather_pd(__m512 i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF0QPS void _mm5 12_mask_prefetch_i64gather_ps(__m512i vdx, __m mask8 m, void * base, int scale, int hint);
None.
See Table 2-62, “Type E12NP Class Exception Conditions.”VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sp arse Prefetch Packed SP/DP Data Values With SignedINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-14 Vol. 2DVGATHERPF1DPS/VGATHERPF1QPS/VGATHERP F1DPD/VGATHERPF1QPD—Sparse Prefetch 
Packed SP/DP Data Values With Signed Dw ord, Signed Qword Indices Using T1 Hint
Lines prefetched are loaded into to a location in th e cache hierarchy specified by a locality hint (T1):
• T1 (temporal data)—prefetch data into the second level cache.[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
Operation
En64/32 
bit Mode 
Feature 
EVEX.512.66.0F38.W0 C6 /2 /vsib 
VGATHERPF1DPS vm32z {k1}A V/V AVX512PF Using signed dword indices, prefetch sparse byte 
memory locations containing single-precision data using 
opmask k1 and T1 hint.
EVEX.512.66.0F38.W0 C7 /2 /vsib 
VGATHERPF1QPS vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte

En64/32 
bit Mode 
Feature 
VGATHERPF1QPS vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte 
EVEX.512.66.0F38.W1 C6 /2 /vsib 
VGATHERPF1DPD vm32y {k1}A V/V AVX512PF Using signed dword indices, prefetch sparse byte 
memory locations containing double precision data using opmask k1 and T1 hint.
EVEX.512.66.0F38.W1 C7 /2 /vsib
VGATHERPF1QPD vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte 
memory locations containing double precision data using 
A Tuple1 Scalar BaseReg (R): VSIB:base,
VectorReg(R): VSIB:indexN/A N/A N/AVGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sp arse Prefetch Packed SP/DP Data Values With Signed INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-15VGATHERPF1DPS (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 0)
FI;
ENDFOR
VGATHERPF1DPD (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 0)
FI;
ENDFOR
VGATHERPF1QPS (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 0)
FI;
ENDFOR
VGATHERPF1QPD (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 0)
FI;
ENDFOR
VGATHERPF1DPD void _mm5 12_mask_prefetch_i32gather_pd(__m256i vdx, __m mask8 m, void * base, int scale, int hint);
VGATHERPF1DPS void _mm512_mask_prefetch_i32gather_ps(__m512 i vdx, __mmask16 m, void * base, int scale, int hint);
VGATHERPF1QPD void _mm512_mask _prefetch_i64gather_pd(__m512 i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF1QPS void _mm5 12_mask_prefetch_i64gather_ps(__m512i vdx, __m mask8 m, void * base, int scale, int hint);
None.
See Table 2-62, “Type E12NP Class Exception Conditions.”VP4DPWSSDS—Dot Product of Signed Words With Dw ord Accumulation and Saturation (4-Iterations)INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-16 Vol. 2DVP4DPWSSDS—Dot Product of Signed Words Wi th Dword Accumulati on and Saturation 
This instruction computes 4 sequential register source-b lock dot-products of two si gned word operands with 
doubleword accumulation and signed saturation. The memory operand is sequentially selected in each of the four 
steps.
This instruction supports memory fault suppression. The enti re memory operand is loaded if any bit of the lowest 
16-bits of the mask is set to 1 or if a “no masking” encoding is used.
Operation
VP4DPWSSDS dest, src1, src2
(KL,VL) = (16,512)N 
:= 4
src_base := src_reg_id & ~ (N-1) // for src1 operand
FOR m := 0 to N-1:
t := SRC2.dword[m]
p1dword := reg[src_base+m].word [2*i] * t.word[0]
p2dword := reg[src_base+m].word [2*i+1] * t.word[1]
DEST.dword[i] := SIGNED_DWORD_SATURATE(DEST.dword[i] + p1dword + p2dword)
ELSE
En64/32 
bit Mode 
EVEX.512.F2.0F38.W0 53 /r
VP4DPWSSDS zmm1{k1}{z}, 
zmm2+3, m128AV / V A V X 5 1 2 _ 4 V N N I W M u l t i p l y  s i g n e d  w o rds from source register block 
indicated by zmm2 by signed words from m128 
and accumulate the result ing dword results with 
signed saturation in zmm1.
A Tuple1_4X ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/AVP4DPWSSDS—Dot Product of Signed Words With Dw ord Accumulation and Saturation (4-Iterations)INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-17Intel C/C++ Compiler Intrinsic Equivalent
VP4DPWSSDS __m512i _mm512_4dpwssds_epi32(__m512i, __m512ix4, __m128i *);
VP4DPWSSDS __m512i _mm512_mask_4dpwssds_epi32(__m512i, __mmask16, __m512ix4, __m128i *);VP4DPWSSDS __m512i _mm512_maskz_4dpwssds_epi3 2(__mmask16, __m512i, __m512ix4, __m128i *);
None.
See Type E4; additionally:
#UD If the MODRM.mod = 0b11.VP4DPWSSD—Dot Product of Signed Words With Dword Accumulation (4-Iterations)INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-18 Vol. 2DVP4DPWSSD—Dot Product of Signed Words Wi th Dword Accumulation (4-Iterations) 
doubleword accumulation; see Figure 8-1 below. The memory operand is sequentially selected in each of the four 
steps.
In the above box, the notation of “+3”' is used to denote that the instruction accesses 4 source registers based on 
portion of this instruction.Opcode/
En64/32 
bit Mode 
EVEX.512.F2.0F38.W0 52 /r
VP4DPWSSD zmm1{k1}{z}, zmm2+3, 
m128AV / V A V X 5 1 2 _ 4 V N N I W M u l t i p l y  s i g n e d  w o rds from source register block 
and accumulate resulting signed dwords in zmm1.
A Tuple1_4X ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Figure 8-1.  Register Source-Block Dot Product of Two Signed Word Operands With Doubleword Accumulation1
NOTES:
1. For illustration purposes, one source-block dot product instance is shown out of the four.b1 b0 b1 b0
c1 c0
c1=c1+a2*b0+a3*b1 c0=c0+a0*b0+a1*b1a3 a2 a1 a016b 16b 16b 16b
32b 32b
32b 32bVP4DPWSSD—Dot Product of Signed Words With Dword Accumulation (4-Iterations)INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-19Operation
VP4DPWSSD dest, src1, src2
:= 4
DEST.dword[i] := DEST.dword[i] + p1dword + p2dword
ELSE
VP4DPWSSD __m512i _mm512_4dpwssd_epi32(__m512i, __m512ix4, __m128i *);
VP4DPWSSD __m512i _mm512_mask_4dpwssd_epi32(__m512i, __mmask16, __m512ix4, __m128i *);VP4DPWSSD __m512i _mm512_maskz _4dpwssd_epi32(__mmask16, __m512i, __m512ix4, __m128i *);
None.
#UD If the MODRM.mod = 0b11.VRCP28PD—Approximation to the Reciprocal of Packed Double Precis ion Floating-Point Values With Less Than 2^-28 Relative ErrorINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-20 Vol. 2DVRCP28PD—Approximation to the Reciprocal of Pa cked Double Precision Floating-Point Values 
With Less Than 2^-28 Relative Error
Computes the reciprocal approximation of the float64 values in the source operand (the second operand) and store 
the results to the destination operand (the first operand) . The approximate reciprocal is evaluated with less than 
2^-28 of maximum relative error. 
If any source element is NaN, the quietized NaN source valu e is returned for that element. If any source element is 
±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ± ∞ is returned for that element.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-
Operation
VRCP28PD (EVEX Encoded Versions) 
(KL, VL) = (8, 512)
THEN DEST[i+63:i] := RC P_28_DP(1.0/SRC[63:0]);
ELSE DEST[i+63:i] := RC P_28_DP(1.0/SRC[i+63:i]);
FI;
ELSE 
FI;
FI;
En64/32 
bit Mode 
Feature 
EVEX.512.66.0F38.W1 CA /r
VRCP28PD zmm1 {k1}{z}, 
zmm2/m512/m64bcst {sae}A V/V AVX512ER Computes the approximate reciprocals ( < 2^-28 relative error) 
of the packed double precision floating-point values in 
zmm2/m512/m64bcst and stores the results in  zmm1. Under 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVRCP28PD—Approximation to the Reciprocal of Packed Double Precision Floating-Point Valu es With Less Than 2^-28 Relative ErrorINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-21Intel C/C++ Compiler Intrinsic Equivalent
VRCP28PD __m512d _mm512_rcp28_rou nd_pd ( __m512d a, int sae);
VRCP28PD __m512d _mm512_mask_rcp28_round_pd( __m512d a, __mmask8 m,  __m512d b, int sae);
VRCP28PD __m512d _mm512_maskz_rcp28_round _pd( __mmask8 m, __m512d b, int sae);
Invalid (if SNaN input), Divide-by-zero.
See Table 2-46, “Type E2 Class Exception Conditions.”Table 6-46. VRCP28PD Special Cases
Input Value Result Value Comments
NAN QNAN(input) If (SRC = SNaN) then #I0 ≤ X < 2
-1022INF Positive input denormal or zero; #Z
-2-1022 < X ≤ -0 -INF Negative input denormal or zero; #Z
X > 21022+0.0f
X < -21022-0.0f
X = +∞ +0.0f
X = -∞ -0.0f
X = 2-n2nExact result (unless inpu t/output is a denormal)
X = -2-n-2nExact result (unless inpu t/output is a denormal)VRCP28SD—Approximation to the Reciprocal of Scalar Double Precision Floating-Point Va lue With Less Than 2^-28 Relative ErrorINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-22 Vol. 2DVRCP28SD—Approximation to the Reciprocal of Sc alar Double Precision Floating-Point Value 
Computes the reciprocal approximation of the low float64 value in the second source operand (the third operand) 
and store the result to the destination operand (the firs t operand). The approximate reciprocal is evaluated with 
less than 2^-28 of maximum relative e rror. The result is written into the low float64 element of the destination 
operand according to the writemask k1. Bits 127:64 of the de stination is copied from the corresponding bits of the 
first source operand (the second operand).
A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result 
is flushed to zero and does not sign al #UE, irrespective of MXCSR.FTZ.
The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory 
location. The destination operand is a XMM regi ster, conditionally upda ted using writemask k1. 
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-
Operation
VRCP28SD ((EVEX Encoded Versions) 
IF k1[0] OR *no writemask* THEN
DEST[63: 0] := RCP_28_DP(1.0/SRC2[63: 0]);
ELSE 
THEN *DEST[63: 0] remains unchanged*ELSE ; zeroing-masking
DEST[63: 0] := 0
FI;
FI;ENDFOR;DEST[127:64] := SRC1[127: 64]DEST[MAXVL-1:128] := 0Opcode/
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W1 CB /r
VRCP28SD xmm1 {k1}{z}, xmm2, 
xmm3/m64 {sae}A V/V AVX512ER Computes the approximate reciprocal ( < 2^-28 relative 
error) of the scalar double precision floating-point value in 
xmm3/m64 and stores the results in xmm1. Under 
writemask. Also, upper double precision floating-point value (bits[127:64]) from xmm2 is copied to 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVRCP28SD—Approximation to the Reciprocal of Scalar Double Precis ion Floating-Point Value With Less Than 2^-28 Relative ErrorINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-23Intel C/C++ Compiler Intrinsic Equivalent
VRCP28SD __m128d _mm_rcp28_round_sd ( __m128d a, __m128d b, int sae);
VRCP28SD __m128d _mm_mask_rcp28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b, int sae);
VRCP28SD __m128d _mm_maskz_rcp28_round_sd(__mmask8 m, __m128d a, __m128d b, int sae);
See Table 2-47, “Type E3 Class Exception Conditions.”Table 6-47. VRCP28SD Special Cases
X = +∞ +0.0f
X = -∞ -0.0f
X = -2-n-2nExact result (unless inpu t/output is a denormal)VRCP28PS—Approximation to the Reciprocal of Packed Single Precis ion Floating-Point Values With Less Than 2^-28 Relative ErrorINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-24 Vol. 2DVRCP28PS—Approximation to the Reciprocal of Pa cked Single Precision Floating-Point Values 
Computes the reciprocal approximation of the float32 values in the source operand (the second operand) and store 
the results to the destination operand (the first operand)  using the writemask k1. The approximate reciprocal is 
evaluated with less than 2^-28 of maximum relative error prior to final rounding. The final results are rounded to 
< 2^-23 relative error before  written to the destination.
Operation
VRCP28PS (EVEX Encoded Versions) 
(KL, VL) = (16, 512)
THEN DEST[i+31:i] := RCP_28_SP(1.0/SRC[31:0]);ELSE DEST[i+31:i] := RCP_28_SP(1.0/SRC[i+31:i]);
FI;
ELSE 
FI;
FI;
En64/32 
bit Mode 
Feature 
EVEX.512.66.0F38.W0 CA /r
VRCP28PS zmm1 {k1}{z}, 
zmm2/m512/m32bcst {sae}A V/V AVX512ER Computes the approximate reciprocals ( < 2^-28 relative 
error) of the packed single-preci sion floating-point values in 
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVRCP28PS—Approximation to the Reciprocal of Packed Single Precis ion Floating-Point Values With Less Than 2^-28 Relative ErrorINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-25Intel C/C++ Compiler Intrinsic Equivalent
VRCP28PS _mm512_rcp28_round_ps ( __m512 a, int sae);
VRCP28PS __m512 _mm512_mask_rcp28_round_ps(__m512 s, __mmask16 m, __m512 a, int sae);VRCP28PS __m512 _mm512_maskz_rcp28_round_ps( __mmask16 m, __m512 a, int sae);

En64/32 
bit Mode 
Feature 
See Table 2-46, “Type E2 Class Exception Conditions.”Table 6-48. VRCP28PS Special Cases
-126INF Positive input denormal or zero; #Z
-2-126 < X ≤ -0 -INF Negative input denormal or zero; #Z
X > 2126+0.0f
X < -2126-0.0f
X = +∞ +0.0f
X = -∞ -0.0f
X = -2-n-2nExact result (unless inpu t/output is a denormal)VRCP28SS—Approximation to the Reciprocal of Scalar Single Precis ion Floating-Point Value With Less Than 2^-28 Relative ErrorINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-26 Vol. 2DVRCP28SS—Approximation to the Reciprocal of Sc alar Single Precision Floating-Point Value 
Computes the reciprocal approximation of the low float32 value in the second source operand (the third operand) 
less than 2^-28 of maximum relative error prior to final ro unding. The final result is rounded to < 2^-23 relative 
error before written into the low float32 element of the destination according to writemask k1. Bits 127:32 of the 
destination is copied from the corresponding bits of the first source operand (the second operand).
The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory 
Operation
VRCP28SS ((EVEX Encoded Versions) 
DEST[31: 0] := RCP_28_SP(1.0/SRC2[31: 0]);
ELSE 
THEN *DEST[31: 0] remains unchanged*ELSE ; zeroing-masking
DEST[31: 0] := 0
FI;
FI;ENDFOR;DEST[127:32] := SRC1[127: 32]DEST[MAXVL-1:128] := 0Opcode/
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W0 CB /r
VRCP28SS xmm1 {k1}{z}, 
xmm2, xmm3/m32 {sae}A V/V AVX512ER Computes the approximate reciprocal ( < 2^-28 relative 
error) of the scalar single-precision floating-point value in 
xmm3/m32 and stores the results in xmm1. Under 
writemask. Also, upper 3 sing le-precision floating-point 
values (bits[127:32]) from xmm2 is copied to 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVRCP28SS—Approximation to the Reciprocal of Scalar Single Precision Floating-Point Va lue With Less Than 2^-28 Relative ErrorINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-27Intel C/C++ Compiler Intrinsic Equivalent
VRCP28SS __m128 _mm_rcp28_round_ss ( __m128 a, __m128 b, int sae);
VRCP28SS __m128 _mm_mask_rcp28_round_ss(__m128 s, __mmask8 m, __m128 a, __m128 b, int sae);VRCP28SS __m128 _mm_maskz_rcp28_round_ss(__mmask8 m, __m128 a, __m128 b, int sae);
See Table 2-47, “Type E3 Class Exception Conditions.”Table 6-49. VRCP28SS Special Cases
X = +∞ +0.0f
X = -∞ -0.0f
X = -2-n-2nExact result (unless inpu t/output is a denormal)VRSQRT28PD—Approximation to the Reciprocal Sq uare Root of Packed Double Precision Fl oating-Point Values With Less Than 2^-28INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-28 Vol. 2DVRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double Precision 
Floating-Point Values With Less Than 2^-28 Relative Error
Computes the reciprocal square root of the float64 values in the source operand (the second operand) and store 
If any source element is NaN, the quietized NaN source va lue is returned for that element. Negative (non-zero) 
source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the 
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative 
denormals return -∞ and set the DivByZero flag.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-
Operation
VRSQRT28PD (EVEX Encoded Versions) 
THEN DEST[i+63:i] := (1.0/ SQRT(SRC[63:0]));ELSE DEST[i+63:i] := (1.0/ SQRT(SRC[i+63:i]));
FI;
ELSE 
FI;
FI;
En64/32 
bit Mode 
Feature 
EVEX.512.66.0F38.W1 CC /r
VRSQRT28PD zmm1 {k1}{z}, 
zmm2/m512/m64bcst {sae}A V/V AVX512ER Computes approximations to the Reciprocal square root (<2^-
28 relative error) of the packed double precision floating-point 
values from zmm2/m512/m64bcst and stores result in 
zmm1with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVRSQRT28PD—Approximation to the Reciprocal Square Root of Packed  Double Precision Floating-Point  Values With Less Than 2^-28 INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-29Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT28PD __m512d _mm512_rsqrt28 _round_pd(__m512d a, int sae);
VRSQRT28PD __m512d _mm512_mask_rsqrt28_round_pd(__m512d s, __mmask8 m,__m512d a, int sae);VRSQRT28PD __m512d _mm512_maskz_rsqrt28_ro und_pd(__mmask8 m,__m512d a, int sae);
See Table 2-46, “Type E2 Class Exception Conditions.”Table 6-50. VRSQRT28PD Special Cases
NAN QNAN(input) If (SRC = SNaN) then #IX = 2
-2n2n
X < 0 QNaN_Indefinite Including -INFX = -0 or negative denormal -INF #ZX = +0 or positive denormal +INF #Z
X = +INF +0VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar  Double Precision Floating-Point Value With Less Than 2^-28INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-30 Vol. 2DVRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar  Double Precision 
Floating-Point Value With Less  Than 2^-28 Relative Error
Computes the reciprocal square root of the low float64 va lue in the second source operand (the third operand) and 
store the result to the destination operand (the first oper and). The approximate reciprocal  square root is evaluated 
with less than 2^-28 of maximum relative error. The re sult is written into the low float64 element of xmm1 
according to the writemask k1. Bits 127:64 of the destination is copied from the corr esponding bits of the fi rst source operand (the 
second operand).
location. The destination operand is a XMM register.

location. The destination operand is a XMM register. 
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-
Operation
VRSQRT28SD (EVEX Encoded Versions) 
 DEST[63: 0] := (1.0/ SQRT(SRC[63: 0]));
ELSE 
FI;
FI;
ENDFOR;DEST[127:64] := SRC1[127: 64]DEST[MAXVL-1:128] := 0Opcode/
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W1 CD /r
VRSQRT28SD xmm1 {k1}{z}, 
xmm2, xmm3/m64 {sae}A V/V AVX512ER Computes approximate reciprocal square root (<2^-28 
relative error) of the scalar double precision floating-point 
value from xmm3/m64 and stores result in xmm1with 
writemask k1. Also, upper double precision floating-point value (bits[127:64]) from  xmm2 is copied to 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVRSQRT28SD—Approximation to the Reciprocal Square Root of Scal ar Double Precision Floating-Point Value With Less Than 2^-28 INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-31Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT28SD __m128d _mm_rsqrt28_round_sd(__m128d a, __m128d b, int rounding);
VRSQRT28SD __m128d _mm_mask_rsqrt28_round_sd(__m128d s, __mmask8 m,__m128d a, __m128d b, int rounding);
VRSQRT28SD __m128d _mm_maskz_rsqrt28_round_sd( __mmask8 m,__m128d a, __m128d b, int rounding);
See Table 2-47, “Type E3 Class Exception Conditions.”Table 6-51. VRSQRT28SD Special Cases
-2n2n
X = +INF +0VRSQRT28PS—Approximation to the Reciprocal Sq uare Root of Packed Single  Precision Floating-Point Values With Less Than 2^-28INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-32 Vol. 2DVRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single Precision 
Computes the reciprocal square root of the float32 values in the source operand (the second operand) and store 
2^-28 of maximum relative error prior to final rounding. The final results is rounded to < 2^-23 relative error 
before written to the destination.
Operation
VRSQRT28PS (EVEX Encoded Versions) 
THEN DEST[i+31:i] := (1.0/ SQRT(SRC[31:0]));ELSE DEST[i+31:i] := (1.0/ SQRT(SRC[i+31:i]));
FI;
ELSE 
FI;
FI;
En64/32 
bit Mode 
Feature 
EVEX.512.66.0F38.W0 CC /r
VRSQRT28PS zmm1 {k1}{z}, 
zmm2/m512/m32bcst {sae}A V/V AVX512ER Computes approximations to the Reciprocal square root 
(<2^-28 relative error) of the packed single-precision 
floating-point values from zmm2/m512/m32bcst and stores 
result in zmm1with writemask k1.
A Full ModRM:reg (w) ModRM:r/m (r) N/A N/AVRSQRT28PS—Approximation to the Reciprocal Sq uare Root of Packed Single  Precision Floating-Point Values With Less Than 2^-28 INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-33Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT28PS __m512 _mm512_rsqrt28_round_ps(__m512 a, int sae);
VRSQRT28PS __m512 _mm512_mask_rsqrt28_round_p s(__m512 s, __mmask16 m,__m512 a, int sae);
VRSQRT28PS __m512 _mm512_maskz_rsqrt28_round_ps(__mmask16 m,__m512 a, int sae);
See Table 2-46, “Type E2 Class Exception Conditions.”Table 6-52. VRSQRT28PS Special Cases
-2n2n
X = +INF +0VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-Point Value With Less Than 2^-28 Rel -INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-34 Vol. 2DVRSQRT28SS—Approximation to the Reciprocal Squa re Root of Scalar Single Precision Floating-
Point Value With Less Than 2^-28 Relative Error
Computes the reciprocal square root of the low float32 va lue in the second source operand (the third operand) and 
with less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 rela-tive error before written to the low float32 element of  the destination according to the writemask k1. Bits 127:32 of 
the destination is copied from the corresponding bits of the first source operand (the second operand).
Operation
VRSQRT28SS (EVEX Encoded Versions) 
 DEST[31: 0] := (1.0/ SQRT(SRC[31: 0]));
ELSE 
FI;
FI;
ENDFOR;DEST[127:32] := SRC1[127: 32]DEST[MAXVL-1:128] := 0Opcode/
En64/32 
bit Mode 
Feature 
EVEX.LLIG.66.0F38.W0 CD /r
VRSQRT28SS xmm1 {k1}{z}, 
xmm2, xmm3/m32 {sae}A V/V AVX512ER Computes approximate reciprocal square root (<2^-28 
relative error) of the scalar single-precision floating-point 
value from xmm3/m32 and stores result in xmm1with 
writemask k1. Also, upper 3 single-precision floating-point value (bits[127:32]) from xmm2 is copied to 
A Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/AVRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-Point Value With Less Than 2^-28 Rel -INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-35Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT28SS __m128 _mm_rsqrt28_round_ss(__m128 a, __m128 b, int rounding);
VRSQRT28SS __m128 _mm_mask_rsqrt28_round_ss(__m1 28 s, __mmask8 m,__m128 a,__m128 b, int rounding);
VRSQRT28SS __m128 _mm_maskz_rsqrt28_round_ ss(__mmask8 m,__m128 a,__m 128 b, int rounding);
See Table 2-47, “Type E3 Class Exception Conditions.”Table 6-53. VRSQRT28SS Special Cases
-2n2n

-2n2n
X = +INF +0VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF 0QPD—Sparse Prefetch Packed  SP/DP Data Values withINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-36 Vol. 2DVSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERP F0DPD/VSCATTERPF0Q PD—Sparse Prefetch 
Packed SP/DP Data Values with Signed Dword, Signed Qword Indi ces Using T0 Hint With Intent 
to Write
cache lines will be brought into exclusive state (RFO) specified by a locality hint (T0):• T0 (temporal data)—prefetch data into the first level cache.[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
Operation
En64/32 
bit Mode SupportCPUID 
EVEX.512.66.0F38.W0 C6 /5 /vsib 
VSCATTERPF0DPS vm32z {k1}A V/V AVX512PF Using signed dword indices, prefetch sparse byte 
writemask k1 and T0 hint with intent to write.
EVEX.512.66.0F38.W0 C7 /5 /vsib 
VSCATTERPF0QPS vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte 
memory locations containing single-precision data using writemask k1 and T0 hint with intent to write.
EVEX.512.66.0F38.W1 C6 /5 /vsib 
VSCATTERPF0DPD vm32y {k1}A V/V AVX512PF Using signed dword indices, prefetch sparse byte 
using writemask k1 and T0 hint with intent to write.
EVEX.512.66.0F38.W1 C7 /5 /vsib
VSCATTERPF0QPD vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte 
VectorReg(R): VSIB:indexN/A N/A N/AVSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0Q PD—Sparse Prefetch Packed SP/DP Data Values with INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-37VSCATTERPF0DPS (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 1)
FI;
ENDFOR
VSCATTERPF0DPD (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 1)
FI;
ENDFOR
VSCATTERPF0QPS (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 1)
FI;
ENDFOR
VSCATTERPF0QPD (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 1)
FI;
ENDFOR
VSCATTERPF0DPD void _mm512_prefetc h_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);
VSCATTERPF0DPD void _mm512_mask_prefetch _i32scatter_pd(void *base, __mmask8 m,  __m256i vdx, int scale, int hint);
VSCATTERPF0DPS void _mm512 _prefetch_i32scatter_ps(v oid *base, __m512i vdx, int scale, int hint);
VSCATTERPF0DPS void _mm5 12_mask_prefetch_i32scatter_ps(void *base, __m mask16 m, __m512i vdx, int scale, int hint);
VSCATTERPF0QPD void _mm512 _prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);
VSCATTERPF0QPD void _mm512_m ask_prefetch_i64scatter_pd(voi d * base, __mmask8 m, __m512i vdx, int scale, int hint);
VSCATTERPF0QPS void _mm512_prefetc h_i64scatter_ps(void * base, __m5 12i vdx, int scale, int hint);
VSCATTERPF0QPS void _mm512_mask_prefetch _i64scatter_ps(void * base , __mmask8 m, __m512i vdx, int scale, int hint);
None.
See Table 2-62, “Type E12NP Class Exception Conditions.”VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF 1QPD—Sparse Prefetch Packed SP/DP Data Values WithINSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
8-38 Vol. 2DVSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERP F1DPD/VSCATTERPF1Q PD—Sparse Prefetch 
Packed SP/DP Data Values  With Signed Dword, Signed Qword Indices Using T1 Hint With Intent 
to Write
cache lines will be brought into exclusive state (RFO) specified by a locality hint (T1):• T1 (temporal data)—prefetch data into the second level cache.[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
Operation
En64/32 
EVEX.512.66.0F38.W0 C6 /6 /vsib 
VSCATTERPF1DPS vm32z {k1}A V/V AVX512PF Using signed dword indices, prefetch sparse byte memory 
locations containing single-precision data using writemask 
k1 and T1 hint with intent to write.
EVEX.512.66.0F38.W0 C7 /6 /vsib
VSCATTERPF1QPS vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte memory 
locations containing single-precision data using writemask k1 and T1 hint with intent to write.
EVEX.512.66.0F38.W1 C6 /6 /vsib 
VSCATTERPF1DPD vm32y {k1}A V/V AVX512PF Using signed dword indices, prefetch sparse byte memory 
locations containing double precision data using 
writemask k1 and T1 hint  with intent to write.
EVEX.512.66.0F38.W1 C7 /6 /vsib
VSCATTERPF1QPD vm64z {k1}A V/V AVX512PF Using signed qword indices, prefetch sparse byte memory 
VectorReg(R): VSIB:indexN/A N/A N/AVSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1Q PD—Sparse Prefetch Packed SP/DP Data Values With INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS
Vol. 2D 8-39VSCATTERPF1DPS (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 1)
FI;
ENDFOR
VSCATTERPF1DPD (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 1)
FI;
ENDFOR

FI;
ENDFOR
FI;
ENDFOR
VSCATTERPF1QPS (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 1)
FI;
ENDFOR
VSCATTERPF1QPD (EVEX Encoded Version)
Prefetch( [BASE_ADDR + SignEx tend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 1)
FI;
ENDFOR
VSCATTERPF1DPD void _mm512_prefetc h_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);
VSCATTERPF1DPD void _mm512_mask_prefetch _i32scatter_pd(void *base, __mmask8 m,  __m256i vdx, int scale, int hint);
VSCATTERPF1DPS void _mm512 _prefetch_i32scatter_ps(v oid *base, __m512i vdx, int scale, int hint);
VSCATTERPF1DPS void _mm5 12_mask_prefetch_i32scatter_ps(void *base, __m mask16 m, __m512i vdx, int scale, int hint);
VSCATTERPF1QPD void _mm512 _prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);
VSCATTERPF1QPD void _mm512_m ask_prefetch_i64scatter_pd(voi d * base, __mmask8 m, __m512i vdx, int scale, int hint);
VSCATTERPF1QPS void _mm512_prefetc h_i64scatter_ps(void *base, __m512i vdx, int scale, int hint);
VSCATTERPF1QPS void _mm512_mask_prefetch _i64scatter_ps(void *base, __mmask8 m,  __m512i vdx, int scale, int hint);
None.
8-40 Vol. 2DVol. 2D A-1APPENDIX A
OPCODE MAP
           
Use the opcode tables in this chapter to interpret IA-32 and Intel 64 architecture object code. Instructions are 
divided into encoding groups:
•1-byte, 2-byte and 3-byte opcode encodings are us ed to encode integer, system, MMX technology, 
SSE/SSE2/SSE3/SSSE3/SSE4, and VMX instructions. Maps  for these instructions are given in Table A-2 
through Table A-6. 
•Escape opcodes (in the format: ESC character, opcode, Mo dR/M byte) are used for floating-point instructions. 
The maps for these instructions are provided in Table A-7 through Table A-22.
NOTE
All blanks in opcode maps are reserved and must not be used. Do not depend on the operation of 
undefined or blank opcodes.
A.1 USING OPCODE TABLES
Tables in this appendix list opcodes of instructions (inclu ding required instruction prefixes, opcode extensions in 
associated ModR/M byte). Blank cells in the tables indica te opcodes that are reserved or undefined. Cells marked 
“Reserved-NOP” are also reserved but may behave as NOP on certain processors. Software should not use opcodes 
corresponding blank cells or cells marked “Reserved-NOP”  nor depend on the current behavior of those opcodes.
The opcode map tables are organized by hex values of th e upper and lower 4 bits of an opcode byte. For 1-byte 
encodings (Table A-2), use the four high-order bits of an opcode to index a row of the opcode table; use the four 
low-order bits to index a column of the table. For 2-byte  opcodes beginning with 0FH (Table A-3), skip any instruc-
tion prefixes, the 0FH byte (0FH may be preceded by 66H , F2H, or F3H) and use the upper and lower 4-bit values 
of the next opcode byte to index table rows and columns.  Similarly, for 3-byte opcodes beginning with 0F38H or 
0F3AH (Table A-4), skip any instruction prefixes, 0F38H or  0F3AH and use the upper and lower 4-bit values of the 
third opcode byte to index table rows and columns. See Section A.2.4, “Opcode Look-up Examples for One, Two, 
and Three-Byte Opcodes.”
When a ModR/M byte provides opcode extensions, this information qualifies opcode execution. For information on 
how an opcode extension in the ModR/M byte modifies the opcode map in Table A-2 and Table A-3, see Section A.4. 
The escape (ESC) opcode tables for floating-point instructio ns identify the eight high order bits of opcodes at the 
top of each page. See Section A.5. If the accompanying ModR /M byte is in the range of 00H-BFH, bits 3-5 (the top 
row of the third table on each page) along with the re g bits of ModR/M determine the opcode. ModR/M bytes 
outside the range of 00H-BFH are mapped by the bottom two tables on each page of the section.
A.2 KEY TO ABBREVIATIONS
Operands are identified by a two-character code of the fo rm Zz. The first character, an  uppercase letter, specifies 
the addressing method; the second character, a lowercase letter, specifies the type of operand.
A.2.1  Codes for Addressing Method
The following abbreviations are used  to document addressing methods:
A Direct address: the instruction has no ModR/M byte; the address of the operand is encoded in the instruc-
tion. No base register, index register, or scaling fa ctor can be applied (for example, far JMP (EA)).
B The VEX.vvvv field of the VEX prefix selects a general purpose register.A-2 Vol. 2DOPCODE MAP
C The reg field of the ModR/M byte selects a co ntrol register (for example, MOV (0F20, 0F22)).
D The reg field of the ModR/M byte se lects a debug register (for example, 
MOV (0F21,0F23)).
E A ModR/M byte follows the opcode and specifies th e operand. The operand is either a general-purpose 
register or a memory address. If it is a memory addr ess, the address is computed from a segment register 
and any of the following values: a base register, an index register, a scaling factor, a displacement.
FE F L A G S / R F L A G S  R e g i s t e r .
G The reg field of the ModR/M byte selects a general register (for example, AX (000)).
H The VEX.vvvv field of the VEX prefix selects a 128-bit XMM register or a 256-bit YMM register, determined 
by operand type. For legacy SSE encodings this oper and does not exist, changing the instruction to 
destructive form.
I Immediate data: the operand value is encode d in subsequent bytes of the instruction.
J The instruction contains a relative offset to be adde d to the instruction pointer register (for example, JMP 
(0E9), LOOP).
L The upper 4 bits of the 8-bit immediate selects a 128-bit XMM register or a 256-bit YMM register, deter-
mined by operand type. (the MSB is ignored in 32-bit mode)
M The ModR/M byte may refer only to memory (for example, BOUND, LES, LDS, LSS, LFS, LGS, 
CMPXCHG8B).
N The R/M field of the ModR/M byte selects a packed-quadword, MMX technology register.
O The instruction has no ModR/M byte. The offset of  the operand is coded as a word or double word 
(depending on address size attribute) in the instructio n. No base register, index register, or scaling factor 
can be applied (for example, MOV (A0–A3)).
P The reg field of the ModR/M byte selects a packed quadword MMX technology register.
Q A ModR/M byte follows the opcode and specifies the operand. The operand is either an MMX technology 
and any of the following values: a base register, an index register, a scaling factor, and a displacement.
R The R/M field of the ModR/M byte may refer only to  a general register (for example, MOV (0F20-0F23)).
S The reg field of the ModR/M byte selects a segment register (for example, MOV (8C,8E)).
U The R/M field of the ModR/M byte selects a 128-bit X MM register or a 256-bit YMM register, determined by 
operand type.
V The reg field of the ModR/M byte selects a 128-bit XMM register or a 256-bit YMM register, determined by 
W A ModR/M byte follows the opcode and specifies the op erand. The operand is either a 128-bit XMM register, 
a 256-bit YMM register (determined by operand type), or  a memory address. If it is a memory address, the 
address is computed from a segment register and any of the following values: a base register, an index 
register, a scaling factor, and a displacement.
X Memory addressed by the DS:rSI register pair  (for example, MOVS, CMPS, OUTS, or LODS).
Y Memory addressed by the ES:rDI register pair (for example, MOVS, CMPS, INS, STOS, or SCAS).
A.2.2  Codes for Operand Type
The following abbreviations are us ed to document operand types:
a Two one-word operands in memory or two double-w ord operands in memory, depending on operand-size 
attribute (used only by the BOUND instruction).
b Byte, regardless of operand-size attribute.
c Byte or word, depending on operand-size attribute.
d Doubleword, regardless of operand-size attribute.Vol. 2D A-3OPCODE MAP
dq Double-quadword, regardless of operand-size attribute.
p 32-bit, 48-bit, or 80-bit pointer, depending on operand-size attribute.
pd 128-bit or 256-bit packed double precision floating-point data.pi Quadword MMX technology register (for example: mm0).
ps 128-bit or 256-bit packed single-precision floating-point data.
q Quadword, regardless of operand-size attribute.qq Quad-Quadword (256-bits), regard less of operand-size attribute.
s 6-byte or 10-byte pseudo-descriptor.
sd Scalar element of a 128-bit double precision floating data.ss Scalar element of a 128-bit single-precision floating data.

si Doubleword integer register (for example: eax).
v Word, doubleword or quadword (in 64-bit mo de), depending on operand-size attribute.
w Word, regardless of operand-size attribute.x dq or qq based on the operand-size attribute.
y Doubleword or quadword (in 64-bit mode),  depending on operand-size attribute.
z Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size.
A.2.3  Register Codes
When an opcode requires a specific register as an operand, the register is identified by name (for example, AX, CL, 
or ESI). The name indicates whether the register is 64, 32, 16, or 8 bits wide.
A register identifier of the form eXX or rXX is used when  register width depends on the operand-size attribute. eXX 
is used when 16 or 32-bit sizes are possible; rXX is used  when 16, 32, or 64-bit sizes are possible. For example: 
eAX indicates that the AX register is used when the operan d-size attribute is 16 and the EAX register is used when 
the operand-size attribute is 32. rAX can indicate AX, EAX or RAX.
When the REX.B bit is used to modify th e register specified in the reg field of the opcode, this fact is indicated by 
adding “/x” to the register name to indicate the additional  possibility. For example, rCX/r9 is used to indicate that 
the register could either be rCX or r9. Note that the size of  r9 in this case is determined by the operand size attri-
bute (just as for rCX).
A.2.4  Opcode Look-up Examples for One, Two, and Three-Byte Opcodes
This section provides examples that demonstrate how opcode maps are used. 
A.2.4.1  One-Byte Opcode Instructions
The opcode map for 1-byte opcodes is shown in Table A-2.  The opcode map for 1-byte opcodes is arranged by row 
(the least-significant 4 bits of the hexadecimal value) an d column (the most-significant 4 bits of the hexadecimal 
value). Each entry in the table lists one of the following types of opcodes:
•Instruction mnemonics and operand types using the notations listed in Section A.2
•Opcodes used as an instruction prefix
For each entry in the opcode map that corresponds to an instruction, the rules for interpreting the byte following 
the primary opcode fall into one of the following cases:
•A ModR/M byte is required and is interpreted according to the abbreviations listed in Section A.1 and Chapter 
2, “Instruction Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. 
Operand types are listed according to notations listed in Section A.2.A-4 Vol. 2DOPCODE MAP
•A ModR/M byte is required and includes an opcode exte nsion in the reg field in the ModR/M byte. Use Table A-6 
when interpreting the ModR/M byte.
•Use of the ModR/M byte is reserved or undefined. This a pplies to entries that represent an instruction prefix or 
entries for instructions without operands that us e ModR/M (for example: 60H, PUSHA; 06H , PUSH ES).
Example A-1.  Look-up Example for 1-Byte Opcodes
Opcode 030500000000H for an ADD instruction is interpreted using the 1-byte opcode map (Table A-2) as follows:
•The first digit (0) of the opcode indicates the table row and the second digit (3) indicates the table column. This 
locates an opcode for ADD with two operands. 
•The first operand (type Gv) indicates a general register th at is a word or doubleword depending on the operand-
size attribute. The second operand (type Ev) indicate s a ModR/M byte follows that specifies whether the 
operand is a word or doubleword genera l-purpose register or a memory address.
•The ModR/M byte for this instruction is 05H, indicati ng that a 32-bit displacement follows (00000000H). The 
reg/opcode portion of the ModR/M byte (bits 3-5) is 000, indicating the EAX register. 
The instruction for this opcode is ADD EAX, mem_op, and the offset of mem_op is 00000000H.
Some 1- and 2-byte opcodes point to group numbers (s haded entries in the opcode map table). Group numbers 
indicate that the instruction uses the reg/opcode bits in the ModR/M byte as an opcode extension (refer to Section 
A.4).
A.2.4.2  Two-Byte Opcode Instructions
The two-byte opcode map shown in Table A-3 includes prim ary opcodes that are either two bytes or three bytes in 
length. Primary opcodes that are 2 bytes in length begin wi th an escape opcode 0FH. The upper and lower four bits 
of the second opcode byte are used to inde x a particular row and column in Table A-3. 
Two-byte opcodes that are 3 bytes in length begin with a mandatory prefix (66H, F2H,  or F3H) and the escape 
opcode (0FH). The upper and lower four bi ts of the third byte are used to index a particular row and column in Table 
A-3 (except when the second opcode byte is the 3-byte escape opcodes 38H or 3AH; in this situation refer to 
Section A.2.4.3). 
For each entry in the opcode map, the rules for interpreti ng the byte following the primary opcode fall into one of 
the following cases:
2, “Instruction Format,” of the Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 2A. The 
operand types are listed according to notations listed in Section A.2.
•Use of the ModR/M byte is reserved or undefined. This applies to entries that represent an instruction without 
operands that are encoded using Mo dR/M (for example: 0F77H, EMMS).
Example A-2.  Look-up Example for 2-Byte Opcodes
Look-up opcode 0FA4050000000003H for a SHLD instruction using Table A-3.
•The opcode is located in row A, column 4. The location indicates a SHLD instruction with operands Ev, Gv, and 
Ib. Interpret the operands as follows:
— Ev: The ModR/M byte follows the opcode to specify a word or doubleword operand.
— Gv: The reg field of the ModR/M byte selects a general-purpose register.
— Ib: Immediate data is encoded in th e subsequent byte of the instruction.
•The third byte is the ModR/M byte (05H). The mod and opcode/reg fields of ModR/M indicate that a 32-bit 
displacement is used to locate the first oper and in memory and eAX as the second operand.
•The next part of the opcode is the 32-bit displaceme nt for the destination memory operand (00000000H). The 
last byte stores immediate byte that provides the count of the shift (03H).Vol. 2D A-5OPCODE MAP
•By this breakdown, it has been show n that this opcode represents the instruction: SHLD DS:00000000H, EAX, 
3.
A.2.4.3  Three-Byte Opcode Instructions
The three-byte opcode maps shown in Table A-4 and Tabl e A-5 includes primary opcodes that are either 3 or 4 
bytes in length. Primary opcodes that are 3 bytes in leng th begin with two escape bytes 0F38H or 0F3A. The upper 
and lower four bits of the third opcode byte are used to index a particular row and column in Table A-4 or Table A-5. 
Three-byte opcodes that are 4 bytes in  length begin with a mandatory prefix  (66H, F2H, or F3H) and two escape 
bytes (0F38H or 0F3AH). The upper and lower four bits of the fourth byte are used to index a particular row and 
column in Table A-4 or Table A-5. 
For each entry in the opcode map, the rules for interpre ting the byte following the primary opcode fall into the 
following case:
•A ModR/M byte is required and is interpreted accordin g to the abbreviations list ed in A.1 and Chapter 2, 
“Instruction Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. The 
Example A-3.  Look-up Example for 3-Byte Opcodes
Look-up opcode 660F3A0FC108H for a PALIGNR instruction using Table A-5.
•66H is a prefix and 0F3AH indicate to use Table A-5. Th e opcode is located in row 0, column F indicating a 
PALIGNR instruction with operands Vdq, Wdq,  and Ib. Interpret the operands as follows:
— Vdq: The reg field of the ModR/M byte selects a 128-bit XMM register.
— Wdq: The R/M field of the ModR/M byte selects ei ther a 128-bit XMM register or memory location.
•The next byte is the ModR/M byte (C1H). The reg field indicates that the first oper and is XMM0. The mod shows 
that the R/M field specifies a register and the R/M indicates that the second operand is XMM1.
•The last byte is the immediate byte (08H).
•By this breakdown, it has been shown that this opco de represents the instruction: PALIGNR XMM0, XMM1, 8.
A.2.4.4  VEX Prefix Instructions
Instructions that include a VEX prefix are organized relati ve to the 2-byte and 3-byte opcode maps, based on the 
VEX.mmmmm field encoding of implied 0F, 0F38H, 0F3AH, re spectively. Each entry in the opcode map of a VEX-
encoded instruction is based on the value of the opcode byte, similar to non-VEX-encoded instructions. 
A VEX prefix includes several bit fields that encode im plied 66H, F2H, F3H prefix functionality (VEX.pp) and

A VEX prefix includes several bit fields that encode im plied 66H, F2H, F3H prefix functionality (VEX.pp) and 
operand size/opcode information (VEX .L). See chapter 4 for details. 
Opcode tables A2-A6 include both instructions with a VEX prefix and instructions without a VEX prefix. Many entries 
are only made once, but represent both the VEX and non-VEX forms of the instruction. If the VEX prefix is present 
all the operands are valid and the mnemonic is usually pref ixed with a “v”. If the VEX prefix is not present the 
VEX.vvvv operand is not available and the prefix “v” is dropped from the mnemonic. 
A few instructions exist only in VEX form and these are marked with a superscript “v”.
Operand size of VEX prefix instructions can be determined  by the operand type code. 128-bit vectors are indicated 
by 'dq', 256-bit vectors are indicated by 'qq', and instru ctions with operands supporting either 128 or 256-bit, 
determined by VEX.L, are indicated by  'x'. For example, the entry "VMOVUPD  Vx,Wx" indicates both VEX.L=0 and 
VEX.L=1 are supported. A-6 Vol. 2DOPCODE MAP
A.2.5  Superscripts Utilized in Opcode Tables
Table A-1 contains notes on particular encodings. These notes are indicated in the following opcode maps by super-
scripts. Gray cells indicate instruction groupings.
A.3 ONE, TWO, AND THREE-BYTE OPCODE MAPS
See Table A-2 through Table A-5 below. The tables are multiple page presentations. Rows and columns with 
sequential relationships are placed on facing pages to ma ke look-up tasks easier. Note that table footnotes are not 
presented on each page. Table footnotes for each ta ble are presented on the last page of the table.Table A-1.  Superscripts Utilized in Opcode Tables
Superscript
SymbolMeaning of Symbol
1A Bits 5, 4, and 3 of ModR/M byte used as an opcode exte nsion (refer to Section A.4, “Opcode Extensions For One-Byte 
And Two-byte Opcodes”).
1B Use the 0F0B opcode (UD2 instruction), the 0FB9H opcode (UD1 instruction), or the 0FFFH opcode (UD0 instruction) 
when deliberately trying to generate an invalid opcode exception (#UD).
1C Some instructions use the same two- byte opcode. If the instruction has variations, or the opcode represents 
different instructions, the ModR/M byte will be used to differentiate the inst ruction. For the value of the ModR/M 
byte needed to decode the instruction, see Table A-6. 
i64 The instruction is invalid or not encodable in 64-bit mode. 40 through 4F (single-byte INC and DEC) are REX prefix 
combinations when in 64-bit mode (use FE/FF Grp 4 and 5 for INC and DEC).
o64 Instruction is only available when in 64-bit mode.d64 When in 64-bit mode, instruction defaults to 64-bit operand size and cannot encode 32-bit operand size. 
f64 The operand size is forced  to a 64-bit operand size when  in 64-bit mode (prefixes that change operand size are 
ignored for this instruction in 64-bit mode).
v VEX form only exists. There is no le gacy SSE form of the instruction. For Integer GPR instructions it means VEX 
prefix required.
v1 VEX128 & SSE forms only exist (no VEX256), when can’t be inferred  from the data size.Vol. 2D A-7OPCODE MAP
Table A-2.  One-byte Opco de Map: (00H — F7H) *
01 2 3456 7
0 ADD PUSH
ESi64POP
ESi64
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
1 ADC PUSH
SSi64POP
SSi64
2 AND SEG=ES
(Prefix)DAAi64
3 XOR SEG=SS
(Prefix)AAAi64
4 INCi64 general register / REXo64 Prefixes
eAX
REXeCX
REX.BeDX
REX.XeBX
REX.XBeSP
REX.ReBP
REX.RBeSI
REX.RXeDI
REX.RXB
5 PUSHd64 general register
rAX/r8 rCX/r9 rDX/r10 rBX/r11 rSP/r12 rBP/r13 rSI/r14 rDI/r15 
6 PUSHAi64/
PUSHADi64POPAi64/
POPADi64BOUNDi64
Gv, MaARPLi64
Ew, Gw
MOVSXDo64
Gv, EvSEG=FS
(Prefix)SEG=GS
(Prefix)Operand
Size
(Prefix)Address
Size
(Prefix)
7 Jccf64, Jb - Short-displacement jump on condition
O NO B/NAE/C NB/AE/NC Z/E NZ/NE BE/NA NBE/A
8 Immediate Grp 11ATEST XCHG 
Eb, Ib Ev, Iz  Eb, Ibi64Ev, Ib Eb, Gb Ev, Gv Eb, Gb Ev, Gv 
9N O P  
PAUSE(F3)
XCHG r8, rAXXCHG word, double-word or quad-word register with rAX
rCX/r9 rDX/r10 rBX/r11 rSP/r12 rBP/r13 rSI/r14 rDI/r15
A MOV MOVS/B
Yb, XbMOVS/W/D/Q
Yv, Xv CMPS/B
Xb, Yb CMPS/W/D
Xv, YvAL, Ob rAX, Ov Ob, AL Ov, rAX 
B MOV immediate byte into byte register
AL/R8B, Ib CL/R9B, Ib DL/R10B, Ib BL/R11B, Ib AH/R12B, Ib CH/R13B, Ib DH/R14B, Ib BH/R15B, Ib
C Shift Grp 21Anear RETf64
Iwnear RETf64LESi64
Gz, Mp 
VEX+2byteLDSi64
Gz, Mp 
VEX+1byteGrp 111A - MOV
Eb, Ib Ev, Ib Eb, Ib Ev, Iz
D Shift Grp 21AAAMi64
IbAADi64
IbXLAT/
XLATB Eb, 1 Ev, 1 Eb, CL Ev, CL 
E LOOPNEf64/
LOOPNZf64
Jb LOOPEf64/
LOOPZf64
Jb LOOPf64
Jb JrCXZf64/
Jb IN OUT
AL, Ib eAX, Ib Ib, AL Ib, eAX
FL O C K
(Prefix)INT1 REPNE
XACQUIRE
(Prefix) REP/REPE 
XRELEASE
(Prefix)HLT CMC Unary Grp 31A
Eb EvA-8 Vol. 2DOPCODE MAP
Table A-2. One-byte Opcode Map: (08H — FFH) *
89ABC DEF
0O R P U S H
CSi642-byte
escape
(Table A-3) Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
1 SBB PUSH
DSi64POP
DSi64
2 SUB SEG=CS 
(Prefix)DASi64 
3 CMP SEG=DS 
(Prefix)AASi64 
4D E Ci64 general register / REXo64 Prefixes
eAX
REX.WeCX
REX.WBeDX
REX.WXeBX
REX.WXBeSP
REX.WReBP
REX.WRBeSI
REX.WRXeDI 
REX.WRXB
5 POPd64 into general register
6P U S Hd64
IzIMUL
Gv, Ev, IzPUSHd64
IbIMUL
Gv, Ev, IbINS/
INSB
Yb, DXINS/
INSW/
INSD
Yz, DXOUTS/
OUTSB
DX, XbOUTS/
OUTSW/
OUTSD
DX, Xz
7 Jccf64, Jb- Short displacement jump on condition
S NS P/PE NP/PO L/NGE NL/GE LE/NG NLE/G 
8M O VM O V
Ev, SwLEA
Gv, M MOV
Sw, EwGrp 1A1A POPd64 
EvEb, Gb Ev, Gv Gb, Eb Gv, Ev 
9C B W /
CWDE/
CDQECWD/
CDQ/
CQOfar CALLi64
ApFWAIT/
WAITPUSHF/D/Q d64/
FvPOPF/D/Q d64/
FvSAHF LAHF
AT E S T S T O S / B
Yb, AL STOS/W/D/Q
Yv, rAX LODS/B
AL, Xb LODS/W/D/Q
rAX, XvSCAS/B
AL, YbSCAS/W/D/Q
rAX, YvAL, Ib rAX, Iz
B MOV immediate word or double into word, double, or quad register
rAX/r8, Iv rCX/r9, Iv rDX/r10, Iv rBX/r11, Iv rSP/r12, Iv rBP/r13, Iv rSI/r14, Iv rDI/r15 , Iv
CE N T E R L E A V Ed64far RET far RET INT3 INT INTOi64IRET/D/Q 
Iw, Ib Iw Ib
D ESC (Escape to coprocessor instruction set)
En e a r  C A L Lf64JMP IN OUT
Jz nearf64
Jzfari64
Apshortf64
JbAL, DX eAX, DX DX, AL DX, eAX 
F CLC STC CLI STI CLD STD INC/DEC INC/DEC
Grp 41AGrp 51A
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.Vol. 2D A-9OPCODE MAP
Table A-3.  Two-byte Opcode Map: 00H — 77H (First Byte is 0FH) *
pfx 0 1 2 3 4 5 6 7
0Grp 61AGrp 71ALAR
Gv, Ew LSL
Gv, Ew  SYSCALLo64CLTS SYSRETo64
1vmovups
Vps, Wpsvmovups
Wps, Vpsvmovlps
Vq, Hq, Mq
vmovhlps
Vq, Hq, Uqvmovlps
Mq, Vqvunpcklps
Vx, Hx, Wxvunpckhps
Vx, Hx, Wxvmovhpsv1
Vdq, Hq, Mq 
vmovlhps
Vdq, Hq, Uqvmovhpsv1
Mq, Vq
66vmovupd
Vpd, Wpdvmovupd
Wpd,Vpdvmovlpd
Vq, Hq, Mqvmovlpd
Mq, Vqvunpcklpd
Vx,Hx,Wxvunpckhpd
Vx,Hx,Wxvmovhpdv1
Vdq, Hq, Mqvmovhpdv1
Mq, Vq
F3vmovss
Vx, Hx, Wssvmovss
Wss, Hx, Vssvmovsldup 
Vx, Wxvmovshdup 
Vx, Wx
F2vmovsd
Vx, Hx, Wsdvmovsd
Wsd, Hx, Vsdvmovddup
Vx, Wx
2MOV
Rd, CdMOV
Rd, DdMOV
Cd, RdMOV
Dd, Rd
3WRMSR RDTSC  RDMSR RDPMC SYSENTER SYSEXIT GETSEC
4CMOVcc, (Gv, Ev) - Conditional Move
O NO B/C/NAE AE/NB/NC E/Z NE/NZ BE/NA A/NBE
5vmovmskps
Gy, Upsvsqrtps
Vps, Wpsvrsqrtps
Vps, Wpsvrcpps
Vps, Wpsvandps
Vps, Hps, Wpsvandnps
Vps, Hps, Wpsvorps
Vps, Hps, Wpsvxorps
Vps, Hps, Wps
66vmovmskpd 
Gy,Updvsqrtpd
Vpd, Wpdvandpd
Vpd, Hpd, Wpdvandnpd
Vpd, Hpd, Wpdvorpd
Vpd, Hpd, Wpdvxorpd
Vpd, Hpd, Wpd
F3vsqrtss
Vss, Hss, Wssvrsqrtss
Vss, Hss, Wssvrcpss
Vss, Hss, Wss
F2vsqrtsd
Vsd, Hsd, Wsd 
6punpcklbw
Pq, Qdpunpcklwd
Pq, Qdpunpckldq
Pq, Qdpacksswb
Pq, Qqpcmpgtb
Pq, Qqpcmpgtw
Pq, Qqpcmpgtd
Pq, Qqpackuswb
Pq, Qq
66vpunpcklbw
Vx, Hx, Wxvpunpcklwd
Vx, Hx, Wxvpunpckldq
Vx, Hx, Wxvpacksswb
Vx, Hx, Wxvpcmpgtb
Vx, Hx, Wxvpcmpgtw
Vx, Hx, Wxvpcmpgtd
Vx, Hx, Wxvpackuswb
Vx, Hx, Wx
F3
7pshufw
Pq, Qq, Ib(Grp 121A) (Grp 131A) (Grp 141A) pcmpeqb
Pq, Qqpcmpeqw
Pq, Qqpcmpeqd
Pq, Qqemms 
vzeroupperv 
vzeroallv
66vpshufd
Vx, Wx, Ibvpcmpeqb
Vx, Hx, Wxvpcmpeqw
Vx, Hx, Wxvpcmpeqd
Vx, Hx, Wx
F3vpshufhw
Vx, Wx, Ib
F2vpshuflw
Vx, Wx, IbA-10 Vol. 2DOPCODE MAP
Table A-3. Two-byte Opcode Map: 08H — 7FH (First Byte is 0FH) *
pfx 8 9 A B C D E F
0 INVD WBINVD 2-byte Illegal 
Opcodes
UD21B prefetchw(/1)
Ev
1Prefetch1C
(Grp 161A)Reserved-NOP bndldx bndstx Reserved-NOP NOP /0 Ev
66 bndmov bndmov
F3 bndcl bndmk
F2bndcu bndcn
2 vmovaps
Vps, Wpsvmovaps
Wps, Vpscvtpi2ps
Vps, Qpivmovntps
Mps, Vps cvttps2pi
Ppi, Wpscvtps2pi
Ppi, Wpsvucomiss
Vss, Wssvcomiss
Vss, Wss
66vmovapd
Vpd, Wpdvmovapd
Wpd,Vpdcvtpi2pd
Vpd, Qpivmovntpd
Mpd, Vpdcvttpd2pi
Ppi, Wpdcvtpd2pi
Qpi, Wpdvucomisd
Vsd, Wsdvcomisd
Vsd, Wsd
F3vcvtsi2ss
Vss, Hss, Eyvcvttss2si
Gy, Wssvcvtss2si
Gy, Wss
F2vcvtsi2sd
Vsd, Hsd, Ey vcvttsd2si
Gy, Wsd vcvtsd2si
Gy, Wsd 
3 3-byte escape
(Table A-4) 3-byte escape
(Table A-5) 
4 CMOVcc(Gv, Ev) - Conditional Move 
S NS P/PE NP/PO L/NGE NL/GE LE/NG NLE/G
5vaddps
Vps, Hps, Wpsvmulps
Vps, Hps, Wpsvcvtps2pd
Vpd, Wpsvcvtdq2ps
Vps, Wdqvsubps 
Vps, Hps, Wpsvminps
Vps, Hps, Wpsvdivps
Vps, Hps, Wpsvmaxps
66vaddpd

Opcodes
Ev
2 vmovaps
Vss, Wss
66vmovapd
Vsd, Wsd
Gy, Wss
Gy, Wsd 
5vaddps
66vaddpd
Vpd, Hpd, Wpdvmulpd
Vpd, Hpd, Wpdvcvtpd2ps
Vps, Wpdvcvtps2dq
Vdq, Wpsvsubpd
Vpd, Hpd, Wpdvminpd
Vpd, Hpd, Wpdvdivpd
Vpd, Hpd, Wpdvmaxpd
F3vaddss
Vss, Hss, Wssvmulss
Vss, Hss, Wssvcvtss2sd
Vsd, Hx, Wssvcvttps2dq
Vdq, Wpsvsubss
Vss, Hss, Wssvminss
Vss, Hss, Wssvdivss
Vss, Hss, Wssvmaxss
F2vaddsd
Vsd, Hsd, Wsd vmulsd
Vsd, Hsd, Wsd vcvtsd2ss
Vss, Hx, Wsd vsubsd
Vsd, Hsd, Wsd vminsd
Vsd, Hsd, Wsd vdivsd
Vsd, Hsd, Wsd vmaxsd
6punpckhbw
Pq, Qdpunpckhwd
Pq, Qdpunpckhdq
Pq, Qdpackssdw
Pq, Qdmovd/q
Pd, Eymovq
Pq, Qq
66vpunpckhbw
Vx, Hx, Wxvpunpckhwd
Vx, Hx, Wxvpunpckhdq
Vx, Hx, Wxvpackssdw
Vx, Hx, Wxvpunpcklqdq
Vx, Hx, Wxvpunpckhqdq
Vx, Hx, Wxvmovd/q
Vy, Eyvmovdqa 
Vx, Wx
F3vmovdqu
Vx, Wx
7VMREAD
Ey, GyVMWRITE
Gy, Eymovd/q
Ey, Pdmovq
Qq, Pq
66vhaddpd
Vpd, Hpd, Wpdvhsubpd
Vpd, Hpd, Wpdvmovd/q
Ey, Vyvmovdqa
Wx,Vx
F3vmovq
Vq, Wqvmovdqu
Wx,Vx
F2vhaddps
Vps, Hps, Wpsvhsubps
Vps, Hps, WpsVol. 2D A-11OPCODE MAP
Table A-3. Two-byte Opcode Map: 80H — F7H (First Byte is 0FH) *
8Jccf64, Jz - Long-displacement jump on condition
O NO B/CNAE AE/NB/NC E/Z NE/NZ BE/NA A/NBE
9SETcc, Eb - Byte Set on condition
APUSHd64
FSPOPd64
FSCPUID BT
Ev, Gv SHLD
Ev, Gv, Ib SHLD
Ev, Gv, CL  
BCMPXCHG LSS
Gv, Mp BTR
Ev, Gv LFS
Gv, Mp LGS
Gv, Mp MOVZX
Eb, Gb Ev, Gv Gv, Eb Gv, Ew 
CXADD
Eb, GbXADD
Ev, Gvvcmpps
Vps,Hps,Wps,Ibmovnti
My, Gypinsrw
Pq,Ry/Mw,Ibpextrw
Gd, Nq, Ibvshufps
Vps,Hps,Wps,IbGrp 91A
66vcmppd
Vpd,Hpd,Wpd,Ibvpinsrw
Vdq,Hdq,Ry/Mw,Ibvpextrw
Gd, Udq, Ibvshufpd
Vpd,Hpd,Wpd,Ib
F3vcmpss
Vss,Hss,Wss,Ib
F2vcmpsd
Vsd,Hsd,Wsd,Ib
Dpsrlw
Pq, Qqpsrld
Pq, Qqpsrlq
Pq, Qqpaddq
Pq, Qqpmullw
Pq, Qqpmovmskb
Gd, Nq
66vaddsubpd
Vpd, Hpd, Wpdvpsrlw
Vx, Hx, Wxvpsrld
Vx, Hx, Wxvpsrlq
Vx, Hx, Wxvpaddq
Vx, Hx, Wxvpmullw
Vx, Hx, Wxvmovq
Wq, Vqvpmovmskb 
Gd, Ux
F3movq2dq
Vdq, Nq
F2vaddsubps
Vps, Hps, Wpsmovdq2q
Pq, Uq
Epavgb
Pq, Qqpsraw
Pq, Qqpsrad
Pq, Qqpavgw
Pq, Qqpmulhuw
Pq, Qqpmulhw
Pq, Qqmovntq
Mq, Pq
66vpavgb
Vx, Hx, Wxvpsraw
Vx, Hx, Wxvpsrad
Vx, Hx, Wxvpavgw
Vx, Hx, Wxvpmulhuw
Vx, Hx, Wxvpmulhw
Vx, Hx, Wxvcvttpd2dq
Vx, Wpdvmovntdq
Mx, Vx
F3vcvtdq2pd
Vx, Wpd
F2vcvtpd2dq
Vx, Wpd
Fpsllw
Pq, Qqpslld
Pq, Qqpsllq
Pq, Qqpmuludq
Pq, Qqpmaddwd
Pq, Qqpsadbw
Pq, Qqmaskmovq
Pq, Nq
66vpsllw
Vx, Hx, Wxvpslld
Vx, Hx, Wxvpsllq
Vx, Hx, Wxvpmuludq
Vx, Hx, Wxvpmaddwd 
Vx, Hx, Wxvpsadbw
Vx, Hx, Wxvmaskmovdqu
Vdq, Udq
F2vlddqu
Vx, MxA-12 Vol. 2DOPCODE MAP
Table A-3. Two-byte Opcode Map: 88H — FFH (First Byte is 0FH) * 
8  Jccf64, Jz - Long-displacement jump on condition
9 SETcc, Eb - Byte Set on condition
A PUSHd64
GSPOPd64
GSRSM BTS
Ev, Gv SHRD
Ev, Gv, Ib SHRD
Ev, Gv, CL (Grp 151A)1CIMUL
Gv, Ev 
B  JMPE
(reserved for 
emulator on IPF)Grp 101A
Invalid Opcode1BGrp 81A
Ev, IbBTC
Ev, GvBSF
Gv, EvBSR
Gv, EvMOVSX
Gv, Eb Gv, Ew
F3POPCNT
Gv, EvTZCNT 
Gv, EvLZCNT 
Gv, Ev
C  BSWAP
RAX/EAX/
R8/R8DRCX/ECX/ 
R9/R9DRDX/EDX/ 
R10/R10DRBX/EBX/ 
R11/R11DRSP/ESP/ 
R12/R12DRBP/EBP/ 
R13/R13DRSI/ESI/ 
R14/R14DRDI/EDI/ 
R15/R15D
Dpsubusb
Pq, Qqpsubusw
Pq, Qqpminub
Pq, Qqpand
Pq, Qqpaddusb
Pq, Qqpaddusw
Pq, Qqpmaxub
Pq, Qqpandn
Pq, Qq
66vpsubusb
Vx, Hx, Wxvpsubusw
Vx, Hx, Wxvpminub
Vx, Hx, Wxvpand
Vx, Hx, Wxvpaddusb
Vx, Hx, Wxvpaddusw
Vx, Hx, Wxvpmaxub
Vx, Hx, Wxvpandn
Vx, Hx, Wx
F3
F2
Epsubsb
Pq, Qqpsubsw
Pq, Qqpminsw
Pq, Qqpor
Pq, Qqpaddsb
Pq, Qqpaddsw
Pq, Qqpmaxsw
Pq, Qqpxor
Pq, Qq
66vpsubsb
Vx, Hx, Wxvpsubsw
Vx, Hx, Wxvpminsw
Vx, Hx, Wxvpor
Vx, Hx, Wxvpaddsb
Vx, Hx, Wxvpaddsw
Vx, Hx, Wxvpmaxsw
Vx, Hx, Wxvpxor
Vx, Hx, Wx
F3
F2
Fpsubb
Pq, Qqpsubw
Pq, Qqpsubd
Pq, Qqpsubq
Pq, Qqpaddb
Pq, Qqpaddw
Pq, Qqpaddd
Pq, QqUD0
66vpsubb
Vx, Hx, Wxvpsubw
Vx, Hx, Wx vpsubd
Vx, Hx, Wxvpsubq
Vx, Hx, Wxvpaddb
Vx, Hx, Wxvpaddw
Vx, Hx, Wx vpaddd
Vx, Hx, Wx
F2
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.Vol. 2D A-13OPCODE MAP
Table A-4.  Three-byte Opcode Map: 00 H — F7H (First Two By tes are 0F 38H) *
p f x 012345 6 7
0pshufb
Pq, Qqphaddw
Pq, Qqphaddd
Pq, Qqphaddsw
Pq, Qqpmaddubsw
Pq, Qqphsubw
Pq, Qqphsubd
Pq, Qqphsubsw
Pq, Qq
66vpshufb
Vx, Hx, Wxvphaddw
Vx, Hx, Wxvphaddd
Vx, Hx, Wxvphaddsw
Vx, Hx, Wxvpmaddubsw
Vx, Hx, Wxvphsubw
Vx, Hx, Wxvphsubd
Vx, Hx, Wxvphsubsw
Vx, Hx, Wx
16 6pblendvb
Vdq, Wdqvcvtph2psv
Vx, Wx, Ibblendvps
Vdq, Wdqblendvpd
Vdq, Wdqvpermpsv
Vqq, Hqq, Wqqvptest
Vx, Wx
26 6vpmovsxbw
Vx, Ux/Mqvpmovsxbd
Vx, Ux/Mdvpmovsxbq
Vx, Ux/Mwvpmovsxwd
Vx, Ux/Mqvpmovsxwq
Vx, Ux/Mdvpmovsxdq
Vx, Ux/Mq
36 6vpmovzxbw
Vx, Ux/Mqvpmovzxbd
Vx, Ux/Mdvpmovzxbq
Vx, Ux/Mwvpmovzxwd
Vx, Ux/Mqvpmovzxwq
Vx, Ux/Mdvpmovzxdq
Vx, Ux/Mqvpermdv
Vqq, Hqq, Wqqvpcmpgtq
Vx, Hx, Wx
46 6vpmulld
Vx, Hx, Wxvphminposuw 
Vdq, Wdqvpsrlvd/qv
Vx, Hx, Wxvpsravdv
Vx, Hx, Wxvpsllvd/qv
Vx, Hx, Wx
5
6
7
86 6INVEPT 
Gy, MdqINVVPID 
Gy, MdqINVPCID 
Gy, Mdq
96 6vgatherdd/qv 
Vx,Hx,Wxvgatherqd/qv 
Vx,Hx,Wxvgatherdps/dv 
Vx,Hx,Wxvgatherqps/dv 
Vx,Hx,Wxvfmaddsub132ps/dv 
Vx,Hx,Wxvfmsubadd132ps/dv 
Vx,Hx,Wx
A6 6vfmaddsub213ps/dv 
Vx,Hx,Wxvfmsubadd213ps/dv 
Vx,Hx,Wx
B6 6vfmaddsub231ps/dv 
Vx,Hx,Wxvfmsubadd231ps/dv 
Vx,Hx,Wx
C
D
E
FMOVBE 
Gy, MyMOVBE 
My, GyANDNv
Gy, By, Ey
Grp 171ABZHIv
Gy, Ey, ByBEXTRv
Gy, Ey, By
66MOVBE 
Gw, MwMOVBE 
Mw, GwADCX
Gy, EySHLXv
Gy, Ey, By
F3PEXTv
Gy, By, EyADOX
Gy, EySARXv
Gy, Ey, By
F2CRC32 
Gd, EbCRC32 
Gd, EyPDEPv
Gy, By, EyMULXv
By,Gy,rDX,EySHRXv
Gy, Ey, By
66 & 
F2CRC32 
Gd, EwA-14 Vol. 2DOPCODE MAP
Table A-4. Three-byte Opcode Map: 08H — FFH (First Two Bytes are 0F 38H) *
0psignb
Pq, Qqpsignw
Pq, Qqpsignd
Pq, Qqpmulhrsw
Pq, Qq
66vpsignb
Vx, Hx, Wxvpsignw
Vx, Hx, Wxvpsignd
Vx, Hx, Wxvpmulhrsw 
Vx, Hx, Wxvpermilpsv 
Vx,Hx,Wxvpermilpdv 
Vx,Hx,Wxvtestpsv 
Vx, Wxvtestpdv 
Vx, Wx
1pabsb
Pq, Qqpabsw
Pq, Qqpabsd
Pq, Qq
66vbroadcastssv 
Vx, Wdvbroadcastsdv Vqq, 
Wqvbroadcastf128v Vqq, 
Mdqvpabsb
Vx, Wxvpabsw
Vx, Wxvpabsd
Vx, Wx
26 6vpmuldq
Vx, Hx, Wxvpcmpeqq
Vx, Hx, Wxvmovntdqa
Vx, Mxvpackusdw
Vx, Hx, Wxvmaskmovpsv 
Vx,Hx,Mxvmaskmovpdv 
Vx,Hx,Mxvmaskmovpsv 
Mx,Hx,Vxvmaskmovpdv 
Mx,Hx,Vx
36 6vpminsb
Vx, Hx, Wxvpminsd
Vx, Hx, Wxvpminuw
Vx, Hx, Wxvpminud
Vx, Hx, Wxvpmaxsb
Vx, Hx, Wxvpmaxsd
Vx, Hx, Wxvpmaxuw
Vx, Hx, Wxvpmaxud
Vx, Hx, Wx
4
56 6vpbroadcastdv 
Vx, Wxvpbroadcastqv 
Vx, Wxvbroadcasti128v 
Vqq, Mdq
6
76 6vpbroadcastbv 
Vx, Wxvpbroadcastwv 
Vx, Wx
86 6vpmaskmovd/qv 
Vx,Hx,Mxvpmaskmovd/qv 
Mx,Vx,Hx
96 6vfmadd132ps/dv 
Vx, Hx, Wxvfmadd132ss/dv 
Vx, Hx, Wxvfmsub132ps/dv 
Vx, Hx, Wxvfmsub132ss/dv 
Vx, Hx, Wxvfnmadd132ps/dv 
Vx, Hx, Wxvfnmadd132ss/dv 
Vx, Hx, Wxvfnmsub132ps/dv 
Vx, Hx, Wxvfnmsub132ss/dv 
Vx, Hx, Wx
A6 6vfmadd213ps/dv 
Vx, Hx, Wxvfmadd213ss/dv 
Vx, Hx, Wxvfmsub213ps/dv 
Vx, Hx, Wxvfmsub213ss/dv 
Vx, Hx, Wxvfnmadd213ps/dv 
Vx, Hx, Wxvfnmadd213ss/dv 
Vx, Hx, Wxvfnmsub213ps/dv 
Vx, Hx, Wxvfnmsub213ss/dv 
Vx, Hx, Wx
B6 6vfmadd231ps/dv 
Vx, Hx, Wxvfmadd231ss/dv 
Vx, Hx, Wxvfmsub231ps/dv 
Vx, Hx, Wxvfmsub231ss/dv 
Vx, Hx, Wxvfnmadd231ps/dv 
Vx, Hx, Wxvfnmadd231ss/dv 
Vx, Hx, Wxvfnmsub231ps/dv 
Vx, Hx, Wxvfnmsub231ss/dv 
Vx, Hx, Wx
Csha1nexte
Vdq,Wdqsha1msg1
Vdq,Wdqsha1msg2
Vdq,Wdqsha256rnds2
Vdq,Wdqsha256msg1
Vdq,Wdqsha256msg2
Vdq,Wdq
66
D6 6VAESIMC 
Vdq, WdqVAESENC 
Vdq,Hdq,WdqVAESENCLAST 
Vdq,Hdq,WdqVAESDEC 
Vdq,Hdq,WdqVAESDECLAST 
Vdq,Hdq,Wdq
E
F66
F3F2
66 & F2
NOTES:
*All blanks in all opcode maps are reserved and must not be us ed. Do not depend on the operation of undefined or reserved locati ons. Vol. 2D A-15OPCODE MAP
Table A-5.  Three-byte Opcode Map: 00H  — F7H (First two bytes are 0F 3AH) *
p f x 0123456 7
06 6vpermqv
Vqq, Wqq, Ibvpermpdv
Vqq, Wqq, Ibvpblenddv
Vx,Hx,Wx,Ibvpermilpsv 
Vx, Wx, Ibvpermilpdv 
Vx, Wx, Ibvperm2f128v 
Vqq,Hqq,Wqq,Ib
16 6vpextrb
Rd/Mb, Vdq, Ibvpextrw
Rd/Mw, Vdq, Ibvpextrd/q 
Ey, Vdq, Ib vextractps 
Ed, Vdq, Ib
26 6vpinsrb
Vdq,Hdq,Ry/Mb,Ibvinsertps
Vdq,Hdq,Udq/Md,Ibvpinsrd/q
Vdq,Hdq,Ey,Ib 
3
46 6vdpps
Vx,Hx,Wx,Ibvdppd
Vdq,Hdq,Wdq,Ibvmpsadbw
Vx,Hx,Wx,Ibvpclmulqdq
Vdq,Hdq,Wdq,Ibvperm2i128v
5
66 6vpcmpestrm
Vdq, Wdq, Ib vpcmpestri 
Vdq, Wdq, Ib vpcmpistrm 
Vdq, Wdq, Ib vpcmpistri
Vdq, Wdq, Ib 
789
AB
C
D
E
FF2RORX
v
Gy, Ey, IbA-16 Vol. 2DOPCODE MAP
Table A-5. Three-byte Opcode Map: 08 H — FFH (First Two Bytes are 0F 3AH) *
0palignr
Pq, Qq, Ib
66vroundps
Vx,Wx,Ibvroundpd
Vx,Wx,Ibvroundss
Vss,Wss,Ibvroundsd
Vsd,Wsd,Ibvblendps
Vx,Hx,Wx,Ibvblendpd
Vx,Hx,Wx,Ibvpblendw
Vx,Hx,Wx,Ibvpalignr
Vx,Hx,Wx,Ib
16 6vinsertf128v 
Vqq,Hqq,Wqq,Ibvextractf128v 
Wdq,Vqq,Ibvcvtps2phv
Wx, Vx, Ib
2
36 6vinserti128v 
Vqq,Hqq,Wqq,Ibvextracti128v 
Wdq,Vqq,Ib
46 6vblendvpsv
 Vx,Hx,Wx,Lxvblendvpdv 
Vx,Hx,Wx,Lxvpblendvbv
Vx,Hx,Wx,Lx
5
6
7
89
AB
Csha1rnds4
Vdq,Wdq,Ib
D6 6VAESKEYGEN 
Vdq, Wdq, Ib
E
F
NOTES:
*All blanks in all opcode maps are reserved and must not be us ed. Do not depend on the operation of undefined or reserved locati ons.Vol. 2D A-17OPCODE MAP
A.4 OPCODE EXTENSIONS FOR ON E-BYTE AND TWO-BYTE OPCODES

5
789
AB
C
D
E
FF2RORX
v
0palignr
Pq, Qq, Ib
Wx, Vx, Ib
2
5
6
7
89
AB
E
F
NOTES:
Some 1-byte and 2-byte opcodes use bits 3-5 of the ModR/M  byte (the nnn field in Figure A-1) as an extension of 
the opcode.
Opcodes that have opcode extensions  are indicated in Table A-6 and orga nized by group number. Group numbers 
(from 1 to 16, second column) provide a table entry point. The encoding for the r/m field for ea ch instruction can 
be established using the third column of the table.
A.4.1  Opcode Look-up Examples Using Opcode Extensions
An Example is provided below.
Example A-4.  Interpreting an ADD Instruction
An ADD instruction with a 1-byte opco de of 80H is a Group 1 instruction:
•Table A-6 indicates that the opcode extension field enco ded in the ModR/M byte for this instruction is 000B. 
•The r/m field can be encoded to access a register (11B) or a memory address using a specified addressing 
mode (for example: mem = 00B, 01B, 10B).
Example A-5.  Looking Up 0F01C3H
Look up opcode 0F01C3 for a VMRESUME instructio n by using Table A-2, Table A-3, and Table A-6:
•0F indicates that this instruction is in the 2-byte opcode map.
•01 (row 0, column 1 in Table A-3) reveals that this opcode is in Group 7 of Table A-6.
•C3 is the ModR/M byte. The first two bits of C3 are 11B. Th is tells us to look at the second of the Group 7 rows 
in Table A-6.
•The Op/Reg bits [5,4,3] are 000B. This tells us to look in the 000 column for Group 7.
•Finally, the R/M bits [2,1,0] are 011B. This identifies the opcode as the VMRESUME instruction.
A.4.2  Opcode Extension Tables
See Table A-6 below.mod nnn R/M
Figure A-1.  ModR/M Byte nnn Field (Bits 5, 4, and 3)A-18 Vol. 2DOPCODE MAP
Table A-6.  Opcode Extensions for One- and Two-byte Opcodes by Group Number *
Opcode Group Mod 7,6 pfxEncoding of Bits 5,4,3 of the ModR /M Byte (bits 2,1,0 in parenthesis)
000 001 010 011 100 101 110 111
80-83 1 mem, 11B ADD OR ADC SBB AND SUB XOR CMP
8F 1A mem, 11B POP
C0,C1 reg, imm
D0, D1 reg, 1
D2, D3 reg, CL2mem, 11B ROL ROR RCL RCR SHL/SAL SHR SAR
F6, F7 3mem, 11B TEST 
Ib/IzNOT NEG MUL
AL/rAXIMUL
AL/rAXDIV
AL/rAXIDIV
AL/rAX
FE 4mem, 11B INC
EbDEC
Eb
FF 5mem, 11B INC
EvDEC
Evnear CALLf64
Evfar CALL
Ep near JMPf64
Evfar JMP
MpPUSHd64
Ev
0F 00 6mem, 11B SLDT
Rv/MwSTR
Rv/MwLLDT
EwLTR
Ew VERR
EwVERW
Ew
0F 01 7mem SGDT
MsSIDT
MsLGDT
MsLIDT
Ms SMSW
Mw/RvLMSW
EwINVLPG
Mb
11B VMCALL (001) 
VMLAUNCH 
(010) 
VMRESUME 
(011) VMXOFF 
(100) MONITOR 
(000)
MWAIT (001)
CLAC (010)
STAC (011)
ENCLS (111)XGETBV (000)
XSETBV (001)
VMFUNC 
(100)
XEND (101)
XTEST (110)
ENCLU(111)SWAPGS
o64(000)
RDTSCP (001)
0F BA 8m e m ,  1 1 B BT BTS BTR BTC
0F C7 9memCMPXCH8B Mq
CMPXCHG16B
 MdqVMPTRLD
MqVMPTRST
Mq 
66 VMCLEAR
Mq 
F3 VMXON
Mq 
11BRDRAND
RvRDSEED
Rv
F3 RDPID
Rd/q
0F B9 10mem UD1
11B
C6
11mem MOV
Eb, Ib
11B XABORT (000) Ib
C7mem MOV
Ev, Iz11B XBEGIN (000) Jz
0F 71 12mem
11Bpsrlw
Nq, Ibpsraw
Nq, Ibpsllw
Nq, Ib
66 vpsrlw
Hx,Ux,Ibvpsraw
Hx,Ux,Ibvpsllw
Hx,Ux,Ib
0F 72 13mem
11Bpsrld
Nq, Ibpsrad
Nq, Ibpslld
Nq, Ib
66 vpsrld
Hx,Ux,Ibvpsrad
Hx,Ux,Ibvpslld
Hx,Ux,Ib
0F 73 14mem
11Bpsrlq
Nq, Ibpsllq
Nq, Ib
66 vpsrlq
Hx,Ux,Ibvpsrldq
Hx,Ux,Ibvpsllq
Hx,Ux,Ibvpslldq
Hx,Ux,IbVol. 2D A-19OPCODE MAP
0F AE 15mem fxsave fxrstor ldmxcsr stmxcsr XSAVE XRSTOR XSAVEOPT clflush
11Blfence mfence sfence
F3 RDFSBASE  
RyRDGSBASE 
RyWRFSBASE  
RyWRGSBASE 
Ry
0F 18 16memprefetch
NTAprefetch
T0prefetch
T1prefetch
T2Reserved NOP
11B Reserved NOP
VEX.0F38 F3 17mem BLSRv
By, EyBLSMSKv
By, EyBLSIv
By, Ey11B
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.Table A-6.  Opcode Extensions for One- and Two-byte Opcodes by Group Number * (Contd.)A-20 Vol. 2DOPCODE MAP
A.5 ESCAPE OPCODE INSTRUCTIONS
Opcode maps for coprocessor escape instruction opcodes (x87 floating-point instruction opcodes) are in Table A-7 
through Table A-22. These maps are grouped by the first byte of the opcode, from D8-DF. Each of these opcodes 
has a ModR/M byte. If the ModR/M byte is within the rang e of 00H-BFH, bits 3-5 of the ModR/M byte are used as 
an opcode extension, similar to the technique used for 1-and 2-byte opcodes (see A.4). If the ModR/M byte is 
outside the range of 00H through BFH, the entire ModR/M byte is used as an opcode extension.
A.5.1  Opcode Look-up Examples for Escape Instruction Opcodes
Examples are provided below.
Example A-6.  Opcode with ModR/M Byte in the 00H through BFH Range
DD0504000000H  can be interpreted as follows:
•The instruction encoded with this opcode can be located in Section . Since the ModR/M byte (05H) is within the 
00H through BFH range, bits 3 through 5 (000) of this  byte indicate the opcode for an FLD double-real 
instruction (see Table A-9). 
•The double-real value to be loaded is at 00000004H (the  32-bit displacement that follows and belongs to this 
opcode).
Example A-7.  Opcode with ModR/M By te outside the 00H through BFH Range
D8C1H  can be interpreted as follows:
•This example illustrates an opcode with a ModR/M byte  outside the range of 00H through BFH. The instruction 
can be located in Section A.4. 
•In Table A-8, the ModR/M byte C1H indicates row C, co lumn 1 (the FADD instruction using ST(0), ST(1) as 
operands).
A.5.2  Escape Opcode Instruction Tables
Tables are listed below.
A.5.2.1  Escape Opcodes with D8 as First Byte
Table A-7 and A-8 contain maps for the esca pe instruction opcodes that begin with D8H. Table A-7 shows the map if the ModR/M 
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.
Table A-7.  D8 Opcode Map When Mo dR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte (refer to Figure A.4)
000B 001B 010B 011B 100B 101B 110B 111B
FADD
single-realFMUL
single-realFCOM
single-realFCOMP
single-realFSUB
single-realFSUBR
single-realFDIV
single-realFDIVR
single-real
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.Vol. 2D A-21OPCODE MAP
Table A-8 shows the map if the ModR/M byte is outside the range of 00H-BFH. Here, the first digit of the ModR/M byte selects th e 
table row and the second digit selects the column.
A.5.2.2  Escape Opcodes with D9 as First Byte
Table A-9 and A-10 contain maps for escape instruction opcodes that begin with D9H.  Table A-9 shows the map if the ModR/M 
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction..Table A-8.  D8 Opcode Map When Mo dR/M Byte is Outs ide 00H to BFH *
01234567
CF A D D
ST(0),ST(0) ST(0),ST(1) ST(0),ST (2) ST(0),ST(3) ST(0),ST(4) ST(0),ST(5) ST(0),ST(6) ST(0),ST(7)
DF C O M
ST(0),ST(0) ST(0),ST(1) ST(0),T(2) ST(0),ST(3) ST(0),ST(4) ST(0),ST(5) ST(0),ST(6) ST(0),ST(7)
EF S U B
FF D I V
89 A B C D E F
CF M U L
DF C O M P
EF S U B R
FF D I V R
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.
Table A-9.  D9 Opcode Map When Mo dR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte 
FLD
single-realFST
single-realFSTP
single-realFLDENV
14/28 bytesFLDCW
2 bytesFSTENV
14/28 bytesFSTCW
2 bytes
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.A-22 Vol. 2DOPCODE MAP
Table A-10 shows the map if the ModR/M byte is outside the range of 00H-BFH. Here, the first digit of the ModR/M byte selects t he 
A.5.2.3  Escape Opcodes with DA as First Byte
Table A-11 and A-12 contain maps for escape  instruction opcodes that begin with DAH.  Table A-11 shows the map if the ModR/M 
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.Table A-10.  D9 Opcode Map When Mo dR/M Byte is Outside 00H to BFH *
0 12345 6 7
CF L D
ST(0),ST(0) ST(0),ST(1) ST(0),ST(2) ST(0),ST(3) ST(0),ST(4) ST(0),ST(5) ST(0),ST(6) ST(0),ST(7)
DF N O P
E FCHS FABS FTST FXAM
F F2XM1 FYL2X FPTAN FPATAN FXTRACT FPREM1 FDECSTP FINCSTP
89 A B C D E F
CF X C H
D
E FLD1 FLDL2T FLDL2E FLDPI FLDLG2 FLDLN2 FLDZ

0 12345 6 7
CF L D
DF N O P
89 A B C D E F
CF X C H
D
F FPREM FYL2XP1 FSQRT FSINCOS FRNDINT FSCALE FSIN FCOS
NOTES:
Table A-11.  DA Opcode Map When Mo dR/M Byte is Within 00H to BFH *
FIADD
dword-integerFIMUL
dword-integerFICOM
dword-integerFICOMP
dword-integerFISUB
dword-integerFISUBR
dword-integerFIDIV
dword-integerFIDIVR
dword-integer
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.Vol. 2D A-23OPCODE MAP
Table A-12 shows the map if the ModR/M byte is outside the rang e of 00H-BFH. Here, the first digi t of the ModR/M byte selects 
the table row and the second digit selects the column.
A.5.2.4  Escape Opcodes with DB as First Byte
Table A-13 and A-14 contain maps for escape  instruction opcodes that begin with DBH. Table A-13 shows the map if the ModR/M 
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.Table A-12.  DA Opcode Map When ModR/M Byte is Outside 00H to BFH *
0 12345 67
CF C M O V B
D FCMOVBE
E
F
89 A B C D E F
CF C M O V E
DF C M O V U
E FUCOMPP
F
NOTES:
Table A-13.  DB Opcode Map When Mo dR/M Byte is Within 00H to BFH *
FILD
dword-integerFISTTP 
dword-integerFIST
dword-integerFISTP
dword-integerFLD
extended-realFSTP
extended-real
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.A-24 Vol. 2DOPCODE MAP
Table A-14 shows the map if the ModR/M byte is outside the range of 00H-BFH. Here, the first digit of the ModR/M byte selects t he 
A.5.2.5  Escape Opcodes with DC as First Byte
Table A-15 and A-16 contain maps for escape  instruction opcodes that begin with DCH.  Table A-15 shows the map if the ModR/M 
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.Table A-14.  DB Opcode Map When Mo dR/M Byte is Outside 00H to BFH *
0 12345 6 7
C FCMOVNB
D FCMOVNBE
EF C L E X F I N I T
FF C O M I
89 A B C D EF
C FCMOVNE
DF C M O V N U
E FUCOMI
F
NOTES:
* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locat ions.
Table A-15.  DC Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte (refer to Figure A-1)
FADD 
double-realFMUL 
double-realFCOM 
double-realFCOMP 
double-realFSUB 
double-realFSUBR 
double-realFDIV 
double-realFDIVR 
double-real
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.Vol. 2D A-25OPCODE MAP
Table A-16 shows the map if the ModR/M byte is outside the range of 00H-BFH. In this case the first digit of the ModR/M byte 
selects the table row and the second digit selects the column.
A.5.2.6  Escape Opcodes with DD as First Byte
Table A-17 and A-18 contain maps for escape  instruction opcodes that begin with DDH. Table A-17 sh ows the map if the ModR/M 
byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.Table A-16.  DC Opcode Map When Mo dR/M Byte is Outside 00H to BFH *
0 12345 6 7
CF A D D
ST(0),ST(0) ST(1),ST(0) ST(2),ST(0) ST(3),ST(0) ST(4),ST(0) ST(5),ST(0) ST(6),ST(0) ST(7),ST(0)
D
E FSUBR
FF D I V R
89 A B C D EF
CF M U L
D
EF S U B
FF D I V
NOTES:
Table A-17.  DD Opcode Map When ModR/M Byte is Within 00H to BFH *
nnn Field of ModR/M Byte
FLD 
double-realFISTTP 
integer64FST 
double-realFSTP 
double-realFRSTOR 
98/108bytesFSAVE 
98/108bytesFSTSW 
2 bytes
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.A-26 Vol. 2DOPCODE MAP
Table A-18 shows the map if the ModR/M byte is outside the range of 00H-BFH. The first digit of th e ModR/M byte selects the tab le 
row and the second digit selects the column.
A.5.2.7  Escape Opcodes with DE as First Byte
Table A-19 and A-20 contain opcode maps for escape instruction opcodes that begin with DEH. Table A-19 shows the opcode map 
if the ModR/M byte is in the range of 00H-BFH. In this case, the value of bits 3-5 (the nnn field in Figure A-1) selects the ins truc-
tion.Table A-18.  DD Opcode Map When ModR /M Byte is Outside 00H to BFH *
0 12345 6 7
CF F R E E
ST(0) ST(1) ST(2) ST(3) ST(4) ST(5) ST(6) ST(7)
DF S T
E FUCOM
F
89 A B C D EF
C
DF S T P
EF U C O M P
F
NOTES:
Table A-19.  DE Opcode Map When Mo dR/M Byte is Within 00H to BFH *
FIADD 
word-integerFIMUL 
word-integerFICOM 
word-integerFICOMP 
word-integerFISUB 
word-integerFISUBR 
word-integerFIDIV 
word-integerFIDIVR 
word-integer
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.Vol. 2D A-27OPCODE MAP
Table A-20 shows the opcode map if the ModR/M byte is outside the range of 00H-BFH. The first digit of the ModR/M byte selects 
A.5.2.8  Escape Opcodes with DF As First Byte
Table A-21 and A-22 contain the opcode maps for escape instruction opcodes that begin with DFH. Table A-21 shows the opcode 
map if the ModR/M byte is in the range of 00H-BFH. Here, the valu e of bits 3-5 (the nnn field in  Figure A-1) selects the instruc tion.Table A-20.  DE Opcode Map When ModR/M Byte is Outside 00H to BFH *
0 12345 6 7
C FADDP
D
E FSUBRP
FF D I V R P
89 A B C D EF
CF M U L P
DF C O M P P
E FSUBP
FF D I V P
ST(0),ST(0) ST(1),ST(0) ST(2),ST(0). ST(3),ST(0) ST(4),ST(0) ST(5),ST(0) ST(6),ST(0) ST(7),ST(0)
NOTES:
Table A-21.  DF Opcode Map When Mo dR/M Byte is Within 00H to BFH *
FILD
word-integerFISTTP
word-integerFIST 
word-integerFISTP 
word-integerFBLD 
packed-BCDFILD 
qword-integerFBSTP 
packed-BCDFISTP 
qword-integer
NOTES:

D
E FSUBRP
FF D I V R P
89 A B C D EF
CF M U L P
DF C O M P P
E FSUBP
FF D I V P
NOTES:
FILD
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.A-28 Vol. 2DOPCODE MAP
Table A-22 shows the opcode map if the ModR/M byte is outside th e range of 00H-BFH. The first di git of the ModR/M byte selects 
Table A-22.  DF Opcode Map When Mo dR/M Byte is Ou tside 00H to BFH *
0 12345 6 7
C
D
EF S T S W
AX
FF C O M I P
89 A B C D EF
C
D
EF U C O M I P
F
NOTES:
*All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locati ons.Vol. 2D A-29OPCODE MAP
This page was
intentionally left
blank.A-30 Vol. 2DOPCODE MAPVol. 2D B-1APPENDIX B
INSTRUCTION FORMATS AND ENCODINGS
This appendix provides machine instruction formats and en codings of IA-32 instructions. The first section describes 
the IA-32 architecture’s machine instruction format. The remaining sections show the formats and encoding of general-purpose, MMX, P6 family, SSE/SSE2/SSE3, x87 FP U instructions, and VMX instructions. Those instruction 
formats also apply to Intel 64 architecture. Instruction form ats used in 64-bit mode are provided as supersets of 
the above.
B.1 MACHINE INSTRUCTION FORMAT
All Intel Architecture instructions are encoded using subsets of the general machine instruction format shown in Figure B-1. Each instruction consists of:
•an opcode
•a register and/or address mode specifier consisting of the ModR/M byte and sometimes the scale-index-base 
(SIB) byte (if required) 
•a displacement and an immediate data field (if required) 
The following sections discuss this format.
B.1.1  Legacy Prefixes
The legacy prefixes noted in Figure B-1 include 66H, 67H, F2H, and F3H. They are optional, except when F2H, F3H, 
and 66H are used in instruction extensions. Legacy prefixes must be placed before REX prefixes.
Refer to Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A, for more information on legacy prefixes.Figure B-1.  General Machine Instruction FormatModR/M Byte7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7-6     5-3     2-0 7-6     5-3     2-0T T T T T T T T T T T T T T T T
Mod   Reg*  R/M Scale Index Base d32 | 16 | 8 | None d32 | 16 | 8 | None
SIB ByteAddress Displacement
(4, 2, 1 Bytes or None)Immediate Data
(4,2,1 Bytes or None)
Register and/or Address
Mode SpecifierLegacy Prefixes REX Prefixes7 6 5 4 3 2 1 0
T T T T T T T T
(optional) Grp 1, Grp 2, 
Grp 3, Grp 4 
NOTE:
*  The Reg Field may be used as an 
opcode extension field (TTT) and as a way to  encode diagnostic registers 
(eee).1, 2, or 3 Byte Opcodes (T = Opcode B-2 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.1.2  REX Prefixes
REX prefixes are a set of 16 opcodes that span one row of  the opcode map and occupy entries 40H to 4FH. These 
opcodes represent valid instructions (INC or DEC) in IA-32 operating modes and in compatibility mode. In 64-bit 
mode, the same opcodes represent the instruction prefix  REX and are not treated as individual instructions.
Volume 2A, for more information on REX prefixes.
B.1.3  Opcode Fields
The primary opcode for an instruction is encoded in one to three bytes of the instruction. Within the primary 
opcode, smaller encoding fields may be defined. These fields vary according to the class of operation being 
Almost all instructions that refer to a register and/or memory operand have a register and/or address mode byte 
following the opcode. This byte, the ModR/M byte, consists of  the mod field (2 bits), the reg field (3 bits; this field 
is sometimes an opcode extension), and the R/M field (3 bits ). Certain encodings of the ModR/M byte indicate that 
a second address mode byte, the SIB byte, must be used.
If the addressing mode specifies a displacement, the di splacement value is placed immediately following the 
ModR/M byte or SIB byte. Possible sizes are 8, 16, or 32 bits. If the instruction specifies an immediate value, the 
immediate value follows any displacement bytes. The immediate, if specified, is  always the last field of the instruc-
tion.
Volume 2A, for more information on opcodes.
B.1.4  Special Fields
Table B-1 lists bit fields that appear in certain instructio ns, sometimes within the opcode bytes. All of these fields 
(except the d bit) occur in the general-purpose instruction formats in Table B-13.
Table B-1.  Special Fields Within Instruction Encodings
Field Name DescriptionNumber of 
Bits
reg General-register specifier (see Table B-4 or B-5). 3
w Specifies if data is byte or full-sized, wher e full-sized is 16 or 32  bits (see Table B-6). 1
s Specifies sign extension of an immediate field (see Table B-7). 1
sreg2 Segment register specifier for CS, SS, DS, ES (see Table B-8). 2
sreg3 Segment register specifier for CS , SS, DS, ES, FS, GS (see Table B-8). 3
eee Specifies a special-purpose (control or debug) register (see Table B-9). 3
tttn For conditional instru ctions, specifies a cond ition asserted or nega ted (see Table B-12). 4
d Specifies direction of data operation (see Table B-11). 1Vol. 2D B-3INSTRUCTION FORMATS AND ENCODINGS
B.1.4.1  Reg Field (reg) for Non-64-Bit Modes
The reg field in the ModR/M byte specifies a general-purpos e register operand. The group of registers specified is 
modified by the presence and state of the w bit in an encoding (refer to Section B.1.4.3). Table B-2 shows the 
encoding of the reg field when the w bit is not present in an encoding; Table B-3 shows the encoding of the reg field 
when the w bit is present.
Table B-2.  Encoding of reg Field When w Field is Not Pres ent in Instruction
reg FieldRegister Selected during
16-Bit Data OperationsRegister Selected during
32-Bit Data Operations
000 AX EAX
001 CX ECX010 DX EDX
011 BX EBX
100 SP ESP101 BP EBP110 SI ESI
111 DI EDI
Table B-3.  Encoding of reg Field Wh en w Field is Present in Instruction
Register Specified by reg Field
During 16-Bit Data OperationsRegister Specified by reg Field
During 32-Bit Data Operations
regFunction of w Field
When w = 0 When w = 1 When w = 0 When w = 1
000 AL AX 000 AL EAX001 CL CX 001 CL ECX
010 DL DX 010 DL EDX
011 BL BX 011 BL EBX100 AH SP 100 AH ESP
101 CH BP 101 CH EBP
110 DH SI 110 DH ESI111 BH DI 111 BH EDIB-4 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.1.4.2  Reg Field (reg) for 64-Bit Mode
Just like in non-64-bit modes, the reg field in the ModR/M byte specifies a general-purpose register operand. The 
group of registers specified is modified by the presence of  and state of the w bit in an encoding (refer to Section 
B.1.4.3). Table B-4 shows the encoding of the reg field wh en the w bit is not present in an encoding; Table B-5 
shows the encoding of the reg field when the w bit is present.
B.1.4.3  Encoding of Operand Size (w) Bit 
The current operand-size attribute determines whether the processor is performing 16-bit, 32-bit or 64-bit opera-
tions. Within the constraints of the current operand-size a ttribute, the operand-size bit (w) can be used to indicate 
operations on 8-bit operands or the full operand size specified with the operand-size attribute. Table B-6 shows the 
encoding of the w bit depending on the current operand-size attribute.Table B-4.  Encoding of reg Field When  w Field is Not Pres ent in Instruction
32-Bit Data OperationsRegister Selected during
64-Bit Data Operations
000 AX EAX RAX
001 CX ECX RCX010 DX EDX RDX
011 BX EBX RBX
100 SP ESP RSP101 BP EBP RBP110 SI ESI RSI
111 DI EDI RDI
Table B-5.  Encoding of reg Field When  w Field is Presen t in Instruction 
011 BL BX 011 BL EBX100 AH
1SP 100 AH* ESP
101 CH1BP 101 CH* EBP
110 DH1SI 110 DH* ESI
111 BH1DI 111 BH* EDI
NOTES:
1. AH, CH, DH, BH can not be encoded when REX prefix is used. Such an expression defaults to the low byte.
Table B-6.  Encoding of Operand Size (w) Bit 
w BitOperand Size When 
Operand-Size Attribute is 16 BitsOperand Size When 
Operand-Size Attribute is 32 Bits
0 8 Bits 8 Bits
1 16 Bits 32 BitsVol. 2D B-5INSTRUCTION FORMATS AND ENCODINGS
B.1.4.4  Sign-Extend (s) Bit 
The sign-extend (s) bit occurs in instructions with immediat e data fields that are being extended from 8 bits to 16

NOTES:
The sign-extend (s) bit occurs in instructions with immediat e data fields that are being extended from 8 bits to 16 
or 32 bits. See Table B-7.
B.1.4.5  Segment Register (sreg) Field 
When an instruction operates on a segment register, the reg field in the ModR/M byte is called the sreg field and is used to specify the segment register. Table B-8 shows the encoding of the sreg field. This field is sometimes a 2-bit 
field (sreg2) and other times a 3-bit field (sreg3). 
B.1.4.6  Special-Purpose Register (eee) Field 
When control or debug registers are referenced in an instru ction they are encoded in the eee field, located in bits 5 
though 3 of the ModR/M byte (an alternate encoding of the sreg field). See Table B-9.Table B-7.  Encoding of Sign-Extend (s) Bit 
sEffect on 8-Bit
Immediate DataEffect on 16- or 32-Bit
Immediate Data
0 None None
1 Sign-extend to fill 16-bit or 32-bit destination None
Table B-8.  Encoding of the Segment Register (sreg) Field 
2-Bit sreg2 Field Segment Register Selected 3-Bit sreg3 Field Segment Register Selected
00 ES 000 ES
01 CS 001 CS10 SS 010 SS
11 DS 011 DS
100 FS101 GS
110 Reserved
1
111 Reserved
NOTES:
1. Do not use reserved encodings.
Table B-9.  Encoding of Specia l-Purpose Register (eee) Field  
eee Control Register Debug Register
000 CR0 DR0
001 Reserved1DR1
010 CR2 DR2011 CR3 DR3
100 CR4 Reserved
101 Reserved Reserved110 Reserved DR6
111 Reserved DR7
NOTES:
1. Do not use reserved encodings.B-6 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.1.4.7  Condition Test (tttn) Field 
For conditional instructions (such as conditional jumps and set on condition), the condition test field (tttn) is 
encoded for the condition being tested. The ttt part of the field gives the condition to test and the n part indicates 
whether to use the condition (n =0) or its negation (n =1).
•For 1-byte primary opcodes, the tttn field is locate d in bits 3, 2, 1, and 0 of the opcode byte. 
•For 2-byte primary opcodes, the tttn field is located in  bits 3, 2, 1, and 0 of the second opcode byte.
Table B-10 shows the encoding of the tttn field.
B.1.4.8  Direction (d) Bit 
In many two-operand instructions, a direction bit (d) indi cates which operand is considered the source and which 
is the destination. See Table B-11. 
•When used for integer instructions, the d bit is located at  bit 1 of a 1-byte primary opcode. Note that this bit 
does not appear as the symbol “d” in Table B-13; the actual encoding of the bit as 1 or 0 is given. 
•When used for floating-point instructions (in Table B-16) , the d bit is shown as bit 2 of the first byte of the 
primary opcode.
B.1.5  Other Notes
Table B-12 contains notes on particular encodings. These notes are indicated in the tables shown in the following 
sections by superscripts.Table B-10.  Encoding of Conditional Test (tttn) Field
t t t n Mnemonic Condition
0000 O Overflow0001 NO No overflow0010 B, NAE Below, Not above or equal0011 NB, AE Not below, Above or equal0100 E, Z Equal, Zero0101 NE, NZ Not equal, Not zero0110 BE, NA Below or equal, Not above
0111 NBE, A Not below or equal, Above1000 S Sign1001 NS Not sign1010 P, PE Parity, Parity Even1011 NP, PO Not parity, Parity Odd1100 L, NGE Less than, Not gr eater than or equal to
1101 NL, GE Not less than, Gr eater than or equal to
1110 LE, NG Less than or eq ual to, Not greater than
1111 NLE, G Not less than or  equal to, Greater than
Table B-11.  Encoding of Operation Direction (d) Bit 
d Source Destination
0 reg Field ModR/M or SIB Byte
1 ModR/M or SIB Byte reg FieldVol. 2D B-7INSTRUCTION FORMATS AND ENCODINGS
B.2 GENERAL-PURPOSE INSTRUCTION FORMATS AND ENCODINGS FOR NON-
64-BIT MODES
Table B-13 shows machine instruction formats and encodings for general purpose instructions in non-64-bit 
modes.Table B-12.  Notes on Instruction Encoding
Symbol Note
A A value of 11B in bits 7 and 6 of the ModR/M by te is reserved.
B A value of 01B (or 10B) in bits 7 and 6 of the ModR/M byte is reserved.
Table B-13.  General Purpose Instruction Formats and Encodings for Non-64-Bit Modes
Instruction and Format Encoding
AAA – ASCII Adjust after Addition 0011 0111
AAD – ASCII Adjust AX before Division 1101 0101 : 0000 1010
AAM – ASCII Adjust AX after Multiply 1101 0100 : 0000 1010
AAS – ASCII Adjust AL after Subtraction 0011 1111
ADC – ADD with Carry
register1 to register2 0001 000w : 11 reg1 reg2
register2 to register1 0001 001w : 11 reg1 reg2 
memory to register 0001 001w : mod reg r/mregister to memory 0001 000w : mod reg r/m
immediate to register 1000 00sw : 11 010 reg : immediate data
immediate to AL, AX, or EAX 0001 010w : immediate dataimmediate to memory 1000 00sw : mod 010 r/m : immediate data
ADD – Add
register1 to register2 0000 000w : 11 reg1 reg2register2 to register1 0000 001w : 11 reg1 reg2 
memory to register 0000 001w : mod reg r/m
register to memory 0000 000w : mod reg r/mimmediate to register 1000 00sw : 11 000 reg : immediate data
immediate to AL, AX, or EAX 0000 010w : immediate data
immediate to memory 1000 00sw : mod 000 r/m : immediate data
AND – Logical AND
register1 to register2 0010 000w : 11 reg1 reg2
register2 to register1 0010 001w : 11 reg1 reg2 memory to register 0010 001w : mod reg r/m
register to memory 0010 000w : mod reg r/m
immediate to register 1000 00sw : 11 100 reg : immediate dataimmediate to AL, AX, or EAX 0010 010w : immediate data
immediate to memory 1000 00sw : mod 100 r/m : immediate dataB-8 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
ARPL – Adjust RPL Field of Selector
from register 0110 0011 : 11 reg1 reg2
from memory 0110 0011 : mod reg r/m
BOUND – Check Array Against Bounds 0110 0010 : modA reg r/m
BSF – Bit Scan Forward
register1, register2 0000 1111 : 1011 1100 : 11 reg1 reg2
memory, register 0000 1111 : 1011 1100 : mod reg r/m
BSR – Bit Scan Reverse
register1, register2 0000 1111 : 1011 1101 : 11 reg1 reg2
memory, register 0000 1111 : 1011 1101 : mod reg r/m
BSWAP – Byte Swap 0000 1111 : 1100 1 reg
BT – Bit Test
register, immediate 0000 1111 : 1011 1010 : 11 100 reg: imm8 data
memory, immediate 0000 1111 : 1011 1010 : mod 100 r/m : imm8 dataregister1, register2 0000 1111 : 1010 0011 : 11 reg2 reg1
memory, reg 0000 1111 : 1010 0011 : mod reg r/m
BTC – Bit Test and Complement
register, immediate 0000 1111 : 1011 1010 : 11 111 reg: imm8 data
memory, immediate 0000 1111 : 1011 1010 : mod 111 r/m : imm8 data
register1, register2 0000 1111 : 1011 1011 : 11 reg2 reg1memory, reg 0000 1111 : 1011 1011 : mod reg r/m
BTR – Bit Test and Reset
register, immediate 0000 1111 : 1011 1010 : 11 110 reg: imm8 datamemory, immediate 0000 1111 : 1011 1010 : mod 110 r/m : imm8 data
register1, register2 0000 1111 : 1011 0011 : 11 reg2 reg1
memory, reg 0000 1111 : 1011 0011 : mod reg r/m
BTS – Bit Test and Set
register, immediate 0000 1111 : 1011 1010 : 11 101 reg: imm8 data
memory, immediate 0000 1111 : 1011 1010 : mod 101 r/m : imm8 dataregister1, register2 0000 1111 : 1010 1011 : 11 reg2 reg1
memory, reg 0000 1111 : 1010 1011 : mod reg r/m
CALL – Call Procedure (in same segment)
direct 1110 1000 : full displacement
register indirect 1111 1111 : 11 010 reg
memory indirect 1111 1111 : mod 010 r/m
CALL – Call Procedure (in other segment)
direct 1001 1010 : unsigned full offset, selector
indirect 1111 1111 : mod 011 r/mTable B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingVol. 2D B-9INSTRUCTION FORMATS AND ENCODINGS
CBW – Convert Byte to Word 1001 1000
CDQ – Convert Doubleword to Qword 1001 1001
CLC – Clear Carry Flag 1111 1000
CLD – Clear Direction Flag 1111 1100
CLI – Clear Interrupt Flag 1111 1010
CLTS – Clear Task-Swit ched Flag in CR0 0000 1111 : 0000 0110
CMC – Complement Carry Flag 1111 0101
CMP – Compare Two Operands
register1 with register2 0011 100w : 11 reg1 reg2
register2 with register1 0011 101w : 11 reg1 reg2memory with register 0011 100w : mod reg r/mregister with memory 0011 101w : mod reg r/m
immediate with register 1000 00sw : 11 111 reg : immediate data
immediate with AL, AX, or EAX 0011 110w : immediate dataimmediate with memory 1000 00sw : mod 111 r/m : immediate data
CMPS/CMPSB/CMPSW/CMPSD – Compare String Operands 1010 011w
CMPXCHG – Compare and Exchange 
register1, register2 0000 1111 : 1011 000w : 11 reg2 reg1
memory, register 0000 1111 : 1011 000w : mod reg r/m
CPUID – CPU Identification 0000 1111 : 1010 0010
CWD – Convert Word to Doubleword 1001 1001
CWDE – Convert Word to Doubleword 1001 1000
DAA – Decimal Adjust AL after Addition 0010 0111
DAS – Decimal Adjust AL after Subtraction 0010 1111
DEC – Decrement by 1
register 1111 111w : 11 001 reg
register (alternate encoding) 0100 1 reg
memory 1111 111w : mod 001 r/m
DIV – Unsigned Divide
AL, AX, or EAX by register 1111 011w : 11 110 reg
AL, AX, or EAX by memory 1111 011w : mod 110 r/m
HLT – Halt 1111 0100
IDIV – Signed Divide
AL, AX, or EAX by register 1111 011w : 11 111 regAL, AX, or EAX by memory 1111 011w : mod 111 r/mTable B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingB-10 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
IMUL – Signed Multiply

AL, AX, or EAX with register 1111 011w : 11 101 reg
AL, AX, or EAX with memory 1111 011w : mod 101 reg
register1 with register2 0000 1111 : 1010 1111 : 11 : reg1 reg2register with memory 0000 1111 : 1010 1111 : mod reg r/m
register1 with immediate to register2 0110 10s1 : 11 reg1 reg2 : immediate data
memory with immediate to register 01 10 10s1 : mod reg r/m : immediate data
IN – Input From Port
fixed port 1110 010w : port number
variable port 1110 110w
INC – Increment by 1
reg 1111 111w : 11 000 reg
reg (alternate encoding) 0100 0 reg
memory 1111 111w : mod 000 r/m
INS – Input from DX Port 0110 110w
INT n – Interrupt Type n 1100 1101 : type
INT – Single-Step Interrupt 3 1100 1100
INTO – Interrupt 4 on Overflow 1100 1110
INVD – Invalidate Cache 0000 1111 : 0000 1000
INVLPG – Invalidate TLB Entry 0000 1111 : 0000 0001 : mod 111 r/m
INVPCID – Invalidate Pr ocess-Context Identifier 0110 0110:0000 1111:0011 1000:1000 0010: mod reg r/m
IRET/IRETD – Interrupt Return 1100 1111
Jcc – Jump if Condition is Met
8-bit displacement 0111 tttn  : 8-bit displacement
full displacement 0000 1111 : 1000 tttn : full displacement
JCXZ/JECXZ – Jump on CX/ECX Zero
   Address-size prefix  differentiates JCXZ 
   and JECXZ1110 0011 : 8-bit displacement
JMP – Unconditional Jump (to same segment)
short 1110 1011 : 8-bit displacement
direct 1110 1001 : full displacementregister indirect 1111 1111 : 11 100 reg
memory indirect 1111 1111 : mod 100 r/m
JMP – Unconditional Jump (to other segment)
direct intersegment 1110 1010 : unsigned full offset, selector
indirect intersegment 1111 1111 : mod 101 r/m
LAHF – Load Flags into AHRegister 1001 1111Table B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingVol. 2D B-11INSTRUCTION FORMATS AND ENCODINGS
LAR – Load Access Rights Byte
from register 0000 1111 : 0000 0010 : 11 reg1 reg2
from memory 0000 1111 : 0000 0010 : mod reg r/m
LDS – Load Pointer to DS 1100 0101 : modA,B reg r/m
LEA – Load Effective Address 1000 1101 : modA reg r/m
LEAVE – High Level Procedure Exit 1100 1001
LES – Load Pointer to ES 1100 0100 : modA,B reg r/m
LFS – Load Pointer to FS 0000 1111 : 1011 0100 : modA reg r/m
LGDT – Load Global Descriptor Table Register 0000 1111 : 0000 0001 : modA 010 r/m
LGS – Load Pointer to GS 0000 1111 : 1011 0101 : modA reg r/m
LIDT – Load Interrupt Descriptor Table Register 0000 1111 : 0000 0001 : modA 011 r/m
LLDT – Load Local Descriptor Table Register
LDTR from register 0000 1111 : 0000 0000 : 11 010 reg
LDTR from memory 0000 1111 : 0000 0000 : mod 010 r/m
LMSW – Load Machine Status Word
from register 0000 1111 : 0000 0001 : 11 110 reg
from memory 0000 1111 : 0000 0001 : mod 110 r/m
LOCK – Assert LOCK# Signal Prefix 1111 0000
LODS/LODSB/LODSW/LODSD – Load String Operand 1010 110w
LOOP – Loop Count 1110 0010 : 8-bit displacement
LOOPZ/LOOPE – Loop Count while Zero/Equal 1110 0001 : 8-bit displacement
LOOPNZ/LOOPNE – Loop Count while not Zero/Equal 1110 0000 : 8-bit displacement
LSL – Load Segment Limit
from register 0000 1111 : 0000 0011 : 11 reg1 reg2
from memory 0000 1111 : 0000 0011 : mod reg r/m
LSS – Load Pointer to SS 0000 1111 : 1011 0010 : modA reg r/m
LTR – Load Task Register
from register 0000 1111 : 0000 0000 : 11 011 reg
from memory 0000 1111 : 0000 0000 : mod 011 r/m
MOV – Move Data
register1 to register2 1000 100w : 11 reg1 reg2
register2 to register1 1000 101w : 11 reg1 reg2memory to reg 1000 101w : mod reg r/m
reg to memory 1000 100w : mod reg r/m
immediate to register 1100 011w : 11 000 reg : immediate dataimmediate to register (alternate encoding) 1011 w reg : immediate data
immediate to memory 1100 011w : mod 000 r/m : immediate data
memory to AL, AX, or EAX 1010 000w : full displacementTable B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingB-12 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
AL, AX, or EAX to memory 1010 001w : full displacement
MOV – Move to/from Control Registers
CR0 from register 0000 1111 : 0010 0010 : -- 000 reg
CR2 from register 0000 1111 : 0010 0010 : -- 010regCR3 from register 0000 1111 : 0010 0010 : -- 011 reg
CR4 from register 0000 1111 : 0010 0010 : -- 100 reg
register from CR0-CR4 0000 1111 : 0010 0000 : -- eee reg
MOV – Move to/from Debug Registers
DR0-DR3 from register 0000 1111 : 0010 0011 : -- eee reg
DR4-DR5 from register 0000 1111 : 0010 0011 : -- eee regDR6-DR7 from register 0000 1111 : 0010 0011 : -- eee regregister from DR6-DR7 0000 1111 : 0010 0001 : -- eee reg
register from DR4-DR5 0000 1111 : 0010 0001 : -- eee reg
register from DR0-DR3 0000 1111 : 0010 0001 : -- eee reg
MOV – Move to/from Segment Registers
register to segment register 1000 1110 : 11 sreg3 reg
register to SS 1000 1110 : 11 sreg3 regmemory to segment reg 1000 1110 : mod sreg3 r/m
memory to SS 1000 1110 : mod sreg3 r/m
segment register to register 1000 1100 : 11 sreg3 regsegment register to memory 1000 1100 : mod sreg3 r/m
MOVBE – Move data after swapping bytes
memory to register 0000 1111 : 0011 1000:1111 0000 : mod reg r/mregister to memory 0000 1111 : 0011 1000:1111 0001 : mod reg r/m
MOVS/MOVSB/MOVSW/MOVSD – Move Data from String to 
String1010 010w
MOVSX – Move with Sign-Extend
memory to reg 0000 1111 : 1011 111w : mod reg r/m
MOVZX – Move with Zero-Extend
register2 to register1 0000 1111 : 1011 011w : 11 reg1 reg2
memory to register 0000 1111 : 1011 011w : mod reg r/m
MUL – Unsigned Multiply
AL, AX, or EAX with register 1111 011w : 11 100 reg
AL, AX, or EAX with memory 1111 011w : mod 100 r/m
NEG – Two's Complement Negation
register 1111 011w : 11 011 reg
memory 1111 011w : mod 011 r/m
NOP – No Operation 1001 0000Table B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingVol. 2D B-13INSTRUCTION FORMATS AND ENCODINGS
NOP – Multi-byte No Operation1
register 0000 1111 0001 1111 : 11 000 reg
memory 0000 1111 0001 1111 : mod 000 r/m
NOT – One's Complement Negation
register 1111 011w : 11 010 reg
memory 1111 011w : mod 010 r/m
OR – Logical Inclusive OR
register1 to register2 0000 100w : 11 reg1 reg2
register2 to register1 0000 101w : 11 reg1 reg2 
memory to register 0000 101w : mod reg r/mregister to memory 0000 100w : mod reg r/mimmediate to register 1000 00sw : 11 001 reg : immediate data
immediate to AL, AX, or EAX 0000 110w : immediate data
immediate to memory 1000 00sw : mod 001 r/m : immediate data
OUT – Output to Port
fixed port 1110 011w : port number
variable port 1110 111w
OUTS – Output to DX Port 0110 111w
POP – Pop a Word from the Stack
register 1000 1111 : 11 000 regregister (alternate encoding) 0101 1 reg
memory 1000 1111 : mod 000 r/m
POP – Pop a Segment Regi ster from the Stack (Note: CS cannot be sreg2 in this usage.)
segment register  DS, ES 000 sreg2 111
segment register  SS 000 sreg2 111
segment register  FS, GS 0000 1111: 10 sreg3 001
POPA/POPAD – Pop All General Registers 0110 0001
POPF/POPFD – Pop Stack into FLAGS or EFLAGS Register 1001 1101
PUSH – Push Operand onto the Stack
register 1111 1111 : 11 110 reg
register (alternate encoding) 0101 0 reg
memory 1111 1111 : mod 110 r/mimmediate 0110 10s0 : immediate data
PUSH – Push Segment Register onto the Stack
segment register CS,D S,ES,SS 000 sreg2 110
segment register FS,GS 0000 1111: 10 sreg3 000
PUSHA/PUSHAD – Push All General Registers 0110 0000Table B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingB-14 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
PUSHF/PUSHFD – Push Flags Register onto the Stack 1001 1100
RCL – Rotate thru Carry Left
register by 1 1101 000w : 11 010 reg
memory by 1 1101 000w : mod 010 r/mregister by CL 1101 001w : 11 010 reg
memory by CL 1101 001w : mod 010 r/m
register by immediate count 1100 000w : 11 010 reg : imm8 datamemory by immediate count 1100 000w : mod 010 r/m : imm8 data
RCR – Rotate thru Carry Right
register by 1 1101 000w : 11 011 regmemory by 1 1101 000w : mod 011 r/mregister by CL 1101 001w : 11 011 reg
memory by CL 1101 001w : mod 011 r/m
register by immediate count 1100 000w : 11 011 reg : imm8 datamemory by immediate count 1100 000w : mod 011 r/m : imm8 data
RDMSR – Read from Model-Specific Register 0000 1111 : 0011 0010
RDPMC – Read Performance Monitoring Counters 0000 1111 : 0011 0011
RDTSC – Read Time-Stamp Counter 0000 1111 : 0011 0001
RDTSCP – Read Time-Stamp  Counter and Processor ID 0000 1111 : 0000 0001: 1111 1001
REP INS – Input String 1111 0011 : 0110 110w
REP LODS – Load String 1111 0011 : 1010 110w
REP MOVS – Move String 1111 0011 : 1010 010w
REP OUTS – Output String 1111 0011 : 0110 111w
REP STOS – Store String 1111 0011 : 1010 101w
REPE CMPS – Compare String 1111 0011 : 1010 011w
REPE SCAS – Scan String 1111 0011 : 1010 111w
REPNE CMPS – Compare String 1111 0010 : 1010 011w
REPNE SCAS – Scan String 1111 0010 : 1010 111w
RET – Return from Procedure (to same segment)
no argument 1100 0011
adding immediate to SP 1100 0010 : 16-bit displacement

RET – Return from Proc edure (to other segment)
intersegment 1100 1011
adding immediate to SP 1100 1010 : 16-bit displacementTable B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingVol. 2D B-15INSTRUCTION FORMATS AND ENCODINGS
ROL – Rotate Left
register by 1 1101 000w : 11 000 reg
memory by 1 1101 000w : mod 000 r/m
register by CL 1101 001w : 11 000 regmemory by CL 1101 001w : mod 000 r/m
register by immediate count 1100 000w : 11 000 reg : imm8 data
memory by immediate count 1100 000w : mod 000 r/m : imm8 data
ROR – Rotate Right
register by 1 1101 000w : 11 001 reg
memory by 1 1101 000w : mod 001 r/mregister by CL 1101 001w : 11 001 regmemory by CL 1101 001w : mod 001 r/m
register by immediate count 1100 000w : 11 001 reg : imm8 data
memory by immediate count 1100 000w : mod 001 r/m : imm8 data
RSM – Resume from System Management Mode 0000 1111 : 1010 1010
SAHF – Store AH into Flags 1001 1110
SAL – Shift Arithmetic Left same instruction as SHL
SAR – Shift Arithmetic Right
register by 1 1101 000w : 11 111 reg
memory by 1 1101 000w : mod 111 r/mregister by CL 1101 001w : 11 111 reg
memory by CL 1101 001w : mod 111 r/m
register by immediate count 1100 000w : 11 111 reg : imm8 datamemory by immediate count 1100 000w : mod 111 r/m : imm8 data
SBB – Integer Subtraction with Borrow
register1 to register2 0001 100w : 11 reg1 reg2register2 to register1 0001 101w : 11 reg1 reg2 
memory to register 0001 101w : mod reg r/m
register to memory 0001 100w : mod reg r/mimmediate to register 1000 00sw : 11 011 reg : immediate data
immediate to AL, AX, or EAX 0001 110w : immediate data
immediate to memory 1000 00sw : mod 011 r/m : immediate data
SCAS/SCASB/SCASW/SCASD – Scan String 1010 111w
SETcc – Byte Set on Condition
register 0000 1111 : 100 1 tttn : 11 000 reg
memory 0000 1111 : 1001 tttn : mod 000 r/m
SGDT – Store Global Descriptor Table Register 0000 1111 : 0000 0001 : mod
A 000 r/mTable B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingB-16 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
SHL – Shift Left
register by 1 1101 000w : 11 100 reg
memory by 1 1101 000w : mod 100 r/m
register by CL 1101 001w : 11 100 regmemory by CL 1101 001w : mod 100 r/m
register by immediate count 1100 000w : 11 100 reg : imm8 data
memory by immediate count 1100 000w : mod 100 r/m : imm8 data
SHLD – Double Precision Shift Left
register by immediate count 0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8
memory by immediate count 0000 1111 : 1010 0100 : mod reg r/m : imm8register by CL 0000 1111 : 1010 0101 : 11 reg2 reg1memory by CL 0000 1111 : 1010 0101 : mod reg r/m
SHR – Shift Right
register by 1 1101 000w : 11 101 regmemory by 1 1101 000w : mod 101 r/m
register by CL 1101 001w : 11 101 reg
memory by CL 1101 001w : mod 101 r/mregister by immediate count 1100 000w : 11 101 reg : imm8 data
memory by immediate count 1100 000w : mod 101 r/m : imm8 data
SHRD – Double Precision Shift Right
register by immediate count 0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8
memory by immediate count 0000 1111 : 1010 1100 : mod reg r/m : imm8
register by CL 0000 1111 : 1010 1101 : 11 reg2 reg1memory by CL 0000 1111 : 1010 1101 : mod reg r/m
SIDT – Store Interrupt Descriptor Table Register 0000 1111 : 0000 0001 : mod
A 001 r/m
SLDT – Store Local Descriptor Table Register
to register 0000 1111 : 0000 0000 : 11 000 reg
to memory 0000 1111 : 0000 0000 : mod 000 r/m
SMSW – Store Machine Status Word
to register 0000 1111 : 0000 0001 : 11 100 reg
to memory 0000 1111 : 0000 0001 : mod 100 r/m
STC – Set Carry Flag 1111 1001
STD – Set Direction Flag 1111 1101
STI – Set Interrupt Flag 1111 1011
STOS/STOSB/STOSW/STOSD – Store String Data 1010 101w
STR – Store Task Register
to register 0000 1111 : 0000 0000 : 11 001 reg
to memory 0000 1111 : 0000 0000 : mod 001 r/mTable B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingVol. 2D B-17INSTRUCTION FORMATS AND ENCODINGS
SUB – Integer Subtraction
register1 to register2 0010 100w : 11 reg1 reg2
register2 to register1 0010 101w : 11 reg1 reg2 
memory to register 0010 101w : mod reg r/mregister to memory 0010 100w : mod reg r/m
immediate to register 1000 00sw : 11 101 reg : immediate data
immediate to AL, AX, or EAX 0010 110w : immediate dataimmediate to memory 1000 00sw : mod 101 r/m : immediate data
TEST – Logical Compare
register1 and register2 1000 010w : 11 reg1 reg2memory and register 1000 010w : mod reg r/mimmediate and register 1111 011w : 11 000 reg : immediate data
immediate and AL, AX, or EAX 1010 100w : immediate data
immediate and memory 1111 011w : mod 000 r/m : immediate data
UD0 – Undefined instruction 0000 1111 : 1111 1111
UD1 – Undefined instruction 0000 1111 : 0000 1011
UD2 – Undefined instruction 0000 FFFF : 0000 1011
VERR – Verify a Segment for Reading 
register 0000 1111 : 0000 0000 : 11 100 reg
memory 0000 1111 : 0000 0000 : mod 100 r/m
VERW – Verify a Segment for Writing
register 0000 1111 : 0000 0000 : 11 101 reg
memory 0000 1111 : 0000 0000 : mod 101 r/m
WAIT – Wait 1001 1011
WBINVD – Writeback and Invalidate Data Cache 0000 1111 : 0000 1001
WRMSR – Write to Model-Specific Register 0000 1111 : 0011 0000
XADD – Exchange and Add
register1, register2 0000 1111 : 1100 000w : 11 reg2 reg1
memory, reg 0000 1111 : 1100 000w : mod reg r/m
XCHG – Exchange Regist er/Memory with Register
register1 with register2 1000 011w : 11 reg1 reg2
AX or EAX with reg 1001 0 regmemory with reg 1000 011w : mod reg r/m
XLAT/XLATB – Table Look-up Translation 1101 0111
XOR – Logical Exclusive OR
register1 to register2 0011 000w : 11 reg1 reg2
register2 to register1 0011 001w : 11 reg1 reg2 
memory to register 0011 001w : mod reg r/mTable B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingB-18 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.2.1  General Purpose Instruction Formats and Encodings for 64-Bit Mode
Table B-15 shows machine instruction formats and encodings for general purpose instructions in 64-bit mode.register to memory 0011 000w : mod reg r/m
immediate to register 1000 00sw : 11 110 reg : immediate data
immediate to AL, AX, or EAX 0011 010w : immediate data
immediate to memory 1000 00sw : mod 110 r/m : immediate data
Prefix Bytes
address size 0110 0111
LOCK 1111 0000operand size 0110 0110
CS segment override 0010 1110
DS segment override 0011 1110ES segment override 0010 0110FS segment override 0110 0100
GS segment override 0110 0101
SS segment override 0011 0110
NOTES:
1. The multi-byte NOP instruction does not alter the content of the register and will not issue a memory operation. 
Table B-14.  Special Symbols
Symbol Application
S If the value of REX.W. is 1, it  overrides the presence of 66H.
w The value of bit W. in REX is has no effect.
Table B-15.  General Purpos e Instruction Formats and Encodings for 64-Bit Mode
register1 to register2 0100 0R0B : 0001 000w : 11 reg1 reg2
qwordregister1 to qwordregister2 0100 1R0B  : 0001 0001 : 11 qwordreg1 qwordreg2
register2 to register1 0100 0R0B : 0001 001w : 11 reg1 reg2 qwordregister1 to qwordregister2 0100 1R0B  : 0001 0011 : 11 qwordreg1 qwordreg2 
memory to register 0100 0RXB : 0001 001w : mod reg r/m
memory to qwordregister 0100 1RXB : 0001 0011 : mod qwordreg r/mregister to memory 0100 0RXB : 0001 000w : mod reg r/m
qwordregister to memory 0100 1RXB : 0001 0001 : mod qwordreg r/m
immediate to register 0100 000B : 1000 00sw : 11 010 reg : immediateimmediate to qwordregister 0100 100B : 1000 0001 : 11 010 qwordreg : imm32
immediate to qwordregister 0100 1R0B : 1000 0011 : 11 010 qwordreg : imm8Table B-13.  General Purpose Instruction Format s and Encodings for Non-64-Bit Modes (Contd.)
Instruction and Format EncodingVol. 2D B-19INSTRUCTION FORMATS AND ENCODINGS
immediate to AL, AX, or EAX 0001 010w : immediate data
immediate to RAX 0100 1000 : 0000 0101 : imm32
immediate to memory 0100 00XB : 1000 00sw : mod 010 r/m : immediate 
immediate32 to memory64 0100 10XB : 1000 0001 : mod 010 r/m : imm32immediate8 to memory64 0100 10XB : 1000 0031 : mod 010 r/m : imm8
ADD – Add
register1 to register2 0100 0R0B : 0000 000w : 11 reg1 reg2qwordregister1 to qwordregister2 0100 1R0B 0000 0000 : 11 qwordreg1 qwordreg2
register2 to register1 0100 0R0B : 0000 001w : 11 reg1 reg2 
qwordregister1 to qwordregister2 0100 1R0B 0000 0010 : 11 qwordreg1 qwordreg2memory to register 0100 0RXB : 0000 001w : mod reg r/mmemory64 to qwordregister 0100 1RXB  : 0000 0000 : mod qwordreg r/m
register to memory 0100 0RXB : 0000 000w : mod reg r/m
qwordregister to memory64 0100 1RXB : 0000 0011 : mod qwordreg r/mimmediate to register 0100 0000B : 1000 00sw : 11 000 reg : immediate data
immediate32 to qwordregister 0100 100B : 1000 0001 : 11 010 qwordreg : imm

ADD – Add
immediate to AL, AX, or EAX 0000 010w : immediate8immediate to RAX 0100 1000 : 0000 0101 : imm32
immediate to memory 0100 00XB : 1000 00sw : mod 000 r/m : immediate
immediate32 to memory64 0100 10XB : 1000 0001 : mod 010 r/m : imm32immediate8 to memory64 0100 10XB : 1000 0011 : mod 010 r/m : imm8
register1 to register2 0100 0R0B 0010 000w : 11 reg1 reg2qwordregister1 to qwordregister2 0100 1R0B 0010 0001 : 11 qwordreg1 qwordreg2
register2 to register1 0100 0R0B 0010 001w : 11 reg1 reg2 
register1 to register2 0100 1R0B 0010 0011 : 11 qwordreg1 qwordreg2memory to register 0100 0RXB 0010 001w : mod reg r/m
memory64 to qwordregister 0100 1RXB  : 0010 0011 : mod qwordreg r/m
register to memory 0100 0RXB : 0010 000w : mod reg r/mqwordregister to memory64 0100 1RXB : 0010 0001 : mod qwordreg r/m
immediate to register 0100 000B : 1000 00sw : 11 100 reg : immediate 
immediate32 to qwordregister 0100 100B 1000 0001 : 11 100 qwordreg : imm32immediate to AL, AX, or EAX 0010 010w : immediate
immediate32 to RAX 0100 1000 0010 1001 : imm32
immediate to memory 0100 00XB : 1000 00sw : mod 100 r/m : immediate immediate32 to memory64 0100 10XB : 1000 0001 : mod 100 r/m : immediate32
immediate8 to memory64 0100 10XB : 1000 0011 : mod 100 r/m : imm8
BSF – Bit Scan ForwardTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-20 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
register1, register2 0100 0R0B 0000 1111 : 1011 1100 : 11 reg1 reg2
qwordregister1, qwordregister2 0100 1R0B 0000 1111 : 1011 1100 : 11 qwordreg1 
qwordreg2
memory, register 0100 0RXB 0000 1111 : 1011 1100 : mod reg r/m
memory64, qwordregister 0100 1RXB 0000  1111 : 1011 1100 : mod qwordreg r/m
register1, register2 0100 0R0B 0000 1111 : 1011 1101 : 11 reg1 reg2
qwordregister1, qwordregister2 0100 1R0B 0000 1111 : 1011 1101 : 11 qwordreg1 
qwordreg2
memory, register 0100 0RXB 0000 1111 : 1011 1101 : mod reg r/m
memory64, qwordregister 0100 1RXB 0000  1111 : 1011 1101 : mod qwordreg r/m
BSWAP – Byte Swap 0100 100B 0000 1111 : 1100 1 qwordreg
register, immediate 0100 000B 0000 1111 : 1011 1010 : 11 100 reg: imm8 qwordregister, immediate8 0100 100B 1111 : 1011 1010 : 11 100 qwordreg: imm8 data
memory, immediate 0100 00XB 0000 1111 : 1011 1010 : mod 100 r/m : imm8 
memory64, immediate8 0100 10XB 0000 1111 : 1011 1010 : mod 100 r/m : imm8 dataregister1, register2 0100 0R0B 0000 1111 : 1010 0011 : 11 reg2 reg1
qwordregister1, qwordregister2 0100 1R0B 0000 1111 : 1010 0011 : 11 qwordreg2 
qwordreg1
memory, reg 0100 0RXB 0000 1111 : 1010 0011 : mod reg r/m
memory, qwordreg 0100 1RXB 0000 1111 : 1010 0011 : mod qwordreg r/m
register, immediate 0100 000B 0000 1111 : 1011 1010 : 11 111 reg: imm8 
qwordregister, immediate8 0100 100B 0000 1111 : 1011 1010 : 11 111 qwordreg: imm8 memory, immediate 0100 00XB 0000 1111 : 1011 1010 : mod 111 r/m : imm8 
memory64, immediate8 0100 10XB 0000 1111 : 1011 1010 : mod 111 r/m : imm8 
register1, register2 0100 0R0B 0000 1111 : 1011 1011 : 11 reg2 reg1qwordregister1, qwordregister2 0100 1R0B 0000 1111 : 1011 1011 : 11 qwordreg2 
qwordreg1
memory, register 0100 0RXB 0000 1111 : 1011 1011 : mod reg r/m
memory, qwordreg 0100 1RXB 0000 1111 : 1011 1011 : mod qwordreg r/m
register, immediate 0100 000B 0000 1111 : 1011 1010 : 11 110 reg: imm8 
qwordregister, immediate8 0100 100B 0000 1111 : 1011 1010 : 11 110 qwordreg: imm8 
memory, immediate 0100 00XB 0000 1111 : 1011 1010 : mod 110 r/m : imm8 memory64, immediate8 0100 10XB 0000 1111 : 1011 1010 : mod 110 r/m : imm8 
register1, register2 0100 0R0B 0000 1111 : 1011 0011 : 11 reg2 reg1Table B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-21INSTRUCTION FORMATS AND ENCODINGS
qwordregister1, qwordregister2 0100 1R0B 0000 1111 : 1011 0011 : 11 qwordreg2 
qwordreg1
memory, register 0100 0RXB 0000 1111 : 1011 0011 : mod reg r/mmemory64, qwordreg 0100 1RXB 0000 11 11 : 1011 0011 : mod qwordreg r/m
register, immediate 0100 000B 0000 1111 : 1011 1010 : 11 101 reg: imm8qwordregister, immediate8 0100 100B 0000 1111 : 1011 1010 : 11 101 qwordreg: imm8 
memory, immediate 0100 00XB 0000 1111 : 1011 1010 : mod 101 r/m : imm8
memory64, immediate8 0100 10XB 0000 1111 : 1011 1010 : mod 101 r/m : imm8 register1, register2 010 0 0R0B 0000 1111 : 1010 1011 : 11 reg2 reg1
qwordregister1, qwordregister2 0100 1R0B 0000 1111 : 1010 1011 : 11 qwordreg2 
qwordreg1
memory, register 0100 0RXB 0000 1111 : 1010 1011 : mod reg r/m
memory64, qwordreg 0100 1RXB 0000 11 11 : 1010 1011 : mod qwordreg r/m
direct 1110 1000 : displacement32
 register indirect 0100 WR00
w 1111 1111 : 11 010 reg
memory indirect 0100 W0XBw 1111 1111 : mod 010 r/m
indirect 1111 1111 : mod 011 r/m
indirect 0100 10XB 0100 1000 1111 1111 : mod 011 r/m
CDQ – Convert Doubleword to Qword+ 1001 1001
CDQE – RAX, Sign-Extend of EAX 0100 1000 1001 1001CLC – Clear Carry Flag 1111 1000
register1 with register2 0100 0R0B 0011 100w : 11 reg1 reg2
qwordregister1 with qwordregister2 0100 1R0B 0011 1001 : 11 qwordreg1 qwordreg2
register2 with register1 0100 0R0B 0011 101w : 11 reg1 reg2qwordregister2 with qwordregister1 0100 1R0B 0011 101w : 11 qwordreg1 qwordreg2
memory with register 0100 0RXB 0011 100w : mod reg r/m
memory64 with qwordregister 0100 1RXB 0011 1001 : mod qwordreg r/mregister with memory 0100 0RXB 0011 101w : mod reg r/m
qwordregister with memory64 0100 1RXB 0011 101w1 : mod qwordreg r/m
immediate with register 0100 000B 1000 00sw : 11 111 reg : immTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-22 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
immediate32 with qwordregister 0100 100B 1000 0001 : 11 111 qwordreg : imm64
immediate with AL, AX, or EAX 0011 110w : imm
immediate32 with RAX 0100 1000 0011 1101 : imm32
immediate with memory 0100 00XB 1000 00sw : mod 111 r/m : immimmediate32 with memory64 0100 1RXB 1000 0001 : mod 111 r/m : imm64
immediate8 with memory64 0100 1RXB 1000 0011 : mod 111 r/m : imm8
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ – Compare String Operands
compare string operands [ X at DS:(E)SI with Y at ES:(E)DI ] 1010 011w
qword at address RSI with qword at address RDI 0100 1000 1010 0111
register1, register2 0000 1111 : 1011 000w : 11 reg2 reg1byteregister1, byteregister2 0100 000B 0000 1111 : 1011 0000 : 11 bytereg2 reg1
qwordregister1, qwordregister2 0100 100B 0000 1111 : 1011 0001 : 11 qwordreg2 reg1
memory, register 0000 1111 : 1011 000w : mod reg r/mmemory8, byteregister 0100 00XB 0000 1111 : 1011 0000 : mod bytereg r/m
memory64, qwordregister 0100 10XB 0000 1111 : 1011 0001 : mod qwordreg r/m
CQO – Sign-Extend RAX 0100 1000 1001 1001
register 0100 000B 1111 111w : 11 001 reg
qwordregister 0100 100B 1111 1111 : 11 001 qwordregmemory 0100 00XB 1111 111w : mod 001 r/m
memory64 0100 10XB 1111 1111 : mod 001 r/m
AL, AX, or EAX by register 0100 000B 1111 011w : 11 110 reg
Divide RDX:RAX by qwordregister 0100 100B 1111 0111 : 11 110 qwordreg
AL, AX, or EAX by memory 0100 00XB 1111 011w : mod 110 r/mDivide RDX:RAX by memory64 0100 10XB 1111 0111 : mod 110 r/m
ENTER – Make Stack Frame for High Level Procedure 1100 1000 : 16-bit displacement : 8-bit level (L)
AL, AX, or EAX by register 0100 000B 1111 011w : 11 111 reg
RDX:RAX by qwordregister 0100 10 0B 1111 0111 : 11 111 qwordreg
AL, AX, or EAX by memory 0100 00XB 1111 011w : mod 111 r/m
RDX:RAX by memory64 0100 10XB 1111 0111 : mod 111 r/m
IMUL – Signed MultiplyTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-23INSTRUCTION FORMATS AND ENCODINGS
AL, AX, or EAX with register 0100 000B 1111 011w : 11 101 reg
RDX:RAX := RAX with qwordregister 0100 100B 1111 0111 : 11 101 qwordreg
AL, AX, or EAX with memory 0100 00XB 1111 011w : mod 101 r/m
RDX:RAX := RAX with memory64 0100 10XB 1111 0111 : mod 101 r/mregister1 with register2 0000 1111 : 1010 1111 : 11 : reg1 reg2
qwordregister1 := qwordregister1 with qwordregister2 0100 1R0B 0000 1111 : 1010 1111 : 11 : qwordreg1 
qwordreg2
register with memory 0100 0RXB 0000 1111 : 1010 1111 : mod reg r/m

qwordreg2
qwordregister := qwordregister with memory64 0100 1RXB 0000 1111 : 1010 1111 : mod qwordreg r/m
register1 with immediate to register2 0100 0R0B 0110 10s1 : 11 reg1 reg2 : immqwordregister1 := qwordregister2 with sign-extended 
immediate80100 1R0B 0110 1011 : 11 qwordreg1 qwordreg2 : imm8
qwordregister1 := qwordregister2 with immediate32 0100 1R0B 0110 1001 : 11 qwordreg1 qwordreg2 : imm32
memory with immediate to register 0100 0RXB 0110 10s1 : mod reg r/m : imm
qwordregister := memory64 with sign-extended immedi ate8 0100 1RXB 0110 1011 : mod qwordreg r/m : imm8
qwordregister := memory64 with immediate32 0100 1RXB 0110 1001 : mod qwordreg r/m : imm32
fixed port 1110 010w : port numbervariable port 1110 110w
reg 0100 000B 1111 111w : 11 000 regqwordreg 0100 100B 1111 1111 : 11 000 qwordreg
memory 0100 00XB 1111 111w : mod 000 r/m
memory64 0100 10XB 1111 1111 : mod 000 r/m
INVPCID – Invalidate Process-Context Identifier 0110 0110:0000 1111:0011 1000:1000 0010: mod reg r/m
IRETO – Interrupt Return 1100 1111
displacements (excluding 16-bit relative offsets) 0000 1111 : 1000 tttn : displacement32 
Address-size prefix differentiates JCXZ and JECXZ 1110 0011 : 8-bit displacement
short 1110 1011 : 8-bit displacementTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-24 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
direct 1110 1001 : displacement32
register indirect 0100 W00Bw : 1111 1111 : 11 100 reg
memory indirect 0100 W0XBw : 1111 1111 : mod 100 r/m
indirect intersegment 0100 00XB : 1111 1111 : mod 101 r/m
64-bit indirect intersegment 0100 10XB : 1111 1111 : mod 101 r/m
from register 0100 0R0B : 0000 1111 : 0000 0010 : 11 reg1 reg2from dwordregister to qwordregister, masked by 00FxFF00H 0100 WR0B : 0000 1111 : 0000 0010 : 11 qwordreg1 
dwordreg2
from memory 0100 0RXB : 0000 1111 : 0000 0010 : mod reg r/mfrom memory32 to qwordregister, masked by 00FxFF00H 0100 WRXB 0000 1111 : 0000 0010 : mod r/m
LEA – Load Effective Address
in wordregister/dwordregister 0100 0RXB : 1000 1101 : mod
A reg r/m
in qwordregister 0100 1RXB : 1000 1101 : modA qwordreg r/m
LFS – Load Pointer to FS
FS:r16/r32 with far pointer from memory 0100 0RXB : 0000 1111 : 1011 0100 : modA reg r/m
FS:r64 with far pointer from memory 0100 1RXB : 0000 1111 : 1011 0100 : modA qwordreg r/m
LGDT – Load Global Descriptor Table Register 0100 10XB : 0000 1111 : 0000 0001 : modA 010 r/m
LGS – Load Pointer to GS
GS:r16/r32 with far pointer from memory 0100 0RXB : 0000 1111 : 1011 0101 : modA reg r/m
GS:r64 with far pointer from memory 0100 1RXB : 0000 1111 : 1011 0101 : modA qwordreg r/m
LIDT – Load Interrupt Descriptor Table Register 0100 10XB : 0000 1111 : 0000 0001 : modA 011 r/m
LDTR from register 0100 000B : 0000 1111 : 0000 0000 : 11 010 reg
LDTR from memory 0100 00XB :0000 1111 : 0000 0000 : mod 010 r/m
from register 0100 000B : 0000 1111 : 0000 0001 : 11 110 regfrom memory 0100 00XB :0000 1111 : 0000 0001 : mod 110 r/m
LODS/LODSB/LODSW/LODSD/LODSQ – Load String Operand
at DS:(E)SI to AL/EAX/EAX 1010 110w
at (R)SI to RAX 0100 1000 1010 1101
LOOP – Loop Count
if count ≠ 0, 8-bit displacement 1110 0010 
if count ≠ 0, RIP + 8-bit displacement sign-extended to 64-bits 0100 1000 1110 0010 
LOOPE – Loop Count while Zero/EqualTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-25INSTRUCTION FORMATS AND ENCODINGS
if count ≠ 0 & ZF =1, 8-bit displacement 1110 0001 
if count ≠ 0 & ZF = 1, RIP + 8-bit displacement sign-extended to 
64-bits0100 1000 1110 0001 
LOOPNE/LOOPNZ – Loop Count while not Zero/Equal
if count ≠ 0 & ZF = 0, 8-bit displacement 1110 0000 
if count ≠ 0 & ZF = 0, RIP + 8-bit displacement sign-extended to 
64-bits0100 1000 1110 0000 
from qwordregister 0100 1R00 0000 1111 : 0000 0011 : 11 qwordreg1 reg2
from memory16 0000 1111 : 0000 0011 : mod reg r/m
from memory64 0100 1RXB 0000 1111 : 0000 0011 : mod qwordreg r/m
LSS – Load Pointer to SS
SS:r16/r32 with far pointer from memory 0100 0RXB : 0000 1111 : 1011 0010 : modA reg r/m
SS:r64 with far pointer from memory 0100 1WXB : 0000 1111 : 1011 0010 : modA qwordreg r/m
from register 0100 0R00 : 0000 1111 : 0000 0000 : 11 011 reg
from memory 0100 00XB : 0000 1111 : 0000 0000 : mod 011 r/m
register1 to register2 0100 0R0B : 1000 100w : 11 reg1 reg2
qwordregister1 to qwordregister2 0100 1R0B 1000 1001 : 11 qwordeg1 qwordreg2register2 to register1 0100 0R0B : 1000 101w : 11 reg1 reg2
qwordregister2 to qwordregister1 0100 1R0B 1000 1011 : 11 qwordreg1 qwordreg2
memory to reg 0100 0RXB : 1000 101w : mod reg r/mmemory64 to qwordregister 0100 1RXB 1000 1011 : mod qwordreg r/m
reg to memory 0100 0RXB : 1000 100w : mod reg r/m
qwordregister to memory64 0100 1RXB 1000 1001 : mod qwordreg r/mimmediate to register 0100 000B : 1100 011w : 11 000 reg : imm
immediate32 to qwordregister (zero extend) 010 0 100B 1100 0111 : 11 000 qwordreg : imm32
immediate to register (alternate encoding) 0100 000B : 1011 w reg : immimmediate64 to qwordregister (alternate encoding) 0100 100B 1011 1000 reg : imm64
immediate to memory 0100 00XB : 1100 011w : mod 000 r/m : imm
immediate32 to memory64 (zero extend) 0100 10XB 1100 0111 : mod 000 r/m : imm32memory to AL, AX, or EAX 0100 0000 : 1010 000w : displacement
memory64 to RAX 0100 1000 1010 0001 : displacement64
AL, AX, or EAX to memory 0100 0000 : 1010 001w : displacementRAX to memory64 0100 1000 1010 0011 : displacement64
CR0-CR4 from register 0100 0R0B : 0000 1111 : 0010 0010 : 11 eee reg (eee = CR#)Table B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-26 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
CRx from qwordregister 0100 1R0B : 0000 1111 : 0010 0010 : 11 eee qwordreg (Reee 
= CR#)
register from CR0-CR4 0100 0R0B : 0000 1111 : 0010 0000 : 11 eee reg (eee = CR#)qwordregister from CRx 0100 1R0B 0000 1111 : 0010 0000 : 11 eee qwordreg 
(Reee = CR#)
DR0-DR7 from register 0000 1111 : 0010 0011 : 11 eee reg (eee = DR#)
DR0-DR7 from quadregister 0100 10OB 0000 1111 : 0010 0011 : 11 eee reg (eee = DR#)register from DR0-DR7 0000 1111 : 0010 0001 : 11 eee reg (eee = DR#)
quadregister from DR0-DR7 0100 10OB 0000 1111 : 0010 0001 : 11 eee quadreg (eee = 
DR#)
register to segment register 0100 W00B
w : 1000 1110 : 11 sreg reg
register to SS 0100 000B : 1000 1110 : 11 sreg regmemory to segment register 0100 00XB : 1000 1110 : mod sreg r/m
memory64 to segment register (lower 16 bits) 0100 10XB 1000 1110 : mod sreg r/m
memory to SS 0100 00XB : 1000 1110 : mod sreg r/msegment register to register 0100 000B : 1000 1100 : 11 sreg reg
segment register to qwordregister (zero exte nded) 0100 100B 1000 1100 : 11 sreg qwordreg
segment register to memory 0100 00XB : 1000 1100 : mod sreg r/msegment register to memory64 (zero extended) 0100 10XB 1000 1100 : mod sreg3 r/m
memory to register 0100 0RXB : 0000 1111 : 0011 1000:1111 0000 : mod reg r/mmemory64 to qwordregister 0100 1RXB : 0000 1111 : 0011 1000:1111 0000 : mod reg r/m
register to memory 0100 0RXB :0000 1111 : 0011 1000:1111 0001 : mod reg r/m
qwordregister to memory64 0100 1RXB :0000 1111 : 0011 1000:1111 0001 : mod reg r/m
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ – Move Data from String to String
Move data from string to string 1010 010w
Move data from string to string (qword) 0100 1000 1010 0101
MOVSX/MOVSXD – Move with Sign-Extend
register2 to register1 0100 0R0B : 0000 1111 : 1011 111w : 11 reg1 reg2
byteregister2 to qwordregister1 (sign-extend) 0100 1R0B 0000 1111 : 1011 1110 : 11 quadreg1 bytereg2
wordregister2 to qwordregister1 0100 1R0B 0000 1111  : 1011 1111 : 11 quadreg1 wordreg2
dwordregister2 to qwordregister1 0100 1R 0B 0110 0011 : 11 quadreg1 dwordreg2
memory to register 0100 0RXB : 0000 1111 : 1011 111w : mod reg r/m
memory8 to qwordregister (sign-extend) 0100 1R XB 0000 1111 : 1011 1110 : mod qwordreg r/m
memory16 to qwordregister 0100 1RXB 0000 1111 : 1011 1111 : mod qwordreg r/m

memory32 to qwordregister 0100 1RXB 0110 0011 : mod qwordreg r/m
MOVZX – Move with Zero-ExtendTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-27INSTRUCTION FORMATS AND ENCODINGS
register2 to register1 0100 0R0B : 0000 1111 : 1011 011w : 11 reg1 reg2
dwordregister2 to qwordregister1 0100 1R0B 0000 1111 : 1011 0111 : 11 qwordreg1 
dwordreg2
memory to register 0100 0RXB : 0000 1111 : 1011 011w : mod reg r/m
memory32 to qwordregister 0100 1RXB 00 00 1111 : 1011 0111 : mod qwordreg r/m
AL, AX, or EAX with register 0100 000B : 1111 011w : 11 100 reg
RAX with qwordregister (to RDX:RAX) 0100 100B 1111 0111 : 11 100 qwordreg
AL, AX, or EAX with memory 0100 00XB 1111 011w : mod 100 r/mRAX with memory64 (to RDX:RAX) 0100 10XB 1111 0111 : mod 100 r/m
register 0100 000B : 1111 011w : 11 011 reg
qwordregister 0100 100B 1111 0111 : 11 011 qwordregmemory 0100 00XB : 1111 011w : mod 011 r/m
memory64 0100 10XB 1111 0111 : mod 011 r/m
NOP – No Operation 1001 0000
register 0100 000B : 1111 011w : 11 010 reg
qwordregister 0100 000B 1111 0111 : 11 010 qwordregmemory 0100 00XB : 1111 011w : mod 010 r/m
memory64 0100 1RXB 1111 0111 : mod 010 r/m
byteregister1 to byteregister2 0100 0R0B 0000 1000 : 11 bytereg1 bytereg2
qwordregister1 to qwordregister2 0100 1R0B 0000 1001 : 11 qwordreg1 qwordreg2register2 to register1 0000 101w : 11 reg1 reg2 
byteregister2 to byteregister1 0100 0R0B 0000 1010 : 11 bytereg1 bytereg2 
qwordregister2 to qwordregister1 0100 0R0B 0000 1011 : 11 qwordreg1 qwordreg2 memory to register 0000 101w : mod reg r/m
memory8 to byteregister 0100 0RXB 0000 1010 : mod bytereg r/m
memory8 to qwordregister 0100 0RXB 0000 1011 : mod qwordreg r/mregister to memory 0000 100w : mod reg r/m
byteregister to memory8 0100 0RXB 0000 1000 : mod bytereg r/m
qwordregister to memory64 0100 1RXB 0000 1001 : mod qwordreg r/mimmediate to register 1000 00sw : 11 001 reg : imm
immediate8 to byteregister 0100 000B 1000 0000 : 11 001 bytereg : imm8
immediate32 to qwordregister 0100 000B 1000 0001 : 11 001 qwordreg : imm32immediate8 to qwordregister 0100 000B 1000 0011 : 11 001 qwordreg : imm8
immediate to AL, AX, or EAX 0000 110w : immTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-28 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
immediate64 to RAX 0100 1000 0000 1101 : imm64
immediate to memory 1000 00sw : mod 001 r/m : imm
immediate8 to memory8 0100 00XB 1000 0000 : mod 001 r/m : imm8
immediate32 to memory64 0100 00XB 1000 0001 : mod 001 r/m : imm32immediate8 to memory64 0100 00XB 1000 0011 : mod 001 r/m : imm8
fixed port 1110 011w : port numbervariable port 1110 111w
OUTS – Output to DX Port
output to DX Port 0110 111w
POP – Pop a Value from the Stack
wordregister 0101 0101 : 0100 000B : 1000 1111 : 11 000 reg16
qwordregister 0100 W00B
S : 1000 1111 : 11 000 reg64
wordregister (alternate encoding) 0101 0101 : 0100 000B : 0101 1 reg16qwordregister (alternate encoding) 0100 W00B : 0101 1 reg64
memory64 0100 W0XB
S : 1000 1111 : mod 000 r/m
memory16 0101 0101 : 0100 00XB 1000 1111 : mod 000 r/m
POP – Pop a Segment Regi ster from the Stack
(Note: CS cannot be sreg2 in this usage.)
POPF/POPFQ – Pop Stack into FLAGS/RFLAGS Register
pop stack to FLAGS register 0101 0101 : 1001 1101
pop Stack to RFLAGS register 0100 1000 1001 1101
wordregister 0101 0101 : 0100 000B : 1111 1111 : 11 110 reg16
qwordregister 0100 W00BS : 1111 1111 : 11 110 reg64
wordregister (alternate encoding) 0101 0101 : 0100 000B : 0101 0 reg16
qwordregister (alternate encoding) 0100 W00BS : 0101 0 reg64
memory16 0101 0101 : 0100 000B : 1111 1111 : mod 110 r/mmemory64 0100 W00B
S : 1111 1111 : mod 110 r/m
immediate8 0110 1010 : imm8
immediate16 0101 0101 : 0110 1000 : imm16immediate64 0110 1000 : imm64
register by 1 0100 000B : 1101 000w : 11 010 regqwordregister by 1 0100 100B 1101 0001 : 11 010 qwordregTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-29INSTRUCTION FORMATS AND ENCODINGS
memory by 1 0100 00XB : 1101 000w : mod 010 r/m
memory64 by 1 0100 10XB 1101 0001 : mod 010 r/m
register by CL 0100 000B : 1101 001w : 11 010 reg
qwordregister by CL 0100 100B 1101 0011 : 11 010 qwordregmemory by CL 0100 00XB : 1101 001w : mod 010 r/m
memory64 by CL 0100 10XB 1101 0011 : mod 010 r/m
register by immediate count 0100 000B : 1100 000w : 11 010 reg : imm qwordregister by immediate count 0100 100B 1100 0001 : 11 010 qwordreg : imm8
memory by immediate count 0100 00XB : 1100 000w : mod 010 r/m : imm 
memory64 by immediate count 0100 10XB 1100 0001 : mod 010 r/m : imm8
register by 1 0100 000B : 1101 000w : 11 011 reg
qwordregister by 1 0100 100B 1101 0001 : 11 011 qwordreg
memory by 1 0100 00XB : 1101 000w : mod 011 r/mmemory64 by 1 0100 10XB 1101 0001 : mod 011 r/m
register by CL 0100 000B : 1101 001w : 11 011 reg
qwordregister by CL 0100 000B 1101 0010 : 11 011 qwordregmemory by CL 0100 00XB : 1101 001w : mod 011 r/m
memory64 by CL 0100 10XB 1101 0011 : mod 011 r/m
register by immediate count 0100 000B : 1100 000w : 11 011 reg : imm8qwordregister by immediate count 0100 100B 1100 0001 : 11 011 qwordreg : imm8
memory by immediate count 0100 00XB : 1100 000w : mod 011 r/m : imm8
memory64 by immediate count 0100 10XB 1100 0001 : mod 011 r/m : imm8
RDMSR – Read from Model-Specific Register
load ECX-specified register into  EDX:EAX 0000 1111 : 0011 0010
RDPMC – Read Performance Monitoring Counters
load ECX-specified performance counter into EDX:EAX 0000 1111 : 0011 0011
RDTSC – Read Time-Stamp Counter
read time-stamp counter into EDX:EAX 0000 1111 : 0011 0001
RDTSCP – Read Time-Stamp Counter and Processor ID 0000 1111 : 0000 0001: 1111 1001
REP INS – Input String
REP LODS – Load StringREP MOVS – Move String
REP OUTS – Output String
REP STOS – Store StringREPE CMPS – Compare String
REPE SCAS – Scan String
REPNE CMPS – Compare StringTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-30 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
REPNE SCAS – Scan String
adding immediate to SP 1100 1010 : 16-bit displacement
register by 1 0100 000B 1101 000w : 11 000 reg
byteregister by 1 0100 000B 1101 0000 : 11 000 byteregqwordregister by 1 0100 100B 1101 0001 : 11 000 qwordregmemory by 1 0100 00XB 1101 000w : mod 000 r/m
memory8 by 1 0100 00XB 1101 0000 : mod 000 r/m
memory64 by 1 0100 10XB 1101 0001 : mod 000 r/mregister by CL 0100 000B 1101 001w : 11 000 reg
byteregister by CL 0100 000B 1101 0010 : 11 000 bytereg
qwordregister by CL 0100 100B 1101 0011 : 11 000 qwordregmemory by CL 0100 00XB 1101 001w : mod 000 r/m
memory8 by CL 0100 00XB 1101 0010 : mod 000 r/m
memory64 by CL 0100 10XB 1101 0011 : mod 000 r/mregister by immediate count 1100 000w : 11 000 reg : imm8
byteregister by immediate count 0100 000B 1100 0000 : 11 000 bytereg : imm8
qwordregister by immediate count 0100 100B 1100 0001 : 11 000 bytereg : imm8memory by immediate count 1100 000w : mod 000 r/m : imm8
memory8 by immediate count 0100 00XB 1100 0000 : mod 000 r/m : imm8
memory64 by immediate count 0100 10XB 1100 0001 : mod 000 r/m : imm8
register by 1 0100 000B 1101 000w : 11 001 reg
byteregister by 1 0100 000B 1101 0000 : 11 001 byteregqwordregister by 1 0100 100B 1101 0001 : 11 001 qwordreg
memory by 1 0100 00XB 1101 000w : mod 001 r/m
memory8 by 1 0100 00XB 1101 0000 : mod 001 r/mmemory64 by 1 0100 10XB 1101 0001 : mod 001 r/m
register by CL 0100 000B 1101 001w : 11 001 reg
byteregister by CL 0100 000B 1101 0010 : 11 001 byteregqwordregister by CL 0100 100B 1101 0011 : 11 001 qwordreg
memory by CL 0100 00XB 1101 001w : mod 001 r/m
memory8 by CL 0100 00XB 1101 0010 : mod 001 r/mTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-31INSTRUCTION FORMATS AND ENCODINGS
memory64 by CL 0100 10XB 1101 0011 : mod 001 r/m
register by immediate count 0100 000B 1100 000w : 11 001 reg : imm8 
byteregister by immediate count 0100 000B 1100 0000 : 11 001 reg : imm8
qwordregister by immediate count 0100 100B 1100 0001 : 11 001 qwordreg : imm8memory by immediate count 0100 00XB 1100 000w : mod 001 r/m : imm8

qwordregister by immediate count 0100 100B 1100 0001 : 11 001 qwordreg : imm8memory by immediate count 0100 00XB 1100 000w : mod 001 r/m : imm8 
memory8 by immediate count 0100 00XB 1100 0000 : mod 001 r/m : imm8
memory64 by immediate count 0100 10XB 1100 0001 : mod 001 r/m : imm8
register by 1 0100 000B 1101 000w : 11 111 regbyteregister by 1 0100 000B 1101 0000 : 11 111 bytereg
qwordregister by 1 0100 100B 1101 0001 : 11 111 qwordreg
memory by 1 0100 00XB 1101 000w : mod 111 r/mmemory8 by 1 0100 00XB 1101 0000 : mod 111 r/m
memory64 by 1 0100 10XB 1101 0001 : mod 111 r/m
register by CL 0100 000B 1101 001w : 11 111 regbyteregister by CL 0100 000B 1101 0010 : 11 111 bytereg
qwordregister by CL 0100 100B 1101 0011 : 11 111 qwordreg
memory by CL 0100 00XB 1101 001w : mod 111 r/mmemory8 by CL 0100 00XB 1101 0010 : mod 111 r/m
memory64 by CL 0100 10XB 1101 0011 : mod 111 r/m
register by immediate count 0100 000B 1100 000w : 11 111 reg : imm8 byteregister by immediate count 0100 000B 1100 0000 : 11 111 bytereg : imm8 
qwordregister by immediate count 0100 100B 1100 0001 : 11 111 qwordreg : imm8 
memory by immediate count 0100 00XB 1100 000w : mod 111 r/m : imm8 memory8 by immediate count 0100 00XB 1100 0000 : mod 111 r/m : imm8 
memory64 by immediate count 0100 10XB 1100 0001 : mod 111 r/m : imm8 
register1 to register2 0100 0R0B 0001 100w : 11 reg1 reg2
byteregister1 to byteregister2 0100 0R0B 0001 1000 : 11 bytereg1 bytereg2
quadregister1 to quadregister2 0100 1R0B 0001 1001 : 11 quadreg1 quadreg2register2 to register1 0100 0R0B 0001 101w : 11 reg1 reg2 
byteregister2 to byteregister1 0100 0R0B 0001 1010 : 11 reg1 bytereg2 
byteregister2 to byteregister1 0100 1R0B 0001 1011 : 11 reg1 bytereg2 memory to register 0100 0RXB 0001 101w : mod reg r/m
memory8 to byteregister 0100 0RXB 0001 1010 : mod bytereg r/m
memory64 to byteregister 0100 1RXB 0001 1011 : mod quadreg r/mTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-32 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
register to memory 0100 0RXB 0001 100w : mod reg r/m
byteregister to memory8 0100 0RXB 0001 1000 : mod reg r/m
quadregister to memory64 0100 1RXB 0001 1001 : mod reg r/m
immediate to register 0100 000B 1000 00sw : 11 011 reg : immimmediate8 to byteregister 0100 000B 1000 0000 : 11 011 bytereg : imm8
immediate32 to qwordregister 0100 100B 1000 0001 : 11 011 qwordreg : imm32
immediate8 to qwordregister 0100 100B 1000 0011 : 11 011 qwordreg : imm8immediate to AL, AX, or EAX 0100 000B 0001 110w : imm
immediate32 to RAL 0100 1000 0001 1101 : imm32
immediate to memory 0100 00XB 1000 00sw : mod 011 r/m : immimmediate8 to memory8 0100 00XB 1000 0000 : mod 011 r/m : imm8immediate32 to memory64 0100 10XB 1000 0001 : mod 011 r/m : imm32
immediate8 to memory64 0100 10XB 1000 0011 : mod 011 r/m : imm8
SCAS/SCASB/SCASW/SCASD – Scan String
scan string 1010 111w
scan string (compare AL with byte at RDI) 0100 1000 1010 1110
scan string (compare RAX with qword at RDI) 0100 1000 1010 1111
register 0100 000B 0000 1111 : 1001 tttn : 11 000 reg
register 0100 0000 0000 1111 : 1001 tttn : 11 000 regmemory 0100 00XB 00 00 1111 : 1001 tttn  : mod 000 r/m
memory 0100 0000 0000 1111 : 1001 tttn : mod 000 r/m
A 000 r/m
register by 1 0100 000B 1101 000w : 11 100 reg
byteregister by 1 0100 000B 1101 0000 : 11 100 byteregqwordregister by 1 0100 100B 1101 0001 : 11 100 qwordreg
memory by 1 0100 00XB 1101 000w : mod 100 r/m
memory8 by 1 0100 00XB 1101 0000 : mod 100 r/mmemory64 by 1 0100 10XB 1101 0001 : mod 100 r/m
register by CL 0100 000B 1101 001w : 11 100 reg
byteregister by CL 0100 000B 1101 0010 : 11 100 byteregqwordregister by CL 0100 100B 1101 0011 : 11 100 qwordreg
memory by CL 0100 00XB 1101 001w : mod 100 r/m
memory8 by CL 0100 00XB 1101 0010 : mod 100 r/mmemory64 by CL 0100 10XB 1101 0011 : mod 100 r/m
register by immediate count 0100 000B 1100 000w : 11 100 reg : imm8
byteregister by immediate count 0100 000B 1100 0000 : 11 100 bytereg : imm8Table B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-33INSTRUCTION FORMATS AND ENCODINGS
quadregister by immediate count 0100 100B 1100 0001 : 11 100 quadreg : imm8
memory by immediate count 0100 00XB 1100 000w : mod 100 r/m : imm8
memory8 by immediate count 0100 00XB 1100 0000 : mod 100 r/m : imm8
memory64 by immediate count 0100 10XB 1100 0001 : mod 100 r/m : imm8
register by immediate count 0100 0R0B 0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8
qwordregister by immediate8 0100 1R0B 0000 1111 : 1010 0100 : 11 qworddreg2 
qwordreg1 : imm8
memory by immediate count 0100 0RXB 0000 1111 : 1010 0100 : mod reg r/m : imm8memory64 by immediate8 0100 1RXB 0000 1111 : 1010 0100 : mod qwordreg r/m : 
imm8
register by CL 0100 0R0B 0000 1111 : 1010 0101 : 11 reg2 reg1quadregister by CL 0100 1R0B 0000 1111 : 1010 0101 : 11 quadreg2 quadreg1
memory by CL 0100 00XB 0000 1111 : 1010 0101 : mod reg r/m
memory64 by CL 0100 1RXB 0000 1111 : 1010 0101 : mod quadreg r/m
register by 1 0100 000B 1101 000w : 11 101 reg
byteregister by 1 0100 000B 1101 0000 : 11 101 byteregqwordregister by 1 0100 100B 1101 0001 : 11 101 qwordreg
memory by 1 0100 00XB 1101 000w : mod 101 r/m
memory8 by 1 0100 00XB 1101 0000 : mod 101 r/mmemory64 by 1 0100 10XB 1101 0001 : mod 101 r/m
register by CL 0100 000B 1101 001w : 11 101 reg
byteregister by CL 0100 000B 1101 0010 : 11 101 byteregqwordregister by CL 0100 100B 1101 0011 : 11 101 qwordreg
memory by CL 0100 00XB 1101 001w : mod 101 r/m
memory8 by CL 0100 00XB 1101 0010 : mod 101 r/mmemory64 by CL 0100 10XB 1101 0011 : mod 101 r/m
register by immediate count 0100 000B 1100 000w : 11 101 reg : imm8 
byteregister by immediate count 0100 000B 1100 0000 : 11 101 reg : imm8 qwordregister by immediate count 0100 100B 1100 0001 : 11 101 reg : imm8 
memory by immediate count 0100 00XB 1100 000w : mod 101 r/m : imm8 
memory8 by immediate count 0100 00XB 1100 0000 : mod 101 r/m : imm8 memory64 by immediate count 0100 10XB 1100 0001 : mod 101 r/m : imm8 
register by immediate count 0100 0R0B 0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8qwordregister by immediate8 0100 1R0B 0000 1111 : 1010 1100 : 11 qwordreg2 
memory by immediate count 0100 00XB 0000 1111 : 1010 1100 : mod reg r/m : imm8Table B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-34 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
memory64 by immediate8 0100 1RXB 0000 1111 : 1010 1100 : mod qwordreg r/m : 
imm8
register by CL 0100 000B 0000 1111 : 1010 1101 : 11 reg2 reg1qwordregister by CL 0100 1R0B 0000 1111 : 1010 1101 : 11 qwordreg2 
qwordreg1
memory by CL 0000 1111 : 1010 1101 : mod reg r/m
memory64 by CL 0100 1RXB 0000 1111 : 1010 1101 : mod qwordreg r/m
A 001 r/m
to register 0100 000B 0000 1111 : 0000 0000 : 11 000 reg
to memory 0100 00XB 0000 1111 : 0000 0000 : mod 000 r/m
to register 0100 000B 0000 1111 : 0000 0001 : 11 100 reg
to memory 0100 00XB 0000 1111 : 0000 0001 : mod 100 r/m
STOS/STOSB/STOSW/STOSD/STO SQ – Store String Data
store string data 1010 101w
store string data (RAX at address RDI) 0100 1000 1010 1011
to register 0100 000B 0000 1111 : 0000 0000 : 11 001 reg
to memory 0100 00XB 0000 1111 : 0000 0000 : mod 001 r/m
register1 from register2 0100 0R0B 0010 100w : 11 reg1 reg2
byteregister1 from byteregister2 0100 0R0B 0010 1000 : 11 bytereg1 bytereg2
qwordregister1 from qwordregister2 0100 1R0B 0010 1000 : 11 qwordreg1 qwordreg2register2 from register1 0100 0R0B 0010 101w : 11 reg1 reg2 
byteregister2 from byteregister1 0100 0R0B 0010 1010 : 11 bytereg1 bytereg2 
qwordregister2 from qwordregister1 0100 1R0B 0010 1011 : 11 qwordreg1 qwordreg2 memory from register 0100 00XB 0010 101w : mod reg r/m
memory8 from byteregister 0100 0RXB 0010 1010 : mod bytereg r/m
memory64 from qwordregister 0100 1R XB 0010 1011 : mod qwordreg r/m
register from memory 0100 0RXB 0010 100w : mod reg r/m
byteregister from memory8 0100 0RXB 0010 1000 : mod bytereg r/m
qwordregister from memory8 0100 1RXB 0010 1000 : mod qwordreg r/mimmediate from register 0100 000B 1000 00sw : 11 101 reg : imm
immediate8 from byteregister 0100 000B 1000 0000 : 11 101 bytereg : imm8
immediate32 from qwordregister 0100 100B 1000 0001 : 11 101 qwordreg : imm32Table B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-35INSTRUCTION FORMATS AND ENCODINGS

immediate8 from qwordregister 0100 100B 1000 0011 : 11 101 qwordreg : imm8
immediate from AL, AX, or EAX 0100 000B 0010 110w : imm
immediate32 from RAX 0100 1000 0010 1101 : imm32
immediate from memory 0100 00XB 1000 00sw : mod 101 r/m : immimmediate8 from memory8 0100 00XB 1000 0000 : mod 101 r/m : imm8
immediate32 from memory64 0100 10XB 1000 0001 : mod 101 r/m : imm32
immediate8 from memory64 0100 10XB 1000 0011 : mod 101 r/m : imm8
SWAPGS – Swap GS Base Register
Exchanges the current GS base register value for value in MSR 
C0000102H0000 1111 0000 0001 1111 1000
SYSCALL – Fast System Call
fast call to privilege level 0 system procedures 0000 1111 0000 0101
SYSRET – Return From Fast System Call
return from fast system call 0000 1111 0000 0111
register1 and register2 0100 0R0B 1000 010w : 11 reg1 reg2byteregister1 and byteregister2 0100 0R0B 1000 0100 : 11 bytereg1 bytereg2
qwordregister1 and qwordregister2 0100 1R0B 1000 0101 : 11 qwordreg1 qwordreg2
memory and register 0100 0R0B 1000 010w : mod reg r/mmemory8 and byteregister 0100 0RXB 1000 0100 : mod bytereg r/m
memory64 and qwordregister 0100 1RXB 1000 0101 : mod qwordreg r/m
immediate and register 0100 000B 1111 011w : 11 000 reg : immimmediate8 and byteregister 0100 000B 1111 0110 : 11 000 bytereg : imm8
immediate32 and qwordregister 0100 100B 1111 0111 : 11 000 bytereg : imm8
immediate and AL, AX, or EAX 0100 000B 1010 100w : immimmediate32 and RAX 0100 1000 1010 1001 : imm32
immediate and memory 0100 00XB 1111 011w : mod 000 r/m : imm
immediate8 and memory8 0100 1000 1111 0110 : mod 000 r/m : imm8immediate32 and memory64 0100 1000 1111 0111 : mod 000 r/m : imm32
register 0100 000B 0000 1111 : 0000 0000 : 11 100 reg
memory 0100 00XB 0000 1111 : 0000 0000 : mod 100 r/m
register 0100 000B 0000 1111 : 0000 0000 : 11 101 regmemory 0100 00XB 0000 1111 : 0000 0000 : mod 101 r/m
WBINVD – Writeback and Invalidate Data Cache 0000 1111 : 0000 1001Table B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-36 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
WRMSR – Write to Model-Specific Register
write EDX:EAX to ECX specified MSR 0000 1111 : 0011 0000
write RDX[31:0]:RAX[31:0] to RCX specified MSR 0100 1000 0000 1111 : 0011 0000
register1, register2 0100 0R0B 0000 1111 : 1100 000w : 11 reg2 reg1
byteregister1, byteregister2 0100 0R0B 0000 1111 : 1100 0000 : 11 bytereg2 bytereg1
qwordregister1, qwordregister2 0100 0R0B 0000 1111 : 1100 0001 : 11 qwordreg2 
qwordreg1
memory, register 0100 0RXB 0000 1111 : 1100 000w : mod reg r/mmemory8, bytereg 0100 1RXB 0000 1111 : 1100 0000 : mod bytereg r/mmemory64, qwordreg 0100 1RXB 0000 11 11 : 1100 0001 : mod qwordreg r/m
register1 with register2 1000 011w : 11 reg1 reg2AX or EAX with register 1001 0 reg
memory with register 1000 011w : mod reg r/m
XLAT/XLATB – Table Look-up Translation
AL to byte DS:[(E)BX + unsigned AL] 1101 0111
AL to byte DS:[RBX + unsigned AL] 0100 1000 1101 0111
register1 to register2 0100 0RXB 0011 000w : 11 reg1 reg2
byteregister1 to byteregister2 0100 0R0B 0011 0000 : 11 bytereg1 bytereg2
qwordregister1 to qwordregister2 0100 1R0B 0011 0001 : 11 qwordreg1 qwordreg2register2 to register1 0100 0R0B 0011 001w : 11 reg1 reg2 
byteregister2 to byteregister1 0100 0R0B 0011 0010 : 11 bytereg1 bytereg2 
qwordregister2 to qwordregister1 0100 1R0B 0011 0011 : 11 qwordreg1 qwordreg2 memory to register 0100 0RXB 0011 001w : mod reg r/m
memory8 to byteregister 0100 0RXB 0011 0010 : mod bytereg r/m
memory64 to qwordregister 0100 1RXB 0011 0011 : mod qwordreg r/mregister to memory 0100 0RXB 0011 000w : mod reg r/m
byteregister to memory8 0100 0RXB 0011 0000 : mod bytereg r/m
qwordregister to memory8 0100 1RXB 0011 0001 : mod qwordreg r/mimmediate to register 0100 000B 1000 00sw : 11 110 reg : imm
immediate8 to byteregister 0100 000B 1000 0000 : 11 110 bytereg : imm8
immediate32 to qwordregister 0100 100B 1000 0001 : 11 110 qwordreg : imm32immediate8 to qwordregister 0100 100B 1000 0011 : 11 110 qwordreg : imm8
immediate to AL, AX, or EAX 0100 000B 0011 010w : imm
immediate to RAX 0100 1000 0011 0101 : immediate dataimmediate to memory 0100 00XB 1000 00sw : mod 110 r/m : imm
immediate8 to memory8 0100 00XB 1000 0000 : mod 110 r/m : imm8Table B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingVol. 2D B-37INSTRUCTION FORMATS AND ENCODINGS
B.3 PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS
The following table shows formats and encodings introduced by the Pentium processor family.
B.4 64-BIT MODE INSTRUCTION EN CODINGS FOR SIMD INSTRUCTION 
Non-64-bit mode instruction encodings for MMX Technology , SSE, SSE2, and SSE3 are covered by applying these 
rules to Table B-19 through Table B-31. Table B-34 lists sp ecial encodings (instructions that do not follow the rules 
below).
1. The REX instruction has no effect:
•On immediates.
•If both operands are MMX registers.
•On MMX registers and XMM registers.
•If an MMX register is encoded in the reg field of the ModR/M byte.immediate32 to memory64 0100 10XB 1000 0001 : mod 110 r/m : imm32
immediate8 to memory64 0100 10XB 1000 0011 : mod 110 r/m : imm8
address size 0110 0111LOCK 1111 0000
operand size 0110 0110
CS segment override 0010 1110DS segment override 0011 1110
ES segment override 0010 0110
FS segment override 0110 0100GS segment override 0110 0101SS segment override 0011 0110
Table B-16.  Pentium® Processor Family Inst ruction Formats and Encodings, Non-64-Bit Modes
CMPXCHG8B – Compare and Exchange 8 Bytes 
EDX:EAX with memory64 0000 1111 : 1100 0111 : mod 001 r/m
Table B-17.  Pentium® Processor Family Instruction Formats and Encodings, 64-Bit Mode
CMPXCHG8B/CMPXCHG16B – Compare and Exchange Bytes 
RDX:RAX with memory128 0100 10XB 0000 1111 : 1100 0111 : mod 001 r/mTable B-15.  General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format EncodingB-38 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
2. If a memory operand is encoded in the r/m field of  the ModR/M byte, REX.X and REX.B may be used for 
encoding the memory operand.
3. If a general-purpose register is encoded in the r/m fi eld of the ModR/M byte, REX.B may be used for register 
encoding and REX.W may be used to encode the 64-bit operand size.
4. If an XMM register operand is encoded in the reg fiel d of the ModR/M byte, REX.R may be used for register 
encoding. If an XMM register operand is encoded in th e r/m field of the ModR/M byte, REX.B may be used for 
register encoding.
B.5 MMX INSTRUCTION FORMATS AND ENCODINGS
MMX instructions, except the EMMS instruction, use a format  similar to the 2-byte Intel Architecture integer format. 
Details of subfield encodings within these formats are presented below.
B.5.1  Granularity Field (gg)
The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this 
field is used, it is located in bits 1 and 0 of the second opcode byte. Table B-18 shows the encoding of the gg field.
B.5.2  MMX Technology and General-Purpose Register Fields (mmxreg and reg)
When MMX technology registers (mmxreg) are used as oper ands, they are encoded in th e ModR/M byte in the reg 
field (bits 5, 4, and 3) and/or the R/M field (bits 2, 1, and 0).
If an MMX instruction operates on a general-purpose register  (reg), the register is encoded in the R/M field of the 
ModR/M byte.
B.5.3  MMX Instruction Formats and Encodings Table
Table B-19 shows the formats and encodings of the integer instructions.Table B-18.  Encoding of Granularity of Data Field (gg)
gg Granularity of Data
00 Packed Bytes
01 Packed Words10 Packed Doublewords
11 Quadword
Table B-19.  MMX Instruction Formats and Encodings
EMMS – Empty MMX technology state 0000 1111:01110111
MOVD – Move doubleword
reg to mmxreg 0000 1111:0110 1110: 11 mmxreg reg
reg from mmxreg 0000 1111:0111 1110: 11 mmxreg reg
mem to mmxreg 0000 1111:0110 1110: mod mmxreg r/mmem from mmxreg 0000 1111:0111 1110: mod mmxreg r/m
MOVQ – Move quadword
mmxreg2 to mmxreg1 0000 1111:0110 1111: 11 mmxreg1 mmxreg2mmxreg2 from mmxreg1 0000 1111:0111 1111: 11 mmxreg1 mmxreg2Vol. 2D B-39INSTRUCTION FORMATS AND ENCODINGS
mem to mmxreg 0000 1111:0110 1111: mod mmxreg r/m
mem from mmxreg 0000 1111:0111 1111: mod mmxreg r/m
PACKSSDW1 – Pack dword to word data (signed with saturation)
mmxreg2 to mmxreg1 0000 1111:0110 1011: 11 mmxreg1 mmxreg2memory to mmxreg 0000 1111:0110 1011: mod mmxreg r/m
PACKSSWB
1 – Pack word to byte data (signed with saturation)

PACKSSWB
mmxreg2 to mmxreg1 0000 1111:0110 0011: 11 mmxreg1 mmxreg2memory to mmxreg 0000 1111:0110 0011: mod mmxreg r/m
PACKUSWB
1 – Pack word to byte data (unsigned with saturation)
mmxreg2 to mmxreg1 0000 1111:0110 0111: 11 mmxreg1 mmxreg2memory to mmxreg 0000 1111:0110 0111: mod mmxreg r/m
PADD – Add with wrap-around
mmxreg2 to mmxreg1 0000 1111: 1111 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111: 1111 11gg: mod mmxreg r/m
PADDS – Add signed with saturation
mmxreg2 to mmxreg1 0000 1111: 1110 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111: 1110 11gg: mod mmxreg r/m
PADDUS – Add unsigned with saturation
mmxreg2 to mmxreg1 0000 1111: 1101 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111: 1101 11gg: mod mmxreg r/m
PAND – Bitwise And
mmxreg2 to mmxreg1 0000 1111:1101 1011: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111:1101 1011: mod mmxreg r/m
PANDN – Bitwise AndNot
mmxreg2 to mmxreg1 0000 1111:1101 1111: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111:1101 1111: mod mmxreg r/m
PCMPEQ – Packed compare for equality
 mmxreg1 with mmxreg2 0000 1111:0111 01gg: 11 mmxreg1 mmxreg2
  mmxreg with memory 0000 1111:0111 01gg: mod mmxreg r/mPCMPGT – Packed compare greater (signed)
mmxreg1 with mmxreg2 0000 1111:0110 01gg: 11 mmxreg1 mmxreg2
mmxreg with memory 0000 1111:0110 01gg: mod mmxreg r/m
PMADDWD – Packed multiply add
mmxreg2 to mmxreg1 0000 1111:1111 0101: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111:1111 0101: mod mmxreg r/m
PMULHUW – Packed multiplication, store high word (unsigned)
   mmxreg2 to mmxreg1 0000 1111: 1110 0100: 11 mmxreg1 mmxreg2
   memory to mmxreg 0000 1111: 1110 0100: mod mmxreg r/mTable B-19.  MMX Instruction Formats and Encodings (Contd.)
Instruction and Format EncodingB-40 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
PMULHW – Packed multiplication, store high word
mmxreg2 to mmxreg1 0000 1111:1110 0101: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111:1110 0101: mod mmxreg r/m
PMULLW – Packed multip lication, store low word
mmxreg2 to mmxreg1 0000 1111:1101 0101: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111:1101 0101: mod mmxreg r/m
POR – Bitwise Or
mmxreg2 to mmxreg1 0000 1111:1110 1011: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111:1110 1011: mod mmxreg r/m
PSLL2 – Packed shift left logical
mmxreg1 by mmxreg2 0000 1111:1111 00gg: 11 mmxreg1 mmxreg2mmxreg by memory 0000 1111:1111 00gg: mod mmxreg r/m
mmxreg by immediate 0000 1111:0111 00gg: 11 110 mmxreg: imm8 data
PSRA
2 – Packed shift right arithmetic
mmxreg1 by mmxreg2 0000 1111:1110 00gg: 11 mmxreg1 mmxreg2
mmxreg by memory 0000 1111:1110 00gg: mod mmxreg r/m
mmxreg by immediate 0000 1111:0111 00gg: 11 100 mmxreg: imm8 data
PSRL2 – Packed shift right logical
mmxreg1 by mmxreg2 0000 1111:1101 00gg: 11 mmxreg1 mmxreg2
   mmxreg by memory 0000 1111:1101 00gg: mod mmxreg r/m
mmxreg by immediate 0000 1111:0111 00gg: 11 010 mmxreg: imm8 data
PSUB – Subtract with wrap-around
mmxreg2 from mmxreg1 0000 1111:1111 10gg: 11 mmxreg1 mmxreg2memory from mmxreg 0000 1111:1111 10gg: mod mmxreg r/m
PSUBS – Subtract signed with saturation
mmxreg2 from mmxreg1 0000 1111:1110 10gg: 11 mmxreg1 mmxreg2memory from mmxreg 0000 1111:1110 10gg: mod mmxreg r/m
PSUBUS – Subtract unsigned with saturation
mmxreg2 from mmxreg1 0000 1111:1101 10gg: 11 mmxreg1 mmxreg2memory from mmxreg 0000 1111:1101 10gg: mod mmxreg r/m
PUNPCKH – Unpack high data to next larger type
mmxreg2 to mmxreg1 0000 1111:0110 10gg: 11 mmxreg1 mmxreg2memory to mmxreg 0000 1111:0110 10gg: mod mmxreg r/m
PUNPCKL – Unpack low data to next larger type
mmxreg2 to mmxreg1 0000 1111:0110 00gg: 11 mmxreg1 mmxreg2memory to mmxreg 0000 1111:0110 00gg: mod mmxreg r/mTable B-19.  MMX Instruction Formats and Encodings (Contd.)
Instruction and Format EncodingVol. 2D B-41INSTRUCTION FORMATS AND ENCODINGS
B.6 PROCESSOR EXTENDED STATE IN STRUCTION FORMATS AND ENCODINGS
Table B-20 shows the formats and encodings for several instructions that relate to processor extended state 
  
B.7 P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS 
Table B-20 shows the formats and encodings for several instructions that were introduced into the IA-32 architec-
ture in the P6 family processors.
  PXOR – Bitwise Xor
mmxreg2 to mmxreg1 0000 1111:1110 1111: 11 mmxreg1 mmxreg2
memory to mmxreg 0000 1111:1110 1111: mod mmxreg r/m
NOTES:
1. The pack instructions perform saturation from signed packed data of one type to signed or unsigned data of the next smaller t ype.
2. The format of the shift instructions has one additional format  to support shifting by immedi ate shift-counts. The shift opera tions 
are not supported equally for all data types.
Table B-20.  Formats and Encodings of XSAVE/XRSTOR/XGETBV/XSETBV Instructions
XGETBV – Get Value of Extended Control Register 0000 1111:0000 0001: 1101 0000
XRSTOR – Restore Processor Extended States10000 1111:1010 1110: modA 101 r/m
XSAVE – Save Processor Extended States10000 1111:1010 1110: modA 100 r/m
XSETBV – Set Extended Control Register 0000 1111:0000 0001: 1101 0001
NOTES:
1.   For XSAVE and XRSTOR, “mod = 11” is reserved.
Table B-21.  Formats and Encodings of P6 Family Instructions 
CMOVcc – Conditional Move
register2 to  register1 0000 1111: 0100 tttn : 11 reg1 reg2
memory to register  0000 1111 : 0100 tttn : mod reg r/m
FCMOVcc – Conditional Move on EFLAG Register Condition Codes
move if below (B) 11011 010 : 11 000 ST(i)
move if equal (E) 11011 010 : 11 001 ST(i)move if below or equal (BE) 11011 010 : 11 010 ST(i)
move if unordered (U) 11011 010 : 11 011 ST(i)
move if not below (NB) 11011 011 : 11 000 ST(i)move if not equal (NE) 11011 011 : 11 001 ST(i)
move if not below or equal (NBE) 11011 011 : 11 010 ST(i)Table B-19.  MMX Instruction Formats and Encodings (Contd.)
Instruction and Format EncodingB-42 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.8 SSE INSTRUCTION FORMATS AND ENCODINGS 
The SSE instructions use the ModR/M format and are preced ed by the 0FH prefix byte. In general, operations are 
not duplicated to provide two directions (that is, separate load and store variants).
The following three tables (Tables B-22, B-23, and B- 24) show the formats and encodings for the SSE SIMD 
floating-point, SIMD integer, and cach eability and memory ordering instruct ions, respectively. Some SSE instruc-
tions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode. Mand atory prefixes are included 
in the tables.move if not unordered (NU) 11011 011 : 11 011 ST(i)
FCOMI  – Compare Real and Set EFLAGS 11011 011 : 11 110 ST(i)
FXRSTOR – Restore x87 FPU, MMX, SSE, and SSE2 State10000 1111:1010 1110: modA 001 r/m
FXSAVE – Save x87 FPU, MMX, SSE, and SSE2 State10000 1111:1010 1110: modA 000 r/m
SYSENTER – Fast System Call 0000 1111:0011 0100
SYSEXIT – Fast Return from Fast System Call 0000 1111:0011 0101
NOTES:
1.   For  FXSAVE and FXRSTO R, “mod = 11” is reserved.
Table B-22.  Formats and Encodings of SSE Floating-Point Instructions 
ADDPS—Add Packed Single Prec ision Floating-Point Values
   xmmreg2 to xmmreg1 0000 1111:0101 1000:11 xmmreg1 xmmreg2 
   mem to xmmreg 0000 1111:0101 1000:  mod xmmreg r/m
ADDSS—Add Scalar Single Prec ision Floating-Point Values
   xmmreg2 to xmmreg1 1111 0011:0000 1111:01011000:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0011:0000 1111:01011000: mod xmmreg r/m
ANDNPS—Bitwise Logical AND NOT of Packed  Single Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 0101:11 xmmreg1 xmmreg2
   mem to xmmreg 0000 1111:0101 0101:  mod xmmreg r/m
ANDPS—Bitwise Logical AND of Packed Si ngle Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 0100:11 xmmreg1 xmmreg2
  mem to xmmreg 0000 1111:0101 0100:  mod xmmreg r/m
CMPPS—Compare Packed Single Pr ecision Floating-Point Values
   xmmreg2 to xmmreg1, imm8 0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
   mem to xmmreg, imm8 0000 1111:1100 0010:  mod xmmreg r/m: imm8
CMPSS—Compare Scalar Single Pr ecision Floating-Point Values
   xmmreg2 to xmmreg1, imm8 1111 0011:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
   mem to xmmreg, imm8 1111 0011:0000 1111:1100 0010: mod xmmreg r/m: imm8
COMISS—Compare Scalar Ordered Single Precis ion Floating-Point Values and Set EFLAGS
   xmmreg2 to xmmreg1 0000 1111:0010 1111:11 xmmreg1 xmmreg2
   mem to xmmreg 0000 1111:0010 1111:  mod xmmreg r/mTable B-21.  Formats and Encodings of P6 Family Instructions  (Contd.)
Instruction and Format EncodingVol. 2D B-43INSTRUCTION FORMATS AND ENCODINGS
CVTPI2PS—Convert Packed Doublewo rd Integers to Packed Single Precision Floating-Point Values
  mmreg to xmmreg 0000 1111:0010 1010:11 xmmreg1 mmreg1
  mem to xmmreg 0000 1111:0010 1010:  mod xmmreg r/m
CVTPS2PI—Convert Packed Single Precision Floati ng-Point Values to Packed Doubleword Integers
  xmmreg to mmreg 0000 1111:0010 1101:11 mmreg1 xmmreg1
  mem to mmreg 0000 1111:0010 1101:  mod mmreg r/m
CVTSI2SS—Convert Doubleword Integer to Scal ar Single Precision Floating-Point Value

xmmreg2 to xmmreg1, imm8 1111 0011:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
  r32 to xmmreg1 1111 0011:0000 1111:00101010:11 xmmreg1 r32
  mem to xmmreg 1111 0011:0000 1111:00101010: mod xmmreg r/m
CVTSS2SI—Convert Scalar Single Precision Fl oating-Point Value to Doubleword Integer
  xmmreg to r32 1111 0011:0000 1111:0010 1101:11 r32 xmmreg  mem to r32 1111 0011:0000 1111:0010 1101: mod r32 r/m
CVTTPS2PI—Convert with Truncation Packed  Single Precision Floati ng-Point Values to Packed Doubleword Integers
  xmmreg to mmreg 0000 1111:0010 1100:11 mmreg1 xmmreg1  mem to mmreg 0000 1111:0010 1100:  mod mmreg r/m
CVTTSS2SI—Convert with Truncation Sc alar Single Precision Floating-Point Value to Doubleword Integer
  xmmreg to r32 1111 0011:0000 1111:0010 1100:11 r32 xmmreg1  mem to r32 1111 0011:0000 1111:0010 1100: mod r32 r/m
DIVPS—Divide Packed Single Pr ecision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 1110:11 xmmreg1 xmmreg2  mem to xmmreg 0000 1111:0101 1110:  mod xmmreg r/m
DIVSS—Divide Scalar Single Pr ecision Floating-Point Values
  xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 1110:11 xmmreg1 xmmreg2  mem to xmmreg 1111 0011:0000 1111:0101 1110: mod xmmreg r/m
LDMXCSR—Load  MXCSR Register State
  m32 to MXCSR 0000 1111:1010 1110:mod
A 010 mem
MAXPS—Return Maximum Packed Single  Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 1111:11 xmmreg1 xmmreg2
  mem to xmmreg 0000 1111:0101 1111: mod xmmreg r/mMAXSS—Return Maximum Scalar Double  Precision Floating-Point Value
  xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 1111:11 xmmreg1 xmmreg2
  mem to xmmreg 1111 0011:0000 1111:0101 1111: mod xmmreg r/mMINPS—Return Minimum Packed Double  Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 1101:11 xmmreg1 xmmreg2
  mem to xmmreg 0000 1111:0101 1101: mod xmmreg r/mMINSS—Return Minimum Scalar Double  Precision Floating-Point Value
  xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 1101:11 xmmreg1 xmmreg2
  mem to xmmreg 1111 0011:0000 1111:0101 1101: mod xmmreg r/mTable B-22.  Formats and Encodings of SSE Floating-Point Instructions  (Contd.)
Instruction and Format EncodingB-44 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
MOVAPS—Move Aligned Packed Single  Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0010 1000:11 xmmreg2 xmmreg1
  mem to xmmreg1 0000 1111:0010 1000: mod xmmreg r/m
  xmmreg1 to xmmreg2 0000 1111:0010 1001:11 xmmreg1 xmmreg2
  xmmreg1 to mem 0000 1111:0010 1001: mod xmmreg r/mMOVHLPS—Move Packed Single Precision Floating-Point Values High to Low
  xmmreg2 to xmmreg1 0000 1111:0001 0010:11 xmmreg1 xmmreg2
MOVHPS—Move High Packed Single Precision Floating-Point Values
  mem to xmmreg 0000 1111:0001 0110: mod xmmreg r/m  xmmreg to mem 0000 1111:0001 0111: mod xmmreg r/m
MOVLHPS—Move Packed Single Precision Floating-Point Values Low to High
  xmmreg2 to xmmreg1 0000 1111:00010110:11 xmmreg1 xmmreg2
MOVLPS—Move Low Packed Single Precision Floating-Point Values
  mem to xmmreg 0000 1111:0001 0010: mod xmmreg r/m
  xmmreg to mem 0000 1111:0001 0011: mod xmmreg r/mMOVMSKPS—Extract Packed Single Pr ecision Floating-Point Sign Mask
  xmmreg to r32 0000 1111:0101 0000:11 r32 xmmreg
MOVSS—Move Scalar Single Pr ecision Floating-Point Values
  xmmreg2 to xmmreg1 1111 0011:0000 1111:0001 0000:11 xmmreg2 xmmreg1
  mem to xmmreg1 1111 0011:0000 1111:0001 0000: mod xmmreg r/m
  xmmreg1 to xmmreg2 1111 0011:0000 1111:0001 0001:11 xmmreg1 xmmreg2  xmmreg1 to mem 1111 0011:0000 1111:0001 0001: mod xmmreg r/m
MOVUPS—Move Unaligned Packed Single  Precision Floating-Point Values
   xmmreg2 to xmmreg1 0000 1111:0001 0000:11 xmmreg2 xmmreg1
  mem to xmmreg1 0000 1111:0001 0000: mod xmmreg r/m
   xmmreg1 to xmmreg2 0000 1111:0001 0001:11 xmmreg1 xmmreg2
  xmmreg1 to mem 0000 1111:0001 0001: mod xmmreg r/m
MULPS—Multiply Packed Single Precision Floating-Point Values
   xmmreg2 to xmmreg1 0000 1111:0101 1001:11 xmmreg1 xmmreg2
   mem to xmmreg 0000 1111:0101 1001: mod xmmreg r/m
MULSS—Multiply Scalar Single Precision Floating-Point Values
  xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 1001:11 xmmreg1 xmmreg2
  mem to xmmreg 1111 0011:0000 1111:0101 1001: mod xmmreg r/m
ORPS—Bitwise Logical OR of Single  Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 0110:11 xmmreg1 xmmreg2
   mem to xmmreg 0000 1111:0101 0110: mod xmmreg r/mRCPPS—Compute Reciprocals of Packed Si ngle Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 0011:11 xmmreg1 xmmreg2Table B-22.  Formats and Encodings of SSE Floating-Point Instructions  (Contd.)
Instruction and Format EncodingVol. 2D B-45INSTRUCTION FORMATS AND ENCODINGS
  mem to xmmreg 0000 1111:0101 0011: mod xmmreg r/m
RCPSS—Compute Reciprocals of Scalar Si ngle Precision Floating-Point Value
  xmmreg2 to xmmreg1 1111 0011:0000 1111:01010011:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0011:0000 1111:01010011: mod xmmreg r/mRSQRTPS—Compute Reciprocals of Sq uare Roots of Packed Single Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 0010:11 xmmreg1 xmmreg2
  mem to xmmreg 0000 1111:0101 0010: mode xmmreg r/mRSQRTSS—Compute Reciprocals of Sq uare Roots of Scalar Single Precision Floating-Point Value
   xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 0010:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0011:0000 1111:0101 0010: mod xmmreg r/m
SHUFPS—Shuffle Packed Single Precision Fl oating-Point Values
  xmmreg2 to xmmreg1, imm8 0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8
  mem to xmmreg, imm8 0000 1111:1100 0110: mod xmmreg r/m: imm8
SQRTPS—Compute Square Roots of Packed Single Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 0001:11 xmmreg1 xmmreg2
  mem to xmmreg 0000 1111:0101 0001: mod xmmreg r/m
SQRTSS—Compute Square Root  of Scalar Single Precis ion Floating-Point Value
  xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 0001:11 xmmreg1 xmmreg2
  mem to xmmreg 1111 0011:0000 1111:0101 0001:mod xmmreg r/m
STMXCSR—Store MXCSR Register State   MXCSR to mem 0000 1111:1010 1110:mod
A 011 mem
SUBPS—Subtract Packed Single Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0101 1100:11 xmmreg1 xmmreg2  mem to xmmreg 0000 1111:0101 1100:mod xmmreg r/m
SUBSS—Subtract Scalar Single Precision Floating-Point Values
  xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 1100:11 xmmreg1 xmmreg2  mem to xmmreg 1111 0011:0000 1111:0101 1100:mod xmmreg r/m
UCOMISS—Unordered Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS
  xmmreg2 to xmmreg1 0000 1111:0010 1110:11 xmmreg1 xmmreg2
  mem to xmmreg 0000 1111:0010 1110: mod xmmreg r/m
UNPCKHPS—Unpack and Interleave High Packed  Single Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0001 0101:11 xmmreg1 xmmreg2
  mem to xmmreg 0000 1111:0001 0101: mod xmmreg r/m
UNPCKLPS—Unpack and Interleave Low Packed  Single Precision Floating-Point Values
  xmmreg2 to xmmreg1 0000 1111:0001 0100:11 xmmreg1 xmmreg2  mem to xmmreg 0000 1111:0001 0100: mod xmmreg r/m
XORPS—Bitwise Logical XOR of Single  Precision Floating-Point Values
   xmmreg2 to xmmreg1 0000 1111:0101 0111:11 xmmreg1 xmmreg2Table B-22.  Formats and Encodings of SSE Floating-Point Instructions  (Contd.)
Instruction and Format EncodingB-46 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
   mem to xmmreg 0000 1111:0101 0111: mod xmmreg r/m
Table B-23.  Formats and Encodings of SSE Integer Instructions
PAVGB/PAVGW—Average Packed Integers
   mmreg2 to mmreg1 0000 1111:1110 0000:11 mmreg1 mmreg2
0000 1111:1110 0011:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1110 0000: mod mmreg r/m
0000 1111:1110 0011: mod mmreg r/m
PEXTRW—Extract Word  mmreg to reg32, imm8 0000 1111:1100 0101:11 r32 mmreg: imm8PINSRW—Insert Word
  reg32 to mmreg, imm8 0000 1111:1100 0100:11 mmreg r32: imm8
  m16 to mmreg, imm8 0000 1111:1100 0100: mod mmreg r/m: imm8PMAXSW—Maximum of Packed Signed Word Integers
  mmreg2 to mmreg1 0000 1111:1110 1110:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1110 1110: mod mmreg r/mPMAXUB—Maximum of Packed Unsigned Byte Integers
  mmreg2 to mmreg1 0000 1111:1101 1110:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1101 1110: mod mmreg r/mPMINSW—Minimum of Packed Signed Word Integers
   mmreg2 to mmreg1 0000 1111:1110 1010:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1110 1010: mod mmreg r/m
PMINUB—Minimum of Packed Unsigned Byte Integers
   mmreg2 to mmreg1 0000 1111:1101 1010:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1101 1010: mod mmreg r/mPMOVMSKB—Move Byte Mask To Integer
   mmreg to reg32 0000 1111:1101 0111:11 r32 mmreg
PMULHUW—Multiply Packed Unsigned  Integers and Store High Result
  mmreg2 to mmreg1 0000 1111:1110 0100:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1110 0100: mod mmreg r/m
PSADBW—Compute Sum of Absolute Differences  mmreg2 to mmreg1 0000 1111:1111 0110:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1111 0110: mod mmreg r/m
PSHUFW—Shuffle Packed Words   mmreg2 to mmreg1, imm8 0000 1111:0111 0000:11 mmreg1 mmreg2: imm8

mmreg2 to mmreg1 0000 1111:1101 1110:11 mmreg1 mmreg2
   mem to mmreg, imm8 0000 1111:0111 0000: mod mmreg r/m: imm8Table B-22.  Formats and Encodings of SSE Floating-Point Instructions  (Contd.)
Instruction and Format EncodingVol. 2D B-47INSTRUCTION FORMATS AND ENCODINGS
B.9 SSE2 INSTRUCTION FORMATS AND ENCODINGS 
The SSE2 instructions use the ModR/M format and are preced ed by the 0FH prefix byte. In general, operations are 
The following three tables show the formats and encoding s for the SSE2 SIMD floating-point, SIMD integer, and 
cacheability instructions, respectively. Some SSE2 instructio ns require a mandatory prefix (66H, F2H, F3H) as part 
of the two-byte opcode. These pref ixes are included in the tables.
B.9.1  Granularity Field (gg)
field is used, it is located in bits 1 and 0 of the second  opcode byte. Table B-25 shows the encoding of this gg field.Table B-24.  Format and Encoding of SSE Cacheability & Memory Ordering Instructions  
MASKMOVQ—Store Selected Bytes of Quadword   mmreg2 to mmreg1 0000 1111:1111 0111:11 mmreg1 mmreg2
MOVNTPS—Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint
   xmmreg to mem 0000 1111:0010 1011: mod xmmreg r/mMOVNTQ—Store Quadword Using Non-Temporal Hint
   mmreg to mem 0000 1111:1110 0111: mod mmreg r/m
PREFETCHT0—Prefetch Temporal to All Cache Levels 0000 1111:0001 1000:mod
A 001 mem
PREFETCHT1—Prefetch Temporal to First Level Cache 0000 1111:0001 1000:modA 010 mem
PREFETCHT2—Prefetch Temporal to Second Level Cache 0000 1111:0001 1000:modA 011 mem
PREFETCHNTA—Prefetch Non-Te mporal to All Cache Levels 0000 1111:0001 1000:modA 000 mem
SFENCE—Store Fence 0000 1111:1010 1110:11 111 000
Table B-25.  Encoding of Gr anularity of Data Field (gg)
00 Packed Bytes01 Packed Words
10 Packed Doublewords
11 QuadwordB-48 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
Table B-26.  Formats and Encodings of SSE2 Floating-Point Instructions
ADDPD—Add Packed Double Prec ision Floating-Point Values
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 1000:11 xmmreg1 xmmreg2 
  mem to xmmreg 0110 0110:0000 1111:0101 1000:  mod xmmreg r/m
ADDSD—Add Scalar Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 1111 0010:0000 1111:0101 1000:11 xmmreg1 xmmreg2
  mem to xmmreg 1111 0010:0000 1111:0101 1000: mod xmmreg r/m
ANDNPD—Bitwise Logical AND NOT of Packed  Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 0101:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0101 0101:  mod xmmreg r/m
ANDPD—Bitwise Logical AND of Packed Do uble Precision Floating-Point Values
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 0100:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0101 0100:  mod xmmreg r/m
CMPPD—Compare Packed Double Pr ecision Floating-Point Values
  xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8  mem to xmmreg, imm8 0110 0110:0000 1111:1100 0010:  mod xmmreg r/m: imm8
CMPSD—Compare Scalar Double Pr ecision Floating-Point Values
  xmmreg2 to xmmreg1, imm8 1111 0010:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8  mem to xmmreg, imm8 11110 010:0000 1111:1100 0010: mod xmmreg r/m: imm8
COMISD—Compare Scalar Ordered Double Prec ision Floating-Point Values and Set EFLAGS
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0010 1111:11 xmmreg1 xmmreg2   mem to xmmreg 0110 0110:0000 1111:0010 1111:  mod xmmreg r/m
CVTPI2PD—Convert Packed Doubleword Integers to  Packed Double Precision Floating-Point Values
   mmreg to xmmreg 0110 0110:0000 1111:0010 1010:11 xmmreg1 mmreg1   mem to xmmreg 0110 0110:0000 1111:0010 1010:  mod xmmreg r/m
CVTPD2PI—Convert Packed Double Precision Floati ng-Point Values to Packed Doubleword Integers
  xmmreg to mmreg 0110 0110:0000 1111:0010 1101:11 mmreg1 xmmreg1
  mem to mmreg 0110 0110:0000 1111:0010 1101:  mod mmreg r/m
CVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point Value
  r32 to xmmreg1 1111 0010:0000 1111:0010 1010:11 xmmreg r32  mem to xmmreg 1111 0010:0000 1111:0010 1010: mod xmmreg r/m
CVTSD2SI—Convert Scalar Double Precision Fl oating-Point Value to Doubleword Integer
  xmmreg to r32 1111 0010:0000 1111:0010 1101:11 r32 xmmreg  mem to r32 1111 0010:0000 1111:0010 1101: mod r32 r/m
CVTTPD2PI—Convert with Truncation Packed  Double Precision Floating-Point Va lues to Packed Doubleword Integers
  xmmreg to mmreg 0110 0110:0000 1111:0010 1100:11 mmreg xmmreg   mem to mmreg 0110 0110:0000 1111:0010 1100:  mod mmreg r/m
CVTTSD2SI—Convert with Truncation Sc alar Double Precision Floating-Poi nt Value to Doubleword Integer
  xmmreg to r32 1111 0010:0000 1111:0010 1100:11 r32 xmmregVol. 2D B-49INSTRUCTION FORMATS AND ENCODINGS
  mem to r32 1111 0010:0000 1111:0010 1100: mod r32 r/m
CVTPD2PS—Covert Packed Double  Precision Floating-Point Values to Pack ed Single Precision Floating-Point Values
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 1010:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:0101 1010:  mod xmmreg r/m
CVTPS2PD—Covert Packed Single  Precision Floating-Point Values to Pack ed Double Precision Floating-Point Values
   xmmreg2 to xmmreg1 0000 1111:0101 1010:11 xmmreg1 xmmreg2
   mem to xmmreg 0000 1111:0101 1010:  mod xmmreg r/m
CVTSD2SS—Covert Scalar Double  Precision Floating-Point Value to Scalar  Single Precision Fl oating-Point Value
   xmmreg2 to xmmreg1 1111 0010:0000 1111:0101 1010:11 xmmreg1 xmmreg2   mem to xmmreg 1111 0010:0000 1111:0101 1010:  mod xmmreg r/m
CVTSS2SD—Covert Scalar Single Precisio n Floating-Point Value to Scalar Do uble Precision Floating-Point Value
   xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 1010:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0011:00001 111:0101 1010:  mod xmmreg r/m
CVTPD2DQ—Convert Packed Double Precision Floati ng-Point Values to Packed Doubleword Integers
   xmmreg2 to xmmreg1 1111 0010:0000 1111:1110 0110:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0010:0000 1111:1110 0110:  mod xmmreg r/m
CVTTPD2DQ—Convert With Truncation Packed  Double Precision Floating-Point Va lues to Packed Doubleword Integers
   xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 0110:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:1110 0110:  mod xmmreg r/m
CVTDQ2PD—Convert Packed Doubleword Integers to  Packed Single Precision Floating-Point Values
   xmmreg2 to xmmreg1 1111 0011:0000 1111:1110 0110:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0011:0000 1111:1110 0110:  mod xmmreg r/m
CVTPS2DQ—Convert Packed Single Precision Floati ng-Point Values to Packed Doubleword Integers
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 1011:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:0101 1011:  mod xmmreg r/m
CVTTPS2DQ—Convert With Truncation Packed  Single Precision Floati ng-Point Values to Packed Doubleword Integers
   xmmreg2 to xmmreg1 1111 0011:0000 1111:0101 1011:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0011:0000 1111:0101 1011:  mod xmmreg r/m
CVTDQ2PS—Convert Packed Doubleword Integers to  Packed Double Precisio n Floating-Point Values
   xmmreg2 to xmmreg1 0000 1111:0101 1011:11 xmmreg1 xmmreg2
   mem to xmmreg 0000 1111:0101 1011:  mod xmmreg r/m
DIVPD—Divide Packed Double Precision Floating-Point Values   xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 1110:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:0101 1110:  mod xmmreg r/m
DIVSD—Divide Scalar Double Pr ecision Floating-Point Values
   xmmreg2 to xmmreg1 1111 0010:0000 1111:0101 1110:11 xmmreg1 xmmreg2Table B-26.  Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format EncodingB-50 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
   mem to xmmreg 1111 0010:0000 1111:0101 1110: mod xmmreg r/m
MAXPD—Return Maximum Packed Double  Precision Floating-Point Values
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 1111:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:0101 1111: mod xmmreg r/mMAXSD—Return Maximum Scalar Double  Precision Floating-Point Value
   xmmreg2 to xmmreg1 1111 0010:0000 1111:0101 1111:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0010:0000 1111:0101 1111: mod xmmreg r/mMINPD—Return Minimum Packed Double  Precision Floating-Point Values
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 1101:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:0101 1101: mod xmmreg r/mMINSD—Return Minimum Scalar Double  Precision Floating-Point Value
   xmmreg2 to xmmreg1 1111 0010:0000 1111:0101 1101:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0010:0000 1111:0101 1101: mod xmmreg r/m
MOVAPD—Move Aligned Packed Double  Precision Floating-Point Values
   xmmreg1 to xmmreg2 0110 0110:0000 1111:0010 1001:11 xmmreg2 xmmreg1
   xmmreg1 to mem 0110 0110:0000 1111:0010 1001: mod xmmreg r/m
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0010 1000:11 xmmreg1 xmmreg2   mem to xmmreg1 0110 0110:0000 1111:0010 1000: mod xmmreg r/m
MOVHPD—Move High Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1 1111 0010:0000 1111:0101 1111:11 xmmreg1 xmmreg2
   xmmreg to mem 0110 0110:0000 1111:0001 0111: mod xmmreg r/m   mem to xmmreg 0110 0110:0000 1111:0001 0110: mod xmmreg r/m
MOVLPD—Move Low Packed Double Precision Floating-Point Values
   xmmreg to mem 0110 0110:0000 1111:0001 0011: mod xmmreg r/m   mem to xmmreg 0110 0110:0000 1111:0001 0010: mod xmmreg r/m
MOVMSKPD—Extract Packed Double Pr ecision Floating-Point Sign Mask
   xmmreg to r32 0110 0110:0000 1111:0101 0000:11 r32 xmmregMOVSD—Move Scalar Double Pr ecision Floating-Point Values
   xmmreg1 to xmmreg2 1111 0010:0000 1111:0001 0001:11 xmmreg2 xmmreg1
   xmmreg1 to mem 1111 0010:0000 1111:0001 0001: mod xmmreg r/m   xmmreg2 to xmmreg1 1111 0010:0000 1111:0001 0000:11 xmmreg1 xmmreg2
   mem to xmmreg1 1111 0010:0000 1111:0001 0000: mod xmmreg r/m
MOVUPD—Move Unaligned Packed Double  Precision Floating-Point Values
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0001 0001:11 xmmreg2 xmmreg1
  mem to xmmreg1 0110 0110:0000 1111:0001 0001: mod xmmreg r/m
  xmmreg1 to xmmreg2 0110 0110:0000 1111:0001 0000:11 xmmreg1 xmmreg2   xmmreg1 to mem 0110 0110:0000 1111:0001 0000: mod xmmreg r/m
MULPD—Multiply Packed Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 1001:11 xmmreg1 xmmreg2Table B-26.  Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format EncodingVol. 2D B-51INSTRUCTION FORMATS AND ENCODINGS
  mem to xmmreg 0110 0110:0000 1111:0101 1001: mod xmmreg r/m
MULSD—Multiply Scalar Double Precision Floating-Point Values
   xmmreg2 to xmmreg1 1111 0010:00001111:01011001:11 xmmreg1 xmmreg2
   mem to xmmreg 1111 0010:00001111:01011001: mod xmmreg r/mORPD—Bitwise Logical OR of Double  Precision Floating-Point Values
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 0110:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0101 0110: mod xmmreg r/m
SHUFPD—Shuffle Packed Double Pr ecision Floating-Point Values
  xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8
  mem to xmmreg, imm8 0110 0110:0000 1111:1100 0110: mod xmmreg r/m: imm8
SQRTPD—Compute Square Roots of Packed Double Precision Floating-Point Values
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 0001:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:0101 0001: mod xmmreg r/m
SQRTSD—Compute Square Root of Scalar Double Precision Floating-Point Value
  xmmreg2 to xmmreg1 1111 0010:0000 1111:0101 0001:11 xmmreg1 xmmreg2
  mem to xmmreg 1111 0010:0000 1111:0101 0001: mod xmmreg r/m
SUBPD—Subtract Packed Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 1100:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0101 1100: mod xmmreg r/m
SUBSD—Subtract Scalar Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 1111 0010:0000 1111:0101 1100:11 xmmreg1 xmmreg2
  mem to xmmreg 1111 0010:0000 1111:0101 1100: mod xmmreg r/m
UCOMISD—Unordered Compare Scalar Ordered Double Precision Floating-Point  Values and Set EFLAGS
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0010 1110:11 xmmreg1 xmmreg2  mem to xmmreg 0110 0110:0000 1111:0010 1110: mod xmmreg r/m
UNPCKHPD—Unpack and Interleave High Packed  Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0001 0101:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:0001 0101: mod xmmreg r/m
UNPCKLPD—Unpack and Interleave Low Packed  Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0001 0100:11 xmmreg1 xmmreg2   mem to xmmreg 0110 0110:0000 1111:0001 0100: mod xmmreg r/m
XORPD—Bitwise Logical OR of Double  Precision Floating-Point Values
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0101 0111:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0101 0111: mod xmmreg r/mTable B-26.  Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format EncodingB-52 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
Table B-27.  Formats and Encodings of SSE2 Integer Instructions
MOVD—Move Doubleword   reg to xmmreg 0110 0110:0000 1111:0110 1110: 11 xmmreg reg
reg from xmmreg 0110 0110:0000 1111:0111 1110: 11 xmmreg reg
mem to xmmreg 0110 0110:0000 1111:0110 1110: mod xmmreg r/mmem from xmmreg 0110 0110:0000 1111:0111 1110: mod xmmreg r/m
MOVDQA—Move Aligned Double Quadword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0110 1111:11 xmmreg1 xmmreg2  xmmreg2 from xmmreg1 0110 0110:0000 1111:0111 1111:11 xmmreg1 xmmreg2
   mem to xmmreg 0110 0110:0000 1111:0110 1111: mod xmmreg r/m
   mem from xmmreg 0110 0110:0000 1111:0111 1111: mod xmmreg r/mMOVDQU—Move Unaligned Double Quadword  xmmreg2 to xmmreg1 1111 0011:0000 1111:0110 1111:11 xmmreg1 xmmreg2
xmmreg2 from xmmreg1 1111 0011:0000 1111:0111 1111:11 xmmreg1 xmmreg2
  mem to xmmreg 1111 0011:0000 1111:0110 1111: mod xmmreg r/m
   mem from xmmreg 1111 0011:0000 1111:0111 1111: mod xmmreg r/m
MOVQ2DQ—Move Quadword from MMX to XMM Register
   mmreg to xmmreg 1111 0011:0000 1111:1101 0110:11 mmreg1 mmreg2MOVDQ2Q—Move Quadword from XMM to MMX Register
   xmmreg to mmreg 1111 0010:0000 1111:1101 0110:11 mmreg1 mmreg2
MOVQ—Move Quadword
xmmreg2 to xmmreg1 1111 0011:0000 1111:0111 1110: 11 xmmreg1 xmmreg2
xmmreg2 from xmmreg1 0110 0110:0000 1111:1101 0110: 11 xmmreg1 xmmreg2
mem to xmmreg 1111 0011:0000 1111:0111 1110: mod xmmreg r/mmem from xmmreg 0110 0110:0000 1111:1101 0110: mod xmmreg r/m
PACKSSDW
1—Pack Dword To Word Data (signed with saturation)
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0110 1011: 11 xmmreg1 xmmreg2  memory to xmmreg 0110 0110:0000 1111:0110 1011: mod xmmreg r/m
PACKSSWB—Pack  Word To Byte Data (signed with saturation)
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0110 0011: 11 xmmreg1 xmmreg2
   memory to xmmreg 0110 0110:0000 1111:0110 0011: mod xmmreg r/m
PACKUSWB—Pack Word To Byte Da ta (unsigned with saturation)
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0110 0111: 11 xmmreg1 xmmreg2
  memory to xmmreg 0110 0110:0000 1111:0110 0111: mod xmmreg r/m
PADDQ—Add Packed Quadword Integers
   mmreg2 to mmreg1 0000 1111:1101 0100:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1101 0100: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1101 0100:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:1101 0100: mod xmmreg r/mVol. 2D B-53INSTRUCTION FORMATS AND ENCODINGS
PADD—Add With Wrap-around
  xmmreg2 to xmmreg1 0110 0110:0000 1111: 1111 11gg: 11 xmmreg1 xmmreg2
  memory to xmmreg 0110 0110:0000 1111: 1111 11gg: mod xmmreg r/m
PADDS—Add Signed With Saturation
  xmmreg2 to xmmreg1 0110 0110:0000 1111: 1110 11gg: 11 xmmreg1 xmmreg2
  memory to xmmreg 0110 0110:0000 1111: 1110 11gg: mod xmmreg r/m
PADDUS—Add Unsigned With Saturation  xmmreg2 to xmmreg1 0110 0110:0000 1111: 1101 11gg: 11 xmmreg1 xmmreg2
  memory to xmmreg 0110 0110:0000 1111: 1101 11gg: mod xmmreg r/m
PAND—Bitwise And  xmmreg2 to xmmreg1 0110 0110:0000 1111:1101 1011: 11 xmmreg1 xmmreg2  memory to xmmreg 0110 0110:0000 1111:1101 1011: mod xmmreg r/m
PANDN—Bitwise AndNot
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1101 1111: 11 xmmreg1 xmmreg2  memory to xmmreg 0110 0110:0000 1111:1101 1111: mod xmmreg r/m
PAVGB—Average Packed Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:11100 000:11 xmmreg1 xmmreg2  mem to xmmreg 01100110:00001111:11100000 mod xmmreg r/m
PAVGW—Average Packed Integers
   xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 0011:11 xmmreg1 xmmreg2  mem to xmmreg 0110 0110:0000 1111:1110 0011 mod xmmreg r/m
PCMPEQ—Packed Compare For Equality
  xmmreg1 with xmmreg2 0110 0110:0000 1111:0111 01gg: 11 xmmreg1 xmmreg2  xmmreg with memory 0110 0110:0000 1111:0111 01gg: mod xmmreg r/m
PCMPGT—Packed Compare Greater (signed)
  xmmreg1 with xmmreg2 0110 0110:0000 1111:0110 01gg: 11 xmmreg1 xmmreg2  xmmreg with memory 0110 0110:0000 1111:0110 01gg: mod xmmreg r/m
PEXTRW—Extract Word
  xmmreg to reg32, imm8 0110 0110:0000 1111:1100 0101:11 r32 xmmreg: imm8PINSRW—Insert Word
  reg32 to xmmreg, imm8 0110 0110:0000 1111:1100 0100:11 xmmreg r32: imm8
   m16 to xmmreg, imm8 0110 0110:0000 1111:1100 0100: mod xmmreg r/m: imm8PMADDWD—Packed Multiply Add
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1111 0101: 11 xmmreg1 xmmreg2
  memory to xmmreg 0110 0110:0000 1111:1111 0101: mod xmmreg r/mPMAXSW—Maximum of Packed  Signed Word Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 1110:11 xmmreg1 xmmreg2
  mem to xmmreg 01100110:00001111:11101110: mod xmmreg r/mTable B-27.  Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format EncodingB-54 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
PMAXUB—Maximum of Packed Unsigned Byte Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1101 1110:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:1101 1110: mod xmmreg r/m
PMINSW—Minimum of Packed Signed Word Integers  xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 1010:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:1110 1010: mod xmmreg r/m
PMINUB—Minimum of Packed Unsigned Byte Integers  xmmreg2 to xmmreg1 0110 0110:0000 1111:1101 1010:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:1101 1010 mod xmmreg r/m

xmmreg2 to xmmreg1 0110 0110:0000 1111:1111 0101: 11 xmmreg1 xmmreg2
PMOVMSKB—Move Byte Mask To Integer  xmmreg to reg32 0110 0110:0000 1111:1101 0111:11 r32 xmmregPMULHUW—Packed multiplication, store high word (unsigned)
   xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 0100: 11 xmmreg1 xmmreg2
   memory to xmmreg 0110 0110:0000 1111:1110 0100: mod xmmreg r/mPMULHW—Packed Multiplica tion, store high word
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 0101: 11 xmmreg1 xmmreg2
  memory to xmmreg 0110 0110:0000 1111:1110 0101: mod xmmreg r/m
PMULLW—Packed Multiplication, store low word
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1101 0101: 11 xmmreg1 xmmreg2
  memory to xmmreg 0110 0110:0000 1111:1101 0101: mod xmmreg r/m
PMULUDQ—Multiply Packed Unsigned Doubleword Integers
  mmreg2 to mmreg1 0000 1111:1111 0100:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:1111 0100: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:00001111:1111 0100:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:00001111:1111 0100: mod xmmreg r/m
POR—Bitwise Or   xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 1011: 11 xmmreg1 xmmreg2
 memory to xmmreg 0110 0110:0000 1111:1110 1011: mod xmmreg r/m
PSADBW—Compute Sum of Absolute Differences  xmmreg2 to xmmreg1 0110 0110:0000 1111:1111 0110:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:1111 0110: mod xmmreg r/m
PSHUFLW—Shuffle Packed Low Words  xmmreg2 to xmmreg1, imm8 1111 0010:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
  mem to xmmreg, imm8 1111 0010:0000 1111:0111 0000:11 mod xmmreg r/m: imm8
PSHUFHW—Shuffle Packed High Words  xmmreg2 to xmmreg1, imm8 1111 0011:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
  mem to xmmreg, imm8 1111 0011:0000 1111:0111 0000: mod xmmreg r/m: imm8
PSHUFD—Shuffle Packed DoublewordsTable B-27.  Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format EncodingVol. 2D B-55INSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
  mem to xmmreg, imm8 0110 0110:0000 1111:0111 0000: mod xmmreg r/m: imm8
PSLLDQ—Shift Double Quadword Left Logical
  xmmreg, imm8 0110 0110:0000 1111:0111 0011:11 111 xmmreg: imm8PSLL—Packed Shift Left Logical
  xmmreg1 by xmmreg2 0110 0110:0000 1111:1111 00gg: 11 xmmreg1 xmmreg2
  xmmreg by memory 0110 0110:0000 1111:1111 00gg: mod xmmreg r/m  xmmreg by immediate 0110 0110:0000 1111:0111 00gg: 11 110 xmmreg: imm8 
PSRA—Packed Shift Right Arithmetic
  xmmreg1 by xmmreg2 0110 0110:0000 1111:1110 00gg: 11 xmmreg1 xmmreg2  xmmreg by memory 0110 0110:0000 1111:1110 00gg: mod xmmreg r/m
  xmmreg by immediate 0110 0110:0000 1111:0111 00gg: 11 100 xmmreg: imm8 
PSRLDQ—Shift Double Quadword Right Logical
  xmmreg, imm8 0110 0110:00001111:01110011:11 011 xmmreg: imm8PSRL—Packed Shift Right Logical
  xmmreg1 by xmmreg2 0110 0110:0000 1111:1101 00gg: 11 xmmreg1 xmmreg2
  xmmreg by memory 0110 0110:0000 1111:1101 00gg: mod xmmreg r/m
  xmmreg by immediate 0110 0110:0000 1111:0111 00gg: 11 010 xmmreg: imm8 
PSUBQ—Subtract Packed Quadword Integers
  mmreg2 to mmreg1 0000 1111:11111 011:11 mmreg1 mmreg2
   mem to mmreg 0000 1111:1111 1011: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1111 1011:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:1111 1011: mod xmmreg r/mPSUB—Subtract With Wrap-around
  xmmreg2 from xmmreg1 0110 0110:0000 1111:1111 10gg: 11 xmmreg1 xmmreg2
  memory from xmmreg 0110 0110:0000 1111:1111 10gg: mod xmmreg r/mPSUBS—Subtract Signed With Saturation
  xmmreg2 from xmmreg1 0110 0110:0000 1111:1110 10gg: 11 xmmreg1 xmmreg2
  memory from xmmreg 0110 0110:0000 1111:1110 10gg: mod xmmreg r/mPSUBUS—Subtract Unsigned With Saturation
  xmmreg2 from xmmreg1 0000 1111:1101 10gg: 11 xmmreg1 xmmreg2
  memory from xmmreg 0000 1111:1101 10gg: mod xmmreg r/mPUNPCKH—Unpack High Data To Next Larger Type
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0110 10gg:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0110 10gg: mod xmmreg r/mPUNPCKHQDQ—Unpack High Data
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0110 1101:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0110 1101: mod xmmreg r/mTable B-27.  Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format EncodingB-56 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
PUNPCKL—Unpack Low Data To Next Larger Type
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0110 00gg:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0110 00gg: mod xmmreg r/m
PUNPCKLQDQ—Unpack Low Data
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0110 1100:11 xmmreg1 xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0110 1100: mod xmmreg r/m
PXOR—Bitwise Xor
xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 1111: 11 xmmreg1 xmmreg2
memory to xmmreg 0110 0110:0000 1111:1110 1111: mod xmmreg r/m
Table B-28.  Format and Encoding of SSE2 Cacheability Instructions
MASKMOVDQU—Store Selected Bytes of Double Quadword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:1111 0111:11 xmmreg1 xmmreg2
CLFLUSH—Flush Cache Line
  mem 0000 1111:1010 1110: mod 111 r/m
MOVNTPD—Store Packed Double Precision Floa ting-Point Values Using Non-Temporal Hint
  xmmreg to mem 0110 0110:0000 1111:0010 1011: mod xmmreg r/m
MOVNTDQ—Store Double Quadword Using Non-Temporal Hint  xmmreg to mem 0110 0110:0000 1111:1110 0111: mod xmmreg r/m
MOVNTI—Store Doubleword Using Non-Temporal Hint
  reg to mem 0000 1111:1100 0011: mod reg r/mPAUSE—Spin Loop Hint 1111 0011:1001 0000
LFENCE—Load Fence 0000 1111:1010 1110: 11 101 000
MFENCE—Memory Fence 0000 1111:1010 1110: 11 110 000Table B-27.  Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format EncodingVol. 2D B-57INSTRUCTION FORMATS AND ENCODINGS
B.10 SSE3 FORMATS AND ENCODINGS TABLE
The tables in this section provide SSE3 formats and encodi ngs. Some SSE3 instructions require a mandatory prefix 
(66H, F2H, F3H) as part of the two-byte opco de. These prefixes are included in the tables.
When in IA-32e mode, use of the REX.R prefix permits instructions that use general purpose and XMM registers to 
access additional registers. Some instructions require the REX.W prefix to promote the instruction to 64-bit opera-
tion. Instructions that require the REX.W prefix  are listed (with their opcodes) in Section B.13.
Table B-29.  Formats and Encodings of SSE3 Floating-Point Instructions
ADDSUBPD—Add /Sub packed DP FP numbers from XMM2/Mem to XMM1
xmmreg2 to xmmreg1 01100110:00001111:11010000:11 xmmreg1 xmmreg2mem to xmmreg 01100110:00001111:11010000: mod xmmreg r/m
ADDSUBPS—Add /Sub packed SP FP  numbers from XMM2/Mem to XMM1
xmmreg2 to xmmreg1 11110010:00001111:11010000:11 xmmreg1 xmmreg2mem to xmmreg 11110010:00001111:11010000: mod xmmreg r/mHADDPD—Add horizontally packed DP  FP numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1 01100110:00001111:01111100:11 xmmreg1 xmmreg2
mem to xmmreg 01100110:00001111:01111100: mod xmmreg r/mHADDPS—Add horizontally packed SP  FP numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1 11110010:00001111:01111100:11 xmmreg1 xmmreg2
mem to xmmreg 11110010:00001111:01111100: mod xmmreg r/mHSUBPD—Sub horizontally  packed DP FP numbers XMM2/Mem to XMM1 
xmmreg2 to xmmreg1 01100110:00001111:01111101:11 xmmreg1 xmmreg2
mem to xmmreg 01100110:00001111:01111101: mod xmmreg r/mHSUBPS—Sub horizontally packed SP FP numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1 11110010:00001111:01111101:11 xmmreg1 xmmreg2
mem to xmmreg 11110010:00001111:01111101: mod xmmreg r/m
Table B-30.  Formats and Encodings for SSE3 Event Management Instructions 
MONITOR—Set up a linear address ra nge to be monitored by hardware
eax, ecx, edx 0000 1111 : 0000 0001:11 001 000
MWAIT—Wait until write-back store performed within the range specified by the instruction MONITOR
eax, ecx 0000 1111 : 0000 0001:11 001 001
Table B-31.  Formats and Encodings for SSE3 Integer and Move Instructions 
FISTTP—Store ST in int16 (chop) and pop
m16int 11011 111 : modA 001 r/m
FISTTP—Store ST in int32 (chop) and pop
m32int 11011 011 : modA 001 r/m
FISTTP—Store ST in int64 (chop) and popB-58 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.11 SSSE3 FORMATS AND ENCODING TABLE
The tables in this section provide SSSE3 formats and en codings. Some SSSE3 instructions require a mandatory 
prefix (66H) as part of the three-byte opcode. These prefixes are included in the table below.
 m64int 11011 101 : modA 001 r/m
LDDQU—Load unaligned integer 128-bit
xmm, m128 11110010:00001111:11110000: modA xmmreg r/m
MOVDDUP—Move 64 bits represen ting one DP data from XMM2/Mem to XMM1 and duplicate
xmmreg2 to xmmreg1 11110010:00001111:00010010:11 xmmreg1 xmmreg2
mem to xmmreg 11110010:00001111:00010010: mod xmmreg r/m
MOVSHDUP—Move 128 bits represen ting 4 SP data from XMM2/Mem to XMM1 and duplicate high
xmmreg2 to xmmreg1 11110011:00001111:00010110:11 xmmreg1 xmmreg2
mem to xmmreg 11110011:00001111:00010110: mod xmmreg r/m
MOVSLDUP—Move 128 bits representing 4 SP data  from XMM2/Mem to XMM1 and duplicate low

xmmreg2 to xmmreg1 11110011:00001111:00010010:11 xmmreg1 xmmreg2mem to xmmreg 11110011:00001111:00010010: mod xmmreg r/m
Table B-32.  Formats and En codings for SSSE 3 Instructions
PABSB—Packed Absolute Value Bytes
   mmreg2 to mmreg1 0000 1111:0011 1000: 0001 1100:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0001 1100: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0001 1100:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0001 1100: mod xmmreg r/m
PABSD—Packed Absolute Value Double Words
   mmreg2 to mmreg1 0000 1111:0011 1000: 0001 1110:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0001 1110: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0001 1110:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0001 1110: mod xmmreg r/m
PABSW—Packed Absolute Value Words   mmreg2 to mmreg1 0000 1111:0011 1000: 0001 1101:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0001 1101: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0001 1101:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0001 1101: mod xmmreg r/m
PALIGNR—Packed Align Right
   mmreg2 to mmreg1, imm8 0000 1111:0011 1010: 0000 1111:11 mmreg1 mmreg2: imm8Table B-31.  Formats and Encodings for SSE3 Integer and Move Instructions  (Contd.)
Instruction and Format EncodingVol. 2D B-59INSTRUCTION FORMATS AND ENCODINGS
  mem to mmreg, imm8 0000 1111:0011 1010: 0000 1111: mod mmreg r/m: imm8
  xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0000 1111:11 xmmreg1 
xmmreg2: imm8
  mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0000 1111: mod xmmreg r/m: 
imm8
PHADDD—Packed Horizontal Add Double Words
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 0010:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 0010: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 0010:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0010: mod xmmreg r/m
PHADDSW—Packed Horizontal Add and Saturate
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 0011:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 0011: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 0011:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0011: mod xmmreg r/m
PHADDW—Packed Horizontal Add Words
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 0001:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 0001: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 0001:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0001: mod xmmreg r/m
PHSUBD—Packed Horizontal Subtract Double Words
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 0110:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 0110: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 0110:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0110: mod xmmreg r/m
PHSUBSW—Packed Horizontal Subtract and Saturate   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 0111:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 0111: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 0111:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0111: mod xmmreg r/m
PHSUBW—Packed Horizontal Subtract Words
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 0101:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 0101: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 0101:11 xmmreg1 
xmmreg2Table B-32.  Formats and Encoding s for SSSE3 Instructions (Contd.)
Instruction and Format EncodingB-60 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.12 AESNI AND PCLMULQDQ INSTRUCTION FORMATS AND ENCODINGS 
Table B-33 shows the formats and encodings for AESNI and PCLMULQDQ instructions.  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0101: mod xmmreg r/m
PMADDUBSW—Multiply and Add Packed Signed and Unsigned Bytes
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 0100:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 0100: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 0100:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0100: mod xmmreg r/m
PMULHRSW—Packed Multiply HIgn with Round and Scale
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 1011:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 1011: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 1011:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1011: mod xmmreg r/m
PSHUFB—Packed Shuffle Bytes
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 0000:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 0000: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 0000:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0000: mod xmmreg r/m
PSIGNB—Packed Sign Bytes   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 1000:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 1000: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 1000:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1000: mod xmmreg r/m
PSIGND—Packed Sign Double Words
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 1010:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 1010: mod mmreg r/m  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 1010:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1010: mod xmmreg r/m
PSIGNW—Packed Sign Words
   mmreg2 to mmreg1 0000 1111:0011 1000: 0000 1001:11 mmreg1 mmreg2
  mem to mmreg 0000 1111:0011 1000: 0000 1001: mod mmreg r/m
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0000 1001:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1001: mod xmmreg r/mTable B-32.  Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format EncodingVol. 2D B-61INSTRUCTION FORMATS AND ENCODINGS
  
B.13 SPECIAL ENCODINGS FOR 64-BIT MODE
The following Pentium, P6, MMX, SSE, SSE2, SSE3 instru ctions are promoted to 64-bit operation in IA-32e mode 
by using REX.W. However, these entries are special cases th at do not follow the general rules (specified in Section 
B.4).Table B-33.  Formats and Encodings of AESNI and PCLMULQDQ Instructions
AESDEC—Perform One Round of  an AES Decryption Flow
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000:1101 1110:11 xmmreg1 
xmmreg2 
   mem to xmmreg 0110 0110:0000 1111:0011 1000:1101 1110: mod xmmreg r/m
AESDECLAST—Perform Last Round of an AES Decryption Flow
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000:1101 1111:11 xmmreg1 
xmmreg2 
   mem to xmmreg 0110 0110:0000 1111:0011 1000:1101 1111:  mod xmmreg r/mAESENC—Perform One Round of  an AES Encryption Flow
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000:1101 1100:11 xmmreg1 
xmmreg2 
   mem to xmmreg 0110 0110:0000 1111:0011 1000:1101 1100:  mod xmmreg r/m
AESENCLAST—Perform Last Round  of an AES Encryption Flow
   xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000:1101 1101:11 xmmreg1 
xmmreg2 
   mem to xmmreg 0110 0110:0000 1111:0011 1000:1101 1101:  mod xmmreg r/mAESIMC—Perform the AES In vMixColumn Transformation
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000:1101 1011:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000:1101 1011: mod xmmreg r/m
AESKEYGENASSIST—AES Round Key Generation Assist   xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010:1101 1111:11 xmmreg1 
   mem to xmmreg, imm8 0110 0110:0000 11 11:0011 1010:1101 1111: mod xmmreg r/m: 
imm8
PCLMULQDQ—Carry-Less Multiplication Quadword
   xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010:0100 0100:11 xmmreg1 
xmmreg2: imm8 
   mem to xmmreg, imm8 0110 0110:0000 1111 :0011 1010:0100 0100:  mod xmmreg r/m: 
imm8
Table B-34.  Special Case Inst ructions Promoted Using REX.W
CMOVcc—Conditional MoveB-62 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
register2 to  register1 0100 0R0B 0000 1111: 0100 tttn : 11 reg1 reg2
qwordregister2 to qwordregister1 0100 1R0B 0000 1111: 0100 tttn : 11 qwordreg1 qwordreg2
memory to register  0100 0RXB 0000 1111 : 0100 tttn : mod reg r/m
memory64 to qwordregister 0100 1RXB 0000 1111 : 0100 tttn : mod qwordreg r/m
CVTSD2SI—Convert Scalar Doub le Precision Floating-Point Value to Doubleword Integer
  xmmreg to r32 0100 0R0B 1111 0010:0000 1111:0010 1101:11 r32 
xmmreg
  xmmreg to r64 0100 1R0B 1111 0010:0000 1111:0010 1101:11 r64 
xmmreg
  mem64 to r32 0100 0R0XB 1111 0010:0000 1111:0010 1101: mod r32 r/m
  mem64 to r64 0100 1RXB 1111 0010:0000 1111:0010 1101: mod r64 r/mCVTSI2SS—Convert Doubleword Integer to Scal ar Single Precision Floating-Point Value
  r32 to xmmreg1 0100 0R0B 1111 0011:0000 1111:0010 1010:11 xmmreg 
r32
  r64 to xmmreg1 0100 1R0B 1111 0011:0000 1111:0010 1010:11 xmmreg 
r64
  mem to xmmreg 0100 0RXB 1111 0011:0000 1111:0010 1010: mod xmmreg 
r/m

xmmreg
xmmreg
r32
r64
r/m
  mem64 to xmmreg 0100 1RXB 1111 0011:0000 1111:0010 1010: mod xmmreg 
r/m
  r32 to xmmreg1 0100 0R0B 1111 0010:0000 1111:0010 1010:11 xmmreg 
r32
  r64 to xmmreg1 0100 1R0B 1111 0010:0000 1111:0010 1010:11 xmmreg 
r64
  mem to xmmreg 0100 0RXB 1111 0010:0000 1111:00101 010: mod xmmreg 
r/m
  mem64 to xmmreg 0100 1RXB 1111 0010:0000 1111:0010 1010: mod xmmreg 
r/m
  xmmreg to r32 0100 0R0B 1111 0011:0000 1111:0010 1101:11 r32 
xmmreg
  xmmreg to r64 0100 1R0B 1111 0011:0000 1111:0010 1101:11 r64 
xmmreg
  mem to r32 0100 0RXB 11110011:00001111:00101101: mod r32 r/m  mem32 to r64 0100 1RXB 1111 0011:0000 1111:0010 1101: mod r64 r/m
  xmmreg to r32 0100 0R0B 11110010:00001111:00101100:11 r32 xmmreg
  xmmreg to r64 0100 1R0B 1111 0010:0000 1111:0010 1100:11 r64 
xmmreg
  mem64 to r32 0100 0RXB 1111 0010:0000 1111:0010 1100: mod r32 r/m  mem64 to r64 0100 1RXB 1111 0010:0000 1111:0010 1100: mod r64 r/mTable B-34.  Special Case Instruct ions Promoted Us ing REX.W (Contd.)
Instruction and Format EncodingVol. 2D B-63INSTRUCTION FORMATS AND ENCODINGS
  xmmreg to r32 0100 0R0B 1111 0011:0000 1111:0010 1100:11 r32 
xmmreg1
  xmmreg to r64 0100 1R0B 1111 0011:0000 1111:0010 1100:11 r64 
xmmreg1
  mem to r32 0100 0RXB 1111 0011:0000 1111:0010 1100: mod r32 r/m
  mem32 to r64 0100 1RXB 1111 0011:0000 1111:0010 1100: mod r64 r/m
MOVD/MOVQ—Move doubleword
reg to mmxreg 0100 0R0B 0000 1111:0110 1110: 11 mmxreg reg
qwordreg to mmxreg 0100 1R0B 0000 1111:0110 1110: 11 mmxreg qwordreg
reg from mmxreg 0100 0R0B 0000 1111:0111 1110: 11 mmxreg regqwordreg from mmxreg 0100 1R0B 0000  1111:0111 1110: 11 mmxreg qwordreg
mem to mmxreg 0100 0RXB 0000 1111:0110 1110: mod mmxreg r/m
mem64 to mmxreg 0100 1RXB 0000 1111:0110 1110: mod mmxreg r/m
mem from mmxreg 0100 0RXB 0000 1111:0111 1110: mod mmxreg r/mmem64 from mmxreg 0100 1RXB 0000 1111:0111 1110: mod mmxreg r/m
mmxreg with memory 0100 0RXB 0000 1111:0110 01gg: mod mmxreg r/m
MOVMSKPS—Extract Packed Single Pr ecision Floating-Point Sign Mask
  xmmreg to r32 0100 0R0B 0000 1111:0101 0000:11 r32 xmmreg
  xmmreg to r64 0100 1R0B 00001111:01010000:11 r64 xmmreg
PEXTRW—Extract Word  mmreg to reg32, imm8 0100 0R0B 0000 1111:1100 0101:11 r32 mmreg: imm8
  mmreg to reg64, imm8 0100 1R0B 0000 1111:1100 0101:11 r64 mmreg: imm8
  xmmreg to reg32, imm8 0100 0R0B 0110 0110 0000 1111:1100 0101:11 r32 
xmmreg: imm8
  xmmreg to reg64, imm8 0100 1R0B 0110 0110 0000 1111:1100 0101:11 r64 
PINSRW—Insert Word  reg32 to mmreg, imm8 0100 0R0B 00 00 1111:1100 0100:11 mmreg r32: imm8
  reg64 to mmreg, imm8 0100 1R0B 00 00 1111:1100 0100:11 mmreg r64: imm8
  m16 to mmreg, imm8 0100 0R0B 0000 1111:1100 0100 mod mmreg r/m: imm8  m16 to mmreg, imm8 0100 1RXB 0000 1111:11000100 mod mmreg r/m: imm8
  reg32 to xmmreg, imm8 0100 0RXB 0110 0110 0000 1111:1100 0100:11 xmmreg 
r32: imm8
  reg64 to xmmreg, imm8 0100 0RXB 0110 0110 0000 1111:1100 0100:11 xmmreg 
r64: imm8
  m16 to xmmreg, imm8 0100 0RXB 0110 0110 0000 1111:1100 0100 mod xmmreg 
r/m: imm8
  m16 to xmmreg, imm8 0100 1RXB 0110 0110 0000 1111:1100 0100 mod xmmreg 
r/m: imm8
PMOVMSKB—Move Byte Mask To IntegerTable B-34.  Special Ca se Instructions Promot ed Using REX.W (Contd.)
Instruction and Format EncodingB-64 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.14 SSE4.1 FORMATS AND ENCODING TABLE
The tables in this section provide SSE4.1 formats and en codings. Some SSE4.1 instructions require a mandatory 
prefix (66H, F2H, F3H) as part of the three-byte opcode. These prefixes are included in the tables. 
In 64-bit mode, some instructions requires REX.W, the by te sequence of REX.W prefix in the opcode sequence is 
shown.   mmreg to reg32 0100 0RXB 0000 1111:1101 0111:11 r32 mmreg
   mmreg to reg64 0100 1R0B 0000 1111:1101 0111:11 r64 mmreg
   xmmreg to reg32 0100 0RXB 0110 0110 0000 1111:1101 0111:11 r32 mmreg
   xmmreg to reg64 0110 0110 0000 1111:1101 0111:11 r64 xmmreg
Table B-35.  Encodings of SSE4.1 instructions
BLENDPD — Blend Packed Double Precision Floats
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1010: 0000 1101:11 xmmreg1 
xmmreg2
 mem to xmmreg 0110 0110:0000 1111:0011 1010: 0000 1101: mod xmmreg r/m
BLENDPS — Blend Packed Single Precision Floats
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1010: 0000 1100:11 xmmreg1 
xmmreg2
 mem to xmmreg 0110 0110:0000 1111:0011 1010: 0000 1100: mod xmmreg r/m
BLENDVPD — Variable Blend Packed Double Precision Floats
 xmmreg2 to xmmreg1 <xmm0> 0110 0110:0000 1111:0011 1000: 0001 0101:11 xmmreg1 
xmmreg2
 mem to xmmreg <xmm0> 0110 0110:0000 1111:0011 1000: 0001 0101: mod xmmreg r/m
BLENDVPS — Variable Blend Pa cked Single Precision Floats
 xmmreg2 to xmmreg1 <xmm0> 0110 0110:0000 1111:0011 1000: 0001 0100:11 xmmreg1 
xmmreg2
 mem to xmmreg <xmm0> 0110 0110:0000 1111:0011 1000: 0001 0100: mod xmmreg r/m
DPPD — Packed Double Precision Dot Products
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0100 0001:11 xmmreg1 
 mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0100 0001: mod xmmreg r/m: 
imm8
DPPS — Packed Single Precision Dot Products
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0100 0000:11 xmmreg1 
 mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0100 0000: mod xmmreg r/m: 
imm8
EXTRACTPS — Extract From Pack ed Single Precision Floats
  reg from xmmreg , imm8 0110 0110:0000 1111:0011 1010: 0001 0111:11 xmmreg reg: 
imm8Table B-34.  Special Case Instruct ions Promoted Us ing REX.W (Contd.)
Instruction and Format EncodingVol. 2D B-65INSTRUCTION FORMATS AND ENCODINGS
 mem from xmmreg , imm8 0110 0110:0000 1111:0011 1010: 0001 0111: mod xmmreg r/m: 
imm8
INSERTPS — Insert Into Pack ed Single Precision Floats
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0010 0001:11 xmmreg1 
 mem to xmmreg, imm8 0110 0110:0000 1111 :0011 1010: 0010 0001: mod xmmreg r/m: 
imm8
MOVNTDQA — Load Double Quadword Non-temporal Aligned
 m128 to xmmreg 0110 0110:0000 1111:0011 1000: 0010 1010:11 r/m xmmreg2
MPSADBW — Multiple Packed Sums of Absolute Difference
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0100 0010:11 xmmreg1 
 mem to xmmreg, imm8 0110 0110:0000 1111 :0011 1010: 0100 0010: mod xmmreg r/m: 
imm8
PACKUSDW — Pack with  Unsigned Saturation
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 1011:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 1011: mod xmmreg r/m
PBLENDVB — Variable Blend Packed Bytes
 xmmreg2 to xmmreg1 <xmm0> 0110 0110:0000 1111:0011 1000: 0001 0000:11 xmmreg1 
xmmreg2
 mem to xmmreg <xmm0> 0110 0110:0000 1111:0011 1000: 0001 0000: mod xmmreg r/m
PBLENDW — Blend Packed Words
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0001 1110:11 xmmreg1 
 mem to xmmreg, imm8 0110 0110:0000 1111 :0011 1010: 0000 1110: mod xmmreg r/m: 
imm8
PCMPEQQ — Compare Packed Qword Data of Equal
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 1001:11 xmmreg1 
xmmreg2
 mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 1001: mod xmmreg r/m
PEXTRB — Extract Byte
 reg from xmmreg , imm8 0110 0110:0000 1111:0011 1010: 0001 0100:11 xmmreg reg: 
imm8
 xmmreg to mem, imm8 0110 0110:0000 1111:0011 1010: 0001 0100: mod xmmreg r/m: 
imm8
PEXTRD — Extract DWord
 reg from xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0001 0110:11 xmmreg reg: 
imm8
 xmmreg to mem, imm8 0110 0110:0000 1111:0011 1010: 0001 0110: mod 
xmmreg r/m: imm8Table B-35.  Encodings of SSE4.1 instructions
Instruction and Format EncodingB-66 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
PEXTRQ — Extract QWord
 r64 from xmmreg, imm8 0110 0110:REX.W:0000 1111:0011 1010: 0001 0110:11 xmmreg 
reg: imm8
 m64 from xmmreg, imm8 0110 0110:REX.W:0000 1111:0011 1010: 0001 0110: mod 
xmmreg r/m: imm8
PEXTRW — Extract Word
 reg from xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0001 0101:11 reg xmmreg: 
imm8
  mem from xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0001 0101: mod xmmreg r/m: 
imm8
PHMINPOSUW — Packed Horizontal Word Minimum
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0100 0001:11 xmmreg1 
xmmreg2
 mem to xmmreg 0110 0110:0000 1111:0011 1000: 0100 0001: mod xmmreg r/m
PINSRB — Extract Byte
  reg to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0010 0000:11 xmmreg reg: 
imm8
 mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0010 0000: mod xmmreg r/m: 
imm8
PINSRD — Extract DWord
 reg to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0010 0010:11 xmmreg reg: 
imm8
 mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0010 0010: mod xmmreg r/m: 
imm8
PINSRQ — Extract QWord
 r64 to xmmreg, imm8 0110 0110:REX.W:0000 1111:0011 1010: 0010 0010:11 xmmreg 
reg: imm8

reg: imm8
imm8
imm8
xmmreg2
imm8
imm8
imm8
imm8
reg: imm8
 m64 to xmmreg, imm8 0110 0110:REX.W:0000 1111:0011 1010: 0010 0010: mod 
PMAXSB — Maximum of Packed Signed Byte Integers
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 1100:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 1100: mod xmmreg r/m
PMAXSD — Maximum of Packed Signed Dword Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 1101:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 1101: mod xmmreg r/m
PMAXUD — Maximum of Packed Unsigned Dword Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 1111:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 1111: mod xmmreg r/m
PMAXUW — Maximum of Packed Unsigned Word IntegersTable B-35.  Encodings of SSE4.1 instructions
Instruction and Format EncodingVol. 2D B-67INSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 1110:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 1110: mod xmmreg r/m
PMINSB — Minimum of Packed Signed Byte Integers
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 1000:11 xmmreg1 
xmmreg2
 mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 1000: mod xmmreg r/m
PMINSD — Minimum of Pack ed Signed Dword Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 1001:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 1001: mod xmmreg r/m
PMINUD — Minimum of Packed  Unsigned Dword Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 1011:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 1011: mod xmmreg r/m
PMINUW — Minimum of Packed  Unsigned Word Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 1010:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 1010: mod xmmreg r/m
PMOVSXBD — Packed Move Sign Extend - Byte to Dword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 0001:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 0001: mod xmmreg r/m
PMOVSXBQ — Packed Move Sign Extend - Byte to Qword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 0010:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 0010: mod xmmreg r/m
PMOVSXBW — Packed Move Sign Extend - Byte to Word
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 0000:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 0000: mod xmmreg r/m
PMOVSXWD — Packed Move Sign Extend - Word to Dword
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 0011:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 0011: mod xmmreg r/m
PMOVSXWQ — Packed Move Sign Extend - Word to Qword
 xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 0100:11 xmmreg1 
xmmreg2
 mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 0100: mod xmmreg r/m
PMOVSXDQ — Packed Move Sign Extend - Dword to Qword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 0101:11 xmmreg1 
xmmreg2Table B-35.  Encodings of SSE4.1 instructions
Instruction and Format EncodingB-68 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 0101: mod xmmreg r/m
PMOVZXBD — Packed Move Zero Extend - Byte to Dword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 0001:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 0001: mod xmmreg r/m
PMOVZXBQ — Packed Move Zero Extend - Byte to Qword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 0010:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 0010: mod xmmreg r/m
PMOVZXBW — Packed Move Zero Extend - Byte to Word
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 0000:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 0000: mod xmmreg r/m
PMOVZXWD — Packed Move Zero Extend - Word to Dword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 0011:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 0011: mod xmmreg r/m
PMOVZXWQ — Packed Move Zero Extend - Word to Qword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 0100:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 0100: mod xmmreg r/m
PMOVZXDQ — Packed Move Zero Extend - Dword to Qword
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0011 0101:11 xmmreg1 
xmmreg2
 mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 0101: mod xmmreg r/m
PMULDQ — Multiply Packed Signed Dword Integers
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0010 1000:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0010 1000: mod xmmreg r/m
PMULLD — Multiply Packed Signed Dword Integers, Store low Result
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0100 0000:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0100 0000: mod xmmreg r/m
PTEST — Logical Compare
  xmmreg2 to xmmreg1 0110 0110:0000 1111:0011 1000: 0001 0111:11 xmmreg1 
xmmreg2
  mem to xmmreg 0110 0110:0000 1111:0011 1000: 0001 0111: mod xmmreg r/m
ROUNDPD — Round Packed Double Precision Values
  xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0000 1001:11 xmmreg1 
  mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0000 1001: mod xmmreg r/m: 
imm8Table B-35.  Encodings of SSE4.1 instructions
Instruction and Format EncodingVol. 2D B-69INSTRUCTION FORMATS AND ENCODINGS
B.15 SSE4.2 FORMATS AND ENCODING TABLE
The tables in this section provide SSE4.2 formats and en codings. Some SSE4.2 instructions require a mandatory 
prefix (66H, F2H, F3H) as part of th e three-byte opcode. These prefixes are included in the tables. In 64-bit mode, 
some instructions requires REX.W, the byte sequence  of REX.W prefix in the opcode sequence is shown.ROUNDPS — Round Packed Single Precision Values
  xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0000 1000:11 xmmreg1 
  mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0000 1000: mod xmmreg r/m: 
imm8
ROUNDSD — Round Scalar Double Precision Value
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0000 1011:11 xmmreg1 
  mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0000 1011: mod xmmreg r/m: 
imm8
ROUNDSS — Round Scalar Single Precision Value
  xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0000 1010:11 xmmreg1 
  mem to xmmreg, imm8 0110 0110:0000 1111:0011 1010: 0000 1010: mod xmmreg r/m: 
imm8
Table B-36.  Encodings of SSE4.2 instructions
CRC32 — Accumulate CRC32
 reg2 to reg1 1111 0010:0000 1111:0011 1000: 1111 000w :11 reg1 reg2
 mem to reg 1111 0010:0000 1111:0011 1000: 1111 000w : mod reg r/m bytereg2 to reg1 1111 0010:0100 WR0B:0000 1111:0011 1000: 1111 0000 :11 
reg1 bytereg2
 m8 to reg 1111 0010:0100 WR0B:0000 1111:0011 1000: 1111 0000 : mod 
reg r/m
 qwreg2 to qwreg1 1111 0010:0100 1R0B:0000 1111:0011 1000: 1111 0001 :11 
qwreg1 qwreg2
 mem64 to qwreg 1111 0010:0100 1R0B:0000 1111:0011 1000: 1111 0001 : mod 
qwreg r/m
PCMPESTRI— Packed Compare Explicit-Length Strings To Index
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0110 0001:11 xmmreg1 
 mem to xmmreg 0110 0110:0000 1111:0011 1010: 0110 0001: mod xmmreg r/m
PCMPESTRM— Packed Compare Explicit-Length Strings To Mask
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0110 0000:11 xmmreg1 
xmmreg2: imm8Table B-35.  Encodings of SSE4.1 instructions
Instruction and Format EncodingB-70 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.16 AVX FORMATS AND ENCODING TABLE
The tables in this section provide AVX formats and encodings. A mixed form of bit/hex/symbolic forms are used to 
express the various bytes:
The C4/C5 and opcode bytes are expressed in hex notation; the first and second payload byte of VEX, the modR/M 
byte is expressed in combination of bi t/symbolic form. The first payload byte of C4 is expressed as combination of 
bits and hex form, with the hex value preceded by an un derscore. The VEX bit field to encode upper register 8-15 
uses 1’s complement form, each of those bit field is expressed as lower case notation rxb, instead of RXB.
The hybrid bit-nibble-byte form is depicted below: mem to xmmreg 0110 0110:0000 1111:0011 1010: 0110 0000: mod xmmreg r/m
PCMPISTRI— Packed Compare Impl icit-Length String To Index
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0110 0011:11 xmmreg1 
 mem to xmmreg 0110 0110:0000 1111:0011 1010: 0110 0011: mod xmmreg r/m
PCMPISTRM— Packed Compare Implicit-Length Strings To Mask
 xmmreg2 to xmmreg1, imm8 0110 0110:0000 1111:0011 1010: 0110 0010:11 xmmreg1 
 mem to xmmreg 0110 0110:0000 1111:0011 1010: 0110 0010: mod xmmreg r/m
PCMPGTQ— Packed Compare Greater Than
 xmmreg to xmmreg 0110 0110:0000 1111:0011 1000: 0011 0111:11 xmmreg1 
xmmreg2
 mem to xmmreg 0110 0110:0000 1111:0011 1000: 0011 0111: mod xmmreg r/m
POPCNT— Return Number of Bits Set to 1
 reg2 to reg1 1111 0011:0000 1111:1011 1000:11 reg1 reg2

xmmreg2
 mem to reg1 1111 0011:0000 1111:1011 1000:mod reg1 r/m
 qwreg2 to qwreg1 1111 0011:0100 1R0B:0000 1111:1011 1000:11 reg1 reg2 mem64 to qwreg1 1111 0011:0100 1R0B:0000 1111:1011 1000:mod reg1 r/m
Figure B-2.  Hybrid Notation of  VEX-Encoded Key Instruction BytesTable B-36.  Encodings of SSE4.2 instructions
7 6 ----3 2 1 0 hex notation 7-6     5-3     2-0
R srcreg Lp p Opcode byte Mod   Reg*  R/M C5
7 6 ----3 2 1 0
W srcreg L ppTwo-Byte VEXhex notation
7 6 5 hex notation 7-6     5-3     2-0
R X B Opcode byte Mod   Reg R/M C44 ----- 0
0_hex 
mmmmm
Three-Byte VEXVol. 2D B-71INSTRUCTION FORMATS AND ENCODINGS
Table B-37.  Encodings of AVX instructions
VBLENDPD — Blend Packed Double Precision Floats
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_3: w xmmreg2 001:0D:11 xmmreg1 xmmreg3: imm xmmreg2 with mem to xmmreg1 C4: rxb0_3: w xmmreg2 001:0D:mod xmmreg1 r/m: imm
 ymmreg2 with ymmreg3 into ymmreg1 C4: rxb0_3: w ymmreg2 101:0D:11 ymmreg1 ymmreg3: imm
 ymmreg2 with mem to ymmreg1 C4: rxb0_3: w ymmreg2 101:0D:mod ymmreg1 r/m: imm
VBLENDPS — Blend Packed Single Precision Floats
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_3: w xmmreg2 001:0C:11 xmmreg1 xmmreg3: imm
 xmmreg2 with mem to xmmreg1 C4: rxb0_3: w xmmreg2 001:0C:mod xmmreg1 r/m: imm ymmreg2 with ymmreg3 into ymmreg1 C4: rxb0_3: w ymmreg2 101:0C:11 ymmreg1 ymmreg3: imm
 ymmreg2 with mem to ymmreg1 C4: rxb0_3: w ymmreg2 101:0C:mod ymmreg1 r/m: imm
VBLENDVPD — Variable Blend Pa cked Double Precision Floats
 xmmreg2 with xmmreg3 into xmmreg1 using xmmreg4 as 
maskC4: rxb0_3: 0 xmmreg2 001:4B:11 xmmreg1 xmmreg3: xmmreg4
 xmmreg2 with mem to xmmreg1 using xmmreg4 as mask C4 : rxb0_3: 0 xmmreg2 001:4B:mod xmmreg1 r/m: xmmreg4
 ymmreg2 with ymmreg3 into ymmreg1 using ymmreg4 as 
maskC4: rxb0_3: 0 ymmreg2 101:4B:11  ymmreg1 ymmreg3: ymmreg4
 ymmreg2 with mem to ymmreg1 using ymmreg4 as mask C4: rxb0_3: 0 ymmreg2 101:4B:mod ymmreg1 r/m: ymmreg4
VBLENDVPS — Variable Blend Packed Single Precision Floats
maskC4: rxb0_3: 0 xmmreg2 001:4A: 11 xmmreg1 xmmreg3: xmmreg4
 xmmreg2 with mem to xmmreg1 using xmmreg4 as mask C4 : rxb0_3: 0 xmmreg2 001:4A:mod xmmreg1 r/m: xmmreg4
maskC4: rxb0_3: 0 ymmreg2 101:4A:11  ymmreg1 ymmreg3: ymmreg4
 ymmreg2 with mem to ymmreg1 using ymmreg4 as mask C4: rxb0_3: 0 ymmreg2 101:4A:mod ymmreg1 r/m: ymmreg4
VDPPD — Packed Double Precision Dot Products
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_3: w xmmreg2 001:41:11 xmmreg1 xmmreg3: imm xmmreg2 with mem to xmmreg1 C4: rxb0_3: w xmmreg2 001:41:mod xmmreg1 r/m: imm
VDPPS — Packed Single Precision Dot Products
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_3: w xmmreg2 001:40:11 xmmreg1 xmmreg3: imm xmmreg2 with mem to xmmreg1 C4: rxb0_3: w xmmreg2 001:40:mod xmmreg1 r/m: imm
 ymmreg2 with ymmreg3 into ymmreg1 C4: rxb0 _3: w ymmreg2 101:40:11 ymmreg1 ymmreg3: imm
 ymmreg2 with mem to ymmreg1 C4: rxb0_3: w ymmreg2 101:40:mod ymmreg1 r/m: imm
VEXTRACTPS — Extract From Pa cked Single Precision Floats
 reg from xmmreg1 using imm C4: rxb0_3: w_F 001:17:11 xmmreg1 reg: imm
 mem from xmmreg1 using imm C4: rxb0_3: w_F 001:17:mod xmmreg1 r/m: imm
VINSERTPS — Insert Into Packed Single Precision Floats
 use imm to merge xmmreg3 with xmmreg2 into xmmreg1 C4: rxb0_3: w xmmreg2 001:21:11 xmmreg1 xmmreg3: imm
 use imm to merge mem with xmmreg2 into xmmreg1 C 4: rxb0_3: w xmmreg2 001:21:mod xmmreg1 r/m: imm
VMOVNTDQA — Load Double Quadword Non-temporal Aligned
 m128 to xmmreg1 C4: rxb0_2: w_F 001:2A:11 xmmreg1 r/mB-72 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
VMPSADBW — Multiple Packed Sums of Absolute Difference
  xmmreg3 with xmmreg2 into xmmreg1 C4: rxb0_3: w xmmreg2 001:42:11 xmmreg1 xmmreg3: imm
  m128 with xmmreg2 into xmmreg1 C4: rx b0_3: w xmmreg2 001:42:mod xmmreg1 r/m: imm
VPACKUSDW — Pack with Unsigned Saturation
 xmmreg3 and xmmreg2 to xmmreg1 C4: rxb0_2 : w xmmreg2 001:2B:11 xmmreg1 xmmreg3: imm
  m128 and xmmreg2 to xmmreg1 C4: rxb0_2: w xmmreg2 001:2B:mod xmmreg1 r/m: imm
VPBLENDVB — Variable Blend Packed Bytes
maskC4: rxb0_3: w xmmreg2 001:4C:11 xmmreg1 xmmreg3: xmmreg4
 xmmreg2 with mem to xmmreg1 using xmmreg4 as mask C4 : rxb0_3: w xmmreg2 001:4C:mod xmmreg1 r/m: xmmreg4
VPBLENDW — Blend Packed Words
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_3: w xmmreg2 001:0E:11 xmmreg1 xmmreg3: imm xmmreg2 with mem to xmmreg1 C4: rxb0_3: w xmmreg2 001:0E:mod xmmreg1 r/m: imm
VPCMPEQQ — Compare Packed Qword Data of Equal
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:29:11 xmmreg1 xmmreg3 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:29:mod xmmreg1 r/m:
VPEXTRB — Extract Byte
 reg from xmmreg1 using imm C4: rxb0_3: 0_F 001:14:11 xmmreg1 reg: imm mem from xmmreg1 using imm C4: rxb0_3: 0_F 001:14:mod xmmreg1 r/m: imm
VPEXTRD — Extract DWord
 reg from xmmreg1 using imm C4: rxb0_3: 0_F 001:16:11 xmmreg1 reg: imm mem from xmmreg1 using imm C4: rxb0_3: 0_F 001:16:mod xmmreg1 r/m: imm
VPEXTRQ — Extract QWord
 reg from xmmreg1 using imm C4: rxb0_3: 1_F 001:16:11 xmmreg1 reg: imm mem from xmmreg1 using imm C4: rxb0_3: 1_F 001:16:mod xmmreg1 r/m: imm
VPEXTRW — Extract Word
 reg from xmmreg1 using imm C4: rxb0_3: 0_F 001:15:11 xmmreg1 reg: imm mem from xmmreg1 using imm C4: rxb0_3: 0_F 001:15:mod xmmreg1 r/m: imm
VPHMINPOSUW — Packed Horizontal Word Minimum
 xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:41:11 xmmreg1 xmmreg2 mem to xmmreg1 C4: rxb0_2: w_F 001:41:mod xmmreg1 r/m
VPINSRB — Insert Byte
  reg with xmmreg2 to xmmreg1, imm8 C4: rx b0_3: 0 xmmreg2 001:20:11 xmmreg1 reg: imm
 mem with xmmreg2 to xmmreg1, imm8 C4: rx b0_3: 0 xmmreg2 001:20:mod xmmreg1 r/m: imm
VPINSRD — Insert DWord
 reg with xmmreg2 to xmmreg1, imm8 C4: rx b0_3: 0 xmmreg2 001:22:11 xmmreg1 reg: imm
 mem with xmmreg2 to xmmreg1, imm8 C4: rx b0_3: 0 xmmreg2 001:22:mod xmmreg1 r/m: imm
VPINSRQ — Insert QWord
 r64 with xmmreg2 to xmmreg1, imm8 C4: rx b0_3: 1 xmmreg2 001:22:11 xmmreg1 reg: immInstruction and Format EncodingVol. 2D B-73INSTRUCTION FORMATS AND ENCODINGS
 m64 with xmmreg2 to xmmreg1, imm8 C4: rxb0_3: 1 xmmreg2 001:22:mod xmmreg1 r/m: imm
VPMAXSB — Maximum of Packed Signed Byte Integers
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:3C:11 xmmreg1 xmmreg3 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:3C:mod xmmreg1 r/m
VPMAXSD — Maximum of Packed Signed Dword Integers
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:3D:11 xmmreg1 xmmreg3 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:3D:mod xmmreg1 r/m
VPMAXUD — Maximum of Packed Unsigned Dword Integers
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:3F:11 xmmreg1 xmmreg3 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:3F:mod xmmreg1 r/m
VPMAXUW — Maximum of Packed Unsigned Word Integers
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:3E:11 xmmreg1 xmmreg3 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:3E:mod xmmreg1 r/m
VPMINSB — Minimum of Packed Signed Byte Integers
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:38:11 xmmreg1 xmmreg3
 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:38:mod xmmreg1 r/m
VPMINSD — Minimum of Packed Signed Dword Integers
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:39:11 xmmreg1 xmmreg3
 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:39:mod xmmreg1 r/m
VPMINUD — Minimum of Packed Unsigned Dword Integers
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:3B:11 xmmreg1 xmmreg3
 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:3B:mod xmmreg1 r/m
VPMINUW — Minimum of Packed Unsigned Word Integers
 xmmreg2 with xmmreg3 into xmmreg1 C4: rxb0_2: w xmmreg2 001:3A:11 xmmreg1 xmmreg3
 xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:3A:mod xmmreg1 r/m
VPMOVSXBD — Packed Move Sign Extend - Byte to Dword
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:21:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_2: w_F 001:21:mod xmmreg1 r/m
VPMOVSXBQ — Packed Move Sign Extend - Byte to Qword
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:22:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_2: w_F 001:22:mod xmmreg1 r/m
VPMOVSXBW — Packed Move Sign Extend - Byte to Word
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:20:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_2: w_F 001:20:mod xmmreg1 r/m
VPMOVSXWD — Packed Move Sign Extend - Word to Dword
 xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:23:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_2: w_F 001:23:mod xmmreg1 r/m
VPMOVSXWQ — Packed Move Sign Extend - Word to Qword
 xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:24:11 xmmreg1 xmmreg2Instruction and Format EncodingB-74 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
 mem to xmmreg1 C4: rxb0_2: w_F 001:24:mod xmmreg1 r/m
VPMOVSXDQ — Packed Move Sign  Extend - Dword to Qword
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:25:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_2: w_F 001:25:mod xmmreg1 r/m

mem to xmmreg1 C4: rxb0_2: w_F 001:21:mod xmmreg1 r/m
VPMOVZXBD — Packed Move Zero Extend - Byte to Dword
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:31:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_2: w_F 001:31:mod xmmreg1 r/m
VPMOVZXBQ — Packed Move Zero Extend - Byte to Qword
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:32:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_2: w_F 001:32:mod xmmreg1 r/m
VPMOVZXBW — Packed Move Zero Extend - Byte to Word
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:30:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_2: w_F 001:30:mod xmmreg1 r/m
VPMOVZXWD — Packed Move Zero Extend - Word to Dword
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:33:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_2: w_F 001:33:mod xmmreg1 r/m
VPMOVZXWQ — Packed Move Zero Extend - Word to Qword
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:34:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_2: w_F 001:34:mod xmmreg1 r/m
VPMOVZXDQ — Packed Move Zero Extend - Dword to Qword
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:35:11 xmmreg1 xmmreg2
 mem to xmmreg1 C4: rxb0_2: w_F 001:35:mod xmmreg1 r/m
VPMULDQ — Multiply Packed Signed Dword Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:28:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:28:mod xmmreg1 r/m
VPMULLD — Multiply Packed Signed  Dword Integers, Store low Result
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:40:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:40:mod xmmreg1 r/m
VPTEST — Logical Compare
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:17:11 xmmreg1 xmmreg2
  mem to xmmreg C4: rxb0_2: w_F 001:17:mod xmmreg1 r/m  ymmreg2 to ymmreg1 C4: rxb0_2: w_F 101:17:11 ymmreg1 ymmreg2
  mem to ymmreg C4: rxb0_2: w_F 101:17:mod ymmreg1 r/m
VROUNDPD — Round Packed Double Precision Values
  xmmreg2 to xmmreg1, imm8 C4: rxb0_3: w_F 001:09:11 xmmreg1 xmmreg2: imm
  mem to xmmreg1, imm8 C4: rxb0_3: w_F 001:09:mod xmmreg1 r/m: imm
  ymmreg2 to ymmreg1, imm8 C4: rxb0_3 : w_F 101:09:11 ymmreg1 ymmreg2: imm
  mem to ymmreg1, imm8 C4: rxb0_3: w_F 101:09:mod ymmreg1 r/m: imm
VROUNDPS — Round Packed Single Precision ValuesInstruction and Format EncodingVol. 2D B-75INSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 to xmmreg1, imm8 C4: rxb0_3: w_F 001:08:11 xmmreg1 xmmreg2: imm
  mem to xmmreg1, imm8 C4: rxb0_3: w_F 001:08:mod xmmreg1 r/m: imm
  ymmreg2 to ymmreg1, imm8 C4: rxb0_3 : w_F 101:08:11 ymmreg1 ymmreg2: imm
  mem to ymmreg1, imm8 C4: rxb0_3: w_F 101:08:mod ymmreg1 r/m: imm
VROUNDSD — Round Scalar Double Precision Value
 xmmreg2 and xmmreg3 to xmmreg1, imm8 C4: rxb0 _3: w xmmreg2 001:0B:11 xmmreg1 xmmreg3: imm
  xmmreg2 and mem to xmmreg1, imm8 C4: rxb0_3: w xmmreg2 001:0B:mod xmmreg1 r/m: imm
VROUNDSS — Round Scalar Single Precision Value
 xmmreg2 and xmmreg3 to xmmreg1, imm8 C4: rxb0 _3: w xmmreg2 001:0A:11 xmmreg1 xmmreg3: imm
  xmmreg2 and mem to xmmreg1, imm8 C4: rxb0 _3: w xmmreg2 001:0A:mod xmmreg1 r/m: imm
VPCMPESTRI — Packed Compare Explicit Length Strings, Return Index
  xmmreg2 with xmmreg1, imm8 C4: rxb0_3: w_F 001:61:11 xmmreg1 xmmreg2: imm  mem with xmmreg1, imm8 C4: rxb0_3: w_F 001:61:mod xmmreg1 r/m: imm
VPCMPESTRM — Packed Compare Explicit Length Strings, Return Mask
  xmmreg2 with xmmreg1, imm8 C4: rxb0_3: w_F 001:60:11 xmmreg1 xmmreg2: imm
  mem with xmmreg1, imm8 C4: rxb0_3: w_F 001:60:mod xmmreg1 r/m: imm
VPCMPGTQ — Compare Packed Data for Greater Than
VPCMPISTRI — Packed Compare Implicit Length Strings, Return Index
  xmmreg2 with xmmreg1, imm8 C4: rxb0_3: w_F 001:63:11 xmmreg1 xmmreg2: imm
  mem with xmmreg1, imm8 C4: rxb0_3: w_F 001:63:mod xmmreg1 r/m: imm
VPCMPISTRM — Packed Compare Implicit Length Strings, Return Mask
  xmmreg2 with xmmreg1, imm8 C4: rxb0_3: w_F 001:62:11 xmmreg1 xmmreg2: imm
  mem with xmmreg, imm8 C4: rxb0_3: w_F 001:62:mod xmmreg1 r/m: imm
VAESDEC — Perform One Round of an AES Decryption Flow
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:DE:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:DE:mod xmmreg1 r/m
VAESDECLAST — Perform Last Round  of an AES Decryption Flow
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:DF:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:DF:mod xmmreg1 r/m
VAESENC — Perform One Round of an AES Encryption Flow
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:DC:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:DC:mod xmmreg1 r/m
VAESENCLAST — Perform Last Round  of an AES Encryption Flow
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:DD:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:DD:mod xmmreg1 r/m
VAESIMC — Perform the AES In vMixColumn Transformation
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:DB:11 xmmreg1 xmmreg2Instruction and Format EncodingB-76 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  mem to xmmreg1 C4: rxb0_2: w_F 001:DB:mod xmmreg1 r/m
VAESKEYGENASSIST — AES Ro und Key Generation Assist
  xmmreg2 to xmmreg1, imm8 C4: rxb0_3: w_F 001:DF:11 xmmreg1 xmmreg2: imm  mem to xmmreg, imm8 C4: rxb0_3: w_F 001:DF:mod xmmreg1 r/m: imm
VPABSB — Packed Absolute Value
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:1C:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_2: w_F 001:1C:mod xmmreg1 r/m
VPABSD — Packed Absolute Value
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:1E:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_2: w_F 001:1E:mod xmmreg1 r/m
VPABSW — Packed Absolute Value
  xmmreg2 to xmmreg1 C4: rxb0_2: w_F 001:1D:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_2: w_F 001:1D:mod xmmreg1 r/m
VPALIGNR — Packed Align Right
  xmmreg2 with xmmreg3 to xmmreg1, imm8 C4: rxb0_3: w xmmreg2 001:DD:11 xmmreg1 xmmreg3: imm
  xmmreg2 with mem to xmmreg1, imm8 C4: rxb0_3: w xmmreg2 001:DD:mod xmmreg1 r/m: imm
VPHADDD — Packed Horizontal Add
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:02:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:02:mod xmmreg1 r/m
VPHADDW — Packed Horizontal Add
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:01:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:01:mod xmmreg1 r/m
VPHADDSW — Packed Horizontal Add and Saturate
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:03:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:03:mod xmmreg1 r/m
VPHSUBD — Packed Horizontal Subtract
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:06:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:06:mod xmmreg1 r/m
VPHSUBW — Packed Horizontal Subtract
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:05:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:05:mod xmmreg1 r/m
VPHSUBSW — Packed Horizontal Subtract and Saturate
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:07:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:07:mod xmmreg1 r/m
VPMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:04:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:04:mod xmmreg1 r/m
VPMULHRSW — Packed Multiply High with Round and Scale
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:0B:11 xmmreg1 xmmreg3Instruction and Format EncodingVol. 2D B-77INSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:0B:mod xmmreg1 r/m
VPSHUFB — Packed Shuffle Bytes
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:00:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:00:mod xmmreg1 r/m
VPSIGNB — Packed SIGN
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:08:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:08:mod xmmreg1 r/m
VPSIGND — Packed SIGN
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:0A:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:0A:mod xmmreg1 r/m
VPSIGNW — Packed SIGN
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: w xmmreg2 001:09:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_2: w xmmreg2 001:09:mod xmmreg1 r/m
VADDSUBPD — Packed Double-FP Add/Subtract
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:D0:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:D0:mod xmmreg1 r/m  xmmreglo2
1 with xmmreglo3 to xmmreg1 C5: r_x mmreglo2 001:D0:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:D0:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:D0:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:D0:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 101:D0:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:D0:mod ymmreg1 r/m
VADDSUBPS — Packed Single-FP Add/Subtract

  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:D0:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:D0:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 011:D0:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:D0:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 111:D0:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 111:D0:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 111:D0:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 111:D0:mod ymmreg1 r/m
VHADDPD — Packed Double-FP Horizontal Add
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:7C:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:7C:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:7C:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:7C:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:7C:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:7C:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:7C:11 ymmreg1 ymmreglo3Instruction and Format EncodingB-78 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:7C:mod ymmreg1 r/m
VHADDPS — Packed Single-FP Horizontal Add
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:7C:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:7C:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:7C:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:7C:mod xmmreg1 r/m  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 111:7C:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 111:7C:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 111:7C:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 111:7C:mod ymmreg1 r/m
VHSUBPD — Packed Double-FP Horizontal Subtract
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:7D:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:7D:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:7D:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:7D:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:7D:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:7D:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:7D:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:7D:mod ymmreg1 r/m
VHSUBPS — Packed Single-FP Horizontal Subtract
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:7D:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:7D:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 011:7D:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:7D:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 111:7D:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 111:7D:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 111:7D:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 111:7D:mod ymmreg1 r/m
VLDDQU — Load Unaligned Integer 128 Bits
  mem to xmmreg1 C4: rxb0_1: w_F 011:F0:mod xmmreg1 r/m
  mem to xmmreg1 C5: r_F 011:F0:mod xmmreg1 r/m  mem to ymmreg1 C4: rxb0_1: w_F 111:F0:mod ymmreg1 r/m
  mem to ymmreg1 C5: r_F 111:F0:mod ymmreg1 r/m
VMOVDDUP — Move One Double-FP and Duplicate
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 011:12:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 011:12:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 011:12:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 011:12:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 111:12:11 ymmreg1 ymmreg2Instruction and Format EncodingVol. 2D B-79INSTRUCTION FORMATS AND ENCODINGS
  mem to ymmreg1 C4: rxb0_1: w_F 111:12:mod ymmreg1 r/m
  ymmreglo to ymmreg1 C5: r_ F 111:12:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 111:12:mod ymmreg1 r/m
VMOVHLPS — Move Packed Single Precision Floating-Point Values High to Low
  xmmreg2 and xmmreg3 to xmmreg1 C4: rx b0_1: w xmmreg2 000:12:11 xmmreg1 xmmreg3
  xmmreglo2 and xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:12:11 xmmreg1 xmmreglo3
VMOVSHDUP — Move Packed Single-FP High and Duplicate
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 010:16:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 010:16:mod xmmreg1 r/m  xmmreglo to xmmreg1 C5: r_F 010:16:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 010:16:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 110:16:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 110:16:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 110:16:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 110:16:mod ymmreg1 r/m
VMOVSLDUP — Move Packed Single-FP Low and Duplicate
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 010:12:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 010:12:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 010:12:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 010:12:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 110:12:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 110:12:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 110:12:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 110:12:mod ymmreg1 r/m
VADDPD — Add Packed Double Pr ecision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:58:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:58:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:58:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 001:58:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:58:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:58:mod ymmreg1 r/m  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:58:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:58:mod ymmreg1 r/m
VADDSD — Add Scalar Double Pr ecision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:58:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:58:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:58:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5 r_xmmreglo2 011:58:mod xmmreg1 r/m
VANDPD — Bitwise Logical AND of Packed Double Precision Floating-Point ValuesInstruction and Format EncodingB-80 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:54:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:54:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:54:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:54:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:54:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:54:mod ymmreg1 r/m  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 101:54:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:54:mod ymmreg1 r/m
VANDNPD — Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:55:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:55:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:55:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:55:mod xmmreg1 r/m  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:55:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:55:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 101:55:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:55:mod ymmreg1 r/m
VCMPPD — Compare Packed Double Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:C2:11 xmmreg1 xmmreg3: imm  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:C2:mod xmmreg1 r/m: imm
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:C2:11 xmmreg1 xmmreglo3: imm
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:C2:mod xmmreg1 r/m: imm  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0 _1: w ymmreg2 101:C2:11 ymmreg1 ymmreg3: imm
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:C2:mod ymmreg1 r/m: imm
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:C2:11 ymmreg1 ymmreglo3: imm
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:C2:mod ymmreg1 r/m: imm
VCMPSD — Compare Scalar Double Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:C2:11 xmmreg1 xmmreg3: imm  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:C2:mod xmmreg1 r/m: imm
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:C2:11 xmmreg1 xmmreglo3: imm
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:C2:mod xmmreg1 r/m: imm

xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:C2:11 xmmreg1 xmmreglo3: imm
VCOMISD — Compare Scalar Ordered Double Prec ision Floating-Point Values and Set EFLAGS
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 001:2F:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 001:2F:mod xmmreg1 r/m  xmmreglo to xmmreg1 C5: r_F 001:2F:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 001:2F:mod xmmreg1 r/m
VCVTDQ2PD— Convert Packed Dword Integers  to Packed Double Precision FP Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 010:E6:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 010:E6:mod xmmreg1 r/mInstruction and Format EncodingVol. 2D B-81INSTRUCTION FORMATS AND ENCODINGS
  xmmreglo to xmmreg1 C5: r_F 010:E6:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 010:E6:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 110:E6:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 110:E6:mod ymmreg1 r/m
  ymmreglo to ymmreg1 C5: r_F 110:E6:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 110:E6:mod ymmreg1 r/m
VCVTDQ2PS— Convert Packed Dword Integers  to Packed Single Precision FP Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 000:5B:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 000:5B:mod xmmreg1 r/m  xmmreglo to xmmreg1 C5: r_F 000:5B:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 000:5B:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 100:5B:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 100:5B:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 100:5B:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 100:5B:mod ymmreg1 r/m
VCVTPD2DQ— Convert Packed Double Precis ion FP Values to Packed Dword Integers
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 011:E6:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 011:E6:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 011:E6:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 011:E6:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 111:E6:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 111:E6:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 111:E6:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 111:E6:mod ymmreg1 r/m
VCVTPD2PS— Convert Packed Double Precision FP Values to Packed Single Precision FP Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 001:5A:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 001:5A:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 001:5A:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 001:5A:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 101:5A:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 101:5A:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 101:5A:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 101:5A:mod ymmreg1 r/m
VCVTPS2DQ— Convert Packed Single Precis ion FP Values to Packed Dword Integers
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 001:5B:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 001:5B:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 001:5B:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 001:5B:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 101:5B:11 ymmreg1 ymmreg2Instruction and Format EncodingB-82 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  mem to ymmreg1 C4: rxb0_1: w_F 101:5B:mod ymmreg1 r/m
  ymmreglo to ymmreg1 C5: r_F 101:5B:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 101:5B:mod ymmreg1 r/m
VCVTPS2PD— Convert Packed Single Precision FP Values to Packed Double Precision FP Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 000:5A:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 000:5A:mod xmmreg1 r/m  xmmreglo to xmmreg1 C5: r_F 000:5A:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 000:5A:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 100:5A:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 100:5A:mod ymmreg1 r/m
  ymmreglo to ymmreg1 C5: r_F 100:5A:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 100:5A:mod ymmreg1 r/m
VCVTSD2SI— Convert Scalar Double Precision FP Value to Integer
  xmmreg1 to reg32 C4: rxb0_1: 0_F 011:2D:11 reg xmmreg1
  mem to reg32 C4: rxb0_1: 0_F 011:2D:mod reg r/m
  xmmreglo to reg32 C5: r_F 011:2D:11 reg xmmreglo  mem to reg32 C5: r_F 011:2D:mod reg r/m
  ymmreg1 to reg64 C4: rxb0_1: 1_F 111:2D:11 reg ymmreg1
  mem to reg64 C4: rxb0_1: 1_F 111:2D:mod reg r/m
VCVTSD2SS — Convert Scalar Doub le Precision FP Value to Scalar Single Precision FP Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:5A:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:5A:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:5A:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:5A:mod xmmreg1 r/m
VCVTSI2SD— Convert Dword Integer to Scalar Double Precision FP Value
  xmmreg2 with reg to xmmreg1 C4: rxb0_1: 0 xmmreg2 011:2A:11 xmmreg1 reg
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: 0 xmmreg2 011:2A:mod xmmreg1 r/m
  xmmreglo2 with reglo to xmmreg1 C5: r_xmmreglo2 011:2A:11 xmmreg1 reglo  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:2A:mod xmmreg1 r/m
  ymmreg2 with reg to ymmreg1 C4: rxb0_1: 1 ymmreg2 111:2A:11 ymmreg1 reg
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: 1 ymmreg2 111:2A:mod ymmreg1 r/m
VCVTSS2SD — Convert Scalar Sing le Precision FP Value to Scalar Double Precision FP Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:5A:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:5A:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:5A:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:5A:mod xmmreg1 r/m
VCVTTPD2DQ— Convert with Truncatio n Packed Double Precision FP Values to Packed Dword Integers
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 001:E6:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 001:E6:mod xmmreg1 r/mInstruction and Format EncodingVol. 2D B-83INSTRUCTION FORMATS AND ENCODINGS
  xmmreglo to xmmreg1 C5: r_F 001:E6:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 001:E6:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 101:E6:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 101:E6:mod ymmreg1 r/m
  ymmreglo to ymmreg1 C5: r_F 101:E6:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 101:E6:mod ymmreg1 r/m
VCVTTPS2DQ— Convert with Truncation Packed Single Precision FP  Values to Packed Dword Integers
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 010:5B:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 010:5B:mod xmmreg1 r/m  xmmreglo to xmmreg1 C5: r_F 010:5B:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 010:5B:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 110:5B:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 110:5B:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 110:5B:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 110:5B:mod ymmreg1 r/m
VCVTTSD2SI— Convert with Truncat ion Scalar Double Precision FP Value to Signed Integer
  xmmreg1 to reg32 C4: rxb0_1: 0_F 011:2C:11 reg xmmreg1
  mem to reg32 C4: rxb0_1: 0_F 011:2C:mod reg r/m
  xmmreglo to reg32 C5: r_F 011:2C:11 reg xmmreglo  mem to reg32 C5: r_F 011:2C:mod reg r/m
  xmmreg1 to reg64 C4: rxb0_1: 1_F 011:2C:11 reg xmmreg1
  mem to reg64 C4: rxb0_1: 1_F 011:2C:mod reg r/m
VDIVPD — Divide Packed Double Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:5E:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:5E:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:5E:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:5E:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:5E:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:5E:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:5E:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:5E:mod ymmreg1 r/m
VDIVSD — Divide Scalar Double Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:5E:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:5E:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:5E:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:5E:mod xmmreg1 r/m
VMASKMOVDQU— Store Selected Bytes of Double Quadword
  xmmreg1 to mem; xmmreg2 as mask C4: rxb0_1: w_F 001:F7:11 r/m xmmreg1: xmmreg2
  xmmreg1 to mem; xmmreg2 as mask C5: r_F 001:F7:11 r/m xmmreg1: xmmreg2Instruction and Format EncodingB-84 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
VMAXPD — Return Maximum Packed Doub le Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:5F:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:5F:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:5F:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:5F:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:5F:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:5F:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 101:5F:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:5F:mod ymmreg1 r/m
VMAXSD — Return Maximum Scalar Doub le Precision Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:5F:11 xmmreg1 xmmreg3

xmmreg1 to mem; xmmreg2 as mask C5: r_F 001:F7:11 r/m xmmreg1: xmmreg2Instruction and Format EncodingB-84 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:5F:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:5F:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:5F:mod xmmreg1 r/m
VMINPD — Return Minimum Packed Doub le Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:5D:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:5D:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:5D:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:5D:mod xmmreg1 r/m  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:5D:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:5D:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:5D:11 ymmreg1 ymmreglo3  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:5D:mod ymmreg1 r/m
VMINSD — Return Minimum Scalar Doub le Precision Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:5D:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:5D:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 011:5D:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:5D:mod xmmreg1 r/m
VMOVAPD — Move Aligned Packed Doub le Precision Floating-Point Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 001:28:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 001:28:mod xmmreg1 r/m  xmmreglo to xmmreg1 C5: r_F 001:28:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 001:28:mod xmmreg1 r/m
  xmmreg1 to xmmreg2 C4: rxb0_1: w_F 001:29:11 xmmreg2 xmmreg1  xmmreg1 to mem C4: rxb0_1: w_F 001:29:mod r/m xmmreg1
  xmmreg1 to xmmreglo C5: r_F 001:29:11 xmmreglo xmmreg1
  xmmreg1 to mem C5: r_F 001:29:mod r/m xmmreg1  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 101:28:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 101:28:mod ymmreg1 r/mInstruction and Format EncodingVol. 2D B-85INSTRUCTION FORMATS AND ENCODINGS
  ymmreglo to ymmreg1 C5: r_F 101:28:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 101:28:mod ymmreg1 r/m
  ymmreg1 to ymmreg2 C4: rxb0_1: w_F 101:29:11 ymmreg2 ymmreg1  ymmreg1 to mem C4: rxb0_1: w_F 101:29:mod r/m ymmreg1
  ymmreg1 to ymmreglo C5: r_F 101:29:11 ymmreglo ymmreg1
  ymmreg1 to mem C5: r_F 101:29:mod r/m ymmreg1
VMOVD — Move Doubleword
  reg32 to xmmreg1 C4: rxb0_1: 0_F 001:6E:11 xmmreg1 reg32
  mem32 to xmmreg1 C4: rxb0_1: 0_F 001:6E:mod xmmreg1 r/m  reg32 to xmmreg1 C5: r_F 001:6E:11 xmmreg1 reg32
  mem32 to xmmreg1 C5: r_F 001:6E:mod xmmreg1 r/m
  xmmreg1 to reg32 C4: rxb0_1: 0_F 001:7E:11 reg32 xmmreg1  xmmreg1 to mem32 C4: rxb0_1: 0_F 001:7E:mod mem32 xmmreg1  xmmreglo to reg32 C5: r_F 001:7E:11 reg32 xmmreglo
  xmmreglo to mem32 C5: r_F 001:7E:mod mem32 xmmreglo
VMOVQ — Move Quadword
  reg64 to xmmreg1 C4: rxb0_1: 1_F 001:6E:11 xmmreg1 reg64
  mem64 to xmmreg1 C4: rxb0_1: 1_F 001:6E:mod xmmreg1 r/m
  xmmreg1 to reg64 C4: rxb0_1: 1_F 001:7E:11 reg64 xmmreg1  xmmreg1 to mem64 C4: rxb0_1: 1_F 001:7E:mod r/m xmmreg1
VMOVDQA — Move Aligned Double Quadword
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 001:6F:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_1: w_F 001:6F:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 001:6F:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 001:6F:mod xmmreg1 r/m  xmmreg1 to xmmreg2 C4: rxb0_1: w_F 001:7F:11 xmmreg2 xmmreg1
  xmmreg1 to mem C4: rxb0_1: w_F 001:7F:mod r/m xmmreg1
  xmmreg1 to xmmreglo C5: r_F 001:7F:11 xmmreglo xmmreg1  xmmreg1 to mem C5: r_F 001:7F:mod r/m xmmreg1
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 101:6F:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 101:6F:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 101:6F:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 101:6F:mod ymmreg1 r/m
  ymmreg1 to ymmreg2 C4: rxb0_1: w_F 101:7F:11 ymmreg2 ymmreg1  ymmreg1 to mem C4: rxb0_1: w_F 101:7F:mod r/m ymmreg1
  ymmreg1 to ymmreglo C5: r_F 101:7F:11 ymmreglo ymmreg1
  ymmreg1 to mem C5: r_F 101:7F:mod r/m ymmreg1
VMOVDQU — Move Unaligned Double Quadword
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 010:6F:11 xmmreg1 xmmreg2Instruction and Format EncodingB-86 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  mem to xmmreg1 C4: rxb0_1: w_F 010:6F:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 010:6F:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 010:6F:mod xmmreg1 r/m  xmmreg1 to xmmreg2 C4: rxb0_1: w_F 010:7F:11 xmmreg2 xmmreg1
  xmmreg1 to mem C4: rxb0_1: w_F 010:7F:mod r/m xmmreg1
  xmmreg1 to xmmreglo C5: r_F 010:7F:11 xmmreglo xmmreg1  xmmreg1 to mem C5: r_F 010:7F:mod r/m xmmreg1
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 110:6F:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 110:6F:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 110:6F:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 110:6F:mod ymmreg1 r/m
  ymmreg1 to ymmreg2 C4: rxb0_1: w_F 110:7F:11 ymmreg2 ymmreg1  ymmreg1 to mem C4: rxb0_1: w_F 110:7F:mod r/m ymmreg1  ymmreg1 to ymmreglo C5: r_F 110:7F:11 ymmreglo ymmreg1
  ymmreg1 to mem C5: r_F 110:7F:mod r/m ymmreg1
VMOVHPD — Move High Packed Double  Precision Floating-Point Value
  xmmreg1 and mem to xmmreg2 C4: rxb0_1: w xmmreg1 001:16:11 xmmreg2 r/m
  xmmreg1 and mem to xmmreglo2 C5: r_xmmreg1 001:16:11 xmmreglo2 r/m
  xmmreg1 to mem C4: rxb0_1: w_F 001:17:mod r/m xmmreg1  xmmreglo to mem C5: r_F 001:17:mod r/m xmmreglo
VMOVLPD — Move Low Packed Double  Precision Floating-Point Value
  xmmreg1 and mem to xmmreg2 C4: rxb0_1: w xmmreg1 001:12:11 xmmreg2 r/m  xmmreg1 and mem to xmmreglo2 C5: r_xmmreg1 001:12:11 xmmreglo2 r/m
  xmmreg1 to mem C4: rxb0_1: w_F 001:13:mod r/m xmmreg1
  xmmreglo to mem C5: r_F 001:13:mod r/m xmmreglo
VMOVMSKPD — Extract Packed Double Precision Floating -Point Sign Mask
  xmmreg2 to reg C4: rxb0_1: w_F 001:50:11 reg xmmreg1
  xmmreglo to reg C5: r_F 001:50:11 reg xmmreglo  ymmreg2 to reg C4: rxb0_1: w_F 101:50:11 reg ymmreg1
  ymmreglo to reg C5: r_F 101:50:11 reg ymmreglo
VMOVNTDQ — Store Double Quad word Using Non-Temporal Hint
  xmmreg1 to mem C4: rxb0_1: w_F 001:E7:11 r/m xmmreg1
  xmmreglo to mem C5: r_F 001:E7:11 r/m xmmreglo
  ymmreg1 to mem C4: rxb0_1: w_F 101:E7:11 r/m ymmreg1  ymmreglo to mem C5: r_F 101:E7:11 r/m ymmreglo
VMOVNTPD — Store Packed Double Precision Fl oating-Point Values Using Non-Temporal Hint
  xmmreg1 to mem C4: rxb0_1: w_F 001:2B:11 r/m xmmreg1  xmmreglo to mem C5: r_F 001:2B:11 r/m xmmreglo
  ymmreg1 to mem C4: rxb0_1: w_F 101:2B:11r/m ymmreg1Instruction and Format EncodingVol. 2D B-87INSTRUCTION FORMATS AND ENCODINGS
  ymmreglo to mem C5: r_F 101:2B:11r/m ymmreglo
VMOVSD — Move Scalar Double Precision Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:10:11 xmmreg1 xmmreg3  mem to xmmreg1 C4: rxb0_1: w_F 011:10:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:10:11 xmmreg1 xmmreglo3
  mem to xmmreg1 C5: r_F 011:10:mod xmmreg1 r/m  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:11:11 xmmreg1 xmmreg3
  xmmreg1 to mem C4: rxb0_1: w_F 011:11:mod r/m xmmreg1
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:11:11 xmmreg1 xmmreglo3  xmmreglo to mem C5: r_F 011:11:mod r/m xmmreglo
VMOVUPD — Move Unaligned Packed Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 001:10:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_1: w_F 001:10:mod xmmreg1 r/m  xmmreglo to xmmreg1 C5: r_F 001:10:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 001:10:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 101:10:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 101:10:mod ymmreg1 r/m 
  ymmreglo to ymmreg1 C5: r_F 101:10:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 101:10:mod ymmreg1 r/m   xmmreg1 to xmmreg2 C4: rxb0_1: w_F 001:11:11 xmmreg2 xmmreg1
  xmmreg1 to mem C4: rxb0_1: w_F 001:11:mod r/m xmmreg1
  xmmreg1 to xmmreglo C5: r_F 001:11:11 xmmreglo xmmreg1  xmmreg1 to mem C5: r_F 001:11:mod r/m xmmreg1
  ymmreg1 to ymmreg2 C4: rxb0_1: w_F 101:11:11 ymmreg2 ymmreg1
  ymmreg1 to mem C4: rxb0_1: w_F 101:11:mod r/m ymmreg1  ymmreg1 to ymmreglo C5: r_F 101:11:11 ymmreglo ymmreg1
  ymmreg1 to mem C5: r_F 101:11:mod r/m ymmreg1
VMULPD — Multiply Packed Double  Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:59:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:59:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:59:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 001:59:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:59:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:59:mod ymmreg1 r/m   ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:59:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:59:mod ymmreg1 r/m 
VMULSD — Multiply Scalar Double  Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:59:11 xmmreg1 xmmreg3

ymmreg1 to mem C4: rxb0_1: w_F 101:11:mod r/m ymmreg1  ymmreg1 to ymmreglo C5: r_F 101:11:11 ymmreglo ymmreg1
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:59:mod xmmreg1 r/mInstruction and Format EncodingB-88 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:59:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:59:mod xmmreg1 r/m
VORPD — Bitwise Logical OR of Doub le Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:56:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:56:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:56:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:56:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:56:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:56:mod ymmreg1 r/m   ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 101:56:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:56:mod ymmreg1 r/m 
VPACKSSWB— Pack with Signed Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:63:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:63:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:63:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:63:mod xmmreg1 r/m
VPACKSSDW— Pack with Signed Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:6B:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:6B:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:6B:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:6B:mod xmmreg1 r/m
VPACKUSWB— Pack with Unsigned Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:67:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:67:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:67:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:67:mod xmmreg1 r/m
VPADDB — Add Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:FC:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:FC:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:FC:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:FC:mod xmmreg1 r/m
VPADDW — Add Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:FD:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:FD:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:FD:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:FD:mod xmmreg1 r/m
VPADDD — Add Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:FE:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:FE:mod xmmreg1 r/mInstruction and Format EncodingVol. 2D B-89INSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:FE:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:FE:mod xmmreg1 r/m
VPADDQ — Add Packed Quadword Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:D4:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:D4:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:D4:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:D4:mod xmmreg1 r/m
VPADDSB — Add Packed Signed Integers with Signed Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:EC:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:EC:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:EC:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:EC:mod xmmreg1 r/m
VPADDSW — Add Packed Signed In tegers with Signed Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:ED:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:ED:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:ED:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:ED:mod xmmreg1 r/m
VPADDUSB — Add Packed Unsigned In tegers with Unsigned Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:DC:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:DC:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:DC:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:DC:mod xmmreg1 r/m
VPADDUSW — Add Packed Unsigned In tegers with Unsigned Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:DD:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:DD:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:DD:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:DD:mod xmmreg1 r/m
VPAND — Logical AND
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:DB:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:DB:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C 5: r_xmmreglo2 001:DB:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:DB:mod xmmreg1 r/m
VPANDN — Logical AND NOT
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:DF:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:DF:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:DF:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:DF:mod xmmreg1 r/m
VPAVGB — Average Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:E0:11 xmmreg1 xmmreg3Instruction and Format EncodingB-90 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:E0:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:E0:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:E0:mod xmmreg1 r/m
VPAVGW — Average Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:E3:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:E3:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:E3:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:E3:mod xmmreg1 r/m
VPCMPEQB — Compare Packed Data for Equal
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:74:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:74:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:74:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:74:mod xmmreg1 r/m
VPCMPEQW — Compare Packed Data for Equal
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:75:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:75:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:75:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:75:mod xmmreg1 r/m
VPCMPEQD — Compare Packed Data for Equal
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:76:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:76:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:76:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:76:mod xmmreg1 r/m
VPCMPGTB — Compare Packed Signed Integers for Greater Than
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:64:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:64:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:64:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:64:mod xmmreg1 r/m
VPCMPGTW — Compare Packed Signed Integers for Greater Than
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:65:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:65:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:65:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:65:mod xmmreg1 r/m
VPCMPGTD — Compare Packed Signed Integers for Greater Than
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:66:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:66:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:66:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:66:mod xmmreg1 r/m
VPEXTRW — Extract WordInstruction and Format EncodingVol. 2D B-91INSTRUCTION FORMATS AND ENCODINGS
  xmmreg1 to reg using imm C4: rxb0_1: 0_F 001:C5:11 reg xmmreg1: imm
  xmmreg1 to reg using imm C5: r_F 001:C5:11 reg xmmreg1: imm
VPINSRW — Insert Word
  xmmreg2 with reg to xmmreg1 C4: rxb0_1: 0 xmmreg2 001:C4:11 xmmreg1 reg: imm
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: 0 xmmreg2 001:C4:mod xmmreg1 r/m: imm

xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:65:mod xmmreg1 r/m
  xmmreglo2 with reglo to xmmreg1 C5: r_xmmreglo2 001:C4:11 xmmreg1 reglo: imm  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:C4:mod xmmreg1 r/m: imm
VPMADDWD — Multiply and Add Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:F5:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:F5:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:F5:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:F5:mod xmmreg1 r/m
VPMAXSW — Maximum of Packed Signed Word Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:EE:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:EE:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:EE:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:EE:mod xmmreg1 r/m
VPMAXUB — Maximum of Packed Unsigned Byte Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:DE:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:DE:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:DE:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:DE:mod xmmreg1 r/m
VPMINSW — Minimum of Pack ed Signed Word Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:EA:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:EA:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:EA:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 001:EA:mod xmmreg1 r/m
VPMINUB — Minimum of Packed Unsigned Byte Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:DA:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:DA:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:DA:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 001:DA:mod xmmreg1 r/m
VPMOVMSKB — Move Byte Mask
  xmmreg1 to reg C4: rxb0_1: w_F 001:D7:11 reg xmmreg1  xmmreg1 to reg C5: r_F 001:D7:11 reg xmmreg1
VPMULHUW — Multiply Packed Unsign ed Integers and Store High Result
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:E4:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:E4:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:E4:11 xmmreg1 xmmreglo3Instruction and Format EncodingB-92 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:E4:mod xmmreg1 r/m
VPMULHW — Multiply Packed Signed Integers and Store High Result
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:E5:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:E5:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:E5:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:E5:mod xmmreg1 r/m
VPMULLW — Multiply Packed Signed  Integers and Store Low Result
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:D5:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:D5:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:D5:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:D5:mod xmmreg1 r/m
VPMULUDQ — Multiply Packed Unsigned Doubleword Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:F4:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:F4:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:F4:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:F4:mod xmmreg1 r/m
VPOR — Bitwise Logical OR
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:EB:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:EB:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:EB:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:EB:mod xmmreg1 r/m
VPSADBW — Compute Sum of Absolute Differences
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:F6:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:F6:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:F6:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:F6:mod xmmreg1 r/m
VPSHUFD — Shuffle Packed Doublewords
  xmmreg2 to xmmreg1 using imm C4: rxb0_1: w_F 001:70:11 xmmreg1 xmmreg2: imm  mem to xmmreg1 using imm C4: rxb0_1: w_F 001:70:mod xmmreg1 r/m: imm
  xmmreglo to xmmreg1 using imm C5: r_F 001:70:11 xmmreg1 xmmreglo: imm
  mem to xmmreg1 using imm C5: r_F 001:70:mod xmmreg1 r/m: imm
VPSHUFHW — Shuffle Packed High Words
  xmmreg2 to xmmreg1 using imm C4: rxb0_1: w_F 010:70:11 xmmreg1 xmmreg2: imm
  mem to xmmreg1 using imm C4: rxb0_1: w_F 010:70:mod xmmreg1 r/m: imm  xmmreglo to xmmreg1 using imm C5: r_F 010:70:11 xmmreg1 xmmreglo: imm
  mem to xmmreg1 using imm C5: r_F 010:70:mod xmmreg1 r/m: imm
VPSHUFLW — Shuffle Packed Low Words
  xmmreg2 to xmmreg1 using imm C4: rxb0_1: w_F 011:70:11 xmmreg1 xmmreg2: imm
  mem to xmmreg1 using imm C4: rxb0_1: w_F 011:70:mod xmmreg1 r/m: immInstruction and Format EncodingVol. 2D B-93INSTRUCTION FORMATS AND ENCODINGS
  xmmreglo to xmmreg1 using imm C5: r_F 011:70:11 xmmreg1 xmmreglo: imm
  mem to xmmreg1 using imm C5: r_F 011:70:mod xmmreg1 r/m: imm
VPSLLDQ — Shift Double Quadword Left Logical
  xmmreg2 to xmmreg1 using imm C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
  xmmreglo to xmmreg1 using imm C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSLLW — Shift Packed Data Left Logical
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:F1:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:F1:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:F1:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:F1:mod xmmreg1 r/m
  xmmreg2 to xmmreg1 using imm8 C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
  xmmreglo to xmmreg1 using imm8 C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSLLD — Shift Packed Data Left Logical
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:F2:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:F2:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:F2:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:F2:mod xmmreg1 r/m
  xmmreg2 to xmmreg1 using imm8 C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
  xmmreglo to xmmreg1 using imm8 C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSLLQ — Shift Packed Data Left Logical
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:F3:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:F3:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:F3:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:F3:mod xmmreg1 r/m
  xmmreg2 to xmmreg1 using imm8 C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm  xmmreglo to xmmreg1 using imm8 C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSRAW — Shift Packed Data Right Arithmetic
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:E1:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:E1:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:E1:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:E1:mod xmmreg1 r/m  xmmreg2 to xmmreg1 using imm8 C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
VPSRAD — Shift Packed Data Right Arithmetic
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:E2:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:E2:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:E2:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:E2:mod xmmreg1 r/m
  xmmreg2 to xmmreg1 using imm8 C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: immInstruction and Format EncodingB-94 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
VPSRLDQ — Shift Double Quadword Right Logical
VPSRLW — Shift Packed Data Right Logical
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:D1:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:D1:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:D1:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:D1:mod xmmreg1 r/m  xmmreg2 to xmmreg1 using imm8 C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
VPSRLD — Shift Packed Data Right Logical
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:D2:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:D2:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:D2:11 xmmreg1 xmmreglo3

  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:D2:mod xmmreg1 r/m  xmmreg2 to xmmreg1 using imm8 C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
VPSRLQ — Shift Packed Data Right Logical
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:D3:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:D3:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:D3:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:D3:mod xmmreg1 r/m
  xmmreg2 to xmmreg1 using imm8 C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
  xmmreglo to xmmreg1 using imm8 C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSUBB — Subtract Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:F8:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:F8:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:F8:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:F8:mod xmmreg1 r/m
VPSUBW — Subtract Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:F9:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:F9:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:F9:11 xmmreg1 xmmreglo3  xmmrelog2 with mem to xmmreg1 C5: r_xmmreglo2 001:F9:mod xmmreg1 r/m
VPSUBD — Subtract Packed Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:FA:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:FA:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:FA:11 xmmreg1 xmmreglo3Instruction and Format EncodingVol. 2D B-95INSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 001:FA:mod xmmreg1 r/m
VPSUBQ — Subtract Packed Quadword Integers
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:FB:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:FB:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:FB:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 001:FB:mod xmmreg1 r/m
VPSUBSB — Subtract Packed Signed Integers with Signed Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:E8:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:E8:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:E8:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:E8:mod xmmreg1 r/m
VPSUBSW — Subtract Packed Signed Integers with Signed Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:E9:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:E9:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:E9:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:E9:mod xmmreg1 r/m
VPSUBUSB — Subtract Packed Unsigned  Integers with Unsigned Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:D8:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:D8:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:D8:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:D8:mod xmmreg1 r/m
VPSUBUSW — Subtract Packed Unsigned  Integers with Unsigned Saturation
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:D9:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:D9:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:D9:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:D9:mod xmmreg1 r/m
VPUNPCKHBW — Unpack High Data
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:68:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:68:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:68:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 001:68:mod xmmreg1 r/m
VPUNPCKHWD — Unpack High Data
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:69:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:69:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:69:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 001:69:mod xmmreg1 r/m
VPUNPCKHDQ — Unpack High Data
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:6A:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:6A:mod xmmreg1 r/mInstruction and Format EncodingB-96 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:6A:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:6A:mod xmmreg1 r/m
VPUNPCKHQDQ — Unpack High Data
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:6D:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:6D:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 001:6D:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:6D:mod xmmreg1 r/m
VPUNPCKLBW — Unpack Low Data
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:60:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:60:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:60:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:60:mod xmmreg1 r/m
VPUNPCKLWD — Unpack Low Data
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:61:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:61:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:61:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:61:mod xmmreg1 r/m
VPUNPCKLDQ — Unpack Low Data
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:62:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:62:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:62:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:62:mod xmmreg1 r/m
VPUNPCKLQDQ — Unpack Low Data
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:6C:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:6C:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:6C:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:6C:mod xmmreg1 r/m
VPXOR — Logical Exclusive OR
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:EF:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:EF:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:EF:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:EF:mod xmmreg1 r/m
VSHUFPD — Shuffle Packed Double Precision Floati ng-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 using imm8 C4: rxb0_1: w xmmreg2 001:C6:11 xmmreg1 xmmreg3: imm  xmmreg2 with mem to xmmreg1 using imm8 C4: rxb0_1: w xmmreg2 001:C6:mod xmmreg1 r/m: imm
  xmmreglo2 with xmmreglo3 to xmmreg1 using imm8 C5: r_xmmreglo2 001:C6:11 xmmreg1 xmmreglo3: imm
  xmmreglo2 with mem to xmmreg1 using imm8 C5: r_xmmreglo2 001:C6:mod xmmreg1 r/m: imm
  ymmreg2 with ymmreg3 to ymmreg1 using imm8 C4: rxb0_1: w ymmreg2 101:C6:11 ymmreg1 ymmreg3: imm
  ymmreg2 with mem to ymmreg1 using imm8 C4: rxb0_1: w ymmreg2 101:C6:mod ymmreg1 r/m: immInstruction and Format EncodingVol. 2D B-97INSTRUCTION FORMATS AND ENCODINGS
  ymmreglo2 with ymmreglo3 to ymmreg1 using imm8 C5: r_ymmreglo2 101:C6:11 ymmreg1 ymmreglo3: imm
  ymmreglo2 with mem to ymmreg1 using imm8 C5: r_ymmreglo2 101:C6:mod ymmreg1 r/m: imm
VSQRTPD — Compute Square Roots of Packed  Double Precision Floating-Point Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 001:51:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 001:51:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 001:51:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 001:51:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 101:51:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 101:51:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 101:51:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 101:51:mod ymmreg1 r/m
VSQRTSD — Compute Square Root of Scalar  Double Precision Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:51:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:51:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:51:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 011:51:mod xmmreg1 r/m
VSUBPD — Subtract Packed Double  Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:5C:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:5C:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:5C:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:5C:mod xmmreg1 r/m

ymmreg2 to ymmreg1 C4: rxb0_1: w_F 101:51:11 ymmreg1 ymmreg2
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:5C:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:5C:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:5C:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:5C:mod ymmreg1 r/m
VSUBSD — Subtract Scalar Double  Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 011:5C:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 011:5C:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 011:5C:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 011:5C:mod xmmreg1 r/m
VUCOMISD — Unordered Compare Scalar Double Pr ecision Floating-Point Values and Set EFLAGS
  xmmreg2 with xmmreg1, set EFLAGS C4: rxb0_1: w_F xmmreg1 001:2E:11 xmmreg2
  mem with xmmreg1, set EFLAGS C4: rxb0_1: w_F xmmreg1 001:2E:mod r/m
  xmmreglo with xmmreg1, set EFLAGS C5: r_F xmmreg1 001:2E:11 xmmreglo  mem with xmmreg1, set EFLAGS C5: r_F xmmreg1 001:2E:mod r/m
VUNPCKHPD — Unpack and Interleave High Packed Double Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:15:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:15:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:15:11 xmmreg1 xmmreglo3Instruction and Format EncodingB-98 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:15:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:15:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:15:mod ymmreg1 r/m  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 101:15:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:15:mod ymmreg1 r/m
VUNPCKHPS — Unpack and Interleave High Pack ed Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:15:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:15:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:15:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:15:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:15:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:15:mod ymmreg1 r/m  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 100:15:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:15:mod ymmreg1 r/m
VUNPCKLPD — Unpack and Interleave Low Pack ed Double Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:14:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:14:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:14:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:14:mod xmmreg1 r/m  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:14:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:14:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 101:14:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:14:mod ymmreg1 r/m
VUNPCKLPS — Unpack and Interleave Low Pack ed Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:14:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:14:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:14:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:14:mod xmmreg1 r/m  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:14:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:14:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 100:14:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:14:mod ymmreg1 r/m
VXORPD — Bitwise Logical XOR for Doub le Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 001:57:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 001:57:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 001:57:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 001:57:mod xmmreg1 r/m  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 101:57:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 101:57:mod ymmreg1 r/mInstruction and Format EncodingVol. 2D B-99INSTRUCTION FORMATS AND ENCODINGS
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 101:57:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 101:57:mod ymmreg1 r/m
VADDPS — Add Packed Single Pr ecision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:58:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:58:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:58:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 000:58:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:58:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:58:mod ymmreg1 r/m  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 100:58:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:58:mod ymmreg1 r/m
VADDSS — Add Scalar Single Pr ecision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:58:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:58:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:58:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 010:58:mod xmmreg1 r/m
VANDPS — Bitwise Logical AND of Packed Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:54:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:54:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:54:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 000:54:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:54:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:54:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 100:54:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:54:mod ymmreg1 r/m
VANDNPS — Bitwise Logical AND NOT of Packed  Single Precision Fl oating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:55:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:55:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:55:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 000:55:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:55:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:55:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 100:55:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:55:mod ymmreg1 r/m
VCMPPS — Compare Packed Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:C2:11 xmmreg1 xmmreg3: imm
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:C2:mod xmmreg1 r/m: imm  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:C2:11 xmmreg1 xmmreglo3: imm
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:C2:mod xmmreg1 r/m: immInstruction and Format EncodingB-100 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0 _1: w ymmreg2 100:C2:11 ymmreg1 ymmreg3: imm
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:C2:mod ymmreg1 r/m: imm
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 100:C2:11 ymmreg1 ymmreglo3: imm
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:C2:mod ymmreg1 r/m: imm
VCMPSS — Compare Scalar Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:C2:11 xmmreg1 xmmreg3: imm  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:C2:mod xmmreg1 r/m: imm
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:C2:11 xmmreg1 xmmreglo3: imm
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:C2:mod xmmreg1 r/m: imm
VCOMISS — Compare Scalar Orde red Single Precision Floating -Point Values and Set EFLAGS
  xmmreg2 with xmmreg1 C4: rxb0_1: w_F 000:2F:11 xmmreg1 xmmreg2
  mem with xmmreg1 C4: rxb0_1: w_F 000:2F:mod xmmreg1 r/m  xmmreglo with xmmreg1 C5: r_F 000:2F:11 xmmreg1 xmmreglo  mem with xmmreg1 C5: r_F 000:2F:mod xmmreg1 r/m
VCVTSI2SS — Convert Dword Integer to Scalar Single Precision FP Value
  xmmreg2 with reg to xmmreg1 C4: rxb0_1: 0 xmmreg2 010:2A:11 xmmreg1 reg  xmmreg2 with mem to xmmreg1 C4: rxb0_1: 0 xmmreg2 010:2A:mod xmmreg1 r/m
  xmmreglo2 with reglo to xmmreg1 C5: r_xmmreglo2 010:2A:11 xmmreg1 reglo

xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:C2:11 xmmreg1 xmmreg3: imm  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:C2:mod xmmreg1 r/m: imm
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:2A:mod xmmreg1 r/m  xmmreg2 with reg to xmmreg1 C4: rxb0_1: 1 xmmreg2 010:2A:11 xmmreg1 reg
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: 1 xmmreg2 010:2A:mod xmmreg1 r/m
VCVTSS2SI — Convert Scalar Single Pr ecision FP Value to Dword Integer
  xmmreg1 to reg C4: rxb0_1: 0_F 010:2D:11 reg xmmreg1
  mem to reg C4: rxb0_1: 0_F 010:2D:mod reg r/m
  xmmreglo to reg C5: r_F 010:2D:11 reg xmmreglo  mem to reg C5: r_F 010:2D:mod reg r/m
  xmmreg1 to reg C4: rxb0_1: 1_F 010:2D:11 reg xmmreg1
  mem to reg C4: rxb0_1: 1_F 010:2D:mod reg r/m
VCVTTSS2SI — Convert with Truncation Scalar Single Precision FP Value to Dword Integer
  xmmreg1 to reg C4: rxb0_1: 0_F 010:2C:11 reg xmmreg1
  mem to reg C4: rxb0_1: 0_F 010:2C:mod reg r/m  xmmreglo to reg C5: r_F 010:2C:11 reg xmmreglo
  mem to reg C5: r_F 010:2C:mod reg r/m
  xmmreg1 to reg C4: rxb0_1: 1_F 010:2C:11 reg xmmreg1  mem to reg C4: rxb0_1: 1_F 010:2C:mod reg r/m
VDIVPS — Divide Packed Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:5E:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:5E:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:5E:11 xmmreg1 xmmreglo3Instruction and Format EncodingVol. 2D B-101INSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:5E:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:5E:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:5E:mod ymmreg1 r/m  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 100:5E:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:5E:mod ymmreg1 r/m
VDIVSS — Divide Scalar Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:5E:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:5E:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:5E:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:5E:mod xmmreg1 r/m
VLDMXCSR — Load MXCSR Register
  mem to MXCSR reg C4: rxb0_1: w_F 000:AEmod 011 r/m  mem to MXCSR reg C5: r_F 000:AEmod 011 r/m
VMAXPS — Return Maximum Packed Sing le Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:5F:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:5F:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:5F:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:5F:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:5F:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:5F:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 100:5F:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:5F:mod ymmreg1 r/m
VMAXSS — Return Maximum Scalar Sing le Precision Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:5F:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:5F:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:5F:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:5F:mod xmmreg1 r/m
VMINPS — Return Minimum Packed Sing le Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:5D:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:5D:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 000:5D:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:5D:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:5D:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:5D:mod ymmreg1 r/m  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 100:5D:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:5D:mod ymmreg1 r/m
VMINSS — Return Minimum Scalar Sing le Precision Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:5D:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:5D:mod xmmreg1 r/mInstruction and Format EncodingB-102 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with xmmreglo3 to xmmreg1 C5:  r_xmmreglo2 010:5D:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:5D:mod xmmreg1 r/m
VMOVAPS— Move Aligned Packed Sing le Precision Floating-Point Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 000:28:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 000:28:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 000:28:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 000:28:mod xmmreg1 r/m
  xmmreg1 to xmmreg2 C4: rxb0_1: w_F 000:29:11 xmmreg2 xmmreg1
  xmmreg1 to mem C4: rxb0_1: w_F 000:29:mod r/m xmmreg1  xmmreg1 to xmmreglo C5: r_F 000:29:11 xmmreglo xmmreg1
  xmmreg1 to mem C5: r_F 000:29:mod r/m xmmreg1
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 100:28:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 100:28:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 100:28:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 100:28:mod ymmreg1 r/m
  ymmreg1 to ymmreg2 C4: rxb0_1: w_F 100:29:11 ymmreg2 ymmreg1  ymmreg1 to mem C4: rxb0_1: w_F 100:29:mod r/m ymmreg1
  ymmreg1 to ymmreglo C5: r_F 100:29:11 ymmreglo ymmreg1
  ymmreg1 to mem C5: r_F 100:29:mod r/m ymmreg1
VMOVHPS — Move High Packed Single  Precision Floating-Point Values
  xmmreg1 with mem to xmmreg2 C4: rxb0_1: w xmmreg1 000:16:mod xmmreg2 r/m
  xmmreg1 with mem to xmmreglo2 C5: r_xmmreg1 000:16:mod xmmreglo2 r/m  xmmreg1 to mem C4: rxb0_1: w_F 000:17:mod r/m xmmreg1
  xmmreglo to mem C5: r_F 000:17:mod r/m xmmreglo
VMOVLHPS — Move Packed Single Precis ion Floating-Point Values Low to High
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:16:11 xmmreg1 xmmreg3
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:16:11 xmmreg1 xmmreglo3
VMOVLPS — Move Low Packed Single  Precision Floating-Point Values
  xmmreg1 with mem to xmmreg2 C4: rxb0_1: w xmmreg1 000:12:mod xmmreg2 r/m
  xmmreg1 with mem to xmmreglo2 C5: r_xmmreg1 000:12:mod xmmreglo2 r/m
  xmmreg1 to mem C4: rxb0_1: w_F 000:13:mod r/m xmmreg1  xmmreglo to mem C5: r_F 000:13:mod r/m xmmreglo
VMOVMSKPS — Extract Packed Single Precision Floating-Point Sign Mask
  xmmreg2 to reg C4: rxb0_1: w_F 000:50:11 reg xmmreg2  xmmreglo to reg C5: r_F 000:50:11 reg xmmreglo
  ymmreg2 to reg C4: rxb0_1: w_F 100:50:11 reg ymmreg2
  ymmreglo to reg C5: r_F 100:50:11 reg ymmreglo
VMOVNTPS — Store Packed Single  Precision Floating-Point Va lues Using Non-Temporal Hint
  xmmreg1 to mem C4: rxb0_1: w_F 000:2B:mod r/m xmmreg1Instruction and Format EncodingVol. 2D B-103INSTRUCTION FORMATS AND ENCODINGS
  xmmreglo to mem C5: r_F 000:2B:mod r/m xmmreglo
  ymmreg1 to mem C4: rxb0_1: w_F 100:2B:mod r/m ymmreg1
  ymmreglo to mem C5: r_F 100:2B:mod r/m ymmreglo
VMOVSS — Move Scalar Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:10:11 xmmreg1 xmmreg3
  mem to xmmreg1 C4: rxb0_1: w_F 010:10:mod xmmreg1 r/m  xmmreg2 with xmmreg3 to xmmreg1 C5: r_xmmreg2 010:10:11 xmmreg1 xmmreg3
  mem to xmmreg1 C5: r_F 010:10:mod xmmreg1 r/m
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:11:11 xmmreg1 xmmreg3  xmmreg1 to mem C4: rxb0_1: w_F 010:11:mod r/m xmmreg1
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:11:11 xmmreg1 xmmreglo3
  xmmreglo to mem C5: r_F 010:11:mod r/m xmmreglo
VMOVUPS— Move Unaligned Packed Sing le Precision Floating-Point Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 000:10:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 000:10:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 000:10:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 000:10:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 100:10:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 100:10:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 100:10:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 100:10:mod ymmreg1 r/m
  xmmreg1 to xmmreg2 C4: rxb0_1: w_F 000:11:11 xmmreg2 xmmreg1  xmmreg1 to mem C4: rxb0_1: w_F 000:11:mod r/m xmmreg1
  xmmreg1 to xmmreglo C5: r_F 000:11:11 xmmreglo xmmreg1
  xmmreg1 to mem C5: r_F 000:11:mod r/m xmmreg1  ymmreg1 to ymmreg2 C4: rxb0_1: w_F 100:11:11 ymmreg2 ymmreg1
  ymmreg1 to mem C4: rxb0_1: w_F 100:11:mod r/m ymmreg1
  ymmreg1 to ymmreglo C5: r_F 100:11:11 ymmreglo ymmreg1  ymmreg1 to mem C5: r_F 100:11:mod r/m ymmreg1
VMULPS — Multiply Packed Single  Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:59:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:59:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:59:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 000:59:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:59:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:59:mod ymmreg1 r/m

xmmreg1 to xmmreg2 C4: rxb0_1: w_F 000:11:11 xmmreg2 xmmreg1  xmmreg1 to mem C4: rxb0_1: w_F 000:11:mod r/m xmmreg1
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 100:59:11 ymmreg1 ymmreglo3  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:59:mod ymmreg1 r/m
VMULSS — Multiply Scalar Single Precision Floating-Point ValuesInstruction and Format EncodingB-104 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:59:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:59:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:59:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:59:mod xmmreg1 r/m
VORPS — Bitwise Logical OR of Sing le Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:56:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:56:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:56:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:56:mod xmmreg1 r/m  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:56:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:56:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 100:56:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:56:mod ymmreg1 r/m
VRCPPS — Compute Reciprocals of Packed Single Precision Fl oating-Point Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 000:53:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 000:53:mod xmmreg1 r/m  xmmreglo to xmmreg1 C5: r_F 000:53:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 000:53:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 100:53:11 ymmreg1 ymmreg2  mem to ymmreg1 C4: rxb0_1: w_F 100:53:mod ymmreg1 r/m
  ymmreglo to ymmreg1 C5: r_F 100:53:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 100:53:mod ymmreg1 r/m
VRCPSS — Compute Reciprocal of Scalar Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:53:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:53:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:53:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:53:mod xmmreg1 r/m
VRSQRTPS — Compute Reciprocals of  Square Roots of Packed Single  Precision Floating-Point Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 000:52:11 xmmreg1 xmmreg2
  mem to xmmreg1 C4: rxb0_1: w_F 000:52:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 000:52:11 xmmreg1 xmmreglo  mem to xmmreg1 C5: r_F 000:52:mod xmmreg1 r/m
  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 100:52:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 100:52:mod ymmreg1 r/m  ymmreglo to ymmreg1 C5: r_F 100:52:11 ymmreg1 ymmreglo
  mem to ymmreg1 C5: r_F 100:52:mod ymmreg1 r/m
VRSQRTSS — Compute Reciprocal of Square Root of  Scalar Single Precisio n Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:52:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:52:mod xmmreg1 r/mInstruction and Format EncodingVol. 2D B-105INSTRUCTION FORMATS AND ENCODINGS
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:52:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 010:52:mod xmmreg1 r/m
VSHUFPS — Shuffle Packed Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1, imm8 C4: rxb0_1: w xmmreg2 000:C6:11 xmmreg1 xmmreg3: imm
  xmmreg2 with mem to xmmreg1, imm8 C4: rx b0_1: w xmmreg2 000:C6:mod xmmreg1 r/m: imm
  xmmreglo2 with xmmreglo3 to xmmreg1, imm8 C5 : r_xmmreglo2 000:C6:11 xmmreg1 xmmreglo3: imm
  xmmreglo2 with mem to xmmreg1, imm8 C5 : r_xmmreglo2 000:C6:mod xmmreg1 r/m: imm
  ymmreg2 with ymmreg3 to ymmreg1, imm8 C4: rx b0_1: w ymmreg2 100:C6:11 ymmreg1 ymmreg3: imm
  ymmreg2 with mem to ymmreg1, imm8 C4: rxb0_1: w ymmreg2 100:C6:mod ymmreg1 r/m: imm  ymmreglo2 with ymmreglo3 to ymmreg1, imm8 C5 : r_ymmreglo2 100:C6:11 ymmreg1 ymmreglo3: imm
  ymmreglo2 with mem to ymmreg1, imm8 C5: r_ymmreglo2 100:C6:mod ymmreg1 r/m: imm
VSQRTPS — Compute Square Roots of Packed  Single Precision Fl oating-Point Values
  xmmreg2 to xmmreg1 C4: rxb0_1: w_F 000:51:11 xmmreg1 xmmreg2  mem to xmmreg1 C4: rxb0_1: w_F 000:51:mod xmmreg1 r/m
  xmmreglo to xmmreg1 C5: r_F 000:51:11 xmmreg1 xmmreglo
  mem to xmmreg1 C5: r_F 000:51:mod xmmreg1 r/m  ymmreg2 to ymmreg1 C4: rxb0_1: w_F 100:51:11 ymmreg1 ymmreg2
  mem to ymmreg1 C4: rxb0_1: w_F 100:51:mod ymmreg1 r/m
  ymmreglo to ymmreg1 C5: r_F 100:51:11 ymmreg1 ymmreglo  mem to ymmreg1 C5: r_F 100:51:mod ymmreg1 r/m
VSQRTSS — Compute Square Root of Scalar  Single Precision Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:51:11 xmmreg1 xmmreg3  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:51:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:51:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5:  r_xmmreglo2 010:51:mod xmmreg1 r/m
VSTMXCSR — Store MX CSR Register State
  MXCSR to mem C4: rxb0_1: w_F 000:AE:mod 011 r/m
  MXCSR to mem C5: r_F 000:AE:mod 011 r/m
VSUBPS — Subtract Packed Single  Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:5C:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:5C:mod xmmreg1 r/m  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:5C:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:5C:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:5C:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:5C:mod ymmreg1 r/m
  ymmreglo2 with ymmreglo3 to ymmreg1 C5: r_ymmreglo2 100:5C:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:5C:mod ymmreg1 r/m
VSUBSS — Subtract Scalar Single Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 010:5C:11 xmmreg1 xmmreg3Instruction and Format EncodingB-106 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 010:5C:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 010:5C:11 xmmreg1 xmmreglo3
  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 010:5C:mod xmmreg1 r/m
VUCOMISS — Unordered Compare Scalar Single Pr ecision Floating-Point Values and Set EFLAGS
  xmmreg2 with xmmreg1 C4: rxb0_1: w_F 000:2E:11 xmmreg1 xmmreg2
  mem with xmmreg1 C4: rxb0_1: w_F 000:2E:mod xmmreg1 r/m  xmmreglo with xmmreg1 C5: r_F 000:2E:11 xmmreg1 xmmreglo
  mem with xmmreg1 C5: r_F 000:2E:mod xmmreg1 r/m
UNPCKHPS — Unpack and Interleave High Pack ed Single Precision Floating-Point Values
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:15mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:15:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:15mod ymmreg1 r/m
UNPCKLPS — Unpack and Interleave Low Packed  Single Precision Floating-Point Value
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:14:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:14mod xmmreg1 r/m  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:14:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:14mod ymmreg1 r/m
VXORPS — Bitwise Logical XOR for Sing le Precision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_1: w xmmreg2 000:57:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_1: w xmmreg2 000:57:mod xmmreg1 r/m
  xmmreglo2 with xmmreglo3 to xmmreg1 C5: r_xmmreglo2 000:57:11 xmmreg1 xmmreglo3  xmmreglo2 with mem to xmmreg1 C5: r_xmmreglo2 000:57:mod xmmreg1 r/m
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_1: w ymmreg2 100:57:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_1: w ymmreg2 100:57:mod ymmreg1 r/m  ymmreglo2 with ymmreglo3 to ymmreg1 C5:  r_ymmreglo2 100:57:11 ymmreg1 ymmreglo3
  ymmreglo2 with mem to ymmreg1 C5: r_ymmreglo2 100:57:mod ymmreg1 r/m
VBROADCAST —Load with Broadcast
  mem to xmmreg1 C4: rxb0_2: 0_F 001:18:mod xmmreg1 r/m
  mem to ymmreg1 C4: rxb0_2: 0_F 101:18:mod ymmreg1 r/m
  mem to ymmreg1 C4: rxb0_2: 0_F 101:19:mod ymmreg1 r/m  mem to ymmreg1 C4: rxb0_2: 0_F 101:1A:mod ymmreg1 r/m
VEXTRACTF128 — Extract Packed Floating-Point Values
 ymmreg2 to xmmreg1, imm8 C4: rxb0_3: 0_F 001:19:11 xmmreg1 ymmreg2: imm  ymmreg2 to mem, imm8 C4: rxb0_3: 0_F 001:19:mod r/m ymmreg2: imm
VINSERTF128 — Insert Packed Floating-Point Values
 xmmreg3 and merge with ymmreg2 to ymmreg1, imm8 C4: rxb0_3: 0 ymmreg2101:18:11 ymmreg1 xmmreg3: imm  mem and merge with ymmreg2 to ymmreg1, imm8 C4: rxb0_3: 0 ymmreg2 101:18:mod ymmreg1 r/m: imm
VPERMILPD — Permute Double Pr ecision Floating-Point ValuesInstruction and Format EncodingVol. 2D B-107INSTRUCTION FORMATS AND ENCODINGS
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: 0 xmmreg2 001:0D:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: 0 xmmreg2 001:0D:mod xmmreg1 r/m

  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_2: 0 ymmreg2 101:0D:11 ymmreg1 ymmreg3  ymmreg2 with mem to ymmreg1 C4: rxb0_2: 0 ymmreg2 101:0D:mod ymmreg1 r/m
  xmmreg2 to xmmreg1, imm C4: rxb0_3: 0_F 001:05:11 xmmreg1 xmmreg2: imm
  mem to xmmreg1, imm C4: rxb0_3: 0_F 001:05:mod xmmreg1 r/m: imm  ymmreg2 to ymmreg1, imm C4: rxb0_3 : 0_F 101:05:11 ymmreg1 ymmreg2: imm
  mem to ymmreg1, imm C4: rxb0_3: 0_F 101:05:mod ymmreg1 r/m: imm
VPERMILPS — Permute Single Pr ecision Floating-Point Values
  xmmreg2 with xmmreg3 to xmmreg1 C4: rxb0_2: 0 xmmreg2 001:0C:11 xmmreg1 xmmreg3
  xmmreg2 with mem to xmmreg1 C4: rxb0_2: 0 xmmreg2 001:0C:mod xmmreg1 r/m
  xmmreg2 to xmmreg1, imm C4: rxb0_3: 0_F 001:04:11 xmmreg1 xmmreg2: imm  mem to xmmreg1, imm C4: rxb0_3: 0_F 001:04:mod xmmreg1 r/m: imm  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0_2: 0 ymmreg2 101:0C:11 ymmreg1 ymmreg3
  ymmreg2 with mem to ymmreg1 C4: rxb0_2: 0 ymmreg2 101:0C:mod ymmreg1 r/m
  ymmreg2 to ymmreg1, imm C4: rxb0_3 : 0_F 101:04:11 ymmreg1 ymmreg2: imm
  mem to ymmreg1, imm C4: rxb0_3: 0_F 101:04:mod ymmreg1 r/m: imm
VPERM2F128 — Permute Floating-Point Values
  ymmreg2 with ymmreg3 to ymmreg1 C4: rxb0 _3: 0 ymmreg2 101:06:11 ymmreg1 ymmreg3: imm
  ymmreg2 with mem to ymmreg1 C4: rxb0_3: 0 ymmreg2 101:06:mod ymmreg1 r/m: imm
VTESTPD/VTESTPS — Packed Bit Test
  xmmreg2 to xmmreg1 C4: rxb0_2: 0_F 001:0E:11 xmmreg2 xmmreg1  mem to xmmreg1 C4: rxb0_2: 0_F 001:0E:mod xmmreg2 r/m
  ymmreg2 to ymmreg1 C4: rxb0_2: 0_F 101:0E:11 ymmreg2 ymmreg1
  mem to ymmreg1 C4: rxb0_2: 0_F 101:0E:mod ymmreg2 r/m  xmmreg2 to xmmreg1 C4: rxb0_2: 0_F 001:0F:11 xmmreg1 xmmreg2: imm
  mem to xmmreg1 C4: rxb0_2: 0_F 001:0F:mod xmmreg1 r/m: imm
  ymmreg2 to ymmreg1 C4: rxb0_2: 0_F 101:0F:11 ymmreg1 ymmreg2: imm  mem to ymmreg1 C4: rxb0_2: 0_F 101:0F:mod ymmreg1 r/m: imm
NOTES:
1. The term “lo” refers to the lower eight registers, 0-7Instruction and Format EncodingB-108 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.17 FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS
Table B-38 shows the five different formats used for floating-point instructions. In all cases, instructions are at 
least two bytes long and begin with the bit pattern 11011.
The Mod and R/M fields of the ModR/M byte have the same interpretation as the corresponding fields of the integer 
instructions. The SIB byte and disp (displacement) are op tionally present in instructions that have Mod and R/M 
fields. Their presence depends on the values of Mod and R/M, as for integer instructions.
Table B-39 shows the formats and encodings of the floating-point instructions.Table B-38.  General Floating-Point Instruction Formats
First Byte Second Byte Optional Fields
1 11011 OPA 1 mod 1 OPB r/m s-i-b disp
2 11011 MF OPA mod OPB r/m s-i-b disp3 11011 d P OPA 1 1 OPB R ST(i)
4 11011 0 0 1 1 1 1 OP
5 11011 0 1 1 1 1 1 OP
15–11 10 9 8 7 6 5 4 3 2 1 0
MF = Memory Format
00 — 32-bit real01 — 32-bit integer
10 — 64-bit real
11 — 16-bit integer
P = Pop
0 — Do not pop stack1 — Pop stack after operation
d = Destination
0 — Destination is ST(0)
1 — Destination is ST(i)R XOR d = 0 — Destination OP Source
R XOR d = 1 — Source OP Destination
ST(i) = Register stack element i
000 = Stack Top
001 = Second stack element
 ⋅
 ⋅
 ⋅
111 = Eighth stack element
Table B-39.  Floating-Point Instruction Formats and Encodings
F2XM1 – Compute 2ST(0) – 1 11011 001 : 1111 0000
FABS – Absolute Value 11011 001 : 1110 0001
FADD – Add
   ST(0) := ST(0) + 32-bit memory 11011 000 : mod 000 r/m
ST(0) := ST(0) + 64-bit memory 11011 100 : mod 000 r/m
ST(d) := ST(0) + ST(i) 11011 d00 : 11 000 ST(i)
FADDP – Add and Pop
ST(0) := ST(0) + ST(i) 11011 110 : 11 000 ST(i)
FBLD – Load Binary Coded Decimal 11011 111 : mod 100 r/m 
FBSTP – Store Binary Coded Decimal and Pop 11011 111 : mod 110 r/m
FCHS – Change Sign 11011 001 : 1110 0000
FCLEX – Clear Exceptions 11011 011 : 1110 0010
FCOM – Compare RealVol. 2D B-109INSTRUCTION FORMATS AND ENCODINGS
32-bit memory 11011 000 : mod 010 r/m
64-bit memory 11011 100 : mod 010 r/m
ST(i) 11011 000 : 11 010 ST(i)
FCOMP – Compare Real and Pop
32-bit memory 11011 000 : mod 011 r/m
64-bit memory 11011 100 : mod 011 r/m
ST(i) 11011 000 : 11 011 ST(i)
FCOMPP – Compare Real and Pop Twice 11011 110 : 11 011 001
FCOMIP – Compare Real, Set EFLAGS, and Pop 11011 111 : 11 110 ST(i)
FCOS – Cosine of ST(0) 11011 001 : 1111 1111
FDECSTP – Decrement Stack-Top Pointer  11011 001 : 1111 0110
FDIV – Divide
ST(0) := ST(0) ÷ 32-bit memory 11011 000 : mod 110 r/m
ST(0) := ST(0) ÷ 64-bit memory 11011 100 : mod 110 r/m
ST(d) := ST(0) ÷ ST(i) 11011 d00 : 1111 R ST(i)
FDIVP – Divide and Pop
ST(0) := ST(0) ÷ ST(i) 11011 110 : 1111 1 ST(i)
FDIVR – Reverse Divide
ST(0) := 32-bit memory ÷ ST(0) 11011 000 : mod 111 r/m
ST(0) := 64-bit memory ÷ ST(0) 11011 100 : mod 111 r/m
ST(d) := ST(i) ÷ ST(0) 11011 d00 : 1111 R ST(i)
FDIVRP – Reverse Divide and Pop
ST(0) := ST(i) ÷ ST(0) 11011 110 : 1111 0 ST(i)
FFREE – Free ST(i) Register 11011 101 : 1100 0 ST(i)
FIADD – Add Integer
ST(0) := ST(0) + 16-bit memory 11011 110 : mod 000 r/m
ST(0) := ST(0) + 32-bit memory 11011 010 : mod 000 r/m
FICOM – Compare Integer
16-bit memory 11011 110 : mod 010 r/m32-bit memory 11011 010 : mod 010 r/m
FICOMP – Compare Integer and Pop
16-bit memory 11011 110 : mod 011 r/m32-bit memory 11011 010 : mod 011 r/m
FIDIV – Divide
ST(0) := ST(0) ÷ 16-bit memory 11011 110 : mod 110 r/m
ST(0) := ST(0) ÷ 32-bit memory 11011 010 : mod 110 r/m
FIDIVR – Reverse Divide
ST(0) := 16-bit memory ÷ ST(0) 11011 110 : mod 111 r/mTable B-39.  Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format EncodingB-110 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
ST(0) := 32-bit memory ÷ ST(0) 11011 010 : mod 111 r/m
FILD – Load Integer
16-bit memory 11011 111 : mod 000 r/m
32-bit memory 11011 011 : mod 000 r/m64-bit memory 11011 111 : mod 101 r/m
FIMUL– Multiply
ST(0) := ST(0) × 16-bit memory 11011 110 : mod 001 r/m
ST(0) := ST(0) × 32-bit memory 11011 010 : mod 001 r/m
FINCSTP – Increment Stack Pointer 11011 001 : 1111 0111
FINIT – Initialize Floating-Point UnitFIST – Store Integer
16-bit memory 11011 111 : mod 010 r/m
32-bit memory 11011 011 : mod 010 r/m
FISTP – Store Integer and Pop
16-bit memory 11011 111 : mod 011 r/m
32-bit memory 11011 011 : mod 011 r/m
64-bit memory 11011 111 : mod 111 r/m
FISUB – Subtract
ST(0) := ST(0) - 16-bit memory 11011 110 : mod 100 r/m
ST(0) := ST(0) - 32-bit memory 11011 010 : mod 100 r/m
FISUBR – Reverse Subtract
ST(0) := 16-bit memory − ST(0) 11011 110 : mod 101 r/m
ST(0) := 32-bit memory − ST(0) 11011 010 : mod 101 r/m
FLD – Load Real
32-bit memory 11011 001 : mod 000 r/m
64-bit memory 11011 101 : mod 000 r/m80-bit memory 11011 011 : mod 101 r/m
ST(i) 11011 001 : 11 000 ST(i)
FLD1 – Load +1.0 into ST(0) 11011 001 : 1110 1000
FLDCW – Load Control Word 11011 001 : mod 101 r/m
FLDENV – Load FPU Environment 11011 001 : mod 100 r/m
FLDL2E – Load log
2(ε) into ST(0) 11011 001 : 1110 1010
FLDL2T – Load log2(10) into ST(0) 11011 001 : 1110 1001
FLDLG2 – Load log10(2) into ST(0) 11011 001 : 1110 1100
FLDLN2 – Load logε(2) into ST(0) 11011 001 : 1110 1101
FLDPI – Load π into ST(0) 11011 001 : 1110 1011
FLDZ – Load +0.0 into ST(0) 11011 001 : 1110 1110
FMUL – MultiplyTable B-39.  Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format EncodingVol. 2D B-111INSTRUCTION FORMATS AND ENCODINGS
ST(0) := ST(0) × 32-bit memory 11011 000 : mod 001 r/m
ST(0) := ST(0) × 64-bit memory 11011 100 : mod 001 r/m
ST(d) := ST(0) × ST(i) 11011 d00 : 1100 1 ST(i)
FMULP – Multiply
ST(i) := ST(0) × ST(i) 11011 110 : 1100 1 ST(i)
FNOP – No Operation 11011 001 : 1101 0000
FPATAN – Partial Arctangent 11011 001 : 1111 0011
FPREM – Partial Remainder 11011 001 : 1111 1000
FPREM1 – Partial Remainder (IEEE) 11011 001 : 1111 0101
FPTAN – Partial Tangent 11011 001 : 1111 0010
FRNDINT – Round to Integer 11011 001 : 1111 1100
FRSTOR – Restore FPU State 11011 101 : mod 100 r/m
FSAVE – Store FPU State 11011 101 : mod 110 r/m
FSCALE – Scale 11011 001 : 1111 1101
FSIN – Sine 11011 001 : 1111 1110
FSINCOS – Sine and Cosine 11011 001 : 1111 1011
FSQRT – Square Root 11011 001 : 1111 1010
FST – Store Real
32-bit memory 11011 001 : mod 010 r/m
64-bit memory 11011 101 : mod 010 r/mST(i) 11011 101 : 11 010 ST(i)
FSTCW – Store Control Word 11011 001 : mod 111 r/m
FSTENV – Store FPU Environment 11011 001 : mod 110 r/m
FSTP – Store Real and Pop
32-bit memory 11011 001 : mod 011 r/m
64-bit memory 11011 101 : mod 011 r/m80-bit memory 11011 011 : mod 111 r/m
ST(i) 11011 101 : 11 011 ST(i)
FSTSW – Store Status Word into AX 11011 111 : 1110 0000
FSTSW – Store Status Word into Memory 11011 101 : mod 111 r/m
FSUB – Subtract
ST(0) := ST(0) – 32-bit memory 11011 000 : mod 100 r/m
ST(0) := ST(0) – 64-bit memory 11011 100 : mod 100 r/m
ST(d) := ST(0) – ST(i) 11011 d00 : 1110 R ST(i)
FSUBP – Subtract and Pop
ST(0) := ST(0) – ST(i) 11011 110 : 1110 1 ST(i)
FSUBR – Reverse Subtract

ST(0) := 32-bit memory – ST(0) 11011 000 : mod 101 r/mTable B-39.  Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format EncodingB-112 Vol. 2DINSTRUCTION FORMATS AND ENCODINGS
B.18 VMX INSTRUCTIONS
Table B-40 describes virtual-machine extensions (VMX).ST(0) := 64-bit memory – ST(0) 11011 100 : mod 101 r/m
ST(d) := ST(i) – ST(0) 11011 d00 : 1110 R ST(i)
FSUBRP – Reverse Subtract and Pop
ST(i) := ST(i) – ST(0) 11011 110 : 1110 0 ST(i)
FTST – Test 11011 001 : 1110 0100
FUCOM – Unordered Compare Real 11011 101 : 1110 0 ST(i)
FUCOMP – Unordered Compare Real and Pop 11011 101 : 1110 1 ST(i)
FUCOMPP – Unordered Compare Real and Pop Twice 11011 010 : 1110 1001
FUCOMI – Unorderd Compare Real and Set EFLAGS 11011 011 : 11 101 ST(i)
FUCOMIP – Unorderd Compare Real, Set EFLAGS, and Pop 11011 111 : 11 101 ST(i)
FXAM – Examine 11011 001 : 1110 0101
FXCH – Exchange ST(0) and ST(i) 11011 001 : 1100 1 ST(i)
FXTRACT – Extract Exponent and Significand 11011 001 : 1111 0100
FYL2X – ST(1) × log2(ST(0)) 11011 001 : 1111 0001
FYL2XP1 – ST(1) × log2(ST(0) + 1.0) 11011 001 : 1111 1001
FWAIT – Wait until FPU Ready 1001 1011 (same instruction as WAIT)
Table B-40.  Encodings for VMX Instructions
INVEPT—Invalidate Cached EPT Mappings
Descriptor m128 according to reg 01100110 00001111 00111000 10000000: mod reg r/m
INVVPID—Invalidate Cached VPID Mappings
Descriptor m128 according to reg 01100110 00001111 00111000 10000001: mod reg r/m
VMCALL—Call to VM Monitor
Call VMM: causes VM exit 00001111 00000001 11000001
VMCLEAR—Clear Virtual-Machine Control Structure
mem32:VMCS_data_ptr 01100110 00001111 11000111: mod 110 r/mmem64:VMCS_data_ptr 01100110 00001111 11000111: mod 110 r/m
VMFUNC—Invoke VM Function
Invoke VM function specified in EAX 00001111 00000001 11010100
VMLAUNCH—Launch Virtual Machine
Launch VM managed by Current_VMCS 00001111 00000001 11000010
VMRESUME—Resume Virtual Machine
Resume VM managed by Current_VMCS 00001111 00000001 11000011
VMPTRLD—Load Pointer to Virtual-Machine Control Structure
mem32 to Current_VMCS_ptr 00001111 11000111: mod 110 r/mTable B-39.  Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format EncodingVol. 2D B-113INSTRUCTION FORMATS AND ENCODINGS
B.19 SMX INSTRUCTIONS
Table B-38 describes Safer Mode extensions (VMX). GETSEC leaf functions are selected by a valid value in EAX on input.mem64 to Current_VMCS_ptr 00001111 11000111: mod 110 r/m
VMPTRST—Store Pointer to Virt ual-Machine Control Structure
Current_VMCS_ptr to mem32 00001111 11000111: mod 111 r/mCurrent_VMCS_ptr to mem64 00001111 11000111: mod 111 r/m
VMREAD—Read Field from Virtua l-Machine Control Structure
r32 (VMCS_fieldn)  to r32
r32 (VMCS_fieldn) to mem32
r64 (VMCS_fieldn) to r64
r64 (VMCS_fieldn) to mem6400001111 01111000: 11 reg2 reg1
00001111 01111000: mod r32 r/m
00001111 01111000: 11 reg2 reg1
00001111 01111000: mod r64 r/m
VMWRITE—Write Field to Virtual-Machine Control Structure
r32 to r32 (VMCS_fieldn)
mem32 to r32 (VMCS_fieldn)
r64 to r64 (VMCS_fieldn)
mem64 to r64 (VMCS_fieldn)00001111 01111001: 11 reg1 reg2
00001111 01111001: mod r32 r/m
00001111 01111001: 11 reg1 reg200001111 01111001: mod r64 r/m
VMXOFF—Leave VMX Operation
Leave VMX. 00001111 00000001 11000100
VMXON—Enter VMX Operation
Enter VMX. 11110011 000011111 11000111: mod 110 r/m
Table B-41.  Encodings for SMX Instructions
GETSEC—GETSEC leaf functions are sele cted by the value in EAX on input
GETSEC[CAPABILITIES] 00001111 00110111 (EAX= 0)
GETSEC[ENTERACCS] 00001111 00110111 (EAX= 2)
GETSEC[EXITAC] 00001111 00110111 (EAX= 3)
GETSEC[SENTER] 00001111 00110111 (EAX= 4)
GETSEC[SEXIT] 00001111 00110111 (EAX= 5)
GETSEC[PARAMETERS] 00001111 00110111 (EAX= 6)
GETSEC[SMCTRL] 00001111 00110111 (EAX= 7)
GETSEC[WAKEUP] 00001111 00110111 (EAX= 8)Table B-40.  Encodings for VMX Instructions
Instruction and Format EncodingB-114 Vol. 2DINSTRUCTION FORMATS AND ENCODINGSVol. 2D C-1APPENDIX C
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
The two tables in this appendix itemize the Intel C/C ++ compiler intrinsics and functional equivalents for the Intel 
MMX technology, SSE, SSE2, SSE3, and SSSE3 instructions.
There may be additional intrinsics that do not have an in struction equivalent. It is strongly recommended that the 
reader reference the compiler documentation for the comp lete list of supported intrinsics. Please refer to 
http://www.intel.com/support/performancetools/. 
Table C-1 presents simple intrinsics and Table C-2 presents  composite intrinsics. Some intrinsics are “composites” 
because they require more than one instruction to implement them.
Intel C/C ++ Compiler intrinsic names reflect the following naming conventions:
_mm_ <intrin_op >_<suffix >
where:
<intrin_op > Indicates the intrinsics basic operation; for example, add for addition and sub for subtrac-
tion
<suffix > Denotes the type of data operated on by the instruction. The first one or two letters of 
each suffix denotes whether the data is packed  (p), extended packed (ep), or scalar (s). 
The remaining letters denote the type:
s single-precision floating-point
d double precision floating-point
i128 signed 128-bit integeri64 signed 64-bit integer
u64 unsigned 64-bit integer
i32 signed 32-bit integeru32 unsigned 32-bit integer
i16 signed 16-bit integer
u16 unsigned 16-bit integeri8 signed 8-bit integer
u8 unsigned 8-bit integer
The variable r is generally used for the intrinsic's return value. A number appended to a variable name indicates the 
element of a packed object. For example, r0 is the lowest word of r.
The packed values are represented in right-to-left order,  with the lowest value being used for scalar operations. 
Consider the following example operation:
double a[2] = {1.0, 2.0};
__m128d t = _mm_load_pd(a);
The result is the same as either of the following:
__m128d t = _mm_set_pd(2.0, 1.0);
__m128d t = _mm_setr_pd(1.0, 2.0);
In other words, the XMM register that holds the value t will look as follows:
0 127 64 632.0 1.0C-2 Vol. 2DINTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTS
The “scalar” element is 1.0. Due to the nature of the in struction, some intrinsics require their arguments to be 
immediates (constant integer literals).
To use an intrinsic in your code, inse rt a line with the following syntax:
data_type intrinsic_ name (parameters)
Where:
data_type Is the return data type, which can be either void, int, __m64, __m128, __m128d, or 
__m128i. Only the _mm_empty intrinsic returns void.
intrinsic_name Is the name of the intrinsic, which behaves like a function that you can use in your C/C ++ 
code instead of in-lining the actual instruction.
parameters Represents the parameters required by each intrinsic.
C.1 SIMPLE INTRINSICS
NOTE
For detailed descriptions of the intrinsics in Tabl e C-1, see the corresponding mnemonic in Chapter 
3, “Instruction Set Reference, A-L‚” of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2A; Chapter 4, “Instructi on Set Reference, M-U‚” of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 2B; Ch apter 5, “Instruction Se t Reference, V,” of the 
Intel® 64 and IA-32 Architectures Software Deve loper’s Manual, Volume 2C; or Chapter 6, 
“Instruction Set Referenc e, W-Z,” of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2D. 
Table C-1.  Simple Intrinsics
Mnemonic Intrinsic
ADDPD __m128d _mm_add_pd(__m128d a, __m128d b)ADDPS __m128 _mm_add_ps(__m128 a, __m128 b)ADDSD __m128d _mm_add_sd(__m128d a, __m128d b)ADDSS __m128 _mm_add_ss(__m128 a, __m128 b)ADDSUBPD __m128d _mm_addsub_pd(__m128d a, __m128d b)ADDSUBPS __m128 _mm_addsub_ps(__m128 a, __m128 b)AESDEC  __m128i _mm_aesdec (__m128i, __m128i)AESDECLAST  __m128i _mm_aesdeclast (__m128i, __m128i)AESENC  __m128i _mm_aesenc (__m128i, __m128i)AESENCLAST __m128i _mm_aesenclast (__m128i, __m128i)AESIMC __m128i _mm_aesimc (__m128i)AESKEYGENASSIST __m128i _mm_aesimc (__m128i, const int)ANDNPD __m128d _mm_andnot_pd(__m128d a, __m128d b)ANDNPS __m128 _mm_andnot_ps(__m128 a, __m128 b)ANDPD __m128d _mm_and_pd(__m128d a, __m128d b)ANDPS __m128 _mm_and_ps(__m128 a, __m128 b)BLENDPD __m128d _mm_blend_pd(__m128d v1, __m128d v2, const int mask)BLENDPS __m128 _mm_blend_ps(__m128 v1, __m128 v2, const int mask)BLENDVPD __m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3)BLENDVPS __m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3)CLFLUSH void _mm_clflush(void const *p)Vol. 2D C-3INTEL® C/C++ COMPILER INTRINSI CS AND FUNCTIONAL EQUIVALENTS
CMPPD __m128d _mm_cmpeq_pd(__m128d a, __m128d b)

__m128d _mm_cmplt_pd(__m128d a, __m128d b)__m128d _mm_cmple_pd(__m128d a, __m128d b)__m128d _mm_cmpgt_pd(__m128d a, __m128d b)__m128d _mm_cmpge_pd(__m128d a, __m128d b)__m128d _mm_cmpneq_pd(__m128d a, __m128d b)__m128d _mm_cmpnlt_pd(__m128d a, __m128d b)__m128d _mm_cmpngt_pd(__m128d a, __m128d b)__m128d _mm_cmpnge_pd(__m128d a, __m128d b)__m128d _mm_cmpord_pd(__m128d a, __m128d b)__m128d _mm_cmpunord_pd(__m128d a, __m128d b)__m128d _mm_cmpnle_pd(__m128d a, __m128d b)
CMPPS __m128 _mm_cmpeq_ps(__m128 a, __m128 b)
__m128 _mm_cmplt_ps(__m128 a, __m128 b)__m128 _mm_cmple_ps(__m128 a, __m128 b)__m128 _mm_cmpgt_ps(__m128 a, __m128 b)__m128 _mm_cmpge_ps(__m128 a, __m128 b)__m128 _mm_cmpneq_ps(__m128 a, __m128 b)__m128 _mm_cmpnlt_ps(__m128 a, __m128 b)__m128 _mm_cmpngt_ps(__m128 a, __m128 b)__m128 _mm_cmpnge_ps(__m128 a, __m128 b)__m128 _mm_cmpord_ps(__m128 a, __m128 b)__m128 _mm_cmpunord_ps(__m128 a, __m128 b)__m128 _mm_cmpnle_ps(__m128 a, __m128 b)
CMPSD __m128d _mm_cmpeq_sd(__m128d a, __m128d b)
__m128d _mm_cmplt_sd(__m128d a, __m128d b)__m128d _mm_cmple_sd(__m128d a, __m128d b)__m128d _mm_cmpgt_sd(__m128d a, __m128d b)__m128d _mm_cmpge_sd(__m128d a, __m128d b)__m128 _mm_cmpneq_sd(__m128d a, __m128d b)__m128 _mm_cmpnlt_sd(__m128d a, __m128d b)__m128d _mm_cmpnle_sd(__m128d a, __m128d b)__m128d _mm_cmpngt_sd(__m128d a, __m128d b)__m128d _mm_cmpnge_sd(__m128d a, __m128d b)__m128d _mm_cmpord_sd(__m128d a, __m128d b)__m128d _mm_cmpunord_sd(__m128d a, __m128d b)
CMPSS __m128 _mm_cmpeq_ss(__m128 a, __m128 b)
__m128 _mm_cmplt_ss(__m128 a, __m128 b)__m128 _mm_cmple_ss(__m128 a, __m128 b)__m128 _mm_cmpgt_ss(__m128 a, __m128 b)__m128 _mm_cmpge_ss(__m128 a, __m128 b)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicC-4 Vol. 2DINTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTS
__m128 _mm_cmpneq_ss(__m128 a, __m128 b)
__m128 _mm_cmpnlt_ss(__m128 a, __m128 b)__m128 _mm_cmpnle_ss(__m128 a, __m128 b)__m128 _mm_cmpngt_ss(__m128 a, __m128 b)__m128 _mm_cmpnge_ss(__m128 a, __m128 b)__m128 _mm_cmpord_ss(__m128 a, __m128 b)__m128 _mm_cmpunord_ss(__m128 a, __m128 b)
COMISD int _mm_comieq_sd(__m128d a, __m128d b)
int _mm_comilt_sd(__m128d a, __m128d b)int _mm_comile_sd(__m128d a, __m128d b)int _mm_comigt_sd(__m128d a, __m128d b)int _mm_comige_sd(__m128d a, __m128d b)int _mm_comineq_sd(__m128d a, __m128d b)
COMISS int _mm_comieq_ss(__m128 a, __m128 b)
int _mm_comilt_ss(__m128 a, __m128 b)int _mm_comile_ss(__m128 a, __m128 b)int _mm_comigt_ss(__m128 a, __m128 b)int _mm_comige_ss(__m128 a, __m128 b)int _mm_comineq_ss(__m128 a, __m128 b)
CRC32 unsigned int _mm_crc32_u8(unsigned int crc, unsigned char data)
unsigned int _mm_crc32_u16(unsigned int crc, unsigned short data)unsigned int _mm_crc32_u32(unsigned int crc, unsigned int data)unsigned __int64 _mm_crc32_u64(unsigned  __int64 crc, unsigned __int64 data)
CVTDQ2PD __m128d _mm_cvtepi32_pd(__m128i a)CVTDQ2PS __m128 _mm_cvtepi32_ps(__m128i a)CVTPD2DQ __m128i _mm_cvtpd_epi32(__m128d a)CVTPD2PI __m64 _mm_cvtpd_pi32(__m128d a)CVTPD2PS __m128 _mm_cvtpd_ps(__m128d a)CVTPI2PD __m128d _mm_cvtpi32_pd(__m64 a)CVTPI2PS __m128 _mm_cvt_pi2ps(__m128 a, __m64 b)
__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)
CVTPS2DQ __m128i _mm_cvtps_epi32(__m128 a)CVTPS2PD __m128d _mm_cvtps_pd(__m128 a)CVTPS2PI __m64 _mm_cvt_ps2pi(__m128 a)
__m64 _mm_cvtps_pi32(__m128 a)
CVTSD2SI int _mm_cvtsd_si32(__m128d a)CVTSD2SS __m128 _mm_cvtsd_ss(__m128 a, __m128d b)CVTSI2SD __m128d _mm_cvtsi32_sd(__m128d a, int b)CVTSI2SS __m128 _mm_cvt_si2ss(__m128 a, int b)
__m128 _mm_cvtsi32_ss(__m128 a, int b)__m128 _mm_cvtsi64_ss(__m128 a, __int64 b)
CVTSS2SD __m128d _mm_cvtss_sd(__m128d a, __m128 b)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicVol. 2D C-5INTEL® C/C++ COMPILER INTRINSI CS AND FUNCTIONAL EQUIVALENTS
CVTSS2SI int _mm_cvt_ss2si(__m128 a)
int _mm_cvtss_si32(__m128 a)
CVTTPD2DQ __m128i _mm_cvttpd_epi32(__m128d a)CVTTPD2PI __m64 _mm_cvttpd_pi32(__m128d a)CVTTPS2DQ __m128i _mm_cvttps_epi32(__m128 a)CVTTPS2PI __m64 _mm_cvtt_ps2pi(__m128 a)
__m64 _mm_cvttps_pi32(__m128 a)
CVTTSD2SI int _mm_cvttsd_si32(__m128d a)CVTTSS2SI int _mm_cvtt_ss2si(__m128 a)
int _mm_cvttss_si32(__m128 a)
__m64 _mm_cvtsi32_si64(int i)int _mm_cvtsi64_si32(__m64 m)
DIVPD __m128d _mm_div_pd(__m128d a, __m128d b)DIVPS __m128 _mm_div_ps(__m128 a, __m128 b)DIVSD __m128d _mm_div_sd(__m128d a, __m128d b)DIVSS __m128 _mm_div_ss(__m128 a, __m128 b)DPPD __m128d _mm_dp_pd(__m128d a, __m128d b, const int mask)DPPS __m128 _mm_dp_ps(__m128 a, __m128 b, const int mask)EMMS void _mm_empty()EXTRACTPS int _mm_extract_ps (__m128 src, const int ndx)
HADDPD __m128d _mm_hadd_pd(__m128d a, __m128d b)HADDPS __m128 _mm_hadd_ps(__m128 a, __m128 b)HSUBPD __m128d _mm_hsub_pd(__m128d a, __m128d b)HSUBPS __m128 _mm_hsub_ps(__m128 a, __m128 b)INSERTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int ndx)
LDDQU __m128i _mm_lddqu_si128(__m128i const *p)LDMXCSR __mm_setcsr(unsigned int i)LFENCE void _mm_lfence(void)MASKMOVDQU void _mm_maskmoveu_si128( __m128i d, __m128i n, char *p)
MASKMOVQ void _mm_maskmove_si 64(__m64 d, __m64 n, char *p)
MAXPD __m128d _mm_max_pd(__m128d a, __m128d b)MAXPS __m128 _mm_max_ps(__m128 a, __m128 b)MAXSD __m128d _mm_max_sd(__m128d a, __m128d b)MAXSS __m128 _mm_max_ss(__m128 a, __m128 b)MFENCE void _mm_mfence(void)MINPD __m128d _mm_min_pd(__m128d a, __m128d b)MINPS __m128 _mm_min_ps(__m128 a, __m128 b)MINSD __m128d _mm_min_sd(__m128d a, __m128d b)MINSS __m128 _mm_min_ss(__m128 a, __m128 b)MONITOR void _mm_monitor(void const *p, unsigned extensions, unsigned hints)MOVAPD __m128d _mm_load_pd(double * p)
void_mm_store_pd(double *p, __m128d a)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicC-6 Vol. 2DINTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTS
MOVAPS __m128 _mm_load_ps(float * p)
void_mm_store_ps(float *p, __m128 a)
MOVD __m128i _mm_cvtsi32_si128(int a)
int _mm_cvtsi128_si32(__m128i a)__m64 _mm_cvtsi32_si64(int a)int _mm_cvtsi64_si32(__m64 a)
MOVDDUP __m128d _mm_movedup_pd(__m128d a)
__m128d _mm_loaddup_pd(double const * dp)
MOVDQA __m128i _mm_load_si128(__m128i * p)
void_mm_store_si128(__m128i *p, __m128i a)
MOVDQU __m128i _mm_loadu_si128(__m128i * p)
void_mm_storeu_si128(__m128i *p, __m128i a)
MOVDQ2Q __m64 _mm_movepi64_pi64(__m128i a)MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)MOVHPD __m128d _mm_loadh_pd(__m128d a, double * p)
void _mm_storeh_pd(double * p, __m128d a)
MOVHPS __m128 _mm_loadh_pi(__m128 a, __m64 * p)
void _mm_storeh_pi(__m64 * p, __m128 a)
MOVLPD __m128d _mm_loadl_pd(__m128d a, double * p)
void _mm_storel_pd(double * p, __m128d a)
MOVLPS __m128 _mm_loadl_pi(__m128 a, __m64 *p)
void_mm_storel_pi(__m64 * p, __m128 a)
MOVLHPS __m128 _mm_movelh_ps(__m128 a, __m128 b)MOVMSKPD int _mm_movemask_pd(__m128d a)MOVMSKPS int _mm_movemask_ps(__m128 a)MOVNTDQA __m128i _mm_stream_load_si128(__m128i *p)MOVNTDQ void_mm_stream_si128(__m128i * p, __m128i a)MOVNTPD void_mm_stream_pd(double * p, __m128d a)MOVNTPS void_mm_stream_ps(float * p, __m128 a)MOVNTI void_mm_stream_si32(int * p, int a)MOVNTQ void_mm_stream_pi(__m64 * p, __m64 a)MOVQ __m128i _mm_loadl_epi64(__m128i * p)
void_mm_storel_epi64(_m128i * p, __m128i a)__m128i _mm_move_epi64(__m128i a)
MOVQ2DQ __m128i _mm_movpi64_epi64(__m64 a)MOVSD __m128d _mm_load_sd(double * p)
void_mm_store_sd(double * p, __m128d a)__m128d _mm_move_sd(__m128d a, __m128d b)
MOVSHDUP __m128 _mm_movehdup_ps(__m128 a)MOVSLDUP __m128 _mm_moveldup_ps(__m128 a)MOVSS __m128 _mm_load_ss(float * p)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicVol. 2D C-7INTEL® C/C++ COMPILER INTRINSI CS AND FUNCTIONAL EQUIVALENTS
void_mm_store_ss(float * p, __m128 a)
__m128 _mm_move_ss(__m128 a, __m128 b)
MOVUPD __m128d _mm_loadu_pd(double * p)
void_mm_storeu_pd(double *p, __m128d a) 
MOVUPS __m128 _mm_loadu_ps(float * p)
void_mm_storeu_ps(float *p, __m128 a) 
MPSADBW __m128i _mm_mpsadbw_epu8(__m128i s1, __m128i s2, const int mask)MULPD __m128d _mm_mul_pd(__m128d a, __m128d b)MULPS __m128 _mm_mul_ss(__m128 a, __m128 b)MULSD __m128d _mm_mul_sd(__m128d a, __m128d b)MULSS __m128 _mm_mul_ss(__m128 a, __m128 b)MWAIT void _mm_mwait(unsigned extensions, unsigned hints)ORPD __m128d _mm_or_pd(__m128d a, __m128d b)ORPS __m128 _mm_or_ps(__m128 a, __m128 b)PABSB  __m64 _mm_abs_pi8 (__m64 a)
 __m128i _mm_abs_epi8 (__m128i a)
PABSD  __m64 _mm_abs_pi32 (__m64 a)
 __m128i _mm_abs_epi32 (__m128i a)
PABSW  __m64 _mm_abs_pi16 (__m64 a)
 __m128i _mm_abs_epi16 (__m128i a)
PACKSSWB __m128i _mm_packs_epi16(__m128i m1, __m128i m2)PACKSSWB __m64 _mm_packs_ pi16(__m64 m1, __m64 m2)
PACKSSDW __m128i _mm_packs_epi32 (__m128i m1, __m128i m2)PACKSSDW __m64 _mm_packs_pi32 (__m64 m1, __m64 m2)PACKUSDW __m128i _mm_packus_epi 32(__m128i m1, __m128i m2)
PACKUSWB __m128i _mm_packus_epi 16(__m128i m1, __m128i m2)
PACKUSWB __m64 _mm_packs_ pu16(__m64 m1, __m64 m2)
PADDB __m128i _mm_add_epi8(__m128i m1, __m128i m2)PADDB __m64 _mm_add_pi8(__m64 m1, __m64 m2)PADDW __m128i _mm_add_epi16(__m128i m1, __m128i m2)PADDW __m64 _mm_add_pi16(__m64 m1, __m64 m2)PADDD __m128i _mm_add_epi32(__m128i m1, __m128i m2)PADDD __m64 _mm_add_pi32(__m64 m1, __m64 m2)PADDQ __m128i _mm_add_epi64(__m128i m1, __m128i m2)PADDQ __m64 _mm_add_si64(__m64 m1, __m64 m2)PADDSB __m128i _mm_adds_epi8(__m128i m1, __m128i m2)PADDSB __m64 _mm_adds_pi8(__m64 m1, __m64 m2)PADDSW __m128i _mm_adds_epi16(__m128i m1, __m128i m2)PADDSW __m64 _mm_adds_pi16(__m64 m1, __m64 m2)PADDUSB __m128i _mm_adds_epu8(__m128i m1, __m128i m2)PADDUSB __m64 _mm_adds_pu8(__m64 m1, __m64 m2)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicC-8 Vol. 2DINTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTS
PADDUSW __m128i _mm_adds_epu16(__m128i m1, __m128i m2)
PADDUSW __m64 _mm_adds_pu16(__m64 m1, __m64 m2)PALIGNR  __m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)
 __m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)

PAND __m128i _mm_and_si128(__m128i m1, __m128i m2)PAND __m64 _mm_and_si64(__m64 m1, __m64 m2)PANDN __m128i _mm_andnot_si128(__m128i m1, __m128i m2)PANDN __m64 _mm_andnot_si64(__m64 m1, __m64 m2)PAUSE void _mm_pause(void)PAVGB __m128i _mm_avg_epu8(__m128i a, __m128i b)PAVGB __m64 _mm_avg_pu8(__m64 a, __m64 b)PAVGW __m128i _mm_avg_epu16(__m128i a, __m128i b)PAVGW __m64 _mm_avg_pu16(__m64 a, __m64 b)PBLENDVB __m128i _mm_blendv_epi (__m128i v1, __m128i v2, __m128i mask)PBLENDW __m128i _mm_blend_epi16(__m1 28i v1, __m128i v2, const int mask)
PCLMULQDQ __m128i _mm_clmulepi64_s i128 (__m128i, __m128i, const int)
PCMPEQB __m128i _mm_cmpeq_epi8(__m128i m1, __m128i m2)PCMPEQB __m64 _mm_cmpeq_pi8(__m64 m1, __m64 m2)PCMPEQQ __m128i _mm_cmpeq_epi64(__m128i a, __m128i b)PCMPEQW __m128i _mm_cmpeq_epi16 (__m128i m1, __m128i m2)PCMPEQW __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)PCMPEQD __m128i _mm_cmpeq_epi32(__m128i m1, __m128i m2)PCMPEQD __m64 _mm_cmpeq_pi32(__m64 m1, __m64 m2)PCMPESTRI int _mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)int _mm_cmpestrc (__m128i a, int la , __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la , __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la , __m128i b, int lb, const int mode)
int _mm_cmpestrz (__m128i a, int la , __m128i b, int lb , const int mode)
PCMPESTRM __m128i _mm_cmpestrm (__m128i a, int la, __m128i b, in t lb, const int mode)
PCMPGTB __m128i _mm_cmpgt_epi8 (__m128i m1, __m128i m2)PCMPGTB __m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)PCMPGTW __m128i _mm_cmpgt_epi16(__m128i m1, __m128i m2)PCMPGTW __m64 _mm_cmpgt_pi16 (__m64 m1, __m64 m2)PCMPGTD __m128i _mm_cmpgt_epi32(__m128i m1, __m128i m2)PCMPGTD __m64 _mm_cmpgt_pi32(__m64 m1, __m64 m2)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicVol. 2D C-9INTEL® C/C++ COMPILER INTRINSI CS AND FUNCTIONAL EQUIVALENTS
PCMPISTRI __m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la , __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la , __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la , __m128i b, int lb , const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)int _mm_cmpistrz (__m128i a, __m128i b, const int mode)
PCMPISTRM __m128i _mm_cmpi strm (__m128i a, __m128i b, const int mode)
int _mm_cmpistra (__m128i a,  __m128i b, const int mode)
int _mm_cmpistrc (__m128i a, __m128i b, const int mode)int _mm_cmpistro (__m128i a, __m128i b, const int mode)int _mm_cmpistrs (__m128i a, __m128i b, const int mode)
int _mm_cmpistrz (__m128i a, __m128i b, const int mode)
PCMPGTQ __m128i _mm_cmpgt_epi64(__m128i a, __m128i b)PEXTRB int _mm_extract_epi8 (_ _m128i src, const int ndx)
PEXTRD int _mm_extract_epi32 (__m128i src, const int ndx)
PEXTRQ __int64 _mm_extract_epi64 (__m128i src, const int ndx)PEXTRW int _mm_extract_ epi16(__m128i a, int n)
PEXTRW int _mm_extract_pi16(__m64 a, int n)
int _mm_extract_epi16 (__m128i src, int ndx)
PHADDD  __m64 _mm_hadd_pi32 (__m64 a, __m64 b)
 __m128i _mm_hadd_epi32 (__m128i a, __m128i b)
PHADDSW  __m64 _mm_hadds _pi16 (__m64 a, __m64 b)
 __m128i _mm_hadds_epi16 (__m128i a, __m128i b)
__m128i _mm_hadd_epi16 (__m128i a, __m128i b)
PHMINPOSUW __m128i _mm_minpos_epu16( __m128i packed_words)PHSUBD  __m64 _mm_hsub_pi32 (__m64 a, __m64 b)
 __m128i _mm_hsub_epi32 (__m128i a, __m128i b)
PHSUBSW  __m64 _mm_hsubs_pi16 (__m64 a, __m64 b)
 __m128i _mm_hsubs_epi16 (__m128i a, __m128i b)
PHSUBW  __m64 _mm_hsub_pi16 (__m64 a, __m64 b)
 __m128i _mm_hsub_epi16 (__m128i a, __m128i b)
PINSRB __m128i _mm_insert_epi8(__m128i s1, int s2, const int ndx)PINSRD __m128i _mm_insert_epi32(__m128i s2, int s, const int ndx)PINSRQ __m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx)PINSRW __m128i _mm_insert_epi16(__m128i a, int d, int n)PINSRW __m64 _mm_insert_pi1 6(__m64 a, int d, int n)
PMADDUBSW  __m64 _mm_maddubs_pi16 (__m64 a, __m64 b)
 __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)
PMADDWD __m128i _mm_madd_epi16(__m128i m1 __m128i m2)PMADDWD __m64 _mm_madd_pi16(__m64 m1, __m64 m2)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicC-10 Vol. 2DINTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTS
PMAXSB __m128i _mm_max_epi8( __m128i a, __m128i b)
PMAXSD __m128i _mm_max_epi32( __m128i a, __m128i b)PMAXSW __m128i _mm_max_epi16(__m128i a, __m128i b)PMAXSW __m64 _mm_max_pi16(__m64 a, __m64 b)PMAXUB __m128i _mm_max_epu8(__m128i a, __m128i b)PMAXUB __m64 _mm_max_pu8(__m64 a, __m64 b)PMAXUD __m128i _mm_max_epu32( __m128i a, __m128i b)PMAXUW __m128i _mm_max_epu16( __m128i a, __m128i b)PMINSB _m128i _mm_min_epi8( __m128i a, __m128i b)PMINSD __m128i _mm_min_epi32( __m128i a, __m128i b)PMINSW __m128i _mm_min_epi16(__m128i a, __m128i b)PMINSW __m64 _mm_min_pi16(__m64 a, __m64 b)PMINUB __m128i _mm_min_epu8(__m128i a, __m128i b)PMINUB __m64 _mm_min_pu8(__m64 a, __m64 b)PMINUD __m128i _mm_min_epu32 ( __m128i a, __m128i b)PMINUW __m128i _mm_min_epu16 ( __m128i a, __m128i b)PMOVMSKB int _mm_movemask_epi8(__m128i a)PMOVMSKB int _mm_movemask_pi8(__m64 a)PMOVSXBW __m128i _mm_ cvtepi8_epi16( __m128i a)PMOVSXBD __m128i _mm_ cvtepi8_epi32( __m128i a)PMOVSXBQ __m128i _mm_ cvtepi8_epi64( __m128i a)PMOVSXWD __m128i _mm_ cvtepi16_epi32( __m128i a)PMOVSXWQ __m128i _mm_ cvtepi16_epi64( __m128i a)PMOVSXDQ __m128i _mm_ cvtepi32_epi64( __m128i a)PMOVZXBW __m128i _mm_ cvtepu8_epi16( __m128i a)PMOVZXBD __m128i _mm_ cvtepu8_epi32( __m128i a)PMOVZXBQ __m128i _mm_ cvtepu8_epi64( __m128i a)PMOVZXWD __m128i _mm_ cvtepu16_epi32( __m128i a)PMOVZXWQ __m128i _mm_ cvtepu16_epi64( __m128i a)PMOVZXDQ __m128i _mm_ cvtepu32_epi64( __m128i a)PMULDQ __m128i _mm_mul_epi32( __m128i a, __m128i b)PMULHRSW __m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)
__m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)
PMULHUW __m128i _mm_mulhi_epu16(__m128i a, __m128i b)PMULHUW __m64 _mm_mulhi_pu16(__m64 a, __m64 b)PMULHW __m128i _mm_mulhi_epi16(__m128i m1, __m128i m2)PMULHW __m64 _mm_mulhi_pi16(__m64 m1, __m64 m2)PMULLUD __m128i _mm_mullo_e pi32(__m128i a, __m128i b)
PMULLW __m128i _mm_mullo_epi16(__m128i m1, __m128i m2)PMULLW __m64 _mm_mullo_pi16(__m64 m1, __m64 m2)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicVol. 2D C-11INTEL® C/C++ COMPILER INTRINSI CS AND FUNCTIONAL EQUIVALENTS
PMULUDQ __m64 _mm_mul_su32(__m64 m1, __m64 m2)
__m128i _mm_mul_epu32(__m128i m1, __m128i m2)
POPCNT int _mm_popcnt_u32(unsigned int a)
int64_t _mm_popcnt_u64(unsigned __int64 a)
POR __m64 _mm_or_si64(__m64 m1, __m64 m2)POR __m128i _mm_or_si128(__m128i m1, __m128i m2)PREFETCHh void _mm_prefetch(char *a, int sel)PSADBW __m128i _mm_sad_epu8(__m128i a, __m128i b)PSADBW __m64 _mm_sad_pu8(__m64 a, __m64 b)PSHUFB  __m64 _mm_shuffle_pi8 (__m64 a, __m64 b)
 __m128i _mm_shuffle_epi8 (__m128i a, __m128i b)
PSHUFD __m128i _mm_shuffle_epi32(__m128i a, int n)PSHUFHW __m128i _mm_shufflehi_epi16(__m128i a, int n)PSHUFLW __m128i _mm_shufflelo_epi16(__m128i a, int n)PSHUFW __m64 _mm_shuffle_pi16(__m64 a, int n)PSIGNB  __m64 _mm_sign_pi8 (__m64 a, __m64 b)
 __m128i _mm_sign_epi8 (__m128i a, __m128i b)
PSIGND  __m64 _mm_sign_pi32 (__m64 a, __m64 b)
 __m128i _mm_sign_epi32 (__m128i a, __m128i b)
PSIGNW  __m64 _mm_sign_pi16 (__m64 a, __m64 b)
 __m128i _mm_sign_epi16 (__m128i a, __m128i b)
PSLLW __m128i _mm_sll_epi16(__m128i m, __m128i count)PSLLW __m128i _mm_slli_epi16(__m128i m, int count)PSLLW __m64 _mm_sll_pi16(__m64 m, __m64 count)
__m64 _mm_slli_pi16(__m64 m, int count)
PSLLD __m128i _mm_slli_epi32(__m128i m, int count)
__m128i _mm_sll_epi32(__m128i m, __m128i count)
PSLLD __m64 _mm_slli_pi32(__m64 m, int count)
__m64 _mm_sll_pi32(__m64 m, __m64 count)
PSLLQ __m64 _mm_sll_si64(__m64 m, __m64 count)
__m64 _mm_slli_si64(__m64 m, int count)
PSLLQ __m128i _mm_sll_epi64(__m128i m, __m128i count)
__m128i _mm_slli_epi64(__m128i m, int count)
PSLLDQ __m128i _mm_slli_si128(__m128i m, int imm)PSRAW __m128i _mm_sra_epi16(__m128i m, __m128i count)
__m128i _mm_srai_epi16(__m128i m, int count)
PSRAW __m64 _mm_sra_pi16(__m64 m, __m64 count)
__m64 _mm_srai_pi16( __m64 m, int count)
PSRAD __m128i _mm_sra_epi32 (__m128i m, __m128i count)
__m128i _mm_srai_epi32 (__m128i m, int count)
PSRAD __m64 _mm_sra_pi32 (__m64 m, __m64 count)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicC-12 Vol. 2DINTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTS
__m64 _mm_srai_pi32 (__m64 m, int count)
PSRLW _m128i _mm_srl_epi16 (__m128i m, __m128i count)
__m128i _mm_srli_epi16 (__m128i m, int count)__m64 _mm_srl_pi16 (__m64 m, __m64 count)__m64 _mm_srli_pi16(__m64 m, int count)
PSRLD __m128i _mm_srl_epi32 (__m128i m, __m128i count)
__m128i _mm_srli_epi32 (__m128i m, int count)
PSRLD __m64 _mm_srl_pi32 (__m64 m, __m64 count)
__m64 _mm_srli_pi32 (__m64 m, int count)
PSRLQ __m128i _mm_srl_epi64 (__m128i m, __m128i count)
__m128i _mm_srli_epi64 (__m128i m, int count)
PSRLQ __m64 _mm_srl_si64 (__m64 m, __m64 count)
__m64 _mm_srli_si64 (__m64 m, int count)

PSRLDQ __m128i _mm_srli_si128(__m128i m, int imm)PSUBB __m128i _mm_sub_epi8(__m128i m1, __m128i m2)PSUBB __m64 _mm_sub_pi8(__m64 m1, __m64 m2)PSUBW __m128i _mm_sub_epi16(__m128i m1, __m128i m2)PSUBW __m64 _mm_sub_pi16(__m64 m1, __m64 m2)PSUBD __m128i _mm_sub_epi32(__m128i m1, __m128i m2)PSUBD __m64 _mm_sub_pi32(__m64 m1, __m64 m2)PSUBQ __m128i _mm_sub_epi64(__m128i m1, __m128i m2)PSUBQ __m64 _mm_sub_si64(__m64 m1, __m64 m2)PSUBSB __m128i _mm_subs_epi8(__m128i m1, __m128i m2)PSUBSB __m64 _mm_subs_pi8(__m64 m1, __m64 m2)PSUBSW __m128i _mm_subs_epi16(__m128i m1, __m128i m2)PSUBSW __m64 _mm_subs_pi16(__m64 m1, __m64 m2)PSUBUSB __m128i _mm_subs_epu8(__m128i m1, __m128i m2)PSUBUSB __m64 _mm_subs_pu8(__m64 m1, __m64 m2)PSUBUSW __m128i _mm_subs_epu16(__m128i m1, __m128i m2)PSUBUSW __m64 _mm_subs_pu16(__m64 m1, __m64 m2)PTEST int _mm_testz_si128(__m128i s1, __m128i s2)
int _mm_testc_si128(__m128i s1, __m128i s2)int _mm_testnzc_si128(__m128i s1, __m128i s2)
PUNPCKHBW __m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)PUNPCKHBW __m128i _mm_unpackhi _epi8(__m128i m1, __m128i m2)
PUNPCKHWD __m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)PUNPCKHWD __m128i _mm_unpackhi_epi16(__m128i m1, __m128i m2)PUNPCKHDQ ___m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)PUNPCKHDQ __m128i _mm_unpackhi _epi32(__m128i m1, __m128i m2)
PUNPCKHQDQ __m128i _mm_unpackhi _epi64(__m128i m1, __m128i m2)
PUNPCKLBW __m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicVol. 2D C-13INTEL® C/C++ COMPILER INTRINSI CS AND FUNCTIONAL EQUIVALENTS
PUNPCKLBW __m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)
PUNPCKLWD __m64 _mm_unpacklo_pi16(__m64 m1, __m64 m2)PUNPCKLWD __m128i _mm_unpacklo_epi16(__m128i m1, __m128i m2)PUNPCKLDQ __m64 _mm_unpacklo _pi32(__m64 m1, __m64 m2)
PUNPCKLDQ __m128i _mm_unpacklo_epi32(__m128i m1, __m128i m2)PUNPCKLQDQ __m128i _mm_unpacklo_epi64(__m128i m1, __m128i m2)PXOR __m64 _mm_xor_si64(__m64 m1, __m64 m2)PXOR __m128i _mm_xor_si128(__m128i m1, __m128i m2)RCPPS __m128 _mm_rcp_ps(__m128 a)RCPSS __m128 _mm_rcp_ss(__m128 a)ROUNDPD __m128 mm_round_pd(__m128d s1, int iRoundMode)
__m128 mm_floor_pd(__m128d s1)__m128 mm_ceil_pd(__m128d s1)
ROUNDPS __m128 mm_round_ps( __m128 s1, int iRoundMode)
__m128 mm_floor_ps(__m128 s1)__m128 mm_ceil_ps(__m128 s1)
ROUNDSD __m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode)
__m128d mm_floor_sd(__m128d dst, __m128d s1)__m128d mm_ceil_sd(__m128d dst, __m128d s1)
ROUNDSS __m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode)
__m128 mm_floor_ss(__m128 dst, __m128 s1)__m128 mm_ceil_ss(__m128 dst, __m128 s1)
RSQRTPS __m128 _mm_rsqrt_ps(__m128 a)RSQRTSS __m128 _mm_rsqrt_ss(__m128 a)SFENCE void_mm_sfence(void)SHUFPD __m128d _mm_shuffle_pd(__m128d a, __m128d b, unsigned int imm8)
SHUFPS __m128 _mm_shuffle_ps(__m128 a, __m128 b, unsigned int imm8)SQRTPD __m128d _mm_sqrt_pd(__m128d a)SQRTPS __m128 _mm_sqrt_ps(__m128 a)SQRTSD __m128d _mm_sqrt_sd(__m128d a)SQRTSS __m128 _mm_sqrt_ss(__m128 a)STMXCSR _mm_getcsr(void)SUBPD __m128d _mm_sub_pd(__m128d a, __m128d b)SUBPS __m128 _mm_sub_ps(__m128 a, __m128 b)SUBSD __m128d _mm_sub_sd(__m128d a, __m128d b)SUBSS __m128 _mm_sub_ss(__m128 a, __m128 b)UCOMISD int _mm_ucomieq_sd(__m128d a, __m128d b)
int _mm_ucomilt_sd(__m128d a, __m128d b)int _mm_ucomile_sd(__m128d a, __m128d b)int _mm_ucomigt_sd(__m128d a, __m128d b)int _mm_ucomige_sd(__m128d a, __m128d b)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicC-14 Vol. 2DINTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTS
C.2 COMPOSITE INTRINSICSint _mm_ucomineq_sd(__m128d a, __m128d b)
UCOMISS int _mm_ucomieq_ss(__m128 a, __m128 b)
int _mm_ucomilt_ss(__m128 a, __m128 b)int _mm_ucomile_ss(__m128 a, __m128 b)int _mm_ucomigt_ss(__m128 a, __m128 b)int _mm_ucomige_ss(__m128 a, __m128 b)int _mm_ucomineq_ss(__m128 a, __m128 b)
UNPCKHPD __m128d _mm_unpackhi_pd(__m128d a, __m128d b)UNPCKHPS __m128 _mm_unpackhi_ps(__m128 a, __m128 b)UNPCKLPD __m128d _mm_unpacklo_pd(__m128d a, __m128d b)UNPCKLPS __m128 _mm_unpacklo_ps(__m128 a, __m128 b)XORPD __m128d _mm_xor_pd(__m128d a, __m128d b)XORPS __m128 _mm_xor_ps(__m128 a, __m128 b)
Table C-2.  Composite Intrinsics
(composite) __m128i _mm_set_epi64(__m64 q1, __m64 q0)(composite) __m128i _mm_set_epi32(int i3, int i2, int i1, int i0)(composite) __m128i _mm_set_epi1 6(short w7,short w6, short w5, short w4, short w3, short w2, 
 short w1,short w0)
(composite) __m128i _mm_set_epi8(c har w15,char w14, char w13, ch ar w12, char w11, char w10,
 char w9, char w8, char w7,char w6, char w5, char w4, char w3, char w2,char w1, char w0)
(composite) __m128i _m m_set1_epi64(__m64 q)
(composite) __m128i _mm_set1_epi32(int a)(composite) __m128i _m m_set1_epi16(short a)
(composite) __m128i _m m_set1_epi8(char a)
(composite) __m128i _mm_setr _epi64(__m64 q1, __m64 q0)
(composite) __m128i _mm_setr_epi32(int i3, int i2, int i1, int i0)(composite) __m128i _mm_se tr_epi16(short w7,short w6, short w5, short w4, short w3, short w2, short w,
short w0)
(composite) __m128i _mm_se tr_epi8(char w15,ch ar w14, char w13, char w12, char w11, char w10,
char w9, char w8,char w7, char w6,char w5, char w4, char w3, char w2,char w1,char w0)
(composite) __m128i _mm_setzero_si128()(composite) __m128 _mm_set_ps1(float w)
__m128 _mm_set1_ps(float w)
(composite) __m128cmm_set1_pd(double w)(composite) __m128d _mm_set_sd(double w)(composite) __m128d _mm_set_pd(double z, double y)(composite) __m128 _mm_set_ps(float  z, float y, float x, float w)
(composite) __m128d _mm_setr_pd(double z, double y)(composite) __m128 _mm_setr_ps(floa t z, float y, float x, float w)Table C-1.  Simple Intrinsics (Contd.)
Mnemonic IntrinsicVol. 2D C-15INTEL® C/C++ COMPILER INTRINSI CS AND FUNCTIONAL EQUIVALENTS
(composite) __m128d _m m_setzero_pd(void)
(composite) __m128 _mm_setzero_ps(void)MOVSD + shuffle __m128d _mm_load_pd(double * p)
__m128d _mm_load1_pd(double *p)
MOVSS + shuffle __m128 _mm_load_ps1(float * p)
__m128 _mm_load1_ps(float *p)
MOVAPD + shuffle __m128d _mm_loadr_pd(double * p)
MOVAPS + shuffle __m128 _mm_loadr_ps(float * p)
MOVSD + shuffle void _mm_store1_pd(double *p, __m128d a)
MOVSS + shuffle void _mm_store_ps1(float * p, __m128 a)
void _mm_store1_ps(float *p, __m128 a)
MOVAPD + shuffle _mm_storer_pd(double * p, __m128d a)
MOVAPS + shuffle _mm_storer_ps(float * p, __m128 a)Table C-2.  Composit e Intrinsics (Contd.)
Mnemonic IntrinsicC-16 Vol. 2DINTEL® C/C++ COMPILER  INTRINSICS AND FUNCTIONAL EQUIVALENTSIntel® 64 and IA-32 Architectures
Volume 3 (3A, 3B, 3C, & 3D):
System Programming Guide
NOTE:  The Intel 64 and IA-32 Architec tures Software Developer's Manual consists of four volumes:
System Programming Guide , Order Number 325384; Model-Specific Registers, Order Number 335592.
Refer to all four volumes when evaluating your design needs.
Order Number:  325384-082US
© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Othe r

names and brands may be claimed as the property of others.Vol. 3A iiiCONTENTS
PAGE
CHAPTER 1
1.1 INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 1-1
1.2 OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3.1 Bit and Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3.2 Reserved Bits and Software Compatibility  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3.3 Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.3.4 Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.3.5 Segmented Addressing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.3.6 Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.3.7 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.4 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-10
CHAPTER 2
SYSTEM ARCHITECTURE OVERVIEW
2.1 OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1 Global and Local Descriptor Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.1.1 Global and Local Descriptor Tables in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.2 System Segments, Segment Descriptors, and Gates  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.2.1 Gates in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.3 Task-State Segments and Task Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.3.1 Task-State Segments in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.4 Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.4.1 Interrupt and Exception Handling IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.5 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.5.1 Memory Management in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.6 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.6.1 System Registers in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.1.7 Other System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2 MODES OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1 Extended Feature Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3 SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.1 System Flags and Fields in IA-32e Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.4 MEMORY-MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-11
2.4.1 Global Descriptor Table Register (GDTR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.4.2 Local Descriptor Table Register (LDTR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.4.3 IDTR Interrupt Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.4.4 Task Register (TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.5 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-13
2.5.1 CPUID Qualification of Control Register Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.6 EXTENDED CONTROL REGISTERS (INCLUDING XCR0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-20
2.7 PROTECTION-KEY RIGHTS REGISTERS (PKRU AND IA32_PKRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-22
2.8 SYSTEM INSTRUCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-23
2.8.1 Loading and Storing System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.8.2 Verifying of Access Privileges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.8.3 Loading and Storing Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.8.4 Invalidating Caches and TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.8.5 Controlling the Processor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.8.6 Reading Performance-Monitoring and Time-Stamp Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 2-26
2.8.6.1 Reading Counters in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.8.7 Reading and Writing Model-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.8.7.1 Reading and Writing Model-Specific Registers in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.8.8 Enabling Processor Extended States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27CONTENTS
ivVol. 3APAGE
CHAPTER 3
PROTECTED-MODE ME MORY MANAGEMENT
3.1 MEMORY MANAGEMENT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 USING SEGMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.1 Basic Flat Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.2 Protected Flat Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.3 Multi-Segment Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.4 Segmentation in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.5 Paging and Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3 PHYSICAL ADDRESS SPACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.3.1 Intel® 64 Processors and Physical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4 LOGICAL AND LINEAR ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4.1 Logical Address Translation in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.2 Segment Selectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.3 Segment Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.4 Segment Loading Instructions in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.5 Segment Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.5.1 Code- and Data-Segment Descriptor Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.5 SYSTEM DESCRIPTOR TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-13
3.5.1 Segment Descriptor Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.5.2 Segment Descriptor Tables in IA-32e Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
CHAPTER 4
PAGING
4.1 PAGING MODES AND CONTROL BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Four Paging Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.2 Paging-Mode Enabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.3 Paging-Mode Modifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.1.4 Enumeration of Paging Features by CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2 HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3 32-BIT PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.4 PAE PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-14
4.4.1 PDPTE Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.4.2 Linear-Address Translation with PAE Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.5 4-LEVEL PAGING AND 5-LEVEL PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-20
4.5.1 Ordinary Paging and HLAT Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.5.2 Use of CR3 with Ordinary 4-Level Paging and 5-Level Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-20
4.5.3 Use of HLATP with HLAT 4-Level Paging and 5-Level Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.5.4 Linear-Address Translation with 4-Level Paging and 5-Level Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 4-22
4.5.5 Restart of HLAT Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
4.6 ACCESS RIGHTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-33
4.6.1 Determination of Access Rights  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
4.6.2 Protection Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
4.7 PAGE-FAULT EXCEPTIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-37
4.8 ACCESSED AND DIRTY FLAGS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-39

4.9 PAGING AND MEMORY TYPING  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-39
4.9.1 Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium II Processors) . . . . . . . . . . . . . . 4 -40
4.9.2 Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent Processor Families). . . . . . . . . . 4-40
4.9.3 Caching Paging-Related Information about Memory Typing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 4-41
4.10 CACHING TRANSLATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4-41
4.10.1 Process-Context Identifiers (PCIDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
4.10.2 Translation Lookaside Buffers (TLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
4.10.2.1 Page Numbers, Page Frames, and Page Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 4-42
4.10.2.2 Caching Translations in TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
4.10.2.3 Details of TLB Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
4.10.2.4 Global Pages  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
4.10.3 Paging-Structure Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
4.10.3.1 Caches for Paging Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
4.10.3.2 Using the Paging-Structure Caches to Translate Linear Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47
4.10.3.3 Multiple Cached Entries for a Single Paging-Structure Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47
4.10.4 Invalidation of TLBs and Paging-Structure Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
4.10.4.1 Operations that Invalidate TLBs and Paging-Structure Caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
4.10.4.2 Recommended Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50Vol. 3A vCONTENTS
PAGE
4.10.4.3 Optional Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
4.10.4.4 Delayed Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
4.10.5 Propagation of Paging-Structure Changes to Multiple Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
4.11 INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (VMX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-53
4.11.1 VMX Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
4.11.2 VMX Support for Address Translation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
4.12 USING PAGING FOR VIRTUAL MEMORY  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
4.13 MAPPING SEGMENTS TO PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
CHAPTER 5
PROTECTION
5.1 ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-1
5.2 FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND PAGE-LEVEL PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-2
5.2.1 Code-Segment Descriptor in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3 LIMIT CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-4
5.3.1 Limit Checking in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.4 TYPE CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-5
5.4.1 Null Segment Selector Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.4.1.1 NULL Segment Checking in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5 PRIVILEGE LEVELS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-6
5.6 PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5-8
5.6.1 Accessing Data in Code Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.7 PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 5-10
5.8 PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS . . . . . . . . . . . . . . . . 5-10
5.8.1 Direct Calls or Jumps to Code Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.8.1.1 Accessing Nonconforming Code Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.8.1.2 Accessing Conforming Code Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.8.2 Gate Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.8.3 Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.8.3.1 IA-32e Mode Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.8.4 Accessing a Code Segment Through a Call Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.8.5 Stack Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

5.8.5.1 Stack Switching in 64-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.8.6 Returning from a Called Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.8.7 Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions  . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.8.7.1 SYSENTER and SYSEXIT Instructions in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.8.8 Fast System Calls in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.9 PRIVILEGED INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.10 POINTER VALIDATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.10.1 Checking Access Rights (LAR Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.10.2 Checking Read/Write Rights (VERR and VERW Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.10.3 Checking That the Pointer Offset Is Within Limits (LSL Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.10.4 Checking Caller Access Privileges (ARPL Instruction). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.10.5 Checking Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.11 PAGE-LEVEL PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.11.1 Page-Protection Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.11.2 Restricting Addressable Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.11.3 Page Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.11.4 Combining Protection of Both Levels of Page Tables  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.11.5 Overrides to Page Protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.12 COMBINING PAGE AND SEGMENT PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.13 PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 5-30
5.13.1 Detecting and Enabling the Execute-Disable Capability  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.13.2 Execute-Disable Page Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.13.3 Reserved Bit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.13.4 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
CHAPTER 6
INTERRUPT AND EXCEPTION HANDLING
6.1 INTERRUPT AND EXCEPTION OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-1
6.2 EXCEPTION AND INTERRUPT VECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-1
6.3 SOURCES OF INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-2CONTENTS
viVol. 3APAGE
6.3.1 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3.2 Maskable Hardware Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3.3 Software-Generated Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4 SOURCES OF EXCEPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4.1 Program-Error Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4.2 Software-Generated Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4.3 Machine-Check Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.5 EXCEPTION CLASSIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6 PROGRAM OR TASK RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.7 NONMASKABLE INTERRUPT (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.7.1 Handling Multiple NMIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.8 ENABLING AND DISABLING INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.8.1 Masking Maskable Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.8.2 Masking Instruction Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.8.3 Masking Exceptions and Interrupts When Switching Stacks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.9 PRIORITIZATION OF CONCURRENT EVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.10 INTERRUPT DESCRIPTOR TABLE (IDT)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.11 IDT DESCRIPTORS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-10

6.12 EXCEPTION AND INTERRUPT HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-11
6.12.1 Exception- or Interrupt-Handler Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.12.1.1 Shadow Stack Usage on Transfers to Interrupt and Exception Handling Routines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.12.1.2 Protection of Exception- and Interrupt-Handler Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.12.1.3 Flag Usage By Exception- or Interrupt-Handler Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.12.2 Interrupt Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.13 ERROR CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-18
6.14 EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-19
6.14.1 64-Bit Mode IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.14.2 64-Bit Mode Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.14.3 IRET in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.14.4 Stack Switching in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.14.5 Interrupt Stack Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.15 EXCEPTION AND INTERRUPT REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6-23
Interrupt 0—Divide Error Exception (#DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Interrupt 1—Debug Exception (#DB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Interrupt 2—NMI Interrupt  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Interrupt 3—Breakpoint Exception (#BP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Interrupt 4—Overflow Exception (#OF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Interrupt 5—BOUND Range Exceeded Exception (#BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
Interrupt 6—Invalid Opcode Exception (#UD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Interrupt 7—Device Not Available Exception (#NM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 6-32
Interrupt 8—Double Fault Exception (#DF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
Interrupt 9—Coprocessor Segment Overrun. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Interrupt 10—Invalid TSS Exception (#TS)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
Interrupt 11—Segment Not Present (#NP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
Interrupt 12—Stack Fault Exception (#SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
Interrupt 13—General Protection Exception (#GP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
Interrupt 14—Page-Fault Exception (#PF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
Interrupt 16—x87 FPU Floating-Point Error (#MF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
Interrupt 17—Alignment Check Exception (#AC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 6-50
Interrupt 18—Machine-Check Exception (#MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
Interrupt 19—SIMD Floating-Point Exception (#XM)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
Interrupt 20—Virtualization Exception (#VE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
Interrupt 21—Control Protection Exception (#CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 6-56
Interrupts 32 to 255—User Defined Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 6-58
CHAPTER 7
USER INTERRUPTS
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 ENUMERATION AND ENABLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.3 USER-INTERRUPT STATE AND USER-INTERRUPT MSRS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.3.1 User-Interrupt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2Vol. 3A viiCONTENTS
PAGE
7.3.2 User-Interrupt MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.4 EVALUATION AND DELIVERY OF USER INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7-3
7.4.1 User-Interrupt Recognition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.4.2 User-Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.5 USER-INTERRUPT NOTIFICATION IDENTIFICATION AND PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .  7-5
7.5.1 User-Interrupt Notification Identification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.5.2 User-Interrupt Notification Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.6 USER-INTERRUPT INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7-7
7.7 USER IPIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7-7
CHAPTER 8
TASK MANAGEMENT
8.1 TASK MANAGEMENT OVERVIEW  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8-1
8.1.1 Task Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2 Task State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.3 Executing a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2 TASK MANAGEMENT DATA STRUCTURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8-3
8.2.1 Task-State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2.2 TSS Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.2.3 TSS Descriptor in 64-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.2.4 Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.2.5 Task-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3 TASK SWITCHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8-9
8.4 TASK LINKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.4.1 Use of Busy Flag To Prevent Recursive Task Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.4.2 Modifying Task Linkages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.5 TASK ADDRESS SPACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.5.1 Mapping Tasks to the Linear and Physical Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 8-17
8.5.2 Task Logical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.6 16-BIT TASK-STATE SEGMENT (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.7 TASK MANAGEMENT IN 64-BIT MODE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
CHAPTER 9
MULTIPLE-PROCESSOR MANAGEMENT
9.1 LOCKED ATOMIC OPERATIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-1
9.1.1 Guaranteed Atomic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.1.2 Bus Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.1.2.1 Automatic Locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.1.2.2 Software Controlled Bus Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.1.2.3 Features to Disable Bus Locks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.1.3 Handling Self- and Cross-Modifying Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.1.4 Effects of a LOCK Operation on Internal Processor Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.2 MEMORY ORDERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-6
9.2.1 Memory Ordering in the Intel® Pentium® and Intel486™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.2.2 Memory Ordering in P6 and More Recent Processor Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.2.3 Examples Illustrating the Memory-Ordering Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.2.3.1 Assumptions, Terminology, and Notation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.2.3.2 Neither Loads Nor Stores Are Reordered with Like Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 9-9
9.2.3.3 Stores Are Not Reordered With Earlier Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.2.3.4 Loads May Be Reordered with Earlier Stores to Different Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 9-10
9.2.3.5 Intra-Processor Forwarding Is Allowed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.2.3.6 Stores Are Transitively Visible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.2.3.7 Stores Are Seen in a Consistent Order by Other Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 9-12
9.2.3.8 Locked Instructions Have a Total Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.2.3.9 Loads and Stores Are Not Reordered with Locked Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 9-12
9.2.4 Fast-String Operation and Out-of-Order Stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.2.4.1 Memory-Ordering Model for String Operations on Write-Back (WB) Memory. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 9-13

9.2.4.2 Examples Illustrating Memory-Ordering Principles for String Operations . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 9-14
9.2.5 Strengthening or Weakening the Memory-Ordering Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 9-16
9.3 SERIALIZING INSTRUCTIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9.4 MULTIPLE-PROCESSOR (MP) INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
9.4.1 BSP and AP Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19CONTENTS
viii Vol. 3APAGE
9.4.2 MP Initialization Protocol Requirements and Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.4.3 MP Initialization Protocol Algorithm for MP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.4.4 MP Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.4.4.1 Typical BSP Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.4.4.2 Typical AP Initialization Sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
9.4.5 Identifying Logical Processors in an MP System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9.5 INTEL® HYPER-THREADING TECHNOLOGY AND INTEL® MULTI-CORE TECHNOLOGY  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . .  9-25
9.6 DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .  9-25
9.6.1 Initializing Processors Supporting Intel® Hyper-Threading Technology  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 9-26
9.6.2 Initializing Multi-Core Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9.6.3 Executing Multiple Threads on an Intel® 64 or IA-32 Processor Supporting Hardware Multi-Threading . . . . . . . . . . . . .  .9 - 2 7
9.6.4 Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 9-27
9.7 INTEL® HYPER-THREADING TECHNOLOGY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .  9-27
9.7.1 State of the Logical Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.7.2 APIC Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9.7.3 Memory Type Range Registers (MTRR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9.7.4 Page Attribute Table (PAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9.7.5 Machine Check Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9.7.6 Debug Registers and Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9.7.7 Performance Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9.7.8 IA32_MISC_ENABLE MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9.7.9 Memory Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9.7.10 Serializing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9.7.11 Microcode Update Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9.7.12 Self Modifying Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.7.13 Implementation-Specific Intel® HT Technology Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.7.13.1 Processor Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.7.13.2 Processor Translation Lookaside Buffers (TLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.7.13.3 Thermal Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
9.7.13.4 External Signal Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
9.8 MULTI-CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9-32
9.8.1 Logical Processor Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
9.8.2 Memory Type Range Registers (MTRR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
9.8.3 Performance Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
9.8.4 IA32_MISC_ENABLE MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
9.8.5 Microcode Update Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
9.9 PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS . . . . . . . . . . . . . . . . . . . . .  9-349.9.1 Hierarchical Mapping of Shared Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34
9.9.2 Hierarchical Mapping of CPUID Extended Topology Leaf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9.9.3 Hierarchical ID of Logical Processors in an MP System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
9.9.3.1 Hierarchical ID of Logical Processors with x2APIC ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
9.9.4 Algorithm for Three-Domain Mappings of APIC_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 9-41

9.9.5 Identifying Topological Relationships in an MP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 9-45
9.10 MANAGEMENT OF IDLE AND BLOCKED CONDITIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .  9-48
9.10.1 HLT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
9.10.2 PAUSE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
9.10.3 Detecting Support MONITOR/MWAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49
9.10.4 MONITOR/MWAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49
9.10.5 Monitor/Mwait Address Range Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-50
9.10.6 Required Operating System Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-51
9.10.6.1 Use the PAUSE Instruction in Spin-Wait Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 9-51
9.10.6.2 Potential Usage of MONITOR/MWAIT in C0 Idle Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 
. . . . . . . . . . . . . . . . . . . . . . 9-51
9.10.6.3 Halt Idle Logical Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-53
9.10.6.4 Potential Usage of MONITOR/MWAIT in C1 Idle Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-53
9.10.6.5 Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources . . . . . . . . . . . . . . . . . . . . . . . . . 9-54
9.10.6.6 Eliminate Execution-Based Timing Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54
9.10.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 9-54
9.11 MP INITIALIZATION FOR P6 FAMILY PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  9-54
9.11.1 Overview of the MP Initialization Process for P6 Family Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55
9.11.2 MP Initialization Protocol Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55
9.11.2.1 Error Detection and Handling During the MP Initialization Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 9-57Vol. 3A ixCONTENTS
PAGE
CHAPTER 10
PROCESSOR MANAGEMENT AND INITIALIZATION
10.1 INITIALIZATION OVERVIEW  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Processor State After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.2 Processor Built-In Self-Test (BIST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.1.3 Model and Stepping Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.1.4 First Instruction Executed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2 X87 FPU INITIALIZATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.1 Configuring the x87 FPU Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.2.2 Setting the Processor for x87 FPU Software Emulation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3 CACHE ENABLING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.4 MODEL-SPECIFIC REGISTERS (MSRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.5 MEMORY TYPE RANGE REGISTERS (MTRRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.6 INITIALIZING SSE/SSE2/SSE3/SSSE3 EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.7 SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 10-8
10.7.1 Real-Address Mode IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.7.2 NMI Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.8 SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.8.1 Protected-Mode System Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.8.2 Initializing Protected-Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .10-10
10.8.3 Initializing Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10
10.8.4 Initializing Multitasking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10
10.8.5 Initializing IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11
10.8.5.1 IA-32e Mode System Data Structures  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11
10.8.5.2 IA-32e Mode Interrupts and Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12
10.8.5.3 64-bit Mode and Compatibility Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .10-12
10.8.5.4 Switching Out of IA-32e Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12
10.9 MODE SWITCHING  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10-13
10.9.1 Switching to Protected Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-13
10.9.2 Switching Back to Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-14

10.10 INITIALIZATION AND MODE SWITCHING EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  10-14
10.10.1 Assembler Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-16
10.10.2 STARTUP.ASM Listing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-16
10.10.3 MAIN.ASM Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-25
10.10.4 Supporting Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-25
10.11 MICROCODE UPDATE FACILITIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10-27
10.11.1 Microcode Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28
10.11.2 Optional Extended Signature Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-31
10.11.3 Processor Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-32
10.11.4 Platform Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-32
10.11.5 Microcode Update Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-33
10.11.6 Microcode Update Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-34
10.11.6.1 Hard Resets in Update Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-35
10.11.6.2 Update in a Multiprocessor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-35
10.11.6.3 Update in a System Supporting Intel Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-35
10.11.6.4 Update in a System Supporting Dual-Core Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-35
10.11.6.5 Update Loader Enhancements  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-35
10.11.7 Update Signature and Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-36
10.11.7.1 Determining the Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-36
10.11.7.2 Authenticating the Update. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-37
10.11.8 Optional Processor Microcode Update Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-37
10.11.8.1 Responsibilities of the BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-38
10.11.8.2 Responsibilities of the Calling Program  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-39
10.11.8.3 Microcode Update Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-42
10.11.8.4 INT 15H-based Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-42
10.11.8.5 Function 00H—Presence Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-42
10.11.8.6 Function 01H—Write Microcode Update Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .10-43
10.11.8.7 Function 02H—Microcode Update Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .10-46
10.11.8.8 Function 03H—Read Microcode Update Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .10-47
10.11.8.9 Return Codes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-48CONTENTS
xVol. 3APAGE
CHAPTER 11
ADVANCED PROGRAMMABLE INTE RRUPT CONTROLLER (APIC)
11.1 LOCAL AND I/O APIC OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-1
11.2 SYSTEM BUS VS. APIC BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-3
11.3 THE INTEL® 82489DX EXTERNAL APIC, THE APIC, THE XAPIC, AND THE X2APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . .  11-4
11.4 LOCAL APIC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-4
11.4.1 The Local APIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.4.2 Presence of the Local APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.3 Enabling or Disabling the Local APIC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.4 Local APIC Status and Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.4.5 Relocating the Local APIC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.4.6 Local APIC ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.4.7 Local APIC State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10
11.4.7.1 Local APIC State After Power-Up or Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10
11.4.7.2 Local APIC State After It Has Been Software Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10
11.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10

11.4.7.4 Local APIC State After It Receives an INIT-Deassert IPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .11-11
11.4.8 Local APIC Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11
11.5 HANDLING LOCAL INTERRUPTS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-12
11.5.1 Local Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12
11.5.2 Valid Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15
11.5.3 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15
11.5.4 APIC Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16
11.5.4.1 TSC-Deadline Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17
11.5.5 Local Interrupt Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-18
11.6 ISSUING INTERPROCESSOR INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-19
11.6.1 Interrupt Command Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-19
11.6.2 Determining IPI Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-22
11.6.2.1 Physical Destination Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-23
11.6.2.2 Logical Destination Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-23
11.6.2.3 Broadcast/Self Delivery Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-25
11.6.2.4 Lowest Priority Delivery Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-25
11.6.3 IPI Delivery and Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-26
11.7 SYSTEM AND APIC BUS ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-26
11.8 HANDLING INTERRUPTS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-26
11.8.1 Interrupt Handling with the Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-27
11.8.2 Interrupt Handling with the P6 Family and Pentium Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-27
11.8.3 Interrupt, Task, and Processor Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-28
11.8.3.1 Task and Processor Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-29
11.8.4 Interrupt Acceptance for Fixed Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-30
11.8.5 Signaling Interrupt Servicing Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-31
11.8.6 Task Priority in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-31
11.8.6.1 Interaction of Task Priorities between CR8 and APIC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .11-32
11.9 SPURIOUS INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-32
11.10 APIC BUS MESSAGE PASSING MECHANISM AND PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS) . . . . . . . . . . . . . . . . . . .  11-3 3
11.10.1 Bus Message Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-34
11.11 MESSAGE SIGNALLED INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-34
11.11.1 Message Address Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-34
11.11.2 Message Data Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-35
11.12 EXTENDED XAPIC (X2APIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-36
11.12.1 Detecting and Enabling x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-37
11.12.1.1 Instructions to Access APIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-37
11.12.1.2 x2APIC Register Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-38
11.12.1.3 Reserved Bit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-40
11.12.2 x2APIC Register Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-40
11.12.3 MSR Access in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-40
11.12.4 VM-Exit Controls for MSRs and x2APIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-41
11.12.5 x2APIC State Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-41
11.12.5.1 x2APIC States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-41
x2APIC After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-42
x2APIC Transitions From x2APIC Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .11-42

x2APIC Transitions From Disabled Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .11-43
State Changes From xAPIC Mode to x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-43
11.12.6 Routing of Device Interrupts in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-43Vol. 3A xiCONTENTS
PAGE
11.12.7 Initialization by System Software  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-43
11.12.8 CPUID Extensions And Topology Enumeration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .11-43
11.12.8.1 Consistency of APIC IDs and CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-44
11.12.9 ICR Operation in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-44
11.12.10 Determining IPI Destination in x2APIC Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-45
11.12.10.1 Logical Destination Mode in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-45
11.12.10.2 Deriving Logical x2APIC ID from the Local x2APIC ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-46
11.12.11 SELF IPI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-47
11.13 APIC BUS MESSAGE FORMATS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11-47
11.13.1 Bus Message Formats  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-47
11.13.2 EOI Message  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-47
11.13.2.1 Short Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-48
11.13.2.2 Non-focused Lowest Priority Message. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-49
11.13.2.3 APIC Bus Status Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-50
CHAPTER 12
MEMORY CACHE CONTROL
12.1 INTERNAL CACHES, TLBS, AND BUFFERS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 CACHING TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.3 METHODS OF CACHING AVAILABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.3.1 Buffering of Write Combining Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.3.2 Choosing a Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.3.3 Code Fetches in Uncacheable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.4 CACHE CONTROL PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.5 CACHE CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12-10
12.5.1 Cache Control Registers and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10
12.5.2 Precedence of Cache Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-13
12.5.2.1 Selecting Memory Types for Pentium Pro and Pentium II Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-14
12.5.2.2 Selecting Memory Types for Pentium III and More Recent Processor Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-15
12.5.2.3 Writing Values Across Pages with Different Memory Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16
12.5.3 Preventing Caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16
12.5.4 Disabling and Enabling the L3 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-17
12.5.5 Cache Management Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-17
12.5.6 L1 Data Cache Context Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-18
12.5.6.1 Adaptive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-18
12.5.6.2 Shared Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-18
12.6 SELF-MODIFYING CODE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12-18
12.7 IMPLICIT CACHING (PENTIUM 4, INTEL® XEON®, AND P6 FAMILY PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .  12-19
12.8 EXPLICIT CACHING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12-19
12.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12-19
12.10 STORE BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12-20
12.11 MEMORY TYPE RANGE REGISTERS (MTRRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .  12-20
12.11.1 MTRR Feature Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-21
12.11.2 Setting Memory Ranges with MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-22
12.11.2.1 IA32_MTRR_DEF_TYPE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-22
12.11.2.2 Fixed Range MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-23

12.11.2.3 Variable Range MTRRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-23
12.11.2.4 System-Management Range Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .12-25
12.11.3 Example Base and Mask Calculations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-26
12.11.3.1 Base and Mask Calculations for Greater-Than 36-bit Physical Address Support. . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .12-27
12.11.4 Range Size and Alignment Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-28
12.11.4.1 MTRR Precedences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-28
12.11.5 MTRR Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-29
12.11.6 Remapping Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-29
12.11.7 MTRR Maintenance Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-29
12.11.7.1 MemTypeGet() Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-29
12.11.7.2 MemTypeSet() Function  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-31
12.11.8 MTRR Considerations in MP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-32
12.11.9 Large Page Size Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-33
12.12 PAGE ATTRIBUTE TABLE (PAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12-33
12.12.1 Detecting Support for the PAT Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-34
12.12.2 IA32_PAT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-34
12.12.3 Selecting a Memory Type from the PAT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-35
12.12.4 Programming the PAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-35CONTENTS
xiiVol. 3APAGE
12.12.5 PAT Compatibility with Earlier IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .12-36
CHAPTER 13
INTEL® MMX™ TECHNOLOGY  SYSTEM PROGRAMMING
13.1 EMULATION OF THE MMX INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .  13-1
13.2 THE MMX STATE AND MMX REGISTER ALIASING  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  13-1
13.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3 SAVING AND RESTORING THE MMX STATE AND REGISTERS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13-3
13.4 SAVING MMX STATE ON TASK OR CONTEXT SWITCHES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  13-4
13.5 EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13-4
13.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.6 DEBUGGING MMX CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13-5
CHAPTER 14
SYSTEM PROGRAMMING FOR INSTRUCTION SE T EXTENSIONS AND PROCESSOR EXTENDED 
STATES
14.1 PROVIDING OPERATING SYSTEM SUPPORT FOR SSE EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-1
14.1.1 Adding Support to an Operating System for SSE Extensions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.1.2 Checking for CPU Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.1.3 Initialization of the SSE Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.1.4 Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE Instructions . . . . . . . . . . . . . . . . . . . . . 14-4
14.1.5 Providing a Handler for the SIMD Floating-Point Exception (#XM)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 14-5
14.1.5.1 Numeric Error flag and IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.2 EMULATION OF SSE EXTENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-6
14.3 SAVING AND RESTORING SSE STATE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-6
14.4 DESIGNING OS FACILITIES FOR SAVING X87 FPU, SSE, AND EXTENDED STATES ON TASK OR CONTEXT SWITCHES. . . .  14-6
14.4.1 Using the TS Flag to Control the Saving of the x87 FPU and SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.5 THE XSAVE FEATURE SET AND PROCESSOR EXTENDED STATE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .  14-7
14.5.1 Checking the Support for XSAVE Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.5.2 Determining the XSAVE Managed Feature States And The Required Buffer Size . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 14-8
14.5.3 Enable the Use Of XSAVE Feature Set And XSAVE State Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 14-9
14.5.4 Provide an Initialization for the XSAVE State Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.5.5 Providing the Required Exception Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.6 INTEROPERABILITY OF THE XSAVE FEATURE SET AND FXSAVE/FXRSTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-9
14.7 THE XSAVE FEATURE SET AND PROCESSOR SUPERVISOR STATE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .  14-10
14.8 SYSTEM PROGRAMMING FOR XSAVE MANAGED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14-10
14.8.1 Intel® Advanced Vector Extensions (Intel® AVX)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-11

14.8.2 Intel® Advanced Vector Extensions 512 (Intel® AVX-512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-11
CHAPTER 15
POWER AND THERMAL MANAGEMENT
15.1 ENHANCED INTEL SPEEDSTEP® TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .  15-1
15.1.1 Software Interface For Initiating Performance State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 15-1
15.2 P-STATE HARDWARE COORDINATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-1
15.3 SYSTEM SOFTWARE CONSIDERATIONS AND OPPORTUNISTIC PROCESSOR PERFORMANCE OPERATION . . . . . . . . . . . . . .  15-3
15.3.1 Intel® Dynamic Acceleration Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.3.2 System Software Interfaces for Opportunistic Processor Performance Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.3.2.1 Discover Hardware Support and Enabling of Opportunistic Processor Performance Operation. . . . . . . . . . . . . . . . . . . 15-3
15.3.2.2 OS Control of Opportunistic Processor Performance Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3.2.3 Required Changes to OS Power Management P-State Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3.3 Intel® Turbo Boost Technology  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3.4 Performance and Energy Bias Hint Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.4 HARDWARE-CONTROLLED PERFORMANCE STATES (HWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-5
15.4.1 HWP Programming Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.4.2 Enabling HWP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.4.3 HWP Performance Range and Dynamic Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.4.4 Managing HWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.4.4.1 IA32_HWP_REQUEST MSR (Address: 774H Logical Processor Scope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.4.4.2 IA32_HWP_REQUEST_PKG MSR (Address: 772H Package Scope). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .15-11
15.4.4.3 IA32_HWP_PECI_REQUEST_INFO MSR (Address 775H Package Scope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-11
15.4.4.4 IA32_HWP_CTL MSR (Address: 776H Logical Processor Scope). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .15-12Vol. 3A xiiiCONTENTS
PAGE
15.4.5 HWP Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-13
15.4.5.1 Non-Architectural HWP Feedback  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-15
15.4.6 HWP Notifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-16
15.4.7 Idle Logical Processor Impact on Core Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-16
15.4.8 Fast Write of Uncore MSR (Model Specific Feature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-17
15.4.8.1 FAST_UNCORE_MSRS_CAPABILITY (Address: 0x65F, Logical Processor Scope) . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .15-17
15.4.8.2 FAST_UNCORE_MSRS_CTL (Address: 0x657, Logical Processor Scope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .15-17
15.4.8.3 FAST_UNCORE_MSRS_STATUS (Address: 0x65E, Logical Processor Scope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-18
15.4.9 Fast_IA32_HWP_REQUEST CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-18
15.4.10 Recommendations for OS use of HWP Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-18
15.5 HARDWARE DUTY CYCLING (HDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-20
15.5.1 Hardware Duty Cycling Programming Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .15-20
15.5.2 Package level Enabling HDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-21
15.5.3 Logical-Processor Level HDC Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-22
15.5.4 HDC Residency Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-22
15.5.4.1 IA32_THREAD_STALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-22
15.5.4.2 Non-Architectural HDC Residency Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .15-23
15.5.5 MPERF and APERF Counters Under HDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-25
15.6 HARDWARE FEEDBACK INTERFACE AND INTEL® THREAD DIRECTOR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-25
15.6.1 Hardware Feedback Interface Table Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .15-25
15.6.2 Intel® Thread Director Table Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-27
15.6.3 Intel® Thread Director Usage Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-30
15.6.4 Hardware Feedback Interface Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-31
15.6.5 Hardware Feedback Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .15-31
15.6.6 Hardware Feedback Interface Notifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-32
15.6.7 Hardware Feedback Interface and Intel® Thread Director Structure Dynamic Update . . . . . . . . . . . . . . . . . . . . .  . . . . . . . .15-33
15.6.8 Logical Processor Scope Intel® Thread Director Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-33
15.6.9 Implicit Reset of Package and Logical Processor Scope Configuration MSRs . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .15-34
15.6.10 Logical Processor Scope Intel® Thread Director Run Time Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-34

15.6.11 Logical Processor Scope History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-34
15.6.11.1 Enabling Intel® Thread Director History Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .15-35
15.6.11.2 Implicit Intel® Thread Director History Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-35
15.7 MWAIT EXTENSIONS FOR ADVANCED POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .  15-35
15.8 THERMAL MONITORING AND PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15-36
15.8.1 Catastrophic Shutdown Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-37
15.8.2 Thermal Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-37
15.8.2.1 Thermal Monitor 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-37
15.8.2.2 Thermal Monitor 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-37
15.8.2.3 Two Methods for Enabling TM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-37
15.8.2.4 Performance State Transitions and Thermal Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-38
15.8.2.5 Thermal Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-38
15.8.2.6 Adaptive Thermal Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-39
15.8.3 Software Controlled Clock Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-40
15.8.3.1 Extension of Software Controlled Clock Modulation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .15-41
15.8.4 Detection of Thermal Monitor and Software Controlled Clock Modulation Facilities . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .15-41
15.8.4.1 Detection of Software Controlled Clock Modulation Extension  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .15-41
15.8.5 On Die Digital Thermal Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-42
15.8.5.1 Digital Thermal Sensor Enumeration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-42
15.8.5.2 Reading the Digital Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-42
15.8.6 Power Limit Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-45
15.9 PACKAGE LEVEL THERMAL MANAGEMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .  15-45
15.9.1 Support for Passive and Active cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-47
15.10 PLATFORM SPECIFIC POWER MANAGEMENT SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .  15-48
15.10.1 RAPL Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-48
15.10.2 RAPL Domains and Platform Specificity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-49
15.10.3 Package RAPL Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-50
15.10.4 PP0/PP1 RAPL Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-52
15.10.5 DRAM RAPL Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-54
CHAPTER 16
MACHINE-CHECK ARCHITECTURE
16.1 MACHINE-CHECK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 COMPATIBILITY WITH PENTIUM PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.3 MACHINE-CHECK MSRS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2CONTENTS
xiv Vol. 3APAGE
16.3.1 Machine-Check Global Control MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3.1.1 IA32_MCG_CAP MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3.1.2 IA32_MCG_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.1.3 IA32_MCG_CTL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.1.4 IA32_MCG_EXT_CTL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.1.5 Enabling Local Machine Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.2 Error-Reporting Register Banks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.2.1 IA32_MC i_CTL MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.2.2 IA32_MCi_STATUS MSRS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.2.3 IA32_MCi_ADDR MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.3.2.4 IA32_MC i_MISC MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.3.2.5 IA32_MC i_CTL2 MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-11
16.3.2.6 IA32_MCG Extended Machine Check State MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-12
16.3.3 Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture . . . . . . . . . . . . . . . . . . . . .16-13

16.4 ENHANCED CACHE ERROR REPORTING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-13
16.5 CORRECTED MACHINE CHECK ERROR INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .  16-14
16.5.1 CMCI Local APIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-14
16.5.2 System Software Recommendation for Managing CMCI and Machine Check Resources. . . . . . . . . . . . . . . . . . . . . . .  . . . . .16-15
16.5.2.1 CMCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-15
16.5.2.2 CMCI Threshold Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-16
16.5.2.3 CMCI Interrupt Handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-16
16.6 RECOVERY OF UNCORRECTED RECOVERABLE (UCR) ERRORS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-16
16.6.1 Detection of Software Error Recovery Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .16-16
16.6.2 UCR Error Reporting and Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-16
16.6.3 UCR Error Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-17
16.6.4 UCR Error Overwrite Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-18
16.7 MACHINE-CHECK AVAILABILITY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-19
16.8 MACHINE-CHECK INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-19
16.9 INTERPRETING THE MCA ERROR CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-20
16.9.1 Simple Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-20
16.9.2 Compound Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-21
16.9.2.1 Correction Report Filtering (F) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-21
16.9.2.2 Transaction Type (TT) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-22
16.9.2.3 Level (LL) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-22
16.9.2.4 Request (RRRR) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-22
16.9.2.5 Bus and Interconnect Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-23
16.9.2.6 Memory Controller and Extended Memory Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .16-24
16.9.3 Architecturally Defined UCR Errors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-24
16.9.3.1 Architecturally Defined SRAO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-24
16.9.3.2 Architecturally Defined SRAR Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-25
16.9.4 Multiple MCA Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-27
16.9.5 Machine-Check Error Codes Interpretation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-27
16.10 GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-28
16.10.1 Machine-Check Exception Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-28
16.10.2 Pentium Processor Machine-Check Exception Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .16-29
16.10.3 Logging Correctable Machine-Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-29
16.10.4 Machine-Check Software Handler Guidelines for Error Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-31
16.10.4.1 Machine-Check Exception Handler for Error Recovery  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .16-31
16.10.4.2 Corrected Machine-Check Handler for Error Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-35
CHAPTER 17
INTERPRETING MACHINE CHECK ERROR CODES
17.1 INCREMENTAL DECODING IN FORMATION: PROCESSOR FAMILY  06H, MACHINE ERROR CODES FOR MACHINE CHECK. . .  17-1
17.2 INCREMENTAL DECODING IN FORMATION: INTEL® CORE™ 2 PROCESSOR FA MILY, MACHINE ERROR CODES FOR MACHINE 
CHECK  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-3
17.2.1 Model-Specific Machine Check Error Codes for Intel® Xeon® Processor 7400 Series . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 17-5
17.2.1.1 Processor Machine Check Status Register, Incremental MCA Error Code Definition. . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 17-6
17.2.2 Intel® Xeon® Processor 7400 Model Specific Error Code Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.2.2.1 Processor Model Specific Error Code Field, Type B: Bus and Interconnect Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.2.2.2 Processor Model Specific Error Code Field, Type C: Cache Bus Controller Error Codes  . . . . . . . . . . . . . . . . . .  . . . . . . . . . 17-7
17.3 INCREMENTAL DECODING INFORMAT ION: INTEL® XEON® PROCESSOR 3400,  3500, 5500 SERIES, MACHINE ERROR 
CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-7
17.3.1 Intel® QPI Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.3.2 Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9Vol. 3A xvCONTENTS
PAGE
17.3.3 Memory Controller Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9

PAGE
17.4 INCREMENTAL DECODING INFORMATIO N: INTEL® XEON® PROCESSOR E5 FAMILY, MACHINE ERROR CODES FOR MACHINE 
CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-10
17.4.1 Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-10
17.4.2 Intel® QPI Machine Check Errors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-11
17.4.3 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-11
17.5 INCREMENTAL DECODING INFORMATIO N: INTEL® XEON® PROCESSOR E5 V2 AND INTEL® XEON® PROCESSOR E7 V2 
FAMILIES, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .  17-13
17.5.1 Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-13
17.5.2 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-14
17.5.3 Home Agent Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-15
17.6 INCREMENTAL DECODING INFORMATIO N: INTEL® XEON® PROCESSOR E5 V3 FAMILY, MACHINE ERROR CODES FOR 
MACHINE CHECK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-15
17.6.1 Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-16
17.6.2 Intel® QPI Machine Check Errors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-17
17.6.3 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-17
17.6.4 Home Agent Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-19
17.7 INCREMENTAL DECODING INFORMATIO N: INTEL® XEON® PROCESSOR D FAMILY, MACHINE ERROR CODES FOR MACHINE 
CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-19
17.7.1 Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-19
17.7.2 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-20
17.8 INCREMENTAL DECODING INFORMATIO N: INTEL® XEON® PROCESSOR E5 V4 FAMILY, MACHINE ERROR CODES FOR 
MACHINE CHECK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-21
17.8.1 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-21
17.8.2 Home Agent Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-21
17.9 INCREMENTAL DECODING INFORMATIO N: INTEL® XEON® SCALABLE PROCESSO R FAMILY, MACHINE ERROR CODES FOR 
MACHINE CHECK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-22
17.9.1 Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-22
17.9.2 Interconnect Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-24
17.9.3 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-25
17.9.4 M2M Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-26
17.9.5 Home Agent Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-27
17.10 INCREMENTAL DECODING INFORMATIO N: PROCESSOR FAMILY WITH CPUID DI SPLAYFAMILY_DISPLAYMODEL SIGNATURE 
06_5FH, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .  17-28
17.10.1 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .17-28
17.11 INCREMENTAL DECODING INFORMATION: 3RD GENERATI ON INTEL® XEON® SCALABLE PROCESSOR FAMILY, MACHINE 
ERROR CODES FOR MACHINE CHECK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-28
17.11.1 Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-29
17.11.2 Interconnect Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-31
17.11.3 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .17-32
17.11.4 M2M Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-36
17.12 INCREMENTAL DECODING INFORMATIO N: PROCESSOR FAMILY WITH CPUID DI SPLAYFAMILY_DISPLAYMODEL SIGNATURE 
06_86H, MACHINE ERROR CODES FOR MACHINE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-36
17.12.1 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .17-36
17.12.2 M2M Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-37
17.13 INCREMENTAL DECODING INFORMATION: 4TH GENERATIO N INTEL® XEON® SCALABLE PROCESSOR FAMILY, MACHINE 
ERROR CODES FOR MACHINE CHECK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-37
17.13.1 Internal Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-37
17.13.2 Interconnect Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-39
17.13.3 Integrated Memory Controller Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .17-41
17.13.4 M2M Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-43

17.13.5 High Bandwidth Memory Machine Check Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-44
17.14 INCREMENTAL DECODING INFORMATIO N: PROCESSOR FAMILY 0FH, MACHINE ER ROR CODES FOR MACHINE CHECK. .  17-44
17.14.1 Model-Specific Machine Check Error Codes for the Intel® Xeon® Processor MP 7100 Series. . . . . . . . . . . . . . . . . . . . . . . .17-45
17.14.1.1 Processor Machine Check Status Register MCA Error Code Definition . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .17-46
17.14.2 Other_Info Field (All MCA Error Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-47
17.14.3 Processor Model Specific Error Code Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-48
17.14.3.1 MCA Error Type A: L3 Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-48
17.14.3.2 Processor Model Specific Error Code Field Type B: Bus and Interconnect Error . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .17-48
17.14.3.3 Processor Model Specific Error Code Field Type C: Cache Bus Controller Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-49CONTENTS
xvi Vol. 3APAGE
CHAPTER 18
DEBUG, BRANCH PROFILE, TSC, AND INTEL® RE SOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) 
FEATURES
18.1 OVERVIEW OF DEBUG SUPPORT FACILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-1
18.2 DEBUG REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-2
18.2.1 Debug Address Registers (DR0-DR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.2 Debug Registers DR4 and DR5  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.3 Debug Status Register (DR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.4 Debug Control Register (DR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.5 Breakpoint Field Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
18.2.6 Debug Registers and Intel® 64 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.3 DEBUG EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-7
18.3.1 Debug Exception (#DB)—Interrupt Vector 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.3.1.1 Instruction-Breakpoint Exception Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.3.1.2 Data Memory and I/O Breakpoint Exception Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .18-10
18.3.1.3 General-Detect Exception Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-10
18.3.1.4 Single-Step Exception Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-11
18.3.1.5 Task-Switch Exception Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-11
18.3.1.6 OS Bus-Lock Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-11
18.3.2 Breakpoint Exception (#BP)—Interrupt Vector 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-11
18.3.3 Debug Exceptions, Breakpoint Exceptions, and Restricted Transactional Memory (RTM) . . . . . . . . . . . . . . . . . . . . . . . . . .18-12
18.4 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING OVERVIEW  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-12
18.4.1 IA32_DEBUGCTL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-13
18.4.2 Monitoring Branches, Exceptions, and Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .18-14
18.4.3 Single-Stepping on Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-14
18.4.4 Branch Trace Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-15
18.4.4.1 Branch Trace Message Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-15
18.4.5 Branch Trace Store (BTS)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-15
18.4.6 CPL-Qualified Branch Trace Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-15
18.4.7 Freezing LBR and Performance Counters on PMI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-15
18.4.8 LBR Stack  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-17
18.4.8.1 LBR Stack and Intel® 64 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-18
18.4.8.2 LBR Stack and IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-19
18.4.8.3 Last Exception Records and Intel 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-19
18.4.9 BTS and DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-19
18.4.9.1 64 Bit Format of the DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-22
18.4.9.2 Setting Up the DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-24
18.4.9.3 Setting Up the BTS Buffer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-25
18.4.9.4 Setting Up CPL-Qualified BTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-26
18.4.9.5 Writing the DS Interrupt Service Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-26

18.5 LAST BRANCH, INTERRUPT, AND EXCEPTI ON RECORDING (INTEL® CORE™ 2 DUO AN D INTEL ATOM® PROCESSORS)  . .  18-27
18.5.1 LBR Stack  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-27
18.5.2 LBR Stack in Intel Atom® Processors based on the Silvermont Microarchitecture  . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .18-28
18.6 LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPT ION RECORDING FOR PROCESSORS BASED ON GOLDMONT 
MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-28
18.7 LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTIO N RECORDING FOR PROCESSORS BASED ON GOLDMONT PLUS 
MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-29
18.8 LAST BRANCH, INTERRUPT, AND EXCEPTI ON RECORDING FOR INTEL® XEON PHI™  PROCESSOR 7200/5200/3200 . . .  18-29
18.9 LAST BRANCH, INTERRUPT, AND EXCEPTION R ECORDING FOR PROCESSORS BASED ON NEHALEM 
18.9.1 LBR Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-30
18.9.2 Filtering of Last Branch Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-31
18.10 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR PROCES SORS BASED ON SANDY BRIDGE 
MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-31
18.11 LAST BRANCH, CALL STACK, INTERRUPT, AND EXCE PTION RECORDING FOR PROCESSORS BASED ON HASWELL 
MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-32
18.11.1 LBR Stack Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-33
18.12 LAST BRANCH, CALL STACK, INTERRUPT, AND EXCE PTION RECORDING FOR PROCESSORS BASED ON SKYLAKE 
MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-33
18.12.1 MSR_LBR_INFO_x MSR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-34
18.12.2 Streamlined Freeze_LBRs_On_PMI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .18-34
18.12.3 LBR Behavior and Deep C-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-35
18.13 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PROCESSORS BASED ON INTEL NETBURST® 
MICROARCHITECTURE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-35Vol. 3A xviiCONTENTS
PAGE
18.13.1 MSR_DEBUGCTLA MSR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-35
18.13.2 LBR Stack for Processors Based on Intel NetBurst® Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-36
18.13.3 Last Exception Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-37
18.14 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ SOLO AND INTEL® CORE™ DUO 
PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-38
18.15 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PENTIUM M PROCESSORS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-39
18.16 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (P6 FAMILY PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .  18-40
18.16.1 DEBUGCTLMSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-40
18.16.2 Last Branch and Last Exception MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-41
18.16.3 Monitoring Branches, Exceptions, and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-42
18.17 TIME-STAMP COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-42
18.17.1 Invariant TSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-43
18.17.2 IA32_TSC_AUX Register and RDTSCP Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .18-43
18.17.3 Time-Stamp Counter Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-44
18.17.4 Invariant Time-Keeping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-44
18.18 INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) MONITORING FEATURES  . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . .  18-44
18.18.1 Overview of Cache Monitoring Technology and Memory Bandwidth Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-45
18.18.2 Enabling Monitoring: Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-45
18.18.3 Enumeration and Detecting Support of Cache Monitoring Technology and Memory Bandwidth Monitoring . . . . . . . . .18-4618.18.4 Monitoring Resource Type and Capability Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-46
18.18.5 Feature-Specific Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-47
18.18.5.1 Cache Monitoring Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-48
18.18.5.2 Memory Bandwidth Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-48
18.18.6 Monitoring Resource RMID Association  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-49
18.18.7 Monitoring Resource Selection and Reporting Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-50
18.18.8 Monitoring Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-51
18.18.8.1 Monitoring Dynamic Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-51

18.18.8.2 Monitoring Operation With Power Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .18-51
18.18.8.3 Monitoring Operation with Other Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .18-52
18.18.8.4 Monitoring Operation with RAS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .18-52
18.19 INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18-52
18.19.1 Introduction to Cache Allocation Technology (CAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-52
18.19.2 Cache Allocation Technology Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-53
18.19.3 Code and Data Prioritization (CDP) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .18-56
18.19.4 Enabling Cache Allocation Technology Usage Flow  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-57
18.19.4.1 Enumeration and Detection Support of Cache Allocation Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-57
18.19.4.2 Cache Allocation Technology: Resource Type and Capability Enumeration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-58
18.19.4.3 Cache Allocation Technology: Cache Mask Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .18-61
18.19.4.4 Class of Service to Cache Mask Association: Common Across Allocation Features. . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .18-61
18.19.5 Code and Data Prioritization (CDP): Enumerating and Enabling L3 CDP Technology . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .18-62
18.19.5.1 Mapping Between L3 CDP Masks and CAT Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-62
18.19.6 Code and Data Prioritization (CDP): Enumerating and Enabling L2 CDP Technology . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .18-63
18.19.6.1 Mapping Between L2 CDP Masks and L2 CAT Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .18-64
18.19.6.2 Common L2 and L3 CDP Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-64
18.19.6.3 Cache Allocation Technology Dynamic Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-64
18.19.6.4 Cache Allocation Technology Operation With Power Saving Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-65
18.19.6.5 Cache Allocation Technology Operation with Other Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-65
18.19.6.6 Associating Threads with CAT/CDP Classes of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .18-65
18.19.7 Introduction to Memory Bandwidth Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .18-66
18.19.7.1 Memory Bandwidth Allocation Enumeration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .18-66
18.19.7.2 Memory Bandwidth Allocation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .18-67
18.19.7.3 Memory Bandwidth Allocation Usage Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .18-68
18.20 INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) FOR NON-CPU AGENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .  18-68
18.20.1 Non-CPU Agent Intel® RDT Features Enumeration Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .18-69
18.20.1.1  CPUID-Based Enumeration for Non-CPU Agent Intel® RDT Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 . . . . . . . . . . . . . .18-69
18.20.1.2  ACPI Enumeration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-70
18.20.2 Non-CPU Agent Intel® RDT Feature Enable MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-70
CHAPTER 19
LAST BRANCH RECORDS
19.1 BEHAVIOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.1 Logged Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.2 Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.1.2.1 Enabling and Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2CONTENTS
xviii Vol. 3APAGE
19.1.2.2 LBR Depth  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.1.2.3 Branch Type Enabling and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.1.2.4 Call-Stack Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
Call-Stack Mode and LBR Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.1.2.5 CPL Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.1.3 Record Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.1.3.1 IP Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.1.3.2 Branch Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.1.3.3 Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.1.3.4 Mispredict Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.1.3.5 Intel® TSX Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.1.4 Interaction with Other Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.1.4.1 SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.1.4.2 SMM Transfer Monitor (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.1.4.3 VMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.1.4.4 Intel® SGX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.1.4.5 Debug Exceptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.1.4.6 SMX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.1.4.7 MWAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.1.4.8 Processor Event-Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.2 MSRS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19-6
19.3 FAST LBR READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19-6
19.4 OTHER IMPACTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19-7
19.4.1 Branch Trace Store on Intel Atom® Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.4.2 IA32_DEBUGCTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.4.3 IA32_PERF_CAPABILITIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
CHAPTER 20
PERFORMANCE MONITORING
20.1 PERFORMANCE MONITORING OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20-1
20.2 ARCHITECTURAL PERFORMANCE MONITORING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  20-2
20.2.1 Architectural Performance Monitoring Version 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2.1.1 Architectural Performance Monitoring Version 1 Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 20-3
20.2.1.2 Pre-defined Architectural Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.2.2 Architectural Performance Monitoring Version 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.2.3 Architectural Performance Monitoring Version 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-10
20.2.3.1 AnyThread Counting and Software Evolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-13
20.2.4 Architectural Performance Monitoring Version 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-13
20.2.4.1 Enhancement in IA32_PERF_GLOBAL_STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .20-13
20.2.4.2 IA32_PERF_GLOBAL_STATUS_RESET and IA32_PERF_GLOBAL_STATUS_SET MSRS. . . . . . . . . . . . . . . . . . . . . . . . . .20 -15
20.2.4.3 IA32_PERF_GLOBAL_INUSE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-15
20.2.5 Architectural Performance Monitoring Version 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-17
20.2.5.1 AnyThread Mode Deprecation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-17
20.2.5.2 Fixed Counter Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-17
20.2.5.3 Domain Separation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-17
20.2.6 Full-Width Writes to Performance Counter Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-17
20.3 PERFORMANCE MONITORING (INTEL® CORE™ PROCESSORS AND INTEL® XEON® PROCESSORS) . . . . . . . . . . . . . . . . . . . . . .  20 -17
20.3.1 Performance Monitoring for Processors Based on Nehalem Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .20-17
20.3.1.1 Enhancements of Performance Monitoring in the Processor Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .20-18
20.3.1.2 Performance Monitoring Facility in the Uncore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .20-26
20.3.1.3 Intel® Xeon® Processor 7500 Series Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-31
20.3.2 Performance Monitoring for Processors Based on Westmere Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .20-32
20.3.3 Intel® Xeon® Processor E7 Family Performance Monitoring Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .20-33
20.3.4 Performance Monitoring for Processors Based on Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .20-33
20.3.4.1 Global Counter Control Facilities in Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-34
20.3.4.2 Counter Coalescence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-36
20.3.4.3 Full Width Writes to Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .20-36
20.3.4.4 PEBS Support in Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-36
20.3.4.5 Off-core Response Performance Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .20-41
20.3.4.6 Uncore Performance Monitoring Facilities in the Intel® Core™ i7-2xxx, Intel® Core™ i5-2 xxx, and Intel® Core™ i3-2xxx 
Processor Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-44
20.3.4.7 Intel® Xeon® Processor E5 Family Performance Monitoring Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .20-46
20.3.4.8 Intel® Xeon® Processor E5 Family Uncore Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .20-47Vol. 3A xixCONTENTS
PAGE
20.3.5 3rd Generation Intel® Core™ Processor Performance Monitoring Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-47
20.3.5.1 Intel® Xeon® Processor E5 v2 and E7 v2 Family Uncore Performance Monitoring Facility. . . . . . . . . . . . . . . . . .  . . . . .20-47

PAGE
20.3.6 4th Generation Intel® Core™ Processor Performance Monitoring Facility  . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .20-47
20.3.6.1 Processor Event Based Sampling (PEBS) Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .20-48
20.3.6.2 PEBS Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-49
20.3.6.3 PEBS Data Address Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-50
20.3.6.4 Off-core Response Performance Monitoring  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-51
20.3.6.5 Performance Monitoring and Intel® TSX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-53
20.3.6.6 Uncore Performance Monitoring Facilities in the 4th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . .20-55
20.3.6.7 Intel® Xeon® Processor E5 v3 Family Uncore Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .20-55
20.3.7 5th Generation Intel® Core™ Processor and Intel® Core™ M Processor Performance Monitoring Facility . . . . . . . . . . . . .20-56
20.3.8 6th Generation, 7th Generation and 8th Generation Intel® Core™ Processor Performance Monitoring Facility  . . . . . .20-57
20.3.8.1 Processor Event Based Sampling (PEBS) Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .20-58
20.3.8.2 Frontend Retired Facility  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-61
20.3.8.3 Off-core Response Performance Monitoring  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-63
20.3.8.4 Uncore Performance Monitoring Facilities on Intel® Co re™ Processors Based on Cannon Lake Microarchitecture.20-66
20.3.9 10th Generation Intel® Core™ Processor Performance Monitoring Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-66
20.3.9.1 Processor Event Based Sampling (PEBS) Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .20-67
20.3.9.2 Off-core Response Performance Monitoring  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-67
20.3.9.3 Performance Metrics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-69
20.3.10 12th and 13th Generation Intel® Core™ Processors, an d 4th Generation Intel® Xeon® Scalable Processor Family 
Performance Monitoring Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-70
20.3.10.1 P-core Performance Monitoring Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-70
20.3.10.2 E-core Performance Monitoring Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-73
20.3.10.3 Unhalted Reference Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-75
20.4 PERFORMANCE MONITORING (INTEL® XEON™ PHI PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20-76
20.4.1 Intel® Xeon Phi™ Processor 7200/5200/3200 Performance Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .20-76
20.4.1.1 Enhancements of Performance Monitoring in the Intel® Xeon Phi™ Processor Tile . . . . . . . . . . . . . . . . . . . . .  . . . . . . . .20-76
20.5 PERFORMANCE MONITORING (INTEL ATOM® PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .  20-80
20.5.1 Performance Monitoring (45 nm and 32 nm Intel Atom® Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-80
20.5.2 Performance Monitoring for Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-80
20.5.2.1 Enhancements of Performance Monitoring in the Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-80
20.5.2.2 Offcore Response Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-82
20.5.2.3 Average Offcore Request Latency Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-85
20.5.3 Performance Monitoring for Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .20-85
20.5.3.1 Processor Event Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-86
20.5.3.2 Offcore Response Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-89
20.5.3.3 Average Offcore Request Latency Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-90
20.5.4 Performance Monitoring for Goldmont Plus Microarchitecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-91
20.5.4.1 Extended PEBS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-91
20.5.5 Performance Monitoring for Tremont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-91
20.5.5.1 Adaptive PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-92
20.5.5.2 PEBS output to Intel® Processor Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-92
20.5.5.3 Precise Distribution Support on Fixed Counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .20-94
20.5.5.4 Compatibility Enhancements to Offcore Response MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-94
20.6 PERFORMANCE MONITORING (LEGACY INTEL PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20-96
20.6.1 Performance Monitoring (Intel® Core™ Solo and Intel® Core™ Duo Processors) . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .20-96
20.6.2 Performance Monitoring (Processors Based on Intel® Core™ Microarchitecture). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-97
20.6.2.1 Fixed-function Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-98
20.6.2.2 Global Counter Control Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-99
20.6.2.3 At-Retirement Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-101
20.6.2.4 Processor Event Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-101

20.6.3 Performance Monitoring (Processors Based on Intel NetBurst® Microarchitecture). . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 20-104
20.6.3.1 ESCR MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-107
20.6.3.2 Performance Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-108
20.6.3.3 CCCR MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-109
20.6.3.4 Debug Store (DS) Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-111
20.6.3.5 Programming the Performance Counters for Non-Retirement Events  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-111
20.6.3.6 At-Retirement Counting  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-117
20.6.3.7 Tagging Mechanism for Replay_event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-118
20.6.3.8 Processor Event-Based Sampling (PEBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-119
20.6.3.9 Operating System Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-120
20.6.4 Performance Monitoring and Intel® Hyper-Threadin g Technology in Processors Based on Intel NetBurst® 
Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-120
20.6.4.1 ESCR MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-120CONTENTS
xx Vol. 3APAGE
20.6.4.2 CCCR MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-121
20.6.4.3 IA32_PEBS_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-123
20.6.4.4 Performance Monitoring Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-123
20.6.4.5 Counting Clocks on systems with Intel® Hyper-Thre ading Technology in Processors Based on Intel NetBurst® 
Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-124
20.6.5 Performance Monitoring and Dual-Core Technology  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 20-125
20.6.6 Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3 Cache . . . . . . . . . . . . . . . . . . . . 20-125
20.6.7 Performance Monitoring on L3 and Caching Bus Controller Sub-Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-127
20.6.7.1 Overview of Performance Monitoring with L3/Caching Bus Controller  . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 20-129
20.6.7.2 GBSQ Event Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-130
20.6.7.3 GSNPQ Event Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-131
20.6.7.4 FSB Event Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-132
20.6.7.5 Common Event Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-133
20.6.8 Performance Monitoring (P6 Family Processor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 20-133
20.6.8.1 PerfEvtSel0 and PerfEvtSel1 MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-134
20.6.8.2 PerfCtr0 and PerfCtr1 MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-135
20.6.8.3 Starting and Stopping the Performance-Monitoring Counters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 20-135
20.6.8.4 Event and Time-Stamp Monitoring Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-135
20.6.8.5 Monitoring Counter Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-136
20.6.9 Performance Monitoring (Pentium Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 20-136
20.6.9.1 Control and Event Select Register (CESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-137
20.6.9.2 Use of the Performance-Monitoring Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 20-137
20.6.9.3 Events Counted  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-138
20.7 COUNTING CLOCKS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-138
20.7.1 Non-Halted Reference Clockticks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-139
20.7.2 Cycle Counting and Opportunistic Processor Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 20-139
20.7.3 Determining the Processor Base Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 20-140
20.7.3.1 For Intel® Processors Based on Sandy Bridge, Ivy Bridge, Haswell, and Broadwell Microarchitectures . . . . . . . . . 20 -140
20.7.3.2 For Intel® Processors Based on Nehalem Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 20-140
20.7.3.3 For Intel Atom® Processors Based on Silvermont Micr oarchitecture (Including Intel Processors Based on Airmont 
Microarchitecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-140
20.7.3.4 For Intel® Core™ 2 Processor Family and for Intel® Xeon ® Processors Based on Intel Core Microarchitecture . . . 20-140
20.8 IA32_PERF_CAPABILITIES MSR ENUMERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 20-141
20.8.1 Filtering of SMM Handler Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-142
20.9 PEBS FACILITY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-142

20.9.1 Extended PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-142
20.9.2 Adaptive PEBS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-144
20.9.2.1 Adaptive_Record Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-145
20.9.2.2 PEBS Record Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-146
20.9.2.3 MSR_PEBS_DATA_CFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-150
20.9.2.4 PEBS Record Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-151
20.9.3 Precise Distribution of Instructions Retired (PDIR) Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 20-153
20.9.4 Reduced Skid PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-153
20.9.5 EPT-Friendly PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-154
20.9.6 PDist: Precise Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-154
20.9.7 Load Latency Facility  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-154
20.9.8 Store Latency Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-155
CHAPTER 21
8086 EMULATION
21.1 REAL-ADDRESS MODE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21-1
21.1.1 Address Translation in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.1.2 Registers Supported in Real-Address Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.1.3 Instructions Supported in Real-Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.1.4 Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.2 VIRTUAL-8086 MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21-5
21.2.1 Enabling Virtual-8086 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.2.2 Structure of a Virtual-8086 Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.2.3 Paging of Virtual-8086 Tasks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.2.4 Protection within a Virtual-8086 Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.2.5 Entering Virtual-8086 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.2.6 Leaving Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.2.7 Sensitive Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10
21.2.8 Virtual-8086 Mode I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10Vol. 3A xxiCONTENTS
PAGE
21.2.8.1 I/O-Port-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-11
21.2.8.2 Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-11
21.2.8.3 Special I/O Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-11
21.3 INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21-11
21.3.1 Class 1—Hardware Interrupt and Exception Handling in Virtual-8086 Mode. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .21-12
21.3.1.1 Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate. . . . . . . . . . . . . . . . . . .  . . . . . .21-12
21.3.1.2 Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler  . . . . . . . . . . . . . . . . . . . .21-14
21.3.1.3 Handling an Interrupt or Exception Through a Task Gate  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-14
21.3.2 Class 2—Maskable Hardware Interrupt Handling in Virtual- 8086 Mode Using the Virtual Interrupt Mechanism . . . . .21-15
21.3.3 Class 3—Software Interrupt Handling in Virtual-8086 Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-16
21.3.3.1 Method 1: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-18
21.3.3.2 Methods 2 and 3: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .21-18
21.3.3.3 Method 4: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-19
21.3.3.4 Method 5: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-19
21.3.3.5 Method 6: Software Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-19
21.4 PROTECTED-MODE VIRTUAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21-20
CHAPTER 22
MIXING 16-BIT AND 32-BIT CODE
22.1 DEFINING 16-BIT AND 32-BIT PROGRAM MODULES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.2 MIXING 16-BIT AND 32-BIT OPERATIONS WITHIN A CODE SEGMENT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 22-2
22.3 SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.4 TRANSFERRING CONTROL AMONG MIXED-SIZE CODE SEGMENTS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 22-3

CHAPTER 22
22.4.1 Code-Segment Pointer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.4.2 Stack Management for Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.4.2.1 Controlling the Operand-Size Attribute For a Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.4.2.2 Passing Parameters With a Gate  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.4.3 Interrupt Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.4.4 Parameter Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.4.5 Writing Interface Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
CHAPTER 23
ARCHITECTURE COMPATIBILITY
23.1 PROCESSOR FAMILIES AND CATEGORIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.2 RESERVED BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.3 ENABLING NEW FUNCTIONS AND MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.4 DETECTING THE PRESENCE OF NEW FEATURES THROUGH SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.5 INTEL MMX TECHNOLOGY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.6 STREAMING SIMD EXTENSIONS (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.7 STREAMING SIMD EXTENSIONS 2 (SSE2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.8 STREAMING SIMD EXTENSIONS 3 (SSE3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.9 ADDITIONAL STREAMING SIMD EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.10 INTEL HYPER-THREADING TECHNOLOGY  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.11 MULTI-CORE TECHNOLOGY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.12 SPECIFIC FEATURES OF DUAL-CORE PROCESSOR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.13 NEW INSTRUCTIONS IN THE PENTIUM AND LATER IA-32 PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.13.1 Instructions Added Prior to the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.14 OBSOLETE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.15 UNDEFINED OPCODES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.16 NEW FLAGS IN THE EFLAGS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.16.1 Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 23-6
23.17 STACK OPERATIONS AND USER SOFTWARE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.17.1 PUSH SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.17.2 EFLAGS Pushed on the Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.18 X87 FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.18.1 Control Register CR0 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.18.2 x87 FPU Status Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.18.2.1 Condition Code Flags (C0 through C3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.18.2.2 Stack Fault Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.18.3 x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.18.4 x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.18.5 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9CONTENTS
xxii Vol. 3APAGE
23.18.5.1 NaNs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.18.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.18.6 Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-10
23.18.6.1 Denormal Operand Exception (#D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-10
23.18.6.2 Numeric Overflow Exception (#O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-10
23.18.6.3 Numeric Underflow Exception (#U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-10
23.18.6.4 Exception Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-10
23.18.6.5 CS and EIP For FPU Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-11

23.18.6.6 FPU Error Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-11
23.18.6.7 Assertion of the FERR# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-11
23.18.6.8 Invalid Operation Exception On Denormals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .23-11
23.18.6.9 Alignment Check Exceptions (#AC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-11
23.18.6.10 Segment Not Present Exception During FLDENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .23-12
23.18.6.11 Device Not Available Exception (#NM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-12
23.18.6.12 Coprocessor Segment Overrun Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-12
23.18.6.13 General Protection Exception (#GP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-12
23.18.6.14 Floating-Point Error Exception (#MF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-12
23.18.7 Changes to Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-12
23.18.7.1 FDIV, FPREM, and FSQRT Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-12
23.18.7.2 FSCALE Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-12
23.18.7.3 FPREM1 Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13
23.18.7.4 FPREM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13
23.18.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .23-13
23.18.7.6 FPTAN Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13
23.18.7.7 Stack Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13
23.18.7.8 FSIN, FCOS, and FSINCOS Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13
23.18.7.9 FPATAN Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13
23.18.7.10 F2XM1 Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13
23.18.7.11 FLD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-14
23.18.7.12 FXTRACT Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-14
23.18.7.13 Load Constant Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-14
23.18.7.14 FXAM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-14
23.18.7.15 FSAVE and FSTENV Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-14
23.18.8 Transcendental Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-14
23.18.9 Obsolete Instructions and Undefined Opcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .23-15
23.18.10 WAIT/FWAIT Prefix Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-15
23.18.11 Operands Split Across Segments and/or Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .23-15
23.18.12 FPU Instruction Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-15
23.19 SERIALIZING INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-16
23.20 FPU AND MATH COPROCESSOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  23-16
23.20.1 Intel® 387 and Intel® 287 Math Coprocessor Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .23-16
23.20.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .23-16
23.21 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-17
23.22 MEMORY MANAGEMENT FACILITIES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-19
23.22.1 New Memory Management Control Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-19
23.22.1.1 Physical Memory Addressing Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-19
23.22.1.2 Global Pages  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-19
23.22.1.3 Larger Page Sizes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-19
23.22.2 CD and NW Cache Control Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-19
23.22.3 Descriptor Types and Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-19
23.22.4 Changes in Segment Descriptor Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-20
23.23 DEBUG FACILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-20

23.23.1 Differences in Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-20
23.23.2 Differences in Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-20
23.23.3 Debug Registers DR4 and DR5  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-20
23.24 RECOGNITION OF BREAKPOINTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-20
23.25 EXCEPTIONS AND/OR EXCEPTION CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-21
23.25.1 Machine-Check Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-22
23.25.2 Priority of Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-22
23.25.3 Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .23-22
23.26 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-27
23.26.1 Interrupt Propagation Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-27
23.26.2 NMI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-27
23.26.3 IDT Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-27
23.27 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .  23-27Vol. 3A xxiiiCONTENTS
PAGE
23.27.1 Software Visible Differences Between the Local APIC and the 82489DX . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .23-28
23.27.2 New Features Incorporated in the Local APIC for the P6 Family and Pentium Processors . . . . . . . . . . . . . . . . . . . . . . . . .23-28
23.27.3 New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon Processors. . . . . . . . . . . . . . . . . . . . . . . .23-28
23.28 TASK SWITCHING AND TSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-28
23.28.1 P6 Family and Pentium Processor TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-29
23.28.2 TSS Selector Writes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-29
23.28.3 Order of Reads/Writes to the TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-29
23.28.4 Using A 16-Bit TSS with 32-Bit Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-29
23.28.5 Differences in I/O Map Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-29
23.29 CACHE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-30
23.29.1 Self-Modifying Code with Cache Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-30
23.29.2 Disabling the L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-31
23.30 PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-31
23.30.1 Large Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-31
23.30.2 PCD and PWT Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-31
23.30.3 Enabling and Disabling Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-32
23.31 STACK OPERATIONS AND SUPERVISOR SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  23-32
23.31.1 Selector Pushes and Pops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-32
23.31.2 Error Code Pushes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-32
23.31.3 Fault Handling Effects on the Stack  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-33
23.31.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .23-33
23.32 MIXING 16- AND 32-BIT SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-33
23.33 SEGMENT AND ADDRESS WRAPAROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-33
23.33.1 Segment Wraparound. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-34
23.34 STORE BUFFERS AND MEMORY ORDERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .  23-34
23.35 BUS LOCKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-35
23.36 BUS HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-35
23.37 MODEL-SPECIFIC EXTENSIONS TO THE IA-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .  23-35
23.37.1 Model-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-36
23.37.2 RDMSR and WRMSR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-36
23.37.3 Memory Type Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-36
23.37.4 Machine-Check Exception and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-36

23.37.5 Performance-Monitoring Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-37
23.38 TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23-37
23.39 INITIAL STATE OF PENTIUM, PENTIUM PRO AND PENTIUM 4 PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .  23-37
CHAPTER 24 
INTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
24.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.2 VIRTUAL MACHINE ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.3 INTRODUCTION TO VMX OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.4 LIFE CYCLE OF VMM SOFTWARE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.5 VIRTUAL-MACHINE CONTROL STRUCTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.6 DISCOVERING SUPPORT FOR VMX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.7 ENABLING AND ENTERING VMX OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.8 RESTRICTIONS ON VMX OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
CHAPTER 25
VIRTUAL MACHINE CONTROL STRUCTURES
25.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.2 FORMAT OF THE VMCS REGION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
25.3 ORGANIZATION OF VMCS DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.4 GUEST-STATE AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.4.1 Guest Register State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.4.2 Guest Non-Register State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.5 HOST-STATE AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.6 VM-EXECUTION CONTROL FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.6.1 Pin-Based VM-Execution Controls  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.6.2 Processor-Based VM-Execution Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-10
25.6.3 Exception Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-14
25.6.4 I/O-Bitmap Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-14
25.6.5 Time-Stamp Counter Offset and Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-14CONTENTS
xxiv Vol. 3APAGE
25.6.6 Guest/Host Masks and Read Shadows for CR0 and CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-14
25.6.7 CR3-Target Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-14
25.6.8 Controls for APIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-15
25.6.9 MSR-Bitmap Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-16
25.6.10 Executive-VMCS Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-16
25.6.11 Extended-Page-Table Pointer (EPTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-17
25.6.12 Virtual-Processor Identifier (VPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-17
25.6.13 Controls for PAUSE-Loop Exiting  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-17
25.6.14 VM-Function Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-18
25.6.15 VMCS Shadowing Bitmap Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-18
25.6.16 ENCLS-Exiting Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-18
25.6.17 ENCLV-Exiting Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-18
25.6.18 PCONFIG-Exiting Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-18
25.6.19 Control Field for Page-Modification Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-19
25.6.20 Controls for Virtualization Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-19
25.6.21 XSS-Exiting Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-19
25.6.22 Sub-Page-Permission-Table Pointer (SPPTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-19
25.6.23 Fields Related to Hypervisor-Managed Linear-Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20
25.6.24 Fields Related to PASID Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20
25.6.25 Instruction-Timeout Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20

25.6.26 Fields Controlling Virtualization of the IA32_SPEC_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .25-21
25.7 VM-EXIT CONTROL FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25-21
25.7.1 VM-Exit Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-21
25.7.2 VM-Exit Controls for MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-22
25.8 VM-ENTRY CONTROL FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25-23
25.8.1 VM-Entry Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-23
25.8.2 VM-Entry Controls for MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-24
25.8.3 VM-Entry Controls for Event Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-24
25.9 VM-EXIT INFORMATION FIELDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25-25
25.9.1 Basic VM-Exit Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-26
25.9.2 Information for VM Exits Due to Vectored Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-27
25.9.3 Information for VM Exits That Occur During Event Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-27
25.9.4 Information for VM Exits Due to Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .25-28
25.9.5 VM-Instruction Error Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-29
25.10 VMCS TYPES: ORDINARY AND SHADOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25-29
25.11 SOFTWARE USE OF THE VMCS AND RELATED STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25-29
25.11.1 Software Use of Virtual-Machine Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-29
25.11.2 VMREAD, VMWRITE, and Encodings of VMCS Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-30
25.11.3 Initializing a VMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-32
25.11.4 Software Access to Related Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-32
25.11.5 VMXON Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-32
CHAPTER 26
VMX NON-ROOT OPERATION
26.1 INSTRUCTIONS THAT CAUSE VM EXITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26-1
26.1.1 Relative Priority of Faults and VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
26.1.2 Instructions That Cause VM Exits Unconditionally  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.1.3 Instructions That Cause VM Exits Conditionally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2 OTHER CAUSES OF VM EXITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26-5
26.3 CHANGES TO INSTRUCTION BEHAVIOR IN VMX NON-ROOT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .  26-7
26.4 OTHER CHANGES IN VMX NON-ROOT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26-13
26.4.1 Event Blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-13
26.4.2 Treatment of Task Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-13
26.4.3 Shadow-Stack Updates  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-14
26.5 FEATURES SPECIFIC TO VMX NON-ROOT OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26-14
26.5.1 VMX-Preemption Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-14
26.5.2 Monitor Trap Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-15
26.5.3 Translation of Guest-Physical Addresses Using EPT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-16
26.5.4 Translation of Guest-Physical Addresses Used by Intel Processor Trace  . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .26-16
26.5.4.1 Guest-Physical Address Translation for Intel PT: Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .26-16
26.5.4.2 Trace-Address Pre-Translation (TAPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-17
26.5.5 APIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-17
26.5.6 VM Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-17
26.5.6.1 Enabling VM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-17Vol. 3A xxvCONTENTS
PAGE
26.5.6.2 General Operation of the VMFUNC Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .26-18
26.5.6.3 EPTP Switching  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-18
26.5.7 Virtualization Exceptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-19
26.5.7.1 Convertible EPT Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-20

PAGE
26.5.7.2 Virtualization-Exception Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-20
26.5.7.3 Delivery of Virtualization Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-21
26.5.8 PASID Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-21
26.6 UNRESTRICTED GUESTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26-22
CHAPTER 27
VM ENTRIES
27.1 BASIC VM-ENTRY CHECKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2 CHECKS ON VMX CONTROLS AND HOST-STATE AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 27-2
27.2.1 Checks on VMX Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2.1.1 VM-Execution Control Fields  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2.1.2 VM-Exit Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
27.2.1.3 VM-Entry Control Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.2.2 Checks on Host Control Registers, MSRs, and SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
27.2.3 Checks on Host Segment and Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
27.2.4 Checks Related to Address-Space Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.3 CHECKING AND LOADING GUEST STATE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.3.1 Checks on the Guest State Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.3.1.1 Checks on Guest Control Registers, Debug Registers, and MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 27-8
27.3.1.2 Checks on Guest Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-10
27.3.1.3 Checks on Guest Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-12
27.3.1.4 Checks on Guest RIP, RFLAGS, and SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-12
27.3.1.5 Checks on Guest Non-Register State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-13
27.3.1.6 Checks on Guest Page-Directory-Pointer-Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-15
27.3.2 Loading Guest State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-15
27.3.2.1 Loading Guest Control Registers, Debug Registers, and MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .27-15
27.3.2.2 Loading Guest Segment Registers and Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-17
27.3.2.3 Loading Guest RIP, RSP, RFLAGS, and SSP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .27-17
27.3.2.4 Loading Page-Directory-Pointer-Table Entries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .27-18
27.3.2.5 Updating Non-Register State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-18
27.3.3 Clearing Address-Range Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-18
27.4 LOADING MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27-18
27.5 TRACE-ADDRESS PRE-TRANSLATION (TAPT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .  27-19
27.6 EVENT INJECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27-19
27.6.1 Vectored-Event Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-19
27.6.1.1 Details of Vectored-Event Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-20
27.6.1.2 VM Exits During Event Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-21
27.6.1.3 Event Injection for VM Entries to Real-Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .27-22
27.6.2 Injection of Pending MTF VM Exits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-22
27.7 SPECIAL FEATURES OF VM ENTRY  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27-22
27.7.1 Interruptibility State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-22
27.7.2 Activity State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-23
27.7.3 Delivery of Pending Debug Exceptions after VM Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .27-24
27.7.4 VMX-Preemption Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-25
27.7.5 Interrupt-Window Exiting and Virtual-Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-25
27.7.6 NMI-Window Exiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-25
27.7.7 VM Exits Induced by the TPR Threshold  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-25
27.7.8 Pending MTF VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-26
27.7.9 VM Entries and Advanced Debugging Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-26

27.7.10 User-Interrupt Recognition After VM Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-26
27.8 VM-ENTRY FAILURES DURING OR AFTER LOADING GUEST STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27-26
27.9 MACHINE-CHECK EVENTS DURING VM ENTRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27-27
CHAPTER 28
VM EXITS
28.1 ARCHITECTURAL STATE BEFORE A VM EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.2 RECORDING VM-EXIT INFORMATION AND UPDATING VM-ENTRY CONTROL FIELDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 28-4
28.2.1 Basic VM-Exit Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4CONTENTS
xxvi Vol. 3APAGE
28.2.2 Information for VM Exits Due to Vectored Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-12
28.2.3 Information About NMI Unblocking Due to IRET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .28-13
28.2.4 Information for VM Exits During Event Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .28-13
28.2.5 Information for VM Exits Due to Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .28-15
28.3 SAVING GUEST STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28-21
28.3.1 Saving Control Registers, Debug Registers, and MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-23
28.3.2 Saving Segment Registers and Descriptor-Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-23
28.3.3 Saving RIP, RSP, RFLAGS, and SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-24
28.3.4 Saving Non-Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-26
28.4 SAVING MSRS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28-28
28.5 LOADING HOST STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28-28
28.5.1 Loading Host Control Registers, Debug Registers, MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .28-28
28.5.2 Loading Host Segment and Descriptor-Table Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .28-30
28.5.3 Loading Host RIP, RSP, RFLAGS, and SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-31
28.5.4 Checking and Loading Host Page-Directory-Pointer-Table Entries  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-31
28.5.5 Updating Non-Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-31
28.5.6 Clearing Address-Range Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-32
28.6 LOADING MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28-32
28.7 VMX ABORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28-32
28.8 MACHINE-CHECK EVENTS DURING VM EXIT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28-33
28.9 USER-INTERRUPT RECOGNITION AFTER VM EXIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  28-34
CHAPTER 29
VMX SUPPORT FOR AD DRESS TRANSLATION
29.1 VIRTUAL PROCESSOR IDENTIFIERS (VPIDS)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29-1
29.2 HYPERVISOR-MANAGED LINEAR-ADDRESS TRANSLATION (HLAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .  29-1
29.3 THE EXTENDED PAGE TABLE MECHANISM (EPT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29-1
29.3.1 EPT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.3.2 EPT Translation Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.3.3 EPT-Induced VM Exits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-10
29.3.3.1 EPT Misconfigurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-10
29.3.3.2 EPT Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-12
29.3.3.3 Prioritization of EPT Misconfigurations and EPT Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .29-15
29.3.4 Sub-Page Write Permissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-16
29.3.4.1 Write Accesses That Are Eligible for Sub-Page Write Permissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-17
29.3.4.2 Determining an Access’s Sub-Page Write Permission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-17
29.3.5 Accessed and Dirty Flags for EPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-18
29.3.6 Page-Modification Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-19
29.3.7 EPT and Memory Typing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-19
29.3.7.1 Memory Type Used for Accessing EPT Paging Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-19
29.3.7.2 Memory Type Used for Translated Guest-Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-19
29.4 CACHING TRANSLATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29-20
29.4.1 Information That May Be Cached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-20

29.4.2 Creating and Using Cached Translation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-21
29.4.3 Invalidating Cached Translation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-22
29.4.3.1 Operations that Invalidate Cached Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-22
29.4.3.2 Operations that Need Not Invalidate Cached Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-24
29.4.3.3 Guidelines for Use of the INVVPID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-24
29.4.3.4 Guidelines for Use of the INVEPT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .29-25
CHAPTER 30
APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
30.1 VIRTUAL APIC STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30-1
30.1.1 Virtualized APIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
30.1.2 TPR Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
30.1.3 PPR Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
30.1.4 EOI Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
30.1.5 Self-IPI Virtualization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
30.1.6 IPI Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
30.2 EVALUATION AND DELIVERY OF VIRTUAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  30-4
30.2.1 Evaluation of Pending Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4
30.2.2 Virtual-Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5Vol. 3A xxviiCONTENTS
PAGE
30.2.3 Virtualizing User-Interrupt Notifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6
30.3 VIRTUALIZING CR8-BASED TPR ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6
30.4 VIRTUALIZING MEMORY-MAPPED APIC ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 30-6
30.4.1 Priority of APIC-Access VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7
30.4.2 Virtualizing Reads from the APIC-Access Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8
30.4.3 Virtualizing Writes to the APIC-Access Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9
30.4.3.1 Determining Whether a Write Access is Virtualized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9
30.4.3.2 APIC-Write Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-10
30.4.3.3 APIC-Write VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-11
30.4.4 Instruction-Specific Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-11
30.4.5 Issues Pertaining to Page Size and TLB Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-12
30.4.6 APIC Accesses Not Directly Resulting From Linear Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-12
30.4.6.1 Guest-Physical Accesses to the APIC-Access Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-13
30.4.6.2 Physical Accesses to the APIC-Access Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-13
30.5 VIRTUALIZING MSR-BASED APIC ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30-14
30.6 POSTED-INTERRUPT PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30-15
30.7 VIRTUALIZING SENDUIPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30-16
CHAPTER 31
VMX INSTRUCTION REFERENCE
31.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
31.2 CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
31.3 VMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
INVEPT— Invalidate Translations Derived from EPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
INVVPID— Invalidate Translations Based on VPID  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6
VMCALL—Call to VM Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9
VMCLEAR—Clear Virtual-Machine Control Structure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 31-11
VMFUNC—Invoke VM function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13
VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 31-14
VMPTRLD—Load Pointer to Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 31-17
VMPTRST—Store Pointer to Virtual-Machine Control Structure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-19
VMREAD—Read Field from Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 31-21
VMRESUME—Resume Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 31-23

VMWRITE—Write Field to Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-24
VMXOFF—Leave VMX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26
VMXON—Enter VMX Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-28
31.4 VM INSTRUCTION ERROR NUMBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31-31
CHAPTER 32
SYSTEM MANAGEMENT MODE
32.1 SYSTEM MANAGEMENT MODE OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1
32.1.1 System Management Mode and VMX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.2 SYSTEM MANAGEMENT INTERRUPT (SMI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.3 SWITCHING BETWEEN SMM AND THE OTHER PROCESSOR OPERATING MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.3.1 Entering SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.3.2 Exiting From SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
32.4 SMRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.4.1 SMRAM State Save Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.4.1.1 SMRAM State Save Map and Intel 64 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 32-6
32.4.2 SMRAM Caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8
32.4.2.1 System Management Range Registers (SMRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9
32.5 SMI HANDLER EXECUTION ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9
32.5.1 Initial SMM Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9
32.5.2 SMI Handler Operating Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-10
32.5.3 Control-flow Enforcement Technology Interactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .32-11
32.6 EXCEPTIONS AND INTERRUPTS WITHIN SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32-11
32.7 MANAGING SYNCHRONOUS AND ASYNCHRONOUS SYSTEM MANAGEMENT INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . . .  32 -12
32.7.1 I/O State Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-12
32.8 NMI HANDLING WHILE IN SMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32-13
32.9 SMM REVISION IDENTIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32-13
32.10 AUTO HALT RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32-14CONTENTS
xxviii Vol. 3APAGE
32.10.1 Executing the HLT Instruction in SMM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-14
32.11 SMBASE RELOCATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32-14
32.12 I/O INSTRUCTION RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32-15
32.12.1 Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-16
32.13 SMM MULTIPLE-PROCESSOR CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  32-16
32.14 DEFAULT TREATMENT OF SMIS AND SMM WITH VMX OPERATION AND SMX OPERATION  . . . . . . . . . . . . . . . . . . . . . . . . . .  32-16
32.14.1 Default Treatment of SMI Delivery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-17
32.14.2 Default Treatment of RSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-18
32.14.3 Protection of CR4.VMXE in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-19
32.14.4 VMXOFF and SMI Unblocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-19
32.15 DUAL-MONITOR TREATMENT OF SMIs AND SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  32-19
32.15.1 Dual-Monitor Treatment Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-19
32.15.2 SMM VM Exits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-20
32.15.2.1 Architectural State Before a VM Exit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-20
32.15.2.2 Updating the Current-VMCS and Executive-VMCS Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .32-20
32.15.2.3 Recording VM-Exit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-20
32.15.2.4 Saving Guest State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-21
32.15.2.5 Updating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-21
32.15.3 Operation of the SMM-Transfer Monitor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-22
32.15.4 VM Entries that Return from SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-22
32.15.4.1 Checks on the Executive-VMCS Pointer Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-22

32.15.4.2 Checks on VM-Execution Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-22
32.15.4.3 Checks on VM-Entry Control Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-23
32.15.4.4 Checks on the Guest State Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-23
32.15.4.5 Loading Guest State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-23
32.15.4.6 VMX-Preemption Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-23
32.15.4.7 Updating the Current-VMCS and SMM-Transfer VMCS Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-24
32.15.4.8 VM Exits Induced by VM Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-24
32.15.4.9 SMI Blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-24
32.15.4.10 Failures of VM Entries That Return from SMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .32-24
32.15.5 Enabling the Dual-Monitor Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-25
32.15.6 Activating the Dual-Monitor Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-26
32.15.6.1 Initial Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-26
32.15.6.2 Updating the Current-VMCS and Executive-VMCS Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .32-27
32.15.6.3 Saving Guest State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-27
32.15.6.4 Saving MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-27
32.15.6.5 Loading Host State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-27
32.15.6.6 Loading MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-29
32.15.7 Deactivating the Dual-Monitor Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-29
32.16 SMI AND PROCESSOR EXTENDED STATE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32-29
32.17 MODEL-SPECIFIC SYSTEM MANAGEMENT ENHANCEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32-30
32.17.1 SMM Handler Code Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-30
32.17.2 SMI Delivery Delay Reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-30
32.17.3 Blocked SMI Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-30
CHAPTER 33
INTEL® PROCESSOR TRACE
33.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33-1
33.1.1 Features and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1
33.1.1.1 Packet Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1
33.2 INTEL® PROCESSOR TRACE OPERATIONAL MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  33-2
33.2.1 Change of Flow Instruction (COFI) Tracing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
33.2.1.1 Direct Transfer COFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
33.2.1.2 Indirect Transfer COFI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
33.2.1.3 Far Transfer COFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4
33.2.2 Software Trace Instrumentation with PTWRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4
33.2.3 Power Event Tracing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4
33.2.4 Event Tracing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
33.2.5 Trace Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
33.2.5.1 Filtering by Current Privilege Level (CPL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
33.2.5.2 Filtering by CR3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
33.2.5.3 Filtering by IP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
33.2.6 Packet Generation Enable Controls  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7
33.2.6.1 Packet Enable (PacketEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7Vol. 3A xxixCONTENTS
PAGE
33.2.6.2 Trigger Enable (TriggerEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8
33.2.6.3 Context Enable (ContextEn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8
33.2.6.4 Branch Enable (BranchEn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8
33.2.6.5 Filter Enable (FilterEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8
33.2.7 Trace Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-9

33.2.7.1 Single Range Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-9
33.2.7.2 Table of Physical Addresses (ToPA)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-10
Single Output Region ToPA Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 33-12
ToPA Table Entry Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12
ToPA STOP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-13
ToPA PMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-13
PMI Preservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-14
ToPA PMI and Single Output Region ToPA Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-14
ToPA PMI and XSAVES/XRSTORS State Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 33-15
ToPA Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-15
33.2.7.3 Trace Transport Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-16
33.2.7.4 Restricted Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-16
Modifications to Restricted Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 33-16
33.2.8 Enabling and Configuration MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-17
33.2.8.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-17
33.2.8.2 IA32_RTIT_CTL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-17
33.2.8.3 Enabling and Disabling Packet Generation with TraceEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .33-20
Disabling Packet Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-21
Other Writes to IA32_RTIT_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-21
33.2.8.4 IA32_RTIT_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-21
33.2.8.5 IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-22
33.2.8.6 IA32_RTIT_CR3_MATCH MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-22
33.2.8.7 IA32_RTIT_OUTPUT_BASE MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-23
33.2.8.8 IA32_RTIT_OUTPUT_MASK_PTRS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .33-23
33.2.9 Interaction of Intel® Processor Trace and Other Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .33-24
33.2.9.1 Intel® Transactional Synchronization Extensions (Intel® TSX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .33-24
33.2.9.2 TSX and IP Filtering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-25
33.2.9.3 System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-25
33.2.9.4 Virtual-Machine Extensions (VMX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-26
33.2.9.5 Intel® Software Guard Extensions (Intel® SGX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-26
33.2.9.6 SENTER/ENTERACCS and ACM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-26
33.2.9.7 Intel® Memory Protection Extensions (Intel® MPX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-26
33.3 CONFIGURATION AND PROGRAMMING GUIDELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33-26
33.3.1 Detection of Intel Processor Trace and Capability Enumeration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-26
33.3.1.1 Packet Decoding of RIP versus LIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-30
33.3.1.2 Model Specific Capability Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-30
33.3.2 Enabling and Configuration of Trace Packet Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-30
33.3.2.1 Enabling Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-30
33.3.2.2 Disabling Packet Generation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-31
33.3.3 Flushing Trace Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-31
33.3.4 Warm Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-31
33.3.5 Context Switch Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-31
33.3.5.1 Manual Trace Configuration Context Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-31
33.3.5.2 Trace Configuration Context Switch Using XSAVES/XRSTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .33-32
33.3.6 Cycle-Accurate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-32
33.3.6.1 Cycle Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-33
33.3.6.2 Cycle Packet Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-33

33.3.6.3 Cycle Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-33
33.3.7 Decoder Synchronization (PSB+)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-34
33.3.8 Internal Buffer Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-35
33.3.8.1 Overflow Impact on Enables  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-35
33.3.8.2 Overflow Impact on Timing Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-35
33.3.9 TNT Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-36
33.3.10 Operational Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-36
33.4 TRACE PACKETS AND DATA TYPES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33-36
33.4.1 Packet Relationships and Ordering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-36
33.4.1.1 Packet Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-37
Decoder Implications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-37CONTENTS
xxx Vol. 3APAGE
33.4.2 Packet Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-38
33.4.2.1 Taken/Not-taken (TNT) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-39
33.4.2.2 Target IP (TIP) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-40
IP Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-40
Indirect Transfer Compression for Returns (RET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .33-41
33.4.2.3 Deferred TIPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-42
33.4.2.4 Packet Generation Enable (TIP.PGE) Packet  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .33-43
33.4.2.5 Packet Generation Disable (TIP.PGD) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .33-44
33.4.2.6 Flow Update (FUP) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-45
FUP IP Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-45
33.4.2.7 Paging Information (PIP) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-47
33.4.2.8 MODE Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-47
MODE.Exec Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-48
MODE.TSX Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-49
33.4.2.9 TraceStop Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-50
33.4.2.10 Core:Bus Ratio (CBR) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-50
33.4.2.11 Timestamp Counter (TSC) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-51
33.4.2.12 Mini Time Counter (MTC) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-52
33.4.2.13 TSC/MTC Alignment (TMA) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-53
33.4.2.14 Cycle Count (CYC) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-54
33.4.2.15 VMCS Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-55
33.4.2.16 Overflow (OVF) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-56
33.4.2.17 Packet Stream Boundary (PSB) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-56
33.4.2.18 PSBEND Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-57
33.4.2.19 Maintenance (MNT) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-58
33.4.2.20 PAD Packet  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-58
33.4.2.21 PTWRITE (PTW) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-59
33.4.2.22 Execution Stop (EXSTOP) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-60
33.4.2.23 MWAIT Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-61
33.4.2.24 Power Entry (PWRE) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-62
33.4.2.25 Power Exit (PWRX) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-63
33.4.2.26 Block Begin Packet (BBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-64

33.4.2.27 Block Item Packet (BIP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-65
BIP State Value Encodings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-65
33.4.2.28 Block End Packet (BEP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-70
33.4.2.29 Control Flow Event (CFE) Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-71
CFE Packet Type and Vector Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-71
33.4.2.30 Event Data (EVD) Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-73
33.5 TRACING IN VMX OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33-73
33.5.1 VMX-Specific Packets and VMCS Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-74
33.5.2 Managing Trace Packet Generation Across VMX Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-74
33.5.2.1 System-Wide Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-75
33.5.2.2 Guest-Only Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-75
33.5.2.3 Emulation of Intel PT Traced State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-76
33.5.2.4 TSC Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-76
33.5.2.5 Failed VM Entry  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-76
33.5.2.6 VMX Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-77
33.6 TRACING AND SMM TRANSFER MONITOR (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  33-77
33.7 PACKET GENERATION SCENARIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33-77
33.8 SOFTWARE CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33-81
33.8.1 Tracing SMM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-81
33.8.2 Cooperative Transition of Multiple Trace Collection Agents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .33-81
33.8.3 Tracking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-81
33.8.3.1 Time Domain Relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-82
33.8.3.2 Estimating TSC within Intel PT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-82
33.8.3.3 VMX TSC Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-83
33.8.3.4 Calculating Frequency with Intel PT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33-83
CHAPTER 34
INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
34.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34-1
34.2 ENCLAVE INTERACTION AND PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .  34-1
34.3 ENCLAVE LIFE CYCLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34-2Vol. 3A xxxiCONTENTS
PAGE
34.4 DATA STRUCTURES AND ENCLAVE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2
34.5 ENCLAVE PAGE CACHE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2
34.5.1 Enclave Page Cache Map (EPCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3
34.6 ENCLAVE INSTRUCTIONS AND INTEL® SGX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3
34.7 DISCOVERING SUPPORT FOR INTEL® SGX AND ENABLING ENCLAVE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 34-4
34.7.1 Intel® SGX Opt-In Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5
34.7.2 Intel® SGX Resource Enumeration Leaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5
34.8 INTEL® SGX INTERACTIONS WITH CONTROL-FLOW ENFORCEMENT TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 34-7
34.8.1 CET in Enclaves Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7
34.8.2 Operations Not Supported on Shadow Stack Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 34-8
34.8.3 Indirect Branch Tracking – Legacy Compatibility Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8
CHAPTER 35
ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.1 OVERVIEW OF ENCLAVE EXECUTION ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 35-1
35.2 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1
35.3 ACCESS-CONTROL REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1
35.4 SEGMENT-BASED ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2
35.5 PAGE-BASED ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2
35.5.1 Access-control for Accesses that Originate from Non-SGX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 35-2

35.5.2 Memory Accesses that Split Across ELRANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2
35.5.3 Implicit vs. Explicit Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3
35.5.3.1 Explicit Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3
35.5.3.2 Implicit Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3
35.6 INTEL® SGX DATA STRUCTURES OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4
35.7 SGX ENCLAVE CONTROL STRUCTURE (SECS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5
35.7.1 ATTRIBUTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
35.7.2 SECS.MISCSELECT Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
35.7.3 SECS.CET_ATTRIBUTES Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
35.8 THREAD CONTROL STRUCTURE (TCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-7
35.8.1 TCS.FLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8
35.8.2 State Save Area Offset (OSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8
35.8.3 Current State Save Area Frame (CSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8
35.8.4 Number of State Save Area Frames (NSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8
35.9 STATE SAVE AREA (SSA) FRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8
35.9.1 GPRSGX Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-9
35.9.1.1 EXITINFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-10
35.9.1.2 VECTOR Field Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-10
35.9.2 MISC Region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-11
35.9.2.1 EXINFO Structure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-11
35.9.2.2 Page Fault Error Code  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-12
35.10 CET STATE SAVE AREA FRAME. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-12
35.11 PAGE INFORMATION (PAGEINFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-12
35.12 SECURITY INFORMATION (SECINFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-13
35.12.1 SECINFO.FLAGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-13
35.12.2 PAGE_TYPE Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-13
35.13 PAGING CRYPTO METADATA (PCMD)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-14
35.14 ENCLAVE SIGNATURE STRUCTURE (SIGSTRUCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-14
35.15 EINIT TOKEN STRUCTURE (EINITTOKEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-15
35.16 REPORT (REPORT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-16
35.16.1 REPORTDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-17
35.17 REPORT TARGET INFO (TARGETINFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-17
35.18 KEY REQUEST (KEYREQUEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-17
35.18.1 KEY REQUEST KeyNames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-18
35.18.2 Key Request Policy Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-18
35.19 VERSION ARRAY (VA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-19
35.20 ENCLAVE PAGE CACHE MAP (EPCM)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-19
35.21 READ INFO (RDINFO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35-19
35.21.1 RDINFO Status Structure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-20
35.21.2 RDINFO Flags Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-20CONTENTS
xxxii Vol. 3APAGE
CHAPTER 36 
ENCLAVE OPERATION
36.1 CONSTRUCTING AN ENCLAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36-1
36.1.1 ECREATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2
36.1.2 EADD and EEXTEND Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2

CHAPTER 36 
36.1.3 EINIT Interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2
36.1.4 Intel® SGX Launch Control Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3
36.2 ENCLAVE ENTRY AND EXITING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36-3
36.2.1 Controlled Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3
36.2.2 Asynchronous Enclave Exit (AEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4
36.2.3 Resuming Execution After AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4
36.2.3.1 ERESUME Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5
36.2.3.2 Asynchronous Enclave Exit Notify and EDECCSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 36-5
36.3 CALLING ENCLAVE PROCEDURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36-6
36.3.1 Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
36.3.2 Register Preservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
36.3.3 Returning to Caller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
36.4 INTEL® SGX KEY AND ATTESTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36-6
36.4.1 Enclave Measurement and Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
36.4.1.1 MRENCLAVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
36.4.1.2 MRSIGNER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
36.4.1.3 CONFIGID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
36.4.2 Security Version Numbers (SVN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
36.4.2.1 Enclave Security Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8
36.4.2.2 Hardware Security Version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8
36.4.2.3 CONFIGID Security Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8
36.4.3 Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8
36.4.3.1 Sealing Enclave Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9
36.4.3.2 Using REPORTs for Local Attestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9
36.5 EPC AND MANAGEMENT OF EPC PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36-10
36.5.1 EPC Implementation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-10
36.5.2 OS Management of EPC Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-10
36.5.2.1 Enhancement to Managing EPC Pages  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .36-10
36.5.3 Eviction of Enclave Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-10
36.5.4 Loading an Enclave Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-11
36.5.5 Eviction of an SECS Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-11
36.5.6 Eviction of a Version Array Page  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-12
36.5.7 Allocating a Regular Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-12
36.5.8 Allocating a TCS Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-12
36.5.9 Trimming a Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-13
36.5.10 Restricting the EPCM Permissions of a Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-13
36.5.11 Extending the EPCM Permissions of a Page  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-14
36.5.12 VMM Oversubscription of EPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-14
36.6 CHANGES TO INSTRUCTION BEHAVIOR INSIDE AN ENCLAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .  36-14
36.6.1 Illegal Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-15
36.6.2 RDRAND and RDSEED Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-15
36.6.3 PAUSE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-15
36.6.4 Executions of INT1 and INT3 Inside an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-16
36.6.5 INVD Handling when Enclaves Are Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-16
CHAPTER 37
ENCLAVE EXITING EVENTS

CHAPTER 37
37.1 COMPATIBLE SWITCH TO THE EXITING STACK OF AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37-1
37.2 STATE SAVING BY AEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37-2
37.3 SYNTHETIC STATE ON ASYNCHRONOUS ENCLAVE EXIT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37-3
37.3.1 Processor Synthetic State on Asynchronous Enclave Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 37-3
37.3.2 Synthetic State for Extended Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3
37.3.3 Synthetic State for MISC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4
37.4 AEX FLOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37-4
37.4.1 AEX Operational Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5Vol. 3A xxxiiiCONTENTS
PAGE
CHAPTER 38 
INTEL® SGX INSTRUCTION REFERENCES
38.1 INTEL® SGX INSTRUCTION SYNTAX AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1
38.1.1 ENCLS Register Usage Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1
38.1.2 ENCLU Register Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
38.1.3 ENCLV Register Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
38.1.4 Information and Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
38.1.5 Internal CREGs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3
38.1.6 Concurrent Operation Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4
38.1.6.1 Concurrency Tables of Intel® SGX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4
38.2 INTEL® SGX INSTRUCTION REFERENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-8
ENCLS—Execute an Enclave System Function of Specified Leaf Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-9
ENCLU—Execute an Enclave User Function of Specified Leaf Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 38-11
ENCLV—Execute an Enclave VMM Function of Specified Leaf Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 38-14
38.3 INTEL® SGX SYSTEM LEAF FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38-16
EADD—Add a Page to an Uninitialized Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 38-17
EAUG—Add a Page to an Initialized Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 38-22
EBLOCK—Mark a page in EPC as Blocked  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 38-27
ECREATE—Create an SECS page in the Enclave Page Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-30
EDBGRD—Read From a Debug Enclave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 38-36
EDBGWR—Write to a Debug Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-40
EEXTEND—Extend Uninitialized Enclave Measurement by 256 Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-44
EINIT—Initialize an Enclave for Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-47
ELDB/ELDU/ELDBC/ELDUC—Load an EPC Page and Mark its State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-55
EMODPR—Restrict the Permissions of an EPC Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-61
EMODT—Change the Type of an EPC Page  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 38-64
EPA—Add Version Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-67
ERDINFO—Read Type and Status Information About an EPC Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 38-69
EREMOVE—Remove a page from the EPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 38-73
ETRACK—Activates EBLOCK Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-77
ETRACKC—Activates EBLOCK Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-80
EWB—Invalidate an EPC Page and Write out to Main Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 38-84
38.4 INTEL® SGX USER LEAF FUNCTION REFERENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38-89
EACCEPT—Accept Changes to an EPC Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 38-90
EACCEPTCOPY—Initialize a Pending Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 38-95
EDECCSSA—Decrements TCS.CSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-99
EENTER—Enters an Enclave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-103
EEXIT—Exits an Enclave  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-112
EGETKEY—Retrieves a Cryptographic Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .38-115
EMODPE—Extend an EPC Page Permissions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-125
EREPORT—Create a Cryptographic Report of the Enclave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .38-128
ERESUME—Re-Enters an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .38-133
38.5 INTEL® SGX VIRTUALIZATION LEAF FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38-145

EDECVIRTCHILD—Decrement VIRTCHILDCNT in SECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .38-146
EINCVIRTCHILD—Increment VIRTCHILDCNT in SECS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-150
ESETCONTEXT—Set the ENCLAVECONTEXT Field in SECS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-153
CHAPTER 39
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
39.1 INTEL® SGX AVAILABILITY IN VARIOUS PROCESSOR MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 39-1
39.2 IA32_FEATURE_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1
39.2.1 Availability of Intel SGX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1
39.2.2 Intel SGX Launch Control Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1
39.3 INTERACTIONS WITH SEGMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1
39.3.1 Scope of Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1
39.3.2 Interactions of Intel® SGX Instructions with Segment, Operand, and Addressing Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
39.3.3 Interaction of Intel® SGX Instructions with Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
39.3.4 Interactions of Enclave Execution with Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 39-2
39.4 INTERACTIONS WITH PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
39.5 INTERACTIONS WITH VMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3CONTENTS
xxxiv Vol. 3APAGE
39.5.1 VMM Controls to Configure Guest Support of Intel® SGX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3
39.5.2 Interactions with the Extended Page Table Mechanism (EPT)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 39-3
39.5.3 Interactions with APIC Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4
39.5.4 Interactions with VT and SGX concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4
39.5.5 Virtual Child Tracking  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
39.5.6 Handling EPCM Entry Lock Conflicts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
39.5.7 Context Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6
39.6 INTEL® SGX INTERACTIONS WITH ARCHITECTURALLY-VISIBLE EVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39-6
39.7 INTERACTIONS WITH THE PROCESSOR EXTENDED STATE AND MISCELLANEOUS STATE  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39-6
39.7.1 Requirements and Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6
39.7.2 Relevant Fields in Various Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7
39.7.2.1 SECS.ATTRIBUTES.XFRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7
39.7.2.2 SECS.SSAFRAMESIZE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8
39.7.2.3 XSAVE Area in SSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8
39.7.2.4 MISC Area in SSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8
39.7.2.5 SIGSTRUCT Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8
39.7.2.6 REPORT.ATTRIBUTES.XFRM and REPORT.MISCSELECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 39-9
39.7.2.7 KEYREQUEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
39.7.3 Processor Extended States and ENCLS[ECREATE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
39.7.4 Processor Extended States and ENCLU[EENTER] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
39.7.4.1 Fault Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
39.7.4.2 State Loading  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9
39.7.5 Processor Extended States and AEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
39.7.5.1 State Saving  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
39.7.5.2 State Synthesis  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
39.7.6 Processor Extended States and ENCLU[ERESUME]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .39-10
39.7.6.1 Fault Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
39.7.6.2 State Loading  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
39.7.7 Processor Extended States and ENCLU[EEXIT] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
39.7.8 Processor Extended States and ENCLU[EREPORT]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .39-11
39.7.9 Processor Extended States and ENCLU[EGETKEY] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .39-11
39.8 INTERACTIONS WITH SMM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39-11

39.8.1 Availability of Intel® SGX instructions in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-11
39.8.2 SMI while Inside an Enclave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-11
39.8.3 SMRAM Synthetic State of AEX Triggered by SMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-11
39.9 INTERACTIONS OF INIT, SIPI, AND WAIT-FOR-SIPI WITH INTEL® SGX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39-12
39.10 INTERACTIONS WITH DMA  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39-12
39.11 INTERACTIONS WITH TXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39-12
39.11.1 Enclaves Created Prior to Execution of GETSEC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .39-12
39.11.2 Interaction of GETSEC with Intel® SGX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-12
39.11.3 Interactions with Authenticated Code Modules (ACMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .39-13
39.12 INTERACTIONS WITH CACHING OF LINEAR-ADDRESS TRANSLATIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .  39-13
39.13 INTERACTIONS WITH INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS (INTEL® TSX)  . . . . . . . . . . . . . . . . . . . . .  3 9-13
39.13.1 HLE and RTM Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-14
39.14 INTEL® SGX INTERACTIONS WITH S STATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .  39-14
39.15 INTEL® SGX INTERACTIONS WITH MACHINE CHECK ARCHITECTURE (MCA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .  39-14
39.15.1 Interactions with MCA Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-14
39.15.2 Machine Check Enables (IA32_MCi_CTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-14
39.15.3 CR4.MCE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-14
39.16 INTEL® SGX INTERACTIONS WITH PROTECTED MODE VIRTUAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39-15
39.17 INTEL SGX INTERACTION WITH PROTECTION KEYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  39-15
CHAPTER 40 
ENCLAVE CODE DEBUG AND PROFILING
40.1 CONFIGURATION AND CONTROLS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40-1
40.1.1 Debug Enclave vs. Production Enclave  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1
40.1.2 Tool-Chain Opt-in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1
40.1.3 Debugging an Enclave That Uses Asynchronous Enclave Exit Notify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1
40.2 SINGLE STEP DEBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40-1
40.2.1 Single Stepping ENCLS Instruction Leafs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1
40.2.2 Single Stepping ENCLU Instruction Leafs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2
40.2.3 Single-Stepping Enclave Entry with Opt-out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2
40.2.3.1 Single Stepping without AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2
40.2.3.2 Single Step Preempted by AEX Due to Non-SMI Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 40-2Vol. 3A xxxvCONTENTS
PAGE
40.2.4 RFLAGS.TF Treatment on AEX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
40.2.5 Restriction on Setting of TF after an Opt-Out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
40.2.6 Trampoline Code Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
40.3 CODE AND DATA BREAKPOINTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
40.3.1 Breakpoint Suppression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
40.3.2 Reporting of Instruction Breakpoint on Next Instruction on a Debug Trap  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 40-4
40.3.3 RF Treatment on AEX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4
40.3.4 Breakpoint Matching in Intel® SGX Instruction Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4
40.4 CONSIDERATION OF THE INT1 AND INT3 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 40-4
40.4.1 Behavior of INT1 and INT3 Inside an Enclave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4
40.4.2 Debugger Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4
40.4.3 VMM Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5
40.5 BRANCH TRACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5
40.5.1 BTF Treatment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5
40.5.2 LBR Treatment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5
40.5.2.1 LBR Stack on Opt-in Entry  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5
40.5.2.2 LBR Stack on Opt-out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-6

40.5.2.3 Mispredict Bit, Record Type, and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7
40.6 INTERACTION WITH PERFORMANCE MONITORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7
40.6.1 IA32_PERF_GLOBAL_STATUS Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7
40.6.2 Performance Monitoring with Opt-in Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7
40.6.3 Performance Monitoring with Opt-out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-8
40.6.4 Enclave Exit and Performance Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-8
40.6.5 PEBS Record Generation on Intel® SGX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-8
40.6.6 Exception-Handling on PEBS/BTS Loads/Stores after AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 40-8
40.6.6.1 Other Interactions with Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 40-9
APPENDIX A
VMX CAPABILITY REPORTING FACILITY
A.1 BASIC VMX INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-1
A.2 RESERVED CONTROLS AND DEFAULT SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .  A-2
A.3 VM-EXECUTION CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-2
A.3.1 Pin-Based VM-Execution Controls  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.3.2 Primary Processor-Based VM-Execution Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.3.3 Secondary Processor-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . A-4
A.3.4 Tertiary Processor-Based VM-Execution Controls  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A.4 VM-EXIT CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-4
A.4.1 Primary VM-Exit Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A.4.2 Secondary VM-Exit Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.5 VM-ENTRY CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-5
A.6 MISCELLANEOUS DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-6
A.7 VMX-FIXED BITS IN CR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-7
A.8 VMX-FIXED BITS IN CR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-7
A.9 VMCS ENUMERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-7
A.10 VPID AND EPT CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-8
A.11 VM FUNCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  A-9
APPENDIX B
FIELD ENCODING IN VMCS
B.1 16-BIT FIELDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-1
B.1.1 16-Bit Control Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1.2 16-Bit Guest-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1.3 16-Bit Host-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
B.2 64-BIT FIELDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-2
B.2.1 64-Bit Control Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
B.2.2 64-Bit Read-Only Data Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
B.2.3 64-Bit Guest-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
B.2.4 64-Bit Host-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
B.3 32-BIT FIELDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  B-7
B.3.1 32-Bit Control Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
B.3.2 32-Bit Read-Only Data Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
B.3.3 32-Bit Guest-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8CONTENTS
xxxvi Vol. 3APAGE
B.3.4 32-Bit Host-State Field  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
B.4 NATURAL-WIDTH FIELDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
B.4.1 Natural-Width Control Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
B.4.2 Natural-Width Read-Only Data Fields  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
B.4.3 Natural-Width Guest-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10

B.4.4 Natural-Width Host-State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11
APPENDIX C
VMX BASIC EXIT REASONSVol. 3A xxxviiCONTENTS
PAGE
FIGURES
Figure 1-1. Bit and Byte Order  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Figure 2-1. IA-32 System-Level Registers and Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2. System-Level Registers and Data Structures in IA-32e Mode and 4-Level Paging . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 2-3
Figure 2-3. Transitions Among the Processor’s Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-4. IA32_EFER MSR Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 2-5. System Flags in the EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2-6. Memory Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Figure 2-7. Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Figure 2-8. XCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Figure 2-9. Format of Protection-Key Rights Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Figure 2-10. WBINVD Invalidation of Shared and Non-Shared Cache Hierarchy  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Figure 3-1. Segmentation and Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-2. Flat Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Figure 3-3. Protected Flat Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Figure 3-4. Multi-Segment Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Figure 3-5. Logical Address to Linear Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-6. Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-7. Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-8. Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Figure 3-9. Segment Descriptor When Segment-Present Flag Is Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 3-11
Figure 3-10. Global and Local Descriptor Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Figure 3-11. Pseudo-Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Figure 4-1. Enabling and Changing Paging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-2. Linear-Address Translation to a 4-KByte Page using 32-Bit Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Figure 4-4. Formats of CR3 and Paging-Structure Entries with 32-Bit Paging . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-11
Figure 4-3. Linear-Address Translation to a 4-MByte Page using 32-Bit Paging  . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 4-11
Figure 4-5. Linear-Address Translation to a 4-KByte Page using PAE Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-16
Figure 4-6. Linear-Address Translation to a 2-MByte Page using PAE Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-17
Figure 4-7. Formats of CR3 and Paging-Structure Entries with PAE Paging  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Figure 4-8. Linear-Address Translation to a 4-KByte Page Using 4-Level Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Figure 4-9. Linear-Address Translation to a 2-MByte Page using 4-Level Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Figure 4-10. Linear-Address Translation to a 1-GByte Page using 4-Level Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Figure 4-11. Formats of CR3 and Paging-Structure Entries with 4-Level Paging and 5-Level Paging . . . . . . . . . . . . . . . . .  . . . . . . . . 4-32
Figure 4-12. Page-Fault Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Figure 4-13. Memory Management Convention That Assigns a Page Table to Each Segment . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 4-55
Figure 5-1. Descriptor Fields Used for Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Figure 5-2. Descriptor Fields with Flags used in IA-32e Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Figure 5-3. Protection Rings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Figure 5-4. Privilege Check for Data Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Figure 5-5. Examples of Accessing Data Segments From Various Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 5-9
Figure 5-6. Privilege Check for Control Transfer Without Using a Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 5-11
Figure 5-7. Examples of Accessing Conforming and Nonconforming Code Segments From Various Privilege Levels. . . . . . . . . . 5- 12
Figure 5-8. Call-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Figure 5-9. Call-Gate Descriptor in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Figure 5-10. Call-Gate Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Figure 5-11. Privilege Check for Control Transfer with Call Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Figure 5-12. Example of Accessing Call Gates At Various Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 5-17
Figure 5-13. Stack Switching During an Interprivilege-Level Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Figure 5-14. MSRs Used by SYSCALL and SYSRET  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Figure 5-15. Use of RPL to Weaken Privilege Level of Called Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 5-26
Figure 6-1. Relationship of the IDTR and IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Figure 6-2. IDT Gate Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Figure 6-3. Interrupt Procedure Call  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Figure 6-4. Stack Usage on Transfers to Interrupt and Exception-Handling Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Figure 6-5. Shadow Stack Usage on Transfers to Interrupt and Exception-Handling Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Figure 6-6. Interrupt Task Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Figure 6-7. Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Figure 6-8. 64-Bit IDT Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Figure 6-9. IA-32e Mode Stack Usage After Privilege Level Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Figure 6-10. Interrupt Shadow Stack Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Figure 6-11. Page-Fault Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46CONTENTS
xxxviii Vol. 3APAGE
Figure 6-12. Exception Error Code Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
Figure 8-1. Structure of a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
Figure 8-2. 32-Bit Task-State Segment (TSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
Figure 8-3. TSS Descriptor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6
Figure 8-4. Format of TSS and LDT Descriptors in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7
Figure 8-5. Task Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
Figure 8-6. Task-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
Figure 8-7. Task Gates Referencing the Same Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9
Figure 8-8. Nested Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Figure 8-9. Overlapping Linear-to-Physical Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Figure 8-10. 16-Bit TSS Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Figure 8-11. 64-Bit TSS Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Figure 9-1. Example of Write Ordering in Multiple-Processor Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .9-8
Figure 9-2. Interpretation of APIC ID in Early MP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Figure 9-3. Local APICs and I/O APIC in MP System Supporting Intel HT Technology  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 9-27
Figure 9-4. IA-32 Processor with Two Logical Processors Supporting Intel HT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
Figure 9-5. Generalized Seven-Domain Interpretation of the APIC ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
Figure 9-6. Conceptual Six-Domain Topology and 32-bit APIC ID Composition. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 9-36
Figure 9-7. Topological Relationships Between Hierarchical IDs in a Hypothetical MP Platform . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 9-39
Figure 9-8. MP System Wi th Multiple Pentium III Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-56
Figure 10-1. Contents of CR0 Register after Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Figure 10-2. Version Information in the EDX Register after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Figure 10-3. Processor State After Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Figure 10-4. Constructing Temporary GDT and Switching to Protected Mode (Lines 162-172 of List File) . . . . . . . . . . . . . . . . . . . 10-23
Figure 10-5. Moving the GDT, IDT, and TSS from ROM to RAM (Lines 196-261 of List File) . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 10-24
Figure 10-6. Task Switching (Lines 282-296 of List File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
Figure 10-7. Applying Microcode Updates  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
Figure 10-8. Microcode Update Write Operation Flow [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45
Figure 10-9. Microcode Update Write Operation Flow [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-46
Figure 11-1. Relationship of Local APIC and I/O APIC In Single-Processor Systems  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 11-2
Figure 11-2. Local APICs and I/O APIC When Intel Xeon Processors Are Used in Multiple-Processor Systems  . . . . . . . . . . . . .  . . . . 11-3

Figure 11-3. Local APICs and I/O AP IC When P6 Family Processors Are Used in Multiple-Processor Systems . . . . . . . . . . . . . . . . . . 11-3
Figure 11-4. Local APIC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Figure 11-5. IA32_APIC_BASE MSR (APIC_BASE_MSR in P6 Family) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Figure 11-6. Local APIC ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Figure 11-7. Local APIC Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Figure 11-8. Local Vector Table (LVT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Figure 11-9. Error Status Register (ESR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Figure 11-10. Divide Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Figure 11-11. Initial Count and Current Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Figure 11-12. Interrupt Command Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Figure 11-13. Logical Destination Register (LDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
Figure 11-14. Destination Format Register (DFR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
Figure 11-15. Arbitration Priority Register (APR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
Figure 11-16. Interrupt Acceptance Flow Chart for the Local APIC (Pentium 4 and Intel Xeon Processors). . . . . . . . . . . . . . . . . . . . 11-27
Figure 11-17. Interrupt Acceptance Flow Chart for the Local APIC (P6 Family and Pentium Processors) . . . . . . . . . . . . . . . . . . . . . . 11-28
Figure 11-18. Task-Priority Register (TPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
Figure 11-19. Processor-Priority Register (PPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
Figure 11-20. IRR, ISR, and TMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
Figure 11-21. EOI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
Figure 11-22. CR8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32
Figure 11-23. Spurious-Interrupt Vector Register (SVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
Figure 11-24. Layout of the MSI Message Address Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
Figure 11-25. Layout of the MSI Message Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36
Figure 11-26. IA32_APIC_BASE MSR Supporting x2APIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
Figure 11-27. Local x2APIC State Transitions with IA32_APIC_BASE, INIT, and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42
Figure 11-28. Interrupt Command Register (ICR) in x2APIC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 11-45
Figure 11-29. Logical Destination Register in x2APIC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46
Figure 11-30. SELF IPI register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47
Figure 12-1. Cache Structure of the Pentium 4 and Intel Xeon Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Figure 12-2. Cache Structure of the Intel Core i7 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Figure 12-3. Cache-Control Registers and Bits Available in Intel 64 and IA-32 Processors . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 12-11
Figure 12-4. Mapping Physical Memory With MTRRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
Figure 12-5. IA32_MTRRCAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
Figure 12-6. IA32_MTRR_DEF_TYPE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23Vol. 3A xxxixCONTENTS
PAGE
Figure 12-7. IA32_MTRR_PHYSBASEn and IA32_MTRR_PHYSMASKn Variable-Range Register Pair . . . . . . . . . . . . . . . . . . . . . . . . 12-25
Figure 12-8. IA32_SMRR_PHYSBASE and IA32_SMRR_PHYSMASK SMRR Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
Figure 12-9. IA32_PAT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
Figure 13-1. Mapping of MMX Registers to Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Figure 13-2. Mapping of MMX Registers to x87 FPU Data Register Stack  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 13-5
Figure 15-1. IA32_MPERF MSR and IA32_APERF MSR for P-state Coordination  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
Figure 15-2. IA32_PERF_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Figure 15-3. IA32_ENERGY_PERF_BIAS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
Figure 15-4. IA32_PM_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
Figure 15-5. IA32_HWP_CAPABILITIES  Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Figure 15-6. IA32_HWP_REQU EST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Figure 15-7. IA32_HWP_REQU EST_PKG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
Figure 15-8. IA32_HWP_PECI_REQUEST_INFO MSR.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11

Figure 15-9. IA32_HWP_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Figure 15-10. IA32_THERM_STATUS Register With HWP Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Figure 15-11. MSR_PPERF MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Figure 15-12. IA32_HWP_INTERRUPT MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
Figure 15-13. FAST_UNCORE_MSRS_CAPABILITY MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
Figure 15-14. FAST_UNCORE_MSRS_CTL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
Figure 15-15. FAST_UNCORE_MSRS_STATUS MSR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
Figure 15-16. IA32_PKG_HDC_CTL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
Figure 15-17. IA32_PM_CTL1 MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
Figure 15-18. IA32_THREAD_STALL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
Figure 15-19. MSR_CORE_HDC_RESIDENCY MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
Figure 15-20. MSR_PKG_HDC_SHALLOW_RESIDENCY MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 15-23
Figure 15-21. MSR_PKG_HDC_DEEP_RESIDENCY MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
Figure 15-22. MSR_PKG_HDC_CONFIG MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
Figure 15-23. Example of Effective Frequency Reduction and Forced Idle Period of HDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25
Figure 15-24. Processor Modulation Through Stop-Clock Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 15-36
Figure 15-25. MSR_THERM2_CTL Register On Processors with CPUID Family/Model/Stepping Signature Encoded as 0x69n or 
0x6Dn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
Figure 15-26. MSR_THERM2_CTL Register for Supporting TM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
Figure 15-27. IA32_THERM_STATUS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39
Figure 15-28. IA32_THERM_INTERRUPT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39
Figure 15-29. IA32_CLOCK_MODULATION MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40
Figure 15-30. IA32_CLOCK_MODULATION MSR with Clock Modulation Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41
Figure 15-31. IA32_THERM_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-42
Figure 15-32. IA32_THERM_INTERRUPT Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-44
Figure 15-33. IA32_PACKAGE_THERM_STATUS Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 15-45
Figure 15-34. IA32_PACKAGE_THERM_INTERRUPT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 15-47
Figure 15-35. MSR_RAPL_POWER_UNIT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49
Figure 15-36. MSR_PKG_POWER_LIMIT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50
Figure 15-37. MSR_PKG_ENERGY_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-51
Figure 15-38. MSR_PKG_POWER_INFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-51
Figure 15-39. MSR_PKG_PERF_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52
Figure 15-40. MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52
Figure 15-41. MSR_PP0_ENERGY_STATUS /MSR_PP1_ENERGY_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 15-53
Figure 15-42. MSR_PP0_POLICY/MSR_ PP1_POLICY Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-53
Figure 15-43. MSR_PP0_PERF_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54
Figure 15-44. MSR_DRAM_POWER_LIMIT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54
Figure 15-45. MSR_DRAM_ENERGY_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-55
Figure 15-46. MSR_DRAM_POWER_INFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-55
Figure 15-47. MSR_DRAM_PERF_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-55
Figure 16-1. Machine-Check MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
Figure 16-2. IA32_MCG_CAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Figure 16-3. IA32_MCG_STATUS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
Figure 16-4. IA32_MCG_EXT_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Figure 16-5. IA32_MCi_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Figure 16-6. IA32_MCi_STATUS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7

Figure 16-7. IA32_MCi_ADDR MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
Figure 16-8. UCR Support in IA32_MCi_MISC Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Figure 16-9. IA32_MCi_CTL2 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
Figure 16-10. CMCI Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
Figure 18-1. Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Figure 18-2. DR6/DR7 Layout on Processors Supporting Intel® 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8CONTENTS
xlVol. 3APAGE
Figure 18-3. IA32_DEBUGCTL MSR for Pr ocessors Based on Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13
Figure 18-4. 64-bit Address Layout of LBR MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18
Figure 18-5. DS Save Area Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
Figure 18-6. 32-bit Branch Trace Record Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22
Figure 18-7. PEBS Record Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22
Figure 18-8. IA-32e Mode DS Save Area Example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23
Figure 18-9. 64-bit Branch Trace Record Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23
Figure 18-10. 64-bit PEBS Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24
Figure 18-11. IA32_DEBUGCTL MSR for Processors Based on Nehalem Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 18-30
Figure 18-12. MSR_DEBUGCTLA MSR for Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36
Figure 18-13. LBR MSR Branch Record Layout for the Pentium 4 and Intel® Xeon® Processor Family . . . . . . . . . . . . . . . . .  . . . . . . . . 18-37
Figure 18-14. IA32_DEBUGCTL MSR for Intel® Core™ Solo and Intel® Core™ Duo Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-38
Figure 18-15. LBR Branch Record Layout  for the Intel® Core™ Solo and Intel® Core™ Duo Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39
Figure 18-16. MSR_DEBUGCTLB MSR for Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 18-40
Figure 18-17. LBR Branch Record Layout for the Pentium M Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-40
Figure 18-18. DEBUGCTLMSR Register (P6 Family Processors). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 18-41
Figure 18-19. Platform Shared Resource Monitoring Usage Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46
Figure 18-20. CPUID.(EAX=0FH, ECX=0H) Monitoring Resource Type Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47
Figure 18-21. L3 Cache Monitoring Capability Enumeration Data (CPUID.(EAX=0FH, ECX=1H) ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47
Figure 18-22. L3 Cache Monitoring Capability Enumeration Event Type Bit Vector (CPUID.(EAX=0FH, ECX=1H) ). . . . . . . . . . . .  . . 18-48
Figure 18-23. IA32_PQR_ASSOC MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49
Figure 18-24. IA32_QM_EVTSEL and IA32_QM_CTR MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 18-51
Figure 18-25. Software Usage of Cache Monitoring Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51
Figure 18-26. Cache Allocation Technology Enables Allocation of More Resources to High Priority Applications. . . . . . . . . . . . . . . 18-53
Figure 18-27. Examples of Cache Capacity Bitmasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54
Figure 18-28. Class of Service and Cache Capacity Bitmasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-55
Figure 18-29. Code and Data Capacity Bitmasks of CDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56
Figure 18-30. Cache Allocation Technology Usage Flow  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-57
Figure 18-31. CPUID.(EAX=10H, ECX=0H) Available Resource Type Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-58
Figure 18-32. L3 Cache Allocation Technology and CDP Enumeration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-59
Figure 18-33. L2 Cache Allocation Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-60
Figure 18-34. IA32_PQR_ASSOC, IA32_L3_MASK_n MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 18-61
Figure 18-35. IA32_L2_MASK_n MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61
Figure 18-36. Layout of IA32_L3_QOS_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-62
Figure 18-37. Layout of IA32_L2_QOS_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-63
Figure 18-38. CPUID.(EAX=10H, ECX=3H) MBA Feature Details Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-67
Figure 18-39. IA32_L2_QoS_Ext_BW_Thrtl_n MSR Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 18-68
Figure 18-40. Layout of the IA32_L3_IO_QOS_CFG MSR for Enabling Non-CPU Agent Intel® RDT  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 18-70
Figure 20-1. Layout of IA32_PERFEVTSELx MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
Figure 20-2. Layout of IA32_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
Figure 20-3. Layout of IA32_PERF_GLOBAL_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
Figure 20-4. Layout of IA32_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
Figure 20-5. Layout of IA32_PERF_GLOBAL_OVF_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10

Figure 20-6. Layout of IA32_PERFEVTSELx MSRs Supporting Architectural Performance Monitoring Version 3 . . . . . . . . . . . . . 20-11
Figure 20-7. IA32_FIXED_CTR_CTRL MSR Supporting Architectural Performance Monitoring Version 3 . . . . . . . . . . . . . . . . . . . . . 20-11
Figure 20-8. Layout of Global Performance Monitoring Control MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
Figure 20-9. Global Performance Monitoring Overflow Status and Control MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 20-12
Figure 20-10. IA32_PERF_GLOBAL_STATUS MSR and Architectural Perfmon Version 4 . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 20-14
Figure 20-11. IA32_PERF_GLOBAL_STATUS_RESET MSR and Architectural Perfmon Version 4  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15
Figure 20-12. IA32_PERF_GLOBAL_STATUS_SET MSR and Architectural Perfmon Version 4 . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 20-15
Figure 20-13. IA32_PERF_GLOBAL_INUSE MSR and Architectural Perfmon Version 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16
Figure 20-14. IA32_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18
Figure 20-15. Layout of IA32_PEBS_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19
Figure 20-16. PEBS Programming Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21
Figure 20-17. Layout of MSR_PEBS_LD_LAT MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24
Figure 20-18. Layout of MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 to Configure Off-core Response Events. . . . . . . . . . 20-25
Figure 20-19. Layout of MSR_UNCORE_PERF_GLOBAL_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 20-27
Figure 20-20. Layout of MSR_UNCORE_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 20-28
Figure 20-21. Layout of MSR_UNCORE_PERF_GLOBAL_OVF_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 20-28
Figure 20-22. Layout of MSR_UNCORE_PERFEVTSELx MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29
Figure 20-23. Layout of MSR_UNCORE_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29
Figure 20-24. Layout of MSR_UNCORE_ADDR_OPCODE_MATCH MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 20-30
Figure 20-25. Distributed Units of the Uncore of Intel® Xeon® Processor 7500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31
Figure 20-26. IA32_PERF_GLOBAL_CTRL MSR in Sandy Bridge Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 20-34
Figure 20-27. IA32_PERF_GLOBAL_STATUS MSR in Sandy Bridge Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 20-35Vol. 3A xliCONTENTS
PAGE
Figure 20-28. IA32_PERF_GLOBAL_OVF_CTRL MSR in Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-36
Figure 20-29. Layout of IA32_PEBS_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-38
Figure 20-30. Request_Type Fields for MSR_OFFCORE_RSP_x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-42
Figure 20-31. Response_Supplier and Snoop Info Fields for MSR_OFFCORE_RSP_x . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 20-43
Figure 20-32. Layout of Uncore PERFEVTSEL MSR for a C-Box Unit or the ARB Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-44
Figure 20-33. Layout of MSR_UNC_PERF_GLOBAL_CTRL MSR for Uncore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 20-45
Figure 20-34. Layout of IA32_PERFEVTSELx MSRs Supporting Intel TSX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-54
Figure 20-35. IA32_PERF_GLOBAL_STATUS MSR in Broadwell Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-56
Figure 20-36. IA32_PERF_GLOBAL_OVF_CTRL MSR in Broadwell microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 20-56
Figure 20-37. MSR_PERF_METRICS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-69
Figure 20-38. PERF_METRICS MSR Definition for 12th Generation Intel® Core™ Processor P-core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-71
Figure 20-39. Deducing Implied Level 2 Metrics in the Core PMU fo r12th Generation Intel® Core™ Processor P-core. . . . . . . . .  . . 20-72
Figure 20-40. Request_Type Fields for MSR_OFFCORE_RSPx  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 20-83
Figure 20-41. Response_Supplier and Snoop Info Fields for MSR_OFFCORE_RSPx . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 20-84
Figure 20-42. IA32_PEBS_ENABLE MSR with PEBS Output to Intel® Processor Trace  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-93
Figure 20-43. Layout of IA32_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-99
Figure 20-44. Layout of MSR_PERF_GLOBAL_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-100
Figure 20-45. Layout of MSR_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 20-100
Figure 20-46. Layout of MSR_PERF_GLOBAL_OVF_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-101
Figure 20-47. Event Selection Control Register (ESCR) for Pentium 4 and Intel® Xeon® Processors without Intel HT Technology 
Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-107
Figure 20-48. Performance Counter (Pentium 4 and Intel® Xeon® Processors)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-109
Figure 20-49. Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 20-110
Figure 20-50. Effects of Edge Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-113
Figure 20-51. Event Selection Control Register (ESCR) for the Pe ntium 4 Processor, Intel® Xeon ® Processor, and Intel® Xeon® 
Processor MP Supporting Hyper-Threading Technology  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-121
Figure 20-52. Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 20-122
Figure 20-53. Block Diagram of 64-bit Intel® Xeon® Processor MP with 8-MByte L3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-125
Figure 20-54. MSR_IFSB_IBUSQx, Addresses: 107CCH and 107CDH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 20-126
Figure 20-55. MSR_IFSB_ISNPQx, Addresses: 107CEH and 107CFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 20-126

Figure 20-56. MSR_EFSB_DRDYx, Addresses: 107D0H and 107D1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-127
Figure 20-57. MSR_IFSB_CTL6, Address: 107D2H; MSR_IFSB_CNTR7, Address: 107D3H. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 20-127
Figure 20-58. Block Diagram of the Intel® Xeon® Processor 7400 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 20-128
Figure 20-59. Block Diagram of the Intel® Xeon® Processor 7100 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 20-129
Figure 20-60. MSR_EMON_L3_CTR_CTL0/1, Addresses: 107CCH/107CDH  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 20-130
Figure 20-61. MSR_EMON_L3_CTR_CTL2/3, Addresses: 107CEH/107CFH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-132
Figure 20-62. MSR_EMON_L3_CTR_CTL4/5/6/7, A ddresses: 107D0H-107D3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-132
Figure 20-63. PerfEvtSel0 and PerfEvtSel1 MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-134
Figure 20-64. CESR MSR (Pentium Processor Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-137
Figure 20-65. Layout of IA32_PERF_CAPABILITIES MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-142
Figure 20-66. Layout of IA32_PEBS_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-143
Figure 20-67. PEBS Programming Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-144
Figure 20-68. Layout of IA32_PerfEvtSelX MSR Supporting Adaptive PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-145
Figure 20-69. Layout of IA32_FIXED_CTR_CTRL MSR Supporting Adaptive PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-146
Figure 20-70. MSR_PEBS_DATA_CFG  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-150
Figure 21-1. Real-Address Mode Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Figure 21-2. Interrupt Vector Table in Real-Address Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
Figure 21-3. Entering and Leaving Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
Figure 21-4. Privilege Level 0 Stack After Interrupt or Exception in Virtual-8086 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
Figure 21-5. Software Interrupt Redirection Bit Map in TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
Figure 22-1. Stack after Far 16- and 32-Bit Calls  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
Figure 23-1. I/O Map Base Address Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-30
Figure 24-1. Interaction of a Virtual-Machine Monitor and Guests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
Figure 25-1. States of VMCS X  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
Figure 29-1. Formats of EPTP and EPT Paging-Structure Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
Figure 31-1. INVEPT Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
Figure 31-2. INVVPID Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6
Figure 32-1. SMRAM Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
Figure 32-2. SMM Revision Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-13
Figure 32-3. Auto HALT Restart Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-14
Figure 32-4. SMBASE Relocation Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15
Figure 32-5. I/O Instruction Restart Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15
Figure 33-1. ToPA Memory Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-11
Figure 33-2. Layout of ToPA Table Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12
Figure 33-3. Interpreting Tabular Definition of Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 33-38CONTENTS
xlii Vol. 3APAGE
Figure 34-1. An Enclave Within the Application’s Virtual Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 34-1
Figure 36-1. Enclave Memory Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1
Figure 36-2. Measurement Flow of Enclave Build Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
Figure 36-3.  SGX Local Attestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9
Figure 37-1. Exit Stack Just After Interrupt with Stack Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1
Figure 37-2. The SSA Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2
Figure 38-1. Relationships Between SECS, SIGSTRUCT, and EINITTOKEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-47
Figure 40-1. Single Stepping with Opt-out Entry - No AEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2
Figure 40-2. Single Stepping with Opt-out Entry -AEX Due to Non-SMI Event Before Single-Step Boundary . . . . . . . . . . . . . . . . . . 40-3
Figure 40-3. LBR Stack Interaction with Opt-in Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-6
Figure 40-4. LBR Stack Interaction with Opt-out Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7Vol. 3A xliiiCONTENTS
PAGE
TABLES
Table 2-1. IA32_EFER MSR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

PAGE
TABLES
Table 2-2. Action Taken By x87 FPU Instructions for Different Combinations of EM, MP, and TS  . . . . . . . . . . . . . . . . . .  . . . . . . . . 2-16
Table 2-3. Summary of System Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Table 3-1. Code- and Data-Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Table 3-2. System-Segment and Gate-Descriptor Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Table 4-1. Properties of Different Paging Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Table 4-2.  Paging Structures in the Different Paging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
Table 4-3. Use of CR3 with 32-Bit Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Table 4-4. Format of a 32-Bit Page-Directory Entry that Maps a 4-MByte Page  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Table 4-6. Format of a 32-Bit Page-Table Entry that Maps a 4-KByte Page  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Table 4-5. Format of a 32-Bit Page-Directory Entry that References a Page Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Table 4-7. Use of CR3 with PAE Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Table 4-8. Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Table 4-9. Format of a PAE Page-Directory Entry that Maps a 2-MByte Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Table 4-10. Format of a PAE Page-Directory Entry that References a Page Table  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Table 4-11. Format of a PAE Page-Table Entry that Maps a 4-KByte Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 4-18
Table 4-12. Use of CR3 with 4-Level Paging and 5-level Paging and CR4.PCIDE = 0 . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 4-20
Table 4-13. Use of CR3 with 4-Level Paging and 5-Level Paging and CR4.PCIDE = 1  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 4-21
Table 4-14. Format of a PML5 Entry (PML5E) that References a PML4 Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 4-26
Table 4-15. Format of a PML4 Entry (PML4E) that References a Page-Directory-Pointer Table . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 4-26
Table 4-16. Format of a Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page . . . . . . . . . . . . . . . . . . .  . . . . . . . . 4-27
Table 4-17. Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory . . . . . . . . . . . . . . .  . . . . . 4-28
Table 4-18. Format of a Page-Directory Entry that Maps a 2-MByte Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 4-29
Table 4-19. Format of a Page-Directory Entry that References a Page Table . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 4-30
Table 4-20. Format of a Page-Table Entry that Maps a 4-KByte Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 4-31
Table 5-1. Privilege Check Rules for Call Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Table 5-2. 64-Bit-Mode Stack Layout After Far CALL with CPL Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Table 5-3. Combined Page-Directory and Page-Table Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Table 5-4. Extended Feature Enable MSR (IA32_EFER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Table 5-6. 4-KByte Page Level Protection Matrix with Execute-Disable Bit Capability with PAE Paging . . . . . . . . . . . . . . . . . . . . 5-31
Table 5-7. 2-MByte Page Level Protection with Execute-Disable Bit Capability with PAE Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Table 5-5. Page Level Protection Matrix with Execute-Disable Bit Capability with 4-Level Paging  . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Table 5-9. Reserved Bit Checking with Execute-Disable Bit Capability Not Enabled  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-32
Table 5-8. Page Level Protection Matrix with Execute-Disable Bit Capability Enabled . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 5-32
Table 6-1. Protected-Mode Exceptions and Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
Table 6-2. Priority Among Concurrent Events  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
Table 6-3. Debug Exception Conditions and Corresponding Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Table 6-4. Interrupt and Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
Table 6-5. Conditions for Generating a Double Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
Table 6-6. Invalid TSS Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
Table 6-7. Alignment Requirements by Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
Table 6-8. SIMD Floating-Point Exceptions Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
Table 7-1. Format of User Posted-Interrupt Descriptor — UPID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
Table 8-1. Exception Conditions Checked During a Task Switch  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Table 8-2. Effect of a Task Switch on Busy Flag, NT Flag, Previous Task Link Field, and TS Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Table 9-1. Broadcast INIT-SIPI-SIPI Sequence and Choice of Timeouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 9-23
Table 9-2. Initial APIC IDs for the Logical Processors in a System that has Four In tel Xeon MP Processo rs Supporting Intel 
Hyper-Threading Technology1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
Table 9-3. Initial APIC IDs for the Logical Processors in a System that has Two Phys ical Processors Supporting Dual-Core and 
Intel Hyper-Threading Technology  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
Table 9-4. Example of Possible x2APIC ID Assignment in a Syst em that has Two Physical Processors Supporting x2APIC and 

Table 9-5. Boot Phase IPI Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55
Table 10-1. IA-32 and Intel® 64 Processor States Following Power-up, Reset, or INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Table 10-2. Variance of RESET Values in Selected Intel Architecture Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Table 10-3. Recommended Settings of EM and MP Flags on IA-32 Pr ocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Table 10-4. Software Emulation Settings of EM, MP, and NE Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Table 10-5. Main Initialization Steps in STARTUP.ASM Source Listing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
Table 10-6. Relationship Between BLD Item and ASM Source File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 10-27
Table 10-7. Microcode Update Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
Table 10-8. Microcode Update Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
Table 10-9. Extended Processor Signature Table Header Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 10-31CONTENTS
xliv Vol. 3APAGE
Table 10-10. Processor Signature Structure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-31
Table 10-11. Processor Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-33
Table 10-12. Microcode Update Signature  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-37
Table 10-13. Microcode Update Functions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-42
Table 10-14. Parameters for the Presence Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-42
Table 10-15. Parameters for the Write Update Data Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-43
Table 10-16. Parameters for the Control Update Sub-function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47
Table 10-17. Mnemonic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47
Table 10-18. Parameters for the Read Microcode Update Data Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .10-47
Table 10-19. Return Code Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-49
Table 11-1. Local APIC Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Table 11-2. Local APIC Timer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17
Table 11-3. Valid Combinations for Pentium 4 and Intel Xeon Proc essors Local xAPIC Interrupt Command Register . . . . . . . . .11 -21
Table 11-4. Valid Combinations for the P6 Family Processor Local APIC Interrupt Command Register . . . . . . . . . . . . . . . .  . . . . . .11-22
Table 11-5. x2APIC Operating Mode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-37
Table 11-6. Local APIC Register Address Map Supported by x2APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .11-38
Table 11-7. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .11-40
Table 11-8. EOI Message (14 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-47
Table 11-9. Short Message (21 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-48
Table 11-10. Non-Focused Lowest Priority Message (34 Cycles)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .11-49
Table 11-11. APIC Bus Status Cycles Interpretation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-51
Table 12-1. Characteristics of the Caches, TLBs, Store Buffer, and Write Combining Buffer in Intel 64 and IA-32 Processors . 12-2Table 12-2. Memory Types and Their Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Table 12-3. Methods of Caching Available in Intel Core 2 Duo, Intel Atom, Intel Core Du o, Pentium M, Pentium 4, Intel Xeon, P6 
Family, and Pentium Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Table 12-4. MESI Cache Line States  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
Table 12-5. Cache Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-12
Table 12-6. Effective Page-Level Memory Type for Pentium Pro and Pentium II Processors . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .12-14
Table 12-7. Effective Page-Level Memory Types for Pentium III and More Recent Processor Families . . . . . . . . . . . . . . . . . . . . . .12-15
Table 12-8. Memory Types That Can Be Encoded in MTRRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .12-21
Table 12-9. Address Mapping for Fixed-Range MTRRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .12-24
Table 12-10. Memory Types That Can Be Encoded With PAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-34
Table 12-11. Selection of PAT Entries with PAT, PCD, and PWT Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-35
Table 12-12. Memory Type Setting of PAT Entries Following a Power-up or Reset . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .12-35
Table 13-1. Action Taken By MMX Instructions for Different Combinations of EM, MP, and TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Table 13-3. Effect of the MMX, x87 FPU, and FXSAVE/FXRSTOR Instructions on the x87 FPU Tag Word. . . . . . . . . . . . . . . . .  . . . 13-3
Table 13-2. Effects of MMX Instructions on x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Table 14-1. Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE, SSE2, SSE3, EM, MP, and TS. . . . . . . . . . . . . . . . . . . . 14-3
Table 14-2. Action Taken for Combinations of OSFXSR, SSSE3, SSE4, EM, and TS . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 14-4

Table 14-3.  CPUID.(EAX=0DH, ECX=1) EAX Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Table 15-1. Architectural and Non-Architectural MSRs Related to HWP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 15-6
Table 15-2. IA32_HWP_CTL MSR Bit 0 Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-13
Table 15-3. Architectural and non-Architecture MSRs Related to HDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-21
Table 15-4. Hardware Feedback Interface Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-25
Table 15-5. Hardware Feedback Interface Global Header Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-26
Table 15-6. Hardware Feedback Interface Logical Processor Entry Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .15-26
Table 15-7. Intel® Thread Director Table Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-27
Table 15-8. Intel® Thread Director Global Header Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-28
Table 15-9. Intel® Thread Director Logical Processor Entry Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-29
Table 15-10.  IA32_HW_FEEDBACK_CONFIG Control Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 . . . . . . . . . . . . . . . . . . . . . . . .15-32
Table 15-11. On-Demand Clock Modulation Duty Cycle Field Encoding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-40
Table 15-12. RAPL MSR Interfaces and RAPL Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-50
Table 16-1. Bits 54:53 in IA32_MCi_STATUS MSRs when IA32_MCG_CAP [11] = 1 and UC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
Table 16-2. Overwrite Rules for Enabled Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
Table 16-3. Address Mode in IA32_MCi_MISC[8:6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-10
Table 16-4. Address Mode in IA32_MCi_MISC[8:6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-11
Table 16-5. Extended Machine Check State MSRs in Processors Without Support for Intel® 64 Architecture . . . . . . . . . . . . . . . .16-12
Table 16-6. Extended Machine Check State MSRs In Processors With Support for Intel® 64 Architecture . . . . . . . . . . . . . . . . . . .16-12
Table 16-7. MC Error Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-18
Table 16-8. Overwrite Rules for UC, CE, and UCR Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-18
Table 16-9. IA32_MCi_Status [15:0] Simple Error Code Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .16-21
Table 16-10. IA32_MCi_Status [15:0] Compound Error Code Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-21
Table 16-11. Encoding for TT (Transaction Type) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-22
Table 16-12. Level Encoding for LL (Memory Hierarchy Level) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .16-22
Table 16-13. Encoding of Request (RRRR) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-23Vol. 3A xlvCONTENTS
PAGE
Table 16-14. Encodings of PP, T, and II Sub-Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
Table 16-15. Encodings of MMM and CCCC Sub-Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
Table 16-16. MCA Compound Error Code Encoding for SRAO Errors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
Table 16-17. IA32_MCi_STATUS Values for SRAO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
Table 16-18. IA32_MCG_STATUS Flag Indication for SRAO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
Table 16-19. MCA Compound Error Code Encoding for SRAR Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 16-25
Table 16-20. IA32_MCi_STATUS Values for SRAR Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
Table 16-21. IA32_MCG_STATUS Flag Indication for SRAR Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
Table 17-1.  CPUID DisplayFamily_Di splayModel Signatures for Processor Family 06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
Table 17-2. Incremental Decoding Information: Processor Family 06H Machine Error Codes for Machine Check . . . . . . . . . . . . . . 17-1
Table 17-3.  CPUID DisplayFamily_Di splayModel Signatures for Processors Based on Intel® Core™ Microarchitecture . . . . . . . . .  17-3
Table 17-4. Incremental Bus Error Codes of Machine Check for Proc essors Based on Intel® Core™ Microarchitecture . . . . . . . . . 17-4
Table 17-5. Incremental MCA Error Code Types for Intel® Xeon® Processor 7400 . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 17-6
Table 17-6. Type B: Bus and Interconnect Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Table 17-7. Type C: Cache Bus Controller Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
Table 17-8. Intel® QPI Machine Check Error Cod es for IA32_MC0_STATUS and IA32_MC1_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
Table 17-9. Intel® QPI Machine Check Error Cod es for IA32_MC0_MISC and IA32_MC1_MISC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
Table 17-10. Machine Check Error Codes for IA32_MC7_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 17-9
Table 17-11. Incremental Memory Controller E rror Codes of Machine Check for IA32_MC8_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
Table 17-12. Incremental Memory Controller E rror Codes of Machine Check for IA32_MC8_MISC. . . . . . . . . . . . . . . . . . . .  . . . . . . . . 17-10
Table 17-13. Machine Check Error Codes for IA32_MC4_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-10
Table 17-14. Intel® QPI MC Error Codes for IA32_MC6_STATUS and IA32_MC7_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 17-11
Table 17-15. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 8, 11)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 17-12
Table 17-16. Intel IMC MC Error Codes for IA32_MCi_MISC (i= 8, 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
Table 17-17. Machine Check Error Codes for IA32_MC4_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-13

Table 17-18. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9—16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 17-14
Table 17-19. Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9—16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-15
Table 17-20. Machine Check Error Codes for IA32_MC4_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-16
Table 17-21. Intel® QPI MC Error Codes for IA32_MCi_STATUS (i = 5, 20, 21)  . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 17-17
Table 17-22. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9—16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 17-18
Table 17-23. Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9—16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-18
Table 17-24. Machine Check Error Codes for IA32_MC4_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-19
Table 17-25. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9—10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 17-20
Table 17-26. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9—16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 17-21
Table 17-27. Intel HA MC Error Codes for IA32_MCi_MISC (i= 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
Table 17-28. Machine Check Error Codes for IA32_MC4_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-22
Table 17-29. Interconnect MC Error Codes for IA32_MCi_STATUS (i = 5, 12, 19) . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 17-24
Table 17-30. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 13—1 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 17-26
Table 17-31. M2M MC Error Codes for IA32_MCi_STATUS (i= 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27
Table 17-32. Intel HA MC Error Codes for IA32_MCi_MISC (i= 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27
Table 17-33. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-28
Table 17-34. Machine Check Error Codes for IA32_MC4_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-29
Table 17-35. Interconnect MC Error Codes for IA32_MCi_STATUS (i = 5, 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31
Table 17-36. MSRs Reporting MC Error Codes by CPUID DisplayFamily_DisplaySignature . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 17-32
Table 17-37. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 13—1 4, 17—18, 21—22, 25—26). . . . . . . . . . . . . . . . . . . .  . . . . . 17-33
Table 17-38. Additional Information Reported in IA32_MCi_MISC (i= 13—14, 17—18, 21—22, 25—26)  . . . . . . . . . . . . . . . . . . . . . 17-35
Table 17-39. M2M MC Error Codes for IA32_MCi _STATUS (i= 12, 16, 20, 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36
Table 17-40. Machine Check Error Codes for IA32_MC4_STATUS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 17-37
Table 17-41. Interconnect MC Error Codes for IA32_MC5_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40
Table 17-42. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 13—2 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 17-41
Table 17-43. Additional Information Reported in IA32_MCi_MISC (i= 13—20) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 17-43
Table 17-44. M2M MC Error Codes for IA32_MC1 2_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 17-44
Table 17-45. Incremental Decoding Information: Processor Family 0FH, Machine Error Codes for Machine Check. . . . . . . . . . . . . 17-45
Table 17-46. MCi_STATUS Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-46
Table 17-47. Incremental MCA Error Code for Intel® Xeon® Processor MP 7100 . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 17-47
Table 17-48. Other Information Field Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-47
Table 17-49. Type A: L3 Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48
Table 17-50. Type B: Bus and Interconnect Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48
Table 17-51. Type C: Cache Bus Controller Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-49
Table 17-52. Decoding Family 0FH Machine Check Codes for Cache Hierarchy Errors . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 17-50
Table 18-1. Breakpoint Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
Table 18-2. Debug Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
Table 18-4.  LBR Stack Size and TOS Pointer Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17
Table 18-3.  Legacy and Streamlined Operation with Freeze_Perfmon _On_PMI = 1, Counter Overflowed . . . . . . . . . . . . . . . .  . . 18-17
Table 18-5.  IA32_DEBUGCTL Flag Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25CONTENTS
xlvi Vol. 3APAGE
Table 18-6. CPL-Qualified Branch Trace Store Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .18-26
Table 18-7.  MSR_LASTBRANCH_x_TO_IP for the Goldmont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-28
Table 18-8.  MSR_LASTBRANCH_x_FRO M_IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-30
Table 18-9.  MSR_LASTBRANCH_x_TO_IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-31
Table 18-10. LBR Stack Size and TOS Pointer Range  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-31
Table 18-11.  MSR_LBR_SELECT for Nehalem Microarchitecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .18-31
Table 18-12.  MSR_LBR_SELECT for Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-32
Table 18-13.  MSR_LBR_SELECT for Haswell Mi croarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .18-32
Table 18-14.  MSR_LASTBRANCH_x_FROM_IP with  TSX Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .18-33
Table 18-15. LBR Stack Size and TOS Pointer Range  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-34

Table 18-16.  MSR_LBR_INFO_x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-34
Table 18-17. LBR MSR Stack Size and TOS Pointer Range for the Pent ium® 4 and the Intel® Xeon® Processor Family . . . . . . . . .18-3 7
Table 18-18. Monitoring Supported Event IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-49
Table 18-19. Re-indexing of COS Numbers and Mapping to CAT/CDP Mask MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-63
Table 18-20. MBA Delay Value MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-68
Table 19-1. LBR IP Values for Various Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Table 19-2. Branch Type Filtering Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
Table 19-3. IA32_LBR_x_INFO and IA32_LER_INFO Branch Type Encodi ngs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 19-4
Table 19-4. LBR VMCS Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
Table 20-1. UMask and Event Select Encodings for Pre-Defined Architectural Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
Table 20-2. Association of Fixed-Function Performance Counters with Architectural Performance Events  . . . . . . . . . . . . . .  . . . . 20-9
Table 20-3. PEBS Record Format for Intel Core i7 Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .20-20
Table 20-4. Data Source Encoding for Load Latency Record  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .20-23
Table 20-5. Off-Core Response Event Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-24
Table 20-6. MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 Bit Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-25
Table 20-7. Opcode Field Encoding for MSR_UNCORE_ADDR_OPCODE_MATC H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .20-30
Table 20-8. Uncore PMU MSR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-32
Table 20-9. Uncore PMU MSR Summary for Intel® Xeon® Processor E7 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .20-33
Table 20-10. Core PMU Comparison  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-34
Table 20-11. PEBS Facility Comparison  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-37
Table 20-12. PEBS Performance Even ts for Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .20-38
Table 20-13. Layout of Data Source Field of Load Latency Record  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-40
Table 20-15. Off-Core Response Event Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-41
Table 20-14. Layout of Precise Store Information In PEBS Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .20-41
Table 20-16. MSR_OFFCORE_RSP_x Request_Type Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-42
Table 20-17. MSR_OFFCORE_RSP_x Response Supplier Info Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-43
Table 20-18. MSR_OFFCORE_RSP_x Snoop Info Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-44
Table 20-19. Uncore PMU MSR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-45
Table 20-20. MSR_OFFCORE_RSP_x Supplier Info Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-46
Table 20-21. Uncore PMU MSR Summary for Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-47
Table 20-22. Core PMU Comparison  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-48
Table 20-23. PEBS Facility Comparison  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-48
Table 20-24. PEBS Record Format for 4th Generation Intel Core Processor Family . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .20-49
Table 20-25. Precise Events That Supports Data Linear Address Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-50
Table 20-26. Layout of Data Linear Address Information In PEBS Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-51
Table 20-27. MSR_OFFCORE_RSP_x Request_Type Definition (Haswell Microarchitecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-51
Table 20-28. MSR_OFFCORE_RSP_x Supplier Info Field Definition (C PUID Signatures: 06_3CH, 06_46H) . . . . . . . . . . . . . . . .  . . . .20-52
Table 20-29. MSR_OFFCORE_RSP_x Supplier Info Field Definition (C PUID Signature: 06_45H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-52
Table 20-30. MSR_OFFCORE_RSP_x Supplier Info Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .20-53
Table 20-31. TX Abort Information Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-55
Table 20-32. Uncore PMU MSR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-55
Table 20-33. Core PMU Comparison  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-57
Table 20-34. PEBS Facility Comparison  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-58
Table 20-35. PEBS Record Format for the 6th Generation, 7th Generation, and 8th Generation Intel Core Processor Families 20-59
Table 20-36.  Precise Events for the Skylake, Kaby Lake, and Coffee Lake Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-60
Table 20-37. Layout of Data Linear Address Information In PEBS Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-61
Table 20-38. FrontEnd_Retired Sub-Event Encodings Supported by MSR_PEBS_FRONTEND.EVTSEL . . . . . . . . . . . . . . . . . . . . .  . . .20-62
Table 20-39. MSR_PEBS_FRONTEND Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-62
Table 20-40. MSR_OFFCORE_RSP_x Request_Type Definition (Skylake, Kaby Lake, and Coffee Lake Microarchitectures)  . . . .20-63Table 20-41. MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signatures: 06_4EH, 06_5EH, 06_8EH, 06_9EH). . .20-63
Table 20-42. MSR_OFFCORE_RSP_x Snoop Info Field Definition (CPUID Signatures: 06_4EH, 06_5EH, 06_8EH, 06_9E,

Table 20-42. MSR_OFFCORE_RSP_x Snoop Info Field Definition (CPUID Signatures: 06_4EH, 06_5EH, 06_8EH, 06_9E, 
06_55H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-64
Table 20-44. MSR_OFFCORE_RSP_x Supplier Info Field Definition (C PUID Signature: 06_55H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-65
Table 20-43. MSR_OFFCORE_RSP_x Request_Type Definition (Intel® Xe on® Scalable Processor Family) . . . . . . . . . . . . . . . . . . . . .20-65
Table 20-45. MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signature: 06_55H, Steppings 0x5H - 0xFH). . . . . . .20-66Vol. 3A xlviiCONTENTS
PAGE
Table 20-47. MSR_OFFCORE_RSP_x Request_Type Definition (Processors Based on Ice Lake Microarchitecture) . . . . . . . . . . . . 20 -67
Table 20-46. Core PMU Summary of the Ice Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 20-67
Table 20-48. MSR_OFFCORE_RSP_x Supplier Info Field Definition (Processors Based on Ice Lake Microarchitecture). . . . . . . . . 20 -68
Table 20-49. MSR_OFFCORE_RSP_x Snoop Info Field Definition (Process ors Based on Ice Lake Microarchitecture). . . . . . . . . . . 2 0-69
Table 20-50. Core PMU Summary of the Golden Cove Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-71
Table 20-51. Special Performance Monitoring Events with Counter Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 20-72
Table 20-52. Core PMU Summary of the Gracemont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 20-73
Table 20-53. E-core PEBS Memory Access Info Encoding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-73
Table 20-54. E-core PEBS Data Source Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-74
Table 20-55. MSR_OFFCORE_RSPx Request Type Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 20-75
Table 20-56. PEBS Performance Events for Knights Landing Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-77
Table 20-57. PEBS Record Format for Knights Landing Microarchitecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-77
Table 20-58. OffCore Response Event Encoding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-78
Table 20-59. Bit fields of the MSR_OFFCORE_RESP [0, 1] Register s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-78
Table 20-60. PEBS Performance Events for the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-81
Table 20-62. OffCore Response Event Encoding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-82
Table 20-61. PEBS Record Format for the Silvermont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-82
Table 20-63. MSR_OFFCORE_RSPx Request_Type Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 20-83
Table 20-64. MSR_OFFCORE_RSP_x Response Supplier Info Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-84
Table 20-65. MSR_OFFCORE_RSPx Snoop Info Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 20-84
Table 20-66. Core PMU Comparison Between the Goldmont and Silvermont Microarchitectures. . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 20-85
Table 20-67. Precise Events Supported by the Goldmont Microarchi tecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-87
Table 20-68. PEBS Record Format for the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-88
Table 20-69. MSR_OFFCORE_RSPx Request_Type Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 20-89
Table 20-70. MSR_OFFCORE_RSPx For L2 Miss and Outstanding Reques ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-90
Table 20-71. Core PMU Comparison Between the Goldmont Plus and Goldmont Microarchitectures . . . . . . . . . . . . . . . . . . .  . . . . . . 20-91
Table 20-72. Core PMU Comparison Between the Tremont and Goldmont Plus Microarchitectures . . . . . . . . . . . . . . . . . . . .  . . . . . . 20-92
Table 20-73. New Fields in IA32_PEBS_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-93
Table 20-74. MSR_OFFCORE_RSPx Request Type Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 20-94
Table 20-75. MSR_OFFCORE_RSPx Response Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 20-95
Table 20-76. MSR_OFFCORE_RSPx Snoop Info Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 20-95
Table 20-77. Core Specificity Encoding within a Non-Architectural Umask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-96
Table 20-78. Agent Specificity Encoding within a Non-Architectural Umask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-97
Table 20-79. HW Prefetch Qualification Encoding within a Non-Ar chitectural Umask . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 20-97
Table 20-80. MESI Qualification Definitions within a Non-Architec tural Umask . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 20-97
Table 20-81. Bus Snoop Qualification Definitions within a Non-Architectural Umask. . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 20-98
Table 20-82. Snoop Type Qualification Definitions within a Non-Ar chitectural Umask . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 20-98
Table 20-83. At-Retirement Performance Events for Intel Core Micr oarchitecture . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .20-101
Table 20-84. PEBS Performance Events for Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-102
Table 20-85. Requirements to Program PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-103
Table 20-86. Performance Counte r MSRs and Associated CCCR and ESCR MS Rs (Processors Based on Intel NetBurst 
Microarchitecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-104
Table 20-87. Event Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-111
Table 20-88. CCR Names and Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-115
Table 20-89. Effect of Logical Processor and CPL Qualification for Logical-Processor-Specific (TS) Events . . . . . . . . . . . .  . . . . . .20-123
Table 20-90. Effect of Logical Processor and CPL Qualification fo r Non-logical-Processor-specific (TI) Events. . . . . . . . . .  . . . . .20-124
Table 20-91. Nominal Core Crystal Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-140
Table 20-92. Basic Info Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-146

Table 20-93. Memory Access Info Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-147
Table 20-94. Updated Memory Access Info Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-148
Table 20-95. GPRs in Ice Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-149
Table 20-96. XMMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-149
Table 20-97. LBRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-150
Table 20-98. MSR_PEBS_CFG Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-151
Table 20-99. PEBS Record Example 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-151
Table 20-100. PEBS Record Example 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-152
Table 20-101. Data Source Encoding  for Memory Accesses (Ice Lake and Later Microarchitectures) . . . . . . . . . . . . . . . . . . . . . . . . .20-155
Table 21-1. Real-Address Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
Table 21-2. Software Interrupt Handling Methods While in Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 21-17
Table 22-1. Characteristics of 16-Bit and 32-Bit Program Modules .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
Table 23-1. New Instruction in the Pentium Processor and Later IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
Table 23-3. EM and MP Flag Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17
Table 23-2. Recommended Values of the EM, MP, and NE Flags for Intel486 SX Microprocessor/Intel 487 SX Math 
Coprocessor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17
Table 23-4. Exception Conditions for Legacy SIMD/MMX Instructions  with FP Exception and 16-Byte Alignment . . . . . . . . . . . 2 3-22CONTENTS
xlviii Vol. 3APAGE
Table 23-5. Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception . . . . . . . . . . . . . . . . . . . . . . . . .23-23
Table 23-6. Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception . . . . . . . . . . . . . . .  . .23-24
Table 23-7. Exception Conditions for SIMD/MMX Instructions with Memory Reference . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .23-25
Table 23-8. Exception Conditions for Legacy SIMD/MMX Instructions  without FP Exception . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .23-26
Table 23-9. Exception Conditions for Legacy SIMD/MMX Instructions  without Memory Reference  . . . . . . . . . . . . . . . . . . .  . . . . . .23-27
Table 23-10. Processor State Following Power-up/Reset/INIT for Pe ntium, Pentium Pro and Pentium 4 Processors. . . . . . . . . .2 3-37
Table 25-1. Format of the VMCS Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
Table 25-2. Format of Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
Table 25-3. Format of Interruptibility State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
Table 25-4. Format of Pending-Debug-Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
Table 25-5. Definitions of Pin-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-10
Table 25-6. Definitions of Primary Processor-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .25-10
Table 25-7. Definitions of Secondary Processor-Based VM-Execution Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-12
Table 25-8. Definitions of Tertiary Processor-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .25-13
Table 25-9. Format of Extended-Page-Table Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-17
Table 25-10. Definitions of VM-Function Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-18
Table 25-11. Format of Sub-Page-Permission-Table Pointer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .25-19
Table 25-12. Format of Hypervisor-Managed Linear-Address Translation Pointer . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .25-20
Table 25-13. Definitions of Primary VM-Exit Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-21
Table 25-14. Definitions of Secondary VM-Exit Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-22
Table 25-15. Format of an MSR Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-23
Table 25-16. Definitions of VM-Entry Controls  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-23
Table 25-17. Format of the VM-Entry Interruption-Information Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .25-25
Table 25-18. Format of Exit Reason . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-26
Table 25-19. Format of the VM-Exit Interruption-Information Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .25-27
Table 25-20. Format of the IDT-Vectoring Information Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .25-28
Table 25-21. Structure of VMCS Component Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-30
Table 26-1. Format of the Virtualization-Exception Information Area  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-21
Table 28-1. Exit Qualification for Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4
Table 28-2. Exit Qualification for Task Switches  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
Table 28-3. Exit Qualification for Control-Register Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7
Table 28-4. Exit Qualification for MOV DR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8

Table 28-5. Exit Qualification for I/O Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
Table 28-6. Exit Qualification for APIC-Access VM Exits from Linear Accesses and Guest-Physical Accesses . . . . . . . . . . . . .  . . . . 28-9
Table 28-7. Exit Qualification for EPT Violations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-10
Table 28-8. Format of the VM -Exit Instruction-Information Field as Used for INS and OUTS  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .28-16
Table 28-9. Format of the VM -Exit Instruction-Information Field as Used for INVEPT, INVPCID, and INVVPID . . . . . . . . . . . .  . . .28-17
Table 28-10. Format of the VM-Exit Instruct ion-Information Field as Used for LIDT, LGDT, SIDT, or SGDT. . . . . . . . . . . . . . . . . . . .28-18
Table 28-11. Format of the VM-Exit Instruction-Information Field as Used for LLDT, LTR, SLDT, and STR . . . . . . . . . . . . . .  . . . . . .28-19
Table 28-12. Format of the VM-Exit Instruction-Information Field as Used for RDRAND and RDSEED . . . . . . . . . . . . . . . . . . . . . . . .28-20
Table 28-13. Format of the VM-Exit Instruct ion-Information Field as Used for TPAUSE and UMWAIT . . . . . . . . . . . . . . . . . . . . . . . .28-20
Table 28-14. Format of the VM-Exit Inst ruction-Information Field as Used for VMCLEAR, VMPTRLD, VMPTRST, VMXON, 
XRSTORS, and XSAVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-21
Table 28-15. Format of the VM-Exit Instruct ion-Information Field as Used for VMREAD and VMWRITE . . . . . . . . . . . . . . . . . . . . . .28-22
Table 28-16. Format of the VM-Exit Instruction-Information Field as Used for LOADIWKEY . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .28-23
Table 29-1. Format of an EPT PML5 Entry (PML 5E) that References an EPT PML4 Table . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 29-4
Table 29-2. Format of an EPT PML4 Entry (PML 4E) that References an EPT Page-Directory-Pointer Table . . . . . . . . . . . . . . .  . . . 29-5
Table 29-3. Format of an EPT Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page. . . . . . . . . . . . . . . . . . . . . . 29-6
Table 29-4. Format of an EPT Page -Directory-Pointer-Tab le Entry (PDPTE) that References an EPT Page Directory . . . . . . . . . 29 -7
Table 29-5. Format of an EPT Page-Directory Entry (PDE) that Maps a 2-MByte Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8
Table 29-6. Format of an EPT Page-Directory Entry (PDE) that References an EPT Page Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9
Table 29-7. Format of an EPT Page-Table Entry that Maps a 4-KByte Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-11
Table 30-1. Format of Posted-Interrupt Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-15
Table 31-1. VM-Instruction Error Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-31
Table 32-1. SMRAM State Save Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
Table 32-2.  Processor Signatures and 64-bit SMRAM State Save Map Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 32-6
Table 32-3. SMRAM State Save Map for Intel 64 Architecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 32-7
Table 32-4. Processor Register Initialization in SMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9
Table 32-5. I/O Instruction Information in the SMM State Save Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-12
Table 32-6. I/O Instruction Type Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-12
Table 32-7. Auto HALT Restart Flag Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-14
Table 32-8. I/O Instruction Restart Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-16
Table 32-9. Exit Qualification for SMIs That Arrive Immediately After the Retirement of an I/O Instruction . . . . . . . . . . . . . . . . .32-21
Table 32-10. Format of MSEG Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32-25
Table 33-1. COFI Type for Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3Vol. 3A xlixCONTENTS
PAGE
Table 33-2. IP Filtering Packet Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7
Table 33-3. ToPA Table Entry Fields  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12
Table 33-4. Algorithm to Manage Intel PT ToPA PMI and XSAVES/XRSTORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-15
Table 33-5. Behavior on Restricted Memory Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-16
Table 33-6. IA32_RTIT_CTL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-17
Table 33-7. IA32_RTIT_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-21
Table 33-8. IA32_RTIT_OUTPUT_BASE MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-23
Table 33-10. TSX Packet Scenarios with BranchEn=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24
Table 33-9. IA32_RTIT_OUTPUT_MASK _PTRS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24
Table 33-11. CPUID Leaf 14H Enumeration of Intel Processor Trace Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 33-27
Table 33-12. CPUID Leaf 14H, sub-leaf 1H Enumeration of Intel Processor Trace Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-29
Table 33-13. An Illustrative CYC Packet Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-34
Table 33-14. Compound Packet Event Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-37
Table 33-15. Packets Forbidden Between BBP and BEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-37
Table 33-16. TNT Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-39
Table 33-17. IP Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-40
Table 33-18. FUP/TIP IP Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-41

Table 33-19. TNT Examples with Deferred TIPs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-42
Table 33-20. TIP.PGE Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-43
Table 33-21. TIP.PGD Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-44
Table 33-22. FUP Packet Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-45
Table 33-23. FUP Cases and IP Payload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-46
Table 33-24. PIP Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-47
Table 33-25. General Form of MODE Packets  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-48
Table 33-26. MODE.Exec Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-48
Table 33-27. MODE.TSX Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-49
Table 33-28. TraceStop Packet Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-50
Table 33-29. CBR Packet Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-50
Table 33-30. TSC Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-51
Table 33-31. MTC Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-52
Table 33-32. TMA Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-53
Table 33-33. Cycle Count Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-54
Table 33-34. VMCS Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-55
Table 33-35. OVF Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-56
Table 33-36. PSB Packet Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-56
Table 33-37. PSBEND Packet Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-57
Table 33-38. MNT Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-58
Table 33-39. PAD Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-58
Table 33-40. PTW Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-59
Table 33-41. EXSTOP Packet Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-60
Table 33-42. MWAIT Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-61
Table 33-43. PWRE Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-62
Table 33-44. PWRX Packet Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-63
Table 33-45. Block Begin Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-64
Table 33-46. Block Item Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-65
Table 33-47. BIP Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-65
Table 33-48. Block End Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-70
Table 33-49. Control Flow Event Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-71
Table 33-50. CFE Packet Type and Vector Fields Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-71
Table 33-51. Event Data Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-73
Table 33-52. VMX Controls For Intel Processor Trace  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-74
Table 33-53. Packets on VMX Transitions (System-Wide Tracing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-75
Table 33-54. Packets on a Failed VM Entry  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-76
Table 33-55. Packet Generation under Different Example Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 33-77
Table 33-56. Packet Generation with Operations That Alter the Value of PacketEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-78
Table 33-57. Examples of PTWRITE when Trigge rEn && PTWEn is True . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 33-79
Table 33-58. Examples of Power Event Trace when TriggerEn && PwrEvtEn is True. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-79
Table 33-59. Event Trace Examples when Tri ggerEn && ContextEn && EventEn is True . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 33-80
Table 34-1. Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX1  . . . . . . . . . . . . . . . . . .  . . . . . . . . 34-3
Table 34-2. Supervisor and User Mode Enclave Instruction Leaf Functions in Long-Form of SGX2  . . . . . . . . . . . . . . . . . .  . . . . . . . . 34-4
Table 34-3. VMX Operation and Supervisor Mode Enclave Instruction Leaf Functions in Long-Form of OVERSUB . . . . . . . . . . . .  34-4
Table 34-4. Intel® SGX Opt-in and Enabling Behavior  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5
Table 34-5. CPUID Leaf 12H, Sub-Leaf 0 Enumeration of Intel® SGX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5

Table 34-6. CPUID Leaf 12H, Sub-Leaf 1 Enumeration of Intel® SGX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6
Table 34-7. CPUID Leaf 12H, Sub-Leaf Index 2 or Higher Enumeration of Intel® SGX Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6CONTENTS
lVol. 3APAGE
Table 35-1. List of Implicit and Explicit Memory Access by Intel® SGX Enclave Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3
Table 35-2. Layout of SGX Enclave Control Structure (SECS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5
Table 35-3. Layout of ATTRIBUTES Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
Table 35-4. Bit Vector Layout of MISCSELECT Field of Extended Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
Table 35-5. Bit Vector Layout of CET_ATTRIBUTES Field of Extend ed Information. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 35-7
Table 35-6. Layout of Thread Control Structure (TCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-7
Table 35-7. Layout of TCS.FLAGS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8
Table 35-8. Top-to-Bottom Layout of an SSA Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-9
Table 35-9. Layout of GPRSGX Portion of the State Save Area  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-9
Table 35-10. Layout of EXITINFO Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-10
Table 35-11. Exception Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-10
Table 35-12. Layout of MISC region of the State Save Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .35-11
Table 35-13. Layout of EXINFO Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-11
Table 35-14. Page Fault Error Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-12
Table 35-15. Layout of CET State Save Area Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-12
Table 35-16. Layout of PAGEINFO Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-12
Table 35-17. Layout of SECINFO Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-13
Table 35-18. Layout of SECINFO.FLAGS Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-13
Table 35-19. Supported PAGE_TYPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-13
Table 35-20. Layout of PCMD Data Structure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-14
Table 35-21. Layout of Enclave Signature Structure (SIGSTRUCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-14
Table 35-23. Layout of REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-16
Table 35-22. Layout of EINIT Token (EINITTOKEN)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-16
Table 35-24. Layout of TARGETINFO Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-17
Table 35-25. Layout of KEYREQUEST Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-18
Table 35-26. Supported KEYName Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-18
Table 35-27. Layout of KEYPOLICY Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-18
Table 35-28. Layout of Version Array Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-19
Table 35-29. Content of an Enclave Page Cache Map Entry  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-19
Table 35-30. Layout of RDINFO Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-20
Table 35-31. Layout of RDINFO STATUS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-20
Table 35-32. Layout of RDINFO FLAGS Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-20
Table 36-1. Illegal Instructions Inside an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36-15
Table 37-1. GPR, x87 Synthetic States on Asynchronous Enclave Ex it. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3
Table 38-1. Register Usage of Privileged Enclave Instruction Leaf  Functions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1
Table 38-2. Register Usage of Unprivileged Enclave Instruction Leaf Functions . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . 38-2
Table 38-3. Register Usage of Virtualization Operation Enclave In struction Leaf Functions . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 38-2
Table 38-4. Error or Information Codes for Intel® SGX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
Table 38-5. List of Internal CREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3
Table 38-6. Base Concurrency Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-5
Table 38-7. Additional Concurrency Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6
Table 38-8. Base Concurrency Restrictions of EADD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-17
Table 38-9. Additional Concurrency Restrictions of EADD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .38-18
Table 38-10. Base Concurrency Restrictions of EAUG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-22

Table 38-11. Additional Concurrency Restrictions of EAUG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-23
Table 38-12. EBLOCK Return Value in RAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-27
Table 38-13. Base Concurrency Restrictions of EBLOCK  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-27
Table 38-14. Additional Concurrency Restrictions of EBLOCK  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .38-28
Table 38-15. Base Concurrency Restrictions of ECREATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-30
Table 38-16. Additional Concurrency Restrictions of ECREATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-31
Table 38-17. EDBGRD Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-36
Table 38-18. Base Concurrency Restrictions of EDBGRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-37
Table 38-19. Additional Concurrency Restrictio ns of EDBGRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-37
Table 38-20. EDBGWR Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-40
Table 38-21. Base Concurrency Restrictions of EDBGWR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-41
Table 38-22. Additional Concurrency Restrictions of EDBGWR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-41
Table 38-23. Base Concurrency Restrictions of EEXTEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . .38-44
Table 38-24. Additional Concurrency Restrictions of EEXTEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .38-45
Table 38-25. EINIT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-48
Table 38-26. Base Concurrency Restrictions of EINIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-49
Table 38-27. Additional Concurrency Restrictions of ENIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-49
Table 38-28. ELDB/ELDU/ELDBC/ELBUC Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-55
Table 38-29. Base Concurrency Restrictions of ELDB/ELDU/ELDBC/EL BUC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .38-56
Table 38-30. Additional Concurrency Restrictions of ELDB/ELDU/ELDB C/ELBUC. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .38-56
Table 38-31. EMODPR Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-61Vol. 3A liCONTENTS
PAGE
Table 38-32. Base Concurrency Restrictions of EMODPR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-61
Table 38-33. Additional Concurrency Restrictions of EMODPR  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 38-62
Table 38-34. EMODT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-64
Table 38-35. Base Concurrency Restrictions of EMODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-64
Table 38-36. Additional Concurrency Restrictions of EMODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . 38-65
Table 38-37. Base Concurrency Restrictions of EPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-67
Table 38-38. Additional Concurrency Restrictions of EPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-67
Table 38-39. ERDINFO Return Value in RAX  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-69
Table 38-40. Base Concurrency Restrictions of ERDINFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-70
Table 38-41. Additional Concurrency Restrict ions of ERDINFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-70
Table 38-42. EREMOVE Return Value in RAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-73
Table 38-43. Base Concurrency Restrictions of EREMOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-74
Table 38-44. Additional Concurrency Restrictions of EREMOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-74
Table 38-45. ETRACK Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-77
Table 38-46. Base Concurrency Restrictions of ETRACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-77
Table 38-47. Additional Concurrency Restrictions of ETRACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-77
Table 38-48. ETRACKC Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-80
Table 38-49. Base Concurrency Restrictions of ETRACKC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-80
Table 38-50. Additional Concurrency Restrictions of ETRACKC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 38-81
Table 38-51. EWB Return Value in RAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-84
Table 38-52. Base Concurrency Restrictions of EWB  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-84
Table 38-53. Additional Concurrency Restrictions of EWB  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-84
Table 38-54. EACCEPT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-90
Table 38-55. Base Concurrency Restrictions of EACCEPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-91
Table 38-56. Additional Concurrency Restrictions of EACCEPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 38-91

Table 38-57. EACCEPTCOPY Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-95
Table 38-58. Base Concurrency Restrictions of EACCEPTCOPY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 38-96
Table 38-59. Additional Concurrency Restrictions of EACCEPTCOPY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 38-96
Table 38-60. Base Concurrency Restrictions of EDECCSSA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-99
Table 38-61. Additional Concurrency Restrictions of EDECCSSA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-99
Table 38-62. Base Concurrency Restrictions of EENTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-104
Table 38-63. Additional Concurrency Restrictions of EENTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-104
Table 38-64. Base Concurrency Restrictions of EEXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-112
Table 38-65. Additional Concurrency Restrict ions of EEXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-112
Table 38-66. Key Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-116
Table 38-67. EGETKEY Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-116
Table 38-68. Base Concurrency Restrictions of EGETKEY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .38-116
Table 38-69. Additional Concurrency Restrictions of EGETKEY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .38-117
Table 38-70. Base Concurrency Restrictions of EMODPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-125
Table 38-71. Additional Concurrency Restrictions of EMODPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-125
Table 38-72. Base Concurrency Restrictions of EREPORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .38-129
Table 38-73. Additional Concurrency Restrictions of EREPORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .38-129
Table 38-74. Base Concurrency Restrictions of ERESUME. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .38-134
Table 38-75. Additional Concurrency Restrictions of ERESUME. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .38-134
Table 38-76. Base Concurrency Restrictions of EDECVIRTCHILD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-146
Table 38-77. Additional Concurrency Restrict ions of EDECVIRTCHILD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-147
Table 38-78. Base Concurrency Restrictions of EINCVIRTCHILD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .38-150
Table 38-79. Additional Concurrency Restrictions of EINCVIRTCHILD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .38-151
Table 38-80. Base Concurrency Restrictions of ESETCONTEXT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-153
Table 38-81. Additional Concurrency Restrictions of ESETCONTEXT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-154
Table 39-1. SGX Conflict Exit Qualification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4
Table 39-2. SMRAM Synthetic States on Asynchronous Enclave Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 39-11
Table 39-3. Layout of the IA32_SGX_SVN_STATUS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 39-13
Table A-1. Memory Types Recommended for VMCS and Related Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
Table B-1. Encoding for 16-Bit Control Fields (0000_00xx_xxxx_x xx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
Table B-2. Encodings for 16-Bit Guest-State Fields (0000_10xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
Table B-3. Encodings for 16-Bit Host-State Fields (0000_11xx_xxxx_ xxx0B)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .B-2
Table B-4. Encodings for 64-Bit Control Fields (0010_00xx_xxxx_xxxAb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .B-2
Table B-5. Encodings for 64-Bit Read-Only Data Field (0010_01xx_xxxx_xxxAb) . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .B-5
Table B-6. Encodings for 64-Bit Guest-State Fields (0010_10xx_xxxx_xxxAb)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Table B-7. Encodings for 64-Bit Host-State Fields (0010_11xx_xxxx_ xxxAb)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .B-6
Table B-8. Encodings for 32-Bit Control Fields (0100_00xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .B-7
Table B-9. Encodings for 32-Bit Read-Only Data Fields (0100_01xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-8
Table B-10. Encodings for 32-Bit Guest-State Fields (0100_10xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .B-8
Table B-11. Encoding for 32-Bit Host-State Field (0100_11xx_xxxx_xxx0B)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-9CONTENTS
liiVol. 3APAGE
Table B-12. Encodings for Natural-Width Control Fields (0110_00xx_xxxx_xxx0B). . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . B-9
Table B-13. Encodings for Natural-Width Read-Only Data Fields (0 110_01xx_xxxx_xxx0B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
Table B-14. Encodings for Natural-Width Guest-State Fields (0110_ 10xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
Table B-15. Encodings for Natural-Width Host-State Fields (0110_11xx_xxxx_xxx0B) . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . B-11
Table C-1. Basic Exit Reasons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1Vol. 3A 1-1CHAPTER 1
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide, Part 
1 (order number 253668), the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System 
Programming Guide, Part 2 (order number 253669), the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3C: System Programming Guide, Part 3 (order number 326019), and the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 3D:System Programming Guide, Part 4 (order number 
332831) are part of a set that describes the architectu re and programming environm ent of Intel 64 and IA-32 
Architecture processors. The other volumes in this set are:
•Intel® 64 and IA-32 Architectures Software Developer’s Manu al, Volume 1: Basic Architecture (order number 
253665).

253665).
•Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D: Instruction Set 
system and BIOS designers. In addition, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
3B, and Intel® 64 and IA-32 Architectures Software Developer’ s Manual, Volume 3C, address the programming 
environment for classes of software that host operating systems. The Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 4, describes the model-specific registers of Intel 64 and IA-32 processors.
include: 
•Intel® Xeon® processor 5100, 5300 series1-2 Vol. 3AABOUT THIS MANUAL
•Intel® Core™ 2 Extreme QX6000 series
•Intel® Xeon® processor 7100 series
•Intel® Core™ 2 Extreme QX9000 series
C1000 series are built from 45 nm and 32 nm processes.
•Intel® Xeon Phi™ Processor 7215, 7285, 7295 SeriesVol. 3A 1-3ABOUT THIS MANUAL
•2nd generation Intel® Xeon® Scalable Processor Family
The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions ar e based on the Intel NetBurst® micro-
architecture. Most early Intel® Xeon® processors are based on the Intel NetBurst® microarchitecture. Intel Xeon 
the Haswell microarchitecture and support Intel 64 architecture.1-4 Vol. 3AABOUT THIS MANUAL
The Intel Atom® processor Z8000 series is based on the Airmont microarchitecture.

The 12th generation Intel® Core™ processors supporting Alder Lake perf ormance hybrid architecture support Intel 
64 architecture.
1.2 OVERVIEW OF THE SY STEM PROGRAMMING GUIDE
A description of this manual’s content follows1:Vol. 3A 1-5ABOUT THIS MANUAL
Chapter 1  — About This Manual.  Gives an overview of all volumes of the Intel® 64 and IA-32 Architectures Soft-
Chapter 2 — System Architecture Overview. Describes the modes of operation used by Intel 64 and IA-32 
processors and the mechanis ms provided by the architectures to support operating systems and executives, 
including the system-oriented registers and data structures and the system-oriented instructions. The steps neces-
sary for switching between real-address and protected modes are also identified.
Chapter 3 — Protected-Mo de Memory Management.  Describes the data structures, registers, and instructions 
that support segmentation and paging. The chapter explains  how they can be used to implement a “flat” (unseg-
mented) memory model or a segmented memory model.
Chapter 4 — Paging.  Describes the paging modes supported by Intel 64 and IA-32 processors.
Chapter 5 — Protection.  Describes the support for page and segment pr otection provided in the Intel 64 and IA-
32 architectures. This chapter also explains the implementa tion of privilege rules, stack switching, pointer valida-
tion, user mode, and supervisor mode.
Chapter 6 — Interrupt an d Exception Handling.  Describes the basic interrupt mechanisms defined in the Intel 
64 and IA-32 architectures, shows how interrupts and exceptions relate to protection, and describes how the archi-
tecture handles each exception type. Reference information for each exception is given in this chapter. Includes 
programming the LINT0 and LINT1 inputs and gives an ex ample of how to program the LINT0 and LINT1 pins for 
specific interrupt vectors.
Chapter 7 — User Interrupts.  Describes user interrupts supported by Intel 64 and IA-32 processors.
Chapter 8 — Task Management.  Describes mechanisms the Intel 64 and IA-32 architectures provide to support 
multitasking and inter-task protection.
Chapter 9 — Multiple-P rocessor Management.  Describes the instructions and flags that support multiple 
processors with shared memory, memory ordering, and Intel® Hyper-Threading Technology . Includes MP initializa-
tion for P6 family processors and gives an example of how to use the MP protocol to boot P6 family processors in 
an MP system.
Chapter 10 — Processor Mana gement and Initialization.  Defines the state of an Intel 64 or IA-32 processor 
after reset initialization. This chapter also explains how to set up an Intel 64 or IA-32 processor for real-address 
mode operation and protected- mode operation, and how to switch between modes.
Chapter 11 — Advanced Programmabl e Interrupt Controller (APIC).  Describes the programming interface 
to the local APIC and gives an overview of the interface between the local APIC and the I/O APIC. Includes APIC bus 
message formats and describes the message formats for messages transmitted on the APIC bus for P6 family and 
Pentium processors.
Chapter 12 — Memory Cache Control.  Describes the general concept of caching and the caching mechanisms 
supported by the Intel 64 or IA-32 architectures. This chapter also describes the memory type range registers 
(MTRRs) and how they can be used to map memory types of physical memory. Information on using the new cache 
control and memory streaming instructions introduced with the Pentium III, Pentium 4, and Intel Xeon processors 
is also given.
Chapter 13 — Intel® MMX™ Technology Sy stem Programming.  Describes those aspects of the Intel® MMX™ 
technology that must be handled and considered at the system programming level, including: task switching, 
exception handling, and compatibility with existing system environments.
Chapter 14 — System Programming For Instruction Set Extensions And Processor Extended States.  
Describes the operating system requirements to support  SSE/SSE2/SSE3/SSSE3/SSE4 extensions, including task 
switching, exception handling, and compatibility with existi ng system environments. The latter part of this chapter 
describes the extensible framework of operating system  requirements to support processor extended states. 
Processor extended state may be required by instruction set extensions beyond those of 
SSE/SSE2/SSE3/SSSE3/SSE4 extensions.
Chapter 15 — Power and Thermal Management . Describes facilities of Intel 64 and IA-32 architecture used for 
power management and thermal monitoring.
1. Model-Specific Registers have been moved out of this volume and into a separate volume: Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 4.1-6 Vol. 3AABOUT THIS MANUAL
Chapter 16 — Machine-Check Architecture.  Describes the machine-check architecture and machine-check 
exception mechanism found in the Pentium 4, Intel Xeon, and P6 family processors. Additionally, a signaling mech-anism for software to respond to hardware corrected machine check error is covered.
Chapter 17 — Interpreting Machine-Check Error Codes. Gives an example of how to  interpret the error codes 
for a machine-check error that occurred on a P6 family processor.
Chapter 18 — Debug, Branch Profile, TS C, and Resource Monitoring Features.  Describes the debugging 
registers and other debug mechanism provided in Intel 64 or IA-32 processors. This chapter also describes the 
time-stamp counter. 
Chapter 19 — Last Branch Records. Describes the Last Branch Records (architectural feature).
Chapter 20 — Performance Monitoring. Describes the Intel 64 and IA-32 architectures’ facilities for monitoring 
performance.
Chapter 21 — 8086 Emulation.  Describes the real-address and virtual-8086 modes of the IA-32 architecture.
Chapter 22 — Mixing 16 -Bit and 32-Bit Code.  Describes how to mix 16-bit and 32-bit code modules within the 
same program or task.
Chapter 23 — IA-32 Arch itecture Compatibility.  Describes architectural compatibility among IA-32 proces-
sors.
Chapter 24 — Introduction to Virtual Machine Extensions. Describes the basic elements of virtual machine 
architecture and the virtual machine extensions for Intel 64 and IA-32 Architectures.
Chapter 25 — Virtual Machine Control Structures.  Describes components that manage VMX operation. These

sors.
Chapter 25 — Virtual Machine Control Structures.  Describes components that manage VMX operation. These 
include the working-VMCS pointer and the controlling-VMCS pointer.
Chapter 26 — VMX Non-Root Operation. Describes the operation of a VMX non-root operation. Processor oper-
ation in VMX non-root mode can be restricted programmatic ally such that certain operations, events or conditions 
can cause the processor to transfer control from the guest (running in VMX non-root mode) to the monitor software 
(running in VMX root mode).
Chapter 27 — VM Entries. Describes VM entries. VM entry transitions the processor from the VMM running in VMX 
root-mode to a VM running in VMX non-root mode. VM-Entry  is performed by the execution of VMLAUNCH or VMRE-
SUME instructions.
Chapter 28 — VM Exits. Describes VM exits. Certain events, operations or situations while the processor is in VMX 
non-root operation may cause VM-exit transitions. In ad dition, VM exits can also occur on failed VM entries.
Chapter 29 — VMX Support for Address Translation. Describes virtual-machine extensions that support 
address translation and the virtualization of physical memory.
Chapter 30 — APIC Virtualization and Virtual Interrupts. Describes the VMCS including controls that enable 
the virtualization of interrupts and the Advanc ed Programmable Interrupt Controller (APIC).
Chapter 31 — VMX Instruction Reference. Describes the virtual-machine extensions (VMX). VMX is intended 
for a system executive to support virtualization of processo r hardware and a system software layer acting as a host 
to multiple guest software environments.
Chapter 32 — System  Management Mode. Describes Intel 64 and IA-32 architectures’ system management 
mode (SMM) facilities.
Chapter 33 — Intel
® Processor Trace. Describes details of Intel® Processor Trace.
Chapter 34 — Introduction to Intel® Software Guard Extensions. Provides an overview of the Intel® Soft-
ware Guard Extensions (Intel® SGX) set of instructions.
Chapter 35 — Enclave Access Co ntrol and Data Structures. Describes Enclave Access Control procedures and 
defines various Intel SGX data structures.
Chapter 36 — Enclave Operation. Describes enclave creation and initializ ation, adding pages and measuring an 
enclave, and enclave entry and exit.
Chapter 37 — Enclave Exiting Events. Describes enclave-exiting events (E EE) and asynchronous enclave exit 
(AEX).
Chapter 38 — SGX Instruction References. Describes the supervisor and user level instructions provided by 
Intel SGX.Vol. 3A 1-7ABOUT THIS MANUAL
Chapter 39 — Intel® SGX Interactions with IA32 and Intel® 64 Architecture. Describes the Intel SGX 
collection of enclave instructions for creating protecte d execution environments on processors supporting IA32 and 
Intel 64 architectures.
Chapter 40 — Enclave Co de Debug and Profiling. Describes enclave code debug processes and options.
Appendix A — VMX Capability Reporting Facility. Describes the VMX capability MSRs. Support for specific VMX 
features is determined by reading capability MSRs.
Appendix B — Field Encoding in VMCS. Enumerates all fields in the VMCS and their encodings. Fields are 
grouped by width (16-bit, 32-bit, etc.) and type (guest-state, host-state, etc.).
Appendix C — VM Basic Exit Reasons.  Describes the 32-bit fields that encode reasons for a VM exit. Examples 
of exit reasons include, but are not limited to: software  interrupts, processor exceptions, software traps, NMIs, 
external interrupts, and triple faults.
the bytes of a word are numbered starting from the leas t significant byte. Figure 1-1 illustrates these conventions.
In many register and memory layout de scriptions, certain bits are marked as reserved . When bits are marked as 
•Do not depend on the states of any reserved bits when testing the values of registers which contain such bits. 
NOTE
reserved values risk incompatibility with future processors.1-8 Vol. 3AABOUT THIS MANUAL
When instructions are represented symbolically, a subset of  assembly language is used. In this subset, an instruc-
tion has the following format:
where:
In this example LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand, 
1.3.4 Hexadecimal and Binary Numbers
E, and F.
example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might 
arise.
range of memory that can be addressed is called an address space .Figure 1-1.  Bit and Byte OrderByte 3HighestData Structure 
Byte 1 Byte 2 Byte 031 2423 1615 87 0Address
28
24
20
16
12
8
40Address
Byte OffsetVol. 3A 1-9ABOUT THIS MANUAL
register:
DS:FF79H
CS:EIP
1.3.6 Syntax for CPUID, CR, and MSR Values
bits, and by reading model-specific registers. We are moving  toward a single syntax to represent this type of infor-
mation. See Figure 1-2.
Figure 1-2.  Syntax for CPUID, CR, and MSR Data PresentationInput value for EAX register

register:
DS:FF79H
CS:EIP
Value (or range) of output1-10 Vol. 3AABOUT THIS MANUAL
1.3.7 Exceptions
This example refers to a page-fault exception under cond itions where an error code naming a type of fault is 
code. In this case, the error code is zero, as  shown below for a general-protection exception:
#GP(0)
See also: 
•Intel® Software Guard Extensions (Intel® SGX) Information
https://software.intel.com/sites/default/files/article/147714/51534-developing-multithreaded-applica-tions.pdf
•Performance Monitoring Unit Sharing Guide
•Intel® Architecture Instruction Set Extensions Programming Reference
More relevant links are:Vol. 3A 1-11ABOUT THIS MANUAL
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm1-12 Vol. 3AABOUT THIS MANUALVol. 3A 2-1CHAPTER 2
IA-32 architecture (beginning with the Intel386 processor family) provides extensive support for operating-system 
and system-development software. This support offe rs multiple modes of operation, which include:
•Real mode, protected mode, virtual 8086 mode, an d system management mode. These are sometimes 
referred to as legacy modes.
Intel 64 architecture supports almost all the system pr ogramming facilities available in IA-32 architecture and 
extends them to a new operating mode (IA-32e mode) that supports a 64-bit programming environment. IA-32e 
mode allows software to operate in one of two sub-modes: 
•64-bit mode supports 64-bit OS and 64-bit applications
•Compatibility mode allows most legacy software to run; it co-exists with 64-bit applications under a 64-bit OS.
The IA-32 system-level architecture includes fe atures to assist in the following operations:
•Memory management.
•Protection of software modules.
•Multitasking.
•Exception and interrupt handling.
•Multiprocessing.
•Cache management.
•Hardware resource and power management.
•Debugging and performance monitoring.
This chapter provides a description of each part of this architecture. It also describes the system registers that are 
used to set up and control the processor at the system le vel and gives a brief overview of the processor’s system-
level (operating system) instructions.
Many features of the system-level architecture are us ed only by system programmers. However, application 
programmers may need to read this chapter and the follow ing chapters in order to create a reliable and secure 
environment for application programs.
This overview and most subsequent chapters of this book  focus on protected-mode operation of the IA-32 architec-
ture. IA-32e mode operation of the Intel 64 architecture, as it differs from protected mode operation, is also 
described. 
All Intel 64 and IA-32 processors enter real-address mode following a power-up or reset (see Chapter 10, 
“Processor Management and Initialization”). Software th en initiates the switch from real-address mode to 
protected mode. If IA-32e mode operation is desired, softwa re also initiates a switch from protected mode to IA-
32e mode.
2.1 OVERVIEW OF THE SY STEM-LEVEL ARCHITECTURE
System-level architecture consists of a set of registers, data structures, and instructions designed to support basic 
system-level operations such as memory management, interrupt and exception handling, task management, and 
control of multiple processors.
Figure 2-1 provides a summary of system registers and data structures that applies to 32-bit modes. System regis-
ters and data structures that apply to IA-32e mode are shown in Figure 2-2.2-2 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
Figure 2-1.  IA-32 System-Level Registers and Data StructuresLocal Descriptor
Table (LDT)EFLAGS Register
Control Registers
CR1CR2CR3CR4
CR0Global Descriptor
Table (GDT)
Interrupt Descriptor
Table (IDT)
IDTRGDTRInterrupt Gate
Trap GateLDT Desc.TSS Desc.
Code
StackCode
StackCode
Stack
Segment (TSS)
Code
Data
StackTaskInterrupt Handler
Exception Handler
Protected ProcedureTSS Seg. Sel.
Call-Gate
Dir Table OffsetLinear Address
Pg. Dir. EntryLinear Address Space
Linear Addr.
0Seg. Desc. Segment Sel.Code, Data or
Stack Segment
Interrupt
Vector
TSS Desc.Seg. Desc.
Task Gate
Current
TSSCall GateTask-State
Code
Data
StackTask
Seg. Desc.Current
TSS
Current
TSSSegment SelectorLinear Address
CR3*Page Table
Pg. Tbl. EntryPage
Physical Addr.LDTR
This page mapping example is for 4-KByte pages
and 32-bit paging.Register
*Physical AddressPhysical Address
XCR0 (XFEM)Vol. 3A 2-3SYSTEM ARCHITECTURE OVERVIEW
2.1.1 Global and Local Descriptor Tables
When operating in protected mode, all memory accesses pa ss through either the global descriptor table (GDT) or 
an optional local descriptor table (LDT) as shown in Figure 2-1. These tables contain entries called segment 
descriptors. Segment descriptors provide the base addre ss of segments well as access rights, type, and usage 
information.Figure 2-2.  System-Level Regi sters and Data Structures in IA-32e Mode and 4-Level PagingLocal Descriptor
Table (LDT)CR1CR2CR3CR4
Code
StackCode
StackCode
Stack
Current TSSCode
StackInterr. HandlerInterrupt Handler
Protected ProcedureTR
Call-Gate
PML4
PML4.Linear Address Space
0Seg. Desc. Segment Sel.Code, Data or Stack 
Segment (Base =0)
Interrupt
Vector
Seg. Desc.Seg. Desc.
NULLCall GateTask-State
Seg. Desc.NULL
NULLSegment SelectorLinear Address
CR3*PageLDTR
and 4-level paging.Register
CR8Control RegisterRFLAGS
Offset Table Directory
Page Table
EntryPhysical
Addr. Page Tbl
EntryPage Dir. Pg. Dir. Ptr. PML4 Dir. Pointer
Pg. Dir.
EntryInterrupt Gate
IST
XCR0 (XFEM)
PKRU2-4 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
Each segment descriptor has an associated segment selector. A segment selector provides the software that uses

Code
StackCode
StackCode
Stack
Call-Gate
PML4
Interrupt
Vector
Page Table
Pg. Dir.
IST
Each segment descriptor has an associated segment selector. A segment selector provides the software that uses 
it with an index into the GDT or LDT (the offset of its associated segment descriptor), a global/local flag (deter-
mines whether the selector points to the GDT or the LDT), and access rights information. 
To access a byte in a segment, a segment selector and an offset must be supplied. The segment selector provides 
access to the segment descriptor for the segment (in the GDT or LDT). From the segment descriptor, the processor 
obtains the base address of the segment in the linear addr ess space. The offset then provides the location of the 
byte relative to the base address. This mechanism can be  used to access any valid code, data, or stack segment, 
provided the segment is accessible from the current privile ge level (CPL) at which the processor is operating. The 
CPL is defined as the protection level of the currently executing code segment.
See Figure 2-1. The solid arrows in the figure indicate a linear address, dashed lines indicate a segment selector, 
and the dotted arrows indicate a physical address. For simplicity, many of the segment selectors are shown as 
direct pointers to a segment. However, the actual path from a segment selector to its associated segment is always 
through a GDT or LDT.
The linear address of the base of the GDT is contained in  the GDT register (GDTR); the linear address of the LDT is 
contained in the LDT register (LDTR).
2.1.1.1  Global and Local Desc riptor Tables in IA-32e Mode
GDTR and LDTR registers are expanded to 64-bits wide in both IA-32e sub-modes (64-bit mode and compatibility 
mode). For more information: see Section 3.5.2, “Segment Descriptor Tables in IA-32e Mode.”
Global and local descriptor tables are expanded in 64-bit  mode to support 64-bit ba se addresses, (16-byte LDT 
descriptors hold a 64-bit base address and various a ttributes). In compatibility mode, descriptors are not 
expanded. 
2.1.2 System Segments, Segment Descriptors, and Gates
Besides code, data, and stack segments that make up th e execution environment of a program or procedure, the 
architecture defines two system segments: the task-state  segment (TSS) and the LDT. The GDT is not considered 
a segment because it is not accessed by means of a segment selector and segment descriptor. TSSs and LDTs have 
segment descriptors defined for them.
The architecture also defines a set of special descriptors called gates (call gates, interrupt gates, trap gates, and 
task gates). These provide protected ga teways to system procedures and handlers that may operate at a different 
privilege level than application programs and most proc edures. For example, a CALL to a call gate can provide 
access to a procedure in a code segment that is at the sa me or a numerically lower priv ilege level (more privileged) 
than the current code segment. To access a procedure through a call gate, the calling procedure1 supplies the 
selector for the call gate. The processor then performs an access rights check on the call gate, comparing the CPL with the privilege level of the call gate and the dest ination code segment pointed to by the call gate. 
If access to the destination code segment is allowed, th e processor gets the segment selector for the destination 
code segment and an offset into that code segment from the call gate. If the call requires a change in privilege 
level, the processor also switches to the stack for the ta rgeted privilege level. The segment selector for the new 
stack is obtained from the TSS for the currently running task. Gates also facilitate transitions between 16-bit and 
32-bit code segments, and vice versa. 
2.1.2.1  Gates in IA-32e Mode
In IA-32e mode, the following descriptors are 16-byte descriptors (expanded to allow a 64-bit base): LDT descrip-tors, 64-bit TSSs, call gates, in terrupt gates, and trap gates.
Call gates facilitate transitions between 64-bit mode and compatibility mode. Task gates are not supported in IA-
32e mode. On privilege level changes, stack segment selector s are not read from the TSS. Instead, they are set to 
NULL.
1. The word “procedure” is commonly  used in this document as a general term for a logical unit or block of code (such as a progr am, pro-
cedure, function, or routine). Vol. 3A 2-5SYSTEM ARCHITECTURE OVERVIEW
2.1.3 Task-State Segments and Task Gates
The TSS (see Figure 2-1) defines the state of the execution environment for a task. It includes the state of general-
purpose registers, segment registers, the EFLAGS regist er, the EIP register, and segment selectors with stack 
pointers for three stack segments (one stack for each priv ilege level). The TSS also includes the segment selector 
for the LDT associated with the task and the ba se address of the paging-structure hierarchy. 
All program execution in protected mode happens within the context of a task (called the current task). The 
segment selector for the TSS for the current task is stored  in the task register. The si mplest method for switching 
to a task is to make a call or jump to the new task. Here , the segment selector for the TSS of the new task is given 
in the CALL or JMP instruction. In switching tasks, the processor performs the following actions:
1. Stores the state of the current task in the current TSS.
2. Loads the task register with the segment selector for the new task.
3. Accesses the new TSS through a segment descriptor in the GDT.4. Loads the state of the new task from the new TSS into  the general-purpose registers, the segment registers, 
the LDTR, control register CR3 (base address of the pagi ng-structure hierarchy), th e EFLAGS register, and the 
EIP register.
5. Begins execution of the new task.
A task can also be accessed through a task gate. A task gate is similar to a call gate, except that it provides access 
(through a segment selector) to a TSS rather than a code segment. 
2.1.3.1  Task-State Segments in IA-32e Mode
Hardware task switches are not supported in IA-32e mode. However, TSSs continue to exist. The base address of 
a TSS is specified by its descriptor. 
A 64-bit TSS holds the following information that is important to 64-bit operation: 
•Stack pointer addresses for each privilege level.
•Pointer addresses for the interrupt stack table.
•Offset address of the IO-permission bitmap (from the TSS base).
The task register is expanded to hold 64-bit base addr esses in IA-32e mode. See also: Section 8.7, “Task Manage-
ment in 64-bit Mode.”
2.1.4 Interrupt and Exception Handling
External interrupts, software interrupts and exceptions are handled through the interrupt descriptor table (IDT). 
The IDT stores a collection of gate descriptors that provide access to interrupt and exception handlers. Like the GDT, the IDT is not a segment. The linear address for the base of the IDT is contained in the IDT register (IDTR).
Gate descriptors in the IDT can be interrupt, trap, or ta sk gate descriptors. To access an interrupt or exception 
handler, the processor first receives an interrupt vector fr om internal hardware, an external interrupt controller, or 
from software by means of an INT n, INTO, INT3, INT1, or BOUND instruction. The interrupt vector provides an 
index into the IDT. If the selected gate descriptor is an interrupt gate or a trap gate, the associated handler proce-
dure is accessed in a manner similar to calling a procedure th rough a call gate. If the descriptor is a task gate, the 
handler is accessed through a task switch.
2.1.4.1  Interrupt and Exception Handling IA-32e Mode
In IA-32e mode, interrupt gate descriptors  are expanded to 16 bytes to support 64-bit base addresses. This is true 
for 64-bit mode and compatibility mode. 
The IDTR register is expanded to hold a 64-b it base address. Task gates are not supported.2-6 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
2.1.5 Memory Management
System architecture supports either direct physical addr essing of memory or virtual memory (through paging). 
When physical addressing is used, a linear address is treate d as a physical address. When paging is used: all code, 
data, stack, and system segments (including the GDT and IDT) can be paged with only the most recently accessed 
pages being held in  physical memory.
The location of pages (sometimes called page frames) in physical memory is contained in the paging structures. 
These structures reside in physical memory (see Figure 2-1 for the case of 32-bit paging). 
The base physical address of the paging-structure hierarchy is contained in control register CR3. The entries in the 
paging structures determine the physical address of the base of a page frame, access rights and memory manage-
ment information. 
To use this paging mechanism, a linear address is broken  into parts. The parts provide separate offsets into the 
paging structures and the page frame. A system can have a single hierarchy of paging structures or several. For 
example, each task can have its own hierarchy.
2.1.5.1  Memory Management in IA-32e Mode

2.1.5.1  Memory Management in IA-32e Mode 
In IA-32e mode, physical memory pages are managed by a set of system data structures. In both compatibility 
mode and 64-bit mode, four or five levels of system da ta structures are used (see Chapter 4, “Paging”). These 
include the following: 
•The page map level 5 (PML5)  — An entry in the PML5 table contains the physical address of the base of a 
PML4 table, access rights, and memory management information. The base physical address of the PML5 table 
is stored in CR3. The PML5 table is used only with 5-level paging.
•A page map level 4 (PML4)  — An entry in a PML4 table contains the physical address of the base of a page 
directory pointer table, access rights, and memory manage ment information. With 4-level paging, there is only 
one PML4 table and its base physical address is stored in CR3.
•A set of page directory pointer tables  — An entry in a page directory po inter table contains the physical 
address of the base of a page directory table, access rights, and memory management information.
•Sets of page directories  — An entry in a page directory table contai ns the physical address of the base of a 
page table, access rights, and memory management information.
•Sets of page tables  — An entry in a page table contains the phys ical address of a page frame, access rights, 
and memory management information.
2.1.6 System Registers
To assist in initializing the processor and controlling syst em operations, the system ar chitecture provides system 
flags in the EFLAGS register and several system registers:
•The system flags and IOPL field in the EFLAGS register  control task and mode swit ching, interrupt handling, 
instruction tracing, and access rights. See also: Section 2.3, “System Flags and Fields in the EFLAGS Register.”
•The control registers (CR0, CR2, CR3, and CR4) contain a variety of flags and data fields for controlling system-
level operations. Other flags in these registers are used to indicate support for specific processor capabilities 
within the operating system or executive. See also: Chap ter 2, “Control Registers,” and Section 2.6, “Extended 
Control Registers (Including XCR0).”
•The debug registers (not shown in Fi gure 2-1) allow the setting of breakpoints for use in debugging programs 
and systems software. See also: Chapter 18, “Debug, Br anch Profile, TSC, and Intel® Resource Director 
Technology (Intel® RDT) Features.”
•The GDTR, LDTR, and IDTR registers contain the linear addresses and sizes (limits) of their respective tables. See also: Section 2.4, “Memory-Management Registers.”
•The task register contains the linear address and size of the TSS for the current task. See also: Section 2.4, 
“Memory-Management Registers.”
•Model-specific registers (not shown in Figure 2-1).Vol. 3A 2-7SYSTEM ARCHITECTURE OVERVIEW
The model-specific registers (MSRs) are a group of regist ers available primarily to op erating-system or executive 
procedures (that is, code running at privilege level 0). These registers control items such as the debug extensions, the performance-monitoring counters, the machine- chec k architecture, and the memory type ranges (MTRRs). 
The number and function of these registers varies amon g different members of the Intel 64 and IA-32 processor 
families. See also: Section 10.4, “Model-Specific Regist ers (MSRs),” and Chapter 2, “Model-Specific Registers 
(MSRs),” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4.
Most systems restrict access to system registers (other  than the EFLAGS register) by application programs. 
Systems can be designed, however, where all programs and procedures run at the most privileged level (privilege 
level 0). In such a case, application programs wo uld be allowed to modify the system registers.
2.1.6.1  System Registers in IA-32e Mode
In IA-32e mode, the four system-descriptor-table register s (GDTR, IDTR, LDTR, and TR) are expanded in hardware 
to hold 64-bit base addresses. EFLAGS becomes the 64-b it RFLAGS register. CR0–CR4 are expanded to 64 bits. 
CR8 becomes available. CR8 provides read-write access to the task priority register (TPR) so that the operating 
system can control the priority classes of external interrupts. 
In 64-bit mode, debug registers DR0–DR7 are 64 bits. In  compatibility mode, address-matching in DR0–DR3 is 
also done at 64-bit granularity.
On systems that support IA-32e mode, the extended feature enable register (IA32_EFER) is available. This model-
specific register controls activation of IA-32e mode and other IA-32e mode operations. In addition, there are 
several model-specific registers that govern IA-32e mode instructions:
•IA32_KERNEL_GS_BASE — Used by SWAPGS instruction.
•IA32_LSTAR — Used by SYSCALL instruction.
•IA32_FMASK — Used by SYSCALL instruction.
•IA32_STAR — Used by SYSCALL and SYSRET instruction.
2.1.7 Other System Resources
Besides the system registers and data structures described in the previous sections, system architecture provides 
the following additional resources:
•Operating system instructions (see also: Section 2.8, “System Instruction Summary”).
•Performance-monitoring counters (not shown in Figure 2-1).
•Internal caches and buffers (not shown in Figure 2-1).
Performance-monitoring counters are event counters that can be programmed to count processor events such as 
the number of instructions decoded, the number of in terrupts received, or the number of cache loads. 
The processor provides several internal caches and buffers . The caches are used to store both data and instruc-
tions. The buffers are used to store things like decoded addresses to system and application segments and write 
operations waiting to be performed. See also: Chapter 12, “Memory Cache Control.”
2.2 MODES OF OPERATION
The IA-32 architecture supports three oper ating modes and one quasi-operating mode: 
•Protected mode — This is the native operating mode of the proc essor. It provides a rich set of architectural 
features, flexibility, high performance and backward compatibility to existing software base.
•Real-address mode — This operating mode provides the pr ogramming environment of the Intel 8086 
processor, with a few extensions (such as the ability to switch to protected or system management mode).
•System management mode (SMM) — SMM is a standard architectural feature in all IA-32 processors, 
beginning with the Intel386 SL processor. This mode  provides an operating system or executive with a 
transparent mechanism for implementing power mana gement and OEM differentiation features. SMM is 
entered through activation of an external system inte rrupt pin (SMI#), which generates a system management 2-8 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
interrupt (SMI). In SMM, the processor switches to a separate address space while saving the context of the 
currently running program or task. SMM-specific code may then be executed transparently. Upon returning 
from SMM, the processor is placed ba ck into its state prior to the SMI.
•Virtual-8086 mode — In protected mode, the processor supports  a quasi-operating mode known as virtual-
8086 mode. This mode allows the processor execute 8086 software in a protected, multitasking environment.
Intel 64 architecture supports all operating modes of IA-32 architecture and IA-32e modes:
•IA-32e mode — In IA-32e mode, the processor supports two sub-modes: compatibility mode and 64-bit 
mode. 64-bit mode provides 64-bit linear addressing and support for physical address space larger than 64 
GBytes. Compatibility mode allows most legacy protected-mode applications to run unchanged.
Figure 2-3 shows how the processor moves between operating modes.
The processor is placed in real-address mode following power- up or a reset. The PE flag in control register CR0 then 
controls whether the processor is operating in real-address or protected mode. See also: Section 10.9, “Mode 
Switching,” and Section 4.1. 2, “Paging-Mode Enabling.”
The VM flag in the EFLAGS register determines whether the processor is operating in protected mode or virtual-
8086 mode. Transitions between protected mode and virtual- 8086 mode are generally carried out as part of a task 
switch or a return from an interrupt or exception handle r. See also: Section 21.2.5, “Entering Virtual-8086 Mode.”
The LMA bit (IA32_EFER.LMA[bit 10]) determines whether the processor is operating in IA-32e mode. When 
running in IA-32e mode, 64-bit or compatibility sub-mode op eration is determined by CS.L bit of the code segment. 
The processor enters into IA-32e mode from protecte d mode by enabling paging and setting the LME bit 
(IA32_EFER.LME[bit 8]). See also: Chapter 10, “Processor Management and Initialization.”
The processor switches to SMM whenever it receives an SMI while the processor is in real-address, protected, 
virtual-8086, or IA-32e modes. Upon execution of the RS M instruction, the processor always returns to the mode 
it was in when the SMI occurred.Figure 2-3.  Transitions Among the Processor’s Operating ModesReal-Address
ModeSystem

ModePE=1Reset or
VM=1 VM=0PE=0Reset
or
RSMSMI#
RSMSMI#RSMSMI#
Reset Mode
IA-32e
ModeRSMSMI#LME=1, CR0.PG=1*
See**
* See Section 10.8.5
** See Section 10.8.5.4Vol. 3A 2-9SYSTEM ARCHITECTURE OVERVIEW
2.2.1 Extended Feature Enable Register
The IA32_EFER MSR provides several fields related to IA-3 2e mode enabling and operation. It also provides one 
field that relates to page-access right modification (see Section 4.6, “Access Rights”). The layout of the IA32_EFER 
MSR is shown in Figure 2-4.
2.3 SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER
The system flags and IOPL field of the EFLAGS register co ntrol I/O, maskable hardware interrupts, debugging, task 
switching, and the virtual-8086 mode (see Figure 2-5). Only privileged code (typically operating system or execu-
tive code) should be allowed to modify these bits.
The system flags and IOPL are:
TF Trap (bit 8) — Set to enable single-step mode for debugging;  clear to disable single-step mode. In single-
step mode, the processor generates a debug exception after each instruction. This allows the execution 
state of a program to be inspected after each instructio n. If an application program sets the TF flag using a Figure 2-4.  IA32_EFER MSR Layout
Table 2-1.  IA32_EFER MSR Information
0 SYSCALL Enable: IA32_EFER.SCE (R/W) 
Enables SYSCALL/SYSRET instructions in 64-bit mode.
7:1 Reserved.8 IA-32e Mode Enable: IA32_EFER.LME (R/W)
Enables IA-32e mode operation.
9R e s e r v e d .10 IA-32e Mode Active: IA32_EFER.LMA (R) 
Indicates IA-32e mode is active when set.
11 Execute Disable Bit Enable: IA32_EFER.NXE (R/W)
Enables page access restriction by preventing instruction fetches from PAE pages with the XD bit set (See Section 4.6).
63:12 Reserved.ReservedIA-32e Mode Active0 1 789101112 63
IA32_EFER
IA-32e Mode EnableExecute Disable Bit Enable
SYSCALL Enable2-10 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
POPF, POPFD, or IRET instruction, a debug exception is generated after the instruction that follows the 
POPF, POPFD, or IRET.
IF Interrupt enable (bit 9) — Controls the response of the proce ssor to maskable hardware interrupt 
requests (see also: Section 6.3.2, “Maskable Hardware Interrupts”). The flag is se t to respond to maskable 
hardware interrupts; cleared to inhibit maskable hardwa re interrupts. The IF flag does not affect the gener-
ation of exceptions or nonmaskable interrupts (NMI in terrupts). The CPL, IOPL, and the state of the VME 
flag in control register CR4 determine whether the IF flag can be modified by the CLI, STI, POPF, POPFD, and IRET.
IOPL I/O privilege level field (bits 12 and 13) — Indicates the I/O privilege level (IOPL) of the currently 
running program or task. The CPL of the currently running program or task must be less than or equal to 
the IOPL to access the I/O address space. The POPF and IRET instructions can modify this field only when 
operating at a CPL of 0. 
The IOPL is also one of the mechanisms that controls  the modification of the IF flag and the handling of 
interrupts in virtual-8086 mode when virtual mode exte nsions are in effect (when CR4.VME = 1). See also: 
Chapter 19, “Input/Output,” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
1.
NT Nested task (bit 14) — Controls the chaining of interrupted and called tasks. The processor sets this flag 
on calls to a task initiated with a CALL instruction, an  interrupt, or an exception. It examines and modifies 
this flag on returns from a task initiated with the IRET  instruction. The flag can be explicitly set or cleared 
with the POPF/POPFD instructions; however, changing to the state of this flag can generate unexpected 
exceptions in application programs. 
See also: Section 8.4, “Task Linking.”
RF Resume (bit 16) — Controls the processor’s response to instruction-breakpoint conditions. When set, this 
flag temporarily disables debug exceptions (#DB) from being generated for instruction breakpoints 
(although other exception conditions can cause an exception to be generated). When clear, instruction 
breakpoints will generate debug exceptions. 
The primary function of the RF flag is to allow the re starting of an instruction following a debug exception 
that was caused by an instruction breakpoint conditio n. Here, debug software must set this flag in the 
EFLAGS image on the stack just prior to returning to  the interrupted program with IRETD (to prevent the 
instruction breakpoint from causing another debug exception). The processor then automatically clears 
this flag after the instruction returned to has been  successfully executed, enabling instruction breakpoint 
faults again.
See also: Section 18.3.1.1, “Instructi on-Breakpoint Exception Condition.”
VM Virtual-8086 mode (bit 17) — Set to enable virtual-8086 mode; cl ear to return to protected mode. Figure 2-5.  System Flags in the EFLAGS Register31 2221 20 19 181716
R
FI
DA
CV
M
VM — Virtual-8086 Mode
RF — Resume FlagNT — Nested Task Flag
IOPL— I/O Privilege Level
IF — Interrupt Enable FlagAC — Alignment Check / Access ControlID — Identification Flag
VIP — Virtual Interrupt Pending15 1314 12 1110 9 876543 210
0C
FA
FP
F1D
FI
FT
FS
FZ
FN
T0 0V
I
PV
I
FO
FI
O
P
L
VIF — Virtual Interrupt Flag
TF — Trap Flag
ReservedReserved (set to 0)Vol. 3A 2-11SYSTEM ARCHITECTURE OVERVIEW
See also: Section 21.2.1, “Enabling Virtual-8086 Mode.”
AC Alignment check or access control (bit 18) — If the AM bit is set in the CR0 register, alignment 
checking of user-mode data accesses is enabled if and on ly if this flag is 1. An alignment-check exception 
is generated when reference is made to an unaligned op erand, such as a word at an odd byte address or a 
doubleword at an address which is not an integral mu ltiple of four. Alignment-check exceptions are gener-
ated only in user mode (privilege level 3). Memory re ferences that default to privilege level 0, such as 
segment descriptor loads, do not generate this exception even when caused by instructions executed in user-mode.
The alignment-check exception can be used to check al ignment of data. This is useful when exchanging 
data with processors which require all data to be al igned. The alignment-check exception can also be used 
by interpreters to flag some pointers as special by misaligning the pointer. This eliminates overhead of 
checking each pointer and only handles the special pointer when used.
If the SMAP bit is set in the CR4 register, explicit  supervisor-mode data accesses to user-mode pages are 
allowed if and only if this bit is  1. See Section 4.6, “Access Rights.”
VIF Virtual Interrupt (bit 19) — Contains a virtual image of the IF flag. This flag is used in conjunction with 
the VIP flag. The processor only recognizes the VIF flag when either the VME flag or the PVI flag in control 
register CR4 is set and the IOPL is less than 3. (The  VME flag enables the virtual-8086 mode extensions; 
the PVI flag enables the protected-mode virtual interrupts.) 
See also: Section 21.3.3.5, “Method 6: Software Interrupt Handling,” and Section 21.4, “Protected-Mode 
Virtual Interrupts.”
VIP Virtual interrupt pending (bit 20) — Set by software to indicate that an interrupt is pending; cleared to 
indicate that no interrupt is pending. This flag is used in conjunction with the VIF flag. The processor reads this flag but never modifies it. The processor only reco gnizes the VIP flag when either the VME flag or the 
PVI flag in control register CR4 is set and the IOPL is less than 3. The VME fl ag enables the virtual-8086 
mode extensions; the PVI flag enables the protected-mode virtual interrupts. 
See Section 21.3.3.5, “Method 6: Software Interrupt Handling,” and Section 21.4, “Protected-Mode Virtual 
Interrupts.”
ID Identification (bit 21)  — The ability of a program or procedure to set or clear this flag indicates support 
for the CPUID instruction.
2.3.1 System Flags and Fields in IA-32e Mode
In 64-bit mode, the RFLAGS register expands to 64 bits with the upper 32 bits reserved. System flags in RFLAGS (64-bit mode) or EFLAGS (compatibility mode) are shown in Figure 2-5.
In IA-32e mode, the processor does not allow the VM bi t to be set because virtual-8086 mode is not supported 
(attempts to set the bit are ignored). Also, the processor wi ll not set the NT bit. The processor does, however, allow 
software to set the NT bit (note that an IRET causes a gene ral protection fault in IA-32e mode if the NT bit is set).
In IA-32e mode, the SYSCALL/SYSRET instructions have  a programmable method of specifying which bits are 
cleared in RFLAGS/EFLAGS. These inst ructions save/restore EFLAGS/RFLAGS.
2.4 MEMORY-MANAGEMENT REGISTERS
The processor provides four memory-management registers (GDTR, LDTR, IDTR, and TR) that specify the locations 
of the data structures which control segmented memory management (see Figure 2-6). Special instructions are 
provided for loading and storing these registers.2-12 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
2.4.1 Global Descriptor Table Register (GDTR)

The GDTR register holds the base address (32 bits in prot ected mode; 64 bits in IA-32e mode) and the 16-bit table 
limit for the GDT. The base address specifies the linear a ddress of byte 0 of the GDT; the table limit specifies the 
number of bytes in the table. 
The LGDT and SGDT instructions load and store the GDTR  register, respectively. On power up or reset of the 
processor, the base address is set to the default value of 0 and the limit is set to 0FFFFH. A new base address must be loaded into the GDTR as part of the processor initialization process for protected-mode operation. 
See also: Section 3.5.1, “Segment Descriptor Tables.”
2.4.2 Local Descriptor Table Register (LDTR)
The LDTR register holds the 16-bit segment selector, base address (32 bits in protected mode; 64 bits in IA-32e 
mode), segment limit, and descriptor attributes for the LDT.  The base address specifies the linear address of byte 
0 of the LDT segment; the segment limit specifies the numb er of bytes in the segment. See also: Section 3.5.1, 
“Segment Descriptor Tables.”
The LLDT and SLDT instructions load and store the segment selector part of the LDTR register, respectively. The 
segment that contains the LDT must have a segment descr iptor in the GDT. When the LLDT instruction loads a 
segment selector in the LDTR: the base address, limit, an d descriptor attributes from the LDT descriptor are auto-
matically loaded in the LDTR. 
When a task switch occurs, the LDTR is automatically loaded with the segment selector and descriptor for the LDT 
for the new task. The contents of the LDTR are not automatically saved prior to writing the new LDT information 
into the register.
On power up or reset of the processor, the segment select or and base address are set to the default value of 0 and 
the limit is set to 0FFFFH.
2.4.3 IDTR Interrupt Descriptor Table Register
The IDTR register holds the base address (32 bits in prot ected mode; 64 bits in IA-32e mode) and 16-bit table limit 
for the IDT. The base address specifies the linear address of byte 0 of the IDT; the table limit specifies the number 
of bytes in the table. The LIDT and SIDT instructions load  and store the IDTR register, respectively. On power up or 
reset of the processor, the base address is set to the de fault value of 0 and the limit is set to 0FFFFH. The base 
address and limit in the register can then be change d as part of the processor initialization process. 
See also: Section 6.10, “Interrupt Descriptor Table (IDT).”Figure 2-6.  Memory Management Registers0 47(79)
GDTR
IDTRSystem Table Registers
32(64)-bit Linear Base Address 16-Bit Table Limit1516
32(64)-bit Linear Base Address
0
Task
LDTRSystem Segment
Seg. Sel.15
Seg. Sel.Segment Descriptor Registers (Automatically Loaded)
32(64)-bit Linear Base Address Segment LimitAttributesRegisters
32(64)-bit Linear Base Address Segment LimitRegister16-Bit Table LimitVol. 3A 2-13SYSTEM ARCHITECTURE OVERVIEW
2.4.4 Task Register (TR)
The task register holds the 16-bit segment selector, base address (32 bits in protected mode; 64 bits in IA-32e 
mode), segment limit, and descriptor attr ibutes for the TSS of the current task. The selector references the TSS 
descriptor in the GDT. The base address specifies the linea r address of byte 0 of the TSS; the segment limit speci-
fies the number of bytes in the TSS. See also: Section 8.2.4, “Task Register.”
The LTR and STR instructions load and store the segment sele ctor part of the task register, respectively. When the 
LTR instruction loads a segment selector in the task register , the base address, limit, and descriptor attributes from 
the TSS descriptor are automatically loaded into the task re gister. On power up or reset of the processor, the base 
address is set to the default value of 0 and the limit is set to 0FFFFH.
When a task switch occurs, the task register is automati cally loaded with the segmen t selector and descriptor for 
the TSS for the new task. The contents of  the task register are not automatically saved prior to writing the new TSS 
information into the register.
2.5 CONTROL REGISTERS
Control registers (CR0, CR1, CR2, CR3, and CR4; see Fi gure 2-7) determine operating mode of the processor and 
the characteristics of the currently executing task. These re gisters are 32 bits in all 32-bit modes and compatibility 
mode. 
In 64-bit mode, control registers are expanded to 64 bi ts. The MOV CRn instructions are used to manipulate the 
register bits. Operand-size prefixes for these inst ructions are ignored. The following is also true:
•The control registers can be read and loaded (or modi fied) using the move-to-or-from-control-registers forms 
of the MOV instruction. In protected mode, the MOV instruct ions allow the control registers to be read or loaded 
(at privilege level 0 only). This restriction means that  application programs or operating-system procedures 
(running at privilege levels 1, 2, or 3) are prev ented from reading or loading the control registers.
•Some of the bits in CR0 and CR4 are reserved and must be written with zeros. Attempting to set any reserved 
bits in CR0[31:0] is ignored. Attempting to set any rese rved bits in CR0[63:32] results in a general-protection 
exception, #GP(0). Attempting to set any reserved bits  in CR4 results in a general-protection exception, 
#GP(0).
•All 64 bits of CR2 are writable by software. 
•Reserved bits in CR3[63:MAXPHYADDR] must be zero. Attempting to set any of them results in #GP(0).
•The MOV CR2 instruction does not check that address written to CR2 is canonical. 
•A 64-bit capable processor will retain the upper 32 bits of  each control register when transitioning out of IA-32e 
mode.
•On a 64-bit capable processor, an execution of MOV to CR  outside of 64-bit mode zeros the upper 32 bits of the 
•Register CR8 is available in 64-bit mode only. 
The control registers are summarized below, and each archit ecturally defined control field in these control registers 
is described individually. In Figure 2-7, the width of the re gister in 64-bit mode is indicated in parenthesis (except 
for CR0).
•CR0 — Contains system control flags that control operating mode and states of the processor. 
•CR1 — Reserved.
•CR2 — Contains the page-fault linear address (the linear address that caused a page fault).
•CR3 — Contains the physical address of the base of th e paging-structure hierarchy and two flags (PCD and 
PWT). Only the most-significant bits (less the lower 12 bits ) of the base address are specified; the lower 12 bits 
of the address are assumed to be 0. The first paging structure must thus be aligned to a page (4-KByte) 
boundary. The PCD and PWT flags control caching of that  paging structure in the processor’s internal data 
caches (they do not control TLB caching of page-directory information).
When using the physical address extension, the CR3 regi ster contains the base address of the page-directory-
pointer table. With 4-level paging and 5-level paging, th e CR3 register contains the base address of the PML4 2-14 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
table and PML5 table, respectively. If PCIDs are enabled,  CR3 has a format different from that illustrated in 
Figure 2-7. See Section 4.5, “4-Level Paging and 5-Level Paging.”
See also: Chapter 4, “Paging.”
•CR4 — Contains a group of flags that enable several arch itectural extensions, and indi cate operating system or 
executive support for specific processor capabilities. Bi ts CR4[63:32] can only be used for IA-32e mode only 
features that are enabled after entering 64-bit mode. Bits CR4[63:32] do not have any effect outside of IA-32e 
mode. 
•CR8 — Provides read and write access to the Task Priority Register (TPR). It specifies the priority threshold 
value that operating systems use to control the priority class of external interrupts allowed to interrupt the processor. This register is available only in 64-bit mode. However, interrupt filtering continues to apply in 
compatibility mode.
Figure 2-7.  Control RegistersS
M
E
PS
M
A PV
M
EP
V
IT
S
DD
EPS
EP
A
EM
C
EP
G
EP
C
EU
M
I
PL
A
57V
M
X
ES
M
X
EP
C
I
D
EK
LReserved31 (63)                                   25     24     23    22     21     20    19     18     17     16     15     14     13     12     11     10      9       8       7       6      5       4       3       2       1      0 
P
K
E
OSXSAVEFSGSBASEOSFXSR
OSXMMEXCPTCR4
P
W
TP
C
DPage-Directory Base CR3
Page-Fault Linear Address CR2
CR1
T
SE
TN
EW
PA
MP
EM
PE
MN
WC
DP
GCR0
ReservedC
E
TP
K
S
31 (63)                                                                                                                                                     12    11                                                     5       4       3       2                0 
31 (63)                                                                                                                                                                                                                                                                   0

S
DD
EPS
EP
A
EM
C
EP
G
EP
C
EU
M
I
PL
A
57V
M
X
ES
M
X
EP
C
I
D
EK
P
K
E
P
W
TP
C
CR1
T
SE
TN
EW
PA
MP
EM
PE
MN
WC
DP
GCR0
ReservedC
E
TP
K
S
31 (63)                                                                                                                                                                                                                                                                   0 
31 (63)                                                                                                                                                                                                                                                                   0 
31     30     29    28                                                                    19     18     17     16     15                                                                              6      5       4       3       2       1      0 U
I
N
T
RVol. 3A 2-15SYSTEM ARCHITECTURE OVERVIEW
The flags in control registers are:
CR0.PG
Paging (bit 31 of CR0) — Enables paging when set; disables paging when clear. When paging is 
disabled, all linear addresses are treated as physical addr esses. The PG flag has no effect if the PE flag (bit 
0 of register CR0) is not also set; setting the PG flag  when the PE flag is clear causes a general-protection 
exception (#GP). See also: Chapter 4, “Paging.”
On Intel 64 processors, enabling and disabling IA- 32e mode operation also requires modifying CR0.PG.
CR0.CD
Cache Disable (bit 30 of CR0)  — When the CD and NW flags are clear, caching of memory locations for 
the whole of physical memory in the processor’s intern al (and external) caches is enabled. When the CD 
flag is set, caching is restricted as described in Table 12-5. To prevent the processor from accessing and 
updating its caches, the CD flag must be set and the ca ches must be invalidated so that no cache hits can 
occur.
See also: Section 12.5.3, “Preventing Cach ing,” and Section 12.5, “Cache Control.”
CR0.NW
Not Write-through (bit 29 of CR0)  — When the NW and CD flags are clear, write-back (for Pentium 4, 
Intel Xeon, P6 family, and Pentium processors) or write-through (for Intel486 processors) is enabled for 
writes that hit the cache and invalidation cycles are enabled. See Table 12-5 for detailed information about 
the effect of the NW flag on caching fo r other settings of the CD and NW flags.
CR0.AM
Alignment Mask (bit 18 of CR0)  — Enables automatic alignment checking when set; disables alignment 
checking when clear. Alignment checking is performed only when the AM flag is set, the AC flag in the 
EFLAGS register is set, CPL is 3, and the processor is operating in either protected or virtual-8086 mode.
CR0.WP
Write Protect (bit 16 of CR0)  — When set, inhibits supervisor-level  procedures from writing into read-
only pages; when clear, allows supervisor-level proced ures to write into read-only pages (regardless of the 
U/S bit setting; see Section 4.1.3 and Section 4.6). This flag facilitates implementation of the copy-on-
write method of creating a new process (forking) used by operating systems such as UNIX. This flag must 
be set before software can set CR4.CET, and it cannot be cleared as long as CR4.CET = 1 (see below).
CR0.NE
Numeric Error (bit 5 of CR0)  — Enables the native (internal) mechanism for reporting x87 FPU errors 
when set; enables the PC-style x87 FPU error reportin g mechanism when clear. When the NE flag is clear 
and the IGNNE# input is asserted, x87 FPU errors are ignored. When the NE flag is clear and the IGNNE# 
input is deasserted, an unmasked x87 FPU error causes  the processor to assert the FERR# pin to generate 
an external interrupt and to stop instruction exec ution immediately before executing the next waiting 
floating-point instruction or WAIT/FWAIT instruction. 
The FERR# pin is intended to drive an input to an external interrupt controller (the FERR# pin emulates the 
ERROR# pin of the Intel 287 and Intel 387 DX math coprocessors). The NE flag, IGNNE# pin, and FERR# 
pin are used with external logic to implement PC-style error reporting. Using FERR# and IGNNE# to handle 
floating-point exceptions is deprecated by modern oper ating systems; this non-native approach also limits 
newer processors to operate with one logical processor active.
See also: Section 8.7, “Handling x87 FPU Exceptions in Software,” in Chapter 8, “Programming with the 
x87 FPU,” and Appendix A, “EFLAGS Cross-Reference,” in the Intel® 64 and IA-32 Architectures Software 
CR0.ET
Extension Type (bit 4 of CR0)  — Reserved in the Pentium 4, Intel Xeon, P6 family, and Pentium proces-
sors. In the Pentium 4, Intel Xeon, and P6 family proce ssors, this flag is hardcoded to 1. In the Intel386 
and Intel486 processors, this flag indicates support of Intel 387 DX math coprocessor instructions when 
set.
CR0.TS
Task Switched (bit 3 of CR0)  — Allows the saving of the x 87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 
context on a task switch to be delayed until an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction is 2-16 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
actually executed by the new task. The processor sets this flag on every task switch and tests it when 
executing x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
•If the TS flag is set and the EM flag (bit 2 of CR0)  is clear, a device-not-available exception (#NM) is 
raised prior to the execution of any x87 FPU/MMX/ SSE/SSE2/SSE3/SSSE3/SSE4 instruction; with the 
exception of PAUSE, PREFETCH h, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32, and POPCNT. 
See the paragraph below for the special case of the WAIT/FWAIT instructions.
•If the TS flag is set and the MP flag (bit 1 of CR0) and EM flag are clear, an #NM exception is not raised 
prior to the execution of an x87 FPU WAIT/FWAIT instruction.
•If the EM flag is set, the setting of the TS  flag has no effect on the execution of x87 
FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
Table 2-2 shows the actions taken when the processor encounters an x87 FPU instruction based on the 
settings of the TS, EM, and MP flags. Table 13-1 an d 14-1 show the actions taken when the processor 
encounters an MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction.
The processor does not automatically save the contex t of the x87 FPU, XMM, and MXCSR registers on a 
task switch. Instead, it sets the TS flag, which causes the processor to raise an #NM exception whenever it 
encounters an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction in the instruction stream for the 
new task (with the exception of the instructions listed above). 
The fault handler for the #NM exception can then be used to clear the TS flag (with the CLTS instruction) 
and save the context of the x87 FPU, XMM, and MXCS R registers. If the task never encounters an x87 
FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction, the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 
context is never saved.
CR0.EM
Emulation (bit 2 of CR0)  — Indicates that the processor does not have an internal or external x87 FPU when set; 
indicates an x87 FPU is present when clear.  This flag also affects the execution of 
MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
When the EM flag is set, execution of an x87 FPU instruction generates a device-not-available exception 
(#NM). This flag must be set when the processor does not have an internal x87 FPU or is not connected to 
an external math coprocessor. Setting this flag forces all floating-point instructions to be handled by soft-ware emulation. Table 10-3 shows the recommended setti ng of this flag, depending on the IA-32 processor 
and x87 FPU or math coprocessor present in the system . Table 2-2 shows the interaction of the EM, MP, and 
TS flags.
Also, when the EM flag is set, execution of an MM X instruction causes an invalid-opcode exception (#UD) 
to be generated (see Table 13-1). Thus, if an IA-32 or  Intel 64 processor incorporates MMX technology, the 
EM flag must be set to 0 to enable execution of MMX instructions.
Similarly for SSE/SSE2/SSE3/SSSE3/SSE4 extensions, when the EM flag is set, execution of most 
SSE/SSE2/SSE3/SSSE3/SSE4 instructions causes an invalid opcode exception (#UD) to be generated (see Table 2-2.  Action Taken By x87 FPU Instructio ns for Different Combinations of EM, MP, and TS
CR0 Flags x87 FPU Instruction Type
EM MP TS Floating-Point WAIT/FWAIT
0 0 0 Execute Execute.
001 # N M  E x c e p t i o n E x e c u t e .
0 1 0 Execute Execute.0 1 1 #NM Exception #NM exception.
100 # N M  E x c e p t i o n E x e c u t e .
101 # N M  E x c e p t i o n E x e c u t e .110 # N M  E x c e p t i o n E x e c u t e .
1 1 1 #NM Exception #NM exception.Vol. 3A 2-17SYSTEM ARCHITECTURE OVERVIEW
Table 14-1). If an IA-32 or Intel 64 processor incorporates the SSE/SSE2/SSE3/SSSE3/SSE4 extensions, 
the EM flag must be set to 0 to enable execution of these extensions. SSE/SSE2/SSE3/SSSE3/SSE4 instructions not affected by the EM flag include: PAUSE, PREFETCH h, SFENCE, LFENCE, MFENCE, MOVNTI, 
CLFLUSH, CRC32, and POPCNT.
CR0.MP
Monitor Coprocessor (bit 1 of CR0)  — Controls the interaction of the WAIT (or FWAIT) instruction with 
the TS flag (bit 3 of CR0). If the MP flag is set, a WAIT instruction generates a device-not-available exception 
(#NM) if the TS flag is also set. If the MP flag is clear, the WAIT instruct ion ignores the setting of the TS flag.

CR0.MP
(#NM) if the TS flag is also set. If the MP flag is clear, the WAIT instruct ion ignores the setting of the TS flag. 
Table 10-3 shows the recommended se tting of this flag, depending on th e IA-32 processor and x87 FPU or 
math coprocessor present in the system. Table 2-2 shows the interaction of the MP, EM, and TS flags.
CR0.PE
Protection Enable (bit 0 of CR0)  — Enables protected mode when set; enables real-address mode when 
clear. This flag does not enable paging directly. It only enables segment-level pr otection. To enable paging, 
both the PE and PG flags must be set. 
See also: Section 10.9, “Mode Switching.”
CR3.PCD 
Page-level Cache Disable (bit 4 of CR3)  — Controls the memory type used to access the first paging 
structure of the current paging-structure hierarchy. Se e Section 4.9, “Paging and Memory Typing.” This bit 
is not used if paging is disabled, with PAE paging, or with 4-level paging
2 or 5-level paging if CR4.PCIDE=1.
CR3.PWT
Page-level Write-Through (bit 3 of CR3)  — Controls the memory type used to access the first paging 
is not used if paging is disabled, with PAE paging, or  with 4-level paging or 5-level paging if CR4.PCIDE=1.
CR4.VME
Virtual-8086 Mode Extensions (bit 0 of CR4) — Enables interrupt- and exception-handling extensions 
in virtual-8086 mode when set; disables the extensions  when clear. Use of the virtual mode extensions can 
improve the performance of virtual-8086 applications by eliminating the overhe ad of calling the virtual-
8086 monitor to handle interrupts and exceptions that occur while executing an 8086 program and, 
instead, redirecting the interrupts and exceptions back  to the 8086 program’s handlers. It also provides 
hardware support for a virtual interru pt flag (VIF) to improve reliability  of running 8086 pr ograms in multi-
tasking and multiple-processor environments.
See also: Section 21.3, “Interrupt and Exception Handling in Virtual-8086 Mode.”
CR4.PVI
Protected-Mode Virtual In terrupts (bit 1 of CR4)  — Enables hardware support for a virtual interrupt 
flag (VIF) in protected mode when set; disables the VIF flag in protected mode when clear. 
See also: Section 21.4, “Protected-Mode Virtual Interrupts.”
CR4.TSD
Time Stamp Disable (bit 2 of CR4)  — Restricts the execution of the RDTSC instruction to procedures 
running at privilege level 0 when set; allows RDTSC in struction to be executed at  any privilege level when 
clear. This bit also applies to the RDTSCP inst ruction if supported (if CPUID.80000001H:EDX[27] = 1).
CR4.DE
Debugging Extensions (bit 3 of CR4)  — References to debug registers DR4 and DR5 cause an unde-
fined opcode (#UD) exception to be generated when set;  when clear, processor aliases references to regis-
ters DR4 and DR5 for compatibility with software written to run on earlier IA-32 processors. 
See also: Section 18.2.2, “Debug Registers DR4 and DR5.”
CR4.PSE
Page Size Extensions (bit 4 of CR4)  — Enables 4-MByte pages with 32-bit paging when set; restricts 
32-bit paging to pages of 4 KBytes when clear.
See also: Section 4.3, “32-Bit Paging.”
2. Earlier versions of this manual used the term “IA-32e paging” to identify 4-level paging.2-18 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
CR4.PAE
Physical Address Extension (bit 5 of CR4)  — When set, enables paging to produce physical addresses 
with more than 32 bits. When clear, restricts physical addresses to 32 bits. PAE must be set before entering 
IA-32e mode.
CR4.MCE
Machine-Check Enable (bit 6 of CR4)  — Enables the machine-check exception when set; disables the 
machine-check exception when clear.
See also: Chapter 16, “Machine-Check Architecture.”
CR4.PGE
Page Global Enable (bit 7 of CR4)  — (Introduced in the P6 family pr ocessors.) Enables the global page 
feature when set; disables the global page feature wh en clear. The global page feature allows frequently 
used or shared pages to be marked as global to all us ers (done with the global flag, bit 8, in a page-direc-
tory-pointer-table entry, a page-directory entry, or a page-table entry). Global pages are not flushed from 
the translation-lookaside buffer (TLB) on a task switch or a write to register CR3.
When enabling the global page feature, paging must be  enabled (by setting the PG flag in control register 
CR0) before the PGE flag is set. Reversing this se quence may affect program correctness, and processor 
performance will be impacted. 
See also: Section 4.10, “Caching Translation Information.”
CR4.PCE
Performance-Monitoring Counter Enable (bit 8 of CR4)  — Enables execution of the RDPMC instruc-
tion for programs or procedures running at any protection level when set; RDPMC instruction can be 
executed only at protection level 0 when clear.
CR4.OSFXSR
Operating System Support for FXSAVE an d FXRSTOR instructions (bit 9 of CR4)  — When set, this 
flag: (1) indicates to software that the operating system supports the use of the FXSAVE and FXRSTOR 
instructions, (2) enables the FXSAVE and FXRSTOR inst ructions to save and restore the contents of the 
XMM and MXCSR registers along with the contents of the x87 FPU and MMX registers, and (3) enables the 
processor to execute SSE/SSE2/SSE3/SSSE3/SSE4 in structions, with the exception of the PAUSE, 
PREFETCH h, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32, and POPCNT. 
If this flag is clear, the FXSAVE and FXRSTOR instruct ions will save and restore the contents of the x87 FPU 
and MMX registers, but they may not save and restore the contents of the XMM and MXCSR registers. Also, 
the processor will generate an invalid opcode exception (#UD) if it attempts to execute any 
SSE/SSE2/SSE3 instruction, with the exception of PAUSE, PREFETCH h, SFENCE, LFENCE, MFENCE, 
MOVNTI, CLFLUSH, CRC32, and POPCNT. The operating sy stem or executive must explicitly set this flag.
NOTE
CPUID feature flag FXSR indicates availability of the FXSAVE/FXRSTOR instructions. The OSFXSR 
bit provides operating system software with a means of enabling FXSAVE/FXRSTOR to save/restore 
the contents of the X87 FPU, XMM, and MXCSR regi sters. Consequently OSFXSR bit indicates that 
the operating system provides context sw itch support for SSE/SSE2/SSE3/SSSE3/SSE4.
CR4.OSXMMEXCPT
Operating System Support for Unmasked SIMD Floating-Point  Exceptions (bit 10 of CR4)  — 
When set, indicates that the operating system supports the handling of unmasked SIMD floating-point 
exceptions through an exception handler that is invoked when a SIMD floating-point exception (#XM) is generated. SIMD floating-p oint exceptions are only generated by SSE/SSE2/SSE3/SSE4.1 SIMD floating-
point instructions. 
The operating system or executive must explicitly set th is flag. If this flag is not set, the processor will 
generate an invalid opcode exception (#UD) whenever  it detects an unmasked SIMD floating-point excep-
tion.Vol. 3A 2-19SYSTEM ARCHITECTURE OVERVIEW
CR4.UMIP
User-Mode Instruction Prev ention (bit 11 of CR4)  — When set, the following instructions cannot be 
executed if CPL > 0: SGDT, SIDT, SLDT, SMSW, and STR. An attempt at such execution causes a general-
CR4.LA57
57-bit linear addresses (bit 12 of CR4)  — When set in IA-32e mode, the processor uses 5-level paging 
to translate 57-bit linear addresses. When clear in IA-32e mode, the processor uses 4-level paging to translate 48-bit linear addresses. This bit cannot be modified in IA-32e mode.
CR4.VMXE
VMX-Enable Bit (bit 13 of CR4)  — Enables VMX operation when set. See Chapter 24, “Introduction to 
Virtual Machine Extensions.”
CR4.SMXE
SMX-Enable Bit (bit 14 of CR4)  — Enables SMX operation when set. See Chapter 7, “Safer Mode Exten-
sions Reference,” of Intel
® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 2D.
CR4.FSGSBASE
FSGSBASE-Enable Bit (bit 16 of CR4)  — Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, 
and WRGSBASE.
CR4.PCIDE
PCID-Enable Bit (bit 17 of CR4)  — Enables process-context identifiers (PCIDs) when set. See Section 
4.10.1, “Process-Context Identifiers (PCIDs).” Applies only in IA-32e mode (if IA32_EFER.LMA = 1).
CR4.OSXSAVE
XSAVE and Processor Extended St ates-Enable Bit (bit 18 of CR4)  — When set, this flag: (1) indi-
cates (via CPUID.01H:ECX.OSXSAVE[bit 27]) that the operating system supports the use of the XGETBV, 
XSAVE, and XRSTOR instructions by general software; (2) enables the XSAVE and XRSTOR instructions to 
save and restore the x87 FPU state (including MMX registers), the SSE state (XMM registers and MXCSR), 
along with other processor extended states enabled in  XCR0; (3) enables the processor to execute XGETBV 
and XSETBV instructions in order to read and wr ite XCR0. See Section 2.6 and Chapter 14, “System 
Programming for Instruction Set Extensions and Processor Extended States.”
CR4.KL
Key-Locker-Enable Bit (bit 19 of CR4)  — When set, the LOADIWKEY instruction is enabled; in addition,

CR4.KL
Key-Locker-Enable Bit (bit 19 of CR4)  — When set, the LOADIWKEY instruction is enabled; in addition, 
if support for the AES Key Locker instructions has been activated by system firmware, CPUID.19H:EBX.AESKLE[bit 0] is enumerated as 1 and the AES Key Locker instructions are enabled.
3 
When clear, CPUID.19H:EBX.AESKLE[bit 0] is enumerated  as 0 and execution of any Key Locker instruction 
CR4.SMEP
SMEP-Enable Bit (bit 20 of CR4)  — Enables supervisor-mode execution prevention (SMEP) when set. 
See Section 4.6, “Access Rights.”
CR4.SMAP
SMAP-Enable Bit (bit 21 of CR4)  — Enables supervisor-mode access prevention (SMAP) when set. See 
Section 4.6, “Access Rights.”
CR4.PKE
Enable protection keys for user-mode pages (bit 22 of CR4)  — 4-level paging and 5-level paging 
associate each user-mode linear address with a protec tion key. When set, this flag indicates (via 
CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4]) that the operating syst em supports use of the PKRU 
register to specify, for each protection key, whether user-mode linear addresses with that protection key 
can be read or written. This bit also enables access  to the PKRU register us ing the RDPKRU and WRPKRU 
3. Software can check CPUID.19H:EBX.AESKLE[bit 0] after setting CR 4.KL to determine whether the AES Key Locker instructions have  
been enabled. Note that some processors may allow enabling of those instruct ions without activation by  system firmware. Some 
processors may not support use of the AES Key Locker instructions in system-management mode (SMM). Those processors enumer-
ate CPUID.19H:EBX.AESKLE[bit 0] as 0 in SMM regardless of the setting of CR4.KL.2-20 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
CR4.CET
Control-flow Enforcement Te chnology (bit 23 of CR4)  — Enables control-flow enforcement tech-
nology when set. See Chapter 17, “Control-f low Enforcement Technology (CET)‚” of the IA-32 Intel® Archi-
tecture Software Developer’s Manual, Volume 1 . This flag can be set only if CR0.WP is set, and it must be 
clear before CR0.WP can be cleared (see below).
CR4.PKS
Enable protection keys for supervisor-mode pages (bit 24 of CR4)  — 4-level paging and 5-level 
paging associate each supervisor-mode linear address with  a protection key. When set, this flag allows use 
of the IA32_PKRS MSR to specify, for each protection  key, whether supervisor-mode linear addresses with 
that protection key can be read or written.
CR4.UINTR
User Interrupts Enable Bit (bit 25 of CR4)  — Enables user interrupts when set, including user-interrupt 
delivery, user-interrupt notification identification, and the user-interrupt instructions.
CR8.TPL
Task Priority Level (bit 3:0 of CR8)  — This sets the threshold value corresponding to the highest-
priority interrupt to be blocked. A value of 0 means all interrupts are enabled. This field is available in 64-
bit mode. A value of 15 means all interrupts will be disabled.
2.5.1 CPUID Qualification of Control Register Flags
Not all flags in control register CR4 are implemented on a ll processors. With the exception of the PCE flag, they can 
be qualified with the CPUID instruction to determine if they are implemented on the processor before they are 
used. 
The CR8 register is available on processors that support Intel 64 architecture.
2.6 EXTENDED CONTROL REGISTERS (INCLUDING XCR0)
If CPUID.01H:ECX.XSAVE[bit 26] is 1,  the processor supports one or more extended control registers  (XCRs). 
Currently, the only such register defined is XCR0. This register specifies the set of processor state components for 
which the operating system provides context management , e.g., x87 FPU state, SSE state, AVX state. The OS 
programs XCR0 to reflect the features for which it provides context management.Vol. 3A 2-21SYSTEM ARCHITECTURE OVERVIEW
Software can access XCR0 only if CR4.OSXSAVE[ bit 18] = 1. (This bit is also readable as 
CPUID.01H:ECX.OSXSAVE[bit 27].) Software can use CPUID le af function 0DH to enumerate the bits in XCR0 that 
the processor supports (see CPUID instruction in Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A). Each supported state component is represen ted by a bit in XCR0. System software enables state 
components by loading an appropriate bit mask value into XCR0 using the XSETBV instruction.
As each bit in XCR0 (except bit 63) corresponds to a pr ocessor state component, XCR0 thus provides support for 
up to 63 sets of processor state components. Bit 63 of XCR0  is reserved for future expansion and will not represent 
a processor state component.
Currently, XCR0 defines support for the following state components:
•XCR0.X87 (bit 0): This bit 0 must be 1. An atte mpt to write 0 to this bit causes a #GP exception.
•XCR0.SSE (bit 1): If 1, the XSAVE feature set can be used to manage MXCSR and the XMM registers (XMM0-
XMM15 in 64-bit mode; otherwise XMM0-XMM7). 
•XCR0.AVX (bit 2): If 1, Intel AVX instructions can be executed and the XSAVE feature set can be used to 
manage the upper halves of the YMM registers (YMM0-YMM15 in 64-bit mode; otherwise YMM0-YMM7).
•XCR0.BNDREG (bit 3): If 1, Intel MPX instructions can be executed and the XSAVE feature set can be used to 
manage the bounds registers BND0–BND3. 
•XCR0.BNDCSR (bit 4): If 1, Intel MPX instructions can be executed and the XSAVE feature set can be used to 
manage the BNDCFGU and BNDSTATUS registers.
•XCR0.opmask (bit 5): If 1, Intel AVX-512 instructions can be executed and the XSAVE feature set can be used 
to manage the opmask registers k0–k7.
•XCR0.ZMM_Hi256 (bit 6): If 1, Intel AVX-512 instructio ns can be executed and the XSAVE feature set can be 
used to manage the upper halves of the lower ZMM registers (ZMM0-ZMM15 in 64-bit mode; otherwise ZMM0-
ZMM7).
•XCR0.Hi16_ZMM (bit 7): If 1, Intel AVX-512 instructio ns can be executed and the XSAVE feature set can be 
used to manage the upper ZMM register s (ZMM16-ZMM31, only in 64-bit mode).
•XCR0.PKRU (bit 9): If 1, the XSAVE feature set can be used to manage the PKRU register (see Section 2.7).
•XCR0.TILECFG (bit 17): If 1, and if XCR0.TILEDATA is also 1, Intel AMX instructions can be executed and the 
XSAVE feature set can be used to manage TILECFG.Figure 2-8.  XCR0118    17                                                    10     9      8      7      6      5      4      3      2      1      0 63
Reserved for XCR0 bit vector expansion
Reserved / Future processor extended statesTILEDATA stateTILECONFIG statePKRU stateHi16_ZMM stateZMM_Hi256 stateOpmask stateBNDCSR stateBNDREG stateAVX stateSSE state
X87 FPU/MMX state (must be 1)
Reserved (must be 0)2-22 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
•XCR0.TILEDATA (bit 18): If 1, and if XCR0.TILECFG is al so 1, Intel AMX instructions can be executed and the 
XSAVE feature set can be used to manage TILEDATA.
An attempt to use XSETBV to write to XCR0 results in gene ral-protection exceptions (#GP) if it would do any of the 
•Set a bit reserved in XCR0 for a given processor (as dete rmined by the contents of EAX and EDX after executing 
CPUID with EAX=0DH, ECX= 0H).
•Clear XCR0.x87.
•Clear XCR0.SSE and set XCR0.AVX.
•Clear XCR0.AVX and set any of XCR0.opmask, XCR0.ZMM_Hi256, or XCR0.Hi16_ZMM.
•Set either XCR0.BNDREG or XCR0.B NDCSR while not setting the other.
•Set any of XCR0.opmask, XCR0.ZMM_Hi256, and XCR0.Hi16_ZMM while not setting all of them.
•Set either XCR0.TILECFG or XCR0.T ILEDATA while not setting the other.
After reset, all bits (except bit 0) in XCR0  are cleared to zero; XCR0[0] is set to 1.
2.7 PROTECTION-KEY RIGHTS RE GISTERS (PKRU AND IA32_PKRS)
Processors may support either or both of two protection-key rights registers: PKRU for user-mode pages and the 
IA32_PKRS MSR (MSR index 6E1H) for supervisor-mode pages.  4-level paging and 5-level paging associate a 4-bit 
protection key  with each page. The protection-key rights registers determine accessibility based on a page’s 
protection key.
If CPUID.(EAX=07H,ECX=0H):E CX.PKU [bit 3] = 1, the processor supports the protection-key feature for user-
mode pages. When CR4.PKE = 1, software can use the protection-key rights re gister for user pages (PKRU) 
to specify the access rights for user-mode pages for each protection key.
If CPUID.(EAX=07H,ECX=0H):E CX.PKS [bit 31] = 1, the processor supports the protection-key feature for super-
visor-mode pages. When CR4.PKS = 1, software can use the protection-key rights re gister for supervisor 
pages  (the IA32_PKRS MSR) to specify the access rights for supervisor-mode pages for each protection key.
The format of each protection-k ey rights register is given in Figure 2-9. Each contains 16 pairs of disable controls 
to prevent data accesses to linear addresses (user-mode or supervisor-mode, depending on the register) based on 
their protection keys. Each protection key i (0≤ i≤ 15) is associated with two bits in each protection-key rights 
register:
•Bit 2i, shown as “AD i” (access disable): if set, the processor prevents any data accesses to linear addresses 
(user-mode or supervisor-mode, depending on the register) with protection key i.

register:
•Bit 2i+1, shown as “WD i” (write disable): if set, the processor prevents write accesses to linear addresses 
(Bits 63:32 of the IA32_PKRS MSR are reserved and must be zero.)See Section 4.6.2, “Protection Keys,” for details of how the processor uses the protection-key rights registers to 
control accesses to linear addresses.
Software can read and write PKRU using the RDPKRU an d WRPKRU instructions. The IA32_PKRS MSR can be read 
and written with the RDMSR and WRMSR instructions. Writ es to the IA32_PKRS MSR using WRMSR are not serial-
izing.Figure 2-9.  Format of Prot ection-Key Rights RegistersA31 987 6543 210 14 1817 20 16 15 22 21 19 30 29 28 27 25 24 23 26 Bit Position 10111213
DW
D0A
D1W
D10A
DW
D2A
D3W
D32A
DW
D4A
D5W
D54A
DW
D6A
D7W
D76A
DW
D8A
D9W
D98A
DW
D
10A
D
11W
D
11 10A
DW
D
12A
D
13W
D
13 12A
DW
D
14A
D
15W
D
14 15Vol. 3A 2-23SYSTEM ARCHITECTURE OVERVIEW
2.8 SYSTEM INSTRUCTION SUMMARY
System instructions handle system-level functions such  as loading system registers, managing the cache, 
managing interrupts, or setting up the debug registers. Ma ny of these instructions can be executed only by oper-
ating-system or executive procedures (that is, procedures running at privilege level 0). Others can be executed at 
any privilege level and are thus av ailable to application programs. 
Table 2-3 lists the system instructions and indicates whether they are available and useful for application 
programs. These instructions are described in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volumes 2A, 2B, 2C, & 2D.
Table 2-3.  Summary of System Instructions
Instruction DescriptionUseful to
Application?Protected from
Application?
LLDT Load LDT Register No Yes
SLDT Store LDT Register No If CR4.UMIP = 1
LGDT Load GDT Register No YesSGDT Store GDT Register No If CR4.UMIP = 1LTR Load Task Register No Yes
STR Store Task Register No If CR4.UMIP = 1
LIDT Load IDT Register No YesSIDT Store IDT Register No If CR4.UMIP = 1
MOV CR n Load and store control registers No Yes
SMSW Store MSW Yes If CR4.UMIP = 1LMSW Load MSW No Yes
CLTS Clear TS flag in CR0 No Yes
ARPL Adjust RPL Yes
1, 5No
LAR Load Access Rights Yes No
LSL Load Segment Limit Yes No
VERR Verify for Reading Yes NoVERW Verify for Writing Yes No
MOV DR n Load and store debug registers No Yes
INVD Invalidate cache,  no writeback No Yes
WBINVD Invalidate cache, with writeback No Yes
INVLPG Invalidate TLB entry No Yes
HLT Halt Processor No YesLOCK (Prefix) Bus Lock Yes No
RSM Return from system management mode No Yes
RDMSR
3Read Model-Specific Registers No Yes
WRMSR3Write Model-Specific Registers No Yes
RDPMC4Read Performance-Monitoring Counter Yes Yes2
RDTSC3Read Time-Stamp Counter Yes Yes2
RDTSCP7Read Serialized Time-Stamp Counter Yes Yes2
XGETBV Return the state of XCR0 Yes No
XSETBV Enable one or more processor extended states No6Yes2-24 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
2.8.1 Loading and Storing System Registers
The GDTR, LDTR, IDTR, and TR registers each have a load and store instruction for loading data into and storing 
data from the register:
•LGDT (Load GDTR Register)  — Loads the GDT base address and limit from memory into the GDTR register.
•SGDT (Store GDTR Register) — Stores the GDT base address and limit from the GDTR register into memory.
•LIDT (Load IDTR Register) — Loads the IDT base address and limit from memory into the IDTR register.
•SIDT (Store IDTR Register) — Stores the IDT base address and limit from the IDTR register into memory.
•LLDT (Load LDTR Register) — Loads the LDT segment selector and segment descriptor from memory into 
the LDTR. (The segment selector operand can al so be located in a general-purpose register.)
•SLDT (Store LDTR Register)  — Stores the LDT segment selector from the LDTR register into memory or a 
general-purpose register.
•LTR (Load Task Register)  — Loads segment selector and segment descriptor for a TSS from memory into the 
task register. (The segment selector operand can also be located in a general-purpose register.)
•STR (Store Task Register) — Stores the segment selector for the current task TSS from the task register into 
memory or a general-purpose register.
The LMSW (load machine status word) and SMSW (store machine status word) instructions operate on bits 0 
through 15 of control register CR0. These instructions are provided for compatibility with the 16-bit Intel 286 
processor. Programs written to run on 32-bit IA-32 processors should not use these instructions. Instead, they 
should access the control register CR0 using the MOV CR instruction.
The CLTS (clear TS flag in CR0) instruction is provided  for use in handling a device-not-available exception (#NM) 
that occurs when the processor attempts to execute a floa ting-point instruction when the TS flag is set. This 
instruction allows the TS flag to be  cleared after the x87 FPU context has been saved, preventing further #NM 
exceptions. See Section 2.5, “Control Regist ers,” for more information on the TS flag.
The control registers (CR0, CR1, CR2, CR3, CR4, and CR8)  are loaded using the MOV instruction. The instruction 
loads a control register from a general-purpose register or stores the content of a control register in a general-
2.8.2 Verifying of Access Privileges
The processor provides several instruct ions for examining segment selectors and segment descriptors to determine 
if access to their associated segments is allowed. These instructions duplicate some of the automatic access rights 
and type checking done by the processor, thus allowing operating-system or executive software to prevent excep-
tions from being generated. 
The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level) of a segment selector to match that of 
the program or procedure that supplied the segment sele ctor. See Section 5.10.4, “Checking Caller Access Privi-
leges (ARPL Instruction),” for a detailed explanation of the function and use of this instruction. Note that ARPL is 
not supported in 64-bit mode.NOTES:
1. Useful to application programs running at a CPL of 1 or 2.
2. The TSD and PCE flags in control register CR4 control access to these instructions by application programs running at a CPL o f 3.
3. These instructions were introduced into the IA-32 Architecture with the Pentium processor.
4. This instruction was introduced into the IA-32 Architecture with the Pentium Pro processor and the Pentium processor with MMX technol-
ogy.
5. This instruction is not supported in 64-bit mode.6. Application uses XGETBV to query which set of processor extended states are enabled.
7. RDTSCP is introduced in Intel Core i7 processor.Table 2-3.  Summary of Sy stem Instructions (Contd.)
Application?Vol. 3A 2-25SYSTEM ARCHITECTURE OVERVIEW
The LAR (load access rights) instruction verifies the acce ssibility of a specified segment and loads access rights 
information from the segment’s segment descriptor into a general-purpose register. Software can then examine the access rights to determine if the segment type is compatible with its intended use. See Section 5.10.1, 
“Checking Access Rights (LAR Instruction),” for a detailed explanation of the function and use of this instruction.
The LSL (load segment limit) instruction verifies the a ccessibility of a specified segment and loads the segment 
limit from the segment’s segment descriptor into a gene ral-purpose register. Software can then compare the 
segment limit with an offset into the segment to determin e whether the offset lies within the segment. See Section 
5.10.3, “Checking That the Pointer Offset Is Within Limits (LSL Instruction),” for a detailed explanation of the func-
tion and use of this instruction.
The VERR (verify for reading) and VERW (verify for writing) in structions verify if a selected segment is readable or 
writable, respectively, at a given CPL. See Section 5.10 .2, “Checking Read/Write Rights (VERR and VERW Instruc-
tions),” for a detailed explanation of the function and use of these instructions.
2.8.3 Loading and Storing Debug Registers
Internal debugging facilities in the processor are contro lled by a set of 8 debug registers (DR0-DR7). The MOV 
instruction allows setup data to be load ed to and stored from these registers.
On processors that support Intel 64 architecture, debu g registers DR0-DR7 are 64 bits. In 32-bit modes and 
compatibility mode, writes to a debug register fill the uppe r 32 bits with zeros. Reads return the lower 32 bits. In 
64-bit mode, the upper 32 bits of DR6-DR7 are reserved and must be written with zeros.  Writing one to any of the 
upper 32 bits causes an exception, #GP(0).
In 64-bit mode, MOV DRn instructions read or write all 64 bits of a debug register (operand-size prefixes are 
ignored). All 64 bits of DR0-DR3 are writable by software. However, MOV DRn instructions do not check that

ignored). All 64 bits of DR0-DR3 are writable by software. However, MOV DRn instructions do not check that 
addresses written to DR0-DR3 are in the limits of the impl ementation. Address matching is supported only on valid 
addresses generated by the processor implementation.
2.8.4 Invalidating Caches and TLBs
The processor provides several instructions for use in exp licitly invalidating its caches  and TLB entries. The INVD 
(invalidate cache with no writeback) instruction invalidates all data and instruction entries in the internal caches 
and sends a signal to the external caches indi cating that they should also be invalidated.
The WBINVD (invalidate cache with writeback) instruction performs the same function as the INVD instruction, 
except that it writes back modified lines in its internal caches to memory before it invalidates the caches. After 
invalidating the caches local to the executing logical processor or processor core, WBINVD signals caches higher in the cache hierarchy (caches shared with the invalidating logi cal processor or core) to write back any data they have 
in modified state at the time of instruction execution and to invalidate their contents. 
Note, non-shared caches may not be written back nor invalidat ed. In Figure 2-10 below, if code executing on either 
LP0 or LP1 were to execute a WBINVD, th e shared L1 and L2 for LP0/LP1 will be written back and invalidated as will 
the shared L3. However, the L1 and L2 caches not shared with LP0 and LP1 will not be written back nor invalidated.2-26 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
The INVLPG (invalidate TLB entry) instruction invalidates (flushes) the TLB entry for a specified page.
2.8.5 Controlling the Processor
The HLT (halt processor) instruction stops the processor until an enabled interrupt (such as NMI or SMI, which are 
normally enabled), a debug exception, the BINIT# signal, the INIT# signal, or  the RESET# signal is received. The 
processor generates a special bus cycle to indicate that the halt mode has been entered. 
Hardware may respond to this signal in a number of ways . An indicator light on the front panel may be turned on. 
An NMI interrupt for recording diagnostic information may be generated. Reset initialization may be invoked (note 
that the BINIT# pin was introduced with the Pentium Pro processor). If any non-wake events are pending during 
shutdown, they will be handled after the wake event from  shutdown is processed (for example, A20M# interrupts).
The LOCK prefix invokes a locked (atomic) read-modify- write operation when modifying a memory operand. This 
mechanism is used to allow reliable communications betw een processors in multiprocessor systems, as described 
below:
•In the Pentium processor and earlier IA-32 processors, the LOCK prefix causes the processor to assert the 
LOCK# signal during the instruction. This always causes an explicit bus lock to occur. 
•In the Pentium 4, Intel Xeon, and P6 family processors, th e locking operation is handled with either a cache lock 
or bus lock. If a memory access is cacheable and affect s only a single cache line, a cache lock is invoked and 
the system bus and the actual memory location in syst em memory are not locked during the operation. Here, 
other Pentium 4, Intel Xeon, or P6 family processors on the bus write-back any modified data and invalidate 
their caches as necessary to maintain system memory coherency. If the memory access is not cacheable 
and/or it crosses a cache line boundary, the processor’ s LOCK# signal is asserted and the processor does not 
respond to requests for bus control during the locked operation.
The RSM (return from SMM) instruction restores the processo r (from a context dump) to the state it was in prior to 
a system management mode (SMM) interrupt.
2.8.6 Reading Performance-Moni toring and Time-Stamp Counters
The RDPMC (read performance-monitoring counter) and RDTSC (read time-stamp counter) instructions allow 
application programs to read the processor’s performa nce-monitoring and time-stamp counters, respectively. 
Processors based on Intel NetBurst® microarchitecture have eighteen 40-bit performance-monitoring counters; P6 
family processors have two 40-bit counters. Intel Atom® processors and most of the processors based on the Intel 
Core microarchitecture support two types of performanc e monitoring counters: programmable performance coun-
ters similar to those available in the P6 family, and three fixed-function performance monitoring counters. Details Figure 2-10.  WBINVD Invalidation of Shared and Non-Shared Cache HierarchyLogical Processors
L1 & L2 CacheLP0 LP5
QPILP1 LP2 LP3 LP4 LP6 LP7
L3 Cache
Uncore
DDR3Written back
Written back and InvalidatedNot Written back and 
not Invalidated
& InvalidatedVol. 3A 2-27SYSTEM ARCHITECTURE OVERVIEW
of programmable and fixed-function performance monitoring  counters for each processor generation are described 
in Chapter 20, “Performance Monitoring.”
The programmable performance counters can support counting  either the occurrence or duration of events. Events 
that can be monitored on programmable counters generally  are model specific (except for architectural perfor-
mance events enumerated by CPUID le af 0AH); they may include the number of instructions decoded, interrupts 
received, or the number of cache loads. Individual count ers can be set up to monitor different events. Use the 
system instruction WRMSR to set up values in one of the IA32_PERFEVTSELx MSR, in one of the 45 ESCRs and one 
of the 18 CCCR MSRs (for Pentium 4 and Intel Xeon proce ssors); or in the PerfEvtSel0 or the PerfEvtSel1 MSR (for 
the P6 family processors). The RDPMC instruction loads the current count from the selected counter into the 
EDX:EAX registers.
Fixed-function performance counters record only specific events that are defined at: https://perfmon-
events.intel.com/ , and the width/number of fixed-function counters are enumerated by CPUID leaf 0AH.
The time-stamp counter is a model-specific 64-bit counter that  is reset to zero each time the processor is reset. If 
not reset, the counter will increment ~9.5 x 1016 times per year when the processo r is operating at a clock rate 
of 3GHz. At this clock frequency, it would take ov er 190 years for the counter to wrap around. The RDTSC 
instruction loads the current count of the time-stamp counter into the EDX:EAX registers.
See Section 20.1, “Performance Monitoring Overview,” and Section 18.17, “Time-Stam p Counter,” for more infor-
mation about the performance monitoring and time-stamp counters.
The RDTSC instruction was introduced into the IA-32 arch itecture with the Pentium processor. The RDPMC instruc-
tion was introduced into the IA-32 architecture with the Pentium Pro processor and the Pentium processor with 
MMX technology. Earlier Pentium processors have two perfor mance-monitoring counters, but they can be read only 
with the RDMSR instruction, an d only at privilege level 0.
2.8.6.1  Reading Coun ters in 64-Bit Mode
In 64-bit mode, RDTSC operates the same as in protected mode. The count in the time-stamp counter is stored in 
EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32] cleared).
RDPMC requires an index to specify the offset of the pe rformance-monitoring counter. In 64-bit mode for Pentium 
4 or Intel Xeon processor families, the index is specifie d in ECX[30:0]. The current count of the performance-moni-
toring counter is stored in EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32] cleared).
2.8.7 Reading and Writing Model-Specific Registers
The RDMSR (read model-specific register) and WRMSR (w rite model-specific register) instructions allow a 
processor’s 64-bit model-specific registers (MSRs) to be read and written, respectively. The MSR to be read or 
written is specified by the value in the ECX register.
RDMSR reads the value from the specified MSR to the EDX: EAX registers; WRMSR writes the value in the EDX:EAX 
registers to the specified MSR. RDMSR and WRMSR were in troduced into the IA-32 architecture with the Pentium 
See Section 10.4, “Model-Specific Registers (MSRs),” for more information.
2.8.7.1  Reading and Writing Model- Specific Registers in 64-Bit Mode
RDMSR and WRMSR require an index to specify the address of  an MSR. In 64-bit mode, th e index is 32 bits; it is 
specified using ECX.
2.8.8 Enabling Processor Extended States
The XSETBV instruction is requ ired to enable OS support of individual processor extended states in XCR0 (see 
Section 2.6).2-28 Vol. 3ASYSTEM ARCHITECTURE OVERVIEWVol. 3A 3-1CHAPTER 3
PROTECTED-MODE MEMORY MANAGEMENT
This chapter describes the Intel 64 and IA-32 architec ture’s protected-mode memory management facilities, 
including the physical memory requirements, se gmentation mechanism, and paging mechanism.
See also: Chapter 5, “Protection‚” (for a description of  the processor’s protection mechanism) and Chapter 21, 
“8086 Emulation‚” (for a description of memory addressi ng protection in real-address and virtual-8086 modes).
3.1 MEMORY MANAGEMENT OVERVIEW

The memory management facilities of the IA-32 architectu re are divided into two parts: segmentation and paging. 
Segmentation provides a mechanism of isolating indivi dual code, data, and stack modules so that multiple 
programs (or tasks) can run on the same processor withou t interfering with one another. Paging provides a mech-
anism for implementing a conventional demand-paged, vi rtual-memory system where sections of a program’s 
execution environment are mapped into physical memory as  needed. Paging can also be used to provide isolation 
between multiple tasks. When operating in protecte d mode, some form of segmentation must be used. There is 
no mode bit to disable segmentation. The use of paging, however, is optional.
These two mechanisms (segmentation and paging) can be co nfigured to support simple single-program (or single-
task) systems, multitasking systems, or multip le-processor systems that used shared memory.
As shown in Figure 3-1, segmentation provides a mech anism for dividing the processor’s addressable memory 
space (called the linear address space ) into smaller protected address spaces called segments . Segments can 
be used to hold the code, data, and stack for a program or to hold system data structures (such as a TSS or LDT). 
If more than one program (or task) is running on a pr ocessor, each program can be assigned its own set of 
segments. The processor then enforces the boundaries between these segments and ensures that one program 
does not interfere with the execution of another program by writing into the other program’s segments. The 
segmentation mechanism also allows typing of segments so  that the operations that may be performed on a partic-
ular type of segment can be restricted.
All the segments in a system are contained in the processor’ s linear address space. To lo cate a byte in a particular 
segment, a logical address  (also called a far pointer) must be provided. A logical address consists of a segment 
selector and an offset. The segment selector is a unique iden tifier for a segment. Among other things it provides an 
offset into a descriptor table (such as the global descriptor table, GDT) to a data structure called a segment 
descriptor. Each segment has a segment descriptor, which sp ecifies the size of the segment, the access rights and 
privilege level for the segment, the se gment type, and the location of the first byte of the segment in the linear 
address space (called the base address of  the segment). The offset part of the logical address is added to the base 
address for the segment to locate a byte within the se gment. The base address plus the offset thus forms a linear 
address  in the processor’s linear address space.3-2 Vol. 3APROTECTED-MODE MEMORY MANAGEMENT
If paging is not used, the linear address space of the proc essor is mapped directly into the physical address space 
of processor. The physical address space is defined as the range of addresses that the processor can generate on its address bus.
Because multitasking computing systems commonly define a linear address space much larger than it is economi-
cally feasible to contain all at once in physical memory, some method of “virtualizing”  the linear address space is 
needed. This virtualization of the linear address spac e is handled through the pr ocessor’s paging mechanism.
Paging supports a “virtual memory” environment where a large linear address space is simulated with a small 
amount of physical memory (RAM and ROM) and some disk  storage. When using paging, each segment is divided 
into pages (typically 4 KBytes each in size), which are st ored either in physical memory or on the disk. The oper-
ating system or executive maintains a page directory and a set of page tables to keep track of the pages. When a 
program (or task) attempts to access an address location in the linear address space, the processor uses the page 
directory and page tables to translate the linear address into a physical address and then performs the requested 
operation (read or write) on the memory location. 
If the page being accessed is not currently in physical memory, the processor interrupts execution of the program 
(by generating a page-fault exception). The operating sy stem or executive then reads the page into physical 
memory from the disk and continues executing the program. 
When paging is implemented properly in the operating-sy stem or executive, the swapping of pages between phys-
ical memory and the disk is transparent to the correct ex ecution of a program. Even programs written for 16-bit IA-
32 processors can be paged (transparently) when they are run in virtual-8086 mode.
3.2 USING SEGMENTS
The segmentation mechanism supported by the IA-32 archit ecture can be used to implement a wide variety of 
system designs. These designs range from flat models th at make only minimal use of segmentation to protect Figure 3-1.  Segmentation and PagingGlobal Descriptor
Table (GDT)Linear Address
Space
Segment
Segment
DescriptorOffsetLogical Address
Segment
Base Address
PagePhy. Addr.Lin. Addr.Segment
Selector
Page Table
 EntryPhysical
Space
Entry(or Far Pointer)
Paging SegmentationAddress
PageVol. 3A 3-3PROTECTED-MODE MEMORY MANAGEMENT
programs to multi-segmented models that employ segmentation to create a robust operating environment in 
which multiple programs and tasks can be executed reliably.
The following sections give several examples of how se gmentation can be employed in a system to improve 
memory management performance and reliability.
3.2.1 Basic Flat Model
The simplest memory model for a system is the basic “fla t model,” in which the operating system and application 
programs have access to a continuous, unsegmented address sp ace. To the greatest extent possible, this basic flat 
model hides the segmentation mechanism of the architectu re from both the system designer and the application 
To implement a basic flat memory model with the IA-32 architecture, at least two segment descriptors must be 
created, one for referencing a code segment and one fo r referencing a data segment (see Figure 3-2). Both of 
these segments, however, are mapped to the entire linear address space: that is, both segment descriptors have 
the same base address value of 0 and the same segment limit of 4 GBytes. By setting the segment limit to 4 
GBytes, the segmentation mechanism is kept from generati ng exceptions for out of limit memory references, even 
if no physical memory resides at a particular address. RO M (EPROM) is generally located at the top of the physical 
address space, because the processor begins execution at  FFFF_FFF0H. RAM (DRAM) is placed at the bottom of the 
address space because the initial base address for th e DS data segment after reset initialization is 0.
3.2.2 Protected Flat Model
The protected flat model is similar to the basic flat model, except the segment limits are set to include only the 
range of addresses for which physical memory actually exists (see Figure 3-3). A general-protection exception 
(#GP) is then generated on any attempt to access nonexi stent memory. This model provides a minimum level of 
hardware protection against some kinds of program bugs.
Figure 3-2.  Flat ModelLinear Address Space
(or Physical Memory)
Data andFFFFFFFFHSegment
Limit Access
Base AddressRegisters
CS
SS
DS
ES
FS
GSCode
0Code- and Data-Segment
Descriptors
StackNot Present3-4 Vol. 3APROTECTED-MODE MEMORY MANAGEMENT
More complexity can be added to this protected flat mode l to provide more protection. For example, for the paging 
mechanism to provide isolation between user and supervisor  code and data, four segments need to be defined: 
code and data segments at privilege level 3 for the user, and code and data segments at privilege level 0 for the 
supervisor. Usually these segments all overlay each other and start at address 0 in the linear address space. This 
flat segmentation model along with a simple paging structure can protect th e operating system from applications, 
and by adding a separate paging structure for each task or process, it can also protect applications from each other. 
Similar designs are used by several popular multitasking operating systems.
3.2.3 Multi-Segment Model
A multi-segment model (such as the one shown in Figure 3-4)  uses the full capabilities of the segmentation mech-
anism to provide hardware enforced protection of code , data structures, and programs and tasks. Here, each 
program (or task) is given its own table of segment de scriptors and its own segments. The segments can be 
completely private to their assigned programs or shar ed among programs. Access to all segments and to the 
execution environments of individual programs ru nning on the system is controlled by hardware.Figure 3-3.  Protected Flat ModelLinear Address Space
CS

CS
ES
SS
DS
FS
GSCode
0Segment
Memory I/O
StackNot PresentVol. 3A 3-5PROTECTED-MODE MEMORY MANAGEMENT
Access checks can be used to protect not only against re ferencing an address outside the limit of a segment, but 
also against performing disallowed operations in certai n segments. For example, since code segments are desig-
nated as read-only segments, hardware can be used to pr event writes into code segments. The access rights infor-
mation created for segments can also be used to set up prot ection rings or levels. Protection levels can be used to 
protect operating-system procedures from unauthorized access by application programs.
3.2.4 Segmentation in IA-32e Mode
In IA-32e mode of Intel 64 architecture, the effects of segmentation depend on whether the processor is running 
in compatibility mode or 64-bit mode. In compatibility mode , segmentation functions just as it does using legacy 
16-bit or 32-bit protected mode semantics.
In 64-bit mode, segmentation is generally (but not comp letely) disabled, creating a flat 64-bit linear-address 
the effective address. The FS and GS segments are exce ptions. These segment registers (which hold the segment 
base) can be used as additional base registers in linear address calculations. They facilitate addressing local data and certain operating system data structures. 
Note that the processor does not perform segm ent limit checks at runtime in 64-bit mode.
3.2.5 Paging and Segmentation
Paging can be used with any of the segmentation models described in Figures 3-2, 3-3, and 3-4. The processor’s 
paging mechanism divides the linear address space (int o which segments are mapped) into pages (as shown in 
Figure 3-1). These linear-address-space pages are then mapped to pages in the physical address space. The 
paging mechanism offers several page-level protection fac ilities that can be used with or instead of the segment-Figure 3-4.  Multi-Segment ModelLinear Address Space
(or Physical Memory)Segment
Registers
CSSegment
SSLimit Access
DSLimit Access
ESLimit Access
FSLimit Access
GSLimit Access
Base AddressStack
Code
Data
Data
Data
Data3-6 Vol. 3APROTECTED-MODE MEMORY MANAGEMENT
protection facilities. For example, it lets read-write protection be enforced on a page-by-page basis. The paging 
mechanism also provides two-level user-supervisor protection that can also be specified on a page-by-page basis.
3.3 PHYSICAL ADDRESS SPACE
In protected mode, the IA-32 architecture provides  a normal physical address space of 4 GBytes (232
 bytes). This 
is the address space that the processor can address on its address bus. This address space is flat (unsegmented), 
with addresses ranging continuously from 0 to FFFFFFFFH. This physical address space can be mapped to read-
write memory, read-only memory, and memory mapped I/ O. The memory mapping facilities described in this 
chapter can be used to divide this physic al memory up into segments and/or pages.
Starting with the Pentium Pro processor, the IA-32 architecture also supports an extension of the physical address 
space to 236 bytes (64 GBytes); with a maximum physical address of FFFFFFFFFH. This extension is invoked in 
either of two ways:
•Using the physical address extension (PAE) flag, located in bit 5 of control register CR4. 
•Using the 36-bit page size extension (PSE-36) feature (introduced in the Pentium III processors).
Physical address support has since been extended beyond 36 bits. See Chapter 4, “Pag ing‚” for more information 
about 36-bit physical addressing.
3.3.1 Intel® 64 Processors and Phys ical Address Space
On processors that support Intel 64 architecture (CPU ID.80000001H:EDX[29] = 1), the size of the physical 
address range is implementation-specific and indicated by CPUID.80000008H:EAX[bits 7-0]. 
For the format of information returned in EAX, see “CPUID—CPU Identification” in Chapter 3 of the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual,  Volume 2A. See also: Chapter 4, “Paging.”
3.4 LOGICAL AND LINEAR ADDRESSES
At the system-architecture level in protected mode, the processor uses two stages of address translation to arrive 
at a physical address: logical-address tr anslation and linear address space paging.
Even with the minimum use of segments, every byte in the processor’s address space is accessed with a logical 
address. A logical address consists of a 16-bit segment selector and a 32-bit offset (see Figure 3-5). The segment selector identifies the segment the byte is located in and th e offset specifies the location of the byte in the segment 
relative to the base address of the segment. 
The processor translates every logical address into a linea r address. A linear address is a 32-bit address in the 
processor’s linear address space. Like the physical address space, the linear address space is a flat (unsegmented), 
2
32-byte address space, with addresses ranging from 0 to FFFFFFFFH. The linear address space contains all the 
segments and system tables defined for a system. 
To translate a logical address into a linear address, the processor does the following:1. Uses the offset in the segment selector to locate th e segment descriptor for the segment in the GDT or LDT and 
reads it into the processor. (This step is needed only  when a new segment selector is loaded into a segment 
2. Examines the segment descriptor to check the access ri ghts and range of the segment to ensure that the 
segment is accessible and that the offset is within the limits of the segment.
3. Adds the base address of the segment from the segmen t descriptor to the offset to form a linear address.Vol. 3A 3-7PROTECTED-MODE MEMORY MANAGEMENT
If paging is not used, the processor maps the linear address directly to a physical address (that is, the linear 
address goes out on the processor’s address bus). If the linear address space is paged, a second level of address 
translation is used to translate the linear address into a physical address. 
3.4.1 Logical Address Translation in IA-32e Mode
In IA-32e mode, an Intel 64 processor uses the steps de scribed above to translate a logical address to a linear 
address. In 64-bit mode, the offset and base address of  the segment are 64-bits instead of 32 bits. The linear 
address format is also 64 bits wide and is subject to the canonical form requirement.
Each code segment descriptor provides an L bit. This bit allows a code segment to execute 64-bit code or legacy 
32-bit code by code segment.
3.4.2 Segment Selectors
A segment selector is a 16-bit identifier for a segment (see  Figure 3-6). It does not point directly to the segment, 
but instead points to the segment descriptor that defines the segment. A segment selector contains the following items:
Index (Bits 3 through 15) — Selects one of 8192 descriptors in the GDT or LDT. The processor multiplies 
the index value by 8 (the number of bytes in a se gment descriptor) and adds the result to the base 
address of the GDT or LDT (from the GD TR or LDTR register, respectively).
TI (table indicator) flag
(Bit 2) — Specifies the descriptor table to use: clea ring this flag selects the GDT; setting this flag 
selects the current LDT.Figure 3-5.  Logical Address to Linear Address Translation
Figure 3-6.  Segment SelectorOffset (Effective Address)0
Base AddressDescriptor Table
 Segment
Descriptor31(63)
Seg. Selector0 15Logical
Address
+
Linear Address0 31(63)
15 3210
T
IIndex
Table Indicator
   0 = GDT   1 = LDT
Requested Privilege Level (RPL)RPL3-8 Vol. 3APROTECTED-MODE MEMORY MANAGEMENT
Requested Privilege Level (RPL)
(Bits 0 and 1) — Specifies the privilege level of th e selector. The privilege level can range from 0 to 
3, with 0 being the most privileged level. See Sectio n 5.5, “Privilege Levels,” for a description of the 
relationship of the RPL to the CPL of the execut ing program (or task) and the descriptor privilege 
level (DPL) of the descriptor th e segment selector points to.
The first entry of the GDT is not used by the processor. A se gment selector that points to this entry of the GDT (that 
is, a segment selector with an index of 0 and the TI flag se t to 0) is used as a “null segment selector.” The processor 
does not generate an exception when a segment register (oth er than the CS or SS registers) is loaded with a null 
selector. It does, however, generate an exception when a segment register holding a null selector is used to access 
memory. A null selector can be used to initialize unused segm ent registers. Loading the CS or SS register with a null 
segment selector causes a general-protection exception (#GP) to be generated.

Segment selectors are visible to application programs as pa rt of a pointer variable, but the values of selectors are 
usually assigned or modified by link editors or linking loaders, not application programs.
3.4.3 Segment Registers
To reduce address translation time and coding complexity, the processor provides registers for holding up to 6 
segment selectors (see Figure 3-7). Each of these segment registers support a specific kind of memory reference 
(code, stack, or data). For virtually any kind of program execution to take place, at least the code-segment (CS), 
data-segment (DS), and stack-segment (SS) registers must be loaded with valid segment selectors. The processor 
also provides three additional data-segment registers (ES, FS, and GS), which can be used to make additional data 
segments available to the currently executing program (or task).
For a program to access a segment, the segment selector for the segment must have b een loaded in one of the 
segment registers. So, although a system can define thou sands of segments, only 6 can be available for immediate 
use. Other segments can be made available by loading th eir segment selectors into these registers during program 
Every segment register has a “visible” part and a “hidden”  part. (The hidden part is sometimes referred to as a 
“descriptor cache” or a “shadow register.”) When a segment selector is loaded into the visible part of a segment 
register, the processor also loads the hidden part of the segment register with the base  address, segment limit, and 
access control information from the segment descriptor poin ted to by the segment selector. The information cached 
in the segment register (visible and hidden) allows the processor to translate addresses without taking extra bus 
cycles to read the base address and limit from the segm ent descriptor. In systems in which multiple processors 
have access to the same descriptor tables, it is the responsi bility of software to reload the segment registers when 
the descriptor tables are modified. If this is not done, an  old segment descriptor cached in a segment register might 
be used after its memory-resident version has been modified.
Two kinds of load instructions are prov ided for loading the segment registers:
1. Direct load instructions such as the MOV, POP, LDS, LES, LSS, LGS, and LFS instructions. These instructions 
explicitly reference the segment registers.
2. Implied load instructions such as the far pointer versio ns of the CALL, JMP, and RE T instructions, the SYSENTER 
and SYSEXIT instructions, and the IRET, INT n, INTO, INT3, and INT1 instructions. These instructions change Figure 3-7.  Segment RegistersCS
SS
DS
ES
FS
GSSegment Selector Base Address,  Limit, Access InformationVisible Part Hidden PartVol. 3A 3-9PROTECTED-MODE MEMORY MANAGEMENT
the contents of the CS register (and sometimes other segment registers) as an incidental part of their 
The MOV instruction can also be used to store the visible part of a segment register in a general-purpose register.
3.4.4 Segment Loading Instructions in IA-32e Mode
Because ES, DS, and SS segment registers are not used in 64-bit mode, their fields (base, limit, and attribute) in 
segment descriptor registers are ignored. Some forms of se gment load instructions are also invalid (for example, 
LDS, POP ES). Address calculations that reference the ES, DS, or SS segments are treated as if the segment base 
is zero. 
The processor checks that all linear-address references are in canonical form instead of performing limit checks. 
Mode switching does not change the contents of the se gment registers or the associated descriptor registers. 
These registers are also not changed during 64-bit mode execution, unless explicit segment loads are performed.
In order to set up compatibility mode for an application,  segment-load instructions (MOV to Sreg, POP Sreg) work 
normally in 64-bit mode. An entry is read  from the system descriptor table (GDT or LDT) and is loaded in the hidden 
portion of the segment register. The descriptor-register base , limit, and attribute fields are all loaded. However, the 
contents of the data and stack segment sele ctor and the descriptor registers are ignored.
When FS and GS segment overrides are used in 64-bit mode, their respective base addresses are used in the linear 
address calculation: (FS or GS).base + index + displaceme nt. FS.base and GS.base are then expanded to the full 
linear-address size supported by the implementation. The resulting effective address calculation can wrap across 
positive and negative addresses; the resulting linear address must be canonical.
In 64-bit mode, memory accesses using FS-segment and GS-segment overrides are not checked for a runtime limit 
nor subjected to attribute-checking. Normal segment load s (MOV to Sreg and POP Sreg) into FS and GS load a 
standard 32-bit base value in the hidd en portion of the segment register. The base address bits above the standard 
32 bits are cleared to 0 to allow consistency for implementations that use less than 64 bits. 
The hidden descriptor register fields for FS.base and GS.bas e are physically mapped to MSRs in order to load all 
address bits supported by a 64-bit implementation. Soft ware with CPL = 0 (privileged software) can load all 
supported linear-address bits into FS.base or GS.base using WRMSR. Addresses wri tten into the 64-bit FS.base 
and GS.base registers must be in canonical form. A WRMS R instruction that attempts to write a non-canonical 
address to those registers causes a #GP fault. 
When in compatibility mode, FS and GS overrides operate as defined by 32-bit mode behavior regardless of the 
value loaded into the upper 32 linear-address bits of the hidden descriptor register base field. Compatibility mode 
ignores the upper 32 bits when calculating an effective address.
A new 64-bit mode instruction, SWAPGS, can be used to load GS base. SWAPGS exchanges the kernel data struc-
ture pointer from the IA32_KERNEL_GS_BASE MSR with th e GS base register. The kernel can then use the GS 
prefix on normal memory references to access the kernel  data structures. An attempt to write a non-canonical 
value (using WRMSR) to the IA32_KERNEL_GS_BASE MSR causes a #GP fault.
3.4.5 Segment Descriptors
A segment descriptor is a data structure in a GDT or LDT that provides the processor with the size and location of 
a segment, as well as access control and status inform ation. Segment descriptors are typically created by 
compilers, linkers, loaders, or the operating system or  executive, but not application programs. Figure 3-8 illus-
trates the general descriptor format for all types of segment descriptors.3-10 Vol. 3APROTECTED-MODE MEMORY MANAGEMENT
The flags and fields in a segment descriptor are as follows:
Segment limit field
Specifies the size of the segment. The processor pu ts together the two segment limit fields to form 
a 20-bit value. The processor interprets the segm ent limit in one of two ways, depending on the 
setting of the G (granularity) flag:
• If the granularity flag is clear, the segment size  can range from 1 byte to 1 MByte, in byte incre-
ments.
• If the granularity flag is set, the segment size can range from 4 KBytes to 4 GBytes, in 4-KByte 
increments.
The processor uses the segment limit in two diff erent ways, depending on whether the segment is 
an expand-up or an expand-down segment. Se e Section 3.4.5.1, “Code- and Data-Segment 
Descriptor Types,” for more information about segm ent types. For expand-up segments, the offset 
in a logical address can range from 0 to the segment limit. Offsets greater than the segment limit 
generate general-protection exceptions (#GP, for all segments other than SS) or stack-fault excep-tions (#SS for the SS segment). For expand-dow n segments, the segment limit has the reverse 
function; the offset can range from the segment limit plus 1 to FFFFFFFFH or FFFFH, depending on 
the setting of the B flag. Offsets less than or equa l to the segment limit generate general-protection 
exceptions or stack-fault exceptions. Decreasing th e value in the segment limit field for an expand-
down segment allocates new memory at the bottom of  the segment's address space, rather than at 
the top. IA-32 architecture stacks always grow downwards, making this mechanism convenient for expandable stacks.
Base address fields
Defines the location of byte 0 of the segment within the 4-GByte linear address space. The 
processor puts together the three base address fiel ds to form a single 32-bit value. Segment base 
addresses should be aligned to 16-byte boundari es. Although 16-byte alignment is not required, 
this alignment allows programs to maximize perf ormance by aligning code and data on 16-byte 
boundaries.
Type field Indicates the segment or gate type and specifie s the kinds of access that can be made to the 
segment and the direction of growth. The interpre tation of this field depends on whether the

segment and the direction of growth. The interpre tation of this field depends on whether the 
descriptor type flag specifies an application (cod e or data) descriptor or a system descriptor. The 
encoding of the type field is different for code , data, and system descriptors (see Figure 5-1). See 
Section 3.4.5.1, “Code- and Data-Segment Descripto r Types,” for a description of how this field is 
used to specify code an d data-segment types. Figure 3-8.  Segment Descriptor31 24232221 20 19 16 15 1314 12 11 87 0
P Base 31:24 GD
P
LType S L 4
31 1615 0
Base Address 15:00 Segment Limit 15:00 0Base 23:16D
/
BA
V
LSeg.
Limit
19:16
G — Granularity
LIMIT — Segment Limit
P — Segment presentS — Descriptor type (0 = system; 1 = code or data)
TYPE — Segment typeDPL — Descriptor privilege levelAVL — Available for use by system software
BASE — Segment base address
D/B — Default operation size (0 = 16-bit segment; 1 = 32-bit segment)L — 64-bit code segment (IA-32e mode only)Vol. 3A 3-11PROTECTED-MODE MEMORY MANAGEMENT
S (descriptor type) flag
Specifies whether the segment descriptor is for a system segment (S flag is clear) or a code or data segment (S flag is set).
DPL (descriptor privilege level) field
Specifies the privilege level of the segment. The pr ivilege level can range from 0 to 3, with 0 being 
the most privileged level. The DPL is used to cont rol access to the segment. See Section 5.5, “Priv-
ilege Levels,” for a description of the relationsh ip of the DPL to the CPL of the executing code 
segment and the RPL of a segment selector.
P (segment-present) flag
Indicates whether the segment is present in memory (set ) or not present (clear). If this flag is clear, 
the processor generates a segment-not-present ex ception (#NP) when a segment selector that 
points to the segment descriptor is loaded into a segment register. Memory management software 
can use this flag to control which segments are actually loaded into physical memory at a given 
time. It offers a control in addition to paging for managing virtual memory.
Figure 3-9 shows the format of a segment descriptor when the segment-present flag is clear. When 
this flag is clear, the operating system or executive is free to use the locations marked “Available” to 
store its own data, such as information regarding the whereabouts of the missing segment.
D/B (default operation size/default stac k pointer size and/or upper bound) flag
Performs different functions depending on whethe r the segment descriptor is an executable code 
segment, an expand-down data segment, or a stack segment. (This flag should always be set to 1 
for 32-bit code and data segments and to  0 for 16-bit code and data segments.)
•Executable code segment.  The flag is called the D flag and it indicates the default length for 
effective addresses and operands referenced by inst ructions in the segment. If the flag is set, 
32-bit addresses and 32-bit or 8-bit operands are assumed; if it is clear, 16-bit addresses and 
16-bit or 8-bit operands are assumed. 
The instruction prefix 66H can be used to select an operand size other than the default, and the prefix 67H can be used select an address size other than the default.
•Stack segment (data segment poin ted to by the SS register).  The flag is called the B (big) 
flag and it specifies the size of the stack pointer used for implicit stack operations (such as 
pushes, pops, and calls). If the flag is set, a 32-b it stack pointer is used, which is stored in the 
32-bit ESP register; if the flag is clear, a 16-bit stack pointer is used, which is stored in the 16-bit SP register. If the stack segment is set up to  be an expand-down data segment (described in 
the next paragraph), the B flag also specifies the upper bound of the stack segment.
•Expand-down data segment.  The flag is called the B flag and it specifies the upper bound of 
the segment. If the flag is set,  the upper bound is FFFFFFFFH (4 GBytes); if the flag is clear, the 
upper bound is FFFFH (64 KBytes).
G (granularity) flag
Determines the scaling of the segment limit field. When the granularity flag is clear, the segment 
limit is interpreted in byte units; when flag is se t, the segment limit is interpreted in 4-KByte units. 
(This flag does not affect the granularity of the base  address; it is always byte granular.) When the 
granularity flag is set, the twelve least significant bits of an offset are not tested when checking the Figure 3-9.  Segment Descriptor Wh en Segment-Present Flag Is Clear31 1615 1314 12 11 87 0
0 AvailableD
P
LType S 4
31 0
Available 0Available3-12 Vol. 3APROTECTED-MODE MEMORY MANAGEMENT
offset against the segment limit. For example, when the granularity flag is set, a limit of 0 results in 
valid offsets from 0 to 4095.
L (64-bit code segment) flag
In IA-32e mode, bit 21 of the second doubleword  of the segment descriptor indicates whether a 
code segment contains native 64-bit code. A value of 1 indicates instructions in this code segment 
are executed in 64-bit mode. A value of 0 indica tes the instructions in this code segment are 
executed in compatibility mode. If the L-bit is set, then the D-bit must be cleared. Bit 21 is not used 
outside IA-32e mode (or for data segments). Becaus e an attempt to activate IA-32e mode will fault 
if the current CS has the L-bit set (see Section 10.8.5), software operating outside IA-32e mode 
should avoid loading CS from a descriptor that sets the L-bit.
Available and reserved bits
Bit 20 of the second doubleword of the segment de scriptor is available for use by system software.
3.4.5.1  Code- and Data-Segment Descriptor Types
When the S (descriptor type) flag in a segment descriptor is set, the descriptor is for either a code or a data 
segment. The highest order bit of the type field (bit 11 of  the second double word of the segment descriptor) then 
determines whether the descriptor is for a data  segment (clear) or a code segment (set). 
For data segments, the three low-order bits of the type fi eld (bits 8, 9, and 10) are interpreted as accessed (A), 
write-enable (W), and expansion-direction (E). See Table 3- 1 for a description of the encoding of the bits in the 
type field for code and data segments. Data segments ca n be read-only or read/write segments, depending on the 
setting of the write-enable bit. 
Stack segments are data segments which must be read/w rite segments. Loading the SS  register with a segment 
selector for a nonwritable data segment generates a genera l-protection exception (#GP). If the size of a stack 
segment needs to be changed dynamically, the stack se gment can be an expand-down data segment (expansion-Table 3-1.  Code- and Data-Segment Types 
Type Field Descriptor
Decimal 11 10
E9
W8
A
00 0 0 0D a t a R e a d - O n l y
1 0 0 0 1 Data Read-Only, accessed20 0 1 0D a t a R e a d / W r i t e
3 0 0 1 1 Data Read/Write, accessed
4 0 1 0 0 Data Read-Only, expand-down5 0 1 0 1 Data Read-Only, expand-down, accessed
6 0 1 1 0 Data Read/Write, expand-down
7 0 1 1 1 Data Read/Write, expand-down, accessed
CRA
81 0 0 0C o d e E x e c u t e - O n l y
91 0 0 1C o d e E x e c u t e - O n l y ,  a c c e s s e d
1 0 1010 C o d e E x e c u t e / R e a d
1 1 1011 C o d e E x e c u t e / R e a d ,  a c c e s s e d
12 1 1 0 0 Code Execute-Only, conforming13 1 1 0 1 Code Execute-Only, conforming, accessed
1 4 1110 C o d e E x e c u t e / R e a d ,  c o n f o r m i n g
1 5 1111 C o d e E x e c u t e / R e a d ,  c o n f o r m i n g ,  a c c e s s e dVol. 3A 3-13PROTECTED-MODE MEMORY MANAGEMENT
direction flag set). Here, dynamically changing the segmen t limit causes stack space to be added to the bottom of 
the stack. If the size of a stack segment is intended to remain static, the stack segment may be either an expand-
up or expand-down type.
The accessed bit indicates whether the segment has been accessed since the last time the operating-system or 
executive cleared the bit. The processor sets this bit when ever it loads a segment selector for the segment into a 
segment register, assuming that the type of memory that contains the segment descriptor supports processor 
writes. The bit remains set until explicit ly cleared. This bit can be used bo th for virtual memory management and 
for debugging. 
For code segments, the three low-order bits of the type fiel d are interpreted as accessed (A), read enable (R), and 
conforming (C). Code segments can be execute-only or execute/read, depending on the setting of the read-enable 
bit. An execute/read segment might be used when constants or other static data have been placed with instruction 
code in a ROM. Here, data can be read from the code segment either by using an instruction with a CS override prefix or by loading a segment selector  for the code segment in a data-segment register (the DS, ES, FS, or GS 
registers). In protected mode, code segments are not writable.
Code segments can be either conforming or nonconform ing. A transfer of execution into a more-privileged 
conforming segment allows execution to continue at the current privilege level. A transfer into a nonconforming

conforming segment allows execution to continue at the current privilege level. A transfer into a nonconforming 
segment at a different privilege level results in a general-pr otection exception (#GP), unless a call gate or task gate 
is used (see Section 5.8.1, “Direct Calls or Jumps to Code Segments,” for more information on conforming and 
nonconforming code segments). System utilities that do no t access protected facilities and handlers for some types 
of exceptions (such as, divide error or overflow) may be lo aded in conforming code segm ents. Utilities that need to 
be protected from less privileged programs and procedur es should be placed in no nconforming code segments. 
NOTE
Execution cannot be transferred by a call or a jump to a less-privileged (numerically higher 
privilege level) code segment, regardless of wh ether the target segment is a conforming or 
nonconforming code segment. Attempting such an  execution transfer will result in a general-
protection exception.
All data segments are nonconforming, meaning that they cannot be accessed by less pr ivileged programs or proce-
dures (code executing at numerically higher privilege leve ls). Unlike code segments, however, data segments can 
be accessed by more privileged programs or procedures  (code executing at numerically lower privilege levels) 
without using a special access gate.
If the segment descriptors in the GDT or an LDT are placed  in ROM, the processor can enter an indefinite loop if 
software or the processor attempts to update (write to) the ROM-based segment descriptors. To prevent this 
problem, set the accessed bits for all segment descriptors placed in a ROM. Also, remove operating-system or 
executive code that attempts to modify segment descriptors located in ROM.
3.5 SYSTEM DESCRIPTOR TYPES
When the S (descriptor type) flag in a segment descriptor is  clear, the descriptor type is a system descriptor. The 
processor recognizes the following types of system descriptors:
•Local descriptor-table (LDT) segment descriptor.
•Task-state segment (TSS) descriptor.
•Call-gate descriptor.
•Interrupt-gate descriptor.
•Trap-gate descriptor.
•Task-gate descriptor.
These descriptor types fall into two categories: system-segment descriptors and gate descriptors. System-
segment descriptors point to system segments (LDT an d TSS segments). Gate descr iptors are in themselves 
“gates,” which hold pointers to proced ure entry points in code segments (call, interrupt, and trap gates) or which 
hold segment selectors for TSS’s (task gates). 3-14 Vol. 3APROTECTED-MODE MEMORY MANAGEMENT
Table 3-2 shows the encoding of the type field for syst em-segment descriptors and gate descriptors. Note that 
system descriptors in IA-32e mode are 16 bytes instead of 8 bytes.
See also: Section 3.5.1, “Segment Descriptor Tables,” and Section 8.2.2, “TSS Descriptor,” (for more information 
on the system-segment descriptors); see Section 5.8.3, “C all Gates,” Section 6.11, “IDT Descriptors,” and Section 
8.2.5, “Task-Gate Descriptor,” (for more  information on the gate descriptors).
3.5.1 Segment Descriptor Tables
A segment descriptor table is an array of segment descripto rs (see Figure 3-10). A descriptor table is variable in 
length and can contain up to 8192 (213) 8-byte descriptors. There are two kinds of descriptor tables:
•The global descriptor table (GDT).
•The local descriptor tables (LDT).Table 3-2.  System-Segment  and Gate-Descriptor Types
Type Field Description
Decimal 11 10 9 8 32-Bit Mode IA-32e Mode
0 0000 R e s e r v e d R e s e r v e d1 0001 1 6 - b i t  T S S  ( A v a i l a b l e ) R e s e r v e d
2 0010 L D T L D T
3 0011 1 6 - b i t  T S S  ( B u s y ) R e s e r v e d4 0100 1 6 - b i t  C a l l  G a t e R e s e r v e d
5 0101 T a s k  G a t e R e s e r v e d
6 0110 1 6 - b i t  I n t e r r u p t  G a t e R e s e r v e d7 0111 1 6 - b i t  T r a p  G a t e R e s e r v e d8 1000 R e s e r v e d R e s e r v e d
9 1001 3 2 - b i t  T S S  ( A v a i l a b l e ) 6 4 - b i t  T S S  ( A v a i l a b l e )
1 0 1010 R e s e r v e d R e s e r v e d1 1 1011 3 2 - b i t  T S S  ( B u s y ) 6 4 - b i t  T S S  ( B u s y )
1 2 1100 3 2 - b i t  C a l l  G a t e 6 4 - b i t  C a l l  G a t e
1 3 1101 R e s e r v e d R e s e r v e d1 4 1110 3 2 - b i t  I n t e r r u p t  G a t e 6 4 - b i t  I n t e r r u p t  G a t e
1 5 1111 3 2 - b i t  T r a p  G a t e 6 4 - b i t  T r a p  G a t eVol. 3A 3-15PROTECTED-MODE MEMORY MANAGEMENT
Each system must have one GDT defined, which may be us ed for all programs and tasks in the system. Optionally, 
one or more LDTs can be defined. For example, an LDT can be defined for each separate task being run, or some or 
all tasks can share the same LDT.
The GDT is not a segment itself; instead, it is a data st ructure in linear address space. The base linear address and 
limit of the GDT must be loaded into the GDTR register  (see Section 2.4, “Memory-Management Registers”). The 
base address of the GDT should be aligned on an eight-by te boundary to yield the best processor performance. The 
limit value for the GDT is expressed in bytes. As with segments, the limit valu e is added to the base address to get 
the address of the last valid byte. A limit value of 0 resu lts in exactly one valid byte. Because segment descriptors 
are always 8 bytes long, the GDT limit should always be one less than an integral multiple of eight (that is, 8N – 1).
The first descriptor in the GDT is not used by the processo r. A segment selector to this “null descriptor” does not 
generate an exception when loaded into a data-segment re gister (DS, ES, FS, or GS), but it always generates a 
general-protection exception (#GP) when an attempt is made  to access memory using the descriptor. By initializing 
the segment registers with this segment selector, accide ntal reference to unused segment registers can be guar-
anteed to generate an exception.
The LDT is located in a system segment of the LDT type . The GDT must contain a segment descriptor for the LDT 
segment. If the system supports multiple LDTs, each  must have a separate segment selector and segment 
descriptor in the GDT. The segment descriptor for an LDT can be located anywhere in the GDT. See Section 3.5, 
“System Descriptor Types,” for informatio n on the LDT segment-descriptor type.
An LDT is accessed with its segment selector. To eliminate address translations when accessing the LDT, the 
segment selector, base linear address, limit, and access ri ghts of the LDT are stored in the LDTR register (see 
Section 2.4, “Memory-Management Registers”). 
When the GDTR register is stored (using the SGDT instru ction), a 48-bit “pseudo-descriptor” is stored in memory 
(see top diagram in Figure 3-11). To avoid alignment check faults in user mode (privilege level 3), the pseudo-
descriptor should be located at an odd word address (t hat is, address MOD 4 is equal to 2). This causes the Figure 3-10.  Global and Local Descriptor TablesSegment
SelectorGlobal
T
First Descriptor in
GDT is Not UsedTI = 0 I
56
4048
32
24
16
8
0TI = 1
56
4048
32
24
16
8
0Table (GDT)Local
Table (LDT)
Base AddressLimitGDTR Register LDTR Register
Seg. Sel.Limit3-16 Vol. 3APROTECTED-MODE MEMORY MANAGEMENT
processor to store an aligned word, followed by an aligne d doubleword. User-mode programs normally do not store 
pseudo-descriptors, but the possibility of generating an alignment check fault can be avoided by aligning pseudo-
descriptors in this way. The same alignment should be us ed when storing the IDTR register using the SIDT instruc-
tion. When storing the LDTR or task register (using the SLDT or STR instruction, respectively), the pseudo-
descriptor should be located at a doubleword address (that is, address MOD 4 is equal to 0).
3.5.2 Segment Descriptor Tables in IA-32e Mode
In IA-32e mode, a segment descriptor table can contain up to 8192 (213) 8-byte descriptors. An entry in the 
segment descriptor table can be 8 bytes. System descripto rs are expanded to 16 bytes (occupying the space of two 
entries). 
GDTR and LDTR registers are expanded to hold 64-bit base address. The corresponding pseudo-descriptor is 80 
bits. (see the bottom diagram in Figure 3-11).
The following system descriptors expand to 16 bytes:
— Call gate descriptors (see Section 5.8.3.1, “IA-32e Mode Call Gates”).
— IDT gate descriptors (see Section 6.14.1, “64-Bit Mode IDT”).
— LDT and TSS descriptors (see Section 8.2.3, “TSS Descriptor in 64-bit mode”).Figure 3-11.  Pseudo-Descriptor Formats0
32-bit Base Address Limit47 15 16
0
64-bit Base Address Limit79 15 16Vol. 3A 4-1CHAPTER 4
PAGING
Chapter 3 explains how segmentation converts logical addresses to linear addresses. Paging  (or linear-address 
translation) is the process of translating linear addresses so that they can be used to access memory or I/O devices. Paging translates each linear address to a physical address  and determines, for each translation, what 
accesses to the linear address are allowed (the address’s access rights ) and the type of caching used for such

0
PAGING
accesses to the linear address are allowed (the address’s access rights ) and the type of caching used for such 
accesses (the address’s memory type ).
Intel-64 processors support four different paging modes. These modes are identified and defined in Section 4.1. 
Section 4.2 gives an overview of the translation mechanism th at is used in all modes. Section 4.3, Section 4.4, and 
Section 4.5 discuss the four paging modes in detail.
Section 4.6 details how paging determines and uses access rights. Section 4.7 discusses exceptions that may be 
generated by paging (page-fault exceptions). Section 4.8 co nsiders data which the processor writes in response to 
linear-address accesses (accessed and dirty flags).
Section 4.9 describes how paging determines the memory types used for accesses to linear addresses. Section 
4.10 provides details of how a processor may cache in formation about linear-address translation. Section 4.11 
outlines interactions between paging and certain VMX feat ures. Section 4.12 gives an overview of how paging can 
be used to implement virtual memory.
4.1 PAGING MODES AND CONTROL BITS
Paging behavior is controlled by the following control bits:
•The WP and PG flags in control register CR0 (bit 16 and bit 31, respectively).
•The PSE, PAE, PGE, LA57, PCIDE, SM EP, SMAP, PKE, CET, and PKS flags in control register CR4 (bit 4, bit 5, 
bit 7, bit 12, bit 17, bit 20, bit 21, bit 22, bit 23, and bit 24, respectively).
•The LME and NXE flags in the IA32_EFE R MSR (bit 8 and bit 11, respectively).
•The AC flag in the EFLAGS register (bit 18).
•The “enable HLAT” VM-execution control (tertiary processor-based VM-execution control bit 1; see Section 
25.6.2, “Processor-Based VM-Execu tion Controls,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3C).
Software enables paging by using the MOV to CR0 instru ction to set CR0.PG. Before doing so, software should 
ensure that control register CR3 contains the physical a ddress of the first paging structure that the processor will 
use for linear-address translation (see Section 4.2) and that  that structure is initialized as desired. See Table 4-3, 
Table 4-7, and Table 4-12 for the use of CR3 in the different paging modes.
Section 4.1.1 describes how the values of CR0.PG, CR 4.PAE, CR4.LA57, and IA32_EFER.LME determine whether 
paging is enabled and, if so, which of four paging modes is  in use. Section 4.1.2 explains how to manage these bits 
to establish or make changes in paging modes. Se ction 4.1.3 discusses how CR0.WP, CR4.PSE, CR4.PGE, 
CR4.PCIDE, CR4.SMEP, CR4.SMAP, CR4.PKE, CR4.CET, CR4. PKS, and IA32_EFER.NXE modify the operation of the 
different paging modes.
4.1.1 Four Paging Modes
If CR0.PG = 0, paging is not used. The logical processor treats all linear addresses as if they were physical 
addresses. CR4.PAE, CR4.LA57, and IA32_EFER.LME are ignored by the processor, as are CR0.WP, CR4.PSE, 
CR4.PGE, CR4.SMEP, CR4.SMAP, and IA32_EFER.NXE. (CR4.CET is also ignored insofar as it affects linear-address 
access rights.)
Paging is enabled if CR0.PG = 1. Paging can be enabled on ly if protection is enabled (CR0.PE = 1). If paging is 
enabled, one of four paging modes is used. The values of CR4.PAE, CR4.LA57, and IA32_EFER.LME determine 
which paging mode is used:4-2 Vol. 3APAGING
•If CR4.PAE = 0, 32-bit paging  is used. 32-bit paging is detailed in Section 4.3. 32-bit paging uses CR0.WP, 
CR4.PSE, CR4.PGE, CR4.SMEP, CR4.SMAP, and CR4.CET as described in Section 4.1.3 and Section 4.6.
•If CR4.PAE = 1 and IA32_EFER.LME = 0, PAE paging  is used. PAE paging is detail ed in Section 4.4. PAE paging 
uses CR0.WP, CR4.PGE, CR4.SMEP, CR4.SMAP, CR4.CET, and IA32_EFER.NXE as described in Section 4.1.3 and 
Section 4.6.
•If CR4.PAE = 1, IA32_EFER.LME = 1, and CR4.LA57 = 0, 4-level paging1 is used.2 4-level paging is detailed 
in Section 4.5 (along with 5-level paging). 4-level paging uses CR0.WP, CR4.PGE, CR4.PCIDE, CR4.SMEP, CR4.SMAP, CR4.PKE, CR4.CET, CR4.PKS, and IA32_EFER.NXE as described in Section 4.1.3 and Section 4.6.
•If CR4.PAE = 1, IA32_EFER.LME = 1, and CR4.LA57 = 1, 5-level paging  is used. 5-level paging is detailed in 
Section 4.5 (along with 4-level paging). 5-level pa ging uses CR0.WP, CR4.PGE, CR4.PCIDE, CR4.SMEP, 
CR4.SMAP, CR4.PKE, CR4.CET, CR4.PKS, and IA32_EFER.NXE as described in Section 4.1.3 and Section 4.6.
NOTE
32-bit paging and PAE paging can be used only in legacy protected mode (IA32_EFER.LME = 0). In 
contrast, 4-level paging and 5-level paging can be used only IA-32e mode (IA32_EFER.LME = 1).
The four paging modes differ with regard to the following details:
•Linear-address width. The size of the linear addresses that can be translated.
•Physical-address width. The size of the physical addresses produced by paging.
•Page size. The granularity at which linear addresses ar e translated. Linear addresses on the same page are 
translated to corresponding physical addresses on the same page.
•Support for execute-disable access rights. In some pagi ng modes, software can be  prevented from fetching 
instructions from pages that are otherwise readable.
•Support for PCIDs. With 4-level paging and 5-level pagi ng, software can enable a facility by which a logical 
processor caches information for multiple linear-address spaces. The processor may retain cached information when software switches between different linear-address spaces.
•Support for protection keys. With 4-level paging and 5-level paging, each linear address is associated with a 
protection key . Software can use the protection-key rights registers to disable, for each protection key, how 
certain accesses to linear addresses associated with that protection key.
Table 4-1 illustrates the principal differences between the four paging modes.
1. Earlier versions of this manual used the te rm “IA-32e paging” to identify 4-level paging.
2. The LMA flag in the IA32_EFER MSR (bit 10) is a status bit that indicates whether the logical processor is in IA-32e mode (and  thus 
uses either 4-level paging or 5-level paging). The processor al ways sets IA32_EFER.LMA to CR0.PG & IA32_EFER.LME. Software can-
not directly modify IA32_EFER. LMA; an execution of WRMSR to the IA32_EFER MSR ignores bit 10 of its source operand.Table 4-1.  Properties of  Different Paging Modes
Paging
ModePG in
CR0PAE in
CR4LME in
IA32_EFERLA57 in 
CR4Lin.-
Addr.
WidthPhys.-
Addr.
Width1PageSizesSupports
Execute-
Disable?Supports
PCIDs and protection 
keys?
None 0 N/A N/A N/A 32 32 N/A No No
3 2 - b i t 100
2N/A 32 Up to 403 4 KB
4 MB4 No No
P A E110 N / A 3 2 U p  t o  5 24 KB
2 MBYes5No
4 - l e v e l 111 04 8 U p  t o  5 24 KB
2 MB1 GB
6Yes5Yes7Vol. 3A 4-3PAGING
Because 32-bit paging and PAE paging are used only in le gacy protected mode and because legacy protected mode 
cannot produce linear addresses larger than 32 bits, 32-bit paging and PAE paging translate 32-bit linear 
4-level paging and 5-level paging are used only in IA-32e mode. IA-32e mode has two sub-modes:
•Compatibility mode. This sub-mode uses only 32-bit linea r addresses. In this sub-mode, 4-level paging and 5-
level paging treat bits 63:32 of such an address as all 0.
•64-bit mode. While this sub-mode produces 64-bit linear addresses, the processor enforces canonicality , 
meaning that the upper bits of such an address are id entical: bits 63:47 for 4-level paging and bits 63:56 for 
5-level paging. 4-level paging (respectively, 5-level paging) does not use bits 63:48 (respectively, bits 63:57) of such addresses.
4.1.2 Paging-Mode Enabling
If CR0.PG = 1, a logical processor is in one of four paging modes, depending on the values of CR4.PAE, 
IA32_EFER.LME, and CR4.LA57. Figure 4-1 illustrates how software can enable these modes and make transitions 
between them. The following items identify certain limitations and other details:
•IA32_EFER.LME cannot be modified while paging is enab led (CR0.PG = 1). Attempts to do so using WRMSR 
cause a general-protection exception (#GP(0)).
•Paging cannot be enabled (by setting CR0.PG to 1) wh ile CR4.PAE = 0 and IA32_EFER.LME = 1. Attempts to do 
so using MOV to CR0 cause a general-protection exception (#GP(0)).
•One node in Figure 4-1 is labeled “IA-32e mode.” This no de represents either 4-level paging (if CR4.LA57 = 0) 
or 5-level paging (if CR4.LA57 = 1). As noted in the following items, software cannot modify CR4.LA57 (effecting transition between 4-level paging and 5-level paging) without first disabling paging.
•CR4.PAE and CR4.LA57 cannot be modified while either 4-level paging or 5-level paging is in use (when 
CR0.PG = 1 and IA32_EFER.LME = 1). Attempts to do so using MOV to CR4 cause a general-protection 
•Regardless of the current paging mode, software can disable paging by clearing CR0.PG with MOV to CR0.1
•Software can transition between 32-bit paging and PAE paging by changing the value of CR4.PAE with MOV to 
CR4.5 - l e v e l 111 15 7 U p  t o  5 24 KB
2 MB
1 GB6Yes5Yes7
NOTES:
1. The physical-address width is always bounded by MAXPHYADDR; see Section 4.1.4.
2. The processor ensu res that IA32_EFER.LME must be 0 if CR0.PG = 1 and CR4.PAE = 0.

2 MB
NOTES:
3. 32-bit paging supports physical-address widths of more than 32 bits only for 4-MByte pages and only if the PSE-36 mechanism is 
supported; see Section 4.1.4 and Section 4.3.
4. 32-bit paging uses 4-MByte pages only if CR4.PSE = 1; see Section 4.3.
5. Execute-disable access rights are applied only if IA32_EFER.NXE = 1; see Section 4.6.
6. Processors that support 4- level paging or 5-level paging  do not necessarily support 1- GByte pages; see Section 4.1.4.
7. PCIDs are used only if CR4.PC IDE = 1; see Section 4.10.1. Protection keys are used only if certain conditions hold; see Secti on 4.6.2.
1. If the logical processor is in 64-bit mode  or if CR4.PCIDE = 1, an attempt to clear CR0.PG causes a general-protection excepti on 
(#GP). Software shou ld transition to compatibility mode and clear CR4.PCIDE before attempting to disable paging. Table 4-1.  Properties of Di fferent Paging Modes (Contd.)
Paging
ModePG in
CR0PAE in
CR4LME in
CR4Lin.-
Addr.
Addr.
Execute-
keys?4-4 Vol. 3APAGING
•Software cannot transition directly between 4-level pagi ng (or 5-level paging) and any of other paging mode. 
It must first disable paging (by clearing CR0.PG wi th MOV to CR0), then set CR4.PAE, IA32_EFER.LME, and 
CR4.LA57 to the desired values (with MOV to CR4 and WR MSR), and then re-enable paging (by setting CR0.PG 
with MOV to CR0). As noted earlier, an attempt to mo dify CR4.PAE, IA32_EFER.LME, or CR.LA57 while 4-level 
paging or 5-level paging is enabled causes a general-protection exception (#GP(0)).
•VMX transitions allow transitions between paging modes th at are not possible using MOV to CR or WRMSR. This 
is because VMX transitions can load CR0, CR4, and IA32_EFER in one operation. See Section 4.11.1.
4.1.3 Paging-Mode Modifiers
Details of how each paging mode operates are determined by the following control bits:
•The WP flag in CR0 (bit 16).
•The PSE, PGE, PCIDE, SMEP, SMAP, PKE, CET, and PKS flags in CR4 (bit 4, bit 7, bit 17, bit 20, bit 21, bit 22, 
bit 23, and bit 24, respectively).
•The NXE flag in the IA32_EFER MSR (bit 11).
•The “enable HLAT” VM-execution control (tertiary processor-based VM-execution control bit 1).
CR0.WP allows pages to be protected from supervis or-mode writes. If CR0.WP = 0, supervisor-mode write 
accesses are allowed to linear addresses with read-only a ccess rights; if CR0.WP = 1, they are not. (User-mode 
write accesses are never allowed to linear addresses with  read-only access rights, regardless of the value of Figure 4-1.  Enabling and Changing Paging ModesPG = 1No Paging
PAE Paging
PAE = 1
LME = 0PG = 0
PAE = 0LME = 032-bit Paging
PG = 1
PAE = 0LME = 0
PG = 0
PAE = 0LME = 1Set PG Set PAE
Clear PAE Clear PG
No Paging
PG = 0
PAE = 1
LME = 0No Paging
PG = 14-level Paging
PAE = 1
LME = 1
Clear LMESetr LME
PG = 0
PAE = 1LME = 1No PagingClear PAE
Set PAE Clear PGSet PG
Set PAEClear PAE
Setr LMEClear LME
Clear PGSet PG#GP
Set LME#GP
Set LME
#GPSet PGClear PAE#GPClear LME
#GPVol. 3A 4-5PAGING
CR0.WP.) Section 4.6 explains how access rights are dete rmined, including the definition of supervisor-mode and 
user-mode accesses.
CR4.PSE enables 4-MByte pages for 32-bit paging. If CR4.PSE = 0, 32-bit paging can use only 4-KByte pages; if 
CR4.PSE = 1, 32-bit paging can use both 4-KByte pages an d 4-MByte pages. See Section 4.3 for more information. 
(PAE paging, 4-level paging, and 5-level paging can use mu ltiple page sizes regardless of the value of CR4.PSE.)
CR4.PGE enables global pages. If CR4.PGE = 0, no transl ations are shared across address spaces; if CR4.PGE = 1, 
specified translations may be shared across address spaces. See Section 4.10.2.4 for more information.
CR4.PCIDE enables process-context identifiers (PCIDs) for 4-level paging and 5-level paging. PCIDs allow a logical 
processor to cache information for multiple linear-address spaces. See Section 4.10.1 for more information.
CR4.SMEP allows pages to be protected from supervisor -mode instruction fetches. If CR4.SMEP = 1, software 
operating in supervisor mode cannot fetch instructions from linear addresses that are accessible in user mode. 
Section 4.6 explains how access rights are determined, in cluding the definition of supervisor-mode accesses and 
user-mode accessibility.
CR4.SMAP allows pages to be protected from supervisor -mode data accesses. If CR4.SMAP = 1, software oper-
ating in supervisor mode cannot access data at linear addresses that are accessible in user mode. Software can 
override this protection by setting EFLAGS.AC. Section 4.6 explains how access rights are determined, including 
the definition of supervisor-mode accesses and user-mode accessibility.
CR4.PKE and CR4.PKS enable specification of access rights based on protection keys . 4-level paging and 5-level 
paging associate each linear address with a protection ke y. When CR4.PKE = 1, the PKRU register specifies, for 
each protection key, whether user-mode linear addresses with that protection key can be read or written. When 
CR4.PKS = 1, the IA32_PKRS MSR does the same for supervisor-mode linear addresses. See Section 4.6 for more 
CR4.CET enables control-flow enforcement technology , including the shadow-stack feature. If CR4.CET = 1, 
certain memory accesses are identified as shadow-stack accesses  and certain linear addresses translate to 
shadow-stack pages . Section 4.6 explains how access rights are determined for these accesses and pages. (The 
processor allows CR4.CET to be set only if CR0.WP is also set.)
IA32_EFER.NXE enables execute-disable access rights fo r PAE paging, 4-level paging, and 5-level paging. If 
IA32_EFER.NXE = 1, instruction fetches can be prevented fr om specified linear addresses (even if data reads from 
the addresses are allowed). Section 4.6 explains how acce ss rights are determined. (IA32_EFER.NXE has no effect 
with 32-bit paging. Software that wants to use this feat ure to limit instruction fetches from readable pages must 
use PAE paging, 4-level paging, or 5-level paging.)
The “enable HLAT” VM-execution control enables HLAT paging  for 4-level paging and 5-level paging. HLAT paging 
does not use control register CR3 to identify the address of the first paging structure used for linear-address trans-
lation; instead, that structure is located using a field in  the virtual-machine control structure (VMCS). In addition, 
HLAT paging interprets certain bits in paging-structure en tries differently than ordinary paging. See Section 4.5 for 
details.
4.1.4 Enumeration of Paging Features by CPUID
Software can discover support for different paging features using the CPUID instruction:
•PSE: page-size extensions for 32-bit paging.
I f  C P U I D . 0 1 H : E D X . P S E[ b i t3 ]=  1 ,  C R 4 . P S E  m a y  b e  s e t  t o  1, enabling support for 4-MByte pages with 32-bit 
paging (see Section 4.3).
•PAE: physical-address extension.
If CPUID.01H:EDX.PAE [bit 6] = 1, CR4.PAE may be set to 1, enabling PAE paging (this setting is also required 
for 4-level paging and 5-level paging).
•PGE: global-page support.If CPUID.01H:EDX.PGE [bit 13] = 1, CR4.PGE may be set to 1, enabling the global-page feature (see Section 
4.10.2.4).
•PAT: page-attribute table.
If CPUID.01H:EDX.PAT [bit 16] = 1, the 8-entry page-attr ibute table (PAT) is supported. When the PAT is 4-6 Vol. 3APAGING
supported, three bits in certain paging-structure entr ies select a memory type (used to determine type of 
caching used) from the PAT (see Section 4.9.2).
•PSE-36: page-size extensions with 40-bit physical-address extension.If CPUID.01H:EDX.PSE-36 [bit 17] = 1, the PSE-36 mechanis m is supported, indicating that translations using 
4-MByte pages with 32-bit paging may produce physical  addresses with up to 40 bits (see Section 4.3).
•PCID: process-context identifiers.
If CPUID.01H:ECX.PCID [bit 17] = 1, CR4.PCIDE may be se t to 1, enabling process-context identifiers (see 
Section 4.10.1).
•SMEP: supervisor-mode execution prevention.
If CPUID.(EAX=07H,ECX=0H):EBX.SMEP [bit 7] = 1, CR4.SMEP may be set to 1, enabling supervisor-mode 
execution prevention (see Section 4.6).
•SMAP: supervisor-mode access prevention.If CPUID.(EAX=07H,ECX=0H):EBX.SMAP [bit 20] = 1, CR4.SMAP may be set to 1, enabling supervisor-mode 
access prevention (see Section 4.6).
•PKU: protection keys for user-mode pages.
If CPUID.(EAX=07H,ECX=0H):ECX.PKU [bit 3] = 1, CR4.PKE may be set to 1, enabling protection keys for 
user-mode pages (see Section 4.6).
•OSPKE: enabling of protection keys for user-mode pages.
CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4] returns the value of CR4.PKE. Thus, protection keys for user-mode pages are enabled if this flag is 1 (see Section 4.6).
•CET: control-flow enforcement technology.
If CPUID.(EAX=07H,ECX=0H):ECX.CET_SS [bit 7] = 1, CR 4.CET may be set to 1, enabling shadow-stack 
pages (see Section 4.6).

•LA57: 57-bit linear addresses and 5-level paging.If CPUID.(EAX=07H,ECX=0):ECX.LA57 [ bit 16] = 1, CR4.LA57 may be set to 1, enabling 5-level paging.
•PKS: protection keys for supervisor-mode pages.
If CPUID.(EAX=07H,ECX=0H):ECX.PKS [bit 31] = 1, CR4.PK S may be set to 1, enabling protection keys for 
supervisor-mode pages (see Section 4.6).
•NX: execute disable.If CPUID.80000001H:EDX.NX [bit 20] = 1, IA32_EFER.NXE may be set to 1, allowing software to disable 
execute access to selected pages (see Section 4.6). (Processors that do not support CPUID function 
80000001H do not allow IA32_EFER.NXE to be set to 1.)
•Page1GB: 1-GByte pages.If CPUID.80000001H:EDX.Page1GB [bit 26] = 1, 1-GByte pa ges may be supported with 4-level paging and 5-
level paging (see Section 4.5).
•LM: IA-32e mode support.
If CPUID.80000001H:EDX.LM [bit 29] = 1, IA32_EFER.LME ma y be set to 1, enabling IA-32e mode (with either 
4-level paging or 5-level paging). (Processors that do not support CPUID function 80000001H do not allow 
IA32_EFER.LME to be set to 1.)
•CPUID.80000008H:EAX[7:0] reports the physical-address wi dth supported by the processor. (For processors 
that do not support CPUID function 80000008H, the width is generally 36 if CPUID.01H:EDX.PAE [bit 6] = 1 and 32 otherwise.) This width is referred to as MAXPHYADDR. MAXPHYADDR is at most 52.
•CPUID.80000008H:EAX[15:8] reports the linear-address wi dth supported by the processor. Generally, this 
value is reported as follows:
— If CPUID.80000001H:EDX.LM [bit 29] = 0, the value is reported as 32.
— If CPUID.80000001H:EDX.LM [bit 29] = 1 and CPUI D.(EAX=07H,ECX=0):ECX.LA57 [bit 16] = 0, the 
value is reported as 48.
— If CPUID.(EAX=07H,ECX=0):ECX.LA57 [bit 16] = 1, the value is reported as 57.
(Processors that do not support CPUID function 80000008H, support a linear-address width of 32.)Vol. 3A 4-7PAGING
4.2 HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW
All four paging modes translate linear addresses using hierarchical paging structures . This section provides an 
overview of their operation. Section 4.3, Section 4.4, Section 4.5, and Section 4.6 provide details for the four 
paging modes.
Every paging structure is 4096 Bytes in size and comprises a number of individual entries . With 32-bit paging, 
each entry is 32 bits (4 bytes); there are thus 1024 entrie s in each structure. With the other paging modes, each 
entry is 64 bits (8 bytes); there are thus 512 entries in  each structure. (PAE paging includes one exception, a 
paging structure that is 32 bytes in size, containing 4 64-bit entries.)
The processor uses the upper portion of a linear address to id entify a series of paging-structure entries. The last of 
these entries identifies the physical address of the re gion to which the linear address translates (called the page 
frame ). The lower portion of the linear address (called the page offset ) identifies the specific address within that 
region to which the linear address translates.
Each paging-structure entry contains a physical address, which is either the address of another paging structure or 
the address of a page frame. In the first case, the entry is said to reference  the other paging structure; in the 
latter, the entry is said to map a page .
The first paging structure used for any translation is located at the physical address in CR3.1 A linear address is 
translated using the following iterative procedure. A port ion of the linear address (initially the uppermost bits) 
selects an entry in a paging structure (initially the one lo cated using CR3). If that entr y references another paging 
structure, the process continues with that paging structure and with the portion of the linear address immediately 
below that just used. If instead the entry maps a page, th e process completes: the physical address in the entry is 
that of the page frame and the remaining lower po rtion of the linear address is the page offset.
The following items give an example for each of the fo ur paging modes (each example locates a 4-KByte page 
frame):
•With 32-bit paging, each paging structure comprises 1024 = 210 entries. For this reason, the translation 
process uses 10 bits at a time from a 32-bit linear addr ess. Bits 31:22 identify the first paging-structure entry 
and bits 21:12 identify a second. The latter identifies the page frame. Bits 11:0 of the linear address are the 
page offset within the 4-KByte page frame. (See Figure 4-2 for an illustration.)
•With PAE paging, the first paging structure comprises only 4 = 22 entries. Translation thus begins by using 
bits 31:30 from a 32-bit linear address to identify the first paging-structure entry. Other paging structures 
comprise 512 =29 entries, so the process continues by using 9 bits at a time. Bits 29:21 identify a second 
paging-structure entry and bits 20:12 identify a third. Th is last identifies the page frame. (See Figure 4-5 for 
an illustration.)
•With 4-level paging, each paging structure comprises 512 = 29 entries and translation uses 9 bits at a time 
from a 48-bit linear address. Bits 47:39 identify the fi rst paging-structure entry, bits 38:30 identify a second, 
bits 29:21 a third, and bits 20:12 identify a fourth. Agai n, the last identifies the page frame. (See Figure 4-8 
for an illustration.)
•5-level paging is similar to 4-level paging except th at 5-level paging translates 57-bit linear addresses. 
Bits 56:48 identify the first paging-structure entry, while the remaining bits are used as with 4-level paging.
The translation process in each of the examples above co mpletes by identifying a page frame; the page frame is 
part of the translation  of the original linear address. In some cases, however, the paging structures may be 
configured so that the translation process terminates befo re identifying a page frame. This occurs if the process 
encounters a paging-structure entry that is marked “not pres ent” (because its P flag — bit 0 — is clear) or in which 
a reserved bit is set. In this case, there is no translation for the linear address; an access to that address causes a page-fault exception (see Section 4.7).
In the examples above, a paging-structure entry maps a pa ge with a 4-KByte page frame when only 12 bits remain 
in the linear address; entries identified earlier always reference other paging structures. That may not apply in 
other cases. The following items identify when an entry ma ps a page and when it references another paging struc-
ture:
•If more than 12 bits remain in the linear address, bit 7  (PS — page size) of the current paging-structure entry 
is consulted. If the bit is 0, the entry references another paging structure; if the bit is 1, the entry maps a page.
1. If HLAT paging is in use, a different mechanism is used to id entify the first paging structure. See Section 4.5 for more info rmation.4-8 Vol. 3APAGING
•If only 12 bits remain in the linear address, the curre nt paging-structure entry always maps a page (bit 7 is 
used for other purposes).
If a paging-structure entry maps a page when more than 12 bits remain in the linear address, the entry identifies 
a page frame larger than 4 KBytes. For example, 32-bit pa ging uses the upper 10 bits of a linear address to locate 
the first paging-structure entry; 22 bits remain. If that entry maps a page, the page frame is 222 Bytes = 4 MBytes. 
32-bit paging can use 4-MByte pages if CR4.PSE = 1. The other paging modes can use 2-MByte pages (regardless 
of the value of CR4.PSE). 4-level paging and 5-level pagi ng can use 1-GByte pages if the processor supports them 
(see Section 4.1.4).
Paging structures are given different names based on their uses in the translation process. Table 4-2 gives the 
names of the different paging structures. It also provides, for each structure, the source of the physical address 
used to locate it (CR3 or a different paging-structure entr y); the bits in the linear address used to select an entry 
from the structure; and details of whether and how such an entry can map a page.
Table 4-2.   Paging Structures in the Different Paging Modes
Paging StructureEntry 
NamePaging ModePhysical 
Address of 
StructureBits Selecting 
EntryPage Mapping
PML5 table PML5E32-bit, PAE, 4-level N/A
5-level CR31
NOTES:
1. If HLAT paging is in use, a different mechanism is used to identify the first paging structure. See Section 4.5 for more inf ormation.56:48 N/A (PS must be 0)
PML4 table PML4E32-bit, PAE N/A
4-level CR31
47:39 N/A (PS must be 0)
5-level PML5E
Page-directory-
pointer tablePDPTE32-bit N/A
PAE CR3 31:30 N/A (PS must be 0)4-level, 5-level PML4E 38:30 1-GByte page if PS=1
2
2. Not all processors support 1-GByte pages; see Section 4.1.4.Page directory PDE32-bit CR3 31:22 4-MByte page if PS=13
3. 32-bit paging ignores the PS flag in a PDE (and uses the entr y to reference a page table) unless CR4.PSE = 1. Not all process ors sup-
port 4-MByte pages with 32-bit paging; see Section 4.1.4.PAE, 4-level, 5-level PDPTE 29:21 2-MByte page if PS=1
Page table PTE32-bit
PDE21:12

Address of 
NOTES:
2
PDE21:12
4-KByte page
PAE, 4-level, 5-level 20:12Vol. 3A 4-9PAGING
4.3 32-BIT PAGING
A logical processor uses 32-bit paging if CR0.PG = 1 an d CR4.PAE = 0. 32-bit paging translates 32-bit linear 
addresses to 40-bit physical addresses.1 Although 40 bits corresponds to 1 TByte, linear addresses are limited to 
32 bits; at most 4 GBytes of linear-address space may be accessed at any given time.
32-bit paging uses a hierarchy of paging structures to pr oduce a translation for a linear address. CR3 is used to 
locate the first paging-structure, the page directory. Ta ble 4-3 illustrates how CR3 is used with 32-bit paging.
32-bit paging may map linear addresses to either 4-KByte pages or 4-MByte pages. Figure 4-2 illustrates the 
translation process when it uses a 4-KByte page; Figure 4-3 covers the case of a 4-MByte page. The following 
items describe the 32-bit paging process in more de tail as well has how the page size is determined:
•A 4-KByte naturally aligned page directory is located at the physical address specified in bits 31:12 of CR3 (see 
Table 4-3). A page directory comprises 1024 32-bit entries (PDEs). A PDE is selected using the physical address 
defined as follows:
— Bits 39:32 are all 0.
— Bits 31:12 are from CR3.
— Bits 11:2 are bits 31:22 of the linear address.—B i t s 1 : 0  a r e  0 .
Because a PDE is identified using bits 31:22 of the linear address, it controls access to a 4-Mbyte region of the 
linear-address space. Use of the PDE depends on CR4.PSE and the PDE’s PS flag (bit 7):
•If CR4.PSE = 1 and the PDE’s PS flag is 1, the PDE ma ps a 4-MByte page (see Table 4-4). The final physical 
address is computed as follows:
— Bits 39:32 are bits 20:13 of the PDE.— Bits 31:22 are bits 31:22 of the PDE.
2
— Bits 21:0 are from the original linear address.
•If CR4.PSE = 0 or the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is located at the physical 
address specified in bits 31:12 of the PDE (see Table 4-5 ). A page table comprises 1024 32-bit entries (PTEs). 
A PTE is selected using the physical address defined as follows:
— Bits 31:12 are from the PDE.
— Bits 11:2 are bits 21:12 of the linear address.—B i t s 1 : 0  a r e  0 .
•Because a PTE is identified using bits 31:12 of the linear address, every PTE maps a 4-KByte page (see 
Table 4-6). The final physical address is computed as follows:
— Bits 31:12 are from the PTE.
— Bits 11:0 are from the original linear address.
If a paging-structure entry’s P flag (bit 0) is 0 or if the en try sets any reserved bit, the entry is used neither to refer-
ence another paging-structure entry nor to map a page. There is no translation for a linear address whose transla-tion would use such a paging-structure entry; a reference to such a linear address causes a page-fault exception 
(see Section 4.7).
1. Bits in the range 39:32 are 0 in any physical address used by 32-bit paging except those used to map 4-MByte pages. If the pr oces-
sor does not support the PSE-36 mechanism, this is true also for physical addresses used to map 4-MByte pages. If the processor  
does support the PSE-36 mechanism and MAXPHYADDR < 40, bits in the range 39:MAXPHYADDR are 0 in any physical address used to map a 4-MByte page. (The corresponding bits are reserved in PDEs.) See Section 4.1.4 for ho w to determine MAXPHYADDR and 
whether the PSE-36 mechanism is supported.
2. The upper bits in the final physical address do not all come from corresponding positions in the PDE; the physical-address bi ts in the 
PDE are not all contiguous.4-10 Vol. 3APAGING
With 32-bit paging, there are reserved bits only if CR4.PSE = 1:
•If the P flag and the PS flag (bit 7) of a PDE are both 1, the bits reserved depend on MAXPHYADDR, and whether 
the PSE-36 mechanism is supported:1
— If the PSE-36 mechanism is not supported, bits 21:13 are reserved.
— If the PSE-36 mechanism is supported, bits 21:(M–19) are reserved, where M is the minimum of 40 and 
MAXPHYADDR.
•If the PAT is not supported:2
— If the P flag of a PTE is 1, bit 7 is reserved.
— If the P flag and the PS flag of a PDE are both 1, bit 12 is reserved.
(If CR4.PSE = 0, no bits are reserved with 32-bit paging.)
A reference using a linear address that is successfully tran slated to a physical address is performed only if allowed 
by the access rights of the translation; see Section 4.6.
1. See Section 4.1.4 for how to determine MAXPHYA DDR and whether the PSE-36 mechanism is supported.
2. See Section 4.1.4 for how to determine whether the PAT is supported.Figure 4-2.  Linear-Address Translatio n to a 4-KByte Page using 32-Bit Paging0
Directory Table Offset
PDE with PS=0
CR3Page Table
PTE4-KByte Page
Physical Address31 21 11 12 22Linear Address
321012
10
20
20Vol. 3A 4-11PAGING
Figure 4-4 gives a summary of the formats of CR3 and the paging-structure entries with 32-bit paging. For the 
paging structure entries, it identifies separately the form at of entries that map pages, those that reference other 
paging structures, and those that do neither because they  are “not present”; bit 0 (P) and bit 7 (PS) are high-
lighted because they determine how such an entry is used.Figure 4-3.  Linear-Address Translatio n to a 4-MByte Page using 32-Bit Paging
3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210
Address of page directory1
NOTES:
1. CR3 has 64 bits on processors supp orting the Intel-64 archit ecture. These bits are ignored with 32-bit paging.IgnoredP
C
DP
W
TIgnored CR3
Bits 31:22 of address
of 4MB page frameReserved
(must be 0)Bits 39:32 of 
address2
2. This example illustrates a processor in which MAXPHYADDR is 36. If this value is larg er or smaller, the nu mber of bits reser ved in 
positions 20:13 of a PDE mapping a 4-MByte page will change.P
A
TIgnored G 1DAP
C
DP
W
TU
/
SR
/
W1PDE:
4MB
page
Address of page table Ignored 0I
gnAP
C
DP
W
TU
/
SR
/
W1 PDE:
page
table
Ignored 0PDE:
not
present
Address of 4KB page frame Ignored GP
A
TDAP
C
DP
W
TU
/
SR
/
W1PTE:
4KB
page
Ignored 0PTE:
not
present
Figure 4-4.  Formats of CR3 and Pagi ng-Structure Entries with 32-Bit Paging0
Directory Offset
PDE with PS=1
CR34-MByte Page
Physical Address31 21 22Linear Address
1022
32184-12 Vol. 3APAGING
 
Table 4-3.  Use of CR3 with 32-Bit Paging
Bit 
Position(s)Contents
2:0 Ignored
3 (PWT) Page-level write-through; indirectly determines the memory type used to access the page directory during linear-
address translation (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly  determines the memory type used to ac cess the page directory during linear-
11:5 Ignored
31:12 Physical address of the 4-KByte aligned page directory used for linear-address translation63:32 Ignored (these bits exis t only on processors supportin g the Intel-64 architecture)
Table 4-4.  Format of a 32-Bit Page-Directory Entry  that Maps a 4-MByte Page
Bit 
0 (P) Present; must be 1 to map a 4-MByte page
1 (R/W) Read/write; if 0, writes may not be allowed to th e 4-MByte page referenced by this entry (see Section 4.6)
2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 4-MByte page referenced by this entry (see Section 
4.6)
3 (PWT) Page-level write-through; indirectly determines the me mory type used to access the 4-MByte page referenced by 
this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access the 4-MByte page referenced by 
5 (A) Accessed; indica tes whether software has accessed the 4-MByte page referenced by this entry (see Section 4.8)
6 (D) Dirty; indicates whether software has written to the 4-MByte page referenced by this entry (see Section 4.8)
7 (PS) Page size; must be 1 (otherwise, this entry references a page table; see Table 4-5)
8 (G) Global; if CR4.PGE = 1, determines whether the tran slation is global (see Section 4.10); ignored otherwise
11:9 Ignored
12 (PAT) If the PAT is supported, indirectly determines the memory  type used to access the 4-MByte page referenced by this 
entry (see Section 4.9.2); otherwise, reserved (must be 0)1
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.(M–20):13 Bits (M–1):32 of physical address of the 4-MByte page referenced by this entry2
2. If the PSE-36 mechanism is not supported, M is 32, and this row does not apply. If the PSE-36 mechanism is supported, M is t he min-
imum of 40 and MAXPHYADDR (this row does not apply if MAXPHYADDR = 32). See Section 4.1.4 for how to determine MAXPHY-
ADDR and whether the PSE-36 mechanism is supported.21:(M–19) Reserved (must be 0)
31:22 Bits 31:22 of physical address of the 4-MByte page referenced by this entryVol. 3A 4-13PAGING
Table 4-5.  Format of a 32 -Bit Page-Directory Entry th at References a Page Table
Bit 
0 (P) Present; must be 1 to reference a page table

NOTES:
Bit 
1 (R/W) Read/write; if 0, writes may no t be allowed to the 4-MByt e region controlled by this entry (see Section 4.6)
2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 4-MByte region controlled by this entry (see Section 
4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access the page table referenced by this 
entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access the page table referenced by this 
5 (A) Accessed; indicates whet her this entry has been used for linear-address translation (see Section 4.8)
6I g n o r e d7 (PS) If CR4.PSE = 1, must be 0 (oth erwise, this entry maps a 4-MByte page; see Table 4-4); otherwise, ignored
11:8 Ignored
31:12 Physical address of 4-KByte aligned page table referenced by this entry
Table 4-6.  Format of a 32-Bit Page -Table Entry that Maps a 4-KByte Page
Bit 
0 (P) Present; must be 1 to map a 4-KByte page
1 (R/W) Read/write; if 0, writes may not be allowed to the 4-KByte page referenced by this entry (see Section 4.6)
2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 4-KByte page referenced by this entry (see Section 
4.6)
3 (PWT) Page-level write-through; indirectly determines the memo ry type used to access the 4-KByte page referenced by this 
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access the 4-KByte page referenced by this 
5 (A) Accessed; indicates whethe r software has accessed the 4-KByte page referenced by this entry (see Section 4.8)
6 (D) Dirty; indicates whether software has written to the 4-KByte page referenced by this entry (see Section 4.8)
7 (PAT) If the PAT is supported, indirectly determines the memory  type used to access the 4-KB yte page referenced by this 
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.8 (G) Global; if CR4.PGE = 1, determines whether the tran slation is global (see Section 4.10); ignored otherwise
11:9 Ignored31:12 Physical address of the 4-KByte page referenced by this entry4-14 Vol. 3APAGING
4.4 PAE PAGING
A logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 0. PAE paging translates 
32-bit linear addresses to 52-bit physical addresses.1 Although 52 bits corresponds to 4 PBytes, linear addresses 
are limited to 32 bits; at most 4 GBytes of linear-address space may be accessed at any given time.
With PAE paging, a logical processor maintains a set of four  (4) PDPTE registers, which are loaded from an address 
in CR3. Linear address are translated using 4 hierarchie s of in-memory paging structures, each located using one 
of the PDPTE registers. (This is different from the other paging modes, in which there is one hierarchy referenced 
by CR3.)
Section 4.4.1 discusses the PDPTE registers. Section 4.4. 2 describes linear-address translation with PAE paging.
4.4.1 PDPTE Registers
When PAE paging is used, CR3 references the base of a 32-Byte page-directory-pointer table . Table 4-7 illus-
trates how CR3 is used with PAE paging.
The page-directory-pointer-table comprises four (4) 64-bit entries called PDPTEs. Each PDPTE controls access to a 
1-GByte region of the linear-address space. Corresponding to the PDPTEs, the logical processor maintains a set of 
four (4) internal, non-architectural PDPTE registers, called PDPTE0, PDPTE1, PDPTE2, and PDPTE3. The logical 
processor loads these registers from the PDPTEs in memory as part of certain operations:
•If PAE paging would be in use following an execution of  MOV to CR0 or MOV to CR4 (see Section 4.1.1) and the 
instruction is modifying any of CR0.CD, CR0.NW, CR0.PG, CR4.PAE, CR4.PGE, CR4.PSE, or CR4.SMEP; then the 
PDPTEs are loaded from the address in CR3.
•If MOV to CR3 is executed while the logical processor is using PAE paging, the PDPTEs are loaded from the 
address being loaded into CR3.
•If PAE paging is in use and a task switch changes the va lue of CR3, the PDPTEs are loaded from the address in 
the new CR3 value.
•Certain VMX transitions load the PDPTE registers. See Section 4.11.1.
Table 4-8 gives the format of a PDPTE. If any of the PDPTEs  sets both the P flag (bit 0) and any reserved bit, the 
MOV to CR instruction causes a general-protection  exception (#GP(0)) and the PDPTEs are not loaded.2 As shown 
in Table 4-8, bits 2:1, 8:5, and 63:MAXPHYADDR are reserved in the PDPTEs.
1. If MAXPHYADDR < 52, bits in the range 51: MAXPHYADDR will be 0 in any physical address used by PAE paging. (The corresponding 
bits are reserved in the paging-s tructure entries.) See Section 4.1.4 for how to determine MAXPHYADDR.Table 4-7.  Use of CR3 with PAE Paging
Bit 
4:0 Ignored
31:5 Physical address of the 32-Byte aligned page-directory-pointer table used for linear-address translation
63:32 Ignored (these bits exist only on proce ssors supporting the In tel-64 architecture)
2. On some processors, reserved bits are checked even in PDPTEs in which the P flag (bit 0) is 0.Vol. 3A 4-15PAGING
4.4.2 Linear-Address Tran slation with PAE Paging
PAE paging may map linear addresses to either 4-KByte pa ges or 2-MByte pages. Figure 4-5 illustrates the trans-
lation process when it produces a 4-KByte page; Figure 4- 6 covers the case of a 2-MByte page. The following items 
describe the PAE paging process in more detail as  well has how the page size is determined:
•Bits 31:30 of the linear address select a PDPTE register (see Section 4.4.1); this is PDPTE i, where i is the value 
of bits 31:30.1 Because a PDPTE register is identified using bits 31:30 of the linear address, it controls access 
to a 1-GByte region of the linear-address space. If the P flag (bit 0) of PDPTE i is 0, the processor ignores bits 
63:1, and there is no mapping for th e 1-GByte region controlled by PDPTE i. A reference using a linear address 
in this region causes a page-fault exception (see Section 4.7).
•If the P flag of PDPTE i is 1, 4-KByte naturally aligned page directory is located at the physical address specified 
in bits 51:12 of PDPTE i (see Table 4-8 in Section 4.4.1). A page directory comprises 512 64-bit entries (PDEs). 
A PDE is selected using the physical address defined as follows:
— Bits 51:12 are from PDPTE i.
— Bits 11:3 are bits 29:21 of the linear address.
—B i t s 2 : 0  a r e  0 .
Because a PDE is identified using bits 31:21 of the linear address, it controls access to a 2-Mbyte region of the 
linear-address space. Use of the PDE depends on its PS flag (bit 7):
•If the PDE’s PS flag is 1, the PDE maps a 2-MByte page (see Table 4-9). The final physical address is computed 
— Bits 51:21 are from the PDE.— Bits 20:0 are from the original linear address.
•If the PDE’s PS flag is 0, a 4-KByte naturally aligned pa ge table is located at the physical address specified in 
bits 51:12 of the PDE (see Table 4-10). A page table comprises 512 64-bit entries (PTEs). A PTE is selected 
using the physical address defined as follows:
— Bits 51:12 are from the PDE.Table 4-8.  Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE)
Bit 
0 (P) Present; must be 1 to reference a page directory
2:1 Reserved (must be 0)
3 (PWT) Page-level write-through; indirectly determines the memo ry type used to access the page directory referenced by 
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access the page directory referenced by 
8:5 Reserved (must be 0)11:9 Ignored(M–1):12 Physical address of 4-KByte aligned page directory referenced by this entry
1
63:M Reserved (must be 0)
NOTES:
1. M is an abbreviation fo r MAXPHYADDR, which is at most 52; see Section 4.1.4.
1. With PAE paging, the processor does not use CR3 when translating a linear address (as it does in the other paging modes). It does 
not access the PDPTEs in the pa ge-directory-pointer table during linear-address translation.4-16 Vol. 3APAGING
— Bits 11:3 are bits 20:12 of the linear address.
— Bits 2:0 are 0.
Table 4-11). The final physical address is computed as follows:
— Bits 51:12 are from the PTE.
If the P flag (bit 0) of a PDE or a PTE is 0 or if a PDE or  a PTE sets any reserved bit, the entry is used neither to 
reference another paging-structure entry nor to map a pa ge. There is no translation for a linear address whose 
translation would use such a paging-structure entry; a re ference to such a linear address causes a page-fault 
exception (see Section 4.7).
The following bits are reserved with PAE paging:
•If the P flag (bit 0) of a PDE or a PTE is 1, bits 62:MAXPHYADDR are reserved.

•If the P flag and the PS flag (bit 7) of a PDE are both 1, bits 20:13 are reserved.
•If IA32_EFER.NXE = 0 and the P flag of a PDE or a PTE is 1, the XD flag (bit 63) is reserved.
•If the PAT is not supported:1
1. See Section 4.1.4 for how to determine whether the PAT is supported.Figure 4-5.  Linear-Address Translation to a 4-KByte Page using PAE Paging0
PDE with PS=0Page Table
Physical Address31 20 11 12 21Linear Address
PDPTE value30 29
PDPTE RegistersDirectory Pointer
2912
9
40
4040Vol. 3A 4-17PAGING
Figure 4-6.  Linear-Address Translation to a 2-MByte Page using PAE Paging
Table 4-9.  Format of a PAE Page-Dir ectory Entry that Maps a 2-MByte Page
Bit 
0 (P) Present; must be 1 to map a 2-MByte page
1 (R/W) Read/write; if 0, writes may no t be allowed to the 2-MByt e page referenced by this entry (see Section 4.6)
2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte page referenced by this entry (see Section 
4.6)
3 (PWT) Page-level write-through; indirectly determines the me mory type used to access the 2-MByte page referenced by 
4 (PCD) Page-level cache disable; indirectly determines the memo ry type used to access the 2-MB yte page referenced by this 
5 (A) Accessed; indica tes whether software has accessed the 2-MByte page referenced by this entry (see Section 4.8)
6 (D) Dirty; indicates whether software has written to the 2-MByte page referenced by this entry (see Section 4.8)
7 (PS) Page size; must be 1 (otherwise, this entry references a page table; see Table 4-10)
12 (PAT) If the PAT is supported, indirectly  determines the memory type  used to access the 2-MByte page referenced by this 
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.20:13 Reserved (must be 0)
(M–1):21 Physical address of the 2-MB yte page referenced by this entry
62:M Reserved (must be 0)
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowe d from the 2-MByte page controlled by 
this entry; see Section 4.6); otherwise, reserved (must be 0)0
PDE with PS=12-MByte Page
Physical Address31 20 21Linear Address
PDPTE RegistersDirectory
Pointer
2921
31
404-18 Vol. 3APAGING
Table 4-10.  Format of a PAE Page-Directo ry Entry that References a Page Table
Bit 
1 (R/W) Read/write; if 0, writes may not be allowed to th e 2-MByte region controlled by this entry (see Section 4.6)
2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte region controlled by this entry (see 
Section 4.6)
3 (PWT) Page-level write-through; indirectly determines the memo ry type used to access the pa ge table referenced by this 
4 (PCD) Page-level cache disable; indirectly determines the memo ry type used to access the page table referenced by this 
5 (A) Accessed; indicate s whether this entry has been used for li near-address translation (see Section 4.8)
6I g n o r e d7 (PS) Page size; must be 0 (otherwise, this entry maps a 2-MByte page; see Table 4-9)
(M–1):12 Physical address of 4-KByte aligned page table referenced by this entry62:M Reserved (must be 0)
63 (XD) If IA32_EFER.NXE = 1, execute-disa ble (if 1, instruction fetches are not allowed from the 2-MByte region controlled 
by this entry; see Section 4.6); otherwise, reserved (must be 0)
Table 4-11.  Format of a PAE Page-T able Entry that Maps a 4-KByte Page
Bit 
1 (R/W) Read/write; if 0, writes may not be allowed to th e 4-KByte page referenced by this entry (see Section 4.6)
4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access the 4-KByte page referenced by 
5 (A) Accessed; indicates whether software  has accessed the 4-KByte page referenced by this entry (see Section 4.8)
6 (D) Dirty; indicates whether software has written to the 4-KByte page referenced by this  entry (see Section 4.8)
7 (PAT) If the PAT is supported, indirectly determines the memo ry type used to access the 4-KByte page referenced by this 
8 (G) Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwiseVol. 3A 4-19PAGING
Figure 4-7 gives a summary of the formats of CR3 and the pa ging-structure entries with PAE paging. For the paging 
structure entries, it identifies separately the format of entries that map pages, those that reference other paging 
structures, and those that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted 
because they determine how a paging-structure entry is used.11:9 Ignored
(M–1):12 Physical address of the 4-KByte page referenced by this entry
62:M Reserved (must be 0)63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 4-KByte page controlled by 
this entry; see Section 4.6); otherwise, reserved (must be 0)
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.
6
36
26
16
05
95
85
75
65
55
45
35
25
1M1
NOTES:
1. M is an abbreviation for MAXPHYADDR.M-13
23
13
02
92
82
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
09876543210
Ignored2
2. CR3 has 64 bits only on processors supporting the Inte l-64 architecture. These bits are ignored with PAE paging.Address of page-directory-pointer table Ignored CR3
Reserved3
3. Reserved fields must be 0.Address of page directory Ign. Rsvd.P
C
DP
W
TRs
vd1PDPTE:
present
Ignored 0PDTPE:
not
present
X
D
4
4. If IA32_EFER.NXE = 0 and the P flag of a PDE or a PTE is 1, the XD flag  (bit 63) is reserved.ReservedAddress of
2MB page frameReservedP
A
TIgn. G 1DAP
C
DP
W
TU
/SR
/
W1PDE:
2MB
page
X
DReserved Address of page table Ign. 0I
g
nAP
C
DP
W
TU
/SR
/
W1PDE:
page
table
not
present
X
DReserved Address of 4KB page frame Ign. GP
A
TDAP
C
DP
W
TU
/SR
/
W1PTE:
4KB
page
not
present
Figure 4-7.  Formats of CR3 and Paging-Structure Entries with PAE PagingTable 4-11.  Format of a PAE Page-Table Entry that Maps a 4-KByte Page (Contd.)
Bit 
Position(s)Contents4-20 Vol. 3APAGING
4.5 4-LEVEL PAGING AND 5-LEVEL PAGING
Because the operation of 4-level paging and 5-level paging is very similar, they are described together in this 
section. The following items highlight the distinctions between the two paging modes:
•A logical processor uses 4-level paging if CR0.PG = 1, CR4.PAE = 1, IA32_EFER.LME = 1, and CR4.LA57 = 0. 
4-level paging translates 48-bit linear addresses to 52-bit physical addresses.1 Although 52 bits corresponds to 
4 PBytes, linear addresses are limited to 48 bits; at most 256 TBytes of linear-address space may be accessed 
at any given time.
•A logical processor uses 5-level paging if CR0.PG = 1, CR4.PAE = 1, IA32_EFER.LME = 1, and CR4.LA57 = 1. 
5-level paging translates 57-bit linear addresses to 52-b it physical addresses. Thus, 5-level paging supports a 
linear-address space sufficient to access the entire physical-address space.
4.5.1 Ordinary Paging and HLAT Paging
There are two forms of 4-level paging and 5-level paging th at differ principally with regard to how linear-address 
translation identifies the first paging structure.
The normal form is called ordinary paging , and it uses CR3 to locate the first paging structure, similar to what is 
done for 32-bit paging. Section 4.5.2 provides details of this use of CR3.
An alternative form of paging may be used with the VM X feature called hypervisor-managed linear-address trans-
lation (HLAT). Called HLAT paging , this form is used only in VMX non-root  operation and only if the “enable HLAT” 
VM-execution control is 1.2 HLAT paging locates the first paging structure using a VM-execution control field in the 
VMCS called the HLAT pointer  (HLATP ). Section 4.5.3 provides details.
Whether HLAT paging is used to translate a specific lin ear address depends on the address and on the value of a 
VM-execution control field in the VMCS called the HLAT prefix size :

•If the HLAT prefix size is zero, every linear address is translated using HLAT paging.
•If the HLAT prefix size is not zero, a linear address is translated using HLAT paging if bit 63 of the address is 1.3 
The address is translated using ordinary paging if bit 63 of the address is 0.
In some cases, HLAT paging may specify that a translation of a linear address must be restarted. When this occurs, 
the linear address is then translated using ordinary paging  (starting with a paging structure identified using CR3). 
The situations leading to this restart are detailed in Sectio n 4.5.4, and additional details  of the restart process are 
given in Section 4.5.5.
4.5.2 Use of CR3 with Ordinary 4-Level Paging and 5-Level Paging
Ordinary 4-level paging and 5-level paging each translate linear addresses using a hierarchy of in-memory paging 
structures located using the contents of CR3, which is used  to locate the first paging structure. For 4-level paging, 
this is the PML4 table, and for 5-level paging it is the PM L5 table. Use of CR3 with 4-level paging and 5-level paging 
depends on whether process-context identifiers (P CIDs) have been enabled by setting CR4.PCIDE:
•Table 4-12 illustrates how CR3 is used with 4-leve l paging and 5-level paging if CR4.PCIDE = 0.
1. If MAXPHYADDR < 52, bits in the range 51:MAXPHYADDR will be 0 in any physical address used by 4-level paging. (The correspond-
ing bits are reserved in the paging-structure entrie s.) See Section 4.1.4 for how to determine MAXPHYADDR.
2. HLAT paging is used only with 4-level paging and 5-level paging. It is never used with 32-bit paging or PAE paging, regardles s of the 
value of the “enable HLAT” VM-execution control.
3. This behavior applies if the CPU enumerates a maximum HLAT prefix size of 1 in IA32_VMX_EPT_VPID_CAP[53:48] (see Appendix 
A.10). Behavior when a different value is enumerated is not currently defined.Table 4-12.  Use of CR3 with 4-Level Paging and 5-level Paging and CR4.PCIDE = 0
Bit 
2:0 IgnoredVol. 3A 4-21PAGING
•Table 4-13 illustrates how CR3 is used with 4-level paging and 5-level paging if CR4.PCIDE = 1.
After software modifies the value of CR4.PCIDE, the logi cal processor immediately begins using CR3 as specified 
for the new value. For example, if software changes CR4. PCIDE from 1 to 0, the current PCID immediately changes 
from CR3[11:0] to 000H (see also Section 4.10.4.1). In addition, the logical processor subsequently determines 
the memory type used to access the PML4 table using CR 3.PWT and CR3.PCD, which had been bits 4:3 of the PCID.
4.5.3 Use of HLATP with HLAT 4-Level Paging and 5-Level Paging
With HLAT paging, 4-level paging and 5-level paging each translate linear addresses using a hierarchy of in-
memory paging structures located using the value of HLAT P (a VM-execution control field in the VMCS), which is 
used to locate the first paging structure. For 4-level paging, this is the PML4 table, and for 5-level paging it is the PML5 table.
HLATP has the same format as that given for CR3 in Tabl e 4-12, with the exception that bits 2:0 and bits 11:5 are 
reserved and must be zero (these bits are checked by  VM entry). HLATP does not contain a PCID value. HLAT 
paging with CR4.PCIDE = 1 uses the PCID value in CR3[11:0].3 (PWT) Page-level write-through; indirectly determines the memory type used to access th e PML4 table or PML5 table 
during linear-address translation (see Section 4.9.2)
4 (PCD) Page-level cache disable; indirectly determines the memory  type used to access the PML4  table or PML5 table during 
linear-address translation (see Section 4.9.2)
M–1:12 Physical address of the 4-KByte aligned PML4 table or PML5 table used for linear-address translation
1
NOTES:
1. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.
Table 4-13.  Use of CR3 with 4-Level Paging and 5-Level Paging and CR4.PCIDE = 1
Bit 
11:0 PCID (see Section 4.10.1)1
NOTES:
1. Section 4.9.2 explains how the processor determines the memory type used to access the PML4 table during linear-address tran sla-
tion with CR 4.PCIDE = 1.M–1:12 Physical address of the 4-KByte aligned PML4 table used for linear-address translation2
2. M is an abbreviation fo r MAXPHYADDR, which is at most 52; see Section 4.1.4.63:M Reserved (must be 0)3
3. See Section 4.10.4.1 for use of bit 63 of the source operand of the MOV to CR3 instruction.Table 4-12.  Use of CR3 with 4-Level Paging and 5-level Paging and CR4.PCIDE = 0 (Contd.)
Bit 
Position(s)Contents4-22 Vol. 3APAGING
4.5.4 Linear-Address Translation with  4-Level Paging and 5-Level Paging
4-level paging and 5-level paging may map linear addre sses to 4-KByte pages, 2-MByte pages, or 1-GByte pages.1 
Figure 4-8 illustrates the translation process for 4-level pa ging when it produces a 4-KByte page; Figure 4-9 covers 
the case of a 2-MByte page, and Figure 4-10 the case of a 1- GByte page. (The process for 5-level paging is similar.)
1. Not all processors support 1-GByte pages; see Section 4.1.4.Figure 4-8.  Linear-Address Translatio n to a 4-KByte Page Using 4-Level PagingDirectory Ptr
PTELinear Address
Page Table
PDPTE
CR3 or HLATP39 38
Pointer Table99
40129
404-KByte PageOffset
Physical Addr
PDE with PS=0Table0 1112 2021
Directory30 29
Page-Directory-
Page-DirectoryPML447
9
PML4E404040Vol. 3A 4-23PAGING
Figure 4-9.  Linear-Address Translation to a 2-MByte Page using 4-Level Paging
Figure 4-10.  Linear-Address Translation to a 1-GByte Page using 4-Level PagingDirectory PtrLinear Address
PDPTE
4021
312-MByte PageOffset
PDE with PS=10 2021
9
PML4E4040
Directory PtrLinear Address
PDPTE with PS=1
Pointer Table9
4030
221-GByte PageOffset
Physical Addr0 30 29
Page-Directory-PML447
9
PML4E404-24 Vol. 3APAGING
4-level paging and 5-level paging associate with each linear address a protection key . Section 4.6 explains how 
the processor uses the protection key in its determination of the access rights of each linear address.
The remainder of this section describes the translation proc ess used by 4-level paging and 5-level paging in more 
detail, as well has how the page size and protection ke y are determined. Because the process used by the two 
paging modes is similar, they are described together, with any differences identified, in the following items:
•With 5-level paging, a 4-KByte naturally aligned PML5 ta ble is located at the physical address specified in 
bits 51:12 of CR3 (see Table 4-12). (4-level paging does  not use a PML5 table and omits this step.) A PML5 
table comprises 512 64-bit entries (PML5Es). A PML5E is se lected using the physical address defined as follows:
— Bits 51:12 are from CR3 or HLATP.
— Bits 11:3 are bits 56:48 of the linear address.
— Bits 2:0 are all 0.
Because a PML5E is identified using bits 56:48 of the linear address, it controls access to a 256-TByte region of 
the linear-address space.
With HLAT paging, if bit 11 of the PML5E is 1, translat ion is restarted with ordinary paging with a maximum 
page size of 256-TBytes (see Section 4.5.5). Otherwise,  the translation process continues as described in the 
next item.
•A 4-KByte naturally aligned PML4 table is located at the physical address specified in bits 51:12 of CR3 (for 4-
level paging; see Table 4-12) or in bits 51:12 of the PML5E (for 5-level paging; see Table 4-14). A PML4 table 
comprises 512 64-bit entries (PML4Es). A PML4E is selected using the physical address defined as follows:
— Bits 51:12 are from CR3 or the HLATP (for 4-level paging) or in bits 51:12 of the PML5E (for 5-level 
paging).
— Bits 11:3 are bits 47:39 of the linear address.
Because a PML4E is identified using bits 47:39 of the linear address, it controls access to a 512-GByte region of 
With HLAT paging, if bit 11 of the PML4E is 1, translat ion is restarted with ordinary paging with a maximum 
page size of 512-GBytes (see Section 4.5.5). Otherwise,  the translation process continues as described in the 
next item.
•A 4-KByte naturally aligned page-directory-pointer tabl e is located at the physical address specified in 
bits 51:12 of the PML4E (see Table 4-15). A page-directory-pointer table comprises 512 64-bit entries 
(PDPTEs). A PDPTE is selected using the physical address defined as follows:
— Bits 51:12 are from the PML4E.
— Bits 11:3 are bits 38:30 of the linear address.
Because a PDPTE is identified using bits 47:30 of the linear  address, it controls access to a 1-GByte region of the 
linear-address space.
With HLAT paging, if bit 11 of the PDPTE is 1, translatio n is restarted with ordinary paging with a maximum page 
size of 1-GByte (see Section 4.5.5). Otherwise, the translation process continues as described below.
Use of the PDPTE depends on its PS flag (bit 7):1

next item.
•If the PDPTE’s PS flag is 1, the PDPTE maps a 1-GByt e page (see Table 4-16). The final physical address is 
computed as follows:
— Bits 51:30 are from the PDPTE.
— Bits 29:0 are from the original linear address.
The linear address’s protection key is the value of bits 62:59 of the PDPTE (see Section 4.6.2).
1. The PS flag of a PDPTE is rese rved and must be 0 (if the P flag is 1) if 1- GByte pages are not supported. See Section 4.1.4 f or how 
to determine whether 1-GByte pages are supported.Vol. 3A 4-25PAGING
•If the PDPTE’s PS flag is 0, a 4-KByte naturally alig ned page directory is located at the physical address 
specified in bits 51:12 of the PDPTE (see Table 4-17). A page directory comprises 512 64-bit entries (PDEs). A PDE is selected using the physical address defined as follows:
— Bits 51:12 are from the PDPTE.— Bits 11:3 are bits 29:21 of the linear address.
Because a PDE is identified using bits 47:21 of the linear address, it controls access to a 2-MByte region of the 
With HLAT paging, if bit 11 of the PDE is 1, translation is  restarted with ordinary paging with a maximum page size 
of 2-MBytes (see Section 4.5.5). Otherwise, the translation process continues as described below.
Use of the PDE depends on its PS flag:
•If the PDE's PS flag is 1, the PDE maps a 2-MByte page (see Table 4-18). The final physical address is computed 
The linear address’s protection key is the valu e of bits 62:59 of the PDE (see Section 4.6.2).
bits 51:12 of the PDE (see Table 4-19). A page table comprises 512 64-bit entries (PTEs). A PTE is selected 
— Bits 51:12 are from the PDE.
— Bits 11:3 are bits 20:12 of the linear address.— Bits 2:0 are all 0.
•Because a PTE is identified using bits 47:12 of the linear address, every PTE maps a 4-KByte page (see 
Table 4-20).
With HLAT paging, if bit 11 of the PTE is 1, translation is restarted with ordinary paging with a maximum page 
size of 4-KBytes (see Section 4.5.5). Otherwise, th e final physical address is computed as follows:
— Bits 51:12 are from the PTE.— Bits 11:0 are from the original linear address.
The linear address’s protection key is the valu e of bits 62:59 of the PTE (see Section 4.6.2).
ence another paging-structure entry nor to map a page. There is no translation for a linear address whose transla-
tion would use such a paging-structure entry; a reference to such a linear address causes a page-fault exception (see Section 4.7).
The following bits in a paging-structure entry are reserved  with 4-level paging and 5-level paging (assuming that 
the entry’s P flag is 1):
•Bits 51:MAXPHYADDR are reserved in every paging-structure entry.
•The PS flag is reserved in a PML5E or a PML4E.
•If 1-GByte pages are not supported, th e PS flag is reserved in a PDPTE.1
•If the PS flag in a PDPTE is 1, bits 29:13 of the entry are reserved.
•If the PS flag in a PDE is 1, bits 20:13 of the entry are reserved.
•If IA32_EFER.NXE = 0, the XD flag (bit 63) is reserved in every paging-structure entry.
A reference using a linear address that is successfully transl ated to a physical address is performed only if allowed 
1. See Section 4.1.4 for how to determin e whether 1-GByte pages are supported.4-26 Vol. 3APAGING
Figure 4-11 gives a summary of the formats of CR3 and th e 4-level and 5-level paging-structure entries. For the 
paging structures, and those that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted 
because they determine how a paging-structure entry is used.
Table 4-14.  Format of a PML5 Entry (PML5E) that References a PML4 Table
Bit 
0 (P) Present; must be 1 to reference a PML4 table
1 (R/W) Read/write; if 0, writes may not be allowed to the 256-TByte region controlled by this entry (see Section 4.6)
2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 256-TByte region controlled by this entry (see 
3 (PWT) Page-level write-through; indirectly determines the memo ry type used to access the PM L4 table referenced by this 
entry (see Section 4.9.2)
4 (PCD) Page-level cache di sable; indirectly determines the memory type us ed to access the PML4 ta ble referenced by this 
6I g n o r e d7 (PS) Reserved (must be 0)
10:8 Ignored
11 (R) For ordinary paging, ignored; for HLAT paging, restart (if 1, linear-address translation is restarted with ordinary 
paging)
M–1:12 Physical address of 4-KByte aligned PML4 table referenced by this entry51:M Reserved (must be 0)
62:52 Ignored
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, inst ruction fetches are not allowed from the 256-TByte region 
controlled by this entry; see Section 4.6); otherwise, reserved (must be 0)
Table 4-15.  Format of a PML4 Entry (PML4E) th at References a Page-D irectory-Pointer Table
Bit 
0 (P) Present; must be 1 to reference a page-directory-pointer table
1 (R/W) Read/write; if 0, writes may not be allowed to the 512-GByte region controlled by this entry (see Section 4.6)
2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 512-GByte region controlled by this entry (see 
3 (PWT) Page-level write-through; indirectly determines the me mory type used to access the page-directory-pointer table 
referenced by this entry (see Section 4.9.2)
4 (PCD) Page-level cache di sable; indirectly determines the memory type used to access the page-directory-pointer table 
6I g n o r e dVol. 3A 4-27PAGING
7 (PS) Reserved (must be 0)
11 (R) For ordinary paging, ignored; for HLAT paging, restart (if 1, linear-address translatio n is restarted with ordinary 
paging)
M–1:12 Physical address of 4-KByte aligned page-directory-pointer table referenced by this entry51:M Reserved (must be 0)
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instru ction fetches are not allowed from the 512-GByte region 
Table 4-16.  Format of a Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page
Bit 
0 (P) Present; must be 1 to map a 1-GByte page
1 (R/W) Read/write; if 0, writes may not be allowed to the 1-GByte page referenced by this entry (see Section 4.6)2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 1-GByte page referenced by this entry (see Section 
4.6)
3 (PWT) Page-level write-through; indirectly determines the memory  type used to access the 1-GByte page referenced by this 
4 (PCD) Page-level cache disable; indirectly determines the memory  type used to access the 1-GByte page referenced by this 
5 (A) Accessed; indicates whethe r software has accessed the 1-GByte page re ferenced by this en try (see Section 4.8)
6 (D) Dirty; indicates whether software has written to the 1-GByte page referenced by this entry (see Section 4.8)
7 (PS) Page size; must be 1 (otherwise, this entry references a page directory; see Table 4-17)8 (G) Global; if CR4.PGE = 1, determines whether the tran slation is global (see Section 4.10); ignored otherwise
10:9 Ignored
paging)
12 (PAT) Indirectly determines the memory type used to acce ss the 1-GByte page referenced by this entry (see Section 
4.9.2)
1
29:13 Reserved (must be 0)
(M–1):30 Physical address of the 1-GByte page refe renced by this entryTable 4-15.  Format of a PML4 Ent ry (PML4E) that References a Page -Directory-Pointer  Table (Contd.)
Bit 
Position(s)Contents4-28 Vol. 3APAGING
51:M Reserved (must be 0)
58:52 Ignored
62:59 Protection key; if CR4.PKE = 1 or CR4.PKS = 1, this may control the page’s access rights (see Section 4.6.2); otherwise, 
it is ignored and not used to control access rights.
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 1-GByte page controlled by 
NOTES:
1. The PAT is supported on all processors that support 4-level paging.

paging)
4.9.2)
1
Bit 
NOTES:
Table 4-17.  Format of a Page-Dir ectory-Pointer-Table Entry (PDPTE) that References a Page Directory
Bit 
1 (R/W) Read/write; if 0, writes may not be allowed to th e 1-GByte region controlled by this entry (see Section 4.6)
2 (U/S) User/supervisor; if 0, user-mode a ccesses are not allowed to the 1-GByte region controlled by this entry (see Section 
4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access the page directory referenced by 
this entry (see Section 4.9.2)
6I g n o r e d7 (PS) Page size; must be 0 (otherwise, this entry maps a 1-GByte page; see Table 4-16)
paging)
(M–1):12 Physical address of 4-KByte aligned page directory referenced by this entry51:M Reserved (must be 0)
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 1-GByte region controlled 
by this entry; see Section 4.6); otherwise, reserved (must be 0)Table 4-16.  Format of a Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page (Contd.)
Bit 
Position(s)ContentsVol. 3A 4-29PAGING
Table 4-18.  Format of a Page-Direc tory Entry that Maps a 2-MByte Page
Bit 
1 (R/W) Read/write; if 0, writes may not be allowed to th e 2-MByte page referenced by this entry (see Section 4.6)
4.6)
4 (PCD) Page-level cache di sable; indirectly determines the memory type used to access the 2-MByte page referenced by 
5 (A) Accessed; indicates whethe r software has accessed the 2-MByte page referenced by this entry (see Section 4.8)
7 (PS) Page size; must be 1 (otherwise, this entry references a page table; see Table 4-19)
10:9 Ignored11 (R) For ordinary paging, ignored; for HLAT paging, restart (if 1, linear-address translation is restarted with ordinary 
paging)
12 (PAT) Indirectly determines the memory type used to access the 2-MByte pa ge referenced by this  entry (see Section 
4.9.2)
20:13 Reserved (must be 0)
(M–1):21 Physical address of the 2-MByte page referenced by this entry
51:M Reserved (must be 0)58:52 Ignored
62:59 Protection key; if CR4.PKE = 1 or CR4.PKS = 1, this may control the page’s  access rights (see Section 4.6.2); 
otherwise, it is ignored and not used to control access rights.
63 (XD) If IA32_EFER.NXE = 1, execute-disa ble (if 1, instruction fetches are not allo wed from the 2-MByte page controlled by 
this entry; see Section 4.6); otherwise, reserved (must be 0)4-30 Vol. 3APAGING
Table 4-19.  Format of a Page-Directory  Entry that References a Page Table
Bit 
2 (U/S) User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte region controlled by this entry (see Section 
4.6)
6I g n o r e d7 (PS) Page size; must be 0 (otherwise, this  entry maps a 2-MByte page; see Table 4-18)
paging)
(M–1):12 Physical address of 4-KByte aligned page table referenced by this entry51:M Reserved (must be 0)
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 2-MByte region controlled 
by this entry; see Section 4.6); otherwise, reserved (must be 0)Vol. 3A 4-31PAGING
Table 4-20.  Format of a Page-Tab le Entry that Maps a 4-KByte Page
Bit 
4.6)
3 (PWT) Page-level write-through; indirectly determines the me mory type used to access the 4-KByte page referenced by 
7 (PAT) Indirectly determines the memory type used to access th e 4-KByte page referenced by this entry (see Section 4.9.2)
paging)
58:52 Ignored62:59 Protection key; if CR4.PKE = 1 or CR4.PKS = 1, this may control the page’s  access rights (see Section 4.6.2); 
63 (XD) If IA32_EFER.NXE = 1, execute-disabl e (if 1, instruction fetches are not allowed from the 4-KByte page controlled by 
this entry; see Section 4.6); otherwise, reserved (must be 0)4-32 Vol. 3APAGING
6
36
26
16
05
95
85
75
65
55
45
35
25
1M1
NOTES:
23
13
02
92
82
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
Reserved2
2. Reserved fiel ds must be 0.Address of PML4 table (4-level paging)
or PML5 table (5-level paging)IgnoredP
C
DP
W
TIgn. CR3
X
D
3
3. If IA32_EFER.NXE = 0 and the P flag of a paging-struc ture entry is 1, the XD fl ag (bit 63) is reserved.Ignored Rsvd. Address of PML4 tableR4
4. Bit 11 is R (restart) only for HLAT paging; it is ignored for ordinary paging.Ign.Rs
vdI
g
nAP
C
DP
W
TU
/SR
/
W1PML5E:
present
Ignored 0PML5E:
not
present
X
DIgnored Rsvd. Address of page-directory-pointer table R Ign.Rs
vdI
g
nAP
C
DP
W
TU
/SR
/
W1PML4E:
present
Ignored 0PML4E:
not
present
X
DProt.
Key5
5. The protection key is used only if so ftware has enabled the appropriate feature; see Section 4.6.2. It is ignored otherwise.Ignored Rsvd.Address of
1GB page frameReservedP
A
TRI g n .G 1DAP
C
DP
W
TU
/SR
/
W1PDPTE:
1GB
page
X
DIgnored Rsvd. Address of page directory R Ign. 0I
g
nAP
C
DP
W
TU
/SR
/
W1PDPTE:
page
directory
not
present
X
DProt.
KeyIgnored Rsvd.Address of
A
C
DP
W
TU
/SR
/
W1PDE:
2MB
page
X
DIgnored Rsvd. Address of page table R Ign. 0I
g
nAP
C
DP
W
TU
/SR
/
W1PDE:
page
table
not
present
X
DProt.
KeyIgnored Rsvd. Address of 4KB page frame R Ign. GP
A
TDAP
C
DP
W
TU
/SR
/
W1PTE:
4KB
page
not
present
Figure 4-11.  Formats of CR3 and Paging-Structure  Entries with 4-Level Paging and 5-Level PagingVol. 3A 4-33PAGING
4.5.5 Restart of HLAT Paging
As noted in Section 4.5.1, HLAT paging may specify that a translation of a linear address must be restarted. Specif-
ically, this occurs when HLAT paging encounters a pagi ng-structure entry that sets bit 11 (see Section 4.5.4).
When this occurs, translation of the linear address is restarted using ordinary paging (starting with a paging struc-
ture identified using CR3). The restarted translation procee ds just as if the HLAT feature were not enabled. The 
entire linear address is translated agai n, including those portions that had be en used by HLAT paging prior to the 
restart.
The process of restarting HLAT paging (using ordinary paging) always specifies a maximum page size to be used

not
present
X
DProt.
A
TDAP
C
DP
W
TU
/SR
/
W1PTE:
4KB
page
not
present
restart.
The process of restarting HLAT paging (using ordinary paging) always specifies a maximum page size to be used 
when a resulting translation is cached in the TLBs. This  maximum page size depends on the level of the paging-
structure entry that restarts the translation by setting bit 11; details are given in Section 4.5.4. The page size of 
the translation produced by the restarted process is ne ver greater than this maximum page size. See Section 
4.10.2.2 for more discussion.
4.6 ACCESS RIGHTS
There is a translation for a linear address if the processes described in Section 4.3, Section 4.4.2, and Section 4.5 
(depending upon the paging mode) completes and produces a physical address. Whether an access is permitted by 
a translation is determined by the access rights specifie d by the paging-structure entries controlling the transla-
tion;1 paging-mode modifiers in CR0, CR4, and the IA32_EFER MSR; EFLAGS.AC; and the mode of the access.
Section 4.6.1 describes how the processor determines th e access rights for each linear address. Section 4.6.2 
provides additional information about how protection keys contribute to access-rights determination. (They do so 
only with 4-level paging and 5-level paging , and only if CR4.PKE = 1 or CR4.PKS = 1.) 
NOTE
If HLAT paging is restarted, permissions are dete rmined only by the access rights specified by the 
paging-structure entries that the subsequent ordinary paging used to translate the linear address. 
The access rights specified by the entries used earlier by HLAT paging do not apply.
4.6.1 Determination of Access Rights
Every access to a linear address is either a supervisor-mode access  or a user-mode access . For all instruction 
fetches and most data accesses, this distinction is dete rmined by the current privilege level (CPL): accesses made 
while CPL < 3 are supervisor-mode accesses, while accesses made while CPL = 3 are user-mode accesses.
Some operations implicitly access system data structures with linear addresses; the resulting accesses to those 
data structures are supervisor-mode accesses regardless of  CPL. Examples of such accesses include the following: 
accesses to the global descriptor table (GDT) or local descr iptor table (LDT) to load a segment descriptor; accesses 
to the interrupt descriptor table (IDT) when delivering an interrupt or exception; and accesses to the task-state 
segment (TSS) as part of a task switch or change of CPL. All these accesses are called implicit supervisor-mode 
accesses  regardless of CPL. Other accesses made while CPL < 3 are called explicit supervisor-mode accesses .
Access rights are also controlled by the mode  of a linear address as specified by the paging-structure entries 
controlling the translation of the linear address. If the U/S fl ag (bit 2) is 0 in at least one of the paging-structure 
entries, the address is a supervisor-mode address . Otherwise, the address is a user-mode address .
When the shadow-stack feature of control-flow enforcem ent technology (CET) is enabled, certain accesses to 
linear addresses are considered shadow-stack accesses  (see Section 17.2, “Shadow Stacks,” in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 1). Like ordinary data accesses, each shadow-stack 
access is defined as being either a user access or a supervisor access. In general, a shadow-stack access is a user access if CPL = 3 and a supervisor access if CPL < 3. The WRUSS instruction is an exception; although it can be 
executed only if CPL = 0, the processor treats  its shadow-stack accesses as user accesses. 
1. With PAE paging, the PDPTEs do not determine access rights.4-34 Vol. 3APAGING
Shadow-stack accesses are allowed only to shadow-stack addresses . A linear address is a shadow-stack 
address if the following are true of the translation of the linear address: (1) the R/W flag (bit 1) is 0 and the dirty 
flag (bit 6) is 1 in the paging-structure entry that maps the page containing the linear address; and (2) the R/W 
flag is 1 in every other paging-structure entr y controlling the translation of the linear address.
The following items detail how paging determines access ri ghts (only the items noted explicitly apply to shadow-
stack accesses):
NOTE
Many of the items below refer to an address with a protection key for which read (or write) access is permitted. Section 4.6.2 provides details on when a protection key will permit (or not permit) a 
data access (read or write) to a linear address using that protection key.
•For supervisor-mode accesses:
— Data may be read (implicitly or explicitly) from any supervisor-mode address with a protection key for 
which read access is permitted.
— Data reads from user-mode pages.
Access rights depend on the value of CR4.SMAP:
•If CR4.SMAP = 0, data may be read from any user-m ode address with a protection key for which read 
access is permitted.
•If CR4.SMAP = 1, access rights depend on the value of EFLAGS.AC and whether the access is implicit or 
explicit:
— If EFLAGS.AC = 1 and the access is explicit, data may be read from any us er-mode address with a 
protection key for which read access is permitted.
— If EFLAGS.AC = 0 or the access is implicit, data  may not be read from any user-mode address.
— Data writes to supervisor-mode addresses.
Access rights depend on the value of CR0.WP:
•If CR0.WP = 0, data may be written to any superv isor-mode address with a protection key for which 
write access is permitted.
•If CR0.WP = 1, data may be written to any superv isor-mode address with a translation for which the 
R/W flag (bit 1) is 1 in every paging-structure entry controlling the translation and with a protection key 
for which write access is permitted; data may not be written to any supervisor-mode address with a 
translation for which the R/W flag is 0 in any paging-structure entry controlling the translation.
— Data writes to user-mode addresses.
•If CR0.WP = 0, access rights depend on the value of CR4.SMAP:
— If CR4.SMAP = 0, data may be written to any us er-mode address with a protection key for which 
— If CR4.SMAP = 1, access rights depend on the value of EFLAGS.AC and whether the access is 
implicit or explicit:
• If EFLAGS.AC = 1 and the access is explicit, data may be written to any user-mode address 
with a protection key for which write access is permitted.
• If EFLAGS.AC = 0 or the access is implicit, data  may not be written to any user-mode address.
•If CR0.WP = 1, access rights depend on the value of CR4.SMAP:
— If CR4.SMAP = 0, data may be written to any us er-mode address with a translation for which the 
R/W flag is 1 in every paging-structure entry co ntrolling the translation and with a protection key 
for which write access is permitted; data may no t be written to any us er-mode address with a 
translation for which the R/W flag is 0 in any pa ging-structure entry controlling the translation.
implicit or explicit:Vol. 3A 4-35PAGING
with a translation for which the R/W flag is 1 in every paging-structure entry controlling the translation and with a protection key for which write access is permitted; data may not be 
written to any user-mode address with a translation for which the R/W flag is 0 in any paging-
structure entry controlling the translation.
• If EFLAGS.AC = 0 or the access is implicit, data may not be written to any user-mode address.
— Instruction fetches from supervisor-mode addresses.
•For 32-bit paging or if IA32_EFER.NXE = 0, instru ctions may be fetched fr om any supervisor-mode 
address.
•For other paging modes with IA32_EFER.NXE = 1, in structions may be fetched from any supervisor-
mode address with a translation for which the XD flag (bit 63) is 0 in every paging-structure entry 
controlling the translation; instructions may not be fetched from any supervisor-mode address with a 
translation for which the XD flag is 1 in any pa ging-structure entry controlling the translation.
— Instruction fetches from user-mode addresses.
Access rights depend on the values of CR4.SMEP:
•If CR4.SMEP = 0, access rights depend on the paging mode and the value of IA32_EFER.NXE:
— For 32-bit paging or if IA32_EFER.NXE = 0, instructions may be fetched from any user-mode 
address.
— For other paging modes with IA32_EFER.NXE = 1,  instructions may be fetched from any user-
mode address with a translation for which the XD  flag is 0 in every paging-structure entry 
controlling the translation; instructions may not be fetched from any user-mode address with a 
•If CR4.SMEP = 1, instructions may not be fetched from any user-mode address.
— Supervisor-mode shadow-stack accesses are allowed only to supervisor-mode shadow-stack addresses 
(see above).
•For user-mode accesses:
— Data reads.

address.
Access rights depend on the mode of the linear address:
•Data may be read from any user-mode address with a protection key for which read access is 
permitted.
•Data may not be read from any supervisor-mode address.
— Data writes.
•Data may be written to any user-mode address with a translation for which the R/W flag is 1 in every 
paging-structure entry controlling the translation and with a protection key for which write access is permitted.
•Data may not be written to any supervisor-mode address.
— Instruction fetches.
Access rights depend on the mode of the linea r address, the paging mode, and the value of 
IA32_EFER.NXE:
•For 32-bit paging or if IA32_EFER.NXE = 0, instruct ions may be fetched from  any user-mode address.
•For other paging modes with IA32_EFER.NXE = 1, instructions may be fetched from any user-mode 
address with a translation for which the XD flag is  0 in every paging-structure entry controlling the 
•Instructions may not be fetched from any supervisor-mode address.
— User-mode shadow-stack accesses made outside encl ave mode are allowed only to user-mode shadow-
stack addresses (see above). User-mode shadow-stack accesses made in enclave mode are treated like 
ordinary data accesses (see above).4-36 Vol. 3APAGING
A processor may cache information from the paging-structu re entries in TLBs and paging-structure caches (see 
Section 4.10). These structures may include informatio n about access rights. The processor may enforce access 
rights based on the TLBs and paging-structure caches instead of on the paging structures in memory.
This fact implies that, if software modifies a paging-structure entry to change access rights, the processor might 
not use that change for a subsequent access to an affe cted linear address (see Section 4.10.4.3). See Section 
4.10.4.2 for how software can ensure that the processor uses the modified access rights.
4.6.2 Protection Keys
4-level paging and 5-level paging associate a 4-bit protec tion key with each linear address (the protection key 
located in bits 62:59 of the paging-structure entry that mapped the page containing the linear address; see Section 
4.5). Two protection key features control accesses to linear addresses based on their protection keys:
•If CR4.PKE = 1, the PKRU register determines, for each protection key, whether user-mode addresses with that 
protection key may be read or written.
•If CR4.PKS = 1, the IA32_PKRS MSR (MSR index 6E1H ) determines, for each protection key, whether 
supervisor-mode addresses with that pr otection key may be read or written.
32-bit paging and PAE paging do not associate linear addre sses with protection keys. For the purposes of Section 
4.6.1, reads and writes are implicitly permitted for a ll protection keys with either of those paging modes.
The PKRU register (protection-key rights for user pages) is a 32-bit register with the following format: for each i 
(0≤ i ≤ 15), PKRU[2 i] is the access-disable bit  for protection key i (ADi); PKRU[2 i+1] is the write-disable bit  
for protection key i (WDi). The IA32_PKRS MSR has the same format (b its 63:32 of the MSR are reserved and must 
be zero).
Software can use the RDPKRU and WRPKRU instructions wi th ECX = 0 to read and write PKRU. In addition, the 
PKRU register is XSAVE-managed state and can thus be read  and written by instructions in the XSAVE feature set. 
See Chapter 13, “Managing State Usin g the XSAVE Feature Set,” of Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1, for more information about the XSAVE feature set.
Software can use the RDMSR and WRMSR instructions to  read and write the IA32_PKRS MSR. Writes to the 
IA32_PKRS MSR using WRMSR are not serializin g. The IA32_PKRS MSR is not XSAVE-managed.
How a linear address’s protection key controls access to the address depends on the mode of the linear address:
•A linear address’s protection key controls only data accesses to the address. It does not in any way affect 
instructions fetches from the address.
•If CR4.PKE = 0, the protection key of a user-mode addr ess does not control data accesses to the address (for 
the purposes of Section 4.6.1, reads and writes of user-mode addresses are implicitly permitted for all 
protection keys).
If CR4.PKE = 1, use of the protection key i of a user-mode address depends on  the value of the PKRU register:
—I f  A D i= 1, no data accesses are permitted.
—I f  W D i= 1, permission may be denied to certain data write accesses:
•User-mode write accesses are not permitted.
•Supervisor-mode write accesses are not perm itted if CR0.WP = 1. (If CR0.WP = 0, WD i does not affect 
supervisor-mode write accesses to user-mode addresses with protection key i.)
•If CR4.PKS = 0, the protection key of a supervisor-mod e address does not control data accesses to the address 
(for the purposes of Section 4.6.1, reads and writes of  supervisor-mode addresses are implicitly permitted for 
all protection keys).
If CR4.PKS = 1, use of the protection key i of a supervisor-mode address depends on the value of the 
IA32_PKRS MSR:
—I f  W D i= 1, write accesses are not permitted if CR0.WP = 1. (If CR0.WP = 0, IA32_PKRS.WD i does not 
affect write accesses to supervisor-mode addresses with protection key i.)
Protection keys apply to shadow-stack accesses just as they do to ordinary data accesses.Vol. 3A 4-37PAGING
4.7 PAGE-FAULT EXCEPTIONS
Accesses using linear addresses may cause page-fault exceptions  (#PF; exception 14). An access to a linear 
address may cause a page-fault exception for either of two reasons: (1) there is no translation for the linear 
address; or (2) there is a translation for the linear address, but its access rights do not permit the access.
As noted in Section 4.3, Section 4.4.2, and Section 4.5, ther e is no translation for a linear address if the translation 
process for that address would use a paging-structure entr y in which the P flag (bit 0) is 0 or one that sets a 
reserved bit.1 If there is a translation for a linear address, its access rights are determined as specified in Section 
4.6.
When Intel® Software Guard Extensions (Intel® SGX) are enabled, the processor may deliver exception 14 for 
reasons unrelated to paging. See Section 35.3, “Access-co ntrol Requirements,” and Section 35.20, “Enclave Page 
Cache Map (EPCM),” in Chapter 35, “Enclave Access Control and Data Structures.” Such an exception is called an 
SGX-induced page  fault. The processor uses the error code to distinguish SGX-induced page faults from ordinary 
page faults.
Figure 4-12 illustrates the error code that the processor provides on delivery of a page-fault exception. The 
following items explain how the bits in the error co de describe the nature of the page-fault exception:
•P flag (bit 0).
This flag is 0 if there is no translation for the linea r address because the P flag was 0 in one of the paging-
structure entries used to translate that address.
1. If HLAT paging encounters a paging-structu re entry that sets a reserved bit, there is no translatio n even if the bit 11 of the  entry 
indicates a restart. In this ca se, there is a page fault and th e translation is not restarted.Figure 4-12.  Page-Fault Error CodeThe fault was caused by a non-present page.
The fault was caused by a page-level protection violation.
The access causing the fault was a read.
The access causing the fault was a write.
A supervisor-mode access caused the fault.
A user-mode access caused the fault.31 0
Reserved1234
The fault was not caused by  reserved bit violation.
The fault was caused by a reserved bit set to 1 in someP 0
1
W/R 0
1
U/S 0
RSVD 0
11I/D
I/D 0 The fault was not caused by an instruction fetch.
1The fault was caused by an instruction fetch.P
W/RU/SRSVD
paging-structure entry.PK5
PK 0 The fault was not caused by protection keys.
1There was a protection-key violation.
HLAT The fault occurred during ordinary paging or due to access rights.0
1The fault occurred during HLAT paging.Reserved
SGX15SS6
SS 0 The fault was not caused by a shadow-stack access.
1The fault was caused by a shadow-stack access.7HLAT
SGX The fault is not related to SGX.0
1The fault resulted from violati on of SGX-specific access-control
requirements.4-38 Vol. 3APAGING
•W/R (bit 1).
If the access causing the page-fault exception was a write, th is flag is 1; otherwise, it is 0. This flag describes 
the access causing the page-fault exception, not the access rights specified by paging.
•U/S (bit 2).
If a user-mode access caused the page-fault exception, this  flag is 1; it is 0 if a supervisor-mode access did so. 
This flag describes the access causing the page-fault exce ption, not the access rights specified by paging. User-
mode and supervisor-mode accesses are defined in Section 4.6.
•RSVD flag (bit 3).

SGX15SS6
This flag is 1 if there is no translation for the linear ad dress because a reserved bit was set in one of the paging-
structure entries used to translate that address. (Becau se reserved bits are not checked in a paging-structure 
entry whose P flag is 0, bit 3 of the error code can be set only if bit 0 is also set.1)
Bits reserved in the paging-structure entries are reserved  for future functionality. Software developers should 
be aware that such bits may be used in the future and that a paging-structure entry that causes a page-fault 
exception on one processor might not do so in the future.
•I/D flag (bit 4).This flag is 1 if (1) the access causing the page-fault exception was an instruction fetch; and (2) either 
(a) CR4.SMEP = 1; or (b) both (i) CR4.PAE = 1 (either PAE paging, 4-level paging, or 5-level paging is in use); 
and (ii) IA32_EFER.NXE = 1. Otherwise, the flag is 0. This flag describes the access causing the page-fault 
exception, not the access rights specified by paging.
•PK flag (bit 5).
This flag is 1 only for data accesses and only with 4-level paging and 5-level paging. In these cases, the setting depends on the mode of the address being accessed:
— For accesses to supervisor-mode addresses, the flag is set if (1) CR4.PKS = 1; (2) the linear address has 
protection key i; and (3) the IA32_PKRS MSR (see Section 4.6.2) is such that either (a) AD i= 1; or (b) the 
following all hold: (i) WD i= 1; (ii) the access is a write access; and (iii) either CR0.WP = 1 or the access 
causing the page-fault exception was a user-mode access.  (Note that this flag may be set on page faults 
due to user-mode accesses to supervisor-mode addresses.)
— For accesses to user-mode addresses, the flag is set if (1) CR4.PKE = 1; (2) the linear address has 
protection key i; and (3) the PKRU register (see Section 4.6.2) is such that either (a) AD i= 1; or (b) the 
causing the page-fault exception was a user-mode access.
•SS (bit 6).If the access causing the page-fault exception was a sh adow-stack access (including shadow-stack accesses in 
enclave mode), this flag is 1; otherwise, it is 0. This  flag describes the access causing the page-fault exception, 
not the access rights specified by paging.
•HLAT (bit 7).This flag is 1 if there is no translation for the linear address using HLAT paging because, in one of the paging-
structure entries used to translate that address, either th e P flag was 0 or a reserved bit was set. An error code 
will set this flag only if it clears bit 0 or sets bit 3. This flag will not be set by a page fault resulting from a violation of access rights, nor for one encountered during ordinary paging, including the case in which there has 
been a restart of HLAT paging.
•SGX flag (bit 15).
This flag is 1 if the exception is unrelated to paging an d resulted from violation of SGX-specific access-control 
requirements. Because such a violation can occur only if ther e is no ordinary page fault, this flag is set only if 
the P flag (bit 0) is 1 and the RSVD flag (bit 3) and the PK flag (bit 5) are both 0.
Page-fault exceptions occur only due to an attempt to us e a linear address. Failures to load the PDPTE registers 
with PAE paging (see Section 4.4.1) cause general-protec tion exceptions (#GP(0)) and not page-fault exceptions.
1. Some past processors had errata for some page faults that occur when there is no translation for the linear address because t he P 
flag was 0 in one of the paging-structure en tries used to translate that address. Due to these errata, some such page faults pr o-
duced error codes that cleared bit 0 (P flag) and set bit 3 (RSVD flag).Vol. 3A 4-39PAGING
4.8 ACCESSED AND DIRTY FLAGS
For any paging-structure entry that is used during linear-address translation, bit 5 is the accessed  flag.1 For 
paging-structure entries that map a page (as opposed to  referencing another paging structure), bit 6 is the dirty 
flag. These flags are provided for use by memory-manag ement software to manage the transfer of pages and 
paging structures into and out of physical memory.
Whenever the processor uses a paging-structure entry as part of linear-address translation, it sets the accessed 
flag in that entry (if it is not already set).
Whenever there is a write to a linear address, the processor se ts the dirty flag (if it is not already set) in the paging-
structure entry that identifies the final physical address for the linear address (either a PTE or a paging-structure 
entry in which the PS flag is 1).
The previous two paragraphs apply also to HLAT paging. If HLAT paging encounters a paging-structure entry that 
sets bit 11, indicating a restart, the processor will set the a ccessed flag in that entry; it will not set the dirty flag 
because, if an entry indicates a restart, it does identify the final physical address for the linear address being trans-
lated.
NOTE
If software on one logical processor writes to a page while software on another logical processor 
concurrently clears the R/W flag in the paging-structure entry that maps the page, execution on 
some processors may result in the entry’s dirty flag being set (due to the write on the first logical processor) and the entry’s R/W flag being clear (d ue to the update to the entry on the second 
logical processor). This will never occur on a processor that supports control-flow enforcement 
technology (CET). Specifically, a processor that supports CET will never set the dirty flag in a 
paging-structure entry in which the R/W flag is clear.
Memory-management software may clear these flags when a page or a paging structure is initially loaded into 
physical memory. These flags are “sticky,” meaning that, on ce set, the processor does not clear them; only soft-
ware can clear them.
Section 4.10). This fact implies that, if software changes an  accessed flag or a dirty flag from 1 to 0, the processor 
might not set the corresponding bit in memory on a su bsequent access using an affected linear address (see 
Section 4.10.4.3). See Section 4.10.4.2 for how software  can ensure that these bits are updated as desired.
NOTE
The accesses used by the processor to set these flags may or may not be exposed to the 
processor’s self-modifying code detection logic. If  the processor is executing code from the same 
memory area that is being used for the paging st ructures, the setting of these flags may or may not 
result in an immediate change to the executing code stream.
4.9 PAGING AND MEMORY TYPING
The memory type  of a memory access refers to the type of caching used for that access. Chapter 12, “Memory 
Cache Control‚” provides many details regarding memory typing in the Intel-64 and IA-32 architectures. This 
section describes how paging contributes to the determination of memory typing.
The way in which paging contributes to memory typing depends on whether the processor supports the Page 
Attribute Table  (PAT; see Section 12.12).2 Section 4.9.1 and Section 4.9.2 explain how paging contributes to 
memory typing depending on whether the PAT is supported.
1. With PAE paging, the PDPTEs are not used during linear-address translation but only to load the PDPTE registers for some exec u-
tions of the MOV CR instruction (see Section 4.4.1). For this re ason, the PDPTEs do not contain accessed flags wi th PAE paging.  
2. The PAT is supported on Pentium III and mo re recent processor families . See Section 4.1.4 for how to  determine whether the PAT  is 
supported.4-40 Vol. 3APAGING
4.9.1 Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium 
II Processors)
NOTE
The PAT is supported on all processors that supp ort 4-level paging or 5-level paging. Thus, this 
section applies only to 32-bit paging and PAE paging.
If the PAT is not supported, paging contributes to memory  typing in conjunction with the memory-type range regis-
ters (MTRRs) as specified in Table 12-6 in Section 12.5.2.1.
For any access to a physical address, the table combines th e memory type specified for that physical address by the 
MTRRs with a PCD value and a PWT value. The la tter two values are determined as follows:
•For an access to a PDE with 32-bit paging, the PCD and PWT values come from CR3.
•For an access to a PDE with PAE paging, the PCD and PWT values come from the relevant PDPTE register.
•For an access to a PTE, the PCD and PW T values come from the relevant PDE.
•For an access to the physical address that is the transl ation of a linear address, the PCD and PWT values come 
from the relevant PTE (if the translation uses a 4-KByte page) or the relevant PDE (otherwise).
•With PAE paging, the UC memory type is used when loading the PDPTEs (see Section 4.4.1).
4.9.2 Paging and Memory Typing When the PAT is Supported (P entium III and More Recent

4.9.2 Paging and Memory Typing When the PAT is Supported (P entium III and More Recent 
Processor Families)
If the PAT is supported, paging contributes to memory typing in conjunction with the PAT and the memory-type 
range registers (MTRRs) as specified in Table 12-7 in Section 12.5.2.2.
The PAT is a 64-bit MSR (IA32_PAT; MSR index 277H) comprising eight (8) 8-bit entries (entry i comprises 
bits 8 i+7:8i of the MSR).
MTRRs with a memory type selected from the PAT. Table 12-11 in Section 12.12.3 specifies how a memory type is 
selected from the PAT. Specifically, it comes from entry i of the PAT, where i is defined as follows:
•For an access to an entry in a paging structure whose address is in CR3 (e.g., the PML4 table with 4-level 
paging):
— For 4-level paging or 5-level paging with CR4.PCIDE = 1, i= 0.
—O t h e r w i s e ,  i= 2*PCD+PWT, where the PCD and PWT values come from CR3. 
•For an access to a PDE with PAE paging, i= 2*PCD+PWT, where the PCD an d PWT values come from the 
relevant PDPTE register.
•For an access to a paging-structure entry X whose address is in another paging-structure entry Y, i= 
2*PCD+PWT, where the PCD an d PWT values come from Y.
•For an access to the physical address that is the translation of a linear address, i= 4*PAT+2*PCD+PWT, where 
the PAT, PCD, and PWT values come from the relevant PT E (if the translation uses a 4-KByte page), the relevant 
PDE (if the translation uses a 2-MByte page or a 4-MByte page), or the relevant PDPTE (if the translation uses 
a 1-GByte page).
•With PAE paging, the WB memory type is used  when loading the PDPTEs (see Section 4.4.1).1
1. Some older IA-32 processors used the UC memory type when loading the PDPTEs. Some processors may use the UC memory type if 
CR0.CD = 1 or if the MTRRs are disabled. These behaviors are model-specific and not architectural.Vol. 3A 4-41PAGING
4.9.3 Caching Paging-Related Information about Memory Typing
Section 4.10 ). These structures may include information abou t memory typing. The processor may use memory-
typing information from the TLBs and paging-structure caches instead of from the paging structures in memory.
This fact implies that, if software modifies a paging -structure entry to change the memory-typing bits, the 
processor might not use that change for a subsequent translation using that entry or for access to an affected linear address. See Section 4.10.4.2 for how software ca n ensure that the processor uses the modified memory 
typing.
4.10 CACHING TRANSLATION INFORMATION
The Intel-64 and IA-32 architectures may accelerate the address-translation process by caching data from the 
paging structures on the processor. Because the processor does not ensure that the data that it caches are always 
consistent with the structures in memory, it is importan t for software developers to understand how and when the 
processor may cache such data. They should also understand what actions software can take to remove cached 
data that may be inconsistent and when it should do so . This section provides software developers information 
about the relevant processor operation.
Section 4.10.1 introduces process-context identifiers (P CIDs), which a logical processor may use to distinguish 
information cached for different linear-address spaces. Section 4.10.2 and Section 4.10.3 describe how the 
processor may cache information in translation lookaside bu ffers (TLBs) and paging-structure caches, respectively. 
Section 4.10.4 explains how software can remove inconsistent cached information by invalidating portions of the TLBs and paging-structure caches. Section 4.10.5 descr ibes special considerations for multiprocessor systems.
4.10.1 Process-Context Identifiers (PCIDs)
Process-context identifiers ( PCIDs ) are a facility by which a logical processor may cache information for multiple 
linear-address spaces. The processor may retain cached info rmation when software switches to a different linear-
address space with a different PCID (e.g., by loading CR3; see Section 4.10.4.1 for details).
A PCID is a 12-bit identifier. Non-zero PCIDs are enabled by  setting the PCIDE flag (bit 17) of CR4. If CR4.PCIDE = 
0, the current PCID is always 000H; otherwise, the current PCID is the value of bits 11:0 of CR3.1 Not all proces-
sors allow CR4.PCIDE to be set to 1; see Section 4.1.4 for how to determine whether this is allowed.
The processor ensures that CR4.PCIDE can be 1 only in IA -32e mode (thus, 32-bit paging and PAE paging use only 
PCID 000H). In addition, software can change CR4.PCID E from 0 to 1 only if CR 3[11:0] = 000H. These require-
ments are enforced by the following limitations on the MOV CR instruction:
•MOV to CR4 causes a general-protection exception (#GP) if it would change CR4.PCIDE from 0 to 1 and either 
IA32_EFER.LMA = 0 or CR3[11:0] ≠ 000H.
•MOV to CR0 causes a general-protection exception if it would clear CR0.PG to 0 while CR4.PCIDE = 1.
When a logical processor creates entries in the TLBs (S ection 4.10.2) and paging-structure caches (Section 
4.10.3), it associates those entries with the current PCID . When using entries in the TLBs and paging-structure 
caches to translate a linear address, a logical processor us es only those entries associated with the current PCID 
(see Section 4.10.2.4 for an exception).
If CR4.PCIDE = 0, a logical processor does not cache info rmation for any PCID other than 000H. This is because 
(1) if CR4.PCIDE = 0, the logical processor will associat e any newly cached information with the current PCID, 
000H; and (2) if MOV to CR4 clears CR4.PCIDE, all cach ed information is invalidat ed (see Section 4.10.4.1).
1. Note that, while HLAT paging (Section 4.5. 3) does not use CR3 to locate  the first paging structure, it does use the PCID in C R3[11:0] 
when CR4.PCIDE = 1.4-42 Vol. 3APAGING
NOTE
In revisions of this manual that were produced wh en no processors allowed CR4.PCIDE to be set to 
1, Section 4.10, “Caching Translation Information, ” discussed the caching of translation information 
without any reference to PCIDs. While the section no w refers to PCIDs in its specification of this 
caching, this documentation change is not inte nded to imply any change to the behavior of 
processors that do not allow CR4.PCIDE to be set to 1.
4.10.2 Translation Lookaside Buffers (TLBs)
A processor may cache information about the translation of linear addresses in translation lookaside buffers (TLBs). 
In general, TLBs contain entries that map page number s to page frames; these terms are defined in Section 
4.10.2.1. Section 4.10.2.2 describes how information may be  cached in TLBs, and Section 4.10.2.3 gives details of 
TLB usage. Section 4.10.2.4 explains the global-page feature,  which allows software to indicate that certain trans-
lations should receive special trea tment when cached in the TLBs.
4.10.2.1  Page Numbers, Page Frames, and Page Offsets
Section 4.3, Section 4.4.2, and Section 4.5 give deta ils of how the different paging modes translate linear 
addresses to physical addresses. Specifically, the upper bits of a linear address (called the page number ) deter-
mine the upper bits of the physical address (called the page frame ); the lower bits of the linear address (called the 
page offset ) determine the lower bits of the physical addr ess. The boundary between the page number and the 
page offset is determined by the page size . Specifically:
•32-bit paging:
— If the translation does not use a PTE (because CR4.PSE = 1 and the PS flag is 1 in the PDE used), the page 
size is 4 MBytes and the page number comprises bits 31:22 of the linear address.
— If the translation does use a PTE, the page size is 4 KBytes and the page number comprises bits 31:12 of 
the linear address.
•PAE paging:
— If the translation does not use a PTE (because the PS flag is 1 in the PDE used), the page size is 2 MBytes 
and the page number comprises bits 31:21 of the linear address.
•4-level paging and 5-level paging:
— If the translation does not use a PDE (because the PS flag is 1 in the PDPTE used), the page size is 1 GByte 
and the page number comprises bits 47:30 of the linear address.
— If the translation does use a PDE but does not uses a PTE (because the PS flag is 1 in the PDE used), the 
page size is 2 MBytes and the page number comprises bits 47:21 of the linear address.
— If the translation does use a PTE, the page size is 4 KBytes and the page number comprises bits 47:12 of 
— The page size identified by the preceding items may be  reduced if there has been a restart of HLAT paging 
(see Section 4.5.5). Restart of HLAT paging always specifies a maximum page size; this page size is 
determined by the level of the paging-structure entry that caused the restart. The page size used by the

determined by the level of the paging-structure entry that caused the restart. The page size used by the 
translation is the minimum of the maximum page size sp ecified by the restart and the page size determined 
by the restarted translation (as specified by the previous items).
For example, suppose that HLAT paging encounters a PDE that sets bit 11, indicating a restart. As a result, 
the restart uses a maximum page size of 2 MBytes. Suppose that the restarted translation encounters a PDPTE that sets bit 7, indicating a 1-GByte page. In this  case, the translation produced will have a page size 
of 2 MBytes (the smaller of the two sizes).Vol. 3A 4-43PAGING
4.10.2.2  Caching Translations in TLBs
The processor may accelerate the paging process by caching individual translations in translation lookaside 
buffers  (TLBs ). Each entry in a TLB is an individual translation.  Each translation is referenced by a page number. 
It contains the following information from the paging-structure entries used to translate linear addresses with the 
page number:
•The physical address corresponding to the page number (the page frame).
•The access rights from the paging-structure entries used  to translate linear addresses with the page number 
(see Section 4.6):
— The logical-AND of the R/W flags.
— The logical-AND of the U/S flags.
— The logical-OR of the XD flags (n ecessary only if IA32_EFER.NXE = 1).
— The protection key (only with 4-level paging and 5-level paging).
•Attributes from a paging-structure entry that identifies the final page frame for the page number (either a PTE 
or a paging-structure entry in which the PS flag is 1):
— The dirty flag (see Section 4.8).— The memory type (see Section 4.9).
(TLB entries may contain other information as well. A pr ocessor may implement multiple TLBs, and some of these 
may be for special purposes, e.g., only for instruction fetc hes. Such special-purpose TLBs may not contain some of 
this information if it is not necessary. For example, a TLB used only for instruction fetches need not contain infor-mation about the R/W and dirty flags.)
As noted in Section 4.10.1, any TLB entries created by a logical processor are associated with the current PCID.
Processors need not implement any TLBs. Processors that do implement TLBs may invalidate any TLB entry at any 
time. Software should not rely on the existenc e of TLBs or on the retention of TLB entries.
4.10.2.3  Details of TLB Use
Because the TLBs cache entries only for linear addresses with translations, there can be a TLB entry for a page 
number only if the P flag is 1 and the reserved bits are 0 in each of the paging-structure entries used to translate 
that page number. In addition, the processor does not cache a translation for a page number unless the accessed flag is 1 in each of the paging-structure entries used duri ng translation; before caching a translation, the processor 
sets any of these accessed flags that is not already 1.
Subject to the limitations given in the previous paragraph, the processor may cache a translation for any linear 
address, even if that address is not used to access me mory. For example, the processor may cache translations 
required for prefetches and for accesses that result from speculative execution that would never actually occur in the executed code path.
If the page number of a linear address corresponds to a TLB entry associated with the current PCID, the processor 
may use that TLB entry to determine the page frame, access rights, and other attributes for accesses to that linear 
address. In this case, the processor may not actually co nsult the paging structures in memory. The processor may 
retain a TLB entry unmodified even if software subsequently modifies the relevant paging-structure entries in memory. See Section 4.10.4.2 for how software can ensure that the processor uses the modified paging-structure 
entries.
If the paging structures specify a translation using a page larger than 4 KBytes, some processors may cache 
multiple smaller-page TLB entries for that translation. Each such TLB entry would be associated with a page 
number corresponding to the smaller page size (e.g., bi ts 47:12 of a linear address with 4-level paging), even 
though part of that page number (e.g., bits 20:12) is part  of the offset with respect to the page specified by the 
paging structures. The upper bits of the physical address in such a TLB entry are derived from the physical address 
in the PDE used to create the translation, while the lowe r bits come from the linear address of the access for which 
the translation is created. There is no way for software to be aware that multiple translations for smaller pages 
have been used for a large page. For example, an executio n of INVLPG for a linear address on such a page invali-
dates any and all smaller-page TLB entries for the translation of any linear address on that page.4-44 Vol. 3APAGING
If software modifies the paging structures so that the page size used for a 4-KByte range of linear addresses 
changes, the TLBs may subsequently contain multiple transl ations for the address range (one for each page size). 
A reference to a linear address in the address range may use any of these translations. Which translation is used 
may vary from one execution to another, an d the choice may be im plementation-specific.
4.10.2.4  Global Pages
The Intel-64 and IA-32 architectures also allow for global pages  when the PGE flag (bit 7) is 1 in CR4. If the G flag 
(bit 8) is 1 in a paging-structure entry that maps a page  (either a PTE or a paging-structure entry in which the PS 
flag is 1), any TLB entry cached for a linear address us ing that paging-structure entry is considered to be global . 
Because the G flag is used only in paging-structure en tries that map a page, and because information from such 
entries is not cached in the paging-structure caches, the global-page feature does not affect the behavior of the 
paging-structure caches.
A logical processor may use a global TLB entry to translate a linear address, even if the TLB entry is associated with 
a PCID different from the current PCID.
4.10.3 Paging-Structure Caches
In addition to the TLBs, a processor may cache other information about the paging structures in memory.
4.10.3.1  Caches for Paging Structures
A processor may support any or all of the following paging-structure caches:
•PML5E cache  (5-level paging only). Each PML5E-cache entry is referenced by a 9-bit value and is used for 
linear addresses for which bits 56:48 have that value. Th e entry contains information from the PML5E used to 
translate such linear addresses:
— The physical address from the PML5E (the address of the PML4 table).
— The value of the R/W flag of the PML5E.
— The value of the U/S flag of the PML5E.— The value of the XD flag of the PML5E.
— The values of the PCD and PWT flags of the PML5E.
The following items detail how a processor may use the PML5E cache:
— If the processor has a PML5E-cache entry for a linear address, it may use that entry when translating the 
linear address (instead of the PML5E in memory).
— The processor does not create a PML5E-cache entry unless the P flag is 1 and all reserved bits are 0 in the 
PML5E in memory.
— The processor does not create a PML5E-cache entry unless the accessed flag is 1 in the PML5E in memory; 
before caching a translation, the processor sets the accessed flag if it is not already 1.
— The processor may create a PML5E-cache entry even if there are no translations for any linear address that 
might use that entry (e.g., because the P flags are 0 in all entries in the referenced PML4 table).
— If the processor creates a PML5E-cache entry, the pr ocessor may retain it unmodified even if software 
subsequently modifies the corresponding PML5E in memory.
•PML4E cache  (4-level paging and 5-level paging only). Th e use of the PML4E cache depends on the paging 
mode:
— For 4-level paging, each PML4E-cache entry is referenced by a 9-bit value and is used for linear addresses 
for which bits 47:39 have that value.
— For 5-level paging, each PML4E-cache entry is referenced by an 18-bit value and is used for linear 
addresses for which bits 56:39 have that value.
A PML4E-cache entry contains information from the PML5 E and PML4E used to translate the relevant linear 
addresses (for 4-level paging, the PML5E does not apply):Vol. 3A 4-45PAGING
— The physical address from the PML4E (the address of the page-directory-pointer table).
— The logical-AND of the R/W flags in the PML5E and the PML4E.
— The logical-AND of the U/S flags in the PML5E and the PML4E.— The logical-OR of the XD flags in the PML5E and the PML4E.
— The values of the PCD and PWT flags of the PML4E.
The following items detail how a processor may use the PML4E cache:
— If the processor has a PML4E-cache entry for a linear address, it may use that entry when translating the 
linear address (instead of the PML5E and PML4E in memory).
— The processor does not create a PML4E-cache entry unl ess the P flags are 1 and all reserved bits are 0 in

— The processor does not create a PML4E-cache entry unl ess the P flags are 1 and all reserved bits are 0 in 
the PML5E and the PML4E in memory.
— The processor does not create a PML4E-cache entry unless the accessed flags are 1 in the PML5E and the 
PML4E in memory; before caching a translation, the pr ocessor sets any accessed flags that are not already 
1.
— The processor may create a PML4E-cache entry even if there are no translations for any linear address that 
might use that entry (e.g., because the P flags are 0 in all entries in the referenced page-directory-pointer table).
— If the processor creates a PML4E-cache entry, the pr ocessor may retain it unmod ified even if software 
subsequently modifies the corresponding PML4E in memory.
•PDPTE cache  (4-level paging and 5-level paging only).1 The use of the PML4E cache depends on the paging 
mode:
— For 4-level paging, each PDPTE-cache entry is referenced by an 18-bit value and is used for linear 
addresses for which bits 47:30 have that value.
— For 5-level paging, each PDPTE-cache entry is referenc ed by a 27-bit value and is used for linear addresses 
for which bits 56:30 have that value.
A PDPTE-cache entry contains information from the PML5E,  PML4E, PDPTE used to tran slate the relevant linear 
addresses (for 4-level paging, the PML5E does not apply):
— The physical address from the PDPTE (the address of the page directory). (No PDPTE-cache entry is created 
for a PDPTE that maps a 1-GByte page.)
— The logical-AND of the R/W flags in the PML5E, PML4E, and PDPTE.
— The logical-AND of the U/S flags in the PML5E, PML4E, and PDPTE.
— The logical-OR of the XD flags in the PML5E, PML4E, and PDPTE.
— The values of the PCD and PWT flags of the PDPTE.
The following items detail how a processor may use the PDPTE cache:
— If the processor has a PDPTE-cache entry for a linear address, it may use that entry when translating the 
linear address (instead of the PML5 E, PML4E, and PDPTE in memory).
— The processor does not create a PDPTE-cache entry unless the P flags are 1, the PS flags are 0, and the 
reserved bits are 0 in the PML5E, PML4E, and PDPTE in memory.
— The processor does not create a PDPTE-cache entry unless the accessed flags are 1 in the PML5E, PML4E, 
and PDPTE in memory; before caching a translation, the processor sets any accessed flags that are not 
already 1.
— The processor may create a PDPTE-ca che entry even if there are no translations for any linear address that 
might use that entry.
— If the processor creates a PDPTE-cache entry, the pr ocessor may retain it unmodified even if software 
subsequently modifies the corresponding  PML5E, PML4E, or PDPTE in memory.
1. With PAE paging, the PDPTEs are stored in internal, non-architectural registers. The operation of these registers is describe d in Sec-
tion 4.4.1 and differs from that described here.4-46 Vol. 3APAGING
•PDE cache . The use of the PDE cache depends on the paging mode:
— For 32-bit paging, each PDE-cache entry is referenced by a 10-bit value and is used for linear addresses for 
which bits 31:22 have that value.
— For PAE paging, each PDE-cache entry is referenced by an 11-bit value and is used for linear addresses for 
which bits 31:21 have that value.
— For 4-level paging, each PDE-cache entry is referenced by a 27-bit value and is used for linear addresses for 
which bits 47:21 have that value.
— For 5-level paging, each PDE-cache entry is referenced by a 36-bit value and is used for linear addresses for 
which bits 56:21 have that value.
A PDE-cache entry contains information from the PML5E, PML4E, PDPTE, and PDE used to translate the relevant 
linear addresses (for 32-bit paging and PAE paging, only  the PDE applies; for 4-level paging, the PML5E does 
not apply):
— The physical address from the PDE (the address of the page table). (No PDE-cache entry is created for a 
PDE that maps a page.)
— The logical-AND of the R/W flags in the PML5E, PML4E, PDPTE, and PDE.— The logical-AND of the U/S flags in the PML5E, PML4E, PDPTE, and PDE.— The logical-OR of the XD flags in the PML5E, PML4E, PDPTE, and PDE.
— The values of the PCD and PWT flags of the PDE.
The following items detail how a processor may use th e PDE cache (references below to PML5Es, PML4Es, and 
PDPTEs apply only to 4-level paging and to 5-level paging, as appropriate):
— If the processor has a PDE-cache entry for a linear address, it may use that entry when translating the 
linear address (instead of the PML5E, PML4E, PDPTE, and PDE in memory).
— The processor does not create a PDE-cache entry unless the P flags are 1, the PS flags are 0, and the 
reserved bits are 0 in the PML5E, PML4E, PDPTE, and PDE in memory.
— The processor does not create a PDE-cache entry unless the accessed flag is 1 in the PML5E, PML4E, PDPTE, 
and PDE in memory; before caching a translation, the processor sets any accessed flags that are not 
already 1.
— The processor may create a PDE-cache entry even if there are no translations for any linear address that 
— If the processor creates a PDE-cache entry, the processo r may retain it unmodified even if software subse-
quently modifies the corresponding PML5 E, PML4E, PDPTE, or PDE in memory.
Information from a paging-structure entry can be included in entries in the paging-structure caches for other 
paging-structure entries referenced by the original entry. Fo r example, if the R/W flag is 0 in a PML4E, then the R/W 
flag will be 0 in any PDPTE-cache entry for a PDPTE from the page-directory-pointer table referenced by that 
PML4E. This is because the R/W flag of each such PDPT E-cache entry is the logical-AND of the R/W flags in the 
appropriate PML4E and PDPTE.
On processors that support HLAT paging (see Section 4.5.1), each entry in a paging-structure cache indicates 
whether the entry was cached during ordinary paging or HLAT paging. When the processor commences linear-
address translation using ordinary paging (respectively, HLAT paging), it will use only entries that indicate that they 
were cached during ordinary paging (respectively, HLAT paging).
Entries that were cached during HLAT paging also include the restart flag (bit 11) of the original paging-structure 
entry. When the processor commences HLAT paging using su ch an entry, it immediately restarts (using ordinary 
paging) if this cached restart flag is 1.
The paging-structure caches contain information only from paging-structure entries that reference other paging 
structures (and not those that map pages). Because the G fl ag is not used in such paging-structure entries, the 
global-page feature does not affect the behavior of the paging-structure caches.
The processor may create entries in paging-structure caches for translations required for prefetches and for 
accesses that are a result of speculative execution that would never actually occur in the executed code path.Vol. 3A 4-47PAGING
As noted in Section 4.10.1, any entries created in paging -structure caches by a logical processor are associated 
with the current PCID.
A processor may or may not implement any of the paging-str ucture caches. Software should rely on neither their 
presence nor their absence. The processor may invalidate entries in these caches at any time. Because the processor may create the cache entries at the time of tr anslation and not update them following subsequent modi-
fications to the paging structures in memory, software should take care to invalidate the cache entries appropri-
ately when causing such modifications. The invalidation of TLBs and the paging-structure caches is described in Section 4.10.4.
4.10.3.2  Using the Paging-Structure Caches to Translate Linear Addresses
When a linear address is accessed, the processor uses a pr ocedure such as the following to determine the physical 
address to which it translates and whether the access should be allowed:
•If the processor finds a TLB entry that is for the page nu mber of the linear address and that is associated with 
the current PCID (or which is global), it may use the physical address, access rights, and other attributes from 
that entry.
•If the processor does not find a relevant TLB entry, it may use the upper bits of the linear address to select an 
entry from the PDE cache that is associated with the current PCID (Section 4.10.3.1 indicates which bits are 
used in each paging mode). It can then use that entry to complete the translation process (locating a PTE, etc.) 
as if it had traversed the PDE (and, for 4-level paging  and 5-level paging, the PDPTE, PML4E, and PML5E, as 
appropriate) corresponding to the PDE-cache entry.
•The following items apply when 4-level paging or 5-level paging is used:
— If the processor does not find a relevant TLB entry or PDE-cache entry, it may use the upper bits of the 
linear address (for 4-level paging, bits 47:30; for 5-le vel paging, bits 56:30) to select an entry from the 
PDPTE cache that is associated with the current PCID. It can then use that entry to complete the translation 
process (locating a PDE, etc.) as if it had traverse d the PDPTE, the PML4E, and (for 5-level paging) the 
PML5E corresponding to the PDPTE-cache entry.

— If the processor does not find a relevant TLB entry, PDE-cache entry, or PDPTE-cache entry, it may use the 
upper bits of the linear address (for 4-level paging, bi ts 47:39; for 5-level paging, bits 56:39) to select an 
entry from the PML4E cache that is associated with the current PCID. It can then use that entry to complete 
the translation process (locating a PDPTE, etc.) as if it had traversed the corresponding PML4E.
— With 5-level paging, if the processor does not find a relevant TLB entry, PDE-cache entry, PDPTE-cache 
entry, or PML4E-cache entry, it may use bits 56:48 of the linear address to select an entry from the PML5E 
cache that is associated with the current PCID. It can then use that entry to complete the translation 
process (locating a PML4E, etc.) as if it had traversed the corresponding PML5E.
(Any of the above steps would be skipped if the processor does not support the cache in question.)
If the processor does not find a TLB or paging-structure -cache entry for the linear address, it uses the linear 
address to traverse the entire paging-structure hierarchy,  as described in Section 4.3, Section 4.4.2, and Section 
4.5.
4.10.3.3  Multiple Cached Entries for a Single Paging-Structure Entry
The paging-structure caches and TLBs may contain multiple  entries associated with a single PCID and with infor-
mation derived from a single paging-structure entry. Th e following items give some examples for 4-level paging:
•Suppose that two PML4Es contain the same physical address and thus reference the same page-directory-
pointer table. Any PDPTE in that table may result in tw o PDPTE-cache entries, each associated with a different 
set of linear addresses. Specifically, suppose that the n1th and n2th entries in the PML4 table contain the same 
physical address. This implies that the physical address in the mth PDPTE in the page-directory-pointer table 
would appear in the PDPTE-cache entries associated with both p1 and p2, where (p1» 9) = n1, (p2» 9) = n2, 
and (p1& 1FFH) = (p2& 1FFH) = m. This is because both PDPTE-cache entries use the same PDPTE, one 
resulting from a reference from the n1th PML4E and one from the n2th PML4E.
•Suppose that the first PML4E (i.e., the one in position 0)  contains the physical address X in CR3 (the physical 
address of the PML4 table). This implies the following:4-48 Vol. 3APAGING
— Any PML4-cache entry associated with linear addresses with 0 in bits 47:39 contains address X.
— Any PDPTE-cache entry associated with linear addresses with 0 in bits 47:30 contains address X. This is 
because the translation for a linear address for which the value of bits 47:30 is 0 uses the value of 
bits 47:39 (0) to locate a page-directory-pointer table at  address X (the address of the PML4 table). It then 
uses the value of bits 38:30 (also 0) to find address X again and to store that address in the PDPTE-cache 
entry.
— Any PDE-cache entry associated with linear addresses with 0 in bits 47:21 contains address X for similar 
reasons.
— Any TLB entry for page number 0 (associated with linear  addresses with 0 in bits 47:12) translates to page 
frame X » 12 for similar reasons.
The same PML4E contributes its address X to all these ca che entries because the self-referencing nature of the 
entry causes it to be used as a PML4E, a PDPTE, a PDE, and a PTE.
4.10.4 Invalidation of TLBs and Paging-Structure Caches
As noted in Section 4.10.2 and Section 4.10.3, the proce ssor may create entries in the TLBs and the paging-struc-
ture caches when linear addresses are translated, and it ma y retain these entries even after the paging structures 
used to create them have been modified. To ensure that  linear-address translation uses the modified paging struc-
tures, software should take action to invalidate any cached entries that may contain information that has since 
been modified.
4.10.4.1  Operations that Invalida te TLBs and Paging-Structure Caches
The following instructions invalidate entries in the TLBs and the paging-structure caches:
•INVLPG. This instruction takes a single operand, which is a linear address. The instruction invalidates any TLB 
entries that are for a page number corresponding to the linear address and that are associated with the current 
PCID. It also invalidates any global TLB entries with  that page number, regardless of PCID (see Section 
4.10.2.4).1 INVLPG also invalidates all entries in all paging-structure caches associated with the current PCID, 
regardless of the linear addresses to which they correspond.
•INVPCID. The operation of this instruction is based on  instruction operands, called the INVPCID type and the 
INVPCID descriptor. Four INVPCID types are currently defined:
— Individual-address. If the INVPCID type is 0, the logical processor invalidates mappings—except global 
translations—associated with the PCID specified in the INVPCID descriptor and that would be used to 
translate the linear address spec ified in the INVPCID descriptor.2 (The instruction may also invalidate global 
translations, as well as mappings associated with other PCIDs and for other linear addresses.)
— Single-context. If the INVPCID type is 1, the logi cal processor invalidates all mappings—except global 
translations—associated with the PCID specified in the INVPCID descriptor. (The instruction may also 
invalidate global translations, as well as mappings associated with other PCIDs.)
— All-context, including globals. If the INVPCID type is 2, the logical processor invalidates 
mappings—including global translations—associated with all PCIDs.
— All-context. If the INVPCID type is 3, the logical processor invalidates mappings—except global transla-
tions—associated with all PCIDs. (The instruction may also invalidate global translations.)
See Chapter 3 of the Intel 64 and IA-32 Architecture Soft ware Developer’s Manual, Volume 2A  for details of the 
INVPCID instruction.
•MOV to CR0. The instruction invalidates all TLB entries (i ncluding global entries) and all entries in all paging-
structure caches (for all PCIDs) if it changes the value of CR0.PG from 1 to 0.
•MOV to CR3. The behavior of the instruction depends on the value of CR4.PCIDE:
(see Section 4.10.2.3), the instruction invalidates all of them.
2. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that  page 
(see Section 4.10.2.3), the instruction invalidates all of them.Vol. 3A 4-49PAGING
— If CR4.PCIDE = 0, the instruction invalidates all TLB entries associated with PCID 000H except those for 
global pages. It also invalidates all entries in all paging-structure caches associated with PCID 000H.
— If CR4.PCIDE = 1 and bit 63 of the instruction’s source operand is 0, the instruction invalidates all TLB 
entries associated with the PCID specified in bits 11:0 of the instruction’s source operand except those for global pages. It also invalidates all entries in all paging -structure caches associated with that PCID. It is not 
required to invalidate entries in the TLBs and paging-s tructure caches that are associated with other PCIDs.
— If CR4.PCIDE = 1 and bit 63 of the instruction’s source  operand is 1, the instruction is not required to 
invalidate any TLB entries or entr ies in paging-structure caches.
•MOV to CR4. The behavior of the instruct ion depends on the bits being modified:
— The instruction invalidates all TLB entries (including global entries) and all entries in all paging-structure 
caches (for all PCIDs) if (1) it changes the value of CR4.PGE;1 or (2) it changes the value of the CR4.PCIDE 
from 1 to 0.
— The instruction invalidates all TLB entries and all entrie s in all paging-structure caches for the current PCID 
if (1) it changes the value of CR4.PAE; or (2) it changes the value of CR4.SMEP from 0 to 1.
•Task switch. If a task switch changes the value of CR3, it invalidates all TLB entries associated with PCID 000H 
except those for global pages. It also invalidates all entries in all paging-structure caches associated with PCID 
000H.2
•VMX transitions. See Section 4.11.1.
The processor is always free to invalidate additional entr ies in the TLBs and paging-structure caches. The following 
are some examples:
•INVLPG may invalidate TLB entries for pages other than the one corresponding to its linear-address operand. It 
may invalidate TLB entries and paging-structure-cache entries associated with PCIDs other than the current 
PCID.
•INVPCID may invalidate TLB entries for pages other than the one corresponding to the specified linear address. 
It may invalidate TLB entries and paging-structure-cac he entries associated with PCIDs other than the 
specified PCID.
•MOV to CR0 may invalidate TLB entries even if CR0.PG is  not changing. For example, this may occur if either 
CR0.CD or CR0.NW is modified.

000H.2
PCID.
•MOV to CR3 may invalidate TLB entries for global pages. If CR4.PCIDE = 1 and bit 63 of the instruction’s source 
operand is 0, it may invalidate TLB entries and entries in the paging-structure caches associated with PCIDs 
other than the PCID it is establishing. It may invalidate  entries if CR4.PCIDE = 1 and bit 63 of the instruction’s 
source operand is 1. 
•MOV to CR4 may invalidate TLB entries when changing  CR4.PSE or when changing CR4.SMEP from 1 to 0.
•On a processor supporting Hyper-Threading Technology, invalidations performed on one logical processor may 
invalidate entries in the TLBs and paging-structure caches used by other logical processors.
(Other instructions and operations may invalidate entries in the TLBs and the paging-structure caches, but the 
instructions identified above are recommended.)
In addition to the instructions identified above, page faults invalidate entries in the TLBs and paging-structure 
caches. In particular, a page-fault exception resulting from  an attempt to use a linear address will invalidate any 
TLB entries that are for a page number corresponding to that linear address and that are associated with the 
current PCID. It also invalidates all entries in the paging-str ucture caches that would be used for that linear address 
and that are associated with the current PCID.3 These invalidations ensure that the page-fault exception will not 
recur (if the faulting instruction is re-executed) if it woul d not be caused by the contents of the paging structures 
1. If CR4.PGE is changing from 0 to 1, there were no global TLB entries before the execution; if CR4.PGE is changing from 1 to 0 , there 
will be no global TLB en tries after the execution.
2. Task switches do not occur in IA-32e mode and thus cannot occur with 4-level paging. Since CR4.PCIDE can be set only with 4-l evel 
paging, task switch es occur only with CR4.PCIDE = 0.
3. Unlike INVLPG, page faults need not invalidate all entries in the paging-structure caches, on ly those that would be used to translate 
the faulting linear address.4-50 Vol. 3APAGING
in memory (and if, therefore, it resulted from cached en tries that were not invalidated after the paging structures 
were modified in memory).
As noted in Section 4.10.2, some processors may choose to cache multiple smaller-page TLB entries for a transla-
tion specified by the paging structures to use a page larger than 4 KBytes. There is no way for software to be aware 
that multiple translations for smaller pages have been used for a large page. The INVLPG instruction and page 
faults provide the same assurances th at they provide when a single TLB entry is used: they invalidate all TLB 
entries corresponding to the translation specified by the paging structures.
4.10.4.2  Recommended Invalidation
The following items provide some recommendations rega rding when software should perform invalidations:
•If software modifies a paging-structure entry that maps a page (rather than referencing another paging 
structure), it should execute INVLPG for any linear ad dress with a page number whose translation uses that 
paging-structure entry.1
(If the paging-structure entry may be used in the tran slation of different page numbers — see Section 4.10.3.3 
— software should execute INVLPG for linear addresses with each of those page numbers; alternatively, it could 
use MOV to CR3 or MOV to CR4.)
•If software modifies a paging-structure entry that refe rences another paging structure, it may use one of the 
following approaches depending upon the types and number of translations controlled by the modified entry:
— Execute INVLPG for linear addresses with each of th e page numbers with translations that would use the 
entry. However, if no page numbers that would use the entry have translations (e.g., because the P flags are 
0 in all entries in the paging structure referenced by the modified entry), it remains necessary to execute 
INVLPG at least once.
— Execute MOV to CR3 if the modified entry controls no global pages.
— Execute MOV to CR4 to modify CR4.PGE.
•If CR4.PCIDE = 1 and software modifies a paging-structu re entry that does not map a page or in which the G 
flag (bit 8) is 0, additional steps are required if the entry may be used for PCIDs other than the current one. Any 
one of the following suffices:
— Execute MOV to CR4 to modify CR4.PGE, either immediately or before again using any of the affected 
PCIDs. For example, software could use different (pre viously unused) PCIDs for the processes that used the 
affected PCIDs.
— For each affected PCID, execute MOV to CR3 to make that PCID current (and to load the address of the 
appropriate PML4 table). If the modified entry controls  no global pages and bit 63 of the source operand to 
MOV to CR3 was 0, no further steps are required. Otherw ise, execute INVLPG for linear addresses with each 
of the page numbers with translations that would use the entry; if no page numbers that would use the entry have translations, execute INVLPG at least once.
•If software using PAE paging modifies a PDPTE, it should  reload CR3 with the register’s current value to ensure 
that the modified PDPTE is loaded into the corresponding PDPTE register (see Section 4.4.1).
•If the nature of the paging structures is such that a si ngle entry may be used for multiple purposes (see Section 
4.10.3.3), software should perform invalidations for all of these purposes. For example, if a single entry might 
serve as both a PDE and PTE, it may be necessary to ex ecute INVLPG with two (or more) linear addresses, one 
that uses the entry as a PDE and one that uses it as a PTE. (Alternatively, software could use MOV to CR3 or 
MOV to CR4.)
•As noted in Section 4.10.2, the TLBs may subsequently contain multiple translations for the address range if 
software modifies the paging structures so that the pa ge size used for a 4-KByte range of linear addresses 
changes. A reference to a linear address in the address range may use any of these translations.
Software wishing to prevent this uncertainty should not write to a paging-structure entry in a way that would 
change, for any linear address, both the page size and ei ther the page frame, access rights, or other attributes. 
It can instead use the following algorithm: first clear th e P flag in the relevant paging-structure entry (e.g., 
1. One execution of INVLPG is sufficient even for a page with size greater than 4 KBytes.Vol. 3A 4-51PAGING
PDE); then invalidate any translations for the affected  linear addresses (see above); and then modify the 
relevant paging-structure entry to set the P flag and es tablish modified translation(s) for the new page size.
•Software should clear bit 63 of the source operand to a MOV to CR3 instruction that establishes a PCID that had 
been used earlier for a different linear-address space (e.g ., with a different value in bits 51:12 of CR3). This 
ensures invalidation of any information that may have been cached for the previous linear-address space.
This assumes that both linear-address spaces use the same global pages and that it is thus not necessary to 
invalidate any global TLB entries. If that is not the ca se, software should invalidate those entries by executing 
MOV to CR4 to modify CR4.PGE.
4.10.4.3  Optional Invalidation
The following items describe cases in which software may choose not to invalidate and the potential consequences of that choice:
•If a paging-structure entry is modified to change the P fl ag from 0 to 1, no invalidation is necessary. This is 
because no TLB entry or paging-structure cache entry is created with information from a paging-structure 
entry in which the P flag is 0.1
•If a paging-structure entry is modified to change the accessed flag from 0 to 1, no invalidation is necessary 
(assuming that an invalidation was performed the last time the accessed flag was changed from 1 to 0). This is 
entry in which the accessed flag is 0.
•If a paging-structure entry is modified to change the R/ W flag from 0 to 1, failure to perform an invalidation 
may result in a “spurious” page-fault exception (e.g., in response to an attempted write access) but no other 
adverse behavior. Such an exception will occur at most once for each affected linear address (see Section 
4.10.4.1).
•If CR4.SMEP = 0 and a paging-structure entry is modified to  change the U/S flag from 0 to 1, failure to perform 
an invalidation may result in a “spurious” page-fault ex ception (e.g., in response to an attempted user-mode 
access) but no other adverse behavior. Such an exception will occur at most once for each affected linear 
address (see Section 4.10.4.1).
•If a paging-structure entry is modified to change the XD flag from 1 to 0, failure to perform an invalidation may result in a “spurious” page-fault exception (e.g., in re sponse to an attempted instruction fetch) but no other

•If a paging-structure entry is modified to change the XD flag from 1 to 0, failure to perform an invalidation may result in a “spurious” page-fault exception (e.g., in re sponse to an attempted instruction fetch) but no other 
•If a paging-structure entry is modified to change the accessed flag from 1 to 0, failure to perform an invali-
dation may result in the processor not setting that bit in response to a subsequent access to a linear address 
whose translation uses the entry. Software cannot interpret the bit being clear as an indication that such an 
access has not occurred.
•If software modifies a paging-structure entry that identifies the final physical address for a linear address (either a PTE or a paging-structure entry in which the PS flag is 1) to change the dirty flag from 1 to 0, failure 
to perform an invalidation may result in the processor no t setting that bit in response to a subsequent write to 
a linear address whose translation uses the entry. Software cannot interpret the bit being clear as an indication that such a write has not occurred.
•The read of a paging-structure entry in translating an ad dress being used to fetch an instruction may appear to 
execute before an earlier write to that paging-structure entry if there is no serializing instruction between the 
write and the instruction fetch. Note that the invalidat ing instructions identified in Section 4.10.4.1 are all 
serializing instructions.
•Section 4.10.3.3 describes situations in which a single paging-structure entry may contain information cached 
in multiple entries in the paging-structure caches. Beca use all entries in these caches are invalidated by any 
execution of INVLPG, it is not necessary to follow the modification of such a paging-structure entry by executing INVLPG multiple times solely for the purpose of invalidating these multiple cached entries. (It may be 
necessary to do so to invalidate multiple TLB entries.)
1. If it is also the case that no invalidation was performed the last time the P flag was changed from 1 to 0, the processor may  use a 
TLB entry or paging-structure ca che entry that was created when the P flag had earlier been 1.4-52 Vol. 3APAGING
4.10.4.4  Delayed Invalidation
Required invalidations may be delaye d under some circumstances. Software developers should understand that, 
between the modification of a paging-structure entry and execution of the invalidation instruction recommended in 
Section 4.10.4.2, the processor may use translations based on either the old value or the new value of the paging-
structure entry. The following items describe some of the potential consequences of delayed invalidation:
•If a paging-structure entry is modified to change the P flag from 1 to 0, an access to a linear address whose 
translation is controlled by this entry may or may not cause a page-fault exception.
•If a paging-structure entry is modified to change the R/W flag from 0 to 1, write accesses to linear addresses 
whose translation is controlled by this entry may or may not cause a page-fault exception.
•If a paging-structure entry is modified to change th e U/S flag from 0 to 1, user-mode accesses to linear 
addresses whose translation is controlled by this entry may or may not cause a page-fault exception.
•If a paging-structure entry is modified to change the XD flag from 1 to 0, instruction fetches from linear 
As noted in Section 9.1.1, an x87 instruction or an SSE instruction that accesses data larger than a quadword may 
be implemented using multiple memory accesses. If such an instruction stores to memory and invalidation has 
been delayed, some of the accesses may complete (writi ng to memory) while another causes a page-fault excep-
tion.1 In this case, the effects of the completed accesses may be visible to software even though the overall instruc-
tion caused a fault.
In some cases, the consequences of delayed invalidation may not affect software adversely. For example, when 
freeing a portion of the linear-address space (by marking paging-structure entries “not present”), invalidation 
using INVLPG may be delayed if software does not re-a llocate that portion of the linear-address space or the 
memory that had been associated with it. However, beca use of speculative execution (or errant software), there 
may be accesses to the freed portion of the linear-address space before the invalidations occur. In this case, the 
following can happen:
•Reads can occur to the freed portion of the linear-address space. Therefore, invalidation should not be delayed 
for an address range that has read side effects.
•The processor may retain entries in the TLBs and paging -structure caches for an extended period of time. 
Software should not assume that the processor will no t use entries associated with a linear address simply 
because time has passed.
•As noted in Section 4.10.3.1, the processor may create an  entry in a paging-structure cache even if there are 
no translations for any linear address that might use that entry. Thus, if software has marked “not present” all entries in a page table, the processor may subsequently  create a PDE-cache entry for the PDE that references 
that page table (assuming that the PDE itself is marked “present”).
•If software attempts to write to the freed portion of the linear-address space, the processor might not generate 
a page fault. (Such an attempt would lik ely be the result of a software erro r.) For that reason, the page frames 
previously associated with the freed portion of the li near-address space should not be reallocated for another 
purpose until the appropriate invalidations have been performed.
4.10.5 Propagation of Paging-Structure  Changes to Multiple Processors
As noted in Section 4.10.4, software that modifies a pagi ng-structure entry may need to invalidate entries in the 
TLBs and paging-structure caches that were derived from the modified entry before it was modified. In a system 
containing more than one logical processor, software must account for the fact that there may be entries in the 
TLBs and paging-structure caches of logical processors other than the one used to modify the paging-structure 
entry. The process of propagating the changes to a paging -structure entry is commonly referred to as “TLB shoot-
down.”
TLB shootdown can be done using memory-based semaphores  and/or interprocessor interrupts (IPI). The following 
items describe a simple but inefficient example of a TLB shootdown algorithm for processors supporting the 
Intel-64 and IA-32 architectures:
1. If the accesses are to different pages, this ma y occur even if invalidation has not been delayed.Vol. 3A 4-53PAGING
1. Begin barrier: Stop all but one logical processor; that is, cause all but one to execute the HLT instruction or to 
enter a spin loop.
2. Allow the active logical processor to chan ge the necessary paging-structure entries.
3. Allow all logical processors to perform invalidations ap propriate to the modifications to the paging-structure 
entries.
4. Allow all logical processors to resume normal operation.
Alternative, performance-optimized, TLB shootdown algori thms may be developed; however, software developers 
must take care to ensure that the following conditions are met:
•All logical processors that are using the paging structur es that are being modified must participate and perform 
appropriate invalidations after the modifications are made.
•If the modifications to the paging-structure entries are made before the barrier or if there is no barrier, the 
operating system must ensure one of the following: (1 ) that the affected linear-address range is not used 
between the time of modification and the time of invalida tion; or (2) that it is prepared to deal with the conse-
quences of the affected linear-address range being used  during that period. For example, if the operating 
system does not allow pages being freed to be realloca ted for another purpose until after the required invalida-
tions, writes to those pages by errant software w ill not unexpectedly modify memory that is in use.
•Software must be prepared to deal with reads, instruct ion fetches, and prefetch requests to the affected linear-
address range that are a result of speculative execution that would never actually occur in the executed code 
path.
When multiple logical processors are using the same line ar-address space at the same time, they must coordinate 
before any request to modify the paging-structure entries that control that linear-address space. In these cases, 
the barrier in the TLB shootdown routine may not be re quired. For example, when freeing a range of linear 
addresses, some other mechanism can assure no logical processor is using that range before the request to free it is made. In this case, a logical processor freeing the range can clear the P flags in the PTEs associated with the 
range, free the physical page frames associated with the range, and then signal the other logical processors using

path.
range, free the physical page frames associated with the range, and then signal the other logical processors using 
that linear-address space to perform the necessary invalidat ions. All the affected logical processors must complete 
their invalidations before the linear-address range and the physical page frames previously associated with that 
range can be reallocated.
4.11 INTERACTIONS WITH VIRT UAL-MACHINE EXTENSIONS (VMX)
The architecture for virtual-machine extensions (VMX) incl udes features that interact with paging. Section 4.11.1 
discusses ways in which VMX-specific control transfers, called VMX transitions specially affect paging. Section 
4.11.2 gives an overview of VMX features specif ically designed to support address translation.
4.11.1 VMX Transitions
The VMX architecture defines two control transfers called VM entries  and VM exits ; collectively, these are called 
VMX transitions . VM entries and VM exits are described in detail in Chapter 27 and Chapter 28, respectively, in 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C. The following items identify 
paging-related details:
•VMX transitions modify the CR0 and CR4 registers and the IA32_EFER MSR concurrently. For this reason, they 
allow transitions between paging modes that would not otherwise be possible:
— VM entries allow transitions from 4-level paging directly to either 32-bit paging or PAE paging.— VM exits allow transitions from either 32-bit paging or PAE paging directly to 4-level paging or 5-level 
paging.
•VMX transitions that result in PAE paging load the PDPTE registers (see Section 4.4.1) as follows:
— VM entries load the PDPTE registers either from the physical address being loaded into CR3 or from the 
virtual-machine control structure (VMCS); see Section 27.3.2.4.
— VM exits load the PDPTE registers from the physical address being loaded into CR3; see Section 28.5.4.4-54 Vol. 3APAGING
•VMX transitions invalidate the TLBs and paging-structure caches based on certain control settings. See Section 
27.3.2.5 and Section 28.5.5 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C.
4.11.2 VMX Support for Address Translation
Chapter 29, “VMX Support for Addr ess Translation,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3C, describes two features of the virtual- machine extensions (VMX) that interact directly with 
paging. These are virtual-processor  identifiers  (VPIDs ) and the extended page table  mechanism ( EPT).
VPIDs provide a way for software to identify to the proces sor the address spaces for different “virtual processors.” 
The processor may use this identification to maintain conc urrently information for multiple address spaces in its 
TLBs and paging-structure caches, even when non-zero PCIDs are not being used. See Section 29.1 for details.
When EPT is in use, the addresses in the paging-structu res are not used as physical addresses to access memory 
and memory-mapped I/O. Instead, they are treated as guest-physical  addresses and are translated through a set 
of EPT paging structures to produce physical addresses.  EPT can also specify its own access rights and memory 
typing; these are used on conjunction with those specifie d in this chapter. See Section 29.3 for more information.
Both VPIDs and EPT may change the way that a processor maintains information in TLBs and paging structure 
caches and the ways in which software can manage that information. Some of the behaviors documented in Section 4.10 may change. See Section 29.4 for details.
4.12 USING PAGING FOR VIRTUAL MEMORY
With paging, portions of the linear-address space need no t be mapped to the physical-address space; data for the 
unmapped addresses can be stored externally (e.g., on di sk). This method of mapping the linear-address space is 
referred to as virtual memory or  demand-paged virtual memory.
Paging divides the linear address space into fixed-size pa ges that can be mapped into the physical-address space 
and/or external storage. When a program (or task) referenc es a linear address, the processor uses paging to trans-
late the linear address into a corresponding ph ysical address if such an address is defined.
If the page containing the linear address is not currently  mapped into the physical-address space, the processor 
generates a page-fault exception as described in Section 4. 7. The handler for page-fault exceptions typically directs 
the operating system or executive to load data for the unmapped page from external storage into physical memory 
(perhaps writing a different page from physical memory out to external storage in the process) and to map it using 
paging (by updating the paging structures). When the page  has been loaded into physical memory, a return from 
the exception handler causes the instruction that generated the exception to be restarted.
Paging differs from segmentation through its use of fixed- size pages. Unlike segments, which usually are the same 
size as the code or data structures they hold, pages have a fixed size. If segmentation is the only form of address 
translation used, a data structure present in physical memory will have all of its parts in memory. If paging is used, 
a data structure can be partly in memory and partly in disk storage.
4.13 MAPPING SEGMENTS TO PAGES
The segmentation and paging mechanis ms provide support for a wide variety of approaches to memory manage-
ment. When segmentation and paging are combined, segmen ts can be mapped to pages in several ways. To imple-
ment a flat (unsegmented) addressing environment, for example, all the code, data, and stack modules can be 
mapped to one or more large segments (up to 4-GBytes) th at share same range of linear addresses (see Figure 3-2 
in Section 3.2.2). Here, segments are essentially invisible to  applications and the operating-system or executive. If 
paging is used, the paging mechanism can map a single li near-address space (contained in a single segment) into 
virtual memory. Alternatively, each program (or task) can have its own large linear-address space (contained in its 
own segment), which is mapped into virtual memory through its own paging structures.
Segments can be smaller than the size of a page. If one of  these segments is placed in a page which is not shared 
with another segment, the extra memory is wasted. For ex ample, a small data structure, such as a 1-Byte sema-
phore, occupies 4 KBytes if it is placed  in a page by itself. If many semaphores are used, it is more efficient to pack 
them into a single page.Vol. 3A 4-55PAGING
The Intel-64 and IA-32 architectures do not enforce correspondence between the boundaries of pages and 
segments. A page can contain the end of one segment an d the beginning of another. Similarly, a segment can 
contain the end of one page and the beginning of another.
Memory-management software may be simpler and more effi cient if it enforces some alignment between page and 
segment boundaries. For example, if a segment which can fi t in one page is placed in two pages, there may be 
twice as much paging overhead to support access to that segment.
One approach to combining paging and segmentation that simplifies memory-management software is to give 
each segment its own page table, as shown in Figure 4-13. This convention gives the segment a single entry in the 
page directory, and this entry provides the access control information for paging the entire segment.
Figure 4-13.  Memory Management Convention That Assigns a Page Table to Each SegmentSeg. Descript.LDT
Seg. Descript.PDEPage Directory
PDEPTE
PTEPTE
PTE
PTEPage TablesPage Frames4-56 Vol. 3APAGINGVol. 3A 5-1CHAPTER 5
In protected mode, the Intel 64 and IA-32 architectures pr ovide a protection mechanism that operates at both the 
segment level and the page level. This protection me chanism provides the ability to limit access to certain 
segments or pages based on privilege le vels (four privilege levels for segments and two privilege levels for pages). 
For example, critical operating-system code and data can be protected by placing them in more privileged 
segments than those that contain applications code. The processor’s protection mechanism will then prevent appli-
cation code from accessing the operating-system code and data in any but a controlled, defined manner.
Segment and page protection can be used at all stages of software development to assist in localizing and detecting 
design problems and bugs. It can also be incorporated into end-products to offer added robustness to operating 
systems, utilities software, and applications software.
When the protection mechanism is used, each memory reference is checked to verify that it satisfies various 
protection checks. All checks are made before the memory cycle is started; any violation results in an exception. 
Because checks are performed in parallel with address tran slation, there is no performance penalty. The protection 
checks that are performed fall into the following categories:
•Limit checks.
•Type checks.
•Privilege level checks.
•Restriction of addressable domain.

•Restriction of procedure entry-points.
•Restriction of instruction set.
All protection violation results in an exception being gene rated. See Chapter 6, “Interrupt and Exception Handling,” 
for an explanation of the exception mechanism. This ch apter describes the protection mechanism and the viola-
tions which lead to exceptions.
The following sections describe the protection mechanis m available in protected mode. See Chapter 21, “8086 
Emulation,” for information on protection  in real-address and virtual-8086 mode.
5.1 ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION
Setting the PE flag in register CR0 causes the processor to switch to protected mode, which in turn enables the 
segment-protection mechanism. Once in protected mode, th ere is no control bit for turning the protection mecha-
nism on or off. The part of the segment-protection mechanism that is based on privilege levels can essentially be 
disabled while still in protected mode by assigning a privilege level of 0 (most privileged) to all segment selectors 
and segment descriptors. This action disables the privile ge level protection barriers between segments, but other 
protection checks such as limit checking and type checking are still carried out.
Page-level protection is automatically enabled when paging is enabled (by setting the PG flag in register CR0). Here 
again there is no mode bit for turning off page-level protec tion once paging is enabled. However, page-level protec-
tion can be disabled by perfor ming the following operations:
•Clear the WP flag in control register CR0.
•Set the read/write (R/W) and user/supervisor (U/S) fl ags for each page-directory and page-table entry. 
This action makes each page a writable, user page , which in effect disables page-level protection.5-2 Vol. 3APROTECTION
5.2 FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND PAGE-LEVEL 
The processor’s protection mechanism uses the following fiel ds and flags in the system data structures to control 
access to segments and pages:
•Descriptor type (S) flag  — (Bit 12 in the second doubleword of a segment descriptor.) Determines if the 
segment descriptor is for a system segment or a code or data segment.
•Type field  — (Bits 8 through 11 in the second doubleword of  a segment descriptor.) Determines the type of 
code, data, or system segment.
•Limit field  — (Bits 0 through 15 of the first doubleword and bits 16 through 19 of the second doubleword of a 
segment descriptor.) Determines the size  of the segment, along with the G fl ag and E flag (for data segments).
•G flag — (Bit 23 in the second doubleword of a segment descr iptor.) Determines the size of the segment, along 
with the limit field and E flag (for data segments).
•E flag — (Bit 10 in the second doubleword of a data-segment  descriptor.) Determines the size of the segment, 
along with the limit field and G flag.
•Descriptor privilege level (DPL) field  — (Bits 13 and 14 in the second doubleword of a segment descriptor.) 
Determines the privilege level of the segment.
•Requested privilege level (RPL) field  — (Bits 0 and 1 of any segment selector.) Specifies the requested 
privilege level of a segment selector. 
•Current privilege level (CPL) field  — (Bits 0 and 1 of the CS segment register.) Indicates the privilege level 
of the currently executing program or procedure. The term  current privilege level (CPL ) refers to the setting of 
this field.
•User/supervisor (U/S) flag  — (Bit 2 of paging-structure entries.) Determines the type of page: user or 
supervisor.
•Read/write (R/W) flag  — (Bit 1 of paging-structure entries.) De termines the type of access allowed to a 
page: read-only or read/write.
•Execute-disable (XD) flag  — (Bit 63 of certain paging-structure entries.) Determines the type of access 
allowed to a page: executable or not-executable.
Figure 5-1 shows the location of the various fields and fl ags in the data-, code-, and system-segment descriptors; 
Figure 3-6 shows the location of the RPL (or CPL) field in  a segment selector (or the CS register); and Chapter 4 
identifies the locations of the U/S, R/W, and XD flags in the paging-structure entries.Vol. 3A 5-3PROTECTION
Many different styles of protection schemes can be impl emented with these fields and flags. When the operating 
system creates a descriptor, it places values in these fields  and flags in keeping with the particular protection style 
chosen for an operating system or executive. Application programs do not generally access or modify these fields 
and flags. 
The following sections describe how the processor uses these fields and flags to perform the various categories of 
checks described in the introduction to this chapter.
5.2.1 Code-Segment Descriptor in 64-bit Mode
Code segments continue to exist in 64-bit mode even th ough, for address calculations, the segment base is treated 
as zero. Some code-segment (CS) descriptor content (the base address and limit fields) is ignored; the remaining fields function normally (except for the readable bit in the type field). 
Code segment descriptors and selectors are needed in IA-32e mode to establish the processor’s operating mode 
and execution privilege-level. The usage is as follows:Figure 5-1.  Descriptor Fields Used for ProtectionBase 23:1631 24232221 20 19 16 15 1314 12 11 87 0
P
LType
10 4
31 1615 0
Base Address 15:00 Segment Limit 15:00 0Base 23:16A
V
LLimit
19:16B
AWE0Data-Segment Descriptor
31 24232221 20 19 16 15 1314 12 11 87 0
P
LType
10 4
31 1615 0
V
LLimit
19:16D
ARC1Code-Segment Descriptor
P
LType 0 4
31 1615 0
Base Address 15:00 Segment Limit 15:00 0Limit
19:16System-Segment Descriptor
A
B
CDDPLAccessed
Big
ConformingDefaultDescriptor Privilege Level
ReservedE
GRLIMIT
W
PExpansion Direction
GranularityReadableSegment Limit
Writable
Present0
AVL Available to Sys. Programmers5-4 Vol. 3APROTECTION
•IA-32e mode uses a previously unused bit in the CS descr iptor. Bit 53 is defined as the 64-bit (L) flag and is 
used to select between 64-bit mode and compatibility mo de when IA-32e mode is active (IA32_EFER.LMA = 1). 
See Figure 5-2.
— If CS.L = 0 and IA-32e mode is active, the processor is running in compatibility mode. In this case, CS.D 
selects the default size for data and addresses. If CS.D = 0, the default data and address size is 16 bits. If 
CS.D = 1, the default data and address size is 32 bits.
— If CS.L = 1 and IA-32e mode is active, the only valid setting is CS.D = 0. This setting indicates a default 
operand size of 32 bits and a default address size of  64 bits. The CS.L = 1 and CS.D = 1 bit combination is 
reserved for future use and a #GP fault will be genera ted on an attempt to use a code segment with these 
bits set in IA-32e mode.
•In IA-32e mode, the CS descriptor’s DPL is used for execution privilege checks (as in legacy 32-bit mode).
5.3 LIMIT CHECKING
The limit field of a segment descriptor prevents programs or procedures from addressing memory locations outside 
the segment. The effective value of the limit depends on th e setting of the G (granularity) flag (see Figure 5-1). For 
data segments, the limit also depends on the E (expansion direction) flag and the B (default stack pointer size 
and/or upper bound) flag. The E flag is one of the bits in the type field when the segment descriptor is for a data-
segment type.
When the G flag is clear (byte granularity), the effective lim it is the value of the 20-bit limit field in the segment 
descriptor. Here, the limit ranges from 0 to FFFFFH (1 MByt e). When the G flag is set (4-KByte page granularity), 
the processor scales the value in the limit field by a factor of 212 (4 KBytes). In this case, the effective limit ranges 
from FFFH (4 KBytes) to FFFFFFFFH (4 GBytes). Note that when  scaling is used (G flag is set), the lower 12 bits of 
a segment offset (address) are not checked against the limit ; for example, note that if the segment limit is 0, 
offsets 0 through FFFH are still valid.
For all types of segments except expand-down data segments , the effective limit is the last address that is allowed 
to be accessed in the segment, which is one less than the size, in bytes, of the segment. The processor causes a 
general-protection exception (or, if the segment is SS, a stack-fault exception) any time an attempt is made to 
access the following addresses in a segment:
•A byte at an offset greater than the effective limit
•A word at an offset greater than the (effective-limit – 1)
•A doubleword at an offset greater than the (effective-limit – 3)
•A quadword at an offset greater than the (effective-limit – 7)Figure 5-2.  Descriptor Fields with Flags used in IA-32e Mode31 24232221 20 19 16 15 1314 12 11 87 0
P GD
P
LType
1L 4
0
0A
V
LD
31
A
C
DDPLAccessed
DefaultDescriptor Privilege LevelG
RGranularity

P GD
P
LType
1L 4
0
0A
V
LD
31
A
C
ReadableAVL Available to Sys. Programmer’s
L 64-Bit FlagP PresentVol. 3A 5-5PROTECTION
•A double quadword at an offset greater than the (effective limit – 15)
When the effective limit is FFFFFFFFH (4 GBytes), these a ccesses may or may not cause the indicated exceptions. 
Behavior is implementation-specific and may vary from one execution to another.
For expand-down data segments, the segment limit has the sa me function but is interpreted differently. Here, the 
effective limit specifies the last address that is not allo wed to be accessed within the segment; the range of valid 
offsets is from (effective-limit + 1) to FFFFFFFFH if the B fl ag is set and from (effective-limit + 1) to FFFFH if the B 
flag is clear. An expand-down segment has maximum size when the segment limit is 0.
Limit checking catches programming errors such as runaway code, runaway subscripts, and invalid pointer calcu-
lations. These errors are detected when they occur, so id entification of the cause is easier. Without limit checking, 
these errors could overwrite code or data in another segment.
In addition to checking segment limits, the processor also  checks descriptor table limits. The GDTR and IDTR regis-
ters contain 16-bit limit values that the processor uses to prevent programs from selecting a segment descriptors 
outside the respective descriptor tables. The LDTR and task  registers contain 32-bit segment limit value (read from 
the segment descriptors for the current LDT and TSS, respectively). The processor uses these segment limits to 
prevent accesses beyond the bounds of the current LDT and TSS. See Section 3.5.1, “Segment Descriptor Tables,” 
for more information on the GDT and LDT limit fields; see Section 6.10, “Interrupt Descriptor Table (IDT),” for more 
information on the IDT limit field; and see Section 8.2.4, “Task Register,” for more information on the TSS segment 
limit field.
5.3.1 Limit Checking in 64-bit Mode
In 64-bit mode, the processor does not perform runtime li mit checking on code or data segments. However, the 
processor does check descriptor-table limits.
5.4 TYPE CHECKING
Segment descriptors contain type information in two places:
•The S (descriptor type) flag.
•The type field.
The processor uses this information to detect programming errors that result in an attempt to use a segment or 
gate in an incorrect or unintended manner.
The S flag indicates whether a descriptor is a system type or a code or data type. The type field provides 4 addi-
tional bits for use in defining variou s types of code, data, and system descriptors. Table 3-1 shows the encoding of 
the type field for code and data descriptors; Table 3-2 shows the encoding of the field for system descriptors.
The processor examines type information at various ti mes while operating on segment selectors and segment 
descriptors. The following list gives examples of typical oper ations where type checking is performed (this list is not 
exhaustive):
•When a segment selector is lo aded into a segment register  — Certain segment registers can contain only 
certain descriptor types, for example:
— The CS register only can be loaded with a selector for a code segment.
— Segment selectors for code segments that are not read able or for system segments cannot be loaded into 
data-segment registers (DS, ES, FS, and GS).
— Only segment selectors of writable data segm ents can be loaded into the SS register.
•When a segment selector is loaded into the LDTR or task register — For example:
— The LDTR can only be loaded with a selector for an LDT.— The task register can only be loaded with a segment selector for a TSS.
•When instructions access segments whose descri ptors are already loaded into segmen t registers — 
Certain segments can be used by instructions only in certain predefined ways, for example:
— No instruction may write into an executable segment.5-6 Vol. 3APROTECTION
— No instruction may write into a data segment if it is not writable.
— No instruction may read an executable segment unless the readable flag is set.
•When an instructio n operand contains a segment selector  — Certain instructions can access segments 
or gates of only a particular type, for example:
— A far CALL or far JMP instruction can only access a segment descriptor for a conforming code segment, 
nonconforming code segment, call gate, task gate, or TSS.
— The LLDT instruction must reference a segment descriptor for an LDT.
— The LTR instruction must reference a segment descriptor for a TSS.— The LAR instruction must reference a segment or gate descriptor for an LDT, TSS, call gate, task gate, code 
segment, or data segment.
— The LSL instruction must reference a segment descripto r for a LDT, TSS, code segment, or data segment.
— IDT entries must be interrupt, trap, or task gates.
•During certain internal operations  — For example:
— On a far call or far jump (executed with a far CALL or far JMP instruction), the processor determines the 
type of control transfer to be carried out (call or jump to another code segment, a call or jump through a 
gate, or a task switch) by checking the type field in the segment (or gate) descriptor pointed to by the 
segment (or gate) selector given as an operand in the CALL or JMP instruction. If the descriptor type is for 
a code segment or call gate, a call or jump to another co de segment is indicated; if the descriptor type is for 
a TSS or task gate, a task switch is indicated.
— On a call or jump through a call gate (or on an interrupt- or exception-handler call through a trap or 
interrupt gate), the processor automatically checks that the segment descriptor being pointed to by the 
gate is for a code segment.
— On a call or jump to a new task through a task gate (or on an interrupt- or exception-handler call to a new 
task through a task gate), the processor automatically  checks that the segment descriptor being pointed to 
by the task gate is for a TSS.
— On a call or jump to a new task by a direct reference to a TSS, the processor automatically checks that the 
segment descriptor being pointed to by th e CALL or JMP instruction is for a TSS.
— On return from a nested task (initiated by an IRET instruction), the processor checks that the previous task 
link field in the current TSS points to a TSS.
5.4.1 Null Segment Selector Checking
Attempting to load a null segment selector (see Section 3.4.2, “Segment Selectors”) into the CS or SS segment 
register generates a general-protection exception (#GP). A null segment selector can be loaded into the DS, ES, 
FS, or GS register, but any attempt to access a segment thro ugh one of these registers when it is loaded with a null 
segment selector results in a #GP exception being genera ted. Loading unused data-segment registers with a null 
segment selector is a useful method of detecting accesses to unused segment registers and/or preventing unwanted accesses to data segments.
5.4.1.1  NULL Segment Ch ecking in 64-bit Mode
In 64-bit mode, the processor does not perform runtime ch ecking on NULL segment selectors. The processor does 
not cause a #GP fault when an attempt is made to acce ss memory where the referenced segment register has a 
NULL segment selector. 
5.5 PRIVILEGE LEVELS
The processor’s segment-protection mechanism recognizes 4 privilege levels, numbered from 0 to 3. The greater 
numbers mean lesser privileges. Figure 5-3 shows how these levels of privilege can be  interpreted as rings of 
protection. Vol. 3A 5-7PROTECTION
The center (reserved for the most privileged code, data, and stacks) is used for the segments containing the critical 
software, usually the kernel of an operating system. Outer rings are used for less critical software. (Systems that 
use only 2 of the 4 possible privilege levels should use levels 0 and 3.) 
The processor uses privilege levels to prevent a program or  task operating at a lesser privilege level from accessing 
a segment with a greater privilege, except under controlled situations. When the processor detects a privilege level 
violation, it generates a general-protection exception (#GP).
To carry out privilege-level checks between code segm ents and data segments, the processor recognizes the 
following three types of privilege levels: 
•Current privilege level (CPL)  — The CPL is the privilege level of the currently executing program or task. It 
is stored in bits 0 and 1 of the CS and SS segment regist ers. Normally, the CP L is equal to the privilege level of 
the code segment from which instructions are being fetched. The processor changes the CPL when program 
control is transferred to a code segment with a different privilege level. The CPL is treated slightly differently 
when accessing conforming code segments. Conforming  code segments can be accessed from any privilege 
level that is equal to or numerically greater (less priv ileged) than the DPL of the conforming code segment. 
Also, the CPL is not changed when the processor accesses a conforming code segment that has a different 
privilege level than the CPL.

•Descriptor privilege level (DPL)  — The DPL is the privilege level of a segment or gate.  It is stored in the DPL 
field of the segment or gate descriptor for the segmen t or gate. When the currently executing code segment 
attempts to access a segment or gate, the DPL of the se gment or gate is compared to the CPL and RPL of the 
segment or gate selector (as described later in this se ction). The DPL is interpreted differently, depending on 
the type of segment or gate being accessed:
—Data segment  — The DPL indicates the numerically highest priv ilege level that a program or task can have 
to be allowed to access the segment. For example, if th e DPL of a data segment is 1, only programs running 
at a CPL of 0 or 1 can access the segment. 
—Nonconforming code segment (without using a call gate)  — The DPL indicates the privilege level that 
a program or task must be at to access the segment.  For example, if the DPL of a nonconforming code 
segment is 0, only programs running at a CPL of 0 can access the segment. 
—Call gate  — The DPL indicates the numerically highest priv ilege level that the currently executing program 
or task can be at and still be able to access the call gate. (This is the same access rule as for a data 
segment.)
—Conforming code segment and nonconforming code segment accessed through a call gate  — The 
DPL indicates the numerically lowest privilege level that  a program or task can have to be allowed to access 
the segment. For example, if the DPL of a conforming co de segment is 2, programs running at a CPL of 0 or 
1 cannot access the segment. Figure 5-3.  Protection RingsLevel 0
Level 1
Level 2
Operating
ServicesSystem
Kernel
Applications5-8 Vol. 3APROTECTION
—TSS — The DPL indicates the numerically highest privile ge level that the currently executing program or 
task can be at and still be able to access the TSS. (T his is the same access rule as for a data segment.)
•Requested privile ge level (RPL)  — The RPL is an override privilege level that is assigned to segment 
selectors. It is stored in bits 0 and 1 of the segment selector. The processor checks the RPL along with the CPL 
to determine if access to a segment is allowed. Even if  the program or task requesting access to a segment has 
sufficient privilege to access the segment, access is denied if  the RPL is not of sufficient  privilege level. That is, 
if the RPL of a segment selector is numerically greater th an the CPL, the RPL overrides the CPL, and vice versa. 
The RPL can be used to ensure that privileged code does not access a segment on behalf of an application 
program unless the program itself has access privileges fo r that segment. See Section 5.10.4, “Checking Caller 
Access Privileges (ARPL Instruction),” for a detailed de scription of the purpose and typical use of the RPL.
Privilege levels are checked when the segment selector of  a segment descriptor is loaded into a segment register. 
The checks used for data access differ from those used  for transfers of program control among code segments; 
therefore, the two kinds of accesses are consid ered separately in the following sections.
5.6 PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS
To access operands in a data segment, the segment select or for the data segment must be loaded into the data-
segment registers (DS, ES, FS, or GS) or into the stack-segment register (SS). (Segment registers can be loaded with the MOV, POP, LDS, LES, LFS, LGS, and LSS instructions.) Before the processor loads a segment selector into 
a segment register, it performs a privilege check (see Figure 5-4) by comparing the privilege levels of the currently 
running program or task (the CPL), the RPL of the se gment selector, and the DPL of the segment’s segment 
descriptor. The processor loads the segment selector into the segment register if the DPL is numerically greater 
than or equal to both the CPL and the RPL. Otherwise, a general-protection fault is generated and the segment 
Figure 5-5 shows four procedures (located in codes segments  A, B, C, and D), each running at different privilege 
levels and each attempting to access the same data segment. 
1. The procedure in code segment A is able to access da ta segment E using segment selector E1, because the CPL 
of code segment A and the RPL of segment select or E1 are equal to the DPL of data segment E.
2. The procedure in code segment B is able to access data segment E using segment selector E2, because the CPL 
of code segment B and the RPL of segment selector E2 are both numerically lower than (more privileged) than 
the DPL of data segment E. A code segment B procedure can also access data segment E using segment selector E1.
3. The procedure in code segment C is not able to access data segment E using segment selector E3 (dotted line), 
because the CPL of code segment C and the RPL of segmen t selector E3 are both numerically greater than (less 
privileged) than the DPL of data segment E. Even if a code segment C procedure were to use segment selector Figure 5-4.  Privilege Check for Data AccessCPL
RPL
DPLPrivilege
CheckData-Segment DescriptorCS Register
For Data SegmentVol. 3A 5-9PROTECTION
E1 or E2, such that the RPL would be acceptable, it st ill could not access data segment E because its CPL is not 
privileged enough.
4. The procedure in code segment D should be able to access data segment E because code segment D’s CPL is 
numerically less than the DPL of data segment E. However, the RPL of segment selector E3 (which the code segment D procedure is using to access data segment E) is numerically greater than the DPL of data segment 
E, so access is not allowed. If the code segment D proc edure were to use segment selector E1 or E2 to access 
the data segment, access would be allowed.
As demonstrated in the previous examples, the addressable domain of a program or task varies as its CPL changes. 
When the CPL is 0, data segments at all privilege levels are accessible; when the CPL is 1, only data segments at 
privilege levels 1 through 3 are accessible; when the CPL is  3, only data segments at privilege level 3 are acces-
sible. 
The RPL of a segment selector can always override the ad dressable domain of a program or task. When properly 
used, RPLs can prevent problems caused by accidental (or intensional) use of segment selectors for privileged data 
segments by less privileged programs or procedures.
It is important to note that the RPL of a segment selector for a data segment is under software control. For 
example, an application program running at a CPL of 3 can set the RPL for a data- segment selector to 0. With the 
RPL set to 0, only the CPL checks, not the RPL checks, will provide protection against deliberate, direct attempts to 
violate privilege-level security for the data segment. To prevent these types of privilege-level-check violations, a 
program or procedure can check access privileges whenever  it receives a data-segment selector from another 
procedure (see Section 5.10.4, “Checking Ca ller Access Privileges (ARPL Instruction)”).
5.6.1 Accessing Data in Code Segments
In some instances it may be desirable to access data structures that are contained in a code segment. The 
following methods of accessing data in code segments are possible:
•Load a data-segment register with a segment sele ctor for a nonconforming, readable, code segment.
•Load a data-segment register with a segment selector for a conforming, readable, code segment.
•Use a code-segment override prefix (CS) to read a read able, code segment whose sele ctor is already loaded in 
the CS register.
The same rules for accessing data segments apply to meth od 1. Method 2 is always valid because the privilege 
level of a conforming code segment is effectively the same  as the CPL, regardless of its DPL. Method 3 is always 
valid because the DPL of the code segment selected by the CS register is the same as the CPL.Figure 5-5.  Examples of Accessing Data  Segments From Various Privilege LevelsDataLowest Privilege
Highest PrivilegeSegment E3
2
1
0CPL=1CPL=3
CPL=0DPL=2CPL=2Segment Sel. E3
RPL=3
Segment Sel. E1
RPL=2
Segment Sel. E2
RPL=1Code
Segment C
Code
Segment A
Code
Segment B
Code
Segment D5-10 Vol. 3APROTECTION
5.7 PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER
Privilege level checking also occurs when the SS register is loaded with the segment selector for a stack segment. 
Here all privilege levels related to the stack segment must  match the CPL; that is, the CPL, the RPL of the stack-
segment selector, and the DPL of the stack-segment descrip tor must be the same. If the RPL and DPL are not equal 
to the CPL, a general-protection exception (#GP) is generated.
5.8 PRIVILEGE LEVEL CHECKING WHEN  TRANSFERRING PROGRAM CONTROL 
BETWEEN CODE SEGMENTS
To transfer program control from one code segment to another, the segment selector for the destination code

2
1
RPL=3
RPL=2
RPL=1Code
Segment C
Code
Segment A
Code
Segment B
Code
To transfer program control from one code segment to another, the segment selector for the destination code 
segment must be loaded into the code-segment register (C S). As part of this loading process, the processor exam-
ines the segment descriptor for the destination code se gment and performs various limit, type, and privilege 
checks. If these checks are successful, the CS register is  loaded, program control is transferred to the new code 
segment, and program execution begins at the instruction pointed to by the EIP register. 
Program control transfers are carried out with the JMP,  CALL, RET, SYSENTER, SYSEXIT, SYSCALL, SYSRET, INT n, 
and IRET instructions, as well as by the exception and interrupt mechanisms. Exceptions, interrupts, and the IRET 
instruction are special cases discussed in Chapter 6, “Int errupt and Exception Handling.” This chapter discusses 
only the JMP, CALL, RET, SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions.
A JMP or CALL instruction can reference an other code segment in any of four ways:
•The target operand contains the segment selector for the target code segment.
•The target operand points to a call-gate descriptor, wh ich contains the segment selector for the target code 
segment.
•The target operand points to a TSS, which contains the segment selector for the target code segment. 
•The target operand points to a task gate, which points to a TSS, which in turn contains the segment selector for 
the target code segment. 
The following sections describe first two types of referenc es. See Section 8.3, “Task Switching,” for information on 
transferring program control through a task gate and/or TSS.
The SYSENTER and SYSEXIT instructions are special instructio ns for making fast calls to and returns from operating 
system or executive procedures. These instructions are discussed in Section 5.8.7, “Performing Fast Calls to 
System Procedures with the SYSENTER and SYSEXIT Instructions.”
The SYCALL and SYSRET instructions are special instructions for making fast calls to and returns from operating 
system or executive procedures in 64-bit mode. These in structions are discussed in Section 5.8.8, “Fast System 
Calls in 64-Bit Mode.”
5.8.1 Direct Calls or Jumps to Code Segments
The near forms of the JMP, CALL, and RET instructions tr ansfer program control within  the current code segment, 
so privilege-level checks are not performed. The far forms of the JMP, CALL, and RET instructions transfer control 
to other code segments, so the processor does perform privilege-level checks. 
When transferring program control to another code se gment without going through a call gate, the processor 
examines four kinds of privilege level and type information (see Figure 5-6):
•The CPL. (Here, the CPL is the privilege level of the calling code segment; that is, the code segment that 
contains the procedure that is making the call or jump.)Vol. 3A 5-11PROTECTION
•The DPL of the segment descriptor for the destination code segment that contains the called procedure. 
•The RPL of the segment selector of the destination code segment.
•The conforming (C) flag in the segment descriptor for th e destination code segment, which determines whether 
the segment is a conforming (C flag is set) or noncon forming (C flag is clear) code segment. See Section 
3.4.5.1, “Code- and Data-Segment Descriptor Ty pes,” for more information about this flag.
The rules that the processor uses to check the CPL, RPL, and DPL depends on the setting of the C flag, as described 
in the following sections.
5.8.1.1  Accessing Nonc onforming Code Segments
When accessing nonconforming code segments, the CPL of the calling procedure must be equal to the DPL of the 
destination code segment; otherwise, the processor gene rates a general-protection exception (#GP). For example 
in Figure 5-7:
•Code segment C is a nonconforming code segment. A proc edure in code segment A can call a procedure in code 
segment C (using segment selector C1) because they are at  the same privilege level (CPL of code segment A is 
equal to the DPL of code segment C). 
•A procedure in code segment B cannot call a procedure in code segment C (using segment selector C2 or C1) 
because the two code segments are at different privilege levels.Figure 5-6.  Privilege Check for Co ntrol Transfer Without Using a GateCPL
RPL
CheckCS Register
For Code Segment
Destination Code
Segment Descriptor
C5-12 Vol. 3APROTECTION
The RPL of the segment selector that points to a nonconforming code segment has a limited effect on the privilege 
check. The RPL must be numerically less than or equal to  the CPL of the calling procedure for a successful control 
transfer to occur. So, in the example in Figure 5-7, the RPLs of segment selectors C1 and C2 could legally be set to 
0, 1, or 2, but not to 3.
When the segment selector of a nonconforming code segment is loaded into the CS register, the privilege level field 
is not changed; that is, it remains at the CPL (which is the privilege level of the calling procedure). This is true, even 
if the RPL of the segment selector is different from the CPL.
5.8.1.2  Accessing Conf orming Code Segments
When accessing conforming code segm ents, the CPL of the calling procedure may be numerically equal to or 
greater than (less privileged) the DPL of the destination code segment; the processor generates a general-protec-
tion exception (#GP) only if the CPL is less than the DPL. (The segment selector RPL for the destination code 
segment is not checked if the segment is a conforming code segment.)
In the example in Figure 5-7, code segment D is a conformi ng code segment. Therefore, calling procedures in both 
code segment A and B can access code segment D (using eith er segment selector D1 or D2, respectively), because 
they both have CPLs that are greater than or equal to the DPL of the conforming code segment.  For conforming 
code segments, the DPL represents the numerically lowest privilege level that a calling procedure may 
be at to successfully make a call to the code segment.
(Note that segments selectors D1 and D2 are identical except for their respective RPLs. But since RPLs are not 
checked when accessing conforming code segments, the two segment selectors are essentially interchangeable.)
When program control is transferred to a conforming code segment, the CPL does not change, even if the DPL of 
the destination code segment is less than the CPL. This situation is the only one wh ere the CPL may be different 
from the DPL of the current code segment. Also, since the CPL does not change, no stack switch occurs.
Conforming segments are used for code modules such as  math libraries and exception handlers, which support 
applications but do not require access to protected syst em facilities. These modules are part of the operating 
system or executive software, but they can be executed at numerically higher privilege levels (less privileged 
levels). Keeping the CPL at the level of a calling code  segment when switching to a conforming code segment Figure 5-7.  Examples of Accessing Conforming and No nconforming Code Segments From Various Privilege LevelsCode
Segment DCode
Segment C Code
Segment ALowest Privilege
Highest PrivilegeCPL=3Code
Segment B
Nonconforming
Code Segment
Code Segment3
2
1
0CPL=2DPL=2
DPL=1Segment Sel. D1
RPL=2Segment Sel. D2
RPL=3
Segment Sel. C2
RPL=3
Segment Sel. C1
RPL=2Vol. 3A 5-13PROTECTION
prevents an application program from accessing nonconform ing code segments while at the privilege level (DPL) of 
a conforming code segment and thus prevents it from accessing more privileged data.
Most code segments are nonconforming. For these segmen ts, program control can be transferred only to code 
segments at the same level of privilege, unless the transfer  is carried out through a call gate, as described in the 
5.8.2 Gate Descriptors
To provide controlled access to code segments with different  privilege levels, the processor provides special set of 
descriptors called gate descriptors. There are four kinds of gate descriptors:
•Call gates
Task gates are used for task switching and are discussed in Chapter 8, “Task Management.” Trap and interrupt 
gates are special kinds of call gates used for calling exception and interrupt handlers. The are described in Chapter 6, “Interrupt and Exception Handling.” This chapter is concerned only with call gates. 
5.8.3 Call Gates
Call gates facilitate controlled transfers of program cont rol between different privilege levels. They are typically 
used only in operating systems or executives that use the privilege-level protection mechanism. Call gates are also 
useful for transferring program control between 16-bit and 32-bit code segments, as described in Section 22.4, 
“Transferring Control Among Mixed-Size Code Segments.”
Figure 5-8 shows the format of a call-gate descriptor. A call- gate descriptor may reside in the GDT or in an LDT, but 
not in the interrupt descriptor table (IDT). It performs six functions:
•It specifies the code segment to be accessed.

•It defines an entry point for a proc edure in the specified code segment.
•It specifies the privilege level required for a caller trying to access the procedure.
•If a stack switch occurs, it specifies the number of optional parameters to be copied between stacks.
•It defines the size of values to be pushed onto the ta rget stack: 16-bit gates force 16-bit pushes and 32-bit 
gates force 32-bit pushes.
•It specifies whether the call-gate descriptor is valid. 
The segment selector field in a call gate specifies the code  segment to be accessed. Th e offset field specifies the 
entry point in the code segment. This en try point is generally to the first instruction of a specific procedure. The DPL 
field indicates the privilege level of the call gate, which in turn is the privilege level required to access the selected Figure 5-8.  Call-Gate Descriptor31 1615 1314 12 11 87 0
P Offset in Segment 31:16D
P
LType
04
31 1615 0
Segment Selector Offset in Segment 15:00 0Param.
0011
PDPL
Gate ValidDescriptor Privilege LevelCount45 6
0   0   05-14 Vol. 3APROTECTION
procedure through the gate. The P flag indicates whether the call-gate descriptor is valid. (The presence of the code 
segment to which the gate points is indicated by the P fl ag in the code segment’s de scriptor.) The parameter count 
field indicates the number of parameters to copy from th e calling procedures stack to the new stack if a stack 
switch occurs (see Section 5.8.5, “Stack Switching”). The parameter count specifies the number of words for 16-
bit call gates and doublewords for 32-bit call gates.
Note that the P flag in a gate descriptor is normally always set to 1. If it is set to 0, a not present (#NP) exception 
is generated when a program attempts to access the descrip tor. The operating system can use the P flag for special 
purposes. For example, it could be used to track the number of times the gate is used. Here, the P flag is initially 
set to 0 causing a trap to the not-present exception hand ler. The exception handler then increments a counter and 
sets the P flag to 1, so that on returning from the handler, the gate descriptor will be valid.
5.8.3.1  IA-32e Mode Call Gates
Call-gate descriptors in 32-bit mode provide a 32-bit offset for the instruction pointer (EIP); 64-bit extensions 
double the size of 32-bit mode call gates in order to  store 64-bit instruction pointers (RIP). See Figure 5-9:
•The first eight bytes (bytes 7:0) of a 64-bit mode call ga te are similar but not identical to legacy 32-bit mode 
call gates. The parameter-copy-count field has been removed. 
•Bytes 11:8 hold the upper 32 bits of the target-segme nt offset in canonical form. A general-protection 
exception (#GP) is generated if software attempts to use a call gate with a target offset that is not in canonical 
form.
•16-byte descriptors may reside in the same descriptor table with 16-bit and 32-bit descriptors. A type field, 
used for consistency checking, is define d in bits 12:8 of the 64-bit descriptor’s highest dword (cleared to zero). 
A general-protection exception (#GP) results if an atte mpt is made to access the upper half of a 64-bit mode 
descriptor as a 32-bit mode descriptor.
•Target code segments referenced by a 64-bit call gate must be 64-bit code segments (CS.L = 1, CS.D = 0). If not, the reference generates a general-protection exception, #GP (CS selector). 
•Only 64-bit mode call gates can be referenced in IA -32e mode (64-bit mode and compatibility mode). The 
legacy 32-bit mode call gate type (0CH) is redefined in  IA-32e mode as a 64-bit call-gate type; no 32-bit call-
gate type exists in IA-32e mode. Figure 5-9.  Call-Gate Descriptor in IA-32e Mode31 87 0
P
LType
04
31 1615 0
Segment Selector Offset in Segment 15:00 0.
0011
PDPL
Gate ValidDescriptor Privilege Level31 0
012
31 0
Offset in Segment 63:31 80000
013 12 11 10 9 8 7
16 15 14 13 12 11Reserved ReservedTypeVol. 3A 5-15PROTECTION
•If a far call references a 16-bit call gate type (04H) in IA-32e mode, a general-protection exception (#GP) is 
When a call references a 64-bit mode call gate, actions ta ken are identical to those taken in 32-bit mode, with the 
following exceptions:
•Stack pushes are made in eight-byte increments.
•A 64-bit RIP is pushed onto the stack.
•Parameter copying is not performed.
Use a matching far-return instruction size for correct operation (returns from 64-bit calls must be performed with 
a 64-bit operand-size return to process the stack correctly).
5.8.4 Accessing a Code Segment Through a Call Gate
To access a call gate, a far pointer to the gate is provided as a target operand in a CALL or JMP instruction. The segment selector from this pointer identifies the call gate (see Figure 5-10); the offset from the pointer is required, 
but not used or checked by the processor.  (The offset can be set to any value.) 
When the processor has accessed the call gate, it uses the segment selector from the call gate to locate the 
segment descriptor for the destination code segment. (Thi s segment descriptor can be in the GDT or the LDT.) It 
then combines the base address from the code-segment descr iptor with the offset from the call gate to form the 
linear address of the procedure entry point in the code segment.
As shown in Figure 5-11, four different privilege levels ar e used to check the validity of a program control transfer 
through a call gate:
•The CPL (current privilege level).
•The RPL (requestor privilege level) of the call gate’s selector.
•The DPL (descriptor privilege level) of the call gate descriptor.
•The DPL of the segment descriptor of the destination code segment.
The C flag (conforming) in the segment descriptor for the destination code segment is also checked.
Figure 5-10.  Call-Gate MechanismOffset Segment SelectorFar Pointer to Call Gate
Required but not used by processor
Call-Gate
DescriptorDescriptor Table
Offset
Base
BaseOffset
BaseSegment Selector
+
Procedure
Entry Point5-16 Vol. 3APROTECTION
The privilege checking rules are different depending on whet her the control transfer was initiated with a CALL or a 
JMP instruction, as shown in Table 5-1.
The DPL field of the call-gate descripto r specifies the numerically highest privilege level from which a calling proce-
dure can access the call gate; that is, to access a call gate, the CPL of a calling procedure must be equal to or less 
than the DPL of the call gate. For example, in Figure 5-15, call gate A has a DPL of 3. So calling procedures at all 
CPLs (0 through 3) can access this call gate, which includes  calling procedures in code segments A, B, and C. Call 
gate B has a DPL of 2, so only calling procedures at a CPL or 0, 1, or 2 can access call gate B, which includes calling 
procedures in code segments B and C.  The dotted line shows that a calling procedure in code segment A cannot 
access call gate B.
The RPL of the segment selector to a call gate must satisfy the same test as the CPL of the calling procedure; that 
is, the RPL must be less than or equal to the DPL of the ca ll gate. In the example in Figure 5-15, a calling procedure 
in code segment C can access call gate B using gate selector  B2 or B1, but it could not use gate selector B3 to 
If the privilege checks between the calling procedure an d call gate are successful, the processor then checks the 
DPL of the code-segment descriptor against the CPL of th e calling procedure. Here, the privilege check rules vary 
between CALL and JMP instructions. Only  CALL instructions can use call gates to transfer program control to more 
privileged (numerically lower privilege level) nonconfo rming code segments; that is, to nonconforming code 
segments with a DPL less than the CPL. A JMP instruction can use a call gate only to transfer program control to a 
nonconforming code segment with a DPL equal to the CPL.  CALL and JMP instruction can both transfer program 
control to a more privileged conforming  code segment; that is, to a conforming code segment with a DPL less than 
or equal to the CPL.Figure 5-11.  Privilege Check for Control Transfer with Call Gate
Table 5-1.  Privilege Check Rules for Call Gates
Instruction Privilege Check Rules
CALL CPL ≤ call gate DPL; RPL ≤ call gate DPL
Destination conforming code segment DPL ≤ CPL
Destination nonconforming code segment DPL ≤ CPL
JMP CPL ≤ call gate DPL; RPL ≤ call gate DPL
Destination nonconforming code segment DPL = CPLCPL
RPL
DPL
CheckCall Gate (Descriptor)
Destination Code-CS Register
Call-Gate Selector
Segment DescriptorVol. 3A 5-17PROTECTION
If a call is made to a more privileged (numerically lowe r privilege level) nonconforming destination code segment, 
the CPL is lowered to the DPL of the destination code segm ent and a stack switch occurs (see Section 5.8.5, “Stack

RPL
DPL
the CPL is lowered to the DPL of the destination code segm ent and a stack switch occurs (see Section 5.8.5, “Stack 
Switching”). If a call or jump is made to a more privil eged conforming destination code segment, the CPL is not 
changed and no stack switch occurs. 
Call gates allow a single code segment to have procedures that can be accessed at different privilege levels. For 
example, an operating system located in a code segment may have some services which are intended to be used 
by both the operating system and app lication software (such as procedures for handling character I/O). Call gates 
for these procedures can be set up that allow access at all privilege levels (0 through 3). More privileged call gates 
(with DPLs of 0 or 1) can then be set up for other operating system services that are intended to be used only by 
the operating system (such as procedures that initialize device drivers).
5.8.5 Stack Switching
Whenever a call gate is used to transfer program contro l to a more privileged nonconforming code segment (that 
is, when the DPL of the nonconforming destination code segment is less than the CPL), the processor automatically 
switches to the stack for the destination code segment’s privilege level. This stack switching is carried out to 
prevent more privileged procedures from crashing due to in sufficient stack space. It also prevents less privileged 
procedures from interfering (by accident or intent) wi th more privileged procedures through a shared stack.
Each task must define up to 4 stacks: one for applications  code (running at privilege level 3) and one for each of 
the privilege levels 2, 1, and 0 that are used. (If only two privilege levels are used [3 and 0], then only two stacks 
must be defined.) Each of these stacks is located in a separate segment and is identified with a segment selector 
and an offset into the stack segment (a stack pointer).
The segment selector and stack pointer for the privilege leve l 3 stack is located in the SS and ESP registers, respec-
tively, when privilege-level-3 code is being executed an d is automatically stored on the called procedure’s stack 
when a stack switch occurs. 
Pointers to the privilege level 0, 1, and 2 stacks are stored in the TSS for the currently running task (see 
Figure 8-2). Each of these pointers consists of a segm ent selector and a stack pointer (loaded into the ESP 
register). These initial pointers are strictly read-only valu es. The processor does not change them while the task is 
running. They are used only to create new stacks when ca lls are made to more privileged levels (numerically lower Figure 5-12.  Example of Accessing Call Gates At Various Privilege LevelsCode
Segment A
Stack Switch No Stack
Switch Occurs OccursLowest Privilege
Highest Privilege3
2
1
0Call
Gate A
Code
Segment BCall
Gate B
Code
Segment C
Code
Segment E
Code SegmentConforming
Code SegmentGate Selector A
RPL=3
Gate Selector B1
RPL=2
Gate Selector B2
RPL=1CPL=3
CPL=2
CPL=1DPL=3
DPL=2
DPL=0 DPL=0Gate Selector B3
RPL=35-18 Vol. 3APROTECTION
privilege levels). These stacks are disposed of when a retu rn is made from the called procedure. The next time the 
procedure is called, a new stack is created using the initial stack pointer. (The TSS does not specify a stack for priv-
ilege level 3 because the processor does not allow a transf er of program control from a procedure running at a CPL 
of 0, 1, or 2 to a procedure running at a CPL of 3, except on a return.)
The operating system is responsible for creating stacks and stack-segment descriptors for all the privilege levels to 
be used and for loading initial pointers for these stacks in to the TSS. Each stack must be read/write accessible (as 
specified in the type field of its segment descriptor) and mu st contain enough space (as specified in the limit field) 
to hold the following items:
•The contents of the SS, ESP, CS, and EIP registers for the calling procedure.
•The parameters and temporary variable s required by the called procedure.
•The EFLAGS register and error code, when implicit calls are made to an exception or interrupt handler.
The stack will need to require enough space to contain ma ny frames of these items, because procedures often call 
other procedures, and an operating system may support nest ing of multiple interrupts. Each stack should be large 
enough to allow for the worst case nesting scenario at its privilege level.
(If the operating system does not use the processor’s multitasking mechanism, it still must create at least one TSS 
for this stack-related purpose.) 
When a procedure call through a call gate results in a change  in privilege level, the processor performs the following 
steps to switch stacks and begin execution of the called procedure at a new privilege level:
1. Uses the DPL of the destination code segment (the ne w CPL) to select a pointer to the new stack (segment
selector and stack pointer) from the TSS. 
2. Reads the segment selector and stack pointer for the stac k to be switched to from the current TSS. Any limit 
violations detected while reading the stack-segment sele ctor, stack pointer, or stack-segment descriptor cause 
an invalid TSS (#TS) exception to be generated.
3. Checks the stack-segment descriptor for the proper pr ivileges and type and generates an invalid TSS (#TS) 
exception if violations are detected.
4. Temporarily saves the current values of the SS and ESP registers.5. Loads the segment selector and stack pointer for the new stack in the SS and ESP registers.
6. Pushes the temporarily saved values for the SS and ESP registers (for the calling procedure) onto the new stack 
(see Figure 5-13).
7. Copies the number of parameter specified in the para meter count field of the call gate from the calling 
procedure’s stack to the new stack. If the count is 0, no parameters are copied.
8. Pushes the return instruction pointer (the current contents of the CS and EIP registers) onto the new stack.
9. Loads the segment selector for the new code segment and the new instruction pointer from the call gate into 
the CS and EIP registers, respectively, and begins execution of the called procedure.
See the description of the CALL instruction in Chapter 3, “Instruction Set Reference, A-L‚”, in the Intel
® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 2A, for a detailed description of the privilege level 
checks and other protection checks that the processor performs on a far call through a call gate.Vol. 3A 5-19PROTECTION
The parameter count field in a call gate specifies the num ber of data items (up to 31) that the processor should 
copy from the calling procedure’s stack to the stack of the ca lled procedure. If more than 31 data items need to be 
passed to the called procedure, one of the parameters can be  a pointer to a data structure, or the saved contents 
of the SS and ESP registers may be used to access paramete rs in the old stack space. The size of the data items 
passed to the called procedure depends on the call gate  size, as described in Se ction 5.8.3, “Call Gates.”
5.8.5.1  Stack Switching in 64-bit Mode
Although protection-check rules for call gates are unchanged from 32-bit mode, stack-switch changes in 64-bit 
mode are different.
When stacks are switched as part of a 64-bit mode priv ilege-level change through a call gate, a new SS (stack 
segment) descriptor is not loaded; 64-bit mode only loads an inner-level RSP from the TSS. The new SS is forced 
to NULL and the SS selector’s RPL fiel d is forced to the new CPL. The new SS  is set to NULL in order to handle 
nested far transfers (far CALL, INTn, interrupts, and exce ptions). The old SS and RSP are saved on the new stack. 
On a subsequent far RET, the old SS is popped from th e stack and loaded into the SS register. See Table 5-2.
In 64-bit mode, stack operations resulting from a privilege -level-changing far call or far return are eight-bytes wide 
and change the RSP by eight. The mode does not suppor t the automatic parameter-copy feature found in 32-bit 
mode. The call-gate count field is ignored. Software can access the old stack, if necessary, by referencing the old 
stack-segment selector and stack poin ter saved on the new process stack. 
In 64-bit mode, far RET is allowed to load a NULL SS under certain conditions. If the target mode is 64-bit mode 
and the target CPL ≠ 3, IRET allows SS to be loaded with a NULL selector. If the called procedure itself is inter-
rupted, the NULL SS is pushed on the stack frame. On the subsequent far RET, the NULL SS on the stack acts as a 
flag to tell the processor not to load a new SS descriptor.Figure 5-13.  Stack Switching Duri ng an Interprivilege-Level Call
Table 5-2.  64-Bit-Mode Stack Layout After Far CALL with CPL Change
32-bit Mode IA-32e mode
Old SS Selector +12 +24 Old SS Selector
Old ESP +8 +16 Old RSPCS Selector +4 +8 Old CS Selector
EIP 0 ESP  RSP 0R I P
< 4 Bytes  > < 8 Bytes >Parameter 1
Parameter 2Parameter 3Calling SS
Calling ESP
Parameter 1Parameter 2Parameter 3
Calling CS
Calling EIPCalled Procedure’s Stack
ESP

Calling CS
ESP
ESPCalling Procedure’s Stack5-20 Vol. 3APROTECTION
5.8.6 Returning from a Called Procedure
The RET instruction can be used to perform a near return, a far return at the same privilege level, and a far return 
to a different privilege level. This instruction is intended  to execute returns from procedures that were called with 
a CALL instruction. It does not support returns from a JMP instruction, because the JMP instruction does not save a 
return instruction pointer on the stack.
A near return only transfers program control within the current code segment; therefore, the processor performs 
only a limit check. When the processor pops the return instruction pointer from the stack into the EIP register, it 
checks that the pointer does not exceed the limit of the current code segment.
On a far return at the same privilege level, the processo r pops both a segment selector for the code segment being 
returned to and a return instruction pointer from the st ack. Under normal conditions, these pointers should be 
valid, because they were pushed on the stack by the CALL instruction. However, the processor performs privilege checks to detect situations where the current procedure might have altered the pointer or failed to maintain the 
stack properly.
A far return that requires a privilege-le vel change is only allowed when return ing to a less privileged level (that is, 
the DPL of the return code segment is numerically greater than the CPL). The processor uses the RPL field from the 
CS register value saved for the calling procedure (see Figure 5-13) to determine if a return to a numerically higher 
privilege level is required. If the RPL is numerically greate r (less privileged) than the CPL, a return across privilege 
levels occurs. 
The processor performs the following steps when performing  a far return to a calling procedure (see Figures 6-2 
and 6-4 in the Intel
® 64 and IA-32 Architectures Soft ware Developer’s Manual, Volume 1, for an illustration of the 
stack contents prior to and after a return):
1. Checks the RPL field of the saved CS register value to determine if a privilege level change is required on the
return.
2. Loads the CS and EIP registers with the values on the ca lled procedure’s stack. (Type and privilege level checks 
are performed on the code-segment descriptor and RPL of the code- segment selector.)
3. (If the RET instruction includes a parameter count oper and and the return requires a privilege level change.) 
Adds the parameter count (in bytes obtained from the RET instruction) to the current ESP register value (after 
popping the CS and EIP values), to step past the parameters on the called procedure’s stack. The resulting 
value in the ESP register points to the saved SS and ES P values for the calling procedure’s stack. (Note that the 
byte count in the RET instruction must be chosen to matc h the parameter count in the call gate that the calling 
procedure referenced when it made the original call multiplied by the size of the parameters.)
4. (If the return requires a privilege level change.) Lo ads the SS and ESP registers with the saved SS and ESP 
values and switches back to the calling procedure’s stac k. The SS and ESP values for the called procedure’s 
stack are discarded. Any limit violations detected while  loading the stack-segment selector or stack pointer 
cause a general-protection exception (#GP) to be genera ted. The new stack-segment descriptor is also checked 
for type and privilege violations.
5. (If the RET instruction includes a parameter count oper and.) Adds the parameter count  (in bytes obtained from 
the RET instruction) to the current ESP register value, to step past the parameters on the calling procedure’s 
stack. The resulting ESP value is not checked against the limit of the stack segment. If the ESP value is beyond 
the limit, that fact is not recognized until the next stack operation.
6. (If the return requires a privilege level change.) Ch ecks the contents of the DS, ES, FS, and GS segment 
registers. If any of these registers refer to segments whose DPL is less than the new CPL (excluding conforming 
code segments), the segment register is loaded with a null segment selector.
See the description of the RET instruction in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 2B, for a detailed description of the privilege level checks and other protection checks that 
the processor performs on a far return.
5.8.7 Performing Fast Calls to System Pr ocedures with the SY SENTER and SYSEXIT 
The SYSENTER and SYSEXIT instructions were introduced in to the IA-32 architecture in the Pentium II processors 
for the purpose of providing a fast (low overhead) mechan ism for calling operating system or executive procedures. Vol. 3A 5-21PROTECTION
SYSENTER is intended for use by user code running at privilege level 3 to access operating system or executive 
procedures running at privilege level 0. SYSEXIT is intend ed for use by privilege level 0 operating system or exec-
utive procedures for fast returns to privilege level 3 user code. SYSENTER can be executed from privilege levels 3, 
2, 1, or 0; SYSEXIT can only be executed from privilege level 0.
This is because SYSENTER does not save any state information for use by SYSEXIT on a return.
The target instruction and stack pointer for these instructions are not specified through instruction operands. 
Instead, they are specified through parameters entered in MSRs and general-purpose registers. 
For SYSENTER, target fields are generated using the following sources:
•Target code segment  — Reads this from IA32_SYSENTER_CS.
•Target instruction  — Reads this from IA32_SYSENTER_EIP.
•Stack segment  — Computed by adding 8 to the value in IA32_SYSENTER_CS.
•Stack pointer  — Reads this from the IA32_SYSENTER_ESP.
For SYSEXIT, target fields are generated using the following sources:
•Target code segment — Computed by adding 16 to the value in the IA32_SYSENTER_CS.
•Target instruction  — Reads this from EDX.
•Stack segment — Computed by adding 24 to the value in IA32_SYSENTER_CS.
•Stack pointer  — Reads this from ECX.
The SYSENTER and SYSEXIT instructions perform “fast” ca lls and returns because they force the processor into a 
predefined privilege level 0 state when SYSENTER is exec uted and into a predefined privilege level 3 state when 
SYSEXIT is executed. By forcing predefined and consistent  processor states, the number of privilege checks ordi-
narily required to perform a far call to another privilege levels are greatly reduced. Also, by predefining the target 
context state in MSRs and general-purpose registers elim inates all memory accesses except when fetching the 
target code.
Any additional state that needs to be saved to allow a retu rn to the calling procedure must be saved explicitly by 
the calling procedure or be predefin ed through programming conventions.
5.8.7.1  SYSENTER and SYSEXIT Instructions in IA-32e Mode
For Intel 64 processors, the SYSENTER and SYSEXIT instructions are enhanced to allow fast system calls from user 
code running at privilege level 3 (in compatibility mode or 64-bit mode) to 64-bit executive procedures running at 
privilege level 0. IA32_SYSENTER_EIP MSR and IA32_SYSENTER_ESP MSR are expanded to hold 64-bit addresses. 
If IA-32e mode is inactive, only the lower 32-bit addre sses stored in these MSRs are used. The WRMSR instruction 
ensures that the addresses stored in  these MSRs are canonical. Note that, in 64-bit mode, IA32_SYSENTER_CS 
must not contain a NULL selector. 
When SYSENTER transfers control, the foll owing fields are generated and bits set:
•Target code segment — Reads non-NULL selector from IA32_SYSENTER_CS.
•New CS attributes  — CS base = 0, CS limit = FFFFFFFFH.
•Target instruction  — Reads 64-bit canonical address from IA32_SYSENTER_EIP.
•Stack segment  — Computed by adding 8 to the value from IA32_SYSENTER_CS.
•Stack pointer  — Reads 64-bit canonical address from IA32_SYSENTER_ESP.
•New SS attributes  — SS base = 0, SS limit = FFFFFFFFH.
When the SYSEXIT instruction transfers control to 64-bit mode user code using REX.W, the following fields are 
generated and bits set:
•Target code segment  — Computed by adding 32 to the value in IA32_SYSENTER_CS.
•New CS attributes  — L-bit = 1 (go to 64-bit mode).
•Target instruction  — Reads 64-bit canonical address in RDX.
•Stack segment  — Computed by adding 40 to the value of IA32_SYSENTER_CS.5-22 Vol. 3APROTECTION
•Stack pointer  — Update RSP using 64-bit canonical address in RCX.
When SYSEXIT transfers control to compatibility mode user  code when the operand size attribute is 32 bits, the 
following fields are generated and bits set:
•Target code segment  — Computed by adding 16 to the value in IA32_SYSENTER_CS.
•New CS attributes  — L-bit = 0 (go to compatibility mode).

•Target instruction  — Fetch the target instruction from 32-bit address in EDX.
•Stack pointer  — Update ESP from 32-bit address in ECX.
5.8.8 Fast System Calls in 64-Bit Mode
The SYSCALL and SYSRET instructions are designed for op erating systems that use a flat memory model (segmen-
tation is not used). The instructions, along with SYSENT ER and SYSEXIT, are suited for IA-32e mode operation. 
SYSCALL and SYSRET, however, are not supported in comp atibility mode (or in protected mode). Use CPUID to 
check if SYSCALL and SYSRET are avai lable (CPUID.80000001H.EDX[bit 11] = 1). 
SYSCALL is intended for use by user code running at privilege level 3 to access operating system or executive 
procedures running at privilege level 0. SYSRET is intend ed for use by privilege level 0 operating system or execu-
tive procedures for fast returns to privilege level 3 user code. 
Stack pointers for SYSCALL/SYSRET are not specified throug h model specific registers. The clearing of bits in 
RFLAGS is programmable rather than fixed. SYSCAL L/SYSRET save and restore the RFLAGS register. 
For SYSCALL, the processor saves RFLAGS into R11 and the RI P of the next instruction into RCX; it then gets the 
privilege-level 0 target code segment, instructio n pointer, stack segment, and flags as follows:
•Target code segment  — Reads a non-NULL selector from IA32_STAR[47:32].
•Target instruction pointer — Reads a 64-bit address from IA32_LSTAR. (The WRMSR instruction ensures 
that the value of the IA32_LSTAR MSR is canonical.)
•Stack segment — Computed by adding 8 to the value in IA32_STAR[47:32].
•Flags — The processor sets RFLAGS to the logical-AND of it s current value with the complement of the value in 
the IA32_FMASK MSR.
When SYSRET transfers control to 64-bit mode user code  using REX.W, the processor gets the privilege level 3 
target code segment, instruction pointe r, stack segment, and flags as follows:
•Target code segment — Reads a non-NULL selector from IA32_STAR[63:48] + 16.
•Target instruction pointer  — Copies the value in RCX into RIP.
•Stack segment  — IA32_STAR[63:48] + 8.
•EFLAGS  — Loaded from R11.
When SYSRET transfers control to 32-bit mode user code using a 32-bit operand size, the processor gets the priv-
ilege level 3 target code segment, instruction pointer, stack segment, and flags as follows:
•Target code segment — Reads a non-NULL selector from IA32_STAR[63:48].
•Target instruction pointer  — Copies the value in ECX into EIP.
It is the responsibility of the OS to ensure the descripto rs in the GDT/LDT correspond to the selectors loaded by 
SYSCALL/SYSRET (consistent with the base, limit, an d attribute values forced by the instructions). 
See Figure 5-14 for the layout of IA32_STAR, IA32_LSTAR, and IA32_FMASK.Vol. 3A 5-23PROTECTION
The SYSCALL instruction does not save the stack pointer, and the SYSRET instruction does not restore it. It is likely 
that the OS system-call handler will change the stack pointer from the user stack to the OS stack. If so, it is the 
responsibility of software first to save the user stack poin ter. This might be done by user code, prior to executing 
SYSCALL, or by the OS system-call handler after SYSCALL.
Because the SYSRET instruction does not modify the stack poin ter, it is necessary for software to switch back to the 
user stack. The OS may load the user stack pointer (if it  was saved after SYSCALL) before executing SYSRET; alter-
natively, user code may load the stack pointer (if it was saved before SYSCALL) after receiving control from 
SYSRET.
If the OS loads the stack pointer before executing SYSRET , it must ensure that the handler of any interrupt or 
exception delivered between restoring th e stack pointer and successful execution of SYSRET is not invoked with the 
•External interrupts. The OS can prev ent an external interrupt from being delivered by clearing EFLAGS.IF 
Stack Table”).
•General-protection exceptions (#GP). The SYSRET instruction generates #GP(0) if the value of RCX is not canonical. The OS can address this possibility using one or more of the following approaches:
— Confirming that the value of RCX is canonical before executing SYSRET.— Using paging to ensure that the SYSCALL instruction will never save a non-canonical value into RCX.
5.9 PRIVILEGED INSTRUCTIONS
Some of the system instructions (called “privileged instru ctions”) are protected from use by application programs. 
The privileged instructions control system functions (such as the loading of system registers). They can be 
executed only when the CPL is 0 (most privileged). If one of these instructions is executed when the CPL is not 0, 
a general-protection exception (#GP) is generated. The fo llowing system instructions are privileged instructions:
•LGDT — Load GDT register.
•LLDT — Load LDT register.Figure 5-14.  MSRs Used  by SYSCALL and SYSRET63 3231 063 0
63 0
Target RIP for 64-bit Mode Calling Program
SYSRET CS and SS SYSCALL CS and SS4847
IA32_STARIA32_LSTARIA32_FMASK3231
SYSCALL EFLAGS Mask Reserved
Reserved5-24 Vol. 3APROTECTION
•LTR — Load task register.
•LIDT — Load IDT register.
•MOV (control registers) — Load and store control registers.
•LMSW — Load machine status word.
•CLTS — Clear task-switched flag in register CR0.
•MOV (debug registers) — Load and store debug registers.
•INVD — Invalidate cache, without writeback.
•WBINVD — Invalidate cache, with writeback.
•INVLPG —Invalidate TLB entry.
•HLT— Halt processor.
•RDMSR — Read Model-Specific Registers.
•WRMSR —Write Model-Specific Registers.
•RDPMC — Read Performance-Monitoring Counter.
•RDTSC — Read Time-Stamp Counter.
Some of the privileged instructions are available only in  the more recent families of Intel 64 and IA-32 processors 
(see Section 23.13, “New Instructions In the Pentium and Later IA-32 Processors”).
The PCE and TSD flags in register CR4 (bits 4 and 2, respectively) enable the RDPMC and RDTSC instructions, 
respectively, to be executed at any CPL.
5.10 POINTER VALIDATION
When operating in protected mode, the processor validate s all pointers to enforce protection between segments 
and maintain isolation between privilege levels. Poin ter validation consists of the following checks:
1. Checking access rights to determine if th e segment type is compatible with its use.
2. Checking read/write rights.
3. Checking if the pointer offset exceeds the segment limit.4. Checking if the supplier of the pointer is allowed to access the segment.
5. Checking the offset alignment.
The processor automatically performs first, second, and th ird checks during instruction execution. Software must 
explicitly request the fourth check by issuing an ARPL in struction. The fifth check (offset alignment) is performed 
automatically at privilege level 3 if alignment checking is turned on. Offset alignment does not affect isolation of 
privilege levels.
5.10.1 Checking Access Rights (LAR Instruction)
When the processor accesses a segment using a far pointer,  it performs an access rights check on the segment 
descriptor pointed to by the far pointer. This check is perf ormed to determine if type and privilege level (DPL) of the 
segment descriptor are compatible with the operation to be performed. For example, when making a far call in 
protected mode, the segment-descriptor type must be fo r a conforming or nonconforming code segment, a call 
gate, a task gate, or a TSS. Then, if the call is to a nonconforming code segment, the DPL of the code segment must 
be equal to the CPL, and the RPL of th e code segment’s segment selector must be less than or equal to the DPL. If 
type or privilege level are found to be incomp atible, the appropriate exception is generated.
To prevent type incompatibility exceptions from being generated, software can check the access rights of a 
segment descriptor using the LAR (load access rights) in struction. The LAR instruction specifies the segment 
selector for the segment descriptor whose access rights ar e to be checked and a destination register. The instruc-
tion then performs the following operations:
1. Check that the segment selector is not null.Vol. 3A 5-25PROTECTION
2. Checks that the segment selector points to a segment de scriptor that is within the descriptor table limit (GDT 
or LDT).
3. Checks that the segment descriptor is a code, data, LD T, call gate, task gate, or TSS segment-descriptor type.

or LDT).
4. If the segment is not a conforming code segment, chec ks if the segment descriptor is visible at the CPL (that 
is, if the CPL and the RPL of the segment se lector are less than or equal to the DPL).
5. If the privilege level and type checks pass, loads th e second doubleword of the segment descriptor into the 
destination register (masked by the value 00FXFF00H, where X indicates that the corresponding 4 bits are 
undefined) and sets the ZF flag in the EFLAGS register. If the segment selector is not visible at the current 
privilege level or is an invalid type for the LAR instru ction, the instruction does not modify the destination 
register and clears the ZF flag.
Once loaded in the destination register, software can perform additional checks on the access rights information.
5.10.2 Checking Read/Write Rights (VERR and VERW Instructions)
When the processor accesses any code or data segment it checks the read/write privileges assigned to the 
segment to verify that the intended re ad or write operation is allowed. Soft ware can check read/write rights using 
the VERR (verify for reading) and VERW (verify for writ ing) instructions. Both these instructions specify the 
segment selector for the segment being checked. The instructions then perform the following operations:
1. Check that the segment selector is not null.
or LDT).
3. Checks that the segment descriptor is a code or data-segment descriptor type.4. If the segment is not a conforming code segment, chec ks if the segment descriptor is visible at the CPL (that 
5. Checks that the segment is readab le (for the VERR instruction) or writable (for the VERW) instruction.
The VERR instruction sets the ZF flag in the EFLAGS regist er if the segment is visible at the CPL and readable; the 
VERW sets the ZF flag if the segment is visible and writ able. (Code segments are never writable.) The ZF flag is 
cleared if any of these checks fail.
5.10.3 Checking That the Pointer Offset  Is Within Limits (LSL Instruction)
When the processor accesses any segment it performs a limit check to ensure that the offset is within the limit of 
the segment. Software can perform this limit check using the LSL (load segment limit) instruction. Like the LAR 
instruction, the LSL instruction specifies the segment selector for the segment descriptor whose limit is to be 
checked and a destination register. The instruct ion then performs the following operations:
or LDT).
3. Checks that the segment descriptor is a code, data, LDT, or TSS segment-descriptor type.
is, if the CPL and the RPL of the segment selector less than or equal to the DPL).
5. If the privilege level and type checks pass, loads the un scrambled limit (the limit scaled according to the setting 
of the G flag in the segment descriptor) into the destinatio n register and sets the ZF flag in the EFLAGS register. 
If the segment selector is not visible at the current privile ge level or is an invalid type for the LSL instruction, 
the instruction does not modify the destination register and clears the ZF flag.
Once loaded in the destination register, software can compare the segment limit with the offset of a pointer. 5-26 Vol. 3APROTECTION
5.10.4 Checking Caller Access Privileges (ARPL Instruction)
The requestor’s privilege level (RPL) field of a segment select or is intended to carry the privilege level of a calling 
procedure (the calling procedure’s CPL) to a called proced ure. The called procedure then uses the RPL to determine 
if access to a segment is allowed. The RPL is said to “wea ken” the privilege level of th e called procedure to that of 
the RPL. 
Operating-system procedures typically use the RPL to pr event less privileged application programs from accessing 
data located in more privileged segmen ts. When an operating-system procedure (the called procedure) receives a 
segment selector from an application program (the callin g procedure), it sets the segment selector’s RPL to the 
privilege level of the callin g procedure. Then, when the operating system  uses the segment selector to access its 
associated segment, the processor performs privilege checks  using the calling procedure’s privilege level (stored in 
the RPL) rather than the numerically lower privilege leve l (the CPL) of the operating-system procedure. The RPL 
thus ensures that the operating system does not access a segment on behalf of an application program unless that 
program itself has access to the segment.
Figure 5-15 shows an example of how the processor uses th e RPL field. In this example, an application program 
(located in code segment A) possesses a segment selector (s egment selector D1) that points to a privileged data 
structure (that is, a data structure located in a data segment D at privilege level 0). 
The application program cannot access data segment D, beca use it does not have sufficient privilege, but the oper-
ating system (located in code segment C) can. So, in an attempt to access data segment D, the application program executes a call to the operating system and pa sses segment selector D1 to the operating system as a 
parameter on the stack. Before passing the segment select or, the (well behaved) application program sets the RPL 
of the segment selector to its current privilege level (which  in this example is 3). If the operating system attempts 
to access data segment D using segment selector D1, the processor compares the CPL (which is now 0 following 
the call), the RPL of segment selector D1, and the DPL of data segment D  (which is 0). Since the RPL is greater than 
the DPL, access to data segment D is denied. The processo r’s protection mechanism thus protects data segment D 
from access by the operating system, because application program’s privilege level (represented by the RPL of 
segment selector B) is greater than the DPL of data segment D.
Figure 5-15.  Use of RPL to Weaken  Privilege Level of Called ProcedurePassed as a 
parameter on
the stack.
Access
allowed
Access
allowedApplication Program
Operating
SystemLowest Privilege
2
1
0Data
Segment DnotSegment Sel. D1
RPL=3
Segment Sel. D2
RPL=0Gate Selector B
RPL=3Code
Segment A
CPL=3
Code
Segment C
DPL=0Call
Gate B
DPL=3
DPL=0Vol. 3A 5-27PROTECTION
Now assume that instead of setting the RPL of the segment selector to 3, th e application program sets the RPL to 
0 (segment selector D2). The operating system can now access data segment D, because its CPL and the RPL of segment selector D2 are both equa l to the DPL of data segment D. 
Because the application program is able to change the RPL of  a segment selector to any value, it can potentially use 
a procedure operating at a numerically lower privilege leve l to access a protected data structure. This ability to 
lower the RPL of a segment selector breaches the processor’s protection mechanism.
Because a called procedure cannot rely on the calling procedure to set the RPL correctly, operating-system proce-
dures (executing at numerically lower privilege-levels) that receive segment selectors from numerically higher 
privilege-level procedures need to test the RPL of the segmen t selector to determine if it is at the appropriate level. 
The ARPL (adjust requested privilege level) instruction is pr ovided for this purpose. This  instruction adjusts the RPL 
of one segment selector to match that of another segment selector.
The example in Figure 5-15 demonstrates how the ARPL in struction is intended to be used. When the operating-
system receives segment selector D2 from the applicatio n program, it uses the ARPL instruction to compare the 
RPL of the segment selector with the privilege level of the application program (represented by the code-segment 
selector pushed onto the stack). If the RPL is less than application program’s privilege level, the ARPL instruction 
changes the RPL of the segment selector to match the privilege level of the application program (segment selector 
D1). Using this instruction thus prevents a procedure running at a numerically higher privilege level from 
accessing numerically lower privilege-level (more privileged)  segments by lowering the RPL of a segment selector.
Note that the privilege level of the application program ca n be determined by reading the RPL field of the segment 
selector for the application-program’s code segment. This se gment selector is stored on the stack as part of the call 
to the operating system. The operating system can copy the segment selector from the stack into a register for use as an operand for the ARPL instruction.
5.10.5 Checking Alignment

When the CPL is 3, alignment of memory references can be  checked by setting the AM flag in the CR0 register and 
the AC flag in the EFLAGS register. Unaligned memory references generate alignment exceptions (#AC). The 
processor does not generate alignment exceptions when oper ating at privilege level 0, 1, or 2. See Table 6-7 for a 
description of the alignment requirements when alignment checking is enabled.
5.11 PAGE-LEVEL PROTECTION
Page-level protection can be used alone or applied to segm ents. When page-level protection is used with the flat 
memory model, it allows supervisor code and data (the op erating system or executive) to be protected from user 
code and data (application programs).  It also allows pages containing code to be write protected. When the 
segment- and page-level protection are combined, page-lev el read/write protection allows more protection granu-
larity within segments.
With page-level protection (as with segment-level protec tion) each memory reference is checked to verify that 
protection checks are satisfied. All checks are made before  the memory cycle is started, and any violation prevents 
the cycle from starting and results in a page-fault exce ption being generated. Because checks are performed in 
parallel with address translation, there is no performance penalty.
The processor performs two page-level protection checks:
•Restriction of addressable domain (supervisor and user modes).
•Page type (read only or read/write).
Violations of either of these checks results in a page-f ault exception being generated. See Chapter 6, “Interrupt 
14—Page-Fault Exception (#PF),” for an explanation of  the page-fault exception mechanism. This chapter 
describes the protection violations wh ich lead to page-fault exceptions.5-28 Vol. 3APROTECTION
5.11.1 Page-Protection Flags
Protection information for pages is contained in two flags in a paging-structure entry (see Chapter 4): the 
read/write flag (bit 1) and the user/supervisor flag (bit 2). The protection checks use the flags in all paging struc-
tures. 
5.11.2 Restricting Addressable Domain
The page-level protection mechanism allows restrict ing access to pages based on two privilege levels:
•Supervisor mode (U/S flag is 0)—(Most privileged) For the operating system or executive, other system 
software (such as device drivers), and prot ected system data (such as page tables).
•User mode (U/S flag is 1)—(Least privileged) For application code and data.
The segment privilege levels map to the page privilege levels as follows. If the processor is currently operating at 
a CPL of 0, 1, or 2, it is in supervisor mode; if it is oper ating at a CPL of 3, it is in user mode. When the processor is 
in supervisor mode, it can access all pages; when in user mode, it can access only user-level pages. (Note that the 
WP flag in control register CR0 modifies the supervisor permissions, as described in Section 5.11.3, “Page Type.”)
Note that to use the page-level protection mechanism, co de and data segments must be set up for at least two 
segment-based privilege levels: level 0 for supervisor code  and data segments and level 3 for user code and data 
segments. (In this model, the stacks are placed in the da ta segments.) To minimize the use of segments, a flat 
memory model can be used (see Section 3.2.1, “Basic Flat Model”). 
Here, the user and supervisor code an d data segments all begin at address zero in the linear address space and 
overlay each other. With this arrangement, operating-system  code (running at the supervisor level) and application 
code (running at the user level) can execute as if there are no segments. Protection between operating-system and 
application code and data is provided by the processor’s page-level protection mechanism. 
5.11.3 Page Type
The page-level protection mechan ism recognizes two page types:
•Read-only access (R/W flag is 0).
•Read/write access (R/W flag is 1).
When the processor is in supervisor mode and the WP flag in register CR0 is clear (its state following reset initial-
ization), all pages are both readable an d writable (write-protection is ignored). When the processor is in user mode, 
it can write only to user-mode pages that are read/wri te accessible. User-mode pages which are read/write or 
read-only are readable; supervisor-mod e pages are neither readable nor writ able from user mode. A page-fault 
exception is generated on any attempt to violate the protection rules.
Starting with the P6 family, Intel processors allow user -mode pages to be write-protected against supervisor-mode 
access. Setting CR0.WP = 1 enables supervisor-mode sensit ivity to write protected pages. If CR0.WP = 1, read-
only pages are not writable from any privilege level. Th is supervisor write-protect feature is useful for imple-
menting a “copy-on-write” strategy used by some operating systems, such as UNIX*, for task creation (also called 
forking or spawning). When a new task is created, it is po ssible to copy the entire address space of the parent task. 
This gives the child task a complete, duplicate set of th e parent's segments and pages. An alternative copy-on-
write strategy saves memory space and time by mapping the child's segments and pages to the same segments 
and pages used by the parent task. A private copy of a page  gets created only when one of the tasks writes to the 
page. By using the WP flag and markin g the shared pages as read-only, the supervisor can detect an attempt to 
write to a page, and can copy the page at that time.
5.11.4 Combining Protection of Both Levels of Page Tables
For any one page, the protection attributes of its page-directory entry (first-level page table) may differ from those 
of its page-table entry (second-level page table). The proc essor checks the protection for a page in both its page-
directory and the page-table entries. Table 5-3 shows th e protection provided by the possible combinations of 
protection attributes when the WP flag is clear.Vol. 3A 5-29PROTECTION
5.11.5 Overrides to Page Protection
The following types of memory accesses are checked as if they are privilege-level 0 accesses, regardless of the CPL 
at which the processor is currently operating:
•Access to segment descriptors in the GDT, LDT, or IDT.
•Access to an inner-privilege-level stack during an inter-pr ivilege-level call or a call to in exception or interrupt 
handler, when a change of privilege level occurs.
5.12 COMBINING PAGE AND SEGMENT PROTECTION
When paging is enabled, the processor evaluates segment protection first, th en evaluates page protection. If the 
processor detects a protection violation at either the se gment level or the page leve l, the memory access is not 
carried out and an exception is generate d. If an exception is generated by segmentation, no paging exception is 
Page-level protections cannot be used to override segm ent-level protection. For example, a code segment is by 
definition not writable. If a code segment is paged, setting  the R/W flag for the pages to read-write does not make 
the pages writable. Attempts to write into the pages will be blocked by segment-level protection checks.
Page-level protection can be used to enhance segment-le vel protection. For example, if a large read-write data 
segment is paged, the page-protection mechanism can be used to write-protect individual pages.
Table 5-3.  Combined Page-Directory and Page-Table Protection
Page-Directory Entry Page- Table Entry Combined Effect
Privilege Access Type Privilege Acc ess Type Privilege Access Type
User Read-Only User Read -Only User Read-Only
User Read-Only User Re ad-Write User Read-Only
User Read-Write User Read -Only User Read-Only 
User Read-Write User Read -Write User Read/Write
User Read-Only Supervisor Read-Only Supervisor Read/Write*User Read-Only Supervisor Read-Write Supervisor Read/Write*
User Read-Write Supervisor Read -Only Supervisor Read/Write*
User Read-Write Supervisor Read -Write Supervisor Read/Write
Supervisor Read-Only User Read-Only Supervisor Read/Write*
Supervisor Read-Only User Read-Write Supervisor Read/Write*
Supervisor Read-Write User Read-Only Supervisor Read/Write*Supervisor Read-Write User Read-Write Supervisor Read/Write
Supervisor Read-Only Supervisor Read-Only Supervisor Read/Write*
Supervisor Read-Only Supervisor Read-Write Supervisor Read/Write*Supervisor Read-Write Supervisor Read-Only Supervisor Read/Write*
Supervisor Read-Write Supervisor Read-Write Supervisor Read/Write
NOTE:
* If CR0.WP = 1, access type is determined by the R/W flags of the page-directory and page -table entries. IF CR0.WP = 0, supervisor 
privilege permits read-write access.5-30 Vol. 3APROTECTION
5.13 PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT
In addition to page-level protection offered by the U/S and R/W flags, paging structures used with PAE paging, 4-
level paging,1 and 5-level paging provide the ex ecute-disable bit (see Chapter 4, “Paging”). This bit offers addi-

NOTE:
tional protection for data pages. 
An Intel 64 or IA-32 processor with the execute-disable bi t capability can prevent data  pages from being used by 
malicious software to execute code. This capability is provided in:
•32-bit protected mode with PAE enabled.
•IA-32e mode.
While the execute-disable bit capability does not introduce new instructions, it does require operating systems to 
use a PAE-enabled environment and establish a page -granular protection policy for memory pages. 
If the execute-disable bit of a memory page is set, that pa ge can be used only as data. An attempt to execute code 
from a memory page with the execute-disable bit set causes a page-fault exception. 
The execute-disable capability is not supported with 32-bit paging. Existing page-level protection mechanisms (see 
Section 5.11, “Page-Level Protection”) continue to apply to memory pages independent of the execute-disable 
setting.
5.13.1 Detecting and Enabling the Execute-Disable Capability
Software can detect the presence of the execute-disable capability using the CPUID instruction. 
CPUID.80000001H:EDX.NX [bit 20] = 1 indi cates the capability is available.
If the capability is available, software can enable it by  setting IA32_EFER.NXE[bit 11] to 1. IA32_EFER is available 
if CPUID.80000001H.EDX[bit 20 or 29] = 1. 
If the execute-disable capability is not available, a write to set IA32_EFER.NXE produces a #GP exception. See 
Table 5-4.
5.13.2 Execute-Disable Page Protection
The execute-disable bit in the paging structures enhances page protection for data pages. Instructions cannot be 
fetched from a memory page if IA32_EFER.NXE =1 and the ex ecute-disable bit is set in any of the paging-structure 
entries used to map the page. Table 5-5 lists the valid usage of a page in relation to the value of execute-disable bit 
(bit 63) of the corresponding entry in each level of the paging structures. Execute-disable protection can be acti-
vated using the execute-disable bit at any level of the pagi ng structure, irrespective of the corresponding entry in 
other levels. When execute-disable protection is not activated, the page can be used as code or data.
1. Earlier versions of this manual used the te rm “IA-32e paging” to identify 4-level paging.Table 5-4.  Extended Feature Enable MSR (IA32_EFER)
63:12 11 10 9 8 7:1 0
Reserved Execute-disable bit 
enable (NXE)IA-32e mode 
active (LMA)Reserved IA-32e mode 
enable (LME)Reserved SysCall enable (SCE)Vol. 3A 5-31PROTECTION
In legacy PAE-enabled mode, Table 5-6 and Table 5-7 show the effect of setting the execute-disable bit for code 
and data pages. 
5.13.3 Reserved Bit Checking
The processor enforces reserved bit checking in paging da ta structure entries. The bits being checked varies with 
paging mode and may vary with the size of physical address space. 
Table 5-8 shows the reserved bits that are checked when the execute disable bit capability is enabled (CR4.PAE = 1 
and IA32_EFER.NXE = 1). Table 5-8 and Table 5-9 show the following paging modes:
•Non-PAE 4-KByte paging: 4-KByte-page only paging (CR4.PAE = 0, CR4.PSE = 0).
•PSE36: 4-KByte and 4-MByte pages (CR4.PAE = 0, CR4.PSE = 1).
•PAE: 4-KByte and 2-MByte pages (CR4.PAE = 1, CR4.PSE = X).
The reserved bit checking depends on the physical ad dress size supported by th e implementation, which is 
reported in CPUID.80000008H. See the table note.Table 5-5.  Page Level Protection Matrix with Execute-Disable Bit Capabi lity with 4-Level Paging
Execute Disable Bit Value (Bit 63) Valid Usage
PML4 PDP PDE PTEBit 63 = 1 * * * Data*B i t  6 3  =  1  * * D a t a* * Bit 63 = 1 * Data** * B i t  6 3  =  1 D a t aBit 63 = 0 Bit 63 = 0 Bit 63 = 0 Bit 63 = 0 Data/CodeNOTES:
* Value not checked.
Table 5-6.  4-KByte Page Level Pr otection Matrix with Execute-Disa ble Bit Capability with PAE Paging
PDE PTEBit 63 = 1 * Data*B i t  6 3  =  1 D a t aBit 63 = 0 Bit 63 = 0 Data/CodeNOTE:
* V a l u e  n o t  c h e c k e d .
Table 5-7.  2-MByte Page Level Protection with  Execute-Disable Bit Capability with PAE Paging
PDEBit 63 = 1 DataBit 63 = 0 Data/Code5-32 Vol. 3APROTECTION
If execute disable bit capability is not enabled or not availa ble, reserved bit checking in 64-bit mode includes bit 63 
and additional bits. This and reserved bit checking fo r legacy 32-bit paging modes are shown in Table 5-10.
 
5.13.4 Exception Handling
When execute disable bit capability is enabled (IA32_EFER.NXE = 1), conditions for a page fault to occur include 
the same conditions that apply to an Intel 64 or IA-32 processor without execute disable bit capability plus the Table 5-8.  Page Level Protection Matrix with Execute-Disable Bit Capability Enabled
Mode Paging Mode Check Bits
32-bit 4-KByte paging (non-PAE) No reserved bits checked
PSE36 - PDE, 4-MByte page Bit [21] PSE36 - PDE, 4-KByte page No reserved bits checkedPSE36 - PTE No reserved bits checkedPAE - PDP table entry Bits [63: MAXPHYADDR] & [8:5] & [2:1] *
PAE - PDE, 2-MByte page Bits  [62:MAXPHYADDR] & [20:13] *
PAE - PDE, 4-KByte page Bits [62:MAXPHYADDR] *PAE - PTE Bits [62:MAXPHYADDR] *
64-bit PML5E Bits [51:MAXPHYADDR] *
PML4E Bits [51:MAXPHYADDR] *PDPTE Bits [51:MAXPHYADDR] *PDE, 2-MByte page Bits [5 1:MAXPHYADDR] & [20:13] *
PDE, 4-KByte page Bits [51:MAXPHYADDR] *PTE Bits [51:MAXPHYADDR] *
NOTES:
* MAXPHYADDR is the maximum physical address size and is indicated by CPUID.80000008H:EAX[bits 7-0].
Table 5-9.  Reserved Bit Checking with Execute-Disable Bit Capability Not Enabled
32-bit KByte paging (non-PAE)  No reserved bits checked
PSE36 - PDE, 4-MByte page  Bit [21] PSE36 - PDE, 4-KByte page  No reserved bits checkedPSE36 - PTE  No reserved bits checkedPAE - PDP table entry  Bits [ 63:MAXPHYADDR] & [8:5] & [2:1]*
PAE - PDE, 2-MByte page  Bits [63:MAXPHYADDR] & [20:13]*PAE - PDE, 4-KByte page  Bits [63:MAXPHYADDR]*PAE - PTE  Bits [63:MAXPHYADDR]*
64-bit PML5E  Bit [63], bits [51:MAXPHYADDR]* 
PML4E  Bit [63], bits [51:MAXPHYADDR]* PDPTE  Bit [63], bits [51:MAXPHYADDR]* PDE, 2-MByte page  Bit [63], bits [51:MAXPHYADDR] & [20:13]* PDE, 4-KByte page  Bit [63], bits [51:MAXPHYADDR]* PTE  Bit [63], bits [51:MAXPHYADDR]* 
NOTES:
* MAXPHYADDR is the maximum physical address size and is indicated by CPUID.80000008H:EAX[bits 7-0].Vol. 3A 5-33PROTECTION
following new condition: an instruction fetch to a linear address that translates to physical address in a memory 
page that has the execute-disable bit set.
An Execute Disable Bit page fault can occur at all privilege levels. It can occur on any instruction fetch, including 
(but not limited to): near branches, far branches, CALL/R ET/INT/IRET execution, sequential instruction fetches, 
and task switches. The execute-disable bit in the page translation mechanism is checked only when:
•IA32_EFER.NXE = 1.
•The instruction translation look-aside buffer (ITLB) is load ed with a page that is not already present in the ITLB.5-34 Vol. 3APROTECTIONVol. 3A 6-1CHAPTER 6
This chapter describes the interrupt and exception-handlin g mechanism when operating in protected mode on an 
Intel 64 or IA-32 processor. Most of the information prov ided here also applies to interrupt and exception mecha-
nisms used in real-address, virtual-8086 mode, and 64-bit mode. 
Chapter 21, “8086 Emulation,” describes information spec ific to interrupt and exception mechanisms in real-
address and virtual-8086 mode. Section 6.14, “Exception an d Interrupt Handling in 64-bit Mode,” describes infor-
mation specific to interrupt and exception me chanisms in IA-32e mode and 64-bit sub-mode.
6.1 INTERRUPT AND EXCEPTION OVERVIEW
Interrupts and exceptions are events that indicate that a condition exists somewhere in the system, the processor, 
or within the currently executing program or task that requires the attention of a processor. They typically result in 
a forced transfer of execution from the currently running program or task to a special software routine or task 
called an interrupt handler or an exception handler. The acti on taken by a processor in response to an interrupt or 
exception is referred to as servicing or handling the interrupt or exception.
Interrupts occur at random times during the execution of a program, in response to signals from hardware. System 
hardware uses interrupts to handle events external to the processor, such as requests to service peripheral devices. 
Software can also generate interrupts by executing the INT n instruction. 
Exceptions occur when the processor detects an error condit ion while executing an instruction, such as division by 
zero. The processor detects a variety of error conditions including protection violations, page faults, and internal 
machine faults. The machine-check architecture of the Pe ntium 4, Intel Xeon, P6 family, and Pentium processors

machine faults. The machine-check architecture of the Pe ntium 4, Intel Xeon, P6 family, and Pentium processors 
also permits a machine-check exception to be generate d when internal hardware errors and bus errors are 
detected.
When an interrupt is received or an exception is detect ed, the currently running procedure or task is suspended 
while the processor executes an interrupt or exception handler. When execution of the handler is complete, the 
processor resumes execution of the interrupted procedure or  task. The resumption of the interrupted procedure or 
task happens without loss of program continuity, unless recovery from an exception was not possible or an inter-rupt caused the currently running program to be terminated.
This chapter describes the processor’s interrupt and exception-handling mechanism, when operating in protected 
mode. A description of the exceptions and the conditions that  cause them to be generated is given at the end of this 
chapter.
6.2 EXCEPTION AND INTERRUPT VECTORS
To aid in handling exceptions and interrupts, each archit ecturally defined exception an d each interrupt condition 
requiring special handling by the processor is assigned a un ique identification number, called a vector number. The 
processor uses the vector number assigned to an exception or interrupt as an index into the interrupt descriptor table (IDT). The table provides the entry point to an ex ception or interrupt handler (see Section 6.10, “Interrupt 
Descriptor Table (IDT)”).
The allowable range for vector numbers is 0 to 255. Vector numbers in the range 0 through 31 are reserved by the 
Intel 64 and IA-32 architectures for architecture-defined ex ceptions and interrupts. Not all of the vector numbers 
in this range have a currently defined function. The unassi gned vector numbers in this range are reserved. Do not 
use the reserved vector numbers. 
Vector numbers in the range 32 to 255 are designated as user-defined interrupts and are not reserved by the Intel 
64 and IA-32 architecture. These interru pts are generally assigned to external  I/O devices to enable those devices 
to send interrupts to the processor through one of the ex ternal hardware interrupt mechanisms (see Section 6.3, 
“Sources of Interrupts”).6-2 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Table 6-1 shows vector number assignments for architectura lly defined exceptions and for the NMI interrupt. This 
table gives the exception type (see Section 6.5, “Exception  Classifications”) and indicates whether an error code is 
saved on the stack for the exception. The source of each predefined exception and the NMI interrupt is also given.
6.3 SOURCES OF INTERRUPTS
The processor receives interrupts from two sources:
•External (hardware generated) interrupts.
•Software-generated interrupts.
6.3.1 External Interrupts
External interrupts are received through pins on the proce ssor or through the local APIC. The primary interrupt pins 
on Pentium 4, Intel Xeon, P6 family, and Pentium proce ssors are the LINT[1:0] pins, which are connected to the 
local APIC (see Chapter 11, “Advanced Programmable Inte rrupt Controller (APIC)”). When the local APIC is 
enabled, the LINT[1:0] pins can be pr ogrammed through the APIC’s local vector table (LVT) to be associated with 
any of the processor’s exception or interrupt vectors.
When the local APIC is global/hardware disabled, these pi ns are configured as INTR and NMI pins, respectively. 
Asserting the INTR pin signals the processor that an external interrupt has occurred. The processor reads from the 
system bus the interrupt vector number provided by an exte rnal interrupt controller, such as an 8259A (see Section 
6.2, “Exception and Interrupt Vectors”). Asserting the NM I pin signals a non-maskable interrupt (NMI), which is 
assigned to interrupt vector 2.
Table 6-1.  Protected-Mode Exceptions and Interrupts 
Vector Mnemonic Description Type Error 
CodeSource
 0 #DE Divide Error Fault No DIV and IDIV instructions.
 1 #DB Debug Exception Fault/ Trap No Inst ruction, data, and I/O breakpoints; 
single-step; and others.
 2 — NMI Interrupt Interrupt No Nonmaskable external interrupt. 3 #BP Breakpoint Trap No INT3 instruction.
 4 #OF Overflow Trap No INTO instruction.
 5 #BR BOUND Range Exceeded Fault No BOUND instruction. 6 #UD Invalid Opcode (Undefined Opcode) F ault No UD instruction or reserved opcode.
 7 #NM Device Not Available (No Math 
Coprocessor)Fault No Floating-point or WAIT/FWAIT instruction.
 8 #DF Double Fault Abort Yes 
(zero)Any instruction that  can generate an 
exception, an NM I, or an INTR.
 9 Coprocessor Segment Overrun 
(reserved)Fault No Floating-point instruction.
1
10 #TS Invalid TSS Fault Yes Task switch or TSS access.
11 #NP Segment Not Present Fault Yes Loading segment registers or accessing 
system segments.
12 #SS Stack-Segment Fault Fault Yes Stack operations and SS register loads.13 #GP General Protection Fault Yes Any memory reference and other 
protection checks.
14 #PF Page Fault Fault Yes Any memory reference.Vol. 3A 6-3INTERRUPT AND EXCEPTION HANDLING
The processor’s local APIC is normally connected to a syst em-based I/O APIC. Here, exte rnal interrupts received at 
the I/O APIC’s pins can be directed to the local APIC thro ugh the system bus (Pentium 4, Intel Core Duo, Intel Core 
2, Intel Atom, and Intel Xeon processors) or the APIC seri al bus (P6 family and Pentium processors). The I/O APIC 
determines the vector number of the interrupt and sends th is number to the local APIC. When a system contains 
multiple processors, processors can also send interrupts to one another by means of the system bus (Pentium 4, 
Intel Core Duo, Intel Core 2, Intel Atom, and Intel Xeon processors) or the APIC serial bus (P6 family and Pentium 
processors). 
The LINT[1:0] pins are not available on the Intel486 processor and earlier Pentium processors that do not contain 
an on-chip local APIC. These processors  have dedicated NMI and INTR pins. With these processors, external inter-
rupts are typically generated by a system-based interrupt controller (8259A), with the interrupts being signaled 
through the INTR pin.
Note that several other pins on the processor can cause a processor interrupt to occur. However, these interrupts 
are not handled by the interrupt and exception mechanism described in this chapter. These pins include the 
RESET#, FLUSH#, STPCLK#, SMI#, R/S#, and INIT# pins. Whet her they are included on a particular processor is 
implementation dependent. Pin functions are described in the data books for the individual processors. The SMI# 
pin is described in Chapter 32, “System Management Mode.”
6.3.2 Maskable Hardware Interrupts
Any external interrupt that is delivered to the processor by means of the INTR pin or through the local APIC is called 
a maskable hardware interrupt. Maskable  hardware interrupts that can be delivered through the INTR pin include 15 — (Intel reserved. Do not use.) No
16 #MF x87 FPU Floating-Point Error (Math 
Fault)Fault No x87 FPU floating-point or WAIT/FWAIT 
17 #AC Alignment Check Fault Yes 
(Zero)Any data reference in memory.2
18 #MC Machine Check Abort No Error codes (if any) and source are model 
dependent.3
19 #XM SIMD Floating-Point Exception Fault No SSE/SSE2/SSE3 floating-point 
instructions4
20 #VE Virtualization Exception Fault No EPT violations5
21 #CP Control Protection Exception Fault Yes RET, IRET, RSTORSSP, and SETSSBSY 
instructions can generate this exception. 
When CET indirect branch tracking is enabled, this exception can be generated 
due to a missing ENDBRANCH instruction 
at target of an indi rect call or jump.
22-31 — Intel reserved. Do not use.
32-255 — User Defined (Non-reserved) 
InterruptsInterrupt External interrupt or INT n instruction.
NOTES:
1. Processors after the Intel386 proc essor do not genera te this exception.
2. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium III processor.5. This exception can occur only on processors that support the 1-setting of the “EPT-violation #VE” VM-execution control.Table 6-1.  Protected-Mode Exceptions and Interrupts  (Contd.)
CodeSource6-4 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
all IA-32 architecture defined interrupt vectors from 0 th rough 255; those that can be delivered through the local 
APIC include interrupt vectors 16 through 255. 
The IF flag in the EFLAGS register permits all maskable hardware interrupts to be masked as a group (see Section 
6.8.1, “Masking Maskable Hardware In terrupts”). Note that when interrupts 0 through 15 are delivered through the 
local APIC, the APIC indicates the receipt of an illegal vector. 
6.3.3 Software-Generated Interrupts
The INT n instruction permits interrupts to be generated from within software by supplying an interrupt vector 
number as an operand. For example, the INT 35 instruction forces an implicit call to the interrupt handler for inter-
rupt 35.

rupt 35. 
Any of the interrupt vectors from 0 to 255 can be used as a parameter in this instruction. If the processor’s 
predefined NMI vector is used, however, the response of th e processor will not be the same as it would be from an 
NMI interrupt generated in the normal manner. If vector num ber 2 (the NMI vector) is used in this instruction, the 
NMI interrupt handler is called, but the processo r’s NMI-handling hardware is not activated. 
Interrupts generated in software with the INT n instruction cannot be masked by the IF flag in the EFLAGS register.
6.4 SOURCES OF EXCEPTIONS
The processor receives exceptions from three sources:
•Processor-detected program-error exceptions.
•Software-generated exceptions.
•Machine-check exceptions.
6.4.1 Program-Error Exceptions
The processor generates one or more exceptions when it detects program errors during the execution in an appli-
cation program or the operating system or executive. In tel 64 and IA-32 architectures define a vector number for 
each processor-detectable exception. Exceptions are classified as faults , traps , and aborts  (see Section 6.5, 
“Exception Classifications”).
6.4.2 Software-Generated Exceptions
The INTO, INT1, INT3, and BOUND instructions permit except ions to be generated in software. These instructions 
allow checks for exception conditions to be performed at po ints in the instruction stream. For example, INT3 causes 
a breakpoint exception to be generated.
The INT n instruction can be used to emulate exceptions in software; but there is a limitation.1 If INT n provides a 
vector for one of the architecturally-defined exceptions, th e processor generates an interrupt to the correct vector 
(to access the exception handler) but does not push an error code on the stack. This is true even if the associated 
hardware-generated exception normally produces an error code. The exception handler will still attempt to pop an 
error code from the stack while handling the exception. Be cause no error code was pushed, the handler will pop off 
and discard the EIP instead (in place of the missing erro r code). This sends the return to the wrong location.
6.4.3 Machine-Check Exceptions
The P6 family and Pentium processors provide both internal and external machine-check mechanisms for checking 
the operation of the internal chip hardware and bus transactions. These mechanisms are implementation depen-
1. The INT n instruction has opcode CD following by an immediate byte encoding the value of n. In contrast, INT1 has opcode F1 and 
INT3 has opcode CC.Vol. 3A 6-5INTERRUPT AND EXCEPTION HANDLING
dent. When a machine-check error is detected, the proc essor signals a machine-check exception (vector 18) and 
returns an error code. 
See Chapter 6, “Interrupt 18—Machine-Check Exception (#MC),” and Chapter 16, “Machine-Check Architecture,” 
for more information about the machine-check mechanism.
6.5 EXCEPTION CLASSIFICATIONS
Exceptions are classified as faults , traps , or aborts  depending on the way they are reported and whether the 
instruction that caused the exception can be restarted without loss of program or task continuity.
•Faults — A fault is an exception that can generally be corrected and that, once corrected, allows the program 
to be restarted with no loss of continuity. When a fault is reported, the processor restores the machine state to 
the state prior to the beginnin g of execution of the faulting instruction.  The return address (saved contents of 
the CS and EIP registers) for the fault handler points to the faulting instruction, rather than to the instruction 
following the faulting instruction.
•Traps — A trap is an exception that is reported immediatel y following the execution of the trapping instruction. 
Traps allow execution of a program or task to be continued without loss of program continuity. The return address for the trap handler points to the instruction to be executed after the trapping instruction.
•Aborts — An abort is an exception that does not always report the precise location of the instruction causing 
the exception and does not allow a restart of the program or  task that caused the exception. Aborts are used to 
report severe errors, such as hardware errors and inconsistent or illegal values in system tables.
NOTE
One exception subset normally reported as a fault is not restartable. Such exceptions result in loss of some processor state. For example, execut ing a POPAD instruction where the stack frame 
crosses over the end of the stack segment causes a fault to be reported. In this situation, the 
exception handler sees that the instruction pointe r (CS:EIP) has been restored as if the POPAD 
instruction had not been executed. However, internal processor state (the general-purpose registers) will have been modified. Such cases are considered programming errors. An application 
causing this class of exceptions should be terminated by the operating system.
6.6 PROGRAM OR TASK RESTART
To allow the restarting of program or task following the handling of an exception or an interrupt, all exceptions 
(except aborts) are guaranteed to report exceptions on an  instruction boundary. All interrupts are guaranteed to be 
taken on an instruction boundary.
For fault-class exceptions, the return instruction pointer (s aved when the processor gene rates an exception) points 
to the faulting instruction. So, when a program or task is restarted following the handling of a fault, the faulting instruction is restarted (re-executed). Restarting the faulting instruction is commonly used to handle exceptions 
that are generated when access to an op erand is blocked. The most  common example of this type of fault is a page-
fault exception (#PF) that occurs when a program or task references an operan d located on a page that is not in 
memory. When a page-fault ex ception occurs, the exception handler can load the page into memory and resume 
execution of the program or task by restarting the faulting instruction. To ensure that the restart is handled trans-
parently to the currently executing pr ogram or task, the processor saves the necessary registers and stack pointers 
to allow a restart to the state prior to the execution of the faulting instruction.
For trap-class exceptions, the return instruction pointer points to the instruction following the trapping instruction. 
If a trap is detected during an instruction which transf ers execution, the return instruction pointer reflects the 
transfer. For example, if a trap is detected while executin g a JMP instruction, the return  instruction pointer points 
to the destination of the JMP instruction, not to the next address past the JMP instruction. All trap exceptions allow 
program or task restart with no loss of continuity. For example, the overflow exception is a trap exception. Here, 
the return instruction pointer points to the instruction fo llowing the INTO instruction that tested EFLAGS.OF (over-
flow) flag. The trap handler for this exception resolves the overflow condition. Upon return from the trap handler, 
program or task execution continues at the instruction following the INTO instruction.6-6 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
The abort-class exceptions do not support reliable restarti ng of the program or task. Abort handlers are designed 
to collect diagnostic information about the state of the processor when the abort exception occurred and then shut 
down the application and system  as gracefully as possible.
Interrupts rigorously support restarting of interrupted pr ograms and tasks without loss of continuity. The return 
instruction pointer saved for an interrupt points to the ne xt instruction to be executed at the instruction boundary 
where the processor took the interrupt. If the instruction ju st executed has a repeat prefix, the interrupt is taken 
at the end of the current iteration with the registers set to execute the next iteration. 
The ability of a P6 family processor to speculatively execut e instructions does not affect the taking of interrupts by 
the processor. Interrupts are taken at instruction boundaries located during the retirement phase of instruction execution; so they are always taken in the “in-order” instruction stream. See Chapter 2, “Intel® 64 and IA-32 
Architectures,” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more informa-
tion about the P6 family processors’ microarchitecture and its support for out-of-order instruction execution.
Note that the Pentium processor and earlier IA-32 proce ssors also perform varying amounts of prefetching and 
preliminary decoding. With these processors as well, exce ptions and interrupts are not signaled until actual “in-
order” execution of the instructions. For a given code sa mple, the signaling of exceptions occurs uniformly when 
the code is executed on any family of IA-32 processors  (except where new exceptions or new opcodes have been 
defined).
6.7 NONMASKABLE INTERRUPT (NMI)
The nonmaskable interrupt (NMI) can be generated in either of two ways:
•External hardware asserts the NMI pin.

defined).
•The processor receives a message on the system bus (Penti um 4, Intel Core Duo, Intel Core 2, Intel Atom, and 
Intel Xeon processors) or the APIC serial bus (P6 family and Pentium processors) with a delivery mode NMI.
When the processor receives a NMI from either of these sources, the processor handles it immediately by calling 
the NMI handler pointed to by interrupt vector number 2.  The processor also invokes certain hardware conditions 
to ensure that no other interrupts, including NMI inte rrupts, are received until the NMI handler has completed 
executing (see Section 6.7.1, “Handling Multiple NMIs”).
Also, when an NMI is received from either of the above sour ces, it cannot be masked by the IF flag in the EFLAGS 
register.
It is possible to issue a maskable hardware interrupt (throu gh the INTR pin) to vector 2 to invoke the NMI interrupt 
handler; however, this interrupt will not truly be an  NMI interrupt. A true NMI interrupt that activates the 
processor’s NMI-handling hardware can only be deli vered through one of the mechanisms listed above.
6.7.1 Handling Multiple NMIs
While an NMI interrupt handler is executing, the processor blocks delivery of subsequent NMIs until the next execu-
tion of the IRET instruction. This blocking of NMIs preven ts nested execution of the NMI handler. It is recommended 
that the NMI interrupt handler be accessed through an inte rrupt gate to disable maskable hardware interrupts (see 
Section 6.8.1, “Masking Mask able Hardware Interrupts”). 
An execution of the IRET instruction unblocks NMIs even if the instruction causes a fault. For example, if the IRET 
instruction executes with EFLAGS.VM = 1 and IOPL of less than 3, a general-protection exception is generated (see 
Section 21.2.7, “Sensitive Instructions”). In such a case, NMIs are unmasked before the exception handler is 
invoked.
6.8 ENABLING AND DISABLING INTERRUPTS
The processor inhibits the generation of some interrupts, depending on the state of the processor and of the IF and 
RF flags in the EFLAGS register, as described in the following sections.Vol. 3A 6-7INTERRUPT AND EXCEPTION HANDLING
6.8.1 Masking Maskable  Hardware Interrupts
The IF flag can disable the servicing of maskable hardwa re interrupts received on th e processor’s INTR pin or 
through the local APIC (see Section 6.3.2, “Maskable Ha rdware Interrupts”). When the IF flag is clear, the 
processor inhibits interrupts delivered to the INTR pin or through the local APIC from generating an internal inter-
rupt request; when the IF flag is se t, interrupts delivered to the INTR or through the local APIC pin are processed 
as normal external interrupts. 
The IF flag does not affect non-maskable interrupts (NMIs) delivered to the NMI pin or delivery mode NMI 
messages delivered through the local APIC, nor does it affect processor generated exceptions. As with the other 
flags in the EFLAGS register, the processor clears  the IF flag in response to a hardware reset.
The fact that the group of maskable hardware interrupts includes the reserv ed interrupt and exception vectors 0 
through 32 can potentially cause confusion. Architecturally, when the IF flag is set, an interrupt for any of the 
vectors from 0 through 32 can be delivered to the processo r through the INTR pin and any of the vectors from 16 
through 32 can be delivered through the local APIC. The pr ocessor will then generate an interrupt and call the 
interrupt or exception handler pointed to by the vector number. So for example, it is possible to invoke the page-fault handler through the INTR pin (by means of vector 14); however, this is not a true page-fault exception. It is 
an interrupt. As with the INT n instruction (see Section 6.4.2, “Software-Generated Exceptions”), when an inter-
rupt is generated through the INTR pin to an exception ve ctor, the processor does not push an error code on the 
stack, so the exception handler may not operate correctly.
The IF flag can be set or cleared with the STI (set in terrupt-enable flag) and CLI (clear interrupt-enable flag) 
instructions, respectively. These instructions may be execut ed only if the CPL is equal to or less than the IOPL. A 
general-protection exception (#GP) is generated if they  are executed when the CPL is greater than the IOPL.
2 If 
IF = 0, maskable hardware interrupts remain inhibited on  the instruction boundary following an execution of STI.3 
The inhibition ends after delivery of  another event (e.g., exception) or the execution of the next instruction.
The IF flag is also affected by the following operations:
•The PUSHF instruction stores all flags on the stack, where they can be examined and modified. The POPF 
instruction can be used to load the modifi ed flags back into the EFLAGS register.
•Task switches and the POPF and IRET instructions load the EFLAGS register; therefore, they can be used to 
modify the setting of the IF flag.
•When an interrupt is handled through an interrupt gate, the IF flag is automatically cleared, which disables 
maskable hardware interrupts. (If an interrupt is hand led through a trap gate, the IF flag is not cleared.)
See the descriptions of the CLI,  STI, PUSHF, POPF, and IRET instructions in Chapter 3, “Instruction Set Reference, 
A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’ s Manual, Volume 2A, and Chapter 4, “Instruc-
tion Set Reference, M-U,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for a 
detailed description of the operations these instru ctions are allowed to perform on the IF flag.
6.8.2 Masking Instruction Breakpoints
The RF (resume) flag in the EFLAGS register controls the response of the processor to instruction-breakpoint condi-
tions (see the description of the RF flag in Section 2. 3, “System Flags and Fields in the EFLAGS Register”). 
When set, it prevents an instruction breakpoint from ge nerating a debug exception (#DB); when clear, instruction 
breakpoints will generate debug exceptions. The primary func tion of the RF flag is to prevent the processor from 
going into a debug exception loop on an instruction-br eakpoint. See Section 18.3.1.1, “Instruction-Breakpoint 
Exception Condition,” for more information on the use of this flag.
As noted in Section 6.8.3, execution of the MOV or POP in struction to load the SS register suppresses any instruc-
tion breakpoint on the next instruction (just as if EFLAGS.RF were 1).
2. The effect of the IOPL on these instructions is modified slightly when the virtual mode extension is enabled by setting the V ME flag 
in control register CR4: see Section 21.3, “Interrupt and Exceptio n Handling in Virtual-8086 Mode.” Behavior is also impacted b y the 
PVI flag: see Section 21.4, “Protected-Mode Virtual Interrupts.”
3. Nonmaskable interrupts and system-management interrupts may also  be inhibited on the instruction boundary following such an 
execution of STI.6-8 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
6.8.3 Masking Exceptions and In terrupts When Switching Stacks
To switch to a different stack segment, software often uses a pair of instructions, for example:
MOV SS, AX
MOV ESP, StackTop
(Software might also use the POP instruction to load SS and ESP.)
If an interrupt or exception occurs after the new SS segm ent descriptor has been loaded but before the ESP register 
has been loaded, these two parts of the logical address into  the stack space are inconsistent for the duration of the 
interrupt or exception handler (assuming that delivery of th e interrupt or exception does not itself load a new stack 
pointer).
To account for this situation, the processor prevents cert ain events from being delivered after execution of a MOV 
to SS instruction or a POP to SS instruction. The following items provide details:
•Any instruction breakpoint on the next instruction is suppressed (as if EFLAGS.RF were 1).
•Any data breakpoint on the MOV to SS instruction or POP to SS instruction is inhibited until the instruction boundary following the next instruction.
•Any single-step trap that would be delivered following the MOV to SS instruction or POP to SS instruction 
(because EFLAGS.TF is 1) is suppressed.
•The suppression and inhibition ends after delivery of an exception or the execution of the next instruction.
•If a sequence of consecutive instructions each loads the SS register (using MOV or POP), only the first is 
guaranteed to inhibit or suppress events in this way.
Intel recommends that software use the LSS instruction to  load the SS register and ESP together. The problem 
identified earlier does not apply to LSS, and the LSS instruction does not inhibit events as detailed above.
6.9 PRIORITIZATION OF CONCURRENT EVENTS 
If more than one event is pending at an instruction bo undary (between execution of instructions), the processor 
services them in a predictable order. Table 6-2 shows the priority among classes of event sources.
Table 6-2.  Priority Among Concurrent Events
Priority Description
1 (Highest) Hardware Reset and Machine Checks
- RESET- Machine Check (#MC)
2 Trap on Task Switch
- T flag in TSS is set (#DB)
3 External Hardware Interventions
- FLUSH

- FLUSH
- STOPCLK
- SMI- INIT
4 Traps on the Previous Instruction
- Trap-class Debug Exceptions (#DB due to TF flag set or data/I-O breakpoint)
5N o n m a s k a b l e  I n t e r r u p t s  ( N M I )
 1
6 Maskable Hardware Interrupts 1
7 Fault-class Debug Exceptions (#DB due to instruction breakpoint)Vol. 3A 6-9INTERRUPT AND EXCEPTION HANDLING
The processor first services a pending event from the class which has the highest priority, transferring execution to 
the first instruction of the handler. Lower priority exce ptions are discarded; lower priority interrupts are held 
pending. Discarded exceptions may be re-generated when the event handler returns execution to the point in the 
program or task where the original event occurred. While the priority among the classes listed in Table 6-2 is 
consistent across processor implementations, the priority of events within a class is implementation-dependent 
and may vary from processor to processor.
Table 6-2 specifies the prioritization of events that may be  pending at an instruction boundary. It does not specify 
the prioritization of faults that arise during instruction execution or event delivery (these include #BR, #TS, #NP, #SS, #GP, #PF, #AC, #MF, #XM, #VE, or #CP). It also does  not apply to the events generated by the “Call to Inter-
rupt Procedure” instructions (INT n, INTO, INT3, and INT1),  as these events are integral to the execution of those 
instructions and do not occur between instructions.
6.10 INTERRUPT DESCRIPTOR TABLE (IDT)
The interrupt descriptor table (IDT) associates each exception or interrupt vector with a gate descriptor for the procedure or task used to service the associated exceptio n or interrupt. Like the GDT and LDTs, the IDT is an array 
of 8-byte descriptors (in protected mode). Unlike the GDT,  the first entry of the IDT may contain a descriptor. To 
form an index into the IDT, the processor scales the exceptio n or interrupt vector by eight (the number of bytes in 
a gate descriptor). Because there are only 256 interrupt or exception vectors, the IDT need not contain more than 
256 descriptors. It can contain fewer than 256 descriptors, because descriptors are required only for the interrupt 
and exception vectors that may occur. All empty descriptor slots in the IDT should have the present flag for the 
descriptor set to 0.
The base addresses of the IDT should be aligned on an  8-byte boundary to maximize performance of cache line 
fills. The limit value is expressed in bytes and is added to the base address to get the address of the last valid byte. 
A limit value of 0 results in exactly 1 valid byte. Because IDT entries are always eight bytes long, the limit should 
always be one less than an integral multiple of eight (that is, 8N – 1).
The IDT may reside anywhere in the linear address space.  As shown in Figure 6-1, the processor locates the IDT 
using the IDTR register. This register holds both a 32-bit base address and 16-bit limit for the IDT.
The LIDT (load IDT register) and SIDT (store IDT register) instructions load and store the contents of the IDTR 
register, respectively. The LIDT instruction loads the IDTR register with the base address and limit held in a 
memory operand. This instruction can be executed only when  the CPL is 0. It normally is used by the initialization 
code of an operating system when creating an IDT. An op erating system also may use it to change from one IDT to 
another. The SIDT instruction copies the base and limit va lue stored in IDTR to memory. This instruction can be 
executed at any privilege level. 
If a vector references a descriptor beyond the limit of th e IDT, a general-protection exception (#GP) is generated.8 Faults from Fetching Next Instruction 
- Code-Segment Limit Violation (#GP)
- Code Page Fault (#PF)
9 (Lowest) Faults from Deco ding the Next Instruction
- Control protection exception due to missing ENDBRAN CH at target of  an indirect ca ll or jump (#CP)
- Instruction length  > 15 bytes (#GP)
- Invalid Opcode (#UD)
- Coprocessor Not Available (#NM)
NOTE
1. The Intel® 486  processor and earlier processors group nonmaskable an d maskable interrupts in the same prio rity class.Table 6-2.  Priority Among Concurrent Events (Contd.)
Priority Description6-10 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
NOTE
Because interrupts are delivered to the processor core only once, an incorrectly configured IDT 
could result in incomplete interrupt handling  and/or the blocking of interrupt delivery. 
IA-32 architecture rules need to be followed for se tting up IDTR base/limit/access fields and each 
field in the gate descriptors. The same apply for the Intel 64 architecture. This includes implicit 
referencing of the destination code segment through the GDT or LDT and accessing the stack.
6.11 IDT DESCRIPTORS
The IDT may contain any of three kinds of gate descriptors:
•Task-gate descriptor
•Interrupt-gate descriptor
•Trap-gate descriptor
Figure 6-2 shows the formats for the task-gate, interrupt-g ate, and trap-gate descriptors. The format of a task 
gate used in an IDT is the same as that of a task gate used in the GDT or an LDT (see Section 8.2.5, “Task-Gate 
Descriptor”). The task gate contains the segment selector for a TSS for an exception and/or interrupt handler task. 
Interrupt and trap gates are very similar to call gates (see  Section 5.8.3, “Call Gates”). They contain a far pointer 
(segment selector and offset) that the processor uses to transfer program execution to a handler procedure in an 
exception- or interrupt-handler code segment. These gates di ffer in the way the processor handles the IF flag in the 
EFLAGS register (see Section 6.12.1.3, “Flag Usage By Exception- or Interrupt-Handler Procedure”).Figure 6-1.  Relationship of the IDTR and IDTIDT Limit IDT Base Address
+Interrupt
Descriptor Table (IDT)
Gate for0IDTR Register
Interrupt #n
Gate for
Interrupt #3
Gate for
Interrupt #2
Gate for
Interrupt #11516 47
0 310816(n−1)∗8Vol. 3A 6-11INTERRUPT AND EXCEPTION HANDLING
6.12 EXCEPTION AND INTERRUPT HANDLING
The processor handles calls to exception- and interrupt-han dlers similar to the way it handles calls with a CALL 
instruction to a procedure or a task. When responding to an exception or interrupt, the processor uses the excep-tion or interrupt vector as an index to a descriptor in the IDT. If the index points to an interrupt gate or trap gate, 
the processor calls the exception or interrupt handler in a manner similar to a CALL to a call gate (see Section 
5.8.2, “Gate Descriptors,” through Section 5.8.6, “Returning  from a Called Procedure”). If index points to a task 
gate, the processor executes a task switch to the exception-  or interrupt-handler task in a manner similar to a CALL 
to a task gate (see Section 8.3, “Task Switching”).Figure 6-2.  IDT Gate Descriptors31 1615 1314 12 87 0
P Offset 31..16D
P
L0 4
31 1615 0
Segment Selector Offset 15..0 0011DInterrupt Gate
DPL
OffsetP
SelectorDescriptor Privilege Level
Offset to procedure entry pointSegment Present flag
Segment Selector for destination code segment31 1615 1314 12 87 0
PD
P
L0 4
31 1615 0
TSS Segment Selector 01010Task Gate
45
0   0   0
31 1615 1314 12 87 0
P
L0 4
31 1615 0
Segment Selector Offset 15..0 0111DTrap Gate
45
0   0   0
ReservedSize of gate: 1 = 32 bits; 0 = 16 bits D6-12 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
6.12.1 Exception- or Interrupt-Handler Procedures
An interrupt gate or trap gate references an exception- or interrupt-handler procedure that runs in the context of 
the currently executing task (see Figure 6-3). The segment se lector for the gate points to a segment descriptor for 
an executable code segment in either the GDT or the current  LDT. The offset field of the gate descriptor points to 
the beginning of the exception- or interrupt-handling procedure.
Figure 6-3.  Interrupt Procedure CallIDT
Interrupt orCode Segment
GDT or LDT
SegmentInterrupt
Vector
Base
AddressDestination
ProcedureInterrupt
+
DescriptorTrap GateOffsetVol. 3A 6-13INTERRUPT AND EXCEPTION HANDLING
When the processor performs a call to the exception- or interrupt-handler procedure:
•If the handler procedure is going to be executed at a numerically lower privilege level, a stack switch occurs. 
When the stack switch occurs: 
a. The segment selector and stack pointer for the stack to  be used by the handler are obtained from the TSS 
for the currently executing task. On this new stack, the processor pushes the stack segment selector and 
stack pointer of the interrupted procedure. 
b. The processor then saves the current state of the EFLAGS, CS, and EIP registers on the new stack (see 
Figure 6-4). 
c. If an exception causes an error code to be saved, it is pushed on the new stack after the EIP value.
•If the handler procedure is going to be executed at the same privilege level as the interrupted procedure:
a. The processor saves the current state of the EFLAGS, CS, and EIP registers on the current stack (see Figure 
6-4).

6-4). 
b. If an exception causes an error code to be saved, it is pushed on the current stack after the EIP value.
To return from an exception- or interrupt-handler procedur e, the handler must use the IRET (or IRETD) instruction. 
The IRET instruction is similar to the RET instruction ex cept that it restores the saved flags into the EFLAGS 
register. The IOPL field of the EFLAGS register is restored on ly if the CPL is 0. The IF flag is changed only if the CPL 
is less than or equal to the IOPL. See Chapter 3,  “Instruction Set Reference, A-L,” of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 2A, for a description of the complete operation performed by the 
IRET instruction.
If a stack switch occurred when calling the handler procedur e, the IRET instruction switches back to the interrupted 
procedure’s stack on the return.Figure 6-4.  Stack Usage on Transfers to Interrupt and Exception-Handling Routines CSError CodeEFLAGS
CS
 EIP
ESP After
Error CodeESP Before
 EFLAGS
 EIP SS
 ESPStack Usage with No
Privilege-Level Change
Stack Usage with
Interrupted Procedure’s Interrupted Procedure’s
Handler’s Stack
ESP After
Transfer to HandlerTransfer to HandlerESP Before
Stack6-14 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
6.12.1.1  Shadow Stack Usage on Transfers to Interrupt and Exception Handling Routines
•If the handler procedure is going to be execute at a nu merically lower privilege level, a shadow stack switch 
occurs. When the shadow stack switch occurs:
a. On a transfer from privilege level 3,  if shadow stacks are enabled at privilege level 3 then the SSP is saved 
to the IA32_PL3_SSP MSR. 
b. If shadow stacks are enabled at the privilege level wh ere the handler will execute then the shadow stack for 
the handler is obtained from one of the following MS Rs based on the privilege level at which the handler 
executes. 
•IA32_PL2_SSP if handler executes at privilege level 2.
•IA32_PL1_SSP if handler executes at privilege level 1.
•IA32_PL0_SSP if handler executes at privilege level 0.
c. The SSP obtained is then verified to ensure it points to a valid supervisory shadow stack that is not currently 
active by verifying a supervisor shadow stack token at  the address pointed to by the SSP. The operations 
performed to verify and acquire the supervisor shadow stack token by ma king it busy are as described in 
Section 17.2.3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
d. On this new shadow stack, the processor pushes th e CS, LIP (CS.base + EIP), and SSP of the interrupted 
procedure if the interrupted procedure was executing at privilege level less than 3; see Figure 6-5.4
•If the handler procedure is going to be executed at th e same privilege level as the interrupted procedure and 
shadow stacks are enabled at current privilege level:
a. The processor saves the current state of the CS, LI P (CS.base + EIP), and SSP registers on the current 
shadow stack; see Figure 6-5.
4. If any of these pushes leads to an exception or a VM exit, the supervisor shadow -stack token remains busy.Vol. 3A 6-15INTERRUPT AND EXCEPTION HANDLING
When executing a return from an interrupt or exception handler from the same privilege level as the interrupted 
procedure, the processor performs these acti ons to enforce return address protection:
•Restores the CS and EIP registers to their values prior to the interrupt or exception.Figure 6-5.  Shadow Stack Us age on Transfers to Interrupt and Exception-Handling RoutinesInterrupted Procedure’s
SSP Before
Transfer to HandlerShadow Stack Usage with 
No Privilege-Level Change
LIPCS
Shadow Stack Usage with Privilege-
Level Change from Level 3
SSP Before
SSP After
Token
Level Change from Level 2 or 1
SSP Before
SSP After
Token
SSPLIP6-16 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
— Compares the values on shadow stack at address SSP+8 (the LIP) and SSP+16 (the CS) to the CS and 
(CS.base + EIP) popped from the stack and causes a control protection exception (#CP(FAR-RET/IRET)) if 
— Pops the top-of-stack value (the SSP prior to the interrupt or exception) from shadow stack into SSP 
register.
procedure, the processor performs the actions below.
•If shadow stack is enabled at current privilege level:
— If SSP is not aligned to 8 bytes then causes a control protection exception (#CP(FAR-RET/IRET)).
— If privilege level of the procedure being returned to is less than 3 (returning to supervisor mode):
(CS.base + EIP) popped from the stack and causes a control protection exception (#CP(FAR-RET/IRET)) 
if they do not match. 
operations described in section Section 17.2.3 of the Intel® 64 and IA-32 Architectures Software 
enabled at privilege level 3, then restores the SSP register with value of IA32_PL3_SSP MSR.
6.12.1.2  Protection of Exception- and Interrupt-Handler Procedures
The privilege-level protection for exception- and interrupt-h andler procedures is similar to that used for ordinary 
procedure calls when called through a call gate (see Se ction 5.8.4, “Accessing a Code Segment Through a Call 
Gate”). The processor does not permit transfer of executio n to an exception- or interrupt-handler procedure in a 
less privileged code segment (numerically greater privilege level) than the CPL. 
An attempt to violate this rule results in a general-pr otection exception (#GP). The protection mechanism for 
exception- and interrupt-handler procedur es is different in the following ways:
•Because interrupt and exception vectors have no RPL, the RPL is not checked on implicit calls to exception and 
interrupt handlers.
•The processor checks the DPL of the interrupt or trap gate only if an exception or interrupt is generated with an 
INT n, INT3, or INTO instruction.5 Here, the CPL must be less than or equal to the DPL of the gate. This 
restriction prevents application programs or procedures running at privilege level 3 from using a software 
interrupt to access critical exception handlers, such as th e page-fault handler, providing that those handlers are 
placed in more privileged code segments (numerically lower privilege level). For hardware-generated interrupts 
and processor-detected exceptions, the processo r ignores the DPL of interrupt and trap gates.
Because exceptions and interrupts generally do not occur at predictable times, these privilege rules effectively 
impose restrictions on the privilege levels at which exce ption and interrupt- handling procedures can run. Either of 
the following techniques can be used to avoid privilege-level violations.
•The exception or interrupt handler can be placed in a co nforming code segment. This technique can be used for 
handlers that only need to access data available on th e stack (for example, divide error exceptions). If the 
handler needs data from a data segment, the data segmen t needs to be accessible from privilege level 3, which 
would make it unprotected.
•The handler can be placed in a nonconforming code segm ent with privilege level 0. This handler would always 
run, regardless of the CPL that the interrupted program or task is running at.
5. This check is not performed by execution of the INT1 instructio n (opcode F1); it would be performed by execution of INT 1 (opc ode 
CD 01).Vol. 3A 6-17INTERRUPT AND EXCEPTION HANDLING
6.12.1.3  Flag Usage By Exception- or Interrupt-Handler Procedure
When accessing an exception or interrupt handler through either an interrupt gate or a trap gate, the processor 
clears the TF flag in the EFLAGS register after it saves th e contents of the EFLAGS register on the stack. (On calls

clears the TF flag in the EFLAGS register after it saves th e contents of the EFLAGS register on the stack. (On calls 
to exception and interrupt handlers, the processor also clea rs the VM, RF, and NT flags in the EFLAGS register, after 
they are saved on the stack.) Clearing the TF flag prevents instruction tracing from affecting interrupt response and 
ensures that no single-step exception will be delivered afte r delivery to the handler. A subsequent IRET instruction 
restores the TF (and VM, RF, and NT) flags to the values in the saved contents of the EFLAGS register on the stack.
The only difference between an interrupt gate and a trap ga te is the way the processor handles the IF flag in the 
EFLAGS register. When accessing an exception- or inte rrupt-handling procedure through an interrupt gate, the 
processor clears the IF flag to prevent other interrupts fr om interfering with the current interrupt handler. A subse-
quent IRET instruction restores the IF flag to its value in  the saved contents of the EFLAGS register on the stack. 
Accessing a handler procedure through a tr ap gate does not affect the IF flag.
6.12.2 Interrupt Tasks
When an exception or interrupt handler is accessed through a task gate in the IDT, a task switch results. Handling 
an exception or interrupt with a sepa rate task offers several advantages:
•The entire context of the interrupted program or task is saved automatically.
•A new TSS permits the handler to use a new privilege leve l 0 stack when handling the exception or interrupt. If 
an exception or interrupt occurs when the current privilege level 0 stack is corrupted, accessing the handler 
through a task gate can prevent a system crash by pr oviding the handler with a new privilege level 0 stack.
•The handler can be further isolated from other tasks by giving it a separate address space. This is done by 
giving it a separate LDT.
The disadvantage of handling an interrupt with a separate task is that the amount of machine state that must be 
saved on a task switch makes it slower than using an interrupt gate, resulting in increased interrupt latency.
A task gate in the IDT references a TSS descriptor in the GDT (see Figure 6-6). A switch to the handler task is 
handled in the same manner as an ordinary task switch (see Section 8.3, “Task Switching”). The link back to the 
interrupted task is stored in the previous task link field of  the handler task’s TSS. If an exception caused an error 
code to be generated, this error code is copied to the stack of the new task.
When exception- or interrupt-handler tasks are used in an operating system, there are actually two mechanisms 
that can be used to dispatch tasks: the software schedu ler (part of the operating system) and the hardware sched-
uler (part of the processor's interrupt mechanism). The software scheduler needs to accommodate interrupt tasks 
that may be dispatched when interrupts are enabled.6-18 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
NOTE
Because IA-32 architecture tasks are not re-entrant, an interrupt-handler task must disable 
interrupts between the time it completes handling the interrupt and the time it executes the IRET 
instruction. This action prevents another interrupt  from occurring while the interrupt task’s TSS is 
still marked busy, which would cause a general-protection (#GP) exception.
6.13 ERROR CODE
When an exception condition is related to a specific segm ent selector or IDT vector, the processor pushes an error 
code onto the stack of the exception handler (whether it is a procedure or task). The error code has the format 
shown in Figure 6-7. The error code rese mbles a segment selector; however, instead of a TI flag and RPL field, the 
error code contains 3 flags:
EXT External event (bit 0) — When set, indicates that the except ion occurred during delivery of an 
event external to the program, such as an interrupt or an earlier exception.6 The bit is cleared if the 
exception occurred during delivery of a software interrupt (INT n, INT3, or INTO).
IDT Descriptor location (bit 1) — When set, indicates that the index portion of the error code refers 
to a gate descriptor in the IDT; when clear, indicates that the index refers to a descriptor in the GDT or the current LDT.
TI GDT/LDT (bit 2) — Only used when the IDT flag is clear. When set, the TI flag indicates that the 
index portion of the error code refers to a segment or  gate descriptor in the LDT; when clear, it indi-
cates that the index refers to a descriptor in the current GDT.Figure 6-6.  Interrupt Task Switch
6. The bit is also set if the exceptio n occurred during delivery of INT1.IDT
Task GateTSS for Interrupt-
TSS Selector
GDT
TSS DescriptorInterrupt
Vector
TSS
BaseAddressHandling TaskVol. 3A 6-19INTERRUPT AND EXCEPTION HANDLING
The segment selector index field provides an index into the IDT, GDT, or current LDT to the segment or gate 
selector being referenced by the error code. In some case s the error code is null (all bits are clear except possibly 
EXT). A null error code indicates that the error was not caus ed by a reference to a specific segment or that a null 
segment selector was referenced in an operation.
The format of the error code is different for page-fault exceptions (#PF). See the “Interrupt 14—Page-Fault Excep-
tion (#PF)” section in this chapter.
The format of the error code is different for control pr otection exceptions (#CP). See the “Interrupt 21—Control 
Protection Exception (#CP)” section in this chapter.
The error code is pushed on the stack as a doubleword or  word (depending on the default interrupt, trap, or task 
gate size). To keep the stack aligned for doubleword pushes , the upper half of the error code is reserved. Note that 
the error code is not popped when the IRET instruction is executed to return from an exception handler, so the 
handler must remove the error code before executing a return.
Error codes are not pushed on the stack for exceptions th at are generated externally (with the INTR or LINT[1:0] 
pins) or the INT n instruction, even if an error code is  normally produced for those exceptions.
6.14 EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE
In 64-bit mode, interrupt and exception handling is simila r to what has been described for non-64-bit modes. The 
following are the exceptions:
•All interrupt handlers pointed by the IDT are in 64-bit code (this does not apply to the SMI handler).
•The size of interrupt-stack pushes is fixed at 64 bits ; and the processor uses 8-byte, zero extended stores.
•The stack pointer (SS:RSP) is pushed unconditionally on interrupts. In legacy modes, this push is conditional 
and based on a change in cu rrent privilege level (CPL).
6.14.1 64-Bit Mode IDT
Interrupt and trap gates are 16 bytes in length to provid e a 64-bit offset for the instruction pointer (RIP). The 64-
bit RIP referenced by interrupt-gate descr iptors allows an interrupt service ro utine to be located anywhere in the 
linear-address space. See Figure 6-8.Figure 6-7.  Error Code31 0
ReservedI
D
TT
I123
Segment Selector IndexE
X
T6-20 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
In 64-bit mode, the IDT index is formed by scaling the interru pt vector by 16. The first eight bytes (bytes 7:0) of a 
64-bit mode interrupt gate are similar but not identical to le gacy 32-bit interrupt gates. The type field (bits 11:8 in 
bytes 7:4) is described in Table 3-2. The Interrupt Stack Table (IST) field (bits 4:0 in bytes 7:4) is used by the stack switching mechanisms described in Sect ion 6.14.5, “Interrupt Stack Table.” Bytes 11:8 hold the upper 32 bits of 
the target RIP (interrupt segment offset) in canonical fo rm. A general-protection exce ption (#GP) is generated if 
software attempts to reference an interrupt gate with a target RIP that is not in canonical form.
The target code segment referenced by the interrupt gate must be a 64-bit code segment (CS.L = 1, CS.D = 0). If 
the target is not a 64-bit code segment, a general-prot ection exception (#GP) is generated with the IDT vector 
number reported as the error code.
Only 64-bit interrupt and trap gates can be referenced in IA-32e mode (64-bit mode and compatibility mode). 
Legacy 32-bit interrupt or trap gate types (0EH or 0FH) are redefined in IA-32e mode as 64-bit interrupt and trap 
gate types. No 32-bit interrupt or trap  gate type exists in IA-32e mode. If a reference is made to a 16-bit interrupt 
or trap gate (06H or 07H), a general-protection exception (#GP(0)) is generated.
6.14.2 64-Bit Mode Stack Frame
In legacy mode, the size of an IDT entry (16 bits or 32 bits) determines the size of interrupt-stack-frame pushes. 
SS:ESP is pushed only on a CPL change. In 64-bit mode, th e size of interrupt stack-frame pushes is fixed at eight 
bytes. This is because only 64-bit mode gates can be refe renced. 64-bit mode also pushes SS:RSP unconditionally, 
rather than only on a CPL change.

When shadow stacks are enabled at the interrupt handle r’s privilege level and the interrupted procedure was not 
executing at a privilege level 3, then the processor push es the CS:LIP:SSP of the interrupted procedure on the 
shadow stack of the interrupt handler (where LI P is the linear address of the return address).
Aside from error codes, pushing SS:RSP unconditionally presents operating systems with a consistent interrupt-
stackframe size across all interrupts. Interrupt service-rout ine entry points that handle interrupts generated by the 
INTn instruction or external INTR# signal can push an additional error code place-holder to maintain consistency.
In legacy mode, the stack pointer may be at any alignment when an interrupt or exception causes a stack frame to 
be pushed. This causes the stack frame and succeeding push es done by an interrupt handler to be at arbitrary 
alignments. In IA-32e mode, the RSP is aligned to a 16-by te boundary before pushing the stack frame. The stack 
frame itself is aligned on a 16-byte boundary when the in terrupt handler is called. The processor can arbitrarily 
realign the new RSP on interrupts because the previous (p ossibly unaligned) RSP is unconditionally saved on the 
newly aligned stack. The previous RSP will be automatically restored by a subsequent IRET.Figure 6-8.  64-Bit IDT Gate Descriptors31 1615 1314 12 87 0
P
L0 4
31 1615 0
Segment Selector Offset 15..0 0TYPEInterrupt/Trap Gate
DPL
OffsetP
Segment Selector for destination code segment45
0   0   031 0
Offset 63..32831 0
12
11
IST 002Reserved
IST Interrupt Stack TableVol. 3A 6-21INTERRUPT AND EXCEPTION HANDLING
Aligning the stack permits exception and interrupt frames  to be aligned on a 16-byte boundary before interrupts 
are re-enabled. This allows the stack to be formatted fo r optimal storage of 16-byte XMM registers, which enables 
the interrupt handler to use faster 16-byte aligned load s and stores (MOVAPS rather than MOVUPS) to save and 
restore XMM registers. 
Although the RSP alignment is always pe rformed when LMA = 1, it is only of consequence for the kernel-mode case 
where there is no stack switch or IST used. For a stack sw itch or IST, the OS would have presumably put suitably 
aligned RSP values in the TSS.
6.14.3 IRET in IA-32e Mode 
In IA-32e mode, IRET executes with an 8-byte operand size. There is nothing that forces this requirement. The stack is formatted in such a way that for actions where IRET is required, the 8-byte IRET operand size works 
correctly. 
Because interrupt stack-frame pushes are always eight by tes in IA-32e mode, an IRET must pop eight byte items 
off the stack. This is accomplished by preceding the IRET with a 64-bit operand-size prefix. The size of the pop is 
determined by the address size of th e instruction. The SS/ESP/RSP size ad justment is determined by the stack 
size.
IRET pops SS:RSP unconditionally off the interrupt stack fram e only when it is executed in 64-bit mode. In compat-
ibility mode, IRET pops SS:RSP off the stack only if there is a CPL change. This allows legacy applications to 
execute properly in compatibility mode when using the IRET instruction. 64-bit interrupt service routines that exit 
with an IRET unconditionally pop SS:RSP off of the inte rrupt stack frame, even if the target code segment is 
running in 64-bit mode or at CPL = 0. This is be cause the original interrupt always pushes SS:RSP.
When shadow stacks are enabled and the target privilege le vel is not 3, the CS:LIP from the shadow stack frame is 
compared to the return linear address formed by CS:EIP fr om the stack. If they do not match then the processor 
caused a control protection exception (#CP(FAR-RET/IRET )), else the processor pops the SSP of the interrupted 
procedure from the shadow stack. If the target privilege le vel is 3 and shadow stacks are enabled at privilege level 
3, then the SSP for the interrupted procedure is restored from the IA32_PL3_SSP MSR.
In IA-32e mode, IRET is allowed to load a NULL SS under certain conditions. If the target mode is 64-bit mode and 
the target CPL ≠ 3, IRET allows SS to be loaded with a NULL sele ctor. As part of the stack switch mechanism, an 
interrupt or exception sets the new SS to NULL, instead of  fetching a new SS selector from the TSS and loading the 
corresponding descriptor from the GDT or LDT. The new SS selector is set to NULL in order to properly handle 
returns from subsequent nested far transfers. If the called  procedure itself is interrupted, the NULL SS is pushed 
on the stack frame. On the subsequent IRET, the NULL SS on  the stack acts as a flag to tell the processor not to 
load a new SS descriptor.
6.14.4 Stack Switching in IA-32e Mode 
The IA-32 architecture provides a mechanism to automatically  switch stack frames in response to an interrupt. The 
64-bit extensions of Intel 64 architecture implement a mo dified version of the legacy stack-switching mechanism 
and an alternative stack-switching mechan ism called the interrupt stack table (IST).
In IA-32 modes, the legacy IA-32 stack-switch mechanism is unchanged. In IA-32e mode, the legacy stack-switch 
mechanism is modified. When stacks are switched as part of a 64-bit mode privilege-level change (resulting from 
an interrupt), a new SS descriptor is not loaded. IA-32e mode loads only an inner-level RSP from the TSS. The new 
SS selector is forced to NULL and the SS selector’s RPL fi eld is set to the new CPL. The new SS is set to NULL in 
order to handle nested far transfers (far CALL, INT, inte rrupts, and exceptions). The old SS and RSP are saved on 
the new stack (Figure 6-9). On the subsequent IRET, the ol d SS is popped from the stack and loaded into the SS 
register.
In summary, a stack switch in IA-32e mode works like the legacy stack switch, except that a new SS selector is not 
loaded from the TSS. Instead, the new SS is forced to NULL.6-22 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
6.14.5 Interrupt Stack Table 
In IA-32e mode, a new interrupt stack table (IST) mechanism is available as an alternative to the modified legacy 
stack-switching mechanism described above. This mechanism unconditionally switches stacks when it is enabled. 
It can be enabled on an indi vidual interrupt-vector basis using a field in the IDT entry. This means that some inter-
rupt vectors can use the modified legacy mechanism and others can use the IST mechanism. 
The IST mechanism is only available in IA-32e mode. It is part of the 64-bit mode TSS. The motivation for the IST 
mechanism is to provide a method for specific interrupts (s uch as NMI, double-fault, and machine-check) to always 
execute on a known good stack. In legacy mode, interru pts can use the task-switch mechanism to set up a known-
good stack by accessing the interrupt service routine throug h a task gate located in the IDT. However, the legacy 
task-switch mechanism is not supported in IA-32e mode. 
The IST mechanism provides up to seven IST pointers in th e TSS. The pointers are referenced by an interrupt-gate 
descriptor in the interrupt-descriptor table (IDT); see Fi gure 6-8. The gate descriptor contains a 3-bit IST index 
field that provides an offset into the IST section of the TSS. Using the IST mechanism, the processor loads the value 
pointed by an IST pointer into the RSP.
When an interrupt occurs, the new SS se lector is forced to NULL and the SS selector’s RPL field is set to the new 
CPL. The old SS, RSP, RFLAGS, CS, and RIP are pushed onto  the new stack. Interrupt processing then proceeds as 
normal. If the IST index is zero, the modified legacy  stack-switching mechanism described above is used.
To support this stack-switching mechanism with shadow st acks enabled, the processor provides an MSR, IA32_IN-
TERRUPT_SSP_TABLE, to program the linear address of a tabl e of seven shadow stack pointers that are selected 
using the IST index from the gate descriptor. To switch to  a shadow stack selected from the interrupt shadow stack 
table pointed to by the IA32_INTERRUPT_SSP_TABLE, the processor requires that the shadow stack addresses 
programmed into this table point to a supe rvisor shadow stack token; see Figure 6-10.Figure 6-9.  IA-32e Mode Stack Usage After Privilege Level Change CS
Error Code RFLAGS
 RIP SS
 RSPStack Usage with
Stack Pointer After
Transfer to Handler CS
Error Code EFLAGS
 EIP SS
 ESPHandler’s StackLegacy Mode IA-32e Mode
0+4+8+12+16+20
0+8+16+24+32+40Vol. 3A 6-23INTERRUPT AND EXCEPTION HANDLING
6.15 EXCEPTION AND INTERRUPT REFERENCE
The following sections describe conditions which generate  exceptions and interrupts. They are arranged in the 
order of vector numbers. The information contained in these sections are as follows:
•Exception Class — Indicates whether the exception class is a fault, trap, or abort type. Some exceptions can

 RIP SS
 EIP SS
•Exception Class — Indicates whether the exception class is a fault, trap, or abort type. Some exceptions can 
be either a fault or trap type, depending on when the e rror condition is detected. (This section is not applicable 
to interrupts.)
•Description — Gives a general description of the purpose of th e exception or interrupt type. It also describes 
how the processor handles the exception or interrupt.
•Exception Error Code — Indicates whether an error code is saved for the exception. If one is saved, the 
contents of the error code are described. (This section is not applicable to interrupts.)
•Saved Instruction Pointer — Describes which instruction the saved (or return) instruction pointer points to. 
It also indicates whether the pointer can be used to restart a faulting instruction.
•Program State Change — Describes the effects of the exception or interrupt on the state of the currently 
running program or task and the possibilities of restarting the program or task without loss of continuity.Figure 6-10.  Interrupt Shadow Stack TableIA32_INTERRUPT_SSP_TABLEIST2 SSPIST3 SSPIST4 SSPIST5 SSPIST6 SSP
Not used; availableIST1 SSPIST7 SSP
56
4840
32
2416
8
06-24 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 0—Divide Error Exception (#DE)
Exception Class Fault.
Indicates the divisor operand for a DIV or IDIV instruction is 0 or that the result cannot be represented in the 
number of bits specified for the destination operand.
Exception Error Code
None.
Saved Instruction Pointer
Saved contents of CS and EIP registers point to  the instruction that generated the exception.
Program State Change
A program-state change does not accompany the divide error, because the exception occurs before the faulting 
instruction is executed.Vol. 3A 6-25INTERRUPT AND EXCEPTION HANDLING
Interrupt 1—Debug Exception (#DB)
Exception Class Trap or Fault. The exception handler can distinguish between traps or faults by exam-
ining the contents of DR6 and the other debug registers.
Indicates that one or more of several debug-exception conditions has been detected. Whether the exception is a 
fault or a trap depends on the condition (see Table 6-3). See Chapter 18, “Debug, Branch Profile, TSC, and Intel® 
Resource Director Technology (Intel® RDT) Features,”  for detailed information about the debug exceptions.
None. An exception handler can examine the debug regist ers to determine which condition caused the exception.
Fault — Saved contents of CS and EIP registers point to the instruction that generated the exception.
Trap — Saved contents of CS and EIP registers point to the instruction following the instruction that generated the 
Fault — A program-state change does not accompany the debug exception, because the exception occurs before 
the faulting instruction is executed. The program can re sume normal execution upon returning from the debug 
Trap — A program-state change does accompany the debug ex ception, because the instruction or task switch being 
executed is allowed to complete before the exception is generated. However, the new state of the program is not 
corrupted and execution of the program can continue reliably.
The following items detail the treatment of debug exceptions on the instruction boundary following execution of the 
MOV or the POP instruction that loads the SS register:
•If EFLAGS.TF is 1, no single-step trap is generated.
•If the instruction encounters a data breakpoint, the resulting debug exception is delivered after completion of 
the instruction after the MOV or POP. This o ccurs even if the next instruction is INT n, INT3, or INTO.
•Any instruction breakpoint on the instruction after the MOV or POP is suppressed (as if EFLAGS.RF were 1).
Any debug exception inside an RTM region causes a transactional abort and, by default, redirects control flow to the 
fallback instruction address. If adva nced debugging of RTM transactional regions has been enabled, any transac-
tional abort due to a debug exception instead causes execution to roll back to just before the XBEGIN instruction Table 6-3.  Debug Exception Conditions and Corresponding Exception Classes
Exception Condition Exception Class
Instruction fetch breakpoint Fault
Data read or write breakpoint Trap
I/O read or write breakpoint TrapGeneral detect condition (in conjunction with in-circuit emulation) FaultSingle-step Trap
Task-switch Trap
Execution of INT1
1
NOTES:
1. Hardware vendors may use the INT1 instru ction for hardware debug. For that reason, Intel recommends software vendors instead  
use the INT3 instruction for software breakpoints.Trap6-26 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
and then delivers a #DB. See Section 16.3.7, “RTM-Enabled Debugger Support,” of Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 1.Vol. 3A 6-27INTERRUPT AND EXCEPTION HANDLING
Interrupt 2—NMI Interrupt
Exception Class Not applicable.
The nonmaskable interrupt (NMI) is gene rated externally by asserting the processor’s NMI pin or through an NMI 
request set by the I/O APIC to the local APIC. This in terrupt causes the NMI interrupt handler to be called.
Not applicable.
The processor always takes an NMI interrupt on an instruction boundary. The saved contents of CS and EIP regis-
ters point to the next instruction to be executed at the point the interrupt is taken. See Section 6.5, “Exception 
Classifications,” for more information about when the processor takes NMI interrupts.
The instruction executing when an NMI interrupt is receiv ed is completed before the NMI is generated. A program 
or task can thus be restarted upon returning from an interrupt handler without loss of continuity, provided the 
interrupt handler saves the state of the processor before handling the interrupt and restores the processor’s state 
prior to a return.6-28 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 3—Breakpoint Exception (#BP)
Exception Class Trap.
Indicates that a breakpoint instruction (INT3, opcode CC)  was executed, causing a breakpoint trap to be gener-
ated. Typically, a debugger sets a breakpoint by replacing th e first opcode byte of an instruction with the opcode for 
the INT3 instruction. (The INT3 instruction is one byte lo ng, which makes it easy to replace an opcode in a code 
segment in RAM with the breakpoint opcode.) The operat ing system or a debugging tool can use a data segment 
mapped to the same physical address space as the code segm ent to place an INT3 instruction in places where it is 
desired to call the debugger.
With the P6 family, Pentium, Intel486, and Intel386 processors, it is more convenient to set breakpoints with the 
debug registers. (See Section 18.3.2, “Breakpoint Except ion (#BP)—Interrupt Vector 3,” for information about the 
breakpoint exception.) If more breakpoints are needed beyo nd what the debug registers allow, the INT3 instruction 
Any breakpoint exception inside an RTM region causes a tr ansactional abort and, by default, redirects control flow 
to the fallback instruction address. If advanced debugg ing of RTM transactional regions has been enabled, any 
transactional abort due to a break exception instead caus es execution to roll back to just before the XBEGIN 
instruction and then delivers a debug exception  (#DB) — not a breakpoint exception. See Section 16.3.7, “RTM-
Enabled Debugger Support,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
A breakpoint exception can also be generated by executing the INT n instruction with an operand of 3. The action 
of this instruction (INT 3) is slightly different than that of the INT3 instruction (see “INT n/INTO/INT3/INT1—Call to 
Interrupt Procedure” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2A).
None.
Saved contents of CS and EIP registers point to the instruction following the INT3 instruction.
Even though the EIP points to the instruction following the breakpoint instruction, the state of the program is 
essentially unchanged because the INT3 instruction does not affect any register or memory locations. The 
debugger can thus resume the suspended program by replac ing the INT3 instruction that caused the breakpoint 
with the original opcode and decrementing the saved co ntents of the EIP register. Upon returning from the 
debugger, program execution resumes with the replaced instruction.Vol. 3A 6-29INTERRUPT AND EXCEPTION HANDLING
Interrupt 4—Overflow Exception (#OF)
Indicates that an overflow trap occurred when an INTO instruction was executed. The INTO instruction checks the 
state of the OF flag in the EFLAGS register. If th e OF flag is set, an overflow trap is generated.
Some arithmetic instructions (such as the ADD and SUB)  perform both signed and unsigned arithmetic. These

Some arithmetic instructions (such as the ADD and SUB)  perform both signed and unsigned arithmetic. These 
instructions set the OF and CF flags in the EFLAGS regi ster to indicate signed overflow and unsigned overflow, 
respectively. When performing arithmetic on signed oper ands, the OF flag can be tested directly or the INTO 
instruction can be used. The benefit of using the INTO instruction is that if the overflow exception is detected, an exception handler can be called automatically to handle the overflow condition.
None.
The saved contents of CS and EIP registers point to the instruction following the INTO instruction.
Even though the EIP points to the instruction following the INTO instruction, the state of the program is essentially 
unchanged because the INTO instruction does not affect any register or memory locations. The program can thus resume normal execution upon returning from the overflow exception handler.6-30 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 5—BOUND Range Exceeded Exception (#BR)
Indicates that a BOUND-range-exceeded fault occurre d when a BOUND instruction was executed. The BOUND 
instruction checks that a signed array index is within the upper and lower bounds of an array located in memory. If 
the array index is not within the bounds of the array, a BOUND-range-exceeded fault is generated.
None.
The saved contents of CS and EIP registers point to the BOUND instruction that generated the exception.
A program-state change does not accompany the bounds -check fault, because the operands for the BOUND 
instruction are not modified. Returning from the BOUN D-range-exceeded exception handler causes the BOUND 
instruction to be restarted.Vol. 3A 6-31INTERRUPT AND EXCEPTION HANDLING
Interrupt 6—Invalid Opcode Exception (#UD)
Indicates that the processor did one of the following things:
•Attempted to execute an invalid or reserved opcode.
•Attempted to execute an instruction with an operand type that is invalid for its accompanying opcode; for 
example, the source operand for a LES instruction is not a memory location.
•Attempted to execute an MMX or SSE/SSE2/SSE3 instruction on an Intel 64 or IA-32 processor that does not 
support the MMX technology or SSE/SSE2/SSE3/SSSE3 ex tensions, respectively. CPUID feature flags MMX (bit 
23), SSE (bit 25), SSE2 (bit 26), SS E3 (ECX, bit 0), SSSE3 (ECX, bit 9) in dicate support for these extensions.
•Attempted to execute an MMX instruction or SSE/SSE2 /SSE3/SSSE3 SIMD instruction (with the exception of 
the MOVNTI, PAUSE, PREFETCH h, SFENCE, LFENCE, MFENCE, CLFLUSH, MONITOR, and MWAIT instructions) 
when the EM flag in control register CR0 is set (1).
•Attempted to execute an SSE/SE2/SSE3/SSSE3 instructio n when the OSFXSR bit in control register CR4 is 
clear (0). Note this does not include the followi ng SSE/SSE2/SSE3 instructions: MASKMOVQ, MOVNTQ, 
MOVNTI, PREFETCH h, SFENCE, LFENCE, MFENCE, and CLFLUSH; or the 64-bit versions of the PAVGB, PAVGW, 
PEXTRW, PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW, PADDQ, PSUBQ, PALIGNR, PABSB, PABSD, PABSW, PHADDD , PHADDSW, PHADDW, PHSUBD, PHSUBSW, PHSUBW, 
PMADDUBSM, PMULHRSW, PSHUFB, PSIGNB, PSIGND, and PSIGNW.
•Attempted to execute an SSE/SSE2/SSE3/SSSE3 instruction on an Intel 64 or IA-32 processor that caused a 
SIMD floating-point exception when the OSXMMEXCPT bit in control register CR4 is clear (0).
•Executed a UD0, UD1 or UD2 instruction. Note that even  though it is the execution of the UD0, UD1 or UD2 
instruction that causes the invalid opcode exception, th e saved instruction pointer will still points at the UD0, 
UD1 or UD2 instruction.
•Detected a LOCK prefix that precedes an instruction that  may not be locked or one that may be locked but the 
destination operand is not a memory location.
•Attempted to execute an LLDT, SLDT, LTR, STR, LSL, LAR, VERR, VERW, or ARPL instruction while in real-
address or virtual-8086 mode.
•Attempted to execute the RSM instruction when not in SMM mode.
In Intel 64 and IA-32 processors that implement out-of-ord er execution microarchitectures, this exception is not 
generated until an attempt is made to retire the result of executing an invalid instruction; that is, decoding and 
speculatively attempting to execute an invalid opcode does  not generate this exception. Likewise, in the Pentium 
processor and earlier IA-32 processors, this exception is no t generated as the result of  prefetching and preliminary 
decoding of an invalid instruction. (See Section 6.5, “Excep tion Classifications,” for general rules for taking of inter-
rupts and exceptions.)
The opcodes D6 and F1 are undefined opcodes reserved by  the Intel 64 and IA-32 architectures. These opcodes, 
even though undefined, do not generate an invalid opcode exception.
None.
The saved contents of CS and EIP registers point to the instruction that generated the exception.
A program-state change does not accompany an invalid-opcode fault, because the invalid instruction is not 
executed.6-32 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 7—Device Not Available Exception (#NM)
Indicates one of the following things:
The device-not-available exception is generated by either of three conditions:
•The processor executed an x87 FPU floating-point instruction while the EM flag in control register CR0 was set 
(1). See the paragraph below for the special case of the WAIT/FWAIT instruction.
•The processor executed a WAIT/FWAIT instruction whil e the MP and TS flags of register CR0 were set, 
regardless of the setting of the EM flag.
•The processor executed an x87 FPU, MMX, or SSE/SS E2/SSE3 instruction (with the exception of MOVNTI, 
PAUSE, PREFETCH h, SFENCE, LFENCE, MFENCE, and CLFLUSH) while th e TS flag in control register CR0 was set 
and the EM flag is clear.
The EM flag is set when the processor does not have an in ternal x87 FPU floating-point unit. A device-not-available 
exception is then generated each time an x87 FPU floating-point instruction is encountered, allowing an exception 
handler to call floating-point instruction emulation routines.
The TS flag indicates that a context switch (task switch) has occurred since the last time an x87 floating-point, 
MMX, or SSE/SSE2/SSE3 instruction was executed; but that the context of the x87 FPU,  XMM, and MXCSR registers 
were not saved. When the TS flag is set and the EM flag is clear, the processor generates a device-not-available 
exception each time an x87 floating-point, MMX, or SSE/ SSE2/SSE3 instruction is encountered (with the exception 
of the instructions listed above). The exception handler ca n then save the context of the x87 FPU, XMM, and MXCSR 
registers before it executes the instruction. See Section 2. 5, “Control Registers,” for more information about the TS 
flag.
The MP flag in control register CR0 is used along with the TS flag to determine if WAIT or FWAIT instructions should 
generate a device-not-available exception. It extends the function of the TS flag to the WAIT and FWAIT instruc-
tions, giving the exception handler an opportunity to sa ve the context of the x87 FPU before the WAIT or FWAIT 
instruction is executed. The MP flag is provided primarily for use with the Intel 286 and Intel386 DX processors. For 
programs running on the Pentium 4, Intel Xeon, P6 family , Pentium, or Intel486 DX processors, or the Intel 487 SX 
coprocessors, the MP flag should always be set; for prog rams running on the Intel486 SX processor, the MP flag 
should be clear. 
None.
The saved contents of CS and EIP registers point to the floating-point instruction or the WAIT/FWAIT instruction that generated the exception.
A program-state change does not accompany a device-not-a vailable fault, because the instruction that generated 
the exception is not executed.
If the EM flag is set, the exception handler can then read the floating-point instruction pointed to by the EIP and call 
the appropriate emulation routine.
If the MP and TS flags are set or the TS flag alone is set,  the exception handler can save the context of the x87 FPU, 
clear the TS flag, and continue execution at the interrupted floating-point or WAIT/FWAIT instruction.Vol. 3A 6-33INTERRUPT AND EXCEPTION HANDLING
Interrupt 8—Double Fault Exception (#DF)
Exception Class Abort.
Indicates that the processor detected a second exception while calling an exception handler for a prior exception. 
Normally, when the processor detects another exception wh ile trying to call an exception handler, the two excep-
tions can be handled serially. If, however, the processor cannot handle them serially, it signals the double-fault

tions can be handled serially. If, however, the processor cannot handle them serially, it signals the double-fault 
exception. To determine when two faults need to be sign alled as a double fault, the processor divides the excep-
tions into three classes: benign exceptions, contributory exceptions, and page faults (see Table 6-4).
Table 6-5 shows the various combinations of exception classes that cause a double fault to be generated. A double-
fault exception falls in the abort class of exceptions. Th e program or task cannot be restarted or resumed. The 
double-fault handler can be used to collect diagnostic information about the state of the machine and/or, when 
possible, to shut the application and/or system down gracefully or restart the system.Table 6-4.  Interrupt and Exception Classes 
Class Vector Number Description
Benign Exceptions and Interrupts  1
 2
 3
 4 5
 6
 79
16
1718
19
AllAllDebug
NMI Interrupt
OverflowBOUND Range Exceeded
Invalid Opcode
Device Not AvailableCoprocessor Segment Overrun
Floating-Point Error
Alignment CheckMachine Check
SIMD floating-point
INT n
INTR
Contributory Exceptions  0
10
11
1213
21Divide Error
Invalid TSS
Segment Not Present
Stack FaultGeneral Protection
Control Protection
Page Faults 14
20Page Fault
Virtualization Exception6-34 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
A segment or page fault may be encountered while prefetch ing instructions; however, this behavior is outside the 
domain of Table 6-5. Any further faults generated while the processor is attempting to transfer control to the appro-
priate fault handler could still le ad to a double-fault sequence.
If another contributory or page fault exception occurs while attempting to call the double-fault handler, the 
processor enters shutdown mode. This mode is similar to th e state following execution of an HLT instruction. In this 
mode, the processor stops executing instructions until an NMI interrupt, SMI interrupt, hardware reset, or INIT# is 
received. The processor generates a special bus cycle to indicate that it has entered shutdown mode. Software 
designers may need to be aware of the response of hardware when it goes into shutdown mode. For example, hard-ware may turn on an indicator light on the front panel, ge nerate an NMI interrupt to record diagnostic information, 
invoke reset initialization, generate an  INIT initialization, or generate an SMI. If any events are pending during 
shutdown, they will be handled after an wake event from  shutdown is processed (for  example, A20M# interrupts).
If a shutdown occurs while the processor is executing an  NMI interrupt handler, then only a hardware reset can 
restart the processor. Likewise, if the shutdown occurs while executing in SMM, a hardware reset must be used to restart the processor.
Zero. The processor always pushes an error code of  0 onto the stack of the double-fault handler. 
The saved contents of CS and EIP registers are undefined.
A program-state following a double-fault exception is undefined. The program or task cannot be resumed or 
restarted. The only available action of the double-fault exception handler is to collect all possible context informa-
tion for use in diagnostics and then close the application and/or shut down or reset the processor.
If the double fault occurs when any portion of the ex ception handling machine state is corrupted, the handler 
cannot be invoked and the processor must be reset.Table 6-5.  Conditions for Generating a Double Fault 
First ExceptionSecond Exception
Benign Contributory Page Fault
Benign Handle Exceptions Seri ally Handle Exceptions Seria lly Handle Exceptions Serially
Contributory Handle Exceptions Serially Generate a Double Fault Handle Exceptions SeriallyPage Fault Handle Exceptions Serially Generate a Double Fault Generate a Double FaultDouble Fault Handle Exceptions Serially Enter Shutdown Mode Enter Shutdown ModeVol. 3A 6-35INTERRUPT AND EXCEPTION HANDLING
Interrupt 9—Coprocessor Segment Overrun
Exception Class Abort. (Intel reserved; do not use. Recent  IA-32 processors do  not generate this 
exception.)
Indicates that an Intel386 CPU-based systems with an Intel 387 math coprocessor detected a page or segment 
violation while transferring the middle portion of an Inte l 387 math coprocessor operand. The P6 family, Pentium, 
and Intel486 processors do not generate this exception; in stead, this condition is detected with a general protec-
tion exception (#GP), interrupt 13.
None.
A program-state following  a coprocessor segment-overrun ex ception is undefined. The program or task cannot 
be resumed or restarted. The only avai lable action of the exception handler is to save the instruction pointer and 
reinitialize the x87 FPU using the FNINIT instruction.6-36 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 10—Invalid TSS Exception (#TS)
Indicates that there was an error related to a TSS. Such an  error might be detected during a task switch or during 
the execution of instructions that use information from a TSS. Table 6-6 shows the conditions that cause an invalid 
TSS exception to be generated.
Table 6-6.  Invali d TSS Conditions 
Error Code Index Invalid Condition
TSS segment selector index The TSS segm ent limit is less than 67H for 32-bit TSS or less than 2CH for 16-bit TSS.
TSS segment selector index During an IR ET task switch, the TI fl ag in the TSS segment se lector indicates the LDT.
TSS segment selector index During an IR ET task switch, the TSS segment sele ctor exceeds descri ptor table limit.
TSS segment selector index During an IRET task switch, the busy flag in the TSS descriptor indicates an inactive task.
TSS segment selector index During a task switch, an attempt to acce ss data in a TSS results in a limit violation or 
canonical fault.
TSS segment selector index During an IRET ta sk switch, the backlink is a NULL selector.
TSS segment selector index During an IRET  task switch, the backlink points to a descriptor which is not a busy TSS.
TSS segment selector index The new TSS descriptor is beyond the GDT limit.TSS segment selector index The new TSS selector  is null on an attemp t to lock the new TSS.
TSS segment selector index The new TSS selector has the TI bit set on an attempt to lock the new TSS.
TSS segment selector index The new TSS descriptor is not an  available TSS descriptor on an attempt to lock the new 
TSS.
LDT segment selector index LDT not valid or not present.Stack segment selector index T he stack segment selector ex ceeds descriptor table limit.
Stack segment selector index The stack segment selector is NULL.
Stack segment selector index The stack se gment descriptor is a non-data segment.
Stack segment selector index The stack segment is not writable.
Stack segment selector in dex The stack segment DPL ≠ CPL.
Stack segment selector index The  stack segment selector RPL ≠ CPL.
Code segment selector index The code segmen t selector exceeds descriptor table limit.
Code segment selector index The code segment selector is NULL.
Code segment selector index The code segment descriptor is not a code segment type.Code segment selector index The nonconforming code segment DPL ≠ CPL.
Code segment selector index The conforming  code segment DPL is  greater than CPL.
Data segment selector index The  data segment selector exceed s the descriptor table limit.
Data segment selector index The data segment descriptor is not a readable code or data type.
Data segment selector index The data segment descriptor is a nonconforming code type and RPL > DPL.
Data segment selector index The data segment descriptor is a nonconforming code type and CPL > DPL.TSS segment selector index The TSS segment descriptor/upper descriptor is beyond the GDT segment limit.
TSS segment selector index The TSS segment descriptor is not an available TSS type.
TSS segment selector index The TSS segment descriptor is an available 286 TSS type in IA-32e mode.Vol. 3A 6-37INTERRUPT AND EXCEPTION HANDLING
This exception can generated either in the context of the or iginal task or in the context of the new task (see Section 
8.3, “Task Switching”). Until the processor has completely verified the presence of the new TSS, the exception is 
generated in the context of the original task. Once the ex istence of the new TSS is verified, the task switch is 
considered complete. Any invalid-TSS conditions detected after this point are handled in the context of the new 
task. (A task switch is considered comp lete when the task register is loaded  with the segment selector for the new 
TSS and, if the switch is due to a procedure call or inte rrupt, the previous task link field of the new TSS references 
the old TSS.)
The invalid-TSS handler must be a task called using a task  gate. Handling this exception inside the faulting TSS

The invalid-TSS handler must be a task called using a task  gate. Handling this exception inside the faulting TSS 
context is not recommended because the processor state may not be consistent. 
An error code containing the segment selector index for th e segment descriptor that caused the violation is pushed 
onto the stack of the exception handler. If the EXT flag is set, it indicates that the exception was caused by an event 
external to the currently running program (for example,  if an external interrupt handler using a task gate 
attempted a task switch to an invalid TSS).
If the exception condition was detected before the task sw itch was carried out, the saved contents of CS and EIP 
registers point to the instruction that invoked the task swit ch. If the exception condition was detected after the task 
switch was carried out, the saved contents of CS and EIP registers point to the first instruction of the new task. 
The ability of the invalid-TSS handler to recover from the fa ult depends on the error condition than causes the fault. 
See Section 8.3, “Task Switching,” for more information on the task switch process and the possible recovery 
actions that can be taken.
If an invalid TSS exception occurs during a task switch, it  can occur before or after the commit-to-new-task point. 
If it occurs before the commit point, no program state ch ange occurs. If it occurs after the commit point (when the 
segment descriptor information for the new segment select ors have been loaded in the segment registers), the 
processor will load all the state inform ation from the new TSS before it gene rates the exception. During a task 
switch, the processor first loads all the segment registers with segment selectors from the TSS, then checks their 
contents for validity. If an invalid TSS exception is discovered, the remaining segment registers are loaded but not 
checked for validity and therefore may not be usable fo r referencing memory. The invalid TSS handler should not 
rely on being able to use the segment selectors found in  the CS, SS, DS, ES, FS, and GS registers without causing 
another exception. The exception handler should load all segment registers before tryi ng to resume the new task; 
otherwise, general-protection exceptions (#GP) may result  later under conditions that make diagnosis more diffi-
cult. The Intel recommended way of dealing situation is to use a task for the invalid TSS exception handler. The task switch back to the interrupted task from the invalid-TSS exception-handler task will then cause the processor to 
check the registers as it loads them from the TSS.TSS segment selector index The TSS segment upper descriptor is not the correct type.
TSS segment selector index The TSS segment descriptor contains a non-canonical base.Table 6-6.  Invalid TSS Conditions  (Contd.)
Error Code Index Invalid Condition6-38 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 11—Segment Not Present (#NP)
Indicates that the present flag of a se gment or gate descriptor is clear. The processor can generate this exception 
during any of the following operations:
•While attempting to load CS, DS, ES, FS, or GS register s. [Detection of a not-present segment while loading the 
SS register causes a stack fault exception (#SS) to be generated.] This situation can occur while performing a 
task switch.
•While attempting to load the LDTR using an LLDT instru ction. Detection of a not-present LDT while loading the 
LDTR during a task switch operation causes an  invalid-TSS exception (#TS) to be generated.
•When executing the LTR instruction and the TSS is marked not present.
•While attempting to use a gate descriptor or TSS that is marked segment-not-present, but is otherwise valid.
An operating system typically uses the segment-not-pr esent exception to implement virtual memory at the 
segment level. If the exception handler loads the segmen t and returns, the interrupte d program or task resumes 
A not-present indication in a gate descriptor, however, do es not indicate that a segment is not present (because 
gates do not correspond to segments). The operating syst em may use the present flag for gate descriptors to 
trigger exceptions of special sign ificance to the operating system.
A contributory exception or page fault that subsequently  referenced a not-present segment would cause a double 
fault (#DF) to be generated instead of #NP.
onto the stack of the exception handler. If the EXT flag is set, it indicates that the exception resulted from either:
•an external event (NMI or INTR) that caused an in terrupt, which subsequently referenced a not-present 
segment
•a benign exception that subsequently referenced a not-present segment 
The IDT flag is set if the error code refers to an IDT en try. This occurs when the ID T entry for an interrupt being 
serviced references a not-present gate. Such an event co uld be generated by an INT instruction or a hardware 
The saved contents of CS and EIP registers normally point to the instruction that generated the exception. If the 
exception occurred while loading segment descriptors for the segment selectors in a new TSS, the CS and EIP 
registers point to the first instruction in the new task. If the exception occurred while accessing a gate descriptor, the CS and EIP registers point to the instruction that invoked the access (for example a CALL instruction that refer-
ences a call gate).
If the segment-not-present exception occurs as the result of loading a register (CS, DS, SS, ES, FS, GS, or LDTR), 
a program-state change does accompany the exception beca use the register is not loaded. Recovery from this 
exception is possible by simply loading the missing segm ent into memory and setting the present flag in the 
segment descriptor.
If the segment-not-present exception occurs while accessing a gate descriptor, a program-state change does not 
accompany the exception. Recovery from this exception is possible merely by setting the present flag in the gate 
If a segment-not-present exception occurs during a task switch, it can occur before or after the commit-to-new-
task point (see Section 8.3, “Task Switching”). If it o ccurs before the commit point, no program state change Vol. 3A 6-39INTERRUPT AND EXCEPTION HANDLING
occurs. If it occurs after the commit point, the processor will load all the state information from the new TSS 
(without performing any additional limit, present, or ty pe checks) before it generates the exception. The segment-
not-present exception handler should not rely on being ab le to use the segment selectors found in the CS, SS, DS, 
ES, FS, and GS registers without causing another exception. (See the Program State Change description for “Inter-
rupt 10—Invalid TSS Exception (#TS)” in this chapter for additional information on how to handle this situation.) 6-40 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 12—Stack Fault Exception (#SS)
Indicates that one of the following st ack related conditions was detected:
•A limit violation is detected during an  operation that refers to the SS register. Operations that can cause a limit 
violation include stack-oriented instructions such as POP,  PUSH, CALL, RET, IRET, ENTER, and LEAVE, as well as 
other memory references which implicitly or explicitly use the SS register (for ex ample, MOV AX, [BP+6] or 
MOV AX, SS:[EAX+6]). The ENTER instruction generates th is exception when there is not enough stack space 
for allocating local variables.
•A not-present stack segment is detected when attempting  to load the SS register. This violation can occur 
during the execution of a task switch, a CALL instruction to a different privilege level, a return to a different 
privilege level, an LSS instruction, or a MOV or POP instruction to the SS register.
•A canonical violation is detected in 64-bit mode duri ng an operation that reference memory using the stack 
pointer register containing a non-canonical memory address.
Recovery from this fault is possible by either extending the limit of the stack segment (in the case of a limit viola-
tion) or loading the missing stack segment into memory (in the case of a not-present violation. 
In the case of a canonical violation that was caused inte ntionally by software, recovery  is possible by loading the 
correct canonical value into RSP. Otherwise, a canonical viol ation of the address in RSP likely reflects some register 
corruption in the software.
If the exception is caused by a not-present stack segment or  by overflow of the new stac k during an inter-privilege-
level call, the error code contains a segment selector fo r the segment that caused the exception. Here, the excep-

tion handler can test the present flag in the segment de scriptor pointed to by the segment selector to determine 
the cause of the exception. For a normal limit violation (on a stack segment already in use) the error code is set to 
0.
The saved contents of CS and EIP registers generally po int to the instruction that generated the exception. 
However, when the exception results from attempting to lo ad a not-present stack segment during a task switch, the 
CS and EIP registers point to the first instruction of the new task.
A program-state change does not generally accompany a stack-fault exception, because the instruction that gener-ated the fault is not executed. Here, the instruction can be restarted after the exception handler has corrected the 
stack fault condition.
If a stack fault occurs during a task switch, it occurs after the commit-to-new-task point (see Section 8.3, “Task 
Switching”). Here, the processor loads all the state info rmation from the new TSS (without performing any addi-
tional limit, present, or type checks) before it generates the exception. The stack fault handler should thus not rely 
on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and GS registers without causing 
another exception. The exception handler should check all segment registers before trying to resume the new 
task; otherwise, general protection faults may result later under conditions that are more difficult to diagnose. (See 
the Program State Change description for “Interrupt 10—Inval id TSS Exception (#TS)” in this chapter for additional 
information on how to handle this situation.) Vol. 3A 6-41INTERRUPT AND EXCEPTION HANDLING
Interrupt 13—General Protection Exception (#GP)
Indicates that the processor detected one of a class of prot ection violations called “general-protection violations.” 
The conditions that cause this exception to be generated comprise all the protection violations that do not cause 
other exceptions to be generated (such as, invalid-TSS, segment-not-present, stack-fault, or page-fault excep-
tions). The following conditions cause genera l-protection exceptions to be generated:
•Exceeding the segment limit when accessing the CS, DS, ES, FS, or GS segments.
•Exceeding the segment limit when referencing a descriptor table (except during a task switch or a stack 
switch).
•Transferring execution to a segment that is not executable.
•Writing to a code segment or a read-only data segment.
•Reading from an execute-only code segment.
•Loading the SS register with a segment selector for a read-only segment (unless the selector comes from a TSS during a task switch, in which case an invalid-TSS exception occurs).
•Loading the SS, DS, ES, FS, or GS register with a segment selector for a system segment.
•Loading the DS, ES, FS, or GS register with a segment selector for an execute-only code segment.
•Loading the SS register with the segment selector of an executable segment or a null segment selector.
•Loading the CS register with a segment selector for a data segment or a null segment selector.
•Accessing memory using the DS, ES, FS, or GS register when it contains a null segment selector.
•Switching to a busy task during a call or jump to a TSS.
•Using a segment selector on a non-IRET task switch that points to a TSS descriptor in the current LDT. TSS descriptors can only reside in the GDT. This conditio n causes a #TS exception during an IRET task switch.
•Violating any of the privilege rules de scribed in Chapter 5, “Protection.”
•Exceeding the instruction length limit of 15 bytes (this only can occur when redundant prefixes are placed 
before an instruction).
•Loading the CR0 register with a set PG flag (paging enabled) and a clear PE flag (protection disabled).
•Loading the CR0 register with a set NW flag and a clear CD flag.
•Referencing an entry in the IDT (following an interrupt or exception) that is not an interrupt, trap, or task gate.
•Attempting to access an interrupt or exception handler through an interrupt or trap gate from virtual-8086 
mode when the handler’s code segment DPL is greater than 0.
•Attempting to write a 1 into a reserved bit of CR4.
•Attempting to execute a privileged instruction when the CPL is not equal to 0 (see Section 5.9, “Privileged Instructions,” for a list of privileged instructions).
•Attempting to execute SGDT, SIDT, SLDT, SMSW, or ST R when CR4.UMIP = 1 and the CPL is not equal to 0.
•Writing to a reserved bit in an MSR.
•Accessing a gate that contains a null segment selector.
•Executing the INT n instruction when the CPL is greater than the DPL of the referenced in terrupt, trap, or task 
gate.
•The segment selector in a call, interrupt, or trap gate does not point to a code segment.
•The segment selector operand in the LLDT instruction is a local type (TI flag is set) or does not point to a 
segment descriptor of the LDT type.
•The segment selector operand in the LTR instruction is local or points to a TSS that is not available.
•The target code-segment selector for a call, jump, or return is null.6-42 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
•If the PAE and/or PSE flag in control register CR4 is set and the processor detects any reserved bits in a page-
directory-pointer-table entry set to 1. These bits are ch ecked during a write to control registers CR0, CR3, or 
CR4 that causes a reloading of the page-directory-pointer-table entry.
•Attempting to write a non-zero value into the reserved bits of the MXCSR register.
•Executing an SSE/SSE2/SSE3 instruction that attempts to access a 128-bit memory location that is not aligned 
on a 16-byte boundary when the instruction requires 16-byt e alignment. This condition also applies to the stack 
segment.
A program or task can be restarted following any general-protection exception. If the exception occurs while 
attempting to call an interrupt handler, the interrupted pr ogram can be restartable, but the interrupt may be lost.
The processor pushes an error code onto the exception ha ndler's stack. If the fault condition was detected while 
loading a segment descriptor, the error code contains a segment selector to or IDT vector number for the 
descriptor; otherwise, the error code is 0. The source of the selector in an error code may be any of the following:
•An operand of the instruction.
•A selector from a gate which is the operand of the instruction.
•A selector from a TSS involved in a task switch.
•IDT vector number.
In general, a program-state change does not accompan y a general-protection exception, because the invalid 
instruction or operation is not executed. An exception handle r can be designed to correct all of the conditions that 
cause general-protection exceptions and restart the program or task without any loss of program continuity.
If a general-protection exception occurs during a task switch, it can occur before or after the commit-to-new-task 
point (see Section 8.3, “Task Switching”). If it occurs be fore the commit point, no program state change occurs. If 
it occurs after the commit point, the processor will load all the state information from the new TSS (without performing any additional limit, present, or type checks) before it generates the exception. The general-protection 
exception handler should thus not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, 
and GS registers without causing another exception. (See the Program State Change description for “Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for addi tional information on how to handle this situation.)
General Protection Exception in 64-bit Mode
The following conditions cause general-protection exceptions in 64-bit mode:
•If the memory address is in a non-canonical form.
•If a segment descriptor memory address is in non-canonical form.
•If the target offset in a destination operand of a call or jmp is in a non-canonical form.
•If a code segment or 64-bit call gate overlaps non-canonical space.
•If the code segment descriptor pointed to by the selector  in the 64-bit gate doesn't have the L-bit set and the 
D-bit clear.
•If the EFLAGS.NT bit is set in IRET.
•If the stack segment selector of IRET is null when going back to compatibility mode.
•If the stack segment selector of IRET is null going back to CPL3 and 64-bit mode.
•If a null stack segment selector RPL of IRET is not equal to CPL going back to non-CPL3 and 64-bit mode.
•If the proposed new code segment descriptor of  IRET has both the D-bit and the L-bit set.Vol. 3A 6-43INTERRUPT AND EXCEPTION HANDLING
•If the segment descriptor pointed to by  the segment selector in the destination operand is a code segment and 
it has both the D-bit and the L-bit set.

•If the segment descriptor from a 64-bit call gate is in non-canonical space.
•If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.
•If the type field of the upper 64 bits of a 64-bit call gate is not 0.
•If an attempt is made to load a null selector in the SS register in compatibility mode.
•If an attempt is made to load null selector in the SS register in CPL3 and 64-bit mode.
•If an attempt is made to load a null selector in the SS  register in non-CPL3 and 64-bit mode where RPL is not 
equal to CPL.
•If an attempt is made to clear CR0.PG while IA-32e mode is enabled.
•If an attempt is made to set a reserved bit in CR3, CR4 or CR8.6-44 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 14—Page-Fault Exception (#PF)
Indicates that, with paging enabled (the PG flag in the CR0 register is set), the processor detected one of the 
following conditions while using the page-translation mechanism to translate a linear address to a physical 
address:
•The P (present) flag in a page-directory or page-table  entry needed for the address translation is clear, 
indicating that a page table or the page containi ng the operand is not present in physical memory.
•The procedure does not have sufficient privilege to access the indicated page (that is, a procedure running in 
user mode attempts to access a supervisor-mode page). If  the SMAP flag is set in CR4, a page fault may also 
be triggered by code running in supervisor mode that tr ies to access data at a user-mode address. If either the 
PKE flag or the PKS flag is set in CR4, the protection -key rights registers may cause page faults on data 
accesses to linear addresses with certain protection keys.
•Code running in user mode attempts to write to a read-o nly page. If the WP flag is set in CR0, the page fault 
will also be triggered by code running in supervis or mode that tries to write to a read-only page.
•An instruction fetch to a linear address that translates to a physical address in a memory page with the 
execute-disable bit set (for information about the execut e-disable bit, see Chapter 4, “Paging”). If the SMEP 
flag is set in CR4, a page fault will also be triggered by  code running in supervisor mode that tries to fetch an 
instruction from a user-mode address.
•One or more reserved bits in paging-structure entry are set to 1. See description below of RSVD error code flag.
•A shadow-stack access is made to a page that is not a shadow-stack page. See Section 17.2, “Shadow Stacks,” 
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, and Section 4.6, “Access 
Rights.”
•An enclave access violates one of the specified access-control requirements. See Section 35.3, “Access-control 
Requirements,” and Section 35.20, “Enclave Page Cache Map (EPCM),” in Chapter 35, “Enclave Access Control 
and Data Structures.” In this case, the exception is called an SGX-induced page fault . The processor uses the 
error code (below) to distinguish SGX-induced page faults from ordinary page faults.
The exception handler can recover from page-not-present conditions and restart the program or task without any 
loss of program continuity. It can also restart the program or task after a privilege violation, but the problem that 
caused the privilege violation may be uncorrectable.
See also: Section 4.7, “Page-Fault Exceptions.”
Yes (special format). The processor provides the page-fault  handler with two items of information to aid in diag-
nosing the exception and recovering from it:
•An error code on the stack. The error code for a page fa ult has a format different from that for other exceptions 
(see Figure 6-11). The processor establishes the bits in the error code as follows:
—P  f l a g  ( b i t 0 ) .
This flag is 0 if there is no translation for the linear  address because the P flag was 0 in one of the paging-
— W/R (bit 1).
If the access causing the page-fault exception was a write,  this flag is 1; otherwise, it is 0. This flag 
describes the access causing the page-fault except ion, not the access rights specified by paging.
— U/S (bit 2).
If a user-mode access caused the page-fault exception, th is flag is 1; it is 0 if a supervisor-mode access did 
so. This flag describes the access causing the page-fault exception, not the access rights specified by 
paging.Vol. 3A 6-45INTERRUPT AND EXCEPTION HANDLING
—R S V D  f l a g  ( b i t 3 ) .
This flag is 1 if there is no translation for the linear address because a reserved bit was set in one of the paging-structure entries used to translate that address.
— I/D flag (bit 4).
This flag is 1 if the access causing the page-fault exce ption was an instruction fetch. This flag describes the 
access causing the page-fault exception, no t the access rights specified by paging.
—P K  f l a g  ( b i t 5 ) .
This flag is 1 if the access causing the page-fault exception was a data access to a linear address with a 
protection key for which the protection-key rights registers disallow access.
—S S  ( b i t 6 ) .
If the access causing the page-fault exception was a shadow-stack access (including shadow-stack accesses in enclave mode), this flag is  1; otherwise, it is 0. This flag describes the access causing the page-
fault exception, not the access rights specified by paging.
—H L A T  ( b i t 7 ) .
This flag is 1 if there is no translation for the line ar address using HLAT paging because, in one of the 
paging-structure entries used to translate that address, either the P flag was 0 or a reserved bit was set. An 
error code will set this flag only if it clears bit 0 or se ts bit 3. This flag will not be set by a page fault resulting 
from a violation of access rights, nor for one encountered during ordinary paging, including the case in which there has been a restart of HLAT paging.
— SGX flag (bit 15).
This flag is 1 if the exception is unrelated to paging and resulted from violation of SGX-specific access-
control requirements. Because such a violation can occur only  if there is no ordinary page fault, this flag is 
set only if the P flag (bit 0) is 1 and the RSVD flag (bit 3) and the PK flag (bit 5) are both 0.
See Section 4.6, “Access Rights,” and Section 4.7, “Page-Fault Exceptions,”  for more information about page-
fault exceptions and the error codes that they produce.6-46 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
•The contents of the CR2 register. The processor loads the CR2 register with the 32-bit linear address that 
generated the exception. The page-fault handler can use this address to locate the corresponding page 
directory and page-table entries. Another page fault ca n potentially occur during execution of the page-fault 
handler; the handler should save the contents of the CR2 register before a second page fault can occur.7 If a 
page fault is caused by a page-level protection violation, the access flag in the page-directory entry is set when 
the fault occurs. The behavior of IA-32 processors rega rding the access flag in the corresponding page-table 
entry is model specific and not architecturally defined.
The saved contents of CS and EIP registers generally point to the instruction that generated the exception. If the 
page-fault exception occurred during a task switch, the CS and EIP registers may point to the first instruction of the 
new task (as described in the following “Program State Change” section).
A program-state change does not normally accompany a page -fault exception, because the instruction that causes 
the exception to be generated is not executed. After the page-fault exception handler has corrected the violation (for example, loaded the missing page into memory),  execution of the program or task can be resumed.Figure 6-11.  Page-Fault Error Code
7. Processors update CR2 whenever a page fault is detected. If a second page fault occurs while an earlier page fault is being d eliv-
ered, the faulting linear address of the second fault will overwrite the contents of CR2 (replacing the previous address). Thes e 
updates to CR2 occur even  if the page fault results in a double fault or occurs during the delivery of a double fault.The fault was caused by a non-present page.
1
W/R 0
1
U/S 0
RSVD 0
11I/D
W/RU/S
RSVD

1
W/R 0
1
U/S 0
RSVD 0
11I/D
W/RU/S
RSVD
SGX15SS6
requirements.Vol. 3A 6-47INTERRUPT AND EXCEPTION HANDLING
When a page-fault exception is generated during a task switch, the program-state may change, as follows. During 
a task switch, a page-fault exception can occur during any of following operations:
•While writing the state of the original task into the TSS of that task.
•While reading the GDT to locate the TSS descriptor of the new task.
•While reading the TSS of the new task.
•While reading segment descriptors associated with segment selectors from the new task.
•While reading the LDT of the new task to verify  the segment registers stored in the new TSS.
In the last two cases the exception occurs in the context of  the new task. The instruction pointer refers to the first 
instruction of the new task, not to the instruction which caused the task switch (or the last instruction to be executed, in the case of an interrupt). If the design of the operating system permits page faults to occur during 
task-switches, the page-fault handler should be called through a task gate.
If a page fault occurs during a task switch, the proces sor will load all the state information from the new TSS 
(without performing any additional limit, present, or type  checks) before it generates the exception. The page-fault 
handler should thus not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and GS 
registers without causing another exception. (See the Prog ram State Change description for “Interrupt 10—Invalid 
TSS Exception (#TS)” in this chapter for additional information on how to handle this situation.) 
Additional Exception-Handling Information
Special care should be taken to ensure that an exception that occurs during an explicit stack switch does not cause the processor to use an invalid stack pointer (SS:ESP). So ftware written for 16-bit IA-32 processors often use a 
pair of instructions to change to a new stack, for example:
MOV SS, AX
MOV SP, StackTop
When executing this code on one of the 32-bit IA-32 proce ssors, it is possible to get a page fault, general-protec-
tion fault (#GP), or alignment check fault (#AC) after the segment selector has been loaded into the SS register 
but before the ESP register has been loaded. At this po int, the two parts of the st ack pointer (SS and ESP) are 
inconsistent. The new stack segment is being used with the old stack pointer.
The processor does not use the inconsistent stack pointer if the exception handler switches to a well defined stack 
(that is, the handler is a task or a more privileged proced ure). However, if the exception handler is called at the 
same privilege level and from the same task, the proce ssor will attempt to use the inconsistent stack pointer.
In systems that handle page-fault, general-protection, or alignment check exceptions within the faulting task (with 
trap or interrupt gates), software executing at the same privilege level as the exception handler should initialize a 
new stack by using the LSS instruction rather than a pair of MOV instructions, as described earlier in this note. 
When the exception handler is running at privilege level 0 (the normal case), the problem is limited to procedures 
or tasks that run at privilege level 0, ty pically the kernel of the operating system.6-48 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 16—x87 FPU Floating-Point Error (#MF)
Indicates that the x87 FPU has detected a floating-point error. The NE flag in the register CR0 must be set for an 
interrupt 16 (floating-point error exception) to be genera ted. (See Section 2.5, “Control Registers,” for a detailed 
description of the NE flag.)
NOTE
SIMD floating-point exceptions (#XM) are signaled through interrupt 19. 
While executing x87 FPU instructions, th e x87 FPU detects and reports six types of floating-point error conditions:
•Invalid operation (#I)
— Stack overflow or underflow (#IS)— Invalid arithmetic operation (#IA)
•Divide-by-zero (#Z)
•Denormalized operand (#D)
•Numeric overflow (#O)
•Numeric underflow (#U)
•Inexact result (precision) (#P)
Each of these error conditions represents an x87 FPU ex ception type, and for each of exception type, the x87 FPU 
provides a flag in the x87 FPU status register and a mask bit in the x87 FPU control register. If the x87 FPU detects 
a floating-point error and the mask bit for the exception type is set, the x87 FPU handles the exception automati-
cally by generating a predefined (default) response and continuing program execution. The default responses have 
been designed to provide a reasonable result for most floating-point applications.
If the mask for the exception is clear and the NE flag in register CR0 is set, the x87 FPU does the following:
1. Sets the necessary flag in the FPU status register.
2. Waits until the next “waiting” x87 FPU instruction or WAIT/FWAIT instruction is encountered in the program’s 
3. Generates an internal error signal that cause the pr ocessor to generate a floating-point exception (#MF).
Prior to executing a waiting x87 FPU instruction or the WA IT/FWAIT instruction, the x87 FPU checks for pending x87 
FPU floating-point exceptions (as described in step 2 above). Pending x87 FPU floating-point exceptions are ignored for “non-waiting” x87 FPU instructions, which include the FNINIT, FNCLEX, FNSTSW, FNSTSW AX, FNSTCW, 
FNSTENV, and FNSAVE instructions. Pending x87 FPU exce ptions are also ignored when executing the state 
management instructions FXSAVE and FXRSTOR.
All of the x87 FPU floating-point error conditions can be  recovered from. The x87 FPU floating-point-error exception 
handler can determine the error condition that caused the exception from the settings of the flags in the x87 FPU 
status word. See “Software Exception Handling” in Chapter 8 of the Intel
Developer’s Manual, Volume 1, for more informatio n on handling x87 FPU floating-point exceptions.
None. The x87 FPU provides its own error information.
The saved contents of CS and EIP registers point to the floating-point or WAIT/FWAIT instruction that was about to 
be executed when the floating-point-error exception was gene rated. This is not the faulting instruction in which the 
error condition was detected. The address of the faulting in struction is contained in the x87 FPU instruction pointer Vol. 3A 6-49INTERRUPT AND EXCEPTION HANDLING
register. See Section 8.1.8, “x87 FPU Instruction and Data (Operand) Pointers,” in Chapter 8 of the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 1, for more information about information the FPU saves 
for use in handling floating-point-error exceptions.
A program-state change generally accompanies an x87 FPU floating-point exception because the handling of the 
exception is delayed until the next wait ing x87 FPU floating-point or WAIT/FWA IT instruction following the faulting 
instruction. The x87 FPU, however, saves sufficient informat ion about the error condition to allow recovery from the 
error and re-execution of the faulting instruction if needed.
In situations where non- x87 FPU floating-point instructio ns depend on the results of an x87 FPU floating-point 
instruction, a WAIT or FWAIT instruction can be inserted in front of a dependent instruction to force a pending x87 
FPU floating-point exception to be handled before the de pendent instruction is executed. See “x87 FPU Exception 
Synchronization” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for 
more information about synchronization of x87 floating-point-error exceptions.6-50 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 17—Alignment Check Exception (#AC)
Indicates that the processor detected an unaligned memo ry operand when alignment checking was enabled. Align-
ment checks are only carried out in data (or stack) acce sses (not in code fetches or system segment accesses). An 
example of an alignment-check violation is a word stored at an odd byte address, or a doubleword stored at an 
address that is not an integer multiple of 4. Table 6-7 lists the alignment requirements various data types recog-
nized by the processor.
Note that the alignment check exception (#AC) is generate d only for data types that must be aligned on word, 
doubleword, and quadword boundaries. A general-protection  exception (#GP) is generated 128-bit data types that 
are not aligned on a 16-byte boundary.
To enable alignment checking, the fo llowing conditions must be true:
•AM flag in CR0 register is set.
•AC flag in the EFLAGS register is set.

•The CPL is 3 (including virtual-8086 mode).
Alignment-check exceptions (#AC) are generated only when operating at privilege level 3 (user mode). Memory 
references that default to privilege level 0, such as segment descriptor loads, do not generate alignment-check 
exceptions, even when caused by a memory reference made from privilege level 3.
Storing the contents of the GDTR, IDTR, LDTR, or task regi ster in memory while at privilege level 3 can generate 
an alignment-check exception. Although application progra ms do not normally store these registers, the fault can 
be avoided by aligning the informat ion stored on an even word-address.
The FXSAVE/XSAVE and FXRSTOR/XRSTOR instructions save and restore a 512-byte data structure, the first byte 
of which must be aligned on a 16-byte boundary. If the alignment-check exception (#AC) is enabled when 
executing these instructions (and CPL is 3), a misalign ed memory operand can cause either an alignment-check 
exception or a general-protection exception (#GP) depend ing on the processor implementation (see “FXSAVE-Save 
x87 FPU, MMX, SSE, and SSE2 State” and “FXRSTOR-Resto re x87 FPU, MMX, SSE, and SSE2 State” in Chapter 3 Table 6-7.  Alignment Requirements by Data Type
Data Type Address Must Be Divisible By
Word 2Doubleword 4
Single precision floating-point (32-bits) 4
Double precision floating-point (64-bits) 8Double extended precision floating-point (80-bits) 8
Quadword 8
Double quadword 16Segment Selector 2
32-bit Far Pointer 2
48-bit Far Pointer 432-bit Pointer 4
GDTR, IDTR, LDTR, or Task Register Contents 4
FSTENV/FLDENV Save Area 4 or 2, depending on operand sizeFSAVE/FRSTOR Save Area 4 or 2, depending on operand size
Bit String 2 or 4 depending on  the operand-size attribute.Vol. 3A 6-51INTERRUPT AND EXCEPTION HANDLING
of the Intel® 64 and IA-32 Architectures Software Developer’ s Manual, Volume 2A; see “XSAVE—Save Processor 
Extended States” and “XRSTOR—Restore Processor Extended States” in Chapter 6 of the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 2D).
The MOVDQU, MOVUPS, and MOVUPD inst ructions perform 128-bit unaligned loads or stores. The LDDQU instruc-
tions loads 128-bit unaligned data. They do not generate general-protection exceptions (#GP) when operands are 
not aligned on a 16-byte boundary. If alignment checking  is enabled, alignment-check exceptions (#AC) may or 
may not be generated depending on processor implementati on when data addresses are not aligned on an 8-byte 
boundary.
FSAVE and FRSTOR instructions can generate unaligne d references, which can caus e alignment-check faults. 
These instructions are rarely needed by application programs. 
Yes. The error code is null; all bits are clear except possi bly bit 0 — EXT; see Section 6. 13. EXT is set if the #AC is 
recognized during delivery of an event other than a soft ware interrupt (see “INT n/INTO/INT3/INT1—Call to Inter-
rupt Procedure” in Chapter 3 of the Intel®64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).
A program-state change does not accompany an alignment- check fault, because the instruction is not executed.6-52 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 18—Machine-Check Exception (#MC)
Indicates that the processor detected an internal machine e rror or a bus error, or that an external agent detected 
a bus error. The machine-check exception is model-specif ic, available on the Pentium and later generations of 
processors. The implementation of the machine-check exce ption is different between different processor families, 
and these implementations may not be compatible with future Intel 64 or IA-32 pr ocessors. (Use the CPUID 
instruction to determine whether this feature is present.)
Bus errors detected by external agen ts are signaled to the processor on dedicated pins: the BINIT# and MCERR# 
pins on the Pentium 4, Intel Xeon, and P6 family proce ssors and the BUSCHK# pin on the Pentium processor. When 
one of these pins is enabled, asserting the pin causes e rror information to be loaded into machine-check registers 
and a machine-check exception is generated.
The machine-check exception and machine-check architecture are discussed in detail in Chapter 16, “Machine-
Check Architecture.” Also, see the data books for the indivi dual processors for processor-specific hardware infor-
mation. 
None. Error information is provided by machine-check MSRs.
For the Pentium 4 and Intel Xeon processors, the saved co ntents of extended machine-check state registers are 
directly associated with the error that caused the mach ine-check exception to be generated (see Section 16.3.1.2, 
“IA32_MCG_STATUS MSR,” and Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs”).
For the P6 family processors, if the EIPV flag in the MC G_STATUS MSR is set, the saved contents of CS and EIP 
registers are directly associated with the error that caused  the machine-check exception to be generated; if the flag 
is clear, the saved instruction pointer may not be associated with the error (see Section 16.3.1.2, “IA32_MC-
G_STATUS MSR”).
For the Pentium processor, contents of the CS and EIP registers may not be associated with the error.
The machine-check mechanism is enabled by setti ng the MCE flag in control register CR4. 
For the Pentium 4, Intel Xeon, P6 family, and Pentium pr ocessors, a program-state change always accompanies a 
machine-check exception, and an abort class exception is  generated. For abort exceptions, information about the 
exception can be collected from the machine-check MS Rs, but the program cannot generally be restarted. 
If the machine-check mechanism is not enabled (the MCE flag in control register CR4 is clear), a machine-check 
exception causes the processor to enter the shutdown state.Vol. 3A 6-53INTERRUPT AND EXCEPTION HANDLING
Interrupt 19—SIMD Floating-Point Exception (#XM)
Indicates the processor has detected an SSE/SSE2/SSE3 SIMD floating-point exception. The appropriate status 
flag in the MXCSR register must be set and the particular  exception unmasked for this interrupt to be generated.
There are six classes of numeric exception conditions that can occur while executing an SSE/ SSE2/SSE3 SIMD 
floating-point instruction:
•Denormal operand (#D)
•Inexact result (Precision) (#P)
The invalid operation, divide-by-zero, and denormal-opera nd exceptions are pre-computation exceptions; that is, 
they are detected before any arithmetic operation occu rs. The numeric underflow, numeric overflow, and inexact 
result exceptions are post-computational exceptions.
See “SIMD Floating-Point Exceptio ns” in Chapter 11 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, for additional information ab out the SIMD floating-point exception classes.
When a SIMD floating-point exception occurs, the processor does either of the following things:
•It handles the exception automatically by producing the most reasonable result and allowing program 
execution to continue undisturbed. This is the response to masked exceptions.
•It generates a SIMD floating-point exception, which in turn invokes a software exception handler. This is the 
response to unmasked exceptions.
Each of the six SIMD floating-point exception conditions has a corresponding flag bit and mask bit in the MXCSR 
register. If an exception is masked (the corresponding ma sk bit in the MXCSR register is set), the processor takes 
an appropriate automatic default action and continues wi th the computation. If the exception is unmasked (the 
corresponding mask bit is clear) and the operating syst em supports SIMD floating-point exceptions (the OSXM-
MEXCPT flag in control register CR4 is set), a software exception handler is invoked through a SIMD floating-point 
exception. If the exception is unmasked and the OSXMMEXC PT bit is clear (indicating that the operating system 
does not support unmasked SIMD floating-point exceptions),  an invalid opcode exception (#UD) is signaled instead 
of a SIMD floating-point exception.
Note that because SIMD floating-point exceptions are precise and occur immediately, the situation does not arise 
where an x87 FPU instruction, a WAIT/FWAIT instruction, or another SSE/SSE2/SSE3 instruction will catch a 
pending unmasked SIMD floating-point exception.
In situations where a SIMD floating-point exception o ccurred while the SIMD floating-point exceptions were 
masked (causing the corresponding exception flag to be  set) and the SIMD floating-point exception was subse-
quently unmasked, then no exception is generated when the exception is unmasked.

When SSE/SSE2/SSE3 SIMD floating-point instructions oper ate on packed operands (made up of two or four sub-
operands), multiple SIMD floating-poi nt exception conditions may be detect ed. If no more than one exception 
condition is detected for one or more sets of sub-operan ds, the exception flags are set for each exception condition 
detected. For example, an invalid exception detected for one sub-operand will not prevent the reporting of a divide-
by-zero exception for another sub-operand. However, when two or more exceptions conditions are generated for one sub-operand, only one exception condition is reported , according to the precedences shown in Table 6-8. This 
exception precedence sometimes results in the higher pr iority exception condition being reported and the lower 
priority exception conditions being ignored.6-54 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
None.
The saved contents of CS and EIP registers point to th e SSE/SSE2/SSE3 instruction that was executed when the 
SIMD floating-point exception was generated. This is th e faulting instruction in which the error condition was 
detected.
A program-state change does not accompany a SIMD floati ng-point exception because the handling of the excep-
tion is immediate unless the particular exception is mask ed. The available state information is often sufficient to 
allow recovery from the error and re-executi on of the faulting instruction if needed.Table 6-8.  SIMD Floating-Point Exceptions Priority
1 (Highest) Invalid operation exception due to SNaN operand (or any NaN operand for maximum, mi nimum, or certain compare and 
convert operations).
2 QNaN operand1.
3 Any other invalid operation exception not mentioned above or a divide-by-zero exception2.
4 Denormal operand exception2.
5 Numeric overflow and underflow exceptions possibly in conjunction with the inexact result exception2.
6 (Lowest) Inexact result exception.
NOTES:
1. Though a QNaN this is not an exception, the handling of a QNaN operand has precedence over lower priority exceptions. For exa m-
ple, a QNaN divided by zero results in a QNaN, not a divide-by-zero- exception.
2. If masked, then instruction execution continues, and a lower priority exception can occur as well.Vol. 3A 6-55INTERRUPT AND EXCEPTION HANDLING
Interrupt 20—Virtualization Exception (#VE)
Indicates that the processor detected an EPT violation in VMX non-root operation. Not all EPT violations cause 
virtualization exceptions. See Section 26.5.7.2 for details.
The exception handler can recover from EPT violations and restart the program or task without any loss of program 
continuity. In some cases, however, the problem that caused the EPT violation may be uncorrectable.
None.
The saved contents of CS and EIP registers generally point to the instruction that generated the exception.
A program-state change does not normally accompany a virtualization exception, because the instruction that 
causes the exception to be generated is not executed. Af ter the virtualization exception handler has corrected the 
violation (for example, by executing the EPTP-switching VM function), execution of the program or task can be 
resumed.
The processor saves information about virtualization exceptions in the virtualization-exception information area. 
See Section 26.5.7.2 for details.6-56 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupt 21—Control Protection Exception (#CP)
Indicates a control flow transfer attempt violated the control flow enforcement technology constraints.
Yes (special format). The processor provides the control protection exception handler with following information 
through the error code on the stack. 
•Bit 14:0 - CPEC
— 1 - NEAR-RET: Indicates the #CP was caused by a near RET instruction.— 2 - FAR-RET/IRET: Indicates the #CP was caused by a FAR RET or IRET instruction.
— 3 - ENDBRANCH: indicates the #CP was due to missing ENDBRANCH at target of an indirect call or jump 
— 4 - RSTORSSP: Indicates the #CP was caused by a shadow-stack-restore token check failure in the 
RSTORSSP instruction.
— 5- SETSSBSY: Indicates #CP was caused by a supervisor  shadow stack token check failure in the SETSSBSY 
•Bit 15 (ENCL) of the error code, if set to 1, indicates the #CP occurred during enclave execution.
The saved contents of the CS and EIP registers generall y point to the instruction that generated the exception.
A program-state change does not normally accompany a cont rol protection exception, because the instruction that 
causes the exception to be generated is not executed.
When a control protection exception is generated during a task switch, the program-state may change as follows. 
During a task switch, a control protection exception can occur during any of following operations:
•If task switch is initiated by IRET, CS and LIP stored on old task shadow stack do not match CS and LIP of new 
task (where LIP is the linear address of the return address).
•If task switch is initiated by IRET and SSP of new task loaded from shadow stack of old task (if new task CPL is 
< 3), OR the SSP from IA32_PL3_SSP (if new task CPL = 3) is not aligned to 4 bytes or is a value beyond 4GB.Figure 6-12.  Exception Error Code Information  0 31
CPECENCL15 14               
ReservedVol. 3A 6-57INTERRUPT AND EXCEPTION HANDLING
In these cases the exception occurs in the context of the ne w task. The instruction pointer refers to the first instruc-
tion of the new task, not to the instruction which caused the task switch (or the last instruction to be executed, in the case of an interrupt). If the design of the operating system permits control protection faults to occur during 
task-switches, the control protection fault handler should be called through a task gate.6-58 Vol. 3AINTERRUPT AND EXCEPTION HANDLING
Interrupts 32 to 255—User Defined Interrupts
•Executed an INT n instruction where the instruction operand is on e of the vector numbers from 32 through 255.
•Responded to an interrupt request at the INTR pin or from the local APIC when the interrupt vector number 
associated with the request is from 32 through 255.
The saved contents of CS and EIP registers point to the instruction that follows the INT n instruction or instruction 
following the instruction on which the INTR signal occurred.
A program-state change does not accompany interrupts generated by the INT n instruction or the INTR signal. The 
INT n instruction generates the interrupt within the instruction stream. When the processor receives an INTR 
signal, it commits all state changes for all previous instructions before it responds to the interrupt; so, program 
execution can resume upon returning from the interrupt handler.Vol. 3A 7-1CHAPTER 7
7.1 INTRODUCTION
This chapter provides details of an architectural feature called user interrupts .
This feature defines user interrupts as new events in the architecture. User interrupts are delivered to software 
operating in 64-bit mode with CPL = 3 without any change to segmentation state. An individual user interrupt is 
identified by a 6-bit user-interrupt vector, which is push ed on the stack as part of user-interrupt delivery. The 
UIRET (user-interrupt return) instructio n reverses user-interrupt delivery.
System software configures the user-interrupt architectu re with MSRs. An operating system (OS) may update the 
content of some of these MSRs when switching between OS-managed threads.
One of these MSRs references a data structure called the user posted-interrupt  descriptor (UPID) . User inter-
rupts for an OS-managed thread can be posted in the UPID  associated with that thread. Such user interrupts will 
be delivered after receipt of an ordinary interrupt (identified in the UPID) called a user-interrupt notification .1
System software can define operations to post user interru pts and to send user-interrupt notifications. In addition, 
the user-interrupt feature defines the SENDUIPI instructio n, by which application software can send interprocessor 
user interrupts (user IPIs). An execution of SENDUIPI post s a user interrupt in a UPID and may send a user-inter-
rupt notification. 
(Platforms may include mechanisms to process external inte rrupts as either ordinary interrupts or user interrupts. 
Those processed as user interrupts would be posted in UPIDs and may result in user-interrupt notifications. 
Specifics of such mechanisms are outside of the scope of this manual.)

Section 7.2 explains how a processor enumerates support for user interrupts and how they are enabled by system 
software. Section 7.3 identifies the new processor state defined for user interrupts. Section 7.4 explains how a 
processor identifies and delivers user interrupts. Section 7.5 describes how a processor identifies and processes 
user-interrupt notifications. Section 7.6 enumerates new in structions that support management of user interrupts. 
Section 7.7 defines new support for user inter-processor interrupts (user IPIs).
7.2 ENUMERATION AND ENABLING
Software enables user interrupts by setting bit 25 (UINTR) in control regi ster CR4. Setting CR4.UINTR enables 
user-interrupt delivery (Section 7.4.2), user-interrupt notifi cation identification (Section 7.5.1), and the user-inter-
rupt instructions (Section 7.6). It does not affect the accessibility of the user-interrupt MSRs (Section 7.3) by 
RDMSR, WRMSR or the XSAVE feature set.
Processor support for user interrupts is enumerated by CP UID.(EAX=7,ECX=0):EDX [5]. If this bit is set, software 
can set CR4.UINTR to 1 and can access the user-inte rrupt MSRs using RDMSR and WRMSR (see Section 7.3).
The user-interrupt feature is XSAVE-managed (see Sectio n 13.5). This implies that aspects of the feature are 
enumerated as part of enumeration of the XSAV E feature set. See Section 13.5.11 in the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1, for details.
7.3 USER-INTERRUPT STATE AND USER-INTERRUPT MSRS
The user-interrupt architecture defines the following new state. Some of this state can be accessed via the RDMSR 
and WRMSR instructions (through new user-interrupt MSRs detailed in Section 7.3.2) and some can be accessed 
using instructions described in Section 7.6.
1. For clarity, this chapter uses the term ordinary interrupts  to refer to those events  in the existing interrup t architecture, which are 
typically delivered to system software operating with CPL = 0.7-2 Vol. 3AUSER INTERRUPTS
7.3.1 User-Interrupt State
The following are the elements of the user-interrupt st ate (listed here independent of how they are accessed):
•UIRR: user-interrupt request register.
This value includes one bit for each of the 64 user-interrupt vectors. If UIRR[i] = 1, a user interrupt with
vector i is requesting service. The notation UIRRV  is used to refer to the position of the most significant bit
set in UIRR; if UIRR = 0, UIRRV = 0.
•UIF: user-interrupt flag.
If UIF = 0, user-interrupt delivery is blocked; if UIF = 1, user interrupts may be delivered. User-interrupt
delivery clears UIF, and the new UIRET instruction sets it. Section 7.6 defines other instructions for accessing
UIF.
•UIHANDLER: user-interrupt handler.
This is the linear address of the user-interrupt handle r. User-interrupt delivery loads this address into RIP.
•UISTACKADJUST: user-interrupt stack adjustment.
This value controls adjustment to the stack pointer (RSP) prior to user-interrupt delivery. It can be configured
to load RSP with an alternate stack pointer or configured to prevent user -interrupt delivery from overwriting
data above the current stack top.
The value UISTACKADJUST must be canonical. If bit 0 is 1, user-interrupt delivery loads RSP with UISTACK-
ADJUST; otherwise, it subtracts UISTACKADJUST from RS P. Either way, user-interrupt delivery then aligns
RSP to a 16-byte boundary. See Section 7.4.2 for details.
•UINV: user-interrupt notification vector.
This is the vector of the ordinary interrupts that are treated as user-interrupt notifications (Section 7.5.1).
When the logical processor receives user-interrupt notification, it processes the user interrupts in the userposted-interrupt descriptor (UPID) referenced by UPIDADDR (see below and Section 7.5.2).
•UPIDADDR: user posted-interrupt descriptor address.
This is the linear address of the UPID that the logica l processor consults upon receiving an ordinary interrupt
with vector UINV.
•UITTADDR: user-interrupt target table address.
This is the linear address of user-interrupt target table (UITT), which the logical processor consults when
software executes the SENDUIPI instruction (see Section 7.7).
•UITTSZ: user-interrupt target table size.
This value is the highest index of a valid entry in the UITT (see Section 7.7).
7.3.2 User-Interrupt MSRs
Some of the state elements identified in Section 7.3.1 can be accessed as user-interrupt MSRs using the RDMSR 
and WRMSR instructions:
•IA32_UINTR_RR MSR (MSR address 985H). This MSR is an interface to UIRR (64 bits).
Following a WRMSR to this MSR, the logi cal processor recognizes a pending user  interrupt if and only if some bit 
is set in the MSR.
•IA32_UINTR_HANDLER MSR (MSR address 986H). This MSR is  an interface to the UIHANDLER address. This is 
a linear address that must be canonical relative to the maximum linear-address width supported by the 
processor.2 WRMSR to this MSR causes a general-protection fault (#GP) if its source operand does not meet 
this requirement.
•IA32_UINTR_STACKADJUST MSR (MSR address 987H). This MSR is an interface to the UISTACKADJUST value. 
This value includes a linear address that must be canonical relative to the maximum linear-address width 
supported by the processor. WRMSR to this MSR causes  a #GP if its source operand does not meet this 
2. CPUID.80000008H:EAX[15:8] enumerates the maximum linear-address width supported by the processor.Vol. 3A 7-3USER INTERRUPTS
Bit 0 of this MSR corresponds to UI STACKADJUST[0], which controls how user-interrupt delivery updates the 
stack pointer. WRMSR may set it to either 0 or 1.
•IA32_UINTR_MISC MSR (MSR address 988H). This MSR is an interface to the UITTSZ and UINV values. The 
MSR has the following format:
—B i t s  3 1 : 0  a r e  U I T T S Z .— Bits 39:32 are UINV.
— Bits 63:40 are reserved. WRMSR causes a #GP if it would set any of those bits (if 
EDX[31:8] 
≠ 000000H).
Because this MSR will share an 8-byte portion of th e XSAVE area with UIF (see Section 13.5.11 of Intel® 64
and IA-32 Architectures Software Developer’s Manual, Vo lume 1), bit 63 of the MSR will never be used and
will always be reserved.
•IA32_UINTR_PD MSR (MSR address 989H). This MSR is an in terface to the UPIDADDR address. This is a linear 
address that must be canonical relative to the maximum linear-address width supported by the processor. 
WRMSR to this MSR causes a #GP if its source operand does not meet this requirement.
Bits 5:0 of this MSR are reserved. WRMSR causes  a #GP if it would set any of those bits (if 
EAX[5:0] ≠ 000000b).
•IA32_UINTR_TT MSR (MSR address 98AH). This MSR is an interface to the UITTADDR address (in addition, bit 
0 enables SENDUIPI).
Bit 63:4 of this MSR holds the current value of UITTADDR . This a linear address that must be canonical relative 
to the maximum linear-address width supported by the processor. WRMSR to this MSR causes a #GP if its 
source operand does not meet this requirement.
Bits 3:1 of this MSR are reserved. WRMSR causes a #G P if it would set any of those bits (if EAX[3:1] ≠ 000b).
Bit 0 of this MSR determines whether the SENDUIPI instru ction is enabled. WRMSR may set it to either 0 or 1.
7.4 EVALUATION AND DELIVERY OF USER INTERRUPTS
A processor determines whether there is a user interrupt to deliver based on UIRR. Section 7.4.1 describes this 
recognition of pending user interrupts. Once a logical pr ocessor has recognized a pending user interrupt, it will 
deliver it on a subsequent instruction boundary by causing a control-flow change asynchronous to software execu-
tion. Section 7.4.2 details this process of user-interrupt delivery.
7.4.1 User-Interrupt Recognition
There is a user interrupt pending whenever UIRR ≠ 0.
Any instruction or operation that modifies UIRR updates the logical processor’s recognition of a pending user inter-
rupt. The following instructions and operations may do this:
•WRMSR to the IA32_UINTR_RR MSR (Section 7.3).
•XRSTORS of the user-interrupt state component.
•User-interrupt delivery (Section 7.4.2).
•User-interrupt notification processing (Section 7.5.2).
•VMX transitions that lo ad the IA32_UINTR_RR MSR.
Each of these instructions or operations results in reco gnition of a pending user inte rrupt if it completes with 
UIRR ≠ 0; if it completes with UIRR = 0, no pending user interrupt is recognized.
Once recognized, a pending user interrupt may be delivered to software; see Section 7.4.2.7-4 Vol. 3AUSER INTERRUPTS
7.4.2 User-Interrupt Delivery
If CR4.UINTR = 1 and a user interrupt has been recognized (see Section 7.4.1), it will be delivered at an instruction 
boundary when the following conditions all hold: (1) UIF = 1; (2) there is no blocking by MOV SS or by POP SS3; 
(3) CPL = 3; (4) IA32_EFER.LMA = CS.L = 1 (the logical processor is in 64-bit mode); and (5) software is not 
executing inside an enclave.
User-interrupt delivery has priority just below that of or dinary interrupts. It wakes a logical processor from the

User-interrupt delivery has priority just below that of or dinary interrupts. It wakes a logical processor from the 
states entered using the TPAUSE and UMWAIT instructions4; it does not wake a logical processor in the shutdown 
state or in the wait-for-SIPI state.
User-interrupt delivery does not change CPL (it occurs enti rely with CPL = 3). The following pseudocode details the 
behavior of user-interrupt delivery:
IF UIHANDLER is not canonical in current paging mode
FI;holdRSP := RSP;
IF UISTACKADJUST[0] = 1
THEN RSP := UISTACKADJUST;ELSE RSP := RSP – UISTACKADJUST;
FI;RSP := RSP & ~FH;  // force the stack to be 16-byte alignedPush holdRSP;Push RFLAGS;Push RIP;Push UIRRV; // 64-bit push; upper 58 bits pushed as 0IF shadow stack is enabled for CPL = 3
THEN ShadowStackPush RIP;
FI;IF end-branch is enabled for CPL = 3
THEN IA32_U_CET.TRACKER := WAIT_FOR_ENDBRANCH;
FI;UIRR[Vector] := 0;IF UIRR = 0
THEN cease recognition of any pending user interrupt;
FI;UIF := 0;RFLAGS.TF := 0;RFLAGS.RF := 0;RIP := UIHANDLER;
If UISTACKADJUST[0] = 0, user-interrupt delivery decr ements RSP by UISTACKADJUST; otherwise, it loads RSP 
with UISTACKADJUST. In either case, user-interrupt delivery aligns RSP to a 16-byte boundary by clearing 
RSP[3:0].
User-interrupt delivery that occurs during transactional execution causes transactional execution to abort and a 
transition to a non-transactional execution. The transactional abort loads EAX as it would had it been due to an 
ordinary interrupt. User-interrupt delivery occurs after the transactional abort.
3. Execution of the STI instruction does not block delivery of user  interrupts for one instruction as it does ordinary interrupt s. If a user 
interrupt is delivered immediately following execution of a STI instruction, ordinary interrupts are not blocked after delivery  of the 
user interrupt.
4. User-interrupt delivery occurs only if CPL = 3. Since the HLT an d MWAIT instructions can be executed only if CPL = 0, a user in ter-
rupt can never be delivered when a logical processor is an activity state that was entered using one of those instructions.Vol. 3A 7-5USER INTERRUPTS
The stack accesses performed by user-interrupt delivery may incur faults (page faults, or stack faults due to 
canonicality violations). Before such a fault is delivered, RSP is restored to its original value (memory locations above the top of the stack may have been written). If such  a fault produces an error code that uses the EXT bit, 
that bit will be cleared to 0.
If a fault occurs during user-interrupt delivery, UIRR is not updated and UIF is not cleared and, as a result, the 
logical processor continues to recognize that a user interru pt is pending, and user-interrupt delivery will normally 
recur after the fault is handled.
If the shadow-stack feature of control-flow enforcement technology (CET) is enabled for CPL = 3, user-interrupt 
delivery pushes the return instruction pointer on the shadow  stack. If indirect-branch-tracking feature of CET is 
enabled, user-interrupt delivery transitions the indirect  branch tracker to the WAIT_FOR_ENDBRANCH state; an 
ENDBR64 instruction is expected as first instruction of the user-interrupt handler.
User-interrupt delivery can be tracked by Architectural Last Branch Records (LBRs), Intel
® Processor Trace (Intel® 
PT), and Performance Monitoring. For both Intel PT and LBRs , user-interrupt delivery is recorded in precisely the 
same manner as ordinary interrupt delivery. Hence for LBRs, user interrupts fall into the OTHER_BRANCH category, which implies that IA32_LBR_CTL.OTHER_BRANCH[bit 22] must  be set to record user-interrupt delivery, and that 
the IA32_LBR_x_INFO.BR_TYPE field will indicate OTHER_BR ANCH for any recorded user interrupt. For Intel PT, 
control flow tracing must be enabled by setting IA32_RTIT_CTL.BranchEn[bit 13].
User-interrupt delivery will also increment performance counters for which counting 
BR_INST_RETIRED.FAR_BRANCH is enabled. Some implementations may have dedicated events for counting 
user-interrupt delivery; see processor-specific event lists at https://download.01.org/perfmon/index/
.
7.5 USER-INTERRUPT NOTIFICATION  IDENTIFICATION AND PROCESSING
User-interrupt posting  is the process by which a platform agent (or software operating on a CPU) records user 
interrupts in a user posted-interrupt descriptor  (UPID) in memory. The platform agent (or software) may send 
an ordinary interrupt (called a user-interrupt notification ) to the logical processor on which the target of the 
user interrupt is operating.
Table 7-1 gives the format of a UPID.
The notation PIR (posted-interrupt requests) refers to the 64 posted-interrupt requests in a UPID.
If an ordinary interrupt arrives while CR4.UINTR = IA32_ EFER.LMA = 1, the logical processor determines whether 
the interrupt is a user-interrupt notification. This process is called user-interrupt notification identification  
and is described in Section 7.5.1.
Once a logical processor has identified a user-interrupt notification, it copies user interrupts in the UPID’s PIR into 
UIRR. This process is called user-interrupt noti fication processing  and is described in Section 7.5.2.Table 7-1.  Format of User Po sted-Interrupt De scriptor — UPID
Bit Position(s) Name Description
0Outstanding notifi-
cationIf this bit is set, there is a notification outstanding for one or more user interrupts in 
PIR.
1 Suppress notificationIf this bit is set, agents (including SENDUIPI) should not send notifications when 
posting user interrupts in this descriptor.
15:2 ReservedUser-interrupt notification processing ignores these bits; must be zero for 
SENDUIPI.
23:16 Notification vector Used by agents sending us er-interrupt notifications (including SENDUIPI).
31:24 ReservedUser-interrupt notification processing ignores these bits; must be zero for 
SENDUIPI.
63:32 Notification destinationTarget physical APIC ID – used by SENDUIPI.
In xAPIC mode, bits 47:40 are the 8-bit APIC ID.
In x2APIC mode, the entire field forms the 32-bit APIC ID.
127:64Posted-interrupt 
requests (PIR)One bit for each user-interrupt vector. Ther e is a user-interrupt request for a vector 
if the corresponding bit is 1.7-6 Vol. 3AUSER INTERRUPTS
A logical processor is not interruptible during either user-interrupt notification identification or user-interrupt noti-
fication processing or between those operations (when they occur in succession).
7.5.1 User-Interrupt Notification Identification
If CR4.UINTR = IA32_EFER.LMA = 1, a logical processor perfor ms user-interrupt notification identification when it 
receives an ordinary interrupt. The following algorithm de scribes the response by the processor to an ordinary 
maskable interrupt when CR4.UINTR = IA32_EFER.LMA = 15:
1. The local APIC is acknowledged; this provides the processor core with an interrupt vector, V.
2. If V = UINV, the logical processor continues to the next step. Otherwise, an interrupt with vector V is delivered 
normally through the IDT; the remainder of this algo rithm does not apply and user-interrupt notification 
processing does not occur.
3. The processor writes zero to the EOI register in the loca l APIC; this dismisses the interrupt with vector V = UINV 
from the local APIC.
User-interrupt notification identification involves acknow ledgment of the local APIC and thus occurs only when 
ordinary interrupts are not masked.
If user-interrupt notification identification completes st ep #3, the logical processor then performs user-interrupt 
notification processing as described in Section 7.5.2.
An ordinary interrupt that occurs during transactional execution causes the transactional execution to abort and 
transition to a non-transactional execution. This occurs before user-interrupt notification identification.
An ordinary interrupt that occurs while software is executing inside an enclave causes an asynchronous enclave 
exit (AEX). This AEX occurs before user -interrupt notification identification.
7.5.2 User-Interrupt Notification Processing
Once a logical processor has identified a user-interrupt notification, it performs user-interrupt notification 
processing  using the UPID at the linear address in the IA32_UINTR_PD MSR.
The following algorithm describes user-interrupt notification processing:
1. The logical processor clears the outstanding-notification bit (bit 0) in the UPID. This is done atomically so as to 
leave the remainder of the descriptor unmodified.
2. The logical processor reads PIR (bits 127:64 of the UPID) into a temporary register and writes all zeros to PIR. 
This is done atomically so as to ensure that each  bit cleared in PIR is set in the temporary register.
3. If any bit is set in the temporary register, the logical pr ocessor sets in UIRR each bit corresponding to a bit set 
in the temporary register (e.g., with a logical OR) and re cognizes a pending user interrupt (if it has not already 
done so).
The logical processor performs the steps above in an uni nterruptible manner. Steps #1 and #2 may be combined

done so).
The logical processor performs the steps above in an uni nterruptible manner. Steps #1 and #2 may be combined 
into a single atomic step. If step #3 leads to recognitio n of a user interrupt, the processor may deliver that user 
interrupt on the following instruction boundary (see Section 7.4.2).
Although user-interrupt notification processing may occur at any privilege level, all of the memory accesses in 
steps #1 and #2 are performe d with supervisor privilege.
Step #1 and step #2 each access the UPID using a linear address and may therefore incur faults (page faults, or 
general-protection faults due to canonicality violations). If such a fault produces an error code that uses the EXT 
bit, that bit will be set to 1.
If a fault occurs during user-interrupt notification pr ocessing, updates to architectural state performed by the 
earlier user-interrupt notification identification (Section  7.5.1) remain committed and are not undone; if such a 
fault occurs at step #2 (if it is not performed atomically with step #1), any update to architectural state performed 
by step #1 also remains committed. System software is ad vised to prevent such faults (e.g., by ensuring that no 
5. If the interrupt arrives between iterations  of a REP-prefixed string instruction, the processor fi rst updates state as follow s: RIP is 
loaded to reference the string instruction; RCX, RSI, and RDI are updated as appropriate to reflect the iterations completed; a nd 
RFLAGS.RF is set to 1.Vol. 3A 7-7USER INTERRUPTS
page fault occurs and that the linear address in the IA 32_UINTR_PD MSR is canonical with respect to the paging 
mode in use).
If the user-interrupt notification identification that prec edes user-interrupt notification processing occurred due to 
an ordinary interrupt that arrived while the logical processor was in the HLT state, the logical processor returns to the HLT state following user-interrupt notification processing.
7.6 USER-INTERRUPT INSTRUCTIONS
The user-interrupt feature defines instructions for control-flow transfer and access to new state. UIRET is an 
instruction to effect a return from a user-interrupt handler. CLUI, STUI, and TESTUI allow software to access UIF. 
SENDUIPI sends a user IPI. See Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 
2C, & 2D for details on the instructions’ operation.
The following items provide high-lev el overviews of the instructions:
•UIRET pops from the stack the state saved by user-int errupt delivery (see Section 7.4.2) and loads those 
values into the corresponding registers (software should  pop the user-interrupt vector from the stack before 
executing UIRET). Because RIP is one of those registers, UIRET effect a return to the that point from which the 
user interrupt was delivered.
•CLUI clears UIF.
•STUI sets UIF.
•TESTUI copies UIF to RFLAGS.CF.
•SENDUIPI is discussed in Section 7.7.
7.7 USER IPIS
The SENDUIPI instruction sends a user interprocessor interru pt (IPI). The instruction uses a data structure called 
the user-interrupt target table (UITT). This table is lo cated at the linear address UITTADDR and it comprises 
UITTSZ+1 16-byte entries (the values UITTADDR and UITT SZ are defined in Section 7.3.1). SENDUIPI uses the 
UITT entry (UITTE) indexed by the instruction’s regi ster operand. Each UITTE has the following format:
•Bits 127:64: UPIDADDR, the linear address of a UPID  (64-byte aligned, so bits 69:64 must be 0).
SENDUIPI sends a user interrupt by posting a user interru pt with vector V in the UPID referenced by UPIDADDR 
and then sending, as an ordinary IPI, any notification interrupt specified in that UP ID. Details appear in Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D.7-8 Vol. 3AUSER INTERRUPTSVol. 3A 8-1CHAPTER 8
This chapter describes the IA-32 architecture’s task management facilities. These facilities are only available when 
the processor is running in protected mode.
This chapter focuses on 32-bit tasks and the 32-bit TSS structure. For information on 16-bit tasks and the 16-bit 
TSS structure, see Section 8.6, “16-Bit Task-State Segment (TSS).” For information specific to task management in 
64-bit mode, see Section 8.7, “Task Management in 64-bit Mode.”
8.1 TASK MANAGEMENT OVERVIEW
A task is a unit of work that a processor can dispatch, execute, and suspend. It can be used to execute a program, a task or process, an operating-system service utility, an  interrupt or exception handler, or a kernel or executive 
utility.
The IA-32 architecture provides a mechanism for saving the state of a task, for dispatching tasks for execution, and 
for switching from one task to another. When operating in protected mode, all processor execution takes place from within a task. Even simple systems must define at leas t one task. More complex systems can use the processor’s 
task management facilities to support multitasking applications.
8.1.1 Task Structure
A task is made up of two parts: a task execution space and a task-state segment (TSS). The task execution space 
consists of a code segment, a stack segment, and one or  more data segments (see Figure 8-1). If an operating 
system or executive uses the processor’s privilege-level  protection mechanism, the task execution space also 
provides a separate stack for each privilege level.
The TSS specifies the segments that make up the task ex ecution space and provides a storage place for task state 
information. In multitasking systems, the TS S also provides a mechanism for linking tasks.
A task is identified by the segment selector for its TSS. Wh en a task is loaded into the processor for execution, the 
segment selector, base address, limit, and segment descrip tor attributes for the TSS are loaded into the task 
register (see Section 2.4.4, “Task Register (TR)”).
If paging is implemented for the task, the base address of th e page directory used by the task is loaded into control 
register CR3.8-2 Vol. 3ATASK MANAGEMENT
8.1.2 Task State
The following items define the state of the currently executing task:
•The task’s current execution space, defined by the segm ent selectors in the segment registers (CS, DS, SS, ES, 
FS, and GS).
•The state of the general-purpose registers.
•The state of the EFLAGS register.
•The state of the EIP register.
•The state of control register CR3.
•The state of the task register.
•The state of the LDTR register.
•The I/O map base address and I/O map (contained in the TSS).
•Stack pointers to the privilege 0, 1, and 2 stacks (contained in the TSS).
•Link to previously executed task (contained in the TSS).
•The state of the shadow stack pointer (SSP).
Prior to dispatching a task, all of these items are contained in the task’s TSS, except the state of the task register. 
Also, the complete contents of the LDTR register are not contained in the TSS, only the segment selector for the 
LDT.
8.1.3 Executing a Task
Software or the processor can dispatch a task for execution in one of the following ways:
•A explicit call to a task with the CALL instruction.
•A explicit jump to a task with the JMP instruction.
•An implicit call (by the processor) to an interrupt-handler task.
•An implicit call to an exception-handler task.
•A return (initiated with an IRET instruction) wh en the NT flag in the EFLAGS register is set.
All of these methods for dispatching a task identify the task to be dispatched with a segment selector that points to 
a task gate or the TSS for the task. When dispatching a ta sk with a CALL or JMP instruction, the selector in the 
instruction may select the TSS directly or a task gate that holds the selector for the TSS. When dispatching a task Figure 8-1.  Structure of a TaskCode
Segment
Stack
Segment
(Current Priv.Data
Segment
Stack Seg.
Priv. Level 0
Stack Seg.
Priv. Level 1
Stack
Segment
(Priv. Level 2)Task-State
Segment
(TSS)
CR3Level)Vol. 3A 8-3TASK MANAGEMENT
to handle an interrupt or exception, the IDT entry for the interrupt or exception must contain a task gate that holds 
the selector for the interrupt- or exception-handler TSS. 
When a task is dispatched for execution, a task switch occurs between the currently running task and the 
dispatched task. During a task switch, the execution environment of the current ly executing task (called the task’s 
state or context ) is saved in its TSS and execution of the task is suspended. The context for the dispatched task is 
then loaded into the processor and execution of that task begins with the instruction po inted to by the newly loaded 
EIP register. If the task has not been run since the system was last initialized, the EIP will point to the first instruc-
tion of the task’s code; otherwise, it will point to the next instruction after the last instruction that the task 
executed when it was last active.
If the currently executing task (the calling task) calle d the task being dispatched (the called task), the TSS

If the currently executing task (the calling task) calle d the task being dispatched (the called task), the TSS 
segment selector for the calling task is stored in the TSS of  the called task to provide a link back to the calling task.
For all IA-32 processors, tasks are not recursive. A task cannot call or jump to itself.
Interrupts and exceptions can be handled with a task switch  to a handler task. Here, the processor performs a task 
switch to handle the interrupt or exception and automatica lly switches back to the interrupted task upon returning 
from the interrupt-handler task or exception-handler task . This mechanism can also handle interrupts that occur 
during interrupt tasks.
As part of a task switch, the processor can also switch to another LDT, allowing each task to have a different logical-
to-physical address mapping fo r LDT-based segments. The page -directory base register (CR3) also is reloaded on a 
task switch, allowing each task to have its own set of pa ge tables. These protection facilities help isolate tasks and 
prevent them from interf ering with one another. 
If protection mechanisms are not used, the processor provides  no protection between tasks. This is true even with 
operating systems that use multiple privilege levels for prot ection. A task running at priv ilege level 3 that uses the 
same LDT and page tables as other privilege-level-3 tasks can access code and corrupt data and the stack of other 
tasks.
Use of task management facilities for handling multitasking applications is optional. Multitasking can be handled in 
software, with each software defined task executed in the context of a single IA-32 architecture task.
If shadow stack is enabled, then the SSP of the task is located at the 4 bytes at offset 104 in the 32-bit TSS and is 
used by the processor to establish the SSP when a task swit ch occurs from a task associated with this TSS. Note 
that the processor does not write the SSP of the task initia ting the task switch to the TSS of that task, and instead 
the SSP of the previous task is pushed onto the shadow stack of the new task.
8.2 TASK MANAGEMENT DATA STRUCTURES
The processor defines five data structures for handling task-related activities:
•Task-state segment (TSS).
•TSS descriptor.
•Task register.
•NT flag in the EFLAGS register.
When operating in protected mode, a TSS and TSS descrip tor must be created for at least one task, and the 
segment selector for the TSS must be loaded into the task register (using the LTR instruction).
8.2.1 Task-State Segment (TSS)
The processor state information needed to restore a task  is saved in a system segment called the task-state 
segment (TSS). Figure 8-2 shows the format of a TSS for tasks designed for 32-bit CPUs. The fields of a TSS are 
divided into two main categories: dynamic fields and static fields.
For information about 16-bit Intel 286 processor task st ructures, see Section 8.6, “16-Bit Task-State Segment 
(TSS).” For information about 64-bit mode task structures, see Section 8.7, “Task Management in 64-bit Mode.”8-4 Vol. 3ATASK MANAGEMENT
The processor updates dynamic fields when a task is su spended during a task switch. The following are dynamic 
fields:
•General-purpose register fields — State of the EAX, ECX, EDX, EBX, ESP, EBP, ESI, and EDI registers prior 
to the task switch.
•Segment selector fields — Segment selectors stored in the ES, CS, SS, DS, FS, and GS registers prior to the 
•EFLAGS register field — State of the EFLAGS register prior to the task switch.Figure 8-2.  32-Bit Task-State Segment (TSS)LDT Segment Selector Reserved0 15 31
96
GS Reserved 98
FS Reserved 88
DS Reserved 84
SS Reserved 80
CS Reserved 76
ES Reserved 72
EDI 68
ESI 64
EBP 60
ESP 56
EBX 52
EDX 48
ECX 44
EAX 40
EFLAGS 36
EIP 32
CR3 (PDBR) 28
SS2 Reserved 24
ESP2 20
SS1 Reserved 16
ESP1 12
SS0 Reserved 8
ESP0 4
Previous Task Link Reserved 0
Reserved bits. Set to 0.Reserved I/O Map Base Address T104
100SSPVol. 3A 8-5TASK MANAGEMENT
•EIP (instruction pointer) field — State of the EIP register prior to the task switch.
•Previous task link field — Contains the segment selector for the TSS of the previous task (updated on a task 
switch that was initiated by a call, interrupt, or exceptio n). This field (which is sometimes called the back link 
field) permits a task switch back to the previous task by using the IRET instruction.
The processor reads the static fields, but does not normally  change them. These fields are set up when a task is 
created. The following are static fields:
•LDT segment selector field — Contains the segment selector for the task's LDT.
•CR3 control register field — Contains the base physical address of the page directory to be used by the task. 
Control register CR3 is also known as the page-directory base register (PDBR).
•Privilege level-0, -1, and -2 stack pointer fields — These stack pointers consist of a logical address made 
up of the segment selector for the stack segment (SS0, SS1, and SS2) and an offset into the stack (ESP0, 
ESP1, and ESP2). Note that the values in these fields ar e static for a particular task; whereas, the SS and ESP 
values will change if stack switching occurs within the task.
•T (debug trap) flag (byte 100, bit 0)  — When set, the T flag causes the processor to raise a debug exception 
when a task switch to this task occurs (see Se ction 18.3.1.5, “Task-Switch Exception Condition”).
•I/O map base address field — Contains a 16-bit offset from the base of the TSS to the I/O permission bit 
map and interrupt redirection bitmap. When present, these maps are stored in the TSS at higher addresses. 
The I/O map base address points to the beginning of th e I/O permission bit map and the end of the interrupt 
redirection bit map. See Chapter 19, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1, for more information about the I/O permission bit map. See Section 21.3, 
“Interrupt and Exception Handling in Virtual-8086 Mode,”  for a detailed description of the interrupt redirection 
bit map.
•Shadow Stack Pointer (SSP) — Contains task's shadow stack pointer. The shadow stack of the task should 
have a supervisor shadow stack token at the address pointe d to by the task SSP (offset 104). This token will be 
verified and made busy when switching to that shadow  stack using a CALL/JMP instruction, and made free 
when switching out of that task using an IRET instruction.
If paging is used: 
•Pages corresponding to the previous task’s TSS, the cu rrent task’s TSS, and the descriptor table entries for 
each all should be marked as read/write. 
•Task switches are carried out faster if the pages contai ning these structures are present in memory before the 
task switch is initiated.
8.2.2 TSS Descriptor
The TSS, like all other segments, is defined by a segment descriptor. Figure 8-3 shows the format of a TSS 
descriptor. TSS descriptors may only be placed in the GDT; they cannot be placed in an LDT or the IDT. 
An attempt to access a TSS using a segment selector with it s TI flag set (which indicates the current LDT) causes 
a general-protection exception (#GP) to be generated during CALLs and JMPs; it causes an invalid TSS exception (#TS) during IRETs. A general-protection exception is al so generated if an attempt is made to load a segment 
selector for a TSS into a segment register.
The busy flag (B) in the type field indi cates whether the task is busy. A busy ta sk is currently running or suspended. 
A type field with a value of 1001B indicates an inactive task; a value of 1011B indicates a busy task. Tasks are not 
recursive. The processor uses the busy flag to detect an attempt to call a task whose execution has been inter-
rupted. To ensure that there is only one busy flag is a ssociated with a task, each TSS should have only one TSS 
descriptor that points to it.8-6 Vol. 3ATASK MANAGEMENT
The base, limit, and DPL fields and the granularity and present flags have functions similar to their use in data-
segment descriptors (see Section 3.4.5, “Segment Descripto rs”). When the G flag is 0 in a TSS descriptor for a 32-
bit TSS, the limit field must have a value equal to or gr eater than 67H, one byte less than the minimum size of a 
TSS. Attempting to switch to a task whose TSS descriptor has a limit less than 67H generates an invalid-TSS excep-
tion (#TS). A larger limit is required if an I/O permission bit map is included or if the operating system stores addi-
tional data. The processor does not check for a limit grea ter than 67H on a task switch; however, it does check 
when accessing the I/O permission bit map or interrupt redirection bit map.
Any program or procedure with access to a TSS descriptor (that is, whose CPL is numerically equal to or less than 
the DPL of the TSS descriptor) can dispatch the task with a call or a jump. 
In most systems, the DPLs of TSS descriptors are set to va lues less than 3, so that only privileged software can 
perform task switching. However, in multitasking applications, DPLs for some TSS descriptors may be set to 3 to

perform task switching. However, in multitasking applications, DPLs for some TSS descriptors may be set to 3 to 
allow task switching at the application (or user) privilege level.
8.2.3 TSS Descriptor in 64-bit mode
In 64-bit mode, task switching is no t supported, but TSS descriptors still ex ist. The format of a 64-bit TSS is 
described in Section 8.7. 
In 64-bit mode, the TSS descriptor is expanded to 16 byte s (see Figure 8-4). This expansion also applies to an LDT 
descriptor in 64-bit mode. Table 3-2 provides the encoding information for the segment type field.Figure 8-3.  TSS Descriptor31 24232221 20 19 16 15 1314 12 11 87 0
P
LType
00
31 1615 0
Base Address 15:00 Segment Limit 15:00Base 23:16A
V
LLimit
19:160
1B01TSS Descriptor
AVL
BBASE
DPL
GAvailable for use by system software
Busy flagSegment Base Address
Descriptor Privilege Level
LIMITPTYPESegment Limit
Segment PresentSegment Type04Vol. 3A 8-7TASK MANAGEMENT
8.2.4 Task Register
The task register holds the 16-bit segment selector and th e entire segment descriptor (32-bit base address (64 bits 
in IA-32e mode), 16-bit segment limit, and descriptor attr ibutes) for the TSS of the current task (see Figure 2-6). 
This information is copied from the TSS descriptor in th e GDT for the current task. Figure 8-5 shows the path the 
processor uses to access the TSS (using the information in the task register).
The task register has a visible part (that can be read and changed by software) and an invisible part (maintained 
by the processor and is inaccessible by software). The se gment selector in the visible portion points to a TSS 
descriptor in the GDT. The processor uses the invisible port ion of the task register to cache the segment descriptor 
for the TSS. Caching these values in a register makes ex ecution of the task more efficient. The LTR (load task 
register) and STR (store task register) instructions load and read the visible portion of the task register: 
The LTR instruction loads a segment selector (source operand) into the task register that points to a TSS descriptor 
in the GDT. It then loads the invisible portion of the task register with information from the TSS descriptor. LTR is a privileged instruction that may be executed only when the CPL is 0. It’s used during system initialization to put an 
initial value in the task register. Afterwards, the contents of the task register are changed implicitly when a task 
switch occurs.
The STR (store task register) instruction stores the visible portion of the task register in a general-purpose register 
or memory. This instruction can be executed by code running at any privilege level in order to identify the currently running task. However, it is normally used only by operating system software. (If CR4.UMIP = 1, STR can be 
executed only when CPL = 0.)
On power up or reset of the processor, segment selector and base address are set to the default value of 0; the limit 
is set to FFFFH.Figure 8-4.  Format of TSS an d LDT Descriptors in 64-bit Mode31 24232221 20 19 16 15 1314 12 11 87 0
P
LType
00
31 1615 0
V
LLimit
19:160TSS (or LDT) Descriptor
AVL
BBASEDPLGAvailable for use by system software
Busy flagSegment Base AddressDescriptor Privilege LevelGranularity
LIMITP
TYPESegment Limit
Segment PresentSegment Type0431 1312 87 0
Reserved
31 0
Base Address 63:32Reserved 0
8128-8 Vol. 3ATASK MANAGEMENT
8.2.5 Task-Gate Descriptor
A task-gate descriptor provides an indirect, protected refere nce to a task (see Figure 8-6). It can be placed in the 
GDT, an LDT, or the IDT. The TSS segment selector field in a task-gate descriptor points to a TSS descriptor in the 
GDT. The RPL in this segment selector is not used.
The DPL of a task-gate descriptor controls access to the TSS descriptor during a task switch. When a program or 
procedure makes a call or jump to a task through a task gate, the CPL and the RPL field of the gate selector pointing 
to the task gate must be less than or equal to the DPL of  the task-gate descriptor. Note  that when a task gate is 
used, the DPL of the destination TSS descriptor is not used.Figure 8-5.  Task Register
Figure 8-6.  Task-Gate DescriptorSegment Limit Selector+
GDT
0Base AddressTaskInvisible Part Visible PartTSS
Register
31 1615 1314 12 11 87 0
PD
P
LType
0
31 1615 0
TSS Segment Selector1010
DPL
PTYPEDescriptor Privilege Level
Segment PresentSegment Type4
0 ReservedReserved ReservedVol. 3A 8-9TASK MANAGEMENT
A task can be accessed either through a task-gate descriptor or a TSS descriptor. Both of these structures satisfy 
the following needs:
•Need for a task to have only one busy fla g — Because the busy flag for a task is stored in the TSS 
descriptor, each task should have only one TSS descrip tor. There may, however, be several task gates that 
reference the same TSS descriptor. 
•Need to provide selective access to tasks — Task gates fill this need, becaus e they can reside in an LDT and 
can have a DPL that is different from the TSS descript or's DPL. A program or procedure that does not have 
sufficient privilege to access the TSS descriptor for a ta sk in the GDT (which usually has a DPL of 0) may be 
allowed access to the task through a task gate with a hi gher DPL. Task gates give the operating system greater 
latitude for limiting access to specific tasks.
•Need for an interrupt or exception to  be handled by an independent task — Task gates may also reside 
in the IDT, which allows interrupts and exceptions to be handled by handler tasks. When an interrupt or 
exception vector points to a task gate, the processor switches to the specified task.
Figure 8-7 illustrates how a task gate in an LDT, a task gate  in the GDT, and a task gate in the IDT can all point to 
the same task.
8.3 TASK SWITCHING
The processor transfers execution to another task in one of four cases:
•The current program, task, or procedure executes a JMP or CALL instruction to a TSS descriptor in the GDT.
•The current program, task, or procedure executes a JM P or CALL instruction to a task-gate descriptor in the 
GDT or the current LDT.Figure 8-7.  Task Gates Referencing the Same TaskLDT
Task GateTSS GDT
IDT
Task GateTask Gate8-10 Vol. 3ATASK MANAGEMENT
•The current task executes an IRET when the NT flag in the EFLAGS register is set. 
JMP, CALL, and IRET instructions, as well as interrupt s and exceptions, are all mechanisms for redirecting a 
program. The referencing of a TSS descriptor or a task gate  (when calling or jumping to a task) or the state of the 
NT flag (when executing an IRET instruction) determines whether a task switch occurs.
The processor performs the following oper ations when switching to a new task:
1. Obtains the TSS segment selector for the new task as th e operand of the JMP or CALL instruction, from a task 
gate, or from the previous task link field (for a task switch initiated with an IRET instruction).
2. Checks that the current (old) task is allowed to switch  to the new task. Data-access privilege rules apply to JMP 
and CALL instructions. The CPL of the current (old) task  and the RPL of the segment selector for the new task 
must be less than or equal to the DPL of the TSS de scriptor or task gate being referenced. Exceptions, 
interrupts (except for those identified in the next senten ce), and the IRET and INT1 instructions are permitted 
to switch tasks regardless of the DPL of the destination task-gate or TSS descriptor. For interrupts generated by 
the INT n, INT3, and INTO instructions, the DPL is checked an d a general-protection exception (#GP) results if 
it is less than the CPL.1
3. Checks that the TSS descriptor of the new task is marked present and has a valid limit (greater than or equal 
to 67H). If the task switch was initiated by IRET and shadow stacks are enabled at the current CPL, then the 
SSP must be aligned to 8 bytes, else a #TS(current task TSS) fault is generated. If CR4.CET is 1, then the TSS 
must be a 32 bit TSS and the limit of the new task’s TS S must be greater than or equal to 107 bytes, else a 
#TS(new task TSS) fault is generated.
4. Checks that the new task is available (call, ju mp, exception, or interrupt) or busy (IRET return).
5. Checks that the current (old) TSS, new TSS, and all segm ent descriptors used in the task switch are paged into 
6. Saves the state of the current (old) task in the current task’s TSS. The processor finds the base address of the 
current TSS in the task register and then copies the states  of the following registers into the current TSS: all the 
general-purpose registers, segment selectors from the segment registers, the temporarily saved image of the 
EFLAGS register, and the instruction pointer register (EIP).
7. Loads the task register with the segment selector and descriptor for the new task's TSS.
8. If CET is enabled, the processor pe rforms following shadow stack actions:

Read CS of new task from new task TSSRead EFLAGS of new task from new task TSSIF EFLAGS.VM = 1
THEN
new task CPL = 3;
ELSE
new task CPL = CS.RPL;
FI;pushCsLipSsp = 0IF task switch was initiated by CALL  instruction, exception or interrupt
IF shadow stack enabled at current CPL
IF new task CPL < CPL and current task CPL = 3
THEN
IA32_PL3_SSP = SSP (* user 
→ supervisor *)
ELSE
pushCsLipSsp = 1 (* no privilege change; supv → supv; supv → user *) tempSSP = SSP
1. The INT1 has opcode F1; the INT n instruction with n=1 has opcode CD 01.Vol. 3A 8-11TASK MANAGEMENT
tempSsLIP =CSBASE + EIP
tempSsCS = CS
FI;
FI;
FI;verifyCsLIP = 0IF task switch was initiated by IRET
IF shadow stacks enabled at current CPL
IF (CPL of new Task = CPL of current Task) OR
(CPL of new Task < 3 AND CPL of current Task < 3) OR(CPL or new Task < 3 AND CPL of current task = 3)
(* no privilege change or supervisor 
→ supervisor or user → supervisor IRET *)
tempSsCS = shadow_stack_load 8 bytes from SSP+16;tempSsLIP = shadow_stack_load 8 bytes from SSP+8;tempSSP = shadow_stack_load 8 bytes from SSP;SSP = SSP + 24;verifyCsLIP = 1
FI;// Clear busy flag on current shadow stack IF ( SSP & 0x07 == 0 ) (* SSP must be aligned to 8B *)
THEN
            expected_token_value = (SSP & ~0x07) | BUSY_BIT;  (* busy - bit 0 - must be set*)            new_token_value          = SSP                                          (* clear the busy bit *)            shadow_stack_lock_cmpxchg8 b(SSP, new_token_value, expected_token_value)
        FI;
SSP = 0
FI;
FI;
9. The TSS state is loaded into the processor. This includes  the LDTR register, the PDBR (control register CR3), the 
EFLAGS register, the EIP register, the general-purpose registers, and the segment selectors. A fault during the load of this state may corrupt architectural state. (If pa ging is not enabled, a PDBR value is read from the new 
task's TSS, but it is not loaded into CR3.)
10. If the task switch was initiated with a JMP or IRET in struction, the processor clears the busy (B) flag in the 
current (old) task’s TSS descriptor; if initiated with a CA LL instruction, an exception, or an interrupt: the busy 
(B) flag is left set. (See Table 8-2.)
11. If the task switch was initiated with an IRET instructio n, the processor clears the NT flag in a temporarily saved 
image of the EFLAGS register; if initiated with a CALL or JMP instruction, an exception, or an interrupt, the NT 
flag is left unchanged in the saved EFLAGS image.
12. If the task switch was initiated with a CALL instruction,  an exception, or an interrupt, the processor will set the 
NT flag in the EFLAGS loaded from th e new task. If initiated with an IRET instruction or JMP instruction, the NT 
flag will reflect the state of NT in the EFLAGS loaded from the new task (see Table 8-2).
13. If the task switch was initiated with  a CALL instruction, JMP instruction, an exception, or an interrupt, the 
processor sets the busy (B) flag in the new task’s TSS descr iptor; if initiated with an IRET instruction, the busy 
(B) flag is left set.
14. The descriptors associated with the segment selectors are loaded and qualified. Any errors associated with this 
loading and qualification occur in the context of the new task and may corrupt architectural state.8-12 Vol. 3ATASK MANAGEMENT
15. If CET is enabled, the processor pe rforms following shadow stack actions:
IF shadow stack enabled at current CPL OR indirect branch tracking at current CPL
THEN
IF EFLAGS.VM = 1
THEN #TSS(new-Task-TSS);FI;
FI;IF shadow stack enabled at current CPL
IF task switch initiated by CALL instruction, JMP in struction, interrupt or exception (* switch stack *)
new_SSP 
← Load the 4 byte from offset 104 in the TSS
// Verify new SSP to be legalIF new_SSP & 0x07 != 0
THEN #TSS(New-Task-TSS); FI;
expected_token_value = SSP;                     (* busy - bit 0 - must be clear *)new_token_value          = SSP | BUSY_BIT (* set the busy bit - bit 0*)
    IF shadow_stack_lock_cmpxchg8b(SSP, new_token_value,                                                                    expected_token_value) != expected_token_value         THEN #TSS(New-Task-TSS); FI;
SSP = new_SSPIF pushCsLipSsp = 1 (* call, int, exception from user 
→ user or supv → supv or supv → user *)
Push tempSsCS, tempSsLip, tempSsSSP on shadow stack using 8B pushes2
FI;
FI;
FI;IF task switch initiated by IRET
IF verifyCsLIP = 1
(* do 64 bit comparisons; CS zero padded to 64 bit; CSBASE+EIP zero padded to 64 bit *)
IF tempSsCS and tempSsLIP do  not match CS and CSBASE+EIP
THEN
IF (verifyCsLIP == 0) tempSSP = IA32_PL3_SSP;
IF tempSSP & 0x03 != 0 THEN #CP(FAR- RET/IRET) // verify aligned to 4 bytes
IF tempSSP[63:32] != 0 THEN # CP(FAR-RET/IRET)
SSP = tempSSP
FI;
IF task switch initiated by CALL instructio n, JMP instruction, interrupt or exception
IF CPL = 3
THEN
2. If any of these pushes leads to an exception or a VM exit, the supervisor shadow -stack token remains busy.Vol. 3A 8-13TASK MANAGEMENT
ELSE
FI;
FI;
FI;
16. Begins executing the new task. (To an exception handler, the first instruction of the new task appears not to 
have been executed.)
NOTES
If all checks and saves have been carried out successfully, the processor commits to the task 
switch. If an unrecoverable error occurs in steps 1 through 8, the processor does not complete the 
task switch and ensures that the processor is returned to its state prior to the execution of the 
instruction that initiated the task switch.
If an unrecoverable error occurs in step 9, arch itectural state may be corrupted, but an attempt will 
be made to handle the error in the prior executio n environment. If an unrecoverable error occurs 
after the commit point (in step 13), the processor completes the task switch (without performing 
additional access and segment availability checks) and generates the appropriate exception prior to 
beginning execution of the new task.
If exceptions occur after the commit point, the exce ption handler must finish the task switch itself 
before allowing the processor to begin executing the new task. See Chapter 6, “Interrupt 
10—Invalid TSS Exception (#TS),” for more information about the affect of exceptions on a task when they occur after the commit point of a task switch.
The state of the currently executing task is always saved when a successful task switch occurs. If the task is 
resumed, execution starts with the instruction pointed to by the saved EIP value, and the registers are restored to 
the values they held when the task was suspended.
When switching tasks, the privilege level of the new task  does not inherit its privilege level from the suspended 
task. The new task begins executing at the privilege level specified in the CPL field of the CS register, which is 
loaded from the TSS. Because tasks are isolated by thei r separate address spaces and TSSs and because privilege 
rules control access to a TSS, software does not need to perform explicit privilege checks on a task switch.
Table 8-1 shows the exception conditions that the processo r checks for when switching tasks. It also shows the 
exception that is generated for each check if an error is  detected and the segment that the error code references. 
(The order of the checks in the table is the order used in the P6 family processors. The exact order is model specific 
and may be different for other IA-32 processors.) Exceptio n handlers designed to hand le these exceptions may be 
subject to recursive calls if they atte mpt to reload the segment selector that  generated the exception. The cause of 
the exception (or the first of multiple causes) should be fixed before reloading the selector.
Table 8-1.  Exception Conditions Checked During a Task Switch 
Condition Checked Exception1Error Code Reference2
Segment selector for a TSS descriptor references 
the GDT and is within th e limits of  the table.#GP
#TS (for IRET)New Task’s TSS
P bit is set in TSS descriptor. #NP New Task’s TSS
TSS descriptor is not busy (for task switch initiated by a call, interrupt, or 
exception).#GP (for JMP, CALL, INT) Task’s back-link TSS
TSS descriptor is not busy (for task switch initiated by an IRET instruction). #TS  (for IRET) New Task’s TSS
TSS segment limit greater than  or equal to 108 (for 32-bit TSS) or 44 (for 16-bit 
TSS).#TS New Task’s TSS8-14 Vol. 3ATASK MANAGEMENT
The TS (task switched) flag in the control register CR0 is set every time a task switch occurs. System software uses 
the TS flag to coordinate the actions of floating-point unit  when generating floating-point exceptions with the rest 
of the processor. The TS flag indicates that the context of  the floating-point unit may be different from that of the

of the processor. The TS flag indicates that the context of  the floating-point unit may be different from that of the 
current task. See Section 2.5, “Control Registers,” for a deta iled description of the function and use of the TS flag.TSS segment limit grea ter than or equal to 108 (for  32-bit TSS) if CR4.CET = 1.3#TS New Task’s TSS
If shadow stack enabled and SSP not aligne d to 8 bytes (for task switch initiated 
by an IRET instruction).3#TS Current Task’s TSS
Registers are loaded from the values in the TSS.
LDT segment selector of  new task is valid 4. #TS New Task’s LDT
If code segment is non-conf orming, its DPL should equal its RPL. #TS New Code Segment
If code segment is confor ming, its DPL should be le ss than or equal to its RPL. #TS New Code Segment
SS segment selector is valid 2. #TS New Stack Segment
P bit is set in stack segment descriptor. #SS New Stack Segment
Stack segment DPL should equal CPL. #TS New stack segmentP bit is set in new task's LDT descriptor. #TS New Task’s LDT
CS segment selector is valid 
4. #TS New Code Segment
P bit is set in code segment descriptor. #NP New Code SegmentStack segment DPL should equal its RPL. #TS New Stack SegmentDS, ES, FS, and GS segm ent selectors are valid 
4. #TS New Data Segment
DS, ES, FS, and GS segments are readable. #TS New Data SegmentP bits are set in descriptors of DS, ES, FS, and GS segments. #NP New Data SegmentDS, ES, FS, and GS segment DPL greater than or equal to CPL (unless these are 
conforming segments).#TS New Data Segment
Shadow Stack Pointer in a task  not aligned to 8 bytes (for  task switch initiated by 
a call, interrupt, or exception).
3#TS New Task’s TSS
If EFLAGS.VM=1 and shadow stacks are enabled.3#TS New Task’s TSS
Supervisor Shadow Stack Token verification failures (for task switch initiated by a 
call, interrupt, jump, or exception):3
- Busy bit already set.
- Address in Shadow stack token does not match SSP value from TSS.#TS New Task’s TSS
If task switch initiated by IRET, CS and LIP stored on old task shadow stack does 
not match CS and LIP of new task.3#CP FAR-RET/IRET
If task switch initiated by IRET and SSP of new task loaded from shadow stack of 
old task (if new task CPL is < 3) OR th e SSP from IA32_PL3_SSP (if new task CPL 
= 3) fails the following checks:3
- Not aligned to 4 bytes.
- Is beyond 4G.#CP FAR-RET/IRET
NOTES:
1. #NP is segment-not-present exception, #GP is general-protection  exception, #TS is invalid-TSS exception, and #SS is stack-fau lt 
2. The error code contains an index to the segment descriptor referenced in this column.
3. Valid when CET is enabled.
4. A segment selector is valid if it is in a compatible type of table (GDT or LDT), occupies an address within the table's segme nt limit, 
and refers to a compatible type of descriptor (for example, a se gment selector in the CS register  only is valid when it points to a 
code-segment descriptor).Table 8-1.  Exception Conditions Chec ked During a Task Switch  (Contd.)
Condition Checked Exception1Error Code Reference2Vol. 3A 8-15TASK MANAGEMENT
8.4 TASK LINKING
The previous task link field of the TS S (sometimes called the “backlink”) and the NT flag in the EFLAGS register are 
used to return execution to the previous task. EFLAGS.NT = 1 indicates that the currently executing task is nested 
within the execution of another task. 
When a CALL instruction, an interrupt , or an exception causes a task switch: the processor copies the segment 
selector for the current TSS to the previous task link fiel d of the TSS for the new task; it then sets EFLAGS.NT = 1. 
If software uses an IRET instruction to suspend the new task, the processor checks for EFLAGS.NT = 1; it then 
uses the value in the previous task link field to  return to the previous task. See Figures 8-8.
When a JMP instruction causes a task switch, the new task is  not nested. The previous task link field is not used and 
EFLAGS.NT = 0. Use a JMP instruction to dispatch a new task when nesting is not desired.
Table 8-2 shows the busy flag (in the TSS segment descriptor), the NT flag, the previous task link field, and TS flag 
(in control register CR0) during a task switch.
The NT flag may be modified by software executing at any privilege level. It is possible for a program to set the NT 
flag and execute an IRET instruction. This might randomly invoke the task specified in the previous link field of the 
current task's TSS. To keep such spurious task switches from succeeding, the operating system should initialize the 
previous task link field in every TSS that it creates to 0.Figure 8-8.  Nested Tasks
Table 8-2.  Effect of a Task Swit ch on Busy Flag, NT Flag, Previous Task Link Field, and TS Flag
Flag or Field Effect of JMP instruct ion Effect of CALL Instruction or 
InterruptEffect of IRET
Busy (B) flag of new task. Fla g is set. Must have been 
clear before.Flag is set. Must have been 
clear before.No change. Must have been set.
Busy flag of old task. Flag is cleared. No change. Flag is currently 
set.Flag is cleared.
NT flag of new task. Set to value from TSS of new 
task.Flag is set. Set to va lue from TSS of new 
task.
NT flag of old task. No change. No change. Flag is cleared.Previous task link field of new 
task.No change. Loaded with selector 
for old task’s TSS.No change.
Previous task link field of old 
task.No change. No change. No change.
TS flag in control register CR0. Flag  is set. Flag is set. Flag is set.Top Level
Task
NT=0
PreviousTSSNested
Task
NT=1TSSMore Deeply
Nested Task
NT=1TSSCurrently Executing
Task
NT=1EFLAGS
Task Register Task LinkPrevious
Task LinkPrevious
Task Link8-16 Vol. 3ATASK MANAGEMENT
8.4.1 Use of Busy Flag To Prevent Recursive Task Switching
A TSS allows only one context to be saved for a task; ther efore, once a task is called (dispatched), a recursive (or 
re-entrant) call to the task would cause the current state of the task to be lost. The busy flag in the TSS segment 
descriptor is provided to prevent re-entrant task switch ing and a subsequent loss of task state information. The 
processor manages the busy flag as follows:
1. When dispatching a task, the processor sets the busy flag of the new task.2. If during a task switch, the current task is placed in a nested chain (the task switch is being generated by a 
CALL instruction, an interrupt, or an exception), the busy flag for the current task remains set. 
3. When switching to the new task (initiated by a CALL  instruction, interrupt, or exception), the processor 
generates a general-protection exception (#GP) if the busy fl ag of the new task is already set. If the task switch 
is initiated with an IRET instruction, the exception is not raised because the processor expects the busy flag to 
be set.
4. When a task is terminated by a jump to a new task (ini tiated with a JMP instruction in the task code) or by an 
IRET instruction in the task code, the processor clears th e busy flag, returning the task to the “not busy” state.
The processor prevents recursive task switching by preventing  a task from switching to itself or to any task in a 
nested chain of tasks. The chain of nested suspended task s may grow to any length, due to multiple calls, inter-
rupts, or exceptions. The busy flag prevents a task from being invoked if it is in this chain.
The busy flag may be used in multiprocessor configuratio ns, because the processor follows a LOCK protocol (on the 
bus or in the cache) when it sets or clears the busy fl ag. This lock keeps two processors from invoking the same 
task at the same time. See Section 9.1.2.1, “Automatic Lo cking,” for more information about setting the busy flag 
in a multiprocessor applications.
8.4.2 Modifying Task Linkages
In a uniprocessor system, in situations where it is necessary  to remove a task from a chain of linked tasks, use the 
following procedure to remove the task:
1. Disable interrupts.2. Change the previous task link field in the TSS of the pre-empting task (the task that suspended the task to be 
removed). It is assumed that the pre-em pting task is the next task (newer task) in the chain from the task to 
be removed. Change the previous task link field to point to  the TSS of the next oldest task in the chain or to an 
even older task in the chain.
3. Clear the busy (B) flag in the TSS segment descriptor fo r the task being removed from the chain. If more than 
one task is being removed from the chain, the busy flag for each task being remove must be cleared.
4. Enable interrupts.
In a multiprocessing system, additional synchronization an d serialization operations must be added to this proce-
dure to ensure that the TSS and its segment descriptor are both locked when the previous task link field is changed 
and the busy flag is cleared.
8.5 TASK ADDRESS SPACE
The address space for a task consists of the segments th at the task can access. These segments include the code, 
data, stack, and system segments referenced in the TS S and any other segments accessed by the task code. The

data, stack, and system segments referenced in the TS S and any other segments accessed by the task code. The 
segments are mapped into the processor’s linear address spac e, which is in turn mapped into the processor’s phys-
ical address space (either directly or through paging).
The LDT segment field in the TSS can be used to give each  task its own LDT. Giving a task its own LDT allows the 
task address space to be isolated from other tasks by placing the segment descriptors for all the segments associ-
ated with the task in the task’s LDT.
It also is possible for several tasks to use the same LDT. This is a memory-efficient way to allow specific tasks to 
communicate with or control each other, without dropping the protection barriers for the entire system.Vol. 3A 8-17TASK MANAGEMENT
Because all tasks have access to the GDT, it also is poss ible to create shared segm ents accessed through segment 
descriptors in this table.
If paging is enabled, the CR3 register (PDBR) field in the TSS allows each task to have its own set of page tables 
for mapping linear addresses to physical addresses. Or , several tasks can share the same set of page tables.
8.5.1 Mapping Tasks to the Linear and Physical Address Spaces
Tasks can be mapped to the linear address space and physical address space in one of two ways:
•One linear-to-physical address space ma pping is shared among all tasks. — When paging is not 
enabled, this is the only choice. Without paging, all line ar addresses map to the same physical addresses. When 
paging is enabled, this form of linear-to-physical address space mapping is obtained by using one page 
directory for all tasks. The linear address space may ex ceed the available physical space if demand-paged 
virtual memory is supported.
•Each task has its own linear address space th at is mapped to the physical address space. — This form 
of mapping is accomplished by using a different page directory for each task. Because the PDBR (control 
register CR3) is loaded on task switches, each task may have a different page directory.
The linear address spaces of different tasks may map to co mpletely distinct physical addresses. If the entries of 
different page directories point to different page tables and the page tables point to different pages of physical 
memory, then the tasks do not share physical addresses.
With either method of mapping task linear address spaces, the TSSs for all tasks must lie in a shared area of the 
physical space, which is accessible to all tasks. This mapp ing is required so that the mapping of TSS addresses does 
not change while the processor is reading and updating the TSSs during a task switch. The linear address space 
mapped by the GDT also should be mapped to a shared area  of the physical space; otherwise, the purpose of the 
GDT is defeated. Figure 8-9 shows how the linear address spac es of two tasks can overlap in the physical space by 
sharing page tables. 
Figure 8-9.  Overlapping Linear-to-Physical MappingsTask ATSS
PDEPage Directories
PDEPTE
PTE
PTE
PTE
PTEPage Tables Page Frames
Task A
Task A
Shared
Shared
Task B
Task BShared PT
PTE
PTEPDE
PDEPDBR
PDBRTask A TSS
Task B TSS8-18 Vol. 3ATASK MANAGEMENT
8.5.2 Task Logical Address Space
To allow the sharing of data among tasks, use the foll owing techniques to create shared logical-to-physical 
address-space mappings for data segments:
•Through the segment de scriptors in the GDT — All tasks must have access to the segment descriptors in 
the GDT. If some segment descriptors in the GDT poin t to segments in the linear-address space that are 
mapped into an area of the physical-address space common  to all tasks, then all tasks can share the data and 
code in those segments.
•Through a shared LDT — Two or more tasks can use the same LDT if the LDT fields in their TSSs point to the 
same LDT. If some segment descriptors in a shared LD T point to segments that are mapped to a common area 
of the physical address space, the data and code in th ose segments can be shared among the tasks that share 
the LDT. This method of sharing is more selective th an sharing through the GDT, because the sharing can be 
limited to specific tasks. Other tasks in the system may have different LDTs that do not give them access to the 
shared segments.
•Through segment descriptors in di stinct LDTs that are mapped to  common addresses in linear 
address space — If this common area of the linear address spac e is mapped to the same area of the physical 
address space for each task, these segment descriptors  permit the tasks to share segments. Such segment 
descriptors are commonly called aliases. This method of sh aring is even more selective than those listed above, 
because, other segment descriptors in the LDTs may point to independent linear addresses which are not shared.
8.6 16-BIT TASK-STATE SEGMENT (TSS)
The 32-bit IA-32 processors also recognize a 16-bit TSS format like the one used in Intel 286 processors (see 
Figure 8-10). This format is supported for compatibility with software written to run on earlier IA-32 processors. 
The following information is important to know about the 16-bit TSS.
•Do not use a 16-bit TSS to implement a virtual-8086 task.
•The valid segment limit for a 16-bit TSS is 2CH.
•The 16-bit TSS does not contain a field for the base addre ss of the page directory, which is loaded into control 
register CR3. A separate set of page tables for each task  is not supported for 16-bit tasks. If a 16-bit task is 
dispatched, the page-table structure for the previous task is used.
•The I/O base address is not included in the 16-bit TSS.  None of the functions of the I/O map are supported.
•When task state is saved in a 16-bit TSS, the upper 16 bi ts of the EFLAGS register and the EIP register are lost.
•When the general-purpose registers are loaded or saved fr om a 16-bit TSS, the upper 16 bits of the registers 
are modified and not maintained.Vol. 3A 8-19TASK MANAGEMENT
8.7 TASK MANAGEMENT IN 64-BIT MODE
In 64-bit mode, task structure and task state are similar to those in protected mode. However, the task switching 
mechanism available in protected mode is not supported in  64-bit mode. Task management and switching must be 
performed by software. The processor issues a general-prot ection exception (#GP) if the following is attempted in 
64-bit mode:
•Control transfer to a TSS or a task gate using JMP, CALL, INT n, INT3, INTO, INT1, or interrupt.
•An IRET with EFLAGS.NT (nested task) set to 1.
Although hardware task-switching is not supported in 64-b it mode, a 64-bit task state segment (TSS) must exist. 
Figure 8-11 shows the format of a 64-bit TSS. The TSS hold s information important to 64-bit mode and that is not 
directly related to the task-switch mechanism. This information includes:
•RSPn  — The full 64-bit canonical forms of the stack pointers (RSP) for privilege levels 0-2.
•ISTn  — The full 64-bit canonical forms of the interrupt stack table (IST) pointers.
•I/O map base address  — The 16-bit offset to the I/O permission bit map from the 64-bit TSS base.
The operating system must create at least one 64-bit TS S after activating IA-32e mode. It must execute the LTR 
instruction (in 64-bit mode) to load the TR register with  a pointer to the 64-bit TSS responsible for both 64-bit-
mode programs and compatibility-mode programs.Figure 8-10.  16-Bit TSS FormatTask LDT Selector
DS Selector
SS Selector
CS Selector
ES Selector
DI
SI
BP
SP
BX
DX
CX
AX
FLAG Word
IP (Entry Point)
SS2
SP2
SS1
SP1SS0SP0
Previous Task Link15 0
42
40
36
34
32
3038
28
26
24
22
20
18
16
14
12
10
86
4
2
08-20 Vol. 3ATASK MANAGEMENT
Figure 8-11.  64-Bit TSS Format0 31
100
96
92
88
84
80
76I/O Map Base Address15
72
68
64
60
56
52
48
44
40
36
32
28
24
20
16
12
8
4
0RSP0 (lower 32 bits)RSP1 (lower 32 bits)RSP2 (lower 32 bits)
Reserved bits. Set to 0.RSP0 (upper 32 bits)RSP1 (upper 32 bits)RSP2 (upper 32 bits)IST1 (lower 32 bits)IST1 (upper 32 bits)IST2 (lower 32 bits)IST3 (lower 32 bits)IST4 (lower 32 bits)IST5 (lower 32 bits)IST6 (lower 32 bits)IST7 (lower 32 bits)
IST2 (upper 32 bits)IST3 (upper 32 bits)IST4 (upper 32 bits)IST5 (upper 32 bits)IST6 (upper 32 bits)IST7 (upper 32 bits)
ReservedReserved
ReservedReservedReserved
ReservedVol. 3A 9-1CHAPTER 9
The Intel 64 and IA-32 architectures provide mechanisms for managing and improving th e performance of multiple 
processors connected to the same system bus. These include:
•Bus locking and/or cache coherency management for performing atomic operations on system memory.
•Serializing instructions.
•An advance programmable interrupt controller (APIC)  located on the processor chip (see Chapter 11, 
“Advanced Programmable Interrupt Controller (APIC)”). Th is feature was introduced by the Pentium processor.
•A second-level cache (level 2, L2). For the Pentium 4, Intel Xeon, and P6 family processors, the L2 cache is 
included in the processor package and is tightly co upled to the processor. For the Pentium and Intel486 
processors, pins are provided to support an external L2 cache.
•A third-level cache (level 3, L3). For Intel Xeon proce ssors, the L3 cache is included in the processor package

•A third-level cache (level 3, L3). For Intel Xeon proce ssors, the L3 cache is included in the processor package 
and is tightly coupled to the processor.
•Intel Hyper-Threading Technology. This extension to th e Intel 64 and IA-32 architectures enables a single 
processor core to execute two or more threads conc urrently (see Section 9.5, “Intel® Hyper-Threading 
Technology and Intel® Multi-Core Technology”).
These mechanisms are particularly useful in symmetric-mu ltiprocessing (SMP) systems. However, they can also be 
used when an Intel 64 or IA-32 processor and a special- purpose processor (such as a communications, graphics, 
or video processor) share the system bus.
These multiprocessing mechanisms have the following characteristics:
•To maintain system memory coherency — When two or more processors are attempting simultaneously to 
access the same address in system memory, some co mmunication mechanism or memory access protocol 
must be available to promote data cohe rency and, in some instances, to allow one processor to temporarily lock 
a memory location.
•To maintain cache consistency — When one processor accesses data cached on another processor, it must not 
receive incorrect data. If it modifies data, all other processors that access that data must receive the modified 
data.
•To allow predictable ordering of writes to memory — In some circumstances, it is important that memory writes 
be observed externally in precisely the same order as programmed.
•To distribute interrupt handling among a group of processors — When several processors are operating in a 
system in parallel, it is useful to have a centralized mechanism for receiving interrupt s and distributing them to 
available processors for servicing.
•To increase system performance by exploiting the mult i-threaded and multi-process nature of contemporary 
operating systems and applications.
The caching mechanism and cache consistency of Intel 64 and IA-32 processors are discussed in Chapter 12. The 
APIC architecture is described in Chapter 11. Bus and me mory locking, serializing instructions, memory ordering, 
and Intel Hyper-Threading Technology are discussed in the following sections. 
9.1 LOCKED ATOMIC OPERATIONS
The 32-bit IA-32 processors support locked atomic operat ions on locations in system memory. These operations 
are typically used to manage shared data structures (s uch as semaphores, segment descriptors, system segments, 
or page tables) in which two or more processors may tr y simultaneously to modify the same field or flag. The 
processor uses three interdependent mechanisms for carrying out locked atomic operations:
•Guaranteed atomic operations.
•Bus locking, using the LOCK# signal and the LOCK instruction prefix.9-2 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
•Cache coherency protocols that ensure that atomic operations can be carried out on cached data structures 
(cache lock); this mechanism is present in the Pentium 4, Intel Xeon, and P6 family processors.
These mechanisms are interdependent in the following wa ys. Certain basic memory transactions (such as reading 
or writing a byte in system memory) are always guaranteed  to be handled atomically. That is, once started, the 
processor guarantees that the operation will be completed before another processor or bus agent is allowed access 
to the memory location. The processor also supports bus locking for performing selected memory operations (such 
as a read-modify-write operation in a shared area of memo ry) that typically need to be handled atomically, but are 
not automatically handled this way. Because frequently used  memory locations are often cached in a processor’s L1 
or L2 caches, atomic operations can often be carried out inside a processor’s caches without asserting the bus lock. 
Here the processor’s cache coherency protocols ensure th at other processors that are caching the same memory 
locations are managed properly while atomic operat ions are performed on cached memory locations.
NOTE
Where there are contested lock accesses, software may need to implement algorithms that ensure 
fair access to resources in order to prevent lock starvation. The hardware provides no resource that 
guarantees fairness to participating agents. It is the responsibility of software to manage the 
fairness of semaphores and exclusive locking functions.
The mechanisms for handling locked atomic operations have  evolved with the complexity of IA-32 processors. More 
recent IA-32 processors (such as the Pentium 4, Intel Xeon , and P6 family processors) and Intel 64 provide a more 
refined locking mechanism than earlier processors. Thes e mechanisms are described in the following sections.
9.1.1 Guaranteed Atomic Operations
The Intel486 processor (and newer processors since) guaran tees that the following basic memory operations will 
always be carried out atomically:
•Reading or writing a byte.
•Reading or writing a word aligned on a 16-bit boundary.
•Reading or writing a doubleword aligned on a 32-bit boundary.
The Pentium processor (and newer processors since) guaran tees that the following additional memory operations 
will always be carried out atomically:
•Reading or writing a quadword aligned on a 64-bit boundary.
•16-bit accesses to uncached memory locations that fit within a 32-bit data bus.
The P6 family processors (and newer processors since) guarantee that the following additional memory operation 
•Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line.
Processors that enumerate support for Intel® AVX (by setting the feature flag  CPUID.01H:ECX.AVX[bit 28]) guar-
antee that the 16-byte memory operations performed by the following instructions will always be carried out atom-ically:
•MOVAPD, MOVAPS, and MOVDQA.
•VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128.
•VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded with EVEX.128 and k0 (masking 
disabled).
(Note that these instructions require the linear addre sses of their memory operands to be 16-byte aligned.)
Accesses to cacheable memory that are split across cache lines and page boundaries are not guaranteed to be 
atomic by the Intel Core 2 Duo, Intel Atom, Intel Core Du o, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, 
and Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and 
P6 family processors provide bus control signals that pe rmit external memory subsystems to make split accesses 
atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be 
avoided.Vol. 3A 9-3MULTIPLE-PROCESSOR MANAGEMENT
Except as noted above, an x87 instruction or an SSE instru ction that accesses data larger than a quadword may be 
implemented using multiple memory accesses. If such an instruction stores to memory, some of the accesses may complete (writing to memory) while another causes the op eration to fault for architectural reasons (e.g., due an 
page-table entry that is marked “not present”). In this case, the effects of the completed accesses may be visible 
to software even though the overall instruction caused a fault. If TLB invalidation has been delayed (see Section 
4.10.4.4), such page faults may occur even  if all accesses are to the same page.
9.1.2 Bus Locking
Intel 64 and IA-32 processors provide a LOCK# signal that is asserted automatically during certain critical memory 
operations to lock the system bus or equivalent link. Assertion of this signal is called a bus lock . While this output 
signal is asserted, requests from other processors or bu s agents for control of the bus are blocked. Software can 
specify other occasions when the LOCK semantics are to be  followed by prepending the LOCK prefix to an instruc-
tion.
In the case of the Intel386, Intel486, and Pentium processors , explicitly locked instructions will result in the asser-
tion of the LOCK# signal. It is the responsibility of the hardware designer to make the LOCK# signal available in 
system hardware to control memory accesses among processors.
For the P6 and more recent processor families, if the me mory area being accessed is cached internally in the 
processor, the LOCK# signal is generally not asserted; inst ead, locking is only applied to the processor’s caches 
(see Section 9.1.4, “Effects of a LOCK Operation on Internal  Processor Caches”). These processors will assert a bus 
lock for a locked access in either of the following situations: (1) the access is to multiple cache lines (a split lock ); 
or (2) the access uses a memory type other than WB (a UC lock )1.
9.1.2.1  Automatic Locking
The operations on which the processor automatica lly follows the LOCK semantics are as follows:
•When executing an XCHG instruction that references memory.
•When switching to a task, the processor tests and sets the busy flag in the type field of the TSS descriptor. To 
ensure that two processors do not switch to the same  task simultaneously, the processor follows the LOCK

ensure that two processors do not switch to the same  task simultaneously, the processor follows the LOCK 
semantics while testing and setting this flag.
•When loading a segment descriptor, the processor sets the accessed flag in the segment descriptor if the flag is 
clear. During this operation, the processor follows the LOCK semantics so that the descriptor will not be 
modified by another processor while it is being updated.  For this action to be ef fective, operating-system 
procedures that update descriptors should use the following steps:
— Use a locked operation to modify the access-rights byte to indicate that the segment descriptor is not-
present, and specify a value for the type field th at indicates that the descriptor is being updated.
— Update the fields of the segment descriptor. (Thi s operation may require several memory accesses; 
therefore, locked operations cannot be used.)
— Use a locked operation to modify the access-rights byte to indicate that the segment descriptor is valid and 
present.
— The Intel386 processor always updates the accessed flag in the segment descriptor, whether it is clear or 
not. The Pentium 4, Intel Xeon, P6 family, Pentium, and In tel486 processors only update this flag if it is not 
already set.
•The processor uses locked cycles to set the accessed and dirty flag in paging-structure entries.
•After an interrupt request, an interrupt controller may use the data bus to send the interrupt’s vector to the 
processor. The processor follows the LOCK semantics during this time to ensure that no other data appears on the data bus while the vector is being transmitted.
1. The term “UC lock” is used because the most common situation regards accesses to UC memory. De spite the name, locked accesses  
to WC, WP, and WT memory also cause bus locks.9-4 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
9.1.2.2  Software Controlled Bus Locking
To explicitly force the LOCK semantics, software can use th e LOCK prefix with the following instructions when they 
are used to modify a memory location. An invalid-opcode  exception (#UD) is generated when the LOCK prefix is 
used with any other instruction or when no write operat ion is made to memory (that is, when the destination 
operand is in a register).
•The bit test and modify instructions (BTS, BTR, and BTC).
•The exchange instructions (XADD, CMPXCHG, CMPXCHG8B, and CMPXCHG16B). 
•The LOCK prefix is automatically  assumed for XCHG instruction.
•The following single-operand arithmetic and lo gical instructions: INC, DEC, NOT, and NEG.
•The following two-operand arithmetic and logical inst ructions: ADD, ADC, SUB, SBB, AND, OR, and XOR.
A locked instruction is guaranteed to lock only the area of memory defined by the destination operand, but may be 
interpreted by the system as a lock for a larger memory area.
Software should access semaphores (shared memory used for signalling between multiple processors) using iden-
tical addresses and operand lengths. For example, if on e processor accesses a semaphore using a word access, 
other processors should not access the semaphore using a byte access. 
NOTE
Do not implement semaphores using the WC memory type. Do not perform non-temporal stores to a cache line containing a location used to implement a semaphore.
The integrity of a bus lock is not affected by the alignm ent of the memory field. The LOCK semantics are followed 
for as many bus cycles as necessary to update the entire  operand. However, it is recommend that locked accesses 
be aligned on their natural bounda ries for better system performance:
•Any boundary for an 8-bit access (locked or otherwise).
•16-bit boundary for locked word accesses.
•32-bit boundary for locked doubleword accesses.
•64-bit boundary for locked quadword accesses.
Locked operations are atomic with respect to all other memory operations and all externally visible events. Only 
instruction fetch and page table accesses can pass locked instructions. Locked instructions can be used to synchro-nize data written by one processo r and read by another processor.
For the P6 family processors, locked op erations serialize all outstanding load and store operations (that is, wait for 
them to complete). This rule is also true for the Pentium 4 and Intel Xeon processors, with one exception. Load 
operations that reference weakly or dered memory types (such as the WC memory type) may not be serialized.
Locked instructions should not be used to ensure that data written can be fetched as instructions. 
NOTE
The locked instructions for the current versions of  the Pentium 4, Intel Xeon, P6 family, Pentium, 
and Intel486 processors allow data written to  be fetched as instructions. However, Intel 
recommends that developers who require the use of  self-modifying code use a different synchro-
nizing mechanism, described in the following sections.
9.1.2.3  Features to Disable Bus Locks
Because bus locks may adversely affect performance in certain situations, processors may support two features 
that system software can use to disable bus locking. These are called UC-lock disable  and split-lock disable .
A processor enumerates support for UC-lock disable by setting bit 4 of the IA32_CO RE_CAPABILITIES MSR (MSR 
index CFH). Support for split-lock disable is enumerated by IA32_CORE_CAPABILITIES[5].
Software enables UC-lock disable by setting bit 28 of th e MSR_MEMORY_CTRL MSR (MSR index 33H). When this bit 
is set, a locked access using a memory type other than WB causes a general-protection exception (#GP) with a 
zero error code. The locked access does not occur.Vol. 3A 9-5MULTIPLE-PROCESSOR MANAGEMENT
Software enables split-lock disable by setting MSR_MEMORY _CTRL[29]. When this bit is set, a locked access to 
multiple cache lines causes an alignment-check exception (#AC) with a zero error code.2 The locked access does 
not occur.
If both features are enabled, a locked access to multip le cache lines causes #AC(0) regardless of the memory 
type(s) being accessed.
While MSR_MEMORY_CTRL is not an architectural MSR, the behavior described above is consistent across 
processor models that enumerate the support in IA32_CORE_CAPABILITIES.
In addition to these features that disable bus locks, there are features that allow software to detect when a bus lock 
has occurred. See Section 18.3.1.6 for information about OS bus-lock detection and Section 26.2 for information 
about the VMM bus-lock detection.
9.1.3 Handling Self- and Cross-Modifying Code
The act of a processor writing data into a currently executin g code segment with the inte nt of executing that data 
as code is called self-modifying code . IA-32 processors exhibi t model-specific behavior when executing self-
modified code, depending upon how fa r ahead of the current execution pointer the code has been modified. 
As processor microarchitectures become more complex and start to speculatively execute code ahead of the retire-
ment point (as in P6 and more recent processor families), the rules regarding which code should execute, pre- or 
post-modification, become blurred. To write self-modifying  code and ensure that it is compliant with current and 
future versions of the IA-32 architectures, use one of the following coding options:
(* OPTION 1 *)
Store modified code (as data) into code segment; Jump to new code or an  intermediate location;
Execute new code;
(* OPTION 2 *)
Store modified code (as data) into code segment;Execute a serializing instruction; (*  For example, CPUID instruction *)
The use of one of these options is not required for programs  intended to run on the Pentium or Intel486 processors, 
but are recommended to ensure compatibility wi th the P6 and more recent processor families.
Self-modifying code will execute at a lower level of pe rformance than non-self-modifying or normal code. The 
degree of the performance deterioration wi ll depend upon the frequency of modification and specific characteristics 
of the code.
The act of one processor writing data into the currently executing code segment of a second processor with the 
intent of having the second processor execute that data as code is called cross-modifying code . As with self-
modifying code, IA-32 processors exhibit model-specif ic behavior when execut ing cross-modifying code, 
depending upon how far ahead of the executing processors  current execution pointer the code has been modified. 
To write cross-modifying code and ensure that it is compliant with current and future versions of the IA-32 archi-
tecture, the following processor synchron ization algorithm must be implemented:
(* Action of Modifying Processor *)
Memory_Flag := 0; (* Set Memory _Flag to value other than 1 *)
Store modified code (as data) into code segment;Memory_Flag := 1;
(* Action of Executing Processor *)
WHILE (Memory_Flag ≠ 1)
Wait for code to update;
2. Other alignment-check exceptions  occur only if CR0.AM = 1, EFLAGS.AC = 1, and CPL = 3. The alignment-check exceptions resulting 
from split-lock disable may occur even if  CR0.AM = 0, EFLAGS.AC = 0, or CPL < 3.9-6 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
ELIHW;

ELIHW;
Execute serializing instruction; (*  For example, CPUID instruction *)
Begin executing modified code;
(The use of this option is not required for programs inte nded to run on the Intel486 processor, but is recommended 
to ensure compatibility with the Pentium 4, Intel Xeon, P6 family, and Pentium processors.)
Like self-modifying code, cross-modifying code will exec ute at a lower level of performance than non-cross-modi-
fying (normal) code, depending upon the frequency of mo dification and specific characteristics of the code.
The restrictions on self-modifying code and cross-modifying code also apply to the Intel 64 architecture.
9.1.4 Effects of a LOCK Operation on Internal Processor Caches
For the Intel486 and Pentium processors, the LOCK# signal is  always asserted on the bus during a LOCK operation, 
even if the area of memory being locked is cached in the processor.
For the P6 and more recent processor families, if the ar ea of memory being locked during a LOCK operation is 
cached in the processor that is performing the LOCK oper ation as write-back memory and is completely contained 
in a cache line, the processor may not assert the LOCK# signal  on the bus. Instead, it will modify the memory loca-
tion internally and allow it’s cache co herency mechanism to ensure that the operation is carried out atomically. This 
operation is called “cache locking.” The cache coherenc y mechanism automatically prevents two or more proces-
sors that have cached the same area of memory from simultaneously modifying data in that area.
9.2 MEMORY ORDERING
The term memory ordering  refers to the order in which the processor issues reads (loads) and writes (stores) 
through the system bus to system memory. The Intel 64 and IA-32 architectures support several memory-ordering 
models depending on the implementation of the archit ecture. For example, the Intel386 processor enforces 
program ordering  (generally referred to as strong ordering ), where reads and writes are issued on the system 
bus in the order they occur in the instruction stream under all circumstances. 
To allow performance optimization of instruction execution, the IA-32 architecture allows departures from strong-
ordering model called processor ordering  in Pentium 4, Intel Xeon, and P6 family processors. These processor-
ordering  variations (called here the memory-ordering model ) allow performance enhancing operations such as 
allowing reads to go ahead of buffered writes. The goal of  any of these variations is to increase instruction execu-
tion speeds, while maintaining memory cohe rency, even in multiple-processor systems.
Section 9.2.1 and Section 9.2.2 describe the memory-order ing implemented by Intel486, Pentium, Intel Core 2 
Duo, Intel Atom, Intel Core Duo, Pentium 4, Intel Xeon, and P6 family processors. Section 9.2.3 gives examples 
illustrating the behavior of the memory-ordering model on  IA-32 and Intel-64 processors. Section 9.2.4 considers 
the special treatment of stores for string operations and Section 9.2.5 discusses how memory-ordering behavior 
may be modified through the use of specific instructions.
9.2.1 Memory Ordering in the Intel® Pentium® and Intel486™ Processors
The Pentium and Intel486 processors follow the proce ssor-ordered memory model; however, they operate as 
strongly-ordered processors under most circumstances. Re ads and writes always appear in programmed order at 
the system bus—except for the following situation wher e processor ordering is exhibited. Read misses are 
permitted to go ahead of buffered writes on the system bu s when all the buffered writes are cache hits and, there-
fore, are not directed to the same address being accessed by the read miss. 
In the case of I/O operations, both reads an d writes always appear in programmed order.
Software intended to operate correctly in processor-ordere d processors (such as the Pe ntium 4, Intel Xeon, and P6 
family processors) should not depend on the relatively strong ordering of the Pentium or Intel486 processors. 
Instead, it should ensure that accesses to shared variables that are intended to control concurrent execution among processors are explicitly  required to obey program ordering throug h the use of appropriate locking or seri-
alizing operations (see Section 9.2.5, “Strengthe ning or Weakening the Memory-Ordering Model”).Vol. 3A 9-7MULTIPLE-PROCESSOR MANAGEMENT
9.2.2 Memory Ordering in P6 and More Recent Processor Families
The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, and P6 family processors also use a processor-
ordered memory-ordering model that can be further defined as “write ordered with store-buffer forwarding.” This 
model can be characterized as follows. 
In a single-processor system for memo ry regions defined as write-back cacheable, the memory-ordering model 
respects the following principles ( Note  the memory-ordering principles for single-processor and multiple-
processor systems are written from the perspective of software executing on the processor, where the term 
“processor” refers to a logical processor. For example, a physical processor supporting multiple cores and/or Intel 
Hyper-Threading Technology is treated as a multi-processor systems.):
•Reads are not reordered with other reads.
•Writes are not reordered with older reads.
•Writes to memory are not reordered with other writes, with the following exceptions:
— streaming stores (writes) executed with the no n-temporal move instructions (MOVNTI, MOVNTQ, 
MOVNTDQ, MOVNTPS, and MOVNTPD); and
— string operations (see Section 9.2.4.1).
•No write to memory may be reordered with an executio n of the CLFLUSH instruction; a write may be reordered 
with an execution of the CLFLUSHOPT instruction that flushes a cache line other than the one being written.3 
Executions of the CLFLUSH instruction are not reordere d with each other. Executions of CLFLUSHOPT that 
access different cache lines may be reordered with each other. An execution of CLFLUSHOPT may be reordered with an execution of CLFLUSH that accesses a different cache line.
•Reads may be reordered with older writes to different lo cations but not with older writes to the same location. 
•Reads or writes cannot be reordered with I/O instructions, locked instructions, or serializing instructions.
•Reads cannot pass earlier LFENCE and MFENCE instructions.
•Writes and executions of CLFLUSH and CLFLUSHOPT  cannot pass earlier LFENCE, SFENCE, and MFENCE 
•LFENCE instructions cannot pass earlier reads.
•SFENCE instructions cannot pass earlier writes or executions of CLFLUSH and CLFLUSHOPT.
•MFENCE instructions cannot pass earlier reads, wr ites, or executions of CLFLUSH and CLFLUSHOPT.
In a multiple-processor system, the following ordering principles apply:
•Individual processors use the same ordering principles as in a single-processor system.
•Writes by a single processor are observed in the same order by all processors.
•Writes from an individual processor are NOT ordered with respect to the writes from other processors.
•Memory ordering obeys causality (memory or dering respects transitive visibility).
•Any two stores are seen in a consistent order by processors other than those performing the stores
•Locked instructions have a total order.
See the example in Figure 9-1. Consider three processors in a system and each processor performs three writes, 
one to each of three defined locations (A, B, and C). Indi vidually, the processors perform the writes in the same 
program order, but because of bus arbitration and othe r memory access mechanisms, the order that the three 
processors write the individual memory locations can differ each time the respective code sequences are executed on the processors. The final values in location A, B, and C would possibly vary on each execution of the write 
sequence.
The processor-ordering model described in this section is virtually identical to that used by the Pentium and 
Intel486 processors. The only enhancements in the Pe ntium 4, Intel Xeon, and P6 family processors are:
•Added support for speculative reads, while sti ll adhering to the ordering principles above.
•Store-buffer forwarding, when a read passes a write to the same memory location.
3. Earlier versions of this manual specified that writes to memory may be reordered with executions of the CLFLUSH instruction. No 
processors implementing the CLFLUSH instruction allow such reordering.9-8 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
•Out of order store from long string store and string move operations (see Section 9.2.4, “Fast-String Operation 
and Out-of-Order Stores,” below).
NOTE
In P6 processor family, store-buffer forwarding to  reads of WC memory from streaming stores to 
the same address does not occur due to errata.
9.2.3 Examples Illustrating the Memory-Ordering Principles
This section provides a set of examples that illustrate th e behavior of the memory-order ing principles introduced in

NOTE
This section provides a set of examples that illustrate th e behavior of the memory-order ing principles introduced in 
Section 9.2.2. They are designed to give software writer s an understanding of how memory ordering may affect the 
results of different sequences of instructions.
These examples are limited to accesses to memory regions defined as write-back cacheable (WB). (Section 9.2.3.1 
describes other limitations on the generality of the exam ples.) The reader should understand that they describe 
only software-visible behavior. A logical processor may reor der two accesses even if one of examples indicates that 
they may not be reordered. Such an example states only  that software cannot detect that such a reordering 
occurred. Similarly, a logical processor may execute a memory access more than once as long as the behavior 
visible to software is consistent with a single execution of the memory access.
9.2.3.1  Assumptions, Terminology, and Notation
As noted above, the examples in this section are limite d to accesses to memory regions defined as write-back 
cacheable (WB). They apply only to ordinary loads stores and to locked read-modify-write instructions. They do not 
necessarily apply to any of the following: out-of-order stores for string instructions (see Section 9.2.4); accesses with a non-temporal hint; reads from memory by the proce ssor as part of address translation (e.g., page walks); 
and updates to segmentation and paging structures by the processor (e.g., to update “accessed” bits).
The principles underlying the examples in this section a pply to individual memory accesses and to locked read-
modify-write instructions. The Intel-64 memory-orderin g model guarantees that, for each of the following 
memory-access instructions, the constituent memory operation appears to execute as a single memory access:
•Instructions that read or write a single byte.
•Instructions that read or write a word (2 byte s) whose address is aligned on a 2 byte boundary.Figure 9-1.  Example of Write Orde ring in Multiple-Processor SystemsProcessor #1 Processor #2 Processor #3
Write A.3
Write B.3Write C.3
Write A.1
Write B.1Write A.2Write A.3Write C.1
Write B.2
Write C.2Write B.3Write C.3Order of Writes From Individual Processors
Write A.2
Write B.2
Write C.2Write A.1
Write B.1Write C.1
Writes from all
processors are
not guaranteed
to occur in a
particular order.Each processor
is guaranteed toperform writes inprogram order.
Writes are in order
with respect to individual processes.Example of order of actual writes
from all processors to memoryVol. 3A 9-9MULTIPLE-PROCESSOR MANAGEMENT
•Instructions that read or write a doubleword (4 by tes) whose address is aligned on a 4 byte boundary.
•Instructions that read or write a quadword (8 byte s) whose address is aligned on an 8 byte boundary.
Any locked instruction (either the XCHG instruction or an other read-modify-write instruction with a LOCK prefix) 
appears to execute as an indivisible and uninterruptible sequence of load(s) followed by store(s) regardless of 
alignment.
Other instructions may be implemented with multiple me mory accesses. From a memory-ordering point of view, 
there are no guarantees regarding the relative order in which the constituent memory accesses are made. There is 
also no guarantee that the constituent operations of a store are executed in the same order as the constituent 
operations of a load.
Section 9.2.3.2 through Section 9.2.3.7 give examples us ing the MOV instruction. The principles that underlie 
these examples apply to load and store accesses in general and to other instructions that load from or store to 
memory. Section 9.2.3.8 and Section 9.2.3.9 give exampl es using the XCHG instruction. The principles that 
underlie these examples apply to other locked read-modify-write instructions.
This section uses the term “processor” is to refer to a logical processor. The examples are written using Intel-64 
assembly-language syntax and use the following notational conventions:
•Arguments beginning with an “r”, such as r1 or r2 refe r to registers (e.g., EAX) visible only to the processor 
being considered.
•Memory locations are denoted with x, y, z.
•Stores are written as mov [ _x], val , which implies that val is being stored into the memory location x.
•Loads are written as mov r, [ _x] , which implies that the contents of the memory location x are being loaded 
into the register r.
As noted earlier, the examples refer only to software visible behavior. When the succeeding sections make state-
ment such as “the two stores are reordered,” the implicatio n is only that “the two stores appear to be reordered 
from the point of view of software.”
9.2.3.2  Neither Loads Nor Stores Are Reordered with Like Operations
The Intel-64 memory-ordering model allows neither loads no r stores to be reordered with the same kind of opera-
tion. That is, it ensures that loads are seen in program order and that stores are seen in program order. This is illus-
trated by the following example:
The disallowed return values could be exhibited only if processor 0’s two stores are reordered (with the two loads 
occurring between them) or if processor 1’s two loads ar e reordered (with the two stor es occurring between them).
If r1 = 1, the store to y occurs before the load from y.  Because the Intel-64 memory-ordering model does not allow 
stores to be reordered, the earlier store to x occurs befo re the load from y. Because the Intel-64 memory-ordering 
model does not allow loads to be reordered, the store to x also occurs before the later load from x. This r2 = 1.
9.2.3.3  Stores Are Not Re ordered With Earlier Loads
The Intel-64 memory-ordering model ensures that a store by  a processor may not occur before a previous load by 
the same processor. This is illustrated in Example 9-2.Example 9-1.  Stores Are Not Reordered with Other Stores
mov [ _x], 1 mov r1, [ _y]mov [ _y], 1 mov r2, [ _x]Initially x = y = 0r1 = 1 and r2 = 0 is not allowed9-10 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
Assume r1 = 1.
•Because r1 = 1, processor 1’s store to x occurs before processor 0’s load from x.
•Because the Intel-64 memory-ordering model prevents ea ch store from being reordered with the earlier load 
by the same processor, processor 1’s load from y occurs before its store to x.
•Similarly, processor 0’s load from x occurs before its store to y.
•Thus, processor 1’s load from y occurs before processor 0’s store to y, implying r2 = 0.
9.2.3.4  Loads May Be Reordered with Earlier Stores to Different Locations
The Intel-64 memory-ordering model allows a load to be re ordered with an earlier store to a different location. 
However, loads are not reordered with stores to the same location.
The fact that a load may be reordered with an earlier stor e to a different location is illustrated by the following 
example:
At each processor, the load and the store are to different  locations and hence may be reordered. Any interleaving 
of the operations is thus allowed. One such interleaving  has the two loads occurring before the two stores. This 
would result in each load returning value 0.
The fact that a load may not be reordered with an earlier store to the same location is illustrated by the following 
example:
The Intel-64 memory-ordering model does not allow the load  to be reordered with the earlier store because the 
accesses are to the same location. Therefore, r1 = 1 must hold.Example 9-2.  Stores Are No t Reordered with Older Loads
mov r1, [ _x] mov r2, [ _y]mov [ _y], 1 mov [ _x], 1Initially x = y = 0r1 = 1 and r2 = 1 is not allowed
Example 9-3.  Loads May be Reordered with Older Stores
mov [ _x], 1 mov [ _y], 1mov r1, [ _y] mov r2, [ _x]Initially x = y = 0r1 = 0 and r2 = 0 is allowed
Example 9-4.  Loads Are not Reordered with Older Stores to the Same Location
Processor 0
mov [ _x], 1mov r1, [ _x]Initially x = 0r1 = 0 is not allowedVol. 3A 9-11MULTIPLE-PROCESSOR MANAGEMENT
9.2.3.5  Intra-Processor Forwarding Is Allowed
The memory-ordering model allows concurrent stores by two processors to be seen in different orders by those two 
processors; specifically, each processor may perceive its own store occurring before that of the other. This is illus-
The memory-ordering model imposes no constraints on the or der in which the two stores appear to execute by the 
two processors. This fact allows processor 0 to see its store before seeing processor 1's, while processor 1 sees its 
store before seeing processor 0's. (Each processor is self consistent.) This allows r2 = 0 and r4 = 0.
In practice, the reordering in this example can arise as a result of store-buffer forwarding. While a store is tempo-
rarily held in a processor's store buffer, it can satisfy the processor's own loads but is not visible to (and cannot 
satisfy) loads by other processors.
9.2.3.6  Stores Are Transitively Visible
The memory-ordering model ensures transitive visibility of stores; stores that are causally related appear to all

The memory-ordering model ensures transitive visibility of stores; stores that are causally related appear to all 
processors to occur in an order consistent with the causa lity relation. This is illustra ted by the following example:
Assume that r1 = 1 and r2 = 1.
•Because r1 = 1, processor 0’s store occurs before processor 1’s load.
•Because the memory-ordering model prevents a store from  being reordered with an earlier load (see Section 
9.2.3.3), processor 1’s load occurs before its store. Thus, processor 0’s store causally precedes processor 1’s 
store.
•Because processor 0’s store causally precedes processo r 1’s store, the memory-ordering model ensures that 
processor 0’s store appears to occur before processor 1’s store from the point of view of all processors.
•Because r2 = 1, processor 1’s store occurs before processor 2’s load.
•Because the Intel-64 memory-ordering model prevents  loads from being reordered (see Section 9.2.3.2), 
processor 2’s load occur in order.
•The above items imply that processor 0’s store to x occurs  before processor 2’s load from x. This implies that 
r3 = 1.Example 9-5.  Intra-Processor Forwarding is Allowed
mov [ _x], 1 mov [ _y], 1mov r1, [ _x] mov r3, [ _y]mov r2, [ _y] mov r4, [ _x]Initially x = y = 0r2 = 0 and r4 = 0 is allowed
Example 9-6.  Stores Are Transitively Visible
mov [ _x], 1 mov r1, [ _x]
mov [ _y], 1 mov r2, [ _y]
mov r3, [_x]
Initially x = y = 0r1 = 1, r2 = 1, r3 = 0 is not allowed9-12 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
9.2.3.7  Stores Are Seen in a Consistent Order by Other Processors
As noted in Section 9.2.3.5, the memory-ordering model allo ws stores by two processors to be seen in different 
orders by those two processors. However, any two stores must appear to execute in the same order to all proces-sors other than those performing the stores. This is illustrated by the following example:
By the principles discussed in Section 9.2.3.2:
•Processor 2’s first and second load cannot be reordered.
•Processor 3’s first and second load cannot be reordered. 
•If r1 = 1 and r2 = 0, processor 0’s store appears to precede processor 1’s store with respect to processor 2. 
•Similarly, r3 = 1 and r4 = 0 imply that processor 1’s st ore appears to precede processor 0’s store with respect 
to processor 1. 
Because the memory-ordering model ensures that any two stores appear to execute in the same order to all 
processors (other than those performing the stor es), this set of return values is not allowed.
9.2.3.8  Locked Instructions Have a Total Order
The memory-ordering model ensures that all processors agree on a single execution order of all locked instructions, 
including those that are larger than 8 bytes or are not natu rally aligned. This is illustrated by the following example:
Processor 2 and processor 3 must agree on the order of the two executions of XCHG. Without loss of generality, 
suppose that processor 0’s XCHG occurs first.
•If r5 = 1, processor 1’s XCHG into y occurs before processor 3’s load from y.
•Because the Intel-64 memory-ordering model prevents loads from being reordered (see Section 9.2.3.2), processor 3’s loads occur in order and, therefore, processor 1’s XCHG occurs before processor 3’s load from x.
•Since processor 0’s XCHG into x occurs before proc essor 1’s XCHG (by assumption), it occurs before 
processor 3’s load from x. Thus, r6 = 1.
A similar argument (referring instead to processor 2’s loads) applies if processor 1’s XCHG occurs before 
processor 0’s XCHG.
9.2.3.9  Loads and Stores Are Not Reordered with Locked Instructions
The memory-ordering model prevents loads and stores from being reordered with locked instructions that execute 
earlier or later. The examples in this section illustrate only  cases in which a locked instruction is executed before a Example 9-7.  Stores Are Seen in a Consistent Order by Other Processors
Processor 0 Processor 1 Processor 2 Processor 3
mov [ _x], 1 mov [ _y], 1 m ov r1, [ _x] mov r3, [_y] 
mov r2, [ _y] mov r4, [_x] 
Initially x = y =0
r1 = 1, r2 = 0, r3 = 1,  r4 = 0 is not allowed
Example 9-8.  Locked Instructions Have a Total Order
xchg [ _x], r1 xchg [ _y], r2
mov r3, [ _x] mov r5, [_y]mov r4, [ _y] mov r6, [_x]
Initially r1 = r2 = 1, x = y = 0r3 = 1, r4 = 0, r5 = 1,  r6 = 0 is not allowedVol. 3A 9-13MULTIPLE-PROCESSOR MANAGEMENT
load or a store. The reader should note that reordering is  prevented also if the locked instruction is executed after 
a load or a store.
The first example illustrates that loads may not be reordered with earlier locked instructions:
As explained in Section 9.2.3.8, there is a total order of  the executions of locked instructions. Without loss of 
generality, suppose that processor 0’s XCHG occurs first.
Because the Intel-64 memory-ordering model prevents proc essor 1’s load from being reordered with its earlier 
XCHG, processor 0’s XCHG occurs before processor 1’s load. This implies r4 = 1.
A similar argument (referring instead to processor 2’s accesses) applies if processor 1’s XCHG occurs before 
The second example illustrates that a store may not be reordered with an earlier locked instruction:
Assume r2 = 1.
•Because r2 = 1, processor 0’s store to y occurs before processor 1’s load from y.
•Because the memory-ordering model prevents a store from being reordered with an earlier locked instruction, 
processor 0’s XCHG into x occurs before its store to y. Thus, processor 0’s XCHG into x occurs before 
processor 1’s load from y.
•Because the memory-ordering model prevents loads from being reordered (see Section 9.2.3.2), processor 1’s 
loads occur in order and, therefore, processor 1’s XCHG into x occurs before processor 1’s load from x. Thus, 
r3 = 1.
9.2.4 Fast-String Operation and Out-of-Order Stores
Section 7.3.9.3 of Intel® 64 and IA-32 Architectures Software Develope r’s Manual, Volume 1, described an optimi-
zation of repeated string operations called fast-string operation .
As explained in that section, the stores produced by fast -string operation may appear to execute out of order. Soft-
ware dependent upon sequential store ordering should not us e string operations for the entire data structure to be 
stored. Data and semaphores should be separated. Orde r-dependent code should write to a discrete semaphore 
variable after any string operations to allow correctly orde red data to be seen by all processors. Atomicity of load 
and store operations is guaranteed only for native data elemen ts of the string with native data size, and only if they 
are included in a single cache line.
Section 9.2.4.1 and Section 9.2.4.2 pr ovide further explain and examples.
9.2.4.1  Memory-Ordering Model for String  Operations on Write-Back (WB) Memory
This section deals with the memory-ordering model for stri ng operations on write-back (WB) memory for the Intel 
64 architecture. Example 9-9.  Loads Are not Reordered with Locks
xchg [ _x], r1 xchg [ _y], r3mov r2, [ _y] mov r4, [ _x]Initially x = y = 0, r1 = r3 = 1r2 = 0 and r4 = 0 is not allowed
Example 9-10.  Stores Are not Reordered with Locks
xchg [ _x], r1 mov r2, [ _y]mov [ _y], 1 mov r3, [ _x]Initially x = y = 0, r1 = 1r2 = 1 and r3 = 0 is not allowed9-14 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
The memory-ordering model respects the follow principles:
1. Stores within a single string oper ation may be executed out of order.
2. Stores from separate string operations (for example, stores from consecutive string operations) do not execute 
out of order. All the stores from an earlier string oper ation will complete before any store from a later string 
3. String operations are not reordered with other store operations.
Fast string operations (e.g., string operations initiate d with the MOVS/STOS instructions and the REP prefix) may 
be interrupted by exceptions or interrupts. The interrupt s are precise but may be dela yed - for example, the inter-
ruptions may be taken at cache line boundaries, after ever y few iterations of the loop, or after operating on every 
few bytes. Different implementations may choose different options, or may even choose not to delay interrupt 
handling, so software should not rely on the delay. When  the interrupt/trap handler is reached, the source/destina-
tion registers point to the next string element to be oper ated on, while the EIP stored in the stack points to the 
string instruction, and the ECX register has the value it held following the last successful iteration. The return from that trap/interrupt handler should cause the string instruction to be resumed from the point where it was inter-
rupted.
The string operation memory-ordering principles, (item 2 an d 3 above) should be interpreted by taking the incor-
ruptibility of fast string operations into account. For exampl e, if a fast string operation gets interrupted after k iter-
ations, then stores performed by the interrupt handler will be come visible after the fast string stores from iteration

rupted.
ations, then stores performed by the interrupt handler will be come visible after the fast string stores from iteration 
0 to k, and before the fast string st ores from the (k+1)th iteration onward. 
Stores within a single string operation may execute out of  order (item 1 above) only if fast string operation is 
enabled. Fast string operations are enabled/disabled through the IA32_MISC_ENABLE model specific register. 
9.2.4.2  Examples Illustrating Memory-O rdering Principles for String Operations
The following examples uses the same notation and convention as described in Section 9.2.3.1.
In Example 9-11, processor 0 does one round of (128 iterations) doubleword string store operation via rep:stosd, 
writing the value 1 (value in EAX) into a block of 512 byte s from location _x (kept in ES:EDI) in ascending order. 
Since each operation stores a doubleword (4 bytes), the operation is repeated 128 times (value in ECX). The block 
of memory initially contained 0. Proc essor 1 is reading two memory locations that are part of the memory block 
being updated by processor 0, i.e, readin g locations in the range _x to (_x+511).
It is possible for processor 1 to perceive that the repeated  string stores in processor 0 are happening out of order. 
Assume that fast string operations are enabled on processor 0.
In Example 9-12, processor 0 does two separate rounds of  rep stosd operation of 128 doubleword stores, writing 
the value 1 (value in EAX) into the firs t block of 512 bytes from location _x (k ept in ES:EDI) in ascending order. It 
then writes 1 into a second block of memory from (_x+ 512) to (_x+1023). All of the memory locations initially 
contain 0. The block of memory initially contained 0. Proc essor 1 performs two load operations from the two blocks 
of memory.Example 9-11.  Stores Within a St ring Operation May be Reordered
rep:stosd [ _x] mov r1, [ _z]
mov r2, [ _y]
Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x 
Initially [_x] to 511[_x]= 0, _x <= _y < _z < _x+512
r1 = 1 and r2 = 0 is allowedVol. 3A 9-15MULTIPLE-PROCESSOR MANAGEMENT
It is not possible in the above example for processor 1 to pe rceive any of the stores from the later string operation 
(to the second 512 block) in processor 0 before seeing the stores from the earlier string operation to the first 512 
block. 
The above example assumes that writes to the second bl ock (_x+512 to _x+1023) does not get executed while 
processor 0’s string operation to the first block has been interrupted. If the string operation to the first block by 
processor 0 is interrupted, and a write to the second memory  block is executed by the interrupt handler, then that 
change in the second memory block will be visible before  the string operation to the first memory block resumes.
In Example 9-13, processor 0 does one round of (128 iterat ions) doubleword string store operation via rep:stosd, 
writing the value 1 (value in EAX) into a block of 512 bytes from location _x (kept in ES:EDI) in ascending order. It 
then writes to a second memory location outside the memo ry block of the previous string operation. Processor 1 
performs two read operations, the first read is from an address outside the 512-byte block but to be updated by 
processor 0, the second ready is from inside the block of memory of string operation.
Processor 1 cannot perceive the later store by processor 0 until it sees all the stores from the string operation. 
Example 9-13 assumes that processor 0’s store to [_z] is  not executed while the string operation has been inter-
rupted. If the string operation is interrupted and the stor e to [_z] by processor 0 is executed by the interrupt 
handler, then changes to [_z] will become visible before the string operation resumes. 
Example 9-14 illustrates the visibility princi ple when a string oper ation is interrupted. Example 9-12.  Stores Across Stri ng Operations Are not Reordered
rep:stosd [ _x]
mov r1, [ _z]
mov ecx, $128
rep:stosd 512[ _x]Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x 
Initially [_x] to 1023[_x]= 0, _x <= _y < _x+512 < _z < _x+1024
r1 = 1 and r2 = 0 is not allowed
Example 9-13.  String Operations Are not Reordered with later Stores
rep:stosd [ _x] mov r1, [ _z]mov [_z], $1 mov r2, [ _y]Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x 
Initially [_y] = [_z] = 0, [_x] to 511[_x]= 0, _x <= _y < _x+512, _z is a separate memory location
Example 9-14.  Interrupted String Operation
rep:stosd [ _x] // interrupted before es:edi reach _y mov r1, [ _z]mov [_z], $1 // interrupt handler mov r2, [ _y]Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x 
Initially [_y] = [_z] = 0, [_x] to 511[_x]= 0, _x  <= _y < _x+512, _z is a separate memory location
r1 = 1 and r2 = 0 is allowed9-16 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
In Example 9-14, processor 0 started a string operation to write to a memory block of 512 bytes starting at address 
_x. Processor 0 got interrupted after k iterations of stor e operations. The address _y has not yet been updated by 
processor 0 when processor 0 got interrupted. The interrupt handler that took control on processor 0 writes to the 
address _z. Processor 1 may see the store to _z from the interrupt handler, before seeing the remaining stores to 
the 512-byte memory block that are executed when the string operation resumes.
Example 9-15 illustrates the ordering of string operations with earlier stores. No store from a string operation can 
be visible before all prior stores are visible.
9.2.5 Strengthening or Weaken ing the Memory-Ordering Model
The Intel 64 and IA-32 architectures provide several me chanisms for strengthening or weakening the memory-
ordering model to handle special programmi ng situations. These mechanisms include:
•The I/O instructions, locked instructions, the LOCK prefix , and serializing instructions force stronger ordering 
on the processor.
•The SFENCE instruction (introduced to the IA-32 architecture in the Pentium III processor) and the LFENCE and 
MFENCE instructions (introduced in the Pentium 4 processor) provide memory-ordering and serialization capabilities for specific types of memory operations.
•The memory type range registers (MTRRs) can be used to  strengthen or weaken memory ordering for specific 
area of physical memory (see Section 12.11, “Memor y Type Range Registers (MTRRs)”). MTRRs are available 
only in the Pentium 4, Intel Xeon, and P6 family processors. 
•The page attribute table (PAT) can be used to strengthen memory ordering for a specific page or group of pages 
(see Section 12.12, “Page Attribute Table (PAT)”). The PA T is available only in the Pentium 4, Intel Xeon, and 
Pentium III processors. 
These mechanisms can be used as follows:
Memory mapped devices and other I/O devices on the bus are often sensitive to the order of writes to their I/O 
buffers. I/O instructions can be used to (the IN and OUT instructions) impose strong write ordering on such 
accesses as follows. Prior to executing an I/O instruction, the processor waits for all previous instructions in the 
program to complete and for all buffered writes to drain to memory. Only instruction fetch and page tables walks 
can pass I/O instructions. Execution of subsequent instructions do not begin until the processor determines that 
the I/O instruction has been completed.
Synchronization mechanisms in multiple-processor system s may depend upon a strong memory-ordering model. 
Here, a program can use a locked instruction such as the XCHG  instruction or the LOCK prefix to ensure that a read-
modify-write operation on memory is carried out atomically . Locked instructions typically operate like I/O instruc-
tions in that they wait for all previous memory accesses to  complete and for all buffered writes to drain to memory 
(see Section 9.1.2, “Bus Locking”). Unlike I/O operations, locked instructions do not wait for all previous instruc-
tions to complete execution.
Program synchronization can also be carried out with serializing instructions (see Section 9.3). These instructions 
are typically used at critical procedure or task boundaries to force completion of all previous instructions before a jump to a new section of code or a context switch occurs . Like the I/O instructions, the processor waits until all 
previous instructions have been completed and all buffere d writes have been drained to memory before executing 
the serializing instruction.Example 9-15.  String Operations Ar e not Reordered with Earlier Stores
mov [_z], $1 mov r1, [ _y]rep:stosd [ _x] mov r2, [ _z]Initially on processor 0: EAX = 1, ECX=128, ES:EDI =_x 
r1 = 1 and r2 = 0 is not allowedVol. 3A 9-17MULTIPLE-PROCESSOR MANAGEMENT
The SFENCE, LFENCE, and MFENCE instructions provide a performance-efficient way of ensuring load and store

The SFENCE, LFENCE, and MFENCE instructions provide a performance-efficient way of ensuring load and store 
memory ordering between routines that produce weakly-ord ered results and routines that consume that data. The 
functions of these instructions are as follows:
•SFENCE  — Serializes all store (write) operations that occurred prior to the SFENCE instruction in the program 
instruction stream, but does not affect load operations.
•LFENCE  — Serializes all load (read) operations that occu rred prior to the LFENCE instruction in the program 
instruction stream, but does not affect store operations.4
•MFENCE  — Serializes all store and load operations that  occurred prior to the MFENCE instruction in the 
program instruction stream.
Note that the SFENCE, LFENCE, and MFENCE instructions provide a more efficient method of controlling memory 
ordering than the CPUID instruction.
The MTRRs were introduced in the P6 family processors to  define the cache characteristics for specified areas of 
physical memory. The following are two examples of how memory types set up with MTRRs can be used strengthen 
or weaken memory ordering for the Pentium 4, Intel Xeon, and P6 family processors:
•The strong uncached (UC) memory type forces a stro ng-ordering model on memory accesses. Here, all reads 
and writes to the UC memory region appear on the bus and out-of-order or speculative accesses are not 
performed. This memory type can be applied to an ad dress range dedicated to memory mapped I/O devices to 
force strong memory ordering.
•For areas of memory where weak ordering is acceptab le, the write back (WB) me mory type can be chosen. 
Here, reads can be performed speculatively and writes ca n be buffered and combined. For this type of memory, 
cache locking is performed on atomic (locked) operations that do not split across cache lines, which helps to 
reduce the performance penalty associated with the use of the typical synchronization instructions, such as 
XCHG, that lock the bus during the entire read-modify-write operation. With the WB memory type, the XCHG 
instruction locks the cache instead of the bus if the memory access is contained within a cache line.
The PAT was introduced in the Pentium III processor to enhance the caching characteristics that can be assigned to 
pages or groups of pages. The PAT mechanism typically used to strengthen caching characteristics at the page level 
with respect to the caching characteristics established by the MTRRs. Table 12-7 shows the interaction of the PAT 
with the MTRRs.
Intel recommends that software written to run on Intel Co re 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, Intel 
Xeon, and P6 family processors assume the processor-or dering model or a weaker memory-ordering model. The 
Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, Intel Xeon, and P6 family processors do not implement a 
strong memory-ordering model, except when using the UC  memory type. Despite the fact that Pentium 4, Intel 
Xeon, and P6 family processors support processor ordering , Intel does not guarantee that future processors will 
support this model. To make software portable to future processors, it is recommended that operating systems 
provide critical region and resource control constructs and API’s (application program interfaces) based on I/O, locking, and/or serializing instructions be used to sy nchronize access to shared areas of memory in multiple-
processor systems. Also, software should not depend on processor ordering in situations where the system hard-
ware does not support this memory-ordering model.
9.3 SERIALIZING INSTRUCTIONS
The Intel 64 and IA-32 architectures define several serializing instructions . These instructions force the 
processor to complete all modifications to flags, registers, and memory by previous instructions and to drain all buffered writes to memory before the next instructio n is fetched and executed. For example, when a MOV to 
control register instruction is used to load a new value into control register CR0 to enable protected mode, the 
processor must perform a serializing operation before it enters protected mode. This serializing operation ensures 
4. Specifically, LFENCE does not execute until all prior instruct ions have completed locally, and no later instruction begins ex ecution 
until LFENCE completes. As a resu lt, an instruction that loads from memory and th at precedes an LFENCE receives data from mem-
ory prior to completion of the LFENCE. An LFENCE that follows an instruction that stores to memo ry might complete  before the da ta 
being stored have become globally visible. Instructions following  an LFENCE may be fetched from  memory before the LFENCE, but 
they will not execute until the LFENCE completes.9-18 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
that all operations that were started while the processor was in real-address mode are completed before the switch 
to protected mode is made.
The concept of serializing instructions was introduced in to the IA-32 architecture with the Pentium processor to 
support parallel instruction execution. Serializing instructio ns have no meaning for the Intel486 and earlier proces-
sors that do not implement parallel instruction execution.
It is important to note that executing of serializing instructions on P6 and more recent processor families constrain 
speculative execution because the results of speculativ ely executed instructions are discarded. The following 
instructions are serializing instructions:
•Privileged serializing instructions  — INVD, INVEPT, INVLPG, INVVPID, LGDT, LIDT, LLDT, LTR, MOV (to 
control register, with the exception of MOV CR85), MOV (to debug register), WBINVD, and WRMSR6.
•Non-privileged serializing instructions  — CPUID, IRET, RSM, and SERIALIZE.
When the processor serializes instruction execution, it en sures that all pending memory transactions are completed 
(including writes stored in its store buffer) before it executes the next  instruction. Nothing can pass a serializing 
instruction and a serializing instruction cannot pass any other instruction (read, write, instruction fetch, or I/O). For 
example, CPUID can be executed at any privilege level to serialize instruction execution with no effect on program 
flow, except that the EAX, EBX, EC X, and EDX registers are modified.
The following instructions are memory-ordering instructio ns, not serializing instructions. These drain the data 
memory subsystem. They do not serialize the instruction execution stream:7
•Non-privileged memory -ordering instructions  — SFENCE, LFENCE, and MFENCE.
The SFENCE, LFENCE, and MFENCE instructions provide more  granularity in controlling the serialization of memory 
loads and stores (see Section 9.2.5, “Strengthe ning or Weakening the Memory-Ordering Model”).
The following additional information is worth noting regarding serializing instructions:
•The processor does not write back the contents of modified  data in its data cache to external memory when it 
serializes instruction execution. Software can force modi fied data to be written back by executing the WBINVD 
instruction, which is a serializing inst ruction. The amount of time or cycl es for WBINVD to complete will vary 
due to the size of different cache hierarchies and othe r factors. As a consequence, the use of the WBINVD 
instruction can have an impact on interrupt/event response time.
•When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register 
CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is 
fetched with the new setting of the PG flag (that is, pa ging is enabled or disabled), but the jump instruction 
itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require 
the jump operation following the move to register CR0 (b ecause any use of the MOV instruction in a Pentium 4, 
Intel Xeon, or P6 family processor to write to CR0 is completely serializing). However, to maintain backwards 
and forward compatibility with code written to run on ot her IA-32 processors, it is recommended that the jump 
operation be performed.
•Whenever an instruction is executed to change the conten ts of CR3 while paging is enabled, the next instruction 
is fetched using the translation tables that correspond to  the new value of CR3. Ther efore the next instruction 
and the sequentially following instructions should have  a mapping based upon the new value of CR3. (Global 
entries in the TLBs are not invalidated, see Section 4.10.4, “Invalidation of TLBs and Paging-Structure 
Caches.”)
•The Pentium processor and more recent processor families use branch-prediction techniques to improve performance by prefetching the destination of a branch instruction before the branch instruction is executed. 
Consequently, instruction execution is not deterministically serialized when a branch instruction is executed.
5. MOV CR8 is not defined architecturally as a serializing instruction.

Caches.”)
6. An execution of WRMSR to any non-serializing MSR is not serializing. Non-serializing MSRs include the following: IA32_SPEC_CT RL 
MSR (MSR index 48H), IA32_PRED_CMD MSR (MSR index 49H), IA32_TSX_CTRL MSR (MSR index 122H), IA32_TSC_DEADLINE MSR (MSR index 6E0H), IA32_PKRS MSR (MSR in dex 6E1H), IA32_HWP_REQUEST MSR (MSR index 774H), or any of the x2APIC MSRs 
(MSR indices 802H to 83FH).
7. LFENCE does provide some guarantees on instruction ordering. It does not execute until all pr ior instructions have completed locally, 
and no later instruction begins execution until LFENCE completes.Vol. 3A 9-19MULTIPLE-PROCESSOR MANAGEMENT
9.4 MULTIPLE-PROCESSOR (MP) INITIALIZATION
The IA-32 architecture (beginning with the P6 family pr ocessors) defines a multiple-processor (MP) initialization 
protocol called the Multiprocessor Specification Version 1.4. This specification defines the boot protocol to be used 
by IA-32 processors in multiple-processor systems. (Here, multiple processors  is defined as two or more proces-
sors.) The MP initialization protocol has the following important features:
•It supports controlled booting of multiple processo rs without requiring dedicated system hardware.
•It allows hardware to initiate the booting of a system without the need for a dedicated signal or a predefined 
boot processor.
•It allows all IA-32 processors to be booted in th e same manner, including those supporting Intel Hyper-
Threading Technology.
•The MP initialization protocol also applies to MP systems using Intel 64 processors.
The mechanism for carrying out the MP initialization protocol  differs depending on the Intel processor generations. 
The following bullets summarizes  the evolution of the changes:
•For P6 family or older proce ssors supporting MP operations — The selection of the BSP and APs (see 
Section 9.4.1, “BSP and AP Processors”) is handled thro ugh arbitration on the APIC bus, using BIPI and FIPI 
messages. These processor generations have CPUI D signatures of (family=06H, extended_model=0, 
model<=0DH), or family <06H. See Se ction 9.11.1, “Overview of the MP Initialization Process for P6 Family 
Processors,” for a complete discussion of MP  initialization for P6 family processors.
•Early generations of IA pr ocessors with family 0FH  — The selection of the BSP and APs (see Section 
9.4.1, “BSP and AP Processors”) is handled through arbitration on the system bus, using BIPI and FIPI 
messages (see Section 9.4.3, “MP Initialization Prot ocol Algorithm for MP Systems”). These processor 
generations have CPUID signatures of family=0FH, model=0H, stepping<=09H.
•Later generations of IA  processors with family 0FH, an d IA processors with system bus — The 
selection of the BSP and APs is handled through a spec ial system bus cycle, without using BIPI and FIPI 
message arbitration (see Section 9.4.3, “MP Initializa tion Protocol Algorithm for MP Systems”). These 
processor generations have CPUID signatures of family =0FH with (model=0H, step ping>=0AH) or (model >0, 
all steppings); or family=06H, extended_model=0, model>=0EH.
•All other modern IA processor gene rations supporting MP operations — The selection of the BSP and 
APs in the system is handled by platform-specific arra ngement of the combination of hardware, BIOS, and/or 
configuration input options. The basis of the selection me chanism is similar to those of the Later generations of 
family 0FH and other Intel processor using system bus (s ee Section 9.4.3, “MP Initialization Protocol Algorithm 
for MP Systems”). These processor generations have CPUID signatures of family=06H, extended_model>0.
The family, model, and stepping ID for a processor is gi ven in the EAX register when the CPUID instruction is 
executed with a value of 1 in the EAX register.
9.4.1 BSP and AP Processors
The MP initialization protocol defines two classes of pr ocessors: the bootstrap processor (BSP) and the application 
processors (APs). Following a power-up or RESET of an MP system, system hardware dynamically selects one of 
the processors on the system bus as the BSP. The remaining processors are designated as APs.
As part of the BSP selection mechanism, the BSP flag is set in the IA32_APIC_BASE MSR (see Figure 11-5) of the 
BSP, indicating that it is the BSP. This flag is cleared for all other processors. 
The BSP executes the BIOS’s boot-strap code to configur e the APIC environment, sets up system-wide data struc-
tures, and starts and initializes the APs. When the BSP and APs are initializ ed, the BSP then begins executing the 
operating-system initialization code.
Following a power-up or reset, the APs complete a minimal se lf-configuration, then wait for a startup signal (a SIPI 
message) from the BSP processor. Upon receiving a SIPI message, an AP executes the BIOS AP configuration code, 
which ends with the AP being placed in halt state.
For Intel 64 and IA-32 processors support ing Intel Hyper-Threading Technology, the MP initialization protocol treats 
each of the logical processors on the system bus or coherent link domain as a separate processor (with a unique 9-20 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
APIC ID). During boot-up, one of the logical processors is selected as the BSP and the remainder of the logical 
processors are designated as APs.
9.4.2 MP Initialization Protocol  Requirements and Restrictions
The MP initialization protocol imposes the followi ng requirements and restrictions on the system:
•The MP protocol is executed only af ter a power-up or RESET. If the MP protocol has completed and a BSP is 
chosen, subsequent INITs (either to a specific processor or system wide) do not cause the MP protocol to be 
repeated. Instead, each logical processor examines it s BSP flag (in the IA32_APIC_BASE MSR) to determine 
whether it should execute the BIOS boot-strap code (if it is the BSP) or enter a wait-for-SIPI state (if it is an 
AP).
•All devices in the system that are capable of delivering interrupts to the processors must be inhibited from 
doing so for the duration of the MP initialization protoc ol. The time during which interrupts must be inhibited 
includes the window between when the BSP issues an INIT-SIPI-SIPI sequence to an AP and when the AP 
responds to the last SIPI in the sequence.
9.4.3 MP Initialization Prot ocol Algorithm for MP Systems
Following a power-up or RESET of an MP system, the proce ssors in the system execute the MP initialization protocol 
algorithm to initialize each of the logical processors on the system bus or coherent link domain. In the course of executing this algorithm, the following boot-up and initialization operations are carried out:
1. Each logical processor is assigned a unique APIC ID, based on system topology. The unique ID is a 32-bit value 
if the processor supports CPUID leaf 0BH,  otherwise the unique ID is an 8-bit value. (see Section 9.4.5, “Identi-
fying Logical Processors in an MP System”). 
2. Each logical processor is assigned a unique arbitration priority based on its APIC ID.
3. Each logical processor executes its internal BIST simultaneously with the other logical processors in the 
system. 
4. Upon completion of the BIST, the logical processors use a hardware-defined selection mechanism to select the 
BSP and the APs from the available logical processors on the system bus. The BSP selection mechanism differs 
depending on the family, model, and steppi ng IDs of the processors, as follows: 
— Later generations of IA processors within family 0FH (see Section 9.4), IA processors with system bus 
(family=06H, extended_model=0, mode l>=0EH), or all other modern Intel processors (family=06H, 
extended_model>0):
•The logical processors begin monitoring the BNR# si gnal, which is toggling. When the BNR# pin stops 
toggling, each processor attempts to issue a NOP special cycle on the system bus. 
•The logical processor with the highest arbitration priority succeeds in issuing a NOP special cycle and is 
nominated the BSP. This processor sets the BSP fl ag in its IA32_APIC_BASE MSR, then fetches and 
begins executing BIOS boot-strap code, beginning  at the reset vector (physical address FFFF FFF0H).
•The remaining logical processors (that failed in issuin g a NOP special cycle) are designated as APs. They 
leave their BSP flags in the clear state and enter a “wait-for-SIPI state.”
— Early generations of IA processors within family 0FH (family=0FH, model=0H, st epping<=09H), P6 family 
or older processors supporting MP operations (fam ily=06H, extended_model=0, model<=0DH; or family 
<06H):
•Each processor broadcasts a BIPI to “all including self.” The first processor that broadcasts a BIPI (and 
thus receives its own BIPI vector), selects itself as  the BSP and sets the BSP flag in its IA32_APIC_BASE 
MSR. (See Section 9.11.1, “Overview of the MP Init ialization Process for P6 Family Processors,” for a 
description of the BIPI, FIPI, and SIPI messages.)

<06H):
•The remainder of the processors (which were not se lected as the BSP) are designated as APs. They 
•The newly established BSP broadcasts an FIPI message to “all including self,” which the BSP and APs 
treat as an end of MP initialization signal. Only the processor with its BSP flag set responds to the FIPI Vol. 3A 9-21MULTIPLE-PROCESSOR MANAGEMENT
message. It responds by fetching and executing th e BIOS boot-strap code, beginning at the reset 
vector (physical address FFFF FFF0H).
5. As part of the boot-strap code, the BS P creates an ACPI table and/or an MP table and adds its initial APIC ID to 
these tables as appropriate. 
6. At the end of the boot-strap procedure, the BSP sets a processor counter to 1, then broadcasts a SIPI message 
to all the APs in the system. Here, the SIPI message cont ains a vector to the BIOS AP initialization code (at 
000VV000H, where VV is the vector contained in the SIPI message).
7. The first action of the AP initialization code is to set up a race (among the APs) to a BIOS initialization 
semaphore. The first AP to the semaphore begins executing the initialization code. (See Section 9.4.4, “MP 
Initialization Example,” for semaphore implementation deta ils.) As part of the AP initialization procedure, the 
AP adds its APIC ID number to the ACPI and/or MP tabl es as appropriate and increments the processor counter 
by 1. At the completion of the initialization procedur e, the AP executes a CLI instruction and halts itself.
8. When each of the APs has gained access to the sema phore and executed the AP initialization code, the BSP 
establishes a count for the number of processors connect ed to the system bus, completes executing the BIOS 
boot-strap code, and then begins executing operating-system boot-strap and start-up code.
9. While the BSP is executing operating-system boot-strap and start-up code, the APs remain in the halted state. 
In this state they will respond only to INITs, NMIs, and SMIs. They will also respond to snoops and to assertions 
of the STPCLK# pin.
The following section gives an example (with code) of the MP  initialization protocol for of multiple processors oper-
ating in an MP configuration.
Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectu res Software Developer’s 
Manual, Volume 4, describes how to program the LINT[0:1] pins of the processor’s local APICs after an MP config-
uration has been completed.
9.4.4 MP Initialization Example
The following example illustrates the use of the MP initializ ation protocol used to initialize processors in an MP 
system after the BSP and APs have been established. The code runs on Intel 64 or IA-32 processors that use a 
protocol. This includes P6 Family processors, Pentium 4 processors, Intel Core Duo, Intel Core 2 Duo and Intel Xeon 
The following constants and data definitions are used in the accompanying 
code examples. They are based on the addresses of the APIC registers defined in Table 11-1.
ICR_LOW EQU 0FEE00300H
SVR EQU 0FEE000F0HAPIC_ID EQU 0FEE00020HLVT3 EQU 0FEE00370HAPIC_ENABLED EQU 0100HBOOT_ID DD ?COUNT EQU 00HVACANT EQU 00H
9.4.4.1  Typical BSP Initialization Sequence
After the BSP and APs have been selected (by means of a hardware protocol, see Section 9.4.3, “MP Initialization 
Protocol Algorithm for MP Systems”), the BSP begins exec uting BIOS boot-strap code (POST) at the normal IA-32 
architecture starting address (FFFF FFF0H). The boot-str ap code typically performs the following operations:
1. Initializes memory.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs.4. Enables the caches.9-22 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
5. Executes the CPUID instruction with a value of 0H in  the EAX register, then reads the EBX, ECX, and EDX 
registers to determine if the BSP is “GenuineIntel.”
6. Executes the CPUID instruction with a value of 1H in th e EAX register, then saves th e values in the EAX, ECX, 
and EDX registers in a system configuration space in RAM for use later.
7. Loads start-up code for the AP to execute into  a 4-KByte page in the lower 1 MByte of memory.
8. Switches to protected mode and ensures that the APIC address space is mapped to the strong uncacheable 
(UC) memory type.
9. Determine the BSP’s APIC ID from the local APIC ID re gister (default is 0), the code snippet below is an 
example that applies to logical processors in a system whose local APIC units operate in xAPIC mode that APIC 
registers are accessed using memory mapped interface:
MOV ESI, APIC_ID; Address of local APIC ID register
MOV EAX, [ESI];AND EAX, 0FF000000H; Zero out all other bits except APIC IDMOV BOOT_ID, EAX; Save in memory
Saves the APIC ID in the ACPI and/or MP tables and optionally in the system configuration space in RAM.
10. Converts the base address of the 4-KByte page for the AP’s bootup code into 8-bit vector. The 8-bit vector 
defines the address of a 4-KByte page in the real-add ress mode address space (1-MByte space). For example, 
a vector of 0BDH specifies a star t-up memory address of 000BD000H. 
11. Enables the local APIC by setting bit 8 of  the APIC spurious vector register (SVR).
MOV ESI, SVR; Address of SVR
MOV EAX, [ESI];OR  EAX, APIC_ENABLED; Set bi t 8 to enable (0 on reset)
MOV [ESI], EAX;
12. Sets up the LVT error handling entry by establishing an 8-bit vector for the APIC error handler.
MOV ESI, LVT3;
MOV EAX, [ESI];AND EAX, FFFFFF00H; Clear out previous vector.OR EAX, 000000xxH; xx is the 8-bi t vector the APIC error handler. 
13. Initializes the Lock Semaphore variable VACANT to 00H . The APs use this semaphore to determine the order in 
which they execute BIOS AP initialization code.
14. Performs the following operation to set up the BSP to detect the presence of APs in the system and the number 
of processors (within a finite duration, minimally 100 milliseconds):
— Sets the value of the COUNT variable to 1.
— In the AP BIOS initialization code, the AP will increm ent the COUNT variable to indicate its presence. The 
finite duration while waiting for the COUNT to be upda ted can be accomplished with a timer. When the timer 
expires, the BSP checks the value of the COUNT variab le. If the timer expires and the COUNT variable has 
not been incremented, no APs are present or some error has occurred.
15. Broadcasts an INIT-SIPI-SIPI IPI sequence to the APs to wake them up and initialize them. Alternatively, 
following a power-up or RESET, since all APs are already in the “wait-for-SIPI state,” the BSP can broadcast just 
a single SIPI IPI to the APs to wake them up and initia lize them. If software knows how many logical processors 
it expects to wake up, it may choose to poll the COUNT va riable. If the expected processors show up before the 
100 millisecond timer expires, the timer can be canceled and skip to step 16. 
The left-hand-side of the procedure illustrated in Table 9-1 provides an algorithm when the expected processor 
count is unknown. The right-hand-side of Table 9-1 can be used when the expected processor count is known. Vol. 3A 9-23MULTIPLE-PROCESSOR MANAGEMENT
16. Reads and evaluates the COUNT variable and establishes a processor count.
17. If necessary, reconfigures the APIC and continues wi th the remaining system diagnostics as appropriate.
9.4.4.2  Typical AP In itialization Sequence
When an AP receives the SIPI, it begins  executing BIOS AP initialization code at the vector encoded in the SIPI. The 
AP initialization code typically performs the following operations:
1. Waits on the BIOS initialization Lock Semaphore. When  control of the semaphore is attained, initialization 
continues.
2. Loads the microcode update into the processor.3. Initializes the MTRRs (using the same mapping that was used for the BSP).
4. Enables the cache.
registers to determine if the AP is “GenuineIntel.”
6. Executes the CPUID instruction with a value of 1H in th e EAX register, then saves the values in the EAX, ECX, 
7. Switches to protected mode and ensures that the APIC address space is mapped to the strong uncacheable 
8. Determines the AP’s APIC ID from the local APIC ID register, and adds it to th e MP and ACPI tables and 
optionally to the system configuration space in RAM.
9. Initializes and configures the local APIC by setting bit 8 in the SVR register and setting up the LVT3 (error LVT) 
for error handling (as described in steps 9 and 10 in Se ction 9.4.4.1, “Typical BSP Initialization Sequence”).
10. Configures the APs SMI execution environment. (Each AP  and the BSP must have a different SMBASE address.)
11. Increments the COUNT variable by 1.
12. Releases the semaphore.

13. Executes one of the following:Table 9-1.  Broadcast INIT-SIPI-SIPI Sequence and Choice of Timeouts 
INIT-SIPI-SIPI when the expected processor count is unknown INIT-SIPI-SIPI when the expected processor count is known
MOV ESI, ICR_LOW; Load address of ICR low dword into ESI.
MOV EAX, 000C4500H; Load ICR encoding for broadcast INIT IPI 
; to all APs into EAX.
MOV [ESI], EAX; Broadcas t INIT IPI to all APs
; 10-millisecond delay loop.
MOV EAX, 000C46XXH; Load ICR encoding for broadcast SIPI IP
; to all APs into EAX, where xx is the vector computed in step 10.MOV [ESI], EAX; Broadcast SIPI IPI to all APs
; 200-microsecond delay loop
MOV [ESI], EAX; Broadcast second SIPI IPI to all APs
;Waits for the timer interr upt until the timer expiresMOV ESI, ICR_LOW; Load address of ICR low dword into ESI.
MOV EAX, 000C4500H; Load ICR en coding for broadcast INIT IPI 
; to all APs into EAX, where xx is  the vector comput ed in step 10.
MOV [ESI], EAX; Broadcas t SIPI IPI to all APs
; 200 microsecond delay loop with check to see if COUNT has
; reached the expected processor count. If COUNT reaches
; expected processor count, cancel timer and go to step 16.
MOV [ESI], EAX; Broadcast se cond SIPI IPI to all APs
; Wait for the timer interrupt polling COUNT. If COUNT reaches
; If timer expires,  go to step 16.9-24 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
— the CLI and HLT instructions (if MONITOR/MWAIT is not supported), or
— the CLI, MONITOR, and MWAIT sequence to enter a deep C-state.
14. Waits for an INIT IPI.
9.4.5 Identifying Logical Processors in an MP System
After the BIOS has completed the MP init ialization protocol, each logical processor can be uniquely identified by its 
local APIC ID. Software can access these AP IC IDs in either of the following ways:
•Read APIC ID for a local APIC  — Code running on a logical processor can read APIC ID in one of two ways 
depending on the local APIC unit is operat ing in x2APIC mode or in xAPIC mode:
— If the local APIC unit supports x2APIC and is operat ing in x2APIC mode, 32-bit APIC ID can be read by 
executing a RDMSR instruction to read the processor’s x2APIC ID register. This method is equivalent to 
executing CPUID leaf 0BH described below.
— If the local APIC unit is operating in xAPIC mode, 8-bi t APIC ID can be read by executing a MOV instruction 
to read the processor’s local APIC ID register (see Section 11.4.6, “Local APIC ID”). This is the ID to use for 
directing physical destination mode interrupts to the processor.
•Read ACPI or MP table  — As part of the MP initialization protocol, the BIOS creates an ACPI table and an MP 
table. These tables are defined in the Multiprocessor Specification Version 1.4 and provide software with a list of the processors in the system and their local APIC IDs.  The format of the ACPI table is derived from the ACPI 
specification, which is an industry standard power mana gement and platform configuration specification for MP 
systems.
•Read Initial APIC ID  (If the processor does not support CPUID leaf 0BH) — An APIC ID is assigned to a logical 
processor during power up. This is the initial APIC ID  reported by CPUID.1:EBX[31:24] and may be different 
from the current value read from the local APIC. The init ial APIC ID can be used to determine the topological 
relationship between logical processors for multi-pr ocessor systems that do not support CPUID leaf 0BH.
Bits in the 8-bit initial APIC ID can be interpreted using several bit masks. Each bit mask can be used to extract 
an identifier to represent a hierarchical domain of the multi-threading resource topology in an MP system (See 
Section 9.9.1, “Hierarchical Mapping of Shared Resources” ). The initial APIC ID may consist of up to four bit-
fields. In a non-clustered MP system, the fi eld consists of up to three bit fields. 
•Read 32-bit APIC ID from CPUID leaf 0BH (If the processor supports CPUID leaf 0BH) — A unique APIC ID 
is assigned to a logical processor during power up. This  APIC ID is reported by CPUID.0BH:EDX[31:0] as a 32-
bit value. Use the 32-bit APIC ID and CPUID leaf 0BH to  determine the topological relationship between logical 
processors if the processor supports CPUID leaf 0BH.
Bits in the 32-bit x2APIC ID can be extracted into su b-fields using CPUID leaf 0BH parameters. (See Section 
9.9.1, “Hierarchical Mapping of Shared Resources”). 
Figure 9-2 shows two examples of APIC ID bit fields in earlier single-core processors. In single-core Intel Xeon 
processors, the APIC ID assigned to a logical processor duri ng power-up and initialization is 8 bits. Bits 2:1 form a 
2-bit physical package identifier (which can also be though t of as a socket identifier). In systems that configure 
physical processors in clusters, bits 4:3 form a 2-bit cluster ID. Bit 0 is used in the Intel Xeon processor MP to iden-tify the two logical processors within th e package (see Section 9.9.3, “Hierarchical ID of Logical Processors in an MP 
System”). For Intel Xeon processors that do not support In tel Hyper-Threading Technology, bit 0 is always set to 0; 
for Intel Xeon processors supporting Intel Hyper-Threading Te chnology, bit 0 performs the same function as it does 
for Intel Xeon processor MP. 
For more recent multi-core processors, see Section 9.9. 1, “Hierarchical Mapping of Shared Resources,” for a 
complete description of the topological relationships between logical processors and bit field locations within an 
initial APIC ID across Intel 64 and IA-32 processor families.
Note the number of bit fields and the width of bit-fields  are dependent on processor and platform hardware capa-
bilities. Software should determine these at runtime. When  initial APIC IDs are assigned to logical processors, the 
value of APIC ID assigned to a logical processor will resp ect the bit-field boundaries corresponding core, physical 
package, etc. Additional examples of the bit fields in the initial APIC ID of multi-threading capable systems are 
shown in Section 9.9.Vol. 3A 9-25MULTIPLE-PROCESSOR MANAGEMENT
For P6 family processors, the APIC ID that is assigned to  a processor during power-up and initialization is 4 bits 
(see Figure 9-2). Here, bits 0 and 1 form a 2-bit processor (or socket) identifier and bits 2 and 3 form a 2-bit cluster 
ID. 
9.5 INTEL® HYPER-THREADING TEC HNOLOGY AND INTEL® MULTI-CORE 
TECHNOLOGY
Intel Hyper-Threading Technology and In tel multi-core technology are extensio ns to Intel 64 and IA-32 architec-
tures that enable a single physical processor to execute two or more separate code streams (called threads ) 
concurrently. In Intel Hyper-Threading Technology, a single processor core provides two logical processors that 
share execution resources (see Section 9.7, “Intel® Hype r-Threading Technology Architecture”). In Intel multi-
core technology, a physical processor package provides tw o or more processor cores. Both configurations require 
chipsets and a BIOS that support the te chnologies.
Software should not rely on processor names to dete rmine whether a processor supports Intel Hyper-Threading 
Technology or Intel multi-core technology. Use the CP UID instruction to determine processor capability (see 
Section 9.6.2, “Initializing Multi-Core Processors”). 
9.6 DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY
Use the CPUID instruction to detect the presence of hard ware multi-threading support in a physical processor. 
Hardware multi-threading can support several varieties of multigrade and/or Intel Hyper-Threading Technology. 
CPUID instruction provides several sets of parameter in formation to aid software enumerating topology informa-
tion. The relevant topology enumeration parameters provided by CPUID include:
•Hardware Multi-Threading feat ure flag (CPUID.1:EDX[28] = 1)  — Indicates when set that the physical 
package is capable of supporting Intel Hyper-Th reading Technology and/or multiple cores. 
•Processor topology enumeration parameters for 8-bit APIC ID :
—Addressable IDs for Logical processors in the same Pa ckage (CPUID.1:EBX[23:16])  — Indicates 
the maximum number of addressable ID for logical processors in a physical package. Within a physical 
package, there may be addressable IDs that are not occupied by any logical processors. This parameter does not represents the hardware capability of the physical processor.
8Figure 9-2.  Interpretation of APIC ID in Early MP Systems0
Processor ID1 7 43 2
ClusterReserved0
Processor ID1 7 43 2 5
ClusterReservedAPIC ID Format for Intel Xeon Processors that
APIC ID Format for P6 Family Processors0do not Support Intel Hyper-Threading Technology9-26 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
•Addressable IDs for processor cores in the same Package9 (CPUID.(EAX=4, ECX=010):EAX[31:26]

•Addressable IDs for processor cores in the same Package9 (CPUID.(EAX=4, ECX=010):EAX[31:26] 
+ 1 = Y) — Indicates the maximum number of addressable IDs attributable to processor cores (Y) in the 
physical package.
•Extended Processor Topology Enumerat ion parameters for 32-bit APIC ID : Intel 64 processors 
supporting CPUID leaf 0BH will assign unique APIC IDs to  each logical processor in the system. CPUID leaf 0BH 
reports the 32-bit APIC ID and provide topology enum eration parameters. See CPUID instruction reference 
pages in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
The CPUID feature flag may indicate support for hardware  multi-threading when only one logical processor avail-
able in the package. In this case, th e decimal value represented by bits 16 through 23 in the EBX register will have 
a value of 1.
Software should note that the number of logical processors  enabled by system software may be less than the value 
of “Addressable IDs for Logical processo rs”. Similarly, the number of cores enabled by system software may be less 
than the value of “Addressabl e IDs for processor cores”.
Software can detect the availability of the CPUID extend ed topology enumeration leaf (0BH) by performing two 
steps:
•Check maximum input value for basic CPUID information by  executing CPUID with EAX= 0. If CPUID.0H:EAX is 
greater than or equal or 11 (0BH), then proceed to next step,
•Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero.
If both of the above conditions are true, extended topolo gy enumeration leaf is available. Note the presence of 
CPUID leaf 0BH in a processor does not guarantee support that the local APIC supports x2APIC. If 
CPUID.(EAX=0BH, ECX=0H ):EBX returns zero and maximum input value for basic CPUID information is greater 
than 0BH, then CPUID.0BH leaf is not supported on that processor.
9.6.1 Initializing Processors Supporting Intel® Hyper-Threading Technology
The initialization process for an MP system that contai ns processors supporting Intel Hyper-Threading Technology 
is the same as for conventional MP systems (see Section 9. 4, “Multiple-Processor (MP) Initialization”). One logical 
processor in the system is selected as the BSP and other processors (or logical processors) are designated as APs. 
The initialization process is identical to that described in Section 9.4.3, “MP Initialization Protocol Algorithm for MP 
Systems,” and Section 9.4.4, “MP Initialization Example.”
During initialization, each logical processor is assigned an APIC ID that is stored in the local APIC ID register for 
each logical processor. If two or more processors suppor ting Intel Hyper-Threading Te chnology are present, each 
logical processor on the system bus is assigned a unique ID  (see Section 9.9.3, “Hierarchical ID of Logical Proces-
sors in an MP System”). Once logical processors have AP IC IDs, software communicates with them by sending APIC 
IPI messages.
9.6.2 Initializing Multi-Core Processors
The initialization process for an MP system that contains multi-core Intel 64 or IA-32 processors is the same as for 
conventional MP systems (see Section 9.4, “Multiple-Processo r (MP) Initialization”). A logical processor in one core 
is selected as the BSP; other logical processors are designated as APs. 
During initialization, each logical processor is assigned an APIC ID. Once logical processors have APIC IDs, software 
may communicate with them by sending APIC IPI messages.
8. Operating system and BIOS may implement features that reduce the number of logical processors available in a platform to appl ica-
tions at runtime to less than the number of physical packages ti mes the number of hardware-capable logical processors per packa ge.
9. Software must check CPUID for its support of leaf 4 when implementing support for multi-core. If CPUID leaf 4 is not availabl e at run-
time, software should handle the situation as if there is only one core per package.
10. Maximum number of cores in the physical package must be queried by executing CPUID with EAX=4 and a valid ECX input value. 
Valid ECX input values start from 0.Vol. 3A 9-27MULTIPLE-PROCESSOR MANAGEMENT
9.6.3 Executing Multiple  Threads on an Intel® 64 or IA- 32 Processor Supporting Hardware 
Multi-Threading
Upon completing the operating system boot-up procedur e, the bootstrap processor (BSP) executes operating 
system code. Other logical processors are placed in the halt  state. To execute a code stream (thread) on a halted 
logical processor, the operating system issues an interprocessor interrupt (IPI) addressed to the halted logical 
processor. In response to the IPI, the processor wakes up  and begins executing the code identified by the vector 
received as part of the IPI. 
To manage execution of multiple threads on logical processors, an operating system can use conventional 
symmetric multiprocessing (SMP) techniques. For example,  the operating-system can use a time-slice or load 
balancing mechanism to periodically interrupt each of the active logical processors. Upon interrupting a logical 
processor, the operating system checks its run queue for a thread waiting to be executed and dispatches the thread 
to the interrupted logical processor.
9.6.4 Handling Interrupts on an IA-32 Proc essor Supporting Hardware Multi-Threading
Interrupts are handled on processors supporting Intel Hype r-Threading Technology as they are on conventional MP 
systems. External interrupts are received by the I/O APIC, which distributes them as interrupt messages to specific 
logical processors (see Figure 9-3). 
Logical processors can also send IPIs to other logical proces sors by writing to the ICR register of its local APIC (see 
Section 11.6, “Issuing Interprocessor Interrupts”).  This also applies to dual-core processors.
9.7 INTEL® HYPER-THREADING TECHNOLOGY ARCHITECTURE
Figure 9-4 shows a generalized view of an Intel proce ssor supporting Intel Hyper-Threading Technology, using the 
original Intel Xeon processor MP as an example. This implementation of the Intel Hyper-Threading Technology  
Figure 9-3.  Local APICs and I/O APIC in MP System Supporting Intel HT TechnologyI/O APIC External
Interrupts
System ChipsetBridge
PCIInterrupt MessagesLocal APICLogical 
Local APICLogical 
Processor 1Hyper-Threading TechnologyIntel Processor with Intel
Bus InterfaceProcessor Core
IPIsInterrupt
MessagesLocal APICLogical 
Messages9-28 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
consists of two logical processors (each represented by a separate architectural state) which share the processor’s 
execution engine and the bus interface. Each logical processor also has its own advanced programmable interrupt controller (APIC).
9.7.1 State of the Logical Processors
The following features are part of the architectural state of  logical processors within Intel 64 or IA-32 processors 
supporting Intel Hyper-Threading Technology. The fe atures can be subdivided into three groups: 
•Duplicated for each logical processor
•Shared by logical processors in a physical processor
•Shared or duplicated, depe nding on the implementation
The following features are duplicated for each logical processor:
•General purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, and EBP)
•Segment registers (CS, DS, SS, ES, FS, and GS)
•EFLAGS and EIP registers. Note that the CS and EIP/RIP registers for each logical processor point to the 
instruction stream for the thread being executed by the logical processor.
•x87 FPU registers (ST0 through ST7, status word, contro l word, tag word, data operand pointer, and instruction 
pointer)
•MMX registers (MM0 through MM7)
•XMM registers (XMM0 through XMM7) and the MXCSR register
•Control registers and system table pointer registers (GDTR, LDTR, IDTR, task register)
•Debug registers (DR0, DR1, DR2, DR3, DR6, DR7) and the debug control MSRs
•Machine check global status (IA32_MCG_STATUS) and machine check capability (IA32_MCG_CAP) MSRs
•Thermal clock modulation and ACPI  Power management control MSRs
•Time stamp counter MSRs
•Most of the other MSR registers, including the page  attribute table (PAT). See the exceptions below.
•Local APIC registers.
•Additional general purpose registers (R8-R15), XMM re gisters (XMM8-XMM15), control register, IA32_EFER on 
Intel 64 processors.
The following features are sh ared by logical processors:Figure 9-4.  IA-32 Processor with Two Logical Processors Su pporting Intel HT TechnologyLogical
Architectural
State
Bus InterfaceLocal APIC Local APICLogical
Processor 1
State
System BusVol. 3A 9-29MULTIPLE-PROCESSOR MANAGEMENT
•Memory type range registers (MTRRs)
Whether the following features are shared or duplicated is implementation-specific:
•IA32_MISC_ENABLE MSR (MSR address 1A0H)
•Machine check architecture (MCA ) MSRs (except for the IA32_MCG_STATUS and IA32_MCG_CAP MSRs)
•Performance monitoring control and counter MSRs
9.7.2 APIC Functionality

State
State
When a processor supporting Intel Hyper- Threading Technology support is init ialized, each logical processor is 
assigned a local APIC ID (see Table 11-1). The local APIC ID serves as an ID for the logical processor and is stored 
in the logical processor’s APIC ID register. If two or mo re processors supporting Inte l Hyper-Threading Technology 
are present in a dual processor (DP) or MP system, each logical processor on the system bus is assigned a unique 
local APIC ID (see Section 9.9.3, “Hierarchical ID of Logical Processors in an MP System”).
Software communicates with local processors using the APIC’s interprocessor interrupt (IPI) messaging facility. 
Setup and programming for APICs is identical in processors  that support and do not su pport Intel Hyper-Threading 
Technology. See Chapter 11, “Advanced Programmable Interrupt Controller (APIC),” for a detailed discussion.
9.7.3 Memory Type Range Registers (MTRR)
MTRRs in a processor supporting Intel Hyper-Threading Te chnology are shared by logical processors. When one 
logical processor updates the setting of the MTRRs, settings are automatically shared with the other logical proces-
sors in the same physical package. 
The architectures require that all MP systems based on Intel 64 and IA-32 processors (this includes logical proces-
sors) must use an identical MTRR memory map. This gives software a consistent view of memory, independent of 
the processor on which it is running . See Section 12.11, “Memory Type Range Registers (MTRRs),” for information 
on setting up MTRRs.
9.7.4 Page Attribute Table (PAT)
Each logical processor has its own PAT MSR (IA32_PAT). Ho wever, as described in Section 12.12, “Page Attribute 
Table (PAT),” the PAT MSR settings must be the same for al l processors in a system, including the logical proces-
sors.
9.7.5 Machine Check Architecture
In the Intel HT Technology context as implem ented by processors based on Intel NetBurst® microarchitecture, all 
of the machine check architecture (MCA) MSRs (excep t for the IA32_MCG_STATUS and IA32_MCG_CAP MSRs) are 
duplicated for each logical processor. This permits logica l processors to initialize, co nfigure, query, and handle 
machine-check exceptions simultaneously within the same  physical processor. The design is compatible with 
machine check exception handlers that follow the guide lines given in Chapter 16, “Machine-Check Architecture.”
The IA32_MCG_STATUS MSR is duplicated for each logical pr ocessor so that its machine check in progress bit field 
(MCIP) can be used to detect recursion on the part of  MCA handlers. In addition, the MSR allows each logical 
processor to determine that a machine-check exception is in progress independent of the actions of another logical 
processor in the same physical package.
Because the logical processors within a physical packag e are tightly coupled with respect to shared hardware 
resources, both logical processors are notified of machine check errors that occur within a given physical processor. 
If machine-check exceptions are enabled when a fatal error is reported, all the logical processors within a physical 
package are dispatched to the machine-check exception ha ndler. If machine-check exceptions are disabled, the 
logical processors enter the shutdown state and assert the IERR# signal.
When enabling machine-check exceptions, the MCE flag in  control register CR4 should be set for each logical 
processor.9-30 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
On Intel Atom family processors that support Intel Hy per-Threading Technology, the MCA facilities are shared 
between all logical processors on the same processor core.
9.7.6 Debug Registers and Extensions
Each logical processor has its own set of debug register s (DR0, DR1, DR2, DR3, DR6, DR7) and its own debug 
control MSR. These can be set to control and record debu g information for each logical processor independently. 
Each logical processor also has its own last branch records (LBR) stack.
9.7.7 Performance Monitoring Counters
Performance counters and their companion control MSRs are shared between the logical processors within a 
processor core for processors based on Intel NetBurst microarchitecture. As a result, software must manage the use of these resources. The performance counter interrupt s, events, and precise event monitoring support can be 
set up and allocated on a per thread (per logical processor) basis. 
See Section 20.6.4, “Performance Monitoring and Intel® Hy per-Threading Technology in Processors Based on Intel 
NetBurst® Microarchitecture,” for a discussion of performance monitoring in the Intel Xeon processor MP. 
In Intel Atom processor family that support Intel Hyper-Thread ing Technology, the performance counters (general-
purpose and fixed-function counters) and their companion control MSRs are duplicated for each logical processor.
9.7.8 IA32_MISC_ENABLE MSR
The IA32_MISC_ENABLE MSR (MSR address 1A0H) is gene rally shared between the logical processors in a 
processor core supporting Intel Hyper-Threading Technolo gy. However, some bit fields within IA32_MISC_ENABLE 
MSR may be duplicated per logical processor. The partition of shared or duplicated bit fields within IA32_MISC_EN-
ABLE is implementation dependent. Software should program duplicated fields carefully on all logical processors in 
the system to ensure consistent behavior.
9.7.9 Memory Ordering
The logical processors in an Intel 64 or IA-32 proce ssor supporting Intel Hyper-Thre ading Technology obey the 
same rules for memory ordering as Intel 64 or IA-32 pr ocessors without Intel HT Technology (see Section 9.2, 
“Memory Ordering”). Each logical processor uses a proce ssor-ordered memory model that can be further defined 
as “write-ordered with store buffer forwarding.” All mechanisms for strengthening or weakening the memory-
ordering model to handle special programming situations apply to each logical processor.
9.7.10 Serializing Instructions
As a general rule, when a logical processor in a processor supporting Intel Hyper-Threading Technology executes a 
serializing instruction, only that logical processor is affected  by the operation. An exception to this rule is the execu-
tion of the WBINVD, INVD, and WRMSR instructions; and the MOV CR instruction when the state of the CD flag in 
control register CR0 is modified. Here, both logical processors are serialized.
9.7.11 Microcode Update Resources
In an Intel processor supporting Intel Hyper-Threading Technology, the microcode update facilities are shared 
between the logical processors; either logical processor can initiate an update. Each logical processor has its own BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR address 8B H). When a logical processor performs an update for 
the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logical processors are updated with identical 
information. If logical processors initiate an update simultaneously, the processor core provides the necessary synchronization needed to ensure that on ly one update is performed at a time. Vol. 3A 9-31MULTIPLE-PROCESSOR MANAGEMENT
NOTE
Some processors (prior to the introduction of Intel 64 Architecture and based on Intel NetBurst 
microarchitecture) do not support simultaneous loading of microcode update to the sibling logical 
processors in the same core. All other processors support logical processors initiating an update simultaneously. Intel recommends a common approach that the microcode loader use the 
sequential technique described in Section 10.11.6.3.
9.7.12 Self Modifying Code
Intel processors supporting Intel Hyper-Threading Techno logy support self-modifying code, where data writes 
modify instructions cached or currently in flight. They also support cross-modifying code, where on an MP system 
writes generated by one processor modify instructions cached  or currently in flight on another. See Section 9.1.3, 
“Handling Self- and Cross-Modifying Code,” for a description of the requirements for self- and cross-modifying code 
in an IA-32 processor.
9.7.13 Implementation-Specific Intel® HT Technology Facilities
The following non-architectural facilities are implementati on-specific in IA-32 processors supporting Intel Hyper-
Threading Technology:
•Caches.
•Translation lookaside buffers (TLBs).
•Thermal monitoring facilities.
The Intel Xeon processor MP implementation  is described in the following sections.
9.7.13.1  Processor Caches
For processors supporting Intel Hyper-Threading Technology, the caches are shared. Any cache manipulation 
instruction that is executed on one logical processor has a global effect on the cache hierarchy of the physical processor. Note the following:
•WBINVD instruction — The entire cache hierarchy is invalidated after modified data is written back to 
memory. All logical processors are stopped from executin g until after the write-back and invalidate operation is 
completed. A special bus cycle is sent to all caching agents. The amount of time or cycles for WBINVD to

•Caches.
completed. A special bus cycle is sent to all caching agents. The amount of time or cycles for WBINVD to 
complete will vary due to the size of different cache hier archies and other factors. As a consequence, the use of 
the WBINVD instruction can have an impact on interrupt/event response time.
•INVD instruction  — The entire cache hierarchy is invalidated without writing back modified data to memory. 
All logical processors are stopped from executing until af ter the invalidate operation is completed. A special bus 
cycle is sent to all caching agents.
•CLFLUSH and CLFLUSHOPT instructions  — The specified cache line is invalidated from the cache hierarchy 
after any modified data is written back to memory and a bus cycle is sent to all caching agents, regardless of 
which logical processor caused the cache line to be filled.
•CD flag in control register CR0  — Each logical processor has its own CR0 control register, and thus its own 
CD flag in CR0. The CD flags for the two logical proc essors are ORed together, such that when any logical 
processor sets its CD flag, the entire cache is nominally disabled. 
9.7.13.2  Processor Translation Lookaside Buffers (TLBs)
In processors supporting Intel Hyper-Threading Technology , data cache TLBs are shared. The instruction cache TLB 
may be duplicated or shared in each logical processo r, depending on implementation specifics of different 
processor families.
Entries in the TLBs are tagged with an ID that indicates th e logical processor that initiated the translation. This tag 
applies even for translations that are marked global us ing the page-global feature fo r memory paging. See Section 
4.10, “Caching Translation Information,” for information about global translations.9-32 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
When a logical processor performs a TLB invalidation operatio n, only the TLB entries that are tagged for that logical 
processor are guaranteed to be flushed. This protocol app lies to all TLB invalidation operations, including writes to 
control registers CR3 and CR4 and uses of the INVLPG instruction.
9.7.13.3  Thermal Monitor
In a processor that supports Intel Hyper-Threading Technology, logical processors share the catastrophic shutdown detector and the automatic thermal monitoring mechanis m (see Section 15.8, “Thermal Monitoring and Protec-
tion”). Sharing results in the following behavior:
•If the processor’s core temperature rises above the preset catastrophic shutdown temperature, the processor 
core halts execution, which causes both logical processors to stop execution.
•When the processor’s core temperature rises above the pr eset automatic thermal monitor trip temperature, the 
frequency of the processor core is automatically modula ted, which effects the execution speed of both logical 
For software controlled clock modulation, each logi cal processor has its own IA32_CLOCK_MODULATION MSR, 
allowing clock modulation to be enabled or disabled on a logical processor basis. Typically, if software controlled 
clock modulation is going to be used, the feature must be  enabled for all the logical processors within a physical 
processor and the modulation duty cycle must be set to the same value for each logical processor. If the duty cycle 
values differ between the logical processors, the proce ssor clock will be modulated at the highest duty cycle 
selected.
9.7.13.4  External Signal Compatibility
This section describes the constraints on external signals received through the pins of a processor supporting Intel 
Hyper-Threading Technology and how these signals are shared between its logical processors.
•STPCLK#  — A single STPCLK# pin is provided on the physical  package of the Intel Xeon processor MP. External 
control logic uses this pin for power management within the system. When the STPCLK# signal is asserted, the processor core transitions to the stop-grant state, where instruction execution is halted but the processor core 
continues to respond to snoop transactions. Regardless of whether the logical processors are active or halted 
when the STPCLK# signal is asserted, execution is stoppe d on both logical processors and neither will respond 
to interrupts.
In MP systems, the STPCLK# pins on all physical processo rs are generally tied together. As a result this signal 
affects all the logical processors within the system simultaneously.
•LINT0 and LINT1 pins  — A processor supporting Intel Hyper-Thread ing Technology has only one set of LINT0 
and LINT1 pins, which are shared between the logical pr ocessors. When one of these pins is asserted, both 
logical processors respond unless the pin has been masked in  the APIC local vector tables for one or both of the 
logical processors.
Typically in MP systems, the LINT0 and LINT1 pins are no t used to deliver interrupts to the logical processors. 
Instead all interrupts are delivered to the local processors through the I/O APIC.
•A20M# pin  — On an IA-32 processor, the A20M# pin is typica lly provided for compatibility with the Intel 286 
processor. Asserting this pin causes bit 20 of the physical  address to be masked (forced to zero) for all external 
bus memory accesses. Processors supporting Intel Hype r-Threading Technology provide one A20M# pin, which 
affects the operation of both logical processors within the physical processor. 
The functionality of A20M# is used primarily by olde r operating systems and not used by modern operating 
systems. On newer Intel 64 processors, A20M# may be absent. 
9.8 MULTI-CORE ARCHITECTURE
This section describes the architecture of Intel 64 and IA -32 processors supporting dual-core and quad-core tech-
nology. The discussion is applicable to the Intel Pentiu m processor Extreme Edition, Pentium D, Intel Core Duo, 
Intel Core 2 Duo, Dual-core Intel Xeon processor, Intel Core 2 Quad processors, and quad-core Intel Xeon proces-
sors. Features vary across different microarchitectures and are detectable using CPUID.Vol. 3A 9-33MULTIPLE-PROCESSOR MANAGEMENT
In general, each processor core has dedicated microarchi tectural resources identical to a single-processor imple-
mentation of the underlying microarchitecture without hardware multi-threading capability. Each logical processor in a dual-core processor (whether supporting Intel Hyper- Threading Technology or not) has its own APIC function-
ality, PAT, machine check architecture, debug registers and extensions. Each logical processor handles serialization 
instructions or self-modifying code on its own. Memory order is handled the same way as in Intel Hyper-Threading 
Technology.
The topology of the cache hierarchy (with respect to wh ether a given cache level is shared by one or more 
processor cores or by all logical processors in the phys ical package) depends on the processor implementation. 
Software must use the deterministic cache parameter leaf of CPUID instruction to discover the cache-sharing 
topology between the logical processors in a multi-threading environment.
9.8.1 Logical Processor Support
The topological composition of processor cores and logical processors in a multi-core processor can be discovered using CPUID. Within each processor core, one or more logical processors may be available. 
System software must follow the requirement MP initia lization sequences (see Section 9.4, “Multiple-Processor 
(MP) Initialization”) to recognize and enable logical proc essors. At runtime, software can enumerate those logical 
processors enabled by system software to identify the topological relationships between these logical processors. 
(See Section 9.9.5, “Identifying Topolo gical Relationships in an MP System”). 
9.8.2 Memory Type Range Registers (MTRR)
MTRR is shared between two logical processors sharing a processor core if the physical processor supports Intel 
Hyper-Threading Technology. MTRR is not shared between logical processors located in different cores or different 
physical packages. 
The Intel 64 and IA-32 architectures require that all logi cal processors in an MP system use an identical MTRR 
memory map. This gives software a consistent view of memory, independent of the processor on which it is running. 
See Section 12.11, “Memory Type Range Registers (MTRRs).”
9.8.3 Performance Monitoring Counters
Performance counters and their companion control MSRs are shared between two logical processors sharing a 
processor core if the processor core supports Intel Hyper-Threading Technology and is based on Intel NetBurst 
microarchitecture. They are not shared between logical proc essors in different cores or different physical packages. 
As a result, software must manage the use of these resources, based on the topology of performance monitoring resources. Performance counter interrupts, events, and pr ecise event monitoring support can be set up and allo-
cated on a per thread (per logical processor) basis. 
9.8.4 IA32_MISC_ENABLE MSR

Some bit fields in IA32_MISC_ENABLE MSR (MSR addre ss 1A0H) may be shared between two logical processors 
sharing a processor core, or may be shared between differen t cores in a physical processor. See Chapter 2, “Model-
Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4.
9.8.5 Microcode Update Resources
Microcode update facilities are shared between two logica l processors sharing a processor core if the physical 
package supports Intel Hyper-Threading Technology. They ar e not shared between logical processors in different 9-34 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
cores or different physical packages. Either logical proc essor that has access to the microcode update facility can 
initiate an update. 
Each logical processor has its own BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical 
processor performs an update for the physical proce ssor, the IA32_BIOS_SIGN_ID MSRs for resident logical 
processors are updated with identical information. 
All microcode update steps during processor initialization sh ould use the same update data on all cores in all phys-
ical packages of the same stepping. Any subsequent microcode update must apply consistent update data to all 
cores in all physical packages of the same stepping. If th e processor detects an attempt to load an older microcode 
update when a newer microcode update had previously been loaded, it may reject the older update to stay with the 
newer update.
NOTE
microarchitecture) do not support simultaneous lo ading of microcode update to the sibling logical 
processors in the same core. All other processors support logical processors initiating an update 
simultaneously. Intel recommends a common approach that the microcode loader use the 
9.9 PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING 
CAPABLE PROCESSORS
In a multi-threading environment, there may be certain ha rdware resources that are physically shared at some 
level of the hardware topology. In the multi-processor systems, typically bus and memory sub-systems are physi-
cally shared between multiple sockets. Within a hardwa re multi-threading capable processors, certain resources 
are provided for each processor core, while other resources may be provided for each logical processors (see 
Section 9.7, “Intel® Hyper-Threading Technology Archit ecture,” and Section 9.8, “Multi-Core Architecture”). 
From a software programming perspective, control transfer of processor operation is managed at the granularity of 
logical processor (operating systems dispatch a runnable ta sk by allocating an available logical processor on the 
platform). To manage the topology of shared resources in a multi-threading environment, it may be useful for soft-
ware to understand and manage resources that are shared by more than one logical processors.
9.9.1 Hierarchical Mapping of Shared Resources
The APIC_ID value associated with each logical processor in a multi-processor system is unique (see Section 9.6, 
“Detecting Hardware Multi-Threading Support and Topology ”). This 8-bit or 32-bit value can be decomposed into 
sub-fields, where each sub-field corresponds a hierarch ical domain of the topological mapping of hardware 
resources. 
The decomposition of an APIC_ID may consist of several su b fields representing the topology within a physical 
processor package, the higher-order bits of an APIC ID  may also be used by cluster vendors to represent the 
topology of cluster nodes of each coherent multiprocessor systems:
•Cluster  — Some multi-threading environments consists of multiple clusters of multi-processor systems. The 
CLUSTER_ID sub-field is usually supported by vendor firmware to distinguish different clusters. For non-
clustered systems, CLUSTER_ID is usua lly 0 and system topology is reduced.
•Package  — A physical processor package mates with a socket. A package may contain one or more software 
visible die. The PACKAGE_ID sub-field distinguishes different physical packages within a cluster.
•Die — A software-visible chip inside a package. The DI E_ID sub-field distinguishes different die within a 
package. If there are no software visible die, the width of this bit field is 0.
•DieGrp  — A group of die that share certain resources.
•Tile — A set of cores that share certain resources. The TI LE_ID sub-field distinguishes different tiles. If there 
are no software visible tiles, the width of this bit field is 0.Vol. 3A 9-35MULTIPLE-PROCESSOR MANAGEMENT
•Module  — A set of cores that share certain resources. The MODULE_ID sub-field distinguishes different 
modules. If there are no software visible modules, the width of this bit field is 0.
•Core — Processor cores may be contained within modules, within tiles, on software-visible die, or appear 
directly at the package domain. The CORE_ID sub-field distinguishes processor cores. For a single-core 
processor, the width of this bit field is 0.
•Logical Processor — A processor core provides one or more logical processors sharing execution resources. 
The LOGICAL_PROCESSOR_ID sub-field dist inguishes logical processors in a core. The width of this bit field is 
non-zero if a processor core provides more than one logical processors.
The LOGICAL_PROCESSOR_ID and CORE_ID sub-fields ar e bit-wise contiguous in the APIC_ID field (see 
Figure 9-5). 
If the processor supports CPUID leaf 0BH and leaf 1FH,  the 32-bit APIC ID can represent cluster plus several 
domains of topology within the physical processor pack age. The exact number of hierarchical domains within a 
physical processor package must be enumerated through CPUID leaf 0BH and leaf 1FH. Common processor fami-
lies may employ a topology similar to that represented by the 8-bit Initial APIC ID. In general, CPUID leaf 0BH and 
leaf 1FH can support a topology enumeration algorithm that  decompose a 32-bit APIC ID into more than four sub-
fields (see Figure 9-6). 
NOTE
CPUID leaf 0BH and leaf 1FH can have differences in the number of domain types reported (CPUID 
leaf 1FH defines additional domain types). If the processor supports CPUID le af 1FH, usage of this 
leaf is preferred over leaf 0BH. CPUID leaf 0BH is available for legacy compatibility going forward.
The width of each sub-field depends on hardware and soft ware configurations. Field widths can be determined at 
runtime using the algorithm discussed belo w (Example 9-16 through Example 9-21). 
Figure 7-6 depicts the relationships of three of the hierarch ical sub-fields in a hypothetical MP system. The value of 
valid APIC_IDs need not be contiguous ac ross package boundary or core boundaries.Figure 9-5.  Generalized Seven-Doma in Interpretation of the APIC IDX            0
 X=31 if x2APIC is supported, otherwise X= 7Reserved
CLUSTER_ID
PACKAGE_ID
DIE_ID
TILE_ID
MODULE_ID
CORE_ID
LOGICAL_PROCESSOR_ID9-36 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
9.9.2 Hierarchical Mapping of C PUID Extended Topology Leaf 
CPUID leaf 0BH and leaf 1FH provide enumeration paramete rs for software to identify each hierarchy of the 
processor topology in a deterministic manner. Each hierarch ical domain of the topology starting from the Logical 
Processor domain is represented numerically by a sub-le af index within the CPUID 0BH leaf and 1FH leaf. Each 
domain of the topology is mapped to a sub-field in the APIC ID, following the general relationship depicted in 
Figure 9-6. This mechanism allows software to query th e exact number of domains within a physical processor 
package and the bit-width of each sub-fi eld of x2APIC ID directly. For example,
•Starting from sub-leaf index 0 and incrementing EC X until CPUID.(EAX=0BH or  1FH, ECX=N):ECX[15:8] 
returns an invalid “domain type” encoding. The number of domains within the physical processor package is “N” 
(excluding PACKAGE). Using Figure 9-6 as an exampl e, CPUID.(EAX=0BH or 1F H, ECX=4):ECX[15:8] will 
report 00H, indicating sub leaf 04H is invalid. This is also de picted by a pseudo code example:
Example 9-16.  Number of Domains Be low the Physical Processor Package
Word NumberOfDomainsBelowPackage = 0;
DWord Subleaf = 0;
EAX = 0BH or 1FH; // query each sub leaf of CPUID leaf 0BH or 1FH; CPUID leaf 1FH is preferred over leaf 0BH if available.
ECX = Subleaf;CPUID;while(EBX != 0)  // Enumerate until EBX reports 0{       if(EAX[4:0] != 0)   // A Shift Va lue of 0 indicates this domain does not exist.
// (Such as no SMT_ID, which is required entry at sub-leaf 0.)
      {             Nu mberOfDomainsBelowPackage++;

     }     Subleaf++;     EAX = 0BH or 1FH;     ECX = Subleaf;     CPUID;}// NumberOfDomainsBelowPackage contains the absolute number of domains that exist below package.N = Subleaf;   // Sub-leaf supplies the number of entries CPUID will return.Figure 9-6.  Conceptual Six-Domain To pology and 32-bit APIC ID Composition31            0
Physical Processor TopologyReservedPACKAGE
Q
R
CORE
LOGICAL 
PROCESSOR
32-bit APIC ID CompositionCLUSTER_ID
Q_ID
R_ID
CORE_ID
LOGICAL_PROCESSOR_IDVol. 3A 9-37MULTIPLE-PROCESSOR MANAGEMENT
•Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract the LOGICAL_PROCESSOR_ID 
sub-field of x2APIC ID. If EAX = 0BH or 1FH, and EC X =0 is specified as input when executing CPUID, 
CPUID.(EAX=0BH or 1FH, ECX=0):EAX[4:0] reports a value (a right-shift count) that allow software to extract 
part of x2APIC ID to distinguish the next higher topological entities above the LOGICAL_PROCESSOR_ID 
domain. This value also corresponds to the bit-width of  the sub-field of x2APIC ID corresponding the hierar-
chical domain with sub-leaf index 0. 
•For each subsequent higher sub-leaf index m, CPUI D.(EAX=0BH or 1FH, ECX=m):E AX[4:0] reports the right-
shift count that will allow software to extract part of x2APIC ID to distinguish higher-domain topological 
entities. This means the right-shift value at of sub-leaf m, corresponds to the least significant (m+1) sub-fields of the 32-bit x2APIC ID. 
Example 9-17.  BitWidth Determination of x2APIC ID Sub-fields
For m = 0, m < N, m ++;
{ cumulative_width[m] = CPUID.(EAX=0 BH or 1FH, ECX= m): EAX[4:0]; }
BitWidth[0] = cumu lative_width[0];
For m = 1, m < N, m ++;
BitWidth[m] = cumulative_width [m] - cumulative_width[m-1];
NOTE
CPUID leaf 1FH is a preferred superset to leaf 0B H. Leaf 1FH defines additional domain types, and 
it must be parsed by an algorithm that can handle the addition of future domain types.
Previously, only the following encoding of  hierarchical domain types were defined: 0 (invalid), 1 (logical processor), 
and 2 (core). With the additional hierarchical domain type s available (see Section 9.9.1, “Hierarchical Mapping of 
Shared Resources,” and Figure 9-5, “Generalized Seven-Doma in Interpretation of the APIC ID” ) software must not 
assume any “domain type” encoding value to be related to any sub-leaf index, except sub-leaf 0.
Example 9-18.  Support Routines for Id entifying Package, Die, Core, and Logi cal Processors from 32-bit x2APIC ID
a. Derive the extraction bitmask for logical processors in a processor core and associated mask offset for different
cores.
//
// This example shows how to enumerate CPU topology domain types (domain types may or may not be known/supported by the 
software)
//// Below is the list of sample do main types used in the example. 
// Refer to the CPUID Le af 1FH definition for the actual domain type numbers: “V2 Extended Topology Enumeration Leaf (Initial E AX 
Value = 1FH)” . 
//// LOGICAL PROCESSOR// CORE// MODULE// TILE// DIE// PACKAGE//// The example shows how to identify and derive the ex traction bitmask for the do mains with identify type 
LOGICAL_PROCESSOR_ID/COR E_ID/DIE_ID/PACKAGE_ID
//
int DeriveLogical_Processor_Mask_Offsets  (void)
{9-38 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
IF (!HWMTSupporte d()) return -1;
execute cpuid with EAX = 0BH or 1FH, ECX = 0;IF (returned domain type encoding in EXC[15:8] does not match LOGICAL_PROCESSOR_ID) return -1;Mask_Logical_Processor_shift = EAX[4:0];          //# bits shift right of APIC ID to  distinguish different cores, note this can  be a shift
// of zero if there is only one logical processor per core.
Logical Processor Mask =~( (-1) << Mask_Logical_Processor_s hift);        //shift left to derive extrac tion bitmask for
// LOGICAL_PROCESSOR_ID
return 0;
}
b. Derive the extraction bitmask for processor cores in a physical processor package and associated mask offset for
different packages.
int DeriveCore_Mask_Offsets  (void)
{
execute cpuid with EAX = 0BH or 1FH, ECX = 0;WHILE( ECX[15:8] ) {         //domain type encoding is valid
Mask_last_known_shift = EAX[4:0]IF (returned domain type encoding in ECX[15:8] matches CORE) {
Mask_Core_shift = EAX[4:0];
}ELSE IF (returned domain type encoding in ECX[15:8] matches DIE {
Mask_Die_shift = EAX[4:0];
}//// Keep enumerating. Check if the next domain is the desired domain and if not, keep enumerating until you reach a known // domain or the invalid domain (“0” domain type). If there ar e more domains between DIE and PACKAGE, the unknown 
// domains will be ignored and treated as an extension of the last known domain (i.e., DIE in this case).
//
ECX++;
execute cpuid with EAX = 0BH or 1FH;
}
COREPlusLogical_Processor_MASK = ~( (-1) << Mask_Core_shift);
DIEPlusCORE_MASK = ~( (-1) << Mask_Die_shift);
 
//// Treat domains between DIE and physical package as an extension of DIE for software choosing not to implement or recognize // these unknown domains.//
CORE_MASK = COREPlusLogical_Processor_MASK ^ Logical Processor Mask;
DIE_MASK = DIEPlusCORE_MASK ^ COREPlusLogical_Processor_MASK;
PACKAGE_MASK = (-1) << Mask_last_known_shift;
 
return -1;
} Vol. 3A 9-39MULTIPLE-PROCESSOR MANAGEMENT
9.9.3 Hierarchical ID of Logica l Processors in an MP System
For Intel 64 and IA-32 processors, system hardware establis hes an 8-bit initial APIC ID (or 32-bit APIC ID if the 
processor supports CPUID leaf 0BH) that is unique for each logical processor following power-up or RESET (see 
Section 9.6.1). Each logical processor on the system is allocated an initial APIC ID. BIOS may implement features that tell the OS to support less than the total number of lo gical processors on the system bus. Those logical proces-
sors that are not available to applications at runtime are halted during the OS boot process. As a result, the number 
valid local APIC_IDs that can be querie d by affinitizing-current-thread-context (See Example 9-23) is limited to the 
number of logical processors enabled at runtime by the OS boot process.
Table 9-2 shows an example of the 8-bit APIC IDs that are in itially reported for logical processors in a system with 
four Intel Xeon MP processors that support Intel Hyper-Th reading Technology (a total of 8 logical processors, each 
physical package has two processor cores and supports In tel Hyper-Threading Technology). Of the two logical 
processors within a Intel Xeon processor MP, logical processor 0 is designated the primary logical processor and logical processor 1 as the secondary logical processor.
Table 9-3 shows the initial APIC IDs for a hypothetical situation with a dual processor system. Each physical 
package providing two processor cores, and each proce ssor core also supporting Intel Hyper-Threading Tech-
nology.Figure 9-7.  Topological Relationships Between Hierarchical IDs in a Hypothetical MP Platform
Table 9-2.  Initial APIC IDs for the Logi cal Processors in a System that has Four  Intel Xeon MP Processors Supporting 
Intel Hyper-Threading Technology1 
Initial APIC ID PACKAGE_ID CORE_ID LOGICAL_PROCESSOR_ID
0H 0H 0H 0H1H 0H 0H 1H2H 1H 0H 0H
3H 1H 0H 1H
4H 2H 0H 0H5H 2H 0H 1H
6H 3H 0H 0H
7H 3H 0H 1H
NOTE:
1. Because information on the number of processor cores in a physical package was not available in early single-core processors sup-
porting Intel Hyper-Threading Technology, the CORE_ID can be treated as 0.T0 T1 T0 T1 T0 T1 T0 T1
Package 0 Package 1Core 0 Core 1 Core 0 Core 1LOGICAL_PROCESSOR_ID
CORE_ID
PACKAGE_ID9-40 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
9.9.3.1  Hierarchical ID of Logical Processors with x2APIC ID
Table 9-4 shows an example of possible x2APIC ID assign ments for a dual processor system that support x2APIC. 
Each physical package providing four processor cores, and each processor core also supporting Intel Hyper-
Threading Technology. Note that the x2APIC ID need not be contiguous in the system.Table 9-3.  Initial APIC IDs for the Logi cal Processors in a System that has Tw o Physical Processors  Supporting Dual-
Core and Intel Hyper- Threading Technology 
Initial APIC ID PACKAGE_ID CO RE_ID LOGICAL_PROCESSOR_ID
0H 0H 0H 0H1H 0H 0H 1H
2H 0H 1H 0H
3H 0H 1H 1H4H 1H 0H 0H
5H 1H 0H 1H
6H 1H 1H 0H7H 1H 1H 1H
Table 9-4.  Example of Possible x2APIC  ID Assignment in a System that ha s Two Physical Processors Supporting 
x2APIC and Intel Hyper-Threading Technology 
x2APIC ID PACKAGE_ID CORE_ID LOGICAL_PROCESSOR_ID
0H 0H 0H 0H
1H 0H 0H 1H
2H 0H 1H 0H3H 0H 1H 1H
4H 0H 2H 0H
5H 0H 2H 1H6H 0H 3H 0H
7H 0H 3H 1H
10H 1H 0H 0H11H 1H 0H 1H
12H 1H 1H 0H
13H 1H 1H 1H14H 1H 2H 0H
15H 1H 2H 1H
16H 1H 3H 0H17H 1H 3H 1HVol. 3A 9-41MULTIPLE-PROCESSOR MANAGEMENT
9.9.4 Algorithm for Three-Domain Mappings of APIC_ID
Software can gather the initial APIC_IDs for each logica l processor supported by the operating system at runtime11 
and extract identifiers corresponding to the three doma ins of sharing topology (package, core, and logical

2H 0H 1H 0H
5H 1H 0H 1H
0H 0H 0H 0H
1H 0H 0H 1H
4H 0H 2H 0H
7H 0H 3H 1H
12H 1H 1H 0H
15H 1H 2H 1H
and extract identifiers corresponding to the three doma ins of sharing topology (package, core, and logical 
processor). The three-domain algorithms below focus on a non-clustered MP system for simplicity. They do not assume APIC IDs are contiguous or that all logical processors on the platform are enabled.
Intel supports multi-threading systems where all physical processors report identical values in CPUID leaf 0BH, 
CPUID.1:EBX[23:16]), CPUID.4
12:EAX[31:26], and CPUID.413:EAX[25:14]. The algorithms below assume the 
target system has symmetry across physical package boundar ies with respect to the number of logical processors 
per package, number of cores per package,  and cache topology within a package.
Software can choose to assume three-domain hierarchy if it was developed to understand only three domains. 
However, software implementation needs to ensure it does not break if it runs on systems that have more domains in the hierarchy even if it does not recognize them.
The extraction algorithm (for three-domain mappings from  an APIC ID) uses the general procedure depicted in 
Example 9-19, and is supplemented by more detailed de scriptions on the derivation of topology enumeration 
parameters for extraction bit masks:
1. Detect hardware multi-threading support in the processor.
2. Derive a set of bit masks that can extract the sub ID of each hierarchical domain of the topology. The algorithm 
to derive extraction bit masks for LOGICAL_PROCESSO R_ID/CORE_ID/PACKAGE_ID differs based on APIC ID 
is 32-bit (see step 3 below) or 8-bit (see step 4 below).
3. If the processor supports CPUID leaf 0BH, each APIC ID contains a 32-b it value, the topology enumeration 
parameters needed to derive three-domain extraction bit masks are:
a. Query the right-shift value for the LOGICAL_PROCESSO R_ID domain of the topolo gy using CPUID leaf 0BH 
with ECX =0H as input. The number of bits to shift-ri ght on x2APIC ID (EAX[4:0]) can distinguish different 
higher-domain entities above logical processor in the sa me physical package. This is also the width of the 
bit mask to extract the LOGICAL_PROCESSOR_ID. The shift value may be 0 and enumerate no logical 
processor bit mask to create. A platform where cores only have one logical processor are not required to enumerate a separate bit layout for logical processor, and the lowest bits may only identify the core (where 
core and logical processor are then synonymous).
b. Enumerate until the desired domain is found (i.e., pr ocessor cores). Determine if the next domain is the 
expected domain. If the next domain is not known to  the software, keep enumerating until the next known 
or the last domain. Software should use the previous domain before this to represent the last previously 
known domain (i.e., processor cores). If the software does not recognize or implement certain hierarchical 
domains, it should assume these unknown domains as an extension of the last known domain.
c. Query CPUID leaf 0BH for the amount of bit shift to di stinguish next higher-domain entities (e.g., physical 
processor packages) in the system. This describes an explicit three-domain-topology situation for 
commonly available processors. Consult Example 9-17 to adapt to situations beyond a three-domain topology of a physical processor. The width of the extr action bit mask can be used to derive the cumulative 
extraction bitmask to extract the sub IDs of logical processors (including different processor cores) in the 
same physical package. The extraction bit mask to distinguish merely different processor cores can be derived by xor’ing the logical processor extraction bit mask from the cumulative extraction bit mask.
d. Query the 32-bit x2APIC ID for the logical pr ocessor where the current thread is executing.
e. Derive the extraction bit masks corresponding to  LOGICAL_PROCESSOR_ID, CORE_ID, and PACKAGE_ID, 
starting from LOGICAL_PROCESSOR_ID.
f. Apply each extraction bit mask to the 32-bit x2APIC ID to extract sub-field IDs.
11. As noted in Section 9.6 and Section 9.9.3, the number of logical processors supported by the OS at runtime may be less than the 
total number logical processors av ailable in the platform hardware.
12. Maximum number of addressable ID for processor cores in a phys ical processor is obtained by executing CPUID with EAX=4 and a  
valid ECX index. The ECX index starts at 0.
13. Maximum number addressable ID for proce ssor cores sharing the target cache level is obtained by executing CPUID with EAX = 4  
and the ECX index corresponding to the target cache level.9-42 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
4. If the processor does not support CPUID leaf 0BH, each initial APIC ID contains an 8-bit value, the topology 
enumeration parameters needed to derive extraction bit masks are:
a. Query the size of address space for sub IDs that can accommodate logical processors in a physical 
processor package. This size parameters (CPUID.1:E BX[23:16]) can be used to derive the width of an 
extraction bitmask to enumerate the sub IDs of different logical processo rs in the same physical package.
b. Query the size of address space for sub IDs that ca n accommodate processor cores in a physical processor 
package. This size parameters can be used to derive  the width of an extraction bitmask to enumerate the 
sub IDs of processor cores in the same physical package.
c. Query the 8-bit initial APIC ID for the logical processor where the current thread is executing.
d. Derive the extraction bit masks using respective address sizes corresponding to LOGICAL_PROCESSOR_ID, 
CORE_ID, and PACKAGE_ID, starting from LOGICAL_PROCESSOR_ID.
e. Apply each extraction bit mask to the 8-bi t initial APIC ID to extract sub-field IDs.
Example 9-19.  Support Routines for Dete cting Hardware Multi-Threading and Identifying the Relationships Between Package, 
Core, and Logical Processors
1. Detect support for Ha rdware Multi-Threading Support in a processor.
// Returns a non-zero value if CPUID reports the presence of hardware multi-threading 
// support in the physical package where th e current logical proc essor is located. 
// This does not guarantee BIOS or OS will en able all logical processors in the physical 
// package and make them available to applications. // Returns zero if hardware multi-threading is not present. 
#define HWMT_BIT 10000000Hunsigned int HWMTSupported(void)
{
 // ensure cpuid instruction is supported
execute cpuid with eax = 0 to get vendor string
execute cpuid with eax = 1 to get feature flag and signature
// Check to see if this a Genuine Intel Processor 
if (vendor string EQ GenuineIntel) {
return (feature_flag_edx & HWMT_BIT); // bit 28
}return 0;
}
Example 9-20.  Support Routines for Identifying Package,  Core, and Logical Processo rs from 32-bit x2APIC ID
cores.
int DeriveLogical_Proce ssor_Mask_Offsets (void)
{
if (!HWMTSupporte d()) return -1;
execute cpuid with eax = 11, ECX = 0;If (returned domain type encoding in ECX[15:8] does not match logical processor) return -1;Mask_Logical_Processor_shift = EAX[4:0]; // # bi ts shift right of APIC ID to distinguis h different cores, no te this can be a sh ift
Logical Processor Mask = ~( (-1) << Ma sk_Logical_Processor_shift); // shift le ft to derive extr action bitmask for 
// LOGICAL_PROCESSOR_IDVol. 3A 9-43MULTIPLE-PROCESSOR MANAGEMENT
return 0;
}
int DeriveCore_Mask_Offsets (void)
{
if (!HWMTSupported()) return -1;
execute cpuid with eax = 11, ECX = 0;
while( ECX[15:8] ) { // doma in type encoding is valid
Mask_Core_shift = EAX[4:0];   // needed to distinguish different physical packages 
         ECX ++;          execute cpuid with eax = 11;      }
// treat domains between core and physical package as a core for software choosing not to implement or recognize 
// these unknown domainsCORE_MASK = COREPlusLogical_Processor_MASK ^ Logical Processor Mask;PACKAGE_MASK = (-1) << Mask_Core_shift;
return -1;
}
c. Query the x2APIC ID of a logical processor.
APIC_IDs for each logical processor.
unsigned char Getx2APIC_ID (void)
{
unsigned reg_edx = 0;execute cpuid with eax = 11, ECX = 0store returned value of edxreturn (unsigned) (reg_edx) ;
}
Example 9-21.  Support Routines for Id entifying Package, Core, and Logical Processors from 8-bit Initial APIC ID
a. Find the size of address space for logical  processors in a physical processor package.
#define NUM_LOGICAL_BITS 00FF0000H 
// Use the mask above and CPUID.1.EBX[23:16] to obtain the max number of addressable IDs
// for logical processors in a physical package, 
//Returns the size of address space of logica l processors in a physical processor package;
// Software should not assume the value to be a power of 2.
unsigned char MaxLPIDsPerPackage(void)
{
if (!HWMTSupported()) return 1;
execute cpuid with eax = 1

return -1;
}
{
}
{
store returned value of ebxreturn (unsigned char) ((reg_ebx  & NUM_LOGICAL_BITS) >> 16);
}9-44 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
b. Find the size of address space for proc essor cores in a physical processor package.
// Returns the max number of addressable IDs for processor cores in a phys ical processor package;
// Software should not assu me cpuid reports this value to be a power of 2.
unsigned MaxCoreIDsPerPackage(void)
{
if (!HWMTSupported()) re turn (unsigned char) 1;
if cpuid supports leaf number 4 { // we can retrieve multi-core topology info using leaf 4
execute cpuid with eax = 4, ecx = 0store returned value of eaxreturn (unsigned) ((reg_eax >> 26) +1);
}else // must be a single-core processorreturn 1;
}
c. Query the initial APIC ID of a logical processor.
#define INITIAL_APIC_ID_BITS FF000000H // CPUID.1.EBX[31:24] initial APIC ID
// Returns the 8-bit unique initial APIC ID for the processor running the code. 
// Software can use OS services to affinitize the current thread to each logica l processor 
// available under the OS to gather the in itial APIC_IDs for ea ch logical processor.
unsigned GetInitAPIC_ID (void)
{
unsigned int reg_ebx = 0;execute cpuid with eax = 1store returned value of ebxreturn (unsigned) ((reg_ebx & INITIAL_ APIC_ID_BITS) >> 24;
}
d. Find the width of an extracti on bitmask from the m aximum count of the bi t-field (address size).
// Returns the mask bit width of a bit field from the maximum coun t that bit field can represent.
// This algorithm does not assume ‘address si ze’ to have a value equal to power of 2.
// Address size for LOGICAL_PROCESSOR_ID can be calculated from MaxLPIDsPerPackage()/MaxCoreIDsPerPackage()// Then use the routine below to derive the correspo nding width of logical processor extraction bitmask
// Address size for CORE_ID is MaxCoreIDsPerPackage(), // Derive the bitwidth for CORE  extraction mask similarly
unsigned FindMaskWidth(Unsigned Max_Count)
{unsigned int mask_width, cnt = Max_Count;
__asm {
mov eax, cntmov ecx, 0mov mask_width, ecxdec eaxbsr cx, axjz nextinc cxmov  mask_width, ecxnext:  mov eax, mask_widthVol. 3A 9-45MULTIPLE-PROCESSOR MANAGEMENT
}
return mask_width;
}
e. Extract a sub ID from an 8-bit full ID, using address size of the sub ID and shift count.
// The routine below can extract LOGICAL_PROCESSOR_ID, CORE_I D, and PACKAGE_ID respective ly from the init APIC_ID
// To extract LOGICAL_PROCESSOR_ID, MaxSub IDvalue is set to the address size of  LOGICAL_PROCESSOR_ID, Shift_Count = 0
// To extract CORE_ID, MaxSubIDva lue is the address size of CORE _ID, Shift_Count is width of lo gical processor extraction bitma sk.
// Returns the value of the sub ID, this is not a zero-based value 
Unsigned char GetSubID(unsigned char Full_ID, unsign ed char MaxSubIDvalue, unsigned char Shift_Count)
{
MaskWidth = FindMaskWidth(MaxSubIDValue);MaskBits = ((uchar) (FFH << Shift_Count)) ^ ((uchar ) (FFH << Shift_Coun t + MaskWidth)) ;
SubID = Full_ID & MaskBits;Return SubID;
}
Software must not assume local APIC_ID values in an MP  system are consecutive. Non-consecutive local APIC_IDs 
may be the result of hardware configurations or  debug features implemented in the BIOS or OS.
An identifier for each hierarchical domain can be extrac ted from an 8-bit APIC_ID using the support routines illus-
trated in Example 9-21. The appropriate bit mask and shift value to construct the appropriate bit mask for each 
domain must be determined dynamically at runtime. 
9.9.5 Identifying Topological Relationships in an MP System
To detect the number of physical packages, processor cores,  or other topological relationships in a MP system, the 
following procedures are recommended:
•Extract the three-domain identifiers from the APIC ID of each logical processor enabled by system software. 
The sequence is as follows (see the pseudo code shown in Example 9-22 and support routines shown in 
Example 9-19):
•The extraction start from the right-most bit field, corresponding to LOGICAL_PROCESSOR_ID, the 
innermost hierarchy in a three-domain topology (See Figure 9-7). For the right-most bit field, the shift value of the working mask is zero. The width of the bit field is determined dynamically using the 
maximum number of logical processor per core, which can be derived from information provided from 
CPUID.
•To extract the next bit-field, the shift value of the working mask is determined from the width of the bit 
mask of the previous step. The width of the bit field is determined dynamically using the maximum 
number of cores per package.
•To extract the remaining bit-field, the shift value of  the working mask is determined from the maximum 
number of logical processor per package. So the rema ining bits in the APIC ID (excluding those bits 
already extracted in the two previous steps) are extr acted as the third identifier. This applies to a non-
clustered MP system, or if there is no need to  distinguish between PACKAGE_ID and CLUSTER_ID.
If there is need to distinguish between PACKAGE_ ID and CLUSTER_ID, PACKAGE_ID can be extracted 
using an algorithm similar to the extraction of CORE _ID, assuming the number of physical packages in 
each node of a clustered system is symmetric.
•Assemble the three-domain identifiers of LOGICAL_PR OCESSOR_ID, CORE_ID, PACKAGE_IDs into arrays for 
each enabled logical processor. This is shown in Example 9-23a.
•To detect the number of physical packages: use PACKAGE_ID to identify those logical processors that reside in 
the same physical package. This is shown in Example 9-23b. This example also depicts a technique to construct a mask to represent the logical processors that reside in the same package.9-46 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
•To detect the number of processor cores: use CORE_ID to identify those logical processors that reside in the 
same core. This is shown in Example 9-23. This example also depicts a technique to construct a mask to represent the logical processors that reside in the same core.
In Example 9-22, the numerical ID value can be obtained from  the value extracted with the mask by shifting it right 
by shift count. Algorithms below do not shift the value. The assumption is that the SubID values can be compared 
for equivalence without the need to shift. 
Example 9-22.  Pseudo Code Depictin g Three-Domain Extraction Algorithm
For Each local_APIC_ID{
// Calculate Logical Processor Mask, the bit ma sk pattern to extract LOGICAL_PROCESSOR_ID, 
// Logical Processor Mask is determined using topology enumertaion parameters// from CPUID leaf 0BH ( Example 9-20) ;
// otherwise, Logical Processor Mask is determined  using CPUID leaf 01H and leaf 04H (Example 9-21).
// This algorithm assumes there is symmetry ac ross core boundary, i.e. , each core within a
// package has the same number of logical processors// LOGICAL_PROCESSOR_ID always starts from bit 0, correspondin g to the right-most bit-field
LOGICAL_PROCESSOR_ID = APIC_I D & Logical Processor Mask;
// Extract CORE_ID:
// Core Mask is determined in  Example 9-20 or Example 9-21
CORE_ID = (APIC_ID & Core Mask);
// Extract PACKAGE_ID:
// Assume sing le cluster. 
// Shift out the mask width for maximum logical processors per package// Package Mask is determined in Example 9-20 or Example 9-21
PACKAGE_ID = (APIC_ID & Package Mask) ;
}
Example 9-23.  Compute the Number of Packages, Co res, and Processor Relationships in a MP System
a) Assemble lists of PACKAGE_ID, CORE_ID, and LOGICAL_PROCESSOR_ID of each enabled logical processors
// The BIOS and/or OS may limit the number of logical processors available to applications after system boot. 
// The below algorithm will compute topology for the proc essors visible to the thread that is computing it.
// Extract the 3-domains of IDs on every processor.
// SystemAffinity is a bitmask of all the processors started by the OS. Us e OS specific APIs to obtain it.
// ThreadAffinityMask is used to affinitize the topology enumeration thread to each processor using OS specific APIs.// Allocate per processor arrays to store the Package_ID, Core_ID, and LOGICAL_PROCESSOR_ID for every started processor. 
ThreadAffinityMask = 1;
     ProcessorNum = 0;
while (ThreadAffinityMask 
≠ 0 && ThreadAffinityMask  <= SystemAffinity) {
// Check to make sure we can utilize this processor first.if (ThreadAffinityMask & SystemAffinity){
Set thread to run on the processo r specified in ThreadAffinityMask
Wait if necessary and ensure thread is running on specified processor
APIC_ID = GetAPIC_ID(); // 32 bit ID in Example 9-20 or 8-bit ID in Example 9-21
Extract the Package_ID, Core_ID, and LOGICAL_PROCESSOR_ID as explained in three domain extraction 
algorithm of Example 9-22
PackageID[ProcessorNUM] = PACKAGE_ID;CoreID[ProcessorNum] = CORE_ID;Vol. 3A 9-47MULTIPLE-PROCESSOR MANAGEMENT
LOGICAL_PROCESSOR_ID[Processor Num] = LOGICAL_PROCESSOR_ID;
ProcessorNum++;
}ThreadAffinity Mask <<= 1;
}NumStartedLPs = ProcessorNum;
b) Using the list of PACKAGE_ID to count the number of physical pack ages in a MP system and construc t, for each package, a multi-b it

b) Using the list of PACKAGE_ID to count the number of physical pack ages in a MP system and construc t, for each package, a multi-b it 
mask corresponding to those logical proc essors residing in  the same package.
// Compute the number of packages by counting the number of  processors with unique PACKAG E_IDs in the PackageID array. 
// Compute the mask of processors in each package.
// PackageIDBucket is an array of unique PACKAGE_ID values. Allo cate an array of NumStartedLPs count of entries in this array.
// PackageProcessorMask is a corresponding array of the bit mask of processors belonging to the same package, these are 
// processors with the same PACKAGE_ID.
// The algorithm below assumes there is symmetry across package boundary if more than one socket is populated in an MP
//system.
// Bucket Package IDs and compute processor mask for every package.
PackageNum = 1;
PackageIDBucket[0] = PackageID[0];ProcessorMask = 1;PackageProcessorMask[0] = ProcessorMask;For (ProcessorNum = 1; ProcessorNum < NumStartedLPs; ProcessorNum++) { 
ProcessorMask << = 1; For (i=0; i < PackageNum; i++) {
// we may be comparing bit-fields of logical processors residing in different// packages, the code below assume package symmetryIf (PackageID[ProcessorNum] = PackageIDBucket[i]) {
PackageProcess orMask[i] |= ProcessorMask;
Break; // found in existing bucket, skip to next iteration
}
}if (i =PackageNum) {
//PACKAGE_ID did not match any bucket, start new bucket
PackageIDBucket[i] = PackageID[ProcessorNum];PackageProcess orMask[i] = ProcessorMask;
PackageNum++;
}
}// PackageNum has the number of Packages started in OS// PackageProcessorMask[] array has the processor set of each package
c) Using the list of CORE_ID to coun t the number of cores in a MP system and constr uct, for each core, a multi-bit mask correspond ing 
to those logical processors residing in the same core. 
Processors in the same core can be determined by bucketing the pr ocessors with the same PACKAGE_ID  and CORE_ID. Note that code 
below can BIT OR the values of PACKGE and CORE  ID because they have not been shifted right.
The algorithm below assumes there is symmetry  across package boundary if  more than one socket is populated in an MP system.
//Bucketing PACKAGE and CORE IDs and co mputing processor mask for every core
CoreNum = 1;CoreIDBucket[0] = PackageID[0] | CoreID[0];ProcessorMask = 1;9-48 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
CoreProcessorMask[0] = ProcessorMask;
For (ProcessorNum = 1; ProcessorNum < NumStartedLPs; ProcessorNum++) { 
ProcessorMask << = 1; For (i=0; i < CoreNum; i++) {
// we may be comparing bit-fields of logical processors residing in different// packages, the code below assume package symmetryIf ((PackageID[ProcessorNum] | CoreID[ ProcessorNum]) = Co reIDBucket[i]) {
CoreProcessorMask[i] |= ProcessorMask;
}
}if (i = CoreNum) {
//Did not match any bucket, start new bucketCoreIDBucket[i] = PackageID[ProcessorNum] | CoreID[ProcessorNum];CoreProcessorMask[i] = ProcessorMask;CoreNum++;
}
}// CoreNum has the number of  cores started in the OS
// CoreProcessorMask[] array has the processor set of each core
Other processor relationships such as processor mask of si bling cores can be computed from set operations of the 
PackageProcessorMask[] and CoreProcessorMask[]. 
The algorithm shown above can be adapted to work with ea rlier generations of single-core IA-32 processors that 
support Intel Hyper-Threading Technology and in situatio ns that the deterministic cache parameter leaf is not 
supported (provided CPUID supports initial APIC ID). A refe rence code example is available (see Intel® 64 Archi-
tecture Processor Topology Enumeration Technical Paper).
9.10 MANAGEMENT OF IDLE  AND BLOCKED CONDITIONS
When a logical processor in an MP system (including mu lti-core processor or processors supporting Intel Hyper-
Threading Technology) is idle (no work to do) or blocked (on a lock or semaphore), additional management of the 
core execution engine resource can be accomplished by using the HLT (halt), PAUSE, or the MONITOR/MWAIT 
9.10.1 HLT Instruction
The HLT instruction stops the execution of the logical proce ssor on which it is executed and places it in a halted 
state until further notice (see the description of the HLT instruction in Chapter 3 of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 2A). When a logical processor is halted, active logical processors continue to have full access to the shared resources within the physical package. Here shared resources that were 
being used by the halted logical processor become availabl e to active logical processors, allowing them to execute 
at greater efficiency. When the halted logical processo r resumes execution, shared resources are again shared 
among all active logical processors. (See Section 9.10.6.3,  “Halt Idle Logical Processors,” for more information 
about using the HLT instruction with processors  supporting Intel Hyper-Threading Technology.)
9.10.2 PAUSE Instruction
The PAUSE instruction can improves the performance of pr ocessors supporting Intel Hyper-Threading Technology 
when executing “spin-wait loops” and other routines where one thread is accessing a shared lock or semaphore in a tight polling loop. When executing a spin-wait loop, the processor can suffer a severe performance penalty when 
exiting the loop because it detects a possible memory order violation and flushes the core processor’s pipeline. The 
PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses Vol. 3A 9-49MULTIPLE-PROCESSOR MANAGEMENT
this hint to avoid the memory order vi olation and prevent the pipeline flush. In addition, the PAUSE instruction de-
pipelines the spin-wait loop to prevent it from cons uming execution resources excessively and consume power 
needlessly. (See Section 9.10.6.1, “Use the PAUSE Instru ction in Spin-Wait Loops,” for more information about 
using the PAUSE instruction with IA-32 processo rs supporting Intel Hyper-Threading Technology.)
9.10.3 Detecting Support MONITOR/MWAIT Instruction
Streaming SIMD Extensions 3 introduced two instructions  (MONITOR and MWAIT) to help multithreaded software 
improve thread synchronization. In the initial implemen tation, MONITOR and MWAIT are available to software at 
ring 0. The instructions are conditionally available at leve ls greater than 0. Use the fo llowing steps to detect the 
availability of MONITOR and MWAIT:
•Use CPUID to query the MONITOR bit (CPUID.1.ECX[3] = 1).
•If CPUID indicates support, execute MONITOR inside a TRY/EXCEPT exception handler and trap for an 
exception. If an exception occurs, MONITOR and MWAIT ar e not supported at a privilege level greater than 0. 
See Example 9-24.
Example 9-24.  Verifying MONITOR/MWAIT Support
boolean MONITOR_MWAIT_works = TRUE;
try {
_asm {
xor ecx, ecxxor edx, edxmov eax, MemAreamonitor }
        // Use monitor} except (UNWIND) {        // if we get here , MONITOR/MWAIT is not supported
MONITOR_MWAIT_works = FALSE;
}
9.10.4 MONITOR/MWAIT Instruction
Operating systems usually implement idle loops to handle thread synchronization. In a typical idle-loop scenario, 
there could be several “busy loops” and they would use a se t of memory locations. An impacted processor waits in 
a loop and poll a memory location to determine if there is available work to execute. The posting of work is typically 
a write to memory (the work-queue of the waiting processo r). The time for initiating a work request and getting it 
scheduled is on the order of a few bus cycles. 
From a resource sharing perspective (logical processors sharing execution resources), use of the HLT instruction in 
an OS idle loop is desirable but has implications. Executin g the HLT instruction on a idle logical processor puts the 
targeted processor in a non-execution state. This requir es another processor (when posting work for the halted 
logical processor) to wake up the halted processor using an inter-processor interrupt. The posting and servicing of 
such an interrupt introduces a delay in  the servicing of new work requests. 
In a shared memory configuration, exits from busy loops usually occur because of a state change applicable to a 
specific memory location; such a change tends to be trig gered by writes to the memory location by another agent 
(typically a processor). 
MONITOR/MWAIT complement the use of HLT and PAUSE to a llow for efficient partitioning and un-partitioning of 
shared resources among logical processors sharing physic al resources. MONITOR sets up an effective address 
range that is monitored for write-to-memory activities; MWAIT places the processor in an optimized state (this 
may vary between different implementations) until a write to the monitored address range occurs. 
In the initial implementation of MONITOR and MWAIT, they are available at CPL = 0 only.9-50 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
Both instructions rely on the state of the processor’s mo nitor hardware. The monitor hardware can be either armed

Both instructions rely on the state of the processor’s mo nitor hardware. The monitor hardware can be either armed 
(by executing the MONITOR instruction) or triggered (due to  a variety of events, including a store to the monitored 
memory region). If upon execution of MWAIT, monitor ha rdware is in a triggered state: MWAIT behaves as a NOP 
and execution continues at the next instruction in the execution stream. The state of monitor hardware is not archi-
tecturally visible except through the behavior of MWAIT.
Multiple events other than a write to the triggering address range can cause a processor that executed MWAIT to 
wake up. These include events that would lead to voluntary or involuntary context switches, such as:
•External interrupts, including NMI, SMI, INIT, BINIT, MCERR, A20M#
•Faults, Aborts (including Machine Check)
•Architectural TLB invalidations including writes to CR0,  CR3, CR4, and certain MSR writes; execution of LMSW 
(occurring prior to issuing MWAIT but after setting the monitor)
•Voluntary transitions due to fast system call and far calls (occurring prior to issuing MWAIT but after setting the 
monitor)
Power management related events (such as Thermal Monitor 2 or chipset driven STPCLK# assertion) will not cause 
the monitor event pending flag to be cleared. Faults will  not cause the monitor event pending flag to be cleared.
Software should not allow for voluntary context switches in between MONITOR/MWAIT in the instruction flow. Note 
that execution of MWAIT does not re-arm the monitor hardware. This means that MONITOR/MWAIT need to be executed in a loop. Also note that exits from the MWAIT state could be due to a condition other than a write to the 
triggering address; software should explicitly check the tr iggering data location to determine if the write occurred. 
Software should also check the value of the triggering address following the execution of the monitor instruction 
(and prior to the execution of the MWAIT instruction). This check is to identify any writes to the triggering address 
that occurred during the course of MONITOR execution. 
The address range provided to the MONITOR instruction mu st be of write-back caching type. Only write-back 
memory type stores to the monitored address range will tr igger the monitor hardware. If the address range is not 
in memory of write-back type, the address monitor hardwa re may not be set up properly or the monitor hardware 
may not be armed. Software is also responsible for ensuring that
•Writes that are not intended to cause the exit of a busy loop do not write to a location within the address region 
being monitored by the monitor hardware,
•Writes intended to cause the exit of a busy loop are written to locations within the monitored address region.
Not doing so will lead to more false wakeups (an exit from the MWAIT state not due to a write to the intended data 
location). These have negative performance implications. It might be necessary for software to use padding to 
prevent false wakeups. CPUID provides a mechanism for dete rmining the size data locations for monitoring as well 
as a mechanism for determining the size of a the pad.
9.10.5 Monitor/Mwait Address Range Determination
To use the MONITOR/MWAIT instructions, software should  know the length of the region monitored by the 
MONITOR/MWAIT instructions and the size of the coherenc e line size for cache-snoop traffic in a multiprocessor 
system. This information can be queried using the CPUID monitor leaf function (EAX = 05H). You will need the 
smallest and largest monitor line size:
•To avoid missed wake-ups: make sure that the data structure used to monitor writes fits within the smallest 
monitor line-size. Otherwise, the processor may not wake  up after a write intended to trigger an exit from 
MWAIT. 
•To avoid false wake-ups; use the largest monitor line size to pad the data structure used to monitor writes. Software must make sure that beyond the data structure,  no unrelated data variable exists in the triggering 
area for MWAIT. A pad may be needed to avoid this situation.
These above two values bear no relationship to cache line  size in the system and software should not make any 
assumptions to that effect. Within a single-cluster system , the two parameters should default to be the same (the 
size of the monitor triggering area is the same as the system coherence line size).
Based on the monitor line sizes returned by the CPUID, the OS should dynamically allocate structures with appro-
priate padding. If static data structures must be used  by an OS, attempt to adapt the data structure and use a Vol. 3A 9-51MULTIPLE-PROCESSOR MANAGEMENT
dynamically allocated data buffer for thread synchronizatio n. When the latter technique is not possible, consider 
not using MONITOR/MWAIT when using static data structures.
To set up the data structure correctly for MONITOR/MWAIT on multi-clustered systems: interaction between 
processors, chipsets, and the BIOS is required (system coherence line size may depend on the chipset used in the system; the size could be different from the processor’s moni tor triggering area). The BIOS is responsible to set the 
correct value for system coherence line size using the IA32_MONITOR_FILTER_LINE_SIZE MSR. Depending on the 
relative magnitude of the size of the monitor triggering  area versus the value written into the IA32_MONITOR_FIL-
TER_LINE_SIZE MSR, the smaller of the parameters will be reported as the Smallest Monitor Line Size . The larger 
of the parameters will be reported as the Largest Monitor Line Size .
9.10.6 Required Operating System Support
This section describes changes that must be made to an operating system to run on processors supporting Intel 
Hyper-Threading Technology. It also describes optimization s that can help an operating system make more effi-
cient use of the logical processors sharing execution reso urces. The required changes and suggested optimizations 
are representative of the types of modifications that ap pear in Windows* XP and Linux* kernel 2.4.0 operating 
systems for Intel processors supporting Intel Hyper-Threading Technology. Additional optimizations for processors 
supporting Intel Hyper-Threading Technology are described in the Intel® 64 and IA-32 Architectures Optimization 
Reference Manual.
9.10.6.1  Use the PAUSE Instruction in Spin-Wait Loops
Intel recommends that a PAUSE instruction be placed in a ll spin-wait loops that run on Intel processors supporting 
Intel Hyper-Threading Technology and multi-core processors. 
Software routines that use spin-wait loops include mult iprocessor synchronization primitives (spin-locks, sema-
phores, and mutex variables) and idle loops. Such routines  keep the processor core busy executing a load-compare-
branch loop while a thread waits for a resource to become available. Including a PAUSE instruction in such a loop greatly improves efficiency (see Section 9.10.2, “PAUSE Instruction”). The following routine gives an example of a 
spin-wait loop that uses a PAUSE instruction:
Spin_Lock:
CMP lockvar, 0 ;Check if lock is freeJE Get_LockPAUSE ;Short delayJMP Spin_Lock
Get_Lock:
MOV EAX, 1XCHG EAX, lockvar ;Try to get lockCMP EAX, 0 ;Test if successfulJNE Spin_Lock
Critical_Section:
<critical section code>MOV lockvar, 0...
Continue:
The spin-wait loop above uses a “test, test-and-set” tec hnique for determining the availability of the synchroniza-
tion variable. This technique is reco mmended when writing spin-wait loops.
In IA-32 processor generations earlier than the Pentium 4 processor, the PAUSE instruction is treated as a NOP 
9.10.6.2  Potential Usage of MO NITOR/MWAIT in C0 Idle Loops
An operating system may implement different handlers for di fferent idle states. A typical OS idle loop on an ACPI-
compatible OS is shown in Example 9-25: 9-52 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
Example 9-25.  A Typical OS Idle Loop
// WorkQueue is a memory location  indicating there is a thread 
// ready to run.  A non-zero value for WorkQueue is assumed to// indicate the presence of work to be scheduled on the processor.// The idle loop is entered with interrupts disabled.
WHILE (1) {
IF (WorkQueue) THEN {
// Schedule work at WorkQueue.} 
ELSE {
// No work to do - wait in ap propriate C-state handler depending 
// on Idle ti me accumulated
IF (IdleTime >= IdleTimeThreshhold) THEN {
// Call appropriate C1, C2, C3 state handler, C1 handler 
// shown below
}
}
}// C1 handler uses a Halt instructionVOID C1Handler() {S T I
HLT
}
The MONITOR and MWAIT instructions may be considered for use in  the C0 idle state loops, if MONITOR and MWAIT are supported. 
Example 9-26.  An OS Idle Loop with MONITOR/MWAIT in the C0 Idle Loop
// ready to run.  A non-zero value for WorkQueue is assumed to// indicate the presence of work to be scheduled on the processor.// The following example assumes that the necessary padding has been // added surrounding WorkQueue to eliminate false wakeups// The idle loop is entered with interrupts disabled.
WHILE (1) {

WHILE (1) {
ELSE {
}
}
HLT
}
WHILE (1) {
ELSE {
// on Idle time accumulated.
// Call appropriate C1, C2, C3 state handler, C1 // handler shown belowMONITOR WorkQueue // Setup of eax with WorkQueue
// LinearAddress, // ECX, EDX = 0
IF (WorkQueue = 0) THEN {
MWAIT}
}
}Vol. 3A 9-53MULTIPLE-PROCESSOR MANAGEMENT
}
// C1 handler uses a Halt instruction.
VOID C1Handler() 
{S T I
HLT
}
9.10.6.3  Halt Idle  Logical Processors
If one of two logical processors is idle or in a spin-wait lo op of long duration, explicitly halt that processor by means 
of a HLT instruction. 
In an MP system, operating systems can place idle processors into a loop that continuously checks the run queue 
for runnable software tasks. Logical processors that ex ecute idle loops consume a significant amount of core’s 
execution resources that might otherwise be used by the ot her logical processors in the physical package. For this 
reason, halting idle logical processors optimizes the performance.14 If all logical processors within a physical 
package are halted, the processor will enter a power-saving state.
9.10.6.4  Potential Usage of MO NITOR/MWAIT in C1 Idle Loops
An operating system may also consider replacing HLT with MONITOR/MWAIT in its C1 idle loop. An example is 
shown in Example 9-27: 
Example 9-27.  An OS Idle Loop with  MONITOR/MWAIT in the C1 Idle Loop
// WorkQueue is a memory location indicating there is a thread 
WHILE (1) {
// Schedule work at WorkQueue} 
ELSE {
// No work to do - wait in appropriate C-state handler depending // on Idle ti me accumulated
IF (IdleTime >= IdleTimeThreshhold) THEN {// Call appropriate C1, C2, C3 state handler, C1 // handler shown below}
}
}
VOID C1Handler() { MONITOR WorkQueue // Setup of eax with WorkQueue LinearAddress, 
// ECX, EDX = 0
STI
14. Excessive transitions into an d out of the HALT state could also incur perfor mance penalties. Operatin g systems should evalua te the 
performance trade-offs for their operating system.9-54 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
MWAIT // EAX, ECX = 0
}
}
9.10.6.5  Guidelines for Scheduling Threads on  Logical Processors Shar ing Execution Resources
Because the logical processors, the order in which threads are dispatched to logical processors for execution can 
affect the overall efficiency of a system. The followin g guidelines are recommended for scheduling threads for 
•Dispatch threads to one logical processor per processor core before dispatching threads to the other logical 
processor sharing execution resources in the same processor core. 
•In an MP system with two or more physical packages, distribute threads out over all the physical processors, rather than concentrate them in one or two physical processors.
•Use processor affinity to assign a thread to a specif ic processor core or package, depending on the cache-
sharing topology. The practice increases the chance that the processor’s caches will contain some of the 
thread’s code and data when it is dispatched for execution after being suspended. 
9.10.6.6  Eliminate Execution-Based Timing Loops
Intel discourages the use of timing loops that depend on a processor’s execution speed to measure time. There are several reasons:
•Timing loops cause problems when they are calibrated on a IA-32 processor running at one frequency and then 
executed on a processor running at another frequency. 
•Routines for calibrating execution-based timing loops produce unpredictable results when run on an IA-32 
processor supporting Intel Hyper-Threading Technology. This is due to the sharing of execution resources 
between the logical processors within a physical package. 
To avoid the problems described, timing loop routines mu st use a timing mechanism for the loop that does not 
depend on the execution speed of the logical processors in the system. The following sources are generally avail-
able:
•A high resolution system timer (for example, an Intel 8254).
•A high resolution timer within the processor (such as, the local APIC timer or the time-stamp counter).
For additional information, see the Intel® 64 an d IA-32 Architectures Optimization Reference Manual.
9.10.6.7  Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory
When software uses locks or semaphores to synchronize processes, threads, or other code sections; Intel recom-
mends that only one lock or semaphore be present within a cache line (or 128 byte sector, if 128-byte sector is 
supported). In processors based on Intel NetBurst microa rchitecture (which support 128-byte sector consisting of 
two cache lines), following this recommendation means that each lock or semaphore should be contained in a 128-
byte block of memory that begins on a 128-byte boundar y. The practice minimizes the bus traffic required to 
service locks.
9.11 MP INITIALIZATION FOR P6 FAMILY PROCESSORS
This section describes the MP initialization process for syst ems that use multiple P6 family processors. This process 
uses the MP initialization protocol that was introduced with the Pentium Pro processor (see Section 9.4, “Multiple-Processor (MP) Initialization”). For P6 family processors, th is protocol is typically used to boot 2 or 4 processors 
that reside on single system bus; however, it can support from 2 to 15 processors in a multi-clustered system when 
the APIC buses are tied together. Larger systems are not supported.Vol. 3A 9-55MULTIPLE-PROCESSOR MANAGEMENT
9.11.1 Overview of the MP Initializati on Process for P6 Family Processors
During the execution of the MP initialization protocol, on e processor is selected as the bootstrap processor (BSP) 
and the remaining processors are designated as applicat ion processors (APs), see Se ction 9.4.1, “BSP and AP 
Processors.” Thereafter, the BSP manages the initializatio n of itself and the APs. This initialization includes 
executing BIOS initialization code and operating-system initialization code.
The MP protocol imposes the following requirements and restrictions on the system:
•An APIC clock (APICLK) must be provided.
•The MP protocol will be executed only after a power-up or RESET. If the MP protocol has been completed and a 
BSP has been chosen, subsequent INITs (either to a spec ific processor or system wide) do not cause the MP 
protocol to be repeated. Instead, each processor exam ines its BSP flag (in the AP IC_BASE MSR) to determine 
AP).
The following special-purpose interprocessor interrupts (IPI s) are used during the boot phase of the MP initializa-
tion protocol. These IPIs are broadcast on the APIC bus.
•Boot IPI (BIPI)—Initiates the arbitration mechanism that  selects a BSP from the group of processors on the 
system bus and designates the remainder of the processors as APs. Each processor on the system bus broadcasts a BIPI to all the processors following a power-up or RESET. 
•Final Boot IPI (FIPI)—Initiates the BIOS initialization procedure for the BSP. This IPI is broadcast to all the 
processors on the system bus, but only the BSP responds  to it. The BSP responds by beginning execution of the 
BIOS initialization code at the reset vector.
•Startup IPI (SIPI)—Initiates the initialization procedure fo r an AP. The SIPI message contains a vector to the AP 
initialization code in the BIOS.
Table 9-5 describes the various fields of the boot phase IPIs.
For BIPI messages, the lower 4 bits of the vector field co ntain the APIC ID of the processor issuing the message and 
the upper 4 bits contain the “generation ID” of the message.  All P6 family processor will have a generation ID of 
4H. BIPIs will therefore use vector valu es ranging from 40H to 4EH (4FH can not be used because FH is not a valid 
APIC ID). 
9.11.2 MP Initialization Protocol Algorithm
Following a power-up or RESET of a syst em, the P6 family processors in the system execute the MP initialization 
protocol algorithm to initialize each of the processors on the system bus. In the course of executing this algorithm, 
the following boot-up and initialization operations are carried out:Table 9-5.  Boot Phase IPI Message Format
TypeDestination

APIC ID). 
FieldDestination
ShorthandTrigger
Mode LevelDestination
ModeDelivery
ModeVector
(Hex)
BIPI Not used All including self Edge Deassert Don’t Care Fixed
(000)40 to 4E*
FIPI Not used All including self Edge Deassert Don’t Care Fixed
(000)10
SIPI Used All excluding self Edge Assert Physical StartUp
(110)00 to FF
NOTE:
* For all P6 family processors.9-56 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENT
1. Each processor on the system bus is assigned a unique  APIC ID, based on system topology (see Section 9.4.5, 
“Identifying Logical Processors in an MP System”). This ID is written into the local APIC ID register for each 
2. Each processor executes its internal BIST simultaneously with the other processors on the system bus. Upon 
completion of the BIST (at T0), each processor broadc asts a BIPI to “all including self” (see Figure 9-8). 
3. APIC arbitration hardware causes all the APICs to resp ond to the BIPIs one at a time (at T1, T2, T3, and T4). 
4. When the first BIPI is received (at time T1), each APIC  compares the four least significant bits of the BIPI’s 
vector field with its APIC ID. If the vector and APIC ID match, the processor selects itself as the BSP by setting 
the BSP flag in its IA32_APIC_BASE MSR. If the vector an d APIC ID do not match, the processor selects itself 
as an AP by entering the “wait for SIPI” state. (Note th at in Figure 9-8, the BIPI from processor 1 is the first 
BIPI to be handled, so processor 1 becomes the BSP.)
5. The newly established BSP broadcasts an FIPI message to  “all including self.” The FIPI is guaranteed to be 
handled only after the completion of the BIPIs that were issued by the non-BSP processors.
6. After the BSP has been established, the outstanding BI PIs are received one at a time (at T2, T3, and T4) and 
ignored by all processors.
7. When the FIPI is finally received (at T5), only the BS P responds to it. It responds by fetching and executing 
BIOS boot-strap code, beginning at the reset vector (physical address FFFF FFF0H).
8. As part of the boot-strap code, the BSP creates an ACPI  table and an MP table and adds its initial APIC ID to 
9. At the end of the boot-strap procedure, the BSP broadc asts a SIPI message to all the APs in the system. Here, 
the SIPI message contains a vector to the BIOS AP init ialization code (at 000V V000H, where VV is the vector 
contained in the SIPI message).
10. All APs respond to the SIPI message by racing to a BIOS initialization semaphore. The first one to the 
semaphore begins executing the initialization code. (See MP init code for semaphore implementation details.) 
As part of the AP initialization procedure, the AP adds  its APIC ID number to the ACPI and MP tables as appro-
priate. At the completion of the initialization procedure, th e AP executes a CLI instruction (to clear the IF flag in 
the EFLAGS register) and halts itself.
11. When each of the APs has gained access to the sema phore and executed the AP initialization code and all 
written their APIC IDs into the appropriate places in th e ACPI and MP tables, the BS P establishes a count for the 
number of processors connected to the system bus, co mpletes executing the BIOS boot-strap code, and then 
begins executing operating-system boot-strap and start-up code. 
Figure 9-8.  MP System With Multiple Pentium III ProcessorsPentium III
Processor 0Pentium III
Processor 1Pentium III
Processor 2Pentium III
Processor 3
BIPI.1 BIPI.0 BIPI.3 BIPI.2 FIPIT0 T1 T2 T3 T4 T5System (CPU) Bus
APIC Bus
Serial Bus ActivityProcessor 1
Becomes BSPVol. 3A 9-57MULTIPLE-PROCESSOR MANAGEMENT
12. While the BSP is executing operating-system boot-strap and start-up code, the APs remain in the halted state. 
See Section 9.4.4, “MP Initialization Example,” for an anno tated example the use of the MP protocol to boot IA-32 
processors in an MP. This code should run on any IA-32 processor that used the MP protocol.
9.11.2.1  Error Detection and Handling During the MP Initialization Protocol
Errors may occur on the APIC bus during the MP initializ ation phase. These errors may be transient or permanent 
and can be caused by a variety of failure mechanisms (for  example, broken traces, soft errors during bus usage, 
etc.). All serial bus related errors will result  in an APIC checksum or acceptance error. 
The MP initialization protocol makes the following assump tions regarding errors that occur during initialization:
•If errors are detected on the APIC bus during execution of the MP initialization protocol, the processors that 
detect the errors are shut down. 
•The MP initialization protocol will be executed by processors even if they fail their BIST sequences.9-58 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENTVol. 3A 10-1CHAPTER 10
This chapter describes the facilities provided for mana ging processor wide functions and for initializing the 
processor. The subjects covered include: processor initia lization, x87 FPU initializati on, processor configuration, 
feature determination, mode switching, the MSRs (in the Pentium, P6 family, Pentium 4, and Intel Xeon proces-
sors), and the MTRRs (in the P6 family, Pentium 4, and Intel Xeon processors).
10.1 INITIALIZATION OVERVIEW
Following power-up or an assertion of the RESET# pin, each processor on the system bus performs a hardware 
initialization of the processor (known as a hardware rese t) and an optional built-in self-test (BIST). A hardware 
reset sets each processor’s registers to a known state and places the processor in real-address mode. It also inval-idates the internal caches, translation lookaside buffers (T LBs) and the branch target buffer (BTB). At this point, 
the action taken depends on the processor family:
•Pentium 4 processors (CPU ID DisplayFamily 0FH) — All the processors on the system bus (including a 
single processor in a uniprocessor system) execute the multiple processor (MP) initialization protocol. The 
processor that is selected through this protocol as the bootstrap processor (BSP) then immediately starts 
executing software-initialization code in the current code  segment beginning at the offset in the EIP register. 
The application (non-BSP) processors (APs) go into a Wait For Startup IPI (SIPI) state while the BSP is 
executing initialization code. See Section 9.4, “Multiple-Processor (MP) Initialization,” for more details. Note 
that in a uniprocessor system, the single Pentium 4 or Intel Xeon processor automatically becomes the BSP.
•IA-32 and Intel 64 processors  (CPUID DisplayFamily 06H)  — The action taken is the same as for the 
Pentium 4 processors (as described in the previous paragraph).
•Pentium processors  — In either a single- or dual- processor system, a single Pentium processor is always 
pre-designated as the primary processor. Following a reset, the primary processor behaves as follows in both 
single- and dual-processor systems. Using the dual-proce ssor (DP) ready initialization protocol, the primary 
processor immediately starts executing software-initialization code in the current code segment beginning at 
the offset in the EIP register. The secondary processor (if there is one) goes into a halt state.
•Intel486 processor  — The primary processor (or single processor in a uniprocessor system) immediately 
starts executing software-initialization code in the current code segment beginning at the offset in the EIP register. (The Intel486 does not automatically execute a DP or MP initialization protocol to determine which 
processor is the primary processor.)
The software-initialization code performs all system-speci fic initialization of the BSP or primary processor and the 
system logic.
At this point, for MP (or DP) systems, the BSP (or primar y) processor wakes up each AP (or secondary) processor 
to enable those processors to execute self-configuration code.
When all processors are initialized, configured, and sync hronized, the BSP or primary processor begins executing 
an initial operating-system or executive task.
The x87 FPU is also initialized to a known state during hard ware reset. x87 FPU software initialization code can then 
be executed to perform operations such as setting the pr ecision of the x87 FPU and the exception masks. No special 
initialization of the x87 FPU is required to switch operating modes. 
Asserting the INIT# pin on the processor invokes a similar response to a hardware rese t. The major difference is 
that during an INIT, the internal caches, MSRs, MTRRs, an d x87 FPU state are left unchanged (although, the TLBs 
and BTB are invalidated as with a hardware reset). An INIT  provides a method for switching from protected to real-
address mode while maintaining the contents of the internal caches.10-2 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
10.1.1 Processor State After Reset

Following power-up, The state of control register CR0 is 60000010H (see Figure 10-1). This places the processor is 
in real-address mode with paging disabled. 
The state of the flags and other registers following power- up for the Pentium 4, Pentium Pro, and Pentium proces-
sors are shown in Section 23.39, “Initial State of Pent ium, Pentium Pro and Pentium 4 Processors,” of the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Table 10-1 shows processor states of IA-32 and Intel 64 processors with CPUID DisplayFamily signature of 06H at 
the following events: power-up, RESET, and INIT. In a few cases, the behavior of some registers behave slightly 
different across warm RESET, the variant cases are marked  in Table 10-1 and described in more detail in Table 
10-2.Figure 10-1.  Contents of  CR0 Register after Reset
Table 10-1.  IA-32 and Intel® 64 Processor States Following Power-up, Reset, or INIT 
Register Power up Reset INIT
EFLAGS100000002H 00000002H 00000002H
EIP 0000FFF0H 0000FFF0H 0000FFF0H
CR0 60000010H260000010H260000010H2
CR2, CR3, CR4 00000000H 00000000H 00000000H
CS Selector = F000H
Base = FFFF0000H
Limit = FFFFHAR = Present, R/W, AccessedSelector = F000H
Limit = FFFFHAR = Present, R/W, Accessed
SS, DS, ES, FS, GS Selector = 0000H
Base = 00000000H
Limit = FFFFH
AR = Present, R/W, AccessedSelector = 0000H
AR = Present, R/W, Accessed
EDX 000n06xxH
3 000n06xxH3 000n06xxH3 
EAX 040404
EBX, ECX, ESI, EDI, EBP, ESP 00000000H 00000000H 00000000HExternal x87 FPU error reporting: 0
(Not used): 1No task switch: 0x87 FPU instructions not trapped: 0
WAIT/FWAIT instructions not trapped: 0Real-address mode: 031 19 16 15 0
P
E123456 1718 282930
M
PE
M1N
ET
SP
GCDN
WW
PA
MPaging disabled: 0
Alignment check disabled: 0Caching disabled: 1
Not write-through disabled: 1
Write-protect disabled: 0
Reserved ReservedVol. 3A 10-3PROCESSOR MANAGEMENT AND INITIALIZATION
ST0 through ST75+0.0 +0.0 FINIT/FNINIT: Unchanged
x87 FPU Control Word50040H 0040H FINIT/FNINIT: 037FH
x87 FPU Status Word50000H 0000H FINIT/FNINIT: 0000H
x87 FPU Tag Word55555H 5555H FINIT/FNINIT: FFFFH
x87 FPU Data Operand and 
CS Seg. Selectors50000H 0000H FINIT/FNINIT: 0000H
Inst. Pointers500000000H 00000000H FINIT/FNINIT: 00000000H
MM0 through MM750000000000000000H 0000000000000000H INIT  or FINIT/FNINIT: Unchanged
XMM0 through XMM7 0H 0H Unchanged
MXCSR 1F80H 1F80H UnchangedGDTR, IDTR Base = 00000000H
AR = Present, R/WBase = 00000000H
AR = Present, R/W
LDTR, Task Register Selector = 0000H
Limit = FFFFHAR = Present, R/WSelector = 0000H
Limit = FFFFHAR = Present, R/W
DR0, DR1, DR2, DR3 0 0000000H 00000000H 00000000H
DR6 FFFF0FF0H FFFF0FF0H FFFF0FF0H
DR7 00000400H 00000400H 00000400H
R8-R15 0000000000000000H 0000000000000000H 0000000000000000HXMM8-XMM15 0H 0H Unchanged
XCR0 1H 1H Unchanged
IA32_XSS 0H 0H UnchangedYMM_H[255:128] 0H 0H Unchanged
BNDCFGU 0H 0H 0H
BND0-BND3 0H 0H 0HIA32_BNDCFGS 0H 0H 0H
OPMASK 0H 0H Unchanged
ZMM_H[511:256] 0H 0H UnchangedZMMHi16[511:0] 0H 0H Unchanged
PKRU 0H 0H Unchanged
Intel Processor Trace MSRs 0H 0H
WUnchanged
Time-Stamp Counter 0H 0HWUnchanged
IA32_TSC_AUX 0H 0H Unchanged
IA32_TSC_ADJUST 0H 0H UnchangedIA32_TSC_DEADLINE 0H 0H Unchanged
IA32_SYSENTER_CS/ESP/EIP 0H 0H Unchanged
IA32_EFER 0000000000000000H 0000000000000000H 0000000000000000HIA32_STAR/LSTAR 0H 0H UnchangedTable 10-1.  IA-32 and Intel® 64  Processor States Following Power-up, Reset, or INIT  (Contd.)
Register Power up Reset INIT10-4 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
IA32_FS_BASE/GS_BASE 0H 0H 0H
IA32_PMCx, 
IA32_PERFEVTSELx0H 0H Unchanged
IA32_PERF_GLOBAL_CTRL Sets bits n-1:0 and clears the 
upper bits.7Sets bits n-1:0 and clears the upper bits.
7Unchanged
IA32_FIXED_CTRx, 
IA32_FIXED_CTR_CTRL0H 0H Unchanged
Data and Code Cache, TLBs Invalid6Invalid6Unchanged
Fixed MTRRs Disabled Disabled Unchanged
Variable MTRRs Disabl ed Disabled Unchanged
Machine-Check Banks Undefined UndefinedWUnchanged
Last Branch Record Stack 0 0WUnchanged
APIC Enabled Enabled Unchanged
X2APIC Disabled Disabled UnchangedIA32_DEBUG_INTERFACE 0 0
NOTES: 
1. The 10 most-significant bits of the EFLAGS register are undefi ned following a reset. Software should not depend on the states  of 
any of these bits.
2. The CD and NW flags are unchanged, bit 4 is set to 1, all other bits are cleared.3. Where “n” is the Extended Model Value for the respective processor, and “xx” = don’t care.
4. If Built-In Self-Test (BIST) is invoked on power up or reset, EAX is 0 only if all tests passed. (BIST cannot be invoked duri ng an INIT.)
5. The state of the x87 FPU and MMX registers is not changed by the execution of an INIT.6. Internal caches are invalid after power-up and RESET, but left unchanged with an INIT.
7. Where “n” is the number of general-purpose counters available in the processor. See Chapter 20, “Performance Monitoring,” fo r addi-
tional details.
W: Warm RESET behavior differs from power-on  RESET with details listed in Table 10-2.
Table 10-2.  Variance of RE SET Values in Selected In tel Architecture Processors
State XREF Value Feature Flag or Di splayFamily_DisplayModel Signatures
Time-Stamp Counter Warm RESET Unmodified across warm 
Reset06_2DH, 06_3EH
Machine-Check Banks Warm RESET IA32_MCi_Status banks are 
unmodified across warm Reset06_2DH, 06_3EH, 06_3FH, 06_4FH, 06_56H
Last Branch Record Stack Warm RESET LBR stack MSRs are 
unmodified across warm 
Reset06_1AH, 06_1CH, DisplayFamiy= 06 and DisplayModel >1DH
Intel Processor Trace 
MSRsWarm RESET Clears 
IA32_RTIT_CTL.TraceEn, 
the rest of MSRs are unmodifiedIf CPUID.(EAX=14H, ECX=0H):EBX[bit 2] = 1
IA32_DEBUG_INTERFACE Warm RESET Unmodified across warm 
ResetIf CPUID.01H:ECX.[11] = 1 Table 10-1.  IA-32 and Intel® 64 Processor States Following Power-up, Reset, or INIT  (Contd.)
Register Power up Reset INITVol. 3A 10-5PROCESSOR MANAGEMENT AND INITIALIZATION
10.1.2 Processor Built-In Self-Test (BIST)
Hardware may request that the BIST be  performed at power-up. The EAX regist er is cleared (0H) if the processor 
passes the BIST. A nonzero value in the EAX register after the BIST indicates that a processor fault was detected. 
If the BIST is not requested, the contents of the EAX register after a hardware reset is 0H. 
The overhead for performing a BIST varies between processor families. For example, the BIST takes approximately 
30 million processor clock periods to execute on the Pent ium 4 processor. This clock count is model-specific; Intel 
reserves the right to change the number of periods for any Intel 64 or IA-32 processor, without notification.
10.1.3 Model and Stepping Information
Following a hardware reset, the EDX register contains component identification and revision information (see 
Figure 10-2). For example, the model, family, and processor type returned for the first processor in the Intel 
Pentium 4 family is as follows: model (0000B), family (1111B), and processor type (00B). 
The stepping ID field contains a unique identifier for the processor’s stepping ID or revision level. The extended 
family and extended model fields were added to th e IA-32 architecture in the Pentium 4 processors.
10.1.4 First Instruction Executed
The first instruction that is fetched and executed following a hardware reset is located at physical address 
FFFFFFF0H. This address is 16 bytes below the processor’s uppermost physical address. The EPROM containing the 
software-initialization code must be located at this address. 
The address FFFFFFF0H is beyond the 1-MB yte addressable range of the processor while in real-address mode. The 
processor is initialized to this starting address as foll ows. The CS register has two parts: the visible segment 
selector part and the hidden base address part. In real -address mode, the base address is normally formed by 
shifting the 16-bit segment selector value 4 bits to the le ft to produce a 20-bit base address. However, during a 
hardware reset, the segment selector in the CS register is  loaded with F000H and the base address is loaded with 
FFFF0000H. The starting address is thus formed by adding th e base address to the value in the EIP register (that 
is, FFFF0000 + FFF0H = FFFFFFF0H).
The first time the CS register is loaded with a new value after a hardware reset, the processor will follow the normal 
rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]). To

rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]). To 
ensure that the base address in the CS register remains unchanged until the EPROM based software-initialization code is completed, the code must not contain a far jump or far call or allow an interrupt to occur (which would 
cause the CS selector value to be changed).
10.2 X87 FPU INITIALIZATION
Software-initialization code can determine the whether the processor contains an x87 FPU by using the CPUID 
instruction. The code must then initiali ze the x87 FPU and set flags in control register CR0 to reflect the state of the 
x87 FPU environment.Figure 10-2.  Version Information in the EDX Register after Reset31 12 11 8 7 4 3 0
EDX
Family (1111B for the Pentium 4 Processor Family)
Model (Beginning with 0000B)1314
Processor TypeModel FamilyStepping
ID15
ModelExtended Extended
Family16 1920 2728
Reserved10-6 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
A hardware reset places the x87 FPU in the state shown in Table 10-1. This state is different from the state the x87 
FPU is placed in following the execution of an FINIT or FNI NIT instruction (also shown in Table 10-1). If the x87 FPU 
is to be used, the software-initialization code should execute an FINIT/FNINIT instruction following a hardware 
reset. These instructions, tag all data registers as empty,  clear all the exception masks, set the TOP-of-stack value 
to 0, and select the default rounding and precision cont rols setting (round to nearest and 64-bit precision).
If the processor is reset by asserting the INIT# pin, the x87 FPU state is not changed.
10.2.1 Configuring the x87 FPU Environment
Initialization code must load the appropriate values into th e MP, EM, and NE flags of control register CR0. These bits 
are cleared on hardware reset of the processor. Fi gure 10-3 shows the suggested settings for these flags, 
depending on the IA-32 processor being initialized. Initiali zation code can test for the type of processor present 
before setting or clearing these flags.
The EM flag determines whether floating-point instructions are executed by the x87 FPU (EM is cleared) or a 
device-not-available exception (#NM) is generated for all fl oating-point instructions so that an exception handler 
can emulate the floating-point operation (EM = 1). Ordinarily, the EM flag is cleared when an x87 FPU or math 
coprocessor is present and set if they are not present. If the EM flag is set and no x87 FPU, math coprocessor, or 
floating-point emulator is present, the processor will hang when a floating-point instruction is executed.
The MP flag determines whether WAIT/FWAIT  instructions react to the setting of the TS flag. If the MP flag is clear, 
WAIT/FWAIT instructions ignore the setting of the TS flag; if the MP flag is set, they will generate a device-not-
available exception (#NM) if the TS flag is set. Generally,  the MP flag should be set for processors with an inte-
grated x87 FPU and clear for processors without an inte grated x87 FPU and without a math coprocessor present. 
However, an operating system can choose to save the floa ting-point context at every context switch, in which case 
there would be no need to set the MP bit. 
Table 2-2 shows the actions taken for floating-point and WA IT/FWAIT instructions based on the settings of the EM, 
MP, and TS flags.
The NE flag determines whether unmasked floating-point exceptions are handled by generating a floating-point 
error exception internally (NE is set, native mode) or th rough an external interrupt (NE is cleared). In systems 
where an external interrupt controller is used to in voke numeric exception handle rs (such as MS-DOS-based 
systems), the NE bit should be cleared.
10.2.2 Setting the Processor for x87 FPU Software Emulation
Setting the EM flag causes the processor to generate a de vice-not-available exception (#NM) and trap to a software 
exception handler whenever it encounters a floating-point in struction. (Table 10-3 shows when it is appropriate to 
use this flag.) Setting this flag has two functions:
•It allows x87 FPU code to run on an IA-32 processor that has neither an integrated x87 FPU nor is connected to 
an external math coprocessor, by using a floating-point emulator. 
•It allows floating-point code to be executed using a sp ecial or nonstandard floating-point emulator, selected for 
a particular application, regardless of whether an x87 FPU or math coprocessor is present. Table 10-3.  Recommended Settings of EM and MP Flags on IA-32 Processors
EM MP NE IA-32 processor
1 0 1 Intel486™ SX, Intel386™ DX, and Intel386™ SX processors only, without the presence of a math 
coprocessor.
01 1  o r  0*Pentium 4, Intel Xeon, P6 fami ly, Pentium, Intel486™ DX, and Intel 487 SX processors, and 
Intel386 DX and Intel386 SX processors when  a companion math coprocessor is present.
01 1  o r  0*More recent Intel 64 or IA-32 processors
NOTE:
* The setting of the NE flag depends on the operating system being used.Vol. 3A 10-7PROCESSOR MANAGEMENT AND INITIALIZATION
To emulate floating-point instructions, the EM, MP, and NE flag in control register CR0 should be set as shown in 
Table 10-4.
Regardless of the value of the EM bit, the Intel486 SX processor generates a device-not-available exception (#NM) 
upon encountering any floating-point instruction.
10.3 CACHE ENABLING
IA-32 processors (beginning with the Intel486 processor)  and Intel 64 processors contain internal instruction and 
data caches. These caches are enabled by clearing the CD  and NW flags in control register CR0. (They are set 
during a hardware reset.) Because all internal cache lines are invalid following reset initialization, it is not neces-
sary to invalidate the cache before enabling caching. Any ex ternal caches may require initialization and invalidation 
using a system-specific initialization and invalidation code sequence.
Depending on the hardware and operating system or ex ecutive requirements, additional configuration of the 
processor’s caching facilities will probab ly be required. Beginning with the In tel486 processor, page-level caching 
can be controlled with the PCD and PWT flags in page-dir ectory and page-table entrie s. Beginning with the P6 
family processors, the memory type ra nge registers (MTRRs) control the caching characteristics of the regions of 
physical memory. (For the Intel486 and Pentium processors , external hardware can be used to control the caching 
characteristics of regions of physical memory.) See Ch apter 12, “Memory Cache Control,” for detailed information 
on configuration of the caching facilities in the Pentiu m 4, Intel Xeon, and P6 family processors and system 
memory.
10.4 MODEL-SPECIFIC REGISTERS (MSRS)
Most IA-32 processors (starting from Pentium processors) and Intel 64 processors contain a model-specific regis-ters (MSRs). A given MSR may not be supported across al l families and models for Intel 64 and IA-32 processors. 
Some MSRs are designated as architectural to simplify so ftware programming; a feature introduced by an architec-
tural MSR is expected to be supported in future proce ssors. Non-architectural MSRs are not guaranteed to be 
supported or to have the same functions on future processors.   
MSRs that provide control for a number of ha rdware and software-related features, include:
•Performance-monitoring counters (see Chapter 20, “Performance Monitoring”).
•Debug extensions (see Chapter 18, “Debug, Branch Prof ile, TSC, and Intel® Resource Director Technology 
(Intel® RDT) Features”).
•Machine-check exception capability and its accompanying machine-check architecture (see Chapter 16, 
“Machine-Check Architecture”).
•MTRRs (see Section 12.11, “Memory Type Range Registers (MTRRs)”).
•Thermal and power management.
•Instruction-specific support (for exam ple: SYSENTER, SYSEXIT, SWAPGS, etc.).
•Processor feature/mode support (for exam ple: IA32_EFER, IA32_FEATURE_CONTROL).
The MSRs can be read and written to using the RDMSR and WRMSR instructions, respectively.
When performing software initialization of an IA-32 or Inte l 64 processor, many of the MSRs will need to be initial-
ized to set up things like performance-monitoring even ts, run-time machine checks, and memory types for phys-
ical memory.Table 10-4.  Software Emulation Se ttings of EM, MP, and NE Flags
CR0 Bit Value
EM 1
MP 0
NE 110-8 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
Lists of available performance-monitoring events can be found at: https://perfmon-events.intel.com/ , and lists of 
available MSRs are given in Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 4. The references ea rlier in this section show where the functions of the 
various groups of MSRs are described in this manual.
10.5 MEMORY TYPE RANGE REGISTERS (MTRRS)
Memory type range registers (MTRRs) we re introduced into the IA-32 architecture with the Pentium Pro processor. 
They allow the type of caching (or no caching) to be sp ecified in system memory for selected physical address

EM 1
MP 0
They allow the type of caching (or no caching) to be sp ecified in system memory for selected physical address 
ranges. They allow memory accesses to be optimized for va rious types of memory such as RAM, ROM, frame buffer 
memory, and memory-mapped I/O devices.
In general, initializing the MTRRs is no rmally handled by the software initializat ion code or BIOS and is not an oper-
ating system or executive function. At the very least, all the MTRRs must be cleared to 0, which selects the 
uncached (UC) memory type. See Section 12.11, “Memory Type Range Registers (MTRRs),” for detailed informa-
tion on the MTRRs.
10.6 INITIALIZING SSE/S SE2/SSE3/SSSE3 EXTENSIONS
For processors that contain SSE/SSE2/SSE3/SSSE3 exte nsions, steps must be taken when initializing the 
processor to allow execution of these instructions.
1. Check the CPUID feature flags for the presence of the SSE/SSE2/SSE3/SSSE3 extensions (respectively: EDX 
bits 25 and 26, ECX bit 0 and 9) and support for the FX SAVE and FXRSTOR instructions (EDX bit 24). Also check 
for support for the CLFLUSH instruction (EDX bit 19). Th e CPUID feature flags are lo aded in the EDX and ECX 
registers when the CPUID instruction is executed with a 1 in the EAX register.
2. Set the OSFXSR flag (bit 9 in control register CR4) to  indicate that the operating system supports saving and 
restoring the SSE/SSE2/SSE3/SSSE3 execution environmen t (XMM and MXCSR register s) with the FXSAVE and 
FXRSTOR instructions, respectively. See Section 2.5, “Con trol Registers,” for a description of the OSFXSR flag.
3. Set the OSXMMEXCPT flag (bit 10 in control register CR 4) to indicate that the op erating system supports the 
handling of SSE/SSE2/SSE3 SIMD floating-point exceptions  (#XM). See Section 2.5, “Control Registers,” for a 
description of the OSXMMEXCPT flag.
4. Set the mask bits and flags in the MXCSR register according to the mode of operation desired for 
SSE/SSE2/SSE3 SIMD floating-point instructions. See “MXCSR Control and Status Register” in Chapter 10, 
“Programming with Intel® Streaming SIMD Extensions (Intel® SSE),” of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 1, for a detailed de scription of the bits and flags in the MXCSR register.
10.7 SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION
Following a hardware reset (either through a power-up or th e assertion of the RESET# pin) the processor is placed 
in real-address mode and begins executing software init ialization code from physical address FFFFFFF0H. Software 
initialization code must first set up the necessary data structures for handling basic system functions, such as a 
real-mode IDT for handling interrupts and exceptions. If the processor is to remain in real-address mode, software 
must then load additional operating-system or executive code modules and data structures to allow reliable execu-
tion of application programs in real-address mode.
If the processor is going to operate in protected mode, soft ware must load the necessary data structures to operate 
in protected mode and then switch to protected mode. Th e protected-mode data structures that must be loaded 
are described in Section 10.8, “Software Initialization for Protected-Mode Operation.”
10.7.1 Real-Address Mode IDT
In real-address mode, the only system data structure that must be loaded into memory is the IDT (also called the “interrupt vector table”). By default, the address of the base of the IDT is ph ysical address 0H. This address can be Vol. 3A 10-9PROCESSOR MANAGEMENT AND INITIALIZATION
changed by using the LIDT instruction to change the base address value in the IDTR. Software initialization code 
needs to load interrupt- and exception-handler pointe rs into the IDT before interrupts can be enabled. 
The actual interrupt- and exception-handler code can be contained either in EPROM or RAM; however, the code 
must be located within the 1-MByte a ddressable range of the processor in re al-address mode. If the handler code 
is to be stored in RAM, it must be loaded along with the IDT.
10.7.2 NMI Interrupt Handling
The NMI interrupt is always enabled (except when multip le NMIs are nested). If the IDT and the NMI interrupt 
handler need to be loaded into RAM, there will be a period of time following  hardware reset when an NMI interrupt 
cannot be handled. During this time, hardware must provide a mechanism to prevent an NMI interrupt from halting 
code execution until the IDT and the necessary NMI handle r software is loaded. Here  are two examples of how 
NMIs can be handled during the initial states of processor initialization:
•A simple IDT and NMI interrupt handler can be provided in EPROM. This allows an NMI interrupt to be handled 
immediately after reset initialization.
•The system hardware can provide a mechanism to enable and disable NMIs by passing the NMI# signal through 
an AND gate controlled by a flag in an I/O port. Hardwa re can clear the flag when the processor is reset, and 
software can set the flag when it is ready to handle NMI interrupts.
10.8 SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION
The processor is placed in real-address mode following a hard ware reset. At this point in the initialization process, 
some basic data structures and code modules must be loaded  into physical memory to support further initialization 
of the processor, as described in Section 10.7, “Softwar e Initialization for Real-Address Mode Operation.” Before 
the processor can be switched to protected mode, the soft ware initialization code must load a minimum number of 
protected mode data structures and code modules into me mory to support reliable operation of the processor in 
protected mode. These data stru ctures include the following:
•A IDT.
•A GDT.
•A TSS.
•(Optional) An LDT.
•If paging is to be used, at least one page directory and one page table.
•A code segment that contains the code to be executed when the processor switches to protected mode.
•One or more code modules that contain the necessary interrupt and exception handlers.
Software initialization code must also initialize the following system registers before the processor can be switched 
to protected mode:
•The GDTR.
•(Optional.) The IDTR. This register can also be initiali zed immediately after switching to protected mode, prior 
to enabling interrupts.
•Control registers CR1 through CR4.
•(Pentium 4, Intel Xeon, and P6 family processors  only.) The memory type range registers (MTRRs).
With these data structures, code modules, and system registers initialized, the processor can be switched to 
protected mode by loading control register CR0 with a value that sets the PE flag (bit 0).
10.8.1 Protected-Mode System Data Structures
The contents of the protected-mode system data structur es loaded into memory during software initialization, 
depend largely on the type of memory management the pr otected-mode operating-system or executive is going to 
support: flat, flat with paging, segmented, or segmented with paging.10-10 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
To implement a flat memory model without paging, software initialization code must at a minimum load a GDT with 
one code and one data-segment descriptor. A null descriptor in the first GDT entry is also required. The stack can 
be placed in a normal read/write data segment, so no de dicated descriptor for the stack is required. A flat memory 
model with paging also requires a page directory and at  least one page table (unless all pages are 4 MBytes in 
which case only a page directory is required). See Section 10.8.3, “Initializing Paging.”
Before the GDT can be used, the base address and limit fo r the GDT must be loaded into the GDTR register using 
an LGDT instruction.
A multi-segmented model may require additional segments fo r the operating system, as well as segments and LDTs 
for each application program. LDTs require segment descriptors in the GDT. Some operating systems allocate new segments and LDTs as they are needed. This provides  maximum flexibility for handling a dynamic programming 
environment. However, many operating systems use a single  LDT for all tasks, allocating GDT entries in advance. 
An embedded system, such as a process controller, might pre-allocate a fixed number of segments and LDTs for a 
fixed number of application programs. This would be a simple and efficient way to structure the software environ-
ment of a real-time system.
10.8.2 Initializing Protected-Mode Exceptions and Interrupts
Software initialization code must at a minimum load a protected-mode IDT with gate descriptor for each exception 
vector that the processor can generate. If interrupt or trap  gates are used, the gate descriptors can all point to the 
same code segment, which contains the necessary exception handlers. If task gates are used, one TSS and accom-
panying code, data, and task segments are required for each exception handler called with a task gate.
If hardware allows interrupts to be ge nerated, gate descriptors must be prov ided in the IDT for one or more inter-
rupt handlers.

Before the IDT can be used, the base address and limit for the IDT must be loaded into the IDTR register using an 
LIDT instruction. This operation is typically carried  out immediately after switching to protected mode.
10.8.3 Initializing Paging
Paging is controlled by the PG flag in control register CR0.  When this flag is clear (its state following a hardware 
reset), the paging mechanism is turned off; when it is set, paging is enabled. Before setting the PG flag, the 
following data structures and registers must be initialized:
•Software must load at least one page directory and on e page table into physical memory. The page table can 
be eliminated if the page directory contains a directory entry pointing to itself (here, the page directory and page table reside in the same page),  or if only 4-MByte pages are used.
•Control register CR3 (also called the PDBR register) is loaded with the physical base address of the page 
directory.
•(Optional) Software may provide one set of code and data descriptors in the GDT or in an LDT for supervisor 
mode and another set for user mode.
With this paging initialization complete, paging is enable d and the processor is switched to protected mode at the 
same time by loading control register CR0 with an image in which the PG and PE flags are set. (Paging cannot be 
enabled before the processor is switched to protected mode.)
10.8.4 Initializing Multitasking
If the multitasking mechanism is not going to be used an d changes between privilege levels are not allowed, it is 
not necessary load a TSS into memory or to initialize the task register.
If the multitasking mechanism is going to be used and/or changes between pr ivilege levels are allowed, software 
initialization code must load at least one TSS and an a ccompanying TSS descriptor. (A TSS is required to change 
privilege levels because pointers to the privileged-level 0,  1, and 2 stack segments and the stack pointers for these 
stacks are obtained from the TSS.) TSS descriptors must not be marked as busy when they are created; they 
should be marked busy by the processor only as a side-effe ct of performing a task switch. As with descriptors for 
LDTs, TSS descriptors reside in the GDT.Vol. 3A 10-11PROCESSOR MANAGEMENT AND INITIALIZATION
After the processor has switched to protected mode, the LTR instruction can be used to load a segment selector for 
a TSS descriptor into the task register. This instruction marks the TSS descriptor as busy, but does not perform a task switch. The processor can, however, use the TSS to lo cate pointers to privilege-level 0, 1, and 2 stacks. The 
segment selector for the TSS must be loaded before soft ware performs its first task switch in protected mode, 
because a task switch copies the current task state into the TSS.
After the LTR instruction has been executed, further oper ations on the task register are performed by task 
switching. As with other segments and LDTs, TSSs and TSS descriptors can be either pre-allocated or allocated as needed.
10.8.5 Initializing IA-32e Mode
On Intel 64 processors, the IA32_EFER MSR is cleared on sy stem reset. The operating system must be in protected 
mode with paging enabled before atte mpting to initialize IA-32e mode. IA-32e mode operation also requires phys-
ical-address extensions with four or five levels of enhanc ed paging structures (see Section 4.5, “4-Level Paging and 
5-Level Paging”).
Operating systems should follow this sequence to initialize IA-32e mode:1. Starting from protected mode, disable paging by setti ng CR0.PG = 0. Use the MOV CR0 instruction to disable 
paging (the instruction must be located in an identity-mapped page).
2. Enable physical-address extensions (PAE) by setting CR 4.PAE = 1. Failure to enable PAE will result in a #GP 
fault when an attempt is made to initialize IA-32e mode.
3. Load CR3 with the physical base address of the Leve l 4 page map table (PML4) or Level 5 page map table 
(PML5).
4. Enable IA-32e mode by setting IA32_EFER.LME = 1.5. Enable paging by setting CR0.PG = 1. This causes th e processor to set the IA32_EFER.LMA bit to 1. The MOV 
CR0 instruction that enables paging and the following inst ructions must be located in  an identity-mapped page 
(until such time that a branch to non-identity mapped pages can be effected).
64-bit mode paging structures must be located in the firs t 4 GBytes of physical-address space prior to activating 
IA-32e mode. This is necessary because the MOV CR3 instruct ion used to initialize the page-directory base must be 
executed in legacy mode prior to activating IA-32e mode (setting CR0.PG = 1 to enable paging). Because MOV CR3 
is executed in protected mode, only the lower 32 bits of th e register are written, limiting the table location to the 
low 4 GBytes of memory. Software can relocate the page tables anywhere in physical memory after IA-32e mode 
is activated.
The processor performs 64-bit mode consistency checks when ever software attempts to modify any of the enable 
bits directly involved in activating IA-32e mode (IA32_ EFER.LME, CR0.PG, and CR4.PAE). It will generate a general 
protection fault (#GP) if consistency checks fail. 64-bit mode consistency checks ensure that the processor does not enter an undefined mode or state with unpredictable behavior.
64-bit mode consistency checks fail in the following circumstances:
•An attempt is made to enable or disable IA-32e mode while paging is enabled.
•IA-32e mode is enabled and an attempt is made to enab le paging prior to enabling  physical-address extensions 
(PAE).
•IA-32e mode is active and an attempt is made to disable physical-address extensions (PAE).
•If the current CS has the L-bit set on an attempt to activate IA-32e mode.
•If the TR contains a 16-bit TSS on an attempt to activate IA-32e mode.
10.8.5.1  IA-32e Mode System Data Structures
After activating IA-32e mode, the system-descriptor-table registers (GDTR, LDTR, IDTR, TR) continue to reference 
legacy protected-mode descriptor tables. Tables referenced by the descriptors all reside in the lower 4 GBytes of 
linear-address space. After activating IA-32e mode, 64-bi t operating-systems should use the LGDT, LLDT, LIDT, 
and LTR instructions to load the system-descriptor-table registers with references to 64-bit descriptor tables.10-12 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
10.8.5.2  IA-32e Mode Interrupts and Exceptions
Software must not allow exceptions or interrupts to o ccur between the time IA-32e mode is activated and the 
update of the interrupt-descriptor-table register (IDTR) that establishes references to a 64-bit interrupt-descriptor 
table (IDT). This is because the IDT remains in legacy form immediately after IA-32e mode is activated.
If an interrupt or exception occurs prior to updating the IDTR, a legacy 32-bit interrupt gate will be referenced and 
interpreted as a 64-bit interrupt gate with unpredictable results. External interrupts can be disabled by using the 
CLI instruction.
Non-maskable interrupts (NMI) must be disabled using external hardware.
10.8.5.3  64-bit Mode and Compatibility Mode Operation
IA-32e mode uses two code segment-descriptor bits (CS.L and CS.D, see Figure 3-8) to control the operating modes 
after IA-32e mode is initialized. If CS.L = 1 and CS.D = 0, the processor is running in 64-bit mode. With this 
encoding, the default operand size is 32 bits and default address size is 64 bits. Using instruction prefixes, operand 
size can be changed to 64 bits or 16 bits ; address size can be changed to 32 bits. 
When IA-32e mode is active and CS.L = 0, the processor operates in compatibility mode. In this mode, CS.D 
controls default operand and address sizes exactly as it do es in the IA-32 architecture. Setting CS.D = 1 specifies 
default operand and address size as 32 bits. Clearing CS.D  to 0 specifies default operand and address size as 16 
bits (the CS.L = 1, CS.D = 1 bit combination is reserved).
Compatibility mode execution is selected on a code-segment basis. This mode allows legacy applications to coexist 
with 64-bit applications running in 64-bit mode. An operat ing system running in IA-32e mode can execute existing 
16-bit and 32-bit applications by clearing their code-segment descriptor’s CS.L bit to 0.
In compatibility mode, the following system-level mechan isms continue to operate using the IA-32e-mode archi-
tectural semantics:
•Linear-to-physical address translation uses the 64-bit mode extended page-translation mechanism.
•Interrupts and exceptions are handled using the 64-bit mode mechanisms.
•System calls (calls through call gates and SYSE NTER/SYSEXIT) are handled using the IA-32e mode 
10.8.5.4  Switching Out of  IA-32e Mode Operation
To return from IA-32e mode to paged-protected mode  operation operating systems must use the following 
sequence:
1. Switch to compatibility mode.
2. Deactivate IA-32e mode by clearing CR0.PG = 0. This causes the processor to set IA32_EFER.LMA = 0. The

sequence:
2. Deactivate IA-32e mode by clearing CR0.PG = 0. This causes the processor to set IA32_EFER.LMA = 0. The 
MOV CR0 instruction used to disable paging and subsequent instructions must be located in an identity-mapped 
page.
3. Load CR3 with the physical base address of the legacy page-table-directory base address.
4. Disable IA-32e mode by setting IA32_EFER.LME = 0.
5. Enable legacy paged-protected mode by setting CR0.PG = 16. A branch instruction must follow the MOV CR0 that  enables paging. Both the MOV CR0 and the branch 
compatibility mode to 64-bit mode.Vol. 3A 10-13PROCESSOR MANAGEMENT AND INITIALIZATION
10.9 MODE SWITCHING
To use the processor in protected mode after hardware or software reset, a mode switch must be performed from 
real-address mode. Once in protected mode, software genera lly does not need to return to real-address mode. To 
run software written to run in real-address mode (8086 mode ), it is generally more convenient to run the software 
in virtual-8086 mode, than to switch back to real-address mode.
10.9.1 Switching to Protected Mode
Before switching to protected mode from real mode, a minimum set of system data structures and code modules 
must be loaded into memory, as described in Section 10.8 , “Software Initialization for Protected-Mode Operation.” 
Once these tables are created, software initia lization code can switch into protected mode.
Protected mode is entered by executing a MOV CR0 instruct ion that sets the PE flag in the CR0 register. (In the 
same instruction, the PG flag in register CR0 can be set to  enable paging.) Execution in protected mode begins with 
a CPL of 0.
Intel 64 and IA-32 processors have slightly different requirements for switching to protected mode. To ensure 
upwards and downwards code compatibility with Intel 64 and IA-32 processors, we recommend that you follow 
these steps:
1. Disable interrupts. A CLI instruction disables maskable  hardware interrupts. NMI interrupts can be disabled 
with external circuitry. (Software must guarantee that  no exceptions or interrupts are generated during the 
mode switching operation.)
2. Execute the LGDT instruction to load the GDTR  register with the base address of the GDT.
3. Execute a MOV CR0 instruction that sets the PE flag (and optionally the PG flag) in control register CR0.
4. Immediately following the MOV CR0 instruction, execute a far JMP or far CALL instruction. (This operation is 
typically a far jump or call to the next instruction in the instruction stream.)
5. The JMP or CALL instruction immediately after the MOV CR0 instruction changes the flow of execution and 
serializes the processor.
6. If paging is enabled, the code for the MOV CR0 instru ction and the JMP or CALL instruction must come from a 
page that is identity mapped (that is, the linear addre ss before the jump is the same as the physical address 
after paging and protected mode is enabled). The target  instruction for the JMP or CALL instruction does not 
need to be identity mapped.
7. If a local descriptor table is going to be used, execute the LLDT instruction to load the segment selector for the 
LDT in the LDTR register.
8. Execute the LTR instruction to load the task register wi th a segment selector to the initial protected-mode task 
or to a writable area of memory that can be used to store TSS information on a task switch.
9. After entering protected mode, the se gment registers continue to hold the contents they had in real-address 
mode. The JMP or CALL instruction in step 4 resets the CS register. Perform one of the following operations to 
update the contents of the remaining segment registers.
— Reload segment registers DS, SS, ES, FS, and GS. If th e ES, FS, and/or GS registers are not going to be 
used, load them with a null selector.
— Perform a JMP or CALL instruction to a new task, which automatically resets the values of the segment 
registers and branches to a new code segment.
10. Execute the LIDT instruction to load the IDTR register  with the address and limit of the protected-mode IDT.
11. Execute the STI instruction to enable maskable ha rdware interrupts and perfor m the necessary hardware 
operation to enable NMI interrupts.
Random failures can occur if other instructions exist between  steps 3 and 4 above. Failures will be readily seen in 
some situations, such as when instructions that reference memory are inserted between steps 3 and 4 while in 
system management mode.10-14 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
10.9.2 Switching Back to Real-Address Mode
The processor switches from protected mode back to real -address mode if software clears the PE bit in the CR0 
register with a MOV CR0 instruction. A procedure that re-enters real-address mode should perform the following 
steps:
with external circuitry.
2. If paging is enabled, perform the following operations:
— Transfer program control to linear addresses that are identity mapped to physical addresses (that is, linear 
addresses equal physical addresses).
— Ensure that the GDT and IDT are in identity mapped pages.
— Clear the PG bit in the CR0 register.— Move 0H into the CR3 register to flush the TLB.
3. Transfer program control to a readable segment that has a limit of 64 KBytes (FFFFH). This operation loads the 
CS register with the segment limi t required in real-address mode.
4. Load segment registers SS, DS, ES, FS, and GS with a selector for a descriptor containing the following values, 
which are appropriate for real-address mode:
— Limit = 64 KBytes (0FFFFH)
— Byte granular (G = 0)
—E x p a n d  u p  ( E  =  0 )—W r i t a b l e  ( W  =  1 )
—P r e s e n t  ( P  =  1 )
— Base = any value
The segment registers must be loaded with non-null segment selectors or the segment registers will be 
unusable in real-address mode. Note that if the segmen t registers are not reloaded, execution continues using 
the descriptor attributes loaded during protected mode.
5. Execute an LIDT instruction to point to a real-address mode interrupt table that is within the 1-MByte real-
address mode address range.
6. Clear the PE flag in the CR0 register to switch to real-address mode.
7. Execute a far JMP instruction to jump to a real-addre ss mode program. This operation flushes the instruction 
queue and loads the appropriate base-address value in the CS register.
8. Load the SS, DS, ES, FS, and GS registers as needed by  the real-address mode code. If any of the registers are 
not going to be used in real-address mode, write 0s to them.
9. Execute the STI instruction to enable maskable ha rdware interrupts and perfor m the necessary hardware 
NOTE
All the code that is executed in steps 1 through 9 must be in a single page and the linear addresses in that page must be identity  mapped to physical addresses.
10.10 INITIALIZATION AND MODE SWITCHING EXAMPLE
This section provides an initialization and mode switchin g example that can be incorporated into an application. 
This code was originally written to initialize the Intel386  processor, but it will execute successfully on the Pentium 
4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The code in this example is intended to reside in EPROM 
and to run following a hardware reset of the processor.  The function of the code is to do the following:
•Establish a basic real-address mode operating environment.Vol. 3A 10-15PROCESSOR MANAGEMENT AND INITIALIZATION
•Load the necessary protected-mode system data structures into RAM.
•Load the system registers with the necessary pointers to the data structures and the appropriate flag settings 
for protected-mode operation.
•Switch the processor to protected mode.
Figure 10-3 shows the physical memory layout for the proc essor following a hardware reset and the starting point 
of this example. The EPROM that contai ns the initialization code resides at the upper end of the processor’s physical 
memory address range, starting at a ddress FFFFFFFFH and going down from ther e. The address of the first instruc-
tion to be executed is at FFFFFFF0H, the default starting address for the processor following a hardware reset.
The main steps carried out in this example are summarized  in Table 10-5. The source listing for the example (with 
the filename STARTUP.ASM) is given in Example 10-1. The line numbers given in Table 10-5 refer to the source 
listing.
The following are some additional notes concerning this example:
•When the processor is switched into protected mode , the original code segment base-address value of 
FFFF0000H (located in the hidden part of the CS register ) is retained and execution continues from the current

listing.
FFFF0000H (located in the hidden part of the CS register ) is retained and execution continues from the current 
offset in the EIP register. The processor will thus continue to execute code in the EPROM until a far jump or call 
is made to a new code segment, at which time, the base address in the CS register will be changed.
•Maskable hardware interrupts are disabled after a ha rdware reset and should remain disabled until the 
necessary interrupt handlers have been installed. The NM I interrupt is not disabled following a reset. The NMI# 
pin must thus be inhibited from being asserted until an  NMI handler has been loaded and made available to the 
•The use of a temporary GDT allows simple transfer of tables from the EPROM to anywhere in the RAM area. A 
GDT entry is constructed with its base pointing to address 0 and a limit of 4 GBytes. When the DS and ES 
registers are loaded with this descriptor, the temporary GDT is no longer needed and can be replaced by the 
application GDT.
•This code loads one TSS and no LDTs. If more TSSs exist in the application, they must be loaded into RAM. If 
there are LDTs they may be loaded as well.
Figure 10-3.  Processor State After Reset0FFFF FFFFHAfter Reset
[CS.BASE+EIP] FFFF FFF0H
EIP = 0000 FFF0H
[SP, DS, SS, ES]FFFF 0000H64K EPROM
CS.BASE = FFFF 0000H
DS.BASE = 0HES.BASE = 0HSS.BASE = 0HESP = 0H10-16 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
10.10.1 Assembler Usage
In this example, the Intel assembler ASM386 and build tool s BLD386 are used to assemble and build the initializa-
tion code module. The following assumptions are used when using the Intel ASM386 and BLD386 tools.
•The ASM386 will generate the right operand size opco des according to the code-segment attribute. The 
attribute is assigned either by the ASM386 invoca tion controls or in the code-segment definition.
•If a code segment that is going to run in real-address mode  is defined, it must be se t to a USE 16 attribute. If 
a 32-bit operand is used in an instruction in this co de segment (for example, MOV EAX, EBX), the assembler 
automatically generates an operand prefix for the instruction that forces the processor to execute a 32-bit 
operation, even though its default code-segment attribute is 16-bit.
•Intel's ASM386 assembler allows specific use of the 16- or 32-bit instructions, for example, LGDTW, LGDTD, 
IRETD. If the generic instruction LGDT is used, the defaul t- segment attribute will be used to generate the right 
opcode.
10.10.2 STARTUP.ASM Listing
Example 10-1 provides high-level sample code designed to  move the processor into protected mode. This listing 
does not include any opcode and offset information.Table 10-5.  Main Initialization St eps in STARTUP.ASM Source Listing
STARTUP.ASM Line 
NumbersDescription
From To
157 157 Jump (short) to the entry code in the EPROM
162 169 Construct a temporary GDT in RAM with one entry:
0 - null1 - R/W data segment, base = 0, limit = 4 GBytes
171 172 Load the GDTR to po int to the temporary GDT
174 177 Load CR0 with PE flag se t to switch to protected mode
179 181 Jump near to clear re al mode instruction queue
184 186 Load DS, ES registers with GD T[1] descriptor, so both point to the entire physical memory space
188 195 Perform specific board initialization that is imposed by the new protected mode196 218 Copy the application's GDT from ROM into RAM
220 238 Copy the application's IDT from ROM into RAM
241 243 Load application's GDTR244 245 Load application's IDTR
247 261 Copy the application's TSS from ROM into RAM
263 267 Update TSS descriptor and other al iases in GDT (GDT alias or IDT alias) 
277 277 Load the task register (without  task switch) using LTR instruction
282 286 Load SS, ESP with the valu e found in the application's TSS
287 287 Push EFLAGS value found in the application's TSS288 288 Push CS value found in the application's TSS
289 289 Push EIP value found in the application's TSS
290 293 Load DS, ES with the valu e found in the application's TSS
296 296 Perform IRET; pop the above values and enter the application codeVol. 3A 10-17PROCESSOR MANAGEMENT AND INITIALIZATION
Example 10-1.  STARTUP.ASM
MS-DOS* 5.0(045-N) 386(TM) MACRO ASSEMBLER STARTUP  09:44:51 08/19/92 PAGE 1
MS-DOS 5.0(045-N) 386(TM) MACRO ASSEMBLER V4.0, ASSEMBLY OF MODULE STARTUP
OBJECT MODULE PLACED IN startup.objASSEMBLER INVOKED BY: f:\386tools\ASM386.EXE startup.a58 pw (132 )
LINE     SOURCE   1      NAME    STARTUP
   2     3  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;   4  ;   5  ;   ASSUMPTIONS:   6  ;
   7  ;     1.  The bottom 64K of memory is ram, and can be used for
   8  ;         scratch space by this module.   9  ;  10  ;     2.  The system has sufficient free usable ram to copy the  11  ;         initial GDT, IDT, and TSS  12  ;  13  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  14    15  ; configuration data - must match with build definition  16    17  CS_BASE       EQU     0FFFF0000H  18    19   ; CS_BASE is the linear address of the segment STARTUP_CODE  20   ; - this is specified in the build language file  21    22  RAM_START     EQU     400H  23    24  ; RAM_START  is the start of free, usable ram in the linear  25  ; memory  space.   The GDT,  IDT, and  initial TSS  will be  26  ; copied above this space, and a small data segment will be  27  ; discarded at  this linear  address.   The 32-bit  word at  28  ; RAM_START will contain  the linear  address of  the first  29  ; free byte above the copied tables - this may be useful if  30  ; a memory manager is used.  31    32  TSS_INDEX    EQU     10  33    34  ; TSS_INDEX is the  index of the  TSS of the  first task to  35  ; run after startup  36    37    38   ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  39    40  ; ------------------------- STRUCTURES and EQU ---------------  41  ; structures for system data  42    43  ; TSS structure  44  TASK_STATE  STRUC  45      link DW ?10-18 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
  46      link_h DW ?
  47      ESP0 DD ?  48      SS0 DW ?  49      SS0_h DW ?  50      ESP1 DD ?  51      SS1 DW ?  52      SS1_h DW ?  53      ESP2 DD ?  54      SS2 DW ?  55      SS2_h DW ?  56      CR3_reg DD ?  57      EIP_reg DD ?  58      EFLAGS_regDD ?  59      EAX_reg DD ?  60      ECX_reg DD ?  61      EDX_reg DD ?  62      EBX_reg DD ?  63      ESP_reg DD ?  64      EBP_reg DD ?  65      ESI_reg DD ?  66      EDI_reg DD ?  67      ES_reg DW ?  68      ES_h DW ?  69      CS_reg DW ?  70      CS_h DW ?  71      SS_reg DW ?  72      SS_h   DW ?  73      DS_reg DW ?  74      DS_h DW ?  75      FS_reg DW ?  76      FS_h DW ?  77      GS_reg DW ?  78      GS_h DW ?  79      LDT_reg DW ?  80      LDT_h DW ?  81      TRAP_reg DW ?  82      IO_map_baseDW ?  83  TASK_STATE  ENDS  84    85  ; basic structure of a descriptor  86  DESC    STRUC  87      lim_0_15 DW ?  88      bas_0_15 DW ?  89      bas_16_23DB ?  90      access DB ?  91      gran DB ?  92      bas_24_31DB ?  93  DESC    ENDS  94    95  ; structure for use with LGDT and LIDT instructions  96  TABLE_REG   STRUC  97      table_limDW ?  98      table_linearDD ?  99  TABLE_REG   ENDSVol. 3A 10-19PROCESSOR MANAGEMENT AND INITIALIZATION
 100  
 101  ; offset of GDT and IDT descriptors in builder generated GDT 102  GDT_DESC_OFF    EQU 1*SIZE(DESC) 103  IDT_DESC_OFF    EQU 2*SIZE(DESC) 104   105  ; equates for building temporary GDT in RAM 106  LINEAR_SEL          EQU     1*SIZE (DESC) 107  LINEAR_PROTO_LO     EQU     00000FFFFH  ; LINEAR_ALIAS 108  LINEAR_PROTO_HI     EQU     000CF9200H 109   110  ; Protection Enable Bit in CR0 111  PE_BIT  EQU 1B 112   113  ; ------------------------------------------------------------ 114   115  ; ------------------------- DATA SEGMENT---------------------- 116   117  ; Initially, this  data segment starts at linear 0, according 118  ; to the processor’s power-up state. 119   120  STARTUP_DATA    SEGMENT RW 121   122  free_mem_linear_base    LABEL   DWORD 123  TEMP_GDT                LABEL   BYTE  ; must be first in segment 124  TEMP_GDT_NULL_DESC   DESC    <> 125  TEMP_GDT_LINEAR_DESC DESC    <> 126   127  ; scratch areas for LGDT and LIDT instructions 128  TEMP_GDT_SCRATCH TABLE_REG   <> 129  APP_GDT_RAM     TABLE_REG    <> 130  APP_IDT_RAM     TABLE_REG    <> 131          ; align end_data 132  fill    DW      ? 133    134  ; last thing in this segment - should be on a dword boundary 135  end_data    LABEL   BYTE 136   137  STARTUP_DATA    ENDS 138  ; ------------------------------------------------------------ 139   140   141  ; ------------------------- CODE SEGMENT---------------------- 142  STARTUP_CODE SEGMENT ER PUBLIC USE16 143   144  ; filled in by builder 145      PUBLIC  GDT_EPROM 146  GDT_EPROM   TABLE_REG   <> 147   148  ; filled in by builder 149      PUBLIC  IDT_EPROM 150  IDT_EPROM   TABLE_REG   <> 151   152  ; entry point into startup code - the bootstrap will vector 153  ; here  with a  near JMP  generated by  the builder.   This10-20 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
 154  ; label must be in the top 64K of linear memory.

154  ; label must be in the top 64K of linear memory.
 155   156      PUBLIC  STARTUP 157  STARTUP: 158   159  ; DS,ES address the bottom 64K of flat linear memory 160      ASSUME  DS:STARTUP_DATA, ES:STARTUP_DATA 161  ; See Figure 10 -4
 162  ; load GDTR with temporary GDT 163          LEA     EBX,TEMP_GDT  ; build the TEMP_GDT in low ram, 164          MOV     DWORD PTR [EBX],0   ; where we can address 165          MOV     DWORD PTR [EBX]+4,0 166          MOV     DWORD PTR [EBX]+8, LINEAR_PROTO_LO 167          MOV     DWORD PTR [EBX]+12, LINEAR_PROTO_HI 168          MOV     TEMP_GDT_scratch.table_linear,EBX 169          MOV     TEMP_GDT_scratch.table_lim,15 170   171 DB 66H; execute a 32 bit LGDT 172          LGDT    TEMP_GDT_scratch 173   174  ; enter protected mode 175          MOV     EBX,CR0 176          OR      EBX,PE_BIT 177          MOV     CR0,EBX 178  
 179   ; clear prefetch queue
 180          JMP     CLEAR_LABEL 181  CLEAR_LABEL: 182   183   ; make DS and ES address 4G of linear memory 184          MOV     CX,LINEAR_SEL 185          MOV     DS,CX 186          MOV     ES,CX 187   188    ; do board specific initialization  189    ; 190                  ;  191                  ; ...... 192                  ;  193   194   195          ; See Figure 10 -5
 196          ; copy EPROM GDT to ram at: 197          ;                RAM_START + size (STARTUP_DATA) 198          MOV     EAX,RAM_START 199          ADD     EAX,OFFSET (end_data)    200          MOV     EBX,RAM_START 201          MOV     ECX, CS_BASE 202          ADD     ECX, OFFSET (GDT_EPROM)  203          MOV     ESI, [ECX].table_linear 204          MOV     EDI,EAX 205          MOVZX   ECX, [ECX].table_lim 206          MOV     APP_GDT_ram[EBX].table_lim,CXVol. 3A 10-21PROCESSOR MANAGEMENT AND INITIALIZATION
 207          INC     ECX
 208          MOV     EDX,EAX 209          MOV     APP_GDT_ram[EBX].table_linear,EAX 210          ADD     EAX,ECX 211      REP MOVS    BYTE PTR ES:[EDI],BYTE PTR DS:[ESI] 212   213          ; fixup GDT base in descriptor 214          MOV     ECX,EDX 215          MOV     [EDX].bas_0_15+GDT_DESC_OFF,CX 216          ROR     ECX,16 217          MOV     [EDX].bas_16_23+GDT_DESC_OFF,CL 218          MOV     [EDX].bas_24_31+GDT_DESC_OFF,CH 219   220          ; copy EPROM IDT to ram at: 221          ; RAM_START+size(STARTUP_DATA)+SIZE (EPROM GDT) 222          MOV     ECX, CS_BASE 223          ADD     ECX, OFFSET (IDT_EPROM)      224          MOV     ESI, [ECX].table_linear 225          MOV     EDI,EAX 226          MOVZX   ECX, [ECX].table_lim 227          MOV     APP_IDT_ram[EBX].table_lim,CX 228          INC     ECX 229          MOV     APP_IDT_ram[EBX].table_linear,EAX 230          MOV     EBX,EAX 231          ADD     EAX,ECX 232      REP MOVS    BYTE PTR ES:[EDI],BYTE PTR DS:[ESI] 233   234                  ; fixup IDT pointer in GDT 235          MOV     [EDX].bas_0_15+IDT_DESC_OFF,BX 236          ROR     EBX,16 237          MOV     [EDX].bas_16_23+IDT_DESC_OFF,BL 238          MOV     [EDX].bas_24_31+IDT_DESC_OFF,BH 239   240                  ; load GDTR and IDTR 241          MOV     EBX,RAM_START 242                  DB      66H         ; execute a 32 bit LGDT 243          LGDT    APP_GDT_ram[EBX]     244                  DB      66H         ; execute a 32 bit LIDT 245          LIDT    APP_IDT_ram[EBX]     246   247                  ; move the TSS 248          MOV     EDI,EAX 249          MOV     EBX,TSS_INDEX*SIZE(DESC) 250          MOV     ECX,GDT_DESC_OFF ;build linear address for TSS 251          MOV     GS,CX 252          MOV     DH,GS:[EBX].bas_24_31 253          MOV     DL,GS:[EBX].bas_16_23 254          ROL     EDX,16 255          MOV     DX,GS:[EBX].bas_0_15 256          MOV     ESI,EDX 257          LSL     ECX,EBX 258          INC     ECX 259          MOV     EDX,EAX 260          ADD     EAX,ECX10-22 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
 261      REP MOVS    BYTE PTR ES:[EDI],BYTE PTR DS:[ESI]
 262 263                  ; fixup TSS pointer 264          MOV     GS:[EBX].bas_0_15,DX 265          ROL     EDX,16 266          MOV     GS:[EBX].bas_24_31,DH 267          MOV     GS:[EBX].bas_16_23,DL 268          ROL     EDX,16 269      ;save start of free ram at linear location RAMSTART 270          MOV     free_mem_linear_base+RAM_START,EAX 271 272      ;assume no  LDT used in  the initial task  - if necessary, 273      ;code  to move the LDT could be added, and should resemble 274      ;that used to move the TSS 275 276      ; load task register 277          LTR     BX   ; No task switch, only descriptor loading 278      ; See Figure 10 -6
 279      ; load minimal set of registers necessary to simulate task 280      ; switch 281   282 283          MOV     AX,[EDX].SS_reg     ; start loading registers 284          MOV     EDI,[EDX].ESP_reg 285          MOV     SS,AX 286          MOV     ESP,EDI             ; stack now valid 287          PUSH    DWORD PTR [EDX].EFLAGS_reg 288          PUSH    DWORD PTR [EDX].CS_reg 289          PUSH    DWORD PTR [EDX].EIP_reg 290          MOV     AX,[EDX].DS_reg 291          MOV     BX,[EDX].ES_reg 292          MOV     DS,AX     ; DS and ES no longer linear memory 293          MOV     ES,BX
294
 295          ; simulate far jump to initial task 296          IRETD 297 298  STARTUP_CODE  ENDS*** WARNING #377 IN 298, (PASS 2) SEGMENT CONTAINS PRIVILEGED INSTRUCTION(S) 299 300  END STARTUP, DS:STARTUP_DATA, SS:STARTUP_DATA 301 302
ASSEMBLY COMPLETE,   1 WARNING,   NO ERRORS.Vol. 3A 10-23PROCESSOR MANAGEMENT AND INITIALIZATION
Figure 10-4.  Constructing Temporary GDT and Switchin g to Protected Mode (Lines 162-172 of List File)FFFF FFFFH
Base=0, Limit=4GSTART: [CS.BASE+EIP]
TEMP_GDT• Jump near startFFFF 0000H
• Construct TEMP_GDT
• LGDT• Move to protected mode
DS, ES = GDT[1] 4 GB
0GDT [1]
GDT [0]GDT_SCRATCHBase
Limit10-24 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
Figure 10-5.  Moving the GDT, IDT, and TSS fr om ROM to RAM (Lines 196-261 of List File)FFFF FFFFH
GDT RAM• Move the GDT, IDT, TSS
• Fix Aliases
• LTR
0RAM_STARTTSS
IDT
GDT
TSS RAM
IDT RAMfrom ROM to RAMVol. 3A 10-25PROCESSOR MANAGEMENT AND INITIALIZATION
10.10.3 MAIN.ASM Source Code
The file MAIN.ASM shown in Example 10-2 defines the da ta and stack segments for this application and can be 
substituted with the main module task written in a high-l evel language that is invoked by the IRET instruction 
executed by STARTUP.ASM. 
Example 10-2.  MAIN.ASM
NAME    main_module
data    SEGMENT RW
dw 1000 dup(?)
DATA    ENDS
stack stackseg 800CODE SEGMENT ER  use32 PUBLIC
main_start:
nop
nop
nop
CODE  ENDSEND main_start, ds:data, ss:stack
10.10.4 Supporting Files
The batch file shown in Example 10-3 can be used to a ssemble the source code file s STARTUP.ASM and MAIN.ASM 
and build the final application.Figure 10-6.  Task Switching (Lines 282-296 of List File)GDT RAMRAM_STARTTSS RAM
IDT RAM
GDT AliasIDT AliasDSEIP
EFLAGS
CS
SS
0ESESP
••
•
•
•
•SS = TSS.SS
ESP = TSS.ESPPUSH TSS.EFLAGPUSH TSS.CSPUSH TSS.EIPES = TSS.ES
DS = TSS.DSIRET
GDT10-26 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
Example 10-3.  Batch File to Assemble and Build the Application
ASM386 STARTUP.ASM
ASM386 MAIN.ASMBLD386 STARTUP.OBJ, MAIN.OBJ buildfile(EPROM.BLD) bootstrap(STARTUP) Bootload
BLD386 performs several operations in this example:
It allocates physical memory location to segments and tables.It generates tables using the build file and the input files.It links object files and resolves references.It generates a boot-loadable file to be programmed into the EPROM.
Example 10-4 shows the build file used as an in put to BLD386 to perform the above functions.
Example 10-4.  Build File
INIT_BLD_EXAMPLE;
SEGMENT
        *SEGMENTS(DPL = 0)    ,   startup.startup_code(BASE = 0FFFF0000H)    ;
TASK
        BOOT_TASK(OBJECT = startup, INITIAL,DPL = 0, 
NOT INTENABLED)
,       PROTECTED_MODE_TASK(OBJECT = main_module,DPL = 0, 
    ;
TABLE
    GDT (        LOCATION = GDT_EPROM    ,   ENTRY = (            10:   PROTECTED_MODE_TASK    , startup.startup_code    ,       startup.startup_data    ,       main_module.data    ,       main_module.code    ,       main_module.stack
          )
        ),
    IDT (
        LOCATION = IDT_EPROM        );
MEMORY
    (        RESERVE = (0..3FFFH 
-- Area for the GDT, IDT, TSS copied from ROM
    ,              60000H..0FFFEFFFFH)    ,   RANGE = (ROM_AREA = ROM (0FFFF0000H..0FFFFFFFFH)) 
-- Eprom size 64K
    ,   RANGE = (RAM_AREA = RAM (4000H..05FFFFH))Vol. 3A 10-27PROCESSOR MANAGEMENT AND INITIALIZATION
    );
END
Table 10-6 shows the relationship of each build item with an ASM source file.
10.11 MICROCODE UPDATE FACILITIES
The P6 family and later processors have the capability to co rrect errata by loading an In tel-supplied data block into 
the processor. The data block is called a microcode update. This section describes the mechanisms the BIOS needs 
to provide in order to use this feature during system initia lization. It also describes a specification that permits the 
incorporation of future updates into a system BIOS.
Intel considers the release of a microcode update for a silicon  revision to be the equivalent of a processor stepping 
and completes a full-stepping level validation for releases of microcode updates.
A microcode update is used to correct errata in the proce ssor. The BIOS, which has an update loader, is responsible 
for loading the update on processors du ring system initialization (Figure 10-7). There are two steps to this process: 
the first is to incorporate the necessary update data blocks into the BIOS; the second is to load update data blocks 
into the processor.Table 10-6.  Relationship Betwee n BLD Item and ASM Source File 
Item ASM386 and Startup.A58 BLD386 Controls 
and BLD fileEffect
Bootstrap public startup
startup:bootstrap
start(startup)Near jump at 0FFFFFFF0H to 
start.
GDT location public GDT_EPROM
GDT_EPROM TABLE_REG  <>TABLE

start.
GDT(location = GDT_EPROM)The location of the GDT will be 
programmed into the 
GDT_EPROM location.
IDT location public IDT_EPROM
IDT_EPROM TABLE_REG  <>TABLE
IDT(location = IDT_EPROMThe location of the IDT will be 
IDT_EPROM location.
RAM start RAM_START equ 400H memory (reserve = (0..3FFFH)) RAM_START is used as the ram 
destination for moving the 
tables. It must be excluded from the application's segment area.
Location of the 
application TSS in 
the GDTTSS_INDEX EQU 10 TABLE GDT(
ENTRY = (10: PROTECTED_MODE_
TASK))Put the descriptor of the 
application TSS in GDT entry 10.
EPROM size and 
locationsize and location of  the initialization 
codeSEGMENT startup.code (base = 
0FFFF0000H) ...memory (RANGE(
ROM_AREA = ROM(x..y)) Initialization code  size must be 
less than 64K an d resides at 
upper most 64K of the 4-GByte memory space.10-28 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
10.11.1 Microcode Update
A microcode update consists of an Intel-supplied binary th at contains a descriptive header and data. No executable 
code resides within the update. Each microcode update is tailored for a specific list of processor signatures. A 
mismatch of the processor’s signature with the signature co ntained in the update will result in a failure to load. A 
processor signature includes the extended family, extend ed model, type, family, model, and stepping of the 
processor (starting with processor family 0fH, model 03H, a given microcode update may be associated with one of 
multiple processor signatures; see Section 10.11.2 for details).
Microcode updates are composed of a multi-byte header, followed by encryp ted data and then by an optional 
extended signature table. Table 10-7 provides a definition of the fields; Table 10-8 shows the format of an update. 
The header is 48 bytes. The first 4 bytes of the header  contain the header version. The update header and its 
reserved fields are interpreted by so ftware based upon the header version.  An encoding scheme guards against 
tampering and provides a means for dete rmining the authenticity of any given update. For microcode updates with 
a data size field equal to 00000000H, the size of the micr ocode update is 2048 bytes. The first 48 bytes contain the 
microcode update header. The remaining 2000 bytes contain encrypted data. 
For microcode updates with a data size not equal to 000000 00H, the total size field specifies the size of the micro-
code update. The first 48 bytes contain the microcode upda te header. The second part of the microcode update is 
the encrypted data. The data size field of the microcode up date header specifies the encrypted data size, its value 
must be a multiple of the size of DWORD. The total si ze field of the microcode update header specifies the 
encrypted data size plus the header size; its value must be in multiples of 1024 bytes (1 KBytes). The optional 
extended signature table if implemented follows the encrypted data, and its size is calculated by (Total Size – (Data 
Size + 48)). 
NOTE
The optional extended signature table is supported  starting with processor family 0FH, model 03H.Figure 10-7.  Applyi ng Microcode Updates
Table 10-7.  Microcode Update Field Definitions
Field Name Offset (bytes) Length 
(bytes)Description
Header Version 0 4 Version number of the update header.
Update Revision 4 4 Unique version number fo r the update, the ba sis for the update 
signature provided by the processor to indicate the current update functioning within the pr ocessor. Used by the BIOS to authenticate 
the update and verify that the processor loads successfully. The 
value in this field cannot be used for processor stepping identification 
alone. This is a signed 32-bit number.
Date 8 4 Date of the update creation  in binary form at: mmddyyyy (e.g., 
07/18/98 is 07181998H).CPU
BIOSUpdate
BlocksNew UpdateUpdate
LoaderVol. 3A 10-29PROCESSOR MANAGEMENT AND INITIALIZATION
Processor Signature 12 4 Extended family, extended model, type, family, model , and stepping  
of processor that requires this particular update revision (e.g., 00000650H). Each microcode update is designed specifically for a 
given extended family, extended model,  type, family, model , and 
stepping  of the processor. 
Software should use the processor signature field in conjunction with 
the CPUID instruction to determin e whether or not an update is 
appropriate to load on a processor. The information encoded within 
this field exactly corresponds to the bit representations returned by 
Checksum 16 4 Checksum of Update Data and He ader. Used to verify the integrity of 
the update header and data. Checksum is correct when the 
summation of all the DWORDs (inc luding the extended Processor 
Signature Table) that comprise the microcode update result in 00000000H.
Loader Revision 20 4 Version number of the loader program needed to correctly load this 
update. The initial version is 00000001H.
Processor Flags 24 4 Platform type information is encoded in the lower 8 bits of this 4-
byte field. Each bit represents a particular platform type for a given 
CPUID. Software should use the pr ocessor flags field in conjunction 
with the platform Id bi ts in MSR (17H) to de termine whether or not 
an update is appropriate to load on a processor.  Multiple bits may be 
set representing support for multiple platform IDs.
Data Size 28 4 Specifies the si ze of the encrypted data in bytes, and must be a 
multiple of DWORDs. If this value is 00000000H, then the microcode 
update encrypted data is 2000 bytes (or 500 DWORDs).
Total Size 32 4 Specifies the to tal size of the mi crocode update in bytes. It is the 
summation of the header size, the en crypted data size and the size of 
the optional extended signature table. This value is always a multiple 
of 1024.
Reserved 36 12 Reserved fields for future expansion.
Update Data 48 Data Size or 
2000Update data.
Extended Signature 
CountData Size + 48 4 Specifies the number of extended signature structures (Processor 
Signature[n], processor flags[n] and checksum[n]) that exist in this 
microcode update.
Extended Checksum Data Size + 52 4 Checksum of update extended processor signature table. Used to 
verify the integrity of the extended processor signature table. 
Checksum is correct when the summation of the DWORDs that comprise the extended processor signature table results in 
00000000H.
Reserved Data Size + 56 12 Reserved fields.Table 10-7.  Microcode Update  Field Definitions (Contd.)
(bytes)Description10-30 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
Processor Signature[n] Data Size + 68 + 
(n * 12)4 Extended family, extended model, type, family, model , and stepping  
of processor that requires this pa rticular update revision (e.g., 
00000650H). Each microcode update is designed specifically for a 
Processor Flags[n] Data Size + 72 + 
(n * 12)4 Platform type informatio n is encoded in the lower 8 bits of this 4-
CPUID. Software should use the processor flags field in conjunction 
Checksum[n] Data Size + 76 + 
(n * 12)4 Used by utility software to decompose a microcode update into 
multiple microcode updates where each of the new updates is 
constructed without the optional  Extended Processor Signature 
Table.
To calculate the Checksum, subs titute the Primary Processor 
Signature entry and the Proc essor Flags entry with the 
corresponding Extended Patch entry. Delete the Extended Processor 
Signature Table entries. The Checksum is correct when the summation of all DWORDs that comprise the cr eated Extended 
Processor Patch resu lts in 00000000H.
Table 10-8.  Microcode Update Format
31 24 16 8 0 Bytes
Header Version 0
Update Revision 4
Month: 8 Day: 8 Year: 16 8
Processor Signature (CPUID) 12
Res: 4Extended
Family: 8Extended 
Mode: 4Reserved: 2Type: 2Family: 4Model: 4Stepping: 4
Checksum 16
Loader Revision 20
Processor Flags 24
Reserved (24 bits)P7P6P5P4P3P2P1P0
Data Size 28
Total Size 32
Reserved (12 Bytes) 36Table 10-7.  Microcode Update  Field Definitions (Contd.)
(bytes)DescriptionVol. 3A 10-31PROCESSOR MANAGEMENT AND INITIALIZATION
10.11.2 Optional Extended Signature Table
The extended signature table is a structure that may be  appended to the end of the encrypted data when the

The extended signature table is a structure that may be  appended to the end of the encrypted data when the 
encrypted data only supports a single processor signature (optional case). The extended signature table will always 
be present when the encrypted data supports multiple  processor steppings and/or models (required case). 
The extended signature table consists of a 20-byte exte nded signature header structure, which contains the 
extended signature count, the extended processor signat ure table checksum, and 12 reserved bytes (Table 10-9). 
Following the extended signature header structure, th e extended signature table contains 0-to-n extended 
processor signature structures.
Each processor signature structure consist of the processor signature, processor flags, and a checksum 
(Table 10-10). 
The extended signature count in the ex tended signature header structure indi cates the number of processor signa-
ture structures that exist in the extended signature table.  
The extended processor signature table checksum is a chec ksum of all DWORDs that comprise the extended signa-
ture table. That includes the extended signature count, extended processor signature table checksum, 12 reserved 
bytes and the n processor signature structures. A valid ex tended signature table exists when the result of a 
DWORD checksum is 00000000H.Update Data (Data Size bytes, or  2000 Bytes if Data Size = 00000000H) 48
Extended Signature Count ‘n’ Data Size + 
48
Extended Processor Signature Table Checksum Data Size + 
52
Reserved (12 Bytes) Data Size + 
56
Processor Signature[n] Data Size + 
68 + 
(n * 12)
Processor Flags[n] Data Size + 
72 + 
(n * 12)
Checksum[n] Data Size + 
76 + (n * 12)
Table 10-9.  Extended Processor Signature Table Header Structure
Extended Signature Count ‘n’ Data Size + 48
Extended Processor Signature Table Checksum Data Size + 52Reserved (12 Bytes) Data Size + 56
Table 10-10.  Processo r Signature Structure 
Processor Signature[n] Data Size + 68 + (n * 12)
Processor Flags[n] Data Size + 72 + (n * 12)
Checksum[n] Data Size  + 76 + (n * 12)Table 10-8.  Microcode Update Format (Contd.)
31 24 16 8 0 Bytes10-32 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
10.11.3 Processor Identification
Each microcode update is designed to for a specific processor or set of processors. To determine the correct micro-
code update to load, software must ensure that one of the processor signatures embedded in the microcode update 
matches the 32-bit processor signature returned by the CP UID instruction when executed by the target processor 
with EAX = 1.  Attempting to load a microcode update th at does not match a processor signature embedded in the 
microcode update with the processor signature returned  by CPUID will cause the BIOS to reject the update.
Example 10-5 shows how to check for a valid processor signature match between the processor and microcode 
update.
Example 10-5.  Pseudo Code to Validate the Processor Signature
ProcessorSignature ← CPUID(1):EAX
If (Update.HeaderVersion = 00000001h)
{
// first check the ProcessorSignature field
If (ProcessorSignature = Update.ProcessorSignature)
Success
// if extended signature is present
Else If (Update.TotalSize > (Update.DataSize + 48)){
//
// Assume the Data Size has been used to calculate the 
// location of Update.ProcessorSignature[0].
//
For (N ← 0; ((N < Update.ExtendedSignatureCount) AND 
 (ProcessorSignature ≠ Update.ProcessorSignature[N])); N++);
// if the loops ended when the iteration count is
// less than the number of processor signatures in// the table, we have a match
If (N < Update.ExtendedSignatureCount)
Success
Else
Fail
}Else
Fail
Else
Fail 
10.11.4 Platform Identification
In addition to verifying the processor signature, the intend ed processor platform type must be determined to prop-
erly target the microcode update. The intended proc essor platform type is determined by reading the 
IA32_PLATFORM_ID register, (MSR 17H).  This 64-bit register must be read using the RDMSR instruction. 
The three platform ID bits, when read as a binary code d decimal (BCD) number, indicate the bit position in the 
microcode update header’s processor flags field associated with the installed processor.  The processor flags in the 
48-byte header and the processor flags field associated with the extended processor signature structures may have 
multiple bits set. Each set bit represents a di fferent platform ID that the update supports.
Register Name: IA32_PLATFORM_ID
MSR Address: 017HVol. 3A 10-33PROCESSOR MANAGEMENT AND INITIALIZATION
Access: Read Only
IA32_PLATFORM_ID is a 64-bit register accessed only when referenced as a Qword through a RDMSR instruction.
To validate the platform information, software may implement an algorithm similar to the algorithms in 
Example 10-6.
Example 10-6.  Pseudo Code Ex ample of Processor Flags Test
Flag ← 1 << IA32_PLATFORM_ID[52:50]
{
If (Update.ProcessorFlags & Flag){
Load Update
}Else
{
//
// location of Update.ProcessorSignature[N] and a match// on Update.ProcessorSignature[N] has already succeeded
//
If (Update.ProcessorFlags[n] & Flag)
{
}
}
}
10.11.5 Microcode Update Checksum
Each microcode update contains a DWORD checksum located in  the update header. It is software’s responsibility to 
ensure that a microcode update is not corrupt. To check for a corrupt microcode update, software must perform a Table 10-11.  Processor Flags
Bit Descriptions
63:53 Reserved
52:50 Platform Id Bits (RO). The field gives information concerning the intended platform for the processor. See also Table 
10-8.
52 51 50
000P r o c e s s o r  F l a g  0001P r o c e s s o r  F l a g  1010P r o c e s s o r  F l a g  2011P r o c e s s o r  F l a g  3
100P r o c e s s o r  F l a g  4
101P r o c e s s o r  F l a g  5110P r o c e s s o r  F l a g  6111P r o c e s s o r  F l a g  7
49:0 Reserved10-34 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
unsigned DWORD (32-bit) checksum of the microcode upda te. Even though some fields are signed, the checksum 
procedure treats all DWORDs as unsigned. Microcode updates with a header version equal to 00000001H must sum all DWORDs that comprise the microcode update. A valid checksum check will yield a value of 00000000H. Any 
other value indicates the microcode update is corrupt and should not be loaded.
The checksum algorithm shown by the pseudo code in Ex ample 10-7 treats the microcode update as an array of 
unsigned DWORDs. If the data size DWORD field at byte  offset 32 equals 00000000H, the size of the encrypted 
data is 2000 bytes, resulting in 500 DWORDs. Othe rwise the microcode update size in DWORDs = ( Total Size / 4 ), 
where the total size is a multiple of 1024 bytes (1 KBytes).
Example 10-7.  Pseudo Code  Example of Checksum Test
N ← 512
If (Update.DataSize ≠ 00000000H)
N ← Update.TotalSize / 4
ChkSum ← 0
For (I ← 0; I < N; I++)
{
ChkSum ← ChkSum + MicrocodeUpdate[I]
}
If (ChkSum = 00000000H)
Success
Else
Fail
10.11.6 Microcode Update Loader
This section describes an update loader used to load an upda te into a P6 family or later processors. It also discusses 
the requirements placed on the BIOS to ensure proper lo ading. The update loader described contains the minimal 
instructions needed to load an update. The specific instru ction sequence that is required to load an update is 
dependent upon the loader revision field contained within the update header. This revision is expected to change 
infrequently (potentially, only when new processor models are introduced).
Example 10-8 below represents the update loader with a loader revision of 00000001H. Note that the microcode 
update must be aligned on a 16-byte boundary and the si ze of the microcode update must be 1-KByte granular.
Example 10-8.  Assembly Code Exampl e of Simple Microcode Update Loader
mov ecx,79h ; MSR to write in ECX
xor eax,eax ; clear EAXxor ebx,ebx ; clear EBXmov ax,cs ; Segment of microcode updateshl eax,4mov bx,offset Update ; Offset of microcode updateadd eax,ebx ; Linear Address of Update in EAXadd eax,48d ; Offset of the Update Data within the Updatexor edx,edx ; Zero in EDXWRMSR ; microcode update trigger
The loader shown in Example 10-8 assumes that update is the address of a microcode update (header and data) 
embedded within the code segment of the BIOS. It also assumes that the processor is operating in real mode. The data may reside anywhere in memory, aligned on a 16-byte boundary, that is accessible by the processor within its 
current operating mode.
Before the BIOS executes the microcode update trigge r (WRMSR) instruction, the following must be true:Vol. 3A 10-35PROCESSOR MANAGEMENT AND INITIALIZATION
•In 64-bit mode, EAX contains the lower 32-bits of the mi crocode update linear addre ss. In protected mode, EAX 
contains the full 32-bit linear address of the microcode update.
•In 64-bit mode, EDX contains the upper 32-bits of th e microcode update linear address. In protected mode, 
EDX equals zero.
•ECX contains 79H (address of IA32_BIOS_UPDT_TRIG).

Other requirements are:
•The addresses for the microcode update data must be in canonical form.
•If paging is enabled, the microcode update data must map that data as present.
•The microcode update data must start at a 16-byte aligned linear address.
10.11.6.1  Hard Resets in Update Loading
The effects of a loaded update are cleared from the processo r upon a hard reset. Therefore, each time a hard reset 
is asserted during the BIOS POST, the update must be re loaded on all processors that observed the reset. The 
effects of a loaded update are, howeve r, maintained across a processor INIT. There are no side effects caused by 
loading an update into a processor multiple times.
10.11.6.2  Update in a Multiprocessor System
A multiprocessor (MP) system requires loading each proce ssor with update data appropriate for its CPUID and plat-
form ID bits. The BIOS is responsible for ensuring that th is requirement is met and that the loader is located in a 
module executed by all processors in the system. If a syst em design permits multiple steppings of Pentium 4, Intel 
Xeon, and P6 family processors to exist concurrently; then the BIOS must verify individual processors against the update header information to ensure ap propriate loading. Given these considerations, it is most practical to load 
the update during MP initialization.
10.11.6.3  Update in a System Support ing Intel Hyper-Threading Technology 
Intel Hyper-Threading Technology has implications on th e loading of the microcode update. The update must be 
loaded for each core in a physical processor. Thus, fo r a processor supporting Intel Hyper-Threading Technology, 
only one logical processor per core is required to load the microcode update. Each individual logical processor can 
independently load the update . However, MP initialization must provide some mechanism (e.g., a software sema-
phore) to force serialization of microcode update loads and to prevent simultaneous load attempts to the same 
core.
10.11.6.4  Update in a System Supporting Dual-C ore Technology 
Dual-core technology has implications on the loading of th e microcode update. The microcode update facility is not 
shared between processor cores in the same physical packag e. The update must be loaded for each core in a phys-
ical processor. 
If processor core supports Intel Hyper-Threading Techno logy, the guideline described in Section 10.11.6.3 also 
applies.
10.11.6.5  Update Loader Enhancements
The update loader presented in Section 10.11.6, “Microcode  Update Loader,” is a minimal implementation that can 
be enhanced to provide additional functionality. Potential enhancements are described below:
•BIOS can incorporate multiple updates to support mult iple steppings of the Pentium 4, Intel Xeon, and P6 
family processors. This feature provides for operating in a mixed stepping environment on an MP system and 
enables a user to upgrade to a later version of the proce ssor. In this case, modify the loader to check the CPUID 
and platform ID bits of the processor that it is ru nning on against the available headers before loading a 
particular update. The number of updates is  only limited by available BIOS space.10-36 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
•A loader can load the update and test the processor to determine if the update  was loaded correctly. See 
Section 10.11.7, “Update Signature and Verification.”
•A loader can verify the integrity of the update data by performing a checksum on the double words of the 
update summing to zero. See Section 10.11.5, “Microcode Update Checksum.”
•A loader can provide power-on messages indicating successful loading of an update.
10.11.7 Update Signature and Verification
The P6 family and later processors provide capabilities to ve rify the authenticity of a particular update and to iden-
tify the current update revision. This section describes the model-specific extensions of processors that support 
this feature. The update verification method below assumes that the BIOS will only verify  an update that is more 
recent than the revision currently loaded in the processor.
CPUID returns a value in a model specific register in additi on to its usual register return values. The semantics of 
CPUID cause it to deposit an update ID value in the 64-bit model-specific register at address 08BH 
(IA32_BIOS_SIGN_ID). If no update is  present in the processor, the value in the MSR remains unmodified. The 
BIOS must pre-load a zero into the MSR before executing CP UID. If a read of the MSR at 8BH still returns zero after 
executing CPUID, this indicates that no update is present.
The update ID value returned in the EDX register after RD MSR executes indicates the revision of the update loaded 
in the processor. This value, in comb ination with the CPUID value returned in the EAX register, uniquely identifies a 
particular update. The signature ID can be directly compar ed with the update revision field in a microcode update 
header for verification of a correct load. No consecutive updates released for a given stepping of a processor may 
share the same signature. The processor signature returned by CPUID differentiates updates for different step-
pings.
10.11.7.1  Determining the Signature
An update that is successfully loaded into the processor provides a signature that matches the update revision of 
the currently functioning revision. This signature is ava ilable any time after the actual update has been loaded. 
Requesting the signature does not have a negative impact upon a loaded update.  
The procedure for determining this  signature shown in Example 10-9.
Example 10-9.  Assembly Code to  Retrieve the Update Revision
MOV ECX, 08BH ;IA32_BIOS_SIGN_ID
XOR EAX, EAX ;clear EAXXOR EDX, EDX ;clear EDXWRMSR ;Load 0 to MSR at 8BHMOV EAX, 1cpuidMOV ECX, 08BH ;IA32_BIOS_SIGN_IDrdmsr ;Read Model Specific Register
If there is an update active in the processor, its revision  is returned in the EDX register after the RDMSR instruction 
executes.
IA32_BIOS_SIGN_ID Microcode Update Signature Register 
MSR Address: 08BH Accessed as a Qword
Default Value: XXXX XXXX XXXX XXXXhAccess: Read/Write
The IA32_BIOS_SIGN_ID register is used to report th e microcode update signatur e when CPUID executes. The 
signature is returned in the upper DWORD (Table 10-12).Vol. 3A 10-37PROCESSOR MANAGEMENT AND INITIALIZATION
10.11.7.2  Authenti cating the Update
An update may be authenticated by the BIOS using the si gnature primitive, described above, and the algorithm in 
Example 10-10.
Example 10-10.  Pseudo Code to Authenticate the Update
Z ← Obtain Update Revision from the Update Header to be authenticated;
X ← Obtain Current Update Signature from MSR 8BH;
If (Z > X)
{
Load Update that is to be authenticated;
Y ← Obtain New Signature from MSR 8BH;
If (Z = Y)
Success
Else
Fail
}Else
Fail
Example 10-10 requires that the BIOS only authenticate u pdates that contain a numerically larger revision than 
the currently loaded revision, where Current Signature (X) <  New Update Revision (Z). A processor with no loaded 
update is considered to have a revision equal to zero.
This authentication procedure relies upon the decoding prov ided by the processor to verify an update from a poten-
tially hostile source.  As an example, this mechanism in  conjunction with other safeguards provides security for 
dynamically incorporating fi eld updates into the BIOS.
10.11.8 Optional Processor Microcode Update Specifications
This section an interface that an OEM-BIOS may provide to its client system software to manage processor micro-
code updates. System software may choose to build its own facility to manage microcode updates (e.g., similar to the facility described in Section 9.11.6) or rely on a fa cility provided by the BIOS to perform microcode updates.
Sections 10.11.8.1-10.11.8.9 describes an extension (Functi on 0D042H) to the real mode INT 15H service. INT 
15H 0D042H function is one of several alternatives that a BIOS may choose to implement microcode update facility 
and offer to its client application (e.g., an OS). Other alternative microcode update facility that BIOS can choose 
are dependent on platform-specific capabilities, includin g the Capsule Update mechanism from the UEFI specifica-
tion (www.uefi.org). In this discussion, the applicat ion is referred to as the calling program or caller.
The real mode INT15 call specification described here is an  Intel extension to an OEM BIOS. This extension allows 
an application to read and modify the contents of the mi crocode update data in NVRAM. The update loader, which 
is part of the system BIOS, cannot be updated by the interf ace. All of the functions defined in the specification must 
be implemented for a system to be considered compliant with the specification. The INT15 functions are accessible 
only from real mode.Table 10-12.  Microcod e Update Signature 
63:32 Microcode update signature. This field contains the signature of the currently loaded microcode update when read following

63:32 Microcode update signature. This field contains the signature of the currently loaded microcode update when read following  
the execution of the CPUID instruction, function 1. It is requir ed that this register  field be pre-loaded with zero prior to 
executing the CPUID, function 1. If the field remains equal to zero, then there is no microcode update loaded. Another non-
zero value will be  the signature.
31:0 Reserved.10-38 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
10.11.8.1  Responsibilities of the BIOS
If a BIOS passes the presence test (INT 15H, AX = 0D042H , BL = 0H), it must implem ent all of the sub-functions 
defined in the INT 15H, AX = 0D042H specification. There are no optional functions. BIOS  must load the appropriate 
update for each processor during system initialization.
A Header Version of an update block containing the valu e 0FFFFFFFFH indicates that the update block is unused and 
available for storing a new update.
The BIOS is responsible for providing a region of non-vo latile storage (NVRAM) for each potential processor step-
ping within a system. This storage unit consists of one or more update blocks. An update block is a contiguous 
2048-byte block of memory. The BIOS for a single processo r system need only provide update blocks to store one 
microcode update. If the BIOS for a multiple processor sy stem is intended to support mixed processor steppings, 
then the BIOS needs to provide enough update blocks to store each unique microcode update or for each processor 
socket on the OEM’s system board. 
The BIOS is responsible for managing the NVRAM update  blocks. This includes garbage collection, such as 
removing microcode updates that exist in NVRAM for which a corresponding processor does not exist in the system. 
This specification only provides the me chanism for ensuring security, the uniqueness of an entry, and that stale 
entries are not loaded. The actual update block manageme nt is implementation specific on a per-BIOS basis. 
As an example, the BIOS may use update blocks sequentially in ascendin g order with CPU signatures sorted versus 
the first available block. In addition, garbage collection may be implemented as a setup option to clear all NVRAM 
slots or as BIOS code that searches and eliminates unused entries during boot.
NOTES
For IA-32 processors starting with family 0F H and model 03H and Intel 64 processors, the 
microcode update may be as large as 16 KBytes. Thus, BIOS must allocate 8 update blocks for each microcode update. In a MP system, a common microcode update may be sufficient for each socket 
in the system. 
For IA-32 processors earlier than family 0FH and model 03H, the microcode update is 2 KBytes. An 
MP-capable BIOS that supports multiple stepping s must allocate a block for each socket in the 
system.
A single-processor BIOS that supports variable-siz ed microcode update and fixed-sized microcode 
update must allocate one 16-KByte region and a second region of at least 2 KBytes.
The following algorithm (Example 10-11) describes the steps pe rformed during BIOS initialization used to load the 
updates into the processor(s). The algorithm assumes:
•The BIOS ensures that no update contained within NVRAM has a header version or loader version that does not 
match one currently supported by the BIOS.
•The update contains a correct checksum.
•The BIOS ensures that (at most) one update exists for each processor stepping.
•Older update revisions are not allowed to overwrite more recent ones.
These requirements are checked by the BIOS during the exec ution of the write update function of this interface. 
The BIOS sequentially scans through all of the update bloc ks in NVRAM starting with index 0. The BIOS scans until 
it finds an update where the processor fields in the header match the processor signature (extended family, 
extended model, type, family, model, and stepping) as well as the platform bits of the current processor.
Example 10-11.  Pseudo Code, Checks Required Prior to Loading an Update
For each processor in the system
{
Determine the Processor Signature via CPUID function 1;Determine the Platform Bits ← 1 << IA32_PLATFORM_ID[52:50];
For (I ← UpdateBlock 0, I < NumOfBlocks; I++)
{
If (Update.Header_Version = 00000001H)
{Vol. 3A 10-39PROCESSOR MANAGEMENT AND INITIALIZATION
If ((Update.ProcessorSignature = Processor Signature) &&
 (Update.ProcessorFlags & Platform Bits))
{
Load Update.UpdateData into the Processor;
Verify update was correctly loaded into the processor Go on to next processor
Break;
}Else If (Update.TotalSize > (Update.DataSize + 48))
{
N ← 0
While (N < Update.ExtendedSignatureCount)
{
If ((Update.ProcessorSignature[N] = 
 Processor Signature) &&
 (Update.ProcessorFlags[N] & Platform Bits))
{
Verify update correctly loaded into the processorGo on to next processor
Break;
}N ← N + 1
}
I ← I + (Update.TotalSize / 2048)
If ((Update.TotalSize MOD 2048) = 0)
I ← I + 1
}
}
}
}
NOTES
The platform Id bits in IA32_PLATFORM_ID are enco ded as a three-bit binary coded decimal field. 
The platform bits in the microcode update header are individually bit encoded. The algorithm must 
do a translation from one format to the other prior to doing a check.
When performing the INT 15H, 0D042H functions, the BIOS must assume that the caller has no knowledge of plat-
form specific requirements. It is the responsibility of BIOS  calls to manage all chipset and platform specific prereq-
uisites for managing the NVRAM device. When writing the update data using the Write Update sub-function, the 
BIOS must maintain implementation specific data requ irements (such as the update of NVRAM checksum). The 
BIOS should also attempt to verify the success of write op erations on the storage device used to record the update.
10.11.8.2  Responsibilities of the Calling Program
This section of the document lists the re sponsibilities of a calling program usin g the interface specifications to load 
microcode update(s) into BIOS NVRAM.
•The calling program should call the IN T 15H, 0D042H functions from a pure real mode program and should be 
executing on a system that is running in pure real mode. 
•The caller should issue the presence test function (sub function 0) and verify the signature and return codes of 
that function. 
•It is important that the calling program provides the re quired scratch RAM buffers for the BIOS and the proper 
stack size as specified in the interface definition.
•The calling program should read any update data that al ready exists in the BIOS in order to make decisions 
about the appropriateness of loading the update. The BIOS  must refuse to overwrite a newer update with an 10-40 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
older version. The update header contains informatio n about version and processor specifics for the calling 
program to make an intelligent decision about loading.
•There can be no ambiguous updates. The BIOS must refuse  to allow multiple updates for the same CPU to exist 
at the same time; it also must refuse to load updates for processors that don’t exist on the system.
•The calling application should implement a verify function that is run after the update write function success-
fully completes. This function reads back the update and verifies that the BIOS returned an image identical to 
the one that was written. 
Example 10-12 represents a calling program.
Example 10-12.  INT 15 DO42 Calling Program Pseudo-code
//
// We must be in real mode//
If the system is not in Real mode exit
//
// Detect presence of Genuine Intel processor(s) that can be updated 
// using(CPUID)//
If no Intel processors exist that can be updated exit
//// Detect the presence of the Intel microcode update extensions
//
If the BIOS fails the PresenceTestexit//
// If the APIC is enabled, see if any other processors are out there
//Read IA32_APICBASE
If APIC enabled
{
Send Broadcast Message to all processors except self via APIC
Have all processors execute CPUID, record the Processor Signature 
(i.e.,Extended Family, Extended Model, Type, Family, Model, Stepping)Have all processors read IA32_PLATFORM_ID[52:50], record Platform
 Id Bits
If current processor cannot be updated
exit
}//
// Determine the number of unique update blocks needed for this system
//NumBlocks = 0
For each processor
{
If ((this is a unique processor stepping) AND
(we have a unique update in the database for this processor))
{
Checksum the update from the database;
If Checksum fails
exit
NumBlocks ← NumBlocks + size of microcode update / 2048
}
}
//
// Do we have enough update slots for all CPUs?//Vol. 3A 10-41PROCESSOR MANAGEMENT AND INITIALIZATION
If there are more blocks required to support the unique processor steppings than update blocks 
provided by the BIOS exit//
// Do we need any update blocks at all?  If not, we are done
//If (NumBlocks = 0)
exit
//// Record updates for processors in NVRAM.
//
For (I=0; I<NumBlocks; I++){
//
// Load each Update//
Issue the WriteUpdate function
If (STORAGE_FULL) returned
{
Display Error -- BIOS is not managing NVRAM appropriately
exit
}
If (INVALID_REVISION) returned
{

Id Bits
exit
}//
{
{
exit
}
}
//
exit
//
//
{
exit
}
{
Display Message: More recent update already loaded in NVRAM for
 this stepping
continue
}
If any other error returned
{
Display Diagnostic
exit
}
//
// Verify the update was loaded correctly
//
Issue the ReadUpdate function
If an error occurred
{
exit
}//
// Compare the Update read to that written
//If (Update read ≠ Update written)
{
Display Diagnosticexit
}
I ← I + (size of microcode update / 2048)
}
//// Enable Update Loading, and inform user10-42 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
//
Issue the Update Control function with Task = Enable.
10.11.8.3  Microcode Update Functions
Table 10-13 defines the processor microcode update fu nctions that implementations of INT 15H 0D042H must 
support.
10.11.8.4  INT 15H-based Interface
If an OEM-BIOS is implementing INT 15H 0D042H interface and offer to its client, the BI OS should allow additional 
microcode updates to be added to system flash.
The program that calls this interface is responsible for providing three 64-kilobyte RAM areas for BIOS use during 
calls to the read and write functions. These RAM scratch pa ds can be used by the BIOS for any purpose, but only 
for the duration of the function call. The calling routine pl aces real mode segments pointing to the RAM blocks in 
the CX, DX, and SI registers. Calls to functions in this in terface must be made with a minimum of 32 kilobytes of 
stack available to the BIOS.
In general, each function returns with CF cleared and AH  contains the returned status. The general return codes 
and other constant definitions are liste d in Section 10.11.8.9, “Return Codes.”
The OEM error field (AL) is provided for the OEM to return additional error information specific to the platform. If 
the BIOS provides no additional information about the e rror, OEM error must be set to SUCCESS. The OEM error 
field is undefined if AH contains either SUCCESS (00H) or  NOT_IMPLEMENTED (86H). In all other cases, it must be 
set with either SUCCESS or a value meaningful to the OEM.
The following sections describe functions provided by the INT15H-based interface.
10.11.8.5  Function 00H—Presence Test
This function verifies that the BIOS has implemented required microcode update functions. Table 10-14 lists the 
parameters and return codes for the function.Table 10-13.  Microcode Update Functions 
Microcode Update Function Function 
NumberDescription Required/Optional
Presence test 00H Returns in formation about the suppo rted functions. Required
Write update data 01H Writes one of the update data areas (slots). RequiredUpdate control 02H Globally controls the loading of updates. RequiredRead update data 03H Reads one of the update data areas (slots). Required
Table 10-14.  Parameters  for the Presence Test 
Input
AX Function Code 0D042HBL Sub-function 00H - Presence test
Output
CF Carry Flag Carry Set - Failure - AH contains status
Carry Clear - All return values valid
AH Return Code  AL OEM Error Additional OEM information.
EBX Signature Part 1 'INTE' - Part one of the signature 
ECX Signature Part 2 'LPEP'- Part two of the signature
EDX Loader Version Version number of the microcode update loaderVol. 3A 10-43PROCESSOR MANAGEMENT AND INITIALIZATION
In order to assure that the BIOS function is present, the caller must verify the carry flag, the return code, and the 
64-bit signature. The update count reflects the number of  2048-byte blocks available for storage within one non-
volatile RAM.
The loader version number refers to the revision of the upda te loader program that is included in the system BIOS 
image.
10.11.8.6  Function 01H—Write Microcode Update Data
This function integrates a new microcode update into th e BIOS storage device. Table 10-15 lists the parameters 
and return codes for the function.SI Update Count Number of 2048 update blocks  in NVRAM the BIOS allocated to storing 
microcode updates 
Return Codes (see Table 10-19 for code definitionsSUCCESS The function completed successfully.
NOT_IMPLEMENTED The function is not implemented. 
Table 10-15.  Parameters for the Write Update Data Function
Input
AX Function Code 0D042H
BL Sub-function 01H - Write update
ES:DI Update Address Real Mode poin ter to the Intel Update structure.  This buffer is 2048 bytes in 
length if the processor supports only  fixed-size microcode update or...
Real Mode pointer to  the Intel Update structure. This buffer is 64 KBytes in 
length if the processo r supports a variable-size microcode update.
CX Scratch Pad1 Real mode segment ad dress of 64 KBytes of RAM block
DX Scratch Pad2 Real mode segment ad dress of 64 KBytes of RAM block
SI Scratch Pad3 Real mode segment ad dress of 64 KBytes of RAM block
SS:SP Stack pointer 32 KBytes of stack minimumOutput
CF Carry Flag Carry Set - Failure - AH Contains status
AH Return Code Status of the call
AL OEM Error Additional OEM informationReturn Codes (see Table 10-19 for code definitions
SUCCESS The function co mpleted successfully.
NOT_IMPLEMENTED The functi on is not implemented. 
WRITE_FAILURE A failure occurred because of the inability to write the storage device.
ERASE_FAILURE A failure occurred because of the inability to erase the storage device.
READ_FAILURE A failure occurred because of the inability to read the storage device.Table 10-14.  Parame ters for the Presence Test  (Contd.)
Input10-44 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
The BIOS is responsible for selecting an appropriate upda te block in the non-volatile storage for storing the new 
update. This BIOS is also responsible for ensuring the inte grity of the information provided by the caller, including 
authenticating the proposed update before incorporating it into storage.
Before writing the update block into NVRAM, the BIOS shou ld ensure that the update structure meets the following 
criteria in the following order:
1. The update header version should be equal to an  update header version recognized by the BIOS.
2. The update loader version in the update header should be equal to the update loader version contained within 
the BIOS image.
3. The update block must checksum. This checksum is computed as a 32-bit summation of all double words in the 
structure, including the header, data, and processor signature table.
The BIOS selects update block(s) in non-volatile storage for storing the candidate update. The BIOS can select any 
available update block as long as it guarantees that only a single update exists for any given processor stepping in 
non-volatile storage. If the update block selected already contains an update, the following additional criteria apply 
to overwrite it:
•The processor signature in the proposed update must be equal to the processor signature in the header of the 
current update in NVRAM (Processor Signature + platform ID bits).
•The update revision in the proposed update should be greater than the update revision in the header of the 
current update in NVRAM.
If no unused update blocks are available and the above criteria are not met, the BIOS can overwrite update 
block(s) for a processor stepping that is no longer presen t in the system. This can be done by scanning the update 
blocks and comparing the processor steppings, identified in  the MP Specification table, to the processor steppings 
that currently exist in the system.
Finally, before storing the proposed update in NVRAM, the BIOS must verify the authenticity of the update via the 
mechanism described in Section 10.11.6, “Microcode Update  Loader.” This includes loading the update into the 
current processor, executing the CPUID instruction, read ing MSR 08Bh, and comparing a calculated value with the 
update revision in the proposed update header for equality.
When performing the write update func tion, the BIOS must record the entire update, including the header, the 
update data, and the extended processor signature table (if applicable). When writing an update, the original 
contents may be overwritten, assuming the above criteria have been met. It is the responsibility of the BIOS to 
ensure that more recent updates are not overwritten thro ugh the use of this BIOS call, and that only a single 
update exists within the NVRAM for any processor stepping and platform ID.
Figure 10-8 and Figure 10-9 show the process the BIOS follo ws to choose an update block and ensure the integrity 
of the data when it stores the new microcode update. STORAGE_FULL The BIOS non-volatile storage area is unable to accommodate the update 
because all available update blocks are filled with updates th at are needed for 
processors in the system.
CPU_NOT_PRESENT The processor stepping does not currently exist in the system.
INVALID_HEADER The update header contains a header or loader version that is not recognized by 
the BIOS.
INVALID_HEADER_CS The update does not checksum correctly.SECURITY_FAILURE The processor rejected the update.

the BIOS.
INVALID_REVISION The same or more recent revision  of the update exists in the storage device. Table 10-15.  Parameters for the Write Update Data Function (Contd.)
InputVol. 3A 10-45PROCESSOR MANAGEMENT AND INITIALIZATION
Figure 10-8.  Microcode Upda te Write Operation Flow [1] 
1 Valid Update 
Header Version? 
Loader Revision Match 
BIOS’s Loader?  Does Update Match A 
CPU in The System Write Microcode Update  
Does Update 
Checksum Correctly? Yes 
Yes 
Yes No Retur n 
CPU_NOT_PRESENT  
No Retur n 
INVALID _HE ADER  
No Retur n 
No Retur n 
IN VALID _HE ADER_C S  10-46 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
10.11.8.7  Function 02H—Microcode Update Control
This function enables loading of binary updates into th e processor. Table 10-16 lists the parameters and return 
codes for the function.Figure 10-9.  Microcode Upda te Write Operation Flow [2] 
Return  
INVALID_REVISION  
Yes 1 
Update Revision Newer  
Than NVRAM Update?  
Update Pass  
Authenticity Test?  Return  
SECURITY_FAILURE  
Yes 
Update NMRAM Record  
Return  
SUCCESS  Update Matching CPU  
Already In NVRAM?  Space Available in  
NVRAM?  
Yes No 
Return  
STORAGE_FULL  Replacement   
policy implemented?  
No No 
No Yes Yes Vol. 3A 10-47PROCESSOR MANAGEMENT AND INITIALIZATION
This control is provided on a global basis for all updates and processors. The caller can determine the current status 
of update loading (enabled or disabled) without changing the state. The function does not allow the caller to disable 
loading of binary updates, as this poses a security risk.
The caller specifies the requested operation by placing one of the values from Table 10-17 in the BH register. After 
successfully completing this function, the BL register contai ns either the enable or the disable designator. Note that 
if the function fails, the update status return value is undefined.
The READ_FAILURE error code returned by  this function has meaning only if th e control function is implemented in 
the BIOS NVRAM. The state of this feature (enabled/disabled) can also be implemented using CMOS RAM bits 
where READ failure errors cannot occur. 
10.11.8.8  Function 03H—Read Microcode Update Data
This function reads a currently installed microcode update from the BIOS storage into a caller-provided RAM buffer. 
Table 10-18 lists the parameters and return codes. Table 10-16.  Parameters for the Control Update Sub-function
Input
BL Sub-function 02H - Control update
BH Task See the description below.CX Scratch Pad1 Real mode segmen t of 64 KBytes of RAM block
DX Scratch Pad2 Real mode segmen t of 64 KBytes of RAM block
SI Scratch Pad3 Real mode segmen t of 64 KBytes of RAM block
SS:SP Stack pointer 32 kilobytes of stack minimum
Output
Carry Clear - All return values valid.
AH Return Code Status of the callAL OEM Error Additiona l OEM Information. 
BL Update Status Either enab le or disable indicator
Return Codes (see Table 10-19 for code definitions)
SUCCESS Function completed successfully.READ_FAILURE A failure occurred because of the inability to read the storage device. 
Table 10-17.  Mnemonic Values
Mnemonic Value Meaning
Enable 1 Enable the Update load ing at initialization time.
Query 2 Determine the current state of the up date control without changing its status.
Table 10-18.  Parameters for the Re ad Microcode Update Data Function
Input
AX Function Code 0D042HBL Sub-function 03H - Read UpdateES:DI Buffer Address Real Mode pointer to the Intel Update structure that 
will be written with the binary data10-48 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATION
The read function enables the caller to read any microcod e update data that already exists in a BIOS and make 
decisions about the addition of new updates.  As a result of a successful call, the BIOS copies the microcode update 
into the location pointed to by ES:DI, with the contents of  all Update block(s) that are used to store the specified 
If the specified block is not a header block, but does cont ain valid data from a microcode update that spans multiple 
update blocks, then the BIOS must return Fa ilure with the NOT_EMPTY error code in AH.
An update block is considered unused and available for storing a new update if its Header Version contains the 
value 0FFFFFFFFH after return from this function call.  The actual implementation of  NVRAM storage management 
is not specified here and is BIOS dependent.  As an ex ample, the actual data value used to represent an empty 
block by the BIOS may be zero, rather than 0FFFFFFFFH. Th e BIOS is responsible for translating this information 
into the header provided by this function.
10.11.8.9  Return Codes
After the call has been made, the return codes listed in Table 10-19 are available in the AH register.ECX Scratch Pad1 Real Mode Segment address of 64 KBytes of RAM 
Block (lower 16 bits)
ECX Scratch Pad2 Real Mode Segment address of 64 KBytes of RAM 
Block (upper 16 bits)
DX Scratch Pad3 Real Mode Segment address of 64 KBytes of RAM 
Block
SS:SP Stack pointer 32 KB ytes of Stack Minimum
SI Update Number This is the index nu mber of the update block to be 
read. This value is zero based and must be less than 
the update count returned from the presence test 
function.
OutputCF Carry Flag Carry Set     - Failure - AH contains StatusCarry Clear - All return values are 
valid.
AH Return Code Status of the CallAL OEM Error Additional OEM InformationReturn Codes (see Table 10-19 for code definitions)SUCCESS The function completed successfully.READ_FAILURE There was a failure beca use of the inability to read the 
storage device.
UPDATE_NUM_INVALID Update number exceeds the maximum number of 
update blocks implemented by the BIOS.
NOT_EMPTY The specified update block is a subsequent block in use 
to store a valid microcode up date that sp ans multiple 
blocks. 
The specified block is not a header block and is not 
empty. Table 10-18.  Parameters for the Read Microcode Update Data Function (Contd.)Vol. 3A 10-49PROCESSOR MANAGEMENT AND INITIALIZATION
Table 10-19.  Return Code Definitions
Return Code Value Description
SUCCESS 00H The function completed successfully.
NOT_IMPLEMENTED 86H The function is not implemented.
ERASE_FAILURE 90H A failure because of the inability to erase the storage device.
WRITE_FAILURE 91H A failure because of the inability to write the storage device.READ_FAILURE 92H A failure because of the inability to read the storage device.
STORAGE_FULL 93H The BIOS non-volatile storage area is unable to accommodate the update 
because all available update blocks are filled with updates that are needed 
for processors in the system.
CPU_NOT_PRESENT 94H The processor stepping does not currently exist in the system.
INVALID_HEADER 95H The update header contains a header or loader version that is not 
recognized by the BIOS.
INVALID_HEADER_CS 96H The update does not checksum correctly.
SECURITY_FAILURE 97H The update was rejected by the processor.
INVALID_REVISION 98H The same or more recent revisi on of the update exists  in the storage device.
UPDATE_NUM_INVALID 99H The update number exceeds the maximum number of update blocks 
implemented by the BIOS.
NOT_EMPTY 9AH The specified update block is a subsequent block in use to store a valid 
microcode update that spans multiple blocks. 
The specified block is not a header block and is not empty.10-50 Vol. 3APROCESSOR MANAGEMENT  AND INITIALIZATIONVol. 3A 11-1CHAPTER 11
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The Advanced Programmable Interrupt Controller (APIC), re ferred to in the following sections as the local APIC, 
was introduced into the IA-32 processors with the Pentium processor (see Section 23.27, “Advanced Program-
mable Interrupt Controller (APIC)”) and is included in th e P6 family, Pentium 4, Intel Xeon processors, and other 
more recent Intel 64 and IA-32 processor families (see Section 11.4.2, “Presence of the Local APIC”). The local 
APIC performs two primary functions for the processor:
•It receives interrupts from the processor’s interrupt pins , from internal sources and from an external I/O APIC 
(or other external interrupt controller). It se nds these to the processor core for handling.
•In multiple processor (MP) systems, it sends and rece ives interprocessor interrupt (IPI) messages to and from 
other logical processors on the system bus. IPI messa ges can be used to distribute interrupts among the 
processors in the system or to execute system wide functions (such as, booting up processors or distributing work among a group of processors).
The external I/O APIC  is part of Intel’s system chipset. Its primary function is to receive external interrupt events 
from the system and its associated I/O devices and relay them to the local APIC as interrupt messages. In MP 
systems, the I/O APIC also provides a mechanism for distributing external inte rrupts to the local APICs of selected

systems, the I/O APIC also provides a mechanism for distributing external inte rrupts to the local APICs of selected 
processors or groups of processors on the system bus. 
This chapter provides a description of the local APIC and it s programming interface. It also provides an overview of 
the interface between the local APIC and the I/O APIC. Co ntact Intel for detailed information about the I/O APIC.
When a local APIC has sent an interrupt to its processor core for handling, the processor uses the interrupt and 
exception handling mechanism described in Chapter 6, “Int errupt and Exception Handling.” See Section 6.1, “Inter-
rupt and Exception Overview,” for an introd uction to interrupt and exception handling.
11.1 LOCAL AND I/O APIC OVERVIEW
Each local APIC consists of a set of APIC registers (s ee Table 11-1) and associated hardware that control the 
delivery of interrupts to the processor core and the gene ration of IPI messages. The APIC registers are memory 
mapped and can be read and written to using the MOV instruction.
Local APICs can receive interrupts from the following sources:
•Locally connected I/O devices — These interrupts originate as an edge or level asserted by an I/O device 
that is connected directly to the processor’s local interrupt pins (LINT0 and LINT1). The I/O devices may also be connected to an 8259-type interrupt controller that is  in turn connected to the processor through one of the 
local interrupt pins.
•Externally connected I/O devices — These interrupts originate as an edge or level asserted by an I/O 
device that is connected to the interrupt input pins of an I/O APIC. Interrupts are sent as I/O interrupt 
messages from the I/O APIC to one or more of the processors in the system.
•Inter-processor interrupts (IPIs) — An Intel 64 or IA-32 processor can use the IPI mechanism to interrupt 
another processor or group of processors on the system bus. IPIs are used for software self-interrupts, 
interrupt forwarding, or preemptive scheduling.
•APIC timer generated interrupts — The local APIC timer can be programme d to send a local interrupt to its 
associated processor when a programmed count is reached (see Section 11.5.4, “APIC Timer”).
•Performance monitoring counter interrupts — P6 family, Pentium 4, and Intel Xeon processors provide the 
ability to send an interrupt to its associated processor when a performance-monitoring counter overflows (see 
Section 20.6.3.5.8, “Generating an Interrupt on Overflow”).
•Thermal Sensor interrupts — Pentium 4 and Intel Xeon processors provide the ability to send an interrupt to 
themselves when the internal thermal sensor has be en tripped (see Section 15.8.2, “Thermal Monitor”).
•APIC internal er ror interrupts — When an error condition is recognized within the local APIC (such as an 
attempt to access an unimplemented register), the APIC  can be programmed to send an interrupt to its 
associated processor (see Section 11.5.3, “Error Handling”).11-2 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Of these interrupt sources: the processor’s LINT0 and LI NT1 pins, the APIC timer, the performance-monitoring 
counters, the thermal sensor, and the internal  APIC error detector are referred to as local interrupt sources . 
Upon receiving a signal from a local interrupt source, the local APIC delivers the interrupt to the processor core 
using an interrupt delivery protocol that has been se t up through a group of APIC registers called the local vector 
table  or LVT (see Section 11.5.1, “Local Vector Table”). A separa te entry is provided in the local vector table for 
each local interrupt source, which allows a specific interr upt delivery protocol to be set up for each source. For 
example, if the LINT1 pin is going to be used as an NMI pi n, the LINT1 entry in the local vector table can be set up 
to deliver an interrupt with vector number  2 (NMI interrupt) to the processor core.
The local APIC handles interrupts from the other two interrupt sources (externally connected I/O devices and IPIs) 
through its IPI message handling facilities. 
A processor can generate IPIs by programming the interrupt command register (ICR) in its local APIC (see Section 
11.6.1, “Interrupt Command Register (ICR)”). The act of wr iting to the ICR causes an IPI message to be generated 
and issued on the system bus (for Pentium 4 and Intel Xe on processors) or on the APIC bus (for Pentium and P6 
family processors). See Section 11.2, “System Bus Vs. APIC Bus.”
IPIs can be sent to other processors in the system or to  the originating processor (self-interrupts). When the target 
processor receives an IPI message, its local APIC handle s the message automatically (using information included 
in the message such as vector number and trigger mode ). See Section 11.6, “Issuing Interprocessor Interrupts,” 
for a detailed explanation of the local APIC’s IPI message delivery and acceptance mechanism.
The local APIC can also receive interrupts from externally connected devices through the I/O APIC (see 
Figure 11-1). The I/O APIC is responsi ble for receiving interrupts generated by system hardware and I/O devices 
and forwarding them to the local APIC as interrupt messages.
Individual pins on the I/O APIC can be programmed to gene rate a specific interrupt vector when asserted. The I/O 
APIC also has a “virtual wire mode” that allows it to communicate with a standard 8259A-style external interrupt 
controller. Note that the local APIC can be disabled (see  Section 11.4.3, “Enabling or Disabling the Local APIC”). 
This allows an associated processor core to receive interrupts directly from an 8259A interrupt controller.
Both the local APIC and the I/O APIC are designed to oper ate in MP systems (see Figures 11-2 and 11-3). Each local 
APIC handles interrupts from the I/O APIC, IPIs from proce ssors on the system bus, and self-generated interrupts. 
Interrupts can also be delivered to the individual processo rs through the local interrupt pins; however, this mecha-
nism is commonly not used in MP systems. 
Figure 11-1.  Relationship of Local APIC  and I/O APIC In Single-Processor SystemsI/O APIC External
System ChipsetSystem BusProcessor Core
Local APICPentium 4 and 
Local
Bridge
PCIIntel Xeon Processors
I/O APIC External
System Chipset3-Wire APIC BusProcessor Core
Local APICPentium and P6
Local
InterruptsFamily Processors
Interrupt
MessagesInterrupt
Messages
Interrupt
MessagesVol. 3A 11-3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The IPI mechanism is typically used in MP systems to send  fixed interrupts (interrupts for a specific vector number) 
and special-purpose interrupts to processors on the syst em bus. For example, a local APIC can use an IPI to 
forward a fixed interrupt to another processor for servicin g. Special-purpose IPIs (including NMI, INIT, SMI, and 
SIPI IPIs) allow one or more processors on the system bus to perform system-wide boot-up and control functions.
The following sections focus on the local APIC and its im plementation in the Pentium 4, Intel Xeon, and P6 family 
processors. In these sections, the terms “local APIC” and “I /O APIC” refer to local and I/O APICs used with the P6 
family processors and to local and I/O xAPICs used wi th the Pentium 4 and Intel Xeon processors (see Section 
11.3, “The Intel® 82489DX External APIC , the APIC, the xAPIC, and the X2APIC”). 
11.2 SYSTEM BUS VS. APIC BUS
For the P6 family and Pentium processors, the I/O APIC and local APICs communicate through the 3-wire inter-
APIC bus (see Figure 11-3). Local APICs also use the AP IC bus to send and receive IPIs. The APIC bus and its 
messages are invisible to software and are not classed as architectural. 
Figure 11-2.  Local APICs and I/O APIC When Intel Xe on Processors Are Used in  Multiple-Processor Systems
 
Figure 11-3.  Local APICs and I/O APIC When P6 Family  Processors Are Used in Multiple-Processor SystemsI/O APIC External
System ChipsetProcessor System BusCPU
Local APICProcessor #2
CPU
Local APICProcessor #3
CPU
Local APICProcessor #1
CPU
Bridge
PCIIPIs IPIs IPIs
Interrupt
MessagesIPIsInterrupt
Messages
CPU
CPU
CPU
Interrupt
Messages
I/O APICExternal
System Chipset3-wire APIC Bus CPU
Local APICProcessor #4
IPIs IPIs IPIs IPIs Interrupt
Messages
Interrupt
Messages11-4 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Beginning with the Pentium 4 and Intel Xeon processors, the I/O APIC and local APICs (using the xAPIC architec-
ture) communicate through the system bus (see Figure 11- 2). The I/O APIC sends interrupt requests to the 
processors on the system bus through bridge hardware that is part of the Intel chipset.  The bridge hardware gener-
ates the interrupt messages that go to the local APICs. IPIs between local APICs are transmitted directly on the 
system bus.
11.3 THE INTEL® 82489DX EXTERNAL APIC, THE APIC, THE XAPIC, AND THE 
X2APIC

Bridge
Interrupt
Messages
CPU
CPU
CPU
Interrupt
Messages
Messages
Interrupt
X2APIC
The local APIC in the P6 family and Pentium proc essors is an architectural subset of the Intel® 82489DX external 
APIC. See Section 23.27.1, “Software Visible Diff erences Between the Local APIC and the 82489DX.”
The APIC architecture used in the Pentium 4 and Intel Xeon  processors (called the xAPIC architecture) is an exten-
sion of the APIC architecture found in the P6 family processors. The pr imary difference between the APIC and 
xAPIC architectures is that with the xAPIC architecture, the local APICs and the I/O APIC communicate through the 
system bus. With the APIC architecture, they communica tion through the APIC bus (see Section 11.2, “System Bus 
Vs. APIC Bus”). Also, some APIC architectural features ha ve been extended and/or modified in the xAPIC architec-
ture. These extensions and modifications are de scribed in Section 11.4 through Section 11.10.
The basic operating mode of the xAPIC is xAPIC mode . The x2APIC architecture is an extension of the xAPIC 
architecture, primarily to increase processor addressabilit y. The x2APIC architecture provides backward compati-
bility to the xAPIC architecture and forward extendability for future Intel platform innovations. These extensions 
and modifications are supported by a new mode of execution ( x2APIC mode ) are detailed in Section 11.12.
11.4 LOCAL APIC
The following sections describe the architecture of the loca l APIC and how to detect it, identify it, and determine its 
status. Descriptions of how to program the local APIC are given in Section 11.5.1, “Local Vector Table,” and Section 
11.6.1, “Interrupt Command Register (ICR).”
11.4.1 The Local APIC Block Diagram
Figure 11-4 gives a functional block diagram for the local AP IC. Software interacts with the local APIC by reading 
and writing its registers. APIC registers are memory-ma pped to a 4-KByte region of the processor’s physical 
address space with an initial starting address of FEE00 000H. For correct APIC operation, this address space must 
be mapped to an area of memory that has been desi gnated as strong uncacheable (UC). See Section 12.3, 
“Methods of Caching Available.”
In MP system configurations, the APIC registers for Inte l 64 or IA-32 processors on the system bus are initially 
mapped to the same 4-KByte region of the physical addre ss space. Software has the option of changing initial 
mapping to a different 4-KByte region for all the local APICs or of mapping the APIC registers for each local APIC to 
its own 4-KByte region. Section 11.4.5, “Relocating the Loca l APIC Registers,” describes how to relocate the base 
address for APIC registers.
On processors supporting x2APIC architecture (indicat ed by CPUID.01H:ECX[21] = 1), the local APIC supports 
operation both in xAPIC mode and (if enabled by software) in x2APIC mode. x2APIC mode provides extended 
processor addressability (see Section 11.12).
NOTE
For P6 family, Pentium 4, and Intel Xeon processors, the APIC handles all memory accesses to addresses within the 4-KByte APIC register spac e internally and no external bus cycles are 
produced. For the Pentium processors with an on-chip APIC, bus cycles are produced for accesses 
to the APIC register space. Thus, for software intended to run on Pentium processors, system 
software should explicitly not map the APIC regist er space to regular system memory. Doing so can 
result in an invalid opcode exception (#UD ) being generated or unpredictable execution.Vol. 3A 11-5ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 11-1 shows how the APIC registers are mapped into the 4-KByte APIC register space. Registers are 32 bits, 
64 bits, or 256 bits in width; all are aligned on 128-bit boundaries. All 32-bit registers should be accessed using 
128-bit aligned 32-bit loads or stores. Some processors may support loads and stores of less than 32 bits to some of the APIC registers. This is model specific behavior  and is not guaranteed to work on all processors. Any 
FP/MMX/SSE access to an APIC register, or any access th at touches bytes 4 through 15 of an APIC register may 
cause undefined behavior and must not be executed. This undefined behavior could include hangs, incorrect results 
or unexpected exceptions, including machine checks, an d may vary between implementations. Wider registers 
(64-bit or 256-bit) must be accessed using multiple 32-bit loads or stores, with all accesses being 128-bit aligned. 
The local APIC registers listed in Table 11-1 are not MSRs . The only MSR associated with the programming of the 
local APIC is the IA32_APIC_BASE MSR (see Section 11.4.3, “Enabling or Disabling the Local APIC”).
NOTE
In processors based on Nehalem1 microarchitecture, the Local APIC ID Register is no longer 
Read/Write; it is Read Only.Figure 11-4.  Local APIC StructureVersion Register
Timer
Current Count 
Register
Initial Count 
Register
Divide Configuration
Register
Local Vector Table
Thermal Sensor2
Error
RegisterLINT0/1
Perf. Mon.
(InternalInterrupt)
Thermal
Sensor(InternalInterrupt)EOI Register
Task Priority Register
Processor Priority
Register
PrioritizerINTR
EXTINTTo 
CPUCoreFrom 
CPU
CoreINTA
Timer
Local 
Interrupts 0,1
Monitoring Counters1/ 
Intel Processor TraceIn-Service Register (ISR)
Interrupt Request Register (IRR)
Trigger Mode Register (TMR)
Arb. ID
Register4Vecter
Decode
Acceptance
LogicVec[3:0]
& TMR BitRegister
Select
Protocol
Translation LogicDest. Mode
& VectorLocal 
To CPUCore
INIT
NMISMI
Interrupt Command
Register (ICR)
Processor System Bus3APIC ID
Register
Logical Destination 
Register
Destination Format
Register
Spurious Vector Register
1. Introduced in P6 family processors.
2. Introduced in the Pentium 4 and Intel Xeon processors.3. Three-wire APIC bus in P6 family and Pentium processors.
4. Not implemented in Pentium 4 and Intel Xeon processors.11-6 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
1. See Table 2-1, “CPUID Signature Values of DisplayFamily_DisplayM odel,” on page 1, and Section 2.8, “MSRs In Processors Based on  
Nehalem Microarchitect ure,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, to determine which 
processors are based on Nehalem microarchitecture.Table 11-1. Local APIC Register Address Map 
Address Register Name Software Read/Write
FEE0 0000H Reserved
FEE0 0010H Reserved
FEE0 0020H Local APIC ID Register Read/Write.FEE0 0030H Local APIC Version Register Read Only.
FEE0 0040H Reserved
FEE0 0050H ReservedFEE0 0060H Reserved
FEE0 0070H Reserved
FEE0 0080H Task Priority Register (TPR) Read/Write.FEE0 0090H Arbitration Priority Register
1 (APR) Read Only.
FEE0 00A0H Processor Priority  Register (PPR) Read Only.
FEE0 00B0H EOI Register Write Only.
FEE0 00C0H Remote Read Register1 (RRD) Read Only
FEE0 00D0H Logical Destination Register Read/Write.
FEE0 00E0H Destination Format Register Read/Write (see Section 
11.6.2.2).
FEE0 00F0H Spurious Interrupt Vector Register Read/Write (see Section 11.9.
FEE0 0100H In-Service Register (ISR); bits 31:0 Read Only.FEE0 0110H In-Service Register (ISR); bits 63:32 Read Only.
FEE0 0120H In-Service Register (ISR); bits 95:64 Read Only.
FEE0 0130H In-Service Register (ISR); bits 127:96 Read Only.FEE0 0140H In-Service Register (ISR); bits 159:128 Read Only.
FEE0 0150H In-Service Register (ISR); bits 191:160 Read Only.
FEE0 0160H In-Service Register (ISR); bits 223:192 Read Only.FEE0 0170H In-Service Register (ISR); bits 255:224 Read Only.
FEE0 0180H Trigger Mode Register (TMR); bits 31:0 Read Only.
FEE0 0190H Trigger Mode Register (TMR); bits 63:32 Read Only.FEE0 01A0H Trigger Mode Register (TMR); bits 95:64 Read Only.
FEE0 01B0H Trigger Mode Register  (TMR); bits 127:96 Read Only.
FEE0 01C0H Trigger Mode Register (TMR); bits 159:128  Read Only.
FEE0 01D0H Trigger Mode Register (TMR); bits 191:160 Read Only.
FEE0 01E0H Trigger Mode Register (TMR); bits 223:192 Read Only.
FEE0 01F0H Trigger Mode Register (TMR); bits 255:224 Read Only.FEE0 0200H Interrupt Re quest Register (IRR); bits 31:0 Read Only.
FEE0 0210H Interrupt Requ est Register (IRR); bits 63:32 Read Only.
FEE0 0220H Interrupt Requ est Register (IRR); bits 95:64 Read Only.Vol. 3A 11-7ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.4.2 Presence of the Local APIC
Beginning with the P6 family processors, the presence or absence of an on-chip local APIC can be detected using 
the CPUID instruction. When the CPUID instruction is execut ed with a source operand of 1 in the EAX register, bit 9 
of the CPUID feature flags returned in the EDX register in dicates the presence (set) or absence (clear) of a local 
APIC.
11.4.3 Enabling or Disabling the Local APIC
The local APIC can be enabled or disabled in either of two ways:
1. Using the APIC global enable/disable flag in the IA32_APIC_BASE MSR (MSR address 1BH; see Figure 11-5):FEE0 0230H Interrupt Request Register (IRR); bits 127:96 Read Only.
FEE0 0240H Interrupt Request Register (IRR); bits 159:128 Read Only.

APIC.
FEE0 0250H Interrupt Request Register (IRR); bits 191:160 Read Only.
FEE0 0260H Interrupt Request Register (IRR); bits 223:192 Read Only.FEE0 0270H Interrupt Request Register (IRR); bits 255:224 Read Only.
FEE0 0280H Error Status Register Write/Read; see Section 
11.5.3.
FEE0 0290H through
FEE0 02E0HReserved
FEE0 02F0H LVT Corrected Machine Check Interrupt (CMCI) Register Read/Write.
FEE0 0300H Interrupt Command Register (ICR); bits 0-31 Read/Write.FEE0 0310H Interrupt Command Register (ICR); bits 32-63 Read/Write.FEE0 0320H LVT Timer Register Read/Write.
FEE0 0330H LVT Thermal Sensor Register
2Read/Write.
FEE0 0340H LVT Performance Moni toring Counte rs Register3Read/Write.
FEE0 0350H LVT LINT0 Register Read/Write.
FEE0 0360H LVT LINT1 Register Read/Write.
FEE0 0370H LVT Error Register Read/Write.FEE0 0380H Initial Count Register (for Timer) Read/Write.
FEE0 0390H Current Count Register (for Timer) Read Only.
FEE0 03A0H through 
FEE0 03D0HReserved
FEE0 03E0H Divide Configuration Register (for Timer) Read/Write.
FEE0 03F0H Reserved
NOTES:
1. Not supported in the Pentium 4 and Intel Xeon processors. The Illegal Register Access bit (7) of the ESR will not be set when  writ-
ing to these registers.
2. Introduced in the Pentium 4 and Intel Xeon processors. This AP IC register and its associated function are implementation depe n-
dent and may not be present in future IA-32 or Intel 64 processors.
3. Introduced in the Pentium Pro processor. This APIC register and its associated function are implementation dependent and may not 
be present in future IA-3 2 or Intel 64 processors.Table 11-1. Local APIC Regi ster Address Map  (Contd.)
Address Register Name Software Read/Write11-8 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
— When IA32_APIC_BASE[11] is 0, the processor is functi onally equivalent to an IA-32 processor without an 
on-chip APIC. The CPUID feature flag for the APIC (see Se ction 11.4.2, “Presence of the Local APIC”) is also 
set to 0.
— When IA32_APIC_BASE[11] is set to 0, processor APIC s based on the 3-wire APIC bus cannot be generally 
re-enabled until a system hardware reset. The 3-wire bus loses track of arbitration that would be necessary 
for complete re-enabling. Certain APIC functiona lity can be enabled (for example: performance and 
thermal monitoring interrupt generation).
— For processors that use Front Side Bus (FSB) delivery of interrupts, software may disable or enable the 
APIC by setting and resetting IA3 2_APIC_BASE[11]. A hardware reset is  not required to re-start APIC 
functionality, if software guarantees no interrupt wi ll be sent to the APIC as IA32_APIC_BASE[11] is 
cleared.
— When IA32_APIC_BASE[11] is set to 0, prior initializati on to the APIC may be lost and the APIC may return 
to the state described in Section 11.4.7.1, “Local APIC State After Power-Up or Reset.”
2. Using the APIC software enable/dis able flag in the spurious-interrupt vector register (see Figure 11-23):
— If IA32_APIC_BASE[11] is 1, software can temporarily disable a local APIC at any time by clearing the APIC 
software enable/disable flag in the spurious-interrupt  vector register (see Figure 11-23). The state of the 
local APIC when in this software-disabled state is descr ibed in Section 11.4.7.2, “Local APIC State After It 
Has Been Software Disabled.” 
— When the local APIC is in the software-disabled state, it can be re-enabled at any time by setting the APIC 
software enable/disable flag to 1.
For the Pentium processor, the APICEN pin (which is shared  with the PICD1 pin) is used during power-up or reset 
to disable the local APIC.
Note that each entry in the LVT has a mask bit that can be used to inhibit interrupts from being delivered to the 
processor from selected local interrupt sources (the LINT 0 and LINT1 pins, the APIC timer, the performance-moni-
toring counters, Intel® Processor Trace, the thermal sensor, an d/or the internal APIC error detector).
11.4.4 Local APIC Status and Location
The status and location of the local APIC ar e contained in the IA32_APIC_BASE MSR (see Figure 11-5 ). MSR bit 
functions are described below:
•BSP flag, bit 8 ⎯ Indicates if the processor is the bootstrap processor (BSP). See Section 9.4, “Multiple-
Processor (MP) Initialization.” Following a power-up or rese t, this flag is set to 1 for the processor selected as 
the BSP and set to 0 for the remaining processors (APs).
•APIC Global Enable flag, bit 11 ⎯ Enables or disables the local APIC (see Section 11.4.3, “Enabling or 
Disabling the Local APIC”). This flag is available in the Pe ntium 4, Intel Xeon, and P6 family processors. It is not 
guaranteed to be available or available at the same location in future Intel 64 or IA-32 processors.
•APIC Base field, bits 12 through 35 ⎯ Specifies the base address of the APIC  registers. This 24-bit value is 
extended by 12 bits at the low end to form the base addr ess. This automatically aligns the address on a 4-KByte 
boundary. Following a power-up or rese t, the field is set to FEE0 0000H.
•Bits 0 through 7, bits 9 and 10, and bits MAXPHYADDR2 through 63 in the IA32_APIC_BASE MSR are reserved.
2. The MAXPHYADDR is 36 bits for processors that do not support CPUID leaf 80000008H, or indicated by 
CPUID.80000008H:EAX[bits 7:0] for processo rs that support CPUID leaf 80000008H.Vol. 3A 11-9ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.4.5 Relocating the Local APIC Registers
The Pentium 4, Intel Xeon, and P6 family processors permit  the starting address of the APIC registers to be relo-
cated from FEE00000H to another physical address by mo difying the value in the base address field of the 
IA32_APIC_BASE MSR. This extension of the APIC architectu re is provided to help resolve conflicts with memory 
maps of existing systems and to allo w individual processors in an MP system to map their APIC registers to 
different locations in physical memory.
11.4.6 Local APIC ID
At power up, system hardware assigns a unique APIC ID to  each local APIC on the system bus (for Pentium 4 and 
Intel Xeon processors) or on the APIC bus (for P6 family  and Pentium processors). The hardware assigned APIC ID 
is based on system topology and includes encoding for socket position and cluster information (see Figure 9-2 and 
Section 9.9.1, “Hierarchical Mapping of Shared Resources”).
In MP systems, the local APIC ID is  also used as a processor ID by the BIOS and the operating system. Some 
processors permit software to modify the APIC ID. Howeve r, the ability of software to modify the APIC ID is 
processor model specific. Because of this, operating system  software should avoid writing to the local APIC ID 
register. The value returned by bits 31-24 of the EBX re gister (when the CPUID instruction is executed with a 
source operand value of 1 in the EAX register) is always th e Initial APIC ID (determined by the platform initializa-
tion). This is true even if software has changed the value in the Local APIC ID register.
The processor receives the hardware assigned APIC ID (o r Initial APIC ID) by sampling pins A11# and A12# and 
pins BR0# through BR3# (for the Pentium 4, Intel Xeon, and P6 family processors) and pins BE0# through BE3# 
(for the Pentium processor). The APIC ID latched from these pins is stored in the APIC ID field of the local APIC ID 
register (see Figure 11-6), and is used as the Initial APIC ID for the processor. Figure 11-5.  IA32_APIC_BASE MS R (APIC_BASE_MSR in P6 Family)
Figure 11-6.  Local APIC ID RegisterBSP—Processor is BSPAPIC global enable/disableAPIC Base—Base physical address63 0 7 1011 89 12
ReservedMAXPHYADDR
APIC Base Reserved
31 27 24 0
Reserved APIC IDAddress: 0FEE0 0020H
Value after reset: 0000 0000HP6 family and Pentium processors 
Pentium 4 processors, Xeon processors, and later processors
31 24 0
Reserved APIC ID
MSR Address: 802H31     0
x2APIC IDx2APIC ModexAPIC Mode11-10 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
For the P6 family and Pentium processors, the local APIC ID field in the local APIC ID register is 4 bits. Encodings 
0H through EH can be used to uniquely identify 15 differe nt processors connected to the APIC bus. For the Pentium 
4 and Intel Xeon processors, the xAPIC specification extends the local APIC ID field to 8 bits. These can be used to 
identify up to 255 processors in the system.
11.4.7 Local APIC State
The following sections describe the state of the local APIC and its registers following a power-up or reset, after the 
local APIC has been software disabled, following an INIT reset, and following an INIT-deassert message.
x2APIC will introduce 32-bit ID; see Section 11.12.
11.4.7.1  Local APIC Stat e After Power-Up or Reset
Following a power-up or reset of the processor, the state of local APIC and its registers are as follows:
•The following registers are reset to all 0s. 
•IRR, ISR, TMR, IC R, LDR, and TPR.
•Timer initial count and timer current count registers.
•Divide configuration register.
•The DFR register is reset to all 1s.

•The LVT register is reset to 0s except for the mask bits; these are set to 1s.
•The local APIC version register is not affected.
•The local APIC ID register is set to a unique APIC ID . (Pentium and P6 family processors only). The Arb ID 
register is set to the value in the APIC ID register.
•The spurious-interrupt vector register is initialized to 000000FFH. By setting bit 8 to 0, software disables the 
local APIC.
•If the processor is the only processor in the system or it  is the BSP in an MP system (see Section 9.4.1, “BSP 
and AP Processors”); the local APIC will respond norma lly to INIT and NMI messages, to INIT# signals and to 
STPCLK# signals. If the processor is in an MP system and has been designated as an AP; the local APIC will 
respond the same as for the BSP. In addition, it will re spond to SIPI messages. For P6 family processors only, 
an AP will not respond to a STPCLK# signal.
11.4.7.2  Local APIC State After It Has Been Software Disabled 
When the APIC software enable/disable fl ag in the spurious interrupt vector register has been explicitly cleared (as 
opposed to being cleared during a power up or reset), the local APIC is temporarily disabled (see Section 11.4.3, 
“Enabling or Disabling the Local APIC”). The operation and re sponse of a local APIC while  in this software-disabled 
state is as follows:
•The local APIC will respond normally to  INIT, NMI, SMI, and SIPI messages.
•Pending interrupts in the IRR and ISR registers ar e held and require masking or handling by the CPU.
•The local APIC can still issue IPIs. It is software’s resp onsibility to avoid issuing IPIs through the IPI mechanism 
and the ICR register if sending interrupt s through this mechanism is not desired.
•The reception of any interrupt or transmission of any IPIs that are in progress when the local APIC is disabled 
are completed before the local APIC enters the software-disabled state.
•The mask bits for all the LVT entries are set. Attempts to reset these bits will be ignored.
•(For Pentium and P6 family processors) The local APIC continues to listen to all bus messages in order to keep 
its arbitration ID synchronized with the rest of the system.
11.4.7.3  Local APIC State After an  INIT Reset (“Wait-for-SIPI” State)
An INIT reset of the processor can be initiated in either of two ways:Vol. 3A 11-11ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
•By asserting the processor’s INIT# pin.
•By sending the processor an INIT IPI (an IPI with the delivery mode set to INIT).
Upon receiving an INIT through either of these mechanis ms, the processor responds by beginning the initialization 
process of the processor core and the local APIC. The state of the local APIC following an INIT reset is the same as 
it is after a power-up or hardware rese t, except that the APIC ID and arbitrat ion ID registers are not affected. This 
state is also referred to at the “wait-for-SIPI” state (see  also: Section 9.4.2, “MP Initialization Protocol Require-
ments and Restrictions”).
11.4.7.4  Local APIC State After It Receives an INIT-Deassert IPI
Only the Pentium and P6 family processo rs support the INIT-deassert IPI. An IN IT-deassert IPI has no affect on the 
state of the APIC, other than to reload the arbitration ID register with the value in the APIC ID register. 
11.4.8 Local APIC Version Register
The local APIC contains a hardwired version register. Softwa re can use this register to identify the APIC version 
(see Figure 11-7). In addition, the register specifies the nu mber of entries in the local vector table (LVT) for a 
specific implementation. 
The fields in the local APIC version register are as follows:
Version The version numbers of the local APIC:
0XH 82489DX discrete APIC.10H - 15H Integrated APIC.
Other values reserved.
Max LVT Entry Shows the number of LVT entries minus 1. For the Pentium 4 and Intel Xeon processors (which 
have 6 LVT entries), the value returned in the Max LVT field is 5; for the P6 family processors (which have 5 LVT entries), the value returned is 4; for the Pentium processor (which has 4 LVT 
entries), the value returned is 3. For processors based on the Nehalem microarchitecture 
(which has 7 LVT entries) and onward, the value returned is 6.
Suppress EOI-broadcasts
Indicates whether software can inhibit the broa dcast of EOI message by setting bit 12 of the 
Spurious Interrupt Vector Register; see Section 11.8.5 and Section 11.9.
Figure 11-7.  Local APIC Version Register31 0
Reserved78 23 15
Support for EOI-broadcast suppression16
Reserved25 24
Version Max LVT Entry
Value after reset: 0BNN 00VVH
V = Version, N = # of LVT entries minus 1,
Address: FEE0 0030HB = 1 if EOI-broadcast suppression supported11-12 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.5 HANDLING LOCAL INTERRUPTS
The following sections describe facilities that are provided  in the local APIC for handling local interrupts. These 
include: the processor’s LINT0 and LINT1 pins, the APIC  timer, the performance-monitoring counters, Intel 
Processor Trace, the thermal sensor, and the internal APIC e rror detector. Local interrupt handling facilities include: 
the LVT, the error status register (ESR), the divide conf iguration register (DCR), and the initial count and current 
count registers.
11.5.1 Local Vector Table
The local vector table (LVT) allows software to specify the manner in which the local interrupts are delivered to the 
processor core. It consists of the following 32-bit APIC registers (see Figure 11-8), one for each local interrupt:
•LVT CMCI Register (FEE0 02F0H)  — Specifies interrupt delivery when an overflow condition of corrected 
machine check error count reaching a threshold value occurred in a machine check bank supporting CMCI (see 
Section 16.5.1, “CMCI Local APIC Interface”).
•LVT Timer Regist er (FEE0 0320H)  — Specifies interrupt delivery when the APIC timer signals an interrupt 
(see Section 11.5.4, “APIC Timer”).
•LVT Thermal Monitor Register (FEE0 0330H)  — Specifies interrupt delivery when the thermal sensor 
generates an interrupt (see Section 15 .8.2, “Thermal Monitor”). This LVT entry is implementation specific, not 
architectural. If implemented, it will always be at base address FEE0 0330H.
•LVT Performance Counter Register (FEE0 0340H)  — Specifies interrupt delivery when a performance 
counter generates an interrupt on overflow (see Section 20.6.3.5.8, “Generating an Interrupt on Overflow”) or 
when Intel PT signals a ToPA PMI (see Section 33.2.7.2).  This LVT entry is implementation specific, not archi-
tectural. If implemented, it is not guaran teed to be at base address FEE0 0340H.
•LVT LINT0 Register (FEE0 0350H)  — Specifies interrupt delivery when an interrupt is signaled at the LINT0 
pin.
•LVT LINT1 Register (FEE0 0360H)  — Specifies interrupt delivery when an interrupt is signaled at the LINT1 
pin.
•LVT Error Register (FEE0 0370H)  — Specifies interrupt delivery when the APIC detects an internal error 
(see Section 11.5.3, “Error Handling”).
The LVT performance counter register and its associated interrupt were introduced in the P6 processors and are 
also present in the Pentium 4 and Intel Xeon processors. The LVT thermal monitor register and its associated inter-
rupt were introduced in the Pentium 4 and Intel Xeon pr ocessors. The LVT CMCI register and its associated inter-
rupt were introduced in the Intel Xeon 5500 processors.
As shown in Figure 11-8, some of these fields and fl ags are not available (and reserved) for some entries.Vol. 3A 11-13ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The setup information that can be specified in the registers of the LVT table is as follows:
Vector Interrupt vector number.
Delivery Mode Specifies the type of interrupt to be sent to  the processor. Some delivery modes will only 
operate as intended when used in conjunction  with a specific trigger mode. The allowable 
delivery modes are as follows:
000 (Fixed) Delivers the interrupt specified in the vector field.
010 (SMI) Delivers an SMI interrupt to the proc essor core through the processor’s lo-
cal SMI signal path. When using this delivery mode, the vector field should be set to 00H for future compatibility.Figure 11-8.  Local Vector Table (LVT)31 0 7
Vector
Timer Mode
00: One-shot
01: Periodic12 15161718
Delivery Mode
000: Fixed
100: NMIMask†
0: Not Masked
1: Masked
Address: FEE0 0350H
Value After Reset: 0001 0000HReserved1213 15 16Vector31 0 78 10
Address: FEE0 0360H
Address: FEE0 0370HVectorVector
ErrorLINT1LINT0Value after Reset: 0001 0000HAddress: FEE0 0320H
111: ExtlNT
All other combinations
are reservedInterrupt Input
Pin Polarity
Trigger Mode
0: Edge
1: LevelRemote
IRRDelivery Status
0: Idle
1: Send PendingTimer13 11 8
11
1417
Address: FEE0 0340HPerformanceVector
ThermalVectorMon. Counters
Sensor
Address: FEE0 0330H† (Pentium 4 and Intel Xeon processors.) When a 
performance monitoring counters interrupt is generated, the mask bit for its associated LVT entry is set.010: SMI
101: INIT19
10: TSC-Deadline
Vector CMCI

Vector
Timer Mode
000: Fixed
1: Masked
0: Edge
0: Idle
11
1417
Sensor
Address: FEE0 02F0H11-14 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
100 (NMI) Delivers an NMI interrupt to the processor. The vector information is ig-
nored. 
101 (INIT) Delivers an INIT request to the processor core, which causes the processor 
to perform an INIT. When using this delivery mode, the vector field should be set to 00H for future compatibility.  Not supported for the LVT CMCI reg-
ister, the LVT thermal monitor register, or the LVT performance counter 
register.
110 Reserved; not supported for any LVT register.
111 (ExtINT) Causes the processor to respond to th e interrupt as if the interrupt origi-
nated in an externally connected (8259A-compatible) interrupt controller. 
A special INTA bus cycle corresponding to ExtINT, is routed to the external controller. The external controller is expected to supply the vector informa-
tion. The APIC architecture supports only one ExtINT source in a system, 
usually contained in the compatibilit y bridge. Only one processor in the 
system should have an LVT entry configured to use the ExtINT delivery 
mode. Not supported for the LVT CMCI register, the LVT thermal monitor 
register, or the LVT performance counter register.
Delivery Status (Read Only)
Indicates the interrupt delivery status, as follows:
0 (Idle) There is currently no activity for this interrupt source, or the previous in-
terrupt from this source was delivered to the processor core and accepted.
1 (Send Pending)
Indicates that an interrupt from this source has been delivered to the pro-
cessor core but has not yet been accepted (see Section 11.5.5, “Local In-
terrupt Acceptance”).
Interrupt Input Pin Polarity
Specifies the polarity of the corresponding interru pt pin: (0) active high or (1) active low. 
Remote IRR Flag (Read Only)
For fixed mode, level-triggered interrupts; this flag is set when the local APIC accepts the 
interrupt for servicing and is reset when an EO I command is received from the processor. The 
meaning of this flag is undefined for edge-t riggered interrupts and other delivery modes. 
Trigger Mode Selects the trigger mode for the local LINT0 and LINT1 pins: (0) edge sensitive and (1) level 
sensitive. This flag is only used when the deliv ery mode is Fixed. When the delivery mode is 
NMI, SMI, or INIT, the trigger mode is always edge sensitive. When the delivery mode is 
ExtINT, the trigger mode is always level sensitive. The timer and error interrupts are always treated as edge sensitive. 
If the local APIC is not used in conjunction with an I/O APIC and fixed delivery mode is 
selected; the Pentium 4, Intel Xeon, and P6 family processors will always use level-sensitive triggering, regardless if edge-sensitive triggering is selected.
Software should always set the trigger mode in the LVT LINT1 register to 0 (edge sensitive). 
Level-sensitive interrupts are not supported for LINT1.
Mask Interrupt mask: (0) enables reception of the inte rrupt and (1) inhibits reception of the inter-
rupt. When the local APIC handles a performance-monitoring counters interrupt, it automati-
cally sets the mask flag in the LVT performance counter register. This flag is set to 1 on reset. It can be cleared only by software.
Timer Mode Bits 18:17 selects the timer mode (see Section 11.5.4): 
(00b) one-shot mode using a count-down value,(01b) periodic mode reloading a count-down value,
(10b) TSC-Deadline mode using absolute target value in IA32_TSC_DEADLINE MSR (see 
Section 11.5.4.1),
(11b) is reserved.Vol. 3A 11-15ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.5.2 Valid Interrupt Vectors
The Intel 64 and IA-32 architectures define 256 vector  numbers, ranging from 0 through 255 (see Section 6.2, 
“Exception and Interrupt Vectors”). Local and I/O APICs su pport 240 of these vectors (in the range of 16 to 255) 
as valid interrupts.
When an interrupt vector in the range of 0 to 15 is sent  or received through the local APIC, the APIC indicates an 
illegal vector in its Error Status Register (see Section 11.5.3, “Error Handling”). The Intel 64 and IA-32 architec-tures reserve vectors 16 through 31 fo r predefined interrupts, exceptions, and Intel-reserved encodings (see Table 
6-1). However, the local APIC does not treat vectors in this range as illegal.
When an illegal vector value (0
 to 15) is written to an LVT entry and the delivery mode is Fixed (bits 8-11  equal 0), 
the APIC may signal an illegal vector error, without regard to whether the mask bit is set or whether an interrupt is 
actually seen on the input.
11.5.3 Error Handling
The local APIC records errors detected during interrupt handling in the e rror status register (ESR). The format of 
the ESR is given in Figure 11-9; it contains the following flags:
•Bit 0: Send Checksum Error.
Set when the local APIC detects a checksum error for a messa ge that it sent on the APIC bus. Used only on P6 
family and Pentium processors.
•Bit 1: Receive Checksum Error.
Set when the local APIC detects a checksum error for a messa ge that it received on the APIC bus. Used only on 
P6 family and Pentium processors.
•Bit 2: Send Accept Error.
Set when the local APIC detects that a message it sent was not accepted by any APIC on the APIC bus. Used 
only on P6 family and Pentium processors.
•Bit 3: Receive Accept Error.Set when the local APIC detects that the message it received was not accepted by any APIC on the APIC bus, 
including itself. Used only on P6 family and Pentium processors.Figure 11-9.  Error St atus Register (ESR)Address: FEE0 0280H
Value after reset: 0H31 0
Reserved781 23456
Illegal Register Address1
Received Illegal Vector
Send Illegal Vector
Redirectable IPI2
Receive Accept Error3
Send Accept Error3
Receive Checksum Error3
Send Checksum Error3
2. Used only by some Intel Core and Intel Xeon processors;
reserved on other processors.1. Used only by Intel Core, Pentium 4, Intel Xeon, and P6 family
processors; reserved on the Pentium processor.NOTES:
3. Used only by the P6 family and Pentium processors;
reserved on Intel Core, Pentium 4 and Intel Xeon processors.11-16 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
•Bit 4: Redirectable IPI.
Set when the local APIC detects an attempt to send an IPI with the lowest-priority delivery mode and the local 
APIC does not support the sending of such IPIs. This bit is used on some Intel Core and Intel Xeon processors. 
As noted in Section 11.6.2, the ability of a processor to send a lowest-priority IPI is model-specific and should 
be avoided.
•Bit 5: Send Illegal Vector.Set when the local APIC detects an illegal vector (one in the range 0 to 15) in the message that it is sending. 
This occurs as the result of a write to the ICR (in both xAPIC and x2APIC modes) or to SELF IPI register (x2APIC 
mode only) with an illegal vector.
If the local APIC does not support the sending of lowest -priority IPIs and software writes the ICR to send a 
lowest-priority IPI with an illegal vector, the local APIC se ts only the “redirectable IPI” error bit. The interrupt is 
not processed and hence the “Send Illegal Vector” bit is not set in the ESR.
•Bit 6: Receive Illegal Vector.
Set when the local APIC detects an illegal vector (one in  the range 0 to 15) in an interrupt message it receives 
or in an interrupt generated locally from the local vector table or via a self IPI. Such interrupts are not delivered 
to the processor; the local APIC will never set an IRR bit in the range 0 to 15.
•Bit 7: Illegal Register Address
Set when the local APIC is in xAPIC mode and software attempts to access a register that is reserved in the 
processor's local-APIC register-address space; see Table 10-1. (The local-APIC register-address space 
comprises the 4 KBytes at the physical address specif ied in the IA32_APIC_BASE MSR.) Used only on Intel 
Core, Intel Atom, Pentium 4, Intel Xeon, and P6 family processors.
In x2APIC mode, software accesses the APIC register s using the RDMSR and WRMSR instructions. Use of one 
of these instructions to access a reserved register cause a general-protection exception (see Section 
10.12.1.3). They do not set the “Illegal Register Access” bit in the ESR.
The ESR is a write/read register. Before attempt to read fr om the ESR, software should first write to it. (The value 
written does not affect the values read subsequently; only zero may be written in x2APIC mode.) This write clears 
any previously logged errors and updates the ESR with any errors detected since the last write to the ESR. This 
write also rearms the APIC error interrupt triggering mechanism.
The LVT Error Register (see Section 11.5.1) allows specificat ion of the vector of the interrupt to be delivered to the 
processor core when APIC error is detected. The register also provides a means of masking an APIC-error interrupt. 
This masking only prevents delivery of APIC-error interru pts; the APIC continues to record errors in the ESR.
11.5.4 APIC Timer
The local APIC unit contains a 32-bit programmable timer that is available to software to time events or operations.

The local APIC unit contains a 32-bit programmable timer that is available to software to time events or operations. 
This timer is set up by programming four registers: the di vide configuration register (see Figure 11-10), the initial-
count and current-count registers (see Figure 11-11 ), and the LVT timer register (see Figure 11-8). 
If CPUID.06H:EAX.ARAT[bit 2] = 1, the pr ocessor’s APIC timer runs at a constant rate regardless of P-state transi-
tions and it continues to run at the same rate in deep C-states.
If CPUID.06H:EAX.ARAT[bit 2] = 0 or if  CPUID 06H is not supporte d, the APIC timer may temporarily stop while the 
processor is in deep C-states or during transiti ons caused by Enhanced Intel SpeedStep® Technology.
The APIC timer frequency will be the processor’s bus clock or core crystal clock frequency (when TSC/core crystal 
clock ratio is enumerated in CPUID leaf  0x15) divided by the value specified in the divide configuration register.
The timer can be configured through the timer LVT entry for one-shot or periodic operation. In one-shot mode, the 
timer is started by programming its initial-count register. The initial count value is then copied into the current-
count register and count-down begins. After the timer re aches zero, a timer interrupt is generated and the timer 
remains at its 0 value until reprogrammed. 
In periodic mode, the timer is started by writing to the in itial-count register (as in one-shot mode), and the value 
written is copied into the current-count register, which counts down. The current-count register is automatically 
reloaded from the initial-count register when the count re aches 0 and a timer interrupt is generated, and the count-
down is repeated. If during the count-down process the initia l-count register is set, counting will restart, using the 
new initial-count value. The initial-count register is a read -write register; the current-count register is read only.Vol. 3A 11-17ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
A write of 0 to the initial-count register effectively stops the local APIC timer, in both one-shot and periodic mode.
The LVT timer register determines the vector number that is  delivered to the processor with the timer interrupt that 
is generated when the timer count reaches zero. The mask fl ag in the LVT timer register can be used to mask the 
timer interrupt.
NOTE
Changing the mode of the APIC timer (from one-shot  to periodic or vice versa) by writing to the 
timer LVT entry does not start the timer. To start the timer, it is necessary to write to the initial-count register as described above.
11.5.4.1  TSC-Deadline Mode
The mode of operation of the local-APIC timer is determined by the LVT Timer Register. Specifically:
•If CPUID.01H:ECX.TSC_Deadline[bit 24] = 0, the mo de is determined by bit 17 of the register.
•If CPUID.01H:ECX.TSC_Deadline[bit 24] = 1, the mode  is determined by bits 18:17. See Figure 11-8. (If 
CPUID.01H:ECX.TSC_Deadline[bit 24] = 0, bit 18 of the register is reserved.) 
The supported timer modes are given in Table 11-2. The th ree modes of the local APIC timer are mutually exclu-
sive.Figure 11-10.  Divide Configuration Register
 
Figure 11-11.  Initial Coun t and Current Count Registers
Table 11-2. Local APIC Timer Modes
LVT Bits [18:17] Timer Mode
00b One-shot mode, program count-down value in an initial-count register. See Section 11.5.4
01b Periodic mode, program interval value in an initial-count register. See Section 11.5.410b TSC-Deadline mode, program target value in IA32_TSC_DEADLINE MSR.
11b ReservedAddress: FEE0 03E0H
Value after reset: 0H0
Divide Value (bits 0, 1, and 3)
000: Divide by 2
001: Divide by 4
010: Divide by 8
011: Divide by 16
100: Divide by 32
101: Divide by 64
110: Divide by 128
111: Divide by 131 0
31 0
Initial Count
Address: Initial Count
Value after reset: 0HCurrent Count
Current Count FEE0 0390HFEE0 0380H11-18 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
TSC-deadline mode allows software to use the local APIC ti mer to signal an interrupt at an absolute time. In TSC-
deadline mode, writes to the initial-count register are igno red; and current-count register always reads 0. Instead, 
timer behavior is controlled us ing the IA32_TSC_DEADLINE MSR.
The IA32_TSC_DEADLINE MSR (MSR address 6E0H) is a per-lo gical processor MSR that specifies the time at which 
a timer interrupt should occur. Writing a non-zero 64-bit  value into IA32_TSC_DEADLIN E arms the timer. An inter-
rupt is generated when the logical processor’s time-sta mp counter equals or exceeds the target value in the 
IA32_TSC_DEADLINE MSR.3 When the timer generates an interrupt, it disarms itself and clears the 
IA32_TSC_DEADLINE MSR. Thus, each write to the IA32_T SC_DEADLINE MSR generates at most one timer inter-
rupt.
In TSC-deadline mode, writing 0 to the IA32_TSC_DEADLINE MSR disarms the local-APIC timer. Transitioning 
between TSC-deadline mode and other timer modes also disarms the timer.
The hardware reset value of the IA32_TSC_DEADLINE MSR is 0. In other timer modes (LVT bit 18 = 0), the 
IA32_TSC_DEADLINE MSR reads zero and writes are ignored.
Software can configure the TSC-deadline timer to deliver a single interrupt using the following algorithm:
1. Detect support for TSC-deadline mode by verifying CPUID.1:ECX.24 = 1.2. Select the TSC-deadline mode by programming bits 18:17 of the LVT Timer register with 10b.3. Program the IA32_TSC_DEADLINE MSR with the target TSC value at which the timer interrupt is desired. This 
causes the processor to arm the timer.
4. The processor generates a timer interrupt when the value of time-stamp counter is greater than or equal to that 
of IA32_TSC_DEADLINE. It then disarms the timer an d clear the IA32_TSC_DEADLINE MSR. (Both the time-
stamp counter and the IA32_TSC_DEADLINE MSR are 64-bit unsigned integers.)
5. Software can re-arm the timer by repeating step 3.The following are usage guidelines for TSC-deadline mode:
•Writes to the IA32_TSC_DEADLINE MSR are not serialized . Therefore, system software should not use WRMSR 
to the IA32_TSC_DEADLINE MSR as a serializing instruction. Read and write accesses to the 
IA32_TSC_DEADLINE and other MSR registers will occur in program order. 
•Software can disarm the timer at any time by writing 0 to the IA32_TSC_DEADLINE MSR. 
•If timer is armed, software can change the deadline (forward or backward) by writing a new value to the 
IA32_TSC_DEADLINE MSR.
•If software disarms the timer or postpones the deadline, race conditions may result in the delivery of a spurious 
timer interrupt. Software is expected to detect such sp urious interrupts by checking the current value of the 
time-stamp counter to confirm that the interrupt was desired.3
•In xAPIC mode (in which the local-APIC registers are memory-mapped), software must order the memory-
mapped write to the LVT entry that enables TSC- deadline mode and any subsequent WRMSR to the 
IA32_TSC_DEADLINE MSR. Software can assure proper or dering by executing the MFENCE instruction after the 
memory-mapped write and before any WRMSR. (In x2APIC  mode, the WRMSR instruction is used to write to 
the LVT entry. The processor ensures the ordering of th is write and any subsequent WRMSR to the deadline; no 
fencing is required.)
11.5.5 Local Interrupt Acceptance
When a local interrupt is sent to the processor core, it is subject to the acceptance criteria specified in the interrupt 
acceptance flow chart in Figure 11-17. If the interrupt is accepted, it is logged into the IRR register and handled by 
the processor according to its priority (see Section 11.8.4,  “Interrupt Acceptance for Fixed Interrupts”). If the 
interrupt is not accepted, it is sent  back to the local APIC and retried.
3. If the logical processor is in VMX non-root operation, a read of the time-stamp counter (using either RDMSR, RDTSC, or RDTSCP ) may 
not return the actual value of the time-stamp counter; see Chapter 26 of the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 3C. It is the responsibility of software operating in VMX root operation to coordinate th e virtualization  of the 
time-stamp counter and th e IA32_TSC_DEADLINE MSR.Vol. 3A 11-19ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.6 ISSUING INTERPROCESSOR INTERRUPTS
The following sections describe the local APIC facilities that  are provided for issuing inte rprocessor interrupts (IPIs) 
from software. The primary local APIC facility for issuing IPIs is the interrupt command register (ICR). The ICR can 
be used for the following functions:
•To send an interrupt to another processor.
•To allow a processor to forward an interrupt that it received but did not service to another processor for servicing.
•To direct the processor to interrupt itself (perform a self interrupt).
•To deliver special IPIs, such as the start- up IPI (SIPI) message, to other processors. 
Interrupts generated with this facility are delivered to th e other processors in the system through the system bus

Interrupts generated with this facility are delivered to th e other processors in the system through the system bus 
(for Pentium 4 and Intel Xeon processors) or the APIC bus (for P6 family and Pentium processors). The ability for a 
processor to send a lowest priority IPI is model specific and should be avoided by BIOS  and operating system soft-
ware.
11.6.1 Interrupt Command Register (ICR)
The interrupt command register (ICR) is a 64-bit4 local APIC register (see Figure 11-12) that allows software 
running on the processor to specify and send interprocessor interrupts (IPIs) to other processors in the system. 
4. In XAPIC mode the ICR is addr essed as two 32-bit registers, ICR_LOW (FFE0 0300H) and ICR_HIGH (FFE0 0310H). In x2APIC mode, 
the ICR uses MSR 830H.Figure 11-12.  Interrupt Command Register (ICR)31 0
Reserved7
Vector
Destination Shorthand8 10
000: Fixed
001: Lowest Priority100: No Shorthand
01: Self111213141516171819
10: All Including Self
11: All Excluding Self010: SMI
011: Reserved
100: NMI
101: INIT
110: Start Up
111: Reserved
Destination Mode
0: Physical
1: Logical
Delivery Status
0: Idle
1: Send Pending
Level
0 = De-assert
1 = Assert
0: Edge
1: Level63 32
Reserved Destination Field56
Address: FEE0 0300H (0 - 31)
Value after Reset: 0HReserved2055
FEE0 0310H (32 - 63)
 NOTE:
1. The ability of a processor to send Low est Priority IPI is model specific.11-20 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
To send an IPI, software must set up the ICR to indicate  the type of IPI message to be sent and the destination 
processor or processors. (All fields of the ICR are read-wri te by software with the exception of the delivery status 
field, which is read-only.) The act of writing to the low doubleword of the ICR causes the IPI to be sent.
The ICR consists of the following fields. 
Vector The vector number of the interrupt being sent.
Delivery Mode  Specifies the type of IPI to be sent. This fi eld is also know as the IPI message type field.
000 (Fixed) Delivers the interrupt specified in the ve ctor field to the target processor or 
001 (Lowest Priority)
Same as fixed mode, except that the interrupt is delivered to the processor 
executing at the lowest priority amon g the set of processors specified in 
the destination field. The ability for a processor to send a lowest priority 
IPI is model specific and should be avoided by BIOS and operating system 
software.
010 (SMI) Delivers an SMI interrupt to the target processor or processors. The vector 
field must be programmed to 00H for future compatibility.
011 (Reserved)100 (NMI) Delivers an NMI interrupt to the target  processor or processors. The vector 
information is ignored. 
101 (INIT) Delivers an INIT request to the ta rget processor or processors, which 
causes them to perform an INIT. As a result of this IPI message, all the tar-get processors perform an INIT. The vector field must be programmed to 
00H for future compatibility.
101 (INIT Level De-assert)
(Not supported in the Pentium 4 and Intel Xeon processors.) Sends a syn-
chronization message to all the local APICs in the system to set their arbi-tration IDs (stored in their Arb ID registers) to the values of their APIC IDs 
(see Section 11.7, “System and APIC Bus Arbitration”). For this delivery 
mode, the level flag must be set to 0 an d trigger mode flag to 1. This IPI is 
sent to all processors, regardless of the value in the destination field or the 
destination shorthand field; however, software should specify the “all in-
cluding self” shorthand. 
110 (Start-Up)
Sends a special “start-up” IPI (called a SIPI) to the target processor or processors. The vector typically points to a start-up routine that is part of 
the BIOS boot-strap code (see Section 9.4, “Multiple-Processor (MP) Ini-
tialization”). IPIs sent with this delivery mode are not automatically retried if the source APIC is unable to deliver it. It is up to the software to deter-
mine if the SIPI was not successfully delivered and to reissue the SIPI if 
Destination Mode Selects either physical (0) or logical (1) destination mode (see Section 11.6.2, “Determining 
IPI Destination”).
Indicates the IPI delivery status, as follows:
0 (Idle) Indicates that this local APIC has completed sending any previous IPIs.
Indicates that this local APIC has not completed sending the last IPI.
Level For the INIT level de-assert delivery mode this flag must be set to 0; for all other delivery 
modes it must be set to 1. (This flag has no meaning in Pentium 4 and Intel Xeon processors, 
and will always be issued as a 1.)Vol. 3A 11-21ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Trigger Mode Selects the trigger mode when using the INIT le vel de-assert delivery mode: edge (0) or level 
(1). It is ignored for all other delivery modes. (This flag has no meaning in Pentium 4 and Intel 
Xeon processors, and will always be issued as a 0.) 
Destination Shorthand
Indicates whether a shorthand notation is used to specify the destination of the interrupt and, if so, which shorthand is used. Destination shor thands are used in place of the 8-bit destina-
tion field, and can be sent by software using a single write to the low doubleword of the ICR. 
Shorthands are defined for the following cases: software self interrupt, IPIs to all processors in the system including the sender, IPIs to all processors in the system excluding the sender.
00: (No Shorthand)
The destination is specified in the destination field.
01: (Self) The issuing APIC is the one and only destination of the IPI. This destination 
shorthand allows software to interrupt the processor on which it is execut-
ing. An APIC implementation is free to deliver the self-interrupt message 
internally or to issue the message to the bus and “snoop” it as with any other IPI message.
10: (All Including Self)
The IPI is sent to all processors in the system including the processor send-
ing the IPI. The APIC will broadcast an IPI message with the destination field set to FH for Pentium and P6 fami ly processors and to FFH for Pentium 
4 and Intel Xeon processors.
11: (All Excluding Self)
The IPI is sent to all processors in a system with the exception of the pro-
cessor sending the IPI. The APIC broadcasts a message with the physical destination mode and destination field set to FH for Pentium and P6 family 
processors and to FFH for Pentium 4 and Intel Xeon processors. Support 
for this destination shorthand in conj unction with the lowest-priority deliv-
ery mode is model specific. For Pentium 4 and Intel Xeon processors, when 
this shorthand is used together with lowest priority delivery mode, the IPI 
may be redirected back to the issuing processor.
Destination Specifies the target processor or processors. This field is only used when the destination 
shorthand field is set to 00B. If the destination mode is set to physical, then bits 56 through 59 
contain the APIC ID of the target processor for Pentium and P6 family processors and bits 56 
through 63 contain the APIC ID of the target processor the for Pentium 4 and Intel Xeon 
processors. If the destination mode is set to logi cal, the interpretation of the 8-bit destination 
field depends on the settings of the DFR and LDR registers of the local APICs in all the proces-
sors in the system (see Section 11.6.2, “Determining IPI Destination”).
Not all combinations of options for the ICR are valid. Tabl e 11-3 shows the valid combinations for the fields in the 
ICR for the Pentium 4 and Intel Xeon processors; Table 11-4  shows the valid combinations for the fields in the ICR 
for the P6 family processors. Also note that the lower half of the ICR may not be preserved over transitions to the 
deepest C-States.
ICR operation in x2APIC mode is discussed in Section 11.12.9.
Table 11-3. Valid Combinations for Pentium 4 and Intel Xeon Processors Local xAPIC  Interrupt Command Register
Destination Shorthand Valid/Invalid Trigger Mode Delivery Mode Destination Mode
No Shorthand Valid Edge All Modes1Physical or Logical
No Shorthand Invalid2Level All Modes Physical or Logical
Self Valid Edge Fixed X3
Self Invalid2Level Fixed X
Self Invalid X Lowest Priority, NMI, INIT, SMI, Start-Up X
All Including Self Valid Edge Fixed X
All Including Self Invalid2Level Fixed X11-22 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 11-4. Valid Combinations fo r the P6 Family Processor Local APIC Interrupt Command Register
11.6.2 Determining IPI Destination
The destination of an IPI5 can be one, all, or a subset (group) of the processors on the system bus. The sender of 
the IPI specifies the destination of an  IPI with the following APIC registers and fields within the registers:
•ICR Register  — The following fields in the ICR register ar e used to specify the destination of an IPI.All Including Self Invalid X Lowest Pr iority, NMI, INIT , SMI, Start-Up X
All Excluding Self Valid Edg eF i x e d ,  L o w e s t  P r i o r i t y1, 4, NMI, INIT, SM I, Start-Up X
All Excluding Self Invalid2Level FIxed, Lowest Priority4, NMI, INIT, SMI, Start-Up X
NOTES:

NOTES:
1. The ability of a processor to send a lowest priority IPI is model specific.
2. For these interrupts, if the trigger mode bit is 1 (Level), the local xAPIC will override the bit se tting and issue the inte rrupt as an edge 
triggered interrupt.
3. X means the setting is ignored.
4. When using the “lowest priori ty” delivery mode and the “all ex cluding self” destination, the IPI can be redirected back to t he issuing 
APIC, which is essentially the same as the “all including self ” destination mode.
No Shorthand Valid Edge All Modes1
NOTES:
1. The ability of a processor to send a lowest priority IPI is model specific.Physical or Logical
No Shorthand Valid2
2. Treated as edge triggered if leve l bit is set to 1,  otherwise ignored.Level Fixed, Lowest Priority1, NMI Physical or Logical
No Shorthand Valid3
3. Treated as edge triggered when Level bi t is set to 1; treated as “INIT Level Dea ssert” message when leve l bit is set to 0 (d eassert). 
Only INIT level deassert message s are allowed to have th e level bit set to 0. Fo r all other messages the level bit must be set to 1.Level INIT Physical or Logical
Self Valid Edge Fixed X4
4. X means the setting is ignored.Self Valid2Level Fixed X
Self Invalid5
5. The behavior of the APIC is undefined.XL o w e s t  P r i o r i t y ,  N M I ,  INIT, SMI, Start-Up X
All including Self Valid Edge Fixed XAll including Self Valid
2Level Fixed X
All including Self Invalid5XL o w e s t  P r i o r i t y ,  N M I ,  INIT, SMI, Start-Up X
All excluding Self Valid Edge All Modes1X
All excluding Self Valid2Level Fixed, Lowest Priority1, NMI X
All excluding Self Invalid5Level SMI, Start-Up X
All excluding Self Valid3Level INIT X
XI n v a l i d5Level SMI, Start-Up X
5. Determination of IPI destinations in x2APIC mode is discussed in Section 10.12.10.Table 11-3. Valid Combinations for Pentium 4 and Intel Xeon Processors Local xAPIC  Interrupt Command Register
Destination Shorthand Valid/Invalid Tri gger Mode Delivery Mode Destination ModeVol. 3A 11-23ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
—Destination Mode — Selects one of two destination modes (physical or logical).
—Destination Field — In physical destination mode, used to specify the APIC ID of the destination 
processor; in logical destination mode, used to spec ify a message destination address (MDA) that can be 
used to select specific processors in clusters.
—Destination Shorthand  — A quick method of specifying all proce ssors, all excluding self, or self as the 
—Delivery mode, Lowest Priority  — Architecturally specif ies that a lowest-priority arbitration mechanism 
be used to select a destination processor from a spec ified group of processors. The ability of a processor to 
send a lowest priority IPI is model specific and shou ld be avoided by BIOS and operating system software.
•Local destination register (LDR)  — Used in conjunction with the logical destination mode and MDAs to 
select the destination processors.
•Destination format register (DFR)  — Used in conjunction with the lo gical destination mode and MDAs to 
How the ICR, LDR, and DFR are used to select an IPI de stination depends on the destination mode used: physical, 
logical, broadcast/self, or lowest-priority delivery mode . These destination modes are described in the following 
sections.
11.6.2.1  Physical Destination Mode
In physical destination mode, the destination processor is sp ecified by its local APIC ID (see Section 11.4.6, “Local 
APIC ID”). For Pentium 4 and Intel Xeon processors, either a single destination (local APIC IDs 00H through FEH) 
or a broadcast to all APICs (the APIC ID is FFH ) may be specified in physical destination mode. 
A broadcast IPI (bits 28-31 of the MDA are 1's) or I/O subsystem initiated interrupt with lowest priority delivery 
mode is not supported in physical destination mode and must not be configured by software. Also, for any non-
broadcast IPI or I/O subsystem initiated interrupt with lowe st priority delivery mode, software must ensure that 
APICs defined in the interrupt address are present and enabled to receive interrupts. 
For the P6 family and Pentium processors , a single destination is specified in physical destination mode with a local 
APIC ID of 0H through 0EH, allowing up to 15 local APICs to be addressed on the APIC bus. A broadcast to all local 
APICs is specified with 0FH.
NOTE
The number of local APICs that can be addresse d on the system bus may be restricted by 
hardware.
11.6.2.2  Logical Destination Mode
In logical destination mode, IPI destination is specified using an 8-bit message destination address (MDA), which 
is entered in the destination field of the ICR. Upon receiv ing an IPI message that was sent using logical destination 
mode, a local APIC compares the MDA in the message with th e values in its LDR and DFR to determine if it should 
accept and handle the IPI. For both configurations of logi cal destination mode, when combined with lowest priority 
delivery mode, software is responsible for ensuring that all of the local APICs included in or addressed by the IPI or 
I/O subsystem interrupt are present an d enabled to receive the interrupt.
Figure 11-13 shows the layout of the logical destination re gister (LDR). The 8-bit logical APIC ID field in this 
register is used to create an identifi er that can be compared with the MDA.
NOTE
The logical APIC ID should not be confused with the local APIC ID that is contained in the local APIC 
ID register.11-24 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Figure 11-14 shows the layout of the destination format regist er (DFR). The 4-bit model field in this register selects 
one of two models (flat or cluster) that can be used to interpret the MDA when using logical destination mode.
The interpretation of MDA for the two models is described in the following paragraphs.
1.Flat Model — This model is selected by programming DFR bits 28 through 31 to 1111. Here, a unique logical 
APIC ID can be established for up to 8 local APICs by setti ng a different bit in the logical APIC ID field of the LDR 
for each local APIC. A group of local APICs can then be  selected by setting one or more bits in the MDA. 
Each local APIC performs a bit-wise AND of the MDA and its logical APIC ID. If a true condition (non-zero) is 
detected, the local APIC accepts the IP I message. A broadcast to all APICs is achieved by setting the MDA to 1s.
2.Cluster Model — This model is selected by programming DFR bits 28 through 31 to 0000. This model supports 
two basic destination schemes: flat cluster and hierarchical cluster.
The flat cluster destination model is only supported for P6 family and Pentium processors. Using this model, all 
APICs are assumed to be connected through the APIC bus.  Bits 60 through 63 of the MDA contains the encoded 
address of the destination cluster and bits 56 through 59 id entify up to four local APICs within the cluster (each 
bit is assigned to one local APIC in the cluster, as in the flat connection model). To identify one or more local 
APICs, bits 60 through 63 of the MDA are compared with  bits 28 through 31 of the LDR to determine if a local 
APIC is part of the cluster. Bits 56 through 59 of the MDA are compared with Bits 24 through 27 of the LDR to 
identify a local APICs within the cluster. 
Sets of processors within a cluster can be specified by  writing the target cluster address in bits 60 through 63 
of the MDA and setting selected bits in bits 56 throug h 59 of the MDA, corresponding to the chosen members 
of the cluster. In this mode, 15 clusters (with cluster addresses of 0 through 14) each having 4 local APICs can 
be specified in the message. For the P6 and Pentium proc essor’s local APICs, however, the APIC arbitration ID 
supports only 15 APIC agents. Therefore, the total number of processors and their local APICs supported in this mode is limited to 15. Broadcast to all local APICs is  achieved by setting all destination bits to one. This 
guarantees a match on all clusters and selects all APICs in each cluster. A broadcast IPI or I/O subsystem 
broadcast interrupt with lowest priority delivery mode  is not supported in cluster mode and must not be 
configured by software.
The hierarchical cluster destination model can be used with Pentium 4, Intel Xeon, P6 family, or Pentium 
processors. With this model, a hierarchical network ca n be created by connecting different flat clusters via 
independent system or APIC buses. This scheme requires a cluster manager within each cluster, which is 
responsible for handling message passing between system or  APIC buses. One cluster contains up to 4 agents. 
Thus 15 cluster managers, each with 4 agents, can form a network of up to 60 APIC agents. Note that hierar-Figure 11-13.  Logical Destination Register (LDR)

Figure 11-14.  Destinatio n Format Register (DFR)31 0 2324
Reserved Logical APIC ID
Address: 0FEE0 00D0H
Value after reset: 0000 0000H
31 0
Model28
Reserved (All 1s)
Address: 0FEE0 00E0H
Value after reset: FFFF FFFFHFlat model: 1111B
Cluster model: 0000BVol. 3A 11-25ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
chical APIC networks requires a special cluster manager device, which is not part of the local or the I/O APIC 
units.
NOTES
All processors that have their APIC software enable d (using the spurious vector enable/disable bit) 
must have their DFRs (Destination Format Registers) programmed identically.
The default mode for DFR is flat mode. If you are using cluster mode, DFRs must be programmed 
before the APIC is software enabled. Since some chipsets do not accurately track a system view of 
the logical mode, program DFRs as soon as possible after starting the processor.
11.6.2.3  Broadcast/Self Delivery Mode
The destination shorthand field of the ICR allows the delivery  mode to be by-passed in favor of broadcasting the IPI 
to all the processors on the system bus and/or back to itself (see Section 11.6.1, “Interrupt Command Register 
(ICR)”). Three destination shorthands are supported: self, all excluding self, and all including self. The destination 
mode is ignored when a destination shorthand is used.
11.6.2.4  Lowest Pr iority Delivery Mode
With lowest priority delivery mode, th e ICR is programmed to send an IPI to several processors on the system bus, 
using the logical or shorthand destination mechanism for selecting the processor. The selected processors then 
arbitrate with one another over the system bus or the AP IC bus, with the lowest-priority processor accepting the 
IPI. 
For systems based on the Intel Xeon processor, the chipset bus controller accepts messages from the I/O APIC 
agents in the system and directs interrupts to the processo rs on the system bus. When using the lowest priority 
delivery mode, the chipset chooses a target processor to rece ive the interrupt out of the set of possible targets. The 
Pentium 4 processor provides a special bus cycle on the sy stem bus that informs the chipset of the current task 
priority for each logical processor in the system. The chipset saves this information and uses it to choose the lowest priority processor when an interrupt is received.
For systems based on P6 family processors, the processor priority used in lowest-priority arbitration is contained in 
the arbitration priority register (APR) in each lo cal APIC. Figure 11-15 shows the layout of the APR. 
The APR value is computed as follows:
IF (TPR[7:4] 
≥ IRRV[7:4]) AND (TPR[7:4] > ISRV[7:4]) 
THEN 
APR[7:0] ← TPR[7:0]
ELSE 
APR[7:4] ← max(TPR[7:4] AND IS RV[7:4], IRRV[7:4])
APR[3:0] ← 0.
Here, the TPR value is the task priority value in the TP R (see Figure 11-18), the IRRV value is the vector number 
for the highest priority bit that is set in the IRR (see Fi gure 11-20) or 00H (if no IRR bit is set), and the ISRV value 
is the vector number for the highest priority bit that is set in the ISR (see Figure 11-20). Following arbitration  
Figure 11-15.  Arbitration Priority Register (APR)31 0 78
Reserved
Address: FEE0 0090H
Value after reset: 0HArbitration Priority Sub-ClassArbitration Priority Class4311-26 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
among the destination processors, the processor with the lowest value in its APR handles the IPI and the other 
processors ignore it.
(P6 family and Pentium processors.) For these processors, if a focus processor  exists , it may accept the interrupt, 
regardless of its priority. A processor is said to be the focus of an interrupt if it is curre ntly servicing that interrupt 
or if it has a pending request for that interrupt. For Intel Xeon processors, the concept of a focus processor is not 
In operating systems that use the lowest priority delive ry mode but do not update the TPR, the TPR information 
saved in the chipset will potentially cause the interrupt to be always delivered to the same processor from the 
logical set. This behavior is functionally backward compat ible with the P6 family processor but may result in unex-
pected performance implications.
11.6.3 IPI Delivery and Acceptance
When the low double-word of the ICR is written to, the local APIC creates an IPI message from the information 
contained in the ICR and sends the message out on the sy stem bus (Pentium 4 and Intel Xeon processors) or the 
APIC bus (P6 family and Pentium processors). The manner in which these IPIs are handled after being issued is 
described in Section 11.8, “Handling Interrupts.”
11.7 SYSTEM AND APIC BUS ARBITRATION
When several local APICs and the I/O APIC are sending IPI and interrupt messages on the system bus (or APIC 
bus), the order in which the messages are sent and handled is determined through bus arbitration. 
For the Pentium 4 and Intel Xeon processors, the local and I/O APICs use the arbitration mechanism defined for the 
system bus to determine the order in which IPIs are hand led. This mechanism is non-architectural and cannot be 
controlled by software.
For the P6 family and Pentium processors, the local and I/O APICs use an APIC-based arbitration mechanism to 
determine the order in which IPIs are handled. Here, each loca l APIC is given an arbitration priority of from 0 to 15, 
which the I/O APIC uses during arbitration to determine wh ich local APIC should be given access to the APIC bus. 
The local APIC with the highest arbitration priority always wins bus access. Upon completion of an arbitration 
round, the winning local APIC lowers its arbitration priority  to 0 and the losing local APICs each raise theirs by 1.
The current arbitration priority for a local APIC is stored in a 4-bit, software-transparent arbitration ID (Arb ID) 
register. During reset, this register is initialized to the APIC ID number (stored in the local APIC ID register). The 
INIT level-deassert IPI, which is issued with and ICR co mmand, can be used to resynchronize the arbitration prior-
ities of the local APICs by resetting Arb ID register of ea ch agent to its current APIC ID value. (The Pentium 4 and 
Intel Xeon processors do not implement the Arb ID register.)
Section 11.10, “APIC Bus Message Passing Mechanism and Protocol (P6 Family, Pentium Processors),” describes the 
APIC bus arbitration protocols and bus message formats, while Section 11.6.1, “Interrupt Command Register (ICR),” describes the INIT level de-assert IPI message. 
Note that except for the SIPI IPI (see Section 11.6.1, “I nterrupt Command Register (ICR)”), all bus messages that 
fail to be delivered to their specified destination or dest inations are automatically retried. Software should avoid 
situations in which IPIs are sent to disabled or nonexist ent local APICs, causing the messages to be resent repeat-
edly. Additionally, interrupt sources that target the APIC sh ould be masked or changed to no longer target the APIC.
11.8 HANDLING INTERRUPTS
When a local APIC receives an interrupt from a local source , an interrupt message from an I/O APIC, or an IPI, the 
manner in which it handles the message depends on processor implementation, as described in the following sections.Vol. 3A 11-27ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.8.1 Interrupt Handling with the Pentium 4 and Intel Xeon Processors
With the Pentium 4 and Intel Xeon processors, the local APIC handles the local interrupts, interrupt messages, and 
IPIs it receives as follows: 
1. It determines if it is the specified destination or not (see Figure 11-16). If it is the specified destination, it 
accepts the message; if it is not, it discards the message.
2. If the local APIC determines that it is the designated destination for the interrupt and if the interrupt request is 
an NMI, SMI, INIT, ExtINT, or SIPI, the interrupt is  sent directly to the processor core for handling.
3. If the local APIC determines that it is the designated  destination for the interrupt but the interrupt request is 
not one of the interrupts given in step 2, the lo cal APIC sets the appropriate bit in the IRR. 
4. When interrupts are pending in the IRR register, the loca l APIC dispatches them to the processor one at a time, 
based on their priority and the current processor priority  in the PPR (see Section 11.8.3.1, “Task and Processor 
Priorities”).
5. When a fixed interrupt has been dispatched to the proc essor core for handling, the completion of the handler 
routine is indicated with an instruction in the instructio n handler code that writes to the end-of-interrupt (EOI) 
register in the local APIC (see Section 11.8.5, “Signaling Interrupt Servicing Completion”). The act of writing to 
the EOI register causes the local APIC to delete the interrupt from its ISR queu e and (for level-triggered 
interrupts) send a message on the bus indicating that th e interrupt handling has been completed. (A write to 
the EOI register must not be included in the handle r routine for an NMI, SMI, INIT, ExtINT, or SIPI.)
11.8.2 Interrupt Handling with the P6 Family and Pentium Processors

With the P6 family and Pentium processors, the local AP IC handles the local interrupts, interrupt messages, and 
IPIs it receives as follows (see Figure 11-17).
1. (IPIs only) The local APIC examines the IPI message to de termines if it is the specified destination for the IPI 
as described in Section 11.6.2, “Determining IPI Destinatio n.” If it is the specified destination, it continues its 
acceptance procedure; if it is not the destination, it discards the IPI message. When the message specifies 
lowest-priority delivery mode, the local APIC will arbitrat e with the other processors that were designated as 
recipients of the IPI message (see Section 11.6.2.4, “Lowest Priority Delivery Mode”).
an NMI, SMI, INIT, ExtINT, or INIT-deassert interrupt, or  one of the MP protocol IPI messages (BIPI, FIPI, and 
SIPI), the interrupt is sent directly to the processor core for handling.
not one of the interrupts given in step 2, the local APIC l ooks for an open slot in one of its two pending interrupt 
queues contained in the IRR and ISR registers (see Figure 11-20). If a slot is available (see Section 11.8.4, 
“Interrupt Acceptance for Fixed Interrupts”), places the inte rrupt in the slot. If a slot is not available, it rejects 
the interrupt request and sends it back to the sender with a retry message.
routine is indicated with an instruction in the instructio n handler code that writes to the end-of-interrupt (EOI) Figure 11-16.  Interrupt Acceptance Flow Chart for the Local APIC (Pentium 4 and Intel Xeon Processors)Wait to Receive 
Bus Message
Belong to 
Destination? Discard 
MessageNo Accept 
MessageYes11-28 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
register in the local APIC (see Section 11.8.5, “Signalin g Interrupt Servicing Completion”). The act of writing to 
the EOI register causes the local APIC to delete the inte rrupt from its queue and (for level-triggered interrupts) 
send a message on the bus indicating that the interrupt  handling has been completed. (A write to the EOI 
register must not be included in the handler routine for an NMI, SMI, INIT, ExtINT, or SIPI.)
The following sections describe the acceptance of interrupt s and their handling by the local APIC and processor in 
greater detail. 
11.8.3 Interrupt, Task, and Processor Priority
Each interrupt delivered to the processor through the local APIC has a priority based on its vector number. The local APIC uses this priority to determine when to service the in terrupt relative to the other activities of the processor, 
including the servicing of other interrupts. 
Each interrupt vector is an 8-bit value. The interrupt-priority class  is the value of bits 7:4 of the interrupt vector. 
The lowest interrupt-priority class is 1 and the highest is  15; interrupts with vectors in the range 0–15 (with inter-
rupt-priority class 0) are illegal and are never delivered. Because vectors 0–31 are reserved for dedicated uses by 
the Intel 64 and IA-32 architectures, software should configure interrupt vectors to use interrupt-priority classes in 
the range 2–15.
Each interrupt-priority class encompasses 16 vectors. The relative priority of interrupts within an interrupt-priority 
class is determined by the value of bits 3:0 of the vector number. The higher the value of those bits, the higher the Figure 11-17.  Interrupt Acceptance Flow Chart fo r the Local APIC (P6 Family  and Pentium Processors)Wait to Receive
Belong
to
Destination?
Is it
NMI/SMI/INIT
/ExtINT?
Delivery
Am I
Focus?
Other 
Focus?Is Interrupt Slot 
Available?
Is Status a 
Retry?Discard 
MessageAccept 
MessageYes
Yes
Accept 
Message
Is Interrupt 
Slot Avail-
able?ArbitrateYes
Am I Winner? Accept 
MessageYes NoSet Status
to RetryNo
NoYes
Set Status 
to RetryNoDiscard
MessageNo
Accept
Lowest 
Priority Fixed
Yes No
NoYes
No
P6 Family 
Processor Specific
 Vol. 3A 11-29ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
priority within that interrupt-priority class. Thus, each in terrupt vector comprises two parts, with the high 4 bits 
indicating its interrupt-priority class and the low 4 bits indicating its ranking within  the interrupt-priority class.
11.8.3.1  Task and Processor Priorities
The local APIC also defines a task priority  and a processor priority  that determine the order in which interrupts 
are handled. The task-priority class  is the value of bits 7:4 of the task-priority register (TPR), which can be 
written by software (TPR is a read/write register); see Figure 11-18. 
NOTE
In this discussion, the term “task” refers to a so ftware defined task, process, thread, program, or 
routine that is dispatched to run on the processor by the operating system. It does not refer to an 
IA-32 architecture defined task as descr ibed in Chapter 8, “Task Management.”
The task priority allows software to set a priority thresh old for interrupting the processor. This mechanism enables 
the operating system to temporarily block low priority interrupts from disturbing high-priority work that the 
processor is doing. The ability to block such interrupts using task priority results from the way that the TPR controls 
the value of the processor-priority register (PPR).6
The processor-priority class  is a value in the range 0–15 that is mainta ined in bits 7:4 of the processor-priority 
register (PPR); see Figure 11-19. The PPR is a read-only register. The processor-priority class represents the 
current priority at which the processor is executing.
The value of the PPR is based on the value of TPR and th e value ISRV; ISRV is the vector number of the highest 
priority bit that is set in the ISR or 00H if no bit is set in the ISR. (See Section 11.8.4 for more details on the ISR.) 
The value of PPR is determined as follows:
•PPR[7:4] (the processor-priority cla ss) the maximum of TPR[7:4] (the task- priority class) and ISRV[7:4] (the 
priority of the highest priority interrupt in service).
•PPR[3:0] (the processor-priority sub-class) is determined as follows:
— If TPR[7:4] > ISRV[7:4], PPR[3:0] is TPR[3:0] (the task-priority sub-class).— If TPR[7:4] < ISRV[7:4], PPR[3:0] is 0.
— If TPR[7:4] = ISRV[7:4], PPR[3:0] may be either TPR[ 3:0] or 0. The actual behavior is model-specific. 
Figure 11-18.  Task-Priority Register (TPR)
6. The TPR also determines the arbitration pr iority of the local processor; see Section 11.6.2.4, “Lowest Priority Delivery Mode .” 
Figure 11-19.  Processor- Priority Register (PPR)31 0 78
Reserved
Address: FEE0 0080H
Value after reset: 0HTask-Priority Sub-ClassTask-Priority Class43
31 0 78
Reserved
Address: FEE0 00A0H
Value after reset: 0HProcessor-Priority Sub-ClassProcessor-Priority Class4311-30 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The processor-priority class determines the priority th reshold for interrupting the processor. The processor will 
deliver only those interrupts that have an interrupt-priority class higher than the processor-priority class in the PPR. If the processor-priority class is 0,  the PPR does not inhibit the delivery any interrupt; if it is 15, the processor 
inhibits the delivery of all interrupts. (The processor-prio rity mechanism does not affect the delivery of interrupts 
with the NMI, SMI, INIT, ExtINT, INIT-deassert, and start-up delivery modes.)
The processor does not use the processor-priority sub-class to determine which interrupts to deliver and which to 
inhibit. (The processor uses the processor-priority sub-class only to satisfy reads of the PPR.)
11.8.4 Interrupt Acceptan ce for Fixed Interrupts
The local APIC queues the fixed interrupts that it accepts in one of two interrupt pend ing registers: the interrupt 
request register (IRR) or in-service register (ISR). These two 256-bit read-only registers are shown in 
Figure 11-20. The 256 bits in these registers represent the 256 possible vectors; vectors 0 through 15 are reserved 
by the APIC (see also: Section 11.5.2, “Valid Interrupt Vectors”).
NOTE
All interrupts with an NMI, SMI, INIT, ExtINT, st art-up, or INIT-deassert delivery mode bypass the 
IRR and ISR registers and are sent direct ly to the processor core for servicing.
The IRR contains the active interrupt requests that have been accepted, but not yet dispatched to the processor for 
servicing. When the local APIC accepts an interrupt, it se ts the bit in the IRR that corresponds the vector of the

NOTE
servicing. When the local APIC accepts an interrupt, it se ts the bit in the IRR that corresponds the vector of the 
accepted interrupt. When the processor core is ready to ha ndle the next interrupt, the local APIC clears the highest 
priority IRR bit that is set and sets the corresponding ISR bi t. The vector for the highest priority bit set in the ISR is 
then dispatched to the processor core for servicing. 
While the processor is servicing the highest priority interru pt, the local APIC can send additional fixed interrupts by 
setting bits in the IRR. When the interrupt service routin e issues a write to the EOI register (see Section 11.8.5, 
“Signaling Interrupt Servicing Completion”), the local APIC re sponds by clearing the highest priority ISR bit that is 
set. It then repeats the process of clearing the highest pr iority bit in the IRR and setting the corresponding bit in 
the ISR. The processor core then begins executing the se rvice routing for the highest priority bit set in the ISR.
If more than one interrupt is generated with the same ve ctor number, the local APIC can set the bit for the vector 
both in the IRR and the ISR. This means that for the Pentium 4 and Intel Xeon processors, the IRR and ISR can 
queue two interrupts for each interrupt vector: one in the IRR and one in the ISR. Any additional interrupts issued 
for the same interrupt vector are collapsed into the single bit in the IRR.
For the P6 family and Pentium processors, the IRR and ISR registers can queue no more than two interrupts per 
interrupt vector and will reject other interrupt s that are received within the same vector. 
If the local APIC receives an interrupt with an interrupt-priority class higher than that of the interrupt currently in 
service, and interrupts are enabled in the processor core, th e local APIC dispatches the higher priority interrupt to 
the processor immediately (without waiting for a write to  the EOI register). The currently executing interrupt 
handler is then interrupted so the high er-priority interrupt can be handled. When the handling of the higher-priority 
interrupt has been completed, the servicin g of the interrupted interrupt is resumed. 
Figure 11-20.  IRR, ISR, and TMR Registers255 0
Reserved
Addresses: IRR FEE0 0200H - FEE0 0270H 
Value after reset: 0H16 15
IRR
Reserved ISRReserved TMR
ISR FEE0 0100H - FEE0 0170H
TMR FEE0 0180H - FEE0 01F0HVol. 3A 11-31ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The trigger mode register (TMR) indicates the trigger mo de of the interrupt (see Figure 11-20). Upon acceptance 
of an interrupt into the IRR, the corresponding TMR bit is cleared for edge-triggered interrupts and set for level-
triggered interrupts. If a TMR bit is set when an EOI cycl e for its corresponding interrupt vector is generated, an 
EOI message is sent to all I/O APICs.
11.8.5 Signaling Interrupt Servicing Completion
For all interrupts except those delivered with the NMI, SMI, INIT, ExtINT, the start-up, or INIT-Deassert delivery 
mode, the interrupt handler must include a write to the en d-of-interrupt (EOI) register (see Figure 11-21). This 
write must occur at the end of the handler routine, sometime  before the IRET instruction. This action indicates that 
the servicing of the current interrupt is complete and th e local APIC can issue the next interrupt from the ISR. 
Upon receiving an EOI, the APIC clears the highest priority  bit in the ISR and dispatches the next highest priority 
interrupt to the processor. If the terminated interrupt wa s a level-triggered interrupt, the local APIC also sends an 
end-of-interrupt message to all I/O APICs. 
System software may prefer to direct EOIs to specific I/O APICs rather than having the local APIC send end-of-
interrupt messages to all I/O APICs.
Software can inhibit the broadcast of EOI message by setting  bit 12 of the Spurious Interrupt Vector Register (see 
Section 11.9). If this bit is set, a broadcast EOI is not ge nerated on an EOI cycle even if the associated TMR bit indi-
cates that the current interrupt was level-triggered. The defa ult value for the bit is 0, indicating that EOI broadcasts 
are performed.
Bit 12 of the Spurious Interrupt Vector Register is reserv ed to 0 if the processor does not support suppression of 
EOI broadcasts. Support for EOI-broadcast suppression is reported in bit 24 in the Local APIC Version Register (see 
Section 11.4.8); the feature is supported if that bit is set to 1. When supported, the feature is available in both 
xAPIC mode and x2APIC mode.
System software desiring to perform directed EOIs for le vel-triggered interrupts should set bit 12 of the Spurious 
Interrupt Vector Register and follow each the EOI to the lo cal xAPIC for a level triggered interrupt with a directed 
EOI to the I/O APIC generating the interrupt (this is done by writing to the I/O APIC’s EOI register). System soft-
ware performing directed EOIs must retain a mapping a ssociating level-triggered interrupts with the I/O APICs in 
11.8.6 Task Priority in IA-32e Mode
In IA-32e mode, operating systems can manage the 16 inte rrupt-priority classes (see Section 11.8.3, “Interrupt, 
Task, and Processor Priority”) explicitly using the task priority register  (TPR). Operating systems can use the TPR 
to temporarily block specific (low-priority) interrupts from interrupting a high-priority task. This is done by loading 
TPR with a value in which the task-priority class corresponds to the highest interrupt-priority class that is to be blocked. For example: 
•Loading the TPR with a task-priority class of 8 (01000B) bl ocks all interrupts with an interrupt-priority class of 
8 or less while allowing all interrupts with an interrupt-priority class of 9 or more to be recognized.
•Loading the TPR with a task-priority cla ss of 0 enables all external interrupts. 
•Loading the TPR with a task-priority class of 0FH (01111B) disables all external interrupts. 
The TPR (shown in Figure 11-18) is cleared to 0 on rese t. In 64-bit mode, software can read and write the TPR 
using an alternate interface, MOV CR8 instruction. The new task-priority class is established when the MOV CR8 Figure 11-21.  EOI Register31 0
Address: 0FEE0 00B0H
Value after reset: 0H11-32 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
instruction completes execution. Software does not need  to force serialization after loading the TPR using MOV 
CR8. 
Use of the MOV CRn instruction requires a privilege level of  0. Programs running at privilege level greater than 0 
cannot read or write the TPR. An attempt to do so causes  a general-protection exception. The TPR is abstracted 
from the interrupt controller (IC), which prioritizes and manages external interrupt delivery to the processor. The 
IC can be an external device, such as an APIC or 8259. Typically, the IC provides a priority mechanism similar or 
identical to the TPR. The IC, however, is considered impl ementation-dependent with th e under-lying priority mech-
anisms subject to change. CR8, by contrast, is part of th e Intel 64 architecture. Software can depend on this defi-
nition remaining unchanged. 
Figure 11-22 shows the layout of CR8; only the low four bits are used. The remaining 60 bits are reserved and must 
be written with zeros. Failure to do this causes a general-protection exception.
11.8.6.1  Interaction of Task Priorities between CR8 and APIC
The first implementation of Intel 64 architecture includ es a local advanced programmable interrupt controller 
(APIC) that is similar to the APIC used with previous IA -32 processors. Some aspects of the local APIC affect the 
operation of the architecturally defined task priori ty register and the progra mming interface using CR8.
Notable CR8 and APIC interactions are:
•The processor powers up with the local APIC enabled.
•The APIC must be enabled for CR8 to f unction as the TPR. Writes to CR8 are reflected into the APIC Task Priority 
Register.
•APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0. A read of CR8 returns a 64-bit value which is the 
value of TPR[bits 7:4], zero extended to 64 bits.
There are no ordering mechanisms between direct update s of the APIC.TPR and CR8. Operating software should 
implement either direct APIC TPR updates or CR8 style TPR updates but not mix them. Software can use a serial-izing instruction (for example, CPUID) to serializ e updates between MOV CR8 and stores to the APIC.
11.9 SPURIOUS INTERRUPT
A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the 
interrupt for which the processor INTR signal is currently be ing asserted. If at the time the INTA cycle is issued, the 
interrupt that was to be dispensed has become masked (p rogrammed by software), the local APIC will deliver a 
spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this 
vector should return without an EOI.
The vector number for the spurious-interrupt vector is specified in the spurious-interrupt vector register (see

The vector number for the spurious-interrupt vector is specified in the spurious-interrupt vector register (see 
Figure 11-23). The functions of the fields in this register are as follows:
Spurious Vector Determines the vector number to be delivered to the processor when the local APIC generates 
a spurious vector. 
(Pentium 4 and Intel Xeon processors.) Bits 0 through 7 of the this field are programmable by 
software. 
(P6 family and Pentium processors). Bits 4 through 7 of the this field are programmable by 
software, and bits 0 through 3 are hardwired to logical ones. Software writes to bits 0 through 
3 have no effect.Figure 11-22.  CR8 Register63 0
Value after reset: 0H34
ReservedVol. 3A 11-33ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
APIC Software Enable/Disable
Allows software to temporarily enable (1) or disable (0) the local APIC (see Section 11.4.3, 
“Enabling or Disabling the Local APIC”).
Focus Processor Checking
Determines if focus processor checking is enab led (0) or disabled (1) when using the lowest-
priority delivery mode. In Pentium 4 and Intel Xeon processors, this bit is reserved and should 
be cleared to 0.
Suppress EOI Broadcasts
Determines whether an EOI for a level-triggere d interrupt causes EOI messages to be broad-
cast to the I/O APICs (0) or not (1). See Section 11.8.5. The default value for this bit is 0, indi-
cating that EOI broadcasts are performed. This bit is reserved to 0 if the processor does not 
support EOI-broadcast suppression.
NOTE
Do not program an LVT or IOAPIC RTE with a spurious vector even if you set the mask bit. A 
spurious vector ISR does not do an EOI. If for some reason an interrupt is generated by an LVT or 
RTE entry, the bit in the in-service register will be left set for the spurious vector. This will mask all 
interrupts at the same or lower priority
11.10 APIC BUS MESSAGE PASSING MECH ANISM AND PROTOCOL (P6 FAMILY, 
PENTIUM PROCESSORS)
The Pentium 4 and Intel Xeon processors pass messages among the local and I/O APICs on the system bus, using 
the system bus message passing mechanism and protocol.
The P6 family and Pentium processors, pass messages among the local and I/O APICs on the serial APIC bus, as 
follows. Because only one message can be sent at a time on the APIC bus, the I/O APIC and local APICs employ a 
“rotating priority” arbitration protocol to gain permission  to send a message on the APIC bus. One or more APICs 
may start sending their messages simultaneously. At the be ginning of every message, each APIC presents the type 
of the message it is sending and its current arbitration priority on the APIC bus. This information is used for arbi-
tration. After each arbitration cycle (within an arbitration round), only the potential winners keep driving the bus. Figure 11-23.  Spurious-Interrupt Vector Register (SVR)31 0
Reserved7
Focus Processor Checking2
APIC Software Enable/Disable8910
0: APIC Disabled
1: APIC Enabled
Spurious Vector3
Address: FEE0 00F0H
Value after reset: 0000 00FFH0: Enabled
1: Disabled
1. Not supported on all processors. See bi t 24 of Local APIC Version Register.
2. Not supported in Pentium 4 and Intel Xeon processors.3. For the P6 family and Pentium processors, bits 0 through 3 are always 1.1112
EOI-Broadcast Suppression1
0: Disabled
1: Enabled11-34 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
By the time all arbitration cycles are completed, there will be only one APIC left driving the bus. Once a winner is 
selected, it is granted exclusive use of the bus, and w ill continue driving the bus to send its actual message.
After each successfully transmitted message, all APICs increa se their arbitration priority by 1. The previous winner 
(that is, the one that has just successfully transmitted its message) assumes a priority of 0 (lowest). An agent 
whose arbitration priority was 15 (highest) during arbitr ation, but did not send a me ssage, adopts the previous 
winner’s arbitration priority, incremented by 1. 
Note that the arbitration protocol described above is slight ly different if one of the APICs issues a special End-Of-
Interrupt (EOI). This high-priority message is granted the bus regardless of its sender’s arbitration priority, unless 
more than one APIC issues an EOI message simultan eously. In the latter case, the APICs sending the EOI 
messages arbitrate using their arbitration priorities.
If the APICs are set up to use “lowest priority” arbitratio n (see Section 11.6.2.4, “Lowest Priority Delivery Mode”) 
and multiple APICs are currently executing at the lowest pr iority (the value in the APR register), the arbitration 
priorities (unique values in the Arb ID register) are used to  break ties. All 8 bits of the APR are used for the lowest 
priority arbitration.
11.10.1 Bus Message Formats
See Section 11.13, “APIC Bus Message Formats,” for a de scription of bus message formats used to transmit 
messages on the serial APIC bus.
11.11 MESSAGE SIGNALLED INTERRUPTS
The PCI Local Bus Specification, Rev 2.2 (www.pcisig.com) introduces the concept of message signalled interrupts. 
As the specification indicates:
“Message signalled interrupts (MSI) is an option al feature that enables PCI devices to request 
service by writing a system-specified message to  a system-specified addr ess (PCI DWORD memory 
write transaction). The transaction address specifies the message destination while the transaction 
data specifies the message. System software is expected to initialize the message destination and message during device configuration, allocating one or more non-shared messages to each MSI 
capable function.” 
The capabilities mechanism provided by  the PCI Local Bus Specification is used to identify and configure MSI 
capable PCI devices. Among other fields, this structure contains a Message Data Register and a Message Address 
Register. To request service, the PCI device function wr ites the contents of the Message Data Register to the 
address contained in the Message Address Register (and  the Message Upper Address register for 64-bit message 
addresses). 
Section 11.11.1 and Section 11.11.2 provide layout details for the Message Address Register and the Message Data 
Register. The operation issued by the device is a PCI write command to the Message Address Register with the 
Message Data Register contents. The operation follows semantic rules as defined for PCI write operations and is a DWORD operation.
11.11.1 Message Address Register Format
The format of the Message Address Register (lower 32-bits) is shown in Figure 11-24.
Figure 11-24.  Layout of th e MSI Message Address Register31 20 19 12 11 4 3 2 1 0
0FEEH Destination ID Reserved RH DM XXVol. 3A 11-35ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Fields in the Message Address Register are as follows:
1.Bits 31-20  — These bits contain a fixed value for interrupt messages (0FEEH). This value locates interrupts at 
the 1-MByte area with a base address of 4G – 18M. All accesses to this region are directed as interrupt messages. Care must to be taken to ensure that no other device claims the region as I/O space.
2.Destination ID  — This field contains an 8-bit destination ID. It identifies the message’s target processor(s). 
The destination ID corresponds to bits 63:56 of the I/O APIC Redirection Table Entry if the IOAPIC is used to 
dispatch the interrupt to the processor(s).
3.Redirection hint indication  (RH) — When this bit is set, the message is directed to the processor with the 
lowest interrupt priority among processors that can receive the interrupt. 
•When RH is 0, the interrupt is directed to th e processor listed in the Destination ID field. 
•When RH is 1 and the physical destination mode is us ed, the Destination ID field must not be set to FFH; 
it must point to a processor that is present and enabled to receive the interrupt.
•When RH is 1 and the logical destination mode is acti ve in a system using a flat addressing model, the 
Destination ID field must be set so that bits set to 1 identify processors that are present and enabled to 
receive the interrupt.
•If RH is set to 1 and the logical destination mode is active in a system using cluster addressing model, 
then Destination ID field must not be set to FFH; th e processors identified with this field must be 
present and enabled to receive the interrupt.
4.Destination mode (DM)  — This bit indicates whether the Destination ID field should be interpreted as logical 
or physical APIC ID for delivery of the lowest priority interrupt. 
•If RH is 1 and DM is 0, the Destination ID field is in physical destination mode and only the processor in 
the system that has the matching APIC ID is consider ed for delivery of that interrupt (this means no re-
direction). 
•If RH is 1 and DM is 1, the Destination ID Field is  interpreted as in logical destination mode and the 
redirection is limited to only those processors that are part of the logical group of processors based on 
the processor’s logical APIC ID and the Destinatio n ID field in the message. The logical group of

the processor’s logical APIC ID and the Destinatio n ID field in the message. The logical group of 
processors consists of those identified by matching the 8-bit Destination ID with the logical destination 
identified by the Destination Format Register and the Logical Destination Register in each local APIC. 
The details are similar to those described in Section 11.6.2, “Determining IPI Destination.” 
•If RH is 0, then the DM bit is ignored and the message is sent ahead independent of whether the 
physical or logical destination mode is used.
11.11.2 Message Data Register Format
The layout of the Message Data Register is shown in Figure 11-25.
Reserved fields are not assumed to be any value. Software must preserve their contents on writes. Other fields in 
the Message Data Register are described below.
1.Vector  — This 8-bit field contains the interrupt vector a ssociated with the message. Values range from 010H 
to 0FEH. Software must guarantee that the fiel d is not programmed with vector 00H to 0FH.
2.Delivery Mode  — This 3-bit field specifies how the interrupt receipt is handled. Delivery Modes operate only in 
conjunction with specified Trigger Modes. Correct Trigge r Modes must be guaranteed by software. Restrictions 
are indicated below:
a.000B (Fixed Mode)  — Deliver the signal to all the agents list ed in the destination. The Trigger Mode for
fixed delivery mode can be edge or level.
b.001B (Lowest Priority)  — Deliver the signal to the agent that is executing at the lowest priority of all 
agents listed in the destination field. The trigger mode can be edge or level.
c.010B (System Management Interrupt or SMI)  — The delivery mode is edge only. For systems that rely 
on SMI semantics, the vector field is ignored but must be programmed to all zeroes for future compatibility. 11-36 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
d.100B (NMI)  — Deliver the signal to all the agents listed in the destination field. The vector information is 
ignored. NMI is an edge triggered interru pt regardless of the Trigger Mode Setting.
e.101B (INIT)  — Deliver this signal to all the agents listed in  the destination field. The vector information is 
ignored. INIT is an edge triggered interrupt regardless of the Trigger Mode Setting.
f.111B (ExtINT)  — Deliver the signal to the INTR signal of all agents in the destination field (as an interrupt 
that originated from an 8259A compatible interrupt co ntroller). The vector is supplied by the INTA cycle 
issued by the activation of the ExtINT. ExtINT is an edge triggered interrupt.
3.Level  — Edge triggered interrupt messages are always in terpreted as assert messages. For edge triggered 
interrupts this field is not used. For level triggered interru pts, this bit reflects the state of the interrupt input.
4.Trigger Mode  — This field indicates the signal type that will trigger a message. 
a.0 — Indicates edge sensitive.
b.1 — Indicates level sensitive.
11.12 EXTENDED XAPIC (X2APIC)
The x2APIC architecture extends the xAPIC architecture (described in Section 11.4) in a backward compatible 
manner and provides forward extendability for future Intel platform innovations. Specifically, the x2APIC architec-
ture does the following.
•Retains all key elements of compatibility to the xAPIC architecture.
— Delivery modes.— Interrupt and processor priorities.— Interrupt sources.
— Interrupt destination types.
•Provides extensions to scale processor addressability for both the logical and physical destination modes.Figure 11-25.  Layout of the MSI Message Data RegisterReserved
Reserved Reserved Vector
001 - Lowest Priority
010 - SMI
011 - Reserved
101 - INIT
110 - Reserved
111 - ExtINTTrigger Mode
0 - Edge
1 - Level
Level for Trigger Mode = 0
X - Don’t care
Level for Trigger Mode = 1
0 - Deassert
1 - Assert000 - Fixed
100 - NMI31 16  15 14 13 11 10 8 7 063 32Vol. 3A 11-37ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
•Adds new features to enhance performance of interrupt delivery.
•Reduces complexity of logical destination mode inte rrupt delivery on link based platform architectures.
•Uses MSR programming interface to access APIC regi sters in x2APIC mode instead of memory-mapped 
interfaces. Memory-mapped interface is su pported when operating in xAPIC mode.
11.12.1 Detecting and Enabling x2APIC Mode
Processor support for x2APIC mode can be detected by executing CPUID with EAX=1 and then checking ECX, bit 
21 ECX. If CPUID.(EAX=1):ECX.21 is set , the processor supp orts the x2APIC capability and can be placed into the 
x2APIC mode. 
System software can place the local APIC in the x2APIC mode  by setting the x2APIC mode enable bit (bit 10) in the 
IA32_APIC_BASE MSR at MSR address 01BH. The layout fo r the IA32_APIC_BASE MSR is shown in Figure 11-26.
Table 11-5, “x2APIC operating mode configurations” describ e the possible combinations of the enable bit (EN - bit 
11) and the extended mode bit (EXTD - bit 10) in the IA32_APIC_BASE MSR.
Once the local APIC has been switched to x2APIC mode (EN = 1, EXTD = 1), switching back to xAPIC mode would 
require system software to disable the local APIC unit. Specifically, attempting to write a value to the IA32_APIC_BASE MSR that has (EN= 1, EXTD = 0) when th e local APIC is enabled and in x2APIC mode causes a 
general-protection exception. Once bit 10 in IA32_APIC_ BASE MSR is set, the only way to leave x2APIC mode 
using IA32_APIC_BASE would require a WRMSR to set both bit 11 and bit 10 to zero. Section 11.12.5, “x2APIC State Transitions,” provides a detailed state diagram for the state transitions allowed for the local APIC.
11.12.1.1  Instructions to Access APIC Registers
In x2APIC mode, system software uses RDMSR and WRMSR to access the APIC regist ers. The MSR addresses for 
accessing the x2APIC registers are architecturally define d and specified in Section 11.12.1.2, “x2APIC Register 
Address Space.” Executing the RDMSR in struction with the APIC register address specified in ECX returns the 
content of bits 0 through 31 of the APIC registers in EAX. Bits 32 through 63 are returned in register EDX - these 
bits are reserved if the APIC register being read is a 32- bit register. Similarly executing the WRMSR instruction with 
the APIC register address in ECX, writes bits 0 to 31 of re gister EAX to bits 0 to 31 of the specified APIC register. If 
the register is a 64-bit register then bits 0 to 31 of regist er EDX are written to bits 32 to 63 of the APIC register. The Figure 11-26.  IA32_APIC_BASE MSR Supporting x2APIC
Table 11-5. x2APIC Operat ing Mode Configurations 
xAPIC global enable 
(IA32_APIC_BASE[11])x2APIC enable 
(IA32_APIC_BASE[10]) Description
0 0 local APIC is disabled01 I n v a l i d
1 0 local APIC is en abled in xAPIC mode
1 1 local APIC is enabled in x2APIC modeBSP—Processor is BSPEN—xAPIC global enable/disableAPIC Base—Base physical address63 0 7 1011 89 12
Reserved3635
EXTD—Enable x2APIC mode11-38 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Interrupt Command Register is the only APIC register that is implemented as a 64-bit MSR. The semantics of 
handling reserved bits are defined in Section 11.12.1.3, “Reserved Bit Checking.”
11.12.1.2  x2APIC Register Address Space
The MSR address range 800H through 8FFH is architecturally  reserved and dedicated for accessing APIC registers 
in x2APIC mode. Table 11-6 lists the APIC registers that ar e available in x2APIC mode. When appropriate, the table 
also gives the offset at which each register is availa ble on the page referenced by IA32_APIC_BASE[35:12] in 
xAPIC mode. 
There is a one-to-one mapping between the x2APIC MSRs an d the legacy xAPIC register offsets with the following 
exceptions:
•The Destination Format Register (DFR): The DFR, supporte d at offset 0E0H in xAPIC mode, is not supported in 
x2APIC mode. There is no MSR with address 80EH.
•The Interrupt Command Register (ICR): The two 32-bit re gisters in xAPIC mode (at offsets 300H and 310H) are 
merged into a single 64-bit MSR in  x2APIC mode (with MSR address 830H). There is no MSR with address 
831H.
•The SELF IPI register. This register is available only in  x2APIC mode at address 83FH. In xAPIC mode, there is 
no register defined at offset 3F0H.
MSR addresses in the range 800H–8FFH that are not listed in Table 11-6 (including 80EH and 831H) are reserved. 
Executions of RDMSR and WRMSR that attempt to access such addresses cause general-protection exceptions.
The MSR address space is compressed to allow for future gr owth. Every 32 bit register on a 128-bit boundary in the 
legacy MMIO space is mapped to a single MSR in the lo cal x2APIC MSR address space. The upper 32-bits of all 
x2APIC MSRs (except for the ICR) are reserved. 
Table 11-6. Local APIC Register Address Map Supported by x2APIC
MSR Address (x2APIC mode)MMIO Offset 
(xAPIC mode)Register NameMSR R/W 
SemanticsComments
 802H 020H Local APIC ID register Read-only
1See Section 11.12.5.1 for initial 
values.
803H 030H Local APIC Version register Read -only Same version used in xAPIC mode 
and x2APIC mode.

831H.
values.
808H 080H Task Priority Register (T PR) Read/write Bits 31:8 are reserved.2
80AH 0A0H Processor Priority Register 
(PPR)Read-only
80BH 0B0H EOI register Write-only3WRMSR of a non-zero value causes 
#GP(0).
80DH 0D0H Logical Destination Register 
(LDR)Read-only Read/write in xAPIC mode.
80FH 0F0H Spurious Interrupt Vector 
Register (SVR)Read/write See Section 11.9 for reserved bits.
810H 100H In-Service Register (ISR); bits 
31:0Read-only
811H 110H ISR bits 63:32 Read-only
812H 120H ISR bits 95:64 Read-only
813H 130H ISR bits 127:96 Read-only814H 140H ISR bits 159:128 Read-only
815H 150H ISR bits 191:160 Read-only
816H 160H ISR bits 223:192 Read-onlyVol. 3A 11-39ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
817H 170H ISR bits 255:224 Read-only
818H 180H Trigger Mode Register (TMR); 
bits 31:0 Read-only
819H 190H TMR bits 63:32 Read-only
81AH 1A0H TMR bits 95:64 Read-only
81BH 1B0H TMR bits 127:96 Read-only
81CH 1C0H TMR bits 159:128 Read-only81DH 1D0H TMR bits 191:160 Read-only
81EH 1E0H TMR bits 223:192 Read-only
81FH 1F0H TMR bits 255:224 Read-only820H 200H Interrupt Request Register 
(IRR); bits 31:0Read-only
821H 210H IRR bits 63:32 Read-only
822H 220H IRR bits 95:64 Read-only
823H 230H IRR bits 127:96 Read-only
824H 240H IRR bits 159:128 Read-only825H 250H IRR bits 191:160 Read-only
826H 260H IRR bits 223:192 Read-only
827H 270H IRR bits 255:224 Read-only828H 280H Error Status Register (ESR) Read/write WRMSR of a non-zero value causes 
#GP(0). See Section 11.5.3.
82FH 2F0H LVT CMCI register Read/write See Figure 11-8 for reserved bits.
830H
4300H and 310H Interrupt Command Register 
(ICR)Read/write See Figure 11-28 for reserved bits
832H 320H LVT Timer register Read/write See Figure 11-8 for reserved bits.
833H 330H LVT Thermal Sensor register Read/write See Figure 11-8 for reserved bits.834H 340H LVT Performance Monitoring 
registerRead/write See Figure 11-8 for reserved bits.
835H 350H LVT LINT0 register Read/write See Figure 11-8 for reserved bits.
836H 360H LVT LINT1 register Read/write See Figure 11-8 for reserved bits.
837H 370H LVT Error register Read/write See Figure 11-8 for reserved bits.
838H 380H Initial Count register (for 
Timer)Read/write
839H 390H Current Count register (for 
Timer)Read-only
83EH 3E0H Divide Configuration Register 
(DCR; for Timer)Read/write See Figure 11-10 for reserved bits.
83FH Not available SELF IPI
5Write-only Available only in x2APIC mode.
NOTES:
1. WRMSR causes #GP(0) for read-only registers.Table 11-6. Local APIC Register Address Map Supported by x2APIC (Contd.)
SemanticsComments11-40 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.12.1.3  Reserved Bit Checking
Section 11.12.1.2 and Table 11-6 specifies the reserved bit definitions for the APIC registers in x2APIC mode. Non-
zero writes (by WRMSR instruction) to reserved bits to these registers will raise a general protection fault exception while reads return zeros (RsvdZ semantics).
In x2APIC mode, the local APIC ID register is  increased to 32 bits wide. This enables 2
32–1 processors to be 
addressable in physical destination mode. This 32-bit value is referred to as “x2APIC ID”. A processor implementa-
tion may choose to support less than 32 bits in its hardware. System software should be agnostic to the actual number of bits that are implemented. All non-implem ented bits will return zeros on reads by software. 
The APIC ID value of FFFF_FFFFH and the highest value co rresponding to the implemented bit-width of the local 
APIC ID register in the system are reserved an d cannot be assigned to any logical processor. 
In x2APIC mode, the local APIC ID register is a read-only re gister to system software and will be initialized by hard-
ware. It is accessed via the RDMSR instruction reading the MSR at address 0802H. 
Each logical processor in the system (including clusters with a communication fabric) must be configured with an 
unique x2APIC ID to avoid collisions of x2APIC IDs. On DP  and high-end MP processors targeted to specific market 
segments and depending on the system configuration, it is possible that logical processors in different and “un-
connected” clusters power up initialized with overlappin g x2APIC IDs. In these configurations, a model-specific 
means may be provided in those product segments to enab le BIOS and/or platform firmware to re-configure the 
x2APIC IDs in some clusters to provide for unique and non-overlapping system wide IDs before configuring the 
disconnected components into a single system. 
11.12.2 x2APIC Register Availability
The local APIC registers can be accessed via the MSR interf ace only when the local APIC  has been switched to the 
x2APIC mode as described in Section 11.12.1. Accessing any APIC register in the MSR address range 0800H 
through 08FFH via RDMSR or WRMSR when the local APIC is not in x2APIC mode causes a general-protection 
exception. In x2APIC mode, the memory  mapped interface is not available and any access to the MMIO interface 
will behave similar to that of a legacy xAPIC in globally disabled state. Table 11-7 provides the interactions between 
the legacy & extended modes and the legacy and register interfaces.
11.12.3 MSR Access in x2APIC Mode
To allow for efficient access to the APIC registers in x2 APIC mode, the serializing semantics of WRMSR are relaxed 
when writing to the APIC registers. Thus, system softwa re should not use “WRMSR to APIC registers in x2APIC 
mode” as a serializing instruction. Read and write accesses to the APIC registers will occur in program order. A 
WRMSR to an APIC register may complete before all precedin g stores are globally visible; software can prevent this 
by inserting a serializing instruction or th e sequence MFENCE;LFENCE before the WRMSR.
The RDMSR instruction is not serializing and this behavior  is unchanged when reading APIC registers in x2APIC 
mode. System software accessing the APIC registers usin g the RDMSR instruction should not expect a serializing 
behavior. (Note: The MMIO-based xAPIC interface is mappe d by system software as an un-cached region. Conse-
quently, read/writes to the xAPIC-MMIO interface have serializing semantics in the xAPIC mode.)2. WRMSR causes #GP(0) for attemp ts to set a reserved bit to 1 in a read/write register (including bits 63:32 of each register).
3. RDMSR causes #GP(0) for write-only registers.
4. MSR 831H is reserved; read/write operations cause general-protection exceptions. The contents of the APIC register at MMIO o ffset 
310H are accessible in x2APIC mode through the MSR at address 830H.
5. SELF IPI register is supp orted only in x2APIC mode.
Table 11-7. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation
MMIO Interface MSR Interface
xAPIC mode Available General-protection exceptionx2APIC mode Behavior  identical to xAPIC in glob ally disabled state AvailableVol. 3A 11-41ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.12.4 VM-Exit Controls for MSRs and x2APIC Registers
The VMX architecture allows a VMM to specify lists of MSRs  to be loaded or stored on VMX transitions using the 
VMX-transition MSR areas (see VM-exit MSR-store address field, VM-exit MSR-load address field, and VM-entry MSR-load address field in Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C).
The X2APIC MSRs cannot to be loaded and stored on VMX transitions. A VMX transition fails if the VMM has speci-
fied that the transition should access any MSRs in the address range from 0000_0800H to 0000_08FFH (the range 
used for accessing the X2APIC registers). Specifically, proc essing of an 128-bit entry in any of the VMX-transition 
MSR areas fails if bits 31:0 of that entry (repre sented as ENTRY_LOW_DW) satisfies the expression: 
“ENTRY_LOW_DW & FFFFF800H = 00000800H”. Such a failure ca uses an associated VM entry to fail (by reloading 
host state) and causes an associated VM exit to lead to VMX abort.
11.12.5 x2APIC State Transitions
This section provides a detailed description of the x2APIC states of a local x2APIC unit, transitions between these 
states as well as interactions of these states with INIT and reset. 
11.12.5.1  x2APIC States
The valid states for a local x2APIC unit are listed in Table 11-5.
•APIC disabled: IA32_APIC_BASE[EN] =0 and IA32_APIC_BASE[EXTD]=0.
•xAPIC mode: IA32_APIC_BASE[EN]=1  and IA32_APIC_BASE[EXTD]=0.
•x2APIC mode: IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=1.
•Invalid: IA32_APIC_BASE[EN]=0 and IA32_APIC_BASE[EXTD]=1.
The state corresponding to EXTD=1 and EN=0 is not valid and it is not possible to get into this state. An execution 
of WRMSR to the IA32_APIC_BASE_MSR that attempts a transi tion from a valid state to this invalid state causes a 
general-protection exception. Figure 11-27 shows the co mprehensive state transition diagram for a local x2APIC 
unit.

unit. 
On coming out of reset, the local APIC unit is enab led and is in the xAPIC mo de: IA32_APIC_BASE[EN]=1 and 
IA32_APIC_BASE[EXTD]=0. The APIC re gisters are initialized as follows.
•The local APIC ID is initialized by hardware with a 32 bit ID (x2APIC ID). The lowest 8 bits of the x2APIC ID are 
the legacy local xAPIC ID, and are stored in the upper 8 bits of the APIC register for access in xAPIC mode.
•The following APIC registers are reset to all zeros for those fields that are defined in the xAPIC mode.
— IRR, ISR, TMR, ICR, LDR, TPR, Di vide Configuration Register (See Section 11.4 through Section 11.6 for 
details of individual APIC registers).
— Timer initial count and timer current count registers.
•The LVT registers are reset to 0s except for the mask bits; these are set to 1s.
•The Spurious Interrupt Vector Register is initialized to 000000FFH. 
•The DFR (available only in xAPIC mode) is reset to all 1s. 
•SELF IPI register is reset to zero.11-42 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
x2APIC After Reset
The valid transitions from the xAPIC mode state are:
•to the x2APIC mode by setting EXT to  1 (resulting EN=1, EXTD = 1). The physical x2APIC ID (see Figure 11-6) 
is preserved across this transition and the logical x2APIC ID (see Figure 11-29) is initialized by hardware during 
this transition as documented in Section 11.12.10.2. The state of the extended fields in other APIC registers, 
which was not initialized at reset, is not architecturally defined across this transition and system software 
should explicitly initialize those programmable APIC registers. 
•to the disabled state by setting EN  to 0 (resulting EN=0, EXTD= 0).
The result of an INIT in the xAPIC state places the APIC in the state with EN= 1, EXTD= 0. The state of the local 
APIC ID register is preserved (the 8-bit xAPIC ID is in th e upper 8 bits of the APIC ID register). All the other APIC 
registers are initialized as a result of INIT. 
A reset in this state places the APIC in the state with EN = 1, EXTD= 0. The state of the local APIC ID register is 
initialized as described in Section 11.12.5.1. All the ot her APIC registers are initialized described in Section 
11.12.5.1. 
x2APIC Transitions From x2APIC Mode
From the x2APIC mode, the on ly valid x2APIC transition using IA32_API C_BASE is to the state where the x2APIC 
is disabled by setting EN to 0 and EX TD to 0. The x2APIC ID (32 bits) and the legacy local xAPIC ID (8 bits) are 
preserved across this transition. A transition from the x2 APIC mode to xAPIC mode is not valid, and the corre-
sponding WRMSR to the IA32_APIC_BASE MSR causes a general-protection exception. 
A reset in this state places the x2APIC in xAPIC mode. All APIC registers (including the local APIC ID register) are 
initialized as described in Section 11.12.5.1. 
An INIT in this state keeps the x2APIC in the x2APIC mode. The state of the lo cal APIC ID register is preserved (all 
32 bits). However, all the other APIC registers are initialized as a result of the INIT transition.Figure 11-27.  Local x2APIC State Transi tions with IA32_APIC_BASE, INIT, and ResetxAPIC ModeEN =1Illegal
TransitionInit
EN=1, Extd=1ExtendedInvalid
State
ModeReset
Extd = 1
Illegal
Transition
EN = 0EN = 0 Illegal
Transition Extd = 0
Illegal
Extd = 0EN=1, Extd=0EN = 0
Extd = 1
ResetResetInit
InitDisabled
EN = 0
Extd = 0
Extd = 1
EN = 0Vol. 3A 11-43ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
x2APIC Transitions From Disabled Mode
From the disabled state, the only valid x2APIC transiti on using IA32_APIC_BASE is to the xAPIC mode (EN= 1, 
EXTD = 0). Thus the only means to transition from x2APIC mode to xAPIC mode is a two-step process: 
•first transition from x2APIC mode to loca l APIC disabled mode (EN= 0, EXTD = 0),
•followed by another transition from disabl ed mode to xAPIC mode (EN= 1, EXTD= 0).
Consequently, all the APIC register states in the x2APIC , except for the x2APIC ID (32 bits), are not preserved 
across mode transitions. 
A reset in the disabled state places the x2APIC in the xA PIC mode. All APIC registers (including the local APIC ID 
register) are initialized as described in Section 11.12.5.1. 
An INIT in the disabled state keeps the x2APIC in the disabled state.
State Changes From xAPIC Mode to x2APIC Mode
After APIC register states have been initialized by software in xAPIC mode, a transition from xAPIC mode to x2APIC 
mode does not affect most of the APIC register states, except the following:
•The Logical Destination Register is not preserved.
•Any APIC ID value written to the memory-mappe d local APIC ID register is not preserved.
•The high half of the Interrupt Command Register is not preserved. 
11.12.6 Routing of Device Interrupts in x2APIC Mode
The x2APIC architecture is intended to  work with all existing IOxAPIC units  as well as all PCI and PCI Express 
(PCIe) devices that support the capability for message-sign aled interrupts (MSI). Support for x2APIC modifies only 
•the local APIC units;
•the interconnects joining IOxAPIC units to the local APIC units; and
•the interconnects joining MSI-capable PCI an d PCIe devices to the local APIC units.
No modifications are required to MSI-capable PCI and PCIe devices. Similarly, no modifications are required to 
IOxAPIC units. This is made possible through use of the interrupt-remapping architecture specified in the Intel® 
Virtualization Technology for Directed I/O Specification, Re vision 1.3 and/or later versions, for the routing of inter-
rupts from MSI-capable devices to local APIC units operating in x2APIC mode.
11.12.7 Initialization by System Software
Routing of device interrupts to local APIC units operating in x2APIC mode requires use of the interrupt-remapping 
architecture specified in the Intel® Virtualization Technology for Directed I/O Specification (Revision 1.3 and/or 
later versions). Because of this, BIOS must enumerate support for and software must enable this interrupt remap-ping with Extended Interrupt Mode Enabled before it enabling x2APIC mode in the local APIC units.
The ACPI interfaces for the x2APIC are described in Sectio n 5.2, “ACPI System Description Tables,” of the Advanced 
Configuration and Power Interface Specification, Revi sion 4.0a (http://www.acpi.info/spec.htm). The default 
behavior for BIOS is to pass the control to the operating system with the local x2APICs in xAPIC mode if all APIC 
IDs reported by CPUID.0BH:EDX are less than 255, and in x2APIC mode if th ere are any logical processor reporting 
an APIC ID of 255 or greater.
11.12.8 CPUID Extensions An d Topology Enumeration
For Intel 64 and IA-32 processors that support x2APIC, a va lue of 1 reported by CPUID.01H:ECX[21] indicates that 
the processor supports x2APIC and the extend ed topology enumeration leaf (CPUID.0BH). 11-44 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The extended topology enumeration leaf can be accessed by  executing CPUID with EAX = 0BH. Processors that do 
not support x2APIC may support CPUID leaf 0BH. Software can detect the availability of the extended topology 
enumeration leaf (0BH) by performing two steps:
greater than or equal or 11 (0BH), then proceed to next step
•Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero. 
If both of the above conditions are true, extended topology enumeration leaf is available. If available, the extended 
topology enumeration leaf is the preferred mechanism fo r enumerating topology. The pr esence of CPUID leaf 0BH 
in a processor does not guarantee support for x2AP IC. If CPUID.EAX=0BH, ECX=0H:EBX returns zero and 
maximum input value for basic CPUID information is greate r than 0BH, then CPUID.0BH leaf is not supported on 
that processor.
The extended topology enumeration leaf is intended to assist software with enumerating processor topology on 
systems that requires 32-bit x2APIC IDs to address individu al logical processors. Details of CPUID leaf 0BH can be 
found in the reference pages of CPUID in Chapter 3 of Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2A.
Processor topology enumeration algorithm for processors supporting the extended topo logy enumeration leaf of 
CPUID and processors that do not support CPUID leaf 0B H are treated in Section 9. 9.4, “Algorithm for Three-
Domain Mappings of APIC_ID.”
11.12.8.1  Consistency of APIC IDs and CPUID
The consistency of physical x2APIC ID in MSR 802H  in x2APIC mode and the 32-bit value returned in 
CPUID.0BH:EDX is facilitate d by processor hardware. 
CPUID.0BH:EDX will report the full 32 bit ID, in xAPIC and x2APIC mode. This al lows BIOS to determine if a system 
has processors with IDs exceeding the 8-bit initial AP IC ID limit (CPUID.01H:EBX [31:24]). Initial APIC ID 
(CPUID.01H:EBX[31:24]) is always equal to CPUID.0BH:EDX[7:0].

(CPUID.01H:EBX[31:24]) is always equal to CPUID.0BH:EDX[7:0]. 
If the values of CPUID.0BH:EDX reported by all logical pr ocessors in a system are less than 255, BIOS can transfer 
control to OS in xAPIC mode.
If the values of CPUID.0BH:EDX reported by some logical pr ocessors in a system are greater than or equal to 255, 
BIOS must support two options to hand off to OS.
•If BIOS enables logical processors with x2APIC IDs greate r than 255, then it should enable x2APIC in the Boot 
Strap Processor (BSP) and all Application Processors (AP) before passing control to the OS. Applications 
requiring processor topology information must use OS provided services based on  x2APIC IDs or CPUID.0BH 
leaf.
•If a BIOS transfers control to OS in xAPIC mode, then th e BIOS must ensure that only logical processors with 
CPUID.0BH.EDX value less than 255 are enabled. BIOS  initialization on all logical processors with 
CPUID.0B.EDX values greater than or equal to 255 must  (a) disable APIC and execute CLI in each logical 
processor, and (b) leave these logical processor in the lowest power state so that these processors do not 
respond to INIT IPI during OS boot. The BSP and all th e enabled logical processor operate in xAPIC mode after 
BIOS passed control to OS. Application requiring proce ssor topology information can use OS provided legacy 
services based on 8-bit initial APIC IDs or legacy to pology information from CPUI D.01H and CPUID 04H leaves. 
Even if the BIOS passes control in xAPIC mode, an OS ca n switch the processors to x2APIC mode later. BIOS 
SMM handler should always read the APIC_BASE_MSR, determine the APIC mode and use the corresponding 
access method.
11.12.9 ICR Operation in x2APIC Mode
In x2APIC mode, the layout of the Interrupt Command Register is shown in Figure 11-28. The lower 32 bits of ICR in x2APIC mode is identical to the lower half of the IC R in xAPIC mode, except the Delivery Status bit is removed 
since it is not needed in x2APIC mode. The destinatio n ID field is expanded to 32 bits in x2APIC mode. 
To send an IPI using the ICR, software must set up the IC R to indicate the type of IPI message to be sent and the 
destination processor or processors. Self IPIs can also be  sent using the SELF IPI register (see Section 11.12.11). Vol. 3A 11-45ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
A single MSR write to the Interrupt Co mmand Register is required for dispat ching an interrupt in x2APIC mode. 
With the removal of the Delivery Status bit, system softwa re no longer has a reason to read the ICR. It remains 
readable only to aid in debugging; however, software sh ould not assume the value returned by reading the ICR is 
the last written value.
A destination ID value of FFFF_FFFFH is used for broadcast of interrupts in both logical destination and physical 
destination modes.
11.12.10 Determining IPI Destination in x2APIC Mode
11.12.10.1  Logical Destin ation Mode in x2APIC Mode
In x2APIC mode, the Logical Destination Register (LDR) is increased to 32 bits wide. It is a read-only register to 
system software. This 32-bit value is re ferred to as “logical x2APIC ID”. System software accesses this register via 
the RDMSR instruction reading the MSR at address 80DH. Fi gure 11-29 provides the layout of the Logical Destina-
tion Register in x2APIC mode. Figure 11-28.  Interrupt Command Register (ICR) in x2APIC Mode31 0
Reserved7
Vector
000: Fixed
001: Reserved00: No Shorthand
100: NMI
101: INIT
1: Logical
Level
1 = Assert
0: Edge
Destination Field
Address: 830H (63 - 0)
Value after Reset: 0HReserved20
 11-46 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
In the xAPIC mode, the Destination Format Register (DFR ) through the MMIO interface determines the choice of a 
flat logical mode or a clustered logical mode. Flat logi cal mode is not supported in the x2APIC mode. Hence the 
Destination Format Register (DFR) is eliminated in x2APIC mode. 
The 32-bit logical x2APIC ID field of LD R is partitioned into two sub-fields:
•Cluster ID (LDR[31:16]): is the address of the destination cluster
•Logical ID (LDR[15:0]): defines a logical ID of the indi vidual local x2APIC within the cluster specified by 
LDR[31:16]. 
This layout enables 2^16-1 clusters each with up to 16 un ique logical IDs - effectively providing an addressability 
of ((2^20) - 16) processors in logical destination mode. 
It is likely that processor implementations may choose to su pport less than 16 bits of the cluster ID or less than 16-
bits of the Logical ID in the Logical Destination Regist er. However system software should be agnostic to the 
number of bits implemented in the cluster ID and logica l ID sub-fields. The x2APIC hardware initialization will 
ensure that the appropriately initialized logical x2APIC IDs are available to system software and reads of non-
implemented bits return zero. This is a read-only register that software must read to determine the logical x2APIC 
ID of the processor. Specifically, software can apply a 16-bit mask to the lowest 16 bits of the logical x2APIC ID to 
identify the logical address of a processor within a cluste r without needing to know the number of implemented bits 
in cluster ID and Logical ID sub-fields. Similarly, software can create a message destination address for cluster model, by bit-Oring the Logical X2APIC ID (31:0) of  processors that have matching Cluster ID(31:16).
To enable cluster ID assignment in a fashion that matche s the system topology characteristics and to enable effi-
cient routing of logical mode lowest priority device in terrupts in link based platform interconnects, the LDR are 
initialized by hardware based on the valu e of x2APIC ID upon x2APIC state tran sitions. Details of this initialization 
are provided in Section 11.12.10.2. 
11.12.10.2  Deriving Logical x2AP IC ID from the Local x2APIC ID
In x2APIC mode, the 32-bit logical x2APIC ID, which can be  read from LDR, is derived from the 32-bit local x2APIC 
ID. Specifically, the 16-bit logical ID sub-field is derived by  shifting 1 by the lowest 4 bits of the x2APIC ID, i.e., 
Logical ID = 1 « x2APIC ID[3:0]. The remaining bits of the x2 APIC ID then form the cluster ID portion of the logical 
x2APIC ID: 
Logical x2APIC ID = [(x2APIC ID[19: 4] « 16) | (1 « x2APIC ID[3:0])]
The use of the lowest 4 bits in the x2APIC ID implies that  at least 16 APIC IDs are reserved for logical processors 
within a socket in multi-socket configurations. If more th an 16 APIC IDS are reserved for logical processors in a 
socket/package then multiple cluster IDs can exist within the package. 
The LDR initialization occurs whenever the x2 APIC mode is enabled (see Section 11.12.5).Figure 11-29.  Logical Destination Register in x2APIC ModeMSR Address: 80DH
31     0
Logical x2APIC IDVol. 3A 11-47ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
11.12.11 SELF IPI Register
SELF IPIs are used extensively by some system software. The x2APIC architecture introduces a new register inter-
face. This new register is dedicated to the purpose of se nding self-IPIs with the intent of enabling a highly opti-
mized path for sending self-IPIs. 
Figure 11-30 provides the layout of the SELF IPI register. System software only specifies the vector associated with 
the interrupt to be sent. The semantics of sending a self-IPI  via the SELF IPI register are identical to sending a self 
targeted edge triggered fixed interrupt with the specifie d vector. Specifically the semantics are identical to the 
following settings for an inter-processor interrupt sent via the ICR - Destination Shorthand (ICR[19:18] = 01 (Self)), Trigger Mode (ICR[15] = 0 (Edge)), Delivery Mo de (ICR[10:8] = 000 (Fixed)), Vector (ICR[7:0] = Vector).
The SELF IPI register is a write-only register. A RDMSR in struction with address of the SELF IPI register causes a 
general-protection exception. 
The handling and prioritization of a self-IPI sent via the SE LF IPI register is architecturally identical to that for an 
IPI sent via the ICR from a legacy xAPIC unit. Specifically  the state of the interrupt would be tracked via the Inter-
rupt Request Register (IRR) and In Service Register (ISR) and Trigger Mode Register (TMR) as if it were received 
from the system bus. Also sending the IPI via the Self Inte rrupt Register ensures that interrupt is delivered to the 
processor core. Specifically completion of the WRMSR instruction to the SELF IP I register implies that the interrupt 
has been logged into the IRR. As expected for edge tri ggered interrupts, depending on  the processor priority and 
readiness to accept interrupts, it is possible that interrupt s sent via the SELF IPI register or via the ICR with iden-
tical vectors can be combined.
11.13 APIC BUS MESSAGE FORMATS

This section describes the message formats used when tran smitting messages on the serial APIC bus. The informa-
tion described here pertains only to the Pentium and P6 family processors.
11.13.1 Bus Message Formats
The local and I/O APICs transmit three types of message s on the serial APIC bus: EOI message, short message, 
and non-focused lowest priority message. The purpose of  each type of message and its format are described 
below.
11.13.2 EOI Message
Local APICs send 14-cycle EOI messages to the I/O APIC to indicate that a level triggered interrupt has been accepted by the processor. This interrupt, in turn, is a result of software writing into the EOI register of the local 
APIC. Table 11-8 shows the cycles in an EOI message.Figure 11-30.  SELF IPI register
Table 11-8. EOI Message (14 Cycles)
Cycle Bit1 Bit0
1 1 1 11 = EOI2 ArbID3 0 Arbitration ID bits 3 through 0MSR Address: 083FH
31 8 7 0
Reserved Vector11-48 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The checksum is computed for cycles 6 through 9. It is a cumulative sum of the 2-bit (Bit1:Bit0) logical data values. 
The carry out of all but the last addition is added to the sum. If any APIC computes a different checksum than the 
one appearing on the bus in cycle 10, it signals an error, driving 11 on the APIC bus during cycle 12. In this case, 
the APICs disregard the message. The sending APIC will receive an appropriate error indication (see Section 
11.5.3, “Error Handling”) and resend the message. The status cycles are defined in Table 11-11.
11.13.2.1  Short Message
Short messages (21-cycles) are used for sending fixed, NMI,  SMI, INIT, start-up, ExtINT, and lowest-priority-with-
focus interrupts. Table 11-9 shows the cycles in a short message.3A r b I D 2 0
4A r b I D 1 0
5A r b I D 0 0
6 V7 V6 Interrupt vector V7 - V07V 5 V 4
8V 3 V 2
9V 1 V 0
10 C C Checksum for cycles 6 - 9
11 0 0
12 A A Status Cycle 013 A1 A1 Status Cycle 114 0 0 Idle
Table 11-9. Short Message (21 Cycles)
101 0  1  =  n o r m a l
2 ArbID3 0 Arbitration ID  bits 3 through 0
3A r b I D 20
4A r b I D 10
5A r b I D 006 DM M2 DM = Destination Mode 
7M 1 M 0 M 2 - M 0  =  D e l i v e r y  m o d e
8 L TM L = Level, TM = Trigger Mode9 V7 V6 V7-V0 = Interrupt Vector
10 V5 V4
11 V3 V212 V1 V0
13 D7 D6 D7-D0 = Destination
14 D5 D415 D3 D2
16 D1 D0Table 11-8. EOI Message (14 Cycles) (Contd.)
Cycle Bit1 Bit0Vol. 3A 11-49ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
If the physical delivery mode is being used, then cycles 15 and 16 represent the APIC ID and cycles 13 and 14 are 
considered don't care by the receiver. If the logical deliv ery mode is being used, then cycles 13 through 16 are the 
8-bit logical destination field. 
For shorthands of “all-incl-self” and “all-excl-self,” the ph ysical delivery mode and an arbitration priority of 15 
(D0:D3 = 1111) are used. The agent sending the message is  the only one required to distinguish between the two 
cases. It does so using internal information.
When using lowest priority delivery with an existing focus processor, the focus processor identifies itself by driving 
10 during cycle 19 and accepts the interrupt. This is an in dication to other APICs to terminate arbitration. If the 
focus processor has not been found, the short message is extended on-the-fly to the non-focused lowest-priority 
message. Note that except for the EOI message, messages generating a checksum or an acceptance error (see Section 11.5.3, “Error Handling”) terminate after cycle 21.
11.13.2.2  Non-focused Lowest Priority Message
These 34-cycle messages (see Table 11-10) are used in the lowest priority delivery mode when a focus processor 
is not present. Cycles 1 through 20 are same as for the short message. If during the status cycle (cycle 19) the state of the (A:A) flags is 10B, a focus processor has be en identified, and the short message format is used (see 
Table 11-9). If the (A:A) flags are set to 00B, lowest prio rity arbitration is started and the 34-cycles of the non-
focused lowest priority message are competed. For other co mbinations of status flags, refer to Section 11.13.2.3, 
“APIC Bus Status Cycles.”17 C C Checksum for cycles 6-16
18 0 0
19 A A Status cycle 0
20 A1 A1 Status cycle 121 0 0 Idle
Table 11-10. Non-Focused Lowest Priority Message (34 Cycles)
Cycle Bit0 Bit1
10  1 0  1  =  n o r m a l
2 ArbID3 0 Arbitration ID bits 3 through 0
3A r b I D 204A r b I D 10
5A r b I D 00
6 DM M2 DM = Destination mode 7 M1 M0 M2-M0 = Delivery mode
8 L TM L = Level, TM = Trigger Mode
9 V7 V6 V7-V0 = Interrupt Vector
10 V5 V4
11 V3 V2
12 V1 V013 D7 D6 D7-D0 = Destination
14 D5 D4
15 D3 D216 D1 D0Table 11-9. Short Message (21 Cycles) (Contd.)
Cycle Bit1 Bit011-50 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Cycles 21 through 28 are used to arbitrate for the lowest pr iority processor. The processo rs participating in the arbi-
tration drive their inverted processor priority on the bus. Only the local APICs having free interrupt slots participate 
in the lowest priority arbitration. If no  such APIC exists, the message will be rejected, requiring it to be tried at a 
later time.
Cycles 29 through 32 are also used for arbitration in case two or more processors have the same lowest priority. In 
the lowest priority delivery mode, all combinations of errors  in cycle 33 (A2 A2) will set the “accept error” bit in the 
error status register (see Figure 11-9). Arbitration priority  update is performed in cycle 20, and is not affected by 
errors detected in cycle 33. Only the local APIC that wins in  the lowest priority arbitration, drives cycle 33. An error 
in cycle 33 will force the sender to resend the message.
11.13.2.3  APIC Bus Status Cycles
Certain cycles within an APIC bus message are status cycles. During these cycles the status flags (A:A) and 
(A1:A1) are examined. Table 11-11 shows how these stat us flags are interpreted, depending on the current 
delivery mode and existence of a focus processor.17 C C Checksum for cycles 6-16
18 0 0
20 A1 A1 Status cycle 121 P7 0 P7 - P0 = Inverted Processor Priority
22 P6 0
23 P5 024 P4 0
25 P3 0
26 P2 027 P1 028 P0 0
29 ArbID3 0 Arbitration ID 3 -0 
30 ArbID2 031 ArbID1 0
32 ArbID0 0
33 A2 A2 Status Cycle34 0 0 IdleTable 11-10. Non-Focused Lowest Pr iority Message (34 Cycles) (Contd.)
Cycle Bit0 Bit1Vol. 3A 11-51ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 11-11. APIC Bus Status Cycles Interpretation
Delivery
ModeA Status A1 Status A2 Status Update ArbID 
and Cycle#Message 
LengthRetry
EOI 00: CS_OK 10: Accept XX: Yes, 13 14 Cycle No
00: CS_OK 11: Retry XX: Yes, 13 14 Cycle Yes00: CS_OK 0X: Accept Error XX: No 14 Cycle Yes11: CS_Error XX: XX: No 14 Cycle Yes10: Error XX: XX: No 14 Cycle Yes01: Error XX: XX: No 14 Cycle Yes
Fixed 00: CS_OK 10: Accept XX: Yes, 20 21 Cycle No
00: CS_OK 11: Retry XX: Yes, 20 21 Cycle Yes00: CS_OK 0X: Accept Error XX: No 21 Cycle Yes11: CS_Error XX: XX: No 21 Cycle Yes10: Error XX: XX: No 21 Cycle Yes01: Error XX: XX: No 21 Cycle Yes
NMI, SMI, INIT, 
ExtINT,
Start-Up00: CS_OK 10: Accept XX: Yes, 20 21 Cycle No
Lowest 00: CS_OK, NoFocus 11: Do Lowest 10: Accept Yes, 20 34 Cycle No
00: CS_OK, NoFocus 11: Do Lowest 11: Error Yes, 20 34 Cycle Yes
00: CS_OK, NoFocus 11: Do Lowest 0X: Error Yes, 20 34 Cycle Yes
00: CS_OK, NoFocus 10: End and Retry XX: Yes, 20 34 Cycle Yes
00: CS_OK, NoFocus 0X: Error XX: No 34 Cycle Yes10: CS_OK, Focus XX: XX: Yes, 20 34 Cycle No11: CS_Error XX: XX: No 21 Cycle Yes01: Error XX: XX: No 21 Cycle Yes11-52 Vol. 3AADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Vol. 3A 12-1CHAPTER 12
This chapter describes the memory cache and cache contro l mechanisms, the TLBs, and the store buffer in Intel 64 
and IA-32 processors. It also describes the memory type  range registers (MTRRs) introduced in the P6 family 
processors and how they are used to control caching of physical memory locations.
12.1 INTERNAL CACHES, TLBS, AND BUFFERS
The Intel 64 and IA-32 architectures support cache, transl ation look aside buffers (TLBs), and a store buffer for 
temporary on-chip (and external) storage of instructions  and data. (Figure 12-1 shows the arrangement of caches, 
TLBs, and the store buffer for the Pentium 4 and Intel Xeon processors.) Table 12-1 shows the characteristics of 
these caches and buffers for the Pentium 4, In tel Xeon, P6 family, and Pentium processors. The sizes and char-
acteristics of these units are machine specific and may change in future versions of the processor.  The 
CPUID instruction returns the sizes and characteristics of the caches and buffers for the processor on which the 
instruction is executed. See “CPUID—CPU Identification” in  Chapter 3, “Instruction Se t Reference, A-L,” of the

instruction is executed. See “CPUID—CPU Identification” in  Chapter 3, “Instruction Se t Reference, A-L,” of the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
Figure 12-1.  Cache Structure of th e Pentium 4 and Intel Xeon ProcessorsTrace Cache Instruction DecoderBus Interface UnitSystem Bus
Data Cache
Unit (L1) (External)Physical
Memory
Store BufferData TLBsL2 Cache
TLBsL3 Cache†
† Intel Xeon processors only12-2 Vol. 3AMEMORY CACHE CONTROL
Figure 12-2 shows the cache arrangement of Intel Core i7 processor.Figure 12-2.  Cache Structure of  the Intel Core i7 Processors
Table 12-1.  Characteristics of th e Caches, TLBs, Store Buffer, and 
Write Combining Buffer in In tel 64 and IA-32 Processors
Cache or Buffer Characteristics
Trace Cache1• Pentium 4 and Intel Xeon processors (Based  on Intel NetBurst® microarchitecture): 12 K μops, 8-way set 
associative.
• Intel Core i7, Intel Core 2 Duo, Intel Atom, Intel Core Duo, Intel Core Solo, Pentium M processor: not 
• P6 family and Pentium processors: not implemented.
L1 Instruction Cache • Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): not implemented.
• Intel Core i7 processor: 32- KByte, 4-way set associative.
• Intel Core 2 Duo, Intel Atom, Intel Core Duo, Intel Core Solo, Pentium M processor: 32-KByte, 8-way set 
• P6 family and Pentium processors: 8- or 16-KByte, 4-wa y set associative, 32-byte cache line size; 2-way set 
associative for earlier Pentium processors.
L1 Data Cache • Pentium 4 and Intel Xeon processors (Based on Intel NetBurst microarchitecture): 8-KByte, 4-way set 
associative, 64-byte cache line size.
• Pentium 4 and Intel Xeon processo rs (Based on Intel NetBurst microarchitecture): 16-KByte, 8-way set 
• Intel Atom processors: 24-KByte, 6-way se t associative, 64-byte cache line size.
• Intel Core i7, Intel Core 2 Duo, Intel Core Duo, Intel Core Solo, Pentium M and Intel Xeon processors: 32-
KByte, 8-way set associative,  64-byte cache line size.
• P6 family processors: 16-KByte, 4-way set associat ive, 32-byte cache line size; 8-KBytes, 2-way set 
associative for earlier P6 family processors.
• Pentium processors: 16-KByte, 4- way set associative, 32 -byte cache line size ; 8-KByte, 2-way set 
associative for earlier Pentium processors.Instruction Decoder and front end
Out-of-Order EngineChipset
Data Cache
Unit (L1)Instruction
Cache
STLBData TLB
L2 CacheITLB
L3 CacheIMCQPIVol. 3A 12-3MEMORY CACHE CONTROL
L2 Unified Cache • Intel Core 2 Duo and Intel Xeon processors: up  to 4-MByte (or 4MBx2 in quadcore processors), 16-way set 
associative, 64-byte  cache line size.
• Intel Core 2 Duo and Intel Xeon processors: up to 6- MByte (or 6MBx2 in quadcore processors), 24-way set 
• Intel Core i7, i5, i3 processors: 256KBbyte, 8-way set associative, 64- byte cache line size.
• Intel Atom processors: 512-KByte, 8-way se t associative, 64-byte  cache line size.
• Intel Core Duo, Intel Core Solo processors: 2-MByt e, 8-way set associative, 64-byte cache line size 
• Pentium 4 and Intel Xeon processors: 256, 512, 1024, or 2048-KByte, 8-way set associative, 64-byte cache 
line size, 128-byte sector size.
• Pentium M processor: 1 or 2-MByte, 8-way set associative, 64-byte cache line size.
• P6 family processors: 128-KByte, 256-KByte, 512-KByte, 1-MByte, or 2-MByte, 4-way set associative, 
32-byte cache line size.
• Pentium processor (external optional): System specif ic, typically 256- or 512-KByte, 4-way set associative, 
L3 Unified Cache • Intel Xeon processors: 512-KByte, 1-MByte, 2- MByte, or 4-MByte, 8-way set as sociative, 64-byte cache line 
size, 128-byte sector size.
• Intel Core i7 processor, Intel Xeon processor 5500: Up to 8MByte, 16-way set associative, 64-byte cache 
line size.
• Intel Xeon processor 5600: Up to 12MByte, 64-byte cache line size.
• Intel Xeon processor 7500: Up to 24MByte, 64-byte cache line size.
Instruction TLB
(4-KByte Pages)• Pentium 4 and Intel Xeon processors (Based on Inte l NetBurst microarchitectur e): 128 entries, 4-way set 
• Intel Atom processors: 32-entries, fully associative.
• Intel Core i7, i5, i3 processors: 64-entries per th read (128-entries per core), 4-way set associative.
• Intel Core 2 Duo, Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128 entries, 4-way set 
• P6 family processors: 32 entries, 4-way set associative.• Pentium processor: 32 entries, 4-wa y set associative; fully set associat ive for Pentium processors with MMX 
Data TLB (4-KByte 
Pages)• Intel Core i7, i5, i3 processors, DT LB0: 64-entries, 4- way set associative.
• Intel Core 2 Duo processors: DTLB0, 16  entries, DTLB1, 256 entries, 4 ways.
• Intel Atom processors: 16-entry-per-thread micro- TLB, fully associative; 64-entry DTLB, 4-way set 
associative; 16-entry PDE cache, fully associative.
• Pentium 4 and Intel Xeon processors (Based on In tel NetBurst microarchitect ure): 64 entry, fully set 
associative, shared wi th large page DTLB.
• Intel Core Duo, Intel Core Solo processors, Pent ium M processor: 128 entrie s, 4-way set associative.
• Pentium and P6 family processors: 64 entries, 4-way set a ssociative; fully set, associative for Pentium 
processors with MMX technology.
Instruction TLB 
(Large Pages)• Intel Core i7, i5, i3 processors: 7- entries per thread, fully associative.
• Intel Core 2 Duo processors: 4 entries, 4 ways.
• Pentium 4 and Intel Xeon processors: large pages are fragmented.
• Intel Core Duo, Intel Core Solo, Pentium M processor: 2 entrie s, fully associative.
• P6 family processors: 2 en tries, fully associative.
• Pentium processor: Uses same TLB as used for 4-KByte pages.
Data TLB (Large 
Pages)• Intel Core i7, i5, i3 processors, DT LB0: 32-entries, 4- way set associative.
• Intel Core 2 Duo processors: DTLB0, 16  entries, DTLB1, 32 entries, 4 ways.
• Intel Atom processors: 8 entries, 4-way set associative.
• Pentium 4 and Intel Xeon pr ocessors: 64 entries, fully  set associative; shared with small page data TLBs.
• Intel Core Duo, Intel Core Solo, Pentium M processor: 8 entrie s, fully associative.
• P6 family processors: 8 entr ies, 4-way set associative.
• Pentium processor: 8 entries, 4-wa y set associative; uses same TLB as used for 4-KByte pages in Pentium 
Second-level Unified 
TLB (4-KByte 
Pages)• Intel Core i7, i5, i3 processor, ST LB: 512-entries, 4-way set associative.Table 12-1.  Characteristics of th e Caches, TLBs, Store Buffer, and 
Write Combining Buffer in Intel 64 and IA-32 Processors (Contd.)
Cache or Buffer Characteristics12-4 Vol. 3AMEMORY CACHE CONTROL
Intel 64 and IA-32 processors may implement four types of  caches: the trace cache, the level 1 (L1) cache, the 
level 2 (L2) cache, and the level 3 (L3) cache. Se e Figure 12-1. Cache availability is described below:
•Intel Core i7, i5, i3 processor fa mily and Intel Xeon processor fami ly based on Nehalem microarchi-
tecture and Westmere  microarchitecture — The L1 cache is divided into two sections: one section is 
dedicated to caching instructions (pre-decoded instru ctions) and the other caches data. The L2 cache is a 
unified data and instruction cache. Each processor core has its own L1 and L2. The L3 cache is an inclusive, 
unified data and instruction cache, shared by all proce ssor cores inside a physical package. No trace cache is 
•Intel® Core™ 2 processor family and Intel® Xeon® processor family  based on Intel® Core™ micro-
architecture — The L1 cache is divided into two sections: one section is dedicated to caching instructions (pre-
decoded instructions) and the other caches data. The L2 cache is a unified data and instruction cache located 
on the processor chip; it is shared between two proc essor cores in a dual-core processor implementation. 
Quad-core processors have two L2, each shared by two processor cores. No trace cache is implemented.
•Intel Atom® processor — The L1 cache is divided into two sections: one section is dedicated to caching 
instructions (pre-decoded instructions) and the other caches data. The L2 cache is a unified data and instruction cache is located on the processor chip. No trace cache is implemented.
•Intel® Core™ Solo and Intel® Core™ Duo processors  — The L1 cache is divided into two sections: one 
section is dedicated to caching instructions (pre-decoded  instructions) and the other caches data. The L2 cache 
is a unified data and instruction cache located on the processor chip. It is shared between two processor cores in a dual-core processor implementati on. No trace cache is implemented.
•Pentium® 4 and Intel® Xeon® processors Based on Intel NetBurst® microarchitecture — The trace 
cache caches decoded instructions ( μops) from the instruction decoder and the L1 cache contains data. The L2 
and L3 caches are unified data and instruction caches located on the processor chip. Dualcore processors have two L2, one in each processor core. Note that the L3 ca che is only implemented on some Intel Xeon processors.

•P6 family processors  — The L1 cache is divided into two sections: one dedicated to caching instructions (pre-
decoded instructions) and the other to caching data. Th e L2 cache is a unified data and instruction cache 
located on the processor chip. P6 family processors do not implement a trace cache.
•Pentium® processors — The L1 cache has the same structure as on P6 family processors. There is no trace 
cache. The L2 cache is a unified data and instruction cache external to the processor chip on earlier Pentium 
processors and implemented on the processor chip in later Pentium processors. For Pentium processors where 
the L2 cache is external to the processor, access to the cache is through the system bus.
For Intel Core i7 processors and processors based on Inte l Core, Intel Atom, and Intel NetBurst microarchitectures, 
Intel Core Duo, Intel Core Solo and Pentium M processors, the cache lines for the L1 and L2 caches (and L3 caches if supported) are 64 bytes wide. The processor always read s a cache line from system memory beginning on a 64-
byte boundary. (A 64-byte aligned cache line begins at an address with its 6 least-significant bits clear.) A cache Store Buffer • Intel Core i7, i5, i3 processors: 32entries.
• Intel Core 2 Duo processors: 20 entries.• Intel Atom processors: 8 entries, used for both WC and store buffers.
• Pentium 4 and Intel Xeon  processors: 24 entries.
• Pentium M processor: 16 entries.• P6 family processors: 12 entries.
• Pentium processor: 2 buffers, 1 entry each (Pentium processors with MMX techno logy have 4 buffers for 4 
entries).
Write Combining 
(WC) Buffer• Intel Core 2 Duo processors: 8 entries.
• Intel Atom processors: 8 entries, used for both WC and store buffers.
• Pentium 4 and Intel Xeon processors: 6 or 8 entries.
• Intel Core Duo, Intel Core Solo, Pentium M processors: 6 entries.
• P6 family processors: 4 entries.
NOTES:
1 Introduced to the IA-32 arch itecture in the Pentium 4 and Intel Xeon processors.Table 12-1.  Characteristics of th e Caches, TLBs, Store Buffer, and 
Cache or Buffer CharacteristicsVol. 3A 12-5MEMORY CACHE CONTROL
line can be filled from memory with a 8-transfer burst tr ansaction. The caches do not support partially-filled cache 
lines, so caching even a single doubleword requires caching an entire line.
The L1 and L2 cache lines in the P6 family and Pentium pr ocessors are 32 bytes wide, with cache line reads from 
system memory beginning on a 32-byte boundary (5 least-significant bits of a memory address clear.) A cache line can be filled from memory with a 4-transfer burst transaction. Partially-filled cache lines are not supported.
The trace cache in processors based on Intel NetBurst microarchitecture is available in all execution modes: 
protected mode, system management mode (SMM), and re al-address mode. The L1,L2, and L3 caches are also 
available in all execution modes; however, use of them  must be handled carefully in SMM (see Section 32.4.2, 
“SMRAM Caching”).
The TLBs store the most recently used page-directory and page-table entries. They speed up memory accesses 
when paging is enabled by reducing th e number of memory accesses that ar e required to read the page tables 
stored in system memory. The TLBs are divided into four groups: instruction TLBs for 4-KByte pages, data TLBs for 
4-KByte pages; instruction TLBs for large pages (2-MByte , 4-MByte or 1-GByte pages), and data TLBs for large 
pages. The TLBs are normally active on ly in protected mode with paging enabled. When paging is disabled or the 
processor is in real-address mode, the TLBs maintain their co ntents until explicitly or implicitly flushed (see Section 
12.9, “Invalidating the Translation Lookaside Buffers (TLBs)”).
Processors based on Intel Core microarchitectures implem ent one level of instruction TLB and two levels of data 
TLB. Intel Core i7 processor provides a second-level unified TLB. 
The store buffer is associated with the processors instruction execution units. It allows writes to system memory 
and/or the internal caches to be saved and in some case s combined to optimize the processor’s bus accesses. The 
store buffer is always enabled in all execution modes.
The processor’s caches are for the most part transparent to software. When enabled, instructions and data flow 
through these caches without the need fo r explicit software control. However, knowledge of the behavior of these 
caches may be useful in optimizing software performa nce. For example, knowledge of cache dimensions and 
replacement algorithms gives an indication of how large of  a data structure can be operated on at once without 
causing cache thrashing.
In multiprocessor systems, maintenance of cache consistenc y may, in rare circumstances, require intervention by 
system software. For these rare cases, the processor provides privileged cache control instructions for use in 
flushing caches and forcing memory ordering.
There are several instructions that software can use to  improve the performance of the L1, L2, and L3 caches, 
including the PREFETCHh, CLFLUSH, and CLFLUSHOPT in structions and the non-temporal move instructions 
(MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD). Th e use of these instructions are discussed in Section 
12.5.5, “Cache Management Instructions.”
12.2 CACHING TERMINOLOGY
IA-32 processors (beginning with the Pentium processor) and Intel 64 processors use the MESI (modified, exclu-
sive, shared, invalid) cache protocol to maintain consistency with internal caches and caches in other processors 
(see Section 12.4, “Cache Control Protocol”).
When the processor recognizes that an operand being re ad from memory is cacheable, the processor reads an 
entire cache line into the appropriate cache (L1,  L2, L3, or all). This operation is called a cache line fill . If the 
memory location containing that operand is still cach ed the next time the processor attempts to access the 
operand, the processor can read the operand from the cach e instead of going back to memory. This operation is 
called a cache hit . 
When the processor attempts to write an operand to a cacheable area of memory, it first checks if a cache line for 
that memory location exists in the cache. If a valid ca che line does exist, the processor (depending on the write 
policy currently in force) can write the operand into the cache instead of writing it out to system memory. This 
operation is called a write hit . If a write misses the cache (that is, a valid cache line is not present for area of 
memory being written to), the processor performs a cache line  fill, write allocation. Then it writes the operand into 
the cache line and (depending on the write policy currently in force) can also write it out to memory. If the operand 
is to be written out to memory, it is written first into the store buffer, and then written from the store buffer to 
memory when the system bus is available. (Note that for the Pentium processor, write misses do not result in a 
cache line fill; they always result in a write to memory. For this processor, only read misses result in cache line fills.)12-6 Vol. 3AMEMORY CACHE CONTROL
When operating in an MP system, IA-32 processors (beginni ng with the Intel486 processor) and Intel 64 processors 
have the ability to snoop  other processor’s accesses to system memory and to their internal caches. They use this 
snooping ability to keep their internal caches consistent both with system memory and with the caches in other 
processors on the bus. For example, in the Pentium and P6 family processors, if through snooping one processor 
detects that another processor intends to write to a memory location that it currently has cached in shared state , 
the snooping processor will invalidate its cache line forcing it  to perform a cache line fill the next time it accesses 
the same memory location. 
Beginning with the P6 family processors, if a processor detects (through snooping) that another processor is trying 
to access a memory location that it has modified in its cache, but has not yet written back to system memory, the 
snooping processor will signal the other processor (by means of the HITM# signal) that the cache line is held in modified state and will perform an imp licit write-back of the modified data. The implicit write-back is transferred 
directly to the initial requesting processor and snooped by the memory controller to assure that system memory 
has been updated. Here, the processor with the valid data  may pass the data to the other processors without actu-
ally writing it to system memory; however, it is the responsibility of the memory controller to snoop this operation 
and update memory.
12.3 METHODS OF CACHING AVAILABLE
The processor allows any area of system memory to be cach ed in the L1, L2, and L3 caches. In individual pages or 
regions of system memory, it allows the type of caching (also called memory type ) to be specified (see Section 
12.5). Memory types currently defined for the Intel 64 and IA-32 architectures are (see Table 12-2):

•Strong Uncacheable (UC) —System memory locations are not cached. All reads and writes appear on the 
system bus and are executed in program order withou t reordering. No speculative memory accesses, page-
table walks, or prefetches of speculated branch target s are made. This type of cache-control is useful for 
memory-mapped I/O devices. When used with normal RAM, it greatly reduces processor performance.
NOTE
The behavior of x87 and SIMD instructions refere ncing memory is implementation dependent. In 
some implementations, accesses to UC memory may occur more than once. To ensure predictable 
behavior, use loads and stores of general purpose registers to access UC memory that may have 
read or write side effects.
•Uncacheable (UC-) — Has same characteristics as the strong uncacheable (UC) memory type, except that 
this memory type can be overridden by programming th e MTRRs for the WC memory type. This memory type 
is available in processor families starting from the Pentium III processors and can only be selected through the 
PAT.Table 12-2.  Memory Types and Their Properties
Memory Type and 
MnemonicCacheable Writeback 
CacheableAllows
Speculative 
ReadsMemory Ordering Model
Strong Uncacheable 
(UC)No No No Strong Ordering
Uncacheable (UC-) No No No Strong Ordering. Can only be selected through the PAT. Can be 
overridden by WC in MTRRs.
Write Combining (WC) No No Yes Weak Ordering. Availa ble by programming MTRRs or by selecting it 
through the PAT.
Write Through (WT) Yes No Yes Spec ulative Processor Ordering.
Write Back (WB) Yes Yes Yes Speculative Processor Ordering.
Write Protected (WP) Yes for 
reads; no for 
writesNo Yes Speculative Processor Ordering . Available by programming MTRRs.Vol. 3A 12-7MEMORY CACHE CONTROL
•Write Combining (WC) — System memory locations are not cach ed (as with uncacheable memory) and 
coherency is not enforced by the processor’s bus cohe rency protocol. Speculative reads are allowed. Writes 
may be delayed and combined in the write combining buff er (WC buffer) to reduce memory accesses. If the WC 
buffer is partially filled, the writes may be delayed until the next occurrence of a serializing event; such as an 
SFENCE or MFENCE instruction, CPUID or other serializing instruction, a re ad or write to uncached memory, an 
interrupt occurrence, or an execution of a LOCK instruction (including one with an XACQUIRE or XRELEASE 
prefix). In addition, an execution of the XEND instructio n (to end a transactional region) evicts any writes that 
were buffered before the corresponding execution of th e XBEGIN instruction (to begin the transactional region) 
before evicting any writes that were pe rformed inside the transactional region.
This type of cache-control is appropriate for video fram e buffers, where the order of writes is unimportant as 
long as the writes update memory so they can be seen  on the graphics display. See Section 12.3.1, “Buffering 
of Write Combining Memory Locations,” for more inform ation about caching the WC memory type. This memory 
type is available in the Pentium Pro and Pentium II processors by programming the MTRRs; or in processor 
families starting from the Pentium III processors by programming the MTRRs or by selecting it through the PAT.
•Write-through (WT) — Writes and reads to and from system memory are cached. Reads come from cache 
lines on cache hits; read misses cause cache fills. Speculative reads are allowed. All writes are written to a 
cache line (when possible) and through to system me mory. When writing through to memory, invalid cache 
lines are never filled, and valid cache lines are either fille d or invalidated. Write combining is allowed. This type 
of cache-control is appropriate for frame buffers or when there are devices on the system bus that access 
system memory, but do not perform snooping of memory accesses. It enforces coherency between caches in 
the processors and system memory.
•Write-back (WB) — Writes and reads to and from system memo ry are cached. Reads come from cache lines 
on cache hits; read misses cause cache fills. Speculative reads are allowed. Write misses cause cache line fills 
(in processor families starting with the P6 family proce ssors), and writes are performed entirely in the cache, 
when possible. Write combining is allowed. The write- back memory type reduces bus traffic by eliminating 
many unnecessary writes to system memory. Writes to a cache line are not immediately forwarded to system 
memory; instead, they are accumulated in the cache. Th e modified cache lines are written to system memory 
later, when a write-back operation is performed. Write- back operations are triggered when cache lines need to 
be deallocated, such as when new cache lines are being a llocated in a cache that is already full. They also are 
triggered by the mechanisms used to maintain cache cons istency. This type of cache-control provides the best 
performance, but it requires that all devices that acce ss system memory on the syst em bus be able to snoop 
memory accesses to ensure system memory and cache coherency.
•Write protected (WP) —  Reads come from cache lines when possi ble, and read misses cause cache fills. 
Writes are propagated to the system bus and cause corre sponding cache lines on all processors on the bus to 
be invalidated. Speculative reads are allowed. This memory  type is available in processor families starting from 
the P6 family processors by programming the MTRRs (see Table 12-6).
Table 12-3 shows which of these caching methods are ava ilable in the Pentium, P6 Family, Pentium 4, and Intel 
Xeon processors.
Table 12-3.  Methods of Caching Available in Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, 
Intel Xeon, P6 Family, and Pentium Processors
Memory Type Intel Core 2 Duo, Intel Atom, Intel Core Duo, 
Pentium M, Pentium 4 and Intel Xeon ProcessorsP6 Family 
ProcessorsPentium 
Processor
Strong Uncacheable (UC) Yes Yes Yes
Uncacheable (UC-) Yes Yes* No
Write Combining (WC) Yes Yes NoWrite Through (WT) Yes Yes Yes
Write Back (WB) Yes Yes Yes
Write Protected (WP) Yes Yes NoNOTE:
* Introduced in the Pentium III processor; not available in the Pentium Pro or Pentium II processors12-8 Vol. 3AMEMORY CACHE CONTROL
12.3.1 Buffering of Write Combining Memory Locations
Writes to the WC memory type are not cached in the typi cal sense of the word cached. They are retained in an 
internal write combining buffer (WC buffe r) that is separate from the internal L1, L2, and L3 caches and the store 
buffer. The WC buffer is not snooped and thus does not pr ovide data coherency. Buffering of writes to WC memory 
is done to allow software a small window of time to supply  more modified data to the WC buffer while remaining as 
non-intrusive to software as possible. The buffering of writ es to WC memory also causes data to be collapsed; that 
is, multiple writes to the same memory location will leave the last data written in the location and the other writes 
will be lost.
The size and structure of the WC buffer is not architectu rally defined. For the Intel Core 2 Duo, Intel Atom, Intel 
Core Duo, Pentium M, Pentium 4 and Intel Xeon processo rs; the WC buffer is made up of several 64-byte WC 
buffers. For the P6 family processors, the WC bu ffer is made up of several 32-byte WC buffers. 
When software begins writing to WC memory, the processo r begins filling the WC buffers one at a time. When one 
or more WC buffers has been filled, the processor has th e option of evicting the bu ffers to system memory. The 
protocol for evicting the WC buffers is implementation dependent and should not be relied on by software for 
system memory coherency. When using the WC memory type, software must  be sensitive to the fact that the 
writing of data to system memory is being delayed and must  deliberately empty the WC buffers when system 
memory coherency is required.
Once the processor has started to evict data from the WC buffer into system memory, it will make a bus-transaction 
style decision based on how much of the buffer contains va lid data. If the buffer is full (for example, all bytes are 
valid), the processor will execute a burst-write transaction on  the bus. This results in a ll 32 bytes (P6 family proces-
sors) or 64 bytes (Pentium 4 and more recent processor) be ing transmitted on the data bus in a single burst trans-
action. If one or more of the WC buffer’s bytes are invalid  (for example, have not been written by software), the 
processor will transmit the data to memory using “partial write” transactions (one chunk at a time, where a “chunk” 
is 8 bytes). 
This will result in a maximum of 4 partial write transactions (for P6 family processors) or 8 partial write transactions 
(for the Pentium 4 and more recent processors) for one WC buffer of data sent to memory. 
The WC memory type is weakly ordered by definition. Once the eviction of a WC buffer has started, the data is

The WC memory type is weakly ordered by definition. Once the eviction of a WC buffer has started, the data is 
subject to the weak ordering semantics of its definition. Ordering is not maintained between the successive alloca-
tion/deallocation of WC buffers (for example, writes to WC buffer 1 followed by writes to WC buffer 2 may appear 
as buffer 2 followed by buffer 1 on the system bus). When a WC buffer is evicted to memory as partial writes there 
is no guaranteed ordering between successive partial writ es (for example, a partial write for chunk 2 may appear 
on the bus before the partial write for chunk 1 or vice versa). 
The only elements of WC propagation to the system bus that are guaranteed are those provided by transaction 
atomicity. For example, with a P6 family processor, a co mpletely full WC buffer will always be propagated as a 
single 32-bit burst transaction using any chunk order. In a WC buffer eviction where data will be evicted as partials, 
all data contained in the same chunk (0 mod 8 aligned) will be propagated simultaneously. Likewise, for more 
recent processors starting with those based on Intel NetB urst microarchitectures, a full WC buffer will always be 
propagated as a single burst transactions, using any chunk  order within a transaction. For partial buffer propaga-
tions, all data contained in the same chunk will be propagated simultaneously.
12.3.2 Choosing a Memory Type
The simplest system memory model does not use memory-m apped I/O with read or write side effects, does not 
include a frame buffer, and uses the write-back memory type for all memory. An I/O agent can perform direct 
memory access (DMA) to write-back memory and the cache protocol maintains cache coherency.
A system can use strong uncacheable memory for other memory-mapped I/O, and should always use strong unca-
cheable memory for memory-mapped I/O with read side effects.
Dual-ported memory can be considered a write side effect , making relatively prompt writes desirable, because 
those writes cannot be observed at the other port until they reach the memory agent. A system can use strong 
uncacheable, uncacheable, write-through, or write-comb ining memory for frame buffers or dual-ported memory 
that contains pixel values displayed on a screen. Frame buffer memory is typically large (a few megabytes) and is 
usually written more than it is read by the processor.  Using strong uncacheable memory for a frame buffer gener-
ates very large amounts of bus traffic, because operations on the entire buffer are impl emented using partial writes 
rather than line writes. Using write-through memory for a frame buffer can displace almost all other useful cached Vol. 3A 12-9MEMORY CACHE CONTROL
lines in the processor's L2 and L3 caches and L1 data  cache. Therefore, systems should use write-combining 
memory for frame buffers whenever possible.
Software can use page-level cache control, to assign ap propriate effective memory types when software will not 
access data structures in ways that benefit from write-ba ck caching. For example, software may read a large data 
structure once and not access the structure again until the structure is rewritten by another agent. Such a large 
data structure should be marked as uncacheable, or read ing it will evict cached lines that the processor will be 
referencing again. 
A similar example would be a write-only data structure that is written to (to export the data to another agent), but 
never read by software. Such a structure can be marked as uncacheable, because software never reads the values 
that it writes (though as uncacheable memory, it will be  written using partial writes, while as write-back memory, 
it will be written using line writes, which may not occur until the other agent reads the structure and triggers 
implicit write-backs).
On the Pentium III, Pentium 4, and more recent processors, new instructions are provided that give software 
greater control over the caching, prefetching, and the write-back characteristics of data. These instructions allow software to use weakly ordered or processor ordered me mory types to improve processor performance, but when 
necessary to force strong ordering on memory reads and/or  writes. They also allow software greater control over 
the caching of data. For a description of these instructio ns and their intended use, see Section 12.5.5, “Cache 
Management Instructions.”
12.3.3 Code Fetches in Uncacheable Memory
Programs may execute code from uncacheable (UC) memo ry, but the implications are different from accessing 
data in UC memory. When doing code fetches, the proce ssor never transitions from cacheable code to UC code 
speculatively. It also never speculatively fetches branch targets that result in UC code.
The processor may fetch the same UC cache line multiple times in order to decode an instruction once. It may 
decode consecutive UC instructions in a cache line withou t fetching between each instruction. It may also fetch 
additional cachelines from the same or a consecutive 4- KByte page in order to decode one non-speculative UC 
instruction (this can be true even when the instruction is contained fully in one line). 
Because of the above and because cache line sizes may change in future processors, software should avoid placing 
memory-mapped I/O with read side effects in the same pa ge or in a subsequent page used to execute UC code.
12.4 CACHE CONTROL PROTOCOL
The following section describes the cache control protocol  currently defined for the Intel 64 and IA-32 architec-
tures. 
In the L1 data cache and in the L2/L3 unified caches, the ME SI (modified, exclusive, shared, invalid) cache protocol 
maintains consistency with caches of other processors. The L1 data cache and the L2/L3 unified caches have two MESI status flags per cache line. Each line can be marked as being in one of the states defined in Table 12-4. In 
general, the operation of the MESI protocol is transparent to programs.
Table 12-4.  MESI Cache Line States
Cache Line State M (Modified) E (Exclusive) S (Shared) I (Invalid)
This cache line is  valid? Yes Yes Yes No
The memory copy is… Out  of date Valid Valid —
Copies exist in caches of other 
processors?No No Maybe Maybe
A write to this line … Does not go to the 
system bus.Does not go to the 
system bus.Causes the processor to 
gain exclusive ownership 
of the line.Goes directly to the 
system bus.12-10 Vol. 3AMEMORY CACHE CONTROL
The L1 instruction cache in P6 family processors implemen ts only the “SI” part of the MESI protocol, because the 
instruction cache is not writable. The instruction cache monitors changes in the data cache to maintain consistency 
between the caches when instructions are modified. See Se ction 12.6, “Self-Modifying Code,” for more information 
on the implications of caching instructions.
12.5 CACHE CONTROL
The Intel 64 and IA-32 architectures provide a variety of  mechanisms for controlling the caching of data and 
instructions and for controlling the ordering of reads and writes between the processor, the caches, and memory. These mechanisms can be divided into two groups:
•Cache control registers and bits  — The Intel 64 and IA-32 architectures define several dedicated registers 
and various bits within control registers and page- and directory-table entries that control the caching system 
memory locations in the L1, L2, and L3 caches. These me chanisms control the caching of virtual memory pages 
and of regions of physical memory.
•Cache control and memory  ordering instructions  — The Intel 64 and IA-32 architectures provide several 
instructions that control the caching of data, the orderi ng of memory reads and writes, and the prefetching of 
data. These instructions allow software to control the ca ching of specific data structures, to control memory 
coherency for specific locations in memory, and to forc e strong memory ordering at specific locations in a 
program.
The following sections describe these two groups of cache control mechanisms.
12.5.1 Cache Control Registers and Bits
Figure 12-3 depicts cache-control mechanisms in IA-32 pr ocessors. Other than for the matter of memory address 
space, these work the same in Intel 64 processors.
The Intel 64 and IA-32 architectures provide the following cache-control registers and bits for use in enabling or 
restricting caching to various pages or regions in memory:
•CD flag, bit 30 of control register CR0 — Controls caching of system memory locations (see Section 2.5, 
“Control Registers”). If the CD flag is clear, cachin g is enabled for the whole of system memory, but may be 
restricted for individual pages or regions of memory by  other cache-control mechanisms. When the CD flag is 
set, caching is restricted in the processor’s caches (cache hierarchy) for the P6 and more recent processor families and prevented for the Pentium processor (see note  below). With the CD flag set, however, the caches 
will still respond to snoop traffic. Caches should be exp licitly flushed to ensure memory coherency. For highest

will still respond to snoop traffic. Caches should be exp licitly flushed to ensure memory coherency. For highest 
processor performance, both the CD and the NW flags in control register CR0 should be cleared. Table 12-5 shows the interaction of the CD and NW flags.
The effect of setting the CD flag is somewhat different for processor families starting with P6 family than the 
Pentium processor (see Table 12-5). To ensure memory coherency after the CD flag is set, the caches should 
be explicitly flushed (see Section 12.5.3, “Preventing Caching”). Setting the CD flag for the P6 and more recent processor families modifies cache line fill and update behavior. Also, setting the CD flag on these 
processors do not force strict ordering of memory accesses unless the MTRRs are disabled and/or all memory 
is referenced as uncached (see Section 9.2.5, “Str engthening or Weakening the Memory-Ordering Model”).Vol. 3A 12-11MEMORY CACHE CONTROL
Figure 12-3.  Cache-Control Registers and Bits Available in Intel 64 and IA-32 ProcessorsPage-Directory or
Page-Table Entry
TLBsMTRRs3Physical Memory
0FFFFFFFFH2
control overall caching
of system memoryCD and NW Flags PCD and PWT flags
control page-level
caching
G flag controls page-
level flushing of TLBsMTRRs control caching
of selected regions of
physical memoryP
C
DCR3
Control caching of
page directoryP
W
T
C
DCR0
N
W
Store BufferP
C
DP
W
TG1CR4
Enables global pagesP
G
E
designated with G flag
1. G flag only available in P6  and later processor families
3. MTRRs available only in P6  and later processor families;
 similar control available in Pentium processor with the KEN#
 and WB/WT# pins.2. The maximum physical address si ze is reported by CPUID leaf
function 80000008H. The maximu m physical address size ofPAT4
PAT controls caching
of virtual memory
pages
4. PAT available only in Pentium III and later processor families.P4
A
T
FFFFFFFFFH applies only If 36-bit physical addressing is used.
5. L3 in processors based on Intel NetBurst microarchitecture can
be disabled using IA32_MISC_ENABLE MSR.12-12 Vol. 3AMEMORY CACHE CONTROL
Table 12-5.  Cache Operating Modes 
CD NW Caching and Read/Write Policy L1 L2/L31
00 N o r m a l  C a c h e  M o d e .  H i g h e s t  performance cache operation.
• Read hits access the cache; read misses may cause replacement.
• Write hits update the cache.• Only writes to shared lines and write misses update system memory.Yes
Yes
YesYes
Yes
Yes
• Write misses cause cache line fills.
• Write hits can change shared lines to modified  under control of the MTRRs and with associated 
read invalidation cycle.
• (Pentium processor only.) Write mi sses do not cause cache line fills.Yes
Yes
YesYes
• (Pentium processor only.) Write hits can change shared lines to exclusive under control of WB/WT#.
• Invalidation is allowed.
• External snoop traffic is supported.Yes
Yes
YesYes
Yes
0 1 Invalid setting.
Generates a general-protection exception (#GP) with an error code of 0.NA NA
1 0 No-fill Cache Mode. Memory coherency is maintained.3
• (Pentium 4 and later processor families.) St ate of processor after a power up or reset.
• Read hits access the cache; re ad misses do not cause replacement (see Pentium 4 and Intel Xeon 
processors reference below).
• Write hits update the cache. 
• Only writes to shared lines and write misses update system memory.Yes
Yes
Yes
YesYes
Yes
Yes
Yes
• Write misses access memory.
• Write hits can change shared lines to exclusive under control of the MTRRs and with associated 
• (Pentium processor only.) Write hits can change shared lines to exclusive under control of the 
WB/WT#.Yes
Yes
YesYes
Yes
• (P6 and later processor families only.) Strict memory ordering is not enforced unless the MTRRs are 
disabled and/or all memory is referenced as uncached (see Section 7.2.4., “Strengthening or 
Weakening the Memory Ordering Model”).
Yes
YesYes
Yes
Yes
1 1 Memory coherency is not maintained.2, 3
• (P6 family and Pentium processors.) State of the processor after a power up or reset.
• Read hits access the cache; read  misses do not cause replacement.
• Write hits update the cache and ch ange exclusive lines to modified.Yes
Yes
YesYes
Yes
Yes
• Shared lines remain shared after write hit.
• Invalidation is inhibited when snooping; but is allowed with INVD and WBINVD instructions.
Yes
Yes
NoYes
Yes
Yes
Yes
NOTES:
1. The L2/L3 column in this table is definitive for the Pentium 4,  Intel Xeon, and P6 family proces sors. It is intended to repre sent what 
could be implemented in a system based on a Pentium processor with an external, platform specific, write-back L2 cache.
2. The Pentium 4 and more recent processor families do not support this mode; setting the CD and NW bits to 1 selects the no-fil l 
cache mode.
3. Not supported In Intel Atom processors. If CD = 1 in an Intel Atom processor, caching is disabled.Vol. 3A 12-13MEMORY CACHE CONTROL
•NW flag, bit 29 of control register CR0  — Controls the write policy for system memory locations (see 
Section 2.5, “Control Registers”). If the NW and CD fl ags are clear, write-back is enabled for the whole of 
system memory, but may be restricted for individual pages or regions of memory by other cache-control 
mechanisms. Table 12-5 shows how the other comb inations of CD and NW flags affects caching.
NOTES
For the Pentium 4 and Intel Xeon processors, the NW flag is a don’t care flag; that is, when the CD 
flag is set, the processor uses the no-fill cach e mode, regardless of the setting of the NW flag.
For Intel Atom processors, the NW flag is a don’t care flag; that is, when the CD flag is set, the 
processor disables caching, regardless of the setting of the NW flag.
For the Pentium processor, when the L1 cache is di sabled (the CD and NW flags in control register 
CR0 are set), external snoops are accepted in DP (dual-processor) systems and inhibited in unipro-
cessor systems. 
When snoops are inhibited, address parity is not checked and APCHK# is not asserted for a corrupt 
address; however, when snoops are accepted, addr ess parity is checked and APCHK# is asserted 
for corrupt addresses.
•PCD and PWT flags in paging-structure entries  — Control the memory type used to access paging 
structures and pages (see Section 4.9, “Paging and Memory Typing”).
•PCD and PWT flags in control register CR3  — Control the memory type used to access the first paging 
structure of the current paging-structure hierarchy (see Section 4.9, “Paging and Memory Typing”).
•G (global) flag in the page-directory and page-table  entries (introduced to th e IA-32 architecture in 
the P6 family processors)  — Controls the flushing of TLB entries for individual pages. See Section 4.10, 
“Caching Translation Information,” for more information about this flag.
•PGE (page global enable) flag  in control register CR4 — Enables the establishment of global pages with 
the G flag. See Section 4.10, “Caching Translation Information,” for more information about this flag.
•Memory type range regist ers (MTRRs) (introduced in  P6 family processors)  — Control the type of 
caching used in specific regions of physical memory . Any of the caching types described in Section 12.3, 
“Methods of Caching Available,” can be selected. See Section 12.11, “Memory Type Range Registers (MTRRs),” 
for a detailed description of the MTRRs.
•Page Attribute Table (PAT) MSR (introduced in the Pentium III processor)  — Extends the memory 
typing capabilities of the processor to permit memory  types to be assigned on a page-by-page basis (see 
Section 12.12, “Page Attribute Table (PAT)”).
•Third-Level Cache Disable flag, bit 6 of the IA32_MISC_ENABLE  MSR (Available only in processors 
based on Intel NetBurst microarchitecture)  — Allows the L3 cache to be disabled and enabled, indepen-
dently of the L1 and L2 caches. 
•KEN# and WB/WT# pins  (Pentium processor)  — Allow external hardware to control the caching method 
used for specific areas of memory. They perform similar (but not identical) functions to the MTRRs in the P6 
family processors.
•PCD and PWT pins (Pentium processor)  — These pins (which are associated with the PCD and PWT flags in 
control register CR3 and in the page-directory and page-t able entries) permit caching in an external L2 cache 
to be controlled on a page-by-page basis, consistent with the control exercised on the L1 cache of these 
processors. The P6 and more recent processor families do not provide these pins because the L2 cache in 
internal to the chip package.
12.5.2 Precedence of Cache Controls
The cache control flags and MTRRs operate hierarchically for restricting caching. That is, if the CD flag is set, 
caching is prevented globally (see Table 12-5). If the CD fl ag is clear, the page-level cache control flags and/or the 
MTRRs can be used to restrict caching. If there is an overlap of page-level and MTRR caching controls, the mecha-

nism that prevents caching has precedence. For example,  if an MTRR makes a region of system memory uncache-
able, a page-level caching control cannot be used to enable caching for a page in that region. The converse is also 12-14 Vol. 3AMEMORY CACHE CONTROL
true; that is, if a page-level caching control designates a page as uncacheable, an MTRR cannot be used to make 
the page cacheable.
In cases where there is a overlap in the assignment of the write-back and write-through caching policies to a page 
and a region of memory, the write-through policy takes pr ecedence. The write-combining policy (which can only be 
assigned through an MTRR or the PAT) takes preced ence over either write-through or write-back.
The selection of memory types at the page level varies de pending on whether PAT is being used to select memory 
types for pages, as described in the following sections.
On processors based on Intel NetBurst microarchitecture, the third-level cache can be disabled by bit 6 of the 
IA32_MISC_ENABLE MSR. Using IA32_MISC_ENABLE[bit 6] takes precedence over the CD flag, MTRRs, and PAT 
for the L3 cache in those processors. That is, when the th ird-level cache disable flag is set (cache disabled), the 
other cache controls have no affect on the L3 cache; when the flag is clear (enabled), the cache controls have the same affect on the L3 cache as they have on the L1 and L2 caches.
IA32_MISC_ENABLE[bit 6] is not supported in Intel Core i7 processors, nor processors based on Intel Core, and 
Intel Atom microarchitectures.
12.5.2.1  Selecting Memory Types fo r Pentium Pro and Pentium II Processors
The Pentium Pro and Pentium II processors do not support th e PAT. Here, the effective memory type for a page is 
selected with the MTRRs and the PCD and PWT bits in the page-table or page-directory entry for the page. Table 
12-6 describes the mapping of MTRR memo ry types and page-level caching attr ibutes to effective memory types, 
when normal caching is in effect (the CD and NW flags in  control register CR0 are clear). Combinations that appear 
in gray are implementation-defined for the Pentium Pro and Pentium II processors. System designers are encour-
aged to avoid these implementation-defined combinations.
When normal caching is in effect, the effective memory type shown in Table 12 -6 is determined using the following 
rules:
1. If the PCD and PWT attributes for th e page are both 0, then the effective memory type is identical to the
MTRR-defined memory type.Table 12-6.  Effective Page-Level Memo ry Type for Pentium Pro and Pentium II Processors 
MTRR Memory Type1PCD Value PWT Value Effective Memory Type
UC X X UC
WC 0 0 WC
0 1 WC
1 0 WC
11 U C
WT 0 X WT
1X U C
WP 0 0 WP
0 1 WP
1 0 WC
11 U C
WB 0 0 WB
01 W T1X U C
NOTE:
1. These effective memory types also apply to the Pentium 4, Intel Xeon , and Pentium III processors wh en the PAT bit is not used  
(set to 0) in page-table and page-directory entries.Vol. 3A 12-15MEMORY CACHE CONTROL
2. If the PCD flag is set, then the effective memory type is UC.
3. If the PCD flag is clear and the PWT flag is set, the effective memory type is WT for the WB memory type and 
the MTRR-defined memory type for all other memory types. 
4. Setting the PCD and PWT flags to opposite values is considered model-specific for the WP and WC memory 
types and architecturally-defined fo r the WB, WT, and UC memory types.
12.5.2.2  Selecting Memory Types for Pent ium III and More Recent Processor Families
The Intel Core 2 Duo, Intel Atom, Inte l Core Duo, Intel Core Solo, Pentium M, Pentium 4, Intel Xeon, and Pentium 
III processors use the PAT to select effective page-level me mory types. Here, a memory ty pe for a page is selected 
by the MTRRs and the value in a PAT entry that is selected with the PAT, PCD, and PWT bits in a page-table or page-
directory entry (see Section 12.12.3, “Selecting a Memory Type from the PAT”). Table 12-7 describes the mapping 
of MTRR memory types and PAT entry types to effective memo ry types, when normal caching is in effect (the CD 
and NW flags in control register CR0 are clear).
Table 12-7.  Effective Page-Level Memory Types fo r Pentium III and More Re cent Processor Families 
MTRR Memory Type PAT Entry Value Effective Memory Type
UC UC UC1
UC- UC1
WC WC
WT UC1
WB UC1
WP UC1
WC UC UC2
UC- WC
WC WC
WT UC2,3
WB WC
WP UC2,3
WT UC UC2
UC- UC2
WC WC
WT WT
WB WT
WP WP3
WB UC UC2
UC- UC2
WC WC
WT WT
WB WB
WP WP12-16 Vol. 3AMEMORY CACHE CONTROL
12.5.2.3  Writing Valu es Across Pages with Different Memory Types
If two adjoining pages in memory have  different memory types, and a word or longer operand is written to a 
memory location that crosses the page boundary betw een those two pages, the operand might be written to 
memory twice. This action does not present a problem for wr ites to actual memory; however, if a device is mapped 
to the memory space assigned to the pages, the device might malfunction.
12.5.3 Preventing Caching
To disable the L1, L2, and L3 caches after they have b een enabled and have received cache fills, perform the 
1. Enter the no-fill cache mode. (Set the CD flag in  control register CR0 to 1 and the NW flag to 0.
2. Flush all caches using the WBINVD instruction.
3. Disable the MTRRs and set the default memory type to  uncached or set all MTRRs for the uncached memory 
type (see the discussion of the discussion of the TYPE  field and the E flag in Section 12.11.2.1, “IA32_MTR-
R_DEF_TYPE MSR”).
The caches must be flushed (step 2) after the CD flag is set to ensure system memory coherency. If the caches are 
not flushed, cache hits on reads will still occur and data will be read from valid cache lines.
The intent of the three sepa rate steps listed above address three distinct requirements: (i) discontinue new data 
replacing existing data in the cache (ii) ensure data alre ady in the cache are evicted to memory, (iii) ensure subse-
quent memory references observe UC memory type sema ntics. Different processor implementation of caching 
control hardware may allow some variation of software implementation of these three requirements. See note 
below.
NOTES
Setting the CD flag in control register CR0 modifies the processor’s caching behavior as indicated in Table 12-5, but setting the CD flag alone may not be  sufficient across all processor families to force 
the effective memory type for all physical memory  to be UC nor does it force strict memory 
ordering, due to hardware implementation variations across different processor families. To force 
the UC memory type and strict memory ordering on all of physical memory, it is sufficient to either 
program the MTRRs for all physical memory to  be UC memory type or disable all MTRRs.
For the Pentium 4 and Intel Xeon processors, afte r the sequence of steps given above has been 
executed, the cache lines containing the code between the end of the WBINVD instruction and 
before the MTRRS have actually been disabled ma y be retained in the cache hierarchy. Here, to WP UC UC
2
UC- WC3
WC WC
WT WT3
WB WP
WP WP
NOTES: 
1. The UC attribute comes from the MTRRs and the processors are no t required to snoop their caches since the data could never ha ve 
been cached. This attribute is preferred for performance reasons.
2. The UC attribute came from the page-table or page-directory entry and processors are required to check their caches because t he 
data may be cached due to page aliasing, which is not recommended.
3. These combinations were specified as “undefined” in previous editions of the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual. However, all processors th at support both the PAT and the MTRRs de termine the effective page-level memory 
types for these combinations as given.Table 12-7.  Effective Page-Level Memory Types for Pent ium III and More Recent Pr ocessor Families  (Contd.)
MTRR Memory Type PAT Entry Value Effective Memory TypeVol. 3A 12-17MEMORY CACHE CONTROL
remove code from the cache completely, a second WBINVD instruction must be executed after the 
MTRRs have been disabled.
For Intel Atom processors, setting the CD flag forc es all physical memory to observe UC semantics 
(without requiring memory type of physical memory  to be set explicitly). Consequently, software 
does not need to issue a second WBINVD as so me other processor generations might require. 
12.5.4 Disabling and Enabling the L3 Cache
IA32_MISC_ENABLE MSR. The third-level cache disable flag  (bit 6 of the IA32_MISC_ENABLE MSR) allows the L3 
cache to be disabled and enabled, independently of the L1 and L2 caches. Prior to using this control to disable or 
enable the L3 cache, software should disable and flush all the processor caches, as described earlier in Section 12.5.3, “Preventing Caching,” to prevent of loss of informat ion stored in the L3 cache. After the L3 cache has been

enable the L3 cache, software should disable and flush all the processor caches, as described earlier in Section 12.5.3, “Preventing Caching,” to prevent of loss of informat ion stored in the L3 cache. After the L3 cache has been 
disabled or enabled, caching for the whole processor can be restored.
Newer Intel 64 processor with L3 do not support IA32_MI SC_ENABLE[bit 6], the procedure described in Section 
12.5.3, “Preventing Caching,” apply to the entire cache hierarchy.
12.5.5 Cache Management Instructions
The Intel 64 and IA-32 architectures provide several instructions for managing the L1, L2, and L3 caches. The INVD 
and WBINVD instructions are privileged instructions and operate on the L1, L2, and L3 caches as a whole. The 
PREFETCHh, CLFLUSH, and CLFLUSHOPT instructions and the non-temporal move instructions (MOVNTI, MOVNTQ, 
MOVNTDQ, MOVNTPS, and MOVNTPD) offer more granular cont rol over caching, and are available to all privileged 
levels.
The INVD and WBINVD instructions are used to invalidat e the contents of the L1, L2, and L3 caches. The INVD 
instruction invalidates all internal cache entries, then ge nerates a special-function bus cycle that indicates that 
external caches also should be invalidated. The INVD in struction should be used with care. It does not force a 
write-back of modified cache lines; therefore, data stor ed in the caches and not written back to system memory 
will be lost. Unless there is a specific requirement or benefit to invalidating the caches without writing back the 
modified lines (such as, during testing or fault recovery where cache coherency with main memory is not a 
concern), software should use the WBINVD instruction. 
The WBINVD instruction first writes back any modified lines in all the internal caches, then invalidates the contents 
of the L1, L2, and L3 caches. It ensures that cache cohe rency with main memory is maintained regardless of the 
write policy in effect (that is, write-through or write-back ). Following this operation, the WBINVD instruction gener-
ates one (P6 family processors) or two (Pentium and Intel486  processors) special-function bus cycles to indicate to 
external cache controllers that write-back of modified data  followed by invalidation of ex ternal caches should occur. 
The amount of time or cycles for WBINVD to complete w ill vary due to the size of different cache hierarchies and 
other factors. As a consequence, the use of the WBINVD  instruction can have an impact on interrupt/event 
response time.
The PREFETCH h instructions allow a program to suggest to the processor that a cache line from a specified location 
in system memory be prefetched into the cache hierarchy (see Section 12.8, “Explicit Caching”).
The CLFLUSH and CLFLUSHOPT instructio ns allow selected cache lines to be flushed from memory. These instruc-
tions give a program the ability to explicitly free up cache space, when it is known that cached section of system 
memory will not be accessed in the near future.
The non-temporal move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD) allow data to be 
moved from the processor’s registers directly into syst em memory without being also written into the L1, L2, 
and/or L3 caches. These instructions can be used to prevent cache pollution when operating on data that is going 
to be modified only once before being stored back into system memory. These instructions operate on data in the general-purpose, MMX, and XMM registers.12-18 Vol. 3AMEMORY CACHE CONTROL
12.5.6 L1 Data Cache Context Mode
L1 data cache context mode is a feature of processors ba sed on the Intel NetBurst microarchitecture that support 
Intel Hyper-Threading Technology. When  CPUID.1:ECX[bit 10] = 1, the processor supports setting L1 data cache 
context mode using the L1 data cache context mode fl ag ( IA32_MISC_ENABLE[bit 24] ). Selectable modes are 
adaptive mode (default) and shared mode.
The BIOS is responsible for configuring the L1 data cache context mode.
12.5.6.1  Adaptive Mode
Adaptive mode facilitates L1 data cache sharing between logical processors. When running in adaptive mode, the 
L1 data cache is shared across logical processors in the same core if:
•CR3 control registers for logical processors sharing the cache are identical.
•The same paging mode is used by logical processors sharing the cache.
In this situation, the entire L1 data cache is available to each logical processor (instead of being competitively 
shared).
If CR3 values are different for the logical processors sharin g an L1 data cache or the logical processors use different 
paging modes, processors compete for cache resources. This  reduces the effective size of the cache for each logical 
processor. Aliasing of the cache is not allowed (which prevents data thrashing).
12.5.6.2  Shared Mode
In shared mode, the L1 data cache is competitively shared  between logical processors. This is true even if the 
logical processors use identical CR3 registers and paging modes.
In shared mode, linear addresses in the L1 data cache can be aliased, meaning that one linear address in the cache 
can point to different physical locations. The mechanism for resolving aliasing can lead to thrashing. For this reason, IA32_MISC_ENABLE[bit 24] = 0 is the preferred conf iguration for processors based on the Intel NetBurst 
microarchitecture that support Intel Hyper-Threading Technology.
12.6 SELF-MODIFYING CODE
A write to a memory location in a code segment that is currently cached in the processor causes the associated 
cache line (or lines) to be invalidated. This check is base d on the physical address of the instruction. In addition, 
the P6 family and Pentium processors check whether a write to a code segment may modify an instruction that has been prefetched for execution. If the write affects a prefet ched instruction, the prefetch queue is invalidated. This 
latter check is based on the linear address of the instruct ion. For the Pentium 4 and Intel Xeon processors, a write 
or a snoop of an instruction in a code segment, where the target instruction is already decoded and resident in the 
trace cache, invalidates the entire trace cache. The latter behavior means that programs that self-modify code can 
cause severe degradation of performance when r un on the Pentium 4 and Intel Xeon processors.
In practice, the check on linear addresses should not cr eate compatibility problems among IA-32 processors. Appli-
cations that include self-modifying code use the same lin ear address for modifying and fetching the instruction. 
Systems software, such as a debugger, that might possibly modify an instruction using a different linear address than that used to fetch the instruction, will execute a seri alizing operation, such as a CPUID instruction, before the 
modified instruction is executed, which will automatically resynchronize the instruction cache and prefetch queue. 
(See Section 9.1.3, “Handling Self- an d Cross-Modifying Code,” for more information about the use of self-modi-
fying code.)
For Intel486 processors, a write to an instruction in the ca che will modify it in both the cache and memory, but if 
the instruction was prefetched before the write, the old version of the inst ruction could be the one executed. To 
prevent the old instruction from being executed, flush the instruction prefetch unit by coding a jump instruction 
immediately after any write that modifies an instruction.Vol. 3A 12-19MEMORY CACHE CONTROL
12.7 IMPLICIT CACHING (PENTIUM 4,  INTEL® XEON®, AND P6 FAMILY 
PROCESSORS)
Implicit caching occurs when a memory element is made  potentially cacheable, although the element may never 
have been accessed in the normal von Neumann sequence. Implicit caching occurs on the P6 and more recent 
processor families due to aggressive prefetching, branch pr ediction, and TLB miss handli ng. Implicit caching is an 
extension of the behavior of existing  Intel386, Intel486, and Pentium proce ssor systems, since software running 
on these processor families also has not been able to dete rministically predict the behavior of instruction prefetch.
To avoid problems related to implicit caching, the oper ating system must explicitly invalidate the cache when 
changes are made to cacheable data that the cache coherency mechanism does not automatically handle. This includes writes to dual-ported or physically aliased me mory boards that are not detected by the snooping mecha-
nisms of the processor, and changes to page- table entries in memory.
The code in Example 12-1 shows the effect of implicit ca ching on page-table entries. The linear address F000H 
points to physical location B000H (the page-table entr y for F000H contains the value B000H), and the page-table 
entry for linear address F000 is PTE_F000.
Example 12-1.  Effect of Implicit Caching on Page-Table Entries
mov EAX, CR3; Invalidate the TLB
mov CR3, EAX; by copying CR3 to itselfmov PTE_F000, A000H; Change F000H to point to A000Hmov EBX, [F000H];
Because of speculative execution in the P6 and more rece nt processor families, the last MOV instruction performed 
would place the value at physical loca tion B000H into EBX, rather than th e value at the new physical address

would place the value at physical loca tion B000H into EBX, rather than th e value at the new physical address 
A000H. This situation is remedied by placing a TLB invalidation between the load and the store.
12.8 EXPLICIT CACHING
The Pentium III processor introduced four new instructions, the PREFETCH h instructions, that provide software with 
explicit control over the caching of da ta. These instructions provide “hints” to the processor that the data requested 
by a PREFETCH h instruction should be read into cache hierarchy now or as soon as possible, in anticipation of its 
use. The instructions provide different variations of the hi nt that allow selection of the cache level into which data 
will be read.
The PREFETCH h instructions can help reduce the long latency typi cally associated with reading data from memory 
and thus help prevent processor “stalls.” However, these instructions should be used judiciously. Overuse can lead 
to resource conflicts and hence reduce the performance of an application. Also, these instructions should only be 
used to prefetch data from memory; they should not be used to prefetch instructions. For more detailed informa-
tion on the proper use of the prefetch instruction, refe r to Chapter 7, “Optimizing Cache Usage,” in the Intel® 64 
and IA-32 Architectures Optimization Reference Manual.
12.9 INVALIDATING THE TRANSL ATION LOOKASIDE BUFFERS (TLBS)
The processor updates its address translation caches (TLB s) transparently to software. Several mechanisms are 
available, however, that allow software and hardware to inva lidate the TLBs either explicitly or as a side effect of 
another operation. Most details are given in Section 4.10.4,  “Invalidation of TLBs and Paging-Structure Caches.” In 
addition, the following operations invalidate all TLB entries, irrespective of the setting of the G flag:
•Asserting or de-asserting the FLUSH# pin.
•(Pentium 4, Intel Xeon, and later processors only .) Writing to an MTRR (with a WRMSR instruction).
•Writing to control register CR0 to modify the PG or PE flag.12-20 Vol. 3AMEMORY CACHE CONTROL
•(Pentium 4, Intel Xeon, and later processors only.) Writin g to control register CR4 to modify the PSE, PGE, or 
PAE flag.
•Writing to control register CR4 to change the PCIDE flag from 1 to 0.
See Section 4.10, “Caching Translation Informatio n,” for additional information about the TLBs.
12.10 STORE BUFFER
Intel 64 and IA-32 processors temporarily store each writ e (store) to memory in a store buffer. The store buffer 
improves processor performance by allowing the processor to continue executing instructions without having to 
wait until a write to memory and/or to a cache is complete. It also allows writes to be delayed for more efficient use of memory-access bus cycles.
In general, the existence of the store buffer is transparen t to software, even in systems that use multiple proces-
sors. The processor ensures that write operations are always  carried out in program order. It also ensures that the 
contents of the store buffer are always drained to memory in the following situations:
•When an exception or interrupt is generated.
•(P6 and more recent processor families only) When a serializing instruction is executed.
•When an I/O instruction is executed.
•When a LOCK operation is performed.
•(P6 and more recent processor families on ly) When a BINIT operation is performed.
•(Pentium III, and more recent processor families only) When  using an SFENCE instruction to order stores.
•(Pentium 4 and more recent processor families only) When using an MFENCE instruction to order stores.
The discussion of write ordering in Sect ion 9.2, “Memory Ordering,” gives a de tailed description of the operation of 
the store buffer.
12.11 MEMORY TYPE RA NGE REGISTERS (MTRRS)
The following section pertains only to the P6 and more recent processor families.
The memory type range registers (MTRRs) provide a mechanism for associating the memory types (see Section 
12.3, “Methods of Caching Available”) with physical-addre ss ranges in system memory. They allow the processor to 
optimize operations for different ty pes of memory such as RAM, ROM, frame-buffer memory, and memory-mapped 
I/O devices. They also simplify system hardware design by  eliminating the memory control pins used for this func-
tion on earlier IA-32 processors and the external logic needed to drive them.
The MTRR mechanism allows multiple ranges to be define d in physical memory, and it defines a set of model-
specific registers (MSRs) for specifying the type of memo ry that is contained in each range. Table 12-8 shows the 
memory types that can be specified and their properties ; Figure 12-4 shows the mapping of physical memory with 
MTRRs. See Section 12.3, “Methods of Caching Available,” for a more detailed description of each memory type.
Following a hardware reset, the P6 an d more recent processor families disa ble all the fixed and variable MTRRs, 
which in effect makes all of physical memory uncacheable.  Initialization software should then set the MTRRs to a 
specific, system-defined memory map. Typically, the BIOS  (basic input/output system) software configures the 
MTRRs. The operating system or executive is then free to modify the memory map us ing the normal page-level 
cacheability attributes.
In a multiprocessor system using a processor in the P6 fa mily or a more recent family, each processor MUST use 
the identical MTRR memory map so that software  will have a consistent view of memory.
NOTE
In multiple processor systems, the operating sy stem must maintain MTRR consistency between all 
the processors in the system (that is, all proce ssors must use the same MTRR values). The P6 and 
more recent processor families provide no hardware support for maintaining this consistency.Vol. 3A 12-21MEMORY CACHE CONTROL
12.11.1 MTRR Feature Identification
The availability of the MTRR feature is model-specific . Software can determine if MTRRs are supported on a 
processor by executing the CPUID instruction and reading th e state of the MTRR flag (bit 12) in the feature infor-
mation register (EDX).
If the MTRR flag is set (indicating that the processor im plements MTRRs), additional information about MTRRs can 
be obtained from the 64-bit IA32_MTRRCAP MSR (named  MTRRcap MSR for the P6 family processors). The 
IA32_MTRRCAP MSR is a read-only MSR that can be read with the RDMSR instruction. Figure 12-5 shows the 
contents of the IA32_MTRRCAP MSR. The functions of the flags and field in this register are as follows:Table 12-8.  Memory Types That Can Be Encoded in MTRRs 
Memory Type and Mnemonic Encoding in MTRR
Uncacheable (UC) 00H
Write Combining (WC) 01H
Reserved* 02H
Reserved* 03H
Write-through (WT) 04H
Write-protected (WP) 05H
Writeback (WB) 06H
Reserved* 7H through FFH
NOTE:
* Use of these encodings results in a general-protection exception (#GP).
Figure 12-4.  Mapping Phys ical Memory With MTRRs0FFFFFFFFH
80000HBFFFFHC0000HFFFFFH100000H
7FFFFH
512 KBytes256 KBytes
256 KBytes
8 fixed ranges16 fixed ranges64 fixed rangesVariable ranges
(64-KBytes each)(16 KBytes each)(4 KBytes each)(from 4 KBytes to
maximum size ofAddress ranges notPhysical Memory
mapped by an MTRR
are set to a default type
physical memory)12-22 Vol. 3AMEMORY CACHE CONTROL
•VCNT (variable range registers co unt) field, bits 0 through 7 — Indicates the number of variable ranges 
implemented on the processor.
•FIX (fixed range registers supported) flag, bit 8 — Fixed range MTRRs (IA32_MTRR_FIX64K_00000 
through IA32_MTRR_FIX4K_0F8000) are supported when se t; no fixed range registers are supported when 
clear.
•WC (write combining) flag, bit 10 — The write-combining (WC) memory type is supported when set; the 
WC type is not supported when clear.
•SMRR (System-Management Range Register) flag, bit 11 — The system-management range register 
(SMRR) interface is supported when bit 11 is se t; the SMRR interface is not supported when clear.
Bit 9 and bits 12 through 63 in the IA32_MTRRCAP MSR ar e reserved. If software attempts to write to the 
IA32_MTRRCAP MSR, a general-protection exception (#GP) is generated. 
Software must read IA32_MTRRCAP VCNT field to dete rmine the number of variable MTRRs and query other 
feature bits in IA32_MTRRCAP to determine additional capa bilities that are supported in a processor. For example, 
some processors may report a value of ‘8’ in the VCNT field, other processors may report VCNT with different 
values. 
12.11.2 Setting Memory Ranges with MTRRs
The memory ranges and the types of me mory specified in each range are set by three groups of registers: the 
IA32_MTRR_DEF_TYPE MSR, the fixed-range MTRRs, and th e variable range MTRRs. These registers can be read 
and written to using the RDMSR and WRMSR instructio ns, respectively. The IA32_MTRRCAP MSR indicates the 
availability of these registers on the processor (see Section 12.11.1, “MTRR Feature Identification”).
12.11.2.1  IA32_MTRR_DEF_TYPE MSR
The IA32_MTRR_DEF_TYPE MSR (named MTRRdefType MSR for the P6 family processors) sets the default proper-

values. 
ties of the regions of physical memory that are not enco mpassed by MTRRs. The functions of the flags and field in 
this register are as follows:
•Type field, bits 0 through 7 — Indicates the default memory type us ed for those physical memory address 
ranges that do not have a memory type specified for th em by an MTRR (see Table 12-8 for the encoding of this 
field). The legal values for this field are 0, 1, 4, 5, and 6. All other values result in a general-protection exception (#GP) being generated. 
Intel recommends the use of the UC (uncached) memo ry type for all physical memory addresses where 
memory does not exist. To assign the UC type to nonexist ent memory locations, it can either be specified as the 
default type in the Type field or be explicit ly assigned with the fixed and variable MTRRs.Figure 12-5.  IA32 _MTRRCAP RegisterVCNT — Number of variable range registersFIX — Fixed range registers supportedWC — Write-combining memory type supported63 0
ReservedW
C7 1011
VCNTF
I
X89
ReservedSMRR — SMRR interface supportedVol. 3A 12-23MEMORY CACHE CONTROL
•FE (fixed MTRRs enabled) flag, bit 10 — Fixed-range MTRRs are enabled when set; fixed-range MTRRs are 
disabled when clear. When the fixed-range MTRRs are en abled, they take priority over the variable-range 
MTRRs when overlaps in ranges occur. If the fixed- range MTRRs are disabled, the variable-range MTRRs can 
still be used and can map the range ordi narily covered by the fixed-range MTRRs.
•E (MTRRs enabled) flag, bit 11 — MTRRs are enabled when set; all MTRR s are disabled when clear, and the 
UC memory type is applied to all of physical memory. When this flag is set, the FE flag can disable the fixed-range MTRRs; when the flag is clear, the FE flag has no af fect. When the E flag is set, the type specified in the 
default memory type field is used for areas of memory not already mapped by either a fixed or variable MTRR.
Bits 8 and 9, and bits 12 through 63, in the IA32_MT RR_DEF_TYPE MSR are reserved ; the processor generates a 
general-protection exception (#GP) if software attempts to write nonzero values to them.
12.11.2.2  Fixed Range MTRRs
The fixed memory ranges are mapped with 11 fixed-range re gisters of 64 bits each. Each of these registers is 
divided into 8-bit fields that are used to specify the memo ry type for each of the sub-ranges the register controls:
•Register IA32_MTRR_FIX64K_00000 — Maps the 512-KByte address range from 0H to 7FFFFH. This range 
is divided into eight 64-KByte sub-ranges.
•Registers IA32_MTRR_FIX16K_80000 and IA32_MTRR_FIX16K_A0000 — Maps the two 128-KByte 
address ranges from 80000H to BFFFFH. This range is divided into sixteen 16-KByte sub-ranges, 8 ranges per 
register.
•Registers IA32_MTRR_FIX4K_C0000 through IA32_MTRR_FIX4K_F8000 — Maps eight 32-KByte 
address ranges from C0000H to FFFFFH. This range is divided into sixty-four 4-KByte sub-ranges, 8 ranges per 
register.
Table 12-9 shows the relationship between the fixed phys ical-address ranges and the corresponding fields of the 
fixed-range MTRRs; Table 12-8 shows memory type encoding for MTRRs.
For the P6 family processors, the prefix for the fixed range MTRRs is MTRRfix.
12.11.2.3  Variable Range MTRRs
The Pentium 4, Intel Xeon, and P6 family processors perm it software to specify the memory type for m variable-
size address ranges, using a pair of MTRRs for each range.  The number m of ranges supported is given in bits 7:0 
of the IA32_MTRRCAP MSR (see Figure 12-5 in Section 12.11.1).
The first entry in each pair (IA32_MTRR_PHYSBASEn) defi nes the base address and memory type for the range; 
the second entry (IA32_MTRR_PHYSMASKn) contains a mask used to determine the address range. The “n” suffix 
is in the range 0 through m–1 and identifies a specific register pair.
For P6 family processors, the prefixes for these va riable range MTRRs are MTRRphysBase and MTRRphysMask.Figure 12-6.  IA32_MTRR_DEF_TYPE MSRType — Default memory typeFE — Fixed-range MTRRs enable/disableE — MTRR enable/disable63 0
ReservedF
E7 1011
Type89 12
E
Reserved12-24 Vol. 3AMEMORY CACHE CONTROL
Figure 12-7 shows flags and fields in these register s. The functions of these flags and fields are:
•Type field, bits 0 through 7 — Specifies the memory type for the rang e (see Table 12-8 for the encoding of 
this field).
•PhysBase field, bits 12  through (MAXPHYADDR-1) — Specifies the base address of the address range. 
This 24-bit value, in the case where MAXPHYADDR is 36 bi ts, is extended by 12 bits at the low end to form the 
base address (this automatically aligns the address on a 4-KByte boundary).
•PhysMask field, bits 12 through (MAXPHYADDR-1) — Specifies a mask (24 bits if the maximum physical 
address size is 36 bits, 28 bits if the maximum physical address size is 40 bits). The mask determines the range 
of the region being mapped, accord ing to the following relationships:
— Address_Within_Range AND PhysMask = PhysBase AND PhysMask— This value is extended by 12 bits at the low end to fo rm the mask value. For more information: see Section 
12.11.3, “Example Base and Mask Calculations.”
— The width of the PhysMask field depends on the maximum physical address size supported by the 
processor. 
CPUID.80000008H reports the maximum physical address size supported by the processor. If 
CPUID.80000008H is not available, software may assume  that the processor supports a 36-bit physical 
address size (then PhysMask is 24 bits wide an d the upper 28 bits of IA32_MTRR_PHYSMASKn are 
reserved). See the Note below.
•V (valid) flag, bit 11 — Enables the register pair when set; disables register pair when clear.Table 12-9.  Address Mapping for Fixed-Range MTRRs
Address Range (hexadecimal) MTRR
63   56 55    48 47    40 39    32 31     24 23     16 15     8 7      070000-
7FFFF60000-
6FFFF50000-
5FFFF40000-
4FFFF30000-
3FFFF20000-
2FFFF10000-
1FFFF00000-
0FFFFIA32_MTRR_
FIX64K_00000
9C000
9FFFF98000-
9BFFF94000-
97FFF90000-
93FFF8C000-
8FFFF88000-
8BFFF84000-
87FFF80000-
83FFFIA32_MTRR_
FIX16K_80000
BC000
BFFFFB8000-
BBFFFB4000-
B7FFFB0000-
B3FFFAC000-
AFFFFA8000-
ABFFFA4000-
A7FFFA0000-
A3FFFIA32_MTRR_
FIX16K_A0000
C7000
C7FFFC6000-
C6FFFC5000-
C5FFFC4000-
C4FFFC3000-
C3FFFC2000-
C2FFFC1000-
C1FFFC0000-
C0FFFIA32_MTRR_
FIX4K_C0000
CF000
CFFFFCE000-
CEFFFCD000-
CDFFFCC000-
CCFFFCB000-
CBFFFCA000-
CAFFFC9000-
C9FFFC8000-
C8FFFIA32_MTRR_
FIX4K_C8000
D7000
D7FFFD6000-
D6FFFD5000-
D5FFFD4000-
D4FFFD3000-
D3FFFD2000-
D2FFFD1000-
D1FFFD0000-
D0FFFIA32_MTRR_
FIX4K_D0000
DF000
DFFFFDE000-
DEFFFDD000-
DDFFFDC000-
DCFFFDB000-
DBFFFDA000-
DAFFFD9000-
D9FFFD8000-
D8FFFIA32_MTRR_
FIX4K_D8000
E7000
E7FFFE6000-
E6FFFE5000-
E5FFFE4000-
E4FFFE3000-
E3FFFE2000-
E2FFFE1000-
E1FFFE0000-
E0FFFIA32_MTRR_
FIX4K_E0000
EF000
EFFFFEE000-
EEFFFED000-
EDFFFEC000-
ECFFFEB000-
EBFFFEA000-
EAFFFE9000-
E9FFFE8000-
E8FFFIA32_MTRR_
FIX4K_E8000
F7000
F7FFFF6000-
F6FFFF5000-
F5FFFF4000-
F4FFFF3000-
F3FFFF2000-
F2FFFF1000-
F1FFFF0000-
F0FFFIA32_MTRR_
FIX4K_F0000
FF000
FFFFFFE000-
FEFFFFD000-
FDFFFFC000-
FCFFFFB000-
FBFFFFA000-
FAFFFF9000-
F9FFFF8000-
F8FFFIA32_MTRR_
FIX4K_F8000Vol. 3A 12-25MEMORY CACHE CONTROL
All other bits in the IA32_MTRR_PHYSBASE n and IA32_MTRR_PHYSMASK n registers are reserved; the processor 
generates a general-protection exception (#GP ) if software attempts to write to them.
Some mask values can result in ranges that are not continuous. In such ranges, the area not mapped by the mask 
value is set to the default memory type, unless some othe r MTRR specifies a type for that range. Intel does not 
encourage the use of “discontinuous” ranges.
NOTE
It is possible for software to parse the memory  descriptions that BIOS provides by using the 
ACPI/INT15 e820 interface mechanism. This information then can be used to determine how 
MTRRs are initialized (for example: allowing th e BIOS to define valid memory ranges and the 
maximum memory range supported by the platform, including the processor).
See Section 12.11.4.1, “MTRR Precedences,” for information on overlapping variable MTRR ranges.
12.11.2.4  System-Management Range Register Interface 
If IA32_MTRRCAP[bit 11] is set, the processor supports the SMRR interface to restrict access to a specified 
memory address range used by system-management mode (SMM) software (see Section 32.4.2.1). If the SMRR 
interface is supported, SMM software is strongly encouraged  to use it to protect the SMI code and data stored by 
SMI handler in the SMRAM region.
The system-management range registers consist of a pair of MSRs (see Figure 12-8). The IA32_SMRR_PHYSBASE 
MSR defines the base address for the SMRAM memory range and the memory ty pe used to access it in SMM. The 
IA32_SMRR_PHYSMASK  MSR contains a valid bit and a mask that de termines the SMRAM address range protected 
by the SMRR interface. These MSRs may be written only in  SMM; an attempt to write them outside of SMM causes 
a general-protection exception.1

Figure 12-8 shows flags and fields in these registers. The functions of these flags and fields are the following:Figure 12-7.  IA32_MTRR_PHYSBASE n and IA32_MTRR_PHYSMASK n Variable-Range Register Pair
1. For some processor models, these MSRs can be accessed by RDMSR and WRMSR only if the SMRR interface has been enabled using 
a model-specific bit in the IA32_FEATURE_CONTROL MSR.V — ValidPhysMask — Sets range maskIA32_MTRR_PHYSMASK n Register
63 0
Reserved101112
V ReservedMAXPHYADDR
PhysMaskType — Memory type for rangePhysBase — Base address of rangeIA32_MTRR_PHYSBASE n Register
63 0
Reserved1112
TypeMAXPHYADDR
PhysBase78
Reserved
MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the maximum
physical address range supported by the processor. It is reported by CPUID leaf
function 80000008H. If CPUID does not support leaf 80000008H, the processor
supports 36-bit physical address size, then bit PhysMask consists of bits 35:12, andbits 63:36 are reserved.12-26 Vol. 3AMEMORY CACHE CONTROL
•PhysBase field, bits 12 through 31 — Specifies the base address of the address range. The address must be 
less than 4 GBytes and is automatically aligned on a 4-KByte boundary.
•PhysMask field, bits 12 through 31 — Specifies a mask that determines the range of the region being 
mapped, according to the following relationships:
— Address_Within_Range AND PhysMask = PhysBase AND PhysMask
— This value is extended by 12 bits at the low end to fo rm the mask value. For more information: see Section 
•V (valid) flag, bit 11 — Enables the register pair when set; disables register pair when clear.
Before attempting to access these SMRR registers, software  must test bit 11 in the IA32_MTRRCAP register. If 
SMRR is not supported, reads from or writes to registers cause general-protection exceptions.
When the valid flag in the IA32_SMRR_PHYSMASK MSR is 1,  accesses to the specified address range are treated as 
follows:
•If the logical processor is in SMM, accesses uses  the memory type in the IA32_SMRR_PHYSBASE MSR.
•If the logical processor is not in SMM, write accesses are ignored and read accesses return a fixed value for each 
byte. The uncacheable memory type (UC) is used in this case.
The above items apply even if the address range spec ified overlaps with a range specified by the MTRRs.
12.11.3 Example Base and Mask Calculations
The examples in this section apply to processors that su pport a maximum physical address size of 36 bits. The base 
and mask values entered in variable-range MTRR pairs are 24-bit values that the processor extends to 36-bits. 
For example, to enter a base address of 2 MBytes (20000 0H) in the IA32_MTRR_PHYSBASE3 register, the 12 least-
significant bits are truncated and the value 000200H is ente red in the PhysBase field. The same operation must be 
performed on mask values. For example, to map the address range from 200000H to 3FFFFFH (2 MBytes to 4 
MBytes), a mask value of FFFE00000H is required. Again, th e 12 least-significant bits of this mask value are trun-
cated, so that the value entered in the PhysMask field of IA32_MTRR_PHYSMASK3 is FFFE 00H. This mask is chosen 
so that when any address in the 200000H to 3FFFFFH range is  AND’d with the mask value, it will return the same 
value as when the base address is AND’d with the mask value (which is 200000H).Figure 12-8.  IA32_SMRR_PHYSBASE and IA32_SMRR_PHYSMASK SMRR PairV — ValidPhysMask — Sets range maskIA32_SMRR_PHYSMASK Register
63 0
V Reserved31
PhysMaskType — Memory type for rangePhysBase — Base address of rangeIA32_SMRR_PHYSBASE Register
63 0
Type31
ReservedVol. 3A 12-27MEMORY CACHE CONTROL
To map the address range from 400000H to 7FFFFFH (4 MByt es to 8 MBytes), a base value of 000400H is entered 
in the PhysBase field and a mask value of  FFFC00H is entered in the PhysMask field.
Example 12-2.  Setting-Up Memory for a System
Here is an example of setting up the MTRRs for an syst em. Assume that the system has the following characteris-
tics:
•96 MBytes of system memory is mapped as write- back memory (WB) for highest system performance.
•A custom 4-MByte I/O card is mapped to uncached me mory (UC) at a base ad dress of 64 MBytes. This 
restriction forces the 96 MBytes of system memory to be addressed from 0 to 64 MBytes and from 68 MBytes 
to 100 MBytes, leaving a 4-MByte hole for the I/O card. 
•An 8-MByte graphics card is mapped to write-combin ing memory (WC) beginning at address A0000000H. 
•The BIOS area from 15 MBytes to 16 MBytes is mapped to UC memory.
The following settings for the MTRRs will yield the proper mapping of the physical address space for this system 
IA32_MTRR_PHYSBASE0 =  0000 0000 0000 0006H
IA32_MTRR_PHYSMASK0 =  0000 000F FC00 0800H  Caches 0-64 MByte as WB cache type.
IA32_MTRR_PHYSBASE1 =  0000 0000 0400 0006H
IA32_MTRR_PHYSMASK1 =  0000 000F FE00 0800H  Caches 64-96 MByte as WB cache type.
IA32_MTRR_PHYSBASE2 =  0000 0000 0600 0006H
IA32_MTRR_PHYSMASK2 =  0000 000F FFC0 0800H  Caches 96-100 MByte as WB cache type.
IA32_MTRR_PHYSBASE3 =  0000 0000 0400 0000H
IA32_MTRR_PHYSMASK3 =  0000 000F FFC0 0800H  Caches 64-68 MByte as UC cache type.
IA32_MTRR_PHYSBASE4 =  0000 0000 00F0 0000H
IA32_MTRR_PHYSMASK4 =  0000 000F FFF0 0800H  Caches 15-16 MByte as UC cache type.
IA32_MTRR_PHYSBASE5 =  0000 0000 A000 0001H
IA32_MTRR_PHYSMASK5 =  0000 000F FF80 0800H  Caches A0000000-A0800000 as WC type.
This MTRR setup uses the ability to overlap any two memory  ranges (as long as the ranges are mapped to WB and 
UC memory types) to minimize the number of MTRR regist ers that are required to configure the memory environ-
ment. This setup also fulfills the requirement that tw o register pairs are left for operating system usage.
12.11.3.1  Base and Mask Calculations for Greater-Than 36-bit Ph ysical Address Support
For Intel 64 and IA-32 processors that support greater than  36 bits of physical address size, software should query 
CPUID.80000008H to determine the maximu m physical address. See the example.
Example 12-3.  Setting-Up Memory for a System with a 40-Bit Address Size
If a processor supports 40-bits of physical address size, then the PhysMask field (in IA32_MTRR_PHYSMASK n 
registers) is 28 bits instead of 24 bits. For this si tuation, Example 12-2 should  be modified as follows:
IA32_MTRR_PHYSMASK0 =  0000 00FF FC00 0800H  Caches 0-64 MByte as WB cache type.12-28 Vol. 3AMEMORY CACHE CONTROL
IA32_MTRR_PHYSMASK1 =  0000 00FF FE00 0800H  Caches 64-96 MByte as WB cache type.
IA32_MTRR_PHYSMASK2 =  0000 00FF FFC0 0800H  Caches 96-100 MByte as WB cache type.
IA32_MTRR_PHYSMASK3 =  0000 00FF FFC0 0800H  Caches 64-68 MByte as UC cache type.
IA32_MTRR_PHYSMASK4 =  0000 00FF FFF0 0800H  Caches 15-16 MByte as UC cache type.
IA32_MTRR_PHYSMASK5 =  0000 00FF FF80 0800H  Caches A0000000-A0800000 as WC type.
12.11.4 Range Size and Alignment Requirement
A range that is to be mapped to a variable-range MTRR mu st meet the following “power of 2” size and alignment 
rules:
1. The minimum range size is 4 KBytes and the base ad dress of the range must be on at least a 4-KByte
boundary.
2. For ranges greater than 4 KBytes, each range must be of length 2n and its base address must be aligned on a 
2n boundary, where  n is a value equal to or greater than 12. The base-address alignment value cannot be less 
than its length. For example, an 8-KByte range cannot be aligned on a 4-KByte boundary. It must be aligned on 
at least an 8-KByte boundary.
12.11.4.1  MTRR Precedences
If the MTRRs are not enabled (by setting the E flag in  the IA32_MTRR_DEF_TYPE MSR), then all memory accesses 
are of the UC memory type. If the MTRRs are enabled, th en the memory type used for a memory access is deter-
mined as follows:
1. If the physical address falls within the first 1 MByt e of physical memory and fixed MTRRs are enabled, the
processor uses the memory type stored for the appropriate fixed-range MTRR.
2. Otherwise, the processor attempts to match the physical  address with a memory type set by the variable-range 
MTRRs:
— If one variable memory range matches, the pr ocessor uses the memory type stored in the 
IA32_MTRR_PHYSBASE n register for that range.
— If two or more variable memory ranges match and the memory types are identical, then that memory type 
is used.
— If two or more variable memory ranges match and one of the memory types is UC, the UC memory type 
used.
— If two or more variable memory ranges match and th e memory types are WT and WB, the WT memory type 
is used.

MTRRs:
is used.
used.
is used.
— For overlaps not defined by the above rules, processor behavior is undefined.
3. If no fixed or variable memory range matche s, the processor uses the default memory type.Vol. 3A 12-29MEMORY CACHE CONTROL
12.11.5 MTRR Initialization
On a hardware reset, the P6 and more recent processors clear the valid flags in variab le-range MTRRs and clear the 
E flag in the IA32_MTRR_DEF_TYPE MSR to disable a ll MTRRs. All other bits in the MTRRs are undefined. 
Prior to initializing the MTRRs, software (normally the sy stem BIOS) must initialize all fixed-range and variable-
range MTRR register fields to 0. Software can then in itialize the MTRRs according to known types of memory, 
including memory on devices that it auto-configures. Initia lization is expected to occur prior to booting the oper-
ating system.
See Section 12.11.8, “MTRR Considerations in MP Systems, ” for information on initializing MTRRs in MP (multiple-
processor) systems.
12.11.6 Remapping Memory Types
A system designer may re-map memory types to tune performance or because a future processor may not imple-
ment all memory types supported by the Pentium 4, Inte l Xeon, and P6 family processors. The following rules 
support coherent memory-type re-mappings:
1. A memory type should not be mapped into another me mory type that has a weaker memory ordering model.
For example, the uncacheable type cannot be mapped in to any other type, and the write-back, write-through,
and write-protected types cannot be mapped in to the weakly ordered write-combining type.
2. A memory type that does not delay writes should not be mapped into a memory type that does delay writes, 
because applications of such a memory type may rely on its write-through behavior. Accordingly, the write-
back type cannot be mapped into the write-through type.
3. A memory type that views write data as not necessarily  stored and read back by a subsequent read, such as 
the write-protected type, can only be mapped to another type with the same behavior (and there are no others 
for the Pentium 4, Intel Xeon, and P6 family processors) or to the uncacheable type.
In many specific cases, a system designer can have ad ditional information about how a memory type is used, 
allowing additional mappings. For example, write-through memory with no associated write side effects can be 
mapped into write-back memory.
12.11.7 MTRR Maintenance Programming Interface
The operating system maintains the MT RRs after booting and sets up or changes the memory types for memory-
mapped devices. The operating system should provide a driver and application prog ramming interface (API) to 
access and set the MTRRs. The function calls MemTypeGet() and MemTypeSet() define this interface.
12.11.7.1  MemTypeGet() Function
The MemTypeGet() function returns the memory type of th e physical memory range specified by the parameters 
base and size. The base address is the starting physical ad dress and the size is the number of bytes for the memory 
range. The function automatically aligns the base address and size to 4-KByte boundaries. Pseudocode for the 
MemTypeGet() function is given in Example 12-4.12-30 Vol. 3AMEMORY CACHE CONTROL
Example 12-4.  MemTypeGet() Pseudocode
#define MIXED_TYPES -1     /* 0 < MIXED_TYPES || MIXED_TYPES > 256 */
IF CPU_FEATURES.MTRR /* processor supports MTRRs */
THEN
Align BASE and SIZE to 4-KByte boundary;IF (BASE + SIZE) wrap physical-address space 
THEN return INVALID;
FI;IF MTRRdefType.E = 0
THEN return UC;
FI;FirstType 
:= Get4KMemType (BASE);
/* Obtains memory type fo r first 4-KByte range. */
/* See Get4KMemType (4KByteRange) in Example 12-5. */FOR each additional 4-KByte range specified in SIZE
NextType := Get4KMemType (4KByteRange);IF NextType != FirstType
THEN return Mixed_Types;
FI;
ROF;
return FirstType;
ELSE return UNSUPPORTED;
FI;
If the processor does not support MTRRs, the function re turns UNSUPPORTED. If the MTRRs are not enabled, then 
the UC memory type is returned. If more than one memory  type corresponds to the specified range, a status of 
MIXED_TYPES is returned. Otherwise, the memory type  defined for the range (UC, WC, WT, WB, or WP) is 
returned.
The pseudocode for the Get4KMemType() function in Exampl e 12-5 obtains the memory type for a single 4-KByte 
range at a given physical address. The sample code de termines whether an PHY_ADDRESS falls within a fixed 
range by comparing the address with the known fixed ra nges: 0 to 7FFFFH (64-KByte regions), 80000H to BFFFFH 
(16-KByte regions), and C0000H to FFFFFH (4-KByte regions) . If an address falls within one of these ranges, the 
appropriate bits within one of its MTRRs determine the memory type.
Example 12-5.  Get4KMemType() Pseudocode
IF IA32_MTRRCAP.FIX AND MTRRdefType.FE /* fixed registers enabled */
THEN IF PHY_ADDRESS is within a fixed range
return IA32_MTRR_FIX.Type;
FI;FOR each variable-range MTRR in IA32_MTRRCAP.VCNT
IF IA32_MTRR_PHYSMASK.V = 0
THEN continue;
FI;IF (PHY_ADDRESS AND IA32 _MTRR_PHYSMASK.Mask) =
(IA32_MTRR_PHYSBASE.Base AND IA32_MTRR_PHYSMASK.Mask)
THEN
return IA32_MTRR_PHYSBASE.Type;
FI;
ROF;return MTRRdefType.Type;Vol. 3A 12-31MEMORY CACHE CONTROL
12.11.7.2  MemTypeSet() Function
The MemTypeSet() function in Example 12-6 sets a MTRR fo r the physical memory range specified by the parame-
ters base and size to the type specif ied by type. The base address and size are multiples of 4 KBytes and the size 
is not 0.
Example 12-6.  MemTypeSet Pseudocode
IF CPU_FEATURES.MTRR (* processor supports MTRRs *)
THEN
IF BASE and SIZE are not 4-KByte aligned or size is 0
THEN return INVALID; 
FI;IF (BASE + SIZE) wrap 4-GByte address space
FI;
IF TYPE is invalid for Pentium 4, Intel Xeon, and P6 family
processors
THEN return UNSUPPORTED; 
FI;IF TYPE is WC and not supported
FI;IF IA32_MTRRCAP.FIX is set AND range can be mapped using afixed-range MTRR
THEN
pre_mtrr_change();update affected MTRR;post_mtrr_change();
FI;
ELSE (* try to map using a variable MTRR pair *)
IF IA32_MTRRCAP.VCNT = 0
FI;IF conflicts with current variable ranges 
THEN return RANGE_OVERLAP;
FI;IF no MTRRs available
THEN return VAR_NOT_AVAILABLE; 
FI;IF BASE and SIZE do not meet the power of 2 requirements forvariable MTRRs
THEN return INVALID_VAR_REQUEST; 
FI;pre_mtrr_change();Update affected MTRRs;post_mtrr_change();
FI;
pre_mtrr_change()
BEGIN
disable interrupts;Save current value of CR4;disable and flush caches;12-32 Vol. 3AMEMORY CACHE CONTROL
flush TLBs;
disable MTRRs;IF multiprocessing
THEN maintain consistency through IPIs;
FI;
END
post_mtrr_change()
BEGIN
flush caches and TLBs;enable MTRRs;enable caches;restore value of CR4;enable interrupts;
END
The physical address to variable range mapping algorith m in the MemTypeSet function detects conflicts with 
current variable range registers by cycling through them and determining whether the physical address in question 
matches any of the current ranges. During this scan, the algorithm can detect whether any current variable ranges 
overlap and can be concatenated into a single range.
The pre_mtrr_change() function disables interrupts prior to  changing the MTRRs, to avoid executing code with a 
partially valid MTRR setup. The algorithm disables caching by setting the CD flag and clearing the NW flag in control 
register CR0. The caches are invalidated using the WBINVD instruction. The algorithm flushes all TLB entries either by clearing the page-global enable (PGE) flag in control re gister CR4 (if PGE was already set) or by updating control 
register CR3 (if PGE was already clear). Finally, it disables MTRRs by clearing the E flag in the 
IA32_MTRR_DEF_TYPE MSR.
After the memory type is updated, the post_mtrr_change () function re-enables the MTRRs and again invalidates 
the caches and TLBs. This second invalidation is required because of the processor's aggressive prefetch of both instructions and data. The algorithm restores interrupts and re-enables caching by setting the CD flag.
An operating system can batch multiple MTRR updates so that only a single pair of cache invalidations occur.
12.11.8 MTRR Considerations in MP Systems
In MP (multiple-processor) systems, the operating systems must maintain MTRR consistency between all the 
processors in the system. The Pentium 4, Intel Xeon, and P6 family processors provide no hardware support to 
maintain this consistency. In general, all processors must have the same MTRR values.
This requirement implies that when the operating system in itializes an MP system, it must load the MTRRs of the 
boot processor while the E flag in register MTRRdefType is 0. The operating system then directs other processors to 
load their MTRRs with the same memory map. After all the processors have loaded their MTRRs, the operating 
system signals them to enable their MTRRs. Barrier sync hronization is used to prevent further memory accesses 
until all processors indicate that the MTRRs are enabled. This synchronization is likely to be a shoot-down style

until all processors indicate that the MTRRs are enabled. This synchronization is likely to be a shoot-down style 
algorithm, with shared variables and interprocessor interrupts.
Any change to the value of the MTRRs in an MP system requires the operating system to repeat the loading and 
enabling process to maintain consistency, using the following procedure:
1. Broadcast to all processors to execute the following code sequence.
2. Disable interrupts.
3. Wait for all processors to reach this point.4. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and the NW flag to 0.)
5. Flush all caches using the WBINVD instructions. On a processor that supports self-snooping (enumerating 
CPUID.01H:EDX.SS[bit 27] as 1), this step may be unnece ssary. However, if there are changes for which self-
snooping behavior would be problematic (e.g., changing the memory type of a cache line from WB to UC for 
memory-mapped I/O), execution of WBINVD would still be required.Vol. 3A 12-33MEMORY CACHE CONTROL
6. If either the PGE or PCIDE flag is set in control register CR4, flush all TLBs by clearing one or both of these flags.
7. If the PGE and PCIDE flags are both clear in control regi ster CR4, flush all TLBs by executing a MOV from control 
register CR3 to another register and then a MOV from that register back to CR3.
8. Disable all range registers (by clearing the E flag in re gister MTRRdefType). If only variable ranges are being 
modified, software may clear the valid bits for the affected register pairs instead.
9. Update the MTRRs.
10. Enable all range registers (by setting the E flag in regi ster MTRRdefType). If only variable-range registers were 
modified and their individual valid bi ts were cleared, then set the valid bits for the affected ranges instead.
11. Flush all caches and all TLBs a second time. (The TLB fl ush is required for Pentium 4, Intel Xeon, and P6 family 
processors. Executing the WBINVD instruction is not need ed when using Pentium 4, Intel Xeon, and P6 family 
processors, but it may be needed in future systems.)
12. Enter the normal cache mode to re-enable caching. (Set the CD and NW flags in control register CR0 to 0.)
13. Restore the values of the PGE and/or PCIDE flags in control register CR4, if cleared in Step 6 (above).
14. Wait for all processors to reach this point.15. Enable interrupts.
12.11.9 Large Page Size Considerations
The MTRRs provide memory typing for a limited number of re gions that have a 4 KByte granularity (the same gran-
ularity as 4-KByte pages). The memory type for a given page is cached in the processor’s TLBs. When using large 
pages (2 MBytes, 4 MBytes, or 1 GBytes), a single page-table entry covers multiple 4-KByte granules, each with a 
single memory type. Because the memory type for a large pa ge is cached in the TLB, the processor can behave in 
an undefined manner if a large page is mapped to a re gion of memory that MTRRs have mapped with multiple 
memory types. 
Undefined behavior can be avoided by ensuring that all MTRR memory-type ranges within a large page are of the 
same type. If a large page maps to a region of memory containing different MTRR-defined memory types, the PCD 
and PWT flags in the page-table entry should be set for the most conservative memory type for that range. For 
example, a large page used for memory mapped I/O and re gular memory is mapped as UC memory. Alternatively, 
the operating system can map the region using multiple 4-KByte pages each with its own memory type. 
The requirement that all 4-KByte ranges in a large page ar e of the same memory type implies that large pages with 
different memory types may suffer a performance penalty,  since they must be marked  with the lowest common 
denominator memory type. The same consideration apply to 1 GByte pages, each of which may consist of multiple 
2-Mbyte ranges. 
The Pentium 4, Intel Xeon, and P6 family processors prov ide special support for the physical memory range from 0 
to 4 MBytes, which is potentially mapped by both the fi xed and variable MTRRs. This support is invoked when a 
Pentium 4, Intel Xeon, or P6 family processor detects a large page overlapping the first 1 MByte of this memory 
range with a memory type that conflicts with the fixe d MTRRs. Here, the processor maps the memory range as 
multiple 4-KByte pages within the TLB. This operation en sures correct behavior at the cost of performance. To 
avoid this performance penalty, operating-system software  should reserve the large page option for regions of 
memory at addresses greater than or equal to 4 MBytes.
12.12 PAGE ATTRIBUTE TABLE (PAT)
The Page Attribute Table (PAT) extends the IA-32 architectu re’s page-table format to allow memory types to be 
assigned to regions of physical memory based on linear address mappings. The PAT is a companion feature to the 
MTRRs; that is, the MTRRs allow mapping of memory types to regions of the physical address space, where the PAT 
allows mapping of memory types to pages within the line ar address space. The MTRRs are useful for statically 
describing memory types for physical ranges, and are typi cally set up by the system BIOS. The PAT extends the 
functions of the PCD and PWT bits in page tables to allow al l five of the memory types that can be assigned with the 
MTRRs (plus one additional memory type) to also be a ssigned dynamically to pages of the linear address space.12-34 Vol. 3AMEMORY CACHE CONTROL
The PAT was introduced to IA-32 architecture on the Pentium III processor. It is also available in the Pentium 4 and 
Intel Xeon processors.
12.12.1 Detecting Support for the PAT Feature
An operating system or executive can detect the availabili ty of the PAT by executing the CPUID instruction with a 
value of 1 in the EAX register. Support for the PAT is indica ted by the PAT flag (bit 16 of the values returned to EDX 
register). If the PAT is supported, the operating system or executive can use the IA32_PAT MSR to program the PAT. 
When memory types have been assigned to entries in the PAT, software can then use of the PAT-index bit (PAT) in 
the page-table and page-directory entries along with the PCD and PWT bits to assign memory types from the PAT 
to individual pages.
Note that there is no separate flag or control bit in any of the control registers that enables the PAT. The PAT is 
always enabled on all processors that support it, and the table lookup always occurs whenever paging is enabled, 
in all paging modes.
12.12.2 IA32_PAT MSR
The IA32_PAT MSR is located at MSR address 277H (see Chapter 2, “Model-Specific Registers (MSRs)‚” in the 
Intel® 64 and IA-32 Architectures Software Developer’s Manu al, Volume 4). Figure 12-9. shows the format of the 
64-bit IA32_PAT MSR.
The IA32_PAT MSR contains eight page attribute fields: PA0 through PA7. The three low-order bits of each field are 
used to specify a memory type. The five high-order bits of  each field are reserved, and must be set to all 0s. Each 
of the eight page attribute fields can contain any of  the memory type encodings specified in Table 12-10.
Note that for the P6 family processors, the IA32_PAT MSR is named the PAT MSR.31 27 26 24 23 19 18 16 15 11 10 8 7 3 2 0
63 59 58 56 55 51 50 48 47 43 42 40 39 35 34 32
Figure 12-9.  IA32_PAT MSR
Table 12-10.  Memory Types Th at Can Be Encoded With PAT
Encoding Mnemonic
00H Uncacheable (UC)
01H Write Combining (WC)02H Reserved*
03H Reserved*
04H Write Through (WT)05H Write Protected (WP)
06H Write Back (WB)
07H Uncached (UC-)
08H - FFH Reserved*
NOTE:
* Using these encodings will result in a general-protection exception (#GP).Vol. 3A 12-35MEMORY CACHE CONTROL
12.12.3 Selecting a Memory Type from the PAT
To select a memory type for a page from the PAT, a 3-bi t index made up of the PAT, PCD, and PWT bits must be 
encoded in the page-table or page-directory entry for the page. Table 12-11 shows the possible encodings of the 
PAT, PCD, and PWT bits and the PAT entry selected with each  encoding. The PAT bit is bit 7 in page-table entries that 
point to 4-KByte pages and bit 12 in paging-structure entr ies that point to larger pages. The PCD and PWT bits are 
bits 4 and 3, respectively, in paging-structu re entries that point to pages of any size.
The PAT entry selected for a page is used in conjunction with the MTRR setting for the region of physical memory 
in which the page is mapped to determine the effect ive memory type for the page, as shown in Table 12-7.
12.12.4 Programming the PAT
Table 12-12 shows the default setting for each PAT entry follo wing a power up or reset of the processor. The setting 
remain unchanged following a soft reset (INIT reset). 
The values in all the entries of the PAT can be changed by writing to the IA32_PAT MSR using the WRMSR instruc-
tion. The IA32_PAT MSR is read and write accessible (use of the RDMSR and WRMSR instructions, respectively) to 
software operating at a CPL of 0. Table 12-10 shows the allo wable encoding of the entries in the PAT. Attempting to

software operating at a CPL of 0. Table 12-10 shows the allo wable encoding of the entries in the PAT. Attempting to 
write an undefined memory type encodi ng into the PAT causes a general-prot ection (#GP) exception to be gener-
ated.
The operating system (OS) is responsible for ensuring th at changes to a PAT entry occur in a manner that main-
tains the consistency of the processor caches and translatio n lookaside buffers (TLB). It requires the OS to invali-
date all affected TLB entries (including global entries) an d all entries in all paging-structure caches. It may also 
require flushing of the processor caches in certain situat ions. This can be accomplished in various ways, including 
the sequence below or by following the procedure specif ied in Section 12.11.8, “MTRR Considerations in MP 
Systems.” (See Section 4.10.4, “Invalidation of TLBs an d Paging-Structure Caches” for additional background 
information.) Also note that in a multi-processor environmen t, it is the software's resp onsibility to resolve differ-
ences in conflicting memory types across logical processors  that may arise from changes to the PAT (e.g., if two Table 12-11.  Selection of PAT Entr ies with PAT, PCD, and PWT Flags
PAT PCD PWT PAT Entry
000 P A T 0
001 P A T 1
010 P A T 2011 P A T 3
100 P A T 4
101 P A T 5
110 P A T 6
111 P A T 7
Table 12-12.  Memory Type Setting of PA T Entries Following a Power-up or Reset 
PAT Entry Memory Type Following Power-up or Reset
PAT0 WBPAT1 WT
PAT2 UC-
PAT3 UCPAT4 WB
PAT5 WT
PAT6 UC-PAT7 UC12-36 Vol. 3AMEMORY CACHE CONTROL
logical processors map a linear address to the same physical address but have PATs that specify a different memory 
type for that physical address).
Example of a sequence to invalidate the processor TLBs and caches (if necessary):
1. If the PCIDE or PGE flag is set in CR4, flush TLBs by  clearing one of those flags (then restore the flag via a 
subsequent CR4 write).
Otherwise, flush TLBs by executing a MOV from control register CR3 to another register and then a MOV from 
that register back to CR3.
2. In the case that there are changes to memory-type ma ppings for which cache self-snooping behavior would be 
problematic given the existing mappings (e.g., changing a cache line's memory type from WB to UC to be used for memory-mapped I/O), then cache flushing is also  required. This can be done by executing CLFLUSH 
operations for all affected cache lines or by executing the WBINVD instruction (recommended only if there are 
a large number of affected mappings or if it  is unknown which mappings are affected).
The PAT allows any memory type to be specified in the page tables, and therefore it is possible to have a single 
physical page mapped to two or more different linear addr esses, each with different me mory types. Intel does not 
support this practice because it may lead to undefined oper ations that can result in a system failure. In particular, 
a WC page must never be aliased to a cacheable page because WC writes may not check the processor caches.
When remapping a page that was previously mapped as a cacheable memory type to a WC page, an operating 
system can avoid this type of aliasing by doing the following:
1. Remove the previous mapping to a cacheable memory type in the page tables; that is, make them not
present.
2. Flush the TLBs of processors that may ha ve used the mapping, even speculatively.
3. Create a new mapping to the same physical ad dress with a new memory type, for instance, WC.
4. Flush the caches on all processors that may have used the mapping previously. Note on processors that support 
self-snooping, CPUID feature flag bit 27, this step is unnecessary.
Operating systems that use a page directory as a page tabl e (to map large pages) and enable page size extensions 
must carefully scrutinize the use of the PAT index bit fo r the 4-KByte page-table entries. The PAT index bit for a 
page-table entry (bit 7) corresponds to the page size bit in a page-directory entry. Th erefore, the operating system 
can only use PAT entries PA0 through PA3 when setting the cach ing type for a page table that is also used as a page 
directory. If the operating system attempts to use PAT entries PA4 through PA7 when using this memory as a page 
table, it effectively sets the PS bit for th e access to this memory as a page directory.
For compatibility with earlier IA-32 processors that do not support the PAT, care should be taken in selecting the 
encodings for entries in the PAT (see Section 12.12.5, “PAT Compatibility with Earlier IA-32 Processors”).
12.12.5 PAT Compatibility with Earlier IA-32 Processors
For IA-32 processors that support the PAT, the IA32_PAT MS R is always active. That is, the PCD and PWT bits in 
page-table entries and in page-directory entries (that poin t to pages) are always select a memory type for a page 
indirectly by selecting an entry in the PAT. They never se lect the memory type for a page directly as they do in 
earlier IA-32 processors that do not implement the PAT (see Table 12-6).
To allow compatibility for code written to run on earlier IA-32 processor that do not support the PAT, the PAT mech-
anism has been designed to allow backward compatibility to earlier processors. This compatibility is provided 
through the ordering of the PAT, PCD, and PWT bits in th e 3-bit PAT entry index. For processors that do not imple-
ment the PAT, the PAT index bit (bit 7 in the page-table entr ies and bit 12 in the page-dir ectory entries) is reserved 
and set to 0. With the PAT bit reserved, only the first four  entries of the PAT can be selected with the PCD and PWT 
bits. At power-up or reset (see Table 12-12), these first fo ur entries are encoded to select the same memory types 
as the PCD and PWT bits would normally select directly in  an IA-32 processor that does not implement the PAT. So, 
if encodings of the first four entries in the PAT are left unc hanged following a power-up or reset, code written to run 
on earlier IA-32 processors that do not implement the PAT will run correctly on IA-32 pr ocessors that do implement 
the PAT.Vol. 3A 13-1CHAPTER 13
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
This chapter describes those features of the Intel® MMX™ technology that must be  considered when designing or 
enhancing an operating system to support MMX technolo gy. It covers MMX instruction set emulation, the MMX 
state, aliasing of MMX registers, saving MMX state, task  and context switching considerations, exception handling, 
and debugging.
13.1 EMULATION OF THE MMX INSTRUCTION SET
The IA-32 or Intel 64 architecture does not support emul ation of the MMX instructions, as it does for x87 FPU 
instructions. The EM flag in control register CR0 (provide d to invoke emulation of x87 FPU instructions) cannot be 
used for MMX instruction emulation. If an MMX instruction is  executed when the EM flag is set, an invalid opcode 
exception (UD#) is generated. Table 13-1 shows the interact ion of the EM, MP, and TS flags in control register CR0 
when executing MMX instructions.
13.2 THE MMX STATE AND MMX REGISTER ALIASING
The MMX state consists of eight 64-bit registers (MM0 th rough MM7). These registers are aliased to the low 64-bits 
(bits 0 through 63) of floating-point registers R0 throug h R7 (see Figure 13-1). Note that the MMX registers are 
mapped to the physical locations of the floating-point regi sters (R0 through R7), not to the relative locations of the 
registers in the floating-point register stack (ST0 throug h ST7). As a result, the MMX register mapping is fixed and 
is not affected by value in the Top Of Stack (TOS) field in the floating-point status word (bits 11 through 13).Table 13-1.  Action Taken By MMX Instructions  for Different Combinations of EM, MP, and TS
CR0 Flags
EM MP* TS Action
0 1 0 Execute.011 # N M  e x c e p t i o n .
110 # U D  e x c e p t i o n .
111 # U D  e x c e p t i o n .
NOTE:
* For processors that supp ort the MMX instructions, th e MP flag should be set.13-2 Vol. 3AINTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
When a value is written into an MMX register using an MMX  instruction, the value also appears in the corresponding 
floating-point register in bits 0 through 63. Likewise, wh en a floating-point value written into a floating-point 
register by a x87 FPU, the low 64 bits of that va lue also appears in a the corresponding MMX register.
The execution of MMX instructions have several side effe cts on the x87 FPU state contained in the floating-point 
registers, the x87 FPU tag word, and the x87 FPU status word. These side effects are as follows:
•When an MMX instruction writes a value into an MMX regi ster, at the same time, bits 64 through 79 of the corre-
sponding floating-point register are set to all 1s.
•When an MMX instruction (other than the EMMS instruction) is executed, ea ch of the tag fields in the x87 FPU 
tag word is set to 00B (valid). (See also Section 13.2.1, “Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR 
Instructions on the x87 FPU Tag Word.”)
•When the EMMS instruction is executed, each tag fi eld in the x87 FPU tag word is set to 11B (empty).

•Each time an MMX instruction is executed, the TOS value is set to 000B.
Execution of MMX instructions does not affect the other bits  in the x87 FPU status word (bits 0 through 10 and bits 
14 and 15) or the contents of the other x87 FPU register s that comprise the x87 FPU state (the x87 FPU control 
word, instruction pointer, data pointer, or opcode registers). 
Table 13-2 summarizes the effects of th e MMX instructions on the x87 FPU state.Figure 13-1.  Mapping of MMX Registers to Floating-Point Registers0 79
R7
R6
R5
R4
R3
R2
R1
R0Floating-Point Registers6463
x87 FPU Status Register
1113x87 FPU Tag
TOSRegister
0
MM7
MM6
MM5
MM4
MM3
MM2
MM1
MM063
TOS = 000
00
00
00
00
00
00
00
000Vol. 3A 13-3INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
13.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag 
Word
Table 13-3 summarizes the effect of MMX and x87 FPU instructions and the FXSAVE and FXRSTOR instructions on 
the tags in the x87 FPU tag word and the corresponding tags in an image of the tag word stored in memory.
The values in the fields of the x87 FPU tag word do not af fect the contents of the MMX registers or the execution of 
MMX instructions. However, the MMX instructions do modify  the contents of the x87 FPU tag word, as is described 
in Section 13.2, “The MMX State and MMX Register Aliasing .” These modifications may affect the operation of the 
x87 FPU when executing x87 FPU instructions, if the x87 FPU state is not initialized or restored prior to beginning 
x87 FPU instruction execution.
Note that the FSAVE, FXSAVE, and FSTE NV instructions (which save x87 FPU state information) read the x87 FPU 
tag register and contents of each of the floating-point re gisters, determine the actual tag values for each register 
(empty, nonzero, zero, or special), and store the updated tag word in memory. After executing these instructions, 
all the tags in the x87 FPU tag word are set to empty (11B ). Likewise, the EMMS instruction clears MMX state from 
the MMX/floating-point registers by setting a ll the tags in the x87 FPU tag word to 11B.
13.3 SAVING AND RESTORING THE MMX STATE AND REGISTERS
Because the MMX registers are aliased to the x87 FPU data  registers, the MMX state can be saved to memory and 
restored from memory as follows:Table 13-2.  Effects of MMX In structions on x87 FPU State
MMX Instruction 
Typex87 FPU Tag 
WordTOS Field of x87 
FPU Status WordOther x87 FPU 
RegistersBits 64 Through 79 
of x87 FPU Data RegistersBits 0 Through 63 
of x87 FPU Data Registers
Read from MMX 
registerAll tags set to 00B 
(Valid)000B Unchanged Unchanged Unchanged
Write to MMX 
(Valid)000B Unchanged Set to a ll 1s Overwritten with 
MMX data
EMMS All fields set to 
11B (Empty)000B Unchanged Unchanged Unchanged
Table 13-3.  Effect of the MMX , x87 FPU, and FXSAVE/FXRSTOR Instructions on the x87 FPU Tag Word
TypeInstruction x87 FPU Tag Word Image of x87 FPU Tag Word Stored in 
Memory
MMX All (except EMMS) All tags are se t to 00B (valid). Not affected.
MMX EMMS All tags are set to 11B (empty). Not affected.
x87 FPU All (except FSAVE, 
FSTENV, FRSTOR, 
FLDENV)Tag for modified floating-point register is 
set to 00B or 11B.Not affected.
x87 FPU and 
FXSAVEFSAVE, FSTENV, FXSAVE Tags and register values are read and 
interpreted; then all tags are set to 11B.Tags are set accord ing to the actual 
values in the floating-point registers; 
that is, empty registers are marked 11B and valid registers are marked 00B 
(nonzero), 01B (zero) , or 10B (special).
x87 FPU and 
FXRSTORFRSTOR, FLDENV, 
FXRSTORAll tags marked 11B in memory are set 
to 11B; all other tags  are set according 
to the value in the corresponding floating-point register: 00B (nonzero), 
01B (zero), or 10B (special).Tags are read and interpreted, but not 
modified.13-4 Vol. 3AINTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
•Execute an FSAVE, FNSAVE, or FXSAVE instruction to sa ve the MMX state to memory. (The FXSAVE instruction 
also saves the state of the XMM and MXCSR registers.)
•Execute an FRSTOR or FXRSTOR instruction to restore the MMX state from memory. (The FXRSTOR instruction also restores the state of the XMM and MXCSR registers.)
The save and restore methods described above are requir ed for operating systems (s ee Section 13.4, “Saving MMX 
State on Task or Context Switches”). Applications can in some cases save and restore only the MMX registers in the 
following way:
•Execute eight MOVQ instructions to save the conten ts of the MMX0 through MMX7 registers to memory. An 
EMMS instruction may then (optionally) be executed to clear the MMX state in the x87 FPU.
•Execute eight MOVQ instructions to read the saved co ntents of MMX registers from memory into the MMX0 
through MMX7 registers.
NOTE
The IA-32 architecture does not support scanning the x87 FPU tag word and then only saving valid entries.
13.4 SAVING MMX STATE ON TASK OR CONTEXT SWITCHES
When switching from one task or context to another, it is  often necessary to save the MMX state. As a general rule, 
if the existing task switching code for an operating system  includes facilities for saving the state of the x87 FPU, 
these facilities can also be relied upon to save the MMX stat e, without rewriting the task switch code. This reliance 
is possible because the MMX state is aliased to the x 87 FPU state (see Section 13.2, “The MMX State and MMX 
Register Aliasing”).
With the introduction of the FXSAVE and FXRSTOR instru ctions and of SSE/SSE2/SSE3/SSSE3 extensions, it is 
possible (and more efficient) to create state saving faciliti es in the operating system or executive that save the x87 
FPU/MMX/SSE/SSE2/SSE3/SSSE3 state in one operation. Se ction 14.4, “Designing OS Facilities for Saving x87 
FPU, SSE, AND EXTENDED States on Task or Context Switch es,” describes how to design such facilities. The tech-
niques describes in this section can be adapted to  saving only the MMX and x87 FPU state if needed.
13.5 EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS
MMX instructions do not generate x87 FPU floating-point exceptions, nor do they affect the processor’s status flags 
in the EFLAGS register or the x87 FPU status word. The fo llowing exceptions can be generated during the execution 
of an MMX instruction:
•Exceptions during memory accesses:
— Stack-segment fault (#SS).
— General protection (#GP).
— Page fault (#PF).— Alignment check (#AC), if alignment checking is enabled.
•System exceptions:
— Invalid Opcode (#UD), if the EM flag in control regist er CR0 is set when an MMX instruction is executed (see 
Section 13.1, “Emulation of the MMX Instruction Set”).
— Device not available (#NM), if an MMX instruction is ex ecuted when the TS flag in control register CR0 is 
set. (See Section 14.4.1, “Using the TS Flag to Control the Saving of the x87 FPU and SSE State.”)
•Floating-point error (#MF). (See Section 13.5.1, “Effect  of MMX Instructions on Pending x87 Floating-Point 
Exceptions.”)
•Other exceptions can occur indirectly due to the faulty execution of the exception handlers for the above exceptions.Vol. 3A 13-5INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
13.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions
If an x87 FPU floating-point exception is pending and th e processor encounters an MMX instruction, the processor 
generates a x87 FPU floating-point error (#MF) prior to ex ecuting the MMX instruction, to allow the pending excep-
tion to be handled by the x87 FPU floating-point error exce ption handler. While this exception handler is executing, 
the x87 FPU state is maintained and is visible to the hand ler. Upon returning from the exception handler, the MMX 
instruction is executed, which will alter the x87 FPU state,  as described in Section 13.2, “The MMX State and MMX 
Register Aliasing.” 
13.6 DEBUGGING MMX CODE
The debug facilities operate in the same manner when executing MMX instructions as when executing other IA-32 or Intel 64 architecture instructions.
To correctly interpret the contents of the MMX or x87 FPU registers from the FSAVE/FNSAVE or FXSAVE image in 
memory, a debugger needs to take account of the relati onship between the x87 FPU register’s logical locations 
relative to TOS and the MMX register’s physical locations.
In the x87 FPU context, ST n refers to an x87 FPU register at location n relative to the TOS. However, the tags in the 
x87 FPU tag word are associated with the physical loca tions of the x87 FPU registers (R0 through R7). The MMX 
registers always refer to the physical locations of the registers (with MM0 through MM7 being mapped to R0 through R7). Figure 13-2 shows this relationship. Here, the inner circle refers to the physical location of the x87 
FPU and MMX registers. The outer circle refers to the x8 7 FPU register’s relative location to the current TOS.
When the TOS equals 0 (case A in Figure 13-2), ST0 points to  the physical location R0 on the floating-point stack.

When the TOS equals 0 (case A in Figure 13-2), ST0 points to  the physical location R0 on the floating-point stack. 
MM0 maps to ST0, MM1 maps to ST1, and so on.
When the TOS equals 2 (case B in Figure 13-2), ST0 points  to the physical location R2. MM0 maps to ST6, MM1 
maps to ST7, MM2 maps to ST0, and so on.
Figure 13-2.  Mapping of MMX Registers to x87 FPU Data Register StackMM0
MM1
MM2
MM3
MM4MM5MM6MM7ST1
ST2ST7ST0 ST6
ST7
ST1TOSTOSx87 FPU “push” x87 FPU “pop”x87 FPU “push”
x87 FPU “pop”
Case A: TOS=0Case B: TOS=2MM0
MM1
MM2
MM3
MM4MM5MM6MM7
ST0
Outer circle = x87 FPU data register’s  logical location relative to TOS
Inner circle = x87 FPU tags = MMX register’s location = FP register’s physical location(R0)
(R2)(R2)(R0)13-6 Vol. 3AINTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMINGVol. 3A 14-1CHAPTER 14
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND
PROCESSOR EXTENDED STATES
This chapter describes system programming features for instruction set extensions operating on the processor 
state extension known as the SSE state (XMM registers, MX CSR) and for other processor extended states. Instruc-
tion set extensions operating on the SSE state include the streaming SIMD extensions (SSE), streaming SIMD 
extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), Supplemental SSE3 (SSSE3), and SSE4. Collectively, 
these are called SSE extensions1 and the corresponding instructions are called SSE instructions . 
FXSAVE/FXRSTOR instructions can be used save/restore SSE state along with FP state. See Section 10.5 in the Intel
® 64 and IA-32 Architectures Software Developer’s Ma nual, Volume 1, for information about FXSAVE and 
FXRSTOR.
Sections 14.1 through 14.4 cover system programming requirements to enable th e SSE extensions, providing 
operating system or executive support for the SSE extensio ns, SIMD floating-point exceptions, exception handling, 
and task (context) switching. These sections primarily discuss use of FXSAVE/FXRSTOR to save/restore SSE state.
XSAVE feature set  refers to extensions to the Intel architecture that will allow system executives to implement 
support for multiple processor extended states along with FP/SSE states that may be introduced over time without 
requiring the system executive to be modified each ti me a new processor state extension is introduced. XSAVE 
feature set provide mechanisms to enumerate the supported extended states, enable some or all of them for soft-
ware use, instructions to save/restore the states and en umerate the layout of the states when saved to memory. 
XSAVE/XRSTOR instructions are part of the XSAVE feature set. These instructions are introduced after the intro-
duction of FP/SSE states but can be used to manage lega cy FP/SSE state along with processor extended states. See 
Chapter 13 in the Intel® 64 and IA-32 Architectures Software Develope r’s Manual, Volume 1, for information about 
XSAVE feature set.
System programming for managing processor extended stat es is described in sections 14.5 through 14.6. XSAVE 
feature set is designed to be compatible with FXSAVE/F XRSTOR and hence much of the material through sections 
14.1 to 14.4 related to SSE state also applies to XS AVE feature set with the exception of enumeration and 
saving/restoring state.
XSAVE Compaction  is an XSAVE feature that allows operating systems to allocate space for only the states saved 
to conserve memory usage. A new instruction called XSAVEC  is introduced to save extended states in compacted 
format and XRSTOR instruction is enhanced to comprehe nd compacted format. System programming for managing 
processor extended states in compacted format is also described in section 14.5.
Supervisor state  is an extended state that can only be accessed in ring 0. XSAVE feature set has been enhanced 
to manage supervisor states. Two new ring 0 instruct ions, XSAVES/XRSTORS, are introduced to save/restore 
supervisor states along with other XSAVE managed states . They are privileged instruction and only operate in 
compacted format. System programming for managing supervisor states in described in section 14.7.
Each XSAVE managed features may have additional featur e specific system programming requirements such as 
exception handlers etc. Feature specific system prog ramming requirements for XSAVE managed features are 
described in Section 14.8.
14.1 PROVIDING OPERATING SYSTEM SUPPORT FOR SSE EXTENSIONS
To use SSE extensions, the operating system or executive mu st provide support for initializing the processor to use 
these extensions, for handling SIMD floating-point exce ptions, and for using FXSAVE and FXRSTOR (Section 10.5 
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1) to manage context. XSAVE 
feature set can also be used to manage SSE state along wi th other processor extended states as described in 14.5. 
This section primarily focuses on using FXSAVE/FXRSTOR to manage SSE state. Because SSE extensions share the 
same state, experience the same sets of non-numerical and numerical exception behavior, these guidelines that 
1. The collection also includes PCLMULQDQ an d AES instructions operating on XMM state.14-2 Vol. 3ASYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
apply to SSE also apply to other sets of SIMD extensions  that operate on the same processor state and subject to 
the same sets of non-numerical and numerical exception behavior. 
Chapter 11, “Programming with Intel® Streaming SIMD Extensions 2 (Intel® SSE2)‚” and Chapter 12, “Program-
ming with Intel® SSE3, SSSE3, Intel® SSE4, and Intel® AES-NI,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 1, provid e details on the Intel SSE instruction set.
14.1.1 Adding Support to an Op erating System for SSE Extensions
The following guidelines describe functions that an oper ating system or executive must perform to support SSE 
extensions:
1. Check that the processor supports the SSE extensions.
2. Check that the processor supports the FXSAVE an d FXRSTOR instructions or the XSAVE feature set.
3. Provide an initialization for the SSE states.
4. Provide support for the FXSAVE and FXRSTOR instructions or the XSAVE feature set.
5. Provide support (if necessary) in non-numeric exception handlers for exceptions generated by the SSE instruc-
tions.
6. Provide an exception handler for the SIMD floating-point exception (#XM).
The following sections describe how to implement each of these guidelines.
14.1.2 Checking for CPU Support
If the processor attempts to execute an unsupported SS E instruction, the processor generates an invalid-opcode 
exception (#UD). Before an operating system or executiv e attempts to use SSE extensions, it should check that 
support is present by confirming  the following bit values retu rned by the CPUID instruction:
•CPUID.1:EDX.SSE[bit 25] = 1
•CPUID.1:EDX.SSE2[bit 26] = 1
•CPUID.1:ECX.SSE3[bit 0] = 1
•CPUID.1:ECX.SSSE3[bit 9] = 1
•CPUID.1:ECX.SSE4_1[bit 19] = 1
•CPUID.1:ECX.SSE4_2[bit 20] = 1
(To use POPCNT instruction, software must  check CPUID.1:ECX.POPCNT[bit 23] = 1.)
Separate checks must be made to ensure that the proc essor supports either FXSAVE and FXRSTOR or the XSAVE 
feature set. See Section 10.5 of the Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 1, and 
Chapter 13 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, respectively.
14.1.3 Initialization of the SSE Extensions
The operating system or executive should carry out the fo llowing steps to set up SSE extensions for use by appli-
cation programs:
1. Set CR4.OSFXSR[bit 9] = 1. Setting this flag implies that the operating system provides facilities for saving 
and restoring SSE state using FXSAVE and FXRSTOR instructions. These instructions may be used to save the SSE state during task switches and when invoking the SIMD floating-point exception (#XM) handler (see 
Section 14.1.5, “Providing a Handler for th e SIMD Floating-Point Exception (#XM)”). 
If the processor does not support the FXSAVE and FXRS TOR instructions, attempting to set the OSFXSR flag 
causes a general-protection exception (#GP) to be generated.Vol. 3A 14-3SYSTEM PROGRAMMING FOR INSTRUCTION SET EX TENSIONS AND PROCESSOR EXTENDED STATES
2. Set CR4.OSXMMEXCPT[bit 10] = 1. Setting this flag implies that the operating system provides a SIMD 
floating-point exception (#XM) handler (see Section 14.1 .5, “Providing a Handler for the SIMD Floating-Point 
Exception (#XM)”). 
NOTE
The OSFXSR and OSXMMEXCPT bits in control regi ster CR4 must be set by the operating system. 
The processor has no other way of detecting operating-system support for the FXSAVE and 
FXRSTOR instructions or for handling SIMD floating-point exceptions.
3. Clear CR0.EM[bit 2] = 0. This action disables emulation of the x87 FPU, which is required when executing SSE 
instructions (see Section 2.5, “Control Registers”).
4. Set CR0.MP[bit 1] = 1. This setting is required fo r Intel 64 and IA-32 proce ssors that support the SSE 
extensions (see Section 10.2.1, “Configuring the x87 FPU Environment”).

NOTE
Table 14-1 and Table 14-2 show the actions of the proce ssor when an SSE instruction is executed, depending on 
the following: 
•OSFXSR and OSXMMEXCPT flags in control register CR4
•SSE/SSE2/SSE3/SSSE3/SSE4 feature flags returned by CPUID
•EM, MP, and TS flags in control register CR0
Table 14-1.  Action Taken for Combinations of OS FXSR, OSXMMEXCPT, SSE, SSE2, SSE3, EM, MP, and TS1
NOTES:
1. For execution of any SSE instruction except the PAUSE, PREFETCH h, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH instructions.CR4 CPUID CR0 Flags
OSFXSR OSXMMEXCPT SSE, SSE2, 
SSE32,
SSE4_13
2. Exception conditions due to CR4.OSFXSR or CR4.OSXMMEXCPT do not apply to FISTTP.
3. Only applies to DPPS, DPPD, RO UNDPS, ROUNDPD, ROUNDSS, ROUNDSD.EM MP4
4. For processors that supp ort the MMX instructions, th e MP flag should be set.TS Action
0X5
5. X = Don’t care.XX 1 X # U D  e x c e p t i o n .
1X 0 X 1 X # U D  e x c e p t i o n .
1X 1 1 1 X # U D  e x c e p t i o n .1 0 1 0 1 0 Execute instruction; #UD exception if unmasked 
SIMD floating-point exception is detected.
1 1 1 0 1 0 Execute instruction; #XM exception if unmasked 
1X 1 0 1 1 # N M  e x c e p t i o n .14-4 Vol. 3ASYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
The SIMD floating-point exception mask bits (bits 7 throug h 12), the flush-to-zero flag (bit 15), the denormals-are-
zero flag (bit 6), and the rounding control field (bits 13 an d 14) in the MXCSR register should be left in their default 
values of 0. This permits the application to determine how these features are to be used.
14.1.4 Providing Non-Numeric Exception Handle rs for Exceptions Generated by the SSE 
SSE instructions can generate the same type of memory-access exceptions (such as page faults and limit viola-
tions) and other non-numeric exceptions as other In tel 64 and IA-32 architecture instructions generate. 
Ordinarily, existing exception handlers can handle these and other non-numeric exceptions without code modifica-
tion. However, depending on the mechanisms used in exis ting exception handlers, some modifications might need 
to be made.
The SSE extensions can generate the non-numeric exceptions listed below:
•Memory Access Exceptions:— Stack-segment fault (#SS).
— General protection exception (#GP). Executing most SSE instructions with an unaligned 128-bit memory 
reference generates a general-protection exceptio n. (The MOVUPS and MOVUPD instructions allow 
unaligned a loads or stores of 128-bit memory lo cations, without generating a general-protection 
exception.) A 128-bit reference within the stack segment that is not aligned to a 16-byte boundary will also 
generate a general-protection exception, instead a stack-segment fault exception (#SS).
— Page fault (#PF).
— Alignment check (#AC). When enable d, this type of alignment check op erates on operands that are less 
than 128-bits in size: 16-bit, 32-bit, and 64-bit. To en able the generation of alignment check exceptions, do 
•Set the AM flag (bit 18 of control register CR0)
•Set the AC flag (bit 18 of the EFLAGS register)
•CPL must be 3
If alignment check exceptions are enabled, 16-bit, 32-bit, and 64-bit misalignment will be detected for the 
MOVUPD and MOVUPS instructions; detection of 128- bit misalignment is not guaranteed and may vary 
with implementation.Table 14-2.  Action Taken for Combinations of OSFXSR, SSSE3, SSE4, EM, and TS
CR4 CPUID CR0 Flags
OSFXSR SSSE3
SSE4_11
SSE4_22
NOTES:
1. Applies to SSE4_1 instruct ions except DPPS, DPPD, ROUNDPS, ROUNDPD, ROUNDSS, ROUNDSD.
2. Applies to SSE4_2 instructions except CRC32 and POPCNT.EM TS Action
0X3
3. X = Don’t care.XX # U D  e x c e p t i o n .
10 X X # U D  e x c e p t i o n .
11 1 X # U D  e x c e p t i o n .
11 0 1 # N M  e x c e p t i o n .Vol. 3A 14-5SYSTEM PROGRAMMING FOR INSTRUCTION SET EX TENSIONS AND PROCESSOR EXTENDED STATES
•System Exceptions:
— Invalid-opcode exception (#UD). This exception is generated when executing SSE instructions under the 
following conditions:
•SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 feature flags returned by CPUID are set to 0. This condition 
does not affect the CLFLUSH instruction, nor POPCNT.
•The CLFSH feature flag returned by the CPUID instru ction is set to 0. This exception condition only 
pertains to the execution of the CLFLUSH instruction. 
•The POPCNT feature flag returned by the CPUID instru ction is set to 0. This exception condition only 
pertains to the execution of  the POPCNT instruction. 
•The EM flag (bit 2) in control register CR0 is set to 1, regardless of the value of TS flag (bit 3) of CR0. 
This condition does not affect the PAUSE, PREFETCH h, MOVNTI, SFENCE, LFENCE, MFENCE, CLFLUSH, 
CRC32, and POPCNT instructions.
•The OSFXSR flag (bit 9) in control register CR4 is set to 0. This condition does not affect the PSHUFW, 
MOVNTQ, MOVNTI, PAUSE, PREFETCH h, SFENCE, LFENCE, MFENCE, CLFLUSH, CRC32, and POPCNT 
•Executing an instruction that causes a SIMD floati ng-point exception when the OSXMMEXCPT flag (bit 
10) in control register CR4 is set to 0. See Section 14.4.1, “Using the TS Flag to Control the Saving of 
the x87 FPU and SSE State.”
— Device not available (#NM). This exception is genera ted by executing a SSE instruction when the TS flag 
(bit 3) of CR0 is set to 1.
Other exceptions can occur during delivery of the above exceptions.
14.1.5 Providing a Handler for the SIM D Floating-Point Exception (#XM)
SSE instructions do not generate numeric exceptions on packed integer operations. They can generate the 
following numeric (SIMD floating-point) exceptions on pa cked and scalar single precision and double precision 
floating-point operations. 
These SIMD floating-point exceptions (with the exception of the denormal operand exception) are defined in the 
IEEE Standard 754 for Floating-Point Arithmetic and repr esent the same conditions that cause x87 FPU floating-
point error exceptions (#MF) to be generated for x87 FPU instructions.
Each of these exceptions can be masked, in which case th e processor returns a reasonable result to the destination 
operand without invoking an exception handler. However, if any of these exceptions are left unmasked, detection 
of the exception condition results in a SIMD floating-p oint exception (#XM) being generated. See Chapter 6, 
“Interrupt 19—SIMD Floating-Point Exception (#XM).”
To handle unmasked SIMD floating-point exceptions, the operating system or executive must provide an exception 
handler. The section titled “SSE and SSE2 SIMD Floati ng-Point Exceptions” in Chapter 11, “Programming with 
Intel® Streaming SIMD Extensions 2 (Intel® SSE2),” of the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 1, describes the SIMD floating-poi nt exception classes and gives suggestions for writing an 
exception handler to handle them.
To indicate that the operating system provides a handle r for SIMD floating-point exceptions (#XM), the OSXM-
MEXCPT flag (bit 10) must be set in control register CR4.14-6 Vol. 3ASYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
14.1.5.1  Numeric Er ror flag and IGNNE#
SSE extensions ignore the NE flag in control register CR0 (t hat is, they treat it as if it were always set) and the 
IGNNE# pin. When an unmasked SIMD floating-point exceptio n is detected, it is always reported by generating a 
SIMD floating-point exception (#XM).
14.2 EMULATION OF SSE EXTENSIONS 
The Intel 64 and IA-32 architectures do not support emul ation of the SSE instructions, as they do for x87 FPU 
The EM flag in control register CR0 (provided to invoke em ulation of x87 FPU instructions) cannot be used to invoke 
emulation of SSE instructions. If an SSE instruction is  executed when CR0.EM = 1, an invalid opcode exception 
(#UD) is generated. See Table 14-1.
14.3 SAVING AND RESTORING SSE STATE
The SSE state consists of the state of the XMM and MXCS R registers. Intel recommends the following method for 
saving and restoring this state:
•Execute the FXSAVE instruction to save the state of the XMM and MXCSR registers to memory.
•Execute the FXRSTOR instruction to restore the state of  the XMM and MXCSR register s from the image saved in 
memory earlier.
This save and restore method is required for all oper ating systems. XSAVE feature set can also be used to 
save/restore SSE state. See Section 14.5, “The XSAVE Feature Set and Processor Extended State Management,” 
for using the XSAVE feature set to save/restore SSE state.
In some cases, applications may choose to save only the XMM and MXCSR registers in the following manner:
•Execute MOVDQ instructions to save the contents of the XMM registers to memory.

•Execute MOVDQ instructions to save the contents of the XMM registers to memory. 
•Execute a STMXCSR instruction to save the state of the MXCSR register to memory.
Such applications must restore the XMM and MXCSR registers as follows:
•Execute MOVDQ instructions to load the saved contents of the XMM registers from memory into the XMM 
•Execute a LDMXCSR instruction to restore the state of the MXCSR register from memory.
14.4 DESIGNING OS FACILITIES FOR SAVING X87 FPU, SSE, AND EXTENDED 
STATES ON TASK OR  CONTEXT SWITCHES
The x87 FPU and SSE state consist of the state of the x87 FPU, XMM, and MXCSR registers. The FXSAVE and 
FXRSTOR instructions provide a fast method for saving and restoring this state. The XSAVE feature set can also be 
used to save FP and SSE state along with other extended states (see Section 14.5).
Older operating systems may use FSAVE/FNSAVE and FRSTOR to save the x87 FPU state. These facilities can be 
extended to save and restore SSE state by substituting FXSAVE and FXRSTOR or the XSAVE feature set in place of 
If task or context switching facilities are written from scr atch, any of several approaches may be taken for using the 
FXSAVE and FXRSTOR instructions or the XSAVE feat ure set to save and restore x87 FPU and SSE state:
•The operating system can require applications that are inte nded to be run as tasks take responsibility for saving 
the states prior to a task suspension during a task switch  and for restoring the states when the task is resumed. 
This approach is appropriate for cooperative multitasking operating systems, where the application has control over (or is able to determine) when a task switch is about to occur and can save state prior to the task switch.Vol. 3A 14-7SYSTEM PROGRAMMING FOR INSTRUCTION SET EX TENSIONS AND PROCESSOR EXTENDED STATES
•The operating system can take the responsibility for saving the states as part of the task switch process and 
restoring the state of the registers when a suspended task is resumed. This approach is appropriate for 
preemptive multitasking operating systems, where the application cannot know when it is going to be 
preempted and cannot prepare in advance for task switching. 
•The operating system can take the responsibility for saving the states as part of the task switch process, but 
delay the restoring of the states until an instruction op erating on the states is actually executed by the new 
task. See Section 14.4.1, “Using the TS Flag to Contro l the Saving of the x87 FPU and SSE State,” for more 
information. This approach is called lazy restore.
The use of lazy restore mechanism in context switches is not recommended when XSAVE feature set is used to 
save/restore states for the following reasons.
— With XSAVE feature set, Intel proce ssors have optimizations in place to avoid saving the state components 
that are in their initial configurations or when they have not been modified since they were restored last. 
These optimizations eliminate the need for lazy restore. See section 13.5.4 in Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 1. 
— Intel processors have power optimizations when state components are in their initial configurations. Use of 
lazy restore retains the non-initial configuration of the last thread and is not power efficient.
— Not all extended states support lazy restore mechan isms. As such, when one or more such states are 
enabled it becomes very inefficient to use lazy restore as it results in two separate state restore, one in context switch for the states that does not support lazy restore and one in the #NM handler for states that 
support lazy restore.
14.4.1 Using the TS Flag to Control th e Saving of the x87 FPU and SSE State
The TS flag in control register CR0 is provided to allow the operating system to delay saving/restoring the x87 FPU 
and SSE state until an instruction that actually accesses th is state is encountered in a new task. When the TS flag 
is set, the processor monitors the instruction stream for x87 FPU, MMX, SSE instructions. When the processor 
detects one of these instructions, it raises a device-not -available exception (#NM) prior to executing the instruc-
tion. The #NM exception handler can then be used to save  the x87 FPU and SSE state for the previous task (using 
an FXSAVE, XSAVE, or XSAVEOPT instruction) and load the x87 FPU and SSE state for the current task (using an 
FXRSTOR or XRSOTR instruction). If the task never encount ers an x87 FPU, MMX, or SSE instruction, the device-
not-available exception will not be raised and a task state will not be saved/restored unnecessarily.
NOTE
The CRC32 and POPCNT instructions do not operate on the x87 FPU or SSE state. They operate on 
the general-purpose registers and are not invo lved with the techniques described above.
The TS flag can be set either explicitly (by executing a MOV instruction to control register CR0) or implicitly (using 
the IA-32 architecture’s native task switching mechanism) . When the native task switching mechanism is used, the 
processor automatically sets the TS flag on a task switch . After the device-not-available handler has saved the x87 
FPU and SSE state, it should execute the CLTS instruction to clear the TS flag.
14.5 THE XSAVE FEATURE SET AND PROCESSOR EXTENDED STATE 
MANAGEMENT 
The architecture of XSAVE feature set is described in Chapter 13 of Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1. The XSAVE feature set includes the following:
•An extensible data layout for existing and future processor state extensions. The layout of the XSAVE area 
extends from the 512-byte FXSAVE/FXRSTOR layout to provide compatibility and migration path from 
managing the legacy FXSAVE/FXRSTOR area. The XSAVE area  is described in more detail in Section 13.4 of the 
•CPUID enhancements for feature enumer ation. See Section 13.2 of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 1.14-8 Vol. 3ASYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
•Control register enhancement and dedi cated register for enabling each proc essor extended state. See Section 
13.3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
•Instructions to save state to and restore state from the XSAVE area. See Section 13.7 through Section 13.9 of 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Operating systems can utilize XSAVE feature set to manage both FP/SSE state and processor extended states. 
CPUID leaf 0DH enumerates XSAVE feature set related info rmation. The following guidelines provide the steps an 
operating system needs to take to support legacy FP/SSE states and processor extended states.
1. Check that the processor supports the XSAVE feature set
2. Determine the set of XSAVE managed features that the operating system intends to enable and calculate the 
size of the buffer needed to save/restore the states during context switch and other flows
3. Enable use of XSAVE feature set and XSAVE managed features
4. Provide an initialization for the XSAVE managed feature state components5. Provide (if necessary) required exception handlers for exceptions generated each of the XSAVE managed 
features.
14.5.1 Checking the Support for XSAVE Feature Set
Support for XSAVE Feature set is enumerated in CPUID.1.EC X.XSAVE[bit 26]. Enumeration of this bit indicates that 
the processor supports XSAVE/XRSTOR instructions to ma nage state and XSETBV/XGETBV on XCR0 to enable and 
get enabled states. An operating system needs to  enable XSAVE feature set as described later.
Additionally, CPUID.(EAX=0DH, ECX=1).E AX enumerates additional XSAVE sub features such as optimized save, 
compaction, and supervisor state support. The following table summarizes XSAVE sub features. Once an operating 
system enables XSAVE feature set, all the sub-features enum erated are also available. There is no need to enable 
each additional sub feature.
14.5.2 Determining the XSAVE Managed Featur e States And The Required Buffer Size 
Each XSAVE managed feature has one or more state components associated with it. An operating system policy 
needs to determine the XSAVE managed features to suppor t and determine the corresponding state components to 
enable. When determining the XSAVE managed features to support, operating system needs to take into account 
the dependencies between them (e.g.,  AVX feature depends on SSE feature) . Similarly, when a XSAVE managed 
feature has more than one state component, all of them need to be enabled. Each logical processor enumerates 
supported XSAVE state components in CPUID.(EAX=0DH, ECX=0).EDX:EAX. An operating system may enable all 
or a subset of the state components enumerat ed by the processor based on the OS policy.
The size of the memory buff er needed to save enabled XSAVE state co mponents depends on whether the OS opts-
in to use compacted format or not. Section 13.4.3 of the Intel® 64 and IA-32 Architectures Software Developer’s

in to use compacted format or not. Section 13.4.3 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, describes the layout of the extended region of the XSAVE area.Table 14-3.   CPUID.(EAX=0DH, ECX=1) EAX Bit Assignment
EAX Bit Position Meaning
0 If set, indicates availability  of the XSAVEOPT instruction.
1 If set, indicates availability of the XSAVEC instruction and the corresponding compaction enhancements 
to the legacy XRSTOR instruction.
2 If set, indicates support for execution of XGETBV with ECX=1. This executio n returns the state-compo-
nent bitmap XINUSE. If XINUSE[i] = 0, state component i is in its initial configuration. Execution of 
XSETBV with ECX=1 causes a #GP.
3 If set, indicates support for XSAVES/XRSTORS and IA32_XSS MSR
31:4 ReservedVol. 3A 14-9SYSTEM PROGRAMMING FOR INSTRUCTION SET EX TENSIONS AND PROCESSOR EXTENDED STATES
14.5.3 Enable the Use Of XSAVE Feat ure Set And XSAVE State Components
Operating systems need to enable the use of XSAVE feat ure set by writing to CR4. OSXSAVE[bit 18] to enable 
XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using 
XSAVE/XRSTOR. When the XSAVE feature set is enabled, all enumerated XSAVE sub features such as optimized 
save, compaction, and supervisor state support are also enabled. Operating systems also need to enable the 
XSAVE state components in XCR0 using the XSETBV instruction.
XSAVE state components can subsequently be disabled in  XCR0. However, disabling state components of AVX or 
AVX-512 that are not in initial configuration may incur po wer and performance penalty on SSE and AVX instructions 
respectively. If AVX state is disabled when it is not in its initial configuration, subsequent SSE instructions may 
incur a penalty. If AVX-512 state is disabled when it is  not in its initial configuration, subsequent SSE and AVX 
instructions may incur a penalty. It is recommended that  the operating systems and VMM set AVX or AVX-512 state 
components to their initial configuration before disablin g them. This can be achieved  by one of the two methods 
below.
•Using XRSTOR: Operating system or VMM can set the st ate of AVX or AVX-512 state components using XRSTOR 
instruction before disabling them in XCR0.
•Using VZEROUPPER: Operating system or VMM can set AVX and AVX-512 state components to their initial 
configuration using VZEROUPPER instruction before disab ling them in XCR0. Note that this will set both AVX 
and AVX-512 state components to their initial configuratio n. If the intent is to only disable AVX-512 state, 
Operating system or VMM will need to save AVX state before executing VZEROUPPER and restore it afterwards.
14.5.4 Provide an Initialization  for the XSAVE State Components
The XSAVE header of a newly allocated XSAVE area should be  initialized to all zeroes before saving context. An 
operating system may choose to establish beginning state- component values for a task by executing XRSTOR from 
an XSAVE area that the OS has configured. If it is desired to begin state component i in its initial configuration, the 
OS should clear bit i in the XSTATE_BV field in the XSAVE header; otherwise, it should set that bit and place the 
desired beginning value in the approp riate location in the XSAVE area.
When a buffer is allocated for compacted size, software must ensure that the XCOMP_BV field is setup correctly 
before restoring from the buffer. Bit 63 of the XCOMP_BV field indicates that the save area is in the compacted 
format and the remaining bits indicate the states that have  space allocated in the save area. If the buffer is first 
used to save the state in compacted format, then the sa ve instructions will setup the XCOMP_BV field appropri-
ately. If the buffer is first used to restore the state, then software must set up the XCOMP_BV field.
14.5.5 Providing the Required Exception Handlers
Instructions part of each XSAVE managed features may generate exceptions and operating system may need to 
enable such exceptions and provide handlers for them. Se ction 14.8 describes feature specific OS requirements for 
each XSAVE managed features.
14.6 INTEROPERABILITY OF THE XS AVE FEATURE SET AN D FXSAVE/FXRSTOR
The FXSAVE instruction writes x87 FPU and SSE state in formation to a 512-byte FXSAVE save area. FXRSTOR 
restores the processor’s x87 FPU and SSE states from an  FXSAVE area. The XSAVE fe atures set supports x87 FPU 
and SSE states using the same layout as the FXSAVE area to provide interoperability of FXSAVE versus XSAVE, and FXRSTOR versus XRSTOR. The XSAVE feature set allows syst em software to manage SSE state independent of x87 
FPU states. Thus system software that had been using FXSAVE and FXRSTOR to manage x87 FPU and SSE states 
can transition to using the XSAVE feature set to manage x87 FPU, SSE, and other processor extended states in a 
systematic and forward-looking manner. See Section 10.5 and Chapter 13 of the Intel
Software Developer’s Manual, Volume 1, for more details.
System software can implement forward-looking processor extended state management using the XSAVE feature 
set. In this case, system software must specify the bi t vector mask in EDX:EAX appropriately when executing 
XSAVE/XRSTOR instructions. 14-10 Vol. 3ASYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
For instance, the OS can supply instructions in the XSAVE feature set with a bit vector in EDX:EAX with the two 
least significant bits (corresponding to x87 FPU and SSE state) equal to 0. Then, the XSAVE instruction will not 
write the processor’s x87 FPU and SSE state into memory. Similarly, the XRSTOR instruction executed with a value 
in EDX:EAX with the least two significant bit equal to 0 will not restore nor initialize the processor’s x87 FPU and 
SSE state.
The processor’s action as a result of executing XRSTOR is given in Section 13.8 of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1. The inst ruction may be used to init ialize x87 FPU or XMM regis-
ters. When the MXCSR register is updated from memory, rese rved bit checking is enforced. The saving/restoring of 
MXCSR is bound to the SSE state, independent of the x87 FP U state. The action of XSAVE is given in Section 13.7 
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
14.7 THE XSAVE FEATURE SET AN D PROCESSOR SUPERVISOR STATE 
Supervisor state is a processor state that is only accessible in ring 0. An extension to the XSAVE feature set, 
enumerated by CPUID.(EAX=0DH, ECX=1).EAX[bit 3] allows  the management of the supervisor states using the 
XSAVE feature set. See Chapter 13 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, 
for the details of the supervisor state XSAVE feature set extension. The supervisor state extension includes the 
•CPUID enhancements to enumerate the set of supervisor  states and their sizes that can be managed by the 
XSAVE feature set. 
•The IA32_XSS MSR to enable the XSAVE feature set to manage one or more enumerated supervisor states. 
•A pair of privileged save/restore inst ructions, XSAVES and XRSTORS, to save/restore supervisor states along 
with other XSAVE managed feature states.
The guidelines to enable the XSAVE feature set to manage su pervisor state are very similar to the steps outlined in 
Section 13.6 with the differences noted below. The set of  supervisor states that can be managed by the XSAVE 
feature set is enumerated in (EAX=0DH, ECX=1).EDX:ECX . XSAVE managed supervisor states are enabled in the 
IA32_XSS MSR instead of the XCR0 control register. There are semantic differences between user states enabled in 
XCR0 and supervisor state enabled in the IA32_XSS MSR. A supervisor state enabled in the IA32_XSS MSR:
•May be accessed via other mechanisms such as RDMS R/WRMSR even when they are not enabled in the 
IA32_XSS MSR. Enabling a su pervisor state in the IA32_XSS MSR merely indicates that the state can be 
saved/restored using XSAVES/XRSTORS instructions. 
•May have side effects when saving/restoring the state such as disabling/enabling the feature associated with the state. This behavior is feature specific and wi ll be documented along with the feature description. 
•May generate faults when saving/restoring the state. XSAVES/XRSTORS will follow the faulting behavior of 
RDMSR/WRMSR respectively if the corresponding state is also accessible using RDMSR/WRMSR. 
•XRSTORS may fault when restoring the state for superv isor features that are already enabled via feature 
specific mechanisms. This behavior is feature spec ific and will be documented along with the feature 
When a supervisor state is disabled via a feature specific  mechanism, the state does not automatically get marked 
as INIT. Hence XSAVES/XRSTORS will continue to save/resto re the state subject to available optimizations. If the 
software does not intend to preserve the state when it disa bles the feature, it should initialize it to hardware INIT

software does not intend to preserve the state when it disa bles the feature, it should initialize it to hardware INIT 
value with the XRSTORS instruction so that XS AVES/XRSTORS perform optimally for that state.
14.8 SYSTEM PROGRAMMING FOR XSAVE MANAGED FEATURES
This section describes system programming requirement for each XSAVE managed features that are feature 
specific, such as exception handling.Vol. 3A 14-11SYSTEM PROGRAMMING FOR INSTRUCTION SET EX TENSIONS AND PROCESSOR EXTENDED STATES
14.8.1 Intel® Advanced Vector Extensions (Intel® AVX)
Intel AVX instructions comprises of 256-bit and 128-bit in structions that operates on 256-bit YMM registers. The 
XSAVE feature set allows software to save and restore th e state of these registers. See Chapter 13 of the Intel® 64 
For processors that support YMM states, the YMM state ex ists in all operating modes. However, the available 
instruction interfaces to access YMM states may vary in different modes. 
Operating systems must use the XSAVE feature set for YMM state management. The XSAVE feature set also 
provides flexible and efficient interface to manage XM M/MXCSR states and x87 FPU states in conjunction with 
newer processor extended states like YMM states. Operatin g systems may need to be aw are of the following when 
supporting AVX.
•Saving/Restoring AVX state in non-compacted format without SSE state will also save/restore MXCSR even though MXCSR is not part of AVX state. This does not happen when compacted format is used. 
•Few AVX instructions such as VZEROUPPER/VZEROALL may operate on future expansion of YMM registers.
An operating system must enable its YMM state manage ment to support AVX and an y 256-bit extensions that 
operate on YMM registers. Otherwise, an attempt to ex ecute an instruction in AVX extensions (including an 
enhanced 128-bit SIMD instructions using VE X encoding) will cause a #UD exception. 
AVX instructions may generate SIMD floating-point except ions. An OS must enable SIMD floating-point exception 
support by setting CR4.OSXMMEXCPT[bit 10]=1.
14.8.2 Intel® Advanced Vector  Extensions 512 (Intel® AVX-512)
Intel AVX-512 instructions are encode d using EVEX prefix. The EVEX enco ding scheme can support 512-bit, 256-
bit and 128-bit instructions that operate on opmask, ZMM, YMM, and XMM registers.
For processors that support the Intel AVX-512 family of instructions, the extended processor states (ZMM and 
opmask registers) exist in all operating modes. However, the access to these states may vary in different modes. 
The processor's support for instruction extensions that employ EVEX prefix encodi ng is independent of the 
processor's support for using XSAVE feature set on those states.
Instructions requiring EVEX prefix enco ding are generally supported in 64-bit, 32-bit modes, and 16-bit protected 
mode. They are not supported in Real mode, Virtual-8086 mo de or entering into SMM mode. Note that bits MAXVL-
1:256 (511:256) of ZMM register state are maintained acro ss transitions into and out of these modes. Because the 
XSAVE feature set instruction can operate in all operating modes, it is possible that the processor's ZMM register 
state can be modified by software in any operating mode by executing XRSTOR.
Operating systems must use the XSAVE/XRSTOR/XSAVEOPT instructions for ZMM and opmask state management. 
An OS must enable its ZMM and opmask state management to support Intel AVX-512 Foundation instructions. 
Otherwise, an attempt to execute an instruction in Inte l AVX-512 Foundation instructions (including a scalar 128-
bit SIMD instructions using EVEX enco ding) will cause a #UD exception. An operating system, which enables the 
AVX-512 state to support Intel AVX-512 Foundation instructions, is also sufficient to support the rest of the Intel 
AVX-512 family of instructions. Note that even though ZMM8-ZMM31 are not accessible in 32 bit mode, a 32 bit OS 
is still required to allocate memory for the entire ZMM state.
Intel AVX-512 Foundation instructions may generate SIMD floating-point exceptions. An OS must enable SIMD 
floating-point exception support by  setting CR4.OSXMMEXCPT[bit 10]=1.14-12 Vol. 3ASYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATESVol. 3B 15-1CHAPTER 15
This chapter describes facilities of Intel 64 and IA-32 ar chitecture used for power management and thermal moni-
toring.
15.1 ENHANCED INTEL SPEEDSTEP® TECHNOLOGY
Enhanced Intel SpeedStep® Technology was introduced in the Pentiu m M processor. The technology enables the 
management of processor power consumption via performa nce state transitions. These states are defined as 
discrete operating points associated with  different voltages and frequencies. 
Enhanced Intel SpeedStep Technology differs fr om previous generations of Intel SpeedStep® Technology in two 
ways:
•Centralization of the control mechanism and software interface in the processor by using model-specific 
•Reduced hardware overhead; this permits mo re frequent performance state transitions.
Previous generations of the Intel SpeedS tep Technology require processors to be a deep sleep state, holding off bus 
master transfers for the duration of a performance state transition. Performance state transitions under the Enhanced Intel SpeedStep Technology are discr ete transitions to a new target frequency.
Support is indicated by CPUID, using ECX feature bit 07.  Enhanced Intel SpeedStep Technology is enabled by 
setting IA32_MISC_ENABLE MSR, bit 16. On reset, bit 16 of IA32_MISC_ENABLE MSR is cleared. 
15.1.1 Software Interface For Initia ting Performance State Transitions
State transitions are initiated by writing a 16-bit value to  the IA32_PERF_CTL register, see Figure 15-2. If a transi-
tion is already in progress, transition to  a new value will subsequently take effect. 
Reads of IA32_PERF_CTL determine the last targeted operat ing point. The current operating point can be read from 
IA32_PERF_STATUS. IA32_PERF_STATUS is updated dynamically.
The 16-bit encoding that defines valid operating points is model-specific. Applications and performance tools are 
not expected to use either IA32_PERF_CTL or IA32_PERF_ STATUS and should treat both as reserved. Performance 
monitoring tools can access model-specific events and report the occurrences of state transitions.
15.2 P-STATE HARDWARE COORDINATION
The Advanced Configuration and Power Interface (ACPI) de fines performance states (P-states) that are used to 
facilitate system software’s ability to manage processor power consumption. Different P-states correspond to different performance levels that are applied while the proc essor is actively executing instructions. Enhanced Intel 
SpeedStep Technology supports P-states by providing soft ware interfaces that control the operating frequency and 
voltage of a processor. 
With multiple processor cores residing in the same ph ysical package, hardware dependencies may exist for a 
subset of logical processors on a platform. These depend encies may impose requirements that impact the coordi-
nation of P-state transitions. As a result, multi-core processors may require an OS to provide additional software 
support for coordinating P-state transitions for those subsets of logical processors.
ACPI firmware can choose to expose P-states as dependent and hardware-coordinated to OS power management 
(OSPM) policy. To support OSPMs, multi-core processors must have additional built-in support for P-state hardware 
coordination and feedback.
Intel 64 and IA-32 processors with dependent P-states am ongst a subset of logical processors permit hardware 
coordination of P-states and provide a hardware-coo rdination feedback mechanism using IA32_MPERF MSR and 15-2 Vol. 3BPOWER AND THERMAL MANAGEMENT
IA32_APERF MSR. See Figure 15-1 for an overview of the two 64-bit MSRs and the bullets below for a detailed 
•Use CPUID to check the P-State hardware coordination  feedback capability bit. CPUID.06H.ECX[Bit 0] = 1 
indicates IA32_MPERF MSR and IA32_APERF MSR are present.
•IA32_MPERF MSR (E7H) increments in proportion to a fixe d frequency, which is configured when the processor 
is booted.
•IA32_APERF MSR (E8H) increments in proportion to actu al performance, while accounting for hardware coordi-
nation of P-state and TM1/TM2; or software initiated throttling.
•The MSRs are per logical processor; they measure perfor mance only when the targeted processor is in the C0 
state.
•Only the IA32_APERF/IA32_MPERF ratio is architecturally defined; software should not attach meaning to the 
content of the individual of IA32_APERF or IA32_MPERF MSRs.
•When either MSR overflows, both MSRs are reset to zero and continue to increment.
•Both MSRs are full 64-bits counters. Each MSR can be written to independently. However, software should 
follow the guidelines illustrated in Example 15-1.
If P-states are exposed by the BIOS as hardware coordinated, software is expected to confirm processor support

is booted.
state.
If P-states are exposed by the BIOS as hardware coordinated, software is expected to confirm processor support 
for P-state hardware coordination feedback and use the fe edback mechanism to make P-state decisions. The OSPM 
is expected to either save away the cu rrent MSR values (for determination of th e delta of the counter ratio at a later 
time) or reset both MSRs (execute WRMSR with 0 to these MSRs individually) at the start of the time window used 
for making the P-state decision. When not resetting the valu es, overflow of the MSRs can be detected by checking 
whether the new values read are less than the previously saved values. 
Example 15-1 demonstrates steps for using the hardware  feedback mechanism provided by IA32_APERF MSR and 
IA32_MPERF MSR to determine a target P-state.
Example 15-1.  Determine Target P-stat e From Hardware Coordinated Feedback
DWORD PercentBusy; // Percentage  of processor time not idle.
// Measure “PercentBusy“ during previous sampling window.// Typically, “PercentBusy“ is meas ure over a time scale suitable for
// power management decisions// // RDMSR of MCNT and ACNT should be performed without delay.// Software needs to exercise care to avoid delays between 
// the two RDMSRs (for  example, interrupts).
MCNT = RDMSR(IA32_MPERF);ACNT = RDMSR(IA32_APERF);
// PercentPerformance indicates the percentage of the processor
// that is in use. The calculat ion is based on the PercentBusy, 
// that is the percentage of proc essor time not idle  and the P-state
// hardware coordinated feedback using the ACNT/MCNT ratio.// Note that both values need to be calculated over the same Figure 15-1.  IA32_MPERF MSR and IA 32_APERF MSR for P- state Coordination63 0
IA32_MPERF (Addr: E7H)63 0
IA32_APERF (Addr: E8H)Vol. 3B 15-3POWER AND THERMAL MANAGEMENT
// time window. 
PercentPerformance = PercentBusy * (ACNT/MCNT);
// This example does not cover the additional logic or algorithms
// necessary to coordinate  multiple logical processo rs to a target P-state.
TargetPstate = FindPstate(PercentPerformance);if (TargetPstate ≠ currentPstate) {
SetPState(TargetPstate);
} // WRMSR of MCNT and ACNT should be performed without delay.
  // Software needs to exercise  care to avoid delays between 
  // the two WRMSRs (for example, interrupts).  WRMSR(IA32_MPERF, 0);  WRMSR(IA32_APERF, 0);
15.3 SYSTEM SOFTWARE CONSIDERAT IONS AND OPPORTUNISTIC PROCESSOR 
PERFORMANCE OPERATION
An Intel 64 processor may support a form of processor op eration that takes advantage of design headroom to 
opportunistically increase performance. The Intel® Turbo Boost Technology can convert thermal headroom into 
higher performance across multi-threaded and single-threaded workloads. The Intel® Dynamic Acceleration Tech-
nology feature can convert thermal headroom into higher performance if only one thread is active.
15.3.1 Intel® Dynamic Acceleration Technology
The Intel Core 2 Duo processor T 7700 introduces Intel Dy namic Acceleration Technology. Intel Dynamic Accelera-
tion Technology takes advantage of thermal design headroom and opportunistically allows a single core to operate 
at a higher performance level when the operat ing system requests increased performance. 
15.3.2 System Software Interfaces for Oppo rtunistic Processor Performance Operation
Opportunistic processor performance operation, applicable  to Intel Dynamic Acceleration Technology and Intel® 
Turbo Boost Technology, has the following characteristics:
•A transition from a normal state of operation (e.g., Intel Dynamic Acceleration Technology/Turbo mode disengaged) to a target state is not guaranteed, but ma y occur opportunistically after the corresponding enable 
mechanism is activated, the headroom is available and certain criteria are met.
•The opportunistic processor performance operation is generally transparent to most application software.
•System software (BIOS and Operating system) must be aware of hardware support for opportunistic processor 
performance operation and may need to temporarily di sengage opportunistic processor performance operation 
when it requires more predictable processor operation. 
•When opportunistic processor performance operation is engaged, the OS should use hardware coordination 
feedback mechanisms to prevent un-intended policy effect s if it is activated during inappropriate situations.
15.3.2.1  Discover Hardware Support and Enabling  of Opportunistic Processor Performance Operation
If an Intel 64 processor has hardware support for opport unistic processor performance operation, the power-on 
default state of IA32_MISC_ENABLE[38] indicates the presen ce of such hardware support. For Intel 64 processors 
that support opportunistic processor performance operation, the default value is 1, indicating its presence. For 
processors that do not support opportunistic processor performance operation, the default value is 0. The power-15-4 Vol. 3BPOWER AND THERMAL MANAGEMENT
on default value of IA32_MISC_ENABLE[38] allows BIOS to  detect the presence of hardware support of opportu-
nistic processor performance operation. 
IA32_MISC_ENABLE[38] is shared across all logical processors  in a physical package. It is written by BIOS during 
platform initiation to enable/disable opportunistic proc essor performance operation in conjunction of OS power 
management capabilities, see Section 15.3.2.2. BIOS ca n set IA32_MISC_ENABLE[38] with 1 to disable opportu-
nistic processor performance operation; it must clear th e default value of IA32_MISC_ENABLE[38] to 0 to enable 
opportunistic processor performance operation. OS and applic ations must use CPUID leaf 06H if it needs to detect 
processors that have opportunistic processor performance operation enabled.
When CPUID is executed with EAX = 06H on input, Bit 1 of EAX in Leaf 06H (i.e.,  CPUID.06H:EAX[1]) indicates 
opportunistic processor performance operation, such as Intel Dynamic Acceleration Technology, has been enabled 
by BIOS. 
Opportunistic processor performance operation can be di sabled by setting bit 38 of IA32_MISC_ENABLE. This 
mechanism is intended for BIOS on ly. If IA32_MISC_ENABLE[38] is set, CPUID.06H:EAX[1] will return 0. 
15.3.2.2  OS Control of  Opportunistic Processor Performance Operation
There may be phases of software execution in which system software cannot tolerate the non-deterministic aspects 
of opportunistic processor performance operation. For exam ple, when calibrating a real-time workload to make a 
CPU reservation request to the OS, it may be undesirable  to allow the possibility of the processor delivering 
increased performance that cannot be sustained after the calibration phase. 
System software can temporarily disengage opportunistic pr ocessor performance operation by setting bit 32 of the 
IA32_PERF_CTL MSR (0199H), using a read-modify-write sequence on the MSR. The opportunistic processor 
performance operation can be re-engaged by clearing bit 32 in IA32_PERF_CTL MSR,  using a read-modify-write 
sequence. The DISENGAGE bit in IA32_PERF_CTL is not reflected in bit 32 of the IA32_PERF_STATUS MSR (0198H), and it is not shared between logical processors in a physical package. In order for OS to engage Intel 
Dynamic Acceleration Technology/Turbo mode, the BIOS must:
•Enable opportunistic processor performance operation, as described in Section 15.3.2.1.
•Expose the operating points associated with Intel Dy namic Acceleration Technology/Turbo mode to the OS.
15.3.2.3  Required Changes to OS  Power Management P-State Policy
Intel Dynamic Acceleration Technology  and Intel Turbo Boost Technology can provide opportunistic performance 
greater than the performance level corresponding to the Processor Base frequency of the processor (see CPUID’s 
processor frequency information). System software can use a pair of MSRs to observe performance feedback. Soft-
ware must query for the presence of IA32_APERF an d IA32_MPERF (see Section 15.2). The ratio between 
IA32_APERF and IA32_MPERF is architecturally defined and a value greater than unity indicates performance 
increase occurred during the observation period due to Intel Dynamic Acceleration Technology. Without incorpo-
rating such performance feedback, the target P-state evaluation algorithm can result in a non-optimal P-state 
target. Figure 15-2.  IA32_PERF_CTL Register0 63 16 15 33 32 31
Reserved
Enhanced Intel Speedstep® Technology Transition TargetIntel® Dynamic Acceleration Technology / Turbo Engage Bit 
(Used to Disengage Feature)ReservedVol. 3B 15-5POWER AND THERMAL MANAGEMENT
There are other scenarios under which OS power manageme nt may want to disable Intel Dynamic Acceleration 
Technology, some of these are listed below:
•When engaging ACPI defined passive thermal management , it may be more effective to disable Intel Dynamic 
Acceleration Technology for the duration of passive thermal management.
•When the user has indicated a policy preference of power savings over performance, OS power management 
may want to disable Intel Dynamic Acceleration Technology while that policy is in effect.

Reserved
15.3.3 Intel® Turbo Boost Technology
Intel Turbo Boost Technology is supported in Intel Core i7  processors and Intel Xeon processors based on Nehalem 
microarchitecture. It uses the same principle of levera ging thermal headroom to dynamically increase processor 
performance for single-threaded and multi-threaded/mul ti-tasking environment. The programming interface 
described in Section 15.3.2 also applies to Intel Turbo Boost Technology.
15.3.4 Performance and Ener gy Bias Hint Support
Intel 64 processors may support additional software hint  to guide the hardware heuristic of power management 
features to favor increasing dynamic performance or conserve energy consumption. 
Software can detect the processor's capability to suppor t the performance-energy bias preference hint by exam-
ining bit 3 of ECX in CPUID leaf 6. The processor supports this capability if CPUID.06H:ECX.SETBH[bit 3] is set and 
it also implies the presence of a new archit ectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
Software can program the lowest four bits of IA32_ENE RGY_PERF_BIAS MSR with a value from 0 - 15. The values 
represent a sliding scale, where a value of 0 (the default re set value) corresponds to a hint preference for highest 
performance and a value of 15 corresponds to the maximum energy savings. A value of 7 roughly translates into a 
hint to balance performance with energy consumption.
The layout of IA32_ENERGY_PERF_BIAS is shown in Fi gure 15-3. The scope of IA32_ENERGY_PERF_BIAS is per 
logical processor, which means that each of the logical processors in the package can be programmed with a different value. This may be especially important in virtualization scenarios, where the performance / energy 
requirements of one logical processor ma y differ from the other. Conflicting “hints” from various logical processors 
at higher hierarchy level will be resolved in  favor of performance over energy savings. 
Software can use whatever criteria it sees fit to progra m the MSR with an appropriate value. However, the value 
only serves as a hint to the hardware and the actual im pact on performance and energy savings is model specific.
15.4 HARDWARE-CONTROLLED PERFORMANCE STATES (HWP)
Intel processors may contain support for Hardware-Contr olled Performance States (HWP), which autonomously 
selects performance states while uti lizing OS supplied performance guidance  hints. The Enhanced Intel Speed-
Step® Technology provides a means for the OS to control and monitor discrete frequency-based operating points 
via the IA32_PERF_CTL and IA32_PERF_STATUS MSRs. Figure 15-3.  IA32_ENE RGY_PERF_BIAS Register4 3      0 63
Reserved
Energy Policy Preference Hint15-6 Vol. 3BPOWER AND THERMAL MANAGEMENT
In contrast, HWP is an implementation of the ACPI-def ined Collaborative Processor Performance Control (CPPC), 
which specifies that the platform enumerates a continuous , abstract unit-less, performance value scale that is not 
tied to a specific performance state / frequency by definition. While the enumer ated scale is roughly linear in terms 
of a delivered integer workload performance result, the OS is required to characterize the performance value range 
to comprehend the delivered performance for an applied workload. 
When HWP is enabled, the processor autonomously sele cts performance states as deemed appropriate for the 
applied workload and with consideration of constraining hints that are programmed by the OS. These OS-provided 
hints include minimum and maximum performance limits, preference towards energy efficiency or performance, 
and the specification of a relevant workload history obse rvation time window. The means for the OS to override 
HWP's autonomous selection of performance state with a specific desired performance target is also provided, however, the effective frequency delivered is subject to the result of energy efficiency and performance optimiza-
tions.
15.4.1 HWP Programming Interfaces 
The programming interfac es provided by HWP include the following:
•The CPUID instruction allows software to discover the pr esence of HWP support in an Intel processor. Specifi-
cally, execute CPUID instruction with EAX=06H as input will return 5 bit flags covering the following aspects in 
bits 7 through 11 of CPUID.06H:EAX:
— Availability of HWP baseline resource and capability, CP UID.06H:EAX[bit 7]: If this bit is set, HWP provides 
several new architectural MSRs: IA32_PM_ENAB LE, IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, 
IA32_HWP_STATUS. 
— Availability of HWP Notification upon dynamic Guar anteed Performance change, CPUID.06H:EAX[bit 8]: If 
this bit is set, HWP provides IA32_HWP_INTERRUPT MSR to enable interrupt generation due to dynamic 
Performance changes and excursions.
— Availability of HWP Activity window control, CPUID.06H:EAX [bit 9]: If this bit is set, HWP allows software to 
program activity window in the IA32_HWP_REQUEST MSR.
— Availability of HWP energy/performan ce preference control, CPUID.06H:EAX [bit 10]: If this bit is set, HWP 
allows software to set an energy/performance preference hint in the IA32_HWP_REQUEST MSR.
— Availability of HWP package level control, CPUID.06H :EAX[bit 11]:If this bit is set, HWP provides the 
IA32_HWP_REQUEST_PKG MSR to convey OS Power Mana gement’s control hints for all logical processors 
in the physical package.
Table 15-1.  Architectural and Non- Architectural MSRs Related to HWP
Address Architectural Regi ster Name Description
770H Y IA32_PM_ENABLE Enable/Disable HWP.771H Y IA32_HWP_CAPABILITIES Enumerates the HW P performance range (static and dynamic). 
772H Y IA32_HWP_REQUEST_PKG Conveys OSPM's control hints (Min, Max, Activity Window, Energy 
Performance Preference, Desired) for all logical pr ocessor in the 
773H Y IA32_HWP_INTERRUPT Controls HWP native in terrupt generation (Guaranteed Performance 
changes, excursions).
774H Y IA32_HWP_REQUEST Conveys OSPM's control hints (Min, Max, Activity Window, Energy 
Performance Preference, Desired) for a single logical processor.
775H Y IA32_HWP_PECI_REQUEST_INFO Conveys embedded system controller requests to override some of 
the OS HWP Reques t settings via the PECI mechanism.
777H Y IA32_HWP_STATUS Status bits indicating changes to Guaranteed Performance and 
excursions to Minimum Performance. 
19CH Y IA32_THERM_STATUS[bit s 15:12] Conveys reasons for performance excursions.
64EH N MSR_PPERF Productive Performance Count.Vol. 3B 15-7POWER AND THERMAL MANAGEMENT
•Additionally, HWP may provide a non-architectural MSR, MSR_PPERF, which provides a quantitative metric to 
software of hardware’s view of workload scalability. This  hardware’s view of workload scalability is implemen-
tation specific.
15.4.2 Enabling HWP 
The layout of the IA32_PM_ENABLE MSR is shown in Figure 15-4. The bit fields are described below: 
•HWP_ENABLE (bit 0, R/W1Once)  — Software sets this bit to enable HWP with autonomous selection of 
processor P-States. When set, the processor will disreg ard input from the legacy performance control interface 
(IA32_PERF_CTL). Note this bit can only be enabled once  from the default value. Once set, writes to the 
HWP_ENABLE bit are ignored. Only RESET w ill clear this bit. Default = zero (0). 
•Bits 63:1 are reserved and must be zero.
After software queries CPUID and verifies the processor’s support of HWP, system software can write 1 to IA32_P-
M_ENABLE.HWP_ENABLE (bit 0) to enable hardware controlled performance states. The default value of IA32_P-M_ENABLE MSR at power-on is 0, i.e., HWP is disabled.
Additional MSRs associated with HWP may only be a ccessed after HWP is enabled, with the exception of 
IA32_HWP_INTERRUPT and MSR_PPERF. Accessing the IA 32_HWP_INTERRUPT MSR requires only HWP is present 
as enumerated by CPUID but does not require enabling HWP.
IA32_PM_ENABLE is a package level MSR, i.e., writing to it  from any logical processor within a package affects all 
logical processors within that package.
15.4.3 HWP Performance Rang e and Dynamic Capabilities
The OS reads the IA32_HWP_CAPABILITIES MSR to comp rehend the limits of the HWP-managed performance 
range as well as the dynamic capability, which may change  during processor operation. The enumerated perfor-
mance range values reported by IA32_HWP_CAPABILITIES dire ctly map to initial frequency targets (prior to work-
load-specific frequency optimizations of HWP). Ho wever the mapping is processor family specific.
The layout of the IA32_HWP_CAPABILITIES MSR is shown in Figure 15-5. The bit fields are described below: Figure 15-4.  IA32_PM_ENABLE MSR1  0 63
Reserved
HWP_ENABLE15-8 Vol. 3BPOWER AND THERMAL MANAGEMENT
•Highest_Performance (bits 7:0, RO)  — Value for the maximum non-guaranteed performance level.
•Guaranteed_Performan ce (bits 15:8, RO)  — Current value for the guaranteed performance level. This 
value can change dynamically as a result of internal or external constraints, e.g., thermal or power limits.
•Most_Efficient_Performa nce (bits 23:16, RO)  — Current value of the most efficient performance level.

Reserved
•Most_Efficient_Performa nce (bits 23:16, RO)  — Current value of the most efficient performance level. 
This value can change dynamically as a result of workload characteristics.
•Lowest_Performance (bits 31:24, RO)  — Value for the lowest performance level that software can program 
to IA32_HWP_REQUEST.
•Bits 63:32 are reserved and must be zero.
The value returned in the Guaranteed_Performance  field is hardware's best-effort approximation of the avail-
able performance given current operating constraints.  Changes to the Guaranteed_Performance value will 
primarily occur due to a shift in operational mode. This incl udes a power or other limit ap plied by an external agent, 
e.g., RAPL (see Figure 15.10.1), or the setting of a Configurable TDP level (see model-specific controls related to 
Programmable TDP Limit in Chapter 2, “Model -Specific Registers (MSRs),” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 4.). Notification of a change to the Guaranteed_Performance occurs via 
interrupt (if configured) and the IA32_HWP_Status MSR. Changes to Guaranteed_Performance are indicated when 
a macroscopically meaningful change in performance occu rs i.e., sustained for greater than one second. Conse-
quently, notification of a change in Guaranteed Performance will typically occur no more frequently than once per 
second. Rapid changes in platform conf iguration, e.g., docking/undocking, with  corresponding changes to a Config-
urable TDP level could potentially cause more frequent notifications.
The value returned by the Most_Efficient_ Performance  field provides the OS with an indication of the practical 
lower limit for the IA32_HWP_REQUEST. The processo r may not honor IA32_HWP_REQUEST.Maximum Perfor-
mance settings below this value.
15.4.4 Managing HWP
15.4.4.1  IA32_HWP_REQUEST MSR (Address: 774H Logical Processor Scope)
Typically, the operating system controls HWP operation for each logical processor via the writing of control hints / constraints to the IA32_HWP_REQUEST MSR. The layout of the IA32_HWP_REQUEST MSR is shown in Figure 15-6. 
The bit fields are described below Figure 15-6.
Operating systems can control HWP by writing both  IA32_HWP_REQUEST and IA32_HWP_REQUEST_PKG MSRs 
(see Section 15.4.4.2). Five valid bits within the IA32_HW P_REQUEST MSR let the operatin g system flexibly select 
which of its five hint / constraint fields should be derived by the processor from  the IA32_HWP_REQUEST MSR and 
which should be derived from the IA32_HWP_REQUEST_P KG MSR. These five valid bits are supported if 
CPUID[6].EAX[17] is set. Figure 15-5.  IA32_HWP _CAPABILITIES Register 0 63 8 7 16 15 24 23 32 31
Reserved
Most_Efficient_Performance
Guaranteed_Performance
Highest_PerformanceLowest_PerformanceVol. 3B 15-9POWER AND THERMAL MANAGEMENT
When the IA32_HWP_REQUEST MSR Package Control bit is set, any valid bit that is NOT set indicates to the 
processor to use the respective field value from the IA32_HWP_REQUEST_PKG MSR. Otherwise, the values are 
derived from the IA32_HWP_REQUEST MSR. The valid bits are ignored when the IA32_HWP_REQUEST MSR 
Package Control bit is zero.
•Minimum_Performance (bits 7:0, RW)  — Conveys a hint to the HWP hardware. The OS programs the 
minimum performance hint to achieve the required qu ality of service (QOS) or to meet a service level 
agreement (SLA) as needed. Note that an excursion be low the level specified is possible due to hardware 
constraints. The default value of this field is IA32_HWP_CAPABILITIES.Lowest_Performance.
•Maximum_Performance (bits 15:8, RW)  — Conveys a hint to the HWP hardware. The OS programs this 
field to limit the maximum performance that is expect ed to be supplied by th e HWP hardware. Excursions 
above the limit requested by OS are possible due to ha rdware coordination between the processor cores and 
other components in the package. The default value of  this field is IA32_HWP_CAPABILITIES.Highest_Perfor-
mance.
•Desired_Performance (bits 23:16, RW)  — Conveys a hint to the HWP hardware. When set to zero, 
hardware autonomous selection determines the performa nce target. When set to a non-zero value (between 
the range of Lowest_Performance and Highest_Performa nce of IA32_HWP_CAPABILITIE S) conveys an explicit 
performance request hint to the hardware; effectively disabling HW Autonomous selection. The Desired_Per-
formance input is non-constraining in terms of Perfor mance and Energy Efficiency optimizations, which are 
independently controlled. The default value of this field is 0.
•Energy_Performance_Preference (bits 31:24, RW)  — Conveys a hint to the HWP hardware. The OS may 
write a range of values from 0 (performance preference ) to 0FFH (energy efficiency preference) to influence 
the rate of performance increase /decrease and the result  of the hardware's energy efficiency and performance 
optimizations. The default value of this field is 80H. No te: If CPUID.06H:EAX[bit 10] indicates that this field is 
not supported, HWP uses the value of the IA32_ENERGY_ PERF_BIAS MSR to determine the energy efficiency / 
performance preference.
•Activity_Window (bits 41:32, RW)  — Conveys a hint to the HWP hardware specifying a moving workload 
history observation window for performance/frequency op timizations. If 0, the hardware will determine the 
appropriate window size. When writing a non-zero value to th is field, this field is encoded in the format of bits 
38:32 as a 7-bit mantissa and bits 41:39 as a 3-bit expo nent value in powers of 10. The resultant value is in 
microseconds. Thus, the minimal/maximum activity window size is 1 microsecond/1270 seconds. Combined with the Energy_Performance_Preference input, Activity _Window influences the rate of performance increase Figure 15-6.  IA32_HWP_REQUEST Register 0 63 62 61 60 59 8 7 16 15 24 23 32 31 43 42 41
Reserved
Energy_Performance_PreferenceActivity_Window
Desired_Performance
Maximum_Performance
Minimum_PerformanceActivity_Window ValidEPP ValidDesired ValidMaximum ValidMinimum Valid
Package_Control15-10 Vol. 3BPOWER AND THERMAL MANAGEMENT
/ decrease. This non-zero hint only has meaning when De sired_Performance = 0. The default value of this field 
is 0.
•Package_Control (bit 42, RW)  — When set, causes this logical processor's IA32_HWP_REQUEST control 
inputs to be derived from the IA32_HWP_REQUEST_PKG MSR.
•Bits 58:43 are reserved and must be zero.
•Activity_Window Valid (bit 59, RW)  — When set, indicates to the processor to derive the Activity Window 
field value from the IA32_HWP_REQUEST MSR even if the pa ckage control bit is set. Otherwise, derive it from 
the IA32_HWP_REQUEST_PKG MSR. The default value of this field is 0.
•EPP Valid (bit 60, RW)  — When set, indicates to the processor to derive the EPP field value from the 
IA32_HWP_REQUEST MSR even if the pack age control bit is set. Otherwise, derive it from the IA32_HWP_RE-
QUEST_PKG MSR. The default value of this field is 0.
•Desired Valid (bit 61, RW)  — When set, indicates to the processor to derive the Desired Performance field 
value from the IA32_HWP_REQUEST MSR ev en if the package control bit is set. Otherwise, derive it from the 
IA32_HWP_REQUEST_PKG MSR. The defa ult value of this field is 0.
•Maximum Valid (bit 62, RW)  — When set, indicates to the processor to derive the Maximum Performance 
•Minimum Valid (bit 63, RW)  — When set, indicates to the processor to derive the Minimum Performance field 
The HWP hardware clips and resolves the field values as necessary to the valid range. Reads return the last value 
written not the clipped values.
Processors may support a subset of IA32_HWP_REQUEST fi elds as indicated by CPUID. Reads of non-supported 
fields will return 0. Writes to non-supported fields are ignored.
The OS may override HWP's autonomous selection of perf ormance state with a specific performance target by 
setting the Desired_Performance field to a non-zero value, however, the effective frequency delivered is subject to 
the result of energy efficiency and performance optimiza tions, which are influenced by the Energy Performance 
Preference field.
Software may disable all hardware optimizations by  setting Minimum_Performance = Maximum_Performance 
(subject to package coordination).
Note: The processor may run below the Minimum_Performance level due to hardware constraints including: power, 
thermal, and package coordination constraints. The processor may also run below the Minimum_Performance level 
for short durations (few milliseconds) following C-state ex it, and when Hardware Duty Cycling (see Section 15.5) is 
enabled.
When the IA32_HWP_REQUEST MSR is set to fast access mode, writes of this MSR are posted, i.e., the WRMSR

enabled.
When the IA32_HWP_REQUEST MSR is set to fast access mode, writes of this MSR are posted, i.e., the WRMSR 
instruction retires before the data reaches its destinatio n within the processor. It may retire even before all 
preceding IA stores are globally visible, i.e., it is not an architecturally serializing instruction anymore (no store 
fence). A new CPUID bit indicates this new characteristic of the IA32_HWP_REQUEST MSR (see Section 15.4.8 for additional details).Vol. 3B 15-11POWER AND THERMAL MANAGEMENT
15.4.4.2  IA32_HWP_REQUEST_PKG MSR (Address: 772H Package Scope)
The structure of the IA32_HWP_REQUEST_PKG MSR (packa ge-level) is identical to the IA32_HWP_REQUEST MSR 
with the exception of the the Package Control bit field and the five valid bit fields, which do not exist in the IA32_HWP_REQUEST_PKG MSR. Field values written to this MSR apply to all logical proc essors within the physical 
package with the exception of logical processors whose IA32_HWP_REQUEST.Package Control field is clear (zero). 
Single P-state Control mode is only supported  when IA32_HWP_REQUEST_PKG is not supported. 
15.4.4.3  IA32_HWP_PEC I_REQUEST_INFO MSR (Address 775H Package Scope)
When an embedded system controller is integrated in th e platform, it can override some of the OS HWP Request 
settings via the PECI mechanism. PECI initiated setting s take precedence over the relevant fields in the 
IA32_HWP_REQUEST MSR and in the IA32_HWP_REQUEST_PKG MSR, irrespective of the Package Control bit or 
the Valid Bit values described above. PECI can indepe ndently control each of: Minimum Performance, Maximum 
Performance and EPP fields. This MSR contains both the PE CI induced values and the control bits that indicate 
whether the embedded controller actually set the processor to use the respective value.
PECI override is supported if CPUID[6].EAX[16] is set.Figure 15-7.  IA32_HWP_REQUEST_PKG Register 
Figure 15-8.  IA32_HWP_ PECI_REQUEST_INFO MSR0 63 8 7 16 15 24 23 32 31 42 41
Reserved
Minimum_Performance
0 63 62 61 60 59 8 7 16 15 24 23 32 31
Reserved
Energy_Performance_Preference
Minimum_PerformanceEPP PECI OverrideReservedMax PECI OverrideMin PECI OverrideReserved15-12 Vol. 3BPOWER AND THERMAL MANAGEMENT
The layout of the IA32_HWP_PECI_REQUEST_INFO MSR is shown in Figure 15-8. This MSR is writable by the 
embedded controller but is read-only by software executin g on the CPU. This MSR has Package scope. The bit fields 
are described below: 
•Minimum_Performance (bits 7:0, RO)  — Used by the OS to read the latest value of PECI minimum 
performance input.
•Maximum_Performance (bits 15:8, RO)  — Used by the OS to read the latest value of PECI maximum 
•Bits 23:16 are reserved and must be zero.
•Energy_Performance_Preference (bits 31:24, RO)  — Used by the OS to read the latest value of PECI 
energy performance preference input.
•Bits 59:32 are reserved and must be zero.
•EPP_PECI_Overrid e (bit 60, RO)  — Indicates whether PECI if currently overriding the Energy Performance 
Preference input. If set(1), PECI is overriding the Energy Performance Preference input. If clear(0), OS has 
control over Energy Performance Preference input.
•Bit 61 is reserved and must be zero.
•Max_PECI_Override (bit 62, RO)  — Indicates whether PECI if currently overriding the Maximum 
Performance input. If set(1), PECI is overriding the Maximum Performance input. If clear(0), OS has control 
over Maximum Performance input.
•Min_PECI_Override (bit 63, RO)  — Indicates whether PECI if currently  overriding the Minimum Performance 
input. If set(1), PECI is overriding the Minimum Perfor mance input. If clear(0), OS has control over Minimum 
Performance input.
HWP Request Field Hierarchical Resolution
HWP Request field resolution is fed by three MS Rs: IA32_HWP_REQUEST, IA32_HWP_REQUEST_PKG, and 
IA32_HWP_PECI_REQUEST_INFO. The flow that the processor goes through to resolve which field value is chosen 
is shown below.
For each of the two HWP Request fields; Desired and Activity Window:
If IA32_HWP_REQUEST.PACKAGE_CONTROL = 1 and IA32_HWP_REQUEST.<field> valid bit = 0
Resolved Field Value = IA32_HWP_REQUEST_PKG.<field>
Else
Resolved Field Value = IA32_HWP_REQUEST.<field>
For each of the three HWP Request fields; Min, Max, and EPP:
If IA32_HWP_PECI_REQUEST_INFO.<field> PECI Override bit = 1
Resolved Field Value = IA32_HWP_PECI_REQUEST_INFO.<field>
Else if IA32_HWP_REQUEST.PACKAGE_CONTROL = 1 and IA32_HWP_REQUEST.<field> valid bit = 0
Else
15.4.4.4  IA32_HWP_CTL  MSR (Address: 776H Lo gical Processor Scope)
IA32_HWP_CTL[0] controls the behavior  of IA32_HWP_REQUEST Package Control [bit 42]. This control bit allows 
the IA32_HWP_REQUEST MSR to stay in INIT mode most of th e time (Control Bit is equal to its RESET value of 0) 
thus avoiding actual saving/restoring of the MSR contents when the OS adds it to the register set saved and 
restored by XSAVES/XRSTORS.
•When IA32_HWP_CTL[0] = 0:
— If IA32_HWP_REQUEST[42] = 0, the processor ignores all fields of the IA32_HWP_REQUEST_PKG MSR and 
selects all HWP values (Min, Max, EPP, Desired, Activity Window) from the IA32_HWP_REQUEST MSR.
— If IA32_HWP_REQUEST[42] = 1, the processor selects the HWP values (Min, Max, EPP, Desired, Activity 
Window) either from the IA32_HWP_REQUEST MSR or  from the IA32_HWP_REQUEST_PKG MSR according Vol. 3B 15-13POWER AND THERMAL MANAGEMENT
to the values contained in the IA32_HWP_REQUEST MS R bit fields [bits 63:59]. See Section 15.4.4.1 for 
additional details.
•When IA32_HWP_CTL[0] = 1, the behavior is reversed:
— If IA32_HWP_REQUEST[42] = 1, the processor ignore s all fields of the IA32_HWP_REQUEST_PKG MSR and 
— If IA32_HWP_REQUEST[42] = 0, the processor selects the HWP values (Min, Max, EPP, Desired, Activity 
Window) either from the IA32_HWP_REQUEST MSR or from the IA32_HWP_REQUEST_PKG MSR according 
Section 15-2 summarizes the IA32_HWP_CTL MSR bit 0 control behavior.
This MSR is supported if CPUID[6].EAX[22] is set.
If the IA32_PM_ENABLE[HWP_ENABLE] (bit 0 ) is not set, access to this MSR will generate a #GP fault.
15.4.5 HWP Feedback
The processor provides several types of f eedback to the OS during HWP operation. 
The IA32_MPERF MSR and IA32_APERF MSR mechanism (see Sect ion 15.2) allows the OS to calculate the resultant 
effective frequency delivered over a time period. Energy efficiency and performance optimizations directly impact 
the resultant effective frequency delivered.
The layout of the IA32_HWP_STATUS MSR is shown in Fi gure 15-9. It provides fee dback regarding changes to 
IA32_HWP_CAPABILITIES.Guaranteed_Performance, IA 32_HWP_CAPABILITIES.Highest_Performance, excur-
sions to IA32_HWP_CAPABILITIES.Minimum_Performance, an d PECI_Override entry/exit events. The bit fields are 
described below: 
•Guaranteed_Performance_C hange (bit 0, RWC0)  — If set (1), a change to Guaranteed_Performance has 
occurred. Software should query IA32_HWP_CAPABILITIE S.Guaranteed_Performance value to ascertain the 
new Guaranteed Performance value and to assess whet her to re-adjust HWP hints via IA32_HWP_REQUEST. 
Software must clear this bit by writing a zero (0).
•Bit 1 is reserved and must be zero.
•Excursion_To_Minimum (bit 2, RWC0)  — If set (1), an excursion to Minimum_Performance of 
IA32_HWP_REQUEST has occurred. Software must clear this bit by writing a zero (0).
•Highest_Change (bit 3, RWC0)  — If set (1), a change to Highest Performance has occurred. Software 
should query IA32_HWP_CAPABILITIES to ascertain the new Highest Performance value. Software must clear 
this bit by writing a zero (0). Interrupts upon Highes t Performance change are supported if CPUID[6].EAX[15] 
is set.
•PECI_Override_Entry (bit 4, RWC0)  — If set (1), an embedded/management controller has started a PECI 
override of one or more OS control hints (Min, Max,  EPP) specified in IA32_HWP_REQUEST or IA32_HWP_RE-
QUEST_PKG. Software may query IA32_HWP_PECI_REQU EST_INFO MSR to ascertain which fields are now 
overridden via the PECI mechanism and what their values  are (see Section 15.4.4.3 for additional details). Table 15-2.  IA32_HWP_CTL MSR Bit 0 Behavior
Thread request 
PKG CTL 
meaningDefines which HWP Request MSR is used, whether thread level or package level. When the package MSR is used, the 
thread MSR valid bits define which thread MSR fields override the package (default 0).
IA32_HWP_CTL[PKG_CTL_PLR] IA32_HWP_REQUEST[PKG_CTL] HWP Request MSR Used0 0 IA32_HWP_REQUEST MSR
0 1 IA32_HWP_REQUEST_PKG MSR
1 0 IA32_HWP_REQUEST_PKG MSR1 1 IA32_HWP_REQUEST MSR15-14 Vol. 3BPOWER AND THERMAL MANAGEMENT
Software must clear this bit by writing a zero (0). Interrupts upon PECI override entry are supported if 
CPUID[6].EAX[16] is set.

PKG CTL 
•PECI_Override_Exit (bit 5, RWC0)  — If set (1), an embedded/management controller has stopped 
overriding one or more OS control hints (Min, Max,  EPP) specified in IA32_HWP_REQUEST or IA32_HWP_RE-
QUEST_PKG. Software may query IA 32_HWP_PECI_REQUEST_I NFO MSR to ascertain which fields are still 
overridden via the PECI mechanism and which fields are now back under software control (see Section 15.4.4.3 
for additional details). Software must clear this bit by wr iting a zero (0). Interrupts upon PECI override exit are 
supported if CPUID[6].EAX[16] is set.
•Bits 63:6 are reserved and must be zero.
The status bits of IA32_HWP_STATUS must be cleared (0) by software so that a new status condition change will 
cause the hardware to set the bit again and issue the notifi cation. Status bits are not set for “normal” excursions, 
e.g., running below Minimum Performance for short durati ons during C-state exit. Changes to Guaranteed_Perfor-
mance, Highest_Performance, excursions to Minimum_Pe rformance, or PECI_Override entry/exit will occur no 
more than once per second.
The OS can determine the specific reasons for a Guaran teed_Performance change or an excursion to Mini-
mum_Performance in IA32_HWP_REQUEST by examining the associated status and log bits reported in the 
IA32_THERM_STATUS MSR. The layout of the IA32_HWP_STA TUS MSR that HWP uses to support software query of 
HWP feedback is shown in Figure 15-10. The bit fields of IA32_THERM_STATUS associat ed with HWP feedback are 
described below (Bit fields of IA32_THERM_STATUS unr elated to HWP can be found in Section 15.8.5.2).Figure 15-9.  IA32_HWP_STATUS MSR6  5  4  3  2  1  0 63
Reserved
Highest_Change
Excursion_To_Minimum
Reserved
Guaranteed_Performance_ChangePECI_Override_EntryPECI_Override_ExitVol. 3B 15-15POWER AND THERMAL MANAGEMENT
•Bits 11:0, See Section 15.8.5.2.
•Current Limit Status (bit 12, RO)  — If set (1), indicates an electrical current limit (e.g., Electrical Design 
Point/IccMax) is being exceeded  and is adversely impacting energy efficiency optimizations.
•Current Limit Log (bit 13, RWC0)  — If set (1), an electrical current limit has been exceeded that has 
adversely impacted energy efficiency optimizations since the la st clearing of this bit or a reset. This bit is sticky, 
software may clear this bit by writing a zero (0).
•Cross-domain Limit Status (bit 14, RO)  — If set (1), indicates another hardware domain (e.g., processor 
graphics) is currently limiting energy efficiency  optimizations in the processor core domain.
•Cross-domain Limit Log (bit 15, RWC0)  — If set (1), indicates another hardware domain (e.g., processor 
graphics) has limited energy efficiency optimizations in the processor core domain since the last clearing of this 
bit or a reset. This bit is sticky, software may clear this bit by writing a zero (0).
•Bits 63:16, See Section 15.8.5.2.
15.4.5.1  Non-Archit ectural HWP Feedback
The Productive Performance (MSR_PPERF) MSR (non-archite ctural) provides hardware's view of workload scal-
ability, which is a rough assessment of the relationship be tween frequency and workload performance, to software. 
The layout of the MSR_PPERF is shown in Figure 15-11. 
•PCNT (bits 63:0, RO)  — Similar to IA32_APERF but only counts cycl es perceived by hardware as contributing 
to instruction execution (e.g., unhalted and unstalled cycles). This counter increments at the same rate as IA32_APERF, where the ratio of ( ΔPCNT/ ΔACNT) is an indicator of workload scalability (0% to 100%). Note that 
values in this register are valid even when HWP is not enabled. Figure 15-10.  IA32_THERM_STATUS Register With HWP Feedback
Figure 15-11.  MSR_PPERF MSR63 0
Reserved15
Reading Valid12345 8 10 16 2223 27
Resolution in Deg. Celsius
Digital Readout
Thermal Threshold #2 Log
Thermal Threshold #2 Status 
Thermal Threshold #1 LogThermal Threshold #1 Status
Critical Temperature Log67 9 3132
Critical Temperature Status
PROCHOT# or FORCEPR# Log
PROCHOT# or FORCEPR# Event
Thermal Status Log
Thermal Status11
Power Limit Notification Log
Power Limit Notification Status14 13 12
Cross-domain Limit LogCross-domain Limit Status
Current Limit Log
Current Limit Status
63 0
PCNT - Productive Performance Count15-16 Vol. 3BPOWER AND THERMAL MANAGEMENT
15.4.6 HWP Notifications
Processors may support interrupt-based notification of chan ges to HWP status as indicated by CPUID. If supported, 
the IA32_HWP_INTERRUPT MSR is used to enable interrupt- based notifications. Notification events, when enabled, 
are delivered using the existing thermal LVT entry. The layout of the IA32_HWP_INTERRUPT is shown in 
Figure 15-12. The bit fields are described below:
•EN_Guaranteed_Performance_Change (bit 0, RW)  — When set (1), an HWP Interrupt will be generated 
whenever a change to the IA32_HWP_CAPABILITIES.Gua ranteed_Performance occurs. The default value is 0 
(Interrupt generation is disabled). 
•EN_Excursion_Minimum (bit 1, RW)  — When set (1), an HWP Interrupt will be generated whenever the 
HWP hardware is unable to meet the IA32_HWP_REQUES T.Minimum_Performance setting. The default value is 
0 (Interrupt generation is disabled). 
•EN_Highest_Change (bit 2, RW)  — When set (1), an HWP Interrupt will  be generated whenever a change to 
the IA32_HWP_CAPABILITIES.Highest_Performance occurs. The default value is 0 (interrupt generation is 
disabled). Interrupts upon Highest Performance ch ange are supported if CPUID[6].EAX[15] is set.
•EN_PECI_OVERRIDE (bit 3, RW)  — When set (1), an HWP Interrupt will  be generated whenever PECI starts 
or stops overriding any of the three HWP fields described  in Section 15.4.4.3. The default value is 0 (interrupt 
generation is disabled). See Section 15.4.5 and Section 15.4.4.3 for details on how the OS learns what is the 
current set of HWP fields that are overridden by PECI. Interrupts upon PECI override change are supported if 
•Bits 63:4 are reserved and must be zero.
15.4.7 Idle Logical Processor Impact on Core Frequency
Intel processors use one of two schemes for setting core frequency:
1. All cores share same frequency.
2. Each physical core is set to a frequency of its own.
In both cases the two logical processors that share a single physical core are set to the same frequency, so the 
processor accounts for the IA32_HWP_REQUEST MSR fields of both logical processors when defining the core 
frequency or the whole package frequency.
When CPUID[6].EAX[20]  is set and only one logical processor of the two is active, while the other is idle (in any 
C1 sub-state  or in a deeper sleep state), only the active logical processor's  IA32_HWP_REQUEST MSR fields 
are considered, i.e., the HWP Request fields of a logical pr ocessor in the C1E sub-state or in a deeper sleep state 
are ignored. 
Note:  when a logical processor is in C1 state  its HWP Request fields are accounted for.Figure 15-12.  IA32_HWP_INTERRUPT MSR4  3  2  1  0 63
Reserved
EN_PECI_OVERRIDE
EN_Highest_Change
EN_Excursion_Minimum
EN_Guaranteed_Performance_ChangeVol. 3B 15-17POWER AND THERMAL MANAGEMENT
15.4.8 Fast Write of Uncore MS R (Model Specific Feature)
There are a few logical processor scope MSRs whose values need to be observed outside the logical processor. The 
WRMSR instruction takes over 1000 cycles to complete (r etire) for those MSRs. This overhead forces operating 
systems to avoid writing them too often whereas in many cases it is preferable that the OS writes them quite 
frequently for optimal power/performance operation of the processor. 
The model specific “Fast Write MSR” feature reduces this over head by an order of magnitude to a level of 100 cycles 
for a selected subset of MSRs. 
Note:  Writes to Fast Write MSRs are posted, i.e., when the WRMSR instruction completes, the data may still be “in 
transit” within the processor. Software can check the stat us by querying the processor to ensure data is already 
visible outside the logical processor (see Section 15.4.8.3 fo r additional details). Once the data is visible outside 
the logical processor, software is ensured that later writes by the same logical processor to the same MSR will be visible later (will not bypass the earlier writes). 
MSRs that are selected for Fast Write are specified in a special capability MSR (see Section 15.4.8.1). Architectural 
MSRs that existed prior to the introduction of this feature and are selected for Fast Write, thus turning from slow to 
fast write MSRs, will be noted as such via a new CPUID bit.  New MSRs that are fast upon introduction will be docu-
mented as such without an additional CPUID bit.
Three model specific MSRs are associated with the featur e itself. They enable enumer ating, controlling, and moni-
toring it. All three are logical processor scope.
15.4.8.1  FAST_UNCORE_MSRS_CAPABILITY (Address: 0x65F, Logical Processor Scope)
Operating systems or BIOS can read the FAST_UNCORE_ MSRS_CAPABILITY MSR to enumerate those MSRs that 
are Fast Write MSRs.

•FAST_IA32_HWP_REQUEST MSR (bit 0, RO)  — When set (1), indicates that the IA32_HWP_REQUEST MSR 
is supported as a Fast Write MSR. A value of 0 indi cates the IA32_HWP_REQUEST MSR is not supported as a 
Fast Write MSR.
15.4.8.2  FAST_UNCORE_MSRS_CTL (Addr ess: 0x657, Logical Processor Scope)
Operating Systems or BIOS can use the FAST_UNCORE_MSRS _CTL MSR to opt-in or opt-out for fast write of 
specific MSRs that are enabled fo r Fast Write by the processor. 
Note:  Not all MSRs that are selected for this feature will ne cessarily have this opt-in/opt-out option. They may be 
supported in fast write mode only.Figure 15-13.  FAST_UNCORE_MSRS_CAPABILITY MSR1  0 63
Reserved
FAST_IA32_HWP_REQUEST MSR15-18 Vol. 3BPOWER AND THERMAL MANAGEMENT
•FAST_IA32_HWP_REQUEST_MSR_ENABLE (bit 0, RW)  — When set (1), enables fast access mode for the 
IA32_HWP_REQUEST MSR and sets the low latency, posted IA32_HWP_REQUESRT MSR' CPUID[6].EAX[18]. 
The default value is 0. Note that this bit can only be en abled once from the default value. Once set, writes to 
this bit are ignored. Only RESET will clear this bit.
15.4.8.3  FAST_UNCORE_MSRS_STATUS (Add ress: 0x65E, Logical Processor Scope)
Software that executes the WRMSR instruction of a Fast Write MSR can check whether the data is already visible 
outside the logical processor by reading the FAST_UNCORE_MSRS_STATUS MSR. For each Fast Write MSR there is 
a status bit that indicates whether the data is already visible outside the logical processor or is still in “transit”.
•FAST_IA32_HWP_REQUEST_WRITE_STATUS (bit 0, RO)  — Indicates whether the CPU is still in the 
middle of writing IA32_HWP_REQUEST MSR, even afte r the WRMSR instruction has retired. A value of 1 
indicates the last write of IA32_HWP_REQUEST is sti ll ongoing. A value of 0 indicates the last write of 
IA32_HWP_REQUEST is visible outside the logical processor.
15.4.9 Fast_IA32_HWP_REQUEST CPUID
IA32_HWP_REQUEST is an architectural MSR that exists in processors whose CPUID[6].EAX[7] is set (HWP BASE 
is enabled). This MSR has logical processor scope, but afte r its contents are written the contents become visible 
outside the logical processor. When the FAST_IA32_HWP_R EQUEST CPUID[6].EAX[18] bit is set, writes to the 
IA32_HWP_REQUEST MSR are visible outside the logical processor via the “Fast Write” feature described in Section 
15.4.8.
15.4.10 Recommendations for OS use of HWP Controls
Common Cases of Using HWP
The default HWP control field values are expected to be suitable for many applications. The OS can enable autono-
mous HWP for these common cases byFigure 15-14.  FAST_UNCORE_MSRS_CTL MSR
Figure 15-15.  FAST_UNCORE_MSRS_STATUS MSR1  0 63
Reserved
FAST_IA32_HWP_REQUEST_MSR_ENABLE
1  0 63
Reserved
FAST_IA32_HWP_REQUEST_WRITE_STATUSVol. 3B 15-19POWER AND THERMAL MANAGEMENT
•Setting IA32_HWP_REQUEST.Desired Performance = 0 (hardware autonomous selection determines the 
performance target). Set IA32_HWP_REQUEST.Activity Wi ndow = 0 (enable HW dynamic selection of window 
size).
To maximize HWP benefit for the common cases, the OS should set 
•IA32_HWP_REQUEST.Minimum_Performance = IA3 2_HWP_CAPABILITIES.Lowest_Performance and 
•IA32_HWP_REQUEST.Maximum_Performance = IA 32_HWP_CAPABILITIES.Highest_Performance. 
Setting IA32_HWP_REQUEST.Minimum_Performance = IA 32_HWP_REQUEST.Maximum_Performance is function-
ally equivalent to using of the IA32_PERF_CTL interf ace and is therefore not recommended (bypassing HWP).
Calibrating HWP for Applicatio n-Specific HWP Optimization
In some applications, the OS may have Quality of Service requirements that may not be met by the default values. 
The OS can characterize HWP by: 
•keeping IA32_HWP_REQUEST.Minimum_Performance  = IA32_HWP_REQUEST.Maximum_Performance to 
prevent non-linearity in the characterization process,
•utilizing the range values enumerated from the IA32_HWP_CAPABILITIES MSR to program IA32_HWP_RE-
QUEST while executing workloads of interest an d observing the power and performance result.
The power and performance result of characterization is also influenced by the IA32_HWP_REQUEST.Energy 
Performance Preference field, which must also be characterized. 
Characterization can be used to set IA32_HWP_REQUEST .Minimum_Performance to achieve the required QOS in 
terms of performance. If IA32_HWP_REQUEST.Minimum _Performance is set higher than IA32_HWP_CAPABILI-
TIES.Guaranteed Performance then notification of excursions to Minimum Performance may be continuous.
If autonomous selection does not deliver the required workload performance, the OS should assess the current 
delivered effective frequency and for the duration of the specific performance requirement set IA32_HWP_RE-
QUEST.Desired_Performance ≠ 0 and adjust IA32_HWP_REQUEST.Energ y_Performance_Preference as necessary 
to achieve the required workload performance. The MSR_ PPERF.PCNT value can be used to better comprehend the 
potential performance result from adjustments to IA32_ HWP_REQUEST.Desired_Performance. The OS should set 
IA32_HWP_REQUEST.Desired_Performance = 0 to re-enable autonomous selection. 
Tuning for Maximum Performance or Lowest Power Consumption
Maximum performance will be delivered by setting IA 32_HWP_REQUEST.Minimum_Per formance = IA32_HWP_RE-
QUEST.Maximum_Performance = IA32_HWP_CAPABILITIES .Highest_Performance and setting IA32_HWP_RE-
QUEST.Energy_Performance_Preferenc e = 0 (performance preference).
Lowest power will be achieved by setting IA 32_HWP_REQUEST.Minimum_Performance = IA32_HWP_RE-
QUEST.Maximum_Performance = IA32_HWP_CAPABILITI ES.Lowest_Performance and setting IA32_HWP_RE-
QUEST.Energy_Performance_Preference = 0FFH (energy efficiency preference).
Mixing Logical Processor and Pa ckage Level HWP Field Settings
Using the IA32_HWP_REQUEST Package_Contr ol bit and the five valid bits in that MSR, the OS can mix and match 
between selecting the Logical Processor scope fields and the Package level fields. For example, the OS can set all 
logical cores' IA32_HWP_REQUEST.Package_Control bit to ‘1’, and for those logical processors if it prefers a 
different EPP value than the one set in the IA32_HWP_R EQUEST_PKG MSR, the OS can set the desired EPP value 
and the EPP valid bit. This overrides the package EPP value for only a subset  of the logical processors in the 
package.
Additional Guidelines
Set IA32_HWP_REQUEST.Energy_Performance_Preference as appropriate for the platform's current mode of oper-
ation. For example, a mobile platforms' setting may be  towards performance preference when on AC power and 
more towards energy efficiency when on DC power.
The use of the Running Average Power Limit (RAPL) processor capability (see section 14.7.1) is highly recom-
mended when HWP is enabled. Use of IA32_HWP_Request.M aximum_Performance for thermal control is subject to 
limitations and can adversely impact the performance of other processor components, e.g., graphics15-20 Vol. 3BPOWER AND THERMAL MANAGEMENT
If default values deliver undesirable performance latency in response to events, the OS should set IA32_HWP_RE-
QUEST. Activity_Window to a low (non-zero) value and IA32_HWP_REQUEST.Energy_Performance_Preference 
towards performance (0) for the event duration.
Similarly, for “real-time” threads, set IA32_HWP_REQ UEST.Energy_Performance_Preference towards performance 
(0) and IA32_HWP_REQUEST. Activity_Window to a low valu e, e.g., 01H, for the duration of their execution.
When executing low priority work that may otherwise cause the hardware to deliver high performance, set 
IA32_HWP_REQUEST. Activity_Window to a longer valu e and reduce the IA32_HWP_Request.Maximum_Perfor-
mance value as appropriate to control energy effici ency. Adjustments to IA32_HWP_REQUEST.Energy_Perfor-
mance_Preference may also be necessary.
15.5 HARDWARE DUTY CYCLING (HDC)
Intel processors may contain support for Hardware Duty Cycling (HDC), which enables the processor to autono-mously force its components inside the physical package in to idle state. For example, the processor may selectively 
force only the processor cores into an idle state. 
HDC is disabled by default on processors that support it. System software can dynamically enable or disable HDC 
to force one or more components into an idle state or wa ke up those components previously forced into an idle 
state. Forced Idling (and waking up) of multiple components in a physical package can be done with one WRMSR to a packaged-scope MSR from any logical processor within the same package. 
HDC does not delay events such as timer expiration, but it  may affect the latency of short (less than 1 msec) soft-
ware threads, e.g., if a thread is forced to idle stat e just before completion and entering a “natural idle”.
HDC forced idle operation can be thought of as operatin g at a lower effective frequency. The effective average

HDC forced idle operation can be thought of as operatin g at a lower effective frequency. The effective average 
frequency computed by software will in clude the impact of HDC forced idle. 
The primary use of HDC is enable system software to ma nage low active workloads to increase the package level 
C6 residency. Additionally, HDC can lower the effective av erage frequency in case or power or thermal limitation. 
When HDC forces a logical processor, a processor core or a ph ysical package to enter an idle state, its C-State is set 
to C3 or deeper. The deep “C-states” referred to in this section are processor-specific C-states.
15.5.1 Hardware Duty Cyclin g Programming Interfaces 
The programming interfac es provided by HDC include the following:
•The CPUID instruction allows software to discover the presence of HDC support in an Intel processor. Specifi-
cally, execute CPUID instruction with EAX=06H as input, bit 13 of EAX indicates the processor’s support of the 
following aspects of HDC.
— Availability of HDC baseline resource, CPUID.06H:EAX[bit 13]: If this bit is set, HDC provides the following 
architectural MSRs: IA32_PKG_HDC_CTL, IA32_PM_CTL1, and the IA32_THREAD_STALL MSRs.
•Additionally, HDC may provide se veral non-architectural MSR. Vol. 3B 15-21POWER AND THERMAL MANAGEMENT
15.5.2 Package level Enabling HDC
The layout of the IA32_PKG_HDC_CTL MSR is shown in Fi gure 15-16. IA32_PKG_HDC_CTL is a writable MSR from 
any logical processor in a package. The bit fields are described below: 
•HDC_PKG_Enable (bit 0, R/W)  — Software sets this bit to enable HDC operation by allowing the processor 
to force to idle all “HDC-allowed” (see Figure 15.5.3) logical processors in the package. Clearing this bit 
disables HDC operation in the package by waking up all the processor cores that were forced into idle by a 
previous ‘0’-to-’1’ transition in IA32_PKG_HDC_CT L.HDC_PKG_Enable. This bit is writable only if 
CPUID.06H:EAX[bit 13] = 1. Default = zero (0). 
After processor support is determined via CPUID, system  software can enable HDC operation by setting IA32_PK-
G_HDC_CTL.HDC_PKG_Enable to 1. At reset, IA32_PKG_HDC_CTL.HDC_PKG_Enable is cleared to 0. A '0'-to-'1' 
transition in HDC_PKG_Enable allows the processor to fo rce to idle all HDC-allowed (indicated by the non-zero 
state of IA32_PM_CTL1[bit 0]) logical processors in the package. A ‘1’-to-’0’ transition wakes up those HDC force-
idled logical processors. 
Software can enable or disable HDC using this package le vel control multiple times from any logical processor in 
the package. Note the latency of writing a value to the package-visible IA32_PKG_HDC_CTL.HDC_PKG_Enable is 
longer than the latency of a WRMSR operation to a Logica l Processor MSR (as opposed to package level MSR) such 
as: IA32_PM_CTL1 (described in Section 15.5.3). Prop agation of the change in IA32_PKG_HDC_CTL.HDC_PK-
G_Enable and reaching all HDC idled logical processor to be woken up may take on the order of core C6 exit 
latency.Table 15-3.  Architectural and non- Architecture MSRs Related to HDC
Address Architec
turalRegister Name Description
DB0H Y IA32_PKG_HDC_CTL Package Enable/Disable HDC.
DB1H Y IA32_PM_CTL1 Per-logical-p rocessor select control to a llow/block HDC forced idling. 
DB2H Y IA32_THREAD_STALL Accumulate st alled cycles on this logical proc essor due to HDC forced idling.
653H N MSR_CORE_HDC_RESIDENCY Core level stalled cycle counter due to HDC forced idling on one or more 
logical processor.
655H N MSR_PKG_HDC_SHALLOW_RE
SIDENCYAccumulate the cycles the package was in C21 state and at least one logical 
processor was in forced idle
656H N MSR_PKG_HDC_DEEP_RESIDE
NCYAccumulate the cycles the package was in the software specified Cx1 state 
and at least one logical pr ocessor was in forced idle. Cx is specified in 
MSR_PKG_HDC_CONFIG_CTL.
652H N MSR_PKG_HDC_CONFIG_CTL HDC configuration controls
NOTES:
1. The package “C-states” referred to in this section are processor-specific C-states.
Figure 15-16.  IA32_PKG_HDC_CTL MSR63 0
Reserved1
HDC_PKG_Enable Reserved15-22 Vol. 3BPOWER AND THERMAL MANAGEMENT
15.5.3 Logical-Processor Level HDC Control
The layout of the IA32_PM_CTL1 MSR is shown in Figure 15-17. Each logical processor in a package has its own 
IA32_PM_CTL1 MSR. The bit fields are described below: 
•HDC_Allow_Block (bit 0, R/W)  — Software sets this bit to allow this logical processors to honor the 
package-level IA32_PKG_HDC_CTL.HDC_PKG_Enable control. Clearing this bit prevents this logical processor 
from using the HDC. This bit is writable only if CPUID.06H:EAX[bit 13] = 1. Default = one (1). 
Fine-grain OS control of HDC operation at the granularity of per-logical-proc essor is provided by IA32_PM_CTL1. At 
RESET, all logical processors are allowed to participate in HDC operation such that OS can manage HDC using the 
package-level IA32_PKG_HDC_CTL.
Writes to IA32_PM_CTL1 complete with  the latency that is typical to WRMSR to a Logical Processor level MSR. 
When the OS chooses to manage HDC operation at per-logi cal-processor granularity, it can write to IA32_PM_CTL1 
on one or more logical processors as desired. Each write to IA32_PM_CTL1 must be done by code that executes on 
the logical processor targeted to be allowed into or blocked from HDC operation. 
Blocking one logical processor for HDC operation may have package level impact. For example, the processor may 
decide to stop duty cycling of all other Logical Processors as well. 
The propagation of IA32_PKG_HDC_CTL .HDC_PKG_Enable in a package takes longer than a WRMSR to IA32_P-
M_CTL1. The last completed write to IA3 2_PM_CTL1 on a logical processor will be honored when a ‘0’-to-’1’ transi-
tion of IA32_PKG_HDC_CTL.HDC_PKG_Enable arrives to a logical processor.
15.5.4 HDC Residency Counters
There is a collection of counters available for software to  track various residency metrics related to HDC operation. 
In general, HDC residency time is defined as the time in  HDC forced idle state at the granularity of per-logical-
processor, per-core, or package. At the granularity of pe r-core/package-level HDC residency, at least one of the 
logical processor in a core/package must be in the HDC forced idle state.
15.5.4.1  IA32_THREAD_STALL
Software can track per-logical-processor HDC residenc y using the architectural MSR IA32_THREAD_STALL.The 
layout of the IA32_THREAD_STALL MSR is shown in Figure 15-18. Each logical processor in a package has its own 
IA32_THREAD_STALL MSR. The bit fields are described below: Figure 15-17.  IA32_PM_CTL1 MSR
Figure 15-18.  IA 32_THREAD_STALL MSR63 0
Reserved1
HDC_Allow_Block
Reserved
63 0
Stall_cycle_cntVol. 3B 15-23POWER AND THERMAL MANAGEMENT
•Stall_Cycle_Cnt (bits 63:0, R/O)  — Stores accumulated HDC forced-idle cycle count of this processor core 
since last RESET. This counter increments at the same rate of the TSC. The count is updated only after the 
logical processor exits from the forced idled C-state. At each update, the number of cycles that the logical 
processor was stalled due to forced-idle will be adde d to the counter. This counter is available only if 
A value of zero in IA32_THREAD_STALL indicates either  HDC is not supported or the logical processor never 
serviced any forced HDC idle. A non-zero value in IA 32_THREAD_STALL indicates the HDC forced-idle residency 
times of the logical processor. It also indicates the forced-idle cycles due to HDC that could appear as C0 time to 
traditional OS accounting mechanisms (e .g., time-stamping OS idle/exit events).
Software can read IA32_THREAD_STALL irrespective of the state of IA32_PKG_HDC_CTL and IA32_PM_CTL1, as 
long as CPUID.06H:EAX[bit 13] = 1.
15.5.4.2  Non-Architectu ral HDC Residency Counters
Processors that support HDC operation may provide th e following model-specific HDC residency counters.
MSR_CORE_HDC_RESIDENCY
Software can track per-core HDC residency using the counter MSR_CORE_HDC_RESIDENCY. This counter incre-
ments when the core is in C3 state or deeper (all logical pr ocessors in this core are idle due to either HDC or other 
mechanisms) and at least one of the logical processors is in HDC forced idle state. The layout of the MSR_CORE_H-DC_RESIDENCY is shown in Figure 15-19. Each processo r core in a package has its own MSR_CORE_HDC_RESI-
DENCY MSR. The bit fields are described below: 
•Core_Cx_Duty_Cycle_Cnt (bits 63:0, R/O)  — Stores accumulated HDC forced-idle cycle count of this 
processor core since last RESET. This counter increments at the same rate of the TSC. The count is updated only after core C-state exit from a forced idled C-stat e. At each update, the increment counts cycles when the 
core is in a Cx state (all its logical processor are idle) an d at least one logical processor in this core was forced 
into idle state due to HDC. If CPUI D.06H:EAX[bit 13] = 0, attempt to ac cess this MSR will cause a #GP fault. 
Default = zero (0). 
A value of zero in MSR_CORE_HDC_RESIDENCY indicates eith er HDC is not supported or this processor core never 
serviced any forced HDC idle. 
MSR_PKG_HDC_SHALLOW_RESIDENCY

The counter MSR_PKG_HDC_SHALLOW_RESIDENCY allows software to track HDC residency time when the 
package is in C2 state, all processor cores in the package are not active and at least one logical processor was 
forced into idle state due to HDC. The layout of the MSR_PKG_HDC_SHALLOW_RESIDENCY is shown in 
Figure 15-20. There is one MSR_PKG_HDC_SHALLOW_RESI DENCY per package. The bit fields are described 
below: Figure 15-19.  MSR_CORE_HDC_RESIDENCY MSR
Figure 15-20.  MSR_PKG_HDC_SHALLOW_RESIDENCY MSR63 0
Core_Cx_duty_cycle_cnt
63 0
Pkg_Duty_cycle_cnt15-24 Vol. 3BPOWER AND THERMAL MANAGEMENT
•Pkg_Duty_Cycle_Cnt (bits 63:0, R/O)  — Stores accumulated HDC forced-idle cycle count of this processor 
core since last RESET. This counter increments at the same rate of the TSC. Package shallow residency may be 
implementation specific. In the initial implem entation, the threshold is package C2-state.  The count is updated 
only after package C2-state exit from a forced idled C-st ate. At each update, the increment counts cycles when 
the package is in C2 state and at least one processor core in this package was forced into idle state due to HDC. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR 
may cause a #GP fault. Default = zero (0). 
A value of zero in MSR_PKG_HDC_SHALLOW_RESIDENCY indi cates either HDC is not su pported or this processor 
package never serviced any forced HDC idle. 
MSR_PKG_HDC_DEEP_RESIDENCY
The counter MSR_PKG_HDC_DEEP_RESIDENCY allows software  to track HDC residency time when the package is 
in a software-specified package Cx state, all processor co res in the package are not active and at least one logical 
processor was forced into idle state due to HDC. Selectio n of a specific package Cx state can be configured using 
MSR_PKG_HDC_CONFIG. The layout of the MSR_PKG_HDC_ DEEP_RESIDENCY is shown in Figure 15-21. There is 
one MSR_PKG_HDC_DEEP_RESIDENCY per package. The bit fields are described below: 
•Pkg_Cx_Duty_Cycle_Cnt (bits 63:0, R/O)  — Stores accumulated HDC forced-idle cycle count of this 
processor core since last RESET. This counter increments at the same rate of the TSC. The count is updated only 
after package C-state exit from a forced idle state. At each update, the increment counts cycles when the 
package is in the software-configured Cx state and at least one processor core in this package was forced into idle state due to HDC. If CPUID.06H:EAX[b it 13] = 0, attempt to access this MSR 
may cause a #GP fault. 
MSR_PKG_HDC_CONFIG
MSR_PKG_HDC_CONFIG allows software to configure th e package Cx state that the counter MSR_PKG_HD-
C_DEEP_RESIDENCY monitors. The layout of the MSR_PKG_ HDC_CONFIG is shown in Figure 15-22. There is one 
MSR_PKG_HDC_CONFIG per package. The bit fields are described below: 
•Pkg_Cx_Monitor (bits 2:0, R/W)  — Selects which package C-state the MSR_HDC_DEEP_RESIDENCY 
counter will monitor. The encoding of the HDC_Cx_Monitor field are: 0: no-counting; 1: count package C2 only, 
2: count package C3 and deeper; 3: count package C6 and deeper; 4: count package C7 and deeper; other 
encodings are reserved. If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR may cause a #GP fault. 
•Bits 63:3 are reserved and must be zero.Figure 15-21.  MSR_PKG_HDC_DEEP_RESIDENCY MSR
Figure 15-22.  MSR_PKG_HDC_CONFIG MSR63 0
Pkg_Cx_duty_cycle_cnt
63 0
Reserved2
HDC_Cx_Monitor
ReservedVol. 3B 15-25POWER AND THERMAL MANAGEMENT
15.5.5 MPERF and APERF Counters Under HDC
HDC operation can be thought of as an average effective fr equency drop due to all or some of the Logical Proces-
sors enter an idle state period. 
By default, the IA32_MPERF counter counts during forced idle periods as if the logical processor was active. The 
IA32_APERF counter does not count during forced idle st ate. This counting convention allows the OS to compute 
the average effective frequency of the Logical Processor between the last MWAIT exit and the next MWAIT entry 
(OS visible C0) by ΔACNT/ ΔMCNT * TSC Frequency.
15.6 HARDWARE FEEDBACK INTERFAC E AND INTEL® THREAD DIRECTOR
Intel processors that enumerate CPUID.06H.0H:EAX.HW _FEEDBACK[bit 19] as 1 support Hardware Feedback 
Interface (HFI). Hardware provides guidance to the Oper ating System (OS) scheduler to perform optimal workload 
scheduling through a hardware feedback interface struct ure in memory. Details on this table structure are 
described in Section 15.6.1.
Intel processors that enumerate CPUID.06H.0H:EAX[bit 23] as 1 support Intel® Thread Director. Hardware 
provides guidance to the Operating System (OS) sched uler to perform optimal wo rkload scheduling through a 
memory resident table and software thread specific index (Class ID) that points into that table and selects which 
data to use for that software thread. Details on this table structure are described in Section 15.6.2.
15.6.1 Hardware Feedback In terface Table Structure
This structure has a global header that is 16 bytes in size . Following this global header, there is one 8 byte entry 
per logical processor in the socket. The structure is designed as follows.Figure 15-23.  Example of Effective Frequenc y Reduction and Forced Idle Period of HDC
Table 15-4.  Hardware Feedback Interface Structure
Byte Offset Size (Bytes) Description
0 16 Global Header
16 8 Per Logical Processor Entry24 8 Per Logical Processor Entry
... ... ...
16 + n*8 8 Per Logical Processor Entry1600 MHz: 25% Utilization /75% Forced Idle
Effective Frequency @ 100% Utilization: 400 MHz15-26 Vol. 3BPOWER AND THERMAL MANAGEMENT
The global header is structured as shown in Table 15-5.
The per logical processor scheduler feedback entry is stru ctured as follows. The operating system can determine 
the index of the logical processor feedback entry fo r a logical processor using CPUID.06H.0H:EDX[31:16] by 
executing CPUID on that logical processor.Table 15-5.  Hardware Feedback In terface Global Header Structure
Byte Offset Size (Bytes) Field Name Description
0 8 Timestamp Timestamp of when the table was last updated by hardware. This is a 
timestamp in crystal clock units.
Initialized by the OS to 0.
81P e r f o r m a n c e  
Capability FlagsIf bit 0 is set to 1, indicates the perf ormance capability field for one or more 
logical processors was updated in the table and/or another bit in this field is updated.
If bit 1 is set to 1, indicates a force id le/inject idle reques t to the OS for one 
or more logical processors.Initialized by the OS to 0.
9 1 Energy Efficiency 
Capability ChangedIf bit 0 is set to 1, indi cates the energy efficiency capability field for one or 
more logical processors was updated in the table and/or another bit in this 
field is updated.
or more logical processors.
10 6 Reserved Initialized by the OS to 0.
Table 15-6.  Hardware Feedback Interf ace Logical Processor Entry Structure
01P e r f o r m a n c e  
CapabilityPerformance capability is an 8-bit value (0 ... 255) specifying the relative 
performance level of a logica l processor. Higher values indicate higher perfor-
mance; the lowest performanc e level of 0 indicates a reco mmendation to  the OS to 
not schedule any software threads on it for performance reasons. The OS scheduler is expected to initialize the Hardware Feedback Interface Structure to 0 
prior to enabling Hardware Feedback.
CPUID.06H.0H:EDX[0] enumer ates support for Performance capability reporting.
11E n e r g y  
Efficiency CapabilityEnergy Efficiency capability is an 8-bit value (0 ... 255) specifying the relative 
energy efficiency level of a logical processor. Higher values indicate higher energy efficiency; the lowest energy  efficiency capability of 0 indicates a recommendation 
to the OS to not schedule any software threads on it for efficiency reasons. An 
Energy Efficiency capability of 255 indicates which logical processors have the highest relative energy efficiency capability. In addition, the value 255 is an 
explicit recommendation for the OS to consolidate work on those logical 
processors for energy efficiency reasons. Th e OS scheduler is expected to initialize 
the Hardware Feedback Interface Structure to 0 prior to enabling Hardware 
Feedback.
CPUID.06H.0H:EDX[1] enumerates support for Energy Efficiency capability reporting.
2 6 Reserved The OS scheduler is expected to initialize the Hardware Feedback Interface 
Structure to 0 prior to en abling Hardware Feedback.Vol. 3B 15-27POWER AND THERMAL MANAGEMENT
15.6.2 Intel® Thread Director Table Structure
This structure has a global header that is at least 16 bytes in size. Its size depends on the number of classes and 
capabilities enumerated by the CPUID instruction (see note s below Table 15-7). Following this global header there 
are multiple Logical Processor related entries. The structure is designed as follows.

Feedback.
The global header is structured as shown in Table 15-8.Table 15-7.  Intel® Thread  Director Ta ble Structure
Byte Offset1,2,3
NOTES:
1. Byte offset of Capabilitycp of Classcl change indication: 8 + CP * cl + cp.
2. Byte offset of LP Entryi : 8 + (i+1) * (CP * CL + R8).
3. Byte offset of capabilitycp of classcl of LP Entryi: 8 + (i+1) * (CP * CL + R8) + CP * cl + cp.Size (Bytes) Description
08  +  C P4*CL4 + R85
4. Both upper case  CL and CP denote total number of classes and capabilities defined for the processor. Lower case cl and cp de note 
one instance of a cla ss or capability. cl and cp are counted starting at zero. See “CPUID —CPU Identification” in Chapter 3 of t he Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 2A for the number of classes (CL) and the number of supported capabilities (CP). CP (# of capabilities): number of enumer ated bits in CPUID.06H.0H.EDX [7:0] and CL (# of classes): 
CPUID.06H.0H.ECX[15:8].
5. R8 is the number of bytes necessary to  round up the Capability Change Indication  array and the Logical Processor Entry to wh ole 
multiple of 8 bytes.Global Header
8 + CP*CL + R8 CL*CP + R8 Per Logical Processor Entry
06
6. Table size: 8 + (N+1)* (CP * CL + R8).8 + 2*(CP*CL + R8) CL*CP + R8 Per Logical Processor Entry1
... ... ...
8 + (N7 -1)*(CP*CL + R8)
7. N is the number of Lo gical Processor Entries in the table. It is not grea ter than the number of Lo gical Processors on the so cket, but 
may be lower.
8. The Operating System can determine the index for the Logical Processor Entry within the Intel Thread Director table using 
CPUID.06H.0H:EDX[31:16] by ex ecuting the CPUID instruction on that Logical Processor.
9. The Operating System shou ld allocate space to accomm odate for one such structure per socket in the system.
10. The Intel Thread Director table struct ure extends the Hardware Fee dback Interface table structur e without brea king backward  
compatibility. The Hardware Feedback Interface can be viewed as having two capabilities and a single class.CL*CP +R8 Logical Processor EntryN-115-28 Vol. 3BPOWER AND THERMAL MANAGEMENT
Table 15-8.  Intel® Thread Dire ctor Global Header Structure 
Byte OffsetSize 
0 8 Time-stamp of when the table was last updated by hardware. This is a time-stamp in crystal clock units. 
8 1 Class 0 Performance 
Capability FlagsIf bit 0 is set to 1, in dicates the performance capability field for one or 
more logical processors was updated in the table and/or another bit in 
this field is updated. If bit 1 is set to 1, indi cates a force idle/inject id le request to the OS for 
one or more logical processors.
8 + 1 1 Class 0 Energy Efficiency 
Capability FlagsIf bit 0 is set to 1, in dicates the energy efficiency capability field for 
one or more logical processors was updated in the table and/or another bit in this field is updated. 
If bit 1 is set to 1, indi cates a force idle/inject id le request to the OS for 
...
8 + CP - 1 1 Class 0 change indication for 
Capability #(CP-1) if existsUnavailable for capabilities that are not enumerated.
8 + CP 1 Class 1 Performance 
this field is updated. 
8 + CP + 1 1 Class 1 Energy Efficiency 
one or more logical processors was updated in the table and/or 
another bit in this field is updated.If bit 1 is set to 1, indi cates a force idle/inject id le request to the OS for 
...
8 + 2*CP - 1 1 Class 1 change indication for 
... Change indication for Capabilities of additional Classes if exist.
8 + (CL-1)*CP 1 Class #(CL-1) Performance 
8 + (CL-1)*CP + 1 1 Class #(CL-1) Energy 
Efficiency Capability FlagsIf bit 0 is set to 1, in dicates the energy efficiency capability field for 
another bit in this field is updated. If bit 1 is set to 1, indi cates a force idle/inject id le request to the OS for 
Initialized by the OS to 0.Vol. 3B 15-29POWER AND THERMAL MANAGEMENT
The logical processor capability entry in the Intel Thread Director table is structured as follows. ...
8 + CL*CP - 1 1 Class #(CL-1) change 
indication for Capability #(CP-
1) if existsUnavailable for capabilities that are not enumerated.
8 + CL*CP R8 Padding Padding to nearest multiple of  8 bytes. Initialized by the OS to 0 prior 
to enabling Intel Thread Director.
Table 15-9.  Intel® Thread Director  Logical Processor Entry Structure 
CapabilityClass 0 Performance capability is an 8-bit value (0 ... 255) specifying the relative 
performance level of a single  logical processor. Higher values indicate higher 
performance; the lowest performance leve l of 0 indicates a recommendation to 
the OS to not schedule an y software threads on it for performance reasons. 
11E n e r g y  
Efficiency 
CapabilityClass 0 Energy Efficiency ca pability is an 8-bit value (0 ... 255) specifying the 
relative energy efficiency level of a logica l processor. Higher values indicate higher 
energy efficiency; the lowest energy efficiency capability of 0 indicates a recom-mendation to the OS to not schedule any software threads on it for efficiency 
reasons. An Energy Efficiency capability of 255 indicates which logical processors 
have the highest relative energy efficiency capability. In addition, the value 255 is an explicit recommendation for the OS to consolidate work on those logical 
processors for energy efficiency reasons. 
...
CP - 1 1 Capability 
#(CP-1)Class 0 Capability #(CP-1) if exists. If  the capability does  not exist (is not 
enumerated in the CPUID), the entry is unavailable (no space is reserved for future 
use here).
CP R8 Padding Padding to nearest multiple of 8 bytes. Initialized by the OS to 0 prior to enabling 
Intel Thread Director.
CP + R8 1 Performance 
CapabilityClass 1 Performance capability is an 8-bit value (0 ... 255) specifying the relative 
the OS to not schedule an y software threads on it for performance reasons.
CP + 1 1 Energy 
Efficiency CapabilityClass 1 Energy Efficiency ca pability is an 8-bit value (0 ... 255) specifying the 
energy efficiency; the lowest energy efficiency capability of 0 indicates a recom-
mendation to the OS to not schedule any software threads on it for efficiency 
reasons. An Energy Efficiency capability of 255 indicates which logical processors have the highest relative energy efficiency capability. In addition, the value 255 is 
an explicit recommendation for the OS to consolidate work on those logical 
processors for energy efficiency reasons. Initialized by the OS to 0.
...2*CP - 1 1 Capability 
#(CP-1)Class 1 Capability #(CP-1) if exists. If  the capability does  not exist (is not 
enumerated in the CPUID), the entry is unavailable (no space is reserved for future use here).Table 15-8.  Intel® Thread Director  Global Header Structure  (Contd.)
(Bytes)Description15-30 Vol. 3BPOWER AND THERMAL MANAGEMENT
15.6.3 Intel® Thread Director Usage Model
When the OS Scheduler needs to decide which one of mult iple free logical processors to assign to a software 
thread that is ready to execute, it can choose one of the following options:
1. The free logical processor with the highest performance va lue of that software thread class, if the system is 
scheduling for performance.
2. The free logical processor with the highest energy efficien cy value of that software thread class, if the system 
is scheduling for energy efficiency.
When the OS Scheduler needs to decide which of two logica l processors (i,j) to assign to which of two software 
threads whose Class IDs are k1 and k2, it can compute the two performance ratios: Perf Ratio1 = Perfik1 / Perfjk1

threads whose Class IDs are k1 and k2, it can compute the two performance ratios: Perf Ratio1 = Perfik1 / Perfjk1 
and Perf Ratio2 = Perfik2 / Perfjk2, or two energy efficiency ratios: Energy Eff. Ratio1 = Energy Effik1 / Energy Effjk1 
and Energy Eff. Ratio2 = Energy Effik2 / Energy Effjk2 between the two logical processors for each of the two classes, 
depending on whether the OS is scheduling for performance or for energy efficiency.
For example, assume that the system is scheduling for performance and that Perf Ratio1 > Perf Ratio2. The OS 
Scheduler will assign the software thread whose Class ID is  k1 to logical processor i, and the one whose Class ID is 
k2 to logical processor j.
When the two software threads in question belong to th e same Class ID, the OS Scheduler can schedule to higher 
performance logical processors within that class when sch eduling for performance and to  higher energy efficiency 
logical processors within that class when scheduling for energy efficiency.
The highest to lowest ordering may be different be tween classes across cores and between the performance 
column and the energy efficiency column of the same class across cores.2*CP R8 Padding Padding to nearest mu ltiple of 8 bytes. Initialized by  the OS to 0 prior to enabling 
...(CL-1)*CP 1 Performance 
CapabilityClass #(CL-1) Performance capability is an 8-bit value (0 ... 255) specifying the 
relative performance level of a single lo gical processor. Higher values indicate 
higher performance; the lowest performance level of 0 indicates a recommen-
dation to the OS to  not schedule any software th reads on it for performance 
reasons. Initialized by the OS to 0.
(CL-1)*CP + 1 1 Energy 
CapabilityClass #(CL-1) Energy Efficiency capability is an 8-bit value (0 ... 255) specifying the 
relative energy efficiency le vel of a logical processor. Hi gher values indicate higher 
processors for energy efficiency reasons.
...
CL*CP - 1 1 Capability 
#(CP-1)Class #(CL-1) Capability #(CP-1) if exists. If the capability do es not exist (is not 
use here).
CL*CP R8 Padding Padding to nearest multiple of 8 byte s. Initialized by the OS to 0 prior to enabling 
Intel Thread Director.Table 15-9.  Intel® Thread Director Lo gical Processor Entry Structure  (Contd.)
Byte Offset Size (Bytes) Field Name DescriptionVol. 3B 15-31POWER AND THERMAL MANAGEMENT
15.6.4 Hardware Feedback Interface Pointer
The physical address of the HFI/Intel Thread Director st ructure is programmed by the OS into a package scoped 
MSR named IA32_HW_FEEDBACK_PTR. The MSR is structured as follows:
•Bits 63:MAXPHYADDR1 – Reserved. 
•Bits MAXPHYADDR-1:12 – ADDR. This is the physical ad dress of the page frame of the first page of this 
•Bits 11:1 – Reserved. 
•Bit 0 – Valid. When set to 1, indicates a valid po inter is programmed into the ADDR field of the MSR.
The address of this MSR is 17D0H. This MSR is cleared on processor reset to its default value of 0. It retains its 
value upon INIT.
CPUID.06H.0H:EDX[11:8] enumerates the si ze of memory that must be allocated by the OS for this structure. 
15.6.5 Hardware Feedback Interface Configuration
The operating system enables HFI/Intel Thread Dire ctor using a package scoped MSR named IA32_HW_FEED-
BACK_CONFIG (address 17D1H). This MSR is cleared on processo r reset to its default value of 0. It retains its value 
upon INIT.
The MSR is structured as follows:
•Bits 63:2 – Reserved. 
•Bit 1 – Enable Intel Thread Director (or multi-class supp ort). Both bits 0 and 1 must be set for Intel Thread 
Director to be enabled. The extra class columns in th e Intel Thread Director tabl e are updated by hardware 
immediately following setting those two bits, as well as during run time as necessary.
•Bit 0 – Enable. When set to 1, enables HFI.
Before enabling HFI, the OS must set a valid hard ware feedback interface structure using IA32_HW_FEED-
BACK_PTR.
When the OS sets bit 0 only, the hardware populates class 0 capabilities only in the HFI structure. When bit 1 is set 
after or together with bit 0, the Intel Thread  Director multi-class structure is populated. 
When either the HFI structure or the Intel Thread Director  structure are ready to use by the OS, the hardware sets 
IA32_PACKAGE_THERM_STATUS[bit 26]. An interrupt is generated by the hardware if IA32_PACKAGE_THERM_IN-
TERRUPT[bit 25] is set. 
When the OS clears bit 1 but leaves bit 0 set, Intel Thre ad Director is disabled, but HFI is kept operational. 
IA32_PACKAGE_THERM_STATUS[bit 26] is NOT set in this case.
Clearing bit 0 disables both HFI and Intel Thread Director, independent of the bit 1 state. Setting bit 1 to '1' while 
keeping bit 0 at '0' is an invalid combination which is quietly ignored.
When the OS clears bit 0, hardware sets the IA32_ PACKAGE_THERM_STATUS[bit 26] to 1 to acknowledge 
disabling of the interface. The OS should wait for this bit to be set to 1 to reclaim the memory of the Intel Thread 
Director structure, as by setting IA32_PACKAGE_THERM_S TATUS[bit 26] hardware guarantees not to write into 
the Intel Thread Director structure anymore. 
The OS may clear bit 0 only after receiving an indication  from the hardware that the structure initialization is 
complete via the same IA32_PACKAGE_THERM_STATUS[bit 26] , following enabling of HFI/Intel Thread Director, 
thus avoiding a race condition between OS and hardware. 
Bit 1 is valid only if CPUID[6].EAX[bit 23] is set. When setting this bit while support is not enumerated, the hard-
ware generates #GP.
Table 15-10 summarizes the control options described above.See Section 15.6.9 for details on scenarios where IA32_ HW_FEEDBACK_CONFIG bits are implicitly reset by the 
hardware.
1. MAXPHYADDR is reported in CPUID.80000008H:EAX[7:0].15-32 Vol. 3BPOWER AND THERMAL MANAGEMENT
15.6.6 Hardware Feedback Interface Notifications
The IA32_PACKAGE_THERM_STATUS MSR is  extended with a new bit, hardwa re feedback interface structure 
change status (bit 26, R/WC0), to indicate that the hard ware has updated the HFI/Intel Thread Director structure. 
This is a sticky bit and once set, indicates that the OS sh ould read the structure to determine the change and adjust 
its scheduling decisions. Once set, the hardware will not ge nerate any further updates to this structure until the OS 
clears this bit by writing 0.
The OS can enable interrupt-based notifications when the structure is updated by hardware through a new enable 
bit, hardware feedback interrupt enable (bit 25, R/W) , in the IA32_PACKAGE_THERM_INTERRUPT MSR. When this 
bit is set to 1, it enables the generation of an interrupt when the HFI/Intel Thread Dire ctor structure is updated by 
hardware. When the enable bit transitions from 0 to 1, hard ware will generate an initial notify, with the IA32_PACK-
AGE_THERM_STATUS bit 26 set to 1, to indicate that th e OS should read the current HFI/Intel Thread Director 
structure.Table 15-10.   IA32_HW_FEEDBACK_CONFIG Control Options 
Pre-Bit 1 Pre-Bit 0 Post-Bit 1 Post-Bit 0 Action IA32_PACKAGE_THERM_STATUS [bit 26] and 
Interrupt
0 0 0 0 Reset value. Both Hardware Feedback Interface and Intel 
Thread Director are disabled, no status bit set, no 
interrupt is generated.
0001E n a b l e  H F I  s t r u c t u r e . S e t  t h e  s t a t us bit and genera te interrupt if 
enabled.
0010I n v a l i d  o p t i o n ;  q u i e t l y  
ignored by the hardware.No action (no update in the table).
0011E n a b l e  H F I  a n d  I n t e l  
Thread Director.Set the status bit and generate interrupt if 
enabled.
0 1 0 0 Disable HFI support. Set the stat us bit and genera te interrupt if 
enabled.
0110D i s a b l e  H F I  a n d  I n t e l  
enabled.
0111E n a b l e  I n t e l  T h r e a d  
Director.Set the status bit and generate interrupt if 
enabled.
1000N o  a c t i o n ;  k e e p s  H F I  a n d  
Intel Thread Director disabled.No action (no update in the table).
1001E n a b l e  H F I . S e t  t h e  s t a t u s  b i t and generate interrupt if 
enabled.
1011E n a b l e  H F I  a n d  I n t e l  
enabled.
1100D i s a b l e  H F I  a n d  I n t e l  
enabled.
1101D i s a b l e  I n t e l  T h r e a d  
Director; keep HFI 
enabled.No action (no update in the table).
1110D i s a b l e  H F I  a n d  I n t e l  
enabled.Vol. 3B 15-33POWER AND THERMAL MANAGEMENT

enabled.
enabled.
enabled.
enabled.
enabled.
enabled.
15.6.7 Hardware Feedback Interface and Intel®  Thread Director Structure Dynamic Update
The HFI/Intel Thread Director structure can be updated dy namically during run time. Changes to the structure may 
occur to one or more of its cells. Such changes may occur for one or more logical processors. The hardware sets a non-zero value in the “capability change” field of the HFI/Intel Thread Director structure as an indication for the OS 
to read that capability for all logical processors. A thermal interrupt is delivered to indicate to the OS that the struc-
ture has just changed. Section 15.6.6 contains more details  on this notification mechanism. The hardware clears 
all “capability change” fields after the OS  resets IA32_PACKAGE_THERM_STATUS[bit 26].
Zeroing a performance or energy efficiency  cell hints to the OS that it is beneficial not to schedule software threads 
of that class on the associated logical processor for perfor mance or energy efficiency reasons, respectively. If SMT 
is supported, it may be the case that  the hardware zeroes one of the core's logical processors only. Zeroing the 
performance and energy efficiency cells of all classes for a logical processor implies that the hardware provides a 
hint to the OS to completely avoid sched uling work on that logical processor. 
Zeroing a performance and energy efficiency cell hint of a logical processor across all classes along with Capability 
Flag bit 1 set to 1 across all capabilities and classes, indicates to the OS to force idle logical processor(s), and if affinitized activity occurs on those logical processor(s), the OS should inject idle periods such that overall utilization 
of those idled cores has a minimal-to-no impact to power. Capability Flag bit 1 will be set to 1 while this hint 
persists.
When EE=255 is set on one or more logical processors, it represents a request that the OS attempt to consolidate 
work to those logical processors with EE=255. These requ ests are made when the SOC has knowledge that consol-
idating the work to a subset of cores will result in sign ificantly better platform ener gy efficiency. Examples of 
consolidating work would include, but not limited to, dela ying less important work as needed to provide compute 
bandwidth for more important work, and routing interrupts to the logical processors wi th EE=255. When the cumu-
lative workload requires performance greater than that whic h is available on the subset of cores with EE=255, it is 
expected that the OS will scale the work out to additional logical processors.
A few example reasons for runtime changes in the HGS/Intel Thread Director Table:
•Over clocking run time update that changes the capability values.
•Change in run time physical constraints.
•Run time performance or energy efficiency optimization.
•Change in core frequency, voltage, or power budget.
15.6.8 Logical Processor Scope Intel®  Thread Director Configuration
The operating system enables Intel Thread Director at th e logical processor scope using a logical processor scope 
MSR named IA32_HW_FEEDBACK_THREAD_CONFIG (address 17D4H).
The MSR is read/write and is structured as follows:
•Bits 63:1 – Reserved. 
•Bit 0 – Enables Intel Thread Director. When set to 1, lo gical processor scope Intel Thread Director is enabled. 
Default is 0 (disabled).
Bit 0 of the logical processor scope configuration MSR can be cleared or set regardless of the state of the 
HFI/Intel Thread Director package configuration MSR state.  Even when bit 0 of all logical processor configuration 
MSRs is clear , the processor can still update the Intel Thread Director structure if it is still enabled in the 
IA32_HW_FEEDBACK_CONFIG package scope MSR. When the operating system clears 
IA32_HW_FEEDBACK_THREAD_CONFIG[bit 0], hardware clears the history accumulated on that logical processor which otherwise drives assigning the Class ID to the softwa re thread that executes on that logical processor. As 
long as IA32_HW_FEEDBACK_THREAD_CONFIG[bit 0] is set, th e Class ID is available for the operating system to 
read, independent of the state of the packag e scope IA32_HW_FEEDBACK_CONFIG[1:0] bits.
See Section 15.6.9 for details on scenarios where IA32_ HW_FEEDBACK_CONFIG bits are implicitly reset by the 
hardware.15-34 Vol. 3BPOWER AND THERMAL MANAGEMENT
15.6.9 Implicit Reset of Package and Logi cal Processor Scope Configuration MSRs
HFI/Intel Thread Director enable bits are re set by hardware in the following scenarios:
1. When GETSEC[SENTER] is executed:
a. The processor implicitly resets the HFI/Intel Thre ad Director enable bits in the IA32_HW_FEEDBACK_-
CONFIG MSR on all sockets (packages) in the system.
b. The processor implicitly resets the Intel Thread Di rector enable bit in the IA32_HW_FEEDBACK_THREAD_-
CONFIG MSR on all logical processors in the system across all sockets.
c. The processor implicitly clears the HFI/Intel Thread Director table structure pointer in the IA32_HW_FEED-
BACK_PTR package MSR across all sockets.
2. When GETSEC[ENTERACCS] is executed:
CONFIG MSR on the socket where the GETS EC[ENTERACCS] instruction was executed.
CONFIG MSR on all logical processors on the sock et where the GETSEC[ENT ERACCS] instruction was 
executed. 
BACK_PTR package MSR on the socket where th e GETSEC[ENTERACCS] instruction was executed.
3. When an INIT or a wait-for-SIPI state are processed by a logical processor:
a. The processor implicitly resets the Intel Thread Di rector enable bit in the IA32_HW_FEEDBACK_THREAD_-
CONFIG MSR on that logical processor, whether the si gnal was in the context of GETSEC[ENTERACCS] or 
not. 
If the OS requires HFI/Intel Thread Director to be active after exiting the measured environment or when 
processing a SIPI event, it should re-enable HFI/Intel Thread Director.
15.6.10 Logical Processor Scope Intel® Th read Director Run Time Characteristics
The processor provides the operating system with run ti me feedback about the execution characteristics of the 
software thread executing on logical processors wh ose IA32_HW_FEEDBACK_THREAD_CONFIG[bit 0] is set. 
The run time feedback is communicated via a read-onl y MSR named IA32_THREAD_F EEDBACK_CHAR. This is a 
logical processor scope MSR whose address is 17 D2H. This MSR is structured as follows: 
•Bit 63 – Valid bit. When set to 1 the OS Scheduler can use the Class ID (in bits 7:0) for its scheduling decisions. 
If this bit is 0, the Class ID field should be ignored. It  is recommended that the OS uses the last known Class ID 
of the software thread for its scheduling decisions. 
•Bits 62:8 – Reserved.
•Bits 7:0 – Application Class ID, pointing into the Intel Thread Director structure described in Table 15-8.
This MSR is valid only if CP UID.06H:EAX[bit 23] is set. 
The valid bit is cleared by the hardware in the following cases:
•The hardware does not have enough information to pr ovide the operating system with a reliable Class ID.
•The operating system cleared the logical proce ssor’s IA32_HW_FEEDBACK_THREAD_CONFIG[bit 0] bit.
The HRESET instruction is executed while configur ed to reset the Intel Thread Director history.
15.6.11 Logical Processor Scope History
The operating system can reset the Intel Thread Director  related history accumulated on the current logical pro-
cessor it is executing on by issuing the HRESET instruction. See “CPUID—CPU  Identification” in Chapter 3 of the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for enumeration of the HRESET Vol. 3B 15-35POWER AND THERMAL MANAGEMENT
instruction. See also the “HRESET—History Reset” instruction description in Chapter 3 of the Intel® 64 and IA-32 
15.6.11.1  Enabling Intel® Thread Director History Reset
The IA32_HRESET_ENABLE MSR is a read/wri te MSR and is structured as follows:
•Bits 63:32 – Reserved.
•Bits 31:1 – Reserved for other capabilities that can be reset by the HRESET instruction.
•Bit 0 – Enable reset of the Intel Thread Director history.
The operating system should set IA32_HRESET_ENABLE[bit 0]  to enable Intel Thread Director history reset via 
the HRESET instruction. 
15.6.11.2  Implicit Intel® Thread Director History Reset
The Intel Thread Director history is implicitly reset in the following scenarios:
1. When the processor enters or exits SMM mode and IA32_DEBUGCTL MSR.FREEZE_WHIL E_SMM (bit 14) is set, 
the Intel Thread Director history is implicitly reset by the processor.
2. When GETSEC[SENTER] is executed, the processor rese ts the Intel Thread Director history on all logical 
processors in the system, including logical processors on other sockets (other than the one GETSEC[SENTER] 
is executed).

3. When GETSEC[ENTERACCS] is executed, the processor rese ts the Intel Thread Director history on the logical 
processor it is executed on.
4. When an INIT or a wait-for-SIPI state are processed by a logical processor, the Intel Thread Director history is 
reset whether the signal was a resu lt of GETSEC[ENTERACCS] or not.
If the operating system requires HFI/Intel Thread Director  to be active after exiting the measured environment or 
when processing a SIPI event, it should re-enable HFI/Intel Thread Director.
15.7 MWAIT EXTENSIONS FOR ADVANCED POWER MANAGEMENT
IA-32 processors may support a number of C-states2 that reduce power consumption for inactive states. Intel Core 
Solo and Intel Core Duo processors support both deeper C- state and MWAIT extensions that can be used by OS to 
implement power management policy.
Software should use CPUID to discover if a target pr ocessor supports the enumeration of MWAIT extensions. If 
CPUID.05H.ECX[Bit 0] = 1, the target processor supports MWAIT extensions and their enumeration (see Chapter 
4, “Instruction Set Reference, M-U,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2B).
If CPUID.05H.ECX[Bit 1] = 1, the target processor support s using interrupts as break-events for MWAIT, even 
when interrupts are disabled. Use this feature to measure C-state residency as follows:
•Software can write to bit 0 in the MWAIT Extensions re gister (ECX) when issuing an MWAIT to enter into a 
processor-specific C-state or sub C-state.
•When a processor comes out of an inactive C-state or sub C-state, software can read a timestamp before an interrupt service routine (ISR) is potentially executed. 
CPUID.05H.EDX allows software to enumerate processor-specific C-states and sub C-states available for use with 
MWAIT extensions. IA-32 processors may support more than  one C-state of a given C-state type. These are called 
sub C-states. Numerically higher C-state have higher power savings and latency (upon entering and exiting) than 
lower-numbered C-state. 
2. The processor-specific C-states  defined in MWAIT extensions can map to ACPI defined C-state types (C0, C1, C2, C3). The mappi ng 
relationship depends on the definition of a C-state by processor implementation and is exposed to  OSPM by the BIOS using the AC PI 
defined _CST table.15-36 Vol. 3BPOWER AND THERMAL MANAGEMENT
At CPL = 0, system software can specify desired C-state an d sub C-state by using the MWAIT hints register (EAX). 
Processors will not go to C-state and sub C-state deeper than what is specified by the hint register. If CPL > 0 and if MONITOR/MWAIT is supported at CPL > 0, the processo r will only enter C1-state (regardless of the C-state 
request in the hints register). 
Executing MWAIT generates an exception on processors operating at a privilege level where MONITOR/MWAIT are 
NOTE
If MWAIT is used to enter a C-state (including su b C-state) that is numerically higher than C1, a 
store to the address range armed by MONITOR instru ction will cause the processor to exit MWAIT if 
the store was originated by other processor ag ents. A store from non-processor agent may not 
cause the processor to exit MWAIT. 
15.8 THERMAL MONITORING AND PROTECTION
The IA-32 architecture provides the following mechanis ms for monitoring temperature and controlling thermal 
power:
1. The catastrophic shutdown detector  forces processor execution to stop if the processor’s core temperature 
rises above a preset limit.
2.Automatic and adaptive thermal monitoring mechanism s force the processor to reduce it’s power 
consumption in order to operate within predetermined temperature limits.
3. The software controlled cloc k modulation mechanism  permits operating systems to implement power 
management policies that reduce power consumption; this is in addition to the reduction offered by automatic 
thermal monitoring mechanisms.
4.On-die digital thermal sensor  and interrupt mechanisms permit the  OS to manage thermal conditions 
natively without relying on BIOS or other system board components.
The first mechanism is not visible to software. The other three mechanisms are visible to software using processor 
feature information returned by executing CPUID with EAX = 1.
The second mechanism includes: 
•Automatic thermal monitoring  provides two modes of operation. One mode modulates the clock duty cycle; 
the second mode changes the processor’s frequency. Both modes are used to control the core temperature of the processor.
•Adaptive thermal monitoring  can provide flexible thermal management on processors made of multiple 
cores.
The third mechanism modulates the clock duty cycle of the processor. As shown in Figure 15-24, the phrase ‘duty 
cycle’ does not refer to the actual duty cycle of the clock si gnal. Instead it refers to the time period during which the 
clock signal is allowed to drive the processor chip. By using the stop clock mechanism to control how often the 
processor is clocked, processor power consumption can be modulated. 
Figure 15-24.  Processor Modulati on Through Stop-Clock MechanismClock Applied to Processor
Stop-Clock Duty Cycle
25% Duty Cycle (example only)Vol. 3B 15-37POWER AND THERMAL MANAGEMENT
For previous automatic thermal monitoring mechanisms, so ftware controlled mechanisms that changed processor 
operating parameters to impact changes in thermal conditions. Software did not have native access to the native thermal condition of the processor; nor could software al ter the trigger condition that initiated software program 
control. 
The fourth mechanism (listed above) provides access to an  on-die digital thermal sensor using a model-specific 
register and uses an interrupt mechanism to alert software to initiate digital thermal monitoring. 
15.8.1 Catastrophic Shutdown Detector
P6 family processors introduced a thermal sensor that acts as a catastrophic shutdown detector. This catastrophic 
shutdown detector was also implemented in Pentium 4, Intel Xeon and Pentium M processors. It is always enabled. When processor core temperature reaches a factory preset le vel, the sensor trips and processor execution is halted 
until after the next reset cycle.
15.8.2 Thermal Monitor
Pentium 4, Intel Xeon and Pentium M processors introduced a second temperature sensor that is factory-calibrated 
to trip when the processor’s core temperature crosses a level corresponding to the recommended thermal design 
envelop. The trip-temperature of the second sensor is  calibrated below the temperat ure assigned to the cata-
strophic shutdown detector. 
15.8.2.1  Thermal Monitor 1
The Pentium 4 processor uses the second temperature se nsor in conjunction with a mechanism called Thermal 
Monitor 1 (TM1) to control the core temperature of the processor. TM1 controls the processor’s temperature by 
modulating the duty cycle of the processor clock. Modulation  of duty cycles is processor model specific. Note that 
the processors STPCLK# pin is not used here; the stop-clock circuitry is controlled internally.
Support for TM1 is indicated by CPUID.1:EDX.TM[bit 29] = 1.TM1 is enabled by setting the thermal- monitor enable flag (bit 3) in IA32_MISC_ENABLE; see Chapter 2, “Model-
Specific Registers (MSRs)‚” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4. 
Following a power-up or reset, the flag is cleared, disab ling TM1. BIOS is required to  enable only one automatic 
thermal monitoring modes. Operating systems and applic ations must not disable the operation of these mecha-
nisms.
15.8.2.2  Thermal Monitor 2
An additional automatic thermal protection mechanism, called Thermal Monitor 2 (TM2), was introduced in the 
Intel Pentium M processor and also incorporated in newer models of the Pentium 4 processor family. Intel Core Duo 
and Solo processors, and Intel Core 2 Duo processor fa mily all support TM1 and TM2. TM2 controls the core 
temperature of the processor by reducing the operating fr equency and voltage of the processor and offers a higher 
performance level for a given level of power reduction than TM1.
TM2 is triggered by the same temperature sensor as TM1. The mechanism to enable TM2 may be implemented 
differently across various IA-32 processor families with di fferent CPUID signatures in the family encoding value, 
but will be uniform within an IA-32 processor family. 
Support for TM2 is indicated by CPUID.1:ECX.TM2[bit 8] = 1.
15.8.2.3  Two Methods for Enabling TM2
On processors with CPUID family/model/stepping signature encoded as 0x69n or 0x6Dn (early Pentium M proces-
sors), TM2 is enabled if the TM_SELECT flag (bit 16) of  the MSR_THERM2_CTL register is set to 1 (Figure 15-25) 
and bit 3 of the IA32_MISC_ENABLE register is set to 1. 15-38 Vol. 3BPOWER AND THERMAL MANAGEMENT
Following a power-up or reset, the TM_SELECT flag may be cl eared. BIOS is required to enable either TM1 or TM2.

Following a power-up or reset, the TM_SELECT flag may be cl eared. BIOS is required to enable either TM1 or TM2. 
Operating systems and applications must not disable mechan isms that enable TM1 or TM2. If bit 3 of the IA32_-
MISC_ENABLE register is set and TM_SELECT flag of the MSR_THERM2_CTL register is cleared, TM1 is enabled.
On processors introduced after the Pentium 4 processor (this includes most Pentium M processors), the method 
used to enable TM2 is different. TM2 is enable by setting bit 13 of IA32_MISC_ENABLE register to 1. This applies to 
Intel Core Duo, Core Solo, and Intel Core 2 processor family.
The target operating frequency and voltage for the TM2 tran sition after TM2 is triggered is specified by the value 
written to MSR_THERM2_CTL, bits 15:0 (Figure 15-26). Followi ng a power-up or reset, BIOS is required to enable 
at least one of these two thermal monitoring mechanis ms. If both TM1 and TM2 are supported, BIOS may choose 
to enable TM2 instead of TM1. Operating systems and appl ications must not disable the mechanisms that enable 
TM1or TM2; and they must not alter the value in  bits 15:0 of the MSR_THERM2_CTL register.
15.8.2.4  Performance State Transitions and Thermal Monitoring
If the thermal control circuitry (TCC) for thermal monito r (TM1/TM2) is active, writes to the IA32_PERF_CTL will 
effect a new target operating point as follows:
•If TM1 is enabled and the TCC is engaged, the perfor mance state transition can commence before the TCC is 
disengaged. 
•If TM2 is enabled and the TCC is engaged, the perfor mance state transition specified by a write to the 
IA32_PERF_CTL will commence after the TCC has disengaged. 
15.8.2.5  Thermal Status Information
The status of the temperature sensor that triggers the thermal monitor (TM1/TM2) is indicated through the thermal 
status flag and thermal status log flag in the IA32_THERM_STATUS MSR (see Figure 15-27). 
The functions of these flags are:
•Thermal Status flag, bit 0 — When set, indicates that the processor co re temperature is currently at the trip 
temperature of the thermal monitor and that the proce ssor power consumption is being reduced via either TM1 
or TM2, depending on which is enabled. When clear, th e flag indicates that the core temperature is below the 
thermal monitor trip temperature. This flag is read only. Figure 15-25.  MSR_THERM2_CTL Regi ster On Processors with  CPUID Family/Model/Stepping Signature Encoded 
as 0x69n or 0x6Dn
Figure 15-26.  MSR_THERM2_CTL  Register for Supporting TM2TM_SELECTReserved31 0
Reserved16
63 0
TM2 Transition Target Vol. 3B 15-39POWER AND THERMAL MANAGEMENT
•Thermal Status Log flag, bit 1 — When set, indicates that the thermal sensor has tripped since the last 
power-up or reset or since the last time that software cleared this flag. This flag is a sticky bit; once set it remains set until cleared by software or until a power-up or reset of the processor. The default state is clear.
After the second temperature sensor has been tripped, the thermal monitor (TM1/TM2) will remain engaged for a 
minimum time period (on the order of 1 ms). The thermal monitor will remain engaged until the processor core 
temperature drops below the preset trip temperature of the temperature sensor, taking hysteresis into account.
While the processor is in a stop-clock state, interrupts w ill be blocked from interrupting the processor. This holding 
off of interrupts increases the interrupt latency, but does  not cause interrupts to be lost. Outstanding interrupts 
remain pending until clock modulation is complete. 
The thermal monitor can be programmed to generate an interrupt to the processor when the thermal sensor is 
tripped; this is called a thermal interrupt. The deliv ery mode, mask, and vector for this interrupt can be 
programmed through the thermal entry in the local APIC’s LVT (see Section 11.5.1, “Local Vector Table”). The low-
temperature interrupt enable and high-temperature inte rrupt enable flags in the IA32_THERM_INTERRUPT MSR 
(see Figure 15-28) control when the interrupt is generated; that is, on a transition from a temperature below the 
trip point to above and/or vice-versa.
•High-Temperature Interrupt Enable flag, bit 0 — Enables an interrupt to be generated on the transition 
from a low-temperature to a high-temperature when set; disables the interrupt when clear.(R/W).
•Low-Temperature Interrupt Enable flag, bit 1 — Enables an interrupt to be generated on the transition 
from a high-temperature to a low-temperature when set; disables the interrupt when clear.
The thermal interrupt can be masked by the thermal LVT entry. After a power-up or reset, the low-temperature 
interrupt enable and high-temperature interrupt enab le flags in the IA32_THERM_INTERRUPT MSR are cleared 
(interrupts are disabled) and the thermal LVT entry is set to mask interrupts. This interrupt should be handled 
either by the operating system or system management mode (SMM) code.
Note that the operation of the thermal monitoring mechanis m has no effect upon the clock rate of the processor's 
internal high-resolution timer (time stamp counter). 
15.8.2.6  Adaptive Thermal Monitor 
The Intel Core 2 Duo processor family supports enhanced  thermal management mechanism, referred to as Adap-
tive Thermal Monitor (Adaptive TM). 
Unlike TM2, Adaptive TM is not limited to one TM2 transiti on target. During a thermal trip event, Adaptive TM (if 
enabled) selects an optimal target operating point based on whether or not the current operating point has effec-
tively cooled the processor.Figure 15-27.  IA32_THERM_STATUS MSR
Figure 15-28.  IA32_THERM_INTERRUPT MSR63 0
Reserved12
Thermal StatusThermal Status Log
63 0
High-Temperature Interrupt EnableLow-Temperature Interrupt Enable15-40 Vol. 3BPOWER AND THERMAL MANAGEMENT
Similar to TM2, Adaptive TM is enable by BIOS. The BIOS  is required to test the TM1 and TM2 feature flags and 
enable all available thermal control mechanisms (i ncluding Adaptive TM) at platform initiation. 
Adaptive TM is available only to a subset of processors that support TM2.
In each chip-multiprocessing (CMP) silicon die, each core  has a unique thermal sensor that triggers independently. 
These thermal sensor can trigger TM1 or TM2 transitions in  the same manner as described in Section 15.8.2.1 and 
Section 15.8.2.2. The trip point of the thermal sensor is not programmable by software since it is set during the 
fabrication of the processor. 
Each thermal sensor in a processor core may be triggere d independently to engage thermal management features. 
In Adaptive TM, both cores will transition to a lower freque ncy and/or lower voltage level if one sensor is triggered.
Triggering of this sensor is visible to software via the th ermal interrupt LVT entry in the local APIC of a given core. 
15.8.3 Software Controlled Clock Modulation
Pentium 4, Intel Xeon and Pentium M processors also supp ort software-controlled clock modulation. This provides 
a means for operating systems to implement a power mana gement policy to reduce the power consumption of the 
processor. Here, the stop-clock duty cycle is contro lled by software through the IA32_CLOCK_MODULATION MSR 
(see Figure 15-29). 
The IA32_CLOCK_MODULATION MSR contains  the following flag and field used to enable software-controlled clock 
modulation and to select the clock modulation duty cycle:
•On-Demand Clock Modulation Enable, bit 4 — Enables on-demand software controlled clock modulation 
when set; disables software-controlled clock modulation when clear.
•On-Demand Clock Modulation Du ty Cycle, bits 1 through 3 — Selects the on-demand clock modulation 
duty cycle (see Table 15-11). This field is only active when the on-demand clock modulation enable flag is set.
Note that the on-demand clock modulation mechanism (like the thermal monitor) controls the processor’s stop-
clock circuitry internally to modulate the clock signal. The STPCLK# pin is not used in this mechanism.Figure 15-29.  IA32_CLOCK_MODULATION MSR
Table 15-11.  On-Demand Clock Modu lation Duty Cycle Field Encoding
Duty Cycle Field Encoding Duty Cycle
000B Reserved001B 12.5% (Default)010B 25.0%
011B 37.5%
100B 50.0%101B 63.5%
110B 75%
111B 87.5%63 0
Reserved13
On-Demand Clock Modulation Duty CycleOn-Demand Clock Modulation Enable45
ReservedVol. 3B 15-41POWER AND THERMAL MANAGEMENT
The on-demand clock modulation mechanism can be used to control processor power consumption. Power 
management software can write to the IA32_CLOCK_MODULATION MSR to enable clock modulation and to select a modulation duty cycle. If on-demand clock modulation and TM1 are both enabled and the thermal status of the 
processor is hot (bit 0 of the IA32_THERM_STATUS MSR is se t), clock modulation at the duty cycle specified by TM1 
takes precedence, regardless of the setting of the on-demand clock modulation duty cycle.
For Hyper-Threading Technology enabled processors, th e IA32_CLOCK_MODULATION register is duplicated for

011B 37.5%
110B 75%
For Hyper-Threading Technology enabled processors, th e IA32_CLOCK_MODULATION register is duplicated for 
each logical processor. In order for the On-demand clock mo dulation feature to work properly, the feature must be 
enabled on all the logical processors within a physical proc essor. If the programmed duty cycle is not identical for 
all the logical processors, the processor core clock will modulate to the highest duty cycle programmed for proces-
sors with any of the following CPUID DisplayFamily_Disp layModel signatures (see CPUI D instruction in Chapter3, 
“Instruction Set Reference, A-L” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
2A): 06_1A, 06_1C, 06_1E, 06_1F, 06_25, 06_26, 06_27, 06_2C, 06_2E, 06_2F, 06_35, 06_36, and 0F_xx. For all 
other processors, if the programmed duty cycle is not identical for all logical processors in the same core, the processor core will modulate at the lowest programmed duty cycle. 
For multiple processor cores in a physical package, each processor core can modulate to a programmed duty cycle 
independently.
For the P6 family processors, on-demand clock modulation  was implemented through the chipset, which controlled 
clock modulation through the processor’s STPCLK# pin.
15.8.3.1  Extension of Softwa re Controlled Clock Modulation
Extension of the software controlled clock modulation faci lity supports on-demand clock modulation duty cycle with 
4-bit dynamic range (increased from 3-bit range). Granularit y of clock modulation duty cycle is increased to 6.25% 
(compared to 12.5%).
Four bit dynamic range control is provided by using bit 0 in conjunction with bits 3:1 of the IA32_CLOCK_MODULA-
TION MSR (see Figure 15-30).
Extension to software controlled clock modulation is  supported only if CPUID.06H:EAX[Bit 5] = 1. If 
CPUID.06H:EAX[Bit 5] = 0, then bit 0 of IA32_CLOCK_MODULATION is reserved.
15.8.4 Detection of Thermal Monitor and Softwa re Controlled Clock Modulation Facilities
The ACPI flag (bit 22) of the CPUID feature flags indi cates the presence of the IA32_THERM_STATUS, IA32_THER-
M_INTERRUPT, IA32_CLOCK_MODULATION MSRs, and the xAPIC thermal LVT entry. 
The TM1 flag (bit 29) of the CPUID feature flags indicates the presence of the automatic thermal monitoring facili-
ties that modulate clock duty cycles.
15.8.4.1  Detection of Software Controlled Clock Modulation Extension
Processor’s support of software controlled clock modulation  extension is indicated by CPUID.06H:EAX[Bit 5] = 1. Figure 15-30.  IA32_CLOCK_MODULATION MSR with Clock Modulation Extension63 0
Reserved3
Extended On-Demand Clock Modulation Duty CycleOn-Demand Clock Modulation Enable45
Reserved15-42 Vol. 3BPOWER AND THERMAL MANAGEMENT
15.8.5 On Die Digital Thermal Sensors
On die digital thermal sensor can be read using an MSR (n o I/O interface). In Intel Core Duo processors, each core 
has a unique digital sensor whose temperature is accessi ble using an MSR. The digi tal thermal sensor is the 
preferred method for reading the die temperature because (a) it  is located closer to the hottest portions of the die, 
(b) it enables software to accurately track the die temp erature and the potential activation of thermal throttling.
15.8.5.1  Digital Ther mal Sensor Enumeration
The processor supports a digital thermal sensor if CPUID. 06H.EAX[0] = 1. If the processor supports digital thermal 
sensor, EBX[bits 3:0] determine the number of thermal thresholds that are available for use. 
Software sets thermal thresholds by using the IA32_THERM_INTERRUPT MSR. Software reads output of the digital 
thermal sensor using the IA32_THERM_STATUS MSR.
15.8.5.2  Reading the Digital Sensor
Unlike traditional analog thermal devices, the output of th e digital thermal sensor is a temperature relative to the 
maximum supported operating temperature of the processor.
Temperature measurements returned by digital thermal sensors are always at or below TCC activation tempera-
ture. Critical temperature conditions are detected using the “Critical Temperature Status” bit. When this bit is set, 
the processor is operating at a critical temperature and i mmediate shutdown of the system should occur. Once the 
“Critical Temperature Status” bit is set, reliable operation is not guaranteed. 
See Figure 15-31 for the layout of IA32_THERM_STATUS MSR. Bit fields include:
•Thermal Status (bit 0, RO) — This bit indicates whether the digital thermal sensor high-temperature output 
signal (PROCHOT#) is currently active. Bit 0 = 1 indicates the feature is active. This bit may not be written by 
software; it reflects the state of the digital thermal sensor.
•Thermal Status Log (bit 1, R/WC0) — This is a sticky bit that indicates the history of the thermal sensor 
high temperature output signal (PROCHOT#). Bit 1 = 1 if PROCHOT# has been asserted since a previous 
RESET or the last time software cleared the bit. Software may clear this bit by writing a zero.
•PROCHOT# or FORCEPR# Event (bit 2, RO) — Indicates whether PROCHOT# or FORCEPR# is being 
asserted by another agent on the platform. 
Figure 15-31.  IA32_THERM_STATUS Register 63 0
Thermal Threshold #2 Status Thermal Threshold #1 Log
Thermal Threshold #1 Status
Power Limit Notification StatusVol. 3B 15-43POWER AND THERMAL MANAGEMENT
•PROCHOT# or FORCEPR# Log (bit 3, R/WC0) — Sticky bit that indicates whether PROCHOT# or 
FORCEPR# has been asserted by another agent on the platfo rm since the last clearing of this bit or a reset. If 
bit 3 = 1, PROCHOT# or FORCEPR# has been externally asse rted. Software may clear this bit by writing a zero. 
External PROCHOT# assertions are only acknowledged if the Bidirectional Prochot feature is enabled.
•Critical Temperature Status (bit 4, RO) — Indicates whether the critical temperature detector output signal 
is currently active. If bit 4 = 1, the critical temper ature detector output signal is currently active.
•Critical Temperature Log (bit 5, R/WC0) — Sticky bit that indicates whether the critical temperature 
detector output signal has been asserted since the last clearing of this bit or reset. If bit 5 = 1, the output 
signal has been asserted. Software may clear this bit by writing a zero.
•Thermal Threshold #1 Status (bit 6, RO) — Indicates whether the actual temperature is currently higher 
than or equal to the value set in Thermal Threshold #1. If bit 6 = 0, the actual temperature is lower. If bit 6 = 1, the actual temperature is greater than or equal to TT#1. Quantitative information of actual 
temperature can be inferred from Digital Readout, bits 22:16.
•Thermal Threshold #1 Log (bit 7, R/WC0) — Sticky bit that indicates whether the Thermal Threshold #1 
has been reached since the last clearing of this bit or a reset. If bit 7 = 1, the Threshold #1 has been reached. 
Software may clear this bit by writing a zero.
•Thermal Threshold #2 Status (bit 8, RO) — Indicates whether actual temperature is currently higher than 
or equal to the value set in Thermal Threshold #2. If bit 8 = 0, the actual temperature is lower. If bit 8 = 1, the 
actual temperature is greater than or equal to TT#2. Quantitative information of actual temperature can be 
inferred from Digital Readout, bits 22:16.
•Thermal Threshold #2 Log (bit 9, R/WC0) — Sticky bit that indicates whether the Thermal Threshold #2 
has been reached since the last clearing of this bit or a reset. If bit 9 = 1, the Thermal Threshold #2 has been reached. Software may clear this bit by writing a zero.
•Power Limitation Status (bit 10, RO) — Indicates whether the processor is currently operating below OS-
requested P-state (specified in IA32_PERF_CTL) or OS-r equested clock modulation duty cycle (specified in 
IA32_CLOCK_MODULATION). This field is supported only if CPUID.06H:EAX[bit 4] = 1. Package level power 
limit notification can be delivered inde pendently to IA32_PACKAGE_THERM_STATUS MSR.
•Power Notification Log (bit 11, R/WCO) — Sticky bit that indicates the processor went below OS-
requested P-state or OS-requested clock modulation duty cycle since the last clearing of this or RESET. This 
field is supported only if CPUID.06H:EAX[bit 4] = 1.  Package level power limit notification is indicated 
independently in IA32_PACKAGE_THERM_STATUS MSR.
•Digital Readout (bits 22:16, RO) — Digital temperature reading in 1 degree Celsius relative to the TCC 
activation temperature. 
0: TCC Activation temperature, 1: (TCC Activation - 1) , etc. See the processor’ s data sheet for details regarding TCC activation.
A lower reading in the Digital Readout field (bits 22:16) indicates a higher actual temperature.
•Resolution in Degrees Celsius (bits 30:27, RO) — Specifies the resolution (or tolerance) of the digital 
thermal sensor. The value is in degrees Celsius. It is re commended that new threshold values be offset from the

thermal sensor. The value is in degrees Celsius. It is re commended that new threshold values be offset from the 
current temperature by at least the resolution + 1 in order to avoid hysteresis of interrupt generation.
•Reading Valid  (bit 31, RO)  — Indicates if the digital readout in bits 22:16 is valid. The readout is valid if 
bit 31 = 1.
Changes to temperature can be detected  using two thresholds (see Figure 15-32); one is set above and the other 
below the current temperature. These thresholds have the capability of generating interrupts using the core's local 
APIC which software must then service. Note that the local APIC entries used by these thresholds are also used by 
the Intel® Thermal Monitor; it is up to software to determine the source of a specific interrupt.15-44 Vol. 3BPOWER AND THERMAL MANAGEMENT
See Figure 15-32 for the layout of IA32_THERM_INTERRUPT MSR. Bit fields include:
•High-Temperature Interrup t Enable (bit 0, R/W)  — This bit allows the BIOS to enable the generation of 
an interrupt on the transition from low-temperature to a high-temperature threshold. Bit 0 = 0 (default) 
disables interrupts; bit 0 = 1 enables interrupts.
•Low-Temperature Interrupt Enable (bit 1, R/W) — This bit allows the BIOS to enable the generation of an 
interrupt on the transition from high-temperature to a low-temperature (TCC de-activation). Bit 1 = 0 (default) 
disables interrupts; bit 1 = 1 enables interrupts.
•PROCHOT# Interrupt Enable (bit 2, R/W) — This bit allows the BIOS or OS to enable the generation of an 
interrupt when PROCHOT# has been asserted by anothe r agent on the platform and the Bidirectional Prochot 
feature is enabled. Bit 2 = 0 disables th e interrupt; bit 2 = 1 enables the interrupt.
•FORCEPR# Interrupt Enable (bit 3, R/W) — This bit allows the BIOS or OS to enable the generation of an 
interrupt when FORCEPR# has been asserted by anot her agent on the platform. Bit 3 = 0 disables the 
interrupt; bit 3 = 1 enables the interrupt.
•Critical Temperature Interrupt Enable (bit 4, R/W) — Enables the generation of an interrupt when the 
Critical Temperature Detector has detected a critical thermal condition. The recommended response to this 
condition is a system shutdown. Bit 4 = 0 disabl es the interrupt; bit 4 = 1 enables the interrupt.
•Threshold #1 Value (bits 14:8, R/W) — A temperature threshold, encoded relative to the TCC Activation 
temperature (using the same format as the Digital Read out). This threshold is compared against the Digital 
Readout and is used to generate the Thermal Threshold #1 Status and Log bits as well as the Threshold #1 
thermal interrupt delivery.
•Threshold #1 Interrupt Enable (bit 15, R/W) — Enables the generation of an interrupt when the actual 
temperature crosses the Threshold #1 setting in any direction. Bit 15 = 1 enables the interrupt; bit 15 = 0 disables the interrupt.
•Threshold #2 Value (bits 22:16, R/W) —A temperature threshold, encoded relative to the TCC Activation 
Readout and is used to generate the Thermal Threshold #2 Status and Log bits as well as the Threshold #2 
•Threshold #2 Interrupt Enable (bit 23, R/W) — Enables the generation of an interrupt when the actual 
temperature crosses the Threshold #2 setting in any di rection. Bit 23 = 1enables the interrupt; bit 23 = 0 
disables the interrupt.
•Power Limit Notification Enable (bit 24, R/W) — Enables the generation of power notification events when 
the processor went below OS-requested P-state or OS-req uested clock modulation duty cycle. This field is 
supported only if CPUID.06H:EAX[bit 4] = 1. Pack age level power limit notification can be enabled 
independently by IA32_PACKAGE_THERM_INTERRUPT MSR.Figure 15-32.  IA32_THERM_INTERRUPT Register 63 0
Threshold #2 Interrupt Enable 12345 8 14 16 222324
Threshold #2 Value 
Threshold #1 Interrupt Enable Threshold #1 Value
Overheat Interrupt Enable
FORCPR# Interrupt Enable PROCHOT# Interrupt Enable 
Low Temp. Interrupt Enable 
High Temp. Interrupt Enable25
Power Limit Notification Enable Vol. 3B 15-45POWER AND THERMAL MANAGEMENT
15.8.6 Power Limit Notification
Platform firmware may be capable of sp ecifying a power limit to restrict power delivered to a platform component, 
such as a physical processor package. This constraint imposed by platform firmware may occasionally cause the 
processor to operate below OS-requested P or T-state. A power limit notification event can be delivered using the existing thermal LVT entry in the local APIC. 
Software can enumerate the presence of the processor’ s support for power limit no tification by verifying 
CPUID.06H:EAX[bit 4] = 1.
If CPUID.06H:EAX[bit 4] = 1, then IA32_THERM_INTE RRUPT and IA32_THERM_STATU S provides the following 
facility to manage power limit notification:
•Bits 10 and 11 in IA32_THERM_STATUS informs software  of the occurrence of processor operating below OS-
requested P-state or clock modulation duty cycle setting (see Figure 15-31).
•Bit 24 in IA32_THERM_INTERRUPT enables the local APIC  to deliver a thermal event when the processor went 
below OS-requested P-state or clock modulation duty cycle setting (see Figure 15-32).
15.9 PACKAGE LEVEL THERMAL MANAGEMENT
The thermal management facilities like IA32_THER M_INTERRUPT and IA32_THERM_STATUS are often imple-
mented with a processor core granularity. To facilitate software manage thermal events from a package level gran-
ularity, two architectural MSR is provided for package level thermal management. The 
IA32_PACKAGE_THERM_STATUS and IA32_PACKAGE_THER M_INTERRUPT MSRs use similar interfaces as 
IA32_THERM_STATUS and IA32_THERM_INTERRUPT, but ar e shared in each physical processor package.
Software can enumerate the presence of the processor’ s support for package level thermal management facility 
(IA32_PACKAGE_THERM_STATUS and IA32_PACKAGE_THERM_I NTERRUPT) by verifying CPUID.06H:EAX[bit 6] = 
1.
The layout of IA32_PACKAGE_THERM_STA TUS MSR is shown in Figure 15-33.
•Package Thermal Status (bit 0, RO) — This bit indicates whether the digital thermal sensor high-
temperature output signal (PROCHOT#) for the package is currently active. Bit 0 = 1 indicates the feature is 
active. This bit may not be written by software; it reflects the state of the digital thermal sensor.Figure 15-33.  IA32_PACKAGE_THERM_STATUS Register 63 0
Reserved15 12345 8 10 16 2223 27
PKG Digital Readout
PKG Thermal Threshold #2 Log
PKG Thermal Threshold #2 Status 
PKG Thermal Threshold #1 Log
PKG Thermal Threshold #1 StatusPKG Critical Temperature Log67 9 3132
PKG Critical Temperature Status
PKG PROCHOT# or FORCEPR# LogPKG PROCHOT# or FORCEPR# Event
PKG Thermal Status Log
PKG Thermal Status11
PKG Power Limit Notification Log
PKG Power Limit Notification Status15-46 Vol. 3BPOWER AND THERMAL MANAGEMENT
•Package Thermal Status Log (bit 1, R/WC0) — This is a sticky bit that indicates the history of the thermal 
sensor high temperature output signal (PROCHOT#) of the package. Bit 1 = 1 if package PROCHOT# has been asserted since a previous RESET or the last time software  cleared the bit. Software may clear this bit by writing 
a zero.
•Package PROCHOT# Event (bit 2, RO) — Indicates whether package PROCHOT# is being asserted by 
another agent on the platform. 
•Package PROCHOT# Log (bit 3, R/WC0) — Sticky bit that indicates whether package PROCHOT# has been 
asserted by another agent on the platform since the last  clearing of this bit or a reset. If bit 3 = 1, package 
PROCHOT# has been externally asserted. Soft ware may clear this bit by writing a zero. 
•Package Critical Temperature Status (bit 4, RO) — Indicates whether the package critical temperature 
detector output signal is currently active. If bit 4 = 1, the package critical temperature detector output signal 
is currently active.
•Package Critical Temperature Log (bit 5, R/WC0) — Sticky bit that indicates whether the package critical 
temperature detector output signal has been asserted since the last clearing of this bit or reset. If bit 5 = 1, the 
output signal has been asserted. Software may clear this bit by writing a zero.
•Package Thermal Threshold #1 Status (bit 6, RO) — Indicates whether the actual package temperature is 
currently higher than or equal to the value set in Package Thermal Threshold #1. If bit 6 = 0, the actual 
temperature is lower. If bit 6 = 1, the actual temperature is greater than or equal to PTT#1. Quantitative information of actual package temperature can be inferred from Package Digital Readout, bits 22:16.
•Package Thermal Threshold #1 Log (bit 7, R/WC0) — Sticky bit that indicates whether the Package 
Thermal Threshold #1 has been reached since the last clea ring of this bit or a reset. If bit 7 = 1, the Package 
Threshold #1 has been reached. Software  may clear this bit by writing a zero.
•Package Thermal Threshold #2 Status (bit 8, RO) — Indicates whether actual package temperature is 
currently higher than or equal to the value set in Package Thermal Threshold #2. If bit 8 = 0, the actual

currently higher than or equal to the value set in Package Thermal Threshold #2. If bit 8 = 0, the actual 
temperature is lower. If bit 8 = 1, the actual temperature is greater than or equal to PTT#2. Quantitative 
information of actual temperature can be infe rred from Package Digital Readout, bits 22:16.
•Package Thermal Threshold #2 Log (bit 9, R/WC0) — Sticky bit that indicates whether the Package 
Thermal Threshold #2 has been reached since the last clea ring of this bit or a reset. If bit 9 = 1, the Package 
Thermal Threshold #2 has been reached. Software may clear this bit by writing a zero.
•Package Power Limitation Status (bit 10, RO) — Indicates package power limit is forcing one ore more 
processors to operate below OS-requested P-state. Note that package power limit violation may be caused by processor cores or by devices residing in the uncore . Software can examine IA32_THERM_STATUS to determine 
if the cause originates from a processor core (see Figure 15-31).
•Package Power Notification  Log (bit 11, R/WCO) — Sticky bit that indicates any processor in the package 
went below OS-requested P-state or OS-requested clock modulation duty cycle since the last clearing of this or RESET. 
•Package Digital Readout (bits 22:16, RO) — Package digital temperature reading in 1 degree Celsius 
relative to the package TCC activation temperature. 
0: Package TCC Activation temperature, 1: (PTCC Activation - 1) , etc. See the processor’s data sheet for details regarding PTCC activation.A lower reading in the Package Digital Readout field (bits 22:16) indicates a higher actual temperature.
The layout of IA32_PACKAGE_THERM_INTER RUPT MSR is shown in Figure 15-34.Vol. 3B 15-47POWER AND THERMAL MANAGEMENT
•Package High-Temperature Inte rrupt Enable (bit 0, R/W)  — This bit allows the BIOS to enable the 
generation of an interrupt on the transition from lo w-temperature to a package hi gh-temperature threshold. 
Bit 0 = 0 (default) disables interrupts; bit 0 = 1 enables interrupts.
•Package Low-Temperature Interr upt Enable (bit 1, R/W) — This bit allows the BIOS to enable the 
generation of an interrupt on the transition from high -temperature to a low-temperature (TCC de-activation). 
Bit 1 = 0 (default) disables interrupts; bit 1 = 1 enables interrupts.
•Package PROCHOT# Interrup t Enable (bit 2, R/W) — This bit allows the BIOS or OS to enable the 
generation of an interrupt when Package PROCHOT# has been asserted by another agent on the platform and 
the Bidirectional Prochot feature is enabled. Bit 2 = 0 disables the interrupt; bit 2 = 1 enables the interrupt.
•Package Critical Temperature In terrupt Enable (bit 4, R/W) — Enables the generation of an interrupt 
when the Package Critical Temperature Detector has de tected a critical thermal condition. The recommended 
response to this condition is a system shutdown. Bit 4 = 0 disables the interrupt; bit 4 = 1 enables the 
•Package Threshold #1 Va lue (bits 14:8, R/W) — A temperature threshold, encoded relative to the 
Package TCC Activation temperature (using the same format as the Digital Readout). This threshold is compared against the Package Digital Readout and is used to generate the Package Thermal Threshold #1 
Status and Log bits as well as the Pack age Threshold #1 thermal interrupt delivery.
•Package Threshold #1 Interr upt Enable (bit 15, R/W) — Enables the generation of an interrupt when the 
actual temperature crosses the Package Threshold #1 setti ng in any direction. Bit 15 = 1 enables the interrupt; 
bit 15 = 0 disables the interrupt.
•Package Threshold #2 Value (bits 22:16, R/W) —A temperature threshold, encoded relative to the PTCC 
Activation temperature (using the same format as the Package Digital Readout). This threshold is compared 
against the Package Digital Readout and is used to gene rate the Package Thermal Threshold #2 Status and Log 
bits as well as the Package Threshold #2 thermal interrupt delivery.
•Package Threshold #2 Interr upt Enable (bit 23, R/W) — Enables the generation of an interrupt when the 
actual temperature crosses the Package Threshold #2 setti ng in any direction. Bit 23 = 1 enables the interrupt; 
bit 23 = 0 disables the interrupt.
•Package Power Limit Notificati on Enable (bit 24, R/W) — Enables the generation of package power 
notification events.
15.9.1 Support for Passive and Active cooling
Passive and active cooling may be cont rolled by the OS power management agent through ACPI control methods. 
On platforms providing packag e level thermal management facility described in the previous section, it is recom-
mended that active cooling (FAN control) should be driven by measuring the package temperature using the 
IA32_PACKAGE_THERM_INTERRUPT MSR. Figure 15-34.  IA32_PACKAGE_THERM_INTERRUPT Register 63 0
Pkg Threshold #2 Interrupt Enable 12345 8 14 16 222324
Pkg Threshold #2 Value 
Pkg Threshold #1 Interrupt Enable Pkg Threshold #1 Value
Pkg Overheat Interrupt Enable
Pkg PROCHOT# Interrupt Enable 
Pkg Low Temp. Interrupt Enable 
Pkg High Temp. Interrupt Enable25
Pkg Power Limit Notification Enable 15-48 Vol. 3BPOWER AND THERMAL MANAGEMENT
Passive cooling (frequency throttling) should be driven by measuring (a) the core and package temperatures, or 
(b) only the package temperature. If measured packag e temperature led the power management agent to choose 
which core to execute passive cooling, then all cores need to execute passive cooling. Core temperature is 
measured using the IA32_THERMAL_STATUS and IA32_T HERMAL_INTERRUPT MSRs. The exact implementation 
details depend on the platform firmware and possible solu tions include defining two different thermal zones (one 
for core temperature and passive cooling and the other for package temperature and active cooling).
15.10 PLATFORM SPECIFIC POWER MANAGEMENT SUPPORT
This section covers power management interfaces that are not architectural but addresses the power management needs of several platform specific components. Specifically , RAPL (Running Average Power Limit) interfaces provide 
mechanisms to enforce power consumption limit. Power limiti ng usages have specific usages in client and server 
platforms. 
For client platform power limit control and for server platforms used in a data center, the following power and 
thermal related usages are desirable:
•Platform Thermal Management: Robust mechanisms to manage component, platform, and group-level 
thermals, either proactively or reactively (e.g., in  response to a platform-level thermal trip point).
•Platform Power Limiting: More deterministic control over  the system's power consumption, for example to meet 
battery life targets on rack-level or container-level power consumption goals within a datacenter. 
•Power/Performance Budgeting: Efficient means to cont rol the power consumed (and therefore the sustained 
performance delivered) within and across platforms.
The server and client usage models are addressed by RA PL interfaces, which expose multiple domains of power 
rationing within each processor socket. Generally, these RAPL domains may be viewed to include hierarchically:
•Package domain is the processor die. 
•Memory domain includes the directly-attached DRAM; an  additional power plane may constitute a separate 
domain. 
In order to manage the power consumed across multiple sockets via RAPL, individual limits must be programmed 
for each processor complex. Programming specific RA PL domain across multiple sockets is not supported.
15.10.1 RAPL Interfaces
RAPL interfaces consist of non-architectural MSRs. Each RAPL domain supports the following set of capabilities, 
some of which are optional as stated below.
•Power limit - MSR interfaces to specify power limit, time window; lock bit, clamp bit etc.
•Energy Status - Power metering interface providing energy consumption information.
•Perf Status (Optional) - Interface providing informatio n on the performance effects (regression) due to power 
limits. It is defined as a duration metric that measur es the power limit effect in the respective domain. The 
meaning of duration is domain specific.
•Power Info (Optional) - Interface providing informat ion on the range of parameters for a given domain, 
minimum power, maximum power etc.
•Policy (Optional) - 4-bit priority information that is a hint to hardware for dividing budget between sub-domains 
in a parent domain.
Each of the above capabilities requires specific units in order to describe them. Power is expressed in Watts, Time 
is expressed in Seconds, and Energy is  expressed in Joules. Scaling factors are supplied to each unit to make the 
information presented meaningful in a finite number of bi ts. Units for power, energy, and time are exposed in the 
read-only MSR_RAPL_POWER_UNIT MSR. Vol. 3B 15-49POWER AND THERMAL MANAGEMENT
MSR_RAPL_POWER_UNIT (Figure 15-35) provides th e following information across all RAPL domains:
•Power Units  (bits 3:0): Power related information (in Watts) is  based on the multiplier, 1/ 2^PU; where PU is

•Power Units  (bits 3:0): Power related information (in Watts) is  based on the multiplier, 1/ 2^PU; where PU is 
an unsigned integer represented by bits 3:0. Default value is 0011b, indicating power unit is in 1/8 Watts 
increment.
•Energy Status Units  (bits 12:8): Energy related information (in Joules) is based on the multiplier, 1/2^ESU; 
where ESU is an unsigned integer represented by bits 12:8. Default value is 10000b, indicating energy status unit is in 15.3 micro-Joules increment.
•Time Units  (bits 19:16): Time related information (in Seconds)  is based on the multiplier, 1/ 2^TU; where TU 
is an unsigned integer represented by bits 19:16. Defa ult value is 1010b, indicating time unit is in 976 micro-
seconds increment.
15.10.2 RAPL Domains an d Platform Specificity
The specific RAPL domains available in a platform vary  across product segments. Platforms targeting the client 
segment support the following RAPL domain hierarchy:
•Package
•Two power planes: PP0 and PP1 (PP1 may reflect to uncore devices)
Platforms targeting the server segment supp ort the following RAPL domain hierarchy:
•Package
•Power plane: PP0
•DRAM
Each level of the RAPL hierarchy provides a respective se t of RAPL interface MSRs. Table 15-12 lists the RAPL MSR 
interfaces available for each RAPL domain. The power limit MS R of each RAPL domain is located at offset 0 relative 
to an MSR base address which is non-architectural; see Ch apter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Vo lume 4. The energy status MSR of each domain is 
located at offset 1 relative to the MSR base address of respective domain.Figure 15-35.  MSR_RAPL_POWER_UNIT Register 63 0
Reserved13 34 78 12 15 1920
Time units
Energy status units
Power units 1615-50 Vol. 3BPOWER AND THERMAL MANAGEMENT
The presence of the optional MSR interfaces (the three ri ght-most columns of Table 15-12) may be model-specific. 
See Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 4, for details.
15.10.3 Package RAPL Domain
The MSR interfaces defined for the package RAPL domain are:
•MSR_PKG_POWER_LIMIT allows software to set power limits for the package and measurement attributes 
associated with each limit,
•MSR_PKG_ENERGY_STATUS reports me asured actual energy usage,
•MSR_PKG_POWER_INFO reports the package power range information for RAPL usage.
MSR_PKG_PERF_STATUS can report the performance impact of power limiting, but its availability may be model-
specific.
MSR_PKG_POWER_LIMIT allows a software agent to define power limitation for the package domain. Power limita-
tion is defined in terms of average power usage (Watts) over a time window specified in MSR_PKG_POWER_LIMIT. 
Two power limits can be specified, corresponding to time wi ndows of different sizes. Each power limit provides inde-
pendent clamping control that would permit the processor cores to go below OS-requested state to meet the power 
limits. A lock mechanism allow the software agent to enfo rce power limit settings. Once the lock bit is set, the 
power limit settings are static and un-modifiable until next RESET. 
The bit fields of MSR_PKG_POWER_LIMIT (Figure 15-36) are:
•Package Power Limit #1 (bits 14:0): Sets the average power usage limit of the package domain corre-
sponding to time window # 1. The unit of this field is  specified by the “Power Units” field of MSR_RAPL_POW-
ER_UNIT.Table 15-12.  RAPL MSR In terfaces and RAPL Domains
 Domain  Power Limit
(Offset 0) Energy Status (Offset 
1) Policy
(Offset 2) Perf Status
(Offset 3) Power Info
(Offset 4)
PKG MSR_PKG_POWER_
LIMITMSR_PKG_ENERGY_STA
TUSRESERVED MSR_PKG_PERF_STATUS MSR_PKG_POWER_I
NFO
DRAM MSR_DRAM_POWER
_LIMITMSR_DRAM_ENERGY_S
TATUSRESERVED MSR_DRAM_PERF_STATUS MSR_DRAM_POWER
_INFO
PP0 MSR_PP0_POWER_
LIMITMSR_PP0_ENERGY_STA
TUSMSR_PP0_POLICY MSR_PP0_ PERF_STATUS RESERVED
PP1 MSR_PP1_POWER_
LIMITMSR_PP1_ENERGY_STA
TUSMSR_PP1_POLICY RESERVED RESERVED
Figure 15-36.  MSR_PKG_POWER_LIMIT Register63
Enable limit #1
Pkg clamping limit #1
Enable limit #2
Pkg clamping limit #231 24 23 15 0
Pkg Power Limit #14847 32 62 56 55 49 46 14
L
O
CPkg Power Limit #21617
KTime window 
Power Limit #2Time window 
Power Limit #1Vol. 3B 15-51POWER AND THERMAL MANAGEMENT
•Enable Power Limit #1 (bit 15): 0 = disabled; 1 = enabled.
•Package Clamping Limitation #1 (bit 16): Allow going below OS-requested P/T state setting during time 
window specified by bits 23:17.
•Time Window for Power Limit #1 (bits 23:17): Indicates the time window for power limit #1 
Time limit = 2^Y * (1.0 + Z/4.0) * Time_Unit Here “Y” is the unsigned integer value represented. by bits 21:17, “Z” is an unsigned integer represented by 
bits 23:22. “Time_Unit” is specified by the “Time Units” field of MSR_RAPL_POWER_UNIT.
•Package Power Limit #2 (bits 46:32): Sets the average power usage limit of the package domain corre-
sponding to time window # 2. The unit of this field is  specified by the “Power Units” field of MSR_RAPL_POW-
ER_UNIT.
•Enable Power Limit #2 (bit 47): 0 = disabled; 1 = enabled.
•Package Clamping Limitation #2 (bit 48): Allow going below OS-requested P/T state setting during time 
•Time Window for Power Limit #2 (bits 55:49): Indicates the time window for power limit #2 
Time limit = 2^Y * (1.0 + Z/4.0) * Time_Unit 
Here “Y” is the unsigned integer value represented. by bits 53:49, “Z” is an unsigned integer represented by 
bits 55:54. “Time_Unit” is specified by the “Time Unit s” field of MSR_RAPL_POWER_UNIT. This field may have 
a hard-coded value in hardware and ignores values written by software.
•Lock (bit 63): If set, all write attempts to this MSR are ignored until next RESET.
MSR_PKG_ENERGY_STATUS is a read-only MSR. It reports the actual energy use for the package domain. This 
MSR is updated every ~1msec. It has a wraparound time of around 60 secs when power consumption is high, and 
may be longer otherwise.
•Total Energy Consumed (bits 31:0): The unsigned integer value represents the total amount of energy 
consumed since that last time this register is cleared. The unit of this field is sp ecified by the “Energy Status 
Units” field of MSR_RAPL_POWER_UNIT. 
MSR_PKG_POWER_INFO is a read-only MSR. It reports the package power range information for RAPL usage. This 
MSR provides maximum/minimum values (derived from electrical specification), thermal specification power of the 
package domain. It also provides the largest possible ti me window for software to program the RAPL interface.
•Thermal Spec Power (bits 14:0): The unsigned integer value is th e equivalent of thermal specification power 
of the package domain. The unit of th is field is specified by the “Power Units” field of MSR_RAPL_POWER_UNIT. Figure 15-37.  MSR_PKG_ENERGY_STATUS MSR
Figure 15-38.  MSR_PKG_POWER_INFO Register63 0
Reserved
Total Energy Consumed3132
Reserved
63 31 30 15 0
Thermal Spec Power 48 47 32 5453 46 14
Maximum Power16
Maximum Time window Minimum Power15-52 Vol. 3BPOWER AND THERMAL MANAGEMENT
•Minimum Power (bits 30:16): The unsigned integer value is the equivalent of minimum power derived from 
electrical spec of the package domain. The unit of this  field is specified by the “Power Units” field of 
MSR_RAPL_POWER_UNIT. 
•Maximum Power (bits 46:32): The unsigned integer value is the equivalent of maximum power derived from 
the electrical spec of the package do main. The unit of this field is specified by the “Power Units” field of 
•Maximum Time Window (bits 53:48): The unsigned integer value is the equivalent of largest acceptable 
value to program the time window of MSR_PKG_POWER_LIMIT. The unit of th is field is specified by the “Time 
MSR_PKG_PERF_STATUS is a read-only MS R. It reports the total time for which the package was throttled due to 
the RAPL power limits. Throttling in this context is define d as going below the OS-requested P-state or T-state. It 
has a wrap-around time of many hours. The availability of  this MSR is platform specific; see Chapter 2, “Model-
•Accumulated Package Throttled Time (bits 31:0): The unsigned integer value represents the cumulative 
time (since the last time this register is cleared) that the package has throttled. The unit of this field is specified 
by the “Time Units” field of MSR_RAPL_POWER_UNIT. 
15.10.4 PP0/PP1 RAPL Domains
The MSR interfaces defined for the PP0 and PP1 domains ar e identical in layout. Generally, PP0 refers to the 
processor cores. The availability of PP 1 RAPL domain interface is platform-spe cific. For a client platform, the PP1 
domain refers to the power plane of a specific device in  the uncore. For server platforms, the PP1 domain is not 
supported, but its PP0 domain supports the MSR_PP0_PERF_STATUS interface.
•MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT allow softwa re to set power limits for the respective power 
plane domain.

•MSR_PP0_ENERGY_STATUS/MSR_PP1_ENERGY_STATUS re port actual energy usage on a power plane.
•MSR_PP0_POLICY/MSR_PP1_POLICY allow software to adjust balance for respective power plane.
MSR_PP0_PERF_STATUS can report the performance impact of power limiting, but it is not available in client plat-
forms.Figure 15-39.  MSR_PKG_PERF_STATUS MSR
Figure 15-40.  MSR_PP0_POWER_LI MIT/MSR_PP1_POWE R_LIMIT Register63 0
Reserved
Accumulated pkg throttled time3132
Reserved
63
Enable limit 
Clamping limit30 24 23 15 0
Power Limit3132 14
L
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C1617
Power Limit Vol. 3B 15-53POWER AND THERMAL MANAGEMENT
MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT allow a soft ware agent to define power limitation for the 
respective power plane domain. A lock  mechanism in each power plane domain allows the software agent to 
enforce power limit settings independently. Once a lock bit is set, the power limit settings in that power plane are 
static and un-modifiable until next RESET. 
The bit fields of MSR_PP0_POWER_LIMIT/MSR_PP1_POWER_LIMIT (Figure 15-40) are:
•Power Limit (bits 14:0): Sets the average power usage limit of  the respective power plane domain. The unit 
of this field is specified by the “Pow er Units” field of MSR_RAPL_POWER_UNIT.
•Enable Power Limit (bit 15): 0 = disabled; 1 = enabled.
•Clamping Limitation (bit 16): Allow going below OS-requested P/T state setting during time window specified 
by bits 23:17.
•Time Window for Power Limit (bits 23:17): Indicates the length of ti me window over which the power limit 
#1 will be used by the processor. The numeric value en coded by bits 23:17 is represented by the product of 
2^Y *F; where F is a single-digit decimal floating-poi nt value between 1.0 and 1.3 with the fraction digit 
represented by bits 23:22, Y is an unsigned integer repres ented by bits 21:17. The unit of this field is specified 
by the “Time Units” field of MSR_RAPL_POWER_UNIT.
•Lock (bit 31): If set, all write attempts to the MSR and corresponding policy 
MSR_PP0_POLICY/MSR_PP1_POLICY are ignored until next RESET.
MSR_PP0_ENERGY_STATUS/MSR_PP1_ENERGY_STATUS are read -only MSRs. They report the actual energy use 
for the respective power plane domains. These MSRs are updated every ~1msec. 
consumed since the last time this register was cleared. Th e unit of this field is spec ified by the “Energy Status 
MSR_PP0_POLICY/MSR_PP1_POLICY provide balance power po licy control for each power plane by providing 
inputs to the power budgeting management algorithm. On  platforms that support PP0 (IA cores) and PP1 (uncore 
graphic device), the default values give priority to the non-IA power plane. These MSRs enable the PCU to balance 
power consumption between the IA cores and uncore graphic device. 
•Priority Level (bits 4:0): Priority level input to the PCU for respective power plane. PP0 covers the IA 
processor cores, PP1 covers the uncore graphic devi ce. The value 31 is considered highest priority.
MSR_PP0_PERF_STATUS is a read -only MSR. It reports the total time fo r which the PP0 domain was throttled due 
to the power limits. This MSR is supported only in server  platform. Throttling in this context is defined as going 
below the OS-requested P-state or T-state. Figure 15-41.  MSR_PP0_ENERGY_STATUS/MSR_PP1_ENERGY_STATUS MSR
Figure 15-42.  MSR_PP0_POLICY/MSR_PP1_POLICY Register63 0
Reserved
Reserved
63 4 0
Priority Level515-54 Vol. 3BPOWER AND THERMAL MANAGEMENT
•Accumulated PP0 Throttled Time (bits 31:0): The unsigned integer value represents the cumulative time 
(since the last time this register is cleared) that the PP 0 domain has throttled. The unit  of this field is specified 
15.10.5 DRAM RAPL Domain
The MSR interfaces defined for the DRAM domains are supp orted only in the server platform. The MSR interfaces 
are:
•MSR_DRAM_POWER_LIMIT allows software to set power limits for the DRAM domain and measurement attributes associated with each limit.
•MSR_DRAM_ENERGY_STATUS reports measured actual energy usage.
•MSR_DRAM_POWER_INFO reports the DRAM domain  power range information for RAPL usage.
•MSR_DRAM_PERF_STATUS can report the performance impact of power limiting.
MSR_DRAM_POWER_LIMIT allows a softwa re agent to define power limitation for the DRAM domain. Power limita-
tion is defined in terms of average power usage (Wa tts) over a time window sp ecified in MSR_DRAM_POW-
ER_LIMIT. A power limit can be specified along with a time  window. A lock mechanism allow the software agent to 
enforce power limit settings. Once the lock bit is set, the power limit settings are static and un-modifiable until next 
RESET. 
The bit fields of MSR_DRAM_POWER_LIMIT (Figure 15-44) are:
•DRAM Power Limit #1 (bits 14:0): Sets the average power usage lim it of the DRAM domain corresponding to 
time window # 1. The unit of this field is specifie d by the “Power Units” field of MSR_RAPL_POWER_UNIT.
•Time Window for Power Limit (bits 23:17): Indicates the length of time window over which the power limit 
will be used by the processor. The numeric value encode d by bits 23:17 is represented by the product of 2^Y 
*F; where F is a single-digit decimal floating-point valu e between 1.0 and 1.3 with the fraction digit represented 
by bits 23:22, Y is an unsigned integer represented by bi ts 21:17. The unit of this fiel d is specified by the “Time 
Units” field of MSR_RAPL_POWER_UNIT.
•Lock (bit 31): If set, all write attempts to  this MSR are ignored until next RESET.Figure 15-43.  MSR_PP0_PERF_STATUS MSR
Figure 15-44.  MSR_DRAM_POWER_LIMIT Register63 0
Reserved
Accumulated PP0 throttled time3132
Reserved
63
L
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Power Limit Vol. 3B 15-55POWER AND THERMAL MANAGEMENT
MSR_DRAM_ENERGY_STATUS is a read-only MSR. It reports the actual energy use for the DRAM domain. This MSR 
is updated every ~1msec. 
MSR_DRAM_POWER_INFO is a read-only MSR. It reports th e DRAM power range information for RAPL usage. This 
DRAM domain. It also provides the largest possible time window for software to program the RAPL interface.
of the DRAM domain. The unit of this field is specifie d by the “Power Units” field of MSR_RAPL_POWER_UNIT. 
electrical spec of the DRAM domain. The unit of this  field is specified by the “Power Units” field of 
•Maximum Power (bits 46:32): The unsigned intege r value is the equivalent of maximum power derived from 
the electrical spec of the DRAM domain. The unit of th is field is specified by the “Power Units” field of 
value to program the time window of  MSR_DRAM_POWER_LIMIT. The unit of this field is specified by the “Time 
MSR_DRAM_PERF_STATUS is a read-only MSR. It reports th e total time for which the package was throttled due to 
Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4.Figure 15-45.  MSR_DR AM_ENERGY_STATUS MSR
Figure 15-46.  MSR_DRAM_POWER_INFO Register
Figure 15-47.  MSR_DRAM_PERF_STATUS MSR63 0
Reserved
Reserved
63 31 30 15 0
Thermal Spec Power 4847 32 5453 46 14
Maximum Time window Minimum Power
63 0
Reserved
Accumulated DRAM throttled time3132
Reserved15-56 Vol. 3BPOWER AND THERMAL MANAGEMENT
time (since the last time this register is cleared) that  the DRAM domain has throttled. The unit of this field is 
specified by the “Time Units” field of MSR_RAPL_POWER_UNIT. Vol. 3B 16-1CHAPTER 16
This chapter describes the machine-check architecture and machine-check exception mechanism found in the 
Pentium 4, Intel Xeon, Intel Atom, and P6 family proce ssors. See Chapter 6, “Interrupt 18—Machine-Check Excep-

Reserved
Reserved
63 31 30 15 0
63 0
Reserved
tion (#MC),” for more information on machine-check exceptions. A brief description of the Pentium processor’s 
machine check capability is also given.
Additionally, a signaling mechanism for software to respon d to hardware corrected machine check error is covered.
16.1 MACHINE-CHECK ARCHITECTURE
The Pentium 4, Intel Xeon, Intel Atom, and P6 family pr ocessors implement a machine-check architecture that 
provides a mechanism for detecting and reporting hardwa re (machine) errors, such as: system bus errors, ECC 
errors, parity errors, cache errors, and TLB errors. It consis ts of a set of model-specific registers (MSRs) that are 
used to set up machine checking and additional banks of MSRs used for recording errors that are detected. 
The processor signals the detection of an uncorrected ma chine-check error by generating a machine-check excep-
tion (#MC), which is an abort class exception. The impl ementation of the machine-check architecture does not 
ordinarily permit the processor to be restarted reliably after generating a machine-check exception. However, the 
machine-check-exception handler can collect information about the machine-check error from the machine-check MSRs.
Starting with 45 nm Intel 64 processor on which CPUID reports DisplayFamily_DisplayModel as 06H_1AH; see the 
CPUID instruction in Chapter 3, “Instruc tion Set Reference, A-L,” in the Intel
Developer’s Manual, Volume 2A. The processor can report  information on corrected machine-check errors and 
deliver a programmable interrupt for software to respon d to MC errors, referred to as corrected machine-check 
error interrupt (CMCI). See Section 16.5 for details. 
Intel 64 processors supporting machine-check architecture  and CMCI may also support an additional enhance-
ment, namely, support for software recovery from cert ain uncorrected recoverable machine check errors. See 
Section 16.6 for details. 
16.2 COMPATIBILITY WITH PENTIUM PROCESSOR
The Pentium 4, Intel Xeon, Intel Atom, and P6 family processors support and extend the machine-check exception 
mechanism introduced in the Pentium processor. The Pentium processor reports the following machine-check 
errors:
•Data parity errors during read cycles.
•Unsuccessful completion of a bus cycle.
The above errors are reported using the P5_MC_TYPE an d P5_MC_ADDR MSRs (implementation specific for the 
Pentium processor). Use the RDMSR instruction to read these MSRs. See Chapter 2, “Model-Specific Registers 
(MSRs)‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, for the addresses.
The machine-check error reporting mechanism that Pentium pr ocessors use is similar to that used in Pentium 4, 
Intel Xeon, Intel Atom, and P6 family processors. When an  error is detected, it is recorded in P5_MC_TYPE and 
P5_MC_ADDR; the processor then generates a machine-check exception (#MC).
See Section 16.3.3, “Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture,” 
and Section 16.10.2, “Pentium Processor Machine-Check Exception Handli ng,” for information on compatibility 
between machine-check code written to run on the Pentiu m processors and code written to run on P6 family 
processors.16-2 Vol. 3BMACHINE-CHECK ARCHITECTURE
16.3 MACHINE-CHECK MSRS
Machine check MSRs in the Pentium 4, Intel Atom, Intel Xeon , and P6 family processors consist of a set of global 
control and status registers and several erro r-reporting register banks. See Figure 16-1.
Each error-reporting bank is associated with a specific ha rdware unit (or group of hardware units) in the processor. 
Use RDMSR and WRMSR to read and to write these registers. 
16.3.1 Machine-Check Global Control MSRs
The machine-check global control MSRs include the IA 32_MCG_CAP, IA32_MCG_STATUS, and optionally IA32_MC-
G_CTL and IA32_MCG_EXT_CTL. See Chapter 2, “Model-Specific Registers (MSRs),” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volu me 4, for the addresses of these registers. 
16.3.1.1  IA32_MCG_CAP MSR
The IA32_MCG_CAP MSR is a read-only register that provid es information about the machine-check architecture of 
the processor. Figure 16-2 shows the layout of the register.Figure 16-1.  Machine-Check MSRs0
63 063
IA32_MCG_CAP MSR
IA32_MCG_STATUS MSRError-Reporting Bank Registers
0
63 063
IA32_MC i_CTL MSR
IA32_MC i_STATUS MSR
0
63 063
IA32_MC i_ADDR MSR
IA32_MC i_MISC MSRGlobal Control MSRs
(One Set for Each Hardware Unit)
0 63
IA32_MCG_CTL MSR
0 63
IA32_MC i_CTL2 MSR0 63
IA32_MCG_EXT_CTL MSRVol. 3B 16-3MACHINE-CHECK ARCHITECTURE
Where:
•Count field, bits 7:0  — Indicates the number of hardware unit error-reporting banks available in a particular 
•MCG_CTL_P (control MSR present) flag, bit 8  — Indicates that the processor implements the IA32_MC-
G_CTL MSR when set; this register is absent when clear.
•MCG_EXT_P (extended MSRs present) flag, bit 9 — Indicates that the processor implements the extended 
machine-check state registers found starting at MSR address 180H; these registers are absent when clear.
•MCG_CMCI_P (Corrected MC error counting/s ignaling extension pres ent) flag, bit 10 — Indicates 
(when set) that extended state and associated MSRs ne cessary to support the reporting of an interrupt on a 
corrected MC error event and/or count th reshold of corrected MC errors, is present. When this bit is set, it does 
not imply this feature is supported across all banks. So ftware should check the availability of the necessary 
logic on a bank by bank basis when using this signalin g capability (i.e., bit 30 settable in individual IA32_M-
Ci_CTL2 register). 
•MCG_TES_P (threshold-based error status present) flag, bit 11 — Indicates (when set) that bits 56:53 
of the IA32_MCi_STATUS MSR are part of the architectura l space. Bits 56:55 are reserved, and bits 54:53 are 
used to report threshold-based error status. Note that when MCG_TES_P is not set, bits 56:53 of the IA32_M-
Ci_STATUS MSR are model-specific.
•MCG_EXT_CNT, bits 23:16  — Indicates the number of extended machine-check state registers present. This 
field is meaningful only when the MCG_EXT_P flag is set.
•MCG_SER_P (software error recovery support present) flag, bit 24 — Indicates (when set) that the 
processor supports software error recovery (see Section 16.6), and IA32_MCi_STATUS MSR bits 56:55 are 
used to report the signaling of uncorrected recovera ble errors and whether software must take recovery 
actions for uncorrected errors. Note that when MCG_TES_ P is not set, bits 56:53 of the IA32_MCi_STATUS MSR 
are model-specific. If MCG_TES_P is set but MC G_SER_P is not set, bits 56:55 are reserved.
•MCG_EMC_P (Enhanced Machine Ch eck Capability) flag, bit 25 — Indicates (when set) that the 
processor supports enhanced machine check capabilities for firmware first signaling.
•MCG_ELOG_P (extended erro r logging) flag, bit 26  — Indicates (when set) that the processor allows 
platform firmware to be invoked when an error is detect ed so that it may provide additional platform specific 
information in an ACPI format “Generic Error Data Entr y” that augments the data included in machine check 
bank registers.
For additional information about exte nded error logging interface, see 
https://cdrdv2.intel.com/v1/dl/getContent/671064 .
•MCG_LMCE_P (local machine check exception) flag, bit 27  — Indicates (when set) that the following 
interfaces are present:Figure 16-2.  IA32_MCG_CAP RegisterMCG_TES_P[11]MCG_EXT_CNT[23:16]63 9
MCG_CMCI_P[10]0 87
Count
MCG_EXT_P[9]1516 2324
MCG_CTL_P[8]MCG_SER_P[24]25
MCG_ELOG_P[26]2726
MCG_LMCE_P[27]
MCG_EMC_P[25]16-4 Vol. 3BMACHINE-CHECK ARCHITECTURE
— an extended state LMCE_S (located in bit 3 of IA32_MCG_STATUS), and
— the IA32_MCG_EXT_CTL MSR, necessary to su pport Local Machine Check Exception (LMCE). 
A non-zero MCG_LMCE_P indicates that, when LMCE is en abled as described in Section 16.3.1.5, some machine 
check errors may be delivered to only a single logical processor.
The effect of writing to the IA32_MCG_CAP MSR is undefined. 
16.3.1.2  IA32_MCG_STATUS MSR
The IA32_MCG_STATUS MSR describes the current state of  the processor after a machine-check exception has 
occurred (see Figure 16-3).
Where:
•RIPV (restart IP valid) flag, bit 0 — Indicates (when set) that program execution can be restarted reliably 
at the instruction pointed to by the instruction pointer pushed on the stack when the machine-check exception is generated. When clear, the program cannot be re liably restarted at the pushed instruction pointer.
•EIPV (error IP valid) flag, bit 1 — Indicates (when set) that the instruction pointed to by the instruction 
pointer pushed onto the stack when the machine-check ex ception is generated is directly associated with the 
error. When this flag is cleared, the instructio n pointed to may not be associated with the error.
•MCIP (machine check in  progress) flag, bit 2 — Indicates (when set) that a machine-check exception was

Where:
•MCIP (machine check in  progress) flag, bit 2 — Indicates (when set) that a machine-check exception was 
generated. Software can set or clear this flag. The o ccurrence of a second Machine-Check Event while MCIP is 
set will cause the processor to enter a shutdown state. For information on processor behavior in the shutdown 
state, please refer to the description in Chapter 6, “I nterrupt and Exception Handling”: “Interrupt 8—Double 
Fault Exception (#DF)”.
•LMCE_S (local machine check exception signaled), bit 3 — Indicates (when set) that a local machine-
check exception was generated. This indicates that the current machine-check event was delivered to only this 
Bits 63:04 in the IA32_MCG_STATUS MSR are reserved. An attempt to write to the IA32_MCG_STATUS MSR’s 
reserved bits with any value other than 0 results in #GP.
16.3.1.3  IA32_MCG_CTL MSR
The IA32_MCG_CTL MSR is present if the capability  flag MCG_CTL_P is set in the IA32_MCG_CAP MSR. 
IA32_MCG_CTL controls the reporting of machine-check except ions. If present, writing 1s to this register enables 
machine-check features and writing all 0s disables machin e-check features. All other values are undefined and/or 
16.3.1.4  IA32_MCG_EXT_CTL MSR
The IA32_MCG_EXT_CTL MSR is present if the capabilit y flag MCG_LMCE_P is set in the IA32_MCG_CAP MSR.Figure 16-3.  IA32_MCG_STATUS RegisterEIPV—Error IP valid flagMCIP—Machine check in progress flag63 0
Reserved123
E
I
PVM
C
I
PR
I
PV
RIPV—Restart IP valid flagLMCE_S—Local machine check exception signaledVol. 3B 16-5MACHINE-CHECK ARCHITECTURE
IA32_MCG_EXT_CTL.LMCE_EN (bit 0) allows the processor to  signal some MCEs to only a single logical processor 
If MCG_LMCE_P is not set in IA32_MCG_CAP, or platfo rm software has not enabled LMCE by setting IA32_FEA-
TURE_CONTROL.LMCE_ENABLED (bit 20), any attempt to write or read IA32_MCG_EXT_CTL will result in #GP. 
The IA32_MCG_EXT_CTL MSR is cleared on RESET.Figure 16-4 shows the layout of the IA32_MCG_EXT_CTL register
where
•LMCE_EN (local machine check exception enable) flag, bit 0 - System software sets this to allow 
hardware to signal some MCEs to only a single logical processor. System software can set LMCE_EN only if the 
platform software has configured IA32_FEATURE_CONTROL as described in Section 16.3.1.5. 
16.3.1.5  Enabling Local Machine Check
The intended usage of LMCE requires proper configuratio n by both platform software and system software. Plat-
form software can turn LMCE on by setting bit 20 (LMCE_ENABLED) in IA32_FEATURE_CONTROL MSR (MSR 
address 3AH). 
System software must ensure that both IA32_FE ATURE_CONTROL.Lock (bit 0)and IA32_FEATURE_CON-
TROL.LMCE_ENABLED (bit 20) are set before attempting to set IA32_MC G_EXT_CTL.LMCE_EN (bit 0). When 
system software has enabled LMCE, then hardware will dete rmine if a particular error can be delivered only to a 
single logical processor. Software should make no assumptions about the type of error that hardware can choose 
to deliver as LMCE. The severity and override rules stay  the same as described in Table 16-8 to determine the 
recovery actions. 
16.3.2 Error-Reporting Register Banks
Each error-reporting register bank can contain th e IA32_MCi_CTL, IA32_MCi_STATUS, IA32_MCi_ADDR, and 
IA32_MCi_MISC MSRs. The number of reporting banks is indicated by bits [7:0] of IA32_MCG_CAP MSR (address 
0179H). The first error-reporting register (I A32_MC0_CTL) always starts at address 400H. 
See Chapter 2, “Model-Specific Registers (MSRs),” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 4, for addresses of the error-reporting registers in the Pentium 4, Intel Atom, and Intel Xeon 
processors; and for addresses of the error- reporting registers P6 family processors. 
16.3.2.1  IA32_MC i_CTL MSRs
The IA32_MC i_CTL MSR controls signaling of #MC for errors prod uced by a particular hardware unit (or group of 
hardware units). Each of the 64 flags (EE j) represents a potential error. Setting an EE j flag enables signaling #MC 
of the associated error and clearing it disables signaling of  the error. Error logging happens regardless of the setting 
of these bits. The processor drops writes to bits that are not implemented. Figure 16-5 shows the bit fields of 
IA32_MC i_CTL.Figure 16-4.  IA32_MCG_EXT_CTL Register63 0
Reserved1
LMCE_EN - system software control to enable/disable LMCE16-6 Vol. 3BMACHINE-CHECK ARCHITECTURE
NOTE
For P6 family processors, processors based on Intel Core microarchitecture (excluding those on 
which CPUID reports DisplayFamily_DisplayModel  as 06H_1AH and onward): the operating system 
or executive software must not modify the co ntents of the IA32_MC0_CTL MSR. This MSR is 
internally aliased to the EBL_CR_POWERON MSR and controls platform-specific error handling 
features. System specific firmware (the BIOS) is re sponsible for the appropriate initialization of the 
IA32_MC0_CTL MSR. P6 family proce ssors only allow the writing of all 1s or all 0s to the IA32_M-
Ci_CTL MSR.
16.3.2.2  IA32_MCi_STATUS MSRS
Each IA32_MCi_STATUS MSR contains information related to a machine-check error if its VAL (valid) flag is set (see 
Figure 16-6). Software is responsible for clearing IA32_MCi _STATUS MSRs by explicitly writing 0s to them; writing 
1s to them causes a general-protection exception.
NOTE
Figure 16-6 depicts the IA32_MCi_STATUS MSR when IA32_MCG_CAP[24] = 1, IA32_MC-G_CAP[11] = 1 and IA32_MCG_CAP[10] = 1. When IA32_MCG_CAP[24] = 0 and IA32_MC-
G_CAP[11] = 1, bits 56:55 is reserved and bits 54:53 for threshold-based error reporting. When 
IA32_MCG_CAP[11] = 0, bits 56:53 are part of the “O ther Information” field. The use of bits 54:53 
for threshold-based error reporting began with Inte l Core Duo processors, and is currently used for 
cache memory. See Section 16.4, “Enhanced Cache Error reporting,” for more information. When IA32_MCG_CAP[10] = 0, bits 52:38 are part of the “O ther Information” field. The use of bits 52:38 
for corrected MC error count is introduced with Intel 64 processor on which CPUID reports Display-
Family_DisplayModel as 06H_1AH. 
Where:
•MCA (machine-check ar chitecture) error code field, bits 15:0 — Specifies the machine-check archi-
tecture-defined error code for the machine-check erro r condition detected. The machine-check architecture-
defined error codes are guaranteed to be the same for all IA-32 processors that implement the machine-check 
architecture. See Section 16.9, “Interpreting the MCA Error Codes,” and Chapter 17, “Interpreting Machine 
Check Error Codes‚” for information on machine-check error codes. 
•Model-specific error code field, bits 31:16  — Specifies the model-specific error code that uniquely 
identifies the machine-check error condition detected. The model-specific error codes may differ among IA-32 
processors for the same machine-check error condition. See Chapter 17, “Interpreting Machine Check Error 
Codes‚” for information on model-specific error codes.
•Reserved, Error Status, and Other Information fields, bits 56:32 — 
•If IA32_MCG_CAP.MCG_EMC_P[bit 25] is 0, bits 37:32  contain “Other Information” that is implemen-
tation-specific and is not part of the machine-check architecture.
•If IA32_MCG_CAP.MCG_EMC_P is 1, “O ther Information” is in bits 36:32. If bit 37 is 0, system firmware 
has not changed the contents of IA32_MCi_STATUS. If bit 37 is 1, system firm ware may have edited the 
contents of IA32_MCi_STATUS. 
•If IA32_MCG_CAP.MCG_CMCI_P[bit 10] is 0, bits 52:38 also contain “Other Information” (in the same 
sense as bits 37:32).Figure 16-5.  IA32_MC i_CTL RegisterEEj—Error reporting enable flag63 0123
E
E
01E
E
0
2E
E
0
0EE
61E
E
62E
E
6362 61. . . . .
         (where  j is 00 through 63)Vol. 3B 16-7MACHINE-CHECK ARCHITECTURE
•If IA32_MCG_CAP[10] is 1, bits 52:38 are architectura l (not model-specific). In this case, bits 52:38 
reports the value of a 15 bit counter that increments each time a corrected error is observed by the MCA 
recording bank. This count value will continue to increment until cleared by software. The most 
significant bit, 52, is a sticky count overflow bit. 
•If IA32_MCG_CAP[11] is 0, bits 56:53 also cont ain “Other Information” (in the same sense).
•If IA32_MCG_CAP[11] is 1, bits 56:53 are architectura l (not model-specific). In this case, bits 56:53 
have the following functionality:
•If IA32_MCG_CAP[24] is 0, bits 56:55 are reserved.
•If IA32_MCG_CAP[24] is 1, bits 56:55 are defined as follows: 
•S (Signaling) flag, bit 56 - Signals the reporting of  UCR errors in this MC bank. See Section 16.6.2 
for additional details. 
•AR (Action Required) flag, bit 55 - Indicates (whe n set) that MCA error code specific recovery 
action must be performed by system software at  the time this error was signaled. See Section 
16.6.2 for additional details.
•If the UC bit (Figure 16-6) is 1, bits 54:53 are undefined. 
•If the UC bit (Figure 16-6) is 0, bits 54:53 indicate the status of the hardware structure that

•If the UC bit (Figure 16-6) is 0, bits 54:53 indicate the status of the hardware structure that 
reported the threshold-based error. See Table 16-1.Figure 16-6.  IA32_MC i_STATUS Register
Table 16-1.  Bits 54:53 in IA32_MCi_STATUS MSRs when IA32_MCG_CAP[11] = 1 and UC = 0
Bits 54:53 Meaning
00 No tracking  - No hardware status tracking is provid ed for the structure reporting this event. 
01 Green  - Status tracking is provided for the structure posting the event; the current status is green (below threshold). 
For more information, see Section 16. 4, “Enhanced Cache Error reporting.”
10 Yellow - Status tracking is provided for the structure posting th e event; the current status is  yellow (above threshold). 
11 Reserved63
Threshold-based error status (54:53)**
AR — Recovery action required for UCR error (55)***
S — Signaling an uncorrected recoverable (UCR) error (56)***
PCC — Processor context corrupted (57)37 32 31 16 0
P
CA E
ADDRV — MCi_ADDR register valid (58)
MISCV — MCi_MISC register valid (59)EN — Error reporting enabled (60)UC — Uncorrected error (61)OVER — Error overflow (62)VAL — MCi_STATUS register valid (63)CMCA Error CodeU S
R Other MSCOD Model54 53 38 62 61 60 59 58 57 56 55 52 15
V
A
LO
V
E
RCNSpecific Error Code  InfoCorrected Error
Count
** When IA32_MCG_CAP[11] (MCG_TES_P) is not  set, these bits are model-specific 
 (part of “Other Information”).
*** When IA32_MCG_CAP[11] or IA32_MCG_CAP[24] ar e not set, these bits are reserved, or
 model-specific (part of “Other Information”).36
* When IA32_MCG_CAP[25] (MCG_EMC_P) is set, bit 37 is not part of “O ther Information”.Firmware updated error status indicator (37)*16-8 Vol. 3BMACHINE-CHECK ARCHITECTURE
•PCC (processor context corrupt) flag, bit 57  — Indicates (when set) that the state of the processor might 
have been corrupted by the error condition detected and that reliable restarting of the processor may not be 
possible. When clear, this flag indicates that the error did not affect the processor’s state, and software may be 
able to restart. When system software supports reco very, consult Section 16.10.4,  “Machine-Check Software 
Handler Guidelines for Error Recovery,” for additional rules that apply.
•ADDRV (IA32_MC i_ADDR register valid) flag, bit 58 — Indicates (when set) that the IA32_MCi_ADDR 
register contains the address where the error occurred (see Section 16.3.2.3, “IA32_MCi_ADDR MSRs”). When 
clear, this flag indicates that the IA32_MCi_ADDR regist er is either not implemented or does not contain the 
address where the error occurred. Do not read these re gisters if they are not implemented in the processor.
•MISCV (IA32_MC i_MISC register valid) flag, bit 59 — Indicates (when set) that the IA32_MC i_MISC 
register contains additional information regarding the e rror. When clear, this flag indicates that the IA32_M-
Ci_MISC register is either not implemented or does not contain additional information regarding the error. Do 
not read these registers if they ar e not implemented in the processor.
•EN (error enabled) flag, bit 60 — Indicates (when set) that the error was enabled by the associated EEj bit 
of the IA32_MC i_CTL register.
•UC (error uncorrected) flag, bit 61 — Indicates (when set) that the processor did not or was not able to 
correct the error condition. When clear, this flag indicates that the processor was able to correct the error 
•OVER (machine check overflow) flag, bit 62 — Indicates (when set) that a machine-check error occurred 
while the results of a previous error were still in the error-reporting register bank (that is, the VAL bit was 
already set in the IA32_MC i_STATUS register). The processor sets the OVER flag and software is responsible for 
clearing it. In general, enabled errors are written over disabled errors, and uncorrected errors are written over 
corrected errors. Uncorrected errors are not writte n over previous valid uncorrected errors. When 
MCG_CMCI_P is set, corrected errors may not set the OVER flag. Software ca n rely on corrected error count in 
IA32_MCi_Status[52:38] to determine if any additional corrected errors may have occurred. For more infor-
mation, see Section 16.3.2.2.1, “Overwrite Rules for Machine Check Overflow.”
•VAL (IA32_MC i_STATUS register valid) flag, bit 63 — Indicates (when set) that the information within the 
IA32_MCi_STATUS register is valid. When this flag is set,  the processor follows the rules given for the OVER flag 
in the IA32_MCi_STATUS register when overwriting previo usly valid entries. The processor sets the VAL flag 
and software is responsible for clearing it.
16.3.2.2.1  Overwrite Rule s for Machine Check Overflow
Table 16-2 shows the overwrite rules for how to treat a second event if the MC bank already contains a valid log 
from an earlier event – that is, what to do if the valid bit for an MC bank already is set to 1. When more than one structure posts events in a given bank, these rules specif y whether a new event will overwrite a previous posting or 
not. These rules define a priority for uncorrected (hig hest priority), yellow, and green/unmonitored (lowest 
priority) status.
In Table 16-2, the values in the two le ft-most columns are IA32_MCi_STATUS[54:53]. 
If a second event overwrites a previously posted event, th e information (as guarded by in dividual valid bits) in the 
MCi bank is entirely from the second event. Similarly, if a first event is retained, all of the information previously 
posted for that event is retained. In general, when the logged error or the recent error is a corrected error, the 
OVER bit (MCi_Status[62]) may be set to indicate an overflow. When MCG_CMCI_P is set in IA32_MCG_CAP, 
system software should consult IA32_MCi_STATUS[52:38] to  determine if additional corrected errors may have Table 16-2.  Overwrite Rules for Enabled Errors
First Event Second Event UC bit Color MCA Info
00/green 00/green 0 00/green either00/green yellow 0 ye llow second error
yellow 00/green 0 ye llow first error 
yellow yellow 0 yellow either00/green/yellow UC 1 undefined secondUC 00/green/yellow 1 undefined first Vol. 3B 16-9MACHINE-CHECK ARCHITECTURE
occurred. Software may re-read IA32_MCi_STATUS, IA32_MCi_ADDR, and IA32_MCi_MISC appropriately to 
ensure data collected represent the last error logged.
After software polls a posting and clears the register, the va lid bit is no longer set and therefore the meaning of the 
rest of the bits, including the yellow/green/00 status field in bits 54:53, is undefined. The yellow/green indication 
will only be posted for events associated with monitored structures – otherwise the unmonitored (00) code will be 
posted in IA32_MC i_STATUS[54:53].
16.3.2.3  IA32_MCi_ADDR MSRs
The IA32_MC i_ADDR MSR contains the address of the code or da ta memory location that produced the machine-
check error if the ADDRV flag in the IA32_MC i_STATUS register is set (see Section 16-7, “IA32_MCi_ADDR MSR”). 
The IA32_MCi_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_M-
Ci_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a 
general protection exception. 
The address returned is an offset into a segment, linear address, or physical address. This depends on the error 
encountered. When these registers are implemented, these registers can be cleared by explicitly writing 0s to 
these registers. Writing 1s to these registers will cause a general-protection exception. See Figure 16-7.
16.3.2.4  IA32_MC i_MISC MSRs
The IA32_MC i_MISC MSR contains additional information describin g the machine-check error if the MISCV flag in 
the IA32_MC i_STATUS register is set. The IA32_MCi_MISC_MSR is either not implemented or does not contain 
additional information if the MISCV flag in the IA32_MCi_STATUS register is clear. 
When not implemented in the processor, all reads and writes  to this MSR will cause a general protection exception. 
When implemented in a processor, these registers can be clea red by explicitly writing all 0s to them; writing 1s to 
them causes a general-protection exception to be generate d. This register is not implemented in any of the error-
reporting register banks for the P6 or Intel Atom family processors. 
If both MISCV and IA32_MCG_CAP[24] are set, the IA32_M Ci_MISC_MSR is defined according to Figure 16-8 to 
support software recovery of uncorrected errors (see Section 16.6).Figure 16-7.  IA32_MC i_ADDR MSRAddress63 0
Reserved3536
Address*63 0Processor Without Support For Intel 64 Architecture
Processor With Support for Intel 64 Architecture
* Useful bits in this field depend on the address methodology in use when the 
the register state is saved.16-10 Vol. 3BMACHINE-CHECK ARCHITECTURE
•Recoverable Address LSB (bits 5:0): The lowest valid recove rable address bit. Indicates the position of the least 
significant bit (LSB) of the recoverable error address. Fo r example, if the processor logs bits [43:9] of the

significant bit (LSB) of the recoverable error address. Fo r example, if the processor logs bits [43:9] of the 
address, the LSB sub-field in IA32_MCi_MISC is 01001b (9 decimal). For this example, bits [8:0] of the 
recoverable error address in IA32_MCi_ADDR should be ignored. 
•Address Mode (bits 8:6): Address mode for the address logged in IA32_MCi_ADDR. The supported address 
modes are given in Table 16-3.
•Model Specific Information (bits 63:9): Not architecturally defined.
16.3.2.4.2  IOMCA
Logging and Signaling of errors from PCI Express domain is governed by PCI Express Advanced Error Reporting 
(AER) architecture. PCI Express architec ture divides errors in two categories: Uncorrectable errors and Correctable 
errors. Uncorrectable errors can further be classified as Fatal or Non-Fatal. Uncorrected IO errors are signaled to 
the system software either as AER Message Signaled Interru pt (MSI) or via platform specific mechanisms such as 
NMI. Generally, the signaling mechanism is controlled by BIOS and/or platform firmware. Certain processors 
support an error handling mode, called IOMCA mode, wher e Uncorrected PCI Express errors are signaled in the 
form of machine check exception and logged in machine check banks. 
When a processor is in this mode, Uncorrected PCI Expre ss errors are logged in the MCACOD field of the IA32_M-
Ci_STATUS register as Generic I/O error. The corresponding MCA error code is defined in Table 15-8. IA32_M-
Ci_Status [15:0] Simple Error Code Encoding. Machin e check logging complements and does not replace AER 
logging that occurs inside the PCI Express hierarchy. Th e PCI Express Root Complex and Endpoints continue to log 
the error in accordance with PCI Express AER mechanism.  In IOMCA mode, MCi_MISC register in the bank that 
logged IOMCA can optionally contain information that link the Machine Check logs with the AER logs or proprietary 
logs. In such a scenario, the machine check handler can utilize  the contents of MCi_MISC to locate the next level of 
error logs corresponding to the same error. Specifically , if MCi_Status.MISCV is 1 and MCACOD is 0x0E0B, MCi_-
MISC contains the PCI Express address of the Root Comple x device containing the AER Logs. Software can consult 
the header type and class code registers in the Root Comp lex device's PCIe Configuration space to determine what 
type of device it is. This Root Complex device can eith er be a PCI Express Root Port, PCI Express Root Complex 
Event Collector or a proprietary device. Figure 16-8.  UCR Support in IA32_MCi_MISC Register
Table 16-3.  Address Mode in IA32_MCi_MISC[8:6] 
IA32_MCi_MISC[8:6] Encoding Definition
000 Segment Offset001 Linear Address010 Physical Address011 Memory Address
100 to 110 Reserved
111 GenericAddress Mode63 0
Model Specific Information65
Recoverable Address LSB89Vol. 3B 16-11MACHINE-CHECK ARCHITECTURE
Errors that originate from PCI Express or Legacy Endpoints are logged in the corresponding Root Port in addition to 
the generating device. If MISCV=1 and MCi_MISC contains the address of the Root Port or a Root Complex Event 
collector, software can parse the AER logs to learn more about the error. 
If MISCV=1 and MCi_MISC points to a de vice that is neither a Root Complex Event Collector not a Root Port, soft-
ware must consult the Vendor ID/Device ID and use device specific knowledge to locate  and interpret the error log 
registers. In some cases, the Root Complex device conf iguration space may not be accessible to the software and 
both the Vendor and Device ID read as 0xFFFF.
•The format of MCi_MISC for IOMCA errors is shown in Table 16-4.
Refer to PCI Express Specification 3.0 for definition of PC I Express Requestor ID and AER architecture. Refer to PCI 
Firmware Specification 3.0 for an explanation of PC I Ex-press Segment number and how software can access 
configuration space of a PCI Ex-press device given the segment number and Requestor ID.
16.3.2.5  IA32_MC i_CTL2 MSRs
The IA32_MC i_CTL2 MSR provides the programming interface to us e corrected MC error signaling capability that is 
indicated by IA32_MCG_CAP[10] = 1. Softwa re must check for the presence of IA32_MC i_CTL2 on a per-bank 
basis. 
When IA32_MCG_CAP[10] = 1, the IA32_MCi_CTL2 MSR for ea ch bank exists, i.e., reads and writes to these MSR 
are supported. However, signaling interface for correct ed MC errors may not be supported in all banks. 
The layout of IA32_MC i_CTL2 is shown in Figure 16-9.
•Corrected error count threshold, bits 14:0 — Software must initialize this field. The value is compared with 
the corrected error count field in IA32_MCi_STATUS, bits 38 through 52. An overflow event is signaled to the 
CMCI LVT entry (see Table 11-1) in the APIC when the count value equals the threshold value. The new LVT 
entry in the APIC is at 02F0H offset from the APIC_BAS E. If CMCI interface is not supported for a particular 
bank (but IA32_MCG_CAP[10] = 1), this field will always read 0.
•CMCI_EN (Corrected error interrupt enable/disable/indicator), bits 30  — Software sets this bit to 
enable the generation of corrected machine-check error in terrupt (CMCI). If CMCI interface is not supported for 
a particular bank (but IA32_MCG_CAP[10] = 1), this bit is  writeable but will always return 0 for that bank. This 
bit also indicates CMCI is supported or not supported in  the corresponding bank. See Section 16.5 for details of 
software detection of CMCI facility.Table 16-4.  Address Mode in IA32_MCi_MISC[8:6] 
63:40 39:32 31:16 15:9 8:6 5:0
RSVD PCI Express Segment 
numberPCI Express 
Requestor IDRSVD ADDR MODE1
NOTES:
1. Not Applicable if ADDRV=0.RECOV ADDR LSB1
Figure 16-9.  IA32_MCi_CTL2 RegisterCMCI_EN—Enable/disable CMCI63 15
Reserved29
Corrected error count threshold0 14 31 30
Reserved16-12 Vol. 3BMACHINE-CHECK ARCHITECTURE
Some microarchitectural sub-systems that are the source of  corrected MC errors may be shared by more than one 
logical processors. Consequently, the facilities for report ing MC errors and controlling mechanisms may be shared 
by more than one logical processors. For example, the IA32_MC i_CTL2 MSR is shared between logical processors 
sharing a processor core. Software is responsible to program IA32_MC i_CTL2 MSR in a consistent manner with 
CMCI delivery and usage. 
After processor reset, IA32_MC i_CTL2 MSRs are zeroed.
16.3.2.6  IA32_MCG Extended Machine Check State MSRs
The Pentium 4 and Intel Xeon processors implement a va riable number of extended machine-check state MSRs. 
The MCG_EXT_P flag in the IA32_MCG_CAP MSR indicates the presence of these extended registers, and the 
MCG_EXT_CNT field indicates the number of these registers actually implemented. See Section 16.3.1.1, 
“IA32_MCG_CAP MSR.” Also see Table 16-5.
In processors with support for Intel 64 architecture, 64-bit machine check state MSRs are aliased to the legacy 
MSRs. In addition, there may be registers beyond IA32_MCG _MISC. These may include up  to five reserved MSRs 
(IA32_MCG_RESERVED[1:5]) and save-state MSRs for registers introduced in 64-bit mode. See Table 16-6. Table 16-5.  Extended Machine Check State MSRs in Processors Without Support for Intel® 64 Architecture
MSR Address Description
IA32_MCG_EAX 180H Contains state of the EAX regist er at the time of the machine-check error.
IA32_MCG_EBX 181H Contains state of the EBX regist er at the time of th e machine-check error.
IA32_MCG_ECX 182H Contains state of the ECX regist er at the time of th e machine-check error.
IA32_MCG_EDX 183H Contains state of the EDX regist er at the time of the machine-check error.
IA32_MCG_ESI 184H Contains state of the ESI register at the time of the machine-check error.IA32_MCG_EDI 185H Contains state of the EDI regist er at the time of the machine-check error.
IA32_MCG_EBP 186H Contains state of the EBP regist er at the time of th e machine-check error.
IA32_MCG_ESP 187H Contains state of the ESP regist er at the time of th e machine-check error.
IA32_MCG_EFLAGS 188H Contains state of the EFLAGS re gister at the time of the machine-check error.
IA32_MCG_EIP 189H Contains state of the EIP register at the time of the machine-check error.IA32_MCG_MISC 18AH When set, indicates that a page assist or page fault occurred during DS normal 
Table 16-6.  Extended Machine Chec k State MSRs In Processors With Support for Intel® 64 Architecture
IA32_MCG_RAX 180H Contains state of the RAX regist er at the time of th e machine-check error.
IA32_MCG_RBX 181H Contains state of the RBX regist er at the time of th e machine-check error.
IA32_MCG_RCX 182H Contains state of the RCX register at the time of the machine-check error.IA32_MCG_RDX 183H Contains state of the RDX regist er at the time of the machine-check error.
IA32_MCG_RSI 184H Contains state of the RSI regist er at the time of th e machine-check error.
IA32_MCG_RDI 185H Contains state of the RDI regist er at the time of the machine-check error.
IA32_MCG_RBP 186H Contains state of the RBP regist er at the time of th e machine-check error.
IA32_MCG_RSP 187H Contains state of the RSP regist er at the time of the machine-check error.

IA32_MCG_RFLAGS 188H Contains state of the RFLAGS re gister at the time of the machine-check error.
IA32_MCG_RIP 189H Contains state of the RIP register at the time of the machine-check error.IA32_MCG_MISC 18AH When set, indicates that a page assist or page fault occurred during DS normal 
operation.Vol. 3B 16-13MACHINE-CHECK ARCHITECTURE
When a machine-check error is detected on a Pentium 4 or  Intel Xeon processor, the processor saves the state of 
the general-purpose registers, the R/EFLAGS register, an d the R/EIP in these extended machine-check state MSRs. 
This information can be used by a debugger to analyze the error.
These registers are read/write to zero registers. This me ans software can read them; but if software writes to 
them, only all zeros is allowed. If software attempts to wr ite a non-zero value into one of these registers, a general-
protection (#GP) exception is generated. These register s are cleared on a hardware reset (power-up or RESET), 
but maintain their contents following a soft reset (INIT reset).
16.3.3 Mapping of the Pentium Processor Machine-Check Erro rs to the Machine-Check 
The Pentium processor reports machine-check errors us ing two registers: P5_MC_TYPE and P5_MC_ADDR. The 
Pentium 4, Intel Xeon, Intel Atom, and P6 family processors map these registers to the IA32_MC i_STATUS and 
IA32_MC i_ADDR in the error-reportin g register bank. This bank reports on the same type of external bus errors 
reported in P5_MC_TYPE and P5_MC_ADDR. 
The information in these registers can then be accessed in two ways:
•By reading the IA32_MC i_STATUS and IA32_MC i_ADDR registers as part of a general machine-check exception 
handler written for Pentium 4, Intel Atom and P6 family processors.
•By reading the P5_MC_TYPE and P5_MC_ADDR registers using the RDMSR instruction.
The second capability permits a machine-check exception handler written to run on a Pentium processor to be run 
on a Pentium 4, Intel Xeon, Intel Atom, or P6 family proce ssor. There is a limitation in that information returned by 
the Pentium 4, Intel Xeon, Intel Atom, and P6 family processors is encoded differently than information returned 
by the Pentium processor. To run a Pentium processor machine-check exception handler on a Pentium 4, Intel 
Xeon, Intel Atom, or P6 family processor; the handle r must be written to interpret P5_MC_TYPE encodings 
correctly.
16.4 ENHANCED CACHE ERROR REPORTING
Starting with Intel Core Duo processors, cache error re porting was enhanced. In earlier Intel processors, cache 
status was based on the number of correction events that occurred in a cache. In the new paradigm, called 
“threshold-based error status”, cache status is based on the number of lines (ECC blocks) in a cache that incur 
repeated corrections. The threshold is ch osen by Intel, based on various factors. If a processor supports threshold-
based error status, it sets IA32_MCG_CAP[11] (MCG_TES_P) to 1; if not, to 0. 
A processor that supports enhanced cache error reporting contains hardware that tracks the operating status of 
certain caches and provides an indicator of their “health”. The hardware reports a “green” status when the number 
of lines that incur repeated corrections is at or below a pre-defined threshold, and a “yellow” status when the IA32_MCG_
RSERVED[1:5]18BH-
18FHThese registers, if present, are reserved.
IA32_MCG_R8 190H Contains state of the R8 regist er at the time of the machine-check error.
IA32_MCG_R9 191H Contains state of the R9 regist er at the time of the machine-check error.
IA32_MCG_R10 192H Contains state of the R10 register at the time of the machine-check error.IA32_MCG_R11 193H Contains state of the R11 register at the time of the machine-check error.IA32_MCG_R12 194H Contains state of the R12 register at the time of the machine-check error.IA32_MCG_R13 195H Contains state of the R13 register at the time of the machine-check error.IA32_MCG_R14 196H Contains state of the R14 register at the time of the machine-check error.IA32_MCG_R15 197H Contains state of the R15 register at the time of the machine-check error.Table 16-6.  Extended Machin e Check State MSRs In Proces sors With Support for Intel® 64 Architecture (Contd.)
MSR Address Description16-14 Vol. 3BMACHINE-CHECK ARCHITECTURE
number of affected lines exceeds the threshold. Yellow stat us means that the cache reporting the event is operating 
correctly, but you should schedule the sy stem for servicing within a few weeks.
Intel recommends that you rely on this mechanism for st ructures supported by threshold-base error reporting. 
The CPU/system/platform response to a yellow event should be less severe than its response to an uncorrected 
error. An uncorrected error means that a serious error ha s actually occurred, whereas the yellow condition is a 
warning that the number of affected lines has exceeded the th reshold but is not, in itself, a serious event: the error 
was corrected and system state was not compromised. 
The green/yellow status indicator is not a foolproof early wa rning for an uncorrected error resulting from the failure 
of two bits in the same ECC block. Such a failure ca n occur and cause an uncorrected error before the yellow 
threshold is reached. However, the chance of an unco rrected error increases as the number of affected lines 
increases. 
16.5 CORRECTED MACHINE CHECK ERROR INTERRUPT
Corrected machine-check error interrupt (CMCI) is an ar chitectural enhancement to the machine-check architec-
ture. It provides capabilities beyond th ose of threshold-based error reporting (Section 16.4). With threshold-based 
error reporting, software is limited to use periodic pol ling to query the status of hardware corrected MC errors. 
CMCI provides a signaling mechanism to deliver a local interrupt based on threshold values that software can 
program using the IA32_MCi_CTL2 MSRs. 
CMCI is disabled by default. System software is required  to enable CMCI for each IA32_MCi bank that support the 
reporting of hardware corrected errors if IA32_MCG_CAP[10] = 1.
System software use IA32_MCi_CTL2 MSR to enable/disab le the CMCI capability for each bank and program 
threshold values into IA32_MCi_CTL2 MSR.  CMCI is not affected by the CR4.MCE bit, and it is not affected by the 
IA32_MCi_CTL MSRs.
To detect the existence of thresholding for a given bank, soft ware writes only bits 14:0 with the threshold value. If 
the bits persist, then thresholding is available (and CMCI is  available). If the bits are all 0's, then no thresholding 
exists. To detect that CMCI signaling exists, software writ es a 1 to bit 30 of the MCi_CTL2 register. Upon subsequent 
read, if bit 30 = 0, no CMCI is available for this bank and no corrected or UCNA errors will be reported on this bank. 
If bit 30 = 1, then CMCI is available and enabled.
16.5.1 CMCI Local APIC Interface
The operation of CMCI is depicted in Figure 16-10. 
CMCI interrupt delivery is configured by  writing to the LVT CMCI register entr y in the local APIC register space at 
default address of APIC_BASE + 2F0H. A CMCI interrupt can be delivered to more than one logical processors if 
multiple logical processors are affected by the associated MC errors. For example, if a corrected bit error in a cache 
shared by two logical processors caused a CMCI, the interru pt will be delivered to both logical processors sharing Figure 16-10.  CMCI BehaviorError threshold63 0
MCi_CTL23031
Error count53 0Software write 1 to enable
Count overflow threshold -> CMCI LVT in local APIC29 14
37
MCi_STATUS38 52?=
APIC_BASE + 2F0HVol. 3B 16-15MACHINE-CHECK ARCHITECTURE
that microarchitectural sub-system. Similarly, package leve l errors may cause CMCI to be delivered to all logical 
processors within the package. However, system  level errors will not be handled by CMCI.
See Section 11.5.1, “Local Vector Table,” for details regarding the LVT CMCI register.
16.5.2 System Software Recommendation for Ma naging CMCI and Machine Check Resources
System software must enable and manage CMCI, set up in terrupt handlers to service CMCI interrupts delivered to 
affected logical processors, program CMCI LVT entry, an d query machine check banks that are shared by more 
than one logical processors. 
This section describes techniques system software can implement to manage CMCI initialization, service CMCI 
interrupts in a efficient manner to minimize contentions to access shared MSR resources.
16.5.2.1  CMCI Initialization
Although a CMCI interrupt may be delivered to more than  one logical processors depending on the nature of the 
corrected MC error, only one instance of the interrupt service routine needs to perform the necessary service and 
make queries to the machine-check banks. The following steps describes a technique that limits the amount of 
work the system has to do in response to a CMCI.
•To provide maximum flexibility, system software should define per-thread data structure for each logical 
processor to allow equal-opportunity and efficient response to interrupt delivery. Specifically, the per-thread

processor to allow equal-opportunity and efficient response to interrupt delivery. Specifically, the per-thread 
data structure should include a set of per-bank fields to track which machine check bank it needs to access in 
response to a delivered CMCI interru pt. The number of banks that needs to be tracked is determined by 
IA32_MCG_CAP[7:0].
•Initialization of per-thread data structure. The initializa tion of per-thread data structure must be done serially 
on each logical processor in the system. The sequencing order to start the per-thread initialization between different logical processor is arbitrary. But it must ob serve the following specific detail to satisfy the shared 
nature of specific MSR resources:
a. Each thread initializes its data structure to indi cate that it does not own any MC bank registers.
b. Each thread examines IA32_MCi_CTL2[30] indicator for each bank to determine if another thread has 
already claimed ownership of that bank.
•If IA32_MCi_CTL2[30] had been set by anot her thread. This thread can not own bank i and should 
proceed to step b. and examine the next machine ch eck bank until all of the machine check banks are 
exhausted. 
•If IA32_MCi_CTL2[30] = 0, proceed to step c.
c. Check whether writing a 1 into IA32_MCi_CTL2[30] can return with 1 on a subsequent read to determine 
this bank can support CMCI. 
•If IA32_MCi_CTL2[30] = 0, this bank does no t support CMCI. This thread can not own bank i and should 
exhausted.
•If IA32_MCi_CTL2[30] = 1, modify the per-thread da ta structure to indicate this thread claims 
ownership to the MC bank; proceed to initialize the error threshold count (bits 15:0) of that bank as 
described in Chapter 16, “CMCI Threshold Management”.  Then proceed to step b. and examine the next 
machine check bank until all of th e machine check banks are exhausted.
•After the thread has examined all of the machine check bank s, it sees if it owns any MC banks to service CMCI. 
If any bank has been claimed by this thread:
— Ensure that the CMCI interrupt handler has been se t up as described in Chapter 16, “CMCI Interrupt 
Handler”.
— Initialize the CMCI LVT entry, as described in  Section 16.5.1, “CMCI Local APIC Interface.”
— Log and clear all of IA32_MCi_Statu s registers for the banks that this  thread owns. This will allow new 
errors to be logged.16-16 Vol. 3BMACHINE-CHECK ARCHITECTURE
16.5.2.2  CMCI Threshold Management
The Corrected MC error threshold field, IA32_MCi_CTL2[14:0], is architecturally defined. Specifically, all these bits 
are writable by software, but different processor implem entations may choose to implement less than 15 bits as 
threshold for the overflow comparison  with IA32_MCi_STATUS[52:38]. The following describes techniques that 
software can manage CMCI threshold to be compatible with changes in implementation characteristics:
•Software can set the initial threshold value to 1 by writ ing 1 to IA32_MCi_CTL2[14:0]. This will cause overflow 
condition on every corrected MC e rror and generates a CMCI interrupt.
•To increase the threshold and reduce the frequency of CMCI servicing:
a. Find the maximum threshold value a given processor implementation supports. The steps are:
•Write 7FFFH to IA32_MCi_CTL2[14:0],
•Read back IA32_MCi_CTL2[14:0]; these 15 bits (14: 0) contain the maximum threshold supported by 
b. Increase the threshold to a value below the maximum value discovered using step a.
16.5.2.3  CMCI Interrupt Handler
The following describes techniques system software may consider to implement a CMCI service routine:
•The service routine examines its private per-thread data structure to check which set of MC banks it has 
ownership. If the thread does not have ownership of a given MC bank, proceed to the next MC bank. Ownership 
is determined at initialization time which is described in Section 16.5.2.1.
If the thread had claimed ownership to an MC bank, this  technique will allow each logical processors to handle 
corrected MC errors independently an d requires no synchronization to access shared MSR resources. Consult 
Example 16-5 for guidelines on logging when processing CMCI.
16.6 RECOVERY OF UNCORRECTE D RECOVERABLE (UCR) ERRORS 
Recovery of uncorrected recoverable machine check errors is an enhancement in machine-check architecture. The 
first processor that supports this feature is 45 nm Inte l 64 processor on which CPUID reports DisplayFamily_Dis-
playModel as 06H_2EH; see the CPUID in struction in Chapter 3, “Instruction Set Reference, A-L‚” in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume  2A. This allows system software to perform recovery 
action on a certain class of uncorrected errors and continue execution.
16.6.1 Detection of Software Error Recovery Support
Software must use bit 24 of IA32_MCG_CAP (MCG_SER_P) to detect the presence of software error recovery 
support (see Figure 16-2). When IA32_MCG_CAP[24] is set, this indicates that the processor supports software 
error recovery. When this bit is clear, this indicates that  there is no support for error recovery from the processor 
and the primary responsibility of the machine check hand ler is logging the machine check error information and 
shutting down the system. 
The new class of architectural MCA errors from which syst em software can attempt recovery is called Uncorrected 
Recoverable (UCR) Errors. UCR errors are uncorrected errors  that have been detected and signaled but have not 
corrupted the processor context. For certain UCR errors, this means that once system software has performed a 
certain recovery action, it is possible to continue executio n on this processor. UCR error reporting provides an error 
containment mechanism for data poisoning. The machine ch eck handler will use the error log information from the 
error reporting registers to analyze and implement specific error recovery actions for UCR errors. 
16.6.2 UCR Error Reporting and Logging
IA32_MCi_STATUS MSR is used for reporting UCR errors an d existing corrected or uncorrected errors. The defini-
tions of IA32_MCi_STATUS, including bit fields to identify  UCR errors, is shown in Fi gure 16-6. UCR errors can be Vol. 3B 16-17MACHINE-CHECK ARCHITECTURE
signaled through either the corrected machine check in terrupt (CMCI) or machine check exception (MCE) path 
depending on the type of the UCR error. 
When IA32_MCG_CAP[24] is set, a UCR error is indicate d by the following bit settings in the IA32_MCi_STATUS 
register: 
•Valid (bit 63) = 1
•UC (bit 61) = 1
•PCC (bit 57) = 0
Additional information from the IA32_MCi_MISC and the IA 32_MCi_ADDR registers for the UCR error are available 
when the ADDRV and the MISCV flags in the IA32_MCi_STATU S register are set (see Section 16.3.2.4). The MCA 
error code field of the IA32_MCi_STATUS register indicate s the type of UCR error. System software can interpret 
the MCA error code field to analyze and identify th e necessary recovery action for the given UCR error.
In addition, the IA32_MCi_STATUS register bit fields, bits  56:55, are defined (see Figure 16-6) to provide addi-
tional information to help system software to properly identify the necessary recovery action for the UCR error:
•S (Signaling) flag, bit 56 - Indicates (when set) that a machine check exception was generated for the UCR 
error reported in this MC bank and system software need s to check the AR flag and the MCA error code fields in 
the IA32_MCi_STATUS register to identify the necessary re covery action for this error. When the S flag in the 
IA32_MCi_STATUS register is clear, this UCR error was not signaled via a machine check exception and instead 
was reported as a corrected machine check (CMC). System software is not required to take any recovery action 
when the S flag in the IA32_MCi_STATUS register is clear. 
•AR (Action Required) flag, bit 55 - Indicates (when set) th at MCA error code specific recovery action must be 
performed by system software at the time this error was signaled. This recovery action must be completed successfully before any additional work is scheduled fo r this processor. When the RIPV flag in the IA32_MC-
G_STATUS is clear, an alternative execution stream n eeds to be provided; when the MCA error code specific 
recovery specific recovery action cannot be successfu lly completed, system software must shut down the 
system. When the AR flag in the IA32_MCi_STATUS register  is clear, system software may still take MCA error 
code specific recovery action but this is optional; system software can safely resume program execution at the 
instruction pointer saved on the stack from the machin e check exception when the RIPV flag in the IA32_MC-
G_STATUS register is set. 
Both the S and the AR flags in the IA32_MCi_STATUS register  are defined to be sticky bits, which mean that once 
set, the processor does not clear them. Only software an d good power-on reset can clear the S and the AR-flags.

set, the processor does not clear them. Only software an d good power-on reset can clear the S and the AR-flags. 
Both the S and the AR flags are only set when the pr ocessor reports the UCR errors (MCG_CAP[24] is set).
16.6.3 UCR Error Classification
With the S and AR flag encoding in the IA32_MCi_STATUS register, UCR errors can be classified as:
•Uncorrected no action required (UCNA) - is a UCR error that is not signaled via a machine check exception and, 
instead, is reported to system software as a corrected  machine check error. UCNA errors indicate that some 
data in the system is corrupted, but the data has not been consumed and the processor state is valid and you may continue execution on this processor. UCNA errors require no action from system software to continue 
execution. A UCNA error is indicated with UC=1, P CC=0, S=0 and AR=0 in the IA32_MCi_STATUS register.
•Software recoverable action optional (SRAO) - a UCR error is signaled either via a machine check exception or 
CMCI. System software recovery action is optional and not required to continue execution from this machine 
check exception. SRAO errors indicate that some data in the system is corrupt, but the data has not been 
consumed and the processor state is valid. SRAO errors provide the additional error information for system 
software to perform a recovery action. An SRAO error when signaled as a machine check is indicated with 
UC=1, PCC=0, S=1, EN=1 and AR=0 in the IA32_MC i_STATUS register. In cases when SRAO is signaled via 
CMCI the error signature is indicated via UC=1, PCC=0, S=0. Recovery actions for SRAO errors are MCA error 
code specific. The MISCV and the ADDRV flags in the IA32_MC i_STATUS register are set when the additional 
error information is available from the IA32_MC i_MISC and the IA32_MC i_ADDR registers. System software 
needs to inspect the MCA error code fields in the IA32_MC i_STATUS register to identify the specific recovery 
action for a given SRAO error. If MISCV and ADDRV are not set, it is recommended that no system software 
error recovery be performed however, system software can resume execution.
•Software recoverable action required (SRAR) - a UCR error that requires system software to take a recovery 
action on this processor before scheduling another stream of execution on this processor. SRAR errors indicate 16-18 Vol. 3BMACHINE-CHECK ARCHITECTURE
that the error was detected and raised at the point of the consumption in the execution flow. An SRAR error is 
indicated with UC=1, PCC=0, S=1, EN=1 and AR=1 in  the IA32_MCi_STATUS register. Recovery actions are 
MCA error code specific. The MISCV and the ADDRV flag s in the IA32_MCi_STATUS register are set when the 
additional error information is available from the IA 32_MCi_MISC and the IA32_MCi_ADDR registers. System 
software needs to inspect the MCA error code fields in the IA32_MCi_STATUS register to identify the specific 
recovery action for a given SRAR error. If MISCV an d ADDRV are not set, it is recommended that system 
software shutdown the system.
Table 16-7 summarizes UCR, corrected, and uncorrected errors. 
16.6.4 UCR Error Overwrite Rules
In general, the overwrite rules are as follows:
•UCR errors will overwrite corrected errors. 
•Uncorrected (PCC=1) errors overwrite UCR (PCC=0) errors.   
•UCR errors are not written over previous UCR errors. 
•Corrected errors do not write over previous UCR errors. 
Regardless of whether the 1st error is retained or the 2nd e rror is overwritten over the 1st error, the OVER flag in 
the IA32_MCi_STATUS register will be se t to indicate an overflow condition. As the S flag and AR flag in the 
IA32_MCi_STATUS register are defined to be sticky flags,  a second event cannot clear these 2 flags once set, 
however the MC bank information may be filled in for th e 2nd error. The table below shows the overwrite rules and 
how to treat a second error if the first event is already lo gged in a MC bank along with the resulting bit setting of 
the UC, PCC, and AR flags in the IA32_MCi_STATUS regist er. As UCNA and SRA0 errors do not require recovery 
action from system software to continue program executio n, a system reset by system software is not required 
unless the AR flag or PCC flag is set for the UC R overflow case (OVER=1,  VAL=1, UC=1, PCC=0). 
Table 16-8 lists overwrite rules for uncorrected errors , corrected errors, and uncorrected recoverable errors. Table 16-7.  MC Error Classifications
Type of Error1
NOTES:
1. SRAR, SRAO and UCNA errors are supported by the proc essor only when IA32_MCG_CAP[24] (MCG_SER_P) is set. UC EN PCC S AR Signaling Software Action Example
Uncorrected Error (UC) 1 1 1 x x MCE If EN=1, reset the system, else log 
and OK to keep th e system running.
SRAR 1 1 0 1 1 MCE For known MCACOD, take specific 
recovery action;
For unknown MCACOD, must 
bugcheck.
If OVER=1, reset system, else take 
specific recovery action.Cache to processor load 
error.
SRAO 1 x2
2. EN=1, S=1 when signaled via MCE.  EN=x, S=0 when signaled via CMC.0x20 MCE/CMC For known MCACOD, take specific 
For unknown MCACOD, OK to keep 
the system running.Patrol scrub and explicit 
writeback poison errors.
UCNA 1 x 0 0 0 CMC Log the error and Ok to keep the 
system running.Poison detection error.
Corrected Error (CE) 0 x x x x CMC Log the error and no corrective 
action required.ECC in caches and 
memory.
Table 16-8.  Overwrite Rules for UC, CE, and UCR Errors
First Event Second Event UC PCC S AR MCA Bank Reset System
CE UCR 1 0 0 if UCNA, else 1 1 if SRAR, else 0 second yes, if AR=1UCR CE 1 0 0 if UCNA, else 1 1 if SRAR, else 0 first  yes, if AR=1Vol. 3B 16-19MACHINE-CHECK ARCHITECTURE
16.7 MACHINE-CHECK AVAILABILITY
The machine-check architecture and machine-check except ion (#MC) are model-specific features. Software can 
execute the CPUID instruction to determine whether a pr ocessor implements these features. Following the execu-
tion of the CPUID instruction, the settings of the MCA flag (bit 14) and MCE flag (bit 7) in EDX indicate whether the 
processor implements the machine-check architecture and machine-check exception.
16.8 MACHINE-CHECK INITIALIZATION
To use the processors machine-check architecture, software must initialize the processor to activate the machine-check exception and the error-reporting mechanism. 
Example 16-1 gives pseudocode for perfor ming this initialization. This pseudocode checks for the existence of the 
machine-check architecture and exception; it then enables machine-check exception and the error-reporting 
register banks. The pseudocode shown is compatible with  the Pentium 4, Intel Xeon, Intel Atom, P6 family, and 
Pentium processors. 
Following power up or power cycling, IA32_MC i_STATUS registers are not guaranteed to have valid data until after 
they are initially cleared to zero by software (as sh own in the initialization pseudocode in Example 16-1). 
Example 16-1.  Machine-Check Initialization Pseudocode
Check CPUID Feature Flags for MCE and MCA support
IF CPU supports MCE
THEN
IF CPU supports MCA
THEN
IF (IA32_MCG_CAP.MCG_CTL_P = 1)(* IA32_MCG_CTL register is present *)
THEN
IA32_MCG_CTL 
← FFFFFFFFFFFFFFFFH;
(* enables all MCA features *)
FI
IF (IA32_MCG_CAP.MCG_LMCE_P = 1 and IA32_FEATURE_CONTR OL.LOCK = 1 and IA32_FEATURE_CONTROL.LMCE_ENABLED = 1)
(* IA32_MCG_EXT_CTL register is presen t and platform has enabled LMCE to permit system software to use LMCE *)
THEN
IA32_MCG_EXT_CTL ← IA32_MCG_EXT_CTL | 01H;
(* System software enables LMCE capability for hardwa re to signal MCE to a single logical processor*)
FIUCNA UCNA 1 0 0 0 first no
UCNA SRAO 1 0 1 0 first noUCNA SRAR 1 0 1 1 first yesSRAO UCNA 1 0 1 0 first noSRAO SRAO 1 0 1 0 first noSRAO SRAR 1 0 1 1 first yesSRAR UCNA 1 0 1 1 first yesSRAR SRAO 1 0 1 1 first yesSRAR SRAR 1 0 1 1 first yesUCR UC 1 1 undefined undefined second yesUC UCR 1 1 undefined undefined first yes Table 16-8.  Overwrite Rule s for UC, CE, and UCR Errors
First Event Second Event UC PCC S AR MCA Bank Reset System16-20 Vol. 3BMACHINE-CHECK ARCHITECTURE
(* Determine number of error-reporting banks supported *)
COUNT ← IA32_MCG_CAP.Count;
MAX_BANK_NUMBER ← COUNT - 1;
IF (Processor Family is 6H and Proces sor EXTMODEL:MODEL is less than 1AH)
THEN
(* Enable logging of all errors except for MC0_CTL register *)
FOR error-reporting banks (1 through MAX_BANK_NUMBER)
DO
IA32_MCi_CTL ← 0FFFFFFFFFFFFFFFFH;
OD
ELSE
(* Enable logging of all errors including MC0_CTL register *)
FOR error-reporting banks (0 through MAX_BANK_NUMBER)DO
IA32_MCi_CTL 
← 0FFFFFFFFFFFFFFFFH;
OD
FI
(* BIOS clears all errors only on power-on reset *)
IF (BIOS detects Power-on reset)
THEN 
IA32_MCi_STATUS 
← 0;
OD
ELSE
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
(Optional for BIOS and OS) Log valid errors
(OS only) IA32_MCi_STATUS ← 0;
OD
FI
FI
Setup the Machine Check Exception (#MC) handler for vector 18 in IDT
Set the MCE bit (bit 6) in CR4 register to enable Machine-Check Exceptions
FI
16.9 INTERPRETING THE MCA ERROR CODES
When the processor detects a machine-check error condition,  it writes a 16-bit error code to the MCA error code

THEN
DO
OD
ELSE
OD
FI
THEN 
← 0;
OD
ELSE
DO
OD
FI
FI
FI
When the processor detects a machine-check error condition,  it writes a 16-bit error code to the MCA error code 
field of one of the IA32_MC i_STATUS registers and sets the VAL (valid) flag in that register. The processor may also 
write a 16-bit model-specific error code in the IA32_MC i_STATUS register depending on the implementation of the 
machine-check architecture of the processor.
The MCA error codes are architecturally defined for Inte l 64 and IA-32 processors. To determine the cause of a 
machine-check exception, the machine-check exceptio n handler must read the VAL flag for each IA32_M-
Ci_STATUS register. If the flag is set, the machine check-ex ception handler must then read the MCA error code field 
of the register. It is the encoding of the MCA error code fi eld [15:0] that determines the type of error being reported 
and not the register bank reporting it.
There are two types of MCA error codes: simp le error codes and compound error codes. 
16.9.1 Simple Error Codes
Table 16-9 shows the simple error codes. These unique codes indicate global error information.Vol. 3B 16-21MACHINE-CHECK ARCHITECTURE
16.9.2 Compound Error Codes
Compound error codes describe errors related to the TLBs, memory, caches, bus and interconnect logic, and 
internal timer. A set of sub-fields is common to all of compound errors. These sub-fields describe the type of 
access, level in the cache hierarchy, and type of reques t. Table 16-10 shows the general form of the compound 
error codes. 
The “Interpretation” column in the table indicates the name of a compound error. The name is constructed by 
substituting mnemonics for the sub-field names given within curly braces. For example, the error code 
ICACHEL1_RD_ERR is constructed from the form: 
{TT}CACHE{LL}_{RRRR}_ERR,
where {TT} is replaced by I, {LL} is repl aced by L1, and {RRRR} is replaced by RD.
For more information on the “Form” and “Interpretatio n” columns, see Section 16.9.2.1, “Correction Report 
Filtering (F) Bit,” through Section 16.9. 2.5, “Bus and Interconnect Errors.”
16.9.2.1  Correction Report Filtering (F) Bit 
Starting with Intel Core Duo processors, bit 12 in the “Form” column in Table 16-10 is used to indicate that a partic-
ular posting to a log may be the last posting for corrections in that line/entry, at least for some time:Table 16-9.  IA32_MCi_Status [15:0] Simple Error Code Encoding 
Error Code Binary Encoding Meaning
No Error 0000 0000 0000 0000 No error has been reported to this bank of error-reporting 
Unclassified 0000 0000 0000 0001 This error has not been classified into the MCA error classes.Microcode ROM Parity Error 0000 0000 0000 0010 Parity error in internal microcode ROMExternal Error 0000 0000 0000 0011 The BINIT# from another processor caused this processor to 
enter machine check.
1
FRC Error 0000 0000 0000 0100 FRC (functional redundancy check) main/secondary error.
Internal Parity Error 0000 0000 0000 0101 Internal parity error.SMM Handler Code Access 
Violation0000 0000 0000 0110 An attempt was made by the SMM Handler to execute 
outside the ranges specified by SMRR.
Internal Timer Error 0000 0100 0000 0000 Internal timer error.I/O Error 0000 1110 0000 1011 generic I/O error.Internal Unclassified 0000 01xx xxxx xxxx Internal unclassified errors. 
2
NOTES:
1. BINIT# assertion will cause a machine check exception if the processor (or any processor on the same external bus) has BINIT#  
observation enabled during power-on configuration (hardware strapping) and if machine check exceptions are enabled (by setting CR4.MCE = 1).
2. At least one X must equal one. Internal unclassified errors have not been classified. 
Table 16-10.  IA32_MCi_Status [15:0] Compound Error Code Encoding 
Type Form Interpretation
Generic Cache Hierarchy 000F 0000 0000 11LL Generic cache hierarchy errorTLB Errors 000F 0000 0001 TTLL {TT}TLB{LL}_ERRMemory Controller Errors 000F 0000 1MMM CCCC {MMM}_CHANNEL{CCCC}_ERRCache Hierarchy Errors 000F 0001 RRRR TTLL {TT}CACHE{LL}_{RRRR}_ERRExtended Memory Errors 000F 0010 1MMM CCCC {MMM}_CHANNEL{CCCC}_ERRBus and Interconnect Errors 000F 1PPT RRRR IILL BUS{LL}_{PP}_{RRRR}_{II}_{T}_ERR16-22 Vol. 3BMACHINE-CHECK ARCHITECTURE
•0 in bit 12 indicates “normal” filtering (ori ginal P6/Pentium4/Atom/Xeon processor meaning).
•1 in bit 12 indicates “corrected” filtering (filtering is acti vated for the line/entry in the posting). Filtering means 
that some or all of the subsequent corrections to this entry (in this structure) will not be posted. The enhanced error reporting introduced with the Intel Core Duo processors is based on tracking the lines affected by 
repeated corrections (see Section 16.4, “Enhanced Cache Error reporting”). This ca pability is indicated by 
IA32_MCG_CAP[11]. Only the first few correction even ts for a line are posted; subsequent redundant 
correction events to the same line are not posted. Uncorrected events are always posted. 
The behavior of error filtering after crossing the yellow th reshold is model-specific. Filtering has meaning only for 
corrected errors (UC=0 in IA 32_MCi_STATUS MSR). System software must ignore filtering bit (12) for uncorrected 
errors.
16.9.2.2  Transaction Type (TT) Sub-Field
The 2-bit TT sub-field (Table 16-11) indicates the type of transaction (data, instruction, or generic). The sub-field 
applies to the TLB, cache, and interconnect error conditio ns. Note that interconnect error conditions are primarily 
associated with P6 family and Pentium processors, which utilize an external APIC bus separate from the system 
bus. The generic type is reported when the processor cannot determine the transaction type.
16.9.2.3  Level (LL) Sub-Field
The 2-bit LL sub-field (see Table 16-12) indicates the leve l in the memory hierarchy wh ere the error occurred (level 
0, level 1, level 2, or generic). The LL sub-field also ap plies to the TLB, cache, and interconnect error conditions. 
The Pentium 4, Intel Xeon, Intel Atom, and P6 family proc essors support two levels in the cache hierarchy and one 
level in the TLBs. Again, the generic type is reported when the processor cannot determine the hierarchy level.
16.9.2.4  Request (RRRR) Sub-Field
The 4-bit RRRR sub-field (see Table 16-13) indicates the type  of action associated with the error. Actions include 
read and write operations, prefetches, cache evictions, and snoops. Generic e rror is returned when the type of 
error cannot be determined. Generic read and generic writ e are returned when the processor cannot determine the 
type of instruction or data request that caused the error.  Eviction and snoop requests apply only to the caches. All 
of the other requests apply to TLBs, caches, and interconnects.Table 16-11.  Encoding for TT (Transaction Type) Sub-Field
Transaction Type Mnemonic Binary Encoding
Instruction I 00Data D 01Generic G 10
Table 16-12.  Level Encoding for LL (Memory Hierarchy Level) Sub-Field 
Hierarchy Level Mnemonic Binary Encoding
Level 0 L0 00Level 1 L1 01Level 2 L2 10Generic LG 11Vol. 3B 16-23MACHINE-CHECK ARCHITECTURE
16.9.2.5  Bus and Interconnect Errors
The bus and interconnect errors are defined with the 2- bit PP (participation), 1-bit T (time-out), and 2-bit II 
(memory or I/O) sub-fields, in addition to the LL and RRRR sub-fields (see Table 16-14). The bus error conditions 
are implementation dependent and related to the type of  bus implemented by the processor. Likewise, the inter-
connect error conditions are predicated on a specific im plementation-dependent interc onnect model that describes 
the connections between the different levels of the storag e hierarchy. The type of bus is implementation depen-
dent, and as such is not specified in this document. A bus or interconnect transaction consists of a request involving 
an address and a response.Table 16-13.  Encoding of Request (RRRR) Sub-Field 
Request Type Mnemonic Binary Encoding
Generic Error ERR 0000Generic Read RD 0001Generic Write WR 0010Data Read DRD 0011Data Write DWR 0100Instruction Fetch IRD 0101Prefetch PREFETCH 0110Eviction EVICT 0111Snoop SNOOP 1000
Table 16-14.  Encodings of PP, T, and II Sub-Fields 
Sub-Field Transaction Mnemonic Binary EncodingPP (Participation) Local processor* originated request SRC 00
Local processor* responded to request RES 01Local processor* observed error as third party OBS 10Generic 11
T (Time-out) Request timed out TIMEOUT 1
Request did not ti me out NOTIMEOUT 0
II (Memory or I/O) Memory Access M 00
Reserved 01I/O IO 10Other transaction 11
NOTE:
* Local processor differentiates the processor reporting the error from other system components (including the APIC, other proce s-
sors, etc.).16-24 Vol. 3BMACHINE-CHECK ARCHITECTURE
16.9.2.6  Memory Controller and Extended Memory Errors
The memory controller errors are defined with the 3-bit MMM (memory transaction type), and 4-bit CCCC (channel) 
sub-fields. The encodings for MMM and CCCC are defined in Table 16-15. Extended Memory errors use the same 
encodings and are used to report errors in memory used as a cache.
Note that the CCCC channel number may be enumerated from zero separately by each memory controller on a

NOTE:
Note that the CCCC channel number may be enumerated from zero separately by each memory controller on a 
system. On a multi-socket system, or a system with multiple  memory controllers per socket, it is necessary to also 
consider which machine check bank logged the error. S ee Chapter 17 for details on specific implementations.
16.9.3 Architecturally Defined UCR Errors 
Software recoverable compound error code are defined in this section.
16.9.3.1  Architectura lly Defined SRAO Errors
The following two SRAO errors are architecturally defined. 
•UCR Errors detected by memory controller scrubbing; and
•UCR Errors detected during L3 cache (L3) explicit writebacks.
The MCA error code encodings for these two architectura lly-defined UCR errors corresponds to sub-classes of 
compound MCA error codes (see Table 16-10). Their values  and compound encoding format are given in Table 
16-16. Table 16-15.  Encodings of MMM and CCCC Sub-Fields 
Sub-Field Transaction Mnemonic Binary Encoding
MMM Generic undefined request GEN 000
Memory read error RD 001Memory write error WR 010Address/Command Error AC 011Memory Scrubbing Error MS 100Reserved 101-111
CCCC Channel number CHN 0000-1110
Channel not specified 1111
Table 16-16.  MCA Compound Error Code Encoding for SRAO Errors
Type MCACOD Value MCA Error Code Encoding1
NOTES:
1. Note that for both of these errors the correction report filtering (F) bit (bit 12) of th e MCA error must be ignored. Memory Scrubbing C0H - CFH 0000_0000_1100_CCCC
000F 0000 1MMM CCCC (Memory Controller Error), where
Memory subfield MMM = 100B (memory scrubbing)Channel subfield CCCC = channel # or generic
L3 Explicit Writeback 17AH 0000_0001_0111_1010
000F 0001 RRRR TTLL (Cache Hierarchy Error) where
Request subfields RRRR = 0111B (Eviction)Transaction Type subfields TT = 10B (Generic)
Level subfields LL = 10B Vol. 3B 16-25MACHINE-CHECK ARCHITECTURE
Table 16-17 lists values of relevant bit fields of IA32_MCi_STATUS for architecturally defined SRAO errors. 
For both the memory scrubbing and L3 explicit writ eback errors, the ADDRV and MISCV flags in the IA32_M-
Ci_STATUS register are set to indicate that the offend ing physical address information is available from the 
IA32_MCi_MISC and the IA32_MCi_ADDR registers. For the memory scrubbing and L3 explicit writeback errors, 
the address mode in the IA32_MCi_MISC register should be set as physical address mode (010b) and the address 
LSB information in the IA32_MCi_MISC re gister should indicate the lowest valid address bit in the address informa-
tion provided from the IA32_MCi_ADDR register. 
MCE signal is broadcast to all logical processors as outlin ed in Section 16.10.4.1. If LMCE is supported and enabled, 
some errors (not limited to UCR errors) may be delivered to  only a single logical processor. System software should 
consult IA32_MCG_STATUS.LMCE_S to determine if the MCE signaled is only to this logical processor. 
IA32_MCi_STATUS banks can be shared by logical processors within a core or within the same package. So several 
logical processors may find an SRAO error in the shared  IA32_MCi_STATUS bank but other processors do not find 
it in any of the IA32_MCi_STATUS banks. Table 16-18 sh ows the RIPV and EIPV flag indication in the IA32_MC-
G_STATUS register for the memory scrubbing and L3 explicit writeback errors on both the reporting and non-
reporting logical processors. 
16.9.3.2  Architectura lly Defined SRAR Errors
The following two SRAR errors are architecturally defined. 
•UCR Errors detected on data load; and
•UCR Errors detected on instruction fetch.
The MCA error code encodings for thes e two architecturally-defined UCR errors corresponds to sub-classes of 
16-19. Table 16-17.  IA32_MCi_STATUS Values for SRAO Errors
SRAO Error Valid OVER UC EN MISCV ADDRV PCC S AR MCACOD
Memory Scrubbing 1 0 1 x1
NOTES:
1. When signaled as M CE, EN=1 and S=1. If error was sign aled via CMC, then EN=x, and S=0.11 0 x10C 0 H - C F H
L3 Explicit Writeback 1 0 1 x111 0 x101 7 A H
Table 16-18.  IA32_MCG_STATUS Flag Indication for SRAO Errors
SRAO Type Reporting Logical Processors No n-reporting Logical Processors
RIPV EIPV RIPV EIPV
M e m o r y  S c r u b b i n g  1010L 3  E x p l i c i t  W r i t e b a c k  1010
Table 16-19.  MCA Compound Error Code Encoding for SRAR Errors
Data Load 134H 0000_0001_0011_0100
000F 0001 RRRR TTLL (Cache Hierarchy Error), where
Request subfield RRRR = 0011B (Data Load)Transaction Type subfield TT= 01B (Data)
Level subfield LL  = 00B (Level 0)
Instruction Fetch 150H 0000_0001_0101_0000
000F 0001 RRRR TTLL (Cache Hierarchy Error), whereRequest subfield RRRR = 0 101B (Instruction Fetch)
Transaction Type subfield TT= 00B (Instruction)
Level subfield LL  = 00B (Level 0)16-26 Vol. 3BMACHINE-CHECK ARCHITECTURE
Table 16-20 lists values of relevant bit fields of IA32_MCi_STATUS for architecturally defined SRAR errors. 
For both the data load and instruction fetch errors, th e ADDRV and MISCV flags in the IA32_MCi_STATUS register 
are set to indicate that the offending physical address information is available from the IA32_MCi_MISC and the 
IA32_MCi_ADDR registers. For the data load and instruct ion fetch errors, the address mode in the IA32_MCi_MISC 
register should be set as physical address mode (010 b) and the address LSB information in the IA32_MCi_MISC 
register should indicate the lowest valid address bit in  the address information provided from the IA32_MCi_ADDR 
register. 
MCE signal is broadcast to all logical processors on the system on which the UCR errors are supported, except when 
the processor supports LMCE and LMCE is enabled by system software (see Section 16.3.1.5). The IA32_MC-
G_STATUS MSR allows system software to distinguish the affected logical processor of an SRAR error amongst 
logical processors that observed SRAR via MCi_STATUS bank.
Table 16-21 shows the RIPV and EIPV flag indication in  the IA32_MCG_STATUS register for the data load and 
instruction fetch errors on both the reporting and non-reporting logical processors. The recoverable SRAR error 
reported by a processor may be continuable, where the system software can interpret the context of continuable 
as follows: the error was isolated, contained. If software can rectify the error condition in the current instruction 
stream, the execution context on that logical processor can be continued without loss of information.
SRAR Error And Affected Logical Processors
The affected logical processor is the one that has detected  and raised an SRAR error at the point of the consump-
tion in the execution flow. The affected logical processor should find the Data Load or the Instruction Fetch error information in the IA32_MCi_STATUS regist er that is reporting the SRAR error. 
Table 16-21 list the actionable scenarios that system software can respond to an SRAR error on an affected logical 
processor according to RIPV and EIPV values:
•Recoverable-Continuable SRAR Error (RIPV=1, EIPV=1):
For Recoverable-Continuable SRAR errors, the affected logical processor should find that both the IA32_MC-
G_STATUS.RIPV and the IA32_MCG_STATUS.EIPV flags are set,  indicating that system software may be able to 
restart execution from the interrupted context if it is ab le to rectify the error condition. If system software 
cannot rectify the error condition then it must treat the error as a recoverable error where restarting execution 
with the interrupted context is not possi ble. Restarting without rectifying the error condition will result in most 
cases with another SRAR error on the same instruction.NOTES:
1. Note that for both of these errors the correction report  filtering (F) bit (bit 12) of the MCA error must be ignored.
Table 16-20.  IA32_MCi_STATUS Values for SRAR Errors
SRAR Error Valid OVER UC EN MISCV ADDRV PCC S AR MCACOD
D a t a  L o a d 1 0 111 1 0 1 1 1 3 4 HI n s t r u c t i o n  F e t c h 1 0 111 1 0 1 1 1 5 0 H
Table 16-21.  IA32_MCG_STATUS Fl ag Indication for SRAR Errors
SRAR Type Affected Logical Processor Non -Affected Logical Processors
RIPV EIPV Continuable RIPV EIPV Continuable
Recoverable-
continuable11Y e s1
NOTES:
1. see the definition of the context of “con tinuable” above and additional detail below.10 Y e sRecoverable-not-
continuable0xN oVol. 3B 16-27MACHINE-CHECK ARCHITECTURE
•Recoverable-not-continuable SRAR Error (RIPV=0, EIPV=x):
For Recoverable-not-continuable errors, the affected logical processor should find that either
— IA32_MCG_STATUS.RIPV= 0, IA32_MCG_STATUS.EIPV=1, or 
— IA32_MCG_STATUS.RIPV= 0, IA32_MCG_STATUS.EIPV=0.
In either case, this indicates that the error is detected at the instruction pointer saved on the stack for this 
machine check exception and restarting execution with the interrupted context is not possible. System 
software may take the following recovery actions for the affected logical processor: 
•The current executing thread cannot be continued. System software must terminate the interrupted

NOTES:
•The current executing thread cannot be continued. System software must terminate the interrupted 
stream of execution and provide a new stream of execution on return from the machine check handler 
for the affected logical processor.
SRAR Error And Non-Affected Logical Processors
The logical processors that observed but not affected by an SRAR error should find that the RIPV flag in the 
IA32_MCG_STATUS register is set and the EIPV flag in the IA32_MCG_STATUS register is cleared, indicating that it 
is safe to restart the execution at the instruction saved on the stack for the machine check exception on these 
processors after the recovery action is successfully taken by system software. 
16.9.4 Multiple MCA Errors 
When multiple MCA errors are detected within a cert ain detection window, the processor may aggregate the 
reporting of these errors together as a single event, i. e., a single machine exception condition. If this occurs, 
system software may find multiple MCA errors logged in  different MC banks on one logical processor or find 
multiple MCA errors logged across different processors fo r a single machine check broadcast event. In order to 
handle multiple UCR errors reported from a single mach ine check event and possibly recover from multiple errors, 
system software may consider the following: 
•Whether it can recover from multiple errors is determined  by the most severe error reported on the system.  If 
the most severe error is found to be an unrecoverab le error (VAL=1, UC=1, PCC=1 and EN=1) after system 
software examines the MC banks of all processors to which the MCA signal is broadcast, recovery from the 
multiple errors is not possible and system software needs to reset the system. 
•When multiple recoverable errors are reported and no ot her fatal condition (e.g., overflowed condition for SRAR 
error) is found for the reported recoverable errors, it  is possible for system software to recover from the 
multiple recoverable errors by taking necessary recovery action for each individual recoverable error. However, 
system software can no longer expect one to one rela tionship with the error information recorded in the 
IA32_MCi_STATUS register and the states of the RIPV an d EIPV flags in the IA32_MCG_STATUS register as the 
states of the RIPV and the EIPV flags in the IA32_MCG_ STATUS register may indicate the information for the 
most severe error recorded on the processor. System softwa re is required to use the RIPV flag indication in the 
IA32_MCG_STATUS register to make a final decision of re coverability of the errors and find the restart-ability 
requirement after examining each IA32_MCi_STATUS register error information in the MC banks. 
In certain cases where system software observes more  than one SRAR error logged for a single logical 
processor, it can no longer rely on affected threads as specified in Table 15-20 above. System software is 
recommended to reset the system if this condition is observed. 
16.9.5 Machine-Check Error Codes Interpretation
Chapter 17, “Interpreting Machine Check Error Codes,” prov ides information on interpreting the MCA error code, 
model-specific error code, and other information error code fields. For P6 family processors, information has been 
included on decoding external bus errors. For Pentium 4 and Intel Xeon processors; information is included on 
external bus, internal timer and cache hierarchy errors.16-28 Vol. 3BMACHINE-CHECK ARCHITECTURE
16.10 GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE
The machine-check architecture and error logging can be used in three different ways:
•To detect machine errors during normal instruction execution, using the machine-check exception (#MC).
•To periodically check and log machine errors.
•To examine recoverable UCR errors, determine software recoverability and perform recovery actions via a 
machine-check exception handler or a corrected machine-check interrupt handler.
To use the machine-check exception, the operating system  or executive software must provide a machine-check 
exception handler. This handler may need to be desi gned specifically for each family of processors.
A special program or utility is required to log machine errors.Guidelines for writing a machine-check exception handle r or a machine-error logging utility are given in the 
16.10.1 Machine-Check Exception Handler
The machine-check exception (#MC) corresponds to vector 18. To service machine-check exceptions, a trap gate 
must be added to the IDT. The pointer in the trap gate  must point to a machine-check exception handler. Two 
approaches can be taken to designing the exception handler:
1. The handler can merely log all the machine status and erro r information, then call a debugger or shut down the 
system.
2. The handler can analyze the reported error information and, in some cases, attempt to correct the error and 
restart the processor.
For Pentium 4, Intel Xeon, Intel Atom, P6 family, and Pe ntium processors; virtually all machine-check conditions 
cannot be corrected (they result in abort-type exceptions).  The logging of status and error information is therefore 
a baseline implementation requirement.
When IA32_MCG_CAP[24] is clear, consider the followi ng when writing a machine-check exception handler:
•To determine the nature of the error, the handler must read each of the error-reporting register banks. The 
count field in the IA32_MCG_CAP register gives number of register banks. The first register of register bank 0 
is at address 400H.
•The VAL (valid) flag in each IA32_MC i_STATUS register indicates whether th e error information in the register 
is valid. If this flag is clear, the registers in that bank do not contain valid error information and do not need to 
be checked.
•To write a portable exception handler, only  the MCA error code field in the IA32_MC i_STATUS register should be 
checked. See Section 16.9, “Interpret ing the MCA Error Codes,” for information that can be used to write an 
algorithm to interpret this field.
•Correctable errors are corrected automatically by the processor. The UC flag in each IA32_MCi_STATUS reg-
ister indicates whether the processor automatically corrected an error.
•The RIPV, PCC, and OVER flags in each IA32_MCi_STATUS re gister indicate whether recovery from the error is 
possible. If PCC or OVER are set, recovery is not possible. If RIPV is not set, program execution can not be 
restarted reliably. When recovery is not possible, the ha ndler typically records the error information and signals 
an abort to the operating system.
•The RIPV flag in the IA32_MCG_STATUS register indi cates whether the program can be restarted at the 
instruction indicated by the instruction pointer (the address of the instruction pushed on the stack when the 
exception was generated). If this flag is clear, the pr ocessor may still be able to be restarted (for debugging 
purposes) but not without loss of program continuity.
•For unrecoverable errors, the EIPV flag in the IA32_M CG_STATUS register indicates whether the instruction 
indicated by the instruction pointer pushed on the stac k (when the exception was generated) is related to the 
error. If the flag is clear, the pushed instruction may not be related to the error.
•The MCIP flag in the IA32_MCG_STATUS register indica tes whether a machine-check exception was generated. 
Before returning from the machine-check exception handler, software should clear this flag so that it can be used reliably by an error logging utility. The MCIP flag  also detects recursion. The machine-check architecture Vol. 3B 16-29MACHINE-CHECK ARCHITECTURE
does not support recursion. When the processor detects machine-check recursion, it enters the shutdown 
state.
Example 16-2 gives typical steps carried out by a machine-check exception handler.
Example 16-2.  Machine-Check Exception Handler Pseudocode
THEN
THEN
call errorlogging routine; (* returns restartability *)
FI;
ELSE (* Pentium(R) processor compatible *)
READ P5_MC_ADDR
READ P5_MC_TYPE;
report RESTARTABILITY to console;
FI;
IF error is not restartable
THEN
abort system;
FI;CLEAR MCIP flag in IA32_MCG_STATUS;
16.10.2 Pentium Processor Machine-Check Exception Handling
Machine-check exception handler on P6 family, Intel Atom and later processor families, should follow the guidelines 
described in Section 16.10.1 and Example 16-2 that check the processor’s support of MCA.
NOTE
On processors that support MCA (CPUID.1.E DX.MCA = 1) reading the P5_MC_TYPE and 
P5_MC_ADDR registers may produce invalid data.
When machine-check exceptions are enabled for the Pentium processor (MCE flag is set in control register CR4), 
the machine-check exception handler uses the RDMSR inst ruction to read the error type from the P5_MC_TYPE 
register and the machine check address from the P5_MC_AD DR register. The handler then normally reports these 
register values to the system console before aborting execution (see Example 16-2).

FI;
THEN
NOTE
16.10.3 Logging Correctable Machine-Check Errors
The error handling routine for servicing the machine-chec k exceptions is responsible for logging uncorrected 
errors.
If a machine-check error is correctable, the processor does not generate a machine-check exception for it. To 
detect correctable machine-check errors, a utility program must be written that reads each of the machine-check error-reporting register banks and logs the results in an accounting file or data structure. This utility can be imple-
mented in either of the following ways.
•A system daemon that polls the register banks on an infrequent basis, such as hourly or daily.
•A user-initiated application that polls the register ba nks and records the exceptions. Here, the actual polling 
service is provided by an operating-system driver or through the system call interface.
•An interrupt service routine servicing CMCI can read the MC banks and log the error. Please refer to Section 
16.10.4.2 for guidelines on logging correctable machine checks.
Example 16-3 gives pseudocode for an error logging utility.16-30 Vol. 3BMACHINE-CHECK ARCHITECTURE
Example 16-3.  Machine-Check Error Logging Pseudocode
Assume that execut ion is restartable;
IF the processor supports MCA
THEN
FOR each bank of machine-check registers 
DO
READ IA32_MC i_STATUS;
IF VAL flag in IA32 _MCi_STATUS = 1
THEN
IF ADDRV flag in IA32_MC i_STATUS = 1
THEN READ IA32_MC i_ADDR; 
FI;IF MISCV flag in IA32_MC i_STATUS = 1
THEN READ IA32_MC i_MISC;
FI;IF MCIP flag in IA32_MCG_STATUS = 1
(* Machine-check exception is in progress *) 
AND PCC flag in IA32_MC i_STATUS = 1
OR RIPV flag in IA32_MCG_STATUS = 0
(* execution is not restartable *)
THEN 
RESTARTABILITY = FALSE;
return RESTARTABILITY to calling procedure;
FI;Save time-stamp counter and processor ID;
Set IA32_MC i_STATUS to all 0s;
Execute serializing instruction (i.e., CPUID);
FI;
OD;
FI;
If the processor supports the machin e-check architecture, the utility reads through the banks of error-reporting 
registers looking for valid register entries.  It then saves the values of the IA32_MC i_STATUS, IA32_MC i_ADDR, 
IA32_MC i_MISC, and IA32_MCG_STATUS registers for each bank that is valid. The routine minimizes processing 
time by recording the raw data into a system data structur e or file, reducing the overhead associated with polling. 
User utilities analyze the collected  data in an off-line environment.
When the MCIP flag is set in the IA32_MCG_STATUS regi ster, a machine-check exception is in progress and the 
machine-check exception handler has ca lled the exception logging routine. 
Once the logging process has been completed the except ion-handling routine must determine whether execution 
can be restarted, which is usually possible when damage has not occurred (The PCC flag is clear, in the IA32_M-
Ci_STATUS register) and when the processor can guarantee that execution is restartable (the RIPV flag is set in the 
IA32_MCG_STATUS register). If execution cannot be restar ted, the system is not recoverable and the exception-
handling routine should signal the console appropriately before returning the error status to the Operating System 
kernel for subsequent shutdown.
The machine-check architecture allows buffering of exce ptions from a given error-reporting bank although the 
Pentium 4, Intel Xeon, Intel Atom, and P6 family proce ssors do not implement this feature. The error logging 
routine should provide compatibility with future proce ssors by reading each hardware error-reporting bank's 
IA32_MC i_STATUS register and then writing 0s to clear the OV ER and VAL flags in this register. The error logging 
utility should re-read the IA32_MC i_STATUS register for the bank ensuring that the valid bit is clear. The processor 
will write the next error into the register bank and set the VAL flags. 
Additional information that should be stored by the exce ption-logging routine includes the processor’s time-stamp 
counter value, which provides a mechanism to indicate the frequency of exceptions. A multiprocessing operating 
system stores the identity of the processor node incurri ng the exception using a unique identifier, such as the 
processor’s APIC ID (see Section 11.8, “Handling Interrupts”). 
The basic algorithm given in Example 16-3 can be modifi ed to provide more robust  recovery techniques. For 
example, software has the flexibility to attempt recovery  using information unavailable to the hardware. Specifi-
cally, the machine-check exception handler can, after logg ing carefully analyze the error-reporting registers when 
the error-logging routine reports an error that does not a llow execution to be restarted. These recovery techniques Vol. 3B 16-31MACHINE-CHECK ARCHITECTURE
can use external bus related model-specific information provid ed with the error report to localize the source of the 
error within the system and determine the appropriate recovery strategy. 
16.10.4 Machine-Check Software Hand ler Guidelines for Error Recovery
16.10.4.1  Machine-Check Exception Handler for Error Recovery
When writing a machine-check exception (MCE) handler to  support software recovery from Uncorrected Recover-
able (UCR) errors, consider the following: 
•When IA32_MCG_CAP [24] is zero, there are no recoverable errors supported and all machine-check are fatal 
exceptions. The logging of status and error informatio n is therefore a baseline implementation requirement. 
•When IA32_MCG_CAP [24] is 1, certain uncorrected erro rs called uncorrected recove rable (UCR) errors may be 
software recoverable. The handler can analyze the report ed error information, and in some cases attempt to 
recover from the uncorrected error and continue execution.
•For processors on which CPUID reports DisplayFamily_Di splayModel as 06H_0EH and onward, an MCA signal is 
broadcast to all logical processors in the system; see the CPUID instruction in Chapter 3, “Instruction Set Reference, A-L‚” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. Due to the 
potentially shared machine check MSR resources among th e logical processors on the same package/core, the 
MCE handler may be required to synchronize with the ot her processors that received a machine check error and 
serialize access to the machine check registers when analyzing, logging, and clearing the information in the 
machine check registers.
— On processors that indicate ability for local machine-check exception (MCG_LMCE_P), hardware can choose 
to report the error to only a single logical proce ssor if system software ha s enabled LMCE by setting 
IA32_MCG_EXT_CTL[LMCE_EN] = 1 as outlined in Section 16.3.1.5.
•The VAL (valid) flag in each IA32_MCi_STATUS register indicates whether the error information in the register 
is valid. If this flag is clear, the registers in that ba nk do not contain valid error information and should not be 
checked.
•The MCE handler is primarily responsible for processing  uncorrected errors. The UC flag in each IA32_M-
Ci_Status register indicates whether the reported erro r was corrected (UC=0) or uncorrected (UC=1). The MCE 
handler can optionally log and clear the corrected errors in the MC banks if it can implement software algorithm 
to avoid the undesired race conditions with the CMCI or CMC polling handler.
•For uncorrectable errors, the EIPV flag in the IA32_ MCG_STATUS register indicates (when set) that the 
instruction pointed to by the instru ction pointer pushed onto the stack when the machine-check exception is 
generated is directly associated with the error. When this  flag is cleared, the instruction pointed to may not be 
associated with the error. 
When a machine check exception is generated, it is expected that the MCIP flag in the IA32_MCG_STATUS 
register is set to 1. If it is not set, this machine check was generated by either an INT 18 instruction or some 
piece of hardware signaling an interrupt with vector 18. 
When IA32_MCG_CAP [24] is 1, the following rules ca n apply when writing a machine check exception (MCE) 
handler to support software recovery: 
•The PCC flag in each IA32_MCi_STATUS register indica tes whether recovery from the error is possible for 
uncorrected errors (UC=1). If the PCC flag is set for en abled uncorrected errors (UC= 1 and EN=1), recovery is 
not possible. When recovery is not possible, the MCE ha ndler typically records the error information and signals 
the operating system to reset the system. 
•The RIPV flag in the IA32_MCG_STATUS register indicate s whether restarting the program execution from the 
instruction pointer saved on the stack for the machine check exception is possible. When the RIPV is set, 
program execution can be restarted reliably when recovery  is possible. If the RIPV flag is not set, program

program execution can be restarted reliably when recovery  is possible. If the RIPV flag is not set, program 
execution cannot be restarted reliably. In this case th e recovery algorithm may involve terminating the current 
program execution and resuming an alternate thread of execution upon return from the machine check handler 
when recovery is possible. When recovery is not possi ble, the MCE handler signals the operating system to 
reset the system. 16-32 Vol. 3BMACHINE-CHECK ARCHITECTURE
•When the EN flag is zero but the VAL and UC flags are one in the IA32_MCi_STATUS register, the reported 
uncorrected error in this bank is not enabled. As uncorre cted errors with the EN flag = 0 are not the source of 
machine check exceptions, the MCE handler should log an d clear non-enabled errors when the S bit is set and 
should continue searching for enabled errors from th e other IA32_MCi_STATUS registers. Note that when 
IA32_MCG_CAP [24] is 0, any uncorrected error conditio n (VAL =1 and UC=1) including the one with the EN 
flag cleared are fatal and the handler must signal the op erating system to reset the system. For the errors that 
do not generate machine check exceptions, the EN flag has no meaning.
•When the VAL flag is one, the UC flag is one, the EN fl ag is one and the PCC flag is  zero in the IA32_MCi_STATUS 
register, the error in this bank is an uncorrected recoverable (UCR) error. The MCE handler needs to examine the S flag and the AR flag to find the type of the UCR e rror for software recovery and determine if software error 
recovery is possible. 
•When both the S and the AR flags are clear in the IA 32_MCi_STATUS register for the UCR error (VAL=1, UC=1, 
EN=x and PCC=0), the error in this bank is an uncorre cted no-action required error (UCNA). UCNA errors are 
uncorrected but do not require any OS recovery action to  continue execution. These errors indicate that some 
data in the system is corrupt, but that data has not been consumed and may not be consumed.   If that data is 
consumed a non-UCNA machine check exception will be ge nerated. UCNA errors are signaled in the same way 
as corrected machine check errors and the CMCI and CM C polling handler is primarily responsible for handling 
UCNA errors. Like corrected errors, the MCA handler can op tionally log and clear UCNA errors as long as it can 
avoid the undesired race condition with the CMCI or CMC polling handler. As UCNA errors are not the source of 
machine check exceptions, the MCA handler should continue searching for uncorrected or software recoverable 
errors in all other MC banks. 
•When the S flag in the IA32_MCi_STATUS register is set for the UCR error ((VAL=1, UC=1, EN=1 and PCC=0), 
the error in this bank is software recoverable and it was signaled through a machine-check exception.  The AR 
flag in the IA32_MCi_STATUS register further clarif ies the type of the software recoverable errors. 
•When the AR flag in the IA32_MCi_STATUS register is clear for the software recoverable error (VAL=1, UC=1, 
EN=1, PCC=0 and S=1), the error in this  bank is a software recoverable action optional (SRAO) error. The MCE 
handler and the operating system can analyze the IA 32_MCi_STATUS [15:0] to implement MCA error code 
specific optional recovery action, but this recovery acti on is optional. System software can resume the program 
execution from the instruction pointer saved on the stac k for the machine check exception when the RIPV flag 
in the IA32_MCG_STATUS register is set. 
•Even if the OVER flag in the IA32_MCi_STATUS register is set for the SRAO error (VAL=1, UC=1, EN=1, PCC=0, 
S=1 and AR=0), the MCE handler can take recovery acti on for the SRAO error logged in the IA32_MCi_STATUS 
register. Since the recovery action for SRAO errors is optional, restarting the program execution from the instruction pointer saved on the stack for the machine ch eck exception is still possible for the overflowed SRAO 
error if the RIPV flag in the IA32_MCG_STATUS is set. 
•When the AR flag in the IA32_MCi_STATUS register is  set for the software recoverable error (VAL=1, UC=1, 
EN=1, PCC=0 and S=1), the error in this bank is a softwa re recoverable action required (SRAR) error. The MCE 
handler and the operating system must take recovery ac tion in order to continue execution after the machine-
check exception. The MCA handler and the operating syst em need to analyze the IA32_MCi_STATUS [15:0] to 
determine the MCA error code specific recovery action. If no recovery acti on can be performed, the operating 
system must reset the system. 
•When the OVER flag in the IA32_MCi_STATUS register is set for the SRAR error (VAL=1, UC=1, EN=1, PCC=0, 
S=1 and AR=1), the MCE handler cannot take recovery ac tion as the information of the SRAR error in the 
IA32_MCi_STATUS register was potentially lost due to th e overflow condition. Since the recovery action for 
SRAR errors must be taken, the MCE handler must signal the operating system to reset the system. 
•When the MCE handler cannot find any uncorrected (V AL=1, UC=1 and EN=1) or any software recoverable 
errors (VAL=1, UC=1, EN=1, PCC=0 and S=1) in any of  the IA32_MCi banks of the processors, this is an 
unexpected condition for the MCE handler and the handle r should signal the operating system to reset the 
system. 
•Before returning from the machine-check exception handle r, software must clear the MCIP flag in the IA32_MC-
G_STATUS register. The MCIP flag is used to detect re cursion. The machine-check architecture does not support 
recursion. When the processor receives a machine chec k when MCIP is set, it automatically enters the 
shutdown state.
Example 16-4 gives pseudocode for an MC except ion handler that supports recovery of UCR.Vol. 3B 16-33MACHINE-CHECK ARCHITECTURE
Example 16-4.  Machine-Check Error Handler Pseudocode Supporting UCR
MACHINE CHECK HANDLER:  (* Called from INT 18 handler *)
NOERROR = TRUE;ProcessorCount = 0;
THEN
RESTARTABILITY = TRUE;
IF (Processor Family = 6 AND DisplayModel ≥ 0EH) OR (Processor Family > 6) 
THEN
IF ( MCG_LMCE = 1)
MCA_BROADCAST = FALSE;
ELSE
MCA_BROADCAST = TRUE;
FI;
Acquire SpinLock; ProcessorCount++;  (* Allowing on e logical processor at a time to examine machine check registers *)
CALL MCA ERROR PROCESSING; (* retu rns RESTARTABILITY and NOERROR *)
ELSE 
(* Implement a rendezvous mechanism with  the other processors if necessary *)
CALL MCA ERROR PROCESSING;
FI;
READ P5_MC_ADDRREAD P5_MC_TYPE;
FI;
IF NOERROR = TRUE
    THEN
IF NOT (MCG_RIPV = 1 AND MCG_EIPV = 0) 
THEN 
FI
FI;
IF RESTARTABILITY = FALSE
THEN 
Report RESTARTABILITY to console;
Reset system; 
FI;
IF MCA_BROADCAST = TRUE
THEN
IF ProcessorCount = MAX_PROCESSORS
    AND NOERROR = TRUE
THEN
Reset system;
FI;
Release SpinLock; 
Wait till ProcessorCount = MAX_PROCESSRS on system; (* implement a timeout and ab ort function if necessary *)
FI;
CLEAR IA32_MCG_STATUS;RESUME Execution;
(* End of MACHINE CHECK HANDLER*)
MCA ERROR PROCESSING:    (* MCA Error Proc essing Routine called from MCA Handler *)
IF MCIP flag in IA32_MCG_STATUS = 0
THEN (* MCIP=0 upon MCA is unexpected *)
FI;16-34 Vol. 3BMACHINE-CHECK ARCHITECTURE
DO
CLEAR_MC_BANK = FALSE;READ IA32_MCi_STATUS;
IF VAL Flag in IA32_MCi_STATUS = 1
THEN
IF UC Flag in IA32_MCi_STATUS = 1
THEN 
IF Bit 24 in IA32_MCG_CAP = 0
THEN (* the processor does not support software error recovery *)
NOERROR = FALSE;GOTO LOG MCA REGISTER;
FI;
(* the processor supports software error recovery *)IF EN Flag in IA32_MCi_STATUS = 0 AND OVER Flag in IA32_MCi_STATUS=0
THEN (* It is a spurious MCA Lo g. Log and clear the register *)
CLEAR_MC_BANK = TRUE;GOTO LOG MCA REGISTER;
FI;
IF PCC = 1 and EN = 1 in IA32_MCi_STATUS
THEN (* processor context might have been corrupted *)
RESTARTABILITY = FALSE; 
ELSE (* It is a uncorrected recoverable (UCR) error *)
IF S Flag in IA32_MCi_STATUS = 0
THEN 
IF AR Flag in IA32_MCi_STATUS = 0
THEN (* It is a uncorrected no action required (UCNA) error *)
GOTO CONTINUE; (* let CMCI and CMC polling handler to process *)
ELSE
RESTARTABILITY = FALSE; (* S=0, AR=1 is illegal *)
FI
FI; IF RESTARTABILITY = FALSE
THEN (* no need to take recovery acti on if RESTARTABILITY is already false *)
FI;
(* S in IA32_MCi_STATUS = 1 *) IF AR Flag in IA32_MCi_STATUS = 1
THEN (* It is a software recoverabl e and action required (SRAR) error *)
IF OVER Flag in IA32_MCi_STATUS = 1
THEN
NOERROR = FALSE;
GOTO LOG MCA REGISTER;
FI
IF MCACOD Value in IA32_MCi_STATUS is recognized
    AND Current Processor is an Affected Processor 
THEN
Implement MCACOD specific recovery action;
CLEAR_MC_BANK = TRUE; 
ELSE 
FI;
ELSE (* It is a software recoverabl e and action optional (SRAO) error *)
IF OVER Flag in IA32_MCi_STATUS = 0 AND
 MCACOD in IA32_MCi_STATUS is recognized
THEN
FI;CLEAR_MC_BANK = TRUE;

ELSE
FI
FI;
THEN
FI
THEN
ELSE 
FI;
THEN
FI; AR 
FI; PCCNOERROR = FALSE;Vol. 3B 16-35MACHINE-CHECK ARCHITECTURE
ELSE  (* It is a corrected error; continue to the next IA32_MCi_STATUS *) 
GOTO CONTINUE;
FI; UC
FI; VAL 
LOG MCA REGISTER:
SAVE IA32_MCi_STATUS;
If MISCV in IA32_MCi_STATUS 
THEN
SAVE IA32_MCi_MISC;
FI;
IF ADDRV in IA32_MCi_STATUS
THEN
SAVE IA32_MCi_ADDR;
FI;IF CLEAR_MC_BANK = TRUE
THEN
SET all 0 to IA32_MCi_STATUS;If MISCV in IA32_MCi_STATUS 
THEN
SET all 0 to IA32_MCi_MISC;
FI;
THEN
SET all 0 to IA32_MCi_ADDR;
FI;
FI;CONTINUE:
OD;
( *END FOR *)RETURN;
(* End of MCA ERROR PROCESSING*)
16.10.4.2  Corrected Machine-Check Handler for Error Recovery
When writing a corrected machine check handler, which is in voked as a result of CMCI or called from an OS CMC 
Polling dispatcher, consider the following: 
is valid. If this flag is clear, the registers in that bank  does not contain valid error information and does not need 
to be checked.
•The CMCI or CMC polling handler is responsible for logging  and clearing corrected errors. The UC flag in each 
IA32_MCi_Status register indicates whether the repo rted error was corrected (UC=0) or not (UC=1). 
•When IA32_MCG_CAP [24] is one, the CMC handler is al so responsible for logging and clearing uncorrected no-
action required (UCNA) errors. When the UC flag is on e but the PCC, S, and AR flags are zero in the IA32_M-
Ci_STATUS register, the reported  error in this bank is an uncorrected no-action required (UCNA) error. In cases 
when SRAO error are signaled as UCNA error via CM CI, software can perform recovery for those errors 
identified in Table 16-16.
•In addition to corrected errors and UCNA errors, th e CMC handler optionally logs uncorrected (UC=1 and 
PCC=1), software recoverable machine check errors (UC= 1, PCC=0 and S=1), but should avoid clearing those 
errors from the MC banks. Clearing these errors may resu lt in accidentally removing these errors before these 
errors are actually handled and processed by the MCE handler for attempted software error recovery.
Example 16-5 gives pseudocode for a CMCI handler with UCR support.16-36 Vol. 3BMACHINE-CHECK ARCHITECTURE
Example 16-5.  Corrected Error Handler Pseudocode with UCR Support
Corrected Error HANDLER:  (* Called from CMCI handler or  OS CMC Polling Dispatcher*)
THEN
DO
READ IA32_MCi_STATUS;
IF VAL flag in IA32_MCi_STATUS = 1
THEN
IF UC Flag in IA32_MCi_STATUS = 0 (* It is a corrected error *)
THEN 
GOTO LOG CMC ERROR;
ELSE 
THEN
FI;
IF S Flag in IA32_MCi_STATUS = 0 AN D AR Flag in IA32_MCi_STATUS = 0
THEN (* It is a uncorrected no action required error *)
GOTO LOG CMC ERROR
FIIF EN Flag in IA32_MCi_STATUS = 0
THEN (* It is a spurious MCA error *)
FI;
FI;
FI;GOTO CONTINUE;
LOG CMC ERROR: 
SAVE IA32_MCi_STATUS;If MISCV Flag in IA32_MCi_STATUS 
THEN
SAVE IA32_MCi_MISC;SET all 0 to IA32_MCi_MISC;
FI;
IF ADDRV Flag in IA32_MCi_STATUS
THEN
SET all 0 to IA32_MCi_ADDR
FI;SET all 0 to IA32_MCi_STATUS;
CONTINUE:
OD;
( *END FOR *)
FI;Vol. 3B 17-1CHAPTER 17
Encoding of the model-specific and ot her information fields is different across processor families. The differences 
are documented in the following sections.
17.1 INCREMENTAL DECODING INFORM ATION: PROCESSOR FAMILY 06H, 
MACHINE ERROR CODES FOR MACHINE CHECK
This section provides information for inte rpreting additional model-specific fields  for external bus errors relating to 
processor family 06H. The references to processor family  06H refers to only IA-32 processors with CPUID signa-
tures listed in Table 17-1.
These errors are reported in the IA32_MCi_STATUS MSRs. They are reported architecturally as compound errors 
with a general form of 0000 1PPT RRRR IILL  in the MCA error code field. See Chapter 16 for information on the 
interpretation of compound error codes. Incremen tal decoding information is listed in Table 17-2.Table 17-1.   CPUID DisplayFamily_DisplayM odel Signatures for Processor Family 06H
DisplayFamily_DisplayModel Processor Families/Processor Number Series
06_0EH Intel® Core™ Duo processor, Intel® Core™ Solo processor
06_0DH Intel Pentium M processor
06_09H Intel Pentium M processor
06_7H, 06_08H, 06_0AH, 06_0BH Intel Pentium III Xeon Processor, Intel Pentium III Processor
06_03H, 06_05H Intel Pentium II Xeon Processor, Intel Pentium II Processor 
06_01H Intel Pentium Pro Processor 
Table 17-2.  Incremental Decoding In formation: Processor Family 06H Ma chine Error Codes for Machine Check 
Type Bit No. Bit Function Bit Description
MCA Error 
Codes1 15:0
Model Specific 
Errors18:16 Reserved Reserved
24:19 Bus Queue Request 
Type000000: BQ_DCU_READ_TYPE error.
000010: BQ_IFU_DEMAND_TYPE error.000011: BQ_IFU_DEMAND_NC_TYPE error.
000100: BQ_DCU_RFO_TYPE error.
000101: BQ_DCU_RFO_LOCK_TYPE error.
000110: BQ_DCU_ITOM_TYPE error.
001000: BQ_DCU_WB_TYPE error.
001010: BQ_DCU_WCEVICT_TYPE error.
001011: BQ_DCU_WCLINE_TYPE error.001100: BQ_DCU_BTM_TYPE error.17-2 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
001101: BQ_DCU_INTACK_TYPE error.
001110: BQ_DCU_INVALL2_TYPE error.
001111: BQ_DCU_FLUSHL2_TYPE error.
010000: BQ_DCU_PART_RD_TYPE error.010010: BQ_DCU_PAR T_WR_TYPE error.
010100: BQ_DCU_SPEC_CYC_TYPE error.
011000: BQ_DCU_IO_RD_TYPE error.
011001: BQ_DCU_IO_WR_TYPE error.011100: BQ_DCU_LOCK_RD_TYPE error.
011110: BQ_DCU_SPLOCK_RD_TYPE error.
011101: BQ_DCU_LOCK_WR_TYPE error.
27:25 Bus Queue Error Type 000: BQ_ERR_HARD_TYPE error.
001: BQ_ERR_DOUBLE_TYPE error.
010: BQ_ERR_AERR2_TYPE error.
100: BQ_ERR_SINGLE_TYPE error.
101: BQ_ERR_AERR1_TYPE error.
28 FRC Error 1 if FRC error active.29 BERR 1 if BERR is driven.30 Internal BINIT 1 if BINI T driven for this processor.
31 Reserved Reserved
Other 
Information34:32 Reserved Reserved
35 External BINIT 1 if BINIT is  received from external bus.
36 Response Parity Error This bit is asserted in IA32_MC i_STATUS if this component has received a parity 
error on the RS[2:0]# pins for a response transaction. The RS signals are checked 
by the RSP# external pin.
37 Bus BINIT This bit is asserted in IA32_MC i_STATUS if this component has received a hard 
error response on a split tr ansaction one access that ha s needed to be split across 
the 64-bit external bus in terface into two accesses).
38 Timeout BINIT This bit is asserted in IA32_MC i_STATUS if this component has experienced a ROB 
time-out, which indicates that no micro-instruction has been retired for a predetermined period of time.
A ROB time-out occurs when the 15-bit ROB time-out coun ter carries a 1 out of its 
high order bit. 
2 The timer is cleared when a micro-instruction retires, an exception 
is detected by the core processor, RESET is asserted, or when a ROB BINIT occurs.
The ROB time-out counter is prescaled by the 8-bit PIC timer which is a divide by 
128 of the bus clock (the bus clock is 1:2, 1:3, 1:4 of the core clock3). When a carry 
out of the 8-bit PIC timer occurs, the ROB count er counts up by one. While this bit is 
asserted, it cannot be overwritten by another error.
41:39 Reserved Reserved42 Hard Error This bit is asserted in IA32_MC i_STATUS if this component has initiated a bus 
transactions which has received a hard error response. While this bit is asserted, it 
cannot be overwritten.
43 IERR This bit is asserted in IA32_MC i_STATUS if this component has experienced a 
failure that causes the IERR pin to be asserted. While this  bit is asserted, it cannot 
be overwritten.Table 17-2.  Incremental Decoding In formation: Processor Family 06H Mach ine Error Codes for Machine Check  
Type Bit No. Bit Function Bit DescriptionVol. 3B 17-3INTERPRETING MACHINE CHECK ERROR CODES
17.2 INCREMENTAL DECODING INFORM ATION: INTEL® CORE™ 2 PROCESSOR 
FAMILY, MACHINE ERROR CODES FOR MACHINE CHECK
Table 17-4 provides information for interpreting additional model-specific fields for external bus errors relating to 
processors based on Intel® Core™ microarchitecture, which implements the P4 bus specification. Table 17-3 lists 
the CPUID signatures for Intel 64 processors that are co vered by Table 17-4. These errors are reported in the 
IA32_MCi_STATUS MSRs. They are reported architecturally as compound errors with a general form of 
0000 1PPT RRRR IILL  in the MCA error code field. See Chapter 16 for information on the interpretation of 
compound error codes.44 AERR This bit is asserted in IA32_MC i_STATUS if this component has initiated 2 failing 
bus transactions which have failed due to  Address Parity Errors AERR asserted). 
While this bit is asserted, it cannot be overwritten.
45 UECC The Uncorrectable ECC error bit is asserted in IA32_MC i_STATUS for uncorrected 
ECC errors. While this bit is asserted, the ECC syndrome field will not be overwritten.

46 CECC The correctable ECC error bit is asserted in IA32_MC i_STATUS for corrected ECC 
errors.
54:47 ECC Syndrome The ECC syndrome field in IA32_MCi_STATUS contains the 8-bit ECC syndrome only 
if the error was a correctable/uncorrectable ECC error and there wasn't a previous valid ECC error syndrome logged in IA32_MCi_STATUS. 
A previous valid ECC error in IA32_MCi_STATUS is indicated by 
IA32_MCi_STATUS.bit45 uncorrectable er ror occurred) being asserted. After 
processing an ECC error, machine check handling software should clear 
IA32_MCi_STATUS.bit45 so that future ECC error syndromes can be logged.
56:55 Reserved Reserved
Status Register 
Validity 
Indicators1 63:57
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.
2. For processors with a CPUID signature of 06_0EH, a ROB time-o ut occurs when the 23-bit ROB time-out counter carries a 1 out of its 
high order bit.
3. For processors with a CPUID signature of 6_06_60H an d later, the PIC timer will count crystal clock cycles.
Table 17-3.   CPUID DisplayFamily_Disp layModel Signatures for Pr ocessors Based on Intel®  Core™ Microarchitecture
06_1DH Intel® Xeon® Processor 7400 series
06_17H Intel® Xeon® Processor 5200, 5400 series , Intel® Core™ 2 Quad processor Q9650
06_0FH Intel® Xeon® Processor 3000, 3200, 5100, 5300, 7 300 series, Intel® Core™ 2 Quad, Intel® Core™ 2 
Extreme, Intel® Core™ 2 Duo processo rs, Intel Pentium dual-core processorsTable 17-2.  Incremental Decoding In formation: Processor Family 06H Machine Error Codes for Machine Check  
Type Bit No. Bit Function Bit Description17-4 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
Table 17-4.  Incremental Bus Error Co des of Machine Check for Processors 
Based on Intel® Core™ Microarchitecture
MCA Error 
Type‘000001: BQ_PREF_READ_TYPE error.
000000: BQ_DCU_READ_TYPE error.000010: BQ_IFU_DEMAND_TYPE error
000011: BQ_IFU_DEMAND_NC_TYPE error.
000100: BQ_DCU_RFO_TYPE error.000101: BQ_DCU_RFO_LOCK_TYPE error.
001000: BQ_DCU_WB_TYPE error.001010: BQ_DCU_WCEVICT_TYPE error.
001011: BQ_DCU_WCLINE_TYPE error.
001100: BQ_DCU_BTM_TYPE error.
010000: BQ_DCU_PART_RD_TYPE error.010010: BQ_DCU_PART_WR_TYPE error.
011110: BQ_DCU_SPL OCK_RD_TYPE error.
100100: BQ_L2_WI_RFO_TYPE error.100110: BQ_L2_WI_ITOM_TYPE error.
27:25 Bus Queue Error Type ‘001: Address Parity Error.
‘010: Response Hard Error.
‘011: Response Parity Error.
28 MCE Driven 1 if MCE is driven.29 MCE Observed 1 if MCE is observed.30 Internal BINIT 1 if BINIT driven for this processor.31 BINIT Observed 1 if BINIT is observed for this processor.
Other 
Information33:32 Reserved Reserved
34 PIC and FSB Data 
ParityData Parity dete cted on either PIC or FSB access.
35 Reserved Reserved
error on the RS[2:0]# pins for a response  transaction. The RS signals are checked 
by the RSP# external pin.Vol. 3B 17-5INTERPRETING MACHINE CHECK ERROR CODES
17.2.1  Model-Specific Machine Check Error Codes for Intel® Xeon® Processor 7400 Series
The Intel® Xeon® processor 7400 series has machine check register banks that generally follow the description of 
Chapter 16 and Section 17.2. Additional error codes specific to the Intel Xeon processor 7400 series are described 
MC4_STATUS[63:0] is the main error logging for the proce ssor’s L3 and front side bus errors for the Intel Xeon 
processor 7400 series. It supports the L3 Errors, Bus an d Interconnect Errors Compound Error Codes in the MCA 
Error Code Field.37 FSB Address Parity Addre ss parity error detected:
1: Address parity error detected.
0: No address parity error.
time-out, which indicates that no micro-instruction has been retired for a 
predetermined period of time.
A ROB time-out occurs when the 23-bit ROB time-out counter carries a 1 out of its 
high order bit. The timer is cleared when a micro-instruction retires, an exception is detected by the core processor, RESET is asserted, or when a ROB BINIT occurs.
128 of the bus clock the bus clock is 1:2, 1:3, 1:4 of the core clock). When a carry 
out of the 8-bit PIC timer occu rs, the ROB counter counts up by one. While this bit is 
transactions which has received a hard error response. While this bit is asserted, it cannot be overwritten.
failure that causes the IERR pin to be asse rted. While this bit is asserted, it cannot 
be overwritten.
44 Reserved Reserved45 Reserved Reserved46 Reserved Reserved54:47 Reserved Reserved56:55 Reserved Reserved.
Validity 
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.Table 17-4.  Incremental Bus Error Co des of Machine Check for Processors 
Based on Intel® Core™ Microarchitecture (Contd.)
Type Bit No. Bit Function Bit Description17-6 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.2.1.1  Processor Machine Check Status Re gister, Incremental MCA Error Code Definition
The Intel Xeon processor 7400 series uses compound MCA Error Codes for logging its Bus internal machine check 
errors, L3 Errors, and Bus/Interc onnect Errors. It defines incremental Machine Check error types 
(IA32_MC6_STATUS[15:0]) beyond those defined in Chap ter 16. Table 17-5 lists these incremental MCA error 
code types that apply to IA32_MC6_STATUS. Error co de details are specified in MC6_STATUS [31:16] (see 
Section 17.2.2), the “Model Specific Error Code” fi eld. The information in the “Other_Info” field 
(MC4_STATUS[56:32]) is common to the three processor e rror types. It contains a correctable event count and 
specifies the MC6_MISC register format.
The Bold faced  binary encodings are the only encodings used by the processor for MC4_STATUS[15:0].
17.2.2  Intel® Xeon® Processor 7400 Model Specific Error Code Field
17.2.2.1  Processor Mode l Specific Error Code Fi eld, Type B: Bus and In terconnect Error Codes
The Model Specific Error Code field in MC6_STATUS (bits 31:16) is defined in Table 17-6.Table 17-5.  Incremental MCA Error Code Types for Intel® Xeon® Processor 7400 
Processor MCA_Error_Code (MC6_STATUS[15:0])
Type Error Code Binary Encoding MeaningC Internal Error 0000 0100 0000 0000 Internal Error Type Code.BB u s  a n d  
Interconnect 
Error0000 100x 0000 1111 Not used but this encoding is reserved for compatibility with other MCA 
0000 101x 0000 1111 Not used but this encoding is reserved for compatibility with other MCA 
0000 110x 0000 1111 Not used but this encoding is reserved for compatibility with other MCA 
0000 1110 0000 1111 Bus and Interconnection Error Type Code.0000 1111 0000 1111 Not used but this encoding is reserved for compatibility with other MCA 
Table 17-6.  Type B: Bus and Interconnect Error Codes
Bit Number Sub-Field Name Description
16 FSB Request Parity Parity error de tected during FSB request phase.
19:17 Reserved Reserved20 FSB Hard Fail Response “Hard Failure“ response received for a local transaction.21 FSB Response Parity Parity error on FSB response field detected.
22 FSB Data Parity FSB data parity error on inbound data detected.31:23 Reserved ReservedVol. 3B 17-7INTERPRETING MACHINE CHECK ERROR CODES
17.2.2.2  Processor Model Specific Error Code Field, Type C: Cache Bus Controller Error Codes
17.3 INCREMENTAL DECODING INFORM ATION: INTEL® XEON® PROCESSOR 
3400, 3500, 5500 SERIES , MACHINE ERROR CODES FOR MACHINE CHECK
Table 17-8 through Table 17-12 provide information for inte rpreting additional model-specific fields for memory 
controller errors relating to the Intel® Xeon® processor 3400, 3500, 5500 series with CPUID DisplayFamily_Dis-
playSignature 06_1AH, which supports Intel® QuickPath Interconnect links. Incremental MC error codes related to 
the Intel QPI links are reported in the register banks IA 32_MC0 and IA32_MC1, incremental error codes for internal

the Intel QPI links are reported in the register banks IA 32_MC0 and IA32_MC1, incremental error codes for internal 
machine check are reported in the register bank IA32_MC7,  and incremental error codes for the memory controller 
unit are reported in the register bank IA32_MC8.Table 17-7.  Type C: Cache Bus Controller Error Codes
MC4_STATUS[31:16] (MSCE) Value Error Description
0000_0000_0000_0001 0001H Inclusion Error from Core 0.0000_0000_0000_0010 0002H Inclusion Error from Core 1.0000_0000_0000_0011 0003H Write Exclusive Error from Core 0.0000_0000_0000_0100 0004H Write Exclusive Error from Core 1.0000_0000_0000_0101 0005H Inclusion Error from FSB.0000_0000_0000_0110 0006H SNP Stall Error from FSB.0000_0000_0000_0111 0007H Write Stall Error from FSB.0000_0000_0000_1000 0008H FSB Arb Timeout Error.0000_0000_0000_1010 000AH Inclusion Error from Core 2.0000_0000_0000_1011 000BH Write Exclusive Error from Core 2.0000_0010_0000_0000 0200H Internal Timeout Error.0000_0011_0000_0000 0300H Internal Timeout Error.0000_0100_0000_0000 0400H Intel® Cache Safe Technology Queue Full Error or Disabled-ways-in-a-set overflow.0000_0101_0000_0000 0500H Quiet cycle Timeout Error (correctable).1100_0000_0000_0010 C002H Correctable ECC event on outgoing Core 0 data.1100_0000_0000_0100 C004H Correctable ECC event on outgoing Core 1 data.1100_0000_0000_1000 C008H Correctable ECC event on outgoing Core 2 data.1110_0000_0000_0010 E002H Uncorrectable ECC error on outgoing Core 0 data.1110_0000_0000_0100 E004H Uncorrectable ECC error on outgoing Core 1 data.1110_0000_0000_1000 E008H Uncorrectable ECC error on outgoing Core 2 data. — All other encodings — Reserved17-8 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.3.1  Intel® QPI Machine Check Errors
Table 17-8.  Intel® QPI Machine Check Error Codes for IA32_MC0_STATUS and IA32_MC1_STATUS
MCA Error Codes1 
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD Bus error format: 1PPTRRRRIILL
Model Specific Errors 16 Header Parity If 1, QPI Header had bad parity.
17 Data Parity If 1, QPI Data packet had bad parity.
18 Retries Exceeded If 1, the number of QPI retries was exceeded.19 Received Poison if 1, received  a data packet that was marked  as poisoned by the sender.
21:20 Reserved Reserved22 Unsupported Message If 1, QPI received a message encoding it does not support.23 Unsupported Credit If 1, QPI credit type is not supported.
24 Receive Flit Overrun If 1, sender sent  too many QPI flits to the receiver.
25 Received Failed Response If 1,  indicates that send er sent a failed response to receiver.
26 Receiver Clock Jitter If 1, clock jitter detected in the internal QPI clocking.
56:27 Reserved Reserved
Validity Indicators1 63:57
Table 17-9.  Intel® QPI Machine Check Erro r Codes for IA32_MC0_MISC and IA32_MC1_MISC
Errors1
NOTES:
1. Which of these fields are valid depends on the error type.7:0 QPI Opcode Message class and opcode  from the packet with the error.
13:8 RTID QPI Request Transaction ID.
15:14 Reserved Reserved18:16 RHNID QPI Requestor/Home Node ID.23:19 Reserved Reserved24 IIB QPI Interleave/H ead Indication Bit.Vol. 3B 17-9INTERPRETING MACHINE CHECK ERROR CODES
17.3.2  Internal Machine Check Errors
17.3.3  Memory Controller ErrorsTable 17-10.  Machine Check Error Codes for IA32_MC7_STATUS
Type Bit No. Bit Functi on Bit Description
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD
Model Specific Errors 23:16 Reserved Reserved
31:24 Reserved, except for the 
following00H: No error.
03H: Reset firmware  did not complete.
08H: Received an invalid CMPD.
0AH: Invalid Power Management Request.
0DH: Invalid S-state transition.11H: VID controller does not match POC controller selected.
1AH: MSID from POC does not match CPU MSID.
56:32 Reserved Reserved
Table 17-11.  Incremental Memory Controller Er ror Codes of Machine Check for IA32_MC8_STATUS
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD Memory error format: 1MMMCCCC
Model Specific Errors 16 Read ECC Error If 1, ECC occurred on a read.
17 RAS ECC Error If 1, ECC occurred on a scrub.18 Write Parity Error If 1, bad parity on a write.19 Redundancy Loss if 1, error in half of redundant memory.20 Reserved Reserved21 Memory Range Error If 1, me mory access out of range.
22 RTID Out of Range If 1, Internal ID invalid.
23 Address Parity Error If 1, bad address parity.
24 Byte Enable Parity 
ErrorIf 1, bad enable parity.
Other Information 37:25 Reserved Reserved
52:38 CORE_ERR_CNT Corrected error count.56:53 Reserved Reserved
Status Register Validity 
Indicators1 63:5717-10 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.4 INCREMENTAL DECODING INFORMAT ION: INTEL® XEON® PROCESSOR E5 
Table 17-13 through Table 17-15 provide information for inte rpreting additional model-specific fields for memory 
controller errors relating to the Intel® Xeon® processor E5 Family with CPUI D DisplayFamily_DisplaySignature 
06_2DH, which supports Intel QuickPath Interconnect links . Incremental MC error codes related to the Intel QPI 
links are reported in the register banks IA32_MC6 an d IA32_MC7, incremental error codes for internal machine 
check error from PCU controller are reported in the regi ster bank IA32_MC4, and incremental error codes for the 
memory controller unit are reported  in the register banks IA32_MC8 —IA32_MC11.
17.4.1  Internal Machine Check ErrorsTable 17-12.  Incremental Memory Controller E rror Codes of Machine Check for IA32_MC8_MISC
Errors1
NOTES:
1. Which of these fields are valid depends on the error type.7:0 RTID Transaction Tracker ID.
15:8 Reserved Reserved
17:16 DIMM DIMM ID which received the error.19:18 Channel Channel ID which received the error.31:20 Reserved Reserved63:32 Syndrome ECC Syndrome.
Table 17-13.  Machine Check Error Codes for IA32_MC4_STATUS
MCA Error Codes1 15:0 MCACOD
Model Specific Errors 19:16 Reserved, except for the 
following0000b: No Error
0001b: Non_IMem_Sel
0010b: I_Parity_Error0011b: Bad_OpCode
0100b: I_Stack_Underflow
0101b: I_Stack_Overflow0110b: D_Stack_Underflow
0111b: D_Stack_Overflow
1000b: Non-DMem_Sel1001b: D_Parity_ErrorVol. 3B 17-11INTERPRETING MACHINE CHECK ERROR CODES
17.4.2  Intel® QPI Machine Check Errors
17.4.3  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory  controllers are reported in the IA32_MC8_STATUS −
IA32_MC11_STATUS MSRs. The supported error codes fo llow the architectural MCACOD definition type 
1MMMCCCC ; see Chapter 16, “Machine-Check Architecture.” MS R_ERROR_CONTROL.[bit 1] can enable additional 
information logging of the IMC. The additional error in formation logged by the IMC is stored in the IA32_M-
Ci_STATUS and IA32_MCi_MISC, where i = 8, 11.23:20 Reserved Reserved
following00H: No Error
0DH: MC_IMC_FORCE_SR_S3_TIMEOUT
0EH: MC_CPD_UNCPD_ST_TIMEOUT
0FH: MC_PKGS_SAFE_WP_TIMEOUT43H: MC_PECI_MAILBOX_QUIESCE_TIMEOUT
5CH: MC_MORE_TH AN_ONE_LT_AGENT
60H: MC_INVALID_PKGS_REQ_PCH61H: MC_INVALID_PKGS_REQ_QPI
62H: MC_INVALID_PKGS_RES_QPI
63H: MC_INVALID_PKGC_RES_PCH
64H: MC_INVALID_PKG_STATE_CONFIG
70H: MC_WATCHDG_TIMEOUT_PKGC_SECONDARY71H: MC_WATCHDG_TIMEOUT_PKGC_MAIN
72H: MC_WATCHDG_TIMEOUT_PKGS_MAIN
7AH: MC_HA_FAILST S_CHANGE_DETECTED
81H: MC_RECOVERABLE _DIE_THERMAL_TOO_HOT
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.
Table 17-14.  Intel® QPI MC Error Codes for IA32_MC6_STATUS and IA32_MC7_STATUS
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD Bus error format: 1PPTRRRRIILL
Model Specific Errors 56:16 Reserved Reserved
Validity Indicators1 63:57Table 17-13.  Machine Check Error Codes for IA32_MC4_STATUS (Contd.)
Type Bit No. Bit Functi on Bit Description17-12 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
Table 17-15.  Intel IMC MC Error Co des for IA32_MCi_STATUS (i= 8, 11)
NOTES:
Model Specific Errors 31:16 Reserved, except for the 
following001H: Address parity error.
002H: HA Wrt buffer Data parity error.
004H: HA Wrt byte en able parity error.

NOTES:
NOTES:
008H: Corrected patrol scrub error.010H: Uncorrected patrol scrub error.
020H: Corrected spare error.
040H: Uncorrected spare error.
36:32 Other Info When MSR_ERROR_CONTROL.[1] is  set, allows the iMC to log first device 
error when corrected error is detected during normal read.
37 Reserved Reserved
56:38 See Chapter 16, “Mac hine-Check Architecture.”
Table 17-16.  Intel IMC MC Error Codes for IA32_MCi_MISC (i= 8, 11) 
MCA Addr Info1 
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.8:0 See Chapter 16, “Machine-Check Architecture.”
Model Specific Errors 13:9 • When MSR_ERROR_CONTRO L.[1] is set, allows the iMC to log second 
device error when corrected error is detected during normal read.
• Otherwise, contains parity error if  MCi_Status indicates HA_WB_Data 
or HA_W_BE parity error.
29:14 ErrMask_1stErrDev When MSR_ERROR_CONTROL.[1] is set, allows the iM C to log first-device 
error bit mask.
45:30 ErrMask_2ndErrDev When MSR_ERROR_CONTROL. [1] is set, allows th e iMC to log second-
device error bit mask.
50:46 FailRank_1stErrDev When MSR_ER ROR_CONTROL.[1] is set, allows  the iMC to log first-device 
error failing rank.
55:51 FailRank_2ndErrDev When MSR_ERROR_CONTROL. [1] is set, allows th e iMC to log second-
device error failing rank.
58:56 Reserved Reserved61:59 Reserved Reserved62 Valid_1stErrDev When MSR_ERROR_CONTROL.[1] is  set, indicates the iMC has logged valid 
data from the first correctable error in a memory device.
63 Valid_2ndErrDev When MSR_ERROR_CONTROL.[1] is  set, indicates the iMC has logged valid 
data due to a second correctable er ror in a memory device. Use this 
information only after there is valid first error information indicated by bit 
62.Vol. 3B 17-13INTERPRETING MACHINE CHECK ERROR CODES
17.5 INCREMENTAL DECODING INFORMAT ION: INTEL® XEON ® PROCESSOR E5 
V2 AND INTEL® XEON® PROCESSOR E7 V2 FAMILIES, MACHINE ERROR 
CODES FOR MACHINE CHECK
The Intel® Xeon® processor E5 v2 family and the Intel® Xeon® processor E7 v2 family are based on the Ivy 
Bridge-EP microarchitecture and can be identified with  CPUID DisplayFamily_DisplaySignature 06_3EH. Incre-
mental error codes for internal machine check error from the PCU controller is reported in the register bank 
IA32_MC4; Table 17-17 lists model-specific fields to inte rpret error codes applicable to IA32_MC4_STATUS. Incre-
mental MC error codes related to the Intel QPI links are reported in the register bank IA32_MC5. Information listed 
in Table 17-14 for QPI MC error codes apply to IA32 _MC5_STATUS. Incremental error codes for the memory 
controller unit are reported in  the register banks IA32_MC9 −IA32_MC16. Table 17-18 lists model-specific error 
codes that apply to IA32_MCi_STATUS, where i = 9-16.
17.5.1  Internal Machine Check Errors
Table 17-17.  Machine Check Error Codes for IA32_MC4_STATUS 
0010b: I_Parity_Error
0011b: Bad_OpCode0100b: I_Stack_Underflow
0101b: I_Stack_Overflow
0110b: D_Stack_Underflow0111b: D_Stack_Overflow
1000b: Non-DMem_Sel
1001b: D_Parity_Error
23:20 Reserved Reserved31:24 Reserved, except for the 
44H: MC_CRITICAL_VR_FAILED
45H: MC_ICC_MAX-NOTSUPPORTED5CH: MC_MORE_TH AN_ONE_LT_AGENT
60H: MC_INVALID_PKGS_REQ_PCH
61H: MC_INVALID_PKGS_REQ_QPI62H: MC_INVALID_PKGS_RES_QPI
64H: MC_INVALID_PKG_STATE_CONFIG70H: MC_WATCHDG_TIMEOUT_PKGC_SECONDARY
71H: MC_WATCHDG_TIMEOUT_PKGC_MAIN
72H: MC_WATCHDG_TIMEOUT_PKGS_MAIN17-14 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.5.2  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory  controllers are reported in the IA32_MC9_STATUS −
IA32_MC16_STATUS MSRs. The supported error codes fo llow the architectural MCACOD definition type 
1MMMCCCC ; see Chapter 16, “Machine-Check Architecture.”
MSR_ERROR_CONTROL.[bit 1] can enable additional inform ation logging of the IMC. The additional error informa-
tion logged by the IMC is stored in IA32 _MCi_STATUS and IA32_MCi_MISC, where i = 9 —16.
IA32_MCi_STATUS (i=9 —12) logs errors from the first memory controller. The second memory controller logs 
errors into IA32_MCi_STATUS (i=13 —16).7AH: MC_HA_FAILSTS_CHANGE_DETECTED
7BH: MC_PCIE_R2PCIE-RW_BLOCK_ACK_TIMEOUT
81H: MC_RECOVERABLE_D IE_THERMAL_TOO_HOT
NOTES:
Table 17-18.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9—16)
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD Memory Controller error fo rmat: 000F 0000 1MMM CCCC
002H: HA Wrt buffer data parity error.
008H: Corrected patrol scrub error.
010H: Uncorrected patrol scrub error.
040H: Uncorrected spare error.080H: Corrected memory read error. (Only applicable with iMC’s 
“Additional Error logging” Mode-1 enabled.) 
100H - iMC, WDB, parity errors
36:32 Other Info When MSR_ERROR_CONTROL.[1] is set, logs an en coded value from the 
first error device.
37 Reserved Reserved56:38 See Chapter 16, “Mac hine-Check Architecture.”
Validity Indicators1 63:57Table 17-17.  Machine Check Error Codes for IA32_MC4_STATUS  (Contd.)
Type Bit No. Bit Function Bit DescriptionVol. 3B 17-15INTERPRETING MACHINE CHECK ERROR CODES
17.5.3  Home Agent Machine Check Errors
Memory errors from the first memory controller may be  logged in the IA32_MC7_{STATUS,ADDR,MISC} registers, 
while the second memory controller logs errors  to the IA32_MC8_{STATUS,ADDR,MISC} registers.
17.6 INCREMENTAL DECODING INFORMAT ION: INTEL® XEON ® PROCESSOR E5 
V3 FAMILY, MACHINE ERROR CODES FOR MACHINE CHECK
The Intel® Xeon® processor E5 v3 family is based on the Haswell-E microarchitecture and can be identified with 
CPUID DisplayFamily_DisplaySignature 06_3FH. Incrementa l error codes for internal machine check errors from 
the PCU controller are reported in the re gister bank IA32_MC4. Table 17-20 lists model-specific fields to interpret 
error codes applicable to IA32_MC4_STATUS. Incrementa l MC error codes related to the Intel QPI links are 
reported in the register banks IA32_MC5, IA32_MC20, and IA32_MC21. Table 17-21 contains information for QPI 
MC error codes. Incremental error codes for the memory  controller unit are reported in the register banks 
IA32_MC9 −IA32_MC16. Table 17-22 lists model-specific error codes that apply to IA32_MCi_STATUS, where i = 
9—16.Table 17-19.  Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9—16)
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.8:0 See Chapter 16, “Machine-Check Architecture.”
Model Specific Errors 13:9 If the error logged is a MCWrDataPar error or a MCWrBEPar error, this field 
is the WDB ID that has the parity error;  OR if the second error logged is a 
correctable read error, MC logs the second error device in this field.
45:30 ErrMask_2ndErrDev When MSR_ERROR_CONTROL.[1 ] is set, allows the iMC to log second-
50:46 FailRank_1stErrDev When MSR_ERROR_CONTROL.[1] is set, allows the iM C to log first-device 
55:51 FailRank_2ndErrDev When MSR_ERROR_CONTROL. [1] is set, allows the iMC to log second-
61:56 Reserved62 Valid_1stErrDev When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid 
data from a correctable error from memory read associated with first 
error device.
63 Valid_2ndErrDev When MSR_ERROR_CONTROL.[1] is set, indicates the iMC has logged valid 
data due to a second correctable error in a memory device. Use this 
information only after there is valid first error info indicated by bit 62.17-16 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.6.1  Internal Machine Check Errors
Table 17-20.  Machine Check Error Codes for IA32_MC4_STATUS 
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD
MCACOD2

NOTES:
MCACOD2
2. The internal error codes may be model-specific.15:0 Internal Errors 0402H: PCU internal errors.
0403H: PCU internal errors.0406H: Intel TXT errors
0407H: Other UBOX internal errors.
An IERR caused by a core 3-strike the IA32_MC3_STATUS (MLC) is copied 
to the IA32_MC4_STATUS. After a 3-strike, the core MCA banks will be 
unavailable. 
following0000b: No error.
00xxb: PCU internal error.
09H: MC_MESSAGE_CHANNEL_TIMEOUT
13H: MC_DMI_TRAINING_TIMEOUT15H: MC_DMI_CPU_R ESET_ACK_TIMEOUT
1EH: MC_VR_ICC_MAX_LT_FUSED_ICC_MAX
25H: MC_SVID_COMMAND_TIMEOUT29H: MC_VR_VOUT_MAC_LT_FUSED_SVID
2BH: MC_PKGC_WATCHDOG_HANG_CBZ_DOWN
2CH: MC_PKGC_WATCHDOG_HANG_CBZ_UP44H: MC_CRITICAL_VR_FAILED
46H: MC_VID_RAMP_DOWN_FAILED
49H: MC_SVID_WRITE_REG_VOUT_MAX_FAILED4BH: MC_BOOT_VID_TIMEOUT; timeou t setting boot VID for DRAM 0.
4FH: MC_SVID_COMMAND_ERROR
52H: MC_FIVR_CATA S_OVERVOL_FAULT
53H: MC_FIVR_CATAS_OVERCUR_FAULT
57H: MC_SVID_PKGC_REQUEST_FAILED
58H: MC_SVID_IMON_REQUEST_FAILED
59H: MC_SVID_ALERT_REQUEST_FAILED62H: MC_INVALID_PKGS_RSP_QPI
67H: MC_HA_IMC_RW_BLOCK_ACK_TIMEOUT6AH: MC_MSGCH_PMREQ_CMP_TIMEOUT
72H: MC_WATCHDG_TIM EOUT_PKGS_MASTER
Validity Indicators1 63:57Vol. 3B 17-17INTERPRETING MACHINE CHECK ERROR CODES
17.6.2  Intel® QPI Machine Check Errors
MC error codes associated with the Intel QPI agents are reported in the IA32_MC5_STATUS, IA32_MC20_STATUS, 
and IA32_MC21_STATUS MSRs. The supported error codes follow the architectural MCACOD definition type 
1PPTRRRRIILL ; see Chapter 16, “Machine-Check Architecture.”
Table 17-21 lists model-specific fields to interpret error codes applicable to IA32_MC5_STATUS, 
IA32_MC20_STATUS, and IA32_MC21_STATUS.
17.6.3  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the IA32_MC9_STATUS —IA32_MC16_STATUS MSRs. The supported error codes follow the architectural MCACOD defi-
nition type 1MMMCCCC ; see Chapter 16, “Machine-Check Architecture.” 
IA32_MCi_STATUS (i=9 —12) logs errors from the first memory cont roller. The second memory controller logs 
errors into IA32_MCi_STATUS (i=13 —16).Table 17-21.  Intel® QPI MC Error Codes for IA32_MCi_STATUS (i = 5, 20, 21)
NOTES:
Model Specific Errors 31:16 MSCOD 02H: Intel QPI physical layer detected drift buffer alarm.
03H: Intel QPI physical layer de tected latency buffer rollover.
10H: Intel QPI link layer dete cted control error from R3QPI.
11H: Rx entered LLR abort state on CRC error.
12H: Unsupported or undefined packet.
13H: Intel QPI link layer control error.
15H: RBT used un-initialized value.
20H: Intel QPI physical layer detected a QPI in-band reset but aborted 
21H: Link failover data self-healing.
22H: Phy detected in-band reset (no width change).
23H: Link failover clock failover.30H: Rx detected CRC error; successful LLR after Phy re-init.
31H: Rx detected CRC error; su ccessful LLR without Phy re-init.
37:32 Reserved Reserved52:38 Corrected Error Cnt56:53 Reserved Reserved
Validity Indicators1 63:5717-18 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
Table 17-22.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9—16) 
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD Memory Controller error fo rmat: 0000 0000 1MMM CCCC
Model Specific Errors 31:1 6 Reserved, except for 
the following0001H: DDR3 address parity error.
0002H: Uncorrected HA write data error.
0004H: Uncorrected HA da ta byte enable error.
0008H: Corrected patrol scrub error.
0010H: Uncorrected patrol scrub error.0020H: Corrected spare error.
0040H: Uncorrected spare error.
0080H: Corrected memory read error. (Only applicable with iMC’s “Additional 
Error logging” Mode-1 enabled.) 
0100H: iMC, write data buffer parity errors.
0200H: DDR4 command address parity error.
36:32 Other Info When MSR_ERROR_CONTROL.[1] is set, logs an encoded value from the first 
37 Reserved Reserved56:38 See Chapter 16, “Machine-Check Architecture.”
Table 17-23.  Intel IMC MC Error Codes for IA32_MCi_MISC (i= 9—16)
NOTES:
Model Specific Errors 13:9 If the error logged is an MC WrDataPar error or an MCWrBEPar error, this field 
45:30 ErrMask_2ndErrDev When MSR_ER ROR_CONTROL.[1] is set, allows  the iMC to log second-device 
55:51 FailRank_2ndErrDev When MSR_ERROR_CONTROL.[1] is set, allows the iM C to log second-device 
61:56 Reserved Reserved62 Valid_1stErrDev When MSR_ERROR_CONTROL.[1] is  set, indicates the iMC has logged valid 
data from a correctable error from a memory read associated with first error 
device.
information only after there is valid firs t error information indicated by bit 62.Vol. 3B 17-19INTERPRETING MACHINE CHECK ERROR CODES
17.6.4  Home Agent Machine Check Errors
while the second memory controller logs errors  in the IA32_MC8_{STATUS,ADDR,MISC} registers.
17.7 INCREMENTAL DECODING INFORM ATION: INTEL® XEON® PROCESSOR D 
The Intel® Xeon® processor D family is based on the Broadwell microarchitecture and can be identified with CPUID 
DisplayFamily_DisplaySignature 06_56H. Incremental error codes for internal machine check error from the PCU 
controller are reported in the register bank IA32_MC4. Ta ble 17-24 lists model-specific fields to interpret error 
codes applicable to IA32_MC4_STATUS. Incremental error co des for the memory controller unit are reported in the 
register banks IA32_MC9 −IA32_MC10. Table 17-18 lists model-specific error codes that apply to IA32_M-
Ci_STATUS, where i = 9 —10.
17.7.1  Internal Machine Check Errors
Table 17-24.  Machine Check Error Codes for IA32_MC4_STATUS 
MCACOD215:0 Internal Errors 0402H: PCU internal errors.
0403H: Internal errors.
0406H: Intel TXT errors.
0407H: Other UBOX internal errors.On an IERR caused by a core 3-st rike, the IA32_MC3_STATUS (MLC) is 
copied to the IA32_MC4_ST ATUS. After a 3-strike, the core MCA banks will 
be unavailable. 
00x1b: PCU internal error.
001xb: PCU internal error.
23:20 Reserved, except for the 
followingx1xxb: UBOX error.
13H: MC_DMI_TRAINING_TIMEOUT
15H: MC_DMI_CPU_R ESET_ACK_TIMEOUT
25H: MC_SVID_COMMAND_TIMEOUT
26H: MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT29H: MC_VR_VOUT_MAC_LT_FUSED_SVID
49H: MC_SVID_WRITE_REG_VOUT_MAX_FAILED17-20 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.7.2  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated  memory controllers are reported in the 
IA32_MC9_STATUS —IA32_MC10_STATUS MSRs. The supported error co des follow the architectural MCACOD defi-
tion logged by the IMC is stored in IA32 _MCi_STATUS and IA32_MCi_MISC, where i = 9 —10.4BH: MC_PP1_BOOT_VID_TI MEOUT. Timeout setting boot VID for DRAM 0.

4FH: MC_SVID_COMMAND_ERROR.
52H: MC_FIVR_CATAS_OVERVOL_FAULT.
53H: MC_FIVR_CATAS_OVERCUR_FAULT.57H: MC_SVID_PKGC_REQUEST_FAILED
NOTES:
2. The internal error codes may be model-specific.
Table 17-25.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9—10)
MCA Error Codes1 15:0 MCACOD Memory Controller error fo rmat: 0000 0000 1MMM CCCC
following0001H: DDR3 address parity error.
0010H: Uncorrected patrol scrub error.
36:32 Other Info Reserved37 Reserved Reserved56:38 See Chapter 16, “Mac hine-Check Architecture.”
Validity Indicators1 63:57Table 17-24.  Machine Check Error Codes for IA32_MC4_STATUS  (Contd.)
Type Bit No. Bit Function Bit DescriptionVol. 3B 17-21INTERPRETING MACHINE CHECK ERROR CODES
17.8 INCREMENTAL DECODING INFORMAT ION: INTEL® XEON ® PROCESSOR E5 
V4 FAMILY, MACHINE ERROR CODES FOR MACHINE CHECK
The Intel® Xeon® processor E5 v4 family is based on the Broadwell microarchitecture and can be identified with 
CPUID DisplayFamily_DisplaySignature 06_4FH. Incrementa l error codes for internal machine check errors from 
the PCU controller are reported in the register bank IA32 _MC4. Table 17-20 in Section 17.6.1 lists model-specific 
fields to interpret error codes applicable to IA32_MC4_STATUS. 
Incremental MC error codes related to the Intel QPI links are reported in the register banks IA32_MC5, 
IA32_MC20, and IA32_MC21. Information listed in Table 17-21 of Section 17.6.1 covers QPI MC error codes. 
17.8.1  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the 
IA32_MC9_STATUS —IA32_MC16_STATUS MSRs. The supported error codes follow the architectural MCACOD defi-
nition type 1MMMCCCC ; see Chapter 16, “Machine-Check Architecture.”
Table 17-26 lists model-specific error codes that apply to IA32_MCi_STATUS, where i = 9 —16.
errors into IA32_MCi_STATUS (i=13 —16).
17.8.2  Home Agent Machine Check Errors
MC error codes associated with mirrored memory co rrections are reported in the IA32_MC7_MISC and 
IA32_MC8_MISC MSRs. Table 17-27 lists model-specific error codes that apply to IA32_MCi_MISC, where i = 7, 8.NOTES:
Table 17-26.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 9—16)
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD Memory Controller error format: 0000 0000 1MMM CCCC
0004H: Uncorrected HA data byte enable error.
0020H: Corrected spare error.0040H: Uncorrected spare error.
36:32 Other Info Reserved37 Reserved Reserved56:38 See Chapter 16, “Machine-Check Architecture.”
Validity Indicators1 63:5717-22 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.9 INCREMENTAL DECODING INFORM ATION: INTEL® XEON® SCALABLE 
PROCESSOR FAMILY, MACHINE ER ROR CODES FOR MACHINE CHECK
In the Intel® Xeon® Scalable Processor Family with CPUID Disp layFamily_DisplaySignature 06_55H, incremental 
error codes for internal machine check errors from the PC U controller are reported in the register bank IA32_MC4. 
Table 17-28 in Section 17.9.1 lists model-specific fields to interpret error codes applicable to IA32_MC4_STATUS. 
17.9.1  Internal Machine Check ErrorsTable 17-27.  Intel HA MC Error Codes for IA32_MCi_MISC (i= 7, 8)
Bit No. Bit Function Bit Description
5:0 LSB See Figure 16-8.8:6 Address Mode See Table 16-3.40:9 Reserved Reserved41 Failover Error occurred at a pair of mirrored memo ry channels. Error was corr ected by mirroring with 
channel failover.
42 Mirrorcorr Error was corrected by mirroring and primary channel scrubbed successfully.63:43 Reserved Reserved
Table 17-28.  Machine Check Error Codes for IA32_MC4_STATUS
0403H: PCU internal errors.0406H: Intel TXT errors.
On an IERR caused by a core 3-strike, the IA32_MC3_STATUS (MLC) is 
copied to the IA32_MC4_STATUS. Afte r a 3-strike, the core MCA banks will 
00xxb: PCU internal error.Vol. 3B 17-23INTERPRETING MACHINE CHECK ERROR CODES
23:20 Reserved Reserved
0DH: MCA_DMI_TRAINING_TIMEOUT 
0FH: MCA_DMI_CPU_ RESET_ACK_TIMEOUT
10H: MCA_MORE_THAN_ONE_LT_AGENT1EH: MCA_BIOS_RST_CPL_INVALID_SEQ
1FH: MCA_BIOS_INVAL ID_PKG_STATE_CONFIG
25H: MCA_MESSAGE_CHANNEL_TIMEOUT27H: MCA_MSGCH_PMREQ_CMP_TIMEOUT
30H: MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT
31H: MCA_PKGC_INVALID_RSP_PCH
33H: MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN
34H: MCA_PKGC_WATCHDOG_HANG_CBZ_UP38H: MCA_PKGC_WATCH DOG_HANG_C3_UP_SF
40H: MCA_SVID_VCCIN _VR_ICC_MAX_FAILURE
41H: MCA_SVID_COMMAND_TIMEOUT42H: MCA_SVID_VCCIN_VR_VOUT_MAX_FAILURE
43H: MCA_SVID_CPU_VR_CAPABILITY_ERROR
44H: MCA_SVID_CRITICAL_VR_FAILED45H: MCA_SVID_SA_ITD_ERROR
46H: MCA_SVID_READ_REG_FAILED
47H: MCA_SVID_WRITE_REG_FAILED48H: MCA_SVID_PKGC_INIT_FAILED
49H: MCA_SVID_PKGC_CONFIG_FAILED
4AH: MCA_SVID_PKGC_REQUEST_FAILED
4BH: MCA_SVID_IMON_REQUEST_FAILED4CH: MCA_SVID_ALERT_REQUEST_FAILED
4DH: MCA_SVID_MCP_VP_ ABSENT_OR_RAMP_ERROR
4EH: MCA_SVID_UNEXPECTED_MCP_VP_DETECTED51H: MCA_FIVR_CAT AS_OVERVOL_FAULT
52H: MCA_FIVR_CATAS_OVERCUR_FAULT
58H: MCA_WATCHDG_TIMEOUT_PKGC_SECONDARY59H: MCA_WATCHDG_TIMEOUT_PKGC_MAIN
5AH: MCA_WATCHDG_TIMEOUT_PKGS_MAIN
61H: MCA_PKGS_CPD_UNPCD_TIMEOUT63H: MCA_PKGS_INVALID_REQ_PCH
64H: MCA_PKGS_INVALID_REQ_INTERNAL
65H: MCA_PKGS_INVALID_RSP_INTERNAL6BH: MCA_PKGS_SMBUS _VPP_PAUSE_TIMEOUT
52:32 Reserved Reserved54:53 CORR_ERR_STATUS ReservedTable 17-28.  Machine Check Error Codes for IA32_MC4_STATUS
Type Bit No. Bit Functi on Bit Description17-24 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.9.2  Interconnect Machine Check Errors
MC error codes associated with the link interco nnect agents are reported in the IA32_MC5_STATUS, 
IA32_MC12_STATUS, and IA32_MC19_STATUS MSRs. The supp orted error codes follow the architectural MCACOD 
definition type 1PPTRRRRIILL ; see Chapter 16, “Machine-Check Architecture.”
Table 17-29 lists model-specific fields to interpret error codes applicable to IA32_MCi_STATUS, i= 5, 12, 19.56:55 Reserved Reserved
NOTES:
Table 17-29.  Interconnect MC Error Codes for IA32_MCi_STATUS (i = 5, 12, 19)
MCA Error Codes1 15:0 MCACOD Bus error format: 1PPTRRRRIILL
The two supported compound error codes:• 0x0C0F: Unsupported/Undefined Packet.
• 0x0E0F: For all other corrected and uncorrected errors.
Model Specific Errors 21:16 MSCOD The encodi ng of Uncorrectable  (UC) errors are:
00H: UC Phy Initialization Failure.
01H: UC Phy detected drift buffer alarm.02H: UC Phy detected latency buffer rollover.
10H: UC link layer Rx detected CRC error: unsuccessful LLR entered abort 
state.
11H: UC LL Rx unsupported or undefined packet.
12H: UC LL or Phy control error.
13H: UC LL Rx parameter exchange exception.1FH: UC LL detected control erro r from the link-mesh interface.
The encoding of correctable (COR) errors are:
20H: COR Phy initialization abort.21H: COR Phy reset.
22H: COR Phy lane failure,  recovery in x8 width.

state.
23H: COR Phy L0c error corrected without Phy reset.24H: COR Phy L0c error triggering Phy reset.
25H: COR Phy L0p exit error corrected with Phy reset.
30H: COR LL Rx detected CRC error; successful LLR without Phy re-init.31H: COR LL Rx detected CRC error; successful LLR with Phy re-init.
All other values are reserved.Table 17-28.  Machine Check Error Codes for IA32_MC4_STATUS
Type Bit No. Bit Function Bit DescriptionVol. 3B 17-25INTERPRETING MACHINE CHECK ERROR CODES
17.9.3  Integrated Memory Controller Machine Check Errors
IA32_MC13_STATUS —IA32_MC18_STATUS MSRs. The supported error codes follow the architectural MCACOD 
definition type 1MMMCCCC ; see Chapter 16, “Machine-Check Architecture.” 
IA32_MCi_STATUS (i=13,14,17) logs errors from the first memory controller. The second memory controller logs 
errors into IA32_MCi_STATUS (i=15,16,18).31:22 MSCOD_SPARE The definition below applies to MSCOD 12h (UC LL or Phy Control Errors)
[Bit 22] : Phy Control Error.
[Bit 23] : Unexpected Retry.Ack flit.
[Bit 24] : Unexpected Retry.Req flit.[Bit 25] : RF parity error.
[Bit 26] : Routeback Table error.
[Bit 27] : Unexpected Tx Protoc ol flit (EOP, Header or Data).
[Bit 28] : Rx Header-or-Credit BGF credit overflow/underflow.
[Bit 29] : Link Layer Reset still in  progress when Phy enters L0 (Phy 
training should not be enabled until af ter LL reset is comp lete as indicated 
by KTILCL.LinkLayerReset going back to 0).
[Bit 30] : Link Layer reset initiated while protocol traffic not idle.
[Bit 31] : Link Layer Tx Parity Error.
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.Table 17-29.  Interconnect  MC Error Codes for IA32_MCi_STATUS (i = 5, 12, 19)
Type Bit No. Bit Functi on Bit Description17-26 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.9.4  M2M Machine Check Errors
MC error codes associated with M2M are reported in the IA32_MC7_STATUS and IA32_MC8_STATUS MSRs. The 
supported error codes follow the arch itectural MCACOD definition type 1MMMCCCC ; see Chapter 16, “Machine-
Check Architecture.” Table 17-30.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 13—18)
NOTES:
following0001H: Address parity error.
0002H: HA write data parity error.
0004H: HA write byte enable parity error.
0008H: Corrected patrol scrub error.0010H: Uncorrected patrol scrub error.
0020H: Corrected spare error.
0040H: Uncorrected spare error.0080H: Any HA read error.
0100H: WDB read parity error.
0400H: Uncorrected address parity error.
0800H: Unrecognized request type.0801H: Read response to an  invalid scoreboard entry.
0802H: Unexpected read response.
0803H: DDR4 completion to an invalid scoreboard entry.0804H: Completion to an invalid scoreboard entry.
0805H: Completion FIFO overflow.
0806H: Correctable parity error.0807H: Uncorrectable error.
0808H: Interrupt received while outstanding interrupt was not ACKed.
0809H: ERID FIFO overflow.080AH: Error on Write credits.
080BH: Error on Read credits.
080CH: Scheduler error.080DH: Error event.
36:32 Other Info MC logs the first error device. This is an encoded 5-bit value of the device.
Validity Indicators1 63:57Vol. 3B 17-27INTERPRETING MACHINE CHECK ERROR CODES
17.9.5  Home Agent Machine Check Errors
IA32_MC8_MISC MSRs. Table 17-32 lists model-specific erro r codes that apply to IA32_MCi_MISC, where i = 7, 8. 
while the second memory controller logs errors  in the IA32_MC8_{STATUS,ADDR,MISC} registers.Table 17-31.  M2M MC Error Code s for IA32_MCi_STATUS (i= 7, 8)
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD Compound error format: 0000 0000 1MMM CCCC
Model Specific Errors 16 MscodDataRdErr Logged an MC read data error.
17 Reserved Reserved18 MscodPtlWrErr Logged an MC partial write data error.19 MscodFullWrErr Logged a full write data error.20 MscodBgfErr Logged an M2M clock-domain-crossing buffer (BGF) error.21 MscodTimeOut Logged an M2M time out.22 MscodParErr Logged an M2M tracker parity error.23 MscodBucket1Err Logged a fatal Bucket1 error.31:24 Reserved Reserved36:32 Other Info MC logs the first error device. Th is is an encoded 5-bit value of the device.
Table 17-32.  Intel HA MC Error Codes for IA32_MCi_MISC (i= 7, 8)
5:0 LSB See Figure 16-8.8:6 Address Mode See Table 16-3.40:9 Reserved Reserved61:41 Reserved Reserved62 Mirrorcorr Error was corrected by mirroring and primary channel scrubbed successfully.63 Failover Error occurred at a pair of mirrored memo ry channels. Error was corrected by mirroring with 
channel failover.17-28 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.10 INCREMENTAL DECODING INFORMAT ION: PROCESSOR FAMILY WITH CPUID 
DISPLAYFAMILY_DISPLAYMODEL SI GNATURE 06_5FH, MACHINE ERROR 
In Intel Atom® processors based on Goldmont Microarchitecture with CPUID DisplayFamily_DisplaySignature 
06_5FH (Denverton), incremental error codes for the memo ry controller unit are reported in the register banks 
IA32_MC6 and IA32_MC7. Table 17-33 in Section 17.10.1 list s model-specific fields to interpret error codes appli-
cable to IA32_MCi_STATUS, where i = 6, 7.
17.10.1  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers are reported in the IA32_MC6_STATUS and 
IA32_MC7_STATUS MSRs. The supported error codes fo llow the architectural MCACOD definition type 
17.11 INCREMENTAL DECODING INFORMAT ION: 3RD GENERATION INTEL® XEON® 
SCALABLE PROCESSOR FAMILY, MA CHINE ERROR CODES FOR MACHINE 
CHECK
In the 3rd generation Intel® Xeon® Scalable Processor Family with CPUID DisplayFamily_DisplaySignatures of 
06_6AH and 06_6CH, incremental error codes for internal  machine check errors from  the PCU controller are 
reported in the register bank IA32_MC4. Table 17-34 in Sect ion 17.11.1 lists model-specific fields to interpret error 
codes applicable to IA32_MC4_STATUS. Table 17-33.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 6, 7)
NOTES:
following01H: Cmd/Addr parity.
02H: Corrected Demand/Patrol Scrub error.
04H: Uncorrected patrol scrub error.
08H: Uncorrected demand read error.10H: WDB read ECC.
36:32 Other Info37 Reserved Reserved56:38 See Chapter 16, “Mac hine-Check Architecture.”
Validity Indicators1 63:57Vol. 3B 17-29INTERPRETING MACHINE CHECK ERROR CODES
17.11.1  Internal Machine Check Errors
Table 17-34.  Machine Check Error Codes for IA32_MC4_STATUS 
Machine Check Error 
Codes1 15:0 MCCOD
MCCOD 15:0 Internal Errors The value of this field will be 0402H for the PCU and 0406H for internal 
firmware errors.
This applies for any logged error. 
followingModel specific error code bits 19:16.
This logs the type of HW UC (PCU/VCU) error that has occurred. There are 
7 errors defined.
01H: Instruction addres s out of valid space.
02H: Double bit RAM error on Instruction Fetch.
03H: Invalid OpCode seen.
04H: Stack Underflow.05H: Stack Overflow.
06H: Data address out of valid space.
07H: Double bit RAM error on Data Fetch.
followingModel specific error code bits 23:20.
This logs the type of HW FSM error that has occurred. There are 3 errors 
defined.
04H: Clock/power IP response timeout.05H: SMBus controller raised SMI.
09H: PM controller received invalid transaction.
following0DH: MCA_LLC_BIST_ACTIVE_TIMEOUT
0EH: MCA_DMI_TRAINING_TIMEOUT0FH: MCA_DMI_STRAP_SET_ARRIVAL_TIMEOUT
10H: MCA_DMI_CPU_ RESET_ACK_TIMEOUT

defined.
10H: MCA_DMI_CPU_ RESET_ACK_TIMEOUT 
11H: MCA_MORE_THAN_ONE_LT_AGENT14H: MCA_INCOMP ATIBLE_PCH_TYPE 
1EH: MCA_BIOS_RST_CPL_INVALID_SEQ
2DH: MCA_PCU_PMAX_CALIB_ERROR
2EH: MCA_TSC100_SYNC_TIMEOUT
3AH: MCA_GPSB_TIMEOUT3BH: MCA_PMSB_TIMEOUT
3EH: MCA_IOSFSB_PMREQ_CMP_TIMEOUT
42H: MCA_SVID_VCCIN_VR_VOUT_FAILURE
47H: MCA_SVID_WRITE_REG_FAILED4AH: MCA_SVID_PKGC_REQUEST_FAILED17-30 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
4BH: MCA_SVID_IMON_REQUEST_FAILED
4CH: MCA_SVID_ALERT_REQUEST_FAILED
4DH: MCA_SVID_MCP_VR_RAMP_ERROR
56H: MCA_FIVR_PD_HARDERR58H: MCA_WATCHDOG_TIMEOUT_PKGC_SECONDARY 
59H: MCA_WATCHDOG_TIMEOUT_PKGC_MAIN
5AH: MCA_WATCHDOG_TIMEOUT_PKGS_MAIN5BH: MCA_WATCHDOG_TIMEOUT_MSG_CH_FSM 
5CH: MCA_WATCHDOG_TIMEOUT_BULK_CR_FSM
5DH: MCA_WATCHDOG_TIMEOUT_IOSFSB_FSM60H: MCA_PKGS_SAFE_WP_TIMEOUT
61H: MCA_PKGS_CPD_UNCPD_TIMEOUT
62H: MCA_PKGS_INVALID_REQ_PCH
63H: MCA_PKGS_INVALID_REQ_INTERNAL
64H: MCA_PKGS_INVALID_RSP_INTERNAL65H-7AH: MCA_PKGS_RESET_PREP_TIMEOUT
7BH: MCA_PKGS_SMBUS _VPP_PAUSE_TIMEOUT
7CH: MCA_PKGS_SMBUS _MCP_PAUSE_TIMEOUT
7DH: MCA_PKGS_SMBUS_SPD_PAUSE_TIMEOUT
80H: MCA_PKGC_DISP_BUSY_TIMEOUT
81H: MCA_PKGC_INVALID_RSP_PCH83H: MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN
84H: MCA_PKGC_WATCHDOG_HANG_CBZ_UP
87H: MCA_PKGC_WATCHDOG_HANG_C2_BLKMASTER88H: MCA_PKGC_WATCHDOG_HANG_C2_PSLIMIT
89H: MCA_PKGC_WATCHDOG_HANG_SETDISP
8BH: MCA_PKGC_ALLOW_L1_ERROR90H: MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT
A0H: MCA_ADR_SIGNAL_TIMEOUT
A1H: MCA_BCLK_FREQ_OC_ABOVE_THRESHOLDB0H: MCA_DISPATCHER_RUN_BUSY_TIMEOUT
37:32 ENH_MCA_AVAIL0 Available when Enhanced MCA is in use.52:38 CORR_ERR_COUNT Correctable error count.54:53 CORRERRORSTATUSIND These bits are used to indicate when the number of corrected errors has 
exceeded the safe threshold to the point where an uncorrected error has 
become more likely to happen.
Table 3 shows the encoding of these bits.
56:55 ENH_MCA_AVAIL1 Available when Enhanced MCA is in use.
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.Table 17-34.  Machine Check Error Codes for IA32_MC4_STATUS  (Contd.)
Type Bit No. Bit Function Bit DescriptionVol. 3B 17-31INTERPRETING MACHINE CHECK ERROR CODES
17.11.2  Interconnect Machine Check Errors
IA32_MC7_STATUS, and IA32_MC8_STATUS MSRs. The supp orted error codes follow the architectural MCACOD 
NOTE
The interconnect machine check errors in this section apply only to the 3rd generation Intel Xeon 
Scalable Processor Family with a CPUID DisplayFamily_DisplaySignature of 06_6AH. These do not apply to the 3rd generation Intel Xeon Scalable Processor Family with a CPUID 
DisplayFamily_DisplaySignature of 06_6CH.
Table 17-35 lists model-specific fields to interpret erro r codes applicable to IA32_MCi_STATUS, where i= 5, 7, 8.
Table 17-35.  Interconnect MC Error Co des for IA32_MCi_STATUS (i = 5, 7, 8) 
The two supported compound error codes:
• 0x0C0F: Unsupported/Undefined Packet.
Model Specific Errors 21:16 MSCOD The encodi ng of Uncorrectable (UC) errors are:
00H: Phy Initialization Failure (NumInit).01H: Phy Detected Drift Buffer Alarm.
02H: Phy Detected Latency Buffer Rollover.
10H: LL Rx detected CRC error: unsu ccessful LLR (entered Abort state).
11H: LL Rx Unsupported/Undefined packet.
12H: LL or Phy Control Error.
13H: LL Rx Parameter Exception.1FH: LL Detected Control Error.
20H: Phy Initialization Abort.21H: Phy Inband Reset.
22H: Phy Lane failure, recovery in x8 width.
23H: Phy L0c error corrected without Phy reset.24H: Phy L0c error triggering Phy reset.
25H: Phy L0p exit error corrected with reset.
30H: LL Rx detected CRC error: successful LLR without Phy Re-init.31H: LL Rx detected CRC error: successful LLR with Phy Re-init.
32H: Tx received LLR.
All other values are reserved.17-32 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.11.3  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers for the 3rd generation Intel® Xeon® Scalable 
Processor Family based on Ice Lake microarchitecture are defined in Table 17-37.
The MSRs reporting MC error codes differ depending on the CPUID DisplayFamily_DisplaySignature of the 
processor. See Table 17-36 for details.31:22 MSCOD_SPARE The definition below applies to MSCOD 12h (UC LL or Phy Control Errors).
[Bit 27] : Unexpected Tx Protocol flit (EOP, Header or Data).[Bit 28] : Rx Header-or-Credit BGF credit overflow/underflow.
[Bit 29] : Link Layer Reset still in progress when Phy enters L0 (Phy 
training should not be enabled until after LL reset is complete as indicated by KTILCL.LinkLayerReset going back to 0).
37:32 OTHER_INFO Other Info.56:38 Corrected Error Cnt See Chapter 16, “Machine-Check Architecture.”
NOTES:
Table 17-36.  MSRs Reporting MC Error Codes by CPUID DisplayFamily_DisplaySignature
Processor CPUID 
DisplayFamily_Di splaySignature MSRs Reporting MC Error Codes
3rd generation Intel® Xeon® Scalable Processor 
Family based on Ice Lake microarchitecture06_6AH IA32_MC13_STATUS −IA32_MC14_STATUS
IA32_MC17_STATUS −IA32_MC18_STATUS
IA32_MC21_STATUS −IA32_MC22_STATUS
IA32_MC25_STATUS −IA32_MC26_STATUS
Family based on Ice Lake microarchitecture06_6CH IA32_MC13_STATUS −IA32_MC14_STATUS
IA32_MC17_STATUS −IA32_MC18_STATUSTable 17-35.  Interconnect MC Error Codes fo r IA32_MCi_STATUS (i = 5, 7, 8)  (Contd.)
Type Bit No. Bit Function Bit DescriptionVol. 3B 17-33INTERPRETING MACHINE CHECK ERROR CODES
The supported error codes follow the architectural MCACOD definition type 1MMMCCCC ; see Chapter 16, 
“Machine-Check Architecture.” 
Table 17-37.  Intel IMC MC Error Codes for IA32 _MCi_STATUS (i= 13—14, 17—18, 21—22, 25—26) 
MCA Error Codes1 15:0 MCACOD Memory Controller error format: 0000 0000 1MMM CCCC
Model Specific Errors 27:16 Error Codes 0000H: Uncorrectable spare error.
0001H: End to End address parity error.
0002H: Write data parity error.
0003H: End to End uncorrectable/correctable write data ECC error.0004H: Write byte enable parity error.
0007H: Transaction ID parity error.
0008H: Correctable patrol scrub error.0010H: Uncorrectable patrol scrub error.
0020H: Correctable spare error.
0080H: Transient or correctable error for demand or underfill reads or 
read 2LM metadata error.
00A0H: Uncorrectable error for demand or underfill reads.0100H: WDB read parity error.
0108H: DDR/DDRT link failure.
0111H: PCLS address CSR parity error.0112H: PCLS illegal ADDDC configuration error.
0200H: DDR4 command / address parity error.
0400H: RPQ scheduler address parity error.0800H: 2LM unrecognized request type.
0801H: 2LM read response to an invalid scoreboard entry.
0802H: 2LM unexpected read response.0803H: 2LM DDR4 completion to an invalid scoreboard entry.
0804H: 2LM DDRT completion to an invalid scoreboard entry.
0805H: 2LM completion FIFO overflow.0806H: DDRT link parity error.
0807H: DDRT RID uncorrectable error.
0809H: DDRT RID FIFO overflow.080AH: DDRT error on FNV write credits.
080BH: DDRT error on FNV read credits.
080CH: DDRT scheduler error.080DH: DDRT FNV error.
080EH: DDRT FNV thermal error.
080FH: DDRT unexpected data packet during CMI idle.0810H: DDRT RPQ request parity error.
0811H: DDRT WPQ request parity error.
0812H: 2LM NmFillWr CAM multiple hit error.0813H: CMI credit over subscription error.
0814H: CMI total credit count error.
0815H: CMI reserved credit pool error.0816H: DDRT link ECC error.17-34 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
0817H: WDB FIFO overflow  or underflow errors.
0818H: CMI request FIFO overflow error.
0819H: CMI request FIFO underflow error.
081AH: CMI response FIFO overflow error.081BH: CMI response FIFO underflow error.
081CH: CMI miscellaneous credit errors.
081DH: CMI MC arbiter errors.081EH: DDRT write completion  FIFO overflow error.
081FH: DDRT write completion FIFO underflow error.
0820H: CMI read completion FIFO overflow error.0821H: CMI read completion FIFO underflow error.
0822H: TME key RF parity error.

0823H: TME miscellaneous CMI errors.
0824H: TME CMI overflow error.
0825H: TME CMI underflow error.0826H: Intel® SGX TEM secure bit mi smatch detected on demand read.
0827H: TME detected underfill read  completion data  parity error.
0828H: 2LM Scoreboard Overflow Error.1008H: Correctable patrol scrub error (mirror secondary example).
28 Mirror secondary error. Mirror secondary error.31:29 Reserved Reserved37:32 Other Info Other Info.56:38 See Chapter 16, “Mac hine-Check Architecture.”
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.Table 17-37.  Intel IMC MC Error Codes for IA32_MCi _STATUS (i= 13—14, 17—18, 21—22, 25—26)  (Contd.)
Type Bit No. Bit Function Bit DescriptionVol. 3B 17-35INTERPRETING MACHINE CHECK ERROR CODES
Additional information is reported in the IA32_MC13_MISC −IA32_MC14_MISC, IA32_MC17_MISC − 
IA32_MC18_MISC, IA32_MC21_MISC −IA32_MC22_MISC, and IA32_MC25_MISC −IA32_MC26_MISC MSRs. Table 
17-38 lists the information reported in IA32_MCi_MISC, where i = 13 −14, 17 −18, 21 −22, and 25 −26.
Table 17-38.  Additional Information Reported in IA32_MCi_MISC (i= 13—14, 17—18, 21—22, 25—26)
5:0 LSB See Figure 16-8.8:6 Address Mode See Table 16-3.18:9 Column Component of sub-DIMM address.
Bits 18-17: Reserved.
Bit 16: Column 9.Bit 15: Column 8.
Bit 14: Column 7.
Bit 13: Column 6.
Bit 12: Column 5.
Bit 11: Column 4.Bit 10: Column 3.
Bit 9: Reserved.
39:19 Row Component of sub-DIMM address.45:40 Bank Component of sub-DIMM address.
Bit 45: Reserved.Bit 44: Bank group 2.
Bit 43: Bank address 1.
Bit 42: Bank address 0.Bit 41: Bank group 1.
Bit 40: Bank group 0.
51:46 Failed Device Failing device fo r correctable error (not valid for uncorrectable or transient errors).
55:52 CBit CBit58:56 Chip Select Chip Select62:59 ECC Mode 0000b: SDDC 2LM.
0001b: SDDC 1LM.0010b: SDDC + 1 2LM.
0011b: SDDC + 1 1LM.
0100b: ADDDC 2LM.0101b: ADDDC 1LM.
0110b: ADDDC + 1 2LM.
0111b: ADDDC + 1 1LM.1000b: Read from DDRT.
1001b: x8 SDDC.
1010b: x8 SDDC + 1.1011b: Not a valid ECC mode.
Other values: Reserved.
63 Transient 0b:
1b: Error was transient.17-36 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.11.4  M2M Machine Check Errors
MC error codes associated with M2M for the 3rd generati on Intel Xeon Scalable Processor Family with a CPUID 
DisplayFamily_DisplaySignature of 06_6AH are report ed in the IA32_MC12_STATUS, IA32_MC16_STATUS, 
IA32_MC20_STATUS, and IA32_MC24_STATUS MSRs. 
DisplayFamily_DisplaySignature of 06_6CH are report ed in the IA32_MC12_STATUS and IA32_MC16_STATUS 
MSRs. 
The supported error codes follow the ar chitectural MCACOD definition type 1MMMCCCC ; see Chapter 16, 
“Machine-Check Architecture.”
MC error codes associated with mirrored memory corrections are reported in the IA32_MC12_MISC, 
IA32_MC16_MISC, IA32_MC20_MISC, and IA32_MC24_MISC MSRs . The model-specific error codes listed in Table 
17-32 also apply to IA32_MCi_MISC, where i = 12, 16, 20, 24.
17.12 INCREMENTAL DECODING INFORMAT ION: PROCESSOR FAMILY WITH CPUID 
DISPLAYFAMILY_DISPLAYMODEL SI GNATURE 06_86H, MACHINE ERROR 
In Intel Atom® processors based on Tremont microarchitecture with CPUID DisplayFamily_DisplaySignature 
06_86H, incremental error codes for internal machine chec k errors from the PCU controller are reported in the 
register bank IA32_MC4. Table 17-34 in Section 17.11.1 lists model-specific fields to interpret error codes appli-
cable to IA32_MC4_STATUS. 
17.12.1  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory co ntrollers are reported in the MSRs IA32_MC13_STATUS −
IA32_MC15_STATUS. The supported error codes follo w the architectural MCACOD definition type 1MMMCCCC ; see 
Chapter 16, “Machine-Check Architecture.”
The IA32_MCi_STATUS MSR (where i = 13, 14, 15) contains information related to a machine check error if its 
VAL(valid) flag is set. Bit definitions are the same as those found in Table 17-37 “Intel IMC MC Error Codes for 
IA32_MCi_STATUS (i= 13—14, 17—18, 21—22, 25—26).”
The IA32_MCi_MISC MSR (where i = 13, 14, 15) contains information related memory corrections. Bit definitions 
are the same as those found in Tabl e 17-38 “Additional Information Reported in IA32_MCi_MISC (i= 13—14, 
17—18, 21—22, 25—26).”Table 17-39.  M2M MC Error Codes for IA32_MCi_STATUS (i= 12, 16, 20, 24)
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.15:0 MCACOD Compound error format: 0000 0000 1MMM CCCC
Model Specific Errors 23:16 M SCOD Logged an MC error.
25:24 MscodDDRType Logged a DDR/DDRT specific error.
26 MscodFailoverWhileResetPrep Logged a failover  specific error while preparing to reset.
31:27 Reserved Reserved37:32 Other Info Other information.56:38 See Chapter 16, “Machine-Check Architecture.”
Validity Indicators1 63:57Vol. 3B 17-37INTERPRETING MACHINE CHECK ERROR CODES
17.12.2  M2M Machine Check Errors
MC error codes associated with M2M are reported in  the IA32_MC12_STATUS MSR. The supported error codes 
follow the architectural MCACOD definition type 1MMMCCCC ; see Chapter 16, “Machine-Check Architecture.”
Bit definitions are the same as those found in Table 17 -39 “M2M MC Error Codes for IA32_MCi_STATUS (i= 12, 16, 
20, 24).”
17.13 INCREMENTAL DECODING INFORMAT ION: 4TH GENERATION INTEL® XEON® 
CHECK
In the 4th generation Intel® Xeon® Scalable Processor Family with CPUI D DisplayFamily_DisplaySignature of 
06_8FH, incremental error codes for internal machine chec k errors from the PCU controller are reported in the 
register bank IA32_MC4. Table 17-40 in Section 17.13.1 lists model-specific fields to interpret error codes appli-
17.13.1  Internal Machine Check Errors
Table 17-40.  Machine Check Error Codes for IA32_MC4_STATUS 
MCACOD115:0 Internal Errors The value of this field will be 0402H for the PCU and 0406H for internal 
If MACOD = 40CH, MSCOD encoding should be interpreted as:
01H: MCE when CR4.MCE is clear.02H: MCE when MCIP bit is set.
03H: MCE under WPS.
04H: Unrecoverable error during security flow execution.05H: Software triple fault shutdown.
06H: VMX-exit-consist ency-check failures.
07H: RSM-consistency-check failures.08H: Invalid conditions on protected mode SMM entry.
09H: Unrecoverable error during security flow execution.
For all other MACOD values, MSCOD logs the type of hardware UC 
(PCU/VCU) error that has occurred. There are seven errors defined:
03H: Invalid OpCode seen.04H: Stack Underflow.
05H: Stack Overflow.
06H: Data address out of valid space.07H: Double bit RAM error on Data Fetch.17-38 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
defined:
09H: PM controller receiv ed invalid transaction.
10H: MCA_DMI_CPU_RESET_ACK_TIMEOUT 
11H: MCA_MORE_THAN_ONE_LT_AGENT14H: MCA_INCOMPATIBLE_PCH_TYPE 
1EH: MCA_BIOS_RST _CPL_INVALID_SEQ
1FH: MCA_BIOS_INVALID_PKG_STATE_CONFIG
2EH: MCA_TSC100_SYNC_TIMEOUT3AH: MCA_GPSB_TIMEOUT
3BH: MCA_PMSB_TIMEOUT
3EH: MCA_IOSFSB_PMREQ_CMP_TIMEOUT40H: MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE
43H: MCA_SVID_CPU_VR_CAPABILITY_ERROR44H: MCA_SVID_CRITICAL_VR_FAILED
45H: MCA_SVID_SA_ITD_ERROR
46H: MCA_SVID_READ_REG_FAILED47H: MCA_SVID_WRITE_REG_FAILED
62H: MCA_PKGS_INVALID_REQ_PCH63H: MCA_PKGS_INVALID_REQ_INTERNAL
64H: MCA_PKGS_INVALID_RSP_INTERNAL
65H-7AH: MCA_PKGS_RESET_PREP_TIMEOUT7BH: MCA_PKGS_SMBUS _VPP_PAUSE_TIMEOUTTable 17-40.  Machine Check Error Codes for IA32_MC4_STATUS  (Contd.)

Type Bit No. Bit Function Bit DescriptionVol. 3B 17-39INTERPRETING MACHINE CHECK ERROR CODES
17.13.2  Interconnect Machine Check Errors
MC error codes associated with the link interconnect agents are reported in the IA32_MC5_STATUS MSR. The 
supported error codes follow the architectural MCACOD definition type 1PPTRRRRIILL ; see Chapter 16, 
Table 17-41 lists model-specific fields to interpret error codes applicable to IA32_MC5_STATUS.7CH: MCA_PKGS_SMBUS_MCP_PAUSE_TIMEOUT
7DH: MCA_PKGS_SMBUS _SPD_PAUSE_TIMEOUT
8BH: MCA_PKGC_ALLOW_L1_ERROR90H: MCA_RECOVERABLE_ DIE_THERMAL_TOO_HOT
A1H: MCA_BCLK_FREQ_ OC_ABOVE_THRESHOLD
B0H: MCA_DISPATCHER_RUN_BUSY_TIMEOUT
C0H: MCA_DISPATCHER_RUN_BUSY_TIMEOUT
become more like ly to happen.
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.Table 17-40.  Machine Check Error Codes for IA32_MC4_STATUS  (Contd.)
Type Bit No. Bit Functi on Bit Description17-40 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
Table 17-41.  Interconnect MC Error Codes for IA32_MC5_STATUS
NOTES:
01H: UC Phy Detected Drift Buffer Alarm.
02H: UC Phy Detected La tency Buffer Rollover.
10H: UC LL Rx detected CRC error: unsuccessful LLR (entered Abort state).
11H: UC LL Rx Unsupported/Undefined packet.12H: UC LL or Phy Control Error.
13H: UC LL Rx Parameter Exception.
15H: UC LL Rx SGX MAC Error.
1FH: UC LL Detected Control Error.
The encoding of correctable (COR) errors are:20H: COR Phy Initialization Abort.
21H: COR Phy Inband Reset.
22H: COR Phy Lane failure,  recovery in x8 width.
23H: COR Phy L0c error corrected without Phy reset.
24H: COR Phy L0c error triggering Phy reset.
25H: COR Phy L0p exit error corrected with reset.30H: COR LL Rx detected CRC error: successful LLR without Phy Re-init.
31H: COR LL Rx detected CRC error: successful LLR with Phy Re-init.
31:22 MSCOD_SPARE The definition below applies to MSCOD 12H (UC LL or Phy Control Errors).
[Bit 22]: Phy Control Error.
[Bit 23]: Unexpected Retry.Ack flit.
[Bit 24]: Unexpected Retry.Req flit.[Bit 25]: RF parity error.
[Bit 26]: Routeback Table error.
[Bit 27]: Unexpected Tx Protocol flit (EOP, Header, or Data).[Bit 28]: Rx Header -or-Credit BGF credit  overflow/underflow.
[Bit 29]: Link Layer Reset still in progress when Phy enters L0 (Phy 
[Bit 30]: Link Layer reset initiated while protocol traffic not idle.
[Bit 31]: Link Layer Tx Parity Error.
Validity Indicators1 63:57Vol. 3B 17-41INTERPRETING MACHINE CHECK ERROR CODES
17.13.3  Integrated Memory Controller Machine Check Errors
MC error codes associated with integrated memory controllers for the 4th generation Intel® Xeon® Scalable 
Processor Family based on Sapphire Rapids microa rchitecture are reported in the IA32_MC13_STATUS −
IA32_MC20_STATUS MSRs.
Table 17-42.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 13—20)
0002H: Data parity error.
0003H: Data ECC error.
0004H: Data byte en able parity error.
0040H: Uncorrected spare error.0080H: Corrected read error.
00A0H: Uncorrected read error.
00C0H: Uncorrected metadata.0100H: WDB read parity error.
0108H: DDR link failure.
0200H: DDR5 command / address parity error.0400H: RPQ0 parity (primary) error.
0800H: DDR-T bad request.
0801H: DDR Data response to an invalid entry.0802H: DDR data response to an entry not expecting data.
0803H: DDR5 completion to an invalid entry.
0804H: DDR-T completion to an invalid entry.0805H: DDR data/completion FIFO overflow.
0806H: DDR-T ERID correctable parity error.
0807H: DDR-T ERID uncorrectable error.0808H: DDR-T interrupt received wh ile outstanding interrupt was not 
ACKed.
0809H: ERID FIFO overflow.080AH: DDR-T error on FNV write credits.
080BH: DDR-T error on FNV read credits.
080CH: DDR-T scheduler error.080DH: DDR-T FNV error event.
080EH: DDR-T FNV thermal event.
080FH: CMI packet while idle.0810H: DDR_T_RPQ_REQ_PARITY_ERR.
0811H: DDR_T_WPQ_REQ_PARITY_ERR.
0812H: 2LM_NMFILLWR_CAM_ERR.17-42 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
Additional information is reported in the IA32_MC13_MISC −IA32_MC20_MISC MSRs. Table 17-43 lists the infor-
mation reported in IA32_MCi_MISC, where i = 13 −20.0813H: CMI_CREDIT_OVERSUB_ERR.
0814H: CMI_CREDIT_TOTAL_ERR.
0815H: CMI_CREDIT _RSVD_POOL_ERR.
0816H: DDR_T_RD_ERROR.0817H: WDB_FIFO_ERR.
0818H: CMI_REQ_FIFO_OVERFLOW.
0819H: CMI_REQ_FIFO_UNDERFLOW.081AH: CMI_RSP_FIFO_OVERFLOW.
081BH: CMI_RSP_FIFO_UNDERFLOW.
081CH: CMI_MISC_MC_CRDT_ERRORS.081DH: CMI_MISC_MC_ARB_ERRORS.
081EH: DDR_T_WR_CMPL_FIFO_OVERFLOW.
081FH: DDR_T_WR_CMPL_FIFO_UNDERFLOW.
0820H: CMI_RD_CPL_FIFO_OVERFLOW.
0821H: CMI_RD_CPL_FIFO_UNDERFLOW.0822H: TME_KEY_PAR_ERR.
0823H: TME_CMI_MISC_ERR.
0824H: TME_CMI_OVFL_ERR.0825H: TME_CMI_UFL_ERR.
0826H: TME_TEM_SECURE_ERR.
0827H: TME_UFILL_PAR_ERR.0829H: INTERNAL_ERR.
082AH: TME_INTEGRITY_ERR.
082BH: TME_TDX_ERR082CH: TME_UFILL_TEM_SECURE_ERR.
082DH: TME_KEY_POISON_ERR.
082EH: TME_SECURITY_ENGINE_ERR.1008H: CORR_PATSCRUB_MIRR2ND_ERR.
1010H: UC_PATSCRUB_MIRR2ND_ERR.
1020H: COR_SPARE_MIRR2ND_ERR.1040H: UC_SPARE_MIRR2ND_ERR.
1080H: HA_RD_MIRR2ND_ERR.10A0H: HA_UNCORR_RD_MIRR2ND_ERR.
37:32 Other Info Other Info.56:38 See Chapter 16, “Mac hine-Check Architecture.”
NOTES:
1. These fields are architecturally defined. Refer to Chap ter 16, “Machine-Check Architecture,” for more information.Table 17-42.  Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 13—20)
Type Bit No. Bit Function Bit DescriptionVol. 3B 17-43INTERPRETING MACHINE CHECK ERROR CODES
17.13.4  M2M Machine Check Errors
MC error codes associated with M2M for the 4th generation Intel Xeon Scalable Processor Family with a CPUID 
DisplayFamily_DisplaySignature of 06_8FH are reported in the IA32_MC12_STATUS MSR. 
“Machine-Check Architecture.”Table 17-43.  Additional Information Reported in IA32_MCi_MISC (i= 13—20)
5:0 LSB See Figure 16-8.8:6 Address Mode See Table 16-3.18:9 Column Column address for the last retry. To get the real column ad dress from this field, shift the 
value left by 2.
36:19 Row Component of sub-DIMM address.42:37 Bank ID Component of sub-DIMM address.
Bit 42: Reserved.
Bit 41: Bank group 2.Bit 40: Bank address 1.
Bit 39: Bank address 0.
Bit 38: Bank group 1.
Bit 37: Bank group 0.
48:43 Failed Device Failing device fo r correctable error (not valid for uncorrectable or transient errors).
50:49 Reserved Reserved55:51 Failed Device Number In HBM mode, holds the failed device number for upper 32 bytes.55:52 CBit In DDR mode, bits 54-52: sub_rank[2:0]; bit 55: reserved.58:56 Chip Select Chip Select62:59 ECC Mode 0000b: SDDC 2LM.
1011b: Not a valid ECC mode.
For HBM mode:0001b: 64B read.
1001b: 32B read.

63 Transient Indicates if the error was a transient erro r. A transient error is only indicated for demand 
reads, underfill reads, and patrol. If there was a WDBParity Error, this field indicates the WDB 
ID bit 6.17-44 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.13.5  High Bandwidth Memory Machine Check Errors
MC error codes associated with high bandwidth memory for the 4th generation Intel Xeon Scalable Processor 
Family are reported in the IA32_MC29_STATUS −IA32_MC31_STATUS MSRs.
17.14 INCREMENTAL DECODING INFORM ATION: PROCESSOR FAMILY 0FH, 
Table 17-45 provides information for interpreting additional family 0FH model-specific fields for external bus errors. 
interpretation of compound error codes.Table 17-44.  M2M MC Error Codes for IA32_MC12_STATUS
NOTES:
Model Specific Errors 23:16 MscodDataRdErr 00H: No error (default).
01H: Read ECC error (MemSpecRd; MemRd; MemRdData; MemRdXto*; 
MemInv; MemInvXto*; MemInvItoX).
02H: Bucket1 error.03H: RdTrkr Parity error.
05H: Prefetch ch annel mismatch.
07H: Read completion parity error.08H: Response parity error.
09H: Timeout error.
0AH: CMI reserved credit pool error.
0BH: CMI total credit count error.
0CH: CMI credit oversubscription error.
25:24 MscodDDRType 00: Not logged, whether error on DDR4 or DDRT.
01: HBM errors.
31:26 Reserved Reserved37:32 Other Info Other Info.56:38 See Chapter 16, “Mac hine-Check Architecture.”
Validity Indicators1 63:57Vol. 3B 17-45INTERPRETING MACHINE CHECK ERROR CODES
Table 17-10 provides information on interpreting addition al family 0FH model specific fields for cache hierarchy 
errors. These errors are reported in one of the IA32_MCi _STATUS MSRs. These errors are reported, architecturally, 
as compound errors with a general form of 0000 0001 RRRR TTLL  in the MCA error code field. See Chapter 16 for 
how to interpret the compound error code. 
17.14.1  Model-Specific Machine Check Error Codes for the Intel® Xeon® Processor MP 7100 
Series
The Intel Xeon processor MP 7100 series has five register banks which contain information related to Machine 
Check Errors. MCi_STATUS[63:0] refers to all five regi ster banks. MC0_STATUS[63:0] through MC3_STATUS[63:0] 
is the same as previous generations of Intel Xeon proce ssors within Family 0FH. MC4_STATUS[63:0] is the main 
error logging for the processor’s L3 and front side bus errors . It supports the L3 Errors, Bus and Interconnect Errors 
Compound Error Codes in the MCA Error Code Field.Table 17-45.  Incremental Decoding Information: Processor Fa mily 0FH, Machine Error Codes for Machine Check 
MCA Error 
Codes1 
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.15:0
Model-Specific 
Error Codes16 FSB Address Parity Address parity error detected:
17 Response Hard Fail Hardware failure detected on response.18 Response Parity Parity error detected on response.19 PIC and FSB Data Parity Da ta Parity detected on either PIC or FSB access.
20 Processor Signature = 
00000F04H: 
Invalid PIC RequestProcessor Signature = 00000F04H:
Indicates error due to an invalid PIC request access was made to PIC space 
with WB memory):
1: Invalid PIC request error.
0: No Invalid PIC request error.
All other processors:
21 Pad State Machine The state machine that trac ks P and N data-strobe relative timing has 
become unsynchronized or a glitch has been detected.
22 Pad Strobe Glitch Data strobe glitch.23 Pad Address Glitch Address strobe glitch.
Other 
Information56:24 Reserved Reserved
Status 
Register 
Validity 
Indicators1 63:5717-46 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.14.1.1  Processor Machine Check Status Register MCA Error Code Definition
The Intel Xeon processor MP 7100 series uses compound  MCA Error Codes for logging its CBC internal machine 
check errors, L3 Errors, and Bus/In terconnect Errors. It defines additional Machine Check error types 
(IA32_MC4_STATUS[15:0]) beyond those defined in Chapter 16. Table 17-47 lists these model-specific MCA error 
codes. Error code details are specified in MC4_STATUS [31:16]; see Section 17.14.3, the “Model Specific Error 
Code” field. The information in the “Other_Info” fiel d (MC4_STATUS[56:32]) is common to the three processor 
error types and contains a correctable event count and specifies the MC4_MISC register format.Table 17-46.  MCi_STATUS Register Bit Definition 
Bit Field Name Bits Description
MCA_Error_Code 15:0 This field specifies the machine check architecture defined error code for the machine check error 
condition detected. The machine check architecture defined error codes are guaranteed to be the same 
for all Intel Architecture processors that implemen t the machine check architec ture. See tables below. 
Model_Specific_E
rror_Code31:16 This field specifies the model specific error code that uniquely identifies the machine check error 
condition detected. The model specific error codes ma y differ among Intel Architecture processors for 
the same Machine Check Error condition. See tables below.
Other_Info 56:32 The functions of the bits in this field are implementation specific  and are not part of the machine check 
architecture. Software that is inte nded to be portable among Intel Ar chitecture processors should not 
rely on the values in this field.
PCC 57 The Processor Context Corrupt fl ag indicates that the st ate of the processor might have been corrupted 
by the error condition detec ted and that reliable restarting of th e processor may not be possible. When 
clear, this flag indicates that the error did not affect the processor's st ate. This bit will always be set for 
MC errors, which are not corrected.
ADDRV 58 The MC_ADDR register valid flag indicates that the MC_ADDR register contains the address where the 
error occurred. When clear, this flag indicates that the MC_ADDR register does not contain the address 
where the error occurred. The MC_ADDR register should not be read if the ADDRV bit is clear.
MISCV 59 The MC_MISC register valid flag indicates that the MC_MISC register contains additional 
information regarding the error. When clear, this flag indicates that the MC_MISC register does not 
contain additional information regarding the error. MC_MISC should not be read if the MISCV bit is not 
set.  
EN 60 The error enabled flag indicates that reporting of the machine check exception for this error was 
enabled by the associated flag bit of the MC_CTL register. Note that correctable errors do not have 
associated enable bits in the MC_CTL register so the EN bit should be clear when a correctable error is 
logged.
UC 61 The error uncorrected flag indicates that the proc essor did not correct the error condition. When clear, 
this flag indicates that the processor was able to correct the event condition.
OVER 62 The machine check overflow flag indicates that a machine check error occurred while the results of a 
previous error were still in the register bank (i.e., the VAL bit was already set in the 
MC_STATUS register). The processor sets the OVER flag and software is responsible for clearing it.  Enabled errors are written over disabled errors, and uncorrected errors are written over corrected 
events. Uncorrected errors are not written over previous valid uncorrected errors. 
VAL 63 The MC_STATUS register valid flag indicates that the inform ation within the MC_STATUS register is valid. 
When this flag is set, the processo r follows the rules given for the OVER flag in the MC_STATUS register 
when overwriting previously valid entries. The processor sets the VAL flag and software is responsible 
for clearing it.Vol. 3B 17-47INTERPRETING MACHINE CHECK ERROR CODES
The bold faced  binary encodings are the only encodings us ed by the processor for MC4_STATUS[15:0].
17.14.2  Other_Info Field (All MCA Error Types)
The MC4_STATUS[56:32] field is common to the pr ocessor's three MCA error types (A, B, and C).Table 17-47.  Incremental MCA Error Code  for Intel® Xeon® Processor MP 7100 
Processor MCA_Error_Code (MC4_STATUS[15:0])
Type Error Code Binary Encoding MeaningC Internal Error 0000 0100 0000 0000 Internal Error Type Code.A L3 Tag Error 0000 0001 0000 1011 L3 Tag Error Type Code.BB u s  a n d  
Interconnect Error0000 100x 0000 1111 Not used, but this encoding is reserved for compatibility with other MCA 
0000 101x 0000 1111 Not used, but this encoding is reserved for compatibility with other MCA 

0000 110x 0000 1111 Not used, but this encoding is reserved for compatibility with other MCA 
0000 1110 0000 1111 Bus and Interconnection Error Type Code.0000 1111 0000 1111 Not used, but this encoding is reserved for compatibility with other MCA 
Table 17-48.  Other Information Field Bit Definition 
39:32 8-bit Correctable 
Event CountThis field holds a count of the number of correctabl e events since cold reset.  This is a saturating 
counter; the counter be gins at 1 (with the first error) and saturates at a count of 255.
41:40 MC4_MISC 
Format TypeThe value in this field specifies the format of information in the MC4_MISC register. Currently, 
only two values are defined. Vali d only when MISCV is asserted.
43:42 Reserved Reserved51:44 ECC Syndrome ECC syndrome value for a correctable ECC event when the “Valid ECC syndrome” bit is asserted.52 Valid ECC 
SyndromeSet when a correctable ECC event supplies the ECC syndrome.
54:53 Threshold-Based 
Error Status00: No tracking. No hardware stat us tracking is provided for th e structure reporting this event.
01: Green. Status tracking is provided for the structure posting the event; the current status is 
green (below threshold).
10: Yellow. Status tracking is pr ovided for the structure posting the event; the current status is 
yellow (above threshold).
11: Reserved for future use.
Valid only if the Vali d bit (bit 63) is set.
Undefined if the UC bit (bit 61) is set.
56:55 Reserved Reserved17-48 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
17.14.3  Processor Model Specific Error Code Field
17.14.3.1  MCA Error Type A: L3 Error
Note: The Model Specific Error Code field in MC4_STATUS (bits 31:16).
17.14.3.2  Processor Model Specific Error Code  Field Type B: Bus an d Interconnect Error
Note: The Model Specific Error Code field in MC4_STATUS (bits 31:16).Table 17-49.  Type A: L3 Error Codes
Bit Num Sub-Field 
NameDescription Legal Value(s)
18:16 L3 Error 
CodeDescribes the L3 
error encountered000: No error.
001: More than one way reporting a correctable event.010: More than one way reporting an uncorrectable error.
011: More than one way reporting a tag hit.
100: No error.
101: One way reporting a correctable event.
110: One way reporting an uncorrectable error.111: One or more ways reporting a correctable event while one or more ways are 
reporting an uncorrectable error.
20:19 --- Reserved 00 31:21 --- Fixed pattern 0010_0000_000
Table 17-50.  Type B: Bus and Interconnect Error Codes
Bit Num Sub-Field Name Description
16 FSB Request Parity Parity error detected during FSB request phase.17 Core0 Addr Parity Parity error detected on Core 0 request’s address field.18 Core1 Addr Parity Parity error detected on Core 1 request’s address field.19 Reserved Reserved20 FSB Response Parity Parity error on FSB response field detected.21 FSB Data Parity FSB data parity error on inbound data detected.
22 Core0 Data Parity Data parity error on  data receiv ed from Core 0 detected.
23 Core1 Data Parity Data parity error on  data receiv ed from Core 1 detected.
24 IDS Parity Detected an Enhanced Defer parity error (phase A or phase B).25 FSB Inbound Data ECC Data ECC event to error on  inbound data (correctable or uncorrectable).
26 FSB Data Glitch Pad logic detected a data strobe ‘glitch’ (or sequencing error).27 FSB Address Glitch Pad logic detected a request strobe ‘glitch’ (or sequencing error).31:28 Reserved ReservedVol. 3B 17-49INTERPRETING MACHINE CHECK ERROR CODES
Exactly one of the bits defined in the preceding table will be set for a Bus and Interconnect Error. The Data ECC can 
be correctable or uncorrectable; the MC4_STATUS.UC bi t distinguishes between corre ctable and uncorrectable 
cases with the Other_Info field possibly providing the ECC Sy ndrome for correctable errors. All other errors for this 
processor MCA Error Type are uncorrectable.
17.14.3.3  Processor Model Specific Error Code Field Type C: Cache Bus Controller Error
All errors, except for the correctable ECC types, in this  table are uncorrectable. The correctable ECC events may 
supply the ECC syndrome in the Other_Info field of the MC4_STATUS MSR.Table 17-51.  Type C: Cache Bus Controller Error Codes 
0000_0000_0000_0001 0001H Inclusion Error from Core 0.0000_0000_0000_0010 0002H Inclusion Error from Core 1.0000_0000_0000_0011 0003H Write Exclusive Error from Core 0.0000_0000_0000_0100 0004H Write Exclusive Error from Core 1.0000_0000_0000_0101 0005H Inclusion Error from FSB.0000_0000_0000_0110 0006H SNP Stall Error from FSB.0000_0000_0000_0111 0007H Write Stall Error from FSB.0000_0000_0000_1000 0008H FSB Arb Timeout Error.0000_0000_0000_1001 0009H CBC OOD Queue Underflow/overflow.0000_0001_0000_0000 0100H Enhanced Intel SpeedStep Technology TM1-TM2 Error.0000_0010_0000_0000 0200H Internal Timeout Error.0000_0011_0000_0000 0300H Internal Timeout Error.0000_0100_0000_0000 0400H Intel® Cache Safe Technology Queue Full Error or Disabled-ways-in-a-set overflow.1100_0000_0000_0001 C001H Correctable ECC event on outgoing FSB data.1100_0000_0000_0010 C002H Correctable ECC event on outgoing Core 0 data.1100_0000_0000_0100 C004H Correctable ECC event on outgoing Core 1 data.1110_0000_0000_0001 E001H Uncorrectable ECC error on outgoing FSB data.1110_0000_0000_0010 E002H Uncorrectable ECC error on outgoing Core 0 data.1110_0000_0000_0100 E004H Uncorrectable ECC error on outgoing Core 1 data. — All other encodings — Reserved17-50 Vol. 3BINTERPRETING MACHINE CHECK ERROR CODES
Table 17-52.  Decoding Family 0FH Mach ine Check Codes for Cache Hierarchy Errors
MCA error 
codes115:0
Model 
Specific Error 
Codes17:16 Tag Error Code Contains the tag er ror code for this machine check error:
00: No error detected.
01: Parity error on tag miss with a clean line.
10: Parity error/multiple  tag match on tag hit.
11: Parity error/multiple  tag match on tag miss.
19:18 Data Error Code Contains the data error code for this machine check error:
00: No error detected.01: Single bit error.
10: Double bit error on a clean line.
11: Double bit error on a modified line.
20 L3 Error This bit is set if the machine check error originated in the L3 (it can be ignored for 
invalid PIC request errors):
1: L3 error.0: L2 error.
21 Invalid PIC Request Indicates error due to invalid PIC request access was made to PIC space with WB 
memory:
1: Invalid PIC request error.0: No invalid PIC request error.
31:22 Reserved Reserved
Other 
Information39:32 8-bit Error Count Holds a count of the number of e rrors since reset. The counter begins at 0 for the first 
error and saturates at a count of 255.
56:40 Reserved Reserved
Status 
Register 
Validity 
Indicators163:57
NOTES:
1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.Vol. 3B 18-1CHAPTER 18
DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOURCE DIRECTOR
TECHNOLOGY (INTEL® RDT) FEATURES
NOTE
This chapter makes numerous references to last -branch recording (LBR) facilities. Unless noted 
otherwise, all such references in this chapter are to  an earlier non-architectural form of the feature. 
Chapter 19 defines an architectu ral form of last-branch recording that is supported on newer 
Intel 64 and IA-32 architectures provide debug facilities fo r use in debugging code and monitoring performance. 
These facilities are valuable for debugging application software, system software, and multitasking operating 
systems. Debug support is accessed using debug regist ers (DR0 through DR7) and model-specific registers 
(MSRs): 
•Debug registers hold the addresses of memory and I/O locations called breakpoints. Breakpoints are user-
selected locations in a program, a data-storage area in memory, or specific I/O ports. They are set where a 
programmer or system designer wishes to halt executio n of a program and examine the state of the processor 
by invoking debugger software. A debug exception (#DB ) is generated when a memory or I/O access is made 
to a breakpoint address. 
•MSRs monitor branches, interrupts, and exceptions; they  record addresses of the last branch, interrupt or 
exception taken and the last branch taken before an interrupt or exception.
•Time stamp counter is described in  Section 18.17, “Time-Stamp Counter.”
•Features that allow monitoring of shared platform resources such as the L3 cache are described in Section 
18.18, “Intel® Resource Director Technology (Intel® RDT) Monitoring Features.”
•Features that enable control over shared platform reso urces are described in Section 18.19, “Intel® Resource 
Director Technology (Intel® RDT) Allocation Features.”
•Features that enable control over shared platform resources for non-CPU agents are described in Section 
18.20, “Intel® Resource Director Technology (Intel® RDT) for Non-CPU Agents.”1
18.1 OVERVIEW OF DE BUG SUPPORT FACILITIES

The following processor facilities support debugging and performance monitoring:
•Debug exception (#DB) — Transfers program control to a debug procedure or task when a debug event 
occurs.
•Breakpoint exception (#BP) — See breakpoint instruction (INT3) below.
•Breakpoint-address register s (DR0 through DR3) — Specifies the addresses of up to 4 breakpoints.
•Debug status register (DR6) — Reports the conditions that were in effect when a debug or breakpoint 
exception was generated.
•Debug control register (DR7) — Specifies the forms of memory or I/O access that cause breakpoints to be 
•T (trap) flag, TSS — Generates a debug exception (#DB) when an a ttempt is made to switch to a task with 
the T flag set in its TSS.
•RF (resume) flag, EFLAGS register —  Suppresses multiple exceptions to the same instruction.
•TF (trap) flag, EFLAGS register — Generates a debug exception (#DB) after every execution of an 
1. Additional information about Intel® RDT can be found in the do cument titled “Intel® Resource Director Technology Architecture  Spec-
ification,” available here: https://www.int el.com/content/www/us/en/ developer/articles/technical/intel-sdm.html .18-2 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
•Breakpoint instruction (INT3) — Generates a breakpoint exception (#BP) that transfers program control to 
the debugger procedure or task. This instruction is an alternative way to set instruction breakpoints. It is especially useful when more than four breakpoints are desired, or when breakpoints are being placed in the 
source code.
•Last branch recording facilities — Store branch records in the last branch record (LBR) stack MSRs for the 
most recent taken branches, interrupts, and/or exceptions in MSRs. A branch record consist of a branch-from and a branch-to instruction address. Send branch reco rds out on the system bus as branch trace messages 
(BTMs).
These facilities allow a debugger to be called as a separa te task or as a procedure in the context of the current 
program or task. The following conditions can be used to invoke the debugger:
•Task switch to a specific task.
•Execution of the breakpoint instruction.
•Execution of any instruction.
•Execution of an instruction at a specified address.
•Read or write to a specified memory address/range.
•Write to a specified memory address/range.
•Input from a specified I/O address/range.
•Output to a specified I/O address/range.
•Attempt to change the cont ents of a debug register.
18.2 DEBUG REGISTERS
Eight debug registers (see Figure 18-1 for 32-bit operation and Figure 18-2 for 64-bit operation) control the debug 
operation of the processor. These registers can be written to and read using the move to/from debug register form 
of the MOV instruction. A debug register may be the source or destination operand for one of these instructions. Vol. 3B 18-3DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
Debug registers are privileged resources; a MOV instructio n that accesses these registers can only be executed in 
real-address mode, in SMM or in protected mode at a CPL of 0. An attempt to read or write the debug registers 
from any other privilege level generates a general-protection exception (#GP).
The primary function of the debug registers is to set up  and monitor from 1 to 4 breakpoints, numbered 0 though 
3. For each breakpoint, the following information can be specified:
•The linear address where the breakpoint is to occur.
•The length of the breakpoint location: 1, 2, 4, or 8 bytes (refer to the notes in Section 18.2.4).
•The operation that must be performed at the address for a debug exception to be generated.
•Whether the breakpoint is enabled.
•Whether the breakpoint condition was present when the debug exception was generated.
The following paragraphs describe the functions of flags and fields in the debug registers.Figure 18-1.  Debug RegistersL
0G
0L1 G
1L
2G
2L3 G
3L
EG
E1R
T
M0G
D0  0R/W
0LEN 
0R/W
1LEN
1R/W
2LEN
2R/W
3LEN
3DR7
B
0B
1B
2B
3B
DBS B
TR
T
MReserved (set to 1) DR6
0 31
DR5
0 31
DR4
0 31
Breakpoint 3 Linear Address DR3
0 31
Breakpoint 2 Linear Address DR2
0 31
Breakpoint 1 Linear Address DR1
0 31
Breakpoint 0 Linear Address DR01 1 1 1 1 1 1 1 0
Reserved31    30    29    28    27    26    25    24    23    22    21    20    19    18    17    16   15    14    13    12    11    10     9      8      7      6      5      4      3      2      1      0
31                                                                                                                   16   15    14    13    12    11    10    9      8      7      6      5      4      3      2      1      0
B
L
D18-4 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
18.2.1 Debug Address Registers (DR0-DR3)
Each of the debug-address registers (DR0 through DR3) holds the 32-bit linear address of a breakpoint (see 
Figure 18-1). Breakpoint comparisons are made before phys ical address translation occurs. The contents of debug 
register DR7 further specifies breakpoint conditions. 
18.2.2 Debug Registers DR4 and DR5
Debug registers DR4 and DR5 are reserved when debug ex tensions are enabled (when the DE flag in control 
register CR4 is set) and attempts to reference the DR4 and DR5 registers cause invalid-opcode exceptions (#UD). 
When debug extensions are not enabled (when the DE flag is clear), these registers are aliased to debug registers 
DR6 and DR7.
18.2.3 Debug Status Register (DR6)
The debug status register (DR6) reports debug conditions that were sampled at the time the last debug exception 
was generated (see Figure 18-1). Updates to this register on ly occur when an exception is generated. The flags in 
this register show the following information:
•B0 through B3 (breakpoin t condition detected) flags (bits 0 through 3) — Indicates (when set) that its 
associated breakpoint condition was met when a debug exception was generated. These flags are set if the 
condition described for each breakpoint by the LEN n, and R/W n flags in debug control register DR7 is true. They 
may or may not be set if the breakpoint is not enabled by  the Ln or the Gn flags in register DR7. Therefore on 
a #DB, a debug handler should check only those B0-B 3 bits which correspond to an enabled breakpoint.
•BLD (bus-lock detected) flag (bit 11) — Indicates (when clear ) that the debug exception was triggered by 
the assertion of a bus lock when CPL > 0 and OS bus- lock detection was enabled (see Section 18.3.1.6). Other 
debug exceptions do not modify this bit. To avoid co nfusion in identifying debug exceptions, software debug-
exception handlers should set bit 11 to 1 before return ing. (Software that never enables OS bus-lock detection 
need not do this as DR6[11] = 1 following reset.) This bi t is always 1 if the processor does not support OS bus-
lock detection.
•BD (debug register access detected) flag (bit 13) — Indicates that the next instruction in the instruction 
stream accesses one of the debug registers (DR0 throug h DR7). This flag is enabled when the GD (general 
detect) flag in debug control register DR7 is set. See Section 18.2.4, “Debug Control Register (DR7),” for 
further explanation of the purpose of this flag. 
•BS (single step) flag (bit 14) — Indicates (when set) that the debug ex ception was triggered by the single-
step execution mode (enabled with the TF flag in the EFLAGS register). The single-step mode is the highest-
priority debug exception. When the BS flag is set, any of the other debug status bits also may be set.
•BT (task switch) flag (bit 15) — Indicates (when set) that the debug exception resulted from a task switch 
where the T flag (debug trap flag) in the TSS of the target task was set. See Section 8.2.1, “Task-State Segment (TSS),” for the format of a TSS. There is no flag in debug control register DR7 to enable or disable this 
exception; the T flag of the TSS is the only enabling flag.
•RTM (restricted transactional memory) flag (bit 16)  — Indicates (when clear ) that a debug exception 
(#DB) or breakpoint exception (#BP) occurred inside an  RTM region while advanced debugging of RTM trans-
actional regions was enabled (see Section 18.3.3). This bit is set for any other debug exception (including all 
those that occur when advanced debugging of RTM transact ional regions is not enabled). This bit is always 1 if 
the processor does not support RTM.
Certain debug exceptions may clear bits 0-3. The remainin g contents of the DR6 register are never cleared by the 
processor. To avoid confusion in iden tifying debug exceptions, debug handlers should clear the register (except 
bit 16, which they should set) before returning to the interrupted task.
18.2.4 Debug Control Register (DR7)
The debug control register (DR7) enables or disables brea kpoints and sets breakpoint conditions (see Figure 18-1).

The debug control register (DR7) enables or disables brea kpoints and sets breakpoint conditions (see Figure 18-1). 
The flags and fields in this register control the following things:Vol. 3B 18-5DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
•L0 through L3 (local breakpoint enab le) flags (bits 0, 2, 4, and 6) — Enables (when set) the breakpoint 
condition for the associated breakpoint for the current task. When a breakpoint condition is detected and its associated L n flag is set, a debug exception is generated. The processor automatically clears these flags on 
every task switch to avoid unwanted breakpoint conditions in the new task.
•G0 through G3 (global breakpoint enab le) flags (bits 1, 3, 5, and 7) — Enables (when set) the 
breakpoint condition for the associated breakpoint for all tasks. When a breakpoint condition is detected and its 
associated G n flag is set, a debug exception is generated. The processor does not clear these flags on a task 
switch, allowing a breakpoint to be enabled for all tasks.
•LE and GE (local and global exact br eakpoint enable) flags (bits 8, 9) — This feature is not supported in 
the P6 family processors, later IA-32 processors, and Intel 64 processors. When set, these flags cause the 
processor to detect the exact instruction that caused a data breakpoint condition. For backward and forward 
compatibility with other Intel processors, we recommend  that the LE and GE flags be set to 1 if exact 
breakpoints are required.
•RTM (restricted transactional memory) flag (bit 11)  — Enables (when set) ad vanced debugging of RTM 
transactional regions (see Section 18.3.3). This advanced  debugging is enabled only  if IA32_DEBUGCTL.RTM is 
also set.
•GD (general detect enable) flag (bit 13) — Enables (when set) debug-register protection, which causes a 
debug exception to be generated prior to any MOV instruction that accesses a debug register. When such a 
condition is detected, the BD flag in debug status regist er DR6 is set prior to generating the exception. This 
condition is provided to support in-circuit emulators. 
When the emulator needs to access the debug registers, emulator software can set the GD flag to prevent 
interference from the program curre ntly executing on the processor.
The processor clears the GD flag upon entering to the debug exception handler, to allow the handler access to 
the debug registers.
•R/W0 through R/W3 (read/write) fields (b its 16, 17, 20, 21, 24 , 25, 28, and 29) — Specifies the 
breakpoint condition for the corresponding breakpoint. Th e DE (debug extensions) flag in control register CR4 
determines how the bits in the R/W n fields are interpreted. When the DE flag is set, the processor interprets 
bits as follows:
00 — Break on instruction execution only. 
01 — Break on data writes only.
10 — Break on I/O reads or writes.11 — Break on data reads or writes but not instruction fetches.
When the DE flag is clear, the processor interprets the R/W n bits the same as for the Intel386™ and Intel486™ 
processors, which is as follows:
00 — Break on instruction execution only.
10 — Undefined.11 — Break on data reads or writes but not instruction fetches.
•LEN0 through LEN3 (Length) fields (bit s 18, 19, 22, 23, 26 , 27, 30, and 31) — Specify the size of the 
memory location at the address specified in the corresp onding breakpoint address register (DR0 through DR3). 
These fields are interpreted as follows:
00 — 1-byte length.
01 — 2-byte length.10 — Undefined (or 8 byte length, see note below).
11 — 4-byte length.
If the corresponding RW n field in register DR7 is 00 (instruction execution), then the LEN n field should also be 00. 
The effect of using other lengths is  undefined. See Section 18.2.5, “B reakpoint Field Recognition,” below.18-6 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
NOTES
For Pentium® 4 and Intel® Xeon® processors with a CPUID signature corresponding to family 15 
(model 3, 4, and 6), break point conditions permit specifying 8-byte length on data read/write with 
an of encoding 10B in the LEN n field. 
Encoding 10B is also supported in processors based on Intel Core microarchitecture or enhanced 
Intel Core microarchitecture, the respective CPUID signatures corresponding to family 6, model 15, 
and family 6, DisplayModel value 23 (see the CPUID instruction in Chapter 3, “Instruction Set Reference, A-L,” in the Intel
2A). The Encoding 10B is supported in processors based on Intel Atom® microarchitecture, with 
CPUID signature of family 6, DisplayModel valu e 1CH. The encoding 10B is undefined for other 
18.2.5 Breakpoint Field Recognition
Breakpoint address registers (debug registers DR0 through DR3) and the LEN n fields for each breakpoint define a 
range of sequential byte addresses for a data or I/O breakpoint. The LEN n fields permit specification of a 1-, 2-, 4- 
or 8-byte range, beginning at the linear address specified in the corresponding debug register (DR n). Two-byte 
ranges must be aligned on word boundaries; 4-byte rang es must be aligned on doubleword boundaries, 8-byte 
ranges must be aligned on quadword boundaries. I/O ad dresses are zero-extended (from 16 to 32 bits, for compar-
ison with the breakpoint address in the selected debu g register). These requirements are enforced by the 
processor; it uses LEN n field bits to mask the lower address bits in the debug registers. Unaligned data or I/O 
breakpoint addresses do not yield valid results.
A data breakpoint for reading or writing data is triggered if any of the bytes participating in an access is within the 
range defined by a breakpoint address register and its LEN n field. Table 18-1 provides an example setup of debug 
registers and data accesses that would subseque ntly trap or not trap on the breakpoints.
A data breakpoint for an unaligned operand can be constr ucted using two breakpoints, where each breakpoint is 
byte-aligned and the two breakpoints together cover the op erand. The breakpoints generate exceptions only for 
the operand, not for neighboring bytes.
Instruction breakpoint addresses must have a length specification of 1 byte (the LEN n field is set to 00). Instruction 
breakpoints for other operand sizes are undefined. The proc essor recognizes an instruction breakpoint address only 
when it points to the first byte of an instruction. If th e instruction has prefixes, the breakpoint address must point 
to the first prefix.
Table 18-1.  Breakpoint Examples
Debug Register Setup
Debug Register R/W n Breakpoint Address LEN n
DR0
DR1
DR2DR3R/W0 = 11 (Read/Write)
R/W1 = 01 (Write)
R/W2 = 11 (Read/Write)R/W3 = 01 (Write)A0001H
A0002H
B0002HC0000HLEN0 = 00 (1 byte)
LEN1 = 00 (1 byte)
LEN2 = 01) (2 bytes)LEN3 = 11 (4 bytes)
Data Accesses
Operation Address Access Length 
(In Bytes)
Data operations that trap
- Read or write- Read or write
- Write
- Write- Read or write
- Read or write
- Read or write- Write
- Write
- WriteA0001H
A0001H
A0002H
A0002HB0001H
B0002H
B0002HC0000H
C0001H
C0003H1
2
1
24
1
24
2
1Vol. 3B 18-7DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.2.6 Debug Registers and Intel® 64 Processors
For Intel 64 architecture processors, debug registers DR 0–DR7 are 64 bits. In 16-bit or 32-bit modes (protected 
mode and compatibility mode), writes to a debug register  fill the upper 32 bits with zeros. Reads from a debug 
register return the lower 32 bits. In 64-bit mode, MOV DR n instructions read or write all 64 bits. Operand-size 
prefixes are ignored. 
In 64-bit mode, the upper 32 bits of DR6 and DR7 are reserv ed and must be written with zeros. Writing 1 to any of 
the upper 32 bits results in a #GP(0) exception (see Figure 18-2). All 64 bits of DR0–DR3 are writable by software. 
However, MOV DRn instructions do not check that addresses written to DR0–DR3 are in the linear-address limits of 
the processor implementation (address matching is suppor ted only on valid addresses generated by the processor 
implementation). Breakpoint conditions for 8-byte  memory read/writes are supported in all modes.
18.3 DEBUG EXCEPTIONS
The Intel 64 and IA-32 architectures dedicate two interrupt  vectors to handling debug exceptions: vector 1 (debug 
exception, #DB) and vector 3 (breakpoint exception, #BP). The following sections describe how these exceptions are generated and typical exception handler operations.
18.3.1 Debug Exception (#DB)—Interrupt Vector 1
The debug-exception handler is usually a debugger progra m or part of a larger software system. The processor 
generates a debug exception for any of several conditions. The debugger checks flags in the DR6 and DR7 registers 
to determine which condition caused the exception and wh ich other conditions might apply. Table 18-2 shows the 
states of these flags following the generati on of each kind of breakpoint condition.

Instruction-breakpoint and general-detect condition (see  Section 18.3.1.3, “General-Detect Exception Condition”) 
result in faults; other debug-exception conditions result in traps. The debug exception may report one or both at 
one time. The following sections describe each class of debug exception.
The INT1 instruction generates a debug exception as a trap. Hardware vendors may use the INT1 instruction for 
hardware debug. For that reason, Intel recommends soft ware vendors instead use the INT3 instruction for soft-
ware breakpoints.
See also: Chapter 6, “Interrupt 1—Debug Exception (#DB),” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3A.Data operations that do not trap
- Read or write- Read
- Read or writeA0000H
A0002H
A0003H
B0000HC0000H
C0004H1
1
4
22
4Table 18-1.  Breakpoint Examples (Contd.)
Debug Register R/W n Breakpoint Address LEN n18-8 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
Figure 18-2.  DR6/DR7 Layout on Proces sors Supporting Inte l® 64 Architecture32 63
L
0G
0L1 G
1L
2G
2L
3G
3L
EG
EG
DR/W
0LEN
0R/W
1LEN
1R/W
2LEN
2R/W
3LEN
3DR7DR7
32 63
B
0B
1B
2B
3B
DB
SB
TReserved (set to 1) DR6DR60 0 1 0 0
1 1 1 1 1 1 1 0
32 63
DR5
32 63
DR4
32 63
32 63
32 63
32 63
Breakpoint 0 Linear Address DR0
ReservedR
T
MB
L
D31    30    29    28    27    26    25    24    23    22    21    20    19    18    17    16   15    14    13    12    11    10     9      8      7      6      5      4      3      2      1      0
1Vol. 3B 18-9DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.3.1.1  Instruction-Brea kpoint Exception Condition
The processor reports an instruction breakpoint when it attempts to execute an instruction at an address specified 
in a breakpoint-address register (DR0 through DR3) that ha s been set up to detect instruction execution (R/W flag 
is set to 0). Upon reporting the instruction breakpoint , the processor generates a fault-class, debug exception 
(#DB) before it executes the target instruction for the breakpoint. 
Instruction breakpoints are the highest priority debug exceptions. They are se rviced before any other exceptions 
detected during the decoding or execution of an instruction.  However, if an instruction breakpoint is placed on an 
instruction located immediately after a POP SS/MOV SS in struction, the breakpoint will be suppressed as if 
EFLAGS.RF were 1 (see the next paragraph and Section 6.8.3, “Masking Exceptions and Interrupts When Switching Stacks,” of the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).
Because the debug exception for an instruction breakpoint is generated before the instruction is executed, if the 
instruction breakpoint is not removed by the exception handler; the processor will detect the instruction breakpoint 
again when the instruction is restarted and generate anothe r debug exception. To prevent looping on an instruction 
breakpoint, the Intel 64 and IA-32 architectures provide th e RF flag (resume flag) in the EFLAGS register (see 
Section 2.3, “System Flags and Fields in the EFLAGS Register,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3A). When the RF flag is  set, the processor ignores instruction breakpoints.
All Intel 64 and IA-32 processors manage the RF flag as foll ows. The RF Flag is cleared at the start of the instruction 
after the check for instruction breakpoints, CS limit viol ations, and FP exceptions. Task Switches and IRETD/IRETQ 
instructions transfer the RF image from the TSS/stack to the EFLAGS register.
When calling an event handler, Intel 64 and IA-32 processors  establish the value of the RF flag in the EFLAGS image 
pushed on the stack:
•For any fault-class exception except a debug exception generated in response to an instruction breakpoint, the value pushed for RF is 1.
•For any interrupt arriving after any iteration of a repeat ed string instruction but th e last iteration, the value 
pushed for RF is 1.
•For any trap-class exception generated by any iteration of a repeated string instruction but the last iteration, 
the value pushed for RF is 1.
•For other cases, the value pushed for RF is the value th at was in EFLAG.RF at the time the event handler was 
called. This includes:
— Debug exceptions generated in response to instruction breakpoints— Hardware-generated interrupts arriving between inst ructions (including those arriving after the last 
iteration of a repeated string instruction)Table 18-2.  Debug Exception Conditions
Debug or Breakpoint Condition DR6 Flags Tested DR7 Flags Tested Exception Class
Single-step trap BS = 1 TrapInstruction breakpoint, at  addresses defined by DR n and 
LENnBn = 1 and 
(Gn or Ln = 1)R/Wn = 0 Fault
Data write breakpoint, at addresses defined by DR n and 
(Gn or Ln = 1)R/Wn = 1 Trap
I/O read or write breakpoint, at addresses defined by DR n 
and LEN nBn = 1 and 
(Gn or Ln = 1)R/Wn = 2 Trap
Data read or write (but not instruction fetches), at 
addresses defined by DR n and LEN nBn = 1 and 
(Gn or Ln = 1)R/Wn = 3 Trap
General detect fault, resultin g from an attempt to modify 
debug registers (usually in conjunction with in-circuit emulation)BD = 1 None Fault
Task switch BT = 1 None Trap
INT1 instruction None None Trap18-10 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
— Trap-class exceptions generated after an instruction completes (including those generated after the last 
iteration of a repeated string instruction)
— Software-generated interrupts (RF is pushed as 0, since it was cleared at the start of the software interrupt)
As noted above, the processor does not set the RF flag prior to calling the debug exception handler for debug 
exceptions resulting from instruction breakpoints. Th e debug exception handler can prevent recurrence of the 
instruction breakpoint by setting the RF flag in the EFLAGS image on the stack. If the RF flag in the EFLAGS image is set when the processor returns from the exception handler, it is copied into the RF flag in the EFLAGS register by 
IRETD/IRETQ or a task switch that causes the return. Th e processor then ignores instruction breakpoints for the 
duration of the next instruction. (Note that the POPF, PO PFD, and IRET instructions do not transfer the RF image 
into the EFLAGS register.) Setting the RF flag does not prevent other types of debug-exception conditions (such as, 
I/O or data breakpoints) from being detected, nor does  it prevent non-debug exceptions from being generated.
For the Pentium processor, when an instruction breakpoint coincides with another fault-type exception (such as a 
page fault), the processor may generate one spurious debug exception after the second exception has been 
handled, even though the debug exception handler set the RF flag in the EFLAGS image. To prevent a spurious 
exception with Pentium processors, all fault-class exceptio n handlers should set the RF flag in the EFLAGS image.
18.3.1.2  Data Memory and I/O Breakpoint Exception Conditions
Data memory and I/O breakpoints are reported when the processor attempts to access a memory or I/O address 
specified in a breakpoint-address register (DR0 through DR3) that has been set up to detect data or I/O accesses 
(R/W flag is set to 1, 2, or 3). The processor generates th e exception after it executes the instruction that made the 
access, so these breakpoint condition causes a trap-class exception to be generated. 
Because data breakpoints are traps, an instruction that writes memory overwrites th e original data before the 
debug exception generated by a data breakpoint is generate d. If a debugger needs to save the contents of a write 
breakpoint location, it should save the original contents before setting the breakpoint. The handler can report the 
saved value after the breakpoint is triggered. The addre ss in the debug registers can be used to locate the new 
value stored by the instruction that triggered the breakpoint.
If a data breakpoint is detected during an iteration of a string instruction executed with fast-string operation (see 
Section 7.3.9.3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1), delivery of the 
resulting debug exception may be delayed until completion of the corresponding group of iterations.
Intel486 and later processors ignore the GE and LE flags in DR7. In Intel386 processors, exact data breakpoint 
matching does not occur unless it is enable d by setting the LE an d/or the GE flags.

matching does not occur unless it is enable d by setting the LE an d/or the GE flags. 
For repeated INS and OUTS instructions that generate an  I/O-breakpoint debug exception, the processor generates 
the exception after the completion of the first iteration. Repeated INS and OUTS instructions generate a data-
breakpoint debug exception after the iteration in whic h the memory address breakpoint location is accessed.
If an execution of the MOV or POP instruction loads the SS  register and encounters a data breakpoint, the resulting 
debug exception is delivered after completion of th e next instruction (the one after the MOV or POP).
Any pending data or I/O breakpoints are lost upon delive ry of an exception. For example, if a machine-check 
exception (#MC) occurs following an instruction that encoun ters a data breakpoint (but before the resulting debug 
exception is delivered), the data breakpoint is lost. If a MOV or POP instruction that loads the SS register encoun-
ters a data breakpoint, the data breakpoint is lost if the next instruction causes a fault.
Delivery of events due to INT n, INT3, or INTO does not cause a loss of data breakpoints. If a MOV or POP instruc-
tion that loads the SS register encounters a data breakpoint, and the next instruction is software interrupt (INT n, 
INT3, or INTO), a debug exception (#DB) resulting from a da ta breakpoint will be delivered after the transition to 
the software-interrupt handler. The #DB handler should account for the fact that the #DB may have been delivered after a invocation of a software-interrupt handler, and in  particular that the CPL may have changed between recog-
nition of the data breakpoi nt and delivery of the #DB.
18.3.1.3  General-Dete ct Exception Condition
When the GD flag in DR7 is set, the general-detect debu g exception occurs when a program attempts to access any 
of the debug registers (DR0 through DR7) at the same time they are being used by another application, such as an 
emulator or debugger. This protection feature guarantees full control over the debug registers when required. The Vol. 3B 18-11DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
debug exception handler can detect this condition by chec king the state of the BD flag in the DR6 register. The 
processor generates the exception before it executes th e MOV instruction that accesses a debug register, which 
causes a fault-class exception to be generated. 
18.3.1.4  Single-Ste p Exception Condition
The processor generates a single-step debug exception if (wh ile an instruction is being executed) it detects that the 
TF flag in the EFLAGS register is set. The exception is a trap-class exception, because the exception is generated after the instruction is executed. The processor will not gene rate this exception after the instruction that sets the 
TF flag. For example, if the POPF instruction is used to se t the TF flag, a single-step trap does not occur until after 
the instruction that follows the POPF instruction.
The processor clears the TF flag before calling the exception handler. If the TF flag was set in a TSS at the time of 
a task switch, the exception occurs after the first instruction is executed in the new task.
The TF flag normally is not cleared by privilege changes inside a task. The INT n, INT3, and INTO instructions, 
however, do clear this flag. Therefore, software debugg ers that single-step code must recognize and emulate INT n 
or INTO instructions rather than executing them directly. To maintain protection, the operating system should 
check the CPL after any single-step trap to see if single stepping should continue at the current privilege level.
The interrupt priorities guarantee that, if an external interrupt occurs, single stepping stops. When both an 
external interrupt and a single-step interrupt occur together , the single-step interrupt is processed first. This oper-
ation clears the TF flag. After saving the return address or  switching tasks, the external interrupt input is examined 
before the first instruction of the single-step handler execut es. If the external interrupt is still pending, then it is 
serviced. The external interrupt handler does not run in single-step mode. To single step an interrupt handler, 
single step an INT n instruction that calls the interrupt handler.
If an occurrence of the MOV or POP instruction loads the SS register executes with EFLAGS.TF = 1, no single-step 
debug exception occurs following the MOV or POP instruction.
18.3.1.5  Task-Switch Exception Condition
The processor generates a debug exception after a task switch if the T flag of the new task 's TSS is set. This excep-
tion is generated after program control has passed to the new task, and prior to the execution of the first instruc-tion of that task. The exception handler can detect this condition by examining the BT flag of the DR6 register.
If entry 1 (#DB) in the IDT is a task gate, the T bit of th e corresponding TSS should not be set. Failure to observe 
this rule will put the processor in a loop.
18.3.1.6  OS Bus-Lock Detection
OS bus-lock detection  is a feature that causes the processor to generate a debug exception (called a bus-lock 
detection debug exception ) if it detects that a bus lock has been asserted (see Section 9.1.2). Such an excep-
tion is a trap-class exception, because it is generated afte r execution of an instruction that asserts a bus lock. The 
exception thus does not prevent assert ion of the bus lock. Delivery of a bus-lock detection debug exception clears 
DR6.BLD.
Software can enable OS bus-lock detection by setting  IA32_DEBUGCTL.BLD[bit 2]. Bus-lock detection debug 
exceptions occur only if CPL > 0.
18.3.2 Breakpoint Exception (#BP)—Interrupt Vector 3
The breakpoint exception (interrupt 3) is caused by  execution of an INT3 instruction. See Chapter 6, 
“Interrupt 3—Breakpoint Exception (#BP).” Debuggers use br eakpoint exceptions in the same way that they use 
the breakpoint registers; that is, as a mechanism for suspending program execution to examine registers and 
memory locations. With earlier IA-32 processors, breakpoint exceptions are used extensively for setting instruction breakpoints.
With the Intel386 and later IA-32 processors, it is more convenient to set breakpoints with the breakpoint-address 
registers (DR0 through DR3). However, the breakpoint ex ception still is useful fo r breakpointing debuggers, 18-12 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
because a breakpoint exception can call a separate exception handler. The breakpoint exception is also useful when 
it is necessary to set more breakpoints than there are de bug registers or when breakpoints are being placed in the 
source code of a program under development.
18.3.3 Debug Exceptions, Breakpoint Except ions, and Restricted Transactional Memory 
(RTM)
Chapter 16, “Programming with Intel® Transactional Synchronization Extensions,” of Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 1, describes Rest ricted Transactional Memory (RTM). This is an instruc-
tion-set interface that allows software to identify transactional regions  (or critical sections) using the XBEGIN 
and XEND instructions.
Execution of an RTM transactional region begins with an XB EGIN instruction. If execution of the region successfully 
reaches an XEND instruction, the processor ensures that  all memory operations performed within the region 
appear to have occurred instantaneously when viewed from other logical processors. Execution of an RTM transac-tion region does not succeed if the processor cannot commit the updates atomically. When this happens, the 
processor rolls back the execution, a process referred to as a transactional abort . In this case, the processor 
discards all updates performed in the region, restores arch itectural state to appear as if the execution had not 
occurred, and resumes execution at a fallback instruction address that was specified with the XBEGIN instruction.
If debug exception (#DB) or breakpoint exception (#BP) o ccurs within an RTM transaction region, a transactional 
abort occurs, the processor sets EAX[4], and no exception is delivered.
Software can enable advanced debugging of RTM transactional regions  by setting DR7.RTM[bit 11] and 
IA32_DEBUGCTL.RTM[bit 15]. If these bits are both set, th e transactional abort caused by a #DB or #BP within an 
RTM transaction region does not resume execution at the fallback instruction address specified with the XBEGIN 
instruction that begin the region. Instead, execution is resu med at that XBEGIN instructio n, and a #DB is delivered. 
(A #DB is delivered even if the transactional abort was caused by a #BP.) Such a #DB will clear DR6.RTM[bit 16] 
(all other debug exceptions set DR6[16]).
18.4 LAST BRANCH, INTERRUPT, AN D EXCEPTION RECORDING OVERVIEW
P6 family processors introduced the ability to set brea kpoints on taken branches, interrupts, and exceptions, and

P6 family processors introduced the ability to set brea kpoints on taken branches, interrupts, and exceptions, and 
to single-step from one branch to the next. This capabilit y has been modified and extended in the Pentium 4, Intel 
Xeon, Pentium M, Intel® Core™ Solo, Intel® Core™ Duo, Intel® Core™2 Duo, Intel® Core™ i7 and Intel Atom® 
processors to allow logging of branch trace messages in a branch trace store (BTS) buffer in memory. 
See the following sections for processor specific implementation of last branch, interrupt, and exception recording:
— Section 18.5, “Last Branch, Interrupt, and Except ion Recording (Intel® Core™ 2 Duo and Intel Atom® 
Processors).”
— Section 18.6, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on 
Goldmont Microarchitecture.”
— Section 18.9, “Last Branch, Interrupt, and Exception Recording for Processors based on Nehalem Microar-
chitecture.”
— Section 18.10, “Last Branch, Interrupt, and Except ion Recording for Processors based on Sandy Bridge 
Microarchitecture.”
— Section 18.11, “Last Branch, Call Stack, Interrupt , and Exception Recording for Processors based on 
Haswell Microarchitecture.”
— Section 18.12, “Last Branch, Call Stack, Interrupt , and Exception Recording for Processors based on 
Skylake Microarchitecture.”
— Section 18.14, “Last Branch, Interrupt, and Except ion Recording (Intel® Core™ Solo and Intel® Core™ 
Duo Processors).”
— Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”
— Section 18.16, “Last Branch, Interrupt, and Exception Recording (P6 Family Processors).”Vol. 3B 18-13DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
The following subsections of Section 18.4 describe commo n features of profiling branches. These features are 
generally enabled using the IA32_DEBUGCTL MSR (older processor may have implemented a subset or model-
specific features, see definitions of MSR_ DEBUGCTLA, MSR_DEBUGCTLB, MSR_DEBUGCTL).
18.4.1 IA32_DEBUGCTL MSR
The IA32_DEBUGCTL MSR provides bit field controls to enable de bug trace interrupts, debug trace stores, trace 
messages enable, single stepping on branches, last branch record recording, and to co ntrol freezing of LBR stack 
or performance counters on a PMI request. IA32_D EBUGCTL MSR is located at register address 01D9H. 
See Figure 18-3 for the MSR layout and the bullets below for a description of the flags:
•LBR (last branch/interrupt/e xception) flag (bit 0) — When set, the processor records a running trace of 
the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug exception being generated) in the last branch record (LBR) stac k. For more information, see the Section 18.5.1, “LBR 
Stack” (Intel
® Core™2 Duo and Intel Atom® processor family) and Section 18.9.1, “LBR Stack” (processors 
based on Nehalem microarchitecture).
•BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS 
register as a “single-step on branches” flag rather than a “single-step on instructions” flag. This mechanism 
allows single-stepping the processor on taken branches . See Section 18.4.3, “Single-Stepping on Branches,” 
for more information about the BTF flag.
•BLD (bus-lock detection) flag (bit 2) —  If this bit is set, OS bus-lock detection is enabled when CPL > 0. 
See Section 18.3.1.6.
•TR (trace message enable) flag (bit 6) — When set, branch trace messages are enabled. When the 
processor detects a taken branch, interrupt, or exception; it sends the branch record out on the system bus as a branch trace message (BTM). See Section 18.4.4, “Branch Trace Messages,” for more information about the 
TR flag.
•BTS (branch trace stor e) flag (bit 7) — When set, the flag enables BTS facilities to log BTMs to a memory-
resident BTS buffer that is part of the DS save area. See Section 18.4.9, “BTS and DS Save Area.”
•BTINT (branch trace interrupt) flag (bit 8) — When set, the BTS facilities generate an interrupt when the 
BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 18.4.5, “Branch 
Trace Store (BTS),” for a description of this mechanism.
Figure 18-3.  IA32_DEBUGCTL MSR for Processors Based on Intel® Core™ MicroarchitectureRTM
FREEZE_WHILE_SMM
FREEZE_PERFMON_ON_PMIFREEZE_LBRS_ON_PMI
BTS_OFF_USR — BTS off in user code
BTS_OFF_OS — BTS off in OS
BTINT — Branch trace interrupt
BTS — Branch trace store
TR — Trace messages enable
Reserved
BTF — Single-step on branches
LBR — Last branch/interrupt/exception0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 31
Reserved
BLD — Bus-lock detection
Reserved18-14 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
•BTS_OFF_OS (branch trace off in privileged code) flag (bit 9) — When set, BTS or BTM is skipped if CPL 
is 0. See Section 18.13.2.
•BTS_OFF_USR (branch trace off in user code) flag (bit 10) — When set, BTS or BTM is skipped if CPL is 
greater than 0. See Section 18.13.2.
•FREEZE_LBRS_ON_PMI flag (bit 11) — When set, the LBR stack is frozen on a hardware PMI request (e.g., 
when a counter overflows and is configured to trigger PMI). See Section 18.4.7 for details.
•FREEZE_PERFMON_ON_PMI flag (bit 12) — When set, the performance counters (IA32_PMCx and IA32_-
FIXED_CTRx) are frozen on a PMI request. See Section 18.4.7 for details. 
•FREEZE_WHILE_SMM (bit 14) — If this bit is set, upon the delivery of an SMI, the processor will clear all the 
enable bits of IA32_PERF_GLOBAL_CTRL, save a copy of the content of IA32_DEBUGCTL and disable LBR, BTF, 
TR, and BTS fields of IA32_DEBUGCTL be fore transferring control to the SMI handler. If Intel Thread Director 
support was enabled before transferring control to the SM I handler, then the processor will also reset the Intel 
Thread Director history (see Section 15.6.11 for more de tails about Intel Thread Director enable, reset, and 
history reset operations).
Subsequently, the enable bits of IA32_PERF_GLOBAL_CTR L will be set to 1, the saved copy of IA32_DEBUGCTL 
prior to SMI delivery will be restored, after the SMI handle r issues RSM to complete its service. If Intel Thread 
Director support is enabled when RSM is executed, then the processor resets the Intel Thread Director history.
Note that system software must check if the pr ocessor supports the IA32_DEBUGCTL.FREEZE_WHILE_SMM 
control bit. IA32_DEBUGCTL.FREEZE_WHILE_S MM is supported if IA32_PERF_CAPABIL-
ITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See Se ction 20.8 for details of detecting the presence of 
IA32_PERF_CAPABILITIES MSR.
•RTM (bit 15)  — If this bit is set, advanced debugging of RT M transactional regions is enabled if DR7.RTM is 
also set. See Section 18.3.3.
18.4.2 Monitoring Branches, Exceptions, and Interrupts
When the LBR flag (bit 0) in the IA32_DEBUGCTL MSR is set, the processor automatically begins recording branch 
records for taken branches, interrupts, and exceptions (except for debug exceptions) in the LBR stack MSRs.
When the processor generates a debug exception (#DB), it automatically clears the LBR flag before executing the 
exception handler. This action does not clear previously stored LBR stack MSRs.
A debugger can use the linear addresses in the LBR stack to  re-set breakpoints in the breakpoint address registers 
(DR0 through DR3). This allows a backward trace from the manifestation of a particular bug toward its source.
On some processors, if the LBR flag is cleared and TR flag in the IA32_DEBUGCTL MS R remains set, the processor 
will continue to update LBR stack MSRs. This is because those processors use the entries in the LBR stack in the 
process of generating BTM/BTS records. A #D B does not automatically clear the TR flag.
18.4.3 Single-Stepping on Branches
When software sets both the BTF flag (bit 1) in the IA 32_DEBUGCTL MSR and the TF flag in the EFLAGS register, 
the processor generates a single-step debug exception only after instructions that cause a branch.2 This mecha-
nism allows a debugger to single-step on control transfers caused by branches. This “branch single stepping” helps 
isolate a bug to a particular block of code before in struction single-stepping further narrows the search. The 
processor clears the BTF flag when it generates a debu g exception. The debugger must set the BTF flag before 
resuming program execution to continue single-stepping on branches.
2. Executions of CALL, IRET, and JMP that cause task switches ne ver cause single-step debug exceptions (regardless of the value of the 
BTF flag). A debugger desiring debug exceptions on switches to a task should set the T flag (debug trap flag) in the TSS of tha t task. 
See Section 8.2.1, “Task-State Segment (TSS).”Vol. 3B 18-15DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.4.4 Branch Trace Messages
Setting the TR flag (bit 6) in the IA32_DEBUGCTL MSR enables branch trace messages (BTMs). Thereafter, when

Setting the TR flag (bit 6) in the IA32_DEBUGCTL MSR enables branch trace messages (BTMs). Thereafter, when 
the processor detects a branch, exception, or interrupt, it  sends a branch record out on the system bus as a BTM. 
A debugging device that is monitoring the system bus can read these messages and synchronize operations with 
taken branch, interrupt, and exception events. 
When interrupts or exceptions occur in conjunction with a taken branch, additional BTMs are sent out on the bus, 
as described in Section 18.4.2, “Monitor ing Branches, Exceptions, and Interrupts.”
For the P6 processor family, Pentium M processor family, and processors based on Intel Core microarchitecture, TR 
and LBR bits can not be set at the same time due to ha rdware limitation. The content of LBR stack is undefined 
when TR is set. 
For processors with Intel NetBurst microarchitecture, Inte l Atom processors, and Intel Core and related Intel Xeon 
processors both starting with the Nehalem microarchitecture, the processor can collect branch records in the LBR 
stack and at the same time send/store BTMs when both  the TR and LBR flags are set in the IA32_DEBUGCTL MSR 
(or the equivalent MSR_DEBUGCTLA, MSR_DEBUGCTLB).
The following exception applies:
•BTM may not be observable on Intel Atom processor families that do not provide an externally visible system 
bus (i.e., processors based on the Silvermont microarchitecture or later).
18.4.4.1  Branch Tr ace Message Visibility
Branch trace message (BTM) visibility is implementation spec ific and limited to systems with a front side bus (FSB). 
BTMs may not be visible to newer system link interfaces or a system bus that deviates from a traditional FSB.
18.4.5 Branch Trace Store (BTS)
A trace of taken branches, interrupts, and exceptions is us eful for debugging code by providing a method of deter-
mining the decision path taken to reach a particular code location. The LBR flag (bit 0) of IA32_DEBUGCTL provides 
a mechanism for capturing records of taken branches, inte rrupts, and exceptions and saving them in the last 
branch record (LBR) stack MSRs, setting the TR flag for se nding them out onto the system bus as BTMs. The branch 
trace store (BTS) mechanism provides the additional capab ility of saving the branch records in a memory-resident 
BTS buffer, which is part of the DS save area. The BTS buffer can be configured to be circular so that the most recent branch records are always available or it can be configured to generate an in terrupt when the buffer is 
nearly full so that all the branch records can be saved. Th e BTINT flag (bit 8) can be used to enable the generation 
of interrupt when the BTS buffer is full. See Section 18.4.9 .2, “Setting Up the DS Save Area,” for additional details.
Setting this flag (BTS) alone can greatly reduce the pe rformance of the processor. CPL-qualified branch trace 
storing mechanism can help mitigate the performanc e impact of sending/logging branch trace messages.
18.4.6 CPL-Qualified Branch Trace Mechanism
CPL-qualified branch trace mechanism is available to a su bset of Intel 64 and IA-32 processors that support the 
branch trace storing mechanism. The processor supp orts the CPL-qualified branch trace mechanism if 
CPUID.01H:ECX[bit 4] = 1.
The CPL-qualified branch trace mechanism is described in Section 18.4.9.4. System software can selectively 
specify CPL qualification to not send/store Branch Trace Me ssages associated with a specified privilege level. Two 
bit fields, BTS_OFF_USR (bit 10) and BTS_OFF_OS (bit 9), ar e provided in the debug control register to specify the 
CPL of BTMs that will not be logged in  the BTS buffer or sent on the bus.
18.4.7 Freezing LBR and Performance Counters on PMI 
Many issues may generate a performance monitoring inte rrupt (PMI); a PMI service handler will need to determine 
cause to handle the situation. Two capabilities that a llow a PMI service routine to improve branch tracing and 
performance monitoring are available for processors supporting architectural performance monitoring version 2 or 18-16 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
greater (i.e., CPUID.0AH:EAX[7:0] > 1). These capabilities  provides the following interface in IA32_DEBUGCTL to 
reduce runtime overhead of PMI servicing, profiler-cont ributed skew effects on analysis or counter metrics:
•Freezing LBRs on PMI (bit 11) — Allows the PMI service routine to en sure the content in the LBR stack are 
associated with the target workload and not polluted by the branch flows of handling the PMI. Depending on the 
version ID enumerated by CPUID.0AH:EAX.ArchPe rfMonVerID[bits 7:0], two flavors are supported:
— Legacy Freeze_LBR_on_PMI is supported for ArchPe rfMonVerID <= 3 and ArchPerfMonVerID >1. If 
IA32_DEBUGCTL.Freeze_LBR_On_PMI = 1, the LBR is fr ozen on the overflowed condition of the buffer 
area, the processor clears the LBR bit (bit 0) in IA32_DEBUGCTL. Software must then re-enable IA32_DE-
BUGCTL.LBR to resume recording branches. When usin g this feature, software should be careful about 
writes to IA32_DEBUGCTL to avoid re-enabling LB Rs by accident if they were just disabled.
— Streamlined Freeze_LBR_on_PMI is supported for Ar chPerfMonVerID >= 4. If IA32_DEBUGCTL.Freeze_L-
BR_On_PMI = 1, the processor behaves as follows:
•sets IA32_PERF_GLOBAL_STATUS.LBR_Frz =1 to disa ble recording, but does not change the LBR bit 
(bit 0) in IA32_DEBUGCTL. The LBRs are frozen on  the overflowed conditio n of the buffer area.
•Freezing PMCs on PMI (bit 12) — Allows the PMI service routine to ensure the content in the performance 
counters are associated with the target workload and not polluted by the PMI and activities within the PMI 
service routine. Depending on the version ID enumerat ed by CPUID.0AH:EAX.ArchPerfMonVerID[bits 7:0], two 
flavors are supported:
— Legacy Freeze_Perfmon_on_PMI is supported for Arch PerfMonVerID <= 3 and ArchPerfMonVerID >1. If 
IA32_DEBUGCTL.Freeze_Perfmon_On_PMI = 1, the pe rformance counters are frozen on the counter 
overflowed condition when the processor clears the IA32_PERF_GLOBAL_CTRL MSR (see Figure 20-3). The 
PMCs affected include both genera l-purpose counters and fixed-function counters (see Section 20.6.2.1, 
“Fixed-function Performance Counters”). Software mu st re-enable counts by writing 1s to the corre-
sponding enable bits in IA32_PERF_GLOBAL_CTRL before  leaving a PMI service routine to continue counter 
— Streamlined Freeze_Perfmon_on_PMI is supported for ArchPerfMonVerID >= 4. The processor behaves as 
follows:
•sets IA32_PERF_GLOBAL_STATUS.CTR_Frz =1 to disabl e counting on a counter overflow condition, but 
does not change the IA32_PERF_GLOBAL_CTRL MSR. 
Freezing LBRs and PMCs on PMIs (both legacy and streamlined operation) occu r when one of the following applies:
•A performance counter had an overflow and was programmed to signal a PMI in case of an overflow.
— For the general-purpose counters; enabling PMI is done by setting bit 20 of the IA32_PERFEVTSELx 
register.
— For the fixed-function counters; enabling PMI is done  by setting the 3rd bit in the corresponding 4-bit 
control field of the MSR_PERF_FIXED_CTR_CTRL regist er (see Figure 20-1) or IA32_FIXED_CTR_CTRL MSR 
(see Figure 20-2).
•The PEBS buffer is almost full and reaches the interrupt threshold.
•The BTS buffer is almost full and reaches the interrupt threshold.
Table 18-3 compares the interaction of the processor with  the PMI handler using the legacy versus streamlined 
Freeza_Perfmon_On_PMI interface.Vol. 3B 18-17DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.4.8 LBR Stack 
The last branch record stack and top-of-stack (TOS ) pointer MSRs are supported across Intel 64 and IA-32 
processor families. However, the number of MSRs in the LBR stack and the valid range of TOS pointer value can 
vary between different processor families. Table 18-4 lists  the LBR stack size and TOS pointer range for several 
processor families according to the CPUID signatures of DisplayFamily_DisplayModel encoding (see the CPUID 
instruction in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). Table 18-3.   Legacy and Streamlined Operation wi th Freeze_Perfmon_On_PMI = 1, Counter Overflowed 
Legacy Freeze_Perfmon_On_PMI Stream lined Freeze_Perfmon_On_PMI Comment
Processor freezes the counters on 
overflowProcessor freezes the counte rs on overflow Unchanged
Processor clears 
IA32_PERF_GLOBAL_CTRLProcessor set IA32_PERF _GLOBAL_STATUS.CTR_FTZ
Handler reads 
IA32_PERF_GLOBAL_STATUS (0x38E) to examine which counter(s) overflowedmask  = RDMSR(0x38E) Similar
Handler services the PMI Handler services the PMI Unchanged
Handler writes 1s to 
IA32_PERF_GLOBAL_OVF_CTL (0x390) Handler writes mask  into 
IA32_PERF_GLOBAL_OVF_RESET (0x390) 
IA32_PERF_GLOBAL_STATUSProcessor clears IA32_PERF_GLOBAL_STATUS Unchanged
Handler re-enables 
IA32_PERF_GLOBAL_CTRLNone Reduced software overhead

Table 18-4.   LBR Stack Size and TOS Pointer Range 
DisplayFamily_DisplayMod el Size of LBR Stack Component of an LBR Entry Range of TOS Pointer
06_5CH, 06_5FH 32 FROM_IP, TO_IP 0 to 31
06_4EH, 06_5EH, 06_8E H, 06_9EH, 06_55H, 
06_66H, 06_7AH, 06_67H, 06_6AH, 06_6CH, 06_7DH, 06_7EH, 06_8C H, 06_8DH, 06_6AH, 
06_A5H, 06_A6H, 06_A7 H, 06_A8H, 06_86H, 
06_8AH, 06_96H, 06_9CH32 FROM_IP, TO_IP, LBR_INFO1
NOTES:
1. See Section 18.12.0 to 31
06_3DH, 06_47H, 06_4F H, 06_56H, 06_3CH, 
06_45H, 06_46H, 06_3FH,  06_2AH, 06_2DH, 
06_3AH, 06_3EH, 06_1A H, 06_1EH, 06_1FH, 
06_2EH, 06_25H, 06_2CH, 06_2FH16 FROM_IP, TO_IP 0 to 15
06_17H, 06_1DH, 06_0FH 4F R O M _ I P ,  T O _ I P 0  t o  3
06_37H, 06_4AH, 06_4CH, 06_4DH, 06_5AH, 
06_5DH, 06_1CH, 06_26H, 06_27H, 06_35H, 
06_36H8F R O M _ I P ,  T O _ I P 0  t o  718-18 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
The last branch recording mechanism tracks not only branch  instructions (e.g., JMP, Jcc, LOOP, and CALL instruc-
tions), but also other operations that cause a change in th e instruction pointer (e.g., ex ternal interrupts, traps, and 
faults). The branch recording mechanisms generally employs a set of MSRs, referred to as last branch record (LBR) 
stack. The size and exact locations of the LBR stack are generally model-specific (see Chapter 2, “Model-Specific 
Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, for model-
specific MSR addresses). 
•Last Branch Record (LBR) Stack — The LBR consists of N pairs of MSRs (N is listed in the LBR stack size 
column of Table 18-4) that store source and destination address of recent branches (see Figure 18-3): 
— MSR_LASTBRANCH_0_FROM_IP (address is model spec ific) through the next consecutive (N-1) MSR 
address store source addresses.
— MSR_LASTBRANCH_0_TO_IP (address is model specific ) through the next consecutive (N-1) MSR address 
store destination addresses.
•Last Branch Record Top-of-Stack (TOS) Pointer — The lowest significant M bits of the TOS Pointer MSR 
(MSR_LASTBRANCH_TOS, address is model specific) contains  an M-bit pointer to the MSR in the LBR stack that 
contains the most recent branch, interrupt, or exception recorded. The valid range of the M-bit POS pointer is 
given in Table 18-4.
18.4.8.1  LBR Stack and Intel® 64 Processors 
LBR MSRs are 64-bits. In 64-bit mode, last branch records store the full address. Outside of 64-bit mode, the upper 
32-bits of branch addresses will be stored as 0. 
Software should query an architectural MSR IA32_PERF_CAP ABILITIES[5:0] about the format of the address that 
is stored in the LBR stack. Four format s are defined by the following encoding:
—000000B (32-bit record format) — Stores 32-bit offset in current CS of respective source/destination,
—000001B (64-bit LIP record format) — Stores 64-bit linear address of respective source/destination,
—000010B (64-bit EIP record format) — Stores 64-bit offset (effective address) of respective 
source/destination.
—000011B (64-bit EIP record format) and Flags  — Stores 64-bit offset (effective address) of respective 
source/destination. Misprediction info is reported in the upper bit of 'FROM' registers in the LBR stack. See 
LBR stack details below for fl ag support and definition.
—000100B (64-bit EIP record format), Flags, and TSX — Stores 64-bit offset (effective address) of 
respective source/destination. Misprediction and TSX info are reported in the upper bits of ‘FROM’ registers 
in the LBR stack. 
—000101B (64-bit EIP record format), Flags, TSX, and LBR_INFO — Stores 64-bit offset (effective 
address) of respective source/destination. Mispredictio n, TSX, and elapsed cycles since the last LBR update 
are reported in the LBR_INFO MSR stack. 
—000110B (64-bit LIP record format), Flags, and Cycles — Stores 64-bit linear address (CS.Base + 
effective address) of respective so urce/destination. Misprediction info is reported in the upper bits of Figure 18-4.  64-bit Address Layout of LBR MSR 63
Source Address0
0 63
Destination AddressMSR_LASTBRANCH_0_FROM_IP through MSR_LASTBRANCH_(N-1)_FROM_IP
MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_(N-1)_TO_IPVol. 3B 18-19DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
'FROM' registers in the LBR stack. Elapsed cycles since the last LBR update are reported in the upper 16 bits 
of the 'TO' registers in the LBR stack (see Section 18.6). 
—000111B (64-bit LIP record format), Flags, and LBR_INFO — Stores 64-bit linear address (CS.Base 
+ effective address) of respective source/destination. Misprediction, and elapsed cycles since the last LBR 
update are reported in the LBR_INFO MSR stack.
Processor’s support for the architectural MSR IA32_PERF_ CAPABILITIES is provided by CPUID.01H:ECX[PERF_CA-
PAB_MSR] (bit 15).
18.4.8.2  LBR Stack and IA-32 Processors 
The LBR MSRs in IA-32 processors introduced prior to Inte l 64 architecture store the 32-bit “To Linear Address” and 
“From Linear Address” using the high and low half of each 64-bit MSR. 
18.4.8.3  Last Exception Reco rds and Intel 64 Architecture
Intel 64 and IA-32 processors also provide MSRs that store the branch record for the last branch taken prior to an 
exception or an interrupt. The location of the last except ion record (LER) MSRs are model specific. The MSRs that 
store last exception records are 64-bits. If IA-32e mode is disabled, only the lower 32-bits of the address is 
recorded. If IA-32e mode is enabled, the processor writes  64-bit values into the MSR. In 64-bit mode, last excep-
tion records store 64-bit addresses; in compatibility mode , the upper 32-bits of last exception records are cleared.
18.4.9 BTS and DS Save Area
The Debug store (DS)  feature flag (bit 21), returned by CPUID.1:EDX[21] indicates that the processor provides 
the debug store (DS) mechanism. The DS mechanism allows: 
•BTMs to be stored in a memory-resident BTS buff er. See Section 18.4.5, “Branch Trace Store (BTS).” 
•Processor event-based sampling (PEBS) also uses the DS  save area provided by debug store mechanism. The 
capability of PEBS varies across different microarc hitectures. See Section 20.6.2.4, “Processor Event Based 
Sampling (PEBS),” and the relevant PEBS sub-sections across the core PMU sections in Chapter 20, “Perfor-
mance Monitoring.” 
When CPUID.1:EDX[21] is set:
•The BTS_UNAVAILABLE and PEBS_UNAVAILABLE flags in the IA32_MISC_ENABLE MSR indicate (when clear) 
the availability of the BTS and PEBS facilities, including the ability to set the BTS and BTINT bits in the 
appropriate DEBUGCTL MSR.
•The IA32_DS_AREA MSR exists and points to the DS save area. 
The debug store (DS) save area is a software-designated ar ea of memory that is used to collect the following two 
types of information:
•Branch records — When the BTS flag in the IA32_DEBUGCTL MSR is set, a branch record is stored in the BTS 
buffer in the DS save area whenever a taken branch, interrupt, or exception is detected. 
•PEBS records — When a performance counter is configured for PEBS, a PEBS record is stored in the PEBS 
buffer in the DS save area after the counter overflow occu rs. This record contains the architectural state of the 
processor (state of the 8 general purpose registers, EI P register, and EFLAGS register) at the next occurrence 
of the PEBS event that caused the counter to overfl ow. When the state information has been logged, the 
counter is automatically reset to a specified value, an d event counting begins again. The content layout of a 
PEBS record varies across different implementations th at support PEBS. See Section 20.6.2.4.2 for details of 
enumerating PEBS record format.18-20 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
NOTES
Prior to processors based on the Goldmont microarchitecture, PEBS facility only supports a subset 
of implementation-specific precise events. See Section 20.5.3.1 for a PEBS enhancement that can 
generate records for both precise and non-precise events.
The DS save area and recording mechanism are disabled on INIT, processor Reset or transition to 
system-management mode (SMM) or IA-32e mode. It is similarly disabled on the generation of a 
machine-check exception on 45nm and 32nm Intel Atom processors and on processors with 
Netburst or Intel Core microarchitecture.
The BTS and PEBS facilities may not be available on all processors. The availability of these facilities 
is indicated by the BTS_UNAVAILABLE and PEBS_UNA VAILABLE flags, respectively, in the IA32_-
MISC_ENABLE MSR (see Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 4).
The DS save area is divided into thr ee parts: buffer management area, bran ch trace store (BTS) buffer, and PEBS 
buffer (see Figure 18-5). The buffer management area is used  to define the location and size of the BTS and PEBS

buffer (see Figure 18-5). The buffer management area is used  to define the location and size of the BTS and PEBS 
buffers. The processor then uses the buffer management ar ea to keep track of the branch and/or PEBS records in 
their respective buffers and to record the performance counter reset value. Th e linear address of the first byte of 
the DS buffer management area is specified with the IA32_DS_AREA MSR.
The fields in the buffer mana gement area are as follows: 
•BTS buffer base — Linear address of the first byte of the BTS bu ffer. This address should point to a natural 
doubleword boundary.
•BTS index  — Linear address of the first byte of the next BTS record to be written to. Initially, this address 
should be the same as the address in the BTS buffer base field.
•BTS absolute maximum  — Linear address of the next byte past the end of the BTS buffer. This address should 
be a multiple of the BTS record size (12 bytes) plus 1.
•BTS interrupt threshold  — Linear address of the BTS record on which an interrupt is to be generated. This 
address must point to an offset from the BTS buffer base that is a multiple of the BTS record size. Also, it must 
be several records short of the BTS absolute maximum a ddress to allow a pending interrupt to be handled prior 
to processor writing the BTS absolute maximum record.
•PEBS buffer base — Linear address of the first byte of the PEBS buffer. This address should point to a natural 
•PEBS index  — Linear address of the first byte of the next PEBS record to be written to. Initially, this address 
should be the same as the address in the PEBS buffer base field.
•PEBS absolute maximum  — Linear address of the next byte past th e end of the PEBS buffer. This address 
should be a multiple of the PEBS record size (40 bytes) plus 1.
•PEBS interrupt threshold — Linear address of the PEBS record on whic h an interrupt is to be generated. This 
address must point to an offset from the PEBS buffer base  that is a multiple of the PEBS record size. Also, it 
must be several records short of the PEBS absolute maximum address to allow a pending interrupt to be handled prior to processor writing the PEBS absolute maximum record.
•PEBS counter reset value — A 64-bit value that the counter is to be se t to when a PEBS record is written. Bits 
beyond the size of the counter are ignored. This value allows state information to be collected regularly every 
time the specified number of events occur. Vol. 3B 18-21DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
Figure 18-6 shows the structure of a 12-byte branch record  in the BTS buffer. The fields in each record are as 
follows:
•Last branch from — Linear address of the instruction from which the branch, interrupt, or exception was 
taken.
•Last branch to — Linear address of the branch target or the fi rst instruction in the interrupt or exception 
service routine.
•Branch predicted — Bit 4 of field indicates whether the branch that was taken was predicted (set) or not 
predicted (clear).Figure 18-5.  DS Save Area Example1
NOTES:
1. This example represents the format for a sy stem that supports PEBS  on only one counter.BTS Buffer Base
BTS Index
BTS Absolute 
BTS Interrupt 
PEBS Absolute
PEBS Interrupt
PEBS  MaximumMaximum
Threshold
PEBS IndexPEBS Buffer Base
Threshold
Counter Reset
Reserved0H
4H
8H
CH
10H
14H
18H
1CH
20H
24H
30HBranch Record 0
Branch Record 1
Branch Record n
PEBS Record 0
PEBS Record 1
PEBS Record nBTS Buffer
PEBS BufferDS Buffer Management AreaIA32_DS_AREA MSR18-22 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
Figure 18-7 shows the structure of the 40-byte PEBS record s. Nominally the register values are those at the begin-
ning of the instruction that caused the event. However,  there are cases where the registers may be logged in a 
partially modified state. The linear IP field shows the value in the EIP register translated from an offset into the 
current code segment to a linear address.
18.4.9.1  64 Bit Format of the DS Save Area
When DTES64 = 1 (CPUID.1.ECX[2] = 1), the structure of the DS save area is shown in Figure 18-8. 
When DTES64 = 0 (CPUID.1.ECX[2] = 0) and IA-32e mode is active, the structure of the DS save area is shown in 
Figure 18-8. If IA-32e mode is not active the structur e of the DS save area is as shown in Figure 18-5.Figure 18-6.  32-bit Branch Trace Record Format
Figure 18-7.  PEBS Record FormatLast Branch From
Last Branch To
Branch Predicted0H
4H
8H0 31 4
EFLAGS 0H
4H
8H0 31
Linear IP
10H
18H14H
1CH
20H
24HCHEAX
EBX
ECX
EDX
ESI
EDI
EBP
ESPVol. 3B 18-23DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
The IA32_DS_AREA MSR holds the 64-bit linear address of the first byte of the DS buffer management area. The 
structure of a branch trace record is similar to that show n in Figure 18-6, but each field is 8 bytes in length. This 
makes each BTS record 24 bytes (see Figure 18-9). The stru cture of a PEBS record is similar to that shown in 
Figure 18-7, but each field is 8 bytes in length and architec tural states include register R8 through R15. This makes 
the size of a PEBS record in 64-bit mode 144 bytes (see Figure 18-10).Figure 18-8.  IA-32e Mode DS Save Area Example1 
NOTES:
1. This example represents the format for a sy stem that supports PEBS  on only one counter.
Figure 18-9.  64-bit Branch Trace Record FormatBTS Buffer Base
BTS Index
Threshold
Threshold
8H
10H
18H
20H
28H
30H
38H
40H
48H
50HBranch Record 0
PEBS BufferDS Buffer Management AreaIA32_DS_AREA MSR
Last Branch From
8H
10H0 63 418-24 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
Fields in the buffer management area of a DS  save area are described in Section 18.4.9. 
The format of a branch trace record an d a PEBS record are the same as the 64 -bit record formats shown in Figures 
18-9 and Figures 18-10, with the exception that the branch predicted bit is not supported by Intel Core microarchi-
tecture or Intel Atom microarchitecture. The 64-bit record formats for BTS and PEBS apply to DS save area for all 
The procedures used to program IA32_DEBUGCTL MSR to se t up a BTS buffer or a CPL-qualified BTS are described 
in Section 18.4.9.3 and Section 18.4.9.4.
Required elements for writing a DS interrupt service routin e are largely the same on processors that support using 
DS Save area for BTS or PEBS records. Howe ver, on processors based on Intel NetBurst® microarchitecture, re-
enabling counting requires writing to CCCRs. But a DS inte rrupt service routine on processors supporting architec-
tural performance monitoring should:
•Re-enable the enable bits in IA32_PERF_GLOBAL_CTRL MSR if it is servicing an overflow PMI due to PEBS.
•Clear overflow indications by writing to IA32_PERF_ GLOBAL_OVF_CTRL when a counting configuration is 
changed. This includes bit 62 (ClrOv fBuffer) and the overflow indication of counters used in either PEBS or 
general-purpose counting (specifically: bits 0 or 1; see Figures 20-3).
18.4.9.2  Setting Up the DS Save Area
To save branch records with the BTS buffer, the DS save ar ea must first be set up in memory as described in the 
following procedure (See Section 20.6.2.4 .1, “Setting up the PEBS Buffer,” for instructions for setting up a PEBS 
buffer, respectively, in the DS save area):
1. Create the DS buffer management information area in  memory (see Section 18.4.9, “BTS and DS Save Area,” 
and Section 18.4.9.1, “64 Bit Format of the DS Save Ar ea”). Also see the additional notes in this section.
2. Write the base linear address of the DS buffer  management area into the IA32_DS_AREA MSR. 
3. Set up the performance counter entry in the xAPIC LVT for fixed delivery and edge sensitive. See Section 
11.5.1, “Local Vector Table.”
4. Establish an interrupt handler in the IDT for the vector associated with the performance counter entry in the 
xAPIC LVT.Figure 18-10.  64-bit PEBS Record FormatRFLAGS 0H
8H
10H0 63
RIP
20H
30H28H
38H
40H
48H18HRAX
RBX
RCX
RDX
RSI
RDI
RBP
RSP
R8
...
R1550H
...
88HVol. 3B 18-25DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
5. Write an interrupt service routine to handle the inte rrupt. See Section 18.4.9.5, “Writing the DS Interrupt 
Service Routine.”
The following restrictions should be applied to the DS save area.
•The recording of branch records in the BTS buffer (o r PEBS records in the PEBS buffer) may not operate 
properly if accesses to the linear addresses in any of the three DS save area sections cause page faults, VM 
exits, or the setting of accessed or dirty flags in the paging structures (ordinary or EPT). For that reason,

8H
10H0 63
RIP
20H
30H28H
38H
40H
48H18HRAX
RBX
RCX
RDX
RSI
RDI
RBP
RSP
R8
...
R1550H
...
exits, or the setting of accessed or dirty flags in the paging structures (ordinary or EPT). For that reason, 
system software should establish paging structures (both ordinary and EPT) to prevent such occurrences. 
Implications of this may be that an operating system should allocate this memory from a non-paged pool and 
that system software cannot do “lazy” page-table entry propagation for these pages. Some newer processor 
generations support “lazy” EPT page-table entry prop agation for PEBS; see Section 20.3.9.1 and Section 
20.9.5 for more information. A virtual-machine monito r may choose to allow use of  PEBS by guest software 
only if EPT maps all guest-physical  memory as present and read/write.
•The DS save area can be larger than a page, but the pages must be mapped to contiguous linear addresses. 
The buffer may share a page, so it need not be aligne d on a 4-KByte boundary. For performance reasons, the 
base of the buffer must be aligned on a doubleword boundary and should be aligned on a cache line boundary. 
•It is recommended that the buffer size for the BTS buffe r and the PEBS buffer be an integer multiple of the 
corresponding record sizes.
•The precise event records buffer should be large enough to hold the number of precise event records that can 
occur while waiting for the interrupt to be serviced.
•The DS save area should be in kernel space. It must not be on the same page as code, to avoid triggering self-modifying code actions.
•There are no memory type restrictions on the buffer s, although it is recommended that the buffers be 
designated as WB memory type for performance considerations.
•Either the system must be prevented fr om entering A20M mode while DS save area is active, or bit 20 of all 
addresses within buffer bounds must be 0.
•Pages that contain buffers must be mapped to the same physical addresses for all processes, such that any change to control register CR3 will not change the DS addresses. 
•The DS save area is expected to used only on syst ems with an enabled APIC. The LVT Performance Counter 
entry in the APCI must be initialized to use an interrupt gate instead of the trap gate.
18.4.9.3  Setting Up the BTS Buffer
Three flags in the MSR_DEBUGCTLA MSR (see Table 18- 5), IA32_DEBUGCTL (see Figure 18-3), or MSR_DE-
BUGCTLB (see Figure 18-16) control the generation of branch records and storing of them in the BTS buffer; these 
are TR, BTS, and BTINT. The TR flag enables the generati on of BTMs. The BTS flag determines whether the BTMs 
are sent out on the system bus (clear) or stored in the BTS buffer (set). BTMs cannot be simultaneously sent to the system bus and logged in the BTS buffer. The BTINT flag en ables the generation of an interrupt when the BTS buffer 
is full. When this flag is clear, the BTS buffer is a circular buffer.
The following procedure describes how to set up a DS Sa ve area to collect branch records in the BTS buffer:
1. Place values in the BTS buffer base, BTS index, BTS ab solute maximum, and BTS interrupt threshold fields of 
the DS buffer management area to set up the BTS buffer in memory.
2. Set the TR and BTS flags in the IA32_DEBUGCTL for Inte l Core Solo and Intel Core Duo processors or later 
processors (or MSR_DEBUGCTLA MSR fo r processors based on Intel NetBurst Microarchitecture; or MSR_DE-
BUGCTLB for Pentium M processors).Table 18-5.   IA32_DEBUGCTL Flag Encodings 
TR BTS BTINT Description
0 X X Branch trace messages (BTMs) off1 0 X Generate BTMs1 1 0 Store BTMs in the BTS buffer, used here as a circular buffer1 1 1 Store BTMs in the BTS buffer, and generate an interrupt when the buffer is nearly full18-26 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
3. Clear the BTINT flag in the corresponding IA32_DEB UGCTL (or MSR_DEBUGCTLA MSR; or MSR_DEBUGCTLB) 
if a circular BTS buffer is desired.
NOTES
If the buffer size is set to less than the minimum allowable value (i.e., BTS absolute maximum < 1 + size of BTS record), the results of BTS is undefined.
In order to prevent generating an interrupt, when working with circular BTS buffer, SW need to set 
BTS interrupt threshold to a value greater than BTS absolute maximum (fields of the DS buffer 
management area). It's not enough to clear the BTINT flag itself only. 
18.4.9.4  Setting Up  CPL-Qualified BTS 
If the processor supports CPL-qualified last branch reco rding mechanism, the generation of branch records and 
storing of them in the BTS buffer are determined by : TR, BTS, BTS_OFF_OS, BTS_OFF_USR, and BTINT. The 
encoding of these five bits are shown in Table 18-6.
18.4.9.5  Writing the DS Interrupt Service Routine
The BTS, non-precise event-based sampling, and PEBS fac ilities share the same interrupt vector and interrupt 
service routine (called the debug store interrupt service routine or DS ISR). To handle BTS, non-precise event-
based sampling, and PEBS interrupts: separate handler routin es must be included in the DS ISR. Use the following 
guidelines when writing a DS ISR to handle BTS, no n-precise event-based sampli ng, and/or PEBS interrupts.
•The DS interrupt service routine (ISR) must be part of a kernel driver and operate at a current privilege level of 
0 to secure the buffer storage area.
•Because the BTS, non-precise event-based sampling, and PEBS facilities share the same interrupt vector, the 
DS ISR must check for all the possible causes of inte rrupts from these facilities and pass control on to the 
appropriate handler. 
BTS and PEBS buffer overflow would be the sources of the interrupt if the buffer index matches/exceeds the 
interrupt threshold specified. Detection of non-precise event-based sampling as the source of the interrupt is accomplished by checking for counter overflow.
•There must be separate save areas, buffers, and state for each processor in an MP system.
•Upon entering the ISR, branch trace messages and PEBS sh ould be disabled to prevent race conditions during 
access to the DS save area. This is done by clearing  TR flag in the IA32_DEBUGCTL (or MSR_DEBUGCTLA MSR) 
and by clearing the precise event enable flag in the MSR_PEBS_ENABLE MSR. These settings should be restored to their original values when exiting the ISR. Table 18-6.  CPL-Qualified Branch Trace Store Encodings 
TR BTS BTS_OFF_OS BTS_OFF_ USR BTINT Description
0 X X X X Branch trace messages (BTMs) off1 0 X X X Generates BTMs but do not store BTMs1 1 0 0 0 Store all BTMs in the BTS buff er, used here as a circular buffer
1 1 1 0 0 Store BTMs with CPL > 0 in the BTS buffer1 1 0 1 0 Store BTMs with CPL = 0 in the BTS buffer1 1 1 1 X Generate BTMs but do not store BTMs1 1 0 0 1 Store all BTMs in the BTS buff er; generate an interrupt when the 
buffer is nearly full
1 1 1 0 1 Store BTMs with CPL > 0 in th e BTS buffer; generate an interrupt 
when the buffer is nearly full
1 1 0 1 1 Store BTMs with CPL = 0 in th e BTS buffer; generate an interrupt 
when the buffer is nearly fullVol. 3B 18-27DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
•The processor will not disable the DS save area when th e buffer is full and the circular mode has not been 
selected. The current DS setting must be retained and restored by the ISR on exit.
•After reading the data in the appropriate buffer, up to bu t not including the current index into the buffer, the ISR 
must reset the buffer index to the beginning of the buffer . Otherwise, everything up to the index will look like 
new entries upon the next invocation of the ISR.
•The ISR must clear the mask bit in the performance counter LVT entry.
•The ISR must re-enable the counters to count via IA32_PERF_GLOBAL_CTRL/IA32_PERF_GLOBAL_OVF_CTRL 
if it is servicing an overflow PMI due to PEBS (or via CCCR's ENABLE bit on processor based on Intel NetBurst 
microarchitecture).
•The Pentium 4 Processor and Intel Xeon Processor mask PM Is upon receiving an interrupt. Clear this condition 
before leaving the interrupt handler.
18.5 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ 2 
DUO AND INTEL ATOM® PROCESSORS)
The Intel Core 2 Duo processor family  and Intel Xeon processors based on Intel Core microarchitecture or 
enhanced Intel Core microarchitecture provide last branch interrupt and exception recording. The facilities 
described in this section also apply to 45 nm and 32 nm Intel Atom processors. These capabilities are similar to 
those found in Pentium 4 processors, including support for the following facilities:
•Debug Trace and Branch Recording Control — The IA32_DEBUGCTL MSR provide bit fields for software to 
configure mechanisms related to debug trace, branch re cording, branch trace store, and performance counter 
operations. See Section 18.4.1 for a description of the flags. See Figure 18-3 for the MSR layout.
•Last branch record (LBR) stack — There are a collection of MSR pairs that store the source and destination 
addresses related to recently executed branches. See Section 18.5.1. 
•Monitoring and single-stepping of branches, exceptions, and interrupts

— See Section 18.4.2 and Section 18.4.3. In addition, the ability to freeze the LBR stack on a PMI request is 
— 45 nm and 32 nm Intel Atom processors clear the TR flag when the FREEZE_LBRS_ON_PMI flag is set.
•Branch trace messages — See Section 18.4.4. 
•Last exception records — See Section 18.13.3. 
•Branch trace store and CPL-qualified BTS — See Section 18.4.5.
•FREEZE_LBRS_ON_PMI flag (bit 11) — see Section 18.4.7 for legacy Freeze_LBRs_On_PMI operation. 
•FREEZE_PERFMON_ON_PMI flag (bit 12) — see Section 18.4.7 for legacy Freeze_Perfmon_On_PMI 
•FREEZE_WHILE_SMM (bit 14) — FREEZE_WHILE_SMM is supported if IA32_PERF_CAPABIL-
ITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See Section 18.4.1.
18.5.1 LBR Stack 
The last branch record stack and top-of-stack (TOS) poin ter MSRs are supported across Intel Core 2, Intel Atom 
processor families, and Intel processors based on Intel NetBurst microarchitecture. 
Four pairs of MSRs are supported in the LBR stack for Inte l Core 2 processors families and Intel processors based 
on Intel NetBurst microarchitecture:
•Last Branch Record (LBR) Stack 
— MSR_LASTBRANCH_0_FROM_IP (address 40H) through MSR_LASTBRANCH_3_FROM_IP (address 43H) 
store source addresses
— MSR_LASTBRANCH_0_TO_IP (address 60H) through MSR_LASTBRANCH_3_TO_IP (address 63H) store 
destination addresses18-28 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
•Last Branch Record Top-of-Stack (TOS) Pointer — The lowest significant 2 bits of the TOS Pointer MSR 
(MSR_LASTBRANCH_TOS, address 1C9H) contains a pointer to the MSR in the LBR stack that contains the most 
recent branch, interrupt, or exception recorded.
Eight pairs of MSRs are supported in the LBR stack for 45 nm and 32 nm Intel Atom processors:
•Last Branch Record (LBR) Stack — MSR_LASTBRANCH_0_FROM_IP (address 40H) thro ugh MSR_LASTBRANCH_7_FROM_IP (address 47H) 
— MSR_LASTBRANCH_0_TO_IP (address 60H) through MSR_LASTBRANCH_7_TO_IP (address 67H) store 
destination addresses
•Last Branch Record Top-of-Stack (TOS) Pointer — The lowest significant 3 bits of the TOS Pointer MSR 
The address format written in the FROM_IP/TO_IP MSRS may differ between processors. Software should query 
IA32_PERF_CAPABILITIES[5:0] and consult Section 18.4 .8.1. The behavior of the MSR_LER_TO_LIP and the 
MSR_LER_FROM_LIP MSRs corresponds to that of the La stExceptionToIP and LastExceptionFromIP MSRs found in 
P6 family processors. 
18.5.2 LBR Stack in Intel Atom® Processors  based on the Silvermont Microarchitecture
The last branch record stack and top-of-stack (TOS) pointer MSRs are supported in Intel Atom processors based on 
the Silvermont and Airmont microarchitectures. Eight pairs of MSRs are supported in the LBR stack. 
LBR filtering is supported. Filtering of LBRs based on a comb ination of CPL and branch type  conditions is supported. 
When LBR filtering is enabled, the LBR stack only captur es the subset of branches that are specified by MSR_L-
BR_SELECT. The layout of MSR_LBR_SE LECT is described in Table 18-11.
18.6 LAST BRANCH, CALL STACK, IN TERRUPT, AND EXCEPTION RECORDING 
FOR PROCESSORS BASED ON GOLDMONT MICROARCHITECTURE
Processors based on the Goldmont microarchitecture extend  the capabilities described in Section 18.5.2 with the 
following enhancements:
•Supports new LBR format encoding 00110b in IA32_PERF_CAPABILITIES[5:0]. 
•Size of LBR stack increased to 32. Each entry incl udes MSR_LASTBRANCH_x_FROM_IP (address 0x680..0x69f) 
and MSR_LASTBRANCH_x_TO_IP (address 0x6c0..0x6df). 
• LBR call stack filtering supported. The layout of MSR_LBR_SELECT is described in Table 18-13.
• Elapsed cycle information is added to MSR_LAST BRANCH_x_TO_IP. Format is shown in Table 18-7.
• Misprediction info is reported in the upper bits of MSR_LASTBRANCH_x_FROM_IP. MISPRED bit format is 
shown in Table 18-8.
• Streamlined Freeze_LBRs_On_PMI operation; see Section 18.12.2.
• LBR MSRs may be cleared when MWAIT is used to requ est a C-state that is numerically higher than C1; see 
Section 18.12.3.
Table 18-7.   MSR_LASTBRANCH_x_TO_IP for the Goldmont Microarchitecture
Bit Field Bit Offset Access Description
Data 47:0 R/W This is the “branch to“ address. See Section 18.4.8.1 for address format.
Cycle Count 
(Saturating)63:48 R/W Elapsed core clocks sinc e last update to the LBR stack.Vol. 3B 18-29DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.7 LAST BRANCH, CALL STACK, IN TERRUPT, AND EXCEPTION RECORDING 
FOR PROCESSORS BASED ON GOLDMONT PLUS MICROARCHITECTURE
Next generation Intel Atom processors are based on the Goldmont Plus microarchitecture. Processors based on the 
Goldmont Plus microarchitecture extend the capabilitie s described in Section 18.6 with the following changes:
• Enumeration of new LBR format: encoding 00111b in IA32_PERF_CAPABILITIES[5:0] is supported, see 
Section 18.4.8.1.
• Each LBR stack entry consists of three MSRs:
— MSR_LASTBRANCH_x_FROM_IP, the layout is simplified, see Table 18-9.
— MSR_LASTBRANCH_x_TO_IP, the layout is the same as Table 18-9.
— MSR_LBR_INFO_x, stores branch prediction flag, TSX in fo, and elapsed cycle data. Layout is the same as 
Table 18-16.
18.8 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR INTEL® 
XEON PHI™ PROCESSOR 7200/5200/3200
The last branch record stack and top-of-stack (TOS) pointer MSRs are supported in the Intel® Xeon Phi™ processor 
7200/5200/3200 series based on the Knights Landing microarc hitecture. Eight pairs of MSRs are supported in the 
LBR stack, per thread:
•Last Branch Record (LBR) Stack
— MSR_LASTBRANCH_0_FROM_IP (address 680H) through MSR_LASTBRANCH_7_FROM_IP (address 687H) 
store source addresses.
— MSR_LASTBRANCH_0_TO_IP (address 6C0H) through MSR_LASTBRANCH_7_TO_IP (address 6C7H) store 
destination addresses.
•Last Branch Record Top- of-Stack (TOS) Pointer — The lowest significant 3 bits of the TOS Pointer MSR 
(MSR_LASTBRANCH_TOS, address 1C9H) contains a pointe r to the MSR in the LBR stack that contains the 
most recent branch, interrupt, or exception recorded.
LBR filtering is supported. Filtering of LBRs based on a combination of CPL and branch type conditions is supported. 
BR_SELECT. The layout of MSR_LBR_SELECT is described in Table 18-11.
IA32_PERF_CAPABILITIES[5:0] and consult Section 18.4. 8.1.The behavior of the MSR_LER_TO_LIP and the 
the P6 family processors.
18.9 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR 
PROCESSORS BASED ON NEHALEM MICROARCHITECTURE
The processors based on Nehalem microarchitecture and Westmere microarchitecture support last branch inter-
rupt and exception recording. These capabilities are simila r to those found in Intel Core 2 processors and add addi-
tional capabilities:
•Debug Trace and Branch Recording Control — The IA32_DEBUGCTL MSR provides bit fields for software to 
operations. See Section 18.4.1 for a description of  the flags. See Figure 18-11 for the MSR layout. 
•Last branch record (LBR) stack — There are 16 MSR pairs that store the source and destination addresses 
related to recently executed branches. See Section 18.9.1.
•Monitoring and single-stepping of br anches, exceptions, and interrupts — See Section 18.4.2 and 
Section 18.4.3. In addition, the ability to freez e the LBR stack on a PMI request is available.18-30 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
•Branch trace messages — The IA32_DEBUGCTL MSR provides bit fields  for software to enable each logical 
processor to generate branch trace messages. See Section 18.4.4. However, not all BTM messages are 
observable using the Intel® QPI link.
•Branch trace store and CPL-qualified BTS — See Section 18.4.6 and Section 18.4.5.
•UNCORE_PMI_EN (bit 13) — When set. this logical processor is enabled to receive an counter overflow 
interrupt form the uncore.
Processors based on Nehalem microarchitecture provide additional capabilities:

•Independent control of uncore PMI — The IA32_DEBUGCTL MSR provides a bit field (see Figure 18-11) for 
software to enable each logical processor to receive an uncore counter overflow interrupt.
•LBR filtering — Processors based on Nehalem microarchitecture support filtering of LBR based on combination 
of CPL and branch type conditions. When LBR filtering is  enabled, the LBR stack only captures the subset of 
branches that are specified by MSR_LBR_SELECT.
18.9.1 LBR Stack
Processors based on Nehalem microarchitecture provide 16 pa irs of MSR to record last branch record information. 
The layout of each MSR pair is shown in Table 18-8 and Table 18-9.Figure 18-11.  IA32_DEBUGCTL MSR for Proc essors Based on Nehalem Microarchitecture
Table 18-8.   MSR_LASTBRANCH_x_FROM_IP 
Data 47:0 R/W This is the “branch from” address. See Section 18.4.8.1 for address format.
SIGN_EXt 62:48 R/W Signed extension of bit 47 of this register.
MISPRED 63 R/W When set, indicates either  the target of the branch was mispredicted and/or the 
direction (taken/non-taken) was mispredicted; otherwise, the target branch was 
predicted.31
TR — Trace messages enableBTINT — Branch trace interrupt
LBR — Last branch/interrupt/exceptionReserved87654321 0
Reserved910
BTS_OFF_OS — BTS off in OSBTS_OFF_USR — BTS off in user codeFREEZE_LBRS_ON_PMIFREEZE_PERFMON_ON_PMI1112 14
UNCORE_PMI_EN13Vol. 3B 18-31DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
Processors based on Nehalem microarchitecture have an LBR MSR Stack as shown in Table 18-10.
Table 18-10.  LBR Stack Size and TOS Pointer Range
18.9.2 Filtering of Last Branch Records
MSR_LBR_SELECT is cleared to zero at RESET, and LBR filt ering is disabled, i.e., all branches will be captured. 
MSR_LBR_SELECT provides bit fields to specify the conditions of subsets of branches that will not be captured in 
the LBR. The layout of MSR_LBR_ SELECT is shown in Table 18-11.
18.10 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR 
PROCESSORS BASED ON SANDY BRIDGE MICROARCHITECTURE
Generally, all of the last branch record, interrupt, and ex ception recording facility described in Section 18.9, “Last 
Branch, Interrupt, and Exception Recording for Processors based on Nehalem Microarchitecture,” apply to proces-
sors based on Sandy Bridge microarchitecture. For processors based on Ivy Bridge microarchitecture, the same holds true. 
One difference of note is that MSR_LBR_SELECT is shared  between two logical processors in the same core. In 
Sandy Bridge microarchitecture, each logical processor has its own MSR_LBR_SELECT. The filtering semantics for 
“Near_ind_jmp” and “Near_rel_jmp” has been enhanced, see Table 18-12.Table 18-9.   MSR_LASTBRANCH_x_TO_IP 
Data 47:0 R/W This is the “branch to” address. See Section 18.4.8.1 for address format
SIGN_EXt 63:48 R/W Signed extension of bit 47 of th is register.
DisplayFamily_DisplayMod el Size of LBR Stack Range of TOS Pointer
06_1AH 16 0 to 15
Table 18-11.   MSR_LBR_SELECT  for Nehalem Microarchitecture
CPL_EQ_0 0 R/W When set, do not capture branches ending in ring 0
CPL_NEQ_0 1 R/W When set, do not capture branches ending in ring >0
JCC 2 R/W When set, do not capture conditional branches
NEAR_REL_CALL 3 R/W When set, do not ca pture near relative calls
NEAR_IND_CALL 4 R/W When set, do not capture near indirect calls
NEAR_RET 5 R/W When set, do not capture near returns
NEAR_IND_JMP 6 R/W When set, do not capture near indirect jumps
NEAR_REL_JMP 7 R/W When set, do not capt ure near relative jumps 
FAR_BRANCH 8 R/W When set, do no t capture far branches
Reserved 63:9 Must be zero18-32 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
18.11 LAST BRANCH, CALL STACK, IN TERRUPT, AND EXCEPTION RECORDING 
FOR PROCESSORS BASED ON HASWELL MICROARCHITECTURE
Generally, all of the last branch record, interrupt, and ex ception recording facility described in Section 18.10, “Last 
Branch, Interrupt, and Exception Recording for Processors ba sed on Sandy Bridge Microarchitecture,” apply to next 
generation processors based on Haswell microarchitecture. 
The LBR facility also supports an alternate capability to profile call stack profiles. Configuring the LBR facility to 
conduct call stack profiling is by writing 1 to the MS R_LBR_SELECT.EN_CALLSTACK[bit 9]; see Table 18-13. If 
MSR_LBR_SELECT.EN_CALLSTACK is clear, the LBR facility will capture branches normally as described in Section 
18.10.
The call stack profiling capability is an enhancement of the LBR facility. The LBR stack is a ring buffer typically used 
to profile control flow transitions resulting from branches . However, the finite depth of the LBR stack often become 
less effective when profiling certain high-level languages (e .g., C++), where a transition of the execution flow is 
accompanied by a large number of leaf function calls, each of  which returns an individual parameter to form the list Table 18-12.   MSR_LBR_SELECT fo r Sandy Bridge Microarchitecture
NEAR_REL_CALL 3 R/W When set, do not capture near relative calls
NEAR_IND_JMP 6 R/W When set, do not capture near indirect jump s except near indirect calls and near returns
NEAR_REL_JMP 7 R/W When set, do not capture near rela tive jumps except ne ar relative calls.
FAR_BRANCH 8 R/W When set, do not capture far branches
Reserved 63:9 Must be zero
Table 18-13.   MSR_LBR_SELECT  for Haswell Microarchitecture
EN_CALLSTACK1
NOTES:
1. Must set valid combination of bits 0-8 in conjunction with bit 9 (as described below), otherwise the contents of the LBR MSR s are 
undefined.9 Enable LBR stack to use LIFO filtering to capture Call stack profile
Reserved 63:10 Must be zeroVol. 3B 18-33DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
of parameters for the main execution function call. A long  list of such parameters returned by the leaf functions 
would serve to flush the data captured in the LBR stack, often losing the main execution context. 
When the call stack feature is enabled, the LBR stack will capture unfiltered call data normally, but as return 
instructions are executed the last captured branch record is flushed from the on-chip registers in a last-in first-out 
(LIFO) manner. Thus, branch information relative to leaf functions will not be captured, while preserving the call 
stack information of the main line execution path.
The configuration of the call stack facility is summarized below:
•Set IA32_DEBUGCTL.LBR (bit 0) to en able the LBR stack to capture branch records. The source and target 
addresses of the call branches will be captured in th e 16 pairs of From/To LBR MSRs  that form the LBR stack.
•Program the Top of Stack (TOS) MSR that points to the la st valid from/to pair. This register is incremented by 
1, modulo 16, before recording the next pair of addresses.
•Program the branch filtering bits of MSR_LBR_SELECT (bits 0:8) as desired.
•Program the MSR_LBR_SELECT to enable LIFO filtering of return instructions with:
— The following bits in MSR_LBR_SELECT must be  set to ‘1’: JCC, NEAR_IND_JMP, NEAR_REL_JMP, 
FAR_BRANCH, EN_CALLSTACK;
— The following bits in MSR_LBR_SELECT must be cleared: NEAR_REL_CALL, NEAR-IND_CALL, NEAR_RET;
— At most one of CPL_EQ_0, CPL_NEQ_0 is set.
Note that when call stack profiling is enabled, “zero leng th calls” are excluded from writing into the LBRs. (A “zero 
length call” uses the attribute of the call instruction to push the immediate instruction pointer on to the stack and 
then pops off that address into a register. This is accomplished without any matching return on the call.)
18.11.1 LBR Stack Enhancement

Processors based on Haswell microarchitecture provide 16 pairs of MSR to record last branch record information. The layout of each MSR pair is enumerated by IA32_PE RF_CAPABILITIES[5:0] = 04H, an d is shown in Table 18-14 
and Table 18-9.
18.12 LAST BRANCH, CALL STACK, IN TERRUPT, AND EXCEPTION RECORDING 
FOR PROCESSORS BASED ON SKYLAKE MICROARCHITECTURE
Processors based on the Skylake microarchitecture provide a number of enhancement with storing last branch 
records:
•enumeration of new LBR format: encoding 00101b in IA 32_PERF_CAPABILITIES[5:0] is  supported, see Section 
18.4.8.1. 
•Each LBR stack entry consists of a triplets of MSRs: Table 18-14.   MSR_LASTBRANCH_x_FROM_IP with TSX Information
SIGN_EXT 60:48 R/W Signed extension of bit 47 of th is register.
TSX_ABORT 61 R/W When set, indica tes a TSX Abort entry
LBR_FROM: EIP at the ti me of the TSX Abort
LBR_TO: EIP of the start of HLE region, or EIP of the RTM Abort Handler
IN_TSX 62 R/W When set, indicates the en try occurred in a TSX region
predicted.18-34 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
— MSR_LBR_INFO_x, stores branch prediction  flag, TSX info, and elapsed cycle data.
•Size of LBR stack increased to 32. 
Processors based on the Skylake microarchitecture support the same LBR filtering capabilities as described in 
Table 18-13.
Table 18-15.  LBR Stack Si ze and TOS Pointer Range
18.12.1 MSR_LBR_INFO_x MSR
The layout of each MSR_LBR_INFO _x MSR is shown in Table 18-16.
18.12.2 Streamlined Freeze_LBRs_On_PMI Operation
The FREEZE_LBRS_ON_PMI feature causes the LBRs to be fr ozen on a hardware request for a PMI. This prevents 
the LBRs from being overwritten by new branches, allowing the PMI handler to examine the control flow that 
preceded the PMI generation. Architectural performance monitoring version 4 and above supports a streamlined 
FREEZE_LBRs_ON_PMI operation for PMI service routine th at replaces the legacy FREEZE_LBRs_ON_PMI operation 
(see Section 18.4.7).
While the legacy FREEZE_LBRS_ON_PMI clear the LBR bi t in the IA32_DEBUGCTL MSR on a PMI request, the 
streamlined FREEZE_LBRS_ON_PMI will set the LBR_FRZ bi t in IA32_PERF_GLOBAL_STATUS. Branches will not 
cause the LBRs to be updated when LBR_FRZ is set. Software  can clear LBR_FRZ at the same time as it clears over-
flow bits by setting the LBR_FRZ bit as well as the n eeded overflow bit when writing to IA32_PERF_GLOBAL_STA-
TUS_RESET MSR.
This streamlined behavior avoids race conditions betwee n software and processor writes to IA32_DEBUGCTL that 
are possible with FREEZE_LBRS_ON_PMI clearing of the LBR enable.DisplayFamily_DisplayModel Size of  LBR Stack Range of TOS Pointer
06_4EH, 06_5EH 32 0 to 31
Table 18-16.   MSR_LBR_INFO_x 
(saturating)15:0 R/W Elapsed core clocks sinc e last update to the LBR stack.
Reserved 60:16 R/W Reserved
TSX_ABORT 61 R/W When set, indicates a TSX Abort entry
LBR_FROM: EIP at the time of the TSX AbortLBR_TO: EIP of the start of HLE region    OR
                EIP of the RTM Abort Handler
IN_TSX 62 R/W When set, indicates the entry occurred in a TSX region.
direction (taken/non-taken) was mispredicted; otherwise, the target branch was predicted.Vol. 3B 18-35DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.12.3 LBR Behavior and Deep C-State
When MWAIT is used to request a C-state that is numerica lly higher than C1, then LBR state may be initialized to 
zero depending on optimized “waiting” state that is select ed by the processor The affected LBR states include the 
FROM, TO, INFO, LAST_BRANCH, LER, and LBR_TOS regist ers. The LBR enable bit and LBR_FROZEN bit are not 
affected. The LBR-time of the first LBR record inserted after an exit from such a C-state request will be zero. 
18.13 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PROCESSORS 
BASED ON INTEL NETBURST® MICROARCHITECTURE)
Pentium 4 and Intel Xeon processors based on Intel NetBurst microarchitecture provide the following methods for 
recording taken branches, interrupts, and exceptions:
•Store branch records in the last branch record (LBR) stack MSRs for the most recent taken branches, 
interrupts, and/or exceptions in MSRs. A branch record  consist of a branch-from and a branch-to instruction 
address. 
•Send the branch records out on the system bus as branch trace messages (BTMs).
•Log BTMs in a memory-resident branch trace store (BTS) buffer.
To support these functions, the processor provides the following MSRs and related facilities:
•MSR_DEBUGCTLA MSR  — Enables last branch, interrupt, and exception recording; single-stepping on taken 
branches; branch trace messages (BTMs); and branch trace store (BTS). This register is named DebugCtlMSR 
in the P6 family processors.
•Debug store (DS) feature fl ag (CPUID.1:EDX.DS[bit 21])  — Indicates that the processor provides the 
debug store (DS) mechanism, which allows BTMs to be stored in a memory-resident BTS buffer.
•CPL-qualified debug store (DS) feature flag (CPU ID.1:ECX.DS-CPL[bit 4])  — Indicates that the 
processor provides a CPL-qualified debug store (DS) me chanism, which allows software to selectively skip 
sending and storing BTMs, according to specified current privilege level settings, into a memory-resident BTS buffer.
•IA32_MISC_ENABLE MSR  — Indicates that the processor provides the BTS facilities.
•Last branch record (LBR) stack — The LBR stack is a circular stack that consists of four MSRs (MSR_LAST-
BRANCH_0 through MSR_ LASTBRANCH_3) for the Pentium 4 and Intel Xeon processor family [CPUID family 
0FH, models 0H-02H]. The LBR stack consists of  16 MSR pairs (MSR_LASTBRANCH_0_FROM_IP through 
MSR_LASTBRANCH_15_FROM_IP and MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_15_TO_IP) 
for the Pentium 4 and Intel Xeon processor family [CPUID family 0FH, model 03H].
•Last branch record top-of-stack (TOS) pointer — The TOS Pointer MSR contains a 2-bit pointer (0-3) to 
the MSR in the LBR stack that contains the most rece nt branch, interrupt, or exception recorded for the 
Pentium 4 and Intel Xeon processor family [CPUID family  0FH, models 0H-02H]. This pointer becomes a 4-bit 
pointer (0-15) for the Pentium 4 and Intel Xeon proce ssor family [CPUID family 0FH, model 03H]. See also: 
Table 18-17, Figure 18-12, and Section 18.13.2, “LBR St ack for Processors Based on Intel NetBurst® Microar-
•Last exception record — See Section 18.13.3, “Last Exception Records.”
18.13.1 MSR_DEBUGCTLA MSR 
The MSR_DEBUGCTLA MSR enables and disables the various last branch recording mechanisms described in the 
previous section. This register can be written to using the WRMSR instruction, when op erating at privilege level 0 
or when in real-address mode. A protected-mode operating system procedure is required  to provide user access to 
this register. Figure 18-12 shows the flags in the MSR_ DEBUGCTLA MSR. The function s of these flags are as 
follows:
the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug exception being generated) in the last branch record (LBR) stack. Each branch, interrupt, or exception is recorded as a 
64-bit branch record. The processor clears this flag whenever a debug exception is generated (for example, 18-36 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
when an instruction or data breakpoint or a single-step trap occurs). See Section 18.13.2, “LBR Stack for 
Processors Based on Intel NetBurst® Microarchitecture.”
register as a “single-step on branches” flag rather th an a “single-step on instructions” flag. This mechanism 
allows single-stepping the processor on taken branches. See Section 18.4.3, “Single-Stepping on Branches.”
•TR (trace message enable) flag (bit 2) — When set, branch trace messages are enabled. Thereafter, when 
the processor detects a taken branch, interrupt, or exceptio n, it sends the branch record out on the system bus 
as a branch trace message (BTM). See Section 18.4.4, “Branch Trace Messages.”
•BTS (branch trace stor e) flag (bit 3) — When set, enables the BTS facilities to log BTMs to a memory-

•BTINT (branch trace interrupt) flag (bits 4) — When set, the BTS facilities generate an interrupt when the 
BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion.  See Section 18.4.5, “Branch 
Trace Store (BTS).”
•BTS_OFF_OS (disable ring 0 branch  trace store) flag (bit 5) — When set, enables the BTS facilities to 
skip sending/logging CPL_0 BTMs to  the memory-resident BTS buffer. See Section 18.13.2, “LBR Stack for 
•BTS_OFF_USR (disable ring 0 branch  trace store) flag (bit 6) — When set, enables the BTS facilities to 
skip sending/logging non-CPL_0 BTMs to the memory-res ident BTS buffer. See Section 18.13.2, “LBR Stack for 
NOTE
The initial implementation of BTS_OFF_USR an d BTS_OFF_OS in MSR_DEBUGCTLA is shown in 
Figure 18-12. The BTS_OFF_USR and BTS_OFF_OS fields may be implemented on other model-specific debug control register at different locations.
See Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel
Manual, Volume 4, for a detailed description of  each of the last branch recording MSRs.
18.13.2 LBR Stack for Processors Based on Intel NetBurst® Microarchitecture
The LBR stack is made up of LBR MSRs that are treated by the processor as a circular stack. The TOS pointer 
(MSR_LASTBRANCH_TOS MSR) points to the LBR MSR (or LB R MSR pair) that contains the most recent (last) 
branch record placed on the stack. Prior to placing a new branch record on the stack, the TOS is incremented by 1. 
When the TOS pointer reaches it maximum value, it wraps around to 0. See Table 18-17 and Figure 18-12.Figure 18-12.  MSR_DEBUGCTLA MSR fo r Pentium 4 and Intel Xeon Processors31
LBR — Last branch/interrupt/exception543 210
BTS — Branch trace storeReserved67
BTS_OFF_OS — Disable storing CPL_0 BTSBTS_OFF_USR — Disable storing non-CPL_0 BTSVol. 3B 18-37DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
Table 18-17.  LBR MSR Stack Size an d TOS Pointer Range for the Pentium® 4 and the Intel®Xeon®Processor Family
The registers in the LBR MSR stack an d the MSR_LASTBRANCH_TOS MSR are re ad-only and can be read using the 
RDMSR instruction.
Figure 18-13 shows the layout of a branch record in an LB R MSR (or MSR pair). Each branch record consists of two 
linear addresses, which represent the “from” and “to” inst ruction pointers for a branch, interrupt, or exception. The 
contents of the from and to addresses diff er, depending on the source of the branch:
•Taken branch  — If the record is for a taken branch, the “from” address is the address of the branch instruction 
and the “to” address is the target instruction of the branch. 
•Interrupt — If the record is for an interrupt, the “from” a ddress the return instruction pointer (RIP) saved for 
the interrupt and the “to” address is the address of the fi rst instruction in the interrupt handler routine. The RIP 
is the linear address of the next instruction to be  executed upon returning from the interrupt handler.
•Exception  — If the record is for an exception, the “from” a ddress is the linear address of the instruction that 
caused the exception to be generate d and the “to” address is the addre ss of the first instruction in the 
exception handler routine.
Additional information is saved if an exception or interrupt  occurs in conjunction with a branch instruction. If a 
branch instruction generates a trap type exception, two branch records are stored in the LBR stack: a branch 
record for the branch instruction followed by a branch record for the exception.
If a branch instruction is immediately followed by an inte rrupt, a branch record is stored in the LBR stack for the 
branch instruction followed by  a record for the interrupt. 
18.13.3 Last Exception Records
The Pentium 4, Intel Xeon, Pentium M, Intel® Core™ Solo, Intel® Core™ Duo, Intel® Core™2 Duo, Intel® Core™ i7 
and Intel Atom® processors provide two MSRs (the MSR_LER_ TO_LIP and the MSR_LER_FROM_LIP MSRs) that 
duplicate the functions of the LastExceptionToIP and LastEx ceptionFromIP MSRs found in the P6 family processors. DisplayFamily_DisplayModel Size of  LBR Stack Range of TOS Pointer
Family 0FH, Models 0H-02H; MSRs at locations 1DBH-1DEH. 40  t o  3
Family 0FH, Models; MSRs  at locations 680H-68FH. 16 0 to 15
Family 0FH, Model 03H; MSRs at locations 6C0H-6CFH. 16 0 to 15
Figure 18-13.  LBR MSR Branch Record Layout for the Pentium 4 and Intel® Xeon® Processor Family63
From Linear Address0
To Linear Address
63
0 63
To Linear Address32 - 31MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3  CPUID Family 0FH, Models 0H-02H
ReservedCPUID Family 0FH, Model 03H-04H
ReservedMSR_LASTBRANCH_0_FROM_IP through MSR_LASTBRANCH_15_FROM_IP
32 - 313 2-3 1
MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_15_TO_IP18-38 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
The MSR_LER_TO_LIP and MSR_LER_FROM_LIP MSRs contai n a branch record for the last branch that the 
processor took prior to an exception or interrupt being generated.
18.14 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ 
SOLO AND INTEL® CORE™ DUO PROCESSORS)
Intel Core Solo and Intel Core Duo processors provide last  branch interrupt and exception recording. This capability 
is almost identical to that found in Pentium 4 and Intel Xeon processors. There are differences in the stack and in 
some MSR names and locations. 
•IA32_DEBUGCTL MSR — Enables debug trace interrupt, debug trace store, trace messages enable, 
performance monitoring breakpoint flags, single step ping on branches, and last branch. IA32_DEBUGCTL MSR 
is located at register address 01D9H. 
See Figure 18-14 for the layout and the entries below for a description of the flags:
—LBR (last branch/interrupt/exception) flag (bit 0) — When set, the processor records a running trace 
of the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug 
exception being generated) in the last branch record  (LBR) stack. For more information, see the “Last 
Branch Record (LBR) Stack” below.
—BTF (single-step on bran ches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS 
register as a “single-step on branches” flag rather than a “single-step on instructions” flag. This mechanism allows single-stepping the processor on taken br anches. See Section 18.4.3, “Single-Stepping on 
Branches,” for more information about the BTF flag.
—TR (trace message enable) flag (bit 6) — When set, branch trace messages are enabled. When the 
processor detects a taken branch, interrupt, or exception; it sends the branch record out on the system bus 
as a branch trace message (BTM). See Section 18.4. 4, “Branch Trace Messages,” for more information 
about the TR flag.
—BTS (branch trace stor e) flag (bit 7) — When set, the flag enables BTS facilities to log BTMs to a 
memory-resident BTS buffer that is part of the DS sa ve area. See Section 18.4.9, “BTS and DS Save Area.”
—BTINT (branch trace interrupt) flag (bits 8) — When set, the BTS facilities generate an interrupt when 
the BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 18.4.5, 
“Branch Trace Store (BTS),” for a description of this mechanism.
•Debug store (DS) feature flag (bit 21 ), returned by the CPUID instruction  — Indicates that the 
processor provides the debug store (DS) mechanism, wh ich allows BTMs to be stored in a memory-resident 
BTS buffer. See Section 18.4.5, “Branch Trace Store (BTS).”
•Last Branch Record (LBR) Stack  — The LBR stack consists of 8 MSRs (MSR_LASTBRANCH_0 through 
MSR_LASTBRANCH_7); bits 31-0 hold the ‘from’ address, bits 63-32 hold the ‘to’ address (MSR addresses start 
at 40H). See Figure 18-15.Figure 18-14.  IA32_DEBUGCTL MSR for Intel® Core™ Solo and Intel® Core™ Duo Processors31
ReservedVol. 3B 18-39DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
•Last Branch Record Top- of-Stack (TOS) Pointer — The TOS Pointer MSR contains a 3-bit pointer (bits 2-
0) to the MSR in the LBR stack that contains the most recent branch, interrupt, or exception recorded. For Intel 
Core Solo and Intel Core Duo processors, this MSR is located at register address 01C9H.
For compatibility, the Intel Core Solo and Intel Co re Duo processors provide two 32-bit MSRs (the 
MSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) that du plicate functions of the LastExceptionToIP and Last-
ExceptionFromIP MSRs found in P6 family processors.

For details, see Section 18.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based 
on Skylake Microarchitecture,” and Section 2.20, “MSRs In Intel® Core™ Solo and Intel® Core™ Duo Processors,” 
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4.
18.15 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PENTIUM M 
Like the Pentium 4 and Intel Xeon processor family, Pentiu m M processors provide last branch interrupt and excep-
tion recording. The capability operates almost identically to that found in Pentium 4 and Intel Xeon processors. 
There are differences in the shape of  the stack and in some MSR names and locations. Note the following:
•MSR_DEBUGCTLB MSR — Enables debug trace interrupt, debug trace store, trace messages enable, 
performance monitoring breakpoint flags, single st epping on branches, and last branch. For Pentium M 
processors, this MSR is located at register address 01D9H. See Figure 18-16 and the entries below for a 
description of the flags.
Branch Record (LBR) Stack” bullet below.
—BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS 
allows single-stepping the processor on taken branches. See Section 18.4.3, “Single-Stepping on 
—PBi (performance monitoring/break point pins) flags (bits 5-2) — When these flags are set, the 
performance monitoring/breakpoint pins on the processor (BP0#, BP1#, BP2#, and BP3#) report 
breakpoint matches in the corresponding breakpoint -address registers (DR0 through DR3). The processor 
asserts then deasserts the corresponding BP i# pin when a breakpoint match occurs. When a PB i flag is 
clear, the performance monitoring/breakpoint pins re port performance events. Processor execution is not 
affected by reporting performance events.
processor detects a taken branch, interrupt, or exception, it sends the branch record out on the system bus 
—BTS (branch trace store) flag (bit 7) — When set, enables the BTS facilities to log BTMs to a memory-
the BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 18.4.5, “Branch Trace Store (BTS),” for a description of this mechanism.Figure 18-15.  LBR Branch Record Layo ut for the Intel® Core™ Solo and Intel® Core™ Duo Processor0 63
From Linear Address To Linear Address32 - 31MSR_LASTBRANCH_0 through MSR_LASTBRANCH_718-40 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
MSR_LASTBRANCH_7); bits 31-0 hold the ‘from’ address, bits 63-32 hold the ‘to’ address. For Pentium M 
Processors, these pairs are located at regi ster addresses 040H-047H. See Figure 18-17.
•Last Branch Record Top- of-Stack (TOS) Pointer — The TOS Pointer MSR contains a 3-bit pointer (bits 2-0) 
to the MSR in the LBR stack that contains the most rece nt branch, interrupt, or exception recorded. For Pentium 
M Processors, this MSR is located at register address 01C9H.
For more detail on these capabilities, see Section 18.13. 3, “Last Exception Records,” and Section 2.21, “MSRs In 
the Pentium M Processor,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4.
18.16 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (P6 FAMILY 
The P6 family processors provide five MSRs for recordin g the last branch, interrupt, or exception taken by the 
processor: DEBUGCTLMSR, LastBranchToIP, LastBranchFr omIP, LastExceptionToIP, and LastExceptionFromIP. 
These registers can be used to collect last branch records, to set breakpoints on branches, interrupts, and excep-
tions, and to single-step from one branch to the next.
18.16.1 DEBUGCTLMSR Register
The version of the DEBUGCTLMSR register found in the P6 family processors enables last branch, interrupt, and 
exception recording; taken branch breakpoints; the breakp oint reporting pins; and trace messages. This register 
can be written to using the WRMSR instruction, when oper ating at privilege level 0 or when in real-address mode. Figure 18-16.  MSR_DEBUGCTLB MSR for Pentium M Processors
Figure 18-17.  LBR Branch Record Layout for the Pentium M Processor31
PB3/2/1/0 — Performance monitoring breakpoint flags
0 63
From Linear Address To Linear Address3 2-3 1MSR_LASTBRANCH_0 through MSR_LASTBRANCH_7Vol. 3B 18-41DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
A protected-mode operating system procedure is required  to provide user access to this register. Figure 18-18 
shows the flags in the DEBUGCTLMSR register for the P6 family processors. The functions of these flags are as 
follows:
•LBR (last branch/interrupt/e xception) flag (bit 0) — When set, the processor records the source and 
target addresses (in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP 
MSRs) for the last branch and the last exception or interrupt taken by the processor prior to a debug exception being generated. The processor clears this flag whenever a debug exception, such as an instruction or data 
breakpoint or single-step trap occurs.
register as a “single-step on branches” flag. Se e Section 18.4.3, “Single-Stepping on Branches.”
•PBi (performance monitoring/breakpoint pins) flags (bits 2 through 5) — When these flags are set, 
the performance monitoring/breakpoint pins on th e processor (BP0#, BP1#, BP2#, and BP3#) report 
asserts then deasserts the corresponding BP i# pin when a breakpoint match occurs. When a PB i flag is clear, 
the performance monitoring/breakpoint pins report performance events. Proc essor execution is not affected by 
reporting performance events.
•TR (trace message enable) flag (bit 6) — When set, trace messages are enabled as described in Section 
18.4.4, “Branch Trace Messages.” Setting this flag gr eatly reduces the performanc e of the processor. When 
trace messages are enabled, the values stored in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, 
and LastExceptionFromIP MSRs are undefined.
18.16.2 Last Branch and Last Exception MSRs
The LastBranchToIP and LastBranchFromIP MSRs are 32-bit registers for recording the instruction pointers for the 
last branch, interrupt, or exception that the processor to ok prior to a debug exception being generated. When a 
branch occurs, the processor loads the address of the bran ch instruction into the LastBranchFromIP MSR and loads 
the target address for the branch  into the LastBranchToIP MSR. 
When an interrupt or exception occurs (other than a debug exception), the address of the instruction that was 
interrupted by the exception or interrupt is loaded into  the LastBranchFromIP MSR and the address of the excep-
tion or interrupt handler that is called  is loaded into the LastBranchToIP MSR.
The LastExceptionToIP and LastExceptionFromIP MSRs (also 32-bit registers) record the instruction pointers for 
the last branch that the processor took prior to an exception or interrupt being generated. When an exception or 
interrupt occurs, the contents of the LastBranchToIP and LastBranchFromIP MSRs are copied into these registers

interrupt occurs, the contents of the LastBranchToIP and LastBranchFromIP MSRs are copied into these registers 
before the to and from addresses of the exception or inte rrupt are recorded in the LastBranchToIP and LastBranch-
FromIP MSRs.
These registers can be read using the RDMSR instruction.
Note that the values stored in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP 
MSRs are offsets into the current code segment, as oppo sed to linear addresses, which are saved in last branch 
records for the Pentium 4 and Intel Xeon processors.Figure 18-18.  DEBUGCTLMSR Register (P6 Family Processors)31
PBi — Performance monitoring/breakpoint pins
LBR — Last branch/interrupt/exception76543 210
P
B
2P
B
1P
B
0B
T
FT
RL
B
RP
B
3Reserved18-42 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
18.16.3 Monitoring Branches, Exceptions, and Interrupts
When the LBR flag in the DEBUGCTLMSR re gister is set, the processor automatically begins recording branches that 
it takes, exceptions that are generated (except for debug exceptions), and interrupts that are serviced. Each time 
a branch, exception, or interrupt occurs, the processor records the to and from instruction pointers in the Last-BranchToIP and LastBranchFromIP MSRs. In addition, fo r interrupts and exceptions, the processor copies the 
contents of the LastBranchToIP and LastBranchFromIP MSRs into the LastExceptionToIP and LastExceptionFromIP 
MSRs prior to recording the to and from addresses of the interrupt or exception.
exception handler, but does not touch the last branch and last exception MSRs. The addresses for the last branch, interrupt, or exception taken are thus retained in th e LastBranchToIP and LastBranchFromIP MSRs and the 
addresses of the last branch prior to an interrupt or ex ception are retained in the LastExceptionToIP, and LastEx-
ceptionFromIP MSRs.
The debugger can use the last branch, interrupt, and/or exception addresses in combination with code-segment 
selectors retrieved from the stack to reset breakpoints in the breakpoint-address registers (DR0 through DR3), 
allowing a backward trace from the manifestation of a particular bug toward its source. Because the instruction 
pointers recorded in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP MSRs are 
offsets into a code segment, software must determine th e segment base address of the code segment associated 
with the control transfer to calculate the linear addre ss to be placed in the breakpoint-address registers. The 
segment base address can be determined by reading the segment selector for the code segment from the stack 
and using it to locate the segment descriptor for the segment in the GDT or LDT. The segment base address can 
then be read from the segment descriptor.
Before resuming program execution from a debug-exception handler, the handler must set the LBR flag again to re-
enable last branch and last exception/interrupt recording.
18.17 TIME-STAMP COUNTER
The Intel 64 and IA-32 architectures (beginning with th e Pentium processor) define a time-stamp counter mecha-
nism that can be used to monitor and identify the relati ve time occurrence of processor events. The counter’s archi-
tecture includes the following components:
•TSC flag  — A feature bit that indicates the availability of the time-stamp counter. The counter is available in an 
if the function CPUID.1:EDX.TSC[bit 4] = 1.
•IA32_TIME_STAMP_COUNTER MSR  (called TSC MSR in P6 family and Pentium processors) — The MSR used 
as the counter.
•RDTSC instruction  — An instruction used to read the time-stamp counter.
•TSD flag  — A control register flag is used to enable or  disable the time-stamp counter (enabled if 
CR4.TSD[bit 2] = 1).
The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, Intel Xeon, Intel Core 
Solo and Intel Core Duo processors and later processors) is  a 64-bit counter that is set to 0 following a RESET of 
the processor. Following a RESET, the counter increments ev en when the processor is ha lted by the HLT instruction 
or the external STPCLK# pin. Note that the assertion of the external DPSLP# pi n may cause the time-stamp 
counter to stop.
Processor families increment the time-stamp counter differently:
•For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors, Intel Xeon processors 
(family [0FH], models [00H, 01H, or 02H]); and for P6 fa mily processors: the time-stamp counter increments 
with every internal processor clock cycle. 
The internal processor clock cycle is determined by  the current core-clock to bus-clock ratio. Intel® 
SpeedStep® technology transitions may also impact the processor clock.
•For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]); for Intel Core Solo 
and Intel Core Duo processors (family [06H], model [0 EH]); for the Intel Xeon processor 5100 series and Intel 
Core 2 Duo processors (family [06H], model [0FH]); for In tel Core 2 and Intel Xeon processors (family [06H], 
DisplayModel [17H]); for Intel Atom processors (famil y [06H], DisplayModel [1CH]): the time-stamp counter 
increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the Vol. 3B 18-43DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
processor or may be set by the maximum resolved frequency at which the processor is booted. The maximum 
resolved frequency may differ from the processor base frequency, see Section 20.7.2 for more detail. On certain processors, the TSC frequency may not be the same as the frequency in the brand string.
The specific processor configuration determines the behavior. Constant TSC behavior ensures that the duration 
of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if the processor core 
changes frequency. This is the architectural behavior moving forward.
NOTE
To determine average processor clock frequenc y, Intel recommends the use of performance 
monitoring logic to count processor core clocks over the period of time for which the average is required. See Section 20.6.4.5, “Counting Clocks on systems with Intel® Hyper-Threading 
Technology in Processors Based on Intel NetBurst® Microarchitecture,” and https://perfmon-
events.intel.com/  for more information.
The RDTSC instruction reads the time-stamp counter and is guaranteed to return a monotonically increasing 
unique value whenever executed, except for a 64-bit count er wraparound. Intel guarantees that the time-stamp 
counter will not wraparound within 10 years after being reset.  The period for counter wrap is longer for Pentium 4, 
Intel Xeon, P6 family, and Pentium processors.
Normally, the RDTSC instruction can be executed by progra ms and procedures running at any privilege level and in 
virtual-8086 mode. The TSD flag allows use of this instruct ion to be restricted to programs and procedures running 
at privilege level 0. A secure operating system would set the TSD flag during system initialization to disable user 
access to the time-stamp counter. An operating system that disables user access to the time-stamp counter should emulate the instruction through a user-accessible programming interface.
The RDTSC instruction is not serializing or ordered with ot her instructions. It does not necessarily wait until all 
previous instructions have been executed before reading the counter. Similarly, subsequent instructions may begin 
execution before the RDTSC instruction operation is performed.
The RDMSR and WRMSR instructions read and write the time -stamp counter, treating the time-stamp counter as 
an ordinary MSR (address 10H). In the Pentium 4, Intel Xe on, and P6 family processors, all 64-bits of the time-
stamp counter are read using RDMSR (just as with RDTSC) . When WRMSR is used to write the time-stamp counter 
on processors before family [0FH], models [03H, 04H]: only the low-order 32- bits of the time-stamp counter can 
be written (the high-order 32 bits are cleared to 0). For family [0FH], models [03H, 04H, 06H]; for family [06H]], 
model [0EH, 0FH]; for family [06H]], DisplayModel [17H, 1AH, 1CH, 1DH]: all 64 bits are writable.
18.17.1 Invariant TSC
The time stamp counter in newer processors may suppo rt an enhancement, referred to as invariant TSC. 
Processor’s support for invariant TSC is  indicated by CPUID.80000007H:EDX[8]. 
The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior 
moving forward. On processors with invariant TSC suppo rt, the OS may use the TSC for wall clock timer services 
(instead of ACPI or HPET timers). TS C reads are much more efficient and do not incur the overhead associated with 
a ring transition or access to a platform resource.
18.17.2 IA32_TSC_AUX Register and RDTSCP Support

Processors based on Nehalem microarchitecture provide an  auxiliary TSC register, IA32_TSC_AUX that is designed 
to be used in conjunction with IA32_TSC. IA32_TSC_AUX pr ovides a 32-bit field that is initialized by privileged 
software with a signature value (for example, a logical processor ID). 
The primary usage of IA32_TSC_AUX in conjunction with IA 32_TSC is to allow software to read the 64-bit time 
stamp in IA32_TSC and signature value in IA32_TSC_AUX wi th the instruction RDTSCP in an atomic operation. 
RDTSCP returns the 64-bit time stamp in EDX:EAX and the 32-bit TSC_AUX si gnature value in ECX. The atomicity 
of RDTSCP ensures that no context switch can occu r between the reads of the TSC and TSC_AUX values.
Support for RDTSCP is indicated by CPUID.80000001H:EDX[27]. As with RDTSC instruction, non-ring 0 access is 
controlled by CR4.TSD (Time Stamp Disable flag).18-44 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
User mode software can use RDTSCP to detect if CPU mi gration has occurred between successive reads of the TSC. 
It can also be used to adjust for per-CPU differences in TSC values in a NUMA system.
18.17.3 Time-Stamp Counter Adjustment
Software can modify the value of the time-stamp counter (TSC) of a logical processor by using the WRMSR instruc-
tion to write to the IA32_TIME_STAMP _COUNTER MSR (address 10H). Because su ch a write applies only to that 
logical processor, software seeking to synchronize the TSC values of multiple logical processors must perform these 
writes on each logical processor. It may be difficult for software to do this in a way that ensures that all logical processors will have the same value for the TSC at a given point in time.
The synchronization of TSC adjustment can be simplif ied by using the 64-bit IA32_TSC_ADJUST MSR (address 
3BH). Like the IA32_TIME_STAMP_COUNTER MSR, the IA3 2_TSC_ADJUST MSR is maintained separately for each 
logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows:
•On RESET, the value of the IA32_TSC_ADJUST MSR is 0.
•If an execution of WRMSR to the IA32_TIME_STAMP_COUN TER MSR adds (or subtracts) value X from the TSC, 
the logical processor also adds (or subtra cts) value X from the IA32_TSC_ADJUST MSR.
•If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds  (or subtracts) value X from that MSR, the logical 
processor also adds (or subtracts) value X from the TSC.
Unlike the TSC, the value of the IA32_TSC_ADJUST MSR ch anges only in response to WRMSR (either to the MSR 
itself, or to the IA32_TIME_STAMP_COUNTER MSR). Its value does not otherwise change as time elapses. Software 
seeking to adjust the TSC can do so  by using WRMSR to write the same value to the IA32_TSC_ADJUST MSR on 
each logical processor.
Processor support for the IA32_TSC_ADJUST MSR is in dicated by CPUID.(EAX=07H , ECX=0H):EBX.TSC_ADJUST 
(bit 1).
18.17.4 Invariant Time-Keeping
The invariant TSC is based on the invariant timekeeping hardware (called Always Running Timer or ART), that runs 
at the core crystal clock frequency. The ratio defined by CPUID leaf 15H expresses the frequency relationship 
between the ART hardware and TSC.
If CPUID.15H:EBX[31:0] != 0 and CPUID.80000007H:EDX[Invar iantTSC] = 1, the following linearity relationship 
holds between TSC and the ART hardware:
TSC_Value = (ART_Value * CPUID.15H: EBX[31:0] )/ CPUID.15H:EAX[31:0] + K
Where 'K' is an offset that can be adjusted by a privileged agent3.
When ART hardware is reset, both invariant TSC and K are also reset.
18.18 INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) MONITORING 
FEATURES
The Intel Resource Director Technology (Intel RDT) featur e set provides a set of monitoring capabilities including 
Cache Monitoring Technology (CMT) and Memo ry Bandwidth Monitoring (MBM). The Intel® Xeon® processor E5 v3 
family introduced resource monitoring capability in each logical processor to measure specific platform shared 
resource metrics, for example, L3 cache occupancy. The programming interface for these monitoring features is 
described in this section. Two features within the monito ring feature set provided are described - Cache Monitoring 
Technology (CMT) and Memory Bandwidth Monitoring.
3. IA32_TSC_ADJUST MSR and the TSC-offset field in the VM execution controls of VMCS are some of the common interfaces that priv -
ileged software can use to manage th e time stamp counte r for keeping timeVol. 3B 18-45DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
Cache Monitoring Technology (CMT) allows an Operating System, Hypervisor or similar system management agent 
to determine the usage of cache by applications running on  the platform. The initial implementation is directed at 
L3 cache monitoring (currently the last level cache in most server platforms).   
Memory Bandwidth Monitoring (MBM), introduced in the Intel® Xeon® processor E5 v4 family, builds on the CMT 
infrastructure to allow monitoring of bandwidth from one level of the cache hierarchy to the next - in this case 
focusing on the L3 cache, which is typically backed direct ly by system memory. As a result of this implementation, 
memory bandwidth can be monitored.
The monitoring mechanisms descri bed provide the following key shared infrastructure features:
•A mechanism to enumerate the presence of the monitoring  capabilities within the platform (via a CPUID feature 
bit).
•A framework to enumerate the details of each sub-feat ure (including CMT and MBM, as discussed later, via 
CPUID leaves and sub-leaves). 
•A mechanism for the OS or Hypervisor to indicate a softwa re-defined ID for each of the software threads (appli-
cations, virtual machines, etc.) that are scheduled to ru n on a logical processor. These identifiers are known as 
Resource Monitoring IDs (RMIDs). 
•Mechanisms in hardware to monitor cache occupancy and bandwidth statistics as applicable to a given product 
generation on a per software-id basis. 
•Mechanisms for the OS or Hypervisor to read back th e collected metrics such as L3 occupancy or Memory 
Bandwidth for a given software ID at any point during runtime.
18.18.1 Overview of Cache Monitoring Tec hnology and Memory Bandwidth Monitoring
The shared resource monitoring features described in th is chapter provide a layer of abstraction between applica-
tions and logical processors through the use of Resource Monitoring ID s (RMIDs). Each logical processor in the 
system can be assigned an RMID independently, or multip le logical processors can be assigned to the same RMID 
value (e.g., to track an application with multiple threads). For each logical processor, only one RMID value is active 
at a time. This is enforced by the IA32_PQR_ASSOC MSR, which specifies the active RMID of a logical processor. 
Writing to this MSR by software changes the active RMID of the logical processor from an old value to a new value.
The underlying platform shared resource monitoring hard ware tracks cache metrics such as cache utilization and 
misses as a result of memory accesses according to the RMIDs and reports monitored data via a counter register 
(IA32_QM_CTR). The specific event types supported vary by generation and can be enumerated via CPUID. To read 
back monitored data, software configures an event select ion MSR (IA32_QM_EVTSEL) to specify which metric is to 
be reported and the specific RMID fo r which the data should be returned. 
Processor support of the monitoring framework and sub-fe atures such as CMT is reported via the CPUID instruc-
tion. The resource type available to the monitoring framework is enumerated via a new leaf function in CPUID. 
Reading and writing to the monitoring MSRs requires the RDMSR and WRMSR instructions.
The Cache Monitoring Technology feature set provides the following unique mechanisms:
•A mechanism to enumerate the presence and details of th e CMT feature as applicable to a given level of the 
cache hierarchy, independent of other monitoring features. 
•CMT-specific event codes to read occupancy for a given level of the cache hierarchy.
The Memory Bandwidth Monitoring feature provides the following unique mechanisms:
•A mechanism to enumerate the presence and details of the MBM feature as applicable to a given level of the 
cache hierarchy, independent of other monitoring features.
•MBM-specific event codes to read band width out to the next level of the hierarchy and various sub-event codes 
to read more specific metrics as discussed later (e.g.,  total bandwidth vs. bandwidth only from local memory 
controllers on the same package).
18.18.2 Enabling Monitoring: Usage Flow
Figure 18-19 illustrates the key steps for OS/VMM to detect support of shared resource monitoring features such 
as CMT and enable resource monitoring for av ailable resource types and monitoring events.18-46 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES

18.18.3 Enumeration and Detecting Support of Cache Monitoring Technology and Memory 
Bandwidth Monitoring
Software can query processor support of shared resource monitoring features capabilities by executing CPUID 
instruction with EAX = 07H, ECX = 0H as input. If CPUID.(EAX=07H, ECX=0):EBX.P QM[bit 12] reports 1, the 
processor provides the following prog ramming interfaces for shared resource monitoring, including Cache Moni-
toring Technology:
•CPUID leaf function 0FH (Shared Resource Monitoring Enumeration leaf) provides information on available 
resource types (see Section 18.18.4), and monitoring capabilities for each resource type (see Section 18.18.5). 
Note CMT and MBM capabilities are enumerated as separate event vectors using shared enumeration infra-
structure under a given resource type.
•IA32_PQR_ASSOC.RMID: The per-logical-processor MSR, IA32_PQR_ASSOC, that OS/VMM can use to assign an RMID to each logical processor, see Section 18.18.6.
•IA32_QM_EVTSEL: This MSR specifies an Event ID (EvtID) and an RMID which the platform uses to look up and 
provide monitoring data in the monitoring counter, IA32_QM_CTR, see Section 18.18.7. 
•IA32_QM_CTR: This MSR reports monitored resource data wh en available along with bits to allow software to 
check for error conditions and verify data validity. 
Software must follow the following sequence of enumerat ion to discover Cache Monitoring Technology capabilities:
1. Execute CPUID with EAX=0 to discover the “cpuid_maxLeaf” supported in the processor;
2. If cpuid_maxLeaf >= 7, then execute CPUID with EAX=7, ECX= 0 to verify CPUID.(EAX=07H, 
ECX=0):EBX.PQM[bit 12] is set;
3. If CPUID.(EAX=07H, ECX=0):EBX.PQM[bit 12] = 1, th en execute CPUID with EAX=0FH, ECX= 0 to query 
available resource types that support monitoring;
4. If CPUID.(EAX=0FH, ECX=0):EDX.L3[ bit 1] = 1, then execute CPUID wi th EAX=0FH, ECX= 1 to query the 
specific capabilities of L3 Cache Monitoring Te chnology (CMT) and Memory Bandwidth Monitoring.
5. If CPUID.(EAX=0FH, ECX=0):EDX reports additional resource types supporting monitoring, then execute 
CPUID with EAX=0FH, ECX set to a corresponding resource  type ID (ResID) as enumerated by the bit position 
of CPUID.(EAX=0FH, ECX=0):EDX.
18.18.4 Monitoring Resource Type and Capability Enumeration
CPUID leaf function 0FH (Shared Resource Monitoring Enumeration leaf) provides one sub-leaf (sub-function 0) 
that reports shared enumeration infrastructure, and one or more sub-functions that report feature-specific 
enumeration data:
•Monitoring leaf sub-function 0 enumerates available resources that support monitoring, i.e., executing CPUID 
with EAX=0FH and ECX=0H. In the initial implementation, L3 cache is the only resource type available. Each Figure 18-19.  Platform Shared Resource Monitoring Usage FlowCPUID.(7,0):EBX.12On OS/VMM Initialization
CPUID.(0FH,0):EDX[31:1]PQM Capability
Enumeration
IA32_PQR_ASSOC.RMIDOn Context Switch
Set RMID to monitor
the scheduled appPeriodical Resource
IA32_QM_EVTSELConfigure event type
Read monitored data
CPUID.(0FH,1):ECX[31:0]
CPUID.(0FH,1):EDX[31:0]
CPUID.(0FH,1):EBX[31:0]CPUID[ WRMSR RDMSR/WRMSRSelection/Reporting
IA32_QM_CTR
CPUID.(0FH,0):EBX[31:0]Vol. 3B 18-47DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
supported resource type is represented by a bit in  CPUID.(EAX=0FH, ECX=0):EDX[31:1]. The bit position 
corresponds to the sub-leaf index (ResID) that software must use to query details of the monitoring capability of that resource type (see Figure 18-21 and Fi gure 18-22). Reserved bits of CPUID.(EAX=0FH, 
ECX=0):EDX[31:2] correspond to unsupported sub- leaves of the CPUID.0FH leaf. Additionally, 
CPUID.(EAX=0FH, ECX=0H):EBX reports the highest RM ID value of any resource type that supports 
monitoring in the processor.
18.18.5 Feature-Specific Enumeration
Each additional sub-leaf of CPUID.(EAX=0FH, ECX=ResID) enumerates the specific details for software to program 
monitoring MSRs using the resource type associated with the given ResID. 
Note that in future Monitoring implementations the mean ings of the returned registers may vary in other sub-
leaves that are not yet defined. The registers w ill be specified and defined on a per-ResID basis.
CPUID.(EAX=0FH, ECX=1H).EAX[7:0]: Encode  counter width as offset from 24b. See Section 18.18.5.2 for details. 
Bits 31:11 of EAX are reserved.Figure 18-20.  CPUID.(EAX=0FH, ECX=0H) Monitoring Resource Type Enumeration
Figure 18-21.  L3 Cache Monitoring Capability Enumeration Data (CPUID.(EAX=0FH, ECX=1H) )0 2 31CPUID.(EAX=0FH, ECX=0H) Output: (EAX: Reserved; ECX: Reserved)
EDX L
EBX0 31
Highest RMID Value of Any Resource Type (Zero-Based)31
Reserved
0 31
Upscaling Factor to Total Occupancy (Bytes) EBX Upscaling Factor
0 31CPUID.(EAX=0FH, ECX=1H) Output:
Highest RMID Value of this Resource Type (Zero-Based) ECX MaxRMID10    9    8   7                                                 0 31
Reserved EAX
Non-CPU Agent Cache Occupancy Monitoring Non-CPU Agent Memory L3 External Bandwidth Monitoring
Enumeration of an Overflow Bit (Bit 61) in the IA32_QM_CTR MSR 
Counter Width Encoded as an Offset from 24b18-48 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
CPUID.(EAX=0FH, ECX=1H).EAX[bit 8]: If 1, indicates the presence of an ov erflow bit in the IA32_QM_CTR MSR. 
See Section 18.18.5.2 for details. Bits 31:11 of EAX are reserved.
CPUID.(EAX=0FH, ECX=1H).EAX[bit 9]: If  1, indicates the presence of non-CPU agent Intel RDT CMT support. See 
Section 18.20 for details. Bits 31:11 of EAX are reserved.
CPUID.(EAX=0FH, ECX=1H).EAX[bit 10]:I f 1, indicates the presence of no n-CPU agent Intel RDT MBM support. 
See Section 18.20 for details. Bits 31:11 of EAX are reserved.
For each supported Cache Monitoring resource type, hardware supports only a finite number of RMIDs. 
CPUID.(EAX=0FH, ECX=1H).ECX enumerates the highest RMID  value that can be monitored with this resource 
type, see Figure 18-21. 
CPUID.(EAX=0FH, ECX=1H).EDX specifies a bit vector that is  used to look up the EventID (See Figure 18-22 and 
Table 18-18) that software must program with IA32_QM_EV TSEL in order to retrieve event data. After software 
configures IA32_QMEVTSEL with the desired RMID and EventI D, it can read the resulting data from IA32_QM_CTR. 
The raw numerical value reported from IA32_QM_CTR can be  converted to the final value (occupancy in bytes or 
bandwidth in bytes per sampled time period) by multiply ing the counter value by the value from CPUID.(EAX=0FH, 
ECX=1H).EBX, see Figure 18-21. 
18.18.5.1  Cache Monitoring Technology
On processors for which Cache Monitoring Technology supports the L3 cache occupancy event, CPUID.(EAX=0FH, 
ECX=1H).EDX returns with bit 0 set. Th e corresponding event ID is shown in Table 18-18. The L3 occupancy data 
accumulated in the IA32_QM_CTR MSR can be converted to total occupancy (in bytes) by multiplying with 
CPUID.(EAX=0FH, ECX=1H).EBX.
Event codes for Cache Monitoring Technology are discussed in the next section.
18.18.5.2  Memory Bandwidth Monitoring
On processors that monitoring supports Memory Bandwidth Monitoring using ResID=1 (L3), two additional bits are 
defined in the vector at CPUID.(EAX=0FH, ECX=1H).EDX:
•CPUID.(EAX=0FH, ECX=1H).EDX[bit 1]: indicates the L3  total external bandwidth monitoring event is 
supported if set. This event monitors the L3 total external bandwidth to the next level of the cache hierarchy, 
including all demand and prefetch misses from the L3 to  the next hierarchy of the memory system. In most 
platforms, this represents memory bandwidth.
•CPUID.(EAX=0FH, ECX=1H).EDX[bit 2]: indicates L3 local memory bandwidth monitoring event is supported if 
set. This event monitors the L3 external bandwidth sa tisfied by the local memory. In most platforms that 
support this event, L3 requests are likely serviced by a memory system with non-uniform memory architecture. 
This allows bandwidth to off-package memory resources to  be tracked by subtracting local from total bandwidth 
(for instance, bandwidth over QPI to a memory controlle r on another physical processor could be tracked by 
subtraction). Note that it is not possible to read the local and total bandwidth atomically; multiple operations are needed. Because of this, it is possible for th e counters to change in between the two reads.
The corresponding Event ID is shown in Table 18-18. Th e L3 bandwidth data accumulated in IA32_QM_CTR can be 
converted to total bandwidth (in byte s) using CPUID.(EAX=0FH, ECX=1H).EBX.Figure 18-22.  L3 Cache Monitoring Capability Enumerati on Event Type Bit Vector (CPUID.(EAX=0FH, ECX=1H) )0 2 31
EDX1
ReservedEventTypeBitMask
3
L3 Occupancy
L3 Total BW
L3 Local BWVol. 3B 18-49DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
Table 18-18.  Monitori ng Supported Event IDs
A field is added to CPUID to enumerate the MBM counte r width in platforms that support the extensible MBM

EDX1
3
L3 Total BW
A field is added to CPUID to enumerate the MBM counte r width in platforms that support the extensible MBM 
counter width feature.
•CPUID.(EAX=0FH, ECX=1H).EAX[7:0]: Encode counter width as  offset from 24b in bits[7:0]. In EAX bits 7:0, 
the counter width is encoded as an offset from 24b. A value of zero in this field means 24-bit counters are 
supported. A value of 8 indicates that 32-bit counters  are supported, as in the 3rd generation Intel Xeon 
Scalable Processor Family. With this enumerable counter width, the requirement that software polls at 1Hz is 
removed. Software may poll at a varying rate with a reduced risk of rollover. Under typical conditions, rollover 
will likely require hundreds of seconds (though this value is not explicitly specified and may vary and decrease 
in future processor generations as memory bandwidths increase). Suppose software seeks to ensure that 
rollover does not occur more than once between sample s. In that case, sampling at 1Hz while consuming the 
enumerated counter widths' worth of data will provide th is guarantee for a specific platform and counter width 
under all conditions.
•CPUID.(EAX=0FH, ECX=1H).EAX[8]: Enumeration of the pr esence of an overflow bit in the IA32_QM_CTR MSR 
via EAX bit[8]. Software that uses the MBM event retr ieval MSR interface should be updated to comprehend 
this new format, which enables up to 62-bit MBM counter s to be provided by future  platforms. Higher-level 
software that consumes the resulting bandwidth values is not expected to be affected. An overflow bit is 
defined in the IA32_QM_CTR MSR, bit 61, if CPUID.(EAX=0 FH, ECX=1H).EAX[bit 8] is set. This rollover bit will 
be set on overflow of the MBM counters and reset upon read. Current processors do not support this capability.
18.18.6 Monitoring Resource RMID Association
After Monitoring and sub-features have been enumerated , software can begin using the monitoring features. The 
first step is to associate a given software thread (or multip le threads as part of an application, VM, group of appli-
cations or other abstraction) with an RMID. 
Note that the process of associating an RMID with a given software thread is the same for all shared resource moni-
toring features (CMT, MBM), and a given RMID number ha s the same meaning from th e viewpoint of any logical 
processors in a package. Stated another way, a thread ma y be associated in a 1:1 mapping with an RMID, and that 
RMID may allow cache occupancy, memory bandwidth informat ion or other monitoring data to be read back later 
with monitoring event codes (retrieving data is discussed in a previous section). 
The association of an application thread with an RMID requires an OS to program the per-logical-processor MSR 
IA32_PQR_ASSOC at context swap time (updates may also be made at any other arbitrary points during program 
execution such as application phase changes). The IA32_P QR_ASSOC MSR specifies the active RMID that moni-
toring hardware will use to tag internal operations, such as L3 cache requests. The layout of the MSR is shown in 
Figure 18-23. Software specifies the active RMID to moni tor in the IA32_PQR_ASSOC.RMID field. The width of the 
RMID field can vary from one implementation to another, and is derived from Ceil (LOG2 ( 1 + CPUID.(EAX=0FH, 
ECX=0):EBX[31:0])). The value of IA 32_PQR_ASSOC after power-on is 0.Event Type Event ID Context
L3 Cache Occupancy 01H Cache Monitoring Technology
L3 Total External Bandwidth 02H MBM
L3 Local External Bandwidth 03H MBM
Reserved All other event codes N/A
Figure 18-23.  IA32_PQR_ASSOC MSR0 10 63Width of IA32_PQR_ASSOC.RMID field: Log2 ( CPUID.(EAX=0FH, ECX=0H).EBX[31:0] +1)
RMID9
Reserved IA32_PQR_ASSOCReserved for CLOS32 3118-50 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
In the initial implementation, the width of the RMID field is  up to 10 bits wide, zero-referenced and fully encoded. 
However, software must use CPUID to query the maximum RM ID supported by the processor. If a value larger than 
the maximum RMID is written to IA32_PQR_ASSO C.RMID, a #GP(0) fault will be generated.
RMIDs have a global scope within the physical package- if  an RMID is assigned to one logical processor then the 
same RMID can be used to read multiple thread attribut es later (for example, L3 cache occupancy or external 
bandwidth from the L3 to the next level of the cache hierarchy). In a multiple LLC platform the RMIDs are to be 
reassigned by the OS or VMM scheduler when an application is migrated across LLCs. 
Note that in a situation where Monitoring supports multiple  resource types, some upper range of RMIDs (e.g., RMID 
31) may only be supported by one resource  type but not by another resource type. 
18.18.7 Monitoring Resource Select ion and Reporting Infrastructure
The reporting mechanism for Cache Monitoring Technology an d other related features is architecturally exposed as 
an MSR pair that can be programmed and read to measur e various metrics such as the L3 cache occupancy (CMT) 
and bandwidths (MBM) depending on the level of Monitoring  support provided by the platform. Data is reported 
back on a per-RMID basis. These events do not trigger ba sed on event counts or trigger APIC interrupts (e.g., no 
Performance Monitoring Interrupt occurs based on counts) . Rather, they are used to sample counts explicitly. 
The MSR pair for the shared resource monitoring features (CMT, MBM) is separate from and not shared with archi-
tectural Perfmon counters, meaning software can use these monitoring features simultaneously with the Perfmon 
counters. 
Access to the aggregated monitoring information is acco mplished through the following programmable monitoring 
MSRs:
•IA32_QM_EVTSEL: This MSR provides a role similar to  the event select MSRs for programmable performance 
monitoring described in Chapter 18. The simplifie d layout of the MSR is shown in Figure 18-24. 
IA32_QM_EVTSEL.EvtID (bits 7:0) specifies an event code of a supported resource type for hardware to report 
monitored data associated with IA32_QM_EVTSEL.RMID (bits 41:32). Software can configure IA32_QM_EVTSEL.RMID with any RMID  that is active within the physical processor. The width of 
IA32_QM_EVTSEL.RMID matches that of IA32_PQR_ASSOC.RMID. Supported event codes for the 
IA32_QM_EVTSEL register are shown in Table 18-18. No te that valid event codes may not necessarily map 
directly to the bit position used to enumerate support for the resource via CPUID. 
Software can program an RMID / Event ID pair into th e IA32_QM_EVTSEL MSR bit field to select an RMID to 
read a particular counter for a given resource. The currently supported list of Monitoring Event IDs is discussed 
in Section 18.18.5, which covers feature-specific details.
Thread access to the IA32_QM_EVTSEL and IA32_QM_CTR MSR pair should be serialized (that is, treated as a 
critical section under lock) to avoid situations where one thread changes the RMID/EvtID just before another 
thread reads monitoring data from IA32_QM_CTR.
•IA32_QM_CTR: This MSR reports monitored data when ava ilable. It contains three bit fields. If software 
configures an unsupported RMID or event type in IA32_ QM_EVTSEL, then IA32_QM_CTR.Error (bit 63) will be 
set, indicating there is no valid data to report. If IA32_QM_CTR.Unavailable (bit 62) is set, it indicates 
monitored data for the RMID is not available, and IA32_Q M_CTR.data (bits 61:0) should be ignored. Therefore, 
IA32_QM_CTR.data (bits 61:0) is valid on ly if bit 63 and 62 are both clear. For Cache Monitoring Technology, 
software can convert IA32_QM_CTR.data into cache occu pancy or bandwidth metrics expressed in bytes by 
multiplying with the conversion fact or from CPUID.(EAX=0FH, ECX=1H).EBX.Vol. 3B 18-51DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.18.8 Monitoring Programming Considerations
Figure 18-25 illustrates how system software can program IA32_QOSEVTSEL and IA32_QM_CTR to perform 
resource monitoring.
Though the field provided in IA32_QM_CTR allows for up to 62  bits of data to be returned, often a subset of bits are 
used. With Cache Monitoring Technology for instance, the number of bits used is the base-two logarithm of the 
total cache size divided by th e Upscaling Factor from CPUID.
In Memory Bandwidth Monitoring, the initial counter size is 24 bits, and retrieving the value at 1Hz or faster is suffi-
cient to ensure at most one rollover per sampling period. Any changes to counter width are enumerated to soft-ware; see Section 18.18.5.2 for details.
18.18.8.1  Monitoring Dynamic Configuration 
Both the IA32_QM_EVTSEL and IA32_PQR_ASSOC registers are accessible and modifiable at any time during 
execution using RDMSR/WRMSR unless otherwise noted. When  writing to these MSRs a #GP(0) will be generated 
if any of the following conditions occur:
•A reserved bit is modified,
•An RMID exceeding the maximum RMID is used.
18.18.8.2  Monitoring Operation With Power Saving Features

Some advanced power management features such as deep  package C-states may shrink the L3 cache and cause 
CMT occupancy count to be reduced. MBM bandwidth counts may increase due to flushing cached data out of L3.Figure 18-24.  IA32_QM_EVTSEL and IA32_QM_CTR MSRs
Figure 18-25.  Software Usage of Cache Monitoring Resources0 63
IA32_QM_CTR U61
E Resource Monitoring Data0 31 63
RMID7
Reserved IA32_QM_EVTSEL Reserved41 3242 8
EvtID
RMID
0 63
Monitoring DataIA32_QM_CTR MSR
62
Availability
Error7 63
Reserved41
RMID
Resource Monitoring ID0
EvtID32
Reserved
Event IDIA32_QOSEVTSEL MSRSystem Software
Event IDCounter Data18-52 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
18.18.8.3  Monitoring Operation with Other Operating Modes
The states in IA32_PQR_ASSOC and monitoring counter ar e unmodified across an SMI delivery. Thus, the execu-
tion of SMM handler code and SMM handler’s data can mani fest as spurious contribution in the monitored data. 
It is possible for an SMM handler to minimize the impact on of spurious contribution in the QOS monitoring counters 
by reserving a dedicated RMID for monitoring the SMM ha ndler. Such an SMM handler can save the previously 
configured QOS Monitoring state immediately upon entering  SMM, and restoring the QOS monitoring state back to 
the prev-SMM RMID upon exit.
18.18.8.4  Monitoring Operation with RAS Features
In general, the Reliability, Availability, and Serviceability (RAS) features present in Intel Platforms are not expected 
to significantly affect shared resource monitoring counts. In cases where software RAS features cause memory 
copies or cache accesses, these may be tracked and may influence the shared resource monitoring counter values.
18.19 INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) ALLOCATION 
FEATURES
The Intel Resource Director Technology (Intel RDT) feature set provides a set of allocation (resource control) capa-
bilities including Cache Allocation Technology (CAT) an d Code and Data Prioritization (CDP). The Intel Xeon 
processor E5 v4 family (and a subset of communication-foc used processors in the Intel Xeon E5 v3 family) intro-
duce capabilities to configure and make use of the Cache A llocation Technology (CAT) mechanisms on the L3 cache. 
Certain Intel Atom processors also provide support for control over the L2 cache, with capabilities as described 
below. The programming interface for Cache Allocation Tech nology and for the more general allocation capabilities 
are described in the rest of this chapter. The CAT and CDP capabilities, where architecturally supported, may be 
detected and enumerated in software using the CPUID instruction, as described in this chapter.
The Intel Xeon Scalable Processor Family introduces the Memory Bandwidth Allocation (MBA) feature which 
provides indirect control over the memo ry bandwidth available to CPU cores, and is discussed later in this chapter.
18.19.1 Introduction to Cache Allocation Technology (CAT)
Cache Allocation Technology enables an Operating System  (OS), Hypervisor /Virtual Machine Manager (VMM) or 
similar system service management agent to specify the amount of cache space into which an application can fill 
(as a hint to hardware - certain features such as powe r management may override CAT settings). Specialized user-
level implementations with minimal OS support are also possible, though not necessarily recommended (see notes 
below for OS/Hypervisor with respect to ring 3 software an d virtual guests). Depending on the processor family, L2 
or L3 cache allocation capability may be provided, and the techno logy is designed to scale across multiple cache 
levels and technology generations.
Software can determine which levels are supported in a given platform programmatically using CPUID as described 
The CAT mechanisms defined in this document provide the following key features:
•A mechanism to enumerate platform Cache Allocation Technology capabilities and available resource types that 
provides CAT control capabilities. For implementations that support Cache Allocation Technology, CPUID 
provides enumeration support to query which levels of  the cache hierarchy are supported and specific CAT 
capabilities, such as the max allocation bitmask size, 
•A mechanism for the OS or Hypervisor to configure the am ount of a resource available to a particular Class of 
Service via a list of allocation bitmasks, 
•Mechanisms for the OS or Hypervisor to signal the Cl ass of Service to which an application belongs, and
•Hardware mechanisms to guide the LLC fill policy when an application has been de signated to belong to a 
specific Class of Service.
Note that for many usages, an OS or Hypervisor may not want to expose Cache Allocation Technology mechanisms 
to Ring3 software or virtualized guests.Vol. 3B 18-53DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
The Cache Allocation Technology feature enables more cache resources (i.e., cache space) to be made available for 
high priority applications based on guidance from the execution environment as shown in Figure 18-26. The archi-tecture also allows dynamic resource reassignment during runtime to further optimize the performance of the high 
priority application with minimal degradation to the low pr iority app. Additionally, resources can be rebalanced for 
system throughput benefit across uses cases of OSes, VMMs, containers, and other scenarios by managing the 
CPUID and MSR interfaces. This section describes the hard ware and software support required in the platform 
including what is required of the exec ution environment (i.e., OS/VMM) to support such resource control. Note that 
in Figure 18-26 the L3 Cache is shown as an example resource.
18.19.2 Cache Allocation Technology Architecture
The fundamental goal of Cache Allocation Technology is to enable resource allocation based on application priority 
or Class of Service (COS or CLOS). The processor exposes a set of Classes of Service into which applications (or 
individual threads) can be assigned. Cache allocation for the respective applications or threads is then restricted 
based on the class with which they are associated. Each Cl ass of Service can be configured using capacity bitmasks 
(CBMs) which represent capacity and indicate the degree of overlap and isolation between classes. For each logical processor there is a register exposed (referred to here as the IA32_PQR_ASSOC MSR or PQR) to allow the OS/VMM 
to specify a COS when an applicat ion, thread or VM is scheduled. 
The usage of Classes of Service (COS) are consistent across resources and a COS may have multiple resource 
control attributes attached, which reduces software overhead at context swap time. Rather than adding new types 
of COS tags per resource for instance, the COS management overhead is constant. Cache allocation for the indi-cated application/thread/container/VM is then controlled automatically by the hardware based on the class and the 
bitmask associated with that class. Bitmasks are co nfigured via the IA32_resourceType_MASK_n MSRs, where 
resourceType indicates a resource type (e.g., “L3” for the L3 cache) and “n” indicates a COS number. 
The basic ingredients of Cache Allocation Technology are as follows:
•An architecturally exposed mechanism using CPUID to indicate whether CAT is supported, and what resource 
types are available which can be controlled,
•For each available resourceType, CPUID also enumerates th e total number of Classes of Services and the length 
of the capacity bitmasks that can be used to enforce cache allocation to applications on the platform, 
•An architecturally exposed mechanism to allow the exec ution environment (OS/VMM) to configure the behavior 
of different classes of service using the bitmasks available, 
•An architecturally exposed mechanism to allow the execution environment (OS/VMM) to assign a COS to an 
executing software thread (i.e., associating the ac tive CR3 of a logical processor with the COS in 
IA32_PQR_ASSOC), 
•Implementation-dependent mechanisms to indicate whic h COS is associated with a memory access and to 
enforce the cache allocation on a per COS basis.
A capacity bitmask (CBM) provides a hint to the hardware  indicating the cache space an application should be 
limited to as well as providing an indication of overlap and isolation in the CAT-capable cache from other applica-tions contending for the cache. The bit length of the ca pacity mask available generally depends on the configura-Figure 18-26.  Cache Alloca tion Technology Enables Allocation of More  Resources to High Priority ApplicationsWithout CAT
Core 0
Shared LLC, Low priority got more cacheLo Pri App Hi Pri App
Core 1 Core 0
Shared LLC, High priority got more cacheLo Pri App Hi Pri App

Core 0
Core 1With CAT18-54 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
tion of the cache and is specified in the enumeration proc ess for CAT in CPUID (this may vary between models in a 
processor family as well). Similarly, other parameters such as the number of supported COS may vary for each 
resource type, and these details can be enumerated via CPUID. 
Sample cache capacity bitmasks for a bit length of 8 are sh own in Figure 18-27. Note that all (and only) contiguous 
'1' combinations are allowed (e.g., FFFFH, 0FF0H, 003CH, etc.), unless otherwise non-contiguous capacity bitmask 
support is specified in CPUID enumeration for the resource  type. Attempts to program a value without contiguous 
'1's (including zero) will result in a general protection fault (#GP(0)). It is generally expected that in way-based 
implementations, one capacity mask bit corresponds to some  number of ways in cache, but the specific mapping is 
implementation-dependent. In all cases, a mask bit set to '1 ' specifies that a particular Class of Service can allocate 
into the cache subset represented by that bit. A value of '0' in a mask bit specifies that a Class of Service cannot 
allocate into the given cache subset. In general, allocating more cache to a given application is usually beneficial to 
its performance. 
Figure 18-27 also shows three examples  of sets of Cache Capacity Bitmasks. For simplicity these are represented 
as 8-bit vectors, though this may vary depending on the implementation and how the mask is mapped to the avail-
able cache capacity. The first example shows the default ca se where all 4 Classes of Service (the total number of 
COS are implementation-dependent) have full access to th e cache. The second case shows an overlapped case, 
which would allow some lower-priority threads to share cache space with the highest priority threads. The third case shows various non-overlapped partitioning schemes. As a matter of software policy for extensibility, COS0 
should typically be considered and configured as the high est priority COS, followed by COS1, and so on, though 
there is no hardware restriction enforcing this mapping. When the system boots all threads are initialized to COS0, 
which has full access to the cache by default.
Though the representation of the CBMs looks similar to a way-based mapping they are independent of any specific 
enforcement implementation (e.g., way partitioning.) Rath er, this is a convenient manner to represent capacity, 
overlap, and isolation of cache space. For example, executing a POPCNT instruction (population count of set bits) Figure 18-27.  Examples of Cache Capacity BitmasksM7 M6 M5 M4 M3 M2 M1 M0
A A A A A A A A
A A A A A A A A
A A A A A A A A
A A A A A A A ACOS0
COS1COS2COS3Default Bitmask
M7 M6 M5 M4 M3 M2 M1 M0
A A A A
A A
A
ACOS0COS1COS2
COS3Isolated BitmaskM7 M6 M5 M4 M3 M2 M1 M0
A A A A A A A A
A A A A
A A
ACOS0
COS1COS2COS3Overlapped BitmaskVol. 3B 18-55DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
on the capacity bitmask can provide the fraction of cache sp ace that a class of service can allocate into. In addition 
to the fraction, the exact location of the bits also shows whether the class of service overlaps with other classes of service or is entirely isolated in terms of cache space used. 
Figure 18-28 shows how the Cache Capacity Bitmasks and the per-logical-processor Class of Service are logically 
used to enable Cache Allocation Technology. All (and on ly) contiguous 1's in the CBM are permitted, unless other-
wise non-contiguous capacity bitmask support is specifie d in CPUID enumeration for the resource type. The length 
of a CBM may vary from resource to resource or betw een processor generations and can be enumerated using 
CPUID. From the available mask set and based on the goals of the OS/VMM (shared or isolated cache, etc.) 
bitmasks are selected and associated with different classes of service. For the available Classes of Service the asso-
ciated CBMs can be programmed via the global set of CAT configuration registers (in the case of L3 CAT, via the 
IA32_L3_MASK_n MSRs, where “n” is the Cl ass of Service, starting from zero). In all architectural implementations 
supporting CPUID it is possible to change the CBMs dynamically, during program execution, unless stated other-wise by Intel. 
The currently running application's Class of Service is  communicated to the hardware through the per-logical-
processor PQR MSR (IA32_PQR_ASSOC MSR). When the OS schedules an application thread on a logical processor, 
the application thread is associated with a specific COS (i .e., the corresponding COS in the PQR) and all requests to 
the CAT-capable resource from that logical processor are tagged with that COS (in other words, the application thread is configured to belong to a specific COS). Th e cache subsystem uses this tagged request information to 
enforce QoS. The capacity bitmask may be mapped into a way bitmask (or a similar enforcement entity based on 
the implementation) at the cache before it is applied to the allocation policy. For example, the capacity bitmask can 
be an 8-bit mask and the enforcement may be accomp lished using a 16-way bitmask for a cache enforcement 
implementation based on way partitioning.
The following sections describe extensions of CAT such as Code and Data Prioritization (CDP), followed by details 
on specific features such as L3 CAT, L3 CDP, L2 CAT, and L2 CDP. Depending on the specific processor a mix of 
features may be supported, and CPUID provides enumeratio n capabilities to enable software to dynamically detect 
the set of supp orted features. Figure 18-28.  Class of Serv ice and Cache Ca pacity BitmasksSet 1
Set 2
....Cache SubsystemConfigTag with CacheEnforcement
Set n
way 1
......
way 16Enforce Mask
Capacity bitmask 3 COS 3Capacity bitmask 3 COS 2Capacity bitmask 3 COS 1Capacity bitmask 3 COS 0Cache AllocationTransaction COSCOS = 2 Mem RequestClass of ServiceApplication
Memory Request
Set Class of ServiceAssociation
in IA32_PQROS Context
Switch
Configure CBM for Enum/Confg
each Class of ServiceEnumerate
Enforcement
218-56 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
18.19.3 Code and Data Prioritization (CDP) Technology
Code and Data Prioritization Technology is an extension of  CAT. CDP enables isolation and separate prioritization of 
code and data fetches to the L2 or L3 cache in a softwa re configurable manner, depe nding on hardware support, 
which can enable workload prioritization and tuning of ca che capacity to the characteristics of the workload. CDP 
extends Cache Allocation Technology (CAT) by providing se parate code and data masks per Class of Service (COS). 
Support for the L2 CDP feature and the L3 CDP features are separately enumerated (via CPUID) and separately 
controlled (via remapping the L2 CAT MSRs or L3 CAT MSRs respectively). Section 18.19.6.3 and Section 18.19.7 provide details on enumerating, controlling, and enabling L3  and L2 CDP respectively, while this section provides a 
general overview.
The L3 CDP feature was first introduced on the Intel Xeon E5  v4 family of server processors, as an extension to L3 
CAT. The L2 CDP feature is first introduced on future In tel Atom family processors, as an extension to L2 CAT.
By default, CDP is disabled on the processor. If the CA T MSRs are used without enabling CDP, the processor oper-
ates in a traditional CAT-only mode. When CDP is enabled, 
•the CAT mask MSRs are re-mapped into interleaved pa irs of mask MSRs for data or code fetches (see 
Figure 18-29), 
•the range of COS for CAT is re-indexed, with the lower-half of the COS range available for CDP. 
Using the CDP feature, virtual isolation between code and data  can be configured on the L2 or L3 cache if desired, 
similar to how some processor cache levels provide separate L1 data and L1 instruction caches. 
Like the CAT feature, CDP may be dynamically configured by  privileged software at any point during normal system 
operation, including dynamically enabling or disabling th e feature provided that certain software configuration 
requirements are met (see Section 18.19.5). 
An example of the operating mode of CDP is shown in Figure 18-29. Shown at the top are traditional CAT usage 
models where capacity masks map 1:1 with a COS number to enable control over the cache space which a given 
COS (and thus applications, threads or VMs) may occupy. Shown at the bottom are example mask configurations where CDP is enabled, and each COS number maps 1:2 to two masks, one for code and one for data. This enables 
code and data to be either overlapped or isolated to varying degrees either globally or on a per-COS basis, 
depending on application and system needs.
Figure 18-29.  Code and Data Capacity Bitmasks of CDP1 1 1 1 000000000000
0000 1 1 0000000000
000000 1 1 1 1 1 00000

000000000 1 1 1 0000
000000000000 1 1 1 1
000000000000 1 1 1 1COS0.Data
COS0.CodeCOS1.DataCOS1.CodeCAT with1 1 1 1 000000000000
0000 1 1 1 1 00000000
00000000 1 1 000000
00000000 1 1 1 1 1 1 1 1COS0
COS1COS2COS3 Traditional
CAT
CDP
Other COS.DataExample of Code/Data Prioritizati on Usage - 16 bit Capacity MasksExample of CAT-Only Usage - 16 bit Capacity Masks
Other COS.CodeVol. 3B 18-57DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
When CDP is enabled, the existing mask space for CAT-only operation is split. As an exam ple if the system supports 
16 CAT-only COS, when CDP is enabled the same MSR inte rfaces are used, however half of the masks correspond 
to code, half correspond to data, and the effective number  of COS is reduced by half. Code/Data masks are defined 
per-COS and interleaved in the MSR space as described in subsequent sections.
In cases where CPUID exposes a non-even number of suppo rted Classes of Service for the CAT or CDP features, 
software using CDP should use the lower matched pairs of  code/data masks, and any upper unpaired masks should 
not be used. As an example, if CPUID exposes 5 CLOS, wh en CDP is enabled then two code/data pairs are available 
(masks 0/1 for CLOS[0] data/code and masks 2/3 for CL OS[1] data/code), however the upper un-paired mask 
should not be used (mask 4 in this ca se) or undefined behavior may result.
18.19.4 Enabling Cache Alloca tion Technology Usage Flow
Figure 18-30 illustrates the key steps for OS/VMM to detect support of Cache Allocation Technology and enable 
priority-based resource allocation for a CAT-capable resource.
Enumeration and configuration of L2 CAT is similar to L3 CAT, however CPUID details and MSR addresses differ. 
Common CLOS are used across the features.
18.19.4.1  Enumeration and Detection Su pport of Cache Allocation Technology
Software can query processor support of CAT capabilities  by executing CPUID instruct ion with EAX = 07H, ECX = 
0H as input. If CPUID.(EAX=07H, ECX= 0):EBX.PQE[bit 15] reports 1, the processor supports software control over 
shared processor resources. Software must use CPUID le af 10H to enumerate additional details of available 
resource types, classes of services an d capability bitmasks. The programming interfaces provided by Cache Alloca-
tion Technology include:
•CPUID leaf function 10H (Cache Allocation Technology Enumeration leaf) and its sub-functions provide information on available resource types, and CAT capability for each resource type (see Section 18.19.4.2).
•IA32_L3_MASK_n: A range of MSRs is provided for each re source type, each MSR within that range specifying 
a software-configured capacity bitmask for each class of service. For L3 with Cache Allocation support, the CBM 
is specified using one of the IA32_L3_QOS_MASK_n MS R, where 'n' corresponds to a number within the 
supported range of COS, i.e., the range between 0 an d CPUID.(EAX=10H, ECX=ResID):EDX[15:0], inclusive. 
See Section 18.19.4.3 for details.
•IA32_L2_MASK_n: A range of MSRs is provided for L2 Ca che Allocation Technology, enabling software control 
over the amount of L2 cache available for each CLOS. Sim ilar to L3 CAT, a CBM is specified for each CLOS using 
the set of registers, IA32_L2_QOS_MASK_n MSR, where 'n' ranges from zero to the maximum CLOS number 
reported for L2 CAT in CPUID. See Section 18.19.4.3 for details.
The L2 mask MSRs are scoped at the same level as the L2  cache (similarly, the L3 mask MSRs are scoped at the 
same level as the L3 cache). Software may determine which logical processors share an MSR (for instance local Figure 18-30.  Cache Alloca tion Technology Usage FlowCPUID.(7,0):EBX.15On OS/VMM Initialization
CPUID.(10H,0):EBX[31:1]CQE Capability
IA32_L3_QOS_MASK_0Cache Allocation Configuration
...Configure CBM
per COSOn Context Switch
IA32_PQR_ASSOCSet COS for scheduled
thread context
IA32_L3_QOS_MASK_nCPUID.(10H,1):EAX[4:0]
CPUID.(10H,1):EDX[15:0]
CPUID.(10H,1):EBX[CPUID[ WRMSR WRMSR18-58 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
to a core, or shared across multiple cores) by performing  a write to one of these MSRs and noting which logical 
threads observe the change. Example flows for a similar method to determine register scope are described in 
Section 16.5.2, “System Software Recommendation for Managing CMCI and Machine Check Resources.” 
Software may also use CPUID leaf 4 to determine the maximum number of logical processor IDs that may share 
a given level of the cache.
•IA32_PQR_ASSOC.CLOS: The IA32_PQR_ASSOC MSR provides  a COS field that OS/VMM can use to assign a 
logical processor to an available COS. The set of COS are common across all allocation features, meaning that 
multiple features may be supported in the same pr ocessor without additional software COS management 
overhead at context swap time. See Section 18.19.4.4 for details. 
18.19.4.2  Cache Allocation Technology: Re source Type and Capability Enumeration
CPUID leaf function 10H (Cache Allocation Technology Enumeration leaf) provides two or more sub-functions:
•CAT Enumeration leaf sub-function 0 enumerates available resource types that support allocation control, i.e., 
by executing CPUID with EAX=10H and ECX=0H. Each suppor ted resource type is represented by a bit field in 
CPUID.(EAX=10H, ECX=0):EBX[31:1]. The bit position of each set bit corresponds to a Resource ID (ResID), 
for instance ResID=1 is used to indicate L3 CAT suppor t, and ResID=2 indicates L2 CAT support. The ResID is 
also the sub-leaf index that software must use to query de tails of the CAT capability of that resource type (see 
Figure 18-31). 
— For ECX>0, EAX[4:0] reports the length of the capaci ty bitmask (ECX=1 or 2 for L3 CAT or L2 CAT respec-
tively). Add one to the return value to get the result, e.g., a value of 15 corresponds to the capacity bitmask 
having length of 16 bits. Bits 31:5 of EAX are reserved.
•Sub-functions of CPUID.EAX=10H with a non-zero EC X input matching a supported ResID enumerate the 
specific enforcement details of the corresponding ResID. The capabilities enumerated include the length of the 
capacity bitmasks and the number of Classes of Service for a given ResID. Software should query the capability of each available ResID that supports CAT from a sub-leaf  of leaf 10H using the sub-leaf index reported by the 
corresponding non-zero bit in CPUI D.(EAX=10H, ECX=0 ):EBX[31:1] in order to obtain additional feature 
details. Figure 18-31.  CPUID.(EAX=10H, ECX=0H) Available Resource Type IdentificationM
B
AL
2L
34     3     2     1     0
EBX31CPUID.(EAX=10H, ECX=0) Output: (EAX: Reserved; ECX: Reserved; EDX: Reserved)
ReservedVol. 3B 18-59DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
•CAT capability for L3 is enumerated by CPUID.(EAX =10H, ECX=1H), see Figure  18-32. The specific CAT 
capabilities reported by CPUID.(EAX=10H, ECX=1) are:
— CPUID.(EAX=10H, ECX=ResID= 1):EAX[4:0] reports the length of the capacity bitmask. Add one to the 
return value to get the result, e.g., a value of 15 co rresponds to the capability bitmask having length of 16 
bits. Bits 31:5 of EAX are reserved.
— CPUID.(EAX=10H, ECX=1):EBX [31:0] reports a bit mask. Each set bit within the length of the CBM 
indicates the corresponding unit of the L3 allocation may be used by other entities in the platform (e.g., an 
integrated graphics engine or hardware units outside th e processor core and have direct access to L3). Each 
cleared bit within the length of the CBM indicates the corresponding allocation unit can be configured to 
implement a priority-based allocation scheme chosen  by an OS/VMM without interference with other 
hardware agents in the system. Bits outs ide the length of the CBM are reserved.
— CPUID.(EAX=10H, ECX=1 ):ECX[bit 1]: If 1, indicates L3 CAT for non-CPU agents is supported. Bits 0 and 
31:4 of ECX are reserved. See section 18.20 for details.
— CPUID.(EAX=10H, ECX=1):ECX.C DP[bit 2]: If 1, indicates L3 Code and Data Prioritization Technology is 
supported (see Section 18.19.5). Bits 0 and 31:4 of ECX are reserved.
— CPUID.(EAX=10H, ECX=1 ):ECX[bit 3]: If 1, indicates non-contiguo us capacity bitmask is supported. The 
bits that are set in the various IA32_L3_MASK_n regist ers do not have to be contiguous. Bits 0 and 31:4 of 
ECX are reserved.
— CPUID.(EAX=10H, ECX=1):EDX[15:0]  reports the maximum COS supported for the resource (COS are 
zero-referenced, meaning a reported value of '15' wo uld indicate 16 total supported COS). Bits 31:16 are 
reserved.Figure 18-32.  L3 Ca che Allocation Technology and CDP Enumeration 0 4 5 31
CBM_LEN Reserved EAX
0 31
Bitmask of Shareable Resource with Other Executing Entities EBX
31
Reserved ECX
0 15 16 31
COS_MAX Reserved EDXCPUID.(EAX=10H, ECX=ResID=1) Output:
3     2     1        0
CDP
Non-contiguous

0 31
31
0 15 16 31
3     2     1        0
CDP
Non-contiguous 
Capacity BitmaskL3 CAT for Non-CPU Agents18-60 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
•CAT capability for L2 is enumerated by CPUID.(EAX =10H, ECX=2H), see Figure  18-33. The specific CAT 
capabilities reported by CPUID.(EAX=10H, ECX=2) are:
— CPUID.(EAX=10H, ECX=ResID=2):EAX[4 :0] reports the length of the capacity bitmask. Add one to the 
— CPUID.(EAX=10H, ECX=2):EBX[31:0] reports a bit ma sk. Each set bit within the length of the CBM 
indicates the corresponding unit of the L2 allocation may be used by other entities in the platform. Each 
hardware agents in the system. Bits outs ide the length of th e CBM are reserved.
— CPUID.(EAX=10H, ECX=2):ECX.C DP[bit 2]: If 1, indicates L2 Code and Data Prioritization Technology is 
supported (see Section 17.19.6). Bits 1:0 and 31:4 of ECX are reserved.
— CPUID.(EAX=10H, ECX=2):ECX[bit 3]: If 1, indicates non-contiguous ca pacity bitmask is supported. The 
bits which are set in the various IA32_L2_MASK_n regist ers do not have to be contiguous. Bits 1:0 and 31:4 
of ECX are reserved.
— CPUID.(EAX=10H, ECX=2):EDX[15:0] reports the ma ximum COS supported for the resource (COS are 
reserved.
A note on migration of Classes of Service (COS): Software should minimize migrations of COS across logical 
processors (across threads or cores), as a reduction in th e performance of the Cache Allocation Technology feature 
may result if COS are migrated frequently. This is aligne d with the industry-standard practice of minimizing unnec-
essary thread migrations across processor cores in orde r to avoid excessive time spent warming up processor 
caches after a migration. In general, for best performa nce, minimize thread migration and COS migration across 
processor logical threads and processor cores.Figure 18-33.  L2 Cach e Allocation Technology  Bitmask of Shareable Resource with Other Executing Entities0 31
3    2    1    0 31                                   Reserved0 31
ECXEBXEAX CBM_LEN
0 31
COS_MAX15
EDX CPUID.(EAX=10H, ECX=ResID=2) Output:
Reserved
CDP5   4
Non-Contiguous 
Capacity BitmaskVol. 3B 18-61DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.19.4.3  Cache Allocation Technology: Cache Mask Configuration
After determining the length of the capacity bitmas ks (CBM) and number of COS supported using CPUID (see 
Section 18.19.4.2), each COS needs to be programmed with  a CBM to dictate its available cache via a write to the 
corresponding IA32_resourceType_MASK_n register, where 'n' corresponds to a number within the supported 
range of COS, i.e., the range between 0 and CPUID.(EAX =10H, ECX=ResID):EDX[15:0], inclusive, and 'resource-
Type' corresponds to a specific resource as enumerated  by the set bits of CPUID.(EAX=10H, ECX=0):EBX[31:1], 
for instance, ‘L2’ or ‘L3’ cache. 
A hierarchy of MSRs is reserved for Cache Allocati on Technology registers of the form IA32_resource-
Type_MASK_n: 
•From 0C90H through 0D8FH (inclusive),  providing support for multiple sub-ranges to support varying resource 
types. The first supported resource type is 'L3', corresp onding to the L3 cache in a platform. The MSRs range 
from 0C90H through 0D0FH (inclusive), enables supp ort for up to 128 L3 CAT Classes of Service. 
•Within the same CAT range hierarchy, another set of registers is defined for resourceType 'L2', corresponding 
to the L2 cache in a platform, and MSRs IA32_L2_M ASK_n are defined for n=[0,63] at addresses 0D10H 
through 0D4FH (inclusive). 
Figure 18-34 and Figure 18-35 provide an overview of the relevant registers. 
All CAT configuration registers can be accessed using the standard RDMSR / WRMSR instructions. 
Note that once L3 or L2 CAT masks are configured, thread s can be grouped into Classes of Service (COS) using the 
IA32_PQR_ASSOC MSR as described in Section 18.19.4.4, “Class of Service to Cache Mask Association: Common 
Across Allocation Features.”
18.19.4.4  Class of Service to Cache Mask Association: Common Across Allocation Features
After configuring the available classes of service with th e preferred set of capacity bitmasks, the OS/VMM can set 
the IA32_PQR_ASSOC.COS of a logical processor to the cl ass of service with the desired CBM when a thread Figure 18-34.  IA32_PQR_ASSOC, IA32_L3_MASK_n MSRs
Figure 18-35.  IA32_L2_MASK_n MSRs0 10 63
RMID9
Reserved IA32_PQR_ASSOC
IA32_L3_MASK_n0 31 63
Reserved IA32_L3_MASK_032
Bit_Mask31
COS
....
0 31 63
Reserved32
Bit_Mask
IA32_L2_MASK_n0 31 63
Reserved IA32_L2_MASK_032
Bit_Mask
....
0 31 63
Bit_Mask18-62 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
context switch occurs. This allows the OS/VMM to indicate  which class of service an executing thread/VM belongs 
within. Each logical processor contains an instance of the IA32_PQR_ASSOC register at MSR location 0C8FH, and 
Figure 18-34 shows the bit field layout for this register. Bi ts[63:32] contain the COS field for each logical processor. 
Note that placing the RMID field within the same PQR re gister enables both RMID and CLOS to be swapped at 
context swap time for simultaneous use of monitoring and allocation features with a single register write for effi-
ciency. 
When CDP is enabled, Specifying a COS value in  IA32_PQR_ASSOC.COS grea ter than MAX_COS_CDP =
(CPUID.(EAX=10H, ECX=1):EDX[15:0] >> 1) will cause undefined performance impact to code and data fetches. 
In all cases, code and data masks for L2 and L3 CDP should be programmed with at least one bit set.
Note that if the IA32_PQR_ASSOC.COS is  never written then the CAT capability defaults to using COS 0, which in 
turn is set to the default mask in IA32_L3_MASK_0 - which is all “1”s (on reset). This essentially disables the enforcement feature by default or for legacy operating systems and software.
See Section 18.19.7, “Introduction to Memory Bandwidt h Allocation,” for important COS programming consider-
ations including maximum valu es when using CAT and CDP.
18.19.5 Code and Data Prioritization (CDP): Enumerating and Enabling L3 CDP Technology 
L3 CDP is an extension of L3 CAT. The presence of the L3 CDP feature is enumerated via CPUID.(EAX=10H, 
ECX=1):ECX.CDP[bit 2] (see Figure 18-32). Most of the CPUID.(EAX=10H, ECX=1) sub-leaf data that applies to 
CAT also apply to CDP. However, CPUID.(EAX=10H, ECX=1):EDX.COS_MAX_CAT specifies the maximum COS 
applicable to CAT-only operation. For CDP operat ions, COS_MAX_CDP is equa l to (CPUID.(EAX=10H, 
ECX=1):EDX.COS_MAX_CAT >>1). 
If CPUID.(EAX=10H, ECX=1 ):ECX.CDP[bit 2] =1, the processor su pports CDP and provides a new MSR 
IA32_L3_QOS_CFG at address 0C81H. The layout of IA32_L 3_QOS_CFG is shown in Figure 18-36. The bit field 
definition of IA32_L3_QOS_CFG are:
•Bit 0: L3 CDP Enable. If set, enables CDP, maps CAT ma sk MSRs into pairs of Data Mask and Code Mask MSRs. 
The maximum allowed value to write in to IA32_PQR_ASSOC.COS is COS_MAX_CDP.
•Bits 63:1: Reserved. Attemp ts to write to reserved bits result in a #GP(0).
IA32_L3_QOS_CFG default values are all 0s at RESET, the mask MSRs are all 1s. Hence, all logical processors are 
initialized in COS0 allocated with the entire L3 with CD P disabled, until software programs CAT and CDP. The scope 
of the IA32_L3_QOS_CFG MSR is defined to be the same scope as the L3 cache (e.g., typically per processor 
socket). Refer to Section 18.19.7 for software considerations while enabling or disabling L3 CDP.
18.19.5.1  Mapping Between L3 CDP Masks and CAT Masks
When CDP is enabled, the existing CAT mask MSR space is  re-mapped to provide a code mask and a data mask per 
COS. The re-mapping is shown in Table 18-19.Figure 18-36.  Layout of IA32_L3_QOS_CFG0 2 63 1
ReservedIA32_L3_QOS_CFG
3
L3 CDP EnableVol. 3B 18-63DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
Table 18-19.  Re-indexing of COS Numbers and Mapping to CAT/CDP Mask MSRs
One can derive the MSR address for the data mask or code mask for a given COS number ‘n’ by:
•data_mask_address (n) = base + (n <<1), where base is the address of IA32_L3_QOS_MASK_0.
•code_mask_address (n) = base + (n <<1) +1.
When CDP is enabled, each COS is mapped 1:2 with ma sk MSRs, with one mask enabling programmatic control 
over data fill location and one mask enabling control over  code placement. A variety of overlapped and isolated 
mask configurations are possible (see the example in Figure 18-29).

3
mask configurations are possible (see the example in Figure 18-29). 
Mask MSR field definitions remain the same. Capacity masks must be formed of contiguous set bits, unless other-
wise non-contiguous capacity bitmask support is specif ied in CPUID enumeration for the resource type with a 
length of 1 bit or longer and should not exceed the maxi mum mask length specified in CPUID. As examples, valid 
masks on a cache with max bitmask length of 16b (fro m CPUID) include 0xFFFF, 0xFF 00, 0x00FF, 0x00F0, 0x0001, 
0x0003, and so on. Maximum valid mask lengths are unchan ged whether CDP is enabled or disabled, and writes of 
invalid mask values may lead to undefined behavior . Writes to reserved bits will generate #GP(0). 
18.19.6 Code and Data Prioritization (CDP): Enumerating and Enabling L2 CDP Technology
L2 CDP is an extension of the L2 CAT feature. The presence of the L2 CDP feature is enumerated via 
CPUID.(EAX=10H, ECX=2):ECX.C DP[bit 2] (see Figure 17-33). Most of  the CPUID.(EAX=10H, ECX=2) sub-leaf 
data that applies to CAT also apply to CDP. However,  CPUID.(EAX=10H, ECX=2):EDX .COS_MAX_CAT specifies the 
maximum COS applicable to CAT-only operation. For CDP operations, COS_MAX_CDP is equal to 
(CPUID.(EAX=10H, ECX=2):EDX.COS_MAX_CAT >>1). 
If CPUID.(EAX=10H, ECX=2 ):ECX.CDP[bit 2] =1, the processor supports L2 CDP and provides a new MSR 
IA32_L2_QOS_CFG at address 0C82H. The layout of IA3 2_L2_QOS_CFG is shown in Figure 18-37. The bit field 
definition of IA32_L2_QOS_CFG are:
•Bit 0: L2 CDP Enable. If set, enables CDP, maps CAT ma sk MSRs into pairs of Data  Mask and Code Mask MSRs. 
•Bits 63:1: Reserved. Attempts to write to reserved bits result in a #GP(0).Mask MSR CAT-only Operation CDP Operation
IA32_L3_QOS_Mask_0 COS0 COS0.DataIA32_L3_QOS_Mask_1 COS1 COS0.CodeIA32_L3_QOS_Mask_2 COS2 COS1.DataIA32_L3_QOS_Mask_3 COS3 COS1.CodeIA32_L3_QOS_Mask_4 COS4 COS2.DataIA32_L3_QOS_Mask_5 COS5 COS2.Code.... .... ....IA32_L3_QOS_Mask_’2n’ COS’2n’ COS’n’.DataIA32_L3_QOS_Mask_’2n+1’ COS’2n+1’ COS’n’.Code
Figure 18-37.  Layout of IA32_L2_QOS_CFG0 2 63 1
ReservedIA32_L2_QOS_CFG
3
L2 CDP Enable18-64 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
IA32_L2_QOS_CFG default values are all 0s at RESET, and the mask MSRs are all 1s. Hence all logical processors 
are initialized in COS0 allocated with the entire L2 available and with CDP disabled, until software programs CAT and CDP. The IA32_L2_QOS_CFG MSR is defined at the same scope as the L2 cache, typically at the module level 
for Intel Atom processors for instance. In processors with multiple modules present it is recommended to program 
the IA32_L2_QOS_CFG MSR consistently across all modules for simplicity.
18.19.6.1  Mapping Between L2  CDP Masks and L2 CAT Masks
COS. This remapping is the same as the remapping shown in Table 18-19 for L3 CDP, but for the L2 MSR block 
(IA32_L2_QOS_MASK_n) instead of the L3 MSR block (I A32_L3_QOS_MASK_n). The same code / data mask 
mapping algorithm applies to remapping the MSR block between code and data masks. 
As with L3 CDP, when L2 CDP is enabled, each COS is  mapped 1:2 with mask MSRs, with one mask enabling 
programmatic control over data fill location and one mask enabling control over code placement. A variety of over-
lapped and isolated mask configurations ar e possible (see the example in Figure 18-29). 
Mask MSR field definitions for L2 CDP remain the same as fo r L2 CAT. Capacity masks must be formed of contiguous 
set bits, unless otherwise non-contiguous capacity bitm ask support is specified in CPUID enumeration for the 
resource type with a length of 1 bit or longer and should  not exceed the maximum mask length specified in CPUID. 
As examples, valid masks on a cache with max bitmask length of 16b (from CPUID) include 0xFFFF, 0xFF00, 
0x00FF, 0x00F0, 0x0001, 0x0003, and so on. Maximum valid  mask lengths are unchanged whether CDP is enabled 
or disabled, and writes of invalid mask values may lead to undefined behavior. Writes to reserved bits will generate 
#GP(0).
18.19.6.2  Common L2 and L3 CDP Programming Considerations
Before enabling or disabling L2 or L3 CDP, software shou ld write all 1's to all of the corresponding CAT/CDP masks 
to ensure proper behavior (e.g., the IA32_L3_QOS_Mask_n set of MSRs for the L3 CAT feature). When enabling 
CDP, software should also ensure that only COS number which are valid in CDP operation is used, otherwise unde-
fined behavior may result. For instance in a case with 16 CAT COS, since COS are reduced by half when CDP is enabled, software should ensure that only COS 0-7 are in  use before enabling CDP (along with writing 1's to all 
mask bits before enabling or disabling CDP). 
Software should also account for the fact that mask interpretations change when CDP is enabled or disabled, 
meaning for instance that a CAT mask for a given COS ma y become a code mask for a different Class of Service 
when CDP is enabled. In order to simplify this beha vior and prevent unintended remapping software should 
consider resetting all threads to COS[0] before enabling or disabling CDP.
18.19.6.3  Cache Allocation Technology Dynamic Configuration 
All Intel Resource Director Technology (Intel RDT) interfaces including the IA32_PQR_ASSOC MSR, CAT/CDP 
masks, MBA delay values, and CQM/MBM registers are accessible and modifiable at any time during execution using RDMSR/WRMSR unless otherwise noted. When writing to  these MSRs a #GP(0) will be generated if any of the 
following conditions occur:
•Accessing a QOS mask register outside the support ed COS (the max COS number is specified in 
CPUID.(EAX=10H, ECX=Re sID):EDX[15:0]), or
•Writing a COS greater than the supported maximum (s pecified as the maximum value of CPUID.(EAX=10H, 
ECX=ResID):EDX[15:0] for all valid ResID values) is written to the IA32_PQR_ASSOC.CLOS field.
When CDP is enabled, specifying a COS value in IA32_PQR _ASSOC.COS outside of the lower half of the COS space 
will cause undefined performance impact to code and data  fetches due to MSR space re-indexing into code/data 
masks when CDP is enabled.
When reading the IA32_PQR_ASSOC register the current ly programmed COS on the core will be returned. 
When reading an IA32_ resourceType _MASK_ n register the current capacity bit mask for COS 'n' will be returned.Vol. 3B 18-65DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
As noted previously, software should minimize migrations of COS across logical processors (across threads or 
cores), as a reduction in the accuracy of the Cache Alloca tion feature may result if COS are migrated frequently. 
This is aligned with the industry standard practice of minimizing unnecessary thread migrations across processor 
cores in order to avoid excessive time spent warming up pr ocessor caches after a migration. In general, for best 
performance, minimize thread migration and COS migration across processor logical threads and processor cores.
18.19.6.4  Cache Allocation Technology Operation With Power Saving Features
Note that the Cache Allocation Technology feature canno t be used to enforce cache coherency, and that some 
advanced power management features such as C-states wh ich may shrink or power off various caches within the 
system may interfere with CAT hints - in such cases th e CAT bitmasks are ignored and the other features take 
precedence. If the highest possible le vel of CAT differentiation or determinism is required, disable any power-
saving features which shrink the caches or power off ca ches. The details of the power management interfaces are 
typically implementation-specific, but can be found at Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3C. 
If software requires differentiation between threads but no t absolute determinism then in many cases it is possible 
to leave power-saving cache shrink features enabled, which can provide substantial power savings and increase 
battery life in mobile platforms. In such cases when the caches are powered off (e.g., package C-states) the entire 
cache of a portion thereof may be powered off. Upon resumi ng an active state any new incoming data to the cache 
will be filled subject to the cache capacity bitmasks. Any data in the cache prior to the cache shrink or power off 
may have been flushed to memory during the process of ente ring the idle state, however, and is not guaranteed to 
remain in the cache. If differentiation between threads is  the goal of system software then this model allows 
substantial power savings while continuing to deliver performance differentiation. If system software needs 
optimal determinism then power saving modes which flush portions of the caches and power them off should be 
disabled.
NOTE

disabled.
NOTE
IA32_PQR_ASSOC is saved and restored across C6 entr y/exit. Similarly, the mask register contents 
are saved across package C-state entry/exit and are not lost.
18.19.6.5  Cache Allocation Technology  Operation with Other Operating Modes
The states in IA32_PQR_ASSOC and mask registers are unm odified across an SMI delivery. Thus, the execution of 
SMM handler code can interact with the Cache Allocation  Technology resource and manifest some degree of non-
determinism to the non-SMM software stack. An SMM ha ndler may also perform certain system-level or power 
management practices that affect CAT operation. 
It is possible for an SMM handler to mi nimize the impact on data determinism in the cache by reserving a COS with 
a dedicated partition in the cache. Such an SMM hand ler can switch to the dedicated COS immediately upon 
entering SMM, and switching back to the previously running COS upon exit.
18.19.6.6  Associating Threads wi th CAT/CDP Classes of Service 
Threads are associated with Classes of Service (CLOS) via the per-logical-processor IA32_PQR_ASSOC MSR. The 
same COS concept applies to both CAT and CDP (for inst ance, COS[5] means the same thing whether CAT or CDP 
is in use, and the COS has associated resource usage co nstraint attributes including cache capacity masks). The 
mapping of COS to mask MSRs does change when CDP is enabled, according to the following guidelines:
•In CAT-only Mode - one set of bitmasks in  one mask MSR control both code and data.
— Each COS number map 1:1 with a capacity mask on the applicable resource (e.g., L3 cache).
•When CDP is enabled, 
— Two mask sets exist for each COS number, one for code, one for data. 
— Masks for code/data are interleaved in the MSR address space (see Table 18-19).18-66 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
18.19.7 Introduction to Memory Bandwidth Allocation
The Memory Bandwidth Allocation (MBA) feature provides indirect and approximate control over memory band-
width available per-core. It was introduced in the Intel Xeon Scalable Processor Family. This feature provides a 
method to control applications that may be over-utilizing bandwidth relative to their priority in environments such as the data-center. 
The MBA feature uses existing constructs from the Intel RDT feature set, including Classes of Service (CLOS). A 
given CLOS used for L3 CAT, for instance, means the same thing as a CLOS used for MBA. Infrastructure, such as 
the MSR used to associate a thread with a CLOS (the  IA32_PQR_ASSOC_MSR) and some elements of the CPUID 
enumeration (such as CPUID leaf 10H), are shared. Certai n generations include advanced hardware controllers for 
efficiency. For more information, refer to the “Intel
® Resource Director Technology Architecture Specification.”
The following sections describe CPU interfaces to Memory  Bandwidth Allocation, such as CPUID enumeration and 
configuration interfaces (MSRs).
18.19.7.1  Memory Bandwidth Allocation Enumeration
Similar to other Intel RDT features, enumeration of the pr esence and details of the MBA feature is provided via a 
sub-leaf of the CPUID instruction. 
Key components of the enumeration are as follows.
•Support for the MBA feature on the processor, and if MBA is supported, the following details: — Number of supported Classes of Service (CLOS) for the processor. 
— The maximum MBA delay value supported (which also im plicitly provides a definition of the granularity).
— An indication of whether the delay values which can be programmed are linearly spaced or not.
The presence of any of the Intel RDT features which enable  control over shared platform resources is enumerated 
by executing CPUID instruction with EAX = 07H, ECX = 0H  as input. If CPUID.(EAX=0 7H, ECX=0):EBX.PQE[bit 15] 
reports 1, the processor supports software control over shared processor resources. Software may then use CPUID 
leaf 10H to enumerate additional detail s on the specific controls provided. 
Through CPUID leaf 10H software may determine whether MB A is supported on the platform. Specifically, as shown 
in Figure 18-31, bit 3 of the EBX register indicates whethe r MBA is supported on the processor, and the bit position 
(3) constitutes a Resource ID (ResID) which allows enumeration of MBA details. For instance, if bit 3 is supported this implies the presence of CPUID.10H.[ResID=3] as show n in Figure 18-38 which provides the following details. 
•CPUID.(EAX=10H, ECX=ResID= 3):EAX[11:0] reports the maximum MBA throttling value supported, minus 
one. For instance, a value of 89 indicates that a maximu m throttling value of 90 is su pported. Additionally, in 
cases where a linear interface (see below) is supporte d then one hundred minus the maximum throttling value 
indicates the granularity, 10% in this example. 
•CPUID.(EAX=10H, ECX=ResI D=3):EBX is reserved.
•CPUID.(EAX=10H, ECX=ResID= 3):ECX[2] reports whether the response of the delay values is linear (see 
text). 
•CPUID.(EAX=10H, ECX=ResID= 3):EDX[15:0] reports the number of Cla sses of Service (CLOS) supported for 
the feature (minus one). For instance, a reported valu e of 15 implies a maximum of 16 supported MBA CLOS. 
The number of CLOS supported for the MBA feature may or may not align with other resources such as L3 CAT. In 
cases where the Intel RDT features support different nu mbers of CLOS the lowest numerical CLOS support the 
common set of features, while higher CLOS may support a subset. For instance, if L3 CAT supports 8 CLOS while 
MBA supports 4 CLOS, all 8 CLOS would have L3 CAT masks available for cache control, but the upper 4 CLOS would 
not offer MBA support. In this case the upper 4 CLOS woul d not be subject to any throttling control. Software can 
manage supported resources / CLOS in order to either have consistent capabilities across CLOS by using the 
common subset or enable more flexibility by selectively applying resource control where needed based on careful 
CLOS and thread mapping. In all case s, CLOS[0] supports all Intel RDT reso urce control features present on the 
platform.
Discussion on the interpretation and usage of the MBA delay values is provided in Section 18.19.7.2 on MBA config-
uration.Vol. 3B 18-67DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
18.19.7.2  Memory Bandwidth Allocation Configuration
The configuration of MBA takes consists of two processes once enumeration is complete.
•Association of threads to Classes of Service (CLOS) - accomplished in a common fashion across Intel RDT 
features as described in Section 18.19.7.1 via the IA32_P QR_ASSOC MSR. As with features such as L3 CAT, 
software may update the CLOS field of the PQR MSR at context swap time in order to maintain the proper 
association of software threads to Classes of Service on the hardware. While logical processors may each be 
associated with independent CLOS, see Section 18.19.7. 3 for important usage model considerations (initial 
versions of the MBA feature select the maximum delay value across threads). 
•Configuration of the per-CLOS delay values, acco mplished via the IA32_L2_QoS_Ext_BW_Thrtl_n MSR set 
shown in Table 18-20. 
The MBA delay values which may be programmed range from  zero (implying zero delay,  and full bandwidth avail-
able) to the maximum (MBA_MAX) specified in CPUID as di scussed in Section 18.19.7.1. The throttling values are 
approximate and do not sum to 100% across CLOS, rather they should be viewed as a maximum bandwidth “cap” 
per-CLOS.
Software may select an MBA delay value then write th e value into one or more of the IA32_L2_QoS_Ext_B-
W_Thrtl_n MSRs to update the delay values applied for a specific CLOS. As shown in Table 18-20 the base address of the MSRs is at D50H, and the range corresponds to the maximum supported CLOS from CPUID.(EAX=10H, 
ECX=ResID=1):EDX[15:0] as described in Section 18.19.7.1.  For instance, if 16 CLOS are supported then the valid 
MSR range will extend from D50H through D5F inclusive.Figure 18-38.  CPUID.(EAX=10H, ECX=3H) MBA Feature Details Identification11                                       0
EAX31CPUID.(EAX = 10H, ECX = ResID = 3) Output:
Reserved
EBX Reserved
ECX Reserved
EDX ReservedMBA_MAX-1
                                             0 31
31
31         2     1     0
16   15                                                                             0MBA_Lin_Rsp
COS_MAX18-68 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
Table 18-20.  MBA Delay Value MSRs
The definition for the MBA delay value MSRs is provided in  Figure 17.39. The lower 16 bits are used for MBA delay 
values, and values from zero to the maximum from the CP UID MBA_MAX-1 value are supported. Values outside this 
range will generate #GP(0).
If linear input throttling values are indicated by CPUI D.(EAX=10H, ECX=ResID=3):ECX[bit 2] then values from 
zero through the MBA_MAX field from CPUID.(EAX=10H, ECX=ResID=3):EAX[11:0] are supported as inputs. In

Reserved
                                             0 31
31
31         2     1     0
zero through the MBA_MAX field from CPUID.(EAX=10H, ECX=ResID=3):EAX[11:0] are supported as inputs. In 
the linear mode the input precision is defined as 100-(M BA_MAX). For instance, if the MBA_MAX value is 90, the 
input precision is 10%. Values not an even multiple of the precision (e.g., 12%) will be rounded down (e.g., to 10% 
delay applied). 
•If linear values are not supported (CPUID.(EAX=10H, EC X=ResID=3):ECX[bit 2] = 0) then input delay values 
are powers-of-two from zero to the MBA_MAX value from CP UID. In this case any values not a power of two will 
be rounded down the next nearest power of two.
Note that the throttling values provided to software ar e calibrated through specific traffic patterns, however as 
workload characteristics may vary the response precision an d linearity of the delay values will vary across products 
and should be treated as approximate values only.
18.19.7.3  Memory Bandwidth Allocation Usage Considerations
Different versions of Memory Bandwidth Allocation have various usage considerations and improving efficiency 
over time. See the “Intel® Resource Director Technology Architecture Specification” for additional details.
18.20 INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FOR NON-CPU 
AGENTS
This section describes Intel RDT features for non-CPU ag ents. CPU agents are threads running on IA cores. Non-
CPU agents include PCIe and CXL device s and integrated accelerators, thus broadly encompassing the set of agents 
that read from and write to either caches or memory, excluding IA cores. The non- CPU agent Intel RDT features 
enable monitoring of I/O device shared cache and memory bandwidth and cache allocation control. This provides 
features for I/O devices equivalent to the CPU agent In tel RDT capabilities CMT, MBM, and CAT (discussed in Delay Value MSR Address
IA32_L2_QoS_Ext_BW_Thrtl_0 D50HIA32_L2_QoS_Ext_BW_Thrtl_1 D51HIA32_L2_QoS_Ext_BW_Thrtl_2 D52H.... ....
IA32_L2_QoS_Ext_BW_Thrtl_'COS_MAX ' D50H + COS_MAX from CPUID.10H.3
Figure 18-39.  IA32_L2_QoS_ Ext_BW_Thrtl_n MSR Definition16    15                                                                     0 63Base MSR Address = 0xD50
IA32_L2_QOS_Ext_BW_Thrtl_n MSR
Reserved MBA Delay ValueVol. 3B 18-69DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOUR CE DIRECTOR TECHNOLOGY (INTEL® RDT) FEATURES
Section 18.18 and Section 18.19). Refer to the “Intel® Resource Director Technology Architecture Specification” 
regarding design goals, use cases, software architec ture, ACPI enumeration, and MMIO register interfaces.
“Non-CPU agent Intel RDT” refers to capabilities that monitor and control non-CPU agents' resource utilization, 
including PCIe and CXL devices and integrated accelera tors. Non-CPU agent Intel RDT may be called I/O RDT in 
some literature. In this document, the te rm “non-CPU agent Intel RDT” is used.
18.20.1 Non-CPU Agent Intel® RDT Features Enumeration Details
CPU agent Intel RDT features use the CPUID instruction to enumerate supported features and the level of support. 
Architectural Model-Specific Registers (MSRs) are interfaces  to the monitoring and allocation features, as described 
in Sections 18.18 and 18.19.
Non-CPU agent Intel RDT builds on CPU agent Intel RDT by extending CPUID to indicate the presence and integra-
tion of non-CPU agent Intel RDT and by providing rich enum eration information in vendor-specific extensions to the 
Advanced Configuration and Power Interface (ACPI), in partic ular in the I/O RDT (IRDT) table. The ACPI extensions 
detailed in the “Intel® Resource Director Technology Architecture Specification” provide mechanisms to compre-
hend the structure of devices attached behind I/O blocks to particular links and what forms of tagging are 
supported on a per-link basis.
It is recommended that software pars e CPUID and ACPI to obtain a detailed understanding of platform support and 
capabilities before attempting to use non-CPU agent Intel RDT.
18.20.1.1   CPUID-Based Enume ration for Non-CPU Agent Intel® RDT Feature
CPUID-based enumeration provides a me thod by which all architectural Intel RDT features may be enumerated. 
For CPU agent Intel RDT, monitoring details are enumer ated in a CPUID sub-leaf denoted as CPUID.(EAX=0FH, 
ECX=ResID), where ResID corresponds to a resource ID bit index from the CPUID.(EAX=0FH, ECX=0) sub-leaf. 
Similarly, Intel RDT allocation features are described in CPUID.(EAX=10H, ECX=ResID). (Note that the ResID bit 
positions are not guaranteed to be symmetric or have the same encodings.)
No CPUID leaves or sub-leaves are created for non-CPU agent Intel RDT. Rather, non-CPU agent Intel RDT extends 
the existing Intel RDT CPUID sub-leaves with a bit per re source type, indicating whether non-CPU agent Intel RDT 
monitoring or control is present. CPUID.(EAX=0FH, ECX= ResID=1):EAX[bits 9, 10] re presents the presence of 
CMT and MBM features for non-CPU agents. CPUID.(EAX=10H , ECX=ResID=1):ECX[bit 1] represents the presence 
of the CAT feature for non-CPU agents.
Specifically, for non-CPU Agent Intel RDT Monitoring (see Figure 18-21):
•Bits are added in the CPU Agent Intel RDT CMT/MBM leaf: CPUID.(EAX=0FH, ECX= ResID=1):EAX[bits 9, 10].
— EAX[bit 9]: If set, indicates the presence of non-CP U Agent Cache Occupancy Monitoring (the equivalent of 
CPU Agent Intel RDT's CMT feature).
— EAX[bit 10]: If set, indicates the presence of non- CPU Agent memory L3 external BW monitoring (the 
equivalent of CPU Agent Intel RDT's MBM feature).
For non-CPU Agent Intel RDT Allocation (see Figure 18-32): 
•New bit in L3 CAT leaf: CPUID.(E AX=10H, ECX=ResID= 1):ECX[bit 1].
— ECX[bit 1]: If set, indicates the presence of non-CPU Agent Cache Allocation Technology (the equivalent of 
CPU Agent Intel RDT's L3 CAT feature). 
•As before, ECX[bit 2] indicates that L3 CDP is supported if set. 
Note that no equivalent bits are defined in CPUID.(EAX=10H , ECX=ResID=2) as there is no ability for devices to fill 
into core L2 caches. 
If any of these non-CPU agent Intel RDT enumeration bits are set, indicating that a monitoring feature or allocation 
feature is present, it also indicates the presence of th e IA32_L3_IO_RDT_CFG architectural MSR. This MSR may be 
used to enable the non-CPU agent Intel RDT features. See Section 18.20.2 for MSR details.
The presence of Intel RDT is a prerequisite for using the eq uivalent non-CPU agent Intel RDT feature. If a particular 
CPU agent Intel RDT feature is absent, any attempt to us e non-CPU agent Intel RDT equivalents will result in 18-70 Vol. 3BDEBUG, BRANCH PROFILE, TSC, AN D INTEL® RESOURCE DIRECTOR TE CHNOLOGY (INTEL® RDT) FEATURES
general protection faults in the MSR in terface. Attempts to enable unsupport ed features in the I/O complex will 
result in writes to the corresponding MMIO enab le or configuration interfaces being ignored. 
Software may use the existing CPUID leaves to gather the maximum number of RMID and CLOS tags for each 
resource level (e.g., L3 cache), and non-CPU agent Intel RDT is also subject to these limits. 
Some platforms may support a mix of features, for instance , supporting L3 CAT architectural controls and the non-
CPU agent Intel RDT equivalent, but no CMT/MBM monitoring or non-CPU agent monitoring equivalent, and these capabilities should be enumerat ed on a per-platform basis. 
18.20.1.2   ACPI Enumeration
When support for non-CPU agent Intel RDT features is de tected using CPUID, ACPI may be consulted for further 
details on the level of feature support, device structures behind various I/O ports, and the specific MMIO interfaces 
used to control a given device. 
Non-CPU agent Intel RDT enumeration is via the “IRDT” AC PI table. For more information, refer to the “Intel® 
Resource Director Technology Architecture Specification.”
18.20.2 Non-CPU Agent Intel® RDT Feature Enable MSR
Before configuring non-CPU agent Intel RDT through MMIO, the feature should be enabled using the non-CPU agent Intel RDT Feature Enable MSR, IA32_L3_IO_RDT_CFG (MSR address 0C83H). As described in Section 18.20.1.1, the presence of one or more CPUID bits indi cating support for one or more non-CPU agent Intel RDT 
features also indicates the presence of this MSR. This  MSR may be used to enable the non-CPU agent Intel RDT 
features. 
Two bits are defined in this MSR. Bit 0, when set, enab les non-CPU agent RDT resource allocation features. Bit 1, 
when set, enables non-CPU agent Intel RDT monitoring features.
The L3 Non-CPU agent Intel RDT Monitori ng Enable bit is supported if CPUID indicates that one or more non-CPU 
agent Intel RDT resource monitoring features are present. 
The L3 Non-CPU agent Intel RDT Allocati on Enable bit is supported if CPUID indicates that one or more non-CPU 
agent Intel RDT resource allocation features are present. 
The default value is 0x0, so both classes of features ar e disabled by default. All bits not defined are reserved. 
Writing a non-zero value to any reserved bit will generate a General Protection Fault (#GP(0)).
This MSR is scoped at the L3 cache level and is cleared on  system reset. It is expected that the software will

features. 
This MSR is scoped at the L3 cache level and is cleared on  system reset. It is expected that the software will 
configure this MSR consistently across all L3 ca ches that may be present on that package. 
The definition of the IA32_L3_IO_RDT_CFG MSR is shown in Figure 18-40. 
Figure 18-40.  Layout of the IA32_L3_IO_QOS_C FG MSR for Enabling No n-CPU Agent Intel® RDTReserved Reserved  63                                                                                                                                                                                                                                      2     1        0
MA
IRAE = L3 Non-CPU Agent Intel® RDT Allocation EnableIRME = L3 Non-CPU Agent Intel® RDT Monitoring EnableVol. 3B 19-1CHAPTER 19
NOTE
This chapter defines a last-branch recording (LBR) fa cility that is architectural and part of the Intel 
64 architecture. This facility is an enhancement of but distinct from earlier LBR facilities that were 
not architectural. Those earlier facilities are documented in Chapter 18.
Support of the architectural LBR feature in a lo gical processor is reported in CPUID.(EAX=07H, 
ECX=0H):EDX[19]=1. When the architectu ral LBR feature is supported, capability details like the number of LBR 
records that are available is indicated in CPUID.1CH:EA X[7:0]. The number of LBR records available varies across 
processor generations, so software should only access the available LBR records indicated by 
CPUID.1CH:EAX[7:0].
Last Branch Records (LBRs) enable recording of software path history by logging taken branches and other control 
flow transfers within processor registers. Each LBR record or entry is comprised of three MSRs:
•IA32_LBR_x_FROM_IP − Holds the source IP of the operation.
•IA32_LBR_x_TO_IP − Holds the destination IP of the operation.
•IA32_LBR_x_INFO − Holds metadata for the operation, including mispredict, TSX, and elapsed cycle time infor-
mation.
LBR records are stored in age order. The most recent LB R entry is stored in IA32_LBR_0_*, the next youngest in 
IA32_LBR_1_*, and so on. When an operation to be  recorded completes (retires) with LBRs enabled 
(IA32_LBR_CTL.LBREn=1), older LBR entries are shifted in the LBR array by one entry, then a record of the new 
operation is written into entry 0. See Section 19.1.1 for the list of recorded operations.
The number of LBR entries available for recording operatio ns is dictated by the value in IA32_LBR_DEPTH.DEPTH. 
By default, the DEPTH value matches the maximum number of  LBRs supported by the processor, but software may 
opt to use fewer in order to achieve reduced context switch latency. 
In addition to the LBRs, there is a single Last Event Record (LER). It records the last taken branch preceding the 
last exception, hardware interrupt, or software inte rrupt. Like LBRs, the LER is comprised of three MSRs 
(IA32_LER_FROM_IP, IA32_LER_TO_IP, IA32_LER_INFO), and is subject to the same dependencies on enabling 
and filtering.
Which operations are recorded in LBRs depends upon a series of factors:
•Branch Type Filtering − Software must opt in to the types of br anches to be logged; see Section 19.1.2.3.
•Current Privilege Level (CPL) − LBRs can be filtered based on CPL; see Section 19.1.2.5.
•LBR Freeze − LBR and LER recording can be suspended by se tting IA32_PERF_GLOBAL_STATUS.LBR_FRZ to 1. 
See Section 18.4.7 for details on LBR_FRZ.
On some implementations, recording LBRs may require cons training the number of operations that can complete in 
a cycle. As a result, on these implementations, enabling LBRs may have some performance overhead.
19.1 BEHAVIOR
19.1.1 Logged Operations
LBRs can log most control flow transfer operations.
The source IP recorded for a branch instruction is the IP of that instruction. For events that take place between 
instructions, the source IP recorded is the IP of the next sequential instruction.
The destination IP recorded is always the target of the branch or event, the next instruction that will execute.
The full list of operations and the respective IPs recorded is shown in Table 19-1.19-2 Vol. 3BLAST BRANCH RECORDS
19.1.2 Configuration
19.1.2.1  Enabling and Disabling
LBRs are enabled by setting IA32_LBR_CTL.LBREn to 1.
Some operations, such as entry to a secure mode like  SMM or Intel SGX, can cause LBRs to be temporarily 
disabled. Other operations, such as debug exceptions or some SMX operations, disable LBRs and require software 
to re-enable them. Details on these interactions can be found in Section 19.1.4.
19.1.2.2  LBR Depth
The number of LBRs used by the processor can be co nstrained by modifying the IA32_LBR_DEPTH.DEPTH value. 
DEPTH defaults to the maximum number of LBRs supported by the processor.  Allowed DEPTH values can be found 
in CPUID.1CH:EAX[7:0].
Reducing the LBR depth can result in improved performance, by reducing the number of LBRs that need to be read 
and/or context switched.
On a software write to IA32_LBR_DEPTH, all LBR entries are reset to 0. LERs are not impacted.
A RDMSR or WRMSR to any IA32_LBR_x_* MSRs, such that x ≥ DEPTH, will generate a #GP exception. Note that 
the XSAVES and XRSTORS instructions access only the LBRs associated with entries 0 to DEPTH-1.
By clearing the LBR entries on writes to IA32_LBR_DEPTH, and forbidding any software writes to LBRs ≥ DEPTH, it 
is thereby guaranteed that any LBR entries equal to or above DEPTH will have value 0.
19.1.2.3  Branch Type Enabling and Filtering
Software must opt in to the types of branches that ar e desired to be recorded. These elections are made in 
IA32_LBR_CTL; see Section 19.2. Branch type options are lis ted in Table 19-2; only those enabled will be recorded.Table 19-1.  LBR IP Values  for Various Operations 
Operation FROM_IP TO_IP
Taken Branch1, Exception, INT3, INTn, 
INTO, TSX AbortCurrent IP Target IP
Interrupt Next IP Target IP
INIT (BSP) Next IP Reset Vector
INIT (AP) + SIPI Next IP SIPI Vector
EENTER/ERESUME + EEXIT/AEX Current IP Target or Trampoline IPRSM
2Target IP Target IP
#DB, #SMI, VM exit, VM entry None None
NOTES:
1. Direct CALLs with displacement zero, for which the targ et is typically the next sequential IP, are not treated as
taken branches by LBRs.
2. RSM is only recorded in LBRs when IA 32_DEBUGCTL.FREEZE_WHILE_SMM is set to 0.Vol. 3B 19-3LAST BRANCH RECORDS
These encodings match those in IA32_LBR_x_INFO.BR_TYPE.
Control flow transfers that are not recorded include #DB, VM exit, VM entry, and #SMI.
19.1.2.4  Call-Stack Mode
The LBR array is, by default, treated as a ring buffer that  captures control flow transitions. However, the finite 
depth of the LBR array can be limiting when profiling certai n high-level languages (e.g., C++), where a transition 
of the execution flow is accompanied by a large number of le af function calls. These calls to leaf functions, and their 
returns, are likely to displace the main execution context from the LBRs.
When call-stack mode is enabled, the LBR array can capture unfiltered call data normally, but as return instructions 
are executed the last captured branch (call) record is flushed from the LBRs in a last-in first-out (LIFO) manner. Thus, branch information pertaining to completed leaf func tions will not be retained, while preserving the call stack 
information of the main line execution path.
Call-stack mode is enabled by setting IA32_LBR_CTL.CALL _STACK to 1. When enabled, near RET instructions 
receive special treatment. Rather than adding a new record  in LBR_0, a near RET will instead “pop” the CALL entry 
at LBR_0 by shifting entries LBR_1..LBR_[DEPTH-1] up to LBR_0..LBR_[DEPTH-2], and clearing LBR_[DEPTH-1] to 
0. Thus, LBR processing software can consume only valid call-stack entries by reading until finding an entry that is 
all zeros.
Call-stack mode should be used with branch type enabli ng configured to capture only CALLs (NEAR_REL_CALL and 
NEAR_IND_CALL) and RETs (NEAR_RET). When configured in this manner, the LBR array emulates a call stack, 
where CALLs are “pushed” and RETs “p op” them off the stack. If other branch types (JCC, NEAR_*_JMP, or 
OTHER_BRANCH) are enabled for recording with ca ll-stack mode, LBR behavior may be undefined.
It is recommended that call-stack mode be used along with CPL filtering, by setting at most one of the OS and USR 
bits in the IA32_LBR_CTL MSR. Call-stack mode does not emulate the stack switch that can occur on CPL transi-
tions, and hence monitoring all CPLs ma y result in a corrupted LBR call stack.
Call-Stack Mode and LBR Freeze
When IA32_DEBUGCTL.FREEZE_LBRS_ON_ PMI=1, IA32_PERF_GLOBAL_STATUS.LBR _FRZ will be set to 1 when a 
PMI is pended. That will cause LBRs and LERs to cease re cording branches until LBR_FRZ is cleared. Because there 
may be some “skid”, or instructions retiring, in between the PMI being pended and the PMI being taken, it is 
possible that some branches may be missing from the LBRs. In the case of call-stack mode, if a CALL or RET is 
missed, that can lead to confusing results where CALL entrie s fail to get “popped” off the stack, and RETs “pop” the 
wrong CALLs.

An alternative is to utilize CPL filtering to limit LBR reco rding to less privileged modes only (CPL>3) instead of using 
the FREEZE_LBRS_ON_PMI=1 feature. This will record branch es in the “skid”, but avoid recording any branches in 
the privilege level 0 handler.Table 19-2.  Branch Type Filtering Details 
Branch Type Operations Recorded
COND Jcc, J*CXZ, and LOOP*NEAR_IND_JMP JMP r/m*
NEAR_REL_JMP JMP rel*
NEAR_IND_CALL CALL r/m*NEAR_REL_CALL CALL rel* (excluding CALLs to th e next sequential IP)
NEAR_RET RET (0C3H)
OTHER_BRANCH JMP/CALL ptr*, JMP/CALL m*, RET (0C8H) , SYS*, interrupts, exceptions (other than debug 
exceptions), IRET, INT3, INTn, IN TO, TSX Abort, EENTER, ERESUME,  EEXIT, AEX, INIT, SIPI, RSM19-4 Vol. 3BLAST BRANCH RECORDS
19.1.2.5  CPL Filtering
Software must opt in to which CPL(s) will have branch es recorded. If IA32_LBR_CTL.OS=1, then branches in 
CPL=0 can be recorded. If IA32_LBR_CTL.USR=1, then bran ches in CPL>0 can be recorded. For operations which 
change the CPL, the operation is recorded in LBRs only if the CPL at the end of the operation is enabled for LBR 
recording. In cases where the CPL transitions from a value that is filtered out to a value that is enabled for LBR 
recording, the FROM_IP address for the recorded CPL transition branch or event will be 0FFFFFFFFFFFFFFFFH.
19.1.3 Record Data
19.1.3.1  IP Fields
The source and destination IP values in IA32_LBR_x _[FROM|TO]_IP and IA32_LER_x_[FROM|TO]_IP may hold 
effective IPs or linear IPs (LIPs), depending on the processo r generation. The effective IP is the offset from the CS 
base address, while LIP includes the CS base address. Whic h IP type is used is indicated in CPUID.1CH:EAX[bit 31].
The value read from this field will always be canonical. No te that this includes the case where a canonical violation 
(#GP) results from executing sequential code that runs precisely to the end of the lower canonical address space 
(where IP[63:MAXLINADDR-1] is  0, but IP[MAXLINADDR-2:0] is all ones).  In this case, the FROM_IP will hold the 
lowest canonical address in the upper canonical space, su ch that IP[63:MAXLINADDR-1] is all ones, and IP[MAXLI-
NADDR-2:0] is 0.
In some cases, due to CPL filtering, the FROM_IP of the recorded operation may be filtered out. In this case 
0FFFFFFFFFFFFFFFFH will be recorded. See Section 19.1.2.5 for details.
Writes of these fields will be forced canonical, such that the processor ignores the value written to the upper bits 
(IP[63:MAXLINADDR-1]).
19.1.3.2  Branch Types
The IA32_LBR_x_INFO.BR_TYPE and IA32_LER_INFO.BR_TYPE fields encode the branch types as shown in Table 
19-3.
For a list of branch operations that fall into the categori es above, see Table 19-2. In future generations, BR_TYPE 
bits 2:0 may be used to distinguish between differing types of OTHER_BRANCH.
19.1.3.3  Cycle Time
Each time an operation is recorded in an LBR, the value of the LBR cycle timer is recorded in 
IA32_LBR_x_INFO.CYC_CNT. The LBR cycle timer is a saturating counter that counts at the processor clock rate. 
Each time an operation is recorded in an LBR, the counter is reset but continues counting.Table 19-3.  IA32_LBR_x_INFO and IA 32_LER_INFO Branch  Type Encodings
Encoding Branch Type
0000B COND
0001B NEAR_IND_JMP
0010B NEAR_REL_JMP0011B NEAR_IND_CALL
0100B NEAR_REL_CALL
0101B NEAR_RET011xB Reserved
1xxxB OTHER_BRANCHVol. 3B 19-5LAST BRANCH RECORDS
There is an LBR cycle counter valid bit, IA32_LBR_x_I NFO.CYC_CNT_VALID. When set, the CYC_CNT field holds a 
valid value, the number of elapsed cycles since the last operation recorded in an LBR (up to 0FFFFH).
Some implementations may opt to reduce the granularity of  the CYC_CNT field for larger values. The implication of 
this is that the least significant bits may be forced to 1 in cases where the count has reached some minimum 
threshold. It is guaranteed that this reduced granularit y will never result in an inaccuracy of more than 10%.
19.1.3.4  Mispredict Information
IA32_LBR_x_INFO.MISPRED provides an indication of whet her the recorded branch was predicted incorrectly by 
the processor. The bit is set if either the taken/not-taken direction of a conditional branch was mispredicted, or if 
the target of an indirect branch was mispredicted.
19.1.3.5  Intel® TSX Information
IA32_LBR_x_INFO.IN_TSX indicates whether the operat ion recorded retired during a TSX transaction. 
IA32_LBR_x_INFO.TSX_ABORT indicates that the operation is a TSX Abort.
19.1.4 Interaction with Other Processor Features
19.1.4.1  SMM
IA32_LBR_CTL.LBREn is saved and cleared on #SMI, and rest ored on RSM. As a result of disabling LBRs, the #SMI 
is not recorded. RSM is recorded only  if IA32_DEBUGCTL.FREEZE_WHILE_SMM is set to 0, and the FROM_IP will be 
set to the same value as the TO_IP.
19.1.4.2  SMM Transfer Monitor (STM)
LBREn is not cleared on #SMI when it causes SMM VM exit. Instead, the STM should use the VMCS controls 
described in Section 19.1.4.3 to disable LBRs while in SMM, and to restore them on  VM entries that exit SMM.
On VMCALL to configure STM, IA32_LBR_CTL is cleared.
19.1.4.3  VMX
By default, LBR operation persists across VMX transition s. However, VMCS fields have been added to enable 
constraining LBR usage to within non-root operation only. See details in Table 19-4.
To enable “guest-only” LBR use, a VMM should set bo th the “Load Guest IA32_LBR_CTL” entry control and the 
“Clear IA32_LBR_CTL” exit control. For “system-wide” LBR use, where LBRs remain enabled across host and 
guest(s), a VMM should keep both new VMCS controls clear.
VM entry checks that, if the “Load Gu est IA32_LBR_CTL” entry control is 1, bits reserved in the IA32_LBR_CTL MSR 
must be 0 in the field for that register.Table 19-4.  LBR VMCS Fields
Name Type Bit Position Behavior
Guest IA32_LBR_CTL Guest State Field NA The guest value of IA32_LBR_CTL is writte n to this field on all 
VM exits.
Load Guest IA32_LBR_CTL Entry Control 21 When set, VM entry will write the value from the “Guest 
IA32_LBR_CTL” guest stat e field to IA32_LBR_CTL.
Clear IA32_LBR_CTL Exit Control 26 When set, VM ex it will clear IA32_LBR_C TL after the value has 
been saved to the “Guest IA32_LBR_CTL” guest state field.19-6 Vol. 3BLAST BRANCH RECORDS
For additional information relating to VMX transitions,  see Chapter 25, Chapter 27, and Chapter 28 in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 3C.
19.1.4.4  Intel® SGX
On entry to an enclave, via EENTER or ERESUME, logging of LBR entries is suspended. On enclave exit, via EEXIT 
or AEX, logging resumes. The cycle counter w ill continue to run during enclave execution.
An exception to the above is made for opt-in debug enclaves. For such enclaves, LBR logging is not impacted.
19.1.4.5  Debug Exceptions
When a branch happens because of a #DB exception, IA32_L BR_CTL.LBREn is cleared. As a result, the operation is 
not recorded.
19.1.4.6  SMX
On GETSEC leaves SENTER or ENTERACCS, IA32_LBR_CTL is cleared. As a result, the operation is not recorded.
19.1.4.7  MWAIT
On an MWAIT that requests a C-state deeper than C1 , IA32_LBR_x_* MSRs may be cleared to 0. IA32_LBR_CTL, 
IA32_LBR_DEPTH, and IA32_LER_* MSRs will be preserved.
For an MWAIT that enters a C-state equal to or less deep than C1, and all C-states that enter as a result of Hard-
ware Duty Cycling (HDC), all LBR MSRs are preserved.
19.1.4.8  Processor Even t-Based Sampling (PEBS)
PEBS records can be configured to include LBRs, by se tting PEBS_DATA_CFG.LBREn[3] =1. The number of LBRs to 
include in the record is also configurable, via PEBS_D ATA_CFG.NUM_LBRS[28:24]. For details on PEBS, see Section 
20.9 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
If NUM_LBRS is set to a value greater than LBR_DEPTH, then only  LBR_DEPTH entries will be  written into the PEBS 
record. Further, the Record Size field will be decreased to ma tch the actual size of the record to be written, and the 
Record Format field will replace the value of NUM_LBRS with the value of LBR_DEPTH. These adjustments ensure 
that software is able to prop erly interpret the PEBS record.
19.2 MSRS
The MSRs that represent the LBR entries (I A32_LBR_x_[TO|FROM|INFO]) and the LER entry 
(IA32_LER_[TO|FROM|INFO]) do not fault on writes. Any address field written will force sign-extension based on the maximum linear address width supported by the processo r, and any non-zero value written to undefined bits 
may be ignored such that subsequent reads return 0.
On a warm reset, all LBR MSRs, including IA32_LBR_DEPTH, have their values preserved. However, 
IA32_LBR_CTL.LBREn is cleared to 0, disabling LBRs. If a warm reset is triggered while the processor is in the C6 
idle state, also known as warm init, all LBR MSRs will be reset to their initial values.
See Table 2-2 in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, for details on LBR 
MSRs.
19.3 FAST LBR READ ACCESS

19.2 MSRS
MSRs.
XSAVES provides a faster means than RDMSR for software to read all LBRs. When using XSAVES for reading LBRs 
rather than for context switch, software should take care to  ensure that XSAVES does not write LBR state to an area 
of memory that has been or will be used by  XRSTORS. This could corrupt INIT tracking.Vol. 3B 19-7LAST BRANCH RECORDS
19.4 OTHER IMPACTS
19.4.1 Branch Trace Store on Intel Atom® Processors
Branch Trace Store (BTS) on Intel Atom processors that  support the architectural form of the LBR feature has 
dependencies on the LBR configuration. BTS will store ou t the LBR_0 (TOS) record each time a taken branch or 
event retires. If any filtering of LBRs is employed, or if LBRs are disabled, some duplicate entries may be stored by 
BTS. Like LBRs and LERs, BTS is suspended when IA32_PERF_GLOBAL_STATUS.LBR_FRZ is set to 1.
BTS will change to cease issuing branch records for direct near CALLs with displacement zero to align with LBR 
behavior.
19.4.2 IA32_DEBUGCTL
On processors that do not support model-specific LBRs, IA32_DEBUGCTL[bit 0] has no meaning. It can be written 
to 0 or 1, but reads will always return 0.
19.4.3 IA32_PERF_CAPABILITIES
On processors that do not support model-specific LBRs , IA32_PERF_CAPABILITIES.LBR_FMT will have the value 
03FH.19-8 Vol. 3BLAST BRANCH RECORDSVol. 3B 20-1CHAPTER 20
Intel 64 and IA-32 architectures provide facilities for monitoring performance via a PMU (Performance Monitoring 
Unit).
NOTE
Performance monitoring events can be found here: https://perfmon-events.intel.com/ .
Additionally, performance monitoring event files fo r Intel processors are ho sted by the Intel Open 
Source Technology Center. These files can be downloaded here: 
https://download.01.org/perfmon/ . 
20.1 PERFORMANCE MONITORING OVERVIEW
Performance monitoring was introduced in the Pentium pr ocessor with a set of model-specific performance-moni-
toring counter MSRs. These counters permit selection of processor performance parameters to be monitored and 
measured. The information obtained from these counters can be used for tuning system and compiler perfor-
mance. 
In Intel P6 family of processors, the performance monito ring mechanism was enhanced to permit a wider selection 
of events to be monitored and to allo w greater control events to be monito red. Next, Intel processors based on 
Intel NetBurst microarchitecture introduced a distribute d style of performance monitoring mechanism and perfor-
mance events.
The performance monitoring mechanisms  and performance events defined for the Pentium, P6 family, and Intel 
processors based on Intel NetBurst microarchitecture ar e not architectural. They ar e all model specific (not 
compatible among processor families). Intel Core Solo and Intel Core Duo processors support a set of architectural 
performance events and a set of non-architectural perfor mance events. Newer Intel processor generations support 
enhanced architectural performance events and non-architectural performance events.
Starting with Intel Core Solo and Intel Core Duo processo rs, there are two classes of performance monitoring capa-
bilities. The first class supports events for monitoring  performance using counting or interrupt-based event 
sampling usage. These events are non-architectural and vary from one processor model to another. They are 
similar to those available in Pentium M processors. Thes e non-architectural performance monitoring events are 
specific to the microarchitecture and may change with  enhancements. They are discussed in Section 20.6.3, 
“Performance Monitoring (Processors Based on Intel NetBur st® Microarchitecture).” Non-architectural events for a 
given microarchitecture cannot be enumerated using CPUID; and they can be found at: https://perfmon-events.intel.com/
.
The second class of performance monitoring capabilities is  referred to as architectural performance monitoring. 
This class supports the same counting and Interrupt-based  event sampling usages, with a smaller set of available 
events. The visible behavior of architectural performance events is consistent across processor implementations. 
Availability of architectural performance monitoring capab ilities is enumerated using the CPUID.0AH. These events 
are discussed in Section 20.2.
See also:
— Section 20.2, “Architectural Performance Monitoring.”
— Section 20.3, “Performance Monitoring (Intel® Core™ Processors and Intel® Xeon® Processors).”
•Section 20.3.1, “Performance Monitoring for Pr ocessors Based on Nehalem Microarchitecture.”
•Section 20.3.2, “Performance Monitoring for Proc essors Based on Westmere Microarchitecture.”
•Section 20.3.3, “Intel® Xeon® Processor E7 Family Performance Monitoring Facility.”
•Section 20.3.4, “Performance Monitoring for Processors Based on Sandy Bridge Microarchitecture.”
•Section 20.3.5, “3rd Generation Intel® Core ™ Processor Performance Monitoring Facility.”20-2 Vol. 3BPERFORMANCE MONITORING
•Section 20.3.6, “4th Generation Intel® Core™ Processor Performance Monitoring Facility.”
•Section 20.3.7, “5th Generation Intel® Core™ Processor and Intel® Core™ M Processor Performance 
Monitoring Facility.”
•Section 20.3.8, “6th Generation, 7th Generation  and 8th Generation Intel® Core™ Processor 
Performance Monitoring Facility.”
•Section 20.3.9, “10th Generation Intel® Core ™ Processor Performance Monitoring Facility.”
•Section 20.3.10, “12th and 13th Generation Intel®  Core™ Processors, and 4th Generation Intel® 
Xeon® Scalable Processor Family Performance Monitoring Facility.”
— Section 20.4, “Performance monitoring (Intel® Xeon™ Phi Processors).”
•Section 20.4.1, “Intel® Xeon Phi™ Processor 7200/5200/3200 Performance Monitoring.”
— Section 20.5, “Performance Monitoring (Intel Atom® Processors).”
•Section 20.5.1, “Performance Monitoring (45 nm and 32 nm Intel Atom® Processors).”
•Section 20.5.2, “Performance Monitoring  for Silvermont Microarchitecture.”
•Section 20.5.3, “Performance Monitori ng for Goldmont Microarchitecture.”
•Section 20.5.4, “Performance Monitoring for Goldmont Plus Microarchitecture.”
•Section 20.5.5, “Performance Monitori ng for Tremont Microarchitecture.”
— Section 20.6, “Performance Monitoring (Legacy Intel Processors).”
•Section 20.6.1, “Performance Monitoring (Intel® Core™ Solo and Intel® Core™ Duo Processors).”
•Section 20.6.2, “Performance Monitoring (Processors Based on Intel® Core™ Microarchitecture).”
•Section 20.6.3, “Performance Monitoring (Processors Based on Intel NetBurst® Microarchitecture).”
•Section 20.6.4, “Performance Monitoring and Intel®  Hyper-Threading Technology in Processors Based 
on Intel NetBurst® Microarchitecture.”
•Section 20.6.4.5, “Counting Clocks on systems with Intel® Hyper-Threading Technology in 
•Section 20.6.5, “Performance Monitoring and Dual-Core Technology.”
•Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3 
Cache.”
•Section 20.6.7, “Performance Monitoring on L3 and Caching Bus Controller Sub-Systems.”
•Section 20.6.8, “Performance Monitoring (P6 Family Processor).”
•Section 20.6.9, “Performance Monitoring (Pentium Processors).”
— Section 20.7, “Counting Clocks.”— Section 20.8, “IA32_PERF_CAPABILITIES MSR Enumeration.”
— Section 20.9, “PEBS Facility.”
20.2 ARCHITECTURAL PE RFORMANCE MONITORING
Performance monitoring events are architectural when th ey behave consistently across microarchitectures. Intel 
Core Solo and Intel Core Duo processors introduced arch itectural performance monitoring. The feature provides a 
mechanism for software to enumerate performance events  and provides configuration and counting facilities for 
events.
Architectural performance monitoring does allow fo r enhancement across processor implementations. The 
CPUID.0AH leaf provides version ID for each enhancement.  Intel Core Solo and Intel Core Duo processors support 
base level functionality identified by version ID of 1. Pr ocessors based on Intel Core microarchitecture support, at 
a minimum, the base level functionality of architectura l performance monitoring. Intel Core 2 Duo processor T Vol. 3B 20-3PERFORMANCE MONITORING
7700 and newer processors based on Intel Core microarchitecture support both the base level functionality and 
enhanced architectural performance monitoring identified by version ID of 2.
45 nm and 32 nm Intel Atom processors and Intel Atom processors based on the Silvermont microarchitecture 
support the functionality provid ed by versionID 1, 2, and 3; CPUID.0AH:EAX[7:0] reports versionID = 3 to indicate 
the aggregate of architectural performance monitoring ca pabilities. Intel Atom processors based on the Airmont 
microarchitecture support the same performance monitoring capabilities as those based on the Silvermont

microarchitecture support the same performance monitoring capabilities as those based on the Silvermont 
microarchitecture. Intel Atom processors based on the Goldmont and Goldmont Plus microarchitectures support versionID 4. Intel Atom processors starting with processors based on the Tremont microarchitecture support 
versionID 5.
Intel Core processors and related Intel Xeon processor families based on the Nehalem through Broadwell microar-
chitectures support version ID 3. Intel processors based on the Skylake through Coffee Lake microarchitectures 
support versionID 4. Intel processors starting with proc essors based on the Ice Lake microarchitecture support 
20.2.1 Architectural Performance Monitoring Version 1
Configuring an architectural performance monitoring even t involves programming performance event select regis-
ters. There are a finite number of performance event select MSRs (IA32_PERFEVTSELx MSRs). The result of a performance monitoring event is reported in a perfor mance monitoring counter (IA32_PMCx MSR). Performance 
monitoring counters are paired with performance monitoring select registers.
Performance monitoring select registers and counters are architectural in the following respects:
•The bit field layout of IA32_PERFEVTSELx is consistent across microarchitectures. A non-zero write of a field 
that is introduced after the initial implementation of ar chitectural performance monitoring (Version 1) results in 
#GP if that field is not supported.
•Addresses of IA32_PERFEVTSELx MSRs remain the same across microarchitectures.
•Addresses of IA32_PMC MSRs remain the same across microarchitectures.
•Each logical processor has its own set of IA32_PERFEVT SELx and IA32_PMCx MSRs. Configuration facilities and 
counters are not shared between logical processors sharing a processor core.
Architectural performance monitoring provides a CPUI D mechanism for enumerating the following information:
•Number of performance monitoring counters available to software in a logical processor (each 
IA32_PERFEVTSELx MSR is paired to the corresponding IA32_PMCx MSR).
•Number of bits supported in each IA32_PMCx.
•Number of architectural performance monitori ng events supported in a logical processor.
Software can use CPUID to discover architectural performa nce monitoring availability (CPUID.0AH). The architec-
tural performance monitoring leaf provides an identifi er corresponding to the version number of architectural 
performance monitoring available in the processor.
The version identifier is retrieved by querying CPUID.0AH:EAX[bits 7:0] (see Chapter 3, “Instruction Set Refer-
ence, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). If the version iden-
tifier is greater than zero, architectural performance mo nitoring capability is supported. Software queries the 
CPUID.0AH for the version identifier first; it then anal yzes the value returned in CPUID.0AH.EAX, CPUID.0AH.EBX 
to determine the facilities available.
In the initial implementation of architectural perf ormance monitoring; software can determine how many 
IA32_PERFEVTSELx/ IA32_PMCx MSR pairs are supported per core, the bit-width of PMC, and the number of archi-
tectural performance monitoring events available.
20.2.1.1  Architectural Performance Monitoring Version 1 Facilities
Architectural performance monitoring facilities include a set of performance monitoring counters and performance 
event select registers. These MSRs have the following properties:
•IA32_PMCx MSRs start at address 0C1H and occupy a cont iguous block of MSR address space; the number of 
MSRs per logical processor is reported using CPUID.0AH: EAX[15:8]. Note that this may vary from the number 20-4 Vol. 3BPERFORMANCE MONITORING
of physical counters present on the hardware, because an agent running at a higher privilege level (e.g., a 
VMM) may not expose all counters.
•IA32_PERFEVTSELx MSRs start at addr ess 186H and occupy a contiguous bl ock of MSR address space. Each 
performance event select register is paired with a corresponding performance counter in the 0C1H address 
block. Note the number of IA32_PERFEVTSELx MSRs may vary from the number of physical counters present 
on the hardware, because an agent running at a higher  privilege level (e.g., a VMM) may not expose all 
counters.
•The bit width of an IA32_PMCx MSR is reported using th e CPUID.0AH:EAX[23:16]. This the number of valid bits 
for read operation. On write operations, the lower-order 32 bits of the MSR may be written with any value, and 
the high-order bits are sign-extended from the value of bit 31. 
•Bit field layout of IA32_PERFEVTSELx MSRs is defined architecturally.
See Figure 20-1 for the bit field layout of IA32_PERFEVTSELx MSRs. The bit fields are:
•Event select field (bits 0 through 7) — Selects the event logic unit used to detect microarchitectural 
conditions (see Table 20-1, for a list of architectural events  and their 8-bit codes). The set of values for this field 
is defined architecturally; each value corresponds to  an event logic unit for use with an architectural 
performance event. The number of architectural events  is queried using CPUID.0AH:EAX. A processor may 
support only a subset of pre-defined values.
•Unit mask (UMASK) field (bits 8 through 15) — These bits qualify the condition that the selected event 
logic unit detects. Valid UMASK values for each event logic unit are specific to the unit. For each architectural 
performance event, its corresponding UMASK value de fines a specific microarchitectural condition. 
A pre-defined microarchitectural condition associated wi th an architectural event may not be applicable to a 
given processor. The processor then reports only a su bset of pre-defined architectural events. Pre-defined 
architectural events are listed in Table 20-1; support fo r pre-defined architectural events is enumerated using 
CPUID.0AH:EBX. 
•USR (user mode) flag (bit 16) — Specifies that the selected microarchitectural condition is counted when 
the logical processor is operating at privilege levels 1,  2 or 3. This flag can be used with the OS flag.
•OS (operating system mode) flag (bit 17) — Specifies that the selected microarchitectural condition is 
counted when the logical processor is operating at privil ege level 0. This flag can be used with the USR flag.
•E (edge detect) flag (bit 18) — Enables (when set) edge detection of  the selected microarchitectural 
condition. The logical processor counts the number of dea sserted to asserted transitions for any condition that 
can be expressed by the other fields. The mechanism does  not permit back-to-back assertions to be distin-
guished. 
This mechanism allows software to measure not only the frac tion of time spent in a particular state, but also the 
average length of time spent in such a state (for ex ample, the time spent waiting for an interrupt to be 
serviced).
•PC (pin control) flag (bit 19) — Beginning with Sandy Bridge microarchi tecture, this bit is reserved (not 
writeable). On processors based on previous microarchitectures, the logical processor toggles the PM i pins and Figure 20-1.  Layout of IA32_PERFEVTSELx MSRs31
INV—Invert counter mask
EN—Enable counters
INT—APIC interrupt enable
PC—Pin control87 0
Event Select
E—Edge detect
OS—Operating system modeUSR—User ModeCounter Mask EE
NI
N
T19 1618 1517 2021222324
ReservedI
N
VP
CU
S
RO
SUnit Mask (UMASK)(CMASK)63Vol. 3B 20-5PERFORMANCE MONITORING
increments the counter when performance-monitoring ev ents occur; when clear, the processor toggles the PM i 
pins when the counter overflows. The toggling of a pin is defined as assertion of the pin for a single bus clock followed by deassertion.
•INT (APIC interrupt enable) flag (bit 20) — When set, the logical processor generates an exception 
through its local APIC on counter overflow.
•EN (Enable Counters) Flag (bit 22) — When set, performance counting is enabled in the corresponding 
performance-monitoring counter; when clear, the corresp onding counter is disabled. The event logic unit for a 
UMASK must be disabled by setting IA32_PERFE VTSELx[bit 22] = 0, before writing to IA32_PMCx.
•INV (invert) flag (bit 23) — When set, inverts the counter-mask (CMASK) comparison, so that both greater 
than or equal to and less than comparisons can be made  (0: greater than or equal; 1: less than). Note if 
counter-mask is programmed to zero, INV flag is ignored.
•Counter mask (CMASK) field (bits 24 through 31) — When this field is not zero, a logical processor 
compares this mask to the events count of the detected microarchitectural condition during a single cycle. If 
the event count is greater than or equal to this mask, the counter is incremented by one. Otherwise the counter 
is not incremented. 
This mask is intended for software to characterize microarchitectural conditions that can count multiple 
occurrences per cycle (for example, two or more instruct ions retired per clock; or bus queue occupations). If 
the counter-mask field is 0, then the counter is incr emented each cycle by the event count associated with 
multiple occurrences.

20.2.1.2  Pre-defined Architectural Performance Events
Table 20-1 lists architecturally defined events.
A processor that supports architectural performance moni toring may not support all the predefined architectural 
performance events (Table 20-1). The number of architectu ral events is reported through CPUID.0AH:EAX[31:24], 
while non-zero bits in CPUID.0AH:EBX indicate any architectural events that are not available. 
The behavior of each architectural performance event is ex pected to be consistent on all processors that support 
that event. Minor variations between microarchitectures are noted below:
•UnHalted Core Cycles  — Event select 3CH, Umask 00H 
This event counts core clock cycles when the clock signal on a specific core is running (not halted). The counter 
does not advance in the following conditions: 
— An ACPI C-state other than C0 for normal operation.
—H L T .— STPCLK# pin asserted.Table 20-1.  UMask and Event Select Encodings for Pre-Defined Architectural Performance Events
Bit Position 
CPUID.AH.EBXEvent Name UMask Event Select
0 UnHalted Core Cycles 00H 3CH
1 Instruction Retired 00H C0H
2 UnHalted Reference Cycles1
NOTES:
1. Implementations prior to  the 12th generation Intel® Core™ processor P-cores count at core cr ystal clock, TSC, or bus clock f requency.01H 3CH
3 LLC Reference 4FH 2EH
4 LLC Misses 41H 2EH
5 Branch Instruction Retired 00H C4H6 Branch Misses Retired 00H C5H
7 Topdown Slots 01H A4H20-6 Vol. 3BPERFORMANCE MONITORING
— Being throttled by TM1.
— During the frequency switching phase of a performa nce state transition (see Chapter 15, “Power and 
Thermal Management”).
The performance counter for this event counts across performance state transitions using different core clock 
frequencies.
•Instructions Retired  — Event select C0H, Umask 00H 
This event counts the number of instructions at retirement. For instructions that consist of multiple micro-ops, 
this event counts the retirement of the last micro-op of the instruction. An instruction with a REP prefix counts 
as one instruction (not per iteration). Faults before the re tirement of the last micro-op of a multi-ops instruction 
are not counted.
This event does not increment under VM-exit condit ions. Counters continue counting during hardware 
interrupts, traps, and in side interrupt handlers. 
•UnHalted Reference Cycles — Event select 3CH, Umask 01H 
This event counts reference clock cycles at a fixed frequency while the clock signal on the core is running. The 
event counts at a fixed frequency, irrespective of core frequency changes due to performance state transitions. 
Processors may implement this behavior differently. Curre nt implementations use the core crystal clock, TSC or 
the bus clock. Because the rate may differ between impl ementations, software should calibrate it to a time 
source with known frequency.
•Last Level Cache References  — Event select 2EH, Umask 4FH 
This event counts requests originating from the core that  reference a cache line in the last level on-die cache. 
The event count includes speculation and cache line fills due to the first-level cache hardware prefetcher, but 
may exclude cache line fills due to other hardware-prefetchers. 
Because cache hierarchy, cache sizes and other implementation-specific characteristics; value comparison to 
estimate performance differences is not recommended. 
•Last Level Cache Misses  — Event select 2EH, Umask 41H
This event counts each cache miss condition for references to the last level on-die cache. The event count may 
include speculation and cache line fills due to the firs t-level cache hardware prefetcher, but may exclude cache 
line fills due to other hardware-prefetchers. 
•Branch Instructions Retired — Event select C4H, Umask 00H
This event counts branch instructions at retirement. It counts the retirement of the last micro-op of a branch 
•All Branch Mispredict Retired  — Event select C5H, Umask 00H
This event counts mispredicted branch instructions at retirement. It counts the retirement of the last micro-op 
of a branch instruction in the architectural path of execution and experienced misprediction in the branch 
prediction hardware. 
Branch prediction hardware is implementation-specific across microarchitectures; value comparison to 
•Topdown Slots — Event select A4H, Umask 01H
This event counts the total number of available slots for an unhalted logical processor.The event increments by ma chine-width of the narrowest pipeline as  employed by the Top-down Microarchi-
tecture Analysis method. The count is distributed am ong unhalted logical processors (hyper-threads) who 
share the same physical core, in processors that support Intel Hyper-Threading Technology.
Software can use this event as the denominator for th e top-level metrics of the Top-down Microarchitecture 
Analysis method.
NOTE
Programming decisions or software precisians on functionality should not be based on the event 
values or dependent on the existenc e of performance monitoring events.Vol. 3B 20-7PERFORMANCE MONITORING
20.2.2 Architectural Performance Monitoring Version 2
The enhanced features provided by architectural pe rformance monitoring version 2 include the following:
•Fixed-function performance counter re gister and associated control register  — Three of the architec-
tural performance events are counted using three fi xed-function MSRs (IA32_FIXED_CTR0 through IA32_-
FIXED_CTR2). Each of the fixed-function PMC can count only one architectural performance event. 
Configuring the fixed-function PMCs is done by writing to bit fields in the MSR (IA32_FIXED_CTR_CTRL) located 
at address 38DH. Unlike configuring performance even ts for general-purpose PMCs (IA32_PMCx) via UMASK 
field in (IA32_PERFEVTSELx), configuring, programmin g IA32_FIXED_CTR_CTRL for fixed-function PMCs do 
not require any UMASK.
•Simplified event programming  — Most frequent operation in programming performance events are 
enabling/disabling event counting and checking the stat us of counter overflows. Architectural performance 
event version 2 provides three architectural MSRs:
— IA32_PERF_GLOBAL_CTRL allows software to enable/d isable event counting of all or any combination of 
fixed-function PMCs (IA32_FIXED_CTRx) or an y general-purpose PMCs via a single WRMSR.
— IA32_PERF_GLOBAL_STATUS allows software to query counter overflow conditions on any combination of 
fixed-function PMCs or general-purpose PMCs via a single RDMSR.
— IA32_PERF_GLOBAL_OVF_CTRL allows software to clear counter overflow conditions on any combination of 
fixed-function PMCs or general-purpose PMCs via a single WRMSR.
•PMI Overhead Mitigation — Architectural performance monitoring version 2 introduces two bit field interface 
in IA32_DEBUGCTL for PMI service routine to accumulate  performance monitoring data and LBR records with 
reduced perturbation from servicing the PMI. The two bit fields are:
— IA32_DEBUGCTL.Freeze_LBR_On_PMI(bit 11). In architec tural performance monitoring version 2, only the 
legacy semantic behavior is supported. See Section 18.4.7 for details of the legacy Freeze LBRs on PMI 
control.
— IA32_DEBUGCTL.Freeze_PerfMon_On_PMI(bit 12). In architectural performance monitoring version 2, 
only the legacy semantic behavior is  supported. See Section 18.4.7 for details of the legacy Freeze LBRs on 
PMI control.
The facilities provided by architectural performance monito ring version 2 can be queried from CPUID leaf 0AH by 
examining the content of register EDX:
•Bits 0 through 4 of CPUID.0AH.EDX indicates the number of fixed-function performance counters available per 
core,
•Bits 5 through 12 of CPUID.0AH.EDX indicates the bit- width of fixed-function performance counters. Bits 
beyond the width of the fixed-function counter are reserved and must be written as zeros.
NOTE
Early generation of processors based on Intel Core microarchitecture may report in CPUID.0AH:EDX of support for version 2 but indicati ng incorrect information of version 2 facilities.
The IA32_FIXED_CTR_CTRL MSR include multiple sets of 4-bi t field, each 4 bit field controls the operation of a 
fixed-function performance counter. Figure 20-2 shows the layout of 4-bit controls for each fixed-function PMC. 
Two sub-fields are currently defined within each control. The definitions of the bit fields are:20-8 Vol. 3BPERFORMANCE MONITORING
•Enable field (lowest 2 bits within each 4-bit control)  — When bit 0 is set, performance counting is 
enabled in the corresponding fixed-function performa nce counter to increment while the target condition 
associated with the architecture performance event occurre d at ring 0. When bit 1 is set, performance counting

NOTE
associated with the architecture performance event occurre d at ring 0. When bit 1 is set, performance counting 
is enabled in the corresponding fixed-function perfor mance counter to increment while the target condition 
associated with the architecture performance event occurred at ring greater than 0. Writing 0 to both bits stops 
the performance counter. Writing a value of 11B enables the counter to increment irrespective of privilege 
levels.
•PMI field (the fourth bit within each 4-bit control)  — When set, the logical processor generates an 
exception through its local APIC on overflow condition of the respective fixed-function counter.
IA32_PERF_GLOBAL_CTRL MSR provides single-bit contro ls to enable counting of each performance counter. 
Figure 20-3 shows the layout of IA32_PERF_GLOBAL_C TRL. Each enable bit in IA32_PERF_GLOBAL_CTRL is 
AND’ed with the enable bits for all privilege levels in  the respective IA32_PERFEVTSELx or IA32_PERF_FIXED_C-
TR_CTRL MSRs to start/stop the counting of respective count ers. Counting is enabled if the AND’ed results is true; 
counting is disabled when the result is false.
The behavior of the fixed function performance counters  supported by architectural performance version 2 is 
expected to be consistent on all processors that support those counters, and is defined as follows.Figure 20-2.  Layout of IA32_FIXED_CTR_CTRL MSR
Figure 20-3.  Layout of IA32_PERF_GLOBAL_CTRL MSRCntr2 — Controls for IA32_FIXED_CTR2
Cntr1 — Controls for IA32_FIXED_CTR1
PMI — Enable PMI on overflow
Cntr0 — Controls for IA32_FIXED_CTR087 0
ENABLE — 0: disable; 1: OS; 2: User; 3: All ring levelsE
NP
M
I11 312 1
Reserved63 2
E
NE
N4 95
P P
M M
I I
IA32_FIXED_CTR2 enable
IA32_FIXED_CTR1 enable
IA32_FIXED_CTR0 enable
IA32_PMC1 enable210
IA32_PMC0 enable3132333435
Reserved63Vol. 3B 20-9PERFORMANCE MONITORING
IA32_PERF_GLOBAL_STATUS MSR provides single-bit status for software to query the overflow condition of each 
performance counter. IA32_PERF_GLOBAL_STATUS[bit 62] in dicates overflow conditions of the DS area data 
buffer. IA32_PERF_GLOBAL_STATUS[bit 63] provides a Cond Chgd bit to indicate changes to the state of perfor-
mance monitoring hardware. Figure 20-4 shows the layout of IA32_PERF_GLOBAL_STATUS. A value of 1 in bits 0, 
1, 32 through 34 indicates a counter overflow condition has occurred in the associated counter.
When a performance counter is configured for PEBS, overflow condition in the counter generates a performance-
monitoring interrupt signaling a PEBS event. On a PEBS event, the processo r stores data records into the buffer 
area (see Section 18.15.5), clears the counter overflow  status., and sets the “OvfBuffer” bit in IA32_PERF_-
GLOBAL_STATUS. Table 20-2.  Association of Fixed-Function Performa nce Counters with Architectural Performance Events
Fixed-Function 
Performance CounterAddress Event Mask Mnemonic Description
IA32_FIXED_CTR0 309H INST_RETIRED.ANY This event co unts the number of inst ructions that retire 
execution. For instructions that consist of multiple uops, this event counts the retireme nt of the last uop of the 
instruction. The counter continues counting during 
hardware interrupts, traps, an d in-side interrupt handlers.
IA32_FIXED_CTR1 30AH CPU_CLK_UNHALTED.THREAD
CPU_CLK_UNHALTED.COREThe CPU_CLK_UNHALTED.THREAD event counts the 
number of core cycles while the logical processor is not in a halt state.
If there is only one logical processor in a processor core, 
CPU_CLK_UNHALTED.CORE counts the unhalted cycles of 
the processor core.
The core frequency may change from time to time due to 
transitions associat ed with Enhanced Intel SpeedStep 
Technology or TM2. For this reason this event may have a 
changing ratio with  regards to time.
IA32_FIXED_CTR2 30BH CPU_CLK_UNHALTED.REF_TSC This event counts the number of reference cycles at the 
TSC rate when the core is not in a halt state and not in a TM stop-clock state. The core enters the halt state when it is 
running the HLT instruction or the MWAIT instruction. This 
event is not affected by core frequency changes (e.g., P states) but counts at the same  frequency as the time stamp 
counter. This event can approximate elapsed time while the 
core was not in a halt state and not in a TM stopclock state.
IA32_FIXED_CTR3 30CH TOPDOWN.SLOTS This event co unts the number of available slots for an 
unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by 
the Top-down Microarchitect ure Analysis method. The 
count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. 
Software can use this event as the denominator for the 
top-level metrics of the To p-down Microarchitecture 
Analysis method.20-10 Vol. 3BPERFORMANCE MONITORING
IA32_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow indicator(s) of any general-purpose or fixed-
function counters via a single WRMSR. Software should clear overflow indications when
•Setting up new values in the event select and/or UMASK  field for counting or interrupt-based event sampling.
•Reloading counter values to continue collecting next sample.
•Disabling event counting or interrupt-based event sampling.
The layout of IA32_PERF_GLOBAL_O VF_CTL is shown in Figure 20-5.
20.2.3 Architectural Performa nce Monitoring Version 3 
Processors supporting architectural performance monitoring version 3 also supports version 1 and 2, as well as 
capability enumerated by CPUID leaf 0AH. Specifically, version 3 provides the follow ing enhancement in perfor-
mance monitoring facilities if a processor core comprising of more than one logical processor, i.e., a processor core 
supporting Intel Hyper-Threading Technology or  simultaneous multi-threading capability:
•AnyThread counting for processor core supporting two or  more logical processors. The interface that supports 
AnyThread counting include:
— Each IA32_PERFEVTSELx MSR (starting at MSR address 1 86H) support the bit field la yout defined in Figure 
20-6.Figure 20-4.  Layout of IA32_PERF_GLOBAL_STATUS MSR
Figure 20-5.  Layout of IA32_PERF_GLOBAL_OVF_CTRL MSR62
IA32_FIXED_CTR2 Overflow
IA32_FIXED_CTR1 Overflow
IA32_FIXED_CTR0 Overflow
IA32_PMC1 Overflow210
IA32_PMC0 Overflow3132333435
Reserved63
CondChgd
OvfDSBuffer
62
IA32_FIXED_CTR2 ClrOverflow
IA32_FIXED_CTR1 ClrOverflow
IA32_FIXED_CTR0 ClrOverflow
IA32_PMC1 ClrOverflow210
IA32_PMC0 ClrOverflow3132333435
ClrCondChgd
ClrOvfDSBufferVol. 3B 20-11PERFORMANCE MONITORING
Bit 21 (AnyThread)  of IA32_PERFEVTSELx is supported in archit ectural performance monitoring version 3 for 
processor core comprising of two or more logical proces sors. When set to 1, it enables counting the associated 
event conditions (including matching the thread’s CPL with the OS/USR setti ng of IA32_PERFEVTSELx) 
occurring across all logical processors sharing a processor core. When bit 21 is 0, the counter only increments 
the associated event conditions (including matching th e thread’s CPL with the OS/USR setting of IA32_PERFE-
VTSELx) occurring in the logical processor which programmed the IA32_PERFEVTSELx MSR.
— Each fixed-function performance counter IA32_FIXED _CTRx (starting at MSR address 309H) is configured 
by a 4-bit control block in the IA32_PERF_FIXED_CTR_ CTRL MSR. The control block also allows thread-
specificity configuration using an AnyThread bit for fixed-function counters 0, 1, and 2. The layout of 
IA32_PERF_FIXED_CTR_CTRL MSR is shown. 
Each control block for a fixed-function performance counter provides an AnyThread  (bit position 2 + 4*N, N= 
0, 1, etc.) bit. When set to 1, it enables counting th e associated event conditions (including matching the 
thread’s CPL with the ENABLE setti ng of the corresponding control bl ock of IA32_PERF_FIXED_CTR_CTRL) 
occurring across all logical processors sharing a processor core. When an AnyThread bit is 0 in IA32_PERF_-
FIXED_CTR_CTRL, the corresponding fixed counter only increments the associated event conditions occurring 
in the logical processor which programmed the IA32_PERF_FIXED_CTR_CTRL MSR.
•The IA32_PERF_GLOBAL_CTRL, IA32_PERF_GLOBAL_STA TUS, IA32_PERF_GLOBAL_OVF_CTRL MSRs provide 
single-bit controls/status for each general-purpose and fixed-function performance counter. Figure 20-8 and Figure 20-9 show the layout of these MSRs for N gene ral-purpose performance counters (where N is reported 
by CPUID.0AH:EAX[15:8]) and three fixed-function counters.Figure 20-6.  Layout of IA32_PERFEVTSELx MSRs Suppo rting Architectural Performance Monitoring Version 3
Figure 20-7.  IA32_FIXED_CTR_CTRL MSR Supporting Architectural Performanc e Monitoring Version 331
OS—Operating system mode
USR—User ModeCounter Mask EE
NI
N
ReservedI
N
VP
CU
S
RO
SUnit Mask (UMASK)(CMASK)63
ANY—Any ThreadA
N
Y
Cntr2 — Controls fo r IA32_FIXED_CTR2
Cntr1 — Controls fo r IA32_FIXED_CTR1
PMI — Enable PMI on overflow on IA32_FIXED_CTR0
AnyThread — AnyThread for IA32_FIXED_CTR087 0

NI
N
ReservedI
N
VP
CU
S
RO
N
Y
ENABLE — IA32_FIXED_CTR0. 0: disable; 1: OS; 2: User; 3: All ring levelsE
NP
M
I11 312 1
E
NE
N4 95
P P
M M
I IA
N
YA
N
YA
N
Y20-12 Vol. 3BPERFORMANCE MONITORING
NOTE
The number of general-purpose performance monitoring  counters (i.e., N in Figure 20-9) can vary 
across processor generations within a processor family, across processor families, or could be 
different depending on the configuration chosen at  boot time in the BIOS regarding Intel Hyper 
Threading Technology, (e.g., N=2 for 45 nm Intel Atom processors; N =4 for processors based on 
the Nehalem microarchitecture; for processors based on the Sandy Bridge microarchitecture, N = 
4 if Intel Hyper Threading Technology is active an d N=8 if not active). In addition, the number of 
counters may vary from the number of physical counters present on the hardware, because an 
agent running at a higher privilege level (e.g., a VMM) may not expose all counters.
Figure 20-8.  Layout of Global Performance Monitoring Control MSR
Figure 20-9.  Global Performance Monitoring Overflow Status and Control MSRsIA32_FIXED_CTR2 enable
IA32_PMC(N-1) enable..10
.................... enable3132333435
Reserved63 ..N
IA32_PMC1 enable
IA32_PMC0 enableGlobal Enable Controls IA32_PERF_GLOBAL_CTRL
62
IA32_FIXED_CTR1 OverflowIA32_FIXED_CTR0 OverflowIA32_PMC1 Overflow..10
IA32_PMC0 Overflow3132333435 63
CondChgd
OvfDSBuffer..N
...................... OverflowIA32_PMC(N-1) OverflowGlobal Overflow Status IA32_PERF_GLOBAL_STATUS
62
IA32_PMC1 ClrOverflow..10
IA32_PMC0 ClrOverflow3132333435 63
ClrOvfDSBufferGlobal Overflow Status IA32_PERF_GLOBAL_OVF_CTRL
........................ ClrOverflowIA32_PMC(N-1) ClrOverflowN..
ClrOvfUncoreOvfUncore61Vol. 3B 20-13PERFORMANCE MONITORING
20.2.3.1  AnyThread Countin g and Software Evolution
The motivation for characterizing software workload over  multiple software threads running on multiple logical 
processors of the same processor core originates from a time earlier than the introduction of the AnyThread inter-
face in IA32_PERFEVTSELx and IA32_FIXED_CTR_CTRL. Wh ile AnyThread counting prov ides some benefits in 
simple software environments of an earlier era, the evolution contemporary software environments introduce 
certain concepts and pre-requisites that AnyThread counting does not comply with. 
One example is the proliferation of software environments  that support multiple virtual machines (VM) under VMX 
(see Chapter 24, “Introduction to Virtual Machine Extens ions”) where each VM represents a domain separated 
from one another.
A Virtual Machine Monitor (VMM) that manages the VMs may allow an individual VM to  employ performance moni-
toring facilities to profiles the performance characterist ics of a workload. The use of  the Anythread interface in 
IA32_PERFEVTSELx and IA32_FIXED_CTR_C TRL is discouraged with software environments supporting virtualiza-
tion or requiring domain separation. 
Specifically, Intel recommends VMM:
•Configure the MSR bitmap to cause VM-exits for WR MSR to IA32_PERFEVTSELx and IA32_FIXED_CTR_CTRL in 
VMX non-Root operation (see Chapter 25 for additional information), 
•Clear the AnyThread bit of IA32_PERFEVTSELx and IA32_FI XED_CTR_CTRL in the MSR-load lists for VM exits 
and VM entries (see Chapter 25, Chapter 27, and Chapter 28).
Even when operating in simpler legacy software environm ents which might not emphasize the pre-requisites of a 
virtualized software environment, the use of the AnyThr ead interface should be moderated and follow any event-
specific guidance where explicitly noted.
20.2.4 Architectural Performance Monitoring Version 4 
Processors supporting architectural performance monitoring version 4 also supports version 1, 2, and 3, as well as 
capability enumerated by CPUID leaf 0AH. Version 4 intr oduced a streamlined PMI overhead mitigation interface 
that replaces the legacy semantic behavior but reta ins the same control interf ace in IA32_DEBUGCTL.Freeze_L-
BRs_On_PMI and Freeze_PerfMon_On_PMI. Specifically  version 4 provides the following enhancements:
•New indicators (LBR_FRZ, CTR_FRZ) in IA32_PERF_GLOBAL_STATUS, see Section 20.2.4.1.
•Streamlined Freeze/PMI Overhead ma nagement interfaces to use IA32_DEBUGCTL.Freeze_LBRs_On_PMI and 
IA32_DEBUGCTL.Freeze_PerfMon_On_PMI: see Section 20. 2.4.1. Legacy semantics of Freeze_LBRs_On_PMI 
and Freeze_PerfMon_On_PMI (applicable to version 2 an d 3) are not supported with version 4 or higher.
•Fine-grain separation of control interface to ma nage overflow/status of IA32_PERF_GLOBAL_STATUS and 
read-only performance counter enabling interface in IA32_PERF_GLOBAL_STATUS: see Section 20.2.4.2.
•Performance monitoring resource in-use MSR to fac ilitate cooperative sharing protocol between perfmon-
managing privilege agents.
20.2.4.1  Enhancement in  IA32_PERF_GLOBAL_STATUS 
The IA32_PERF_GLOBAL_STATUS MSR provides the following in dicators with architectural performance monitoring 
version 4:
•IA32_PERF_GLOBAL_STATUS.LBR_FRZ[bit 58]: This bit is set due to the following conditions:
— IA32_DEBUGCTL.FREEZE_LBR_ON_PMI has been set by the pr ofiling agent, and
— A performance counter, configured to generate PMI, has overflowed to signal a PMI. Consequently the LBR 
stack is frozen.
Effectively, the IA32_PERF_GLOBAL_STATUS.LBR_FRZ bit also  serves as a control to enable capturing data in 
the LBR stack. To enable capturing LBR records, the foll owing expression must hold with architectural perfmon 
version 4 or higher:
— (IA32_DEBUGCTL.LBR & (!IA32_PERF_GLOBAL_STATUS.LBR_FRZ) ) =1
•IA32_PERF_GLOBAL_STATUS.CTR_FRZ[bit 59]: This bit is set due to the following conditions:20-14 Vol. 3BPERFORMANCE MONITORING
— IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI has been set by the profiling agent, and
— A performance counter, configured to generate PMI, ha s overflowed to signal a PMI. Consequently, all the 
performance counters are frozen.
Effectively, the IA32_PERF_GLOBAL_STATUS.CTR_FRZ bit also serve as an read-only control to enable 
programmable performance counters and fixed counters in the core PMU. To enable counting with the performance counters, the following expression must hold with architectural perfmon version 4 or higher:
•(IA32_PERFEVTSELn.EN & IA32_PERF_GLOBAL_CTRL.PMCn & (!IA32_PERF_-
GLOBAL_STATUS.CTR_FRZ) ) = 1 for programmable counter ‘n’, or 
•(IA32_PERF_FIXED_CRTL.ENi & IA32_PERF_GLOBAL_CTRL.FCi & (!IA32_PERF_-
GLOBAL_STATUS.CTR_FRZ) ) = 1 for fixed counter ‘i’
The read-only enable interface IA32_PERF_GLOBAL_STATUS .CTR_FRZ provides a more efficient flow for a PMI 
handler to use IA32_DEBUGCTL.Freeze_Perfmon_On_PMI to filt er out data that may distort target workload anal-
ysis, see Table 18-3. It should be noted the IA32_PERF_GLOBAL_CTRL register continue to serve as the primary 
interface to control all performance counters of the logical processor. 
For example, when the Freeze-On-PMI mode is not be ing used, a PMI handler would be setting IA32_PERF_-
GLOBAL_CTRL as the very last step to commence the over all operation after configuring the individual counter 
registers, controls, and PEBS facility. This does not only assure atomic monitoring but also avoids unnecessary 
complications (e.g., race conditions) when software attempts to change the core PMU configuration while some counters are kept enabled.
Additionally, IA32_PERF_GLOBAL_STATUS.TraceToPAPMI[bit 55 ]: On processors that support Intel Processor Trace 
and configured to store trace output packets to physical memory using the ToPA scheme, bit 55 is set when a PMI 
occurred due to a ToPA entry memory buffer was completely filled. 
IA32_PERF_GLOBAL_STATUS also provides an indicator to distinguish interaction of performance monitoring oper-
ations with other side-band activities, which apply Intel SG X on processors that support it (for additional informa-
tion about Intel SGX, see the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3D):
•IA32_PERF_GLOBAL_STATUS.ASCI[bit 60]: This bit is set when data accumulated in any of the configured 
performance counters (i.e., IA32_PMCx or IA32_ FIXED_CTRx ) may include contributions from direct or indirect 
operation of Intel SGX to protect an enclave (sin ce the last time IA32_PERF_GLOBAL_STATUS.ASCI was 
cleared). 
Note, a processor’s support for IA32_PERF_GLOBAL_STATUS. TraceToPAPMI[bit 55] is enumerated as a result of 
CPUID enumerated capability of Intel Processor Trace and the use of the ToPA buffer scheme. Support of IA32_PER-
F_GLOBAL_STATUS.ASCI[bit 60] is enumerated  by the CPUID enumeration of Intel SGX.Figure 20-10.  IA32_PERF_GLOBAL_STATUS MSR and Architectural Perfmon Version 4Reserved62
IA32_FIXED_CTR1 OverflowIA32_FIXED_CTR0 OverflowTraceToPAPMI.. 1 0
CondChgd
...................... OverflowIA32_PMC(N-1) OverflowOvfUncore61
IA32_PMC1 Overflow6059 58 55
ASCI

cleared). 
CondChgd
ASCI
LBR_FrzCTR_FrzVol. 3B 20-15PERFORMANCE MONITORING
20.2.4.2  IA32_PERF_GLOBAL_STATUS_RESE T and IA32_PERF_GLOBAL_STATUS_SET MSRS
With architectural performance monitoring version 3 an d lower, clearing of the set bits in IA32_PERF_-
GLOBAL_STATUS MSR by software is done via IA32_PERF_GLOBAL_OVF_CTRL MSR. Starting with architectural performance monitoring version 4, software can manage  the overflow and other indicators in IA32_PERF_-
GLOBAL_STATUS using separate interfaces to set or clear individual bits. 
The address and the architecturally-defined bits of IA32_PERF_GLOBAL_OVF_CTRL is inherited by IA32_PERF_-
GLOBAL_STATUS_RESET (see Figure 20-11). Further, IA 32_PERF_GLOBAL_STATUS_RESET provides additional bit 
fields to clear the new indicators in IA32_PERF_GLOBAL_STATUS described in Section 20.2.4.1.
The IA32_PERF_GLOBAL_STATUS_SET MSR is introduced with  architectural performance monitoring version 4. It 
allows software to set individual bits in IA32_P ERF_GLOBAL_STATUS. The IA32_PERF_GLOBAL_STATUS_SET 
interface can be used by a VMM to virtualize the state of IA32_PERF_GLOBAL_STATUS across VMs.
20.2.4.3  IA32_PERF_GLOBAL_INUSE MSR
In a contemporary software environment, multiple privil eged service agents may wish to employ the processor’s 
performance monitoring facilities. The IA32_MISC_ENABL E.PERFMON_AVAILABLE[bit 7] interface could not serve Figure 20-11.  IA32_PERF_GLOBAL_STATUS_RE SET MSR and Architectural Perfmon Version 4
Figure 20-12.  IA32_PERF_GLOBAL_STATUS_SET MSR and Architectural Perfmon Version 4Reserved62
Clr IA32_FIXED_CTR2 Ovf
Clr IA32_FIXED_CTR1 OvfClr IA32_FIXED_CTR0 OvfClr TraceToPAPMI..10
Clr IA32_PMC0 Ovf3132333435 63
Clr CondChgd
Clr OvfDSBuffer..N
Clr ...................... OvfClr IA32_PMC(N-1) OvfClr OvfUncore61
Clr IA32_PMC1 Ovf6059 58 55
Clr ASCI
Clr LBR_FrzClr CTR_Frz
ReservedSet IA32_FIXED_CTR2 Ovf
Set IA32_FIXED_CTR1 Ovf
Set IA32_FIXED_CTR0 OvfSet TraceToPAPMI..10
Set IA32_PMC0 Ovf3132333435
Set OvfDSBuffer..N
Set ...................... OvfSet IA32_PMC(N-1) OvfSet OvfUncore
Set IA32_PMC1 Ovf55
Set ASCI
Set LBR_FrzSet CTR_Frz63 62 61 60 59 5820-16 Vol. 3BPERFORMANCE MONITORING
the need of multiple agent adequately. A white pape r, “Performance Monitoring Unit Sharing Guideline”1, proposed 
a cooperative sharing protocol that is voluntary for participating software agents. 
Architectural performance monitoring version 4 introduc es a new MSR, IA32_PERF_GLOBAL_INUSE, that simplifies 
the task of multiple cooperating agents to implement the sharing protocol.
The layout of IA32_PERF_GLOBAL_INUSE is shown in Figure 20-13.
The IA32_PERF_GLOBAL_INUSE MSR provides an “InUse” bit for each programmable performance counter and 
fixed counter in the processor. Additionally, it includes an  indicator if the PMI mechanism has been configured by a 
profiling agent.
•IA32_PERF_GLOBAL_INUSE.PERFEVTSEL0_InUse[bit 0]: This bit reflects the logical state of (IA32_PERFE-
VTSEL0[7:0] != 0).
•IA32_PERF_GLOBAL_INUSE.PERFEVTSEL1_InUse[bit 1]: This bit reflects the logical state of (IA32_PERFE-
VTSEL1[7:0] != 0).
•IA32_PERF_GLOBAL_INUSE.PERFEVTSEL2_InUse[bit 2]: This bit reflects the logical state of (IA32_PERFE-VTSEL2[7:0] != 0).
•IA32_PERF_GLOBAL_INUSE.PERFEVTSELn_InUse[bit n]: This  bit reflects the logical state of (IA32_PERFE-
VTSELn[7:0] != 0), n < CPUID.0AH:EAX[15:8].
•IA32_PERF_GLOBAL_INUSE.FC0_InUse[bit 32]: This bi t reflects the logical state of (IA32_FIXED_C-
TR_CTRL[1:0] != 0).
•IA32_PERF_GLOBAL_INUSE.FC1_InUse[bit 33]: This bi t reflects the logical state of (IA32_FIXED_C-
TR_CTRL[5:4] != 0).
•IA32_PERF_GLOBAL_INUSE.FC2_InUse[bit 34]: This bi t reflects the logical state of (IA32_FIXED_C-
TR_CTRL[9:8] != 0).
•IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set if any one of the following bit is set:
— IA32_PERFEVTSELn.INT[bit 20], n < CPUID.0AH:EAX[15:8].
— IA32_FIXED_CTR_CTRL.ENi_PMI, i = 0, 1, 2.— Any IA32_PEBS_ENABLES bit which enables PEBS for a general-purpose or fixed-function performance 
counter.
1. Available at http ://www.intel.com/sdmFigure 20-13.  IA32_PERF_GLOBAL_INUSE MSR and Architectural Perfmon Version 4ReservedPMI InUse
FIXED_CTR2 InUse
FIXED_CTR1 InUse..10
PERFEVTSEL0 InUse3132333435 63 ..N
 ....................... InUsePERFEVTSEL(N-1) InUse
PERFEVTSEL1 InUseFIXED_CTR0 InUse
N = CPUID.0AH:EAX[15:8]Vol. 3B 20-17PERFORMANCE MONITORING
20.2.5 Architectural Performance Monitoring Version 5 
Processors supporting architectural performance monitoring ve rsion 5 also support versions 1, 2, 3, and 4, as well 
as capability enumerated by CPUID leaf 0AH. Specif ically, version 5 provides the following enhancements:
•Deprecation of AnyThread mode, see Section 20.2.5.1.
•Individual enumeration of Fixed counter s in CPUID.0AH, see Section 20.2.5.2.
•Domain separation, see Section 20.2.5.3.
20.2.5.1  AnyThread Mode Deprecation
With Architectural Performance Monitoring Version 5, a processor that supports AnyThread mode deprecation is 
enumerated by CPUID.0AH.EDX[15]. If set, software w ill not have to follow guidelines in Section 20.2.3.1.
20.2.5.2  Fixed Counter Enumeration
With Architectural Performance Monitoring Version 5, register CPUID.0AH.ECX indicates Fixed Counter enumera-
tion. It is a bit mask which enumerates the supported Fixed Counters in a processor. If bit 'i' is set, it implies that 
Fixed Counter 'i' is supported. Software is recommended to use the following logic to check if a Fixed Counter is 
supported on a given processor: 
FxCtr[i]_is_supported := ECX[i] || (EDX[4:0] > i);
20.2.5.3  Domain Separation
When the INV flag in IA32_PERFEVTSELx is used, a counte r stops counting when the logical processor exits the C0 
ACPI C-state.
20.2.6 Full-Width Writes to Performance Counter Registers
The general-purpose performance counter registers IA32_PM Cx are writable via WRMSR instruction. However, the 
value written into IA32_PMCx by WRMSR is the signed ex tended 64-bit value of the EAX[31:0] input of WRMSR.
A processor that supports full-width writes to the general-purpose performance counters enumerated by 
CPUID.0AH:EAX[15:8] will set IA32_PERF_CAPABILITIES[13] to enumerate its full-width-write capability See 
Figure 20-65. 
If IA32_PERF_CAPABILITIES.FW_WRITE[bit 13] =1, each IA32_PMCi is accompanied by a corresponding alias 
address starting at 4C1H for IA32_A_PMC0. 
The bit width of the performance monitoring co unters is specified in CPUID.0AH:EAX[23:16].
If IA32_A_PMCi is present, the 64-bit input value (EDX :EAX) of WRMSR to IA32_A_PMCi will cause IA32_PMCi to 
be updated by:
COUNTERWIDTH = CPUID.0AH:EAX[23:16] bit widt h of the performance monitoring counter
IA32_PMCi[COUNTERWIDTH-1:32] :=  EDX[COUNTERWIDTH-33:0]);    
IA32_PMCi[31:0] := EAX[31:0];
EDX[63:COUNTERWIDTH] are reserved
20.3 PERFORMANCE MONITORING (INT EL® CORE™ PROCESSORS AND INTEL® 
XEON® PROCESSORS)
20.3.1 Performance Monitoring for Proce ssors Based on Nehalem Microarchitecture
Intel Core i7 processor family2 supports architectural performance monitoring capability with version ID 3 (see 
Section 20.2.3) and a host of non-architectural monitoring capabilities. The Intel Core i7 processor family is based 20-18 Vol. 3BPERFORMANCE MONITORING
on Nehalem microarchitecture, and provides four general-purpose performance counters (IA32_PMC0, 
IA32_PMC1, IA32_PMC2, IA32_PMC3) and three fixed-fu nction performance counters (IA32_FIXED_CTR0, IA32_-
FIXED_CTR1, IA32_FIXED_CTR2) in the processor core. 
Non-architectural performance monitoring in Intel Core i7 processor family uses the IA32_PERFEVTSELx MSR to 
configure a set of non-architecture performance monitori ng events to be counted by the corresponding general-
purpose performance counter. The list of non-architectural performance monitoring events can be found at: 
https://perfmon-events.intel.com/ . Non-architectural performance monitoring events fall into two broad catego-
ries:
•Performance monitoring events in the processor core : These include many events that are similar to 
performance monitoring events available to processor based on Intel Core microarchitecture. Additionally, 
there are several enhancements in the performance moni toring capability for detecting microarchitectural 
conditions in the processor core or in the interaction of  the processor core to the off-core sub-systems in the 
physical processor package. The off-core sub-systems in  the physical processor package is loosely referred to 
as “uncore“.
•Performance monitoring events in the uncore: The uncore  sub-system is shared by more than one processor 
cores in the physical processor package. It provides additional performance monitoring facility outside of 
IA32_PMCx and performance monitoring events that are specific to the uncore sub-system.
Architectural and non-architectural performance monitoring ev ents in Intel Core i7 processor family support thread 
qualification using bit 21 of  IA32_PERFEVTSELx MSR.

qualification using bit 21 of  IA32_PERFEVTSELx MSR. 
The bit fields within each IA32_PERFEVTSELx MSR are define d in Figure 20-6 and described in Section 20.2.1.1 and 
Section 20.2.3. 
20.3.1.1  Enhancements of Performance Monitoring  in the Processor Core
The notable enhancements in the monitoring of pe rformance events in the processor core include:
•Four general purpose performance counters, IA32_PMCx,  associated counter configuration MSRs, IA32_PERFE-
VTSELx, and global counter control MS R supporting simplified control of four counters. Each of the four 
performance counter can support processor event based sa mpling (PEBS) and thread-qualification of architec-
tural and non-architectural performance events. Widt h of IA32_PMCx supported by hardware has been 
increased. The width of counter reported by CPUID.0AH: EAX[23:16] is 48 bits. The PEBS facility in Nehalem 
2. Intel Xeon processor 5500 series and 3400 series are also based on Nehalem microarchitecture; the performance monitoring faci li-
ties described in this section generally also apply.Figure 20-14.  IA32_PERF_GLOBAL_STATUS MSR CHG (R/W)
OVF_PMI (R/W)87 0 32 31
Reserved63 2 4 31 56 62 6061
OVF_PC7 (R/O), if CCNT>7
OVF_PC6 (R/O), if CCNT>6
OVF_PC5 (R/O), if CCNT>5OVF_PC4 (R/O), if CCNT>4
OVF_PC3 (R/O)
OVF_PC2 (R/O)OVF_PC1 (R/O)
OVF_PC0 (R/O)
RESET Value — 00000000_00000000HOVF_FC2 (R/O)
OVF_FC1 (R/O)353433
OVF_FC0 (R/O)
CCNT: CPUID.AH:EAX[15:8]Vol. 3B 20-19PERFORMANCE MONITORING
microarchitecture has been enhanced to include new data  format to capture additional information, such as 
load latency.
•Load latency sampling facility. Average latency of memo ry load operation can be sampled using load-latency 
facility in processors based on Nehalem microarchitecture.  This field measures the load latency from load's first 
dispatch of till final data writeback from the memory subsystem. The latency is reported for retired demand 
load operations and in core cycles (it accounts for re-dis patches). This facility is used in conjunction with the 
PEBS facility.
•Off-core response counting facility. This facility in the processor core allows software to count certain 
transaction responses between the processor core to  sub-systems outside the processor core (uncore). 
Counting off-core response requires additional event qu alification configuration facility in conjunction with 
IA32_PERFEVTSELx. Two off-core response MSRs are provid ed to use in conjunction with specific event codes 
that must be specified with IA32_PERFEVTSELx.
NOTE
The number of counters available to software may vary from the number of physical counters present on the hardware, because an agent running at a higher privilege level (e.g., a VMM) may 
not expose all counters. CPUID.0AH:EAX[15:8] reports the MSRs available to software; see Section 
20.2.1.
20.3.1.1.1  Processor Event Based Sampling (PEBS)
All general-purpose performance counte rs, IA32_PMCx, can be used for PEBS if the performance event supports 
PEBS. Software uses IA32_MISC_ENABLE[7] and IA32_MI SC_ENABLE[12] to detect whether the performance 
monitoring facility and PEBS functionality are supported in the processor. The MSR IA32_PEBS_ENABLE provides 4 
bits that software must use to enable which IA32_PMC x overflow condition will cause the PEBS record to be 
captured. 
Additionally, the PEBS record is expanded to allow la tency information to be captured. The MSR IA32_PEBS_EN-
ABLE provides 4 additional bits that software must use to  enable latency data recordin g in the PEBS record upon 
the respective IA32_PMCx overflow condition. The layout  of IA32_PEBS_ENABLE for processors based on Nehalem 
microarchitecture is shown in Figure 20-15.
When a counter is enabled to capture machine state (PEB S_EN_PMCx = 1), the processor will write machine state 
information to a memory buffer spec ified by software as detailed below.  When the counter IA32_PMCx overflows 
from maximum count to zero, the PEBS hardware is armed. 
Upon occurrence of the next PEBS event, the PEBS hardware  triggers an assist and causes a PEBS record to be 
written. The format of the PEBS record is indicate d by the bit field IA32_PERF_CAPABILITIES[11:8] (see 
Figure 20-65).Figure 20-15.  Layout of IA32_PEBS_ENABLE MSR LL_EN_PMC3 (R/W)
LL_EN_PMC2 (R/W)87 0
LL_EN_PMC1 (R/W)32 3 33 1
Reserved63 2 4 31 56 343536
PEBS_EN_PMC3 (R/W)
PEBS_EN_PMC2 (R/W)
PEBS_EN_PMC1 (R/W)
PEBS_EN_PMC0 (R/W)LL_EN_PMC0 (R/W)
RESET Value — 00000000_00000000H20-20 Vol. 3BPERFORMANCE MONITORING
The behavior of PEBS assists is reported by IA32_PER F_CAPABILITIES[6] (see Figure 20-65). The return instruc-
tion pointer (RIP) reported in the PEBS record will point to the instruction after (+1) the instruction that causes the 
PEBS assist. The machine state reported in the PEBS record  is the machine state after the instruction that causes 
the PEBS assist is retired. For instance, if the instructions:
mov eax, [eax] ; causes PEBS assist
nopare executed, the PEBS record will report the address of th e nop, and the value of EAX in the PEBS record will show 
the value read from memory, not the target address of the read operation.
The PEBS record format is shown in Table 20-3, and each fi eld in the PEBS record is 64 bits long. The PEBS record 
format, along with debug/store area storage format, does no t change regardless of IA-32e mode is active or not. 
CPUID.01H:ECX.DTES64[bit 2] reports whether the processo r's DS storage format support is mode-independent. 
When set, it uses 64-bit DS storage format.
In IA-32e mode, the full 64-bit value is written to the regist er. If the processor is not operating in IA-32e mode, 32-
bit value is written to registers with bits 63:32 zeroed. Registers not defined when the processor is not in IA-32e 
mode are written to zero. 
Bytes AFH:90H are enhancement to the PEBS record format. Support for this enhanced PEBS record format is indi-
cated by IA32_PERF_CAPABILITIES[11:8] encoding of 0001B.
The value written to bytes 97H:90H is the state of the IA32_PERF_GLOBAL_STATUS register before the PEBS assist 
occurred. This value is written so software can determin e which counters overflowed when this PEBS record was 
written. Note that this field indicates the overflow st atus for all counters, regardless of whether they were 
programmed for PEBS or not.
Programming PEBS Facility
Only a subset of non-architectural performance events in the processor support PEBS. The subset of precise events 
are listed in Table 20-84. In addition to using IA32_PER FEVTSELx to specify event uni t/mask settings and setting 
the EN_PMCx bit in the IA32_PEBS_ENABLE register for the re spective counter, the software must also initialize the 
DS_BUFFER_MANAGEMENT_A REA data structure in memory to support capturing PEBS records for precise events.
The recording of PEBS records may not operate properly if accesses to the linear addresses in the DS buffer 
management area or in the PEBS buffer (see below) cause page faults, VM exits, or the setting of accessed or dirty flags in the paging structures (ordinary or EPT). For that reason, system software should establish paging struc-
tures (both ordinary and EPT) to preven t such occurrences. Implications of this may be that an operating system 
should allocate this memory from a non-paged pool and that system software cannot do “lazy” page-table entry 
propagation for these pages. A virtual-machine monitor may choose to allow use of PEBS by guest software only if 
EPT maps all guest-physical memo ry as present and read/write.Table 20-3.  PEBS Record Format for Intel Core i7 Processor Family
Byte Offset Field Byte Offset Field
00H R/EFLAGS 58H R908H R/EIP 60H R10
10H R/EAX 68H R11
18H R/EBX 70H R1220H R/ECX 78H R13
28H R/EDX 80H R14
30H R/ESI 88H R1538H R/EDI
90H IA32_PERF_GLOBAL_STATUS
40H R/EBP 98H Data Linear Address
48H R/ESP A0H Data Source Encoding
50H R8 A8H Latency value (core cycles)Vol. 3B 20-21PERFORMANCE MONITORING
NOTE
PEBS events are only valid when the following fi elds of IA32_PERFEVTSELx are all zero: AnyThread, 
Edge, Invert, CMask.
The beginning linear address of the DS_BUFFER_MANAGE MENT_AREA data structure must be programmed into 
the IA32_DS_AREA register. The layout of the DS_B UFFER_MANAGEMENT_AREA is shown in Figure 20-16.
•PEBS Buffer Base : This field is programmed with the linear a ddress of the first byte  of the PEBS buffer 
allocated by software. The processor reads this fiel d to determine the base address of the PEBS buffer.
•PEBS Index : This field is initially programmed with the same value as the PEBS Buffer Base field, or the 
beginning linear address of the PEBS buffer. The processor reads this field to determine the location of the next 
PEBS record to write to. After a PEBS record has been written, the processor also updates this field with the 
address of the next PEBS record to be  written. The figure above illustrates the state of PEBS Index after the first 
PEBS record is written.
•PEBS Absolute Maximum : This field represents the absolute addres s of the maximum length of the allocated

•PEBS Absolute Maximum : This field represents the absolute addres s of the maximum length of the allocated 
PEBS buffer plus the starting address of the PEBS buff er. The processor will not write any PEBS record beyond 
the end of PEBS buffer, when PEBS Index  equals PEBS Absolute Maximum . No signaling is generated when 
PEBS buffer is full. Software must reset the PEBS Index  field to the beginning of the PEBS buffer address to 
continue capturing PEBS records.
Figure 20-16.  PEBS Programming EnvironmentBTS Buffer Base
BTS Index
Threshold
Threshold
Counter0 Reset
8H
10H
18H
20H
28H
30H
38H
40H
48H
58H
60HPEBS  
Counter1 Reset
PEBS  
Counter2 Reset
PEBS  
Counter3 Reset20-22 Vol. 3BPERFORMANCE MONITORING
•PEBS Interrupt Threshold : This field specifies the threshold value to trigger a performance interrupt and 
notify software that the PEBS  buffer is nearly full. This field is programmed with the linear address of the first 
byte of the PEBS record within the PEBS buffer that re presents the threshold record. After the processor writes 
a PEBS record and updates PEBS Index , if the PEBS Index  reaches the threshold value of this field, the 
processor will generate a performance interrupt. This is the same interrupt that is generated by a performance 
counter overflow, as programmed in the Performance Monitoring Counters vector in the Local Vector Table of 
the Local APIC. When a performance interrupt due to PEBS buffer full is generated, the IA32_PERF_-
GLOBAL_STATUS.PEBS_Ovf bit will be set.
•PEBS CounterX Reset : This field allows software to set up PEBS counter overflow condition to occur at a rate 
useful for profiling workload, thereby generating multiple  PEBS records to facilitate characterizing the profile 
the execution of test code. After each PEBS record is wr itten, the processor checks each counter to see if it 
overflowed and was enabled for PEBS (the correspon ding bit in IA32_PEBS_ENABLED was set). If these 
conditions are met, then the reset value for each overfl owed counter is loaded from the DS Buffer Management 
Area. For example, if counter IA32_PMC0 caused a PEBS re cord to be written, then the value of “PEBS Counter 
0 Reset” would be written to counter IA32_PMC0. If a counter is not enabled for PEBS, its value will not be modified by the PEBS assist.
Performance Counter PrioritizationPerformance monitoring interrupts are triggered by a count er transitioning from maximum count to zero (assuming 
IA32_PerfEvtSelX.INT is set). This same transition will ca use PEBS hardware to arm, but not trigger. PEBS hard-
ware triggers upon detection of the first PEBS event afte r the PEBS hardware has been armed (a 0 to 1 transition 
of the counter). At this point, a PEBS a ssist will be undertaken by the processor.
Performance counters (fixed and general-purpose) are priori tized in index order. That is, counter IA32_PMC0 takes 
precedence over all other counters. Counter IA32_P MC1 takes precedence over counters IA32_PMC2 and 
IA32_PMC3, and so on. This means that if simultaneous over flows or PEBS assists occur, the appropriate action will 
be taken for the highest priority performance counter. For example, if IA32_PMC1 cause an overflow interrupt and 
IA32_PMC2 causes an PEBS assist simultaneously, th en the overflow interrupt will be serviced first. 
The PEBS threshold interrupt is triggered by the PEBS assi st, and is by definition prioritized lower than the PEBS 
assist. Hardware will not generate separate interrupts fo r each counter that simultaneously overflows. General-
purpose performance counters are prioritized over fixed counters.
If a counter is programmed with a precise (PEBS-enabled)  event and programmed to generate a counter overflow 
interrupt, the PEBS assist is serviced before the counter over flow interrupt is serviced. If in addition the PEBS inter-
rupt threshold is met, the
threshold interrupt is generated after the PEBS assist co mpletes, followed by the counter overflow interrupt (two 
separate interrupts are generated).
Uncore counters may be programmed to interrupt one or more processor cores (see Section 20.3.1.2). It is 
possible for interrupts posted from the uncore facility to o ccur coincident with counter overflow interrupts from the 
processor core. Software must check core and uncore status registers to determine the exact origin of counter overflow interrupts.
20.3.1.1.2  Load Latency Performance Monitoring Facility
The load latency facility provides software a means to char acterize the average load latency to different levels of 
cache/memory hierarchy. This facility requires processo r supporting enhanced PEBS record format in the PEBS 
buffer, see Table 20-3. This field measures the load latency fr om load's first dispatch of till final data writeback from 
the memory subsystem. The latency is reported for retired demand load operations and in core cycles (it accounts 
for re-dispatches).
To use this feature software must assure:
•One of the IA32_PERFEVTSELx MSR is programmed to specify the event unit MEM_INST_RETIRED, and the 
LATENCY_ABOVE_THRESHOLD event mask must be spec ified (IA32_PerfEvtSelX[15:0] = 100H). The corre-
sponding counter IA32_PMCx will accumulate event count s for architecturally visible loads which exceed the 
programmed latency threshold specified separately in  a MSR. Stores are ignored when this event is 
programmed. The CMASK or INV fields of the IA32_PerfEvtSe lX register used for counting load latency must be 
0. Writing other values will result in undefined behavior. Vol. 3B 20-23PERFORMANCE MONITORING
•The MSR_PEBS_LD_LAT_THRESHOLD MSR is programmed wi th the desired latency threshold in core clock 
cycles. Loads with latencies greater than this value are eligible for counting and latency data reporting. The 
minimum value that may be programmed in this register is 3 (the minimum detectable load latency is 4 core 
clock cycles).
•The PEBS enable bit in the IA32_PEBS_ENABLE register is set for the corresponding IA32_PMCx counter 
register. This means that both the PEBS_EN_CTRX and LL_EN_CTRX bits must be set for the counter(s) of 
interest. For example, to enable load latency on count er IA32_PMC0, the IA32_PEBS_ENABLE register must be 
programmed with the 64-bit value 00000001_00000001H.
When the load-latency facility is enabled, load operations  are randomly selected by hardware and tagged to carry 
information related to data source locality and latency. Latency and data source information of tagged loads are 
updated internally. 
When a PEBS assist occurs, the last update of latency an d data source information are captured by the assist and 
written as part of the PEBS record. The PEBS sample afte r value (SAV), specified in PEBS CounterX Reset, operates 
orthogonally to the tagging mechanism. Loads are randomly  tagged to collect latency data. The SAV controls the 
number of tagged loads with latency information that will be  written into the PEBS record  field by the PEBS assists. 
The load latency data written to the PEBS  record will be for the last tagged lo ad operation which retired just before 
the PEBS assist was invoked.
The load-latency information written into a PEBS record (see Table 20-3, bytes AFH:98H) consists of:
•Data Linear Address : This is the linear address of the target of the load operation.
•Latency Value : This is the elapsed cycles of the tagged load  operation between dispatch to GO, measured in 
processor core clock domain.
•Data Source:  The encoded value indicates the origin of the data obtained by the load instruction. The 
encoding is shown in Table 20-4. In the descriptions,  local memory refers to system memory physically 
attached to a processor package, and remote memory refers to system memory physically attached to another 
processor package. 
Table 20-4.  Data Source Encoding for Load Latency Record
00H Unknown L3 cache miss.
01H Minimal latency core cache hit. This request was satisfied by the L1 data cache.
02H Pending core cache HIT. Outstandin g core cache miss to same cache- line address was already underway.
03H This data request wa s satisfied by the L2.
04H L3 HIT. Local or Remote home requests  that hit L3 cache in the uncore with no coherency actions required (snooping).
05H L3 HIT. Local or Remote home reques ts that hit the L3 cache and were serv iced by another processor core with a 
cross core snoop where no modifi ed copies were  found. (clean).
06H L3 HIT. Local or Remote home reques ts that hit the L3 cache and were serv iced by another processor core with a 
cross core snoop where no mo dified copies were found. 
07H1Reserved/LLC Snoop HitM. Local or Remote home requests that hit the last level cache and were serviced by another 
core with a cross core  snoop where modified copies were found.

core with a cross core  snoop where modified copies were found. 
08H Reserved/L3 MISS. Local homed requests that missed the L3  cache and were serviced by forwarded data following a 
cross package snoop where no modified copies were found. (Remote home requests are not counted).
09H Reserved0AH L3 MISS. Local home requests that missed the L3 cache and were  serviced by local DRAM  (go to shared state).
0BH L3 MISS. Remote home requests that missed the L3 cache and were serviced by remote DRAM (go to shared state).
0CH L3 MISS. Local home requests that mi ssed the L3 cache and were serviced by  local DRAM (go to exclusive state).
0DH L3 MISS. Remote home requests that missed the L3 cache and were serviced by remote DRAM (go to exclusive state).
0EH I/O, Request of in put/output operation.
0FH The request was to un-cacheable memory.20-24 Vol. 3BPERFORMANCE MONITORING
The layout of MSR_PEBS_LD_LAT_TH RESHOLD is shown in Figure 20-17.
Bits 15:0 specifies the threshold load latency in core cloc k cycles. Performance events with latencies greater than 
this value are counted in IA32_PMCx and their latency inform ation is reported in the PEBS record. Otherwise, they 
are ignored. The minimum value that may be programmed in this field is 3.
20.3.1.1.3  Off-core Response Perfor mance Monitoring in the Processor Core
Programming a performance event using the off-core respon se facility can choose any of the four IA32_PERFEVT-
SELx MSR with specific event codes and predefine mask bit value. Each event code for off-core response monitoring 
requires programming an associated configuration MS R, MSR_OFFCORE_RSP_0. There is only one off-core 
response configuration MSR. Table 20-5 lists the event code , mask value and additional off-core configuration MSR 
that must be programmed to count off- core response events using IA32_PMCx. 
The layout of MSR_OFFCORE_RSP_0 is shown in Figure 20-18 . Bits 7:0 specifies the request type of a transaction 
request to the uncore. Bits 15:8 specifie s the response of the uncore subsystem.NOTES:
1. Bit 7 is supported only for processors with a CPUID DisplayFamily_Di splayModel signature of 06_2 A, and 06_2E; otherwise it i s 
reserved.
Figure 20-17.  Layout of MSR_PEBS_LD_LAT MSR 
Table 20-5.  Off-Core Response Event Encoding
Event code in 
IA32_PERFEVTSELxMask Value in 
IA32_PERFEVTSELx Required Off-core Response MSR
B7H 01H MSR_OFFCORE_RSP_0 (address 1A6H)1615 0
THRHLD - Load latency threshold
RESET Value — 00000000_00000000HVol. 3B 20-25PERFORMANCE MONITORING
Figure 20-18.  Layout of MSR_OFFCORE_RSP_0 and MSR_ OFFCORE_RSP_1 to Configure Off-core Response Events
Table 20-6.  MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 Bit Field Definition
Bit Name Offset Description
DMND_DATA_RD 0 Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as 
demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction 
fetches.
DMND_RFO 1 Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a 
write to data cacheline.  Does not count L2 RFO.
DMND_IFETCH 2 Counts the number of demand instruction cacheline reads and L1 instruction cacheline prefetches.
WB 3 Counts the number of writeback (modified to exclusive) transactions.
PF_DATA_RD 4 Counts the number of data cacheline reads generated by L2 prefetchers.PF_RFO 5 Counts the number of RFO requests generated by L2 prefetchers.
PF_IFETCH 6 Counts the number of code reads generated by L2 prefetchers.
OTHER 7 Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or 
non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock.
UNCORE_HIT 8 L3 Hit: local or remote ho me requests that hit L3 cache in th e uncore with no coherency actions 
required (snooping).
OTHER_CORE_HI
T_SNP9 L3 Hit: local or remote home requests that hit L3  cache in the uncore and was serviced by another 
core with a cross core sn oop where no modified copies were found (clean).
TM10 L3 Hit: local or remote  home requests that hit L3 cache in the uncore and was serviced by another 
core with a cross core snoop where modified copies were found (HITM).
Reserved 11 ReservedREMOTE_CACHE_
FWD12 L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following 
a cross package snoop where no modified copies found. (Remote home requests are not counted)
REMOTE_DRAM 13 L3 Miss: remote home requests that missed th e L3 cache and were serviced by remote DRAM.
LOCAL_DRAM 14 L3 Miss: local home requests that miss ed the L3 cache and were serviced by local DRAM.RESPONSE TYPE — NON_DRAM (R/W)
RESPONSE TYPE — LOCAL_DRAM (R/W)
RESPONSE TYPE — REMOTE_DRAM (R/W)
RESPONSE TYPE — REMOTE_CACHE_FWD (R/W)87 0
RESPONSE TYPE — RESERVED11 312 1
Reserved63 2 4 95 6 10 131415
RESPONSE TYPE — OTHER_CORE_HITM (R/W)
RESPONSE TYPE — OTHER_CORE_HIT_SNP (R/W)
RESPONSE TYPE — UNCORE_HIT (R/W)
REQUEST TYPE — OTHER (R/W)
REQUEST TYPE — PF_IFETCH (R/W)
REQUEST TYPE — PF_RFO (R/W)
REQUEST TYPE — PF_DATA_RD (R/W)
REQUEST TYPE — WB (R/W)
REQUEST TYPE — DMND_IFETCH (R/W)
REQUEST TYPE — DMND_RFO (R/W)
REQUEST TYPE — DMND_DATA_RD (R/W)
RESET Value — 00000000_00000000H20-26 Vol. 3BPERFORMANCE MONITORING
20.3.1.2  Performance Monito ring Facility in the Uncore
The “uncore” in Nehalem microarchitecture refers to subsys tems in the physical processor package that are shared 
by multiple processor cores. Some of the sub-systems in the uncore include the L3 cache, Intel QuickPath Intercon-
nect link logic, and integrated memory controller. The perf ormance monitoring facilities inside the uncore operates 
in the same clock domain as the uncore (U-clock domain), which is usually different from the processor core clock 
domain. The uncore performance monitoring facilities describ ed in this section apply to Intel Xeon processor 5500 
series and processors with the following CPUID sign atures: 06_1AH, 06_1EH, 06_1FH (see Chapter 2, “Model-
Specific Registers (MSRs),” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4). An 
overview of the uncore performance monitoring facilities is described separately. 
The performance monitoring facilities available in the U-clock domain consist of:
•Eight General-purpose counters (MSR_UNCORE_PerfCn tr0 through MSR_UNCORE_PerfCntr7). The counters 
are 48 bits wide. Each counter is associated with a configuration MSR, MSR_UNCORE_PerfEvtSelx, to specify 
event code, event mask and other event qualification fields. A set of global un core performance counter 
enabling/overflow/status control MSRs are also provided for software.
•Performance monitoring in the uncore provides an addre ss/opcode match MSR that provides event qualification 
control based on address value or QPI command opcode.
•One fixed-function counter, MSR_UNCORE_FixedCntr0. Th e fixed-function uncore counter increments at the 
rate of the U-clock when enabled.
The frequency of the uncore clock domain can be determined from the uncore clock ratio which is available in 
the PCI configuration space register at offset  C0H under device number 0 and Function 0. 
20.3.1.2.1  Uncore Performance Monitoring Management Facility
MSR_UNCORE_PERF_GLOBAL_CTRL provides bit fields to enable/disable general-pu rpose and fixed-function 
counters in the uncore. Figure 20-19 shows the layout of MSR_UNCORE_PERF_GLOBAL_CTRL for an uncore that is 
shared by four processor cores in a physical package. 
•EN_PCn (bit n, n = 0, 7): When set, enables coun ting for the general-purpose uncore counter MSR_UN-
CORE_PerfCntr n.
•EN_FC0 (bit 32): When set, enables counting for the fixed-function uncore counter MSR_UNCORE_FixedCntr0.
•EN_PMI_COREn (bit n, n = 0, 3 if four cores are present ): When set, processor core n is programmed to receive 
an interrupt signal from any interrupt enabled uncore counter. PMI delivery due to an uncore counter overflow 
is enabled by setting IA32_DEBUGCTL.Offcore_PMI_EN to 1.
•PMI_FRZ (bit 63): When set, all U-clock uncore counters are disabled when any one of them signals a performance interrupt. Software must explicitly re-enabl e the counter by setting th e enable bits in MSR_UN-
CORE_PERF_GLOBAL_CTRL upon exit from the ISR.NON_DRAM 15 Non-DRAM requests that were serviced by IOH.Table 20-6.  MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 Bit Field Definition (Contd.)
Bit Name Offset DescriptionVol. 3B 20-27PERFORMANCE MONITORING
MSR_UNCORE_PERF_GLOBAL_STATUS provides overflow st atus of the U-clock performance counters in the 
uncore. This is a read-only register. If an overflow status bit is set the corresponding counter has overflowed. The 
register provides a condition change bit (bit 63) which can be quickly checked by software to determine if a signif-
icant change has occurred since the last time the condition change status was cleared. Figure 20-20 shows the layout of MSR_UNCORE_PERF_GLOBAL_STATUS.
•OVF_PCn (bit n, n = 0, 7): When set, indicates ge neral-purpose uncore counter MSR_UNCORE_PerfCntr n has 
overflowed.

•OVF_FC0 (bit 32): When set, indicates the fixed-function uncore counter MSR_UNCORE_FixedCntr0 has 
•OVF_PMI (bit 61): When set indicates that an uncore co unter overflowed and generated an interrupt request. 
•CHG (bit 63): When set indicates that at least one st atus bit in MSR_UNCORE_PERF_GLOBAL_STATUS register 
has changed state.
MSR_UNCORE_PERF_GLOBAL_OVF_CTRL allows software to clear the status bits in the UNCORE_PERF_-
GLOBAL_STATUS register. This is a write-only register, and in dividual status bits in the global status register are 
cleared by writing a binary one to the corresponding bit in this register. Writing zero to any bit position in this 
register has no effect on the uncore PMU hardware. Figure 20-19.  Layout of MSR_UNCORE_PERF_GLOBAL_CTRL MSR PMI_FRZ (R/W)
EN_PMI_CORE3 (R/W)
EN_PMI_CORE2 (R/W)EN_PMI_CORE1 (R/W)87 0
EN_PMI_CORE0 (R/W)32 3 48 1
Reserved63 2 4 31 56 62 49 5051
EN_PC7 (R/W)
EN_PC6 (R/W)
EN_PC5 (R/W)EN_PC4 (R/W)
EN_PC3 (R/W)
EN_PC2 (R/W)EN_PC1 (R/W)
EN_PC0 (R/W)EN_FC0 (R/W)
RESET Value — 00000000_00000000H20-28 Vol. 3BPERFORMANCE MONITORING
Figure 20-21 shows the layout of MSR_UNCORE_PERF_GLOBAL_OVF_CTRL.
•CLR_OVF_PCn (bit n, n = 0, 7): Set this bit to clear the overflow status for general-purpose uncore counter 
MSR_UNCORE_PerfCntr n. Writing a value other than 1 is ignored.
•CLR_OVF_FC0 (bit 32): Set this bit to clear the overflow  status for the fixed-function uncore counter MSR_UN-
CORE_FixedCntr0. Writing a value other than 1 is ignored.
•CLR_OVF_PMI (bit 61): Set this bit to clear the OVF_ PMI flag in MSR_UNCORE_PERF_GLOBAL_STATUS. Writing 
a value other than 1 is ignored.
•CLR_CHG (bit 63): Set this bit to clear the CHG flag  in MSR_UNCORE_PERF_GLOBAL_STATUS register. Writing 
20.3.1.2.2  Uncore Performanc e Event Configuration Facility
MSR_UNCORE_PerfEvtSel0 through MSR_UNCORE_PerfEvt Sel7 are used to select performance event and 
configure the counting behavior of the respective uncor e performance counter. Each uncore PerfEvtSel MSR is 
paired with an uncore performance counter. Each uncor e counter must be locally configured using the corre-Figure 20-20.  Layout of MSR_UNCORE_PERF_GLOBAL_STATUS MSR 
Figure 20-21.  Layout of MSR_UNCORE_PERF_GLOBAL_OVF_CTRL MSR CHG (R/W)
OVF_PC7 (R/O)
OVF_PC6 (R/O)OVF_PC5 (R/O)OVF_PC4 (R/O)
OVF_PC2 (R/O)
OVF_PC1 (R/O)OVF_PC0 (R/O)OVF_FC0 (R/O)
RESET Value — 00000000_00000000H
CLR_CHG (WO1)
CLR_OVF_PMI (WO1)87 0 32 31
CLR_OVF_PC7 (WO1)
CLR_OVF_PC6 (WO1)CLR_OVF_PC5 (WO1)CLR_OVF_PC4 (WO1)
CLR_OVF_PC3 (WO1)
CLR_OVF_PC2 (WO1)
CLR_OVF_PC1 (WO1)CLR_OVF_PC0 (WO1)CLR_OVF_FC0 (WO1)
RESET Value — 00000000_00000000HVol. 3B 20-29PERFORMANCE MONITORING
sponding MSR_UNCORE_PerfEvtSelx and counting must be enabled using the respective EN_PCx bit in MSR_UN-
CORE_PERF_GLOBAL_CTRL. Figure 20-22 shows the layout of MSR_UNCORE_PERFEVTSELx.
•Event Select (bits 7:0): Selects the event logic unit used to detect uncore events.
•Unit Mask (bits 15:8) : Condition qualifiers for the ev ent selection logic specified in the Event Select field.
•OCC_CTR_RST (bit17): When set causes the queue occupanc y counter associated with this event to be cleared 
(zeroed). Writing a zero to this bit will be ignored. It will always read as a zero. 
•Edge Detect (bit 18): When set causes the counter to increment when a deasserted to asserted transition 
occurs for the conditions that can be expressed by any of the fields in this register.
•PMI (bit 20): When set, the uncore will generate an interrupt request when this counter overflowed. This 
request will be routed to the logical processors as enabled in the PMI enable bits (EN_PMI_COREx) in the 
register MSR_UNCORE_PERF_GLOBAL_CTRL.
•EN (bit 22): When clear, this counter is locally disabled . When set, this counter is locally enabled and counting 
starts when the corresponding EN_PCx bi t in MSR_UNCORE_PERF_GLOBAL_CTRL is set.
•INV (bit 23): When clear, the Counter Mask field is in terpreted as greater than or equal to. When set, the 
Counter Mask field is interpreted as less than.
•Counter Mask (bits 31:24): When this field is clear, it has no effect on counting. When set to a value other than 
zero, the logical processor compares this field to the even t counts on each core clock cycle. If INV is clear and 
the event counts are greater than or equal to this field, the counter is incremented by one. If INV is set and the 
event counts are less than this field, the counter is in cremented by one. Otherwise the counter is not incre-
mented.
Figure 20-23 shows the layout of MSR_UNCORE_FIXED_CTR_CTRL.
•EN (bit 0): When clear, the uncore fixed-function counter is locally disabled. When set, it is locally enabled and 
counting starts when the EN_FC0 bit in  MSR_UNCORE_PERF_GLOBAL_CTRL is set.
•PMI (bit 2): When set, the uncore will generate an interrupt request when the uncore fixed-function counter 
overflowed. This request will be routed to the logi cal processors as enabled in the PMI enable bits 
(EN_PMI_COREx) in the register MSR_UNCORE_PERF_GLOBAL_CTRL.Figure 20-22.  Layout of MSR_UNCORE_PERFEVTSELx MSRs 
Figure 20-23.  Layout of MSR_UNCORE_FIXED_CTR_CTRL MSR 31
OCC_CTR_RST—Rest Queue Occ870
Event SelectCounter Mask 19 1618 1517 2021222324
ReservedUnit Mask (UMASK)(CMASK)63
PMI—Enable PMI on overflow
87 0 31
Reserved63 2 456
PMI - Generate PMI on overflow
EN - Enable
RESET Value — 00000000_00000000H20-30 Vol. 3BPERFORMANCE MONITORING
Both the general-purpose counters (MSR_UNCORE_PerfCn tr) and the fixed-function counter (MSR_UNCORE_-
FixedCntr0) are 48 bits wide. They support both count ing and interrupt based sampling usages. The event logic 
unit can filter event counts to specific regions of code  or transaction types incoming to the home node logic.
20.3.1.2.3  Uncore Address/Opcode Match MSR
The Event Select field [7:0] of MSR_UNCORE_PERFEVTSELx is used to select different uncore event logic unit. 
When the event “ADDR_OPCODE_MATCH” is selected in the Event Select field, software can filter uncore perfor-
mance events according to transaction address and certain transaction responses. The address filter and transac-
tion response filtering requires the use of MSR_UNCORE _ADDR_OPCODE_MATCH register. The layout is shown in 
Figure 20-24. 
•Addr (bits 39:3): The physical address to match if “Match Sel“ field is set to select address match. The uncore 
performance counter will increment if the lowest 40-bit incoming physical address (excluding bits 2:0) for a 
transaction request matches bits 39:3.
•Opcode (bits 47:40) : Bits 47:40 allow software to filter uncore transactions based on QPI link message class/packed header opcode. These bits are consists two sub-fields:
— Bits 43:40 specify the QPI packet header opcode.— Bits 47:44 specify the QPI message classes.
Table 20-7 lists the encodings supported in the opcode field.Figure 20-24.  Layout of MSR_UNCORE_ADDR_OPCODE_MATCH MSR 
Table 20-7.  Opcode Field Encoding  for MSR_UNCORE_ADDR_OPCODE_MATCH 
Opcode [43:40] QPI Message Class
Home Request
[47:44] = 0000BSnoop Response
[47:44] = 0001BData Response
[47:44] = 1110B
1
DMND_IFETCH 2 2
WB 3 3
PF_DATA_RD 4 4PF_RFO 5 5
PF_IFETCH 6 6
OTHER 7 7NON_DRAM 15 1560
MatchSel—Select addr/Opcode
Opcode—Opcode and Message320 40 39 4748
ReservedADDR63
ADDR—Bits 39:4 of physical address
RESET Value — 00000000_00000000HOpcodeVol. 3B 20-31PERFORMANCE MONITORING
•MatchSel (bits 63:61): Software specifies the matc h criteria according to the following encoding:
— 000B: Disable addr_opcode match hardware.
— 100B: Count if only the address field matches.— 010B: Count if only the opcode field matches.
— 110B: Count if either opcode field matches or the address field matches.
— 001B: Count only if both opcode and address field match.— Other encoding are reserved.
20.3.1.3  Intel® Xeon® Pr ocessor 7500 Series Performance Monitoring Facility
The performance monitoring facility in the processor core of Intel® Xeon® processor 7500 series are the same as 
those supported in Intel Xeon processor 5500 series. The uncore subsystem in Intel Xeon processor 7500 series 
are significantly different The uncore performance monitoring facility consist of many distributed units associated 
with individual logic control units (referred to as boxes) within the uncore subsystem. A high level block diagram of 
the various box units of the uncore is shown in Figure 20-25.
Uncore PMUs are programmed via MSR interfaces. Each of the distributed uncore PMU units have several general-
purpose counters. Each counter requires an associated event select MSR, and may require additional MSRs to 
configure sub-event conditions. The uncore PMU MSRs associ ated with each box can be categorized based on its 
functional scope: per-counter, per-box, or global across the uncore. The number counters available in each box

functional scope: per-counter, per-box, or global across the uncore. The number counters available in each box 
type are different. Each box generally provides a set of MSRs to enable/disab le, check status/overflow of multiple 
counters within each box. 
Table 20-8 summarizes the number MSRs for uncore PMU for each box.Figure 20-25.  Distributed Units of the Uncore of Intel® Xeon® Processor 7500 SeriesPBoxL3 Cache
PBox PBox PBoxUBox WBoxRBox BBox BBox MBox MBox PBox PBoxSBox SBoxCBox CBox CBox CBox CBox CBox CBox CBox
4 Intel QPI LinksSMI Channels
SMI Channels20-32 Vol. 3BPERFORMANCE MONITORING
The W-Box provides 4 general-purpose counters, each requir ing an event select configuration MSR, similar to the 
general-purpose counters in other boxes. There is also a fixed-function counter that increments clockticks in the 
uncore clock domain. 
For C,S,B,M,R, and W boxes, each box provides an MSR to  enable/disable counting, co nfiguring PMI of multiple 
counters within the same box, this is somewhat simila r the “global control“ progra mming interface, IA32_PERF_-
GLOBAL_CTRL, offered in the core PMU. Similarly status information and counter overflow control for multiple 
counters within the same box are also provided in C,S,B,M,R, and W boxes.
In the U-Box, MSR_U_PMON_GLOBAL_CTL provides over all uncore PMU enable/disab le and PMI configuration 
control. The scope of status information in the U-box is at per-box granularity, in contrast to the per-box status 
information MSR (in the C,S,B,M,R, and W boxes) providing status information of individual counter overflow. The 
difference in scope also apply to the overflow cont rol MSR in the U-Box versus those in the other Boxes.
The individual MSRs that provide uncore PMU interfaces are listed in Chapter 2, “Model-Specific Registers (MSRs),” 
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, Table 2-17 under the general 
naming style of MSR_%box#%_PMON_%scope_function%, wh ere %box#% designates the type of box and zero-
based index if there are more the one box of the same type, %scope_function% follows the examples below:
•Multi-counter enabling MSRs: MSR_U_PMON_GLOBAL_CTL, MSR_S0_PMON_BOX_CTL, MSR_C7_PMON_-
BOX_CTL, etc.
•Multi-counter status MSRs: MSR_U_PMON_GLOBAL_STATUS, MSR_S0_PMON_BOX_STATUS, MSR_C7_P-MON_BOX_STATUS, etc.
•Multi-counter overflow control MSRs: MSR_U_PMON_GLOBAL_OVF_CTL, MSR_S0_PMON_BOX_OVF_CTL, 
MSR_C7_PMON_BOX_OVF_CTL, etc.
•Performance counters MSRs: the scope is implicitly  per counter, e.g., MSR_U_PMON_CTR, MSR_S0_P-
MON_CTR0, MSR_C7_PMON_CTR5, etc.
•Event select MSRs: the scope is implicitly pe r counter, e.g., MSR_U_PMON_EVNT_SEL, MSR_S0_P-
MON_EVNT_SEL0, MSR_C7_PMON_EVNT_SEL5, etc.
•Sub-control MSRs: the scope is implicitly per-box gr anularity, e.g., MSR_M0_PMON_TIMESTAMP, MSR_R0_P-
MON_IPERF0_P1, MSR_S1_PMON_MATCH.
Details of uncore PMU MSR bit field definitions can be fo und in a separate document “Intel Xeon Processor 7500 
Series Uncore Performance Monitoring Guide“.
20.3.2 Performance Monitoring for Proces sors Based on Westmere Microarchitecture
All of the performance monitoring prog ramming interfaces (architectural and non-architectural core PMU facilities, 
and uncore PMU) described in Section 20.6.3 also apply to processors based on Westmere microarchitecture. 
Table 20-5 describes a non-architectural performance mo nitoring event (event code 0B7H) and associated 
MSR_OFFCORE_RSP_0 (address 1A6H) in the core PMU. This  event and a second functionally equivalent offcore Table 20-8.  Uncore PMU MSR Summary
Box # of Boxes Counters per BoxCounter 
WidthGeneral 
PurposeGlobal 
Enable Sub-control MSRs
C-Box 8 6 48 Yes per-box None
S-Box 2 4 48 Yes per-box Match/MaskB-Box 2 4 48 Yes per-box Match/Mask
M-Box 2 6 48 Yes per-box Yes
R-Box 1 16 ( 2 port, 8 per port) 48 Yes per-box YesW-Box 1 4 48 Yes per-box None
14 8 N o p e r - b o x N o n e
U-Box 1 1 48 Yes uncore NoneVol. 3B 20-33PERFORMANCE MONITORING
response event using event code 0BBH and MSR_OFFCOR E_RSP_1 (address 1A7H) are supported in processors 
based on Westmere microarchitecture. The event code an d event mask definitions of non-architectural perfor-
mance monitoring events can be found at: https://perfmon-events.intel.com/ . 
The load latency facility is the same as described in Section 20.3.1.1.2, but added enhancement to provide more 
information in the data source encoding field of each lo ad latency record. The additional information relates to 
STLB_MISS and LOCK, see Table 20-13.
20.3.3 Intel ® Xeon ® Processor E7 Family Performance Monitoring Facility
The performance monitoring facility in the processor core of the Intel® Xeon® processor E7 family is the same as 
those supported in the Intel Xeon processor 5600 series3. The uncore subsystem in the Intel Xeon processor E7 
family is similar to those of the Intel Xeon processor 7500 series. The high level construction of the uncore sub-
system is similar to that shown in Figure 20-25, with th e additional capability that up to 10 C-Box units are 
Table 20-9 summarizes the number MSRs for uncore PMU for each box.
Details of the uncore performance monitoring facility of Inte l Xeon Processor E7 family is available in the “Intel® 
Xeon® Processor E7 Uncore Performance Monitoring Programming Reference Manual”.
20.3.4 Performance Monitoring for Processors  Based on Sandy Bridge Microarchitecture
Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series, and Intel® Xeon® processor 
E3-1200 family are based on Sandy Bridge microarchitect ure; this section describes the performance monitoring 
facilities provided in the processor core. The core PMU supports architectural performance monitoring capability 
with version ID 3 (see Section 20.2.3) and a host of non-architectural monitoring capabilities. 
Architectural performance monitoring version 3 capabilities are described in Section 20.2.3. 
The core PMU’s capability is similar to those described in Section 20.3.1.1 and Section 20.6.3, with some differ-
ences and enhancements relative to Westmere microarchitecture summarized in Table 20-10.
3. Exceptions are indicated for event code 0FH in the event list for this processor ( https://perfmon-events.intel.com/ ); and valid 
bits of data source encodi ng field of each load la tency record is limited to  bits 5:4 of Table 20-13.Table 20-9.  Uncore PMU MSR Summary for Intel® Xeon® Processor E7 Family
C-Box 10 6 48 Yes per-box None
U-Box 1 1 48 Yes uncore None20-34 Vol. 3BPERFORMANCE MONITORING
20.3.4.1  Global Counter Control Facili ties in Sandy Bridge Microarchitecture
The number of general-purpose performance counters visible to a logical processor can vary across Processors 
based on Sandy Bridge microarchitecture. Software must use CPUID to determine the number performance 
counters/event select registers (See Section 20.2.1.1). Table 20-10.  Core PMU Comparison
Box Sandy Bridge Microarchitectur e Westmere Microarchitecture Comment
# of Fixed counters per 
thread3 3 Use CPUID to determine # of 
counters. See Section 20.2.1.
# of general-purpose 
counters per core8 8 Use CPUID to determine # of 
Counter width (R,W) R:48, W: 32 /48 R:48, W:32 See Section 20.2.2.
# of programmable counters 
per thread4 or (8 if a core not shared by two 
threads)4 Use CPUID to determine # of 
PMI Overhead Mitigation • Freeze_Perfmon_on_PMI with 
legacy semantics.
• Freeze_LBR_on_PMI with legacy 
semantics for branch profiling.
• Freeze_while_SMM.•F r e e z e _ P e r f m o n _ o n _ P M I  
with legacy semantics.
• Freeze_LBR_on_PMI with 
legacy semantics for branch 
profiling.
• Freeze_while_SMM.See Section 18.4.7.
Processor Event Based 
Sampling (PEBS) EventsSee Table 20-12 . See Table 20-84 . IA32_PMC4-IA32_PMC7 do 
not support PEBS.
PEBS-Load Latency See Section 20.3.4.4.2;
• Data source encoding
• STLB miss encoding• Lock transaction encodingData source encoding 
PEBS-Precise Store Section 20.3.4.4.3 No
PEBS-PDIR Yes (using precise 
INST_RETIRED.ALL).No
Off-core Response Event MSR 1A6H and 1A7H, extended 
request and re sponse types.MSR 1A6H and 1A7H, limited 
response types.Nehalem supports 1A6H 
only.
Figure 20-26.  IA32_PERF_GLOBAL_CTRL MSR in Sandy Bridge MicroarchitectureFIXED_CTR2 enable
FIXED_CTR1 enable
FIXED_CTR0 enable
PMC7_EN (if PMC7 present)210
PMC6_EN (if PMC6 present)3132333435
PMC5_EN (if PMC5 present)
PMC4_EN (if PMC4 present)
PMC3_EN
PMC2_EN
PMC1_EN
Valid if CPUID.0AH:EAX[15:8] = 8, else reserved.PMC0_EN87 65 43Vol. 3B 20-35PERFORMANCE MONITORING
Figure 20-44 depicts the layout of IA32_PERF_GLOBAL_ CTRL MSR. The enable bits (PMC4_EN, PMC5_EN, 
PMC6_EN, PMC7_EN) corresponding to IA32_PMC4-IA32_P MC7 are valid only if CPUID.0AH:EAX[15:8] reports a

only.
PMC3_EN
PMC2_EN
PMC1_EN
PMC6_EN, PMC7_EN) corresponding to IA32_PMC4-IA32_P MC7 are valid only if CPUID.0AH:EAX[15:8] reports a 
value of ‘8’. If CPUID.0AH:EAX[15:8] = 4, attempts to set the invalid bits will cause #GP. 
Each enable bit in IA32_PERF_GLOBAL_CTRL is AND’ed with th e enable bits for all privilege levels in the respective 
IA32_PERFEVTSELx or IA32_PERF_FIXED_CTR_CTRL MSRs to start/stop the counting of respective counters. 
Counting is enabled if the AND’ed results is true; counting is disabled when the result is false.
IA32_PERF_GLOBAL_STATUS MSR provides single-bit status used by software to query the overflow condition of 
each performance counter. IA32_PERF_GLOBAL_STATUS[bit 62] indicates overflow conditions of the DS area data 
buffer (see Figure 20-27). A value of 1 in each bit of the PMCx_OVF field indicates an overflow condition has 
occurred in the associated counter. 
When a performance counter is configured for PEBS, an overflow condition in the counter will arm PEBS. On the 
subsequent event following overflow, the processor will gene rate a PEBS event. On a PE BS event, the processor will 
perform bounds checks based on the parameters defined in the DS Save Area (see Section 18.4.9). Upon 
successful bounds checks, the processor will store the data record in the defined buffer area, clear the counter overflow status, and reload the counter. If the bounds checks  fail, the PEBS will be skipped entirely. In the event 
that the PEBS buffer fills up, the processor will  set the OvfBuffer bit in MSR_PERF_GLOBAL_STATUS.
IA32_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow the indicators for general-purpose or fixed-
function counters via a single WRMSR (see Figure 20-28). Clear overflow indications when:
•Setting up new values in the event select and/or UMASK field for counting or interrupt based sampling.
•Reloading counter values to continue sampling.
•Disabling event counting or interrupt based sampling.Figure 20-27.  IA32_PERF_GLOBAL_STATUS MSR in Sandy Bridge Microarchitecture62
FIXED_CTR2 Overflow (RO)
FIXED_CTR1 Overflow (RO)
FIXED_CTR0 Overflow (RO)
PMC7_OVF (RO, If PMC7 present)210
PMC6_OVF (RO, If PMC6 present)3132333435
CondChgd
Ovf_DSBuffer87 65 4 3
PMC5_OVF (RO, If PMC5 present)
PMC4_OVF (RO, If PMC4 present)
PMC3_OVF (RO)
PMC2_OVF (RO)
PMC1_OVF (RO)
PMC0_OVF (RO)
Valid if CPUID.0AH:EAX[15:8] = 8; else reservedOvf_UncorePMU6120-36 Vol. 3BPERFORMANCE MONITORING
20.3.4.2  Counter Coalescence
In processors based on Sandy Bridge microarchitecture, each processor core implements eight general-purpose 
counters. CPUID.0AH:EAX[15:8] will report the number of counters visible to software. 
If a processor core is shared by two logical processors, each logical processors can access up to four counters 
(IA32_PMC0-IA32_PMC3). This is the same as in the prior generation for processors based on Nehalem microarchi-
tecture.
If a processor core is not shared by two logical processo rs, up to eight general-purpose counters are visible. If 
CPUID.0AH:EAX[15:8] reports 8 counters, then IA32_P MC4-IA32_PMC7 would occupy MSR addresses 0C5H 
through 0C8H. Each counter is accompanied by an ev ent select MSR (IA32_PERFEVTSEL4-IA32_PERFEVTSEL7).
If CPUID.0AH:EAX[15:8] report 4, access to IA32_P MC4-IA32_PMC7, IA32_PMC4-IA32_PMC7 will cause #GP. 
Writing 1’s to bit position 7:4 of IA32_PERF_GLOBAL_CTRL, IA32_PERF_GLOBAL_STATUS, or IA32_PERF_-GLOBAL_OVF_CTL will also cause #GP.
20.3.4.3  Full Width Writes  to Performance Counters
Processors based on Sandy Bridge microarchitecture supp ort full-width writes to the general-purpose counters, 
IA32_PMCx. Support of full-width writes are enumer ated by IA32_PERF_CAPABILITIES.FW_WRITES[13] (see 
Section 20.2.4).
The default behavior of IA32_PMCx is unchanged, i.e., WRMSR to IA32_PMCx results in a sign-extended 32-bit 
value of the input EAX written into IA32_PMCx. Full-wid th writes must issue WRMSR to a dedicated alias MSR 
address for each IA32_PMCx.
Software must check the presence of full-width write ca pability and the presence of the alias address IA32_A_PMCx 
by testing IA32_PERF_CAPABILITIES[13].
20.3.4.4  PEBS Support in Sandy Bridge Microarchitecture
Processors based on Sandy Bridge microarchitecture supp ort PEBS, similar to those of fered in prior generation, 
with several enhanced features. The key components and di fferences of PEBS facility relative to Westmere microar-
chitecture is summarized in Table 20-11.Figure 20-28.  IA32_PERF_GLOBAL_OVF_CTR L MSR in Sandy Bridge Microarchitecture62
FIXED_CTR2 ClrOverflow
FIXED_CTR1 ClrOverflow
FIXED_CTR0 ClrOverflow
PMC7_ClrOvf (if PMC7 present)21 0
PMC6_ClrOvf (if PMC6 present)3132333435
ClrOvfDSBuffer87 65 43
PMC5_ClrOvf (if PMC5 present)
PMC4_ClrOvf (if PMC4 present)
PMC3_ClrOvf
PMC2_ClrOvf
PMC1_ClrOvf
PMC0_ClrOvf
Valid if CPUID.0AH:EAX[15:8] = 8; else reservedClrOvfUncoreVol. 3B 20-37PERFORMANCE MONITORING
Only IA32_PMC0 through IA32_PMC3 support PEBS. 
NOTE
In a PMU with PDIR capability, PE BS behavior is unpredictable if  IA32_PERFEVTSELx or IA32_PMCx 
is changed for a PEBS-enabled counter while an event is being counted. To avoid this, changes to 
the programming or value of a PEBS-enabled coun ter should be performed when the counter is 
disabled.
In IA32_PEBS_ENABLE MSR, bit 63 is defined as PS_ENA BLE: When set, this enables IA32_PMC3 to capture 
precise store information. Only IA32_PMC3 supports the pr ecise store facility. In typical usage of PEBS, the bit 
fields in IA32_PEBS_ENABLE are written to when the agent software starts PEBS operation; the enabled bit fields 
should be modified only when re-programming another PEBS event or cleared when the agent uses the perfor-
mance counters for non-PEBS operations. Table 20-11.  PEBS Facility Comparison
Valid IA32_PMCx PMC0-PMC3 PMC0 -PMC3 No PEBS on PMC4-PMC7.
PEBS Buffer Programming  Section 20.3.1.1.1 Section 20.3.1.1.1 Unchanged
IA32_PEBS_ENABLE 
Layout Figure 20-29 Figure 20-15
PEBS record layout Physical Layout same as 
Table 20-3.Table 20-3 Enhanced fields at offsets 
98H, A0H, A8H.
PEBS Events See Table 20-12. See Table 20-84. IA32_PMC4-IA32_PMC7 do 
PEBS-Load Latency See Table 20-13. Table 20-4
PEBS-Precise Store Yes; see Sect ion 20.3.4.4.3. No IA32_PMC3 only
PEBS-PDIR Yes No IA32_PMC1 onlyPEBS skid from EventingIP 1 (or 2 if micro+macro fusion) 1
SAMPLING Restriction Small SAV(CountDown) value incur higher overhead than prior 
generation.20-38 Vol. 3BPERFORMANCE MONITORING
20.3.4.4.1  PEBS Record Format
The layout of PEBS records physically identical to those sh own in Table 20-3, but the fiel ds at offsets 98H, A0H, and 
A8H have been enhanced to support  additional PEBS capabilities.
•Load/Store Data Linear Address (Offset 98H): This field will contain the linear address of the source of the load, 
or linear address of the destination of the store.
•Data Source /Store Status (Offset A0H): When load late ncy is enabled, this field will contain three piece of 
information (including an encoded value indicating the source which satisfied the load operation). The source 
field encodings are detailed in Table 20-4. When precise store is enabled, this field will contain information 
indicating the status of the store, as detailed in Table 19.
•Latency Value/0 (Offset A8H): When load latency is enabled, this field contains the latency in cycles to service 
the load. This field is not meaningful when precise store is enabled and will be written to zero in that case. Upon 
writing the PEBS record, microcode clears the overflow  status bits in the IA32_PERF_GLOBAL_STATUS corre-
sponding to those counters that both overflowed and were enabled in the IA32_PEBS_ENABLE register. The 
status bits of other counters remain unaffected.
The number PEBS events has expanded. The list of PEBS events supported in Sandy Bridge microarchitecture is 
shown in Table 20-12.Figure 20-29.  Layout of IA32_PEBS_ENABLE MSR 
Table 20-12.  PEBS Perf ormance Events for Sandy Bridge Microarchitecture
Event Name Event Select Sub-event UMask
INST_RETIRED C0H PREC_DIST 01H1
UOPS_RETIRED C2H All 01H
Retire_Slots 02H
BR_INST_RETIRED C4H Conditional 01H
Near_Call 02HAll_branches 04HNear_Return 08HNear_Taken 20H
BR_MISP_RETIRED C5H Conditional 01H
Near_Call 02HAll_branches 04HNot_Taken 10HTaken 20HLL_EN_PMC3 (R/W)
RESET Value — 00000000_00000000H62
PS_EN (R/W)Vol. 3B 20-39PERFORMANCE MONITORING
20.3.4.4.2  Load Latency Performance Monitoring Facility
The load latency facility in Sandy Bridge microarchitecture is similar to that in prior microarchitectures. It provides 
software a means to characterize the average load latency to different levels of cache/memory hierarchy. This

software a means to characterize the average load latency to different levels of cache/memory hierarchy. This 
facility requires processor supporting enhanced PEBS record format in the PEBS buffer, see Table 20-3 and Section 
20.3.4.4.1. This field measures the load latency from load 's first dispatch of till final data writeback from the 
memory subsystem. The latency is reported for retired dema nd load operations and in core cycles (it accounts for 
re-dispatches).
•One of the IA32_PERFEVTSELx MSR is pr ogrammed to specify the event unit MEM_TRANS_RETIRED , and the 
LATENCY_ABOVE_THRESHOLD event mask must be spec ified (IA32_PerfEvtSelX[15:0] = 1CDH). The corre-
0. Writing other values will result in undefined behavior. 
programmed with the 64-bit value 00000001.00000001H.
•When Load latency event is enabled, no other PE BS event can be configured with other counters.
updated internally. The MEM_TRANS_RETIRE D event for load latency counts only tagged retired loads. If a load is 
cancelled it will not be counted and the internal state of the load latency facility will not be updated. In this case the 
hardware will tag the next available load.MEM_UOPS_RETIRED D0H STLB_MISS_LOADS 11H
STLB_MISS_STORE 12HLOCK_LOADS 21HSPLIT_LOADS 41HSPLIT_STORES 42HALL_LOADS 81HALL_STORES 82H
MEM_LOAD_UOPS_RETIRED D1H L1_Hit 01H
L2_Hit 02HL3_Hit 04HHit_LFB 40H
MEM_LOAD_UOPS_LLC_HIT_RETIRED D2H XSNP_Miss 01H
XSNP_Hit 02HXSNP_Hitm 04HXSNP_None 08H
NOTES:
1. Only available on IA32_PMC1.Table 20-12.  PEBS Performance Events for Sandy Bridge Microarchitecture (Contd.)
Event Name Event Select Sub-event UMask20-40 Vol. 3BPERFORMANCE MONITORING
number of tagged loads with latency info rmation that will be written into the PE BS record field by the PEBS assists. 
The load latency data written to the PEBS record will be fo r the last tagged load operation which retired just before 
The physical layout of the PEBS records is the same as sh own in Table 20-3. The specific ity of Data Source entry at 
offset A0H has been enhanced to report three pieces of information. 
The layout of MSR_PEBS_LD_LAT_THRESHOLD is the same as shown in Figure 20-17.
20.3.4.4.3  Precise Store Facility
Processors based on Sandy Bridge microarchitecture offer a precise store capability that complements the load 
latency facility. It provides a means to profile store memory references in the system.
Precise stores leverage the PEBS faci lity and provide additional information about sampled stores. Having precise 
memory reference events with linear address information for both loads and stores can help programmers improve 
data structure layout, eliminate remote node references , and identify cache-line conflicts in NUMA systems.
Only IA32_PMC3 can be used to capture precise store inform ation. After enabling this facility, counter overflows will 
initiate the generation of PEBS records as previously de scribed in PEBS. Upon counter overflow hardware captures 
the linear address and other status information of the next st ore that retires. This information is then written to the 
PEBS record.
To enable the precise store facility, software must complete  the following steps. Please note that the precise store 
facility relies on the PEBS facility, so the PEBS configurat ion requirements must be completed before attempting to 
capture precise store information.
•Complete the PEBS configuration steps.
•Program the MEM_TRANS_RETIRED.PRECISE_STORE event in IA32_PERFEVTSEL3. Only counter 3 
(IA32_PMC3) supports collection of precise store information. 
•Set IA32_PEBS_ENABLE[3] and IA32_PEBS_ENABLE[63]. This enables IA32_PMC3 as a PEBS counter and 
enables the precise store facility, respectively.
The precise store information written into a PEBS record a ffects entries at offsets 98H, A0H, and A8H of Table 20-3. 
The specificity of Data Source entry at offset A0H has been enhanced to report three piece of information. Table 20-13.  Layout of Data So urce Field of Load Latency Record
Field Position Description
Source 3:0 See Table 20-4
STLB_MISS 4 0: The load did not miss the STLB (hit the DTLB or STLB).
1: The load missed the STLB.
Lock 5 0: The load was not part of a locked transaction.
1: The load was part of  a locked transaction.
Reserved 63:6 ReservedVol. 3B 20-41PERFORMANCE MONITORING
20.3.4.4.4  Precise Distribution of Instructions Retired (PDIR) 
Upon triggering a PEBS assist, there will be a finite de lay between the time the counter overflows and when the 
microcode starts to carry out its data collection obligations.  INST_RETIRED is a very common event that is used to 
sample where performance bottleneck happened and to help id entify its location in instruction address space. Even 
if the delay is constant in core clock space, it invariably  manifest as variable “skids” in instruction address space. 
This creates a challenge for programmers to profile a workload and pinpoint the location of bottlenecks.
The core PMU in processors based on Sandy Bridge microarchitecture include a facility referred to as precise distri-
bution of Instruction Retired (PDIR). 
The PDIR facility mitigates the “skid” problem by providin g an early indication of when the INST_RETIRED counter 
is about to overflow, allowing the machine to more prec isely trap on the instruction that actually caused the 
counter overflow. On processors based on Sandy Bridge micr oarchitecture, skid is sign ificantly reduced and can be 
as little as one instruction. On future implementations, PDIR may eliminate skid.
PDIR applies only to the INST_RETIRED.ALL precise even t, and processors based on Sandy Bridge microarchitec-
ture must use IA32_PMC1 with PerfEvtSel1 property conf igured and bit 1 in the IA32_PEBS_ENABLE set to 1. 
INST_RETIRED.ALL is a non-architectural performance event,  it is not supported in prior generation microarchitec-
tures. Additionally, on processors with CPUID DisplayFam ily_DisplayModel signatures of 06_2A and 06_2D, the tool 
that programs PDIR should quiesce the rest of the pr ogrammable counters in the core when PDIR is active. 
20.3.4.5  Off-core Respon se Performanc e Monitoring 
The core PMU in processors based on Sandy Bridge microarchitecture provides off-core response facility similar to 
prior generation. Off-core response can be programmed only with a specific pair of event select and counter MSR, 
and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the off-core 
transaction. Two event codes are dedicated for off-core re sponse event programming. Ea ch event code for off-core 
response monitoring requires programming an associated configuration MSR, MSR_OFFCORE_RSP_x. Table 20-15 
lists the event code, mask value and additional off-core configuration MSR that must be programmed to count off-
core response events using IA32_PMCx. 
The layout of MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RS P_1 are shown in Figure 20-30 and Figure 20-31. Bits 
15:0 specifies the request type of a transaction request to  the uncore. Bits 30:16 specifies supplier information, 
bits 37:31 specifies snoop response information.Table 20-14.  Layout of Precise Store Information In PEBS Record
Field Offset Description
Store Data 
Linear Address98H The linear address of th e destination of the store.
Store Status A0H L1D Hit (Bit 0): The store hit the data cach e closest to the core (lowest late ncy cache) if this bit is set, 
otherwise the store missed the data cache.

Store Data 
STLB Miss (bit 4): The store missed the STLB if set, otherwise the store hit the STLB
Locked Access  (bit 5): The store was part of a locked access if set, otherwise the store was not part of a 
locked access.
Reserved A8H Reserved
Table 20-15.  Off-Core Response Event Encoding
Counter Event code UMask Required Off-core Response MSR
PMC0-3 B7H 01H MSR_OFFCORE_RSP_0 (address 1A6H)
PMC0-3 BBH 01H MSR_OFFCORE_RSP_1 (address 1A7H)20-42 Vol. 3BPERFORMANCE MONITORING
Figure 20-30.  Request_Type Fields for MSR_OFFCORE_RSP_x 
Table 20-16.  MSR_OFFCORE_RSP_ x Request_Type Field Definition
DMND_DATA_RD 0 Counts the number of demand data reads of full and partial cachelines as well as demand data page 
table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.
DMND_RFO 1 Counts the number of demand and DCU prefetch  reads for ownership (RFO) requests generated by a 
write to data cacheline. Does not count L2 RFO prefetches.
DMND_IFETCH 2 Counts the number of demand instruction ca cheline reads and L1 instruction cacheline prefetches.
PF_LLC_DATA_RD 7 L2 prefetcher to L3 for loads.PF_LLC_RFO 8 RFO requests generated by L2 prefetcher 
PF_LLC_IFETCH 9 L2 prefetcher to L3 for instruction fetches.
BUS_LOCKS 10 Bus lock an d split lock requests
STRM_ST 11 Streaming store requests
OTHER 15 Any other request that crosses IDI, including I/O.RESPONSE TYPE — Other (R/W)
RESERVED 87 0
REQUEST TYPE — STRM_ST (R/W)11 312 1
REQUEST TYPE — BUS_LOCKS (R/W)
REQUEST TYPE — PF_LLC_IFETCH (R/W)REQUEST TYPE — PF_LLC_RFO (R/W)
REQUEST TYPE — PF_LLC_DATA_RD (R/W)
REQUEST TYPE — WB (R/W)REQUEST TYPE — DMND_IFETCH (R/W)
RESET Value — 00000000_00000000H37
See Figure 18-30Vol. 3B 20-43PERFORMANCE MONITORING
To properly program this extra register, software must se t at least one request type bit and a valid response type 
pattern. Otherwise, the event count reported will be zero. It  is permissible and useful to set multiple request and 
response type bits in order to obtain various classes of off-core response events . Although MSR_OFFCORE_RSP_x 
allow an agent software to program numerous combinations that meet the above guideline, not all combinations 
produce meaningful data.
To specify a complete offcore response filter, software must  properly program bits in the request and response type 
fields. A valid request type must have at least one bit set in the non-reserved bits of 15:0. A valid response type 
must be a non-zero value of the following expression:
ANY | [(‘OR’ of Supplier Info Bits) & (‘OR’ of Snoop Info Bits)]
If “ANY“ bit is set, the supplier and snoop info bits are ignored.Figure 20-31.  Response_Supplier and Sn oop Info Fields fo r MSR_OFFCORE_RSP_x 
Table 20-17.  MSR_OFFCORE_RSP_x Resp onse Supplier Info Field Definition
Subtype Bit Name Offset Description
Common Any 16 Catch all valu e for any response types.
Supplier 
InfoNO_SUPP 17 No Supplier Information available.
LLC_HITM 18 M-state initial lookup stat in L3.
LLC_HITE 19 E-stateLLC_HITS 20 S-state
LLC_HITF 21 F-state
LOCAL 22 Local DRAM Controller.Reserved 30:23 ReservedRESPONSE TYPE — NON_DRAM (R/W)
RSPNS_SNOOP — HITM (R/W)16
RSPNS_SNOOP — HIT_FWD33 1934 17
Reserved63 18 20 31 21 22 32 353637
RSPNS_SNOOP — HI T_NO_FWD (R/W)
RSPNS_SNOOP — SNP_MISS (R/W)RSPNS_SNOOP — SNP_NOT_NEEDED (R/W)RSPNS_SNOOP — SNPl_NONE (R/W)RSPNS_SUPPLIER — RESERVED
RSPNS_SUPPLIER — LLC_HITF (R/W)
RSPNS_SUPPLIER — LLC_HITS (R/W)RSPNS_SUPPLIER — LLC_HITE (R/W)
RSPNS_SUPPLIER — LLC_HITM (R/W)
RSPNS_SUPPLIER — No_SUPP (R/W)
RSPNS_SUPPLIER — ANY (R/W)
RESET Value — 00000000_00000000HRSPNS_SUPPLIER — Local20-44 Vol. 3BPERFORMANCE MONITORING
20.3.4.6  Uncore Performa nce Monitoring Facilities in the Intel® Core™ i7-2xx x, Intel® Core™ i5-2xxx, 
and Intel® Core™ i3 -2xxx Processor Series
The uncore sub-system in Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series 
provides a unified L3 that can support up to four processor cores. The L3 cache consists multiple slices, each slice 
interface with a processor via a coherence engine, referred to  as a C-Box. Each C-Box prov ides dedicated facility of 
MSRs to select uncore performance monitoring events and each C-Box event select MSR is paired with a counter register, similar in style as those described in Section 20.3.1.2.2. The ARB unit in the uncore also provides its local 
performance counters and event select MSRs. The layout of the event select MSRs in the C-Boxes and the ARB unit 
are shown in Figure 20-32.Table 20-18.  MSR_OFFCORE_RSP_ x Snoop Info Field Definition
Snoop 
InfoSNP_NONE 31 No details on snoop-related information.
SNP_NOT_NEEDED 32 No snoop was ne eded to satisfy the request.
SNP_MISS 33 A snoop was needed and it missed all snooped caches:
-For LLC Hit, ReslHitl was returned by all cores-For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM.
SNP_NO_FWD 34 A snoop was needed and it hits in at le ast one snooped cache. Hit denotes a cache-line was 
valid before snoop effect. This includes:
-Snoop Hit w/ Invalida tion (LLC Hit, RFO)
-Snoop Hit, Left Shared (L LC Hit/Miss, IF etch/Data_RD)
-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
In the LLC Miss case, data  is returned from DRAM.
SNP_FWD 35 A snoop was needed an d data was forwarded from a remote socket. This includes:
-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
HITM 36 A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was 
in modified state before effect as  a results of snoop. This includes:
-Snoop HitM w/ WB (LLC  miss, IFetch/Data_RD)
-Snoop Forward Modified w/ In validation (LLC Hit/Miss, RFO)
-Snoop MtoS (LLC Hit, IFetch/Data_RD).
NON_DRAM 37 Target was non-DRAM  system address. This in cludes MMIO transactions.
Figure 20-32.  Layout of Uncore PERFEV TSEL MSR for a C-Box Unit or the ARB Unit28
EN—Enable counter
E—Edge detect87 0
OVF_EN—Overflow forwarding
RESET Value — 00000000_00000000HVol. 3B 20-45PERFORMANCE MONITORING
The bit fields of the uncore event select MSRs for a C-box unit or the ARB unit are summarized below:
•Event_Select (bits 7:0) and UMASK (bits 15:8): Specifies the microarchitectural condition to count in a local 
uncore PMU counter, see the event list at: https://perfmon-events.intel.com/ .
•E (bit 18): Enables edge de tection filtering, if 1.
•OVF_EN (bit 20): Enables the overflow indicator fr om the uncore counter forwarded to MSR_UNC_PERF_-
GLOBAL_CTRL, if 1.
•EN (bit 22): Enables the local counter associated with this event select MSR.
•INV (bit 23): Event count increments with non-ne gative value if 0, with negated value if 1. 
•CMASK (bits 28:24): Specifies a positive threshold value to filter raw event count input.
At the uncore domain level, there is a master set of co ntrol MSRs that centrally manages all the performance moni-
toring facility of uncore units. Figure 20-33 shows the layout of the uncore domain global control. 
When an uncore counter overflows, a PMI can be rout ed to a processor core. Bits 3:0 of MSR_UNC_PERF_-
GLOBAL_CTRL can be used to select which processor core to handle the uncore PMI. Software must then write to 
bit 13 of IA32_DEBUGCTL (at addre ss 1D9H) to enable this capability.
•PMI_SEL_Core#: Enables the forwarding of an uncore PMI request to a processor core, if 1. If bit 30 (WakePMI) 
is ‘1’, a wake request is sent to the respec tive processor core prior to sending the PMI.
•EN: Enables the fixed uncore counter, the ARB counters, an d the CBO counters in the uncore PMU, if 1. This bit 
is cleared if bit 31 (FREEZE) is set and any enabled uncore counters overflow.
•WakePMI: Controls sending a wake request to any halted  processor core before issuing the uncore PMI request. 
If a processor core was halted and not sent a wake request, the uncore PMI will not be serviced by the processor core.
•FREEZE: Provides the capability to freeze all uncore counters when an overflow condition occurs in a unit 
counter. When this bit is set, and a counter overflow occurs, the uncore PMU logic will clear the global enable 
bit (bit 29).
Additionally, there is also a fixed counter, counting uncore clockticks, for the uncore domain. Table 20-19 summa-

rizes the number MSRs for uncore PMU for each box.Figure 20-33.  Layout of MSR_UNC_PERF_GLOBAL_CTRL MSR for Uncore
Table 20-19.  Uncore PMU MSR Summary
Box # of BoxesCounters per 
BoxCounter 
Enable Comment
C-Box SKU specific 2 44 Yes Per-box Up to 4, seeTable 2-21 
MSR_UNC_CBO_CONFIG
ARB 1 2 44 Yes UncoreFREEZE—Freeze counters
EN—Enable all uncore counters0 2829303132
WakePMI—Wake cores on PMI
RESET Value — 00000000_00000000H4321
PMI_Sel_Core3 — Uncore PMI to core 3
PMI_Sel_Core2 — Uncore PMI to core 2
PMI_Sel_Core1 — Uncore PMI to core 1
PMI_Sel_Core0 — Uncore PMI to core 020-46 Vol. 3BPERFORMANCE MONITORING
20.3.4.6.1  Uncore Performance Monitoring Events
There are certain restrictions on the uncore perf ormance counters in each C-Box. Specifically,
•Occupancy events are supported only with counter 0 but not counter 1.
•Other uncore C-Box events can be programmed with either counter 0 or 1.
The C-Box uncore performance events can collect performance characteristics of transactions initiated by 
processor core. In that respect, they are similar to vari ous sub-events in the OFFCORE_RESPONSE family of perfor-
mance events in the core PMU. Information such as data supplier locality (LLC HIT/MISS) and snoop responses can 
be collected via OFFCORE_RESPONSE and qualified on a per-thread basis. 
On the other hand, uncore performance event logic cannot associate its counts with the same level of per-thread 
qualification attributes as the core PMU events can. Th erefore, whenever similar event programming capabilities 
are available from both core PMU and uncore PMU, the re commendation is that utilizing the core PMU events may 
be less affected by artifacts, complex interactions and other factors.
20.3.4.7  Intel® Xeon® Pr ocessor E5 Family Perfor mance Monitoring Facility
The Intel® Xeon® Processor E5 Family (and Intel® Core™ i7-3930K Processor) are based on Sandy Bridge-E 
microarchitecture. While the processor cores share the same microarchitecture as those of the Intel® Xeon® 
Processor E3 Family and 2nd generation Intel Core i7-2xxx,  Intel Core i5-2xxx, Intel Co re i3-2xxx processor series, 
the uncore subsystems are different. An overview of the uncore performance monitoring facilities of the Intel Xeon 
processor E5 family (and Intel Core i7-3930K processor) is described in Section 20.3.4.8.
Thus, the performance monitoring facilities in the proce ssor core generally are the same as those described in 
Section 20.6.3 through Section 20.3 .4.5. However, the MSR_OFFCORE_RSP_0/MSR_OFFCORE_RSP_1 Response 
Supplier Info field shown in Table 20-17 applies to Intel Core Processors with CPUID signature of DisplayFami-ly_DisplayModel encoding of 06_2AH; Intel Xeon proces sor with CPUID signature of DisplayFamily_DisplayModel 
encoding of 06_2DH supports an additional field for re mote DRAM controller shown in Table 20-20. Additionally, 
there are some small differences in th e non-architectural performance monitori ng events (see event list available 
at: https://perfmon-events.intel.com/
).Fixed 
CounterN.A. N.A. 48 No Uncore
Table 20-20.  MSR_OFFC ORE_RSP_x Supplier Info Field Definitions
Common Any 16 Catch all value for any response types.
Supplier Info NO_SUPP 17 No Supplier Information available.
LLC_HITE 19 E-state
LLC_HITS 20 S-stateLLC_HITF 21 F-state
LOCAL 22 Local DRAM Controller.
Remote 30:23 Remote DRAM Controlle r (either all 0s or all 1s).Table 20-19.  Uncore PMU MSR Summary (Contd.)
Enable CommentVol. 3B 20-47PERFORMANCE MONITORING
20.3.4.8  Intel® Xeon® Proc essor E5 Family Uncore Performance Monitoring Facility
The uncore subsystem in the Intel Xeon processor E5-2600 pr oduct family has some similarities with those of the 
Intel Xeon processor E7 family. Within the uncore subsyste m, localized performance counter sets are provided at 
logic control unit scope. For example, each Cbox caching agent has a set of local performance counters, and the 
power controller unit (PCU) has its own local performance counters. Up to 8 C-Box units are supported in the 
uncore sub-system. 
Table 20-21 summarizes the uncore PMU facilities providing MSR interfaces.
Details of the uncore performance monitoring facility of In tel Xeon Processor E5 family is available in “Intel® 
Xeon® Processor E5 Uncore Performance Monitoring Programming Reference Manual”. The MSR-based uncore 
PMU interfaces are listed in Table 2-24.
20.3.5 3rd Generation Intel® Core™ Proc essor Performance Monitoring Facility
The 3rd generation Intel® Core™ processor family and Intel® Xeon® processor E3-1200v2 product family are 
based on the Ivy Bridge microarchitecture. The performanc e monitoring facilities in the processor core generally 
are the same as those described in Section 20.6.3 thro ugh Section 20.3.4.5. The no n-architectural performance 
monitoring events supported by the processor core can be found at: https://perfmon-events.intel.com/ .
20.3.5.1  Intel® Xeon® Processor E5 v2 and E7 v2 Family Uncore Performance Monitoring Facility
The uncore subsystem in the Intel Xeon processor E5 v2 an d Intel Xeon Processor E7 v2 product families are based 
on the Ivy Bridge-E microarchitecture. There are some simila rities with those of the Intel Xeon processor E5 family 
based on the Sandy Bridge microarchitecture. Within th e uncore subsystem, localized performance counter sets 
are provided at logic control unit scope. 
Details of the uncore performance monitoring facility of Intel Xeon Processor E5 v2 and Intel Xeon Processor E7 v2 
families are available in the “Intel® Xeon® Processor E5 v2 and E7 v2 Uncore Performance Monitoring Program-
ming Reference Manual”. The MSR-based uncore PMU interfaces are listed in Table 2-28.
20.3.6 4th Generation Intel® Core™ Proc essor Performance Monitoring Facility
The 4th generation Intel® Core™ processor and Intel® Xeon® processor E3-1200 v3 prod uct family are based on 
the Haswell microarchitecture. The core PMU supports architectural performance monitoring capability with version ID 3 (see Section 20.2.3) and a host of non-architectural monitoring capabilities. 
Architectural performance monitoring version 3 capabilities are described in Section 20.2.3. The core PMU’s capability is similar to those described in Section 20.6.3 through Section 20.3.4.5, with some differ-
ences and enhancements summarized in Table 20-22. Addi tionally, the core PMU provides some enhancement to 
support performance monitoring when the target workload contains instruction streams using Intel
® Transactional 
Synchronization Extensions (TSX), see Section 20.3.6.5 . For details of Intel TSX, see Chapter 16, “Programming with 
Intel® Transactional Synchronization Extensions‚” of Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1.Table 20-21.  Uncore PMU MSR Summary for Intel® Xeon® Processor E5 Family
C-Box 8 4 44 Yes per-box NonePCU 1 4 48 Yes per-box Match/Mask
U-Box 1 2 44 Yes uncore None20-48 Vol. 3BPERFORMANCE MONITORING
20.3.6.1  Processor Event Base d Sampling (PEBS) Facility 
The PEBS facility in the 4th Generation Intel Core processor is similar to those in processors based on Sandy Bridge 
microarchitecture, with several enhanced features. The key components and differences of PEBS facility relative to 
Sandy Bridge microarchitecture is summarized in Table 20-23.Table 20-22.  Core PMU Comparison
Box Haswell Microarchitecture Sandy Bridge Microarchitecture Comment
# of Fixed counters per thread 3 3 Use CPUID to determine # 
of counters. See Section 
20.2.1.
# of general-purpose counters 
per core8 8 Use CPUID to determine # 
20.2.1.
Counter width (R,W) R:48, W: 32/48 R:48, W: 32/48 See Section 20.2.2.
threads)4 or (8 if a core not shared by two 
threads)Use CPUID to determine # 
20.2.1.
legacy semantics for branch profiling.
• Freeze_while_SMM. •F r e e z e _ P e r f m o n _ o n _ P M I  w i t h  
•F r e e z e _ L B R _ o n _ P M I  w i t h  
Sampling (PEBS) EventsSee Table 20-12 and Section 
20.3.6.5.1.See Table 20-12. IA32_PMC4-IA32_PMC7 
do not support PEBS.
PEBS-Load Latency See Section 20.3.4.4.2. See Section 20.3.4.4.2.PEBS-Precise Store No, re placed by Data Address 
profiling.Section 20.3.4.4.3
INST_RETIRED.ALL)Yes (using precise 
INST_RETIRED.ALL)
PEBS-EventingIP Yes No
Data Address Profiling Yes No

20.2.1.
LBR Profiling Yes YesCall Stack Profiling Yes, see Sect ion 18.11. No Use LBR facility.
Off-core Response Event MSR 1A6H and 1A7H; extended 
request and re sponse types.MSR 1A6H and 1A7H; extended 
request and response types.
Intel TSX support for Perfmo n See Section 20.3.6.5. No
Table 20-23.  PEBS Facility Comparison
Valid IA32_PMCx PMC0-PMC3 PMC0-PMC3 No PEBS on PMC4-PMC7 
PEBS Buffer Programming  Section 20 .3.1.1.1 Section 20. 3.1.1.1 Unchanged
IA32_PEBS_ENABLE Layout  Figure 20-15 Figure 20-29PEBS record layout Table 20-24; enhanced fields 
at offsets 98H, A0H, A8H, B0H.Table 20-3; enhanced fields at 
offsets 98H, A0H, A8H.Vol. 3B 20-49PERFORMANCE MONITORING
NOTE
is changed for a PEBS-enabled counter while an event is being counted. To avoid this, changes to the programming or value of a PEBS-enabled coun ter should be performed when the counter is 
disabled.
20.3.6.2  PEBS Data Format
The PEBS record format for the 4th Generation Intel Co re processor is shown in Ta ble 20-24. The PEBS record 
format, along with debug/store area storage format, does not change regardless of whet her IA-32e mode is active 
or not. CPUID.01H:ECX.DTES64[bit 2] reports whether th e processor's DS storage format support is mode-inde-
pendent. When set, it uses 64-bit DS storage format.Precise Events See Table 20-12. See Table 20-12. IA32_PMC4-IA32_PMC7 do 
PEBS-Load Latency See Table 20-13. Table 20-13PEBS-Precise Store No, replaced by data address 
profiling.Yes; see Section 20.3.4.4.3.
PEBS-PDIR Yes Yes IA32_PMC1 only.
PEBS skid from EventingIP 1 (or 2 if micro+macro fusion) 1
generation.
Table 20-24.  PEBS Record Format for 4t h Generation Intel Core Processor Family
00H R/EFLAGS 60H R1008H R/EIP 68H R11
10H R/EAX 70H R12
18H R/EBX 78H R1320H R/ECX 80H R14
28H R/EDX 88H R15
30H R/ESI 90H IA32_PERF_GLOBAL_STATUS38H R/EDI 98H Data Linear Address
40H R/EBP A0H Data Source Encoding
48H R/ESP A8H Latency value (core cycles)50H R8 B0H EventingIP
58H R9 B8H TX Abort Information ( Section 
20.3.6.5.1 )Table 20-23.  PEBS Facility Comparison
Box Haswell Microarchitecture Sandy Bridge Microarchitecture Comment20-50 Vol. 3BPERFORMANCE MONITORING
The layout of PEBS records are almost identical to those shown in Table 20-3. Offset B0H is a new field that records 
the eventing IP address of the retired in struction that triggered the PEBS assist.
The PEBS records at offsets 98 H, A0H, and ABH record data gathered from  three of the PEBS capabilities in prior 
processor generations: load latency facility (Section 20. 3.4.4.2), PDIR (Section 20.3.4.4.4), and the equivalent 
capability of precise store in prior generation (see Section 20.3.6.3).
In the core PMU of the 4th generation Intel Core processor, load latency facility and PDIR capabilities are 
unchanged. However, precise store is replaced by an e nhanced capability, data address profiling, that is not 
restricted to store address. Data address profiling also records information in PEBS records at offsets 98H, A0H, 
and ABH.
20.3.6.3  PEBS Data Address Profiling
The Data Linear Address facility is also abbreviated as DataLA. The facility is a replacement or extension of the 
precise store facility in previous processor generations. The DataLA facility complements the load latency facility by 
providing a means to profile load and store memory refe rences in the system, leverages the PEBS facility, and 
provides additional information about sampled loads and stores. Having precise memory reference events with 
linear address information for both loads and stores prov ides information to improve data structure layout, elimi-
nate remote node references, and identi fy cache-line conflicts in NUMA systems.
The DataLA facility in the 4th generation processor su pports the following events configured to use PEBS:
DataLA can use any one of the IA32_PMC0-IA32_PMC3 counter s. Counter overflows will initiate the generation of 
PEBS records. Upon counter overflow, hardware captures the linear address and possible other status information 
of the retiring memory uop. This information is then wr itten to the PEBS record that is subsequently generated.
To enable the DataLA facility, software must complete the fo llowing steps. Please note that the DataLA facility relies 
on the PEBS facility, so the PEBS configuration requirem ents must be completed before attempting to capture 
DataLA information.
•Program an event listed in Table 20-25 using any one of IA32_PERFEVTSEL0-IA32_PERFEVTSEL3. 
•Set the corresponding IA32_PEBS_ENABLE.PEBS_EN_CTRx bit. This enables the corresponding IA32_PMCx as 
a PEBS counter and enables the DataLA facility.
When the DataLA facility is enabled, the relevant informat ion written into a PEBS record affects entries at offsets 
98H, A0H, and A8H, as shown in Table 20-26. Table 20-25.  Precise Events That Su pports Data Linear Address Profiling
Event Name Event Name
MEM_UOPS_RETIRED.STLB_MISS_LOADS MEM_UOPS_RETIRED.STLB_MISS_STORESMEM_UOPS_RETIRED.LOCK_LOADS M EM_UOPS_RETIRED.SPLIT_STORES
MEM_UOPS_RETIRED.SPLIT_LOADS MEM_UOPS_RETIRED.ALL_STORES
MEM_UOPS_RETIRED.ALL_LOADS MEM_LOAD _UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
MEM_LOAD_UOPS_RETIRE D.L1_HIT MEM_LOAD_UOPS_RETIRED.L2_HIT
MEM_LOAD_UOPS_RETIRE D.L3_HIT MEM_LOAD_UOPS_RETIRED.L1_MISS
MEM_LOAD_UOPS_RETIRE D.L2_MISS MEM_LOAD_UOPS_RETIRED.L3_MISS
MEM_LOAD_UOPS_RETI RED.HIT_LFB MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT M EM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM
UOPS_RETIRED.ALL (if load or store is tagg ed) MEM_LOAD_UOPS_LLC_H IT_RETIRED.XSNP_NONEVol. 3B 20-51PERFORMANCE MONITORING
20.3.6.3.1  EventingIP Record
The PEBS record layout for processors based on Haswell mi croarchitecture adds a new field at offset 0B0H. This is 
the eventingIP field that records the IP address of the retired instruction that triggered the PEBS assist. The 
EIP/RIP field at offset 08H records the IP address of the ne xt instruction to be executed following the PEBS assist.
20.3.6.4  Off-core Respon se Performanc e Monitoring 
The core PMU facility to collect off-core response events are similar to those described in Section 20.3.4.5. The 
event codes are listed in Table 20-15. Each event code for off-core response monitoring requires programming an 
associated configuration MSR, MSR_ OFFCORE_RSP_x. Software must pr ogram MSR_OFFCORE_RSP_x according 
to:
•Transaction request type encoding (bits 15:0): see Table 20-27.
•Supplier information (bits 30:16): see Table 20-28.
•Snoop response information (bits 37:31): see Table 20-18.Table 20-26.  Layout of Data Linear Address Information In PEBS Record
Data Linear 
Address98H The linear address of the load  or the destination of the store.
Store Status A0H • DCU Hit (Bit 0): The store hit the data cache closest to th e core (L1 cache) if this bit is set, otherwise 
the store missed the data cache. This information is valid only for the following store events: 
UOPS_RETIRED.ALL (if store is tagged),
MEM_UOPS_RETIRED.S TLB_MISS_STORES,
MEM_UOPS_RETIRED.SPLIT_STORES, MEM_UOPS_RETIRED.ALL_STORES
• Other bits are zero, The STLB_MISS, LOCK bit information can be obtained by programming the 
corresponding store event in Table 20-25.
Reserved A8H Always zero.
Table 20-27.  MSR_OFFCORE_RSP_x Request_Ty pe Definition (Haswe ll Microarchitecture)
DMND_DATA_RD 0 Counts the number of demand data reads and pa ge table entry cacheline reads. Does not count L2 data 
read prefetches or instruction fetches.
DMND_RFO 1 Counts demand read (RFO) and software pr efetches (PREFETCHW) for exclusive ownership in 
anticipation of a write.
COREWB 3 Counts the number of modified cachelines written back.
PF_DATA_RD 4 Counts the number of data cacheline reads generated by L2 prefetchers.
PF_RFO 5 Counts the number of RFO requests generated by L2 prefetchers.PF_IFETCH 6 Counts the number of code reads generated by L2 prefetchers.
PF_L3_DATA_RD 7 Counts the number of data ca cheline reads generated by L3 prefetchers.
PF_L3_RFO 8 Counts the number of RFO requests generated by L3 prefetchers.PF_L3_CODE_RD 9 Counts the number of code reads generated by L3 prefetchers.
SPLIT_LOCK_UC_
LOCK10 Counts the number of lock requests that spli t across two cachelines or are to UC memory.
STRM_ST 11 Counts the number of streaming store requests electronically.

Reserved 14:12 Reserved20-52 Vol. 3BPERFORMANCE MONITORING
The supplier information field listed in Table 20-28. The fields vary across products (according to CPUID signatures) 
and is noted in the description.
20.3.6.4.1  Off-core Response Performance Moni toring in Intel Xeon Processors E5 v3 Series
Table 20-28 lists the supplier information field that apply to Intel Xeon processor E5 v3 series (CPUID signature 
06_3FH).OTHER 15 Any other request that crosses IDI, including I/O.
Table 20-28.  MSR_OFFCORE_RSP_x Supplier Info Fi eld Definition (CPUID Signatures: 06_3CH, 06_46H)
Supplier 
L3_HITM 18 M-state initial lookup stat in L3.L3_HITE 19 E-stateL3_HITS 20 S-state
Reserved 21 Reserved
LOCAL 22 Local DRAM Controller.Reserved 30:23 Reserved
Table 20-29.  MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signature: 06_45H)
Subtype Bit Name Offset DescriptionCommon Any 16 Catch all value for any response types.
Supplier 
L3_HITM 18 M-state initial lookup stat in L3.L3_HITE 19 E-state
L3_HITS 20 S-state
Reserved 21 ReservedL4_HIT_LOCAL_L4 22 L4 Cache
L4_HIT_REMOTE_HO P0_L4 23 L4 Cache
L4_HIT_REMOTE_HO P1_L4 24 L4 Cache
L4_HIT_REMOTE_HOP2P_L4 25 L4 Cache
Reserved 30:26 ReservedTable 20-27.  MSR_OFFCORE_RSP_x Request_Type Definition (Haswell Micr oarchitecture) (Contd.)
Bit Name Offset DescriptionVol. 3B 20-53PERFORMANCE MONITORING
20.3.6.5  Performance Monitoring and Intel® TSX
Chapter 16 of the Intel® 64 and IA-32 Architectures Software Develope r’s Manual, Volume 1, describes the details 
of Intel® Transactional Synchronization Extensions (Intel® TSX). This section describes performance monitoring 
support for Intel TSX. 
If a processor supports Intel TSX, the core PMU enhances its IA32_PERFEVTSELx MSR with two additional bit fields 
for event filtering. Support for Intel TSX is indicated by either (a) CPUID.(EAX=7, ECX= 0):RTM[bit 11]=1, or (b) if 
CPUID.07H.EBX.HLE [bit 4] = 1. The TSX-enhanced layout  of IA32_PERFEVTSELx is shown in Figure 20-34. The 
two additional bit fields are:
•IN_TX  (bit 32): When set, the counter will only include counts that occurred inside a transactional region, 
regardless of whether that region was aborted or committe d. This bit may only be set if the processor supports 
HLE or RTM.
•IN_TXCP  (bit 33): When set, the counter will not include co unts that occurred inside of an aborted transac-
tional region. This bit may only be set if the processo r supports HLE or RTM. This bit may only be set for 
IA32_PERFEVTSEL2. 
When the IA32_PERFEVTSELx MSR is programmed with both IN_TX=0 and IN_TXCP=0 on a processor that 
supports Intel TSX, the result in a counter may include detectable conditions associated with a transaction code 
region for its aborted execution (if any) and completed execution. 
In the initial implementation, software may need to take  pre-caution when using the IN_TXCP bit. See Table 2-29.Table 20-30.  MSR_OFFCORE_RSP_x Supplier Info Field Definition
Supplier 
L3_HITM 18 M-state initial lookup stat in L3.
L3_HITE 19 E-stateL3_HITS 20 S-state
L3_HITF 21 F-state
LOCAL 22 Local DRAM Controller.Reserved 26:23 Reserved
L3_MISS_REMOTE_HOP0 27 Hop 0 Remote supplier.
L3_MISS_REMOTE_HOP1 28 Hop 1 Remote supplier.L3_MISS_REMOTE_HOP2P 29 Hop 2 or more Remote supplier.Reserved 30 Reserved20-54 Vol. 3BPERFORMANCE MONITORING
A common usage of setting IN_TXCP=1 is to capture the number of events that were discarded due to a transac-
tional abort. With IA32_PMC2 configured to count in such  a manner, then when a transactional region aborts, the 
value for that counter is restored to the value it had prior to the aborted transactional region. As a result, any updates performed to the counter during the aborted transactional region are discarded.
On the other hand, setting IN_TX=1 can be used to drill do wn on the performance characteristics of transactional 
code regions. When a PMCx is configured with the corresponding IA32_PERFEVTSELx.IN_TX=1, only eventing 
conditions that occur inside transactional code regions are propagated to the event logic and reflected in the 
counter result. Eventing conditions sp ecified by IA32_PERFEVTSELx but occurring outside a transactional region 
are discarded. 
Additionally, a number of performance events are solely fo cused on characterizing the execution of Intel TSX trans-
actional code, they can be found at: https://perfmon-events.intel.com/
.
20.3.6.5.1  Intel® TSX and PEBS Support
If a PEBS event would have occurred inside a transactiona l region, then the transactional region first aborts, and 
then the PEBS event is processed.
Two of the TSX performance monitoring events also suppor t using the PEBS facility to capture additional informa-
tion. They are:
•HLE_RETIRED.ABORTED (encoding C8H mask 04H),
•RTM_RETIRED.ABORTED (encoding C9H mask 04H).
A transactional abort (HLE_RETIRED.ABORTED,RTM_RETIR ED.ABORTED) can also be programmed to cause PEBS 
events. In this scenario, a PEBS event is processed following the abort.
Pending a PEBS record inside of a transactional region will  cause a transactional abort. If a PEBS record was pended 
at the time of the abort or on an overflow of the TSX PE BS events listed above, only the following PEBS entries will 
be valid (enumerated by PEBS entry offset B8H bits[33:32] to indicate an HLE abort or an RTM abort):
•Offset B0H: EventingIP, 
•Offset B8H: TX Abort Information
These fields are set for all PEBS events.
•Offset 08H (RIP/EIP) corresponds to the instruction fo llowing the outermost XACQUIRE in HLE or the first 
instruction of the fallback handler of the outermost XBEGIN  instruction in RTM. This is useful to identify the 
aborted transactional region.
In the case of HLE, an aborted transa ction will restart execution deterministically at the start of the HLE region. In 
the case of RTM, an aborted transaction will transfer execution to the RTM fallback handler.
The layout of the TX Abort Information field is given in Table 20-31.Figure 20-34.  Layout of IA32_PER FEVTSELx MSRs Supp orting Intel TSX31
INV—Invert counter maskEN—Enable countersINT—APIC interrupt enablePC—Pin control87 0
E—Edge detectOS—Operating system modeUSR—User ModeCounter Mask EE
NI
N
ReservedI
N
VP
CU
S
RO
N
Y34
IN_TX—In Trans. Rgn
IN_TXCP—In Tx exclude abo rt (PERFEVTSEL2 Only)Vol. 3B 20-55PERFORMANCE MONITORING
20.3.6.6  Uncore Performance Moni toring Facilities in the 4th Ge neration Intel® Core™ Processors
The uncore sub-system in the 4th Generation Intel® Core™ processors provides its own performance monitoring 
facility. The uncore PMU facility provides dedicated MSRs  to select uncore performance monitoring events in a 
similar manner as those described in Section 20.3.4.6. 
The ARB unit and each C-Box provide local pairs of event select MSR and counter register. The layout of the event 
select MSRs in the C-Boxes are identical as shown in Figure 20-32.
rizes the number MSRs for uncore PMU for each box.
The uncore performance events for the C-Box and ARB units can be found at: https://perfmon-events.intel.com/ .
20.3.6.7  Intel® Xeon® Proces sor E5 v3 Family Uncore Pe rformance Monitoring Facility
Details of the uncore performance monitoring facility of In tel Xeon Processor E5 v3 families are available in “Intel® 
Xeon® Processor E5 v3 Uncore Performance Monitoring Programming Reference Manual”. The MSR-based uncore 
PMU interfaces are listed in Table 2-33.Table 20-31.  TX Abort In formation Field Definition
Cycles_Last_TX 31:0 The number of cycles in the last TSX region, regardless of whether that region had aborted or 
committed. 
HLE_Abort 32 If set, the abort information corresponds to an aborted HLE executionRTM_Abort 33 If set, the abort information corresponds to an aborted RTM execution
Instruction_Abort 34 If set, the abort wa s associated with the instruction corr esponding to the ev enting IP (offset 
0B0H) within the transactional region.
Non_Instruction_Abort 35 If set, the instruction corresponding to the eventing IP may not ne cessarily be related to the 
transactional abort.
Retry 36 If set, retrying the transact ional execution may have succeeded. 
Data_Conflict 37 If set, another logical processor conflicted with a memory address that was part of the

Data_Conflict 37 If set, another logical processor conflicted with a memory address that was part of the 
transactional region that aborted. 
Capacity Writes 38 If set, the transact ional region aborted due to exceeding resources for transactional writes.
Capacity Reads 39 If set, th e transactional region abor ted due to exceeding resour ces for transactional reads.
In_Suspend 40 Transaction was aborted whil e in a suspend region. This is an Intel Xeon processor only feature, 
available beginning with 4th generation Intel Xeon Scalable Processor Family; otherwise reserved.
Reserved 63:41 Reserved
Table 20-32.  Uncore PMU MSR Summary
ARB 1 2 44 Yes Uncore
Fixed Counter N.A. N.A. 48 No Uncore20-56 Vol. 3BPERFORMANCE MONITORING
20.3.7 5th Generation Intel® Core™ Processor and Intel ® Core ™ M Processor Performance 
Monitoring Facility
The 5th Generation Intel® Core™ processor and the Intel® Core™ M processor families are based on the Broadwell 
microarchitecture. The core PMU supports architectural pe rformance monitoring capability with version ID 3 (see 
Section 20.2.3) and a host of non-architectural monitoring capabilities. 
The core PMU has the same capability as those describ ed in Section 20.3.6. IA32_P ERF_GLOBAL_STATUS provide 
a bit indicator (bit 55) for PMI handler to distinguish PMI due to output buffer overflow condition due to accumu-lating packet data from Intel Processor Trace. 
Details of Intel Processor Trace is described in Chapter 33, “Intel® Processor Trace.” The 
IA32_PERF_GLOBAL_OVF_CTRL MSR provides  a corresponding reset control bit. Figure 20-35.  IA32_PERF_GLOBAL_STATUS MSR in Broadwell Microarchitecture 
Figure 20-36.  IA32_PERF_GLOBAL_OVF_C TRL MSR in Broadwell microarchitecture 62
CondChgd
Ovf_Buffer87 65 4 3
Valid if CPUID.0AH:EAX[15:8] = 8; else reservedOvf_UncorePMU61
Trace_ToPA_PMI55
62
Valid if CPUID.0AH:EAX[15:8] = 8; else reservedClrOvfUncore
ClrTraceToPA_PMI61 55Vol. 3B 20-57PERFORMANCE MONITORING
The specifics of non-architectural performance events can be found at: https://perfmon-events.intel.com/ .
20.3.8 6th Generation, 7th Generation and 8th Generation Intel® Core™ Processor 
Performance Monitoring Facility
The 6th generation Intel® Core™ processor is based on the Skylake microarchitecture. The 7th generation Intel® 
Core™ processor is based on the Kaby Lake microarchitecture. The 8th generation Intel® Core™ processors, 9th 
generation Intel® Core™ processors, and Intel® Xeon® E processors are based on the Coffee Lake microarchitec-
ture. For these microarchitectures, the core PMU supports  architectural performance monitoring capability with 
version ID 4 (see Section 20.2.4) and a host of non-architectural monitoring capabilities. 
Architectural performance monitoring version 4 capabilities are described in Section 20.2.4. The core PMU’s capability is similar to those described in Section 20.6.3 through Section 20.3.4.5, with some differ-
ences and enhancements summarized in Table 20-33. Addi tionally, the core PMU provides some enhancement to 
Synchronization Extensions (TSX), see Section 20.3.6.5. For details of Intel TSX, see Chapter 16, “Programming 
with Intel® Transactional Synchronization Extensions‚” of Intel® 64 and IA-32 Architectures Software Developer’s 
Performance monitoring result may be affected by side-ban d activity on processors that support Intel SGX, details 
are described in Chapter 40, “Enclave Code Debug and Profiling.”
Table 20-33.  Core PMU Comparison
Box Skylake, Kaby Lake and Coffee Lake 
MicroarchitecturesHaswell and Broadwell 
MicroarchitecturesComment
# of Fixed counters per thread 3 3 Use CPUID to 
determine # of 
counters. See 
Section 20.2.1.
per core8 8 Use CPUID to 
determine # of counters. See 
threads)Use CPUID to 
Architectural Perfmon version 4 3 See Section 20.2.4
streamlined semantics.
• Freeze_while_SMM.• Freeze_Perfmon_on_PMI with 
Legacy semantics 
not supported with version 4 or higher.
Counter and Buffer Overflow 
Status Management•Q u e r y  v i a  
IA32_PERF_GLOBAL_STATUS
•R e s e t  v i a  
IA32_PERF_GLOBAL_STATUS_RESET
•S e t  v i a  
IA32_PERF_GLOBAL_STATUS_SET• Query via 
•R e s e t  v i a  
IA32_PERF_GLOBAL_OVF_CTRLSee Section 20.2.4.20-58 Vol. 3BPERFORMANCE MONITORING
20.3.8.1  Processor Event Base d Sampling (PEBS) Facility 
The PEBS facility in the 6th generation, 7th generation an d 8th generation Intel Core processors provides a number 
enhancement relative to PEBS in processors based on Haswell/Broadwell microarchitectures. The key components 
and differences of PEBS facility relative to Haswell/Broadwell microarchitecture is summarized in Table 20-34.IA32_PERF_GLOBAL_STATUS 
Indicators of 
Overflow/Overhead/Interference• Individual counter overflow
• PEBS buffer overflow• ToPA buffer overflow
• CTR_Frz, LBR_Frz, ASCI• Individual counter overflow
• PEBS buffer overflow• ToPA buffer overflow 
(applicable to Broadwell 
microarchitecture)See Section 20.2.4.
Enable control in 
IA32_PERF_GLOBAL_STATUS •C T R _ F r z
•L B R _ F r zNA See Section 
20.2.4.1.
Perfmon Counter In-Use 
IndicatorQuery IA32_PERF_GLOBAL_INUSE NA See Section 
20.2.4.3.
Precise Events See Table 20-36. S ee Table 20-12. IA32_PMC4-PMC7 
do not support 
PEBS.
PEBS for front end events See Section 20.3.8.2. No
LBR Record Format Encoding 000101b 000100b Section 18.4.8.1
LBR Size 32 entries 16 entriesLBR Entry From_IP/To_IP/L BR_Info triplet From_IP/To_IP pair Section 18.12
LBR Timing Yes No Section 18.12.1
Call Stack Profiling Yes, see Section 18.11 Yes, see Section 18.11 Use LBR facility.Off-core Response Event MSR 1A6H and 1A7H; Extended request 
and response types.MSR 1A6H and 1A7H; Extended 
Intel TSX support for Perfmon See Section 20.3.6.5. See Section 20.3.6.5.
Table 20-34.  PEBS Facility Comparison 
Box Skylake, Kaby Lake and 
Coffee Lake 
Valid IA32_PMCx PMC0-PMC3 PMC0-PMC3 No PEBS on PMC4-PMC7.
PEBS Buffer Programming Section 20.3.1.1.1  Section 20.3.1.1.1 UnchangedIA32_PEBS_ENABLE Layout Figure 20-15  Figure 20-15
PEBS-EventingIP Yes Yes
PEBS record format encoding 0011b 0010bPEBS record layout Table 20-35; enhanced fields 
at offsets 98H- B8H; and TSC record field at C0H.Table 20-24; enhanced fields at 
offsets 98H, A0H, A8H, B0H.
Multi-counter PEBS 
resolutionPEBS record 90H resolves the 
eventing counter overflow.PEBS record 90H reflects 
IA32_PERF_GLOBAL_STATUS.
Precise Events See Table 20-36. See Ta ble 20-12. IA32_PMC4-IA32_PMC7 do not 
support PEBS.Table 20-33.  Core PMU Comparison (Contd.)
MicroarchitecturesCommentVol. 3B 20-59PERFORMANCE MONITORING
NOTES
Precise events are only valid when the follow ing fields of IA32_PERFEVTSELx are all zero: 
AnyThread, Edge, Invert, CMask.
disabled.
20.3.8.1.1  PEBS Data Format
The PEBS record format for the 6th generation, 7th gene ration and 8th generation Intel Core processors is 
reporting with encoding 0011b in IA32_PERF_CAPABILITIES [11:8]. The lay out is show n in Table 20-35. The PEBS 
record format, along with debug/store area storage format , does not change regardless of whether IA-32e mode is 
active or not. CPUID.01H:ECX.DTES64[bit 2] reports whet her the processor's DS storage format support is mode-

NOTES
disabled.
independent. When set, it uses 64-bit DS storage format.
The layout of PEBS records are largely identical to those shown in Table 20-24. PEBS-PDIR Yes Yes IA32_PMC1 only.
PEBS-Load Latency See Section 20. 3.4.4.2. See Section 20.3.4.4.2.
Data Address Profiling Yes YesFrontEnd event support FrontEnd_Retried event and 
MSR_PEBS_FRONTEND.No IA32_PMC0-PMC3 only.
Table 20-35.  PEBS Record Format fo r the 6th Generation, 7th Generation, and 8th Generation Intel Core Processor 
Families
00H R/EFLAGS 68H R11
08H R/EIP 70H R1210H R/EAX 78H R13
18H R/EBX 80H R14
20H R/ECX 88H R1528H R/EDX 90H Applicable Counter
30H R/ESI 98H Data Linear Address
38H R/EDI A0H Data Source Encoding40H R/EBP A8H Latency value (core cycles)
48H R/ESP B0H EventingIP
50H R8 B8H TX Abort Information (Section 20.3.6.5.1)58H R9 C0H TSC
60H R10Table 20-34.  PEBS Facili ty Comparison  (Contd.)
MicroarchitecturesComment20-60 Vol. 3BPERFORMANCE MONITORING
processor generations: load latency facility (Section 20. 3.4.4.2), PDIR (Section 20.3.4.4.4), and data address 
profiling (Section 20.3.6.3).
In the core PMU of the 6th generation, 7th generation and 8t h generation Intel Core processors, load latency facility 
and PDIR capabilities and data address profiling are unchanged relative to the 4th generation and 5th generation 
Intel Core processors. Similarly, precise st ore is replaced by data address profiling.
With format 0010b, a snapshot of the IA32_PERF_GLOBAL_S TATUS may be useful to resolve the situations when 
more than one of IA32_PMICx have b een configured to collect PEBS data and two consecutive overflows of the 
PEBS-enabled counters are sufficiently far apart in time. It is also possible for the image at 90H to indicate multiple 
PEBS-enabled counters have overflowed. In the latter scena rio, software cannot to correlate the PEBS record entry 
to the multiple overflowed bits.
With PEBS record format encoding 0011b, offset 90H re ports the “applicable counter” field, which is a multi-
counter PEBS resolution index allowing software to correla te the PEBS record entry wi th the eventing PEBS over-
flow when multiple counters are configured to record PEBS records. Additionally, offset C0H captures a snapshot of 
the TSC that provides a time line annotation for each PEBS record entry.
20.3.8.1.2  PEBS Events
The list of precise events supported for PEBS in the Skylake, Kaby Lake and Coffee Lake microarchitectures is 
shown in Table 20-36.
Table 20-36.   Precise Events for the Skylake, Kaby Lake, an d Coffee Lake Microarchitectures
INST_RETIRED C0H PREC_DIST101H
ALL_CYCLES201H
OTHER_ASSISTS C1H ANY 3FH
BR_INST_RETIRED C4H CONDITIONAL 01H
NEAR_CALL 02HALL_BRANCHES 04HNEAR_RETURN 08HNEAR_TAKEN 20HFAR_BRACHES 40H
BR_MISP_RETIRED C5H CONDITIONAL 01H
ALL_BRANCHES 04HNEAR_TAKEN 20H
FRONTEND_RETIRED C6H <Programmable
3>0 1 H
HLE_RETIRED C8H ABORTED 04H
RTM_RETIRED C9H ABORTED 04H
MEM_INST_RETIRED2D0H LOCK_LOADS 21H
SPLIT_LOADS 41HSPLIT_STORES 42HALL_LOADS 81HALL_STORES 82HVol. 3B 20-61PERFORMANCE MONITORING
20.3.8.1.3  Data Address Profiling
The PEBS Data address profiling on the 6th generation, 7th generation and 8th generation Intel Core processors is 
largely unchanged from the prior generation. When the Data LA facility is enabled, the relevant information written 
into a PEBS record affects entries at offset s 98H, A0H, and A8H, as shown in Table 20-26. 
20.3.8.2  Frontend  Retired Facility
The Skylake Core PMU has been extended to cover common microarchitectural conditions related to the front end 
pipeline in addition to providing a generic latency mech anism that can locate fetch bubbles without necessarily 
attributing them to a particular condition. The facility coun ts the events if the associated instruction reaches retire-
ment (architecturally committed). Additionally, the user may opt to enable the PEBS facility to obtain precise infor-
mation on the context of the event, e.g., EventingIP.
The supported frontend microarchitectural co nditions require the following interfaces:
•The IA32_PERFEVTSELx MSR must select the FRONTEND_RETIRED event, EventSelect = C6H and UMASK = 
01H.MEM_LOAD_RETIRED4D1H L1_HIT 01H
L2_HIT 02HL3_HIT 04HL1_MISS 08HL2_MISS 10HL3_MISS 20HHIT_LFB 40H
MEM_LOAD_L3_HIT_RETIRED
2D2H XSNP_MISS 01H
XSNP_HIT 02HXSNP_HITM 04HXSNP_NONE 08H
NOTES:
1. Only available on IA32_PMC1.
2. INST_RETIRED.ALL_CYCLES is configured with additional parameters of cmask = 10 and INV = 1
3. Subevents are specified using MSR_PEBS_FRONTEND, see Section 20.3.8.3
4. Instruction with at least one load uop experiencing the condition specified in the UMask.
Table 20-37.  Layout of Data Linear Address Information In PEBS Record
MEM_INST_RETIRED.STLB_MISS_STORES,MEM_INST_RETIRED.ALL_STORES,
MEM_INST_RETIRED .SPLIT_STORES.
• Other bits are zero.
Reserved A8H Always zero.Table 20-36.   Precise Events for the Skylake, Ka by Lake, and Coffee Lake Microarchitectures (Contd.)
Event Name Event Select Sub-event UMask20-62 Vol. 3BPERFORMANCE MONITORING
•This event employs a new MSR, MSR_PEBS_FRONTEND, to  specify the supported frontend event details, see 
Table 20-38.
•If precise information is desired, program the PEBS_E N_PMCx field of IA32_PEBS_ENABLE MSR as required.
Note the AnyThread field of IA32_PERFEVTSELx is ignore d by the processor for the “FRONTEND_RETIRED” event.
The sub-event encodings supported by MSR_PEBS _FRONTEND.EVTSEL is given in Table 20-38. 
The layout of MSR_PEBS_FRONT END is given in Table 20-39.
The FRONTEND_RETIRED event is designed to help software  developers identify exact instructions that caused 
front-end issues. There are some instances in which the ev ent will, by design, the under -counting scenarios include 
•The event counts only retired (non-speculative) front-end events, i.e., events from just true program execution 
path are counted.
•The event will count once per cacheline (at most). If a cacheline contains multiple instructions which caused 
front-end misses, the count will be only 1 for that line. 
•If the multibyte sequence of an instruction spans across two cachelines and causes a miss it will be recorded 
once. If there were additional misses in the seco nd cacheline, they will no t be counted separately. Table 20-38.  FrontEnd_Retired Sub-Event Encodings Supported by MSR_PEBS_FRONTEND.EVTSEL
Sub-Event Name EVTSEL Description
ANY_DSB_MISS 1H Retired Instructions which experienced any decode stream buffer (DSB) miss.
DSB_MISS 11H Retired Instructions which experienced a DSB miss that caused a fetch starvation cycle.L1I_MISS 12H The fetch of retired Instructions which experienced Instruction L1 Cache true miss
1. Additional 
requests to the same cache line as an in -flight L1I cache miss  will not be counted.
NOTES:
1. A true miss is the first miss for a cacheline/page (excluding secondary miss es that fall into sa me cacheline/page).L2_MISS 13H The fetch of retired Instructions which experi enced L2 Cache true miss. Ad ditional requ ests to the 
same cache line as an  in-flight MLC cache mi ss will not be counted.
ITLB_MISS 14H The fetch of retired Instructions which experi enced ITLB true miss. Additi onal requests to the same 
cache line as an in-flight IT LB miss will not be counted.
STLB_MISS 15H The fetch of retired Instructions which experienced STLB true miss. Additional requests to the 
same cache line as an  in-flight STLB miss  will not be counted.
IDQ_READ_BUBBLES 6H An IDQ read bubble is defined as any one of the 4 allocation slots of IDQ that is not filled by the 
front-end on any cycle where there is no back end stall. Using the threshold and latency fields in 
MSR_PEBS_FRONTEND allows counting of IDQ read bubbles of various magnitude and duration. 
Latency controls the number of cycles and Threshold controls the number of allocation slots that 
contain bubbles.
The event counts if and only if a sequence of at  least FE_LATENCY consecutive cycles contain at 
least FE_TRESHOLD number of bubbles each.
Table 20-39.  MSR_PEBS_FRONTEND Layout
EVTSEL 7:0 Encodes the sub-event within FrontE nd_Retired that can use PEBS facility, see Table 20-38.
IDQ_Bubble_Length 19:8 Specifies the threshold of continuously  elapsed cycles for the specified width of bubbles when 
counting IDQ_READ_BUBBLES event.

IDQ_Bubble_Width 22:20 Specifies the threshold of simultaneous bubbles when counting IDQ_READ_BUBBLES event.Reserved 63:23 ReservedVol. 3B 20-63PERFORMANCE MONITORING
•If a multi-uop instruction exceeds the allocation width of one cycle, the bubbles associated with these uops will 
be counted once per that instruction. 
•If 2 instructions are fused (macro-fusion), and either of them or both cause front-end misses, it will be counted once for the fused instruction.
•If a front-end (miss) event occurs outside instruction boundary (e.g., due to processor handling of architectural 
event), it may be reported for the next instruction to retire.
20.3.8.3  Off-core Respon se Performanc e Monitoring 
The core PMU facility to collect off-core response events are similar to those described in Section 20.3.4.5. Each 
event code for off-core response monitoring requires programming an associated configuration MSR, MSR_OFF-
CORE_RSP_x. Software must program MSR_OFFCORE_RSP_x according to:
•Transaction request type encoding (bits 15:0): see Table 20-40.
•Supplier information (bits 29:16): see Table 20-41.
•Snoop response information (bits 37:30): see Table 20-42.
Table 20-41 lists the supplier information field that applie s to 6th generation, 7th generation and 8th generation 
Intel Core processors. (6th generation Intel Core pr ocessor CPUID signatures: 06_4EH and 06_5EH; 7th genera-
tion and 8th generation Intel Core proc essor CPUID signatures: 06_8EH and 06_9EH).Table 20-40.  MSR_OFFCORE_RSP_x Request_Type Definition 
(Skylake, Kaby Lake, and Coffee Lake Microarchitectures)
DMND_DATA_RD 0 Counts the number of demand data reads and page table entry cacheline reads. Does not count hw or 
sw prefetches.
DMND_RFO 1 Counts the number of demand reads for ownership (RFO) requests generated by a write to data 
cacheline. Does not count L2 RFO prefetches.
Reserved 14:3 Reserved
OTHER 15 Counts miscellaneous requests, su ch as I/O and uncacheable accesses.
Table 20-41.  MSR_OFFCORE_RSP_x Supplier Info Field Definition 
(CPUID Signatures: 06_4EH, 06_5EH,  06_8EH, 06_9EH)
Supplier 
L3_HITE 19 E-state
L3_HITS 20 S-stateReserved 21 Reserved
L4_HIT 22 L4 Cache (if L4 is present in the processor).
Reserved 25:23 ReservedDRAM 26 Local Node
Reserved 29:27 Reserved
SPL_HIT 30 L4 cache super line hit (if L4 is present in the processor).20-64 Vol. 3BPERFORMANCE MONITORING
Table 20-42 lists the snoop information field that appl y to processors with CPUID signatures 06_4EH, 06_5EH, 
06_8EH, 06_9E, and 06_55H.
20.3.8.3.1  Off-core Response Performance Monitori ng for the Intel® Xeon® Scalable Processor Family
The following tables list the requestor and supplier information fields that apply to the Intel® Xeon® Scalable 
Processor Family. 
•Transaction request type encoding (bits 15:0): see Table 20-43.
•Supplier information (bits 29:16): see Table 20-44.
•Supplier information (bits 29:16) with support for Intel® Optane™ DC Persistent Memory support: see 
Table 20-45.
•Snoop response information has not been changed and is the same as in (bits 37:30): see Table 20-42.Table 20-42.  MSR_OFFCORE_RSP_ x Snoop Info Field Definition 
(CPUID Signatures: 06_4EH, 06_5EH , 06_8EH, 06_9E, 06_55H)
Snoop Info SPL_HIT 30 L4 cache super line hit (if L4 is present in the processor).
SNOOP_NONE 31 No details on snoop-related information.
SNOOP_NOT_NEEDED 32 No snoop was needed to satisfy the request.
SNOOP_MISS 33 A snoop was needed an d it missed all snooped caches:
-For LLC Hit, ReslHitl wa s returned by all cores.
-For LLC Miss, Rspl was re turned by all sockets and data was returned from 
DRAM.
SNOOP_HIT_NO_FWD 34 A snoop was needed and it hits in at least one snooped cache. Hit denotes a 
cache-line was vali d before snoop effect. This includes:
-Snoop Hit w/ Invalida tion (LLC Hit, RFO).
-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD).
-Snoop Hit w/ Invalida tion and No Forward (L LC Miss, RFO Hit S).
In the LLC Miss case, data is returned from DRAM.
SNOOP_HIT_WITH_FWD 35 A snoop was needed and data was forwarded from a remote socket. This 
includes:
SNOOP_HITM 36 A snoop was needed and it HitM-ed in local or remote ca che. HitM denotes a 
cache-line was in modified  state before effect as a results of snoop. This 
includes:
-Snoop HitM w/ WB (LLC  miss, IFetch/Data_RD).
-Snoop Forward Modified w/ Inva lidation (LLC Hit/Miss, RFO).
SNOOP_NON_DRAM 37 Target was non-DRAM system address. This includes MMIO transactions.Vol. 3B 20-65PERFORMANCE MONITORING
Table 20-44 lists the supplier information field that applie s to the Intel Xeon Scalable Processor Family (CPUID 
signature: 06_55H).
Table 20-45 lists the supplier information field that applie s to the Intel Xeon Scalable Processor Family (CPUID 
signature: 06_55H, Steppings 0x5H - 0xFH).Table 20-43.  MSR_OFFCORE_RSP_x Request_Type Definition (Intel® Xeon® Scalable Processor Family)
DEMAND_DATA_RD 0 Counts the number of demand data reads and page table entry cacheline reads. Does not count 
hw or sw prefetches.
DEMAND_RFO 1 Counts the number of demand reads for ownership (RFO) requests generated by a write to data 
cacheline. Does not co unt L2 RFO prefetches.
DEMAND_CODE_RD 2 Counts the number of demand instruction cacheline reads and L1 instruction cacheline 
prefetches.
Reserved 3 Reserved.PF_L2_DATA_RD 4 Counts the number of prefetch data reads into L2.
PF_L2_RFO 5 Counts the number of RFO Requests generated by the MLC prefetches to L2.
Reserved 6 Reserved.PF_L3_DATA_RD 7 Counts the number of MLC data read prefetches into L3.PF_L3_RFO 8 Counts the number of RFO requests generated by MLC prefetches to L3.
Reserved 9 Reserved.
PF_L1D_AND_SW 10 Counts data cacheline re ads generated by hardware L1 data cache prefetcher or software 
prefetch requests.
Reserved 14:11 Reserved.OTHER 15 Counts miscellaneous requests, su ch as I/O and un-cacheable accesses.
Table 20-44.  MSR_OFFCORE_RSP_x Supplier Info Field Definition (CPUID Signature: 06_55H)
Supplier 
InfoSUPPLIER_NONE 17 No Supplier Information available.
L3_HIT_M 18 M-state initial lookup stat in L3.
L3_HIT_E 19 E-state
L3_HIT_S 20 S-stateL3_HIT_F 21 F-state
Reserved 25:22 Reserved
L3_MISS_LOCAL_DRAM 26 L3 Miss: local home re quests that missed the L3 cache and were 
serviced by local DRAM.
L3_MISS_REMOTE_HOP0_DRAM 27 Hop 0 Remote supplier.L3_MISS_REMOTE_HOP1_DRAM 28 Hop 1 Remote supplier.
L3_MISS_REMOTE_HOP2P_DRAM 29 Hop  2 or more Remote supplier.
Reserved 30 Reserved20-66 Vol. 3BPERFORMANCE MONITORING
20.3.8.4  Uncore Performa nce Monitoring Facilities on Intel® Core™ Processors Based on Cannon Lake 
Microarchitecture
Cannon Lake microarchitecture introduces LLC support of up to six processor cores. To support six processor cores 
and eight LLC slices, existing MSRs have been rearrang ed and new CBo MSRs have been added. Uncore perfor-
mance monitoring software drivers from prior generations of Intel Core processors wi ll need to update the MSR 
addresses. The new MSRs and updated MSR addresses have  been added to the Uncore PMU listing in Section 
2.17.2, “MSRs Specific to 8th Generation Intel® Core™ i3 Processors,” in Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 4.
20.3.9 10th Generation Intel® Core™ Proc essor Performance Monitoring Facility
Some 10th generation Intel® Core™ processors and some 3rd generation Intel® Xeon® Scalable Processor Family 
are based on Ice Lake microarchitecture. Some 11th generation Intel® Core™ processors are based on the Tiger 
Lake microarchitecture, and some are based on the Rocket  Lake microarchitecture. For these processors, the core 
PMU supports architectural performance monitoring capability with version Id 5 (see Section 20.2.5) and a host of 
non-architectural monitoring capabilities.
The core PMU's capability is similar to those described in  Section 20.3.1 through Section 20.3.8, with some differ-
ences and enhancements summarized in Table 20-46.Table 20-45.  MSR_OFFCORE_RSP_x Supplier Info Field Definition 
(CPUID Signature: 06_55H, Steppings 0x5H - 0xFH)
Common Any 16 Catch all value for any response types.Supplier 
L3_HIT_E 19 E-stateL3_HIT_S 20 S-state
L3_HIT_F 21 F-state
LOCAL_PMM 22 Local home requests that were serviced by local PMM.REMOTE_HOP0_PMM 23 Hop 0 Remote supplier.REMOTE_HOP1_PMM 24 Hop 1 Remote supplier.

REMOTE_HOP2P_PMM 25 Hop 2 or  more Remote supplier.
L3_MISS_LOCAL_DRAM 26 L3 Miss: Local home re quests that missed th e L3 cache and were 
L3_MISS_REMOTE_HOP2P_DRAM 29 Hop 2 or more Remote supplier.
Reserved 30 ReservedVol. 3B 20-67PERFORMANCE MONITORING
20.3.9.1  Processor Event Ba sed Sampling (PEBS) Facility
The PEBS facility in the 10th generation Intel Core processo rs provides a number of enhancements relative to PEBS 
in processors based on the Skylake, Kaby Lake, and Co ffee Lake microarchitectures. Enhancement of the PEBS 
facility with Extended PEBS and Ad aptive PEBS features is described in detail in Section 20.9. 
The 3rd generation Intel Xeon Scalable Family of proce ssors based on the Ice Lake microarchitecture introduce 
EPT-friendly PEBS. This allows EPT viol ations and other VM Exits to be taken on PEBS accesses to the DS Area. See 
Section 20.9.5 for details.
20.3.9.2  Off-core Respon se Performanc e Monitoring
•Transaction request type encoding (bits 15:0): see Table 18-[N1].
•Response type encoding (bits 16-37) of
— Supplier information: see Table [18-N2].
— Snoop response information: see Table [18-N3].
•All transactions are tracked at cacheline granularity except some in request type OTHER.Table 20-46.  Core PMU Summary of  the Ice Lake Microarchitecture
Box Ice Lake Microarchitecture Skylake, Kaby Lake and Coffee 
Lake MicroarchitecturesComment
Architectural Perfmon 
version5 4 See Section 20.2.5.
Number of programmable 
counters per thread8 4 Use CPUID to determine number 
of counters. See Section 20.2.1.
PEBS: Basic functionality Y es Yes See Section 20.3.9.1.
PEBS record format encoding 01 00b 0011b See Section 20.6.2.4.2.
Extended PEBS PEBS is extended to all Fixed 
and General Purpose counters and to all performance 
monitoring events. No See Section 20.9.1.
Adaptive PEBS Yes No See Section 20.9.2.
Performance Metrics Yes (4) No See Section 20.3.9.3.PEBS-PDIR IA32_FIXED0 only 
(Corresponding counter control 
MSRs must be enabled.)IA32_PMC1 only.
Table 20-47.  MSR_OFFCORE_RSP_x Request_Type Definition 
(Processors Based on Ice Lake Microarchitecture)
DEMAND_DATA_RD 0 Counts demand data and page table entry reads.
DEMAND_RFO 1 Counts demand read (RFO) and software  prefetches (PREFETCHW) for exclusive ownership 
in anticipation of a write.
DEMAND_CODE_RD 2 Counts demand instruction fetches and instruction prefetches targeting the L1 instruction 
cache.
Reserved 3 Reserved20-68 Vol. 3BPERFORMANCE MONITORING
Ice Lake microarchitecture has added a new category of Re sponse subtype, called a Co mbined Response Info. To 
count a feature in this type, all the bits specified must be set to 1.
A valid response type must be a non-ze ro value of the following expression:
Any | ['OR' of Combined Response Info Bits | [('OR' of Supplier Info Bits) & ('OR' of Snoop Info Bits)]]If "ANY" bit[16] is set, other response type bits [17-39] are ignored.
Table 20-48 lists the supplier information field that applies to processors based on Ice Lake microarchitecture.
Table 20-49 lists the snoop information field that applies to processors based on Ice Lake microarchitecture.HWPF_L2_DATA_RD 4 Counts hardware generated data read prefetches targeting the L2 cache.
HWPF_L2_RFO 5 Counts hardware generated prefetches for exclusive ownership (RFO) targeting the L2 
cache.
Reserved 6 Reserved
HWPF_L3 9:7 and 13
1Counts hardware generated prefetches of any type targeting the L3 cache.
HWPF_L1D_AND_SWPF 10 Counts hardware generated data re ad prefetches targeting the L1 data cache and the 
following software prefetches (PREFETCHNTA, PREFETCHT0/1/2).
STREAMING_WR 11 Counts streaming stores.
Reserved 12 Reserved
Reserved 14 Reserved
OTHER 15 Counts miscellaneous requests, su ch as I/O and un-cacheable accesses.
NOTES:
1. All bits need to be se t to 1 to count this type.
Table 20-48.  MSR_OFFCORE_RSP_x Supplier Info Field Definition
Combined 
Response 
InfoDRAM 26, 31, 321
NOTES:
1. All bits need to be se t to 1 to count this type.Requests that are satisfied by DRAM.
NON_DRAM 26, 371Requests that are satisfied by a NON_DR AM system component. This includes 
MMIO transactions.
L3_MISS 22, 23, 24, 25, 26, 27, 
28, 29, 30, 31, 32, 33, 34, 35, 36, 37
1Requests that were not supplied by the L3 Cache. The event includes some currently reserved bits in anticipation of future memory designs.
Supplier 
InfoL3_HIT 18,19, 20
1Requests that hit in L3 cache. Depending on the sn oop response the L3 cache 
may have retrieved the cacheline from another core's cache.
Reserved 17, 21:25, 27:29 Reserved.Table 20-47.  MSR_OFFCORE_RSP_x Request_Type Definition 
Bit Name Offset DescriptionVol. 3B 20-69PERFORMANCE MONITORING
20.3.9.3  Performance Metrics
The Ice Lake core PMU provides built-in support for Top- down Microarchitecture Analysis (TMA) method level 1 
metrics. These metrics are always available to cross-validate performance observations, freeing general purpose 
counters to count other events in high counter utilizat ion scenarios. For more details about the method, refer to 
Top-Down Analysis Method chapter (Appendix B.1) of th e Intel® 64 and IA-32 Architectures Optimization Refer-
ence Manual.
A new MSR called MSR_PERF_METRICS re ports the metrics directly. Software can check (and/or expose to its 
guests) the availability of the PERF_METRICS feature using IA32_PERF_CAPABILITIE S.PERF_METRICS_AVAILABLE 
(bit 15). For additional details on this MSR, refer to Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 4.
This register exposes the four TMA Level 1 metrics. The lowe r 32 bits are divided into four 8-bit fields, as shown by 
the above figure, each of which is an integer fraction of 255.Table 20-49.  MSR_OFFCORE_RSP_x Snoop Info Field Definition
Snoop 
InfoReserved 30 Reserved.
SNOOP_MISS 33 A snoop was sent and none of the snooped caches contained the cacheline.
SNOOP_HIT_NO_FWD 34 A snoop was sent and hit in at least one snooped cache. The unmodified 
cacheline was not forwarded back, because the L3 already has a valid copy.
Reserved 35 Reserved.SNOOP_HITM 36 A snoop was sent and the cachel ine was found modified in another core's 
caches. The modified cacheline was forwarded to the requesting core.
Figure 20-37.  MSR_PERF_METRICS Definition6355 47 393123 15 7 0Backend Bound Frontend Bound Bad Speculation RetiringReserved20-70 Vol. 3BPERFORMANCE MONITORING
To support built-in performance metrics, new bi ts have been added to the following MSRs:
•IA32_PERF_GLOBAL_CTRL. EN_PERF_METRICS[48]: If th is bit is set and fixed-function performance-
monitoring counter 3 is enabled, built-in performance metrics are enabled.
•IA32_PERF_GLOBAL_STATUS_SET. SET_OVF_PERF_METRICS[48]: If this bit is set, it will set the status bit in the IA32_PERF_GLOBAL_STATUS register for PERF_METRICS.
•IA32_PERF_GLOBAL_STATUS_RESET. RESET_OVF_PERF_METRICS[48]: If this bit is set, it will clear the status 
bit in the IA32_PERF_GLOBAL_STATUS register for PERF_METRICS.
•IA32_PERF_GLOBAL_STATUS. OVF_PERF_METRICS[48]: If this  bit is set, it indicates that a PERF_METRICS-
related resource has overflowed and a PMI is triggered4. If this bit is clear, no such overflow has occurred.
NOTE
Software has to synchronize, e.g., re-start, fixed-function performance-monitoring counter 3 as well as PERF_METRICS when either bit 35 or 48 in IA32_PERF_GLOBAL_STATUS is set. Otherwise, 
PERF_METRICS may return undefined values.
The values in MSR_PERF_METRICS are derived from fixed-function performance-monitoring counter 3. Software 
should start both registers, PERF_METRICS and fixed-func tion performance-monitoring counter 3, from zero. Addi-
tionally, software is recommended to periodically clear bo th registers in order to maintain accurate measurements 
for certain scenarios that involve sampling metrics at high rates. 
In order to save/restore PE RF_METRICS, software should follow these guidelines:
•PERF_METRICS and fixed-function performance-monitoring  counter 3 should be saved and restored together.
•To ensure that PERF_METRICS and fixed-function pe rformance-monitoring counter 3 remain synchronized,

NOTE
•To ensure that PERF_METRICS and fixed-function pe rformance-monitoring counter 3 remain synchronized, 
both should be disabled during both save and restore. Software should enable/disable them atomically, with a 
single write to IA32_PERF_GLOBAL_CTRL to se t/clear both EN_PERF_METRICS[bit 48] and 
EN_FIXED_CTR3[bit 35].
•On state restore, fixed-function performanc e-monitoring counter 3 must be restored before PERF_METRICS, 
otherwise undefined results may be observed.
20.3.10 12th and 13th Generation Intel® Core™ Processors, and 4th Generation Intel® Xeon® 
Scalable Processor Family Pe rformance Monitoring Facility
The 12th generation Intel® Core™ processor supports Alder Lake perf ormance hybrid architecture. These proces-
sors offer a unique combination of Performance and Effici ent-cores (P-core and E-core). The P-core is based on 
Golden Cove microarchitecture and the E-core is based on Gracemont microarchitecture. The 13th generation 
Intel® Core™ processor supports Raptor Lake performance hybrid architecture, utilizing both Raptor Cove cores 
and enhanced Gracemont cores. The 4th generation Intel® Xeon® Scalable Processor Family is based on Sapphire 
Rapids microarchitecture utilizing Golden Cove cores. These processors all report architectural performance moni-toring version ID = 5 and support non-architectural monitoring capabilities described in this section. 
20.3.10.1  P-core Performance Monitoring Unit
The P-core PMU's capability is similar to those described in Section 20.3.1 through Section 20.3.9, with some differ-
ences and enhancements summarized in Table 20-50.
4. An overflow of fixed-function performance-monitoring counter 3 should normally happen first if software follows Intel’s recom men-
dations.Vol. 3B 20-71PERFORMANCE MONITORING
20.3.10.1.1  P-core Perf Metrics Extensions
For 12th generation Intel Core processor P-cores, the core  PMU supports the built-in me trics that were introduced 
in the Ice Lake microarchitecture PMU. This core PM U extends the PERF_METRICS MSR to feature TMA method 
level 2 metrics, as shown in Figure 20-38.Table 20-50.  Core PMU Summary of the Golden Cove Microarchitecture 
Box Golden Cove 
MicroarchitectureIce Lake Microarchitecture Comment
version5 5 See Section 20.2.5.
Event-Counter Restrictions Simplified identification Counters 4-7 support a subset of 
events. See Section 20.3.10.1.2.
Performance Metrics Yes (12) Yes (4) See Section 20.3.9.3.
PEBS: Baseline, record 
formatYes
0100bYes
0100bSee Section 20.3.9.
PEBS: EPT-friendly Yes No; debuts in Ice Lake server 
microarchitectureSee Section 20.6.2.4.2.
PEBS: Precise Distribution IA32_FIXED0 instruction-
granularity
PDist on IA32_PMC0IA32_FIXED0 cycle-granularity
No PDistSee Section 20.9.6.
PEBS: Load Latency Instruction latency
Cache latencyAccess info fields (5)Instruction latency
Access info fields (3)See Section 20.9.7.
PEBS: Store Latency Cache latency
Access info fields (3)None See Section 20.9.8.
PEBS: Intel TSX support Abort info fields (9) A bort info fields (8) See Section 20.3.6.5.1.
(Intel Xeon processor only 
feature.)
Figure 20-38.  PERF_METRICS MSR Definition for 12th Generation Intel® Core™ Processor P-core31 23 15 7 0Backend Bound Frontend Bound Bad Speculation Retiring
Memory Bound Fetch Latency Branch Mispredicts Heavy Operations
63 55 47 39 3220-72 Vol. 3BPERFORMANCE MONITORING
The lower half of the register is the TMA level 1 metrics (leg acy). The upper half is also divided into four 8-bit fields, 
each of which is an integer fraction of 255. Additionally, ea ch of the new level 2 metrics in the upper half is a subset 
of the corresponding level 1 metric in the lower half (tha t is, its parent node per the TMA hierarchy). This enables 
software to deduce the other four level 2 metrics by subtracting corresponding metrics as shown in Figure 20-39.
The PERF_METRICS MSR and fixed-function performance-mo nitoring counter 3 of the core PMU feature 12 metrics 
in total that cover all level 1 and level 2 nodes of the TMA hierarchy.
20.3.10.1.2  P-core Counter Restrictions Simplification
The 12th generation Intel Core processor P-core allows identification of performance monitoring events with 
counter restrictions based on event encodings. The genera l rule is: Event Codes < 0x90 are restricted to general-
purpose performance-monitoring counters 0-3. Event Codes ≥ 0x90 are likely to have no restrictions. Table 20-51 
lists the exceptions to this rule.
20.3.10.1.3  P-core Off-core Response Facility
For the 12th generation Intel Core processor P-core, th e Off-core Response (OCR) Facility is similar to that 
described in Section 20.3.9.2.
The following enhancements are introduced for the Request_Type of MSR_OFFCORE_RSP_x:
•WB (bits 3 and 12): Count writeback (modified or non-modified) transactions by core caches.
•HWPF_L1D (bit 10): Counts hardware generated data read prefetches targeting the L1 data cache (only).
•SWPF_READ (bit 14): Counts software generated data read prefetches by the PREFETCHNTA and 
PREFETCHT0/1/2 instructions.Figure 20-39.  Deducing Implied Leve l 2 Metrics in the Core PMU for12th Ge neration Intel® Co re™ Processor P-core
Table 20-51.  Special Performance Monito ring Events with Counter Restrictions
Event Encoding1
NOTES:
1. Linux perf rUUEE syntax, where UU is the Unit Mask  field and EE is the Event Select (also known as Event
Code) field in the IA32_PERFEVTSELx MSRs.Event Name Counter Restriction
xx3C CPU_CLK_UNHALTED.*
0-7 (No restriction for all architectural events.)
xx2E LONGEST_LAT_CACHE.*
xxDx MEM_*_RETIRED.* 0-3
01A3, 02A3, 08A3 Some CYCLE_ACTIVITY sub-events 0-3
02CD MEM_TRANS_RETIRED.STORE_SAMPLE 004A4 TOPDOWN.BAD_SPEC_SLOTS
0
08A4 TOPDOWN.BR_MISPREDICT_SLOTS
xxCE AMX_OPS_RETIRED 0Light_Operations = Retiring - Heavy_Operations
Machine_Clears = Bad_Speculation - Branch_MispredictsFetch_Bandwidth = Frontend_Bound - Fetch_LatencyCore_Bound = Backend_Bound - Memory_BoundVol. 3B 20-73PERFORMANCE MONITORING
20.3.10.2  E-core Performance Monitoring Unit
The core PMU capabilities on the 12th generation Intel Core processor E-core are summarized in Table 20-52 
below.
20.3.10.2.1  E-core PEBS Load Latency
The 12th generation Intel Core processor E-core includes PEBS Load Latency support similar to that described in 
Section 20.9.7.
When a programmable counter is configured to co unt MEM_UOPS_RETIRED.LOAD_ LATENCY_ABOVE_THRESHOLD 
(IA32_PERFEVTSELx[15:0] = 0xD005, with CMASK=0 and INV=0), selected load operations whose latency 
exceeds the threshold provided in MSR_PEBS_LD_LAT_THRE SHOLD (MSR 03F6H) will be counted. If a PEBS record 
is generated on overflow of this counter, the Memory Acce ss Latency and Memory Auxiliary Info data is reported in 
the Memory Access Info group (Section 20.9.2.2.2). The form ats of these fields are shown in Table 20-53 and Table 
20-94.Table 20-52.  Core PMU Summary of  the Gracemont Microarchitecture 
Box Gracemont 
MicroarchitectureTremont Microarchitecture Comment
Number of fixed-function 
performance-monitoring 
counters per core3 3 Use CPUID to enumerate number of 
Number of general-purpose 
counters per core6 4 Use CPUID to enumerate number of 
Architectural Performance 
Monitoring version ID5 5 See Section 20.2.5.
PEBS record format encoding 0100b 0100b See Section 20.5.5.
EPT-friendly PEBS support Yes No See Section 20.9.5.
Extended PEBS Yes Yes See Section 20.9.1.
Adaptive PEBS Yes Yes See Section 20.9.2.Precise distribution (PDist) PEBS IA32_PMC0 and 
IA32_FIXED_CTR0IA32_PMC0 and 
IA32_FIXED_CTR0PDist eliminates skid, see Section 
20.9.3, Section 20.9.4, and Section 20.9.6.
PEBS Latency Load and Store Latency No See Section 20.3.10.2.1, Section 
20.3.10.2.2, Section 20.9.7, and 
Section 20.9.8.
PEBS Output DS Save  Area or Intel® 
Processor TraceDS Save Area or Intel® 
Processor TraceSee Section 20.5.5.2.1.
Offcore Response MSR 01A6H and 01A7H, 
each core has its own 
register, extended request and response types.MSR 1A6H and 1A7H, each 
core has its own register, 
extended request and response types.See Section 20.5.5.4.
Table 20-53.  E-core PEBS Me mory Access Info Encoding 
Bit(s) Field Description
3:0 Data Source The source of the data; see Table 20-54.4 Lock 0: The operation was not part of a locked transaction.
1: The operation was part of a locked transaction.20-74 Vol. 3BPERFORMANCE MONITORING
For details on E-core PEBS memory access latency encoding, see the Access Latency Field in Table 20-94.
20.3.10.2.2  E-core PEBS Store Latency
The 12th generation Intel Core processor E-core includes PEBS Store Latency support. When a programmable 
counter is configured to count MEM_UOPS_RETIRED.STO RE_LATENCY (IA32_PERFEVTSELx[15:0] = 0xD006, with 
CMASK=0 and INV=0), all store operations will be counted.  If a PEBS record is generated on overflow of this 
counter, the Memory Access Latency and Memory Auxiliary In fo data is reported in the Memory Access Info group 
(Section 18.9.2.2.2). The formats of these fields are shown in Table 20-53 and Table 20-94.
20.3.10.2.3  E-core Precise Distribution (PDist) Support

The 12th generation Intel Core processor E-core supports PEBS with Precise Distribution (PDist) on IA32_PMC0 and 
IA32_FIXED_CTR0. All precise events support PDist save  for UOPS_RETIRED. See Section 20.9.6 for additional 
details on PDist.5 STLB_MISS 0: The load did not miss the STLB (hit the DTLB or STLB).
6 ST_FWD_BLK 0: Load did not get a store forward block.
1: Load got a store forward block.
63:7 Reserved Reserved
Table 20-54.  E-core PEBS  Data Source Encodings
00H Unknown Data Source (the processor could not retrieve th e origin of this request) and MMIO. Memory mapped I/O hit.
01H L1 HIT. This request was sati sfied by the L1 data cache. (M inimal latency core cache hit.)
02H FB HIT. Outstanding core cache miss to same cache-line  address was already underway. (Pending core cache hit.)
03H L2 HIT. This request was satisfied by the L2 cache.
05H L3 HITE. Local or Remote home reques ts that hit the L3 cache and were serviced by another processor core with a 
cross core snoop wher e no modified copies were found (clean).
06H L3 HITM. Local or Remote home reques ts that hit the L3 cache and were serviced by another processor core with a 
cross core snoop where a modified copy was found.
07H Reserved.08H L3 HITF. Local or Remote home reques ts that hit the L3 cache and were serviced by another processor core with a 
cross core snoop wher e a shared or forwarding copy was found.
09H Reserved.
0AH L3 MISS. Local home requests that missed the L3 cache and were  serviced by local DRAM  (go to shared state).
0BH Reserved.0CH Reserved.
0DH Reserved.
0EH I/O. Request of in put/output operation.
0FH The request was to un-cacheable memory.Table 20-53.  E-core PEBS Memory  Access Info Encoding  (Contd.)
Bit(s) Field DescriptionVol. 3B 20-75PERFORMANCE MONITORING
20.3.10.2.4  E-core Enhanced Off-core Response
Event number 0B7H support off-core response monitori ng using an associated configuration MSR, MSR_OFF-
CORE_RSP0 (address 1A6H) in conjunction with UMASK value 01H or MSR_OFFCORE_RSP1 (address 1A7H) in 
conjunction with UMASK value 02H. There are unique pair s of MSR_OFFCORE_RSPx registers per core. The layout 
of MSR_OFFCORE_RSP0 and MSR_OFFCOR E_RSP1 are organized as follows:
•Bits 15:0 and bits 49:44 specify the request type of a transaction request to the uncore. This is described in 
Table 20-55.
•Bits 30:16 specify Response Type information or  an L2 Hit, and is described in Table 20-75.
•If L2 misses, then bits 37:31 can be used to specif y snoop response information and is described in Table 
20-76.
•For outstanding requests, bit 38 can enable measuremen t of average latency of specific type of offcore 
transaction requests using two programmable counte r simultaneously; see Section 20.5.2.3 for details.
20.3.10.3  Unhalted Reference Cycles
The Unhalted Reference Cycles architectural performance moni toring event is enhanced to count at TSC-rate in the 
12th generation Intel Core processor P-core when used on a general-purpose PMC. This enhancement makes it 
consistent with the fixed-function counter 2 and the E-core. As a result, this event is kept enumerated in CPUID leaf 
0AH.EBX (unlike prior hybrid parts).Table 20-55.  MSR_OFFCORE_RS Px Request Type Definition 
DEMAND_DATA_RD 0 Counts demand data reads.
DEMAND_RFO 1 Counts all demand reads for ownership (R FO) requests and software based prefteches for 
exclusive ownership (prefetchw).
DEMAND_CODE_RD 2 Counts demand instruction fetches and L1 instruction cache prefetches.COREWB_M 3 Counts modified write backs from L1 and L2.
HWPF_L2_DATA_RD 4 Counts prefetch (that bring data to L2) data reads.
HWPF_L2_RFO 5 Counts all prefetch (that bring data to L2) RFOs.HWPF_L2_CODE_RD 6 Counts all prefetch (that bring data to MLC only) code reads.
HWPF_L3_DATA_RD 7 Counts L3  cache hardware prefetch data re ads (written to th e L3 cache only).
HWPF_L3_RFO 8 Counts L3 cache hardware prefetch RFOs (written to the L3 cache only) .
HWPF_L3_CODE_RD 9 Counts L3 cache hardware prefet ch code reads (written to the L3 cache only).
HWPF_L1D_AND_SWPF 10 Counts L1 data cache hardware prefetch requests, read for ownership prefetch requests 
and software prefetch requests (except prefetchw).
STREAMING_WR 11 Counts all streaming stores.
COREWB_NONM 12 Counts non-modified write backs from L2.RSVD 14:13 Reserved.
OTHER 15 Counts miscellane ous requests, such as I/O accesses that have  any response type.
UC_RD 44 Counts uncached me mory reads (PRd, UCRdF).
UC_WR 45 Counts uncached memory writes (WiL).
PARTIAL_STREAMING_WR 46 Counts partial (less than 64 byte) streaming stores (WCiL).
FULL_STREAMING_WR 47 Counts full, 64 byte streaming stores (WCiLF).L1WB_M 48 Counts modified WriteBac ks from L1 that miss the L2.
L2WB_M 49 Counts modified WriteBacks from L2.20-76 Vol. 3BPERFORMANCE MONITORING
20.4 PERFORMANCE MONITORING (INTEL® XEON™ PHI PROCESSORS)
NOTE
This section also applies to the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series based on 
Knights Mill microarchitecture.
20.4.1 Intel® Xeon Phi™ Processor 7200/5200/3200 Performance Monitoring 
The Intel® Xeon Phi™ processor 7200/5200/3200 series are base d on the Knights Landing microarchitecture. The 
performance monitoring capabilities are distributed betw een its tiles (pair of processor cores) and untile 
(connecting many tiles in a physical processor package). Functional details of the tiles and untile of the Knights 
Landing microarchitecture can be found in Chapter 16 of In tel® 64 and IA-32 Architectures Optimization Reference 
Manual.
A complete description of the tile and untile PMU programmin g interfaces for Intel Xeon Phi processors based on the 
Knights Landing microarchitecture can be found in the Technical Document section at 
http://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html.
A tile contains a pair of cores attached to a shared L2 cache and is similar to those found in Intel Atom® processors 
based on the Silvermont microarchitecture. The processor provides several new capabilities on top of the Silver-
mont performance monitoring facilities.
The processor supports architectural performance monitoring capability with version ID 3 (see Section 20.2.3) and 
a host of non-architectural performance monitoring capabilities. The processor provides two general-purpose performance counters (IA32_PMC0, IA32_PMC1) and th ree fixed-function performance counters (IA32_-
FIXED_CTR0, IA32_FIXED_CTR1, IA32_FIXED_CTR2).
Non-architectural performance monitoring in the processo r also uses the IA32_PERFEVTSELx MSR to configure a 
set of non-architecture performance monitoring events  to be counted by the corresponding general-purpose 
The bit fields within each IA32_PERFEVTSELx MSR are defi ned in Figure 20-6 and described in Section 20.2.1.1 and 
Section 20.2.3. The processor supports AnyThread counting  in three architectural performance monitoring events.
20.4.1.1  Enhancements of Perf ormance Monitoring in the Intel® Xeon Phi™ Processor Tile
The Intel® Xeon Phi™ processor tile includes the following enhancements to the Silvermont microarchitecture.
•AnyThread support. This facility is limited to following th ree architectural events: Instructions Retired, Unhalted 
Core Cycles, Unhalted Reference Cycles using IA32_FIXED_CTR0-2 and Unhalted Core Cycles, Unhalted 
Reference Cycles using IA32_PERFEVTSELx.
•PEBS-DLA (Processor Event-Based Samp ling-Data Linear Address) fields . The processor provides memory 
address in addition to the Silvermont PEBS record su pport on select events. The PEBS recording format as 
reported by IA32_PERF_CAPABILITIES [11:8] is 2.
transaction responses between the processor tile to subs ystems outside the tile (untile). Counting off-core 
response requires additional event qualification config uration facility in conjunction with IA32_PERFEVTSELx. 
Two off-core response MSRs are provided to use in conjunc tion with specific event codes that must be specified 
with IA32_PERFEVTSELx. Two cores do not share the of f-core response MSRs. Knights Landing expands off-
core response capability to match the processor untile changes.
•Average request latency measurement. The off-core response counting fa cility can be combined to use two 
performance counters to count the o ccurrences and weighted cycles of tr ansaction requests. This facility is 
updated to match the processor untile changes.
20.4.1.1.1  Processor Event-Based Sampling
The processor supports processor event based sampling (P EBS). PEBS is supported using IA32_PMC0 (see also 
Section 18.4.9, “BTS and DS Save Area”).Vol. 3B 20-77PERFORMANCE MONITORING

PEBS uses a debug store mechanism to store a set of architectural state information for the processor. The infor-
mation provides architectural state of the instruction ex ecuted after the instruction that caused the event (See 
Section 20.6.2.4).
The list of PEBS events supported in the processor is shown in the following table.
The PEBS record format 2 supported by processors base d on the Knights Landing microarchitecture is shown in 
Table 20-57, and each field in the PEBS record is 64 bits long. Table 20-56.  PEBS Performance Events for Knights Landing Microarchitecture
Event Name Event Select Sub-event UMask Data Linear
Address Support
BR_INST_RETIRED C4H ALL_BRANCHES 00H No
JCC 7EH NoTAKEN_JCC FEH NoCALL F9H NoREL_CALL FDH NoIND_CALL FBH NoNON_RETURN_IND EBH NoFAR_BRANCH BFH NoRETURN F7H No
BR_MISP_RETIRED C5H ALL_BRANCHES 00H No
JCC 7EH NoTAKEN_JCC FEH NoIND_CALL FBH NoNON_RETURN_IND EBH NoRETURN F7H No
MEM_UOPS_RETIRED 04H L2_HIT_LOADS 02H Yes
L2_MISS_LOADS 04H YesDLTB_MISS_LOADS 08H Yes
RECYCLEQ 03H LD_BLOCK_ST_FORWARD 01H Yes
LD_SPLITS 08H Yes
Table 20-57.  PEBS Record Format for Knights Landing Microarchitecture 
00H R/EFLAGS 60H R100 8 HR / E I P 6 8 HR 1 1
1 0 HR / E A X 7 0 HR 1 2
1 8 HR / E B X 7 8 HR 1 32 0 HR / E C X 8 0 HR 1 4
2 8 HR / E D X 8 8 HR 1 5
30H R/ESI
38H R/EDI 98H PSDLA
40H R/EBP A0H Reserved
48H R/ESP A8H Reserved
50H R8 B0H EventingRIP20-78 Vol. 3BPERFORMANCE MONITORING
20.4.1.1.2  Offcore Response Event
Event number 0B7H support offcore response monitoring  using an associated configuration MSR, MSR_OFF-
conjunction with UMASK value 02H. Table 20-58 lists the ev ent code, mask value and additional off-core configura-
tion MSR that must be programmed to count off-core response events using IA32_PMCx. 
Some of the MSR_OFFCORE_RESP [0,1] register bits are no t valid in this processor and their use is reserved. The 
layout of MSR_OFFCORE_RSP0 and MSR_OFFCORE_RSP1 regi sters are defined in Table 20-59. Bits 15:0 specifies 
the request type of a transaction request to the uncore. Bi ts 30:16 specifies supplier information, bits 37:31 spec-
ifies snoop response information. 
Additionally, MSR_OFFCORE_RSP0 provides bit 38 to enable  measurement of average latency of specific type of 
offcore transaction requests using two programmable coun ter simultaneously, see Section 20.5.2.3 for details. 58H R9 B8H Reserved
Table 20-58.  OffCore Response Event Encoding
PMC0-1 B7H 01H MSR_OFFCORE_RSP0 (address 1A6H)PMC0-1 B7H 02H MSR_OFFCORE_RSP1 (address 1A7H)
Table 20-59.  Bit fields of the MS R_OFFCORE_RESP [0 , 1] Registers
Main Sub-field Bit Name Description
Request Type 0 DEMAND_DATA_RD Demand cacheable data and L1 prefetch data reads.
1 DEMAND_RFO Demand cacheable data writes.2 DEMAND_CODE_RD Demand code reads and prefetch code reads.
3 Reserved Reserved.
4 Reserved Reserved.5 PF_L2_RFO L2 data RFO prefetches (includes PREFETCHW instruction).
6 PF_L2_CODE_RD L2 code HW prefetches.
7 PARTIAL_READS Partial reads (UC or WC).8 PARTIAL_WRITES Partial writes (UC or WT or WP). Valid only for 
OFFCORE_RESP_1 event. Should  only be used on PMC1. 
This bit is reserved for OFFCORE_RESP_0 event.
9 UC_CODE_READS UC code reads.10 BUS_LOCKS Bus locks an d split lock requests.
11 FULL_STREAMING_STO
RESFull streaming stores (WC). Valid only for OFFCORE_RESP_1 
event. Should only be used on PMC1. This bit is reserved for 
OFFCORE_RESP_0 event.
12 SW_PREFETCH Software prefetches.
13 PF_L1_DATA_RD L1 data HW prefetches.
14 PARTIAL_STREAMING_
STORESPartial streaming stores  (WC). Valid only for 
15 ANY_REQUEST Account for any requests.Table 20-57.  PEBS Record Format for Knights Landing Microarchitecture  (Contd.)
Byte Offset Field Byte Offset FieldVol. 3B 20-79PERFORMANCE MONITORING
20.4.1.1.3  Average Offcore Request Latency Measurement
Measurement of average latency of offcore transaction requests can be enabled using MSR_OFFCORE_RSP0.[bit 
38] with the choice of request type sp ecified in MSR_OFFCORE_RSP0.[bit 15:0].
Refer to Section 20.5.2.3, “Average Offcore Request Latency Measurement,” for typical usage. Note that 
MSR_OFFCORE_RESPx registers are not shared between cores in Knights Landing. This allows one core to measure 
average latency while other core is measuring different offcore response events.Response Type Any 16 ANY_RESPONSE Account for any response.
Data Supply from 
Untile17 NO_SUPP No Supplier Details.
18 Reserved Reserved.
19 L2_HIT_OTHER_TILE_N
EAROther tile L2 hit E Near.
20 Reserved Reserved.
21 MCDRAM_NEAR MCDRAM Local.22 MCDRAM_FAR_OR_L2_
HIT_OTHER_TILE_FARMCDRAM Far or Other tile L2 hit far.
23 DRAM_NEAR DRAM Local.
24 DRAM_FAR DRAM Far.
within same tile25 L2_HITM_THIS_TILE M-state.
26 L2_HITE_THIS_TILE E-state.27 L2_HITS_THIS_TILE S-state.
28 L2_HITF_THIS_TILE F-state.
29 Reserved Reserved.30 Reserved Reserved.
Snoop Info; Only 
Valid in case of 
Data Supply from Untile31 SNOOP_NONE None of the cores were snooped.
32 NO_SNOOP_NEEDED No snoop was ne eded to satisf y the request.
33 Reserved Reserved.
34 Reserved Reserved.
35 HIT_OTHER_TILE_FWD Snoop request hit in  the other tile with data forwarded.
36 HITM_OTHER_TILE A snoop was needed and it HitM-ed in other core's L1 cache. 
HitM denotes a cache-line wa s in modified state before 
effect as a result of snoop.
37 NON_DRAM Target was non-DRAM syst em address. This includes MMIO 
Outstanding 
requestsWeighted cycles 38 OU TSTANDING (Valid 
only for 
MSR_OFFCORE_RESP0. 
Should only be used on PMC0. This bit is 
MSR_OFFCORE_RESP1).If set, counts total number of weighted cycles of any 
outstanding offcore requests wi th data response. Valid only 
for OFFCORE_RESP_0 event. Should only be used on PMC0. 
This bit is reserved for OFFCORE_RESP_1 event.Table 20-59.  Bit fields of the MSR_ OFFCORE_RESP [0, 1] Registers (Contd.)
Main Sub-field Bit Name Description20-80 Vol. 3BPERFORMANCE MONITORING
20.5 PERFORMANCE MONITORING  (INTEL ATOM® PROCESSORS)
20.5.1 Performance Monitoring (45 nm and 32 nm Intel Atom® Processors)
45 nm and 32 nm Intel Atom processors report architectural performance monitoring versionID = 3 (supporting the 
aggregate capabilities of versionID 1, 2, and 3; see Sect ion 20.2.3) and a host of non-architectural monitoring 
capabilities. These 45 nm and 32 nm Intel Atom proce ssors provide two general-purpose performance counters 
(IA32_PMC0, IA32_PMC1) and three fixed-function perf ormance counters (IA32_FIXED_CTR0, IA32_FIXED_CTR1, 
IA32_FIXED_CTR2). 
NOTE
The number of counters available to software may vary from the number of physical counters present on the hardware, because an agent running at a higher privilege level (e.g., a VMM) may not expose all counters. CPUID.0AH:EAX[15:8] reports the MSRs available to software; see Section 
20.2.1.
Non-architectural performance monitoring in Intel Atom  processor family uses the IA32_PERFEVTSELx MSR to 
purpose performance counter. The list of non-architectural performance monitoring events can be found at: https://perfmon-events.intel.com/
.
Architectural and non-architectural performance monitori ng events in 45 nm and 32 nm Intel Atom processors 
support thread qualification using bit 21 (AnyThread ) of IA32_PERFEVTSELx MSR, i.e., if IA32_PERFEVT-
SELx.AnyThread =1, event counts include monitored condit ions due to either logical processors in the same 
processor core. 
Valid event mask (Umask) bits can be found at: https://perfmon-events.intel.com/ . The UMASK field may contain 
sub-fields that provide the same qual ifying actions like those listed in Table 20-77, Table 20-78, Table 20-79, and 
Table 20-80. One or more of these sub-fields may apply to  specific events on an event-by-event basis. Precise 
Event Based Monitoring is supported using IA32_PMC0 (see also Section 18.4.9, “BTS and DS Save Area”).
20.5.2 Performance Monitoring for Silvermont Microarchitecture
Intel processors based on the Silvermont microarchitectur e report architectural performance monitoring versionID 
= 3 (see Section 20.2.3) and a host of non-architectural monitoring capabilities. Intel processors based on the Silvermont microarchitecture provide two general-pu rpose performance counters (IA32_PMC0, IA32_PMC1) and 
three fixed-function performance counters (IA32_FIX ED_CTR0, IA32_FIXED_CTR1, IA32_FIXED_CTR2). Intel

three fixed-function performance counters (IA32_FIX ED_CTR0, IA32_FIXED_CTR1, IA32_FIXED_CTR2). Intel 
Atom processors based on the Airmont microarchitecture support the same performance monitoring capabilities as those based on the Silvermont microarchitecture.
Non-architectural performance monitoring in the Silver mont microarchitecture uses the IA32_PERFEVTSELx MSR 
to configure a set of non-architecture performance monito ring events to be counted by the corresponding general-
https://perfmon-events.intel.com/
.
The bit fields (except bit 21) within each IA32_PERFEVT SELx MSR are defined in Figure 20-6 and described in 
Section 20.2.1.1 and Section 20.2.3. Architectural and no n-architectural performance monitoring events in the 
Silvermont microarchitecture ignore the AnyThread qualif ication regardless of its setting in IA32_PERFEVTSELx 
MSR. 
20.5.2.1  Enhancements of Performance Monitoring  in the Processor Core
•The width of counter reported by CPUID.0AH:EAX[23:16] is 40 bits. Vol. 3B 20-81PERFORMANCE MONITORING
•Average request latency measurement. The off-core response counting facility can be combined to use two 
performance counters to count the occurrences and weighted cycles of transaction requests.
20.5.2.1.1  Processor Event Based Sampling (PEBS)
In the Silvermont microarchitecture, the PEBS facility ca n be used with precise events. PEBS is supported using 
IA32_PMC0 (see also Section 18.4.9). 
Section 20.6.2.4). 
The list of precise events supported in the Silv ermont microarchitecture is shown in Table 20-60.
PEBS Record Format The PEBS record format supported by  processors based on the Intel Silvermont microarchi-
tecture is shown in Table 20-61, and each field in the PEBS record is 64 bits long. Table 20-60.  PEBS Performance Events for the Silvermont Microarchitecture
BR_INST_RETIRED C4H ALL_BRANCHES 00H
JCC 7EHTAKEN_JCC FEHCALL F9HREL_CALL FDHIND_CALL FBHNON_RETURN_IND EBHFAR_BRANCH BFHRETURN F7H
BR_MISP_RETIRED C5H ALL_BRANCHES 00H
JCC 7EHTAKEN_JCC FEHIND_CALL FBHNON_RETURN_IND EBHRETURN F7H
MEM_UOPS_RETIRED 04H L2_HIT_LOADS 02H
L2_MISS_LOADS 04HDLTB_MISS_LOADS 08HHITM 20H
REHABQ 03H LD_BLOCK_ST_FORWARD 01H
LD_SPLITS 08H20-82 Vol. 3BPERFORMANCE MONITORING
20.5.2.2  Offcore Response Event
conjunction with UMASK value 02H. Table 20-62 lists the ev ent code, mask value and additional off-core configura-
In the Silvermont microarchitecture, each MSR_OFFCORE_RSPx is shared by two processor cores.
The layout of MSR_OFFCORE_RSP0 an d MSR_OFFCORE_RSP1 are shown in Figure 20-40 and Figure 20-41. Bits 
15:0 specifies the request type of a transaction request to  the uncore. Bits 30:16 spec ifies supplier information, 
bits 37:31 specifies snoop response information. 
offcore transaction requests using two programmable coun ter simultaneously, see Section 20.5.2.3 for details. Table 20-61.  PEBS Record Format for the Silvermont Microarchitecture
30H R/ESI
38H R/EDI 98H Reserved
50H R8 B0H EventingRIP
58H R9 B8H Reserved
Table 20-62.  OffCore Response Event Encoding
PMC0-1 B7H 01H MSR_OFFCORE_RSP0 (address 1A6H)
PMC0-1 B7H 02H MSR_OFFCORE_RSP1 (address 1A7H)Vol. 3B 20-83PERFORMANCE MONITORING
Figure 20-40.  Request_Type Fields for MSR_OFFCORE_RSPx 
Table 20-63.  MSR_OFFCORE_RSPx Request_Type Field Definition
demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.
DMND_RFO 1 Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by 
a write to data cacheline. Does  not count L2 RFO prefetches.
DMND_IFETCH 2 Counts the number of demand instruction ca cheline reads and L1 instru ction cacheline prefetches.
PARTIAL_READ 7 Counts the number of  demand reads of partial cach e lines (including UC and WC).
PARTIAL_WRITE 8 Counts the number of demand RFO requests to write to partial cache lines (includes UC, WT, and 
WP).
UC_IFETCH 9 Counts the number of UC instruction fetches.BUS_LOCKS 10 Bus lock an d split lock requests.
STRM_ST 11 Streaming store requests.
SW_PREFETCH 12 Counts software prefetch requests.PF_DATA_RD 13 Counts DCU hardware prefetcher data read requests.
PARTIAL_STRM_ST 14 Streaming store requests.
ANY 15 Any request that cr osses IDI, in cluding I/O.REQUEST TYPE — Any (R/W)
REQUEST TYPE — PARTIAL_STRM_ST (R/W) 87 0
REQUEST TYPE — UC_IFETCH (R/W)
REQUEST TYPE — PARTIAL_WRITE (R/W)
REQUEST TYPE — PARTIAL_READ (R/W)
REQUEST TYPE — PF_RFO (R/W)REQUEST TYPE — PF_DATA_RD (R/W)REQUEST TYPE — WB (R/W)REQUEST TYPE — DMND_IFETCH (R/W)
See Figure 18-30
REQUEST TYPE — PF_DATA_RD (R/W) 
REQUEST TYPE  — SW_PREFETCH (R/W)20-84 Vol. 3BPERFORMANCE MONITORING
To properly program this extra register, software must set at least one request type  bit (Table 20-63) and a valid 
response type pattern (Table 20-64, Table 20-65). Otherwise,  the event count reported will be zero. It is permis-
sible and useful to set multiple request and response type  bits in order to obtain various classes of off-core 
response events. Although MSR_OFFCORE_RSPx allow an agent software to program numerous combinations that 
meet the above guideline, not all co mbinations produce meaningful data.
ANY | [(‘OR’ of Supplier Info Bits) & (‘OR’ of Snoop Info Bits)]If “ANY” bit is set, the supplier and snoop info bits are ignored.Figure 20-41.  Response_Supplier and Sn oop Info Fields for MSR_OFFCORE_RSPx 
Table 20-64.  MSR_OFFCORE_RSP_x Resp onse Supplier Info Field Definition
Common ANY_RESPONSE 16 Catch all value for any response types.
Supplier Info Reserved 17 Reserved
L2_HIT 18 Cache reference hit L2 in either M/E/S states.
Reserved 30:19 Reserved
Table 20-65.  MSR_OFFCORE_RSPx Snoop Info Field Definition
Snoop 
Reserved 32 Reserved
SNOOP_MISS 33 Counts the number of snoop misses when L2 misses.
SNOOP_HIT 34 Counts the number of snoops hit in the other module where no modified copies were 
found.
Reserved 35 ReservedRESPONSE TYPE — NON_DRAM (R/W)
RESERVED33 1934 17
RSPNS_SNOOP — SNOOP_HIT (R/W)
RSPNS_SNOOP — SNOOP_MISS (R/W)
RESERVEDRSPNS_SNOOP — SNOOP_NONE (R/W)RESERVEDRSPNS_SUPPLIER — L2_HIT (R/W)RESERVED
RESET Value — 00000000_00000000H38
AVG LATENCY — ENABLE AVG LATENCY(R/W)Vol. 3B 20-85PERFORMANCE MONITORING
20.5.2.3  Average Offcore Request Latency Measurement

Snoop 
found.
Average latency for offcore transactions can be determin ed by using both MSR_OFFCORE_RSP registers. Using two 
performance monitoring counters, program the two OFFC ORE_RESPONSE event encodings into the corresponding 
IA32_PERFEVTSELx MSRs. Count the weighted cycles via MSR_OFFCORE_RSP0 by progra mming a request type in 
MSR_OFFCORE_RSP0.[15:0] and setting MSR_OFFCORE_ RSP0.OUTSTANDING[38] to 1, white setting the 
remaining bits to 0. Count the number of requests vi a MSR_OFFCORE_RSP1 by programming the same request 
type from MSR_OFFCORE_RSP0 into MSR_OFFCORE_RSP1 [bit 15:0], and setting MSR_OFFCORE_RSP1.ANY_RE-
SPONSE[16] = 1, while setting the remaining bits to 0. Th e average latency can be obtained by dividing the value 
of the IA32_PMCx register that counted weight cycles by the register that counted requests.
20.5.3 Performance Monitoring for Goldmont Microarchitecture
Intel Atom processors based on the Goldmont microarchitecture report architectural performance monitoring 
versionID = 4 (see Section 20.2.4) and support non-architectural monitoring capabilities described in this section.
Architectural performance monitoring version 4 capabilities are described in Section 20.2.4.
The bit fields (except bit 21) within each IA32_PERFEVTSELx MSR are defined in Figure 20-6 and described in 
Section 20.2.1.1 and Section 20.2.3. The Goldmont microa rchitecture does not support Hyper-Threading and thus 
architectural and non-architectural performance monitoring  events ignore the AnyThr ead qualification regardless 
of its setting in the IA32_PERFEVTSELx MSR. However,  Goldmont does not set the AnyThread deprecation bit 
(CPUID.0AH:EDX[15]).
The core PMU’s capability is similar to that of the Silv ermont microarchitecture described in Section 20.5.2, with 
some differences and enhancements summarized in Table 20-66.HITM 36 Counts the number of snoops hit in the other module where modified copies were 
found in other core's L1 cache.
NON_DRAM 37 Target was non-DRAM system addr ess. This includes MMIO transactions.
AVG_LATENCY 38 Enable average latency measurement by counting weighted cycles of outstanding 
offcore requests of the request type specified in bits 15:0 and any response (bits 37:16 cleared to 0). 
This bit is available in MSR_OFFCORE_RESP0. The weighted cycles is accumulated in the 
specified programmable counter IA32_PMCx and the occurrence of specified requests are counted in the othe r programmable counter.
Table 20-66.  Core PMU Comparison Between th e Goldmont and Silvermo nt Microarchitectures
Box Goldmont Microarchitecture Silv ermont Microarchitecture Comment
# of Fixed counters per core 3 3 Use CPUID to determine # 
20.2.1.
counters per core4 2 Use CPUID to determine # 
Counter width (R,W) R:48, W: 32/4 8 R:40, W:32 See Section 20.2.2.
Monitoring version ID4 3 Use CPUID to determine # 
of counters. See Section 20.2.1.Table 20-65.  MSR_OFFCORE_RSPx Sn oop Info Field Definition (Contd.)
Subtype Bit Name Offset Description20-86 Vol. 3BPERFORMANCE MONITORING
20.5.3.1  Processor Even t Based Sampling (PEBS)
Processor event based sampling (PEBS) on the Goldmont microarchitecture is enhanced over prior generations 
with respect to sampling support of precise events and non-precise events. In the Goldmont microarchitecture, 
PEBS is supported using IA32_PMC0 for all events (see Section 18.4.9). 
PEBS uses a debug store mechanism to store a set of architectural state information for the processor at the time 
the sample was generated. 
Precise events work the same way on  Goldmont microarchitecture as on the Silvermont microarchitecture. The 
record will be generated after an instruction that causes  the event when the counter is already overflowed and will 
capture the architectural state at this point (see Section 20.6.2.4 and Section 18.4.9). The eventingIP in the record 
will indicate the instruction that caused the event. The list  of precise events supported in the Goldmont microarchi-
tecture is shown in Table 20-67.PMI Overhead Mitigation • Freeze_Perfmon_on_PMI with 
streamlined semantics for branch profiling.•F r e e z e _ P e r f m o n _ o n _ P M I  w i t h  
semantics for branch profiling.See Section 18.4.7.
Legacy semantics not 
supported with version 4 
or higher.
Counter and Buffer 
Overflow Status 
Management•Q u e r y  v i a  
•R e s e t  v i a  
IA32_PERF_GLOBAL_STATUS_R
ESET
•S e t  v i a  
IA32_PERF_GLOBAL_STATUS_S
ET• Query via 
•R e s e t  v i a  
IA32_PERF_GLOBAL_OVF_CTRLSee Section 20.2.4.
IA32_PERF_GLOBAL_STATU
S Indicators of 
Overflow/Overhead/Interfer
ence• Individual counter overflow
• PEBS buffer overflow
• ToPA buffer overflow
• CTR_Frz, LBR_Frz• Individual counter overflow
• PEBS buffer overflowSee Section 20.2.4.
IA32_PERF_GLOBAL_STATUS • CTR_Frz, 
•L B R _ F r zNo See Section 20.2.4.1.
IndicatorQuery IA32_PERF_GLOBAL_INUSE No See Section 20.2.4.3.
Sampling (PEBS) EventsGeneral-Purpose Counter 0 only. 
Supports all events (precise and 
non-precise). Precise events are 
listed in Table 20-67 .See Section 20.5.2.1.1. General-
Purpose Counter 0 only. Only 
supports precise events (see 
Table 20-60) .IA32_PMC0 only.
PEBS record format 
encoding0011b 0010b
Reduce skid PEBS IA32_PMC0 only No
PEBS record layout Table 20-68; enhanced fields at 
offsets 90H- 98H; and TSC record 
field at C0H.Table 20-61.
PEBS EventingIP Yes Yes
Off-core Response Event MSR 1A6H and 1A7H, each core 
has its own register.MSR 1A6H and 1A7H, shared by a 
pair of cores.Nehalem supports 1A6H 
only.Table 20-66.  Core PMU Comparison Between th e Goldmont and Silvermont Microarchitectures
Box Goldmont Microarchitecture Silv ermont Microarchitecture CommentVol. 3B 20-87PERFORMANCE MONITORING
In the Goldmont microarchitecture, the PEBS facility al so supports the use of non-precise events to record 
processor state information into PEBS records with the same format as with precise events.
However, a non-precise event may not be attributable to a particular retired instruction or the time of instruction 
execution. When the counter overflows, a PEBS record w ill be generated at the next opportunity. Consider the 
event ICACHE.HIT. When the counter overflows, the processor is fetching future instruct ions. The PEBS record will 
be generated at the next opportunity and capture the state at  the processor's current retirement point. It is likely 
that the instruction fetch that caused the event to increment was beyond that current retirement point. Other examples of non-precise events are CPU_CLK_UN HALTED.CORE_P and HARDWARE_INTERRUPTS.RECEIVED. 
CPU_CLK_UNHALTED.CORE_P will increment each cycle that the processor is awake. When the counter over-flows, 
there may be many instructions in vari ous stages of execution. Additionally, zero, one or multiple instructions may 
be retired the cycle that the counter overflows. HARD WARE_INTERRUPTS.RECEIVED increments independent of 
any instructions being executed. For all non-precise events, the PEBS record will be generated at the next oppor-
tunity, after the counter has overflowed. The PEBS facility thus allows for identification of the instructions which 
were executing when the event overflowed.
After generating a record for a non-precise event, the PEBS  facility reloads the counter and resumes execution, just 
as is done for precise events. Unlike interrupt-based samplin g, which requires an interrupt service routine to collect 
the sample and reload the counter, the PEBS facility can collect samples even when interrupts are masked 
and 
without using NMI . Since a PEBS record is generated immediately when a counter for a non-precise event is 
enabled, it may also be generated after an overflow is set by an MSR write to IA32_PERF_GLOBAL_STATUS_SET.
Table 20-67.  Precise Events Supporte d by the Goldmont Microarchitecture
LD_BLOCKS 03H DATA_UNKNOWN 01H
STORE_FORWARD 02H4K_ALIAS 04HUTLB_MISS 08HALL_BLOCK 10H
MISALIGN_MEM_REF 13H LOAD_PAGE_SPLIT 02H
STORE_PAGE_SPLIT 04H
INST_RETIRED C0H ANY 00HUOPS_RETITRED C2H ANY 00H
LD_SPLITSMS 01H
JCC 7EHTAKEN_JCC FEHIND_CALL FBHNON_RETURN_IND EBHRETURN F7H20-88 Vol. 3BPERFORMANCE MONITORING
The PEBS record format supported by processors ba sed on the Goldmont microarchitecture is shown in 
Table 20-68, and each field in the PEBS record is 64 bits long. 
On Goldmont microarchitecture, all 64 bits of architectura l registers are written into the PEBS record regardless of 
processor mode.

With PEBS record format encoding 0011b, offset 90H repo rts the “Applicable Counter” field, which indicates which 
counters actually requested generating a PEBS record. Th is allows software to correlate the PEBS record entry 
properly with the instruction that caused the event even  when multiple counters are configured to record PEBS 
records and multiple bits are set in the field. Additionally , offset C0H captures a snapshot of the TSC that provides 
a time line annotation for each PEBS record entry.MEM_UOPS_RETIRED D0H ALL_LOADS 81H
ALL_STORES 82HALL 83HDLTB_MISS_LOADS 11HDLTB_MISS_STORES 12HDLTB_MISS 13H
MEM_LOAD_UOPS_RETIRED D1H L1_HIT 01H
L2_HIT 02HL1_MISS 08HL2_MISS 10HHITM 20HWCB_HIT 40HDRAM_HIT 80H
Table 20-68.  PEBS Record Format for the Goldmont Microarchitecture
08H R/EIP 70H R12
10H R/EAX 78H R1318H R/EBX 80H R14
20H R/ECX 88H R15
28H R/EDX 90H Applicable Counters30H R/ESI 98H Data Linear Address
38H R/EDI
A0H Reserved
40H R/EBP A8H Reserved
48H R/ESP B0H EventingRIP
50H R8 B8H Reserved
58H R9 C0H TSC60H R10Table 20-67.  Precise Events Supported by  the Goldmont Microarchitecture (Contd.)
Event Name Event Select Sub-event UMaskVol. 3B 20-89PERFORMANCE MONITORING
20.5.3.1.1  PEBS Data Linear Address Profiling
Goldmont supports the Data Linear Address field introduc ed in Haswell. It does not support the Data Source 
Encoding or Latency Value fields that are also part of Data Address Profiling; those fields are present in the record 
but are reserved. 
For Goldmont microarchitecture, the Data Linear Address field will record the linear address of memory accesses in 
the previous instruction (e.g., the one that triggered a prec ise event that caused the PEBS record to be generated). 
Goldmont microarchitecture may record a Data Linear Address for the instruction that caused the event even for events not related to memory accesses. This may differ from other microarchitectures.
20.5.3.1.2  Reduced Skid PEBS
Processors based on Goldmont Plus microarchitecture supp ort the Reduced Skid PEBS feature described in Section 
20.9.4 on the IA32_PMC0 counter. Although Extended PEBS adds support for generating PEBS records for precise 
events on additional general-purpose and fixed-function performance counters, those counters do not support the 
Reduced Skid PEBS feature.
20.5.3.1.3  Enhancements to IA32 _PERF_GLOBAL_STATU S.OvfDSBuffer[62] 
In addition to IA32_PERF_GLOBAL_STATUS.OvfDSBuffer[62]  being set when PEBS_Index reaches the PEBS_Inter-
rupt_Theshold, the bit is also set when PEBS_Index is out of bounds. That is, the bit will be set when PEBS_Index 
< PEBS_Buffer_Base or PEBS_Index > PEBS_Absolute_Maximum. Note that when an out of bound condition is 
encountered, the overflow bits in IA32_PERF_GLOBAL_STAT US will be cleared according to Applicable Counters, 
however the IA32_PMCx values will not be reloaded  with the Reset values stored in the DS_AREA.
20.5.3.2  Offcore Response Event
conjunction with UMASK value 02H. Table 20-62 lists the ev ent code, mask value and additional off-core configu-
ration MSR that must be programmed to coun t off-core response events using IA32_PMCx. 
The Goldmont microarchitecture provides unique pairs of MSR_OFFCORE_RSPx registers per core.
The layout of MSR_OFFCORE_RSP0 and MSR_ OFFCORE_RSP1 are organized as follows:
•Bits 15:0 specifies the request type of a transaction re quest to the uncore. This is described in Table 20-69.
•Bits 30:16 specifies common supplier information or an L2 Hit, and is described in Table 20-64. 
•If L2 misses, then Bits 37:31 can be used to spec ify snoop response information and is described in 
Table 20-70. 
transaction requests using two programmable counte r simultaneously; see Section 20.5.2.3 for details. 
Table 20-69.  MSR_OFFCORE_RSPx Request_Type Field Definition
DEMAND_DATA_RD 0 Counts cacheline read requests due to demand reads (excludes prefetches).
DEMAND_RFO 1 Counts cacheline read for ownership (R FO) requests due to demand writes (excludes 
prefetches).
DEMAND_CODE_RD 2 Counts demand inst ruction cacheline and I-side pr efetch requests  that miss the 
instruction cache.
COREWB 3 Counts writeback transactions caused by L1 or L2 cache evictions.
PF_L2_DATA_RD 4 Counts da ta cacheline reads ge nerated by hardware L2 cache prefetcher.
PF_L2_RFO 5 Counts reads for ownership (RFO) requests generated by L2 prefetcher.
Reserved 6 Reserved.20-90 Vol. 3BPERFORMANCE MONITORING
response type pattern (either Table 20-64 or Table 20-70). Ot herwise, the event count reported will be zero. It is 
permissible and useful to set multiple request and response type bits in order to obtain various classes of off-core 
Any_Response Bit | L2 Hit | ‘OR’ of  Snoop Info Bits | Outstanding Bit
20.5.3.3  Average Offcore Request Latency Measurement
In Goldmont microarchitecture, measurement of average latency of offcore transaction requests is the same as 
described in Section 20.5.2.3.PARTIAL_READS 7 Counts demand data partial reads, in cluding data in uncachea ble (UC) or uncacheable 
(WC) write combining memory types.
PARTIAL_WRITES 8 Counts partial writes, including uncacheable (UC), write through (WT) and write 
protected (WP) memory type writes.
UC_CODE_READS 9 Counts code reads in uncacheable (UC) memory region.BUS_LOCKS 10 Counts bus lock and split lock requests.
FULL_STREAMING_STORES 11 Counts full cacheline writes due to streaming stores.
SW_PREFETCH 12 Counts cacheline requests due to software prefetch instructions.PF_L1_DATA_RD 13 Counts data cach eline reads generated by hardware L1 data cache prefetcher.
PARTIAL_STREAMING_STORES 14 Counts partial cacheline writes due to streaming stores.
ANY_REQUEST 15 Counts requests  to the unco re subsystem.
Table 20-70.  MSR_OFFCORE_RSPx For L2 Miss and Outstanding Requests
L2_MISS 
(Snoop Info)Reserved 32:31 Reserved
L2_MISS.SNOOP_MISS_O
R_NO_SNOOP_NEEDED33 A true miss to this modu le, for which a snoop request missed the other module or 
no snoop was performed/needed. 
L2_MISS.HIT_OTHER_CO
RE_NO_FWD34 A snoop hit in the other processor module, but no data forwarding is required.
Reserved 35 Reserved
L2_MISS.HITM_OTHER_C
ORE36 Counts the number of snoops hit in th e other module or other core's L1 where 
modified copies were found.
L2_MISS.NON_DRAM 37 Target was a non-DRAM system  address. This includ es MMIO transactions.
requests1
NOTES:
1. See Section 20.5.2.3, “Average Offcore Request Latency Measurem ent,” for details on how to use this bit to extract average l atency.OUTSTANDING 38 Counts weighted cycles of outsta nding offcore requests of the request type 
specified in bits 15:0, from the time  the XQ receives the request and any 
response is received. Bits 37 :16 must be set to 0. This  bit is only available in 
MSR_OFFCORE_RESP0.Table 20-69.  MSR_OFFCORE_RSPx Requ est_Type Field Definition (Contd.)
Bit Name Offset DescriptionVol. 3B 20-91PERFORMANCE MONITORING
20.5.4 Performance Monito ring for Goldmont Plus Microarchitecture
Intel Atom processors based on the Goldmont Plus microarchitecture report architectural performance monitoring 
versionID = 4 and support non-architectural monitoring capabilities described in this section.
Goldmont Plus performance monitoring capabilities are similar to Goldmont capabilities. The differences are in 
specific events and in which counters support PEBS. Gold mont Plus introduces the ability for fixed performance 
monitoring counters to generate PEBS records. 
Goldmont Plus will set the AnyThread deprecation CPUID bi t (CPUID.0AH:EDX[15]) to indi cate that the Any-Thread 
bits in IA32_PERFEVTSELx and IA32_FIXED_CTR_CTRL have no effect. 
The core PMU's capability is similar to that of the Goldmont microarchitecture described in Section 20.6.3, with 
some differences and enhancements summarized in Table 20-71.
20.5.4.1  Extended PEBS
The PEBS facility in Goldmont Plus microarchitecture pr ovides a number of enhancements relative to PEBS in

The PEBS facility in Goldmont Plus microarchitecture pr ovides a number of enhancements relative to PEBS in 
processors from previous generations. Enhancement of PEBS facility with the Exte nded PEBS feature are de-
scribed in detail in section 18.9.
20.5.5 Performance Monitoring  for Tremont Microarchitecture
Intel Atom processors based on the Tremont microarchitecture report architectural performance monitoring 
versionID = 5 and support non-architectural monito ring capabilities described in this section. 
Architectural performance monitoring version 5 capabilities are described in Section 20.2.5.
Tremont performance monitoring capabilities are similar to Goldmont Plus capabilities, with the following exten-
sions:
•Support for Adaptive PEBS.
•Support for PEBS output to Intel® Processor Trace.
•Precise Distribution support on Fixed Counter0.
•Compatibility enhancements to off-core response MSRs, MSR_OFFCORE_RSPx.Table 20-71.  Core PMU Comparis on Between the Goldmont Plus and Goldmont Microarchitectures
Box Goldmont Plus Microarchitecture Goldmont Microarchitecture Comment
20.2.1.
counters per core4 4 Use CPUID to determine # 
20.2.1.
Counter width (R,W) R:48, W: 32/48 R:48, W: 32/48 No change.
Monitoring version ID4 4 No change.
Sampling (PEBS) EventsAll General-Purp ose and Fixed 
counters. Each General-Purpose 
counter supports al l events (precise 
and non-precise).General-Purpose Counter 0 only. 
non-precise). Precise events are listed in Table 20-67 .Goldmont Plus supports 
PEBS on all counters.
encoding0011b 0011b No change.20-92 Vol. 3BPERFORMANCE MONITORING
The differences and enhancements between Tremont microa rchitecture and Goldmont Plus microarchitecture are 
summarized in Table 20-72.
20.5.5.1  Adaptive PEBS
The PEBS record format and configuration interface has changed versus Goldmont Plus, as the Tremont microarchi-tecture includes support for the configurable Adaptive PEBS records; see Section 20.9.2.
20.5.5.2  PEBS output to  Intel® Processor Trace
Intel Atom processors based on the Tremont microarchitecture introduce the following Precise Event-Based 
Sampling (PEBS) extensions:
•A mechanism to direct PEBS output into the Intel® Processor Trace (Intel® PT) output stream. In this scenario, 
the PEBS record is written in packetized form, in order to co-exist with other Intel PT trace data. 
•New Performance Monitoring counter reload MSRs, which are used by PEBS in place of the counter reload 
values stored in the DS Management area when PEBS output is directed into the Intel PT output stream.
Processors that indicate support for Intel PT by setti ng CPUID.07H.0.EBX[25]=1, and set the new IA32_PERF_CA-
PABILITIES.PEBS_OUTPUT_PT_AVAIL[16] bit, support these extensions.
20.5.5.2.1  PEBS Configuration
PEBS output to Intel Processor Trace includes support for two new fields in IA32_PEBS_ENABLE.Table 20-72.  Core PMU Comparison Between the Tremont and Goldmont Plus Microarchitectures
Box Tremont Microarchitecture Goldmo nt Plus Microarchitecture Comment
# of fixed counters per core 3 3 Use CPUID to determine # 
20.2.1.
20.2.1.
Counter width (R,W) R:48, W: 32/48 R:4 8, W: 32/48 No change. See Section 
20.2.2.
Monitoring version ID54  
encoding0100b 0011b See Section 20.6.2.4.2.
Reduce skid PEBS IA32_PMC0 and IA32_FIXED_CTR0 IA32_PMC0 only
Extended PEBS Yes Yes See Section 20.5.4.1.
PEBS output DS Save Ar ea or Intel® Processor 
TraceDS Save Area only See Section 20.5.5.2.1.
PEBS record layout See Section 20.9.2.3 for output to 
DS, Section 20.5.5.2.2 for output to 
Intel PT.Table 20-68; enhanced fields at 
field at C0H.
has its own register, extended 
request and re sponse types.MSR 1A6H and 1A7H, each core has 
its own register.Vol. 3B 20-93PERFORMANCE MONITORING
When PEBS_OUTPUT is set to 01B, the DS Management Area is not used and need not be configured. Instead, the 
output mechanism is configured through IA32_RTIT_CTL an d other Intel PT MSRs, while counter reload values are 
configured in the MSR_RELOAD_PMCx MSRs. Details on co nfiguring Intel PT can be found in Section 33.2.7.
20.5.5.2.2  PEBS Record Format in Intel® Processor Trace
The format of the PEBS record changes when output to Intel PT, as the PEBS state is packetized. Each PEBS 
grouping is emitted as a Block Begin (BBP) and following Block Item (BIP) packets. A PEBS grouping ends when 
either a new PEBS grouping begins (indicated by a BBP packet) or a Block End (BEP) packet is encountered. See 
Section 33.4.1.1 for details of these Intel PT packets.
Because the packet headers describe the state held in the pa cket payload, PEBS state ordering is not fixed. PEBS 
state groupings may be emitted in any order, and the PEBS  state elements within those groupings may be emitted 
in any order. Further, there is no packet that provides indication of “Record Format” or “Record Size”.
If Intel PT tracing is not enabled (IA32_RTIT_STATUS.Tri ggerEn=0), any PEBS records triggered will be dropped. 
PEBS packets do not depend on ContextEn or FilterEn in IA32_RTIT_STATUS, any filtering of PEBS must be enabled 
from within the PerfMon configuration. Counter reload will  occur in all scenarios where PEBS is triggered, regard-
less of TriggerEn.Table 20-73.  New Fields in IA32_PEBS_ENABLE
PMI_AFTER_EACH_RECORD[60] Pend a PerfMon Interrupt (PMI) after each PEBS event.PEBS_OUTPUT[62:61] Specifies PEBS output destination. Encodings:
00B: DS Save Area. Matches legacy PEBS behavior, output location defined by IA32_DS_AREA.01B: Intel PT trace output.
10B: Reserved.
11B: Reserved.
Figure 20-42.  IA32_PEBS_ENABLE MSR with PEBS Output to Intel® Processor Trace m                             1   0 63  62 61 60
PEBS_EN_FIXED 0 (R/W)
PEBS_EN_PMC0 (R/W)PEBS_EN_FIXED 1 (R/W)n                         32  31
Reserved RESET Value – 00000000 _00000000 H PMI_AFTER_EACH_RECORD (R/W)PEBS_OUTPUT (R/W)●  ●  ● ●  ●  ●
PEBS_EN_PMCm (R/W)PEBS_EN_FIXEDn (R/W)20-94 Vol. 3BPERFORMANCE MONITORING
The PEBS threshold mechanism for generating PerfMon Inte rrupts (PMIs) is not available in this mode. However, 
there exist other means to generate PMIs based on PEBS  output. When the Intel PT ToPA output mechanism is 
chosen, a PMI can optionally be pended when a ToPA region is filled; see Section 33.2.7.2 for details. Further, soft-
ware can opt to generate a PMI on each PE BS record by setting the new IA32_PEBS_EN-
ABLE.PMI_AFTER_EACH_RECORD[60] bit.
The IA32_PERF_GLOBAL_STATUS.OvfDSBuffe r bit will not be set in this mode.
20.5.5.2.3  PEBS Counter Reload
When PEBS output is directed into Intel PT (IA 32_PEBS_ENABLE.PEBS_OUTPUT = 01B), new MSR_RELOAD_PMCx 
MSRs are used by the PEBS routine to reload PerfMon counters. The value from the associated reload MSR will be 
loaded to the appropriate counter on each PEBS event.
20.5.5.3  Precise Distribution  Support on Fixed Counter 0
The Tremont microarchitecture supports the PDIR (Precise Di stribution of Retired Instructions) facility, as described 
in Section 20.3.4.4.4, on Fixed Counter 0. Fixed Counte r 0 counts the INST_RETIRED.ALL event. PEBS skid for 
Fixed Counter 0 will be precisely one instruction.
This is in addition to the re duced skid PEBS behavior on IA32_PMC0; see Section 20.5.3.1.2.
20.5.5.4  Compatibility Enhancem ents to Offcore Response MSRs
The Off-core Response facility is similar to that described in Section 20.5.3.2.
The layout of MSR_OFFCORE_RSP0 and MSR_OFFCORE_RSP1 are organized as shown below. RequestType bits are 
defined in Table 20-74, ResponseType bits in Table 20-75, and SnoopInfo bits in Table 20-76.
Table 20-74.  MSR_OFFCORE_RS Px Request Type Definition 
DEMAND_RFO 1 Counts all demand reads for ownership (RFO) requests and software based 
prefetches for exclusive ownership (prefetchw).
HWPF_L2_RFO 5 Counts all prefetch (that bring data to L2) RFOs.HWPF_L2_CODE_RD 6 Counts all prefetch (that bring data to L2 only) code reads.
Reserved 9:7 Reserved.
HWPF_L1D_AND_SWPF 10 Counts L1 data  cache hardware prefet ch requests, read for ownership prefetch 
requests and software prefetch requests (except prefetchw).
STREAMING_WR 11 Counts all streaming stores.COREWB_NONM 12 Counts non-modified write backs from L2.
Reserved 14:13 Reserved.
OTHER 15 Counts miscellane ous requests, such as I/O accesses that have any response type.

PARTIAL_STREAMING_WR 46 Counts partial (le ss than 64 byte) streaming stores (WCiL).
FULL_STREAMING_WR 47 Counts full, 64  byte streaming stores (WCiLF).Vol. 3B 20-95PERFORMANCE MONITORING
L1WB_M 48 Counts modified WriteBac ks from L1 th at miss the L2.
L2WB_M 49 Counts modified WriteBacks from L2.
Table 20-75.  MSR_OFFCORE_RSPx Response Type Definition
Bit Name Offset DescriptionANY_RESPONSE 16 Catch all valu e for any response types.
L3_HIT_M 18 LLC/L3 Hit - M-state.
L3_HIT_E 19 LLC/L3 Hit - E-state.
L3_HIT_S 20 LLC/L3 Hit - S-state.L3_HIT_F 21 LLC/L3 Hit - I-state.LOCAL_DRAM 26 LLC/L3 Miss, DRAM Hit.
OUTSTANDING 63 Average latency of outstanding requ ests with the other co unter counting number 
of occurrences; can also can be used to count occupancy.
Table 20-76.  MSR_OFFCORE_RSPx Snoop Info Definition
SNOOP_NONE 31 None of the cores were snooped.
• LLC miss and Dram data retu rned directly to the core.
SNOOP_NOT_NEEDED 32 No snoop ne eded to satisfy the request.
• LLC hit and CV bit(s) (core valid) was not set.
SNOOP_MISS 33 A snoop was sent but missed.
• LLC hit and CV bit(s) was set but snoop missed (silent data drop in core), data 
returned from LLC.
SNOOP_HIT_NO_FWD 34 A snoop was sent but no data forward.
• LLC hit and CV bit(s) was set but no data forward from  the core, da ta returned 
from LLC.
SNOOP_HIT_WITH_FWD 35 A snoo p was sent and non-modified data was forward.
• LLC hit and CV bit(s) was set, non- modified data was forward from core.
SNOOP_HITM 36 A snoop wa s sent and modified data was forward.
• LLC hit E or M and the CV bit(s) was se t, modified data wa s forward from core.
NON_DRAM_BIT 37 Target was non-DRAM  system address, MMIO access.
• LLC miss and Non-Dram data returned.Table 20-74.  MSR_OFFCORE_RSPx Re quest Type Definition  (Contd.)
Bit Name Offset Description20-96 Vol. 3BPERFORMANCE MONITORING
The Off-core Response capability behaves as follows:
•To specify a complete offcore response filter, software must properly program at least one RequestType and one 
ResponseType. A valid request type must have at least on e bit set in the non-reserved bits of 15:0 or 49:44. A 
valid response type must be a non-zero value of one the following expressions:
•Read requests: 
Any_Response Bit | (‘OR’ of Supplier Info Bits) ‘A ND’ ( ‘OR’ of Snoop Info Bits) | Outstanding Bit
•Write requests: 
Any_Response Bit | (‘OR’ of Supplier Info Bits) | Outstanding Bit
•When the ANY_RESPONSE bit in the ResponseType is se t, all other response type bits will be ignored.
•True Demand Cacheable Loads include neithe r L1 Prefetches nor Software Prefetches.
•Bits 15:0 and Bits 49:44 specifies the request type of a transaction request to the uncore. This is described in 
Table 20-74.
•Bits 30:16 specifies common supplier information.
•“Outstanding Requests” (bit 63) is only available on MSR_OFFCORE_RSP0; a #GP fault will occur if software 
attempts to write a 1 to this bit in MSR_OFFCORE_RS P1. It is mutually exclusive with any ResponseType. 
Software must guarantee that all other ResponseType bits  are set to 0 when the “Outstanding Requests” bit is 
set.
•“Outstanding Requests” bit 63 can enable measurement of the average latency of a specific type of off-core 
transaction; two programmable counters must be used simultaneously and the RequestType programming for MSR_OFFCORE_RSP0 and MSR_OFFCORE_RSP1 must be th e same when using this Average Latency feature. 
See Section 20.5.2.3 for further details.
20.6 PERFORMANCE MONITORING  (LEGACY INTEL PROCESSORS)
20.6.1 Performance Monitoring (Intel® Cor e™ Solo and Intel® Core™ Duo Processors)
In Intel Core Solo and Intel Core Duo processors, non-architectural performance monitoring events are 
programmed using the same facilities (see Figure 20-1) used for architectural performance events.
Non-architectural performance events use event select valu es that are model-specific. Event mask (Umask) values 
are also specific to event logic units. Some microarchitectural conditions detectable by a Umask value may have specificity related to processor topology (see Section 9.6, “Detecting Hardware Multi-Threading Support and 
Topology,” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). As a result, the unit 
mask field (for example, IA32_PERFEVTSELx[bits 15:8]) ma y contain sub-fields that specify topology information 
of processor cores.
The sub-field layout within the Umask field may support tw o-bit encoding that qualifies the relationship between a 
microarchitectural condition and the originating core. This data is shown in Table 20-77. The two-bit encoding for 
core-specificity is only supported for a subset of Umask values (see: https://perfmon-events.intel.com/ ) and for 
Intel Core Duo processors. Such events are referred to as core-specific events.
Table 20-77.  Core Specificity Encodi ng within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit 15:14 Encoding Description11B All cores10B Reserved01B This core00B ReservedVol. 3B 20-97PERFORMANCE MONITORING
Some microarchitectural conditions allow detection specific ity only at the boundary of physical processors. Some 
bus events belong to this category, providing specificity between the originating physic al processor (a bus agent) 
versus other agents on the bus. Sub-field encodi ng for agent specificity is shown in Table 20-78.
Some microarchitectural conditions are detectable only fr om the originating core. In such cases, unit mask does 
not support core-specificity or agent-specificity encodings. These are referred to as core-only conditions.
Some microarchitectural conditions allow detection specific ity that includes or excludes the action of hardware 
prefetches. A two-bit encoding may be su pported to qualify hardware prefetch actions. Typically, this applies only 
to some L2 or bus events. The sub-field encoding for hardware prefetch qualification is shown in Table 20-79.
Some performance events may (a) support none of the three event-specific qualification encodings (b) may 
support core-specificity and agent specificity simultaneously (c) or may support core-specificity and hardware 
prefetch qualification simultaneously. Agent-specificity and hardware prefetch  qualification are mutually exclusive.
In addition, some L2 events permit qualifications that distinguish cache coherent states. The sub-field definition for 
cache coherency state qualification is shown in Table 20-80. If  no bits in the MESI qualification sub-field are set for 
an event that requires setting MESI qualification bits, the event count will not increment.
20.6.2 Performance Monitoring (Processors Based on Intel® Core™ Microarchitecture)
In addition to architectural performance monitoring, proc essors based on the Intel Core microarchitecture support 
non-architectural performance monitoring events.
Architectural performance events can be collected using general-purpose performance counters. Non-architectural 
performance events can be collected using general-purp ose performance counters (coupled with two IA32_PERFE-
VTSELx MSRs for detailed event configur ations), or fixed-function performance counters (see Section 20.6.2.1). 
IA32_PERFEVTSELx MSRs are architectural; their layout is shown in Figure 20-1. St arting with Intel Core 2 Table 20-78.  Agent Specificity Encodi ng within a Non-Architectural Umask
Bit 13 Encoding Description0T h i s  a g e n t1 Include all agents
Table 20-79.  HW Prefetch Qualification Encoding within a Non-Architectural Umask
Bit 13:12 Encoding Description11B All inclusive10B Reserved01B Hardware prefetch only 00B Exclude hardware prefetch
Table 20-80.  MESI Qualification Defini tions within a Non-Architectural Umask
Bit Position 11:8 DescriptionBit 11 Counts modified stateBit 10 Counts exclusive stateBit 9 Counts shared stateBit 8 Counts Invalid state20-98 Vol. 3BPERFORMANCE MONITORING
processor T 7700, fixed-function performance counters an d associated counter control and status MSR becomes 
part of architectural performance monitoring ve rsion 2 facilities (see also Section 20.2.2). 
Non-architectural performance events in  processors based on Intel Core microarchitecture use event select values 
that are model-specific. Valid event mask (Umask) bits can be found at: https://perfmon-events.intel.com/ . The 
UMASK field may contain sub-fields identical to those listed in Table 20-77, Table 20-78, Table 20-79, and 
Table 20-80. One or more of these sub-fields may appl y to specific events on an event-by-event basis. 
In addition, the UMASK filed may also contain a sub-fiel d that allows detection specificity related to snoop

In addition, the UMASK filed may also contain a sub-fiel d that allows detection specificity related to snoop 
responses. Bits of the snoop response qua lification sub-field are defined in Table 20-81.
There are also non-architectural events that support qualification of differen t types of snoop operation. The corre-
sponding bit field for snoop type qualification are listed in Table 20-82.
No more than one sub-field of MESI, snoop response, and sn oop type qualification sub-fi elds can be supported in a 
performance event.
NOTE
Software must write known values to the performance counters prior to enabling the counters. The content of general-purpose counters and fixed-functi on counters are undefined after INIT or RESET.
20.6.2.1  Fixed-function Performance Counters
Processors based on Intel Core microarchitecture provide three fixed-function performance counters. Bits beyond 
the width of the fixed counter are reserved and must be wr itten as zeros. Model-specific fixed-function performance 
counters on processors that support Architectural Perfmon version 1 are 40 bits wide.
Each of the fixed-function counter is dedicated to count a pre-defined performance monitoring events. See Table 
20-2 for details of the PMC addresses and what these events count.
Programming the fixed-function performance counters does  not involve any of the IA32_PERFEVTSELx MSRs, and 
does not require specifying any event masks. Instead, the MSR IA32_FIXED_CTR_CTRL provides multiple sets of 
4-bit fields; each 4-bit field controls the operation of a fixed-function performance counter (PMC). See Figures 
20-43. Two sub-fields are defined for each control. See Figure 20-43; bit fields are:
•Enable field (low 2 bits in each 4-bit control) — When bit 0 is set, performance counting is enabled in the 
corresponding fixed-function performance counter to increment when the target condition associated with the architecture performance event occurs at ring 0. Table 20-81.  Bus Snoop Qualification Defi nitions within a Non-Architectural Umask
Bit Position 11:8 DescriptionBit 11 HITM responseBit 10 Reserved Bit 9 HIT responseBit 8 CLEAN response
Table 20-82.  Snoop Type Qualification Defi nitions within a Non-Architectural Umask
Bit Position 9:8 DescriptionBit 9 CMP2I snoopsBit 8 CMP2S snoopsVol. 3B 20-99PERFORMANCE MONITORING
When bit 1 is set, performance counting is enabled in the corresponding fixed-function performance counter to 
increment when the target condition associated with the architecture performance event occurs at ring greater 
than 0. 
Writing 0 to both bits stops the performance counter. Wr iting 11B causes the counter to increment irrespective 
of privilege levels.
•PMI field (fourth bit in each 4-bit control)  — When set, the logical processor generates an exception 
through its local APIC on overflow condition of the respective fixed-function counter.
20.6.2.2  Global Counter Control Facilities
Processors based on Intel Core microarchitecture provides simplified performance counter control that simplifies 
the most frequent operations in programming performa nce events, i.e., enabling/disabling event counting and 
checking the status of counter overflows. This is done by the following three MSRs:
•MSR_PERF_GLOBAL_CTRL enables/disables event counting for all or any combination of fixed-function PMCs 
(IA32_FIXED_CTRx) or general-purpose PMCs via a single WRMSR.
•MSR_PERF_GLOBAL_STATUS allows software to query co unter overflow conditions on any combination of 
fixed-function PMCs (IA32_FIXED_CTRx) or general-purpose PMCs via a single RDMSR.
•MSR_PERF_GLOBAL_OVF_CTRL allows software to clear counter overflow conditions on any combination of 
fixed-function PMCs (IA32_FIXED_CTRx) or general-purpose PMCs via a single WRMSR.
MSR_PERF_GLOBAL_CTRL MSR provides single-bit controls to enable counting in each performance counter (see 
Figure 20-44). Each enable bit in MSR_PERF_GLOBAL_CTRL is AND’ed with the enable bits for all privilege levels in 
the respective IA32_PERFEVTSELx or IA32_FIXED_CTR_CTRL  MSRs to start/stop the counting of respective 
counters. Counting is enabled if the AND’ed results is true; counting is disabled when the result is false.Figure 20-43.  Layout of IA32_FIXED_CTR_CTRL MSRSDM3026563 012345 789 1112
E
NP
M
IENPM
IE
NPM
I
Cntr2 — Controls for IA32_FIXED_CTR2
Cntr0 — Controls for IA32_FIXED_CTR0ENABLE — 0: disable; 1: OS; 2: User; 3: All ring levels
Reserved20-100 Vol. 3BPERFORMANCE MONITORING
MSR_PERF_GLOBAL_STATUS MSR provides single-bit status used by software to query the overflow condition of 
each performance counter. MSR_PERF_GLOBAL_STATUS[bit 62]  indicates overflow conditions of the DS area data 
buffer. MSR_PERF_GLOBAL_STATUS[bit 63] provides a Cond Chgd bit to indicate changes to the state of perfor-
mance monitoring hardware (see Figure 20-45). A value of 1 in bits 34:32, 1, 0 indicates an overflow condition has 
perform bounds checks based on the parameters define d in the DS Save Area (see Section 18.4.9). Upon 
successful bounds checks, the processor will store the data record in the defined buffer area, clear the counter 
overflow status, and reload the counter. If the bounds chec ks fail, the PEBS will be skipped entirely. In the event 
that the PEBS buffer fills up, the processor will  set the OvfBuffer bit in  MSR_PERF_GLOBAL_STATUS.
MSR_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow the indicators for general-purpose or fixed-
function counters via a single WRMSR (see Figure 20-46). Clear overflow indications when:
•Disabling event counting or interrupt-based event sampling.Figure 20-44.  Layout of MSR_PERF_GLOBAL_CTRL MSR
Figure 20-45.  Layout of MSR_PERF_GLOBAL_STATUS MSRFIXED_CTR2 enable
PMC1 enable210
PMC0 enable3132333435
62
FIXED_CTR2 Overflow
FIXED_CTR1 Overflow
FIXED_CTR0 Overflow
PMC1 Overflow210
PMC0 Overflow3132333435
CondChgd
OvfBufferVol. 3B 20-101PERFORMANCE MONITORING
20.6.2.3  At-Retirement Events
Many non-architectural performance events are impacted by the speculative nature of out-of-order execution. A 
subset of non-architectural performance events on proce ssors based on Intel Core microarchitecture are enhanced 
with a tagging mechanism (similar to that found in Intel NetBurst® microarchitecture) that exclude contributions 
that arise from speculative execution. The at-retiremen t events available in processors based on Intel Core 
microarchitecture does not require special MSR progra mming control (see Section 20.6.3.6, “At-Retirement 
Counting”), but is limited to IA32_PMC0. See Table 20-83 fo r a list of events available to processors based on Intel 
Core microarchitecture.
20.6.2.4  Processor Even t Based Sampling (PEBS)
Processors based on Intel Core microarchitecture also  support processor event based sampling (PEBS). This 
feature was introduced by processors based on Intel NetBurst microarchitecture.
PEBS uses a debug store mechanism and a performance moni toring interrupt to store a set of architectural state 
information for the processor. The information provides ar chitectural state of the instruction executed after the 
instruction that caused the event (See Section 20.6.2.4.2 and Section 18.4.9). 
In cases where the same instruction causes BTS and PEBS to be activated, PEBS is processed before BTS are 
processed. The PMI request is held until the processor completes processing of PEBS and BTS.
For processors based on Intel Core microarchitecture, pr ecise events that can be used with PEBS are listed in 
Table 20-84. The procedure for detecting availability of PEBS is the same as described in Section 20.6.3.8.1.Figure 20-46.  Layout of MSR_PERF_GLOBAL_OVF_CTRL MSR
Table 20-83.  At-Retirement Performance Events for Intel Core Microarchitecture
Event Name UMask Event Select
ITLB_MISS_RETIRED 00H C9H
MEM_LOAD_RETIRED.L1D_MISS 01H CBH
MEM_LOAD_RETIRED.L1D_LINE_MISS 02H CBHMEM_LOAD_RETIRED.L2_MISS 04H CBH
MEM_LOAD_RETIRED.L2_LINE_MISS 08H CBH
MEM_LOAD_RETIRED.DTLB_MISS 10H CBH62
PMC1 ClrOverflow210
PMC0 ClrOverflow3132333435
ClrOvfBuffer20-102 Vol. 3BPERFORMANCE MONITORING
20.6.2.4.1  Setting up the PEBS Buffer
For processors based on Intel Core microarchitecture, PEBS is available using IA32_PMC0 only. Use the following 
procedure to set up the processor and IA32_PMC0 counter for PEBS: 
1. Set up the precise event buffering fac ilities. Place values in the precise ev ent buffer base, precise event index,

1. Set up the precise event buffering fac ilities. Place values in the precise ev ent buffer base, precise event index, 
precise event absolute maximum, precise event interrupt threshold, and precise event counter reset fields of 
the DS buffer management area. In processors based on Intel Core microarchitecture, PEBS records consist of 
64-bit address entries. See Figure 18-8 to set up the precise event records buffer in memory.
2. Enable PEBS. Set the Enable PEBS on PMC0 flag (bit 0) in IA32_PEBS_ENABLE MSR.
3. Set up the IA32_PMC0 performance counter and IA 32_PERFEVTSEL0 for an event listed in Table 20-84.
20.6.2.4.2  PEBS Record Format
The PEBS record format may be extended across diff erent processor implementati ons. The IA32_PERF_CAPABI-
LITES MSR defines a mechanism for software to handle the evolution of PEBS record format in processors that 
support architectural performance monitoring with version ID equals 2 or higher. The bit fields of IA32_PERF_CA-
PABILITES are defined in Table 2-2 of Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 4.  The relevant bit fields that governs PEBS are:
•PEBSTrap [bit 6]: When set, PEBS re cording is trap-like. After the PEBS-enabled counter has overflowed, PEBS 
record is recorded for the next PEBS-able event at the completion of the sampled instruction causing the PEBS 
event. When clear, PEBS recording is fault-like. The PE BS record is recorded befo re the sampled instruction 
causing the PEBS event.
•PEBSSaveArchRegs [bit 7]: When set, PEBS will save ar chitectural register and state information according to 
the encoded value of the PEBSRecordFormat field. When cl ear, only the return instruction pointer and flags are 
recorded. On processors based on Intel Core microarchitecture, this bit is always 1.
•PEBSRecordFormat [bits 11:8]: Valid encodings are:
— 0000B: Only general-purpose registers, instruction po inter and RFLAGS registers are saved in each PEBS 
record (See Section 20.6.3.8). 
— 0001B: PEBS record includes additional informatio n of IA32_PERF_GLOBAL_STATUS and load latency data. 
(See Section 20.3.1.1.1). 
— 0010B: PEBS record includes additional informatio n of IA32_PERF_GLOBAL_STATUS, load latency data, 
and TSX tuning information.  (See Section 20.3.6.2). 
— 0011B: PEBS record includes additional information of  load latency data, TSX tuning information, TSC data, 
and the applicable counter field replaces IA32_P ERF_GLOBAL_STATUS at offset 90H. (See Section 
20.3.8.1.1). 
— 0100B: PEBS record contents are defined by electi ons in MSR_PEBS_DATA_CFG. (See Section 20.9.2.3). 
The PEBS Configuration Buffer is defined as shown in Figure 20-64 with Counter Reset fields allocation for 
8 general-purpose counters followed by 4 fixed-function counters.Table 20-84.  PEBS Performance Even ts for Intel Core Microarchitecture
INSTR_RETIRED.ANY_P 00H C0HX87_OPS_RETIRED.ANY FEH C1HBR_INST_RETIRED.MISPRED 00H C5HSIMD_INST_RETIRED.ANY 1FH C7HMEM_LOAD_RETIRED.L1D_MISS 01H CBHMEM_LOAD_RETIRED.L1D_LINE_MISS 02H CBHMEM_LOAD_RETIRED.L2_MISS 04H CBHMEM_LOAD_RETIRED.L2_LINE_MISS 08H CBHMEM_LOAD_RETIRED.DTLB_MISS 10H CBHVol. 3B 20-103PERFORMANCE MONITORING
— 0101B: PEBS record contents are defined by electi ons in MSR_PEBS_DATA_CFG. (See Section 20.9.2.3). 
32 general-purpose counters followed by 16 fixed-function counters.
20.6.2.4.3  Writing a PEBS  Interrupt Service Routine
The PEBS facilities share the same interrupt vector and inte rrupt service routine (called the DS ISR) with the Inter-
rupt-based event sampling and BTS facilities. To handle PE BS interrupts, PEBS handler code must be included in 
the DS ISR. See Section 18.4.9.1, “64 Bit Format of the DS Save Area,” for guidelines when writing the DS ISR.
The service routine can query MSR_PERF_GLOBAL_STATUS to determine which counter(s) caused of overflow 
condition. The service routine should clear overflow  indicator by writing to MSR_PERF_GLOBAL_OVF_CTL. 
A comparison of the sequence of requ irements to program PEBS for processors based on Intel Core and Intel 
NetBurst microarchitectures is listed in Table 20-85.
Table 20-85.  Requirements to Program PEBS
For Processors based on Intel Core microarchitectureFor Processors based on Intel NetBurst 
microarchitecture
Verify PEBS support of 
processor/OS. • IA32_MISC_ENABLE.EMON_AVAILABE (bit 7) is set.
• IA32_MISC_ENABLE.PEBS_UNAVA ILABE (bit 12) is clear.
Ensure counters are in disabled. On initial set up or changing event configurations, 
write MSR_PERF_GLOBAL_CTRL MSR (38FH) with 0. 
On subsequent entries:• Clear all counters if “Counter Freeze on PMI“ is not 
enabled.
• If IA32_DebugCTL.Freeze is enabled, counters are 
automatically disabled.
Counters MUST be stopped before writing.
1
NOTES:
1. Counters read while enabled are not guaranteed to be precise with event counts that occur in  timing proximity to the RDMSR.Optional
Disable PEBS. Clear ENABLE PMC0 bit in IA32_PEBS_ENABLE MSR 
(3F1H).Optional
Check overflow conditions. Check MSR_PERF_GLOBAL_STATUS MSR (38EH) 
handle any overflow conditions.Check OVF flag of each CCCR for overflow 
condition
Clear overflow status. Clear MSR_ PERF_GLOBAL_STAT US MSR (38EH) 
using IA32_PERF_GLOBAL_OVF_CTRL MSR (390H).Clear OVF flag of each CCCR.
Write “sample-after“ values. Configure the counter(s) with the sample after value.
Configure specific counter 
configuration MSR.• Set local enable bit 22 - 1.
• Do NOT set local counter PMI/INT bit, bit 20 - 0.
• Event programmed must be PEBS capable. • Set appropriate OVF_PMI bits - 1.
• Only CCCR for MSR_IQ_COUNTER4 
support PEBS.
Allocate buffer for PEBS states. Allocate a buffer in memory for the precise information.
Program the IA32_DS_ AREA MSR. Program the IA32_DS_AREA MSR.
Configure the PEBS buffer 
management records.Configure the PEBS buffer management records in the DS buffer management area.
Configure/Enable PEBS. Set Enable PMC0 bit in IA32_PEBS_ENABLE MSR 
(3F1H).Configure MSR_PEBS_ENABLE, 
MSR_PEBS_MATRIX_VERT, and MSR_PEBS_MATRIX_HORZ as needed.
Enable counters. Set Enable bits  in MSR_PERF_GLOBAL_CTRL MSR 
(38FH).Set each CCCR enable bit 12 - 1.20-104 Vol. 3BPERFORMANCE MONITORING
20.6.2.4.4  Re-configuring PEBS Facilities
When software needs to reconfigure PEBS facilities, it sh ould allow a quiescent period between stopping the prior 
event counting and setting up a new PEBS event. The quiescent  period is to allow any latent residual PEBS records 
to complete its capture at their previously spec ified buffer address (provided by IA32_DS_AREA).
20.6.3 Performance Monitoring (Processors Ba sed on Intel NetBurst® Microarchitecture)
The performance monitoring mechanism provided in processors based on Intel NetBurst microarchitecture is 
different from that provided in the P6 family and Pent ium processors. While the general concept of selecting, 
filtering, counting, and reading performance events th rough the WRMSR, RDMSR, and RDPMC instructions is 
unchanged, the setup mechanism and MSR layouts are inco mpatible with the P6 family and Pentium processor 
mechanisms. Also, the RDPMC instruction has been extended to support faster reading of counters and to read all 
performance counters available in processors based on Intel NetBurst microarchitecture.
The event monitoring mechanism consists of the following facilities:
•The IA32_MISC_ENABLE MSR, which indicates the availa bility in an Intel 64 or IA-32 processor of the 
performance monitoring and processor event-based sampling (PEBS) facilities.
•Event selection control (ESCR) MSRs for selecting events  to be monitored with specific performance counters. 
The number available differs by family and model (43 to 45).
•18 performance counter MSRs for counting events.
•18 counter configuration control (CCCR) MSRs, with one CCCR associated with each performance counter. CCCRs sets up an associated performance co unter for a specific method of counting.
•A debug store (DS) save area in memory for storing PEBS records.
•The IA32_DS_AREA MSR, which establishes the location of the DS save area.
•The debug store (DS) feature flag (bit 21) returned by th e CPUID instruction, which indicates the availability of 
the DS mechanism.
•The MSR_PEBS_ENABLE MSR, which enable s the PEBS facilities and replay tagging used in at-retirement event 
counting.
•A set of predefined events and event metrics that simpli fy the setting up of the performance counters to count 
specific events.
Table 20-86 lists the performance counters and their associat ed CCCRs, along with the ESCRs that select events to 
be counted for each performance counter. Predef ined event metrics and events can be found at: https://perfmon-
events.intel.com/.
Table 20-86.  Performance Counter MSRs and Associated CCCR and ESCR MSRs 
(Processors Based on Intel NetBurst Microarchitecture)
Counter CCCR ESCR
Name No. Addr Name Addr Name No. Addr
MSR_BPU_COUNTER0 0 300H MSR_B PU_CCCR0 360H MSR_BSU_ESCR0
MSR_FSB_ESCR0MSR_MOB_ESCR0MSR_PMH_ESCR0MSR_BPU_ESCR0MSR_IS_ESCR0MSR_ITLB_ESCR0MSR_IX_ESCR07
62401353A0H

counting.
3A2H3AAH3ACH3B2H3B4H3B6H3C8HVol. 3B 20-105PERFORMANCE MONITORING
MSR_BPU_COUNTER1 1 301H MSR_BPU_CCCR1 361H MSR_BSU_ESCR0
3A2H3AAH3ACH3B2H3B4H3B6H3C8H
MSR_BPU_COUNTER2 2 302H MSR_BPU_CCCR2 362H MSR_BSU_ESCR1
MSR_FSB_ESCR1MSR_MOB_ESCR1MSR_PMH_ESCR1MSR_BPU_ESCR1
MSR_IS_ESCR1
MSR_ITLB_ESCR1MSR_IX_ESCR17
6240
1
353A1H
3A3H3ABH3ADH3B3H
3B5H
3B7H3C9H
MSR_BPU_COUNTER3 3 303H MSR_BPU_CCCR3 363H MSR_BSU_ESCR1
MSR_FSB_ESCR1MSR_MOB_ESCR1MSR_PMH_ESCR1MSR_BPU_ESCR1MSR_IS_ESCR1MSR_ITLB_ESCR1MSR_IX_ESCR17
62401353A1H
3A3H3ABH3ADH3B3H3B5H3B7H3C9H
MSR_MS_COUNTER0 4 304H MSR_MS_CCCR0 364H MSR_MS_ESCR0
MSR_TBPU_ESCR0MSR_TC_ESCR00
213C0H
3C2H3C4H
MSR_MS_COUNTER1 5 305H MSR_MS_CCCR1 365H MSR_MS_ESCR0
213C0H
3C2H3C4H
MSR_MS_COUNTER2 6 306H MSR_MS_CCCR2 366H MSR_MS_ESCR1
MSR_TBPU_ESCR1MSR_TC_ESCR10
213C1H
3C3H3C5H
MSR_MS_COUNTER3 7 307H MSR_MS_CCCR3 367H MSR_MS_ESCR1
213C1H
3C3H3C5H
MSR_FLAME_COUNTER0 8 308H MSR_FLAME_CCCR0 368H MSR_FIRM_ESCR0
MSR_FLAME_ESCR0MSR_DAC_ESCR0MSR_SAAT_ESCR0MSR_U2L_ESCR01
05233A4H
3A6H3A8H3AEH3B0H
MSR_FLAME_COUNTER1 9 309H MSR_FLAME_CCCR1 369H MSR_FIRM_ESCR0
05233A4H
MSR_FLAME_COUNTER2 10 30AH MSR_FLAME_CCCR2 36AH MSR_FIRM_ESCR1
MSR_FLAME_ESCR1MSR_DAC_ESCR1MSR_SAAT_ESCR1MSR_U2L_ESCR11
05233A5H
3A7H3A9H3AFH3B1H
MSR_FLAME_COUNTER3 11 30BH MSR_FLAME_CCCR3 36BH MSR_FIRM_ESCR1
05233A5H
(Processors Based on Intel NetBur st Microarchitecture) (Contd.)
Name No. Addr Name Addr Name No. Addr20-106 Vol. 3BPERFORMANCE MONITORING
The types of events that can be counted with these perfor mance monitoring facilities are divided into two classes: 
non-retirement events and at-retirement events.
•Non-retirement events are events that occur any time during instruction execution (such as bus transactions or cache transactions).
•At-retirement events are events that are counted at the retirement stage of instruction execution, which allows 
finer granularity in counting events and capturing machine state. 
The at-retirement counting mechanism includes facilities for tagging μops that have encountered a particular 
performance event during instruction execution. Taggin g allows events to be sorted between those that 
occurred on an execution path that resulted in architectural state being committed at retirement as well as 
events that occurred on an execution path where the re sults were eventually cancelled and never committed to 
architectural state (such as, the execution of a mispredicted branch).MSR_IQ_COUNTER0 12 30CH MSR_IQ_CCCR0 36CH MSR_CRU_ESCR0
MSR_CRU_ESCR2MSR_CRU_ESCR4MSR_IQ_ESCR0
1
MSR_RAT_ESCR0MSR_SSU_ESCR0MSR_ALF_ESCR04
5602313B8H
3CCH3E0H3BAH3BCH3BEH3CAH
MSR_IQ_COUNTER1 13 30DH MSR_IQ_CCCR1 36DH MSR_CRU_ESCR0
1
MSR_RAT_ESCR0MSR_SSU_ESCR0
MSR_ALF_ESCR04
56023
13B8H
3CCH3E0H3BAH3BCH3BEH
3CAH
MSR_IQ_COUNTER2 14 30EH MSR_IQ_CCCR2 36EH MSR_CRU_ESCR1
MSR_CRU_ESCR3MSR_CRU_ESCR5MSR_IQ_ESCR1
1
MSR_RAT_ESCR1MSR_ALF_ESCR14
560213B9H
3CDH3E1H3BBH3BDH3CBH
MSR_IQ_COUNTER3 15 30FH MSR_IQ_CCCR3 36FH MSR_CRU_ESCR1
1
56
 0
213B9H
3CDH3E1H
3BBH
3BDH3CBH
MSR_IQ_COUNTER4 16 310H MSR_IQ_CCCR4 370H MSR_CRU_ESCR0
1
MSR_IQ_COUNTER5 17 311H MSR_IQ_CCCR5 371H MSR_CRU_ESCR1
1
560213B9H
NOTES:
1. MSR_IQ_ESCR0 and MSR_IQ_ESCR1 are available only on early processor builds (family 0FH, models 01H-02H). These MSRs are not 
available on later versions.Table 20-86.  Performance Counter MSRs and Associated CCCR and ESCR MSRs 
Name No. Addr Name Addr Name No. AddrVol. 3B 20-107PERFORMANCE MONITORING
The Pentium 4 and Intel Xeon processor performance mo nitoring facilities support the three usage models 
described below. The first two models can be used to count both non-retirement and at-retirement events; the 
third model is used to count a subset of at-retirement events:
•Event counting — A performance counter is configured to count one or more types of events. While the 
counter is counting, software reads the counter at sele cted intervals to determine the number of events that 
have been counted between the intervals.
•Interrupt-based event sampling — A performance counter is configured to count one or more types of 
events and to generate an interrupt when it overflows.  To trigger an overflow, the counter is preset to a 
modulus value that will cause the counter to overflow after a specific number of events have been counted. 
When the counter overflows, the processor generates a performance monitoring interrupt (PMI). The interrupt 
service routine for the PMI then records the return instru ction pointer (RIP), resets the modulus, and restarts 
the counter. Code performance can be analyzed by exam ining the distribution of RIPs with a tool like the 
VTune™ Performance Analyzer.
•Processor event-based sampling (PEBS) — In PEBS, the processor writes a record of the architectural 
state of the processor to a memory buffer after the co unter overflows. The records of architectural state 
provide additional information for us e in performance tuning. Processor-based event sampling can be used to 
count only a subset of at-retirement events. PEBS captures more precise processor state information compared 
to interrupt based event sampling, because the latter need  to use the interrupt service routine to re-construct 
the architectural states of processor. 
The following sections describe the MSRs and data struct ures used for performance monitoring in the Pentium 4 
and Intel Xeon processors.
20.6.3.1  ESCR MSRs
The 45 ESCR MSRs (see Table 20-86) allow software to select specific events to be countered. Each ESCR is usually 
associated with a pair of performance counters (see Ta ble 20-86) and each performance counter has several ESCRs 
associated with it (allowing the events counte d to be selected from a variety of events).
Figure 20-47 shows the layout of an ESCR MSR.  The functions of the flags and fields are:
•USR flag, bit 2 — When set, events are counted when the processor is operating at a current privilege level 
(CPL) of 1, 2, or 3. These privilege levels are genera lly used by application code and unprotected operating 
system code.
•OS flag, bit 3 — When set, events are counted when the processor is operating at CPL of 0. This privilege level 
is generally reserved for protected operating system co de. (When both the OS and USR flags are set, events 
are counted at all privilege levels.)
•Tag enable, bit 4 — When set, enables tagging of μops to assist in at-retirement event counting; when clear, 
disables tagging. See Section 20.6.3.6, “At-Retirement Counting.”Figure 20-47.  Event Selection Cont rol Register (ESC R) for Pentium 4 
and Intel® Xeon® Processors with out Intel HT Technology Support31 24 8 0 1234 9 25 30
63 32
ReservedEvent MaskEvent
Select
USROS5
Tag EnableTag 
Value
Reserved20-108 Vol. 3BPERFORMANCE MONITORING
•Tag value field, bits 5 through 8 — Selects a tag value to associate with a μop to assist in at-retirement 
event counting.
•Event mask field, bits 9 through 24 — Selects events to be counted from the event class selected with the 
event select field.
•Event select field, bits 25 through 30) — Selects a class of events to be counted. The events within this 
class that are counted are selected with the event mask field.
When setting up an ESCR, the event select field is used to se lect a specific class of events to count, such as retired 
branches. The event mask field is then used to select one or more of the specific events within the class to be 
counted. For example, when counting retired branches, four different events can be counted: branch not taken predicted, branch not taken mispredicted, branch taken predicted, and branch taken mispredicted. The OS and 
USR flags allow counts to be enabled for events that occur when operating system code and/or application code are 
being executed. If neither the OS nor USR flag is set, no events will be counted.
The ESCRs are initialized to all 0s on reset. The flags and fields of an ESCR are configured by writing to the ESCR 
using the WRMSR instruction. Table 20-86 gives the addresses of the ESCR MSRs. 
Writing to an ESCR MSR does not enable counting with its associated performance counter; it only selects the event

Writing to an ESCR MSR does not enable counting with its associated performance counter; it only selects the event 
or events to be counted. The CCCR for the selected perfor mance counter must also be configured. Configuration of 
the CCCR includes selecting the ESCR and enabling the counter.
20.6.3.2  Performance Counters
The performance counters in conjunction with the counter configuration control registers (CCCRs) are used for 
filtering and counting the events selected by the ESCRs.  Processors based on Intel NetBurst microarchitecture 
provide 18 performance counters organized into 9 pairs. A pair of performance counters is associated with a partic-
ular subset of events and ESCR’s (see Table 20-86). The counter pairs are partitioned into four groups:
•The BPU group, includes two performance counter pairs:
— MSR_BPU_COUNTER0 and MSR_BPU_COUNTER1.
— MSR_BPU_COUNTER2 and MSR_BPU_COUNTER3.
•The MS group, includes two performance counter pairs:
— MSR_MS_COUNTER0 and MSR_MS_COUNTER1.— MSR_MS_COUNTER2 and MSR_MS_COUNTER3.
•The FLAME group, includes two performance counter pairs:
— MSR_FLAME_COUNTER0 and MSR_FLAME_COUNTER1.
— MSR_FLAME_COUNTER2 and MSR_FLAME_COUNTER3.
•The IQ group, includes three performance counter pairs:— MSR_IQ_COUNTER0 and MSR_IQ_COUNTER1.
— MSR_IQ_COUNTER2 and MSR_IQ_COUNTER3.
— MSR_IQ_COUNTER4 and MSR_IQ_COUNTER5.
The MSR_IQ_COUNTER4 counter in the IQ group provides support for the PEBS. 
Alternate counters in each group can be cascaded: the first counter in one pair can start the first counter in the 
second pair and vice versa. A similar cascading is possible for the second counters in each pair. For example, within 
the BPU group of counters, MSR_BP U_COUNTER0 can start MSR_BPU_COUN TER2 and vice versa, and MSR_B-
PU_COUNTER1 can start MSR_BPU_COUNTER3 and vice ve rsa (see Section 20.6.3.5.6, “Cascading Counters”). 
The cascade flag in the CCCR register for the pe rformance counter enables the cascading of counters.
Each performance counter is 40-bits wide (see Figure 20-48). The RDPMC instruction is intended to allow reading 
of either the full counter-width (40-bits) or, if ECX[31] is  set to 1, the low 32-bits of the counter. Reading the low 
32-bits is faster than reading the full counter width and is appropriate in situations where the count is small enough 
to be contained in 32 bits. In such cases, counter bi ts 31:0 are written to EAX, while 0 is written to EDX.Vol. 3B 20-109PERFORMANCE MONITORING
The RDPMC instruction can be used by programs or proced ures running at any privilege level and in virtual-8086 
mode to read these counters. The PCE flag in control regist er CR4 (bit 8) allows the use of this instruction to be 
restricted to only programs and procedures running at privilege level 0.
The RDPMC instruction is not serializing or ordered with other instructions. Thus, it does not necessarily wait until 
all previous instructions have been executed before re ading the counter. Similarly, subsequent instructions may 
begin execution before the RDPMC instruction operation is performed.
Only the operating system, executing at privilege level 0,  can directly manipulate the performance counters, using 
the RDMSR and WRMSR instructions. A secure operating syst em would clear the PCE flag during system initializa-
tion to disable direct user access to the performance-monitoring counters, but provide a user-accessible program-
ming interface that emulates the RDPMC instruction.
Some uses of the performance counters require the counter s to be preset before counting begins (that is, before 
the counter is enabled). This can be accomplished by writ ing to the counter using the WRMSR instruction. To set a 
counter to a specified number of counts before overflow, enter a 2s complement negative integer in the counter. 
The counter will then count from the pr eset value up to -1 and overflow. Writing to a performance counter in a 
Pentium 4 or Intel Xeon processor with the WRMSR instruct ion causes all 40 bits of the counter to be written.
20.6.3.3  CCCR MSRs
Each of the 18 performance counters has one CCCR MSR associated with it (see Table 20-86). The CCCRs control 
the filtering and counting of events as well as interrupt generation. Figure 20-49 shows the layout of an CCCR MSR. 
The functions of the flags and fields are as follows:
•Enable flag, bit 12 — When set, enables counting; when clear, the co unter is disabled. This flag is cleared on 
reset.
•ESCR select field, bits 13 through 15 — Identifies the ESCR to be used to select events to be counted with 
the counter associated with the CCCR.
•Compare flag, bit 18 — When set, enables filtering of the event co unt; when clear, disables filtering. The 
filtering method is selected with the threshold, complement, and edge flags.
•Complement flag, bit 19 — Selects how the incoming event count is compared with the threshold value. 
When set, event counts that are less than or equal to  the threshold value result in a single count being 
delivered to the performance counter; when clear, counts greater than the threshold value result in a count 
being delivered to the performance counter (see Section 20.6.3.5.2, “Filtering Events”). The complement flag is not active unless the compare flag is set.
•Threshold field, bits 20 through 23 — Selects the threshold value to be used for comparisons. The 
processor examines this field only when the compare fl ag is set, and uses the complement flag setting to 
determine the type of threshold comparis on to be made. The useful range of values that can be entered in this 
field depend on the type of event being counted  (see Section 20.6.3.5.2, “Filtering Events”).
•Edge flag, bit 24 — When set, enables rising edge (false-to-true) edge detection of the threshold comparison 
output for filtering event counts; when clear, rising edge detection is disabled. This fl ag is active only when the 
compare flag is set.Figure 20-48.  Performance Counter (P entium 4 and Intel® Xeon® Processors)63 32
Reserved31 0
Counter
39
Counter20-110 Vol. 3BPERFORMANCE MONITORING
•FORCE_OVF flag, bit 25 — When set, forces a counter overflow on every counter increment; when clear, 
overflow only occurs when the counter actually overflows.
•OVF_PMI flag, bit 26 — When set, causes a performance monitor interrupt (PMI) to be generated when the 
counter overflows occurs; when clear, disables PMI generation. Note that the PMI is generated on the next 
event count after the counter has overflowed.
•Cascade flag, bit 30 — When set, enables counting on one counter of a counter pair when its alternate 
counter in the other the counter pair in the same count er group overflows (see Section 20.6.3.2, “Performance 
Counters,” for further details); when clear, disables cascading of counters.
•OVF flag, bit 31 — Indicates that the counter has overflowed when set. This flag is a sticky flag that must be 
explicitly cleared by software.
The CCCRs are initialized to all 0s on reset. 
The events that an enabled performance counter actually counts are selected an d filtered by the following flags and 
fields in the ESCR and CCCR registers and in the qualification order given:
1. The event select and event mask fields in the ESCR select  a class of events to be counted and one or more event 
types within the class, respectively.
2. The OS and USR flags in the ESCR selected the privilege levels at which events will be counted.
3. The ESCR select field of the CCCR selects the ESCR. Since each counter has several ESCRs associated with it, 
one ESCR must be chosen to select the classes of events that may be counted.
4. The compare and complement flags and the threshold field of the CCCR select an optional threshold to be used 
in qualifying an event count.
5. The edge flag in the CCCR allows events to  be counted only on rising-edge transitions.
The qualification order in the above list implies that the fi ltered output of one “stage” forms the input for the next. 
For instance, events filtered using the privilege level flags can be further qualified by the compare and complement 
flags and the threshold field, and an event that matched the threshold criteria, can be  further qualified by edge 
detection.
The uses of the flags and fields in the CCCRs are discussed in greater detail in Section 20.6.3.5, “Programming the 
Performance Counters for Non-Retirement Events.”Figure 20-49.  Counter Configuration Control Register (CCCR)63 32
Reserved: Must be set to 11B
CompareEnable31 2423 20 19 16 15 12 11 0 1718 252627 2930
Edge
FORCE_OVF
OVF_PMIThreshold
Cascade
OVFComplementReserved13
ESCR
SelectReservedVol. 3B 20-111PERFORMANCE MONITORING
20.6.3.4  Debug Store (DS) Mechanism
The debug store (DS) mechanism was introduced with processors based on Intel NetBurst microarchitecture to 
allow various types of information to be collected in memory-resident buffers for use in debugging and tuning 
programs. The DS mechanism can be used to collect tw o types of information: branch records and processor

Edge
FORCE_OVF
Cascade
ESCR
programs. The DS mechanism can be used to collect tw o types of information: branch records and processor 
event-based sampling (PEBS) re cords. The availability of the DS mechanism in a processor is indicated with the DS 
feature flag (bit 21) returned by the CPUID instruction. 
See Section 18.4.5, “Branch Trace Store (BTS),” and Sect ion 20.6.3.8, “Processor Event-Based Sampling (PEBS),” 
for a description of these facilities. Records collected wi th the DS mechanism are saved in the DS save area. See 
Section 18.4.9, “BTS and DS Save Area.”
20.6.3.5  Programming the Performanc e Counters for Non-Retirement Events
The basic steps to program a performance counter and to count events include the following:
1. Select the event or events to be counted.
2. For each event, select an ESCR that supports the event.3. Match the CCCR Select value and ESCR name to a value listed in Table 20-86; select a CCCR and performance 
counter.
4. Set up an ESCR for the specific event or events to be counted and the privilege levels at which they are to be 
counted.
5. Set up the CCCR for the performance counter by selecting the ESCR and the desired event filters.
6. Set up the CCCR for optional cascading of event count s, so that when the selected counter overflows its 
alternate counter starts.
7. Set up the CCCR to generate an optional performance monitor interrupt (PMI) when the counter overflows. If 
PMI generation is enabled, the local APIC must be set up  to deliver the interrupt to the processor and a handler 
for the interrupt must be in place.
8. Enable the counter to begin counting.
20.6.3.5.1  Selecting Events to Count
There is a set of at-retirement events for processors base d on Intel NetBurst microarchitecture. For each event, 
setup information is provided. Table 20-87 gives an example of one of the events.
Table 20-87.  Event Example 
Event Name Event Parameters  Parameter Value Description
branch_retired Counts the retirement of a branch . Specify one or more mask bits to select 
any combination of branch taken, not-taken, predicted, and mispredicted. 
ESCR restrictions MSR_CRU_ESCR2
MSR_CRU_ESCR3See Table 15-3 for the addresses of the ESCR MSRs.
Counter numbers per 
ESCRESCR2: 12, 13, 16
ESCR3: 14, 15, 17The counter numbers associated with each ESCR are provided. The 
performance counters and corresponding CCCRs can be obtained from 
Table 15-3.
ESCR Event Select 06H ESCR[31:25]ESCR Event Mask
Bit 0: MMNP     1: MMNM
     2: MMTP
     3: MMTMESCR[24:9]
Branch Not-taken PredictedBranch Not-taken Mispredicted
Branch Taken Predicted
Branch Taken Mispredicted
CCCR Select 05H CCCR[15:13]20-112 Vol. 3BPERFORMANCE MONITORING
Event Parameters are described below.
•ESCR restrictions — Lists the ESCRs that can be used to program the event. Typically only one ESCR is 
needed to count an event. 
•Counter numbers per ESCR — Lists which performance counters are associated with each ESCR. Table 20-86 
gives the name of the counter and CCCR for each counter number. Typically only one counter is needed to count 
the event.
•ESCR event select — Gives the value to be placed in the event se lect field of the ESCR to select the event.
•ESCR event mask — Gives the value to be placed in the Event Mask  field of the ESCR to select sub-events to 
be counted. The parameter value column defines the document ed bits with relative bit position offset starting 
from 0, where the absolute bit position of relative o ffset 0 is bit 9 of the ESCR. All undocumented bits are 
reserved and should be set to 0.
•CCCR select — Gives the value to be placed in the ESCR select field of the CCCR associated with the counter 
to select the ESCR to be used to define the event. This  value is not the address of the ESCR; it is the number of 
the ESCR from the Number column in Table 20-86.
•Event specific notes — Gives additional information about the event, such as the name of the same or a 
similar event defined for the P6 family processors.
•Can support PEBS — Indicates if PEBS is supported for the even t (only supplied for at-retirement events).
•Requires additional MSR for tagging — Indicates which if any additional MSRs must be programmed to 
count the events (only supplied for the at-retirement events).
NOTE
The performance-monitoring events found at https://perfmon-events.intel.com/  are intended to be 
used as guides for performance tuning. The coun ter values reported are not guaranteed to be 
absolutely accurate and should be used as a relative guide for tuning. Known discrepancies are 
documented where applicable.
The following procedure shows how to set up a performance counter for basic counting; that is, the counter is set 
up to count a specified event indefinitely, wrapping aro und whenever it reaches its maximum count. This procedure 
is continued through the following four sections.
An event to be counted can be selected as follows:
1. Select the event to be counted.
2. Select the ESCR to be used to select events to be counted from the ESCRs field.3. Select the number of the counter to be used to co unt the event from the Counter Numbers Per ESCR field.
4. Determine the name of the counter and the CCCR a ssociated with the counter, and determine the MSR 
addresses of the counter, CCCR, and ESCR from Table 20-86.
5. Use the WRMSR instruction to write the ESCR Event Sele ct and ESCR Event Mask values into the appropriate 
fields in the ESCR. At the same time set or cl ear the USR and OS flags in the ESCR as desired.
6. Use the WRMSR instruction to write the CCCR Sele ct value into the appropriate field in the CCCR.Event Specific Notes P6: EMON_BR_INST_RETIRED
Can Support PEBS NoRequires Additional 
MSRs for TaggingNoTable 20-87.  Even t Example  (Contd.)
Event Name Event Parameters  Parameter Value DescriptionVol. 3B 20-113PERFORMANCE MONITORING
NOTE
Typically all the fields and flags of the CCCR will be written with one WRMSR instruction; however, 
in this procedure, several WRMSR writes are used to more clearly demonstrate the uses of the 
various CCCR fields and flags.
This setup procedure is continued in the next section, Section 20.6.3.5.2, “Filtering Events.”
20.6.3.5.2  Filtering Events
Each counter receives up to 4 input lines from the pr ocessor hardware from which it is counting events. The 
counter treats these inputs as binary inputs (input 0 has a value of 1, input 1 has a value of 2, input 3 has a value of 4, and input 3 has a value of 8). When a counter is enab led, it adds this binary input value to the counter value 
on each clock cycle. For each clock cycle, the value adde d to the counter can then range from 0 (no event) to 15. 
For many events, only the 0 input line is active, so the counter is merely counting the clock cycles during which the 
0 input is asserted. However, for some events two or more input lines are used. Here, the counters threshold 
setting can be used to filter events. The compare, comple ment, threshold, and edge fields control the filtering of 
counter increments by input value.
If the compare flag is set, then a “greater than” or a “l ess than or equal to” comparison of the input value vs. a 
threshold value can be made. The complement flag selects “l ess than or equal to” (flag set) or “greater than” (flag 
clear). The threshold field selects a threshold value of from 0 to 15. For example, if the complement flag is cleared and the threshold field is set to 6, than any input value of 7 or greater on the 4 inputs to the counter will cause the 
counter to be incremented by 1, and any value less than 7 will cause an increment of 0 (or no increment) of the 
counter. Conversely, if the complement flag is set, any value from 0 to 6 will increment the counter and any value 
from 7 to 15 will not increment the counter. Note that when  a threshold condition has been satisfied, the input to 
the counter is always 1, not the input value that is presented to the threshold filter. 
The edge flag provides further filtering of the counter in puts when a threshold comparison is being made. The edge 
flag is only active when the compare flag is set. When th e edge flag is set, the resulting output from the threshold 
filter (a value of 0 or 1) is used as an input to the edge filter. Each clock cycle, the edge filter examines the last and 
current input values and sends a count to the counter only when it detects a “rising edge” event; that is, a false-
to-true transition. Figure 20-50 illustrates rising edge filtering.
The following procedure shows how to configure a CCCR to filter events using the threshold filter and the edge 
filter. This procedure is a continuation of the setup proc edure introduced in Section 20.6.3.5.1, “Selecting Events 
to Count.”
7. (Optional) To set up the counter for threshold filtering,  use the WRMSR instruction to write values in the CCCR 
compare and complement flags and the threshold field:
— Set the compare flag.
— Set or clear the complement flag for less than or equal to or greater than comparisons, respectively.
— Enter a value from 0 to 15 in the threshold field.
8. (Optional) Select rising edge filtering by setting the CCCR edge flag.

to Count.”
This setup procedure is continued in the next sect ion, Section 20.6.3.5.3, “Starting Event Counting.”
Figure 20-50.  Effects of Edge FilteringOutput from
Threshold Filter
Counter Increments
On Rising Edge(False-to-True)Processor Clock20-114 Vol. 3BPERFORMANCE MONITORING
20.6.3.5.3  Starti ng Event Counting
Event counting by a performance counter can be initiated in either of two ways. The typical way is to set the enable 
flag in the counter’s CCCR. Following the instruction to set the enable flag, event counting begins and continues 
until it is stopped (see Section 20.6.3.5.5, “Halting Event Counting”). 
The following procedural step shows how to start event counting. This step is a continuation of the setup procedure 
introduced in Section 20.6.3.5.2, “Filtering Events.”
9. To start event counting, use the WRMSR instruction to set the CCCR enable flag for the performance counter.
This setup procedure is continued in the next section,  Section 20.6.3.5.4, “Reading a Performance Counter’s 
Count.”
The second way that a counter can be started by using the cascade feature. Here, the overflow of one counter auto-
matically starts its alternate counter (see Section 20.6.3.5.6, “Cascading Counters”).
20.6.3.5.4  Reading a Performance Counter’s Count
Performance counters can be read using either the RDPM C or RDMSR instructions. The enhanced functions of the 
RDPMC instruction (including fast read ) are described in Section 20.6.3.2, “P erformance Counters.” These instruc-
tions can be used to read a performance counter while it is counting or when it is stopped.
The following procedural step shows how to read the event counter. This step is a continuation of the setup proce-
dure introduced in Section 20.6 .3.5.3, “Starting Event Counting.”
10. To read a performance counters current event count, execute the RDPMC instruction with the counter number 
obtained from Table 20-86 used as an operand.
This setup procedure is continued in the next sect ion, Section 20.6.3.5.5, “Halting Event Counting.”
20.6.3.5.5  Halting Event Counting
After a performance counter has been started (enabled), it  continues counting indefinitely. If the counter overflows 
(goes one count past its maximum count), it wraps around and continues counting. When the counter wraps 
around, it sets its OVF flag to indicate that the counter has overflowed. The OVF flag is a sticky flag that indicates that the counter has overflowed at least once since the OVF bit was last cleared. 
To halt counting, the CCCR enable fl ag for the counter must be cleared.
The following procedural step shows how to stop event coun ting. This step is a continuation of the setup procedure 
introduced in Section 20.6.3.5.4, “Reading a Performance Counter’s Count.”
11. To stop event counting, execute a WRMSR instruction to clear the CCCR enable flag for the performance 
counter.
To halt a cascaded counter (a counter that was started when its alternate counter overflowed), either clear the 
Cascade flag in the cascaded counter’s CCCR MSR or cl ear the OVF flag in the alternate counter’s CCCR MSR.
20.6.3.5.6  Cascading Counters
As described in Section 20.6.3.2, “Performance Counter s,” eighteen performance counters are implemented in 
pairs. Nine pairs of counters and associated CCCRs are fu rther organized as four blocks: BPU, MS, FLAME, and IQ 
(see Table 20-86). The first three blocks contain two pairs each. The IQ block contains three pairs of counters (12 
through 17) with associated CCCRs (MSR_IQ_CCCR0 through MSR_IQ_CCCR5).
The first 8 counter pairs (0 through 15) can be programmed  using ESCRs to detect performance monitoring events. 
Pairs of ESCRs in each of the four blocks allow many differe nt types of events to be counted. The cascade flag in the 
CCCR MSR allows nested monitoring of events to be performed by cascading one counter to a second counter 
located in another pair in the same block (see Figure 20-49 for the location of the flag).
Counters 0 and 1 form the first pair in the BPU block. Eith er counter 0 or 1 can be programmed to detect an event 
via MSR_MO B_ESCR0. Counters 0 and 2 can be cascaded in an y order, as can counters 1 and 3. It’s possible to set 
up 4 counters in the same block to cascade on two pairs of independent events. The pairing described also applies 
to subsequent blocks. Since the IQ PUB has two extra counters, cascading operates somewhat differently if 16 and 17 are involved. In the IQ block, counter 16 can only be cascaded from counter 14 (not from 12); counter 14 Vol. 3B 20-115PERFORMANCE MONITORING
cannot be cascaded from counter 16 using the CCCR casca de bit mechanism. Similar restrictions apply to counter 
17.
Example 20-1.  Counting Events
Assume a scenario where counter X is set up to count 200 occurrences of event A; then counter Y is set up to count 
400 occurrences of event B. Each counter is set up to co unt a specific event and overflow to the next counter. In 
the above example, counter X is preset for a count of -200  and counter Y for a count of -400; this setup causes the 
counters to overflow on the 200th and 400th counts respectively.
Continuing this scenario, counter X is set up to count inde finitely and wraparound on overflow. This is described in 
the basic performance counter setup procedure that begins  in Section 20.6.3.5.1, “Selecting Events to Count.” 
Counter Y is set up with the cascade flag in its associ ated CCCR MSR set to 1 and its enable flag set to 0.
To begin the nested counting, the enable bit for the counter  X is set. Once enabled, counter X counts until it over-
flows. At this point, counter Y is automatically enable d and begins counting. Thus counter X overflows after 200 
occurrences of event A. Counter Y then starts, counting 400 occurrences of event B before overflowing. When 
performance counters are cascaded, the counter Y would typica lly be set up to generate an interrupt on overflow. 
This is described in Section 20.6.3.5.8, “Generating an Interrupt on Overflow.” 
The cascading counters mechanism can be used to count a single event. The counting begins on one counter then 
continues on the second counter after the first counter overflows. This technique doubles the number of event 
counts that can be recorded, since the contents of the two counters can be added together.
20.6.3.5.7  EXTENDED CASCADING 
Extended cascading is a model-specific feature in the Intel NetBurst microarchitecture with CPUID DisplayFami-
ly_DisplayModel 0F_02, 0F_03, 0F_04, 0F_06. This feature us es bit 11 in CCCRs associat ed with the IQ block. See 
Table 20-88. 
The extended cascading feature can be adapted to the Interrupt based sampling usage model for performance 
monitoring. However, it is known that performance count ers do not generate PMI in cascade mode or extended 
cascade mode due to an erratum. This erratum applie s to processors with CPUID DisplayFamily_DisplayModel 
signature of 0F_02. For processors with CPUID Displa yFamily_DisplayModel signature of 0F_00 and 0F_01, the 
erratum applies to processors with stepping encoding greater than 09H. 
Counters 16 and 17 in the IQ block are frequently used  in processor event-based sampling or at-retirement 
counting of events indicating a stalled condition in the pipeline. Neither counter 16 or 17 can initiate the cascading 
of counter pairs using the cascade bit in a CCCR.
Extended cascading permits performance monitoring tools to use counters 16 and 17 to initiate cascading of two 
counters in the IQ block. Extended cascading from counter 16 and 17 is conceptually similar to cascading other 
counters, but instead of using CASC ADE bit of a CCCR, one of the four CASCNTxINTOy bits is used. 
Example 20-2.  Scenario for Extended Cascading
A usage scenario for extended cascading is to sample instru ctions retired on logical processor 1 after the first 4096 
instructions retired on logical processor 0. A procedure to  program extended cascading in this scenario is outlined 
below:Table 20-88.  CCR Names and Bit Positions 
CCCR Name:Bit Position Bit Name Description
MSR_IQ_CCCR1|2:11 ReservedMSR_IQ_CCCR0:11 CASCNT4INTO0 Allow coun ter 4 to cascade into counter 0
MSR_IQ_CCCR3:11 CASCNT5INTO3 Allow coun ter 5 to cascade into counter 3
MSR_IQ_CCCR4:11 CASCNT5INTO4 Allow coun ter 5 to cascade into counter 4
MSR_IQ_CCCR5:11 CASCNT4INTO5 Allow coun ter 4 to cascade into counter 520-116 Vol. 3BPERFORMANCE MONITORING
1. Write the value 0 to counter 12. 
2. Write the value 04000603H to MSR_CRU_ESCR0 (corre sponding to selecting the NBOGNTAG and NBOGTAG 
event masks with qualification restricted to logical processor 1).
3. Write the value 04038800H to MSR_IQ _CCCR0. This enables CASCNT4INTO0 and OVF_PMI. An ISR can sample 
on instruction addresses in this case (do not set ENABLE, or CASCADE).
4. Write the value FFFFF000H into counter 16.1.
5. Write the value 0400060CH to MSR_CRU_ESCR2 (corresponding to selecting the NBOGNTAG and NBOGTAG 
event masks  with qualification restricted to logical processor 0).

6. Write the value 00039000H to MSR_IQ_CCCR4 (set ENABLE bit, but not OVF_PMI).Another use for cascading is to locate stalled execution in a multithreaded application. Assume MOB replays in 
thread B cause thread A to stall. Getting a sample of th e stalled execution in this scenario could be accomplished 
by:
1. Set up counter B to count MOB replays on thread B.2. Set up counter A to count resource stalls on thread A; set its force overflow bit and the appropriate CASCNTx-
INTOy bit.
3. Use the performance monitoring interrupt to captur e the program execution data of the stalled thread.
20.6.3.5.8  Generating an Interrupt on Overflow
Any performance counter can be configured to generate a performance monitor interrupt (PMI) if the counter over-
flows. The PMI interrupt service routine can then collect information about the state of the processor or program 
when overflow occurred. This information can then be used with a tool like the Intel® VTune™ Performance 
Analyzer to analyze and tune program performance.
To enable an interrupt on counter overflow, the OVR_PMI fl ag in the counter’s associated CCCR MSR must be set. 
When overflow occurs, a PMI is generated through the loca l APIC. (Here, the performanc e counter entry in the local 
vector table [LVT] is set up to deliver the in terrupt generated by the PMI to the processor.)
The PMI service routine can use the OVF flag to determin e which counter overflowed when multiple counters have 
been configured to generate PMIs. Also, note that these processors mask PMIs upon receiving an interrupt. Clear 
this condition before leaving the interrupt handler.
When generating interrupts on overflow, the performance co unter being used should be preset to value that will 
cause an overflow after a specified number of events are counted plus 1. The simplest way to select the preset 
value is to write a negative number into the counter, as  described in Section 20.6.3.5.6, “Cascading Counters.” 
Here, however, if an interrupt is to be generated after 100 event counts, the counter should be preset to minus 100 
plus 1 (-100 + 1), or -99. The counter will then overflow after it counts 99 events and generate an interrupt on the 
next (100th) event counted. The difference of 1 for this count enables the interrupt to be generated immediately 
after the selected event count has been reached, instead of  waiting for the overflow to be propagation through the 
counter.
Because of latency in the microarchitecture between the ge neration of events and the generation of interrupts on 
overflow, it is sometimes difficult to generate an interrupt close to an event that caused it. In these situations, the 
FORCE_OVF flag in the CCCR can be used to improve reportin g. Setting this flag causes the counter to overflow on 
every counter increment, which in turn trigge rs an interrupt after every counter increment.
20.6.3.5.9  Counter Usage Guideline
There are some instances where the user must take care to configure counting logic properly, so that it is not 
powered down. To use any ESCR, even when it is being used  just for tagging, (any) one of the counters that the 
particular ESCR (or its paired ESCR) can be connected to should be enabled. If this is not done, 0 counts may 
result. Likewise, to use any counter, there must be some  event selected in a corres ponding ESCR (other than 
no_event, which generally has a select value of 0). Vol. 3B 20-117PERFORMANCE MONITORING
20.6.3.6  At-Retirement Counting
At-retirement counting provides a means counting only events that represent work committed to architectural 
state and ignoring work that was perf ormed speculatively and later discarded.
One example of this speculative activity is branch predic tion. When a branch misprediction occurs, the results of 
instructions that were decoded and executed down the mi spredicted path are canceled. If a performance counter 
was set up to count all executed instructions, the count wo uld include instructions whose results were canceled as 
well as those whose results committed to architectural state.
To provide finer granularity in event counting in these situ ations, the performance monitoring facilities provided in 
the Pentium 4 and Intel Xeon processors provide a mechanism for tagging events and then counting only those 
tagged events that represent committed results. Th is mechanism is called “at-retirement counting.” 
There are predefined at-retirement events and event metrics that can be used to for ta gging events when using at 
retirement counting. The following terminology is used in describing at-retirement counting:
•Bogus, non-bogus, retire — In at-retirement event descriptions, the te rm “bogus” refers to instructions or 
μops that must be canceled because they are on a path taken from a mispredicted branch. The terms “retired” 
and “non-bogus”  refer to instructions or μops along the path that results in committed architectural state 
changes as required by the program being executed. Thus instructions and μops are either bogus or non-
bogus, but not both. Several of the Pentium 4 and Intel Xeon processors’ performance monitoring events (such 
as, Instruction_Retired and Uops_Retired) can count instructions or μops that are retired based on the charac-
terization of bogus” versus non-bogus.
•Tagging — Tagging is a means of marking μops that have encountered a particular performance event so they 
can be counted at retirement. During the course of execution, the same event can happen more than once per 
μop and a direct count of the event would not provide an indication of how many μops encountered that event. 
The tagging mechanisms allow a μop to be tagged once during its lifeti me and thus counted once at retirement. 
The retired suffix is used for performance metrics that increment a count once per μop, rather than once per 
event. For example, a μop may encounter a cache miss more than once during its life time, but a “Miss Retired” 
metric (that counts the number of retired μops that encountered a cache miss) will increment only once for that 
μop. A “Miss Retired” metric would be useful for characterizing the performance of the cache hierarchy for a 
particular instruction sequence. Details of various performance metrics and how these can be constructed 
using the Pentium 4 and Intel Xeon processors performa nce events are provided in the Intel® 64 and IA-32 
Architectures Optimization Reference Manual (see Section 1.4, “Related Literature”). 
•Replay — To maximize performance for the common case, the Intel NetBurst microarchitecture aggressively 
schedules μops for execution before all the conditions for correct execution are guaranteed to be satisfied. In 
the event that all of these conditions are not satisfied, μops must be reissued. The mechanism that the Pentium 
4 and Intel Xeon processors use for this reissuing of μops is called replay. Some examples of replay causes are 
cache misses, dependence violations, and unforeseen resour ce constraints. In normal operation, some number 
of replays is common and unavoidable. An excessive nu mber of replays is an indication of a performance 
problem.
•Assist — When the hardware needs the assistance of microc ode to deal with some event, the machine takes 
an assist. One example of this is an underflow condition in the input operands of a floating-point operation. The 
hardware must internally modify the format of the oper ands in order to perform the computation. Assists clear 
the entire machine of μops before they begin and are costly.
20.6.3.6.1  Using At -Retirement Counting
Processors based on Intel NetBurst microarchitecture allow counting both events and μops that encountered a 
specified event. For a subset of the at-retirement events, a μop may be tagged when it encounters that event. The 
tagging mechanisms can be used in Interrupt-based even t sampling, and a subset of these mechanisms can be 
used in PEBS. There are four independent tagging mech anisms, and each mechanism uses a different event to 
count μops tagged with that mechanism: 
•Front-end tagging — This mechanism pertains to the tagging of μops that encountered front-end events (for 
example, trace cache and instruction counts) an d are counted with the Front_end_event event.
•Execution tagging — This mechanism pertains to the tagging of μops that encountered execution events (for 
example, instruction types) and are counted with the Execution_Event event.20-118 Vol. 3BPERFORMANCE MONITORING
•Replay tagging — This mechanism pertains to tagging of μops whose retirement is re played (for example, a 
cache miss) and are counted with the Replay_event event.  Branch mispredictions are also tagged with this 
•No tags — This mechanism does not use tags. It uses the Instr_retired and the Uops_ retired events.
Each tagging mechanism is independent from all others; that is, a μop that has been tagged using one mechanism

Each tagging mechanism is independent from all others; that is, a μop that has been tagged using one mechanism 
will not be detected with another mechanism’s tagged- μop detector. For example, if μops are tagged using the 
front-end tagging mechanisms, the Replay_event will not count those as tagged μops unless they are also tagged 
using the replay tagging mechanism. However, exec ution tags allow up to four different types of μops to be counted 
at retirement through execution tagging.
The independence of tagging mechanisms does not hold  when using PEBS. When using PEBS, only one tagging 
mechanism should be used at a time. 
Certain kinds of μops that cannot be tagged, including I/O, uncacheable and locked accesses, returns, and far 
There are performance monitoring events that support at -retirement counting: specifically the Front_end_event, 
Execution_event, Replay_event, Inst_retired, and Uops_ret ired events. The following sections describe the tagging 
mechanisms for using these events to tag μop and count tagged μops.
20.6.3.6.2  Tagging Mechanism for Front_end_event
The Front_end_event counts μops that have been tagged as encountering any of the following events:
• μop decode events — Tagging μops for μop decode events requires specifying  bits in the ESCR associated with 
the performance-monitoring event, Uop_type. 
•Trace cache events — Tagging μops for trace cache events may require specifying certain bits in the 
MSR_TC_PRECISE_EVENT MSR.
The MSRs that are supported by the front-end tagging mech anism must be set and one or both of the NBOGUS and 
BOGUS bits in the Front_end_event event mask must be  set to count events. None of the events currently 
supported requires the use of the MSR_TC_PRECISE_EVENT MSR. 
20.6.3.6.3  Tagging Mech anism For Execution_event
The execution tagging mechanism differs from other tagging mechanisms in how it causes tagging. One upstream  
ESCR is used to specify an event to detect and to specif y a tag value (bits 5 through 8) to identify that event. A 
second downstream  ESCR is used to detect μops that have been tagged with that tag value identifier using Execu-
tion_event for the event selection. 
The upstream ESCR that counts the event must have its tag enable flag (bit 4) set and must have an appropriate 
tag value mask entered in its tag value field. The 4-bit tag value mask specifies which of tag bits should be set for 
a particular μop. The value selected for the tag value should coin cide with the event mask selected in the down-
stream ESCR. For example, if a tag value of 1 is set, th en the event mask of NBOGUS0 should be enabled, corre-
spondingly in the downstream ESCR. The do wnstream ESCR detects and counts tagged μops. The normal (not tag 
value) mask bits in the downstream ESCR specify which tag bits to count. If any one of the tag bits selected by the 
mask is set, the related counter is incremented by one. The tag enable and tag value bits are irrelevant for the 
downstream ESCR used to select the Execution_event.
The four separate tag bits allow the user to simultaneously but distinctly count up to four execution events at 
retirement. (This applies for interrupt-based event sampling. There are additional restrictions for PEBS as noted in 
Section 20.6.3.8.3, “Setting Up the PEBS Buffer.”) It is al so possible to detect or count combinations of events by 
setting multiple tag value bits in the upstream ESCR or multiple mask bits in the downstream ESCR. For example, 
use a tag value of 3H in the upstream ESCR and use NBOGUS0/NBOGUS1 in the downstream ESCR event mask.
20.6.3.7  Tagging Mech anism for Replay_event
The replay mechanism enables tagging of μops for a subset of all replays before retirement. Use of the replay 
mechanism requires selecting the type of μop that may experience the repl ay in the MSR_PEBS_MATRIX_VERT 
MSR and selecting the type of event in the MSR_PEBS_ENABL E MSR. Replay tagging must also be enabled with the 
UOP_Tag flag (bit 24) in the MSR_PEBS_ENABLE MSR. Vol. 3B 20-119PERFORMANCE MONITORING
The replay tags defined in Table A-5 also enable Proce ssor Event-Based Sampling (PEBS, see Section 18.4.9). Each 
of these replay tags can also be used in normal sa mpling by not setting Bit 24 nor Bit 25 in IA_32_PEBS_EN-
ABLE_MSR. Each of these metrics requires that the Replay_Event be used to count the tagged μops.
20.6.3.8  Processor Even t-Based Sampling (PEBS)
The debug store (DS) mechanism in processors based on In tel NetBurst microarchitecture allow two types of infor-
mation to be collected for use in debugging and tuning programs: PEBS records and BTS records. See Section 
18.4.5, “Branch Trace Store (BTS),” for a description of the BTS mechanism.
PEBS permits the saving of precise architectural informat ion associated with one or more performance events in 
the precise event records buffer, which is part of the DS save area (see Section 18.4.9, “BTS and DS Save Area”). 
To use this mechanism, a counter is configured to overfl ow after it has counted a preset number of events. After 
the counter overflows, the processor copies the current state of the general-purpose and EFLAGS registers and 
instruction pointer into a record in the precise event records buffer. The processor then resets the count in the 
performance counter and restarts the counter. When the prec ise event records buffer is ne arly full, an interrupt is 
generated, allowing the precise event records to be save d. A circular buffer is not supported for precise event 
records.
PEBS is supported only for a subset of the at-retir ement events: Execution_event, Front_end_event, and 
Replay_event. Also, PEBS can only be carried out us ing the one performance counter, the MSR_IQ_COUNTER4 
MSR.
In processors based on Intel Core microarchitecture, a similar PEBS mechanism is also supported using 
IA32_PMC0 and IA32_PERFEVTSEL0 MSRs (See Section 20.6.2.4).
20.6.3.8.1  Detection of the Avai lability of the PEBS Facilities
The DS feature flag (bit 21) returned by the CPUID instruct ion indicates (when set) the availability of the DS mech-
anism in the processor, which supports the PEBS (and BTS) fa cilities. When this bit is set, the following PEBS facil-
ities are available:
•The PEBS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates (when clear) the availability of the 
PEBS facilities, including the MSR_PEBS_ENABLE MSR. 
•The enable PEBS flag (bit 24) in the MSR_PEBS_ENABL E MSR allows PEBS to be enabled (set) or disabled 
(clear).
•The IA32_DS_AREA MSR can be programme d to point to the DS save area. 
20.6.3.8.2  Setting Up the DS Save Area
Section 18.4.9.2, “Setting Up the DS Save Area,” describes  how to set up and enable the DS save area. This proce-
dure is common for PEBS and BTS.
20.6.3.8.3  Setting Up the PEBS Buffer
Only the MSR_IQ_COUNTER4 performance counter can be used  for PEBS. Use the following procedure to set up the 
processor and this counter for PEBS: 
1. Set up the precise event buffering facilities. Place valu es in the precise event buffer base, precise event index, 
precise event absolute maximum, and precise event interru pt threshold, and precise event counter reset fields 
of the DS buffer management area (see Figure 18-5) to set up the precise event records buffer in memory.
2. Enable PEBS. Set the Enable PEBS flag (bit 24) in MSR_PEBS_ENABLE MSR.3. Set up the MSR_IQ_COUNTER4 performance counter an d its associated CCCR and one or more ESCRs for 
PEBS.20-120 Vol. 3BPERFORMANCE MONITORING
20.6.3.8.4  Writing a PEBS Interrupt Service Routine 
The PEBS facilities share the same interrupt vector and in terrupt service routine (calle d the DS ISR) with the non-
precise event-based sampling and BTS facilities. To handle PEBS interrupts, PEBS handler code must be included in 
the DS ISR. See Section 18.4.9.5, “Writing the DS Interrupt  Service Routine,” for guidelines for writing the DS ISR.
20.6.3.8.5  Other DS Mechanism Implications
The DS mechanism is not available in the SMM. It is di sabled on transition to the SMM mode. Similarly the DS 
mechanism is disabled on the generation of a machine check exception and is cleared on processor RESET and INIT. 
The DS mechanism is available in real address mode.
20.6.3.9  Operating System Implications
The DS mechanism can be used by the operating system as a debugging extension to facilitate failure analysis. 
When using this facility, a 25 to 30 times slowdown can be expected due to the effects of the trace store occurring on every taken branch. 
Depending upon intended usage, the instruction pointers th at are part of the branch records or the PEBS records 
need to have an association with the corresponding proce ss. One solution requires the ability for the DS specific 
operating system module to be chained to the context swit ch. A separate buffer can then be maintained for each 
process of interest and the MSR pointing to the configur ation area saved and setup appropriately on each context 
switch. 
If the BTS facility has been enabled, then it must be disabl ed and state stored on transition of the system to a sleep

switch. 
If the BTS facility has been enabled, then it must be disabl ed and state stored on transition of the system to a sleep 
state in which processor context is lost. The state must be restored on return from the sleep state.
It is required that an interrupt gate be used for the DS in terrupt as opposed to a trap ga te to prevent the generation 
of an endless interrupt loop.
Pages that contain buffers must have mappings to the same physical address for all processes/logical processors, 
such that any change to CR3 will not change DS addresse s. If this requirement cannot be satisfied (that is, the 
feature is enabled on a per thread/process basis), then the operating system must ensure that the feature is 
enabled/disabled appropriately in the context switch code.
20.6.4 Performance Monitoring and Intel® Hype r-Threading Technology in Processors Based 
on Intel NetBurst® Microarchitecture
The performance monitoring capability of processors base d on Intel NetBurst microarchitecture and supporting 
Intel Hyper-Threading Technology is similar to that describ ed in Section 20.6.3. However, the capability is extended 
so that:
•Performance counters can be programmed to select events qualified by logical processor IDs. 
•Performance monitoring interrupts can be directed to a specific logical processor within the physical processor. 
The sections below describe performance counters, event qu alification by logical processor ID, and special purpose 
bits in ESCRs/CCCRs. They also describe MSR_PE BS_ENABLE, MSR_PEBS_MATRIX_VERT, and MSR_TC_PRE-
CISE_EVENT. 
20.6.4.1  ESCR MSRs 
Figure 20-51 shows the layout of an ESCR MSR in pr ocessors supporting Intel Hyper-Threading Technology. 
•T1_USR flag, bit 0 — When set, events are counted when thread 1 (logical processor 1) is executing at a 
current privilege level (CPL) of 1, 2, or 3. These priv ilege levels are generally used by application code and 
unprotected operating system code.Vol. 3B 20-121PERFORMANCE MONITORING
•T1_OS flag, bit 1 — When set, events are counted when thread 1 (logical processor 1) is executing at CPL of 
0. This privilege level is generally  reserved for protected operating sy stem code. (When both the T1_OS and 
T1_USR flags are set, thread 1 events are counted at all privilege levels.)
•T0_USR flag, bit 2 — When set, events are counted when thread 0 (logical processor 0) is executing at a CPL 
of 1, 2, or 3. 
•T0_OS flag, bit 3 — When set, events are counted when thread 0 (logical processor 0) is executing at CPL of 
0. (When both the T0_OS and T0_USR flags are set, th read 0 events are counted at all privilege levels.)
disables tagging. See Section 20.6.3.6, “At-Retirement Counting.”
The T0_OS and T0_USR flags and the T1_OS and T1_USR fl ags allow event counting and sampling to be specified 
for a specific logical processor (0 or 1) within an Inte l Xeon processor MP (See also: Section 9.4.5, “Identifying 
Logical Processors in an MP System,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Not all performance monitoring events can be detected with in an Intel Xeon processor MP on a per logical processor 
basis (see Section 20.6.4.4, “Performance Monitoring Events ”). Some sub-events (specified by an event mask bits) 
are counted or sampled without regard to which logica l processor is associated with the detected event. 
20.6.4.2  CCCR MSRs
Figure 20-52 shows the layout of a CCCR MSR in processo rs supporting Intel Hyper-Threading Technology. The 
functions of the flags and fields are as follows:
reset
•Active thread field, bits 16 and 17 — Enables counting depending on which logical processors are active 
(executing a thread). This field enable s filtering of events based on the stat e (active or inactive) of the logical 
processors. The encodings of this field are as follows:
00 — None. Count only when neither logical processor is active.Figure 20-51.  Event Selection Contro l Register (ESCR) for the Pentium 4 Processor, Inte l® Xeon® Processor, and 
Intel® Xeon® Processo r MP Supporting Hyper-Threading Technology31 24 8 0 1234 9 25 30
63 32
Select
T0_USRT0_OS5
Value
T1_USRT1_OSReserved20-122 Vol. 3BPERFORMANCE MONITORING
01 — Single. Count only when one logical processor is active (either 0 or 1).
10 — Both. Count only when both logical processors are active.
11 — Any. Count when either logical processor is active.
A halted logical processor or a logical processor in the “wait for SIPI” state is considered inactive. 
When set, event counts that are less than or equal to the threshold value result in a single count being delivered 
to the performance counter; when clear, counts grea ter than the threshold value result in a count being 
delivered to the performance counter (see Section 20.6.3.5.2, “Filtering Events”). The compare flag is not active unless the compare flag is set.
output for filtering event counts; when clear, rising edge detection is disabled. This flag is active only when the 
compare flag is set.
•OVF_PMI_T0 flag, bit 26 — When set, causes a performance monitor interrupt (PMI) to be sent to logical 
processor 0 when the counter overflows occurs; when clear, disables PMI generation for logical processor 0. Note that the PMI is generate on the next event count after the counter has overflowed.
•OVF_PMI_T1 flag, bit 27 — When set, causes a performance monitor interrupt (PMI) to be sent to logical 
processor 1 when the counter overflows occurs; when clear, disables PMI generation for logical processor 1. 
Note that the PMI is generate on the next event count after the counter has overflowed.
Counters,” for further details); when clear, disables cascading of counters.Figure 20-52.  Counter Configuration Control Register (CCCR)63 32
Active Thread
Edge
FORCE_OVF
OVF_PMI_T0Threshold
Cascade
ESCR
Select
OVF_PMI_T1ReservedVol. 3B 20-123PERFORMANCE MONITORING
20.6.4.3  IA32_P EBS_ENABLE MSR
In a processor supporting Intel Hyper-Threading Technolo gy and based on the Intel NetBurst microarchitecture, 
PEBS is enabled and qualified with two bits in the MSR_PEBS_ENABLE MSR:  bit 25 (ENABLE_PEBS_MY_THR) and 
26 (ENABLE_PEBS_OTH_THR) respectively. These bits do not ex plicitly identify a specific logical processor by logic 
processor ID(T0 or T1); instead, they allow a software ag ent to enable PEBS for subsequent threads of execution 
on the same logical processor on which the agent is running (“my thread”) or for the other logical processor in the 
physical package on which the agent is not running (“other thread”).
PEBS is supported for only a subset of the at-retir ement events: Execution_event, Front_end_event, and 
Replay_event. Also, PEBS can be carried out only with  two performance counters: MSR_IQ_CCCR4 (MSR address 
370H) for logical processor 0 and MSR_IQ_CCCR5 (MSR address 371H) for logical processor 1.

Performance monitoring tools should use a processor affinity  mask to bind the kernel mode components that need 
to modify the ENABLE_PEBS_MY_THR  and ENABLE_PEBS_OTH_THR bits in  the MSR_PEBS_ENABLE MSR to a 
specific logical processor. This is to prevent these ke rnel mode components from migrating between different 
logical processors due to OS scheduling.   
20.6.4.4  Performance Monitoring Events
When Intel Hyper-Threading Technology is active, many pe rformance monitoring events can be can be qualified by 
the logical processor ID, which corresponds to bit 0 of the initial APIC ID. This allows for counting an event in any 
or all of the logical processors. However, not all the events ha ve this logic processor specificity, or thread specificity. 
Here, each event falls into one of two categories: 
•Thread specific (TS)  — The event can be qualified as occurring on a specific logical processor.
•Thread independent (TI)  — The event cannot be qualified as being associated with a specific logical 
If for example, a TS event occurred in logical processo r T0, the counting of the event (as shown in Table 20-89) 
depends only on the setting of the T0_USR and T0_OS flag s in the ESCR being used to set up the event counter. 
The T1_USR and T1_OS flags have no effect on the count.
When a bit in the event mask field is TI, the effect of sp ecifying bit-0-3 of the associated ESCR are described in 
Table 15-6. For events that are marked as TI, the effect  of selectively specifying T0_USR, T0_OS, T1_USR, T1_OS 
bits is shown in Table 20-90. Table 20-89.  Effect of Logica l Processor and CPL Qualification 
for Logical-Processor- Specific (TS) Events
T1_OS/T1_USR = 00 T1_OS/T1_USR = 01 T1_OS/T1_USR = 11 T1_OS/T1_USR = 10
T0_OS/T0_USR = 00 Zero count Counts while T1 in USR Counts while T1 in OS or 
USRCounts while T1 in OS
T0_OS/T0_USR = 01 Counts while T0 in USR Counts while T0 in USR 
or T1 in USRCounts while (a) T0 in 
USR or (b) T1 in OS or (c) 
T1 in USRCounts while (a) T0 in OS 
or (b) T1 in OS
T0_OS/T0_USR = 11 Counts while T0 in OS or 
USRCounts while (a) T0 in OS 
or (b) T0 in USR or (c) T1 
in USRCounts irrespective of 
CPL, T0, T1Counts while (a) T0 in OS 
or (b) or T0 in USR or (c) 
T1 in OS
T0_OS/T0_USR = 10 Counts T0 in OS Counts T0 in OS or T1 in 
USRCounts while (a)T0 in Os 
or (b) T1 in OS or (c) T1 in USRCounts while (a) T0 in OS 
or (b) T1 in OS20-124 Vol. 3BPERFORMANCE MONITORING
20.6.4.5  Counting Clocks on systems with Intel® Hyper-Threading Technology in Processors Based on 
Intel NetBurst® Microarchitecture
20.6.4.5.1  Non-Halted Clockticks
Use the following procedure to program ESCRs and CCCRs to obtain non-halted clockticks on processors based on 
Intel NetBurst microarchitecture: 
1. Select an ESCR for the global_power_events and specify the RUNNING sub-event mask and the desired 
T0_OS/T0_USR/T1_OS/T1_USR bits for the targeted processor.
2. Select an appropriate counter.3. Enable counting in the CCCR for that counter by setting the enable bit.
20.6.4.5.2  Non-Sleep Clockticks
Performance monitoring counters can be configured to count clockticks whenever the performance monitoring 
hardware is not powered-down. To count Non-sleep Clockt icks with a performance-monitoring counter, do the 
1. Select one of the 18 counters.
2. Select any of the ESCRs whose events the selected co unter can count. Set its event select to anything other 
than “no_event”; the counter may be  disabled if this is not done.
3. Turn threshold comparison on in the CCCR by setting the compare bit to “1”.
4. Set the threshold to “15” and the complement to “1” in the CCCR. Since no event can exceed this threshold, the 
threshold condition is met every cycle and the counter coun ts every cycle. Note that this overrides any qualifi-
cation (e.g., by CPL) specified in the ESCR.
5. Enable counting in the CCCR for the counter by setting the enable bit.
In most cases, the counts produced by the non-halted and non-sleep metrics are equivalent if the physical package 
supports one logical processor and is not placed in a power-saving state. Operating systems may execute an HLT 
instruction and place a physical processor in a power-saving state.
On processors that support Intel Hyper-Threading Technolo gy (Intel HT Technology), each physical package can 
support two or more logical processors. Current implementati on of Intel HT Technology provides two logical proces-
sors for each physical processor. While both logical proc essors can execute two threads simultaneously, one logical 
processor may halt to allow the other logical processor to execute without sharing execution resources between 
two logical processors. 
Non-halted Clockticks can be set up to count the number of processor clock cycles for each logical processor when-
ever the logical processor is not halted (the count may include some portion of the clock cycles for that logical 
processor to complete a transition to a halted state). Ph ysical processors that support Intel HT Technology enter 
into a power-saving state if all logical processors halt.Table 20-90.  Effect of Logica l Processor and CPL Qualification 
for Non-logical-Processor-specific (TI) Events
T1_OS/T1_USR = 00 T1_OS/T1_USR = 01 T1 _OS/T1_USR = 11 T1_OS/T1_USR = 10 
T0_OS/T0_USR = 00 Zero count Counts while (a) T0 in 
USR or (b) T1 in USRCounts irrespective of 
or (b) T1 in OS 
T0_OS/T0_USR = 01 Counts while (a) T0 in 
USR or (b) T1 in USRCounts while (a) T0 in 
CPL, T0, T1Counts irrespective of 
CPL, T0, T1 
T0_OS/T0_USR = 11 Counts irrespective of 
CPL, T0, T1 
T0_OS/T0_USR = 0 Counts while (a) T0 in OS 
or (b) T1 in OSCounts irrespective of 
or (b) T1 in OSVol. 3B 20-125PERFORMANCE MONITORING
The Non-sleep Clockticks mechanism uses a filtering mech anism in CCCRs. The mechanism will continue to incre-
ment as long as one logical processor is not halted or in  a power-saving state. Applications may cause a processor 
to enter into a power-saving state by using an OS service th at transfers control to an OS's idle loop. The idle loop 
then may place the processor into a power-saving state af ter an implementation-dependent period if there is no 
work for the processor.
20.6.5 Performance Monitoring and Dual-Core Technology
The performance monitoring capability of dual-core proce ssors duplicates the microarchitectural resources of a 
single-core processor implementation. Each processor core has dedicated performance monitoring resources.
In the case of Pentium D processor, each logical processor is associated with dedicated resources for performance 
monitoring. In the case of Pentium processor Extreme edit ion, each processor core has dedicated resources, but 
two logical processors in the same core share performance monitoring resources (see Section 20.6.4, “Perfor-
mance Monitoring and Intel® Hyper-Threading Technology in Processors Based on Intel NetBurst® Microarchitec-
ture”). 
20.6.6 Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3 
Cache
The 64-bit Intel Xeon processor MP with up to 8-MByte L3 cache has a CPUID signature of family [0FH], model 
[03H or 04H]. Performance monitoring capabilities availabl e to Pentium 4 and Intel Xeon processors with the same 
values (see Section 20.1 and Section 20.6.4) apply to th e 64-bit Intel Xeon processor MP with an L3 cache. 
The level 3 cache is connected between the system bus an d IOQ through additional control logic. See Figure 20-53.
Additional performance monitoring capabilities and facilit ies unique to 64-bit Intel Xeon processor MP with an L3 
cache are described in this section. The facility for monitoring events consists of a set of dedicated model-specific registers (MSRs), each dedicated to a specific event. Programming of these MSRs requires using RDMSR/WRMSR 
instructions with 64-bit values.
The lower 32-bits of the MSRs at addresses 107CC throug h 107D3 are treated as 32 bit performance counter regis-
ters. These performance counters can be accessed using RDPMC instruction with the index starting from 18 
through 25. The EDX register return s zero when reading these 8 PMCs.
The performance monitoring capabilities consist of four events. These are:Figure 20-53.  Block Diagra m of 64-bit Intel®  Xeon® Processor MP with 8-MByte L3iBUSQ and iSNPQSystem Bus
3rd Level Cache
8 or 4 -way
IOQiFSB
Processor Core
(Front end, Execution, 
Retirement, L1, L220-126 Vol. 3BPERFORMANCE MONITORING
•IBUSQ event — This event detects the occurrence of micro-archit ectural conditions related to the iBUSQ unit.

8 or 4 -way
IOQiFSB
•IBUSQ event — This event detects the occurrence of micro-archit ectural conditions related to the iBUSQ unit. 
It provides two MSRs: MSR_IFSB_IBUSQ0 and MSR_IFSB_IBUSQ1. Configure sub-event qualification and enable/disable functions using the high 32 bits of th ese MSRs. The low 32 bits act as a 32-bit event counter. 
Counting starts after software writes a non-zero value to one or more of the upper 32 bits. See Figure 20-54.
•ISNPQ event — This event detects the occurrence of microarchitectural conditions related to the iSNPQ unit. 
It provides two MSRs: MSR_IFSB_I SNPQ0 and MSR_IFSB_ISNPQ1. Config ure sub-event qualifications and 
enable/disable functions using the high 32 bits of th e MSRs. The low 32-bits act as a 32-bit event counter. 
Counting starts after software writes a non-zero value to one or more of the upper 32-bits. See Figure 20-55.
•EFSB event — This event can detect the occurrence of micro-ar chitectural conditions related to the iFSB unit 
or system bus. It provides two MSRs: MSR_EFSB_DRD Y0 and MSR_EFSB_DRDY1. Configure sub-event qualifi-
cations and enable/disable functions using the high 32 bits  of the 64-bit MSR. The low 32-bit act as a 32-bit 
event counter. Counting starts after software writes a non- zero value to one or more of the qualification bits in 
the upper 32-bits of the MSR. See Figure 20-56.Figure 20-54.  MSR_IFSB_IBUSQx, Addresses: 107CCH and 107CDH
Figure 20-55.  MSR_IFSB_ISNPQx, Addresses: 107CEH and 107CFHL3_state_match46 3845 37 36 3334
Saturate
Fill_match
Eviction_match
Snoop_match
Type_match
T1_match
T0_matchReserved63 5655 48 32 49 57585960 35
11
32 bit event countMSR_IFSB_IBUSQx, Addresses: 107CCH and 107CDH
31 0
L3_state_match46 3845 37 36 3334
Saturate
T1_match
T0_matchReserved
63 5655 48 32 57585960 35 39
Agent_matchMSR_IFSB_ISNPQx, Addresses: 107CEH and 107CFH
32 bit event count0 31Vol. 3B 20-127PERFORMANCE MONITORING
•IBUSQ Latency event — This event accumulates weighted cycle counts for latency measurement of transac-
tions in the iBUSQ unit. The count is enabled by setting MSR_IFSB_CTRL6[bit 26] to 1; the count freezes after software sets MSR_IFSB_CTRL6[bit 26] to 0. MSR_IFSB_CNTR7 acts as a 64-bit event counter for this event. 
See Figure 20-57.
20.6.7 Performance Monitoring on L3 and Caching Bus Controller Sub-Systems
The Intel Xeon processor 7400 series and Dual-Core Intel Xe on processor 7100 series employ a distinct L3/caching 
bus controller sub-system. These sub-system have a uni que set of performance monitoring capability and 
programming interfaces that are largely co mmon between these two processor families. 
Intel Xeon processor 7400 series are based on 45 nm enhanced Intel Core microarchitecture. The CPUID signature 
is indicated by DisplayFamily_DisplayModel value of 06_1D H (see the CPUID instruction in Chapter 3, “Instruction 
Set Reference, A-L‚” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). Intel Xeon 
processor 7400 series have six processor cores that share an L3 cache. 
Dual-Core Intel Xeon processor 7100 series are based on Intel NetBurst microarchitecture, have a CPUID signature 
of family [0FH], model [06H] and a unified L3 cache sh ared between two cores. Each core in an Intel Xeon 
processor 7100 series supports Intel Hyper-Threading Te chnology, providing two logical processors per core. 
Both Intel Xeon processor 7400 series and Intel Xeon processor 7100 series support multi-processor configurations 
using system bus interfaces. In Intel Xeon processor 7400 series, the L3/caching bus controller sub-system 
provides three Simple Direct Interface (SDI) to service transactions originated the XQ-replacement SDI logic in 
each dual-core modules. In Intel Xeon processor 7100 series, the IOQ logic in each processor core is replaced with 
a Simple Direct Interface (SDI) logic. The L3 cache is  connected between the system bus and the SDI through 
additional control logic. See Figure 20-58 for the block configuration of six processor cores and the L3/Caching bus Figure 20-56.  MSR_EFSB_DRDYx, Addresses: 107D0H and 107D1H
Figure 20-57.  MSR_IFSB_CTL6, Address:  107D2H; MSR_IFSB_CNTR7, Address: 107D3HOther49 38 50 37 36 33 34
Saturate
OwnReserved63 5655 48 32 57585960 35 39
31 0
32 bit event countMSR_EFSB_DRDYx, Addresses: 107D0H and 107D1H
ReservedMSR_IFSB_CTL6 Address: 107D2H
MSR_IFSB_CNTR7 Address: 107D3HEnable63 0 57 59
63 0
64 bit event count20-128 Vol. 3BPERFORMANCE MONITORING
controller sub-system in Intel Xeon processor 7400 se ries. Figure 20-58 shows the block configuration of two 
processor cores (four logical processors) and the L3/Cachi ng bus controller sub-system in Intel Xeon processor 
7100 series.
Almost all of the performance monitoring capabilities available to processor cores with the same CPUID signatures 
(see Section 20.1 and Section 20.6.4) apply to Intel Xeon processor 7100 series. The MSRs used by performance 
monitoring interface are shared between two logical processors in the same processor core.
The performance monitoring capabilities available to processor with DisplayFamily_DisplayModel signature 06_17H 
also apply to Intel Xeon processor 7400 series. Each processor core provides its own set of MSRs for performance 
monitoring interface.
The IOQ_allocation and IOQ_active_entries events are not supported in Intel Xeon processor 7100 series and 7400 
series. Additional performance monitoring capabilities app licable to the L3/caching bus controller sub-system are 
described in this section. Figure 20-58.  Block Diagram of th e Intel® Xeon® Proc essor 7400 SeriesSDI interface
L2SDI interface
L2L3GBSQ, GSNPQ,
GINTQ, ...FSB
SDI
SDI interface
L2
Core Core Core Core Core CoreVol. 3B 20-129PERFORMANCE MONITORING
20.6.7.1  Overview of Performance Moni toring with L3/Caching Bus Controller 
The facility for monitoring events consists of a set of dedicated model-specific registers (MSRs). There are eight 
event select/counting MSRs that are dedicated to countin g events associated with specified microarchitectural 
conditions. Programming of these MSRs requires using RD MSR/WRMSR instructions with 64-bit values. In addition, 
an MSR MSR_EMON_L3_GL_CTL provides simplified interfac e to control freezing, resetting, re-enabling operation 
of any combination of these event select/counting MSRs. 
The eight MSRs dedicated to count occurr ences of specific conditions are further divided to count three sub-classes 
of microarchitectural conditions:
•Two MSRs (MSR_EMON_L3_CTR_CTL0 and MSR_EMON_L 3_CTR_CTL1) are dedicated to counting GBSQ 
events. Up to two GBSQ events can be programmed and counted simultaneously. 
•Two MSRs (MSR_EMON_L3_CTR_CTL2 and MSR_EMON_L 3_CTR_CTL3) are dedicated to counting GSNPQ 
•Four MSRs (MSR_EMON_L3_CTR_CTL4, MSR_EM ON_L3_CTR_CTL5, MSR_EMON_L3_CTR_CTL6, and 
MSR_EMON_L3_CTR_CTL7) are dedicated to counting external bus operations.
The bit fields in each of eight MSRs share the following common characteristics:
•Bits 63:32 is the event control field that includes an event mask and other bit fields that control counter 
operation. The event mask field specifies details of the microarchitectural condition, and its definition differs 
across GBSQ, GSNPQ, FSB. 
•Bits 31:0 is the event count field. If the specified cond ition is met during each relevant clock domain of the 
event logic, the matched condition signals the counter lo gic to increment the associated event count field. The 
lower 32-bits of these 8 MSRs at addresses 107CC thro ugh 107D3 are treated as 32 bit performance counter 
In Dual-Core Intel Xeon processor 7100 series, the unc ore performance counters can be accessed using RDPMC 
instruction with the index starting from 18 through 25. The EDX register returns zero when reading these 8 PMCs. 
In Intel Xeon processor 7400 series, RDPMC with ECX between 2 and 9 can be used to access the eight uncore 
performance counter/control registers. Figure 20-59.  Block Diagram of the Intel® Xeon® Processor 7100 SeriesSDI interface
Processor coreSDI interface
Processor coreL3GBSQ, GSNPQ,
SDI
Logical
processorLogical
processor20-130 Vol. 3BPERFORMANCE MONITORING
20.6.7.2  GBSQ Event Interface
The layout of MSR_EMON_L3_CTR_CTL0 and MSR_EMON_L3_C TR_CTL1 is given in Figure 20-60. Counting starts 
after software writes a non-zero value to one or more of the upper 32 bits. 
The event mask field (bits 58:32) consists of the following eight attributes:
•Agent_Select (bits 35:32): The definition of this fiel d differs slightly between Intel Xeon processor 7100 and 
7400. 
For Intel Xeon processor 7100 series, each bit specifies a logical processor in the physical package. The lower 
two bits corresponds to two logical processors in the fi rst processor core, the upper two bits corresponds to two 
logical processors in the second processor core. 0FH encoding matches transactions from any logical processor.

SDI
Logical
7400. 
For Intel Xeon processor 7400 series, each bit of [34:32] specifies the SDI logic of a dual-core module as the 
originator of the transaction. A value of 0111B in bits  [35:32] specifies transaction from any processor core.
•Data_Flow (bits 37:36): Bit 36 specifies demand transactions, bit 37 specifies prefetch transactions.
•Type_Match (bits 43:38): Specifies transaction types. If  all six bits are set, event count will include all 
transaction types.
•Snoop_Match: (bits 46:44): The three bits specify (in ascending bit position) clean snoop result, HIT snoop 
result, and HITM snoop results respectively.
•L3_State (bits 53:47): Each bit sp ecifies an L2 coherency state. 
•Core_Module_Select (bits 55:54): The valid encodings fo r L3 lookup differ slightly between Intel Xeon 
processor 7100 and 7400. 
For Intel Xeon processor 7100 series, 
— 00B: Match transactions from any core in the physical package— 01B: Match transactions from this core only
— 10B: Match transactions from the other core in the physical package
— 11B: Match transaction from both cores in the physical package
For Intel Xeon processor 7400 series, 
— 00B: Match transactions from any dual-core module in the physical package
— 01B: Match transactions from this dual-core module only
— 10B: Match transactions from either one of the ot her two dual-core modules in the physical packageFigure 20-60.  MSR_EMON_L3_CTR_CTL0/1, Addresses: 107CCH/107CDHCore_module_select44 3843 37 36 54 53
Saturate
Cross_snoop
Fill_eviction
Data_flow
Agent_selectReserved
63 5655 46 32 47 57585960 35
32 bit event count0 31MSR_EMON_L3_CTR_CTL0/1, Addresses: 107CCH/107CDH
L3_stateVol. 3B 20-131PERFORMANCE MONITORING
— 11B: Match transaction from more than one dual-core modules in the physical package
•Fill_Eviction (bits 57:56): The valid encodings are
— 00B: Match any transactions 
— 01B: Match transactions that fill L3— 10B: Match transactions that fill L3 without an eviction
— 11B: Match transaction fill L3 with an eviction
•Cross_Snoop (bit 58): The encodings are
— 0B: Match any transactions — 1B: Match cross snoop transactions
For each counting clock domain, if all eight attributes match, event logic signals to increment the event count field.
20.6.7.3  GSNPQ Event Interface
The layout of MSR_EMON_L3_CTR_CTL2 and MSR_EMON_L3_ CTR_CTL3 is given in Figure 20-61. Counting starts 
The event mask field (bits 58:32) consists of the following six attributes:
•Agent_Select (bits 37:32): The definition of this fiel d differs slightly between Intel Xeon processor 7100 and 
7400. 
•For Intel Xeon processor 7100 series, each of the lowest 4 bits specifies a logical processor in the physical 
package. The lowest two bits corresponds to two logical pr ocessors in the first processor core, the next two bits 
corresponds to two logical processors in the second processor core. Bit 36 specifies other symmetric agent 
transactions. Bit 37 specifies central agent transactions. 3FH encoding matches transactions from any logical 
For Intel Xeon processor 7400 series, each of the lowest  3 bits specifies a dual-core module in the physical 
package. Bit 37 specifies central agent transactions. 
•Type_Match (bits 43:38): Specifies transaction types. If  all six bits are set, event count will include any 
•L2_State (bits 53:47): Each bit specifies an L3 coherency state. 
•Core_Module_Select (bits 56:54): Bit 56 enables Core_Module_Select matching. If bit 56 is clear, Core_Mod-
ule_Select encoding is ignored. The valid encodings for th e lower two bits (bit 55, 54)  differ slightly between 
Intel Xeon processor 7100 and 7400.
For Intel Xeon processor 7100 series, if bit 56 is set, th e valid encodings for the lower two bits (bit 55, 54) are
— 00B: Match transactions from only one core (irrespective which core) in the physical package— 01B: Match transactions from this core and not the other core
— 10B: Match transactions from the other core in the physical package, but not this core
For Intel Xeon processor 7400 series, if bit 56 is set, th e valid encodings for the lower two bits (bit 55, 54) are
— 00B: Match transactions from only one dual-core mo dule (irrespective which module) in the physical 
package.
— 01B: Match transactions from one or more dual-core modules.
— 10B: Match transactions from two or more dual-core modules.
— 11B: Match transaction from all three dual-core modules in the physical package.
•Block_Snoop (bit 57): specifies blocked snoop.
For each counting clock domain, if all six attributes match, event logic signals to increment the event count field.20-132 Vol. 3BPERFORMANCE MONITORING
20.6.7.4  FSB Event Interface
The layout of MSR_EMON_L3_CTR_CTL4 through MSR_EMON _L3_CTR_CTL7 is given in Figure 20-62. Counting 
starts after software writes a non-zero value to one or more of the upper 32 bits. 
The event mask field (bits 58:32) is organized as follows:
•Bit 58: must set to 1.
•FSB_Submask (bits 57:32): Specifies FSB-specific sub-event mask.
The FSB sub-event mask defines a set of independent attributes. The event logic signals to increment the associ-
ated event count field if one of the attribute matches. So me of the sub-event mask bit counts durations. A duration 
event increments at most once per cycle.
20.6.7.4.1  FSB Sub-Event Mask Interface
•FSB_type (bit 37:32): Specifies different FSB transa ction types originated from  this physical package.
•FSB_L_clear (bit 38): Count clean snoop results from any source for transaction originated from this physical 
package.
•FSB_L_hit (bit 39): Count HIT snoop results from any source for transaction originated from this physical package.Figure 20-61.  MSR_EMON_L3_CTR_ CTL2/3, Addresses: 107CEH/107CFH
Figure 20-62.  MSR_EMON_L3_CTR_CTL4/5/6/7, Addresses: 107D0H-107D3HL2_state46 38 44 37 3643 54
Saturate
Type_matchReserved
63 5655 47 32 57585960 53 39
Agent_matchMSR_EMON_L3_CTR_CTL2/3, Addresses: 107CEH/107CFH
Block_snoop
Core_select
32 bit event count0 31
149 38 50 37 36 33 34
Saturate
FSB submaskReserved63 56 55 48 32 57585960 35 39MSR_EMON_L3_CTR_CTL4/5/6/7, Addresses: 107D0H-107D3H
32 bit event count0 31Vol. 3B 20-133PERFORMANCE MONITORING
•FSB_L_hitm (bit 40): Count HITM snoop results from any source for transaction originated from this physical 
package.
•FSB_L_defer (bit 41): Count DEFER respon ses to this processor’s transactions.
•FSB_L_retry (bit 42): Count RETRY responses to this processor’s transactions.
•FSB_L_snoop_stall (bit 43): Count snoop stalls to this processor’s transactions.
•FSB_DBSY (bit 44): Count DBSY assertions by this processor (without a concurrent DRDY).
•FSB_DRDY (bit 45): Count DRDY assertions by this processor.
•FSB_BNR (bit 46): Count BNR assertions by this processor.
•FSB_IOQ_empty (bit 47): Counts each bus clocks when the IOQ is empty.
•FSB_IOQ_full (bit 48): Counts each bus clocks when the IOQ is full.
•FSB_IOQ_active (bit 49): Counts each bus clocks  when there is at least one entry in the IOQ.
•FSB_WW_data (bit 50): Counts back-to-ba ck write transaction’s data phase.
•FSB_WW_issue (bit 51): Counts back-to-back write tr ansaction request pairs issued by this processor.
•FSB_WR_issue (bit 52): Counts back-to-back write-read transaction request pairs issued by this processor.
•FSB_RW_issue (bit 53): Counts back-to-back read-write transaction request pairs issued by this processor.
•FSB_other_DBSY (bit 54): Count DBSY assertions by another agent (without a concurrent DRDY).
•FSB_other_DRDY (bit 55): Count DRDY assertions by another agent.
•FSB_other_snoop_stall (bit 56): Count snoop stalls on the FSB due to another agent.
•FSB_other_BNR (bit 57): Count BNR assertions from another agent.
20.6.7.5  Common Even t Control Interface
The MSR_EMON_L3_GL_CTL MSR provides simplified access to query overflow status of the GBSQ, GSNPQ, FSB 
event counters. It also provides control bit fields to fr eeze, unfreeze, or reset those counters. The following bit 
fields are supported:
•GL_freeze_cmd (bit 0): Freeze the event count ers specified by the GL_event_select field.
•GL_unfreeze_cmd (bit 1): Unfreeze the event co unters specified by the GL_event_select field.
•GL_reset_cmd (bit 2): Clear the event count field of the event counters specified by the GL_event_select field. 
The event select field is not affected.
•GL_event_select (bit 23:16): Selects one or more event counters to subject to specified command operations 
indicated by bits 2:0. Bit 16 corresponds to  MSR_EMON_L3_CTR_CTL0, bit 23 corresponds to 
MSR_EMON_L3_CTR_CTL7.
•GL_event_status (bit 55:48): Indicates the overflow status of each event counters. Bit 48 corresponds to 
MSR_EMON_L3_CTR_CTL0, bit 55 corresponds to MSR_EMON_L3_CTR_CTL7.

In the event control field (bits 63:32) of each MSR, if th e saturate control (bit 59, see Figure 20-60 for example) is 
set, the event logic forces the value FFFF_FFFFH into the event count field instead of incrementing it. 
20.6.8 Performance Monitoring (P6 Family Processor)
The P6 family processors pr ovide two 40-bit performance counters, allowi ng two types of events to be monitored 
simultaneously. These can either count events or measur e duration. When counting events, a counter increments 
each time a specified event takes place or a specified num ber of events takes place. When measuring duration, it 
counts the number of processor clocks that occur while a specified condition is true. The counters can count events 
or measure durations that occur at any privilege level. 20-134 Vol. 3BPERFORMANCE MONITORING
NOTE
The performance-monitoring events found at https://perfmon-events.intel.com/ are intended to be 
used as guides for performance tuning. Counter valu es reported are not guaranteed to be accurate 
and should be used as a relative guide for tu ning. Known discrepancies are documented where 
The performance-monitoring counters are supported by fo ur MSRs: the performance event select MSRs (PerfEvt-
Sel0 and PerfEvtSel1) and the performance counter MSRs (PerfCtr0 and PerfCtr1). These registers can be read 
from and written to using the RDMSR and WRMSR instructions, respectively. They can be accessed using these 
instructions only when operating at priv ilege level 0. The PerfCtr0 and PerfCtr1 MSRs can be read from any privilege 
level using the RDPMC (read performance-monitoring counters) instruction.
NOTE
The PerfEvtSel0, PerfEvtSel1, Pe rfCtr0, and PerfCtr1 MSRs and th e events listed for P6 family 
processors are model-specific for P6 family proce ssors. They are not guaranteed to be available in 
other IA-32 processors.
20.6.8.1  PerfEvtSel0 and PerfEvtSel1 MSRs
The PerfEvtSel0 and PerfEvtSel1 MSRs control the operat ion of the performance-monitoring counters, with one 
register used to set up each counter. They specify the even ts to be counted, how they should be counted, and the 
privilege levels at which counting should take place. Figure 20-63 shows the flags and fields in these MSRs.
The functions of the flags and fields in the Pe rfEvtSel0 and PerfEvtSel1 MSRs are as follows:
•Event select field (bits 0 through 7) — Selects the event logic unit to detect certain microarchitectural 
•Unit mask (UMASK) field (bits 8 through 15) — Further qualifies the event logic unit selected in the event 
select field to detect a specific microarchitectural cond ition. For example, for some cache events, the mask is 
used as a MESI-protocol qualifier of cache states.
•USR (user mode) flag (bit 16) — Specifies that events are counted only when the processor is operating at 
privilege levels 1, 2 or 3. This flag can be used in conjunction with the OS flag.
•OS (operating system mode) flag (bit 17) — Specifies that events are counted only when the processor is 
operating at privilege level 0. This flag ca n be used in conjunction with the USR flag.
•E (edge detect) flag (bit 18) — Enables (when set) edge detection of events. The processor counts the 
number of deasserted to asserted transitions of any condition that can be expressed by the other fields. The mechanism is limited in that it does not permit back-t o-back assertions to be di stinguished. This mechanism 
allows software to measure not only the fraction of time spent in a particular state, but also the average length 
of time spent in such a state (for example, the ti me spent waiting for an interrupt to be serviced).Figure 20-63.  PerfEvtSel0 and PerfEvtSel1 MSRs31
EN—Enable counters *
USR—User Mode*Only available in PerfEvtSel0.Counter Mask EE
NI
N
ReservedI
N
VP
CU
S
RO
SUnit Mask (UMASK)(CMASK)Vol. 3B 20-135PERFORMANCE MONITORING
•PC (pin control) flag (bit 19) — When set, the processor toggles the PM i pins and increments the counter 
when performance-monitoring events occur;  when clear, the processor toggles the PM i pins when the counter 
overflows. The toggling of a pin is defined as assertion of  the pin for a single bus clock followed by deassertion.
•INT (APIC interrupt enable) flag (bit 20) — When set, the processor generates an exception through its 
local APIC on counter overflow.
•EN (Enable Counters) Flag (bit 22) — This flag is only present in the PerfEvtSel0 MSR. When set, 
performance counting is enabled in both performance- monitoring counters; when clear, both counters are 
disabled.
•Counter mask (CMASK) field (bits 24 through 31) — When nonzero, the processor compares this mask to 
the number of events counted during a single cycle. If th e event count is greater than or equal to this mask, the 
counter is incremented by one. Otherwise the counter is not incremented. This mask can be used to count 
events only if multiple occurrences happen per clock (for  example, two or more instructions retired per clock). 
If the counter-mask field is 0, then the counter is in cremented each cycle by the number of events that 
occurred that cycle.
20.6.8.2  PerfCtr0 and PerfCtr1 MSRs
The performance-counter MSRs (PerfCtr0 and PerfCtr1) co ntain the event or duration counts for the selected 
events being counted. The RDPMC instruction can be used by  programs or procedures running at any privilege level 
and in virtual-8086 mode to read these counters. The PCE flag in control register CR4 (bit 8) allows the use of this instruction to be restricted to only programs  and procedures running at privilege level 0.
tion to disable direct user access to the performance-monitoring counters, but provide a user-accessible program-ming interface that emulates the RDPMC instruction.
The WRMSR instruction cannot arbitrarily write to th e performance-monitoring counter MSRs (PerfCtr0 and 
PerfCtr1). Instead, the lower-order 32 bits of each MSR may be written with any value, and the high-order 8 bits 
are sign-extended according to the value of bit 31. This op eration allows writing both positive and negative values 
to the performance counters.
20.6.8.3  Starting and Stopping the Performance-Monitoring Counters
The performance-monitoring counters ar e started by writing valid setup information in the PerfEvtSel0 and/or 
PerfEvtSel1 MSRs and setting the enable  counters flag in the PerfEvtSel0 MSR.  If the setup is valid, the counters 
begin counting following the execution of a WRMSR instruction that sets the enable counter flag. The counters can be stopped by clearing the enable counters flag or by cl earing all the bits in the PerfEvtSel0 and PerfEvtSel1 MSRs. 
Counter 1 alone can be stopped by clearing the PerfEvtSel1 MSR.
20.6.8.4  Event and Time-S tamp Monitoring Software
To use the performance-monitoring counters and time-stamp  counter, the operating system needs to provide an 
event-monitoring device driver. This driver should in clude procedures for handling the following operations:
•Feature checking.
•Initialize and start counters.
•Stop counters.
•Read the event counters.
•Read the time-stamp counter.20-136 Vol. 3BPERFORMANCE MONITORING
The event monitor feature determination procedure must ch eck whether the current processor supports the perfor-
mance-monitoring counters and time-stamp counter. Th is procedure compares the family and model of the 
processor returned by the CPUID instruction with those of processors known to support performance monitoring. 
(The Pentium and P6 family processors support performa nce counters.) The procedure also checks the MSR and 
TSC flags returned to register EDX by the CPUID instructio n to determine if the MSRs and the RDTSC instruction are 
The initialize and start counters procedure sets the Perf EvtSel0 and/or PerfEvtSel1 MSRs for the events to be 
counted and the method used to count them and initialize s the counter MSRs (PerfCtr0 and PerfCtr1) to starting

counted and the method used to count them and initialize s the counter MSRs (PerfCtr0 and PerfCtr1) to starting 
counts. The stop counters procedure stops the performanc e counters (see Section 20.6.8.3, “Starting and Stopping 
the Performance-Monitoring Counters”).
The read counters procedure reads the values in the Perf Ctr0 and PerfCtr1 MSRs, and a read time-stamp counter 
procedure reads the time-stamp counter. These procedures would be provided in lieu of enabling the RDTSC and 
RDPMC instructions that allow application code to read the counters. 
20.6.8.5  Monitoring Counter Overflow
The P6 family processors provide the option of generati ng a local APIC interrupt when a performance-monitoring 
counter overflows. This mechanism is enabled by setting th e interrupt enable flag in either the PerfEvtSel0 or the 
PerfEvtSel1 MSR. The primary us e of this option is for statistical performance sampling. 
To use this option, the operating system should do the following things on the processor for which performance 
events are required to be monitored:
•Provide an interrupt vector for handling the counter-overflow interrupt.
•Initialize the APIC PERF local vector  entry to enable handling of performance-monitor counter overflow events.
•Provide an entry in the IDT that points to a stub exception handler that returns without executing any instruc-
tions.
•Provide an event monitor driver that provides the actual  interrupt handler and modifies the reserved IDT entry 
to point to its interrupt routine.
When interrupted by a counter overflow, the interru pt handler needs to perform the following actions:
•Save the instruction pointer (EIP register), code-segment selector, TSS segment selector, counter values and 
other relevant information at the time of the interrupt.
•Reset the counter to its initial setting and return from the interrupt.
An event monitor application utility or another applicatio n program can read the information collected for analysis 
of the performance of the profiled application.
20.6.9 Performance Monitoring (Pentium Processors)
The Pentium processor provides two 40-bit performance coun ters, which can be used to count events or measure 
duration. The counters are supported by three MSRs: the control and event select MSR (CESR) and the perfor-
mance counter MSRs (CTR0 and CTR1). These can be read from and written to using the RDMSR and WRMSR instructions, respectively. They can be accessed using these instructions only when operating at privilege level 0. 
Each counter has an associated external pin (PM0/BP0 and PM1/BP1), which can be used to indicate the state of the 
counter to external hardware.
NOTES
The CESR, CTR0, and CTR1 MSRs and the events lis ted for Pentium processors are model-specific 
for the Pentium processor.
applicable.Vol. 3B 20-137PERFORMANCE MONITORING
20.6.9.1  Control and Event Select Register (CESR)
The 32-bit control and event select MSR (CESR) controls  the operation of performance-monitoring counters CTR0 
and CTR1 and the associated pins (see Figure 20-64). To control each counter, the CESR register contains a 6-bit event select field (ES0 and ES1), a pin control flag (PC0 and PC1), and a 3-bit counter control field (CC0 and CC1). 
The functions of these fields are as follows:
•ES0 and ES1 (event select) fields (bits 0-5, bits 16-21) — Selects (by entering an event code in the field) 
up to two events to be monitored.
•CC0 and CC1 (counter control) fields (bits 6-8, bits 22-24) — Controls the operation of the counter. 
Control codes are as follows:
000 — Count nothing (counter disabled).
001 — Count the selected event while CPL is 0, 1, or 2.
010 — Count the selected event while CPL is 3.011 — Count the selected event regardless of CPL.
100 — Count nothing (counter disabled).
101 — Count clocks (duration) while CPL is 0, 1, or 2.110 — Count clocks (duration) while CPL is 3.
111 — Count clocks (duration) regardless of CPL.
The highest order bit selects between counting events an d counting clocks (duration); the middle bit enables 
counting when the CPL is 3; and the low-order bit enables counting when the CPL is 0, 1, or 2.
•PC0 and PC1 (pin control) flags (bits 9, 25) — Selects the function of the external performance-monitoring 
counter pin (PM0/BP0 and PM1/BP1). Setting one of th ese flags to 1 causes the processor to assert its 
associated pin when the counter has overflowed; setting the flag to 0 causes the pin to be asserted when the 
counter has been incremented. These flags permit the pins to be individually programmed to indicate the 
overflow or incremented condition. The external signaling of the event on the pins will lag the internal event by a few clocks as the signals are latched and buffered.
While a counter need not be stopped to sample its contents, it must be stopped and cleared or preset before 
switching to a new event. It is not possible to set one co unter separately. If only one event needs to be changed, 
the CESR register must be read, the appropriate bits modifi ed, and all bits must then be written back to CESR. At 
reset, all bits in the CESR register are cleared.
20.6.9.2  Use of the Performance-Monitoring Pins
When performance-monitor pins PM0/BP0 and/or PM1/BP 1 are configured to indicate when the performance-
monitor counter has incremented and an “occurrence event” is being counted, the associated pin is asserted (high) 
each time the event occurs. When a “duration event” is being counted, the associated PM pin is asserted for the Figure 20-64.  CESR MSR (Pentium Processor Only)31
PC1—Pin control 1
CC1—Counter control 1
ES1—Event select 1
PC0—Pin control 08 0
CC0—Counter control 0
ES0—Event select 016 15 2122 24
Reserved9 56
ESO CC0P
C
0ES1 CC1P
C
12526 1020-138 Vol. 3BPERFORMANCE MONITORING
entire duration of the event. When the performance-monito r pins are configured to indicate when the counter has 
overflowed, the associated PM pin is asserted when the counter has overflowed.
When the PM0/BP0 and/or PM1/BP1 pins are configured to signal that a counter has incremented, it should be 
noted that although the counters may increment by 1 or 2 in a single clock, the pins can only indicate that the event 
occurred. Moreover, since the internal clock frequency may be higher than th e external clock frequency, a single 
external clock may correspond to multiple internal clocks.
A “count up to” function may be provided when the event pin is programmed to signal an overflow of the counter. 
Because the counters are 40 bits, a carry out of bit 39 indica tes an overflow. A counter may be preset to a specific 
value less then 240 − 1. After the counter has been enabled and th e prescribed number of events has transpired, 
the counter will overflow. 
Approximately 5 clocks later, the overfl ow is indicated externally and appropriate action, such as signaling an inter-
rupt, may then be taken.
The PM0/BP0 and PM1/BP1 pins also serve to indicate breakp oint matches during in-circuit emulation, during which 
time the counter increment or overflow function of thes e pins is not available. After RESET, the PM0/BP0 and 
PM1/BP1 pins are configured for performance monitoring , however a hardware debugger may reconfigure these 
pins to indicate breakpoint matches.
20.6.9.3  Events Counted
Events that performance-monitoring counters can be set to  count and record (using CTR0 and CTR1) are divided in 
two categories: occurrence and duration:
•Occurrence events  — Counts are incremented each time an even t takes place. If PM0/BP0 or PM1/BP1 pins 
are used to indicate when a counter increments, the pins  are asserted each clock counters increment. But if an 
event happens twice in one clock, the counter incr ements by 2 (the pins are asserted only once).
•Duration events  — Counters increment the total number of clocks that the condition is true. When used to 
indicate when counters incremen t, PM0/BP0 and/or PM1/BP1 pins are asserted for the duration.
20.7 COUNTING CLOCKS
The count of cycles, also known as clockticks, forms the basis for measuring how long a program takes to execute. 
Clockticks are also used as part of efficiency ratios like cycles per instruction (CPI). Processor clocks may stop ticking under circumstances like the following:
•The processor is halted when there is nothing for the CPU to do. For example, the processor may halt to save 
power while the computer is servicing an I/O request. Wh en Intel Hyper-Threading Tech nology is enabled, both 
logical processors must be halted for performa nce-monitoring counters to be powered down.
•The processor is asleep as a result of being halted  or because of a power-management scheme. There are 
different levels of sleep. In the some deep sleep levels, the time-stamp counter stops counting.

In addition, processor core clocks may undergo transitions at different ratios relative to the processor’s bus clock 
frequency. Some of the situations that can cause processor core clock to undergo frequency transitions include:
•TM2 transitions.
•Enhanced Intel SpeedStep Technology transitions (P-state transitions).
For Intel processors that support TM2, the processor core clocks may operate at a frequency that differs from the 
Processor Base frequency (as indicated by processor freq uency information reported by CPUID instruction). See 
Section 20.7.2 for more detail.
Due to the above considerations there are several important clocks referenced in this manual:
•Base Clock  — The frequency of this clock is the frequency of the processor when the processor is not in turbo 
mode, and not being throttled via Intel SpeedStep.
•Maximum Clock — This is the maximum frequency of the processor when turbo mode is at the highest point.
•Bus Clock  — These clockticks increment at a fixed frequency and help coordinate the bus on some systems. Vol. 3B 20-139PERFORMANCE MONITORING
•Core Crystal Clock — This is a clock that runs at fixed frequency; it coordinates the clocks on all packages 
across the system.
•Non-halted Clockticks — Measures clock cycles in which the specified logical processor is not halted and is 
not in any power-saving state. When Intel Hyper-Threadin g Technology is enabled, ticks can be measured on a 
per-logical-processor basis. There are also performance events on dual-core processors that measure 
clockticks per logical processor when the processor is not halted.
•Non-sleep Clockticks  — Measures clock cycles in which the specified physical processor is not in a sleep 
mode or in a power-saving state. These ticks cannot be measured on a logical-processor basis.
•Time-stamp Counter  — See Section 18.17, “Time-Stamp Counter.”
•Reference Clockticks  — TM2 or Enhanced Intel SpeedStep technology are two examples of processor 
features that can cause processor core clockticks to represent non-uniform tick intervals due to change of bus 
ratios. Performance events that counts clockticks of a constant reference frequency was introduced Intel Core 
Duo and Intel Core Solo processors. The mechanism is further enhanced on processors based on Intel Core 
Some processor models permit clock cycles to be measured  when the physical processor is not in deep sleep (by 
using the time-stamp counter and the RDTSC instruction). Note that such ticks cannot be measured on a per-
logical-processor basis. See Section 18.17, “Time-St amp Counter,” for detail on processor capabilities.
The first two methods use performance counters and can be  set up to cause an interrupt upon overflow (for 
sampling). They may also be useful where it is easier fo r a tool to read a performance counter than to use a time 
stamp counter (the timestamp counter is accessed using the RDTSC instruction). 
For applications with a significant amount of I/O, there are two ratios of interest:
•Non-halted CPI  — Non-halted clockticks/instructions retired me asures the CPI for phases where the CPU was 
being used. This ratio can be measured on a logical-pr ocessor basis when Intel Hyper-Threading Technology is 
enabled.
•Nominal CPI  — Time-stamp counter ticks/instructions retire d measures the CPI over the duration of a 
program, including those periods when the machine halts while waiting for I/O.
20.7.1 Non-Halted Reference Clockticks
Software can use UnHalted Reference Cycles on either a general purpose performance counter using event mask 
0x3C and UMASK 0x01 or on fixed functi on performance counter 2 to count at a constant rate. These events count 
at a consistent rate irrespective of P-state, TM2, or frequency transitions that may occur to the processor. The 
UnHalted Reference Cycles event may count differently on the general purpose event and fixed counter.
20.7.2 Cycle Counting and Opport unistic Processor Operation
As a result of the state transitions due to opportunistic  processor performance operation (see Chapter 15, “Power 
and Thermal Management”), a logical processor or a processor core can operate at frequency different from the 
Processor Base frequency. 
The following items are expected to hold true irrespective  of when opportunistic processor operation causes state 
transitions:
•The time stamp counter operates at a fixed-rate frequency of the processor.
•The IA32_MPERF counter increments at a fixed frequenc y irrespective of any transitions caused by opportu-
nistic processor operation.
•The IA32_FIXED_CTR2 counter increments at the same TS C frequency irrespective of any transitions caused 
by opportunistic processor operation.
•The Local APIC timer operation is unaffected by opportunistic processor operation.
•The TSC, IA32_MPERF, and IA32_FIXED_CTR2 operate at close to the maximum non-turbo frequency, which is 
equal to the product of scalable bus frequency and maximum non-turbo ratio. 20-140 Vol. 3BPERFORMANCE MONITORING
20.7.3 Determining the Processor Base Frequency
For Intel processors in which the nominal core crystal clock frequency is enumerated in CPUID.15H.ECX and the 
core crystal clock ratio is encoded in CPUID.15H (see Tabl e 3-8 “Information Returned by CPUID Instruction”), the 
nominal TSC frequency can be determined by using the following equation:
Nominal TSC frequency = ( CPUID.15H.ECX[31:0] * CPUID.15H.EBX[31:0] ) ÷ CPUID.15H.EAX[31:0]
For Intel processors in which CPUID.15H.EBX[31:0] ÷ CPUID.0x15.EAX[31:0] is enumerated but CPUID.15H.ECX 
is not enumerated, Table 20-91 can be used to l ook up the nominal core crystal clock frequency.
20.7.3.1  For Intel® Processo rs Based on Sandy Bridge, Ivy Bridge, Haswell, and Broadwell 
Microarchitectures
The scalable bus frequency is encoded in the bit field MSR_PLATFORM_INFO[15:8] and the nominal TSC frequency 
can be determined by multiplying th is number by a bus speed of 100 MHz.
20.7.3.2  For Intel® Processors Based on Nehalem Microarchitecture
can be determined by multiplying this  number by a bus speed of 133.33 MHz.
20.7.3.3  For Intel Atom® Processors Based on Silvermont Microarc hitecture (Including Intel Processors 
Based on Airmont Microarchitecture)
can be determined by multiplying th is number by the scalable bus frequency. The scalable bus frequency is 
encoded in the bit field MSR_FSB_FREQ[2:0] for Intel Atom processors based on the Silvermont microarchitecture, 
and in bit field MSR_FSB_FREQ[3:0] for processors base d on the Airmont microarchitecture; see Chapter 2, 
“Model-Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 
4.
20.7.3.4  For Intel® Core™ 2 Proc essor Family and for Intel® Xeon® Processors Based on Intel Core 
For processors based on Intel Core microarchitecture, the scalable bus frequency is  encoded in the bit field 
MSR_FSB_FREQ[2:0] at (0CDH), see Chapter 2, “M odel-Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 4. The maximum resolved bus ratio can be read from the 
following bit field:
•If XE operation is disabled, the maximum resolved bu s ratio can be read in MSR_PLATFORM_ID[12:8]. It 
corresponds to the Processor Base frequency.Table 20-91.  Nominal Core Crystal Clock Frequency
Processor Families/Pro cessor Number Series1
NOTES:
1. For any processor in which CPUID.15H is enumerated and MSR_PL ATFORM_INFO[15:8] (which gives the scalable bus frequency) is 
available, a more accurate frequency can be obtained by using CPUID.15H.Nominal Core Crystal Clock Frequency
Intel® Xeon® Scalable Processor Family with CPUID signature 06_55H. 25 MHz6th and 7th generation Intel® Core™ processors  and Intel® Xeon® W Processor Family. 24 MHz
Next Generation Intel Atom® processors based on Goldmo nt Microarchitecture with 
CPUID signature 06_5CH (does not include Intel Xeon processors).19.2 MHzVol. 3B 20-141PERFORMANCE MONITORING
•IF XE operation is enabled, the maximum resolved bus ratio is given in MSR_PERF_STATUS[44:40], it 
corresponds to the maximum XE operation frequency configured by BIOS.
XE operation of an Intel 64 processor is implementation specific. XE operation can be  enabled only by BIOS. If 
MSR_PERF_STATUS[31] is set, XE operation is enabled. The MSR_PERF_STATUS[31] field is read-only.
20.8 IA32_PERF_CAPABILITIES MSR ENUMERATION
The layout of IA32_PERF_CAPABILITIES MSR is shown in Figure 20-65; it provides enumeration of a variety of 
interfaces:
•IA32_PERF_CAPABILITIES.LBR_FMT[bits 5:0]: encodes th e LBR format, details are described in Section 
18.4.8.1.
•IA32_PERF_CAPABILITIES.PEBSTrap[6]: Trap/Fault-like indicator of PEBS recording assist; see Section 
20.6.2.4.2.

18.4.8.1.
•IA32_PERF_CAPABILITIES.PEBSArchRegs[7]: Indicator of PEBS assist save architectural registers; see Section 
•IA32_PERF_CAPABILITIES.PEBS_FMT[bits 11:8]: Specifies th e encoding of the layout of PEBS records; see 
Section 20.6.2.4.2.
•IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[12]: Indicates IA32_DEBUGCTL.FREEZE_WHILE_SMM is 
supported if 1, see Section 20.8.1.
•IA32_PERF_CAPABILITIES.FULL_WRITE[13]: Indicates th e processor supports IA32_A_PMCx interface for 
updating bits 32 and above of IA32_PMCx; see Section 20.2.6.
•IA32_PERF_CAPABILITIES.PEBS_BASELINE [bit 14]: If set, the following is true:
— The IA32_PEBS_ENABLE MSR (address 3F1H) exists and all architecturally enumerated fixed and general-
purpose counters have corresponding bits in IA32_PEBS _ENABLE that enable generation of PEBS records. 
The general-purpose counter bits start at bit IA32_PEB S_ENABLE[0], and the fixed counter bits start at bit 
IA32_PEBS_ENABLE[32].
— The format of the PEBS record is enumerated  by IA32_PERF_CAPABILITIE S.PEBS_FMT; see Section 
— Extended PEBS is supported. All counters support th e PEBS facility, and all events (both precise and non-
precise) can generate PEBS records when PEBS is enab led for that counter. Note that not all events may be 
available on all counters.
— Adaptive PEBS is supported. The PEBS_DATA_CFG MSR (address 3F2H) and adaptive record enable bits 
(IA32_PERFEVTSELx.Adaptive_Recor d and IA32_FIXED_CTR_CTRL.FCx_Adaptive_Record) are supported. 
The definition of the PEBS_DATA_CFG MSR, including which bits are supported and how they affect the 
record, is enumerated by IA32_PERF_CAPABILITIES.PEBS_FMT; see Section 20.9.2.3.
— NOTE: Software is recommended to feature PEBS Ba seline when the following is true: IA32_PERF_CAPA-
BILITIES.PEBS_BASELINE[14] && IA32_PERF_CAPABILITIES.PEBS_FMT[11:8] ≥ 4.
•IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABLE[15]: If set, indicates that the architecture provides 
built in support for TMA L1 metrics through the PERF_METRICS MSR, see Section 20.3.9.3.
•IA32_PERF_CAPABILITIES.PEBS_OUTPUT_PT_AVAIL[16]: If se t on parts that enumerate support for Intel PT 
(CPUID.0x7.0.EBX[25]=1), setting IA32_PEBS_ENABLE.PEBS_ OUTPUT to 01B will result in PEBS output being 
written into the Intel PT trace stream. See Section 20.5.5.2.20-142 Vol. 3BPERFORMANCE MONITORING
20.8.1 Filtering of SMM Handler Overhead
When performance monitoring facilities and/or branch prof iling facilities (see Section 18.5, “Last Branch, Interrupt, 
and Exception Recording (Intel® Core™ 2 Duo and Intel Atom ® Processors)”) are enabled, these facilities capture 
event counts, branch records and branch trace messages occurring in a logical processor. The occurrence of inter-
rupts, instruction streams due to various interrupt handlers all contribute to the results recorded by these facilities.
If CPUID.01H:ECX.PDCM[bit 15] is 1, the processor su pports the IA32_PERF_CAPABILIT IES MSR. If IA32_PERF_-
CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is 1, the proce ssor supports the ability for system software using 
performance monitoring and/or branch profiling facilities to filter out the effects of servicing system management 
interrupts. 
If the FREEZE_WHILE_SMM capability is enabled on a logica l processor and after an SMI is delivered, the processor 
will clear all the enable bits of IA 32_PERF_GLOBAL_CTRL, save a copy of  the content of IA32_DEBUGCTL and 
disable LBR, BTF, TR, and BTS fields of IA32_DEBUGCT L before transferring control to the SMI handler. 
The enable bits of IA32_PERF_GLOBAL_CTRL will be set to 1, the saved copy of IA32_DEBUGCTL prior to SMI 
delivery will be restored , after the SMI hand ler issues RSM to complete its servicing. 
It is the responsibility of the SMM code to ensure the st ate of the performance monitori ng and branch profiling facil-
ities are preserved upon entry or until prior to exiting the SM M. If any of this state is modified due to actions by the 
SMM code, the SMM code is required to restore such st ate to the values present at entry to the SMM handler.
System software is allowed to set IA32_DEBUGCTL.FREEZ E_WHILE_SMM[bit 14] to 1 only supported as indicated 
by IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] reporting 1.
20.9 PEBS FACILITY
20.9.1 Extended PEBS
•The Extended PEBS feature supports Processor Event Based Sampling (PEBS) on all counters, both fixed 
function and general purpose; and all performance monitoring events, both precise and non-precise. PEBS can be enabled for the general purpose counters using PEBS_E N_PMCi bits of IA32_PEBS_ENABLE (i = 0, 1,..m). 
PEBS can be enabled for 'i' fixed function counters using the PEBS_EN_FIXEDi bits of IA32_PEBS_ENABLE (i = 
0, 1, ...n).Figure 20-65.  Layout of IA32_PERF_CAPABILITIES MSR 5  4  3  2  1  0 63 7  6 11             8 16 15    13 12
PEBS_TRAP (R/O)PEBS_ARCH_REG (R/O)PEBS_REC_FMT (R/O)SMM_FREEZE (R/O)FW_WRITE (R/O)
LBR_FMT (R/O)
ReservedPERF_METRICS_AVAILABLE (R/O)PEBS_OUTPUT_PT_AVAIL (R/O)Vol. 3B 20-143PERFORMANCE MONITORING
A PEBS record due to a precise event will be generated af ter an instruction that causes the event when the counter 
has already overflowed. A PEBS record  due to a non-precise event will occur at the next opportunity after the 
counter has overflowed, including immediately after an overflow is set by an MSR write.
Currently, IA32_FIXED_CTR0 counts instructions retire d and is a precise event. IA32_FIXED_CTR1, IA32_-
FIXED_CTR2 … IA32_FIXED_CTRm count as non-precise events.
The Applicable Counter field in the Basic Info Group of the PEBS record indicates which counters caused the PEBS 
record to be generated. It is in the same format as the enable bits for each counter in IA32_PEBS_ENABLE. As an example, an Applicable Counter field wi th bits 2 and 32 set would indicate that both general purpose counter 2 and 
fixed function counter 0 generated the PEBS record. 
•To properly use PEBS for the additional counters, software  will need to set up the counter reset values in PEBS 
portion of the DS_BUFFER_MANAGEME NT_AREA data structure that is indicated by the IA32_DS_AREA 
register. The layout of the DS_BUFFER_MANAGEMENT _AREA is shown in Figure 20-67. When a counter 
generates a PEBS records, the appropriate counter reset va lues will be loaded into that counter. In the above 
example where general purpose counter 2 and fixed func tion counter 0 generated the PEBS record, general 
purpose counter 2 would be reloaded with the value co ntained in PEBS GP Counter 2 Reset (offset 50H) and 
fixed function counter 0 would be reloaded with the value contained in PEBS Fixed Counter 0 Reset (offset 
80H).Figure 20-66.  Layout of IA32_PEBS_ENABLE MSR1  0 63
PEBS_EN_PMCm (R/W)PEBS_EN_FIXED0 (R/W)
PEBS_EN_PMC0 (R/W)PEBS_EN_FIXED1 (R/W)PEBS_EN_FIXEDn (R/W)n3 2 3 1 m
Reserved RESET Value – 00000000 _00000000 H ●  ●  ● ●  ●  ●20-144 Vol. 3BPERFORMANCE MONITORING
Extended PEBS support debuts on Intel Atom® processors based on the Goldmont Plus microarchitecture and 
future Intel® Core™ processors based on the Ice Lake microarchitecture.
20.9.2 Adaptive PEBS
The PEBS facility has been enhanced to collect the followi ng CPU state in addition to GPRs, EventingIP, TSC, and 
memory access related information collected by legacy PEBS:
•XMM registers
•LBR records (TO/FROM/INFO)
The PEBS record is restructured where fields are grouped into Basic group, Memory group, GPR group, XMM group, 
and LBR group. A new register MSR_PEBS_DATA_CFG provides software the capability to select data groups of interest and thus reduce the record size in memory and re cord generation latency. Hence, a PEBS record's size and 
layout vary based on the selected groups. The MSR also allows software to select LBR depth for branch data 
records.
By default, the PEBS record  will only contain the Basic group. Option ally, each counter can be configured to 
generate a PEBS records with the gr oups specified in MSR_PEBS_DATA_CFG.Figure 20-67.  PEBS Programming Environment00H
08H
10H
18H
20H
28H
30H
38H
40H
●●●PEBS Fixed Counter 0 Reset63          BTS Buffer Base          0
BTS Index
BTS Absolute Maximum
BTS Interrupt Threshold
PEBS Buffer Base
PEBS Index
PEBS Absolute Maximum
PEBS Interrupt Threshold
PEBS GP C ounter 0 Reset
PEBS GP C ounter 1 Reset
●●●
PEBS GP C ounter m ResetPEBS Config BufferDS Buffer Management
Branch Record 0
Branch Record NBTS Buffer
PEBS Record NPEBS BufferIA32_DS_AREA MSR
80H
PEBS Fixed Counter n ResetVol. 3B 20-145PERFORMANCE MONITORING
Details and examples for the Adapti ve PEBS capability follow below.
20.9.2.1  Adaptive_Record Counter Control
•IA32_PERFEVTSELx.Adaptive_Record[34]: If this bit is  set and IA32_PEBS_ENABLE.PEBS_EN_PMCx is set for 
the corresponding GP counter, an overflow of PMCx result s in generation of an adaptive PEBS record with state 
information based on the selections made in MSR_PEBS_D ATA_CFG. If this bit is not set, a basic record is 

08H
10H
18H
20H
28H
30H
38H
40H
BTS Index
PEBS Index
●●●
80H
•IA32_FIXED_CTR_CTRL.FCx_Adaptive_Record: If this bi t is set and IA32_PEBS_ENA BLE.PEBS_EN_FIXEDx is 
set for the corresponding Fixed counter, an overflow of FixedCtrx results in generation of an adaptive PEBS 
record with state information based on the selections ma de in MSR_PEBS_DATA_CFG. If this bit is not set, a 
basic record is generated.Figure 20-68.  Layout of IA32_PerfE vtSelX MSR Supporting Adaptive PEBSIA32_PerfEvtSelX
 Address Range: 0x186 to 0x18D
Scope: Thread
Reset value: 0x00000000.0000000Reserved
0UMask
Event_SelectUSROSEINTENINVCMask
31
63 32IN_TXIN_TXCP7 15 23
39 47 55
ADAPTIVE_RECORDAnyThrDeprecated20-146 Vol. 3BPERFORMANCE MONITORING
20.9.2.2  PEBS Record Format
The data fields in the PEBS record are aggregated into fi ve groups which are described in the sub-sections below. 
Processors that support Adaptive PEBS implement a ne w MSR called MSR_PEBS_DATA_CFG which allows software 
to select the data groups to be captur ed. The data groups are not placed at fixed locations in the PEBS record, but 
are positioned immediately after one another, thus making  the record format/size variable based on the groups 
selected.
20.9.2.2.1  Basic Info
The Basic group contains essential information for software to parse a record along with several critical fields. It is always collected.Figure 20-69.  Layout of IA32_FIXED_CTR_CTRL MSR Supporting Adaptive PEBS
Table 20-92.  Basic Info Group
Field Name Bit Width Description
Record Format [47:0] This field indicates which data grou ps are included in the record. The field is zero if 
none of the counte rs that triggered the current PEBS re cord have their 
Adaptive_Record bit set. Otherwise it contains the value of MSR_PEBS_DATA_CFG.
[63:48] This field provides the size of the cu rrent record in bytes. Selected groups are 
packed back-to-back in the record without gaps or padding for unselected groups.
AnyThr_FC0AnyThr_FC1AnyThr_FC2
IA32_Fixed_CTR_CTRL 
Address: 38DH
Reset value: 0x00000000.000000006355 47 393123 15 7 0FC3_ADAPTIVE_RECO RD
FC2_ADAPTIVE_RECO RD
FC1_ADAPTIVE_RECORD
FC0_ADAPTIVE_RECORDReserved
32PMI_FC3
Reserved
EN_FC3
PMI_FC2
EN_FC2
PMI_FC1
EN_FC1
PMI_FC0
EN_FC0DeprecatedVol. 3B 20-147PERFORMANCE MONITORING
20.9.2.2.2  Memory Access Info
This group contains the legacy PEBS memo ry-related fields; see Section 20.3.1.1.2. 
Beginning with 12th generation Intel Core processors, the memory access information group has been updated. 
New fields added are shaded gray in Table 20-94.Instruction Pointer [63:0] This field reports the Eventing Instruction Po inter (EventingIP) of the retired 
instruction that triggered the PEBS record generation. Note that this field is 
different than R/EIP which records the inst ruction pointer of the next instruction 
to be executed after record generation. The legacy R/EIP field has been removed.
Applicable Counters [63:0] The Applicable Counters field indicates which counters triggered the generation of 
the PEBS record, linking the record to sp ecific events. This allows software to 
correlate the PEBS record entry properly with the instruction that caused the 
event, even when multiple counters are configured to generate PEBS records and multiple bits are set in the field.
TSC [63:0] This field provides the time stamp counter value when the PEBS record was 
Table 20-93.  Memory Access Info Group
Memory Access Address [63:0] This field contains the linear a ddress of the source of the load, or linear address of 
the destination (target) of the store. This  value is written as a 64-bit address in 
Memory Auxiliary Info [63:0] When a MEM_TRANS_RETIRED.* event is configured in a General Purpose counter, 
this field contains an encoded value indi cating the memory hi erarchy source which 
satisfied the load. These encodings are detailed in Table 20-4 and Table 20-13. If 
the PEBS assist was triggered for a store uop, this field will contain information 
indicating the status of the stor e, as detailed in Table 20-14.
Memory Access Latency1
NOTES:
1. In certain conditions, high latencies in fields under “Memory Access Latency” may be observed even when the Data Src of the “Mem-
ory Auxiliary Info” field indicates a close source.[63:0] When a MEM_TRANS_RETIRED.* event is configured in a General Purpose counter, 
this field contains the la tency to service the load in core clock cycles.
TSX Auxiliary Info [31:0] This field contains the numbe r of cycles in the last TSX region, regardless of 
whether that region had aborted or committed.
[63:32] This field contains the abort details. Refer to Section 20.3.6.5.1.Table 20-92.  Basic Info Group (Contd.)20-148 Vol. 3BPERFORMANCE MONITORING
To determine which fields are supported for certain perfor mance monitoring events, consult the Memory Info attri-
bute in the event lists at https://download.01.org/perfmon/ .
NOTE
There may be additional block reasons, even if Data-Blk and Address-Blk are both clear, e.g., non-
optimal instruction latency.
On P-core, the new Data-Blk and Address-Blk bi ts require the event LD_BLOCKS.STORE_FORWARD 
(r8203) to be configured in a programmable counter.
20.9.2.2.3  GPRs
This group is captured when the GPR bit is enabled in MSR_PEBS_DATA_CFG. GPRs are always 64 bits wide. If they are selected for non 64-bit mode, the upper 32-bit of the legacy RAX - RDI and all contents of R8-15 GPRs will be 
filled with 0s. In 64bit mode, the full 64 bit value of each register is written.Table 20-94.  Updated Memory Access Info Group 
Field Name Sub-field Name Bits Description
Access Address 
(offset 0H)DLA [63:0] This field reports the data linear  address (DLA) of the memory access in 
canonical form. 
A zero value indicates the processor could not retrieve the address of the 
particular access.
Access Info 
(offset 8H)Data Src [3:0] An encoded value indicating the memory hierarchy source which satisfied the 
access. These encodings are detailed in Table 20-4.
A zero value indicates the processor could not retrieve the data source of the 
STLB-miss [4] A value of 1 indicates the access has missed the Second-level TLB (STLB).
Is-Lock [5] A value of 1 indicates the access wa s part of a locked (atomic) memory trans-
action.
Data-Blk [6] A value of 1 indicates the load was blocked since its data could not be forwarded 
from a preceding store.
Address-Blk [7] A value of 1 indicates the load was blocked due to potential address conflict with a preceding store.
Access Latency 
(offset 10H)Instruction 
Latency[15:0] Measured instruction latency in core cycles. 
For loads, the latency starts by the disp atch of the load operation for execution 
and lasts until completion of the instruction it belongs to. 
This field includes the entire latenc y including time for data-dependency 
resolution or TLB lookups.
Cache Latency [47:32] Measured cache access la tency in core cycles. 
For loads, the latency starts by the actual  cache access until th e data is returned 
by the memory subsystem. 
For stores, the latency starts when th e demand write acce sses the L1 data-
cache and lasts until the ca cheline write is completed in the memory subsystem.
This field does not include non-data-cache latency such as memory ordering 
checks or TLB lookups.
TSX
(offset 18H)Transaction 
Latency[31:0] This field contains the number of cy cles in the last TSX region, regardless of 
whether that region ha d aborted or committed.
Abort Info [63:32] This field contains the ab ort details. Refer to  Section 20.3.6.5.1.Vol. 3B 20-149PERFORMANCE MONITORING
The order differs from legacy. The ta ble below shows the order of the GPRs in Ice Lake microarchitecture.
The machine state reported in the PEBS record is the committed machine state immediately after the instruction 
that triggers PEBS completes.
For instance, consider the following instruction sequence:
MOV eax, [eax]; triggers PEBS record generation
NOP
If the mov instruction triggers PEBS record generation, the EventingIP field in the PEBS record will report the 
address of the mov, and the value of EA X in the PEBS record will show the va lue read from memory, not the target 
address of the read operation. And the value of  RIP will contain the linear address of the nop.
20.9.2.2.4  XMMs
This group is captured when the XMM bit is enabled in  MSR_PEBS_DATA_CFG and SSE is enabled. If SSE is not 
enabled, the fields will contain zeroes. XMM8-XMM15 will also contain zeroes if not in 64-bit mode.Table 20-95.  GPRs in Ice Lake Microarchitecture
Field Name Bit Width
RFLAGS [63:0]
RIP [63:0]
RAX [63:0]
RCX* [63:0]
RDX* [63:0]
RBX* [63:0]
RSP* [63:0]
RBP* [63:0]
RSI* [63:0]
RDI* [63:0]
R8 [63:0]
... ...
R15 [63:0]
Table 20-96.  XMMs
XMM0 [127:0]... ...
XMM15 [127:0]20-150 Vol. 3BPERFORMANCE MONITORING
20.9.2.2.5  LBRs
To capture LBR data in the PEBS record, the LBR bit in  MSR_PEBS_DATA_CFG must be enabled. The number of LBR

RIP [63:0]
RAX [63:0]
R8 [63:0]
... ...
R15 [63:0]
To capture LBR data in the PEBS record, the LBR bit in  MSR_PEBS_DATA_CFG must be enabled. The number of LBR 
entries included in the record can be configured  in the LBR_entries field of MSR_PEBS_DATA_CFG.
LBR entries are recorded into the record starting at LB R[TOS] and proceeding to LBR[TOS-1] and following. Note 
that LBR index is modulo the number of LBRs supporting on the processor.
20.9.2.3  MSR_PEBS_DATA_CFG
Bits in MSR_PEBS_DATA_CFG can be set to include data fi eld blocks/groups into adaptive records. The Basic Info 
group is always included in the record. Additionally, the number of LBR entries included in the record is configu-
rable.Table 20-97.  LBRs
LBR[].FROM [63:0] Bran ch from address.
LBR[].TO [63:0] Bran ch to address.
LBR[].INFO [63:0] Other LBR information, like timing. This field is described in more 
detail in Section 18.12. 1, “MSR_LBR_INFO_x MSR.”
Figure 20-70.  MSR_PEBS_DATA_CFGMSR_PEBS_DATA_CFG 
Address: 3F2H
Reset value : 0x00000000 .000000006355 47 393123 15 7 31LBR Entri esReserved
63LBRs
XMMs
GPRs
Memory InfoVol. 3B 20-151PERFORMANCE MONITORING
20.9.2.4  PEBS Record Examples
The following example shows the layout of the PEBS record when all data groups are selected (all valid bits in 
MSR_PEBS_DATA_CFG are set) and maximum number of LBRs are selected. There are no gaps in the PEBS record 
when a subset of the groups are selected, thus keeping the layout compact. Implementations that do not support 
some features will have to pad zeroes in the corresponding fields.Table 20-98.  MSR_PEBS_CFG Programming1
NOTES:
1. A write to the MSR will be ignored when IA32_MISC_ENABLE.PERFMON_AVAILABLE is zero (default).Bit Bit Index Access Description
Memory Info 0 R/W Setting th is bit will capture memory informat ion such as the linear address, 
data source and latency of the me mory access in the PEBS record.
GPRs 1 R/W Setting this bit will capture the co ntents of the General Purpose registers 
in the PEBS record.
XMMs 2 R/W Setting this bit will capture the co ntents of the XMM re gisters in the PEBS 
record.
LBRs 3 R/W Setting this bit will capture LBR TO, FROM, and INFO in the PEBS record.
Reserved2
2. Writing to the reserved bits will cause a GP fault.23:4 NA Reserved
LBR Entries 31:24 R/W Set the field to the desired number of entries minus 1. For example, if the 
LBR_entries field is 0, a single entry will be included in the record. To 
include 32 LBR entries, set the LBR_entries field to 31 (0x1F). To ensure 
all PEBS records are 16-byte aligned, it  is recommended to  select an even 
number of LBR entries (programmed into LBR_entries as an odd number).
Table 20-99.  PEBS Record Example 1
Offset Group Name Field Name Legacy Name (If Different)
0x0 Basic Info Record Format New
Record Size New
0x8 Instruction Po inter EventingRIP
0x10 Applicable Counters0x18 TSC
0x20 Memory Info Memory Access Address DLA
0x28 Memory Auxiliary Info DATA_SRC0x30 Memory Access Latency Load Latency
0x38 TSX Auxiliary Info HLE Information20-152 Vol. 3BPERFORMANCE MONITORING
The following example shows the layout of the PEBS record when Basic, GPR,  and LBR group with 3 LBR entries are 
selected.0x40 GPRs RFLAGS
0x48 RIP0x50 RAX
... ...
0x88 RDI0x90 R8
... ...
0xC8 R150xD0 XMMs XMM0 New... ...
0x1C0 XMM15
0x1D0 LBRs LBR[TOS].FROM New0x1D8 LBR[TOS].TO
0x1E0 LBR[TOS].INFO
... ...0x4B8 LBR[TOS +1].FROM
0x4C0 LBR[TOS +1].TO
0x4C8 LBR[TOS +1].INFO
Table 20-100.  PEBS Record Example 2
0x8 Instruction Pointer EventingRIP0x10 Applicable Counters
0x18 TSCTable 20-99.  PEBS Record Example 1Vol. 3B 20-153PERFORMANCE MONITORING
20.9.3 Precise Distribution of Inst ructions Retired (PDIR) Facility
Precise Distribution of Instructions Retired Facility is available via PEBS on some microarchitectures. Refer to 
Section 20.3.4.4.4. Counters that support PDIR also vary. See the processor specific sections for availability.
20.9.4 Reduced Skid PEBS
For precise events, upon triggering a PEBS assist, there will be a finite delay between the time the counter over-
flows and when the microcode starts to carry out its data  collection obligations. The Reduced Skid mechanism miti-
gates the “skid” problem by providing an early indication of when the counter is about to overflow, allowing the 
machine to more precisely trap on the instruction that ac tually caused the counter overflow thus greatly reducing 
skid.
This mechanism is a superset of the PDIR mechanism ava ilable in the Sandy Bridge microarchitecture. See Section 
20.3.4.4.4
In the Goldmont microarchitecture, the mechanism applies to all precise events including, INST_RETIRED, except 
for UOPS_RETIRED. However, the Reduced Skid mechanism is  disabled for any counter when the INV, ANY, E, or 
CMASK fields are set.
With Reduced Skid PEBS, the skid is precisely one even t occurrence. Hence if counting INST_RETIRED, PEBS will 
indicate the instruction that follows that which caused the counter to overflow.
For the Reduced Skid mechanism to operate correctly, th e performance monitoring counters should not be recon-
figured or modified when they are running with PEBS en abled. The counters need to be disabled (e.g., via 
IA32_PERF_GLOBAL_CTRL MSR) before changes to the config uration (e.g., what event is specified in IA32_PERFE-
VTSELx or whether PEBS is enabled for that counter via IA32_PEBS_ENABLE) or counter value (MSR write to 
IA32_PMCx and IA32_A_PMCx).0x20 GPRs RFLAGS
0x28 RIP0x30 RAX
... ...
0x68 RDI0x70 R8
... ...
0xA8 R150xB0 LBRs LBR[TOS].FROM New0xB8 LBR[TOS].TO
0xC0 LBR[TOS].INFO
... ...0xE0 LBR[TOS +1].FROM
0xE8 LBR[TOS +1].TO
0xF0 LBR[TOS +1].INFOTable 20-100.  PEBS Record Example 220-154 Vol. 3BPERFORMANCE MONITORING
20.9.5 EPT-Friendly PEBS
The 3rd generation Intel Xeon Scalable Family of processors based on Ice Lake microarchitecture (and later proces-
sors) and the 12th generation Intel Core processor (and later processors) support VMX guest use of PEBS when the 
DS Area (including the PEBS Buffer and DS Management Area ) is allocated from a paged pool of EPT pages. In such 
a configuration PEBS DS Area accesses may result in VM ex its (e.g., EPT violations due to “lazy” EPT page-table 
entry propagation), and in such cases the PEBS record will not be lost but instead will “skid” to after the subsequent 
VM Entry back to the guest. For precise events the guest will observe that the record sk id by one event occurrence, 
while for non-precise events the re cord will skid by one instruction.
20.9.6 PDist: Precise Distribution
PDist eliminates any skid or shadowing effects from PEBS. With PDist, the PEBS record will be generated precisely 
upon completion of the instruction or operation that causes the counter to overflow (there is no “wait for next 
occurrence” by default).
PDist is supported by selected counter s, and is only supported when thos e counters are programmed to count 
select precise events5. The legacy PEBS behavior applies to counter s that do not support PDist, unless specified 
otherwise. PDist requires that the INV, ANY, E, and CM ASK fields are cleared. Which counters support PDist, and 
which events are supported for PDist, is  model-specific. Further, the counter reload value must not be lesser than 
127 for PDist to operate.
For the PDist mechanism to operate correctly, the performanc e monitoring counters should not be reconfigured or 
modified when they are running with PEBS enabled. Th e counters need to be disabled (e.g., via IA32_PERF_-
GLOBAL_CTRL MSR) before changes to the configuration (e .g., what event is specified in IA32_PERFEVTSELx or 
whether PEBS is enabled for that counter via IA32_PEBS_E NABLE) or counter value (MSR write to IA32_PMCx and 
IA32_A_PMCx).
20.9.7 Load Latency Facility
The load latency facility provides software a means to ch aracterize the latencies of memory load operations to 
different levels of cache/memory hierarchy. This facility requires a processor supporting the enhanced PEBS record 
format in the PEBS buffer. 
Beginning with 12th generation Intel Core processors, the load latency facility supports all fields in Table 20-94, 
“Updated Memory Access Info Group,” in ad dition to the Memory Access Address field:
•The Instruction Latency  field measures the load latency from the load's first dispatch until final data 
writeback from the memory subsystem. The latency is repo rted for retired demand load operations and in core 
cycles (it accounts for re-dispatches and data dependencies).
•The Cache Latency  field measures the subset of cache access latency in core cycles. It starts from the actual 
cache access until the data is returned by the memory subsystem The latency is reported for retired demand 
load operations in core cycles (it does not account for memory ordering blocks).
•The Data Source field is an encoded value indicates the origin of the data obtained by the load instruction. The 
encoding is shown in Table 20-101. In the descriptions,  local memory refers to system memory physically

encoding is shown in Table 20-101. In the descriptions,  local memory refers to system memory physically 
attached to a processor package, and remote memory refers to system memory or cache physically attached 
to another processor package (in a server product).
•Through the Access Info  field, load latency features binary indi cations on certain blocks that the load 
operation may have encountered. Refer to STLB-miss, Is-L ock, Data-Blk and Address-Blk fields in Table 20-94.
NOTE
For loads triggered by software prefetch instructions, the cache related fields including Data Source 
and Cache Latency, report values as if the load wa s an L1 cache hit (the prefetch completes without 
waiting for data return, for performance reasons).
5. To determine whether an event is precise or supports PDis t, consult the relevant attr ibute in the event lists at https://down-
load.01.org/perfmon/.Vol. 3B 20-155PERFORMANCE MONITORING
To use this feature, software must complete the following steps:
•Set the Memory Info bit in the PEBS_DATA_CFG MSR.
•One of the relevant IA32_PERFEVTSELx MSRs is pr ogrammed to specify the event unit MEM_TRANS_RE-
TIRED.LOAD_LATENCY (IA32_PerfEvtSelX[15:0] = 1C DH). The corresponding counter, IA32_PMCx, will 
accumulate event counts for architecturally visible loads which exceed the programmed latency threshold 
specified separately in an MSR. Stores are ignored when  this event is programmed. The CMASK or INV fields of 
the IA32_PerfEvtSelX register used for counting load la tency must be 0. Writing other values will result in 
undefined behavior. 
cycles. Loads with instruction latency greater than this value are eligible for counting and PEBS data reporting. 
The minimum value that may be programmed in this register is 1.
register.
Refer to Section 20.3.4.4.2 for further implementation details of Load Latency.
20.9.8 Store Latency Facility
Store latency support is available on the 12th generation Intel Core processor. Store latency is a PEBS extension 
that provides a means to profile store memory accesses in the system. It complements the load latency facility.
Store latency leverages the PEBS facility where it can provide additional information about sampled stores. The 
additional information includes the data address, memory auxiliary information, and th e cache latency of the store 
access. Normal stores (those preceded with a read-for-o wnership) as well as stream ing stores are supported by 
the store latency facility.Table 20-101.  Data Source Encoding for Memory Accesses (Ice Lake and Later Microarchitectures) 
00H Unknown Data Source (the processor could not retrieve the origin  of this request).
01H L1 HIT. This request was sati sfied by the L1 data cache. (M inimal latency co re cache hit.)
02H FB HIT. This request was merged into an ou tstanding cache miss to sa me cache-line address.
04H L3 HIT. This request was satisfied by the L3 cache with no coherency actions performed (snooping).
05H XCORE MISS. This request was satisfie d by the L3 cache but involved a cohe rency check in some sibling core(s).
06H XCORE HIT. This request was satisfied by the L3 cache but involved a coherency check that hit a non-modified copy in 
a sibling core.
07H XCORE FWD. This request was satisfied by a sibling core wh ere either a modified (cross-core HITM) or a non-modified 
(cross-core FWD) cache- line copy was found.
08H Local Far Memory. This request has missed the L3  cache and was serviced  by local far memory.
09H Remote Far Memory. This request has missed the L3 cache and was serviced by remote far memory.0AH Local Near Memory. This request has missed the L3 cache and was serviced by local near memory.
0BH Remote Near Memory. This request has missed the L3 cache and was serviced by remote near memory.
0CH Remote FWD. This request has missed the L3 cache and a non-modified cache-line copy was forwarded from a 
remote cache.
0DH Remote HITM. This request has missed the L3 cache and a modified cache-line was forwarded from a remote cache.
0FH UC. The request was to uncacheable memory.20-156 Vol. 3BPERFORMANCE MONITORING
Memory store operations typically do not limit performanc e since they update the memory with no operation that 
directly depends on them. Thus, data out of this facility should be carefully used once stores are suspected as a 
performance limiter; for example, once the TMA node of Backend_Bound.Memory_Bound.Store_Bound is flagged6. 
To enable the store latency facility, software must complete the following steps: 
•Program the MEM_TRANS_RETIRED.STORE_SAMPLE even t on general-purpose performance-monitoring 
counter 0 (IA32_PERFEVTSEL0[15:0] = 2CDH).
•Setup the PEBS buffer to hold at least two records, se tting both ‘PEBS Absolute Maximum’ and ‘PEBS Interrupt 
Threshold’, should any other counter be used by  PEBS (that is whenever IA32_PEBS_ENABLE[x] ≠ 0 for x ≠ 0).
•Set IA32_PEBS_ENABLE[0].
The store latency information is written into a PEBS record as shown in Table 20-48. 
The store latency relies on the PEBS facility, so the PEBS configuration must be completed first. Unlike load latency, 
there is no option to filter on a subset of stores that exceed a certain threshold.
6. For more details about th e method, refer to Section B.1, “Top-Down Analysis Method” of the Intel® 64  and IA-32 Architectures Opti-
mization Reference Manual.Vol. 3B 21-1CHAPTER 21
IA-32 processors (beginning with the Intel386 processor) provide two ways to execute new or legacy programs 
that are assembled and/or compiled to run on an Intel 8086 processor: 
•Real-address mode.
•Virtual-8086 mode.
Figure 2-3 shows the relationship of these operating mo des to protected mode and system management mode 
(SMM). 
When the processor is powered up or reset, it is plac ed in the real-address mode. This operating mode almost 
exactly duplicates the execution environment of the Inte l 8086 processor, with some extensions. Virtually any 
program assembled and/or compiled to run on an Intel 8086 processor will run on an IA-32 processor in this mode.
When running in protected mode, the processor can be sw itched to virtual-8086 mode to run 8086 programs. This 
mode also duplicates the execution environment of the Intel 8086 processor, with extensions. In virtual-8086 
mode, an 8086 program runs as a separate protected-mo de task. Legacy 8086 programs are thus able to run 
under an operating system (such as Microsoft Windows* ) that takes advantage of protected mode and to use 
protected-mode facilities, such as the protected-mode in terrupt- and exception-handling facilities. Protected-mode 
multitasking permits multiple virtual-8086 mode tasks (wit h each task running a separate 8086 program) to be run 
on the processor along with other non-virtual-8086 mode tasks.
This section describes both the basic real-address mode  execution environment and the virtual-8086-mode execu-
tion environment, available on the IA-32 proce ssors beginning with the Intel386 processor. 
21.1 REAL-ADDRESS MODE
The IA-32 architecture’s real-address mode runs programs  written for the Intel 8086, Intel 8088, Intel 80186, and 
Intel 80188 processors, or for the real-address mode of the Intel 286, Intel386, Intel486, Pentium, P6 family, 
Pentium 4, and Intel Xeon processors.
The execution environment of the processor in real-addre ss mode is designed to duplicate the execution environ-
ment of the Intel 8086 processor. To an 8086 program, a processor operating in real-address mode behaves like a 
high-speed 8086 processor. The principal features of this architecture are defined in Chapter 3, “Basic Execution 
Environment,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
The following is a summary of the core features of the real-address mode execution environment as would be seen 
by a program written for the 8086:
•The processor supports a nominal 1-MByte physical addr ess space (see Section 21.1.1, “Address Translation in 
Real-Address Mode,” for specific details). This address sp ace is divided into segments, each of which can be up 
to 64 KBytes in length. The base of a segment is specif ied with a 16-bit segment selector, which is shifted left 
by 4 bits to form a 20-bit offset fr om address 0 in the address space. An operand within a segment is addressed 
with a 16-bit offset from the base of the segment. A physic al address is thus formed by adding the offset to the 
20-bit segment base (see Section 21.1.1, “A ddress Translation in Real-Address Mode”).
•All operands in “native 8086 code” are 8-bit or 16-bit va lues. (Operand size override prefixes can be used to 
access 32-bit operands.)

•Eight 16-bit general-purpose registers are provided: AX, BX, CX, DX, SP, BP, SI, and DI. The extended 32 bit 
registers (EAX, EBX, ECX, EDX, ESP, EB P, ESI, and EDI) are accessible to prog rams that explicitly perform a size 
override operation.
•Four segment registers are provided: CS, DS, SS, and ES. (The FS and GS registers are accessible to programs that explicitly access them.) The CS register contains the segment selector for the code segment; the DS and 
ES registers contain segment selectors for data segments; and the SS register contains the segment selector 
for the stack segment.
•The 8086 16-bit instruction pointer (IP) is mapped to the lo wer 16-bits of the EIP register. Note this register is 
a 32-bit register and unintentional address wrapping may occur.21-2 Vol. 3B8086 EMULATION
•The 16-bit FLAGS register contains status and control flag s. (This register is mapped to the 16 least significant 
bits of the 32-bit EFLAGS register.)
•All of the Intel 8086 instructions are supported (see Se ction 21.1.3, “Instructions Supported in Real-Address 
Mode”).
•A single, 16-bit-wide stack is provided for handling proc edure calls and invocations of interrupt and exception 
handlers. This stack is contained in the stack segment identified with the SS register. The SP (stack pointer) 
register contains an offset into the stack segment. Th e stack grows down (toward lower segment offsets) from 
the stack pointer. The BP (base pointer) register also cont ains an offset into the stack segment that can be used 
as a pointer to a parameter list. When a CALL instru ction is executed, the processor pushes the current 
instruction pointer (the 16 least-significant bits of the EIP register and, on far calls, the current value of the CS 
register) onto the stack. On a return, initiated with a RET instruction, the processor pops the saved instruction 
pointer from the stack into the EIP register (and CS register on far returns). When an implicit call to an interrupt 
or exception handler is executed, the processor pushes the EIP, CS, and EFLAGS (low-order 16-bits only) registers onto the stack. On a return from an interrupt or  exception handler, initiated with an IRET instruction, 
the processor pops the saved instruction pointer and EFLAGS image from the stack into the EIP, CS, and 
EFLAGS registers.
•A single interrupt table, called the “interrupt vector table” or “interrupt table,” is provided for handling 
interrupts and exceptions (see Figure 21-2). The interrupt table (which has 4-byte entries) takes the place of 
the interrupt descriptor table (IDT, with 8-byte entrie s) used when handling protected-mode interrupts and 
exceptions. Interrupt and exception ve ctor numbers provide an index to entries in the interrupt table. Each 
entry provides a pointer (called a “vector”) to an in terrupt- or exception-handling procedure. See Section 
21.1.4, “Interrupt and Exception Handling,” for more deta ils. It is possible for software to relocate the IDT by 
means of the LIDT instruction on IA-32 proc essors beginning with the Intel386 processor.
•The x87 FPU is active and available to execute x87 FPU instructions in real-address mode. Programs written to 
run on the Intel 8087 and Intel 287 math coprocessors ca n be run in real-address mode without modification.
The following extensions to the Intel 8086 execution environment are availabl e in the IA-32 architecture’s real-
address mode. If backwards compatibility  to Intel 286 and Intel 8086 processors is required, these features should 
not be used in new programs written to run in real-address mode.
•Two additional segment registers (FS and GS) are available.
•Many of the integer and system instructions that have be en added to later IA-32 processors can be executed in 
real-address mode (see Section 21.1.3, “Instructions Supported in Real-Address Mode”). 
•The 32-bit operand prefix can be used in real-address mode programs to execute the 32-bit forms of instruc-
tions. This prefix also allows real-address mode programs to use the processor’s 32-bit general-purpose 
•The 32-bit address prefix can be used in real -address mode programs, allowing 32-bit offsets.
The following sections describe address formation, regist ers, available instructions, and interrupt and exception 
handling in real-address mode. For information on I/O in  real-address mode, see Chapter 19, “Input/Output,” of 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. 
21.1.1 Address Translation in Real-Address Mode
In real-address mode, the processor does not interpret segment selectors as indexes into a descriptor table; 
instead, it uses them directly to form linear addresses as the 8086 processor does. It shifts the segment selector 
left by 4 bits to form a 20-bit base address (see Figu re 21-1). The offset into a segment is added to the base 
address to create a linear address that maps  directly to the physical address space. 
When using 8086-style address translation, it is possible to specify addresses larger than 1 MByte. For example, 
with a segment selector value of FFFFH and an offset of FFFFH, the linear (and physical) address would be 10FFEFH 
(1 megabyte plus 64 KBytes). The 8086 processor, which can form addresses only up to 20 bits long, truncates the 
high-order bit, thereby “wrapping” this address to FFEF H. When operating in real-address mode, however, the 
processor does not truncate such an address and uses it as a physical address. (Note, however, that for IA-32 
processors beginning with the Intel486 processor, the A2 0M# signal can be used in real-address mode to mask 
address line A20, thereby mimicking the 20-bit wrap-around behavior of the 8086 processor.) Care should be take 
to ensure that A20M# based address wrapping is handled correctly in multiprocessor based system.Vol. 3B 21-38086 EMULATION
The IA-32 processors beginning with the Intel386 processor can generate 32-bit offsets using an address override 
prefix; however, in real-address mode, the value of a 32 -bit offset may not exceed FFFFH without causing an 
For full compatibility with Intel 286 real-address mode, ps eudo-protection faults (interrupt 12 or 13) occur if a 32-
bit offset is generated outside the range 0 through FFFFH.
21.1.2 Registers Supported in Real-Address Mode
The register set available in real-address mode includes all the registers defined for the 8086 processor plus the 
new registers introduced in later IA-32 processors, such as  the FS and GS segment registers, the debug registers, 
the control registers, and the floating-point unit register s. The 32-bit operand prefix  allows a real-address mode 
program to use the 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI).
21.1.3 Instructions Supported in Real-Address Mode
The following instructions make up the core instruction set for the 8086 processor. If backwards compatibility to 
the Intel 286 and Intel 8086 processors is required, only  these instructions should be used in a new program 
written to run in real-address mode.
•Move (MOV) instructions that move operands between  general-purpose registers, segment registers, and 
between memory and general-purpose registers.
•The exchange (XCHG) instruction.
•Load segment register instructions LDS and LES.
•Arithmetic instructions ADD, AD C, SUB, SBB, MUL, IMUL, DIV, IDIV, INC, DEC, CMP, and NEG.
•Logical instructions AND, OR, XOR, and NOT.
•Decimal instructions DAA, DAS, AAA, AAS, AAM, and AAD.
•Stack instructions PUSH and POP (to general-purpose registers and segment registers).
•Type conversion instructions CWD, CDQ, CBW, and CWDE.
•Shift and rotate instructions SAL, SHL,  SHR, SAR, ROL, ROR, RCL, and RCR.
•TEST instruction.
•Control instructions JMP, J cc, CALL, RET, LOOP, LOOPE, and LOOPNE.
•Interrupt instructions INT n, INTO, and IRET.
•EFLAGS control instructions STC, CLC, CMC, CLD, STD, LAHF, SAHF, PUSHF, and POPF.
•I/O instructions IN, INS, OUT, and OUTS.
•Load effective address (LEA) instruction, and translate (XLATB) instruction.Figure 21-1.  Real-Address Mode Address Translation19 0
16-bit Segment Selector3
0  0  0  0 Base
19 0
16-bit Effective Address15
0  0  0  0 Offset
0
20-bit Linear AddressLinear
Address+
=4
16
1921-4 Vol. 3B8086 EMULATION
•LOCK prefix.
•Repeat prefixes REP, REPE, REPZ, REPNE, and REPNZ.
•Processor halt (HLT) instruction.
•No operation (NOP) instruction.
The following instructions, added to later IA-32 processo rs (some in the Intel 286 processor and the remainder in 
the Intel386 processor), can be executed in real-addre ss mode, if backwards compatibility to the Intel 8086 
processor is not required.
•Move (MOV) instructions that operate on the control and debug registers.
•Load segment register instructions LSS, LFS, and LGS.
•Generalized multiply instructions and multiply immediate data.
•Shift and rotate by immediate counts.
•Stack instructions PUSHA, PUSHAD, POPA, POPAD, and PUSH immediate data.
•Move with sign extension instructions MOVSX and MOVZX.

0  0  0  0 Base
19 0
0
Address+
=4
16
•Long-displacement J cc instructions.
•Exchange instructions CMPXCHG, CMPXCHG8B, and XADD. 
•String instructions MOVS, CMPS, SCAS, LODS, and STOS. 
•Bit test and bit scan instructions BT, BTS, BTR, BTC, BSF, and BSR; the byte-set-on condition instruction SET cc; 
and the byte swap (BSWAP) instruction.
•Double shift instructions SHLD and SHRD.
•EFLAGS control instructions PUSHF and POPF.
•ENTER and LEAVE control instructions.
•BOUND instruction.
•CPU identification (CPUID) instruction.
•System instructions CLTS, INVD, WINVD, INVLPG, LG DT, SGDT, LIDT, SIDT, LMSW, SMSW, RDMSR, WRMSR, 
RDTSC, and RDPMC.
Execution of any of the other IA-32 architecture instructions (not given in the previous two lists) in real-address 
mode result in an invalid-opcode  exception (#UD) being generated.
21.1.4 Interrupt and Exception Handling
When operating in real-address mode, software must prov ide interrupt and exception-handling facilities that are 
separate from those provided in protec ted mode. Even during the early stages  of processor initialization when the 
processor is still in real-address mode, elementary real -address mode interrupt and exception-handling facilities 
must be provided to ensure reliable operation of the proce ssor, or the initialization code must ensure that no inter-
rupts or exceptions will occur.
The IA-32 processors handle interrupts and exceptions in real-address mode similar to the way they handle them 
in protected mode. When a processor receives an interrupt or generates an exception, it uses the vector number of 
the interrupt or exception as an index into the interrupt ta ble. (In protected mode, the interrupt table is called the 
interrupt descriptor table (IDT) , but in real-address mode, the table is usually called the interrupt vector 
table , or simply the interrupt table .) The entry in the interrupt vector table provides a pointer to an interrupt- or 
exception-handler procedure. (The pointer consists of a segment selector for a code segment and a 16-bit offset 
into the segment.) The processor performs  the following actions to make an implicit call to the selected handler:
1. Pushes the current values of the CS and EIP registers on to the stack. (Only the 16 least-significant bits of the 
EIP register are pushed.)
2. Pushes the low-order 16 bits of the EFLAGS register onto the stack.
3. Clears the IF flag in the EFLAGS register to disable interrupts.
4. Clears the TF, RF, and AC flags, in the EFLAGS register.Vol. 3B 21-58086 EMULATION
5. Transfers program control to the location specified in the interrupt vector table.
An IRET instruction at the end of the handler procedure re verses these steps to return program control to the inter-
rupted program. Exceptions do not return error codes in real-address mode.
The interrupt vector table is an array of 4-byte entries (s ee Figure 21-2). Each entry consists of a far pointer to a 
handler procedure, made up of a segment selector and an offset. The processor scales the interrupt or exception 
vector by 4 to obtain an offset into the interrupt table. Following reset, the base of the interrupt vector table is 
located at physical address 0 and its limit is set to 3FFH. In the Intel 8086 processor, the base address and limit of 
the interrupt vector table cannot be changed. In the later IA-32 processors, the base address and limit of the inter-
rupt vector table are contained in the IDTR regist er and can be changed using the LIDT instruction. 
(For backward compatibility to Intel 8086 processors, the default base address and limit of the interrupt vector 
table should not be changed.)
Table 21-1 shows the interrupt and exception vectors that  can be generated in real-address mode and virtual-8086 
mode, and in the Intel 8086 processor. See Chapter 6, “Int errupt and Exception Handling‚” for a description of the 
exception conditions.
21.2 VIRTUAL-8086 MODE
Virtual-8086 mode is actually a special type of a task th at runs in protected mode. When the operating-system or 
executive switches to a virtual-8086-mode task, the proc essor emulates an Intel 8086 processor. The execution 
environment of the processor while in the 8086-emulation st ate is the same as is described in Section 21.1, “Real-
Address Mode,” for real-address mode, including the exte nsions. The major difference between the two modes is 
that in virtual-8086 mode the 8086 emulator uses some protected-mode services (such as the protected-mode 
interrupt and exception-handling and paging facilities).Figure 21-2.  Interrupt Vector Table in Real-Address Mode024812
0 15Segment Selector
Offset
* Interrupt vector number 0 selects entry 0Interrupt Vector 0*Entry 1Entry 2Entry 3Up to Entry 255
IDTR(called “interrupt vector 0”) in the interrupt
vector table. Interrupt vector 0 in turnpoints to the start of the interrupt handlerfor interrupt 0.21-6 Vol. 3B8086 EMULATION
As in real-address mode, any new or legacy program that has been assembled and/or compiled to run on an Intel 
8086 processor will run in a virtual-8086-mode task. And several 8086 programs can be run as virtual-8086-mode tasks concurrently with normal protected-mode tasks, using the processor’s multitasking facilities.
21.2.1 Enabling Virtual-8086 Mode
The processor runs in virtual-8086 mode when the VM (virtual machine) flag in the EFLAGS register is set. This flag 
can only be set when the processor switches to a new protected-mode task or resumes virtual-8086 mode via an 
System software cannot change the state of the VM flag dire ctly in the EFLAGS register (for example, by using the 
POPFD instruction). Instead it changes the flag in the imag e of the EFLAGS register stored in the TSS or on the 
stack following a call to an interrupt- or exception-handler procedure. For example, software sets the VM flag in the EFLAGS image in the TSS when first creating a virtual-8086 task.
The processor tests the VM flag under three general conditions:
•When loading segment registers, to determine whether to use 8086-style address translation.
•When decoding instructions, to determine which instruct ions are not supported in virtual-8086 mode and which 
instructions are sensitive to IOPL.Table 21-1.  Real-Address Mode Exceptions and Interrupts
Vector 
No.Description Real-Address Mode Virtual-8086 Mode Intel 8086 Processor
 0 Divide Error (#DE) Yes Yes Yes
 1D e b u g  E x c e p t i o n  ( # D B ) Y e s Y e s N o 2 NMI Interrupt Yes Yes Yes
 3B r e a k p o i n t  ( # B P ) Y e s Y e s Y e s
 4 Overflow (#OF) Yes Yes Yes 5 BOUND Range Exceeded (#BR) Yes Yes Reserved
 6 Invalid Opcode (#UD) Yes Yes Reserved
 7 Device Not Available (#NM) Yes Yes Reserved 8 Double Fault (#DF) Yes Yes Reserved 9 (Intel reserved. Do not use.) Reserved Reserved Reserved
10 Invalid TSS (#TS) Reserved Yes Reserved
11 Segment Not Present (#NP) Reserved Yes Reserved12 Stack Fault (#SS) Yes Yes Reserved
13 General Protection (#GP)* Yes Yes Reserved
14 Page Fault (#PF) Reserved Yes Reserved15 (Intel reserved. Do not use.) Reserved Reserved Reserved
16 Floating-Point Error (#MF) Yes Yes Reserved
17 Alignment Check (#AC) Reserved Yes Reserved18 Machine Check (#MC) Yes Yes Reserved
19-31 (Intel reserved. Do not use.) Reserved Reserved Reserved
32-255 User Defined Interrupts Yes Yes YesNOTE:
* In the real-address mode, vector 13 is the segment overrun exce ption. In protected and virtual-8086 modes, this exception cov -
ers all general-protection error cond itions, including traps to the virtua l-8086 monitor from virtual-8086 mode.Vol. 3B 21-78086 EMULATION
•When checking privileged instructions, on page acce sses, or when performing other permission checks. 
(Virtual-8086 mode always executes at CPL 3.)
21.2.2 Structure of a Virtual-8086 Task
A virtual-8086-mode task consists of the following items:
•A 32-bit TSS for the task.
•The 8086 program.
•A virtual-8086 monitor.
•8086 operating-system services.
The TSS of the new task must be a 32-bit TSS, not a 16-b it TSS, because the 16-bit TSS does not load the most-
significant word of the EFLAGS register, which contains the VM flag. All TSS’s, stacks, data, and code used to handle 
exceptions when in virtual-8086 mode must also be 32-bit segments.
The processor enters virtual-8086 mode to run the 8086 pr ogram and returns to protected mode to run the virtual-
8086 monitor.
The virtual-8086 monitor is a 32-bit protected-mode code mo dule that runs at a CPL of 0. The monitor consists of 
initialization, interrupt- and exception-handling, and I/O emulation procedures that emulate a personal computer 
or other 8086-based platform. Typically, the monitor is either  part of or closely associated with the protected-mode 
general-protection (#GP) exception handler, which also ru ns at a CPL of 0. As with any protected-mode code 
module, code-segment descriptors for the virtual-8086 moni tor must exist in the GDT or in the task’s LDT. The 
virtual-8086 monitor also may need data-segment descriptors  so it can examine the IDT or other parts of the 8086

virtual-8086 monitor also may need data-segment descriptors  so it can examine the IDT or other parts of the 8086 
program in the first 1 MByte of the address space. Th e linear addresses above 10FFEFH are available for the 
monitor, the operating system, and other system software.
The 8086 operating-system services consists of a kern el and/or operating-system procedures that the 8086 
program makes calls to. These services can be im plemented in either of the following two ways:
•They can be included in the 8086 program. This approa ch is desirable for either of the following reasons:
— The 8086 program code modifies the 8086 operating-system services.
— There is not sufficient development time to merge the 8086 operating-system services into main operating 
system or executive.
•They can be implemented or emulated in the virtual-8086  monitor. This approach is desirable for any of the 
— The 8086 operating-system procedures can be more easily coordinated among several virtual-8086 tasks.
— Memory can be saved by not duplicating 8086 operat ing-system procedure code for several virtual-8086 
tasks.
— The 8086 operating-system procedures can be easily emulated by calls to the main operating system or 
executive.
The approach chosen for implementing the 8086 operating- system services may result in different virtual-8086-
mode tasks using different 8086 operating-system services.
21.2.3 Paging of Virtual-8086 Tasks
Even though a program running in virtual-8086 mode can us e only 20-bit linear addresses, the processor converts 
these addresses into 32-bit linear addresses before mapping them to the physical address space. If paging is being 
used, the 8086 address space for a program running in virtual-8086 mode can be paged and located in a set of pages in physical address space. If pa ging is used, it is transparent to th e program running in virtual-8086 mode 
just as it is for any task running on the processor.
Paging is not necessary for a single virtual-8086-mode task, but paging is useful or necessary in the following situ-
ations:21-8 Vol. 3B8086 EMULATION
•When running multiple virtual-8086-mode tasks. Here, pa ging allows the lower 1 MByte of the linear address 
space for each virtual-8086-mode task to be mapped to a different physical address location.
•When emulating the 8086 address-wraparound that occu rs at 1 MByte. When using 8086-style address trans-
lation, it is possible to specify addresses larger than 1 MByte. These addresses automatically wraparound in the 
Intel 8086 processor (see Section 21.1.1, “Address Translation in Real-Address Mode”). If any 8086 programs 
depend on address wraparound, the same effect can be achieved in a virtual-8086-mode task by mapping the 
linear addresses between 100000H and 110000H and lin ear addresses between 0 and 10000H to the same 
physical addresses.
•When sharing the 8086 operating-system services or  ROM code that is common to several 8086 programs 
running as different 8086-mode tasks.
•When redirecting or trapping refere nces to memory-mapped I/O devices.
21.2.4 Protection within a Virtual-8086 Task
Protection is not enforced between the segments of an 8086 program. Either of the following techniques can be 
used to protect the system software running in a virtual-8086-mode task from the 8086 program:
•Reserve the first 1 MByte plus 64 KBytes of each task ’s linear address space for the 8086 program. An 8086 
processor task cannot generate addresses outside this range.
•Use the U/S flag of page-table entries to protect the virtual-8086 monitor and other system software in the 
virtual-8086 mode task space. When the processor is in  virtual-8086 mode, the CPL is 3. Therefore, an 8086 
processor program has only user privileges. If the page s of the virtual-8086 monitor have supervisor privilege, 
they cannot be accessed by the 8086 program.
21.2.5 Entering Virtual-8086 Mode
Figure 21-3 summarizes the methods of entering and le aving virtual-8086 mode. The processor switches to 
virtual-8086 mode in either of the following situations:
•Task switch when the VM flag is set to 1 in the EFLAGS  register image stored in the TSS for the task. Here the 
task switch can be initiated in either of two ways:
— A CALL or JMP instruction.
— An IRET instruction, where the NT flag in the EFLAGS image is set to 1.
•Return from a protected-mode interrupt or exception ha ndler when the VM flag is set to 1 in the EFLAGS 
register image on the stack.
When a task switch is used to enter virtual-8086 mode, the TSS for the virtual-8086-mode task must be a 32-bit 
TSS. (If the new TSS is a 16-bit TSS, the upper word of the EFLAGS register is not in the TSS, causing the processor 
to clear the VM flag when it loads the EFLAGS register.)  The processor updates the VM flag prior to loading the 
segment registers from their images in the new TSS. Th e new setting of the VM flag determines whether the 
processor interprets the contents of  the segment registers as 8086-style segment selectors or protected-mode 
segment selectors. When the VM flag is set, the segmen t registers are loaded from the TSS, using 8086-style 
address translation to form base addresses. 
See Section 21.3, “Interrupt and Exception Handling in Virtual-8086 Mode,” for information on entering virtual-
8086 mode on a return from an interrupt or exception handler.Vol. 3B 21-98086 EMULATION
21.2.6 Leaving Virtual-8086 Mode
The processor can leave the virtual-8086 mode only through an interrupt or exception. The following are situations 
where an interrupt or exception will lead to the processor leaving virtual-8086 mode (see Figure 21-3):
•The processor services a hardware interrupt generated to  signal the suspension of execution of the virtual-
8086 application. This hardware interrupt may be gene rated by a timer or other external mechanism. Upon 
receiving the hardware interrupt, the processor enters protected mode and switches to a protected-mode (or 
another virtual-8086 mode) task either through a task gate in the protected-mode IDT or through a trap or 
interrupt gate that points to a handler that initiates a task switch. A task switch from a virtual-8086 task to 
another task loads the EFLAGS register from the TSS of  the new task. The value of the VM flag in the new 
EFLAGS determines if the new task executes in virtual-8086 mode or not.
•The processor services an exception caused by code executing the virtual-8086 task or services a hardware 
interrupt that “belongs to” the virtual-8086 task. Here, the processor enters protected mode and services the Figure 21-3.  Entering and Leaving Virtual-8086 ModeMonitorVirtual-8086Real Mode
Code
Protected-
Mode Tasks
Mode Tasks
(8086
Programs)Protected-
Mode Interrupt
and Exception
Handlers
Task Switch1
VM = 1Protected
Mode
ModeReal-Address
Mode
RESETPE=1PE=0 or
RESET
#GP Exception3CALL
RETTask Switch
VM=0
Redirect Interrupt to 8086 Program
Interrupt or Exception Handler6IRET4Interrupt or
Exception2VM = 0
NOTES:
- CALL or JMP where the VM flag in the EFLAGS image is 1.
- IRET where VM is 1 and NT is 1.
4. Normal return from protected-mode interrupt or exception handler.3. General-protection exception caused by software interrupt (INT n), IRET,
POPF, PUSHF, IN, or OUT when IOPL is less than 3.2. Hardware interrupt or exception; software interrupt (INT n) when IOPL is 3.
5. A return from the 8086 monitor to redirect an interrupt or exception back
 to an interrupt or exception handler in the 8086 program running in virtual-
6. Internal redirection of a software interrupt (INT  n) when VME is 1,
IOPL is <3, and the redirection bit is 1.IRET5
8086 mode.1. Task switch carried out in either of two ways:21-10 Vol. 3B8086 EMULATION
exception or hardware interrupt through the protected-mo de IDT (normally through an interrupt or trap gate) 
and the protected-mode exception- and interrupt-han dlers. The processor may handle the exception or 
interrupt within the context of the virtual 8086 task an d return to virtual-8086 mode on a return from the 
handler procedure. The processor may also execute a task  switch and handle the exception or interrupt in the 
context of another task.
•The processor services a software interrupt generated by  code executing in the virtual-8086 task (such as a 
software interrupt to call a MS-DOS* operating system  routine). The processor provides several methods of 
handling these software interrupts, which are discussed in detail in Section 21.3.3, “Class 3—Software 
Interrupt Handling in Virtual-8086 Mode.” Most of th em involve the processor entering protected mode, often 
by means of a general-protection (#GP) exception. In protected mode, the processor can send the interrupt to 
the virtual-8086 monitor for handling and/or redirect th e interrupt back to the application program running in 
virtual-8086 mode task for handling.
IA-32 processors that incorporate the virtual mode exte nsion (enabled with the VME flag in control register

IA-32 processors that incorporate the virtual mode exte nsion (enabled with the VME flag in control register 
CR4) are capable of redirecting software-generated inte rrupts back to the program’s interrupt handlers without 
leaving virtual-8086 mode. See Section 21.3.3.4, “Method 5: Software Interrupt Handling,” for more 
information on this mechanism.
•A hardware reset initiated by asserting the RESET or INIT  pin is a special kind of interrupt. When a RESET or 
INIT is signaled while the processor is in virtual-8086 mode, the processor leaves virtual-8086 mode and enters 
real-address mode.
•Execution of the HLT instruction in virtual-8086 mode w ill cause a general-protection (GP#) fault, which the 
protected-mode handler generally sends to the virtual-8086 monitor. The virtual-8086 monitor then 
determines the correct execution sequence after verifyin g that it was entered as a result of a HLT execution.
See Section 21.3, “Interrupt and Exception Handling in Vi rtual-8086 Mode,” for information on leaving virtual-8086 
mode to handle an interrupt or exception generated in virtual-8086 mode.
21.2.7 Sensitive Instructions
When an IA-32 processor is running in virtua l-8086 mode, the CLI, STI, PUSHF, POPF, INT n, and IRET instructions 
are sensitive to IOPL. The IN, INS, OUT, and OUTS instruct ions, which are sensitive to IOPL in protected mode, are 
not sensitive in virtual-8086 mode.
The CPL is always 3 while running in virtual-8086 mode; if th e IOPL is less than 3, an attempt to use the IOPL-sensi-
tive instructions listed above triggers a general-protection exception (#GP). These instructions are sensitive to 
IOPL to give the virtual-8086 monitor a chance to emulate the facilities they affect.
21.2.8 Virtual-8086 Mode I/O
Many 8086 programs written for non-multitasking systems di rectly access I/O ports. This practice may cause prob-
lems in a multitasking environment. If more than one program accesses the same port, they may interfere with 
each other. Most multitasking systems require application programs to access I/O ports through the operating 
system. This results in simplified, centralized control.
The processor provides I/O protection for creating I/O that is compatible with the environment and transparent to 
8086 programs. Designers may take any of several possible approaches to protecting I/O ports:
•Protect the I/O address space and generate exceptions for all attempts to perform I/O directly.
•Let the 8086 program perform I/O directly.
•Generate exceptions on attempts to access specific I/O ports.
•Generate exceptions on attempts to access specific memory-mapped I/O ports.
The method of controlling access to I/O ports depends upon whether they are I/O-port mapped or memory 
mapped.Vol. 3B 21-118086 EMULATION
21.2.8.1  I/O-Port-Mapped I/O
The I/O permission bit map in the TSS can be used to gene rate exceptions on attempts to access specific I/O port 
addresses. The I/O permission bit map of each virtual- 8086-mode task determines which I/O addresses generate 
exceptions for that task. Because each task may have a different I/O permission bit map, the addresses that 
generate exceptions for one task may be different from th e addresses for another task. This differs from protected 
mode in which, if the CPL is less than or equal to the IOPL, I/O access is allowed without checking the I/O permis-
sion bit map. See Chapter 19, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, for more information about the I/O permission bit map.
21.2.8.2  Memory-Mapped I/O
In systems which use memory-mapped I/O, the paging fac ilities of the processor can be used to generate excep-
tions for attempts to access I/O ports. The virtual-8086 monitor may use paging to control memory-mapped I/O in 
these ways:
•Map part of the linear address space of each task th at needs to perform I/O to the physical address space 
where I/O ports are placed. By putting the I/O ports at  different addresses (in different pages), the paging 
mechanism can enforce isolation between tasks.
•Map part of the linear address space to pages that ar e not-present. This generates an exception whenever a 
task attempts to perform I/O to those pages. System  software then can interpret the I/O operation being 
attempted.
Software emulation of the I/O space may require too much  operating system intervention under some conditions. 
In these cases, it may be possible to generate an exception for only the first attempt to access I/O. The system 
software then may determine whether a program can be given exclusive control of I/O temporarily, the protection 
of the I/O space may be lifted, and the program allowed to run at full speed.
21.2.8.3  Special I/O Buffers
Buffers of intelligent controllers (for  example, a bit-mapped frame buffer)  also can be emulated using page 
mapping. The linear space for the buffer can be mapped to  a different physical space for each virtual-8086-mode 
task. The virtual-8086 monitor then can control which virtua l buffer to copy onto the real buffer in the physical 
21.3 INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE
When the processor receives an interrupt or detects an exception condition while in virtual-8086 mode, it invokes 
an interrupt or exception handler, just as it does in protected or real-address mode. The interrupt or exception 
handler that is invoked and the mechanism used to invoke it  depends on the class of interrupt or exception that has 
been detected or generated and the state of various system flags and fields.
In virtual-8086 mode, the interrupts and exceptions are di vided into three classes for the purposes of handling:
•Class 1 — All processor-generated exceptions and all hardwa re interrupts, including the NMI interrupt and the 
hardware interrupts sent to the processor’s external interrupt delivery pins. All class 1 exceptions and interrupts are handled by the protected- mode exception and interrupt handlers.
•Class 2  — Special case for maskable hardware interrupts (Section 6.3.2, “Maskable Hardware Interrupts”) 
when the virtual mode extensions are enabled.
•Class 3 — All software-generated interrupts, that  is interrupts generated with the INT n instruction1.
The method the processor uses to handle class 2 and 3 inte rrupts depends on the setting  of the following flags and 
fields:
•IOPL field (bits 12 and 13 in the EFLAGS register) — Controls how class 3 software interrupts are handled 
when the processor is in virtual-8086 mode (see Section 2.3, “System Flags and Fields in the EFLAGS 
1. The INT 3 instruction is a special ca se (see the description of the INT n instruction in Chapter 3, “Instr uction Set Reference, A-L,” of 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).21-12 Vol. 3B8086 EMULATION
Register”). This field also controls the enabling of th e VIF and VIP flags in the EFLAGS register when the VME 
flag is set. The VIF and VIP flags are provided to assist  in the handling of class 2 maskable hardware interrupts.
•VME flag (bit 0 in control register CR4)  — Enables the virtual mode extension for the processor when set 
(see Section 2.5, “Control Registers”).
•Software interrupt redirection bit map (32 bytes in the TSS, see Figure 21-5) — Contains 256 flags 
that indicates how class 3 software interrupts should be handled when they occur in virtual-8086 mode. A 
software interrupt can be directed either to the interru pt and exception handlers in the currently running 8086 
program or to the protected-mode interrupt and exception handlers.
•The virtual interrupt flag  (VIF) and virtual interr upt pending flag (VIP) in the EFLAGS register — 
Provides virtual interrupt support  for the handling of class 2 maskable hardware interrupts (see Section 
21.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt 
Mechanism”). 
NOTE
The VME flag, software interrupt redirection bit ma p, and VIF and VIP flags are only available in 
IA-32 processors that support the virtual mode ex tensions. These extensions were introduced in 
the IA-32 architecture with the Pentium processor.
The following sections describe the actions that processor takes and the possible actions of interrupt and exception 
handlers for the two classes of interrupts described in  the previous paragraphs. These sections describe three 
possible types of interrupt and exception handlers:
•Protected-mode interrupt and exceptions handlers  — These are the standard handlers that the processor 
calls through the protected-mode IDT.
•Virtual-8086 monitor interr upt and exception handlers — These handlers are resident in the virtual-8086 
monitor, and they are commonly accessed through a gene ral-protection exception (#GP, interrupt 13) that is 
directed to the protected-mode general-protection exception handler.
•8086 program interrupt and exception handlers  — These handlers are part of the 8086 program that is 
running in virtual-8086 mode.
The following sections describe how these handlers are used , depending on the selected class and method of inter-

rupt and exception handling.
21.3.1 Class 1—Hardware Interrupt and Ex ception Handling in Virtual-8086 Mode
In virtual-8086 mode, the Pentium, P6 family, Pentium 4,  and Intel Xeon processors handle hardware interrupts 
and exceptions in the same manner as they are handled by the Intel486 and Intel386 processors. They invoke the 
protected-mode interrupt or exception ha ndler that the interrupt or exception ve ctor points to in the IDT. Here, the 
IDT entry must contain either a 32-bit trap or interrupt gate or a task gate. The following sections describe various 
ways that a virtual-8086 mode interrupt or exception can be handled after the protected-mode handler has been invoked.
See Section 21.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Inter-
rupt Mechanism,” for a description of the virtual interrupt mechanism that is available for handling maskable hard-
ware interrupts while in virtual-8086 mode. When this mech anism is either not available or not enabled, maskable 
hardware interrupts are handled in the same manner as exceptions, as described in the following sections.
21.3.1.1  Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate
When an interrupt or exception vector points to a 32-bit trap or interrupt gate in the IDT, the gate must in turn point 
to a nonconforming, privilege-level 0,  code segment. When accessing this code segment, processor performs the 
following steps.
1. Switches to 32-bit protected mode and privilege level 0.
2. Saves the state of the processor on the privilege-level 0 stack. The states of the EIP, CS, EFLAGS, ESP, SS, ES, 
DS, FS, and GS registers are saved (see Figure 21-4).Vol. 3B 21-138086 EMULATION
3. Clears the segment registers. Saving the DS, ES, FS, and GS registers on the stack and then clearing the 
registers lets the interrupt or exception handler safely save and restore these registers regardless of the type 
segment selectors they contain (protected-mode or 8 086-style). The interrupt and exception handlers, which 
may be called in the context of either a protected-mo de task or a virtual-8086-mode task, can use the same 
code sequences for saving and restoring the registers for any task. Clearing these registers before execution of the IRET instruction does not cause a trap in the interrupt  handler. Interrupt procedures that expect values in 
the segment registers or that return values in the segment registers must use the register images saved on the 
stack for privilege level 0.
4. Clears VM, NT, RF, and TF flags (in the EFLAGS register).  If the gate is an interrupt gate, clears the IF flag.
5. Begins executing the selected interrupt or exception handler.
If the trap or interrupt gate references a procedure in a conforming segment or in a segment at a privilege level 
other than 0, the processor generates a general-protection  exception (#GP). Here, the error code is the segment 
selector of the code segment to which a call was attempted.
Interrupt and exception handlers can examine the VM flag on the stack to determine if the interrupted procedure 
was running in virtual-8086 mode. If so, the interrupt or exception can be handled in one of three ways:
•The protected-mode interrupt or exception handler th at was called can handle the interrupt or exception.
•The protected-mode interrupt or exception handler can call  the virtual-8086 monitor to handle the interrupt or 
•The virtual-8086 monitor (if called) can in turn pass cont rol back to the 8086 program’s interrupt and exception 
handler.
If the interrupt or exception is handled with a protected-mode handler, the handler can return to the interrupted 
program in virtual-8086 mode by executing an IRET inst ruction. This instruction loads the EFLAGS and segment 
registers from the images saved in the privilege level 0 stack (see Figure 21-4). A set VM flag in the EFLAGS image 
causes the processor to switch back to virtual-8086 mode . The CPL at the time the IRET instruction is executed 
must be 0, otherwise the processor does  not change the state of the VM flag.
The virtual-8086 monitor runs at privilege level 0, like th e protected-mode interrupt and exception handlers. It is 
commonly closely tied to the protected-mode general-pr otection exception (#GP, vector 13) handler. If the Figure 21-4.  Privilege Level 0 Stack After Interrupt or Exception in Virtual-8086 ModeUnused
Old GS
Old ESPWith Error Code
ESP from
Old FS
Old DS
Old ES
Old SS
Old EFLAGS
Old CS
Old EIP
Error Code New ESPTSSUnused
Old GS
Old ESPWithout Error Code
ESP from
Old FS
Old DS
Old ES
Old SS
Old EFLAGS
Old CS
Old EIP New ESPTSS21-14 Vol. 3B8086 EMULATION
protected-mode interrupt or exception handler calls the vi rtual-8086 monitor to handle the interrupt or exception, 
the return from the virtual-8086 monitor to the interru pted virtual-8086 mode program requires two return 
instructions: a RET instruction to return to the protected-mode handler and an IRET instruction to return to the 
interrupted program.
The virtual-8086 monitor has the option of directing the in terrupt and exception back to an interrupt or exception 
handler that is part of the interrupted 8086 program, as described in Section 21.3.1.2, “Handling an Interrupt or 
Exception With an 8086 Program In terrupt or Exception Handler.”
21.3.1.2  Handling an Interrupt or Exception With  an 8086 Program Interrupt or Exception Handler
Because it was designed to run on an 8086 processor,  an 8086 program running in a virtual-8086-mode task 
contains an 8086-style interrupt vector table, which starts  at linear address 0. If the virtual-8086 monitor correctly 
directs an interrupt or exception vector back to the virt ual-8086-mode task it came from, the handlers in the 8086 
program can handle the interrupt or exception. The virtua l-8086 monitor must carry out the following steps to send 
an interrupt or exception back to the 8086 program:
1. Use the 8086 interrupt vector to locate the appropriat e handler procedure in the 8086 program interrupt table.
2. Store the EFLAGS (low-order 16 bits only), CS and EIP values of the 8086 program on the privilege-level 3 
stack. This is the stack that the virtual-8086-mode task  is using. (The 8086 handler may use or modify this 
information.)
3. Change the return link on the privilege-level 0 stac k to point to the privilege-level 3 handler procedure.
4. Execute an IRET instruction to pass control to the 8086 program handler.
5. When the IRET instruction from the privilege-level 3 ha ndler triggers a general-protection exception (#GP) and 
thus effectively again calls the virtual-8086 monitor, rest ore the return link on the privilege-level 0 stack to 
point to the original, interrupted, privilege-level 3 procedure.
6. Copy the low order 16 bits of the EFLAGS image from the privilege-level 3 stack to the privilege-level 0 stack 
(because some 8086 handlers modify these flags to return  information to the code that caused the interrupt). 
7. Execute an IRET instruction to pass control back to the interrupted 8086 program.
Note that if an operating system intends to support a ll 8086 MS-DOS-based programs, it is necessary to use the 
actual 8086 interrupt and exception handlers supplied with th e program. The reason for this is that some programs 
modify their own interrupt vector table to substitute (or hook in series) their own specialized interrupt and excep-
tion handlers.
21.3.1.3  Handling an Interrupt or Exception Through a Task Gate
When an interrupt or exception vector points to a task gate  in the IDT, the processor performs a task switch to the 
selected interrupt- or exception-handling task. The following  actions are carried out as part of this task switch:
1. The EFLAGS register with the VM fl ag set is saved in the current TSS.
2. The link field in the TSS of the called task is loaded with the segment selector of the TSS for the interrupted 
virtual-8086-mode task.
3. The EFLAGS register is loaded from the image in th e new TSS, which clears the VM flag and causes the 
processor to switch to protected mode.
4. The NT flag in the EFLAGS register is set.5. The processor begins executing the selected interrupt- or exception-handler task.
When an IRET instruction is executed in the handler task and the NT flag in the EFLAGS register is set, the proces-
sors switches from a protected-mode interrupt- or except ion-handler task back to a virtual-8086-mode task. Here, 
the EFLAGS and segment registers are loaded from images saved in the TSS for the virtual-8086-mode task. If the 
VM flag is set in the EFLAGS image, the processor switch es back to virtual-8086 mode on the task switch. The CPL 
at the time the IRET instruction is executed must be 0,  otherwise the processor does not change the state of the 
VM flag. Vol. 3B 21-158086 EMULATION
21.3.2 Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the 
Virtual Interrupt Mechanism

Maskable hardware interrupts are those interrupts that ar e delivered through the INTR# pin or through an inter-
rupt request to the local APIC (see Section 6.3.2, “Mas kable Hardware Interrupts”). These interrupts can be inhib-
ited (masked) from interrupting an ex ecuting program or task by clearing the IF flag in the EFLAGS register.
When the VME flag in control register CR4 is set and the IO PL field in the EFLAGS register is less than 3, two addi-
tional flags are activated in the EFLAGS register:
•VIF (virtual interrupt) flag, bit 19 of the EFLAGS register.
•VIP (virtual interrupt pending) flag, bit 20 of the EFLAGS register.
These flags provide the virtual-8086 monitor with more efficient control over handling maskable hardware inter-
rupts that occur during virtual-8086 mode tasks. They al so reduce interrupt-handling overhead, by eliminating the 
need for all IF related operations (such as PUSHF, POPF , CLI, and STI instructions) to trap to the virtual-8086 
monitor. The purpose and use of  these flags are as follows.
NOTE
The VIF and VIP flags are only available in IA -32 processors that support the virtual mode 
extensions. These extensions were introduced in the IA-32 architecture with the Pentium 
processor. When this mechanism is either not available or not enabled, maskable hardware 
interrupts are handled as class 1 interrupts. Here, if VIF and VIP flags are needed, the virtual-8086 
monitor can implement them in software.
Existing 8086 programs commonly set and clear the IF flag in the EFLAGS register to enable and disable maskable 
hardware interrupts, respectively; for example, to disabl e interrupts while handling another interrupt or an excep-
tion. This practice works well in single task environmen ts, but can cause problems in multitasking and multiple-
processor environments, where it is often desirable to pr event an application program from having direct control 
over the handling of hardware interrupts. When using ear lier IA-32 processors, this problem was often solved by 
creating a virtual IF flag in software. The IA-32 processo rs (beginning with the Pentium processor) provide hard-
ware support for this virtual IF flag through the VIF and VIP flags.
The VIF flag is a virtualized version of the IF flag, whic h an application program running from within a virtual-8086 
task can used to control the handling of maskable hardware  interrupts. When the VIF fl ag is enabled, the CLI and 
STI instructions operate on the VIF flag instead of the IF  flag. When an 8086 program executes the CLI instruction, 
the processor clears the VIF flag to request that the virtual-8086 monitor inhibit maskable hardware interrupts from interrupting program execution; when it executes the STI instruction, the processor sets the VIF flag 
requesting that the virtual-8086 monitor enable maskable  hardware interrupts for the 8086 program. But actually 
the IF flag, managed by the operating system, always cont rols whether maskable hardware interrupts are enabled. 
Also, if under these circumstances an 8086 program tries to  read or change the IF flag using the PUSHF or POPF 
instructions, the processor will change the VIF flag instead, leaving IF unchanged.
The VIP flag provides software a means of recording the existence of a deferred (or pe nding) maskable hardware 
interrupt. This flag is read by the proc essor but never explicitly written by the processor; it can only be written by 
software. 
If the IF flag is set and the VIF and VIP flags are enable d, and the processor receives a maskable hardware inter-
rupt (interrupt vector 0 through 255), the processor perf orms and the interrupt handler software should perform 
the following operations:
1. The processor invokes the protected-mode interrupt ha ndler for the interrupt received, as described in the 
following steps. These steps are almost identical to those described for method 1 interrupt and exception 
handling in Section 21.3.1.1, “Handlin g an Interrupt or Exception Through a Protected-Mode Trap or Interrupt 
Gate”:
a. Switches to 32-bit protected mode and privilege level 0.
b. Saves the state of the processor on the privilege-level 0 stack. The states of the EIP, CS, EFLAGS, ESP, SS, 
ES, DS, FS, and GS registers are saved (see Figure 21-4).
c. Clears the segment registers.21-16 Vol. 3B8086 EMULATION
d. Clears the VM flag in the EFLAGS register.
e. Begins executing the selected protected-mode interrupt handler.
2. The recommended action of the protected-mode interrupt  handler is to read the VM flag from the EFLAGS 
image on the stack. If this flag is set, the handler makes a call to the virtual-8086 monitor.
3. The virtual-8086 monitor should read the VIF flag in the EFLAGS register. 
— If the VIF flag is clear, the virtual-8086 monitor sets  the VIP flag in the EFLAGS image on the stack to 
indicate that there is a deferred interrupt pend ing and returns to the protected-mode handler.
— If the VIF flag is set, the virtual-8086 monitor can ha ndle the interrupt if it “belongs” to the 8086 program 
running in the interrupted virtual-8086 task; otherwise, it can call the protected-mode interrupt handler to handle the interrupt.
4. The protected-mode handler executes a return to the program executing in virtual-8086 mode.5. Upon returning to virtual-8086 mode, the processor continues execution of the 8086 program.
When the 8086 program is ready to receive maskable hardware  interrupts, it executes the STI instruction to set the 
VIF flag (enabling maskable hardware interrupts). Prior to  setting the VIF flag, the processor automatically checks 
the VIP flag and does one of the followi ng, depending on the state of the flag:
•If the VIP flag is clear (indicating no pendin g interrupts), the processor sets the VIF flag. 
•If the VIP flag is set (indicating a pending interrupt),  the processor generates a general-protection exception 
(#GP).
The recommended action of the protected-mode general-pr otection exception handler is to then call the virtual-
8086 monitor and let it handle the pending interrupt. Afte r handling the pending interrupt, the typical action of the 
virtual-8086 monitor is to clear the VIP flag and set the VIF flag in the EFLAGS image on the stack, and then execute a return to the virtual-8086 mode. The next time the processor receives a maskable hardware interrupt, it 
will then handle it as described in steps 1 through 5 earlier in this section.
If the processor finds that both the VIF and VIP flags are set at the beginning of an instruction, it generates a 
general-protection exception. This action allows the vi rtual-8086 monitor to handle the pending interrupt for the 
virtual-8086 mode task for which the VIF flag is enabled.  Note that this situation can only occur immediately 
following execution of a POPF or IRET instruction or upon  entering a virtual-8086 mode task through a task switch.
Note that the states of the VIF and VIP flags are not modi fied in real-address mode or during transitions between 
real-address and protected modes.
NOTE
The virtual interrupt mechanism described in this section is also available for use in protected mode, see Section 21.4, “Protected-Mode Virtual Interrupts.”
21.3.3 Class 3—Software Interrupt  Handling in Virtual-8086 Mode
When the processor receives a software inte rrupt (an interrupt generated with the INT n instruction) while in 
virtual-8086 mode, it can use any of six different method s to handle the interrupt. The method selected depends 
on the settings of the VME flag in control register CR4, th e IOPL field in the EFLAGS register, and the software inter-
rupt redirection bit map in the TSS. Table 21-2 lists the six methods of handling software interrupts in virtual-8086 
mode and the respective settings of the VME flag, IOPL fiel d, and the bits in the interrupt redirection bit map for 
each method. The table also summarizes the variou s actions the processor takes for each method. 
The VME flag enables the virtual mode extensions for the Pentium and later IA-32 processors. When this flag is 
clear, the processor responds to interrupts and exceptions in virtual-8086 mode in the same manner as an Intel386 
or Intel486 processor does. When this flag is set, the virtual mode extension provides the following enhancements 
to virtual-8086 mode:
•Speeds up the handling of software-generated interrupt s in virtual-8086 mode by allowing the processor to 
bypass the virtual-8086 monitor and redirect software interru pts back to the interrupt handlers that are part of 
the currently running 8086 program.
•Supports virtual interrupts for software written to run on the 8086 processor.Vol. 3B 21-178086 EMULATION
The IOPL value interacts with the VME flag and the bits  in the interrupt redirection bit map to determine how 
specific software interrupts should be handled.
The software interrupt redirection bit map (see Figure 21-5 ) is a 32-byte field in the TSS. This map is located

The software interrupt redirection bit map (see Figure 21-5 ) is a 32-byte field in the TSS. This map is located 
directly below the I/O permission bit map in the TSS. Each bit in the interrupt redirection bit map is mapped to an interrupt vector. Bit 0 in the interrupt redirection bit map (which maps to vector zero in the interrupt table) is 
located at the I/O base map address in the TSS minus 32 bytes.  When a bit in this bit map is set, it indicates that 
the associated software interrupt (interrupt generated with an INT n instruction) should be handled through the 
protected-mode IDT and interrupt and exception handlers. Wh en a bit in this bit map is clear, the processor redi-
rects the associated software interrupt back to the interrupt table in the 8086 program (located at linear address 0 
in the program’s address space). 
NOTE
The software interrupt redirection bit map does  not affect hardware generated interrupts and 
exceptions. Hardware generated interrupts and ex ceptions are always handled by the protected-
mode interrupt and exception handlers.
Table 21-2.  Software Interrupt Handling Methods While in Virtual-8086 Mode
Method VME IOPLBit in 
Redir. 
Bitmap* Processor Action
1 0 3 X Interrupt directed to a pr otected-mode in terrupt handler:
• Switches to privilege-level 0 stack.
• Pushes GS, FS, DS, and ES onto privilege-level 0 stack.
• Pushes SS, ESP, EFLAGS, CS, and EIP of interrupted task onto privilege-level 0 stack.• Clears VM, RF, NT, and TF flags.
• If serviced through interrupt gate, clears IF flag.
• Clears GS, FS, DS, and ES to 0.• Sets CS and EIP fr om interrupt gate.
2 0  < 3 X Interrupt directed to protected-mode  general-protection exception (#GP) handler.
3 1 < 3 1 Interrupt directed to a protected-mode genera l-protection exception (#GP) handler; VIF and VIP 
flag support for handling class 2 maskable hardware interrupts.
4 1 3 1 Interrupt directed to protec ted-mode interrupt handler: (s ee method 1 processor action).
5 1 3 0 Interrupt redirected to 8086 program interrupt handler:
• Pushes EFLAGS. 
• Pushes CS and EIP (lower 16 bits only).• Clears IF flag.
•C l e a r s  T F  f l a g .
• Loads CS and EIP (lower 16 bits only) from sele cted entry in the interrupt vector table of the 
current virtual-8086 task.
6 1 < 3 0 Interrupt redirected to 8086 program interrupt handler; VIF and VIP flag support for handling class 
2 maskable hardware interrupts:
• Pushes EFLAGS with IOPL set to 3 and VIF copied to IF.
• Pushes CS and EIP (lower 16 bits only).•C l e a r s  t h e  V I F  f l a g .
NOTE:
* When set to 0, software interrup t is redirected back to the 8086 program interrup t handler; when set to 1, interrupt is direct ed to 
protected-mode handler.21-18 Vol. 3B8086 EMULATION
Redirecting software interrupts back to the 8086 program potentially speeds up interrupt handling because a 
switch back and forth between virtual-8086 mode and pr otected mode is not required. This latter interrupt-
handling technique is particularly useful for 8086 operating systems (such as MS-DOS) that use the INT n instruc-
tion to call operating system procedures.
The CPUID instruction can be used to verify that the virt ual mode extension is implemented on the processor. Bit 1 
of the feature flags register (EDX) indicates the availab ility of the virtual mode exte nsion (see “CPUID—CPU Iden-
tification” in Chapter 3, “Instruction  Set Reference, A-L,” of the Intel® 64 and IA-32 Architectures Software Devel-
The following sections describe the six methods (or mechan isms) for handling software interrupts in virtual-8086 
mode. See Section 21.3.2, “Class 2—Maskable Hardware Inte rrupt Handling in Virtual-8086 Mode Using the Virtual 
Interrupt Mechanism,” for a description of the use of th e VIF and VIP flags in the EFLAGS register for handling 
21.3.3.1  Method 1: Software Interrupt Handling
When the VME flag in control register CR4 is clear and the IOPL field is 3, a Pentium or later IA-32 processor 
handles software interrupts in the same manner as they are handled by an Intel386 or Intel486 processor. It 
executes an implicit call to the interrupt handler in the protected-mode IDT pointed to by the interrupt vector. See 
Section 21.3.1, “Class 1—Hardware Interrupt and Except ion Handling in Virtual-8086 Mode,” for a complete 
description of this mechanism and its possible uses.
21.3.3.2  Methods 2 and 3: Software Interrupt Handling
When a software interrupt occurs in virtual-8086 mode and the method 2 or 3 conditions are present, the processor 
generates a general-protection exception (#GP). Method 2 is enabled when the VME flag is set to 0 and the IOPL 
value is less than 3. Here the IOPL value is used to bypass the protected-mode interrupt handlers and cause any 
software interrupt that occurs in virtual-8086 mode to be treated as a protected-mode general-protection excep-
tion (#GP). The general-protection exception handler ca lls the virtual-8086 monitor, which can then emulate an 
8086-program interrupt handler or pass control back to the 8086 program’s handler, as described in Section 21.3.1.2, “Handling an Interrupt or Exception With  an 8086 Program Interrupt or Exception Handler.”
Method 3 is enabled when the VME flag is set to 1, the IO PL value is less than 3, and the corresponding bit for the 
software interrupt in the software interrupt redirection bi t map is set to 1. Here, the processor performs the same Figure 21-5.  Software Interrupt Redirection Bit Map in TSSI/O Map BaseTask-State Segment (TSS)
64H31 24 23 0
1 1111111
0I/O map 
base must 
not exceed 
DFFFH.Last byte of 
bit
map must be
Software Interrupt Redirection Bit Map (32 Bytes)Vol. 3B 21-198086 EMULATION
operation as it does for method 2 software interrupt handli ng. If the corresponding bit fo r the software interrupt in 
the software interrupt redirection bit map is set to 0, the interrupt is handled using meth od 6 (see Section 21.3.3.5, 
“Method 6: Software Interrupt Handling”).
21.3.3.3  Method 4: Software Interrupt Handling
Method 4 handling is enabled when the VME flag is set to 1,  the IOPL value is 3, and the bit for the interrupt vector 
in the redirection bit map is set to 1. Method 4 software interrupt handling allows method 1 style handling when the 
virtual mode extension is enabled; that is, the interrupt is directed to a protected-mode handler (see Section 
21.3.3.1, “Method 1: Software Interrupt Handling”).
21.3.3.4  Method 5: Software Interrupt Handling
Method 5 software interrupt handling provides a streamli ned method of redirecting software interrupts (invoked 
with the INT n instruction) that occur in virtual 8086 mode back  to the 8086 program’s interrupt vector table and 
its interrupt handlers. Method 5 handling is enabled when the VME flag is set to 1, the IOPL value is 3, and the bit 
for the interrupt vector in the redirection bit map is set to  0. The processor performs the following actions to make 
an implicit call to the selected 8086 program interrupt handler:
1. Pushes the low-order 16 bits of the EFLAGS register onto the stack.
2. Pushes the current values of the CS and EIP registers on to the current stack. (Only the 16 least-significant bits 
of the EIP register are pushed  and no stack switch occurs.)
3. Clears the IF flag in the EFLAGS register to disable interrupts.4. Clears the TF flag, in the EFLAGS register.
5. Locates the 8086 program interrupt vector table at linear address 0 for the 8086-mode task.
6. Loads the CS and EIP registers with values from the in terrupt vector table entry pointed to by the interrupt 
vector number. Only the 16 low-order bits of the EIP ar e loaded and the 16 high-order bits are set to 0. The 
interrupt vector table is assumed to be at lin ear address 0 of the current virtual-8086 task.
7. Begins executing the selected interrupt handler.
rupted 8086 program.
Note that with method 5 handling, a mode switch from virtual-8086 mode to protected mode does not occur. The 
processor remains in virtual-8086 mode thro ughout the interrupt-handling operation.
The method 5 handling actions are virtually identical to  the actions the processor takes when handling software 
interrupts in real-address mode. The benefit of using meth od 5 handling to access the 8086 program handlers is 
that it avoids the overhead of methods 2 and 3 handling , which requires first going to the virtual-8086 monitor, 
then to the 8086 program handler, then back again to th e virtual-8086 monitor, before returning to the interrupted 
8086 program (see Section 21.3.1.2, “Handling an Interru pt or Exception With an 8086 Program Interrupt or 
Exception Handler”). 
NOTE
Methods 1 and 4 handling can handle a software in terrupt in a virtual-8086 task with a regular 
protected-mode handler, but this approach requires all virtual-8086 tasks to use the same software

NOTE
protected-mode handler, but this approach requires all virtual-8086 tasks to use the same software 
interrupt handlers, which generally does not give sufficient latitude to the programs running in the virtual-8086 tasks, particularly MS-DOS programs.
21.3.3.5  Method 6: Software Interrupt Handling
Method 6 handling is enabled when the VME flag is set to 1,  the IOPL value is less than 3, and the bit for the inter-
rupt or exception vector in the redirection bit map is set to 0. With method 6 interrupt handling, software interrupts 
are handled in the same manner as was described for method 5 handling (see Section 21.3.3.4, “Method 5: Soft-
ware Interrupt Handling”).21-20 Vol. 3B8086 EMULATION
Method 6 differs from method 5 in that with the IOPL valu e set to less than 3, the VIF and VIP flags in the EFLAGS 
register are enabled, providing virtual interrupt suppor t for handling class 2 maskable hardware interrupts (see 
Section 21.3.2, “Class 2—Maskable Hardware Interrupt Ha ndling in Virtual-8086 Mode Using the Virtual Interrupt 
Mechanism”). These flags provide the virtual-8086 monitor with an efficient means of handling maskable hardware 
interrupts that occur during a virtual-8086 mode task. Also, because the IOPL value is less than 3 and the VIF flag is enabled, the information pushed on the stack by the processor when invoki ng the interrupt handler is slightly 
different between methods 5 and 6 (see Table 21-2).
21.4 PROTECTED-MODE VIRTUAL INTERRUPTS
The IA-32 processors (beginning with the Pentium proce ssor) also support the VIF an d VIP flags in the EFLAGS 
register in protected mode by setting the PVI (protected-mod e virtual interrupt) flag in the CR4 register. Setting the 
PVI flag allows applications running at privilege level 3 to execute the CLI and STI instructions without causing a general-protection exception (#GP) or affecting hardware interrupts. 
When the PVI flag is set to 1, the CPL is 3, and the IOPL  is less than 3, the STI and CLI instructions set and clear 
the VIF flag in the EFLAGS register, leaving IF unaffected.  In this mode of operation, an application running in 
protected mode and at a CPL of 3 can inhibit interrupts in the same manner as is described in Section 21.3.2, “Class 
2—Maskable Hardware Interrupt Handling in Virtual-8086  Mode Using the Virtual Interrupt Mechanism,” for a 
virtual-8086 mode task. When the application executes the CL I instruction, the processor clears the VIF flag. If the 
processor receives a maskable hardware interrupt, the pr ocessor invokes the protected-mode interrupt handler. 
This handler checks the state of the VIF flag in the EFLAGS re gister. If the VIF flag is clear (indicating that the active 
task does not want to have interrupts handled now), the ha ndler sets the VIP flag in the EFLAGS image on the stack 
and returns to the privilege-level 3 application, which co ntinues program execution. When the application executes 
a STI instruction to set the VIF flag, the processor automatically invokes the general-protection exception handler, 
which can then handle the pending interrupt. After handing the pending interrupt, the handler typically sets the VIF 
flag and clears the VIP flag in the EFLAGS image on the st ack and executes a return to the application program. The 
next time the processor receives a maskable hardware inte rrupt, the processor will handle it in the normal manner 
for interrupts received while the proc essor is operating at a CPL of 3.
If the protected-mode virtual interrupt extension is enable d, CPL = 3, and the processor finds that both the VIF and 
VIP flags are set at the beginning of an instruction, a general-protection exception is generated.
Because the protected-mode virtual interrupt extension ch anges only the treatment of EFLAGS.IF (by having CLI 
and STI update EFLAGS.VIF instead), it affects only th e masking of maskable hardware interrupts (interrupt 
vectors 32 through 255). NMI interrupts and ex ceptions are handled in the normal manner.
(When protected-mode virtual interrupts are disabled (that is, when the PVI flag in control register CR4 is set to 0, 
the CPL is less than 3, or the IOPL value is 3), then the CLI and STI instructions execute in a manner compatible with the Intel486 processor. That is, if the CPL is greater (less privileged) than the I/O privilege level (IOPL), a 
general-protection exception occurs. If the IOPL value is  3, CLI and STI clear or set the IF flag, respectively.)
PUSHF, POPF, IRET, and INT are executed like in the Inte l486 processor, regardless of whether protected-mode 
virtual interrupts are enabled.
It is only possible to enter virtual-8086 mode through a task  switch or the execution of an IRET instruction, and it 
is only possible to leave virtual-8086 mode by faulting to  a protected-mode interrupt ha ndler (typically the general-
protection exception handler, which in turn calls the virtual 8086-mode monitor). In both cases, the EFLAGS 
register is saved and restored. This is not true, howeve r, in protected mode when the PVI flag is set and the 
processor is not in virtual-8086 mode. Here, it is possible to call a procedure at a different privilege level, in which 
case the EFLAGS register is not saved or modified. Howeve r, the states of VIF and VIP flags are never examined by 
the processor when the CPL is not 3.Vol. 3B 22-1CHAPTER 22
Program modules written to run on IA-32 processors can be either 16-bit modules or 32-bit modules. Table 22-1 
shows the characteristic of 16-bit and 32-bit modules.
The IA-32 processors function most efficiently when exec uting 32-bit program modules. They can, however, also 
execute 16-bit program modules, in any of the following ways:
•In real-address mode.
•In virtual-8086 mode.
•System management mode (SMM).
•As a protected-mode task, when the code, data, and stack segments for the task are all configured as a 16-bit 
segments.
•By integrating 16-bit and 32-bit segmen ts into a single protected-mode task.
•By integrating 16-bit operations into 32-bit code segments.
Real-address mode, virtual-8086 mode, and SMM are native 16-bit modes. A legacy program assembled and/or 
compiled to run on an Intel 8086 or Intel 286 processor should run in real-address mode or virtual-8086 mode 
without modification. Sixteen-bit program modules can also  be written to run in real-address mode for handling 
system initialization or to run in SMM for handling sy stem management functions. See Chapter 21, “8086 Emula-
tion,” for detailed information on real-address mode and virtual-8086 mode; see Chapter 32, “System Manage-
ment Mode,” for information on SMM.
This chapter describes how to integrate 16-bit program modules with 32-bit program modules when operating in 
protected mode and how to mix 16-bit and 32-bit code within 32-bit code segments.
22.1 DEFINING 16-BIT AN D 32-BIT PROGRAM MODULES
The following IA-32 architecture mechanisms are used to distinguish between and support 16-bit and 32-bit 
segments and operations:
•The D (default operand and address size) flag in code-segment descriptors.
•The B (default stack size) flag in stack-segment descriptors.
•16-bit and 32-bit call gates, interrupt gates, and trap gates.
•Operand-size and address-size instruction prefixes.
•16-bit and 32-bit general-purpose registers.
The D flag in a code-segment descriptor determines the default operand-size and address-size for the instructions 
of a code segment. (In real-address mode and virtual-8086 mode, which do not use segment descriptors, the 
default is 16 bits.) A code segment with its D flag set is a 32-bit segment; a code segment with its D flag clear is a 
16-bit segment.Table 22-1.  Characteristics of 16-Bit and 32-Bit Program Modules
Characteristic 16-Bit Program Mo dules 32-Bit Program Modules
Segment Size 0 to 64 KBytes 0 to 4 GBytes
Operand Sizes 8 bits and 16 bits 8 bits and 32 bitsPointer Offset Size (Address Size) 16 bits 32 bits
Stack Pointer Size 16 Bits 32 Bits
Control Transfers Allowe d to Code Segments 
of This Size16 Bits 32 Bits22-2 Vol. 3BMIXING 16-BIT AND 32-BIT CODE
The B flag in the stack-segment descriptor specifies the size of stack pointer (the 32-bit ESP register or the 16-bit 
SP register) used by the processor for implicit stack refe rences. The B flag for all data descriptors also controls 
upper address range for expand down segments.
When transferring program control to another code segmen t through a call gate, interrupt gate, or trap gate, the 
operand size used during the transfer is  determined by the type of gate used (16-bit or 32-bit), (not by the D-flag 
or prefix of the transfer instruction). The gate type de termines how return information is saved on the stack (or 
stacks).
For most efficient and trouble-free operation of the proce ssor, 32-bit programs or tasks should have the D flag in 
the code-segment descriptor and the B flag in the stac k-segment descriptor set, and 16-bit programs or tasks

stacks).
the code-segment descriptor and the B flag in the stac k-segment descriptor set, and 16-bit programs or tasks 
should have these flags clear. Program control transfers fr om 16-bit segments to 32-bit segments (and vice versa) 
are handled most efficiently through call, interrupt, or trap gates.
Instruction prefixes can be used to override the default operand size and address size of a code segment. These 
prefixes can be used in real-address mode as well as in protected mode and virtual-8086 mode. An operand-size or 
address-size prefix only changes the size for the duration of the instruction.
22.2 MIXING 16-BIT AND 32-BIT OP ERATIONS WITHIN A CODE SEGMENT
The following two instruction prefixes allow mixing of 32-bit and 16-bit operations within one segment:
•The operand-size prefix (66H)
•The address-size prefix (67H)
These prefixes reverse the default size selected by the D flag in the code-segment descriptor. For example, the 
processor can interpret the (MOV mem, reg) instruction in any of four ways:
•In a 32-bit code segment:
— Moves 32 bits from a 32-bit register to memory using a 32-bit effective address.
— If preceded by an operand-size prefix, moves 16 bits  from a 16-bit register to memory using a 32-bit 
effective address.
— If preceded by an address-size pr efix, moves 32 bits from a 32-bit register to memory using a 16-bit 
— If preceded by both an address-size prefix and an op erand-size prefix, moves 16 bits from a 16-bit register 
to memory using a 16-bit effective address.
•In a 16-bit code segment:
— Moves 16 bits from a 16-bit register to memory using a 16-bit effective address.
— If preceded by an operand-size prefix, moves 32 bits  from a 32-bit register to memory using a 16-bit 
— If preceded by an address-size pr efix, moves 16 bits from a 16-bit register to memory using a 32-bit 
— If preceded by both an address-size prefix and an op erand-size prefix, moves 32 bits from a 32-bit register 
to memory using a 32-bit effective address.
The previous examples show that any instruction can gene rate any combination of operand size and address size 
regardless of whether the instruction is in a 16- or 32-bit segment. The choice of the 16- or 32-bit default for a code 
segment is normally based on the following criteria:
•Performance — Always use 32-bit code segments when possibl e. They run much faster than 16-bit code 
segments on P6 family processors, and somewhat faster on earlier IA-32 processors.
•The operating system the code  segment will be  running on — If the operating system is a 16-bit 
operating system, it may not support 32-bit program modules.
•Mode of operation — If the code segment is being designed to run in real-address mode, virtual-8086 mode, 
or SMM, it must be a 16-bit code segment.Vol. 3B 22-3MIXING 16-BIT AND 32-BIT CODE
•Backward compatibility to  earlier IA-32 processors — If a code segment must be able to run on an Intel 
8086 or Intel 286 processor, it must be a 16-bit code segment.
22.3 SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS
Data segments can be accessed from both 16-bit and 32-bi t code segments. When a data segment that is larger 
than 64 KBytes is to be shared among 16- and 32-bit code  segments, the data that is  to be accessed from the 16-
bit code segments must be located within the first 64 KByt es of the data segment. The reason for this is that 16-
bit pointers by definition can only poin t to the first 64 KBytes of a segment. 
A stack that spans less than 64 KBytes can be shared by bo th 16- and 32-bit code segments. This class of stacks 
includes:
•Stacks in expand-up segments with the G (granularity) and B (big) flags in the stack-segment descriptor clear.
•Stacks in expand-down segments with the G and B flags clear.
•Stacks in expand-up segments with the G flag set and the B flag clear and where the stack is contained 
completely within the lower 64 KBytes. (Offsets greater than FFFFH can be used for data, other than the stack, 
which is not shared.)
See Section 3.4.5, “Segment Descriptors,” for a descripti on of the G and B flags and the expand-down stack type.
The B flag cannot, in general, be used to change the size of  stack used by a 16-bit code segment. This flag controls 
the size of the stack pointer only for implicit stack refere nces such as those caused by interrupts, exceptions, and 
the PUSH, POP, CALL, and RET instructions. It does not control explicit stack references, such as accesses to 
parameters or local variables. A 16-bit code segment can use a 32-bit stack only if the code is modified so that all explicit references to the stack are preceded by the 32-b it address-size prefix, causing those references to use 32-
bit addressing and explicit writes to the stack po inter are preceded by a 32-bit operand-size prefix.
In 32-bit, expand-down segments, all offsets may be grea ter than 64 KBytes; therefore, 16-bit code cannot use 
this kind of stack segment unless the code segment is modified to use 32-bit addressing.
22.4 TRANSFERRING CONTROL AM ONG MIXED-SIZE CODE SEGMENTS
There are three ways for a procedure in a 16-bit code segment to safely make a call to a 32-bit code segment:
•Make the call through a 32-bit call gate.
•Make a 16-bit call to a 32-bit interface procedure. The interface procedure then makes a 32-bit call to the 
intended destination.
•Modify the 16-bit procedure, inserting an operand-size pr efix before the call, to change it to a 32-bit call.
Likewise, there are three ways for procedure in a 32-bit code segment to safely make a call to a 16-bit code 
segment:
•Make the call through a 16-bit call gate. Here, the EIP value at the CALL instruction cannot exceed FFFFH.
•Make a 32-bit call to a 16-bit interface procedure. The interface procedure then makes a 16-bit call to the 
•Modify the 32-bit procedure, inserting an operand-size pr efix before the call, changing it to a 16-bit call. Be 
certain that the return offset does not exceed FFFFH.
These methods of transferring program control overcome the following architectural limitations imposed on calls 
between 16-bit and 32-bit code segments:
•Pointers from 16-bit code segments (which by default can only be 16 bits) cannot be used to address data or 
code located beyond FFFFH in a 32-bit segment.
•The operand-size attributes for a CALL and its companio n RETURN instruction must be the same to maintain 
stack coherency. This is also true for implicit calls to  interrupt and exception handlers and their companion IRET 
•A 32-bit parameters (particularly a pointer parameter)  greater than FFFFH cannot be squeezed into a 16-bit 
parameter location on a stack.22-4 Vol. 3BMIXING 16-BIT AND 32-BIT CODE
•The size of the stack pointer (SP or ESP) changes when switching between 16-bit and 32-bit code segments.
These limitations are discussed in greater detail in the following sections.
22.4.1 Code-Segment Pointer Size
For control-transfer instructions that use a pointer to identify the next instruction (that is, those that do not use 
gates), the operand-size attribute determines the size of th e offset portion of the pointer. The implications of this 
rule are as follows:
•A JMP, CALL, or RET instruction from a 32-bit segment to a 16-bit segment is always possible using a 32-bit 
operand size, providing the 32-bit pointer does not exceed FFFFH.
•A JMP, CALL, or RET instruction from  a 16-bit segment to a 32-bit segment cannot address a destination greater 
than FFFFH, unless the instruction is given an operand-size prefix.
See Section 22.4.5, “Writing Interface Procedures,” for an  interface procedure that can transfer program control 
from 16-bit segments to destinations in 32-bit segments beyond FFFFH.
22.4.2 Stack Management for Control Transfer
Because the stack is managed differently for 16-bit procedur e calls than for 32-bit calls, the operand-size attribute 
of the RET instruction must match that of the CALL inst ruction (see Figure 22-1). On a 16-bit call, the processor 
pushes the contents of the 16-bit IP register and (for calls between privilege levels) the 16-bit SP register. The 
matching RET instruction must also use a 16-bit operand size  to pop these 16-bit values from the stack into the 16-
bit registers. 
A 32-bit CALL instruction pushes the contents of the 32-bit EIP register and (for inter-pr ivilege-level calls) the 32-
bit ESP register. Here, the matching RET instruction must use a 32-bit operand size to pop these 32-bit values from 
the stack into the 32-bit registers. If the two parts of a CALL/RET instruction pair do not have matching operand 
sizes, the stack will not be managed correctly and the valu es of the instruction pointer and stack pointer will not be 
restored to correct values. Vol. 3B 22-5MIXING 16-BIT AND 32-BIT CODE
While executing 32-bit code, if a call is made to a 16-bit code segment which is at the same or a more privileged 
level (that is, the DPL of the called code segment is less than or equal to the CPL of the calling code segment)

level (that is, the DPL of the called code segment is less than or equal to the CPL of the calling code segment) 
through a 16-bit call gate, then the upper 16-bits of th e ESP register may be unreliable upon returning to the 32-
bit code segment (that is, after executin g a RET in the 16-bit code segment).
When the CALL instruction and its matching RET instruction are in code segments that have D flags with the same 
values (that is, both are 32-bit code segments or both  are 16-bit code segments),  the default settings may be 
used. When the CALL instruction and its matching RET instruction are in segments which have different D-flag 
settings, an operand-size prefix must be used.
22.4.2.1  Controlling the Oper and-Size Attribute For a Call
Three things can determine the operand-size of a call:
•The D flag in the segment descrip tor for the calling code segment.
•An operand-size instruction prefix.
•The type of call gate (16-bit or 32-bit), if a call is made through a call gate.
When a call is made with a pointer (rather than a call ga te), the D flag for the calling code segment determines the 
operand-size for the CALL instruction.  This operand-size attribute can be overridden by prepending an operand-
size prefix to the CALL instruction. So, for example, if the D flag for a code segment is set for 16 bits and the 
operand-size prefix is used with a CALL instruction, the processor will cause the information stored on the stack to Figure 22-1.  Stack after Far 16- and 32-Bit CallsSPAfter 16-bit Call
PARM 1
IP SPSS
PARM 2
CS0 31
SS
EIPAfter 32-bit Call
CS
ESPESP
PARM 2
PARM 10 31With Privilege Transition
Stack
GrowthAfter 16-bit Call
PARM 1
IP SPPARM 2
CS0 31Without Privilege Transition
Stack
GrowthAfter 32-bit Call
PARM 1
ESPPARM 2
CS0 31
EIP
Undefined22-6 Vol. 3BMIXING 16-BIT AND 32-BIT CODE
be stored in 32-bit format. If the call is to a 32-bit code segment, the instructions in that code segment will be able 
to read the stack coherently. Also, a RET instruction from the 32-bit code segment without an operand-size prefix 
will maintain stack coherency with the 16 -bit code segment being returned to.
When a CALL instruction referenc es a call-gate descriptor, the type of call is determined by the type of call gate (16-
bit or 32-bit). The offset to the destination in the code segment being called is taken from the gate descriptor; 
therefore, if a 32-bit call gate is used, a procedure in a 16-bit code segment can call a procedure located more than 
64 KBytes from the base of a 32-bit code segment,  because a 32-bit call gate uses a 32-bit offset.
Note that regardless of the operand size of the call and ho w it is determined, the size of the stack pointer used (SP 
or ESP) is always controlled by the B fl ag in the stack-segment descriptor currently in use (that is, when B is clear, 
SP is used, and when B is set, ESP is used).
An unmodified 16-bit code segment that has run successfu lly on an 8086 processor or in real-mode on a later IA-
32 architecture processor will have its D flag clear and will not use operand-size override prefixes. As a result, all 
CALL instructions in this code segment will use the 16-b it operand-size attribute. Procedures in these code 
segments can be modified to safely call procedures  to 32-bit code segments in either of two ways:
•Relink the CALL instruction to point to 32-bit call gates (see Section 22.4.2.2, “Passing Parameters With a 
Gate”).
•Add a 32-bit operand-size pref ix to each CALL instruction.
22.4.2.2  Passing Parameters With a Gate
When referencing 32-bit gates with 16-bit procedures, it is important to consider the number of parameters passed 
in each procedure call. The count field of  the gate descriptor specifies the size of the parameter string to copy from 
the current stack to the stack of a more privileged (numeric ally lower privilege level) pr ocedure. The count field of 
a 16-bit gate specifies the number of 16-bit words to be  copied, whereas the count field of a 32-bit gate specifies 
the number of 32-bit doublewords to be copied. The count fi eld for a 32-bit gate must thus be half the size of the 
number of words being placed on the stack by a 16-bit procedure. Also, the 16-bit procedure must use an even 
number of words as parameters.
22.4.3 Interrupt Control Transfers
A program-control transfer caused by an exception or inte rrupt is always carried out through an interrupt or trap 
gate (located in the IDT). Here, the type of the gate (16- bit or 32-bit) determines the operand-size attribute used 
in the implicit call to the exception or interru pt handler procedure in another code segment.
A 32-bit interrupt or trap gate provides a safe interface to a 32-bit exception or interrupt handler when the excep-
tion or interrupt occurs in either a 32-bit or a 16-bit code segment. It is sometimes impractical, however, to place 
exception or interrupt handlers in 16 -bit code segments, because only 16-bit return addresses are saved on the 
stack. If an exception or interrupt occurs in a 32-bi t code segment when the EIP was greater than FFFFH, the 16-
bit handler procedure cannot provide the correct return address.
22.4.4 Parameter Translation
When segment offsets or pointers (which contain segmen t offsets) are passed as parameters between 16-bit and 
32-bit procedures, some translation is required. If a 32-bi t procedure passes a pointer to data located beyond 64 
KBytes to a 16-bit procedure, the 16-bit procedure cannot use it. Except for this limitation, interface code can 
perform any format conversion between 32-bit  and 16-bit pointers that may be needed.
Parameters passed by value between 32-bit and 16-bit code also may require translation between 32-bit and 16-
bit formats. The form of the translation is application-dependent.
22.4.5 Writing Interface Procedures
Placing interface code between 32-bit and 16-bit procedures  can be the solution to the following interface prob-
lems:Vol. 3B 22-7MIXING 16-BIT AND 32-BIT CODE
•Allowing procedures in 16-bit code segments to call pr ocedures with offsets greater than FFFFH in 32-bit code 
segments.
•Matching operand-size attributes between companion CALL and RET instructions.
•Translating parameters (data), including managing parameter strings with a variable count or an odd number of 16-bit words.
•The possible invalidation of the upper bits of the ESP register.
The interface procedure is simplif ied where these rules are followed.
1. The interface procedure must reside in a 32-bit code segment (the D flag for the code-segment descriptor is 
set).
2. All procedures that may be called by 16-bit procedures must have offsets not greater than FFFFH.
3. All return addresses saved by 16-bit procedures must have offsets not greater than FFFFH.
The interface procedure becomes more complex if any of these rules are violated. For example, if a 16-bit proce-
dure calls a 32-bit procedure with an entry point beyond  FFFFH, the interface procedure will need to provide the 
offset to the entry point. The mapping between 16- and 32 -bit addresses is only performed automatically when a 
call gate is used, because the gate descriptor for a call gate contains a 32-bit address. When a call gate is not used, 
the interface code must provide the 32-bit address.
The structure of the interface procedure depends on th e types of calls it is going to support, as follows:
•Calls from 16-bit procedur es to 32-bit procedures — Calls to the interface procedure from a 16-bit code 
segment are made with 16-bit CALL instructions (by de fault, because the D flag fo r the calling code-segment 
descriptor is clear), and 16-bit operand-size prefixes are used with RET instructions to return from the interface 
procedure to the calling procedure. Calls from the interf ace procedure to 32-bit procedures are performed with 
32-bit CALL instructions (by default, because the D flag for the interface procedure’s code segment is set), and 
returns from the called procedures to the interface proc edure are performed with 32-bit RET instructions (also 
by default).
•Calls from 32-bit procedur es to 16-bit procedures — Calls to the interface procedure from a 32-bit code 
segment are made with 32-bit CALL instructions (by default), and returns to the calling procedure from the 
interface procedure are made with 32-bit RET instructions  (also by default). Calls from the interface procedure 
to 16-bit procedures require the CALL instructions to have the operand-size prefixes, and returns from the 
called procedures to the interface procedure are perf ormed with 16-bit RET instructions (by default).22-8 Vol. 3BMIXING 16-BIT AND 32-BIT CODEVol. 3B 23-1CHAPTER 23
Intel 64 and IA-32 processors are binary compatible. Co mpatibility means that, within limited constraints, 
programs that execute on previous generations of processo rs will produce identical results when executed on later 
processors. The compatibility constraints and any implem entation differences between the Intel 64 and IA-32 
processors are described in this chapter.
Each new processor has enhanced the software visible arch itecture from that found in earlier Intel 64 and IA-32

Each new processor has enhanced the software visible arch itecture from that found in earlier Intel 64 and IA-32 
processors. Those enhancements have been defined with co nsideration for compatibility with previous and future 
processors. This chapter also summarizes the compatibility considerations for those extensions.
23.1 PROCESSOR FAMILIES AND CATEGORIES
IA-32 processors are referred to in several different ways in this chapter, depending on the type of compatibility 
information being related, as  described in the following:
•IA-32 Processors — All the Intel processors based on the In tel IA-32 Architecture, which include the 
8086/88, Intel 286, Intel386, Intel486, Pentium, Pentium Pro, Pentium II, Pentium III, Pentium 4, and Intel 
•32-bit Processors — All the IA-32 processors that use a 32-bit architecture, which include the Intel386, 
Intel486, Pentium, Pentium Pro, Pentium II, Pentium III, Pentium 4, and Intel Xeon processors.
•16-bit Processors — All the IA-32 processors that use a 16-bit  architecture, which include the 8086/88 and 
Intel 286 processors.
•P6 Family Processors — All the IA-32 processors that are based on the P6 microarchitecture, which include 
the Pentium Pro, Pentium II, and Pentium III processors.
•Pentium® 4 Processors — A family of IA-32 and Intel 64 processo rs that are based on the Intel NetBurst® 
•Intel® Pentium® M Processors — A family of IA-32 processors that are based on the Intel Pentium M 
processor microarchitecture.
•Intel® Core™ Duo and Solo Processors — Families of IA-32 processors that are based on an improved Intel 
Pentium M processor microarchitecture.
•Intel® Xeon® Processors — A family of IA-32 and Intel 64 processors that are based on the Intel NetBurst 
microarchitecture. This family includes the Intel Xeon processor and the Intel Xeon processor MP based on the 
Intel NetBurst microarchitecture. Intel Xeon processors 3000, 3100, 3200, 3300, 3200, 5100, 5200, 5300, 
5400, 7200, 7300 series are based on Intel Core micr oarchitectures and support Intel 64 architecture.
•Pentium® D Processors — A family of dual-core Intel 64 processors that provides two processor cores in a 
physical package. Each core is based on the Intel NetBurst microarchitecture.
•Pentium® Processor Extreme Editions — A family of dual-core Intel 64 processors that provides two 
processor cores in a physical package. Each core is ba sed on the Intel NetBurst microarchitecture and supports 
Intel Hyper-Threading Technology.
•Intel® Core™ 2 Processor family — A family of Intel 64 processors that are based on the Intel Core microar-
chitecture. Intel Pentium Dual-Core processors are also based on the Intel Core microarchitecture.
•Intel Atom® Processors — A family of IA-32 and Intel 64 processors . 45 nm Intel Atom processors are based 
on the Intel Atom microarchitecture. 32 nm Intel Atom processors are based on newer microarchitectures 
including the Silvermont microarchitecture and the Airmon t microarchitecture. Each generation of Intel Atom 
processors can be identified by the CPUID’s DisplayF amily_DisplayModel signature; see Table 2-1 “CPUID 
Signature Values of DisplayFamily_DisplayModel” in Chap ter 2, “Model-Specific Registers (MSRs),” of the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 4.23-2 Vol. 3BARCHITECTURE COMPATIBILITY
23.2 RESERVED BITS
Throughout this manual, certain bits are marked as reserved in many register and memory layout descriptions. 
When bits are marked as undefined or reserved, it is essent ial for compatibility with future processors that software 
treat these bits as having a future, though unknown effect. Software should follow these guidelines in dealing with 
reserved bits:
•Do not depend on the states of any reserved bits when testing the values of registers or memory locations that 
contain such bits. Mask out the reserved bits before testing.
•Do not depend on the states of any reserved bits when storing them to memory or to a register.
Software written for existing IA-32 processor that handles reserved bits correctly will port to future IA-32 proces-
sors without generating protection exceptions.
23.3 ENABLING NEW FUNCTIONS AND MODES
Most of the new control functions defined for the P6 fam ily and Pentium processors are enabled by new mode flags 
in the control registers (primarily register CR4). This re gister is undefined for IA-32 processors earlier than the 
Pentium processor. Attempting to access this register with an Intel486 or earlier IA-32 processor results in an 
invalid-opcode exception (#UD). Consequently, programs th at execute correctly on the Intel486 or earlier IA-32 
processor cannot erroneously enable these functions. Attemp ting to set a reserved bit in register CR4 to a value 
other than its original value results in a general-protecti on exception (#GP). So, programs that execute on the P6 
family and Pentium processors cannot erroneously enable  functions that may be implemented in future IA-32 
The P6 family and Pentium processors do not check for atte mpts to set reserved bits in model-specific registers; 
however these bits may be checked on more recent processors . It is the obligation of the software writer to enforce 
this discipline. These reserved bits ma y be used in future Intel processors.
23.4 DETECTING THE PRESENCE OF  NEW FEATURES THROUGH SOFTWARE
Software can check for the presence of new architectural features and extensions in either of two ways:
1. Test for the presence of the feature or extension. Softwa re can test for the presence of new flags in the EFLAGS 
register and control registers. If these flags are reserv ed (meaning not present in the processor executing the 
test), an exception is generated. Likewise, software can attempt to execute a new instruction, which results in 
an invalid-opcode exception (#UD) being generated if it is not supported.
2. Execute the CPUID instruction. The CPUID instruction (added to the IA-32 in the Pentium processor) indicates 
the presence of new features directly.
See Chapter 20, “Processor Identification and Feature Determination,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 1, for detailed in formation on detecting new processor features and exten-
sions.
23.5 INTEL MMX TECHNOLOGY
The Pentium processor with MMX technology introduced th e MMX technology and a set of MMX instructions to the 
IA-32. The MMX instructions are described in Chapter 9,  “Programming with Intel® MMX™ Technology,” in the 
Intel® 64 and IA-32 Architectures Software Develo per’s Manual, Volume 1, and in the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D. The MMX technology  and MMX instructions are 
also included in the Pentium II, Pentium  III, Pentium 4, and Intel Xeon processors.Vol. 3B 23-3ARCHITECTURE COMPATIBILITY
23.6 STREAMING SIMD EXTENSIONS (SSE)
The Streaming SIMD Extensions (SSE) were introduced in the Pentium III processor. The SSE extensions consist of 
a new set of instructions and a new set of registers. The new registers include the eight 128-bit XMM registers and 
the 32-bit MXCSR control and status register. These instructions and registers are designed to allow SIMD compu-tations to be made on single precision floating-point numbe rs. Several of these new instructions also operate in the 
MMX registers. SSE instructions and registers are describ ed in Section 10, “Programming with Intel® Streaming 
SIMD Extensions (Intel® SSE),” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, 
and in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D. 
23.7 STREAMING SIMD EXTENSIONS 2 (SSE2)
The Streaming SIMD Extensions 2 (SSE2) were introduc ed in the Pentium 4 and Intel Xeon processors. They 
consist of a new set of instructions that operate on th e XMM and MXCSR registers and perform SIMD operations on 
double precision floating-point values and on integer valu es. Several of these new instructions also operate in the 
MMX registers. SSE2 instructions and registers are descri bed in Chapter 11, “Programming with Intel® Streaming 
SIMD Extensions 2 (Intel® SSE2),” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
1, and in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D.
23.8 STREAMING SIMD EXTENSIONS 3 (SSE3)
The Streaming SIMD Extensions 3 (SSE3) were introduced in Pentium 4 processors supporting Intel Hyper-Threading Technology and Intel Xeon processors. SSE3 extensions include 13 instructions. Ten of these 13 instruc-tions support the single instruction multiple data (SIMD) execution model used with SSE/SSE2 extensions. One 
SSE3 instruction accelerates x87 style programming for conversion to integer. The remaining two instructions

SSE3 instruction accelerates x87 style programming for conversion to integer. The remaining two instructions 
(MONITOR and MWAIT) accelerate synchronization of thre ads. SSE3 instructions are described in Chapter 12, 
“Programming with Intel® SSE3, SSSE3, Intel® SSE4, and Intel® AES-NI,” in the Intel
® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 1, and in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volumes 2A, 2B, 2C, & 2D.
23.9 ADDITIONAL STREAMING SIMD EXTENSIONS
The Supplemental Streaming SIMD Extensions 3 (SSSE3) we re introduced in the Intel Core 2 processor and Intel 
Xeon processor 5100 series. Streaming SIMD Extensions 4 pr ovided 54 new instructions introduced in 45 nm Intel 
Xeon processors and Intel Core 2 processors. SSSE3, SSE4.1 and SSE4.2 instructions are described in Chapter 12, 
“Programming with Intel® SSE3, SSSE3, Intel®  SSE4, and Intel® AES-NI,” in the Intel® 64 and IA-32 Architec-
23.10 INTEL HYPER-THREADING TECHNOLOGY
Intel Hyper-Threading Technology provides two logical pr ocessors that can execute two separate code streams 
(called threads ) concurrently by using shared resources in a single processor core or in a physical package. 
This feature was introduced in the Intel Xeon processor MP and later steppings of the Intel Xeon processor, and 
Pentium 4 processors supporting Intel Hyper-Threading Technology. The feature is also found in the Pentium 
processor Extreme Edition. See also: Section 9.7, “Intel® Hyper-Threading Technology Architecture.”
45 nm and 32 nm Intel Atom processors support Intel Hyper-Threading Technology.
Intel Atom processors based on Silvermont and Airmont microarchitectures do not support Intel Hyper-Threading 
Technology.23-4 Vol. 3BARCHITECTURE COMPATIBILITY
23.11 MULTI-CORE TECHNOLOGY
The Pentium D processor and Pentium processor Extreme Edition provide two processor cores in each physical 
processor package. See also: Section 9.5, “Intel® Hyper-Th reading Technology and Intel® Multi-Core Technology,” 
and Section 9.8, “Multi-Core Architecture.” Intel Core 2 Duo, Intel Pentium Dual-Core processors, Intel Xeon processors 3000, 3100, 5100, 5200 series provide two proc essor cores in each physical processor package. Intel 
Core 2 Extreme, Intel Core 2 Quad processors, Intel Xe on processors 3200, 3300, 5300, 5400, 7300 series provide 
two processor cores in each physical processor package.
23.12 SPECIFIC FEATURES OF DUAL-CORE PROCESSOR 
Dual-core processors may have some processor-specific feat ures. Use CPUID feature flags to detect the availability 
features. Note the following:
•CPUID Brand String — On Pentium processor Extreme Edition, the process will report the correct brand string 
only after the correct microcode updates are loaded.
•Enhanced Intel SpeedStep Technology — This feature is supported in Pentium D processor but not in 
Pentium processor Extreme Edition. 
23.13 NEW INSTRUCTIONS IN THE PE NTIUM AND LATER IA-32 PROCESSORS
Table 23-1 identifies the instructions introduced into th e IA-32 in the Pentium processor and later IA-32 processors.
23.13.1 Instructions Added Prior to the Pentium Processor
The following instructions were added in the Intel486 processor:
•BSWAP (byte swap) instruction.
•XADD (exchange and add) instruction.
•CMPXCHG (compare and exchange) instruction.
• ΙNVD (invalidate cache) instruction.
•WBINVD (write-back and invalidate cache) instruction.
•INVLPG (invalidate TLB entry) instruction.
Table 23-1.  New Instructio n in the Pentium Processor and Later IA-32 Processors
Instruction CPUID Identification Bits Introduced In
CMOV cc (conditional move) EDX, Bit 15 Pentium Pro processor
FCMOV cc (floating-point conditional move) EDX, Bits 0 and 15
FCOMI (floating-point compare an d set EFLAGS) EDX, Bits 0 and 15
RDPMC (read performance monitoring co unters) EAX, Bits 8-11, set to 6H; 
see Note 1
UD2 (undefined) EAX, Bi ts 8-11, set to 6HVol. 3B 23-5ARCHITECTURE COMPATIBILITY
The following instructions were added in the Intel386 processor:
•LSS, LFS, and LGS (load SS, FS, and GS registers).
•Long-displacement conditional jumps.
•Single-bit instructions.
•Bit scan instructions.
•Double-shift instructions.
•Byte set on condition instruction.
•Move with sign/zero extension.
•Generalized multiply instruction.
•MOV to and from control registers.
•MOV to and from test registers (now obsolete).
•MOV to and from debug registers.
•RSM (resume from SMM). This instruction was introduc ed in the Intel386 SL and Intel486 SL processors.
The following instructions were added in the Intel 387 math coprocessor:
•FPREM1.
•FUCOM, FUCOMP, and FUCOMPP.
23.14 OBSOLETE INSTRUCTIONS
The MOV to and from test registers instructions were  removed from the Pentium processor and future IA-32 
processors. Execution of these instructions generates an invalid-opcode exception (#UD).
23.15 UNDEFINED OPCODES
All new instructions defined for Intel 64 and IA-32 processo rs use binary encodings that were reserved on earlier-
generation processors. Generally, attempting to execute a reserved opcode results in an invalid-opcode (#UD) 
exception being generated. Consequently, programs that  execute correctly on earlier-generation processors 
cannot erroneously execute these instructions and thereb y produce unexpected results when executed on later 
For compatibility with prior generations, there are a few re served opcodes which do not result in a #UD but rather 
result in the same behavior as certain defined instructions . In the interest of standardization, it is recommended CMPXCHG8B (compare and exchange 8 bytes) EDX, Bit 8 Pentium processor
CPUID (CPU identification) None; see Note 2
RDTSC (read time-stamp  counter) EDX, Bit 4
RDMSR (read model-specific register) EDX, Bit 5WRMSR (write model-specific register) EDX, Bit 5
MMX Instructions EDX, Bit 23
NOTES:
1. The RDPMC instruction was introduced in the P6 family of proc essors and added to later model Pentium processors. This instruc -
tion is model specific in nature and not architectural.
2. The CPUID instruction is available in all Pentium and P6 family  processors and in later models of the Intel486 processors. Th e ability 
to set and clear the ID flag (bit 21) in the EFLAGS regi ster indicates the availabili ty of the CPUID instruction.Table 23-1.  New Instruction in  the Pentium Processor and La ter IA-32 Processors (Contd.)
Instruction CPUID Identification Bits Introduced In23-6 Vol. 3BARCHITECTURE COMPATIBILITY
that software not use the opcodes given below but instead use those defined in the Intel® 64 and IA-32 Architec-
The following items enumerate those reserved opcodes (referring in some cases to opcode groups as defined in 
Appendix A, “Opcode Map,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D).
•Immediate Group 1 - When not in 64-bit mode, instructions enco ded with opcode 82H result in the behavior 
of the corresponding instructions encoded with opcode  80H. Depending on the Op/Reg field of the ModR/M 
Byte, these opcodes are the byte forms of ADD, OR, AD C, SBB, AND, SUB, XOR, CMP. (In 64-bit mode, these 
opcodes cause a #UD.)
•Shift Group 2 /6 - Instructions encoded with opcodes C0H, C1H,  D0H, D1H, D2H, and D3H with value 110B in 
the Op/Reg field (/6) of the ModR/M Byte result in the behavior of the corresponding instructions with value 
100B in the Op/Reg field (/4). These are various forms of the SAL/SHL instruction.
•Unary Group 3 /1  - Instructions encoded with opcodes F6H and F7H with value 001B in the Op/Reg field (/01) 
of the ModR/M Byte result in the behavior of the corresp onding instructions with value 000B in the Op/Reg field 
(/0). These are various forms of the TEST instruction.
•Reserved NOP  - Instructions encoded with the opcode 0F 0DH or with the opcodes 0F18H through 0F1FH 
result in the behavior of the NOP (No Operation) inst ruction, except for those opcodes defined in the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D. The opcodes not so defined 
are considered “Reserved NOP” and may be used for fu ture instructions which have no defined impact on 
existing architectural state. These reserved NOP op codes are decoded with a ModR/M byte and typical 
instruction prefix options but still result in the behavior of the NOP instruction.
•x87 Opcodes  - There are several groups of x87 opcodes wh ich provide the same behavior as other x87 
instructions. See Section 23.18.9 for the complete list.
There are a few reserved opcodes that provide unique beha vior but do not provide capabilities that are not already 
available in the main instructions defined in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
•D6H - When not in 64-bit mode SALC - Set AL to Cary flag. IF (CF=1), AL=FF, ELSE, AL=0 (#UD in 64-bit 
mode)

mode)
•x87 Opcodes  - There are a few x87 opcodes with subtly differ ent behavior from existing x87 instructions. See 
Section 23.18.9 for details.
23.16 NEW FLAGS IN THE EFLAGS REGISTER
The section titled “EFLAGS Register” in Chapter 3, “Basic Execution Environment,” of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1, shows the configuration of flags in the EFLAGS register for the P6 
family processors. No new flags have been added to this register in the P6 family processors. The flags added to 
this register in the Pentium and Intel486 proc essors are described in the following sections.
The following flags were added to the EF LAGS register in the Pentium processor:
•VIF (virtual interrupt flag), bit 19.
•VIP (virtual interrupt pending), bit 20. 
•ID (identification flag), bit 21. 
The AC flag (bit 18) was added to the EFLAGS register in the Intel486 processor.
23.16.1 Using EFLAGS Flags to Distingu ish Between 32-Bit IA-32 Processors
The following bits in the EFLAGS regi ster that can be used to differentiate between the 32-bit IA-32 processors:
•Bit 18 (the AC flag) can be used to distinguish an Inte l386 processor from the P6 family, Pentium, and Intel486 
processors. Since it is not implemented on the Intel386 processor, it will always be clear.
•Bit 21 (the ID flag) indicates whether an application ca n execute the CPUID instructio n. The ability to set and 
clear this bit indicates that the processor is a P6 family or Pentium processor. The CPUID instruction can then 
be used to determine which processor. Vol. 3B 23-7ARCHITECTURE COMPATIBILITY
•Bits 19 (the VIF flag) and 20 (the VIP flag) will always be zero on processors that do not support virtual mode 
extensions, which includes all 32-bit processors prior to the Pentium processor.
Software Developer’s Manual, Volume 1, for more information on identifying processors.
23.17 STACK OPERATIONS AND USER SOFTWARE
This section identifies the differences in stack im plementation between the various IA-32 processors.
23.17.1 PUSH SP
The P6 family, Pentium, Intel486, Intel386, and Intel 286 pr ocessors push a different value on the stack for a PUSH 
SP instruction than the 8086 processor. The 32-bit processors  push the value of the SP register before it is decre-
mented as part of the push operation; the 8086 processor pushes the value of the SP register after it is decre-
mented. If the value pushed is important, replace PUSH SP instructions with the following three instructions:
PUSH BP
MOV  BP, SPXCHG BP, [BP] 
This code functions as the 8086 processor PUSH SP instru ction on the P6 family, Pentium, Intel486, Intel386, and 
23.17.2 EFLAGS Pushed on the Stack
The setting of the stored values of bits 12 through 15 (whi ch includes the IOPL field and the NT flag) in the EFLAGS 
register by the PUSHF instruction, by interrupts, and by exceptions is different with the 32-bit IA-32 processors 
than with the 8086 and Intel 286 processors. The differences are as follows:
•8086 processor—bits 12 through 15 are always set.
•Intel 286 processor—bits 12 through 15 are always cleared in real-address mode. 
•32-bit processors in real-address mode—bit 15 (reserved)  is always cleared, and bits 12 through 14 have the 
last value loaded into them.
23.18 X87 FPU
This section addresses the issues that must be faced wh en porting floating-point software designed to run on 
earlier IA-32 processors and math coprocessors to a Pentium 4, Intel Xeon, P6 family, or Pentium processor with 
integrated x87 FPU. To software, a Pentium 4, Intel Xeon , or P6 family processor looks very much like a Pentium 
processor. Floating-point software which runs on a Pent ium or Intel486 DX processor, or on an Intel486 SX 
processor/Intel 487 SX math coprocessor system or an Intel386 processor/Intel 387 math coprocessor system, 
will run with at most minor modifications on a Pentium 4, Intel Xeon, or P6 family processor. To port code directly 
from an Intel 286 processor/Intel 287 math coprocessor system or an Intel 8086 processor/8087 math copro-cessor system to a Pentium 4, Intel Xeon, P6 family, or Pentium processor, certain additional issues must be 
addressed. 
In the following sections, the term “32-bit x87 FPUs” refers  to the P6 family, Pentium, and Intel486 DX processors, 
and to the Intel 487 SX and Intel 387 math coprocessors; th e term “16-bit IA-32 math coprocessors” refers to the 
Intel 287 and 8087 math coprocessors.23-8 Vol. 3BARCHITECTURE COMPATIBILITY
23.18.1 Control Register CR0 Flags
The ET, NE, and MP flags in control register CR0 control th e interface between the integer unit of an IA-32 processor 
and either its internal x87 FPU or an external math copr ocessor. The effect of these flags in the various IA-32 
processors are described in the following paragraphs.
The ET (extension type) flag (bit 4 of the CR0 register) is used in the Intel386 processor to indicate whether the 
math coprocessor in the system is an Intel 287 math co processor (flag is clear) or an Intel 387 DX math copro-
cessor (flag is set). This bit is hardwired to 1 in  the P6 family, Pentium, and Intel486 processors.
The NE (Numeric Exception) flag (bit 5 of the CR0 register ) is used in the P6 family, Pentium, and Intel486 proces-
sors to determine whether unmasked floating-point exceptio ns are reported internally through interrupt vector 16 
(flag is set) or externally through an ex ternal interrupt (flag is clear). On a hardware reset, the NE flag is initialized 
to 0, so software using the automatic internal error-reportin g mechanism must set this flag to 1. This flag is nonex-
istent on the Intel386 processor.
As on the Intel 286 and Intel386 processors, the MP (monitor  coprocessor) flag (bit 1 of register CR0) determines 
whether the WAIT/FWAIT instructions or waiting-type floati ng-point instructions trap when the context of the x87 
FPU is different from that of the current ly-executing task. If the MP and TS fl ag are set, then a WAIT/FWAIT instruc-
tion and waiting instructions will cause a device-not-available exception (interrupt vector 7). The MP flag is used on 
the Intel 286 and Intel386 processors to support the use of  a WAIT/FWAIT instruction to wait on a device other 
than a math coprocessor. The device reports its status through the BUSY# pin. Since the P6 family, Pentium, and 
Intel486 processors do not have such a pin, the MP flag ha s no relevant use and should be set to 1 for normal oper-
ation.
23.18.2 x87 FPU Status Word
This section identifies differences to the x87 FPU status word for the different IA-32 processors and math coproces-
sors, the reason for the differences, and their impact on software.
23.18.2.1  Condition Code Flags (C0 through C3)
The following information pertains to differences in the use of the condition code flags (C0 through C3) located in 
bits 8, 9, 10, and 14 of the x87 FPU status word.
After execution of an FINIT instruction or a hardware rese t on a 32-bit x87 FPU, the condition code flags are set to 
0. The same operations on a 16-bit IA-32 math coprocessor leave these flags intact (they contain their prior value). 
This difference in operation has no impact on software and provides a consistent state after reset.
Transcendental instruction results in the core range of th e P6 family and Pentium processors may differ from the 
Intel486 DX processor and Intel 487 SX math coprocessor by 2 to 3 units in the last place (ulps)—(see “Transcen-
dental Instruction Accuracy” in Chapter 8, “P rogramming with the x87 FPU,” of the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 1). As a result, the value saved in the C1 flag may also differ.
After an incomplete FPREM/FPREM1 instruction, the C0, C1 , and C3 flags are set to 0 on the 32-bit x87 FPUs. After 
the same operation on a 16-bit IA-32 math coprocessor, these flags are left intact. 
On the 32-bit x87 FPUs, the C2 flag serves as an incomplete  flag for the FTAN instruction. On the 16-bit IA-32 math 
coprocessors, the C2 flag is undefined for the FPTAN instruction. This difference has no impact on software, 
because Intel 287 or 8087 programs do not check C2 after an FPTAN instruction. The use of this flag on later 
processors allows fast checking of operand range.
23.18.2.2  Stack Fault Flag
When unmasked stack overflow or underflow occurs on a 32-bi t x87 FPU, the IE flag (bit 0) and the SF flag (bit 6) 
of the x87 FPU status word are set to indicate a stack fault and condition code flag C1 is set or cleared to indicate 
overflow or underflow, respectively. When unmasked stack overflow or underflow occurs on a 16-bit IA-32 math 
coprocessor, only the IE flag is set. Bit 6 is reserved on these processors. The addition of the SF flag on a 32-bit x87 
FPU has no impact on software. Existing exception handle rs need not change, but may be upgraded to take advan-

tage of the additional information.Vol. 3B 23-9ARCHITECTURE COMPATIBILITY
23.18.3 x87 FPU Control Word
Only affine closure is supported for infinity control on a 32-bit x87 FPU. The infinity control flag (bit 12 of the x87 
FPU control word) remains programmable on these processors, but has no effect. This change was made to 
conform to the IEEE Standard 754 for Floating-Point Arit hmetic. On a 16-bit IA-32 math coprocessor, both affine 
and projective closures are supported, as determined by the setting of bit 12. After a hardware reset, the default 
value of bit 12 is projective. Software that requires projective infinity arithmetic may give different results.
23.18.4 x87 FPU Tag Word
When loading the tag word of a 32-bit x87 FPU, using an FLDENV, FRSTOR, or FXRSTOR (Pentium III processor only) 
instruction, the processor examines the incoming tag and classifies the location only as empty or non-empty. Thus, tag values of 00, 01, and 10 are interpreted by the processo r to indicate a non-empty location. The tag value of 11 
is interpreted by the processor to indicate an empty lo cation. Subsequent operations on a non-empty register 
always examine the value in the register, not the value in its tag. The FSTENV, FSAVE, and FXSAVE (Pentium 
III 
processor only) instructions examine the non-empty register s and put the correct values in the tags before storing 
the tag word.
The corresponding tag for a 16-bit IA-32 math coprocessor is checked before each register access to determine the 
class of operand in the register; the tag is updated after every change to a register so that the tag always reflects 
the most recent status of the register. Software can load a tag with a value that disagrees with the contents of a 
register (for example, the register contains a valid valu e, but the tag says special). Here, the 16-bit IA-32 math 
coprocessors honor the tag and do not examine the register. 
Software written to run on a 16-bit IA-32 math coprocesso r may not operate correctly on a 16-bit x87 FPU, if it 
uses the FLDENV, FRSTOR, or FXRSTOR instructions to change tags to values (other than to empty) that are different from actual register contents.
The encoding in the tag word for the 32-bit x87 FPUs fo r unsupported data formats (including pseudo-zero and 
unnormal) is special (10B), to comply with IEEE Standard  754. The encoding in the 16-bit IA-32 math coprocessors 
for pseudo-zero and unnormal is valid (00B) and the encoding for other unsupported data formats is special (10B). 
Code that recognizes the pseudo-zero or unnormal format as valid must therefore be changed if it is ported to a 32-
bit x87 FPU.
23.18.5 Data Types
This section discusses the differences of data types for the various x87 FPUs and math coprocessors.
23.18.5.1  NaNs
The 32-bit x87 FPUs distinguish betwee n signaling NaNs (SNaNs) and quiet NaNs (QNaNs). These x87 FPUs only 
generate QNaNs and normally do not generate an exce ption upon encountering a QNaN. An invalid-operation 
exception (#I) is generated only upon encountering a SN aN, except for the FCOM, FIST, and FBSTP instructions, 
which also generates an invalid-operation exceptions for a QNaNs. This behavior matches IEEE Standard 754.
The 16-bit IA-32 math coprocessors only generate one kind  of NaN (the equivalent of a QNaN), but the raise an 
invalid-operation exception upon encountering any kind of NaN.
When porting software written to run on a 16-bit IA-32 math  coprocessor to a 32-bit x87 FPU, uninitialized memory 
locations that contain QNaNs should be changed to SNaNs to cause the x87 FPU or math coprocessor to fault when 
uninitialized memory locations are referenced.
23.18.5.2  Pseudo-zero, Pseudo-NaN, Ps eudo-infinity, and Unnormal Formats
The 32-bit x87 FPUs neither generate nor support the ps eudo-zero, pseudo-NaN, pseudo-infinity, and unnormal 
formats. Whenever they encounter them in an arithmetic operation, they raise an invalid-operation exception. The 
16-bit IA-32 math coprocessors define and support specia l handling for these formats. Support for these formats 
was dropped to conform with IEEE Standard 754 for Floating-Point Arithmetic.23-10 Vol. 3BARCHITECTURE COMPATIBILITY
This change should not impact software ported from 16-bit IA-32 math coprocessors to 32-bit x87 FPUs. The 32-
bit x87 FPUs do not generate these formats, and therefor e will not encounter them unless software explicitly loads 
them in the data registers. The only affect may be in how software handles the tags in the tag word (see also: 
Section 23.18.4, “x87 FPU Tag Word”).
23.18.6 Floating-Point Exceptions
This section identifies the implementation differences in exception handling for floating-point instructions in the 
various x87 FPUs and math coprocessors.
23.18.6.1  Denormal Operand Exception (#D)
When the denormal operand exception is masked, the 32 -bit x87 FPUs automatically normalize denormalized 
numbers when possible; whereas, the 16-bit IA-32 math co processors return a denormal result. A program written 
to run on a 16-bit IA-32 math coprocessor that uses th e denormal exception solely to normalize denormalized 
operands is redundant when run on the 32-bit x87 FPUs. If  such a program is run on 32-bit x87 FPUs, performance 
can be improved by masking the denormal exception. Floa ting-point programs run faster when the FPU performs 
normalization of denormalized operands.
The denormal operand exception is not raised for transce ndental instructions and the FXTRACT instruction on the 
16-bit IA-32 math coprocessors. This exception is raised for these instructions on the 32-bit x87 FPUs. The excep-
tion handlers ported to these latter processors need to be  changed only if the handlers gives special treatment to 
different opcodes.
23.18.6.2  Numeric Overflow Exception (#O)
On the 32-bit x87 FPUs, when the numeric overflow except ion is masked and the rounding mode is set to chop 
(toward 0), the result is the largest positive or smallest  negative number. The 16-bit IA-32 math coprocessors do 
not signal the overflow exception when the masked response is not ∞; that is, they signal overflow only when the 
rounding control is not set to round to 0. If rounding is set to chop (toward 0), the result is positive or negative ∞. 
Under the most common rounding modes, this difference has no impact on existing software. 
If rounding is toward 0 (chop), a program on a 32-bit x87 FPU produces, under overflow conditions, a result that is 
different in the least significant bit of the significand, co mpared to the result on a 16-bit IA-32 math coprocessor. 
The reason for this difference is IEEE Standard 754 compatibility.
When the overflow exception is not ma sked, the precision exception is flagge d on the 32-bit x87 FPUs. When the 
result is stored in the stack, the significand is rounded  according to the precision control (PC) field of the FPU 
control word or according to the opcode. On the 16-bit IA-32 math coprocessors, the precision exception is not 
flagged and the significand is not rounded. The impact on exis ting software is that if the result is stored on the 
stack, a program running on a 32-bit x87 FPU produces a di fferent result under overflow conditions than on a 16-
bit IA-32 math coprocessor. The difference is apparent on ly to the exception handler. This difference is for IEEE 
Standard 754 compatibility.
23.18.6.3  Numeric Underflow Exception (#U)
When the underflow exception is masked on the 32-bit x8 7 FPUs, the underflow exception is signaled when the 
result is tiny and inexact (see Section 4.9.1.5,  “Numeric Underflow Exception (#U),” in Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1). When the underflow exception is unmasked and the instruction 
is supposed to store the result on the stack, the signific and is rounded to the appropri ate precision (according to 
the PC flag in the FPU control word, for those instructions controlled by PC, otherwise to extended precision), after 
adjusting the exponent.
23.18.6.4  Exception Precedence
There is no difference in the precedence of the denormal-o perand exception on the 32-bit x87 FPUs, whether it be 
masked or not. When the denormal-operand exception is  not masked on the 16-bit IA-32 math coprocessors, it 
takes precedence over all other exceptions. This differen ce causes no impact on existing software, but some Vol. 3B 23-11ARCHITECTURE COMPATIBILITY
unneeded normalization of denormaliz ed operands is prevented on the Intel486 processor and Intel 387 math 
23.18.6.5  CS and EIP For FPU Exceptions
On the Intel 32-bit x87 FPUs, the values from the CS and EIP registers saved for floating-point exceptions point to 
any prefixes that come before the floating-point instruct ion. On the 8087 math coprocessor, the saved CS and IP 
registers points to the floating-point instruction.
23.18.6.6  FPU Error Signals

The floating-point error signals to the P6 family, Pentium, and Intel486 processors do not pass through an interrupt 
controller; an INT# signal from an Intel 387, Intel 287 or  8087 math coprocessors does. If an 8086 processor uses 
another exception for the 8087 interrupt, both exception vectors should call the floating-point-error exception 
handler. Some instructions in a floating-point-error except ion handler may need to be deleted if they use the inter-
rupt controller. The P6 family, Pentium, and Intel486 proc essors have signals that, with the addition of external 
logic, support reporting for emulation of the interrupt mechanism used in many personal computers.
On the P6 family, Pentium, and Intel486 processors, an undefined floating-point opcode will cause an invalid-
opcode exception (#UD, interrupt vector 6). Undefined floa ting-point opcodes, like legal floating-point opcodes, 
cause a device not available exception (#NM, interrupt vector 7) when either the TS or EM flag in control register 
CR0 is set. The P6 family, Pentium, and Intel486 processo rs do not check for floating-point error conditions on 
encountering an undefined floating-point opcode.
23.18.6.7  Assertion of the FERR# Pin
When using the MS-DOS compatibility mode for handing floating-point exceptions, the FERR# pin must be 
connected to an input to an external interrupt controller . An external interrupt is then generated when the FERR# 
output drives the input to the interrupt controller and the interrupt controller in turn drives the INTR pin on the 
For the P6 family and Intel386 processors, an unmasked fl oating-point exception always causes the FERR# pin to 
be asserted upon completion of the instruction that ca used the exception. For the Pentium and Intel486 proces-
sors, an unmasked floating-point exception may cause the FERR# pin to be asserted either at the end of the instruction causing the exception or immediately before exec ution of the next floating-point instruction. (Note that 
the next floating-point instruction would not be executed until the pending unmasked exception has been 
handled.) See Appendix D, “Guidelines for Writing SIMD  Floating-Point Exception Handlers,” in the Intel
® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 1,  for a complete description of the required mechanism 
for handling floating-point exceptions  using the MS-DOS compatibility mode.
Using FERR# and IGNNE# to handle floating-point exceptio n is deprecated by modern  operating systems; this 
23.18.6.8  Invalid Operation Exception On Denormals 
An invalid-operation exception is not generated on the 32- bit x87 FPUs upon encountering a denormal value when 
executing a FSQRT, FDIV, or FPREM instruction or upon conv ersion to BCD or to integer. The operation proceeds by 
first normalizing the value. On the 16-bit IA-32 math copr ocessors, upon encountering this situation, the invalid-
operation exception is generated. This difference has no impact on existing software. Software running on the 32-
bit x87 FPUs continues to execute in cases where the 16-bit IA-32 math coprocessors trap. The reason for this 
change was to eliminate an exception from being raised.
23.18.6.9  Alignment Check Exceptions (#AC)
If alignment checking is enabled, a misaligned data oper and on the P6 family, Pentium, and Intel486 processors 
causes an alignment check exception (#AC) when a program or procedure is running at privilege-level 3, except 
for the stack portion of the FSAVE/FNSAVE, FXSAVE, FRSTOR, and FXRSTOR instructions.23-12 Vol. 3BARCHITECTURE COMPATIBILITY
23.18.6.10  Segment Not Present Exception During FLDENV
On the Intel486 processor, when a segment not present exception (#NP) occurs in the middle of an FLDENV 
instruction, it can happen that part of the environment is loaded and part not. In such  cases, the FPU control word 
is left with a value of 007FH. The P6 family and Pentium pr ocessors ensure the internal state is correct at all times 
by attempting to read the first and last bytes of the environment before updating the internal state.
23.18.6.11  Device Not Available Exception (#NM)
The device-not-available exception (#NM, interrupt 7) will occur in the P6 family, Pentium, and Intel486 processors 
as described in Section 2.5, “Control Registers,” Table 2-2, and Chapter 6, “Interrupt 7—Device Not Available 
Exception (#NM).”
23.18.6.12  Coprocessor Segment Overrun Exception
The coprocessor segment overrun exception (interrupt 9) do es not occur in the P6 family, Pentium, and Intel486 
processors. In situations where the Intel 387 math coproce ssor would cause an interrupt 9, the P6 family, Pentium, 
and Intel486 processors simply abort the instruction. To avoid undetected segment overruns, it is recommended 
that the floating-point save area be placed in the same page as the TSS. This placement will prevent the FPU envi-
ronment from being lost if a page fault occurs during th e execution of an FLDENV, FRSTOR, or FXRSTOR instruction 
while the operating system is performing a task switch.
23.18.6.13  General Protection Exception (#GP)
A general-protection exception (#GP, interrupt 13) occurs if  the starting address of a floating-point operand falls 
outside a segment’s size. An exception handler should  be included to report these programming errors.
23.18.6.14  Floating-Point Error Exception (#MF)
In real mode and protected mode (not including virtual-8 086 mode), interrupt vector 16 must point to the floating-
point exception handler. In virtual-8086 mode, the vi rtual-8086 monitor can be programmed to accommodate a 
different location of the interrupt vector for floating-point exceptions.
23.18.7 Changes to Floating-Point Instructions
This section identifies the differences in floating-point instructions for the various Intel FPU and math coprocessor 
architectures, the reason for the differences, and their impact on software.
23.18.7.1  FDIV, FPREM, and FSQRT Instructions
The 32-bit x87 FPUs support operations on denormalized operands and, when detected, an underflow exception 
can occur, for compatibility with the IEEE Standard 754. The 16-bit IA-32 math coprocessors do not operate on 
denormalized operands or return underflow results. Inst ead, they generate an invalid-operation exception when 
they detect an underflow condition. An existing underflo w exception handler will requir e change only if it gives 
different treatment to different opcodes. Also, it is po ssible that fewer invalid-operation exceptions will occur.
23.18.7.2  FSCALE Instruction
With the 32-bit x87 FPUs, the range of the scaling operand is not restricted. If (0 < | ST(1) < 1), the scaling factor 
is 0; therefore, ST(0) remains unchange d. If the rounded result is not exact or if there was a loss of accuracy 
(masked underflow), the precision exception is signaled. Wi th the 16-bit IA-32 math coprocessors, the range of the 
scaling operand is restricted. If (0 < | ST(1) | < 1), the re sult is undefined and no exception is signaled. The 
impact of this difference on exiting soft ware is that different results are deliver ed on the 32-bit and 16-bit FPUs and 
math coprocessors when (0 < | ST(1) | < 1).Vol. 3B 23-13ARCHITECTURE COMPATIBILITY
23.18.7.3  FPREM1 Instruction
The 32-bit x87 FPUs compute a partial remainder according to  IEEE Standard 754. This instruction does not exist 
on the 16-bit IA-32 math coprocessors. The availability of the FPREM1 instruction has is no impact on existing soft-ware.
23.18.7.4  FPREM Instruction
On the 32-bit x87 FPUs, the condition code flags C0, C3, C1  in the status word correctly reflect the three low-order 
bits of the quotient following execution of the FPREM in struction. On the 16-bit IA-32 math coprocessors, the 
quotient bits are incorrect when performing a reduction of (64N + M) when (N ≥ 1) and M is 1 or 2. This difference 
does not affect existing software; software that  works around the bug should not be affected.
23.18.7.5  FUCOM, FUCOMP, and FUCOMPP Instructions
When executing the FUCOM, FUCOMP, and FUCOMPP instruct ions, the 32-bit x87 FPUs perform unordered compare 
according to IEEE Standard 754. These instructions do no t exist on the 16-bit IA-32 math coprocessors. The avail-
ability of these new instructions ha s no impact on existing software.
23.18.7.6  FPTAN Instruction
On the 32-bit x87 FPUs, the range of the operand for the FPTAN instruction is much less restricted (| ST(0) | < 263) 
than on earlier math coprocessors. The instruction reduces the operand intern ally using an internal π/4 constant 
that is more accurate. The range of the operand is restricted to (| ST(0) | < π/4) on the 16-bit IA-32 math copro-
cessors; the operand must be reduced to this range using FP REM. This change has no impact on existing software. 
See also sections 8.3.8 and section 8.3.10 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

See also sections 8.3.8 and section 8.3.10 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1, for more information on the accuracy of the FPTAN instruction.
23.18.7.7  Stack Overflow
On the 32-bit x87 FPUs, if an FPU stack overflow occurs when the invalid-operation exception is masked, the FPU 
returns the real, integer, or BCD-integer indefinite value to the destination operand, depending on the instruction 
being executed. On the 16-bit IA-32 math coprocessors, th e original operand remains unchanged following a stack 
overflow, but it is loaded into register ST(1). Th is difference has no impact on existing software.
23.18.7.8  FSIN, FCOS, and FSINCOS Instructions
On the 32-bit x87 FPUs, these instructions perform three common trigonometric functions. These instructions do 
not exist on the 16-bit IA-32 math coprocessors. The availa bility of these instructions has no impact on existing 
software, but using them provides a performance upgrade. See also sections 8.3.8 and section 8.3.10 of the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Vo lume 1, for more information on the accuracy of the 
FSIN, FCOS, and FSINCOS instructions.
23.18.7.9  FPATAN Instruction
On the 32-bit x87 FPUs, the range of operands for the FPAT AN instruction is unrestricted. On the 16-bit IA-32 math 
coprocessors, the absolute value of the operand in register  ST(0) must be smaller than the absolute value of the 
operand in register ST(1). This difference has impact on existing software.
23.18.7.10  F2XM1 Instruction
The 32-bit x87 FPUs support a wider range of operan ds (–1 < ST (0) < + 1) for the F2XM1 instruction. The 
supported operand range for the 16-bit IA-32 math coprocessors is (0 ≤ST(0) ≤0.5). This difference has no impact 
on existing software.23-14 Vol. 3BARCHITECTURE COMPATIBILITY
23.18.7.11  FLD Instruction
On the 32-bit x87 FPUs, when using the FLD instruction to  load an extended-real value, a denormal-operand excep-
tion is not generated because the instruction is not arit hmetic. The 16-bit IA-32 math coprocessors do report a 
denormal-operand exception in this situation. This  difference does not affect existing software.
On the 32-bit x87 FPUs, loading a denormal value that is in  single- or double-real format causes the value to be 
converted to extended-real format. Loading a denormal va lue on the 16-bit IA-32 math coprocessors causes the 
value to be converted to an unnormal. If the next instru ction is FXTRACT or FXAM, the 32-bit x87 FPUs will give a 
different result than the 16-bit IA-32 math coprocessors. This change was made for IEEE Standard 754 compati-bility.
On the 32-bit x87 FPUs, loading an SNaN that is in single- or double-real format causes the FPU to generate an 
invalid-operation exception. The 16-bit IA-32 math coproce ssors do not raise an exception when loading a signaling 
NaN. The invalid-operation exception handler for 16-bit ma th coprocessor software needs to be updated to handle 
this condition when porting software to 32-bit FPUs. Th is change was made for IEEE Standard 754 compatibility.
23.18.7.12  FXTRACT Instruction
On the 32-bit x87 FPUs, if the operand is 0 for the FXTRAC T instruction, the divide-by-zero exception is reported 
and – ∞ is delivered to register ST(1). If the operand is + ∞, no exception is reported. If the operand is 0 on the 16-
bit IA-32 math coprocessors, 0 is delivered to register ST(1) and no exception is reported. If the operand is + ∞, the 
invalid-operation exception is reported. These differences have no impact on existing software. Software usually 
bypasses 0 and ∞. This change is due to the IEEE Standard 754 recommendation to fully support the “logb” func-
tion.
23.18.7.13  Load Constant Instructions
On 32-bit x87 FPUs, rounding control is in effect for the load  constant instructions. Rounding control is not in effect 
for the 16-bit IA-32 math coprocessors. Results for the FLDPI, FLDLN2, FLDLG2, and FL DL2E instructions are the 
same as for the 16-bit IA-32 math coprocessors when rounding control is set to round to nearest or round to + ∞. 
They are the same for the FLDL2T inst ruction when rounding control is set to round to nearest, round to – ∞, or 
round to zero. Results are different from the 16-bit IA-32 math coprocessors in the least significant bit of the mantissa if rounding control is set to round to – ∞ or round to 0 for the FLDPI, FL DLN2, FLDLG2, and FLDL2E instruc-
tions; they are different for the FLDL2T instruction if round to + ∞ is specified. These changes were implemented for 
compatibility with IEEE Standard 754 for Floating-Point Arithmetic recommendations.
23.18.7.14  FXAM Instruction
With the 32-bit x87 FPUs, if the FPU encounters an empty register when executing the FXAM instruction, it not 
generate combinations of C0 through C3 equal to 1101 or  1111. The 16-bit IA-32 math coprocessors may generate 
these combinations, among others. This difference has no impact on existing software; it provides a performance 
upgrade to provide repeatable results.
23.18.7.15  FSAVE and FSTENV Instructions
With the 32-bit x87 FPUs, the address of a memory operand pointer stored by FSAVE or FSTENV is undefined if the 
previous floating-point instruction did not refer to memory
23.18.8 Transcendental Instructions
The floating-point results of the P6 family and Pentium processors for transcendental instructions in the core range may differ from the Intel486 processors by about 2 or 3 ulps (see “Transcendental Instruction Accuracy” in Chapter 
8, “Programming with the x87 FPU,” of the Intel
1). Condition code flag C1 of the status word may differ as a result. The exact threshold for underflow and overflow 
will vary by a few ulps. The P6 family and Pentium processo rs’ results will have a worst case error of less than 1 ulp 
when rounding to the nearest-even and less than 1.5 ul ps when rounding in other modes. The transcendental Vol. 3B 23-15ARCHITECTURE COMPATIBILITY
instructions are guaranteed to be monotonic, with respec t to the input operands, throughout the domain supported 
by the instruction.
Transcendental instructions may generate different result s in the round-up flag (C1) on the 32-bit x87 FPUs. The 
round-up flag is undefined for these instructions on th e 16-bit IA-32 math coprocessors. This difference has no 
impact on existing software.
23.18.9 Obsolete Instructions and Undefined Opcodes
The 8087 math coprocessor instructions FENI and FDISI, and the Intel 287 math coprocessor instruction FSETPM 
are treated as integer NOP instructions in the 32-bit x 87 FPUs. If these opcodes are detected in the instruction 
stream, no specific operation is performed and no internal  states are affected. FSETPM informed the Intel 287 math 
coprocessor that the processor was in protected mode. The 32-bit x87 FPUs handle all addressing and exception-
pointer information, whether in protected mode or not.
For compatibility with prior generations there are a few reserved x87 opcodes which do not result in an invalid-
opcode (#UD) exception, but rather result in the same beha vior as existing defined x87 instructions. In the interest 
of standardization, it is recommended that the opcodes defined in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, be used for these operations for standardization.
•DCD0H through DCD7H - Behaves the same as FCOM, D8D0H through D8D7H.
•DCD8H through DCDFH - Behaves the same as FCOMP, D8D8H through D8DFH.
•DDC8H through DDCFH - Behaves the same as FXCH, D9C8H through D9CFH.
•DED0H through DED7H - Behaves the same as FCOMP, D8D8H through D8DFH.
•DFD0H through DFD7H - Behaves the same as FSTP, DDD8H through DDDFH.
•DFC8H through DFCFH - Behaves the same as FXCH, D9C8H through D9CFH.
•DFD8H through DFDFH - Behaves the same as FSTP, DDD8H through DDDFH.
There are a few reserved x87 opcodes which provide unique behavior but do not provide capabilities which are not 
already available in the main instructions defined in the Intel® 64 and IA-32 Architectures Software Developer’s 
•D9D8H through D9DFH - Behaves the same as FSTP (DDD8H through DDDFH) but won't cause a stack 
underflow exception.
•DFC0H through DFC7H - Behaves the same as FFREE (DDC 0H through DDD7H) with the addition of an x87 
stack POP.
23.18.10 WAIT/FWAIT Prefix Differences
On the Intel486 processor, when a WAIT/FWAIT instruction precedes a floating-point instruction (one which itself 
automatically synchronizes with the previous floating-point  instruction), the WAIT/FWAIT instruction is treated as 
a no-op. Pending floating-point exceptions from a previo us floating-point instruction are processed not on the 
WAIT/FWAIT instruction but on the floating-point instructio n following the WAIT/FWAIT instruction. In such a case, 
the report of a floating-point exception may appear one in struction later on the Intel 486 processor than on a P6 
family or Pentium FPU, or on Intel 387 math coprocessor.
23.18.11 Operands Split Across Segments and/or Pages

stack POP.
On the P6 family, Pentium, and Intel486 processor FPUs, when  the first half of an operand to be written is inside a 
page or segment and the second half is outside, a memory  fault can cause the first half to be stored but not the 
second half. In this situation, the Intel 387 math coprocessor stores nothing.
23.18.12 FPU Instruction Synchronization
On the 32-bit x87 FPUs, all floating-point instructions are automatically synchronized; that is, the processor auto-matically waits until the previous floating-point instructio n has completed before completi ng the next floating-point 23-16 Vol. 3BARCHITECTURE COMPATIBILITY
instruction. No explicit WAIT/FWAIT instructions are requ ired to assure this synchronization. For the 8087 math 
coprocessors, explicit waits are required before each floati ng-point instruction to ensure synchronization. Although 
8087 programs having explicit WAIT instructions execut e perfectly on the 32-bit IA-32 processors without reas-
sembly, these WAIT instructions are unnecessary.
23.19 SERIALIZING INSTRUCTIONS
Certain instructions have been defined to serialize instruction execution to ensure that modifications to flags, regis-ters, and memory are completed before the next instructio n is executed (or in P6 family processor terminology 
“committed to machine state”). Because the P6 family pr ocessors use branch-prediction and out-of-order execu-
tion techniques to improve performance, instruction execut ion is not generally serialized until the results of an 
executed instruction are committed to machine state (see Chapter 2, “Intel® 64 and IA-32 Architectures,” in the 
Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). 
As a result, at places in a program or task where it is cr itical to have execution completed for all previous instruc-
tions before executing the next instruct ion (for example, at a branch, at the end of a procedure, or in multipro-
cessor dependent code), it is useful to add a serializing instruction. See Section 9.3, “Serializing Instructions,” for 
more information on serializing instructions.
23.20 FPU AND MATH COPR OCESSOR INITIALIZATION
Table 10-1 shows the states of the FPUs in the P6 family , Pentium, Intel486 processors  and of the Intel 387 math 
coprocessor and Intel 287 coprocessor following a power-up, reset, or INIT, or following the execution of an FINIT/FNINIT instruction. The following is some additional compatibility information concer ning the initialization of 
x87 FPUs and math coprocessors.
23.20.1 Intel® 387 and Intel® 287 Math  Coprocessor Initialization
Following an Intel386 processor reset, the processor identifies its coprocessor type (Intel®287 or Intel®387 DX 
math coprocessor) by sampling its ERROR# input some time  after the falling edge of RESET# signal and before 
execution of the first floating-point instruction. The Intel 287 coprocessor keeps its ERROR# output in inactive 
state after hardware reset; the Intel 387 coprocessor keep s its ERROR# output in active state after hardware 
reset. 
Upon hardware reset or execution of the FINIT/FNINIT inst ruction, the Intel 387 math coprocessor signals an error 
condition. The P6 family, Pentium, and Intel486 processors, like the Intel 287 coprocessor, do not.
23.20.2 Intel486 SX Processor and Intel 4 87 SX Math Coprocessor Initialization
When initializing an Intel486 SX processor and an Intel 487 SX math coprocessor, the initialization routine should 
check the presence of the math coprocessor and should set the FPU related flags (E M, MP, and NE) in control 
register CR0 accordingly (see Section 2.5, “Control Register s,” for a complete description of these flags). Table 23-2 
gives the recommended settings for these flags when the ma th coprocessor is present. The FSTCW instruction will 
give a value of FFFFH for the Intel486 SX microproce ssor and 037FH for the Intel 487 SX math coprocessor.Vol. 3B 23-17ARCHITECTURE COMPATIBILITY
The EM and MP flags in register CR0 are interpreted as shown in Table 23-3. 
Following is an example code sequence to initialize the system and check for the presence of Intel486 SX 
processor/Intel 487 SX math coprocessor.
fninit
fstcw mem_locmov ax, mem_loccmp ax, 037fhjz Intel487_SX_Math_CoP rocessor_present ;ax=037fh
jmp Intel486_SX_micropro cessor_present ;ax=ffffh
If the Intel 487 SX math coprocessor is not present, the following code can be run to set the CR0 register for the 
Intel486 SX processor.
mov eax, cr0
and eax, fffffffdh ;make MP=0or eax, 0024h ;make EM=1, NE=1mov cr0, eax
This initialization will cause any floating-point instruction to generate a device not avai lable exception (#NM), inter-
rupt 7. The software emulation will then take control to execute these instructions. This code is not required if an Intel 487 SX math coprocessor is present in the system. In that case, the typical initialization routine for the 
Intel486 SX microprocessor will be adequate.
Also, when designing an Intel486 SX processor based system with an Intel 487 SX math coprocessor, timing loops 
should be independent of frequency and clocks per instruct ion. One way to attain this is to implement these loops 
in hardware and not in software (for example, BIOS).
23.21 CONTROL REGISTERS
The following sections identify the new control registers an d control register flags and fields that were introduced 
to the 32-bit IA-32 in various processor families. See Figure 2-7 for the location of these flags and fields in the control registers.Table 23-2.  Recommended Values of the EM, MP, and NE Flags for Intel486 SX Microprocessor/Intel 487 SX Math 
Coprocessor System
CR0 Flags Intel486 SX Processor Only In tel 487 SX Math Coprocessor Present
EM 1 0
MP 0 1
NE 1 0, for MS-DOS* systems
1, for user-defined exception handler
Table 23-3.  EM and MP Flag Interpretation
EM MP Interpretation
0 0 Floating-point instructions are passed to FPU; WAIT/FWAIT and other waiting-type instructions 
ignore TS.
0 1 Floating-point instructions are passed to FPU; WAIT/FWAIT and other waiting-type instructions 
test TS.
1 0 Floating-point instructions trap to emulator; WAIT/FWAIT and other waiting-type instructions 
ignore TS.
1 1 Floating-point instructions trap to emulator; WAIT/FWAIT and other waiting-type instructions 
test TS.23-18 Vol. 3BARCHITECTURE COMPATIBILITY
The Pentium III processor introduced one new control flag in control register CR4:
•OSXMMEXCPT (bit 10) — The OS will set this bit if it supports unmasked SIMD floating-point exceptions.
The Pentium II processor introduced one new control flag in control register CR4:
•OSFXSR (bit 9) — The OS supports saving and restoring the Pentium III processor state during context 
switches.
The Pentium Pro processor introduced three new control flags in control register CR4:
•PAE (bit 5) — Physical address extension. Enables pagi ng mechanism to reference extended physical addresses 
when set; restricts physical addresses to 32 bits when  clear (see also: Section 23.22.1.1, “Physical Memory 
Addressing Extension”).
•PGE (bit 7) — Page global enable. Inhibits flushing of frequently-used or shared pages on CR3 writes (see also: 
Section 23.22.1.2, “Global Pages”). 
•PCE (bit 8) — Performance-monitoring counter enable. Enables execution of the RDPMC instruction at any 
protection level.
The content of CR4 is 0H following a hardware reset.
Control register CR4 was introduced in the Pentium processo r. This register contains flags that enable certain new 
extensions provided in the Pentium processor:
•VME — Virtual-8086 mode extensions. Enables support for a virtual interrupt flag in virtual-8086 mode (see 
Section 21.3, “Interrupt and Exception Handling in Virtual-8086 Mode”).
•PVI — Protected-mode virtual interrupts. Enables support for a virtual interrupt flag in protected mode (see Section 21.4, “Protected-Mode Virtual Interrupts”).
•TSD — Time-stamp disable. Restricts the execution of the RDTSC instruction to procedures running at 
privileged level 0.
•DE — Debugging extensions. Causes an undefined op code (#UD) exception to be generated when debug 
registers DR4 and DR5 are references for improved pe rformance (see Section 23.23.3, “Debug Registers DR4 
and DR5”).
•PSE — Page size extensions. Enables 4-MByte pages with 32-bit paging when set (see Section 4.3, “32-Bit 
Paging”).
•MCE — Machine-check enable. Enables the machine-check exception, allowing exception handling for certain 
hardware error conditions (see Chapte r 16, “Machine-Check Architecture”). 
The Intel486 processor introduced five new flags in control register CR0:
•NE — Numeric error. Enables the normal mechanis m for reporting floating-point numeric errors.
•WP — Write protect. Write-protects read-o nly pages against supervisor-mode accesses.
•AM — Alignment mask. Controls whether alignment checking  is performed. Operates in conjunction with the AC 
(Alignment Check) flag.

and DR5”).
Paging”).
•NW — Not write-through. Enables write-throughs and cach e invalidation cycles when clear and disables invali-
dation cycles and write-throughs that hit in the cache when set. 
•CD — Cache disable. Enables the internal cache when clear and disables the cache when set.
The Intel486 processor introduced two new flags in control register CR3:
•PCD — Page-level cache disable. The state of this flag is  driven on the PCD# pin during bus cycles that are not 
paged, such as interrupt acknowledge cycles, when paging is enabled.   The PCD# pin is used to control caching 
in an external cache on a cycle-by-cycle basis.
•PWT — Page-level write-through. The state of this flag is driven on the PWT# pin during bus cycles that are not 
paged, such as interrupt acknowledge cycles, when paging  is enabled. The PWT# pin is used to control write 
through in an external cache on a cycle-by-cycle basis. Vol. 3B 23-19ARCHITECTURE COMPATIBILITY
23.22 MEMORY MANAGEMENT FACILITIES
The following sections describe the new memory management facilities available in the various IA-32 processors 
and some compatibility differences.
23.22.1 New Memory Management Control Flags
The Pentium Pro processor introduced three new memory  management features: physical memory addressing 
extension, the global bit in page-table entries, and genera l support for larger page sizes. These features are only 
available when operatin g in protected mode.
23.22.1.1  Physical Memory Addressing Extension
The new PAE (physical address extension) flag in control re gister CR4, bit 5, may enable additional address lines 
on the processor, allowing extended physical addresses. This option can only be used when paging is enabled, 
using a new page-table mechanism provided to support the larger physical address range (see Section 4.1, “Paging 
Modes and Control Bits”).
23.22.1.2  Global Pages
The new PGE (page global enable) flag in control regist er CR4, bit 7, provides a mechanism for preventing 
frequently used pages from being flushed from the transl ation lookaside buffer (TLB).  When this flag is set, 
frequently used pages (such as pages containing kernel procedures or common data tables) can be marked global 
by setting the global flag in a pa ge-directory or page-table entry. 
On a task switch or a write to control register CR3 (which normally causes the TLBs to be flushed), the entries in 
the TLB marked global are not flushed. Marking pages global  in this manner prevents unnecessary reloading of the 
TLB due to TLB misses on frequently used pages. See Section 4.10, “Caching Translation Information,” for a 
detailed description of this mechanism.
23.22.1.3  Larger Page Sizes
The P6 family processors support large page sizes. For 32-b it paging, this facility is enabled with the PSE (page size 
extension) flag in control register CR4, bit 4. When this  flag is set, the processor supports either 4-KByte or 4-
MByte page sizes. PAE paging and 4-level paging1 support 2-MByte pages regardless of the value of CR4.PSE (see 
Section 4.4, “PAE Paging,” and Section 4.5, “4-Level Pa ging and 5-Level Paging”). See Chapter 4, “Paging,” for 
more information about large page sizes.
23.22.2 CD and NW Cache Control Flags
The CD and NW flags in control register CR0 were introd uced in the Intel486 processor. In the P6 family and 
Pentium processors, these flags are used to implement a wr iteback strategy for the data  cache; in the Intel486 
processor, they implement a write-through strategy. See Tabl e 12-5 for a comparison of these bits on the P6 family, 
Pentium, and Intel486 processors. For complete informat ion on caching, see Chapter 12, “Memory Cache Control.”
23.22.3 Descriptor Types and Contents
Operating-system code that manages space in descriptor tables often contains an invalid value in the access-rights 
field of descriptor-table entries to identify unused entries.  Access rights values of 80H  and 00H remain invalid for 
the P6 family, Pentium, Intel486, Intel386, and Intel 286 processors. Other values that were invalid on the Intel 
286 processor may be valid on the 32-bit processors  because uses for these bits have been defined.
1. Earlier versions of this manual used the term “IA-32e paging” to identify 4-level paging.23-20 Vol. 3BARCHITECTURE COMPATIBILITY
23.22.4 Changes in Segment Descriptor Loads
On the Intel386 processor, loading a segment descriptor al ways causes a locked read and write to set the accessed 
bit of the descriptor. On the P6 family, Pentium, and Intel4 86 processors, the locked read and write occur only if the 
bit is not already set.
23.23 DEBUG FACILITIES
The P6 family and Pentium processors include extensions to the Intel486 processor debugging support for break-points. To use the new breakpoint features, it is necessary to set the DE flag in control register CR4.
23.23.1 Differences in Debug Register DR6
It is not possible to write a 1 to reserved bit 12 in debu g status register DR6 on the P6 family and Pentium proces-
sors; however, it is possible to write a 1 in this bit on the Intel486 processor. See Table 10-1 for the different setting 
of this register following a power-up or hardware reset.
23.23.2 Differences in Debug Register DR7
The P6 family and Pentium processors de termines the type of breakpoint access by the R/W0 through R/W3 fields 
in debug control register DR7 as follows: 
00 Break on instruction execution only.01 Break on data writes only.
10 Undefined if the DE flag in control register CR4 is cleared; break on I/O reads or writes but not instruction 
fetches if the DE flag in control register CR4 is set.
11 Break on data reads or writes but not instruction fetches.
On the P6 family and Pentium processors, reserved bits 11, 12, 14, and 15 are hard-wired to 0. On the Intel486 
processor, however, bit 12 can be set. See Table 10-1 for the different settings of this register following a power-up 
or hardware reset.
23.23.3 Debug Registers DR4 and DR5
Although the DR4 and DR5 registers are documented as rese rved, previous generations of processors aliased refer-
ences to these registers to debug registers DR6 and DR7,  respectively. When debug extensions are not enabled 
(the DE flag in control register CR4 is cleared), the P6  family and Pentium processo rs remain compatible with 
existing software by allowing these aliased references. When debug extensions are enabled (the DE flag is set), 
attempts to reference registers DR4 or DR5 will result in an invalid-opcode exception (#UD).
23.24 RECOGNITION OF BREAKPOINTS
For the Pentium processor, it is recommended that debugg ers execute the LGDT instruction before returning to the 
program being debugged to ensure that breakpoints are de tected. This operation does not need to be performed 
on the P6 family, Intel486, or Intel386 processors. 
The implementation of test registers on the Intel486 pr ocessor used for testing the cache and TLB has been rede-
signed using MSRs on the P6 family and Pentium processors . (Note that MSRs used for this function are different 
on the P6 family and Pentium processors.) The MOV to and from test register instructions generate invalid-opcode 
exceptions (#UD) on the P6 family processors.Vol. 3B 23-21ARCHITECTURE COMPATIBILITY
23.25 EXCEPTIONS AND/OR EXCEPTION CONDITIONS
This section describes the new exceptions and exception conditions added to the 32-bit IA-32 processors and 
implementation differences in existing exception handling . See Chapter 6, “Interrupt and Exception Handling,” for 
a detailed description of the IA-32 exceptions.
The Pentium  III processor introduced new state with the XMM regist ers. Computations involving data in these regis-
ters can produce exceptions. A new MXCSR control/status re gister is used to determine which exception or excep-
tions have occurred. When an exception associated with the XMM registers occurs, an interrupt is generated.
•SIMD floating-point exception (#XM, interrupt 19) — New exceptions associated with the SIMD floating-point 
registers and resulting computations.
No new exceptions were added with the Pentium Pro and Pe ntium II processors. The set of available exceptions is 
the same as for the Pentium processor. However, the foll owing exception condition was added to the IA-32 with the 
Pentium Pro processor:
•Machine-check exception (#MC, interrupt 18) — New exce ption conditions. Many exception conditions have 
been added to the machine-check exception and a new ar chitecture has been added for handling and reporting 
on hardware errors. See Chapter 16, “Machine-Check Ar chitecture,” for a detailed description of the new 
The following exceptions and/or exception conditions were added to the IA-32 with the Pentium processor:
•Machine-check exception (#MC, interrupt 18) — New exception. This exception reports parity and other 
hardware errors. It is a model-spec ific exception and may not be implem ented or implemented differently in 
future processors. The MCE flag in control register CR4 enables the machine-check exception. When this bit is

future processors. The MCE flag in control register CR4 enables the machine-check exception. When this bit is 
clear (which it is at reset), the processor inhibits generation of the machine-check exception.
•General-protection exception (#GP, interrupt 13) — New ex ception condition added. An attempt to write a 1 to 
a reserved bit position of a special register causes a general-protection exception to be generated.
•Page-fault exception (#PF, interrupt 14) — New exception condition added. When a 1 is detected in any of the 
reserved bit positions of a page-table entry, page-direc tory entry, or page-directory pointer during address 
translation, a page-fault exception is generated. 
The following exception was added to the Intel486 processor:
•Alignment-check exception (#AC, inte rrupt 17) — New exception. Reports unaligned memory references when 
alignment checking is being performed. 
The following exceptions and/or exception cond itions were added to the Intel386 processor:
•Divide-error exception (#DE, interrupt 0)
— Change in exception handling. Divide-error exceptions on the Intel386 processors always leave the saved 
CS:IP value pointing to the instruction that failed. On the 8086 processor, the CS:IP value points to the next 
— Change in exception handling. The Intel386 processo rs can generate the largest negative number as a 
quotient for the IDIV instruction (80H and 8000H). The 8086 processor generates a divide-error exception instead.
•Invalid-opcode exception (#UD, interrupt 6) — New exce ption condition added. Improper use of the LOCK 
instruction prefix can generate an invalid-opcode exception.
•Page-fault exception (#PF, interrupt 14) — New exceptio n condition added. If paging is enabled in a 16-bit 
program, a page-fault exception can be generated as follo ws. Paging can be used in a system with 16-bit tasks 
if all tasks use the same page directory. Because there is no place in a 16-bit TSS to store the PDBR register, 
switching to a 16-bit task does not change the value of  the PDBR register. Tasks ported from the Intel 286 
processor should be given 32-bit TSSs so they can make full use of paging.
•General-protection exception (#GP, interrupt 13) — Ne w exception condition added. The Intel386 processor 
sets a limit of 15 bytes on instruction length. The only wa y to violate this limit is by putting redundant prefixes 
before an instruction. A general-protection exception is generated if the limit on instruction length is violated. 
The 8086 processor has no instruction length limit.23-22 Vol. 3BARCHITECTURE COMPATIBILITY
23.25.1 Machine-Check Architecture
The Pentium Pro processor introduced a new architecture to  the IA-32 for handling and reporting on machine-check 
exceptions. This machine-check architecture (described in detail in Chapter 16, “M achine-Check Architecture”) 
greatly expands the ability of the processor to report on internal hardware errors.
23.25.2 Priority of Exceptions
The priority of exceptions are broken  down into several major categories:
1. Traps on the previous instruction
2. External interrupts
3. Faults on fetching the next instruction4. Faults in decoding the next instruction
5. Faults on executing an instruction
There are no changes in the priority of these major cate gories between the different processors, however, excep-
tions within these categories are implementation dependent and may change from processor to processor.
23.25.3 Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers
MMX instructions and a subset of SSE, SSE2, SSSE3 inst ructions operate on MMX registers. The exception condi-
tions of these instructions are described in the following tables.
Table 23-4.  Exception Conditions fo r Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Alignment
Exception
Real
#UDX X X X If an unmasked SIMD floating-point ex ception and CR 4.OSXMMEXCPT[bit 10] = 0. 
XX XXIf CR0.EM[bit 2] = 1.
X X X X If preceded by a LOCK prefix (F0H)
X X X X If any corresponding CPUID feature flag is ‘0’
#MF X X X X If there is a pending X87 FPU exception
#NM X X X X If CR0.TS[bit 3]=1
Stack, SS(0)X For an illegal address in the SS segment
X If a memory address referencing the SS segment is in a non-canonical form
tion, #GP(0)X X X X Legacy SSE: Memory oper and is not 16-byte aligned
X For an illegal memory operand effective addr ess in the CS, DS, ES, FS or GS segments.
X X If any part of the operand lies outside the effective address space from 0 to FFFFH
#PF(fault-code) X X X For a page fault
#XM X X X X If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1
Applicable 
InstructionsCVTPD2PI, CVTTPD2PIVol. 3B 23-23ARCHITECTURE COMPATIBILITY
Table 23-5.  Exception Conditions  for Legacy SIMD/MMX Instructio ns with XMM and FP Exception
Exception
Real
Invalid Opcode, #UDX X X X If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. 
XXX XIf CR0.EM[bit 2] = 1.
#MF X X X X If there is a pending X87 FPU exception#NM X X X X If CR0.TS[bit 3]=1
ments.
FFFFH
#AC(0)XX XIf alignment checking is enabled and an unaligned memory reference is made while 
Exception, #XMX X X X If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1
Applicable Instruc-
tionsCVTPI2PS, CVTPS2PI, CVTTPS2PI23-24 Vol. 3BARCHITECTURE COMPATIBILITY
Table 23-6.  Exception Conditions for Legacy SIMD/M MX Instructions with XMM and without FP Exception
Exception
Real
Invalid Opcode, #UDXXX XIf CR0.EM[bit 2] = 1.
#MF1
NOTES:
1. Applies to “CVTPI2PD xmm, mm” but not “CVTPI2PD xmm, m64”.X X X X If there is a pending X87 FPU exception
Stack, SS(0)X For an illegal addr ess in the SS segment
ments.
FFFFH
 #PF(fault-code) X X X For a page fault
#AC(0)XX XIf alignment checking is enabled and an unaligned memory reference is made 
while the current privilege level is 3.
tionsCVTPI2PDVol. 3B 23-25ARCHITECTURE COMPATIBILITY
Table 23-7.  Exception Conditions for SIMD /MMX Instructions with Memory Reference
Exception
Real
Invalid Opcode, #UDX X X X If CR0.EM[bit 2] = 1.
Stack, SS(0)X For an illegal addre ss in the SS segment
ments.
 #PF(fault-code) X X X For a page faultAlignment Check 
tionsPABSB, PABSD, PABSW, PACKSSWB, PACKSSDW, PA CKUSWB, PADDB, PADDD, PADDQ, PADDW, PADDSB, 
PADDSW, PADDUSB, PADDUSW, PALIGNR, PAND, PANDN,  PAVGB, PAVGW, PCMPEQB, PCMPEQD, PCMPEQW, 
PCMPGTB, PCMPGTD, PCMPGTW, PHADDD, PHADDW, PHADDSW, PHSU BD, PHSUBW, PHSUBSW, PINSRW, 
PMADDUBSW, PMADDWD, PMAXSW, PMAXUB, PMINSW, PMINUB, PMULHR SW, PMULHUW, PMULHW, PMULLW, 
PMULUDQ, PSADBW, PSHUFB, PSHUFW, PSIGNB PSIGND PSIGNW, PSLL W, PSLLD, PSLLQ, PSRAD, PSRAW, 
PSRLW, PSRLD, PSRLQ, PSUBB, PSUBD, PSUBQ, PSUBW, PSUBSB , PSUBSW, PSUBUSB, PSUBUSW, 
PUNPCKHBW, PUNPCKHWD, PUNPCKHDQ, PU NPCKLBW, PUNPCKLWD, PUNPCKLDQ, PXOR23-26 Vol. 3BARCHITECTURE COMPATIBILITY
Table 23-8.  Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception
Exception
Real
Invalid Opcode, #UDXX XXIf CR0.EM[bit 2] = 1.

Exception
Real
If ModR/M.mod ≠ 11b1
NOTES:
1. Applies to MASKMOVQ only.X X X X If preceded by a LOCK prefix (F0H)
ments.
2
If the DS, ES, FS, or GS register contains a NULL segment selector.3
2. Applies to MASKMOVQ and MOVQ (mmreg) only.
3. Applies to MASKMOVQ only.X If the memory address is in a non-canonical form.
#AC(0) X X XIf alignment checking is enabled and an unaligned memory reference is made while 
tionsMASKMOVQ, MOVNTQ, “MOVQ (mmreg)”Vol. 3B 23-27ARCHITECTURE COMPATIBILITY
23.26 INTERRUPTS
The following differences in handling interrupts are found among the IA-32 
23.26.1 Interrupt Propagation Delay
External hardware interrupts may be recognized on different instruction boundaries on the P6 family, Pentium, 
Intel486, and Intel386 processors, due to the superscaler designs of the P6 family and Pentium processors. There-
fore, the EIP pushed onto the stack wh en servicing an interrupt may be different for the P6 family, Pentium, 
Intel486, and Intel386 processors.   
23.26.2 NMI Interrupts
After an NMI interrupt is recognized by the P6 family, Pentium, Intel486, Intel386, and Intel 286 processors, the 
NMI interrupt is masked until the first IRET instruction is executed, unlike the 8086 processor.
23.26.3 IDT Limit
The LIDT instruction can be used to set a limit on the size of the IDT. A double-fault exception (#DF) is generated if an interrupt or exception attempts to read a vector be yond the limit. Shutdown then occurs on the 32-bit IA-32 
processors if the double-fault handler vector is beyond  the limit. (The 8086 processor does not have a shutdown 
mode nor a limit.)
23.27 ADVANCED PROGRAMMABLE  INTERRUPT CONTROLLER (APIC)
The Advanced Programmable Interrupt Controlle r (APIC), referred to in this book as the local APIC , was intro-
duced into the IA-32 processors with the Pentium proce ssor (beginning with the 735/90 and 815/100 models) and 
is included in the Pentium 4, Intel Xeon, and P6 family pr ocessors. The features and functions of the local APIC are 
derived from the Intel 82489DX external APIC, which was used with the Intel486 and early Pentium processors. 
Additional refinements of the local APIC architecture were  incorporated in the Pentium 4 and Intel Xeon processors.Table 23-9.  Exception Conditions  for Legacy SIMD/MMX Instruct ions without Memory Reference
Exception
Real
#NM X X If CR0.TS[bit 3]=1
tionsPEXTRW, PMOVMSKB23-28 Vol. 3BARCHITECTURE COMPATIBILITY
23.27.1 Software Visible Differences Between the Local APIC and the 82489DX
The following features in the local APIC features differ from those found in the 82489DX external APIC:
•When the local APIC is disabled by clearing the APIC software enable/disable flag in the spurious-interrupt 
vector MSR, the state of its internal registers are unaffecte d, except that the mask bits in the LVT are all set to 
block local interrupts to the processor. Also, the local APIC  ceases accepting IPIs except for INIT, SMI, NMI, and 
start-up IPIs. In the 82489DX, when the local unit is disa bled, all the internal registers including the IRR, ISR, 
and TMR are cleared and the mask bits in the LVT are set.  In this state, the 82489DX local unit will accept only 
the reset deassert message.
•In the local APIC, NMI and INIT (except for INIT deassert ) are always treated as edge triggered interrupts, even 
if programmed otherwise. In the 82489DX, these interrupts are always level triggered. 
•In the local APIC, IPIs generated through the ICR are alwa ys treated as edge triggere d (except INIT Deassert). 
In the 82489DX, the ICR can be used to generate either edge or level triggered IPIs. 
•In the local APIC, the logical destination register su pports 8 bits; in the 82489DX, it supports 32 bits. 
•In the local APIC, the APIC ID register is 4 bi ts wide; in the 82489DX, it is 8 bits wide.
•The remote read delivery mode provided in the 824 89DX and local APIC for Pentium processors is not 
supported in the local APIC in the Pentium 4, Intel Xeon, and P6 family processors.
•For the 82489DX, in the lowest priority delivery mode, all the target local APICs specified by the destination 
field participate in the lowest priority arbitration. Fo r the local APIC, only those local APICs which have free 
interrupt slots will participate in the lowest priority arbitration.
23.27.2 New Features Incorporated in  the Local APIC for the P6 Family  and Pentium 
Processors
The local APIC in the Pentium and P6 family processors have the following new features not found in the 82489DX 
external APIC.
•Cluster addressing is supported in logical destination mode.
•Focus processor checking can be enabled/disabled.
•Interrupt input signal polarity can be programmed for the LINT0 and LINT1 pins.
•An SMI IPI is supported through the ICR and I/O redirection table.
•An error status register is incorporated into the LVT to log and report APIC errors.
In the P6 family processors, the local APIC incorporates an additional LVT register to handle performance moni-
toring counter interrupts.
23.27.3 New Features Incorporated in the Lo cal APIC of the Pentium 4 and Intel Xeon 
The local APIC in the Pentium 4 and Intel Xeon processors has the following new features not found in the P6 family 
and Pentium processors and in the 82489DX.
•The local APIC ID is extended to 8 bits.
•An thermal sensor register is incorporated into the LVT to handle thermal sensor interrupts. 
•The the ability to deliver lowest-priority interrupts to a focus processor is no longer supported.
•The flat cluster logical destination mode is not supported.
23.28 TASK SWITCHING AND TSS
This section identifies the implementation differences of task switching, additions to the TSS and the handling of 
TSSs and TSS segment selectors.Vol. 3B 23-29ARCHITECTURE COMPATIBILITY
23.28.1 P6 Family and Pentium Processor TSS
When the virtual mode extensions are enabled (by setting th e VME flag in control register CR4), the TSS in the P6 
family and Pentium processors contain an interrupt redirect ion bit map, which is used in virtual-8086 mode to redi-
rect interrupts back to an 8086 program.
23.28.2 TSS Selector Writes
During task state saves, the Intel486 processor writes 2-byte segment selectors into a 32-bit TSS, leaving the 
upper 16 bits undefined. For performance reasons, the P6  family and Pentium processors write 4-byte segment 
selectors into the TSS, with the upper 2 bytes being 0. Fo r compatibility reasons, code should not depend on the 
value of the upper 16 bits of the selector in the TSS.
23.28.3 Order of Reads/Writes to the TSS
The order of reads and writes into the TSS is processo r dependent. The P6 family and Pentium processors may 
generate different page-fault addresses in control regi ster CR2 in the same TSS area than the Intel486 and 
Intel386 processors, if a TSS crosses a page boundary (which is not recommended).
23.28.4 Using A 16-Bit TSS with 32-Bit Constructs
Task switches using 16-bit TSSs should be used only for pure 16-bit code. Any new code written using 32-bit constructs (operands, addressing, or th e upper word of the EFLAGS register) sh ould use only 32-bit TSSs. This is 
due to the fact that the 32-bit processors do not save th e upper 16 bits of EFLAGS to a 16-bit TSS. A task switch 
back to a 16-bit task that was executing in virtual mode will never re-enable the virtual mode, as this flag was not saved in the upper half of the EFLAGS value in the TSS. Th erefore, it is strongly recommended that any code using 
32-bit constructs use a 32-bit TSS to ensure correct behavior in a multitasking environment.
23.28.5 Differences in I/O Map Base Addresses
The Intel486 processor considers the TSS segment to be a 16-bit segment and wraps around the 64K boundary. 
Any I/O accesses check for permission to access this I/O address at the I/O base address plus the I/O offset. If the I/O map base address exceeds the specified limit of 0DFFFH , an I/O access will wrap around and obtain the permis-
sion for the I/O address at an incorrect location within the TSS. A TSS limit violation does not occur in this situation

sion for the I/O address at an incorrect location within the TSS. A TSS limit violation does not occur in this situation 
on the Intel486 processor. However, the P6 family and Pent ium processors consider the TSS to be a 32-bit segment 
and a limit violation occurs when the I/O base address plus the I/O offset is greater than the TSS limit. By following 
the recommended specification for the I/O base address to be less than 0DFFFH, the Intel486 processor will not 
wrap around and access incorrect locations within the TSS for I/O port validation and the P6 family and Pentium processors will not experience general-protection exceptio ns (#GP). Figure 23-1 demonstrates the different areas 
accessed by the Intel486 and the P6 family and Pentium processors. 23-30 Vol. 3BARCHITECTURE COMPATIBILITY
23.29 CACHE MANAGEMENT
The P6 family processors include two levels of internal caches: L1 (level 1) and L2 (level 2). The L1 cache is divided 
into an instruction cache and a data cache; the L2 cach e is a general-purpose cache. See Section 12.1, “Internal 
Caches, TLBs, and Buffers,” for a description of these caches. (Note that although the Pentium II processor L2 
cache is physically located on a separate chip in the cassette, it is considered an internal cache.)
The Pentium processor includes separate level 1 instructio n and data caches. The data cache supports a writeback 
(or alternatively write-through, on a line by line basis) policy for memory updates.
The Intel486 processor includes a single leve l 1 cache for both instructions and data. 
The meaning of the CD and NW flags in control register CR0 have been redefined for the P6 family and Pentium 
processors. For these processors, the recommended value (00B) enables writeback for the data cache of the 
Pentium processor and for the L1 data cache and L2 cache of the P6 family processors. In the Intel486 processor, 
setting these flags to (00B) enables write-through for the cache.
External system hardware can force the Pentium processor to disable caching or to use the write-through cache 
policy should that be required. In the P6 family processors, the MTRRs can be used to override the CD and NW flags 
(see Table 12-6).
The P6 family and Pentium processors support page-level cache management in the same manner as the Intel486 
processor by using the PCD and PWT flags in control regist er CR3, the page-directory entries, and the page-table 
entries. The Intel486 processor, however, is not affected by  the state of the PWT flag since the internal cache of the 
Intel486 processor is a write-through cache.
23.29.1 Self-Modifying Code with Cache Enabled
On the Intel486 processor, a write to an instruction in the cache will modify it in both the cache and memory. If the 
instruction was prefetched before the write, however, the old version of the instruction could be the one executed. 
To prevent this problem, it is necessary to flush the inst ruction prefetch unit of the Intel486 processor by coding a 
jump instruction immediately after any write that modifies an instruction. The P6 family and Pentium processors, however, check whether a write may modify an instruction that has been prefetched for execution. This check is 
based on the linear address of the instruction. If the linear address of an instruction is found to be present in the Figure 23-1.  I/O Map Base Address DifferencesIntel486 Processor
FFFFHI/O Map
Base AddresFFFFH
FFFFH + 10H = FH
for I/O Validation
0HFFFFHFFFFH
I/O access at port 10H checks0HFFFFH + 10H = Outside Segment
bitmap at I/O address FFFFH + 10H,
which exceeds segment limit.
Wrap around does not occur,
general-protection exception (#GP) I/O access at port 10H checks
bitmap at I/O map base addressFFFFH + 10H = offset 10H.
Offset FH from beginning of
TSS segment results becauseP6 family and Pentium Processors
I/O Map
Base Addres
occurs.  wraparound occurs.Vol. 3B 23-31ARCHITECTURE COMPATIBILITY
prefetch queue, the P6 family and Pentium processors fl ush the prefetch queue, eliminating the need to code a 
jump instruction after any writes that modify an instruction. 
Because the linear address of the write is checked against the linear address of the instructions that have been 
prefetched, special care must be taken for self-modifying co de to work correctly when the physical addresses of the 
instruction and the written data are the same, but the linear addresses differ. In such cases, it is necessary to 
execute a serializing operation to flush the prefetch qu eue after the write and before executing the modified 
instruction. See Section 9.3, “Seria lizing Instructions,” for more inform ation on serializing instructions.
NOTE
The check on linear addresses described above is no t in practice a concern for compatibility. Appli-
cations that include self-modifying code use the same linear address for modifying and fetching the instruction. System software, such as a debugger , that might possibly modify an instruction using 
a different linear address than that used to fetch the instruction must execute a serializing 
operation, such as IRET, before the modified instruction is executed.
23.29.2 Disabling the L3 Cache
A unified third-level (L3) cache in processors based on Intel NetBurst microarchitecture (see Section 12.1, 
“Internal Caches, TLBs, and Buffers”) provides the third- level cache disable flag, bit 6 of the IA32_MISC_ENABLE 
MSR. The third-level cache disable flag allows the L3 cache to be disabled and enabled, independently of the L1 and 
L2 caches (see Section 12.5.4, “Disabling and Enabling th e L3 Cache”). The third-level cache disable flag applies 
only to processors based on Intel NetBurst microarchitecture. Processors with L3 and based on other microarchi-
tectures do not support the third-level cache disable flag. 
23.30 PAGING
This section identifies enhancements made to the paging mechanism and implementation differences in the paging mechanism for various IA-32 processors.
23.30.1 Large Pages
The Pentium processor extended the memory management/paging facilities of the IA-32 to allow large (4 MBytes) pages sizes (see Section 4.3, “32-Bit Paging”). The first P6 family processor (the Pentium Pro processor) added a 
2 MByte page size to the IA-32 in conjunction with the physical address extension (PAE) feature (see Section 4.4, 
“PAE Paging”). 
The availability of large pages with 32-bit paging on any IA-32 processor can be determined via feature bit 3 (PSE) 
of register EDX after the CPUID instruction has been exec ution with an argument of 1. (Large pages are always 
available with PAE paging and 4-level paging.) Intel proc essors that do not support the CPUID instruction support 
only 32-bit paging and do not support page size enhanc ements. (See “CPUID—CPU Iden tification” in Chapter 3, 
“Instruction Set Reference, A-L,” in the Intel
2A, for more information on the CPUID instruction.)
23.30.2 PCD and PWT Flags
The PCD and PWT flags were introduced to the IA-32 in the Intel486 processor to control the caching of pages:
•PCD (page-level cache disable) flag—Controls caching on a page-by-page basis.
•PWT (page-level write-through) flag—Controls the write- through/writeback caching policy on a page-by-page 
basis. Since the internal cache of the Intel486 processor is  a write-through cache, it is not affected by the state 
of the PWT flag.   23-32 Vol. 3BARCHITECTURE COMPATIBILITY
23.30.3 Enabling and Disabling Paging
Paging is enabled and disabled by load ing a value into control register CR0 that modifies the PG flag. For backward 
and forward compatibility with all IA-32 processors, Intel recommends that the following operations be performed 
when enabling or disabling paging:
1. Execute a MOV CR0, REG instruction to either set (enable paging) or clear (disable paging) the PG flag. 
2. Execute a near JMP instruction.
The sequence bounded by the MOV and JMP instructions should be identity mapped (that is, the instructions should 
reside on a page whose linear and physical addresses are identical).
For the P6 family processors, the MOV CR0, REG instruction is serializing, so the jump operation is not required. 
However, for backwards compatibility, the JMP instruction should still be included.
23.31 STACK OPERATIONS AND SUPERVISOR SOFTWARE
This section identifies the differences in the stack mechanism for the various IA-32 processors.
23.31.1 Selector Pushes and Pops
When pushing a segment selector onto the stack, the Pent ium 4, Intel Xeon, P6 family, and Intel486 processors 
decrement the ESP register by the operand size and then wr ite 2 bytes. If the operand size is 32-bits, the upper two 
bytes of the write are not modified. The Pentium processo r decrements the ESP register by the operand size and 
determines the size of the write by th e operand size. If the operand size is 32-bits, the upper two bytes are written 
as 0s. 
When popping a segment selector from the stack, the Pentium 4, Intel Xeon, P6 family, and Intel486 processors

as 0s. 
When popping a segment selector from the stack, the Pentium 4, Intel Xeon, P6 family, and Intel486 processors 
read 2 bytes and increment the ESP register by the operan d size of the instruction. The Pentium processor deter-
mines the size of the read from the operand size an d increments the ESP register by the operand size.
It is possible to align a 32-bit selector push or pop such that the operation generates an exception on a Pentium 
processor and not on an Pentium 4, Intel Xeon, P6 family, or  Intel486 processor. This could occur if the third and/or 
fourth byte of the operation lies beyond the limit of the se gment or if the third and/or fourth byte of the operation 
is locate on a non-present or inaccessible page.
For a POP-to-memory instruction that meets the following conditions:
•The stack segment size is 16-bit.
•Any 32-bit addressing form with the SIB byte specifying ESP as the base register.
•The initial stack pointer is FFFCH (32-bit operand) or FFF EH (16-bit operand) and will wrap around to 0H as a 
result of the POP operation.
The result of the memory write is implementation-specific. For example, in P6 family pr ocessors, the result of the 
memory write is SS:0H plus any scaled index and displacement. In Pentium processors, the result of the memory 
write may be either a stack fault (real mode or protected mode with stack segment size of 64 KByte), or write to 
SS:10000H plus any scaled index and displacement (protected mode and stack segment size exceeds 64 KByte).
23.31.2 Error Code Pushes
The Intel486 processor implements the error code pushed on  the stack as a 16-bit value. When pushed onto a 32-
bit stack, the Intel486 processor only pushes 2 bytes and updates ESP by 4. The P6 family and Pentium processors’ 
error code is a full 32 bits with the upper 16 bits set to zero. The P6 family and Pentium processors, therefore, push 
4 bytes and update ESP by 4. Any code that relies on the state of the upper 16 bits may produce inconsistent 
results.Vol. 3B 23-33ARCHITECTURE COMPATIBILITY
23.31.3 Fault Handling Effects on the Stack 
During the handling of certain instructions, such as CALL  and PUSHA, faults may occu r in different sequences for 
the different processors. For example, during far calls, th e Intel486 processor pushes the old CS and EIP before a 
possible branch fault is resolved. A branch fault is a fault from a branch instruction occurring from a segment limit or access rights violation. If a branch fault is taken, the Intel486 and P6 family processors will have corrupted 
memory below the stack pointer. However,  the ESP register is backed up to make the instruction restartable. The 
P6 family processors issue the branch before the pushes. Th erefore, if a branch fault does occur, these processors 
do not corrupt memory below the stack pointer. This impl ementation difference, however, does not constitute a 
compatibility problem, as only values at or above the st ack pointer are considered to be valid. Other operations 
that encounter faults may also corrupt memory below the stack pointer and this behavi or may vary on different 
23.31.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate
If a call or interrupt is made from a 32-bit stack environm ent through a 16-bit gate, only 16 bits of the old ESP can 
be pushed onto the stack. On the subsequent RET/IRET, th e 16-bit ESP is popped but the full 32-bit ESP is updated 
since control is being resumed in a 32-bit stack environmen t. The Intel486 processor writes the SS selector into the 
upper 16 bits of ESP. The P6 fami ly and Pentium processors write zeros into the upper 16 bits.     
23.32 MIXING 16- AND 32-BIT SEGMENTS
The features of the 16-bit Intel 286 processor are an obje ct-code compatible subset of those of the 32-bit IA-32 
processors. The D (default operation size) flag in segm ent descriptors indicates whether the processor treats a 
code or data segment as a 16-bit or 32-bit segment; the B (default stack size) flag in segment descriptors indicates 
whether the processor treats a stack segment as a 16-bit or 32-bit segment.
The segment descriptors used by the Intel 286 processor ar e supported by the 32-bit IA-32 processors if the Intel-
reserved word (highest word) of the de scriptor is clear. On the 32-bit IA-32 processors, this word includes the 
upper bits of the base address and the segment limit.
The segment descriptors for data segments, code segments , local descriptor tables (there are no descriptors for 
global descriptor tables), and task gates are the same fo r the 16- and 32-bit processo rs. Other 16-bit descriptors 
(TSS segment, call gate, interrupt gate, and trap  gate) are supported by the 32-bit processors. 
The 32-bit processors also have descriptors for TSS segmen ts, call gates, interrupt ga tes, and trap gates that 
support the 32-bit architecture. Both kinds of descriptors can be used in the same system.
For those segment descriptors common to both 16- and 32-bit processors, clear bits in the reserved word cause the 
32-bit processors to interpret these descriptors ex actly as an Intel 286 processor does, that is:
•Base Address — The upper 8 bits of the 32-bit base address are clear, which limits base addresses to 24 bits.
•Limit — The upper 4 bits of the limit field are clear, restricting the value of the limit field to 64 KBytes.
•Granularity bit — The G (granularity) flag is clear, indicati ng the value of the 16-bit limit is interpreted in units 
of 1 byte.
•Big bit — In a data-segment descriptor, the B flag is  clear in the segment descriptor used by the 32-bit 
processors, indicating the segmen t is no larger than 64 KBytes.
•Default bit — In a code-segment descriptor, the D flag is  clear, indicating 16-bit addressing and operands are 
the default. In a stack-segment descriptor, the D flag is cl ear, indicating use of the SP register (instead of the 
ESP register) and a 64-KByte maximum segment limit.
For information on mixing 16- and 32-bit code in appl ications, see Chapter 22, “Mixing 16-Bit and 32-Bit Code.”
23.33 SEGMENT AND ADDRESS WRAPAROUND
This section discusses differences in segment and address wraparound between the P6 family, Pentium, Intel486, 
Intel386, Intel 286, and 8086 processors.23-34 Vol. 3BARCHITECTURE COMPATIBILITY
23.33.1 Segment Wraparound
On the 8086 processor, an attempt to access a memory op erand that crosses offset 65,535 or 0FFFFH or offset 0 
(for example, moving a word to offset 65,535 or pushing a word when the stack pointer is set to 1) causes the 
offset to wrap around modulo 65,536 or 010000H. With th e Intel 286 processor, any base and offset combination 
that addresses beyond 16 MBytes wraps around to the 1 MByte of the address space. The P6 family, Pentium, 
Intel486, and Intel386 processors in real-address mode generate an exception in these cases: 
•A general-protection exception (#GP) if the segment is a data segment (that is, if the CS, DS, ES, FS, or GS 
register is being used to address the segment).
•A stack-fault exception (#SS) if the segment is a stack segment (that is, if the SS register is being used). 
An exception to this behavior occurs when a stack access is  data aligned, and the stack pointer is pointing to the 
last aligned piece of data that size at the top of th e stack (ESP is FFFFFFFCH). When this data is popped, no 
segment limit violation occurs and the stack pointer will wrap around to 0. 
The address space of the P6 family, Pentium, and Intel486  processors may wraparound at 1 MByte in real-address 
mode. An external A20M# pin forces wraparound if enable d. On Intel 8086 processors, it is possible to specify 
addresses greater than 1 MByte. For example, with a se lector value FFFFH and an offset of FFFFH, the effective 
address would be 10FFEFH (1 MByte plus 65519 bytes). The 8086 processor, which can form addresses up to 20 
bits long, truncates the uppermost bit, which “wraps” this  address to FFEFH. However, the P6 family, Pentium, and 
Intel486 processors do not truncate this bit if A20M# is not enabled. 
If a stack operation wraps around the address limit, shut down occurs. (The 8086 processor does not have a shut-
down mode or a limit.) 
The behavior when executing near the limit of a 4-GB yte selector (limit = FFFFFFFFH) is different between the 
Pentium Pro and the Pentium 4 family of processors. On the Pentium Pro, instructions which cross the limit -- for example, a two byte instruction such as INC EAX that is en coded as FFH C0H starting exactly at the limit faults for 
a segment violation (a one byte instruction at FFFFFFFFH do es not cause an exception). Using the Pentium 4 micro-
processor family, neither of these situations causes a fault.
Segment wraparound and the functionality of A20M# is used  primarily by older operating systems and not used by 
modern operating systems. On newer Intel 64 processors, A20M# may be absent. 
23.34 STORE BUFFERS AND MEMORY ORDERING
The Pentium 4, Intel Xeon, and P6 family processors provid e a store buffer for temporary storage of writes (stores)

The Pentium 4, Intel Xeon, and P6 family processors provid e a store buffer for temporary storage of writes (stores) 
to memory (see Section 12.10, “Store Buffer”). Writes stor ed in the store buffer(s) are always written to memory 
in program order, with the exception of “fast string” store operations (see Section 9.2.4, “Fast-String Operation and 
Out-of-Order Stores”).
The Pentium processor has two store buffers, one correspondin g to each of the pipelines. Writes in these buffers 
are always written to memory in the order they were generated by the processor core.
It should be noted that only memory writes are buffere d and I/O writes are not. The Pentium 4, Intel Xeon, P6 
family, Pentium, and Intel486 processors do not synchron ize the completion of memory writes on the bus and 
instruction execution after a write. An I/O, locked, or se rializing instruction needs to be executed to synchronize 
writes with the next instruction (see Section 9.3, “Serializing Instructions”).
The Pentium 4, Intel Xeon, and P6 family processors use processor ordering to maintain consistency in the order 
that data is read (loaded) and written (stored) in a pr ogram and the order the processor actually carries out the 
reads and writes. With this type of ordering, reads can be  carried out speculatively and in any order, reads can pass 
buffered writes, and writes to memory are always carri ed out in program order. (See Section 9.2, “Memory 
Ordering,” for more information about processor ordering.) The Pentium III processor introduced a new instruction 
to serialize writes and make them globally visible. Me mory ordering issues can arise between a producer and a 
consumer of data. The SFENCE instruction provides a pe rformance-efficient way of ensuring ordering between 
routines that produce weakly-ordered results and routines that consume this data.
No re-ordering of reads occurs on the Pentium processor, except under the condition noted in Section 9.2.1, 
“Memory Ordering in the Intel® Pentium® and Intel486™ Processors,” and in the following paragraph describing 
the Intel486 processor. Vol. 3B 23-35ARCHITECTURE COMPATIBILITY
Specifically, the store buffers are flushed before the IN inst ruction is executed. No reads (as a result of cache miss) 
are reordered around previously generated writes sitting in  the store buffers. The implication of this is that the 
store buffers will be flushed or emptied before a subsequent bus cycle is run on the external bus.
On both the Intel486 and Pentium processors, under certai n conditions, a memory read will go onto the external 
bus before the pending memory writes in the buffer even though the writes occurred earlier in the program execu-
tion. A memory read will only be reordered in front of all writes pending in the buffers if all writes pending in the 
buffers are cache hits and the read is a cache miss. Unde r these conditions, the Intel486 and Pentium processors 
will not read from an external memory location that  needs to be updated by one of the pending writes. 
During a locked bus cycle, the Intel486 processor will al ways access external memory, it will never look for the 
location in the on-chip cache. All data pending in the In tel486 processor's store buffers will be written to memory 
before a locked cycle is allowed to proceed to the extern al bus. Thus, the locked bus cycle can be used for elimi-
nating the possibility of reordering read cycles on th e Intel486 processor. The Pentium processor does check its 
cache on a read-modify-write access and, if the cache line has been modified, writes the contents back to memory 
before locking the bus. The P6 family  processors write to their cache on a read-modify-write operation (if the 
access does not split across a cache line) and does not write back to system memory. If the access does split across a cache line, it locks the bus and accesses system memory.
I/O reads are never reordered in front of buffered memory wr ites on an IA-32 processor. This ensures an update of 
all memory locations before reading the status from an I/O device.
23.35 BUS LOCKING
The Intel 286 processor performs the bus locking differently than the Inte l P6 family, Pentium, Intel486, and 
Intel386 processors. Programs that us e forms of memory locking specific to the Intel 286 processor may not run 
properly when run on later processors.
A locked instruction is guaranteed to lock only the area  of memory defined by the destination operand, but may 
lock a larger memory area. For example, typical 8086 and In tel 286 configurations lock the entire physical memory 
space. Programmers should not depend on this.
On the Intel 286 processor, the LOCK prefix is sensitive to IOPL. If the CPL is grea ter than the IOPL, a general-
protection exception (#GP) is generated. On the Intel386 DX, Intel486, and Pentium, and P6 family processors, no 
check against IOPL is performed.
The Pentium processor automatically asserts the LOCK# si gnal when acknowledging external interrupts. After 
signaling an interrupt request, an exte rnal interrupt controller may use the data bus to send the interrupt vector to 
the processor. After receiving the inte rrupt request signal, the processor asserts LOCK# to ensure that no other 
data appears on the data bus until the interrupt vector is received. This bus locking does not occur on the P6 family 
23.36 BUS HOLD
Unlike the 8086 and Intel 286 processors, but like the Inte l386 and Intel486 processors, the P6 family and Pentium 
processors respond to requests for control of the bus from other potential bus masters, such as DMA controllers, 
between transfers of parts of an unaligned operand, such as two words which fo rm a doubleword. Unlike the 
Intel386 processor, the P6 family, Pentium, and Intel486 processors respond to bus hold during reset initialization.
23.37 MODEL-SPECIFIC EXTENSIONS TO THE IA-32
Certain extensions to the IA-32 are specific to a proce ssor or family of IA-32 processors and may not be imple-
mented or implemented in the same way in future proce ssors. The following sections describe these model-specific 
extensions. The CPUID instruction indicates the avai lability of some of the model-specific features.23-36 Vol. 3BARCHITECTURE COMPATIBILITY
23.37.1 Model-Specific Registers
The Pentium processor introduced a set of model-specific re gisters (MSRs) for use in controlling hardware functions 
and performance monitoring. To access these MSRs, two new instructions were added to the IA-32 architecture: 
read MSR (RDMSR) and write MSR (WRMSR ). The MSRs in the Pentium processor are not guaranteed to be dupli-
cated or provided in the next generation IA-32 processors.
The P6 family processors greatly increased the number of  MSRs available to software. See Chapter 2, “Model-
Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, for a 
complete list of the available MSRs. The new registers co ntrol the debug extensions, the performance counters, the 
machine-check exception capability, the machine-check architecture, and the MTRRs. These registers are acces-
sible using the RDMSR and WRMSR instructions. Specific info rmation on some of these new MSRs is provided in the 
following sections. As with the Pentium processor MSR, th e P6 family processor MSRs are not guaranteed to be 
duplicated or provided in the next generation IA-32 processors.
23.37.2 RDMSR and WRMSR Instructions
The RDMSR (read model-specific register) and WRMSR (wri te model-specific register) instructions recognize a 
much larger number of model-specific registers in the P6 family processors. (See “RDMSR—Read from Model 
Specific Register” and “WRMSR—Write to Model Specific Register” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, for more information.)
23.37.3 Memory Type Range Registers
Memory type range registers (MTRRs) are a new feature in troduced into the IA-32 in the Pentium Pro processor. 
MTRRs allow the processor to optimize memory operations for different types of memory, such as RAM, ROM, frame 
buffer memory, and memory-mapped I/O.
MTRRs are MSRs that contain an internal map of how ph ysical address ranges are mapped to various types of 
memory. The processor uses this internal memory map to  determine the cacheability of various physical memory 
locations and the optimal method of accessing memory locati ons. For example, if a memory location is specified in 
an MTRR as write-through memory, the processor handles access es to this location as follows. It reads data from 
that location in lines and caches the read data or maps all writes to that location to the bus and updates the cache to maintain cache coherency. In mapping the physical address space with MTRRs, the processor recognizes five 
types of memory: uncacheable (UC), uncacheable, spec ulatable, write-combining (WC), write-through (WT), 
write-protected (WP), and writeback (WB).
Earlier IA-32 processors (such as the Intel486 and Pentium processors) used the KEN# (cache enable) pin and

Earlier IA-32 processors (such as the Intel486 and Pentium processors) used the KEN# (cache enable) pin and 
external logic to maintain an external memory map and signal cacheable accesses to the processor. The MTRR mechanism simplifies hardware designs by eliminating the KEN# pin and the external logic required to drive it.
See Chapter 10, “Processor Management and Initialization,” and Chapter 2, “Model-Specific Registers (MSRs)‚” in 
the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, for more information on the MTRRs.
23.37.4 Machine-Check Exception and Architecture
The Pentium processor introduced a new exception called the machine-check exception (#MC, interrupt 18). This 
exception is used to detect hardware-related e rrors, such as a parity error on a read cycle. 
The P6 family processors extend the types of errors th at can be detected and that generate a machine-check 
exception. It also provides a new machine-check architecture for recording information about a machine-check 
error and provides extended recovery capability.
The machine-check architecture provides several banks of  reporting registers for recording machine-check errors. 
Each bank of registers is associated with a specific hardware unit in the processor. The primary focus of the machine checks is on bus and interconnect operations; however, checks are also made of translation lookaside 
buffer (TLB) and cache operations.Vol. 3B 23-37ARCHITECTURE COMPATIBILITY
The machine-check architecture can correct some errors automatically and allow for reliable restart of instruction 
execution. It also collects sufficient information for software to use in correcting other machine errors not corrected by hardware.
See Chapter 16, “Machine-Check Architecture,” for more  information on the machine-check exception and the 
machine-check architecture.
23.37.5 Performance-Monitoring Counters
The P6 family and Pentium processors provide two performance-monitoring counters for use in monitoring internal 
hardware operations. The number of performance monito ring counters and associated programming interfaces 
may be implementation specific for Pentium 4 processors, Pentium M processors. Later processors may have implemented these as part of an architectural performance monitoring feature. The architectural and non-architec-
tural performance monitoring interfaces for different proc essor families are described in Chapter 20, “Performance 
Monitoring.” https://perfmon-events.intel.com/
 lists all the events that can be counted for architectural perfor-
mance monitoring events and non-architectural events. The counters are set up, started, and stopped using two 
MSRs and the RDMSR and WRMSR instructions. For the P6 family processors, the current count for a particular 
counter can be read using the new RDPMC instruction.
The performance-monitoring counters are useful for debugg ing programs, optimizing code, diagnosing system fail-
ures, or refining hardware designs. See Chapter 20, “Performance Monitori ng,” for more information on these 
counters.
23.38 TWO WAYS TO RUN IN TEL 286 PROCESSOR TASKS
When porting 16-bit programs to run on 32-bit IA- 32 processors, there are two approaches to consider:
•Porting an entire 16-bit software system to a 32-bit processor, complete with the old operating system, loader, 
and system builder. Here, all tasks will have 16-bit TSSs. The 32-bit processor is being used as if it were a faster 
version of the 16-bit processor.
•Porting selected 16-bit applications to run in a 32-bit processor environment with a 32-bit operating system, 
loader, and system builder. Here, the TSSs used to repres ent 286 tasks should be changed to 32-bit TSSs. It is 
possible to mix 16 and 32-bit TSSs, but the benefits are small and the problems are great. All tasks in a 32-bit 
software system should have 32-bit TSSs. It is not ne cessary to change the 16-bit object modules themselves; 
TSSs are usually constructed by the operating system, by the loader, or by the system builder. See Chapter 22, 
“Mixing 16-Bit and 32-Bit Code,” for more detailed  information about mixing 16-bit and 32-bit code.
Because the 32-bit processors use the contents of the reserved word of 16-bit segment descriptors, 16-bit 
programs that place values in this word ma y not run correctly on the 32-bit processors.
23.39 INITIAL STATE OF PENTIUM, PE NTIUM PRO AND PENTIUM 4 PROCESSORS
Table 23-10 shows the state of the flags and other regist ers following power-up for the Pentium, Pentium Pro and 
Pentium 4 processors. The state of control register CR0 is 60000010H (see Figure 10-1 “Contents of CR0 Register 
after Reset” in the Intel® 64 and IA-32 Architectures Software Develope r’s Manual, Volume 3A). This places the 
processor in real-address mode with paging disabled.
Table 23-10.  Processor State Followi ng Power-up/Reset/INIT for Pentium, Pentium Pro and Pentium 4 Processors
Register Pentium 4 Processor Pentium  Pro Processor Pentium Processor
EIP 0000FFF0H 0000FFF0H 0000FFF0HCR0 60000010H
260000010H260000010H2
CR2, CR3, CR4 0000000 0H 00000000H 00000000H23-38 Vol. 3BARCHITECTURE COMPATIBILITY
AR = Present, R/W, AccessedSelector = F000H
Base = 00000000HLimit = FFFFH
EDX 00000FxxH  000n06xxH
3 000005xxH 
EAX 040404
EBX, ECX, ESI, EDI, EBP, 
ESP00000000H 00000000H 00000000H
ST0 through ST75Pwr up or Reset: +0.0
FINIT/FNINIT: UnchangedPwr up or Reset: +0.0
FINIT/FNINIT: Unchanged
x87 FPU Control 
Word5Pwr up or Reset: 0040HFINIT/FNINIT: 037FHPwr up or Reset: 0040H
FINIT/FNINIT: 037FHPwr up or Reset: 0040H
FINIT/FNINIT: 037FH
x87 FPU Status Word
5Pwr up or Reset: 0000H
FINIT/FNINIT: 0000HPwr up or Reset: 0000H
FINIT/FNINIT: 0000H
x87 FPU Tag Word5Pwr up or Reset: 5555H
FINIT/FNINIT: FFFFHPwr up or Reset: 5555H
FINIT/FNINIT: FFFFH
x87 FPU Data 
Operand and CS Seg. 
Selectors5Pwr up or Reset: 0000H
Operand and Inst. 
Pointers5Pwr up or Reset: 
   00000000H
FINIT/FNINIT: 00000000HPwr up or Reset: 
   00000000H
   00000000H
FINIT/FNINIT: 00000000H
MM0 through MM75Pwr up or Reset:
   0000000000000000HINIT or FINIT/FNINIT:
   UnchangedPentium II and Pentium III 
Processors Only—
Pwr up or Reset:
   0000000000000000H
INIT or FINIT/FNINIT:   UnchangedPentium with MMX Technology 
Only—
INIT or FINIT/FNINIT:   Unchanged
XMM0 through XMM7 Pwr up or Reset: 0H
INIT: UnchangedIf CPUID.01H:SSE is 1 —
Pwr up or Reset: 0H
INIT: UnchangedNA
MXCSR Pwr up or Reset: 1F80H
INIT: UnchangedPentium III processor only-
Pwr up or Reset: 1F80H
GDTR, IDTR Base = 00000000H
Limit = FFFFHAR = Present, R/WBase = 00000000H
AR = Present, R/WSelector = 0000H
DR6 FFFF0FF0H FFFF0FF0H FFFF0FF0HTable 23-10.  Processor State Followi ng Power-up/Reset/INIT for Pentium, Pentium Pro and Pentium 4 Processors 
Register Pentium 4 Processor Pentium  Pro Processor Pentium ProcessorVol. 3B 23-39ARCHITECTURE COMPATIBILITY
Time-Stamp Counter Power up or Reset: 0H
INIT: UnchangedPower up or Reset: 0H
INIT: Unchanged
Perf. Counters and 
Event SelectPower up or Reset: 0H
All Other MSRs Pwr up or Reset:
   UndefinedINIT: UnchangedPwr up or Reset:
   UndefinedINIT: Unchanged
Data and Code Cache, 
TLBsInvalid
6Invalid6Invalid6
Fixed MTRRs Pwr up or Reset: Disabled
INIT: UnchangedPwr up or Reset: Disabled
INIT: UnchangedNot Implemented
Variable MTRRs Pwr up or Reset: Disabled
Machine-Check 
ArchitecturePwr up or Reset:
    Undefined
INIT: UnchangedPwr up or Reset:
    Undefined
APIC Pwr up or Reset: Enabled
INIT: UnchangedPwr up or Reset: Enabled
R8-R1570000000000000000H 0000000000000000H N.A.
XMM8-XMM157Pwr up or Reset: 0H
INIT: UnchangedPwr up or Reset: 0H
INIT: UnchangedN.A.
NOTES:

    Undefined
    Undefined
NOTES: 
1. The 10 most-significant bits of the EFLAGS register are undefined following a reset. Software should not depend on the states  of 
2. The CD and NW flags are unchanged, bit 4 is set to 1, all other bits are cleared.3. Where “n” is the Extended Model Value for the respective processor.
7. If the processor supports IA-32e mode.Table 23-10.  Processor State Followi ng Power-up/Reset/INIT for Pentium, Pentium Pro and Pentium 4 Processors 
Register Pentium 4 Processor Pentium  Pro Processor Pentium Processor23-40 Vol. 3BARCHITECTURE COMPATIBILITYVol. 3C 24-1CHAPTER 24
24.1 OVERVIEW
This chapter describes the basics of virtual machine architec ture and an overview of th e virtual-machine extensions 
(VMX) that support virtualization of processor hardware for multiple software environments.
Information about VMX instructio ns is provided in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2B. Other aspects of VMX and system prog ramming considerations are described in chapters of 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C.
24.2 VIRTUAL MACHINE ARCHITECTURE
Virtual-machine extensions define processor-level support for virtual machines on IA-32 processors. Two principal classes of software are supported:
•Virtual-machine monitors (VMM)  — A VMM acts as a host and has full control of the processor(s) and other 
platform hardware. A VMM presents gu est software (see next paragraph) with an abstraction of a virtual 
processor and allows it to execute directly on a logical processor. A VMM is able to retain selective control of processor resources, physical memory, interrupt management, and I/O.
•Guest software — Each virtual machine (VM) is a guest software environment that supports a stack consisting 
of operating system (OS) and application software. Each  operates independently of other virtual machines and 
uses on the same interface to processor(s), memory, storage, graphics, and I/O provided by a physical 
platform. The software stack acts as if it were running on a platform with no VMM. Software executing in a 
virtual machine must operate with reduced privilege so that the VMM can retain control of platform resources.
24.3 INTRODUCTION TO VMX OPERATION
Processor support for virtualization is provided by a form  of processor operation called VMX operation. There are 
two kinds of VMX operation: VMX root operation and VMX no n-root operation. In general, a VMM will run in VMX 
root operation and guest software will run in VMX non-root operation. Transi tions between VMX root operation and 
VMX non-root operation are called VMX transitions. There are two kinds of VMX transitions. Transitions into VMX 
non-root operation are called VM entries. Transitions from VMX non-root operation to VMX root operation are called 
VM exits.
Processor behavior in VMX root operation is very much as it is outside VMX operation. The principal differences are 
that a set of new instructions (the VMX instructions) is avai lable and that the values that can be loaded into certain 
control registers are limited (see Section 24.8). 
Processor behavior in VMX non-root operation is restricted and modified to facilitate virtualization. Instead of their 
ordinary operation, certain instructions (including the new VMCALL instruction) and events cause VM exits to the 
VMM. Because these VM exits replace ordinary behavior, the functionality of software in VMX non-root operation is 
limited. It is this limitation that allows the VMM to retain control of processor resources.
There is no software-visible bit whose setting indicates wh ether a logical processor is in VMX non-root operation. 
This fact may allow a VMM to prevent guest software from determining that it is running in a virtual machine. 
Because VMX operation places restrictions even on software running with current privilege level (CPL) 0, guest 
software can run at the privilege level for which it was originally designed. This capability may simplify the devel-
opment of a VMM.24-2 Vol. 3CINTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
24.4 LIFE CYCLE OF VMM SOFTWARE
Figure 24-1 illustrates the life cycle of a VMM and its guest software as well as the interactions between them. The 
following items summarize that life cycle:
•Software enters VMX operation by executing a VMXON instruction.
•Using VM entries, a VMM can then enter guests into virtual machines (one at a time). The VMM effects a 
VM entry using instructions VMLAUNCH and VM RESUME; it regains control using VM exits. 
•VM exits transfer control to an entry point specified by  the VMM. The VMM can take action appropriate to the 
cause of the VM exit and can then return  to the virtual machine using a VM entry.
•Eventually, the VMM may decide to shut itself down an d leave VMX operation. It does so by executing the 
VMXOFF instruction.
24.5 VIRTUAL-MACHINE CONTROL STRUCTURE
VMX non-root operation and VMX transi tions are controlled by a data structure called a virtual-machine control 
structure (VMCS).
Access to the VMCS is managed through a component of pr ocessor state called the VMCS pointer (one per logical 
processor). The value of the VMCS pointer is the 64-bit ad dress of the VMCS. The VMCS pointer is read and written 
using the instructions VMPTRST and VMPTRLD. The VMM configures a VMCS using the VMREAD, VMWRITE, and 
VMCLEAR instructions.
A VMM could use a different VMCS for each virtual machine that it supports. For a virtual machine with multiple 
logical processors (virtual processors), the VMM could use a different VMCS for each virtual processor.
24.6 DISCOVERING SUPPORT FOR VMX
Before system software enters into VMX operation, it mu st discover the presence of VMX support in the processor. 
System software can determine whether a processor supports VMX operation using CPUID. If CPUID.1:ECX.VMX[bit 5] = 1, then VMX operation is supported.  See Chapter 3, “Instruction Set Reference, A-L‚” of 
the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
The VMX architecture is designed to be extensible so th at future processors in VMX operation can support addi-
tional features not present in first-generation implemen tations of the VMX architecture. The availability of exten-
sible VMX features is reported to software using a set of VMX capability MSRs (see Appendix A, “VMX Capability 
Reporting Facility”).Figure 24-1.  Interaction of a Virtual-Machine Monitor and GuestsVM MonitorGuest 0 Guest 1
VM Exit VM Exit VM Entry
VMXOFF VMXONVol. 3C 24-3INTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
24.7 ENABLING AND ENTERING VMX OPERATION
Before system software can enter VMX operation, it en ables VMX by setting CR4.VMXE[bit 13] = 1. VMX operation 
is then entered by executing the VMXON instruction. VMXO N causes an invalid-opcode exception (#UD) if executed 
with CR4.VMXE = 0. Once in VMX operation, it is not possible to clear CR4.VMXE (see Section 24.8). System soft-ware leaves VMX operation by executing the VMXOFF instru ction. CR4.VMXE can be cleared outside of VMX opera-
tion after executing of VMXOFF.
VMXON is also controlled by the IA32_FEATURE_CONTROL MSR (MSR address 3AH). This MSR is cleared to zero 
when a logical processor is reset. The relevant bits of the MSR are:
•Bit 0 is the lock bit.  If this bit is clear, VMXON causes a general- protection exception. If the lock bit is set, 
WRMSR to this MSR causes a general-protection exceptio n; the MSR cannot be modified until a power-up reset 
condition. System BIOS can use this bit to provide a setup option for BIOS to disable support for VMX. To 
enable VMX support in a platform, BIOS must set bit 1, bit 2, or both (see below), as well as the lock bit.
•Bit 1 enables VMXON in SMX operation.  If this bit is clear, execution of VMXON in SMX operation causes a 
general-protection exception. Attempts to set this bi t on logical processors that do not support both VMX 
operation (see Section 24.6) and SMX operation (see Chap ter 7, “Safer Mode Extensions Reference,” in the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D) cause general-protection 
•Bit 2 enables VMXON outside SMX operation.  If this bit is clear, execution of VMXON outside SMX 
operation causes a general-protection exception. Attempts to set this bit on logical processors that do not 
support VMX operation (see Section 24.6) cause general-protection exceptions.
NOTE
A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logical processo r is outside SMX operation if GETSEC[SENTER]

NOTE
A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logical processo r is outside SMX operation if GETSEC[SENTER] 
has not been executed or if GETSEC[SEXIT] was executed after the last execution of 
GETSEC[SENTER]. See Chapter 7, “Safer Mode Extensions Reference,” in Intel
Architectures Software Developer’s Manual, Volume 2D.
Before executing VMXON, software should allocate a natu rally aligned 4-KByte region of memory that a logical 
processor may use to support VMX operation.1 This region is called the VMXON region . The address of the VMXON 
region (the VMXON pointer) is provid ed in an operand to VMXON. Section 25.11.5, “VMXON Region,” details how 
software should initialize and access the VMXON region.
24.8 RESTRICTIONS ON VMX OPERATION
VMX operation places restrictions on processor operation. These are detailed below:
•In VMX operation, processors may fix certain bits in CR0 and CR4 to specific values and not support other 
values. VMXON fails if any of these bits contains an unsupported value (see “VMXON—Enter VMX Operation” in 
Chapter 31). Any attempt to set one of these bits to an  unsupported value while in VMX operation (including 
VMX root operation) using any of the CLTS, LMSW, or MOV CR instructions causes a general-protection 
exception. VM entry or VM exit cannot set any of these bits to an unsupported value. Software should consult 
the VMX capability MSRs IA32_VMX_CR0_FIXED0 and IA 32_VMX_CR0_FIXED1 to determine how bits in CR0 
are fixed (see Appendix A.7). For CR4, soft ware should consult the VMX capability MSRs 
IA32_VMX_CR4_FIXED0 and IA32_VMX_C R4_FIXED1 (see Appendix A.8).
NOTES
The first processors to support VMX operation requir e that the following bits be 1 in VMX operation: 
CR0.PE, CR0.NE, CR0.PG, and CR4.VMXE. The restri ctions on CR0.PE and CR0.PG imply that VMX 
1. Future processors may require that a different amount of memory be reserved. If so, this fact is reported to software using t he 
VMX capability-reporting mechanism.24-4 Vol. 3CINTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
operation is supported only in paged protected mo de (including IA-32e mode). Therefore, guest 
software cannot be run in unpaged protected mode or in real-address mode.
Later processors support a VM-execution control called “unrestricted guest” (see Section 25.6.2). 
If this control is 1, CR0.PE and CR0.PG may be 0 in VMX non-root operation (even if the capability 
MSR IA32_VMX_CR0_FIXED0 reports otherwise).1 Such processors allow guest software to run in 
unpaged protected mode or in real-address mode.
•VMXON fails if a logical processor is in A20M mode (s ee “VMXON—Enter VMX Operation” in Chapter 31). Once 
the processor is in VMX operation, A20M interrupts are bl ocked. Thus, it is impossible to be in A20M mode in 
VMX operation.
•The INIT signal is blocked whenever a logical processor is in VMX root operation. It is not blocked in VMX non-
root operation. Instead, INITs cause VM exits (see Section 26.2, “Other Causes of VM Exits”).
•Intel® Processor Trace (Intel PT) can be used in VMX operation only if IA32_VMX_MISC[14] is read as 1 (see 
Appendix A.6). On processors that su pport Intel PT but which do not allow it to be used in VMX operation, 
execution of VMXON clears IA32_RTIT_CTL.TraceEn (see  “VMXON—Enter VMX Operation” in Chapter 31); any 
attempt to write IA32_RTIT_CTL while in VMX operation (including VMX root operation) causes a general-
protection exception. 
1. “Unrestricted guest” is a secondary proces sor-based VM-execution control. If bit 31 of the primary processor-based VM-executio n 
controls is 0, VMX non-root operation functions as if the “unrestricted guest” VM-execution control were 0. See Section 25.6.2.Vol. 3C 25-1CHAPTER 25
25.1 OVERVIEW
A logical processor uses virtual-machine control data structures  (VMCSs ) while it is in VMX operation. These 
manage transitions into and out of VMX non-root operatio n (VM entries and VM exits) as well as processor behavior 
in VMX non-root operation. This structure is manipula ted by the new instructions VMCLEAR, VMPTRLD, VMREAD, 
and VMWRITE.
A VMM can use a different VMCS for each virtual machine that it supports. For a virtual machine with multiple 
logical processors (virtual processors), the VMM ca n use a different VMCS for each virtual processor.
A logical processor associates a region in memory with each VMCS. This region is called the VMCS region .1 Soft-
ware references a specific VMCS using the 64-bit physical address of the region (a VMCS pointer ). VMCS pointers 
must be aligned on a 4-KByte boundary (bits 11:0 must be  zero). These pointers must not set bits beyond the 
processor’s physical-address width.2,3
A logical processor may maintain a number of VMCSs that are active . The processor may optimize VMX operation 
by maintaining the state of an active VMCS in memory, on the processor, or both. At any given time, at most one 
of the active VMCSs is the current  VMCS. (This document frequently uses the term “the VMCS” to refer to the 
current VMCS.) The VMLAUNCH, VMREAD , VMRESUME, and VMWRITE instructio ns operate only on the current 
VMCS.
The following items describe how a logical processor determines which VMCSs are active and which is current:
•The memory operand of the VMPTRLD instruction is the ad dress of a VMCS. After execution of the instruction, 
that VMCS is both active and current on the logical processor. Any other VMCS that had been active remains so, 
but no other VMCS is current.
•The VMCS link pointer field in the current VMCS (see Sect ion 25.4.2) is itself the address of a VMCS. If VM entry 
is performed successfully with the 1-setting of the “VMCS shadowing” VM-execution control, the VMCS 
referenced by the VMCS link pointer field becomes active  on the logical processor. The identity of the current 
VMCS does not change.
•The memory operand of the VMCLEAR instruction is al so the address of a VMCS. After execution of the 
instruction, that VMCS is neither active nor current on the logical processor. If the VMCS had been current on 
the logical processor, the logical processor no longer has a current VMCS.
The VMPTRST instruction stores the address of the logical processor’s current VMCS into a specified memory loca-
tion (it stores the value FFFFFFFF_FFFFFFFFH if there is no current VMCS).
The launch state  of a VMCS determines which VM-entry instru ction should be used with that VMCS: the 
VMLAUNCH instruction requires a VMCS whose launch state is “clear”; the VMRESUME instruction requires a VMCS 
whose launch state is “launched”. A logical processor maintains a VMCS’s launch state in the corresponding VMCS 
region. The following items describe how a logical processor manages the launch state of a VMCS:
•If the launch state of the current VMCS is “clear”, su ccessful execution of the VMLAUNCH instruction changes 
the launch state to “launched”.
•The memory operand of the VMCLEAR instruction is the ad dress of a VMCS. After execution of the instruction, 
the launch state of that VMCS is “clear”.
•There are no other ways to modify the launch state of a VMCS (it cannot be modified using VMWRITE) and there 
is no direct way to discover it (it cannot be read using VMREAD).
1. The amount of memory required for a VMCS region is at most 4 KBytes. The exact size is implementation specific and can be det er-
mined by consulting the VMX capability MS R IA32_VMX_BASIC to determine the size of  the VMCS region (s ee Appendix A.1).
2. Software can determine a processor’s physical-address width by  executing CPUID with 80000008H in EAX. The physical-address 
width is returned in bits 7:0 of EAX.
3. If IA32_VMX_BASIC[48] is read as 1,  these pointers must not set any bits in the range 63:32; see Appendix A.1.25-2 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
Figure 25-1 illustrates the different states of a VMCS. It uses  “X” to refer to the VMCS an d “Y” to refer to any other 
VMCS. Thus: “VMPTRLD X” always makes X current and acti ve; “VMPTRLD Y” always makes X not current (because 
it makes Y current); VMLAUNCH makes the launch state of X “launched” if X was current and its launch state was 
“clear”; and VMCLEAR X always makes X inactive and not current and makes its launch state “clear”.
The figure does not illustrate operations that do not modi fy the VMCS state relative to these parameters (e.g., 
execution of VMPTRLD X when X is already current). No te that VMCLEAR X makes X “inactive, not current, and 
clear,” even if X’s current state is not defined (e.g., ev en if X has not yet been initialized). See Section 25.11.3.
Because a shadow VMCS (see Section 25.10) cannot be us ed for VM entry, the launch state of a shadow VMCS is 
not meaningful. Figure 25-1 does not illustrate all th e ways in which a shadow VMCS may be made active.
25.2 FORMAT OF THE VMCS REGION
A VMCS region comprises up to 4-KBytes.1 The format of a VMCS region is given in Table 25-1.Figure 25-1.  States of VMCS X
Table 25-1.  Format of the VMCS Region
Byte Offset Contents
0 Bits 30:0: VMCS revision identifier
Bit 31: shadow-VMCS indicator (see Section 25.10)
4V M X - a b o r t  i n d i c a t o r

8 VMCS data (implementation-specific format)
1. The exact size is implementation specific and can be determined  by consulting the VMX capabili ty MSR IA32_VMX_B ASIC to deter-
mine the size of the VMCS region (see Appendix A.1).Active
Not Current
Clear
Active
Current
ClearInactive
ClearActive
Launched
Active
Current
LaunchedVMPTRLD X
VMCLEAR X
VMLAUNCHVM
CL
EAR XVMCLEAR X VMCLEAR X
VMCLEAR X
Anything
ElseVMPTRLD XVMPTRLD Y
VMPTRLD XVMPTRLD YVol. 3C 25-3VIRTUAL MACHINE CONTROL STRUCTURES
The first 4 bytes of the VMCS region contain the VMCS revision identifier  at bits 30:0.1 Processors that maintain 
VMCS data in different formats (see below) use different VMCS revision identifiers. These identifiers enable soft-
ware to avoid using a VMCS region formatted for one processor on a processor that uses a different format.2 Bit 31 
of this 4-byte region indicates whether the VMCS is a shadow VMCS (see Section 25.10).
Software should write the VMCS revision identifier to th e VMCS region before using that region for a VMCS. The 
VMCS revision identifier is never wri tten by the processor; VMPTRLD fails if its operand references a VMCS region 
whose VMCS revision identifier differs from that used by  the processor. (VMPTRLD also fails if the shadow-VMCS 
indicator is 1 and the processor does not support the 1-se tting of the “VMCS shadowing”  VM-execution control; see 
Section 25.6.2) Software can discover the VMCS revision identifier that a processor uses by reading the VMX capa-
bility MSR IA32_VMX_BASIC  (see Appendix A.1).
Software should clear or set the shadow-VMCS indicator depending on whether the VMCS is to be an ordinary 
VMCS or a shadow VMCS (see Section 25.10). VMPTRLD fails if the shadow-VMC S indicator is set and the processor 
does not support the 1-setting of the “VMCS shadowing” VM-execu tion control. Software can discover support for 
this setting by reading the VMX capability MSR IA32_VMX_PROCBASED_CTLS2 (see Appendix A.3.3).
The next 4 bytes of the VMCS region are used for the VMX-abort indicator . The contents of these bits do not 
control processor operation in any way. A logical processor writes a non-zero value into these bits if a VMX abort 
occurs (see Section 28.7). Software may also write into this field.
The remainder of the VMCS region is used for VMCS data  (those parts of the VMCS that control VMX non-root 
operation and the VMX transitions). The format of these da ta is implementation-specific. VMCS data are discussed 
in Section 25.3 through Section 25.9. To  ensure proper behavior in VMX operation, software should maintain the 
VMCS region and related structures (enumerated in Se ction 25.11.4) in writeback cacheable memory. Future 
implementations may allow or require a different memory type3. Software should consult the VMX capability MSR 
IA32_VMX_BASIC (see Appendix A.1).
25.3 ORGANIZATION OF VMCS DATA
The VMCS data are organize d into six logical groups:
•Guest-state area.  Processor state is saved into the guest-stat e area on VM exits and loaded from there on 
VM entries.
•Host-state area.  Processor state is loaded from the host-state area on VM exits.
•VM-execution control fields.  These fields control processor behavi or in VMX non-root operation. They 
determine in part the causes of VM exits.
•VM-exit control fields.  These fields control VM exits.
•VM-entry control fields.  These fields control VM entries.
•VM-exit information fields. These fields receive information on VM exits and describe the cause and the 
nature of VM exits. On some processors, these fields are read-only.4
The VM-execution control fields, the VM-exit control fields , and the VM-entry control fields are sometimes referred 
to collectively as VMX controls.
1. Earlier versions of this manual specified that the VMCS revision identifier was a 32-bit field. For all processors produced p rior to this 
change, bit 31 of the VMCS revision identifier was 0.
2. Logical processors that use the same VMCS revisi on identifier use the same size for VMCS regions.
3. Alternatively, software may map any of th ese regions or structures with the UC memo ry type. Doing so is strongly discouraged 
unless necessary as it will cause the performance of transitions us ing those structures to suffer significantly. In addition, t he pro-
cessor will continue to use the memory type reported in the VMX capability MSR IA32_VMX_BASIC with exceptions noted in Appen-
dix A.1.
4.  Software can discover whether these fields can be written by reading the VMX capability MSR IA32_VMX_MISC (see Appendix A.6) .25-4 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
25.4 GUEST-STATE AREA
This section describes fields contained in the guest-state area of the VMCS. VM entries load processor state from 
these fields and VM exits store processor state into thes e fields. See Section 27.3.2 and Section 28.3 for details.
25.4.1 Guest Register State
The following fields in the guest-state area correspond to processor registers:
•Control registers CR0, CR3, and CR4 (64 bits each; 32 bi ts on processors that do not support Intel 64 archi-
tecture).
•Debug register DR7 (64 bits; 32 bits on processo rs that do not support Intel 64 architecture).
•RSP, RIP, and RFLAGS (64 bits each; 32 bits on proc essors that do not support Intel 64 architecture).1
•The following fields for each of the registers CS, SS, DS, ES, FS, GS, LDTR, and TR:
— Selector (16 bits).— Base address (64 bits; 32 bits on processors that do  not support Intel 64 architecture). The base-address 
fields for CS, SS, DS, and ES have only 32 architec turally-defined bits; nevertheless, the corresponding 
VMCS fields have 64 bits on processors that support Intel 64 architecture.
— Segment limit (32 bits). The limit field is always a measure in bytes.— Access rights (32 bits). The format of this field is given in Table 25-2 and detailed as follows:
•The low 16 bits correspond to bits 23:8 of the upper 32 bits of a 64-bit segment descriptor. While bits 
19:16 of code-segment and data-segment descriptors  correspond to the upper 4 bits of the segment 
limit, the corresponding bits (bits 11:8) are reserved in this VMCS field.
•Bit 16 indicates an unusable segment . Attempts to use such a segment fault except in 64-bit mode. 
In general, a segment register is unusable if  it has been loaded with a null selector.2
•Bits 31:17 are reserved.
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX o per-
ation also support Intel 64 architecture. Fo r processors that do not support Intel 64 architecture, this nota tion refers to the  32-bit 
forms of those registers (EAX, EIP, ESP, EFLA GS, etc.). In a few places, notation such as EAX is used to refer specifically to lower 32 
bits of the indicated register.
2. There are a few exceptions to this statement. For example, a segment with a non-null selector may be unusable following a tas k 
switch that fails after its commi t point; see “Interrupt 10—Invalid TSS Exception (#TS)” in Section 6.14, “Exception and Interr upt 
Handling in 64-bit Mode,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. In contrast, the TR reg-
ister is usable after pr ocessor reset despite having a null se lector; see Table 11-1 in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manu al, Volume 3A.Table 25-2.  Format of Access Rights 
Bit Position(s) Field
3:0 Segment type4 S — Descriptor type (0 = system; 1 = code or data)
6:5 DPL — Descriptor privilege level
7 P — Segment present11:8 Reserved
12 AVL — Available for use by system softwareVol. 3C 25-5VIRTUAL MACHINE CONTROL STRUCTURES
The base address, segment limit, and access rights compos e the “hidden” part (or “descriptor cache”) of each 
segment register. These data are included in the VMCS be cause it is possible for a segment register’s descriptor 
cache to be inconsistent with the segment descriptor in  memory (in the GDT or the LDT) referenced by the 
segment register’s selector.
The value of the DPL field for SS is always equal to  the logical processor’s cu rrent privilege level (CPL).1
On some processors, executions of VM WRITE ignore attempts to write non-zero values to any of bits 11:8 or 
bits 31:17. On such processors, VMREAD always returns 0 for those bits, and VM entry treats those bits as if 
they were all 0 (see Section 27.3.1.2).
•The following fields for each of the registers GDTR and IDTR:
— Base address (64 bits; 32 bits on processors that do not support Intel 64 architecture).
— Limit (32 bits). The limit fields contain 32 bits even th ough these fields are specified as only 16 bits in the 
•The following MSRs:
— IA32_DEBUGCTL (64 bits)— IA32_SYSENTER_CS (32 bits)
— IA32_SYSENTER_ESP and IA32_SYSENTER_EIP (64 bits; 32 bits on processors that do not support Intel 64 
architecture)

— IA32_PERF_GLOBAL_CTRL (64 bits). This field is suppo rted only on processors that support the 1-setting 
of the “load IA32_PERF_GLOBAL_CTRL” VM-entry control.
— IA32_PAT (64 bits). This field is supported only on pr ocessors that support either the 1-setting of the “load 
IA32_PAT” VM-entry control or that of  the “save IA32_PAT” VM-exit control.
— IA32_EFER (64 bits). This field is supported only on pr ocessors that support either the 1-setting of the “load 
IA32_EFER” VM-entry control or that of  the “save IA32_EFER” VM-exit control.
— IA32_BNDCFGS (64 bits). This field is supported only on  processors that support either the 1-setting of the 
“load IA32_BNDCFGS” VM-entry control or that of the “clear IA32_BNDCFGS” VM-exit control.
— IA32_RTIT_CTL (64 bits). This field is supported only on processors that support either the 1-setting of the 
“load IA32_RTIT_CTL” VM-entry control or that of the “clear IA32_RTIT_CTL” VM-exit control.
— IA32_LBR_CTL (64 bits). This field is supported only on  processors that support either the 1-setting of the 
“load guest IA32_LBR_CTL” VM-entry control or that of the “clear IA32_LBR_CTL” VM-exit control.
— IA32_S_CET (64 bits; 32 bits on processors that do  not support Intel 64 architecture). This field is 
supported only on processors that support the 1- setting of the “load CET state” VM-entry control.
— IA32_INTERRUPT_SSP_TABLE_ADDR (64 bits; 32 bits on  processors that do not support Intel 64 archi-
tecture). This field is supported only on processors that support the 1-setting of the “load CET state” VM-
entry control.13 Reserved (except for CS)
L — 64-bit mode active (for CS only)
14 D/B — Default operation size (0 = 16-bit segment; 1 = 32-bit segment)15 G — Granularity
16 Segment unusable (0 = usable; 1 = unusable)
31:17 Reserved
1. In protected mode, CPL is also associated with the RPL field in the CS selector. However, the RPL fields are not meaningful i n real-
address mode or in virtual-8086 mode.Table 25-2.  Format of Access Rights  (Contd.)
Bit Position(s) Field25-6 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
— IA32_PKRS (64 bits). This field is supported only on  processors that support the 1-setting of the “load 
PKRS” VM-entry control.
•The shadow-stack pointer register SSP (64 bits; 32 bits on processors that do not support Intel 64 archi-tecture). This field is supported only on processors that  support the 1-setting of the “load CET state” VM-entry 
control.
•The register SMBASE (32 bits). This register contains the base address of the logical processor’s SMRAM image.
25.4.2 Guest Non-Register State
In addition to the register state described in Section 25.4. 1, the guest-state area includes the following fields that 
characterize guest state but which do not correspond to processor registers:
•Activity state  (32 bits). This field identifies the logical proce ssor’s activity state. When a logical processor is 
executing instructions normally, it is in the active state . Execution of certain instructions and the occurrence 
of certain events may cause a logical processor to transition to an inactive state  in which it ceases to execute 
The following activity states are defined:1
—0 :  Active . The logical processor is executing instructions normally.
—1 :  HLT. The logical processor is inactive because it executed the HLT instruction.
—2 :  Shutdown . The logical processor is inactive because it incurred a triple fault2 or some other serious 
error.
—3 :  Wait-for-SIPI . The logical processor is inactive because it is waiting for a startup-IPI (SIPI).
Future processors may include support for other activity  states. Software should read the VMX capability MSR 
IA32_VMX_MISC (see Appendix A.6) to determine what activity states are supported.
•Interruptibility state  (32 bits). The IA-32 architecture includes features that permit certain events to be 
blocked for a period of time. This field contains information about such blocking. Details and the format of this field are given in Table 25-3.
1. Execution of the MWAIT instruction may put a logical processor into an inactive state. However, this VMCS field never reflect s this 
state. See Section 28.1.
2. A triple fault occurs when a logical processor encounters an exception wh ile attempting to de liver a double fault.Table 25-3.  Format of Interruptibility State
Bit 
Position(s)Bit Name Notes
0 Blocking by STI See the “STI—Set Interrup t Flag” section in Chapter 4 of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 2B.
Execution of STI with RFLAGS.IF = 0 blocks maskable interrupts on the instruction boundary 
following its execution.1 Setting this bit indicates that  this blocking is in effect.
1B l o c k i n g  b y  
MOV SSSee Section 6.8.3, “Masking Exceptions and Interrupts When Switching Stacks,” in the Intel® 64 
Execution of a MOV to SS or a POP to SS blocks or suppresses certain debug exceptions as well 
as interrupts (maskable and nonmaskable) on th e instruction boundary following its execution. 
Setting this bit indicates that this blocking is in effect.2 This document uses the term “blocking 
by MOV SS,” but it applies equally to POP SS.
2 Blocking by SMI See Section 32.2, “System Manageme nt Interrupt (SMI).” Syst em-management interrupts 
(SMIs) are disabled while the processor is in system-management mode (SMM). Setting this bit 
indicates that blocking of SMIs is in effect.Vol. 3C 25-7VIRTUAL MACHINE CONTROL STRUCTURES
•Pending debug exceptions  (64 bits; 32 bits on processors that do  not support Intel 64 architecture). IA-32 
processors may recognize one or more debug ex ceptions without immediately delivering them.1 This field 
contains information about such exceptions. This field is described in Table 25-4.3 Blocking by NMI See Section 6.7.1, “Handling Multiple NMIs,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3A and Section 32.8, “NMI Handling While in SMM.”
Delivery of a non-maskable interrupt (NMI) or a system-management interrupt (SMI) blocks 
subsequent NMIs until the next execution of IRET. See Section 26.3 for how this behavior of 
IRET may change in VMX non-root operation. Setting  this bit indicates that  blocking of NMIs is 
in effect. Clearing this  bit does not imply that NMIs are not (temporarily) blocked for other 
reasons.
If the “virtual NMIs” VM-execution  control (see Section 25.6.1) is 1, this bit does not control the 
blocking of NMIs. Instead, it refers to “virtual-NMI blocking” (the fact that guest software is not 
ready for an NMI).
4E n c l a v e  
interruptionSet to 1 if the VM exit occurred while the logical processor was in enclave mode.
Such VM exits includes those caused by in terrupts, non-maskable  interrupts, system-
management interrupts, INIT signals, and exceptions occurring in enclave mode as well as 
exceptions encountered during the delivery of such events incident to enclave mode.
A VM exit that is incident to delivery of an  event injected by VM entry leaves this bit 
31:5 Reserved VM entry will fail if these bits are not 0. See Section 27.3.1.5.
NOTES:
1. Nonmaskable interrupts and system-management interrupts may also be inhibited on the instruction boundary following such an 
execution of STI.
2. System-management interrupts may also be inhibited on the instruction boundary following such an execution of MOV or POP.
1. For example, execution of a MOV to SS or a POP to SS may inhibit some debug exceptions for one instruction. See Section 6.8.3  of 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. In addition, certain events incident to an instruction 
(for example, an INIT signal) may take priority over debug tr aps generated by that instruction. See Table 6-2 in the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 3A.Table 25-4.  Format of Pending-Debug-Exceptions
Bit 
3:0 B3 – B0 When set, each of these bits indicates that the corresponding breakpoint condition was met. 
Any of these bits may be set even if the corresponding enabling bit in DR7 is not set.
10:4 Reserved VM entry fails if these bits are not 0. See Section 27.3.1.5.11 BLD When set, this bit indicate s that a bus lock was asserted while OS bus-lock detection was 
enabled and CPL > 0 (see Section 18 .3.1.6, “OS Bus-Lock Detection”).
1
12 Enabled 
breakpointWhen set, this bit indicates that at least one data or I/O breakpoint was met and was enabled in 
DR7; the XBEGIN instruction was executed immediately before the VM exit and advanced debugging of RTM transactional regions had been  enabled; or a bus lock was asserted while 
CPL > 0 and OS bus-lock detection had been enabled.
13 Reserved VM entry fails if this bit is not 0. See Section 27.3.1.5.Table 25-3.  Format of Interruptibility State (Contd.)
Bit 
Position(s)Bit Name Notes25-8 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES

1
12 Enabled 
Bit 
•VMCS link pointer  (64 bits). If the “VMCS shad owing” VM-execution control is  1, the VMREAD and VMWRITE 
instructions access the VMCS referenced by this pointer (see Section 25.10). Otherwise, software should set 
this field to FFFFFFFF_FFFFFFFFH to avoid VM-e ntry failures (see Section 27.3.1.5).
•VMX-preemption timer value  (32 bits). This field is supported only on processors that support the 1-setting 
of the “activate VMX-preemption timer” VM-execution co ntrol. This field contains the value that the VMX-
preemption timer will use following the next VM entry wi th that setting. See Section 26.5.1 and Section 27.7.4.
•Page-directory-point er-table entries  (PDPTEs; 64 bits each). These four (4) fields (PDPTE0, PDPTE1, 
PDPTE2, and PDPTE3) are supported only on processors that support the 1-setting of the “enable EPT” VM-
execution control. They correspond to the PDPTEs referenced by CR3 when PAE paging is in use (see Section 
4.4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). They are used only if 
the “enable EPT” VM-execution control is 1.
•Guest interrupt status  (16 bits). This field is supported only on processors that support the 1-setting of the 
“virtual-interrupt delivery” VM-execution control. It ch aracterizes part of the guest’s virtual-APIC state and 
does not correspond to any processor or APIC registers. It comprises two 8-bit subfields:
—Requesting virtual interrupt (RVI) . This is the low byte of the gu est interrupt status. The processor 
treats this value as the vector of the highest priority virtual interrupt that is requesting service. (The value 
0 implies that there is no such interrupt.)
—Servicing virtual interrupt (SVI) . This is the high byte of the guest interrupt status. The processor treats 
this value as the vector of the highest priority virtual interrupt that is in service. (The value 0 implies that 
there is no such interrupt.)
See Chapter 30 for more information on the use of this field.
•PML index  (16 bits). This field is supported only on proces sors that support the 1-setting of the “enable PML” 
VM-execution control. It contains the logical index of the next entry in the page-modification log. Because the 
page-modification log comprises 512 entries, the PML inde x is typically a value in the range 0–511. Details of 
the page-modification log and use of the PML index are given in Section 29.3.6.
25.5 HOST-STATE AREA
This section describes fields contained in the host-state area of the VMCS. As noted earlier, processor state is loaded from these fields on every VM exit (see Section 28.5).
All fields in the host-state area correspond to processor registers:14 BS When set, this bit indicates that a debug exception would have been triggered by single-step 
execution mode.
15 Reserved VM entry fails if this bit is not 0. See Section 27.3.1.5.
16 RTM When set, this bit indicates that a debug exception (#DB) or a breakpoint exception (#BP) 
occurred inside an RTM region while advanced debugging of RTM transactional regions was 
enabled (see Section 16.3.7, “RTM-Enabled Debugger Support,” of Intel
Architectures Software Developer’s Manual, Volume 1).2
63:17 Reserved VM entry fails if these bits are not 0. See Section 27.3.1.5. Bits 63:32 exist only on processors 
that support Intel 64 architecture.
NOTES:
1. In general, the format of this field matches that of DR6. However, DR6 clears  bit 11 to indicate detection of  a bus lock, while this field 
sets the bit to indica te that condition.
2. In general, the format of this field matches that of DR6. However, DR6 clears  bit 16 to indicate an RTM-related exception, while this 
field sets the bit to indicate that condition.Table 25-4.  Format of Pending-Debug-Exceptions (Contd.)
Bit 
Position(s)Bit Name NotesVol. 3C 25-9VIRTUAL MACHINE CONTROL STRUCTURES
•CR0, CR3, and CR4 (64 bits each; 32 bits on proc essors that do not support Intel 64 architecture).
•RSP and RIP (64 bits each; 32 bits on processors that do not support Intel 64 architecture).
•Selector fields (16 bits each) for the segment registers CS, SS, DS, ES, FS, GS, and TR. There is no field in the 
host-state area for the LDTR selector.
•Base-address fields for FS, GS, TR, GDTR, and IDTR (64 bi ts each; 32 bits on processors that do not support 
Intel 64 architecture).
— IA32_SYSENTER_CS (32 bits)— IA32_SYSENTER_ESP and IA32_SYSENTER_EIP (64 bits; 32 bits on processors that do not support Intel 64 
architecture).
of the “load IA32_PERF_GLOBAL_CTRL” VM-exit control.
— IA32_PAT (64 bits). This field is supported only on  processors that support the 1-setting of the “load 
IA32_PAT” VM-exit control.
— IA32_EFER (64 bits). This field is supported only on  processors that support the 1-setting of the “load 
IA32_EFER” VM-exit control.
supported only on processors that support the 1-setting of the “load CET state” VM-exit control.
exit control.
PKRS” VM-exit control.
•The shadow-stack pointer register SSP (64 bits; 32 bits on processors that do not support Intel 64 archi-
tecture). This field is supported only on processors th at support the 1-setting of the “load CET state” VM-exit 
control.
In addition to the state identified here, some processor state components are loaded with fixed values on every 
VM exit; there are no fields corresponding to these compon ents in the host-state area. See Section 28.5 for details 
of how state is loaded on VM exits.
25.6 VM-EXECUTION CONTROL FIELDS
The VM-execution control fields govern VMX non-root op eration. These are described in Section 25.6.1 through 
Section 25.6.8.
25.6.1 Pin-Based VM-Execution Controls
The pin-based VM-execution controls constitute a 32-bit vector that governs the handling of asynchronous events 
(for example: interrupts).1 Table 25-5 lists the controls. See Chapter 28 for how these controls affect processor 
behavior in VMX non-root operation.
1. Some asynchronous events cause VM exits regardless of the settings of the pin-based VM-execution controls (see Section 26.2).25-10 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
All other bits in this field are reserved, some to 0 and so me to 1. Software should consult the VMX capability MSRs 
IA32_VMX_PINBASED_CTLS and IA32_VMX _TRUE_PINBASED_CTLS (see Appendix A.3.1) to determine how to set 
reserved bits. Failure to set reserved bits properly ca uses subsequent VM entries to fail (see Section 27.2.1.1).
The first processors to support the virtual-machine extensions  supported only the 1-settings of bits 1, 2, and 4. The 
VMX capability MSR IA32_VMX_PINB ASED_CTLS will always report that these bits must be 1. Logical processors 
that support the 0-settings of any of these bits will support the VMX capability MSR IA32_VMX_TRUE_PIN-
BASED_CTLS MSR, and software should consult this MSR to discover support for the 0-settings of these bits. Soft-
ware that is not aware of the functionality of any one of these bits should set that bit to 1.
25.6.2 Processor-Based VM-Execution Controls
The processor-based VM-execution controls constitute three vectors that govern the handling of synchronous 
events, mainly those caused by the execution of specific instructions.1 These are the primary processor-based 
VM-execution controls  (32 bits), the secondary processor-based VM-execution controls  (32 bits), and the 
tertiary VM-execution controls  (64 bits).
Table 25-6 lists the primary processor-based VM-execution controls. See Chapter 26 for more details of how these 
controls affect processor behavior in VMX non-root operation.Table 25-5.  Definitions of Pin-Based VM-Execution Controls
0 External-interrupt 
exitingIf this control is 1, external interrupts cause VM exits. Otherwise, they are delivered normally 
through the guest interrupt-descript or table (IDT). If this contro l is 1, the value of RFLAGS.IF 
does not affect interrupt blocking.
3 NMI exiting If this control is 1, non-maskable interrupts (NMIs) cause VM exits. Otherwise, they are 
delivered normally using descriptor 2 of the ID T. This control also de termines interactions 
between IRET and blocking by NMI (see Section 26.3).
5 Virtual NMIs If this control is 1,  NMIs are never blocked and the “blocking by NMI” bit (bit 3) in the 
interruptibility-state fi eld indicates “virtual-NMI blocking” (see Table 25-3). This control also 
interacts with the “NMI-window exiting” VM -execution control (s ee Section 25.6.2).

6A c t i v a t e  V M X -
preemption timerIf this control is 1, the VMX- preemption timer counts down in VMX non-root operation; see 
Section 26.5.1. A VM exit occurs when the timer counts down to zero; see Section 26.2.
7 Process posted 
interruptsIf this control is 1, the proce ssor treats interrupts with the post ed-interrupt notification vector 
(see Section 25.6.8) specially, updating the virtual-APIC page with posted-interrupt requests (see Section 30.6).
1. Some instructions cause VM exits regardless of the settings of the processor-based VM -execution controls (see Section 26.1.2),  as 
do task switches (see Section 26.2).Table 25-6.  Definitions of Primary Processor-Based VM-Execution Controls
2 Interrupt-window 
exitingIf this control is 1, a VM exit occurs at the beginning of any instruction if RFLAGS.IF = 1 and 
there are no other blocking of interrupts (see Section 25.4.2).
3 Use TSC offsetting This control determ ines whether executions of RDTSC, ex ecutions of RDTSCP, and executions 
of RDMSR that read from the IA32_TIME_STAM P_COUNTER MSR return a value modified by 
the TSC offset field (see Section 25.6.5 and Section 26.3).
7 HLT exiting This control determines whether executions of HLT cause VM exits.9 INVLPG exiting This determines whether executions of INVLPG cause VM exits.10 MWAIT exiting This control determines whether executions of MWAIT cause VM exits.11 RDPMC exiting This control determines whether executions of RDPMC cause VM exits.Vol. 3C 25-11VIRTUAL MACHINE CONTROL STRUCTURES
All other bits in this field are reserv ed, some to 0 and some to 1. Software should consult the VMX capability MSRs 
IA32_VMX_PROCBASED_CTLS and IA32_VMX_TRUE_PROCBASE D_CTLS (see Appendix A.3.2) to determine how 
to set reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail (see Section 
27.2.1.1).
The first processors to support the virtual-machine extensio ns supported only the 1-settings of bits 1, 4–6, 8, 13–
16, and 26. The VMX capability MSR IA32_VMX_PROCBASED_CTLS will always report that these bits must be 1. 
Logical processors that support the 0-settings of any of these bits will support the VMX capability MSR IA32_VMX-
_TRUE_PROCBASED_CTLS MSR, and software should consul t this MSR to discover support for the 0-settings of 
these bits. Software that is not aware of the functionality of any one of these bits should set that bit to 1.
Bit 31 of the primary processor-based VM-execution cont rols determines whether the secondary processor-based 
VM-execution controls are used. If that bit is 0, VM en try and VMX non-root operation function as if all the 
secondary processor-based VM-execution controls were 0. Processors that support only the 0-setting of bit 31 of 12 RDTSC exiting This control determines whether executions of RDTSC and RDTSCP cause VM exits.
15 CR3-load exiting In conjunction with the CR3-target controls (see Section 25.6.7), this control determines 
whether executions of MOV to CR3 cause VM exits. See Section 26.1.3.
The first processors to support the virtual-ma chine extensions supported only the 1-setting 
of this control.
16 CR3-store exiting This control determines whether executions of MOV from CR3 cause VM exits.
17 Activate tertiary 
controlsThis control determines whether the tertiary  processor-based VM-execution controls are 
used. If this control is 0, the logical processor operates as if all the tertiary processor-based 
VM-execution controls were also 0.
19 CR8-load exiting This control determines whether executions of MOV to CR8 cause VM exits.
20 CR8-store exiting This control determines whether executions of MOV from CR8 cause VM exits.
21 Use TPR shadow Setting this control to  1 enables TPR virtualization and other APIC-virtualization features. See 
Chapter 30.
22 NMI-window 
exitingIf this control is 1, a VM exit occurs at the be ginning of any instruction if there is no virtual-
NMI blocking (see Section 25.4.2).
23 MOV-DR exiting This control determines whether executions of MOV DR cause VM exits.24 Unconditional I/O 
exitingThis control determines whether executions of I/O instructions (IN, INS/INSB/INSW/INSD, OUT, 
and OUTS/OUTSB/OUTSW/O UTSD) cause VM exits.
25 Use I/O bitmaps This control determines whether I/O bitmap s are used to restrict executions of I/O instructions 
(see Section 25.6.4 and Section 26.1.3).
For this control, “0” me ans “do not use I/O bitmaps” and “1” means “use I/O bitmaps.” If the I/O 
bitmaps are used, the setting of the “uncon ditional I/O exiting” control is ignored.
27 Monitor trap flag If this control is 1, the monitor trap flag debugging feature is enabled. See Section 26.5.2.
28 Use MSR bitmaps This control determines whether MSR bitmaps are used to control execution of the RDMSR 
and WRMSR instructions (see Section 25.6.9 and Section 26.1.3).
For this control, “0” means “do not use MSR bitmaps” and “1” means “use MSR bitmaps.” If the 
MSR bitmaps are not used, all executions of the RDMSR and WRMSR instructions cause 
VM exits.
29 MONITOR exiting This control determines whether executions of MONITOR cause VM exits.30 PAUSE exiting This control determines whether executions of PAUSE cause VM exits.31 Activate secondary 
controlsThis control determines whether the secondar y processor-based VM-execution controls are 
used. If this control is 0, the logical processor operates as if all the secondary processor-based 
VM-execution controls were also 0.Table 25-6.  Definitions of Primary Proce ssor-Based VM-Execution Controls (Contd.)
Bit Position(s) Name Description25-12 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
the primary processor-based VM-execution controls do not support the secondary processor-based VM-execution 
controls.
Table 25-7 lists the secondary processor-based VM-execution controls. See Chapter 26 for more details of how 
these controls affect processor be havior in VMX non-root operation.
Table 25-7.  Definitions of Secondary Processor-Based VM-Execution Controls
0 Virtualize APIC 
accessesIf this control is 1, the logica l processor treats specially acce sses to the page with the APIC-
access address. Se e Section 30.4.
1 Enable EPT If this control is 1, extended page tables (EPT) are enabled. See Section 29.3.2D e s c r i p t o r - t a b l e  
exitingThis control determines whether executions of  LGDT, LIDT, LLDT, LTR, SGDT, SIDT, SLDT, and 
STR cause VM exits.
3 Enable RDTSCP If this control is 0, any execution of  RDTSCP causes an invali d-opcode exception (#UD).
4 Virtualize x2APIC 
modeIf this control is 1, the logi cal processor treats specially RDMSR and WRMSR to APIC MSRs (in 
the range 800H–8FFH). See Section 30.5.
5 Enable VPID If this control is 1, cached translations of linear addresses are associated with a virtual-
processor identifier (VPID). See Section 29.1.
6 WBINVD exiting This control determines whether executions of WBINVD and WBNOINVD cause VM exits.7 Unrestricted guest This control determines whether guest software may run in unpaged protected mode or in real-
address mode.
8A P I C - r e g i s t e r  
virtualizationIf this control is 1, the logica l processor virtualizes certain APIC accesses. See Section 30.4 and 
Section 30.5.
9V i r t u a l - i n t e r r u p t  
deliveryThis controls enables the evalua tion and delivery of pending virtual interrupts as well as the 
emulation of writes to the APIC register s that control interrupt prioritization.
10 PAUSE-loop exiting This control determines whether a series of executions of PAUSE can cause a VM exit (see 
Section 25.6.13 and Section 26.1.3).
11 RDRAND exiting This control determines whether executions of RDRAND cause VM exits.12 Enable INVPCID If this control is 0, any execution of INVPCID causes a #UD.13 Enable 
VM functionsSetting this control to 1 enables use of the VMFUNC instruction in VMX non-root operation. See 
Section 26.5.6.
14 VMCS shadowing If this control is 1, executions of VMREAD and VMWRITE in VMX non-root operation may access 
a shadow VMCS (instead of causing VM exits). See Section 25.10 and Section 31.3.
15 Enable ENCLS 
exitingIf this control is 1, executions of ENCLS consult the ENCLS-exiting bitmap to determine whether 
the instruction causes a VM exit. See Section 25.6.16 and Section 26.1.3.
16 RDSEED exiting This control determines wh ether executions of RDSEED cause VM exits.
17 Enable PML If this control is  1, an access to a guest-physical address that sets an EPT dirty bit first adds an 
entry to the page-modification log. See Section 29.3.6.
18 EPT-violation #VE If this control is 1, EPT violations may cause virtualization exceptions (#VE) instead of VM exits. 
See Section 26.5.7.
19 Conceal VMX from 
PTIf this control is 1, Intel Processor Trace suppre sses from PIPs an indica tion that the processor

PTIf this control is 1, Intel Processor Trace suppre sses from PIPs an indica tion that the processor 
was in VMX non-root operation and omits a VMCS packet from any PSB+ produced in VMX non-
root operation (see Chapter 33).
20 Enable 
XSAVES/XRSTORSIf this control is 0, any execution of XSAVES or XRSTORS causes a #UD.
21 PASID translation If this control is 1, PASID translation is performed for executions of ENQCMD and ENQCMDS. See 
Section 26.5.8.
22 Mode-based 
execute control for 
EPTIf this control is 1, EPT execute permissions are based on whether the linear address being 
accessed is supervisor mode or  user mode. See Chapter 29.Vol. 3C 25-13VIRTUAL MACHINE CONTROL STRUCTURES
All other bits in this field are reserved to 0. Softwa re should consult the VMX capability MSR IA32_VMX_PROC-
BASED_CTLS2 (see Appendix A.3.3) to determine which bits may be set to 1. Failure to clear reserved bits causes 
subsequent VM entries to fail (see Section 27.2.1.1).
Bit 17 of the primary processor-based VM-execution controls determines whether the tertiary processor-based 
VM-execution controls are used. If that bit is 0, VM entry and VMX non-root operation function as if all the tertiary 
processor-based VM-execution controls were 0. Processors that support only the 0-setting of bit 17 of the primary 
processor-based VM-execution controls do not support the tertiary processor-based VM-execution controls.
Table 25-8 lists the tertiary processor-based VM-execution  controls. See Chapter 26 for more details of how these 
controls affect processor behavior in VMX non-root operation.
BASED_CTLS3 (see Appendix A.3.4) to determine which bits may be set to 1. Failure to clear reserved bits causes 
subsequent VM entries to fail (see Section 27.2.1.1).23 Sub-page write 
permissions for 
EPTIf this control is 1, EPT write permissions may be specified at the granularity of 128 bytes. See 
Section 29.3.4.
24 Intel PT uses guest 
physical addressesIf this control is 1, all outp ut addresses used by Intel Processor Trace are treated as guest-
physical addresses and translated  using EPT. See Section 26.5.4.
25 Use TSC scaling This control determines whether executio ns of RDTSC, executions of RDTSCP, and executions 
of RDMSR that read from the IA32_TIME_STAMP_COUNTER MSR return a value modified by the 
TSC multiplier field (see Section 25.6.5 and Section 26.3).
26 Enable user wait 
and pauseIf this control is 0, any execution of TPAUSE, UMONITOR, or UMWAIT causes a #UD.
27 Enable PCONFIG If this control is 0, any execution of PCONFIG causes a #UD.
28 Enable ENCLV 
exitingIf this control is 1, executions of ENCLV consult the ENCLV-exiting bitmap to determine whether 
the instruction causes a VM exit. Se e Section 25.6.17 and Section 26.1.3.
30 VMM bus-lock 
detectionThis control determines whether assertion of a bus lock causes a VM exit. See Section 26.2.
31 Instruction timeout If this control is 1, a VM exit occurs if certain operations prevent the processor from reaching an 
instruction boundary within a specified amount of time. See Section 25.6.25 and Section 26.2.
Table 25-8.  Definitions of Tertiary Processor-Based VM-Execution Controls
0 LOADIWKEY exiting This control determines whether executions of LOADIWKEY cause VM exits.1 Enable HLAT This control enables hypervisor-managed linear-address translation. See Section 4.5.1.2 EPT paging-write 
controlIf this control is 1, EPT permissions can be specified to allow writes only for paging-related 
updates. See Section 29.3.3.2.
3G u e s t - p a g i n g  
verificationIf this control is 1, EPT permissions can be spec ified to prevent accesses using linear addresses 
whose translation has certain properties. See Section 29.3.3.2.
4 IPI virtualization If this control is 1, virtualization of interprocessor interrupts (IPIs) is enabled. See Section 
30.1.6.
7 Virtualize 
IA32_SPEC_CTRLIf this control is 1, the operation of the RDMSR and WRMSR instructions is changed when 
accessing the IA32_SPEC_CTRL MSR. See Section 26.3.Table 25-7.  Definitions of Secondary Proc essor-Based VM-Execution Controls (Contd.)
Bit Position(s) Name Description25-14 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
25.6.3 Exception Bitmap
The exception bitmap  is a 32-bit field that contains one bit for each exception. When an exception occurs, its 
vector is used to select a bit in this field. If the bit is 1, the exception causes a VM exit. If the bit is 0, the exception 
is delivered normally through the IDT, using the descriptor corresponding to the exception’s vector.
Whether a page fault (exception with vector 14) causes a VM exit is determined by bit 14 in the exception bitmap 
as well as the error code produced by the page  fault and two 32-bit fields in the VMCS (the page-fault error-code 
mask  and page-fault error-code match) . See Section 26.2 for details.
25.6.4 I/O-Bitmap Addresses
The VM-execution control fields include the 64-bit physical addresses of I/O bitmaps  A and B (each of which are 
4 KBytes in size). I/O bitmap A contains one bit for each  I/O port in the range 0000H through 7FFFH; I/O bitmap B 
contains bits for ports in the range 8000H through FFFFH.
A logical processor uses these bitmaps if and only if the “use I/O bitmaps” control is 1. If the bitmaps are used, 
execution of an I/O instruction causes a VM exit if any bit in the I/O bitmaps corresponding to a port it accesses is 
1. See Section 26.1.3 for details. If the bitmaps are used, their addresses must be 4-KByte aligned.
25.6.5 Time-Stamp Counter Offset and Multiplier
The VM-execution control fields include a 64-bit TSC-offset  field. If the “RDTSC exiting” control is 0 and the “use 
TSC offsetting” control is 1, this field controls executions  of the RDTSC and RDTSCP instructions. It also controls 
executions of the RDMSR instruction that read from th e IA32_TIME_STAMP_COUNTER MSR. For all of these, the 
value of the TSC offset is added to th e value of the time-stamp counter, and the sum is returned to guest software 
in EDX:EAX.
Processors that support the 1-setting of the “use TSC scaling” control also support a 64-bit TSC-multiplier  field. 
If this control is 1 (and the “RDTSC exiting” control is 0 and the “use TSC offsetting” control is 1), this field also 
affects the executions of the RDTSC, RDTSCP, and RDMSR in structions identified above. Specifically, the contents 
of the time-stamp counter is first multiplied by  the TSC multiplier before adding the TSC offset.
See Chapter 26 for a detailed treatment of the behavior of RDTSC, RDTSCP, and RDMSR in VMX non-root operation.
25.6.6 Guest/Host Masks and Re ad Shadows for CR0 and CR4
VM-execution control fields include guest/host masks  and read shadows  for the CR0 and CR4 registers. These 
fields control executions of instructions that access th ose registers (including CLTS, LMSW, MOV CR, and SMSW). 
They are 64 bits on processors that support Intel 64  architecture and 32 bits on processors that do not.
In general, bits set to 1 in a guest/host mask correspond to bits “owned” by the host:
•Guest attempts to set them (using CLTS, LMSW, or MOV to CR) to values differing from the corresponding bits 
in the corresponding read shadow cause VM exits.
•Guest reads (using MOV from CR or SMSW) return values  for these bits from the corresponding read shadow.
Bits cleared to 0 correspond to bits “owned” by the guest;  guest attempts to modify them succeed and guest reads 
return values for these bits from the control register itself.
See Chapter 28 for details regarding how thes e fields affect VMX non-root operation.
25.6.7 CR3-Target Controls
The VM-execution control fields include a set of 4 CR3-target values  and a CR3-target count . The CR3-target 
values each have 64 bits on processors that support Intel 64  architecture and 32 bits on processors that do not. The 
CR3-target count has 32 bits on all processors.Vol. 3C 25-15VIRTUAL MACHINE CONTROL STRUCTURES
An execution of MOV to CR3 in VMX non-root operation does not cause a VM exit if its source operand matches one 
of these values. If the CR3-target count is n, only the first n CR3-target values are considered; if the CR3-target 
count is 0, MOV to CR3 always causes a VM exit.
There are no limitations on the values that can be wri tten for the CR3-target values. VM entry fails (see Section 
27.2) if the CR3-target count is greater than 4.
Future processors may support a different number of CR3- target values. Software should read the VMX capability 
MSR IA32_VMX_MISC (see Appendix A.6) to de termine the number of values supported.
25.6.8 Controls for APIC Virtualization
There are three mechanisms by which software accesse s registers of the logical processor’s local APIC:
•If the local APIC is in xAPIC mode, it can perform me mory-mapped accesses to addresses in the 4-KByte page 
referenced by the physical address in the IA32_APIC_BA SE MSR (see Section 11.4.4, “Local APIC Status and

referenced by the physical address in the IA32_APIC_BA SE MSR (see Section 11.4.4, “Local APIC Status and 
Location,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, and the Intel® 64 
Architecture Processor Topology Enumeration Technical Paper).1
•If the local APIC is in x2APIC mode, it can accesse s the local APIC’s registers using the RDMSR and WRMSR 
instructions (see the Intel® 64 Architecture Processor Topology Enumeration Technical Paper).
•In 64-bit mode, it can access the local APIC’s task-priority register (TPR) using the MOV CR8 instruction.
Several processor-based VM-execution controls (see Section 25.6.2) control such accesses. These are “use TPR 
shadow”, “virtualize APIC accesses”, “vir tualize x2APIC mode”, “virtual-interrupt delivery”, “APIC-register virtual-
ization”, and “IPI virtualization”. These controls interact with the following fields:
•APIC-access address  (64 bits). This field contains the physical address of the 4-KByte APIC-access page . 
If the “virtualize APIC accesses” VM-execution control is 1, access to this page may cause VM exits or be 
virtualized by the processor. See Section 30.4.
The APIC-access address exists only on processors that support the 1-setting of the “virtualize APIC accesses” 
VM-execution control.
•Virtual-APIC address  (64 bits). This field contains the physical address of the 4-KByte virtual-APIC page . 
The processor uses the virtual-APIC page to virtualize certain accesses to APIC registers and to manage virtual 
interrupts; see Chapter 30.
Depending on the setting of the controls indicated ea rlier, the virtual-APIC page may be accessed by the 
— The MOV CR8 instructions (see Section 30.3).— Accesses to the APIC-access page if, in addition, the “virtualize APIC accesses” VM-execution control is 1 
(see Section 30.4).
— The RDMSR and WRMSR instructions if, in addition, th e value of ECX is in the range 800H–8FFH (indicating 
an APIC MSR) and the “virtualize x2APIC mode” VM-execution control is 1 (see Section 30.5).
If the “use TPR shadow” VM-execution control is 1, VM entry ensures that the virtual-APIC address is 4-KByte 
aligned. The virtual-APIC address exists only on proce ssors that support the 1-setting of the “use TPR shadow” 
•TPR threshold  (32 bits). Bits 3:0 of this field determine the threshold below which bits 7:4 of VTPR (see 
Section 30.1.1) cannot fall. If the “virtual-interrupt deliv ery” VM-execution control is 0, a VM exit occurs after 
an operation (e.g., an execution of MOV to CR8) that reduces the value of those bits below the TPR threshold. 
See Section 30.1.2.
The TPR threshold exists only on processors that supp ort the 1-setting of the “use TPR shadow” VM-execution 
control.
•EOI-exit bitmap  (4 fields; 64 bits each). These fields are su pported only on processors that support the 1-
setting of the “virtual-interrupt delivery” VM-execution control. They are used to determine which virtualized 
writes to the APIC’s EOI register cause VM exits:
1. If the local APIC does not support x2AP IC mode, it is always in xAPIC mode.25-16 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
— EOI_EXIT0 contains bits for vectors from 0 (bit 0) to 63 (bit 63).
— EOI_EXIT1 contains bits for vectors from 64 (bit 0) to 127 (bit 63).
— EOI_EXIT2 contains bits for vectors from 128 (bit 0) to 191 (bit 63).— EOI_EXIT3 contains bits for vectors from 192 (bit 0) to 255 (bit 63).
See Section 30.1.4 for more information on the use of this field.
•Posted-interrupt no tification vector  (16 bits). This field is supported only on processors that support the 1-
setting of the “process posted interrupts” VM-execution co ntrol. Its low 8 bits contain the interrupt vector that 
is used to notify a logical processor that virtual in terrupts have been posted. See Section 30.6 for more 
information on the use of this field.
•Posted-interrupt de scriptor address  (64 bits). This field is supported on ly on processors that support the 1-
setting of the “process posted interrupts” VM-execution control. It is the physical address of a 64-byte aligned posted interrupt descriptor. See Section 30.6 for more information on the use of this field.
•PID-pointer table address (64 bits). This field contains the physical address of the PID-pointer table . If the 
“IPI virtualization” VM-execution control is 1, the logical processor uses entries in this table to virtualize IPIs. 
See Section 30.1.6.
•Last PID-pointer index (16 bits). This field contains the index of the last entry in the PID-pointer table.
25.6.9 MSR-Bitmap Address
On processors that support the 1-setting  of the “use MSR bitmaps” VM-execution control, the VM-execution control 
fields include the 64-bit physical address of four contiguous MSR bitmaps , which are each 1-KByte in size. This 
field does not exist on processors that do not suppor t the 1-setting of that control. The four bitmaps are:
•Read bitmap for low MSRs  (located at the MSR-bitmap address) . This contains one bit for each MSR address 
in the range 00000000H to 00001FFFH. The bit determines  whether an execution of RDMSR applied to that 
MSR causes a VM exit.
•Read bitmap for high MSRs (located at the MSR-bitmap address plus 1024) . This contains one bit for each 
MSR address in the range C0000000H  toC0001FFFH. The bit determines whether an execution of RDMSR 
applied to that MSR causes a VM exit.
•Write bitmap for low MSRs (located at the MSR-bitmap address plus 2048) . This contains one bit for each 
MSR address in the range 00000000H to 00001FFFH. The bit determines whether an execution of WRMSR 
•Write bitmap for high MSRs (located at the MSR-bitmap address plus 3072) . This contains one bit for each 
MSR address in the range C0000000H  toC0001FFFH. The bit determines whether an execution of WRMSR 
A logical processor uses these bitmaps if and only if the “u se MSR bitmaps” control is 1. If the bitmaps are used, an 
execution of RDMSR or WRMSR causes a VM exit if the valu e of RCX is in neither of the ranges covered by the 
bitmaps or if the appropriate bit in the MSR bitmaps (corre sponding to the instruction and the RCX value) is 1. See 
Section 26.1.3 for details. If the bitmaps are used, their address must be 4-KByte aligned.
25.6.10 Executive-VMCS Pointer
The executive-VMCS pointer is a 64-bit field used in th e dual-monitor treatment of system-management interrupts 
(SMIs) and system-management mode (S MM). SMM VM exits save this field as described in Section 32.15.2. 
VM entries that return from SMM use this  field as described in Section 32.15.4.Vol. 3C 25-17VIRTUAL MACHINE CONTROL STRUCTURES
25.6.11 Extended-Page-Table Pointer (EPTP)
The extended-page-table pointer  (EPTP) contains the address of the base of EPT PML4 table (see Section 
29.3.2), as well as other EPT configuration information. The format of this field is shown in Table 25-9.
The EPTP exists only on processors that support th e 1-setting of the “enable EPT” VM-execution control.
25.6.12 Virtual-Processor Identifier (VPID)
The virtual-processor identifier (VPID) is a 16-bit field. It exists only  on processors that support the 1-setting 
of the “enable VPID” VM-execution control. See Sectio n 29.1 for details regarding the use of this field.
25.6.13 Controls for PAUSE-Loop Exiting
On processors that support the 1-setting of the “PAUSE -loop exiting” VM-execution control, the VM-execution 
control fields include the following 32-bit fields:
•PLE_Gap . Software can configure this field as an upper bound on the amount of time between two successive 
executions of PAUSE in a loop.
•PLE_Window . Software can configure this field as an upper bound on the amount of time a guest is allowed to 
execute in a PAUSE loop.
These fields measure time based on a counter that runs at the same rate as the timestamp counter (TSC). See 
Section 26.1.3 for more details regarding PAUSE-loop exiting.Table 25-9.  Format of Ex tended-Page-Table Pointer
Bit 
Position(s)Field
2:0 EPT paging-structure memory  type (see Section 29.3.7):
0 = Uncacheable (UC)
6=  W r i t e - b a c k  ( W B )
Other values are reserved.1
NOTES:
1. Software should read the VMX capability  MSR IA32_VMX_EPT_VPID_CAP (s ee Appendix A.10) to determine what EPT paging-struc-
ture memory types are supported.5:3 This value is 1 less than the EPT page-walk length (see Section 29.3.2)
6 Setting this control to 1 en ables accessed and dirty flags for EPT (see Section 29.3.5)2
2. Not all processors support accessed and dirty flags for EPT. Software should read  the VMX capability MSR IA32_VMX_EPT_VPID_-
CAP (see Appendix A.10) to determine whether the proces sor supports this feature.7 Setting this control to 1 enables enforcement of acce ss rights for supervisor shadow -stack pages (see Section 
29.3.3.2)3
3. Not all processors enforce access rights  for shadow-stack pages. Software shou ld read the VMX capability MSR IA32_VMX-

Bit 
NOTES:
_EPT_VPID_CAP (see Appendix A.10) to determine whether the processor supports this feature.11:8 Reserved
N–1:12 Bits N–1:12 of the physical address of the 4-KByte al igned EPT paging-structure (an EPT PML4 table with 4-level 
EPT and an EPT PML5 table with 5-level EPT)4
4. N is the physical-address width supported by the logical proc essor. Software can determine a processor’s ph ysical-address wi dth by 
executing CPUID with 80000008H in EAX. The physic al-address width is return ed in bits 7:0 of EAX.63:N Reserved25-18 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
25.6.14 VM-Function Controls
The VM-function controls constitute a 64-bit vector that governs use of the VMFUNC instruction in VMX non-root 
operation. This field is supported only  on processors that support the 1-settings of both the “activate secondary 
controls” primary processor-based VM-execution contro l and the “enable VM functions” secondary processor-
based VM-execution control.
Table 25-10 lists the VM-function controls. See Section 26 .5.6 for more details of how these controls affect 
processor behavior in VMX non-root operation.
All other bits in this field are reserved to 0. Softwa re should consult the VMX capability MSR IA32_VMX_VMFUNC 
(see Appendix A.11) to determine which bits are reserved. Failure to clear reserved bits causes subsequent 
VM entries to fail (see Section 27.2.1.1).
Processors that support the 1-setting of the “EPTP switchin g” VM-function control also support a 64-bit field called 
the EPTP-list address . This field contains the physical address of the 4-KByte EPTP list . The EPTP list comprises 
512 8-Byte entries (each an EPTP value) and is used by the EPTP-switching VM function (see Section 26.5.6.3).
25.6.15 VMCS Shadowing Bitmap Addresses
On processors that support the 1-setting of the “VMCS sh adowing” VM-execution control, the VM-execution control 
fields include the 64-bit physical addresses of the VMREAD bitmap  and the VMWRITE bitmap . Each bitmap is 4 
KBytes in size and thus contains 32 KBits. The addresses are the VMREAD-bitmap address  and the VMWRITE-
bitmap address .
If the “VMCS shadowing” VM-execution control is 1, executions of VMREAD and VMWRITE may consult these 
bitmaps (see Section 25.10 and Section 31.3).
25.6.16 ENCLS-Exiting Bitmap
The ENCLS-exiting bitmap  is a 64-bit field. If the “enable ENCLS exit ing” VM-execution control is 1, execution of 
ENCLS causes a VM exit if the bit in this field corresponding to the value of EAX is 1. If the bit is 0, the instruction 
executes normally. See Section 26.1.3 for more information.
25.6.17 ENCLV-Exiting Bitmap
The ENCLV-exiting bitmap  is a 64-bit field. If the “enable ENCLV exiting” VM-execution control is 1, execution of 
ENCLV causes a VM exit if the bit in this field corresponding to the value of EAX is 1. If the bit is 0, the instruction 
25.6.18 PCONFIG-Exiting Bitmap
The PCONFIG-exiting bitmap  is a 64-bit field. If the “enable PCONFIG” VM-execution control is 1, execution of 
PCONFIG causes a VM exit if the bit in this field correspondi ng to the value of EAX is 1. If the control is 0, any 
execution of PCONFIG causes a #UD. See Section 26.1.3 for more information.Table 25-10.  Definitions of VM-Function Controls
0 EPTP switching The EPTP-switching VM function changes th e EPT pointer to a value chosen from the EPTP list. 
See Section 26.5.6.3.Vol. 3C 25-19VIRTUAL MACHINE CONTROL STRUCTURES
25.6.19 Control Field for Page-Modification Logging
The PML address  is a 64-bit field. It is the 4-KByte aligned address of the page-modification log . The page-
modification log consists of 512 64-bit entries. It is us ed for the page-modification logging feature. Details of the 
page-modification logging are given in Section 29.3.6.
If the “enable PML” VM-execution control is 1, VM entry ensures that the PML address is 4-KByte aligned. The PML 
address exists only on processors that support the 1-setting of the “enable PML” VM-execution control.
25.6.20 Controls for Virtualization Exceptions
On processors that support the 1-setting of the “EPT-vi olation #VE” VM-execution control, the VM-execution 
control fields include the following:
•Virtualization-exception information address  (64 bits). This field contains the physical address of the 
virtualization-exception information area . When a logical processor encounters a virtualization exception, 
it saves virtualization-exception information at the vi rtualization-exception information address; see Section 
26.5.7.2.
•EPTP index  (16 bits). When an EPT violation causes a virtua lization exception, the processor writes the value 
of this field to the virtualization-exception information area. The EPTP-switching VM function updates this field 
(see Section 26.5.6.3).
25.6.21 XSS-Exiting Bitmap
On processors that support the 1-setting of the “enabl e XSAVES/XRSTORS” VM-executi on control, the VM-execu-
tion control fields include a 64-bit XSS-exiting bitmap . If the “enable XSAVES/XRSTORS” VM-execution control is 
1, executions of XSAVES and XRSTORS may consult this bitmap (see Section 26.1.3 and Section 26.3).
25.6.22 Sub-Page-Permission-Table Pointer (SPPTP)
If the sub-page write-permission feature of EPT is enab led, EPT write permissions may be determined at a 128-
byte granularity (see Section 29.3.4). These permissions are determined using a hierarchy of sub-page-permission 
structures in memory.
The root of this hierarchy is referenced by a VM-execution control field called the sub-page-permission-table 
pointer  (SPPTP). The SPPTP contains the address of the ba se of the root SPP table (see Section 29.3.4.2). The 
format of this field is shown in Table 25-9.
The SPPTP exists only on processors that support the 1- setting of the “sub-page write permissions for EPT” VM-
execution control.Table 25-11.  Format of Sub- Page-Permission-Table Pointer
Bit 
11:0 Reserved
N–1:12 Bits N–1:12 of the physical address of the 4-KByte aligned root SPP table
63:N1
NOTES:
1. N is the processor’s physical-address width. Software can determine this width by executing CPUID with 80000008H in EAX. The  
physical-address width is returned in bits 7:0 of EAX.Reserved25-20 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
25.6.23 Fields Related to Hypervisor -Managed Linear-Address Translation
Two fields are used when the “enable HLAT” VM-execution control is 1, enabling HLAT paging:
•The hypervisor-managed linear-ad dress translation pointer  (HLAT pointer or HLATP) is used by HLAT 
paging to locate and access the first paging structure used for linear-address translation (see Section 4.5). The 
format of this field is shown in Table 25-12.
•The HLAT prefix size. The value of this field determines  which linear address are subject to HLAT paging. See 
Section 4.5.1.
These fields exist only on processors that support th e 1-setting of the “enable HLAT” VM-execution control.
25.6.24 Fields Related to PASID Translation
Two 64-bit VM-execution control fields are used when th e “PASID translation” VM-execution control is 1, enabling 
translation of PASIDs for executions of ENQCMD and ENQCMDS: the low PASID directory address  and the high 
PASID directory address . These are the physical addresses of the lo w PASID directory and the high PASID direc-
tory, respectively. These fields exist only on processors that support the 1-setting of the “PASID translation” VM-
execution control.
See Section 26.5.8 for information on the PASI D-translation process for ENQCMD and ENQCMDS.
25.6.25 Instruction-Timeout Control
On processors that support the 1-setting of the “instruc tion timeout” VM-execution control, the VM-execution 
control fields include a 32-bit instruction-timeout control . The processor interprets the value of this field as an 
amount of time as measured in units of crystal clock cycles.1 If the “instruction timeout” VM-execution control is 1, 
a VM exit occurs if certain operations prevent the processor from reaching an instruction boundary within this 
amount of time.Table 25-12.  Format of Hypervisor-Man aged Linear-Address Translation Pointer
Bit 
2:0 Reserved
3 (PWT) Page-level write-through; indirectly determines the memory type used to access the first HLAT paging structure 
during linear-add ress translation.
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access the first HLAT paging structure 
11:5 ReservedN–1:12 Guest-physical address (4KB-aligned) of the first HLAT paging structure during  linear-addre ss translation.
1
NOTES:
1. N is the physical-address width supported by the logical pr ocessor. Software can determine a processor’s physical-address wi dth by 
executing CPUID with 80000008H in EAX. The physical-address width is returned in bits 7:0 of EAX.63:N Reserved

Bit 
1
NOTES:
1. CPUID.15H:ECX enumerates the nominal frequency of the core crystal clock in Hz.Vol. 3C 25-21VIRTUAL MACHINE CONTROL STRUCTURES
25.6.26 Fields Controlling Virtualization of the IA32_SPEC_CTRL MSR
On processors that support the 1-setting of the “virtua lize IA32_SPEC_CTRL” VM-execution control, the VM-execu-
tion control fields include the following 64-bit fields:
•IA32_SPEC_CTRL mask.  Setting a bit in this field prevents gues t software from modifying the corresponding 
bit in the IA32_SPEC_CTRL MSR.
•IA32_SPEC_CTRL shadow.  This field contains the value that guest software expects to be in the 
IA32_SPEC_CTRL MSR.
Section 26.3 discusses how these fields are used in VMX non-root operation.
25.7 VM-EXIT CONTROL FIELDS
The VM-exit control fields govern the behavior of VM exits. They are discussed in Section 25.7.1 and Section 
25.7.2.
25.7.1 VM-Exit Controls
The VM-exit controls constitute two vectors that go vern the basic operation of VM exits. These are the primary 
VM-exit controls  (32 bits) and the secondary VM-exits controls  (64 bits).
Table 25-13 lists the primary VM-exit controls. See Chapte r 28 for complete details of how these controls affect 
VM exits. 
Table 25-13.  Definitions of Primary VM-Exit Controls
2 Save debug controls This control determines whet her DR7 and the IA32_DEBUGCTL MSR are saved on 
VM exit.
The first processors to supp ort the virtual-machine extens ions supported only the 1-
setting of this control.
9 Host address-space size On processors  that support Intel 64 architecture, this contro l determines whether a 
logical processor is in 64-bit mode after the next VM exit. Its value is loaded into CS.L, 
IA32_EFER.LME, and IA32_EFER.LMA on every VM exit.1
This control must be 0 on processors that do not support Intel 64 architecture.
12 Load 
IA32_PERF_GLOBAL_CTRLThis control determines whether the IA 32_PERF_GLOBAL_CTRL MSR is loaded on 
VM exit.
15 Acknowledge interrupt on 
exitThis control affects VM exits due to external  interrupts:
• If such a VM exit occurs and this control is  1, the logical proces sor acknowledges the 
interrupt controller, acquiring the interrupt’s vector. The vector is stored in the 
VM-exit interruption-i nformation field, which is marked valid.
• If such a VM exit occurs and this control is 0, the interrupt is not acknowledged and 
the VM-exit interrupti on-information field is marked invalid.
18 Save IA32_PAT This control determines whether the IA32_PAT MSR is saved on VM exit.19 Load IA32_PAT This control determines whether the IA32_PAT MSR is loaded on VM exit.
20 Save IA32_EFER This control determines whether the IA32_EFER MSR is saved on VM exit.
21 Load IA32_EFER This control determines whether the IA32_EFER MSR is loaded on VM exit.22 Save VMX-preemption 
timer valueThis control determines whether the value of the VMX-preemption timer is saved on 
VM exit.
23 Clear IA32_BNDCFGS This control determines whether the IA32_BNDCFGS MSR is cleared on VM exit.
24 Conceal VMX from PT If this control is 1, Intel Proce ssor Trace does not produce a paging information packet 
(PIP) on a VM exit or a VMCS packet on an SMM VM exit (see Chapter 33).25-22 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
IA32_VMX_EXIT_CTLS and IA32_VMX_TRUE_EXIT_CTLS (see Ap pendix A.4) to determine how it should set the 
reserved bits. Failure to set reserved bits properly ca uses subsequent VM entries to fail (see Section 27.2.1.2).
The first processors to support the virtual-machine extens ions supported only the 1-settings of bits 0–8, 10, 11, 
13, 14, 16, and 17. The VMX capability MSR IA32_VMX_EXI T_CTLS always reports that these bits must be 1. 
_TRUE_EXIT_CTLS MSR, and software should consult this MSR to discover support for the 0-settings of these bits. 
Software that is not aware of the functionality of any one of these bits should set that bit to 1.
Bit 31 of the primary processor-based VM-exit controls determines whether the secondary VM-exit controls are 
used. If that bit is 0, VM entries and VM exits function as if all the secondary VM-exit controls were 0. Processors 
that support only the 0-setting of bit 31 of the primar y VM-exit controls do not support the secondary VM-exit 
controls.
Table 25-14 lists the secondary VM-exit controls. See Chap ter 28 for more details of how these controls affect 
VM exits.
All other bits in this field are reserved to 0. Software should consult the VMX capability MSR IA32_VMX_EX-
IT_CTLS2 (see Appendix A.4.2) to determine which bits ma y be set to 1. Failure to clear reserved bits causes 
subsequent VM entries to fail (see Section 27.2.1.2).
25.7.2 VM-Exit Controls for MSRs
A VMM may specify lists of MSRs to be stored and loaded  on VM exits. The following VM-exit control fields deter-
mine how MSRs are stored on VM exits:
•VM-exit MSR-store count  (32 bits).  This field specifies the number of MSRs to be stored on VM exit. It is 
recommended that this count not exceed 512.1 Otherwise, unpredictable processor behavior (including a 
machine check) may result during VM exit.25 Clear IA32_RTIT_CTL This control determines whet her the IA32_RTIT_CTL MSR is cleared on VM exit.
26 Clear IA32_LBR_CTL This control determines whet her the IA32_LBR_CTL MSR is cleared on VM exit.
27 Clear UINV This control determines whether UINV is cleared on VM exit.
28 Load CET state This control determines whether CET-related MSRs and SSP are loaded on VM exit.29 Load PKRS This control determines whether the IA32_PKRS MSR is loaded on VM exit.
30 Save 
IA32_PERF_GLOBAL_CTLThis control determines whether the IA32 _PERF_GLOBAL_CTL MSR is saved on VM 
exit.
31 Activate secondary 
controlsThis control determines whether the second ary VM-exit controls are used. If this 
control is 0, the logica l processor operates as if all th e secondary VM-exi t controls were 
also 0.
NOTES:
1. Since the Intel 64 architecture specifies that IA32_EFER.LMA is always  set to the logical-AND of CR0.PG and IA32_EFER.LME, a nd 
since CR0.PG is always 1 in VMX root op eration, IA32_EFER.LMA is always identical to IA32_EFER.LME in VMX root operation.
Table 25-14.  Definitions of  Secondary VM-Exit Controls
3P r e m a t u r e l y  b u s y  
shadow stackIf this control is 1, VM exits that cause a shadow stack to become prematurely busy (see 
Section 17.2.3, “Supervisor Shadow Stack Token,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 1) indicate this fact and save additional information into the VMCS.Table 25-13.  Definitions of Pr imary VM-Exit Controls (Contd.)
Bit Position(s) Name DescriptionVol. 3C 25-23VIRTUAL MACHINE CONTROL STRUCTURES
•VM-exit MSR-store address  (64 bits). This field contains the physical address of the VM-exit MSR-store area. 
The area is a table of entries, 16 bytes per entry, wh ere the number of entries is given by the VM-exit MSR-
store count. The format of each entry is given in Table 25-15. If the VM-exit MSR-store count is not zero, the 
address must be 16-byte aligned.
See Section 28.4 for how this area is used on VM exits.
The following VM-exit control fields determine how MSRs are loaded on VM exits:
•VM-exit MSR-load count  (32 bits).  This field contains the number of MSRs to be loaded on VM exit. It is 
recommended that this count not exceed 512. Otherwis e, unpredictable processor behavior (including a 
machine check) may result during VM exit.1
•VM-exit MSR-load address  (64 bits).  This field contains the physical address of the VM-exit MSR-load area. 
The area is a table of entries, 16 bytes per entry, wher e the number of entries is given by the VM-exit MSR-load 
count (see Table 25-15). If the VM-exit MSR-load count  is not zero, the address must be 16-byte aligned.
See Section 28.6 for how this area is used on VM exits.
25.8 VM-ENTRY CONTROL FIELDS
The VM-entry control fields govern th e behavior of VM entries. They are discussed in Sections 25.8.1 through 
25.8.3.
25.8.1 VM-Entry Controls
The VM-entry controls  constitute a 32-bit vector that governs the basic operation of VM entries. Table 25-16 lists 
the controls supported. See Chapter 25 for how these controls affect VM entries.
1. Future implementa tions may allow more MSRs to be st ored reliably. Software should cons ult the VMX capability MSR IA32_VMX_-
MISC to determine the number supported (see Appendix A.6).Table 25-15.  Format of an MSR Entry
Bit Position(s) Contents
31:0 MSR index63:32 Reserved127:64 MSR data
1. Future implementa tions may allow more MSRs to  be loaded reliably. Soft ware should consult the VM X capability MSR IA32_VMX_-
MISC to determine the number supported (see Appendix A.6).Table 25-16.  Definition s of VM-Entry Controls
2 Load debug

25.8.3.
2 Load debug 
controlsThis control determines whether DR7 and th e IA32_DEBUGCTL MSR are loaded on VM entry.
The first processors to support the virtual-mach ine extensions supported only the 1-setting of 
this control.
9 IA-32e mode guest On processors that support Intel 64 ar chitecture, this co ntrol determines whether the logical 
processor is in IA-32e mode afte r VM entry. Its value is loaded into IA32_EFER.LMA as part of 
VM entry.1
10 Entry to SMM This control determines whether the lo gical processor is in syst em-management mode (SMM) 
after VM entry. This control must be  0 for any VM entry from outside SMM.
11 Deactivate dual-
monitor treatmentIf set to 1, the de fault treatment of SMIs and SMM is in effect after the VM entry (see Section 
32.15.7). This control must be 0 for any VM entry from outside SMM.25-24 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
IA32_VMX_ENTRY_CTLS and IA32_VMX_TRUE_ENTRY_CTLS (s ee Appendix A.5) to determine how it should set 
the reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail (see Section 27.2.1.3).
The first processors to support the virtual-machine exte nsions supported only the 1-settings of bits 0–8 and 12. 
The VMX capability MSR IA32_VMX_ENTRY_CTLS always reports that these bits must be 1. Logical processors that 
support the 0-settings of any of these bits will su pport the VMX capability MSR IA32_VMX_TRUE_ENTRY_CTLS 
MSR, and software should consult this MSR to discover supp ort for the 0-settings of these bits. Software that is not 
aware of the functionality of any one of these bits should set that bit to 1.
25.8.2 VM-Entry Controls for MSRs
A VMM may specify a list of MSRs to be loaded on VM entr ies. The following VM-entry control fields manage this 
functionality:
•VM-entry MSR-load count  (32 bits). This field contains the number of MSRs to be loaded on VM entry. It is 
recommended that this count not exceed 512. Otherw ise, unpredictable processor behavior (including a 
machine check) may result during VM entry.1
•VM-entry MSR-load address  (64 bits). This field contains the physical address of the VM-entry MSR-load 
area. The area is a table of entries, 16 bytes per entry,  where the number of entries is given by the VM-entry 
MSR-load count. The format of entries is described in Ta ble 25-15. If the VM-entry MSR-load count is not zero, 
the address must be 16-byte aligned.
See Section 27.4 for details of how this area is used on VM entries.
25.8.3 VM-Entry Controls for Event Injection13 Load 
IA32_PERF_GLOBA
L_CTRLThis control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry.
14 Load IA32_PAT This control determines whether the IA32_PAT MSR is loaded on VM entry.
15 Load IA32_EFER This control determines whether the IA32_EFER MSR is loaded on VM entry.16 Load 
IA32_BNDCFGSThis control determines whether the IA32_BNDCFGS MSR is loaded on VM entry.
17 Conceal VMX from 
PTIf this control is 1, Intel Processor Trace does not produce a paging information packet (PIP) on 
a VM entry or a VMCS packet on a VM entry that returns from SMM (see Chapter 33).
18 Load 
IA32_RTIT_CTLThis control determines whether the IA32_RTIT_CTL MSR is loaded on VM entry.
19 Load UINV This control determines whether UINV is lo aded on VM entry.
20 Load CET state This control determines whether CET-related MSRs and SSP are loaded on VM entry.21 Load guest 
IA32_LBR_CTLThis control determines whether the IA32_LBR_CTL MSR is loaded on VM entry.
22 Load PKRS This control determines whethe r the IA32_PKRS MSR is loaded on VM entry.
NOTES:
1. Bit 5 of the IA32_VMX_MISC MSR is read as 1 on any logical processor that su pports the 1-setting of the “unrestricted guest”  VM-
execution control. If it is read as 1, every VM exit stores the value of IA32_EFER.LMA into the “IA-32e mode guest” VM-entry con trol 
(see Section 28.2).
MISC to determine the number supported (see Appendix A.6).Table 25-16.  Definitions of VM-Entry Controls (Contd.)
Bit Position(s) Name DescriptionVol. 3C 25-25VIRTUAL MACHINE CONTROL STRUCTURES
VM entry can be configured to conclude by delivering an event through the IDT (after all guest state and MSRs have 
been loaded). This process is called event injection  and is controlled by the following three VM-entry control 
fields:
•VM-entry interruption-information field  (32 bits). This field provides details about the event to be injected. 
Table 25-17 describes the field.
—T h e  vector  (bits 7:0) determines which entry in the IDT is used or which other event is injected.
—T h e  interruption type  (bits 10:8) determines details of how the injection is performed. In general, a VMM 
should use the type hardware exception for all exceptions other than the following:
•breakpoint exceptions (#BP; a VMM should use the type software exception);
•overflow exceptions (#OF a VMM should us e the use type software exception); and
•those debug exceptions (#DB) that are generated by  INT1 (a VMM should use the use type privileged 
software exception).1
The type other event  is used for injection of events that are not delivered through the IDT.2
—F o r  e x c e p t i o n s ,  t h e  deliver-error-code bit  (bit 11) determines whether delivery pushes an error code on 
the guest stack.
— VM entry injects an event if and only if the valid bit  (bit 31) is 1. The valid bit in this field is cleared on 
every VM exit (see Section 28.2).
•VM-entry exception error code  (32 bits). This field is used if and only if the valid bit (bit 31) and the deliver-
error-code bit (bit 11) are both set in th e VM-entry interruption-information field.
•VM-entry instruction length  (32 bits). For injection of events whose type is software interrupt, software 
exception, or privileged software exception, this field is  used to determine the value of RIP that is pushed on 
the stack.
See Section 27.6 for details regarding the mechanics of ev ent injection, including the use of the interruption type 
and the VM-entry instruction length.
VM exits clear the valid bit (bit 31) in the VM-entry interruption-information field.
25.9 VM-EXIT INFORMATION FIELDS
The VMCS contains a section of fields that contain information about the most recent VM exit.Table 25-17.  Format of the VM- Entry Interruption-Information Field
Bit Position(s) Content
7:0 Vector of interrupt or exception10:8 Interruption type:
0: External interrupt
1: Reserved2: Non-maskable interrupt (NMI)
3: Hardware exception (e.g,. #PF)
4: Software interrupt (INT n)
5: Privileged software exception (INT1)
6: Software exception (INT3 or INTO)
7: Other event
11 Deliver error code (0 = do not deliver; 1 = deliver)30:12 Reserved31 Valid
1. The type hardware exception should be used for all other debug exceptions.
2. INT1 and INT3 refer to the instructions with opcodes F1 and CC, respectively, and not to INT n with values 1 or 3 for n.25-26 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
On some processors, attempts to write to these fields with VMWRITE fail (see “VMWRITE—Write Field to Virtual-
Machine Control Structure” in Chapter 31).1
25.9.1 Basic VM-Exit Information
The following VM-exit information fields provide basic information about a VM exit:
•Exit reason  (32 bits). This field encodes the reason for th e VM exit and has the structure given in Table 25-18.
— Bits 15:0 provide basic information about the cause of the VM exit (if bit 31 is clear) or of the VM-entry 
failure (if bit 31 is set). Appendix C enumerates the basic exit reasons.
— Bit 16 is always cleared to 0.— Bit 25 is set to 1 if the “prematurely busy shadow stack” VM-exit control is 1 and the VM exit caused a 
shadow stack to become prematurely busy (see Section 26.4.3). Otherwise, the bit is cleared.
— Bit 26 is set to 1 if the VM exit occurred after assertio n of a bus lock while the “V MM bus-lock detection” VM-
execution control was 1. Such VM exits include those that  occur due to the 1-setting of that control as well 
as others that might occur during execution of an instruction that asserted a bus lock.
— Bit 27 is set to 1 if the VM exit occurred while the logical processor was in enclave mode.
A VM exit also sets this bit if it is incident to delivery of an event injected by VM entry and the guest inter-
ruptibility-state field indicates an enclave interrupt (bit  4 of the field is 1). See Section 28.2.1 for details.
— Bit 28 is set only by an SMM VM exit (see Section 32. 15.2) that took priority over an MTF VM exit (see 
Section 26.5.2) that would have occurred had th e SMM VM exit not occurred. See Section 32.15.2.3.
— Bit 29 is set if and only if the processor was in VMX root operation at the time the VM exit occurred. This can

— Bit 29 is set if and only if the processor was in VMX root operation at the time the VM exit occurred. This can 
happen only for SMM VM exits. See Section 32.15.2.
— Because some VM-entry failures load processor state from the host-state area (see Section 27.8), software 
must be able to distinguish such cases from true VM exits. Bit 31 is used for that purpose.
•Exit qualification  (64 bits; 32 bits on processors that do not support Intel 64 architecture). This field contains 
additional information about the cause of VM exits due to the following: debug exceptions; page-fault 
exceptions; start-up IPIs (SIPIs); task switches; IN VEPT; INVLPG;INVVPID; LGDT; LIDT; LLDT; LTR; SGDT; 
SIDT; SLDT; STR; VMCLEAR; VMPTRLD; VMPTRST; VMREAD; VMWRITE; VMXON; XRSTORS; XSAVES; control-
1.  Software can discover whether these fields can be written by reading the VMX capability MSR IA32_VMX_MISC (see Appendix A.6) .Table 25-18.  Format of Exit Reason
15:0 Basic exit reason.
16 Always cleared to 0.24:17 Not currently defined.25 A VM exit saves this bit as 1 to in dicate that the VM exit caused a shadow stack to become prematurely busy.
26 A VM exit saves this bit as 1 to indi cate that the VM exit occu rred after assertion of a bus lock while the “VMM 
bus-lock detection” VM-e xecution control was 1.
27 A VM exit saves this bit as 1 to indicate th at the VM exit was incident to enclave mode.
28 Pending MTF VM exit.29 VM exit from VMX root operation.
30 Not currently defined.
31 VM-entry failure (0 = true VM exit; 1 = VM-entry failure)Vol. 3C 25-27VIRTUAL MACHINE CONTROL STRUCTURES
register accesses; MOV DR; I/O instructions; and MWAIT. The format of the field depends on the cause of the 
VM exit. See Section 28.2.1 for details.
•Guest-linear address  (64 bits; 32 bits on processors that do no t support Intel 64 architecture). This field is 
used in the following cases:
— VM exits due to attempts to execute LMSW with a memory operand.— VM exits due to attempts to execute INS or OUTS.
— VM exits due to system-management interrupts (SMIs) that arrive immediately after retirement of I/O 
— Certain VM exits due to EPT violations
See Section 28.2.1 and Section 32.15.2.3 for de tails of when and how this field is used.
•Guest-physical address  (64 bits). This field is used by VM exits due to EPT violations and EPT misconfigura-
tions. See Section 28.2.1 for details of  when and how this field is used.
25.9.2 Information for VM Exits Due to Vectored Events
Event-specific information is provided for VM exits due to  the following vectored events: exceptions (including 
those generated by the instructions INT3, INTO, INT1, BOUN D, UD0, UD1, and UD2); exte rnal interrupts that occur 
while the “acknowledge interrupt on exit” VM-exit control is 1; and non-maskable interrupts (NMIs). This informa-
tion is provided in the following fields:
•VM-exit interruption information  (32 bits). This field receives basic information associated with the event 
causing the VM exit. Table 25-19 describes this field.
•VM-exit interruption error code  (32 bits). For VM exits caused by hardware exceptions that would have 
delivered an error code on the stack, this field receives that error code.
Section 28.2.2 provides details of ho w these fields are saved on VM exits.
25.9.3 Information for VM Exits That Occur During Event Delivery
Additional information is provided for VM exits that occur during event delivery in VMX non-root operation.1 This 
information is provided in the following fields:Table 25-19.  Format of the VM-E xit Interruption-Information Field
1: Not used
2: Non-maskable interrupt (NMI)
3: Hardware exception4: Not used
5: Privileged software exception
6: Software exception7: Not used
11 Error code valid (0 = invalid; 1 = valid)12 NMI unblocking due to IRET30:13 Not currently defined31 Valid
1. This includes cases in which the event delivery was caused by event injection as part of VM entry; see Section 27.6.1.2.25-28 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
•IDT-vectoring information  (32 bits). This field receives basic information associated with the event that was 
being delivered when the VM exit occurre d. Table 25-20 describes this field.
•IDT-vectoring error code  (32 bits). For VM exits the occur during delivery of hardware exceptions that would 
have delivered an error code on the stack, this field receives that error code.
See Section 28.2.4 provides details of how these fields are saved on VM exits.
25.9.4 Information for VM Exits Due to Instruction Execution
The following fields are used for VM exits caused by attemp ts to execute certain instructions in VMX non-root oper-
ation:
•VM-exit instruction length  (32 bits). For VM exits resulting from inst ruction execution, this field receives the 
length in bytes of the instruction whose execution led to the VM exit.1 See Section 28.2.5 for details of when 
and how this field is used.
•VM-exit instruction information  (32 bits). This field is used for VM exits due to attempts to execute INS, 
INVEPT, INVVPID, LIDT, LGDT, LLDT, LTR, OUTS, SIDT, SGDT, SLDT, STR, VMCLEAR, VMPTRLD, VMPTRST, VMREAD, VMWRITE, or VMXON.
2 The format of the field depends on the cause of the VM exit. See Section 
28.2.5 for details.
The following fields (64 bits each; 32 bits on processors that do not support Intel 64 architecture) are used only for 
VM exits due to SMIs that arrive immediately after retire ment of I/O instructions. They provide information about 
that I/O instruction:
•I/O RCX . The value of RCX before the I/O instruction started.
•I/O RSI . The value of RSI before the I/O instruction started.
•I/O RDI . The value of RDI before the I/O instruction started.
•I/O RIP . The value of RIP before the I/O instruction started (the RIP that addressed the I/O instruction).Table 25-20.  Format of the IDT-Vectoring Information Field
1: Not used
3: Hardware exception4: Software interrupt
11 Error code valid (0 = invalid; 1 = valid)
30:12 Not currently defined
31 Valid
1. This field is also used for VM exits that occur during the delivery of a software interrupt or software exception.
2. Whether the processor provides this information on VM exits due to attempts to execute INS or OUTS can be determined by consul t-
ing the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1).Vol. 3C 25-29VIRTUAL MACHINE CONTROL STRUCTURES
25.9.5 VM-Instruction Error Field
The 32-bit VM-instruction error field  does not provide information about the most recent VM exit. In fact, it is 
not modified on VM exits. Instead, it provides informatio n about errors encountered by a non-faulting execution of 
one of the VMX instructions.
25.10 VMCS TYPES: ORDINARY AND SHADOW
Every VMCS is either an ordinary VMCS  or a shadow VMCS . A VMCS’s type is determined by the shadow-VMCS 
indicator in the VMCS region (this is the value of bit 31 of the first 4 bytes of the VMCS region; see Table 25-1): 0 
indicates an ordinary VMCS, while 1 indicates a shadow VMCS. Shadow VMCSs are supported only on processors 
that support the 1-setting of the “VMCS shadowin g” VM-execution control (see Section 25.6.2).
A shadow VMCS differs from an  ordinary VMCS in two ways:
•An ordinary VMCS can be used for VM entry but a shad ow VMCS cannot. Attempts to perform VM entry when 
the current VMCS is a shadow VMCS fail (see Section 27.1).
•The VMREAD and VMWRITE instructions can be used in VMX non-root operation to access a shadow VMCS but 
not an ordinary VMCS. This fact results from the following:
— If the “VMCS shadowing” VM-execution control is 0, execution of the VMREAD an d VMWRITE instructions in 
VMX non-root operation always cause VM exits (see Section 26.1.3).
— If the “VMCS shadowing” VM-execution control is 1, execution of the VMREAD an d VMWRITE instructions in 
VMX non-root operation can access the VMCS referenc ed by the VMCS link pointer (see Section 31.3).
— If the “VMCS shadowing” VM-execution control is 1,  VM entry ensures that any VMCS referenced by the 
VMCS link pointer is a shadow VMCS (see Section 27.3.1.5).
In VMX root operation, both types of VMCSs can be  accessed with the VMREAD and VMWRITE instructions.
Software should not modify the shadow-VMCS indicator in th e VMCS region of a VMCS that is active. Doing so may 
cause the VMCS to become corrupted (see Section 25.11.1) . Before modifying the shadow-VMCS indicator, soft-
ware should execute VMCLEAR for the VMCS  to ensure that it is not active.
25.11 SOFTWARE USE OF THE VMCS AND RELATED STRUCTURES
This section details guidelines that software should ob serve when using a VMCS and related structures. It also 
provides descriptions of consequences for failing to follow guidelines.
25.11.1 Software Use of Virtual-Machine Control Structures

To ensure proper processor behavior, software should observe certain guidelines when using an active VMCS.
No VMCS should ever be active on more than one logical processor. If a VMCS is to be “migrated” from one logical 
processor to another, the first logical processor should execute VMCLEAR for the VMCS (to make it inactive on that 
logical processor and to ensure that all VMCS data are in memory) before the other logical processor executes 
VMPTRLD for the VMCS (to make it active on the second logical processor).1 A VMCS that is made active on more 
than one logical processor may become corrupted  (see below).
Software should not modify the shadow-VMCS indicator (see  Table 25-1) in the VMCS region of a VMCS that is 
active. Doing so may cause the VMCS to become corrupted . Before modifying the shadow-VMCS indicator, software 
should execute VMCLEAR for the VMCS to ensure that it is not active.
Software should use the VMREAD and VMWRITE instructions to access the different fields in the current VMCS (see 
Section 25.11.2). Software should never access or modify  the VMCS data of an ac tive VMCS using ordinary 
1. As noted in Section 25.1, execution of the VMPTRLD instruction makes a VMCS is active. In addition, VM entry makes active any 
shadow VMCS referenced by the VM CS link pointer in the current VMCS. If a shadow VMCS is made active by  VM entry, it is neces-
sary to execute VMCLEAR for that VMCS before allowing that VMCS to become active on another logical processor.25-30 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
memory operations, in part because the format used to store the VMCS data is implementation-specific and not 
architecturally defined, and also because a logical processo r may maintain some VMCS data of an active VMCS on 
the processor and not in the VMCS region. The following it ems detail some of the hazards of accessing VMCS data 
using ordinary memory operations:
•Any data read from a VMCS with an ordinary memory read does not reliably refl ect the state of the VMCS. 
Results may vary from time to time or from logical processor to logical processor.
•Writing to a VMCS with an ordinary memory write is not guaranteed to have a deterministic effect on the VMCS. 
Doing so may cause the VMCS to become corrupted (see below).
(Software can avoid these hazards by removing any linear -address mappings to a VMCS region before executing a 
VMPTRLD for that region and by not remapping it  until after executing VMCLEAR for that region.)
If a logical processor leaves VMX operation, any VMCSs active on that logical processor may be corrupted (see 
below). To prevent such corruption of a VMCS that may be  used either after a return to VMX operation or on 
another logical processor, software should execute VMCL EAR for that VMCS before executing the VMXOFF instruc-
tion or removing power from the processor (e.g., as part of a transition to the S3 and S4 power states).
This section has identified operations that may cause a VMCS to become corrupted. These operations may cause 
the VMCS’s data to become undefined. Behavior may be unpredictable if that VMCS used subsequently on any 
logical processor. The following items detail some hazards of VMCS corruption:
•VM entries may fail for unexplained reasons or may load undesired processor state.
•The processor may not correctly support VMX non-root  operation as documented in Chapter 26 and may 
generate unexpected VM exits.
•VM exits may load undesired processor state, save incorrect state into the VMCS, or cause the logical processor to transition to a shutdown state.
25.11.2 VMREAD, VMWRITE, and Encodings of VMCS Fields
Every field of the VMCS is associated with a 32-bit value that is its encoding . The encoding is provided in an 
operand to VMREAD and VMWRITE when software wishes to read or write that field. These instructions fail if given, 
in 64-bit mode, an operand that sets an encoding bit be yond bit 32. See Chapter 31 for a description of these 
The structure of the 32-bit encodings of the VMCS componen ts is determined principally by the width of the fields 
and their function in the VMCS. See Table 25-21.
Table 25-21.  Structure of VMCS Component Encoding
0 Access type (0 = full; 1 = high); must be fu ll for 16-bit, 32-bit, and natural-width fields
9:1 Index
11:10 Type:
0: control
1: VM-exit information
2: guest state3: host state
12 Reserved (must be 0)14:13 Width:
0: 16-bit
1: 64-bit
2: 32-bit
3: natural-width
31:15 Reserved (must be 0)Vol. 3C 25-31VIRTUAL MACHINE CONTROL STRUCTURES
The following items detail the meaning of the bits in each encoding:
•Field width.  Bits 14:13 encode the width of the field.
— A value of 0 indicates a 16-bit field.
— A value of 1 indicates a 64-bit field.— A value of 2 indicates a 32-bit field.
— A value of 3 indicates a natural-width  field. Such fields have 64 bits on processors that support Intel 64 
architecture and 32 bits on processors that do not.
Fields whose encodings use value 1 are specially treated to allow 32-bit software access to all 64 bits of the 
field. Such access is allowed by defining, for each such fi eld, an encoding that allows direct access to the high 
32 bits of the field. See below.
•Field type.  Bits 11:10 encode the type of VM CS field: control, guest-state, host-state, or VM-exit information. 
(The last category also includes the VM-instruction error field.)
•Index. Bits 9:1 distinguish components with the same field width and type.
•Access type. Bit 0 must be 0 for all fields except for 64-bit fields (those with field-width 1; see above). A 
VMREAD or VMWRITE using an encoding with this bit cleared to 0 accesses the entire field. For a 64-bit field 
with field-width 1, a VMREAD or VMWRITE using an encoding  with this bit set to 1 accesses only the high 32 bits 
of the field.
Appendix B gives the encodings of all fields in the VMCS.
The following describes the operation of VMREAD and VM WRITE based on processor mode, VMCS-field width, and 
access type:
•16-bit fields:
— A VMREAD returns the value of the field in bits 15:0 of the destination operand; other bits of the destination 
operand are cleared to 0.
— A VMWRITE writes the value of bits 15:0 of the source operand into the VMCS field; other bits of the source 
operand are not used.
•32-bit fields:
— A VMREAD returns the value of the field in bits 31:0 of the destination operand; in 64-bit mode, bits 63:32 
of the destination operand are cleared to 0.
— A VMWRITE writes the value of bits 31:0 of the sour ce operand into the VMCS field; in 64-bit mode, 
bits 63:32 of the source operand are not used.
•64-bit fields and natural-width fields usin g the full access type outside IA-32e mode.
— A VMREAD returns the value of bits 31:0 of the field in its destination operand; bits 63:32 of the field are 
ignored.
— A VMWRITE writes the value of its source operand to bits 31:0 of the field and clears bits 63:32 of the field.
•64-bit fields and natural-width fields using the full acce ss type in 64-bit mode (only on processors that support 
— A VMREAD returns the value of the field in bits 63:0 of the destination operand
— A VMWRITE writes the value of bits 63:0 of  the source operand into the VMCS field.
•64-bit fields using the high access type.
— A VMREAD returns the value of bits 63:32 of the fiel d in bits 31:0 of the destination operand; in 64-bit 
mode, bits 63:32 of the destination operand are cleared to 0.
— A VMWRITE writes the value of bits 31:0 of the source  operand to bits 63:32 of the field; in 64-bit mode, 
Software seeking to read a 64-bit field outside IA-32e mode can use VMREAD with the full access type (reading 
bits 31:0 of the field) and VMREAD with the high access type (reading bits 63: 32 of the field); the order of the two 
VMREAD executions is not important. Software seeking to modify a 64-bit field outside IA-32e mode should first 25-32 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURES
use VMWRITE with the full access type (establishing bits 31:0 of the field while clearing bits 63:32) and then use 
VMWRITE with the high access type (establishing bits 63:32 of the field).
25.11.3 Initializing a VMCS
Software should initialize fields in a VMCS (using VMWRIT E) before using the VMCS for VM entry. Failure to do so 
may result in unpredictable behavior; for example, a VM entry may fail for unexplained reasons, or a successful 
transition (VM entry or VM exit) may load processor state with unexpected values.
It is not necessary to initialize fields that the logical pr ocessor will not use. (For example, it is not necessary to 
initialize the MSR-bitmap address if the “use  MSR bitmaps” VM-execution control is 0.)
A processor maintains some VMCS information that cannot be  modified with the VMWRITE instruction; this includes 
a VMCS’s launch state (see Section 25.1). Such informatio n may be stored in the VMCS  data portion of a VMCS

a VMCS’s launch state (see Section 25.1). Such informatio n may be stored in the VMCS  data portion of a VMCS 
region. Because the format of this information is implemen tation-specific, there is no way for software to know, 
when it first allocates a region of memory for use as a VMCS region, how the processor will determine this informa-
tion from the contents of the memory region.
In addition to its other functions, th e VMCLEAR instruction initializes any implementation-specific information in the 
VMCS region referenced by its operan d. To avoid the uncertainties of implementation-specific behavior, software 
should execute VMCLEAR on a VMCS re gion before making the corresponding VMCS active with VMPTRLD for the 
first time. (Figure 25-1 illustrates how execution of  VMCLEAR puts a VMCS into a well-defined state.)
The following software usage is consistent with these limitations:
•VMCLEAR should be executed for a VMCS before it is used for VM entry for the first time.
•VMLAUNCH should be used for the first VM entry using a VMCS after VMCLEAR has been executed for that 
VMCS.
•VMRESUME should be used for any subsequent VM entr y using a VMCS (until the next execution of VMCLEAR 
for the VMCS).
It is expected that, in general, VMRESUME will have lo wer latency than VMLAUNCH. Si nce “migrating” a VMCS from 
one logical processor to another requires use of VMCLEAR (see Section 25.11.1), which sets the launch state of the 
VMCS to “clear”, such migration requires the next VM entry to be performed usin g VMLAUNCH. Software devel-
opers can avoid the performance cost of increased VM-entry  latency by avoiding unnecessary migration of a VMCS 
from one logical processor to another.
25.11.4 Software Access to Related Structures
In addition to data in the VMCS region itself, VMX non-ro ot operation can be controlled by data structures that are 
referenced by pointers in a VMCS (for example, the I/O bitmaps). While the pointers to these data structures are 
parts of the VMCS, the data structures themselves are not. They are not accessible using VMREAD and VMWRITE 
but by ordinary memory writes.
Software should ensure that each such data structure is modified only when no logical processor with a current 
VMCS that references it is in VMX non-root operatio n. Doing otherwise may lead to unpredictable behavior 
(including behaviors identified in Section 25.11.1). Except ions are made for the following data structures (subject 
to detailed discussion in the sections indicated): EPT paging  structures and the data structures used to locate SPP 
vectors (Section 29.4.3); the virtual-APIC page (Section 30.1); the posted interrupt descriptor (Section 30.6); and 
the virtualization-exception information area (Section 26.5.7.2).
25.11.5 VMXON Region
Before executing VMXON, software allocates a region of memory (called the VMXON region)1 that the logical 
processor uses to support VMX operation. The physical addre ss of this region (the VMXON pointer) is provided in an 
operand to VMXON. The VMXON pointer is subject to  the limitations that apply to VMCS pointers:
1. The amount of memory required for the VMXON region is the same as that required for a VMCS regi on. This size is implementatio n 
specific and can be determined by consulting the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1).Vol. 3C 25-33VIRTUAL MACHINE CONTROL STRUCTURES
•The VMXON pointer must be 4-KByte aligned (bits 11:0 must be zero).
•The VMXON pointer must not set any bits beyond the processor’s physical-address width.1,2
Before executing VMXON, software should write the VMCS revision identifier (see Section 25.2) to the VMXON 
region. (Specifically, it should write the 31-bit VMCS revi sion identifier to bits 30:0 of the first 4 bytes of the 
VMXON region; bit 31 should be cleared to 0.) It need not initialize the VMXON region in any other way. Software 
should use a separate region for each logical processor and should not access or modify the VMXON region of a 
logical processor between execution of VMXON and VMXOFF on  that logical processor. Doing otherwise may lead to 
unpredictable behavior (including beha viors identified in Section 25.11.1).
1. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address 
2. If IA32_VMX_BASIC[48] is read as 1, the VMXON pointer mu st not set any bits in the ra nge 63:32; see Appendix A.1.25-34 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURESVol. 3C 26-1CHAPTER 26
In a virtualized environment using VMX, the guest software stack typically runs on a logical processor in VMX non-
root operation. This mode of operation is similar to that  of ordinary processor operation outside of the virtualized 
environment. This chapter describes the differences betw een VMX non-root operation and ordinary processor oper-
ation with special attention to causes of VM exits (which bring a logical processor from VMX non-root operation to 
root operation). The differences between VMX non-root op eration and ordinary processor operation are described 
in the following sections:
•Section 26.1, “Instructions That Cause VM Exits.”
•Section 26.2, “Other Causes of VM Exits.”
•Section 26.3, “Changes to Instruction Behavior in VMX Non-Root Operation.”
•Section 26.4, “Other Changes in VMX Non-Root Operation.” 
•Section 26.5, “Features Specific to VMX Non-Root Operation.”
•Section 26.6, “Unrestricted Guests.”
Chapter 27, “VM Entries,” describes the data control struct ures that govern VMX non-root operation. Chapter 27, 
“VM Entries,” describes the operation of VM entries by whic h the processor transitions from VMX root operation to 
VMX non-root operation. Chapter 26, “VMX Non-Root Oper ation,” describes the operation of VM exits by which the 
processor transitions from VMX non-root operation to VMX root operation.
Chapter 29, “VMX Support for Address Translation,” describes  two features that support address translation in VMX 
non-root operation. Chapter 30, “APIC Virtualization and Virtual Interrupts,” describes features that support virtu-
alization of interrupts and the Advanced Programmable In terrupt Controller (APIC) in VMX non-root operation.
26.1 INSTRUCTIONS THAT CAUSE VM EXITS
Certain instructions may cause VM exits if executed in VM X non-root operation. Unless otherwise specified, such 
VM exits are “fault-like,” meaning that the instruction caus ing the VM exit does not execute and no processor state 
is updated by the instruction. Section 28.1 detail s architectural state in the context of a VM exit.
Section 26.1.1 defines the prioritization between faults  and VM exits for instructions subject to both. Section 
26.1.2 identifies instructions that ca use VM exits whenever they are executed in VMX non-root operation (and thus 
can never be executed in VMX non-root operation). Section 26.1.3 identifies instructions that cause VM exits 
depending on the settings of certain VM-exe cution control fields (see Section 25.6).
26.1.1 Relative Priority of Faults and VM Exits
The following principles describe the ordering between existing faults and VM exits:
•Certain exceptions have priority over VM exits. Thes e include invalid-opcode exceptions, faults based on 
privilege level,1 and general-protection exceptions that are based on checking I/O permission bits in the task-
state segment (TSS). For example, execution of RDMSR with CPL = 3 generates a general-protection exception 
and not a VM exit.2
•Faults incurred while fetching instruction operands have  priority over VM exits that are conditioned based on 
the contents of those operands (see LMSW in Section 26.1.3).
•VM exits caused by execution of the IN S and OUTS instructions (resulting ei ther because the “unconditional I/O 
exiting” VM-execution control is 1 or because the “use I/ O bitmaps control is 1) have priority over the following 
faults: 
1. These include faults generated by attempts  to execute, in virtual-8086 mode, privileged instructions that are not recognized in that 
mode.
2. MOV DR is an exception to this rule; see Section 26.1.3.26-2 Vol. 3CVMX NON-ROOT OPERATION
— A general-protection fault due to the relevant segmen t (ES for INS; DS for OUTS unless overridden by an 
instruction prefix) being unusable
— A general-protection fault due to an offset beyond the limit of the relevant segment
— An alignment-check exception
•Fault-like VM exits have priority over exceptions other than those mentioned above. For example, RDMSR of a 
non-existent MSR with CPL = 0 generates a VM exit and not a general-protection exception.
When Section 26.1.2 or Section 26.1.3 (below) identify an instruction execution that may lead to a VM exit, it is 
assumed that the instruction does not incur a fault that takes priority over a VM exit.
26.1.2 Instructions That Ca use VM Exits Unconditionally
The following instructions cause VM exits when they are executed in VMX non-root operation: CPUID, GETSEC,1 
INVD, and XSETBV. This is also true of instructions introduced with VMX, which include: INVEPT, INVVPID,

INVD, and XSETBV. This is also true of instructions introduced with VMX, which include: INVEPT, INVVPID, 
VMCALL,2 VMCLEAR, VMLAUNCH, VMPTRLD, VMPTRST, VMRESUME, VMXOFF, and VMXON.
26.1.3 Instructions That Ca use VM Exits Conditionally
Certain instructions cause VM exits in VMX non-root operation depending on the setting of the VM-execution 
controls. The following instructions can cause “fault-like” VM exits based on the conditions described:3
•CLTS.  The CLTS instruction causes a VM exit if the bits in  position 3 (corresponding to CR0.TS) are set in both 
the CR0 guest/host mask and the CR0 read shadow.
•ENCLS.  The ENCLS instruction causes a VM exit if the “ena ble ENCLS exiting” VM-execution control is 1 and 
one of the following is true:
— The value of EAX is less than 63 and the corresponding  bit in the ENCLS-exiting bitmap is 1 (see Section 
25.6.16).
— The value of EAX is greater than or equal to  63 and bit 63 in the ENCLS-exiting bitmap is 1.
•ENCLV.  The ENCLV instruction causes a VM exit if the “enable ENCLV exiting” VM-execution control is 1 and 
— The value of EAX is less than 63 and the corresponding  bit in the ENCLV-exiting bitmap is 1 (see Section 
25.6.17).
— The value of EAX is greater than or equal to  63 and bit 63 in the ENCLV-exiting bitmap is 1.
•ENQCMD, ENQCMDS.  The behavior of each of these instructions is determined by the setting of the “PASID 
translation” VM-execution control. If that control is 0,  the instruction executes normally. If the control is 1, 
instruction behavior is modified and may cause a VM exit. See Section 26.5.8.
•HLT. The HLT instruction causes a VM exit if the “HLT exiting” VM-execution control is 1.
•IN, INS/INSB/INSW/INSD, OUT, OUTS/OUTSB/OUTSW/OUTSD. The behavior of each of these instruc-
tions is determined by the settings of the “uncondition al I/O exiting” and “use I/O bitmaps” VM-execution 
controls:
— If both controls are 0, the instruction executes normally.
1. An execution of GETSEC in VMX non-root operation causes a VM exit  if CR4.SMXE[Bit 14] = 1 regardless of the value of CPL or RAX . 
An execution of GETSEC causes an invalid-opcode exception (#UD) if CR4.SMXE[Bit 14] = 0.
2. Under the dual-monitor treatmen t of SMIs and SMM, executions of VMCALL cause SMM VM exits in VMX root operation outside SMM. 
See Section 32.15.2.
3. Items in this section may refer to second ary processor-based VM-execution controls and tertiary processor-based VM-execution 
controls. If bit 31 of the primary processor-based VM-execution controls is 0, VMX non-root operation functions as if the second ary 
processor-based VM-execution controls were all 0; similarly, if bit 17 of the primary processor-based VM-execu tion controls is 0 , 
VMX non-root operation functions as if the tertiary processor-based VM-execution controls were all 0. See Section 25.6.2.Vol. 3C 26-3VMX NON-ROOT OPERATION
— If the “unconditional I/O exiting” VM-execution contro l is 1 and the “use I/O bitmaps” VM-execution control 
is 0, the instruction causes a VM exit.
— If the “use I/O bitmaps” VM-execution control is 1, th e instruction causes a VM exit if it attempts to access 
an I/O port corresponding to a bit set to 1 in the a ppropriate I/O bitmap (see Section 25.6.4). If an I/O 
operation “wraps around” the 16-bit I/O-port space (accesses ports FFFFH and 0000H), the I/O instruction 
causes a VM exit (the “unconditional I/O exiting” VM-e xecution control is ignored if the “use I/O bitmaps” 
VM-execution control is 1).
See Section 26.1.1 for information regarding the priority of VM exits relative to faults that may be caused by 
the INS and OUTS instructions.
•INVLPG.  The INVLPG instruction causes a VM exit if the “INVLPG exiting” VM-execution control is 1.
•INVPCID.  The INVPCID instruction causes a VM exit if the “INVLPG exiting” and “enable INVPCID” 
VM-execution controls are both 1.
•LGDT, LIDT, LLDT, LTR, SGDT, SIDT, SLDT, STR.  These instructions cause VM exits if the “descriptor-table 
exiting” VM-execution control is 1.
•LMSW.  In general, the LMSW instruction causes a VM exit if it would write, for any bit set in the low 4 bits of 
the CR0 guest/host mask, a value different than the co rresponding bit in the CR0 read shadow. LMSW never 
clears bit 0 of CR0 (CR0.PE); thus, LMSW causes a VM exit if either of the following are true:
— The bits in position 0 (corresponding to CR0.PE) are set in both the CR0 guest/host mask and the source 
operand, and the bit in position 0 is clear in the CR0 read shadow.
— For any bit position in the range 3:1, the bit in that  position is set in the CR0 guest/host mask and the 
values of the corresponding bits in the so urce operand and the CR0 read shadow differ.
•LOADIWKEY.  The LOADIWKEY instruction causes a VM exit if the “LOADIWKEY exiting” VM-execution control 
is 1.
•MONITOR.  The MONITOR instruction causes a VM exit if the “MONITOR exiting” VM-execution control is 1.
•MOV from CR3.  The MOV from CR3 instruction causes a VM exit  if the “CR3-store exiting” VM-execution 
control is 1. The first processors to support the virtual- machine extensions supported only the 1-setting of this 
control.
•MOV from CR8.  The MOV from CR8 instruction causes a VM exit  if the “CR8-store exiting” VM-execution 
control is 1.
•MOV to CR0.  The MOV to CR0 instruction causes a VM exit unless the value of its source operand matches, for 
the position of each bit set in the CR0 guest/host mask , the corresponding bit in the CR0 read shadow. (If every 
bit is clear in the CR0 guest/host mask, MOV to CR0 cannot cause a VM exit.)
•MOV to CR3.  The MOV to CR3 instruction causes a VM exit unl ess the “CR3-load exiting” VM-execution control 
is 0 or the value of its source operand is equal to one of the CR3-target values specified in the VMCS. Only the 
first n CR3-target values are considered, where n is the CR3-target count. If the “CR3-load exiting” VM-
execution control is 1 and the CR3-target count is 0, MOV to CR3 always causes a VM exit.
The first processors to support the virtual-machine exte nsions supported only the 1-setting of the “CR3-load
exiting” VM-execution control. These processors always  consult the CR3-target controls to determine whether
an execution of MOV to CR3 causes a VM exit.
•MOV to CR4.  The MOV to CR4 instruction causes a VM exit unless the value of its source operand matches, for 
the position of each bit set in the CR4 guest/host mask, the corresponding bit in the CR4 read shadow.
•MOV to CR8.  The MOV to CR8 instruction causes a VM exit if the “CR8-load exiting” VM-execution control is 1.
•MOV DR.  The MOV DR instruction causes a VM exit if the “M OV-DR exiting” VM-execution control is 1. Such 
VM exits represent an exception to the principles identified in Section 26.1.1 in that they take priority over the 
following: general-protection exceptions based on privilege level; and invalid-opcode exceptions that occur 
because CR4.DE=1 and the instruction specified access to DR4 or DR5.
•MWAIT.  The MWAIT instruction causes a VM exit if the “MWA IT exiting” VM-execution control is 1. If this 
control is 0, the behavior of the MWAIT instruction may be modified (see Section 26.3).
•PAUSE. The behavior of each of this instruction depends on CPL and the settings of the “PAUSE exiting” and 
“PAUSE-loop exiting” VM-execution controls :
—C P L =  0 .26-4 Vol. 3CVMX NON-ROOT OPERATION
•If the “PAUSE exiting” and “PAUSE-loop exiting”  VM-execution controls are both 0, the PAUSE 
instruction executes normally.
•If the “PAUSE exiting” VM-execution control is 1, the PAUSE instruction causes a VM exit (the “PAUSE-
loop exiting” VM-execution control is ignored if CP L = 0 and the “PAUSE exiting” VM-execution control 
is 1).
•If the “PAUSE exiting” VM-execution control is 0 an d the “PAUSE-loop exiting” VM-execution control is 
1, the following treatment applies.
The processor determines the amount of time be tween this execution of PAUSE and the previous 
execution of PAUSE at CPL 0. If this amount of time  exceeds the value of the VM-execution control field 
PLE_Gap, the processor considers this execution to be the first execution of PAUSE in a loop. (It also 
does so for the first execution of PAUSE at CPL 0 after VM entry.)
Otherwise, the processor determines the amount of ti me since the most recent execution of PAUSE that 
was considered to be the first in a loop. If this am ount of time exceeds the value of the VM-execution 
control field PLE_Window, a VM exit occurs.
For purposes of these computations, time is measured based on a counter that runs at the same rate as 
the timestamp counter (TSC).
—C P L >  0 .
•If the “PAUSE exiting” VM-execution control is  0, the PAUSE instruction executes normally.
•If the “PAUSE exiting” VM-execution control is 1, the PAUSE instruction causes a VM exit.
The “PAUSE-loop exiting” VM-execution control is ignored if CPL > 0.
•PCONFIG.  The PCONFIG instruction causes a VM exit if the “enable PCONFIG” VM-execution control is 1 and 
— The value of EAX is less than 63 and the corresponding  bit in the PCONFIG-exiting bitmap is 1 (see Section

—C P L >  0 .
— The value of EAX is less than 63 and the corresponding  bit in the PCONFIG-exiting bitmap is 1 (see Section 
25.6.18).
— The value of EAX is greater than or equal to 63 and bit 63 in the PCONFIG-exiting bitmap is 1.
If the “enable PCONFIG” VM-executi on control is 1 and neither of th e previous items hold, the PCONFIG 
•RDMSR. The RDMSR instruction causes a VM exit  if any of the following are true:
— The “use MSR bitmaps” VM-execution control is 0.
— The value of ECX is not in the rang es 00000000H – 00001FFFH and C0000000H – C0001FFFH.
— The value of ECX is in the range 00000000H – 00001FFFH and bit n in read bitmap for low MSRs is 1, where 
n is the value of ECX.
— The value of ECX is in the range C0000000H – C0001FFFH and bit n in read bitmap for high MSRs is 1, 
where n is the value of ECX & 00001FFFH.
See Section 25.6.9 for details regarding how these bitmaps are identified.
•RDPMC.  The RDPMC instruction causes a VM exit if the “RDPMC exiting” VM-execution control is 1.
•RDRAND.  The RDRAND instruction causes a VM exit if th e “RDRAND exiting” VM-execution control is 1.
•RDSEED.  The RDSEED instruction causes a VM exit if the “RDSEED exiting” VM-e xecution control is 1.
•RDTSC.  The RDTSC instruction causes a VM exit if th e “RDTSC exiting” VM-execution control is 1.
•RDTSCP.  The RDTSCP instruction causes a VM exit if the “RDTSC exiting” and “enable RDTSCP” VM-execution 
controls are both 1.
•RSM.  The RSM instruction causes a VM exit if executed in system-management mode (SMM).1
•TPAUSE.  The TPAUSE instruction causes a VM exit if the “R DTSC exiting” and “enable user wait and pause” 
1. Execution of the RSM instruction outside SMM causes an invalid-opcode exception regardless of whether the processor is in VMX  
operation. It also does so  in VMX root operation in SMM; see Section 32.15.3.Vol. 3C 26-5VMX NON-ROOT OPERATION
•UMWAIT.  The UMWAIT instruction causes a VM exit if the “R DTSC exiting” and “enable user wait and pause” 
•VMREAD.  The VMREAD instruction causes a VM ex it if any of the following are true:
— The “VMCS shadowing” VM-execution control is 0.
— Bits 63:15 (bits 31:15 outside 64-bit mode) of the register source operand are not all 0.
—B i t n in VMREAD bitmap is 1, where n is the value of bits 14:0 of the register source operand. See Section 
25.6.15 for details regarding how th e VMREAD bitmap is identified.
If the VMREAD instruction does not cause a VM exit, it  reads from the VMCS referenced by the VMCS link
pointer. See Chapter 31, “VMREAD—Read Field from Vi rtual-Machine Control Structure” for details of the
operation of the VMREAD instruction.
•VMWRITE.  The VMWRITE instruction causes a VM exit if any of the following are true:
—B i t n in VMWRITE bitmap is 1, where n is the value of bits 14:0 of the re gister source operand. See Section 
25.6.15 for details regarding how th e VMWRITE bitmap is identified.
If the VMWRITE instruction does not cause a VM exit, it  writes to the VMCS referenced by the VMCS link
pointer. See Chapter 31, “VMWRITE—Write Field to Virtual-Machine Control Structure” for details of the
operation of the VMWRITE instruction.
•WBINVD.  The WBINVD instruction causes a VM exit if the “WBINVD exiting” VM-execution control is 1.
•WBNOINVD.  The WBNOINVD instruction causes a VM exit if the “WBINVD exiting” VM-execution control is 1.
•WRMSR.  The WRMSR instruction causes a VM exit if any of the following are true:
— The “use MSR bitmaps” VM-execution control is 0.— The value of ECX is not in the rang es 00000000H – 00001FFFH and C0000000H – C0001FFFH.
— The value of ECX is in the range 00000000H – 00001FFFH and bit n in write bitmap for low MSRs is 1, 
where n is the value of ECX.
— The value of ECX is in the range C0000000H – C0001FFFH and bit n in write bitmap for high MSRs is 1, 
•XRSTORS.  The XRSTORS instruction causes a VM exit if th e “enable XSAVES/XRSTORS” VM-execution control 
is 1and any bit is set in the logical-AND of the foll owing three values: EDX:EAX, the IA32_XSS MSR, and the 
XSS-exiting bitmap (see Section 25.6.21).
•XSAVES.  The XSAVES instruction causes a VM exit if the “enable XSAVES/XRSTORS” VM-execution control is 
1 and any bit is set in the logical-AND of the followin g three values: EDX:EAX, the IA32_XSS MSR, and the XSS-
exiting bitmap (see Section 25.6.21).
26.2 OTHER CAUSES OF VM EXITS
In addition to VM exits caused by instruction ex ecution, the following events can cause VM exits:1
•Exceptions.  Exceptions (faults, traps, and aborts) cause VM exits based on the exception bitmap (see Section 
25.6.3). If an exception occurs, its vector (in the range 0– 31) is used to select a bit in the exception bitmap. If 
the bit is 1, a VM exit occurs; if the bit is 0, the exception is delivered normally through the guest IDT. This use 
of the exception bitmap applies also to exceptions generated by the instructions INT1, INT3, INTO, BOUND, 
UD0, UD1, and UD2.2
1. Items in this section may refer to second ary processor-based VM-execution controls and tertiary processor-based VM-execution 
controls. If bit 31 of the primary processor-based VM-execution co ntrols is 0, VMX non-root operation functions as if the second ary 
processor-based VM-execution controls were all 0; similarly, if bit 17 of  the primary processor-based VM-execution controls is 0 , 
VMX non-root operation functions as if the tertiary processor-based VM-execution controls were all 0. See Section 25.6.2.26-6 Vol. 3CVMX NON-ROOT OPERATION
Page faults (exceptions with vector 14) are specially treated. When a page fault occurs, a processor consults 
(1) bit 14 of the exception bitmap; (2) the error code pr oduced with the page fault [PFEC]; (3) the page-fault 
error-code mask field [PFEC_MASK]; and (4) the page-fau lt error-code match field [PFEC_MATCH]. It checks if 
PFEC & PFEC_MASK = PFEC_MATCH. If there is equality, the specification of bit 14 in the exception bitmap is 
followed (for example, a VM exit occurs if that bit is set). If there is inequality, the meaning of that bit is 
reversed (for example, a VM exit occurs if that bit is clear).
Thus, if software desires VM exits on all page faults, it can set bit 14 in the exception bitmap to 1 and set the 
page-fault error-code mask and match fields each to  00000000H. If software desires VM exits on no page 
faults, it can set bit 14 in the exception bitmap to 1,  the page-fault error-code mask field to 00000000H, and 
the page-fault error-code match field to FFFFFFFFH.
•Triple fault.  A VM exit occurs if the logical processor encount ers an exception while attempting to call the 
double-fault handler and that exception itself does not cause a VM exit due to the exception bitmap. This 
applies to the case in which the double-fault exception was generated within VMX non-root operation, the case 
in which the double-fault exception was generated during event injection by VM entry, and to the case in which 
VM entry is injecting a double-fault exception.
•External interrupts.  An external interrupt causes a VM exit if the “external-interrupt exiting” VM-execution 
control is 1. (See Section 26.6 for an exception.) Othe rwise, the processor handles the interrupt is normally.1 
(If a logical processor is in the shutdown state or the wait-for-SIPI state, external interrupts are blocked. The 
processor does handle the interrupt and no VM exit occurs.)
•Non-maskable inte rrupts (NMIs).  An NMI causes a VM exit if the “NMI exiting” VM-execution control is 1. 
Otherwise, it is delivered using descriptor 2 of the IDT. (I f a logical processor is in the wait-for-SIPI state, NMIs 
are blocked. The NMI is not delivered through the IDT and no VM exit occurs.)
•INIT signals.  INIT signals cause VM exits. A logical processo r performs none of the operations normally 
associated with these events. Such exits do not modify register state or clear pending events as they would 
outside of VMX operation. (If a logical processor is in the wait-for-SIPI state, INIT signals are blocked. They do 
not cause VM exits in this case.)
•Start-up IPIs (SIPIs). SIPIs cause VM exits.  If a logical processor is not in the wait-for-SIPI activity state 
when a SIPI arrives, no VM exit occurs and the SIPI is  discarded. VM exits due to SIPIs do not perform any of 
the normal operations associated with those events: they do not modify register state as they would outside of 
VMX operation. (If a logical processor is not in the wait -for-SIPI state, SIPIs are blocked. They do not cause 
VM exits in this case.)
•Task switches. Task switches are not allowed in VMX non-root op eration. Any attempt to effect a task switch 
in VMX non-root operation causes a VM exit. See Section 26.4.2.

•System-management in terrupts (SMIs). If the logical processor is using the dual-monitor treatment of 
SMIs and system-management mode (SMM), SM Is cause SMM VM exits. See Section 32.15.2.2
•VMX-preemption timer.  A VM exit occurs when the timer counts down to zero. See Section 26.5.1 for details 
of operation of the VMX-preemption timer.
Debug-trap exceptions and higher priority events take  priority over VM exits caus ed by the VMX-preemption 
timer. VM exits caused by the VMX-preemption timer take priority over VM exits caused by the “NMI-window 
exiting” VM-execution control and lower priority events. 
These VM exits wake a logical processor from the same inactive states as would a non-maskable interrupt. 
Specifically, they wake a logical processor from the sh utdown state and from the states entered using the HLT 
and MWAIT instructions. These VM exits do not occur if the logical processor is in the wait-for-SIPI state.
•Bus locks.  Assertion of a bus lock (see Section 9.1.2) ca uses a VM exit if the “VMM bus-lock detection” 
VM-execution control is 1. Such a VM exit is trap-like because it is generated after execution of an instruction 
that asserts a bus lock. The VM exit thus does not prevent assertion of the bus lock. These VM exits take priority over system-management interrupts (SMIs), INIT signals, and lower priority events.
2. INT1 and INT3 refer to the instructions with opcodes F1 and CC, respectively, and not to INT n with value 1 or 3 for n.
1. Normal handling usually means delivery through the IDT, but it  could also mean treatment of the interrupt as a user-interrupt  notifi-
cation.
2. Under the dual-monitor treatment of SMIs and SMM, SMIs also cause SMM VM exits if they occur in VMX root operation outside SMM.  
If the processor is using the default tr eatment of SMIs and SMM, SMIs are delivered as described in Section 32.14.1.Vol. 3C 26-7VMX NON-ROOT OPERATION
•Instruction timeout.  If the “instruction timeout” VM-execution control is 1, a VM exit occurs if certain 
operations prevent the processor from reaching an instru ction boundary within the amount of time specified by 
the instruction-timeout control VM-execution control field (see Section 25.6.25).
In addition, there are controls that cause VM exits based on the readiness of guest so ftware to receive interrupts:
•If the “interrupt-window exiting” VM-execution control is 1, a VM exit occurs before execution of any instruction 
if RFLAGS.IF = 1 and there is no blocking of events by STI or by MOV SS (see Table 25-3). Such a VM exit 
occurs immediately after VM entry if the above conditions are true (see Section 27.7.5).
Non-maskable interrupts (NMIs) and higher priority events  take priority over VM exits caused by this control. 
VM exits caused by this control take priority over external interrupts and lower priority events. 
These VM exits wake a logical processor from the same in active states as would an external interrupt. Specifi-
cally, they wake a logical processor from the states entered using the HLT and MWAIT instructions. These 
VM exits do not occur if the logical processor is in the shutdown state or the wait-for-SIPI state.
•If the “NMI-window exiting” VM-execution control is 1, a VM exit occurs before execution of any instruction if 
there is no virtual-NMI blocking and there is no blocking of events by MOV SS and no blocking of events by STI (see Table 25-3). Such a VM exit occurs immediately after VM entry if the above conditions are true (see 
Section 27.7.6).
VM exits caused by the VMX-preemption timer and higher pr iority events take priority over VM exits caused by 
this control. VM exits caused by this control take priority over non-maskable interrupts (NMIs) and lower 
priority events. 
These VM exits wake a logical processor from the same inactive states as would an NMI. Specifically, they wake 
a logical processor from the shutdown state and from th e states entered using the HLT and MWAIT instructions. 
These VM exits do not occur if the logical processor is in the wait-for-SIPI state.
26.3 CHANGES TO INSTRUCTION BEHA VIOR IN VMX NON-ROOT OPERATION
The behavior of some instructions is changed in VMX no n-root operation. Some of these changes are determined 
by the settings of certain VM-execution control fields. The following items detail such changes:1
•CLTS.  Behavior of the CLTS instruction is determined by th e bits in position 3 (corresponding to CR0.TS) in the 
CR0 guest/host mask and the CR0 read shadow:
— If bit 3 in the CR0 guest/host mask is 0, CLTS clears CR0.TS normally (the value of bit 3 in the CR0 read 
shadow is irrelevant in this case), unless CR0.TS is fi xed to 1 in VMX operation (see Section 24.8), in which 
case CLTS causes a general-protection exception.
— If bit 3 in the CR0 guest/host mask is 1 and bit 3 in the CR0 read shadow is 0, CLTS completes but does not 
change the contents of CR0.TS.
— If the bits in position 3 in the CR0 guest/host mask and the CR0 read shadow are both 1, CLTS causes a 
VM exit.
•ENQCMD, ENQCMDS.  Each of these instructions performs a 64-byte enqueue store that includes a PASID 
value in bits 19:0. For ENQCMD, the PASID is normally  the value of IA32_PASID[19:0], while for ENQCMDS, 
the PASID is normally read from memory.
The behavior of each of these instructions (and in pa rticular the PASID value used for the enqueue store) is
determined by the setting of the “PAS ID translation” VM-execution control:
— If the “PASID translation” VM-execution control is 0, the instruction operates normally.
— If the “PASID translation” VM-execution control is  1, the PASID value used for the enqueue store is 
determined by the PASID-translation process described in Section 26.5.8. (Note the PASID translation may 
result in a VM exit, in which case the enqueue store is not performed.)
VMX non-root operation functions as if the tertiary processor-based VM-execution controls were all 0. See Section 25.6.2.26-8 Vol. 3CVMX NON-ROOT OPERATION
An execution of ENQCMD or ENQCMDS performs PASID translation only after checking for conditions that may
result in general-protection exception (the check of  IA32_PASID.Valid for ENQCMD; the privilege-level check
for ENQCMDS), after loading the instruction's source operand from memory, and thus after any faults or
VM exits that the loading may cause (e.g., page faults or  EPT violations). PASID translation occurs before the
actual enqueue store and thus before an y faults or VM exits that it may cause.
•INVPCID.  Behavior of the INVPCID instruction is determin ed first by the setting of the “enable INVPCID” 
VM-execution control:
— If the “enable INVPCID” VM-execution control is 0, INVPCID causes an invalid-opcode exception (#UD). 
This exception takes priority over any other exception the instruction may incur.
— If the “enable INVPCID” VM-execution control is 1,  treatment is based on the setting of the “INVLPG 
exiting” VM-execution control:
•If the “INVLPG exiting” VM-execution co ntrol is 0, INVPCID operates normally.
•If the “INVLPG exiting” VM-execution control is 1, INVPCID causes a VM exit.
•IRET.  Behavior of IRET with regard to NMI blocking (see Table 25-3) is determined by the settings of the “NMI 
exiting” and “virtual NMIs” VM-execution controls:
— If the “NMI exiting” VM-execution control is 0, IR ET operates normally and unblocks NMIs. (If the “NMI 
exiting” VM-execution control is 0, the “virtual  NMIs” control must be 0; see Section 27.2.1.1.)
— If the “NMI exiting” VM-execution control is 1, IRET does not affect blocking of NMIs. If, in addition, the 
“virtual NMIs” VM-execution control is 1, the logical processor tracks virtual-NMI blocking. In this case, 
IRET removes any virtual-NMI blocking.
The unblocking of NMIs or virtual NMIs specifie d above occurs even if IRET causes a fault.
•LMSW.  Outside of VMX non-root operation, LMSW loads its source operand into CR0[3:0], but it does not clear 
CR0.PE if that bit is set. In VMX non-root operation, an execution of LMSW that does not cause a VM exit (see 
Section 26.1.3) leaves unmodified any bit in CR0[3:0] co rresponding to a bit set in the CR0 guest/host mask. 
An attempt to set any other bit in CR0[3:0] to a value not supported in VMX operation (see Section 24.8) 
causes a general-protection exception. Attempts to clear CR0.PE are ignored without fault.
•MOV from CR0. The behavior of MOV from CR0 is determined by the CR0 guest/host mask and the CR0 read 
shadow. For each position corresponding to a bit clear in the CR0 guest/host mask, the destination operand is 
loaded with the value of the corresponding bit in CR0. For each position corresponding to a bit set in the CR0

loaded with the value of the corresponding bit in CR0. For each position corresponding to a bit set in the CR0 
guest/host mask, the destination operand is loaded with  the value of the corresponding bit in the CR0 read 
shadow. Thus, if every bit is cleared in the CR0 guest/ host mask, MOV from CR0 reads normally from CR0; if 
every bit is set in the CR0 guest/host mask, MOV fr om CR0 returns the value of the CR0 read shadow.
Depending on the contents of the CR0 guest/host mask  and the CR0 read shadow, bits may be set in the 
destination that would never be set when reading directly from CR0.
•MOV from CR3. If the “enable EPT” VM-execution control is 1 and an execution of MOV from CR3 does not 
cause a VM exit (see Section 26.1.3), the value loaded from CR3 is a guest-physical address; see Section 
29.3.1.
•MOV from CR4.  The behavior of MOV from CR4 is determined by the CR4 guest/host mask and the CR4 read 
shadow. For each position corresponding to a bit clear in the CR4 guest/host mask, the destination operand is loaded with the value of the corresponding bit in CR4. For each position corresponding to a bit set in the CR4 
guest/host mask, the destination operand is loaded with  the value of the corresponding bit in the CR4 read 
shadow. Thus, if every bit is cleared in the CR4 guest/ host mask, MOV from CR4 reads normally from CR4; if 
every bit is set in the CR4 guest/host mask, MOV fr om CR4 returns the value of the CR4 read shadow.
Depending on the contents of the CR4 guest/host mask  and the CR4 read shadow, bits may be set in the 
destination that would never be set when reading directly from CR4.
•MOV from CR8.  If the MOV from CR8 instruction does not caus e a VM exit (see Section 26.1.3), its behavior is 
modified if the “use TPR shadow” VM-execution control is 1; see Section 30.3.
•MOV to CR0.  An execution of MOV to CR0 that does not cause a VM exit (see Section 26.1.3) leaves 
unmodified any bit in CR0 corresponding to a bit set in the CR0 guest/host mask. Treatment of attempts to 
modify other bits in CR0 depends on the setting of the “unrestricted guest” VM-execution control:
— If the control is 0, MOV to CR0 causes a general-protection exception if it attempts to set any bit in CR0 to 
a value not supported in VMX operation (see Section 24.8).Vol. 3C 26-9VMX NON-ROOT OPERATION
— If the control is 1, MOV to CR0 causes a general-protec tion exception if it attempts to set any bit in CR0 
other than bit 0 (PE) or bit 31 (PG) to a value not supported in VMX operation. It remains the case, however, that MOV to CR0 causes a general-protection exception if it would result in CR0.PE = 0 and 
CR0.PG = 1 or if it would result in CR0.PG = 1, CR4.PAE = 0, and IA32_EFER.LME = 1.
•MOV to CR3.  If the “enable EPT” VM-execution control is 1 and an execution of MOV to CR3 does not cause a 
VM exit (see Section 26.1.3), the value loaded into CR3 is treated as a guest-physical address; see Section 
29.3.1.
— If PAE paging is not being used, the instruction does not use the guest-physical address to access memory 
and it does not cause it to be translated through EPT.1
— If PAE paging is being used, the instruction translates  the guest-physical address through EPT and uses the 
result to load the four (4) page-directory-pointer-tab le entries (PDPTEs). The instruction does not use the 
guest-physical addresses the PDPTEs to access memory  and it does not cause them to be translated 
through EPT.
•MOV to CR4.  An execution of MOV to CR4 that does not cause a VM exit (see Section 26.1.3) leaves 
unmodified any bit in CR4 corresponding to a bit set in the CR4 guest/host mask. Such an execution causes a 
general-protection exception if it attempts to set any bit in CR4 (not corresponding to a bit set in the CR4 
guest/host mask) to a value not supported in VMX operation (see Section 24.8).
•MOV to CR8.  If the MOV to CR8 instruction does not cause a VM exit (see Section 26.1.3), its behavior is 
•MWAIT.  Behavior of the MWAIT instruction (which alwa ys causes an invalid-opcode exception—#UD—if 
CPL > 0) is determined by the setting of the “MWAIT exiting” VM-execution control:
— If the “MWAIT exiting” VM-execution control is 1, MWAIT causes a VM exit.
— If the “MWAIT exiting” VM-execution control is 0, MWAI T operates normally if one of the following are true: 
(1) ECX[0] is 0; (2) RFLAGS.IF = 1; or both of the following are true: (a) the “interrupt-window exiting” 
VM-execution control is 0; and (b) the logical processor has not recognized a pending virtual interrupt (see Section 29.2.1).
— If the “MWAIT exiting” VM-execution  control is 0, ECX[0] = 1, and RFLAGS.IF = 0, MWAIT does not cause 
the processor to enter an implementation-dependent optimized state if either the “interrupt-window 
exiting” VM-execution control is 1 or the logical processor has recognized a pending virtual interrupt; 
instead, control passes to the instruction following the MWAIT instruction.
•PCONFIG.  Behavior of the PCONFIG instruction is determ ined by the setting of the “enable PCONFIG” 
— If the “enable PCONFIG” VM-execution control is 0,  PCONFIG causes an invalid-opcode exception (#UD). 
This exception takes priority over any exception the instruction may incur.
— If the “enable PCONFIG” VM-execution control is 1, PCONFIG may cause a VM exit as specified in Section 
26.1.3; if it does not cause such a VM exit, it operates normally.
•RDMSR.  Section 26.1.3 identifies when executions of the RDMSR instruction cause VM exits. If such an 
execution causes neither a fault due to CPL > 0 nor a VM exit, the instruction’s behavior may be modified for 
certain values of ECX:
— If ECX contains 10H (indicating the IA32_TIME_ST AMP_COUNTER MSR), the value returned by the 
instruction is determined by the setting of the “use TSC offsetting” VM-execution control:
•If the control is 0, RDMSR operates norma lly, loading EAX:EDX with the value of the 
IA32_TIME_STAMP_COUNTER MSR.
•If the control is 1, the value returned is dete rmined by the setting of the “use TSC scaling” 
— If the control is 0, RDMSR loads EAX: EDX with the sum of the value of the 
IA32_TIME_STAMP_COUNTER MSR and the value of the TSC offset.
1. A logical processor uses PAE paging if CR0.PG = 1, CR4. PAE = 1 and IA32_EFER.LMA = 0. See Section 4.4 in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 3A.26-10 Vol. 3CVMX NON-ROOT OPERATION
— If the control is 1, RDMSR first computes the product of the value of the 
IA32_TIME_STAMP_COUNTER MSR and the value of the TSC multiplier. It then shifts the value of 
the product right 48 bits and loads EAX:EDX with th e sum of that shifted value and the value of the 
TSC offset.
The 1-setting of the “use TSC-offsetting” VM-execution control does not affect executions of RDMSR if ECX 
contains 6E0H (indicating the IA32_TSC_DEADLINE MSR) . Such executions return the APIC-timer deadline 
relative to the actual timestamp counter without regard to the TSC offset.
— If ECX contains 48H (indicating the IA32_SPEC_CTRL MSR), the value returned by the instruction is 
determined by the setting of the “virtual ize IA32_SPEC_CTRL” VM-execution control:
•If the control is 0, RDMSR operates normally, load ing EAX:EDX with the value of the IA32_SPEC_CTRL 
MSR.
•If the control is 1, the value returned is that of the IA32_SPEC_CTRL shadow field in the VMCS.
— If ECX is in the range 800H–8FFH (indicating an APIC  MSR), instruction behavior may be modified if the 
“virtualize x2APIC mode” VM-executi on control is 1; see Section 30.5.
•RDPID.  Behavior of the RDPID instruction is determin ed first by the setting of the “enable RDTSCP” 
— If the “enable RDTSCP” VM-execution control is 0,  RDPID causes an invalid-opcode exception (#UD).
— If the “enable RDTSCP” VM-execution control is 1, RDPID operates normally.
•RDTSC.  Behavior of the RDTSC instruction is determined by  the settings of the “RDTSC exiting” and “use TSC 
offsetting” VM-execution controls:
— If both controls are 0, RDTSC operates normally.
— If the “RDTSC exiting” VM-execution control is 0 and th e “use TSC offsetting” VM-execution control is 1, the 
value returned is determined by the setting of the “use TSC scaling” VM-execution control:
•If the control is 0, RDTSC loads EAX:EDX with th e sum of the value of the IA32_TIME_STAMP_COUNTER 
MSR and the value of the TSC offset.
•If the control is 1, RDTSC first computes the pr oduct of the value of the IA32_TIME_STAMP_COUNTER 
MSR and the value of the TSC multiplier. It then shif ts the value of the product right 48 bits and loads 
EAX:EDX with the sum of that shifted value and the value of the TSC offset.
— If the “RDTSC exiting” VM-execution control is 1, RDTSC causes a VM exit.
•RDTSCP.  Behavior of the RDTSCP instruction is determin ed first by the setting of the “enable RDTSCP” 
— If the “enable RDTSCP” VM-execution control is 0, RD TSCP causes an invalid-opcode exception (#UD). This

— If the “enable RDTSCP” VM-execution control is 0, RD TSCP causes an invalid-opcode exception (#UD). This 
exception takes priority over any other exception the instruction may incur.
— If the “enable RDTSCP” VM-execution control is 1, trea tment is based on the setting s of the “RDTSC exiting” 
and “use TSC offsetting” VM-execution controls:
•If both controls are 0, RDTSCP operates normally.
•If the “RDTSC exiting” VM-execution control is 0 and the “use TSC offsetting” VM -execution control is 1, 
the value returned is determined by the setting  of the “use TSC scaling” VM-execution control:
— If the control is 0, RDTSCP loads EAX:EDX with the sum of the value of the 
— If the control is 1, RDTSCP first computes the product of the value of the 
In either case, RDTSCP also loads ECX with th e value of bits 31:0 of the IA32_TSC_AUX MSR.
•If the “RDTSC exiting” VM-execution control is 1, RDTSCP causes a VM exit.
•SMSW.  The behavior of SMSW is determined by the CR0 guest/host mask and the CR0 read shadow. For each 
position corresponding to a bit clear in the CR0 guest/ host mask, the destination operand is loaded with the Vol. 3C 26-11VMX NON-ROOT OPERATION
value of the corresponding bit in CR0. For each position  corresponding to a bit set in the CR0 guest/host mask, 
the destination operand is loaded with the value of the corresponding bit in the CR0 read shadow. Thus, if every 
bit is cleared in the CR0 guest/host mask, SMSW reads normally from CR0; if every bit is set in the CR0 
guest/host mask, SMSW returns th e value of the CR0 read shadow.
Note the following: (1) for any memory destination or for a 16-bit register destination, only the low 16 bits of 
the CR0 guest/host mask and the CR0 read shadow are used (bits 63:16 of a register destination are left unchanged); (2) for a 32-bit register destination, only th e low 32 bits of the CR0 guest/host mask and the CR0 
read shadow are used (bits 63:32 of the destination ar e cleared); and (3) depending on the contents of the 
CR0 guest/host mask and the CR0 read shadow, bits may be set in the destination that would never be set when reading directly from CR0.
•TPAUSE.  Behavior of the TPAUSE instruction is determined first by the setting of the “enable user wait and 
pause” VM-execution control:
— If the “enable user wait and pause” VM-execution cont rol is 0, TPAUSE causes an invalid-opcode exception 
(#UD). This exception takes priority over any exception the instruction may incur.
— If the “enable user wait and pause” VM-execution cont rol is 1, treatment is based on the setting of the 
“RDTSC exiting” VM-execution control:
•If the “RDTSC exiting” VM-execution control is 0, the instruction delays for an amount of time called 
here the physical delay . The physical delay is first computed by determining the virtual delay  (the 
time to delay relative to the guest’s timestamp counter).
If IA32_UMWAIT_CONTROL[31:2] is zero, the virtual delay is the value in EDX:EAX minus the value 
that RDTSC would return (see above); if IA32_UMWAIT_CONTROL[31:2] is not zero, the virtual delay 
is the minimum of that difference and AND(IA32_UMWAIT_CONTROL,FFFFFFFCH).
The physical delay depends upon the settings of the “use TSC offsetting” and “use TSC scaling” 
VM-execution controls:
— If either control is 0, the physical delay is the virtual delay.
— If both controls are 1, the virtual delay is multiplied by 248 (using a shift) to produce a 128-bit 
integer. That product is then divided by the TSC multiplier to produce a 64-bit integer. The physical 
delay is that quotient.
•If the “RDTSC exiting” VM-execution co ntrol is 1, TPAUSE causes a VM exit.
•UMONITOR.  Behavior of the UMONITOR instruction is determined by the setting of the “enable user wait and 
— If the “enable user wait and pause” VM-execution control is 0, UMONITOR causes an invalid-opcode 
exception (#UD). This exception takes priority over any exception the instruction may incur.
— If the “enable user wait and pause” VM-execution control is 1, UMONITOR operates normally.
•UMWAIT.  Behavior of the UMWAIT instruction is determined first by the setting of the “enable user wait and 
— If the “enable user wait and pause” VM-execution cont rol is 0, UMWAIT causes an invalid-opcode exception 
•If the “RDTSC exiting” VM-execution control is 0, and if the instruction causes a delay, the amount of 
time delayed is called here the physical delay . The physical delay is first computed by determining the 
virtual delay  (the time to delay relative to the guest’s timestamp counter).
that RDTSC would return (see above); if IA32_UMWAIT_CONTROL[31:2] is not zero, the virtual delay is the minimum of that difference and AND(IA32_UMWAIT_CONTROL,FFFFFFFCH).
— If either control is 0, the physical delay is the virtual delay.26-12 Vol. 3CVMX NON-ROOT OPERATION
integer. That product is then divided by the TSC multiplier to produce a 64-bit integer. The physical delay is that quotient.
•If the “RDTSC exiting” VM-execution control is 1, UMWAIT causes a VM exit.
•WRMSR.  Section 26.1.3 identifies when executions of the WRMSR instruction cause VM exits. If such an 
execution neither a fault due to CPL > 0 nor a VM exit, th e instruction’s behavior may be modified for certain 
values of ECX:
— If ECX contains 48H (indicating the IA32_SPEC_CTRL MS R), instruction behavior depends on the setting of 
the “virtualize IA32_SPEC_CTRL” VM-execution control:
•If the control is 0, WRMSR operates normally, lo ading the IA32_SPEC_CTRL MSR with the value in 
EAX:EDX.
•If the control is 1, instruction will attempt to write the IA32_SPEC_CTRL MSR using the instruction’s 
source operand, but it will attempt to modify only th ose bits in positions corresponding to bits cleared in 
the IA32_SPEC_CTRL mask field in the VMCS.
Specifically, the instruction attempts to write the MSR with the following value:
(MSR_VAL & ISC_MASK) OR (SRC & NOT ISC_MASK),
where MSR_VAL is the original value of the MSR, ISC_MASK is the IA32_SPEC_CTRL mask, and SRC is 
the instruction’s source operand.
Any fault that would result from writing that value to the MSR (e.g., due to a reserved-bit violation) 
occurs normally. Otherwise, the value is written to the MSR.
Such a write to the MSR will have any side effects that would occur normally had the MSR been written 
with the value indicated above (including any side effects that may result from writing unchanged 
values to the masked bits).
If the write completes without a fault, the unmodifie d value of the source operand is written to the 
IA32_SPEC_CTRL shadow field in the VMCS.
— If ECX contains 79H (indicating IA32_BIOS_UPDT_TRIG MSR), no microcode update is loaded, and control 
passes to the next instruction. This implies that mi crocode updates cannot be loaded in VMX non-root 
— On processors that support Intel PT but which do not a llow it to be used in VMX operation, if ECX contains 
570H (indicating the IA32_RTIT_CTL MSR), the inst ruction causes a general-protection exception.1
— If ECX contains 808H (indicating the TPR MSR), 80BH  (the EOI MSR), 830H (the ICR MSR), or 83FH (the 
self-IPI MSR), instruction behavior may be modified if  the “virtualize x2APIC mode” VM-execution control is 
1; see Section 30.5.
•XRSTORS.  Behavior of the XRSTORS instruction is dete rmined first by the setting of the “enable 
XSAVES/XRSTORS” VM-execution control:
— If the “enable XSAVES/XRSTORS” VM-execution control is 0, XRSTORS causes an invalid-opcode exception 
(#UD).
— If the “enable XSAVES/XRSTORS” VM-execution control is 1, treatment is based on the value of the XSS-
exiting bitmap (see Section 25.6.21):
•XRSTORS causes a VM exit if any bit is set in the logical-AND of the following three values: EDX:EAX, 
the IA32_XSS MSR, and the XSS-exiting bitmap.
•Otherwise, XRSTORS operates normally.
•XSAVES.  Behavior of the XSAVES instruction is dete rmined first by the se tting of the “enable 
— If the “enable XSAVES/XRSTORS” VM-execution control is 0, XSAVES causes an invalid-opcode exception 
(#UD).
1. Software should read the VMX capability MSR IA32_VMX_MISC to determin e whether the processor allows Intel PT to be used in

(#UD).
(#UD).
1. Software should read the VMX capability MSR IA32_VMX_MISC to determin e whether the processor allows Intel PT to be used in 
VMX operation (see Appendix A.6).Vol. 3C 26-13VMX NON-ROOT OPERATION
•XSAVES causes a VM exit if any bit is set in the lo gical-AND of the following three values: EDX:EAX, the 
IA32_XSS MSR, and the XSS-exiting bitmap.
•Otherwise, XSAVES operates normally.
26.4 OTHER CHANGES IN VMX NON-ROOT OPERATION
Treatments of event blocking, task switches, and certain shadow-stack updates may differ in VMX non-root opera-
tion as described in the following sections.
26.4.1 Event Blocking
Event blocking is modified in VMX non-root operation as follows:
•If the “external-interrupt exiting” VM-execution contro l is 1, RFLAGS.IF does not control the blocking of 
external interrupts. In this case, an external interrupt  that is not blocked for other reasons causes a VM exit 
(even if RFLAGS.IF = 0).
•If the “external-interrupt exiting” VM-execution control is 1, external interrupts may or may not be blocked by 
STI or by MOV SS (behavior is implementation-specific).
•If the “NMI exiting” VM-execution control is 1, non-ma skable interrupts (NMIs) may or may not be blocked by 
26.4.2 Treatment of Task Switches
Task switches are not allowed in VMX non-root operation. An y attempt to effect a task switch in VMX non-root oper-
ation causes a VM exit. However, the following checks are performed (in the order indicated), possibly resulting in 
a fault, before there is any possibilit y of a VM exit due to task switch:
1. If a task gate is being used, appropriate checks are made  on its P bit and on the proper values of the relevant 
privilege fields. The following cases detail the privilege checks performed:
a. If CALL, INT n, INT1, INT3, INTO, or JMP accesses a task gate in IA-32e mode, a general-protection 
exception occurs.
b. If CALL, INT n, INT3, INTO, or JMP accesses a task gate outs ide IA-32e mode, privilege-levels checks are 
performed on the task gate but, if they pass, privileg e levels are not checked on the referenced task-state 
segment (TSS) descriptor.
c. If CALL or JMP accesses a TSS descriptor directly in IA-32e mode, a general-protection exception occurs.d. If CALL or JMP accesses a TSS descriptor directly outs ide IA-32e mode, privilege levels are checked on the 
TSS descriptor.
e. If a non-maskable interrupt (NMI), an exception, or an  external interrupt accesses a task gate in the IDT in 
IA-32e mode, a general-protection exception occurs.
f. If a non-maskable interrupt (NMI), an exception other than breakpoint exceptions (#BP) and overflow 
exceptions (#OF), or an external interrupt accesse s a task gate in the IDT outside IA-32e mode, no 
privilege checks are performed.
g. If IRET is executed with RFLAGS.NT = 1 in IA-32e mode, a general-protection exception occurs.h. If IRET is executed with RFLAGS.NT = 1 outside IA-32e mode, a TSS descriptor is accessed directly and no 
privilege checks are made.
2. Checks are made on the new TSS selector (for example, that is within GDT limits).
3. The new TSS descriptor is read. (A page fault results if a relevant GDT page is not present).
4. The TSS descriptor is checked for proper values of type (d epends on type of task swit ch), P bit, S bit, and limit.26-14 Vol. 3CVMX NON-ROOT OPERATION
Only if checks 1–4 all pass (do not generate faults) might a VM exit occur. However, the ordering between a VM exit 
due to a task switch and a page fault resulting from accessing the old TSS or the new TSS is implementation-specific. Some processors may generate a page fault (instead  of a VM exit due to a task switch) if accessing either 
TSS would cause a page fault. Other processors may generate a VM exit due to a task switch even if accessing 
either TSS would cause a page fault.
If an attempt at a task switch through a task gate in th e IDT causes an exception (before generating a VM exit due 
to the task switch) and that exception causes a VM exit, information about the event whose delivery that accessed the task gate is recorded in the IDT-vectoring informatio n fields and information about the exception that caused 
the VM exit is recorded in the VM-exit interruption-informat ion fields. See Section 28.2. The fact that a task gate 
was being accessed is not recorded in the VMCS.
If an attempt at a task switch through a task gate in the IDT causes VM exit due to the task switch, information 
about the event whose delivery accessed the task gate is recorded in the IDT-vectoring fields of the VMCS. Since 
the cause of such a VM exit is a task switch and not an interruption, the valid bit for the VM-exit interruption infor-
mation field is 0. See Section 28.2.
26.4.3 Shadow-Stack Updates
As noted in Section 17.2.3, “Superviso r Shadow Stack Token,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1, a switch of shadow stack ma y occur as part of IDT event delivery or an execution of 
far CALL that changes the CPL, or as part of IDT ev ent delivery that uses the interrupt stack table (IST).
As part of the shadow-stack switch, the processor gains exclusive access to the new stack through manipulation of 
the supervisor shadow stack token  located at the base of the new shadow stack. The processor reads the token 
and, among other things, confirms that bit 0 of the token (its busy bit ) is 0. If the busy bit is already 1, the tran-
sition (event delivery or far CALL) cause a general-protecti on fault and does not complete. If the busy bit is 0, the 
transition sets the busy bit by writing to the token in memo ry. (The update is atomic with the original read of the 
token.)
If the transition commenced with CPL < 3, it will follow the token update by pushing three items on the new shadow 
stack (for the old values of the CS selector, instruction pointer, and shadow-stack pointer). As noted in Section 17.2.3 of the Intel
® 64 and IA-32 Architectures Software Develope r’s Manual, Volume 1, if any of the pushes 
causes a VM exit, the processor will revert to the old sh adow stack and the busy bit in the new shadow stack's 
token remains set. The new shadow stack is said to be prematurely busy.
If the “prematurely busy shadow stack” VM-exit control is  1, a VM exit that results in a shadow stack becoming 
prematurely busy will indicate that fact through information saved in the VMCS. See Section 28.2.1.
26.5 FEATURES SPECIFIC TO  VMX NON-ROOT OPERATION
Some VM-execution controls support features that are specific to VMX non-root operation. These are the VMX-
preemption timer (Section 26.5.1) and the monitor trap flag (Section 26.5.2), translation of guest-physical 
addresses (Section 26.5.3 and Section 26.5.4), APIC vi rtualization (Section 26.5.5), VM functions (Section 
26.5.6), and virtualization exceptions (Section 26.5.7).
26.5.1 VMX-Preemption Timer
If the last VM entry was performed with the 1-setting of “activate VMX-preemption timer” VM-execution control, 
the VMX-preemption timer  counts down (from the value loaded by VM entry; see Section 27.7.4) in VMX non-
root operation. When the timer counts down to zero, it stops counting down and a VM exit occurs (see Section 
26.2).
The VMX-preemption timer counts down at rate proportional  to that of the timestamp counter (TSC). Specifically, 
the timer counts down by 1 every time bit X in the TSC changes due to a TSC increment. The value of X is in the 
range 0–31 and can be determined by consulting the VMX capability MSR IA32_VMX_MISC (see Appendix A.6).
The VMX-preemption timer operates in the C-states C0, C1, and C2; it also operates in the shutdown and wait-for-
SIPI states. If the timer counts down to zero in any stat e other than the wait-for SIPI state, the logical processor Vol. 3C 26-15VMX NON-ROOT OPERATION
transitions to the C0 C-state and causes a VM exit; the timer does not cause a VM exit if it counts down to zero in 
the wait-for-SIPI state. The timer is not decremented in C-states deeper than C2.
Treatment of the timer in the case of system mana gement interrupts (SMIs) and system-management mode 
(SMM) depends on whether the treatment of SMIs and SMM:
•If the default treatment of SMIs and SMM (see Sectio n 32.14) is active, the VMX-preemption timer counts 
across an SMI to VMX non-root operation, subsequent ex ecution in SMM, and the return from SMM via the RSM 
instruction. However, the timer can cause a VM exit only  from VMX non-root operation. If the timer expires 
during SMI, in SMM, or during RSM, a timer-induced VM exit occurs immediately after RSM with its normal 
priority unless it is blocked based on activity state (Section 26.2).
•If the dual-monitor treatment of SMIs and SMM (see Sect ion 32.15) is active, transitions into and out of SMM 
are VM exits and VM entries, respectively. The treatment of the VMX-preemption timer by those transitions is

are VM exits and VM entries, respectively. The treatment of the VMX-preemption timer by those transitions is 
mostly the same as for ordinary VM exits and VM en tries; Section 32.15.2 and Section 32.15.4 detail some 
differences.
26.5.2 Monitor Trap Flag
The monitor trap flag  is a debugging feature that causes VM exits to occur on certain instruction boundaries in 
VMX non-root operation. Such VM exits are called MTF VM exits . An MTF VM exit may occur on an instruction 
boundary in VMX non-root operation as follows:
•If the “monitor trap flag” VM-execution control is 1 and VM entry is injecting a vectored event (see Section 
27.6.1), an MTF VM exit is pending on the instructio n boundary before the first instruction following the 
VM entry.
•If VM entry is injecting a pending MTF VM exit (see Section 27.6.2), an MTF VM exit is pending on the 
instruction boundary before the first instruction following  the VM entry. This is the case even if the “monitor 
trap flag” VM-execution control is 0.
•If the “monitor trap flag” VM-execution control is 1, VM entry is not injecting an event, and a pending event 
(e.g., debug exception or interrupt) is delivered before an instruction can execute, an MTF VM exit is pending 
on the instruction boundary following deliver y of the event (or any nested exception).
•Suppose that the “monitor trap flag” VM-execution control is 1, VM entry is not injecting an event, and the first 
instruction following VM entry is a REP-prefixed string instruction:
— If the first iteration of the instruction causes a fault,  an MTF VM exit is pending on the instruction boundary 
following delivery of the fault (or any nested exception).
— If the first iteration of the instruction does not cause a fault, an MTF VM exit is pending on the instruction 
boundary after that iteration.
instruction following VM entry is the XBEGIN instruction. In  this case, an MTF VM exit is pending at the fallback 
instruction address of the XBEGIN instruction. This be havior applies regardless of whether advanced debugging 
of RTM transactional regions has been enabled (see Section 16.3.7, “RTM-Enabled Debugger Support,” of 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
instruction following VM entry is neither  a REP-prefixed string instruction or the XBEGIN instruction:
— If the instruction causes a fault, an MTF VM exit is pending on the instruction boundary following delivery of 
the fault (or any nested exception).1
— If the instruction does not cause a fault, an MTF VM exit is pending on the instruction boundary following 
execution of that instruction. If the instruction is IN T1, INT3, or INTO, this boundary follows delivery of any 
software exception. If the instruction is INT n, this boundary follows delivery of a software interrupt. If the 
instruction is HLT, the MTF VM exit will be from the HLT activity state.
No MTF VM exit occurs if another VM exit occurs before re aching the instruction boundary on which an MTF VM exit 
would be pending (e.g., due to an exception or triple fault).
1. This item includes the cases of an invalid opcode exception—#UD— generated by the UD0, UD1, and UD2 instructions and a BOUND-
range exceeded exception—#BR—generated by the BOUND instruction.26-16 Vol. 3CVMX NON-ROOT OPERATION
An MTF VM exit occurs on the instruction boundary on wh ich it is pending unless a higher priority event takes 
precedence or the MTF VM exit is blocked due to the activity state:
•System-management interrupts (SMIs), INIT signals, an d higher priority events take priority over MTF 
VM exits. MTF VM exits take priority over debu g-trap exceptions and lower priority events.
•No MTF VM exit occurs if the processor is in either the sh utdown activity state or wait-for-SIPI activity state. If 
a non-maskable interrupt subsequently takes the logical processor out of the shutdown activity state without 
causing a VM exit, an MTF VM exit is pending after delivery of that interrupt.
Special treatment may apply to Intel SGX instructions or if the logical processor is in enclave mode. See Section 
40.2 for details.
26.5.3 Translation of Guest-Physical Addresses Using EPT
The extended page-table mechanism (EPT) is a feature that can be used to support the virtualization of physical 
memory. When EPT is in use, certain physical addresses are treated as guest-physical addresses and are not used 
to access memory directly. Instead, guest-physical addre sses are translated by traversing a set of EPT paging 
structures to produce physical addresses that are used to access memory.
Details of the EPT mechanism are given in Section 29.3.
26.5.4 Translation of Guest-Physical Addr esses Used by Intel Processor Trace
As described in Chapter 33, Intel® Processor Trace (Intel PT) captures information about software execution using 
dedicated hardware facilities.
Intel PT can be configured so that the trace output is wr itten to memory using physical addresses. For example, 
when the ToPA (table of physical addresses) outp ut mechanism is used, the IA32_RTIT_OUTPUT_BASE MSR 
contains the physical address of the base of the current ToPA. Each entry in that table contains the physical address 
of an output region in memory. When an output region  becomes full, the ToPA output mechanism directs subse-
quent trace output to the next output region as indicated in the ToPA.
When the “Intel PT uses guest physical addresses” VM-e xecution control is 1, the logical processor treats the 
addresses used by Intel PT (the output addresses as well as those used to discover the output addresses) as guest-
physical addresses, translating to physical addresses using EPT before trace output is written to memory.
Translating these addresses through EPT implies that th e trace-output mechanism may cause EPT violations and 
VM exits; details are provided in Section 26.5.4.1. Sectio n 26.5.4.2 describes a mechanism that ensures that these 
VM exits do not cause loss of trace data.
26.5.4.1  Guest-Physical Address Translation for Intel PT: Details
When the “Intel PT uses guest physical addresses” VM-exe cution control is 1, the addresses used by Intel PT are 
treated as guest-physical addresses and translated using EPT. These addresses include the addresses of the output 
regions as well as the addresses of the ToPA entries that contain the output-region addresses.
Translation of accesses by the trace-output process may result in EPT violations or EPT misconfigurations (Section 
29.3.3), resulting in VM exits. EPT violations resulting for the trace-output process always cause VM exits and are never converted to virtualization exceptions (Section 26.5.7.1).
If no EPT violation or EPT misconfiguration occurs and if page-modification logging (Secti on 29.3.6) is enabled, the 
address of an output region may be added to the page-modification log. If the log is full, a page-modification log-
full event occurs, resulting in a VM exit.
If the “virtualize APIC accesses” VM-execution control is  1, a guest-physical address used by the trace-output 
process may be translated to an address on the APIC-a ccess page. In this case, the access by the trace-output 
process causes an APIC-access VM exit as discussed in Section 30.4.6.1.Vol. 3C 26-17VMX NON-ROOT OPERATION
26.5.4.2  Trace-Addre ss Pre-Translation (TAPT)
Because it buffers trace data produced by Intel PT before it is written to memory, the processor ensures that buff-
ered data is not lost when a VM exit disables Intel PT. Specifically, the processor ensures that there is sufficient 
space left in the current output page for the buffered data. If this were not done, buffered trace data could be lost 
and the resulting trace corrupted.
To prevent the loss of buffered trace data, the processor uses a mechanism called trace-address pre-translation  
(TAPT ). With TAPT, the processor translates using EPT the guest-physical address of the current output region 
before that address would be used to write buffered trace data to memory.
Because of TAPT, no translation (and thus no EPT violation) occurs at the time output is written to memory; the 
writes to memory use translations that were cached as part  of TAPT. (The details given in Section 26.5.4.1 apply to 
TAPT.) TAPT ensures that, if a write to the output region would cause an EPT violation, the resulting VM exit is deliv-
ered at the time of TAPT, before the region would be used. This allows software to resolve the EPT violation at that 
time and ensures that, when it is necessary to write buffered trace data to memory, that data will not be lost due to an EPT violation.
TAPT (and resulting VM exits) may occur at any of the following times:
•When software in VMX non-root operation enables tr acing by loading the IA32_ RTIT_CTL MSR to set the 
TraceEn bit, using the WRMSR instruction or the XRSTORS instruction.

Any VM exit resulting from TAPT in this case is tr ap-like: the WRMSR or XRSTORS completes before the
VM exit occurs (for example, the valu e of CS:RIP saved in the guest-stat e area of the VMCS references the
next instruction).
•At an instruction boundary when one output region be comes full and Intel PT transitions to the next output 
region.
VM exits resulting from TAPT in this case take priority  over any pending debug exceptions. Such a VM exit will
save information about such exceptions in the guest-state area of the VMCS.
•As part of a VM entry that enables Intel PT. See Section 27.5 for details.
TAPT may translate not only the guest-physical address of the current output region but those of subsequent 
output regions as well. (Doing so ma y provide better protection of trace data.) This implies that any VM exits 
resulting from TAPT may result from the translation of output-region addresses other than that of the current 
output region.
26.5.5 APIC Virtualization
APIC virtualization is a collection of features that can be used to support the virtua lization of interrupts and the 
Advanced Programmable Interrupt Controller (APIC). When APIC virtualization is enabled, the processor emulates 
many accesses to the APIC, tracks the state of the virt ual APIC, and delivers virtual interrupts — all in VMX non-
root operation without a VM exit.
Details of the APIC virtualization are given in Chapter 30.
26.5.6 VM Functions
A VM function  is an operation provided by the processor that can be invoked from VMX non-root operation 
without a VM exit. VM functions are enabled and configured by the settings of different fields in the VMCS. Soft-
ware in VMX non-root operation invokes a VM function with the VMFUNC  instruction; the value of EAX selects the 
specific VM function being invoked.
Section 26.5.6.1 explains how VM functions are enabled. Section 26.5.6.2 specifies the behavior of the VMFUNC 
instruction. Section 26.5.6.3 describes a specific VM function called EPTP switching .
26.5.6.1  Enabling VM Functions
Software enables VM functions generally by setting the “e nable VM functions” VM-execu tion control. A specific 
VM function is enabled by setting th e corresponding VM-function control.26-18 Vol. 3CVMX NON-ROOT OPERATION
Suppose, for example, that software wants to enable EPTP switching (VM function 0; see Section 25.6.14).To do 
so, it must set the “activate secondary controls” VM-execu tion control (bit 31 of the primary processor-based VM-
execution controls), the “enable VM functions” VM-executi on control (bit 13 of the secondary processor-based VM-
execution controls) and the “EPTP switching” VM-func tion control (bit 0 of the VM-function controls).
26.5.6.2  General Operation of the VMFUNC Instruction
The VMFUNC instruction causes an invalid-opcode except ion (#UD) if the “enable VM functions” VM-execution 
controls is 01 or the value of EAX is greater than 63 (only VM fu nctions 0–63 can be enable). Otherwise, the instruc-
tion causes a VM exit if the bit at position EAX is 0 in the VM-function controls (the selected VM function is not 
enabled). If such a VM exit occurs, the basic exit reason used is 59 (3BH), indicating “VMFUNC”, and the length of 
the VMFUNC instruction is saved into the VM-exit instruct ion-length field. If the instruction causes neither an 
invalid-opcode exception nor a VM exit due to a disabl ed VM function, it performs the functionality of the 
VM function specified by the value in EAX.
Individual VM functions may perform additional fault checking (e.g., one might cause a general-protection excep-
tion if CPL > 0). In addition, specific VM functions may in clude checks that might result in a VM exit. If such a 
VM exit occurs, VM-exit information is saved as described in the previous paragraph. The specification of a 
VM function may indicate that additional VM-exit information is provided.
The specific behavior of the EPTP-switching VM function (i ncluding checks that result in VM exits) is given in 
Section 26.5.6.3.
26.5.6.3  EPTP Switching
EPTP switching is VM function 0. This VM function allows software in VMX non-root operation to load a new value 
for the EPT pointer (EPTP), thereby esta blishing a different EPT paging-structu re hierarchy (see Section 29.3 for 
details of the operation of EPT). Software is limited to sele cting from a list of potentia l EPTP values configured in 
advance by software in VMX root operation.
Specifically, the value of ECX is used to select an entry from the EPTP list, the 4-KByte structure referenced by the 
EPTP-list address (see Section 25.6.14; because this structure contains 512 8-Byte entries, VMFUNC causes a 
VM exit if ECX ≥ 512). The EPTP value in the selected entry is eval uated to determine whether it is valid for EPTP 
switching: a value is valid if (1) it is the same as the cu rrent EPTP value in bits 5:3 (these bits specify the EPT page-
walk length); and (2) it would not cause VM entry to fail (see Section 27.2.1.1). If the value is invalid, a VM exit 
occurs. Otherwise, the value is stored in the EPTP field of the current VMCS and is used for subsequent accesses 
using guest-physical addresses. The fo llowing pseudocode provides details:
IF ECX ≥ 512
THEN VM exit;ELSE
tent_EPTP := 8 bytes from EPTP-list address + 8 * ECX;IF tent_EPTP is not a valid EPTP value (would cause VM entr y to fail if in EPTP or change EPT page-walk length)
write tent_EPTP to the EPTP field in the current VMCS;
use tent_EPTP as the new EPTP value for address translation;IF processor supports the 1-setting of the “EPT-violation #VE” VM-execution control
THEN
write ECX[15:0] to EPTP-index field in current VMCS;use ECX[15:0] as EPTP index for subsequent EPT-violat ion virtualization exceptions (see Section 26.5.7.2);
FI;
FI;
FI;
Execution of the EPTP-switching VM function does not modi fy the state of any registers; no flags are modified.
1. “Enable VM functions” is a secondary processor-based VM-execution  control. If bit 31 of the primary processor-based VM-executio n 
controls is 0, VMX non-root operation functions as if the “enable VM functions” VM-execution control were 0. See Section 25.6.2.Vol. 3C 26-19VMX NON-ROOT OPERATION
If the “Intel PT uses guest physical addresses” VM-exe cution control is 1 and IA32_RTIT_CTL.TraceEn = 1, any 
execution of the EPTP-switching VM function causes a VM exit.1
As noted in Section 26.5.6.2, an execution of the EPTP-switching VM function that causes a VM exit (as specified above), uses the basic exit reason 59, indicating “VMFUNC” . The length of the VMFUNC in struction is saved into the 
VM-exit instruction-length field. No addi tional VM-exit information is provided.
An execution of VMFUNC loads EPTP from the EPTP list (a nd thus does not cause a fault or VM exit) is called an 
EPTP-switching VMFUNC . After an EPTP-switching VMFUNC, control pa sses to the next instruction. The logical 
processor starts creating and using guest-physical and co mbined mappings associated with the new value of bits 
51:12 of EPTP; the combined mappings created and used ar e associated with the current VPID and PCID (these are 
not changed by VMFUNC).
2 If the “enable VPID” VM-execution control is  0, an EPTP-switching VMFUNC invalidates 
combined mappings associated with VPID 0000H (for all PCIDs and for all EPTRTA values, where EPTRTA is the 
value of bits 51:12 of EPTP).
Because an EPTP-switching VMFUNC may change the translat ion of guest-physical addresses, it may affect use of 
the guest-physical address in CR3. The EPTP-switching VM FUNC cannot itself cause a VM exit due to an EPT viola-
tion or an EPT misconfiguration due to the translation of that guest-physical address through the new EPT paging 
structures. The following items provide details that apply if CR0.PG = 1:
•If 32-bit paging or 4-level paging3 is in use (either CR4.PAE = 0 or IA32_EFER.LMA = 1), the next memory 
access with a linear address uses the translation of th e guest-physical address in CR3 through the new EPT 
paging structures. As a result, this access may cause a VM exit due to an EPT violation or an EPT misconfigu-
ration encountered during that translation.
•If PAE paging is in use (CR4.PAE = 1 and IA 32_EFER.LMA = 0), an EPTP-switching VMFUNC does not  load the 
four page-directory-pointer-table entries (PDPTEs) fr om the guest-physical address in CR3. The logical 
processor continues to use the four guest-physical addresses already present in the PDPTEs. The guest-
physical address in CR3 is not translated through the new EPT paging structures (until some operation that would load the PDPTEs).
The EPTP-switching VMFUNC cannot itself cause a VM exit  due to an EPT violation or an EPT misconfiguration
encountered during the translation of a guest-physical  address in any of the PDPTEs. A subsequent memory
access with a linear address uses the translation of the guest-physical address in the appropriate PDPTE
through the new EPT paging structures. As a result, such an access may cause a VM exit due to an EPT

violation or an EPT misconfiguration encountered during that translation.
If an EPTP-switching VMFUNC establishes an EPTP value that enables accessed and dirty flags for EPT (by setting 
bit 6), subsequent memory accesses may fail to set those flags as specified if there has been no appropriate execu-
tion of INVEPT since the last use of an EPTP value that does not enable accessed and dirty flags for EPT (because 
bit 6 is clear) and that is identical to the new value on bits 51:12.
IF the processor supports the 1-setting of the “EPT-viola tion #VE” VM-execution control, an EPTP-switching 
VMFUNC loads the value in ECX[15:0] in to to EPTP-index field in current VM CS. Subsequent EPT-violation virtual-
ization exceptions will save this value into the virtua lization-exception information area (see Section 26.5.7.2).
26.5.7 Virtualization Exceptions
A virtualization exception  is a new processor exception. It uses vector 20 and is abbreviated #VE.
A virtualization exception can occur only in VMX non-root operation. Virtualization exceptions occur only with 
certain settings of certain VM-execution controls. Generally,  these settings imply that certain conditions that would 
normally cause VM exits instead cause virtualization exceptions
In particular, the 1-setting of the “EPT-violation #VE” VM-e xecution control causes some EPT violations to generate 
virtualization exceptions instead of VM exits. Section 26 .5.7.1 provides the details of how the processor deter-
mines whether an EPT violation causes a virtualization exception or a VM exit.
1. Such a VM exit ensures the proper recording of trace data that might otherwise be lost during the change of EPT paging-structu re 
hierarchy. Software handling the VM exit can change emulate the VM function and then resume the guest.
2. If the “enable VPID” VM-execution control is 0, the current VPID is 0000H; if CR4.PCIDE = 0, the current PCID is 000H.
3. Earlier versions of this manual used the term “IA-32e paging” to identify 4-level paging.26-20 Vol. 3CVMX NON-ROOT OPERATION
When the processor encounters a virtualization exception, it saves information about the exception to the virtual-
ization-exception information area; see Section 26.5.7.2.
After saving virtualization-exception information, the processor delivers a virtualization exception as it would any 
other exception; see Section 26.5.7.3 for details.
26.5.7.1  Convertible EPT Violations
If the “EPT-violation #VE” VM-execution  control is 0 (e.g., on processors that do not support this feature), EPT 
violations always cause VM exits. If instead the control is 1, certain EPT violations may be converted to cause virtu-
alization exceptions instead; such EPT violations are convertible . 
The values of certain EPT paging-structure entries determ ine which EPT violations are convertible. Specifically, 
bit 63 of certain EPT paging-structure entries may be defined to mean suppress #VE :
•If bits 2:0 of an EPT paging-structure entry are all 0, the entry is not present .1 If the processor encounters 
such an entry while translating a guest-physical address, it causes an EPT violation. The EPT violation is 
convertible if and only if bit 63 of the entry is 0.
•If an EPT paging-structure entry is present, the following cases apply:
— If the value of the EPT paging-structure entry is not supported, the entry is misconfigured . If the 
processor encounters such an entry while translating a guest-physical address, it causes an EPT misconfig-uration (not an EPT violation). EPT misconfigurations always cause VM exits.
— If the value of the EPT paging-structure en try is supported, the following cases apply:
•If bit 7 of the entry is 1, or if the entry is an EPT PTE, the entry maps a page. If the processor uses such 
an entry to translate a guest-physical address, and if  an access to that address causes an EPT violation, 
the EPT violation is convertible if an d only if bit 63 of the entry is 0.
•If bit 7 of the entry is 0 and the entry is not an  EPT PTE, the entry references another EPT paging 
structure. The processor does not use the value of bit 63 of the entry to determine whether any 
subsequent EPT violation is convertible.
If an access to a guest-physical address causes an EPT vi olation, bit 63 of exactly one of the EPT paging-structure 
entries used to translate that address is used to determin e whether the EPT violation is convertible: either a entry 
that is not present (if the guest-physical address does not translate to a physical address) or an entry that maps a 
page (if it does).
A convertible EPT violation instead causes a virtualization exception if the following all hold:
•CR0.PE = 1;
•the logical processor is not in the process of delivering an event through the IDT; 
•the EPT violation did not cause a shadow stack to become prematurely busy (see Section 26.4.3);
•the EPT violation does not result from the output pr ocess of Intel Processor Trace (Section 26.5.4); and
•the 32 bits at offset 4 in the virtualization-exception information area are all 0.
Delivery of virtualization exceptions writes the value FFFF FFFFH to offset 4 in the virtualization-exception informa-
tion area (see Section 26.5.7.2). Thus, once a virtualization exception occurs, another can occur only if software clears this field.
26.5.7.2  Virtualization-Exception Information
Virtualization exceptions save data into the virtualiza tion-exception information area (see Section 25.6.20). 
Table 26-1 enumerates the data saved and the format of the area.
A VMM may allow guest software to access the virtualization -exception information area. If it does, the guest soft-
ware may modify that memory (e.g., to clear the 32-bit value at offset 4; see Section 26.5.7.1). (This is an excep-tion to the general requirement given in Section 25.11.4.)
1. If the “mode-based execute control for EPT” VM-execution control is 1, an EPT paging-structure entry is present if any of bit s 2:0 or 
bit 10 is 1.Vol. 3C 26-21VMX NON-ROOT OPERATION
26.5.7.3  Delivery of Virtualization Exceptions
After saving virtualization-exception information, the processor treats a virtualization exception as it does other 
•If bit 20 (#VE) is 1 in the exception bitmap in the VMCS, a virtualization exception causes a VM exit (see 
below). If the bit is 0, the virtualization exceptio n is delivered using gate descriptor 20 in the IDT.
•Virtualization exceptions produce no error code. Delivery of a virtualization exception pushes no error code on 
the stack.
•With respect to double faults, virtualization exceptions ha ve the same severity as page faults. If delivery of a 
virtualization exception encounters a nested fault that is either contributory or a page fault, a double fault 
(#DF) is generated. See Chapter 6, “Interrupt  8—Double Fault Exception (#DF)” in Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 3A.
It is not possible for a virtualization exception to be encountered while delivering another exception (see
Section 26.5.7.1).
If a virtualization exception causes a VM exit directly (b ecause bit 20 is 1 in the exception bitmap), information 
about the exception is saved normally in the VM-exit in terruption information field in the VMCS (see Section 
28.2.2). Specifically, the event is reported as a hardware exception with vector 20 and no error code. Bit 12 of the 
field (NMI unblocking due to IRET) is set normally.
If a virtualization exception causes a VM exit indirectly (b ecause bit 20 is 0 in the exception bitmap and delivery of 
the exception generates an event that causes a VM exit), information about the exception is saved normally in the 
IDT-vectoring information field in the VMCS (see Section 28. 2.4). Specifically, the event is reported as a hardware 
exception with vector 20 and no error code.
26.5.8 PASID Translation
The ENQCMD and ENQCMDS instructions each performs a 64-byte enqueue store that includes a 20-bit PASID 
value in bits 19:0. For ENQCMD, the PASID is normally the value of IA32_PASID[19:0], while for ENQCMDS, the 
PASID is normally read from memory.
If the “PASID translation” VM-execution control is 1, the PASID value identified in the previous paragraph is treated 
as a guest PASID . PASID translation converts this guest PASID to a 20-bit host PASID . After this translation, the 
enqueue store is performed, using the ho st PASID in place of the guest PASID.
PASID translation is implemented by two hierarchies of data structures ( PASID-translation hierarchies ) config-
ured by a VMM. Guest PASIDs 00000H to 7FFFFH are transl ated through the low PASID-translation hierarchy, while 
guest PASIDs 80000 to FFFFFH are translated through the high PASID-translation hierarchy.Table 26-1.  Format of the Virtua lization-Exception Information Area
0 The 32-bit value that would have been saved into the VMCS  as an exit reason ha d a VM exit occurred 
instead of the virtualization exception. For EPT violations, this value is 48 (00000030H)

4 FFFFFFFFH8 The 64-bit value that would have been saved into the VMCS as an exit qualification had a VM exit 
occurred instead of the virtualization exception
16 The 64-bit value that would have been saved into the VMCS as a guest-linear address had a VM exit 
24 The 64-bit value that would have be en saved into the VMCS as a guest- physical  address had a VM 
exit occurred instead of the virtualization exception
32 The current 16-bit value of the EPTP index VM-execution control (see Section 25.6.20 and Section 
26.5.6.3)26-22 Vol. 3CVMX NON-ROOT OPERATION
The root of each PASID-translation hierarchy is a 4-KByte PASID directory . The low PASID directory is located at 
the low PASID directory address, and the high PASID directory is located at the high PASID directory address (these physical addresses are VM-execution control fields  in the VMCS). A PASID directory comprises 512 8-byte 
entries, each of which has the following format:
•Bit 0 is the entry’s present bit. The entry is used only if this bit is 1.
•Bits 11:1 are reserved and must be 0.
•Bits M–1:12 specify the 4-KByte aligned address of a PASID table (see below), where M is the processor’s 
physical-address width.
•Bits 63:M are reserved and must be 0.
A PASID-translation hierarchy also includes up to 512 4-KByte PASID tables ; each of these is referenced by a 
PASID directory entry (see above). A PASID table comprise s 1024 4-byte entries, each of which has the following 
format:
•Bits 19:0 are the host PASID specified by the entry.
•Bits 30:20 are reserved and must be 0.
•Bits 31 is the entry’s valid  bit. The entry is used only if this bit is 1.
When PASID translation is enabled, the guest PASID determ ined by the instruction (see above) is converted to a 
host PASID using the following process:
•If bit 19 of guest PASID is clear, the low PASID director y is used; otherwise, the high PASID directory is used.
•Bits 18:10 of the guest PASID select an entry from the PA SID directory. A VM exit occurs if the entry’s present 
bit is clear or if any reserved bit is set. Otherwise, bi ts M:0 of the entry (with bit 0 cleared) contain the physical 
address of a PASID table.
•Bits 9:0 of the guest PASID select an entry from the PASID table. A VM exit occurs if the entry’s valid bit is clear 
or if any reserved bit is set. Otherwise,  bits 19:0 of the entry are the host PASID.
If PASID translation results in a VM exit (due to a present or valid bit being clear, or a reserved bit being set), the 
instruction does not complete and no enqueue store is performed.
26.6 UNRESTRICTED GUESTS
The first processors to support VMX operation require CR0. PE and CR0.PG to be 1 in VMX operation (see Section 
24.8). This restriction implies that guest software cannot be run in unpaged protected mode or in real-address mode. Later processors support a VM-execution control called “unrestricted guest”.
1 If this control is 1, CR0.PE and 
CR0.PG may be 0 in VMX non-root operation. Such proce ssors allow guest software to run in unpaged protected 
mode or in real-address mode. The following items describe the behavior of such software:
•The MOV CR0 instructions does not cause a general-protection exception simply because it would set either CR0.PE and CR0.PG to 0. See Section 26.3 for details.
•A logical processor treats the values of CR0.PE and CR0.PG in VMX non-root operation just as it does outside 
VMX operation. Thus, if CR0.PE = 0, the processor operates as it does normally in real-address mode (for 
example, it uses the 16-bit interrupt table  to deliver interrupts and exceptions). If CR0.PG = 0, the processor 
operates as it does normally when paging is disabled.
•Processor operation is modified by the fact that the processor is in VMX non-root operation and by the settings 
of the VM-execution controls just as it is in protected mode or when paging is enab led. Instructions, interrupts, 
and exceptions that cause VM exits in protected mode or  when paging is enabled also do so in real-address 
mode or when paging is disabled. Th e following examples should be noted:
— If CR0.PG = 0, page faults do not occur and thus cannot cause VM exits.— If CR0.PE = 0, invalid-TSS exceptions do not occur and thus cannot cause VM exits.
controls is 0, VMX non-root operation functions as if the “unrestricted guest” VM-execution control were 0. See Section 25.6.2.Vol. 3C 26-23VMX NON-ROOT OPERATION
— If CR0.PE = 0, the following instructions cause inva lid-opcode exceptions and do not cause VM exits: 
INVEPT, INVVPID, LLDT, LTR, SLDT, STR, VMCLEAR, VMLAUNCH, VMPTRLD, VMPTRST, VMREAD, VMRESUME, VMWRITE, VMXOFF, and VMXON.
•If CR0.PG = 0, each linear address is passed directly to the EPT mechanism for translation to a physical 
address.1 The guest memory type passed on to the EPT mechanism is WB (writeback).
1. As noted in Section 27.2.1.1, the “enable EPT” VM-execution control must be 1 if th e “unrestricted guest”  VM-execution contro l is 1.26-24 Vol. 3CVMX NON-ROOT OPERATIONVol. 3C 27-1CHAPTER 27
VM ENTRIES
Software can enter VMX non-root operation using either of the VM-entry instructions VMLAUNCH and VMRESUME. 
VMLAUNCH can be used only with a VMCS whose launch st ate is clear and VMRESUME can be used only with a 
VMCS whose the launch state is launched. VMLAUNCH should  be used for the first VM entry after VMCLEAR; VMRE-
SUME should be used for subsequent VM entries with the same VMCS.
Each VM entry performs the following steps in the order indicated:
1. Basic checks are performed to ensure th at VM entry can commence (Section 27.1).
2. The control and host-state areas of the VMCS are checke d to ensure that they are proper for supporting VMX 
non-root operation and that the VMCS is correctly co nfigured to support the next VM exit (Section 27.2).
3. The following may be performed in parallel or in any order (Section 27.3):
•The guest-state area of the VMCS is checked to ensure  that, after the VM entry completes, the state of the 
logical processor is consistent with IA-32 and Intel 64 architectures.
•Processor state is loaded from the guest-stat e area and based on controls in the VMCS.
•Address-range monitoring is cleared.
4. MSRs are loaded from the VM-entry MSR-load area (Section 27.4).5. If VMLAUNCH is being executed, the launch state of the VMCS is set to “launched.”
6. If the “Intel PT uses guest physical addresses” VM-exe cution control is 1, trace-address pre-translation (TAPT) 
may occur (see Section 26.5.4 and Section 27.5).
7. An event may be injected in the guest context (Section 27.6).
Steps 1–4 above perform checks that may cause VM entry to fail. Such failures occur in one of the following three 
ways:
•Some of the checks in Section 27.1 may generate ordina ry faults (for example, an invalid-opcode exception). 
Such faults are delivered normally.
•Some of the checks in Section 27.1 and all the checks in Section 27.2 cause control to pass to the instruction 
following the VM-entry instruction. The failure is indicated by setting RFLAGS.ZF1 (if there is a current VMCS) 
or RFLAGS.CF (if there is no current VMCS). If there is  a current VMCS, an error number indicating the cause of 
the failure is stored in the VM-instruction e rror field. See Chapter 31 for the error numbers.
•The checks in Section 27.3 and Section 27.4 cause processo r state to be loaded from the host-state area of the 
VMCS (as would be done on a VM exit). Information about the failure is stored in the VM-exit information fields. See Section 27.8 for details.
EFLAGS.TF = 1 causes a VM-entry instruction to generate a single-step debug exception only  if failure of one of the 
checks in Section 27.1 and Section 27.2 causes control to pass to the following instruction. A VM-entry does not 
generate a single-step debug exception in any of the following cases: (1) the instruction generates a fault; (2) 
failure of one of the checks in Section 27.3 or in loading MSRs causes processor state to be loaded from the host-state area of the VMCS; or (3) the instruction passes all checks in Section 27.1, Section 27.2, and Section 27.3 and 
there is no failure in loading MSRs.
Section 32.15 describes the dual-monitor treatment of system-management interrupts (SMIs) and system-
management mode (SMM). Under this treatment, code runn ing in SMM returns using VM entries instead of the RSM 
instruction. A VM entry returns from SMM  if it is executed in SMM and the “entry to SMM” VM-entry control is 0. 
VM entries that return from SMM differ from ordinary VM entries in ways that are detailed in Section 32.15.4.
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. fo r processor registers because most processors that support VMX o per-
ation also support Intel 64 architecture. For  IA-32 processors, this nota tion refers to the 32-bit forms of those registers (EA X, EIP,

ation also support Intel 64 architecture. For  IA-32 processors, this nota tion refers to the 32-bit forms of those registers (EA X, EIP, 
ESP, EFLAGS, etc.). In a few places, notation such as EAX is us ed to refer specifically to lower 32 bits of the indicated regis ter.27-2 Vol. 3CVM ENTRIES
27.1 BASIC VM-ENTRY CHECKS
Before a VM entry commences, the current state of the logical processor is checked in the following order:
1. If the logical processor is in virtual-8086 mode or compatibility mode, an invalid-opcode exception is
2. If the current privilege level (CPL) is not ze ro, a general-protection exception is generated.
3. If there is no current VMCS, RFLAGS.CF is set to 1 and control passes to the next instruction.
4. If there is a current VMCS but the current VMCS is a shadow VMCS (see Section 25.10), RFLAGS.CF is set to 1 
and control passes to the next instruction.
5. If there is a current VMCS that is not a shadow VMCS, the following conditions are evaluated in order; any of 
these cause VM entry to fail:
a. If there is MOV-SS blocking (see Table 25-3).
b. If the VM entry is invoked by VMLAUNCH and the VMCS launch state is not clear.c. If the VM entry is invoked by VMRESUME and the VMCS launch state is not launched.
If any of these checks fail, RFLAGS.ZF is set to 1 and co ntrol passes to the next instruction. An error number 
indicating the cause of the failure is stored in the VM -instruction error field. See Chapter 31 for the error 
numbers.
27.2 CHECKS ON VMX CONT ROLS AND HOST-STATE AREA
If the checks in Section 27.1 do not cause VM entry to fail, the control and host-state areas of the VMCS are 
checked to ensure that they are proper for supporting VMX non-root operation, that the VMCS is correctly config-
ured to support the next VM exit, and that, after the next VM exit, the processor’s state is consistent with the Intel 
64 and IA-32 architectures.
VM entry fails if any of these checks fail. When such fail ures occur, control is passed to the next instruction, 
RFLAGS.ZF is set to 1 to indicate the failure, and the VM-i nstruction error field is loaded with an error number that 
indicates whether the failure was due to the controls or the host-state area (see Chapter 31).
These checks may be performed in any or der. Thus, an indication by error numb er of one cause (for example, host 
state) does not imply that there are not also other erro rs. Different processors may thus give different error 
numbers for the same VMCS. Some checks prevent establishm ent of settings (or combinations of settings) that are 
currently reserved. Future processors may allow such settings (or combinations) and may not perform the corre-
sponding checks. The correctness of software should not rely  on VM-entry failures resulting from the checks docu-
mented in this section.
The checks on the controls and the host-state area are presented in Section 27.2.1 through Section 27.2.4. These 
sections reference VMCS fields that correspond to processo r state. Unless otherwise stated, these references are to 
fields in the host-state area.
27.2.1 Checks on VMX Controls
This section identifies VM-entry checks on the VMX control fields.
27.2.1.1  VM-Execution Control Fields
VM entries perform the following checks on the VM-execution control fields:1
•Reserved bits in the pin-based VM-execution controls  must be set properly. Software may consult the VMX 
capability MSRs to determine the proper settings (see Appendix A.3.1).
1. If the “activate secondary cont rols” primary processor-based VM-execution control is 0, VM entry operates as if each secondary  pro-
cessor-based VM-execution co ntrol were 0. Similarly, if the “activate tertiary  controls” primary processor-based VM-execution c on-
trol is 0, VM entry oper ates as if each tertiary pr ocessor-based VM-execution control were 0. See Section 25.6.2.Vol. 3C 27-3VM ENTRIES
•Reserved bits in the primary processor-based VM-execution controls must be set properly. Software may 
consult the VMX capability MSRs to determin e the proper settings (see Appendix A.3.2).
•If the “activate secondary controls” primary processor-based VM-execution control is 1, reserved bits in the 
secondary processor-based VM-execution controls must be cleared. Software may consult the VMX capability 
MSRs to determine which bits are reserved (see Appendix A.3.3).
If the “activate secondary controls” primary processor- based VM-execution control is 0 (or if the processor
does not support the 1-setting of that control), no checks are performed on the secondary processor-based
VM-execution controls. The logical processor operates as if all the secondary processor-based VM-execution
controls were 0.
•If the “activate tertiary controls” primary processor-ba sed VM-execution control is 1, reserved bits in the 
tertiary processor-based VM-execution controls must be cleared. Software may consult the VMX capability 
MSRs to determine which bits are reserved (see Appendix A.3.4).
If the “activate tertiary controls” primary processor-based VM-execution control is 0 (or if the processor does
not support the 1-setting of that control), no checks  are performed on the tertiary processor-based VM-
execution controls. The logical processor operates as if all the tertiary processor-based VM-execution controlswere 0.
•The CR3-target count must not be greater than 4. Fu ture processors may support a different number of CR3-
target values. Software should read the VMX capabi lity MSR IA32_VMX_MISC to determine the number of 
values supported (see Appendix A.6).
•If the “use I/O bitmaps” VM-execution control is 1, bi ts 11:0 of each I/O-bitmap address must be 0. Neither 
address should set any bits beyond the processor’s physical-address width.1,2
•If the “use MSR bitmaps” VM-execution control is 1, bits 11:0 of the MSR-bitmap  address must be 0. The 
address should not set any bits beyond the processor’s physical-address width.3
•If the “use TPR shadow” VM-execution control is 1, the virtual-APIC address must satisfy the following checks:
— Bits 11:0 of the address must be 0.
— The address should not set any bits beyond the processor’s physical-address width.4
If all of the above checks are satisfied and the “use TP R shadow” VM-execution control is 1, bytes 3:1 of VTPR
(see Section 30.1.1) may be cleared (behavior may be implementation-specific).
The clearing of these bytes may occur even if the VM entry fails. This is true either if the failure causes control
to pass to the instruction following the VM-entry instruction or if it causes processor state to be loaded fromthe host-state area of the VMCS.
•If the “use TPR shadow” VM-execution control is 1 and th e “virtual-interrupt delivery” VM-execution control is 
0, bits 31:4 of the TPR threshold VM-execution control field must be 0.
•The following check is performed if the “use TPR shadow ” VM-execution control is 1 and the “virtualize APIC 
accesses” and “virtual-interrupt delivery” VM-execution controls are both 0: the value of bits 3:0 of the TPR 
threshold VM-execution control field should not be gr eater than the value of bits 7:4 of VTPR (see Section 
30.1.1).
•If the “NMI exiting” VM-execution control is 0, the “virtual NMIs” VM-execution control must be 0.
•If the “virtual NMIs” VM-execution control is 0, the “NMI-window exiting” VM-execution control must be 0.
•If the “virtualize APIC-accesses” VM-execution control is  1, the APIC-access address must satisfy the following 
checks:
— The address should not set any bits beyond the processor’s physical-address width.5
2. If IA32_VMX_BASIC[48] is read as 1, these addresses must  not set any bits in the ra nge 63:32; see Appendix A.1.
3. If IA32_VMX_BASIC[48] is read as 1,  this address must not set any bits in the range 63:32; see Appendix A.1.
4. If IA32_VMX_BASIC[48] is read as 1,  this address must not set any bits in the range 63:32; see Appendix A.1.
5. If IA32_VMX_BASIC[48] is read as 1,  this address must not set any bits in the range 63:32; see Appendix A.1.27-4 Vol. 3CVM ENTRIES
•If the “use TPR shadow” VM-execution control is 0, th e following VM-execution controls must also be 0: 
“virtualize x2APIC mode”, “APIC-register virtualization” , “virtual-interrupt delivery”, and “IPI virtualization”.
•If the “virtualize x2APIC mode” VM-execution control is 1, the “virtualize APIC accesses” VM-execution control 
must be 0.
•If the “virtual-interrupt delivery” VM-execution contro l is 1, the “external-interrupt exiting” VM-execution 
control must be 1.
•If the “process posted interrupts” VM-execution control is 1, the following must be true:
— The “virtual-interrupt delivery” VM-execution control is 1.
— The “acknowledge interrupt on exit” VM-exit control is 1.— The posted-interrupt notification vector has a value in the range 0–255 (bits 15:8 are all 0).
— Bits 5:0 of the posted-interrupt descriptor address are all 0.

must be 0.
— The posted-interrupt descriptor address does not set any bits beyond the processor's physical-address 
width.
1
•If the “IPI virtualization” VM-execution control is 1, the following must be true:
— Bits 2:0 of the PID-pointer table address are all 0.
— The PID-pointer table address does not set any bits beyond the processor’s physical-address width.— The address of the last entry in the PID-pointer table does not set any bits beyond the processor’s physical-
address width. (This address is the PID-pointer tabl e address plus 8 times the last PID-pointer index.)
•If the “enable VPID” VM-execution control is 1, the valu e of the VPID VM-execution control field must not be 
0000H.
•If the “enable EPT” VM-execution control is 1, the EPTP  VM-execution control field (see Table 25-9 in Section 
25.6.11) must satisfy the following checks:
— The EPT memory type (bits 2:0) must be a value supported by the processor as indicated in the 
IA32_VMX_EPT_VPID_CAP MSR (see Appendix A.10).
— Bits 5:3 must contain a value 1 less than an EPT page-walk length supported by the processor as indicated 
in the IA32_VMX_EPT_VPID_CAP MSR (see Section 29.3.2 and Appendix A.10).
— Bit 6 (enable bit for accessed and dirty flags for EPT)  must be 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP 
MSR (see Appendix A.10) is read as 0, indicating th at the processor does not support accessed and dirty 
flags for EPT.
— Reserved bits 11:7 and 63:N (where N is the processor’s physical-address width) must all be 0.
•The “enable EPT” VM-execution control must be 1 if any of the following VM-execution controls is 1: “enable 
PML,” “unrestricted guest,” “mode-based execute control for EPT,” “sub-page write permissions for EPT,” “Intel 
PT uses guest physical addresses,” “enable HLAT,” “EPT paging-write control,” or “guest-paging verification.”
•If the “enable PML” VM-execution control is 1, the PML address must satisfy the following checks:
— Bits 11:0 of the address must be 0.— The address should not set any bits beyond the processor’s physical-address width.
•If the “sub-page write permissions for EPT” VM-execution  control is 1, the SPPTP VM-execution control field 
(see Table 25-11 in Section 25.6.22) must satisfy the following checks:
— The address should not set any bits beyond the processor’s physical-address width.
•If the “enable VM functions” processor-based VM-executi on control is 1, reserved bits in the VM-function 
controls must be clear. Software may consult the VMX capability MSRs to determine which bits are reserved 
(see Appendix A.11). In addition, the following check is  performed based on the setting of bits in the VM-
function controls (see Section 25.6.14):
1. If IA32_VMX_BASIC[48] is re ad as 1, this address must not set any bi ts in the range 63:32; see Appendix A.1.Vol. 3C 27-5VM ENTRIES
— If “EPTP switching” VM-function control is 1, the “ena ble EPT” VM-execution control must also be 1. In 
addition, the EPTP-list address must satisfy the following checks:
•Bits 11:0 of the address must be 0.
•The address must not set any bits beyond the processor’s physical-address width.
If the “enable VM functions” processor-based VM-executi on control is 0, no checks are performed on the VM-
function controls.
•If the “VMCS shadowing” VM-execution control is 1, the VMREAD-bitmap and VMWRITE-bitmap addresses 
must each satisfy the following checks:
— The address must not set any bits beyond the processor’s physical-address width.
•If the “EPT-violation #VE” VM-execution control is 1,  the virtualization-exception information address must 
satisfy the following checks:
•If the logical processor is operating with Intel PT en abled (if IA32_RTIT_CTL.TraceEn = 1) at the time of 
VM entry, the “load IA32_RTIT_CTL” VM-entry control must be 0.
•If the “Intel PT uses guest physical addresses” VM-exe cution control is 1, the “load IA32_RTIT_CTL” VM-entry 
control and the “clear IA32_RTIT_CTL” VM-exit control must both be 1.
•If the “use TSC scaling” VM-execution control is 1, the TSC-multiplier must not be zero.
•If the “enable HLAT” VM-execution control is 1, the foll owing bits in the HLATP VM-execution control field (see 
Table 25-12 in Section 25.6.23) must be zero: bits 2:0,  bits 11:5, and bits beyond the processor’s physical-
address width.
•If the “PASID translation” VM-execution control is 1, the low PASID directory address and the high PASID 
directory address must each satisfy the following checks:
27.2.1.2  VM-Exit Control Fields
VM entries perform the following checks on the VM-exit control fields.
•Reserved bits in the primary VM-exit controls must be  set properly. Software may consult the VMX capability 
MSRs to determine the proper settings (see Appendix A.4.1).
•If the “activate secondary controls” primary VM-exit co ntrol is 1, reserved bits in the secondary VM-exit 
controls must be cleared. Software may consult the VMX capability MSRs to determin e which bits are reserved 
(see Appendix A.4.2).
•If the “activate secondary controls” primary VM-exit control is 0 (or if the processor does not support the 1-
setting of that control), no checks are performed on  the secondary VM-exit controls. The logical processor 
operates as if all the secondary VM-exit controls were 0.
•If the “activate VMX-preemption timer” VM-execution cont rol is 0, the “save VMX-preemption timer value” VM-
exit control must also be 0.
•The following checks are performed for the VM-exit MSR- store address if the VM-exit MSR-store count field is 
non-zero:
— The lower 4 bits of the VM-exit MSR-store address must be 0. The address should not set any bits beyond 
the processor’s physical-address width.1
width is returned in bits 7:0 of EAX.27-6 Vol. 3CVM ENTRIES
— The address of the last byte in the VM-exit MSR-stor e area should not set any bits beyond the processor’s 
physical-address width. The address of this last byte is VM-exit MSR-store address + (MSR count * 16) – 1. (The arithmetic used for the computation uses more  bits than the processor’s physical-address width.)
If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits in the range 63:32; see Appendix
A.1.
•The following checks are performed for the VM-exit MSR- load address if the VM-exit MSR-load count field is 
non-zero:
— The lower 4 bits of the VM-exit MSR-load address must  be 0. The address should not set any bits beyond 
the processor’s physical-address width.
— The address of the last byte in the VM-exit MSR-load  area should not set any bits beyond the processor’s 
physical-address width. The address of this last by te is VM-exit MSR-load address + (MSR count * 16) – 1. 
(The arithmetic used for the computation uses more  bits than the processor’s physical-address width.)
A.1.
27.2.1.3  VM-Entry Control Fields
VM entries perform the following checks on the VM-entry control fields.
•Reserved bits in the VM-entry controls must be set pr operly. Software may consult the VMX capability MSRs to 
determine the proper settings (see Appendix A.5).
•Fields relevant to VM-entry event injection must be set properly. These fields are the VM-entry interruption-
information field (see Table 25-17 in Section 25.8.3),  the VM-entry exception error code, and the VM-entry 
instruction length. If the valid bit (bit 31) in the VM-entry  interruption-information field is 1, the following must 
hold:
— The field’s interruption type (bits 10:8) is not set to a reserved value. Value 1 is reserved on all logical 
processors; value 7 (other event) is reserved on logical processors that do not support the 1-setting of the 
“monitor trap flag” VM-execution control.
— The field’s vector (bits 7:0) is consistent with the interruption type:
•If the interruption type is non-maskable interrupt (NMI), the vector is 2.
•If the interruption type is hardware exception, the vector is at most 31.
•If the interruption type is other event,  the vector is 0 (pending MTF VM exit).
— The field's deliver-error-code bit (bit 11) is 1 if ea ch of the following holds: (1) the interruption type is 
hardware exception; (2) bit 0 (corresponding to CR0.PE) is set in the CR0 field in the guest-state area; 
(3) IA32_VMX_BASIC[56] is read as 0 (see Appendix A. 1); and (4) the vector indicates one of the following 
exceptions: #DF (vector 8), #TS (10), #NP (11), #SS (12), #GP (13), #PF (14), or #AC (17).
— The field's deliver-error-code bit is 0 if any of the fo llowing holds: (1) the interruption type is not hardware

— The field's deliver-error-code bit is 0 if any of the fo llowing holds: (1) the interruption type is not hardware 
exception; (2) bit 0 is clear in the CR0 field in the guest-state area; or (3) IA32_VMX_BASIC[56] is read as 
0 and the vector is in one of the following ranges: 0–7, 9, 15, 16, or 18–31.
— Reserved bits in the field (30:12) are 0.
— If the deliver-error-code bit (bit 11) is 1, bits 31:16  of the VM-entry exception error-code field are 0.
— If the interruption type is software interrupt, software exception, or privileged software exception, the 
VM-entry instruction-length field is in the range 0–15. A VM-entry instruction length of 0 is allowed only if 
IA32_VMX_MISC[30] is read as 1; see Appendix A.6.
•The following checks are performed for the VM-entry MSR-load address if the VM-entry MSR-load count field is 
non-zero:
— The lower 4 bits of the VM-entry MSR-load address mu st be 0. The address should not set any bits beyond 
width is returned in bits 7:0 of EAX.Vol. 3C 27-7VM ENTRIES
— The address of the last byte in the VM-entry MSR-load  area should not set any bits beyond the processor’s 
physical-address width. The address of this last byte is VM-entry MSR-load address + (MSR count * 16) – 
1. (The arithmetic used for the computation uses mo re bits than the processor’s physical-address width.)
If IA32_VMX_BASIC[48] is read as 1, neither address sh ould set any bits in the range 63:32; see Appendix
A.1.
•If the processor is not in SMM, the “entry to SMM” an d “deactivate dual-monitor treatment” VM-entry controls 
must be 0.
•The “entry to SMM” and “deactivate dual-monitor treatment” VM-entry controls cannot both be 1.
27.2.2 Checks on Host Contro l Registers, MSRs, and SSP
The following checks are performed on fields in the host-state area that correspond to control registers and MSRs:
•The CR0 field must not set any bit to a value not supported in VMX operation (see Section 24.8).1
•The CR4 field must not set any bit to a value not supported in VMX operation (see Section 24.8).
•If bit 23 in the CR4 field (corresponding to CET) is  1, bit 16 in the CR0 field (WP) must also be 1.
•On processors that support Intel 64 architecture, the CR3 field must be such that bits 63:52 and bits in the 
range 51:32 beyond the processor’s physical-address width must be 0.2,3
•On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP 
field must each contain a canonical address.
•If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, bits reserved in the IA32_PERF_GLOBAL_CTRL MSR must be 0 in the field for that register (see Figure 20-3).
•If the “load IA32_PAT” VM-exit control is 1, the value of  the field for the IA32_PAT MSR must be one that could 
be written by WRMSR without fault at CP L 0. Specifically, each of the 8 byte s in the field must have one of the 
values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6 (WB), or 7 (UC-).
•If the “load IA32_EFER” VM-exit control is 1, bits reserv ed in the IA32_EFER MSR must be 0 in the field for that 
register. In addition, the values of the LMA and LME bits  in the field must each be that of the “host address-
space size” VM-exit control.
•If the “load CET state” VM-exit control is 1, the IA32_S_CET field must not set any bits reserved in the 
IA32_S_CET MSR, and bit 10 (corresponding to SUPPRESS ) and bit 11 (TRACKER) in the field cannot both be 
set.
•If the “load CET state” VM-exit control is 1, bits 1:0 must be 0 in the SSP field.
•If the “load PKRS” VM-exit control is 1, bits 63:32 must be 0 in the IA32_PKRS field.
27.2.3 Checks on Host Segment and Descriptor-Table Registers
The following checks are performed on fields in the ho st-state area that correspond to segment and descriptor-
table registers:
•In the selector field for each of CS, SS, DS, ES, FS, GS , and TR, the RPL (bits 1:0) and the TI flag (bit 2) must 
be 0.
•The selector fields for CS and TR cannot be 0000H.
•The selector field for SS cannot be 0000H if th e “host address-space size” VM-exit control is 0.
•On processors that support Intel 64 architecture, the base-address fields for FS, GS, GDTR, IDTR, and TR must 
contain canonical addresses.
1. The bits corresponding to CR0.NW (bit 29) and CR0.CD (bit 30) are never checked because the values of these bits are not chan ged 
by VM exit; see Section 28.5.1.
2. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address 
3. Bit 63 of the CR3 field in the host-state area must be 0. This is true even though, If CR4.PCIDE = 1, bit 63 of the source opera nd to 
MOV to CR3 is used to determine whether cached translation information is invalidated.27-8 Vol. 3CVM ENTRIES
27.2.4 Checks Related to Address-Space Size
On processors that support Intel 64 architecture, the foll owing checks related to address-space size are performed 
on VMX controls and fields in the host-state area:
•If the logical processor is outside IA-32e mode (if IA 32_EFER.LMA = 0) at the time of VM entry, the following 
must hold:
— The “IA-32e mode guest” VM-entry control is 0.
— The “host address-space size” VM-exit control is 0.
•If the logical processor is in IA-32e mode (if IA32_E FER.LMA = 1) at the time of VM entry, the “host address-
space size” VM-exit control must be 1.
•If the “host address-space size” VM-exit control is 0, the following must hold:
— Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0.— Bits 63:32 in the RIP field are 0.— If the “load CET state” VM-exit control is 1, bits 63: 32 in the IA32_S_CET field and in the SSP field are 0.
•If the “host address-space size” VM-exit control is 1, the following must hold:
— Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1.
— The RIP field contains a canonical address.— If the “load CET state” VM-exit control is 1, the IA32_S_CET field and the SSP field contain canonical 
•If the “load CET state” VM-exit control is 1, the IA 32_INTERRUPT_SSP_TABLE_ADDR field contains a canonical 
address.
On processors that do not support In tel 64 architecture, checks are performe d to ensure that the “IA-32e mode 
guest” VM-entry control and the “host address-space size” VM-exit control are both 0.
27.3 CHECKING AND LOADING GUEST STATE
If all checks on the VMX controls and the host-state ar ea pass (see Section 27.2), the following operations take 
place concurrently: (1) the guest-state area of the VMCS is checked to ensure that, after the VM entry completes, 
the state of the logical processor is consistent with IA- 32 and Intel 64 architectures; (2) processor state is loaded 
from the guest-state area or as specified by the VM-e ntry control fields; and (3) address-range monitoring is 
cleared.
Because the checking and the loading occur concurrently, a failure may be discovered only after some state has 
been loaded. For this reason, the logical processor responds  to such failures by loading state from the host-state 
area, as it would for a VM exit. See Section 27.8.
27.3.1 Checks on the Guest State Area
This section describes checks performed on fields in th e guest-state area. These checks may be performed in any 
order. Some checks prevent establishment of settings (or combinations of settings) th at are currently reserved. 
Future processors may allow such settings (or combinations) and may not perform the corresponding checks. The 
correctness of software should not rely on VM-entry failures  resulting from the checks documented in this section. 
The following subsections reference fields that correspond to processor state. Unless otherwise stated, these refer-
ences are to fields in the guest-state area.
27.3.1.1  Checks on Guest Control Registers, Debug Registers, and MSRs
The following checks are performed on fields in the gues t-state area corresponding to control registers, debug 
registers, and MSRs:Vol. 3C 27-9VM ENTRIES
•The CR0 field must not set any bit to a value not support ed in VMX operation (see Se ction 24.8). The following 
are exceptions:
— Bit 0 (corresponding to CR0.PE) and bit 31 (PG) are no t checked if the “unrestricted guest” VM-execution 
control is 1.1
— Bit 29 (corresponding to CR0.NW) and bit 30 (CD) are never checked because the values of these bits are 
not changed by VM entry; see Section 27.3.2.1.
•If bit 31 in the CR0 field (corresponding to PG) is  1, bit 0 in that field (PE) must also be 1.2
•The CR4 field must not set any bit to a value no t supported in VMX operat ion (see Section 24.8).
•If the “load debug controls” VM-entry control is 1, bits  reserved in the IA32_DEBUGCTL MSR must be 0 in the 
field for that register. The first processors to suppor t the virtual-machine extensions supported only the 1-

setting of this control and thus performed this check unconditionally.
•The following checks are performed on proc essors that support Intel 64 architecture:
— If the “IA-32e mode guest” VM-entry control is 1, bi t 31 in the CR0 field (corresponding to CR0.PG) and 
bit 5 in the CR4 field (corresponding to CR4.PAE) must each be 1.3
— If the “IA-32e mode guest” VM-entry control is 0, bit 17 in the CR4 field (corresponding to CR4.PCIDE) 
must be 0.
— The CR3 field must be such that bits 63:52 and bits  in the range 51:32 beyond the processor’s physical-
address width are 0.4,5
— If the “load debug controls” VM-ent ry control is 1, bits 63:32 in the DR7 field must be 0. The first 
processors to support the virtual-machine extensions su pported only the 1-setting of this control and thus 
performed this check unconditionally (if they supported Intel 64 architecture).
— The IA32_SYSENTER_ESP field and the IA32_SYSENTER_ EIP field must each contain a canonical address.
— If the “load CET state” VM-entry cont rol is 1, the IA32_S_CET field and the 
IA32_INTERRUPT_SSP_TABLE_ADDR field must contain canonical addresses.
•If the “load IA32_PERF_GLOBAL_CTRL” VM-entry control is 1, bits reserved in the IA32_PERF_GLOBAL_CTRL MSR must be 0 in the field for that register (see Figure 20-3).
•If the “load IA32_PAT” VM-entry control is 1, the value of the field for the IA32_PAT MSR must be one that could 
•If the “load IA32_EFER” VM-entry control is 1, the following checks are performed on the field for the IA32_EFER MSR:
— Bits reserved in the IA32_EFER MSR must be 0.— Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of the “IA-32e mode guest” VM-entry 
control. It must also be identical to bit 8 (LME) if bit 31 in the CR0 field (corresponding to CR0.PG) is 1.
6
1. “Unrestricted guest” is a seco ndary processor-based VM-execution control. If bit 31 of the primary processor-based VM-executio n 
controls is 0, VM entry functions as if  the “unrestricted guest” VM-execution control were 0. See Section 25.6.2.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, bi t 0 in the CR0 field must be 1 
unless the “unrestricte d guest” VM-execution cont rol and bit 31 of the primary processor-based VM-execution controls are both 1.
3. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, bi t 31 in the CR0 field must be 1 
4. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address 
5. Bit 63 of the CR3 field in the guest-state area must be 0. This is true even though, If CR4.PCIDE = 1, bit 63 of the source oper and to 
MOV to CR3 is used to determine whether cached translation information is invalidated.
6. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, bi t 31 in the CR0 field must be 1 
unless the “unrestricte d guest” VM-execution cont rol and bit 31 of the primary processor-based VM-execution controls are both 1.27-10 Vol. 3CVM ENTRIES
•If the “load IA32_BNDCFGS” VM-entry control is 1, th e following checks are performed on the field for the 
IA32_BNDCFGS MSR:
— Bits reserved in the IA32_BNDCFGS MSR must be 0.
— The linear address in bits 63:12 must be canonical. 
•If the “load IA32_RTIT_CTL” VM-entry control is 1, bits  reserved in the IA32_RTIT_CTL MSR must be 0 in the 
field for that register (see Table 33-6).
•If the “load CET state” VM-entry control is 1, the IA 32_S_CET field must not set any bits reserved in the 
IA32_S_CET MSR, and bit 10 (corresponding to SUPPRESS ) and bit 11 (TRACKER) of the field cannot both be 
set.
•If the “load guest IA32_LBR_CTL” VM-entry control is 1, bits reserved in the IA32_LBR_CTL MSR must be 0 in 
the field for that register.
•If the “load PKRS” VM-entry control is 1, bits 63:32 must be 0 in the IA32_PKRS field.
•If the “load UINV” VM-entry control is 1, bits 15:8 must be 0 in the guest UINV field.
27.3.1.2  Checks on Guest Segment Registers
This section specifies the checks on the fields for CS, SS, DS, ES, FS, GS, TR, and LDTR. The following terms are used in defining these checks:
•The guest will be virtual-8086  if the VM flag (bit 17) is 1 in the RFLAGS field in the guest-state area.
•The guest will be IA-32e mode  if the “IA-32e mode guest” VM-entry control is 1. (This is possible only on 
processors that support Intel 64 architecture.)
•Any one of these registers is said to be usable  if the unusable bit (bit 16) is 0 in the access-rights field for that 
register.
The following are the checks on these fields: 
•Selector fields.— TR. The TI flag (bit 2) must be 0.
— LDTR. If LDTR is usable, the TI flag (bit 2) must be 0.
— SS. If the guest will not be virtual-8086 and the “unr estricted guest” VM-execution control is 0, the RPL 
(bits 1:0) must equal the RPL of the selector field for CS.
1
•Base-address fields.
— CS, SS, DS, ES, FS, GS. If the guest will be virtual-80 86, the address must be the selector field shifted left 
4 bits (multiplied by 16).
— The following checks are performed on processors that support Intel 64 architecture:
•TR, FS, GS. The address must be canonical.
•LDTR. If LDTR is usable, the address must be canonical.
•CS. Bits 63:32 of the address must be zero.
•SS, DS, ES. If the register is usable, bits 63:32 of the address must be zero.
•Limit fields for CS, SS, DS, ES, FS, GS. If the guest will be virtual-8086, the field must be 0000FFFFH.
•Access-rights fields.
— CS, SS, DS, ES, FS, GS.
•If the guest will be virtual-8086, the field must be 000000F3H. This implies the following:
— Bits 3:0 (Type) must be 3, indicating an expand-up read/write accessed data segment.
— Bit 4 (S) must be 1.
controls is 0, VM entry functions as if  the “unrestricted guest” VM-execution control were 0. See Section 25.6.2.Vol. 3C 27-11VM ENTRIES
— Bits 6:5 (DPL) must be 3.
— Bit 7 (P) must be 1.
— Bits 11:8 (reserved), bit 12 (software available), bit 13 (reserved/L), bit 14 (D/B), bit 15 (G),
bit 16 (unusable), and bits 31:17 (reserved) must all be 0.
•If the guest will not be virtual-8086, the different sub-fields are considered separately:
— Bits 3:0 (Type).
•CS. The values allowed depend on the setting  of the “unrestricted guest” VM-execution
control:
— If the control is 0, the Type must be 9, 11, 13, or 15 (accessed code segment).
— If the control is 1, the Type must be either 3 (read/write accessed expand-up data
segment) or one of 9, 11, 13, and 15 (accessed code segment).
•SS. If SS is usable, the Type must be 3 or 7 (read/write, accessed data segment).
•DS, ES, FS, GS. The following checks apply if the register is usable:
— Bit 0 of the Type must be 1 (accessed).
— If bit 3 of the Type is 1 (code segment), then bit 1 of the Type must be 1 (readable).
— Bit 4 (S). If the register is CS or if the register is usable, S must be 1.— Bits 6:5 (DPL).
•CS.— If the Type is 3 (read/write accessed expand -up data segment), the DPL must be 0. The
Type can be 3 only if the “unrestric ted guest” VM-execution control is 1.
— If the Type is 9 or 11 (non-conforming code segment), the DPL must equal the DPL in the
access-rights field for SS.
— If the Type is 13 or 15 (conforming code se gment), the DPL cannot be greater than the
DPL in the access-rights field for SS.
•SS.
— If the “unrestricted guest” VM-execution contro l is 0, the DPL must equal the RPL from the
selector field.
— The DPL must be 0 either if the Type in the access-rights field for CS is 3 (read/write
accessed expand-up data segment) or if bit 0 in the CR0 field (corresponding to CR0.PE) is
0.1
•DS, ES, FS, GS. The DPL cannot be less than the RPL in the selector field if (1) the“unrestricted guest” VM-execution control is 0; (2) the register is usable; and (3) the Type in
the access-rights field is in the range 0 – 11 (d ata segment or non-conforming code segment).
— Bit 7 (P). If the register is CS or if the register is usable, P must be 1.
— Bits 11:8 (reserved). If the register is CS or if the register is usable, these bits must all be 0.— Bit 14 (D/B). For CS, D/B must be 0 if the guest will be IA-32e mode and the L bit (bit 13) in the
access-rights field is 1.
— Bit 15 (G). The following checks apply if the register is CS or if the register is usable:
•If any bit in the limit field in the range 11:0 is 0, G must be 0.
•If any bit in the limit field in the range 31:20 is 1, G must be 1.
— Bits 31:17 (reserved). If the register is CS or if  the register is usable, these bits must all be 0.

0.1
1. The following apply if either the “unrestricted guest” VM-execu tion control or bit 31 of the primary processor-based VM-execut ion 
controls is 0: (1) bit 0 in the CR0 field must be 1 if the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in V MX 
operation; and (2) the Type in the a ccess-rights field fo r CS cannot be 3.27-12 Vol. 3CVM ENTRIES
— TR. The different sub-fields are considered separately:
•Bits 3:0 (Type).
— If the guest will not be IA-32e mode, the Type must be 3 (16-bit busy TSS) or 11 (32-bit busy
TSS).
— If the guest will be IA-32e mode, the Type must be 11 (64-bit busy TSS).
•Bit 4 (S). S must be 0.
•Bit 7 (P). P must be 1.
•Bits 11:8 (reserved). These bits must all be 0.
•Bit 15 (G).
— If any bit in the limit field in the range 11:0 is 0, G must be 0.
— If any bit in the limit field in the range 31:20 is 1, G must be 1.
•Bit 16 (Unusable). The unusable bit must be 0.
•Bits 31:17 (reserved). These bits must all be 0.
— LDTR. The following checks on the different sub-fields apply only if LDTR is usable:
•Bits 3:0 (Type). The Type must be 2 (LDT).
•Bit 15 (G).— If any bit in the limit field in the range 11:0 is 0, G must be 0.
27.3.1.3  Checks on Guest Descriptor-Table Registers
The following checks are performed on the fields for GDTR and IDTR:
•On processors that support Intel 64 architecture, the base-address fields must contain canonical addresses.
•Bits 31:16 of each limit field must be 0.
27.3.1.4  Checks on Guest RIP, RFLAGS, and SSP
The following checks are performed on fields in the gu est-state area corresponding to RIP, RFLAGS, and SSP 
(shadow-stack pointer):
•RIP. The following checks are performed on pr ocessors that support Intel 64 architecture:
— Bits 63:32 must be 0 if the “IA-32e mode guest” VM-ent ry control is 0 or if the L bit (bit 13) in the access-
rights field for CS is 0.
— If the processor supports N < 64 linear-address bits, bi ts 63:N must be identical if the “IA-32e mode guest” 
VM-entry control is 1 and the L bit in the access-rights field for CS is 1.1 (No check applies if the processor 
supports 64 linear-address bits.) The guest RIP value is  not required to be canonical; the value of bit N-1 
may differ from that of bit N.
•RFLAGS.
— Reserved bits 63:22 (bits 31:22 on processors that do not support Intel 64 architecture), bit 15, bit 5 and 
bit 3 must be 0 in the field, and reserved bit 1 must be 1.
1. Software can determine the number N by executing CPUID with 80 000008H in EAX. The number of linear-address bits supported is 
returned in bits 15:8 of EAX.Vol. 3C 27-13VM ENTRIES
— The VM flag (bit 17) must be 0 either if the “IA-32e mo de guest” VM-entry control is 1 or if bit 0 in the CR0 
field (corresponding to CR0.PE) is 0.1
— The IF flag (RFLAGS[bit 9]) must be 1 if the valid bi t (bit 31) in the VM-entry interruption-information field 
is 1 and the interruption type (bits 10:8) is external interrupt.
•SSP. The following checks are performed if the “load CET state” VM-entry control is 1
— Bits 1:0 must be 0.
— If the processor supports the Intel 64 architecture, bits 63:N must be identical, where N is the CPU’s 
maximum linear-address width. (This check does no t apply if the processor supports 64 linear-address 
bits.) The guest SSP value is not required to be canonical; the value of bit N-1 may differ from that of bit N.
27.3.1.5  Checks on Guest Non-Register State
The following checks are performed on fields in the guest-state area corresponding to non-register state:
•Activity state.
— The activity-state field must contain a value in the ra nge 0 – 3, indicating an activity state supported by the 
implementation (see Section 25.4.2). Future proce ssors may include support for other activity states. 
Software should read the VMX capability MSR IA32_V MX_MISC (see Appendix A.6) to determine what 
activity states are supported.
— The activity-state field must not indicate the HLT state if the DPL (bits 6:5) in the access-rights field for SS 
is not 0.2
— The activity-state field must indicate the active state if the interruptibility-state field indicates blocking by 
either MOV-SS or by STI (if either bit 0 or bit 1 in that field is 1).
— If the valid bit (bit 31) in the VM-entry interruption-information field is 1, the interruption to be delivered 
(as defined by interruption type and vector) must not be  one that would normally be blocked while a logical 
processor is in the activity state corresponding to the contents of the activity-state field. The following 
items enumerate the interruptions (as specified in the VM-entry interruption-information field) whose 
injection is allowed for the different activity states:
•Active. Any interruption is allowed.
•HLT. The only events allowed are the following:
— Those with interruption type external interrupt or non-maskable interrupt (NMI).
— Those with interruption type hardware exception and vector 1 (debug exception) or vector 18
(machine-check exception).
— Those with interruption type other event and vector 0 (pending MTF VM exit).
See Table 25-17 in Section 25.8.3 for details rega rding the format of the VM-entry interruption-
information field.
•Shutdown. Only NMIs and machine-check exceptions are allowed.
•Wait-for-SIPI. No interruptions are allowed.
— The activity-state field must not indicate the wait-for-S IPI state if the “entry to SMM” VM-entry control is 1.
•Interruptibility state.
— The reserved bits (bits 31:5) must be 0.
— The field cannot indicate blocking by both STI and MOV SS (bits 0 and 1 cannot both be 1).
— Bit 0 (blocking by STI) must be 0 if the IF flag (bit 9) is 0 in the RFLAGS field.
1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, bi t 0 in the CR0 field must be 1 
2. As noted in Section 25.4.1, SS.DPL corresponds to the logical processor’s current privilege level (CPL).27-14 Vol. 3CVM ENTRIES
— Bit 0 (blocking by STI) and bit 1 (blocking by MOV-SS ) must both be 0 if the valid bit (bit 31) in the 
VM-entry interruption-information field is 1 and the inte rruption type (bits 10:8) in that field has value 0, 
indicating external interrupt, or value 2,  indicating non-maskable interrupt (NMI).
— Bit 2 (blocking by SMI) must be 0 if the processor is not in SMM.— Bit 2 (blocking by SMI) must be 1 if th e “entry to SMM” VM-entry control is 1.
— Bit 3 (blocking by NMI) must be 0 if the “virtual NMIs” VM-execution control is 1, the valid bit (bit 31) in the 
VM-entry interruption-information field is 1, and the in terruption type (bits 10:8) in that field has value 2 
(indicating NMI).
— If bit 4 (enclave interruption) is 1, bit 1 (blocking by MOV-SS) must be 0 and the processor must support 
for SGX by enumerating CPUID.(EAX =07H,ECX=0):EBX.S GX[bit 2] as 1.
NOTE
If the “virtual NMIs” VM-execution control is 0, ther e is no requirement that bit 3 be 0 if the valid bit 
in the VM-entry interruption-information field is 1 and the interruption type in that field has value 2.
•Pending debug exceptions.
— Bits 11:4, bit 13, bit 15, and bits 63:17 (bits 31:17 on processors that do not support Intel 64 architecture) 
must be 0.
— The following checks are performed if any of the followi ng holds: (1) the interruptibility-state field indicates 
blocking by STI (bit 0 in that field is 1); (2) the in terruptibility-state field indicates blocking by MOV SS 
(bit 1 in that field is 1); or (3) the activity-state field indicates HLT:
•Bit 14 (BS) must be 1 if the TF flag (bit 8) in th e RFLAGS field is 1 and the BTF flag (bit 1) in the 
IA32_DEBUGCTL field is 0.
•Bit 14 (BS) must be 0 if the TF flag (bit 8) in th e RFLAGS field is 0 or the BTF flag (bit 1) in the 
IA32_DEBUGCTL field is 1.
— The following checks are performed if bit 16 (RTM) is 1:
•Bits 11:0, bits 15:13, and bits 63:17 (bits 31:17 on processors that do not support Intel 64 archi-
tecture) must be 0; bit 12 must be 1.
•The processor must support for RTM by enumer ating CPUID.(EAX=07H,E CX=0):EBX[bit 11] as 1.
•The interruptibility-state field must not indicate blocking by MOV SS (bit 1 in that field must be 0).
•VMCS link pointer. The following checks apply if the field contains a value other than FFFFFFFF_FFFFFFFFH:
— Bits 11:0 must be 0.
— Bits beyond the processor’s physical-address width must be 0.1,2
— The 4 bytes located in memory referenced by the value of the field (as a physical address) must satisfy the 
•Bits 30:0 must contain the processor’s VMCS revision identifier (see Section 25.2).3
•Bit 31 must contain the setting of the “VMCS shadowing” VM-execution control.4 This implies that the 
referenced VMCS is a shadow VMCS (see Section 25.10) if and only if the “VMCS shadowing” VM-

execution control is 1.
2. If IA32_VMX_BASIC[48] is read as 1, this field must not set any bits in the range 63:32; see Appendix A.1.
3. Earlier versions of this manual specified that the VMCS revision identifier was a 32-bit field. For all processors produced p rior to this 
4. “VMCS shadowing” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-execution 
controls is 0, VM entry functions as if the “VMCS shadowing” VM-execution control were 0. See Section 25.6.2.Vol. 3C 27-15VM ENTRIES
— If the processor is not in SMM or the “entry to SMM” VM-entry control is 1, the field must not contain the 
current VMCS pointer.
— If the processor is in SMM and the “entry to SMM” VM -entry control is 0, the field must differ from the 
executive-VMCS pointer.
27.3.1.6 Checks on Guest Page-D irectory-Pointer-Table Entries
If CR0.PG =1, CR4.PAE = 1, and IA32_EFER.LME = 0, the logical processor uses PAE paging  (see Section 4.4 in 
the Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 3A).1 When PAE paging is in use, the 
physical address in CR3 references a table of page-directory-point er-table entries  (PDPTEs). A MOV to CR3 
when PAE paging is in use chec ks the validity of the PDPTEs.
A VM entry is to a guest that uses PAE paging if (1) bit 31  (corresponding to CR0.PG) is set in the CR0 field in the 
guest-state area; (2) bit 5 (corresponding to CR4.PAE) is set in the CR4 field; and (3) the “IA-32e mode guest” 
VM-entry control is 0. Such a VM entr y checks the validity of the PDPTEs:
•If the “enable EPT” VM-execution control is 0, VM entry checks the validity of the PDPTEs referenced by the CR3 
field in the guest-state area if either (1) PAE paging wa s not in use before the VM entry; or (2) the value of CR3 
is changing as a result of the VM entry. VM entry may check their validity even if neither (1) nor (2) hold.2
•If the “enable EPT” VM-execution control is 1, VM entry checks the validity of the PDPTE fields in the guest-
state area (see Section 25.4.2).
A VM entry to a guest that does not use PAE paging does not check the validity of any PDPTEs.
A VM entry that checks the validity of the PDPTEs uses th e same checks that are used when CR3 is loaded with 
MOV to CR3 when PAE paging is in use.3 If MOV to CR3 would cause a general-protection exception due to the 
PDPTEs that would be loaded (e.g., because a reserved bit is set), the VM entry fails.
27.3.2 Loading Guest State
Processor state is updated on VM entries in the following ways:
•Some state is loaded from the guest-state area.
•Some state is determined by VM-entry controls.
•The page-directory pointers are loaded based on the values of certain control registers.
This loading may be performed in any order and in parall el with the checking of VMCS contents (see Section 
27.3.1).
The loading of guest state is detailed in Section 27.3.2.1 to Section 27.3.2.4. These sections reference VMCS fields 
that correspond to processor state. Unless otherwise stated, these references are to fields in the guest-state area.
In addition to the state loading described in this sectio n, VM entries may load MSRs from the VM-entry MSR-load 
area (see Section 27.4). This loading occurs only after th e state loading described in th is section and the checking 
of VMCS contents described in Section 27.3.1.
27.3.2.1  Loading Guest Control Re gisters, Debug Registers, and MSRs
The following items describe how guest control register s, debug registers, and MSRs are loaded on VM entry:
1. On processors that support In tel 64 architecture, the physical-address extens ion may support more th an 36 physical-address bi ts. 
Software can determine the number physical-address bits suppor ted by executing CPUID with 80000008H in EAX. The physical-
address width is returned in bits 7:0 of EAX.
2. “Enable EPT” is a secondary processor-base d VM-execution control. If bit 31 of the primary processor-based VM-execution contro ls 
is 0, VM entry functions as if th e “enable EPT” VM-execution control were 0. See Section 25.6.2.
3. This implies that (1) bits 11:9 in each PDPTE are ignored; and (2 ) if bit 0 (present) is clear in one of the PDPTEs, bits 63:1 of  that 
PDPTE are ignored.27-16 Vol. 3CVM ENTRIES
•CR0 is loaded from the CR0 field with the exception of the following bits, which are never modified on VM entry: 
ET (bit 4); reserved bits 15:6, 17, and 28:19; NW (bit 29) and CD (bit 30).1 The values of these bits in the CR0 
field are ignored.
•CR3 and CR4 are loaded from the CR3 field and the CR4 field, respectively.
•If the “load debug controls” VM-entry control is 1, DR7 is loaded from the DR7 field with the exception that 
bit 12 and bits 15:14 are always 0 and bit 10 is always 1. The values of these bits in the DR7 field are ignored.
The first processors to support the virtual-machine ex tensions supported only the 1-setting of the “load
debug controls” VM-entry control and thus always loaded DR7 from the DR7 field.
•The following describes how certain MSRs are loaded using fields in the guest-state area:
— If the “load debug controls” VM-entry control is  1, the IA32_DEBUGCTL MSR is loaded from the 
IA32_DEBUGCTL field. The first proce ssors to support the virtual-machine extensions supported only the 1-
setting of this control and thus always loaded the IA32_DEBUGCTL MSR from the IA32_DEBUGCTL field.
— The IA32_SYSENTER_CS MSR is loaded from the IA32_SYSENTER_CS field. Since this field has only 32 bits, 
bits 63:32 of the MSR are cleared to 0.
— The IA32_SYSENTER_ESP and IA32_SYSENTER_EIP MS Rs are loaded from the IA32_SYSENTER_ESP field 
and the IA32_SYSENTER_EIP field, respectively. On proc essors that do not support Intel 64 architecture, 
these fields have only 32 bits; bits 63:32 of the MSRs are cleared to 0.
— The following are performed on processo rs that support Intel 64 architecture:
•The MSRs FS.base and GS.base are loaded from the base-address fields for FS and GS, respectively 
(see Section 27.3.2.2).
•If the “load IA32_EFER” VM-entry control is 0, bi ts in the IA32_EFER MSR are modified as follows:
— IA32_EFER.LMA is loaded with the setting of the “IA-32e mode guest” VM-entry control.— If CR0 is being loaded so that CR0.PG = 1, IA32_EFER.LME is also loaded with the setting of the
“IA-32e mode guest” VM-entry control.
2 Otherwise, IA32_EFER.LME is unmodified.
See below for the case in which the “load IA32_EFER” VM-entry control is 1
— If the “load IA32_PERF_GLOBAL_CTRL” VM-entry contro l is 1, the IA32_PERF_GLOBAL_CTRL MSR is loaded 
from the IA32_PERF_GLOBAL_CTRL field.
— If the “load IA32_PAT” VM-entry control is 1, the IA32_PAT MSR is loaded from the IA32_PAT field.
— If the “load IA32_EFER” VM-entry control is 1, th e IA32_EFER MSR is loaded from the IA32_EFER field.
— If the “load IA32_BNDCFGS” VM-entry control is 1, the IA32_BNDCFGS MSR is loaded from the 
IA32_BNDCFGS field.
— If the “load IA32_RTIT_CTL” VM-entry control is  1, the IA32_RTIT_CTL MSR is loaded from the 
IA32_RTIT_CTL field.
— If the “load CET” VM-entry control is 1, the IA32_S_CET and IA32_INTERRUPT_SSP_TABLE_ADDR MSRs 
are loaded from the IA32_S_CET field and the IA32_I NTERRUPT_SSP_TABLE_ADDR field, respectively. On 
processors that do not support Intel 64 architecture, these fields have only 32 bits; bits 63:32 of the MSRs 
are cleared to 0.
— If the “load guest IA32_LBR_CTL” VM-entry control is 1, the IA32_LBR_CTL MSR is loaded from the 
IA32_LBR_CTL guest state field.
— If the “load PKRS” VM-entry control is 1, the IA 32_PKRS MSR is loaded from the IA32_PKRS field.
— If the “load UINV” VM-entry control is  1, UINV is loaded with the low 8 bits of the UINV field. UINV is 
represented in bits 39:32 of the IA32_UINTR_MISC MSR. The remainder of the MSR is not modified.
1. Bits 15:6, bit 17, and bit 28:19 of CR0 and CR0.ET are unchanged by  executions of MOV to CR0. Bi ts 15:6, bit 17, and bit 28:19 of 
CR0 are always 0 and CR0.ET is always 1.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, VM entry must be loading CR0 so 
that CR0.PG = 1 unless the “unrestricted gues t” VM-execution control and bit 31 of the primary processor-based VM-execution con-
trols are both 1.Vol. 3C 27-17VM ENTRIES
With the exception of FS.base and GS.base, any of these MSRs is subsequently overwritten if it appears in the
VM-entry MSR-load area. See Section 27.4.
•The SMBASE register is unmodified by all VM entries except those that return from SMM.
27.3.2.2  Loading Guest Segment Regi sters and Descriptor-Table Registers
For each of CS, SS, DS, ES, FS, GS, TR, and LDTR, fiel ds are loaded from the guest-state area as follows:

•The unusable bit is loaded from the access-rights field. This bit can never be set for TR (see Section 27.3.1.2). 
If it is set for one of the other registers, the following apply:
— For each of CS, SS, DS, ES, FS, and GS, uses of the segment cause faults (general-protection exception or 
stack-fault exception) outside 64-bit mode, just as they would had the segment been loaded using a null 
selector. This bit does not cause accesses to fault in 64-bit mode.
— If this bit is set for LDTR, uses of LDTR cause general- protection exceptions in all modes, just as they would 
had LDTR been loaded using a null selector.
If this bit is clear for any of CS, SS, DS, ES, FS, GS, TR, and LDTR, a null selector value does not cause a fault
(general-protection exception or stack-fault exception).
•TR. The selector, base, limit, and access-rights fields are loaded.
•CS.
— The following fields are always loaded: selector, base  address, limit, and (from the access-rights field) the 
L, D, and G bits.
— For the other fields, the unusable bit of the access-rights field is consulted:
•If the unusable bit is 0, all of the access-rights field is loaded.
•If the unusable bit is 1, the remainder of CS access rights are undefined after VM entry.
•SS, DS, ES, FS, GS, and LDTR.
— The selector fields are loaded.
— For the other fields, the unusable bit of the corresponding access-rights field is consulted:
•If the unusable bit is 0, the base-address, limit, and access-rights fields are loaded.
•If the unusable bit is 1, the base address, the segm ent limit, and the remainder of the access rights are 
undefined after VM entry with the following exceptions:
— Bits 3:0 of the base address for SS are cleared to 0.
— SS.DPL is always loaded from the SS access-rights field. This will be the current privilege level
(CPL) after the VM entry completes.
— SS.B is always set to 1.— The base addresses for FS and GS are loaded from the corresponding fields in the VMCS. On
processors that support Intel 64 architecture, th e values loaded for base addresses for FS and GS
are also manifest in the FS.base and GS.base MSRs.
— On processors that support Intel 64 architecture, the base address for LDTR is set to an undefined
but canonical value.
— On processors that support Intel 64 architecture, bits 63:32 of the base addresses for SS, DS, and
ES are cleared to 0.
GDTR and IDTR are loaded using the base and limit fields.
27.3.2.3  Loading Guest RIP, RSP, RFLAGS, and SSP
RSP, RIP, and RFLAGS are loaded from the RSP field, the RIP field, and the RFLAGS field, respectively.If the “load CET” VM-entry control is 1, SSP (shadow-stack pointer) is loaded from the SSP field.The following items regard the upper 32 bits of thes e fields on VM entries that are not to 64-bit mode:27-18 Vol. 3CVM ENTRIES
•Bits 63:32 of RSP are undefined outside 64-bit mode. Thus, a logical processor may ignore the contents of 
bits 63:32 of the RSP field on VM entries that are not to 64-bit mode.
•As noted in Section 27.3.1.4, bits 63:32 of the RIP and RF LAGS fields must be 0 on VM entries that are not to 
64-bit mode. (The same is true for SSP for VM entries that are not to 64-bit mode when the “load CET” VM-
entry control is 1.)
27.3.2.4  Loading Page-Directory-Pointer-Table Entries
As noted in Section 27.3.1.6, the logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1, and 
IA32_EFER.LME = 0. A VM entry to a guest that uses PAE pa ging loads the PDPTEs into internal, non-architectural 
registers based on the setting of the “enable EPT” VM-execution control:
•If the control is 0, the PDPTEs are loaded from the pa ge-directory-pointer table re ferenced by the physical 
address in the value of CR3 being loaded by the VM entr y (see Section 27.3.2.1). The values loaded are treated 
as physical addresses in VMX non-root operation.
•If the control is 1, the PDPTEs are loaded from corresponding fields in the guest-state area (see Section 
25.4.2). The values loaded are treated as gues t-physical addresses in VMX non-root operation.
27.3.2.5  Updating Non-Register State
Section 29.4 describes how the VMX architecture controls how a logical processor manage s information in the TLBs 
and paging-structure caches. The following items detail how VM entries invalidate cached mappings:
•If the “enable VPID” VM-execution control is 0, the logi cal processor invalidates linear mappings and combined 
mappings associated with VPID 0000H (for all PCIDs); combined mappings for VPID 0000H are invalidated for 
all EPTRTA values (EPTRTA is the value of bits 51:12 of EPTP).
•VM entries are not required to invalidate any guest-physic al mappings, nor are they required to invalidate any 
linear mappings or combined mappings if th e “enable VPID” VM-execution control is 1.
If the “virtual-interrupt delivery” VM-execution control is 1, VM entry loads the values of RVI and SVI from the 
guest interrupt-status field in the VMCS (see Section 25.4.2). After doing so, the logical processor first causes PPR 
virtualization (Section 30.1.3) and then evaluates pending virtual interrupts (Section 30.2.1).
If a virtual interrupt is recognized, it may be delive red in VMX non-root operation immediately after VM entry 
(including any specified event injection) completes; s ee Section 27.7.5. See Section 30.2.2 for details regarding 
the delivery of virtual interrupts.
27.3.3 Clearing Address-Range Monitoring
The Intel 64 and IA-32 architectures allow software to monitor a specified address range using the MONITOR and 
MWAIT instructions. See Section 9.10.4 in the Intel® 64 and IA-32 Architectures So ftware Developer’s Manual, 
Volume 3A. VM entries clear any address-range monitoring that may be in effect.
27.4 LOADING MSRS
VM entries may load MSRs from the VM-entry MSR-load area (see Section 25.8.2). Specifically each entry in that area (up to the number specified in the VM-entry MSR-load count) is processed in order by loading the MSR indexed 
by bits 31:0 with the contents of bits 127:64 as they would be written by WRMSR.
1 
Processing of an entry fails in any of the following cases:
•The value of bits 31:0 is either C0000100H (the IA3 2_FS_BASE MSR) or C0000101 (the IA32_GS_BASE MSR).
•The value of bits 31:8 is 000008H, meaning that the indexe d MSR is one that allows access to an APIC register 
when the local APIC is in x2APIC mode. 
1. Because attempts to modify the value of IA32_E FER.LMA by WRMSR are ignored, attempts to modify it using the VM-entry MSR-
load area are also ignored.Vol. 3C 27-19VM ENTRIES
•The value of bits 31:0 indicates an MSR that can be wr itten only in system-management mode (SMM) and the 
VM entry did not commence in SMM. (IA32_SMM_MONITOR_ CTL is an MSR that can be  written only in SMM.)
•The value of bits 31:0 indicates an MSR that cannot be loaded on VM entries for model-specific reasons. A 
processor may prevent loading of certain MSRs even if they can normally be written by WRMSR. Such model-
specific behavior is documented in Chapter 2, “Model-Specific Registers (MSRs),” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 4.
•Bits 63:32 are not all 0.
•An attempt to write bits 127:64 to the MSR indexed by bits 31:0 of the entry would cause a general-protection 
exception if executed via WRMSR with CPL = 0.1
The VM entry fails if processing fails for any entry. The logical processor responds to such failures by loading state from the host-state area, as it would for a VM exit. See Section 27.8.
If any MSR is being loaded in such a way that would arch itecturally require a TLB flush, the TLBs are updated so 
that, after VM entry, the logical processor will not use any translations that were cached before the transition.
27.5 TRACE-ADDRESS PRE-TRANSLATION (TAPT)
treated as guest-physical addresses, and these are translated to physical addresses using EPT.
VM entry uses trace-address pre-translation  (TAPT ) to prevent buffered trace data from being lost due to an 
EPT violation; see Section 26.5.4.2. VM entry uses TAPT  only if Intel PT will be enabled following VM entry 
(IA32_RTIT_CTL.TraceEn = 1) and only if the “Intel PT us es guest physical addresses” VM-execution control is 1
As noted in Section 26.5.4, TAPT may cause a VM exit due to an EPT violation, EPT misconfiguration, page-modifi-
cation log-full event, or APIC access. If such a VM exit occu rs as a result of TAPT during VM entry, the VM exit oper-
ates as if it had occurred in VMX non-root operation after the VM entry completed (in the guest context).
If TAPT during VM entry causes a VM exit, the VM entry does  not perform event injection (Section 27.6), even if the 
valid bit in the VM-entry interruption-in formation field is 1. Such VM exits sa ve the contents of VM-entry interrup-
tion-information and VM-entry exception error code fiel ds into the IDT-vectoring information and IDT-vectoring

tion-information and VM-entry exception error code fiel ds into the IDT-vectoring information and IDT-vectoring 
error code fields, respectively.
27.6 EVENT INJECTION
If the valid bit in the VM-entry interruption-information fi eld (see Section 25.8.3) is 1, VM entry causes an event to 
be delivered (or made pending) after all components of guest state have been loaded (including MSRs) and after 
the VM-execution control fields have been established.
•If the interruption type in the field is 0 (externa l interrupt), 2 (non-maskable interrupt); 3 (hardware 
exception), 4 (software interrupt), 5 (privileged software  exception), or 6 (software exception), the event is 
delivered as described in Section 27.6.1.
•If the interruption type in the field is  7 (other event) and the vector field is 0, an MTF VM exit is pending after 
VM entry. See Section 27.6.2.
27.6.1 Vectored-Event Injection
VM entry delivers an injected vectored event within the guest context established by VM entry. This means that 
delivery occurs after all components of guest state have been loaded (including MSRs) and after the VM-execution 
control fields have been established.2 The event is delivered using the vector in that field to select a descriptor in 
the IDT. Since event injection occurs after loading ID TR from the guest-state area, this is the guest IDT.
1. If CR0.PG = 1, WRMSR to the IA32_EFER MSR causes a general-protec tion exception if it would modify the LME bit. If VM entry has 
established CR0.PG = 1, the IA32_EFER MSR should not be included in the VM-entry MSR-load area for the purpose of modifying the LME bit.27-20 Vol. 3CVM ENTRIES
Section 27.6.1.1 provides details of vectored-event injection.  In general, the event is delivered exactly as if it had 
been generated normally.
An exception is made if the following all hold: bit 25 (UIN TR) is set to 1 in the guest CR4 field and the “IA-32e mode 
guest” VM-entry control is 1, and VM entry is modified if it is injecting an external interrupt whose vector is the 
value that UINV would have after VM entry. In this case, the logical processor then performs user-interrupt notifi-
cation processing as specified in Section 7.5.2 instead of  the process described in Section 27.6.1.1. (If the guest 
activity-state field indicated the HLT state, the logical pr ocessor enters the HLT state following user-interrupt noti-
fication processing.)
If event delivery (or user-interrupt notification proc essing; see above) encounters a nested exception (for 
example, a general-protection exception because the ve ctor indicates a descriptor beyond the IDT limit), the 
exception bitmap is consulted usin g the vector of that exception:
•If the bit for the nested exception is 0, the nested exce ption is delivered normally. If the nested exception is 
benign, it is delivered through the IDT. If it is contribu tory or a page fault, a double fault may be generated, 
depending on the nature of the event whose delivery encountered the nested exception. See Chapter 6, 
“Interrupt 8—Double Fault Exception (#DF)” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A.1
•If the bit for the nested exception is 1, a VM exit occurs . Section 27.6.1.2 details cases in which event injection 
causes a VM exit.
27.6.1.1  Details of Vectored-Event Injection
The event-injection process is controlled by the contents  of the VM-entry interruption information field (format 
given in Table 25-17), the VM-entry exception error-code field, and the VM-entry instruction-length field. The 
following items provide details of the process:
•The value pushed on the stack for RFLAGS is generally that which was loaded from the guest-state area. The 
value pushed for the RF flag is not modified based on the type of event being delivered. However, the pushed 
value of RFLAGS may be modified if a software interrupt is being injected into a guest that will be in virtual-
8086 mode (see below). After RFLAGS is pushed on the st ack, the value in the RFLAGS register is modified as 
is done normally when delivering an event through the IDT.
•The instruction pointer that is pushed on the stack depe nds on the type of event an d whether nested exceptions 
occur during its delivery. The term current guest RIP  refers to the value to be loaded from the guest-state 
area. The value pushed is determined as follows:2
— If VM entry successfully injects (with no nested exce ption) an event with interruption type external 
interrupt, NMI, or hardware exception, the current guest RIP is pushed on the stack.
— If VM entry successfully injects (with no nested exception) an event with interruption type software 
interrupt, privileged software exception, or software exception, the current guest RIP is incremented by the VM-entry instruction length before being pushed on the stack.
— If VM entry encounters an exception while injecting an  event and that exception does not cause a VM exit, 
the current guest RIP is pushed on the stack regardless of event type or VM-entry instruction length. If the 
encountered exception does cause a VM exit that saves RIP, the saved RIP is current guest RIP.
•If the deliver-error-code bit (bit 11) is set in the VM-entry interruption-in formation field, the contents of the 
VM-entry exception error-code field is pushed on the stac k as an error code would be pushed during delivery of 
an exception.
•DR6, DR7, and the IA32_DEBUGCTL MSR are not modified by event injection, even if the event has vector 1 
(normal deliveries of debug exceptions, which have vector 1, do update these registers).
2. This does not imply that injection of an exception or interr upt will cause a VM exit due to th e settings of VM-e xecution contr ol fields 
(such as the exception bitmap) that would cause a VM exit if the event had occurred in VMX non-root operation. In contrast, a ne sted 
exception encountered during event delivery may cause a VM exit; see Section 27.6.1.1.
1. Hardware exceptions with the following unused vectors are considered benign: 15 and 21–31. A hardware exception with vector 2 0 
is considered benign unless the pr ocessor supports the 1-setting of  the “EPT-violation #VE” VM-exe cution control; in that case,  it 
has the same severity as page faults.
2. While these items refer to RIP, the width of the value push ed (16 bits, 32 bits, or 64 bi ts) is determined normally.Vol. 3C 27-21VM ENTRIES
•If VM entry is injecting a software interrupt and the gu est will be in virtual-8086 mode (RFLAGS.VM = 1), no 
general-protection exception can occur due to RFLAGS.IOPL < 3. A VM monitor should check RFLAGS.IOPL before injecting such an event and, if desired, inject a general-protection exception instead of a software 
•If VM entry is injecting a software interrupt and the guest will be in virtual-8086 mode with virtual-8086 mode 
extensions (RFLAGS.VM = CR4.VME = 1), event delivery is  subject to VME-based interrupt redirection based 
on the software interrupt redirection bitmap in the task-state segment (TSS) as follows:
—I f  b i t n in the bitmap is clear (where n is the number of the software interrupt), the interrupt is directed to 
an 8086 program interrupt handler: the processor us es a 16-bit interrupt-vector table (IVT) located at 
linear address zero. If the value of RFLAGS.IOPL is less than 3, the following modifications are made to the 
value of RFLAGS that is pushed on the stack: IOPL is set to 3, and IF is set to the value of VIF.
—I f  b i t n in the bitmap is set (where n is the number of the software interru pt), the interrupt is directed to a 
protected-mode interrupt handler. (In other words, the injection is treated as described in the next item.) 
In this case, the software interrupt does not invoke such a handler if RFLAGS.IOPL < 3 (a general-
protection exception occurs instead). However, as noted above, RFLAGS.IOPL cannot cause an injected 
software interrupt to cause such a exception. Thus, in this case, the injection invokes a protected-mode 
interrupt handler independent of the value of RFLAGS.IOPL.
Injection of events of other types are not subject to this redirection.
•If VM entry is injecting a software interrupt (not redirect ed as described above) or software exception, privilege 
checking is performed on the IDT descriptor being accessed as would be the case for executions of INT n, INT3, 
or INTO (the descriptor’s DPL cannot be less than CPL). Th ere is no checking of RFLAGS.IOPL, even if the guest 
will be in virtual-8086 mode. Failure of this check may le ad to a nested exception. Injection of an event with 
interruption type external interrupt, NMI, hardware except ion, and privileged software exception, or with inter-
ruption type software interrupt and being redirected  as described above, do not perform these checks.
•If VM entry is injecting a non-maskable interrupt (NMI ) and the “virtual NMIs” VM-execution control is 1, 
virtual-NMI blocking is in effect after VM entry.
•The transition causes a last-branch record to be logged if the LBR bit is set in the IA32_DEBUGCTL MSR. This is

•The transition causes a last-branch record to be logged if the LBR bit is set in the IA32_DEBUGCTL MSR. This is 
true even for events such as debug exceptions, which normally clear the LBR bit before delivery.
•The last-exception record MSRs (LERs) may be u pdated based on the setting of the LBR bit in the 
IA32_DEBUGCTL MSR. Events such as debug exceptions, which normally clear the LBR bit before they are 
delivered, and therefore do not norm ally update the LERs, may do so as part of VM-entry event injection.
•If injection of an event encounters a nested exception, the value of the EXT bit (bit 0) in any error code for that 
nested exception is determined as follows:
— If event being injected has interruption type external  interrupt, NMI, hardware exception, or privileged 
software exception and encounters a nested exception (but does not produce a double fault), the error code for that exception sets the EXT bit.
— If event being injected is a software interrupt or a software exception and encounters a nested exception, 
the error code for that exception clears the EXT bit.
— If event delivery encounters a nested exception and delivery of that exception encounters another 
exception (but does not produce a double fault), th e error code for that exception sets the EXT bit.
— If a double fault is produced, the error code for the double fault is 0000H (the EXT bit is clear).
27.6.1.2  VM Exits During Event Injection
An event being injected never causes a VM exit directly re gardless of the settings of the VM-execution controls. For 
example, setting the “NMI exiting” VM-execution control to  1 does not cause a VM exit due to injection of an NMI.
However, the event-delivery process may lead to a VM exit:
•If the vector in the VM-entry interruption-information fiel d identifies a task gate in the IDT, the attempted task 
switch may cause a VM exit just as it would had the injected event occurred during normal execution in VMX 
non-root operation (see Section 26.4.2).
•If event delivery encounters a nested exception, a VM exit may occur depending on the contents of the 
exception bitmap (see Section 26.2).27-22 Vol. 3CVM ENTRIES
•If event delivery generates a double-fault exception (due to a nested exception); the logical processor 
encounters another nested exception while attempting to call the double-fault handler; and that exception does 
not cause a VM exit due to the exception bitmap; then a VM exit occurs due to triple fault (see Section 26.2).
•If event delivery injects a double-fault exception and encounters a nested exception that does not cause a 
VM exit due to the exception bitmap, then a VM exit  occurs due to triple fault (see Section 26.2).
•If the “virtualize APIC accesses” VM-execution control is 1 and event delivery generates an access to the APIC-
access page, that access is treated as described in Section 30.4 and may cause a VM exit.1
If the event-delivery process does cause a VM exit, the proce ssor state before the VM exit is determined just as it 
would be had the injected event occurred during normal exec ution in VMX non-root operation. If the injected event 
directly accesses a task gate that cause a VM exit or if the first nested exception encountered causes a VM exit, 
information about the injected event is saved in the IDT-vectoring information field (see Section 28.2.4).
The material in this section applies also if injection of an  external interrupt results in user-interrupt notification 
processing instead of event delivery (see Section 27.6.1 earlier).
27.6.1.3  Event Injection for VM Entries to Re al-Address Mode
If VM entry is loading CR0.PE with 0, any injected vectored  event is delivered as would normally be done in real-
address mode.2 Specifically, VM entry uses the vector provided in the VM-entry interruption-information field to 
select a 4-byte entry from an interrupt-vector table at th e linear address in IDTR.base. Further details are provided 
in Section 15.1.4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
Because bit 11 (deliver error code) in the VM-entry interrupt ion-information field must be 0 if CR0.PE will be 0 after 
VM entry (see Section 27.2.1.3), vectored events injected wi th CR0.PE = 0 do not push an error code on the stack. 
This is consistent with event delivery in real-address mode.
If event delivery encounters a fault (due to a violation of IDTR .limit or of SS.limit), the fault is treated as if it had 
occurred during event delivery in VMX non-root operation. Such a fault may lead to a VM exit as discussed in 
Section 27.6.1.2.
27.6.2 Injection of Pending MTF VM Exits
If the interruption type in the VM-entry interruption-inform ation field is 7 (other event) and the vector field is 0, 
VM entry causes an MTF VM exit to be pending on the instruction boundary following VM entry. This is the case 
even if the “monitor trap flag” VM-execution control is  0. See Section 26.5.2 for the treatment of pending MTF 
VM exits.
27.7 SPECIAL FEATURES OF VM ENTRY
This section details a variety of features of VM entr y. It uses the following terminology: a VM entry is vectoring  if 
the valid bit (bit 31) of the VM-entry interruption informatio n field is 1 and the interruption type in the field is 0 
(external interrupt), 2 (non-maskable interrupt); 3 (har dware exception), 4 (software interrupt), 5 (privileged 
software exception), or 6 (software exception).
27.7.1 Interruptibility State
The interruptibility-state field in the guest-state area (see Table 25-3) contains bits that control blocking by STI, 
blocking by MOV SS, and blocking by NMI. This fi eld impacts event blocking after VM entry as follows:
1. “Virtualize APIC accesses” is a secondary processor-based VM-execution control. If bit 31 of the primary processor-based VM-ex ecu-
tion controls is 0, VM entry functions as if the “virtualize APIC accesses” VM-execution control were 0. See Section 25.6.2.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, VM entry must be loading CR0.PE 
with 1 unless the “unrestric ted guest” VM-execution control an d bit 31 of the primary processor-based VM-execution controls are  
both 1.Vol. 3C 27-23VM ENTRIES
•If the VM entry is vectoring, there is no blocking by STI or by MOV SS following the VM entry, regardless of the 
contents of the interruptibility-state field.
•If the VM entry is not vectoring, the following apply:
— Events are blocked by STI if and only if bit 0 in the in terruptibility-state field is 1. This blocking is cleared 
after the guest executes one instruction or incurs an  exception (including a debug exception made pending 
by VM entry; see Section 27.7.3).
— Events are blocked by MOV SS if and only if bit 1 in the interruptibility-state field is 1. This may affect the 
treatment of pending debug exceptions; see Section 27.7.3. This blocking is cleared after the guest 
executes one instruction or incurs an exception (including a debug exception made pending by VM entry).
•The blocking of non-maskable interrupts (NMIs) is determined as follows:
— If the “virtual NMIs” VM-execution control is 0, NMIs are blocked if and only if bit 3 (blocking by NMI) in the 
interruptibility-state field is 1. If the “NMI exiting”  VM-execution control is 0, execution of the IRET 
instruction removes this blocking (even if the instructio n generates a fault). If the “NMI exiting” control is 
1, IRET does not affect this blocking.
— The following items describe the use of bit 3 (blockin g by NMI) in the interruptibility-state field if the 
“virtual NMIs” VM-execution control is 1:
•The bit’s value does not affect the blocking of NM Is after VM entry. NMIs are not blocked in VMX non-
root operation (except for ordinary blocking for othe r reasons, such as by the MOV SS instruction, the 
wait-for-SIPI state, etc.)
•The bit’s value determines whether there is virtual-NM I blocking after VM entry. If the bit is 1, virtual-
NMI blocking is in effect after VM entry. If the bit is 0, there is no virtual-NMI blocking after VM entry 
unless the VM entry is injecting an NMI (see Section 27.6.1.1). Execution of IRET removes virtual-NMI 
blocking (even if the instruction generates a fault).
If the “NMI exiting” VM-execution control is 0, the “v irtual NMIs” control must be 0; see Section 27.2.1.1.
•Blocking of system-management interrupt s (SMIs) is determined as follows:
— If the VM entry was not executed in system-manag ement mode (SMM), SMI blocking is unchanged by 
VM entry.
— If the VM entry was executed in SMM, SMIs are blocked after VM entry if and only if the bit 2 in the inter-
ruptibility-state field is 1.
27.7.2 Activity State
The activity-state field in the guest-state area controls whet her, after VM entry, the logical processor is active or in 
one of the inactive states identified in Section 25.4. 2. The use of this field is determined as follows:
•If the VM entry is vectoring, the logical processor is in  the active state after VM entry. While the consistency 
checks described in Section 27.3.1.5 on the activity-sta te field do apply in this case, the contents of the

VM entry.
checks described in Section 27.3.1.5 on the activity-sta te field do apply in this case, the contents of the 
activity-state field do not determine the activity state after VM entry.
•If the VM entry is not vectoring, the logical processor en ds VM entry in the activity state specified in the guest-
state area. If VM entry ends with the logical processor in an inactive activity state, the VM entry generates any special bus cycle that is normally generated when that activity state is entered from the active state. If 
VM entry would end with the logical processor in the shutdown state and the logical processor is in SMX 
operation,
1 an Intel® TXT shutdown condition occurs. The error code used is 0000H, indicating “legacy 
shutdown.” See the Intel® Trusted Execution Technology Preliminary Architecture Specification.
•Some activity states unconditionally block certain events . The following blocking is in effect after any VM entry 
that puts the processor in the indicated state:
— The active state blocks start-up IPIs (SIPIs). SIPIs that arrive while a logical processor is in the active state 
and in VMX non-root operation are discarded and do not cause VM exits.
1. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. Se e 
Chapter 6, “Safer Mode Extens ions Reference,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.27-24 Vol. 3CVM ENTRIES
— The HLT state blocks start-up IPIs (SIPIs). SIPIs that arrive while a logical processor is in the HLT state and 
in VMX non-root operation are discarded and do not cause VM exits.
— The shutdown state blocks external interrupts and SIPIs. External interrupts that arrive while a logical 
processor is in the shutdown state and in VMX non-root operation do not cause VM exits even if the “external-interrupt exiting” VM-execution control is 1. SIPIs that arrive while a logical processor is in the 
shutdown state and in VMX non-root operation are discarded and do not cause VM exits.
— The wait-for-SIPI state blocks external interrupts, non-maskable interrupts (NMIs), INIT signals, and 
system-management interrupts (SMIs). Such events do not cause VM exits if they arrive while a logical 
processor is in the wait-for-SIPI state and in VMX non-root operation.
27.7.3 Delivery of Pending Debug Exceptions after VM Entry
The pending debug exceptions field in the guest-state area indicates whether there are debug exceptions that have 
not yet been delivered (see Section 25.4.2). This section describes how these are treated on VM entry.
There are no pending debug exceptions after VM entry if any of the following are true:
•The VM entry is vectoring with one of the following interruption types: external interrupt, non-maskable 
interrupt (NMI), hardware exception,  or privileged software exception.
•The interruptibility-state field does not indicate blocking by MOV SS and the VM entry is vectoring with either of 
the following interruption type: software interrupt or software exception.
•The VM entry is not vectoring and the activity-state field indicates either shutdown or wait-for-SIPI.
If none of the above hold, the pending debug exceptions field specifies the debug exceptions that are pending for 
the guest. There are valid pending debug exceptions  if either the BS bit (bit 14) or the enable-breakpoint bit 
(bit 12) is 1. If there are valid pending de bug exceptions, they are handled as follows:
•If the VM entry is not vectoring, the pending debug ex ceptions are treated as they would had they been 
encountered normally in guest execution:
— If the logical processor is not blocking such exceptions (the interruptibility-state field indicates no blocking 
by MOV SS), a debug exception is delivered after VM entry (see below). 
— If the logical processor is blocking such exceptio ns (due to blocking by MOV SS), the pending debug 
exceptions are held pending or lost as would normally be the case.
•If the VM entry is vectoring (with interruption type softwa re interrupt or software exception and with blocking 
by MOV SS), the following items apply:
— For injection of a software interrupt or of a softwa re exception with vector 3 (#BP) or vector 4 (#OF) — or 
a privileged software exception with vector 1 (#DB) — the pending debug exceptions are treated as they 
would had they been encountered normally in guest ex ecution if the corresponding instruction (INT1, INT3, 
or INTO) were executed after a MOV SS that encountered a debug trap.
— For injection of a software exception with a vector other than 3 and 4, the pending debug exceptions may 
be lost or they may be delivered after injection (see below).
If there are no valid pending debug exceptions (as define d above), no pending debug exceptions are delivered after 
VM entry.
If a pending debug exception is delivered after VM entry, it has the priority of “traps on the previous instruction” 
(see Section 6.9 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). Thus, INIT 
signals and system-management interrupts (SMIs) take priori ty of such an exception, as do VM exits induced by 
the TPR threshold (see Section 27.7.7) and pending MTF VM exits (see Section 27.7.8. The exception takes priority 
over any pending non-maskable interrupt (NMI) or external  interrupt and also over VM exits due to the 1-settings 
of the “interrupt-window exiting” and “NMI -window exiting” VM-execution controls.
A pending debug exception delivered after VM entry causes  a VM exit if the bit 1 (#DB) is 1 in the exception 
bitmap. If it does not cause a VM exit, it updates DR6 normally.Vol. 3C 27-25VM ENTRIES
27.7.4 VMX-Preemption Timer
If the “activate VMX-preemption timer” VM-execution cont rol is 1, VM entry starts the VMX-preemption timer with 
the unsigned value in the VMX-preemption timer-value field.
It is possible for the VMX-preemption timer to expire duri ng VM entry (e.g., if the value in the VMX-preemption 
timer-value field is zero). If this happens (and if the VM entry was not to the wait-for-SIPI state), a VM exit occurs 
with its normal priority after any event injection and be fore execution of any instruction following VM entry. For 
example, any pending debug exceptions established by VM entry (see Section 27.7.3) take priority over a timer-
induced VM exit. (The timer-induced VM exit will occur after delivery of the debug exception, unless that exception 
or its delivery causes a different VM exit.)
See Section 26.5.1 for details of the operation of the VM X-preemption timer in VMX non-root operation, including 
the blocking and priority of the VM exits that it causes.
27.7.5 Interrupt-Window Exiting and Virtual-Interrupt Delivery
If “interrupt-window exiting” VM-execution control is 1,  an open interrupt window may cause a VM exit immedi-
ately after VM entry (see Section 26.2 for details). If the “interrupt-window exiting” VM-execution control is 0 but 
the “virtual-interrupt delivery” VM-execution control is 1, a virtual interrupt may be delivered immediately after 
VM entry (see Section 27.3.2.5 and Section 30.2.1).
The following items detail the treatment of these events:
•These events occur after any event injection specified for VM entry.
•Non-maskable interrupts (NMIs) and higher priority events  take priority over these events. These events take 
priority over external interrupts and lower priority events. 
•These events wake the logical processor if it just entered the HLT state because of a VM entry (see Section 
27.7.2). They do not occur if the logical processor just entered the shutdown state or the wait-for-SIPI state.
27.7.6 NMI-Window Exiting
The “NMI-window exiting” VM-execution control may cause a VM exit to occur immediately after VM entry (see 
Section 26.2 for details).
The following items detail the treatment of these VM exits:
•These VM exits follow event injection if such injection is specified for VM entry.
•Debug-trap exceptions (see Section 27.7.3) and higher pr iority events take priority  over VM exits caused by 
this control. VM exits caused by this control take priority over non-maskable interrupts (NMIs) and lower priority events. 
•VM exits caused by this control wake the logical processor if it just entered either the HLT state or the shutdown 
state because of a VM entry (see Section 27.7.2). They do  not occur if the logical processor just entered the 
wait-for-SIPI state.
27.7.7 VM Exits Induced by the TPR Threshold
If the “use TPR shadow” and “virtualize APIC accesses” VM-execution controls are both 1 and the “virtual-interrupt 
delivery” VM-execution control is 0, a VM exit occurs immediately after VM entr y if the value of bits 3:0 of the TPR 
threshold VM-execution control field is greater than the value of bits 7:4 of VTPR (see Section 30.1.1).1
•The VM exits are not blocked if RFLAGS.IF = 0 or by the setti ng of bits in the interruptibility-state field in guest-
state area.
•The VM exits follow event injection if such injection is specified for VM entry.

1. “Virtualize APIC accesses” and “virtual-interrupt delivery” are secondary processor-based VM-execution controls. If bit 31 of the pri-
mary processor-based VM-execution controls is 0, VM entry functions as if these controls were 0. See Section 25.6.2.27-26 Vol. 3CVM ENTRIES
•VM exits caused by this control take priority over system-management interrupts (SMIs), INIT signals, and 
lower priority events. They thus have priority over the VM exits descr ibed in Section 27.7.5, Section 27.7.6, 
and Section 27.7.8, as well as any interrupts or debug ex ceptions that may be pending at the time of VM entry.
•These VM exits wake the logical processor if it just en tered the HLT state as part of a VM entry (see Section 
If such a VM exit is suppressed because the processor ju st entered the shutdown state, it occurs after the
delivery of any event that cause the logical processor to leave the shutdown state while remaining in VMXnon-root operation (e.g., due to an NMI that occurs  while the “NMI-exiting” VM-execution control is 0).
•The basic exit reason is “TPR below threshold.”
27.7.8 Pending MTF VM Exits
As noted in Section 27.6.2, VM entry may cause an MTF VM exit to be pending immediately after VM entry. The 
following items detail the treatment of these VM exits:
•System-management interrupts (SMIs), INIT signals, and higher priority events take priority over these 
VM exits. These VM exits take priority over debug-trap exceptions and lower priority events. 
•These VM exits wake the logical processor if it just en tered the HLT state because of a VM entry (see Section 
27.7.9 VM Entries and Advanced Debugging Features
VM entries are not logged with last-branch records, do no t produce branch-trace messages, and do not update the 
branch-trace store.
27.7.10 User-Interrupt Recognition After VM Entry
A VM entry results in recognition of a pending user inte rrupt if it completes with CR4.UINTR = IA32_EFER.LMA = 1 
and with UIRR ≠ 0; otherwise, no pending user interrupt is recognized.
27.8 VM-ENTRY FAILURES DURING  OR AFTER LOADING GUEST STATE
VM-entry failures due to the checks identified in Sectio n 27.3.1 and failures during th e MSR loading identified in 
Section 27.4 are treated differently from those that occur earlier in VM entry. In these cases, the following steps 
take place:
1. Information about the VM-entry failure is recorded in the VM-exit information fields:
—E x i t  r e a s o n .
•Bits 15:0 of this field contain the basic exit reason . It is loaded with a number indicating the general 
cause of the VM-entry failure. The following numbers are used:
33. VM-entry failure due to invalid guest state. A VM en try failed one of the checks identified in Section 
27.3.1.
34. VM-entry failure due to MSR loading. A VM entry failed in an attempt to load MSRs (see Section 
27.4).
41. VM-entry failure due to machine-check event.  A machine-check event occurred during VM entry 
(see Section 27.9).
•Bit 31 is set to 1 to indicate a VM-entry failure.
•The remainder of the field (bits 30:16) is cleared.Vol. 3C 27-27VM ENTRIES
— Exit qualification. This field is set based on the exit reason.
•VM-entry failure due to invalid guest state. In most cases, the exit qualification is cleared to 0. The 
following non-zero values are used in the cases indicated:
1. Not used.
2. Failure was due to a problem loading the PDPTEs (see Section 27.3.1.6).3. Failure was due to an attempt to inject a non-mask able interrupt (NMI) into a guest that is blocking 
events through the STI blocking bit in the interruptibility-state field.
4. Failure was due to an invalid VMCS link pointer (see Section 27.3.1.5).
VM-entry checks on guest-state fields may be perf ormed in any order. Thus, an indication by exit
qualification of one cause does not imply that there are not also other errors. Different processorsmay give different exit qualifications for the same VMCS.
•VM-entry failure due to MSR loading.  The exit qualification is loaded to indicate which entry in the 
VM-entry MSR-load area caused the problem (1 for the first entry, 2 for the second, etc.).
— All other VM-exit information fields are unmodified.
2. Processor state is loaded as would be done on  a VM exit (see Section 28.5). If this results in 
[CR4.PAE & CR0.PG & ~IA32_EFER.LMA] = 1, page-directory -pointer-table entries (PDPTEs) may be checked 
and loaded (see Section 28.5.4).
3. The state of blocking by NMI is what it was before VM entry.4. MSRs are loaded as specified in the VM-exit MSR-load area (see Section 28.6).
Although this process resembles that of a VM exit, many  steps taken during a VM exit do not occur for these 
VM-entry failures:
•Most VM-exit information fields are not updated (see step 1 above).
•The valid bit in the VM-entry interruption-information field is not cleared.
•The guest-state area is not modified.
•No MSRs are saved into the VM-exit MSR-store area.
27.9 MACHINE-CHECK EVENTS DURING VM ENTRY
If a machine-check event occurs during a VM entry, one of the following occurs:
•The machine-check event is handled as if it occurred before the VM entry:
— If CR4.MCE = 0, operation of the logical processor depends on whether the logical processor is in SMX 
operation:1
•If the logical processor is in SMX operation, an Intel® TXT shutdown condition occurs. The error code 
used is 000CH, indicating “unrecoverable machine-check condition.”
•If the logical processor is outside SMX operation, it goes to the shutdown state.
— If CR4.MCE = 1, a machine-check exception (#MC) is delivered through the IDT.
•The machine-check event is handled after VM entry completes:
— If the VM entry ends with CR4.MCE = 0, operation of the logical processor depends on whether the logical 
processor is in SMX operation:
•If the logical processor is in SMX operation, an Intel® TXT shutdown condition occurs with error code 
000CH (unrecoverable machine-check condition).
1. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logi-
cal processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last 
execution of GETSEC[SENTER]. See Chapter 7, “Safer Mode Extensions Reference‚” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2D.27-28 Vol. 3CVM ENTRIES
— If the VM entry ends with CR4.MCE = 1, a machine-check exception (#MC) is generated:
•If bit 18 (#MC) of the exception bitmap is 0, the exception is delivered through the guest IDT.
•If bit 18 of the exception bitmap is 1, the exception causes a VM exit.
•A VM-entry failure occurs as described in Section 27.8. Th e basic exit reason is 41, for “VM-entry failure due to 
machine-check event.”
The first option is not used if the machine-check event occurs after any guest state has been loaded. The second 
option is used only if VM entry is able to load all guest state.Vol. 3C 28-1CHAPTER 28
VM EXITS
VM exits occur in response to certain instructions and events  in VMX non-root operation as detailed in Section 26.1 
through Section 26.2. VM exits pe rform the following operations:
1. Information about the cause of the VM exit is recorded in the VM-exit information fi elds and VM-entry control 
fields are modified as described in Section 28.2.
2. Processor state is saved in the guest-state area (Section 28.3).
3. MSRs may be saved in the VM-exit MSR-store area (Secti on 28.4). This step is not performed for SMM VM exits 
that activate the dual-monitor treatment of SMIs and SMM.
4. The following may be performed in parallel and in any order (Section 28.5):
— Processor state is loaded based in part on the host-state area and some VM-exit controls. This step is not 
performed for SMM VM exits that activate the dual-m onitor treatment of SMIs and SMM. See Section 
32.15.6 for information on how processo r state is loaded by such VM exits.
— Address-range monitoring is cleared.
5. MSRs may be loaded from the VM-exit MSR-load area  (Section 28.6). This step is not performed for SMM 
VM exits that activate the dual-mon itor treatment of SMIs and SMM.
VM exits are not logged with last-branch records, do not produce branch-trace messages, and do not update the 
Section 28.1 clarifies the nature of the architectural st ate before a VM exit begins. The steps described above are 
detailed in Section 28.2 through Section 28.6. 
management mode (SMM). Under this treatment, ordinary transitions to SMM are replaced by VM exits to a sepa-
rate SMM monitor. Called SMM VM exits , these are caused by the arrival of an SMI or the execution of VMCALL in

rate SMM monitor. Called SMM VM exits , these are caused by the arrival of an SMI or the execution of VMCALL in 
VMX root operation. SMM VM exits diff er from other VM exits in ways that are detailed in Section 32.15.2.
28.1 ARCHITECTURAL STATE BEFORE A VM EXIT
This section describes the architectural state that exists before a VM exit, especially for VM exits caused by events 
that would normally be delivered through the IDT. Note the following:
•An exception causes a VM exit directly  if the bit corresponding to that exception is set in the exception bitmap. 
A non-maskable interrupt (NMI) causes a VM exit directly if the “NMI exiting” VM-execution control is 1. An 
external interrupt causes a VM exit directly if the “exter nal-interrupt exiting” VM-execution control is 1. A start-
up IPI (SIPI) that arrives while a logical processor is in the wait-for-SIPI activity state causes a VM exit directly. 
INIT signals that arrive while the processor is not in the wait-for-SIPI activity state cause VM exits directly.
•An exception, NMI, external interrupt, or software interrupt causes a VM exit indirectly  if it does not do so 
directly but delivery of the event causes a nested exceptio n, double fault, task switch, APIC access (see Section 
30.4), EPT violation, EPT misconfiguration, page-modif ication log-full event (see Section 29.3.6), or SPP-
related event (see Section 29.3.4) that causes a VM exit.
•An event results in a VM exit if it causes a VM exit (directly or indirectly).
The following bullets detail when architectural stat e is and is not updated in response to VM exits:
•If an event causes a VM exit directly, it does not update architectural state as it would have if it had it not 
caused the VM exit:
— A debug exception does not update DR6, DR7, or IA32_DEBUGCTL. (Information about the nature of the 
debug exception is saved in th e exit qualification field.)
— A page fault does not update CR2. (The linear addre ss causing the page fault is saved in the exit-qualifi-
cation field.)28-2 Vol. 3CVM EXITS
— An NMI causes subsequent NMIs to be bloc ked, but only after the VM exit completes.
— An external interrupt does not acknowledge the inte rrupt controller and the interrupt remains pending, 
unless the “acknowledge interrupt on exit” VM-exit contro l is 1. In such a case, the interrupt controller is 
acknowledged and the interrupt  is no longer pending.
— The flags L0 – L3 in DR7 (bit 0, bit 2, bit 4, and bit 6) are not cleared when a task switch causes a VM exit.
— If a task switch causes a VM exit, none of the followi ng are modified by the task switch: old task-state 
segment (TSS); new TSS; old TSS descriptor; new TSS descriptor; RFLAGS.NT1; or the TR register.
— No last-exception record is made if the even t that would do so directly causes a VM exit. 
— If a machine-check exception causes a VM exit direct ly, this does not prevent machine-check MSRs from 
being updated. These are updated by the machine-chec k event itself and not the resulting machine-check 
— If the logical processor is in an inactive state (see Section 25.4.2) and not executing instructions, some 
events may be blocked but others may return the logical processor to the active state. Unblocked events 
may cause VM exits.2 If an unblocked event causes a VM exit directly, a return to the active state occurs 
only after the VM exit completes.3 The VM exit generates any special bus cycle that is normally generated 
when the active state is entered from that activity state.
MTF VM exits (see Section 26.5.2 and Section 27.7.8) are not blocked in the HLT activity state. If an MTF 
VM exit occurs in the HLT activity state, the logical processor returns to the active state only after the VM exit completes. MTF VM exits are blocked the shutdown state and the wait-for-SIPI state.
•If an event causes a VM exit indirectly, the event does update architectural state:
— A debug exception updates DR6, DR7, and the IA32_D EBUGCTL MSR. No debug exceptions are considered 
pending.
— A page fault updates CR2.— An NMI causes subsequent NMIs to be blocked before the VM exit commences.
— An external interrupt acknowledges the interrupt controller and the interrupt is no longer pending.
— If the logical processor had been in an inactive state,  it enters the active state and, before the VM exit 
commences, generates any special bus cycle that is no rmally generated when the active state is entered 
from that activity state.
— There is no blocking by STI or by MOV SS when the VM exit commences.
— Processor state that is normally updated as part of delivery through the IDT (CS, RIP, SS, RSP, RFLAGS) is 
not modified. However, the incomplete deli very of the event may write to the stack.
— The treatment of last-exception records is implementation dependent:
•Some processors make a last-exception record when beginning the delivery of an event through the IDT 
(before it can encounter a nested exception). Such processors perform this update even if the event 
encounters a nested exception that causes a VM exit (including the case where nested exceptions lead 
to a triple fault).
•Other processors delay making a last-exception record until event delivery has reached some event handler successfully (perhaps after one or more nested  exceptions). Such processors do not update the 
last-exception record if a VM exit or triple fault occurs before an event handler is reached.
2. If a VM exit takes the processor from an inactive state resulting from execution of a specific instruction (HLT or MWAIT), the  value 
saved for RIP by that VM exit will reference the following instruction.
3. An exception is made if the logical processor had been inactive due to execution of MWAIT; in th is case, it is considered to have 
become active before the VM exit.Vol. 3C 28-3VM EXITS
•If the “virtual NMIs” VM-execution control is 1, VM en try injects an NMI, and delivery of the NMI causes a 
nested exception, double fault, task switch, EPT viol ation, EPT misconfiguration, page-modification log-full 
event, or SPP-related event, or APIC access that causes a VM exit, virtual-NMI blocking is in effect before the 
VM exit commences.
•If a VM exit results from a fault, EPT violation, EPT mi sconfiguration, page-modification log-full event, or SPP-
related event that is encountered during execution of IRET  and the “NMI exiting” VM-execution control is 0, any 
blocking by NMI is cleared before the VM exit commences. However, the previous state of blocking by NMI may 
be recorded in the exit qualification or in the VM-e xit interruption-information field; see Section 28.2.3.
related event that is encountered during execution of IR ET and the “virtual NMIs” VM-execution control is 1, 
virtual-NMI blocking is cleared before the VM exit commences. However, the previous state of blocking by NMI 
may be recorded in the exit qualification or in the VM-exit interruption-information field; see Section 28.2.3.
•Suppose that a VM exit is caused directly by an x87 FP U Floating-Point Error (#MF) or by any of the following 
events if the event was unblocked due to (and given prio rity over) an x87 FPU Floating-Point Error: an INIT 
signal, an external interrupt, an NMI, an SMI; or a machine-check exception. In these cases, there is no 
blocking by STI or by MOV SS when the VM exit commences.
•Normally, a last-branch record may be made when an even t is delivered through the IDT. However, if such an 
event results in a VM exit before delivery is  complete, no last-branch record is made.
•If machine-check exception results in a VM exit, processor state is suspect and may result in suspect state 
being saved to the guest-state area. A VM monitor should consult the RIPV and EIPV bits in the 
IA32_MCG_STATUS MSR before resuming a guest that caused a VM exit resulting from a machine-check 
•If a VM exit results from a fault, APIC access (see Se ction 30.4), EPT violation, EPT misconfiguration, page-
modification log-full event, or SPP-related event that  is encountered while executing an instruction, data 
breakpoints due to that instruction may have been reco gnized and information about them may be saved in the 
pending debug exceptions field (unless the VM exit clears that field; see Section 28.3.4).
•The following VM exits are considered to happen after an instruction is executed:
— VM exits resulting from debug traps (single-step, I/O breakpoints, and data breakpoints).— VM exits resulting from debug exceptions (data breakp oints) whose recognition was delayed by blocking by 
MOV SS.
— VM exits resulting from some machine-check exceptions.

MOV SS.
— Trap-like VM exits due to execution of MOV to CR8 wh en the “CR8-load exiting” VM-execution control is 0 
and the “use TPR shadow” VM-execution control is 1 (s ee Section 30.3). (Such VM exits can occur only from 
64-bit mode and thus only on processors that support Intel 64 architecture.)
— Trap-like VM exits due to execution of WRMSR when th e “use MSR bitmaps” VM-execution control is 1; the 
value of ECX is in the range 800H–8FFH ; and the bit corresponding to the ECX value in write bitmap for low 
MSRs is 0; and the “virtualize x2APIC mode” VM-execution control is 1. See Section 30.5.
— VM exits caused by APIC-write emulation (see Section 30.4.3.2) that result from APIC accesses as part of 
instruction execution.
For these VM exits, the instruction’s modifications to ar chitectural state complete before the VM exit occurs. 
Such modifications include those to the logical processo r’s interruptibility state (see Table 25-3). If there had 
been blocking by MOV SS, POP SS, or STI before the instru ction executed, such blocking is no longer in effect.
A VM exit that occurs in enclave mode sets bit 27 of the ex it-reason field and bit 4 of the guest interruptibility-state 
field. Before such a VM exit is delivered, an Asynchrono us Enclave Exit (AEX) occurs (see Chapter 37, “Enclave 
Exiting Events”). An AEX modifies architectural state (Sec tion 37.3). In particular, the processor establishes the 
following architectural state as indicated:
•The following bits in RFLAGS are cleared: CF, PF, AF, ZF, SF, OF, and RF.
•FS and GS are restored to the values they had prior to the most recent enclave entry.
•RIP is loaded with the AEP of interrupted enclave thread.
•RSP is loaded from the URSP field in the enclave’s state-save area (SSA).28-4 Vol. 3CVM EXITS
28.2 RECORDING VM-EXIT INFORMATIO N AND UPDATING VM-ENTRY CONTROL 
FIELDS
VM exits begin by recording information about the nature of  and reason for the VM exit in the VM-exit information 
fields. Section 28.2.1 to Section 28.2.5 detail the use of these fields.
In addition to updating the VM-exit information fields, th e valid bit (bit 31) is cleared in the VM-entry interruption-
information field. If bit 5 of the IA32_VMX_MISC MSR (index  485H) is read as 1 (see Appendix A.6), the value of 
IA32_EFER.LMA is stored into the “I A-32e mode guest” VM-entry control.1
28.2.1 Basic VM-Exit Information
Section 25.9.1 defines the basic VM-exit information fields. The following items detail their use.
•Exit reason.
— Bits 15:0 of this field contain the basic exit reason. It  is loaded with a number indicating the general cause 
of the VM exit. Appendix C lists th e numbers used and their meaning.
— Bit 25 is set if the “prematurely busy shadow stack” VM-exit control is 1 and the VM exit caused a shadow 
stack become prematurely busy (see Section 26.4.3). Otherwise, the bit is cleared.
— Bit 26 of this field is set to 1 if the VM exit occurre d after assertion of a bus lock while the “VMM bus-lock 
detection” VM-execution control was 1. Such VM exits in clude those that occur due to the 1-setting of that 
control as well as others that might occur during execution of an instruction that asserted a bus lock.
— Bit 27 of this field is set to 1 if the VM exit occu rred while the logical processor was in enclave mode.
Such VM exits include those caused by interrupt s, non-maskable interrupts, system-management 
interrupts, INIT signals, and exceptions occurring in enclave mode as well as exceptions encountered 
during the delivery of such events incident to enclave mode.
A VM exit also sets this bit if it is incident to deli very of an event injected by  VM entry and the guest inter-
ruptibility-state field indicates an enclave interruption (bit 4 of the field is 1).
— The remainder of the field (bits 31:28 and bits 24:16) is cleared to 0 (certain SMM VM exits may set some 
of these bits; see Section 32.15.2.3).2
•Exit qualification.  This field is saved for VM exits due to the following causes: debug exceptions; page-fault 
exceptions; start-up IPIs (SIPIs); system-management interrupts (SMIs) that arrive immediately after the 
execution of I/O instructions; task switches; INVEPT; INVLPG; INVPCID; INVVPID; LGDT; LIDT; LLDT; LTR; 
SGDT; SIDT; SLDT; STR; VMCLEAR; VMPTRLD; VMPTRST; VMREAD; VMWRITE; VMXON; WBINVD; WBNOINVD; XRSTORS; XSAVES; control-register accesses; MOV DR; I/O instructions; MWAIT; accesses to the 
APIC-access page (see Section 30.4); EPT violations (see Section 29.3.3.2); EOI virtualization (see Section 
30.1.4); APIC-write emulation (see Section 30.4.3.3); page-modification log full (see Section 29.3.6); SPP-related events (see Section 29.3.4); and instruction timeout (see Section 26.2). For all other VM exits, this field 
is cleared. The following items provide details:
— For a debug exception, the exit qualification co ntains information about the debug exception. The 
information has the format given in Table 28-1.
1. Bit 5 of the IA32_VMX_MISC MSR is read as 1 on any logical processor that suppo rts the 1-setting of the “unrestricted guest” V M-
2. Bit 31 of this field is set on certain VM-entry failures; see Section 27.8.Table 28-1.  Exit Qualification for Debug Exceptions
3:0 B3 – B0. When set, each of these bits indicates that the co rresponding breakpoint condition was met. Any of 
these bits may be set even if its corres ponding enabling bit in DR7 is not set.
10:4 Not currently defined.Vol. 3C 28-5VM EXITS
— For a page-fault exception, the exit qualification cont ains the linear address that caused the page fault. On 
processors that support Intel 64 architecture, bits 63:32 are cleared if the logical processor was not in 64-
bit mode before the VM exit.
If the page-fault exception occurred during execution of an instruction in enclave mode (and not during 
delivery of an event incident to enclave mode), bits 11:0 of the exit qualification are cleared.
— For a start-up IPI (SIPI), the exit qualification contai ns the SIPI vector information in bits 7:0. Bits 63:8 of 
the exit qualification are cleared to 0.
— For a task switch, the exit qualification contains details about the task switch, encoded as shown in 
Table 28-2.
— For INVLPG, the exit qualification contains the linear-address operand of the instruction.
•On processors that support Intel 64 architecture, bits 63:32 are cleared if the logical processor was not 
in 64-bit mode before the VM exit.
•If the INVLPG source operand specifies an unusable segment, the linear addre ss specified in the exit 
qualification will match the linear address that the IN VLPG would have used if no VM exit occurred. This 
address is not architecturally defined and may be implementation-specific.11 BLD. When set, this bit indicates that a bus lock was asserted wh ile OS bus-lock detection was enabled and 
CPL > 0 (see Section 18.3.1.6  (‘‘OS Bus-Lock Detection”)).1
12 Not currently defined.
13 BD. When set, this bit in dicates that the cause of th e debug exception is “debug register access detected.”
14 BS. When set, this bit in dicates that the cause of th e debug exception is either the execution of a single 
instruction (if RFLAGS.TF = 1 and IA32_DEBUGCTL.BTF = 0) or a taken branch (if 
RFLAGS.TF = DEBUGCTL.BTF = 1).
15 Not currently defined.
16 RTM. When set, this bi t indicates that a debug exception (#DB) or a breakpoint exception (#BP) occurred 
inside an RTM region while advanced debugging of RTM transactional regions was enabled (see Section 
16.3.7, “RTM-Enabled Debugger Support,” of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1).2
63:17 Not currently defined. Bits 63:32 exist only on processors that support Intel 64 architecture.
NOTES:
2. In general, the format of this field matches that of DR6. However, DR6 clears  bit 16 to indicate an RTM-re lated exception, while this 
field sets  the bit to indicate that condition.
Table 28-2.  Exit Qualification for Task Switches
15:0 Selector of task-state  segment (TSS) to which th e guest attempted to switch
29:16 Not currently definedTable 28-1.  Exit Qualificatio n for Debug Exceptions (Contd.)
Bit Position(s) Contents28-6 Vol. 3CVM EXITS
— For INVEPT, INVPCID, INVVPID, LGDT, LIDT, LLDT, LTR, SGDT, SIDT, SLDT, STR, VMCLEAR, VMPTRLD, 
VMPTRST, VMREAD, VMWRITE, VMXON, XRSTORS, and XSAVES, the exit qualification receives the value of the instruction’s displacement field, which is sign-extended to 64 bits if necessary (32 bits on processors 
that do not support Intel 64 architecture). If the instruction has no displacement (for example, has a 
register operand), zero is stored into the exit qualification.
On processors that support Intel 64  architecture, an exception is made for RIP-relative addressing (used

On processors that support Intel 64  architecture, an exception is made for RIP-relative addressing (used 
only in 64-bit mode). Such addressing causes an instruction to use an address that is the sum of the 
displacement field and the value of RIP that references  the following instruction. In this case, the exit 
qualification is loaded with the sum of the di splacement field and the appropriate RIP value.
In all cases, bits of this field beyond the instruct ion’s address size are undefined. For example, suppose 
that the address-size field in the VM-exit instruct ion-information field (see Section 25.9.4 and Section 
28.2.5) reports an n-bit address size. Then bits 63: n (bits 31: n on processors that do not support Intel 64 
architecture) of the instruction displacement are undefined.
— For a control-register access, the exit qualification contains information about the access and has the 
format given in Table 28-3.
— For MOV DR, the exit qualification contains informat ion about the instruction and has the format given in 
Table 28-4.
— For an I/O instruction, the exit qualification contains information about the instruction and has the format 
given in Table 28-5.
— For MWAIT, the exit qualification contains a value that indicates whether address-range monitoring 
hardware was armed. The exit qualification is set eith er to 0 (if address-range monitoring hardware is not 
armed) or to 1 (if address-range monitoring hardware is armed).
— WBINVD and WBNOINVD use the same basic exit reason  (see Appendix C). For WBINVD, the exit qualifi-
cation is 0, while for WBNOINVD it is 1.
— For an APIC-access VM exit resulting from a linear access or a guest-physical access to the APIC-access 
page (see Section 30.4), the exit qualification cont ains information about the access and has the format 
given in Table 28-6.
1
If the access to the APIC-access page occurred during ex ecution of an instruction in enclave mode (and not 
during delivery of an event incident to enclave mo de), bits 11:0 of the exit qualification are cleared.
Such a VM exit that set bits 15:12 of the exit qualificat ion to 0000b (data read during instruction execution) 
or 0001b (data write during instruction execution) se t bit 12—which distinguishes data read from data 
write—to that which would have been stored in bit 1—W/R—of the page-fault error code had the access 
caused a page fault instead of an APIC-access VM exit. This implies the following:
•For an APIC-access VM exit caused by the CLFLUSH and CLFLUSHOPT instructions, the access type is 
“data read during instruction execution.”
•For an APIC-access VM exit caused by the ENTER in struction, the access type is “data write during 
instruction execution.”31:30 Source of task switch initiation:
0: CALL instruction
1: IRET instruction
2: JMP instruction3: Task gate in IDT
63:32 Not currently defined. These bits exist only on processors that support Intel 64 architecture.
1. The exit qualification is undefined if the access was part of the logging of a branch record or a processor-event-based-sampl ing 
(PEBS) record to the DS save ar ea. It is recommended that software configure the paging structures so that no address in the DS  
save area translates to an ad dress on the APIC-access page.Table 28-2.  Exit Qualificatio n for Task Switches (Contd.)
Bit Position(s) ContentsVol. 3C 28-7VM EXITS
•For an APIC-access VM exit caused by the MASKMOVQ instruction or the MASKMOVDQU instruction, the 
access type is “data write during instruction execution.”
•For an APIC-access VM exit caused by the MONITOR instruction, the access type is “data read during 
instruction execution.”
•For an APIC-access VM exit caused directly by an access to a linear address in the DS save area (BTS or 
PEBS), the access type is “linear access for monitoring.”
•For an APIC-access VM exit caused by a guest-physical access performed for an access to the DS save 
area (e.g., to access a paging structure to translat e a linear address), the access type is “guest-physical 
access for monitoring or trace.”
•For an APIC-access VM exit caused by trace-address pre-translation (TAPT) when the “Intel PT uses 
guest physical addresses” VM-execution control is 1, the access type is “guest-physical access for 
monitoring or trace.”
Such a VM exit stores 1 for bit 31 for IDT-vectoring info rmation field (see Section 28.2.4) if and only if it 
sets bits 15:12 of the exit qualification to 0011b ( linear access during event delivery) or 1010b (guest-
physical access during event delivery).Table 28-3.  Exit Qualification for Control-Register Accesses 
Bit Positions Contents
3:0 Number of control register (0 for CLTS and LMSW). Bit 3 is always 0 on processors th at do not support Intel 64 
architecture as they do not support CR8.
5:4 Access type:
0=  M O V  t o  C R
1 = MOV from CR
2 = CLTS3=  L M S W
6L M S W  o p e r a n d  t y p e :
0=  r e g i s t e r
1 = memory
For CLTS and MOV CR, cleared to 0
7 Not currently defined
11:8 For MOV CR, the general-purpose register:
0=  R A X
1=  R C X
2=  R D X3=  R B X
4=  R S P
5=  R B P6=  R S I
7=  R D I
8–15 represent R8–R15, respectively (used only on  processors that suppor t Intel 64 architecture)
For CLTS and LMSW, cleared to 0
15:12 Not curr ently defined
31:16 For LMSW, the LMSW source data
63:32 Not currently defined. These bits exist only on processors that supp ort Intel 64 architecture.28-8 Vol. 3CVM EXITS
See Section 30.4.4 for further discussion of these instructions and APIC-access VM exits.
For APIC-access VM exits resulting from physical accesses to the APIC-access page (see Section 30.4.6), 
the exit qualification is undefined.
— For an EPT violation, the exit qualification contains information about the access causing the EPT violation 
and has the format given in Table 28-7.
As noted in that table, the format and meaning of the exit qualification depends on the setting of the 
“mode-based execute control for EPT” VM-execution control and whether the processor supports advanced 
VM-exit information for EPT violations.1
An EPT violation that occurs during as a result of ex ecution of a read-modify-write operation sets bit 1 (data 
write). Whether it also sets bit 0 (data read) is implementation-specific and, for a given implementation, may differ for different kinds of read-modify-write operations.
1. Software can determine whether advanced VM -exit information for EPT violations is su pported by consulting the VMX capability 
MSR IA32_VMX_EPT_VPID_CAP (see Appendix A.10).Table 28-4.  Exit Qualification for MOV DR
2:0 Number of debug register3 Not currently defined
4 Direction of access (0
= MOV to DR; 1 = MOV from DR)
7:5 Not curren tly defined
11:8 General-purpose register:
0 = RAX
1=  R C X
2=  R D X
3=  R B X4=  R S P
5=  R B P
6=  R S I7=  R D I
8 –15 = R8 – R15, respectively
63:12 Not currently defined. Bits 63 :32 exist only on processors that  support Intel 64 architecture.
Table 28-5.  Exit Qualification for I/O Instructions
2:0 Size of access:
0=  1 - b y t e
1=  2 - b y t e3=  4 - b y t e
Other values not used
3 Direction of the attempted access (0
= OUT, 1 = IN)
4 String instruction (0 = n ot string; 1 = string)Vol. 3C 28-9VM EXITS
Bit 12 reports “NMI unblocking due to IRET”; see Section 28.2.3.
Bit 16 is set for certain accesses that are asynchronous to instruction execution and not part of event 
delivery. These include trace-address pre-translation (TAPT) for Intel PT (see Section 26.5.4), accesses 
related to PEBS on processors with the “EPT-friendly ” enhancement (see Section 20.9.5), and accesses as 
part of user-interrupt delivery (see Section 7.4.2).
— For VM exits caused as part of EOI virtualization (Sec tion 30.1.4), bits 7:0 of the exit qualification are set 
to vector of the virtual interrupt that was dismissed by the EOI virtualization. Bits above bit 7 are cleared.
— For APIC-write VM exits (Section 30.4.3.3), bits 11:0 of the exit qualification are set to the page offset of 
the write access that caused the VM exit.1 Bits above bit 11 are cleared.
— For a VM exit due to a page-modification log-full even t (Section 29.3.6), bit 12 of the exit qualification 
reports “NMI unblocking due to IRET” (see Section 28.2. 3). Bit 16 is set if the VM exit occurs during TAPT, 
EPT-friendly PEBS, or user-interru pt delivery. All other bits of the exit qualification are undefined.
— For a VM exit due to an SPP-related event (Section 29.3 .4), bit 11 of the exit qualification indicates the type 
of event: 0 indicates an SPP misconfiguration and 1 indi cates an SPP miss. Bit 12 of the exit qualification 5 REP prefixed (0 = not REP; 1 = REP)
6 Operand encoding (0 = DX, 1 = immediate)
15:7 Not currently defined
31:16 Port number (as specified in DX or in an immediate operand)63:32 Not currently defined. These bits exist only on processors that supp ort Intel 64 architecture.
Table 28-6.  Exit Qualification for APIC-Access VM Exit s from Linear Accesses an d Guest-Physic al Accesses

11:0 • If the APIC-access VM exit is due to a linear a ccess, the offset of access within the APIC page.
• Undefined if the APIC-access VM exit is due a guest-physical access
15:12 Access type:
0 = linear access for a data read during instruction execution
1 = linear access for a data write during instruction execution2 = linear access for an instruction fetch
3 = linear access (read or write) during event delivery
4 = linear access for monitoring10 = guest-physical access during event delivery
11 = guest-physical access for monitoring or trace
15 = guest-physical access for an instruction fetch or during instruction execution
16 This bit is set for certain accesses that are asynchronous  to instruction execution and not part of event delivery. 
These includes guest-physical accesses re lated to trace output by Intel PT (s ee Section 26.5.4), accesses related 
to PEBS on processors with the “EPT-friendly” enhancement (see Section 20.9.5), and accesses that occur during user-interrupt delivery (see Section 7.4.2).
63:17 Not currently defined. Bits 63:32 exist only on processors that supp ort Intel 64 architecture.
1. Execution of WRMSR with ECX = 83FH (self-IPI MSR) can lead to an APIC-write VM exit; the exit qualification for such an APIC- write 
VM exit is 3F0H.Table 28-5.  Exit Qualificatio n for I/O Instructions (Contd.)
Bit Position(s) Contents28-10 Vol. 3CVM EXITS
reports “NMI unblocking due to IRET” (see Section 28.2.3). Bit 16 is set if the VM exit occurs during TAPT 
— If the “PASID translation” VM-execution control, PASID translation is performed for executions of the 
ENQCMD and ENQCMDS instructions (see Section 26.5. 8). PASID translation may fail, resulting in a 
VM exit. Such a VM exit saves an exit qua lification specified in the following items:
•For ENQCMD, the exit qualification is IA32_PASID[19:0].
•For ENQCMDS, the exit qualification contains the low 32 bits of the instruction’s source operand (which 
had been read from memory prior to PASID translation).
— For a VM exit due to an instruction timeout (Section 26 .2), bit 0 indicates (if set) that the context of the 
virtual machine is invalid and that the VM should not be resumed. Bit 12 of the exit qualification reports 
“NMI unblocking due to IRET” (see Section 28.2.3). Al l other bits of the exit qualification are undefined.
•Guest linear address.  For some VM exits, this field receives a line ar address that pertains to the VM exit. The 
field is set for different VM exits as follows:
— VM exits due to attempts to execute LMSW with a memory operand. In these cases, this field receives the 
linear address of that operand. Bits 63:32 are cleared if the logical processor was not in 64-bit mode before 
the VM exit.
— VM exits due to attempts to execute INS or OUTS for which the relevant segment is usable (if the relevant 
segment is not usable, the value is undefined). (ES is  always the relevant segment for INS; for OUTS, the 
relevant segment is DS unless overridden by an instru ction prefix.) The linear address is the base address 
of relevant segment plus (E)DI (for INS) or (E)SI (for  OUTS). Bits 63:32 are cleared if the logical processor 
was not in 64-bit mode before the VM exit.
Table 28-7.  Exit Qualification for EPT Violations
0 Set if the access causing the EPT violation was a data read.1
1 Set if the access causing the EPT violation was a data write.1
2 Set if the access causing the EPT violation was an instruction fetch.
3 The logical-AND of bit 0 in the EPT paging-structure entr ies used to translate the gu est-physical address of the 
access causing the EPT violation (indicates whether the guest-physical address was readable).2
4 The logical-AND of bit 1 in the EPT paging-structure entr ies used to translate the gu est-physical address of the 
access causing the EPT violation (indicates whether the guest-physical address was writeable).2
5 The logical-AND of bit 2 in the EPT paging-structure entr ies used to translate the gu est-physical address of the 
access causing the EPT violation.2
If the “mode-based execute control for EPT” VM-execution control is 0, this indicates whether the guest-physical 
address was executable. If that contro l is 1, this indicates whether the guest-physical address was executable 
for supervisor-mode linear addresses.
6 If the “mode-based execute control” VM-execution control is 0,  the value of this bit is undefined. If that control is 
1, this bit is the logical-AND of bit 10 in the EPT paging -structure entries used to translate the guest-physical 
address of the access causing the EPT vi olation. In this case, it indicates whether the guest-physical address was 
executable for user-mode linear addresses.3
7 Set if the guest linear-address field is valid.
The guest linear-address field is valid for all EPT violatio ns except those resulting fr om an attempt to load the 
guest PDPTEs as part of the execution of the MOV CR in struction and those due to tr ace-address pre-translation 
(TAPT; Section 26.5.4).Vol. 3C 28-11VM EXITS
— VM exits due to EPT violations that set bit 7 of the exit qualification (see Table 28-7; these are all EPT 
violations except those resulting from an attempt to load the PDPTEs as of execution of the MOV CR 
instruction and those due to TAPT). The linear addre ss may translate to the guest-physical address whose 
access caused the EPT violation. Alternatively, tran slation of the linear address may reference a paging-8I f  b i t 7  i s  1 :
• Set if the access causing the EPT violation is to a gues t-physical address that is the translation of a linear 
address.
• Clear if the access causing the EPT violation is to a pa ging-structure entry as part of a page walk or the 
update of an accessed or dirty bit.
Reserved if bit 7 is  0 (cleared to 0).
9 If bit 7 is 1, bit 8 is 1, and the processor supports advanced VM-exit information for EPT violations,4 this bit is 0 
if the linear address is a supervisor-mode linear address and 1 if it is a user-mode linear address. (If CR0.PG = 0, the translation of every linear address is a user-mode linear address and thus this bit will be 1.) Otherwise, this 
bit is undefined.
10 If bit 7 is 1, bit 8 is 1, and the processor supports advanced VM-exit information for EPT violations,
4 this bit is 0 
if paging translates the linear address to a read-only page and 1 if it translates to a read/write page. (If CR0.PG = 
0, every linear address is read/write and thus this  bit will be 1.) Otherwise, this bit is undefined.
11 If bit 7 is 1, bit 8 is 1, and the processor supports advanced VM-exit information for EPT violations,4 this bit is 0 
if paging translates the linear address to an executable pa ge and 1 if it translates to an execute-disable page. (If 
CR0.PG = 0, CR4.PAE = 0, or IA32_EFER.NXE = 0, every linear address is executable and thus this bit will be 0.) 
Otherwise, this bit is undefined.
12 NMI unblocking due to IRET (see Section 28.2.3).
13 Set if the access caus ing the EPT violation was a shadow-stack access.
14 If supervisor shadow-stack control is enabled (by setting bit 7 of EPTP), this  bit is the same as bit 60 in the EPT 
paging-structure entry that maps the page of the guest- physical address of the acce ss causing the EPT violation. 
Otherwise (or if translation of the guest-physical address terminates before reaching an EPT paging-structure 
entry that maps a page),  this bit is undefined.
15 This bit is set if the EPT violation was caused as a re sult of guest-paging verification. See Section 29.3.3.2.
16 This bit is set if the acce ss was asynchronous to instruction execution not the result of event delivery. The bit is 
set if the access is related to tr ace output by Intel PT (see Section 26.5.4), accesses related to PEBS on 
processors with the “EPT-friendly” enhancement (see Sectio n 20.9.5), or to user-interrupt delivery (see Section 
7.4.2). Otherwise, this bit is cleared.
63:17 Not currently defined. Bits 63:32 exist only on processors that suppor t Intel 64 architecture.
NOTES:
1. If accessed and dirty flags for EPT are enabled, processor a ccesses to guest paging -structure entries are treated as writes with 
regard to EPT violations (see Section 29.3.3.2). If such an acce ss causes an EPT violation, the processor sets both bit 0 and b it 1 of 
the exit qualification.
2. Bits 5:3 are cleared to 0 if either (1) any of EPT paging-struc ture entries used to translate the guest-physical address of t he access 
causing the EPT violation is not present; or (2) 4-level EPT is in use and the guest-physical address sets any bits in the rang e 51:48 
(see Section 29.3.2).
3. Bit 6 is cleared to 0 if (1) the “mode-based execute control” VM-execution control is 1; and (2) either (a) any of EPT paging-st ructure

NOTES:
3. Bit 6 is cleared to 0 if (1) the “mode-based execute control” VM-execution control is 1; and (2) either (a) any of EPT paging-st ructure 
entries used to translate the guest-physical address of the acce ss causing the EPT violation is not present; or (b) 4-level EPT is in use 
and the guest-physical addre ss sets any bits in  the range 51:48 (see Section 29.3.2).
4. Software can determine whether advanced VM-exit information for EPT violations is supported by consulting the VMX capability  
MSR IA32_VMX_EPT_VPID_CA P (see Appendix A.10).Table 28-7.  Exit Qualificatio n for EPT Violations (Contd.)
Bit Position(s) Contents28-12 Vol. 3CVM EXITS
structure entry whose access caused the EPT violation.  Bits 63:32 are cleared if the logical processor was 
not in 64-bit mode before the VM exit.
If the EPT violation occurred during execution of an in struction in enclave mode (and not during delivery of 
an event incident to enclave mode), bits 11:0 of this field are cleared.
— VM exits due to SPP-related events.
— If the “prematurely busy shadow stack” VM-exit contro l is 1, certain VM exits (besides those noted above) 
save the linear address that pertains to the VM exit if the VM exit caused a shadow stack to become 
prematurely busy (see Section 26.4.3). This is tr ue for VM exits due for these reasons: EPT misconfigu-
ration, page-modification log-full event, and instruction timeout. (A VM exit due to instruction timeout that 
sets bit 0 of the exit qualification, indicating that VM context is invalid,  does not save a valid linear address.)
— For all other VM exits, the field is undefined.
•Guest-physical address.  For a VM exit due to an EPT violation, an EPT misconfiguration, or an SPP-related 
event, this field receives the guest-physical address th at caused the EPT violation or EPT misconfiguration. For 
all other VM exits, the field is undefined.
If the EPT violation or EPT misconfiguration occurred during execution of an instruction in enclave mode (and 
not during delivery of an event incident to en clave mode), bits 11:0 of this field are cleared.
28.2.2 Information for VM Exits Due to Vectored Events
Section 25.9.2 defines fields containing information for VM exits due to the following events: exceptions (including 
those generated by the instructions INT1, INT3, INTO, BOUN D, UD0, UD1, and UD2); external interrupts that occur 
while the “acknowledge interrupt on  exit” VM-exit control is 1; and non-maskable interrupts (NMIs).1 Such 
VM exits include those that occur on an attempt at a task switch that causes an exception before generating the 
VM exit due to the task switch that causes the VM exit.
The following items detail the use of these fields:
•VM-exit interruption information  (format given in Table 25-19). The following items detail how this field is 
established for VM exits due to these events:
— For an exception, bits 7:0 receive the exception vector  (at most 31). For an NMI, bits 7:0 are set to 2. For 
an external interrupt, bits 7:0 receive the vector.
— Bits 10:8 are set to 0 (external interrupt), 2 (n on-maskable interrupt), 3 (hardware exception), 5 
(privileged software exception), or 6 (software except ion). Hardware exceptions comprise all exceptions 
except the following:
•Debug exceptions (#DB) generated by the INT1 instru ction; these are privileged software exceptions. 
(Other debug exceptions are considered hardware exceptions, as are those caused by executions of 
INT1 in enclave mode.)
•Breakpoint exceptions (#BP; generated by INT3) an d overflow exceptions (#OF; generated by INTO); 
these are software exceptions. (A #BP that occu rs in enclave mode is considered a hardware 
BOUND-range exceeded exceptions (#BR; generated by BOUND) and invalid opcode exceptions (#UD) 
generated by UD0, UD1, and UD2 are hardware exceptions.
— Bit 11 is set to 1 if the VM exit is caused by a hardware exception that would have delivered an error code 
on the stack. This bit is always 0 if the VM exit occurred while the logical processor was in real-address 
mode (CR0.PE=0).2 If bit 11 is set to 1, the error code is plac ed in the VM-exit interruption error code (see 
below).
— Bit 12 reports “NMI unblocking due to IRET”; see Sectio n 28.2.3. The value of this bit is undefined if the 
VM exit is due to a double fault (the interruption type is hardware exception and the vector is 8).
1. INT1 and INT3 refer to the instructions with opcodes F1 and CC, respectively, and not to INT n with value 1 or 3 for n.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, a logical processor cannot be in re al-
address mode unless the “u nrestricted guest” VM -execution control and bit 31 of the primary processor-based VM-execution con-
trols are both 1.Vol. 3C 28-13VM EXITS
— Bits 30:13 are always set to 0.
— Bit 31 is always set to 1.
For other VM exits (including those due to external inte rrupts when the “acknowledge interrupt on exit” VM-exit 
control is 0), the field is marked invalid (by clearing  bit 31) and the remainder of the field is undefined.
•VM-exit interruption error code .
— For VM exits that set both bit 31 (valid) and bit 11 (err or code valid) in the VM-exit interruption-information 
field, this field receives the error code that would ha ve been pushed on the stack had the event causing the 
VM exit been delivered normally through the IDT. The EXT bit is set in this field exactly when it would be set 
normally. For exceptions that occur during the delivery of double fault (if the IDT-vectoring information field 
indicates a double fault), the EXT bit is set to 1, assuming that (1) that the exception would produce an 
error code normally (if not incident to double-fault delivery) and (2) that the error code uses the EXT bit 
(not for page faults, which use a different format).
— For other VM exits, the value of this field is undefined.
28.2.3 Information About NMI Unblocking Due to IRET
A VM exit may occur during execution of the IRET instruction for reasons including the following: faults, EPT viola-
tions, page-modification log-full events, SP P-related events, or instruction timeouts.
An execution of IRET that commences while non-maskable interrupts (NMIs) are blocked will unblock NMIs even if 
a fault or VM exit occurs; the state saved by such a VM exit will indicate that NMIs were not blocked.
VM exits for the reasons enumerated above provide more information to software by saving a bit called “NMI 
unblocking due to IRET.” This bit is defined if (1) either th e “NMI exiting” VM-execution control is 0 or the “virtual 
NMIs” VM-execution control is 1; (2) the VM exit does not set the valid bit in the IDT-vectoring information field (see Section 28.2.4); and (3) the VM exit is not due to a doub le fault. In these cases, the bit is defined as follows:
•The bit is 1 if the VM exit resulted from a memory acce ss as part of execution of the IRET instruction and one 
of the following holds:
— The “virtual NMIs” VM-execution control is 0 and blocking by NMI (see Table 25-3) was in effect before 
execution of IRET.
— The “virtual NMIs” VM-execution control is 1 and virt ual-NMI blocking was in effect before execution of 
IRET.
•The bit is 0 for all other relevant VM exits.
For VM exits due to faults, NMI unblocking due to IRET is  saved in bit 12 of the VM-exit interruption-information 
field (Section 28.2.2). For VM exits due to EPT violations , page-modification log-full events, SPP-related events, 
and instruction timeouts, NMI unblocking due to IRET is sa ved in bit 12 of the exit qualification (Section 28.2.1).
(Executions of IRET may also incur VM exits due to AP IC accesses and EPT misconfigurations. These VM exits do 
not report information about NMI unblocking due to IRET.)
28.2.4 Information for VM Exits During Event Delivery
Section 25.9.3 defined fields containing information for VM exits that occur while delivering an event through the 
IDT and as a result of any of the following cases:1
•A fault occurs during event delivery and causes a VM exit (because the bit associated with the fault is set to 1 
in the exception bitmap).
•A task switch is invoked through a task gate in the IDT. The VM exit occurs due to the task switch only after the 
initial checks of the task switch pass (see Section 26.4.2).
•Event delivery causes an APIC-access VM exit (see Section 30.4).
1. This includes the case in which a VM exit occurs while delivering a software interrupt (INT n) through the 16-bit IVT (interrupt vec-
tor table) that is used in  virtual-8086 mode with virtual-machine extensions (if RFLAGS.VM = CR4.VME = 1).28-14 Vol. 3CVM EXITS
•An EPT violation, EPT misconfiguration, page-modificatio n log-full event, or SPP-related event that occurs 
during event delivery.
•Any of the above VM exits that occur during user-interrupt notification processing (see Section 7.5.2). Such VM exits will be treated as if they occurred during deliv ery of an external interrupt with the vector UINV.
These fields are used for VM exits that occur during delivery of events injected as part of VM entry (see Section 
27.6.1.2).
A VM exit is not considered to occur during even t delivery in any of the following circumstances:

•The original event causes the VM exit directly (for ex ample, because the original event is a non-maskable 
interrupt (NMI) and the “NMI exiting” VM-execution control is 1).
•The original event results in a double-fault exception that causes the VM exit directly.
•The VM exit occurred as a result of fetching the first instruction of the handler invoked by the event delivery.
•The VM exit is caused by a triple fault.
•The original event was a software interrupt (INT n) executed in virtual-8086 mode with EFLAGS.IOPL < 3 and 
the VM exit was due to a general-protection exception (#GP) that occurred because either CR4.VME = 0 or bit 
n of the software interrupt redirection bit map in the TSS is set.
•IDT-vectoring information (format given in Table 25-20). Th e following items detail how this field is established 
for VM exits that occur during event delivery:
— If the VM exit occurred during delivery of an exception, bits 7:0 receive the exception vector (at most 31). 
If the VM exit occurred during delivery of an NMI, bits 7:0 are set to 2. If the VM exit occurred during 
delivery of an external interrupt, bits 7:0 receive the vector.
— Bits 10:8 are set to indicate the type of event th at was being delivered when the VM exit occurred: 0 
(external interrupt), 2 (non-maskable interrupt), 3 (hardware exception), 4 (software interrupt), 5 
(privileged software interrupt), or 6 (software exception).
Hardware exceptions comprise all exceptions except the following:1
— Bit 11 is set to 1 if the VM exit occurred during delivery of a hardware exception that would have delivered 
an error code on the stack. This bit is always 0 if the VM exit occurred while the logical processor was in 
real-address mode (CR0.PE=0).2 If bit 11 is set to 1, the error code is placed in the IDT-vectoring error 
code (see below).
— Bit 12 is undefined.
For other VM exits, the field is marked invalid (by clearing bit 31) and the remainder of the field is undefined.
•IDT-vectoring error code. 
1. In the following items, INT1 and INT3 refer to the instru ctions with opcodes F1 and CC , respectively, and not to INT n with value 1 or 
3 for n.
trols are both 1.Vol. 3C 28-15VM EXITS
— For VM exits that set both bit 31 (valid) and bit 11 (erro r code valid) in the IDT-vectoring information field, 
this field receives the error code that would have b een pushed on the stack by the event that was being 
delivered through the IDT at the time of the VM exit. Th e EXT bit is set in this field when it would be set 
normally.
28.2.5 Information for VM Exits Due to Instruction Execution
Section 25.9.4 defined fields containing information for VM exits that occur due to instruction execution. (The VM-
exit instruction length is also used for VM exits that occu r during the delivery of a software interrupt or software 
exception.) The following items detail their use.
•VM-exit instruction length.  This field is used in the following cases:
— For fault-like VM exits due to attempts to execute one of the following instructions that cause VM exits 
unconditionally (see Section 26.1.2) or based on th e settings of VM-execution controls (see Section 
26.1.3): CLTS, CPUID, ENCLS, GETSEC, HLT, IN, INS, INVD, INVEPT, INVLPG, INVPCID, INVVPID, LGDT, 
LIDT, LLDT, LMSW, LOADIWKEY, LTR, MONITOR, MOV C R, MOV DR, MWAIT, OUT, OUTS, PAUSE, PCONFIG, 
RDMSR, RDPMC, RDRAND, RDSEED, RDTSC, RDTSCP, RSM, SGDT, SIDT, SLDT, STR, TPAUSE, UMWAIT, 
VMCALL, VMCLEAR, VMLAUNCH, VMPTRLD, VMPTRST, VMREAD, VMRESUME, VMWRITE, VMXOFF, VMXON, 
WBINVD, WBNOINVD, WRMSR, XRSTORS, XSETBV, and XSAVES.1
— For VM exits due to software exceptions (those generated by executions of INT3 or INTO) or privileged 
software exceptions (those generated by executions of INT1).
— For VM exits due to faults encountered during delivery of a software interrupt, privileged software 
exception, or software exception.
— For VM exits due to attempts to effect a task swit ch via instruction executio n. These are VM exits that 
produce an exit reason indicating task  switch and either of the following:
•An exit qualification indicating execution of CALL, IRET, or JMP instruction.
•An exit qualification indicating a task gate in the IDT and an IDT-vectoring information field indicating 
that the task gate was encountered during delivery of a software interrupt, privileged software 
— For APIC-access VM exits and for VM exits caused by EPT violations, page-modification log-full events, and 
SPP-related events encountered during delivery of a so ftware interrupt, privileged software exception, or 
software exception.2
— For VM exits due executions of VMFUNC that  fail because one of the following is true:
•EAX indicates a VM function that is not enabled (the bi t at position EAX is 0 in the VM-function controls; 
see Section 26.5.6.2).
•EAX = 0 and either ECX ≥ 512 or the value of ECX selects an invalid tentative EPTP value (see Section 
26.5.6.3).
In all the above cases, this field receives the length in bytes (1–15) of the instruction (including any instruction 
prefixes) whose execution led to the VM exit (see the next paragraph for one exception).
The cases of VM exits encountered during delivery of a software interrupt, privileged software exception, or 
software exception include those encountered during delivery of events injected as part of VM entry (see 
Section 27.6.1.2). If the original event was injected as pa rt of VM entry, this field receives the value of the VM-
entry instruction length.
All VM exits other than those listed in the above items leave this field undefined.
1. This item applies only to faul t-like VM exits. It does  not apply to trap-like VM exits followi ng executions of the MOV to CR8 i nstruc-
tion when the “use TPR sh adow” VM-execution control is 1 or to those following executions of the WRMSR instruction when the 
“virtualize x2APIC mode” VM-execution control is 1.
2. The VM-exit instruction-length field is not defined following APIC-access VM exits resulting from physic al accesses (see Sect ion 
30.4.6) even if encountered during delivery of a software in terrupt, privileged software exception, or software exception.28-16 Vol. 3CVM EXITS
If the VM exit occurred in enclave mode, this fiel d is cleared (none of the previous items apply).
•VM-exit instruction information . For VM exits due to attempts to execute INS, INVEPT, INVPCID, INVVPID, 
LIDT, LGDT, LLDT, LOADIWKEY, LTR, OUTS, RDRAND, RDSEED, SIDT, SGDT, SLDT, STR, TPAUSE, UMWAIT, 
VMCLEAR, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXON, XRSTORS, or XSAVES, this field receives information about the instruction that caused the VM exit. The format of the field depends on the identity of the 
instruction causing the VM exit:
— For VM exits due to attempts to execute INS or OU TS, the field has the format is given in Table 28-8.
1
— For VM exits due to attempts to execute INVEPT, INVPCID, or INVVPID, the field has the format is given in 
Table 28-9.
— For VM exits due to attempts to execute LIDT, LGDT, SIDT, or SGDT, the field has the format is given in 
Table 28-10.
— For VM exits due to attempts to execute LLDT, LTR, SLDT, or STR, the field has the format is given in 
Table 28-11.
— For VM exits due to attempts to execute RDRAND or RDSEED, the field has the format is given in 
Table 28-12.
— For VM exits due to attempts to execute TPAUSE or UMWAIT, the field has the format is given in 
Table 28-13.
— For VM exits due to attempts to execute VMCLEAR,  VMPTRLD, VMPTRST, VMXON, XRSTORS, or XSAVES, 
the field has the format is given in Table 28-14.
— For VM exits due to attempts to execute VMREAD or  VMWRITE, the field has the format is given in 
Table 28-15.
— For VM exits due to attempts to execute LOADIWKEY,  the field has the format is given in Table 28-16.
For all other VM exits, the field is undefined, unless the VM exit occurred in enclave mode, in which case the

For all other VM exits, the field is undefined, unless the VM exit occurred in enclave mode, in which case the 
field is cleared.Table 28-8.  Format of the VM -Exit Instruction-Information Field as Used for INS and OUTS
6:0 Undefined.9:7 Address size:
0: 16-bit
1: 32-bit
2: 64-bit (used only on processors  that support Inte l 64 architecture)
Other values not used.
14:10 Undefined.17:15 Segment register:
0: ES
1: CS2: SS
3: DS
4: FS
5: GS
Other values not used. Undefined for VM exits due to execution of INS.
31:18 Undefined.
1. The format of the field was undefined for these VM exits on the first processors to support the virtual-machine extensions. So ft-
ware can determine whether the format specified in Table 28-8 is  used by consulting the VMX capability MSR IA32_VMX_BASIC 
(see Appendix A.1).Vol. 3C 28-17VM EXITS
•I/O RCX, I/O RSI, I/O RDI, I/O RIP . These fields are undefined except for SMM VM exits due to system-
management interrupts (SMIs) that arrive immediatel y after retirement of I/O instructions. See Section 
32.15.2.3. Note that, if the VM exit occurred in enclave mode, these fields are all cleared.
Table 28-9.  Format of the VM-Exit Instruction-Information Field as Used for INVEPT, INVPCID, and INVVPID
1:0 Scaling:
0: no scaling
1: scale by 2
2: scale by 4
3: scale by 8 (used only on processors  that support Intel 64 architecture)
Undefined for instructions with no index register (bit 22 is set).
6:2 Undefined.9:7 Address size:
0: 16-bit
1: 32-bit
10 Cleared to 0.14:11 Undefined.17:15 Segment register:
0: ES
1: CS
2: SS3: DS
4: FS
5: GS
21:18 IndexReg:
0=  R A X
1=  R C X2=  R D X
3=  R B X
4=  R S P5=  R B P
6=  R S I
7=  R D I8–15 represent R8–R15, respectively (used only on  processors that suppor t Intel 64 architecture)
22 IndexReg invalid (0 = valid; 1 = invalid)
26:23 BaseReg (encoded as IndexReg above)
Undefined for memory instructions with  no base register (bit 27 is set).
27 BaseReg invalid (0 = valid; 1 = invalid)31:28 Reg2 (same encoding as IndexReg above)28-18 Vol. 3CVM EXITS
Table 28-10.  Format of the VM-Exi t Instruction-Information Field as Used for LIDT, LGDT, SIDT, or SGDT
2: scale by 43: scale by 8 (used only on processo rs that support Intel 64 architecture)
0: 16-bit
1: 32-bit
2: 64-bit (used only on processors that support Intel 64 architecture)
10 Cleared to 0.11 Operand size:
0: 16-bit
1: 32-bit
Undefined for VM exits from 64-bit mode.
14:12 Undefined.17:15 Segment register:
0: ES
1: CS2: SS
3: DS
4: FS5: GS
0=  R A X
1=  R C X
2=  R D X
5=  R B P
22 IndexReg invalid (0 = valid; 1 = invalid)26:23 BaseReg (encoded as IndexReg above)
Undefined for instructions with no  base register (bit 27 is set).
27 BaseReg invalid (0 = valid; 1 = invalid)29:28 Instruction identity:
0: SGDT
1: SIDT2: LGDT
3: LIDTVol. 3C 28-19VM EXITS
31:30 Undefined.
Table 28-11.  Format of the VM-Exi t Instruction-Informatio n Field as Used for LLDT, LTR, SLDT, and STR
1: scale by 22: scale by 4
Undefined for register instructions (bit 10 is set) and for me mory instructions with no in dex register (bit 10 is clear 
and bit 22 is set).
2 Undefined.
6:3 Reg1:
0=  R A X
1=  R C X
2=  R D X
5=  R B P
Undefined for memory instructions (bit 10 is clear).
9:7 Address size:
0: 16-bit
1: 32-bit
Other values not used. Undefined for register instructions (bit 10 is set).
10 Mem/Reg (0 = memory; 1 = register).14:11 Undefined.17:15 Segment register:
0: ES
1: CS2: SS
3: DS
4: FS5: GS
21:18 IndexReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set).
26:23 BaseReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no base register (bit 10 is clear 
and bit 27 is set).Table 28-10.  Format of the VM-Exit Instruction-Information Field as Used for LIDT, LGDT, SIDT, or SGDT (Contd.)
Bit Position(s) Content28-20 Vol. 3CVM EXITS
27 BaseReg invalid (0 = valid; 1 = invalid)
29:28 Instruction identity:
0: SLDT
1: STR2: LLDT
3: LTR
Table 28-12.  Format of the VM-Exit Instruction- Information Field as Used for RDRAND and RDSEED
2:0 Undefined.6:3 Operand register (destination register):
0=  R A X
3=  R B X
6=  R S I
10:7 Undefined.12:11 Operand size:
0: 16-bit
1: 32-bit2: 64-bit
The value 3 is not used.
31:13 Undefined.
Table 28-13.  Format of the VM-Exit Instruction-Information Field as Used for TPAUSE and UMWAIT
Bit Position(s) Content2:0 Undefined.6:3 Operand register (source register):
0=  R A X
3=  R B X
6=  R S I
31:7 Undefined.Table 28-11.  Format of the VM-Exit Instruction-Information Field as Used for LLDT, LTR, SLDT, and STR (Contd.)
Bit Position(s) ContentVol. 3C 28-21VM EXITS
 
28.3 SAVING GUEST STATE
VM exits save certain components of processor state into corresponding fields in the guest-state area of the VMCS 
(see Section 25.4). On processors that support Intel 64 arch itecture, the full value of each natural-width field (see 
Section 25.11.2) is saved regardless of the mode of the logical processor before and after the VM exit.Table 28-14.  Format of the VM-Exi t Instruction-Information Field as Used for VMCLEAR, VMPTRLD, VMPTRST, 
VMXON, XRSTORS, and XSAVES
2: scale by 43: scale by 8 (used only on processors  that support Inte l 64 architecture)
0: 16-bit
1: 32-bit
0: ES
1: CS2: SS
3: DS
4: FS5: GS
0=  R A X
1=  R C X
2=  R D X
5=  R B P
27 BaseReg invalid (0 = valid; 1 = invalid)31:28 Undefined.28-22 Vol. 3CVM EXITS
In general, the state saved is that which was in the logical processor at the time the VM exit commences. See 
Section 28.1 for a discussion of which architectural updates occur at that time.Table 28-15.  Format of the VM-Exit Instruction- Information Field as Used  for VMREAD and VMWRITE
2: scale by 43: scale by 8 (used only on processors  that support Intel 64 architecture)
Undefined for register instructions (bit 10 is set) and for memory instructions with no index register (bit 10 is clear 
2 Undefined.6:3 Reg1:
0=  R A X
1=  R C X
4=  R S P
5=  R B P
6=  R S I
0: 16-bit
1: 32-bit
0: ES
1: CS
2: SS3: DS
4: FS
5: GS

0=  R A X
1=  R C X
4=  R S P
5=  R B P
6=  R S I
0: 16-bit
1: 32-bit
0: ES
1: CS
2: SS3: DS
4: FS
5: GS
Undefined for register instructions (bit 10 is set) and for me mory instructions with no ba se register (bit 10 is clear 
and bit 27 is set).
31:28 Reg2 (same encoding as Reg1 above)Vol. 3C 28-23VM EXITS
Section 28.3.1 through Section 28.3.4 provide details for how various components of processor state are saved. 
These sections reference VMCS fields that correspond to  processor state. Unless otherwise stated, these refer-
28.3.1 Saving Control Registers, Debug Registers, and MSRs
Contents of certain control registers, debug registers, and MSRs are saved as follows:
•The contents of CR0, CR3, CR4, and the IA32_SYSEN TER_CS, IA32_SYSENTER_ESP, and IA32_SYSENTER_EIP 
MSRs are saved into the corresponding fields. Bits 63:32 of the IA32_SYSENTER_CS MSR are not saved. On 
processors that do not support Intel 64 architec ture, bits 63:32 of the IA32_SYSENTER_ESP and 
IA32_SYSENTER_EIP MSRs are not saved.
•If the “save debug controls” VM-exit control is 1, th e contents of DR7 and the IA32_DEBUGCTL MSR are saved 
into the corresponding fields. The first processors to su pport the virtual-machine extensions supported only the 
1-setting of this control and thus always saved data into these fields.
•If the “save IA32_PAT” VM-exit control is 1, the conten ts of the IA32_PAT MSR are saved into the corresponding 
field.
•If the “save IA32_EFER” VM-exit control is 1, the co ntents of the IA32_EFER MSR are saved into the corre-
sponding field.
•If the processor supports either the 1-setting of the “load IA32_BNDCFGS” VM-entry control or that of the 
“clear IA32_BNDCFGS” VM-exit contro l, the contents of the IA32_BNDCFGS MSR are saved into the corre-
•If the processor supports either the 1-setting of the “load IA32_RTIT_CTL”  VM-entry control or that of the 
“clear IA32_RTIT_CTL” VM-exit control, the contents of the IA32_RTIT_CTL MSR are saved into the corre-
•If the processor supports the 1-setting of the “load CET”  VM-entry control, the contents of the IA32_S_CET and 
IA32_INTERRUPT_SSP_TABLE_ADDR MSRs are saved into the corresponding fields. On processors that do not 
support Intel 64 architecture, bits 63:32 of these MSRs are not saved.
•If the processor supports either the 1-setting of the “loa d guest IA32_LBR_CTL” VM-entry control or that of the 
“clear IA32_LBR_CTL” VM-exit control, the contents of the IA32_LBR_CTL MSR are saved into the corre-
•If the processor supports the 1-setting of the “load PK RS” VM-entry control, the contents of the IA32_PKRS 
MSR are saved into the corresponding field.
•If a processor supports user interrupts, every VM exit  saves UINV into the guest UINV field in the VMCS 
(bits 15:8 of the field are cleared).
•If the “save IA32_PERF_GLOBAL_CTL” VM-exit control is  1, the contents of the IA32_PERF_GLOBAL_CTL MSR 
are saved into the corresponding field.
•The value of the SMBASE field is undefined after a ll VM exits except SMM VM exits. See Section 32.15.2.
28.3.2 Saving Segment Registers and Descriptor-Table Registers
For each segment register (CS, SS, DS, ES, FS, GS, LDTR, or TR), the values saved for the base-address, segment-
limit, and access rights are based on whether the regist er was unusable (see Section 25.4.1) before the VM exit:Table 28-16.  Format of the VM-Exit Instruction-Information Field as Used for LOADIWKEY
2:0 Undefined.6:3 Reg1: identifies the first XMM register operand (XMM0–XMM15; values 8–15 are used only on processors that 
support Intel 64 architecture).
30:7 Undefined.31:28 Reg2: identifies the second XMM register operand (see above).28-24 Vol. 3CVM EXITS
•If the register was unusable, the values saved into the following fields are undefined: (1) base address; 
(2) segment limit; and (3) bits 7:0 and bits 15:12 in the access-rights field. The following exceptions apply:
—C S .
•The base-address and segment-limit fields are saved.
•The L, D, and G bits are saved in the access-rights field.
—S S .
•DPL is saved in the access-rights field.
•On processors that support Intel 64 architecture, bi ts 63:32 of the value saved for the base address are 
always zero.
— DS and ES. On processors that support Intel 64 arch itecture, bits 63:32 of the values saved for the base 
addresses are always zero.
— FS and GS. The base-address field is saved.— LDTR. The value saved for the base address is always canonical.
•If the register was not unusable, the values saved into the following fields are those which were in the register 
before the VM exit: (1) base address; (2) segment limit; and (3) bits 7:0 and bits 15:12 in access rights.
•Bits 31:17 and 11:8 in the access-rights field are always cl eared. Bit 16 is set to 1 if and only if the segment is 
unusable.
The contents of the GDTR and IDTR registers are saved into the corresponding base-address and limit fields.
28.3.3 Saving RIP, RSP, RFLAGS, and SSP
The contents of the RIP, RSP, RFLAGS, and SSP (shadow-stack pointer) registers are saved as follows:
•The value saved in the RIP field is determined by the nature and cause of the VM exit:
— If the VM exit occurred in enclave mode, the value saved is the AEP of  interrupted enclave thread (the 
remaining items do not apply).
— If the VM exit occurs due to by an attempt to execute an instruction that causes VM exits unconditionally or 
that has been configured to cause a VM exit via the VM-execution controls, the value saved references that 
— If the VM exit is caused by an occurrence of an IN IT signal, a start-up IPI (SIPI), or system-management 
interrupt (SMI), the value saved is that which was in RIP before the event occurred.
— If the VM exit occurs due to the 1-setting of either the “interrupt-window exiting” VM-execution control or 
the “NMI-window exiting” VM-execution  control, the value saved is that which would be in the register had 
the VM exit not occurred.
— If the VM exit is due to an external interrupt, non- maskable interrupt (NMI), or hardware exception (as 
defined in Section 28.2.2), the value saved is the retu rn pointer that would have been saved (either on the 
stack had the event been delivered through a trap or interrupt gate,1 or into the old task-state segment had 
the event been delivered through a task gate).
— If the VM exit is due to a triple fault, the value sa ved is the return pointer that would have been saved 
(either on the stack had the event been delivered through a trap or interrupt gate, or into the old task-state 
segment had the event been delivered through a ta sk gate) had delivery of the double fault not 
encountered the nested exception that caused the triple fault.
— If the VM exit is due to a software exception (due to an execution of INT3 or INTO) or a privileged software 
exception (due to an execution of INT1), the value saved references the INT3, INTO, or INT1 instruction 
that caused that exception.
1. The reference here is to the full value of RIP before any trun cation that would occur had the stack width been only 32 bits o r 16 
bits.Vol. 3C 28-25VM EXITS
— Suppose that the VM exit is due to a task switch that  was caused by execution of CALL, IRET, or JMP or by 
execution of a software interrupt (INT n), software exception (due to execution of INT3 or INTO), or 
privileged software exception (due to execution of INT1 ) that encountered a task gate in the IDT. The value 
saved references the instruction that caused the task switch (CALL, IRET, JMP, INT n, INT3, INTO, INT1).
— Suppose that the VM exit is due to a task switch that was caused by a task gate in the IDT that was 
encountered for any reason except the direct access by a software interrupt or software exception. The 
value saved is that which would have been saved in  the old task-state segment had the task switch 
completed normally.
— If the VM exit is due to an execution of MOV to CR8 or WRMSR that reduced the value of bits 7:4 of VTPR 
(see Section 30.1.1) below that of TPR threshold VM-exe cution control field (see Section 30.1.2), the value 
saved references the instruction fo llowing the MOV to CR8 or WRMSR.
— If the VM exit was caused by APIC-write emulation (see Section 30.4.3.2) that results from an APIC access 
as part of instruction execution, the value saved references the instruction following the one whose 
execution caused the APIC-write emulation.
•The contents of the RSP register are saved into the RSP field.
•With the exception of the resume flag (RF; bit 16), th e contents of the RFLAGS register is saved into the 
RFLAGS field. RFLAGS.RF is saved as follows:
— If the VM exit occurred in enclave mode, the value saved is 0 (the remaining items do not apply).

— If the VM exit is caused directly by an event that would normally be delivered through the IDT, the value 
saved is that which would appear in the saved RFLA GS image (either that which would be saved on the 
stack had the event been delivered through a trap or interrupt gate1 or into the old task-state segment had 
the event been delivered through a task gate) had the event been delivered through the IDT. See below for 
VM exits due to task switches caused by task gates in the IDT.
— If the VM exit is caused by a triple fault, the value saved is that which the logical processor would have in 
RF in the RFLAGS register had the triple fault taken the logical processor to the shutdown state.
— If the VM exit is caused by a task switch (including one caused by a task gate in the IDT), the value saved 
is that which would have been saved in the RFLAGS image in the old task-state segment (TSS) had the task 
switch completed normally without exception.
— If the VM exit is caused by an attempt to execute an instruction that unconditionally causes VM exits or one 
that was configured to do with a VM-execution control, the value saved is 0.2
— For APIC-access VM exits and for VM exits caused by EPT violations, EPT misconfigurations, page-modifi-
cation log-full events, or SPP-related events, the value saved depends on whether the VM exit occurred 
during delivery of an event through the IDT:
•If the VM exit stored 0 for bit 31 for IDT-vectoring information field (because the VM exit did not occur 
during delivery of an event through the IDT; see Section 28.2.4), the value saved is 1.
•If the VM exit stored 1 for bit 31 for IDT-vectorin g information field (because the VM exit did occur 
during delivery of an event through the IDT), the va lue saved is the value that would have appeared in 
the saved RFLAGS image had the event been delivered through the IDT (see above).
— For all other VM exits, the value saved is the value RFLAGS.RF had before the VM exit occurred.
•If the processor supports the 1-setting of the “load CET” VM-entry control, the contents of the SSP register are 
saved into the SSP field.
1. The reference here is to the full value of RFLAGS before any tr uncation that would occur had the stack width been only 32 bit s or 
16 bits.
2. This is true even if RFLAGS.RF was 1 before the instruction wa s executed. If, in response to such a VM exit, a VM monitor re-en ters 
the guest to re-execute the instruction that caused the VM exit (for example, after clearing the VM-execution control that cause d 
the VM exit), the instruction may encounter a code breakpoint that  has already been processed. A VM monitor can avoid this by set -
ting the guest value of RFLAGS.RF to  1 before resuming guest software.28-26 Vol. 3CVM EXITS
28.3.4 Saving Non-Register State
Information corresponding to guest non-register state is saved as follows:
•The activity-state field is saved with the logical processor’s activity state before the VM exit.1 See Section 28.1 
for details of how events leading to a VM exit may affect the activity state. If the VM exit occurred during user-
interrupt notification processing (see Section 7.5.2) and the logical processor would have entered the HLT state following user-interrupt notification processing, the saved activity state is “HLT”.
•The interruptibility-state field is saved to reflect the logical processor’s interruptibility before the VM exit.
— See Section 28.1 for details of how events leading to a VM exit may affect this state.
— VM exits that end outside system-management mode (S MM) save bit 2 (blocking by SMI) as 0 regardless 
of the state of such blocking before the VM exit.
— Bit 3 (blocking by NMI) is treated specially if the “virtu al NMIs” VM-execution control is 1. In this case, the 
value saved for this field does not indicate the blocking  of NMIs but rather the state of virtual-NMI blocking.
— Bit 4 (enclave interruption) is set to 1 if the VM ex it occurred while the logical processor was in enclave 
mode.
Such VM exits includes those caused by interrupt s, non-maskable interrupts, system-management 
A VM exit that is incident to delivery of an even t injected by VM entry leaves this bit unmodified.
•The pending debug exceptions field is saved as clear for all VM exits except the following:
— A VM exit caused by an INIT signal, a machine-chec k exception, or a system-management interrupt (SMI).
— A VM exit with basic exit reason “TPR below threshold”,2 “virtualized EOI”, “APIC write”, “monitor trap flag,” 
or “bus-lock detected.”
— A VM exit due to trace-address pre-translation (TAPT;  see Section 26.5.4) or due to accesses related to 
PEBS on processors with the “EPT-friendly” enhanc ement (see Section 20.9.5). Such VM exits can have 
basic exit reason “APIC access,” “EPT violation,” “EPT  misconfiguration,” “page-modification log full,” or 
“SPP-related event.” When due to TAPT or PEBS, thes e VM exits (with the exception of those due to EPT 
misconfigurations) set bit 16 of the exit qualification, indicating that they are asynchronous to instruction 
execution and not part of event delivery.
— VM exits that are not caused by debug exceptions and that occur while there is MOV-SS blocking of debug 
For VM exits that do not clear the field, the value saved is determined as follows:
— Each of bits 3:0 may be set if it corresponds to a ma tched breakpoint. This may be true even if the corre-
sponding breakpoint is not enabled in DR7.
— Suppose that a VM exit is due to an INIT signal, a ma chine-check exception, or an SMI; or that a VM exit 
has basic exit reason “TPR below threshold” or “monitor  trap flag.” In this case, the value saved sets bits 
corresponding to the causes of any debug exceptions  that were pending at the time of the VM exit.
If the VM exit occurs immediately after VM entry, the value saved may match that which was loaded on 
VM entry (see Section 27.7.3). Otherwise, the following items apply:
•Bit 12 (enabled breakpoint) is set to 1 in any of the following cases:
— If there was at least one matched data or I/O breakpoint that was enabled in DR7.— If it had been set on VM entry, causing there to be valid pending debug exceptions (see Section 
27.7.3) and the VM exit occurred before those exceptions were either delivered or lost.
— If the XBEGIN instruction was executed immediatel y before the VM exit and advanced debugging of 
RTM transactional regions had been enabled (see Section 16.3.7, “RTM-Enabled Debugger 
1. If this activity state was an inactive state resulting from execution of a specific  instruction (HLT or MWAIT), the value sav ed for RIP 
by that VM exit will referenc e the following instruction.
2. This item includes VM exits that occur as a result of certain VM entries (Section 27.7.7).Vol. 3C 28-27VM EXITS
Support,” of Intel® 64 and IA-32 Architectures Software De veloper’s Manual, Volume 1). (This does 
not apply to VM exits with basic exit reason “monitor trap flag.”)
— If a bus lock was asserted while CPL > 0 and OS bus-lock detection was enabled.
In other cases, bit 12 is cleared to 0.
•Bit 14 (BS) is set if RFLAGS.TF = 1 in either of the following cases:
— IA32_DEBUGCTL.BTF = 0 and the cause of a pending debug exception was the execution of a single 
— IA32_DEBUGCTL.BTF = 1 and the cause of a pe nding debug exception was a taken branch.
•Bit 16 (RTM) is set if a debug exception (#DB) or a breakpoint exception (#BP) occurred inside an RTM 
region while advanced debugging of RTM transactiona l regions had been enabled. (This does not apply 
to VM exits with basic exit reason “monitor trap flag.”)
— Suppose that a VM exit is due to an other reason (but not a debug exception) and occurs while there is MOV-
SS blocking of debug exceptions. In this case, the valu e saved sets bits corresponding to the causes of any 
debug exceptions that were pending at the time of the VM exit. If the VM exit occurs immediately after 
VM entry (no instructions were executed in VMX no n-root operation), the value saved may match that 
which was loaded on VM entry (see Section 27.7.3). Otherwise, the following items apply:
•Bit 12 (enabled breakpoint) is set to 1 if there was at  least one matched data or I/O breakpoint that was 
enabled in DR7. Bit 12 is also set if it had been se t on VM entry, causing there to be valid pending debug 
exceptions (see Section 27.7.3) and the VM exit occurred before those exceptions were either delivered 
or lost. In other cases, bit 12 is cleared to 0.
•The setting of bit 14 (BS) is implementation-speci fic. However, it is not set if RFLAGS.TF = 0 or 
IA32_DEBUGCTL.BTF = 1.
— The reserved bits in the field are cleared.
•If the “save VMX-preemption timer value” VM-exit cont rol is 1, the value of timer is saved into the VMX-

preemption timer-value field. This is the value loaded from this field on VM entry as subsequently decremented 
(see Section 26.5.1). VM exits due to timer expiration sa ve the value 0. Other VM exits may also save the value 
0 if the timer expired during VM exit. (If the “save VMX-preemption timer value” VM-exit control is 0, VM exit 
does not modify the value of the VMX-preemption timer-value field.)
•If the logical processor supports the 1-setting of the “ena ble EPT” VM-execution control, values are saved into 
the four (4) PDPTE fields as follows:
— If the “enable EPT” VM-execution control is 1 and the logical processor was using PAE paging at the time of 
the VM exit, the PDPTE values currently in use are saved:1
•The values saved into bits 11:9 of each of the fields is undefined.
•If the value saved into one of the fields has bit 0 (p resent) clear, the value saved into bits 63:1 of that 
field is undefined. That value need not correspond to  the value that was loaded by VM entry or to any 
value that might have been loaded in VMX non-root operation.
•If the value saved into one of the fields has bit 0 (present) set, the value saved into bits 63:12 of the 
field is a guest-physical address.
— If the “enable EPT” VM-execution control is 0 or the logical processor was not using PAE paging at the time 
of the VM exit, the values saved are undefined.
Architectures Software Developer’s Manual, Volume 3A. “Enable EPT”  is a secondary processor-based VM-execution control. If bit 3 1 
of the primary processor-based VM-execution controls is 0, VM exit  functions as if the “enable EP T” VM-execution control were 0.  
See Section 25.6.2.28-28 Vol. 3CVM EXITS
28.4 SAVING MSRS
After processor state is saved to the guest-state area, va lues of MSRs may be stored into the VM-exit MSR-store 
area (see Section 25.7.2). Specifically each entry in that area (up to the number specified in the VM-exit MSR-store 
count) is processed in order by storing the value of the MSR indexed by bits 31:0 (as they would be read by 
RDMSR) into bits 127:64. Processing of an en try fails in either of the following cases:
•The value of bits 31:0 indicates an MSR that can be read only in system-management mode (SMM) and the 
VM exit will not end in SMM. (IA32_SMBASE is  an MSR that can be read only in SMM.)
•The value of bits 31:0 indicates an MSR that cannot be saved on VM exits for model-specific reasons. A 
processor may prevent certain MSRs (based on the value of bits 31:0) from being stored on VM exits, even if 
they can normally be read by RDMSR. Such model-spec ific behavior is documented in Chapter 2, “Model-
Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 4.
•Bits 63:32 of the entry are not all 0.
•An attempt to read the MSR indexed by bits 31:0 would cause a general-protection exception if executed via 
RDMSR with CPL = 0.
A VMX abort occurs if processing fails for any entry. See Section 28.7.
28.5 LOADING HOST STATE
Processor state is updated on VM exits in the following ways:
•Some state is loaded from or otherwise determ ined by the contents of the host-state area.
•Some state is determined by VM-exit controls.
•Some state is established in the same way on every VM exit.
This loading may be performed in any order.
On processors that support Intel 64 architecture, the full values of each 64-bit field loaded (for example, the base 
address for GDTR) is loaded regardless of the mode of the logical processor before and after the VM exit.
The loading of host state is detailed in Section 28.5.1 to Section 28.5.5. These sections reference VMCS fields that 
correspond to processor state. Unless otherwise stated, these references are to fields in the host-state area.
A logical processor is in IA-32e mode after a VM exit only if  the “host address-space size” VM-exit control is 1. If the 
logical processor was in IA-32e mode before the VM exit and this control is 0, a VMX abort occurs. See Section 
28.7.
In addition to loading host state, VM exits cl ear address-range monitoring (Section 28.5.6).
After the state loading described in this section, VM ex its may load MSRs from the VM-exit MSR-load area (see 
Section 28.6). This loading occurs only after the state loading described in this section.
28.5.1 Loading Host Control Registers, Debug Registers, MSRs
VM exits load new values for controls registers, debug registers, and some MSRs:
•CR0, CR3, and CR4 are loaded from the CR0 field, the CR3 field, and the CR4 field, respectively, with the 
— The following bits are not modified:
•For CR0, ET, CD, NW; bits 63:32 (on processors th at support Intel 64 architecture), 28:19, 17, and 
15:6; and any bits that are fixed in VMX operation (see Section 24.8).1
•For CR3, bits 63:52 and bits in the range 51:32 beyond the processor’s physical-address width (they 
are cleared to 0).2 (This item applies only to processors that support Intel 64 architecture.)Vol. 3C 28-29VM EXITS
•For CR4, any bits that are fixed in VMX operation (see Section 24.8).
— CR4.PAE is set to 1 if the “host address-space size” VM-exit control is 1.
— CR4.PCIDE is set to 0 if the “host address-space size” VM-exit control is 0.
•DR7 is set to 400H.
•If the “clear UINV” VM-exit control is 1, VM exit clears UINV.
•The following MSRs are established as follows:— The IA32_DEBUGCTL MSR is cleared to 00000000_00000000H.
— The IA32_SYSENTER_CS MSR is loaded from the IA32_SYSENTER_CS field. Since that field has only 32 
bits, bits 63:32 of the MSR are cleared to 0. 
— The IA32_SYSENTER_ESP and IA32_SYSENTER_EIP MSRs are loaded from the IA32_SYSENTER_ESP and 
IA32_SYSENTER_EIP fields, respectively.
If the processor does not support the Intel 64 architectu re, these fields have only 32 bits; bits 63:32 of the 
MSRs are cleared to 0.
If the processor supports the Intel 64  architecture with N < 64 linear-address bits, each of bits 63:N is set 
to the value of bit N–1.
1
— The following steps are performed on processors that support Intel 64 architecture:
(see Section 28.5.2).
•The LMA and LME bits in the IA32_EFER MSR are each  loaded with the setting of the “host address-
— If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, the IA32_PERF_GLOBAL_CTRL MSR is loaded 
from the IA32_PERF_GLOBAL_CTRL field. Bits that ar e reserved in that MSR are maintained with their 
reserved values.
— If the “load IA32_PAT” VM-exit control is 1, the IA32_PAT MSR is loaded from the IA32_PAT field. Bits that 
are reserved in that MSR are maintained with their reserved values.
— If the “load IA32_EFER” VM-exit control is 1, the IA32 _EFER MSR is loaded from the IA32_EFER field. Bits 
that are reserved in that MSR are maintained with their reserved values.
— If the “clear IA32_BNDCFGS” VM-exit control is 1, the IA32_BNDCFGS MSR is cleared to 
00000000_00000000H; otherwise, it is not modified.
— If the “clear IA32_RTIT_CTL” VM-exit control is 1, the IA32_RTIT_CTL MSR is cleared to 
— If the “load CET” VM-exit control is 1, the IA3 2_S_CET and IA32_INTERRUPT_SSP_TABLE_ADDR MSRs are 
loaded from the IA32_S_CET and IA32_INTE RRUPT_SSP_TABLE_ADDR fields, respectively.
— If the “load PKRS” VM-exit control is 1, the IA32_PKRS MSR is loaded from the IA32_PKRS field. Bits 63:32 
of that MSR are maintained with zeroes.
With the exception of FS.base and GS.base, any of these MSRs is subsequently overwritten if it appears in the 
VM-exit MSR-load area. See Section 28.6.
1. Bits 28:19, 17, and 15:6 of CR0 and CR0.ET are unchanged by exec utions of MOV to CR0. CR0.ET is always 1 and the other bits a re 
always 0.
width is returned in  bits 7:0 of EAX.
1. Software can determine the number N by executing CPUID with 80000008H in EAX. The number of linear-address bits supported is 
returned in bits  15:8 of EAX.28-30 Vol. 3CVM EXITS
28.5.2 Loading Host Segment and Descriptor-Table Registers
Each of the registers CS, SS, DS, ES, FS, GS, and TR is loaded as follows (see below for the treatment of LDTR):

always 0.
•The selector is loaded from the selector field. The segm ent is unusable if its selector is loaded with zero. The 
checks specified in Section 27.2.3 limit the selector va lues that may be loaded. In particular, CS and TR are 
never loaded with zero and are thus never unusable. SS  can be loaded with zero only on processors that 
support Intel 64 architecture and only  if the VM exit is to 64-bit mode (64-bit mode allows use of segments 
marked unusable).
•The base address is set as follows:
— CS. Cleared to zero.
— SS, DS, and ES. Undefined if the segment is unusable; otherwise, cleared to zero.— FS and GS. Undefined (but, on processors that support Intel 64 architecture, canonical) if the segment is 
unusable and the VM exit is not to 64-bit mode; otherwise, loaded from the base-address field.
If the processor supports the Intel 64 architecture and the processor supports N < 64 linear-address bits, 
each of bits 63:N is set to the value of bit N–1.
1 The values loaded for base addresses for FS and GS are 
also manifest in the FS.base and GS.base MSRs.
— TR. Loaded from the host-state area. If the proce ssor supports the Intel 64 architecture and the processor 
supports N < 64 linear-address bits, each of bits 63:N is set to the value of bit N–1.
•The segment limit is set as follows:
— CS. Set to FFFFFFFFH (corresponding to a descriptor limit of FFFFFH and a G-bit setting of 1).
— SS, DS, ES, FS, and GS. Undefined if the se gment is unusable; otherwise, set to FFFFFFFFH.
— TR. Set to 00000067H.
•The type field and S bit are set as follows:
— CS. Type set to 11 and S set to 1 (execute/read, accessed, non-conforming code segment).
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, type set to 3 and S set to 1 
(read/write, accessed, expand-up data segment).
— TR. Type set to 11 and S set to 0 (busy 32-bit task-state segment).
•The DPL is set as follows:— CS, SS, and TR. Set to 0. The current privilege level (CPL) will be 0 after the VM exit completes.
— DS, ES, FS, and GS. Undefined if the se gment is unusable; otherwise, set to 0.
•The P bit is set as follows:
— CS, TR. Set to 1.— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 1.
•On processors that support Intel 64 architecture, CS.L is loaded with the setting of the “host address-space 
size” VM-exit control. Because the value of this control is also loaded into IA32_EFER.LMA (see Section 28.5.1), 
no VM exit is ever to compatibility mode (w hich requires IA32_EFER.LMA = 1 and CS.L = 0).
•D/B.
— CS. Loaded with the inverse of the setting of the “hos t address-space size” VM-exit control. For example, if 
that control is 0, indicating a 32-bit guest, CS.D/B is set to 1.
— SS. Set to 1.— DS, ES, FS, and GS. Undefined if the se gment is unusable; otherwise, set to 1.
— TR. Set to 0.
•G.
returned in bits 15:8 of EAX.Vol. 3C 28-31VM EXITS
— CS. Set to 1.
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 1.
The host-state area does not contain a selector field for LDTR. LDTR is established as follows on all VM exits: the 
selector is cleared to 0000H, the segment is marked u nusable and is otherwise undefined (although the base 
address is always canonical).
The base addresses for GDTR and IDTR are loaded from  the GDTR base-address field and the IDTR base-address 
field, respectively. If the processor supports the Inte l 64 architecture and the processor supports N < 64 linear-
address bits, each of bits 63:N of each base address is se t to the value of bit N–1 of that base address. The GDTR 
and IDTR limits are each set to FFFFH.
28.5.3 Loading Host RIP, RSP, RFLAGS, and SSP
RIP and RSP are loaded from the RIP field and the RSP field,  respectively. RFLAGS is cleared, except bit 1, which is 
always set.
If the “load CET” VM-exit control is 1, SSP (sha dow-stack pointer) is loaded from the SSP field.
28.5.4 Checking and Loading Host Page-Directory-Pointer-Table Entries
If CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LMA = 0, the logical processor uses PAE paging . See Section 4.4 of 
the Intel® 64 and IA-32 Architectures Software  Developer’s Manual, Volume 3A.1 When in PAE paging is in use, the 
when PAE paging is in use checks the validity of the PDPT Es and, if they are valid, loads them into the processor 
(into internal, non-architectural registers).
A VM exit is to a VMM that uses PAE paging if (1) bit 5 (c orresponding to CR4.PAE) is set in the CR4 field in the 
host-state area of the VMCS; and (2) the “host address-sp ace size” VM-exit control is 0. Such a VM exit may check 
the validity of the PDPTEs referenced by the CR3 field in  the host-state area of the VMCS. Such a VM exit must 
check their validity if either (1) PAE paging was not in use before the VM exit; or (2) the value of CR3 is changing 
as a result of the VM exit. A VM exit to a VMM that does  not use PAE paging must not check the validity of the 
PDPTEs.
A VM exit that checks the validity of the PDPTEs uses th e same checks that are used when CR3 is loaded with 
MOV to CR3 when PAE paging is in use. If MOV to CR3 would cause a general-protection exception due to the 
PDPTEs that would be loaded (e.g., because a reserved bit is set), a VMX abort occurs (see Section 28.7). If a 
VM exit to a VMM that uses PAE does not cause a VMX abort, the PDPTEs are loaded into the processor as would 
MOV to CR3, using the value of CR3 being load by the VM exit.
28.5.5 Updating Non-Register State
VM exits affect the non-register state of a logical processor as follows:
•A logical processor is always in the active state after a VM exit.
•Event blocking is affected as follows:
— There is no blocking by STI or by MOV SS after a VM exit.
— VM exits caused directly by non-maskable interrupts (N MIs) cause blocking by NMI (see Table 25-3). Other 
VM exits do not affect blocking by NMI. (See Section 28.1 for the case in which an NMI causes a VM exit 
indirectly.)
•There are no pending debug exceptions after a VM exit.
Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address width is returned in  bits 7:0 of EAX.28-32 Vol. 3CVM EXITS
and paging-structure caches. The following items detail how VM exits invalidate cached mappings:
•VM exits are not required to invalidate any guest-physical  mappings, nor are they required to invalidate any 
linear mappings or combined mappings if the “enable VPID” VM-execution control is 1. 
28.5.6 Clearing Address-Range Monitoring
Volume 3A. VM exits clear any address-range monitoring that may be in effect.
28.6 LOADING MSRS
VM exits may load MSRs from the VM-exit MSR-load area (see  Section 25.7.2). Specifically each entry in that area 
(up to the number specified in the VM-exit MSR-load count ) is processed in order by loading the MSR indexed by 
bits 31:0 with the contents of bits 127:64  as they would be written by WRMSR.
•The value of bits 31:0 is either C0000100H (the IA32_FS_BASE MSR) or C0000101H (the IA32_GS_BASE 
MSR).
VM exit will not end in SMM. (IA32_SMM_MONITOR_CTL is an MSR that can be written only in SMM.)
•The value of bits 31:0 indicates an MSR that cannot be  loaded on VM exits for model-specific reasons. A 
specific behavior is documented in Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 64 and IA-32 
•An attempt to write bits 127:64 to the MSR indexed by bits 31:0 of the entry would cause a general-protection

MSR).
If processing fails for any entry, a VMX abort occurs. See Section 28.7.
that, after VM exit, the logical processor does not use any translations that were cach ed before the transition.
28.7 VMX ABORTS
A problem encountered during a VM exit leads to a VMX abort . A VMX abort takes a logical processor into a shut-
down state as described below.
A VMX abort does not modify the VMCS data in the VMCS re gion of any active VMCS. The contents of these data are 
thus suspect after the VMX abort.
On a VMX abort, a logical processor saves a nonzero 32-bit VMX-abort indicator field at byte offset 4 in the VMCS 
region of the VMCS whose misconfigur ation caused the failure (see Section 25.2). The following values are used:
1. Note the following ab out processors that support Intel 64  architecture. If CR0.PG = 1, WRMSR to the IA32_EFER MSR causes a gen-
eral-protection exception if it would modify the LME bit. Since CR0.PG is always 1 in VMX operation, the IA32_EFER MSR should n ot 
be included in the VM-exit MSR-load area for the purpose of modifying the LME bit.Vol. 3C 28-33VM EXITS
1. There was a failure in saving guest MSRs (see Section 28.4).
2. Host checking of the page-directory-pointer-table entries (PDPTEs) failed (see Section 28.5.4).
3. The current VMCS has been corrupted (through writes to the corresponding VMCS region) in such a way that 
the logical processor cannot complete the VM exit properly.
4. There was a failure on loading host MSRs (see Section 28.6).5. There was a machine-check event during VM exit (see Section 28.8).
6. The logical processor was in IA-32e mode before the VM exit and the “host address-space size” VM-exit control 
was 0 (see Section 28.5).
Some of these causes correspond to failures during the loading of state from the host-state area. Because the 
loading of such state may be done in any order (see Se ction 28.5) a VM exit that might lead to a VMX abort for 
multiple reasons (for example, the current VMCS may be corrupt and the host PDPTEs might not be properly configured). In such cases, the VMX-abort indica tor could correspond to any one of those reasons.
A logical processor never reads the VMX-abort indicator in a VMCS region and writes it only with one of the non-
zero values mentioned above. The VMX-abort indicator allo ws software on one logical processor to diagnose the 
VMX-abort on another. For this reason, it is recommended that software running in VMX root operation zero the 
VMX-abort indicator in the VMCS region of any VMCS that it uses.
After saving the VMX-abort indicator, operation of a logical processor experiencing a VMX abort depends on 
whether the logical processor is in SMX operation:
1
•If the logical processor is in SMX operation, an Intel® TXT shutdown condition occurs. The error code used is 
000DH, indicating “VMX abort.” See the Intel® Trusted Execution Technology Measured Launched Environment 
Programming Guide.
•If the logical processor is outside SMX operation, it issues a special bus cycle (to notify the chipset) and enters the VMX-abort shutdown state . RESET is the only event that wakes a logical processor from the VMX-abort 
shutdown state. The following events do not affect a logical processor in this state: machine-check events; 
INIT signals; external interrupts; non-maskable interrupts (NMIs); start-up IPIs (SIPIs); and system-management interrupts (SMIs).
28.8 MACHINE-CHECK EVENTS DURING VM EXIT
If a machine-check event occurs during  VM exit, one of the following occurs:
•The machine-check event is handled as if it occurred before the VM exit:
— If CR4.MCE = 1, a machine-check exception (#MC) is generated:
•The machine-check event is handled after VM exit completes:
— If the VM exit ends with CR4.MCE = 0, operation of the logical processor depends on whether the logical 
execution of GETSEC[SENTER]. See Chapter 7, “Safer Mode Extensions Reference‚” in Intel® 64 and IA-32 Architectures Software 
Developer’s Manu al, Volume 2D.28-34 Vol. 3CVM EXITS
— If the VM exit ends with CR4.MCE = 1, a machine-chec k exception (#MC) is delivered through the host IDT.
•A VMX abort is generated (see Section 28.7). The logi cal processor blocks events as done normally in 
VMX abort. The VMX abort indicator is 5, for “machine-check event during VM exit.”
The first option is not used if the machine-check event occurs after any host state has been loaded. The second 
option is used only if VM entry is able to load all host state.
28.9 USER-INTERRUPT RE COGNITION AFTER VM EXIT
A VM exit results in recognition of a pending user inte rrupt if it completes with CR4.UINTR = IA32_EFER.LMA = 1 
and with UIRR ≠ 0; otherwise, no pending us er interrupt is recognized.Vol. 3C 29-1CHAPTER 29
The architecture for VMX operation includes two features that support address translation: virtual-processor iden-
tifiers (VPIDs) and the extended page-table mechanism (E PT). VPIDs are a mechanism for managing translations 
of linear addresses. EPT defines a laye r of address translation that augments  the translation of linear addresses.
Section 29.1 details the architecture of VPIDs. Section 29.3  provides the details of EPT. Section 29.4 explains how 
a logical processor may cache information from the paging structures, how it may use that cached information, and 
how software can managed the cached information.
29.1 VIRTUAL PROCESSOR IDENTIFIERS (VPIDS)
The original architecture for VMX operation required VMX tr ansitions to flush the TLBs and paging-structure caches. 
This ensured that translations cached for the old linear-address space would not be used after the transition.
Virtual-processor identifiers ( VPIDs ) introduce to VMX operation a facility by which a logical processor may cache 
information for multiple linear-address spaces. When VPID s are used, VMX transitions may retain cached informa-
tion and the logical processor switches to a different linear-address space.
Section 29.4 details the mechanisms by which a logical pr ocessor manages information cached for multiple address 
spaces. A logical processor may tag some cached informat ion with a 16-bit VPID. This  section specifies how the 
current VPID is determined at any point in time:
•The current VPID is 0000H in the following situations:
— Outside VMX operation. (This includes operation in system-management mode under the default treatment 
of SMIs and SMM with VMX operation; see Section 32.14.)
— In VMX root operation.
— In VMX non-root operation when the “enable VPID” VM-execution control is 0.
•If the logical processor is in VMX non-root operation and the “enable VPID” VM-execution control is 1, the 
current VPID is the value of the VPID VM-execution cont rol field in the VMCS. (VM entry ensures that this value 
is never 0000H; see Section 27.2.1.1.)
VPIDs and PCIDs (see Section 4.10.1) can be used concu rrently. When this is done, the processor associates 
cached information with both a VPID and a PCID. Such in formation is used only if the current VPID and PCID both 
match those associated with the cached information.
29.2 HYPERVISOR-MANAGED LINE AR-ADDRESS TRANSLATION (HLAT)
Hypervisor-managed linea r-address translation  (HLAT ) is a feature that changes the way in which linear 
addresses are translated in VMX non-r oot operation. Instead of ordinary paging, translation uses a modified 
process called HLAT paging .
HLAT paging is used only if the “enable HLAT” VM-execution  control is 1. HLAT paging is used only for the paging 
modes 4-level paging and 5-level paging. Because HLAT paging  is a modification of ordinary paging, details of the 
feature are given in Section 4.5, which describes the operation of 4-level paging and 5-level paging.
29.3 THE EXTENDED PAGE TABLE MECHANISM (EPT)

The extended page-table mechanism ( EPT) is a feature that can be used to support the virtualization of physical 
memory. When EPT is in use, certain addresses that would normally be treated as physical addresses (and used to 
access memory) are instead treated as guest-physical addresses . Guest-physical addresses are translated by 
traversing a set of EPT paging structures  to produce physical addresses that are used to access memory.29-2 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
•Section 29.3.1 gives an overview of EPT.
•Section 29.3.2 describes operation of EPT-based address translation.
•Section 29.3.3 discusses VM exits that may be caused by EPT.
•Section 29.3.7 describes interactions  between EPT and memory typing.
29.3.1 EPT Overview
EPT is used when the “enable EPT” VM-execution control is 1.1 It translates the guest-physical addresses used in 
VMX non-root operation and those us ed by VM entry for event injection.
The translation from guest-physical addresses to physical addresses is determined by a set of EPT paging struc-
tures . The EPT paging structures are similar to those used to translate linear addresses while the processor is in 
IA-32e mode. Section 29.3.2 gives the details of the EPT paging structures.
If CR0.PG = 1, linear addresses are translated through pa ging structures referenced through control register CR3.2 
While the “enable EPT” VM-execution control is 1, these are called guest paging structures . There are no guest 
paging structures if CR0.PG = 0.3
When the “enable EPT” VM-execution  control is 1, the identity of guest-physical addresses  depends on the value 
of CR0.PG:
•If CR0.PG = 0, each linear address is treated as a guest-physical address.
•If CR0.PG = 1, guest-physical addresses are those derive d from the contents of control register CR3 and the 
guest paging structures. (This includes the values of the PDPTEs, which logical processors store in internal, 
non-architectural registers.) The latter includes (in page-t able entries and in other paging-structure entries for 
which bit 7—PS—is 1) the addresses to which linear addr esses are translated by the guest paging structures.
If CR0.PG = 1, the translation of a linea r address to a physical address requires multiple translations of guest-phys-
ical addresses using EPT. Assume, for example, that CR 4.PAE = CR4.PSE = 0. The translation of a 32-bit linear 
address then operates as follows:
•Bits 31:22 of the linear address select an entry in th e guest page directory located at the guest-physical 
address in CR3. The guest-physical address of the gues t page-directory entry (PDE) is translated through EPT 
to determine the guest PDE’s physical address.
•Bits 21:12 of the linear address select an entry in the gu est page table located at the guest-physical address in 
the guest PDE. The guest-physical address of the guest page-table entry (PTE) is translated through EPT to 
determine the guest PTE’s physical address.
•Bits 11:0 of the linear address is the offset in the page  frame located at the guest-physical address in the guest 
PTE. The guest-physical address determined by this offs et is translated through EPT to determine the physical 
address to which the original linear address translates.
In addition to translating a guest-physical address to a ph ysical address, EPT specifies the privileges that software 
is allowed when accessing the address. A ttempts at disallowed accesses are called EPT violations  and cause 
VM exits. See Section 29.3.3.
A processor uses EPT to translate guest-physical addresse s only when those addresses are used to access memory. 
This principle implies the following:
•The MOV to CR3 instruction loads CR3 with a guest-phys ical address. Whether that  address is translated 
through EPT depends on whether PAE paging is being used.4
1. “Enable EPT” is a secondary processor-based VM-execution contro l. If bit 31 of the primary processor-based VM-execution contro ls 
is 0, the logical processor operates as if the “enabl e EPT” VM-execution control were 0. See Section 25.6.2.
2. If HLAT paging is enabled, the processor uses the HLATP VMCS field instead of CR3. See Sectio n 4.5.1. For simplicity, the rem ainder 
of this section refers only to CR3.
3. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, CR0.PG can be 0 in VMX non-root 
operation only if the “unrestric ted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are 
both 1.
4. A logical processor uses PAE paging if CR0.PG = 1, CR4.PA E = 1 and IA32_EFER.LMA = 0. See Section 4.4 in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 3A.Vol. 3C 29-3VMX SUPPORT FOR ADDRESS TRANSLATION
— If PAE paging is not being used, the instruction does not use that address to access memory and does not 
cause it to be translated through EPT. (If CR0.PG = 1, the address will be translated through EPT on the 
next memory accessing using a linear address.)
— If PAE paging is being used, the instruction loads the four (4) page-directory-pointer-table entries (PDPTEs) 
from that address and it does cause the address to be translated through EPT.
•Section 4.4.1 identifies executions of MOV to CR0 an d MOV to CR4 that load the PDPTEs from the guest-
physical address in CR3. Such executions caus e that address to be translated through EPT.
•The PDPTEs contain guest-physical addresses. The instru ctions that load the PDPTEs (see above) do not use 
those addresses to access memory and do not cause them to be translated through EPT. The address in a 
PDPTE will be translated through EPT on the next me mory accessing using a linear address that uses that 
PDPTE.
29.3.2 EPT Translation Mechanism
The EPT translation mechanism can be configured in either of two modes: 4-level EPT  or 5-level EPT. 4-level EPT 
accesses at most 4 EPT paging-structure entries (an EPT page-walk length of 4) to translate a guest-physical 
address and uses only bits 47:0 of each guest-physical address. In contrast, 5-level EPT may access up to 5 EPT 
paging-structure entries (an EPT page-walk length of 5) and uses guest-physical address bits 56:0.1
The EPT page-walk length is configured using the extended -page-table pointer (EPTP), a VM-execution control field 
(see Table 25-9 in Section 25.6.11). Specifically, bits 5:3 contain a value one less than EPT page-walk length. Thus, a value of 3 configures 4-level EPT, while a value of 4 configures 5-level EPT.
2
The remainder of this section describes the translation process used by 4-level EPT and 5-level EPT. Because the processes used by the two EPT modes are similar, they are described together in the following items (with any 
differences identified):
•With 5-level EPT, 4-KByte naturally aligned EPT PML5 table is located at the physical address specified in 
bits 51:12 of the EPTP. An EPT PML5 table comprises 512 64-bit entries (EPT PML5Es). An EPT PML5E is selected using the physical address defined as follows:
— Bits 63:52 are all 0.— Bits 51:12 are from the EPTP.
— Bits 11:3 are bits 56:48 of the guest-physical address.
3
Because an EPT PML5E is identified using bits 56:48 of the guest-physical address, it controls access to a 256-
TByte region of the guest-physical-address space. Th e format of an EPT PML5E is given in Table 29-1.
•With 4-level EPT, bits 51:48 of the guest-physical address must all be zero; otherwise, an EPT violation occurs 
(see Section 29.3.3).
•A 4-KByte naturally aligned EPT PML4 table is located at the physical address specifie d in the EPTP (for 4-level 
EPT) or in the EPT PML5E (for 5-level EPT). An EPT PML4 table comprises 512 64-bit entries (EPT PML4Es). An EPT PML4E is selected using the physical address defined as follows:
— Bits 63:52 are all 0.— Bits 51:12 are from the EPTP (for 4-level EPT) or from bits 51:12 of the EPT PML4E (for 5-level EPT).
— Bits 11:3 are bits 47:39 of the guest-physical address.
1. Physical addresses and guest-physical addresses are architecturally  limited to 52 bits (e.g., by paging), so in practice bits 56:52 are 
zero.
2. Software should read the VMX capability  MSR IA32_VMX_EPT_VPID_CAP (see Appendix A.10) to de termine what EPT page-walk 
lengths are supported.
3. Bits 56:52 of each guest-physical address are necessarily zero because guest-physical addresses are architecturally limited t o 52 
bits.29-4 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
Because an EPT PML4E is identified using bits 47:39 of the guest-physical address, it controls access to a 512-
GByte region of the guest-physical -address space. The format of an EPT PML4E is given in Table 29-2.
•A 4-KByte naturally aligned EPT page-directory-pointer ta ble is located at the physical address specified in 
bits 51:12 of the EPT PML4E. An EPT page-directory-poi nter table comprises 512 64-bit entries (EPT PDPTEs). 
An EPT PDPTE is selected using the physical address defined as follows:

zero.
— Bits 63:52 are all 0.— Bits 51:12 are from the EPT PML4E.
— Bits 11:3 are bits 38:30 of the guest-physical address.
Because an EPT PDPTE is identified using bits 47:30 of the guest-physical address, it controls access to a 1-GByte 
region of the guest-physical-address space. Use of the EPT PDPTE depends on the valu e of bit 7 in that entry:
1
•If bit 7 of the EPT PDPTE is 1, the EPT PDPTE maps a 1- GByte page. The final physical address is computed as 
follows:
— Bits 63:52 are all 0.— Bits 51:30 are from the EPT PDPTE.
— Bits 29:0 are from the original guest-physical address.Table 29-1.  Format of an EPT PML5 Entry (PML5E) that References an EPT PML4 Table
Bit 
0 Read access; indicates whether reads are allowed from the 256-TByte region controlled by this entry.
1 Write access; indicates whether writes are allowed to the 256-TByte region controlled by this entry.
2 If the “mode-based execute control for EPT” VM-execution co ntrol is 0, execute access; indicates whether instruction 
fetches are allowed from the 256-TByte  region controlled  by this entry.
If that control is 1, execute access for supervisor-mode li near addresses; indicates wh ether instruction fetches are 
allowed from supervisor-mode linear addresses in  the 256-TByte region co ntrolled by this entry.
7:3 Reserved (must be 0).
8 If bit 6 of EPTP is 1, accessed flag  for EPT; indicates whether software has accessed the 256-TByte region 
controlled by this entry (see Section 29 .3.5). Ignored if bit 6 of EPTP is 0.
9I g n o r e d .
10 Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is 
1, indicates whether instruction fetc hes are allowed from user-mode linear addresses in the 256-TByte region 
controlled by this entry. If that control is 0, this bit is ignored.
11 Ignored.
(N–1):12 Physical address of 4-KByte aligned EPT PML4 table referenced by this entry.1
51:N Reserved (must be 0).
63:52 Ignored.
NOTES:
1. N is the physical-address width supported by the processor. Software can determine a processor’s physical-address width by e xecut-
ing CPUID with 80000008H in EAX. The physical-a ddress width is returned in bits 7:0 of EAX.
1. Not all processors allow bit 7 of an EPT PD PTE to be set to 1. Software should read  the VMX capability MS R IA32_VMX_EPT_VPID_-
CAP (see Appendix A.10) to determine whether this is allowed.Vol. 3C 29-5VMX SUPPORT FOR ADDRESS TRANSLATION
The format of an EPT PDPTE that maps a 1-GByte page is given in Table 29-3.
•If bit 7 of the EPT PDPTE is 0, a 4-KByte naturally aligne d EPT page directory is located at the physical address 
specified in bits 51:12 of the EPT PDPTE. The format of an EPT PDPTE that references an EPT page directory is 
given in Table 29-4.Table 29-2.  Format of an EPT PML4 Entry (PML4E) th at References an EPT Page-Directory-Pointer Table
Bit 
0 Read access; indicates whether reads are allowed from the 512-GByte region controlled by this entry.
1 Write access; indicates whether wr ites are allowed to the 512-GByte region controlled by this entry.
fetches are allowed from the 512-GByt e region controlled by this entry.
If that control is 1, execute access for supervisor-mode linear addresses; indicates wh ether instruction fetches are 
allowed from supervisor-mode line ar addresses in the 512-GByte region controlled by this entry.
8 If bit 6 of EPTP is 1, accessed fl ag for EPT; indicates whether softwa re has accessed the 512-GByte region 
controlled by this entry (see Section 29 .3.5). Ignored if bi t 6 of EPTP is 0.
9I g n o r e d .
1, indicates whether instruction fetc hes are allowed from user-mode linear addresses in the 512-GByte region 
(N–1):12 Physical address of 4-KByte aligned EPT page -directory-pointer table re ferenced by this entry.1
NOTES:
1. N is the physical-address width supported by the processor.29-6 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
Table 29-3.  Format of an EPT Pa ge-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page
Bit 
0 Read access; indicates whether reads are allowed from the 1-GByte page referenced by this entry.
1 Write access; indicates whether writes are allowed to the 1-GByte page referenced by this entry.
2 If the “mode-based execute control for EPT” VM-execution control is 0, execute access; indicates whether 
instruction fetches are allowed from the 1-GByte page controlled by this entry.
allowed from supervisor-mode linear addresses in the 1-GByte page controlled by this entry.
5:3 EPT memory type for this 1- GByte page (see Section 29.3.7).
6 Ignore PAT memory type for this 1-GByte page (see Section 29.3.7).
7 Must be 1 (otherwise, this entry references an EPT page directory).8 If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 1-GByte page referenced 
by this entry (see Section 29.3.5).  Ignored if bit 6 of EPTP is 0.
9 If bit 6 of EPTP is 1, dirty flag for EPT; indicates whether software has written to the 1-GByte page referenced by 
this entry (see Section 29.3.5). Ignored if bit 6 of EPTP is 0.
1, indicates whether instruction fetche s are allowed from user-mode linear ad dresses in the 1-GByte page controlled 
by this entry. If that contro l is 0, this bit is ignored.
29:12 Reserved (must be 0).(N–1):30 Physical address of the 1-GB yte page referenced by this entry.
1
56:52 Ignored.57 Verify guest paging. If the “guest-paging verification” VM-exe cution control is 1, indicate s limits on the guest paging 
structures used to access the 1-GByte page  controlled by this entry (see Section 29 .3.3.2). If that control is 0, this 
bit is ignored.
58 Paging-write access. If the “EPT paging-write control” VM -execution control is  1, indicates that guest paging may 
update the 1-GByte page controlled by th is entry (see Section 29.3.3.2). If that control is 0, this bit is ignored.
59 Ignored.60 Supervisor shadow stack. If bit 7 of EPTP is 1, indicates whether supervisor shadow stack accesses are allowed to 
guest-physical addresses in the 1-GByte page mapped by this entry (see Section 29.3.3.2).
Ignored if bit 7 of EPTP is 0.
62:61 Ignored.63 Suppress #VE. If the “EPT-violation #VE” VM-execution cont rol is 1, EPT violations caus ed by accesses to this page 
are convertible to virtualization exceptions only if this bi t is 0 (see Section 26.5.7.1).  If “EPT-violation #VE” VM-
execution control is 0, this bit is ignored.
NOTES:
1. N is the physical-address width supported by the processor.Vol. 3C 29-7VMX SUPPORT FOR ADDRESS TRANSLATION
An EPT page-directory comprises 512 64-bit entries (PDEs) . An EPT PDE is selected using the physical address 
— Bits 63:52 are all 0.— Bits 51:12 are from the EPT PDPTE.
— Bits 11:3 are bits 29:21 of the guest-physical address.
Because an EPT PDE is identified using bits 47:21 of the guest-physical address, it controls access to a 2-MByte 
region of the guest-physical-address space. Use of the EPT PDE depends on the value of bit 7 in that entry:
•If bit 7 of the EPT PDE is 1, the EPT PDE maps a 2-MB yte page. The final physical address is computed as 
follows:
— Bits 63:52 are all 0.— Bits 51:21 are from the EPT PDE.
— Bits 20:0 are from the original guest-physical address.
The format of an EPT PDE that maps a 2-MByte page is given in Table 29-5.
•If bit 7 of the EPT PDE is 0, a 4-KByte naturally alig ned EPT page table is located at the physical address 
specified in bits 51:12 of the EPT PDE. The format of an EPT PDE that references an EPT page table is given in 
Table 29-6.
An EPT page table comprises 512 64-bit entries (PTEs). An  EPT PTE is selected using a physical address defined 
— Bits 63:52 are all 0.Table 29-4.  Format of an EPT Page-D irectory-Pointer -Table Entry (PDPTE) that Refe rences an EPT Page Directory
Bit 
0 Read access; indicates whether reads are allowed from the 1-GByte region controlled by this entry.
1 Write access; indicates whether writes are allowed to the 1-GByte region controlled by this entry.
2 If the “mode-based execute control for EPT” VM-execution control is 0, execute access; indicates whether instruction 
fetches are allowed from the 1-GByt e region controlled by this entry.

Bit 
allowed from supervisor-m ode linear addresses in the 1-GByte region controlled by this entry.
8 If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has acce ssed the 1-GByte region controlled 
9I g n o r e d .
1, indicates whether instru ction fetches are allowed from user-mode linear addresses in the 1-GByte region 
(N–1):12 Physical address of 4-KByte aligned EPT page directory referenced by this entry.1
NOTES:
1. N is the physical-address width supported by the processor.29-8 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
— Bits 51:12 are from the EPT PDE.Table 29-5.  Format of an EPT Page-Direc tory Entry (PDE) that Maps a 2-MByte Page
Bit 
0 Read access; indicates whether reads are allowed from the 2-MByte page referenced by this entry.
1 Write access; indicates whether writes are allowed to the 2-MByte page referenced by this entry.
fetches are allowed from the 2-MByt e page controlled by this entry.
allowed from supervisor-mode linear addresses in the 2-MByte page controlled by this entry.
5:3 EPT memory type for this 2-MByte page (see Section 29.3.7).
6 Ignore PAT memory type for this 2-MByte page (see Section 29.3.7).
7 Must be 1 (otherwise, this entry references an EPT page table).
8 If bit 6 of EPTP is 1, accessed flag  for EPT; indicates whether software has accessed the 2-MByte page referenced 
by this entry (see Section 29.3.5). Ignored if bit 6 of EPTP is 0.
9 If bit 6 of EPTP is 1, dirty flag for EPT; indicates whether software has written to the 2-MByte page referenced by 
1, indicates whether instruction fetche s are allowed from user-mode linear addresses in the 2-MByte page controlled 
20:12 Reserved (must be 0).(N–1):21 Physical address of the 2-MByte page referenced by this entry.
1
51:N Reserved (must be 0).56:52 Ignored.57 Verify guest paging. If the “guest-paging verification” VM-exe cution control is 1, indicate s limits on the guest paging 
structures used to access the 2-MByte page controlled by this entry (see Section 29.3.3.2). If that control is 0, this 
58 Paging-write access. If the “EPT pagi ng-write control” VM-execu tion control is 1, indica tes that guest paging may 
update the 2-MByte page controlled by this entry (see Section 29.3.3.2). If that control is 0, this bit is ignored.
59 Ignored.60 Supervisor shadow stack. If bit 7 of EPTP is 1, indica tes whether supervisor shadow stack accesses are allowed to 
guest-physical addresses in the 2-MByte page mapped by this entry (see Section 29.3.3.2).
62:61 Ignored.63 Suppress #VE. If the “EPT-violation #VE”  VM-execution control is 1, EPT violat ions caused by accesses to this page 
NOTES:
1. N is the physical-address width supported by the processor.Vol. 3C 29-9VMX SUPPORT FOR ADDRESS TRANSLATION
— Bits 11:3 are bits 20:12 of the guest-physical address.
•Because an EPT PTE is identified using bits 47:12 of the guest-physical address, every EPT PTE maps a 4-KByte 
page. The final physical address is computed as follows:
— Bits 63:52 are all 0.
— Bits 51:12 are from the EPT PTE.— Bits 11:0 are from the original guest-physical address.
The format of an EPT PTE is given in Table 29-7.
An EPT paging-structure entry is present  if any of bits 2:0 is 1; otherwise, the entry is not present . The processor 
ignores bits 62:3 and uses the entry neither to referenc e another EPT paging-structure entry nor to produce a 
physical address. A reference using a guest-physical ad dress whose translation encounters an EPT paging-struc-
ture that is not present causes an EPT violation (see Se ction 29.3.3.2). (If the “EPT-violation #VE” VM-execution 
control is 1, the EPT violation is convertible to a virtualizat ion exception only if bit 63 is 0; see Section 26.5.7.1. If 
the “EPT-violation #VE” VM-execution control is 0, this bit is ignored.)
NOTE
If the “mode-based execute control for EPT” VM-exe cution control is 1, an EPT paging-structure 
entry is present if any of bits 2:0 or bit 10  is 1. If bits 2:0 are all 0 but bit 10 is 1, the entry is used 
normally to reference another EPT paging-structure entry or to produce a physical address.Table 29-6.  Format of an EPT Page-Directory Entry (PDE) that References an EPT Page Table
Bit 
0 Read access; indicates whether re ads are allowed from the 2-MByte region controlled by this entry.
1 Write access; indicates whether wr ites are allowed to the 2-MByte region controlled by this entry.
fetches are allowed from the 2-MByt e region controlled by this entry.
allowed from supervisor-mode linear addresses in the 2-MByte region controlled by this entry.
6:3 Reserved (must be 0).
7 Must be 0 (otherwise, this entry maps a 2-MByte page).8 If bit 6 of EPTP is 1, accessed flag  for EPT; indicates whethe r software has accessed the 2-MByte region controlled 
9I g n o r e d .
1, indicates whether instruction fetc hes are allowed from user-mode linear addresses in the 2-MByte region 
(N–1):12 Physical address of 4-KByte aligned EPT page table referenced by this entry.
1
NOTES:
1. N is the physical-address width supported by the processor.51:N Reserved (must be 0).
63:52 Ignored.29-10 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
The discussion above describes how the EPT paging structur es reference each other and how the logical processor 
traverses those structures when translating a guest-physical address. It does not cover all details of the translation process. Additional details are provided as follows:
•Situations in which the translation process may lead to VM exits (sometimes before the process completes) are 
described in Section 29.3.3.
•Interactions between the EPT translation mechanism an d memory typing are described in Section 29.3.7.
Figure 29-1 gives a summary of the formats of the EPTP an d the EPT paging-structure entries. For the EPT paging 
structure entries, it identifies separately the format of  entries that map pages, those that reference other EPT 
paging structures, and those that do neither because th ey are not present; bits 2:0 and bit 7 are highlighted 
because they determine how a paging-structure entry is us ed. (Figure 29-1 does not comprehend the fact that, if 
the “mode-based execute control for EPT” VM-execution control is 1, an entry is present if any of bits 2:0 or bit 10 
is 1.)
29.3.3 EPT-Induced VM Exits
Accesses using guest-physical addresses may cause VM exits due to EPT misconfigurations, EPT violations, and 
page-modification log-full events. An EPT misconfiguration  occurs when, in the course of translating a guest-
physical address, the logical processor encounters an EPT paging-structure entry that contains an unsupported value (see Section 29.3.3.1). An EPT violation  occurs when there is no EPT misconfiguration but the EPT paging-
structure entries disallow an access using the gu est-physical address (see Section 29.3.3.2). A page-modifica-
tion log-full event  occurs when the logical processor determines a need to create a page-modification log entry 
and the current log is full (see Section 29.3.6).
These events occur only due to an attempt to access memo ry with a guest-physical address. Loading CR3 with a 
guest-physical address with the MOV to CR3 instruction can cause neither an EPT configuration nor an EPT violation

is 1.)
guest-physical address with the MOV to CR3 instruction can cause neither an EPT configuration nor an EPT violation 
until that address is used to access a paging structure.
1
If the “EPT-violation #VE” VM-executi on control is 1, certain EPT violations may cause virtualization exceptions 
instead of VM exits. See Section 26.5.7.1.
29.3.3.1  EPT Misconfigurations
An EPT misconfiguration occurs if translation of a guest-ph ysical address encounters an EPT paging-structure entry 
that meets any of the following conditions:
•Bit 0 of the entry is clear (indicating that data reads are not allowed) and any of the following hold:
— Bit 1 is set (indicating that data writes are allowed).— The processor does not support execute-only translations and either of the following hold:
•Bit 2 is set (indicating that instruction fetches are allowed).2
•The “mode-based execute control for EPT” VM-execution control is 1 and bit 10 is set (indicating that 
instruction fetches are allowed from user-mode linear addresses).
Software should read the VMX capability MSR IA32_ VMX_EPT_VPID_CAP to determine whether execute-
only translations are supported (see Appendix A.10).
— The “EPT paging-write control” VM-execution control is 1, the entry maps a page, and bit 58 is set 
(indicating that paging writes are allowed).
•The entry is present (see Section 29.3.2) and of the following holds:
1. If the logical processor is using PAE paging—because CR0.PG = CR4.PAE = 1 and IA32_EFER.LMA = 0—the MOV to CR3 instruction 
loads the PDPTEs from memory using the guest-physical address be ing loaded into CR3. In this case, ther efore, the MOV to CR3 
instruction may cause an EPT misconfiguration, an EPT violation, or a page-modification log-full event.
2. If the “mode-based execute control for EPT” VM-execution contro l is 1, setting bit 2  indicates that inst ruction fetches are al lowed 
from supervisor-mode linear addresses.Vol. 3C 29-11VMX SUPPORT FOR ADDRESS TRANSLATION
Table 29-7.  Format of an EPT Page-T able Entry that Maps a 4-KByte Page
Bit 
0 Read access; indicates whether reads are allowed from the 4-KByte page referenced by this entry.
1 Write access; indicates whether writes are allowe d to the 4-KByte page re ferenced by this entry.
2 If the “mode-based execute control for EPT” VM-executi on control is 0, execute access; indicates whether 
instruction fetches are allowed from the 4-KByte page controlled by this entry.
allowed from supervisor-mode linear addresses in the 4-KByte page controlled by this entry.
5:3 EPT memory type for this 4-KByte page (see Section 29.3.7).
6 Ignore PAT memory type for this 4-KByte page (see Section 29.3.7).
7I g n o r e d .8 If bit 6 of EPTP is 1, accessed flag for EPT; indicates whether software has accessed the 4-KByte page referenced 
by this entry (see Section 29.3.5) . Ignored if bit 6 of EPTP is 0.
9 If bit 6 of EPTP is 1, dirty flag for EPT; indicates whether software has written to the 4-KByte page referenced by 
this entry (see Sectio n 29.3.5). Ignored if bit 6 of EPTP is 0.
1, indicates whether instruction fetches are allowed from user-mode linear addresses in the 4-KByte page controlled 
(N–1):12 Physical address of the 4-KByte page referenced by this entry.
1
56:52 Ignored.
57 Verify guest paging. If the “guest-paging verification” VM-execution control is 1, indicates limits on the guest paging 
structures used to access the 4-KByte page  controlled by this entry (see Section 29 .3.3.2). If that control is 0, this 
58 Paging-write access. If the “EPT paging-write control” VM -execution control is 1, indi cates that guest paging may 
update the 4-KByte page controlled by this entry (see Sectio n 29.3.3.2). If that control is 0, this bit is ignored.
59 Ignored.
60 Supervisor shadow stack. If bit 7 of EPTP is 1, indicates whether supervisor  shadow stack accesses are allowed to 
guest-physical addresses in the 4-KByte page mapped by this entry (see Section 29.3.3.2).
61 Sub-page write permissions. If the “sub-page write perm issions for EPT” VM -execution control is 1, writes to 
individual 128-byte regions of the 4-KByte page referenced by this entry may be allowed even if the page would 
normally not be writable (see Section 29.3.4). If “sub-page write permissions for EPT” VM-execution control is 0, this 
62 Ignored.63 Suppress #VE. If the “E PT-violation #VE” VM-execution co ntrol is 1, EPT violations caus ed by accesses to this page 
are convertible to virtualization  exceptions only if this bit is 0 (see Se ction 26.5.7.1). If “EPT-violation #VE” VM-
execution control is 0, this bit is ignored.29-12 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
— A reserved bit is set. This includes the setting of  a bit in the range 51:12 that is beyond the logical 
processor’s physical-address width.1 See Section 29.3.2 for details of which bits are reserved in which EPT 
paging-structure entries.
— The entry is the last one used to translate a guest phys ical address (either an EPT PDE with bit 7 set to 1 or 
an EPT PTE) and the value of bits 5:3 (EPT memory type) is 2, 3, or 7 (these values are reserved).
EPT misconfigurations result when an EPT paging-structure  entry is configured with settings reserved for future 
functionality. Software developers should be aware that such settings may be used in the future and that an EPT 
paging-structure entry that causes an EPT misconfigurat ion on one processor might not do so in the future.
29.3.3.2  EPT Violations
An EPT violation may occur during an access using a guest-physical address whose translation does not cause an 
EPT misconfiguration. An EPT violation occu rs in any of the following situations:
•Translation of the guest-physical address encounters an EPT paging-structure entry that is not present (see 
Section 29.3.2).
•The access is a data read and, for any byte to be read , bit 0 (read access) was clear in any of the EPT paging-
structure entries used to translate the guest-physical address of the byte. Reads by the logical processor of 
guest paging structures to translate a linear address are considered to be data reads.NOTES:
1. N is the physical-address width supported by the processor.
width is returned in bits 7:0 of EAX.Vol. 3C 29-13VMX SUPPORT FOR ADDRESS TRANSLATION
6
36
26
16
05
95
85
75
65
55
45
35
25
1M1
NOTES:
23
13
02
92
82
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
Reserved Address of EPT PML5 table or PML4 table Rsvd.S
S
S2
2. Supervisor shad ow-stack control.A
/
DEPT
PWL–
1EPT
PS
MTEPTP3
3. See Section 25.6.11 for details of the EPTP.Ignored Rsvd. Address of EPT PML4 tableIg
n.X
U4
4. Execute access for user-mode linear addresses. If the “mode-based execute control for EPT” VM-execution control is 0, this b it is 
ignored.Ig
n.A ReservedX5
5. Execute access. If the “mode-based execute control for EPT” VM-execution control is 1, this bit controls execute access for supervi-
sor-mode linear addresses.WRPML5E:
present6
S
V
E7Ignored 000PML5E:
not
present
Ignored Rsvd. Address of EPT page-directory-pointer tableIg
n.X
UIg
n.A Reserved X W RPML4E:
present
S
V
EIgnored 000PML4E:
not
present
S
V
EIgn.S
S
S8Ig
n.P
W
9V
G
P
10Ignored Rsvd.Physical 
address of
1GB pageReservedIg
n.X
UDA 1I
P
A
TEPT
MTXWRPDPTE:
1GB
page
Ignored Rsvd. Address of EPT page directoryIg
n.X
UIg
n.A0Rsvd. X W RPDPTE:
page
directory
S
V
EIgnored 000PDTPE:
not
present
S
V
EIgn.S
SSIg
n.P
WV
G
PIgnored Rsvd.Physical address
of 2MB pageReservedIg
n.X
UDA 1I
P
A
TEPT
MTXWRPDE:
2MB
page
Ignored Rsvd. Address of EPT page tableIg
n.X
UIg
n.A0Rsvd. X W RPDE:
page
table
S
V
EIgnored 000PDE:
not
present
S
V
EIg
n.S
P
P
11S
S
SIg
n.P
WV
G
PIgnored Rsvd. Physical address of 4KB pageIg
n.X
UDAI
g
nI
P
A
TEPT
MTXWRPTE:
4KB
page
S
V
EIgnored 000PTE:
not
present
Figure 29-1.  Formats of EPTP and EPT Paging-Structure Entries29-14 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
•The access is a data write and, for any byte to be written, bit 1 (write access) was clear in any of the EPT 
paging-structure entries used to translate the guest- physical address of the byte. Writes by the logical 
processor to guest paging structures to update accessed and dirty flags are considered to be data writes.
If bit 6 of the EPT pointer (EPTP) is 1 (enabling acce ssed and dirty flags for EPT), processor accesses to guest 
paging-structure entries are treated as writes with regard to EPT violations. Thus, if bit 1 is clear in any of the 
EPT paging-structure entries used to translate the guest-physical address of a guest paging-structure entry, an

page
table
S
V
not
present
S
V
EIg
n.S
P
P
11S
S
SIg
n.P
WV
G
n.X
UDAI
g
nI
P
A
TEPT
MTXWRPTE:
4KB
page
S
V
not
present
EPT paging-structure entries used to translate the guest-physical address of a guest paging-structure entry, an 
attempt to use that entry to translate a linear address causes an EPT violation.
(This does not apply to loads of the PDPTE registers by  the MOV to CR instruction for PAE paging; see Section 
4.4.1. Those loads of guest PDPTEs are treated as reads and do not cause EPT violations due to a guest-physical 
address not being writable.)
Processor writes to guest paging structures to update accessed and dirty flags are called paging writes . 
(When accessed and dirty flags for EPT are enabled all processor accesses to guest paging structures are considered paging writes.) If the “EPT paging-write co ntrol” VM-execution control is 1, clearing the write-
access bit in the EPT paging-structure entry that maps a page does not prevent a paging write if bit 58 (paging-
write access) in that entry is 1. (EPT paging-structure entries that reference other EPT paging structures do not 
use bit 58, and it remains the case that they must set the write-access bit for paging writes to be allowed.)
If the “sub-page write permissions for EPT” VM-execution control is 1, data writes to a guest-physical address 
that would cause an EPT violation (as indicated above) do not do so in certain situations. If the guest-physical 
address is mapped using a 4-KByte page and bit 61 (sub-p age write permissions) of the EPT PTE used to map 
the page is 1, writes to certain 128-byte sub-pa ges may be allowed. See Section 29.3.4 for details.
•The access is an instruction fetch and the EPT paging structures prevent execute access to any of the bytes 
being fetched. Whether this occurs depends upon the se tting of the “mode-based execute control for EPT” VM-
execution control:
— If the control is 0, an instruction fetch from a byte is  prevented if bit 2 (execute access) was clear in any of 
the EPT paging-structure entries used to tran slate the guest-physical address of the byte.
— If the control is 1, an instruction fetch from a by te is prevented in either of the following cases:
•Paging maps the linear address of the byte as a su pervisor-mode address and bit 2 (execute access for 
supervisor-mode linear addresses) was clear in any of the EPT paging-structure entries used to 
translate the guest-physical address of the byte.
Paging maps a linear address as a supervisor-mode addr ess if the U/S flag (bit 2) is 0 in at least one of 
the paging-structure entries controlling the translation of the linear address.
•Paging maps the linear address of the byte as a user-mode address and bit 10 (execute access for user-
mode linear addresses) was clear in any of the EPT paging-structure entries used to translate the guest-
physical address of the byte.
Paging maps a linear address as a user-mode address if  the U/S flag is 1 in all of the paging-structure 
entries controlling the translation of the linear address.  If paging is disabled (CR0.PG = 0), every linear 
address is a user-mode address.
•If supervisor shadow-stack control is enabled (by setti ng bit 7 of EPTP), the access is a supervisor shadow-
stack access, and the EPT paging-structure entries used to translate the guest-physical address of the access disallow supervisor shadow-stack accesses. Such an access is disallowed if any of the following hold:
— Bit 0 (read access) is clear in any EPT paging-structure  entry used to translate the guest-physical address 
of the access.6. If the “mode-based execute control for EPT” VM-execution contro l is 1, an EPT paging-structure  entry is present if any of bi ts 2:0 or 
bit 10 is 1. This table does not comprehend that fact.
7. Suppress #VE. If the “EPT-v iolation #VE” VM-execution control is 0, this bit is ignored.
8. Supervisor shadow-stack page. If bit 7 of the EPTP is 0, this bit is ignored.
9. Paging-write access. If the “EPT paging-write cont rol” VM-execution control is 0, this bit is ignored.
10. Verify guest paging. If the “guest-paging verification” VM-execution control is 0, this bit is ignored.
11. Sub-page write permissions. If the “sub-page write permissi ons for EPT” VM-execution contro l is 0, this bit is ignored.Vol. 3C 29-15VMX SUPPORT FOR ADDRESS TRANSLATION
— Bit 1 (write access) is clear in any EPT paging-structure  entry that references an EPT paging structure in the 
translation of the guest-physical address. (Clearing bit 1 in the EPT paging-structure entry that maps the page of the guest-physical address does not disallow shadow-stack reads and writes.)
— Bit 60 (supervisor-shadow stack access) is clear in the EPT paging-structure entry that maps the page of 
the guest-physical address.
Supervisor shadow-stack control and the supervisor-shadow stack access bits in EPT paging-structure entries 
do not affect other accesses (including user shadow-stack accesses).
•If the “guest-paging verification” and “EPT paging-wri te control” VM-execution controls are both 1, guest-
paging verification  is performed for certain accesses relate d to translation of a linear address.
Specifically, guest-paging verification may apply to an  access using a guest-physical address to the guest 
paging-structure entry that maps a page for the linear address (see Chapter 4, “Paging”). It applies if bit 57 
(verify guest paging) is set in the EPT paging-structure entry that maps a page for that guest-physical address.
When guest-paging verification occurs, there is an EPT violation if bit 58 (paging-write access) is clear in the 
EPT paging-structure entry that was used to map a page  for the guest-physical address of any guest paging-
structure entry that was used during translation of the original linear address.1
See Section 29.3.3.3 for details regarding the prioritization  of such EPT violations relative to any page faults 
that may occur due to the original reference to the linear address being translated.
29.3.3.3  Prioritization of EPT Misconfigurations and EPT Violations
The translation of a linear address to a physical address requires one or more translations of guest-physical 
addresses using EPT (see Section 29.3.1). This section spec ifies the relative priority of EPT-induced VM exits with 
respect to each other and to other events that may be encountered when accessing memory using a linear address.
For an access to a guest-physical address, determination of whether an EPT misconfiguration or an EPT violation 
occurs is based on an iterative process:2
1. An EPT paging-structure entry is read (initially, this is an EPT PML5 entry or an EPT PML4 entry):
a. If the entry is not present (see Section 29.3.2), an EPT violation occurs.
b. If the entry is present but its contents are not conf igured properly (see Section 29.3.3.1), an EPT miscon-
figuration occurs.
c. If the entry is present and its contents are config ured properly, operation depends on whether the entry 
references another EPT paging structur e (or if instead it is an EPT PDPTE or EPT PDE with bit 7 set to 1, or 
an EPT PTE):
i) If the entry does reference another EPT paging structure, an entry from that structure is accessed; 
step 1 is executed for that other entry.
ii) Otherwise, the entry is used to produce the ultimate  physical address (the translation of the original 
guest-physical address); step 2 is executed.
2. Once the ultimate physical address is determined, the privileges determined by the EPT paging-structure 
entries are evaluated:
a. If the access to the guest-physical address is not al lowed by these privileges (see Section 29.3.3.2), an EPT 
violation occurs.
b. If the access to the guest-physical address is allowe d by these privileges, memory is accessed using the 
ultimate physical address.
If CR0.PG = 1, the translation of a linea r address is also an iterative process, with the processor first accessing an 
entry in the guest paging structure referenced by the guest-physical address in CR3,3 then accessing an entry in 
1. When there is a restart of HLAT paging (see Section 4.5), the guest paging-structure entries used by HLAT paging (prior to th e 
restart) are not relevant to guest-paging verification.
2. This is a simplification of the more detailed description given in Section 29.3.2.
3. If PAE paging is in use, the processor instead uses the guest-physical address in the appropriate PDPTE register. If HLAT pag ing is 
enabled, the processor instead uses the HLATP VMCS field. For simplicity, the remainder of this section refers only to CR3.29-16 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
another guest paging structure referenced by the guest-phys ical address in the first guest paging-structure entry, 
etc. Each guest-physical address is itself translat ed using EPT and may cause an EPT-induced VM exit. The 
following items detail how page faults and EPT-induced VM exits are recognized during this iterative process:
1. An attempt is made to access a guest paging-structure  entry with a guest-physical address (initially, the 
address in CR3.
a. If the access fails because of an EPT misconfiguratio n or an EPT violation (see above), an EPT-induced 
VM exit occurs.

b. If the access does not cause an EPT-induced VM exit, the translation continues. If guest-paging verification 
is enabled (see Section 29.3.3.2), the processor note s whether the EPT paging-structure entry used to map 
a page for the guest-physical address set bit 58 (pagin g write). Then, bit 0 (the present flag) of the guest 
paging-structure entry is consulted:
i) If the present flag is 0 or any reserved bit is set, a page fault occurs.
ii) If the present flag is 1, no reserved bit is se t, operation depends on whether the entry references 
another guest paging structure (whether it is a guest PDE with PS = 1 or a guest PTE):
•If the entry does reference another guest paging  structure, an entry from that structure is 
accessed; step 1 is executed for that other entry.
•Otherwise, the entry is used to produce the ultima te guest-physical address (the translation of the 
original linear address); step 2 is executed.
2. Once the ultimate guest-physical address is determ ined, the privileges determ ined by the guest paging-
structure entries are evaluated:
a. If the access to the linear address is not allowed by these privileges (e.g., it was a write to a read-only 
page), a page fault occurs.
b. If the access to the linear address is allowed by thes e privileges, an attempt is made to access memory at 
the ultimate guest-physical address:
i) If the access fails because of an EPT misconfigurat ion or an EPT violation (see above), an EPT-induced 
VM exit occurs. It is at this point that guest-paging verification occurs (if enabled), using the paging-write bits that were noted at occurrences of step 1b  above (see Section 29.3.3.2 for details of guest-
paging verification).
ii) If the access does not cause an EPT-induced VM exit, memory is accessed using the ultimate physical 
address (the translation, using EPT, of the ultimate guest-physical address).
If CR0.PG = 0, a linear address is treated as a guest-physic al address and is translated using EPT (see above). This 
process, if it completes without an EPT violation or EP T misconfiguration, produces a physical address and deter-
mines the privileges allowed by the EPT paging-structure entr ies. If these privileges do not allow the access to the 
physical address (see Section 29.3.3.2), an EPT violation occurs. Otherwise, memory is accessed using the physical 
address.
29.3.4 Sub-Page Write Permissions
Section 29.3.3.2 explained how EPT enforces the access righ ts for guest-physical addresses using EPT violations. 
Since these access rights are determined using the EPT pagi ng-structure entries that are used to translate a guest-
physical address, their granularity is limited to that which is used to map pages (1-GByte, 2-MByte, or 4-KByte).
The sub-page write-permission  feature allows the control of write accesses to guest-physical addresses to be 
controlled at finer granularity. Sub-page write permission s allow write accesses to be controlled at the granularity 
of naturally aligned 128-byte sub-pages . Specifically, the feature allows writes to selected sub-pages of 4-KByte 
page that would otherwise not be writable.
Sub-page write permissions are enabled setting the “sub-p age write permissions for EPT” VM-execution control to 
1. The remainder of this section describes changes to processor operation with this control setting.
Section 29.3.4.1 identifies the data accesses that are e ligible for sub-page write permissions. Section 29.3.4.2 
explains how the processor determines whether to allow such an access.Vol. 3C 29-17VMX SUPPORT FOR ADDRESS TRANSLATION
29.3.4.1  Write Accesses That Are El igible for Sub-Page Write Permissions
A guest-physical address is eligible for sub-page write permissions if writes to it would be disallowed following 
Section 29.3.3.2: bit 1 (write access) is clear in any of th e EPT paging-structure entries used to translate the guest-
physical address. Guest-physical addresses to which writ es would be disallowed for other reasons (e.g., the trans-
lation encounters an EPT paging-structure entry that is not present) are not eligible for sub-page write permis-
sions.
In addition, a guest-physical address is eligible for sub-pa ge write permissions only if it is mapped using a 4-KByte 
page and bit 61 (sub-page write permissions) of the EPT PT E used to map the page is 1. (Guest-physical addresses 
mapped with larger pages are not eligible for sub-page write permissions.)
For some memory accesses, the processor ignores bit 61 in  an EPT PTE used to map a 4-KByte page and does not 
apply sub-page write permissions to the access. (In such a case, the access causes an EPT violation when indicated 
by the conditions given in Section 29.3.3.2.) Sub-page  write permissions never apply to the following accesses:
•A write access performed within a transactional region.
•A write access by an enclave to an address within the enclave's ELRANGE. (Sub-page write permissions may 
apply to write accesses by an enclaves to addresses outside its ELRANGE.)
•A write access to the enclave page cache (EPC) by an Intel SGX instruction.
•A write access to a guest paging structure to update an accessed or dirty flag.
•Processor accesses to guest paging-structure entries when accessed and dirty flags for EPT are enabled (such 
accesses are treated as writes with regard to EPT violations).
There are additional accesses to which sub-page write permissions might not be applied (behavior is model-
specific). The following items enumerate examples:
•A write access that crosses two 4-KByte pages. In this  case, sub-page permissions may be applied to neither 
or to only one of the pages. (There is no write to either page unless the write is allowed to both pages.)
•A write access by an instruction that performs mu ltiple write accesses (sub-page write permissions are 
intended principally for basic instructions such as AND, MOV, OR, TEST, XCHG, and XOR).
If a guest-physical address is eligible for sub-page writ e permissions, the processor determines whether to allow 
write to the address using the process described in Section 29.3.4.2.
If a guest-physical address is eligible for sub-page write permissions and that address translates to an address on 
the APIC-access page (see Section 30.4), the processor may treat a write access to the address as if the “virtualize 
APIC accesses” VM-execution control were 0. For that re ason, it is recommended that software not configure any 
guest-physical address that translates to an address on  the APIC-access page to be eligible for sub-page write 
permissions.
29.3.4.2  Determining an Acce ss’s Sub-Page Write Permission
Sub-page write permissions control write accesses individual ly to each of the 32 128-byte sub-pages of a 4-KByte 
page. Bits 11:7 of guest-physical  address identify the sub-page.
For each guest-physical address eligible for sub-page write permissions, there is a 64-bit sub-page permission 
vector  (SPP vector ). All addresses on a 4-KByte page use the same SPP vector. If an address’s sub-page number 
(bits 11:7 of the address) is S, writes to address are allowe d if and only if bit 2S of the sub-page permission is set 
to 1. (The bits at odd positions in a SP P vector are not used and must be zero.)
Each page’s SPP vector is located in memory. For a write to a guest-physical address eligible for sub-page write 
permissions, the processor uses the following process to locate the address’s SPP vector:
1. The SPPTP (sub-page-permission-table pointer) VM-executi on control field contains the physical address of the 
4-KByte root SPP table (SSPL4 table). Bits 47:39 of the guest-physical address identify a 64-bit entry in that 
table, called an SPPL4E.
2. A 4-KByte SPPL3 table is located at the physical ad dress in the selected SPPL4E. Bits 38:30 of the guest-
physical address identify a 64-bit entr y in that table, called an SPPL3E.
3. A 4-KByte SPPL2 table is located at the physical ad dress in the selected SPPL3E. Bits 29:21 of the guest-
physical address identify a 64-bit entr y in that table, called an SPPL2E.29-18 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
4. A 4-KByte SPP-vector table (SSPL1 table) is located at  the physical address in the selected SPPL2E. Bits 20:12 
of the guest-physical address identify the 64-bit SPP vect or for the address. As noted earlier, bit 2S of the sub-
page permission vector determines whether the addre ss may be written, where S is the value of address 
bits 11:7.
(The memory type used to access these tables is re ported in bits 53:50 of the IA32_VMX_BASIC MSR. See 
Appendix A.1.)
A write access to multiple 128-byte sub-pages on a single 4-KByte page is allowed only if the indicated bit in the 
page’s SPP vector for each of those sub-pages is set to 1. The following items apply to cases in which an access 
writes to two 4-KByte pages:

bits 11:7.
•If a write to either page would be disallowed according to Section 29.3.3.2, the access might be disallowed even if the guest-physical address of that page is eligible for sub-page write permissions. (This behavior is 
model-specific.)
•The access is allowed only if, for each page, either (1) a  write to the page would be allowed following Section 
29.3.3.2; or (2) both (a) the guest-physical address of that page is eligible for sub-page write permissions; and (b) the page’s sub-page vector allows the write (as described above).
Bit 0 of each entry (SPPL4E, SPPL3E, or SPPL2E) is the entry’s valid  bit. If the process above accesses an entry in 
which this bit is 0, the process stops and the logical processor incurs an SPP miss .
In each entry (SPPL4E, SPPL4E, or SPPL2E), bits 11:1 ar e reserved, as are bits 63:N, where N is the processor’s 
physical-address width. If the process above accesses an entry in which the valid bit is 1 and in which some 
reserved bit is set, the process stop s and the logical processor incurs an SPP misconfiguration . Bits in an SPP 
vector in odd positions are also reserved; an SPP misconfiguration occurs also any of those bits are set in the final 
SPP vector.
SPP misses and SPP misconfigurations are called SPP-related events  and cause VM exits.
29.3.5 Accessed and Dirty Flags for EPT
The Intel 64 architecture supports accessed and dirty flags  in ordinary paging-structure entries (see Section 
4.8). Some processors also support corresponding flags in EPT paging-structure entries. Software should read the 
VMX capability MSR IA32_VMX_EPT_VPID_ CAP (see Appendix A.10) to determin e whether the processor supports 
this feature.
Software can enable accessed and dirty flags for EPT usin g bit 6 of the extended-page-table pointer (EPTP), a VM-
execution control field (see Table 25-9 in Section 25.6.11). If this bit is 1, the processor will set the accessed and 
dirty flags for EPT as described below. In addition, setting this flag causes processor accesses to guest paging-
structure entries to be treated as wr ites (see below and Section 29.3.3.2).
For any EPT paging-structure entry that is used during guest-physical-address translation, bit 8 is the accessed 
flag. For a EPT paging-structure entry that maps a page (as opposed to referencing another EPT paging structure), 
bit 9 is the dirty flag.
Whenever the processor uses an EPT paging-structure entry as part of guest-physical-address translation, it sets 
the accessed flag in that entry (if it is not already set).
Whenever there is a write to a guest-phys ical address, the processor sets the dirty flag (if it is not already set) in 
the EPT paging-structure entry that identifies the final ph ysical address for the guest-physical address (either an 
EPT PTE or an EPT paging-structure entry in which bit 7 is 1).
When accessed and dirty flags for EPT are enabled, processor accesses to guest paging-structure entries are 
treated as writes (see Section 29.3.3.2). Thus, such an a ccess will cause the processor to set the dirty flag in the 
EPT paging-structure entry that identifies the final physical address of the guest paging-structure entry.
(This does not apply to loads of the PDPTE registers for PAE paging by the MOV to CR instruction; see Section 4.4.1. 
Those loads of guest PDPTEs are treated as reads and do not cause the processor to set the dirty flag in any EPT 
paging-structure entry.)
These flags are “sticky,” meaning that, once set, the processor does not clear them; only software can clear them.Vol. 3C 29-19VMX SUPPORT FOR ADDRESS TRANSLATION
A processor may cache information from the EPT paging-str ucture entries in TLBs and paging-structure caches 
(see Section 29.4). This fact implies that, if software chan ges an accessed flag or a dirty flag from 1 to 0, the 
processor might not set the corresponding bit in memory on a subsequent access using an affected guest-physical 
address.
29.3.6 Page-Modification Logging
When accessed and dirty flags for EPT are enabled, software  can track writes to guest-physical addresses using a 
feature called page-modification logging .
Software can enable page-modification logging by setting the “enable PML” VM-execution control (see Table 25-7 
in Section 25.6.2). When this control is 1, the processor adds entries to the page-modification log  as described 
below. The page-modification log is a 4-KByte region of me mory located at the physical address in the PML address 
VM-execution control field. The page-modification log cons ists of 512 64-bit entries; the PML index VM-execution 
control field indicates the next entry to use.
Before allowing a guest-physical access, the processor may determine that it first needs to set an accessed or dirty 
flag for EPT (see Section 29.3.5). When this happens, the processor examines the PML index. If the PML index is 
not in the range 0–511, there is a page-modification log-full event  and a VM exit occurs. In this case, the 
accessed or dirty flag is not set, and the guest-physical access that triggered the event does not occur.
If instead the PML index is in the range 0–511, the processo r proceeds to update accessed or dirty flags for EPT as 
described in Section 29.3.5. If the processor updated a dirty flag for EPT (changing it from 0 to 1), it then operates 
1. The guest-physical address of the access is written to the page-modification log. Specifically, the guest-
physical address is written to physical address determin ed by adding 8 times the PM L index to the PML address. 
Bits 11:0 of the value written are always 0 (the guest-physical address written is thus 4-KByte aligned).
2. The PML index is decremented by 1 (this may ca use the value to transition from 0 to FFFFH).
Because the processor decrements the PML index with each log entry, the value may transition from 0 to FFFFH. At 
that point, no further logging will occur, as the processo r will determine that the PML index is not in the range 0–
511 and will generate a page-modification log-full event (see above).
29.3.7 EPT and Memory Typing
This section specifies how a logical processor determines the memory type use for a memory access while EPT is in 
use. (See Chapter 12, “Memory Cache Control‚” of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A, for details of memory typing in the Intel 64 architecture.) Section 29.3.7.1 explains how the 
memory type is determined for accesses to the EPT pagi ng structures. Section 29.3.7.2 explains how the memory 
type is determined for an access using a guest- physical address that is translated using EPT.
29.3.7.1  Memory Type Used fo r Accessing EPT Paging Structures
This section explains how the memory type is determined  for accesses to the EPT paging structures. The determi-
nation is based first on the value of bit 30 (cache disable—CD) in control register CR0:
•If CR0.CD = 0, the memory type used  for any such reference is the EPT paging-structure memory type, which 
is specified in bits 2:0 of the extended-page-table po inter (EPTP), a VM-execution control field (see Section 
25.6.11). A value of 0 indicates the uncacheable type (U C), while a value of 6 indicates the write-back type 
(WB). Other values are reserved.
•If CR0.CD = 1, the memory type used for any such reference is uncacheable (UC).
The MTRRs have no effect on the memory type used for an access to an EPT paging structure.
29.3.7.2  Memory Type Used for Translated Guest-Physical Addresses
The effective memory type  of a memory access using a guest-physical address (an access that is translated 
using EPT) is the memory type that is used to access me mory. The effective memory type  is based on the value of 29-20 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
bit 30 (cache disable—CD) in control register CR0; the last EPT paging-structure entry used to translate the guest-
physical address (either an EPT PDE with bit 7 set to 1 or an EPT PTE); and the PAT memory type (see below):
•The PAT memory type  depends on the value of CR0.PG:
— If CR0.PG = 0, the PAT memory type is WB (writeback).1
— If CR0.PG = 1, the PAT memory type is the memory ty pe selected from the IA32_PAT MSR as specified in 
Section 12.12.3, “Selecting a Memory Type from the PAT.”2
•The EPT memory type  is specified in bits 5:3 of the last EPT pa ging-structure entry: 0 = UC; 1 = WC; 4 = WT; 
5 = WP; and 6 = WB. Other values are reserved an d cause EPT misconfigurations (see Section 29.3.3).
•If CR0.CD = 0, the effective memory type depends upon the value of bit 6 of the last EPT paging-structure 
entry:
— If the value is 0, the effective memory type is the combination of the EPT memory type and the PAT memory 
type specified in Table 12-7 in Section 12.5.2.2, usin g the EPT memory type in place of the MTRR memory 
type.
— If the value is 1, the memory type used for the a ccess is the EPT memory type . The PAT memory type is 
ignored.
•If CR0.CD = 1, the effective memory type is UC.

entry:
type.
ignored.
The MTRRs have no effect on the memory type used for an access to a guest-physical address.
29.4 CACHING TRANSLATION INFORMATION
Processors supporting Intel®64 and IA-32 architectures may accelerate the address-translation process by 
caching on the processor data from the structures in memory that control that process. Such caching is discussed 
in Section 4.10, “Caching Transl ation Information,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A. The current section describes how this caching interacts with the VMX architecture.
The VPID and EPT features of the architecture for VMX operation augment this caching architecture. EPT defines 
the guest-physical address space and defines translations to that address space (from the linear-address space) 
and from that address space (to the physical-address spac e). Both features control the ways in which a logical 
processor may create and use information cached from the paging structures.
Section 29.4.1 describes the different ki nds of information that may be cached. Section 29.4.2 specifies when such 
information may be cached and how it may be used. Section 29.4.3 details how software can invalidate cached information.
29.4.1 Information That May Be Cached
Section 4.10, “Caching Translation Information,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A, identifies two kinds of translation- related information that may be cached by a logical 
processor: translations , which are mappings from linear page numbers to physical page frames, and paging-
structure caches , which map the upper bits of a linear page numb er to information from the paging-structure 
entries used to translate linear addresses matching those upper bits.
The same kinds of information may be cached when VPID s and EPT are in use. A logical processor may cache and 
use such information based on its function. Information with different functionality is identified as follows:
1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, CR0.PG can be 0 in VMX non-root 
both 1.
2. Table 12-11 in Section 12.12.3, “Selecting  a Memory Type from the PAT,” illustrates how the PAT memory type is selected based on 
the values of the PAT, PCD, and PWT bits in a page-table entry (or page-directory entry with PS = 1). For accesses to a guest pa ging-
structure entry X, the PAT memory type is se lected from the table by using a value of 0 for the PAT bit with the values of PCD a nd 
PWT from the paging-structure entr y Y that references X (or from CR3 if X is in the root paging structure). With PAE paging, the  PAT 
memory type for accesses to the PDPTEs is WB.Vol. 3C 29-21VMX SUPPORT FOR ADDRESS TRANSLATION
•Linear mappings .1 There are two kinds:
— Linear translations. Each of these is a mapping from a linear page number to the physical page frame to 
which it translates, along with information about access privileges and memory typing.
— Linear paging-structure-cache entries. Each of these is a mapping from the upper portion of a linear 
address to the physical address of the paging structur e used to translate the corresponding region of the 
linear-address space, along with information about a ccess privileges. For example, bits 47:39 of a linear 
address would map to the address of the relevant page-directory-pointer table.
Linear mappings do not contain information from any EPT paging structure.
•Guest-physical mappings .2 There are two kinds:
— Guest-physical translations. Each of these is a mapping from a guest-physical page number to the physical 
page frame to which it translates, along with information about access privileges and memory typing.
— Guest-physical paging-structure-cache entries. Each of these is a mapping from the upper portion of a 
guest-physical address to the physical address of th e EPT paging structure used to translate the corre-
sponding region of the guest-physical address spac e, along with information about access privileges.
The information in guest-physical mappings about access privileges and memory typi ng is derived from EPT 
paging structures.
•Combined mappings .3 There are two kinds:
— Combined translations. Each of these is a mapping from a linear page number to the physical page frame 
to which it translates, along with information about access privileges and memory typing.
— Combined paging-structure-cache entries. Each of th ese is a mapping from the upper portion of a linear 
linear-address space, along with information about access privileges.
The information in combined mappings about access privil eges and memory typing is derived from both guest 
paging structures and EPT paging structures.
Guest-physical mappings and combined  mappings may also include SPP vectors and information about the data 
structures used to locate SPP vectors (see Section 29.3.4.2).
29.4.2 Creating and Using Ca ched Translation Information
The following items detail the creation of the mappings described in the previous section:4
•The following items describe the creation of mappings wh ile EPT is not in use (including execution outside VMX 
non-root operation):
— Linear mappings may be created. Th ey are derived from the paging structures referenced (directly or 
indirectly) by the current value of CR3 and are asso ciated with the current VPID and the current PCID.
— No linear mappings are created with information derive d from paging-structure entries that are not present 
(bit 0 is 0) or that set reserved bits. For example, if  a PTE is not present, no linear mapping are created for 
any linear page number whose translation would use that PTE.
— No guest-physical or combined mappings are created while EPT is not in use.
•The following items describe the creation of mappings while EPT is in use:
— Guest-physical mappings may be created. They are derived from the EPT paging structures referenced 
(directly or indirectly) by bits 51:12 of the current EP TP. These 40 bits contain the address of the EPT root 
1. Earlier versions of this manual used the te rm “VPID-tagged” to iden tify linear mappings.
2. Earlier versions of this manual used the term “EPTP-tagged” to identify guest-physical mappings.
3. Earlier versions of this manual used the term “dual-tagged” to identify combined mappings.
4. This section associated cached  information with the cu rrent VPID and PCID. If PCIDs are no t supported or are not being used ( e.g., 
because CR4.PCIDE = 0), all the information is implicitly associ ated with PCID 000H; see Section 4.10.1, “Process-Context Identi fiers 
(PCIDs),” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.29-22 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
table (a EPT PML4 table with 4-level EPT or a EPT PML5 table with 5-level EPT); the notation EPTRTA  refers 
to those 40 bits. Newly created guest-physical mappings are associated with the current EPTRTA.
— Combined mappings may be created. They are derived from the EPT paging structures referenced (directly 
or indirectly) by the current EPTRTA. If CR0.PG = 1, they are also derived from the paging structures 
referenced (directly or indirectly) by the current valu e of CR3. They are associated with the current VPID, 
the current PCID, and the current EPTRTA.1 No combined paging-structure-cache entries are created if 
CR0.PG = 0.2
— No guest-physical mappings or combined mappings ar e created with information derived from EPT paging-
structure entries that are not present (see Sectio n 29.3.2) or that are misconfigured (see Section 
29.3.3.1).
— No combined mappings are created with information de rived from guest paging-structure entries that are 
not present or that set reserved bits.
— No linear mappings are created while EPT is in use.
The following items detail the use of the various mappings:
•If EPT is not in use (e.g., when outside VMX non-root operation), a logical processor may use cached mappings 
— For accesses using linear addresses, it may use linear mappings associated with the current VPID and the 
current PCID. It may also use global TLB entries (linear mappings) associated with the current VPID and 
any PCID.
— No guest-physical or combined mappings are used while EPT is not in use.
•If EPT is in use, a logical processor may use cached mappings as follows:
— For accesses using linear addresses, it may use combined mappings associated with the current VPID, the 
current PCID, and the current EPTRTA. It may also us e global TLB entries (combined mappings) associated 
with the current VPID, the current EPTRTA, and any PCID.
— For accesses using guest-physical addresses, it may use guest-physical mappings associated with the 
current EPTRTA.

any PCID.
— No linear mappings are used while EPT is in use.
29.4.3 Invalidating Cached  Translation Information
Software modifications of paging structures (including EPT paging structures and the data structures used to locate 
SPP vectors) may result in inconsistencies between those structures and the mappings cached by a logical 
processor. Certain operations invalidate information cached by a logical processor and can be used to eliminate such inconsistencies.
29.4.3.1  Operations that Invalidate Cached Mappings
The following operations invalidate cached mappings as indicated:
•Operations that architecturally invalidate entries in th e TLBs or paging-structure caches independent of VMX 
operation (e.g., the INVLPG and INVPCID instructions) invalidate linear mappings and combined mappings.3 
They are required to do so only for the current VP ID (but, for combined mappings, all EPTRTAs). Linear 
1. At any given time, a logical processor may be caching combined mappings for a VPID and a PCID that are associated with differ ent 
EPTRTAs. Similarly, it may be caching combined mappings for an EPTRTA that are associated with different VPIDs and PCIDs.
2. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, CR0.PG can be 0 in VMX non-root 
both 1.
3. See Section 4.10.4, “Invalidation of TLBs and Paging-Structure Caches,” in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 3A, for an enumeration of operations that  architecturally invalidate entr ies in the TLBs and paging-struc ture 
caches independent of VMX operation.Vol. 3C 29-23VMX SUPPORT FOR ADDRESS TRANSLATION
mappings for the current VPID are invalidated even if EPT is in use.1 Combined mappings for the current 
VPID are invalidated even if EPT is not in use.2
•An EPT violation invalidates any guest-physical mappings (associated with the current EPTRTA) that would be used to translate the guest-physical address that caused  the EPT violation. If that guest-physical address was 
the translation of a linear address, the EPT violation al so invalidates any combined mappings for that linear 
address associated with the current PCID, the current VPID and the current EPTRTA.
•If the “enable VPID” VM-execution control is 0, VM entries and VM exits invalidate linear mappings and 
combined mappings associated with VPID 0000H (for all PCIDs). Combined mappings for VPID 0000H are 
invalidated for all EPTRTAs.
•Execution of the INVVPID instruction invalidates line ar mappings and combined mappings. Invalidation is 
based on instruction operands, called the INVVPID type  and the INVVPID descriptor. Four INVVPID types are 
currently defined:
—Individual-address.  If the INVVPID type is 0, the logical processor invalidates linear mappings and 
combined mappings associated with the VPID specifie d in the INVVPID descriptor and that would be used 
to translate the linear address specified in of th e INVVPID descriptor. Linear mappings and combined 
mappings for that VPID and linear address are invalidated for all PCID s and, for combined mappings, all 
EPTRTAs. (The instruction may also invalidate mapping s associated with other VPIDs and for other linear 
addresses.)
—Single-context.  If the INVVPID type is 1, the logical pr ocessor invalidates all linear mappings and 
combined mappings associated with the VPID specif ied in the INVVPID descriptor. Linear mappings and 
combined mappings for that VPID are invalidated for all PCIDs and, for combined  mappings, all EPTRTAs. 
(The instruction may also invalidate mappings associated with other VPIDs.)
—All-context.  If the INVVPID type is 2, the logical proc essor invalidates linear mappings and combined 
mappings associated with all VPIDs except VPID 00 00H and with all PCIDs. (The instruction may also 
invalidate linear mappings with VPID 0000H.) Co mbined mappings are invalidated for all EPTRTAs.
—Single-context-ret aining-globals.  If the INVVPID type is 3, the logical processor invalidates linear 
mappings and combined mappings associated with th e VPID specified in the INVVPID descriptor. Linear 
mappings and combined mappings for that VPID are in validated for all PCIDs and, for combined mappings, 
all EPTRTAs. The logical processor is not required to invalidate information that was used for global  trans-
lations (although it may do so). See Section 4.10, “C aching Translation Information,” for details regarding 
global translations. (The instruction may also invalidate mappings associated with other VPIDs.)
See Chapter 31 for details of the INVVPID instruction. Se e Section 29.4.3.3 for guidelines regarding use of this 
•Execution of the INVEPT instruction invalidates guest- physical mappings and combined mappings. Invalidation 
is based on instruction operands, called the INVEPT type and the INVEPT descriptor. Two INVEPT types are 
—Single-context.  If the INVEPT type is 1, the logical proce ssor invalidates all guest-physical mappings and 
combined mappings associated with the EPTRTA specifie d in the INVEPT descriptor. Combined mappings for 
that EPTRTA are invalidated for all VPIDs and a ll PCIDs. (The instruction may invalidate mappings 
associated with other EPTRTAs.)
—All-context.  If the INVEPT type is 2, the logical proc essor invalidates guest-physical mappings and 
combined mappings associated with all EPTRTAs (and , for combined mappings, for all VPIDs and PCIDs).
See Chapter 31 for details of the INVEPT instruction. Se e Section 29.4.3.4 for guidelines regarding use of this 
•A power-up or a reset invalidates all linear mappings, guest-physical mappings, and combined mappings.
1. While no linear mappings are created while EPT is in use, a logical processor may retain, while EPT is in use, linear mapping s (for the 
same VPID as the current one) there were created earlier, when EPT was not in use.
2. While no combined mappings are created while EPT is not in use, a logical processor may retain, while EPT is in not use, comb ined 
mappings (for the same VP ID as the current one) there were created earlier, when EPT was in use.29-24 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
29.4.3.2  Operations that Need  Not Invalidate Cached Mappings
The following items detail cases of operations that ar e not required to invalidate certain cached mappings:
operation are not required to invalidate any guest-physical mappings.
•The INVVPID instruction is not required to invalidate any guest-physical mappings.
•The INVEPT instruction is not required to invalidate any linear mappings.
•VMX transitions are not required to invalidate any guest-physical mappings. If the “enable VPID” VM-execution control is 1, VMX transitions are not required to invalidate any linear mappings or combined mappings. 
•The VMXOFF and VMXON instructions are not required to  invalidate any linear mappings, guest-physical 
mappings, or combined mappings.
A logical processor may invalidate any cached mappings at any time. For this reason, the operations identified 
above may invalidate the indicated mappings despite the fact that doing so is not required.
29.4.3.3  Guidelines for Use of the INVVPID Instruction
The need for VMM software to use the INVVPID instructio n depends on how that software is virtualizing memory. 
If EPT is not in use, it is likely that the VMM is virtua lizing the guest paging structures. Such a VMM may configure 
the VMCS so that all or some of the operations that in validate entries the TLBs and the paging-structure caches 
(e.g., the INVLPG instruction) cause VM exits. If VMM soft ware is emulating these operations, it may be necessary 
to use the INVVPID instruction to ensure that the logical processor’s TLBs and the paging-structure caches are appropriately invalidated.
Requirements of when software should use the INVVPID instruction depend on the specific algorithm being used for 
page-table virtualization. The following items provide guidelines for software developers:
•Emulation of the INVLPG instruction may require execution of the INVVPID instruction as follows:
— The INVVPID type is individual-address (0).— The VPID in the INVVPID descriptor is the one assign ed to the virtual processor whose execution is being 
emulated.
— The linear address in the INVVPID descriptor is th at of the operand of the INVLPG instruction being 
emulated.
•Some instructions invalidate all entries in the TLBs an d paging-structure caches—except for global translations. 
An example is the MOV to CR3 instruction. (See Sectio n 4.10, “Caching Translation Information,” in the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for details regarding global translations.)

emulated.
emulated.
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for details regarding global translations.) 
Emulation of such an instruction may require ex ecution of the INVVPID instruction as follows:
— The INVVPID type is single-context-retaining-globals (3).
— The VPID in the INVVPID descriptor is the one assign ed to the virtual processor whose execution is being 
emulated.
•Some instructions invalidate all entries in the TLBs an d paging-structure caches—including for global transla-
tions. An example is the MOV to CR4 instruction if th e value of value of bit 4 (page global enable—PGE) is 
changing. Emulation of such an instruction may requ ire execution of the INVVPID instruction as follows:
— The INVVPID type is single-context (1).— The VPID in the INVVPID descriptor is the one assign ed to the virtual processor whose execution is being 
emulated.
If EPT is not in use, the logical processor associates all mappings it creates with the current VPID, and it will use 
such mappings to translate linear addresses. For that re ason, a VMM should not use the same VPID for different 
non-EPT guests that use different page tables. Doing so ma y result in one guest using translations that pertain to 
the other.
If EPT is in use, the instructions enumerated above might not be configured to cause VM exits and the VMM might 
not be emulating them. In that case, executions of the instructions by guest software properly invalidate the Vol. 3C 29-25VMX SUPPORT FOR ADDRESS TRANSLATION
required entries in the TLBs and paging-structure caches  (see Section 29.4.3.1); execution of the INVVPID instruc-
tion is not required.
If EPT is in use, the logical processor associates all mapping s it creates with the value of bits 51:12 of current EPTP. 
If a VMM uses different EPTP values for different guests, it may use the same VPID for those guests. Doing so cannot result in one guest using translations that pertain to the other.
The following guidelines apply more generally and are appropriate even if EPT is in use:
•As detailed in Section 30.4.5, an access to the APIC-access page might not cause an APIC-access VM exit if 
software does not properly invalidate information that may be cached from the paging structures. If, at one 
time, the current VPID on a logical processor was a non-zero value X, it is recommended that software use the 
INVVPID instruction with the “single-context” INVVPID ty pe and with VPID X in the INVVPID descriptor before 
a VM entry on the same logical processor that establishe s VPID X and either (a) the “virtualize APIC accesses” 
VM-execution control was changed from 0 to 1; or (b) the value of the APIC-access address was changed.
•Software can use the INVVPID instruction with the “all- context” INVVPID type immediately after execution of 
the VMXON instruction or immediately prior to execution of  the VMXOFF instruction. Either prevents potentially 
undesired retention of information cached from paging  structures between separate uses of VMX operation.
29.4.3.4  Guidelines for Use of the INVEPT Instruction
The following items provide guidelines for use of the INVEPT  instruction to invalidate information cached from the 
EPT paging structures.
•Software should use the INVEPT instruction with the “s ingle-context” INVEPT type  after making any of the 
following changes to an EPT paging-structure entry (the  INVEPT descriptor should contain an EPTP value that 
references — directly or indirectly — the modified EPT paging structure):
— Changing any of the privilege bits 2:0 from 1 to 0.1
— Changing the physical address in bits 51:12.— Clearing bit 8 (the accessed flag) if accessed and dirty flags for EPT will be enabled.— For an EPT PDPTE or an EPT PDE, changing bit 7 (which determines whether the entry maps a page).
—F o r  t h e  last EPT paging-structure entry used to translate a guest-physical address (an EPT PDPTE with bit 7 
set to 1, an EPT PDE with bit 7 set to 1, or an EP T PTE), changing either bits 5:3 or bit 6. (These bits 
determine the effective memory type of accesses us ing that EPT paging-structure entry; see Section 
29.3.7.)
set to 1, an EPT PDE with bit 7 set to 1, or an EPT PT E), clearing bit 9 (the dirty flag) if accessed and dirty 
flags for EPT will be enabled.
•Software should use the INVEPT instruction with the “s ingle-context” INVEPT type before a VM entry with an 
EPTP value X such that X[6] = 1 (accessed and dirty flag s for EPT are enabled) if the logical processor had 
earlier been in VMX non-root operation with an EPTP value Y such that Y[6] = 0 (accessed and dirty flags for 
EPT are not enabled) and Y[51:12] = X[51:12].
EPTP value X if the logical processor had earlier been in VMX non-root operation with an EPTP value Y such that 
Y[5:3] ≠ X[5:3] (different EPT page-walk length) and Y[51:12] = X[51:12].
•Software may use the INVEPT instru ction after modifying a present EPT paging-structure entry (see Section 
29.3.2) to change any of the privilege bits 2:0 from 0 to 1.2 Failure to do so may cause an EPT violation that 
would not otherwise occur. Because an EPT violation invalidates any mappings that would be used by the access that caused the EPT violation (see Section 29.4.3.1), an EPT violation will not recur if the original access 
is performed again, even if the INVEPT instruction is not executed.
1. If the “mode-based execute control for EPT” VM-execution contro l is 1, software should use th e INVEPT instruct ion after chang ing 
privilege bit 10 from 1 to 0.
2. If the “mode-based execute control for EPT” VM-execution control is 1, software may use the INVEPT instruction after modifyin g a 
present EPT paging-structure entry to change privilege bit 10 from 0 to 1.29-26 Vol. 3CVMX SUPPORT FOR ADDRESS TRANSLATION
•Because a logical processor does not cache any informatio n derived from EPT paging-s tructure entries that are 
not present (see Section 29.3.2) or misconfigured (see Sect ion 29.3.3.1), it is not necessary to execute INVEPT 
following modification of an EPT paging-structure entry that had been not present or misconfigured.
software does not properly invalidate information that may be cached from the EPT paging structures. If EPT 
was in use on a logical processor at one time with EPTP  X, it is recommended that software use the INVEPT 
instruction with the “single-context” INVEPT type and with EPTP X in th e INVEPT descriptor before a VM entry 
on the same logical processor that enables EPT with EP TP X and either (a) the “virtualize APIC accesses” VM-
execution control was changed from 0 to 1; or (b) the value of the APIC-access address was changed.
•Software can use the INVEPT instruction with the “all-c ontext” INVEPT type immediately after execution of the 
VMXON instruction or immediately prior to execution of  the VMXOFF instruction. Either prevents potentially 
undesired retention of information cached from EPT paging structures between separate uses of VMX 
In a system containing more than one logical processor, software must account for the fact that information from 
an EPT paging-structure entry may be cached on logical processors other than the one that modifies that entry. The process of propagating the changes to a paging-structure  entry is commonly referred to as “TLB shootdown.” A 
discussion of TLB shootdown appears in  Section 4.10.5, “Propagation of Paging-Structure Changes to Multiple 
Processors,” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Vol. 3C 30-1CHAPTER 30
The VMCS includes controls that enable the virtualizati on of interrupts and the Advanced Programmable Interrupt 
Controller (APIC).
When these controls are used, the processor will emulate many accesses to the APIC, track the state of the virtual 
APIC, and deliver virtual interrupts — all in VMX non-root operation with out a VM exit.1
The processor tracks the state of the virtual APIC using a virtual-APIC page identified by the virtual-machine 
monitor (VMM). Section 30.1 discusses the virtual-APIC page and how the processor uses it to track the state of the 
virtual APIC.
The following are the VM-execution controls relevant to APIC virtualization and virtual interrupts (see Section 25.6 
for information about the locations of these controls):
•Virtual-interrupt delivery.  This control enables the evaluation and delivery of pending virtual interrupts 
(Section 30.2). It also enables the emulation of writ es (memory-mapped or MSR-based, as enabled) to the 
APIC registers that control interrupt prioritization.
•Use TPR shadow.  This control enables emulation of accesses to the APIC’s task-priority register (TPR) via CR8 
(Section 30.3) and, if enabled, via th e memory-mapped or MSR-based interfaces.

•Virtualize APIC accesses.  This control enables virtualization of memory-mapped accesses to the APIC 
(Section 30.4) by causing VM exits on accesses to a VMM-specified APIC-access page. Some of the other 
controls, if set, may cause some of these accesse s to be emulated rather than causing VM exits.
•Virtualize x2APIC mode.  This control enables virtualization of MSR-based accesses to the APIC (Section 
30.5).
•APIC-register virtualization.  This control allows memory-mapped and MSR-based reads of most APIC 
registers (as enabled) by satisfying them from the virt ual-APIC page. It directs memory-mapped writes to the 
APIC-access page to the virtual-APIC page, fo llowing them by VM exits for VMM emulation.
•Process posted interrupts.  This control allows software to post virtual interrupts in a data structure and send 
a notification to another logical processor; upon receipt of the notification, the target processor will process the 
posted interrupts by copying them into the virtual-APIC page (Section 30.6).
•IPI virtualization.  This control enables the virtualization of  interprocessor interrupts (Section 30.1.6).
“Virtualize APIC accesses”, “virtualize x2APIC mode”, “virtu al-interrupt delivery”, and “APIC-register virtualization” 
are all secondary processor-based VM-execution controls; if bit 31 of the primary processor-based VM-execution 
controls is 0, the processor operates as if these controls we re all 0. “IPI virtualization” is a tertiary processor-based 
VM-execution control; if bit 17 of the primary processor-based VM-execution controls is 0, the processor operates 
as if “IPI virtualization” were 0. See Section 25.6.2.
30.1 VIRTUAL APIC STATE
The virtual-APIC page  is a 4-KByte region of memory that the proc essor uses to virtualize certain accesses to 
APIC registers and to manage virtual interrupts. The physical address of the virtual-APIC page is the virtual-APIC 
address , a 64-bit VM-execution control field in the VMCS (see Section 25.6.8).
Depending on the settings of certain VM-execution contro ls, the processor may virtualize certain fields on the 
virtual-APIC page with functionality analogous to that pe rformed by the local APIC. Section 30.1.1 identifies and 
defines these fields. Section 30.1.2, Section 30.1.3, Section 30.1.4, and Section 30.1.5 detail the actions taken to 
virtualize updates to some of these fields.
With the exception of fields corresponding to virtualized APIC registers (defined in Section 30.1.1), software may 
modify the virtual-APIC page referenc ed by the current VMCS of a logical processor in VMX non-root operation. 
(This is an exception to the general requirement given in Section 25.11.4.)
1. In most cases, it is not necessary fo r a virtual-machine monitor (VMM) to inject virtual interrupts as part of VM entry.30-2 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
30.1.1 Virtualized APIC Registers
Depending on the setting of certain VM-execution controls, a logical processor may virtualize certain accesses to 
APIC registers using the following fields on the virtual-APIC page:
•Virtual task-priorit y register (VTPR) : the 32-bit field located at offset 080H on the virtual-APIC page.
•Virtual processor-prior ity register (VPPR) : the 32-bit field located at offset 0A0H on the virtual-APIC 
page.
•Virtual end-of-interrupt register (VEOI) : the 32-bit field located at offset 0B0H on the virtual-APIC page.
•Virtual interrupt-service register (VISR) : the 256-bit value comprising eight non-contiguous 32-bit fields 
at offsets 100H, 110H, 120H, 130H, 140H, 150H, 160H, and 170H on the virt ual-APIC page. Bit x of the VISR 
is at bit position (x & 1FH) at offset (100H | ((x & E0H) » 1)). The processor uses on ly the low 4 bytes of each 
of the 16-byte fields at offsets 100H, 110H, 120H, 130H, 140H , 150H, 160H, and 170H.
•Virtual interrupt-request register (VIRR) : the 256-bit value comprising eight non-contiguous 32-bit fields 
at offsets 200H, 210H, 220H, 230H, 240H, 250H, 260H, and 270H on the virt ual-APIC page. Bit x of the VIRR 
is at bit position (x & 1FH) at offset (200H | ((x & E0H) » 1)). The processor uses on ly the low 4 bytes of each 
of the 16-Byte fields at offsets 200H, 210 H, 220H, 230H, 240H, 25 0H, 260H, and 270H.
•Virtual interrupt-command register (VICR_LO) : the 32-bit field located at offset 300H on the virtual-APIC 
page.
•Virtual interrupt-command register (VICR_HI) : the 32-bit field located at offset 310H on the virtual-APIC 
page.
The VTPR field virtualizes the TPR whenever the “use TPR sh adow” VM-execution control is 1. The other fields indi-
cated above virtualize the corresponding APIC registers whenever the “virtual-interrupt delivery” VM-execution 
control is 1. (VICR_LO and VICR_HI also virtualize the ICR when the “IPI virtualization” VM-execution control is 1.)
30.1.2 TPR Virtualization
The processor performs TPR virtualization  in response to the following operations: (1) virtualization of the MOV 
to CR8 instruction; (2) virtualization of a write to offset  080H on the APIC-access page; and (3) virtualization of the 
WRMSR instruction with ECX = 808H. See Section 30.3, Sect ion 30.4.3, and Section 30.5 for details of when TPR 
virtualization is performed.
The following pseudocode details the behavior of TPR virtualization:
IF “virtual-interrupt delivery” is 0
THEN
IF VTPR[7:4] < TPR threshold (see Section 25.6.8)
THEN cause VM exit due to TPR below threshold;
FI;
ELSE
perform PPR virtualization (see Section 30.1.3);evaluate pending virtual interrupts (see Section 30.2.1);
FI;
Any VM exit caused by TPR virtualization is trap-like: the instruction causing TPR virtualization completes before 
the VM exit occurs (for example, the va lue of CS:RIP saved in the guest-state area of the VMCS references the next 
instruction).
30.1.3 PPR Virtualization
The processor performs PPR virtualization  in response to the following operations: (1) VM entry; (2) TPR virtu-
alization; and (3) EOI virtualization. See Section 27.3.2.5,  Section 30.1.2, and Section 30.1.4 for details of when 
PPR virtualization is performed.
PPR virtualization uses the guest interrupt status (speci fically, SVI; see Section 25.4.2) and VTPR. The following 
pseudocode details the behavior of PPR virtualization:
IF VTPR[7:4] ≥ SVI[7:4]Vol. 3C 30-3APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
THEN VPPR := VTPR & FFH;
ELSE VPPR := SVI & F0H;
FI;
PPR virtualization always clears bytes 3:1 of VPPR.
PPR virtualization is caused only by TPR virtualization, EO I virtualization, and VM entry. Delivery of a virtual inter-
rupt also modifies VPPR, but in a different way (see Sectio n 30.2.2). No other operations modify VPPR, even if they 
modify SVI, VISR, or VTPR.
30.1.4 EOI Virtualization
The processor performs EOI virtualization  in response to the following operat ions: (1) virtualization of a write to 
offset 0B0H on the APIC-access page; and (2) virtualiz ation of the WRMSR instruction with ECX = 80BH. See 
Section 30.4.3 and Section 30.5 for details of when EOI virt ualization is performed. EOI virtualization occurs only 
if the “virtual-interrupt delivery” VM-execution control is 1.
EOI virtualization uses and updates the guest interrupt status  (specifically, SVI; see Section 25.4.2). The following 
pseudocode details the behavior of EOI virtualization:
Vector := SVI;
VISR[Vector] := 0; (see Section 30.1.1 for definition of VISR)IF any bits set in VISR
THEN SVI := highest in dex of bit set in VISR
ELSE SVI := 0;
FI;perform PPR virtualiation (see Section 30.1.3);IF EOI_exit_bitmap[Vector] = 1 (see Section 25.6.8 for definition of EOI_exit_bitmap)
THEN cause EOI-induced VM exit with Vector as exit qualification;ELSE evaluate pending virtual interrupts; (see Section 30.2.1)
FI;
Any VM exit caused by EOI virtualization is trap-like: th e instruction causing EOI virtualization completes before 
30.1.5 Self-IPI Virtualization
The processor performs self-IPI virtualization  in response to the following operations: (1) virtualization of a 
write to offset 300H on the APIC-access page; and (2) vir tualization of the WRMSR in struction with ECX = 83FH. 
See Section 30.4.3 and Section 30.5 for details of when self -IPI virtualization is performed. Self-IPI virtualization 
occurs only if the “virtual-interrupt delivery” VM-execution control is 1.
Each operation that leads to self-IPI virtualization provid es an 8-bit vector (see Section 30.4.3 and Section 30.5). 
Self-IPI virtualization updates the guest interrupt status  (specifically, RVI; see Section 25.4.2). The following 
pseudocode details the behavior  of self-IPI virtualization:
VIRR[Vector] := 1; (see Section 30.1.1 for definition of VIRR)
RVI := max{RVI,Vector};evaluate pending virtual interrupts; (see Section 30.2.1)
30.1.6 IPI Virtualization

The processor performs IPI virtualization  in response to the following operations: (1) virtualization of a write to 
offset 300H on the APIC-access page (Section 30.4.3); (2) virtualization of the WRMSR instruction with ECX = 
830H (Section 30.5); and (3) virtualization of some execut ions of SENDUIPI (Section 30.7). IPI virtualization 
occurs only if the “IPI virtualization” VM-execution control is 1.30-4 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
Each operation that leads to IPI virtualization provides an 8-bit virtual vector V and a 32-bit virtual APIC ID T. IPI 
virtualization uses those values to initiate the indicated virtual IPI using the PID-pointer table. (Recall that the PID-pointer table address is a field in the VMCS, as is the last PID-pointer index.)
Specifically, the CPU uses the virtual APIC ID to select an  entry from the PID-pointer table. It uses the address in 
that entry to locate a posted-interrupt descriptor (PID) and then posts a virtual interrupt with vector V in that PID. 
The following pseudocode details the behavior of self-IPI virtualization:
IF V < 16
THEN APIC-write VM ex it; // illegal vector
ELSE IF T ≤
 last PID-pointer index
THEN
PID_ADDR := 8 bytes at (PID-pointer table address + (T « 3));IF PID_ADDR sets bits beyond the processor’s physical-address width OR
PID_ADDR[5:0]
 ≠ 000001b // PID pointer not valid or reserved bits set
THEN APIC-write VM exit; // See Section 30.4.3.3ELSE
PIR := 32 bytes at PID_ADDR; // under lockPIR[V] := 1;store PIR at PID_ADDR; // release lockNotifyInfo := 8 bytes at PI D_ADDR + 32; // under lock
IF NotifyInfo.ON = 0 AND NotifyInfo.SN = 0
THEN
NotifyInfo.ON := 1;SendNotify := 1;
ELSE SendNotify := 0;
FI;store NotifyInfo at PID_A DDR + 32;  // release lock
IF SendNotify = 1
THEN send an IPI specified by NotifyInfo.NDST and NotifyInfo.NV;
FI;
FI;
ELSE APIC-write VM exit; // virtual APIC ID beyond end of tables
FI;
The sending of the notification IPI is indicated by fi elds in the selected PID: NDST (PID[319:288]) and NV 
(PID[279:272]):
•If the local APIC is in xAPIC mode, this is the IPI that would be generated by writing NDST[15:8] 
(PID[303:296]) to ICR_HI[31:24] (offset 310H from IA 32_APIC_BASE) and then writing NV to ICR_LO (offset 
300H from IA32_APIC_BASE).
•If the local APIC is in x2APIC mode, this is the IPI that would be generated by executing WRMSR with ECX = 
830H (ICR), EAX = NV, and EDX = NDST.
If the pseudocode specifies an APIC-write  VM exit, this VM exit occurs as if  there had been a write access to page 
offset 300H on the APIC-access page (see Section 30.4.3.3).
30.2 EVALUATION AND DELIVE RY OF VIRTUAL INTERRUPTS
If the “virtual-interrupt delivery” VM-execution control is  1, certain actions in VMX non-root operation or during 
VM entry cause the processor to evaluate and deliver virtual interrupts.
Evaluation of virtual interrupts is tri ggered by certain actions change the st ate of the virtual-APIC page and is 
described in Section 30.2.1. This evaluation may result in recognition of a virtual interrupt. Once a virtual interrupt 
is recognized, the processor may deliver it within VMX non-root operation without a VM exit. Virtual-interrupt 
delivery is described in Section 30.2.2.
30.2.1 Evaluation of Pending Virtual Interrupts
If the “virtual-interrupt delivery” VM-execution control is 1, certain actions cause a logical processor to evaluate 
pending virtual interrupts .
The following actions cause the evaluation of pending virtual interrupts: VM entry; TPR virtualization; EOI virtual-
ization; self-IPI virtualization; and posted-interrupt processing. See Section 27.3.2.5, Section 30.1.2, Section Vol. 3C 30-5APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
30.1.4, Section 30.1.5, and Section 30.6 for details of when  evaluation of pending virtual interrupts is performed. 
No other operations cause the evaluation of pending vi rtual interrupts, even if they modify RVI or VPPR.
Evaluation of pending virtual interrupts uses the guest inte rrupt status (specifically, RVI; see Section 25.4.2). The 
following pseudocode details the evaluation of pending virtual interrupts:
IF “interrupt-window exiting” is 0 AND
RVI[7:4] > VPPR[7:4] (see Section 30.1.1 for definition of VPPR)
THEN recognize a pending virtual interrupt;
ELSE
do not recognize a pending virtual interrupt;
FI;
Once recognized, a virtual interrupt may be deliver ed in VMX non-root operation; see Section 30.2.2.
Evaluation of pending virtual interrupts is caused only by VM entry, TPR virtualization, EOI virtualization, self-IPI 
virtualization, and posted-interrupt processing. No other op erations do so, even if they modify RVI or VPPR. The 
logical processor ceases recognition of a pending virtual interrupt following the delivery of a virtual interrupt.
30.2.2 Virtual-Interrupt Delivery
If a virtual interrupt has been recognized (see Section 30.2 .1), it is delivered at an instruction boundary when the 
following conditions all hold: (1) RFLAGS.IF = 1; (2) there is no blocking by STI; (3) there is no blocking by MOV SS or by POP SS; and (4) the “interrupt-w indow exiting” VM-execution control is 0.
Virtual-interrupt delivery has the same priority as that of VM exits due to the 1-setting of the “interrupt-window 
exiting” VM-execution control.
2 Thus, non-maskable interrupts (NMIs) and higher priority events take priority over 
delivery of a virtual interrupt; delivery of a virtual interrupt takes priority over external interrupts and lower priority 
events.
Virtual-interrupt delivery wakes a logical processor from the same inactive activity states as would an external 
interrupt. Specifically, it wakes a logical processor from the states entered using the HLT and MWAIT instructions. It does not wake a logical processor in the shutdown state or in the wait-for-SIPI state.
Virtual-interrupt delivery updates the guest interrupt stat us (both RVI and SVI; see Section 25.4.2) and delivers 
an event within VMX non-root operation without a VM ex it. The following pseudocode details the behavior of 
virtual-interrupt delivery (see Section 30.1.1 for definition of VISR, VIRR, and VPPR):
Vector := RVI;
VISR[Vector] := 1;SVI := Vector;VPPR := Vector & F0H;VIRR[Vector] := 0;IF any bits set in VIRR
THEN RVI := highest index of bit set in VIRRELSE RVI := 0;
FI;cease recognition of any pending virtual interrupt;IF transactional execution is in effect
THEN abort transactional execution and tran sition to a non-tran sactional execution;
FI;IF logical processor is in enclave mode
THEN cause an Asynchronous Enclave Exit (AEX ) (see Chapter 37, “Enc lave Exiting Events”)
FI;IF CR4.UINTR = 1 AND IA32_EFER.LMA = 1 AND Vector = UINV
THEN virtualize user-interrupt notification id entification and processing (see Section 30.2.3)
ELSE deliver interrupt with Vector through IDT;
2. A logical processor never recognizes or delivers a virtual inte rrupt if the “interrupt-window ex iting” VM-execution control i s 1. 
Because of this, the relative priority of virtual-interrupt delive ry and VM exits due to the 1-se tting of that control is not d efined.30-6 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
FI;
30.2.3 Virtualizing User-Interrupt Notifications
Section 7.5 describes the process of user-interrupt notifica tion identification and processing. If the “virtual-inter-
rupt delivery” VM-execution control is 1, this process is modified as described in  the following paragraphs.
The virtualized form of user-interrupt notification identi fication begins as described in Section 30.2.2. Following 
this, instead of writing zero to the EOI register in the lo cal APIC, the logical processor performs the initial steps of 
EOI virtualization:
VISR[V] := 0;
IF any bit is set in VISR
THEN SVI := highest index of bit set in VISRELSE SVI := 0;
FI;perform PPR virtualization (Section 30.1.3);
Unlike EOI virtualization resulting from a guest write to the EOI register (as defined for virtual-interrupt delivery), 
the logical processor does not check the EOI-exit bitmap as part of this modified form of user-interrupt notification identification, and the corresponding VM exits cannot occur.
Following this modified form of user-interrupt notification  identification, the logical processor then performs user-
interrupt notification processing as specified in Section 7.5.2.
A logical processor is not interruptible during this modified  form of user-interrupt notification identification or 
between it and any subsequent user-i nterrupt notification processing.
If the user-interrupt notification identification that prec edes user-interrupt notification processing occurred while 
the logical processor was in the HLT state, the logical processor returns to the HLT state following user-interrupt notification processing.
30.3 VIRTUALIZING CR8-BASED TPR ACCESSES
In 64-bit mode, software can access the local APIC’s task-p riority register (TPR) through CR8. Specifically, software 
uses the MOV from CR8 and MOV to CR8 instructions (see Section 11.8.6, “Task Priority in IA-32e Mode”). This

uses the MOV from CR8 and MOV to CR8 instructions (see Section 11.8.6, “Task Priority in IA-32e Mode”). This 
section describes how these accesses can be virtualized.
A virtual-machine monitor can virtualize these CR8-based APIC accesses by setting the “CR8-load exiting” and 
“CR8-store exiting” VM-execution controls, ensuring that  the accesses cause VM exits (see Section 26.1.3). Alter-
natively, there are methods for virtualizing some CR8-based APIC accesses without VM exits.
Normally, an execution of MOV from CR8 or MOV to CR8 that does not fault or cause a VM exit accesses the APIC’s 
TPR. However, such an execution are treated specially if  the “use TPR shadow” VM-execution control is 1. The 
following items provide details:
•MOV from CR8.  The instruction loads bits 3:0 of its destination operand with bits 7:4 of VTPR (see Section 
30.1.1). Bits 63:4 of the destination operand are cleared.
•MOV to CR8.  The instruction stores bits 3:0 of its source oper and into bits 7:4 of VTPR; the remainder of VTPR 
(bits 3:0 and bits 31:8) are cleared. Following this, th e processor performs TPR virtualization (see Section 
30.1.2).
30.4 VIRTUALIZING MEMORY-MAPPED APIC ACCESSES
When the local APIC is in xAPIC mode, software accesses the local APIC’s control registers using a memory-mapped 
interface. Specifically, software uses linear addresses that  translate to physical addresses on page frame indicated 
by the base address in the IA32_APIC_BASE MSR (see Se ction 11.4.4, “Local APIC Status and Location”). This 
section describes how these accesses can be virtualized.Vol. 3C 30-7APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
A virtual-machine monitor (VMM) can virtualize these me mory-mapped APIC accesses by ensuring that any access 
to a linear address that would access the local APIC instea d causes a VM exit. This could be done using paging or 
the extended page-table mechanism (EPT ). Another way is by using the 1-setti ng of the “virtualize APIC accesses” 
If the “virtualize APIC accesses” VM-execution control is 1, the logical processor treats specially memory accesses 
using linear addresses that translate to physical addresses in the 4-KByte APIC-access page .3,4 (The APIC-
access page is identified by the APIC-access address , a field in the VMCS; see Section 25.6.8.)
In general, an access to the APIC-access page causes an APIC-access VM exit . APIC-access VM exits provide a 
VMM with information about the access causing the VM ex it. Section 30.4.1 discusses the priority of APIC-access 
VM exits.
Certain VM-execution controls enable the processor to virtualize certain accesses to the APIC-access page without 
a VM exit. In general, this virtualization causes these acce sses to be made to the virtual-APIC page instead of the 
APIC-access page.
NOTES
Unless stated otherwise, this section characterizes only linear accesses to the APIC-access page; 
an access to the APIC-access page is a linear access if (1) it results from a memory access using a linear address; and (2) the access’s physical address is the translation of that linear address. 
Section 30.4.6 discusses accesses to the APIC-access page that are not linear accesses.
The distinction between the APIC-access page and the virtual-APIC page allows a VMM to share 
paging structures or EPT paging structures among the virtual processors of a virtual machine (the 
shared paging structures referencing the same AP IC-access address, which appears in the VMCS of 
all the virtual processors) while giving each virtual processor its own virtual APIC (the VMCS of each 
virtual processor will have a unique virtual-APIC address).
Section 30.4.2 discusses when and how the processor may virtualize read accesses from the APIC-access page. 
Section 30.4.3 does the same for write accesses. When virtualizing a write to the APIC-access page, the processor 
typically takes actions in addition to passing the write through to the virtual-APIC page.
The discussion in those sections uses the concept of an operation within which these memory accesses may occur. 
For those discussions, an “operation” can be an iteration of  a REP-prefixed string instruction, an execution of any 
other instruction, or delivery of an event through the IDT.
The 1-setting of the “virtualize APIC accesses” VM-execu tion control may also affect accesses to the APIC-access 
page that do not result directly from linear  addresses. This is discussed in Section 30.4.6.
39.5.3 for details.
30.4.1 Priority of APIC-Access VM Exits
The following items specify the priority of APIC-access VM exits relative to other events.
•The priority of an APIC-access VM exit due to a memory a ccess is below that of any page fault or EPT violation 
that that access may incur. That is, an access does not cause an APIC-access VM exit if it would cause a page 
fault or an EPT violation.
3. Even when addresses are translated using EPT (see Section 29.3), the determination of whether an APIC-access VM exit occurs 
depends on an access’s physical address, not its guest-physical address. Even when CR0.PG = 0, or dinary memory ac cesses by soft-
ware use linear addresses; the fact that CR0.PG = 0 means only th at the identity translation is us ed to convert linear addresses  to 
physical (or guest-physical) addresses.
4. If EPT is enabled and there is write to a guest-physical addres s that translates to an address on the APIC-access page that i s eligible 
for sub-page write permissions (see Section 29.3.4.1), the proces sor may treat the write as if th e “virtualize APIC accesses” V M-exe-
cution control were 0 (and  not apply the treatment specified in this section). For that reason , it is recommended that software  not 
configure any guest-physical address that translates to an address on the APIC-access page to be eligible for sub-page write pe rmis-
sions.30-8 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•A memory access does not cause an APIC-access VM exit until after the accessed flags are set in the paging 
structures (including EPT paging structures, if enabled).
•A write access does not cause an APIC-access VM exit until after the dirty flags are set in the appropriate paging structure and EPT paging structure (if enabled).
•With respect to all other events, any APIC-access VM exit due to a memory access has the same priority as any 
page fault or EPT violation that the access could cause. (This item applies to other events that the access may 
generate as well as events that may be genera ted by other accesses by the same operation.)
These principles imply, among other things, that an APIC-access VM exit may occur during the execution of a 
repeated string instruction (including INS an d OUTS). Suppose, for example, that the first n iterations ( n may be 
0) of such an instruction do not access the APIC-access page and that the next iteration does access that page. As 
a result, the first n iterations may complete and be followed by an APIC-access VM exit. The instruction pointer 
saved in the VMCS references the repeated string inst ruction and the values of the general-purpose registers 
reflect the completion of n iterations.
30.4.2 Virtualizing Reads from the APIC-Access Page
A read access from the APIC-access page causes an APIC-access VM exit if any of the following are true:
•The “use TPR shadow” VM-execution control is 0.
•The access is for an instruction fetch.
•The access is more than 32 bits in size.
•The access is part of an operation for which the proce ssor has already virtualized a write to the APIC-access 
page.
•The access is not entirely contained within the low 4 byte s of a naturally aligned 16-byte region. That is, bits 
3:2 of the access’s address are 0, and the same is true of the address of the highest byte accessed.
If none of the above are true, whether a read access is virtualized depends on the setting of the “APIC-register 
virtualization” and “virtual-interrupt delivery” VM-execution controls:
•A read access is virtualized if its page offset is 080 H (task priority) regardless of the settings of the “APIC-
register virtualization” and “virtual-int errupt delivery” VM-execution controls.
•If the “virtual-interrupt delivery” VM-execution control is 1,  a read access is virtualized if its page offset is 0B0H 
(end of interrupt) or 300H (interrupt command — low).
•If “APIC-register virtualization” is 1, a read access is virt ualized if it is entirely within one the following ranges 
of offsets:
— 020H–023H (local APIC ID);— 030H–033H (local APIC version);
— 080H–083H (task priority);
— 0B0H–0B3H (end of interrupt);— 0D0H–0D3H (logical destination);
— 0E0H–0E3H (destination format);
— 0F0H–0F3H (spurious-interrupt vector);— 100H–103H, 110H–113H, 120H–123H, 130H–133H, 140H–143H, 150H–153H, 160H–163H, or 170H–
173H (in-service);
— 180H–183H, 190H–193H, 1A0H–1A3H, 1B0H–1B3H, 1C 0H–1C3H, 1D0H–1D3H, 1E0H–1E3H, or 1F0H–
1F3H (trigger mode);
— 200H–203H, 210H–213H, 220H–223H, 230H–233H, 240H–243H, 250H–253H, 260H–263H, or 270H–
273H (interrupt request);
— 280H–283H (error status);

— 300H–303H or 310H–313H (interrupt command);Vol. 3C 30-9APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
— 320H–323H, 330H–333H, 340H–343H, 350H–353H, 360H–363H, or 370H–373H (LVT entries);
— 380H–383H (initial count); or
— 3E0H–3E3H (divide configuration).
In all other cases, the access causes an APIC-access VM exit.
A read access from the APIC-access page that is virtualized returns data from the corresponding page offset on the 
virtual-APIC page.5
30.4.3 Virtualizing Writes  to the APIC-Access Page
Whether a write access to the APIC-access page is virtualized  depends on the settings of the VM-execution controls 
and the page offset of the access. Section 30.4.3.1 details when APIC-write virtualization occurs.
Unlike reads, writes to the local APIC have side effects; because of this, virtualization of writes to the APIC-access 
page may require emulation specific to the access’s page offset (which identifies the APIC register being accessed). 
Section 30.4.3.2 describes this APIC-write emulation .
For some page offsets, it is necessary for software to co mplete the virtualization after a write completes. In these 
cases, the processor causes an APIC-write VM exit  to invoke VMM software. Se ction 30.4.3.3 discusses APIC-
write VM exits.
30.4.3.1  Determining Whether a Write Access is Virtualized
A write access to the APIC-access page causes an APIC-access VM exit if any of the following are true:
•The access is part of an operation for which the processor has already virtualized a write (with a different page 
offset or a different size) to the APIC-access page.
If none of the above are true, whether a write access is virtualized depends on the settings of the “APIC-register 
virtualization”, “virtual-interrupt delivery”, an d “IPI virtualization” VM-execution controls:
•A write access is virtualized if its page offset is 080 H (task priority) regardless of the settings of the “APIC-
•If the “virtual-interrupt delivery” VM-e xecution control is 1, a write access is virtualized if its page offset is 
0B0H (end of interrupt) or 300H (interrupt command — low).
•If the “IPI virtualization” VM-execution control is 1, a write access is virtualized if its page offset is 300H.
•If the “APIC-register virtualization” VM-execution control is 1, a write access is virtualized if it is entirely within 
one the following ranges of offsets:
— 020H–023H (local APIC ID);— 080H–083H (task priority);
— 0B0H–0B3H (end of interrupt);
— 0D0H–0D3H (logical destination);— 0E0H–0E3H (destination format);
— 0F0H–0F3H (spurious-interrupt vector);
— 280H–283H (error status);— 300H–303H or 310H–313H (interrupt command);
5. The memory type used for accesses that read from the virtual- APIC page is reported in bits 53:50 of the IA32_VMX_BASIC MSR 
(see Appendix A.1).30-10 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
— 320H–323H, 330H–333H, 340H–343H, 350H–353H,  360H–363H, or 370H–373H (LVT entries);
The processor virtualizes a write access to the APIC-access pa ge by writing data to the corresponding page offset 
on the virtual-APIC page.6 Following this, the processor performs certai n actions after completion of the operation 
of which the access was a part.7 APIC-write emulation is described in Section 30.4.3.2.
30.4.3.2  APIC-Write Emulation
If the processor virtualizes a write access to the APIC-access  page, it performs additional actions after completion 
of an operation of which the access was a part. These actions are called APIC-write emulation .
The details of APIC-write emulation depend upon the page offset of the virtualized write access:8
•080H (task priority). The processor clears bytes 3:1 of  VTPR and then causes TPR virtualization (Section 
30.1.2).
•0B0H (end of interrupt). If the “virtu al-interrupt delivery” VM-execution control is 1, the processor clears VEOI 
and then causes EOI virtualization (Section 30.1.4); ot herwise, the processor causes an APIC-write VM exit 
(Section 30.4.3.3).
•300H (interrupt command — low). If the “virtual-interru pt delivery” VM-execution control is 1, the processor 
checks the value of VICR_LO to determine whether the following are all true:
— Reserved bits (31:20, 17:16, 13) and bit 12 (delivery status) are all 0.— Bits 19:18 (destination shorthand) are 01B (self).
— Bit 15 (trigger mode) is 0 (edge).
— Bits 10:8 (delivery mode) are 000B (fixed).— Bits 7:4 (the upper half of the vector) are not 0000B.
If all of the items above are true, the processor performs self-IPI virtualization using the 8-bit vector in byte 0
of VICR_LO (Section 30.1.5).
If the “virtual-interrupt delivery” VM-execution control is 0, or if any of the items above are false, behavior
depends on the setting of the “IPI virtualization” VM-execution control:
— If the “IPI virtualization” VM-execution control is 1, the processor checks the value of VICR_LO to determine 
whether the following are all true:
•Reserved bits (31:20, 17:16, 13) and bit 12 (delivery status) are all 0.
•Bits 19:18 (destination shorthand) are 00B (no shorthand).
•Bit 15 (trigger mode) is 0 (edge).
•Bit 11 (destination mode) is 0 (physical).
•Bits 10:8 (delivery mode) are 000B (fixed).
If all of the items above are true, th e processor performs IPI virtualization using the 8-bit vector in byte 0 
of VICR_LO and the 8-bit APIC ID in VICR_HI[31:24] (S ection 30.1.6); otherwise, the processor causes an 
APIC-write VM exit.
— If the “IPI virtualization” VM-execution control is  0, the processor causes an APIC-write VM exit.
6. The memory type used for accesses that write to the virtual-APIC page is reported in bits 53:50 of the IA32_VMX_BASIC MSR (see  
Appendix A.1).
7. Recall that, for the purposes of this discussion, an operation is an iteration of a REP-prefixed string instruction, an execu tion of any 
8. For any operation, there can be only one page offset for which a write access was virtualized. This is because a write access  is not 
virtualized if the processor has already virtualized a write access for the same operation with a different page offset.Vol. 3C 30-11APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•310H–313H (interrupt command — high). The processor clea rs bytes 2:0 of VICR_HI. No other virtualization or 
•Any other page offset. The processor causes an APIC-write VM exit.
APIC-write emulation takes priority over system-management interrupts (SMIs), INIT signals, and lower priority 
events. APIC-write emulation is not blocked if RFLAGS.IF = 0 or by the MOV SS, POP SS, or STI instructions.
If an operation causes a fault after a write access to the APIC-access page and before APIC-write emulation, and 
that fault is delivered without a VM exit, APIC-write emulat ion occurs after the fault is delivered and before the fault 
handler can execute. If an operation causes a VM exit (p erhaps due to a fault) after a write access to the APIC-
access page and before APIC-write emulation,  the APIC-write emulation does not occur.
30.4.3.3  APIC-Write VM Exits
In certain cases, VMM software must be invoked to complete the virtualization of a write access to the APIC-access 
page. In this case, APIC-write emulation causes an APIC-write VM exit . (Section 30.4.3.2 details the cases that 
causes APIC-write VM exits.)
APIC-write VM exits are invoked by APIC-write emulation, and APIC-write emulation occurs after an operation that 
performs a write access to the APIC-access page. Because of this, every APIC-write VM exit is trap-like: it occurs after completion of the operation containing the write access that caused the VM exit (for example, the value of 
CS:RIP saved in the guest-state area of the VMCS references the next instruction).
The basic exit reason for an APIC-write VM exit is “APIC writ e.” The exit qualification is the page offset of the write 
access that led to the VM exit.
As noted in Section 30.5, execution of WRMSR with ECX = 83 FH (self-IPI MSR) can lead to an APIC-write VM exit if 
the “virtual-interrupt delivery” VM-execution control is 1; the exit qualification for the APIC-write VM exit is 3F0H. 
As noted in Section 30.1.6 and in Section 30.7, IPI virt ualization and execution of SENDUIPI may lead to APIC-
write VM exits; these VM exits produc e an exit qualification of 300H.
30.4.4 Instruction-Specific Considerations
Certain instructions that use linear address may cause page faults even though they do not use those addresses to

Certain instructions that use linear address may cause page faults even though they do not use those addresses to 
access memory. The APIC-virtualization features may affect these instructions as well:
•CLFLUSH, CLFLUSHOPT.  With regard to faulting, the processor operates as if each of these instructions reads 
from the linear address in its source operand. If that  address translates to one on the APIC-access page, the 
instruction may cause an APIC-access VM exit. If it does not, it will flush the corresponding cache line on the 
virtual-APIC page instead of the APIC-access page.
•ENTER.  With regard to faulting, the processor operates if  ENTER writes to the byte  referenced by the final 
value of the stack pointer (even though it does not if its size operand is non-zero). If that value translates to an address on the APIC-access page, the instruction may cause an APIC-access VM exit. If it does not, it will cause 
the APIC-write emulation appropriate to the address’s page offset.
•MASKMOVQ and MASKMOVDQU.  Even if the instruction’s mask is zero, the processor may operate with 
regard to faulting as if MASKMOVQ or MASKMOVDQU writes to memory (the behavior is implementation-
specific). In such a situation, an APIC-access VM exit may occur.
•MONITOR.  With regard to faulting, the processor operates as if MONITOR reads from the effective address in 
RAX. If the resulting linea r address translates to one on the APIC-access page, the instruction may cause an 
APIC-access VM exit.9 If it does not, it will monitor the corresponding address on the virtual-APIC page instead 
of the APIC-access page.
•PREFETCH.  An execution of the PREFETCH instruction that would result in an access to the APIC-access page 
does not cause an APIC-access VM exit. Such an access may prefetch data; if so, it is from the corresponding 
address on the virtual-APIC page.
9. This chapter uses the no tation RAX, RIP, RSP, RFLAGS, etc. for processor re gisters because most processors that support VMX o per-
ation also support Intel 64 architecture. Fo r IA-32 processors, this notation refers to  the 32-bit forms of  those registers (EA X, EIP, 
ESP, EFLAGS, etc.). In a few places, notation  such as EAX is used to refer specifica lly to lower 32 bits of  the indicated regis ter.30-12 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
Virtualization of accesses to the APIC-access page is principally intended for basic instructions such as AND, MOV, 
OR, TEST, XCHG, and XOR. Use of an instruction that norm ally operates on floating-point, SSE, AVX, or AVX-512 
registers may cause an APIC-access VM exit unconditionally regardless of the page offset it accesses on the APIC-
access page.
30.4.5 Issues Pertaining to Page Size and TLB Management
The 1-setting of the “virtualize APIC accesses” VM-execution is guaranteed to apply only if translations to the APIC-
access address use a 4-KByte page. The following items provide details:
•If EPT is not in use, any linear address that translates  to an address on the APIC-access page should use a 4-
KByte page. Any access to a linear address that translates to the APIC-access page using a larger page may 
operate as if the “virtualize APIC a ccesses” VM-execution control were 0.
•If EPT is in use, any guest-physical address that translates to an address on the APIC-access page should use a 
4-KByte page. Any access to a linear address that translates  to a guest-physical address that in turn translates 
to the APIC-access page using a larger page may operat e as if the “virtualize APIC accesses” VM-execution 
control were 0. (This is true also for guest-physical  accesses to the APIC-access page; see Section 30.4.6.1.)
In addition, software should perform appropriate TLB in validation when making changes that may affect APIC-
virtualization. The specifics depend on  whether VPIDs or EPT is being used:
•VPIDs being used but EPT not being used. Suppose that there is a VPID that  has been used before and that 
software has since made either of the following change s: (1) set the “virtualize APIC accesses” VM-execution 
control when it had previously been 0; or (2) changed  the paging structures so that some linear address 
translates to the APIC-access address when it previous ly did not. In that case, software should execute 
INVVPID (see “INVVPID— Invalidate Translations Based on  VPID” in Section 31.3) before performing on the 
same logical processor and with the same VPID.10
•EPT being used. Suppose that there is an EPTP value that has been used before and that software has since 
made either of the following changes: (1) set the “virtu alize APIC accesses” VM-execution control when it had 
previously been 0; or (2) changed the EPT paging structur es so that some guest-physical address translates to 
the APIC-access address when it previously did not. In that case, software should execute INVEPT (see 
“INVEPT— Invalidate Translations Derived from EPT” in Section 31.3) before performing on the same logical 
processor and with the same EPTP value.11
•Neither VPIDs nor EPT being used.  No invalidation is required.
Failure to perform the appropriate TLB invalidation may result  in the logical processor operating as if the “virtualize 
APIC accesses” VM-execution control were 0 in responses to  accesses to the affected address. (No invalidation is 
necessary if neither VPIDs nor EPT is being used.)
30.4.6 APIC Accesses Not Directly Resulting From Linear Addresses
Section 30.4 has described the treatment of accesses that us e linear addresses that translate to addresses on the 
APIC-access page. This section considers memory accesses that do not result directly from linear addresses.
•An access is called a guest-physical access  if (1) CR0.PG = 1;12 (2) the “enable EPT” VM-execution control 
is 1;13 (3) the access’s physical address is the result of an EPT translation; and (4) either (a) the access was 
not generated by a linear address; or (b) the access’s guest-physical address is not the translation of the 
access’s linear address. Section 30.4.6.1 discusses the treatment of guest-physical accesses to the APIC-access page.
10. INVVPID should use either (1) the all-contexts INVVPID type; (2) the single-con text INVVPID type with the VPID in the INVVPID  
descriptor; or (3)  the individual-address INVVPID type with the linear address and the VPID in the INVVPID descriptor.
11. INVEPT should use either (1) the global INVEPT type; or (2) th e single-context INVEPT type with  the EPTP value in the INVEPT 
12. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PG must be 1 in VMX operation, CR0.PG must be 1 unless the “unre-
stricted guest” VM-execution control and bit 31 of the pr imary processor-based VM-execution controls are both 1.
13. “Enable EPT” is a secondary processor-based VM-execution cont rol. If bit 31 of the primary processor-based VM-execution contr ols 
is 0, VMX non-root operation functions as if the “enable EPT” VM-execution control were 0. See Section 25.6.2.Vol. 3C 30-13APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•An access is called a physical access  if (1) either (a) the “enable EPT” VM-execution control is 0; or (b) the 
access’s physical address is not the result of a translation through the EPT paging structures; and (2) either (a) the access is not generated by a linear address; or (b) the access’s physical address is not the translation 
of its linear address. Section 30.4.6.2 discusses the treatment of physical accesses to the APIC-access page.
30.4.6.1  Guest-Physical Acce sses to the APIC-Access Page
Guest-physical accesses include the following when gues t-physical addresses are being translated using EPT:
•Reads from the guest paging structures when translating a linear address (such an access uses a guest-
physical address that is not the translation of that linear address).
•Loads of the page-directory-pointer-table entries by MOV to CR when the logical processor is using (or that 
causes the logical processor to use) PAE paging (see Section 4.4).
•Updates to the accessed and dirty flags in the guest pagi ng structures when using a linear address (such an 
access uses a guest-physical address that is not the translation of that linear address).
•Memory accesses by Intel Processor Trace when the “Intel PT uses guest physical addresses” VM-execution 
control is 1 (see Section 26.5.4).
Every guest-physical access using a guest-physical address that translates to an address on the APIC-access page 
causes an APIC-access VM exit. Such accesses are never virtualized regardless of the page offset.
The following items specify the priority relative to other events of APIC-access VM exits caused by guest-physical 
accesses to the APIC-access page.
•The priority of an APIC-access VM exit caused by a guest-physical access to memory is below that of any EPT 
violation that that access may incur. That is, a guest-physical access does not cause an APIC-access VM exit if it would cause an EPT violation.
•With respect to all other events, any APIC-access VM exit caused by a guest-physical access has the same 
priority as any EPT violation that the guest-physical access could cause.
30.4.6.2  Physical Accesses to the APIC-Access Page
Physical accesses include the following:

•If the “enable EPT” VM-execution control is 0:
— Reads from the paging structures when translating a linear address.
— Loads of the page-directory-pointer-table entries by MO V to CR when the logical processor is using (or that 
— Updates to the accessed and dirty flags in the paging structures.
•If the “enable EPT” VM-execution control is 1, accesses to the EPT paging structures (including updates to the 
accessed and dirty flags for EPT).
•Any of the following accesses made by the processor to support VMX non-root operation:
— Accesses to the VMCS region.
— Accesses to data structures referenced (directly or indirectly) by physical addresses in VM-execution 
control fields in the VMCS. These include the I/O bi tmaps, the MSR bitmaps, an d the virtual-APIC page.
•Accesses that effect transitions into and out of SMM.14 These include the following:
— Accesses to SMRAM during SMI delivery and during execution of RSM.— Accesses during SMM VM exits (including accesses to MSEG) and during VM entries that return from SMM.
A physical access to the APIC-access page may or may not cause an APIC-access VM exit. If it does not cause an 
APIC-access VM exit, it may access the APIC-access page or the virtual-APIC page. Physical write accesses to the 
APIC-access page may or may not cause APIC-write emulation or APIC-write VM exits.
14. Technically, these accesses do not occur in VMX non-root operation. They are included here for clarity.30-14 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
The priority of an APIC-access VM exit caused by physical access is not defined relative to other events that the 
access may cause.
It is recommended that software not set the APIC-access ad dress to any of the addresses used by physical memory 
accesses (identified above). For example, it should not se t the APIC-access address to the physical address of any 
of the active paging structures if the “enable EPT” VM-execution control is 0.
30.5 VIRTUALIZING MSR-BASED APIC ACCESSES
When the local APIC is in x2APIC mode, software accesse s the local APIC’s control registers using the MSR inter-
face. Specifically, software uses th e RDMSR and WRMSR instructions, setting ECX (identifying the MSR being 
accessed) to values in the range 800H–8FFH (see Section 11.12, “Extended XAPIC (x2APIC)”). This section 
describes how these accesses can be virtualized.
A virtual-machine monitor can virtualize these MSR-base d APIC accesses by configuring the MSR bitmaps (see 
Section 25.6.9) to ensure that the accesses cause VM exit s (see Section 26.1.3). Alternatively, there are methods 
for virtualizing some MSR-based APIC accesses without VM exits.
Normally, an execution of RDMSR or WRMSR that does no t fault or cause a VM exit accesses the MSR indicated in 
ECX. However, such an execution treats some values of  ECX in the range 800H–8FFH specially if the “virtualize 
x2APIC mode” VM-execution control is 1. The following items provide details:
•RDMSR.  The instruction’s behavior depends on the setting of the “APIC-register virtualization” VM-execution 
control.
— If the “APIC-register virtualization” VM-execution co ntrol is 0, behavior depends upon the value of ECX.
•If ECX contains 808H (indicating the TPR MSR), the instruction reads the 8 bytes from offset 080H on 
the virtual-APIC page (VTPR and the 4 bytes above it) into EDX:EAX. This occurs  even if the local APIC 
is not in x2APIC mode (no general-protection fault occurs because the local APIC is not x2APIC mode).
•If ECX contains any other value in the range 800H–8 FFH, the instruction operates normally. If the local 
APIC is in x2APIC mode and ECX indicates a readab le APIC register, EDX and EAX are loaded with the 
value of that register. If the local APIC is not in x2APIC mode or ECX does not indicate a readable APIC 
register, a general-protection fault occurs.
— If “APIC-register virtualization” is 1 and ECX contains  a value in the range 800H–8FFH, the instruction reads 
the 8 bytes from offset X on the virtual-APIC page into EDX:EAX, where X = (ECX & FFH) « 4. This occurs even if the local APIC is not in x2APIC mode (no general-protection fault occurs because the local APIC is 
not in x2APIC mode).
•WRMSR.  The instruction’s behavior depends on the value of ECX and the setting of the “virtual-interrupt 
delivery” and “IPI virtualization” VM-execution controls.
Special processing applies in the following cases: (1 ) ECX contains 808H (indicating the TPR MSR); (2) ECX
contains 80BH (indicating the EOI MSR) and the “virtual-interrupt delivery” VM-execution control is 1;
(3) ECX contains 83FH (indicating the self-IPI MSR) an d the “virtual-interrupt delivery” VM-execution control
is 1; and (4) ECX contains 830H (indicating the ICR MSR)  and the “IPI virtualization” VM-execution control is
1.
If special processing applies, no general-protection exce ption is produced due to the fact that the local APIC is
in xAPIC mode. However, WRMSR does perf orm the normal reserved-bit checking:
— If ECX contains 808H or 83FH, a general-protection fa ult occurs if either EDX or EAX[31:8] is non-zero.
— If ECX contains 80BH, a general-protection fault occurs if either EDX or EAX is non-zero.— If ECX contains 830H, a general-protection fault occurs if any of bits 31:20, 17:16, or 13 of EAX is non-zero.
If there is no fault, WRMSR stores EDX:EAX at offset  X on the virtual-APIC page, where X = (ECX & FFH) « 4.
Following this, the processor performs an operation depending on the value of ECX:
— If ECX contains 808H, the processor performs TPR virtualization (see Section 30.1.2).
— If ECX contains 80BH, the processor performs EOI virtualization (see Section 30.1.4).
— If ECX contains 83FH, the processor then checks  the value of EAX[7:4] and proceeds as follows:Vol. 3C 30-15APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
•If the value is non-zero, the logical processor perfor ms self-IPI virtualization with the 8-bit vector in 
EAX[7:0] (see Section 30.1.5).
•If the value is zero, the logical processor causes an  APIC-write VM exit as if there had been a write 
access to page offset 3F0H on the APIC-access page (see Section 30.4.3.3).
— If ECX contains 830H, the processor then checks the va lue of VICR to determine whether the following are 
all true:
•Bit 12 (unused) is 0.
If all of the items above are true, the processor performs  IPI virtualization using the 8-bit vector in byte 0 
of VICR and the 32-bit APIC ID in VICR[63:32] (see  Section 30.1.6). Otherwise, the logical processor 
causes an APIC-write VM exit (see Section 30.4.3.3).
If special processing does not apply, the instruction op erates normally. If the local APIC is in x2APIC mode
and ECX indicates a writable APIC register, the value in ED X:EAX is written to that register. If the local APIC is
not in x2APIC mode or ECX does not indicate a writab le APIC register, a general-protection fault occurs.
30.6 POSTED-INTERRUPT PROCESSING
Posted-interrupt processing is a feature by which a proce ssor processes the virtual interrupts by recording them as 
pending on the virtual-APIC page.
Posted-interrupt processing is enabled by setting the “process posted interrupts” VM-execution control. The 
processing is performed in response to  the arrival of an interrupt with the posted-interrupt notification vector . 
In response to such an interrupt, the processor processes virtual interrupts recorded in a data structure called a posted-interrupt descriptor . The posted-interrupt notification vector  and the address of the posted-interrupt 
descriptor are fields in the VMCS; see Section 25.6.8.
If the “process posted interrupts” VM-execution control is  1, a logical processor uses a 64-byte posted-interrupt 
descriptor located at the posted-interrupt descriptor addr ess. The posted-interrupt descriptor has the following 
format:
The notation PIR (posted-interrupt requests) refers to the 256 posted-interrupt bits in the posted-interrupt 
Use of the posted-interrupt descriptor differs from that of other data structures that are referenced by pointers in 
a VMCS. There is a general requirement that software ensure  that each such data structure is modified only when 
no logical processor with a current VMCS that references it is in VMX non-root operation. That requirement does 
not apply to the posted-interrupt descriptor. There is a requirement, however, that such modifications be done 
using locked read-modify-write instructions.Table 30-1.  Format of Posted-Interrupt Descriptor
Bit
Position(s)Name Description
255:0 Posted-interrupt requests One bit for each interrupt vect or. There is a posted-interrupt request for a vector if 
the corresponding bit is 1.
256 Outstanding notification If this bit is set, there is a notification outstand ing for one or more posted interrupts 
in bits 255:0.

format:
Bit
511:257 Reserved for software and 
other agentsThese bits may be used by software and by other agents in the system (e.g., 
chipset). The processor does not modify these bits.30-16 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
If the “external-interrupt exiting” VM-execution control is 1, any unmasked external interrupt causes a VM exit (see 
Section 26.2). If the “process posted interrupts” VM-execution  control is also 1, this behavior is changed and the 
processor handles an external interrupt as follows:15
1. The local APIC is acknowledged; this provides the pr ocessor core with an interrupt vector, called here the 
physical vector .
2. If the physical vector equals the posted-interrupt notification vector, the logical processor continues to the next 
step. Otherwise, a VM exit occurs as it would normally due to an external interrupt; the vector is saved in the 
VM-exit interruption-information field.
3. The processor clears the outstanding-notification bit in the posted-interrupt descriptor. This is done atomically 
so as to leave the remainder of the descriptor unmodified (e.g., with a locked AND operation).
4. The processor writes zero to the EOI register in the local APIC; this dismisses the interrupt with the posted-
interrupt notification vector from the local APIC.
5. The logical processor performs a logical-OR of PIR into VIRR and clears PIR. No other agent can read or write a 
PIR bit (or group of bits) between the ti me it is read (to determine what to OR into VIRR) and when it is cleared.
6. The logical processor sets RVI to be the maximum of the old value of RVI and the highest index of all bits that 
were set in PIR; if no bit was set in PIR, RVI is left unmodified.
7. The logical processor evaluates pending virtual interrupts as described in Section 30.2.1.
The logical processor performs the steps above in an uninte rruptible manner. If step #7 leads to recognition of a 
virtual interrupt, the processor may deliver that interrupt immediately.
Steps #1 to #7 above occur when the interrupt controller delivers an unmasked external interrupt to the CPU core. 
The following items consider certain cases of interrupt delivery:
•Interrupt delivery can occur between iterations of a REP-prefixed instruction (after at least one iteration has 
completed but before all iterations have completed). If this occurs, the following items characterize processor 
state after posted-interrupt processing completes and before guest execution resumes:
— RIP references the REP-prefixed instruction;— RCX, RSI, and RDI are updated to re flect the iterations completed; and
—R F L A G S . R F  =  1 .
•Interrupt delivery can occur when the logical processor is in the active, HLT, or MWAIT states. If the logical 
processor had been in the active or MWAIT state before the arrival of the interrupt, it is in the active state 
following completion of step #7; if it had been in the HL T state, it returns to the HLT state after step #7 (if a 
pending virtual interrupt was recognized, the logical processor may immediately wake from the HLT state).
•Interrupt delivery can occur while the logical processor is  in enclave mode. If the lo gical processor had been in 
enclave mode before the arrival of the interrupt, an Asynchronous Enclave Exit (AEX) may occur before the 
steps #1 to #7 (see Chapter 37, “Enclave Exiting Events ”). If no AEX occurs before step #1 and a VM exit 
occurs at step #2, an AEX occurs before the VM exit is delivered.
30.7 VIRTUALIZING SENDUIPI
The user-interrupt feature includes the SENDUIPI instructio n that software operating with CPL = 3 can use to send 
user interrupts to another software thread (“user IPIs”) . The SENDUIPI instruction has the following high-level 
operation:
read selected entry from user-interrupt target table;
use address in entry to read the referenced user posted-interrupt descriptor (UPID);update certain fields in UPID;if necessary, send ordinary IPI indicated in UPID’s notification information;
15. VM entry ensures that the “pro cess posted interrupts” VM -execution control is 1 only if the “external- interrupt exiting” VM- execu-
tion control is also 1. SeeSection 27.2.1.1.Vol. 3C 30-17APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
The last step uses two fields in the UPID: an 8-bit notifi cation vector (UPID.NV) and a 32-bit notification destination 
(an APIC ID, UPID.NDST). Outside of VM X non-root operation, the processor implements the last step as follows:
•If the local APIC is in xAPIC mode, it writes UPID.NDST[15:8] to ICR_HI[31:24] (offset 310H from 
IA32_APIC_BASE) and then writes UPID.NV to ICR_LO (offset 300H).
•If the local APIC is in x2APIC mode, it performs the co ntrol-register write that would be done by an execution 
of WRMSR with ECX = 310H (ICR), EAX = UPID.NV, and EDX = UPID.NDST.
In VMX non-root operation, implementation of the step depends on the settings of th e “use TPR shadow,” “virtu-
alize APIC accesses,” and “IPI virtualization” VM-execution controls:16
1. If the “use TPR shadow” VM-execution control is 0, the behavior is not modified: the logical processor sends the 
specified IPI by writing to the local APIC’s ICR as specif ied above (based on the current mode of the local APIC).
2. If the “use TPR shadow” VM-execution control is 1 and th e “virtualize APIC accesses” VM-execution control is 0, 
the logical processor virtualizes the sending of  an x2APIC-mode IPI with the following steps:
a. The 64-bit value Z is written to offset 300H on the virtual-APIC page (VICR), where Z[7:0] = UPID.NV (the 
8-bit virtual vector), Z[63:32] = UPID.NDST (the 32-bit virtual APIC ID) and Z[31:8] = 000000H (indicating a physically addressed fixed-mode IPI).
b. If the “IPI virtualization” VM-execution control is 1, IPI virtualization (Section 30.1.6) is performed using 
the vector UPID.NV and the 32-bit virtual APIC ID UPID.NDST.
3. If the “use TPR shadow” and “virtual ize APIC accesses” VM-execution controls are both 1, the logical processor 
virtualizes the sending of an xAPIC-mode  IPI by performing the following steps:
a. The 32-bit value X is written to offset 310H on the virtual-APIC page (VICR_HI), where X[31:24] = 
UPID.NDST[15:8] (the 8-bit virtual APIC ID) and X[23:0] = 000000H.
17
b. The 32-bit value Y is written to offset 300H on the virtual-APIC page (VICR_LO), where Y[7:0] = UPID.NV 
(the 8-bit virtual vector) and Y[31:8] = 000000H (indicating a physically addressed fixed-mode IPI).
c. If the “IPI virtualization” VM-execution control is 1, IPI virtualization is performed using the vector UPID.NV 
and the APIC ID UPID.NDST[15:8]. IPI virtualization will  use only the 8-bit APIC ID from bits 15:8 of the 
UPID’s destination field (the 8-bit value written earlier to bits 31:24 of VICR_HI).
4. If the “use TPR shadow” VM-execution control is 1 and the “IPI virtualization” VM-execution control is 0, an 
APIC-write VM exit occurs as if there had been a writ e access to page offset 300H on the APIC-access page (see 
Section 30.4.3.3).
16. The setting of the “virtualize x2APIC mode” VM-executi on control does not affect this operation.
17. For xAPIC mode (which is virtualized if the “virtualize APIC accesses” VM-execution control is 1), the destination APIC ID i s in byte 1 
(not byte 0) of the UPID’s 4-byte NDST field.30-18 Vol. 3CAPIC VIRTUALIZATION AND VIRTUAL INTERRUPTSVol. 3C 31-1CHAPTER 31
31.1 OVERVIEW
This chapter describes the virtual-machine extensions (VMX) for the Intel 64 and IA -32 architectures. VMX is 
intended to support virtualization of processor hardware an d a system software layer acting as a host to multiple 
guest software environments. The virtual-machine extensio ns (VMX) includes five instructions that manage the 
virtual-machine control structure (VMCS), four instructions that manage VMX operation, two TLB-management 
instructions, and two instructions for use by guest software . Additional details of VMX are described in Chapter 24 
through Chapter 30. 
The behavior of the VMCS-maintenance instructions is summarized below:
•VMPTRLD — This instruction takes a single 64-bit source oper and that is in memory. It makes the referenced 
VMCS active and current, loading the current-VMCS pointe r with this operand and establishes the current VMCS 
based on the contents of VMCS-data area in the refere nced VMCS region. Because this makes the referenced 
VMCS active, a logical processor may start maintaining on the processor some of the VMCS data for the VMCS.
•VMPTRST — This instruction takes a single 64-bit destinat ion operand that is in memory. The current-VMCS 
pointer is stored into the destination operand.
•VMCLEAR — This instruction takes a single 64-bit operand th at is in memory. The instruction sets the launch 
state of the VMCS referenced by the operand to “clear”,  renders that VMCS inactive, and ensures that data for 
the VMCS have been written to the VMCS-data area in th e referenced VMCS region. If the operand is the same

the VMCS have been written to the VMCS-data area in th e referenced VMCS region. If the operand is the same 
as the current-VMCS pointer, that pointer is made invalid.
•VMREAD — This instruction reads a component from a VMCS (the  encoding of that field is given in a register 
operand) and stores it into a destination op erand that may be a register or in memory.
•VMWRITE — This instruction writes a component to a VMCS (the encoding of that field is given in a register 
operand) from a source operand that may be a register or in memory.
•VMLAUNCH — This instruction launches a virtual machine managed by the VMCS. A VM entry occurs, trans-
ferring control to the VM.
•VMRESUME — This instruction resumes a virtual machine ma naged by the VMCS. A VM entry occurs, trans-
•VMXOFF — This instruction causes the processor to leave VMX operation.
•VMXON — This instruction takes a single 64-bit source operand that is in memory. It causes a logical processor 
to enter VMX root operation and to use the memory referenced by the operand to support VMX operation.
•INVEPT  — This instruction invalidates entries in the TLBs an d paging-structure caches that were derived from 
extended page tables (EPT).
•INVVPID  — This instruction invalidates entries in the TLBs and paging-structure caches based on a Virtual-
Processor Identifier (VPID).
•VMCALL — This instruction allows software in VMX non-root operation to call the VMM for service. A VM exit 
occurs, transferring control to the VMM.
•VMFUNC — This instruction allows software in VMX non-root operation to invoke a VM function (processor 
functionality enabled and configured by softwa re in VMX root operation) without a VM exit.31-2 Vol. 3CVMX INSTRUCTION REFERENCE
31.2 CONVENTIONS
The operation sections for the VMX instructions in Sect ion 31.3 use the pseudo-function VMexit, which indicates 
that the logical processor performs a VM exit.
The operation sections also use the pseudo-functions VMsucceed, VMfail, VMfailInval id, and VMfailValid. These 
pseudo-functions signal instruction success or failure by setting  or clearing bits in RFLAGS and, in some cases, by 
writing the VM-instruction error field. The follo wing pseudocode fragments detail these functions:
VMsucceed:
CF := 0;PF := 0;AF := 0;ZF := 0;SF := 0;OF := 0;
VMfail(ErrorNumber):
IF VMCS pointer is valid
THEN VMfailValid(ErrorNumber);ELSE VMfailInvalid;
FI;
VMfailInvalid:
CF := 1;PF := 0;AF := 0;ZF := 0;SF := 0;OF := 0;
VMfailValid(ErrorN umber):// executed only if  there is a current VMCS
CF := 0;PF := 0;AF := 0;ZF := 1;SF := 0;OF := 0;Set the VM-instruction er ror field to ErrorNumber;
The different VM-instruction error numbers are enumerat ed in Section 31.4, “VM Instruction Error Numbers.”
31.3 VMX INSTRUCTIONS
This section provides detailed descriptions of the VMX instructions.Vol. 3C 31-3VMX INSTRUCTION REFERENCE
INVEPT— Invalidate Transl ations Derived from EPT
Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches that were derived 
from extended page tables (EPT). (See Chapter 29, “VMX Support for Address Translation.”) Invalidation is based 
on the INVEPT type  specified in the register operand and the INVEPT descriptor  specified in the memory 
operand.
Outside IA-32e mode, the register operand is always 32 bi ts, regardless of the value of CS.D; in 64-bit mode, the 
register operand has 64 bits (the instruction cannot be executed in compatibility mode).
The INVEPT types supported by a logical processors are reported in the IA32_VMX_EPT_VPID_CAP MSR (see 
Appendix A, “VMX Capability Reporting Facility”).  There are two INVEPT types currently defined:
•Single-context invalidation. If the INVEPT type is 1, the logical processor invalidates all mappings associated 
with bits 51:12 of the EPT pointer (EPT P) specified in the INVEPT descriptor. It may invalidate other mappings 
as well.
•Global invalidation: If the INVEPT type is 2, the logical processor invalidates mappings associated with all 
EPTPs.
If an unsupported INVEPT type is specified, the instruction fails.
INVEPT invalidates all the specified mapp ings for the indicated EPTP(s) regardless  of the VPID and PCID values with 
which those mappings may be associated.
The INVEPT descriptor comprises 128 bits and contains a 64-bit EPTP value in bits 63:0 (see Figure 31-1).
Operation
IF (not in VMX operation) or (C R0.PE = 0) or (RFLAGS.VM = 1) or  (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VM exit;
ELSIF CPL > 0
THEN #GP(0);ELSEOpcode/ 
InstructionOp/En Description
66 0F 38 80
INVEPT r64, m128RM Invalidates EPT-derived entries in the TLBs and paging-structure caches (in 64-bit mode).
66 0F 38 80
INVEPT r32, m128RM Invalidates EPT-derived entries in the TLBs and paging-structure caches (outside 64-bit 
mode).
RM ModRM:reg (r) ModRM:r/m (r) NA NA
Figure 31-1.  INVEPT Descriptor127 64 63 0
Reserved (must be zero) EPT pointer (EPTP)31-4 Vol. 3CVMX INSTRUCTION REFERENCE
INVEPT_TYPE := value of register operand;
IF IA32_VMX_EPT_VPID_CAP MSR indicates that  processor does not support INVEPT_TYPE
THEN VMfail(Invalid operand to INVEPT/INVVPID);ELSE // INVEPT_TYPE must be 1 or 2
INVEPT_DESC := value of memory operand;EPTP := INVEPT_DESC[63:0];CASE INVEPT_TYPE OF
1: // single-context invalidation
IF VM entry with the “enable EPT“ VM execution control set to 1would fail due to the EPTP value
THEN VMfail(Invalid operand to INVEPT/INVVPID);ELSE
Invalidate mappings associated with EPTP[51:12];VMsucceed;
FI;BREAK;
2: // global invalidation
Invalidate mappings associated with all EPTPs;VMsucceed;BREAK;
ESAC;
FI;
FI;
See the operation section and Section 31.2.
If the source operand is located in an execute-only code segment.
#SS(0) If the memory operand effective address is outside the SS segment limit.
#UD If not in VMX operation.
If the logical processor does not supp ort EPT (IA32_VMX_PROCBASED_CTLS2[33]=0).
If the logical processor supports EPT (IA3 2_VMX_PROCBASED_CTLS2[33]=1) but does not 
support the INVEPT instruction (IA32_VMX_EPT_VPID_CAP[20]=0).
#UD The INVEPT instruction is not recognized in real-address mode.
#UD The INVEPT instruction is not recognized in virtual-8086 mode.
#UD The INVEPT instruction is not recognized in co mpatibility mode.Vol. 3C 31-5VMX INSTRUCTION REFERENCE
#SS(0) If the memory operand is in the SS segmen t and the memory address is in a non-canonical 
form.
If the logical processor does not suppo rt EPT (IA32_VMX_PROCBASED_CTLS2[33]=0).
If the logical processor supports EPT (IA 32_VMX_PROCBASED_CTLS2[33]=1) but does not 
support the INVEPT instruction (IA32_VMX_EPT_VPID_CAP[20]=0).31-6 Vol. 3CVMX INSTRUCTION REFERENCE
INVVPID— Invalidate Translations Based on VPID
Invalidates mappings in the translation lookaside bu ffers (TLBs) and paging-structure caches based on virtual-
processor identifier (VPID). (See Chapter 29, “VMX Support for Addr ess Translation.”) Invalidation is based on 
the INVVPID type  specified in the register operand and the INVVPID descriptor  specified in the memory 
operand.
The INVVPID types supported by a logical processors are reported in the IA32_VMX_EPT_VPID_CAP MSR (see 
Appendix A, “VMX Capability Reporting Facility”).  There are four INVVPID types currently defined:
•Individual-address invalidation: If the INVVPID type is 0, the logical processor invalidates mappings for the 
linear address and VPID specified in the INVVPID descrip tor. In some cases, it may invalidate mappings for 
other linear addresses (or other VPIDs) as well.

operand.
•Single-context invalidation: If the INVVPID type is 1, th e logical processor invalidates all mappings tagged with 
the VPID specified in the INVVPID descriptor. In some cases, it may invalidate mappings for other VPIDs as 
well.
•All-contexts invalidation: If the INVVPID type is 2, the logical processor invalidates all mappings tagged with all 
VPIDs except VPID 0000H. In some cases, it may invalidate translations with VPID 0000H as well.
•Single-context invalidation, retaining global translatio ns: If the INVVPID type is 3, the logical processor 
invalidates all mappings tagged with th e VPID specified in the INVVPID descriptor except global translations. In 
some cases, it may invalidate global translations (and  mappings with other VPIDs) as well. See the “Caching 
Translation Information” section in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A, for information about global translations.
If an unsupported INVVPID type is specified, the instruction fails.
INVVPID invalidates all the specified mappings for the in dicated VPID(s) regardless of the EPTP and PCID values 
with which those mappings may be associated.
The INVVPID descriptor comprises 128 bits and consists of  a VPID and a linear address as shown in Figure 31-2.Opcode/
66 0F 38 81
INVVPID r64, m128RM Invalidates entries in the TL Bs and paging-structure caches based on VPID (in 64-bit 
mode).
66 0F 38 81
INVVPID r32, m128RM Invalidates entries in the TLBs and paging-structure caches based on VPID (outside 64-bit 
mode).
Figure 31-2.  INVVPID Descriptor127 64 63 0 1516
Reserved (must be zero) Linear Address VPIDVol. 3C 31-7VMX INSTRUCTION REFERENCE
Operation
THEN #UD;
THEN #GP(0);ELSE
INVVPID_TYPE := value of register operand;IF IA32_VMX_EPT_VPID_CAP MSR indicate s that processor does not support
INVVPID_TYPE
THEN VMfail(Invalid operand to INVEPT/INVVPID);ELSE // INVVPID_TYPE must  be in the range 0–3
INVVPID_DESC := value of memory operand;IF INVVPID_DESC[63:16] ≠ 0
CASE INVVPID_TYPE OF
VPID := INVVPID_DESC[15:0];IF VPID = 0
GL_ADDR := INVVPI D_DESC[127:64];
IF (GL_ADDR is not in a canonical form)
THEN
VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
Invalidate mappings for GL_ADDR tagged with VPID;VMsucceed;
FI;
FI;BREAK;
Invalidate all mappings tagged with VPID;VMsucceed;
FI;BREAK;
2: // all-context invalidation
Invalidate all mappings tagged with all non-zero VPIDs;VMsucceed;BREAK;
3: // single-context invali dation retaining globals
Invalidate all mappings tagged with  VPID except global translations;
VMsucceed;31-8 Vol. 3CVMX INSTRUCTION REFERENCE
FI;
BREAK;
ESAC;
FI;
FI;
FI;
If the logical processor does not suppor t VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=0).
If the logical processor supports VPIDs (IA3 2_VMX_PROCBASED_CTLS2[37]=1) but does not 
support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0).
#UD The INVVPID instruction is not recognized in real-address mode.
#UD The INVVPID instruction is not recognized in virtual-8086 mode.
#UD The INVVPID instruction is not recognized in co mpatibility mode.
support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0).Vol. 3C 31-9VMX INSTRUCTION REFERENCE
This instruction allows guest software can make a call for service into an underlying VM monitor. The details of the 
programming interface for such calls are VMM-specific; this  instruction does nothing more than cause a VM exit, 
registering the appropriate exit reason.
Use of this instruction in VMX root operation invokes an SM M monitor (see Section 32.15.2). This invocation will acti-
vate the dual-monitor treatment of system-management interrupts (SMIs) and system-management mode (SMM) 
if it is not already active (see Section 32.15.6).
Operation
IF not in VMX operation
THEN #UD;
ELSIF (RFLAGS.VM = 1) or (I A32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in SMM or the logical processor does not support the dual -monitor treatment of SMIs an d SMM or the valid bit in the 
IA32_SMM_MONITOR_CTL MSR is clear
THEN VMfail (VMCALL executed in VMX root operation);
ELSIF dual-monitor treatment of SMIs and SMM is active
THEN perform an SMM VM ex it (see Section 32.15.2);
ELSIF current-VMCS po inter is not valid
THEN VMfailInvalid;
ELSIF launch state of cu rrent VMCS is not clear
THEN VMfailValid(VMCALL with non-clear VMCS);
ELSIF VM-exit control fields are not valid (see Section 32.15.6.1)
THEN VMfailValid (VMCALL with invalid VM-exit control fields);
ELSE
enter SMM;read revision identifier in MSEG;IF revision identifier does not match that supported by processor
THEN
leave SMM;VMfailValid(VMCALL with incorrect MSEG revision identifier);
ELSE
read SMM-monitor features field in MSEG (see Section 32.15.6.1);IF features field is invalid
THEN
leave SMM;Opcode/
0F 01 C1
VMCALLZO Call to VM monitor by causing VM exit.
ZO NA NA NA NA31-10 Vol. 3CVMX INSTRUCTION REFERENCE
VMfailValid(VMCALL with invalid SMM-monitor features);
ELSE activate dual-monitor  treatment of SMIs and SM M (see Section 32.15.6);
FI;
FI;
FI;
#GP(0) If the current privilege level is not 0 and the logical processor is in VMX root operation. 
#UD If executed outside VMX operation.
#UD If executed outside VMX non-root operation.
#UD If executed outside VMX operation.Vol. 3C 31-11VMX INSTRUCTION REFERENCE
This instruction applies to the VMCS whose VMCS region re sides at the physical address contained in the instruction 
operand. The instruction ensures that VMCS data for that  VMCS (some of these data may be currently maintained 
on the processor) are copied to the VMCS region in memo ry. It also initializes parts of the VMCS region (for 
example, it sets the launch state of that VMCS to clea r). See Chapter 25, “Virtual Machine Control Structures.” 
The operand of this instruction is always 64 bits and is always in memory. If the operand is the current-VMCS 
pointer, then that pointer is made invalid (set to FFFFFFFF_FFFFFFFFH).
Note that the VMCLEAR instruction might not explicitly wr ite any VMCS data to memory; the data may be already 
resident in memory before the VMCLEAR is executed.
Operation
IF (register operand) or (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
addr := contents of 64-bit in-memory operand;IF addr is not 4KB-aligned OR addr sets any bits beyond  the physical-address width
1
THEN VMfail(VMCLEAR with invalid physical address);
ELSIF addr = VMXON pointer
THEN VMfail(VMCLEAR with VMXON pointer);ELSE
ensure that data for VM CS referenced by the operand is in memory;

Operation
THEN #UD;
1
initialize implementation-specific data in VMCS region;launch state of VMCS referenced by the operand := “clear”IF operand addr = current-VMCS pointer
THEN current-VMCS pointer := FFFFFFFF_FFFFFFFFH;
FI;VMsucceed;
FI;
FI;
See the operation section and Section 31.2.Opcode/
66 0F C7 /6
VMCLEAR m64M Copy VMCS data to VMCS region in memory.
M ModRM:r/m (r) NA NA NA
1. If IA32_VMX_BASIC[48] is read as 1, VMfail occurs if addr se ts any bits in the rang e 63:32; see Appendix A.1.31-12 Vol. 3CVMX INSTRUCTION REFERENCE
If the operand is located in an execute-only code segment.
#PF(fault-code) If a page fault occu rs in accessing the memory operand.
#UD If operand is a register.
If not in VMX operation.
#UD The VMCLEAR instruction is not recognized in real-address mode.
#UD The VMCLEAR instruction is not recognized in virtual-8086 mode.
#UD The VMCLEAR instruction is not recognized in compatibility mode.
If the source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in 
#SS(0) If the source operand is in the SS segm ent and the memory address is in a non-canonical 
form.
If not in VMX operation.Vol. 3C 31-13VMX INSTRUCTION REFERENCE
VMFUNC—Invoke VM function
This instruction allows software in VMX non-root operation to invoke a VM function, which is processor functionality 
enabled and configured by software in VMX root operation.  The value of EAX selects the specific VM function being 
invoked.
The behavior of each VM function (including any additional fault checking) is specified in Section 26.5.6, 
“VM Functions.”
Operation
Perform functionality of the VM function specified in EAX;
Depends on the VM function specified in EAX. See Section 26.5.6, “VM Functions.”
Protected Mode Exceptions (not includin g those defined by specific VM functions)
If “enable VM functions” VM-execution control is 0.
If EAX ≥ 64.
Virtual-8086 Exceptions
NP 0F 01 D4
VMFUNCZO Invoke VM function specified in EAX.
ZO NA NA NA NA31-14 Vol. 3CVMX INSTRUCTION REFERENCE
VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine
Effects a VM entry managed by the current VMCS.
•VMLAUNCH fails if the launch state of current VMCS is no t “clear”. If the instruction is successful, it sets the 
launch state to “launched.” 
•VMRESUME fails if the launch state of the current VMCS is not “launched.”
If VM entry is attempted, the logical processor performs a series of consistency checks as detailed in Chapter 27, 
“VM Entries.” Failure to pass checks on the VMX controls or on the host-state area passes control to the instruction 
following the VMLAUNCH or VMRESUME instruction. If these pass but checks on the guest-state area fail, the logical 
processor loads state from the host-state area of the VMCS , passing control to the instruction referenced by the RIP 
field in the host-state area.
VM entry is not allowed when events are blocked by MO V SS or POP SS. Neither VMLAUNCH nor VMRESUME should 
be used immediately after either MOV to SS or POP to SS.
Operation
THEN #UD;
THEN VMexit;
ELSIF events are being blocked by MOV SS
THEN VMfailValid(VM entry with events blocked by MOV SS);
ELSIF (VMLAUNCH and launch state of current VMCS is not “clear”)
THEN VMfailValid(VMLAUNCH with non-clear VMCS);
ELSIF (VMRESUME and launch state of current VMCS is not “launched”)
THEN VMfailValid(VMRESUME with non-launched VMCS);ELSE
Check settings of VMX contro ls and host-state area;
IF invalid settings
THEN VMfailValid(VM entry with invalid VMX-control field(s)) or
VMfailValid(VM entry with invalid host-state field(s)) or VMfailValid(VM entry with invalid executive-VMCS pointer)) or VMfailValid(VM entry with non-launched executive VMCS) orVMfailValid(VM entry with executive-VMCS pointer not VMXON pointer) orOpcode/
0F 01 C2
VMLAUNCHZO Launch virtual machine managed by current VMCS.
0F 01 C3
VMRESUMEZO Resume virtual machine managed by current VMCS.
ZO NA NA NA NAVol. 3C 31-15VMX INSTRUCTION REFERENCE
VMfailValid(VM entry with invalid VM-execution control fields in executive
VMCS)as appropriate;
ELSE
Attempt to load guest state and PDPTRs as appropriate;
clear address-range monitoring;IF failure in checking guest state or PDPTRs
THEN VM entry fails (see Section 27.8);ELSE
Attempt to load MS Rs from VM-entry MSR-load area;
IF failure
THEN VM entry fails(see Section 27.8);ELSE
IF VMLAUNCH
THEN launch state of VMCS := “launched”;
FI;IF in SMM and “entry to SMM” VM-entry control is 0
THEN
IF “deactivate dual-monit or treatment” VM-entry
control is 0
THEN SMM-transfer VMCS pointer := current-VMCS pointer;
FI;IF executive-VMCS pointer is VMXON pointer
THEN current-VMCS pointer := VMCS-link pointer;ELSE current-VMCS pointer := executive-VMCS pointer;
FI;leave SMM;
FI;VM entry succeeds;
FI;
FI;
FI;
FI;
Further details of the operation of the VM-entry appear in Chapter 27.
#UD The VMLAUNCH and VMRESUME  instructions are not recognized in real-address mode.
#UD The VMLAUNCH and VMRESUME  instructions are not recognized in virtual-8086 mode.31-16 Vol. 3CVMX INSTRUCTION REFERENCE
#UD The VMLAUNCH and VMRESUME instructions are not recognized in  compatibility mode.
#UD If executed outside VMX operation.Vol. 3C 31-17VMX INSTRUCTION REFERENCE
Marks the current-VMCS pointer valid and loads it with the physical address in the instruction operand. The instruc-
tion fails if its operand is not properly aligned, sets unsupported physical-address bits, or is equal to the VMXON 
pointer. In addition, the instruction fails if the 32 bits in  memory referenced by the operand do not match the VMCS 
revision identifier supported by this processor.1
The operand of this instruction is always 64 bits and is always in memory.
Operation
THEN #UD;
addr := contents of 64-bit in-memory source operand;IF addr is not 4KB-aligned ORaddr sets any bits beyond  the physical-address width
2
THEN VMfail(VMPTRLD with invalid physical address);
THEN VMfail(VMPTRLD with VMXON pointer);ELSE
rev := 32 bits located at physical address addr;IF rev[30:0] ≠ VMCS revision identifier supported by processor OR
rev[31] = 1 AND processor does not su pport 1-setting of  “VMCS shadowing”
THEN VMfail(VMPTRLD with incorrect VMCS revision identifier);ELSE
current-VMCS pointer := addr;VMsucceed;
FI;
FI;
FI;
NP 0F C7 /6
VMPTRLD m64M Loads the current VMCS pointer from memory.
1. Software should consult the VMX capability MSR VMX_BASIC to disc over the VMCS revision identifi er supported by this processor  
(see Appendix A, “VMX Capability Reporting Facility”).
2. If IA32_VMX_BASIC[48] is read as 1, VMfail occurs if addr se ts any bits in the rang e 63:32; see Appendix A.1.31-18 Vol. 3CVMX INSTRUCTION REFERENCE

FI;
FI;
FI;
NP 0F C7 /6
If the memory source operand effective address is outside the CS, DS, ES, FS, or GS segment 
limit.
#PF(fault-code) If a page fault occurs in  accessing the memory source operand.
#SS(0) If the memory source operand effectiv e address is outside the SS segment limit.
#UD The VMPTRLD instruction is not recognized in real-address mode.
#UD The VMPTRLD instruction is not recognized in virtual-8086 mode.
#UD The VMPTRLD instruction is not recognized in compatibility mode.
#SS(0) If the source operand is in the SS segmen t and the memory address is in a non-canonical 
form.
If not in VMX operation.Vol. 3C 31-19VMX INSTRUCTION REFERENCE
Stores the current-VMCS pointer into a specified memory addr ess. The operand of this instruction is always 64 bits 
and is always in memory.
Operation
THEN #UD;
THEN #GP(0);ELSE 
64-bit in-memory destination operand := current-VMCS pointer;VMsucceed;
FI;
If the memory destination operand effective address is outside the CS, DS, ES, FS, or GS 
segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.If the destination operand is located in a read-only data segment or any code segment.
#PF(fault-code) If a page fault occurs in accessing the memory destination operand.
#SS(0) If the memory destination operand effect ive address is outside the SS segment limit.
#UD The VMPTRST instruction is not recognized in real-address mode.
#UD The VMPTRST instruction is not recognized in virtual-8086 mode.Opcode/
NP 0F C7 /7
VMPTRST m64M Stores the current VMCS  pointer into memory.
M ModRM:r/m (w) NA NA NA31-20 Vol. 3CVMX INSTRUCTION REFERENCE
#UD The VMPTRST instruction is not recognized in compatibility mode.
If the destination operand is in the CS, DS, ES , FS, or GS segments and the memory address 
is in a non-canonical form.
#SS(0) If the destination operand is in the SS segm ent and the memory address is in a non-canonical 
form.
If not in VMX operation.Vol. 3C 31-21VMX INSTRUCTION REFERENCE
Reads a specified field from a VMCS and stores it into a specified destination operand (register or memory). In VMX 
root operation, the instruction reads from the current VMCS . If executed in VMX non-root operation, the instruction 
reads from the VMCS referenced by the VMCS  link pointer field in the current VMCS.
The VMCS field is specified by the VMCS-field encoding co ntained in the register source operand. Outside IA-32e 
mode, the source operand has 32 bits, regardless of the va lue of CS.D. In 64-bit mode, the source operand has 64 
bits. 
The effective size of the destination operand, which may be a register or in memory, is always 32 bits outside IA-
32e mode (the setting of CS.D is ignored with respect to operand size) and 64 bits in 64-bit mode. If the VMCS field 
specified by the source operand is shorter than this effect ive operand size, the high bits of the destination operand 
are cleared to 0. If the VMCS field is longer, then the high bits of the field are not read.
Note that any faults resulting from accessing a memory destination operand can occur only after determining, in 
the operation section below, that the relevant VMCS pointe r is valid and that the specified VMCS field is supported.
Operation
IF (not in VMX operation) or (C R0.PE = 0) or (RFLAGS. VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation AND (“VMCS shadowing” is 0 OR source operand sets bits in range 63:15 OR
VMREAD bit corresponding to bits 14:0 of source operand is 1)1
ELSIF (in VMX root operation AND current-VMCS pointer is not valid) OR (in VMX non-root operation AND VMCS link pointer is not valid)
ELSIF source operand does not correspond to any VMCS field
THEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component);ELSE
IF in VMX root operation
THEN destination operand := contents of field indexed by source operand in current VMCS;ELSE destination operand := contents of field indexed by source operand in VMCS refere nced by VMCS link pointer;
NP 0F 78
VMREAD r/m64, r64MR Reads a specified VMCS field (in 64-bit mode).
NP 0F 78
VMREAD r/m32, r32MR Reads a specified VMCS field (outside 64-bit mode).
MR ModRM:r/m (w) ModRM:reg (r) NA NA
1. The VMREAD bit for a source operand is defined as follows. Let x be the value of bits 14:0 of the source operand and let addr be the 
VMREAD-bitmap address. The corresponding VMREAD bit is in bit position x& 7 of the byte at physical address addr | (x » 3).31-22 Vol. 3CVMX INSTRUCTION REFERENCE
If a memory destination operand effective address is outside the CS, DS, ES, FS, or GS 
If the destination operand is located in a read-only data segment or any code segment.
#PF(fault-code) If a page fault occurs in accessing a memory destination operand.
#SS(0) If a memory destination operand effect ive address is outside the SS segment limit.
#UD The VMREAD instruction is not recognized in real-address mode.
#UD The VMREAD instruction is not recognized in virtual-8086 mode.
#UD The VMREAD instruction is not recognized in compatibility mode.
If the memory destination operand is in the CS, DS, ES, FS, or GS segments and the memory 
address is in a non-canonical form.
#UD If not in VMX operation.Vol. 3C 31-23VMX INSTRUCTION REFERENCE
See VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine.31-24 Vol. 3CVMX INSTRUCTION REFERENCE
Writes the contents of a primary source operand (register or memory) to a specified field in a VMCS. In VMX root 
operation, the instruction writes to the current VMCS. If ex ecuted in VMX non-root operation, the instruction writes 
to the VMCS referenced by the VMCS link pointer field in the current VMCS.
The VMCS field is specified by the VMCS-field encoding  contained in the register secondary source operand. 
Outside IA-32e mode, the secondary source operand is alwa ys 32 bits, regardless of the value of CS.D. In 64-bit 
mode, the secondary source operand has 64 bits. 
The effective size of the primary source operand, which may be a register or in memory, is always 32 bits outside 
IA-32e mode (the setting of CS.D is ignored with respect to operand size) and 64 bits in 64-bit mode. If the VMCS 
field specified by the secondary source operand is shorter than this effective operand size, the high bits of the 
primary source operand are ignored. If the VMCS field is longer, then the high bits of the field are cleared to 0.

Note that any faults resulting from accessing a memory source operand occur after determining, in the operation 
section below, that the relevant VMCS pointer is valid bu t before determining if the destination VMCS field is 
Operation
THEN #UD;
ELSIF in VMX non-root operation AND (“VMCS shadowing” is 0 OR secondary source operand sets bits in range 63:15 OR
VMWRITE bit corresponding to bits 14:0 of second ary source operand is 1)1
ELSIF (in VMX root operation AND current-VMCS pointer is not valid) OR(in VMX non-root operation AND VMCS-link pointer is not valid)
ELSIF secondary source operand does not correspond to any VMCS field
THEN VMfailValid(VMREAD/VMWRITE fr om/to unsupported VMCS component);
ELSIF VMCS field indexed by secondary source operand is a VM-exit information field ANDprocessor does not support writing to such fields
2
THEN VMfailValid(VMWRITE to read-only VMCS component);ELSEOpcode/
NP 0F 79
VMWRITE r64, r/m64RM Writes a specified VMCS field (in 64-bit mode).
NP 0F 79
VMWRITE r32, r/m32RM Writes a specified VMCS field (outside 64-bit mode).
1. The VMWRITE bit for a secondary source operand is defined as follows. Let x be the value of bits 14:0 of the secondary source oper-
and and let addr  be the VMWRITE-bitmap address. The corresponding VMWRITE bit is in bit position x& 7 of the byte at physical 
address addr | (x » 3).
2. Software can discover whether these fields can be written by reading the VMX capability MSR IA32_VMX_MISC (see Appendix A.6).Vol. 3C 31-25VMX INSTRUCTION REFERENCE
THEN field indexed by secondary source operan d in current VMCS := primary source operand;
ELSE field indexed by secondary source operand in VMCS re ferenced by VMCS link pointer := primary source operand;
FI;
If a memory source operand effective address is outside the CS, DS, ES, FS, or GS segment 
limit.
If the DS, ES, FS, or GS register contains an unusable segment.If the source operand is located in an execute-only code segment.
#PF(fault-code) If a page fault occurs in accessing a memory source operand.
#SS(0) If a memory source operand effective address is outside the SS segment limit.
#UD The VMWRITE instruction is not recognized in real-address mode.
#UD The VMWRITE instruction is not recognized in virtual-8086 mode.
#UD The VMWRITE instruction is not recognized in compatibility mode.
If the memory source operand is in the CS, DS, ES, FS, or GS segments and the memory 
#SS(0) If the memory source operand is in the SS segment and the memory address is in a non-
#UD If not in VMX operation.31-26 Vol. 3CVMX INSTRUCTION REFERENCE
Takes the logical processor out of VMX operation, unblocks INIT signals, conditionally re-enables A20M, and clears 
any address-range monitoring.1 
Operation
THEN #UD;
THEN VMfail(VMXOFF under dual-monit or treatment of SMIs and SMM);
ELSE
leave VMX operation;unblock INIT;IF IA32_SMM_MON ITOR_CTL[2] = 0
2
THEN unblock SMIs;
IF outside SMX operation3
THEN unblock and enable A20M;
FI;clear address-range monitoring;VMsucceed;
FI;
#GP(0) If executed in VMX root operation with CPL > 0.Opcode/
0F 01 C4
VMXOFFZO Leaves VMX operation.
ZO NA NA NA NA
1. See the information on MONITOR/MWAIT in Chapter 9, “Multiple-Processor Ma nagement,” of the Intel® 64 and IA-32 Architectures 
2. Setting IA32_SMM_MONITOR_CTL[bit 2] to 1 prevents VMXOFF from unblocking SMIs regardless of the value of the register’s value  
bit (bit 0). Not all processors a llow this bit to be set to 1. Software should consult the VMX capability MSR IA32_VMX_MISC (see  
Appendix A.6) to determin e whether this is allowed.
3. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after t he 
last execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference.”Vol. 3C 31-27VMX INSTRUCTION REFERENCE
#UD The VMXOFF instruction is not recognized in real-address mode.
#UD The VMXOFF instruction is not recognized in virtual-8086 mode.
#UD The VMXOFF instruction is not recognized in compatibility mode.
#GP(0) If executed in VMX root operation with CPL > 0.
#UD If executed outside VMX operation.31-28 Vol. 3CVMX INSTRUCTION REFERENCE
Puts the logical processor in VMX operation with no current  VMCS, blocks INIT signals, disables A20M, and clears 
any address-range monitoring established by the MONITOR instruction.1 
The operand of this instruction is a 4KB-aligned physical addre ss (the VMXON pointer) that references the VMXON 
region, which the logical processor may use to support VMX operation. This operand is always 64 bits and is always in memory. 
Operation
IF (register operand) or (CR0.PE = 0) or (CR4.VMXE = 0)  or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF not in VMX operation
THEN
IF (CPL > 0) or (in A20M mode) or(the values of CR0 and CR4 are not supported in VMX operation; see Section 24.8) or(bit 0 (lock bit) of IA32_FEATURE_CONTROL MSR is clear) or(in SMX operation
2 and bit 1 of IA32_FEATURE_C ONTROL MSR is clear) or
(outside SMX operation and bit 2 of IA32_FEATURE_CONTROL MSR is clear)
addr := contents of 64-bit in-memory source operand;IF addr is not 4KB-aligned or addr sets any bits beyond the physical-address width
3
THEN VMfailInvalid;ELSE
rev := 32 bits located at physical address addr;IF rev[30:0] ≠ VMCS revision identifier supported by processor OR rev[31] = 1
current-VMCS pointer := FFFFFFFF_FFFFFFFFH;enter VMX operation;block INIT signals;block and disable A20M;Opcode/
F3 0F C7 /6
VMXON m64M Enter VMX root operation.
2. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. A logi-
execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference.”
3. If IA32_VMX_BASIC[48] is read  as 1, VMfailInvalid occurs if  addr sets any bits in the range 63:32; see Appendix A.1.Vol. 3C 31-29VMX INSTRUCTION REFERENCE
clear address-range monitoring;
IF the processor supports Intel PT but does no t allow it to be used in VMX operation1
THEN IA32_RTIT_CTL.TraceEn := 0;
FI;
FI;
FI;
THEN #GP(0);ELSE VMfail(“VMXON executed in VMX root operation”);
FI;
#GP(0) If executed outside VMX operation with CPL>0 or with invalid CR0 or CR4 fixed bits.
If executed in A20M mode.If the memory source operand effective address is outside the CS, DS, ES, FS, or GS segment 
limit.
If the value of the IA32_FEATURE_CONTROL MSR does not support entry to VMX operation in 
the current processor mode.
#PF(fault-code) If a page fault occurs in accessing the memory source operand.
#SS(0) If the memory source operand effect ive address is outside the SS segment limit.
If executed with CR4.VMXE = 0.

FI;
FI;
FI;
FI;
limit.
#UD The VMXON instruction is not recognized in real-address mode.
#UD The VMXON instruction is not recognized in virtual-8086 mode.
#UD The VMXON instruction is not recognized in compatibility mode.
#GP(0) If executed outside VMX operation with CPL > 0 or with invalid CR0 or CR4 fixed bits.
If executed in A20M mode.
1. Software should read the VMX capability MSR IA32_VMX_MISC to determin e whether the processor allows  Intel PT to be used in 
VMX operation (see Appendix A.6).31-30 Vol. 3CVMX INSTRUCTION REFERENCE
form.
If executed with CR4.VMXE = 0.Vol. 3C 31-31VMX INSTRUCTION REFERENCE
31.4 VM INSTRUCTION ERROR NUMBERS
For certain error conditions, the VM-instruction error field is  loaded with an error number to indicate the source of 
the error. Table 31-1 lists VM-instruction error numbers.
Table 31-1.  VM-Instruction Error Numbers
Error
NumberDescription
1 VMCALL executed in VMX root operation
2 VMCLEAR with invalid physical address3V M C L E A R  w i t h  VMXON pointer
4 VMLAUNCH with non-clear VMCS5 VMRESUME with non-launched VMCS6 VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME)
1
NOTES:
1. Earlier versions of this manual described this error as “VMRESUME with a corrupted VMCS”.7 VM entry with invalid control field(s)2,3
2. VM-entry checks on control fields and ho st-state fields may be performed in any order. Thus, an indication by error number o f one 
cause does not imply that there are not also other errors. Different processors may give different error numbers for the same V MCS.
3. Error number 7 is not used for VM entries that return from SMM that fail due to invalid VM-execu tion control fields in the exe cutive 
VMCS. Error number 25 is used for these cases.8 VM entry with invali d host-state field(s)2
9 VMPTRLD with invalid physical address
10 VMPTRLD with VMXON pointer
11 VMPTRLD with incorrect VMCS revision identifier
12 VMREAD/VMWRITE from/to unsupported VMCS component13 VMWRITE to read-only VMCS component15 VMXON executed in VMX root operation16 VM entry with invalid executive-VMCS pointer
2
17 VM entry with non-launched executive VMCS2
18 VM entry with executive-VMCS pointer no t VMXON pointer (when attemp ting to deactivate the du al-monitor treatment of 
SMIs and SMM)2
19 VMCALL with non-clear VMCS (when attempting to ac tivate the dual-monitor tr eatment of SMIs and SMM)
20 VMCALL with invalid VM-exit control fields
22 VMCALL with incorrect MSEG revision identifier (when attemp ting to activate the dual-monit or treatment of  SMIs and SMM)
23 VMXOFF under dual-monitor treatment of SMIs and SMM24 VMCALL with invalid SMM-monitor features (when attempting  to activate the du al-monitor treatment of SMIs and SMM)
25 VM entry with invalid VM-exe cution control fields in executive VMCS (when attempting to return from SMM)
2,3
26 VM entry with events blocked by MOV SS.
28 Invalid operand to INVEPT/INVVPID.31-32 Vol. 3CVMX INSTRUCTION REFERENCEVol. 3C 32-1CHAPTER 32
This chapter describes aspects of IA-64 and IA-32 architecture used in system management mode (SMM).
SMM provides an alternate operating environment that can be used to monitor and manage various system 
resources for more efficient energy usage, to control sy stem hardware, and/or to run proprietary code. It was 
introduced into the IA-32 architecture in the Intel386 SL processor (a mobile specialized version of the Intel386 
processor). It is also available in the Pentium M, Pent ium 4, Intel Xeon, P6 family, and Pentium and Intel486 
processors (beginning with the enhanced versions  of the Intel486 SL and Intel486 processors). 
32.1 SYSTEM MANAGEMENT MODE OVERVIEW
SMM is a special-purpose operating mode provided for handling system-wide functions like power management, 
system hardware control, or proprietary OEM-designed code. It is intended for use only by system firmware, not by 
applications software or general-purpose systems software. Th e main benefit of SMM is that it offers a distinct and 
easily isolated processor environment that operates transparently to the operating system or executive and soft-
ware applications. 
When SMM is invoked through a system management interru pt (SMI), the processor saves the current state of the 
processor (the processor’s context), then switches to a separate operating environment defined by a new address 
space. The system management software executive (SMI ha ndler) starts execution in that environment, and the 
critical code and data of the SMI handler reside in a ph ysical memory region (SMRAM) within that address space. 
While in SMM, the processor executes SMI handler code to perform operations such as powering down unused disk 
drives or monitors, executing proprietary code, or placin g the whole system in a suspended state. When the SMI 
handler has completed its operations, it executes a resume (RSM) instruction. This instruction causes the processor 
to reload the saved context of the processor, switch ba ck to protected or real mode, and resume executing the 
interrupted application or operating-system program or task.
The following SMM mechanisms make it transparent to applications programs and operating systems:
•The only way to enter SMM is by means of an SMI.
•The processor executes SMM code in a separate address space that can be made inaccessible from the other 
operating modes.
•Upon entering SMM, the processor saves the context of the interrupted program or task.
•All interrupts normally handled by the operatin g system are disabled upon entry into SMM.
•The RSM instruction can be executed only in SMM.
Section 32.3 describes transitions into and out of SMM. The execution environment after entering SMM is in real-
address mode with paging disabled (CR0.PE = CR0.PG = 0). In this initial execution environment, the SMI handler 
can address up to 4 GBytes of memory and can execute a ll I/O and system instructions. Section 32.5 describes in 
detail the initial SMM execution environment for an SMI handler and operation within that environment. The SMI 
handler may subsequently switch to other operating modes while remaining in SMM.
NOTES
Software developers should be aware that, even  if a logical processor was using the physical-
address extension (PAE) mechanism (introduced in  the P6 family processors) or was in IA-32e 
mode before an SMI, this will not be the case af ter the SMI is delivered. This is because delivery of 
an SMI disables paging (see Table 32-4). (This does not apply if the dual-monitor treatment of SMIs 
and SMM is active; see Section 32.15.)32-2 Vol. 3CSYSTEM MANAGEMENT MODE
32.1.1 System Management Mode and VMX Operation
Traditionally, SMM services system management interrupts and then resumes program execution (back to the soft-
ware stack consisting of executive and application software; see Section 32.2 through Section 32.13). 
A virtual machine monitor (VMM) using VMX can act as a host  to multiple virtual machines and each virtual machine 
can support its own software stack of executive and application software. On processors that support VMX, virtual-
machine extensions may use system-management interrupt s (SMIs) and system-management mode (SMM) in one 
of two ways:
•Default treatment. System firmware handles SMIs. The processor saves architectural states and critical 
states relevant to VMX operation upon entering SMM. When the firmware completes servicing SMIs, it uses 
RSM to resume VMX operation.
•Dual-monitor treatment.  Two VM monitors collaborate to control the servicing of SMIs: one VMM operates 
outside of SMM to provide basic virtualization in suppor t for guests; the other VMM operates inside SMM (while 
in VMX operation) to support system-managemen t functions. The former is referred to as executive monitor , 
the latter SMM-transfer monitor  (STM).1
The default treatment is described in Section 32.14, “Def ault Treatment of SMIs and SMM with VMX Operation and 
SMX Operation.” Dual-monitor treatment of SMM is descri bed in Section 32.15, “Dual-Monitor Treatment of SMIs 
and SMM.”
32.2 SYSTEM MANAGEMENT INTERRUPT (SMI)
The only way to enter SMM is by signaling an SMI through the SMI# pin on the processor or through an SMI message received through the APIC bus. The SMI is a nonm askable external interrupt that operates independently 
from the processor’s interrupt- and exception-handling mechanism and the local APIC. The SMI takes precedence

and SMM.”
from the processor’s interrupt- and exception-handling mechanism and the local APIC. The SMI takes precedence 
over an NMI and a maskable interrupt. SMM is non-reentrant;  that is, the SMI is disabled while the processor is in 
SMM.
NOTES
In the Pentium 4, Intel Xeon, and P6 family proce ssors, when a processor that is designated as an 
application processor during an MP initialization sequ ence is waiting for a startup IPI (SIPI), it is in 
a mode where SMIs are masked. However if a SMI is received while an application processor is in the wait for SIPI mode, the SMI will be pended. The processor then responds on receipt of a SIPI by 
immediately servicing the pended SMI and going into SMM before handling the SIPI.
An SMI may be blocked for one instruction followin g execution of STI, MOV to SS, or POP into SS.
32.3 SWITCHING BETWEEN SMM AND THE OTHER PROCESSOR OPERATING 
MODES
Figure 2-3 shows how the processor moves between SMM and the other processor operating modes (protected, 
real-address, and virtual-8086). Signaling an SMI while the processor is in real-address, protected, or virtual-8086 
modes always causes the processor to switch to SMM. Upon  execution of the RSM instruction, the processor always 
returns to the mode it was in when the SMI occurred. 
32.3.1 Entering SMM
The processor always handles an SMI on an architectura lly defined “interruptible” point in program execution 
(which is commonly at an IA-32 architecture instruction boundary). When the processor receives an SMI, it waits 
for all instructions to retire and for all stores to complete. The processor then saves its current context in SMRAM 
(see Section 32.4), enters SMM, and begins to execute the SMI handler.
1. The dual-monitor treatment may not be su pported by all processors. Software should consult the VMX capability MSR IA32_VMX-
_BASIC (see Appendix A.1) to determine whether it is supported.Vol. 3C 32-3SYSTEM MANAGEMENT MODE
Upon entering SMM, the processor signals external hard ware that SMI handling has begun. The signaling mecha-
nism used is implementation dependent. For the P6 fami ly processors, an SMI acknowledge transaction is gener-
ated on the system bus and the multiplexed status signal EX F4 is asserted each time a bus transaction is generated 
while the processor is in SMM. For the Pentium and Intel486 processors, the SMIACT# pin is asserted.
An SMI has a greater priority than debu g exceptions and external interrupts. Thus, if an NMI, maskable hardware 
interrupt, or a debug exception occurs at an instruction boundary along with an SMI, only the SMI is handled. 
Subsequent SMI requests are not acknowledged while the pr ocessor is in SMM. The first SMI interrupt request that 
occurs while the processor is in SMM (that is, after SMM has been acknowledged to external hardware) is latched 
and serviced when the processor exits SMM with the RSM in struction. The processor will latch only one SMI while 
in SMM.
See Section 32.5 for a detailed description of the execution environment when in SMM.
32.3.2 Exiting From SMM
The only way to exit SMM is to execute the RSM instruction. The RSM instruction  is only available to the SMI 
handler; if the processor is not in SMM, attempts to exec ute the RSM instruction result in an invalid-opcode excep-
tion (#UD) being generated.
The RSM instruction restores the processor’s context by loading the state save image from SMRAM back into the 
processor’s registers. The processor then returns an SM IACK transaction on the system bus and returns program 
control back to the interrupted program.
NOTE
On processors that support the shadow-stack feature, RSM loads the SSP register from the state save image in SMRAM (see Table 32-3). The value is made canonical by sign-extension before 
loading it into SSP.
Upon successful completion of the RSM instruction, the processor signals external hardware that SMM has been 
exited. For the P6 family processors, an SMI acknowledg e transaction is generated on the system bus and the 
multiplexed status signal EXF4 is no longer generated on bus cycles. For the Pentium and Intel486 processors, the 
SMIACT# pin is deserted.
If the processor detects invalid state information saved in  the SMRAM, it enters the shutdown state and generates 
a special bus cycle to indicate it has entered shutdown st ate. Shutdown happens only in the following situations:
•A reserved bit in control register CR4 is set to 1 on a write to CR4. This error should not happen unless SMI 
handler code modifies reserved areas of the SMRAM saved state map (see Section 32.4.1). CR4 is saved in the state map in a reserved location and cannot be read or modified in its saved state.
•An illegal combination of bits is written to control register  CR0, in particular PG set to 1 and PE set to 0, or NW 
set to 1 and CD set to 0.
•CR4.PCIDE would be set to 1 and IA32_EFER.LMA to 0.
•(For the Pentium and Intel486 processors only.) If the address stored in the SMBASE register when an RSM 
instruction is executed is not aligned on a 32-KByte boun dary. This restriction does not apply to the P6 family 
•CR4.CET would be set to 1 and CR0.WP to 0.
In the shutdown state, Intel processors stop executing instructions until a RESET#, INIT# or NMI# is asserted. 
While Pentium family processors recognize the SMI# signal in shutdown state, P6 family and Intel486 processors 
do not. Intel does not support using SMI# to recover from  shutdown states for any processor family; the response 
of processors in this circumstance is not well defined. On Pentium 4 and later processors, shutdown will inhibit INTR and A20M but will not change any of the other inhibits. On th ese processors, NMIs will be inhibited if no action is 
taken in the SMI handler to uninhibit them (see Section 32.8).
If the processor is in the HALT state when the SMI is re ceived, the processor handles the return from SMM slightly 
differently (see Section 32.10). Also, the SMBASE addre ss can be changed on a return from SMM (see Section 
32.11).32-4 Vol. 3CSYSTEM MANAGEMENT MODE
32.4 SMRAM
Upon entering SMM, the processor switches to a new addr ess space. Because paging is disabled upon entering 
SMM, this initial address space maps all memory accesses to the low 4 GBytes of the processor's physical address 
space. The SMI handler's critical code and data reside in a memory region referred to as system-management RAM 
(SMRAM). The processor uses a pre-defined region within  SMRAM to save the processor's pre-SMI context. SMRAM 
can also be used to store system management informatio n (such as the system configuration and specific informa-
tion about powered-down devices)  and OEM-specific information. 
The default SMRAM size is 64 KBytes beginning at a base  physical address in physical memory called the SMBASE 
(see Figure 32-1). The SMBASE default value following a ha rdware reset is 30000H. The processor looks for the 
first instruction of the SMI handler at the address [SMBAS E + 8000H]. It stores the processor’s state in the area 
from [SMBASE + FE00H] to [SMBASE + FFFFH]. See Section 32.4.1 for a description of the mapping of the state 
save area.
The system logic is minimally required to decode th e physical address range for the SMRAM from [SMBASE + 
8000H] to [SMBASE + FFFFH]. A larger area can be decoded if needed. The size of this SMRAM can be between 32 
KBytes and 4 GBytes.
The location of the SMRAM can be changed by changing th e SMBASE value (see Section 32.11). It should be noted 
that all processors in a multiple-processor system are init ialized with the same SMBASE value (30000H). Initializa-
tion software must sequentially place each processor in SMM and change its SMBASE so that it does not overlap 
those of other processors.
The actual physical location of the SMRAM can be in sy stem memory or in a separate RAM memory. The processor 
generates an SMI acknowledge transaction (P6 family processors) or asserts the SMIACT# pin (Pentium and 
Intel486 processors) when the processor receives an SMI (see Section 32.3.1). 
System logic can use the SMI acknowledge transaction or the assertion of the SMIACT# pin to decode accesses to 
the SMRAM and redirect them (if desired) to specific SMRAM memory. If a separate RAM memory is used for 
SMRAM, system logic should provide a programmable method of mapping the SMRAM into system memory space 
when the processor is not in SMM. Th is mechanism will enable start-up proc edures to initialize the SMRAM space 
(that is, load the SMI handler) before  executing the SMI handler during SMM.
32.4.1 SMRAM State Save Map
When an IA-32 processor that does not support Intel 64 arch itecture initially enters SMM, it writes its state to the 
state save area of the SMRAM.   The state save area begins at [SMBASE + 8000H + 7FFFH] and extends down to 
[SMBASE + 8000H + 7E00H]. Table 32-1 shows the state save  map. The offset in column 1 is relative to the 
SMBASE value plus 8000H. Reserved spaces should not be used by software.

Some of the registers in the SMRAM state save area (mar ked YES in column 3) may be read and changed by the 
SMI handler, with the changed values restored to the pr ocessor registers by the RSM instruction. Some register 
images are read-only, and must not be modified (modifying  these registers will result in unpredictable behavior). 
An SMI handler should not rely on any values st ored in an area that is marked as reserved.
 
Figure 32-1.  SMRAM UsageStart of State Save AreaSMBASE + FFFFH
SMBASESMBASE + 8000HSMRAM
SMI Handler Entry PointVol. 3C 32-5SYSTEM MANAGEMENT MODE
The following registers are saved (but not readable) and restored upon exiting SMM:
•Control register CR4. (This register is cleared to all 0s when entering SMM).
•The hidden segment descriptor information stored in segment registers CS, DS, ES, FS, GS, and SS.
If an SMI request is issued for the purp ose of powering down the processor, the values of all reserved locations in 
the SMM state save must be saved to nonvolatile memory.
The following state is not automatically saved and restored  following an SMI and the RSM instruction, respectively:Table 32-1.  SMRAM State Save Map
Offset 
(Added to SMBASE + 8000H)Register Writable?
7FFCH CR0 No
7FF8H CR3 No
7FF4H EFLAGS Yes
7FF0H EIP Yes
7FECH EDI Yes
7FE8H ESI Yes
7FE4H EBP Yes7FE0H ESP Yes
7FDCH EBX Yes
7FD8H EDX Yes7FD4H ECX Yes7FD0H EAX Yes
7FCCH DR6 No
7FC8H DR7 No7FC4H TR
1No
7FC0H Reserved No
7FBCH GS1No
7FB8H FS1No
7FB4H DS1No
7FB0H SS1No
7FACH CS1No
7FA8H ES1No
7FA4H I/O State Field, see Section 32.7 No7FA0H I/O Memory Address Field, see Section 32.7 No
7F9FH-7F03H Reserved No
7F02H Auto HALT Restart Field (Word) Yes7F00H I/O Instruction Restart Field (Word) Yes
7EFCH SMM Revision Identifier Field (Doubleword) No
7EF8H SMBASE Field (Doubleword) Yes
7EF7H - 7E00H Reserved No
NOTE:
1. The two most significant bytes are reserved.32-6 Vol. 3CSYSTEM MANAGEMENT MODE
•Debug registers DR0 through DR3.
•The x87 FPU registers.
•The MTRRs.
•Control register CR2.
•The model-specific registers (for the P6 family and Pent ium processors) or test registers TR3 through TR7 (for 
the Pentium and Intel486 processors).
•The state of the trap controller.
•The machine-check architecture registers.
•The APIC internal interrupt state (ISR, IRR, etc.).
•The microcode update state.
If an SMI is used to power down the processor, a power- on reset will be required befo re returning to SMM, which 
will reset much of this state back to its default values. So an SMI handler that is going to trigger power down should 
first read these registers listed above directly, and save them (along with the rest of RAM) to nonvolatile storage. 
After the power-on reset, the continuation of the SMI hand ler should restore these values, along with the rest of 
the system's state. Anytime the SMI handler changes these registers in the processor, it must also save and restore 
them.
NOTES
A small subset of the MSRs (such as, the time-stamp counter and performance-monitoring counters) are not arbitrarily writable and therefore cannot be saved and restored. SMM-based 
power-down and restoration should only be perfor med with operating systems that do not use or 
rely on the values of these registers. 
Operating system developers should be aware of th is fact and ensure that their operating-system 
assisted power-down and restoration software is immune to unexpected changes in these register values.
32.4.1.1  SMRAM State Save Map and Intel 64 Architecture
When the processor initially enters SMM, it writes its state to the state save area of the SMRAM. The state save area 
on an Intel 64 processor at [SMBASE + 8000H + 7F FFH] and extends to [SMBASE + 8000H + 7C00H]. 
Support for Intel 64 architecture is reported by CPUID. 80000001:EDX[29] = 1. The layout of the SMRAM state save 
map is shown in Table 32-3. 
Additionally, the SMRAM state save map shown in Table 32- 3 also applies to processors with the following CPUID 
signatures listed in Table 32-2, irrespective of the value in CPUID.80000001:EDX[29].
Table 32-2.   Processor Signatures an d 64-bit SMRAM Stat e Save Map Format
06_17H Intel Xeon Processor 5200, 5400 series, Intel Co re 2 Quad processor Q9xxx, Intel Core 2 Duo 
processors E8000, T9000,
06_0FH Intel Xeon Processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad, Intel Core 2 Extreme, 
Intel Core 2 Duo processors, Intel Pentium dual-core processors
06_1CH 45 nm Intel Atom® processorsVol. 3C 32-7SYSTEM MANAGEMENT MODE
Table 32-3.  SMRAM State Save Map for Intel 64 Architecture
Offset 
7FF8H CR0 No
7FF0H CR3 No7FE8H RFLAGS Yes
7FE0H IA32_EFER Yes
7FD8H RIP Yes7FD0H DR6 No
7FC8H DR7 No
7FC4H TR SEL
1No
7FC0H LDTR SEL1No
7FBCH GS SEL1No
7FB8H FS SEL1No
7FB4H DS SEL1No
7FB0H SS SEL1No
7FACH CS SEL1No
7FA8H ES SEL1No
7FA4H IO_MISC No
7F9CH IO_MEM_ADDR No
7F94H RDI Yes
7F8CH RSI Yes
7F84H RBP Yes
7F7CH RSP Yes
7F74H RBX Yes
7F6CH RDX Yes
7F64H RCX Yes
7F5CH RAX Yes
7F54H R8 Yes
7F4CH R9 Yes
7F44H R10 Yes
7F3CH R11 Yes
7F34H R12 Yes
7F2CH R13 Yes
7F24H R14 Yes
7F1CH R15 Yes
7F1BH-7F04H Reserved No
7F02H Auto HALT Restart Field (Word) Yes
7F00H I/O Instruction Restart Field (Word) Yes
7EF8H SMBASE Field (Doubleword) Yes32-8 Vol. 3CSYSTEM MANAGEMENT MODE
32.4.2 SMRAM Caching
An IA-32 processor does not automatically write back and invalidate its caches before entering SMM or before 
exiting SMM. Because of this behavior, care must be taken in the placement of the SMRAM in system memory and in the caching of the SMRAM to prevent cache incohe rence when switching back and forth between SMM and 
protected mode operation. Any of the following three meth ods of locating the SMRAM in system memory will guar-
antee cache coherency.
•Place the SMRAM in a dedicated section of system memo ry that the operating system and applications are 
prevented from accessing. Here, the SMRAM can be de signated as cacheable (WB, WT, or WC) for optimum 
processor performance, without risking cache incoherence when entering or exiting SMM.
•Place the SMRAM in a section of memory that overlaps an  area used by the operating system (such as the video 
memory), but designate the SMRAM as uncacheable (UC). This method prevents cache access when in SMM to 
maintain cache coherency, but the use of uncacheab le memory reduces the performance of SMM code.
•Place the SMRAM in a section of system memory that ov erlaps an area used by the operating system and/or 
application code, but explicitly flush (write back and invalidate) the caches upon entering and exiting SMM 
mode. This method maintains cache coherency, but in curs the overhead of two complete cache flushes.
For Pentium 4, Intel Xeon, and P6 family processors, a co mbination of the first two methods of locating the SMRAM 
is recommended. Here the SMRAM is split between an overlapping and a dedicated region of memory. Upon 
entering SMM, the SMRAM space that is accessed overlaps video memory (typically located in low memory). This 
SMRAM section is designated as UC memory. The initial SM M code then jumps to a second SMRAM section that is 7EF7H - 7EE4H Reserved No
7EE0H Setting of “enable EPT” VM-execution control No
7ED8H Value of EPTP VM-execution control field No
7ED7H - 7ECC0H Reserved No
7EC8H SSP Yes
7EC7H - 7EA0H Reserved No
7E9CH LDT Base (lower 32 bits) No
7E98H Reserved No7E94H IDT Base (lower 32 bits) No7E90H Reserved No
7E8CH GDT Base (lower 32 bits) No
7E8BH - 7E48H Reserved No
7E40H CR4 (64 bits) No
7E3FH - 7DF0H Reserved No
7DE8H IO_RIP Yes
7DE7H - 7DDCH Reserved No
7DD8H IDT Base (Upper 32 bits) No
7DD4H LDT Base (U pper 32 bits) No
7DD0H GDT Base (Upper 32 bits) No
7DCFH - 7C00H Reserved No
NOTE:
1. The two most significant bytes are reserved.Table 32-3.  SMRAM State Save Map for Intel 64 Architecture (Contd.)
Offset 
(Added to SMBASE + 8000H)Register Writable?Vol. 3C 32-9SYSTEM MANAGEMENT MODE
located in a dedicated region of system memory (typically  in high memory). This SMRAM section can be cached for 
optimum processor performance.
For systems that explicitly flush the caches upon entering  SMM (the third method described above), the cache flush 
can be accomplished by asserting the FLUSH# pin at the sa me time as the request to enter SMM (generally initi-
ated by asserting the SMI# pin). The priorities of the FLUS H# and SMI# pins are such that the FLUSH# is serviced 
first. To guarantee this behavior, the processor requires that the following co nstraints on the interaction of FLUSH# 
and SMI# be met. In a system where the FLUSH# and SM I# pins are synchronous and the set up and hold times 
are met, then the FLUSH# and SMI# pins may be assert ed in the same clock. In asynchronous systems, the 
FLUSH# pin must be asserted at least one clock before th e SMI# pin to guarantee that the FLUSH# pin is serviced 
first.

first. 
Upon leaving SMM (for systems that expl icitly flush the caches), the WBINVD instruction should be executed prior 
to leaving SMM to flush the caches.
NOTES
In systems based on the Pentium processor that use the FLUSH# pin to write back and invalidate cache contents before entering SMM, the processo r will prefetch at least one cache line in between 
when the Flush Acknowledge cycle is run and the su bsequent recognition of SMI# and the assertion 
of SMIACT#. 
It is the obligation of the system to ensure th at these lines are not cached by returning KEN# 
inactive to the Pentium processor.
32.4.2.1  System Manageme nt Range Registers (SMRR)
SMI handler code and data stored by SMM code resides in  SMRAM. The SMRR interface is an enhancement in Intel 
64 architecture to limit cacheable reference of addresse s in SMRAM to code running in SMM. The SMRR interface 
can be configured only by code running in SMM. Details of SMRR is described in Section 12.11.2.4.
32.5 SMI HANDLER EXECUTION ENVIRONMENT
Section 32.5.1 describes the initial execution environment for an SMI handler. An SMI handler may re-configure its 
execution environment to other supported operating modes. Section 32.5.2 discusses modifications an SMI 
handler can make to its execution environment. Section 32.5.3 discusses Control-flow Enforcement Technology 
(CET) interactions in the environment.
32.5.1 Initial SMM Execution Environment
After saving the current context of the processor, the proce ssor initializes its core registers to the values shown in 
Table 32-4. Upon entering SMM, the PE and PG flags in co ntrol register CR0 are cleared, which places the processor 
in an environment similar to real-address mode. The di fferences between the SMM execution environment and the 
real-address mode execution environment are as follows:
•The addressable address space ranges from 0 to FFFFFFFFH (4 GBytes). 
•The normal 64-KByte segment limit for real-address mode is increased to 4 GBytes.
•The default operand and address sizes are set to 16 bi ts, which restricts the addressable SMRAM address space 
to the 1-MByte real-address mode limit for native real-address-mode code. However, operand-size and 
address-size override prefixes can be used to access the address space beyond the 1-MByte.
Table 32-4.  Processor Register Initialization in SMM
Register Contents
General-purpose registers Undefined
EFLAGS 00000002H
EIP 00008000H
CS selector SMM Base shifted right 4 bits (default 3000H)32-10 Vol. 3CSYSTEM MANAGEMENT MODE
•Near jumps and calls can be made to anywhere in the 4-GByte address space if a 32-bit operand-size override 
prefix is used. Due to the real-address-mode style of base-address formation, a far call or jump cannot transfer 
control to a segment with a base address of more than 20 bits (1 MByte). However, since the segment limit in 
SMM is 4 GBytes, offsets into a segment that go beyo nd the 1-MByte limit are allowed when using 32-bit 
operand-size override prefixes. Any program control transf er that does not have a 32-bit operand-size override 
prefix truncates the EIP value to the 16 low-order bits.
•Data and the stack can be located anywhere in the 4-GB yte address space, but can be accessed only with a 32-
bit address-size override if they are located above 1 MB yte. As with the code segment, the base address for a 
data or stack segment cannot be more than 20 bits.
The value in segment register CS is automatically set to the default of 30000H for the SMBASE shifted 4 bits to the 
right; that is, 3000H. The EIP register is set to 8000H. When the EIP value is added to shifted CS value (the 
SMBASE), the resulting linear address points to the first instruction of the SMI handler.
The other segment registers (DS, SS, ES, FS, and GS) are cl eared to 0 and their segment limits are set to 4 GBytes. 
In this state, the SMRAM address space may be treated as a single flat 4-GByte linear address space. If a segment 
register is loaded with a 16-bit value, that value is then  shifted left by 4 bits and loaded into the segment base 
(hidden part of the segment register). The limits and attributes are not modified.
Maskable hardware interrupts, exceptions, NMI interrupts,  SMI interrupts, A20M inte rrupts, single-step traps, 
breakpoint traps, and INIT operations are inhibited when the processor enters SMM. Maskable hardware interrupts, exceptions, single-step traps, and breakpoint traps ca n be enabled in SMM if the SMM execution environment 
provides and initializes an interrupt table and the necess ary interrupt and exception handlers (see Section 32.6).
32.5.2 SMI Handler Operating Mode Switching
Within SMM, an SMI handler may change the processor's op erating mode (e.g., to enable PAE paging, enter 64-bit 
mode, etc.) after it has made proper preparation and initia lization to do so. For example, if switching to 32-bit 
protected mode, the SMI handler should follow the guidel ines provided in Chapter 10, “Processor Management and 
Initialization.” If the SMI handler does wish to change operating mode, it is responsible for executing the appro-
priate mode-transition code after each SMI.
It is recommended that the SMI handler make use of all mean s available to protect the integrity of its critical code 
and data. In particular, it should use the system-managemen t range register (SMRR) interface if it is available (see 
Section 11.11.2.4). The SMRR interface can protect only the first 4 GBytes of the physical address space. The SMI 
handler should take that fact into account if it uses operating modes that allow access to physical addresses beyond 
that 4-GByte limit (e.g., PAE paging or 64-bit mode).
Execution of the RSM instruction restores the pre-SM I processor state from the SMRAM state-state map (see 
Section 32.4.1) into which it was stored when the proce ssor entered SMM. (The SMBASE field in the SMRAM state-
save map does not determine the state following RSM but ra ther the initial environment following the next entry to 
SMM.) Any required change to operating mode is performe d by the RSM instruction; there is no need for the SMI 
handler to change modes explic itly prior to executing RSM.CS base SMM Base (default 30000H)
DS, ES, FS, GS, SS Selectors 0000HDS, ES, FS, GS, SS Bases 000000000H
DS, ES, FS, GS, SS Limits 0FFFFFFFFH
CR0 PE, EM, TS, and PG flags set to 0; others unmodifiedCR4 Cleared to zero
DR6 Undefined
DR7 00000400HTable 32-4.  Processor Regist er Initialization in SMMVol. 3C 32-11SYSTEM MANAGEMENT MODE
32.5.3 Control-flow Enforcement Technology Interactions
On processors that support CET shadow stacks, when the processor enters SMM, the processor saves the SSP 
register to the SMRAM state save area (see Table 32-3) an d clears CR4.CET to 0. Thus, the initial execution envi-
ronment of the SMI handler has CET disabled and all of th e CET state of the interrupted program is still in the 
machine. An SMM that uses CET is required to save th e interrupted program’s CET state and restore the CET state 
prior to exiting SMM.
32.6 EXCEPTIONS AND IN TERRUPTS WITHIN SMM
When the processor enters SMM, all hardware interrupts are disabled in the following manner:
•The IF flag in the EFLAGS register is cleared, wh ich inhibits maskable hardware interrupts from being 
•The TF flag in the EFLAGS register is cleared, which disables single-step traps.
•Debug register DR7 is cleared, which disables breakpoint  traps. (This action prevents a debugger from acciden-
tally breaking into an SMI handler if a debug breakpoint is set in normal address space that overlays code or 
data in SMRAM.)
•NMI, SMI, and A20M interrupts are blocked by intern al SMM logic. (See Section 32.8 for more information 
about how NMIs are handled in SMM.)
Software-invoked interrupts and exceptions can still occur,  and maskable hardware interrupts can be enabled by 
setting the IF flag. Intel recommends that SMM code be wri tten in so that it does not invoke software interrupts 
(with the INT n, INTO, INT1, INT3, or BOUND instructions) or generate exceptions. 
If the SMI handler requires interrupt and exception hand ling, an SMM interrupt table and the necessary exception 
and interrupt handlers must be created and initialized from within SMM. Until the interrupt table is correctly initial-
ized (using the LIDT instruction), exceptions and soft ware interrupts will result in unpredictable processor 
behavior. 
The following restrictions apply when designing SMM interrupt and exception-handling facilities:
•The interrupt table should be located at linear address 0 and must contain real-address mode style interrupt 
vectors (4 bytes containing CS and IP).
•Due to the real-address mode style of base address formation, an interrupt or exception cannot transfer control to a segment with a base address of more that 20 bits.
•An interrupt or exception cannot transfer control to a segment offset of more than 16 bits (64 KBytes).

behavior. 
•When an exception or interrupt occurs, only the 16 least- significant bits of the return address (EIP) are pushed 
onto the stack. If the offset of the interrupted procedur e is greater than 64 KBytes, it is not possible for the 
interrupt/exception handler to return control to that proc edure. (One solution to this problem is for a handler 
to adjust the return address on the stack.)
•The SMBASE relocation feature affects the way the proc essor will return from an interrupt or exception 
generated while the SMI handler is executing. For example, if the SMBASE is relocated to above 1 MByte, but 
the exception handlers are below 1 MByte, a normal return  to the SMI handler is not possible. One solution is 
to provide the exception handler with a mechanism for calculating a return address above 1 MByte from the 16-
bit return address on the stack, then use a 32-bit far call to return to the interrupted procedure.
•If an SMI handler needs access to the debug trap faci lities, it must ensure that an SMM accessible debug 
handler is available and save the current contents of debug registers DR0 through DR3 (for later restoration). 
Debug registers DR0 through DR3 and DR7 must then  be initialized with the appropriate values.
•If an SMI handler needs access to the single-step mechan ism, it must ensure that an SMM accessible single-
step handler is available, and then set the TF flag in the EFLAGS register.
•If the SMI design requires the processor to respond to  maskable hardware interrupts or software-generated 
interrupts while in SMM, it must ensure that SMM acce ssible interrupt handlers are available and then set the 
IF flag in the EFLAGS register (using the STI instruct ion). Software interrupts are not blocked upon entry to 
SMM, so they do not need to be enabled.32-12 Vol. 3CSYSTEM MANAGEMENT MODE
32.7 MANAGING SYNCHRONOUS AND AS YNCHRONOUS SYSTEM MANAGEMENT 
INTERRUPTS
When coding for a multiprocessor system or a system with  Intel HT Technology, it was not always possible for an 
SMI handler to distinguish between a sy nchronous SMI (triggered during an I/O instruction) and an asynchronous 
SMI. To facilitate the discrimination of these two events , incremental state information has been added to the SMM 
state save map. 
Processors that have an SMM revision  ID of 30004H or higher have the incremental state information described 
below.
32.7.1 I/O State Implementation
Within the extended SMM state save map, a bit (IO_SMI) is provided that is set only when an SMI is either taken 
immediately after a successful I/O instruction or is taken after a successful iteration of a REP I/O instruction (the 
successful  notion pertains to the processor point of view; no t necessarily to the corresponding platform function).  
When set, the IO_SMI bit provides a st rong indication that the corresponding SMI was synchronous. In this case, 
the SMM State Save Map also supplies the port address of the I/O operation. The IO_SMI bit and the I/O Port 
Address may be used in conjunction with the information logged by the platform to confirm that the SMI was 
indeed synchronous.
The IO_SMI bit by itself is a strong indication, not a guar antee, that the SMI is synchronous. This is because an 
asynchronous SMI might coincidentally be taken after an I/ O instruction. In such a case, the IO_SMI bit would still 
be set in the SMM state save map.
Information characterizing the I/O instruction is saved in two locations in the SMM State Save Map (Table 32-5). 
The IO_SMI bit also serves as a valid bit for the rest of the I/O information fields. The contents of these I/O infor-
mation fields are not defined when the IO_SMI bit is not set.
When IO_SMI is set, the other fields may be interpreted as follows:
•I/O length:
•001 – Byte
•010 – Word
•100 – Dword
•I/O instruction type (Table 32-6)Table 32-5.  I/O Instruction Inform ation in the SMM State Save Map
State (SMM Rev. ID: 30004H or higher) Format
31 16 15 8 7 4 3 1 0
I/0 State Field
SMRAM offset 7FA4I/O PortReservedI/O TypeI/O LengthIO_SMI
31 0
I/O Memory Address Field
SMRAM offset 7FA0I/O Memory Address
Table 32-6.  I/O Instruction Type Encodings
Instruction Encoding
IN Immediate 1001
IN DX 0001
OUT Immediate 1000Vol. 3C 32-13SYSTEM MANAGEMENT MODE
32.8 NMI HANDLING WHILE IN SMM
NMI interrupts are blocked upon entry to the SMI handler. If  an NMI request occurs during the SMI handler, it is 
latched and serviced after the processor exits SMM. Only one NMI request will be latched during the SMI handler. 
If an NMI request is pending when the processor executes the RSM instruction, the NMI is serviced before the next 
instruction of the interrupted code sequence. This assumes that NMIs were not blocked before the SMI occurred. If 
NMIs were blocked before the SMI occurred,  they are blocked after execution of RSM.
Although NMI requests are blocked when the processor en ters SMM, they may be enabled through software by 
executing an IRET instruction. If the SMI handler requir es the use of NMI interrupts,  it should invoke a dummy 
interrupt service routine for the purpose of executing an IRET instruction. Once an IRET instruction is executed, 
NMI interrupt requests are serviced in the same “real mode” manner in which they are handled outside of SMM.
Also, for the Pentium processor, exceptions that invoke a tr ap or fault handler will enab le NMI interrupts from inside 
of SMM. This behavior is implementation specific for th e Pentium processor and is not part of the IA-32 architec-
ture.
32.9 SMM REVISION IDENTIFIER
The SMM revision identifier field is used to indicate th e version of SMM and the SMM extensions that are supported 
by the processor (see Figure 32-2). The SMM revision iden tifier is written during SMM entry and can be examined 
in SMRAM space at offset 7EFCH. The lo wer word of the SMM revision identifier refers to the version of the base 
SMM architecture.
The upper word of the SMM revision identifier refers to th e extensions available. If the I/O instruction restart flag 
(bit 16) is set, the processor supports the I/O instruction restart (see Section 32.12); if the SMBASE relocation flag 
(bit 17) is set, SMRAM base address relocation is supported (see Section 32.11).OUT DX 0000
INS 0011
OUTS 0010
REP INS 0111
REP OUTS 0110
Figure 32-2.  SMM Revision IdentifierTable 32-6.  I/O Instruction Type Encodings (Contd.)
SMM Revision Identifier
I/O Instruction RestartSMBASE RelocationRegister Offset
7EFCH
31 0
Reserved18 17 16 1532-14 Vol. 3CSYSTEM MANAGEMENT MODE
32.10 AUTO HALT RESTART
If the processor is in a HALT state (due to the prior exec ution of a HLT instruction) when it receives an SMI, the 
processor records the fact in the auto HALT restart flag in the saved processor state (see Figure 32-3). (This flag is 
located at offset 7F02H and bit 0 in the state save area of the SMRAM.)
If the processor sets the auto HALT restart flag upon entering SMM (indicating that the SMI occurred when the 
processor was in the HALT state), the SMI handler has two options:
•It can leave the auto HALT restart flag set, which instru cts the RSM instruction to return program control to the 
HLT instruction. This option in effect causes the proce ssor to re-enter the HALT state after handling the SMI. 
(This is the default operation.)
•It can clear the auto HALT restart flag, which instruct s the RSM instruction to return program control to the 
instruction following the HLT instruction. 
These options are summarized in Table 32-7. If the proce ssor was not in a HALT state when the SMI was received 
(the auto HALT restart flag is cleared), setting the flag to 1 will cause unpredictable behavior when the RSM instruc-
tion is executed.
If the HLT instruction is restarted, the processor will genera te a memory access to fetch the HLT instruction (if it is 
not in the internal cache), and execute a HLT bus transaction.  This behavior results in multiple HLT bus transactions 
for the same HLT instruction.
32.10.1 Executing the HLT Instruction in SMM
The HLT instruction should not be executed during SMM, unless interrupts have been enabled by setting the IF flag in the EFLAGS register. If the processor is halted in SMM,  the only event that can remove the processor from this 
state is a maskable hardware interrupt or a hardware reset.
32.11 SMBASE RELOCATION
The default base address for the SMRAM is 30000H. This value is contained in an internal processor register called the SMBASE register. Software can relocate the SMRAM by  setting the SMBASE field in the saved state map (at 
offset 7EF8H) to a new value (see Figure 32-4). The RSM in struction reloads the internal SMBASE register with the 
value in the SMBASE field each time it exits SMM. All subsequent SMI requests will use the new SMBASE value to 
find the starting address for the SMI handler (at SMBASE  + 8000H) and the SMRAM state save area (from SMBASE  
Figure 32-3.  Auto HALT Restart Field
Table 32-7.  Auto HALT Restart Flag Values
Value of Flag After

Value of Flag After 
Entry to SMMValue of Flag When 
Exiting SMMAction of Processor When Exiting SMM
0
0
110
1
01Returns to next instruction in interrupted program or task.
Unpredictable.
Returns to next instruction after HLT instruction.Returns to HALT state.Auto HALT Restart0 15
ReservedRegister Offset
7F02H1Vol. 3C 32-15SYSTEM MANAGEMENT MODE
+ FE00H to SMBASE + FFFFH). (The processor resets the value in its internal SMBASE register to 30000H on a 
RESET, but does not change it on an INIT.) 
In multiple-processor systems, initialization software must adjust the SMBASE value for each processor so that the 
SMRAM state save areas for each processor do not overlap. (For Pentium and Intel486 processors, the SMBASE 
values must be aligned on a 32-KByte boundary or the pr ocessor will enter shutdown state during the execution of 
a RSM instruction.)
If the SMBASE relocation flag in the SMM revision identifi er field is set, it indicates the ability to relocate the 
SMBASE (see Section 32.9).
32.12 I/O INSTRUCTION RESTART
If the I/O instruction restart flag in the SMM revision identifier field is set (see Section 32.9), the I/O instruction restart mechanism is present on the processor. This mechanism allows an interrupted I/O instruction to be re-
executed upon returning from SMM mode. For example, if an I/O instruction is used to access a powered-down I/O 
device, a chipset supporting this device can intercept the access and respond by asserting SMI#. This action 
invokes the SMI handler to power-up the device. Upon retu rning from the SMI handler, the I/O instruction restart 
mechanism can be used to re-execute the I/O instruction that caused the SMI.
The I/O instruction restart field (at offset 7F00H in the SMM state-save area, see Figure 32-5) controls I/O instruc-
tion restart. When an RSM instruction is executed, if this field contains the value FFH, then the EIP register is modi-
fied to point to the I/O instruction that received the SM I request. The processor will then automatically re-execute 
the I/O instruction that the SMI trapped. (The processor saves the necessary machine state to ensure that re-
execution of the instruction is handled coherently.)
If the I/O instruction restart field contains the value 00H when the RSM instruction is executed, then the processor 
begins program execution with the instruction following th e I/O instruction. (When a repeat prefix is being used, 
the next instruction may be the next I/O instruction in the repeat loop.) Not re-executing the interrupted I/O 
instruction is the default behavior; the processor automati cally initializes the I/O instruction restart field to 00H 
upon entering SMM. Table 32-8 summarizes th e states of the I/O instruction restart field. 
Figure 32-4.  SMBASE Relocation Field
 
Figure 32-5.  I/O Instruction Restart Field0 31
SMM BaseRegister Offset
7EF8H
0 15
I/O Instruction Restart FieldRegister Offset
7F00H32-16 Vol. 3CSYSTEM MANAGEMENT MODE
The I/O instruction restart mechanism does not indicate th e cause of the SMI. It is the responsibility of the SMI 
handler to examine the state of the processor to determine the cause of the SMI and to determine if an I/O instruc-
tion was interrupted and should be restarted upon exiting S MM. If an SMI interrupt is signaled on a non-I/O instruc-
tion boundary, setting the I/O instruction restart field to FFH  prior to executing the RSM instruction will likely result 
in a program error.
32.12.1 Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used
If an SMI interrupt is signaled while th e processor is servicing an SMI interrupt that occurred on an I/O instruction 
boundary, the processor will service the new SMI request be fore restarting the originally interrupted I/O instruc-
tion. If the I/O instruction restart field is set to FFH prior to returning from the second SMI handler, the EIP will point 
to an address different from the originally interrupted I/O in struction, which will likely lead to a program error. To 
avoid this situation, the SMI handler must be able to re cognize the occurrence of back-to-back SMI interrupts when 
I/O instruction restart is being used and ensure that the handler sets the I/O instruction restart field to 00H prior 
to returning from the second invocation of the SMI handler.
32.13 SMM MULTIPLE-PROCESSOR CONSIDERATIONS
The following should be noted when designing multiple-processor systems:
•Any processor in a multiprocessor system can respond to an SMI.
•Each processor needs its own SMRAM space. This spac e can be in system memory or in a separate RAM.
•The SMRAMs for different processors can be overlapped in  the same memory space. The only stipulation is that 
each processor needs its own state save area and its own dynamic data storage area. (Also, for the Pentium and Intel486 processors, the SMBASE address must be located on a 32-KByte boundary.) Code and static data 
can be shared among processors. Overlapping SMRAM spaces  can be done more efficiently with the P6 family 
processors because they do not require that the SMBASE address be on a 32-KByte boundary. 
•The SMI handler will need to initia lize the SMBASE for each processor.
•Processors can respond to local SMIs through their SMI# pins or to SMIs received through the APIC interface. 
The APIC interface can distribute  SMIs to different processors.
•Two or more processors can be executing in SMM at the same time.
•When operating Pentium processors in dual processing (DP) mode, the SMIACT# pin is  driven only by the MRM 
processor and should be sampled with ADS#. For additi onal details, see Chapter 14 of the Pentium Processor 
Family User’s Manual, Volume 1.
SMM is not re-entrant, because the SMRAM State Save Map is  fixed relative to the SMBASE. If there is a need to 
support two or more processors in SMM mode at the same  time then each processor should have dedicated SMRAM 
spaces. This can be done by using the SMBASE Relocation feature (see Section 32.11).
32.14 DEFAULT TREATMENT OF SMIS AND SMM WITH VMX OPERATION AND 
SMX OPERATION
Under the default treatment, the interactions of SMIs an d SMM with VMX operation are few. This section details 
those interactions. It also explains how this treatment affects SMX operation.Table 32-8.  I/O Instruction Restart Field Values
00H
00H00H
FFHDoes not re-execute tr apped I/O instruction.
Re-executes trappe d I/O instruction.Vol. 3C 32-17SYSTEM MANAGEMENT MODE
32.14.1 Default Treatment of SMI Delivery
Ordinary SMI delivery saves processor state into SMRAM an d then loads state based on architectural definitions. 
Under the default treatment, processors that support VMX operation perform SMI delivery as follows:
enter SMM;
save the following internal to the processor:
CR4.VMXEan indication of whether the logical processor was in VMX operation (root or non-root)
IF the logical processor is in VMX operation
THEN
save current VMCS pointer internal to the processor;
leave VMX operation;save VMX-critical state defined below;
FI;IF the logical processor supports SMX operation
THEN
save internal to the logi cal processor an indication of whether the Intel® TXT private space is locked;
IF the TXT private space is unlocked
THEN lock the TXT private space;
FI;
FI;CR4.VMXE := 0;perform ordinary SMI delivery:
save processor state in SMRAM;set processor state to standard SMM values;
1
invalidate linear mappings and combined mappings associated with VPID 0000H (for all PCIDs); combined mappings for VPID 0000H 
are invalidated for all EPTRTA values (EPTRTA is th e value of bits 51:12 of EPTP; see Section 29.4);
The pseudocode above makes reference to the saving of VMX-critical state . This state consists of the following: 
(1) SS.DPL (the current privilege level); (2) RFLAGS.VM2; (3) the state of blocking by STI and by MOV SS (see 
Table 25-3 in Section 25.4.2); (4) the state of virtual-NMI blocking (only if the processor is in VMX non-root oper-ation and the “virtual NMIs” VM-execution control is 1); an d (5) an indication of whether an MTF VM exit is pending 
(see Section 26.5.2). These data may be saved internal to  the processor or in the VMCS region of the current 
VMCS. Processors that do not support SMI recognition whil e there is blocking by STI or by MOV SS need not save 
the state of such blocking.
If the logical processor supports the 1-setting of the “e nable EPT” VM-execution control and the logical processor 
was in VMX non-root operation at the time of an SMI, it sa ves the value of that control into bit 0 of the 32-bit field 
at offset SMBASE + 8000H + 7EE0H (SMBASE + FEE0H; see Table 32-3).
3 If the logical processor was not in VMX 
non-root operation at the time of the SMI, it saves 0 into that bit. If the logical processor saves 1 into that bit (it 
was in VMX non-root operation and the “enable EPT” VM-execution control was 1), it saves the value of the EPT

was in VMX non-root operation and the “enable EPT” VM-execution control was 1), it saves the value of the EPT 
pointer (EPTP) into the 64-bit field at offset SMBASE + 8000H + 7ED8H (SMBASE + FED8H).
Because SMI delivery causes a logical processor to leave VMX operation, all the controls associated with VMX non-
root operation are disabled in SMM and thus cannot cause VM exits while the logical processor in SMM.
1. This causes the logical processor to  block INIT signal s, NMIs, and SMIs.
2. Section 32.14 and Section 32.15 use the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that 
support VMX operation also support Intel 64 architecture. For processors that do not support Intel 64  architecture, this notati on 
refers to the 32-bit forms of these registers (EAX, EIP, ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to r efer spe-
cifically to the lower 32  bits of the register.
3. “Enable EPT” is a secondary processor-base d VM-execution control. If bit 31 of the primary processor-based VM-execution contro ls 
is 0, SMI functions as the “enable EPT” VM-execution control were 0. See Section 25.6.2.32-18 Vol. 3CSYSTEM MANAGEMENT MODE
32.14.2 Default Treatment of RSM
Ordinary execution of RSM restores processor state from  SMRAM. Under the default tr eatment, processors that 
support VMX operation perform RSM as follows:
IF VMXE = 1 in CR4 image in SMRAM
THEN fail and enter shutdown state;ELSE
restore state normally from SMRAM;invalidate linear mappings and combined mappings associated with all VPIDs and all PCIDs; combined mappings are invalidated 
for all EPTRTA values (EPTRT A is the value of bits 51:12 of EPTP; see Section 29.4);
IF the logical processor supports SMX operat ion andthe Intel® TXT private space was un locked at the time of the last SMI (as 
saved)
THEN unlock the TXT private space;
FI;CR4.VMXE := value stored internally;
IF internal storage indicate s that the logical processor
had been in VMX operation (root or non-root)
THEN
enter VMX operation (root or non-root);restore VMX-critical state as defined in Section 32.14.1;set to their fixed values any bits in CR0 and CR4 whose values must be fixed in VMX operation (see Section 24.8);
1
IF RFLAGS.VM = 0 AND (in VMX root operation OR the “unrestricted guest” VM-e xecution control is 0)2
THEN
CS.RPL := SS.DPL;SS.RPL := SS.DPL;
FI;restore current VMCS pointer;
FI;leave SMM;IF logical processor will be in VMX operation or in SMX operation after RSM
THEN block A20M and leave A20M mode;
FI;
FI;
RSM unblocks SMIs. It restores the state of blocking by NMI (see Table 25-3 in Section 25.4.2) as follows:
•If the RSM is not to VMX non-root operation or if the “vir tual NMIs” VM-execution control will be 0, the state of 
NMI blocking is restored normally.
•If the RSM is to VMX non-root operation and the “virtual  NMIs” VM-execution control will be 1, NMIs are not 
blocked after RSM. The state of virtual-NMI blocki ng is restored as part of VMX-critical state.
INIT signals are blocked after RSM if and only if th e logical processor will be in VMX root operation.
If RSM returns a logical processor to VMX non-root operatio n, it re-establishes the controls associated with the 
current VMCS. If the “interrupt-window exiting” VM-executi on control is 1, a VM exit occurs immediately after RSM 
if the enabling conditions apply. The same is true fo r the “NMI-window exiting” VM-execution control. Such 
VM exits occur with their normal priority. See Section 26.2.
If an MTF VM exit was pending at the time of the previous SMI, an MTF VM exit is pending on the instruction 
boundary following execution of RSM.  The following items detail the treatment of MTF VM exits that may be 
pending following RSM:
1. If the RSM is to VMX non-root operation and both the “unrestricted gu est” VM-execution control an d bit 31 of the primary proce s-
sor-based VM-execution controls will be 1, CR0.PE and CR0.PG retain the values that were loaded from SMRAM regardless of what i s 
reported in the capability  MSR IA32_VMX_CR0_FIXED0.
2. “Unrestricted guest” is a secondary proces sor-based VM-execution control. If bit 31 of the primary processor-based VM-executio n 
controls is 0, VM entry functi ons as if the “unrestricted guest” VM-execution control were 0. See Section 25.6.2.Vol. 3C 32-19SYSTEM MANAGEMENT MODE
•System-management interrupts (SMIs), INIT signals, and higher priority events take priority over these MTF 
VM exits. These MTF VM exits take priority over de bug-trap exceptions and lower priority events. 
•These MTF VM exits wake the logical processor if RSM caused the logical processor to enter the HLT state (see 
Section 32.10). They do not occur if the logical processor just entered the shutdown state.
32.14.3 Protection of CR4.VMXE in SMM
Under the default treatment, CR4.VMXE is treated as a reserved bit while a logical processor is in SMM. Any 
attempt by software running in SMM to set this bit causes  a general-protection exception. In addition, software 
cannot use VMX instructions or enter VMX operation while in SMM.
32.14.4 VMXOFF and SMI Unblocking
The VMXOFF instruction can be executed only with the default treatment (see Section 32.15.1) and only outside 
SMM. If SMIs are blocked when VMXOFF is  executed, VMXOFF unblocks them unless 
IA32_SMM_MONITOR_CTL[bit 2] is 1 (see Section 32.15.5 for details regarding this MSR).1 Section 32.15.7 iden-
tifies a case in which SMIs may be blocked when VMXOFF is executed.
Not all processors allow this bit to be set to 1. Soft ware should consult the VMX capability MSR IA32_VMX_MISC 
(see Appendix A.6) to determine whether this is allowed.
32.15 DUAL-MONITOR TREA TMENT OF SMIs AND SMM
Dual-monitor treatment is activated through the cooperation of the executive monitor  (the VMM that operates 
outside of SMM to provide basic virtualization) and the SMM-transfer monitor  (STM; the VMM that operates 
inside SMM—while in VMX operation—to support system-man agement functions). Control is transferred to the STM 
through VM exits; VM entries are used to return from SMM.
The dual-monitor treatment may not be supported by all processors. Software should consult the VMX capability 
MSR IA32_VMX_BASIC (see Appendix A.1) to  determine whether it is supported.
32.15.1 Dual-Monitor Treatment Overview
The dual-monitor treatment uses an executive monitor an d an SMM-transfer monitor (STM). Transitions from the 
executive monitor or its guests to the STM are called SMM VM exits  and are discussed in Section 32.15.2. SMM 
VM exits are caused by SMIs as well as executions of VM CALL in VMX root operation. The latter allow the executive 
monitor to call the STM for service.
The STM runs in VMX root operation and uses VMX instructions to establish a VMCS and perform VM entries to its 
own guests. This is done all inside SMM (see Section 32 .15.3). The STM returns from SMM, not by using the RSM 
instruction, but by using a VM entry that returns from SMM. Such VM entries are described in Section 32.15.4.
Initially, there is no STM and the default treatment (Section  32.14) is used. The dual-monitor treatment is not used 
until it is enabled and activated. The steps to do th is are described in Section 32.15.5 and Section 32.15.6.
It is not possible to leave VMX operation under the dual-m onitor treatment; VMXOFF will fail if executed. The dual-
monitor treatment must be deactivated first. The STM de activates dual-monitor treatment using a VM entry that 
returns from SMM with the “deactivate dual-monitor trea tment” VM-entry control set to 1 (see Section 32.15.7).
The executive monitor configures any VMCS that it uses for VM exits to the executive monitor. SMM VM exits, which 
transfer control to the STM, use a different VMCS. Under the dual-monitor treatment, each logical processor uses 
a separate VMCS called the SMM-transfer VMCS . When the dual-monitor treatment is active, the logical 
processor maintains another VMCS pointer called the SMM-transfer VMCS pointer . The SMM-transfer VMCS 
pointer is established when the dual-monitor treatment is activated.
1. Setting IA32_SMM_MONITOR_CTL[bit 2] to 1 prevents VMXOFF from unblocking SMIs regardless of the value of the register’s valid  
bit (bit 0).32-20 Vol. 3CSYSTEM MANAGEMENT MODE
32.15.2 SMM VM Exits
An SMM VM exit is a VM exit that begins outside SMM and that ends in SMM.
Unlike other VM exits, SMM VM exits can be gin in VMX root operation. SMM VM exits result from the arrival of an 
SMI outside SMM or from execution of VMCALL in VMX ro ot operation outside SMM. Execution of VMCALL in VMX 
root operation causes an SMM VM exit only if the vali d bit is set in the IA32_SMM_MONITOR_CTL MSR (see Section 
32.15.5).
Execution of VMCALL in VMX root operation causes an SMM VM exit even under the default treatment. This SMM 
VM exit activates the dual-monitor treatment (see Section 32.15.6).
Differences between SMM VM exits and other VM exits are detailed in Sections 32.15.2.1 through 32.15.2.5. 
Differences between SMM VM exits that activate the dual-monitor treatment and other SMM VM exits are described 
in Section 32.15.6.
32.15.2.1  Architectural State Before a VM Exit

32.15.5).
System-management interrupts (SMIs) that  cause SMM VM exits always do so directly. They do not save state to 
SMRAM as they do under the default treatment.
32.15.2.2  Updating the Current-VMCS and Executive-VMCS Pointers
SMM VM exits begin by perfor ming the following steps:
1. The executive-VMCS pointer field in the SMM-transfer VMCS is loaded as follows:
— If the SMM VM exit commenced in VMX non-root operation, it receives the current-VMCS pointer.— If the SMM VM exit commenced in VMX root operation, it receives the VMXON pointer.
2. The current-VMCS pointer is loaded with th e value of the SMM-transfer VMCS pointer.
The last step ensures that the current  VMCS is the SMM-transfer VMCS. VM-e xit information is recorded in that 
VMCS, and VM-entry control fields in that VMCS are updated.  State is saved into the guest-state area of that VMCS. 
The VM-exit controls and host-state area of that VMCS determine how the VM exit operates.
32.15.2.3  Recording VM-Exit Information
SMM VM exits differ from other VM exit with regard to th e way they record VM-exit information. The differences 
follow.
•Exit reason .
— Bits 15:0 of this field contain the basic exit reason. Th e field is loaded with the reason for the SMM VM exit: 
I/O SMI (an SMI arrived immediately after retirement of an I/O instruction), other SMI, or VMCALL. See 
Appendix C, “VMX Basic Exit Reasons.”
— SMM VM exits are the only VM exits that may occur in VMX root operation. Because the SMM-transfer 
monitor may need to know whether it was invoked from VMX root or VMX non-root operation, this 
information is stored in bit 29 of the exit-reason fiel d (see Table 25-18 in Section 25.9.1). The bit is set by 
SMM VM exits from VMX root operation.
— If the SMM VM exit occurred in VMX non-root operation and an MTF VM exit was pending, bit 28 of the exit-
reason field is set; otherwise, it is cleared.
— Bits 27:16 and bits 31:30 are cleared.
•Exit qualification.  For an SMM VM exit due an SMI that arrives immediately after the retirement of an I/O 
instruction, the exit qualification contains information about the I/O instruction that retired immediately before 
the SMI. It has the format given in Table 32-9.
•Guest linear address. This field is used for VM exits due to SMIs that arrive immediately after the retirement 
of an INS or OUTS instruction for which the relevant segment (ES for INS; DS for OUTS unless overridden by 
an instruction prefix) is usable. The field receives th e value of the linear address generated by ES:(E)DI (for 
INS) or segment:(E)SI (for OUTS; the default segment is DS but can be overridden by a segment override Vol. 3C 32-21SYSTEM MANAGEMENT MODE
prefix) at the time the instruction started. If the rele vant segment is not usable, the value is undefined. On 
processors that support Intel 64 architecture, bits 63:32  are clear if the logical processor was not in 64-bit 
mode before the VM exit.
•I/O RCX, I/O RSI, I/O RDI, and I/O RIP.  For an SMM VM exit due an SMI that arrives immediately after 
the retirement of an I/O instruction, these fields receive the values that were in RCX, RSI, RDI, and RIP, respec-
tively, before the I/O instruction executed. Thus, the value saved for I/O RIP addresses the I/O instruction.
32.15.2.4  Saving Guest State
SMM VM exits save the contents of the SMBASE register into the corresponding field in the guest-state area.
The value of the VMX-preemption timer is saved into the corresponding field in the guest-state area if the “save 
VMX-preemption timer value” VM-exit control is 1. That field becomes undefined if, in addition, either the SMM 
VM exit is from VMX root operation or the SMM VM exit is from VMX non-root operation and the “activate VMX-
preemption timer” VM-execution control is 0.
32.15.2.5  Updating State
If an SMM VM exit is from VMX non-root operation and the “Intel PT uses guest physical addresses” VM-execution 
control is 1, the IA32_RTIT_CTL MSR is cleared to 00000000_00000000H.1 This is done even if the “clear IA32_R-
TIT_CTL” VM-exit control is 0.
SMM VM exits affect the non-register state of a logical processor as follows:
•SMM VM exits cause non-maskable interrupts (NMIs) to be  blocked; they may be unblocked through execution 
of IRET or through a VM entry (depending on the value loaded for the interruptibility state and the setting of 
the “virtual NMIs” VM-execution control).
•SMM VM exits cause SMIs to be blocked; they may be unblocked by a VM entry that returns from SMM (see 
Section 32.15.4).Table 32-9.  Exit Qualification for SMIs That Arrive Immediately After the Retireme nt of an I/O Instruction
0=  1 - b y t e
1=  2 - b y t e
3=  4 - b y t e
3 Direction of the attemp ted access (0 = OUT, 1 = IN)
4 String instruction (0 = not string; 1 = string)5 REP prefixed (0 = not REP; 1 = REP)
15:7 Reserved (cleared to 0)31:16 Port number (as specif ied in the I/O instruction)
63:32 Reserved (cleared to 0). These bits exist only on processors 
1. In this situation, the value of this MSR was saved earlie r into the guest-state area. All VM exits save this MSR if the 1-sett ing of the 
“load IA32_RTIT_CTL” VM-entry control is supported (see Section 28 .3.1), which must be the case if  the “Intel PT uses guest phy si-
cal addresses” VM-execution control is 1 (see Section 27.2.1.1).32-22 Vol. 3CSYSTEM MANAGEMENT MODE
SMM VM exits invalidate linear mappings and combined mappings associated with VPID 0000H for all PCIDs. 
Combined mappings for VPID 0000H are invalidated for all EPTRTA values (EPTRTA is the value of bits 51:12 of 
EPTP; see Section 29.4). (Ordinary VM exits are not required  to perform such invalidation if the “enable VPID” VM-
execution control is 1; see Section 28.5.5.)
32.15.3 Operation of the SMM-Transfer Monitor
Once invoked, the SMM-transfer monito r (STM) is in VMX root operation and can use VMX instructions to configure 
VMCSs and to cause VM entries to virtual machines supporte d by those structures. As noted in Section 32.15.1, the 
VMXOFF instruction cannot be used under the dual-monitor treatment and thus cannot be used by the STM.
The RSM instruction also cannot be used under the dual-monitor treatment. As noted in Section 26.1.3, it causes a 
VM exit if executed in SMM in VMX non-root operation. If  executed in VMX root operat ion, it causes an invalid-
opcode exception. The STM uses VM entries to return from SMM (see Section 32.15.4).
32.15.4 VM Entries that Return from SMM
The SMM-transfer monitor (STM) returns from SMM using a VM entry with the “entry to SMM” VM-entry control 
clear. VM entries that return from SMM reverse th e effects of an SMM VM exit (see Section 32.15.2).
VM entries that return from SMM may differ from other VM entries in that they do not necessarily enter VMX non-
root operation. If the executive-VMCS pointer field in the current VMCS contains the VMXON pointer, the logical 
processor remains in VMX root operation after VM entry.
For differences between VM entries that return from SM M and other VM entries see Sections 32.15.4.1 through 
32.15.4.10.
32.15.4.1  Checks on the Executive-VMCS Pointer Field
VM entries that return from SMM perfor m the following checks on the executive-VMCS pointer field in the current 
VMCS:
•Bits 11:0 must be 0.
•The pointer must not set any bits beyond  the processor’s physical-address width.1,2
•The 32 bits located in memory referenced by the physic al address in the pointer must contain the processor’s 
VMCS revision identifier (see Section 25.2).
The checks above are performed before the checks described  in Section 32.15.4.2 and before any of the following 
checks:
•'If the “deactivate dual-monitor treatm ent” VM-entry control is 0 and the executive-VMCS pointer field does not 
contain the VMXON pointer, the launch state of the ex ecutive VMCS (the VMCS referenced by the executive-
VMCS pointer field) must be launched (see Section 25.11.3).
•If the “deactivate dual-monitor treatment” VM-entry control is 1, the executive-VMCS pointer field must 
contain the VMXON pointer (see Section 32.15.7).3
32.15.4.2  Checks on VM-Execution Control Fields
VM entries that return from SMM differ from other VM en tries with regard to the checks performed on the VM-
execution control fields specified in Section 27.2.1.1. They do not apply the checks to the current VMCS. Instead, 
VM-entry behavior depends on whether the executiv e-VMCS pointer field contains the VMXON pointer:
2. If IA32_VMX_BASIC[48] is read as 1, this pointer mu st not set any bits in the range 63:32; see Appendix A.1.
3. The STM can determine the VMXON pointer by reading the executive-VMCS pointer field in the current VMCS after the SMM VM exit

3. The STM can determine the VMXON pointer by reading the executive-VMCS pointer field in the current VMCS after the SMM VM exit 
that activates the du al-monitor treatment.Vol. 3C 32-23SYSTEM MANAGEMENT MODE
•If the executive-VMCS pointer field contains the VMXON pointer (the VM entry remains in VMX root operation), 
the checks are not performed at all.
•If the executive-VMCS pointer field does not contain the VMXON pointer (the VM entry enters VMX non-root 
operation), the checks are performed on the VM-executi on control fields in the executive VMCS (the VMCS 
referenced by the executive-VMCS pointer field in the current VMCS). These checks are performed after 
checking the executive-VMCS pointer field itself (for proper alignment).
Other VM entries ensure that, if “activate VMX-preemptio n timer” VM-execution control is 0, the “save VMX-
preemption timer value” VM-exit control is also 0. This check is not performed by VM entries that return from SMM.
32.15.4.3  Checks on VM-Entry Control Fields
VM entries that return from SMM differ from other VM entrie s with regard to the checks  performed on the VM-entry 
control fields specified in Section 27.2.1.3.
Specifically, if the executive-VMCS pointer field contains  the VMXON pointer (the VM entry remains in VMX root 
operation), the VM-entry interruption-information field mu st not indicate injection of a pending MTF VM exit (see 
Section 27.6.2). Specifically, the follow ing cannot all be true for that field:
•the valid bit (bit 31) is 1
•the interruption type (bits 10:8) is 7 (other event); and
•the vector (bits 7:0) is 0 (pending MTF VM exit).
32.15.4.4  Checks on the Guest State Area
Section 27.3.1 specifies checks performed on fields in th e guest-state area of the VMCS. Some of these checks are 
conditioned on the settings of certain VM-execution controls (e.g., “virtu al NMIs” or “unrestricted guest”). 
VM entries that return from SMM modify these checks base d on whether the executive-VMCS pointer field contains 
the VMXON pointer:1
the checks are performed as all relevant VM-execution co ntrols were 0. (As a result, some checks may not be 
performed at all.)
operation), this check is performed based on the setting s of the VM-execution controls in the executive VMCS 
(the VMCS referenced by the executive-VMCS pointer field in the current VMCS).
For VM entries that return from SMM, the activity-state fi eld must not indicate the wait-for-SIPI state if the execu-
tive-VMCS pointer field contains the VMXON pointer (the VM entry is to VMX root operation).
32.15.4.5  Loading Guest State
VM entries that return from SMM load the SMBASE register from the SMBASE field.
VM entries that return from SMM invalidate linear mappin gs and combined mappings associated with all VPIDs. 
Combined mappings are invalidated for all EPTRTA values (EPTRTA is the value of bits 51:12 of EPTP; see Section 
29.4). (Ordinary VM entries are required to perform such in validation only for VPID 0000H and are not required to 
do even that if the “enable VPID” VM-execu tion control is 1; see Section 27.3.2.5.)
32.15.4.6  VMX-Preemption Timer
A VM entry that returns from SMM activates the VMX-preemp tion timer only if the executive-VMCS pointer field 
does not contain the VMXON pointer (the VM entry enters  VMX non-root operation) and the “activate VMX-preemp-
tion timer” VM-execution control is 1 in the executive VM CS (the VMCS referenced by  the executive-VMCS pointer 
field). In this case, VM entry starts the VMX-preemption timer with the value in the VMX-preemption timer-value 
field in the current VMCS.
1. The STM can determine the VMXON pointer by reading the executive-VMCS pointer field in the current VMCS after the SMM VM exit 
that activates the dual-monitor treatment.32-24 Vol. 3CSYSTEM MANAGEMENT MODE
32.15.4.7  Updating the Current-VMCS and SMM-Transfer VMCS Pointers
Successful VM entries (returning from SMM) load the SMM-transfer VMCS po inter with the current-VMCS pointer. 
Following this, they load the current-VMCS pointer from a field in the current VMCS:
the current-VMCS pointer is loaded from the VMCS-link pointer field.
operation), the current-VMCS pointer is loaded with  the value of the executive-VMCS pointer field.
If the VM entry successfully enters VMX non-root operation,  the VM-execution controls in effect after the VM entry 
are those from the new current VMCS. This includes any st ructures external to the VM CS referenced by VM-execu-
tion control fields.
The updating of these VMCS pointers occurs before event injection. Event injection is determined, however, by the 
VM-entry control fields in the VMCS that was current when the VM entry commenced.
32.15.4.8  VM Exits Induced by VM Entry
Section 27.6.1.2 describes how the event-delivery proce ss invoked by event injection may lead to a VM exit. 
Section 27.7.3 to Section 27.7.7 describe other situations  that may cause a VM exit to occur immediately after a 
VM entry.
Whether these VM exits occur is determined by the VM-execu tion control fields in the current VMCS. For VM entries 
that return from SMM, they can occur only if the execut ive-VMCS pointer field does not contain the VMXON pointer 
(the VM entry enters VMX non-root operation).
In this case, determination is based on the VM-execution  control fields in the VMCS that is current after the 
VM entry. This is the VMCS referenced by the value of the executive-VMCS pointer field at the time of the VM entry 
(see Section 32.15.4.7). This VMCS also controls the de livery of such VM exits. Thus, VM exits induced by a 
VM entry returning from SMM are to the executive monitor and not to the STM.
32.15.4.9  SMI Blocking
VM entries that return from SMM determine the blocking  of system-management interrupts (SMIs) as follows:
•If the “deactivate dual-monitor treatmen t” VM-entry control is 0, SMIs are blocked after VM entry if and only if 
the bit 2 in the interruptibility-state field is 1.
•If the “deactivate dual-monitor treatment” VM-entry cont rol is 1, the blocking of SMIs depends on whether the 
logical processor is in SMX operation:1
— If the logical processor is in SMX operation, SMIs are blocked after VM entry.
— If the logical processor is outside SMX op eration, SMIs are unblocked after VM entry.
VM entries that return from SMM and that do not deactiva te the dual-monitor treatment may leave SMIs blocked. 
This feature exists to allow the STM to invoke f unctionality outside of SMM without unblocking SMIs.
32.15.4.10  Failures of VM Entries That Return from SMM
Section 27.8 describes the treatment of VM entries that fail during or after loading guest state. Such failures record 
information in the VM-exit information fields and load processor state as would be done on a VM exit. The VMCS 
used is the one that was current before the VM entry comm enced. Control is thus transferred to the STM and the 
logical processor remains in SMM.
ware Developer’s Manual, Volume 2D.Vol. 3C 32-25SYSTEM MANAGEMENT MODE
32.15.5 Enabling the Du al-Monitor Treatment
Code and data for the SMM-transfer monitor (S TM) reside in a region of SMRAM called the monitor segment  
(MSEG). Code running in SMM determines  the location of MSEG and establishes its content. This code is also 
responsible for enabling the dual-monitor treatment. 
SMM code enables the dual-monitor treatment and sp ecifies the location of MSEG by writing to the 
IA32_SMM_MONITOR_CTL MSR (index 9BH). The MSR has the following format:
•Bit 0 is the register’s valid bit.  The STM may be invoked using VMCALL only if this bit is 1. Because VMCALL is 
used to activate the dual-monitor treatment (see Sect ion 32.15.6), the dual-monitor treatment cannot be 
activated if the bit is 0. This bit is cleared when the logical processor is reset.
•Bit 1 is reserved.
•Bit 2 determines whether executions of VMXOFF unblock SMIs under the default treatment of SMIs and SMM. 
Executions of VMXOFF unblock SMIs unless bit 2 is 1 (t he value of bit 0 is irrelevant). See Section 32.14.4.
Certain leaf functions of the GETSEC instruction clea r this bit (see Chapter 7, “Safer Mode Extensions 
Reference,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D).
•Bits 11:3 are reserved.

•Bits 31:12 contain a value that, when shifted left 12 bits, is the physical address of MSEG (the MSEG base address).
•Bits 63:32 are reserved.
The following items detail use of this MSR:
•The IA32_SMM_MONITOR_CTL MSR is supported only on pr ocessors that support the dual-monitor treatment.1 
On other processors, accesses to the MSR using RDMSR or WRMSR generate a general-protection fault (#GP(0)).
•A write to the IA32_SMM_MONITOR_CTL MSR using WRMSR generates a general-protection fault (#GP(0)) if 
executed outside of SMM or if an attempt is made to  set any reserved bit. An attempt to write to the 
IA32_SMM_MONITOR_CTL MSR fails if made as part of a VM exit that does not end in SMM or part of a VM entry that does not begin in SMM.
•Reads from the IA32_SMM_MONITOR_CTL MSR using RDMS R are allowed any time RDMSR is allowed. The 
MSR may be read as part of any VM exit.
•The dual-monitor treatment can be activated on ly if the valid bit in the MSR is set to 1.
The 32 bytes located at the MSEG base address are called the MSEG header . The format of the MSEG header is 
given in Table 32-10 (each field is 32 bits).
1. Software should consult the VMX capability MSR IA32_VMX_BASIC (see Appendix A.1) to determine whether the dual-monitor 
treatment is supported.Table 32-10.  Format of MSEG Header
Byte Offset Field
0 MSEG-header revision identifier4 SMM-transfer monitor features
8G D T R  l i m i t
12 GDTR base offset16 CS selector
20 EIP offset
24 ESP offset28 CR3 offset32-26 Vol. 3CSYSTEM MANAGEMENT MODE
To ensure proper behavior in VMX operation, software should maintain the MSEG header in writeback cacheable 
memory. Future implementations may allow or require a different memory type.1 Software should consult the VMX 
capability MSR IA32_VMX_BASIC (see Appendix A.1).
SMM code should enable the dual-monitor treatment (by setting the valid bit in IA32_SMM_MONITOR_CTL MSR) 
only after establishing the content of the MSEG header as follows:
•Bytes 3:0 contain the MSEG revision identifier . Different processors may use di fferent MSEG revision identi-
fiers. These identifiers enable software to avoid us ing an MSEG header formatted for one processor on a 
processor that uses a different format. Software can discover the MSEG revision identifier that a processor uses by reading the VMX capability MSR IA 32_VMX_MISC (see Appendix A.6).
•Bytes 7:4 contain the SMM-transfer monitor features  field. Bits 31:1 of this field are reserved and must be 
zero. Bit 0 of the field is the IA-32e mode SMM feature bit . It indicates whether the logical processor will be 
in IA-32e mode after the STM is activated (see Section 32.15.6).
•Bytes 31:8 contain fields that determine how processor state is loaded when the STM is activated (see Section 32.15.6.5). SMM code should establish these fields so that  activating of the STM invokes the STM’s initialization 
code. 
32.15.6 Activating the Dual-Monitor Treatment
The dual-monitor treatment may be enabled by SMM code as described in Section 32.15.5. The dual-monitor treat-
ment is activated only if it is enabled and only by the executive monitor. The executive monitor activates the dual-
monitor treatment by executing VMCALL in VMX root operation.
When VMCALL activates the dual-monitor treatment, it  causes an SMM VM exit. Differences between this SMM 
VM exit and other SMM VM exits are discussed in Sections 32.15.6.1 through 32.15.6.6. See also “VMCALL—Call to 
VM Monitor” in Chapter 31.
32.15.6.1  Initial Checks
An execution of VMCALL attempts to activate the dual-m onitor treatment if (1) the processor supports the dual-
monitor treatment;2 (2) the logical processor is in VMX root operat ion; (3) the logical processor is outside SMM and 
the valid bit is set in the IA32_SMM_MONITOR_CTL MSR; (4 ) the logical processor is not in virtual-8086 mode and 
not in compatibility mode; (5) CPL = 0; and (6) the dual-monitor treatment is not active.
Such an execution of VMCALL begins with some initial checks. These checks are performed before updating the 
current-VMCS pointer and the executive-VMCS pointer field (see Section 32.15.2.2).
The VMCS that manages SMM VM exit caused by this VMCA LL is the current VMCS established by the executive 
monitor. The VMCALL performs the following chec ks on the current VMCS in the order indicated:
1. There must be a current VMCS pointer.2. The launch state of the current VMCS must be clear.
3. The VM-exit controls in the curre nt VMCS must be set properly:
•Reserved bits in the primary VM-exit controls mu st be set properly. Software may consult the VMX 
capability MSRs to determine the proper setting (see Appendix A.4.1).
controls must be cleared. Software may consult th e VMX capability MSRs to determine which bits are 
reserved (see Appendix A.4.2).
1. Alternatively, software may map the MSEG header with the UC me mory type; this may be necessary, depending on how memory is 
organized. Doing so is strongly discoura ged unless necessary as it will cause the performance of transitions using those struct ures 
to suffer significantly. In addition, the processor will continue to use the memory type reported in the VMX capability MSR 
IA32_VMX_BASIC with exceptio ns noted in Appendix A.1.
2. Software should consult the VMX capability MSR IA32_VMX_BASIC  (see Appendix A.1) to dete rmine whether the dual-monitor 
treatment is supported.Vol. 3C 32-27SYSTEM MANAGEMENT MODE
•If the “activate secondary controls” primary VM-exit control is 0 (or if the processor does not support 
the 1-setting of that control), no checks are performed on the secondary VM-exit controls. The logical processor operates as if all the secondary VM-exit controls were 0.
If any of these checks fail, subsequent checks are skippe d and VMCALL fails. If all these checks succeed, the logical 
processor uses the IA32_SMM_MONITOR_CTL MSR to determ ine the base address of MS EG. The following checks 
are performed in the order indicated:
1. The logical processor reads the 32 bits at the base of MSEG and compares them to the processor’s MSEG 
revision identifier.
2. The logical processor reads the SMM-transfer monitor features field:
— Bit 0 of the field is the IA-32e mode SMM feature bit, and it indicates whether the logical processor will be 
in IA-32e mode after the SMM-transfer monitor (STM) is activated.
•If the VMCALL is executed on a processor that does  not support Intel 64 architecture, the IA-32e mode 
SMM feature bit must be 0.
•If the VMCALL is executed in 64-bit mode, the IA-32e mode SMM feature bit must be 1.
— Bits 31:1 of this field are currently reserved and must be zero.
If any of these checks fail, subsequent checks are skipped and the VMCALL fails.
32.15.6.2  Updating the Current-VMCS and Executive-VMCS Pointers
Before performing the steps in Section 32.15.2.2, SMM VM ex its that activate the dual-monitor treatment begin by 
loading the SMM-transfer VMCS pointer wi th the value of the current-VMCS pointer.
32.15.6.3  Saving Guest State
As noted in Section 32.15.2.4, SMM VM exits save the conten ts of the SMBASE register into the corresponding field 
in the guest-state area. While this is true also for SMM VM exits that activate the dual-monitor treatment, the VMCS used for those VM exits exists outside SMRAM.
The SMM-transfer monitor (STM) can also discover the curre nt value of the SMBASE re gister by using the RDMSR 
instruction to read the IA32_SMBASE MSR (MSR addre ss 9EH). The following items detail use of this MSR:
•The MSR is supported only if IA32_VMX_MISC[15] = 1 (see Appendix A.6).
•A write to the IA32_SMBASE MSR using WRMSR generates a general-protection fault (#GP(0)). An attempt to 
write to the IA32_SMBASE MSR fails if made as  part of a VM exit or part of a VM entry.
•A read from the IA32_SMBASE MSR using RDMSR generate s a general-protection fault (#GP(0)) if executed 
outside of SMM. An attempt to read fr om the IA32_SMBASE MSR fails if made as  part of a VM exit that does not 
end in SMM.
32.15.6.4  Saving MSRs
The VM-exit MSR-store area is not used by SMM VM exits that activate the dual-monitor treatment. No MSRs are 
saved into that area.
32.15.6.5  Loading Host State
The VMCS that is current during an SMM VM exit that activates the dual-monitor treatment was established by the 
executive monitor. It does not contain the VM-exit controls  and host state required to initialize the STM. For this 
reason, such SMM VM exits do not load processor state as de scribed in Section 28.5. Instead, state is set to fixed 
values or loaded based on the content of the MSEG header (see Table 32-10):
•CR0 is set to as follows:
— PG, NE, ET, MP, and PE are all set to 1.— CD and NW are left unchanged.32-28 Vol. 3CSYSTEM MANAGEMENT MODE
— All other bits are cleared to 0.
•CR3 is set as follows:
— Bits 63:32 are cleared on processors that support IA-32e mode.

end in SMM.
— Bits 31:12 are set to bits 31:12 of the sum of the MSEG  base address and the CR3-offset field in the MSEG 
header.
— Bits 11:5 and bits 2:0 are cleared (the corresponding bits in the CR3-offset field in the MSEG header are 
ignored).
— Bits 4:3 are set to bits 4:3 of the CR3-offset field in the MSEG header.
•CR4 is set as follows:— MCE, PGE, CET, PCIDE, and LA57 are cleared.
— PAE is set to the value of the IA-32e mode SMM feature bit.
— If the IA-32e mode SMM feature bit is clear, PSE is set to 1 if supported by the processor; if the bit is set, 
PSE is cleared.
— All other bits are unchanged.
•The IA32_DEBUGCTL MSR is cleared to 00000000_00000000H.
•The registers CS, SS, DS, ES, FS, and GS are loaded as follows:— All registers are usable.— CS.selector is loaded from the corresponding field in the MSEG header (the high 16 bits are ignored), with 
bits 2:0 cleared to 0. If the result is 0000H, CS.selector is set to 0008H.
— The selectors for SS, DS, ES, FS, and GS are set to CS.selector+0008H. If the result is 0000H (if the CS 
selector was FFF8H), these selectors are instead set to 0008H.
— The base addresses of all registers are cleared to zero.
— The segment limits for all registers are set to FFFFFFFFH.
— The AR bytes for the registers are set as follows:
•CS.Type is set to 11 (execute/read, accessed, non-conforming code segment).
•For SS, DS, ES, FS, and GS, the Type is set to 3 (read/write, accessed, expand-up data segment).
•The S bits for all registers are set to 1.
•The DPL for each register is set to 0.
•The P bits for all registers are set to 1.
•On processors that support Intel 64 architecture, CS.L  is loaded with the value of the IA-32e mode SMM 
feature bit.
•CS.D is loaded with the inverse of the value of the IA-32e mode SMM feature bit.
•For each of SS, DS, ES, FS, and GS, the D/B bit is set to 1.
•The G bits for all registers are set to 1.
•LDTR is unusable. The LDTR selector is cleared to 0000H , and the register is otherwise undefined (although the 
base address is always canonical)
•GDTR.base is set to the sum of the MSEG base addre ss and the GDTR base-offset field in the MSEG header 
(bits 63:32 are always cleared on processors that support IA-32e mode). GDTR.limit is set to the corresponding field in the MSEG header (the high 16 bits are ignored).
•IDTR.base is unchanged. IDTR.limit is cleared to 0000H.
•RIP is set to the sum of the MSEG base address and th e value of the RIP-offset field in the MSEG header 
(bits 63:32 are always cleared on logical processors that support IA-32e mode).
•RSP is set to the sum of the MSEG base address and th e value of the RSP-offset field in the MSEG header 
(bits 63:32 are always cleared on logical processor that supports IA-32e mode).Vol. 3C 32-29SYSTEM MANAGEMENT MODE
•RFLAGS is cleared, except bit 1, which is always set.
•The logical processor is left in the active state.
•Event blocking after the SMM VM exit is as follows:
— There is no blocking by STI or by MOV SS.
— There is blocking by non-maskable interrupts (NMIs) and by SMIs.
•There are no pending debug exceptions after the SMM VM exit.
•For processors that support IA-32e mode, the IA32_EFE R MSR is modified so that LME and LMA both contain 
the value of the IA-32e mode SMM feature bit.
If any of CR3[63:5], CR4.PAE, CR4.PSE, or IA32_EFER. LMA is changing, the TLBs are updated so that, after 
VM exit, the logical processor does not use translations that  were cached before the transition. This is not neces-
sary for changes that would not affect paging due to the se ttings of other bits (for exam ple, changes to CR4.PSE if 
IA32_EFER.LMA was 1 before and after the transition).
32.15.6.6  Loading MSRs
The VM-exit MSR-load area is not used by SMM VM exits th at activate the dual-monitor treatment. No MSRs are 
loaded from that area.
32.15.7 Deactivating the Dual-Monitor Treatment
The SMM-transfer monitor may deactivate the dual-monitor  treatment and return the processor to default treat-
ment of SMIs and SMM (see Section 32.14). It does this by  executing a VM entry with the “deactivate dual-monitor 
treatment” VM-entry control set to 1.
As noted in Section 27.2.1.3 and Section 32.15.4.1, an a ttempt to deactivate the dual-monitor treatment fails in 
the following situations: (1) the processor is not in SMM; (2 ) the “entry to SMM” VM-entry control is 1; or (3) the 
executive-VMCS pointer does not contain the VMXON pointer (the VM entry is to VMX non-root operation).
As noted in Section 32.15.4.9, VM entries that deactivate  the dual-monitor treatment ignore the SMI bit in the 
interruptibility-state field of the guest-state area. Instead,  the blocking of SMIs following such a VM entry depends 
on whether the logical processor is in SMX operation:1
•If the logical processor is in SMX operation, SMIs are blocked after VM entry. SMIs may later be unblocked by 
the VMXOFF instruction (see Section 32.14.4) or by certain leaf functions of the GETSEC instruction (see 
Chapter 7, “Safer Mode Extensions Reference,” in the Intel® 64 and IA-32 Architectu res Software Developer’s 
Manual, Volume 2D).
•If the logical processor is outside SMX op eration, SMIs are unblocked after VM entry.
32.16 SMI AND PROCESSOR EXTENDED STATE MANAGEMENT
On processors that support processor extended states  using XSAVE/XRSTOR (see Chapter 13, “Managing State 
Using the XSAVE Feature Set‚” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1), 
the processor does not save any XSAVE/XRSTOR related state on an SMI. It is the respon sibility of the SMI handler 
code to properly preserve the state information (inclu ding CR4.OSXSAVE, XCR0, and possibly processor extended 
states using XSAVE/XRSTOR). Therefore, the SMI hand ler must follow the rules described in Chapter 13, 
“Managing State Using the XSAVE Feature Set‚” of the Intel® 64 and IA-32 Architectures Software Developer’s 
execution of GETSEC[SENTER]. See Chapter 7, “Safer Mode Extensions Reference,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2D.32-30 Vol. 3CSYSTEM MANAGEMENT MODE
32.17 MODEL-SPECIFIC SYSTEM  MANAGEMENT ENHANCEMENT
This section describes enhancement of system management features that apply only to the 4th generation Intel 
Core processors. These features are model-specific. BIOS and SMM handler must use CPUID to enumerate Display-
Family_DisplayModel sign ature when programming with these interfaces.
32.17.1 SMM Handler Code Access Control
The BIOS may choose to restrict the address ranges of code that SMM handler executes. When SMM handler code 
execution check is enabled, an attempt by the SMM handle r to execute outside the ranges specified by SMRR (see 
Section 32.4.2.1) will cause the assertion of an unrecoverable machine check exception (MCE). 
The interface to enable SMM handler code access check re sides in a per-package scope model-specific register 
MSR_SMM_FEATURE_CONTROL at address 4E0H. An atte mpt to access MSR_SMM_FEATURE_CONTROL outside of 
SMM will cause a #GP. Writes to MSR_SMM_FEATURE_CONTROL is further protected by configuration interface of MSR_SMM_MCA_CAP at address 17DH.
Details of the interface of MSR_S MM_FEATURE_CONTROL and MSR_SMM_MCA_CAP are described in Table 2-29 in 
Chapter 2, “Model-Specific Registers (MSRs),” of the Intel
Manual, Volume 4.
32.17.2 SMI Delivery Delay Reporting 
Entry into the system management mode occurs at instruction boundary. In situations where a logical processor is executing an instruction involving a long flow of internal operations, servicing an SMI by  that logical processor will 
be delayed. Delayed servicing of SMI of each logical proce ssor due to executing long flows of internal operation in 
a physical processor can be queried via a package-scope register MSR_SMM_DELAYED at address 4E2H.
The interface to enable reporting of SMI delivery delay du e to long internal flows resides in a per-package scope 
model-specific register MSR_SMM_DELAYED. An attempt to access MSR_SMM_DELAYED ou tside of SMM will cause 
a #GP. Availability to MSR_SMM_DELAYED is protecte d by configuration interfac e of MSR_SMM_MCA_CAP at 
address 17DH.
Details of the interface of MSR_SMM_DELAYED and MSR_SM M_MCA_CAP are described in Table 2-29 in Chapter 2, 
“Model-Specific Registers (MSRs),” of the Intel
4.
32.17.3 Blocked SMI Reporting 
A logical processor may have entered into a state and bl ocked from servicing other interrupts (including SMI). 
Logical processors in a physical processor that are blocked in serving SMI can be queried in a package-scope

4.
Logical processors in a physical processor that are blocked in serving SMI can be queried in a package-scope 
register MSR_SMM_BLOCKED at address 4E3H. An atte mpt to access MSR_SMM_BLOCKED outside of SMM will 
cause a #GP.
Details of the interface of MSR_SMM_BLOCKED is described in Table 2-29 in Chapter 2, “Model-Specific Registers 
(MSRs),” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4.Vol. 3C 33-1INTEL® PROCESSOR TRACE
CHAPTER 33
33.1 OVERVIEW
Intel® Processor Trace ( Intel PT ) is an extension of Intel® Architecture that captures information about software 
execution using dedicated hardware facilities that cause only minimal performance perturbation to the software being traced. This inform ation is collected in data packets . The initial implementations of Intel PT offer control 
flow tracing , which generates a variety of packets to be proc essed by a software decoder. The packets include 
timing, program flow information (e.g., branch targets, branch taken/not taken indications) and program-induced 
mode related information (e.g., Intel TSX state transitions, CR3 changes). These packets may be buffered inter-
nally before being sent to the memory subsystem or othe r output mechanism available in the platform. Debug soft-
ware can process the trace data and reconstruct the program flow.
Intel Processor Trace was first introduced in Intel
® processors based on Broadwell microarchitecture and Intel 
Atom® processors based on Goldmont microarchitecture. Later generations include additional trace sources, 
including software trace instrumentation using PTWRITE, and Power Event tracing.
33.1.1 Features and Capabilities
Intel PT’s control flow trace generates a variety of packet s that, when combined with the binaries of a program by 
a post-processing tool, can be used to produce an exact execution trace. The packets record flow information such 
as instruction pointers (IP), indirect branch targets, and directions of conditional branches within contiguous code 
regions (basic blocks).
Intel PT can also be configured to log software-gen erated packets using PTWRITE, and packets describing 
processor power management events. Further, Precise Ev ent-Based Sampling (PEBS) can be configured to log 
PEBS records in the Intel PT trace; see Section 20.5.5.2.
In addition, the packets record other contextual, timing, and bookkeeping information that enables both functional 
and performance debugging of applications. Intel PT has several control and filtering capabilities available to 
customize the tracing information collected and to append other processor state and timing information to enable 
debugging. For example, there are modes that allow packet s to be filtered based on the current privilege level 
(CPL) or the value of CR3.
Configuration of the packet generation and filtering ca pabilities are programmed via a set of MSRs. The MSRs 
generally follow the naming convention of IA32_RTIT_*. The capability provided by these configuration MSRs are 
enumerated by CPUID, see Section 33.3. Details of the MSRs for configuring Intel PT are described in Section 
33.2.8.
33.1.1.1  Packet Summary
After a tracing tool has enabled and configured the approp riate MSRs, the processor will collect and generate trace 
information in the following categories of packets (for more details on the packets, see Section 33.4):
•Packets about basic information on program execution; these include:
— Packet Stream Boundary (PSB) packets: PSB packets act as ‘heartbeats’ that are generated at regular 
intervals (e.g., every 4K trace packet bytes). These packets allow the packet decoder to find the packet 
boundaries within the output data stream; a PSB packet should be the first packet that a decoder looks for 
when beginning to decode a trace.
— Paging Information Packet (PIP): PIPs record modifica tions made to the CR3 register. This information, 
along with information from the operating system on the CR3 value of each process, allows the debugger 
to attribute linear addresses to their correct application source.
— Time-Stamp Counter (TSC) packets: TSC packets aid in tracking wall-clock time, and contain some portion 
of the software-visible time-stamp counter.
— Core Bus Ratio (CBR) packets: CBR packets contain the core:bus clock ratio.33-2 Vol. 3CINTEL® PROCESSOR TRACE
— Mini Time Counter (MTC) packets: MTC packets provide periodic indication of the passing of wall-clock time.
— Cycle Count (CYC) packets: CYC packets provide indication of the number of processor core clock cycles 
that pass between packets.
— Overflow (OVF) packets: OVF packets are sent when the processor experiences an internal buffer overflow, 
resulting in packets being dropped. Th is packet notifies the decoder of the loss and can help the decoder to 
respond to this situation.
•Packets about control flow information:
— Taken Not-Taken (TNT) packets: TNT packets track the “direction” of direct conditional branches (taken or 
not taken).
— Target IP (TIP) packets: TIP packets record the target IP of indirect branches, exceptions, interrupts, and 
other branches or events. These packets can contain th e IP, although that IP value may be compressed by 
eliminating upper bytes that match the last IP. There ar e various types of TIP packets; they are covered in 
more detail in Section 33.4.2.2.
— Flow Update Packets (FUP): FUPs provide the source IP addresses for asynchronous events (interrupt and 
exceptions), as well as other cases where the source address cannot be determined from the binary.
— MODE packets: These packets provide the decoder with important processor execution information so that 
it can properly interpret the dis-assembled binary and trace log. MODE packets have a variety of formats that indicate details such as the exec ution mode (16-bit, 32-bit, or 64-bit).
•Packets inserted by software:
— PTWRITE (PTW) packets: includes the value of the operand passed to the PTWRITE instruction (see 
“PTWRITE—Write Data to a Processor Trace Packet” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 2B).
•Packets about processor power management events:
— MWAIT packets: Indicate successful completion of an MWAIT operation to a C-state deeper than C0.0.
— Power State Entry (PWRE) packets: Indicate entry to a C-state deeper than C0.0.— Power State Exit (PWRX) packets: Indicate exit from a C-state deeper than C0.0, returning to C0.
— Execution Stopped (EXSTOP) packets: Indicate that so ftware execution has stopped, due to events such as 
P-state change, C-state change, or thermal throttling.
•Packets containing groups of processor state values:
— Block Begin Packets (BBP): Indicate the type of state held in the following group.
— Block Item Packets (BIP): Indicate the state values held in the group.— Block End Packets (BEP): Indicate the end of the current group.
33.2 INTEL® PROCESSOR TRACE OPERATIONAL MODEL
This section describes the overall Intel Processor Trace mechanism and the essential concepts relevant to how it 
operates.
33.2.1 Change of Flow Instruction (COFI) Tracing
A basic program block is a section of code where no jumps or branches occur. The instruction pointers (IPs) in this 
block of code need not be traced, as the processor will execute them from start to end without redirecting code 
flow. Instructions such as branches, and events such as exceptions or interrupts, can change the program flow. These instructions and events that change program flow ar e called Change of Flow Instructions (COFI). There are 
three categories of COFI:
•Direct transfer COFI.
•Indirect transfer COFI.
•Far transfer COFI.Vol. 3C 33-3INTEL® PROCESSOR TRACE
The following subsections describe the COFI events that re sult in trace packet generation. Table 33-1 lists branch 
instruction by COFI types. For detailed description of specific instructions, see the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual.
33.2.1.1  Direct Transfer COFI
Direct Transfer COFI are relative branches. This means that their target is an IP whose offset from the current IP is embedded in the instruction bytes. It is not necessary to indicate target of these instructions in the trace output 
since it can be obtained through the source disassembly. Conditional branches need to indicate only whether the 
branch is taken or not. Unconditional branches do not need any recording in the trace output. There are two sub-
categories:
•Conditional Branch (Jcc, J*CXZ) and LOOP
To track this type of instruction, the processor encodes a single bit (taken or not taken — TNT) to indicate the 
program flow after the instruction. 
Jcc, J*CXZ, and LOOP can be traced with TNT bits. To improve the trace packet output efficiency, the processor 
will compact several TNT bits into a single packet.
•Unconditional Direct Jumps
There is no trace output required for direct unconditional  jumps (like JMP near relative or CALL near relative)

There is no trace output required for direct unconditional  jumps (like JMP near relative or CALL near relative) 
since they can be directly inferred from the application assembly. Direct unconditional jumps do not generate a TNT bit or a Target IP packet, though TIP.PGD and TIP.PGE packets can be generated by unconditional direct 
jumps that toggle Intel PT enables (see Section 33.2.6).
33.2.1.2  Indirect Transfer COFI
Indirect transfer instructions involve updating the IP fr om a register or memory location. Since the register or 
memory contents can vary at any time during execution, there is no way to know the target of the indirect transfer 
until the register or memory contents are read. As a result , the disassembled code is not sufficient to determine the 
target of this type of COFI. Therefore, tracing hardware must send out the destination IP in the trace packet for 
debug software to determine the target address of the COFI. Note that this IP may be a linear or effective address 
(see Section 33.3.1.1).
An indirect transfer instruction generates a Target IP Pack et (TIP) that contains the target address of the branch. 
There are two sub-categories:
•Near JMP Indirect and Near Call Indirect
As previously mentioned, the target of an indirect COFI  resides in the contents of either a register or memory
location. Therefore, the processor must generate a pack et that includes this target address to allow the
decoder to determine the program flow.
•Near RET
When a CALL instruction executes, it pushes onto the stack the address of the next instruction following the
CALL. Upon completion of the call procedure, the RET in struction is often used to pop the return address off of
the call stack and redirect code flow back to the instruction following the CALL.
A RET instruction simply transfers program flow to the address it popped off the stack. Because a called
procedure may change the return address on the stack before executing the RET instruction, debug softwareTable 33-1. COFI Type for Branch Instructions 
COFI Type Instructions
Conditional Branch JA, JAE, JB, JBE, JC, JCXZ , JECXZ, JRCXZ, JE, JG, JGE, JL, JLE, JNA,  JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JN L, 
JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ, LOOP, LOOPE, LOOPNE, LOOPNZ, LOOPZ
Unconditional Direct Branch JMP (E9 xx, EB xx), CALL (E8 xx)
Indirect Branch JMP (FF /4), CALL (FF /2), RET (C3, C2 xx)
Far Transfers INT1, INT3, INT n, INTO, IRET, IRETD, IRETQ, JMP (EA xx, FF /5 ), CALL (9A xx, FF /3), RET (CB, CA xx), 
SYSCALL, SYSRET, SYSENTER, SYSEXIT, VMLAUNCH, VMRESUME33-4 Vol. 3CINTEL® PROCESSOR TRACE
can be misled if it assumes that code flow will retu rn to the instruction follow ing the last CALL. Therefore,
even for near RET, a Target IP Packet may be sent.
—R E T  C o m p r e s s i o n
A special case is applied if the target of the RET is co nsistent with what would be expected from tracking the 
CALL stack. If it is assured that the decoder has seen  the corresponding CALL (w ith “corresponding” defined 
as the CALL with matching stack depth), and the RET target is the instruction after that CALL, the RET 
target may be “compressed”. In this case, only a single  TNT bit of “taken” is generated instead of a Target 
IP Packet. To ensure that the decoder will not be confused in cases of RET compression, only RETs that 
correspond to CALLs which have been seen since the last PSB packet may be compressed in a given logical 
processor. For details, see “Indirect Transfer Comp ression for Returns (RET)” in Section 33.4.2.2.
33.2.1.3  Far Transfer COFI
All operations that change the instruction pointer and are not near jumps are “far transfers”. This includes excep-
tions, interrupts, traps, TSX aborts, and instructions that do far transfers.
All far transfers will produce a Target IP (TIP) packet, wh ich provides the destination IP address. For those far 
transfers that cannot be inferred from the binary source (e .g., asynchronous events such as exceptions and inter-
rupts), the TIP will be preceded by a Flow Update packet (FUP), which provides the source IP address at which the 
event was taken. Table 33-23 indicates exactly which IP w ill be included in the FUP generated by a far transfer.
33.2.2 Software Trace Instrumentation with PTWRITE
PTWRITE provides a mechanism by which software can inst rument the Intel PT trace. PTWRITE is a ring3-acces-
sible instruction that can be passed to a register or me mory variable, see “PTWRITE—Write Data to a Processor 
Trace Packet” in the Intel® 64 and IA-32 Architectures Software Develo per’s Manual, Volume 2B, for details. The 
contents of that variable will be used as the payload fo r the PTW packet (see Table 33-40 “PTW Packet Definition”), 
inserted at the time of PTWRITE retirement, assuming PT WRITE is enabled and all other filtering conditions are 
met. Decode and analysis software will then be able to determine the meaning of the PTWRITE packet based on the 
IP of the associated PTWRITE instruction.
PTWRITE is enabled via IA32_RTIT_CTL.PTWEn[12] (see Table 33-6). Optionally, the user can use IA32_R-
TIT_CTL.FUPonPTW[5] to enable PTW packets to be followe d by FUP packets containing the IP of the associated 
PTWRITE instruction. Support for PTWRIT E is introduced in Intel Atom processors based on the Goldmont Plus 
33.2.3 Power Event Tracing
Power Event Trace is a capability that exposes core- and th read-level sleep state and power down transition infor-
mation. When this capability is enabled,  the trace will expose information about:
— Scenarios where software execution stops.
•Due to sleep state entry, frequency change, or other powerdown.
•Includes the IP, when in the tracing context.
— The requested and resolved hardware thread C-state.
•Including indication of hardware autonomous C-state entry.
— The last and deepest core C-state achieved during a sleep session.
— The reason for C-state wake.
This information is in addition to the bus ratio (CBR) in formation provided by default after any powerdown, and the 
timing information (TSC, TMA, MTC, CYC) pr ovided during or after a powerdown state.
Power Event Trace is enabled via IA32_RTIT_CTL.PwrEvtEn[ 4]. Support for Power Event Tracing is introduced in 
Intel Atom processors based on the Goldmont Plus microarchitecture.Vol. 3C 33-5INTEL® PROCESSOR TRACE
33.2.4 Event Tracing
Event Trace is a capability that exposes details about th e asynchronous events, when they are generated, and 
when their corresponding software event handler completes execution. These include:
•Interrupts, including NMI and SMI, includ ing the interrupt vector when defined.
•Faults, exceptions including the fault vector.
— Page faults additionally include the page fault address, when in context.
•Event handler returns, including IRET and RSM.
•VM exits and VM entries.1
— VM exits include the values written to the “exi t reason” and “exit qualification” VMCS fields.
•INIT and SIPI events.
•TSX aborts, including the abort status returned for the RTM instructions.
•Shutdown.
Additionally, it provides indication of the status of the Interrupt Flag (IF), to indicate when interrupts are masked. 
Event Trace is enabled via IA32_RTIT_CTL.EventEn[31]. Even t Trace information is conveyed in Control Flow Event 
(CFE) and Event Data (EVD) packets, as well as the le gacy MODE.Exec packet. See Section 33.4.2 for packet 
details. Support for Event Trace is introduced in Intel® processors based on Gracemont microarchitecture.
33.2.5 Trace Filtering
Intel Processor Trace provides filtering capabilities, by whic h the debug/profile tool can control what code is traced. 
33.2.5.1  Filtering by Cu rrent Privilege Level (CPL)
Intel PT provides the ability to configure a logical proce ssor to generate trace packets only when CPL = 0, when 
CPL > 0, or regardless of CPL. 
CPL filtering ensures that no IPs or other architectural st ate information associated with the filtered CPL can be 
seen in the log. For example, if the processor is config ured to trace only when CPL > 0, and software executes 
SYSCALL (changing the CPL to 0), the destination IP of the SYSCALL will be suppressed from the generated packet 
(see the discussion of TIP.PGD in Section 33.4.2.5).
It should be noted that CPL is always 0 in real-address mode and that CPL is always 3 in virtual-8086 mode. To 
trace code in these modes, filtering should be configured accordingly.
When software is executing in a non-enabled CPL, ContextEn is cleared. See Section 33.2.6.1 for details.
33.2.5.2  Filtering by CR3
Intel PT supports a CR3-filtering mechanism by which the ge neration of packets containing architectural states can 
be enabled or disabled based on the value of CR3. A debu gger can use CR3 filtering to trace only a single applica-
tion without context switching the state of the RTIT MSRs . For the reconstruction of traces from software with 
multiple threads, debug software may wish to context-sw itch for the state of the RTIT MSRs (if the operating

multiple threads, debug software may wish to context-sw itch for the state of the RTIT MSRs (if the operating 
system does not provide context-switch support) to sepa rate the output for the diffe rent threads (see Section 
33.3.5, “Context Switch Consideration”).
To trace for only a single CR3 value, software can wr ite that value to the IA32_RTIT_CR3_MATCH MSR, and set 
IA32_RTIT_CTL.CR3Filter. When CR3 value does not ma tch IA32_RTIT_CR3_MATCH and IA32_RTIT_CTL.CR3Filter 
is 1, ContextEn is forced to 0, and packets containing  architectural states will not be generated. Some other 
packets can be generated when ContextEn is 0; see Se ction 33.2.6.3 for details. When CR3 does match IA32_R-
TIT_CR3_MATCH (or when IA32_RTIT_CTL.CR3Filter is 0), CR 3 filtering does not force ContextEn to 0 (although it 
could be 0 due to other filters or modes).
1. Logging of VMX transitions depends on VMCS configuration, see Section 33.5.1.33-6 Vol. 3CINTEL® PROCESSOR TRACE
CR3 matches IA32_RTIT_CR3_MATCH if the two registers are identical for bits 63:12, or 63:5 when in PAE paging 
mode; the lower 5 bits of CR3 and IA32_RTIT_CR3_MATCH are ignored. CR3 filtering is independent of the value of 
CR0.PG. 
When CR3 filtering is in use, PIP packets may still be seen in the log if the processor is configured to trace when 
CPL = 0 (IA32_RTIT_CTL.OS = 1). If not, no PIP packets will be seen.
33.2.5.3  Filtering by IP
Trace packet generation with configurable filtering by IP  is supported if CPUID.(EAX= 14H, ECX=0):EBX[bit 2] = 1. 
Intel PT can be configured to enable the generation of  packets containing architectural states only when the 
processor is executing code within certain IP ranges. If the IP is outside of these ranges, generation of some 
packets is blocked.
IP filtering is enabled using the ADDRn_CFG fields in th e IA32_RTIT_CTL MSR (Section 33.2.8.2), where the digit 
'n' is a zero-based number that selects which address ra nge is being config ured. Each ADDRn_CFG field configures 
the use of the register pair IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B (Section 33.2.8.5). IA32_RTIT_AD-
DRn_A defines the base and IA32_RTIT_ADDRn_B specifies the limit of the range in which tracing is enabled. Thus 
each range, referred to as the ADDRn range, is defined by [IA32_RTIT_ADDRn_A, IA32_RTIT_ADDRn_B]. There 
can be multiple such ranges, software can query CPUID (S ection 33.3.1) for the number of ranges supported on a 
Default behavior (ADDRn_CFG=0) defines no IP filter range, meaning FilterEn is always set. In this case code at 
any IP can be traced, though other filters, such as CR3 or CPL, could limit tracing. When ADDRn_CFG is set to 
enable IP filtering (see Section 33.3.1), tracing will commen ce when a taken branch or event is seen whose target 
address is in the ADDRn range.
While inside a tracing region and with FilterEn is set, le aving the tracing region may only be detected once a taken 
branch or event with a target outside the range is retired.  If an ADDRn range is entered or exited by executing the 
next sequential instruction, rather than by a control flow  transfer, FilterEn may not toggle immediately. See Section 
33.2.6.5 for more details on FilterEn. 
Note that these address range base and limit values are in clusive, such that the range includes the first and last 
instruction whose first instruction byte is in the ADDRn range.
Depending upon processor implementation, IP filtering may be based on linear or effective address. This can cause 
different behavior between implementations if CSbase is not equal to zero or in real mode. See Section 33.3.1.1 for 
details. Software can query CPUID to determine filters are based on linear or effective address (Section 33.3.1).
Note that some packets, such as MTC (Section 33.3.7) and other timing packets, do not depend on FilterEn. For 
details on which packets depend on FilterEn, and henc e are impacted by IP filtering, see Section 33.4.1.
TraceStop
The ADDRn ranges can also be configured to cause tracing to  be disabled upon entry to the specified region. This is 
intended for cases where unexpected code is executed, and the user wishes to immediately stop generating 
packets in order to avoid overwriting previously written packets.
The TraceStop mechanism works much the same way that IP  filtering does, and uses the same address comparison 
logic. The TraceStop region base and limit values are programmed into one or more ADDRn ranges, but 
IA32_RTIT_CTL.ADDRn_CFG is configured with the TraceSto p encoding. Like FilterEn, TraceStop is detected when 
a taken branch or event lands in a TraceStop region.
Further, TraceStop requires that TriggerEn=1 at the beginning of the branch/event, and ContextEn=1 upon 
completion of the branch/event. When this happens,  the CPU will set IA32_RTIT_STATUS.Stopped, thereby 
clearing TriggerEn and hence disabling packet generation. This may generate a TIP.PGD packet with the target IP 
of the branch or event that entered the TraceStop region. Finally, a TraceStop packet will be inserted, to indicate 
that the condition was hit. 
If a TraceStop condition is encountered during buffer over flow (Section 33.3.8), it will not be dropped, but will 
instead be signaled once the overflow has resolved.
Note that a TraceStop event does not guarantee that all internally buffered packets ar e flushed out of internal 
buffers. To ensure that this has occurred, the user should clear TraceEn.Vol. 3C 33-7INTEL® PROCESSOR TRACE
To resume tracing after a TraceStop event, the user must  first disable Intel PT by clearing IA32_RTIT_CTL.TraceEn 
before the IA32_RTIT_STATUS.Stopped bit can be cleared. At  this point Intel PT can be reconfigured, and tracing 
resumed.
Note that the IA32_RTIT_STATUS.Stoppe d bit can also be set using the ToPA STOP bit. See Section 33.2.7.2.
IP Filtering Example
The following table gives an example of  IP filtering behavior. Assume that IA32_RTIT_ADDRn_A = the IP of Range-
Base, and that IA32_RTIT_ADDRn_B = the IP of Rang eLimit, while IA32_RTIT_CTL.ADDRn_CFG = 0x1 (enable 
ADDRn range as a FilterEn range).
IP Filtering and TraceStop
It is possible for the user to configure IP filter range(s) and TraceStop range(s) that overlap. In this case, code executing in the non-overlapping portion of either range w ill behave as would be expected from that range. Code 
executing in the overlapping range will get TraceStop behavior.
33.2.6 Packet Generation Enable Controls
Intel Processor Trace includes a variety of controls that determine whether a packet is generated. In general, most 
packets are sent only if Packet Enable ( PacketEn ) is set. PacketEn is an internal state maintained in hardware in 
response to software configurable enable controls, PacketEn  is not visible to software directly. The relationship of 
PacketEn to the software-visible controls in the configuration MSRs is described in this section.
33.2.6.1  Packet Enable (PacketEn)
When PacketEn is set, the processor is in the mode that  Intel PT is monitoring. PacketEn is composed of other 
states according to this relationship:
PacketEn := TriggerEn AND ContextEn AND FilterEn AND BranchEn
These constituent controls are detailed in the following subsections.PacketEn ultimately determines when the processor is trac ing. When PacketEn is set, all control flow packets are 
enabled. When PacketEn is clear, no control flow packets are generated, though other packets (timing and book-
keeping packets) may still be sent. See Section 33.2.7 for details of PacketEn and packet generation.
Note that, on processors that do not support IP filterin g (i.e., CPUID.(EAX=14H, ECX=0 ):EBX[bit 2] = 0), FilterEn 
is treated as always set.Table 33-2. IP Filtering Packet Example 
Code Flow Packets
Bar:
jmp RangeBase // jump into filter range
RangeBase:
jcc Foo // not takenadd eax, 1
Foo:
jmp RangeLimit+1 // jump out of filter range
RangeLimit:
nopjcc BarTIP.PGE(RangeBase)
TNT(0)
TIP.PGD(RangeLimit+1)33-8 Vol. 3CINTEL® PROCESSOR TRACE
33.2.6.2  Trigger Enable (TriggerEn)
Trigger Enable ( TriggerEn ) is the primary indicator that trace packet generation is active. TriggerEn is set when 
IA32_RTIT_CTL.TraceEn is set, and cleare d by any of the following conditions:
•TraceEn is cleared by software. 
•A TraceStop condition is encountered and IA32_RTIT_STATUS.Stopped is set.
•IA32_RTIT_STATUS.Error is set due to an operational error (see Section 33.3.10).
Software can discover the current TriggerEn value by re ading the IA32_RTIT_STATUS.TriggerEn bit. When Trig-
gerEn is clear, tracing is inactive and no packets are generated.
33.2.6.3  Context Enable (ContextEn)
Context Enable ( ContextEn ) indicates whether the processor is in the state or mode that software configured 
hardware to trace. For example, if execution with CPL = 0 code is not being traced (IA32_RTIT_CTL.OS = 0), then 
ContextEn will be 0 when the processor is in CPL0.
Software can discover the current ContextEn value by re ading the IA32_RTIT_STATUS.ContextEn bit. ContextEn is 
ContextEn = !((IA32_RTIT_CTL.OS = 0 AND CPL = 0) OR

(IA32_RTIT_CTL.USER = 0 AND CPL > 0) OR (IS_IN_A_PRODUCTION_ENCLAVE1) OR
(IA32_RTIT_CTL.CR3Filter = 1 AND IA32_RTIT_CR3_MATCH does not match CR3)
If the clearing of ContextEn causes PacketEn to be cleare d, a Packet Generation Disable (TIP.PGD) packet is gener-
ated, but its IP payload is suppressed. If the setting of Co ntextEn causes PacketEn to be set, a Packet Generation 
Enable (TIP.PGE) packet is generated.
When ContextEn is 0, control flow packets (TNT, FUP, TIP.*, MODE.*) are not generated, and no Linear Instruction 
Pointers (LIPs) are exposed. However, some packets, such as MTC and PSB (see Section 33.4.2.16 and Section 33.4.2.17), may still be generated while ContextEn is 0. For details of which packets are generated only when 
ContextEn is set, see Section 33.4.1.
The processor does not update ContextEn when TriggerEn = 0.The value of ContextEn will toggle only when TriggerEn = 1.
33.2.6.4  Branch Enable (BranchEn)
This value is based purely on the IA32_RTIT_CTL.BranchEn value. If BranchEn  is not set, then relevant COFI 
packets (TNT, TIP*, FUP, MODE.*) are suppressed. Other pa ckets related to timing (TSC , TMA, MTC, CYC), as well 
as PSB, will be generated normally regardless. Further, PI P and VMCS continue to be generated, as indicators of 
what software is running.
33.2.6.5  Filter Enable (FilterEn)
Filter Enable indicates that the Instruction Pointer (IP) is wi thin the range of IPs that Intel PT is configured to watch. 
Software can get the state of Filter Enable by a RDMSR of  IA32_RTIT_STATUS.FilterEn. For details on configuration 
and use of IP filtering, see Section 33.2.5.3.
On clearing of FilterEn that also clears PacketEn, a Pa cket Generation Disable (TIP.PGD) will be generated, but 
unlike the ContextEn case, the IP payload may not be suppre ssed. For direct, unconditional branches, as well as for 
indirect branches (including RETs), the PGD generated by  leaving the tracing region and clearing FilterEn will 
contain the target IP. This means that IPs from outside th e configured range can be exposed in the trace, as long 
as they are within context. 
When FilterEn is 0, control flow packets are not generated (e.g., TNT, TIP). However, some packets, such as PIP, 
MTC, and PSB, may still be generated while FilterEn is clea r. For details on packet enable dependencies, see Section 
33.4.1.
1. Trace packets generation is disabled in a production enclave, see Section 33.2.9.5. See the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3D, about differences between a production enclave and a debug enclave.Vol. 3C 33-9INTEL® PROCESSOR TRACE
After TraceEn is set, FilterEn is set to 1 at all times if there is no IP filter range configured by software 
(IA32_RTIT_CTL.ADDRn_CFG != 1, for all n), or if th e processor does not support IP filtering (i.e., 
CPUID.(EAX=14H, ECX=0):EBX[bit 2] = 0). FilterEn will to ggle only when TraceEn=1 and ContextEn=1, and when 
at least one range is configured for IP filtering.
33.2.7 Trace Output
Intel PT output should be viewed independently from tr ace content and filtering mech anisms. The options available 
for trace output can vary across processor generations and platforms. 
Trace output is written out using one of  the following output schemes, as conf igured by the ToPA and FabricEn bit 
fields of IA32_RTIT_CTL (see Section 33.2.8.2):
•A single, contiguous region of physical address space. 
•A collection of variable-sized regions of physical me mory. These regions are linked together by tables of 
pointers to those regions, referred to as Table of Physical Addresses ( ToPA ). The trace output stores bypass 
the caches and the TLBs, but are not serializing. This is  intended to minimize the performance impact of the 
output.
•A platform-specific trace transport subsystem.
Regardless of the output scheme chosen, Intel PT stores by pass the processor caches by default. This ensures that 
they don't consume precious cache space, but they do no t have the serializing aspects associated with un-cache-
able (UC) stores. Software should avoid using MTRRs to ma rk any portion of the Intel PT  output region as UC, as 
this may override the behavior described above and force Intel PT stores to UC, thereby incurring severe perfor-
mance impact.
There is no guarantee that a packet will be written to memory or other trace endpoint after some fixed number of 
cycles after a packet-producing instruction executes. The only way to assure that all packets generated have 
reached their endpoint is to clear TraceEn and follow that with a store, fence, or serializing instruction; doing so ensures that all buffered packets are flushed out of the processor. 
33.2.7.1  Single Range Output
When IA32_RTIT_CTL.ToPA and IA32_RTIT_CTL.FabricEn bits are clear, trace packet output is sent to a single, 
contiguous memory (or MMIO if DRAM is not av ailable) range defined by a base address in 
IA32_RTIT_OUTPUT_BASE (Section 33.2.8.7) and mask  value in IA32_RTIT_OUTPUT_MASK_PTRS (Section 
33.2.8.8). The current write pointer in this range is al so stored in IA32_RTIT_OUTPUT_MASK_PTRS. This output 
range is circular, meaning that when the writes wrap aro und the end of the buffer they begin again at the base 
address.
This output method is best suited for cases where Intel PT output is either:
•Configured to be directed to a sufficie ntly large contiguous region of DRAM. 
•Configured to go to an MMIO debug port, in order to ro ute Intel PT output to a platform-specific trace endpoint 
(e.g., JTAG). In this scenario, a specific range of addre sses is written in a circular manner, and SoC will intercept 
these writes and direct them to the proper device. Repeated writes to the same address do not overwrite each 
other, but are accumulated by the debugger, and hence no data is lost by the circular nature of the buffer. 
The processor will determine the address to which to write the next trace packet output byte as follows:
OutputBase[63:0] := IA32_RTIT_OUTPUT_BASE[63:0]
OutputMask[63:0] := ZeroExtend64(IA32_RTIT_OUTPUT_MASK_PTRS[31:0])OutputOffset[63:0] := ZeroExtend64(IA32_RTIT_OUTPUT_MASK_PTRS[63:32])
trace_store_phys_addr  := (OutputBase & ~OutputMask) + (OutputOffset & OutputMask)33-10 Vol. 3CINTEL® PROCESSOR TRACE
Single-Range Output Errors
If the output base and mask are not properly configured by software, an operational error (see Section 33.3.10) 
will be signaled, and tracing disabled. Erro r scenarios with single-range output are:
•Mask value is non-contiguous.
IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTablePointer value has a 0 in a less significant bit position than the
most significant bit containing a 1.
•Base address and Mask are mis-aligne d, and have overlapping bits set.
IA32_RTIT_OUTPUT_BASE && IA32_RTIT_OUTPUT_MASK_PTRS[31:0] > 0. 
•Illegal Output OffsetIA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset  is greater than the mask value 
IA32_RTIT_OUTPUT_MASK_PTRS[31:0].
Also note that errors can be signaled due to trace packet output overlapping with restricted memory, see Section 
33.2.7.4.
33.2.7.2  Table of Physical Addresses (ToPA)
When IA32_RTIT_CTL.ToPA is set and IA32_RTIT_CTL.FabricEn  is clear, the ToPA output mechanism is utilized. The 
ToPA mechanism uses a linked list of tables; see Figure 33-1 for an illustrative example. Each entry in the table contains some attribute bits, a pointer to an output region , and the size of the region. The last entry in the table 
may hold a pointer to the next table. This pointer can either point to the top of the current table (for circular array) 
or to the base of another table. The table size is not fi xed, since the link to the next table can exist at any entry.
The processor treats the various output regions referenced by  the ToPA table(s) as a unified buffer. This means that 
a single packet may span the boundary between one output region and the next.
The ToPA mechanism is controlled by three values maintained by the processor:
•proc_trace_table_base.
This is the physical address of the base of the current ToPA table. When tracing is enabled, the processor loads 
this value from the IA32_RTIT_OUTPUT_BASE MSR. Wh ile tracing is enabled, the processor updates the 
IA32_RTIT_OUTPUT_BASE MSR with changes to proc_t race_table_base, but these updates may not be 
synchronous to software execution. When tracing is di sabled, the processor ensures that the MSR contains the 
latest value of proc_trace_table_base.
•proc_trace_table_offset.This indicates the entry of the current  table that is currently in use. (This entry contains the address of the 
current output region.) When tracing is enabled, th e processor loads the value from bits 31:7 (MaskOrT-
ableOffset) of the IA32_RTIT_OUTPUT_MASK_PTRS into bits  27:3 of proc_trace_table_offset. While tracing is 
enabled, the processor updates IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset with changes to 
proc_trace_table_offset, but these updates may not be sy nchronous to software execution. When tracing is

proc_trace_table_offset, but these updates may not be sy nchronous to software execution. When tracing is 
disabled, the processor ensures that the MSR contains the latest value of proc_trace_table_offset.
•proc_trace_output_offset.This a pointer into the current output region and indica tes the location of the next write. When tracing is 
enabled, the processor loads this value from bits 63:32 (OutputOffset) of the 
IA32_RTIT_OUTPUT_MASK_PTRS. While tracing is enabled, the processor updates IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset with change s to proc_trace_output_offset, but these updates 
may not be synchronous to software execution. When tr acing is disabled, the processor ensures that the MSR 
contains the latest value of proc_trace_output_offset.Vol. 3C 33-11INTEL® PROCESSOR TRACE
Figure 33-1 provides an illustration (not to scale) of the table and associated pointers.
With the ToPA mechanism, the processor writes pack ets to the current output region (identified by 
proc_trace_table_base and the proc_trace_table_offset). The offset within that region to which the next byte will 
be written is identified by proc_trace_output_offset. Wh en that region is filled with packet output (thus 
proc_trace_output_offset = RegionSize–1), proc_trac e_table_offset is moved to the next ToPA entry, 
proc_trace_output_offset is set to 0, and packet writ es begin filling the new ou tput region specified by 
proc_trace_table_offset.
As packets are written out, each store derives its physical address as follows:
trace_store_phys_addr  := Base address from current ToPA table entry + 
proc_trace_output_offset
Eventually, the regions represented by all entries in the ta ble may become full, and the final entry of the table is 
reached. An entry can be identified as the final entry be cause it has either the END or STOP attribute. The END 
attribute indicates that the address in the entry does not po int to another output region, but rather to another ToPA 
table. The STOP attribute indicates that tracing will be di sabled once the corresponding region is filled. See Table 
33-3 and the section that follows for details on STOP.
When an END entry is reached, the processor loads proc_t race_table_base with the base address held in this END 
entry, thereby moving the current table pointer to this new table. The proc_trace_table_offset is reset to 0, as is 
the proc_trace_output_offset, and packet writes will re sume at the base address indicated in the first entry.
If the table has no STOP or END entry, and trace-pack et generation remains enabled, eventually the maximum 
table size will be reached (proc_trace_table_offset = 0 FFFFFF8H). In this case, the proc_trace_table_offset and 
proc_trace_output_offset are reset to 0 (wrapping back to the beginning of the current table) once the last output 
region is filled.Figure 33-1.  ToPA Memory Illustration0FF_FFFF _FFFFH
STOP=1proc_trace_output_offset: IA32_RTI T_OUTPUT_MASK_PTRS.OutputOffset
proc_trace_table_offset: 
proc_trace_table_base: IA32_RTIT_OUTPUT_BASE
0ToPA Table BPhysical Memory
64K OutputBaseX4K OutputBaseYEND=1 TableBaseB
ToPA Table A
OutputRegionYOutputRegionX
 IA32_RTIT_OUTPUT_MASK_PRS.MaskOrTableOffset<<333-12 Vol. 3CINTEL® PROCESSOR TRACE
It is important to note that processor updates to the IA32_RTIT_OUTPUT_BASE and 
IA32_RTIT_OUTPUT_MASK_PTRS MSRs are asynchronous to  instruction execution. Thus, reads of these MSRs 
while Intel PT is enabled may return stale values. Like al l IA32_RTIT_* MSRs, the values of these MSRs should not 
be trusted or saved unless trace packet generation is first disabled by clearing IA32_RTIT_CTL.TraceEn. This 
ensures that the output MSR values account for all packet s generated to that point, after which the processor will 
cease updating the output MSR values until tracing resumes. 1
The processor may cache internally any number of entries fr om the current table or from tables that it references 
(directly or indirectly). If tracing is enabled, the proce ssor may ignore or delay detection of modifications to these 
tables. To ensure that table changes are detected by the processor in a predictable manner, software should clear TraceEn before modifying the current table (or tables that it references) and only then re-enable packet generation.
Single Output Region  ToPA Implementation
The first processor generation to implement Intel PT suppor ts only ToPA configurations with a single ToPA entry 
followed by an END entry that points back to the first entr y (creating one circular output buffer). Such processors 
enumerate CPUID.(EAX=14H,ECX=0):ECX.MENTRY[bit 1]  = 0 and CPUID.(EAX=14H,ECX=0):ECX.TOPAOUT[bit 
0] = 1. 
If CPUID.(EAX=14H,ECX=0):ECX.MENTRY[bit 1] = 0, ToPA tabl es can hold only one output entry, which must be 
followed by an END=1 entry which points back to the base  of the table. Hence only one contiguous block can be 
used as output.
The lone output entry can have INT or STOP set, but none theless must be followed by an END entry as described 
above. Note that, if INT=1, the PMI will actua lly be delivered before the region is filled.
ToPA Table Entry Format
The format of ToPA table entries is shown in Figure 33-2.  The size of the address field is determined by the 
processor’s physical-address width (MAXPHYADDR) in  bits, as reported in CPUID.80000008H:EAX[7:0].
Table 33-3 describes the details of the ToPA table entry fiel ds. If reserved bits are set to 1, an error is signaled.
1. Although WRMSR is a serializing instruction, the executio n of WRMSR that forces packet writes by clearing Tra-
ceEn does not itself cause these writes to be globally observed.Figure 33-2.  Layout of ToPA Table Entry
Table 33-3. ToPA Table Entry Fields
ToPA Entry Field Description
Output Region 
Base Physical 
AddressIf END=0, this is the base physical address of the output region specified by this entry. Note  that all regions 
must be aligned based on their size. Thus a 2M region must  have bits 20:12 clear. If the region is not properly 
aligned, an operational error will be signaled when the entry is reached.
If END=1, this is the 4K-aligned base physical address of the next ToPA table (which may be the base of the cur-rent table, or the first table in the link ed list if a circular buffer is desired) . If the processor supports only a single 
ToPA output region (see above), this address must be the value currently in the IA32_RTIT_OUTPUT_BASE 
MSR.11 910 12 MAXPHYADDR–1
9:6 Size65 0
4 : STOP
2 : INT
0 : ENDOutput Region Base Physical Address4132
Reserved63Vol. 3C 33-13INTEL® PROCESSOR TRACE
ToPA STOP
Each ToPA entry has a STOP bit. If this bit is set, th e processor will set the IA32_RTIT_STATUS.Stopped bit when 
the corresponding trace output region is filled. This will  clear TriggerEn and thereby cease packet generation. See 
Section 33.2.8.4 for details on IA32_RTIT_STATUS.Stopped. This sequence is known as “ToPA Stop”.
No TIP.PGD packet will be seen in the output when the To PA stop occurs, since the disable happens only when the 
region is already full. When this occurs, output ceases af ter the last byte of the region is filled, which may mean 
that a packet is cut off in the middle. Any packets remain ing in internal buffers are lost and cannot be recovered. 
When ToPA stop occurs, the IA32_RTIT_OUTPUT_BASE MSR will hold the base address of the table whose entry 
had STOP=1. IA32_RTIT_OUTPUT_MASK_PTRS.MaskOrTableOffset will hold the index value for that entry, and the 
IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset should be  set to the size of the region minus one. 
Note that this means the offset pointer is pointing to the next byte after the end of the region, a configuration that 
would produce an operational error if the configur ation remained when tracing is re-enabled with 
IA32_RTIT_STATUS.Stopped cleared. 
ToPA PMI
Each ToPA entry has an INT bit. If this bit is set, the processor will signal a performance-monitoring interrupt (PMI) 
when the corresponding trace output region is filled. This inte rrupt is not precise, and it is thus likely that writes to 
the next region will occur by the time the interrupt is taken.
The following steps should be taken to configure this interrupt:
1. Enable PMI via the LVT Performance Monitor register (at MMIO offset 340H in xAPIC mode; via MSR 834H in 
x2APIC mode). See the Intel® 64 and IA-32 Architectures Software De veloper’s Manual, Volume 3B, for more 
details on this register. For ToPA PMI, set all fields to 0, save for the interrupt vector, which can be selected by 
software.
2. Set up an interrupt handler to service the interrupt vector that a ToPA PMI can raise.
3. Set the interrupt flag by executing STI.4. Set the INT bit in the ToPA entry of interest and enable  packet generation, using the ToPA output option. Thus, 
TraceEn=ToPA=1 in the IA32_RTIT_CTL MSR.
Once the INT region has been filled with packet output data , the interrupt will be signaled. This PMI can be distin-
guished from others by checking bit 55 (Trace_ToPA_ PMI) of the IA32_PERF_GLOBAL_STATUS MSR (MSR 38EH). 
Once the ToPA PMI handler has serviced the releva nt buffer, writing 1 to bit 55 of the MSR at 390H

software.
Once the ToPA PMI handler has serviced the releva nt buffer, writing 1 to bit 55 of the MSR at 390H 
(IA32_GLOBAL_STATUS_RESET) clears IA32_PERF_GLOBAL_STATUS.Trace_ToPA_PMI.Size Indicates the size of  the associated output region. Encodings are:
0: 4K, 1: 8K, 2: 16K, 3: 32K, 4:  64K, 5: 128K, 6: 256K, 7: 512K, 
8: 1M, 9: 2M, 10: 4M, 11: 8M, 12: 16M, 13: 32M, 14: 64M, 15: 128MThis field is ignored if END=1.
STOP When the output region indicated by this entry is filled, software should disable packet generation. This will be 
accomplished by setting IA32_RTIT_STAT US.Stopped, which clears TriggerEn. This bit must be 0 if END=1; oth-
erwise it is treated as reserved bit violation (see ToPA Errors).
INT When the output region indica ted by this entry is filled, signal Perfmon LVT interrupt. 
Note that if both INT and STOP are se t in the same entry, the STOP will ha ppen before the INT. Thus the inter-
rupt handler should expect that the IA32_RTIT_STATUS.Sto pped bit will be set, and wi ll need to be reset before 
tracing can be resumed.
This bit must be 0 if END=1; otherwise it is tr eated as reserved bit violation (see ToPA Errors).
END If set, indicates that this is an END entry, and thus the address field points to a table base  rather than an output 
region base.
If END=1, INT and STOP must be set to 0; otherwise it is  treated as reserved bit violation (see ToPA Errors). The 
Size field is ignored in this case.If the processor supports only a single ToPA output re gion (see above), END must be set in the second table 
entry.Table 33-3. ToPA Table Entry Fields (Contd.)
ToPA Entry Field Description33-14 Vol. 3CINTEL® PROCESSOR TRACE
Intel PT is not frozen on PMI, and thus the interrupt hand ler will be traced (though filtering can prevent this). The 
Freeze_Perfmon_on_PMI and Freeze_LBRs_on_PMI settings in IA32_DEBUGCTL will be applied on ToPA PMI just as 
on other PMIs, and hence Perfmon counters are frozen.
Assuming the PMI handler wishes to read any buffered packet s for persistent output, or wishes to modify any Intel 
PT MSRs, software should first disable packet generation by  clearing TraceEn. This ensures that all buffered packets 
are written to memory and avoids tracing of the PMI hand ler. The configuration MSRs can then be used to deter-
mine where tracing has stopped. If packet generation is di sabled by the handler, it should then be manually re-
enabled before the IRET if continued tracing is desired.
In rare cases, it may be possible to trigger a second ToPA PMI before the first is handled. This can happen if another 
ToPA region with INT=1 is filled before, or shortly after,  the first PMI is taken, perhaps due to EFLAGS.IF being 
cleared for an extended period of time. This can manifest in two ways: either the second PMI is triggered before the 
first is taken, and hence only one PMI is taken, or the seco nd is triggered after the first is taken, and thus will be 
taken when the handler for the first completes. Software can minimize the likelihood of the second case by clearing 
TraceEn at the beginning of the PMI handler. Further, it  can detect such cases by then checking the Interrupt 
Request Register (IRR) for PMI pending, and checking the ToPA table base and off-set pointers (in 
IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS) to see if multiple entries with INT=1 have been 
filled.
PMI Preservation
In some cases a ToPA PMI may be taken after completion of an XSAVES instruction that saves Intel PT state, and in 
such cases any modification of Intel PT MSRs within the PM I handler will not persist when the saved Intel PT context 
is later restored with XRSTORS. To account for such a scenario, the PMI Preservation feature has been added. 
Support for this feature is indicated by CPUID.(EAX=14H, ECX=0):EBX[bit 6].
When IA32_RTIT_CTL.InjectPsbPmiOnEnable[56] = 1, PMI pr eservation is enabled. When a ToPA region with 
INT=1 is filled, a PMI is pended and the new IA32_RTIT_STATUS.PendToPAPMI[7] is set to 1. If this bit is set when Intel PT is enabled, such that IA32_RTIT_CTL.TraceEn[0]  transitions from 0 to 1, a ToPA PMI is pended. This 
behavior ensures that any ToPA PMI that is pended during  XSAVES, and hence can't be pr operly handled, will be re-
pended when the saved PT state is restored.
When this feature is enabled, the PMI handler should take the following actions:
1. Ignore ToPA PMIs that are taken when TraceEn = 0. Th is indicates that the PMI was pended during Intel PT 
disable, and the PendToPAPMI flag will ensure that the PMI is re-pended once Intel PT is re-enabled in the same 
context. For this reason, the PendToPAPMI bit should be left set to 1.
2. If TraceEn=1 and the PMI can be properly handled, cl ear the new PendTopaPMI bit. This will ensure that 
additional, spurious ToPA PMIs are not taken. It is required that PendToPAPMI is cleared before the PMI LVT 
mask is cleared in the APIC, and before any cleari ng of either LBRS_FROZEN or COUNTERS_FROZEN in 
IA32_PERF_GLOBAL_STATUS. 
ToPA PMI and Single Output Region ToPA Implementation
A processor that supports only a single ToPA output regi on implementation (such that only one output region is 
supported; see above) will attempt to signal a ToPA PMI interrupt before the output wraps and overwrites the top 
of the buffer. To support this functionality, the PMI handler should disable packet generation as soon as possible.
Due to PMI skid, it is possible that, in rare cases, the wrap  will have occurred before the PMI is delivered. Software 
can avoid this by setting the STOP bit in the ToPA entry (see Table 33-3); this will disable tracing once the region is filled, and no wrap will occur. This approach has the downsi de of disabling packet generation so that some of the 
instructions that led up to the PMI will not be traced. If the PMI skid is signif icant enough to cause the region to fill 
and tracing to be disabled, the PMI handler will need to clear the IA32_RTIT_STATUS.Stopped indication before 
tracing can resume.Vol. 3C 33-15INTEL® PROCESSOR TRACE
ToPA PMI and XSAVES/XRSTORS State Handling
In some cases the ToPA PMI may be taken after completion of an XSAVES instruction that switches Intel PT state, 
and in such cases any modification of Intel PT MSRs within  the PMI handler will not persist when the saved Intel PT 
context is later restored with XRSTORS. To account for such  a scenario, it is recommended that the Intel PT output 
configuration be modified by altering the ToPA tables them selves, rather than the Intel PT output MSRs. On proces-
sors that support PMI preservation (CPUID.(EAX=14H, ECX=0):EBX[bit 6] = 1), setting IA32_RTIT_CTL.InjectPsb-
PmiOnEnable[56] = 1 will ensure that a PMI that is pending at  the time PT is disabled will be recorded by setting 
IA32_RTIT_STATUS.PendTopaPMI[7] = 1. A PMI will then be pended when the saved PT context is later restored.
Table 33-4 depicts a recommended PMI handler algorithm fo r managing multi-region ToPA output and handling 
ToPA PMIs that may arrive between XSAVES and XRSTORS, if PMI preservation is not in use. This algorithm is flex-
ible to allow software to choose between adding entries to the current ToPA table, adding a new ToPA table, or using 
the current ToPA table as a circular buffer. It assumes that the ToPA entry that triggers the PMI is not the last entry 
in the table, which is the recommended treatment.
ToPA Errors
When a malformed ToPA entry is found, an operational error  results (see Section 33.3.10). A malformed entry 
can be any of the following:
1.ToPA entry reserved bit violation .
This describes cases where a bit marked as reserved in Section 33.2.7.2 above is set to 1.
2.ToPA alignment violation .
This includes cases where illegal ToPA entry base address bits are set to 1:
a. ToPA table base address is not 4KB-aligned. The table base can be from a WRMSR to 
IA32_RTIT_OUTPUT_BASE, or from a ToPA entry with END=1.
b. ToPA entry base address is not aligned to the ToPA en try size (e.g., a 2MB region with base address[20:12] 
not equal to 0), for ToPA entries with END=0.
c. ToPA entry base address sets upper physical  address bits not supported by the processor.Table 33-4. Algorithm to Manage Intel PT ToPA PMI and XSAVES/XRSTORS 
Pseudo Code Flow
IF (IA32_PERF_GLOBAL_STATUS.ToPA)

    Save IA32_RTIT_CTL value;    IF ( IA32_RTIT_CTL.TraceEN )        Disable Intel PT by clearing TraceEn;     FI;    IF ( there is space available to grow the current ToPA table )        Add one or more ToPA entries after the last entry in the ToPA table;         Point new ToPA entry address field(s) to new output region base(s);    ELSE         Modify an upcoming ToPA entry in the current table to have END=1;        IF (output should transition to a new ToPA table )            Point the address of the “END=1” entry of the current table to the new table base;         ELSE             /* Continue to use the current ToPA table, make a circular. */             Point the address of the “END=1”l entry to the base of the current table;             Modify the ToPA entry address fields for filled output regions to point to new, unused output regions;            /* Filled regions are those with index in the range of 0 to (IA32_RTIT_MASK_PTRS.MaskOrTableOffset -1). */         FI;
FI;
Restore saved IA32_RTIT_CTL.value;
FI;33-16 Vol. 3CINTEL® PROCESSOR TRACE
3.Illegal ToPA Output Offset .
IA32_RTIT_OUTPUT_MASK_PTRS.OutputOffset is greater than  or equal to the size of the current ToPA output 
region size.
4.ToPA rules violations .
These are similar to ToPA entry reserved bit violations; they are cases when a ToPA entry is encountered with 
illegal field combinations. They include the following:
a. Setting the STOP or INT bit on an entry with END=1.
b. Setting the END bit in entry 0 of a ToPA table.c. On processors that support only a single ToPA entry (see above), two additional illegal settings apply:
i) ToPA table entry 1 with END=0.
ii) ToPA table entry 1 with base address not matching the table base.
In all cases, the error will be logged by setting IA32_R TIT_STATUS.Error, thereby disabling tracing when the prob-
lematic ToPA entry is reached (when proc_trace_table_offset  points to the entry containing the error). Any packet 
bytes that are internally buffered when  the error is detected may be lost. 
Note that operational errors may also be signaled du e to attempts to access restricted memory. See Section 
33.2.7.4 for details.
A tracing software have a range of flexibility using ToPA to manage the interaction of Intel PT with application 
buffers, see Section 33.4.2.26.
33.2.7.3  Trace Transport Subsystem 
When IA32_RTIT_CTL.FabricEn is set, the IA32_RTIT_CTL.ToP A bit is ignored, and trace output is written to the 
trace transport subsystem. The endpoints of this transp ort are platform-specific, and details of configuration 
options should refer to the specific platform documentation. The FabricEn bit is available to be set if CPUID(EAX=14H,ECX=0):EBX[bit 3] = 1.
33.2.7.4  Restricted Memory Access
Packet output cannot be directed to any regions of memory  that are restricted by the platform. In particular, all 
memory accesses on behalf of packet output are checked against the SMRR regions. If there is any overlap with 
these regions, trace data collection will not function pr operly. Exact processor behavior is implementation-depen-
dent; Table 33-5 summarizes several scenarios.
It should also be noted that packet output should not be  routed to the 4KB APIC MMIO region, as defined by the 
IA32_APIC_BASE MSR. For details ab out the APIC, refer to the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 3A. No error is signaled for this case.
Modifications to Restricted Memory Regions
It is recommended that software disable packet generation  before modifying the SMRRs to change the scope of the 
SMRR regions. This is because the processor reserves the right to cache any number of ToPA table entries inter-
nally, after checking them against restricted memory ranges. Once cached, the entries will not be checked again, 
meaning one could potentially route packet output to a newly restricted region. Software can ensure that any 
cached entries are written to memory by clearing IA32_RTIT_CTL.TraceEn.Table 33-5. Behavior on Restricted Memory Access
Scenario Description
ToPA output region 
overlaps with 
SMRRStores to the restricted memory region  will be dropped, and that packet data will be lost. Any attempt to read 
from that restricted region will return all 1s. The proc essor also may signal an error (Section 33.3.10) and dis-
able tracing when the output  pointer reaches the restricted region. If packet generation remains enabled, then 
packet output may continue on ce stores are no longer directed to restricted memory (on wrap, or if the output 
region is larger than the restricted memory region).
ToPA table overlaps 
with SMRRThe processor will signal an error (Section 33.3.10) and disable tracing when the ToPA write pointer (IA32_R-
TIT_OUTPUT_BASE + proc_trace_table_offset) enters the restricted region.Vol. 3C 33-17INTEL® PROCESSOR TRACE
33.2.8 Enabling and Configuration MSRs
33.2.8.1  General Considerations
Trace packet generation is enabled and configured by a collection of model-specific registers (MSRs), which are 
detailed below. Some notes on the configuration MSR behavior:
•If Intel Processor Trace is not supported by the pr ocessor (see Section 33.3.1), RDMSR or WRMSR of the 
IA32_RTIT_* MSRs will cause #GP. 
•A WRMSR to any of the IA32_RTIT_* configuratio n MSRs while packet generation is enabled 
(IA32_RTIT_CTL.TraceEn=1) will generate a #GP exception.  Packet generation must be disabled before the 
configuration MSRs can be changed.
Note: Software may write the same value back to  IA32_RTIT_CTL without #GP, even if TraceEn=1.
•All configuration MSRs for Intel PT are duplicated per logical processor
•For each configuration MSR, any MSR write that attempts to change bits marked reserved, or utilize encodings 
marked reserved, will cause a #GP fault.
•All configuration MSRs for Intel PT ar e cleared on a warm or cold RESET. 
— If CPUID.(EAX=14H, ECX=0):E BX[bit 2] = 1, only the TraceEn bit is cleared on warm RESET; though this 
may have the impact of clearing other bits in IA32_ RTIT_STATUS. Other MSR values of the trace configu-
ration MSRs are preserved on warm RESET.
•The semantics of MSR writes to trace configuration MSRs in this chapter generally apply to explicit WRMSR to 
these registers, using VMexit or VM entry MSR load list to these MSRs, XRSTORS with requested feature bit 
map including XSAVE map component of state_8 (corre sponding to IA32_XSS[bit 8]), and the write to 
IA32_RTIT_CTL.TraceEn by XSAVES (Section 33.3.5.2).
33.2.8.2  IA32_RTIT_CTL MSR
IA32_RTIT_CTL, at address 570H, is the primary enable an d control MSR for trace packet generation. Bit positions 
are listed in Table 33-6.
Table 33-6. IA32_RTIT_CTL MSR
Position Bit Name At Reset Bit Description
0 TraceEn 0 If 1, enables tracing;  else tracing is disabled.
When this bit transitions from 1 to 0, all buffered packets are flushed out of internal buffers. 
A further store, fence, or architecturally serializing instruction may be required to ensure that 
packet data can be observed at the trace endpoint. See Section 33.2.8.3 for details of 
enabling and disabling packet generation.
Note that the processor will clea r this bit on #SMI (Section 33.2.9.3) and warm reset. Other 
MSR bits of IA32_RTIT_CTL (and other trace co nfiguration MSRs) are not impacted by these 
events.
1 CYCEn 0 0: Disables CYC Packet (see Section 33.4.2.14).
1: Enables CYC Packet.This bit is reserved if CPUID.(EAX=14H, ECX=0):EBX[bit 1] = 0.
2 OS 0 0: Packet generation is disabled when CPL = 0.
1: Packet generation may be enabled when CPL = 0.
3 User 0 0: Packet generation is disabled when CPL > 0.
1: Packet generation may be enabled when CPL > 0.
4 PwrEvtEn 0 0: Power Event Trace packets are disabled.
1: Power Event Trace packets are enabled (see Section 33.2.3, “Power Event Tracing”).33-18 Vol. 3CINTEL® PROCESSOR TRACE
5 FUPonPTW 0 0: PTW packets are not followed by FUPs.
1: PTW packets are followed by FUPs.
This bit is reserved when CPUID.(EAX=14H, EC X=0):EBX[bit 4] (“PTWRITE Supported”) is 0.
6 FabricEn 0 0: Trace output is directed to the memory subsystem, mechanism depends on 
IA32_RTIT_CTL.ToPA.
1: Trace output is directed to the trace transp ort subsystem, IA32_RTIT_ CTL.ToPA is ignored. 
This bit is reserved if CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0.
7 CR3Filter 0 0: Disables CR3 filtering.
1: Enables CR3 filtering.
This bit is reserved if CPUID.(EAX=14H, ECX=0) :EBX[bit 0] (“CR3 Filt ering Support”) is 0.
8 ToPA 0 0: Single-range output scheme enabled if CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] 
= 1 and IA32_RTIT_CTL.FabricEn=0.
1: ToPA output scheme enabled (see Section 33.2.7.2) if CPUID.(EAX=14H, 
ECX=0):ECX.TOPA[bit 0] = 1, and IA32_RTIT_CTL.FabricEn=0.
Note: WRMSR to IA32_RTIT_CTL th at sets TraceEn but clears this bit and FabricEn would 
cause #GP, if CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0.
WRMSR to IA32_RTIT_CTL that sets this  bit causes #GP, if CPUID.(EAX=14H, 
ECX=0):ECX.TOPA[bit 0] = 0.
9 MTCEn 0 0: Disables MTC Pack et (see Section 33.4.2.16).

1: Enables MTC Packet.This bit is reserved if CPUID.(EAX=14H, ECX=0):EBX[bit 3] = 0.
10 TSCEn 0 0: Disable TSC packets.
1: Enable TSC packets (see Section 33.4.2.11).
11 DisRETC 0 0: Enable RET compression.
1: Disable RET compression (see Section 33.2.1.2).
12 PTWEn 0 0: PTWRITE packet generation disabled.
1: PTWRITE packet generation enabled (see Table 33-40 “PTW Packet Definition”).
13 BranchEn 0 0: Disable COFI-based packets.
1: Enable COFI-based packets: FUP, TIP, TI P.PGE, TIP.PGD, TNT, MODE.Exec, MODE.TSX.
See Section 33.2.6.4 for details on BranchEn.
17:14 MTCFreq 0 Defines MTC packet Frequency, which is based on the core crystal clock, or Always Running 
Timer (ART). MTC will be sent each time the se lected ART bit toggles. The following Encodings 
are defined:
0: ART(0), 1: ART(1), 2: ART(2), 3: ART(3), 4: ART(4), 5: ART(5), 6: ART(6), 7: ART(7), 
8: ART(8),  9: ART(9), 10: ART(10), 11: ART(11) , 12: ART(12), 13: ART(13), 14: ART(14), 15: 
ART(15)
Software must use CPUID to query the support ed encodings in the pr ocessor, see Section 
33.3.1. Use of unsupported encodings will result  in a #GP fault. This field is reserved if 
CPUID.(EAX=14H, ECX=0):EBX[bit 3] = 0.
18 Reserved 0 Must be 0.Table 33-6. IA32_RTIT_CTL MSR (Contd.)
Position Bit Name At Reset Bit DescriptionVol. 3C 33-19INTEL® PROCESSOR TRACE
22:19 CycThresh 0 CYC packet threshold, see Section 33.3.6  for details. CYC packets wi ll be sent with the first 
eligible packet after N cycles have passed since the last CYC packet. If CycThresh is 0 then 
N=0, otherwise N is defined as 2(CycThresh-1). The following Encodings are defined:
0: 0, 1: 1, 2: 2, 3: 4, 4: 8, 5: 16, 6: 32, 7: 64, 
8: 128, 9: 256, 10: 512, 11: 1024, 12: 2048, 13: 4096, 14: 8192, 15: 16384
Software must use CPUID to query the support ed encodings in the processor, see Section 
CPUID.(EAX=14H, ECX=0):EBX[bit 1] = 0.
23 Reserved 0 Must be 0.
27:24 PSBFreq 0 Indicates the frequency of PSB packets. PSB packet frequency is based on the number of Intel 
PT packet bytes output, so this field allo ws the user to determ ine the increment of 
IA32_IA32_RTIT_STATUS.PacketByte Cnt that should caus e a PSB to be gene rated. Note that 
PSB insertion is not precise, but the average output bytes per PSB should approximate the 
SW selected period. The following Encodings are defined:
0: 2K, 1: 4K, 2: 8K, 3: 16K, 4: 32K, 5: 64K, 6: 128K, 7: 256K, 
8: 512K, 9: 1M, 10: 2M, 11: 4M, 12: 8M, 13: 16M, 14: 32M, 15: 64MSoftware must use CPUID to query the support ed encodings in the processor, see Section 
30:28 Reserved 0 Must be 0.
31 EventEn 0 0: Event Trace packets are disabled.
1: Event Trace packets are enabled.This bit is reserved when CPUID.(EAX=14H, ECX=0 ):EBX[bit 7] (“Event Trace Supported”) is 0.
35:32 ADDR0_CFG 0 Configures the base/limit register pair IA32_RTIT_ADDR0_A/B based on the following 
encodings:
0: ADDR0 range unused.
1: The [IA32_RTIT_ADDR0_A..IA32_RTIT_ADDR0_B] range defines a FilterEn range. FilterEn 
will only be set when the IP is within this range, th ough other FilterEn ranges can additionally 
be used. See Section 33.2.5.3 for details on IP filtering.
2: The [IA32_RTIT_ADDR0_A..IA32_RTIT_ADD R0_B] range defines a TraceStop range. 
TraceStop will be asserted if code branches into  this range. See 4.2.8 for details on TraceStop.
3..15: Reserved (#GP).
This field is reserved if CPUID.(EAX=14H, ECX=1):EBX.RANGECNT[2:0] < 1.
39:36 ADDR1_CFG 0 Configures the base/limit register pair IA32_RTIT_ADDR1_A/B based on the following 
0: ADDR1 range unused.
1: The [IA32_RTIT_ADDR1_A..IA32_RTIT_ADDR1_B] range defines a FilterEn range. FilterEn 
2: The [IA32_RTIT_ADDR1_A..IA32_RTIT_ADD R1_B] range defines a TraceStop range. 
TraceStop will be asserted if code branches into  this range. See Section 33.4.2.10 for details 
on TraceStop.
This field is reserved if CPUID.(EAX=14H, ECX=1):EBX.RANGECNT[2:0] < 2.Table 33-6. IA32_RTIT_CTL MSR (Contd.)
Position Bit Name At Reset Bit Description33-20 Vol. 3CINTEL® PROCESSOR TRACE
33.2.8.3  Enabling and Disabling Packet Generation with TraceEn
When TraceEn transitions from 0 to 1, Intel Processor Trac e is enabled, and a series of packets may be generated. 
These packets help ensure that the decoder is aware of th e state of the processor when the trace begins, and that 
it can keep track of any timing or state changes that may have occurred while packet generation was disabled. A full PSB+ (see Section 33.4.2.17) will be generated if  IA32_RTIT_STATUS.PacketByteCnt=0, and may be gener-
ated in other cases as well. Otherwise, timing packets wi ll be generated, including TSC, TMA, and CBR (see Section 
33.4.1.1). 
In addition to the packets discussed above, if and when Pa cketEn (Section 33.2.6.1) transitions from 0 to 1 (which 
may happen immediately, depending on filtering settings), a TIP.PGE packet (Section 33.4.2.3) will be generated. 
When TraceEn is set, the processor may read ToPA entries from memory and cache them internally. For this reason, 
software should disable packet generation before making modifications to the ToPA tables (or changing the config-43:40 ADDR2_CFG 0 Configures the base/limit register pair IA32_RTIT_ADDR2_A/B based on the following 
0: ADDR2 range unused.
1: The [IA32_RTIT_ADDR2_A..IA32_RTIT_ADDR2_B] range defines a FilterEn range. FilterEn 
will only be set when the IP is within this range, though other FilterEn ranges can additionally 
2: The [IA32_RTIT_ADDR2_A..IA32_RTIT_ADDR 2_B] range defines a TraceStop range. 
TraceStop will be asserted if co de branches into this range. See Section 33.4.2.10 for details 
3..15: Reserved (#GP).This field is reserved if CPUID.(EAX=14H, ECX=1):EBX.RANGECNT[2:0] < 3.
47:44 ADDR3_CFG 0 Configures the base/limit register pair IA32_RTIT_ADDR3_A/B based on the following 
0: ADDR3 range unused.1: The [IA32_RTIT_ADDR3_A..IA32_RTIT_ADDR3_B] range defines a FilterEn range. FilterEn 
2: The [IA32_RTIT_ADDR3_A..IA32_RTIT_ADDR 3_B] range defines a TraceStop range. 
This field is reserved if CPUID.(EAX=14H, ECX=1):EBX.RANGECNT[2:0] < 4.
54:48 Reserved 0 Reserved only for future trace content enables, or address filtering configuration enables. 
Must be 0.
55 DisTNT 0 0: Include TNT pack ets in control flow trace.
1: Omit TNT packets from control flow trace.
This bit is reserved when CPUID.(EAX=14H, ECX=0 ):EBX[bit 8] (“TNT Disa ble Supported”) is 0. 
SeeSection 33.3.9 for details.
56 InjectPsbPmi
OnEnable0 1: Enables use of IA32_RTIT_STATUS bits Pe ndPSB[6] and PendTopa PMI[7], see Section 
33.2.8.4, “IA32_RTIT_STATUS MSR,” for behavior of these bits.
0: IA32_RTIT_STATUS bits 6 and 7 are ignored.
This field is reserved if CPUID.(EAX=14H, ECX=0):EBX[ bit 6] = 0.
59:57 Reserved 0 Reserved only for future trace content enables, or address filtering configuration enables. 
Must be 0.
63:60 Reserved 0 Must be 0.Table 33-6. IA32_RTIT_CTL MSR (Contd.)
Position Bit Name At Reset Bit DescriptionVol. 3C 33-21INTEL® PROCESSOR TRACE
uration of restricted memory regions). See Section 33.7 for more details of packets that may be generated with 
modifications to TraceEn.
Disabling Packet Generation
Clearing TraceEn causes any packet data buffered within the logical processor to be flushed out, after which the 
output MSRs (IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS) will have stable values. When 
output is directed to memory, a store, fence, or architec turally serializing instruction may be required to ensure 
that the packet data is globally observed. No special pa ckets are generated by disabling packet generation, though 
a TIP.PGD may result if PacketEn=1 at the time of disable.
Other Writes to IA32_RTIT_CTL
Any attempt to modify IA32_RTIT_CTL wh ile TraceEn is set will result in a ge neral-protection fault (#GP) unless the 
same write also clears TraceEn. However, writes to IA32_RTIT_CTL that do not modify any bits will not cause a 
#GP, even if TraceEn remains set.
33.2.8.4  IA32_RTIT_STATUS MSR
The IA32_RTIT_STATUS MSR is readable an d writable by software, though some fields cannot be modified by soft-
ware. See Table 33-7 for details. The WRMSR instruction ig nores these bits in the source operand (attempts to

ware. See Table 33-7 for details. The WRMSR instruction ig nores these bits in the source operand (attempts to 
modify these bits are ignored and do not cause WRMSR to fault).
This MSR can only be written when IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection 
fault (#GP). The processor does not modify the value of th is MSR while TraceEn is 0 (software can modify it with 
WRMSR).
Table 33-7. IA32_RTIT_STATUS MSR
0 FilterEn 0 This bit is written by th e processor, and indicates that trac ing is allowed for the current IP, 
see Section 33.2.6.5. Writes are ignored.
1 ContextEn 0 The processor sets this bit to indicate that tracing is a llowed for the current context. See 
Section 33.2.6.3. Wr ites are ignored.
2 TriggerEn 0 The processor sets this bi t to indicate that tracing is enable d. See Section 33.2.6.2. Writes are 
ignored.
3 Reserved 0 Must be 0. 
4 Error 0 The processor sets this bit to indicate that  an operational error has been encountered. When 
this bit is set, TriggerEn is cleared to 0 and packet generation is disabled. For details, see 
“ToPA Errors” in Section 33.2.7.2.
When TraceEn is cleared, software can write this bi t. Once it is set, only software can clear it. 
It is not recommended that softwa re ever set this bit, except in cases where it is restoring a 
prior saved state.
5 Stopped 0 The processor sets this bit to indicate that a ToPA Stop condition has been encountered. 
When this bit is set, TriggerEn is cleared to 0 and packet generation is disabled. For details, see “ToPA STOP” in Section 33.2.7.2.
6 PendPSB 0 If IA32_RTIT_CTL.InjectPsbPmiOnEnable[56]  = 1, the processor sets this bit when the 
threshold for a PSB+ to be inserted has been reached. The processor will clear this bit when 
the PSB+ has been inserted into the trace. If PendPSB = 1 and InjectPsbPmiOnEnable = 1 
when IA32_RTIT_CTL.TraceEn[0] transitions from 0 to  1, a PSB+ will be inserted into the 
trace.
This field is reserved if  CPUID.(EAX=14H, ECX=0):EBX[ bit 6] = 0.33-22 Vol. 3CINTEL® PROCESSOR TRACE
33.2.8.5  IA32_RTIT_ADDRn_ A and IA32_RTIT_ADDRn_B MSRs
The role of the IA32_RTIT_ADDRn_A/B register pairs, for each n, is determined by the corresponding ADDRn_CFG 
fields in IA32_RTIT_CTL (see Section 33.2.8.2). The number of these register pairs is enumerated by 
CPUID.(EAX=14H, ECX=1):EAX.RANGECNT[2:0].
•Processors that enumerate support for 1 range support:
— IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
•Processors that enumerate support for 2 ranges support:— IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
— IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B
•Processors that enumerate support for 3 ranges support:
— IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B— IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B
— IA32_RTIT_ADDR2_A, IA32_RTIT_ADDR2_B
•Processors that enumerate support for 4 ranges support:
— IA32_RTIT_ADDR3_A, IA32_RTIT_ADDR3_B
Each register has a single 64-bit field that holds a linear address value. Writes must ensure that the address is in 
canonical form, otherwise a general-protection fault (#GP) fault will result.
Each MSR can be written only when IA32_RTIT_CTL.TraceE n is 0; otherwise WRMSR causes a general-protection 
fault (#GP).
33.2.8.6  IA32_RTIT_CR3_MATCH MSR
The IA32_RTIT_CR3_MATCH register is compared against CR 3 when IA32_RTIT_CTL.CR3Filter is 1. Bits 63:5 hold 
the CR3 address value to match, bits 4:0 are reserved to 0. For more details on CR3 filtering and the treatment of 
this register, see Section 33.2.5.2.7 PendTopaPMI 0 If IA32_RTIT_CTL.InjectPsbPmiOnEnable[5 6] = 1, the processor sets this bit when the 
threshold for a ToPA PMI to be inserted has been reached. Software should clear this bit once 
the ToPA PMI has been handled, see “ToPA PMI” for details. If  PendTopaPMI = 1 and 
InjectPsbPmiOnEnable = 1 when IA32_RTIT_CTL.TraceEn[0] transitions from 0 to 1, a PMI will 
be pended.
31:8 Reserved 0 Must be 0. 
48:32 PacketByteCnt 0 This field is written by the processor, and holds a count of packet bytes that have been sent 
out. The processor also uses this field to de termine when the next PSB packet should be 
inserted. Note that the proc essor may clear or modify th is field at any time while 
IA32_RTIT_CTL.TraceEn=1. It will have a stable value when IA32_RTIT_CTL.TraceEn=0.
See Section 33.4.2.17 for details.
This field is reserved when CPUID.(EAX=14H ,ECX=0):EBX[bit 1] (“Configurable PSB and 
CycleAccurate Mode Supported”) is 0.
63:49 Reserved 0 Must be 0.Table 33-7. IA32_RTIT_STATUS MSR
Position Bit Name At Reset Bit DescriptionVol. 3C 33-23INTEL® PROCESSOR TRACE
This MSR is accessible if CPUID.(EAX= 14H, ECX=0):EBX[bit 0], “CR3 Filtering Support”, is 1. This MSR can be 
written only when IA32_RTIT_CTL.TraceEn is 0; otherw ise WRMSR causes a general-protection fault (#GP). 
IA32_RTIT_CR3_MATCH[4:0] are reserved and must be 0;  an attempt to set those bits using WRMSR causes a 
#GP.
33.2.8.7  IA32_RTI T_OUTPUT_BASE MSR
This MSR is used to configure the trace output destination, when output is directed to memory 
(IA32_RTIT_CTL.FabricEn = 0). The size of the address fiel d is determined by the maximum physical address width 
(MAXPHYADDR), as reported by CPUID.80000008H:EAX[7:0].
When the ToPA output scheme is used, the processor may u pdate this MSR when packet generation is enabled, and 
those updates are asynchronous to instruction execution. Th erefore, the values in this MSR should be considered 
unreliable unless packet generation is disabled (IA32_RTIT_CTL.TraceEn = 0).
Accesses to this MSR are supported only if Intel PT output to memory is supported, hence when either 
CPUID.(EAX=14H, ECX=0):ECX[b it 0] or CPUID.(EAX=14H, ECX=0):ECX[b it 2] are set. Otherwise WRMSR or 
RDMSR cause a general-protection fault (#GP). If supported, this MSR can be written only when 
IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection fault (#GP).
33.2.8.8  IA32_RTIT_OUTPUT_MASK_PTRS MSR
This MSR holds any mask or pointer values needed to in dicate where the next byte of trace output should be 
written. The meaning of the values held  in this MSR depend on whether the ToPA output mechanism is in use. See 
Section 33.2.7.2 for details.
The processor updates this MSR while when packet generati on is enabled, and those updates are asynchronous to 
instruction execution. Therefore, the values in this MSR should be considered unreliable unless packet generation 
is disabled (IA32_RTIT_CTL.TraceEn = 0).
IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection fault (#GP).Table 33-8. IA32_RTIT_OUTPUT_BASE MSR
6:0 Reserved 0 Must be 0.
MAXPHYADDR-1:7 BasePhysAddr 0 The base physical address. How this address is used depends on the value of 
IA32_RTIT_CTL.ToPA:
0: This is the base physical  address of a single, contiguous physical output region. 
This could be mapped to DRAM or to MMIO, depending on the value.
The base address should be aligned with th e size of the region, such that none of 
the 1s in the mask value(Section 33.2.8.8) overlap with 1s in the base address. If 
the base is not aligned, an operationa l error will result (s ee Section 33.3.10).
1: The base physical address of the current ToPA table. The address must be 4K 
aligned. Writing an address in which bits 11:7 are non-zero will not cause a #GP, but 
an operational error will be signaled once TraceEn is set. See “ToPA Errors” in Section 33.2.7.2, as well as Section 33.3.10.
63:MAXPHYADDR Reserved 0 Must be 0.33-24 Vol. 3CINTEL® PROCESSOR TRACE
33.2.9 Interaction of Intel® Processo r Trace and Other Processor Features
33.2.9.1  Intel® Transactional Sync hronization Extensions (Intel® TSX) 
The operation of Intel TSX is described in Chapter 14 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1. For tracing purpose, packet generati on does not distinguish between hardware lock elision 
(HLE) and restricted transactional memory (RTM), but speculative execution does have impacts on the trace 
output. Specifically, packets are generated as instructions complete, even for instructions in a transactional region 
that is later aborted. For this reason, debugging software  will need indication of the beginning and end of a trans-
actional region; this will allow software to understand when instructions are part of a transactional region and whether that region has been committed.

To enable this, TSX information is included in a MODE packet leaf. The mode bits in the leaf are:
•InTX : Set to 1 on an TSX transaction begin, and cleared on transaction commit or abort.
•TXAbort : Set to 1 only when InTX transitions from 1 to 0 on an abort. Cleared otherwise.
If BranchEn=1, this MODE packet will be sent each time the transaction status changes. See Table 33-10 for 
details.Table 33-9. IA32_RTIT_OUTPUT_MASK_PTRS MSR
6:0 LowerMask 7FH Forced to 1, writes are ignored. 
31:7 MaskOrTableO
ffset0 The use of this field depends on  the value of IA32_RTIT_CTL.ToPA:
0: This field holds bits 31:7 of the mask value for the single, contiguous physical output 
region. The size of this field indicates that regions can be of size 128B up to 4GB. This value 
(combined with the lower 7 bi ts, which are reserved to 1) will be ANDed with the 
OutputOffset field to determine the next write address. All 1s in this field should be consecutive and starting at bit 7, otherwise the region will not be contiguous, and an 
operational error (Section 33.3.10) will be signaled when TraceEn is set.
1: This field holds bits 27:3 of the offset poin ter into the current ToPA  table. This value can 
be added to the IA32_RTIT_OUTPUT_BASE value to produce a pointer to the current ToPA 
table entry, which itself is a po inter to the current output region . In this scenario, the lower 7 
reserved bits are ignored. This field supp orts tables up to 256 MBytes in size.
63:32 OutputOffset 0 The use of this field de pends on the value of IA32_RTIT_CTL.ToPA:
0: This is bits 31:0 of the of fset pointer into the single, cont iguous physical output region. 
This value will be added to the IA32_RTIT_OUTP UT_BASE value to form the physical address 
at which the next byte of packet output data will be written. This value must be less than or equal to the MaskOrTableOffset field, otherwise an operational error (Section 33.3.10) will 
be signaled when TraceEn is set.
1: This field holds bits 31:0 of the offset po inter into the current To PA output region. This 
value will be added to the output region base field, found in th e current ToPA table entry, to 
form the physical address at which the next byte of trace output data will be written.
This value must be less than the ToPA entry size, otherwise an operational error (Section 
33.3.10) will be signaled  when TraceEn is set. 
Table 33-10. TSX Packet Scenarios with BranchEn=1
TSX Event Instruction Packets
Transaction Begin Either XBEGIN or XACQ UIRE lock (the latter if executed 
transactionally)MODE(TXAbort=0, InTX=1), FUP(CurrentIP)
Transaction 
CommitEither XEND or XRELEASE lock, if transactional execution 
ends. This happens only on the outermost commitMODE(TXAbort=0, InTX=0), FUP(CurrentIP)Vol. 3C 33-25INTEL® PROCESSOR TRACE
The CurrentIP listed above is the IP of the associated instru ction. The TargetIP is the IP of the next instruction to 
be executed; for HLE, this is the XACQUIRE lock; for RTM, this is the fallback handler.
Intel PT stores are non-transactional, and thus packet writes are not rolled back on TSX abort.
33.2.9.2  TSX and IP Filtering
A complication with tracking transactions is handling tran sactions that start or end outside of the tracing region. 
Transactions can’t span across a change in ContextEn, because CPL changes and CR3 changes each cause aborts. 
But a transaction can start within the IP filter region and end outside it. 
To assist the decoder handling this situation, MODE.TSX pa ckets can be sent even if FilterEn=0, though there will 
be no FUP attached. Instead, they will merely serve to in dicate to the decoder when transactions are active and 
when they are not. When tracing resumes (due to PacketEn =1), the last MODE.TSX preceding the TIP.PGE will indi-
cate the current transaction status. 
33.2.9.3  System Management Mode (SMM) 
SMM code has special privileges that non-SMM code does not have. Intel Processor Trace can be used to trace SMM code, but special care is taken to ensure that SMM handle r context is not exposed in any non-SMM trace collection. 
Additionally, packet output from tracing non-SMM code cannot be written into memory space that is either protected by SMRR or used by the SMM handler.
SMM is entered via a system management inte rrupt (SMI). SMI delivery saves the value of 
IA32_RTIT_CTL.TraceEn into SMRAM and then clears it, thereby disabling packet generation.
The saving and clearing of IA32_RTIT_CTL.TraceEn ensures two things:
1. All internally buffered packet data is flushed before entering SMM (see Section 33.2.8.2). 
2. Packet generation ceases before entering SMM, so any tracing that was configured outside SMM does not 
continue into SMM. No SMM instruction pointers or  other state will be exposed in the non-SMM trace.
When the RSM instruction is executed to return from SM M, the TraceEn value that was saved by SMI delivery is 
restored, allowing tracing to be resumed. As is done any time packet generation is enabled, ContextEn is re-eval-
uated, based on the values of CP L, CR3, etc., established by RSM.
Like other interrupts, delivery of an SMI produces a FUP co ntaining the IP of the next instruction to execute. By 
toggling TraceEn, SMI and RSM can produce TIP.PGD and TIP. PGE packets, respectively, indicating that tracing was 
disabled or re-enabled. See Table 33.7 for more in formation about packets entering and leaving SMM. 
Although #SMI and RSM change CR3, PIP packets are not ge nerated in these cases. With #SMI tracing is disabled 
before the CR3 change; with RSM TraceEn is restored after CR3 is written.
TraceEn must be cleared before executing RSM, otherwise it will cause a shutdown. Further, on processors that 
restrict use of Intel PT with LBRs (see Section 33.3.1.2), an y RSM that results in enabling of both will cause a shut-
down.
Intel PT can support tracing of System Transfer  Monitor operating in SMM, see Section 33.6.Transaction Abort XABORT or other transactional abort MODE(TXAbort=1, InTX=0), FUP(CurrentIP), 
TIP(TargetIP)
Other One of the following:
• Nested XBEGIN or XACQUIRE lock
• An outer XACQUIRE lock that doesn’t begin a transaction 
(InTX not set)
• Non-outermost XEND or XRELEASE lockNone. No change to TS X mode bits for these 
cases.Table 33-10. TSX Packet Scenarios with BranchEn=1
TSX Event Instruction Packets33-26 Vol. 3CINTEL® PROCESSOR TRACE
33.2.9.4  Virtual-Machine Extensions (VMX)
Initial implementations of Intel Processor Trace do not supp ort tracing in VMX operation. Such processors indicate 
this by returning 0 for IA32_VMX_MISC[bit 14]. On these processors, execution of the VMXON instruction clears 
IA32_RTIT_CTL.TraceEn and any attempt to write IA32_RTIT _CTL in VMX operation causes a general-protection 
Processors that support Intel Processor Trace in VMX op eration return 1 for IA32_VMX_MISC[bit 14]. Details of 
tracing in VMX operation are described in Section 33.4.2.26.
33.2.9.5  Intel® Software Guard Extensions (Intel® SGX)
Intel SGX provides an application with the ability to instan tiate a protective container (an enclave) with confidenti-
ality and integrity (see the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3D). On a 
processor with both Intel PT and Intel SGX enabled, when executing code within a production enclave, no control 
flow packets are produced by Intel PT. An enclave entry will clear ContextEn, thereby blocking control flow packet generation. A TIP.PGD packet will be generate d if PacketEn=1 at the time of the entry.
Upon enclave exit, ContextEn will no long er be forced to 0. If other enables are set at the time, a TIP.PGE may be 
generated to indicate that tracing is resumed.
During the enclave execution, Intel PT remains enabled, and periodic or timing packets such as PSB, TSC, MTC, or 
CBR can still be generated. No IPs or other architectural state will be exposed.
For packet generation examples on en clave entry or exit, see Section 33.7.
Debug Enclaves
Intel SGX allows an enclave to be configured with relaxe d protection of confidentiality for debug purposes, see the 
Intel® 64 and IA-32 Architectures Software Developer’s Manual,  Volume 3D. In a debug enclave, Intel PT continues 
to function normally. Specifically, ContextEn is not impacted  by an enclave entry or exit. Hence, the generation of 
ContextEn-dependent packets with in a debug enclave is allowed.
33.2.9.6  SENTER/ENTERACCS and ACM
GETSEC[SENTER] and GETSEC[ENTERACCS] instructions clear TraceEn, and it is not restored when those instruc-
tion complete. SENTER also causes TraceEn to be cleared on other logical processors when they rendezvous and enter the SENTER sleep state. In these two cases, the disa bling of packet generation is not guaranteed to flush 
internally buffered packets. Some packets may be dropped.
When executing an authenticated code module (ACM), packet  generation is silently disabled during ACRAM setup.

When executing an authenticated code module (ACM), packet  generation is silently disabled during ACRAM setup. 
TraceEn will be cleared, but no TIP.PGD packet is generate d. After completion of the module, the TraceEn value will 
be restored. There will be no TIP.PGE packet, but ti ming packets, like TSC and CBR, may be produced.
33.2.9.7  Intel® Memory Prot ection Extensions (Intel® MPX)
Bounds exceptions (#BR) caused by Intel MPX are trea ted like other exceptions, producing FUP and TIP packets 
that indicate the source and destination IPs.
33.3 CONFIGURATION AND PROGRAMMING GUIDELINE
33.3.1 Detection of Intel Processor Trace and Capability Enumeration
Processor support for Intel Processor Trace is indica ted by CPUID.(EAX=07H,ECX=0 H):EBX[bit 25] = 1. CPUID 
function 14H is dedicated to enumerate the resource and capability of processors that report CPUID.(EAX=07H,ECX=0H ):EBX[bit 25] = 1. Different processor gene rations may have architecturally-defined 
variation in capabilities. Table 33-11 describes details of the enumerable capabilities that software must use across 
generations of processors that support Intel Processor Trace.Vol. 3C 33-27INTEL® PROCESSOR TRACE
Table 33-11. CPUID Leaf 14H Enumeratio n of Intel Processor Trace Capabilities
CPUID.(EAX=14H,ECX=0) Nam e Description Behavior
Register Bits
EAX 31:0 Maximum valid sub-leaf Index Specifies the index of the maximum valid sub-leaf for this CPUID leaf.
EBX0 CR3 Filtering Support 1: Indicates that IA32_R TIT_CTL.CR3Filter can be set to 1, and that 
IA32_RTIT_CR3_MATCH MSR can be accessed. See Section 33.2.8.
0: Indicates that writes that set IA32_RTIT_CTL.CR3Filter to 1, or any 
access to IA32_RTIT_CR3_MATCH, will generate a #GP exception.
1 Configurable PSB and Cycle-
Accurate Mode Supported1: (a) IA32_RTIT_CTL.PSBFreq can be set to a non-zero value, in order to 
select the preferred PSB frequency (s ee below for allowed values). (b) 
IA32_RTIT_STATUS.PacketByteCnt can be set to a non-zero value, and 
will be incremented by the processor when tracing to indicate progress towards the next PSB. If trace packet  generation is enabled by setting 
TraceEn, a PSB will only be gene rated if PacketByteCnt=0. (c) 
IA32_RTIT_CTL.CYCEn can be set to 1 to enable Cycle-Accurate Mode. 
See Section 33.2.8.
0: (a) Any attempt to write a non-ze ro value to IA32_RTIT_CTL.PSBFreq 
or IA32_RTIT_STATUS.PacketByteCnt will generate a #GP exception. (b) 
If trace packet generation is enable d by setting TraceEn, a PSB is always 
generated. (c) Any attempt to write a non-zero value to 
IA32_RTIT_CTL.CYCEn or IA32_RTIT_CTL.CycThresh will generate a #GP 
2 IP Filtering and TraceStop 
supported, and Preserve Intel 
PT MSRs across warm reset1: (a) IA32_RTIT_CTL provides at one or more ADDRn_CFG field to 
configure the corresponding address range MSRs for IP Filtering or IP 
TraceStop. Each ADDRn_CFG field accepts a value in the range of 0:2 inclusive. The number of ADDRn_CFG fields is reported by 
CPUID.(EAX=14H, ECX=1):EAX.RANGECNT[ 2:0]. (b) At least one register 
pair IA32_RTIT_ADDRn_A and IA32 _RTIT_ADDRn_B are provided to 
configure address ranges for IP filter ing or IP TraceStop. (c) On warm 
reset, all Intel PT MS Rs will retain their pr e-reset values, though 
IA32_RTIT_CTL.TraceEn will be cleared. The Intel PT MSRs are listed in Section 33.2.8.
0: (a) An Attempt to write IA32_R TIT_CTL.ADDRn_CFG with non-zero 
encoding values will cause #GP. (b) Any access to IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B, will generate  a #GP exception. (c) On warm 
reset, all Intel PT MSRs will be cleared.
3 MTC Supported 1: IA32_RTIT_CTL.MTCEn can be set to 1, and MTC packets will be 
generated. See Section 33.2.8.
0: An attempt to set IA32_RTIT_C TL.MTCEn or IA32_RTIT_CTL.MTCFreq 
to a non-zero value will generate a #GP exception.
4 PTWRITE Supported 1: Writes can set IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] 
(FUPonPTW), and PTWRITE can generate packets.
0: Writes that set IA32_RTIT_CTL[ 12] or IA32_RTIT_CTL[5] will 
generate a #GP exception, and PTWRITE will #UD fault.
5 Power Event Trace Supported 1: Writes can set IA 32_RTIT_CTL[4] (PwrEvtEn) , enabling Power Event 
Trace packet generation.
0: Writes that set IA32_RTIT_CTL[ 4] will generate a #GP exception.33-28 Vol. 3CINTEL® PROCESSOR TRACE
If CPUID.(EAX=14H, ECX=0):EAX reports a non-zero value, additional capabilities of Intel Processor Trace are 
described in the sub-leaves of CPUID leaf 14H.6 PSB and PMI Preservation 
Supported1: Writes can set IA32_RTIT_CTL[56] (InjectPsbPmiOnEnable), enabling 
the processor to set IA32_RTIT_ STATUS[7] (PendTopaPMI) and/or 
IA32_RTIT_STATUS[6] (PendPSB) in order to preserve ToPA PMIs and/or 
PSBs otherwise lost due to Intel PT disable. Writes can also set 
PendToPAPMI and PendPSB.
0: Writes that set IA32_RTIT_CTL[56], IA32_RTIT_STATUS[7], or 
IA32_RTIT_STATUS[6] will ge nerate a #GP exception.
7 Event Trace Supported 1: Writes can set IA32_R TIT_CTL[31] (EventEn), enabling Event Trace 
packet generation.
0: Writes that set IA32_RTIT_CTL[31] will generate a #GP exception.
8 TNT Disable Supported 1: Writes can set IA32_RTIT_CTL[55] (DisTNT), disabling TNT packet 
0: Writes that set IA32_RTIT_CTL[55] will generate a #GP exception.
31:9 Reserved
ECX0 ToPA Output Supported 1: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing 
the ToPA output scheme (Section  33.2.7.2) IA32_RTIT_OUTPUT_BASE 
and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
0: Unless CPUID.(EAX=14H, ECX=0):ECX.SNGLRNGOUT[bit 2] = 1. writes 
to IA32_RTIT_OUTPUT_BASE or IA32_RTIT_OUTPUT_MASK_PTRS. 
MSRs will generate a #GP exception.
1 ToPA Tables Allow Multiple 
Output Entries1: ToPA tables can hold any number  of output entries, up to the 
maximum allowed by the MaskOrTableOffset field of 
IA32_RTIT_OUTPUT_MASK_PTRS.
0: ToPA tables can hold only one ou tput entry, which must be followed 
by an END=1 entry which points ba ck to the base of the table. 
Further, ToPA PMIs will be delivered before the region is filled. See ToPA 
PMI in Section 33.2.7.2.
If there is more than one output en try before the END entry, or if the 
END entry has the wrong base addre ss, an operational error will be 
signaled (see “ToPA Errors” in Section 33.2.7.2).
2S i n g l e - R a n g e  O u t p u t  
Supported1: Enabling tracing (TraceEn=1) with IA32_RTIT_CTL.ToPA=0 is 
0: Unless CPUID.(EAX=14H, ECX=0):ECX.T OPAOUT[bit 0] = 1. writes to 
IA32_RTIT_OUTPUT_BASE or IA32 _RTIT_OUTPUT_MASK_PTRS. MSRs 
will generate a #GP exception. 
3 Output to Trace Transport 
Subsystem Supported1: Setting IA32_RTIT_CTL.Fa bricEn to 1 is supported.
0: IA32_RTIT_CTL.FabricEn is reserved. Write 1 to 
IA32_RTIT_CTL.FabricEn will generate a #GP exception. 
30:4 Reserved
31 IP Payloads are LIP 1: Generated packets whic h contain IP payloads have LIP values, which 
include the CS base component.
0: Generated packets which contain IP payloads have RIP values, which 
are the offset from CS base. 
EDX 31:0 ReservedTable 33-11. CPUID Leaf 14H Enumeration of Intel Processor Trace Capabilities (Contd.)
Register BitsVol. 3C 33-29INTEL® PROCESSOR TRACE
Table 33-12. CPUID Leaf 14H, sub-leaf 1H En umeration of Intel Processor Trace Capabilities
CPUID.(EAX=14H,ECX=1) Name Description Behavior
EAX 2:0 Number of Address Ranges A non-zero value specifies the number ADDRn_CFG field supported in 
IA32_RTIT_CTL and the number of register pair IA32_RTIT_ADDRn_A/IA32_R TIT_ADDRn_B supported for IP filtering 
and IP TraceStop.
NOTE: Currently, no processors suppor t more than 4 address ranges.
15:3 Reserved
31:16 Bitmap of supported MTC 
Period EncodingsThe non-zero bits indicate the map of supported encoding values for 
the IA32_RTIT_CTL.MTCFreq field. This applies only if 
CPUID.(EAX=14H, ECX=0):EBX[bit 3] = 1 (MTC Packet generation is 
supported), otherwise the MTCFreq field is reserved to 0.
Each bit position in this field represents 1 encoding value in the 4-bit 
MTCFreq field (ie, bit 0 is associated with encoding value 0). For each 
bit:
1: MTCFreq can be assigned the associated encoding value.0: MTCFreq cannot be assigned to the associated encoding value. A 
write to IA32_RTIT_CTLMTCFreq with  unsupported encoding will cause 
#GP fault.
EBX 15:0 Bitmap of supported Cycle 
Threshold valuesThe non-zero bits indicate the map of supported encoding values for 
the IA32_RTIT_CTL.CycThresh field. This applies only if CPUID.(EAX=14H, ECX=0):EBX[bit 1]  = 1 (Cycle-Accurate Mode is 
Supported), otherwise the CycThresh field is reserved to 0. See Section 
33.2.8.
CycThresh field (ie, bit 0 is associated with encoding value 0). For each 
bit:
1: CycThresh can be assigned the associated encoding value.
0: CycThresh cannot be assigned to the associated encoding value. A 
write to CycThresh with unsupported encoding will cause #GP fault.
31:16 Bitmap of supported 
Configurable PSB Frequency encodingThe non-zero bits indicate the map of supported encoding values for

#GP fault.
33.2.8.
bit:
Configurable PSB Frequency encodingThe non-zero bits indicate the map of supported encoding values for 
the IA32_RTIT_CTL. PSBFreq field. This applies only if 
CPUID.(EAX=14H, ECX=0):EBX[bit 1] = 1 (Configurable PSB is 
supported), otherwise the PSBFreq  field is reserved to 0. See Section 
33.2.8.
PSBFreq  field (ie, bit 0 is associated with encoding value 0). For each 
bit:
1: PSBFreq  can be assigned the associated encoding value.
0: PSBFreq  cannot be assigned to the associated encoding value. A 
write to PSBFreq  with unsupported encoding will cause #GP fault.
ECX 31:0 Reserved
EDX 31:0 Reserved33-30 Vol. 3CINTEL® PROCESSOR TRACE
33.3.1.1  Packet Decoding of RIP versus LIP
FUP, TIP, TIP.PGE, and TIP.PGE packets can contain an in struction pointer (IP) payload. On some processor gener-
ations, this payload will be an effective address (RIP), whil e on others this will be a linear address (LIP). In the 
former case, the payload is the offset from the current CS ba se address, while in the latter it is the sum of the offset 
and the CS base address (Note that in real mode, the CS base address is the value of CS<<4, while in protected 
mode the CS base address is the base linear address of th e segment indicated by the CS register.). Which IP type 
is in use is indicated by enumeration (see CPUID.(EAX=14H, ECX=0):ECX.LIP[bit 31] in Table 33-11).
For software that executes while the CS base address is 0 (including all software executing in 64-bit mode), the 
difference is indistinguishable. A trace decoder must acco unt for cases where the CS base address is not 0 and the 
resolved LIP will not be evident in a trace generated on a CPU that enumerates use of RIP. This is likely to cause 
problems when attempting to link the trace with the associated binaries.
Note that IP comparison logic, for IP filtering and TraceS top range calculation, is based on the same IP type as 
these IP packets. For processors that output RIP, the IP comparison mechanism is also based on RIP, and hence on 
those processors RIP values should be written to IA32_RTIT_ADDRn_[AB] MSRs. This can produce differing 
behavior if the same trace configuration setting is ru n on processors reporting different IP types, i.e., 
CPUID.(EAX=14H, ECX=0):ECX.LIP[bit 31]. Care should be  taken to check CPUID when configuring IP filters.
33.3.1.2  Model Specific  Capability Restrictions
Some processor generations impose restrictions that prevent use of LBRs/BTS/BTM/LERs when software has 
enabled tracing with Intel Processor Trace. On these proce ssors, when TraceEn is set, updates of LBR, BTS, BTM, 
LERs are suspended but the states of the corresponding IA32_DEBUGCTL control fields remained unchanged as if 
it were still enabled. When TraceEn is cleared, the LBR array is reset, and LBR/BTS/BTM/LERs updates will resume. 
Further, reads of these registers will re turn 0, and writes will be dropped.
The list of MSRs whose updates/accesses are restricted follows.
•MSR_LASTBRANCH_x_TO_IP, MSR_LASTBRANCH_x_FROM_IP, MSR_LBR_INFO_x, MSR_LASTBRANCH_TOS
•MSR_LER_FROM_LIP, MSR_LER_TO_LIP
•MSR_LBR_SELECT
For processors with CPUID DisplayFamily_DisplayModel signatures of 06_3DH, 06_47H, 06_4EH, 06_4FH, 06_56H, 
and 06_5EH, the use of Intel PT and LBRs are mutually exclusive.
33.3.2 Enabling and Configuration of Trace Packet Generation
To configure trace packets, enable packet generation, and capture packets, software starts with using CPUID 
instruction to detect its feature flag, CPUID.(EAX=07H,E CX=0H):EBX[bit 25] = 1; followed by enumerating the 
capabilities described in Section 33.3.1. 
Based on the capability queried from Section 33.3.1, softwa re must configure a number of  model-specific registers. 
This section describes programming considerations related to those MSRs.
33.3.2.1  Enabling  Packet Generation
When configuring and enabling packet generation, the IA 32_RTIT_CTL MSR should be written after any other Intel 
PT MSRs have been written, since writes to the other co nfiguration MSRs cause a general-protection fault (#GP) if 
TraceEn = 1. If a prior trace collection context is not being restored, then software should first clear 
IA32_RTIT_STATUS. This is important since the Stopped, and Error fields are writable; clearing the MSR clears any 
values that may have persisted from prior trace packet collection contexts. See Section 33.2.8.2 for details of 
packets generated by setting TraceEn to 1.
If setting TraceEn to 1 causes an operational error (see  Section 33.3.10), there may be a delay after the WRMSR 
completes before the error is signaled in the IA32_RTIT_STATUS MSR.
While packet generation is enabled, the values of some configuration MSRs (e.g., IA32_RTIT_STATUS and 
IA32_RTIT_OUTPUT_*) are transient, and reads may return va lues that are out of date. Only after packet genera-
tion is disabled (by clearing TraceEn) do reads of these MSRs return reliable values.Vol. 3C 33-31INTEL® PROCESSOR TRACE
33.3.2.2  Disabling Packet Generation
After disabling packet generation by clearing IA32_RTIT_CT L, it is advisable to read the IA32_RTIT_STATUS MSR 
(Section 33.2.8.4):
•If the Error bit is set, an operational error was encounte red, and the trace is most likely compromised. Software 
should check the source of the error (by examining the ou tput MSR values), correct the source of the problem, 
and then attempt to gather the trace again. For details  on operational errors, see Section 33.3.10. Software 
should clear IA32_RTIT_STATUS.Error before re-enabling packet generation. 
•If the Stopped bit is set, software execution encounter ed an IP TraceStop (see Section 33.2.5.3) or the ToPA 
Stop condition (see “ToPA STOP” in Section 33.2 .7.2) before packet generation was disabled.
33.3.3 Flushing Trace Output
Packets are first buffered internally and then written out asynchronously. To collect packet output for post-
processing, a collector needs first to ensure that all pack et data has been flushed from internal buffers. Software 
can ensure this by stopping packet generation by clea ring IA32_RTIT_CTL.TraceEn (see “Disabling Packet Genera-
tion” in Section 33.2.8.2).
When software clears IA32_RTIT_CTL.TraceEn to flush out in ternally buffered packets, the logical processor issues 
an SFENCE operation which ensures that WC trace output st ores will be ordered with respect to the next store, or 
serializing operation. A subsequent re ad from the same logical processor will see the flushed trace data, while a 
read from another logical processor should  be preceded by a store, fence, or architecturally serializing operation on 
the tracing logical processor.
When the flush operations complete, the IA32_RTIT_OUTP UT_* MSR values indicate where the trace ended. While 
TraceEn is set, these MSRs may hold stale values. Further, if a ToPA region with INT=1 is filled, meaning a ToPA PMI 
has been triggered, IA32_PERF_GLOBAL_STATUS.Trace_ToPA_P MI[55] will be set by the time the flush completes.
33.3.4 Warm Reset
The MSRs software uses to program Intel Processor Trace are cleared after a power-on RESET (or cold RESET). On 
a warm RESET, the contents of those MSRs can retain thei r values from before the warm RESET with the exception 
that IA32_RTIT_CTL.TraceEn will be cleared (which may have the side effect of clearing some bits in 
IA32_RTIT_STATUS). 
33.3.5 Context Switch Consideration
To facilitate construction of instruction execution traces at the granularity of a software process or thread context, 
software can save and restore the states of the trace configuration MSRs across the process or thread context 
switch boundary. The principle is the same as saving and restoring the typical architectural processor states across 
context switches. 
33.3.5.1  Manual Trace Co nfiguration Context Switch
The configuration can be saved and restored through a se quence of instructions of RDMSR, management of MSR 
content and WRMSR. To stop tracing and to ensure that al l configuration MSRs contain stable values, software must 
clear IA32_RTIT_CTL.TraceEn before reading any other trace configuration MSRs. The recommended method for 
saving trace configuration context manually follows:
1. RDMSR IA32_RTIT_CTL, save value to memory 
2. WRMSR IA32_RTIT_CTL with saved value from RDMSR above and TraceEn cleared3. RDMSR all other configuration MSRs whose values ha d changed from previous saved value, save changed 
values to memory33-32 Vol. 3CINTEL® PROCESSOR TRACE
When restoring the trace configuration contex t, IA32_RTIT_CTL should be restored last:
1. Read saved configuration MSR values, aside from IA32_RTIT_CTL, from memory, and restore them with 
WRMSR 
2. Read saved IA32_RTIT_CTL value from memory, and restore with WRMSR.
33.3.5.2  Trace Configuration Co ntext Switch Using XSAVES/XRSTORS
On processors whose XSAVE feature set supports XSAVES and XRSTORS, the Trace configuration state can be 
saved using XSAVES and restored by XRSTORS, in conjunction with the bit field associated with supervisory state 
component in IA32_XSS. See Chapter 13, “Managing State Using the XSAVE Feature Set‚” of Intel® 64 and IA-32

WRMSR 
component in IA32_XSS. See Chapter 13, “Managing State Using the XSAVE Feature Set‚” of Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 1.
33.3.6 Cycle-Accurate Mode 
Intel PT can be run in a cycle-accurate mode which enables CYC packets (see Section 33.4.2.14) that provide low-
level information in the processor core clock domain. This cycle counter data in CYC packets can be used to 
compute IPC (Instructions Per Cycle), or to track wall-clock time on a fine-grain level.
To enable cycle-accurate mode packet generation, so ftware should set IA32_RTIT _CTL.CYCEn=1. It is recom-
mended that software also set TSCEn=1 anytime cycle-accura te mode is in use. With this, all CYC-eligible packets 
will be preceded by a CYC packet, the payload of which indi cates the number of core clock cycles since the last CYC 
packet. In cases where multiple CYC-eligible packets are generated in a single cycle, only a single CYC will be 
generated before the CYC-eligible packets, otherwise each CY C-eligible packet will be preceded by its own CYC. The 
CYC-eligible packets are:
•TNT, TIP, TIP.PGE, TIP.PGD, MODE.EXEC, MODE.TSX, PIP, VMCS, OVF, MTC, TSC, PTWRITE, EXSTOP
TSC packets are generated when there is insufficient information to reconstruct wall-clock time, due to tracing 
being disabled (TriggerEn=0), or power down scenarios like a transition to a deep-sleep MWAIT C-state. In this 
case, the CYC that is generated along with the TSC will indicate the number of cycles actively tracing (those 
powered up, with TriggerEn=1) executed between the last  CYC packet and the TSC packet. And hence the amount 
of time spent while tracing is inactive can be inferred from  the difference in time between that expected based on 
the CYC value, and the actual time indicated by the TSC.
Additional CYC packets may be sent stand-alone, so that the processor can ensure that the decoder is aware of the 
number of cycles that have passed before the internal hardware counter wraps, or is reset due to other micro-
architectural condition. There is no guarantee at what intervals these standalone CYC packets will be sent, except 
that they will be sent before the wrap occurs. An illustration is given below.
Example 33-1.  An Illust rative CYC Packet Example
Time (cycles) Instruction Snapshot Generated Packets Comment
x call %eax CYC(?), TIP ?Elapsed cycles from the previous CYC unknown
x + 2 call %ebx CYC(2), TIP 1 byte CYC packet; 2 cycles elapsed from the previous CYCx + 8 jnz Foo (not taken) CYC(6) 1 byte CYC packet
x + 9 ret (compressed)
x + 12 jnz Bar (taken)x + 16 ret (uncompressed) TNT, CYC(8), TIP 1 byte CYC packet
x + 4111 CYC(4095) 2 byte CYC packet
x + 12305 CYC(8194) 3 byte CYC packetx + 16332 mov cr3, %ebx CYC(4027), PIP 2 byte CYC packetVol. 3C 33-33INTEL® PROCESSOR TRACE
33.3.6.1  Cycle Counter
The cycle counter is implemented in hardware (independent  of the time stamp counter or performance monitoring 
counters), and is a simple incrementing counter that does  not saturate, but rather wraps. The size of the counter 
is implementation specific.
The cycle counter is reset to zero any time that TriggerEn is cleared, and when a CYC packet is sent. The cycle 
counter will continue to count when ContextEn or FilterEn are cleared, and cycle packets will still be generated. It will not count during sleep states that result in Intel PT  logic being powered-down, bu t will count up to the point 
where clocks are disabled, and resume counting once they are re-enabled.
33.3.6.2  Cycle Packet Semantics
Cycle-accurate mode adheres to the following protocol:
•All packets that precede a CYC packet represent instruct ions or events that took place before the CYC time. 
•All packets that follow a CYC packet represent instructions or events that took place at the same time as, or 
after, the CYC time. 
•The CYC-eligible packet that immediately follows a CYC packet represents an instruction or event that took 
place at the same time as the CYC time.
These items above give the decoder a means to apply CYC pa ckets to a specific instruction in the assembly stream. 
Most packets represent a single instruction or event, and hence the CYC packet that precedes each of those 
packets represents the retirement time of that instruction or  event. In the case of TNT packets, up to 6 conditional 
branches and/or compressed RETs may be contained in the packet. In this case, the preceding CYC packet provides 
the retirement time of the first branch in the packet. It is  possible that multiple branches retired in the same cycle 
as that first branch in the TNT, but the protocol will not make that obvious. Also note that a MTC packet could be 
generated in the same cycle as the first JCC in the TNT packet. In this case, the CYC would precede both the MTC 
and the TNT, and apply to both.
Note that there are times when the cycle counter will stop  counting, though cycle-accurate mode is enabled. After 
any such scenario, a CYC packet followed by TSC packet will be sent. See Section 33.8.3.2 to understand how to interpret the payload values
Multi-packet Instructions or Events
Some operations, such as interrupts or task switches, ge nerate multiple packets. In these cases, multiple CYC 
packets may be sent for the operation, preceding each CYC- eligible packet in the operation. An example, using a 
task switch on a software interrupt, is shown below.
33.3.6.3  Cycle Thresholds
Software can opt to reduce the frequency of cycle packet s, a trade-off to save bandwidth and intrusion at the 
expense of precision. This is done by utilizing a cycle threshold (see Section 33.2.8.2).
IA32_RTIT_CTL.CycThresh indicates to the processor the minimum number of cycles that must pass before the 
next CYC packet should be sent. If this value is 0, no th reshold is used, and CYC packets can be sent every cycle in 
which a CYC-eligible packet is generated. If this value is greater than 0, the hardware will wait until the associated Example 33-2.  An Example of CYC in th e Presence of Multi-Packet Operations
Time (cycles) Instruction Snapshot Generated Packets
x jnz Foo (not taken) CYC(?)
x + 2 ret (compressed)x + 8 jnz Bar (taken)
x + 9 jmp %eax TNT, CYC(9), TIP
x + 12 jnz Bar (not taken) CYC(3)x + 32 int3 (task gate) TNT, FUP, CYC( 10), PIP, CYC(20), MODE.Exec, TIP33-34 Vol. 3CINTEL® PROCESSOR TRACE
number of cycles have passed since the last CYC packet before sending another. CPUID provides the threshold 
options for CycThresh, see Section 33.3.1.
Note that the cycle threshold does not dictate how frequent ly a CYC packet will be posted, it merely assigns the 
maximum frequency. If the cycle threshold is 16, a CYC pa cket can be posted no more frequently than every 16 
cycles. However, once that threshold of 16 cycles has passed, it still requires a new CYC-eligible packet to be gener-
ated before a CYC will be inserted. Table 33-13 illustrates the threshold behavior.
33.3.7 Decoder Synchronization (PSB+)
The PSB packet (Section 33.4.2.17) serves as a synchronizat ion point for a trace-packet decoder. It is a pattern in 
the trace log for which the decoder can quickly scan to a lign packet boundaries. No legal packet combination can 
result in such a byte sequence. As such, it serves as th e starting point for packet decode. To decode a trace log 
properly, the decoder needs more than simply to be alig ned: it needs to know some state and potentially some 
timing information as well. The decoder should never need  to retain any information (e.g., LastIP, call stack, 
compound packet event) across a PSB; all compound pack et events will be completed before a PSB, and any 
compression state will be reset.
When a PSB packet is generated, it is followed by a PS BEND packet (Section 33.4.2.18). One or more packets may 
be generated in between those two pack ets, and these inform the decoder of the current state of the processor. 
These packets, known collectively as PSB+, should be inte rpreted as “status only”, since they do not imply any 
change of state at the time of the PSB, nor are they asso ciated directly with any instruction or event. Thus, the 
normal binding and ordering rules that apply to these pa ckets outside of PSB+ can be ignored when these packets 
are between a PSB and PSBEND. They inform the decoder of  the state of the processor at the time of the PSB.
PSB+ can include:
•Timestamp (TSC), if IA32_RTIT_CTL.TSCEn=1. 
•Timestamp-MTC Align (TMA), if IA32_RTI T_CTL.TSCEn=1 && IA32_RTIT_CTL.MTCEn=1.
•Paging Information Packet (PIP), if ContextEn=1 and IA 32_RTIT_CTL.OS=1. The non-root bit (NR) is set if the 
logical processor is in VMX non-root operation and th e “conceal VMX from PT” VM-execution control is 0.
•VMCS packet, if either the logical is in VMX root operation or the logical processor is in VMX non-root operation 
and the “conceal VMX from PT” VM-execution control is 0.
•Core Bus Ratio (CBR).
•MODE.TSX, if ContextEn=1 and BranchEn = 1. 
•MODE.Exec, if PacketEn=1. 
•Flow Update Packet (FUP), if PacketEn=1.

PSB is generated only when TriggerEn=1; hence PSB+ has the same dependencies. The ordering of packets within 
PSB+ is not fixed. Timing packets such as CYC and MTC may be generated between PSB and PSBEND, and their 
meanings are the same as outside PSB+.Table 33-13. An Illustrative CYC Packet Example
Time (cycles) Instruction SnapshotThreshold
0 1 63 26 4
x jmp %eax CYC, TIP CYC , TIP CYC, TIP CYC, TIP
x + 9 call %ebx CYC, TIP TIP TIP TIP
x + 15 call %ecx CYC, TIP TIP TIP TIP
x + 30 jmp %edx CYC, TIP CYC, TIP TIP TIPx + 38 mov cr3, %eax CYC, PIP PIP CYC, PIP PIPx + 46 jmp [%eax] CYC, TIP CYC, TIP TIP TIP
x + 64 call %edx CYC, TIP CYC, TIP TIP CYC,TIP
x + 71 jmp %edx CYC, TIP TIP CYC,TIP TIPVol. 3C 33-35INTEL® PROCESSOR TRACE
A PSB+ can be lost in some scenarios. If IA32_RTIT_STA TUS.TriggerEn is cleared just as the PSB threshold is 
reached, e.g., due to TraceEn being cleared, the PSB+ may not be generated. On processors that support PSB 
preservation (CPUID.(EAX=14H, ECX=0):EBX[bit 6] = 1), setting IA32_RTIT_CTL.InjectPsbPmiOnEnable[56] = 1 
will ensure that a PSB+ that is pending at the ti me PT is disabled will be recorded by setting 
IA32_RTIT_STATUS.PendPSB[6] = 1. A PSB will be inserted , and PendPSB cleared, when PT is later re-enabled 
while PendPSB = 1.
Note that an overflow can occur during PSB+, and this co uld cause the PSBEND packet to be lost. For this reason, 
the OVF packet should also be viewed as terminating PSB+ . If IA32_RTIT_STATUS.TriggerEn is cleared just as the 
PSB threshold is reached, the PSB+ may not be generate d. TriggerEn can be cleared by a WRMSR that clears 
IA32_RTIT_CTL.TraceEn, a VM exit that clears IA32_RTI T_CTL.TraceEn, an #SMI, or any time that either 
IA32_RTIT_STATUS.Stopped is set (e.g., by a TraceStop or ToPA stop condition) or IA32_RTIT_STATUS.Error is set 
(e.g., by an Intel PT output error). On processo rs that support PSB pres ervation (CPUID.(EAX=14H, 
ECX=0):EBX[bit 6] = 1), setting IA32_RTIT_CTL.InjectPs bPmiOnEnable[56] = 1 will ensure that a PSB+ that is 
pending at the time PT is disabled will be recorded by  setting IA32_RTIT_STATUS.PendPSB[6] = 1. A PSB will then 
be pended when the saved PT context is later restored.
33.3.8 Internal Buffer Overflow
In the rare circumstances when new packets need to be generated but the processor’s dedicated internal buffers 
are all full, an “internal buffer overflow” occurs. On such an overflow packet generation ceases (as packets would need to enter the processor’s internal buffer) until th e overflow resolves. Once resolved, packet generation 
resumes.
When the buffer overflow is cleared, an OVF packet (Sec tion 33.4.2.16) is generated, and the processor ensures 
that packets which follow the OVF are not compressed (IP compression or RET compression) against packets that were lost. 
If IA32_RTIT_CTL.BranchEn = 1, the OVF packet will be fo llowed by a FUP if the overflow resolves while Pack-
etEn=1. If the overflow resolves while PacketEn = 0 no pa cket is generated, but a TIP.PGE will naturally be gener-
ated later, once PacketEn = 1. The payload of the FUP or TI P.PGE will be the Current IP of the first instruction upon 
which tracing resumes after the overflow is cleared. If th e overflow resolves while PacketEn=1, only timing packets 
may come between the OVF and the FUP. If the overflow resolves while PacketEn=0, any other packets that are not 
dependent on PacketEn may come between the OVF and the TIP.PGE. 
33.3.8.1  Overflow Impact on Enables
The address comparisons to ADDRn ranges, for IP filtering and TraceStop (Section 33.2.5.3), continue during a buffer overflow, and TriggerEn, ContextEn, and FilterEn may change during a buffer overflow. Like other packets, however, any TIP.PGE or TIP.PGD packets that woul d have been generated will be lost. Further, 
IA32_RTIT_STATUS.PacketByteCnt will not increment, sinc e it is only incremented when packets are generated.
If a TraceStop event occurs during the buffer overflow , IA32_RTIT_STATUS.Stopped will still be set, tracing will 
cease as a result. However, the TraceStop packet, and any TIP.PGD that result from the TraceStop, may be dropped.
33.3.8.2  Overflow Impact on Timing Packets
Any timing packets that are generated during a buffer ov erflow will be dropped. If only a few MTC packets are 
dropped, a decoder should be able to detect this by noti cing that the time value in the first MTC packet after the 
buffer overflow incremented by more th an one. If the buffer overflow lasted  long enough that 256 MTC packets are 
lost (and thus the MTC packet ‘wraps’ its 8-bit CTC value) , then the decoder may be unable to properly understand 
the trace. This is not an expected scenario. No CYC packets are generated during overflow, even if the cycle counter 
wraps.
Note that, if cycle-accurate mode is enabled, the OVF pa cket will generate a CYC packet. Because the cycle counter 
counts during overflows, this CYC packet can provide the du ration of the overflow. However, there is a risk that the 
cycle counter wrapped during the overflow, which could render this CYC misleading.33-36 Vol. 3CINTEL® PROCESSOR TRACE
33.3.9 TNT Disable
Software can opt to omit TNT packets from control flow  trace (BranchEn=1) by setting IA32_RTIT_CTL.DisTNT[bit 
55]. This can dramatically reduce trace size. Results will va ry by workload, but trace size reductions of 40-75% are 
typical, which will have a corresponding reduction in performance overhead and memory bandwidth consumption 
from Intel PT. However, omitting TNT packets means the deco der is not able to follow the full control flow trace, 
since conditional branch and compressed RET results won't be known. Thus, TNT Disable should be employed only 
for usages that do not depend on full control flow trace.
NOTE
To avoid loss of RET results with TNT Disable, software may wish to disable RET compression by setting IA32_RTIT_CT L.DisRETC[bit 11].
33.3.10 Operational Errors
Errors are detected as a result of packet output config uration problems, which can include output alignment issues, 
ToPA reserved bit violations, or overlapping packet outp ut with restricted memory. See “ToPA Errors” in Section 
33.2.7.2 for details on ToPA errors, and Section 33.2.7.4 for details on restricted memory errors. Operational errors 
are only detected and signaled when TraceEn=1.
When an operational error is detected, tracing is  disabled and the error is logged. Specifically, 
IA32_RTIT_STATUS.Error is set, which will cause IA32_RTIT_STATUS.TriggerEn to be 0. This will disable generation 
of all packets. Some causes of operational e rrors may lead to packet bytes being dropped.
It should be noted that the timing of error detection may not be predictable. Errors are signaled when the processor 
encounters the problematic configuration. This could be as soon as packet generation is enabled but could also be later when the problematic entry or field needs to be used. 
Once an error is signaled, software should disable packet generation by clearing TraceEn, diagnose and fix the error 
condition, and clear IA32_RTIT_STATUS.Error. At th is point, packet generation can be re-enabled.
33.4 TRACE PACKETS AND DATA TYPES
This section details the data packets gene rated by Intel Processor Trace. It is useful for developers writing the inter-
pretation code that will decode the data pack ets and apply it to the traced source code.
33.4.1 Packet Relationships and Ordering
This section introduces the concept of packet “binding”, which involves determining the IP in a binary disassembly 
at which the change indicated by a given packet applies. Some packets have the associated IP as the payload (FUP, 
TIP), while for others the decoder need only search for the next instance of a particular  instruction (or instructions) 
to bind the packet (TNT). However, in many cases, th e decoder will need to consider the relationship between 
packets, and to use this packet context to determine how to bind the packet.
Section 33.4.1.1 below provides detailed descriptions of the packets, including how packets bind to IPs in the disas-
sembly, to other packets, or to nothing at all. Many pa ckets listed are simple to bind, because they are generated 
in only a few scenarios. Those that require more consideration are typically part of “compound packet events”, such 
as interrupts, exceptions, and some instructions, where multiple packets are generated by a single operation 
(instruction or event). These compound packet events freq uently begin with a FUP to indicate the source address 
(if it is not clear from the disassembly), and are concluded by a TIP or TIP.PGD packet that indicates the destination 
address (if one is provided). In this scenario, the FUP is said to be “coupled” with the TIP packet.
Other packets could be in between the coupled FUP and TIP packet. Timing packets, such as TSC, MTC, CYC, or 
CBR, could arrive at any time, and hence could intercede in  a compound packet event. If an operation changes CR3

CBR, could arrive at any time, and hence could intercede in  a compound packet event. If an operation changes CR3 
or the processor’s mode of execution, a state update packet (i.e., PIP or MODE) is generated. The state changes 
indicated by these intermediate packets should be applie d at the IP of the TIP* packet. A summary of compound 
packet events is provided in Table 33-14; see Section 33. 4.1.1 for more per-packet details and Section 33.7 for 
more detailed packet generation examples.Vol. 3C 33-37INTEL® PROCESSOR TRACE
33.4.1.1  Packet Blocks
Packet blocks are a means to dump one or more groups of state values. Packet bloc ks begin with a Block Begin 
Packet (BBP), which indicates what type of state is held within the block. Following each BBP there may be one or 
more Block Item Packets (BIPs), which contain the state values. The block is terminated by either a Block End 
Packet (BEP) or another BBP indicating the start of a new block.
The BIP packet includes an ID value that, when combined  with the Type field from the BBP that preceded it, 
uniquely identifies the state value held in the BIP payload. The size of each BIP packet payload is provided by the 
Size field in the preceding BBP packet.
Each block type can have up to 32 items defined for it. There is no guarantee, however, that each block of that type 
will hold all 32 items. For more details on which items to  expect, see documentation on the specific block type of 
interest.
See the BBP packet description (Section 33.4.2.26) for details on packet block generation scenarios.Packet blocks are entirely generated within an instruct ion or between instructions, which dictates the types of 
packets (aside from BIPs) that may be seen within a packet  block. Packets that indicate control flow changes, or 
other indication of instruction completion, cannot be gene rated within a block. These are listed in the following 
table. Other packets, including timing packets, may occur between BBP and BEP.
It is possible to encounter an internal buffer overflow in the middle of a block. In such a case, it is guaranteed that 
packet generation will not resume in the middle of a bloc k, and hence the OVF packet terminates the current block. 
Depending on the duration of the overflow , subsequent blocks may also be lost.
Decoder Implications
When a Block Begin Packet (BBP) is encountered, the deco der will need to decode some packets within the block 
differently from those outside a block. The Block Item Pa cket (BIP) header byte has the same encoding as a TNT 
packet outside of a block, but must be treated as a BIP header (with following payload) within one.
When an OVF packet is encountered, the decoder should tr eat that as a block ending condition. Packet generation 
will not resume within a block.Table 33-14. Compound  Packet Event Summary
Event Type Beginning Middle End Comment
Unconditional, 
uncompressed 
control-flow 
transferFUP or none Any combination 
of PIP, VMCS, MODE.Exec, or 
noneTIP or TIP.PGD FUP only for asynchronous events. Order of middle packets 
may vary. 
PIP/VMCS/MODE only if the operation modifies the state 
tracked by these respective packets.
TSX Update MODE.TSX, and 
(FUP or none)None TIP, TIP.PGD, or 
noneFUP
TIP/TIP.PGD only for TSX abort cases.
Overflow OVF  PSB, PSBEND, or 
noneFUP or TIP.PGE FUP if overflow reso lves while ContextEn =1, else TIP.PGE.
Table 33-15. Packets Forbidden Between BBP and BEP
TNT
TIP, TIP.PGE, TIP.PGD
MODE.Exec, MODE.TSX
PIP, VMCS
TraceStop
PSB, PSBEND
PTW
MWAIT33-38 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2 Packet Definitions
The following description of packet definitions are in ta bular format. Figure 33-3 explains how to interpret them. 
Packet bits listed as “RSVD” are not guaranteed to be 0.
Figure 33-3.  Interpreting Tabular Definition of Packet FormatName Packet name
Packet Format
Description of fields
Dependencies Depends on packet generation con-
figuration enable controls or other 
bits (Section 33.2.6).Generation Scenario Which instructions, events, or other 
scenarios can cause this packet to be 
Description Description of the packet, including the purpose it serves, meaning of the information or payload, etc
Application How a decoder should apply this packet. It may bind to a specific instruction from the binary, or to 
another packet in the stream, or have other implications on decode7 6 5 4 3 2 1 0
0 0 1 0 1 0 1 0 1
1 1 1 0 0 0 1 1 0
201000110Byte Number Payload in WhiteHeader bits
in GreenBit NumberVol. 3C 33-39INTEL® PROCESSOR TRACE
33.4.2.1  Taken/Not-taken (TNT) Packet
Table 33-16. TNT Packet Definition
Name Taken/Not-taken (TNT) Packet
B1…BN represent the last N conditional br anch or compressed RET (Section 33.4.2.2 ) results, such th at B1 is oldest 
and BN is youngest. The short TNT packet can contain from  1 to 6 TNT bits. The long TNT packet can contain from 
1 to 47 TNT bits.
Irrespective of how many TNT bi ts is in a packet, the last valid TNT bit is followed by a trailing 1, or Stop bit, as 
shown above. If the TNT packet is not full (fewer than 6 TN T bits for the Short TNT, or fewer than 47 TNT bits for 
the Long TNT), the Stop bit moves up, and the trailing bits of the packet are filled with 0s. Examples of these
“partial TNTs” are shown below. An  implementation may choose to use long TNTs, short TNTs, or both.
Dependencies PacketEn && 
~IA32_RTIT_CTL.DisTNTGeneration ScenarioOn a conditional branch or compre ssed RET, if it fills the TNT. 
Also, partial TNTs may be generated at any time, as a result of other packets being generated, or certain micro-architectural 
conditions occurring, before the TNT is full.7 6 5 4 3 2 1 0
01B1 B2 B3 B4 B5 B6 0S h o r t  T N T
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0L o n g  T N T
1 1 0 1 0 0 0 1 1
2B40 B41 B42 B43 B44 B45 B46 B47
3B32 B33 B34 B35 B36 B37 B38 B39
4B24 B25 B26 B27 B28 B29 B30 B31
5B16 B17 B18 B19 B20 B21 B22 B23
6B8 B9 B10 B11 B12 B13 B14 B15
71B1 B2 B3 B4 B5 B6 B7
7 6 5 4 3 2 1 0
0001B1 B2 B3 B4 0 Short TNT
7 6 5 4 3 2 1 0
1 1 0 1 0 0 0 1 1
2B24 B25 B26 B27 B28 B29 B30 B31
3B16 B17 B18 B19 B20 B21 B22 B23
4B8 B9 B10 B11 B12 B13 B14 B15
51B1 B2 B3 B4 B5 B6 B7
600000000
70000000033-40 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.2  Target IP (TIP) Packet
IP Compression
The IP payload in a TIP. FUP, TIP.PGE, or TIP.PGD packet can vary in size, based on the mode of execution, and the 
use of IP compression. IP compression is an optional compression technique the processor may choose to employ 
to reduce bandwidth. With IP compression, the IP to be repr esented in the payload is compared with the last IP sent 
out, via any of FUP, TIP, TIP.PGE, or TIP.PGD. If that previous IP had the same upper (most significant) address 
bytes, those matching bytes may be suppressed in the curre nt packet. The processor maintains an internal state of 
the “Last IP” that was encoded in trace packets, thus the de coder will need to keep track of the “Last IP” state in Description Provides the taken/not-taken resu lts for the last 1..6 (Short TNT) or 1. .47 (Long TNT) conditional branches (Jcc, 
J*CXZ, or LOOP) or compressed RETs (Section 33.4.2.2).  The TNT payload bits should be interpreted as follows:
• 1 indicates a taken conditiona l branch, or a compressed RET
• 0 indicates a not-taken conditional branch
TNT payload bits are stored internal to the processor in a TNT buffer, until either the buffer is filled or another 
packet is to be generated. In either case a TNT packet ho lding the buffered bits will be emitted, and the TNT buffer 
will be marked as empty.
Application Each valid payload bit (that is, bits between the header  bits and the trailing Stop bi t) applies to an upcoming cond i-
tional branch or RET instruct ion. Once a decoder consumes a TNT packet with N valid payload bits, these bits should 
be applied to (and hence provide the destination for) the next N conditional branches or RETs.
Table 33-17. IP Packet Definition
Name Target IP (TIP) Packet
Dependencies PacketEn Generation Sce-narioIndirect branch (including un-compressed RET), far branch, interrupt, 
exception, INIT, SIPI, VM exit, VM entr y, TSX abort, EENTER, EEXIT, ERE-
SUME, AEX
1.
NOTES:
1. EENTER, EEXIT, ERESUME, AEX would be possible only for a debug enclave.Description Provides the target fo r some control flow transfers
Application Anytime a TIP is encountered, it indicates that control was transferred to the IP provided in the payload.
The source of this control fl ow change, and hence the IP or instruction to which it binds, depends on the packets 
that precede the TIP. If a TIP is encountered and all preceding packets have already been bound, then the TIP will 
apply to the upcoming indire ct branch, far branch, or VMRESUME. However, if there was a preceding FUP that 
remains unbound, it will bind to the TIP. Here, the TIP pr ovides the target of an asyn chronous event or TSX abort 
that occurred at the IP given in the FUP payload. Note that there may be other packets, in addition to the FUP, which

SUME, AEX
1.
NOTES:
that occurred at the IP given in the FUP payload. Note that there may be other packets, in addition to the FUP, which 
will bind to the TIP packet. See the packet application descriptions for other packets for details.Table 33-16. TNT Packet Definition (Contd.)
7 6 5 4 3 2 1 0
0I P B y t e s 0 1 1 0 1
1 TargetIP[7:0]
2 TargetIP[15:8]
3 TargetIP[23:16]
4 TargetIP[31:24]
5 TargetIP[39:32]
6 TargetIP[47:40]
7 TargetIP[55:48]
8 TargetIP[63:56]Vol. 3C 33-41INTEL® PROCESSOR TRACE
software, to match fidelity with packets generated by hardware . “Last IP” is initialized to zero, hence if the first IP 
in the trace may be compressed if the upper bytes are zeroes.
The “IPBytes” field of the IP packets (FUP, TIP, TIP.PGE, TI P.PGD) serves to indicate how many bytes of payload are 
provided, and how the decoder should fi ll in any suppressed bytes. The algori thm for reconstructing the IP for a 
TIP/FUP packet is shown in the table below.
The processor-internal Last IP state is guaranteed to be re set to zero when a PSB is sent out. This means that the 
IP that follows the PSB with either be un-compressed (011b or 110b, see Table 33-18), or compressed against 
zero.
At times, “IPbytes” will have a value of 0. As shown above,  this does not mean that the IP payload matches the full 
address of the last IP, but rather that the IP for this pack et was suppressed. This is used for cases where the IP that 
applies to the packet is out of context. An example is th e TIP.PGD sent on a SYSCALL, when tracing only USR code. 
In that case, no TargetIP will be included in the packet , since that would expose an instruction point at CPL = 0. 
When the IP payload is suppressed in this manner, Last IP is not cleared, and instead refers to the last IP packet 
with a non-zero IPBytes field.
On processors that support a maximum linear address si ze of 32 bits, IP payloads may never exceed 32 bits 
(IPBytes <= 010b).
Indirect Transfer Compre ssion for Returns (RET)
In addition to IP compression, TIP packets for near return  (RET) instructions can also be compressed. If the RET 
target matches the next IP of the corresponding CALL, then the TIP pack et is unneeded, since the decoder can 
deduce the target IP by maintain ing a CALL/RET stack of its own.
When a RET is compressed, a Taken indication is adde d to the TNT buffer. Because the RET generates no TIP 
packet, it also does not update the internal Last IP value,  and thus the decoder should treat it the same way. If the 
RET is not compressed, it will generate a TIP packet  (just like when RET compression is disabled, via 
IA32_RTIT_CTL.DisRETC). 
A CALL/RET stack can be maintained by  the decoder by doing the following:
1. Allocate space to store 64 RET targets. 
2. For near CALLs, push the Next IP onto the stack. Once the stack is full, new CALLs will force the oldest entry off 
the end of the stack, such that only the youngest 64 en tries are stored. Note that this excludes zero-length 
CALLs, which are direct near CALLs with displacement ze ro (to the next IP). These CALLs typically don’t have 
matching RETs. 
3. For near RETs, pop the top (youngest) entry off the st ack. This will be the expected target of the RET.
In cases where a RET is compressed, the RET target is guar anteed to match the expected target from 3) above. If 
the target is not compressed, a TIP packet will be gene rated with the RET target, which may differ from the 
expected target in some cases.Table 33-18. FUP/TIP IP Reconstruction
IPBytes Uncompressed IP Value
63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0
000b None, IP is out of context001b Last IP[63:16] IP Payload[15:0]
010b Last IP[63:32] IP Payload[31:0]
011b IP Payload[47] extended IP Payload[47:0]100b Last IP [63:48] IP Payload[47:0]101b Reserved
110b IP Payload[63:0]
111b Reserved33-42 Vol. 3CINTEL® PROCESSOR TRACE
The hardware ensures that packets read by the decoder wi ll always have seen the CALL that corresponds to any 
compressed RET. The processor will never compress a RET ac ross a PSB, a buffer overflow, or scenario where Pack-
etEn=0. This means that a RET whose corresponding CALL ex ecuted while PacketEn=0, or before the last PSB, etc., 
will not be compressed.
If the CALL/RET stack is manipulated or  corrupted by software, and thereby causes a RET to transfer control to a 
target that is inconsistent with the CALL/RET stack, th en the RET will not be compressed, and will produce a TIP 
packet. This can happen, for example, if software executes a PUSH instruction to push a target onto the stack, and 
a later RET uses this target.
For processors that employ deferred TIPs (Section 33.4. 2.3), an uncompressed RET will not be deferred, and hence 
will force out any accumulated TNTs or TIPs. This serves to  avoid ambiguity, and make clear to the decoder whether 
the near RET was compressed, and hence a bit in the in-p rogress TNT should be consumed, or uncompressed, in 
which case there will be no in-progress TNT and thus a TIP should be consumed.
Note that in the unlikely case that a RET executes in a different execution mode than the associated CALL, the 
decoder will need to model the same behavior with its CALL  stack. For instance, if a CALL executes in 64-bit mode, 
a 64-bit IP value will be pushed onto the software stack.  If the corresponding RET executes in 32-bit mode, then 
only the lower 32 target bits will be popped off of the st ack, which may mean that the RET does not go to the CALL’s 
Next IP. This is architecturally correct behavior, and this  RET could be compressed, thus the decoder should match 
this behavior.
33.4.2.3  Deferred TIPs
The processor may opt to defer sending out the TNT when TI Ps are generated. Thus, rather than sending a partial 
TNT followed by a TIP, both packets will be deferred while  the TNT accumulates more Jcc/RET results. Any number 
of TIP packets may be accumulated this way, such that only once the TNT is filled, or once another packet (e.g., FUP) is generated, the TNT will be sent , followed by all the deferred TIP packet s, and finally terminated by the other 
packet(s) that forced out the TNT and TIP packets. Generati on of many other packets (see list below) will force out 
the TNT and any accumulated TIP packets. This is an opti onal optimization in hardware to reduce the bandwidth 
consumption, and hence the performance impact, incurred by tracing.
Table 33-19. TNT Examples with Deferred TIPs
Code Flow Packets, Non-Deferred  TIPS Packets, Deferred TIPS
0x1000 cmp %rcx, 0
0x1004 jnz Foo // not-taken
0x1008 jmp %rdxTNT(0b0), TIP(0x1308)
0x1308 cmp %rcx, 1
0x130c jnz Bar // not-taken0x1310 cmp %rcx, 2
0x1314 jnz Baz // taken
0x1500 cmp %eax, 70x1504 jg Exit // not-taken
0x1508 jmp %r15TNT(0b010), TIP(0x1100)
0x1100 cmp %rbx, 1
0x1104 jg Start // not-taken
0x1108 add %rcx, %eax0x110c … //  an asynchronous Interrupt arrives
INThandler:
0xcc00 pop %rdxTNT(0b0), FUP(0x110c), 
TIP(0xcc00)
TNT(0b00100), TIP(0x1308), 
TIP(0x1100), FUP(0x110c), TIP(0xcc00)Vol. 3C 33-43INTEL® PROCESSOR TRACE
33.4.2.4  Packet Generati on Enable (TIP.PGE) Packet
Table 33-20. TIP.PGE Packet Definition
Name Target IP - Packet Generation Enable (TIP.PGE) Packet
Dependencies PacketEn  transitions to 1 Generation 
ScenarioAny branch instruction, control flow transfer, or MOV 
CR3 that sets PacketEn , a WRMSR that enables 
packet generation and sets PacketEn
Description Indicates that PacketEn ha s transitioned to 1. It provides the IP at which the tracing begins.
This can occur due to any of the enables that comprise Packet En transitioning from 0 to 1, as long as all the others 
are asserted. Examples:• TriggerEn: This is set on software write to set IA32_RTI T_CTL.TraceEn as long as th e Stopped and Error bits in 
IA32_RTIT_STATUS are clear. The IP payl oad will be the Next IP of the WRMSR.
• FilterEn: This is set when software jumps into the tracing region. This region is defined by enabling IP filtering in 
IA32_RTIT_CTL.ADDRn_CFG, and defining the range in IA32_RTIT_ADDRn_[AB], see. Section 33.2.5.3. The 
IP payload will be the target of the branch.
• ContextEn: This is set on a CPL change, a CR3 write or  any other means of changing ContextEn. The IP payload 
will be the Next IP of the in struction that changes context if it is not a branch, otherwise it will be the target of 
the branch.
Application TIP.PGE packets bind to the instruction at the IP given in the payload.7 6 5 4 3 2 1 0
0I P B y t e s 1 0 0 0 1
2T a r g e t I P [ 1 5 : 8 ]
8 TargetIP[63:56]33-44 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.5  Packet Generati on Disable (TIP.PGD) Packet
Table 33-21. TIP.PG D Packet Definition
Name Target IP - Packet Generation Disable (TIP.PGD) Packet
Dependencies PacketEn  transitions to 
0Generation ScenarioAny branch instruction, control flow  transfer, or MOV CR3 that clears 
PacketEn, a WRMSR that disables pack et generation and clears PacketEn
Description Indicates that PacketEn has tran sitioned to 0. It will incl ude the IP at which the trac ing ends, unless ContextEn= 0  or

Description Indicates that PacketEn has tran sitioned to 0. It will incl ude the IP at which the trac ing ends, unless ContextEn= 0  or 
TraceEn=0 at the conclusion of the inst ruction or event that cleared PacketEn.
PacketEn can be cleared due to any of the enables that comprise PacketEn transition ing from 1 to 0. Examples:
• TriggerEn: This is cleared on software write to clear IA32_RTIT_CTL.TraceEn, or when 
IA32_RTIT_STATUS.Stopped is set, or on  operational error. The IP payload will be suppressed in this case, and the 
“IPBytes” field will have the value 0.
• FilterEn: This is cleared when software jumps out of the tracing region. This region is defined by enabling IP 
filtering in IA32_RTIT_CTL.ADDRn_CFG, and defining the range in IA32_RTIT_ADDRn_[AB], see. Section 33.2.5.3. The IP payload will depend on the type of the branch. For conditional b ranches, the payload is suppressed 
(IPBytes = 0), and in this case the destination can be in ferred from the disassembly. For any other type of branch, 
the IP payload will be th e target of the branch.
• ContextEn: This can happen on a CPL change, a CR3 write or any other means of changing ContextEn. See 
Section 33.2.5.3  for details. In this case, when ContextEn is cleared, there will be no IP payload. The “IPBytes” 
field will have value 0.
Note that, in cases where a branch that would normally produce a TIP packet (i.e., far transfer, indirect branch, inter-
rupt, etc) or TNT update (conditional branch or compressed RT) causes PacketEn to transition from 1 to 0, the TIP or TNT bit will be replaced with TIP.PGD. The payload of the TIP.PGD will be the target of the branch, unless the result 
of the instruction causes Tra ceEn or ContextEn to be cleared (ie, SY SCALL when IA32_RTIT_CTL.OS=0, In the case 
where a conditional branch clears FilterEn and hence PacketEn, there will be no TNT bit for this branch, replaced instead by the TIP.PGD.
Application TIP.PGD can be produced by any branch instructions, as well as some non-branch instructions, that clear PacketEn. 
When produced by a branch, it replaces any TIP or TNT update that the branch would normally produce. 
In cases where there is an unbound FUP preceding the TIP.PGD, then the TIP.PGD is part of compound operation (i.e., 
asynchronous event or TSX abort) which cleared PacketEn. For most such cases, the TIP.PGD is simply replacing a 
TIP, and should be treated the same way. The TIP.PGD ma y or may not have an IP payload, depending on whether 
the operation cleared ContextEn.If there is not an associated FUP, the binding will depend on whether there is an IP payload. If there is an IP payload, 
then the TIP.PGD should be applied to either the next direct branch whose ta rget matches the TIP.PGD payload, or 
the next branch that would normally generate a TIP or TNT packet. If there is no IP payload, then the TIP.PGD should apply to the next branch  or MOV CR3 instruction.7 6 5 4 3 2 1 0
0I P B y t e s 0 0 0 0 1
8 TargetIP[63:56]Vol. 3C 33-45INTEL® PROCESSOR TRACE
33.4.2.6  Flow Update (FUP) Packet
FUP IP Payload
Flow Update Packet gives the source address of an instructio n when it is needed. In general, branch instructions do 
not need a FUP, because the source address is clear from the disassembly. For asynchronous events, however, the 
source address cannot be inferred from the source, and hence a FUP will be sent. Table 33-23 illustrates cases 
where FUPs are sent, and which IP can be expected in those cases.Table 33-22. FUP Packet Definition
Name Flow Update (FUP) Packet
Dependencies TriggerEn && ContextEn.
(Typically depends on BranchEn and FilterEn as well, 
see Section 33.2.5, Section 
33.4.2.21, and Section 33.4.2.22 for details.)Generation ScenarioAsynchronous Events (interrupts, exceptions, INIT, SIPI, SMI, VM exit, 
#MC), PSB+, XBEGIN, XEND, XABORT , XACQUIRE, XRELEASE, EENTER, 
EEXIT, ERESUME, EEE, AEX,
1, INTO, INT1, INT3, INT n, a WRMSR that 
disables packet generation.
NOTES:
1. EENTER, EEXIT, ERESUME, EEE, AEX apply only if Intel Software  Guard Extensions is supported.Description Provides the source ad dress for asynchronous events, an d some other instructions. Is ne ver sent alone, always sent 
with an associated TIP or MODE  packet, and potentially others.
Application FUP packets provide the IP to which they bind. However, they are never standalone, but are coupled with other 
packets.
In TSX cases, the FUP is immediately preceded by a MODE.T SX, which binds to the same IP. A TIP will follow only in 
the case of TSX aborts, see Section 33.4.2.8 for details.Otherwise, FUPs are part of compound packet events (see  Section 33.4.1). In these compound cases, the FUP pro-
vides the source IP for an instruction or event, while a following TIP (or TIP.PGD) packet will provide the destination 
IP. Other packets may be included in the compound event between the FUP and TIP.7 6 5 4 3 2 1 0
0I P B y t e s 1 1 1 0 1
1 IP[7:0]
2I P [ 1 5 : 8 ]
3 IP[23:16]
4 IP[31:24]
5 IP[39:32]
6 IP[47:40]
7 IP[55:48]
8 IP[63:56]33-46 Vol. 3CINTEL® PROCESSOR TRACE
On a canonical fault due to sequentially fetching an instruction in non-canonical space (as opposed to jumping to 
non-canonical space), the IP of the fault (and thus the payl oad of the FUP) will be a non-canonical address. This is 
consistent with what is pushed on the stack for such faulting cases.
If there are post-commit task switch faults, the IP value of  the FUP will be the original IP when the task switch 
started. This is the same value as would be seen in the LBR_ FROM field. But it is a different value as is saved on the 
stack or VMCS.Table 33-23. FUP Cases and IP Payload
Event Flow Update IP Comment
External Interrupt, NMI/SMI, Traps, 
Machine Check (trap- like), INIT/SIPIAddress of next  instruction (Next IP) that 
would have been executedFunctionally, this matc hes the LBR FROM field 
value and also the EIP value which is saved onto 
the stack.
Exceptions/Faults,  Machine check 
(fault-like)Address of the instruction which took the
exception/fault (Current IP)This matches the simila r functionality of LBR 
FROM field value and also the EIP value which is 
saved onto the stack.
Software Interrupt Address of the software interrupt instruction 
(Current IP)This matches the simila r functionality of LBR 
FROM field value, but does not match the EIP value which is saved onto the stack (Next 
Linear Instruction Pointer - NLIP).
EENTER, EEXIT, ERESUME, Enclave 
Exiting Event (EEE), AEX
1 Current IP of the instruction This matc hes the LBR FROM field value and also 
the EIP value which is saved onto the stack.
XACQUIRE Address of the X* instruction
XRELEASE, XBEGIN, XEND, 
XABORT, other transactional abortCurrent IP
#SMI IP that is saved into SMRAM
WRMSR that clears TraceEn, PSB+ Current IP
NOTES:
1. Information on EENTER, EEXIT, ERESUME, EEE, Asynch ronous Enclave eXit (AEX) can be found in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3D.Vol. 3C 33-47INTEL® PROCESSOR TRACE
33.4.2.7  Paging Information (PIP) Packet
33.4.2.8  MODE Packets
MODE packets keep the decoder informed of various processor modes about which it needs to know in order to 
properly manage the packet output, or to properly disa ssemble the associated binaries. MODE packets include a 
header and a mode byte, as shown below.Table 33-24. PIP Packet Definition
Name Paging Information (PIP) Packet
Dependencies TriggerEn && ContextEn && 
IA32_RTIT_CTL.OSGeneration ScenarioMOV CR3, Task switch, INIT, SIPI, PSB+, VM exit, 
VM entry
Description The CR3 payload shown includes only the address po rtion of the CR3 value. For PAE paging, CR3[11:5] are thus 
included. For other paging modes (32-bit and 4-level paging1), these bits are 0.
This packet holds the CR3 address value. It wi ll be generated on operat ions that modify CR3:
• MOV CR3 operation
•T a s k  S w i t c h•I N I T  a n d  S I P I
• VM exit, if “conceal VMX from PT” VM-e xit control is 0 (s ee Section 33.5.1)
•V M e n t r y ,  i f  “ c o n c e a l  V M X  f r o m  PT” VM-entry control is 0
PIPs are not generated, despite changes to CR3, on SMI and RSM. This is due to the spec ial behavior on these oper-
ations, see Section 33.2.9.3 for details. Note that, for some cases of task swit ch where CR3 is not modified, no PIP 
will be produced.
The purpose of the PIP is to indicate to the decoder which application is running, so that it can apply the proper 
binaries to the li near addresses that are being traced. 
The PIP packet contains the new CR3 value when CR3 is written.
PIPs generated by VM entries set the NR bit. PIPs generated in VMX non-root operation set the NR  bit if the “con-
ceal VMX from PT” VM-execu tion control is 0 (see Section 33.5.1 ). All other PIPs clear the NR bit. 
NOTES:
1. Earlier versions of this manual used the term “IA-32e paging” to identify 4-level paging.Application The purpose of the PIP packet is  to help the decoder uniquely  identify what software is  running at any given time.

NOTES:
When a PIP is encountered, a decoder should do the following:1) If there was a prior unbound FUP (that is, a FUP not preceded by a packet such as MODE.TSX that consumes it, 
and it hence pairs with a TIP that has not yet been seen), th en this PIP is part of a compound packet event (Section 
33.4.1). Find the ending TIP and apply the new CR3/NR values to the TIP payload IP.
2) Otherwise, look for the next MOV CR3, far branch, or VMRESUME/VMLAUNCH in the disassembly, and apply the 
new CR3 to the next (or target) IP.
For examples of the packets generated by these flows, see Section 33.7.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 1 1
2 CR3[11:5] or 0 RSVD/NR
3 CR3[19:12]
4 CR3[27:20]
5 CR3[35:28]
6 CR3[43:36]
7 CR3[51:44]33-48 Vol. 3CINTEL® PROCESSOR TRACE
The MODE Leaf ID indicates which set of mode bits are held in the lower bits.
MODE.Exec PacketTable 33-25. General Form of MODE Packets
7 6 5 4 3 2 1 0
0 1 0 0 1 1 0 0 1
1L e a f  I D M o d e
Table 33-26. MODE.Exec Packet Definition
Name MODE.Exec Packet
MODE Leaf ID is '000.
Dependencies TriggerEn 
&& ContextEn 
&& FilterEnGeneration 
ScenarioAny operation that changes the CS.L, CS.D, or EFER.LMA, if 
IA32_RTIT_CTL.BranchEn=1.Any operation that changes RFLAGS .IF, if IA32_RTIT_CTL.EventEn=1.
Any TIP.PGE scenario, such that any of the mode bits tracked may have changed 
since the last MODE.Exec.
Description Indicates whether software is in 16, 32, or 64-bit mode, by providing the CS.D and (CS.L & IA32_EFER.LMA) values. 
Essential for the decoder to properly disassemble the associated binary. Further, if CPUID.0x14.0.EBX[6]=1 (“Event Trace Support”), it indicates when interrupts  are masked by providing the RFLAGS.IF value.
MODE.Exec is sent at the time of a mo de change, if dependencies are met at the time, otherwise it is sent when 
tracing resumes. In the former case, th e MODE.Exec packet is generated along with other packets that result from 
the operation that changes the mode, and is guaranteed to be followed by a TIP or TIP.PG E for branch operations, or 
a FUP for non-branch operations (CLI, STI, or POPF if EventEn=1). In cases where the mode changes while filtering dependencies are not met, the processo r ensures that the decoder doesn't lose  track of the mode by sending any 
needed MODE.Exec once tracing resumes (preceding the TI P.PGE, if BranchEn=1). The processor may opt to sup-
press the MODE.Exec when tracing resumes if the mode ma tches that of the la st MODE.Exec packet.
MODE.Exec packets are generated on CS.L, CS.D, or EFER.L MA changes only if contro l flow tracing is enabled 
(BranchEn=1). This is essential for the decoder to properly disassemble the associated binary.
MODE.Exec packets are generated on interrupt flag (RFLAGS.IF) changes only if event tracing is enabled 
(EventEn=1).
Application MODE.Exec always precedes an IP packet (TIP, TIP.PG E, or FUP). The mode change applies to the IP address in the 
payload of the IP packet. When MODE.Exec is followed by a FUP, it is a stand-alone FUP and should be consumed by 
the MODE.Exec.7 6 5 4 3 2 1 0
0 1 0 0 1 1 0 0 1
1 0 0 0R e s e r v e d I F C S . D ( C S . L  &  L M A )
CS.D (CS.L & IA32_EFER.LMA) Addressing Mode
11 N / A
01 6 4 - b i t  m o d e10 3 2 - b i t  m o d e
00 1 6 - b i t  m o d eVol. 3C 33-49INTEL® PROCESSOR TRACE
MODE.TSX Packet
Table 33-27. MODE.TSX  Packet Definition
Name MODE.TSX Packet
Dependencies TriggerEn && ContextEn Generation 
ScenarioXBEGIN, XEND, XABORT, XACQUIRE, XRELEASE, if InTX 
changes, Asynchronous TSX Abort, PSB+
Description Indicates when a TSX transaction (either HLE or RTM)  begins, commits, or aborts. Inst ructions executed transaction-
ally will be “rolled back” if  the transaction is aborted.
Application If PacketEn=1, MODE.TSX always immediately precedes a FUP. If the TXAbort bit is zero, then the mode change 
applies to the IP address in the payload of the FUP. If TXAbort=1, then the FUP will be followed by a TIP, and the 
mode change will apply to the IP address in the payload of the TIP.
MODE.TSX packets may be generated when PacketEn=0, due to FilterEn=0. In this case, only the last MODE.TSX generated before TIP.PGE need be applied.7 6 5 4 3 2 1 0
0 1 0 0 1 1 0 0 1
1 0 0 1000T X A b o r t I n T X
TXAbort InTX Implication
11 N / A0 1 Transaction begins, or executing transactionally
1 0 Transaction aborted
0 0 Transaction committed, or not executing transactionally33-50 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.9  TraceStop Packet
33.4.2.10  Core:Bus Ratio (CBR) PacketTable 33-28. TraceSto p Packet Definition
Name TraceStop Packet
ScenarioTaken branch with target in TraceStop IP region, MOV CR3 in TraceS-
top IP region, or WRMSR that sets  TraceEn in TraceStop IP region.
Description Indicates when so ftware has entered a user-configured TraceStop region. 
When the IP matches a TraceStop range while ContextEn and TriggerEn are set, a TraceStop action occurs. This dis-
ables tracing by setting IA32_RTIT_STATUS.Stopped, th ereby clearing TriggerEn, and causes a TraceStop
packet to be generated.
The TraceStop action also forces Filter En to 0. Note that TraceStop may no t force a flush of internally buffered 
packets, and thus trace packet genera tion should still be manu ally disabled by clearing IA32_RTIT_CTL.TraceEn 
before examining output. See Section 33.2.5.3 for more details.
Application If TraceStop follows a TIP.PGD (bef ore the next TIP.PGE), then it was trigge red either by the instruction that clear ed 
PacketEn, or it was triggered by some later instruction that executed while FilterEn=0. In either case, the TraceStop 
can be applied at the IP of the TIP.PGD (if any).If TraceStop follows a TIP.PGE (before the next TIP. PGD), it should be applied at the last known IP.
Table 33-29. CBR Packet Definition
Name Core:Bus Ratio (CBR) Packet
Dependencies TriggerEn Generation 
ScenarioAfter any frequency change, on C-state wake up, PSB+, and after 
enabling trace packet generation.
Description Indicates the core:bus ratio of the processor core. Useful for corre lating wall-clock time and cycle time.
Application The CBR packet indicates the point in the trace wh en a frequency transition has occurred. On some implementa-
tions, software execution will continue during transitions to a new frequency, while on others software execution 
ceases during frequency transitions. There is not a pr ecise IP provided, to whic h to bind the CBR packet.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 1 0 0 0 0 0 1 1
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 0 0 0 0 0 0 1 1
2C o r e : B u s  R a t i o
3 ReservedVol. 3C 33-51INTEL® PROCESSOR TRACE
33.4.2.11  Timestamp Counter (TSC) Packet
Table 33-30. TSC Packet Definition
Name Timestamp Counter (TSC) Packet
Dependencies IA32_RTIT_CTL.TSCEn && 
TriggerEnGeneration ScenarioSent after any event that causes the processor clocks or Intel PT timing 
packets (such as MTC or CYC) to stop, This may include P-state changes, wake from C-state, or clock modulati on. Also on transi tion of TraceEn 
from 0 to 1.
Description When enabled by software, a TSC packet provides the lower 7 bytes of the current TSC value, as returned by the 
RDTSC instruction. This may be useful for tracking wall-clock time, and synchronizing the packets in the log with 
other timestamped logs.
Application TSC packet provides a wall-cloc k proxy of the event which ge nerated it (packet generation enable, sleep state wake, 
etc). In all cases, TSC does not precisely indicate the time of any control flow packets; however, all preceding packets represent instructions that executed before the indicated TSC time, and all subsequent packets represent instruc-
tions that executed after it. There is not a precise IP to which to  bind the TSC packet.7 6 5 4 3 2 1 0
0 0 0 0 1 1 0 0 1
1S W  T S C [ 7 : 0 ]
2S W  T S C [ 1 5 : 8 ]
3 SW TSC[23:16]
4 SW TSC[31:24]
5 SW TSC[39:32]
6 SW TSC[47:40]
7 SW TSC[55:48]33-52 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.12  Mini Time Counter (MTC) Packet
Table 33-31. MTC Packet Definition
Name Mini time Counter (MTC) Packet
Dependencies IA32_RTIT_CTL.MTCEn && 
TriggerEnGeneration ScenarioPeriodic, based on the core crystal clock, or Always Running Timer 
(ART).
Description When enabled by software, an MTC packet provides a periodic indication of wall-clock time. The 8-bit CTC (Common 
Timestamp Copy) payload value is set to (ART >> N) & FFH. The frequency of the ART is related to the Maximum 
Non-Turbo frequency, and the ratio can be determined from CPUID leaf 15H, as described in Section 33.8.3.
Software can select the threshold N,  which determines the MTC frequency by setting the IA32_RTIT_CTL.MTCFreq 
field (see Section 33.2.8.2) to a supported value using the lookup enumerated by CPUID (see Section 33.3.1). See Section 33.8.3 for details on how to  use the MTC payload to track TSC time.

(ART).
MTC provides 8 bits from the ART, starting with the bit selected by MTCFreq to dictate the frequency of the packet. 
Whenever that 8-bit range being watched changes, an MTC pa cket will be sent out with the new value of that 8-bit 
range. This allows the decoder to keep track of how much wall-clock time has elapsed since the last TSC packet was 
sent, by keeping track of how many MTC packets were sent and what their value was. The decoder can infer the 
truncated bits, CTC[N-1:0], are 0 at the time of the MTC packet.
There are cases in which MTC packet can be dropped, due to overflow or other micro-architectural conditions. The 
decoder should be able to recover from  such cases by checking the 8-bit payload of the next MTC packet, to deter-
mine how many MTC packets were dropped. It is not expe cted that >256 consecutive MTC packets should ever be 
dropped.
Application MTC does not precisely indicate the time of any other packet, nor does it bind to any IP. However, all preceding pac k-
ets represent instructions or events that executed before the indicated ART time, and all subsequent packets repre-
sent instructions that executed after, or at the same time  as, the ART time.7 6 5 4 3 2 1 0
0 0 1 0 1 1 0 0 1
1C T C [ N + 7 : N ]Vol. 3C 33-53INTEL® PROCESSOR TRACE
33.4.2.13  TSC/MTC Alignment (TMA) Packet
Table 33-32. TMA Packet Definition
Name TSC/MTC Alignment (TMA) Packet
IA32_RTIT_CTL.TSCEn && TriggerEnGeneration Sce-narioSent with any TSC packet.
Description The TMA packet serves to provide the information needed to allow the decoder to correlate MTC packets with TSC 
packets. With this packet, when a MTC packet is encountered, the decoder can determine how many timestamp 
counter ticks have passed since the last TSC or MTC packet. See Section 33.8.3.2 for details on how to make this cal-
culation.
Application TMA is always sent immediately following a TSC packet, and the payload values are consistent with the TSC payload 
value. Thus the application of TMA matches that of TSC.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 0 1 1 1 0 0 1 1
2C T C [ 7 : 0 ]
3C T C [ 1 5 : 8 ]
4 Reserved 0
5 FastCounter[7:0]
6 Reserved FC[8]33-54 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.14  Cycle Count (CYC) Packet
Table 33-33. Cycle Count Packet Definition
Name Cycle Count (CYC) Packet
Dependencies IA32_RTIT_CTL.CYCEn && 
TriggerEnGeneration Sce-narioCan be sent at any time, though a maximum of one CYC packet is 
sent per core clock cycle. See Sect ion 33.3.6 for CYC-eligible packets.
Description The Cycle Counter field increments at the same rate as  the processor core clock ticks,  but with a variable length fo r-
mat (using a trailing EXP bit fiel d) and a range-capped byte length. 
If the CYC value is less than 32, a 1-byte CYC will be ge nerated, with Exp=0.  If the CYC value is between 32 and 
4095 inclusive, a 2-byte CYC will be generated, with byte 0 Exp=1 and byte 1 Exp=0. And so on.
CYC provides the number of core clocks that have passed since the last CYC packet. CYC can be configured to be 
sent in every cycle in which an eligible packet is generate d, or software can opt to us e a threshold to limit the num-
ber of CYC packets, at the expense of some precision. These settings are configured using the
IA32_RTIT_CTL.CycThresh field (see Section 33.2.8.2). For de tails on Cycle-Accurate Mode , IPC calculation, etc, see 
Section 33.3.6.When CycThresh=0, and hence no threshold is in use, then a CYC packet will be generated in any cycle in which any 
CYC-eligible packet is generated. The CYC packet will precede the other packets generated in the cycle, and provides 
the precise cycle time of the packets that follow.In addition to these CYC packets generated with other packets, CYC packets can be sent stand-alone. These packets 
serve simply to update the de coder with the number of cycles passed, an d are used to ensure that a wrap of the 
processor’s internal cycle counter doesn’t cause cycle information to be lost. These stand-alone CYC packets do not indicate the cycle time of any other packet or operation, and will be followed by another CYC packet before any 
other CYC-eligible packet is seen.
When CycThresh>0, CYC packets are generated only after a minimum number of cycles have passed since the last CYC packet. Once this threshold has passed, the behavior above resumes, where CYC will either be sent in the next 
cycle that produces other CYC-eligible packets, or could be  sent stand-alone.
When using CYC thresholds, only the cycle time of the op eration (instruction or even t) that generates the CYC 
packet is truly known. Other operations simply have thei r execution time bounded: they completed at or after the 
last CYC time, and before the next CYC time.
Application CYC provides the offset cycle time (since the last CYC packet) for the CYC-eligible packet that follows. If another CYC 
is encountered before the next CYC-eligible packet, the cycle values should be accumulated and applied to the next 
CYC-eligible packet.If a CYC packet is generated by a TNT,  note that the cycle time  provided by the CYC pack et applies to the first 
branch in the TNT packet.7 6 5 4 3 2 1 0
0 Cycle Counter[4:0] Exp 1 1
1 Cycle Counter[11:5] Exp
2 Cycle Counter[18:12] Exp
... ... (if Exp = 1 in the previous byte)Vol. 3C 33-55INTEL® PROCESSOR TRACE
33.4.2.15  VMCS Packet
Table 33-34. VMCS Packet Definition
Name VMCS Packet
Dependencies TriggerEn && ContextEn;
Also in VMX operation.Generation Scenario Generated on successful VMPTRLD, and optionally on PSB+, SMM 
VM exits, and VM entries that re turn from SMM (see Section 33-
53).
Description The VMCS packet provides a VMCS pointer for a decoder to determ ine the transition of code contexts:
• On a successful VMPTRLD (i.e., a VMPTRLD that doesn’t fa ult, fail, or VM exit), the VMCS packet contains the 
logical processor’s VMCS pointer established by VMPTRLD (for subsequent execution of a VM guest context). 
• An SMM VM exit loads the logical proce ssor’s VMCS pointer with the SMM-transfer VMCS po inter. If the “conceal 
VMX from PT” VM-exit control is 0 (see Section 33.5.1), a VM CS packet provides this pointer. See Section 33.6 on 
tracing inside and outside STM.
• A VM entry that returns from SMM load s the logical processor’s VMCS pointer from a fiel d in the SMM-transfer 
VMCS. If the “conceal VMX from PT” VM-entry control is 0, a VMCS packet provides this pointer. Whether the 
VM entry is to VMX root operation or VMX non-root operation is indicated by the PIP.NR bit.
A VMCS packet generated before a VMCS pointer has been loaded, or after the VMCS pointer has been cleared will 
set all 64 bits in th e VMCS pointer field.
VMCS packets will not be seen on processors with IA32_ VMX_MISC[bit 14]=0, as thes e processors do not allow 
TraceEn to be set in VMX operation.
Application The purpose of the VMCS packet is to help the decoder uniquely identify changes in the executing software context 
in situations that CR 3 may not be unique. 
When a VMCS packet is encountered, a decoder should do the following:
• If there was a prior unbound FUP (that is, a FUP not preceded by a packet such as MODE.TSX that consumes it, and 
it hence pairs with a TIP that has not ye t been seen), then this VMCS is part of a compound packet event (Section 
33.4.1). Find the ending TIP and apply the new VMCS base pointer value to the TIP payload IP. 
• Otherwise, look for the next VMPTRLD, VMRESUME, or VMLAUNCH in the disassembly, and apply the new VMCS 
base pointer on the next VM entry.
For examples of the packets generated by these flows, see Section 33.7 .7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 1 1 0 0 1 0 0 0
2 VMCS pointer [19:12]
3 VMCS pointer [27:20]
4 VMCS pointer [35:28]
5 VMCS pointer [43:36]
6 VMCS pointer [51:44]33-56 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.16  Overflow (OVF) Packet
33.4.2.17  Packet Stream Boundary (PSB) PacketTable 33-35. OVF Packet Definition
Name Overflow (OVF) Packet
ScenarioOn resolution of internal buffer overflow
Description OVF simply indicates to the decoder that an internal buffer overflow occurred, and packets were likely lost. If 
BranchEN= 1, OVF is followed by a FUP or TIP.PGE which will provide the IP at which packet generation resumes. See 
Section 33.3.8.
Application When an OVF packet is encountered, the decoder should skip to the IP given in the subsequent FUP or TIP.PGE. The 
cycle counter for the CYC pack et will be reset at the ti me the OVF packet is sent.
Software should reset its call stack depth on overflow, sinc e no RET compression is allo wed across an overflow. Sim-
ilarly, any IP compression that follows the OVF is guaranteed to use as a reference LastIP the IP payload of an IP packet that preceded the overflow.
Table 33-36. PSB Packet Definition
Name Packet Stream Boundary (PSB) Packet
Packet Format7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 1 1 1 1 0 0 1 1

0 0 0 0 0 0 0 1 0
1 1 1 1 1 0 0 1 1
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 1 0 0 0 0 0 1 0
2 0 0 0 0 0 0 1 0
3 1 0 0 0 0 0 1 0
4 0 0 0 0 0 0 1 0
5 1 0 0 0 0 0 1 0
6 0 0 0 0 0 0 1 0
7 1 0 0 0 0 0 1 0
8 0 0 0 0 0 0 1 0
9 1 0 0 0 0 0 1 0
10 0 0 0 0 0 0 1 0
11 1 0 0 0 0 0 1 0
12 0 0 0 0 0 0 1 0
13 1 0 0 0 0 0 1 0
14 0 0 0 0 0 0 1 0
15 1 0 0 0 0 0 1 0Vol. 3C 33-57INTEL® PROCESSOR TRACE
33.4.2.18  PSBEND PacketDependencies TriggerEn Generation 
ScenarioPeriodic, based on the number of output by tes generated while tracing. PSB is sent 
when IA32_RTIT_STATUS.PacketByteCnt=0, an d each time it cr osses the software 
selected threshold after that. May be sent for other micro-architectural conditions as well.
Description PSB is a unique pattern in the packet output log, and hence serves as a sync point for the decoder. It is a pattern 
that the decoder can search for in order to get aligned on packet boundaries. This packet is periodic, based on the 
number of output bytes, as indicated by IA32_RTIT_STAT US.PacketByteCnt. The period is chosen by software, via 
IA32_RTIT_CTL.PSBFreq (see Sect ion 33.2.8.2). Note, however, th at the PSB period is not precise, it simply reflects 
the average number of output bytes that should pass be tween PSBs. The processor will make a best effort to 
insert PSB as quickly after the selected threshold is reached as possible. The processor also may send extra
PSB packets for some micro- architectural conditions.
PSB also serves as the leading packet for a set of “status-on ly” packets collective ly known as PSB+ (Section 33.3.7). 
Application When a PSB is seen, the decoder should interpret all following packets as “status only ”, until either a PSBEND or 
OVF packet is encountered. “Status only” implies that the binding and ordering rules to which these packets nor-
mally adhere are ignored, and the state they carry can instead be applied to the IP payload in the FUP packet that is 
included.
Table 33-37. PSBEND Packet Definition
Name PSBEND Packet
ScenarioAlways follows PSB packet, separated by PSB+ packets
Description PSBEND is simply a terminator for the series of “s tatus only” (PSB+) packets that follow PSB (Section 33.3.7).
Application When a PSBEND packet is seen, the decode r should cease to treat packets as “status only”.Table 33-36. PSB Packet Definition (Contd.)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 1 133-58 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.19  Maintenance (MNT) Packet
33.4.2.20  PAD PacketTable 33-38. MNT Packet Definition
Name Maintenance (MNT) Packet
Dependencies  TriggerEn Generation 
ScenarioImplementation specific.
Description This packet is generated by hardware, the payload meaning is model-specific.
Application Unless a decoder has been extended for a particular family/model/stepping to interpret MNT packet payloads, this 
packet should simply be ignored.  It does not bi nd to any IP.
Table 33-39. PAD Packet Definition
Name PAD Packet
ScenarioImplementation specific
Description PAD is simply a NOP packet. Processor implementations may choose to add pad packets to improve packet align-
ment or for implementation-specific reasons.
Application Ignore PAD packets.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 1 1
2 1 0 0 0 1 0 0 0
3 Payload[7:0]
4 Payload[15:8]
5 Payload[23:16]
6 Payload[31:24]
7 Payload[39:32]
8 Payload[47:40]
9 Payload[55:48]
10 Payload[63:56]
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0Vol. 3C 33-59INTEL® PROCESSOR TRACE
33.4.2.21  PTWRITE (PTW) Packet
Table 33-40. PTW Packet Definition
Name PTW Packet
The PayloadBytes field indicates the number of bytes of payload that follow the header bytes. Encodings are as fol-
lows:
IP bit indicates if a FUP, whose payload will be the IP of the PTWRITE instruction, will follow.
FilterEn && PTWEnGeneration ScenarioPTWRITE In struction
Description Contains the value held in the PTWRITE operand.
This packet is CYC-eligible, and hence will generate a CYC packet if IA32_RTIT_CTL. CYCEn=1 and any CYC Threshold 
has been reached.
Application Binds to the associated PTWRITE instruction. The IP  of the PTWRITE will be provid ed by a followi ng FUP, when 
PTW.IP=1.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 IP PayloadBytes 1 0 0 1 0
2 Payload[7:0]
3 Payload[15:8]
4 Payload[23:16]
5 Payload[31:24]
6 Payload[39:32]
7 Payload[47:40]
8 Payload[55:48]
9 Payload[63:56]
PayloadBytes Bytes of Payload
‘00 4
‘01 8‘10 Reserved
‘11 Reserved33-60 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.22  Execution Stop (EXSTOP) Packet
Table 33-41. EXSTOP Packet Definition
Name EXSTOP Packet
Dependencies TriggerEn && PwrEvtEn Generation 
ScenarioC-state entry, P-state change, or other processor clock power-
down. Includes :
• Entry to C-state deeper than C0.0
•T M 1 / 2
•S T P C L K #• Frequency change due to IA32_CLOCK_MODULATION, Turbo
Description This packet indicates that so ftware execution has stopped due to processor clock powerdown. Later packets will 
indicate when execution resumes. 
If EXSTOP is generated while ContextEn is set, the IP bit will be set, and EX STOP will be followed by a FUP packet 
containing the IP at which execution stopped. More precisel y, this will be the IP of th e oldest instru ction that has 
not yet completed.
This packet is CYC-eligible, and hence will generate a CY C packet if IA32_RTIT_CTL.CY CEn=1 and any CYC Threshold 
Application If a FUP follows EXSTOP (hence IP bit set), the EXSTOP can be bound to the FUP IP. Otherwise the IP is not known. 
Time of powerdown can be inferred fr om the preceding CYC, if CYCEn=1. Combined with the TSC at the time of 
wake (if TSCEn=1), this can be used to determine the duration of the powerdown.IP bit indicates if  a FUP will follow.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 IP 1 1 0 0 0 1 0Vol. 3C 33-61INTEL® PROCESSOR TRACE
33.4.2.23  MWAIT Packet
Table 33-42. MWAIT Packet Definition
Name MWAIT Packet
Dependencies TriggerEn && PwrEvtEn && 
ContextEnGeneration ScenarioMWAIT, UMWAIT, or TPAUSE instructions, or I/O redirection to 
MWAIT, that complete wi thout fault or VMexit.
Description Indicates that an MWAIT operation to C-state deeper  than C0.0 completed. The MWAIT hints and extensions passed 
in by software are exposed in the payload. For UMWAIT and TPAUSE, the EXT field holds the input register value that determines the op timized state requested.
For entry to some highly optimized C0 sub-C-states, such as C0.1, no MWAIT packet is generated.
Application The binding for the upcoming EXSTOP packet also applies to the MWAIT packet. See Section 33.4.2.22.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 1 0
2 MWAIT Hints[7:0]
3 Reserved
4 Reserved
5 Reserved
6 Reserved EXT[1:0]
7 Reserved
8 Reserved
9 Reserved33-62 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.24  Power Entry (PWRE) Packet
Table 33-43. PWRE Packet Definition
Name PWRE Packet
ScenarioTransition to a C-state deeper than C0.0.
Description Indicates processor en try to the resolved thre ad C-state and sub C-state indicated.  The processor will remain in thi s 
C-state until either another PWRE indi cates the processor has moved to a C- state deeper than C0.0, or a PWRX 
packet indicates a return to C0.0.
For entry to some highly optimized C0 sub-C-stat es, such as C0.1, no PW RE packet is generated.
Note that some CPUs may allow MWAIT to request a deeper C-state than is supported by the core. These deeper C-states may have platform-level implications that differentiate them. However, the PWRE packet will provide only 
the resolved thread C-state, which will not exceed that supp orted by the core.
If the C-state entry was initiated by hardware, rather than a direct software request (such as MWAIT, UMWAIT, 
TPAUSE, HLT, or shutdown), the HW bit will be set to indicate this. Hardware Duty Cycling (see Section 15.5, “Hard-
ware Duty Cycling (HDC),” in the Intel
® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B) is an 
example of such a case.
Application When transitioning from C0.0 to a deeper C-state, th e PWRE packet will be followed by an EXSTOP. If that EXSTOP 
packet has the IP bit set, th en the following FUP will provide the IP at which the C-state entry occurred. Subsequent 
PWRE packets generated before the next PWRX should bind to the same IP.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 1 0
2 HW Reserved
3 Resolved Thread C-State Resolved Thread Sub C-StateVol. 3C 33-63INTEL® PROCESSOR TRACE
33.4.2.25  Power Exit (PWRX) Packet
Table 33-44. PWRX Packet Definition
Name PWRX Packet
ScenarioTransition from a C-state deeper than C0.0 to C0.
Description Indicates processor return to th read C0 from a C-state deeper than C0.0.

0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 1 0
For return from some highly optimized C0 sub-C-st ates, such as C0.1, no PW RX packet is generated.
The Last Core C-State field provides the MWAIT encoding fo r the core C-state at the time of the wake. The Deepest 
Core C-State provides the MWAIT encoding for the deepest core C-state achieved during the sleep session, or since 
leaving thread C0. MWAIT encodings for C-states can be found in Table 4-11 in the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume  2B. Note that these values reflect only the core C-state, and hence will 
not exceed the maximum supported core C-state, even if deeper C-states can be requested.
The Wake Reason field is one-hot, encoded as follows:
Application PWRX will always apply to the same IP as the PWRE. The time of wake can be discerned from (optional) timing pack-
ets that precede PWRX.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 1 0 1 0 0 0 1 0
2 Last Core C-State Deepest Core C-State
3 Reserved Wake Reason
4 Reserved
5 Reserved
6 Reserved
Bit Field Meaning
0 Interrupt Wake due to external interrupt received.
1 Timer Deadline Wake due to timer expiration, such as 
UMWAIT/TPAUSE TSC-quanta.
2 Store to Monitored Address Wake du e to store to monitored address.
3 HW Wake Wake due to hardware autonomous condition, 
such as HDC.33-64 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.26  Block Begin Packet (BBP)
Table 33-45. Block Begin Packet Definition
Name BBP
ScenarioPEBS event, if IA32_PEBS_ENABLE.OUTPUT=1.
Description This packet indicates the beginning of a block of packets which are collectively tied to a single event or instructi on. 
The size of the block item payloads within this block is provided by the Size (SZ) bit:SZ=0: 8-byte block items
SZ=1: 4-byte block items
The meaning of the BIP payloads is provided by the Type field:
Application A BBP will always be followed by a Block End Packet (BEP), and when the block is generated while ContextEn=1 
that BEP will have IP=1 and be followed by a FUP that provides the IP to which the block should be bound. Note 
that, in addition to BEP, a block can be  terminated by a BBP (indicating the start of a new block) or an OVF packet.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 0 1 1 0 0 0 1 1
2 SZ Reserved Type[4:0]
BBP.Type Block name
0x01 General-Purpose Registers0x02..0x03 Reserved
0x04 PEBS Basic
0x05 PEBS Memory0x06..0x07 Reserved
0x08 LBR Block 0
0x09 LBR Block 10x0A LBR Block 2
0x0B..0x0F Reserved
0x10 XMM Registers0x11..0x1F ReservedVol. 3C 33-65INTEL® PROCESSOR TRACE
33.4.2.27  Block Item Packet (BIP)
BIP State Value Encodings
The table below provides the encoding values for all define d block items. State items that are larger than 8 bytes, 
such as XMM register values, are broken into multiple 8-byte components. BIP packets with Size=1 (4 byte 
payload) will provide only the lower 4 bytes of the associated state value.Table 33-46. Block Item Packet Definition
Name BIP
Packet Format If the preceding BBP.SZ=0:
If the preceding BBP.SZ=1:
ScenarioSee BBP.
Description The size of the BIP payload is determined by the Size field in the preceding BBP packet.
The BIP header provides the ID value that, when combined with the Type field from the preceding BBP, uniquely 
identifies the state value held in the BIP payload. See Table 33-47 below for the complete list.
Application See BBP.
Table 33-47. BIP Encodings 
BBP.Type BIP.ID State Value
General-Purpose Registers
0x01 0x00 R/EFLAGS0x01 0x01 R/EIP
0x01 0x02 R/EAX
0x01 0x03 R/ECX7 6 5 4 3 2 1 0
0 ID[5:0] 1 0 0
1 Payload[7:0]
2 Payload[15:8]
3 Payload[23:16]
4 Payload[31:24]
5 Payload[39:32]
6 Payload[47:40]
7 Payload[55:48]
8 Payload[63:56]
7 6 5 4 3 2 1 0
4 Payload[31:24]33-66 Vol. 3CINTEL® PROCESSOR TRACE
0x01 0x04 R/EDX
0x01 0x05 R/EBX
0x01 0x06 R/ESP
0x01 0x07 R/EBP0x01 0x08 R/ESI
0x01 0x09 R/EDI
0x01 0x0A R80x01 0x0B R9
0x01 0x0C R10
0x01 0x0D R110x01 0x0E R120x01 0x0F R13
0x01 0x10 R14
0x01 0x11 R15
PEBS Basic Info (Section 20.9.2.2.1)
0x04 0x00 Instruction Pointer
0x04 0x01 Applicable Counters 0x04 0x02 Timestamp 
PEBS Memory Info (Section 20.9.2.2.2)
0x05 0x00 MemAccessAddress0x05 0x01 MemAuxInfo
0x05 0x02 MemAccessLatency
0x05 0x03 TSXAuxInfo
LBR_0
0x08 0x00 LBR[TOS-0]_FROM_IP
0x08 0x01 LBR[TOS-0]_TO_IP0x08 0x02 LBR[TOS-0]_INFO
0x08 0x03 LBR[TOS-1]_FROM_IP
0x08 0x04 LBR[TOS-1]_TO_IP0x08 0x05 LBR[TOS-1]_INFO
0x08 0x06 LBR[TOS-2]_FROM_IP
0x08 0x07 LBR[TOS-2]_TO_IP0x08 0x08 LBR[TOS-2]_INFO
0x08 0x09 LBR[TOS-3]_FROM_IP
0x08 0x0A LBR[TOS-3]_TO_IP0x08 0x0B LBR[TOS-3]_INFO
0x08 0x0C LBR[TOS-4]_FROM_IP
0x08 0x0D LBR[TOS-4]_TO_IPTable 33-47. BIP Encodings  (Contd.)
BBP.Type BIP.ID State ValueVol. 3C 33-67INTEL® PROCESSOR TRACE
0x08 0x0E LBR[TOS-4]_INFO
0x08 0x0F LBR[TOS-5]_FROM_IP
0x08 0x10 LBR[TOS-5]_TO_IP
0x08 0x11 LBR[TOS-5]_INFO0x08 0x12 LBR[TOS-6]_FROM_IP
0x08 0x13 LBR[TOS-6]_TO_IP
0x08 0x14 LBR[TOS-6]_INFO0x08 0x15 LBR[TOS-7]_FROM_IP
0x08 0x16 LBR[TOS-7]_TO_IP
0x08 0x17 LBR[TOS-7]_INFO0x08 0x18 LBR[TOS-8]_FROM_IP0x08 0x19 LBR[TOS-8]_TO_IP
0x08 0x1A LBR[TOS-8]_INFO
0x08 0x1B LBR[TOS-9]_FROM_IP0x08 0x1C LBR[TOS-9]_TO_IP
0x08 0x1D LBR[TOS-9]_INFO
0x08 0x1E LBR[TOS-10]_FROM_IP0x08 0x1F LBR[TOS-10]_TO_IP
LBR_1
0x09 0x00 LBR[TOS-10]_INFO0x09 0x01 LBR[TOS-11]_FROM_IP
0x09 0x02 LBR[TOS-11]_TO_IP
0x09 0x03 LBR[TOS-11]_INFO0x09 0x04 LBR[TOS-12]_FROM_IP
0x09 0x05 LBR[TOS-12]_TO_IP
0x09 0x06 LBR[TOS-12]_INFO0x09 0x07 LBR[TOS-13]_FROM_IP
0x09 0x08 LBR[TOS-13]_TO_IP
0x09 0x09 LBR[TOS-13]_INFO0x09 0x0A LBR[TOS-14]_FROM_IP
0x09 0x0B LBR[TOS-14]_TO_IP
0x09 0x0C LBR[TOS-14]_INFO0x09 0x0D LBR[TOS-15]_FROM_IP
0x09 0x0E LBR[TOS-15]_TO_IP
0x09 0x0F LBR[TOS-15]_INFO0x09 0x10 LBR[TOS-16]_FROM_IP
0x09 0x11 LBR[TOS-16]_TO_IP
0x09 0x12 LBR[TOS-16]_INFOTable 33-47. BIP Encodings  (Contd.)
BBP.Type BIP.ID State Value33-68 Vol. 3CINTEL® PROCESSOR TRACE
0x09 0x13 LBR[TOS-17]_FROM_IP
0x09 0x14 LBR[TOS-17]_TO_IP
0x09 0x15 LBR[TOS-17]_INFO
0x09 0x16 LBR[TOS-18]_FROM_IP0x09 0x17 LBR[TOS-18]_TO_IP
0x09 0x18 LBR[TOS-18]_INFO
0x09 0x19 LBR[TOS-19]_FROM_IP0x09 0x1A LBR[TOS-19]_TO_IP
0x09 0x1B LBR[TOS-19]_INFO
0x09 0x1C LBR[TOS-20]_FROM_IP0x09 0x1D LBR[TOS-20]_TO_IP0x09 0x1E LBR[TOS-20]_INFO
0x09 0x1F LBR[TOS-21]_FROM_IP
LBR_2
0x0A 0x00 LBR[TOS-21]_TO_IP
0x0A 0x01 LBR[TOS-21]_INFO
0x0A 0x02 LBR[TOS-22]_FROM_IP0x0A 0x03 LBR[TOS-22]_TO_IP
0x0A 0x04 LBR[TOS-22]_INFO
0x0A 0x05 LBR[TOS-23]_FROM_IP0x0A 0x06 LBR[TOS-23]_TO_IP
0x0A 0x07 LBR[TOS-23]_INFO
0x0A 0x08 LBR[TOS-24]_FROM_IP0x0A 0x09 LBR[TOS-24]_TO_IP
0x0A 0x0A LBR[TOS-24]_INFO
0x0A 0x0B LBR[TOS-25]_FROM_IP0x0A 0x0C LBR[TOS-25]_TO_IP
0x0A 0x0D LBR[TOS-25]_INFO
0x0A 0x0E LBR[TOS-26]_FROM_IP0x0A 0x0F LBR[TOS-26]_TO_IP
0x0A 0x10 LBR[TOS-26]_INFO
0x0A 0x11 LBR[TOS-27]_FROM_IP0x0A 0x12 LBR[TOS-27]_TO_IP
0x0A 0x13 LBR[TOS-27]_INFO
0x0A 0x14 LBR[TOS-28]_FROM_IP0x0A 0x15 LBR[TOS-28]_TO_IP
0x0A 0x16 LBR[TOS-28]_INFO
0x0A 0x17 LBR[TOS-29]_FROM_IPTable 33-47. BIP Encodings  (Contd.)
BBP.Type BIP.ID State ValueVol. 3C 33-69INTEL® PROCESSOR TRACE
0x0A 0x18 LBR[TOS-29]_TO_IP
0x0A 0x19 LBR[TOS-29]_INFO
0x0A 0x1A LBR[TOS-30]_FROM_IP
0x0A 0x1B LBR[TOS-30]_TO_IP0x0A 0x1C LBR[TOS-30]_INFO
0x0A 0x1D LBR[TOS-31]_FROM_IP
0x0A 0x1E LBR[TOS-31]_TO_IP0x0A 0x1F LBR[TOS-31]_INFO
0x10 0x00 XMM0_Q00x10 0x01 XMM0_Q10x10 0x02 XMM1_Q0
0x10 0x03 XMM1_Q1
0x10 0x04 XMM2_Q00x10 0x05 XMM2_Q1
0x10 0x06 XMM3_Q0
0x10 0x07 XMM3_Q10x10 0x08 XMM4_Q0
0x10 0x09 XMM4_Q1
0x10 0x0A XMM5_Q00x10 0x0B XMM5_Q1
0x10 0x0C XMM6_Q0
0x10 0x0D XMM6_Q10x10 0x0E XMM7_Q0
0x10 0x0F XMM7_Q1
0x10 0x10 XMM8_Q00x10 0x11 XMM8_Q1
0x10 0x12 XMM9_Q0
0x10 0x13 XMM9_Q10x10 0x14 XMM10_Q0
0x10 0x15 XMM10_Q1
0x10 0x16 XMM11_Q00x10 0x17 XMM11_Q1
0x10 0x18 XMM12_Q0
0x10 0x19 XMM12_Q10x10 0x1A XMM13_Q0
0x10 0x1B XMM13_Q1
0x10 0x1C XMM14_Q0Table 33-47. BIP Encodings  (Contd.)
BBP.Type BIP.ID State Value33-70 Vol. 3CINTEL® PROCESSOR TRACE
33.4.2.28  Block End Packet (BEP)0x10 0x1D XMM14_Q1
0x10 0x1E XMM15_Q0
0x10 0x1F XMM15_Q1
Table 33-48. Block End Packet Definition
Name BEP
Description Indicates the end of a packet block. The IP bit indicates if a FUP will follow, and will be set if ContextEn=1.
Application The block, from initial BBP to the BEP, binds to the FUP IP, if IP=1, and consumes the FUP.Table 33-47. BIP Encodings  (Contd.)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 IP 0 1 1 0 0 1 1Vol. 3C 33-71INTEL® PROCESSOR TRACE
33.4.2.29  Control Flow Event (CFE) Packet
CFE Packet Type and Vector Fields
Every CFE has a Type field, which provides the type of  event which generated the packet. For a subset of CFE 
Types, the CFE.Vector field may be valid. Details on these fi elds, as well as the IP to be expected in any following 
FUP packet, are provided in the table below.Table 33-49. Control Flow  Event Packet Definition
Name CFE
IP bit indicates if a st and-alone FUP will follow.
Dependencies IA32_RTIT_CTL.EventEn && 
TriggerEn && ContextEn

Name BEP
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
Name CFE
TriggerEn && ContextEn 
On ContextEn transitions, the CFE will be generated regardless of 
direction (1
→0 or 0 →1). VM 
exit is an exception, where 
CFE.VMEXIT depends only on the prior value of ContextEn.Generation 
ScenarioSoftware interrupt, external in terrupt, user interrupt, or 
exception, including those injected on VM entry.
INIT, SIPI, SMI, RSM, IRET, Shutdown.VM exit, if “Conceal VMX in PT” VMCS exit control is 0.
VM entry, if “Conce al VMX in PT” VMCS entry control is 0.
TSX Abort.
Description This packet indicates that an asynchronous event or related event (see list above) has occurred. The type of event 
is provided in the packet (see Table 33-50 below), and, if the IP bit is set, the IP at which the event occurred is pro-
vided in a stand-alone FUP packet that follows. Further, in the case of an inte rrupt or exception, the vector field 
provides the vector of the event.The IP bit will be set only wh en ContextEn=1 before the even t is taken, and either Bran chEn=0 or else no FUP is 
generated for this event by BranchEn=1. There are some cases, such as SIPI and RSM, where no FUP is generated.
Note that events that are not delivered to software, such as nested events or events which cause a VM exit, do not 
generate CFE packets.
Application If the IP bit is set, a FUP will follow that is stand-alone (not part of a compound packet event), and the CFE con-
sumes the FUP. If the IP bit is not se t, the CFE binds to the next FUP if Pa cketEn=1 (hence the CFE comes after a 
TIP.PGE but before the next TIP.PGD) , and is stand-alone if PacketEn=0.
Table 33-50. CFE Packet Type and Vector Fields Details
CFE Subtype Type Vector FUP IP Details
INTR 0x1 Event Vector Varies Used for interrupts (external and software), 
Exceptions, Faults, and NMI. FUP contains that address 
of the instruction that has not completed (NLIP for trap 
events, CLIP for fault events).
IRET 0x2 Invalid CLIPSMI 0x3 Invalid NLIP
RSM 0x4 Invalid None
SIPI 0x5 SIPI Vector NoneINIT 0x6 Invalid NLIP
VMENTRY 0x7 Invalid CLIP FUP contai ns IP of VMLAUNCH/VMRESUME.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 0 0 0 1 0 0 1 1
2 IP Reserved Type[4:0]
3 Vector[7:0]33-72 Vol. 3CINTEL® PROCESSOR TRACE
VMEXIT 0x8 Invalid Varies FUP IP varies depending on type of VM exit, but will be 
the address of the instruction that has not completed. 
Will be consistent with Guest IP saved in VMCS.
VMEXIT_INTR 0x9 Event Vector Varies Sent in case s where VM exit was caused by an INTR 
event (interrupt, exception, fault, or NMI). Vector 
provided is for the event which caused the VM exit. FUP IP behavior matches th at of INTR type above.
SHUTDOWN 0xa Invalid Varies FUP IP varies depending on the ty pe of event that 
caused shutdown, but will be the address of the 
instruction that has not completed.
Reserved 0xb N/A N/A
UINTR 0xc User Interrupt Vector NLIP User interrupt delivered.
UIRET 0xd Invalid CLIP Exiting from user interrupt routine.Reserved 0xe...0x1f N/A N/A ReservedTable 33-50. CFE Packet Type an d Vector Fields Details (Contd.)
CFE Subtype Type Vector FUP IP DetailsVol. 3C 33-73INTEL® PROCESSOR TRACE
33.4.2.30  Event Data (EVD) Packet
33.5 TRACING IN VMX OPERATION
On processors that IA32_VMX_MISC[bit 14] reports 1,  TraceEn can be set in VMX operation. The VMM can 
configure specific VMX controls to control what virtualization-specific data is included within the trace packets (see Section 33.5.1 for details). The VMM can also configure the VM CS to limit tracing to non-root operation, or to trace 
across both root and non-root operation. The VMCS controls ex ist to simplify virtualization of Intel PT for guest use, 
including the “Clear IA32_RTIT_CTL” exit control (See Section 25.7.1), “Load IA32_RTIT_CTL” entry control (See 
Section 25.8.1), and “Intel PT uses guest physical addresses” execution control (See Section 26.5.3).
For older processors that do not support these VMCS cont rols, the MSR-load areas used by VMX transitions can be 
employed by the VMM to restrict tracin g to the desired context. See Section 33.5.2 for details. Tracing with SMM 
Transfer Monitor is described in Section 33.6.Table 33-51. Event Data Packet Definition
Name EVD
TriggerEn && ContextEnGeneration ScenarioPage fault, including those injected on VM entry.
VM exit, if “Suppress VMX packets on exit” VMCS exit control 
is 0.
Description Provides additional data about the event that caused the following CFE. The Payload field is dictated by the Type.
EVD packets are never generated in cases where a CFE is not.
Application EVD packets bind to the same IP  (if any) as the subsequent CFE packet.7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0
1 0 1 0 1 0 0 1 1
2 Reserved Type[5:0]
Type Payload
'000000 Page Fault Linear Address, same as CR2 (PFA)'000001 VMX Exit Qualification (VMXQ)
'000010 VMX Exit Reason (VMXR)
'000011 - '111111 Reserved33-74 Vol. 3CINTEL® PROCESSOR TRACE
33.5.1 VMX-Specific Packets and VMCS Controls
In all of the usages of VMX and Intel PT, a decoder in the host or VMM context can identify the occurrences of VMX 
transitions with the aid of VMX-specific packets. There are four kinds of packets relevant to VMX:
•VMCS packet.  The VMX transitions of individual VMs can be distinguished by a decoder using the VMCS-
pointer field in a VMCS packet. A VMCS packet is sent  on a successful execution of VMPTRLD, and its VMCS-
pointer field stores the VMCS pointer loaded by that execution. See Section 33.4.2.15 for details.
•The NR (non-root) bit in a PIP packet.  Normally, the NR bit is set in any PIP packet generated in VMX non-
root operation. In addition, PIP packets are generated wi th each VM entry and VM exit. Thus a transition of the 
NR bit from 0 to 1 indicates the occurrence of a VM entry, and a transition of 1 to 0 indicates the occurrence of 
a VM exit.
•CFE packet. Identifies VM exit and VM entry operations.
•EVD packet.  Provides the exit reason and exit qualification for VM exits.
There are VMX controls that a VMM can set to conceal some  of this VMX-specific information (by suppressing its 
recording) and thereby prevent it from leaking across vi rtualization boundaries. There is one of these controls 
(each of which is called “conceal VMX fr om PT”) of each type of VMX control.
The 0-settings of these VMX controls enable all VMX-spec ific packet information. The scenarios that would use 
these default settings also do not require the VMM to us e VMX MSR-load areas to enable and disable trace-packet 
generation across VMX transitions.
If IA32_VMX_MISC[bit 14] reports 0, the 1-settings of th e VMX controls in Table 33-52 are not supported, and 
VM entry will fail on any attempt to set them.
33.5.2 Managing Trace Packet Gene ration Across VMX Transitions
In tracing scenarios that collect packets for both VMX root operation and VMX non-root operation, a host executive 
can manage the MSRs associated with trace packet generati on directly. The states of these MSRs need not be modi-
fied across VMX transitions.
For tracing scenarios that collect packets only within VMX r oot operation or only within VMX non-root operation, the 
VMM can toggle IA32_RTIT_CTL. TraceEn on VMX transitions.Table 33-52. VMX Controls For Intel Processor Trace
Type of VMX 
ControlBit 
Position1
NOTES:
1. These are the positions of the control bits in the relevant VMX control fields.Value Behavior
Secondary 
processor-based 
VM-execution control19 0 Each PIP generated in VM non-root operation will set the NR bit.
PSB+ in VMX non-root operation will include the VMCS packet, to ensure that the decoder 
knows which guest is currently in use.
1 Each PIP generated in VMX non-root operation will clear the NR bit.
PSB+ in VMX non-root operation will not include the VMCS packet.
VM-exit control 24 0 Each VM exit generates a PIP in which the NR bit is clear, and a CFE/EVD if Event Trace is 
enabled.
In addition, SMM VM exits generate VMCS packets.
1 VM exits do not generate PIPs, CFEs, or EVDs, and no VMCS packets are generated on SMM 
VM exits.
VM-entry control 17 0 Each VM entry generates a PIP in wh ich the NR bit is set (exc ept VM entries that return 
from SMM to VMX root operation), and a CFE if Event Trace is enabled.
In addition, VM entries that return from SMM generate VMCS packets.
1 VM entries do not generate PIPs or CFEs, and no VMCS packets are generated on 
VM entries that return from SMM.Vol. 3C 33-75INTEL® PROCESSOR TRACE
33.5.2.1  System-Wide Tracing
When a host or VMM configures Intel PT to collect trace packets of the entire system, it can leave the relevant VMX 
controls clear to allow VMX-specific packets to provide information across VMX transitions.
The decoder will desire to identify the occurrence of VMX transitions. The packets of interests to a decoder are 
shown in Table 33-53.

enabled.
VM exits.
Since the VMX controls that suppress packet generation are cleared, a VMCS packet will be included in all PSB+ for 
this usage scenario. Additionally, VMPTRLD will generate  such a packet. Thus the decoder can distinguish the 
execution context of different VMs.
When the host VMM configures a system to collect trace pack ets in this scenario, it should emulate CPUID to report 
CPUID.(EAX=07H, ECX=0):EBX[bit 26] as 0 to guests, in dicating to guests that Intel PT is not available.
VMX TSC Manipulation
The TSC packets generated while in VMX non-root operatio n will include any changes resulting from the use of a 
VMM’s use of the TSC offsetting or TSC scaling VMX controls  (see Chapter 26, “VMX Non-Root Operation”). In this 
system-wide usage model, the decoder may need to acco unt for the effect of per-VM adjustments in the TSC 
packets generated in VMX non-root operation and the ab sence of TSC adjustments in TSC packets generated in 
VMX root operation. The VMM can suppl y this information to the decoder.
33.5.2.2  Guest-Only Tracing
A VMM can configure trace-packet generation while in VMX non-root operation for guests executing normally. This 
is accomplished by utilizing VMCS controls to manipulate  the guest IA32_RTIT_CTL value on VMX transitions. For Table 33-53. Packets on VMX Tr ansitions (System-Wide Tracing)
Event Packets Enable Description
VM exit EVD.VMXR, 
EVD.VMXQ, 
CFE.VMEXIT*EventEn The CFE identifies th e transfer as a VM exit, while the associated EVDs 
provide the exit reason and exit qualification.
FUP(GuestIP) BranchEn or 
EventEnThe FUP indicates at which point in the guest flow the VM exit occurred. This 
is important, since VM exit can be an asynchronous event. The IP will match 
that written into the VMCS.
PIP(HostCR3, NR=0) The PIP packet provides the ne w host CR3 value, as we ll as indication that 
the logical proce ssor is entering VMX root operation. This allows the decoder 
to identify the change of  executing context from gu est to host and load the 
appropriate set of binaries to continue decode.
TIP(HostIP) BranchEn The TIP indica tes the destination IP, the IP of  the first instruction to be 
executed in VMX root operation.
Note, this packet could be preceded by a MODE.Exec packet (Section 
33.4.2.8). This is generated only in cases where CS.D or (CS.L & EFER.LMA) 
change during the transition.
VM entry CFEVMENTRY,
FUP(CLIP)EventEn The CFE identifies the transfer as a VM entry, while the FUP identifies the 
VMLAUNCH/VMRESUME IP.
PIP(GuestCR3, NR=1) BranchEn The PIP packet provides the new guest CR3 value, as well as indication that 
the logical processor is en tering VMX non-root operation. This allows the 
decoder to identify the change of executing context from host to guest and 
load the appropriate set of binaries to continue decode.
TIP(GuestIP) BranchEn The TIP indicates the destinat ion IP, the IP of the first instruction to be 
executed in VMX non-root operation. This should match the RIP loaded from 
the VMCS.
change during the transition.33-76 Vol. 3CINTEL® PROCESSOR TRACE
older processors that do not support these VMCS cont rols, a VMM can use the VMX MSR-load areas on VM exits 
(see Section 25.7.2, “VM-Exit Controls for MSRs”) and VM entries (see Section 25.8.2, “VM-Entry Controls for 
MSRs”) to limit trace-packet generation to the guest environment. 
For this usage, VM entry is programmed to enable trace packet generation, while VM exit is programmed to clear 
IA32_RTIT_CTL.TraceEn so as to disable trace-packet genera tion in the host. Further, if it is preferred that the 
guest packet stream contain no indication that execution was in VMX non-root operation, the VMM should set to 1 
all the VMX controls enumerated in Table 33-52.
33.5.2.3  Emulation of Intel PT Traced State
If a VMM emulates an element of processor state by taking a VM exit on reads and/or writes to that piece of state, 
and the state element impacts Intel PT packet generation or values, it may be incumbent upon the VMM to insert 
or modify the output trace data.
If a VM exit is taken on a guest write to CR3 (including “MOV CR3” as well as task switches), the PIP packet 
normally generated on the CR3 write will be missing.
To avoid decoder confusion when the guest trace is decode d, the VMM should emulate the missing PIP by writing it 
into the guest output buffer. If the guest CR3 value is manipulated, the VMM may also need to manipulate the 
IA32_RTIT_CR3_MATCH value, in order to ensure th e trace behavior matches the guest's expectation.
Similarly, if a VMM emulates the TSC value by taking a VM exit on RDTSC, the TSC packets generated in the trace 
may mismatch the TSC values returned by the VMM on RDTS C. To ensure that the trace can be properly aligned 
with software logs based on RDTSC, the VMM should eith er make corresponding modifications to the TSC packet 
values in the guest trace, or use mechanisms such as  TSC offsetting or TSC scaling in place of exiting.
33.5.2.4  TSC Scaling
When TSC scaling is enabled for a guest using Intel PT, the VMM should ensure that the value of Maximum Non-
Turbo Ratio[15:8] in MSR_PLATFORM_INFO (MSR 0CEH) and the TSC/”core crystal clock” ratio (EBX/EAX) in CPUID 
leaf 15H are set in a manner consistent with the resulting TSC rate that will be visible to the VM. This will allow the 
decoder to properly apply TSC packets, MTC packets (based on the core crystal clock or ART, whose frequency is indicated by CPUID leaf 15H), and CBR packets (which indicate the ratio of the processor frequency to the Max 
Non-Turbo frequency). Absent this, or separate indication  of the scaling factor, the decoder will be unable to prop-
erly track time in the trace. See Section 33.8.3 for details on tracking time within an Intel PT trace.
33.5.2.5  Failed VM Entry
The packets generated by a failed VM entry depend both on  the VMCS configuration, as  well as on the type of 
failure. The results to expect are summarized in the table below. Note that packets in italics  may or may not be 
generated, depending on implementati on choice, and the point of failure.
Table 33-54. Packets on  a Failed VM Entry
Usage Model Entry Configuration Early Failure (fall 
through to next IP)Late Failure (VM exit like)
System-Wide No use of “Load 
IA32_RTIT_CTL” entry 
control or VM-entry 
MSR-load areaTIP (NextIP) CFE.VMENTRY, FUP(CLIP) if EventEn=1
PIP(Guest CR3, NR=1), TraceEn 0 →1 Packets (See Section 
33.2.8.3),  PIP(HostCR3, NR=0), TIP(HostIP)
VMM Only “Load IA32_RTIT_CTL” 
entry control or VM-entry MSR-load area 
used to clear TraceEnTIP (NextIP) TraceEn 0
→1 Packets (See Section 33.2.8.3),  TIP(HostIP)
VM Only “Load IA32_RTIT_CTL” 
entry control or VM-
entry MSR-load area used to set TraceEnNone NoneVol. 3C 33-77INTEL® PROCESSOR TRACE
33.5.2.6  VMX Abort
VMX abort conditions take the processor into a shutdown  state. On a VM exit that leads to VMX abort, some 
packets (FUP, PIP) may be generated, but any expe cted TIP, TIP.PGE, or TIP.PGD may be dropped.
33.6 TRACING AND SMM TRANSFER MONITOR (STM)
The SMM-transfer monitor (STM) is a VM M that operates inside SMM while in VMX root operation. An STM operates 
in conjunction with an executive monitor. The latter oper ates outside SMM and in VMX root operation. Transitions 
from the executive monitor or its VMs to the STM ar e called SMM VM exits. The STM returns from SMM via a 
VM entry to the VM in VMX non-root operation or the executive monitor in VMX root operation. 
Intel PT supports tracing in an STM similar to tracing su pport for VMX operation as descr ibed above in Section 33.5. 
As a result, on a SMM VM exit resulting from #SMI, TraceEn is neither saved nor cleared by default. Software can 
save the state of the trace configuration MSRs and clear TraceEn using the MSR load/save lists.
Within Event Trace, SMM VM exits generate packets indicati ng both an #SMI and a VM exit. Similarly, VM entries 
that return from SMM generate packets that indicate both  an RSM and a VM entry. SM M VM exits initiated by the 
VMCALL instruction do not generate any CFE packet, thou gh the subsequent VM entry returning from SMM will 
generate a CFE.RSM.
33.7 PACKET GENERATION SCENARIOS
The following tables provides examples of packet genera tion for various operations. The following acronyms are 
used in the packet examples below:
•CLIP - Current LIP
•NLIP - Next Sequential LIP
•BLIP - Branch Target LIP
Table 33-55 illustrates the packets generated by a series of example operations, assuming that PacketEn 
(TriggerEn && ContextEn && FilterEn && BranchEn) is set before and after the operation.
Table 33-55. Packet Generation under Different Example Operations
Case Operation Details Packets
1 Normal non-jump operation None
2 Conditional branch 6th branch in internal TNT buffer TNT3 Conditional branch 1
st..5th branch in internal TNT buffer None
4 Near indirect JMP or CALL TIP(BLIP)

5 Direct near JMP or CALL None6N e a r  R E T U n c o m p r e s s e d T I P ( B L I P )
7 Near RET Compressed, 6th branch in internal TNT buffer TNT
8 Far Branch Assumes no update to  CR3, CS.L, or CS.D TIP(BLIP)
9 Far Branch Assumes update to  CR3 PIP(NewCR3), TIP(BLIP)
10 Far Branch Assumes update to CR3 and CS.D/CS.L PIP(NewCR3), MODE.Exec, TIP(BLIP)
11 External Interrupt or NMI Assu mes no update to CR3, CS.D, or CS.L FUP(NLIP), TIP(BLIP)
12 External Interrupt or NMI A ssumes update to CR 3 and CS.D/CS.L FUP(NLIP), PIP(NewCR3), 
MODE.Exec, TIP(BLIP)
13 Exception/Fault or Software Interrupt Assumes no up date to CR3, CS.D, or CS.L FUP(CLIP), TIP(BLIP)
14 MOV to CR3 PIP(NewCR3, NR)33-78 Vol. 3CINTEL® PROCESSOR TRACE
Table 33-56 illustrates the packets generated in example scenarios where the operation alters the value of 
PacketEn. Note that insertion of PSB+ is not included here, though it can be coincident with initial enabling of Intel 
PT. See Section 33.3.7 for details.15 VM exit Assumes system-wide tracing, see Section 
33.5.2.1See Table 33-53
16 VM entry Assumes system-w ide tracing, see Section 
17 ENCLU[EENTER] / ENCLU[ERESUME] / 
ENCLU[EEXIT] / AEX/EEEOnly debug enclaves allow PacketEn to be set 
during enclave execution. Assumes no change 
to CS.L or CS.D.FUP(CLIP), TIP(BLIP)
18 XBEGIN/XACQUIRE/XEND/XRELEASE Does not begin/end transactional execution None
19 XBEGIN/XACQUIRE Assumes beginning of transactional execution MODE.TSX(InTX=1, TXAbort=0), 
FUP(CLIP)
20 XEND/XRELEASE Completes transaction MODE.TSX(InTX=0, TXAbort=0), 
FUP(CLIP)
21 XABORT or Asynchronous Abort Aborts transa ctional execution MODE.TSX(InTX=0, TXAbort=1), 
FUP(CLIP), TIP(BLIP)
22 INIT On BSP. Assumes no CR3, CS.D, or  CS.L update. FUP(NLIP), TIP(ResetLIP)
23 INIT On AP, goes to wait -for-SIPI. A ssumes no CR3 
update.FUP(NLIP)
24 SIPI Assumes no CS.D or CS.L update TIP.PGE(SIPI.LIP)
25 Wake from state deeper than C0.1, P-
state change, or other scenario where timing packets (MTC, CYC) may have 
ceased.TSC if TSCEn=1
TMA if TSCEn=MTCEn=1TSC?, TMA?, CBR
26 UINTR User interrupt handler entry. FUP(NLIP)
27 UIRET Exiting from user interrupt handler. FUP(NLIP)
Table 33-56. Packet Generation with Oper ations That Alter th e Value of PacketEn
Case Operation PktEn 
BeforePktEn 
AfterCntxEn 
AfterDetails Packets
1 WRMSR/XRSTORS that 
changes TraceEn 0 → 10 1 0 TSC if TSCEn=1;
TMA if TSCEn=MTCEn=1TSC?, TMA?, CBR, MODE.Exec
2 WRMSR/XRSTORS that 
changes TraceEn 0 → 10 1 1 TSC if TSCEn=1;
TMA if TSCEn=MTCEn=1TSC?, TMA?, CBR, MODE.Exec, 
TIP.PGE(NLIP)
3W R M S R  t h a t  c h a n g e s  
TraceEn 1 → 01 0 D.C. FUP(CLIP), TIP.PGD()
4 Taken Branch 1 0 1 Source is  in IP filter region.
Target is outside IP filter region.TIP.PGD(BLIP)
5 Taken Branch, Interrupt, 
EEXIT, etc.0 1 1 Source is outside IP filter region.
Target is in IP  filter region.TIP.PGE(BLIP)
6 Far Branch, Interrupt, EEN-
TER, etc.1 0 0 Requires change to CPL or CR3, 
or entry to opt-out enclave.TIP.PGD()Table 33-55. Packet Generation under Different Example Operations
Case Operation Details PacketsVol. 3C 33-79INTEL® PROCESSOR TRACE
Table 33-57 illustrates examples of PTWRIT E, assuming TriggerEn && PTWEn is true. 
Table 33-58 illustrates examples of Power Event Tr ace, assuming TriggerEn && PwrEvtEn is true. 7 Trap-like event (external 
interrupt, NMI, VM exit/entry, 
etc.)1 0 0 Requires change to CPL or CR3. FUP(NLIP), TIP.PGD()
8 Fault-like event (excep-
tion/fault, so ftware inter-
rupt, VM exit/entry, etc.)1 0 0 Requires change to CPL or CR3. FUP(CLIP), TIP.PGD()
9 SMI, VM exit/entry 1 0 0 TraceEn is cleared. FUP(NLIP), TIP.PGD()
10 RSM, VM exit/entry 0 1 1 TraceEn is  set. See Case 2 for packets on 
enable. FUP/TIP.PGE IP is the BLIP.
11 VM Exit 1 0 0 Assumes gues t-only tracing, see 
Section 33.5.2.2.
TraceEn is cleared.FUP(VMCSg.RIP), TIP.PGD()
12 VM entry 0 1 1 Assumes gu est-only tracing, see 
Section 33.5.2.2.TraceEn is set.TIP.PGE(VMCSg.RIP)
Table 33-57. Examples of PTWRIT E when TriggerEn && PTWEn is True
Case Operation ContextEn Details Packets
1 MWAIT/UMWAIT gets fault or VM exit. D.C. None.
Other trace sources may generate pack-
ets on fault or VM exit.
2M W A I T / U M W A I T  r e q u e s t s  C 0 ,  o r  m o n i -
tor not armed, or VM X virtual-interrupt 
delivery.D.C. None.
3 MWAIT/UMWAIT enters C-state deeper 
than C0.1.0 PWRE(Cx), EXSTOP
4 MWAIT/UMWAIT enters C-state deeper 
than C0.1.1 MWAIT(Cy), PWRE(Cx), EXSTOP(IP), 
FUP(CLIP)
5 HLT, Triple-fault shutdown, other oper-
ation that enters C1.1 PWRE(C1), EXSTOP(IP), FUP(CLIP)
6 Hardware Duty Cycling (HDC). 1 TSC if TSCEn=1
TMA if TSCEn=MTCEn=1PWRE(HW, C6), EXSTOP(IP), FUP(NLIP), 
TSC?, TMA?, CBR, PWRX(CC6, CC6, 0x8)
7 Wake event during Cx (x  > 0). D.C. TSC if TSCEn=1
TMA if TSCEn=MTCEn=1TSC?, TMA?, CBR, PWRX(LCC, DCC, 0x1)
ets for the wake operation (e.g., inter-
rupt).
Table 33-58. Examples of Power Event Tr ace when TriggerEn && PwrEvtEn is True
Case Operation ContextEn 
&& 
FilterEnDetails Packets
1 PTWRITE rm32/64 0 NoneTable 33-56. Packet Generation with Operations That Alter the Value of PacketEn (Contd.)
AfterDetails Packets33-80 Vol. 3CINTEL® PROCESSOR TRACE
Table 33-59 illustrates examples of Event Trace, assuming  TriggerEn && ContextEn && EventEn is true. In all cases, 
other trace sources (e.g., BranchEn), if enabled, may generate additional packets. For details, see the other tables 
in this section.2 PTWRITE rm32 1 FUP, PTW.I P=1 if FUPonPTW=1 PTW(IP =1?, 4B, rm32_value), 
FUP(CLIP)?
3 PTWRITE rm64 1 FUP, PTW.I P=1 if FUPonPTW=1 PTW(IP =1?, 8B, rm64_value), 
Table 33-59. Event Trace Examples when Tr iggerEn && ContextEn && EventEn is True
BeforeContextEn 
1 IRET 1 D.C. CFE.IRET(IP=1), FUP(CLIP)
2I R E T 0 1 C F E ( I R E T )
3 External interrupt, including 
NMI1 D.C. CFE.INTR(IP=1, Vector), FUP(NLIP)
4 External interrupt, including 
NMI1 1 Assumes BranchEn=1, 
illustrates the shared FUP.CFE.INTR(IP=0, Vector), FUP(NLIP), 
TIP(BLIP)
5 SW Interrupt, Exception/Fault 
other than #PF1 D.C. CFE.INTR(IP=1, Vector), FUP(CLIP)
6 Page Fault (#PF) 1 D.C. EVD.PFA, CFE.INTR(IP=1,14), 
FUP(CLIP)
7 Page Fault (#PF) 0 D.C. None
10 SMI 1 D.C. CFE.SMI(IP=1), FUP(NLIP)11 RSM, TraceEn restored to 1 D.C. 1 CFE.RSM(IP=0)
12 Entry to Shutdown 1 D.C. CFE .SHUTDOWN(IP=1), FUP(CLIP)
13 VM exit caused by interrupt, 
fault, or SMI1 D.C. Assumes “Conceal VMX in 
PT” exit control is 0.EVD.VMXQ, EVD.VMXR, 
CFE.VMEXIT_INTR( IP=1, Vector), 
FUP(VMCSg.LIP)
14 VM exit caused by other than 
interrupt, fault, or SMI1 D.C. Assumes “Conceal VMX in 
CFE.VMEXIT(IP=1), FUP(VMCSg.LIP)
15 VM exit caused by other than 
interrupt, fault, or SMI0 1 Assumes “Conceal VMX in 
PT” exit control is 0.CFE.VMEXIT(IP=0)
16 VM entry 1 D.C. Assumes “Conceal VMX in 
PT” entry control is 0.CFE.VMENTRY(IP=1), FUP(VMCSh.LIP)
17 AEX/EEE, from opt-out (non-
debug) enclave00 N o n e
18 AEX/EEE, from opt-out (non-
debug) enclave0 1 CFE.INTR(IP=0)
19 AEX, from opt-in (debug) 
enclave1 D.C. CFE.INTR(IP=1, Vec), FUP(AEP LIP)
20 INIT 1 D.C. CFE.INIT(IP=1), FUP(NLIP)
21 SIPI 1 D.C. CFE.SIPI(IP=0)Table 33-58. Examples of Power Event Trace when (Contd.)TriggerEn && PwrEvtEn is True
&& 
FilterEnDetails PacketsVol. 3C 33-81INTEL® PROCESSOR TRACE
33.8 SOFTWARE CONSIDERATIONS
33.8.1 Tracing SMM Code
Nothing prevents an SMM handler from configuring and enabli ng packet generation for its own use. As described in 
Section Section 33.2.9.3, SMI will always clear TraceEn, so  the SMM handler would have to set TraceEn in order to 
enable tracing. There are some unique aspects and guid elines involved with tracing SMM code, which follow:
1. SMM should save away the existing values of any conf iguration MSRs that SMM intends to modify for tracing.
This will allow the non-SMM tracing context to be restored before RSM. 
2. It is recommended that SMM wait until it sets CSbase to 0 before enabling packet generation, to avoid possible 
LIP vs RIP confusion. 
3. Packet output cannot be directed to SMRR memory, even while tracing in SMM. 4. Before performing RSM, SMM should take care to rest ore modified configuration MSRs to the values they had 
immediately after #SMI. This involves first disabling pack et generation by clearing TraceEn, then restoring any 
other configuration MSRs that were modified. 
5. RSM
— Software must ensure that TraceEn=0 at the time of RSM. Tracing RSM is not a supported usage model, and 
the packets generated by RSM are undefined.
— For processors on which Intel PT and LBR use are mutually exclusive (see Section 33.3.1.2), any RSM 
during which TraceEn is restored to 1 will suspend any LBR or BTS logging.
33.8.2 Cooperative Transition of Multiple Trace Collection Agents

5. RSM
A third-party trace-collection tool should take into consideration the fact that it may be deployed on a processor 
that supports Intel PT but may run under any operating system. 
In such a deployment scenario, Intel recommends that tool agents follow similar principles of cooperative transition 
of single-use hardware resources, similar to how perf ormance monitoring tools handle performance monitoring 
hardware:
•Respect the “in-use” ownership of an agent who already configured the trace configuration MSRs, see architec-
tural MSRs with the prefix “IA32_RTIT_” in Chapter 2, “Model-Specific Registers (MSRs)‚” in the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 4, where “in-use” can be determined by reading the “enable bits” in the configuration MSRs.
•Relinquish ownership of the trace configuration MSRs by  clearing the “enabled bits” of those configuration 
MSRs.
33.8.3 Tracking Time 
This section describes the relationships of several clock counters whose update frequencies reside in different 
domains that feed into the timing packets. To track time, the decoder also needs to know the regularity or irregu-
larity of the occurrences of various timing packets that store those clock counters. 
Intel PT provides time information for three different but related domains:22 STI/CLI/POPF 1 1 Assu mes a change to 
RFLAGS.IF.MODE.Exec, FUP(CLIP)Table 33-59. Event Trace Exam ples when TriggerEn && ContextEn && EventEn is True
AfterDetails Packets33-82 Vol. 3CINTEL® PROCESSOR TRACE
•Processor timestamp counter
This counter increments at the max non-turbo or P1 fr equency, and its value is returned on a RDTSC. Its
frequency is fixed. The TSC packet holds the lower 7 bytes of the timestamp counter value. The TSC packet
occurs occasionally and are much less frequent than th e frequency of the time stamp counter. The timestamp
counter will continue to increment when the processor is  in deep C-States, with the exception of processors
reporting CPUID.80000007H:EDX.InvariantTSC[bit 8] =0.
•Core crystal clock 
The ratio of the core crystal clock to timestamp counter  frequency is known as P, and can be calculated as
CPUID.15H:EBX[31:0] / CPUID.15H:EAX[31:0]. The freque ncy of the core crystal clock is fixed and lower
than that of the timestamp counter. The periodic MT C packet is generated based on software-selected
multiples of the crystal clock frequency. The MTC packet  is expected to occur more frequently than the TSC
packet.
•Processor core clock
The processor core clock frequency can vary due to P-state and thermal conditions. The CYC packet provides
elapsed time as measured in processor core clock cycles relative to the last CYC packet. 
A decoder can use all or some combination of these packets to track time at different resolutions throughout the 
trace packets.
33.8.3.1  Time Domain Relationships
The three domains are related by the following formula:
TimeStampValue = (CoreCrystalClockValue * P) + AdjustedProcessorCycles + Software_Offset; 
The CoreCrystalClockValue, also known as the Always R unning Timer (ART) value, can provide the coarse-grained 
component of the TSC value. P, or the TSC/ART ratio, can be derived from CPUID leaf 15H, as described in Section 33.8.3.
The AdjustedProcessorCycles component provides the fine-gra ined distance from the rising edge of the last core 
crystal clock. Specifically, it is a cycle count in the same frequency as the timestamp counter from the last crystal 
clock rising edge. The value is adjusted based on the ra tio of the processor core clock frequency to the Maximum 
Non-Turbo (or P1) frequency. 
The Software_Offsets component includes software offsets that are factored into the timestamp value, such as 
IA32_TSC_ADJUST. 
33.8.3.2  Estimating TSC within Intel PT
For many usages, it may be useful to have an estimated timestamp value for all points in the trace. The formula 
provided in Section 33.8.3.1 above provides the framework for how such an estimate can be calculated from the 
various timing packets present in the trace.
The TSC packet provides the precise timestamp value at th e time it is generated; however, TSC packets are infre-
quent, and estimates of the current timestamp value based pu rely on TSC packets are likely to be very inaccurate 
for this reason. In order to get more precise timing information between TSC packets, CYC packets and/or MTC 
packets should be enabled.
MTC packets provide incremental updates of the CoreCrysta lClockValue. On processors that support CPUID leaf 
15H, the frequency of the timestamp counter and the core cr ystal clock is fixed, thus MTC packets provide a means 
to update the running timestamp estimate. Between two MT C packets A and B, the number of crystal clock cycles 
passed is calculated from the 8-bit payloads of respective MTC packets:
(CTCB - CTCA), where CTCi = MTCi[15:8] << IA32_RTIT_CTL.MTCFreq and i = A, B. 
The time from a TSC packet to the subs equent MTC packet can be calculated using the TMA packet that follows the 
TSC packet. The TMA packet provides both the crystal cloc k value (lower 16 bits, in the CTC field) and the Adjust-
edProcessorCycles value (in the FastCounter field) that can be used in the calculation of the corresponding core 
crystal clock value of the TSC packet. 
When the next MTC after a pair of TSC/TMA is seen, the number of crystal clocks passed since the TSC packet can 
be calculated by subtracting the TMA.CTC value from the time indicated by the MTCNext packet by 
CTCDelta[15:0] = (CTCNext[15:0] - TMA.CTC[15:0]), where CTCNext = MTCPayload  << IA32_RTIT_CTL.MTCFreq.Vol. 3C 33-83INTEL® PROCESSOR TRACE
The TMA.FastCounter field provides the number of Adjusted ProcessorCycles since the last crystal clock rising edge, 
from which it can be determined the percentage of the ne xt crystal clock cycle that had passed at the time of the 
TSC packet. 
CYC packets can provide further precision of an estimated timestamp value to many non-timing packets, by 
providing an indication of the time passed between other timing packets (MTCs or TSCs). 
When enabled, CYC packets are sent preceding each CYC- eligible packet, and provide the number of processor 
core clock cycles that have passed since the last CYC packet. Thus between MTCs and TSCs, the accumulated CYC 
values can be used to estimate the AdjustedProcessorC ycles component of the timestamp value. The accumulated 
CPU cycles will have to be adjusted to account for the difference in frequency between the processor core clock and 
the P1 frequency. The necessary adjustment can be esti mated using the core:bus ratio value given in the CBR 
packet, by multiplying the accumulated cycle count value by P1/CBRpayload . 
Note that stand-alone TSC packets (that is, TSC packets that  are not a part of a PSB+) are typically generated only 
when generation of other timing packets (MTCs and CYCs ) has ceased for a period of time. Example scenarios 
include when Intel PT is re-enabled, or on wake after a sl eep state. Thus any calculated estimate of the timestamp 
value leading up to a TSC packet will likely result in a discrepancy, which the TSC packet serves to correct.
A greater level of precision may be achieved by calculating the CPU clock frequency, see Section 33.8.3.4 below for 
a method to do so using Intel PT packets. 
CYCs can be used to estimate time between TSCs even with out MTCs, though this will likely result in a reduction in 
estimated TSC precision.
33.8.3.3  VMX TSC Manipulation
When software executes in non-Root operation, additional offset and scaling factors may be applied to the TSC value. These are optional, but may be enabled via VMCS controls on a per-VM basis. See Chapter 26, “VMX Non-
Root Operation‚” for details on VMX TSC offsetting and TSC scaling.
Like the value returned by RDTSC, TSC packets will include these adjustments, but other timing packets (such as 
MTC, CYC, and CBR) are not impacted. In order to use the algorithm above to estimate the TSC value when TSC scaling is in use, it will be necessary for software to account for the scaling factor. See Section 33.5.2.4 for details.
33.8.3.4  Calculating Frequency with Intel PT
Because Intel PT can provide both wall-clock time and processor clock cycle time, it can be used to measure the processor core clock frequency. Either TSC or MTC packets can be used to track the wall-clock time. By using CYC 
packets to count the number of processor core cycles that pass in between a pair of wall-clock time packets, the 
ratio between processor core clock frequency and TSC freque ncy can be derived. If the P1 frequency is known, it 
can be applied to determine the CPU frequency. See Sectio n 33.8.3.1 above for details on the relationship between 
TSC, MTC, and CYC.33-84 Vol. 3CINTEL® PROCESSOR TRACEVol. 3D 34-1INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
CHAPTER 34
34.1 OVERVIEW

CHAPTER 34
Intel® Software Guard Extensions (Intel® SGX) is a set of instructions and mechanisms for memory accesses 
added to Intel® Architecture processors. Intel SGX can encompass two collections of instruction extensions, 
referred to as SGX1 and SGX2, see Table 34-1 and Table 34-2.  The SGX1 extensions allow an application to instan-
tiate a protected container, referred to as an enclave. The enclave is a trusted area of memory, where critical 
aspects of the application functionality have hardware-e nhanced confidentiality and integrity protections. New 
access controls to restrict access to software not resident in the enclave are also introduced. The SGX2 extensions 
allow additional flexibility in runtime management of en clave resources and thread execution within an enclave.
Chapter 35 covers main concepts, objects and data struct ure formats that interact within the Intel SGX architec-
ture. Chapter 36 covers operational as pects ranging from preparing an enclave, transferring control to enclave 
code, and programming considerations for the enclave co de and system software providing support for enclave 
execution. Chapter 37 describes the behavior of Asyn chronous Enclave Exit (AEX) caused by events while 
executing enclave code. Chapter 38 covers the syntax and op erational details of the instruction and associated leaf 
functions available in Intel SGX. Chapter 39 describes  interaction of various aspects of IA32 and Intel® 64 archi-
tectures with Intel SGX. Chapter 40 covers Intel SGX support for application debug, profiling, and performance 
monitoring.
34.2 ENCLAVE INTERACTION AND PROTECTION
Intel SGX allows the protected portion of an application to be  distributed in the clear. Before the enclave is built, the 
enclave code and data are free for inspection and analysis . The protected portion is loaded into an enclave where 
its code and data is measured. Once the application’s prot ected portion of the code and data are loaded into an 
enclave, memory access controls are in place to restrict access by external software. An enclave can prove its iden-
tity to a remote party and provide the necessary building-b locks for secure provisioning of keys and credentials. 
The application can also request an enclave-specific and platform-specific key that it can use to protect keys and 
data that it wishes to store outside the enclave.1Figure 34-1.  An Enclave Within th e Application’s Virtual Address Space
1. For additional information, see white papers on Intel SGX at https://www.intel.com/content/www /us/en/developer/tools/isa-exten-
sions/overview.html .OS
App Code
App CodeEntry TableEnclave
Enclave Heap
Enclave Stack
Enclave Code34-2 Vol. 3DINTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
Intel SGX introduces two significant ca pabilities to the Intel Architecture. First is the change in enclave memory 
access semantics. The second is protection of the address mappings  of the application.
34.3 ENCLAVE LIFE CYCLE 
Enclave memory management is divided into two part s: address space allocation and memory commitment. 
Address space allocation is the specification of the range of linear addresses that the enclave may use. This range 
is called the ELRANGE. No actual resources are committe d to this region. Memory commitment is the assignment 
of actual memory resources (as pages) within the alloca ted address space. This two-phase technique allows flexi-
bility for enclaves to control their memory usage and to  adjust dynamically without overusing memory resources 
when enclave needs are low. Commitment adds physical pa ges to the enclave. An operating system may support 
separate allocate and commit operations. 
During enclave creation, code and data for an enclave are loaded from a clear-text source, i.e., from non-enclave 
memory.
Untrusted application code starts using an initialized encl ave typically by using the EEN TER leaf function provided 
by Intel SGX to transfer control to the enclave code re siding in the protected Enclave Page Cache (EPC). The 
enclave code returns to the caller via the EEXIT leaf functi on. Upon enclave entry, control is transferred by hard-
ware to software inside the enclave. The software inside  the enclave switches the stack pointer to one inside the 
enclave. When returning back from th e enclave, the software swaps back the stack pointer then executes the 
EEXIT leaf function.
On processors that support the SGX2 extensions, an encl ave writer may add memory to an enclave using the SGX2 
instruction set, after the enclave is built and running. Thes e instructions allow adding additional memory resources 
to the enclave for use in such areas as the heap. In a ddition, SGX2 instructions allow the enclave to add new 
threads to the enclave. The SGX2 features provide addition al capabilities to the software model without changing 
the security properties of the Intel SGX architecture. 
Calling an external procedure from an enclave could be done using the EEXIT leaf function. Software would use 
EEXIT and a software convention between th e trusted section and the untrusted section.
An active enclave consumes resources from the Enclave Page Cache (EPC, see Section 34.5). Intel SGX provides 
the EREMOVE instruction that an EPC manager can use to  reclaim EPC pages committed to an enclave. The EPC 
manager uses EREMOVE on every enclave page when the enclave is torn down. After successful execution of 
EREMOVE the EPC page is available for allocation to another enclave.
34.4 DATA STRUCTURES AND ENCLAVE OPERATION
There are 2 main data structures associated with operat ing an enclave, the SGX Encl ave Control Structure (SECS, 
see Section 35.7) and the Thread Control Structure (TCS, see Section 35.8). 
There is one SECS for each enclave. The SECS contains me ta-data about the enclave which is used by the hardware 
and cannot be directly accessed by software. Included in the SECS is a field that stores the enclave build measure-
ment value. This field, MRENCLAVE, is initialized by  the ECREATE instruction and updated by every EADD and 
EEXTEND. It is locked by EINIT. 
Every enclave contains one or more TCS structures. The TCS contains meta-data used by the hardware to save and 
restore thread specific information when entering/exiting  the enclave. There is one field, FLAGS, that may be 
accessed by software. This field can only be accessed by de bug enclaves. The flag bit, DBGOPTIN, allows to single 
step into the thread associated with the TCS. (see Section 35.8.1)
The SECS is created when ECREATE (see Table 34-1) is ex ecuted. The TCS can be crea ted using the EADD instruc-
tion or the SGX2 instructions (see Table 34-2). 
34.5 ENCLAVE PAGE CACHE
The Enclave Page Cache (EPC) is the secure storage used  to store enclave pages when they are a part of an 
executing enclave. For an EPC page, hardware performs additional access control checks to restrict access to the page. After the current page access checks and translations  are performed, the hardware checks that the EPC page Vol. 3D 34-3INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
is accessible to the program currently executing. Genera lly an EPC page is only a ccessed by the owner of the 
executing enclave or an instruction which is setting up an EPC page
The EPC is divided into EPC pages. An EPC page is 4KB in size and always aligned on a 4KB boundary. 
Pages in the EPC can either be valid or invalid. Every valid  page in the EPC belongs to one enclave instance. Each 
enclave instance has an EPC page that holds its SECS. The security metadata for each EPC page is held in an 
internal micro-architectural structure called Encl ave Page Cache Map (EPCM, see Section 34.5.1).
The EPC is managed by privileged soft ware. Intel SGX provides a set of instructions for adding and removing 
content to and from the EPC. The EPC may be configured by BIOS at boot time. On implementations in which EPC 
memory is part of system DRAM, the contents of  the EPC are protected by an encryption engine. 
34.5.1 Enclave Page Cache Map (EPCM)
The EPCM is a secure structure used by the processor to track the contents of the EPC. The EPCM holds one entry 
for each page in the EPC. The format of the EPCM is micro-architectural, and consequently is implementation 
dependent. However, the EPCM contains the following architectural information:
•The status of EPC page with respect to validity and accessibility.
•An SECS identifier (see Section 35.20) of  the enclave to which the page belongs. 
•The type of page: regular, SECS, TCS or VA.
•The linear address through which the enclave is allowed to access the page.
•The specified read/write/execute permissions on that page. 
The EPCM structure is used by the CPU in the address-translation flow to enforce access-control on the EPC pages. 
The EPCM structure is described in Table 35-29, and the conceptual access-control flow is described in Section 
35.5.
The EPCM entries are managed by the processo r as part of various instruction flows. 
34.6 ENCLAVE INSTRUCTIONS AND INTEL® SGX
The enclave instructions available with Intel SGX are organized as leaf functions under three instruction

35.5.
The enclave instructions available with Intel SGX are organized as leaf functions under three instruction 
mnemonics: ENCLS (ring 0), ENCLU (ring 3), and ENCLV (VT ro ot mode). Each leaf function uses EAX to specify the 
leaf function index, and may require additional implicit input registers as parameters. The use of EAX is implied 
implicitly by the ENCLS, ENCLU, and ENCLV instructions; ModR/M byte encoding is not used with ENCLS, ENCLU, 
and ENCLV. The use of additional registers does not use ModR /M encoding and is implied implicitly by the respective 
leaf function index.
Each leaf function index is also associated with a uniqu e, leaf-specific mnemonic. A long-form expression of Intel 
SGX instruction takes the form of ENCLx[LEAF_MNEMONIC], wher e ‘x’ is either ‘S’, ‘U’, or ‘V’. The long-form expres-
sion provides clear association of the privilege-level re quirement of a given “leaf mnemonic”. For simplicity, the 
unique “Leaf_Mnemonic” name is used (omitting the EN CLx for convenience) throughout in this document. 
Details of individual SGX leaf functions are described in Chapter 38. Table 34-1 provides a summary of the instruc-
tion leaves that are available in the in itial implementation of Intel SGX, whic h is introduced in the 6th generation 
Intel Core processors. Table 34-2 summarizes enha ncement of Intel SGX for future Intel processors.
Table 34-1.  Supervisor and User  Mode Enclave Instruction Leaf Functions in Long-Form of SGX1
ENCLS[EADD] Add an EPC page to an en clave. ENCLU[EENTER] Enter an enclave.
ENCLS[EBLOCK] Block an EPC page. ENCLU[EEXIT] Exit an enclave.ENCLS[ECREATE] Create an enclave. ENCLU[EGETKEY] Create a cryptographic key.ENCLS[EDBGRD] Read data from a debug enclave by debug-
ger.ENCLU[EREPORT] Create a cryptographi c report.34-4 Vol. 3DINTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
34.7 DISCOVERING SUPPORT FOR IN TEL® SGX AND ENABLING ENCLAVE 
INSTRUCTIONS
Detection of support of Intel SGX and enumeration of av ailable and enabled Intel SGX resources are queried using 
the CPUID instruction. The enumeration interface comprises the following:
•Processor support of Intel SGX is enumerated by a feature flag in CPUID leaf 07H: CPUID.(EAX=07H, 
ECX=0H):EBX.SGX[bit 2]. If CPUID. (EAX=07H, ECX=0H):EBX.SGX  = 1, the processor has support for Intel 
SGX, and requires opt-in enabling by BIOS via IA32_FEATURE_CONTROL MSR. 
If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, CPUID will report via the available sub-leaves of
CPUID.(EAX=12H) on available and/or  configured Intel SGX resources.
•The available and configured Intel SGX resources enumer ated by the sub-leaves of  CPUID.(EAX=12H) depend 
on the state of BIOS configuration.ENCLS[EDBGWR] Write data into a debug enclave by debug-
ger.ENCLU[ERESUME] Re-enter an enclave.
ENCLS[EEXTEND] Extend EPC page measurement.
ENCLS[EINIT] Initialize an enclave.ENCLS[ELDB] Load an EPC page in blocked state.ENCLS[ELDU] Load an EPC page in unblocked state.ENCLS[EPA] Add an EPC page to create a version array.ENCLS[EREMOVE] Remove an EPC page from an enclave.ENCLS[ETRACK] Activate EBLOCK checks.ENCLS[EWB] Write back/invalidate an EPC page.
Table 34-2.  Supervisor and User Mode Enclave Instruction Le af Functions in Long-Form of SGX2
ENCLS[EAUG] Allocate EPC page to an existing encl ave. ENCLU[EACCEPT] Accept EPC page into the enclave.
ENCLS[EMODPR] Restrict page permissions. ENCLU[EMODPE] Enhance page permissions.ENCLS[EMODT] Modify EPC page type. ENCLU[EACCE PTCOPY] Copy contents to an augmented EPC 
page and accept the EPC page into 
the enclave.
Table 34-3.  VMX Operation and Supervisor Mode Enclav e Instruction Leaf Function s in Long-Form of OVERSUB
VMX Operation Description Superv isor Instruction Description
ENCLV[EDECVIRTCHILD] Decrement the vi rtual child page count. ENCLS[ERDINFO] Read information about EPC page.
ENCLV[EINCVIRTCHILD] Increment the virtua l child page count. ENCLS[ETRACKC] Activate EBLOCK checks with conflict 
reporting.
ENCLV[ESETCONTEXT] Set virtualization context. EN CLS[ELDBC/UC] Load an EPC page with conflict 
reporting.Table 34-1.  Supervisor and User  Mode Enclave Instru ction Leaf Functions in Long-Form of SGX1
Supervisor Instruction Descripti on User Instruction DescriptionVol. 3D 34-5INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
34.7.1 Intel® SGX Opt-In Configuration
On processors that support Intel SGX, IA32_FEATURE_CON TROL provides the SGX_ENABLE field (bit 18). Before 
system software can configure and enable Inte l SGX resources, BIOS is required to set 
IA32_FEATURE_CONTROL.SGX_ENABLE = 1 to opt-in  the use of Intel SGX by system software.
The semantics of setting SGX_ENABLE follows the rules of IA32_FEATURE_CONTROL.LOCK (bit 0). Software is 
considered to have opted into Intel SGX if an d only if IA32_FEATURE_CONTROL.SGX_ENABLE and 
IA32_FEATURE_CONTROL.LOCK are set to 1. The setting of IA32_FEATURE_CONTROL.SGX_ENABLE (bit 18) is not 
reflected by CPUID.
34.7.2 Intel® SGX Resource Enumeration Leaves
If CPUID.(EAX=07H, ECX=0H):E BX.SGX = 1, the processor also supports  querying CPUID with EAX=12H on Intel 
SGX resource capability and configuration. The number of available sub-leaves in leaf 12H depends on the Opt-in 
and system software configuration. Information returned by CPUID.12H is thread spec ific; software should not 
assume that if Intel SGX instructions are supported on one hardware thread, they are also supported elsewhere. 
A properly configured processor exposes Intel SGX functi onality with CPUID.EAX=12H reporting valid information 
(non-zero content) in three or more sub-leaves, see Table 34-5.
•CPUID.(EAX=12H, ECX=0H) enumerates Intel SGX capabi lity, including enclave instruction opcode support.
•CPUID.(EAX=12H, ECX=1H) enumerates Intel SGX capabi lity of processor state configuration and enclave 
configuration in the SECS structure (see Table 35-3).
•CPUID.(EAX=12H, ECX >1) enumerates available EPC resources.Table 34-4.  Intel® SGX Opt-in and Enabling Behavior
CPUID.(07H,0H):EBX.
SGXCPUID.(12H)FEATURE_CONTROL.
LOCKFEATURE_CONTROL.
SGX_ENABLEEnclave Instruction
0 I n v a l i d XX# U D
1 V a l i d * XX# U D * *1V a l i d * 0X # G P1V a l i d * 10# G P1 Valid* 1 1 Available (see Table 34-5 for details 
of SGX1 and SGX2).
* Leaf 12H enumeration results are dependent on enablement.
** See list of conditions in the #UD section of the reference pages of ENCLS and ENCLU
Table 34-5.  CPUID Leaf 12H, Sub-Leaf 0 Enumeration of Intel® SGX Capabilities
CPUID.(EAX=12H,ECX=0) Description Behavior
EAX 0 SGX1: If 1, indicates leaf functions of SGX1  instruction listed in Table 34-1 are supported.
1 SGX2: If 1, indicates leaf f unctions of SGX2 instruction listed in Table 34-2 are supported.
4:2 Reserved (0)
5 OVERSUB: If 1, indicates Intel SGX supports instructions: EINC VIRTCHILD, EDEC VIRTCHILD, and 
6 OVERSUB: If 1, indicates Intel SGX supports instructions: ETRACKC, ERDINFO, ELDBC, and ELDUC.
31:7 Reserved (0)
EBX31:0 MISCSELECT: Reports the bit vector of supported ex tended features that can be written to the MISC 
region of the SSA.
ECX 31:0 Reserved (0).34-6 Vol. 3DINTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
On processors that support Intel SGX1 and SGX2, CPUID leaf 12H sub-leaf 2 report physical memory resources 
available for use with Intel SGX. These physical me mory sections are typically allocated by BIOS as Processor 
Reserved Memory , and available to the OS to manage as EPC. 
To enumerate how many EPC sections are available to the EPC manager, software can enumerate CPUID leaf 12H 
with sub-leaf index starting from 2, and decode the sub-leaf-type encoding (returned in EAX[3:0]) until the sub-
leaf type is invalid. All invalid sub-leaves of  CPUID leaf 12H return EAX/EBX/ECX/EDX with 0.EDX7:0 MaxEnclaveSize_Not64: the maximum supported enclav e size is 2^(EDX[7:0]) bytes when not in 64-bit 
mode.
15:8 MaxEnclaveSize_64: the maximum supported enclave size is 2^(EDX[15:8]) bytes when operating in 64-
bit mode.
31:16 Reserved (0).
Table 34-6.  CPUID Leaf 12H, Sub-Leaf 1 Enumeration of Intel® SGX Capabilities
CPUID.(EAX=12H,ECX=1) D escription Behavior
EAX 31:0 Report the valid bits of  SECS.ATTRIBUTES[31:0] that so ftware can set with ECREATE. 
SECS.ATTRIBUTES[n] can be set to 1 using ECRE ATE only if EAX[n] is 1, where n < 32.
EBX 31:0 Report the valid bits of  SECS.ATTRIBUTES[63:32] that so ftware can set with ECREATE. 
SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE only if EBX[n] is 1, where n < 32.
ECX 31:0 Report the valid bits of SECS.ATTRIBUTES [95:64] that software can set with ECREATE. 
SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE only if ECX[n] is 1, where n < 32.
EDX 31:0 Report the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE. 
SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE only if EDX[n] is 1, where n < 32.
Table 34-7.  CPUID Leaf 12H, Sub-Leaf Index 2 or Higher Enumeration of Intel® SGX Resources

bit mode.
CPUID.(EAX=12H,ECX > 1) Description Behavior
EAX 3:0 0000b: This sub-leaf is invalid; EDX:ECX:EBX:EAX return 0.
Enclave Page Cache (EPC) section.
11:4 Reserved (enumerate 0).
31:12 If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of the base of the EPC section.
EBX19:0 If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of the base of the EPC section.
31:20 Reserved.
ECX3: 0 If ECX[3:0] = 0000b, then all bits of the EDX:ECX pair are enumerated as 0.
If ECX[3:0] = 0001b, then this section has confidentiality and integrity protection.
If ECX[3:0] = 0010b, then this section has confidentiality protection only.All other encodings are reserved.
11:4 Reserved (enumerate 0).31:12 If EAX[3:0] = 0001b, these are bits 31:12 of the size of the corresponding EPC section within the 
Processor Reserved Memory.Table 34-5.  CPUID Leaf 12H, Sub-Leaf 0 Enumeration of Intel® SGX Capabilities
CPUID.(EAX=12H,ECX=0) D escription Behavior
Register BitsVol. 3D 34-7INTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
34.8 INTEL® SGX INTERACTIONS WITH CONTROL-FLOW ENFORCEMENT 
This section discusses extensions to th e Intel SGX architecture to support CET.
34.8.1 CET in Enclaves Model
Each enclave has its private configuration for CET that is not shared with the CET configurations of the enclosing 
application. On entry into the enclave, the CET state of the enclosing application is saved into scratchpad registers 
inside the processor and the CET state of the enclave is established. On an asynchronous exit, the enclave CET 
state is saved into the enclave state save area frame. On  exit from the enclave, th e CET state of the enclosing 
application is re-established from the scratchpad registers.
A new page type, PT_SS_FIRST, is used to denote pages in an enclave that can be used as a first page of a shadow 
stack.
A new page type, PT_SS_REST, is used to denote pages in an enclave that can be used as a non-first page of a 
shadow stack.
A page denoted as PT_SS_FIRST and PT_SS_REST will be a legal target for shadow_stack_load, 
shadow_stack_store, and regular load operations. Re gular stores will be disallowed to such pages. A 
PT_SS_FIRST/PT_SS_REST page must be writ eable in the IA page tables and in EPT.
When in enclave mode, shadow_stack_load and shadow_sta ck_store operations must be to addresses in the 
enclave ELRANGE.
The EAUG instruction is extended to allocate pages of type PT_SS_FIRST/PT_SS_REST; this page type requires 
specifying a SECINFO structure with page parameters. Shadow page permission must be R/W. Regular R/W pages may continue to be allocated by providing a SECINFO poin ter value of 0. Regular R/W pages may also be allocated 
by providing a SECINFO structure that specifies the pa ge parameters. The EAUG instruction creates a shadow-
stack-restore token at offset 0xFF8 on a PT_SS_FIRST page . This allows a dynamically created shadow stack to be 
restored using the RSTORSSP instructio n. The EADD and EAUG instructions disallow creation of a PT_SS_FIRST or 
PT_SS_REST page as the first or last page in ELRANGE.
The EADD instruction requires that the PT_SS_REST page  be all zeroes. The EADD instruction requires that a 
PT_SS_FIRST page be all zeroes except the 8 bytes at offs et 0xFF8 on that page that must have a shadow-stack-
restore token. This shadow-stack-restore token must have a linear address which is the linear address of the 
PT_SS_FIRST page + 4096. As an enclave could be loaded at varying linear addresses, the enclave builder should 
not extend the measurement of the PT_SS_FIRST pages into  the measurement registers. On first entry on to the 
enclave using a TCS, the enclave software can use the RS TORSSP instruction to restore its SSP. Subsequent to 
performing a RSTORSSP, the enclave software can use the INCSSP instruction to pop the previous-ssp token that 
is created by the RSTORSSP instruction at the top of the restored shadow stack.
On an enclave entry, the SSP will be initialized to the va lue in a new TCS field called PREVSSP. The PREVSSP field is 
written with the value of SSP on enclav e exit and is loaded into SSP at encl ave entry. When a TCS page is added 
using EADD or accepted using EACCEPT, the processor requires the PREVSSP field to be initialized to 0.EDX 19: 0 If EAX[3:0] = 0001b, these are bits 51:32 of the size of the corresponding EPC section within the 
Processor Reserved Memory.
31:20 Reserved.Table 34-7.  CPUID Leaf 12H, Sub-Leaf Index 2 or Higher Enumeration of Intel® SGX Resources
Register Bits34-8 Vol. 3DINTRODUCTION TO INTEL® SOFTWARE GUARD EXTENSIONS
34.8.2 Operations Not Suppor ted on Shadow Stack Pages
The following operations are not allowed on pages of type PT_SS_FIRST and PT_SS_REST:
•EACCEPTCOPY
•EMODPR
•EMODPE
34.8.3 Indirect Branch Tracking – Legacy Compatibility Treatment
The legacy code page bitmap is tested using the page offset within the ELRANGE instead of the absolute linear 
address of the address where ENDBRANCH was missed; see the detailed algorithm in Section 17.3.6, “Legacy 
Compatibility Treatment,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for 
additional details.Vol. 3D 35-1ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
CHAPTER 35
35.1 OVERVIEW OF ENCLAV E EXECUTION ENVIRONMENT
When an enclave is created, it has a range of linear addresses to which the processor applies enhanced access 
control. This range is called the ELRANGE (see Section 34.3). When an enclave generates a memory access, the 
existing IA32 segmentation and paging  architecture are applied. Additiona lly, linear addresses inside the ELRANGE 
must map to an EPC page otherwise when an enclave atte mpts to access that linear address a fault is generated.
The EPC pages need not be physically contiguous. Syst em software allocates EPC pages to various enclaves. 
Enclaves must abide by OS/VMM imposed segmentation and paging policies. OS/VMM-managed page tables and extended page tables provide address translation for the enclave pages. Hardware requ ires that these pages are 
properly mapped to EPC (any failure generates an exception).
Enclave entry must happen throug h specific enclave instructions:
•ENCLU[EENTER], ENCLU[ERESUME].
Enclave exit must happen through spec ific enclave instructions or events:
•ENCLU[EEXIT], Asynchronous Enclave Exit (AEX).
Attempts to execute, read, or write to linear addresses ma pped to EPC pages when not inside an enclave will result 
in the processor altering the access to preserve the confid entiality and integrity of the enclave. The exact behavior 
may be different between implementations. As an example a re ad of an enclave page may result in the return of all 
one's or return of cyphertext of the cache line. Writing to an enclave page may result in a dropped write or a 
machine check at a later time. The processor will provide the protections as described in Section 35.4 and Section 
35.5 on such accesses.
35.2 TERMINOLOGY
A memory access to the ELRANGE and initiated by an instruct ion executed by an enclave is called a Direct Enclave 
Access (Direct EA). 
Memory accesses initiated by certain Intel® SGX instruction leaf functions such as ECREATE, EADD, EDBGRD, 
EDBGWR, ELDU/ELDB, EWB, EREMOVE, EE NTER, and ERESUME to EPC pages are called Indirect Enclave Accesses 
(Indirect EA). Table 35-1 lists additional details of the indirect EA of SGX1 and SGX2 extensions.
Direct EAs and Indirect EAs together are called Enclave Accesses (EAs). Any memory access that is not an Enclave Access is called a non-enclave access. 
35.3 ACCESS-CONTROL REQUIREMENTS
Enclave accesses have the following access-control attributes:
•All memory accesses must conform to segmentation and paging protection mechanisms.
•Code fetches from inside an enclave to a linear addres s outside that enclave result in a #GP(0) exception. 
•Shadow-stack-load or shadow-stack-store from inside an enclave to a linear address outside that enclave 
results in a #GP(0) exception.
•Non-enclave accesses to EPC memory result in undefine d behavior. EPC memory is protected as described in 
Section 35.4 and Section 35.5 on such accesses.
•EPC pages of page types PT_REG, PT_TCS, and PT_TRIM must be mapped to ELRANGE at the linear address 
specified when the EPC page was allocated to the encl ave using ENCLS[EADD] or ENCLS[EAUG] leaf functions. 
Enclave accesses through other linear address re sult in a #PF with the PFEC.SGX bit set. 35-2 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
•Direct EAs to any EPC pages must conform to the currently  defined security attributes for that EPC page in the 
EPCM. These attributes may be defined at enclave creati on time (EADD) or when the enclave sets them using

EPCM. These attributes may be defined at enclave creati on time (EADD) or when the enclave sets them using 
SGX2 instructions. The failure of these checks results in a #PF with the PFEC.SGX bit set.
— Target page must belong to the currently executing enclave.— Data may be written to an EPC pa ge if the EPCM allow write access.
— Data may be read from an EPC page if the EPCM allow read access.
— Instruction fetches from an EPC page are allowed if the EPCM allows execute access.— Shadow-stack-load from an EPC page and shadow-stack-s tore to an EPC page are allowed only if the page 
type is PT_SS_FIRST or PT_SS_REST.
— Data writes that are not shadow-stack-store are not allowed if the EPCM page type is PT_SS_FIRST or 
PT_SS_REST.
— Target page must not have a restricted page type
1 (PT_SECS, PT_TCS, PT_VA, or PT_TRIM).
— The EPC page must not be BLOCKED. 
— The EPC page must not be PENDING. — The EPC page must not be MODIFIED. 
35.4 SEGMENT-BASED ACCESS CONTROL
Intel SGX architecture does not modify the segment checks  performed by a logical processor. All memory accesses 
arising from a logical processor in protected mode (inclu ding enclave access) are subject to segmentation checks 
with the applicable segment register. 
To ensure that outside entities do not modify the enclav e's logical-to-linear address translation in an unexpected 
fashion, ENCLU[EENTER] and ENCLU[ERESUME] check that CS, DS, ES, and SS, if usable (i.e., not null), have 
segment base value of zero. A non-zero segment base value for these registers results in a #GP(0).
On enclave entry either via EENTER or ERESUME, the proces sor saves the contents of the external FS and GS regis-
ters, and loads these registers with values stored in the TC S at build time to enable the enclave’s use of these regis-
ters for accessing the thread-local storage inside the enclav e. On EEXIT and AEX, the contents at time of entry are 
restored. On AEX, the values of FS an d GS are saved in the SSA frame. On ER ESUME, FS and GS are restored from 
the SSA frame. The details of these operations can be found in the descriptions of EENTER, ERESUME, EEXIT, and 
AEX flows.
35.5 PAGE-BASED ACCESS CONTROL
35.5.1 Access-control for Accesses that  Originate from Non-SGX Instructions
Intel SGX builds on the processor's paging mechanism to provide page-granular access-control for enclave pages. 
Enclave pages are designed to be accessible only from inside  the currently executing enclav e if they belong to that 
enclave. In addition, enclave accesses must conform to th e access control requirements described in Section 35.3. 
or through certain Intel SGX instructions. Attempts to exec ute, read, or write to linear addresses mapped to EPC 
pages when not inside an enclave will result in the processor altering the access to preserve the confidentiality and 
integrity of the enclave. The exact behavior  may be different between implementations.
35.5.2 Memory Accesses that Split Across ELRANGE
Memory data accesses are allowed to split across ELRANGE (i .e., a part of the access is inside ELRANGE and a part 
of the access is outside ELRANGE) while the processor is in side an enclave. If an access splits across ELRANGE, the 
1. EPCM may allow write, read or execute access only for pages with page type PT_REG.Vol. 3D 35-3ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
processor splits the access into two sub-accesses (one in side ELRANGE and the other outside ELRANGE), and each 
access is evaluated. A code-fetch access that splits acro ss ELRANGE results in a #GP due to the portion that lies 
outside of the ELRANGE.
35.5.3 Implicit vs. Explicit Accesses
Memory accesses originating from Intel SGX instruction leaf functions are categorized as either explicit accesses or 
implicit accesses. Table 35-1 lists the implicit and exp licit memory accesses made by Intel SGX leaf functions.
35.5.3.1  Explicit Accesses
Accesses to memory locations provided as explicit operands  to Intel SGX instruction leaf functions, or their linked 
data structures are called explicit accesses. 
Explicit accesses are always made using logical addresse s. These accesses are subject to segmentation, paging, 
extended paging, and APIC-virtualizatio n checks, and trigger any faults/exit associated with these checks when the 
access is made.
The interaction of explicit memory accesses with data brea kpoints is leaf-function-specific, and is documented in 
Section 40.3.4.
35.5.3.2  Implicit Accesses
Accesses to data structures whose physical addresses are cached by the processor are called implicit accesses. 
These addresses are not passed as operands of the inst ruction but are implied by use of the instruction. 
These accesses do not trigger any access-control faults/exits  or data breakpoints. Table 35-1 lists memory objects 
that Intel SGX instruction leaf functions access either by ex plicit access or implicit access. The addresses of explicit 
access objects are passed via register operands with the second through fourth column of Table 35-1 matching implicitly encoded regi sters RBX, RCX, RDX.
Physical addresses used in different implicit accesses are cached via different instructions and for different dura-
tions. The physical address of SECS associated with each EPC page is cached at the time the page is added to the 
enclave via ENCLS[EADD] or ENCLS[EAUG], or when the pa ge is loaded to EPC via ENCLS[ELDB] or ENCLS[ELDU]. 
This binding is severed when the corresponding page  is removed from the EPC via ENCLS[EREMOVE] or 
ENCLS[EWB]. Physical addresses of TCS and SSA pages are cached at the time of most-recent enclave entry. Exit 
from an enclave (ENCLU[EEXIT] or AEX) flushes this cachin g. Details of Asynchronous Enclave Exit is described in 
Chapter 37.
The physical addresses that are cached for use by implic it accesses are derived from logical (or linear) addresses 
after checks such as segmentation, paging, EPT, and APIC  virtualization checks. These checks may trigger excep-
tions or VM exits. Note, however, that such exception or VM exits may not occur after a physical address is cached 
and used for an implicit access. 
Table 35-1.  List of Implicit and Explicit Me mory Access by Intel® SGX Enclave Instructions
Instr. Leaf Enum. Explicit 1 Explicit 2 Explicit 3 Implicit 
EACCEPT SGX2 SECINFO EPCPAGE SECSEACCEPTCOPY SGX2 SECINFO EPCPAGE (Src) EPCPAGE (Dst)EADD SGX1 PAGEINFO and linked structures EPCPAGEEAUG SGX2 PAGEINFO and linked structures EPCPAGE SECSEBLOCK SGX1 EPCPAGE SECSECREATE SGX1 PAGEINFO and linked structures EPCPAGEEDBGRD SGX1 EPCADDR Destination SECSEDBGWR SGX1 EPCADDR Source SECSEDECVIRTCHILD OVERSUB EPCPAGE SECSEENTER SGX1 TCS and linked SSA SECS35-4 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.6 INTEL® SGX DATA  STRUCTURES OVERVIEW
Enclave operation is managed via a collection of data structures. Many of the top-level data structures contain sub-
structures. The top-level data structures relate to parame ters that may be used in enclave setup/maintenance, by 
Intel SGX instructions, or AEX event. The top-level data structures are:
•SGX Enclave Control Structure (SECS)
•Thread Control Structure (TCS)
•State Save Area (SSA)
•Page Information (PAGEINFO)
•Security Information (SECINFO)
•Paging Crypto MetaData (PCMD)
•Enclave Signature Structure (SIGSTRUCT)
•EINIT Token Structure (EINITTOKEN)
•Report Structure (REPORT)
•Report Target Info (TARGETINFO)
•Key Request (KEYREQUEST)
•Version Array (VA)
•Enclave Page Cache Map (EPCM)
•Read Info (RDINFO)EEXIT SGX1 SECS, TCS
EEXTEND SGX1 SECS EPCPAGEEGETKEY SGX1 KEYREQUEST KEY SECSEINCVIRTCHILD OVERSUB EPCPAGE SECSEINIT SGX1 SIGSTRUCT SECS EINITTOKENELDB/ELDU SGX1 PAGEINFO and linked structures, PCMD EPCPAGE VAPAGEELDBC/ELDUC OVERSUB PAGEINFO and linked structures EPCPAGE VAPAGEEMODPE SGX2 SECINFO EPCPAGEEMODPR SGX2 SECINFO EPCPAGE SECSEMODT SGX2 SECINFO EPCPAGE SECSEPA SGX1 EPCADDRERDINFO OVERSUB RDINFO EPCPAGEEREMOVE SGX1 EPCPAGE SECSEREPORT SGX1 TARGETINFO REP ORTDATA OUTPUTDATA SECS
ERESUME SGX1 TCS and linked SSA SECSESETCONTEXT OVERSUB SECS ContextValueETRACK SGX1 EPCPAGEETRACKC OVERSUB EPCPAGEEWB SGX1 PAGEINFO and linked structures, PCMD EPCPAGE VAPAGE SECSAsynchronous Enclave Exit* SECS, TCS, 
SSA
*Details of Asynchronous Enclave Exit (AEX) is described in Section 37.4Table 35-1.  List of Implicit and Explicit Memory Access by Intel®  SGX Enclave Inst ructions (Contd.)
Instr. Leaf Enum. Explicit 1 E xplicit 2 Explicit 3 Implicit Vol. 3D 35-5ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
Details of the top-level data structures and associated sub-structures are listed in Section 35.7 through Section 
35.20.
35.7 SGX ENCLAVE CONTROL STRUCTURE (SECS)
The SECS data structure requires 4K-Bytes alignment.
Table 35-2.  Layout of SGX Enclave Control Structure (SECS)
Field OFFSET (Bytes) Size (Bytes) Description
SIZE 0 8 Size of enclave in by tes; must be power of 2.
BASEADDR 8 8 Enclave Base Linear Address must be naturally aligned to size.
SSAFRAMESIZE 16 4 Size of one SSA frame in pages, including XSAVE, pad, GPR, and MISC (if 
CPUID.(EAX=12H, ECX=0):.EBX != 0).

SSA
35.20.
MISCSELECT 20 4 Bit vector specifying which extended features are saved to the MISC region 
(see Section 35.7.2) of the SS A frame when an AEX occurs.
CET_LEG_BITMAP
_OFFSET24 8 Page aligned offset of legacy code page bitmap from enclave base. Soft-
ware is expected to prog ram this offset such that  the entire bitmap re-
sides in the ELRANGE when legacy compatibility mode for indirect branch 
tracking is enabled. However this is not enforced by the hardware.
This field exists when CPUID.(EAX=7 , ECX=0):EDX.CET_IB T[bit 20] is enu-
merated as 1, else  it is reserved.
CET_ATTRIBUTES 32 1 CET feature attributes of the enclave; see Table 35-5. This field exists 
when CPUID.(EAX=12,ECX=1):EAX[6] is enumerated as 1, else it is reserved.
RESERVED 33 15ATTRIBUTES 48 16 Attributes of the Enclave, see Table 35-3.MRENCLAVE 64 32 Measurement Register of enclav e build process. See SIGSTRUCT for format.
RESERVED 96 32MRSIGNER 128 32 Measurement Register extended with the public key that verified the 
enclave. See SIGSTRUCT for format.
RESERVED 160 32CONFIGID 192 64 Post EINIT configuration identity.ISVPRODID 256 2 Product ID of enclave.ISVSVN 258 2 Security version number (SVN) of the enclave.CONFIGSVN 260 2 Post EINIT configuratio n security version number (SVN).
RESERVED 262 3834 The RESERVED field consists of the following:
• EID: An 8 byte Enclave Identifier. Its location is implem entation specific.
• PAD: A 352 bytes padding pattern from the Signature (used for key 
derivation strings). It’s locati on is implementation specific.
• VIRTCHILDCNT: An 8 byte Count of virtual children that have been paged 
out by a VMM. Its location is implementation specific.
• ENCLAVECONTEXT: An 8 byte Enclave context pointer. Its location is 
• ISVFAMILYID: A 16 byte value assigned to identify the family of products 
the enclave belongs to.
• ISVEXTPRODID: A 16 byte value a ssigned to identify the product 
identity of the enclave.
• The remaining 3226 bytes are reserved area.
The entire 3834 byte field must be cleared prior to executing ECREATE.35-6 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.7.1 ATTRIBUTES 
The ATTRIBUTES data structure is comprised of bit-granular  fields that are used in the SECS, the REPORT and the 
KEYREQUEST structures. CPUID.(EAX=12H , ECX=1) enumerates a bitmap of pe rmitted 1-setting of bits in ATTRI-
BUTES.
35.7.2 SECS.MISCSELECT Field
CPUID.(EAX=12H, ECX=0):EBX[31:0] enumerates which exte nded information that the processor can save into 
the MISC region of SSA when an AE X occurs. An enclave writer can specify via SIGSTRUCT how to set the 
SECS.MISCSELECT field. The bit vector of MISCSELECT sele cts which extended information is to be saved in the 
MISC region of the SSA frame when an AEX is generated. Th e bit vector definition of extended information is listed 
in Table 35-4.
If CPUID.(EAX=12H, ECX=0):EBX[31:0] = 0, SECS.MISCSELECT field must be all zeros.
The SECS.MISCSELECT field determines the size of MI SC region of the SSA frame, see Section 35.9.2.
35.7.3 SECS.CET_ATTRIBUTES Field
The SECS.CET_ATTRIBUTES field can be used by the enclave wr iter to enable various CET attributes in an enclave. 
This field exists when CPUID.(EAX =12,ECX=1):EAX[6] is enumerated as 1. Bits 1:0 are defined when 
CPUID.(EAX=7, ECX=0):ECX.CET _SS is 1, and bits 5:2 are defined when  CPUID.(EAX=7, ECX=0):EDX.CET_IBT is 
1.Table 35-3.  Layout of ATTRIBUTES Structure
Field Bit Position Description
INIT 0 This bit indicates if the enclave has been initialized by EINIT. It must be cleared when loaded as 
part of ECREATE. For EREPORT instruction, TARGET _INFO.ATTRIBUTES[ENIT] must always be 1 to 
match the state after EINIT has initialized the enclave.
DEBUG 1  If 1, the enclave permit debugger to read  and write enclave data using EDBGRD and EDBGWR.
MODE64BIT 2 Enclave runs in 64-bit mode.RESERVED 3 Must be Zero.PROVISIONKEY 4 Provisioning Key is available from EGETKEY.EINITTOKEN_KEY 5 EINIT token key is available from EGETKEY.CET 6 Enable CET attributes. When CPUID.(EAX=12H, ECX=1): EAX[6] is 0 this bit is reserved and must be 
0.
KSS 7 Key Separation and Sharing Enabled.RESERVED 9:8 Must be zero.AEXNOTIFY 10 The bit indicates th at threads within th e enclave may receiv e AEX notifications.
RESERVED 63:11 Must be zero.XFRM 127:64 XSAVE Feature Request Mask. See Section 39.7.
Table 35-4.  Bit Vector Layout of MISCSELECT Field of Extended Information
EXINFO 0 Report information about page  fault and general protection exception that occurred inside an 
enclave.
CPINFO 1 Report information about control protection ex ception that occurred inside an enclave. When 
CPUID.(EAX=12H, ECX=0):EBX[1] is 0, this bit is reserved.
Reserved 31:2  Reserved (0).Vol. 3D 35-7ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.8 THREAD CONTROL STRUCTURE (TCS)
Each executing thread in the enclave is associated with a Thread Control Structure. It requires 4K-Bytes alignment.Table 35-5.  Bit Vector Layout of CET_AT TRIBUTES Field of Extended Information
SH_STK_EN 0 When se t to 1, enable shadow stacks.
WR_SHSTK_EN 1 When set to 1, enables the WRSS{D,Q}W instructions.ENDBR_EN 2  When set to 1, enab les indirect branch tracking.
LEG_IW_EN 3 Enable legacy compatibility treatment for indirect branch tracking.NO_TRACK_EN 4 When set to 1, enables use of no -track prefix for indi rect branch tracking.
SUPPRESS_DIS 5 When set to 1, disables  suppression of CET indirect branch  tracking on lega cy compatibility.
Reserved 7:6  Reserved (0).
Table 35-6.  Layout of Thread Control Structure (TCS)
STAGE 0 8 Enclave execution state of the thread controlled by this TCS. A value of 0 indi-
cates that this TCS is available for encl ave entry. A value of 1 indicates that a 
logical processor is currently executing an enclave in the context of this TCS.
FLAGS 8 8 The thread’s execution flags (see Section 35.8.1).OSSA 16 8 Offset of the base of the State Save Area stack, relative to the enclave base. 
Must be page aligned.
CSSA 24 4 Current slot index of an SSA frame, cleared by EADD and EACCEPT.NSSA 28 4 Number of available slots for SSA frames.OENTRY 32 8 Offset in enclave to which control is transferred on EENT ER relative to the 
base of the enclave.
AEP 40 8 The value of the Asynchronous Exit Pointer that was saved at EENTER time.OFSBASE 48 8 Offset to add to the base address of the encl ave for producing the base 
address of FS segment inside the enclave. Must be page aligned.
OGSBASE 56 8 Offset to add to the base address of the encl ave for producing the base 
address of GS segment inside the enclave. Must be page aligned.
FSLIMIT 64 4 Size to become the new FS limit in 32-bit mode.
GSLIMIT 68 4 Size to become the new GS limit in 32-bit mode.
OCETSSA 72 8 When CPUID.(EAX=12H, ECX=1):EAX[6] is 1, this field provides the offset of 
the CET state save area from enclave base. When CPUID.(EAX=12H, 
ECX=1):EAX[6] is 0, this fiel d is reserved and must be 0.
PREVSSP 80 8 When CPUID.(EAX=07H , ECX=00h):ECX[CET_SS] is 1, this field records the SSP 
at the time of AEX or EEXIT; us ed to setup SSP on entry. When 
CPUID.(EAX=07H, ECX=00h):ECX[CET_SS] is 0, this field is reserved and must 
be 0.
RESERVED 72 4024 Must be zero.35-8 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.8.1 TCS.FLAGS 
35.8.2 State Save Area Offset (OSSA)
The OSSA points to a stack of State Save Area (SSA) fram es (see Section 35.9) used to save the processor state 
when an interrupt or exception occu rs while executing in the enclave. 
35.8.3 Current State Save Area Frame (CSSA)
CSSA is the index of the current SSA frame that will be used by the processor to determine where to save the 
processor state on an interrupt or exception that occurs while executing in the enclave. It is an index into the array of frames addressed by OSSA. CSSA is incremen ted on an AEX and decremented on an ERESUME.
35.8.4 Number of State Save Area Frames (NSSA)
NSSA specifies the number of SSA frames available for th is TCS. There must be at least one available SSA frame 
when EENTER-ing the enclav e or the EENTER will fail.
35.9 STATE SAVE AREA (SSA) FRAME
When an AEX occurs while running in an  enclave, the architectural state is saved in the thread’s current SSA frame, 
which is pointed to by TCS.CSSA. An SSA frame must be page aligned, and contains the following regions:
•The XSAVE region starts at the base of the SSA frame, this region contains extended feature register state in 
an XSAVE/FXSAVE-compatible non-compacted format.
•A Pad region: software may choose to maintain a pad regi on separating the XSAVE region and the MISC region. 
Software choose the size of the pad region accord ing to the sizes of the MISC and GPRSGX regions.
•The GPRSGX region. The GPRSGX region is the last region of an SSA frame (see Table 35-8). This is used to hold 
the processor general purpose registers (RAX … R15), th e RIP, the outside RSP and RBP, RFLAGS, and the AEX 

information. 
•The MISC region (If CPUIDEAX=12H, ECX=0):EBX[31:0] != 0). The MISC region is adjacent to the GRPSGX 
region, and may contain zero or more components of ex tended information that would be saved when an AEX 
occurs. If the MISC region is absent, the region between  the GPRSGX and XSAVE regions is the pad region that 
software can use. If the MISC region is present, th e region between the MISC and XSAVE regions is the pad 
region that software can use. See additional details in Section 35.9.2.Table 35-7.  Layout of TCS.FLAGS Field
DBGOPTIN 0 If set, allows debugging features (single-steppi ng, breakpoints, etc.) to be enabled and active while 
executing in the enclave on this TCS. Hardware clears this bit on EADD. A debugger may later mod-ify it if the enclave’s ATTRIBUTES.DEBUG is set. 
AEXNOTIFY 1 A thread that enters the enclave cannot receive AEX notifications unless this flag is set to 1.
RESERVED 63:2 Must be zero.Vol. 3D 35-9ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.9.1 GPRSGX Region
The layout of the GPRSGX region is shown in Table 35-9.Table 35-8.  Top-to-Bottom Layout of an SSA Frame
Region Offset (Byte) Si ze (Bytes) Description
XSAVE 0 Calculate using CPUID 
leaf 0DH informationThe size of XSAVE region in SSA is derived from the enclave’s support of the col-
lection of processor extended states that would be managed by XSAVE. The 
enablement of those processor extended state components in conjunction with 
CPUID leaf 0DH information determines the XSAVE region size in SSA.
Pad End of XSAVE 
regionChosen by enclave 
writerEnsure the end of GPRSGX region is aligned to the end of a 4KB page.
MISC base of GPRSGX 
– sizeof(MISC)Calculate from high-
est set bit of 
SECS.MISCSELECTSee Section 35.9.2.
GPRSGX SSAFRAMESIZE 
– 176176 See Table 35-9 for layout of the GPRSGX region.
Table 35-9.  Layout of GPRSGX Portion of the State Save Area 
Field OFFSET (Bytes) Siz e (Bytes) Description
RAX 0 8RCX 8 8RDX 16 8RBX 24 8RSP 32 8RBP 40 8RSI 48 8RDI 56 8R8 64 8R9 72 8R10 80 8R11 88 8R12 96 8R13 104 8R14 112 8R15 120 8RFLAGS 128 8 Flag register.RIP 136 8 Instruction pointer.URSP 144 8 Non-Enclave (outside) stack pointer. Saved by EENTER, restored on AEX.URBP 152 8 Non-Enclave (outside) RBP pointer. Saved by EENTER, restored on AEX.EXITINFO 160 4 Contains information about exceptions that cause AEXs, which might be 
needed by enclave software (see Section 35.9.1.1).
RESERVED 164 335-10 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.9.1.1  EXITINFO
EXITINFO contains the information used to report exit reasons to software inside the enclave. It is a 4 byte field laid 
out as in Table 35-10. The VALID bit is set only for the ex ceptions conditions which are reported inside an enclave. 
See Table 35-11 for which exceptions are reported inside th e enclave. If the exception condition is not one reported 
inside the enclave then VECTOR and EXIT_TYPE are cleared.
When a higher priority event, such as SMI, and a pendin g debug exception occur at the same time when executing 
inside an enclave, the higher priority  event has precedence. As an example for an SMI, the SSA exit info is zero. 
The debug exception will be delivered up on return from the SMI. In such case s, the EXITINFO field will not contain 
the information of a debug exception.
35.9.1.2  VECTOR Field Definition
Table 35-11 contains the VECTOR field. This field contains information about some exceptions which occur inside 
the enclave. These vector values are the same as the valu es that would be used when vectoring into regular excep-
tion handlers. All values not shown are not reported inside an enclave. AEXNOTIFY 167 1 Bit 0: This bit allows enclave so ftware to dynamically en able/disable AEX noti-
fications. An enclave thre ad cannot receive AEX notifi cations unless this bit is 
set to 1 in the thread 's current SSA frame.
FSBASE 168 8 FS BASE.GSBASE 176 8 GS BASE.
Table 35-10.  Layout of EXITINFO Field
VECTOR 7:0 Exception number of exceptions reported inside enclave.EXIT_TYPE 10:8 011b: Hardware exceptions.
110b: Software exceptions.Other values: Reserved.
RESERVED 30:11 Reserved as zero.VALID 31 0: unsupported exceptions.
1: Supported exceptions. Includes two categories:
• Unconditionally supported exceptions: #DE,  #DB, #BP, #BR, #UD, #MF, #AC, #XM.
• Conditionally supported exception: 
— #PF, #GP if SECS.MISCSELECT.EXINFO = 1.
— #CP if SECS.MISCSELECT.CPINFO=1.
Table 35-11.  Exception Vectors 
Name Vector # Description
#DE 0 Divider exception.#DB 1 Debug exception.#BP 3 Breakpoint exception.#BR 5 Bound range exceeded exception.#UD 6 Invalid opcode exception.#GP 13 General protection exception. Only reported if SECS.MISCSELECT.EXINFO = 1.
#PF 14 Page fault exception. Only repo rted if SECS.MISCSELECT.EXINFO = 1.Table 35-9.  Layout of GPRSGX Portio n of the State Save Area  (Contd.)
Field OFFSET (Bytes) Size (Bytes) DescriptionVol. 3D 35-11ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.9.2 MISC Region
The layout of the MISC region is shown in Table 35-12. The number of components that the processor supports in 
the MISC region corresponds to the bits of CPUID.(E AX=12H, ECX=0):EBX[31:0] set to 1. Each set bit in 
CPUID.(EAX=12H, ECX=0):EBX[31:0] has a defined size for the corresponding component, as shown in Table 
35-12. Enclave writers needs to do the following:
•Decide which MISC region components will be supported for the enclave.
•Allocate an SSA frame large enough to hold the components chosen above.
•Instruct each enclave builder software to set the appropriate bits  in SECS.MISCSELECT.
The first component, EXINFO, starts next to the GPRSGX region. Additional components in the MISC region grow 
in ascending order within the MISC region towards the XSAVE region.
The size of the MISC region is calculated as follows:
•If CPUID.(EAX=12H, ECX=0):EBX[31:0] = 0, MISC region is not supported. 
•If CPUID.(EAX=12H, ECX=0):EBX[31:0] !=  0, the size of MISC region is derived from sum of the highest bit set 
in SECS.MISCSELECT and the size of the MISC compon ent corresponding to that bit. Offset and size 
information of currently defined MISC components are lis ted in Table 35-12. For example, if the highest bit set 
in SECS.MISCSELECT is bit 0, the MISC region offset is OFFSET(GPRSGX)-16 and size is 16 bytes.
•The processor saves a MISC component i in the MISC region if and only if SECS.MISCSELECT[i] is 1.
35.9.2.1  EXINFO Structure
Table 35-13 contains the layout of the EXINFO st ructure that provides additional information. #MF 16 x87 FPU floating-point error.
#AC 17 Alignment check exceptions.#XM 19 SIMD floating-point exceptions.#CP 21 Control protection exception. Only  reported if SECS.MISCSELECT.CPINFO=1.
Table 35-12.  Layout of MISC region of the State Save Area
MISC Components OFFSET (Byt es) Size (Bytes) Description
EXINFO Offset(GPRSGX) –16 16 If CPUID.(EAX=12H, ECX= 0):EBX[0] = 1, exception information on #GP or 
#PF that occurred inside an enclave ca n be written to the EXINFO structure 
if specified by SECS.MISCSELECT[0] = 1.
If CPUID.(EAX=12H, ECX=0):EBX[1] = 1, exception information on #CP that 
occurred inside an enclave can be written to the EXINFO structure if speci-fied by SECS.MISCSELECT[1] = 1.
Future Extension Below EXINFO TBD Reserved. (Zero size if CPUID.(EAX=12H, ECX=0):EBX[31:1] =0).
Table 35-13.  Layout of EXINFO Structure
MADDR 0 8 If #PF: contains the page fault linear address that caused a page fault.
If #GP: the field is cleared.
If #CP: the field is cleared.
ERRCD 8 4 Exception error code for either #GP or #PF.RESERVED 12 4Table 35-11.  Exception Vectors  (Contd.)
Name Vector # Description35-12 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.9.2.2  Page Fault Error Code
Table 35-14 contains page fault error code that may be reported in EXINFO.ERRCD. 
35.10 CET STATE SAVE AREA FRAME
The CET state save area consists of an array of CET state save frames. The number of CET state save frames is 
equal to the TCS.NSSA. The current CET SSA frame is indica ted by TCS.CSSA. The offset of the CET state save area 
is specified by TCS.OCETSSA.
35.11 PAGE INFORMATION (PAGEINFO)
PAGEINFO is an architectural data structure that is used as a parameter to the EPC-management instructions. It 
requires 32-Byte alignment.Table 35-14.  Page Fault Error Code
Name Bit Position Description
P 0 Same as non-SGX page fault exception P flag.W/R 1 Same as non-SGX page fault exception W/R flag.U/S
1
NOTES:
1. Page faults incident to enclave mode th at report U/S=0 are not reported in EXINFO.2 Always set to 1 (use r mode reference).
RSVD 3 Same as non-SGX page fault exception RSVD flag.I/D 4 Same as non-SGX page fault exception I/D flag.PK 5 Protection Key induced fault.RSVD 14:6 Reserved.SGX 15 EPCM induced fault.RSVD 31:5 Reserved.
Table 35-15.  Layout of CET State Save Area Frame
FieldOffset 
(Bytes)Size (Bytes) Description
SSP 0 8 Shadow Stack Pointer.

1
NOTES:
SSP 0 8 Shadow Stack Pointer. 
This field is reserved when CPUID.(EAX=7, ECX=0):ECX[CET_SS] is 0.
IB_TRACK_STATE 8 8 Indirect branch tracker state:
Bit 0: SUPPRESS – supp ressed(1), tracking(0)
Bit 1: TRACKER - IDLE (0), WAIT_FOR_ENDBRANCH (1)Bits 63:2 – Reserved
This field is reserved when CPUID.(EAX=7, ECX=0):EDX[CET_IBT] is 0.
Table 35-16.  Layout of PAGEINFO Data Structure
LINADDR 0 8 Enclave linear address.SRCPGE 8 8 Effective address of the page where contents are located.SECINFO/PCMD 16 8 Effective address of the SECINFO or PCMD (for ELDU, ELDB, EWB) structure for 
the page.
SECS 24 8 Effective address of EPC slot that currently contains the SECS.Vol. 3D 35-13ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.12 SECURITY INFORMATION (SECINFO)
The SECINFO data structure holds meta-data about an enclave page. 
35.12.1 SECINFO.FLAGS
The SECINFO.FLAGS are a set of fields describing the properties of an enclave page.
35.12.2 PAGE_TYPE Field Definition
The SECINFO flags and EPC flags contain bits indicating the type of page. Table 35-17.  Layout of  SECINFO Data Structure
FLAGS 0 8 Flags describing the state of the enclave page.RESERVED 8 56 Must be zero.
Table 35-18.  Layout of SECINFO.FLAGS Field
R 0 If 1 indicates that the page can be read from inside the enclave; otherwise the page cannot be read 
from inside the enclave.
W 1 If 1 indicates that the page can be written from inside the enclave; otherwise the page cannot be writ-
ten from inside the enclave.
X 2 If 1 indicates that the page can be executed from inside the enclave; otherwise the page cannot be 
executed from inside the enclave.
PENDING 3 If 1 indicates that the page is in the PENDING state; otherwise the page is not in the PENDING state.MODIFIED 4 If 1 indicates that the page is in the MODIFIED state; otherwise the page is not in the MODIFIED state.
PR 5 If 1 indicates that a permission re striction operation on the page is in progress, otherwise a permission 
restriction operation is not in progress.
RESERVED 7:6 Must be zero.PAGE_TYPE 15:8 The type of page that  the SECINFO is associated with.
RESERVED 63:16 Must be zero.
Table 35-19.  Supported PAGE_TYPE
TYPE Value Description
PT_SECS 0 Page is an SECS.PT_TCS 1 Page is a TCS.PT_REG 2 Page is a regular page.PT_VA 3 Page is a Version Array.PT_TRIM 4 Page is in trimmed state.PT_SS_FIRST 5 When CPUID.(EAX=12H, ECX=1):EAX[6] is 1, Page is first page of a shadow stack. When 
CPUID.(EAX=12H, ECX=1):EAX[6] is 0, this value is reserved.
PT_SS_REST 6 When CPUID.(EAX=12H, ECX=1):EAX[6] is 1, Page is not first page of a shadow stack. When 
All others Reserved.35-14 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.13 PAGING CRYPTO METADATA (PCMD)
The PCMD structure is used to keep track of crypto me ta-data associated with a paged-out page. Combined with 
PAGEINFO, it provides enough information for the processo r to verify, decrypt, and reload a paged-out EPC page. 
The size of the PCMD structure (128 bytes) is architectural. 
EWB calculates the Message Authentication Code (MAC) va lue and writes out the PCMD. ELDB/U reads the fields 
and checks the MAC.
The format of PCMD is as follows:
35.14 ENCLAVE SIGNATURE STRUCTURE (SIGSTRUCT)
SIGSTRUCT is a structure created and signed by the en clave developer that contains information about the 
enclave. SIGSTRUCT is processed by the EINIT leaf func tion to verify that the enclave was properly built.
SIGSTRUCT includes ENCLAVEHASH as SHA256 digest, as de fined in FIPS PUB 180-4. The digests are byte strings 
of length 32. Each of the 8 HASH dwords is stored in little-endian order.
SIGSTRUCT includes four 3072-bit integers (MODULUS, SIGN ATURE, Q1, Q2). Each such integer is represented as 
a byte strings of length 384, with the most significant byte at the position “offset + 383”, and the least significant 
byte at position “offset”.
The (3072-bit integer) SIGNATURE should be an RSA sign ature, where: a) the RSA modulus (MODULUS) is a 3072-
bit integer; b) the public exponent is set to 3; c) the signing procedure uses the EMSA-PKCS1-v1.5 format with DER 
encoding of the “DigestInfo” value as specified in of PKCS#1 v2.1/RFC 3447.
The 3072-bit integers Q1 and Q2 are defined by:q1 = floor(Signature^2 / Modulus);q2 = floor((Signature^3 - q1 * Signature * Modulus) / Modulus);SIGSTRUCT must be page alignedIn column 5 of Table 35-21, ‘Y’ indicates that this field sh ould be included in the signature generated by the devel-
oper.Table 35-20.  Layout of PCMD Data Structure
SECINFO 0 64 Flags describing the state of the enclave page; R/W by software.ENCLAVEID 64 8 Enclave Identifier used to establish a cryptographic binding between paged-out 
page and the enclave.
RESERVED 72 40 Must be zero.MAC 112 16 Message Authentication Code  for the page, page meta-data and reserved 
field.
Table 35-21.  Layout of Enclav e Signature Structure (SIGSTRUCT)
Field OFFSET (Bytes) Size (Bytes) Description Signed
HEADER 0 16 Must be byte stream
06000000E10000000000010000000000HY
VENDOR 16 4 Intel Enclave: 00008086H
Non-Intel Enclave: 00000000HY
DATE 20 4 Build date is yyyymmdd in hex:
yyyy=4 digit year, mm=1-12, dd=1-31Y
HEADER2 24 16 Must be byte stream
01010000600000006000000001000000HY
SWDEFINED 40 4 Available for software use. YVol. 3D 35-15ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.15 EINIT TOKEN STRUCTURE (EINITTOKEN)
The EINIT token is used by EINIT to verify that the enclav e is permitted to launch. EINIT token is generated by an 
enclave in possession of the EINITTOKEN key (the Launch Enclave).
EINIT token must be 512-Byte aligned.RESERVED 44 84 Must be zero. Y
MODULUS 128 384 Module Public Key (keylength=3072 bits). NEXPONENT 512 4 RSA Exponent = 3. NSIGNATURE 516 384 Signature over Header and Body. NMISCSELECT
1900 4 Bit vector specifying Extended SSA frame feature set to be 
used.Y
MISCMASK 904 4 Bit vector mask of MISCSELECT to enforce. Y
CET_ATTRIBUTES 908 1 When CPUID.(EAX=12H, ECX=1):EAX[6] is 1, this field pro-
vides the Enclave CET attributes  that must be  set. When 
CPUID.(EAX=12H, ECX=1):EAX[6] is 0, this field is reserved and must be 0.Y
CET_ATTRIBUTES
_MASK909 1 When CPUID.(EAX=1 2H, ECX=1):EAX[6] is 1, this field pro-
vides the Mask of CET attributes to enforce. When 
CPUID.(EAX=12H, ECX=1):EAX[6] is 0, this field is reserved 
and must be 0.Y
RESERVED 910 2 Must be zero. Y
ISVFAMILYID 912 16 ISV assigned Product Family ID. YATTRIBUTES 928 16 Enclave Attrib utes that must be set. Y
ATTRIBUTEMASK 944 16 Mask of Attributes to enforce. YENCLAVEHASH 960 32 MRENCLAVE of encl ave this structure applies to. Y
RESERVED 992 16 Must be zero. YISVEXTPRODID 1008 16 ISV assigned extended Product ID. YISVPRODID 1024 2 ISV assigned Product ID. YISVSVN 1026 2 ISV assigned SVN (security version number). YRESERVED 1028 12 Must be zero. NQ1 1040 384 Q1 value for RSA Signature Verification. NQ2 1424 384 Q2 value for RSA Signature Verification. N
NOTES:
1. If CPUID.(EAX=12H, ECX=0):EBX[31:0] = 0, MISCSELECT must be 0.Table 35-21.  Layout of Enclav e Signature Structure (SIGSTRUCT)
Field OFFSET (Bytes) Size (Bytes) Description Signed35-16 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.16 REPORT (REPORT)
The REPORT structure is the output of the EREP ORT instruction, and must be 512-Byte aligned.Table 35-22.  Layout of EINIT Token (EINITTOKEN)
Field OFFSET (Bytes) Size (Bytes) MACed Description
Valid 0 4 Y Bit 0: 1: Valid; 0: Invalid. 
RESERVED 4 44 Y Must be zero.ATTRIBUTES 48 16 Y ATTRIBUTES of the Enclave.MRENCLAVE 64 32 Y MRENCLAVE of the Enclave.RESERVED 96 32 Y Reserved.MRSIGNER 128 32 Y MRSIGNER of the Enclave.RESERVED 160 32 Y Reserved.CPUSVNLE 192 16 N Launch Enclave’s CPUSVN.ISVPRODIDLE 208 02 N Launch Enclave’s ISVPRODID.ISVSVNLE 210 02 N Launch Enclave’s ISVSVN.
CET_MASKED_AT
TRIBUTES_LE212 1 N When CPUID.(EAX=12H, ECX=1):EAX[6] is 1, this field provides the 
Launch enclaves masked CET attributes. This sh ould be set to LE’s 
CET_ATTRIBUTES masked with CET_ATTTRIBUTES_MASK of the LE’s 
KEYREQUEST. When CPUID.(EAX=12H, EC X=1):EAX[6] is 0, this field is 
reserved.
RESERVED 213 23 N Reserved.MASKEDMISCSEL
ECTLE236 4 Launch Enclave’s MASKEDMISCSELECT : set by the LE to the resolved 
MISCSELECT value, used by EGETKEY (after applying KEYREQUEST’s 
masking).
MASKEDATTRIBU
TESLE240 16 N Launch Enclave’s MASKEDATTRIBUTES : This should be set to the LE’s 
ATTRIBUTES masked with ATTRIBUTEMASK of the LE’s KEYREQUEST.
KEYID 256 32 N Value for key wear-out protection.MAC 288 16 N Message Authentication Code on EINITTOKEN using EINITTOKEN_KEY.
Table 35-23.  Layout of REPORT 
CPUSVN 0 16 The security version number of the processor.MISCSELECT 16 4 Bit vector specifying which extended features are saved to the MISC region of 
the SSA frame when an AEX occurs.

reserved.
masking).
CET_ATTRIBUTES 20 1 When CPUID.(EAX=12H, ECX=1):EAX[6] is 1, this field reports the CET_ATTRIB-
UTES of the Enclave. When CPUID.(EAX=12H , ECX=1):EAX[6] is 0, this field is re-
served and must be 0.
RESERVED 21 11 Zero.ISVEXTNPRODID 32 16 The value of SECS.ISVEXTPRODID.ATTRIBUTES 48 16 ATTRIBUTES of the Enclave. See Section 35.7.1.MRENCLAVE 64 32 The value of SECS.MRENCLAVE.RESERVED 96 32 Zero.MRSIGNER 128 32 The value of SECS.MRSIGNER.RESERVED 160 32 Zero.Vol. 3D 35-17ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.16.1 REPORTDATA
REPORTDATA is a 64-Byte data structure that is provided by the enclave and included in the REPORT. It can be used 
to securely pass information from th e enclave to the target enclave. 
35.17 REPORT TARGET INFO (TARGETINFO)
This structure is an input parameter to the EREPORT leaf function. The address of TARGETINFO is specified as an 
effective address in RBX. It is used to identify the target  enclave which will be able to cryptographically verify the 
REPORT structure returned by EREPORT. TARGETINFO must be 512-Byte aligned.
35.18 KEY REQUEST (KEYREQUEST)
This structure is an input parameter to the EGETKEY leaf f unction. It is passed in as an effective address in RBX and 
must be 512-Byte aligned. It is used for selecting the ap propriate key and any additional parameters required in 
the derivation of that key.CONFIGID 192 64 Value provided by SW to identify enclave's post EINIT configuration.
ISVPRODID 256 2 Product ID of enclave.ISVSVN 258 2 Security version number (SVN) of the enclave.CONFIGSVN 260 2 Value provided by SW to indicate expected SVN of enclave's post EINIT configu-
ration.
RESERVED 262 42 Zero.ISVFAMILYID 304 16 The value of SECS.ISVFAMILYID.REPORTDATA 320 64 Data provided by the user and protected by the REPORT's MAC, see Section 
35.16.1.
KEYID 384 32 Value for key wear-out protection.MAC 416 16 Message Authenti cation Code on the report using report key.
Table 35-24.  Layout of TARGETINFO Data Structure
MEASUREMENT 0 32 The MRENCLAV E of the target enclave.
ATTRIBUTES 32 16 The ATTRIBUTES field of the target enclave.CET_ATTRIBUTES 48 1 When CPUID.(EAX=12H, ECX=1):EAX[6] is 1, this field provides the 
CET_ATTRIBUTES field of the target enclave. When CPUID.(EAX=12H, 
ECX=1):EAX[6] is 0, th is field is reserved.
RESERVED 49 1 Must be zero.CONFIGSVN 50 2 CONFIGSVN of the target enclave.MISCSELECT 52 4 The MISCSELECT of the target enclave.RESERVED 56 8 Must be zero.CONFIGID 64 64 CONFIGID of target enclave.
RESERVED 128 384 Must be zero.Table 35-23.  Layout of REPORT 
Field OFFSET (Bytes) Size (Bytes) Description35-18 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.18.1 KEY REQUEST KeyNames
35.18.2 Key Request Policy StructureTable 35-25.  Layout of KEYREQUEST Data Structure
KEYNAME 0 2 Identifies the Key Required.KEYPOLICY 2 2 Identifies which inputs are required to be used in the key derivation.ISVSVN 4 2 The ISV security version number that will be used in the key derivation.CET_ATTRIBUTES
_MASK6 1 When CPUID.(EAX=12H, ECX=1):EAX[6] is 1, this field provides a mask that 
defines which CET_ATTRIBUTES bits will be included in key derivation. When 
CPUID.(EAX=12H, ECX=1):EAX[6] is 0, then  this field is reserved and must be 
0.
RESERVED 7 1 Must be zero.CPUSVN 8 16 The security version number of the processor used in the key derivation.ATTRIBUTEMASK 24 16 A mask defining which ATTRIBUTES bits will be included in key derivation.KEYID 40 32 Value for key wear-out protection.MISCMASK 72 4 A mask defining which MISCSELECT bits will be included in key derivation.CONFIGSVN 76 2 Identifies which enclave Configuration's Security Version should be used in key 
derivation.
RESERVED 78 434
Table 35-26.  Suppor ted KEYName Values
Key Name Value Description
EINITTOKEN_KEY 0 EINIT_TOKEN keyPROVISION_KEY 1 Provisioning KeyPROVISION_SEAL_KEY 2 Provisioning Seal KeyREPORT_KEY 3 Report KeySEAL_KEY 4 Seal Key
All others Reserved
Table 35-27.  Layout of KEYPOLICY Field
MRENCLAVE 0 If 1, derive key using the enclave's MRENCLAVE measurement register.MRSIGNER 1 If 1, derive key using the enclave's MRSIGNER measurement register.NOISVPRODID 2 If 1, derive key WITHOUT using the enclave' ISVPRODID value.CONFIGID 3 If 1, derive key usin g the enclave's CONFIGID value.
ISVFAMILYID 4 If 1, derive key us ing the enclave ISVFAMILYID value.
ISVEXTPRODID 5 If 1, derive key us ing enclave's ISVE XTPRODID value.
RESERVED 15:6 Must be zero.Vol. 3D 35-19ENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.19 VERSION ARRAY (VA)
In order to securely store the versions of evicted EPC pages, Intel SGX defines a special EPC page type called a 
Version Array (VA). Each VA page contains 512 slots, each of which can contain an 8-byte version number for a page evicted from the EPC. When an EPC page is evicted, software chooses an empty slot in a VA page; this slot 
receives the unique version number of the page being evicte d. When the EPC page is reloaded, there must be a VA 
slot that must hold the version of the page. If the page is successfully reloaded, the version in the VA slot is cleared.
VA pages can be evicted, just like any other EPC page. Wh en evicting a VA page, a version slot in some other VA 
page must be used to hold the version for the VA being evicted. A Version Array Page must be 4K-Bytes aligned.
35.20 ENCLAVE PAGE CACHE MAP (EPCM)
EPCM is a secure structure used by the processor to track the contents of the EPC. The EPCM holds exactly one 
entry for each page that is currently loaded into the EP C. EPCM is not accessible by software, and the layout of 
EPCM fields is implementation specific.
35.21 READ INFO (RDINFO)
The RDINFO structure contains status information about an EPC page. It must be aligned to 32-Bytes.Table 35-28.  Layout of Ve rsion Array Data Structure
Slot 0 0 8 Version Slot 0Slot 1 8 8 Version Slot 1...Slot 511 4088 8 Version Slot 511
Table 35-29.  Content of an Enclave Page Cache Map Entry
VALID Indicates whether the EPCM entry is valid.R Read access; indicates whether enclave accesses for reads are allowed from the EPC page referenced by this 
entry.
W Write access; indicates whether enclave accesses for writes are allowed to the EPC page referenced by this 
entry.
X Execute access; indicates whether enclave accesses for instruction fetches are allowed from the EPC page 
referenced by this entry.
PT EPCM page type (PT_SECS, PT_TCS, PT_REG, PT_VA, PT_TRIM, PT_SS_FIRST, PT_SS_REST).
ENCLAVESECS SECS identifier of the enclave to which the EPC page belongs.ENCLAVEADDRESS Linear enclave address of the EPC page.BLOCKED Indicates whether the EPC page is in the blocked state.PENDING Indicates whether the EPC page is in the pending state.MODIFIED Indicates whether the EPC page is in the modified state.PR Indicates whether the EPC page is in a permission restriction state.35-20 Vol. 3DENCLAVE ACCESS CONTROL AND DATA STRUCTURES
35.21.1 RDINFO Status Structure
35.21.2 RDINFO Flags StructureTable 35-30.  Layout of RDINFO Structure
FieldOFFSET 
STATUS 0 8 Page status information.
FLAGS 8 8 EPCM state of the page.ENCLAVECONTEXT 16 8 Context pointer desc ribing the page's parent location.
Table 35-31.  Layout of RDINFO STATUS Structure
CHILDPRESENT 0 Indicates that the page has one or more child pages present (always zero for non-SECS 
pages). In VMX non-root operation includes the presence of virtual children.
VIRTCHLDPRESENT 1 Indicates that the page has one or more virtual child pages present (always zero for non-
SECS pages). In VMX non-root operation this value is always zero.
RESERVED 63:2
Table 35-32.  Layout of RDINFO FLAGS Structure
R 0 Read access; indicates whether enclave accesses for reads are allowed from the EPC page 
W 1 Write access; indicates whether enclave acce sses for writes are allowed to the EPC page 
X 2 Execute access; indicates whether enclave a ccesses for instructio n fetches are allowed 
from the EPC page referenced by this entry.
PENDING 3 Indicates whether the EPC page is in the pending state.MODIFIED 4 Indicates whether the EPC page is in the modified state.PR 5 Indicates whether the EPC page is in a permission restriction state.RESERVED 7:6PAGE_TYPE 15:8 Indicates the page type of the EPC page.RESERVED 62:16BLOCKED 63 Indicates whether the EPC page is in the blocked state.Vol. 3D 36-1ENCLAVE OPERATION
CHAPTER 36
The following aspects of enclave operation are described in this chapter:
•Enclave creation: Includes loading code and data from outside of enclave into the EPC and establishing the 
enclave entity.
•Adding pages and measuring the enclave.
•Initialization of an enclave: Finalizes the cryptograp hic log and establishes the enclave identity and sealing 
identity.

CHAPTER 36
identity.
•Enclave entry and exiting including:
— Controlled entry and exit.— Asynchronous Enclave Exit (AEX) an d resuming execution after an AEX.
36.1 CONSTRUCTING AN ENCLAVE
Figure 36-1 illustrates a typical Enclave memory layout. 
The enclave creation, commitment of memory resources, an d finalizing the enclave’s identity with measurement 
comprises multiple phases. This process can be illustrated by the following exemplary steps:
1. The application hands over the enclave content along with additional information required by the enclave 
creation API to the enclave creation service running at privilege level 0.
2. The enclave creation service running at privilege level 0 uses the ECREATE leaf function to set up the initial 
environment, specifying base address and size of the encl ave. This address range, the ELRANGE, is part of the 
application's address space. This reserves the memory range. The enclave will now reside in this address Figure 36-1.  Enclave Memory LayoutThread Data
Global Data
CodeEnclave MemorySECS
TCSBase + Size
BaseReplicated once 
per thread
Enclave {Base, Size}Application ContextOS Context36-2 Vol. 3DENCLAVE OPERATION
region. ECREATE also allocates an Enclave Page Cache (EPC) page for the SGX Enclave Control Structure 
(SECS). Note that this page is not required to be a pa rt of the enclave linear address space and is not required 
to be mapped into the process. 
3. The enclave creation service uses the EADD leaf function to commit EPC pages to the enclave, and use 
EEXTEND to measure the committed memory content of the enclave. For each page to be added to the enclave:
— Use EADD to add the new page to the enclave. — If the enclave developer requires measurement of the page as a proof for the content, use EEXTEND to add 
a measurement for 256 bytes of the page. Repeat this  operation until the entire page is measured. 
4. The enclave creation service uses the EINIT leaf function to complete the enclave creation process and finalize 
the enclave measurement to establish the enclave identi ty. Until an EINIT is executed, the enclave is not 
permitted to execute any enclave code (i.e., entering th e enclave by executing EENTER would result in a fault).
36.1.1 ECREATE
The ECREATE leaf function sets up the initial environmen t for the enclave by reading an SGX Enclave Control Struc-
ture (SECS) that contains the enclave's address range (ELRANGE) as defined by BASEADDR and SIZE, the ATTRI-
BUTES and MISCSELECT bitmaps, and the SSAFRAMESIZE. It then securely stores this information in an Enclave 
Page Cache (EPC) page. ELRANGE is part of the applicat ion's address space. ECREATE also initializes a crypto-
graphic log of the enclave's build process.
36.1.2 EADD and EEXTEND Interaction
Once the SECS has been created, enclave pages can be a dded to the enclave via EADD. This involves converting a 
free EPC page into either a PT_REG or a PT_TCS page.
When EADD is invoked, the processor w ill update the EPCM entry with the type  of page (PT_REG or PT_TCS), the 
linear address used by the enclave to access the page, and the enclave access permissions for the page. It associ-
ates the page to the SECS provided as input. The EPCM entry information is used by hardware to manage access 
control to the page. EADD records EPCM information in the cryptographic log stored in the SECS and copies 4 
KBytes of data from unprotected memory outside the EPC to the allocated EPC page.
System software is responsible for selecting a free EPC page. System software is also responsible for providing the 
type of page to be added, the attributes of the page, th e contents of the page, and the SECS (enclave) to which the 
page is to be added as requested by the application. Incorre ct data would lead to a failure of EADD or to an incor-
rect cryptographic log and a failure at EINIT time.
After a page has been added to an enclave, software ca n measure a 256 byte region as determined by the devel-
oper by invoking EEXTEND. Thus to measure an entire  4KB page, system software must execute EEXTEND 16 
times. Each invocation of EEXTEND adds to the cryptograp hic log information about which region is being measured 
and the measurement of the section.
Entries in the cryptographic log define the measurement of  the enclave and are critical in gaining assurance that 
the enclave was correctly constructed by the untrusted system software.
36.1.3 EINIT Interaction
Once system software has completed the process of adding  and measuring pages, the enclave needs to be initial-
ized by the EINIT leaf function. After an enclave is initia lized, EADD and EEXTEND are disabled for that enclave (An 
attempt to execute EADD/EEXTEND to enclave after enclave initialization will result in  a fault). The initialization 
process finalizes the cryptographic log and establishes the enclave identity  and sealing identity  used by 
EGETKEY and EREPORT.
A cryptographic hash of the log is stored as the enclave identity . Correct construction of the enclave results in the 
cryptographic hash matching the one built by the encl ave owner and included as the ENCLAVEHASH field of 
SIGSTRUCT. The enclave identity  provided by the EREPORT leaf function  can be verified by a remote party. Vol. 3D 36-3ENCLAVE OPERATION
The EINIT leaf function checks the EINIT token to validate that the enclave has been enabled on this platform. If 
the enclave is not correctly constructed, or the EINIT toke n is not valid for the platform, or SIGSTRUCT isn't prop-
erly signed, then EINIT will fail. See the EINIT le af function for details on the error reporting. 
The enclave identity  is a cryptographic hash that reflects the en clave attributes and MISCSELECT value, content 
of the enclave, the order in which it was built, the addr esses it occupies in memory, the security attributes, and 
access right permissions of each page. The enclave identity  is established by the EINIT leaf function.
The sealing identity  is managed by a sealing authority represented by  the hash of the public key used to sign the 
SIGSTRUCT structure processed by EINIT. The sealing au thority assigns a product ID (ISVPRODID) and security 
version number (ISVSVN) to a particular enclave identity.
EINIT establishes the sealing identity using the following steps:1. Verifies that SIGSTRUCT is properly signed using the public key enclosed in the SIGSTRUCT.
2. Checks that the measurement of the enclave matches the measurement of the enclave specified in SIGSTRUCT.
3. Checks that the enclave’s attributes and MISCSELECT values are compatible with those specified in SIGSTRUCT.
4. Finalizes the measurement of the enclave and records the sealing identity  (the sealing authority, product id 
and security version number) and enclave identity  in the SECS.
5. Sets the ATTRIBUTES.INIT bit for the enclave.
36.1.4 Intel® SGX Launch Control Configuration
Intel® SGX Launch Control is a set of controls that govern th e creation of enclaves. Before the EINIT leaf function 
will successfully initialize an enclave, a designated Launch  Enclave must create an EINITTOKEN for that enclave. 
Launch Enclaves have SECS.ATTRIBUTES.EINITTOKEN_KEY = 1, granting them access to the EINITTOKEN_KEY 
from the EGETKEY leaf function. EINITTOKEN_KEY must be used by the Launch Enclave when computing EINIT-
TOKEN.MAC, the Message Authentica tion Code of the EINITTOKEN. 
The hash of the public key used to sign the SIGSTR UCT of the Launch Enclave must equal the value in the 
IA32_SGXLEPUBKEYHASH MSRs. Only Launch Enclaves are allowed to launch without a valid token. 
The IA32_SGXLEPUBKEYHASH MSRs are provided to designate the platform’s Launch Enclave. 
IA32_SGXLEPUBKEYHASH defaults to digest of Intel’s launch enclave signing key after reset. 
IA32_FEATURE_CONTROL bit 17 controls the permi ssions on the IA32_SGXLEPUBKEYHASH MSRs when 
CPUID.(EAX=12H, ECX=00H ):EAX[0] = 1. If IA32_FEATURE_CONTROL is locked with bit 17 set, 
IA32_SGXLEPUBKEYHASH MSRs are reconfigurable (writeable). If either IA32_FEATURE_CONTROL is not locked or 
bit 17 is clear, the MSRs are read only. By leaving these MSRs writable, system SW or a VMM can support a plurality 
of Launch Enclaves for hosting multiple executio n environments. See Table 40.2.2 for more details. 
36.2 ENCLAVE ENTRY AND EXITING
36.2.1 Controlled Entry and Exit
The EENTER leaf function is the method to enter the en clave under program control. To execute EENTER, software 
must supply an address of a TCS that is part of the enclave to be entered. The TCS holds the location inside the 
enclave to transfer control to and a pointer to the SSA frame inside the enclave that an AEX should store the 
register state to. 
When a logical processor enters an enclave, the TCS is considered busy until the logical processors exits the 
enclave. An attempt to enter an enclave through a busy TCS results in a fault. Intel® SGX allows an enclave builder 
to define multiple TCSs, thereby providing support for multithreaded enclaves.

to define multiple TCSs, thereby providing support for multithreaded enclaves. 
Software must also supply to EENTER the Asynchronous Ex it Pointer (AEP) parameter. AEP is an address external 
to the enclave which an exception handler will return to  using IRET. Typically the location would contain the 
ERESUME instruction. ERESUME transfers control back to the enclave, to the address retrieved from the enclave 
thread’s saved state. 
EENTER performs the following operations:36-4 Vol. 3DENCLAVE OPERATION
1. Check that TCS is not busy and flush all cached linear-to-physical mappings. 
2. Change the mode of operation to be in enclave mode. 
3. Save the old RSP, RBP for later restore on AEX (Softwar e is responsible for setting up the new RSP, RBP to be 
used inside enclave). 
4. Save XCR0 and replace it with the XFRM value for the enclave. 5. Check if software wishes to debug (applicable to a debuggable enclave):
— If not debugging, then configure hardware so the enclave appears as a single instruction. 
— If debugging, then configure hardware to allow traps,  breakpoints, and single steps inside the enclave.
6. Set the TCS as busy.
7. Transfer control from outside enclave to predetermi ned location inside the enclave specified by the TCS.
The EEXIT leaf function is the method of leaving the en clave under program control. EEXIT receives the target 
address outside of the enclave that the enclave wishes to transfer control to. It is the responsibility of enclave soft-
ware to erase any secret from the registers prior to invoki ng EEXIT. To allow enclave software to easily perform an 
external function call and re-enter the enclave (using EE XIT and EENTER leaf functions), EEXIT returns the value of 
the AEP that was used when the enclave was entered. 
EEXIT performs the following operations:
1. Clear enclave mode and flush all cached linear-to-physical mappings. 
2. Mark TCS as not busy. 
3. Transfer control from inside the enclave to a location on the outside specified as parameter to the EEXIT leaf 
function.
36.2.2 Asynchronous Enclave Exit (AEX)
Asynchronous and synchronous events, such as exceptions , interrupts, traps, SMIs, and VM exits may occur while 
executing inside an enclave. These events are referred to  as Enclave Exiting Events (EEE). Upon an EEE, the 
processor state is securely saved inside the enclave (in the thread’s current SSA frame) and then replaced by a 
synthetic state to prevent leakage of secrets. The process of securely saving state and establishing the synthetic 
state is called an Asynchronous Enclave Exit (AEX). De tails of AEX is described in Chapter 37, “Enclave Exiting 
Events.”
As part of most EEEs, the AEP is pushed onto the stack as the location of the eventing address. This is the location 
where control will return to after executing the IRET. The ERESUME leaf function can be executed from that point 
to reenter the enclave and resume execution from the interrupted point.
After AEX has completed, the logical processor is no long er in enclave mode and the exiting event is processed 
normally. Any new events that occur after the AEX has completed are treated as having occurred outside the 
enclave (e.g., a #PF in dispatching to an interrupt handler).
36.2.3 Resuming Execution After AEX
After system software has serviced the event that caused  the logical processor to exit an enclave, the logical 
processor can continue enclave execution using ERESUME. ERESUME restores processor state and returns control 
to where execution was interrupted. 
If the cause of the exit was an exception or a fault and was not resolved, the event will be triggered again if the 
enclave is re-entered using ERESUME. For example, if an enclave performs a divide by 0 operation, executing 
ERESUME will cause the enclave to attemp t to re-execute the faulting instruction and result in another divide by 0 
exception. Intel® SGX provides the means for an enclave developer to handle enclave exceptions from within the 
enclave. Software can enter the enclave at a different loca tion and invoke the exception handler within the enclave 
by executing the EENTER leaf function. The exception hand ler within the enclave can read the fault information 
from the SSA frame and attempt to resolve the faulting condit ion or simply return and indicate to software that the 
enclave should be terminated (e.g., using EEXIT).Vol. 3D 36-5ENCLAVE OPERATION
36.2.3.1  ERESUME Interaction
ERESUME restores registers depending on the mode of the enclave (32 or 64 bit).
•In 32-bit mode (IA32_EFER.LMA = 0 || CS.L = 0), the low 32-bits of the legacy regist ers (EAX, EBX, ECX, EDX, 
ESP, EBP, ESI, EDI, EIP, and EFLAGS) are restored fr om the thread’s GPR area of the current SSA frame. 
Neither the upper 32 bits of the legacy registers nor the 64-bit registers (R8 … R15) are loaded. 
•In 64-bit mode (IA32_EFER.LMA = 1 && CS.L = 1), all 64 bits of the general processor registers (RAX, RBX, 
RCX, RDX, RSP, RBP, RSI, RDI, R8 … R15, RIP, and RFLAGS) are loaded.
Extended features specified by SECS.ATTRIBUTES.XFRM are restored from the XSAVE area of the current SSA 
frame. The layout of the x87 area depends on  the current values of IA32_EFER.LMA and CS.L:
•IA32_EFER.LMA = 0 || CS.L = 0
— 32-bit load in the same format that XSAVE/FXSAVE uses with these values.
•IA32_EFER.LMA = 1 && CS.L = 1— 64-bit load in the same format that XSAVE/FX SAVE uses with these values as if REX.W = 1.
36.2.3.2  Asynchronous Encl ave Exit Notify and EDECCSSA
Asynchronous Enclave Exit Notify (AEX-Notify) is an exte nsion to Intel SGX that allows Intel SGX enclaves to be 
notified after an asynchronous enclave exit (AEX) has oc curred. EDECCSSA is a new Intel SGX user leaf function 
(ENCLU[EDECCSSA]) that can facilitate AEX notification hand ling, as well as software exception handling. This 
section provides information about changes to the Intel SGX architecture that support AEX-Notify and 
ENCLU[EDECCSSA].
NOTE
On some platforms, AEX-Notify and the EDECCSSA  user leaf function may be enumerated by 
CPUID following a microcode update.
The following list summarizes the additions to existing  Intel SGX data structures to support AEX-Notify:
•SECS.ATTRIBUTES.AEXNOTIFY: This enclave supports AEX-Notify.
•TCS.FLAGS.AEXNOTIFY: This enclave thread may receive AEX notifications.
•SSA.GPRSGX.AEXNOTIFY: Enclave-writable byte that allo ws enclave software to dynamically enable/disable 
AEX notifications.
An AEX notification is delivered by ENCLU[ERESUME] when the following conditions are met:
1. TCS.FLAGS.AEXNOTIFY is set.
2. TCS.CSSA (the current slot index of an SSA frame) is greater than zero.
3. TCS.SSA[TCS.CSSA-1].GPRSGX.AEXNOTIFY[0] is set.
Note that AEX increments TCS.CSSA, and ENCLU[ERESUME] decrements TCS.CSSA, except when an AEX notifica-
tion is delivered. Instead of decrementing TCS.CSSA an d restoring state from the SSA, ENCLU[ERESUME] delivers 
an AEX notification by behaving as ENCLU[EENT ER]. Implications of this behavior include:
•The enclave thread is resumed at EnclaveBase + TCS.OENTRY.
•EAX contains the (non-decremented) value of TCS.CSSA.
•RCX contains the address of the IP following ENCLU[ERESUME].
•The architectural state saved by the most recent AEX is preserved in TCS.SSA[TCS.CSSA-1].
The enclave thread can return to the previous SSA co ntext by invoking ENCLU[EDECCSSA], which decrements 
TCS.CSSA.36-6 Vol. 3DENCLAVE OPERATION
36.3 CALLING ENCLAVE PROCEDURES
36.3.1 Calling Convention
In standard call conventions subroutine parameters are ge nerally pushed onto the stack. The called routine, being 
aware of its own stack layout, knows how to find parame ters based on compile-time-computable offsets from the 
SP or BP register (depending on runtime conventions used by the compiler).
Because of the stack switch when calling an enclave, stack-located parameters cannot be found in this manner. 
Entering the enclave requires a modified parameter passing convention.
For example, the caller might push parameters onto the untrusted stack and then pass a pointer to those parame-
ters in RAX to the enclave software. The exact choice of ca lling conventions is up to the writer of the edge routines; 
be those routines hand-coded or compiler generated. 
36.3.2 Register Preservation
As with most systems, it is the responsibility of the callee  to preserve all registers except that used for returning a 
value. This is consistent with conventional usage and tend s to optimize the number of register save/restore opera-
tions that need be performed. It has the additional securi ty result that it ensures that data is scrubbed from any 
registers that were used by enclave to temporarily contain secrets.
36.3.3 Returning to Caller
No registers are modified during EEXIT. It is the responsibility of software to remove secrets in registers before executing EEXIT.
36.4 INTEL® SGX KEY AND ATTESTATION
36.4.1 Enclave Measurement and Identification
During the enclave build process, two “measurements” ar e taken of each enclave and are stored in two 256-bit

During the enclave build process, two “measurements” ar e taken of each enclave and are stored in two 256-bit 
Measurement Registers (MR): MRENCLAVE and MRSIGNER. MRENCLAVE represents the enclave's contents and 
build process. MRSIGNER represents the en tity that signed the enclave's SIGSTRUCT.
The values of the Measurement Registers are included in atte stations to identify the enclave to remote parties. The 
MRs are also included in most keys, binding keys to enclaves with specific MRs. 
36.4.1.1  MRENCLAVE
MRENCLAVE is a unique 256 bit value that identifies the code  and data that was loaded into the enclave during the 
initial launch. It is computed as a SHA256 hash that is initialized by the ECREATE leaf function. EADD and EEXTEND 
leaf functions record information about each page and the content of those pages. The EINIT leaf function finalizes 
the hash, which is stored in SECS.MRENCLAVE. Any tamper ing with the build process, contents of a page, page 
permissions, etc will result in a different MRENCLAVE value. 
Figure 36-2 illustrates a simplified flow of changes to  the MRENCLAVE register when building an enclave:
•Enclave creation with ECREATE.
•Copying a non-enclave source page into the EPC of an un-initialized enclave with EADD.
•Updating twice of the MRENCLAVE after modifying the enclave’s page content, i.e., EEXTEND twice.
•Finalizing the enclave build with EINIT.
Details on specific values inserted in the hash ar e available in the individual instruction definitions.Vol. 3D 36-7ENCLAVE OPERATION
36.4.1.2  MRSIGNER
Each enclave is signed using a 3072 bit RSA key. The signature is stored in the SIGSTRUCT. In the SIGSTRUCT, the 
enclave's signer also assigns a product ID (ISVPRODID ) and a security version (ISVSVN) to the enclave. 
MRSIGNER is the SHA-256 hash of the signer's public key.  For platforms that support Key Separation and Sharing 
(CPUID.(EAX=12H, ECX=1).EAX.KSS[7]) th e SIGSTRUCT can additionally specify an 16 byte extended product ID 
(ISVEXTPRODID), and a 16 byte  family ID (ISVFAMILYID).
In attestation, MRSIGNER can be used to allow software to  approve of an enclave based on the author rather than 
maintaining a list of MRENCLAVEs. It is used in key deriva tion to allow software to create a lineage of an applica-
tion. By signing multiple enclaves with the same key, th e enclaves will share the same keys and data. Combined 
with security version numbering, the author can release mu ltiple versions of an application which can access keys 
for previous versions, but not future versions of that application.
36.4.1.3  CONFIGID
For platforms that support enhancements for key separa tion and sharing (CPUID.(EAX=12H, ECX=1).EAX.KSS[7]) 
when the enclave is created the platform can additional ly provide 32-byte configuration identifier (CONFIGID). 
How this value is used is dependent on the enclave but it is intended to allow enclave creators to indicate what 
additional content may be accepted by the enclave post-initialization.
36.4.2 Security Version Numbers (SVN) 
Intel® SGX supports a versioning system that allows the si gner to identify different versions of the same software 
released by an author. The security version is independent of the functional version an author uses and is intended 
to specify security equivalence. Multip le releases with functional enhancements may all share the same SVN if they 
all have the same security properties or posture. Each enclave has an SVN and the underlying hardware has an SVN.
The SVNs are attested to in EREPORT and are included in the derivation of most keys, thus providing separation 
between data for older/newer versions. Figure 36-2.  Measurement Flow of Enclave Build ProcessSHA_INIT
MRENCLAVESHA_UPDATE
MRENCLAVESHA_FINAL
MRENCLAVEPage
MetadataData
Chunk 1Data
Chunk 2Chunk 1
MetadataChunk 2
Metadata
ECREATE EADD EEXTEND EEXTEND EINIT36-8 Vol. 3DENCLAVE OPERATION
36.4.2.1  Enclave Security Version
In the SIGSTRUCT, the MRSIGNER is associated with a 16-bit Product ID (ISVPRODID) and a 16 bit integer SVN 
(ISVSVN). Together they define a specific group of versions of a specific product. Most keys, including the Seal Key, 
can be bound to this pair. 
To support upgrading from one release to another, EGETKEY will return keys corresponding to any value less than 
or equal to the software's ISVSVN.
36.4.2.2  Hardware Security Version
CPUSVN is a 128 bit value that reflects the microcode up date version and authenticated code modules supported 
by the processor. Unlike ISVSVN, CPUSVN  is not an integer and cannot be compared mathematically. Not all values 
are valid CPUSVNs. 
Software must ensure that the CPUSVN provided to EG ETKEY is valid. EREPORT will return the CPUSVN of the 
current environment. Software can execute EREPORT with TARGETINFO set to zeros to retrieve a CPUSVN from 
REPORTDATA. Software can access keys for a CPUSVN record ed previously, provided that each of the elements 
reflected in CPUSVN are the same or have been upgraded.
36.4.2.3  CONFIGID Security Version
The CONFIGID field can be used to contain the hash of a si gning key for verifying the additional content. In this 
case, similar to the relationship between MRSIGNER and ISVSVN, CONFIGID needs a CONFIGID Security Version 
Number. CONFIGIDSVN can be specifie d at the same time as CONFIGID.
36.4.3 Keys
Intel® SGX provides software with access to keys unique to each processor and rooted in HW keys inserted into the 
processor during manufacturing. 
Each enclave requests keys using the EGETKEY leaf func tion. The key is based on enclave parameters such as 
measurement, the enclave signing key, se curity attributes of the enclave, and the Hardware Security version of the 
processor itself. A full list of parameter options is spec ified in the KEYREQUEST structure, see details in Section 
35.18. 
By deriving keys using enclave properties, SGX guarantees that if two enclaves call EGETKEY, they will receive a 
unique key only accessible by the respective enclave. It al so guarantees that the enclave will receive the same key 
on every future execution of EGETKEY. Some parameters ar e optional or configurable by software. For example, a 
Seal key can be based on the signer of the enclave, resulting in a key available to multiple enclaves signed by the 
same party.
The EGETKEY leaf function provides several key types. Ea ch key is specific to the processor, CPUSVN, and the 
enclave that executed EGETKEY. The EGETKEY instruction defi nition details how each of these keys is derived, see 
Table 38-66. Additionally,
•SEAL Key: The Seal key is a general purpose key for the enclave to use to protect secrets. Typical uses of the 
Seal key are encrypting and calculating MAC of secrets on disk. There are 2 types of Seal Key described in Section 36.4.3.1. 
•REPORT Key: This key is used to compute the MAC on th e REPORT structure. The EREPORT leaf function is used 
to compute this MAC, and destination enclave uses the Re port key to verify the MAC. The software usage flow 
is detailed in Section 36.4.3.2. 
•EINITTOKEN_KEY: This key is used by Launch Enclaves  to compute the MAC on EINITTOKENs. These tokens are 
then verified in the EINIT leaf function. The ke y is only available to enclaves with ATTRIBUTE. EINITTOKEN_KEY  set 
to 1. 
•PROVISIONING Key and PROVISIONING SEAL Key: These keys are used by attestation key provisioning 
software to prove to remote parties that the processo r is genuine and identify the currently executing TCB. 
These keys are only available to enclaves  with ATTRIBUTE.PROVISIONKEY set to 1.Vol. 3D 36-9ENCLAVE OPERATION
36.4.3.1  Sealing Enclave Data
Enclaves can protect persistent data using Seal keys to  provide encryption and/or integrity protection. EGETKEY 
provides two types of Seal keys specified in KE YREQUEST.KEYPOLICY field: MRENCLAVE-based key and 
MRSIGNER-based key. 
The MRENCLAVE-based keys are available only to encl ave instances sharing the same MRENCLAVE. If a new 
version of the enclave is released, the Seal keys will be di fferent. Retrieving previous data requires additional soft-
ware support.
The MRSIGNER-based keys are bound to the 3 tuple (MRS IGNER, ISVPRODID, ISVSVN). These keys are available 
to any enclave with the same MRSIGNER and ISVPRODID an d an ISVSVN equal to or greater than the key in ques-
tions. This is valuable for allowing new versions of the same software to retrieve keys created before an upgrade.
four additional key policies for seal key derivation ar e provided. These add the ISVEXTPRODID, ISVFAMILYID, and 
CONFIGID/CONFIGSVN to the key derivation. Additionally, th ere is a policy to remove ISVPRODID from a key deri-
vation to create a shared between different  products that share the same MRSIGNER.
36.4.3.2  Using REPORTs for Local Attestation
Intel SGX provides a means for enclaves to securely identify  one another, this is referred to as “Local Attestation”.

Intel SGX provides a means for enclaves to securely identify  one another, this is referred to as “Local Attestation”. 
SGX provides a hardware assertion, REPORT that contains calling enclaves Attributes, Measurements and User 
supplied data (described in detail in Section 35.16).  Figure 36-3 shows the basic flow of information.
1. The source enclave determines the identity of  the target enclave to populate TARGETINFO. 
2. The source enclave calls EREPORT instruction to generate a REPORT structure. The EREPORT instruction 
conducts the following:
— Populates the REPORT with identify information about the calling enclave. — Derives the Report Key that is returned when th e target enclave executes the EGETKEY. TARGETINFO 
provides information about the target.
— Computes a MAC over the REPORT usin g derived target enclave Report Key.
3. Non-enclave software copies the REPORT from source to destination. 
4. The target enclave executes the EGETKEY instruction to request its REPORT key, which is the same key used by 
EREPORT at the source. 
5. The target enclave verifies the MAC and can then inspect the REPORT to identify the source.
Figure 36-3.   SGX Local AttestationEREPORT
REPORT
SoftwareVerify REPORT(Symmetric Key)Source Enclave
Destination Enclave
EGETKEY
REPORT KEY
(Symmetric Key)
HardwareLegend:TARGETINFO36-10 Vol. 3DENCLAVE OPERATION
36.5 EPC AND MANAGEMENT OF EPC PAGES
EPC layout is implementation specific, and is enumerated  through CPUID (see Table 34-7 for EPC layout). EPC is 
typically configured by BIOS at system boot time.
36.5.1 EPC Implementation
EPC must be properly protected against attacks. One ex ample of EPC implementation could use a Memory Encryp-
tion Engine (MEE). An MEE provides a cost-effective mech anism of creating cryptographically protected volatile 
storage using platform DRAM. These units provide integrit y, replay, and confidentiality protection. Details are 
36.5.2 OS Management of EPC Pages
The EPC is a finite resource. SGX1 (i.e., CPUID. (EAX=12H, ECX=0):EAX.SGX1 = 1 but CPUID.(EAX=12H, 
ECX=0):EAX.SGX2 = 0) provides the EPC manager with leaf functions to manage this resource and properly swap 
pages out of and into the EPC. For that, the EPC manager would need to keep track of all EPC entries, type and 
state, context affiliation, and SECS affiliation.
Enclave pages that are candidates for eviction should be  moved to BLOCKED state using EBLOCK instruction that 
ensures no new cached virtual to physical address mappin gs can be created by attempts to reference a BLOCKED 
page.
Before evicting blocked pages, EPC manager should execute ETRACK leaf function on that enclave and ensure that 
there are no stale cached virtual to physical address mapp ings for the blocked pages remain on any thread on the 
platform.
After removing all stale translations from blocked pages,  system software should use the EWB leaf function for 
securely evicting pages out of the EPC. EWB encrypts a page in the EPC, writes it to unprotected memory, and 
invalidates the copy in EPC. In addition, EWB also create s a cryptographic MAC (PCMD.MAC) of the page and stores 
it in unprotected memory. A page can be reloaded back to the processor only if the data and MAC match. To ensure 
that only the latest version of the evicted page can be loaded back, the version of the evicted page is stored 
securely in a Version Array (VA) in EPC.
SGX1 includes two instructions for reloading pages that have been evicted by system software: ELDU and ELDB. 
The difference between the two instructions is the value of  the paging state at the end of the instruction. ELDU 
results in a page being reloaded and se t to an UNBLOCKED state, while ELDB results in a page loaded to a BLOCKED 
state.
ELDB is intended for use by a Virtual Machine Monitor (VMM). When a VMM reloads an evicted page, it needs to 
restore it to the correct state of the page (BLOCKED vs . UNBLOCKED) as it existed at the time the page was 
evicted. Based on the state of the page at ev iction, the VMM chooses either ELDB or ELDU.
36.5.2.1  Enhancement to Managing EPC Pages
On processors supporting SGX2 (i.e., CPUID.(EAX= 12H, ECX=0):EAX.SGX2 = 1), th e EPC manager can manage 
EPC resources (while enclave is running) with more flexibi lity provided by the SGX2 leaf functions. The additional 
flexibility is described in Sectio n 36.5.7 through Section 36.5.11.
36.5.3 Eviction of Enclave Pages
Intel SGX paging is optimized to allow the Operating Syst em (OS) to evict multiple pages out of the EPC under a 
single synchronization.
The suggested flow for evicting a list of pages from the EPC is: 
1. For each page to be evicted from the EPC:
a. Select an empty slot in a Version Array (VA) page.
•If no empty VA page slots exist, create a new VA page using the EPA leaf function.Vol. 3D 36-11ENCLAVE OPERATION
b. Remove linear-address to physical -address mapping from the enclave context’s mapping tables (page table 
and EPT tables). 
c. Execute the EBLOCK leaf function for the target page. This sets the target page state to BLOCKED. At this 
point no new mappings of the page will be created. So any access which does not have the mapping cached in the TLB will generate a #PF.
2. For each enclave containing pages selected in step 1:
— Execute an ETRACK leaf function pointing to that en clave’s SECS. This initiates the tracking process that 
ensures that all caching of linear-address to physical-address translations for the blocked pages is cleared.
3. For all logical processors executing in processes (OS) or guests (VMM) that contain the enclaves selected in 
step 1:
— Issue an IPI (inter-processor interrupt) to those threads. This causes those logical processors to asynchro-
nously exit any enclaves they might be in, and as a result flush cached linear-address to physical-address translations that might hold stale translations to blocked pages. There is no need for additional measures 
such as performing a “TLB shootdown”.
4. After enclaves exit, allow logical processors to resume  normal operation, including enclave re-entry as the 
tracking logic keeps track of the activity. 
5. For each page to be evicted:
— Evict the page using the EWB leaf function with para meters include the effective-address pointer to the EPC 
page, the VA slot, a 4K byte buffer to hold the encrypte d page contents, and a 128 byte buffer to hold page 
metadata. The last three elements are tied together cr yptographically and must be used to later reload the 
page.
At this point, system software has the only copy of ea ch page data encrypted with its page metadata in main 
memory. 
36.5.4 Loading an Enclave Page
To reload a previously evicted page, system software n eeds four elements: the VA slot used when the page was 
evicted, a buffer containing the encrypted page contents , a buffer containing the page metadata, and the parent 
SECS to associate this page with. If the VA page or th e parent SECS are not already in the EPC, they must be 
reloaded first.
1. Execute ELDB/ELDU (depending on the desired BLOCKED state for the page), passing as parameters: the EPC 
page linear address, the VA slot, the encrypted page, and the page metadata. 
2. Create a mapping in the enclave context’s mapping tables  (page tables and EPT tables) to allow the application 
to access that page (OS: system page table; VMM: EPT).
The ELDB/ELDU instruction marks the VA  slot empty so that the page cannot be replayed at a later date.
36.5.5 Eviction of an SECS Page
The eviction of an SECS page is similar to the eviction of an enclave page. The only difference is that an SECS page 
cannot be evicted until all other pages belonging to the en clave have been evicted. Since all other pages have been 
evicted, there will be no threads executing inside the enclave and tracking with ETRACK isn’t necessary. When 
reloading an enclave, the SECS page must be  reloaded before all other constituent pages.
1. Ensure all pages are evicted from enclave. 2. Select an empty slot in a Version Array page. 
— If no VA page exists with an empty slot, create a new one using the EPA function leaf. 
3. Evict the page using the EWB leaf function with para meters include the effective-address pointer to the EPC 
page, the VA slot, a 4K byte buffer to hold the encr ypted page contents and a 128 byte buffer to hold page 
page.36-12 Vol. 3DENCLAVE OPERATION
36.5.6 Eviction of a Version Array Page
VA pages do not belong to any enclave and tracking with ETRACK isn’t necessary. When evicting the VA page, a slot 
in a different VA page must be specified in orde r to provide versioning of the evicted VA page. 
1. Select a slot in a Version Array page other than the page being evicted. 
— If no VA page exists with an empty slot, create a new one using the EPA leaf function. 
2. Evict the page using the EWB leaf function with para meters include the effective-address pointer to the EPC 
page, the VA slot, a 4K byte buffer to hold the encrypte d page contents, and a 128 byte buffer to hold page

page.
36.5.7 Allocating a Regular Page
On processors that support SGX2, allocating a new page  to an already initialized enclave is accomplished by 
invoking the EAUG leaf function. Typically, the enclave re quests that the OS allocates a new page at a particular 
location within the enclave’s address space. Once allocate d, the page remains in a pending state until the enclave 
executes the corresponding EACCEPT leaf function to accept  the new page into the enclave. Page allocation opera-
tions may be batched to improve efficiency. 
The typical process for allocating a regular page is as follows: 
1. Enclave requests additional memory from OS wh en the current allocation becomes insufficient. 
2. The OS invokes the EAUG leaf function to  add a new memory page to the enclave. 
a. EAUG may only be called on a free EPC page. b. Successful completion of the EAUG instruction places  the target page in the VALID and PENDING state. 
c. All dynamically created pages have the type PT_REG and content of all zeros. 
3. The OS maps the page in the enclave context's mapping tables.4. The enclave issues an EACCEPT instruction, which verifies the page’s attributes and clears the PENDING state. 
At that point the page becomes accessible for normal enclave use. 
36.5.8 Allocating a TCS Page 
On processors that support SGX2, allocating a new TCS page to an already initialized enclave is a two-step process. 
First the OS allocates a regular page with a call to EAUG. This page must then be accepted and initialized by the 
enclave to which it belongs. Once the page has been init ialized with appropriate values for a TCS page, the enclave 
requests the OS to change the page’s type to PT_TCS. Th is change must also be accepted. As with allocating a 
regular page, TCS allocation operations may be batched. 
A typical process for allocating a TCS page is as follows: 
1. Enclave requests an additional page from the OS. 
2. The OS invokes EAUG to add a new regular memory page to the enclave. 
a. EAUG may only be called on a free EPC page. 
b. Successful completion of the EAUG instruction places  the target page in the VALID and PENDING state. 
3. The OS maps the page in the enclave context's mapping tables.4. The enclave issues an EACCEPT instruction, at which po int the page becomes accessible for normal enclave use. 
5. The enclave initializes the contents of the new page. 
6. The enclave requests that the OS conver t the page from type PT_REG to PT_TCS. 
7. OS issues an EMODT instruction on the page. 
a. The parameters to EMODT indicate that the regular page should be converted into a TCS. Vol. 3D 36-13ENCLAVE OPERATION
b. EMODT forces all access rights to a page to be removed because TCS pages may not be accessed by enclave 
code. 
8. The enclave issues an EACCEPT instructio n to confirm the requested modification. 
36.5.9 Trimming a Page 
On processors that support SGX2, Intel SGX supports the trimming of an enclave page as a special case of EMODT. 
Trimming allows an enclave to actively participate in th e process of removing a page from the enclave (dealloca-
tion) by splitting the process into first removing it from  the enclave's access and then removing it from the EPC 
using the EREMOVE leaf function. The page type PT_TRIM indicates that a page has been trimmed from the 
enclave’s address space and that the page is no longer accessible to enclave software. Modifications to a page in 
the PT_TRIM state are not permitted; the page must be re moved and then reallocated by  the OS before the enclave 
may use the page again. Page deallocation oper ations may be batched to improve efficiency. 
The typical process for trimming a page from an enclave is as follows: 
1. Enclave signals OS that a particular page is no longer in use. 2. OS invokes the EMODT leaf function on the page, requesting that the pa ge’s type be changed to PT_TRIM. 
a. SECS and VA pages cannot be trimmed in this way, so  the initial type of the page must be PT_REG or 
PT_TCS.
b. EMODT may only be called on valid enclave pages.
3. OS invokes the ETRACK leaf function on the enclave containing the page to track removal the TLB addresses 
from all the processors.
4. Issue an IPI (inter-processor interrupt) to flush the stale linear-address to physical-address translations for all 
logical processors executing in processes that contain the enclave.
5. Enclave issues an EACCEPT leaf function. 6. The OS may now permanently remove the page from the EPC (b y issuing EREMOVE). 
36.5.10 Restricting the EPCM Permissions of a Page 
On processors that support SGX2, restricting the EPCM permissions associated with an enclave page is accom-
plished using the EMODPR leaf function. This operation requires the cooperation of the OS to flush stale entries to 
the page and to update the page-table  permissions of the page to match. Permissions restriction operations may 
be batched. 
The typical process for restricting the permissions of an enclave page is as follows: 
1. Enclave requests that the OS to restrict the permissions of an EPC page. 
2. OS performs permission restriction, flushing cached linear-address to physical-address translations, and page-
table modifications.
a. Invokes the EMODPR leaf function to restrict permissions (EMODPR may only be called on VALID pages).
b. Invokes the ETRACK leaf function on the enclave cont aining the page to track removal of the TLB addresses 
from all the processor.
c. Issue an IPI (inter-processor interrupt) to flush the stale linear-address to physical-address translations for 
all logical processors executing in processes that contain the enclave.
d. Sends IPIs to trigger enclave thread exit and TLB shootdown. 
e. OS informs the Enclave that all logical processo rs should now see the new restricted permissions.
3. Enclave invokes the EACCEPT leaf function.
a. Enclave may access the page throughout the entire process.b. Successful call to EACCEPT guarantees that no stale cached linear-address to physical-address translations 
are present.36-14 Vol. 3DENCLAVE OPERATION
36.5.11 Extending the EPCM  Permissions of a Page 
On processors that support SGX2, extending the EPCM permissions associated with an enclave page is accom-
plished directly by the enclave using the EMODPE leaf function. After performing the EPCM  permission extension, 
the enclave requests the OS to update  the page table permissions to match the extended permission. Security 
wise, permission extension does not require enclave threads to leave the enclave as TLBs with stale references to 
the more restrictive permissions will be flushed on dema nd, but to allow forward progress, an OS needs to be 
aware that an application might signal a page fault. 
The typical process for extending the permis sions of an enclave page is as follows:
1. Enclave invokes EMODPE to extend the EPCM permission s associated with an EPC page (EMODPE may only be 
called on VALID pages).
2. Enclave requests that OS update the page tables to match the new EPCM permissions. 
3. Enclave code resumes.
a. If cached linear-address to physical-address translatio ns are present to the more restrictive permissions, 
the enclave thread will page fault. The SGX2-aware OS will see that the page tables permit the access and 
resume the thread, which can now successfully a ccess the page because exiting cleared the TLB. 
b. If cached linear-address to physical-address translatio ns are not present, access to the page with the new 
permissions will succeed without an enclave exit. 
36.5.12 VMM Oversubscription of EPC
On processors supporting oversubscription enhancemen ts (i.e., CPUID.(EAX=12H, ECX=0):EAX[5]=1 & EAX[6] = 
1) a Virtual Machine Monitor or other executive can more efficiently manage the EPC space available on the plat-
form between virtualized entities. A typical process for using these instructions to support oversubscribing the 
physical EPC space on the platform is as follows:
1. VMM creates data structures for SECS tracking including a count of child pages.
2. VMM selects possible EPC victim pages.3. VMM ages the victim pages. Some of the selected pages will be accessed by the guest. In this case the VMM will 
remove these pages from the victim pool and return them to the guest.
4. VMM makes remaining pages not present in EPT. It th en issues IPI on each page to remove TLB mappings.
5. For every EPC victim page the VMM obtains the victim's SECS page info using ERDINFO.
a. ENCLAVECONTEXT field in RDINFO structure will indica te the location of SECS, and the PAGE_TYPE field will 
indicate the page type.
b. Child pages of SECS can be evicted.c. SECS pages may be evicted if the child count is zero.
d. Some pages may be returned to active state depend ing on such things as page type or child count.
6. VMM increments its evicted page count for the SECS of each page (stored in the data structure created in 1).

7. If this is the first evicted page of that SECS, set Ma rker on SECS of the victim page (EINCVIRTCHILD). This 
locks the SECS in the guest. The guest cannot page out the SECS.
8. EBLOCK, ETRACK, EWB eviction sequence is executed for page.
9. After loading an SECS page back  in, the VMM will set the correct EN CLAVECONTEXT for the guest using 
ESETCONTEXT instruction.
36.6 CHANGES TO INSTRUCTION BEHAVIOR INSIDE AN ENCLAVE
This section covers instructions whose behavior changes when executed in enclave mode.Vol. 3D 36-15ENCLAVE OPERATION
36.6.1 Illegal Instructions
The instructions listed in Table 36-1 are ring 3 instructions  which become illegal when executed inside an enclave. 
Executing these instructions inside an enclave will generate an exception. 
The first row of Table 36-1 enumerates instructions th at may cause a VM exit for VMM emulation. Since a VMM 
cannot emulate enclave execution, execution of any of thes e instructions inside an enclave results in an invalid-
opcode exception (#UD) and no VM exit.
The second row of Table 36-1 enumerates I/O instructions th at may cause a fault or a VM exit for emulation. Again, 
enclave execution cannot be emulated, so execution of any of these instructions inside an enclave results in #UD.
The third row of Table 36-1 enumerates instructions that lo ad descriptors from the GDT or the LDT or that change 
privilege level. The former class is disallowed because encl ave software should not depend on the contents of the 
descriptor tables and the latter because enclave execution must be entirely with CPL = 3. Again, execution of any 
of these instructions inside an enclave results in #UD. 
The fourth row of Table 36-1 enumerates instructions that  provide access to kernel information from user mode 
and can be used to aid kernel exploits from within enclave.  Execution of any of these instructions inside an enclave 
results in #UD.
RDTSC and RDTSCP are legal inside an enclave for processors that support SGX2 (subject to the value of 
CR4.TSD). For processors which support SGX1 but not SGX2, RDTSC and RDTSCP will cause #UD.
RDTSC and RDTSCP instructions may cause a VM exit when inside an enclave.Software developers must take into account that the RDTSC/RDTSCP results are not immune to influences by other 
software, e.g., the TSC can be manipula ted by software outside the enclave.
36.6.2 RDRAND and RDSEED Instructions
These instructions may cause a VM exit if the “RDRAND exit ing” VM-execution control is 1. Unlike other instructions 
that can cause VM exits, these instructions are legal inside an enclave. As noted in Section 28.1 of the Intel® 64 
and IA-32 Architectures Software Deve loper’s Manual, Volume 3C, any VM exit originating on an instruction 
boundary inside an enclave sets bit 27 of the exit-reason fi eld of the VMCS. If a VMM receives a VM exit due to an 
attempt to execute either of these instructions determines (by that bit) that the execution was inside an enclave, 
it can do either of two things. It can clear the “RDRAND exiting” VM-execution contro l and execute VMRESUME; this 
will result in the enclave executing RDRAND  or RDSEED again, and this time a VM  exit will not occur. Alternatively, 
the VMM might choose to discontinue execution of this virtual machine.
NOTE
It is expected that VMMs that virtualize Intel SGX will not set “RDRAND exiting” to 1.
36.6.3 PAUSE Instruction
The PAUSE instruction may cause a VM exit from an enclave if the “PAUSE exiting” VM-exe cution control is 1. Unlike 
other instructions that can cause VM exits, the PAUSE instru ction is legal inside an enclave. If a VMM receives a VM 
exit due to the 1-setting of “PAUSE exiting”, it can do ei ther of two things. It can clear the “PAUSE exiting” VM-Table 36-1.  Illegal Instructions Inside an Enclave
 Instructions Result Comment
CPUID, GETSEC, RDPMC, SGDT, SIDT, SLDT, ST R, VMCALL, VMFUNC #UD Might cause VM exit.
IN, INS/INSB/INSW/INSD, OUT, OUTS/OUTSB/OUTSW/OUTSD #UD I/O fault may not safely recover. May require emulation.Far call, Far jump, Far Ret, INT n/INTO, IRET, LDS/LES/LFS/LGS/LSS, 
MOV to DS/ES/SS/FS/GS, POP DS/ES/SS/FS/GS, SYSCALL, 
SYSENTER #UD Access segment register could change privilege level.
SMSW #UD Might provide access to kernel information.
ENCLU[EENTER], ENCLU[ERESUME] #GP Cannot en ter an enclave from within an enclave.36-16 Vol. 3DENCLAVE OPERATION
execution control and execute VMRESUME; this will result in  the enclave executing PAUSE again, but this time a VM 
exit will not occur. Alternatively, the VMM might choose to discontinue execution of this virtual machine.
The PAUSE instruction may also cause a VM exit outside of  an enclave if the “PAUSE-loop exiting” VM-execution 
control is 1, but as the “PAUSE-loop exiting” control is ignored at CPL > 0 (see Section 26.1.3), VM exit from an 
enclave due to the 1-setting of “P AUSE-LOOP exiting”  will never occur.
NOTE
It is expected that VMMs that virtualize Intel SGX will not set “PAUSE exiting” to 1.
36.6.4 Executions of INT1 and INT3 Inside an Enclave
The INT1 and INT3 instructions are legal inside an enclave,  however, their behavior inside an enclave differs from 
that outside an enclave. See Section 40.4.1 for details.
36.6.5 INVD Handling when Enclaves Are Enabled
Once processor reserved memory protections are activated (see Section 36.5), any execution of INVD will result in a #GP(0).Vol. 3D 37-1ENCLAVE EXITING EVENTS
CHAPTER 37
Certain events, such as exceptions and interrupts, incident to (but asynchronous with) enclave execution may 
cause control to transition outside of enclave mode. (Mos t of these also cause a change of privilege level.) To 
protect the integrity and security of the enclave, the pr ocessor will exit the enclave (and enclave mode) before 
invoking the handler for such an event. For that reason, such events are called enclave-exiting events  (EEE); 
EEEs include external interrupts, non-maskable interr upts, system-management interrupts, exceptions, and VM 
exits.
The process of leaving an enclave in response to an EEE is called an asynchronous enclave exit  (AEX). To protect 
the secrecy of the enclave, an AEX saves the state of cert ain registers within enclave memory and then loads those 
registers with fixed values called synthetic state .
37.1 COMPATIBLE SWITCH TO  THE EXITING STACK OF AEX
AEXs load registers with a pre-determined synthetic state. These registers may be later pushed onto the appro-
priate stack in a form as defined by the enclave-exitin g event. To allow enclave execution to resume after the 
invoking handler has processed the enclave exiting event,  the asynchronous enclave exit loads the address of 
trampoline code outside of the enclave into RIP. This tr ampoline code eventually retu rns to the enclave by means 
of an ENCLU(ERESUME) leaf function. Prior to exiting th e enclave the RSP and RBP registers are restored to their 
values prior to enclave entry.
The stack to be used is chosen using the same rules as for non-SGX mode:
•If there is a privilege level change, the stack will be the one associated with the new ring. 
•If there is no privilege level change, the current application stack is used. 
•If the IA-32e IST mechanism is used, the exit stack is chosen using that method.
Figure 37-1.  Exit Stack Just After Interrupt with Stack SwitchENCLU[ERESUME]
RAXCurrent SSA FramePer-Thread
Trampoline in uRTS
RSP after pushesCSSA
AEPTCS
Exit Stack
SS
RSP
RFLAGS
CS
RIP
Error Code (optional)uRSP
AEP
RSPTCS LAENCLU[ERESUME]
RCXRBXNext SSA Frame
uRSP37-2 Vol. 3DENCLAVE EXITING EVENTS
In all cases, the choice of exit stack and the informatio n pushed onto it is consistent with non-SGX operation. 
Figure 37-1 shows the Application and Exiting Stacks after an exit with a stack switch. An exit without a stack switch uses the Application Stack. The ERESUME leaf index value is placed into RAX, the TCS pointer is placed in 
RBX and the AEP (see below) is placed into RCX to facilitate resuming the enclave after the exit.
Upon an AEX, the AEP (Asynchronous Exit Pointer) is load ed into the RIP. The AEP points to a trampoline code 
sequence which includes the ERESUME instruction that is later used to reenter the enclave. 
The following bits of RFLAGS are cleared before RFLAGS is pushed onto the exit stack: CF, PF, AF, ZF, SF, OF, RF. The 
remaining bits are left unchanged.
37.2 STATE SAVING BY AEX
The State Save Area holds the processor state at the time of an AEX. To allow handling events within the enclave 
and re-entering it after an AEX, the SSA can be a stac k of multiple SSA frames as illustrated in Figure 37-2.
The location of the SSA frames to be used is controll ed by the following variables in the TCS and the SECS:
•Size of a frame in the State Save Area (SECS.SSAFRAMESIZE): This defines the number of 4-KByte pages in a 
single frame in the State Save Area. The SSA frame size must be large enough to ho ld the GPR state, the XSAVE

single frame in the State Save Area. The SSA frame size must be large enough to ho ld the GPR state, the XSAVE 
state, and the MISC state. 
•Base address of the enclave (SECS.B ASEADDR): This defines the enclave's base linear address from which the 
offset to the base of the SSA stack is calculated. 
•Number of State Save Area Slots (TCS.NSSA): This defines the total number of slots (frames) in the State Save 
Area stack. 
•Current State Save Area Slot (TCS.CSSA): This defines the slot to use on the next exit. 
•State Save Area Offset (TCS.OSSA): This defines the offset of the base address of a set of State Save Area slots 
from the enclave’s base address.
When an AEX occurs, hardware selects the SSA frame to us e by examining TCS.CSSA. Processor state is saved into 
the SSA frame (see Section 37.4) and loaded with a synt hetic state (as described in Section 37.3.1) to avoid 
leaking secrets, RSP and RBP are restored to their values prior to enclave entry, and TCS.CSSA is incremented. As 
will be described later, if an exception takes the last slot, it will not be possible to reenter the enclave to handle the Figure 37-2.  The SSA Stack Current 
SECS.SSAFRAMESIZE  TCS
NSSA
CSSA
OSSA
(in pages)MISC_N-1GRP_N-1
GPR_1XSAVE_N-1
XSAVE_1MISC_1
XAVE_0MISC_0GRP_0SSA Stack
SSA FramVol. 3D 37-3ENCLAVE EXITING EVENTS
exception from within the enclave. A subsequent ERES UME restores the processor state from the current SSA 
frame and frees the SSA frame.
The format of the XSAVE section of SSA is identical to the format used by the XSAVE/XRSTOR instructions. On 
EENTER, CSSA must be less than NSSA, ensuring that there is  at least one State Save Area slot available for exits. 
If there is no free SSA frame when executing EENTER, the entry will fail.
37.3 SYNTHETIC STATE ON ASYNCHRONOUS ENCLAVE EXIT
37.3.1 Processor Synthetic State on Asynchronous Enclave Exit
Table 37-1 shows the synthetic state loaded on AEX. The values shown are the lower 32 bits when the processor is 
in 32 bit mode and 64 bits when the processor is in 64 bit mode.
37.3.2 Synthetic State for Extended Features
When CR4.OSXSAVE = 1, extended features (those contro lled by XCR0[63:2]) are set to their respective INIT 
states when this corresponding bit of SECS.XFRM is set. The INIT state is the state that would be loaded by the 
XRSTOR instruction had the instruction mask and the XSTATE_BV field of the XSAVE header each contained the 
value XFRM. (When the AEX occurs in 32-bit mode, those fe atures that do not exist in 32-bit mode are unchanged.)Table 37-1.  GPR, x87 Synthetic States on Asynchronous Enclave Exit
Register Value
RAX 3 (ENCLU[3] is ERESUME).RBX Pointer to TCS of in terrupted enclave thread.
RCX AEP of interrupted enclave thread.RDX, RSI, RDI 0.RSP Restored from SSA.uRSP.RBP Restored from SSA.uRBP.R8-R15 0 in 64-bit mode; unchanged in 32-bit mode.RIP AEP of interrupted enclave thread.RFLAGS CF, PF, AF, ZF, SF, OF, RF bits are cleared. All other bits are left unchanged.x87/SSE State Unless otherwise listed here, all x87 and SSE stat e are set to the INIT state. The INIT state is the state 
that would be loaded by the XRSTOR instruction with  bits 1:0 both set in th e requested feature bitmask 
(RFBM), and both clear in XSTATE_BV the XSAVE header.
FCW On #MF exception: set to 037EH. On all other exits: set to 037FH.FSW On #MF exception: set to 8081H. On all other exits: set to 0H.MXCSR On #XM exception: set to 1F01H.  On all other exits: set to 1FB0H.
CR2 If the event that caused the AEX is a #PF, and the #PF does not directly cause a VM exit, then the low 
12 bits are cleared. 
If the #PF leads directly to a VM exit, CR2 is not updated (usual IA behavior).Note: The low 12 bits are not cleare d if a #PF is encountered during th e delivery of the EEE that caused 
the AEX. This is because the #PF was not the EEE. 
FS, GS Restored to values as of most recent EENTER/ERESUME.37-4 Vol. 3DENCLAVE EXITING EVENTS
37.3.3 Synthetic State for MISC Features
State represented by SECS.MISCSELECT might also be overri dden by synthetic state after it has been saved into 
the SSA. State represented by MISCSELECT[0] is not overridd en but if the exiting event is a page fault then lower 
12 bits of CR2 are cleared. 
37.4 AEX FLOW
On Enclave Exiting Events (interrupts, exceptions, VM exits or SMIs), the processor state is securely saved inside 
the enclave, a synthetic state is loaded and the enclave is  exited. The EEE then proceeds in the usual exit-defined 
fashion. The following sections describes the details of an AEX:
1. The exact processor state saved into the current SSA fr ame depends on whether the enclave is a 32-bit or a 64-
bit enclave. In 32-bit mode (IA32_EFER.LMA = 0 || CS.L = 0), the low 32 bits of the legacy registers (EAX, EBX, 
ECX, EDX, ESP, EBP, ESI, EDI, EIP, and EFLAGS) are st ored. The upper 32 bits of the legacy registers and the 
64-bit registers (R8 … R15) are not stored.
In 64-bit mode (IA32_EFER.LMA = 1 && CS.L = 1), all 64 bits of the general processor registers (RAX, RBX,
RCX, RDX, RSP, RBP, RSI, RDI, R8 … R15, RIP, and RFLAGS) are stored.
The state of those extended features specified by SE CS.ATTRIBUTES.XFRM are stored into the XSAVE area of
the current SSA frame. The layout of the x87 and XM M portions (the 1st 512 bytes) depends on the current
values of IA32_EFER.LMA and CS.L:
If IA32_EFER.LMA = 0 || CS.L = 0, the same format ( 32-bit) that XSAVE/FXSAVE uses with these values.
If IA32_EFER.LMA = 1 && CS.L = 1, the same format (64-bit) that XSAVE/FXSAVE uses with these values
when REX.W = 1. 
The cause of the AEX is saved in the EXITINFO field. See Table 35-10 for details and values of the various
fields.
The state of those miscellaneous features (see Section 35.7.2) specified by SECS.M ISCSELECT are stored into 
the MISC area of the current SSA frame.
If CET was enabled in the enclave, then the CET state of the enclave is saved in the CET state save area. If
shadow stacks were enabled in the enclave, then the SSP is also saved into the TCS.PREVSSP field.
2. Synthetic state is created for a number of processor registers to present an opaque view of the enclave state. 
Table 37-1 shows the values for GPRs, x87, SSE, FS, GS, Debug, and performance monitoring on AEX. The 
synthetic state for other extended features (those controlled by XCR0[62:2]) is set to their respective INIT 
states when their corresponding bit of SECS.ATTRIBUTES.XFRM  is set. The INIT state is that state as defined by 
the behavior of the XRSTOR instruct ion when HEADER.XSTATE_BV[n] is 0. Synthetic state of those miscella-
neous features specified by SECS.MIS CSELECT depends on the miscellaneous feature. There is no synthetic 
state required for the miscellaneous st ate controlled by SECS.MISCSELECT[0]. 
3. Any code and data breakpoints that were suppressed at the time of enclave entry are unsuppressed when 
exiting the enclave.
4. RFLAGS.TF is set to the value that it had at the time of the most recent enclave en try (except for the situation 
that the entry was opt-in for debug; see Section 40.2). In the SSA, RFLAGS.TF is set to 0. 
5. RFLAGS.RF is set to 0 in the synthetic state. In the SS A, the value saved is the same as what would have been 
saved on stack in the non-SGX case (architectural value of RF). Thus, AEXs due to interrupts, traps, and code 
breakpoints save RF unmodified into SSA, while AEXs due to other faults save RF as 1 in the SSA. 
If the event causing AEX happened on intermediate it eration of a REP-prefixed instruction, then RF=1 is
saved on SSA, irrespective of its priority.
6. Any performance monitoring activity (including PEBS) or  profiling activity (LBR, Tr acing using Intel PT) on the 
exiting thread that was suppressed due to the enclave entry on that thread is unsuppressed. Any counting that 
had been demoted from AnyThread counting to MyThread counting (on one logical processor) is promoted back 
to AnyThread counting.
7. The CET state of the enclosing application is restored to the state at the time of the most recent enclave entry, 
and if CET indirect branch tracking was enabled then th e indirect branch tracker is unsuppressed and moved to 
the WAIT_FOR_ENDBRANCH state.Vol. 3D 37-5ENCLAVE EXITING EVENTS
37.4.1 AEX Operational Detail
Temp Variables in AEX Operational Flow
The pseudo code in this section describes the internal oper ations that are executed when an AEX occurs in enclave 
mode. These operations occur just before the normal interrupt or exception processing occurs.
(* Save RIP for later use *)
TMP_RIP = Linear Address of Resume RIP(* Is the processor in 64-bit mode? *)TMP_MODE64 := ((IA32_EFER.LMA = 1) && (CS.L = 1));
(* Save all registers, When saving EFLAGS, the TF bit is set to 0 and
the RF bit is set to what would have been saved on stack in the non-SGX case *)
 IF (TMP_MODE64 = 0)
THEN
Save EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI, EFLAGS, EIP into the current SSA frame using 
CR_GPR_PA; (* see Table 38-5 for list of CREGs used to describe internal operation within Intel SGX *)
SSA.RFLAGS.TF := 0;

THEN
ELSE    (* TMP_MODE64 = 1 *) Save RAX, RBX, RCX, RDX, RSP, RBP, RSI, RDI, R8-R15, RFLAGS, RI P into the current SSA frame using 
CR_GPR_PA;
FI;Save FS and GS BASE into SSA using CR_GPR_PA;
(* store XSAVE state into the current SSA fram e's XSAVE area using the physical addresses 
that were determined and cached at encl ave entry time with CR_XSAVE_PAGE_i. *)
For each XSAVE state i defined by (SECS.ATTRIBUT ES.XFRM[i] = 1, destination address cached in 
CR_XSAVE_PAGE_i)
   SSA.XSAVE.i := XSAVE_STATE_i;
(* Clear bytes 8 to 23 of XSAVE_HEADER, i.e., the next 16 bytes after XHEADER_BV *)CR_XSAVE_PAGE_0.XHEADER_BV[191:64] := 0;(* Clear bits in XHEADER_BV[63:0] that  are not enabled in ATTRIBUTES.XFRM *)
CR_XSAVE_PAGE_0.XHEADER_BV[63:0] := 
CR_XSAVE_PAGE_0.XHEADER_BV[63:0] & SE CS(CR_ACTIVE_SECS).ATTRIBUTES.XFRM;
Apply synthetic state to GPRs, RFLAGS, extended features, etc.
(* Restore the RSP and RBP from the current SS A frame's GPR area using the physical address 
that was determined and cached at enclave entry time with CR_GPR_PA. *)
RSP := CR_GPR_PA.URSP;RBP := CR_GPR_PA.URBP;Name Type Size (bits) Description
TMP_RIP Effective Address 32/64 Address of instruct ion at which to resume execution on ERESUME.
TMP_MODE64 binary 1 ((IA32_EFE R.LMA = 1) && (CS.L = 1)).
TMP_BRANCH_RECORD LBR Record 2x64 From/To address to be pushed onto LBR stack.37-6 Vol. 3DENCLAVE EXITING EVENTS
(* Restore the FS and GS *)
FS.selector := CR_SAVE_FS.selector;FS.base := CR_SAVE_FS.base;FS.limit := CR_SAVE_FS.limit;FS.access_rights := CR_SAVE_FS.access_rights;GS.selector := CR_SAVE_GS.selector;GS.base := CR_SAVE_GS.base;GS.limit := CR_SAVE_GS.limit;GS.access_rights := CR_SAVE_GS.access_rights;
(* Examine exception code and update enclave internal states*)
exception_code := Exception or interrupt vector;
(* Indicate the exit reason in SSA *)
IF (exception_code = (#DE OR #DB OR #BP OR #BR OR #UD OR #MF OR #AC OR #XM ))
THEN
CR_GPR_PA.EXITINFO.VECTOR := exception_code;IF (exception code = #BP)
THEN CR_GPR_PA.EXITINFO.EXIT_TYPE := 6;ELSE CR_GPR_PA.EXITINFO.EXIT_TYPE := 3;
FI;CR_GPR_PA.EXITINFO.VALID := 1;
ELSE IF (exception_code is #PF or #GP )
THEN (* Check SECS.MISCSELECT using CR_ACTIVE_SECS *) IF (SECS.MISCSELECT[0] is set) 
THEN CR_GPR_PA.EXITINFO.VECTOR := exception_code; CR_GPR_PA.EXITINFO.EXIT_TYPE := 3; IF (exception_code is #PF) 
THEN 
SSA.MISC.EXINFO. MADDR := CR2; SSA.MISC.EXINFO.ERRCD := PFEC; SSA.MISC.EXINFO.RESERVED := 0; 
ELSE
SSA.MISC.EXINFO. MADDR := 0; SSA.MISC.EXINFO.ERRCD := GPEC; SSA.MISC.EXINFO.RESERVED := 0; 
FI; CR_GPR_PA.EXITINFO.VALID := 1; 
ELSE IF (exception code is #CP)
THEN
IF (SECS.MISCSELECT[1] is set)
THEN
CR_GPR_PA.EXITINFO.VECTOR := exception_code;CR_GPR_PA.EXITINFO.EXIT_TYPE := 3;CR_GPR_PA.EXITINFO.VALID := 1;SSA.MISC.EXINFO. MADDR := 0;SSA.MISC.EXINFO.ERRCD := CPEC;SSA.MISC.EXINFO.RESERVED := 0;
FI;
FI;
ELSEVol. 3D 37-7ENCLAVE EXITING EVENTS
CR_GPR_PA.EXITINFO.VECTOR := 0;
CR_GPR_PA.EXITINFO.EXIT_TYPE := 0CR_GPR_PA.REASON.VALID := 0;
FI;
(* Execution will resume at the AEP *)
RIP := CR_TCS_PA.AEP;
(* Set EAX to the ERESUME leaf index *)
EAX := 3;
(* Put the TCS LA into RBX for later use by ERESUME *)
RBX := CR_TCS_LA;
(* Put the AEP into RCX fo r later use by ERESUME *)
RCX := CR_TCS_PA.AEP;
(* Increment the SSA frame # *)
CR_TCS_PA.CSSA := CR_TCS_PA.CSSA + 1;
(* Restore XCR0 if needed *)
IF (CR4.OSXSAVE = 1)
THEN XCR0 := CR_SAVE_XCR0; FI;
Un-suppress all code breakpoints that are outside ELRANGEIF (CPUID.(EAX=12H, ECX=1):EAX[6]= 1)
THEN
IF (CR4.CET == 1 AND IA32_U_CET.SH_STK_EN == 1) 
THEN 
CR_CET_SAVE_AREA_PA.SSP := SSP; CR_TCS_PA.PREVSSP := SSP; 
FI;IF (CR4.CET == 1 AND IA32_U_CET.ENDBR_EN == 1) 
THEN 
CR_CET_SAVE_AREA_PA.TRACKER := IA32_U_CET.TRACKER;CR_CET_SAVE_AREA_PA.SUPPRESS := IA32_U_CET.SUPPRESS; 
FI;
FI;IF ((CPUID.(EAX=7H, ECX=0):EDX [CET_IBT] = 1) OR (CPUID.(EA X=7H, ECX=0):ECX[CET_SS] = 1)
THEN
(* restore enclosing applications CET state *) IA32_U_CET := CR_SAVE_IA32_U_CET;
IF (CPUID.(EAX=7, ECX=0):ECX[CET_SS])
SSP := CR_SAVE_SSP; FI;
(* If indirect branch tracking enabled for enclosing application *) 
(* then move the tracker to wait_for_endbranch *) IF (CR4.CET == 1 AND IA32_U_CET.ENDBR_EN == 1) 
THEN 
IA32_U_CET.TRACKER := WAIT_FOR_ENDBRANCH; IA32_U_CET.SUPPRESS := 0; 
FI;37-8 Vol. 3DENCLAVE EXITING EVENTS
FI;
(* Update the thread context to show not in enclave mode *)
CR_ENCLAVE_MODE := 0;
(* Assure consistent translations. *)
Flush linear context including TLBs and paging-structure caches
IF (CR_DBGOPTIN = 0)
THEN
Un-suppress all breakpoints that overlap ELRANGE(* Clear suppressed breakpoint matches *)Restore suppressed breakpoint matches(* Restore TF *)RFLAGS.TF := CR_SAVE_TF;Un-suppress monitor trap flag;Un-suppress branch recording facilities;Un-suppress all suppressed perf ormance monitoring activity;
Promote any sibling-thread counters that were de moted from AnyThread to MyThread during enclave 
entry back to AnyThread; 
FI;
IF the “monitor trap flag” VM-execution control is 1
THEN Pend MTF VM Exit at the end of exit; FI;
(* Clear low 12 bits of CR2 on #PF *)
IF (Exception code is #PF)
THEN CR2 := CR2 & ~0xFFF; FI;
(* end_of_flow *)
(* Execution continues with normal event processing. *)Vol. 3D 38-1INTEL® SGX INSTRUCTION REFERENCES
CHAPTER 38
INTEL ® SGX INSTRUCTION REFERENCES
This chapter describes the supervisor and user level instructions provided by Intel® Software Guard Extensions 
(Intel® SGX). In general, various functionality is encoded as  leaf functions within the ENCLS (supervisor), ENCLU 
(user), and the ENCLV (virtualization operation) instruct ion mnemonics. Different leaf functions are encoded by 
specifying an input value in the EAX regist er of the respective instruction mnemonic.
38.1 INTEL® SGX INSTRUCTION SYNTAX AND OPERATION
ENCLS, ENCLU, and ENCLV instruction mnemonics for all leaf functions are covered in this section.
For all instructions, the value of CS.D is ignored; addresse s and operands are 64 bits in 64-bit mode and are other-
wise 32 bits. Aside from EAX specifying the leaf number as  input, each instruction leaf may require all or some 
subset of the RBX/RCX/RDX as input parameters. Some leaf functions may return data or status information in one 
or more of the general purpose registers.
38.1.1 ENCLS Register Usage Summary
Table 38-1 summarizes the implicit register us age of supervisor mode enclave instructions.
Table 38-1.  Register Usag e of Privileged Enclave Instruction Leaf Functions
Instr. Leaf EAX RBX RCX RDX
ECREATE 00H (In) PAGEINFO (I n, EA) EPCPAGE (In, EA)
EADD 01H (In) PAGEINFO (In,  EA) EPCPAGE (In, EA)
EINIT 02H (In) SIGSTRUCT (In, EA) S ECS (In, EA) EINITTOKEN (In, EA)
EREMOVE 03H (In) EPCPAGE (In, EA)EDBGRD 04H (In) Result Data (Out) EPCPAGE (In, EA)EDBGWR 05H (In) Source Data (In) EPCPAGE (In, EA)EEXTEND 06H (In) SECS (In, EA) EPCPAGE (In, EA)ELDB 07H (In) PAGEINFO (In, EA) EPC PAGE (In, EA) VERSION (In, EA)
ELDU 08H (In) PAGEINFO (In, EA) EPC PAGE (In, EA) VERSION (In, EA)
EBLOCK 09H (In) EPCPAGE (In, EA)EPA 0AH (In) PT_VA (In) EPCPAGE (In, EA)EWB 0BH (In) PAGEINFO (I n, EA) EPCPAGE (In, EA) VERSION (In, EA)
ETRACK 0CH (In) EPCPAGE (In, EA)EAUG 0DH (In) PAGEINFO (In, EA) EPCPAGE (In, EA)EMODPR 0EH (In) SECINFO (In, EA) EPCPAGE (In, EA)EMODT 0FH (In) SECINFO (In,  EA) EPCPAGE (In, EA)
ERDINFO 010H (In) RDINFO (I n, EA*) EPCPAGE (In, EA)
ETRACKC 011H (In) EPCPAGE (In, EA)ELDBC 012H (In) PAGEINFO (In, EA*) EPCPAGE (In, EA) VERSION (In, EA)ELDUC 013H (In) PAGEINFO (In, EA*) EPCPAGE (In, EA) VERSION (In, EA)EA: Effective Address38-2 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
38.1.2 ENCLU Register Usage Summary
Table 38-2 summarizes the implicit register  usage of user mode enclave instructions.
38.1.3 ENCLV Register Usage Summary
Table 38-3 summarizes the implicit register usage of virtualization operation enclave instructions.
38.1.4 Information and Error Codes
Information and error codes are reported by various instruction leaf functions to show an abnormal termination of 
the instruction or provide information which may be usef ul to the developer. Table 38-4 shows the various codes 
and the instruction which generated the code. Details of the meaning of the code is provided in the individual 
instruction.Table 38-2.  Register Usag e of Unprivileged Enclave Instruction Leaf Functions
EREPORT 00H (In) TARGETINFO (In, EA) REPORTDATA (In, EA) OUTPUTDATA (In, EA)EGETKEY 01H (In) KEYREQUEST (In, EA) KEY (In, EA)EENTER 02H (In) TCS (In, EA) AEP (In, EA)
RBX.CSSA (Out) Return (Out, EA)
ERESUME 03H (In) TCS (In, EA) AEP (In, EA)EEXIT 04H (In) Target (In, EA) Current AEP (Out)EACCEPT 05H (In) SECINFO (In, EA) EPCPAGE (In, EA)EMODPE 06H (In) SECINFO (In, EA) EPCPAGE (In, EA)EACCEPTCOPY 07H (In) SECINFO (In, EA) E PCPAGE (In, EA) EPCPAGE (In, EA)
EDECCSSA 09H (In)EA: Effective Address
Table 38-3.  Register Usage of Virtualization  Operation Enclave Instruction Leaf Functions

EDECVIRTCHILD 00H (In) EPCPAGE (In, EA) SECS (In, EA)EINCVIRTCHILD 01H (In) EPCPAGE (In, EA) SECS (In, EA)ESETCONTEXT 02H (In) EPCPAGE (In, EA) Context Value (In, EA)EA: Effective Address
Table 38-4.  Error or Information Codes for Intel® SGX Instructions
Name Value Returned ByNo Error 0SGX_INVALID_SIG_STRUCT 1 EINITSGX_INVALID_ATTRIBUTE 2 EINIT, EGETKEYSGX_BLKSTATE 3 EBLOCKSGX_INVALID_MEASUREMENT 4 EINITSGX_NOTBLOCKABLE 5 EBLOCKSGX_PG_INVLD 6 EBLOCK, ERDINFO, ETRACKCVol. 3D 38-3INTEL® SGX INSTRUCTION REFERENCES
38.1.5 Internal CREGs
The CREGs as shown in Table 5-4 are hardware specific regist ers used in this document to indicate values kept by 
the processor. These values are used while executing in en clave mode or while executing an Intel SGX instruction. 
These registers are not software visible and are implementati on specific. The values in Table 38-5 appear at various 
places in the pseudo-code of this document. They ar e used to enhance understanding of the operations.SGX_EPC_PAGE_CONFLICT 7 EBLOCK, EM ODPR, EMODT, ERDINFO , EDECVIRT CHILD, EINCVIRTCHILD, ELDBC, 
ELDUC, ESETCONTEXT, ETRACKC
SGX_INVALID_SIGNATURE 8 EINITSGX_MAC_COMPARE_FAIL 9 ELDB, ELDU, ELDBC, ELDUCSGX_PAGE_NOT_BLOCKED 10 EWBSGX_NOT_TRACKED 11 EWB, EACCEPTSGX_VA_SLOT_OCCUPIED 12 EWBSGX_CHILD_PRESENT 13 EWB, EREMOVESGX_ENCLAVE_ACT 14 EREMOVESGX_ENTRYEPOCH_LOCKED 15 EBLOCKSGX_INVALID_EINITTOKEN 16 EINIT
SGX_PREV_TRK_INCMPL 1 7E T R A C K ,  E T R A C K C
SGX_PG_IS_SECS 18 EBLOCKSGX_PAGE_ATTRIBUTES_MISMATCH 19 EACCEPT, EACCEPTCOPYSGX_PAGE_NOT_MODIFIABLE 20 EMODPR, EMODTSGX_PAGE_NOT_DEBUGGA BLE 21 EDBGRD, EDBGWR
SGX_INVALID_COUNTER 25 EDECVIRTCHILDSGX_PG_NONEPC 26 ERDINFOSGX_TRACK_NOT_REQUIRED 27 ETRACKCSGX_INVALID_CPUSVN 32 EINIT, EGETKEYSGX_INVALID_ISVSVN 64 EGETKEYSGX_UNMASKED_EVENT 128 EINITSGX_INVALID_KEYNAME 256 EGETKEY
Table 38-5.  List of Internal CREG 
Name Size (Bits) ScopeCR_ENCLAVE_MODE 1 LPCR_DBGOPTIN 1 LPCR_TCS_LA 64 LPCR_TCS_PA 64 LPCR_ACTIVE_SECS 64 LPCR_ELRANGE 128 LPCR_SAVE_TF 1 LPCR_SAVE_FS 64 LPCR_GPR_PA 64 LPCR_XSAVE_PAGE_n 64 LPTable 38-4.  Error or Information Codes for Intel® SGX Instructions
Name Value Returned By38-4 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
38.1.6 Concurrent Operation Restrictions
Under certain conditions, Intel SGX disallows certain leaf functions from operating concurrently. Listed below are 
some examples of concurrency that are not allowed. 
•For example, Intel SGX disallows the following leafs to concurrently operate on the same EPC page.
— ECREATE, EADD, and EREMOVE are not allowed to op erate on the same EPC page concurrently with 
themselves. 
— EADD, EEXTEND, and EINIT leaves are not allowe d to operate on the same SECS concurrently.
•Intel SGX disallows the EREMOVE leaf from remo ving pages from an enclave that is in use.
•Intel SGX disallows entry (EENTER and ERESUME) to an  enclave while a page from that enclave is being 
removed. 
When disallowed operation is detected, a le af function may do one of the following:
•Return an SGX_EPC_PAGE_CONFLICT error code in RAX.
•Cause a #GP(0) exception.
To prevent such exceptions, software must serialize leaf functions or prevent these leaf functions from accessing 
the same EPC page. 
38.1.6.1  Concurrency Tables  of Intel® SGX Instructions
The tables below detail the concurrent operation restrictions  of all SGX leaf functions. For each leaf function, the 
table has a separate line for each of the EPC pages the leaf function accesses.
For each such EPC page, the base concurre ncy requirements are detailed as follows:
•Exclusive Access  means that no other leaf function that requires either shared or exclusive access to the 
same EPC page may be executed concurrently. For exampl e, EADD requires an exclusive access to the target 
page it accesses.CR_SAVE_DR7 64 LP
CR_SAVE_PERF_GLOBAL_CTRL 64 LPCR_SAVE_DEBUGCTL 64 LPCR_SAVE_PEBS_ENABLE 64 LPCR_CPUSVN 128 PACKAGECR_SGXOWNEREPOCH 128 PACKAGECR_SAVE_XCR0 64 LPCR_SGX_ATTRIBUTES_MASK 128 LPCR_PAGING_VERSION 64 PACKAGECR_VERSION_THRESHOLD 64 PACKAGECR_NEXT_EID 64 PACKAGECR_BASE_PK 128 PACKAGECR_SEAL_FUSES 128 PACKAGECR_CET_SAVE_AREA_PA 64 LPCR_ENCLAVE_SS_TOKEN_PA 64 LPCR_SAVE_IA32_U_CET 64 LPCR_SAVE_SSP 64 LPTable 38-5.  List of Internal CREG 
Name Size (Bits) ScopeVol. 3D 38-5INTEL® SGX INSTRUCTION REFERENCES
•Shared Access  means that no other leaf function that requir es an exclusive access to the same EPC page may 
be executed concurrently. Other leaf functions that re quire shared access may run concurrently. For example, 
EADD requires a shared access to the SECS page it accesses.
•Concurrent Access means that any other leaf function that requ ires any access to the same EPC page may be 
executed concurrently. For example, EGETKEY has no concurrency requirements for the KEYREQUEST page.
In addition to the base concurrency requirements, addi tional concurrency requirements are listed, which apply 
only to specific sets of leaf functions. For example, th ere are additional requirements that apply for EADD, EXTEND, 
and EINIT. EADD and EEXTEND can't execut e concurrently on the same SECS page.
The tables also detail the leaf function's behavior when a conflict happens, i.e., a concurrency requirement is not 
met. In this case, the leaf function may return an SGX_ EPC_PAGE_CONFLICT error code in RAX, or it may cause an 
exception. In addition, the tables detail those conflicts wh ere a VM Exit may be triggered, and list the Exit Qualifi-
cation code that is provided in such cases.
Table 38-6.  Base Concurrency Restrictions
Leaf Parameter Base Concurrency Restrictions
Access On ConflictSGX_CONFLICT VM Exit 
Qualification
EACCEPT Target [DS:RCX] Shared #GP
SECINFO [DS:RBX] Concurrent
EACCEPTCOPY Target [DS:RCX] Concurrent
Source [DS:RDX] ConcurrentSECINFO [DS:RBX] Concurrent
EADD Target [DS:RCX] Exclusive # GP EPC_PAGE_CONFLICT_EXCEPTION
SECS [DS:RBX]PAGEINFO.
SECSShared #GP
EAUG Target [DS:RCX] Exclusive # GP EPC_PAGE_CONFLICT_EXCEPTION
EBLOCK Target [DS:RCX] Shared SGX_EPC_PAGE
_CONFLICT
ECREATE SECS [DS:RCX] Exclusive #G P EPC_PAGE_CONFLICT_EXCEPTION
EDBGRD Target [DS:RCX] Shared #GPEDBGWR Target [DS:RCX] Shared #GPEDECVIRTCHILD Target [DS:RBX] Shared SGX_EPC_PAGE
_CONFLICT
SECS [DS:RCX] Concurrent
EENTERTCS SECS [DS:RBX] Shared #GPEEXIT ConcurrentEEXTEND Target [DS:RCX] Shared #GP
SECS [DS:RBX] Concurrent
EGETKEY KEYREQUEST [DS:RBX] Concurrent
OUTPUTDATA [DS:RCX] Concurrent
EINCVIRTCHILD Target [DS:RBX] Shared SGX_EPC_PAGE
_CONFLICT
EINIT SECS [DS:RCX] Shared #GP38-6 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
ELDB/ELDU Target [DS:RCX] Exclusive #GP EPC_PAGE_CONFLICT_EXCEPTION
VA [DS:RDX] Shared #GPSECS [DS:RBX]PAGEINFO.
EDLBC/ELDUC Target [DS:RCX] Exclusive SGX_EPC_PAGE
_CONFLICTEPC_PAGE_CONFLICT_ERROR
VA [DS:RDX] Shared SGX_EPC_PAGE
_CONFLICT
SECSShared SGX_EPC_PAGE
_CONFLICT
EMODPE Target [DS:RCX] Concurrent
EMODPR Target [DS:RCX] Shared #GPEMODT Target [DS:RCX] Exclusive SGX_EPC_PAGE
EPA VA [DS:RCX] Exclusive #GP EPC_PAGE_CONFLICT_EXCEPTION
ERDINFO Target [DS:RCX ]S h a r e d S G X _ E P C _ P A G E
_CONFLICT
EREMOVE Target [DS:RCX] Exclusive #GP EPC_PAGE_CONFLICT_EXCEPTIONEREPORT TARGETINFO [DS:RBX] Concurrent
REPORTDATA [DS:RCX] ConcurrentOUTPUTDATA [DS:RDX] Concurrent
ERESUME TCS [DS:RBX] Shared #GPESETCONTEXT SECS [DS:RC X] Shared SGX_EPC_PAGE
_CONFLICT
ETRACK SECS [DS:RCX] Shared #GPETRACKC Target [DS:RCX] Shared SGX_EPC_PAGE
_CONFLICT
SECS Implicit Concurrent
EWB Source [DS:RCX] Exclusive #GP EPC_PAGE_CONFLICT_EXCEPTION
VA [DS:RDX] Shared #GP
Table 38-7.  Additional Concurrency Restrictions
Leaf Parameter Additional Concurrency Restrictions
vs. EACCEPT, 
EACCEPTCOPY, 
EMODPE, EMODPR, 
EMODTvs. EADD, EEXTEND, 
EINITvs. ETRACK, ETRACKC
AccessOn 
ConflictAccessOn 
Conflict
EACCEPT Target [DS:RCX] Exclusive #GP Concurrent Concurrent
SECINFO [DS:RBX] Concurrent Concurrent ConcurrentTable 38-6.  Base Concurrency Restrictions
QualificationVol. 3D 38-7INTEL® SGX INSTRUCTION REFERENCES
EACCEPTCOPY Target [DS:RCX] Exclusive #GP Concurrent Concurrent
Source [DS:RDX] Concurrent Concurrent ConcurrentSECINFO [DS:RBX] Concurrent Concurrent Concurrent
EADD Target [DS:RCX] Concurrent Concurrent Concurrent
SECSConcurrent Exclusive #GP Concurrent
EAUG Target [DS:RCX] Concurrent Concurrent Concurrent
SECSConcurrent Concurrent Concurrent
EBLOCK Target [DS:RCX] Concurrent Concurrent Concurrent
ECREATE SECS [DS:RCX] Concurrent Concurrent ConcurrentEDBGRD Target [DS:RCX] Concurrent Concurrent ConcurrentEDBGWR Target [DS:RCX] Concurrent Concurrent ConcurrentEDECVIRTCHILD Target [DS:RBX] Con current Concurrent Concurrent
SECS [DS:RCX] Concurrent Concurrent Concurrent

EENTERTCS SECS [DS:RBX] Concurrent Concurrent ConcurrentEEXIT Concurrent Concurrent ConcurrentEEXTEND Target [DS:RCX] Concur rent Concurrent Concurrent
SECS [DS:RBX] Concurrent Exclusive #GP Concurrent
EGETKEY KEYREQUEST [DS:RBX] Concurrent Concurrent Concurrent
OUTPUTDATA [DS:RCX] Concurrent Concurrent Concurrent
EINCVIRTCHILD Target [DS:RBX] Con current Concurrent Concurrent
EINIT SECS [DS:RCX] Concurrent Exclusive #GP ConcurrentELDB/ELDU Target [DS:RCX] Concu rrent Concurrent Concurrent
VA [DS:RDX] Concurrent Concurrent ConcurrentSECS [DS:RBX]PAGEINFO.
EDLBC/ELDUC Target [DS:RCX] Con current Concurrent Concurrent
EMODPE Target [DS:RCX] Exclusive #GP Concurrent Concurrent
SECINFO [DS:RBX] Concurrent Concurrent Concurrent
EMODPR Target [DS:RCX] Exclusive SGX_EPC_
PAGE_CON
FLICTConcurrent ConcurrentTable 38-7.  Additional Concurrency Restrictions
AccessOn 
Conflict38-8 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
38.2 INTEL® SGX INSTRUCTION REFERENCEEMODT Target [DS:RCX] Exclusive SGX_EPC_
PAGE_CONFLICTConcurrent Concurrent
EPA VA [DS:RCX] Concurrent Concurrent Concurrent
ERDINFO Target [DS:RCX] Concurrent Concurrent ConcurrentEREMOVE Target [DS:RCX] Concurrent Concurrent Concurrent
EREPORT TARGETINFO [DS:RBX] Concurrent Concurrent Concurrent
REPORTDATA [DS:RCX] Concurrent Concurrent ConcurrentOUTPUTDATA [DS:RDX] Concurrent Concurrent Concurrent
ERESUME TCS [DS:RBX] Concurrent Concurrent ConcurrentESETCONTEXT SECS [DS:RCX] Concurrent Concurrent ConcurrentETRACK SECS [DS:RCX] Concurrent Concurrent Exclusive SGX_EPC_
PAGE_CONFLICT
1
ETRACKC Target [DS:RCX] Concurrent Concurrent Concurrent
SECS Implicit Concurrent Concurrent Exclusive SGX_EPC_
PAGE_CO
NFLICT1
EWB Source [DS:RCX] Concurrent Concurrent Concurrent
VA [DS:RDX] Concurrent Concurrent Concurrent
NOTES:
1. SGX_CONFLICT VM Exit Qualification =TRACKING_RESOURCE_CONFLICT.Table 38-7.  Additional Concurrency Restrictions
AccessOn 
ConflictVol. 3D 38-9INTEL® SGX INSTRUCTION REFERENCES
ENCLS—Execute an Enclave System F unction of Specified Leaf Number 
The ENCLS instruction invokes the specified privileged Intel SGX leaf function for managing and debugging 
enclaves. Software specifies the leaf function by setting the appropriate value in the register EAX as input. The 
registers RBX, RCX, and RDX have leaf-specific purpose, an d may act as input, as output, or may be unused. In 64-
bit mode, the instruction ignores upper 32 bits of the RAX register.
The ENCLS instruction produces an invalid-opcode exceptio n (#UD) if CR0.PE = 0 or RFLA GS.VM = 1, or if it is 
executed in system-management mode (SMM). Additionally , any attempt to execute the instruction when CPL > 0 
results in #UD. The instruction produces a general-protec tion exception (#GP) if CR0. PG = 0 or if an attempt is 
made to invoke an undefined leaf function.
In VMX non-root operation, execution of ENCLS may caus e a VM exit if the “enable ENCLS exiting” VM-execution 
control is 1. In this case, execution of individual leaf functions of ENCLS is governed by the ENCLS-exiting bitmap 
field in the VMCS. Each bit in that field corresponds to th e index of an ENCLS leaf function (as provided in EAX).
Software in VMX root operation can thus intercept the invo cation of various ENCLS leaf functions in VMX non-root 
operation by setting the “enable ENCLS exiting” VM-execu tion control and setting the corresponding bits in the 
ENCLS-exiting bitmap.
Addresses and operands are 32 bits outside 64-bit mode (IA32_EFER.LMA = 0 || CS.L = 0) and are 64 bits in 64-
bit mode (IA32_EFER.LMA = 1 || CS.L = 1). CS.D value has no impact on address calculation. The DS segment is 
used to create linear addresses.
Segment override prefixes and address-si ze override prefixes are ignored, and is the REX prefix in 64-bit mode.
Operation
IF TSX_ACTIVE
THEN GOTO TSX_ABORT_PROCESSING; FI;
IF CR0.PE = 0 or RFLAGS.VM = 1 or in  SMM or CPUID.SGX_LEAF.0:EAX.SE1 = 0
IF (CPL > 0) 
IF in VMX non-root operation and the “enable ENCLS exiting“ VM-execution control is 1
THEN 
IF EAX < 63 and ENCLS_exiting_bitmap[EAX] = 1 or EAX> 62 and ENCLS_exiting_bitmap[63] = 1
FI;
FI;IF IA32_FEATURE_CONTROL.LOCK = 0 or IA32_FEATURE_CONTROL.SGX_ENABLE = 0
IF (EAX is an in valid leaf  number)
THEN #GP(0); FI;Opcode/
InstructionOp/En 64/32 
NP 0F 01 CF 
ENCLSZO V/V NA This instruction is used to execute privileged Intel SGX leaf func-
tions that are used for managing and debugging the enclaves.
Op/En Operand 1 Operand 2 Operand 3 Implicit Register Operands
ZO NA NA NA See Section 38.338-10 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF CR0.PG = 0
(* DS must not be an expanded down segment *)
IF not in 64-bit mode and DS.Type is expand-down data
Jump to leaf specific flow
See individual leaf functions
#UD If any of the LOCK/66H/REP/VEX prefixes are used.
If CPUID.(EAX=12H,ECX=0 ):EAX.SGX1 [bit 0] = 0.
If logical processor is in SMM.
#GP(0) If IA32_FEATURE_CONTROL.LOCK = 0.
If IA32_FEATURE_CONTROL.SGX_ENABLE = 0.
If input value in EAX enco des an unsupported leaf.
If data segment expand down.If CR0.PG=0.
#UD ENCLS is not recognized in real mode.
#UD ENCLS is not recognized in virtual-8086 mode.
If current privilege level is not 0.If CPUID.(EAX=12H,ECX=0 ):EAX.SGX1 [bit 0] = 0.
If input value in EAX enco des an unsupported leaf.Vol. 3D 38-11INTEL® SGX INSTRUCTION REFERENCES
ENCLU—Execute an Enclave User Function of Specified Leaf Number 
The ENCLU instruction invokes the specified non-privileged Intel SGX leaf functions. Software specifies the leaf 
function by setting the appropriate value in the register EAX as input. The registers RB X, RCX, and RDX have leaf-
specific purpose, and may act as input, as output, or may be unused. In 64-bit mode, the instruction ignores upper 
32 bits of the RAX register.
The ENCLU instruction produces an invalid-opcode exceptio n (#UD) if CR0.PE = 0 or RFLAGS.VM = 1, or if it is 
executed in system-management mode (SMM). Additionally, any attempt to execute this instruction when CPL < 3 
results in #UD. The instruction produces a general-protection  exception (#GP) if either CR0.PG or CR0.NE is 0, or 
if an attempt is made to invoke an undefined leaf function. Th e ENCLU instruction produces a device not available 
exception (#NM) if CR0.TS = 1.
Addresses and operands are 32 bits outside 64-bit mode (IA32_EFER.LMA = 0 or CS.L = 0) and are 64 bits in 64-
bit mode (IA32_EFER.LMA = 1 and CS.L = 1). CS.D value ha s no impact on address calculation. The DS segment 
is used to create linear addresses.
Segment override prefixes and address-si ze override prefixes are ignored, as is the REX prefix in 64-bit mode.
Operation
IN_64BIT_MODE := 0;
(* If enclosing app has CET indirect branch tracking enab led then if it is not ERESUME leaf cause a #CP fault *) 
(* If the ERESUME is not successful it wi ll leave tracker in WA IT_FOR_ENDBRANCH *)
TRACKER = (CPL == 3) ? IA32_U_C ET.TRACKER : IA32_S_CET.TRACKER 
IF EndbranchEnabledAndNotSuppressed(CPL ) and TRACKER = WAIT_FOR_ENDBRANCH and 
 (EAX != ERESUME or CR0.TS or  (in SMM) or (CPUID.SGX_LEAF. 0:EAX.SE1 = 0) or (CPL < 3)) 
THEN
Handle CET State machine violation (* see Section 17.3.6, “Legacy Compatibility Treatment,” in the
 Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. *)
FI;
IF CR0.PE= 0 or RFLAGS.VM = 1 or in SMM or CPUID.SGX_LEAF.0:EAX.SE1 = 0
IF CR0.TS = 1
THEN #NM; FI;
IF CPL < 3
IF IA32_FEATURE_CONTROL.LOCK = 0 or IA32_FEATURE_CONTROL.SGX_ENABLE = 0
NP 0F 01 D7 
ENCLUZO V/V NA This instruction is used to execute non-privileged Intel SGX leaf 
ZO NA NA NA See Section 38.438-12 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES

THEN
FI;
IF CPL < 3
NP 0F 01 D7 
IF EAX is invalid leaf number
IF CR0.PG = 0 or CR0.NE = 0
IN_64BIT_MODE := IA32_EFER.LMA AND CS.L ? 1 : 0;
(* Check not in 16-bit mode and DS is not a 16-bit segment *)
IF not in 64-bit mode and CS.D = 0 
IF CR_ENCLAVE_MODE = 1 and (EAX = 2 or  EAX = 3) (* EENTER or ERESUME *)
IF CR_ENCLAVE_MODE = 0 and (EAX = 0 or EAX = 1 or EA X = 4 or EAX = 5 or EAX = 6 or EAX = 7 or EAX = 9)
(* EREPORT, EGETKEY, EEXIT, EACCEPT,  EMODPE, EACCEPTCOPY, or EDECCSSA *)
If current privilege level is not 3.If CPUID.(EAX=12H,ECX=0 ):EAX.SGX1 [bit 0] = 0.
If input value in EAX encodes EENT ER/ERESUME and ENCLAVE_MODE = 1.
If input value in EAX encodes EGETKEY/EREPORT/EEXIT/EACCEPT/EACCEPTCOPY/EMODPE 
and ENCLAVE_MODE = 0.
If operating in 16-bit mode.If data segment is in 16-bit mode.
If CR0.PG = 0 or CR0.NE= 0.
Same exceptions as in protected mode.Vol. 3D 38-13INTEL® SGX INSTRUCTION REFERENCES
If current privilege level is not 3.If CPUID.(EAX=12H,ECX=0):EAX.SGX1 [bit 0] = 0.
If CR0.NE= 0.
#NM If CR0.TS = 1.38-14 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
ENCLV—Execute an Enclave VMM Function of Specified Leaf Number 
The ENCLV instruction invokes the virtualization SGX leaf functions for managing enclaves in a virtualized environ-
ment. Software specifies the leaf function by setting the appropriate value in the register EAX as input. The regis-
ters RBX, RCX, and RDX have leaf-specific purpose, and ma y act as input, as output, or may be unused. In non 64-
The ENCLV instruction produces an invalid-opcode except ion (#UD) if CR0.PE = 0 or RFLAGS.VM = 1, if it is 
executed in system-management mode (SMM), or not in VM X operation. Additionally, any attempt to execute the 
instruction when CPL > 0 results in #UD. The instruction produces a general-protection exception (#GP) if CR0.PG 
= 0 or if an attempt is made to invoke an undefined leaf function.
Software in VMX root mode of operation can enable exec ution of the ENCLV instruction in VMX non-root mode by 
setting enable ENCLV execution control in the VMCS. If enab le ENCLV execution control in the VMCS is clear, execu-
tion of the ENCLV instruction in VMX non-root mode results in #UD. 
When execution of ENCLV instruction in VMX non-root mode  is enabled, software in VMX root operation can inter-
cept the invocation of various ENCLV leaf functions in VM X non-root operation by setting the corresponding bits in 
the ENCLV-exiting bitmap.
Addresses and operands are 32 bits in 32-bit mode (IA32_ EFER.LMA == 0 || CS.L == 0) and are 64 bits in 64-bit 
mode (IA32_EFER.LMA == 1 && CS.L == 1). CS.D value has no impact on address calculation.
Segment override prefixes and address-size override prefix es are ignored, as is the REX prefix in 64-bit mode.
Operation
IF CR0.PE = 0 or RFLAGS.VM = 1 or in  SMM or CPUID.SGX_LEAF.0:EAX.OSS = 0
IF not in VMX Operation or (IA32_EFER.LMA = 1 and CS.L = 0)
IF (CPL > 0) 
IF in VMX non-root operation 
    IF “enable ENCLV exitin g“ VM-execution control is 1
        THEN            IF EAX < 63 and ENCLV_exiting_bitmap [EAX] = 1 or EAX> 62 and ENCLV_exiting_bitmap[63] = 1
                  THEN VM exit;            FI;     ELSE        #UD; FI;Opcode/
NP 0F 01 C0 
ENCLVZO V/V NA This instruction is used to execute privileged SGX leaf functions 
that are reserved for VMM use. They are used for managing the 
enclaves.
ZO NA NA NA See Section 38.3Vol. 3D 38-15INTEL® SGX INSTRUCTION REFERENCES
FI;
See individual leaf functions.
If current privilege level is not 0.If CPUID.(EAX=12H,ECX=0 ):EAX.OSS [bit 5] = 0.
#UD ENCLV is not recognized in real mode.
#UD ENCLV is not recognized in virtual-8086 mode.
If input value in EAX enco des an unsupported leaf.38-16 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
38.3 INTEL® SGX SYSTEM LEAF FUNCTION REFERENCE
Leaf functions available with the ENCLS instruction mnemonic are covered in this section. In general, each instruc-
tion leaf requires EAX to spec ify the leaf function index and/or additional  implicit registers specifying leaf-specific 
input parameters. An instruction operand encoding table prov ides details of each implicit register usage and asso-
ciated input/output semantics.
In many cases, an input parameter specifies an effective ad dress associated with a memory object inside or outside 
the EPC, the memory addressing semantics of these me mory objects are also summarized in a separate table.Vol. 3D 38-17INTEL® SGX INSTRUCTION REFERENCES
EADD—Add a Page to an Uninitialized Enclave  
This leaf function copies a source page from non-enclav e memory into the EPC, associates the EPC page with an 
SECS page residing in the EPC, and stores the linear addr ess and security attributes in EPCM. As part of the asso-
ciation, the enclave offset and the security attributes are measured and extended into the SECS.MRENCLAVE. This 
instruction can only be executed when current privilege level is 0.
RBX contains the effective address of a PAGEINFO struct ure while RCX contains the effective address of an EPC 
page. The table below provides addi tional information on the memory parameter of EADD leaf function.
EADD Memory Parameter Semantics
The instruction faults if any of the following: 
EADD Faulting Conditions
Concurrency RestrictionsOpcode/
EAX = 01H
ENCLS[EADD]IR V/V SGX1 This leaf function adds a page to an uninitialized enclave.
Op/En EAX RBX RCX
IR EADD (In) Address of a PAGEINFO (In) Ad dress of the destination EPC page (In)
PAGEINFO PAGEINFO.SECS PAGEINFO. SRCPGE PAGEINFO.SECINFO EPCPAGE
Read access permitted 
by Non Enclave Read/Write access permit-
ted by Enclave Read access permitted 
by Non Enclave Read access permitted 
by Non Enclave Write access permitted 
by Enclave
The operands are not properly aligned. Unsupported security attributes are set.
Refers to an invalid SECS. Refer ence is made to an SECS that is locked  by another thread.
The EPC page is locked by another thread. RCX does  not contain an effective address of an EPC page.
The EPC page is already valid. If security attributes specifies a TCS and the source page specifies unsupported 
TCS values or fields.
The SECS has been initialized. The specified enclave offset is outside of the enclave address space.
Table 38-8.  Base Concurrency Restrictions of EADD
Leaf ParameterBase Concurrency Restrictions
Access On Conflict SGX_CONFLICT VM Exit Qualification
SECS [DS:RBX]PAGEINFO.SECS Shared #GP38-18 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EADD Operational Flow

by Enclave
Operation
IF (DS:RBX is not 32Byte Aligned)
IF (DS:RCX is not 4KByte Aligned)
IF (DS:RCX does not re solve within an EPC)
THEN #PF(DS:RCX); FI;
TMP_SRCPGE := DS:RBX.SRCPGE;
TMP_SECS := DS:RBX.SECS;TMP_SECINFO := DS:RBX.SECINFO;TMP_LINADDR := DS:RBX.LINADDR;
IF (DS:TMP_SRCPGE is not 4KByte aligned or DS:TMP_SECS is not 4KByte aligned or
DS:TMP_SECINFO is not 64Byte aligned or TMP_LINADDR is not 4KByte aligned)
IF (DS:TMP_SECS does no t resolve within an EPC)
THEN #PF(DS:TMP_SECS); FI;
SCRATCH_SECINFO := DS:TMP_SECINFO;(* Check for misconfigured SECINFO flags*)
IF (SCRATCH_SECINFO reserved fields are not zero or Table 38-9.  Additional Concurrency Restrictions of EADD
Leaf ParameterAdditional Concur rency Restrictions
vs. EACCEPT, EACCEPTCOPY, 
EMODPE, EMODPR, EMODTvs. EADD, EEXTEND, EINIT vs. ETRACK, ETRACKC
Access On Conflict Access On Conflict Access On Conflict
SECS [DS:RBX]PAGE-
INFO.SECSConcurrent Exclusive #GP Concurrent
Name Type Size (bits) Description
TMP_SRCPGE Effective Address 32/64 Effe ctive address of the source page.
TMP_SECS Effective Address 32/ 64 Effective address of th e SECS destination page.
TMP_SECINFO Effective Address 32/64 Effective address of an SECINFO structure which contains security 
attributes of the page to be added.
SCRATCH_SECINFO SECINFO 512 Scratch storage for holding the contents of DS:TMP_SECINFO.
TMP_LINADDR Unsigned Integer 64 Holds the linear address to be stored in the EPCM and used to 
calculate TMP_ENCLAVEOFFSET.
TMP_ENCLAVEOFFSET Enclave Offset 64 The page displacement from the enclave base address.TMPUPDATEFIELD SHA256 Buffer 512 Buffer used to hold data being added to TMP_SECS.MRENCLAVE.Vol. 3D 38-19INTEL® SGX INSTRUCTION REFERENCES
! (SCRATCH_SECINFO.FLAGS.PT is PT_REG or  SCRATCH_SECINFO.FLAGS.PT is PT_TCS or
(SCRATCH_SECINFO.FLAGS.PT is PT_SS_FIRST and CPUID.(EAX=12H, ECX=1):EAX[6] = 1) or
(SCRATCH_SECINFO.FLAGS.PT is PT_SS_REST and CPUID.(EAX=12H, EC X=1):EAX[6] = 1)) ) 
(* If PT_SS_FIRST/PT_SS_REST page types are requested then CR4.CET must be 1 *)
IF ( (SCRATCH_SECINFO.FLAGS.PT is PT_SS_FIRST OR
SCRATCH_SECINFO.FLAGS.PT is PT_SS_REST) AND CR4.CET == 0)THEN #GP(0); FI;
(* Check the EPC page for concurrency *)
IF (EPC page is not available for EADD) 
THEN 
IF (<<VMX non-root operation>> AND <<E NABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)
THEN
VMCS.Exit_reason := SGX_CONFLICT;VMCS.Exit_qualification.code := EPC_PAGE_CONFLICT_EXCEPTION;VMCS.Exit_qualification.error := 0;VMCS.Guest-physical_address := << translat ion of DS:RCX produced by paging >>;
VMCS.Guest-linear_address := DS:RCX;
        Deliver VMEXIT; ELSE
#GP(0);
FI;
FI;
IF (EPCM(DS:RCX).VALID ≠ 0) 
(* Check the SECS for concurrency *)
IF (SECS is not available for EADD) 
IF (EPCM(DS:TMP_SECS).VALID = 0 or EPCM(DS:TMP_SECS).PT ≠ PT_SECS) 
(* Copy 4KBytes from so urce page to EPC page*)
DS:RCX[32767:0] := DS:TMP_SRCPGE[32767:0];
CASE (SCRATCH_SECINFO.FLAGS.PT) 
PT_TCS:
IF (DS:RCX.RESERVED ≠ 0) #GP(0); FI;
IF ( (DS:TMP_SECS.ATTRIBU TES.MODE64BIT = 0) and 
((DS:TCS.FSLIMIT & 0FFFH ≠ 0FFFH) or (DS:TCS.GSLIMIT & 0FFFH ≠ 0FFFH) )) #GP(0); FI;
(* Ensure TCS.PREVSSP is zero *)IF (CPUID.(EAX=07H, ECX=00h):ECX[CET_SS] = 1) and (DS:RCX.PREVSSP != 0) #GP(0); FI;
BREAK;
PT_REG:
IF (SCRATCH_SECINFO.FLAGS.W = 1 and SC RATCH_SECINFO.FLAGS.R = 0) #GP(0); FI;
BREAK;
PT_SS_FIRST:PT_SS_REST:(* SS pages cannot be created on first or last page of ELRANGE *)38-20 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF ( TMP_LINADDR = DS:TMP_SECS.BASEA DDR or TMP_LINADDR = (DS:TMP_SECS.BAS EADDR + DS:TMP_SECS.SIZE - 0x1000) )
IF ( DS:RCX[4087:0] != 0 ) #GP(0); FI;IF (SCRATCH_SECINFO.FLA GS.PT == PT_SS_FIRST)
THEN
(* Check that valid RSTORSSP token exists *)IF ( DS:RCX[4095:4088] != ((TMP_L INADDR + 0x1000) | DS:T MP_SECS.ATTRIBUTES.MODE64BIT) ) #GP(0); FI;
ELSE
(* Check the 8 bytes are zero *)IF ( DS:RCX[4095:4088] != 0 ) #GP(0); FI;
FI;IF (SCRATCH_SECINFO.FLAGS.W = 0 OR SCRATCH_SECINFO.FLAGS.R = 0 OR SCRATCH_SECINFO.FLAGS.X = 1) #GP(0); FI;
BREAK;
ESAC;
(* Check the enclave offset is within the enclave linear address space *)
IF (TMP_LINADDR < DS:TMP_SECS.BASEADDR or TMP_LINADDR 
≥ DS:TMP_SECS.BASEADDR + DS:TMP_SECS.SIZE) 
(* Check concurrency of measurement resource*)
IF (Measurement being updated) 
(* Check if the enclave to which the page will be added is already in Initialized state *)
IF (DS:TMP_SECS already initialized) 
(* For TCS pages, force EPCM.rwx bits to 0 and no debug access *)
IF (SCRATCH_SECINFO.FLAGS.PT = PT_TCS) 
THEN
SCRATCH_SECINFO.FLAGS.R := 0;SCRATCH_SECINFO.FLAGS.W := 0;SCRATCH_SECINFO.FLAGS.X := 0;(DS:RCX).FLAGS.DBGOPTIN := 0; // force TCS.FLAGS.DBGOPTIN offDS:RCX.CSSA := 0;DS:RCX.AEP := 0;DS:RCX.STATE := 0;
FI;
(* Add enclave offset and security attributes to MRENCLAVE *)
TMP_ENCLAVEOFFSET := TMP_LINADDR - DS:TMP_SECS.BASEADDR;TMPUPDATEFIELD[63:0] := 0000000044444145H; // “EADD”TMPUPDATEFIELD[127:64] := TMP_ENCLAVEOFFSET;TMPUPDATEFIELD[511:128] := SCRATCH_SECINFO[375:0]; // 48 bytesDS:TMP_SECS.MRENCLAVE := SHA256UPDATE(DS:TMP_SECS.MRENCLAVE, TMPUPDATEFIELD)
INC enclave’s MRENCLAVE update counter;
EPCM(DS:RCX).R := SCRATCH_SECINFO.FLAGS.R;EPCM(DS:RCX).W := SCRATCH_SECINFO.FLAGS.W;EPCM(DS:RCX).X := SCRATCH_SECINFO.FLAGS.X;EPCM(DS:RCX).PT := SCRATCH_SECINFO.FLAGS.PT;EPCM(DS:RCX).ENCLAVEADDRESS := TMP_LINADDR;Vol. 3D 38-21INTEL® SGX INSTRUCTION REFERENCES
(* associate the EPCPAGE with the SECS by storing the SECS identifier of DS:TMP_SECS *)
Update EPCM(DS:RCX) SECS identifier to reference DS:TMP_SECS identifier;
(* Set EPCM entry fields *)
EPCM(DS:RCX).BLOCKED := 0;EPCM(DS:RCX).PENDING := 0;EPCM(DS:RCX).MODIFIED := 0;EPCM(DS:RCX).VALID := 1;
None
#GP(0) If a memory operand effective a ddress is outside the DS segment limit.
If a memory operand is not properly aligned.
If an enclave memory operand is outside of the EPC.
If an enclave memory operand is the wrong type.
If a memory operand is locked.If the enclave is initialized.
If the enclave's MRENCLAVE is locked.
If the TCS page reserved bits are set.If the TCS page PREVSSP field is not zero.
If the PT_SS_REST or PT_SS_REST page is  the first or last page in the enclave.
If the PT_SS_FIRST or PT_SS_REST page is not initialized correctly.
#PF(error code) If a page fault occurs in accessing memory operands.
If the EPC page is valid.
#GP(0) If a memory operand is non-canonical form.
If an enclave memory operand is the wrong type.If a memory operand is locked.
If the enclave is initialized.
If the enclave's MRENCLAVE is locked.If the TCS page reserved bits are set.
If the TCS page PREVSSP field is not zero.
If the EPC page is valid.38-22 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EAUG—Add a Page to an Initialized Enclave  
This leaf function zeroes a page of EPC memory, associates the EPC page with an SECS page residing in the EPC, 
and stores the linear address and security attributes in the EPCM. As part of the association, the security attributes 
are configured to prevent access to the EPC page until a co rresponding invocation of the EACCEPT leaf or EACCEPT-
COPY leaf confirms the addition of the new page into the enclave. This instruction can only be executed when current privilege level is 0.
RBX contains the effective address of a PAGEINFO structure while RCX contains the effective address of an EPC 
page. The table below provides additi onal information on the memory parameter of the EAUG leaf function.
EAUG Memory Parameter Semantics
EAUG Faulting Conditions
EAX = 0DH
ENCLS[EAUG]IR V/V SGX2 This leaf function adds a page to an initialized enclave.
IR EAUG (In) Address of a PAGEINFO (In) Address of the destination EPC page (In)
PAGEINFO PAGEINFO.SECS PAGEINFO.SRCPGE PAGEINFO.SECINFO EPCPAGE
Read access permit-
ted by Non Enclave Read/Write access permit-
ted by Enclave Must be zeroRead access permitted by 
Non Enclave Write access permitted by 
Enclave
Refers to an invalid SECS. Reference is made to  an SECS that is lock ed by another thread.

EAX = 0DH
Enclave
The EPC page is locked by another thread. RCX does not contain an effective address of an EPC page.The EPC page is already valid. The specified enclave offset is outside of the enclave address space.
The SECS has been initialized.
Table 38-10.  Base Concur rency Restrictions of EAUG
EAUG Target [DS:RCX] Exclusive #GP EPC_PAGE_CONFLICT_EXCEPTION
SECS [DS:RBX]PAGEINFO.SECS Shared #GPVol. 3D 38-23INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EAUG Operational Flow
IF (DS:RCX does not resolve within an EPC)
TMP_SECS := DS:RBX.SECS;
TMP_SECINFO := DS:RBX.SECINFO;IF (DS:RBX.SECINFO is not 0)
THEN
IF (DS:TMP_SECINFO is not 64B aligned)
FI;
TMP_LINADDR := DS:RBX.LINADDR;IF ( DS:TMP_SECS is not 4KByte aligned or TMP_LINADDR is not 4KByte aligned )
IF DS:RBX.SRCPAGE is not 0
(* Check the EPC page for concurrency *)Table 38-11.  Additional Concurrency Restrictions of EAUG
INFO.SECSConcurrent Concurrent Concurrent
TMP_SECS Effective Address 32/64 Effective address of the SECS destination page.
TMP_LINADDR Unsigned Integer 64 Holds the linear ad dress to be stored in the EPCM and used to 
calculate TMP_ENCLAVEOFFSET.38-24 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF (EPC page in use) 
THEN
THEN
VMCS.Exit_reason := SGX_CONFLICT;VMCS.Exit_qualification.code :=  EPC_PAGE_CONFLICT_EXCEPTION;
VMCS.Exit_qualification.error := 0;VMCS.Guest-physical_address := << translation of DS:RCX  produced by paging >>;
VMCS.Guest-linear_address := DS:RCX;Deliver VMEXIT;
ELSE
#GP(0);
FI;
FI:
(* copy SECINFO contents into a scratch SECINFO *)
IF (DS:RBX.SECINFO is 0)
THEN
(* allocate and initialize a new scratch SECINFO structure *)SCRATCH_SECINFO.PT := PT_REG;SCRATCH_SECINFO.R := 1;SCRATCH_SECINFO.W := 1;SCRATCH_SECINFO.X := 0;<< zero out remaining fields of SCRATCH_SECINFO >>
ELSE
(* copy SECINFO contents  into scratch SECINFO *)
SCRATCH_SECINFO := DS:TMP_SECINFO;(* check SECINFO flags for misconfiguration *)(* reserved flags must be zero *)(* SECINFO.FLAGS.PT must either be PT_SS_FIRST, or PT_SS_REST *)
IF ( (SCRATCH_SECINFO reserved fields are not 0) orCPUID.(EAX=12H, ECX=1):EAX[6] is 0) OR (SCRATCH_SECINFO.PT is not PT_SS_FIRST, or PT_SS_REST) OR ( (SCRATCH_SECINFO.FLAGS.R is 0) OR (SCRATCH_SECINFO.F LAGS.W is 0) OR (SCRATCH_SECINFO.FLAGS.X is 1) ) )
FI;(* Check if PT_SS_FIRST/PT_SS_REST page types are requested then CR4.CET must be 1 *)IF ( (SCRATCH_SECINFO.PT is PT_SS_FIRST OR SCRATCH_SECINFO.PT is PT_SS_REST) AND CR4.CET == 0 )
IF (SECS is not available for EAUG) 
(* Check if the enclave to which the page will be added is in the Initialized state *)
IF (DS:TMP_SECS is not initialized) 
THEN #GP(0); FI;Vol. 3D 38-25INTEL® SGX INSTRUCTION REFERENCES
IF ( (TMP_LINADDR < DS:TMP_SECS.BASEADDR) or (TMP_LINADDR ≥ DS:TMP_SECS.BASEADDR + DS:TMP_SECS.SIZE) )
IF ( (SCRATCH_SECINFO.PT is PT_SS_FIRST OR SCRATCH_SECINFO.PT is PT_SS_REST) )
THEN
(* SS pages cannot created on first or last page of ELRANGE *)IF ( TMP_LINADDR == DS :TMP_SECS.BASEADDR OR
 TMP_LINADDR == (DS:TMP_SECS.BASEADDR  + DS:TMP_SECS.SIZE - 0x1000) )
THEN
FI;
(* Clear the content of EPC page*)
DS:RCX[32767:0] := 0;
IF (CPUID.(EAX=07H, ECX=0H):ECX[CET_SS] = 1)
THEN
(* set up shadow stack RSTORSSP token *)IF (SCRATCH_SECINFO.PT is PT_SS_FIRST)THEN
DS:RCX[0xFF8] := (TMP_LINADDR + 0x1000)  | TMP_SECS.ATTRIBUTES.MODE64BIT; FI;
FI;
(* Set EPCM security attributes *)
EPCM(DS:RCX).R := SCRATCH_SECINFO.FLAGS.R;EPCM(DS:RCX).W := SCRATCH_SECINFO.FLAGS.W;EPCM(DS:RCX).X := SCRATCH_SECINFO.FLAGS.X;EPCM(DS:RCX).PT := SCRATCH_SECINFO.FLAGS.PT;EPCM(DS:RCX).ENCLAVEADDRESS := TMP_LINADDR;EPCM(DS:RCX).BLOCKED := 0;EPCM(DS:RCX).PENDING := 1;EPCM(DS:RCX).MODIFIED := 0;EPCM(DS:RCX).PR := 0;
(* Set EPCM valid fields *)
EPCM(DS:RCX).VALID := 1;
None
If a memory operand is not properly aligned.If a memory operand is locked.
If the enclave is not initialized.
#PF(error code) If a page fault occurs in accessing memory operands.38-26 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
#PF(error code) If a page fault occurs in accessing memory operands.Vol. 3D 38-27INTEL® SGX INSTRUCTION REFERENCES
EBLOCK—Mark a page in EPC as Blocked  
This leaf function causes an EPC page to be marked as BLOCKED. This instruction can only be executed when 
current privilege level is 0.
The content of RCX is an effective address of an EPC pa ge. The DS segment is used to create linear address. 
Segment override is not supported.
An error code is returned in RAX.
The table below provides additional information on  the memory parameter of EBLOCK leaf function.
EBLOCK Memory Pa rameter Semantics
The error codes are: 
EAX = 09H
ENCLS[EBLOCK]IR V/V SGX1 This leaf function marks a page in the EPC as blocked.
Op/En EAX RCX
IR EBLOCK (In) Return error code (Out) Effective address of the EPC page (In)
EPCPAGE
Read/Write access pe rmitted by Enclave
Table 38-12.  EBLOCK Return Value in RAX
 Error Code (see Table 38-4) Description
No Error EBLOCK successful.SGX_BLKSTATE Page already blocked. This value is used to indicate to a VMM that  the page was already in 
BLOCKED state as a result of EBLOCK and thus will need to be restored to this state when it is eventually reloaded  (using ELDB). 
SGX_ENTRYEPOCH_LOCKED SECS locked for Entry Epoch update . This value indicates that an ETRACK is currently 
executing on the SECS. The EBLOCK should be reattempted.
SGX_NOTBLOCKABLE Page type is not one which can be blocked.SGX_PG_INVLD Page is not valid and cannot be blocked.SGX_EPC_PAGE_CONFLICT Page is being written by  EADD, EAUG, ECREATE, ELDU/B, EMODT, or EWB.
Table 38-13.  Base Concurrency Restrictions of EBLOCK
EBLOCK Target [DS:RCX] Shared SGX_EPC_PAGE_
CONFLICT38-28 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EBLOCK Operational Flow
RFLAGS.ZF,CF,PF,AF,OF,SF := 0;
RAX := 0;
(* Check the EPC page for concurrency*)
IF (EPC page in use)
THEN
RFLAGS.ZF := 1;RAX := SGX_EPC_PAGE_CONFLICT;GOTO DONE;
FI;
IF (EPCM(DS:RCX). VALID = 0)
THEN 
RFLAGS.ZF := 1;RAX := SGX_PG_INVLD;GOTO DONE;
FI;
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) and (E PCM(DS:RCX).PT ≠ PT_TRIM) 
and EPCM(DS:RCX).PT ≠ PT_SS_FIRST) and (EPCM(DS:RCX).PT ≠ PT_SS_REST))
THEN 
RFLAGS.CF := 1;IF (EPCM(DS:RCX). PT = PT_SECS) 
THEN RAX := SGX_PG_IS_SECS;ELSE RAX := SGX_NOTBLOCKABLE;
FI;GOTO DONE;
FI;
(* Check if the page is already blocked and report blocked state *)
TMP_BLKSTATE := EPCM(DS:RCX).BLOCKED;Table 38-14.  Additional Concurrency Restrictions of EBLOCK
Name Type Size (Bits) Description
TMP_BLKSTATE Integer 64 Page is already blocked.Vol. 3D 38-29INTEL® SGX INSTRUCTION REFERENCES
(* at this point, the page must be va lid and PT_TCS or PT _REG or PT_TRIM*)
IF (TMP_BLKSTATE = 1) 
THEN

FI;
THEN 
FI;
THEN 
RFLAGS.CF := 1;RAX := SGX_BLKSTATE;
ELSE
EPCM(DS:RCX).BLOCKED := 1
FI;DONE:
Sets ZF if SECS is in use or invalid, otherwise cleared.  Sets CF if page is BLOCKED or not blockable, otherwise 
cleared. Clears PF, AF, OF, SF.
If the specified EPC resource is in use.
If a memory operand is not an EPC page.
If a memory operand is not properly aligned.If the specified EPC resource is in use.
If a memory operand is not an EPC page.38-30 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
ECREATE—Create an SECS page  in the Enclave Page Cache 
ENCLS[ECREATE] is the first instruction executed in the enclave build process. ECREATE copies an SECS structure 
outside the EPC into an SECS page insi de the EPC. The internal structure of SECS is not accessible to software.
ECREATE will set up fields in the protected SECS and mark the page as valid inside the EPC. ECREATE initializes or 
checks unused fields.
Software sets the following fields in the source stru cture: SECS:BASEADDR, SECS:S IZE in bytes, ATTRIBUTES, 
CONFIGID, and CONFIGSVN. SECS:BASEADDR must be natu rally aligned on an SECS.SIZE boundary. SECS.SIZE 
must be at least 2 pages (8192).
The source operand RBX contains an effective address of a PAGEINFO structure. PAGEINFO contains an effective 
address of a source SECS and an effective address of an SECINFO. The SECS field in PAGEINFO is not used.
The RCX register is the effective address of the destination SECS. It is an address of an empty slot in the EPC. The 
SECS structure must be page aligned. SECINFO flags must specify the page as an SECS page. 
ECREATE Memory Parameter Semantics
ECREATE will fault if the SECS target page is in use; already valid; outside the EPC. It will also fault if addresses are 
not aligned; unused PAGEINFO fields are not zero.
If the amount of space needed to store the SSA frame is greater than the amount specified in SECS.SSAFRAME-
SIZE, a #GP(0) results. The amount of space needed for an SSA frame is computed based on DS:TMP_SECS.ATTRIBUTES.XFRM size. Details of computing the size can be found Section 39.7.
EAX = 00H
ENCLS[ECREATE]IR V/V SGX1 This leaf function begins an enclave build by creating an SECS 
page in EPC.
IR ECREATE (In) Address of a PAGEINFO (In) A ddress of the destination SECS page (In)
PAGEINFO PAGEINFO.SRCPGE P AGEINFO.SECINFO EPCPAGE
Read access permitted by 
Non Enclave Read access permitted by 
Non Enclave Read access permitted by Non 
Enclave Write access permitted by 
Enclave
Table 38-15.  Base Concurre ncy Restrictions of ECREATE
ECREATE SECS [DS:RCX] Exclusive # GP EPC_PAGE_CONFLICT_EXCEPTIONVol. 3D 38-31INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in ECREATE Operational Flow
TMP_SECINFO := DS:RBX.SECINFO;
IF (DS:TMP_SRCPGE is not 4KByte aligned or DS:TMP_SECINFO is not 64Byte aligned)
IF (DS:RBX.LINADDR ! = 0 or DS:RBX.SECS ≠ 0)
(* Check for misconfigured SECINFO flags*)
IF (DS:TMP_SECINFO reserved fields are not zero or DS:TMP_SECINFO.FLAGS.PT ≠ PT_SECS) 
TMP_SECS := RCX;IF (EPC entry in use) 
THEN 
THEN
VMCS.Exit_reason := SGX_CONFLICT;Table 38-16.  Additional Concurrency Restrictions of ECREATE
ECREATE SECS [DS:RCX] Concurrent Concurrent Concurrent
TMP_SRCPGE Effective Address 32/64 Effectiv e address of the SECS source page.
attributes of the SECS page to be added.
TMP_XSIZE SSA Size 64 The size calculation of SSA frame.TMP_MISC_SIZE MISC Field Size 64 Size of the selected MISC field components.
TMPUPDATEFIELD SHA256 Bu ffer 512 Buffer used to hold data being added to TMP_SECS.MRENCLAVE.38-32 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
VMCS.Exit_qualification.code :=  EPC_PAGE_CONFLICT_EXCEPTION;
VMCS.Exit_qualification.error := 0;VMCS.Guest-physical_address := 
<< translation of DS:TMP_SECS produced by paging >>;
VMCS.Guest-linear_address := DS:TMP_SECS;
#GP(0);
FI;
FI;
IF (EPC entry in use) 
IF (EPCM(DS:RCX).VALID = 1) 
DS:RCX[32767:0] := DS :TMP_SRCPGE[32767:0];
(* Check lower 2 bits of XFRM are set *)
IF ( ( DS:TMP_SECS.ATTRIBUTES.XFRM BitwiseAND 03H) ≠ 03H) 
IF (XFRM is illegal) 
(* Check legality of CET_ATTRIBUTES *)
IF ((DS:TMP_SECS.ATTRIBUTES.CET = 0 and DS:TMP_SECS.CET_ATTRIBUTES ≠ 0) ||
(DS:TMP_SECS.ATTRIBUTES.CET = 0 and DS:TMP_SECS.CET_LEG_BITMAP_OFFSET ≠ 0) ||
(CPUID.(EAX=7, ECX=0):EDX[CET_IBT] = 0 and DS:TMP_SECS.CET_LEG_BITMAP_OFFSET ≠ 0) ||
(CPUID.(EAX=7, ECX=0):EDX[CET_IBT] = 0 and DS:TMP_SECS.CET_ATTRIBUTES[5:2] ≠ 0) ||
(CPUID.(EAX=7, ECX=0):ECX[CET_SS] = 0 and DS:TMP_SECS.CET_ATTRIBUTES[1:0] ≠ 0) ||
(DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 1 and (DS:TMP_SECS.BASEADDR + DS:TMP_SECS.CET _LEG_BITMAP_OFFSET) not canonical) ||
(DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 0 and (DS:TMP_SECS.BASEADDR + DS:TMP_SECS.CET_L EG_BITMAP_OFFSET) & 0xFFFFFFFF00000000) ||
(DS:TMP_SECS.CET_ATTRIBUTES.reserved fields not 0) or (DS:TMP_SECS.CET_LEG_BITMAP_OFFSET) is not page aligned))THEN
#GP(0);
FI;
(* Make sure that the SECS does not have any un supported MISCSELECT options*)
IF ( !(CPUID.(EAX=12H, ECX=0):EBX[31:0] & DS:TMP_SECS.MISCSELECT[31:0]) )
THEN
EPCM(DS:TMP_SECS).EntryLock.Release();#GP(0);
FI;
( * Compute size of MISC area *)
TMP_MISC_SIZE := compute_misc_region_size();
(* Compute the size required to save state of the enclave on async exit, see Section 39.7.2.2*)Vol. 3D 38-33INTEL® SGX INSTRUCTION REFERENCES
TMP_XSIZE := compute_xsave_size(DS:TMP_SECS.A TTRIBUTES.XFRM) + GPR_SIZE + TMP_MISC_SIZE;
(* Ensure that the declared area is la rge enough to hold XSAVE and GPR stat *)
IF ( DS:TMP_SECS.SSAFRAMESIZE*4096 < TMP_XSIZE) 
IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 1) and (DS:TMP_SECS.BASEADDR is not canonical) )
IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 0) an d (DS:TMP_SECS.BASEADDR and 0FFFFFFFF00000000H) )
IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 0) and (DS:TMP_SECS.SIZE ≥ 2 ^ (CPUID.(EAX=12H, ECX=0):.EDX[7:0]) ) )
IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 1) and (DS:TMP_SECS.SIZE ≥ 2 ^ (CPUID.(EAX=12H, ECX=0):.EDX[15:8]) ) )
(* Enclave size must be at least 8192 by tes and must be power of 2 in bytes*)
IF (DS:TMP_SECS.SIZE < 8192 or popcnt(DS:TMP_SECS.SIZE) > 1) 
(* Ensure base address of an  enclave is aligned on size*)
IF ( ( DS:TMP_SECS.BASEADDR and (DS:TMP_SECS.SIZE-1) ) )
(* Ensure the SECS does not have any unsupported attributes*)
IF ( DS:TMP_SECS.ATTRIBUTES an d (~CR_SGX_ATTRI BUTES_MASK) )
IF ( DS:TMP_SECS reserved fields are not zero) 
(* Verify that CONFIGID/CONFIGS VN are not set with attribute *)
IF ( ((DS:TMP_SECS.CONFIGID ≠ 0) or (DS:TMP_SECS.CONFIGSVN ≠0)) AND (DS:TMP_SECS.A TTRIBUTES.KSS == 0 ))
Clear DS:TMP_SECS to Uninitialized;
DS:TMP_SECS.MRENCLAVE := SHA256INITIALIZE(DS:TMP_SECS.MRENCLAVE);
DS:TMP_SECS.ISVSVN := 0;DS:TMP_SECS.ISVPRODID := 0;
(* Initialize hash updates etc*)
Initialize enclave’s MRENCLAVE update counter;
(* Add “ECREATE” string and SECS fields to MRENCLAVE *)
TMPUPDATEFIELD[63:0] := 0045544145524345H; // “ECREATE”TMPUPDATEFIELD[95:64] := DS:TMP_SECS.SSAFRAMESIZE;TMPUPDATEFIELD[159:96] := DS:TMP_SECS.SIZE;IF (CPUID.(EAX=7, ECX=0):EDX[CET_IBT] = 1)
THEN
TMPUPDATEFIELD[223:160] := DS:T MP_SECS.CET_LEG_BITMAP_OFFSET;
ELSE
TMPUPDATEFIELD[223:160] := 0;38-34 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
FI;
TMPUPDATEFIELD[511:160] := 0; DS:TMP_SECS.MRENCLAVE := SHA256UPDATE(DS:TMP_SECS.MRENCLAVE, TMPUPDATEFIELD)
(* Set EID *)
DS:TMP_SECS.EID := LockedXAdd(CR_NEXT_EID, 1);

THEN
ELSE
FI;
(* Initialize the virtual child count to zero *)
DS:TMP_SECS.VIRTCHILDCNT := 0;
(* Load ENCLAVECONTEXT with Address out of paging of SECS *)
<< store translation of DS:R CX produced by paging in SECS(DS:RCX).ENCLAVECONTEXT >>
(* Set the EPCM entry, first create SECS identifier and store the identifier in EPCM *)
EPCM(DS:TMP_SECS).PT := PT_SECS;EPCM(DS:TMP_SECS).ENCLAVEADDRESS := 0;EPCM(DS:TMP_SECS).R := 0;EPCM(DS:TMP_SECS).W := 0;EPCM(DS:TMP_SECS).X := 0;
EPCM(DS:RCX).BLOCKED := 0;EPCM(DS:RCX).PENDING := 0;EPCM(DS:RCX).MODIFIED := 0;EPCM(DS:RCX).PR := 0;EPCM(DS:RCX).VALID := 1;
None
#GP(0) If a memory operand effective address is outside the DS segment limit.
If a memory operand is not properly aligned.If the reserved fields are not zero.
If PAGEINFO.SECS is not zero.
If PAGEINFO.LINADDR is not zero.If the SECS destination is locked.
If SECS.SSAFRAMESIZE is insufficient.
If the SECS destination is outside the EPC.
#GP(0) If a memory address is non-canonical form.
If SECS.SSAFRAMESIZE is insufficient.Vol. 3D 38-35INTEL® SGX INSTRUCTION REFERENCES
If the SECS destination is outside the EPC.38-36 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EDBGRD—Read From a Debug Enclave 
This leaf function copies a quadword/doubleword from an EPC page belonging to a debug enclave into the RBX 
register. Eight bytes are read in 64-bit mode, four bytes are read in non-64-bit modes. The size of data read cannot 
be overridden.
The effective address of the source location in side the EPC is provided in the register RCX.
EDBGRD Memory Parameter Semantics
EDBGRD Faulting Conditions
This instruction ignores the EPCM RWX attributes on the enclave page. Consequently, violation of EPCM RWX attri-
butes via EDBGRD does not result in a #GP.Opcode/
EAX = 04H
ENCLS[EDBGRD]IR V/V SGX1 This leaf function reads a dword/quadword from a debug enclave.
IR EDBGRD (In)Return error 
code (Out)Data read from a debug enclave (Out) Address of source memory in the EPC (In)
EPCQW
Read access permitted by Enclave 
Table 38-17.  EDBGRD Return Value in RAX
No Error EDBGRD successful.SGX_PAGE_NOT_DEBUGGABLE The EPC page cannot be accesse d because it is in the PENDING or MODIFIED state.
RCX points into a page that is an SECS. RCX does not resolve to a naturally aligned linear address.
RCX points to a page that  does not belong to an 
enclave that is in debug mode.RCX points to a location insi de a TCS that is beyond th e architectural size of the 
TCS (SGX_TCS_LIMIT).
An operand causing any segment violation. May page fault.
CPL > 0.Vol. 3D 38-37INTEL® SGX INSTRUCTION REFERENCES
Concurrency Restrictions
Operation
Temp Variables in EDBGRD Operational Flow
TMP_MODE64 := ((IA32_EFER.LMA = 1) && (CS.L = 1));
IF ( (TMP_MODE64 = 1) and (DS:RCX is not 8Byte Aligned) )
IF ( (TMP_MODE64 = 0) and (DS:RCX is not 4Byte Aligned) )
(* make sure no other Inte l SGX instruction is accessi ng the same EPCM entry *)
IF (Another instruction modifying the same EPCM entry is executing) 
IF (EPCM(DS:RCX).VALID = 0)
(* make sure that DS:RCX (S OURCE) is pointing  to a PT_REG or PT_TCS or PT_VA or PT_SS_FIRST or PT_SS_REST *) 
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) and (E PCM(DS:RCX).PT ≠ PT_VA)
and (EPCM(DS:RCX).PT ≠ PT_SS_FIRST) and (EPCM(DS:RCX).PT ≠ PT_SS_REST))
(* make sure that DS:RCX poin ts to an accessible EPC page *)
IF (EPCM(DS:RCX).PENDING is not 0 or (EPCM(DS:RCX).MODIFIED is not 0) )
THEN
RFLAGS.ZF := 1;Table 38-18.  Base Concurrency Restrictions of EDBGRD
EDBGRD Target [DS:RCX] Shared #GP
Table 38-19.  Additional Conc urrency Restrictions of EDBGRD
EDBGRD Target [DS:RCX] Concurrent Concurrent Concurrent
TMP_MODE64 Binary 1 ((IA32_EFER.LMA = 1) && (CS.L = 1))
TMP_SECS  64 Physical address of SECS of the enclave to which source operand belongs.38-38 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
RAX := SGX_PAGE_NOT_DEBUGGABLE;
GOTO DONE;
FI;
(* If source is a TCS, then make sure that the offset into  the page is not beyond the TCS size*)
IF ( ( EPCM(DS:RCX). PT = PT_TCS) and ((DS:RCX) & FFFH ≥ SGX_TCS_LIMIT) )
(* make sure the enclave owning the PT _REG or PT_TCS page allow debug *) 
IF ( (EPCM(DS:RCX).PT = PT_REG) or (EPCM(DS:RCX).PT = PT_TCS) )
THEN 
TMP_SECS := GET_SECS_ADDRESS;IF (TMP_SECS.ATTRIB UTES.DEBUG = 0) 
IF ( (TMP_MODE64 = 1) )
THEN RBX[63:0] := (DS:RCX)[63:0]; ELSE EBX[31:0] := (DS:RCX)[31:0]; 
FI;
ELSE
TMP_64BIT_VAL[63:0] := (DS:RCX)[63:0] & (~07H); // Read contents from VA slotIF (TMP_MODE64 = 1) 
THEN
IF (TMP_64BIT_VAL ≠ 0H) 
THEN RBX[63:0] := 0FFFFFFFFFFFFFFFFH;ELSE RBX[63:0] := 0H;
FI;
ELSE
THEN EBX[31:0] := 0FFFFFFFFH;ELSE EBX[31:0] := 0H;
FI;
FI;
(* clear EAX and ZF to indica te successful completion *) 
RAX := 0;RFLAGS.ZF := 0;
DONE:
(* clear flags *)RFLAGS.CF,PF,AF,OF,SF := 0;
ZF is set if the page is MODIFIED or PENDING; RAX contai ns the error code. Otherwise ZF is cleared and RAX is set 
to 0. CF, PF, AF, OF, SF are cleared.
#GP(0) If the address in RCS violates DS limit or access rights.
If DS segment is unusable.
If RCX points to a memory location not 4Byte-aligned.
If the address in RCX points to a pa ge belonging to a non-debug enclave.
If the address in RCX points to a page which is not PT_TCS, PT_REG or PT_VA.
If the address in RCX points to a location inside TCS that is beyond SGX_TCS_LIMIT.Vol. 3D 38-39INTEL® SGX INSTRUCTION REFERENCES
If the address in RCX points to a non-EPC page.If the address in RCX points to an invalid EPC page.
#GP(0) If RCX is non-canonical form.
If RCX points to a memory location not 8Byte-aligned.If the address in RCX points to a page belonging to a non-debug enclave.
If the address in RCX points to a location inside TCS that is beyond SGX_TCS_LIMIT.
If the address in RCX points to a non-EPC page.
If the address in RCX points to an invalid EPC page.38-40 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EDBGWR—Write to a Debug Enclave 
This leaf function copies the content in EBX/RBX to an  EPC page belonging to a debug enclave. Eight bytes are 
written in 64-bit mode, four bytes are written in non- 64-bit modes. The size of data cannot be overridden.
The effective address of the target location in side the EPC is provided in the register RCX.
EDBGWR Memory Parameter Semantics
EDBGWR Faulting Conditions
EAX = 05H
ENCLS[EDBGWR]IR V/V SGX1 This leaf function writes a dword/quadword to a debug enclave.
IR EDBGWR (In)Return error 
code (Out)Data to be written to a de bug enclave (In) Address of Target memory in the EPC (In)
EPCQW
Write access permitted by Enclave 
enclave that is in debug mode.RCX points to a location inside a TCS that is not the FLAGS word.
CPL > 0.
Table 38-20.  EDBGWR Return Value in RAX
No Error EDBGWR successful.SGX_PAGE_NOT_DEBUGGABLE The EPC page cannot be access ed because it is in the PENDING or MODIFIED state.Vol. 3D 38-41INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EDBGWR Operational Flow

EAX = 05H
EPCQW
CPL > 0.
Operation
(* make sure that DS:RCX (DST) is  pointing to a PT_REG or PT_TCS or PT_SS_FIRST or PT_SS_REST *) 
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) 
IF ( (EPCM(DS:RCX).PENDING is not 0) or  (EPCM(DS:RCS).MODI FIED is not 0) )
THEN
RFLAGS.ZF := 1;Table 38-21.  Base Concurrency Restrictions of EDBGWR
EDBGWR Target [DS:RCX] Shared #GP
Table 38-22.  Additional Conc urrency Restrictions of EDBGWR
EDBGWR Target [DS:RCX] Concurrent Concurrent Concurrent
TMP_MODE64 Binary 1 ((IA32_EFE R.LMA = 1) && (CS.L = 1)).
TMP_SECS  64 Physical address of SECS of the enclave to which source operand belongs.38-42 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
GOTO DONE;
FI;
(* If destination is a TCS, then make sure that the of fset into the page can only  point to the FLAGS field*)
IF ( ( EPCM(DS:RCX). PT = PT_TCS) and ((DS:RCX) & FF8H ≠ offset_of_FLAGS & 0FF8H) )
(* Locate the SECS for the enclave to  which the DS:RCX page belongs *) 
TMP_SECS := GET_SECS_PHYS_ADDRESS(EPCM(DS:RCX).ENCLAVESECS);
IF (TMP_SECS.ATTRIBUTES.DEBUG = 0) 
THEN (DS:RCX)[63:0] := RBX[63:0]; ELSE (DS:RCX)[31:0] := EBX[31:0]; 
FI;
DONE:
(* clear flags *)RFLAGS.CF,PF,AF,OF,SF := 0
If the address in RCX points to a page which is not PT_TCS or PT_REG.
If the address in RCX points to a location inside TCS that is not the FLAGS word.
If the address in RCX points to an invalid EPC page.
If RCX points to a memory location not 8Byte-aligned.
If the address in RCX points to a page which is not PT_TCS or PT_REG.If the address in RCX points to a location inside TCS that is not the FLAGS word.Vol. 3D 38-43INTEL® SGX INSTRUCTION REFERENCES
If the address in RCX points to a non-EPC page.If the address in RCX points to an invalid EPC page.38-44 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EEXTEND—Extend Uninitialized En clave Measurement by 256 Bytes 
This leaf function updates the MRENCL AVE measurement register of an SECS with the measurement of an EXTEND 
string compromising of “EEXTEND” || ENCLAVEOFFSET || PA DDING || 256 bytes of the en clave page. This instruc-
tion can only be executed when current privile ge level is 0 and the enclave is uninitialized. 
RBX contains the effective address of th e SECS of the region to be measured. The address must be the same as the 
one used to add the page into the enclave.
RCX contains the effective address of th e 256 byte region of an EPC page to be measured. The DS segment is used 
to create linear addresses. Segment override is not supported.
EEXTEND Memory Pa rameter Semantics
EEXTEND Faulting Conditions
EAX = 06H
ENCLS[EEXTEND]IR V/V SGX1 This leaf function measures 256 bytes of an uninitialized enclave 
page.
Op/En EAX EBX RCX
IR EEXTEND (In)Effective address of the SECS of the 
data chunk (In)Effective address of a 256-byte chunk in the EPC (In)
EPC[RCX]
Read access by Enclave 
RBX points to an address not 4KBytes aligned. RBX does  not resolve to an SECS.
RBX does not point to an SECS page. RBX does not point to the SECS pa ge of the data chunk.
RCX points to an addr ess not 256B aligned. RCX points to an unused page or a SECS.
RCX does not resolve in an EPC page. If SECS is locked.
If the SECS is already initialized. May page fault.CPL > 0.
Table 38-23.  Base Concurrency Restrictions of EEXTEND
EEXTEND Target [DS:RCX] Shared #GP
SECS [DS:RBX] ConcurrentVol. 3D 38-45INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EEXTEND Operational Flow
IF (DS:RBX is not 4096 Byte Aligned)
IF (DS:RBX does not resolve to an EPC page) 
THEN #PF(DS:RBX); FI;
IF (DS:RCX is not 256Byte Aligned) 
(* make sure no other Intel SGX instruction is accessing EPCM *)
IF (Other instructio ns accessing EPCM) 
TMP_SECS := Get_SECS_ADDRESS();IF (DS:RBX does not resolve to TMP_SECS)
(* make sure no other instruction is accessing MRENCLAVE or ATTRIBUTES.INIT *) 
IF ( (Other instruction accessing MRENCLAVE) or (Other instructions checking or updating the initialized state of the SECS)) Table 38-24.  Additional Concurrency Restrictions of EEXTEND
EEXTEND Target [DS:RCX] Con current Concurrent Concurrent
TMP_SECS  64 Physical address of SECS of the enclave to which source operand belongs.
TMP_ENCLAVEOFFS
ETEnclave Offset 64 The page displacement from the enclave base address.
TMPUPDATEFIELD SHA256 Buffer 512 Buffer used to hold data being added to TMP_SECS.MRENCLAVE.38-46 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
(* Calculate enclave offset *)
TMP_ENCLAVEOFFSET := EPCM(DS:RCX).ENCLAVEADDRESS - TMP_SECS.BASEADDR;TMP_ENCLAVEOFFSET := TMP_ENCLAVEOFFSET + (DS:RCX & 0FFFH)
(* Add EEXTEND message and offset to MRENCLAVE *)
TMPUPDATEFIELD[63:0] := 00444E4554584545H; // “EEXTEND”TMPUPDATEFIELD[127:64] := TMP_ENCLAVEOFFSET;TMPUPDATEFIELD[511:128] := 0; // 48 bytesTMP_SECS.MRENCLAVE := SHA256UPDATE(T MP_SECS.MRENCLAVE, TMPUPDATEFIELD)
(*Add 256 bytes to MRENCLAVE,  64 byte at a time *) 
TMP_SECS.MRENCLAVE := SHA256UPDATE(T MP_SECS.MRENCLAVE,  DS:RCX[511:0] );
TMP_SECS.MRENCLAVE := SHA256UPDATE(TMP _SECS.MRENCLAVE, DS :RCX[1023: 512] );
TMP_SECS.MRENCLAVE := SHA256UPDATE(TMP _SECS.MRENCLAVE, DS :RCX[1535: 1024] );
TMP_SECS.MRENCLAVE := SHA256UPDATE(TMP _SECS.MRENCLAVE, DS :RCX[2047: 1536] );
INC enclave’s MRENCLAVE update counter by 4;
None
#GP(0) If the address in RBX is outside the DS segment limit.
If RBX points to an SECS page which is not the SECS of the data chunk.If the address in RCX is outside the DS segment limit.
If RCX points to a memory location not 256Byte-aligned.
If another instruction is accessing MRENCLAVE.If another instruction is checking or updating the SECS.
If the enclave is already initialized.
If the address in RBX points to a non-EPC page.
#GP(0) If RBX is non-canonical form.

None
If RBX points to an SECS page which is not the SECS of the data chunk.If RCX is non-canonical form.
If RCX points to a memory location not 256 Byte-aligned.
If the address in RCX points to a non-EPC page.If the address in RCX points to an invalid EPC page.Vol. 3D 38-47INTEL® SGX INSTRUCTION REFERENCES
EINIT—Initialize an Enclave for Execution 
This leaf function is the final instruction executed in  the enclave build process. After EINIT, the MRENCLAVE 
measurement is complete, and the enclave is ready to start user code execution using the EENTER instruction.
EINIT takes the effective address of a SIGSTRUCT an d EINITTOKEN. The SIGSTRUCT describes the enclave 
including MRENCLAVE, ATTRIBUTES, ISVSVN, a 3072 bit RSA key, and a signature using the included key. 
SIGSTRUCT must be populated with two values, q1 and q2 . These are calculated using the formulas shown below: 
q1 = floor(Signature2 / Modulus);
q2 = floor((Signature3 - q1 * Signature * Modulus) / Modulus);
The EINITTOKEN contains the MRENCLAVE, MRSIGNER, and ATTRIBUTES. These values must match the corre-
sponding values in the SECS. If the EINITTOKEN was created with a debug launch key, the enclave must be in 
debug mode as well. Opcode/
EAX = 02H
ENCLS[EINIT]IR V/V SGX1 This leaf function initializes the enclave and makes it ready to 
execute enclave code.
Op/En EAX RBX RCX RDX
IR EINIT (In) Error code (Out) Address of SIGSTRUCT (In) Address of SECS (In) Address of EINITTOKEN (In)
Figure 38-1.  Relationships Between  SECS, SIGSTRUCT, and EINITTOKENMRSIGNER
ATTRIBUTES
MRENCLAVEHashed
Check
If VALID=1, CheckSignature
ATTRIBUTESPubKey
ATTRIBUTEMASK
MRENCLAVE
SIGSTRUCTVerify
DS:RBX
EINIT
SECS
ENCLAVE
EPCATTRIBUTES
MRENCLAVEMRSIGNER
If VALID=1, 
Check
Copy
DS:RCX
CheckDS:RDX
EINITTOKEN38-48 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EINIT Memory Para meter Semantics
EINIT performs the following steps, which can be seen in Figure 38-1:
1. Validates that SIGSTRUCT is signed using the enclosed public key.
2. Checks that the completed computation of SECS.MRENCLAVE equals SIGSTRUCT.HASHENCLAVE.
3. Checks that no controlled ATTRIBUTES bits are set in SIGSTRUCT.ATTRIBUTES unless the SHA256 digest of 
SIGSTRUCT.MODULUS equals IA32_SGX_LEPUBKEYHASH. 
4. Checks that the result of bitwise and-ing SIGSTR UCT.ATTRIBUTEMASK with SIGSTRUCT.ATTRIBUTES equals 
the result of bitwise and-ing SIGSTRUC T.ATTRIBUTEMASK with SECS.ATTRIBUTES. 
5. If EINITTOKEN .VALID is 0, checks that the SHA256 digest of SIGSTRUCT.MODULUS equals 
IA32_SGX_LEPUBKEYHASH. 
6. If EINITTOKEN .VALID is 1, checks the validity of EINITTOKEN . 
7. If EINITTOKEN .VALID is 1, checks that EINITTOKEN .MRENCLAVE equals SECS.MRENCLAVE. 
8. If EINITTOKEN .VALID is 1 and EINITTOKEN .ATTRIBUTES.DEBUG is 1, SECS.ATTRIBUTES.DEBUG must be 1. 
9. Commits SECS.MRENCLAVE, and sets SECS.MRSIGNER, SECS.ISVSVN, and SECS.ISVPRODID based on 
SIGSTRUCT. 
10. Update the SECS as Initialized.
Periodically, EINIT polls for certain asynchronous events. If such an event is detected, it completes with failure code 
(ZF=1 and RAX = SGX_UNMASKED_EVENT), and RIP is incremen ted to point to the next instruction. These events 
includes external interrupts, non-maskable interrupts,  system-management interrup ts, machine checks, INIT 
signals, and the VMX-preemption timer. EINIT does not fail if the pending event is inhi bited (e.g., external inter-
rupts could be inhibited due to blocking by MOV SS blocking or by STI). 
The following bits in RFLAGS are cleared: CF, PF, AF, OF , and SF. When the instruction completes with an error, 
RFLAGS.ZF is set to 1, and the corresponding error bit is set in RAX. If no error occurs, RFLAGS.ZF is cleared and 
RAX is set to 0.
The error codes are: SIGSTRUCT SECS EINITTOKEN
 Access by non-Enclave Re ad/Write access by Enclav e  Access by non-Enclave 
Table 38-25.  EINIT Return Value in RAX
No Error EINIT successful.SGX_INVALID_SIG_STRUCT If SIGSTRUCT contained an invalid value.SGX_INVALID_ATTRIBUTE If SIGSTRUCT contains an unauthorized attributes mask.SGX_INVALID_MEASUREMENTIf SIGSTRUCT contains an incorrect measurement.
If EINITTOKEN contains an incorrect measurement.
SGX_INVALID_SIGNATURE If signature does not validate with enclosed public key.SGX_INVALID_LICENSE If license is invalid.SGX_INVALID_CPUSVN If license SVN is unsupported.SGX_UNMASKED_EVENT If an unmasked event is received before the instruction completes its operation.Vol. 3D 38-49INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EINIT Operational Flow
(* make sure SIGSTRUCT and SECS are aligned *)
IF ( (DS:RBX is not 4KByte Aligned) or (DS:RCX is not 4KByte Aligned) )
(* make sure the EINI TTOKEN is aligned *)
IF (DS:RDX is not 512Byte Aligned) 
(* make sure the SECS  is inside the EPC *)
IF (DS:RCX does not resolve within an EPC) 
TMP_SIG[14463:0] := DS:RBX[14463:0]; // 1808 bytes
TMP_TOKEN[2423:0] := DS:RDX[2423:0]; // 304 bytesTable 38-26.  Base Concurrency Restrictions of EINIT
EINIT SECS [DS:RCX] Shared #GP
Table 38-27.  Additional Concurrency Restrictions of ENIT
EINIT SECS [DS:RCX] Concurrent Exclusive #GP Concurrent
Name Type Size Description
TMP_SIG  SIGSTRUCT 1808Bytes Temp space for SIGSTRUCT.
TMP_TOKEN  EINITTOKEN 304Bytes Temp space for EINITTOKEN.
TMP_MRENCLAVE  32Bytes Temp space for calculating MRENCLAVE.TMP_MRSIGNER  32Bytes Temp space for calculating MRSIGNER.
CONTROLLED_ATTRIBU
TESATTRIBUTES 16Bytes Constant mask of all ATTRIBUT E bits that can only be set for authorized 
enclaves.
TMP_KEYDEPENDENCIE
S Buffer 224Bytes Temp space for key derivation.
TMP_EINITTOKENKEY  16Bytes Temp spac e for the derived EINITTOKEN Key.
TMP_SIG_PADDING PKCS Padding 
Buffer352Bytes The value of the top 352 bytes from the computation of Signature
3 
modulo MRSIGNER.38-50 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
(* Verify SIGSTRUCT Header. *)
IF ( (TMP_SIG.HEADER ≠ 06000000E10000000000010000000000h) or
((TMP_SIG.VENDOR ≠ 0) and (TMP_SIG.VENDOR ≠ 00008086h) ) or
(TMP_SIG HEADER2 ≠ 01010000600000006000000001000000h) or
(TMP_SIG.EXPONENT   ≠ 00000003h) or (Reserved space is not 0’s) )
THEN 
RFLAGS.ZF := 1;RAX := SGX_INVALID_SIG_STRUCT;GOTO EXIT;
FI;
(* Open “Event Window” Check for Interrupts. Verify signature using embedded public key, q1, and q2. Save upper 352 bytes of th e 
PKCS1.5 encoded message into the TMP_SIG_PADDING*)
IF (interrupt was pending) THEN
RFLAGS.ZF := 1;RAX := SGX_UNMASKED_EVENT;GOTO EXIT;
FIIF (signature failed to verify) THEN
RFLAGS.ZF := 1;RAX := SGX_INVALID_SIGNATURE;GOTO EXIT;
FI;(*Close “Event Window” *)
(* make sure no other Intel SGX instruction is modifying SECS*)
IF (Other instructions modifying SECS) 
IF ( (EPCM(DS:RCX). VALID = 0) or (EPCM(DS:RCX).PT ≠ PT_SECS) )
(* Verify ISVFAMILYID is not used on an enclave with KSS disabled *)
IF ((TMP_SIG.ISVFAMILYID != 0) AND (DS:RCX.ATTRIBUTES.KSS == 0))
THEN 
        RFLAGS.ZF := 1;        RAX := SGX_INVALID_SIG_STRUCT;
        GOTO EXIT;FI;
IF ( (Other instruction modifying MRENCLAVE) or (Other instructions modifying the SECS’s Initialized state)) 
(* Calculate finalized version of MRENCLAVE *)
(* SHA256 algorithm requires one last upda te that compresses the length of the hashed message into the output SHA256 digest *)
TMP_ENCLAVE := SHA256FINAL( (DS:RCX).MRENCLAVE, enclave’s MRENCLAVE update count *512);
(* Verify MRENCLAVE from SIGSTRUCT *)
IF (TMP_SIG.ENCLAVEHASH ≠ TMP_MRENCLAVE)
RFLAGS.ZF := 1;RAX := SGX_INVALID_MEASUREMENT;GOTO EXIT;
FI;Vol. 3D 38-51INTEL® SGX INSTRUCTION REFERENCES
TMP_MRSIGNER := SHA256(TMP_SIG.MODULUS)
(* if controlled ATTRIBUTES ar e set, SIGSTRUCT must be sign ed using an authorized key *)
CONTROLLED_ATTRIBUTES := 0000000000000020H;IF ( ( (DS:RCX.ATTRIBUTES & CONTROLLED_ATTRIBUTES) ≠ 0) and (TMP_MRSIGNER ≠ IA32_SGXLEPUBKEYHASH) )
RFLAGS.ZF := 1;RAX := SGX_INVALID_ATTRIBUTE;GOTO EXIT;
FI;
(* Verify SIGSTRUCT.ATTRIBUTE requirements are met *)
IF ( (DS:RCX.ATTRIBUTES & TMP_SIG.ATTRIBUTEMASK) ≠ (TMP_SIG.ATTRIBUTE & TMP_SIG.ATTRIBUTEMASK) )

FI;
FI;
( *Verify SIGSTRUCT.MISCSELECT requirements are met *)
IF ( (DS:RCX.MISCSELECT & TMP_SIG.MISCMASK) ≠ (TMP_SIG.MISCSELECT & TMP_SIG.MISCMASK) )
THEN
RFLAGS.ZF := 1;RAX := SGX_INVALID_ATTRIBUTE;
GOTO EXIT
FI;
IF (CPUID.(EAX=12H, ECX=1):EAX[6] = 1)
IF ( DS:RCX.CET_ATTRIBUTES & TMP_SIG.CET_ATTRIBUTES_MASK ≠ TMP_SIG.CET_ATTRIBUTES & 
 TMP_SIG.CET_ATTRIB-UTES_MASK )
THEN
RFLAGS.ZF := 1;RAX := SGX_INVALID_ATTRIBUTE;GOTO EXIT
FI;
FI;
(* If EINITTOKEN.VALID[0] is 0, verify the enclave is sign ed by an authorized key *)
IF (TMP_TOKEN.VALID[0] = 0)
IF (TMP_MRSIGNER ≠ IA32_SGXLEPUBKEYHASH)
RFLAGS.ZF := 1;RAX := SGX_INVALID_EINITTOKEN;GOTO EXIT;
FI;GOTO COMMIT;
FI;
(* Debug Launch Encl ave cannot launch Pr oduction Enclaves *)
IF ( (DS:RDX.MASKEDATTRIBUTESLE.DEBUG = 1) and (DS:RCX.ATTRIBUTES.DEBUG = 0) )
FI;38-52 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
(* Check reserve space in EINIT token includes reserved regions and upper bits in valid field *)
IF (TMP_TOKEN reserved space is not clear)
FI;
(* EINIT token must not have been created by a configuration beyond the current CPU configuration *)
IF (TMP_TOKEN.CPUSVN must not be a configuration beyond CR_CPUSVN)
RFLAGS.ZF := 1;RAX := SGX_INVALID_CPUSVN;GOTO EXIT;
FI;
(* Derive Launch key used to calculate EINITTOKEN.MAC *)
HARDCODED_PKCS1_5_PADDING[15:0] := 0100H;HARDCODED_PKCS1_5_PADDING[2655:16] := SignExtend330Byte(-1); // 330 bytes of 0FFHHARDCODED_PKCS1_5_PADDING[2815:2656] :=  2004000501020403650148866009060D30313000H;
TMP_KEYDEPENDENCIES.KEYNA ME := EINITTOKEN_KEY;
TMP_KEYDEPENDENCIES.ISVFAMILYID := 0;TMP_KEYDEPENDENCIES. ISVEXTPRODID := 0;
TMP_KEYDEPENDENCIES.ISVPRODI D := TMP_TOKEN.ISVPRODIDLE;
TMP_KEYDEPENDENCIES.ISVSVN  := TMP_TOKEN.ISVSVNLE;
TMP_KEYDEPENDENCIES.SGXOWNER EPOCH := CR_SGXOWNEREPOCH;
TMP_KEYDEPENDENCIES.ATTRIBUTES :=  TMP_TOKEN.MASKEDATTRIBUTESLE;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK := 0;TMP_KEYDEPENDENCIES.MRENCLAVE := 0;TMP_KEYDEPENDENCIES.MRSIGNER  := IA32_SGXLEPUBKEYHASH;
TMP_KEYDEPENDENCIES.KEYID := TMP_TOKEN.KEYID;TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES := CR_SEAL_FUSES;TMP_KEYDEPENDENCIES.CPUSVN := TMP_TOKEN.CPUSVNLE;TMP_KEYDEPENDENCIES.MISCSELECT :=  TMP_TOKEN.MASKEDMISCSELECTLE;
TMP_KEYDEPENDENCIES.MISCMASK := 0;TMP_KEYDEPENDENCIES.PADDING :=  HARDCODED_PKCS1_5_PADDING;
TMP_KEYDEPENDENCIES.KEYPOLICY := 0;TMP_KEYDEPENDENCIE S.CONFIGID := 0;
TMP_KEYDEPENDENCIES.CONFIGSVN := 0;IF (CPUID.(EAX=12H, ECX=1):EAX[6] = 1))
TMP_KEYDEPENDENCIES.CET_ATTRIBUTES := TMP_TOKEN.CET_MASKED_ATTRIBUTES_ LE;
TMP_KEYDEPENDENCIES.CET_ATTRIBUTES_MASK := 0;
FI;
(* Calculate the derived key*) 
TMP_EINITTOKENKEY := derivekey(TMP_KEYDEPENDENCIES);
(* Verify EINITTOKEN was generated using this CPU's Launch key and that it has not been modified since issuing by the Launch 
Enclave. Only 192 bytes of EINITTOKEN are CMACed *)
IF (TMP_TOKEN.MAC ≠ CMAC(TMP_EINITTOKENKEY, TMP_TOKEN[1535:0] ) )
FI;Vol. 3D 38-53INTEL® SGX INSTRUCTION REFERENCES
(* Verify EINITTOKEN (RDX) is for this enclave *)
IF ( (TMP_TOKEN.MRENCLAVE ≠ TMP_MRENCLAVE) or (TMP_TOKEN.MRSIGNER ≠ TMP_MRSIGNER) )
FI;
(* Verify ATTRIBUTES in EINITTOKEN are the same as the enclave’s *)
IF (TMP_TOKEN.ATTRIBUTES ≠ DS:RCX.ATTRIBUTES)
RFLAGS.ZF := 1;RAX := SGX_INVALID_EINIT_ATTRIBUTE;GOTO EXIT;
FI;
COMMIT:
(* Commit changes to the SECS; Set ISVPRODID, ISVSVN, MRSIGN ER, INIT ATTRIBUTE fiel ds in SECS (RCX) *) 
DS:RCX.MRENCLAVE := TMP_MRENCLAVE;(* MRSIGNER stores a SHA 256 in little endian implem ented natively on x86 *) 
DS:RCX.MRSIGNER := TMP_MRSIGNER;DS:RCX.ISVEXTPRODID := TMP_SIG.ISVEXTPRODID;DS:RCX.ISVPRODID := TMP_SIG.ISVPRODID;DS:RCX.ISVSVN := TMP_SIG.ISVSVN;DS:RCX.ISVFAMILYID :=  TMP_SIG.ISVFAMILYID;
DS:RCX.PADDING := TMP_SIG_PADDING;
(* Mark the SECS as initialized *)
Update DS:RCX to initialized;
(* Set RAX and ZF for success*) 
RFLAGS.ZF := 0;RAX := 0;
EXIT:RFLAGS.CF,PF,AF,OF,SF := 0;
ZF is cleared if successful, otherwise ZF is set and RAX contains the error code. CF, PF, AF, OF, SF are cleared.
#GP(0) If a memory operand is not properly aligned.
If another instruction is modifying the SECS.If the enclave is already initialized.
If the SECS.MRENCLAVE is in use.
If RCX does not resolve in an EPC page.
If the memory address is not a valid, uninitialized SECS.
If another instruction is modifying the SECS.
If the SECS.MRENCLAVE is in use.38-54 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
If RCX does not resolve in an EPC page.If the memory address is not a valid, uninitialized SECS.Vol. 3D 38-55INTEL® SGX INSTRUCTION REFERENCES
ELDB/ELDU/ELDBC/ELDUC—Load an EPC Page and Mark its State 
This leaf function copies a page from regular main memory to the EPC. As part of the copying process, the page is 
cryptographically authenticated and decr ypted. This instruction can only be executed when current privilege level 
is 0.
The ELDB leaf function sets the BLOCK bit in the EPCM entry for the destination page in the EPC after copying. The 
ELDU leaf function clears the BLOCK bit in the EPCM entry for the destin ation page in the EPC after copying.
RBX contains the effective address of a PAGEINFO structur e; RCX contains the effective address of the destination 
EPC page; RDX holds the effective address of the vers ion array slot that holds the version of the page.
The ELDBC/ELDUC leafs are very similar to ELDB and ELDU. They provide an error code on the concurrency conflict 
for any of the pages which need to acquire a lock. These include the destination, SECS, and VA slot.
The table below provides additional information on the memory parameter of ELDB/ELDU leaf functions.
ELDB/ELDU/ELDBC/ELBUC Memory Parameter Semantics
The error codes are: Opcode/
EAX = 07H
ENCLS[ELDB]IR V/V SGX1 This leaf function loads, verifies an EPC page and marks the page 
as blocked.
EAX = 08H
ENCLS[ELDU]IR V/V SGX1 This leaf function loads, verifies an EPC page and marks the page 
as unblocked.
EAX = 12H
ENCLS[ELDBC]IR V/V EAX[6] This leaf function behaves lie ELDB but with improved conflict 
handling for oversubscription.
EAX = 13H
ENCLS[ELDUC]IR V/V EAX[6] This leaf function behaves li ke ELDU but with improved conflict 
IRELDB/ELDU 
(In)Return error 
code (Out)Address of the PAGEINFO 
(In)Address of the EPC page 
(In)Address of the version-
array slot (In)
PAGEINFO PAGEINFO.SRCPGE PAGEINFO.PCMD PA GEINFO.SECS EPCPAGE Version-Array Slot
Non-enclave 
read accessNon-enclave read 
accessNon-enclave read 
accessEnclave read/write 
accessRead/Write access 
permitted by EnclaveRead/Write access per-
mitted by Enclave
Table 38-28.  ELDB/ELDU/ELDBC/ELBUC Return Value in RAX
No Error ELDB/ELDU successful.SGX_MAC_COMPARE_FAIL If the MAC check fails.38-56 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in ELDB/ELDU/ELDBC/ELBUC Operational Flow
(* Check PAGEINFO and EPCPAGE alignment *)
IF ( (DS:RBX is not 32Byte Aligned) or (DS:RCX is not 4KByte Aligned) )
THEN #GP(0); FI;Table 38-29.  Base Concurrency Re strictions of ELDB/ELDU/ELDBC/ELBUC
ELDB/ELDU Target [DS:RCX] Exclusiv e #GP EPC_PAGE_CONFLICT_EXCEPTION
VA [DS:RDX] Shared #GPSECS [DS:RBX]PAGEINFO.SECS Shared #GP
ELDBC/ELBUC Target [DS:RCX] Exclusive SGX_EPC_PAGE_
CONFLICTEPC_PAGE_CONFLICT_ERROR
VA [DS:RDX] Shared SGX_EPC_PAGE_
CONFLICT
SECS [DS:RBX]PAGEINFO.SECS Shared SGX_EPC_PAGE_
CONFLICT
Table 38-30.  Additional Concurrency Restrictions of ELDB/ELDU/ELDBC/ELBUC
EACCEPTCOPY, EMODPE, 
EMODPR, EMODTvs. EADD, EEXTEND, 
ELDB/ELDU Target [DS:RCX] Concurrent Concurrent Concurrent
VA [DS:RDX] Concurrent Concurrent ConcurrentSECS [DS:RBX]PAGEINFO.SECS Concurrent Concurrent Concurrent
ELDBC/ELBUC Target [DS:RCX] Concurrent Concurrent Concurrent
TMP_SRCPGE Memory page 4KBytesTMP_SECS Memory page 4KBytes
TMP_PCMD PCMD 128 Bytes
TMP_HEADER MACHEADER 128 BytesTMP_VER UINT64 64
TMP_MAC UINT128 128
TMP_PK UINT128 128 Page encryption/MAC key.

CONFLICT
CONFLICT
SCRATCH_PCMD PCMD 128 BytesVol. 3D 38-57INTEL® SGX INSTRUCTION REFERENCES
(* Check VASLOT alignment *)
IF (DS:RDX is not 8Byte aligned)
IF (DS:RDX does not resolve within an EPC)
THEN #PF(DS:RDX); FI;
TMP_SECS := DS:RBX.SECS;TMP_PCMD := DS:RBX.PCMD;
(* Check alignment of PAGEINFO (RBX) linked parameters. Note: PCMD pointer is overlaid on top of PAGEINFO.SECINFO field *)
IF ( (DS:TMP_PCMD is not 128Byte aligned) or (DS:TMP_SRCPGE is not 4KByte aligned) )
(* Check concurrency of EPC by other Intel SGX instructions *)
IF (other instruct ions accessing EPC)
THEN
    IF ((EAX==07h) OR (E AX==08h))   (* ELDB/ELDU *)
    THEN        IF (<<VMX non-root operation>> AND  
    <<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)
THEN 
                              << translation of DS:RCX  produced by paging >>;
ELSE
#GP(0);
FI;
ELSE (* ELDBC/ELDUC *)
        IF (<<VMX non-root operation>> AND  
THEN 
VMCS.Exit_reason := SGX_CONFLICT;VMCS.Exit_qualification.code := EPC_PAGE_CONFLICT_ERROR;VMCS.Exit_qualification.error := SGX_EPC_PAGE_CONFLICT;VMCS.Guest-physical_address := 
ELSE
            RFLAGS.ZF := 1;
            RFLAGS.CF := 0; 
            RAX := SGX_EPC_PAGE_CONFLICT;            GOTO ERROR_EXIT;
FI;38-58 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
FI;
FI;
(* Check concurrency of EPC and VASLOT by other Intel SGX instructions *)
IF (Other instructions modifying VA slot) THEN
IF ((EAX==07h) OR (EAX==08h)) (* ELDB/ELDU *)
RFLAGS.ZF := 1;RFLAGS.CF := 0; RAX := SGX_EPC_PAGE_CONFLICT;GOTO ERROR_EXIT;
FI;
FI; 
(* Verify EPCM attributes of EPC page, VA, and SECS *)
IF ( (EPCM(DS:RDX & ~0FFFH).VALID = 0) or (EPCM(DS:RDX & ~0FFFH).PT ≠ PT_VA) )
(* Copy PCMD into scratch buffer *)
SCRATCH_PCMD[1023: 0] := DS:TMP_PCMD[1023:0];
(* Zero out TMP_HEADER*)
TMP_HEADER[sizeof(TMP_HEADER)-1: 0] := 0;
TMP_HEADER.SECINFO := SCRATCH_PCMD.SECINFO;
TMP_HEADER.RSVD := SCRATCH_PCMD.RSVD;TMP_HEADER.LINADDR := DS:RBX.LINADDR;
(* Verify various attributes of SECS parameter *)
IF ( (TMP_HEADER.SECINFO.FLAGS.PT = PT_REG) or  (TMP_HEADER.SECINFO.FL AGS.PT = PT_TCS) or 
 (TMP_HEADER.SECINFO.FLAGS.PT = PT_TRIM) or (TMP_HEADER.SECINFO.FLAGS.PT = PT_SS_FIRS T and CPUID.(EAX=12H, ECX=1):EAX[6] = 1) or
 (TMP_HEADER.SECINFO.FLAGS.PT = PT_SS_REST  and CPUID.(EAX=12H, ECX=1):EAX[6] = 1))
THEN 
IF ( DS:TMP_SECS is not 4KByte aligned) 
THEN #GP(0) FI;
IF (DS:TMP_SECS does not resolve within an EPC) 
THEN #PF(DS:TMP_SECS) FI;
IF ( Another instruction is currently modifying the SECS) THEN
        THEN #GP(0);
RFLAGS.ZF := 1;
        RFLAGS.CF := 0;         RAX := SGX_EPC_PAGE_CONFLICT;        GOTO ERROR_EXIT;
FI;
FI;TMP_HEADER.EID := DS:TMP_SECS.EID;
ELSEVol. 3D 38-59INTEL® SGX INSTRUCTION REFERENCES
(* TMP_HEADER.SECINFO.FLAGS.PT is PT_SECS or PT_VA which do not have a parent SECS, and hence no EID binding *)
TMP_HEADER.EID := 0;IF (DS:TMP_SECS ≠ 0)
FI;
(* Copy 4KBytes SRCPGE to secure location *)
DS:RCX[32767: 0] := DS:TMP_SRCPGE[32767: 0];TMP_VER := DS:RDX[63:0];
(* Decrypt and MAC page. AES_GCM_DEC has 2 outputs, {plain text, MAC} *)
(* Parameters for AES_GCM_DEC {Key, Counter, ..} *){DS:RCX, TMP_MAC} := AES_GCM_ DEC(CR_BASE_PK, TMP_VER << 32, TMP_HEADER, 128, DS:RCX, 4096);
IF ( (TMP_MAC ≠ DS:TMP_PCMD.MAC) )
THEN 
RFLAGS.ZF := 1;RAX := SGX_MAC_COMPARE_FAIL;GOTO ERROR_EXIT;
FI;
(* Clear VA Slot *)
DS:RDX := 0
(* Commit EPCM changes *)
EPCM(DS:RCX).PT := TMP_HEADER.SECINFO.FLAGS.PT;EPCM(DS:RCX).RWX := TMP_HEADER.SECINFO.FLAGS.RWX;EPCM(DS:RCX).PENDING := TMP_HEADER.SECINFO.FLAGS.PENDING;EPCM(DS:RCX).MODIFIED := TMP_ HEADER.SECINFO.FLAGS.MODIFIED;
EPCM(DS:RCX).PR := TMP_ HEADER.SECINFO.FLAGS.PR;
EPCM(DS:RCX).ENCLAVEADDRESS := TMP_HEADER.LINADDR;
IF ( ((EAX = 07H) or (EAX = 12 H)) and (TMP_HEADER.SECINFO.FLAGS. PT is NOT PT_SECS or PT_VA))
THEN 
EPCM(DS:RCX).BLOCKED := 1;
ELSE
EPCM(DS:RCX).BLOCKED := 0;
FI;
IF (TMP_HEADER.SECINFO.FLAGS.PT is PT_SECS)
   << store translation of DS:RCX produced by paging in SECS(DS:RCX).ENCLAVECONTEXT >>
FI;
EPCM(DS:RCX). VALID := 1;RAX := 0;
ERROR_EXIT:
RFLAGS.CF,PF,AF,OF,SF := 0;
Sets ZF if unsuccessful, otherwise cleared and RAX returns error code. Clears CF, PF, AF, OF, SF.38-60 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
If a memory operand is not properly aligned.If the instruction’s EPC resource is in use by others.
If the instruction fails to verify MAC.
If the version-array slot is in use.If the parameters fail consistency checks.
If a memory operand expected to be in  EPC does not resolve to an EPC page.
If one of the EPC memory operands has incorrect page type.
If the destination EPC page is already valid.
If the instruction’s EPC resource is in use by others.If the instruction fails to verify MAC.
If the version-array slot is in use.
If the parameters fail consistency checks.
If one of the EPC memory operands has incorrect page type.If the destination EPC page is already valid.Vol. 3D 38-61INTEL® SGX INSTRUCTION REFERENCES
EMODPR—Restrict the Permis sions of an EPC Page  
This leaf function restricts the access rights associated with an EPC page in an initialized enclave. THE RWX bits of 
the SECINFO parameter are treated as a permissions mask ; supplying a value that does not restrict the page 
permissions will have no effect. This instruction can only be executed when current privilege level is 0.
RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC 
page. The table below provides additi onal information on the memory para meter of the EMODPR leaf function.
EMODPR Memory Parameter Semantics
EMODPR Faulting Conditions
EAX = 0EH
ENCLS[EMODPR]IR V/V SGX2 This leaf function restricts the access rights associated with a 
EPC page in an initialized enclave.
IR EMODPR (In) Return Error Code (Out) Address of a S ECINFO (In) Address of the destination EPC page (In)
SECINFO EPCPAGE
Read access permitted by Non Enclave Read/Write access permitted by Enclave
The operands are not properly aligned. If unsupported security attributes are set.
The Enclave is not initialized. SECS is locked by another thread.
The EPC page is locked by another thread. RCX does not contai n an effective address of an EPC page in the running enclave.
The EPC page is not valid.
Table 38-31.  EMODPR Return Value in RAX
No Error EMODP R successful.
SGX_PAGE_NOT_MODIFIABLE The EPC page cannot be modifi ed because it is in the PENDING or MODIFIED state.
SGX_EPC_PAGE_CONFLICT Page is be ing written by EADD, EAUG, ECRE ATE, ELDU/B, EMODT, or EWB.
Table 38-32.  Base Concurre ncy Restrictions of EMODPR
EMODPR Target [DS:RCX] Shared #GP38-62 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EM ODPR Operational Flow
IF (DS:RBX is not 64Byte Aligned)
IF (DS:RCX does not re solve within an EPC) 
SCRATCH_SECINFO := DS:RBX;(* Check for misconfigured SECINFO flags*)
IF ( (SCRATCH_SECINFO reserved fields are not zero ) or
(SCRATCH_SECINFO.FLAGS.R is 0 and SCRATCH_SECINFO.FLAGS.W is not 0) )THEN #GP(0); FI;
(* Check concurrency with SGX1 or SG X2 instructions on the EPC page *)
IF (SGX1 or other SGX2 instructions accessing EPC page) 
IF (EPCM(DS:RCX).VALID is 0 )
IF (EPC page in use by another SGX2 instruction) 
THEN 
FI;
THEN

Operation
THEN 
FI;
THEN 
RFLAGS.ZF := 1;RAX := SGX_PAGE_NOT_MODIFIABLE;Table 38-33.  Additional Conc urrency Restrictions of EMODPR
EMODPR Target [DS:RCX] Exclusive SGX_EPC_PAGE
_CONFLICTConcurrent Concurrent
TMP_SECS Effective Address 32/64 Physical addr ess of SECS to which EPC operand belongs.
SCRATCH_SECINFO SECINFO 512 Scratch storage for holding the contents of DS:RBX.Vol. 3D 38-63INTEL® SGX INSTRUCTION REFERENCES
GOTO DONE;
FI;
IF (EPCM(DS:RCX).PT is not PT_REG)
TMP_SECS := GET_SECS_ADDRESSIF (TMP_SECS.ATTRIBUTES.INIT = 0)
  THEN #GP(0); FI;
(* Set the PR bit to indi cate that permission restriction is in progress *)
EPCM(DS:RCX).PR := 1;
(* Update EPCM permissions *)
EPCM(DS:RCX).R := EPCM(DS:RCX).R & SCRATCH_SECINFO.FLAGS.R;EPCM(DS:RCX).W := EPCM(DS:RCX).W & SCRATCH_SECINFO.FLAGS.W;EPCM(DS:RCX).X := EPCM(DS:RCX) .X & SCRATCH_SECINFO.FLAGS.X;
RAX := 0;
DONE:
Sets ZF if page is not modifiable or if other SGX2 instru ctions are executing concurrently, otherwise cleared. Clears 
CF, PF, AF, OF, SF.
If a memory operand is locked.
If a memory operand is not an EPC page.38-64 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EMODT—Change the Type of an EPC Page  
This leaf function modifies the type of an EPC page. The security attributes are configured to prevent access to the 
EPC page at its new type until a corresponding invocation  of the EACCEPT leaf confir ms the modification. This 
RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC page. 
The table below provides additional information on the memory parameter of the EMODT leaf function.
EMODT Memory Parameter Semantics
EMODT Faulting Conditions
EAX = 0FH
ENCLS[EMODT]IR V/V SGX2 This leaf function changes the type of an ex isting EPC page.
IR EMODT (In) Return Error Code (Out) Address of a SECINFO (In) Address of the destination EPC page (In)
Table 38-34.  EMODT Return Value in RAX
No Error EMODT successful.SGX_PAGE_NOT_MODIFIABLE The EPC page cannot be modifi ed because it is in the PENDING or MODIFIED state.
SGX_EPC_PAGE_CONFLICT Page is being written by EADD, EAUG, ECREATE, ELDU/B, EMODPR, or EWB.
Table 38-35.  Base Concurrency Restrictions of EMODT
EMODT Target [DS:RCX] Exclusive SGX_EPC_PAGE_
CONFLICTEPC_PAGE_CONFLICT_ERRORVol. 3D 38-65INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EMODT Operational Flow
IF ( (SCRATCH_SECINFO reserv ed fields are not zero ) or
!(SCRATCH_SECINFO.FLAGS.PT is PT_TCS or SCRATCH_SECINFO.FLAGS.PT is PT_TRIM) )THEN #GP(0); FI;
(* Check concurrency with SGX1 instructions on the EPC page *)
IF (other SGX1 instruct ions accessing EPC page) 
THEN
FI;
IF (EPCM(DS:RCX).VALID is 0)
THEN
RFLAGS.ZF := 1;RAX := SGX_EPC_PAGE_CONFLICT;GOTO DONE;Table 38-36.  Additional Conc urrency Restrictions of EMODT
EMODT Target [DS:RCX] Exclusive SGX_EPC_PAGE
TMP_SECS Effective Address 32/64 Physical address of SECS to which EPC operand belongs.SCRATCH_SECINFO SECINFO 512 Scratch storage for holding the contents of DS:RBX.38-66 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
FI;
IF (!(EPCM(DS:RCX).PT is PT_REG or
((EPCM(DS:RCX).PT is PT_TCS or PT _SS_FIRST or PT_SS_REST) and SCRATCH_SECINFO.FLAGS.PT is PT_TRIM)))
THEN 
RFLAGS.ZF := 1;RAX := SGX_PAGE_NOT_MODIFIABLE;GOTO DONE;
FI;
(* Update EPCM fields *)
EPCM(DS:RCX).PR := 0;EPCM(DS:RCX).MODIFIED := 1;EPCM(DS:RCX).R := 0;EPCM(DS:RCX).W := 0;EPCM(DS:RCX).X := 0;EPCM(DS:RCX).PT := SCRATCH_SECINFO.FLAGS.PT;
RAX := 0;
DONE:
If a memory operand is not an EPC page.Vol. 3D 38-67INTEL® SGX INSTRUCTION REFERENCES
EPA—Add Version Array 
This leaf function creates an empty version array in the EPC page whose logical address is  given by DS:RCX, and 
sets up EPCM attributes for that page. At the time of exec ution of this instruction, the register RBX must be set to 
PT_VA.
The table below provides additional information on the memory parameter of EPA leaf function.
EPA Memory Parameter Semantics
Operation
IF (RBX ≠ PT_VA or DS:RCX is not 4KByte Aligned)
(* Check concurrency with other Intel SGX instructions *)
IF (Other Intel SGX instructions accessing the page) 
THEN 
IF (<<VMX non-root operation>> AND <<E NABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)Opcode/
EAX = 0AH
ENCLS[EPA]IR V/V SGX1 This leaf function a dds a Version Array to the EPC.
IR EPA (In) PT_VA (In, Constant) Effective address of the EPC page (In)
EPCPAGE
Write access permitted by Enclave
Table 38-37.  Base Concur rency Restrictions of EPA
EPA VA [DS:RCX] Exclusive #GP EP C_PAGE_CONFLICT_EXCEPTION
Table 38-38.  Additional Conc urrency Restrictions of EPA
EPA VA [DS:RCX] Concurrent L Concurrent Concurrent38-68 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
THEN
#GP(0);
FI;
FI;
(* Check EPC page must be empty *)
IF (EPCM(DS:RCX). VALID ≠ 0)
(* Clears EPC page *)
EPCM(DS:RCX).PT := PT_VA;
EPCM(DS:RCX).ENCLAVEADDRESS := 0;EPCM(DS:RCX).BLOCKED := 0;EPCM(DS:RCX).PENDING := 0;EPCM(DS:RCX).MODIFIED := 0;EPCM(DS:RCX).PR := 0;EPCM(DS:RCX).RWX := 0;EPCM(DS:RCX).VALID := 1;
None

THEN
#GP(0);
FI;
FI;
None
If a memory operand is not properly aligned.If another Intel SGX instruction is accessing the EPC page.
If RBX is not set to PT_VA.
If another Intel SGX instruction is accessing the EPC page.
If the EPC page is valid.Vol. 3D 38-69INTEL® SGX INSTRUCTION REFERENCES
ERDINFO—Read Type and Status Information About an EPC Page 
This instruction reads type and status information about an EPC page and returns it in a RDINFO structure. The 
STATUS field of the structure describes the status of the page and determines the validi ty of the remaining fields. 
The FLAGS field returns the EPCM perm issions of the page; the page type; and the BLOCKED, PENDING, MODI-
FIED, and PR status of the page. For enclave pages, the ENCLAVECONTEXT field of the structure returns the value 
of SECS.ENCLAVECONTEXT. For non-enclave pa ges (e.g., VA) ENCLAVECONTEXT returns 0.
For invalid or non-EPC pages, the instruction returns an in formation code indicating the page's status, in addition 
to populating the STATUS field.
ERDINFO returns an error code if the destination EPC page  is being modified by a co ncurrent SGX instruction. 
RBX contains the effective address of a RDINFO structure while RCX contains the effective address of an EPC page. 
The table below provides additional information on the memory parameter of ERDINFO leaf function.
ERDINFO Memory Parameter Semantics
ERDINFO Faulting Conditions
EAX = 10H
ENCLS[ERDINFO]IR V/V EAX[6] This leaf function returns type and status information about an 
EPC page.
IR ERDINFO (In)Return error code 
(Out)Address of a RDIN FO structure (In)Address of the destination EPC page 
(In)
RDINFO EPCPAGE
Read/Write access permitted by Non Enclave Read access permitted by Enclave
A memory operand effective address is outside the DS 
segment limit (32b mode).A memory operand is not properly aligned.
DS segment is unusable (32b mode). A page fault occurs in  accessing memory operands.
A memory address is in a non-canonical form (64b mode).
Table 38-39.  ERDINFO Return Value in RAX
 Error Code Value Description
No Error 0 ERDINFO successful.SGX_EPC_PAGE_CONFLICT Failure due to concur rent operation of another SGX instruction.
SGX_PG_INVLD Target page is not a valid EPC page.SGX_PG_NONEPC Page is not an EPC page.38-70 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in ERDINFO Operational Flow
(* check alignment of RDINFO structure (RBX) *)
IF (DS:RBX is not 32Byte Aligned) THEN    #GP(0); FI;
(* check alignment of the EPCPAGE (RCX) *)
IF (DS:RCX is not 4KByte Aligned) THEN    #GP(0); FI;
(* check that EPCPAGE (DS:RCX) is  the address of an EPC page *)
IF (DS:RCX does not resolve within EPC) THEN    RFLAGS.CF := 1;    RFLAGS.ZF := 0;    RAX := SGX_PG_NONEPC;    goto DONE;FI;
IF (EPC page is being modified) THEN    RFLAGS.ZF = 1;    RFLAGS.CF = 0;    RAX = SGX_EPC_PAGE_CONFLICT;    goto DONE;FI;
(* check page validity *)
IF (EPCM(DS:RCX).VALID = 0) THEN    RFLAGS.CF = 1;Table 38-40.  Base Concurrency Restrictions of ERDINFO
ERDINFO Target [DS:RCX] Shared SGX_EPC_PAGE_
CONFLICT
Table 38-41.  Additional Concurrency Restrictions of ERDINFO
ERDINFO Target [DS:RCX] Concurrent Concurrent Concurrent
TMP_SECS Physical Address 64 Physical address of the SECS of the page being modified.TMP_RDINFO Linear Address 64 Address of the RDINFO structure.Vol. 3D 38-71INTEL® SGX INSTRUCTION REFERENCES
    RFLAGS.ZF = 0;
    RAX = SGX_PG_INVLD;    goto DONE;FI;
(* clear the fields of the RDINFO structure *)
TMP_RDINFO := DS:RBX;TMP_RDINFO.STATUS := 0;TMP_RDINFO.FLAGS := 0;TMP_RDINFO.ENCLAVECONTEXT := 0;
(* store page info in  RDINFO structure *)
TMP_RDINFO.FLAGS.RWX := EPCM(DS:RCX).RWX;TMP_RDINFO.FLAGS.PENDING := EPCM(DS:RCX).PENDING;TMP_RDINFO.FLAGS.M ODIFIED := EPCM(D S:RCX).MODIFIED;
TMP_RDINFO.FLAGS.PR := EPCM(DS:RCX).PR;TMP_RDINFO.FLAGS.PAGE_TYPE := EPCM(DS:RCX).PAGE_TYPE;
TMP_RDINFO.FLAGS.BLOCKED := EPCM(DS:RCX).BLOCKED;
(* read SECS.ENCLAVECONTEXT for enclave child pages *)
IF ((EPCM(DS:RCX).PAGE_TYPE = PT_REG) or    (EPCM(DS:RCX).PAGE_TYPE = PT_TCS) or    (EPCM(DS:RCX).PAGE_TYPE = PT_TRIM) or
(EPCM(DS:RCX).PAGE_TYPE = PT_SS_FIRST) or
(EPCM(DS:RCX).PAGE_TYPE = PT_SS_REST)
   ) THEN    TMP_SECS := Addres s of SECS for (DS:RCX);
    TMP_RDINFO.ENCLAVECONTEXT := SECS(TMP_SECS).ENCLAVECONTEXT;
FI;
(* populate enclave information for SECS pages *)
IF (EPCM(DS:RCX).PAGE_TYPE = PT_SECS) THEN    IF ((VMX non-root mode) and        (ENABLE_EPC_VIRTUALIZA TION_EXTENSIONS Execution Control = 1)
       ) THEN        TMP_RDINFO .STATUS.CHILDPRESENT := 
                            ((SECS(DS:RCX).CHLDCNT ≠ 0) or
                              SECS(DS:RCX).VIRTCHILDCNT ≠ 0);
    ELSE        TMP_RDINFO.STATUS.CHIL DPRESENT := (SECS(DS:RCX).CHLDCNT ≠ 0);
        TMP_RDINFO.S TATUS.VIRTCHILDPRESENT := 
                            (SECS(DS:RCX).VIRTCHILDCNT ≠ 0);
        TMP_RDINFO .ENCLAVECONTEXT := SECS(DS_RCX).ENCLAVECONTEXT;
    FI;FI;
RAX := 0;
RFLAGS.ZF := 0;RFLAGS.CF := 0;
DONE:
(* clear flags *)RFLAGS.PF := 0;RFLAGS.AF := 0;38-72 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
RFLAGS.OF := 0;
RFLAGS.SF := ?  0;
ZF is set if ERDINFO fails due to concurrent operation with another SGX instruction; otherwise cleared.CF is set if page is not a valid EPC page or not an EPC page; otherwise cleared.PF, AF, OF, and SF are cleared.
#PF(error code) If a page fault occurs in accessing memory operands.Vol. 3D 38-73INTEL® SGX INSTRUCTION REFERENCES
EREMOVE—Remove a page from the EPC 
This leaf function causes an EPC page to be un-associated  with its SECS and be marked as unused. This instruction 
leaf can only be executed when the current privilege level is 0.
The instruction fails if the operand is not properly aligned or  does not refer to an EPC page or the page is in use by 
another thread, or other threads are running in the enclave to which the page belongs. In addition the instruction 
fails if the operand refers to an SECS with associations.
EREMOVE Memory Parameter Semantics
EREMOVE Faulting Conditions
EAX = 03H
ENCLS[EREMOVE]IR V/V SGX1 This leaf function removes a page from the EPC.
IR EREMOVE (In) Return error code (Out) Effective address of the EPC page (In)
EPCPAGE
The memory operand is not properly aligned. The memory operand does not resolve in an EPC page.
Refers to an invalid SECS. Ref ers to an EPC page that is  locked by another thread.
Another Intel SGX instruction is accessing the EPC page. RCX  does not contain an effective address of an EPC page.
the EPC page refers to an SECS with associations.
Table 38-42.  EREMOVE Return Value in RAX
No Error EREMOVE successful.SGX_CHILD_PRESENT If the SECS still have enclave pages loaded into EPC.SGX_ENCLAVE_ACT If there are still logical processors executing inside the enclave.38-74 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EREMOVE Operational Flow
IF (DS:RCX does not re solve to an EPC page)
TMP_SECS := Get_SECS_ADDRESS();(* Check the EPC page for concurrency *)
IF (EPC page being referenced by another Intel SGX instruction) 
THEN

Operation
THEN 
THEN
#GP(0);
FI;
FI;
(* if DS:RCX is already unused, nothing to do*)
IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX ).PT = PT_TRIM AND EPCM(DS:RCX).MODIFIED = 0))
THEN GOTO DONE; 
FI;Table 38-43.  Base Concurrency Restrictions of EREMOVE
EREMOVE Target [DS:RCX] Exclusiv e #GP EPC_PAGE_CONFLICT_EXCEPTION
Table 38-44.  Additional Concu rrency Restrictions of EREMOVE
EREMOVE Target [DS:RCX] Concurrent Concurrent Concurrent
TMP_SECS Effective Address 32/64 Effective address of the SECS destination page.Vol. 3D 38-75INTEL® SGX INSTRUCTION REFERENCES
IF ( (EPCM(DS:RCX).PT = PT_VA) OR
((EPCM(DS:RCX).PT = PT_TRIM) AND (EPCM(DS:RCX).MODIFIED = 0)) )
THEN 
EPCM(DS:RCX).VALID := 0;GOTO DONE; 
FI;
IF (EPCM(DS:RCX).PT = PT_SECS) 
THEN 
IF (DS:RCX has an EPC page associated with it) 
THEN 
RFLAGS.ZF := 1;RAX := SGX_CHILD_PRESENT;GOTO ERROR_EXIT;
FI;(* treat SECS as having  a child page when VIRT CHILDCNT is non-zero *)
IF (<<in VMX non-root operation>> AND 
             <<ENABLE_E PC_VIRTUALIZATION_ EXTENSIONS>> AND 
             (SECS(DS:RCX).VIRTCHILDCNT ≠ 0))
THEN
   RAX := SGX_CHILD_PRESENT
GOTO ERROR_EXIT
FI;EPCM(DS:RCX).VALID := 0;GOTO DONE; 
FI;
IF (Other threads active using SECS) 
THEN 
RFLAGS.ZF := 1;RAX := SGX_ENCLAVE_ACT;GOTO ERROR_EXIT;
FI;
IF ( (EPCM(DS:RCX).PT is PT_REG) or (EPCM(DS:RCX).PT is PT_TCS) or  (EPCM(DS:RCX).PT is PT_TRIM) or
(EPCM(DS:RCX).PT is PT_SS_FIRST) or  (EPCM(DS:RCX).PT is PT_SS_REST))
THEN
EPCM(DS:RCX).VALID := 0;GOTO DONE;
FI;
DONE:
Sets ZF if unsuccessful, otherwise cleared and RAX returns error code. Clears CF, PF, AF, OF, SF.38-76 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
If a memory operand is not properly aligned.If another Intel SGX instruction is accessing the page.
If the memory operand is not an EPC page.
#GP(0) If the memory operand is non-canonical form.
If another Intel SGX instruction is accessing the page.
If the memory operand is not an EPC page.Vol. 3D 38-77INTEL® SGX INSTRUCTION REFERENCES
ETRACK—Activates EBLOCK Checks 
This leaf function provides the mechanism for hardware to track that software has completed the required TLB 
address clears successfully. The instruction can only be executed when the current privilege level is 0.
The content of RCX is an effective address of an EPC page.The table below provides additional information on  the memory parameter of ETRACK leaf function.
ETRACK Memory Parameter Semantics
EAX = 0CH
ENCLS[ETRACK]IR V/V SGX1 This leaf function  activates EBLOCK checks.
IR ETRACK (In) Return error code (Out) Pointer to the SECS of the EPC page (In)
EPCPAGE
Table 38-45.  ETRACK Return Value in RAX
No Error ETRACK successful.SGX_PREV_TRK_INCMPL All processors did not complete the previous shoot-down sequence.
Table 38-46.  Base Concurre ncy Restrictions of ETRACK
ETRACK SECS [DS:RCX] Shared #GP
Table 38-47.  Additional Conc urrency Restrictions of ETRACK
ETRACK SECS [DS:RCX] Concurrent Concurrent Exclusive SGX_EPC_PAGE
_CONFLICT38-78 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
IF (Other Intel SGX instructions usin g tracking facility on this SECS) 
THEN 
THEN
VMCS.Exit_reason := SGX_CONFLICT;VMCS.Exit_qualification.code := TRACKING_RESOURCE_CONFLICT;VMCS.Exit_qualification.error := 0;VMCS.Guest-physical_address := SECS(TMP_SECS).ENCLAVECONTEXT;VMCS.Guest-linear_address := 0;
#GP(0);
FI;
FI;
IF (EPCM(DS:RCX).PT ≠ PT_SECS) 
(* All processors must have comple ted the previous tracking cycle*)
IF ( (DS:RCX).TRACKING ≠ 0) ) 
THEN 
THEN
VMCS.Exit_reason := SGX_CONFLICT;VMCS.Exit_qualification.code := TRACKING_REFERENCE_CONFLICT;VMCS.Exit_qualification.error := 0;VMCS.Guest-physical_address := SECS(TMP_SECS).ENCLAVECONTEXT;VMCS.Guest-linear_address := 0;
        Deliver VMEXIT;
FI;
RAX := SGX_PREV_TRK_INCMPL;GOTO DONE;
ELSE
FI;
DONE:
Sets ZF if SECS is in use or invalid, otherwise cleared. Clears CF, PF, AF, OF, SF.Vol. 3D 38-79INTEL® SGX INSTRUCTION REFERENCES
If a memory operand is not properly aligned.If another thread is concurrently using the tracking facility on this SECS.
If a memory operand is not an EPC page.38-80 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
ETRACKC—Activates EBLOCK Checks 
The ETRACKC instruction is thread safe variant of ETRACK  leaf and can be executed concurrently with other CPU 
threads operating on the same SECS. 
The content of RCX is an effective address of an EPC page.The table below provides additional  information on the memory parameter of ETRACK leaf function.
ETRACKC Memory Parameter Semantics
EAX = 11H
ENCLS[ETRACKC]IR V/V EAX[6] This leaf function  activates EBLOCK checks.
IRETRACK 
(In)Return error code (Out)Address of the destination EPC page 
(In, EA)Address of the SECS page (In, EA)
EPCPAGE
Read/Write access permitted by Enclave
Table 38-48.  ETRACKC Return Value in RAX
No Error 0 ETRACKC successful.SGX_EPC_PAGE_CONFLICT 7 Failure due to concurrent operation of another SGX instruction.SGX_PG_INVLD 6 Target page is not a VALID EPC page.SGX_PREV_TRK_INCMPL 17 All proc essors did not complete the previous tracking sequence.
SGX_TRACK_NOT_REQUIRED 27 Target page type does not require tracking.
Table 38-49.  Base Concurrency Restrictions of ETRACKC
ETRACKC Target [DS:RCX] Shared SGX_EPC_PAGE_
CONFLICT
SECS implicit ConcurrentVol. 3D 38-81INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in ETRACKC Operational Flow
(* check alignment of EPCPAGE (RCX) *)
IF (DS:RCX is not 4KByte Aligned) THEN#GP(0); FI;
(* check that EPCPAGE (DS:RCX) is the address of an EPC page *)
IF (DS:RCX does not reso lve within an EPC) THEN
#PF(DS:RCX, PFEC.SGX); FI;
IF (EPC page is being modified) THEN    RFLAGS.ZF := 1;    RFLAGS.CF := 0;    RAX := SGX_ EPC_PAGE_CONFLICT;
    goto DONE_POST_LOCK_RELEASE;FI;
(* check to make sure the page is valid *)

CONFLICT
Operation
IF (EPCM(DS:RCX).VALID = 0) THEN    RFLAGS.ZF := 1;    RFLAGS.CF := 0;    RAX := SGX_PG_INVLD;    GOTO DONE;FI;
(* find out the target SECS page *)
IF (EPCM(DS:RCX).PT is PT_REG or PT_TCS or  PT_TRIM or PT_SS_FIRST or PT_SS_REST) THEN 
    TMP_SECS := Obtain SECS through EPCM(DS:RCX).ENCLAVESECS;ELSE IF (EPCM(DS:RCX). PT is PT_SECS) THEN
    TMP_SECS := Obtain  SECS through (DS:RCX);
ELSE     RFLAGS.ZF := 0;    RFLAGS.CF := 1;    RAX := SGX_TRACK_NOT_REQUIRED;    GOTO DONE;FI;Table 38-50.  Additional Concurrency Restrictions of ETRACKC
SECS implicit Concurrent Concurrent Exclusive SGX_EPC_PAGE
_CONFLICT
TMP_SECS Physical Address 64 Physical address of the SECS of the page being modified.38-82 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF (Other Intel SGX instructions using tracking facility on this SECS) THEN
IF ((VMX non-root mode) and(ENABLE_EPC_VIRTUALIZATION_EXTENSI ONS Execution Control = 1)) THEN
        VMCS.Exit_ reason := SGX_CONFLICT;
        VMCS.Exit_qualification. code := TRACKING_RESOURCE_CONFLICT;
        VMCS.Exit_ qualification.error := 0;
        VMCS.Gue st-physical_address := 
SECS(TMP_SECS).ENCLAVECONTEXT;
        VMCS.Gue st-linear_address := 0;
        Deliver VMEXIT;    FI;
    RFLAGS.ZF := 1;
    RFLAGS.CF := 0;    RAX := SGX_EPC_PAGE_CONFLICT;    GOTO DONE;FI;(* All processors must have comple ted the previous tracking cycle*) 
IF ( (TMP_SECS).TRACKING ≠ 0) )
THEN
        VMCS.Exit_qualification.code := TRACKING_REFERENCE_CONFLICT;        VMCS.Exit_ qualification.error := 0;
        VMCS.Guest -physical_address :=  
    RFLAGS.CF := 0;    RAX := SGX_PREV_TRK_INCMPL;    GOTO DONE;FI; 
RFLAGS.CF := 0;RAX := 0;
DONE:
(* clear flags *)RFLAGS.PF,AF,OF,SF := 0;
ZF is set if ETRACKC fails due to concurrent operations wi th another SGX instructions or target page is an invalid 
EPC page or tracking is not completed on SECS page; otherwise cleared.
CF is set if target page is not of a type that requires tracking; otherwise cleared.PF, AF, OF, and SF are cleared.Vol. 3D 38-83INTEL® SGX INSTRUCTION REFERENCES
#GP(0) If the memory operand violates access-control policies of DS segment.
If DS segment is unusable.If the memory operand is not properly aligned.
#PF(error code) If the memory operand expected to be in EPC does not resolve to an EPC page.
If a page fault occurs in access memory operand.
If a page fault occurs in access memory operand.38-84 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EWB—Invalidate an EPC Page and Write out to Main Memory 
This leaf function copies a page from the EPC to regular main memory. As part of the copying process, the page is 
cryptographically protected. This instruction can on ly be executed when current privilege level is 0.
The table below provides addition al information on the memory parameter of EPA leaf function.
EWB Memory Parameter Semantics
 EAX = 0BH
ENCLS[EWB]IR V/V SGX1 This leaf function invalidates an EPC page and writes it out to 
IR EWB (In) Error code (Out) Address of an PAGEINFO (In) Ad dress of the EPC page (In) Address of a VA slot (In)
PAGEINFO PAGEINFO.SRCPGE PAGEINFO.PCMD EPCPAGE VASLOT
Non-EPC R/W access Non-EPC R/W access Non-EPC R/W access EPC R/W access EPC R/W access 
Table 38-51.  EWB Return Value in RAX
No Error EWB successful.SGX_PAGE_NOT_BLOCKED If page is not marked as blocked.SGX_NOT_TRACKED If EWB is raci ng with ETRACK instruction.
SGX_VA_SLOT_OCCUPIED Version array slot contained valid entry.SGX_CHILD_PRESENT Child page present wh ile attempting to page out enclave.
Table 38-52.  Base Concurrency Restrictions of EWB
Table 38-53.  Additional Concurrency Restrictions of EWB
VA [DS:RDX] Concurrent Concurrent ExclusiveVol. 3D 38-85INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EWB Operational Flow
IF (DS:RDX is not 8Byte Aligned)
(* EPCPAGE and VASLOT should not resolve to the same EPC page*)
IF (DS:RCX and DS:RDX resolve to the same EPC page)
(* Note PAGEINFO.PCMD is overlaid on top of PAGEINFO.SECINFO *)TMP_PCMD := DS:RBX.PCMD;
If (DS:RBX.LINADDR ≠ 0) OR (DS:RBX.SECS ≠ 0) 
IF ( (DS:TMP_PCMD is not 128By te Aligned) or (DS:TMP_SRCPGE  is not 4KByte Aligned) )
(* Check for concurrent Intel SGX instruction access to the page *)
IF (Other Intel SGX instruction is accessing page) 
THEN 
THEN
VMCS.Exit_reason := SGX_CONFLICT;VMCS.Exit_qualification.code := EPC_PAGE_CONFLICT_EXCEPTION;VMCS.Exit_qualification.error := 0;VMCS.Guest-physical_address := << translat ion of DS:RCX produced by paging >>;Name Type Size (Bytes) Description
TMP_SRCPGE Memory page 4096TMP_PCMD PCMD 128
TMP_SECS SECS 4096
TMP_BPEPOCH UINT64 8TMP_BPREFCOUNT UINT64 8
TMP_HEADER MAC Header 128
TMP_PCMD_ENCLAVEID UINT64 8TMP_VER UINT64 8TMP_PK UINT128 1638-86 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
     Deliver VMEXIT; ELSE
#GP(0);
FI;
FI;
(*Check if the VA Page is being removed or changed*)
IF (VA Page is being modified)
(* Verify that EPCPAGE and VASLOT page are valid EPC pages and DS:RDX is VA *)
IF (EPCM(DS:RCX).VALID = 0) 
IF ( (EPCM(DS:RDX & ~0FFFH).VALID = 0) or (EPCM(DS:RDX & ~FFFH).PT is not PT_VA) )
(* Perform page-type-specific exception checks *)
IF ( (EPCM(DS:RCX).PT is PT_REG) or (EPCM(DS:RCX).PT is PT_TCS ) or (EPCM(DS:RCX).PT is PT_TRIM ) or
(EPCM(DS:RCX).PT is PT_SS_FIRST ) or  (EPCM(DS:RCX).PT is PT_SS_REST))
THEN
TMP_SECS = Obtain SECS through EPCM(DS:RCX)
(* Check that EBLOCK has occurred correctly *)IF (EBLOCK is not correct)
FI;
RAX := 0;
TMP_HEADER[ sizeof(TMP_HEADER) - 1 : 0] := 0; 
(* Perform page-type-specific checks *)
IF ( (EPCM(DS:RCX).PT is PT_REG) or (EPCM(DS:RCX).PT is PT_TCS ) or (EPCM(DS:RCX).PT is PT_TRIM )or
THEN
(* check to see if the page is evictable *)IF (EPCM(DS:RCX).BLOCKED = 0) 
THEN
RAX := SGX_PAGE NOT_BLOCKED;RFLAGS.ZF := 1;GOTO ERROR_EXIT;
FI;(* Check if tracking done correctly *)IF (Tracking not correct)
THEN
RAX := SGX_NOT_TRACKED;RFLAGS.ZF := 1;GOTO ERROR_EXIT;
FI;
(* Obtain EID to establish cryptographic binding between the paged-out page and the enclave *)Vol. 3D 38-87INTEL® SGX INSTRUCTION REFERENCES
TMP_HEADER.EID := TMP_SECS.EID;
(* Obtain EID as an encl ave handle for software *)
TMP_PCMD_ENCLAVEID := TMP_SECS.EID;
ELSE IF (EPCM(DS:R CX).PT is PT_SECS)
(*check that there are no child pages inside the enclave *)IF (DS:RCX has an EPC page associated with it)
THEN
RAX := SGX_CHILD_PRESENT;RFLAGS.ZF := 1;GOTO ERROR_EXIT;
FI:(* treat SECS as having  a child page when VIRT CHILDCNT is non-zero *)
        <<ENABLE_EPC_VIR TUALIZATION_EXTENSIONS>> AND 
        (SECS(DS:RCX).VIRTCHILDCNT ≠ 0))
THEN
   RAX := SGX_CHILD_PRESENT;
GOTO ERROR_EXIT;
FI;TMP_HEADER.EID := 0; (* Obtain EID as an encl ave handle for software *)
TMP_PCMD_ENCLAVEID := (DS:RCX).EID;
ELSE IF (EPCM(DS:R CX).PT is PT_VA)
TMP_HEADER.EID := 0; // Zero is not a special value(* No enclave handle for VA pages*)TMP_PCMD_ENCLAVEID := 0;
FI;
TMP_HEADER.LINADDR := EP CM(DS:RCX).ENCLAVEADDRESS;

THEN
THEN
FI;
TMP_HEADER.SECINFO.FLAGS.PT := EPCM(DS:RCX).PT;TMP_HEADER.SECINFO.FLAGS.RWX := EPCM(DS:RCX).RWX;TMP_HEADER.SECINFO.FLAGS.PENDI NG := EPCM(DS:RCX).PENDING;
TMP_HEADER.SECINFO.FLAGS.MODIF IED := EPCM(DS:RCX).MODIFIED;
TMP_HEADER.SECINFO.FLAGS.PR := EPCM(DS:RCX).PR;
(* Encrypt the page, DS:RCX could be encrypted in pl ace. AES-GCM produces 2 values, {ciphertext, MAC}. *)
(* AES-GCM input parameters: ke y, GCM Counter, MAC_HDR, MAC_HDR_SIZE, SRC, SRC_SIZE)*)
{DS:TMP_SRCPGE, DS:TMP_PCMD.MAC} := AES_ GCM_ENC(CR_BASE_PK), (TMP_VER << 32), 
TMP_HEADER, 128, DS:RCX, 4096);
(* Write the output *)
Zero out DS:TMP_PCMD.SECINFO DS:TMP_PCMD.SECINFO.FLAGS.PT := EPCM(DS:RCX).PT;DS:TMP_PCMD.SECINFO.FLAGS.RWX := EPCM(DS:RCX).RWX;DS:TMP_PCMD.SECINFO.FLAGS.PEND ING := EPCM(DS:RCX).PENDING;
DS:TMP_PCMD.SECINFO.FLAGS.MODIFIED := EPCM(DS:RCX).MODIFIED;DS:TMP_PCMD.SECINFO.FLAGS. PR := EPCM(DS:RCX).PR;
DS:TMP_PCMD.RESERVED := 0;DS:TMP_PCMD.ENCLAVEID := TMP_PCMD_ENCLAVEID;DS:RBX.LINADDR := EPCM(DS:RCX).ENCLAVEADDRESS;
(*Check if version array slot was empty *)38-88 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF ([DS.RDX]) 
THEN
RAX := SGX_VA_SLOT_OCCUPIEDRFLAGS.CF := 1;
FI;
(* Write version to Version Array slot *)
[DS.RDX] := TMP_VER; 
(* Free up EPCM Entry *)
EPCM.(DS:RCX).VALID := 0;ERROR_EXIT:
ZF is set if page is not blocked, not tracke d, or a child is present. Otherwise cleared. 
CF is set if VA slot is previously occupied, Otherwise cleared.
If a memory operand is not properly aligned.If the EPC page and VASLOT resolve to the same EPC page.
If another Intel SGX instruction is concurrently accessing either the target EPC, VA, or SECS 
pages.
If the tracking resource is in use.
If the EPC page or the version array page is invalid.
If the EPC page and VASLOT resolve to the same EPC page.If another Intel SGX instruction is concurrently accessing either the target EPC, VA, or SECS 
pages.
If the tracking resource is in use.If the EPC page or the version array page in invalid.
If one of the EPC memory operands has incorrect page type.Vol. 3D 38-89INTEL® SGX INSTRUCTION REFERENCES
38.4 INTEL® SGX USER LE AF FUNCTION REFERENCE
Leaf functions available with the ENCLU instruction mnemonic  are covered in this section. In general, each instruc-
tion leaf requires EAX to specify the leaf function index and/or additional registers specifying leaf-specific input 
parameters. An instruction operand enco ding table provides details of the implicitly-encoded register usage and 
associated input/output semantics.
In many cases, an input parameter specifies an effectiv e address associated with a memory object inside or 
outside the EPC, the memory addressing semantics of th ese memory objects are also summarized in a separate 
table.38-90 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EACCEPT—Accept Changes to an EPC Page  
This leaf function accepts changes to a page in the runnin g enclave by verifying that th e security attributes speci-
fied in the SECINFO match the security attributes of th e page in the EPCM. This instruction leaf can only be 
executed when inside the enclave. 
The table below provides additional information on the memory parameter of the EACCEPT leaf function.
EACCEPT Memory Pa rameter Semantics
EACCEPT Faulting Conditions
The error codes are:Opcode/
EAX = 05H
ENCLU[EACCEPT]IR V/V SGX2 This leaf function accepts ch anges made by system software to 
an EPC page in the running enclave.
IR EACCEPT (In) Return Error Code (Out) Address of a SECINFO (In) Address of the destination EPC page (In)
SECINFO EPCPAGE (Destination)
Read access permitted by Non Enclave Read access permitted by Enclave
The operands are not properly aligned. RBX does not contain an effective address in an EPC page in the running enclave.
The EPC page is locked by another thread. RCX does not contain an effective address of an EPC page in the running enclave.
The EPC page is not valid. Page type is PT_REG and MODIFIED bit is 0.SECINFO contains an invalid request. Pa ge type is PT_TCS or PT_TRIM and PE NDING bit is 0 and MODIFIED bit is 1.
If security attributes of  the SECINFO page make 
the page inaccessible.
Table 38-54.  EACCEPT Return Value in RAX
No Error EACCEPT successful.SGX_PAGE_ATTRIBUTES_MISMATCH The attr ibutes of the target EPC page do not match the expected values.
SGX_NOT_TRACKED The OS did not comple te an ETRACK on the target page.Vol. 3D 38-91INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EACCEPT Operational Flow
IF (DS:RBX is not within CR_ELRANGE) 
IF (DS:RBX does not resolve within an EPC) 
IF ( (EPCM(DS:RBX &~FFFH).VALID = 0) or (EPCM(DS:R BX &~FFFH).R = 0) or (EPCM(DS:RBX &~FFFH).PENDING ≠ 0) or 
(EPCM(DS:RBX &~FFFH).MODIFIED ≠ 0) or (EPCM(DS:RBX &~FFFH).BLOCKED ≠ 0) or 
(EPCM(DS:RBX &~FFFH).PT ≠ PT_REG) or (EPCM(DS:RBX &~FFFH).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RBX &~FF FH).ENCLAVEADDRESS ≠ (DS:RBX & FFFH)) )
(* Copy 64 bytes of contents *)
SCRATCH_SECINFO := DS:RBX; 
IF (SCRATCH_SECINFO reserved fields are not zero )
THEN #GP(0); FI;Table 38-55.  Base Concurrency Restrictions of EACCEPT
Table 38-56.  Additional Concurrency Restrictions of EACCEPT
TMP_SECS Effective Address 32/64 Physical address of SECS to which EPC operands belongs.
SCRATCH_SECINFO SECINFO 512 Scratch storage for holding the contents of DS:RBX.38-92 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF (DS:RCX is not within CR_ELRANGE) 
(* Check that the combinatio n of requested PT, PENDING, and MODIFIED is legal *)
IF (CPUID.(EAX=12H, ECX=1):EAX[6] = 0 )
THEN
IF (NOT (((SCRAT CH_SECINFO.FLAGS.PT is PT_REG) and
 ((SCRATCH_SECINFO.FLAGS.PR is 1) or  (SCRATCH_SECINFO.FLAGS.PENDING is 1)) and (SCRATCH_SECINFO.FLA GS.MODIFIED is 0)) or
 ((SCRATCH_SECINFO.FLAGS.PT is PT_TCS or PT_TRIM) and (SCRATCH_SECINFO.FLAGS.PR is 0) and (SCRATCH_SECINFO.FLAGS.PENDING is 0) and  (SCRATCH_SECINFO.FLA GS.MODIFIED is 1) )))
ELSE
IF (NOT (((SCRAT CH_SECINFO.FLAGS.PT is PT_REG) AND
 ((SCRATCH_SECINFO.FLAGS.PR is 1) OR (SCRATCH_SECINFO.FLAGS.PENDING is 1)) AND (SCRATCH_SECINFO.FLA GS.MODIFIED is 0)) OR
 ((SCRATCH_SECINFO.FLAGS.PT is PT_TCS OR PT_TRIM) AND
 (SCRATCH_SECINFO.FLAGS.PENDING is 0) AND (SCRATCH_SECINFO.FLAGS .MODIFIED is 1) AND
 (SCRATCH_SECINFO.FLAGS.PR is 0)) OR ((SCRATCH_SECINFO.FLAGS.PT is PT_SS_FIRST or PT_SS_REST) AND
 (SCRATCH_SECINFO.FLAGS.PENDING is 1) AND (SCRATCH_SECINFO.FLAGS .MODIFIED is 0) AND
 (SCRATCH_SECINFO .FLAGS.PR is 0))))
FI;
(* Check security attributes of the destination EPC page *)
IF ( (EPCM(DS:RCX).VALID is 0) or (EPCM(DS:RCX).BLOCKED is not 0) or
 ((EPCM(DS:RCX).PT is not PT_REG) and (EPCM(DS:RCX).PT is not PT_T CS) and (EPCM(DS:RCX).PT is not PT_TRIM)
 and (EPCM(DS:RCX).PT is not PT_SS_FIRST) and (EPCM(DS:RCX).PT is  not PT_SS_REST)) or
 (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS))
THEN #PF((DS:RCX); FI;
(* Check the destination EPC page for concurrency *)
IF ( EPC page in use ) 
(* Re-Check security attributes of the destination EPC page *)
IF ( (EPCM(DS:RCX).VALID is 0) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) )
(* Verify that accept request ma tches current EPC page settings *)
IF ( (EPCM(DS:RCX ).ENCLAVEADDRESS ≠ DS:RCX) or (EPCM(DS:RCX).PENDING ≠ SCRATCH_SECINFO.FLAGS.PENDING) or

(SCRATCH_SECINFO.FLAGS.PENDING is 1) AND (SCRATCH_SECINFO.FLAGS .MODIFIED is 0) AND
FI;
(EPCM(DS:RCX).MODIFIED ≠ SCRATCH_SECINFO.FLAGS.MODIFIED) or (EPCM(DS:RCX).R ≠ SCRATCH_SECINFO.FLAGS.R) or
(EPCM(DS:RCX).W ≠ SCRATCH_SECINFO.FLAGS.W) or (EPCM(DS:RCX).X ≠ SCRATCH_SECINFO.FLAGS.X) or
(EPCM(DS:RCX).PT ≠ SCRATCH_SECINFO.FLAGS.PT) )Vol. 3D 38-93INTEL® SGX INSTRUCTION REFERENCES
THEN
RFLAGS.ZF := 1;RAX := SGX_PAGE_ATT RIBUTES_MISMATCH;
GOTO DONE;
FI;(* Check that all required threads have left enclave *)IF (Tracking not correct)
THEN
RFLAGS.ZF := 1;RAX := SGX_NOT_TRACKED;GOTO DONE;
FI;
(* Get pointer to the SECS to  which the EPC page belongs *)
TMP_SECS = << Obtain physical address of SECS through EPCM(DS:RCX)>>(* For TCS pages, perform additional checks *)IF (SCRATCH_SECINFO.FLAGS.PT = PT_TCS) 
THEN
(* Check that TCS.FLAGS.DBGOPTIN, TCS stack, and TCS status are correctly initialized *)
(* check that TCS.PREVSSP is 0 *)IF ( ((DS:RCX).FLAGS.DBGOPTIN is not 0) or ((DS:RCX).CSSA 
≥ (DS:RCX).NSSA) or ((DS:RCX).AEP is not 0) or ((DS:RCX).STATE is not 0) 
or ((CPUID.(EAX=07H, ECX=0H):ECX[CET_SS]  = 1) AND ((DS:RCX).PREVSSP != 0)))
(* Check consistency of FS & GS Limit *)
IF ( (TMP_SECS.ATTRIBUTES .MODE64BIT is 0) and ((DS:RCX.FSLIMIT & FFFH ≠ FFFH) or (DS:RCX.GSLIMIT & FFFH ≠ FFFH)) )
FI;
(* Clear PENDING/MODIFIED flags to mark accept operation complete *)
EPCM(DS:RCX).PENDING := 0;EPCM(DS:RCX).MODIFIED := 0;EPCM(DS:RCX).PR := 0;
(* Clear EAX and ZF to indi cate successful completion *)
DONE:
Sets ZF if page cannot be accepted, ot herwise cleared. Clears CF, PF, AF, OF, SF38-94 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
#GP(0) If executed outside an enclave.
If a memory operand effective address is outside the DS segment limit.If a memory operand is not properly aligned.
If EPC page has incorrect page type or security attributes.
If a memory operand is not an EPC page.If EPC page has incorrect page type or security attributes.Vol. 3D 38-95INTEL® SGX INSTRUCTION REFERENCES
EACCEPTCOPY—Initialize a Pending Page  
This leaf function copies the contents of an existing EP C page into an uninitialized EPC page (created by EAUG). 
After initialization, the instruction may also modify the a ccess rights associated with the destination EPC page. This 
instruction leaf can only be exec uted when inside the enclave. 
RBX contains the effective address of a SECINFO structure while RCX and RDX each contain the effective address 
of an EPC page. The table below provides additional in formation on the memory parameter of the EACCEPTCOPY 
leaf function.
EACCEPTCOPY Memory Parameter Semantics
EACCEPTCOPY Faulting Conditions
EAX = 07H
ENCLU[EACCEPTCOPY]IR V/V SGX2 This leaf function initiali zes a dynamically allocated EPC page 
from another page in the EPC.
IR EACCEPTCOPY (In)Return Error Code 
(Out)Address of a SECINFO (In)Address of the destina-
tion EPC page (In)Address of the 
source EPC page (In)
SECINFO EPCPAGE (Destina tion) EPCPAGE (Source)
Read access permitted by Non Enclave Read/Write access permitted by Enclave Read access permitted by Enclave
The operands are not properly aligned. If security attributes of the SECINFO page make the page inaccessible.
The EPC page is locked by another thread. If security attr ibutes of the source EPC page make the page inaccessible.
The EPC page is not valid. RBX does not contain an effective address in an EPC page in the running enclave.
SECINFO contains an invalid request. RCX/RDX does not contain an effective address of an EPC page in the running 
enclave.
Table 38-57.  EACCEPTCOPY Return Value in RAX
No Error EACCEPTCOPY successful.SGX_PAGE_ATTRIBUTES_MISMATCH The attr ibutes of the target EPC page do not match the expected values.38-96 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EACCEPTCOPY Operational Flow
IF ( (DS:RCX is not 4KByte Aligned) or (DS:RDX is not 4KByte Aligned) )
IF ((DS:RBX is not within CR_ELRANGE) or (DS:RCX is not within CR_ELRANGE) or (DS:RD X is not within CR_ELRANGE))
IF (DS:RBX does not re solve within an EPC) 
IF (DS:RDX does not resolve within an EPC) 
IF ( (EPCM(DS:RBX &~FFFH).VALID = 0) or (EPCM(DS:RBX &~FFFH).R = 0)  or (EPCM(DS:RBX &~FFFH).PENDING ≠ 0) or 
(EPCM(DS:RBX &~FFFH).MODIFIED ≠ 0) or (EPCM(DS:RBX &~FFFH).BLOCKED ≠ 0) or (EPCM(DS:RBX &~FFFH).PT ≠ PT_REG) or 
(EPCM(DS:RBX &~FF FH).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RBX &~FF FH).ENCLAVEADDRESS ≠ DS:RBX) )
THEN #PF(DS:RBX); FI;Table 38-58.  Base Concurrency Restrictions of EACCEPTCOPY
Table 38-59.  Additional Concurrency Restrictions of EACCEPTCOPY
SCRATCH_SECINFO SECINFO 512 Scratch storage for holding the contents of DS:RBX.Vol. 3D 38-97INTEL® SGX INSTRUCTION REFERENCES
SCRATCH_SECINFO := DS:RBX;
IF ( (SCRATCH_SECINFO reserv ed fields are not zero ) or (SCRATCH_SEC INFO.FLAGS.R=0) AND(SCRATCH_SECINFO.FLAGS.W ≠0 ) or
(SCRATCH_SECINFO.FLAGS.PT is not PT_REG) ) THEN #GP(0); FI;
(* Check security attributes of the source EPC page *)
IF ( (EPCM(DS:RDX).VALID = 0) or (EPCM(DS:RCX).R = 0) or (EPCM(DS:RDX).PENDING ≠ 0) or (EPCM(DS:RDX).MODIFIED ≠ 0) or 
(EPCM(DS:RDX).BLOCKED ≠ 0) or (EPCM(DS:RDX).PT ≠ PT_REG) or (EPCM( DS:RDX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RDX).ENCLAVEADDRESS ≠ DS:RDX))
IF ( (EPCM(DS:RCX).VALID = 0)  or (EPCM(DS:RCX).PENDING ≠ 1) or (EPCM(DS:RCX).MODIFIED ≠ 0) or 
(EPCM(DS:RDX).BLOCKED ≠ 0) or (EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) )
THEN 
RFLAGS.ZF := 1;RAX := SGX_PAGE_ATT RIBUTES_MISMATCH; 
GOTO DONE;
FI;
IF (destination EPC page in use ) 
(EPCM(DS:RCX).R ≠ 1) or (EPCM(DS:RCX).W ≠ 1) or (EPCM(DS:RCX).X ≠ 0) or 
(EPCM(DS:RCX).PT ≠ SCRATCH_SECINFO.FLAGS.PT) or  (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RCX).ENCLAVEADDRESS ≠ DS:RCX))
THEN 
GOTO DONE;
FI;
(* Copy 4KBbytes form the source to destination EPC page*)
DS:RCX[32767:0] := DS:RDX[32767:0];
EPCM(DS:RCX).R := SCRATCH_SECINFO.FLAGS.R;EPCM(DS:RCX).W := SCRATCH_SECINFO.FLAGS.W;EPCM(DS:RCX).X := SCRATCH_SECINFO.FLAGS.X;EPCM(DS:RCX).PENDING := 0;
RAX := 0;
DONE:
RFLAGS.CF,PF,AF,OF,SF := 0;38-98 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Sets ZF if page is not modifiable, othe rwise cleared. Clears CF, PF, AF, OF, SF.
If a memory operand effective address is outside the DS segment limit.
If EPC page has incorrect page type or security attributes.Vol. 3D 38-99INTEL® SGX INSTRUCTION REFERENCES
EDECCSSA—Decrements TCS.CSSA

RAX := 0;
DONE:
EDECCSSA—Decrements TCS.CSSA 
This leaf function changes the current SSA frame by decr ementing TCS.CSSA for the current enclave thread. If the 
enclave has enabled CET shadow stacks or indirect branch  tracking, then EDECCSSA also changes the current CET 
state save frame. This instruction leaf can only be executed inside an enclave.
EDECCSSA Memory Pa rameter Semantics
EDECCSSA Faulting Conditions
EAX = 09H
ENCLU[EDECCSSA]IR V/V EDECCSSA This leaf function decrements TCS.CSSA.
Op/En EAX
IR EDECCSSA (In)
TCS
Read/Write access by Enclave
TCS.CSSA is 0. TCS is not valid or available or locked.
The SSA frame is not valid or in use.
Table 38-60.  Base Concurrency Restrictions of EDECCSSA
EDECCSSA TCS [CR_TCS_PA] Shared #GP
Table 38-61.  Additional Concurrency Restrictions of EDECCSSA
EDECCSSA TCS [CR_TCS_PA] Concurrent Concurrent Concurrent38-100 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EDECCSSA Operational Flow
IF (CR_TCS_PA.CSSA = 0)
(* Compute linear address of SSA frame *)
TMP_SSA := CR_TCS_PA.OSSA + CR_ACTIVE_SECS.BASEADDR + 4096 * CR_ACTIVE_SECS.SSAFRAMESIZE * (CR_TCS_PA.CSSA - 1);TMP_XSIZE := compute_XSAVE_frame_si ze(CR_ACTIVE_SECS.ATTRIBUTES.XFRM);
FOR EACH TMP_SSA_PAGE = TMP_ SSA to TMP_SSA + TMP_XSIZE
(* Check page is read/write accessible *)Check that DS:TMP_SSA_PAGE is read/write accessible;If a fault occurs, release locks,  abort and deliver that fault;
IF (DS:TMP_SSA_PAGE does not resolve to EPC page)
THEN #PF(DS:TMP _SSA_PAGE); FI;
IF (EPCM(DS:TMP_SSA_PAGE).VALID = 0)
IF (EPCM(DS:TMP_SSA _PAGE).BLOCKED = 1)
IF ((EPCM(DS:TMP_SSA_PAGE).PENDING = 1) or (EPCM(DS:TMP_SSA_PAGE_.MODIFIED = 1))
IF ( ( EPCM(DS:TMP_SSA_PAGE).ENCLAVEADDRESS 
≠ DS:TMPSSA_PAGE) or
(EPCM(DS:TMP_SSA_PAGE).PT ≠ PT_REG) or
(EPCM(DS:TMP_SSA_PAGE).ENCLAVESECS ≠ EPCM(CR_TCS_PA).ENCLAVESECS) or
(EPCM(DS:TMP_SSA_PAGE).R = 0) or (EPCM(DS:TMP_SSA_PAGE).W = 0))
TMP_XSAVE_PAGE_PA_n := Physic al_Address(DS:T MP_SSA_PAGE);
ENDFOR
(* Compute address of GPR area*)
TMP_GPR := TMP_SSA + 4096 * CR_ACTIVE_ SECS.SSAFRAMESIZE - sizeof(GPRSGX_AREA);
Check that DS:TMP_SSA_PAGE is read/write accessible;
If a fault occurs, release locks, abort and deliver that fault;IF (DS:TMP_GPR does no t resolve to EPC page)
THEN #PF(DS:TMP_GPR); FI;Name Type Size (bits) Description
TMP_SSA Effective 
Address32/64 Address of current SSA frame.
TMP_XSIZE Integer 64 Size of XSAVE area based on SECS.ATTRIBUTES.XFRM.
TMP_SSA_PAGE Effective 
Address32/64 Pointer used to iterate over the SSA pages in the target frame.
TMP_GPR Effective 
Address32/64 Address of the GPR area within the target SSA frame.
TMP_XSAVE_PAGE_PA_n Physical 
Address32/64 Physical address of the nth page within the target SSA frame.
TMP_CET_SAVE_AREA Effective 
Address32/64 Address of the current CET save area.
TMP_CET_SAVE_PAGE Effective 
Address32/64 Address of the current CET save area page.Vol. 3D 38-101INTEL® SGX INSTRUCTION REFERENCES
IF (EPCM(DS:TMP_GPR).VALID = 0)
THEN #PF(DS:TMP_GPR); FI;
IF (EPCM(DS:TMP_GPR).BLOCKED = 1)
IF ((EPCM(DS:TMP_GPR).PENDING = 1) or (EPCM(DS:TMP_GPR).MODIFIED = 1))
IF ( ( EPCM(DS:TMP_ GPR).ENCLAVEADDRESS ≠ DS:TMP_GPR) or
(EPCM(DS:TMP_GPR).PT ≠ PT_REG) or
(EPCM(DS:TMP_GPR).ENCLAVESECS ≠ EPCM(CR_TCS_PA).ENCLAVESECS) or
(EPCM(DS:TMP_GPR).R = 0) or (EPCM(DS:TMP_GPR).W = 0) )
IF (TMP_MODE64 = 0)
THEN
IF (TMP_GPR + (sizeof(GPRSGX_AREA) -1) is not in DS segment)
FI;
THEN
IF ((CR_ACTIVE_SECS.CET_ATTRIBUTES.SH_STK_EN == 1)  OR (CR_ACTIVE_SECS.CET_ATTRIBUTES.ENDBR_EN == 1)) 
THEN
(* Compute linear address of what will become  new CET state save area and cache its PA *)
TMP_CET_SAVE_AREA := CR_TCS_PA.OCETSSA + CR_ACT IVE_SECS.BASEADDR + (CR_ TCS_PA.CSSA - 1) * 16;
TMP_CET_SAVE_PAGE := TMP_CET_SAVE_AREA & ~0xFFF; Check the TMP_CET_SAVE_PAGE page is read/write accessible If fault occurs release locks, abort and deliver fault
(* read the EPCM VALID, PENDING, MODIFIED, BLOCKED and PT fields atomically *)
IF ((DS:TMP_CET_SAVE_PAGE Does NOT RESOLVE TO EPC PAGE) OR (EPCM(DS:TMP_CET_SAVE_PAGE).VALID = 0) OR (EPCM(DS:TMP_CET_SAVE_PAGE).PENDING = 1) OR (EPCM(DS:TMP_CET_SAVE_PAGE).MODIFIED = 1) OR (EPCM(DS:TMP_CET_SAVE_PAGE).BLOCKED = 1) OR (EPCM(DS:TMP_CET_SAVE_PAGE).R = 0) OR (EPCM(DS:TMP_CET_SAVE_PAGE).W = 0) OR (EPCM(DS:TMP_CET_SAVE_ PAGE).ENCLAVEADDRESS 
≠ DS:TMP_CET_SAVE_PAGE) OR 
(EPCM(DS:TMP_CET_SAVE_PAGE).PT ≠ PT_SS_REST) OR 
(EPCM(DS:TMP_CET_SAV E_PAGE).ENCLAVESECS ≠ EPCM(CR_TCS_PA).ENCLAVESECS))
THEN #PF(DS:TMP_CET_SAVE_PAGE); FI;
FI;
FI;
(* At this point, the instructio n is guaranteed to complete *)
CR_TCS_PA.CSSA := CR_TCS_PA.CSSA - 1;
CR_GPR_PA := Physical _Address(DS:TMP_GPR);
FOR EACH TMP_ XSAVE_PAGE_n
CR_XSAVE_PAGE_n := TMP_XSAVE_PAGE_PA_n;
ENDFOR
THEN38-102 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF ((TMP_SECS.CET_ATTRIBUTES.SH_STK_EN == 1) OR
(TMP_SECS.CET_ATTRIBUTES.ENDBR_EN == 1)) 
THEN
CR_CET_SAVE_AREA_PA := Physical _Address(DS:TMP_CET_SAVE_AREA);
FI;
FI;
None
If CR_TCS_PA.CSSA = 0.
#PF(error code) If a page fault occurs in accessing memory.
If one or more pages of the target SSA frame ar e not readable/writable, or do not resolve to a 
valid PT_REG EPC page.
If CET is enabled for the enclave and the target  CET SSA frame is not readable/writable, or 
does not resolve to a valid PT_REG EPC page.
does not resolve to a valid PT_REG EPC page.Vol. 3D 38-103INTEL® SGX INSTRUCTION REFERENCES
EENTER—Enters an Enclave
The ENCLU[EENTER] instruction transfers execution to an enclave. At the end of the instruction, the logical 
processor is executing in enclave mode at the RIP comput ed as EnclaveBase + TCS.OENTRY. If the target address 
is not within the CS segment (32-bit) or is not canonical (64-bit), a #GP(0) results.
EENTER Memory Parameter Semantics
EENTER is a serializing instruction. The instruction faults if any of the following occurs: 
The following operations are performed by EENTER:
•RSP and RBP are saved in the current SSA frame on EENTER and are automatically restored on EEXIT or 
•The AEP contained in RCX is stored into the TCS for us e by AEXs.FS and GS (including hidden portions) are 
saved and new values are constructed using TCS.OFSBASE/GSBASE (32 and 64-bit mode) and 
TCS.OFSLIMIT/GSLIMIT (32-bit mode only). The resultin g segments must be a subset of the DS segment. 
•If CR4.OSXSAVE == 1, XCR0 is saved and replaced by SECS.ATTRIBUTES.XFRM. The effect of RFLAGS.TF 
depends on whether the enclave entry is opt-in or opt-out (see Section 40.1.2):
— On opt-out entry, TF is saved and cleared (it is restor ed on EEXIT or AEX). Any attempt to set TF via a POPF 
instruction while inside the enclave clears TF (see Section 40.2.5).
— On opt-in entry, a single-step debug exception is pended on the instruction boundary immediately after 
EENTER (see Section 40.2.2). Opcode/
EAX = 02H
ENCLU[EENTER]IR V/V SGX1 This leaf function is used to enter an enclave.
IR EENTER (In)Content of RBX.CSSA 
(Out)Address of a TCS (In) Address of AEP (In)Address of IP following 
EENTER (Out)
TCS
 Enclave access
Address in RBX is not properly aligned. Any TCS.FLAGS’s must-be-zero bit is not zero.
TCS pointed to by RBX is not valid or available or locked. Current 32/64 mode does not match the enclave mode in 
SECS.ATTRIBUTES.MODE64.
The SECS is in use. Either of TCS-specified FS and GS segment is not a subsets of the 
current DS segment.
Any one of DS, ES, CS, SS is not zero. If XSAVE available, CR4.OSXSAVE = 0, but 
SECS.ATTRIBUTES.XFRM ≠ 3.
CR4.OSFXSR ≠ 1. If CR4.OSXSAVE = 1, SECS.ATTRIBUTES.XFRM is not a subset of 
XCR0.
If SECS.ATTRIBUTES.AEXNOTIFY ≠ TCS.FLAGS.AEXNOTIFY and 
TCS.FLAGS.DBGOPTIN = 0.38-104 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES

EAX = 02H
TCS
XCR0.
•All code breakpoints that do not overlap with ELRANGE are also suppressed. If the entry is an opt-out entry, all 
code and data breakpoints that over lap with the ELRANGE are suppressed.
•On opt-out entry, a number of performance monitoring counters and behaviors are modified or suppressed (see 
Section 40.2.3):
— All performance monitoring activity on the current th read is suppressed except for incrementing and firing 
of FIXED_CTR1 and FIXED_CTR2.
— PEBS is suppressed.— AnyThread counting on other threads is demoted to  MyThread mode and IA32_PERF_GLOBAL_STATUS[60] 
on that thread is set
— If the opt-out entry on a hardware thread results in  suppression of any performance monitoring, then the 
processor sets IA32_PERF_GLOBAL_STATUS[60] and IA32_PERF_GLOBAL_STATUS[63].
Operation
Temp Variables in EE NTER Operational Flow
(* Make sure DS is usable, expand up *)
IF (TMP_MODE64 = 0 and (DS not usable or ( ( DS[S] = 1) and (DS[bit 11] = 0) and DS[bit 10] = 1) ) ) 
(* Check that CS, SS, DS, ES.base is 0 *)
THEN Table 38-62.  Base Concurrency Restrictions of EENTER
EENTER TCS [DS:RBX] Shared #GP
Table 38-63.  Additional Concurrency Restrictions of EENTER
EENTER TCS [DS:RBX] Concurrent Concurrent Concurrent
TMP_FSBASE Effective Address 32/64 Proposed base address for FS segment.
TMP_GSBASE Effective Address 32/64 Proposed base address for FS segment.TMP_FSLIMIT Effective Address 32/64 Highest legal address in proposed FS segment.
TMP_GSLIMIT Effective Address 32/64 Highest legal address in proposed GS segment.
TMP_XSIZE integer 64 Size of XSAVE area based on SECS.ATTRIBUTES.XFRM.
TMP_SSA_PAGE Effective Address 32/64 Pointer used to iterate over the SSA pages in the current frame.
TMP_GPR Effective Address 32/64 Address of the GPR area within the current SSA frame.Vol. 3D 38-105INTEL® SGX INSTRUCTION REFERENCES
IF(CS.base ≠ 0 or DS.base ≠ 0) #GP(0); FI;
IF(ES usable and ES.base ≠ 0) #GP(0); FI;
IF(SS usable and SS.base ≠ 0) #GP(0); FI;
IF(SS usable and SS.B = 0) #GP(0); FI;
FI;
IF (DS:RBX is not 4KByte Aligned)
IF (DS:RBX does not resolve within an EPC)
(* Check AEP is canonical*)
IF (TMP_MODE64 = 1 and (CS:RCX is not canonical) )
(* Check concurrency of TCS operation*)
IF (Other Intel SGX instruct ions are operating on TCS) 
(* TCS verification *)
IF (EPCM(DS:RBX).VALID = 0) 
IF (EPCM(DS:RBX).BLOCKED = 1) 
IF ( (EPCM(DS:RBX).ENCLAVEADDRESS ≠ DS:RBX) or (EPCM(DS:RBX).PT ≠ PT_TCS) )
IF ((EPCM(DS:RBX).PENDING = 1) or (EPCM(DS:RBX).MODIFIED = 1))
IF ( (DS:RBX).OSSA is not 4KByte Aligned)
(* Check proposed FS and GS *)
IF ( ( (DS:RBX).OFSBASE is not 4KByte Aligned) or ( (DS:RBX).OGSBASE is not 4KByte Aligned) )
(* Get the SECS for the enclave in which the TCS resides *)
TMP_SECS := Address of SECS for TCS;
(* Ensure that the FLAGS field in the TC S does not have any reserved bits set *)
IF ( ( (DS:RBX).FLAGS & FFFFFFFFFFFFFFFCH) ≠ 0) 
(* SECS must exist and enclave must have previously been EINITted *)
IF (the enclave is not already initialized) 
(* make sure the logical processor’s operating mode matches the enclave *)
IF ( (TMP_MODE64 ≠ TMP_SECS.ATTRIBUTES.MODE64BIT) )
THEN #GP(0); FI;38-106 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF (CR4.OSFXSR = 0)
(* Check for legal values of SECS.ATTRIBUTES.XFRM *)
IF (CR4.OSXSAVE = 0)
THEN 
IF (TMP_SECS.ATTRIBUTES.XFRM ≠ 03H) THEN #GP(0); FI;
ELSE
IF ( (TMP_SECS.ATTR IBUTES.XFRM & XCR0) ≠ TMP_SECS.ATTRIBUES.XFRM) THEN #GP(0); FI;
FI;
IF ((DS:RBX).CSSA.FLAGS.DBGOPTIN = 0)  and (DS:RBX).CSSA.FLAGS.AEXNOTIFY ≠ TMP_SECS.ATTRIBUTES.AEXNOTIFY))
(* Make sure the SSA contains  at least one more frame *)
IF ( (DS:RBX).CSSA ≥ (DS:RBX).NSSA) 
TMP_SSA := (DS:RBX).OSSA + TMP_SECS.BASEADDR + 4096 * TMP_SECS.SSAFRAMESIZE * (DS:RBX).CSSA;TMP_XSIZE := compute_XSAVE_frame_ size(TMP_SECS.ATTRIBUTES.XFRM);
(* Check page is read/write accessible *)Check that DS:TMP_SSA_PAGE is read/write accessible; If a fault occurs, release locks,  abort, and deliver that fault;
IF (DS:TMP_SSA_PAGE does not resolve to EPC page) 
IF (EPCM(DS:TMP_SSA_PAGE).VALID = 0) 
IF (EPCM(DS:TMP_SSA_P AGE).BLOCKED = 1) 
IF ((EPCM(DS:TMP_SSA_PAGE).PENDING = 1) or (EPCM(DS:TMP_SSA_PAGE).MODIFIED = 1))
IF ( ( EPCM(DS:TMP_SSA_PAGE).ENCLAVEADDRESS ≠ DS:TMP_SSA_PAGE) or (E PCM(DS:TMP_SSA_PAGE).PT ≠ PT_REG) or
(EPCM(DS:TMP_SSA_PAGE).ENCLAVESECS ≠ EPCM(DS:RBX).ENCLAVESECS) or 
(EPCM(DS:TMP_SSA_PAGE).R = 0) or (EPCM(DS:TMP_SSA_PAGE).W = 0) )THEN #PF(DS:TMP _SSA_PAGE); FI;
CR_XSAVE_PAGE_n := Physical_Address(DS:TMP_SSA_PAGE);
ENDFOR
TMP_GPR := TMP_SSA + 4096 * DS:TMP_SEC S.SSAFRAMESIZE - sizeof(GPRSGX_AREA);
If a fault occurs; release locks,  abort, and deliver that fault;
IF (DS:TMP_GPR does no t resolve to EPC page) 
IF (EPCM(DS:TMP_GPR).VALID = 0) 
IF (EPCM(DS:TMP_GPR).BLOCKED = 1) 
THEN #PF(DS:TMP_GPR); FI;Vol. 3D 38-107INTEL® SGX INSTRUCTION REFERENCES
IF ( ( EPCM(DS:TMP_ GPR).ENCLAVEADDRESS ≠ DS:TMP_GPR) or (EPCM(DS:TMP_GPR).PT ≠ PT_REG) or
(EPCM(DS:TMP_GPR).ENCLAVESECS EPCM(DS:RBX).ENCLAVESECS) or 
(EPCM(DS:TMP_GPR).R = 0) or (EPCM(DS:TMP_GPR).W = 0) )THEN #PF(DS:TMP_GPR); FI;
THEN 
IF (TMP_GPR + (GPR_SIZE -1) is not in DS segment) THEN #GP(0); FI;
FI;
CR_GPR_PA := Physical_A ddress (DS: TMP_GPR);
(* Validate TCS.OENTRY *)
TMP_TARGET := (DS:RBX).OENTRY + TMP_SECS.BASEADDR;IF (TMP_MODE64 = 1)
THEN 
IF (TMP_TARGET is not canonical) THEN #GP(0); FI;
ELSE
IF (TMP_TARGET > CS li mit) THEN #GP(0); FI;
FI;
(* Check proposed FS/GS se gments fall within DS *)
THEN 
TMP_FSBASE := (DS:RBX).OFSBASE + TMP_SECS.BASEADDR;TMP_FSLIMIT := (DS:RBX).OFSBASE + TM P_SECS.BASEADDR + (DS:RBX).FSLIMIT;
TMP_GSBASE := (DS:RBX).OGSBASE + TMP_SECS.BASEADDR;TMP_GSLIMIT := (DS:RBX).OGSBASE + TM P_SECS.BASEADDR + (DS:RBX).GSLIMIT;
(* if FS wrap-around, make sure DS has no holes*)IF (TMP_FSLIMIT < TMP_FSBASE)
THEN 
IF (DS.limit < 4GB) THEN #GP(0); FI;
ELSE
IF (TMP_FSLIMIT > DS.limit) THEN #GP(0); FI;
FI;(* if GS wrap-aro und, make sure DS has no holes*)
IF (TMP_GSLIMIT < TMP_GSBASE)
THEN 
ELSE
IF (TMP_GSLIMIT > DS.limit) THEN #GP(0); FI;
FI;
ELSE
TMP_FSBASE := (DS:RBX).OFSBASE + TMP_SECS.BASEADDR;TMP_GSBASE := (DS:RBX).OGSBASE + TMP_SECS.BASEADDR;IF ( (TMP_FSBASE is not canonical) or (TMP_GSBASE is not canonical))
FI;
(* Ensure the enclave is not already active and this thread is the only one using the TCS*)
IF (DS:RBX.STATE = ACTIVE) 
TMP_IA32_U_CET := 038-108 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
TMP_SSP : = 0
IF CPUID.(EAX=12H, ECX=1):EAX[6] = 1
THEN
IF ( CR4.CET = 0 )
THEN
(* If part does not support CET or CET has not been enabled and enclave requires CET then fail *)IF ( TMP_SECS.CET_ATTRIBUTES ≠ 0 OR TMP_SECS.CET_LEG_BITMAP_OFFSET ≠ 0 ) #GP(0); FI;
FI;(* If indirect branch tracking or shadow stacks enabled bu t CET state save area is not 16B aligned then fail EENTER *)
IF ( TMP_SECS.CET_ATTRIBUTES.SH_STK_EN = 1 OR TMP_SECS.CET_ATTRIBUTES.ENDBR_EN = 1 )
THEN
IF (DS:RBX.OCETSSA is not 16B aligned) #GP(0); FI;
FI;
IF (TMP_SECS.CET_ATTRIBUTE S.SH_STK_EN OR TMP_SECS.C ET_ATTRIBUTES.ENDBR_EN) 
THEN
(* Setup CET state from SECS, note tracker goes to IDLE *) TMP_IA32_U_CET = TMP_ SECS.CET_ATTRIBUTES; 
IF (TMP_IA32_U_CET.LEG_IW_EN = 1 AND TMP_IA32_U_CET.ENDBR_EN = 1 ) 
THEN
TMP_IA32_U_CET := TMP_IA32_U_CET + TMP_SECS.BASEADDR;TMP_IA32_U_CET := TMP_IA32_U_CET + TMP_SECS.CET_LEG_BITMAP_BASE;
FI;
(* Compute linear address of what will become new CET state save area and cache its PA *) 
TMP_CET_SAVE_AREA = DS:RBX.OCETSSA + TM P_SECS.BASEADDR + (DS:RBX.CSSA) * 16 
TMP_CET_SAVE_PAGE = TMP_CET_SAVE_AREA & ~0xFFF; 
Check the TMP_CET_SAVE_PAGE page is read/write accessible 
If fault occurs release lock s, abort, and deliver fault
(* Read the EPCM VALID, PENDING, MODIFI ED, BLOCKED, and PT fields atomically *)

THEN
FI;
THEN
THEN
FI;
IF ((DS:TMP_CET_SAVE_PAGE Does NOT RESOLVE TO EPC PAGE) OR (EPCM(DS:TMP_CET_SAVE_PAGE).VALID = 0) OR (EPCM(DS:TMP_CET_SAVE_PAGE).PENDING = 1) OR (EPCM(DS:TMP_CET_SAVE_PAGE).MODIFIED = 1) OR (EPCM(DS:TMP_CET_SAVE_PAGE).BLOCKED = 1) OR (EPCM(DS:TMP_CET_SAVE_PAGE).R = 0) OR (EPCM(DS:TMP_CET_SAVE_PAGE).W = 0) OR (EPCM(DS:TMP_CET_SAV E_PAGE).ENCLAVEADDRESS ≠ DS:TMP_CET_SAVE_PAGE) OR
 (EPCM(DS:TMP_CET_SAVE_PAGE).PT ≠ PT_SS_REST) OR
 (EPCM(DS:TMP_CET_SAV E_PAGE).ENCLAVESECS ≠ EPCM(DS:RBX).ENCLAVESECS))
THEN
#PF(DS:TMP_CET_SAVE_PAGE);
FI;
CR_CET_SAVE_AREA_PA := Physical  address(DS:TMP_CET_SAVE_AREA)
IF TMP_IA32_U_CET.SH_STK_EN = 1
THEN
TMP_SSP = TCS.PREVSSP;
FI;
FI;Vol. 3D 38-109INTEL® SGX INSTRUCTION REFERENCES
FI;
CR_ENCLAVE_MODE := 1;
CR_ACTIVE_SECS := TMP_SECS;CR_ELRANGE := (TMPSECS.BASEADDR, TMP_SECS.SIZE);
(* Save state for possible AEXs *)
CR_TCS_PA := Physical_Address (DS:RBX);CR_TCS_LA := RBX;CR_TCS_LA.AEP := RCX;
(* Save the hidden port ions of FS and GS *)
CR_SAVE_FS_selector := FS.selector;CR_SAVE_FS_base := FS.base;CR_SAVE_FS_limit := FS.limit;CR_SAVE_FS_access_rights := FS.access_rights;CR_SAVE_GS_selector := GS.selector;CR_SAVE_GS_base := GS.base;CR_SAVE_GS_limit := GS.limit;CR_SAVE_GS_access_rights  := GS.access_rights;
(* If XSAVE is enabled, save XCR0 an d replace it with SECS.ATTRIBUTES.XFRM*)
IF (CR4.OSXSAVE = 1) 
CR_SAVE_XCR0 := XCR0;XCR0 := TMP_SECS.ATTRIBUTES.XFRM;
FI;
RCX := RIP;
RIP := TMP_TARGET;RAX := (DS:RBX).CSSA;(* Save the outside RSP and RBP so they can be restored on interrupt or EEXIT *)
DS:TMP_SSA.U_RSP := RSP; DS:TMP_SSA.U_RBP := RBP; 
(* Do the FS/GS swap *)
FS.base := TMP_FSBASE;FS.limit := DS:RBX.FSLIMIT;FS.type := 0001b;FS.W := DS.W;FS.S := 1;FS.DPL := DS.DPL;FS.G := 1;FS.B := 1;FS.P := 1;FS.AVL := DS.AVL;FS.L := DS.L;FS.unusable := 0;FS.selector := 0BH;
GS.base := TMP_GSBASE;
GS.limit := DS:RBX.GSLIMIT;GS.type := 0001b;GS.W := DS.W;GS.S := 1;38-110 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
GS.DPL := DS.DPL;
GS.G := 1;GS.B := 1;GS.P := 1;GS.AVL := DS.AVL;GS.L := DS.L;GS.unusable := 0;GS.selector := 0BH;
CR_DBGOPTIN := TCS.FLAGS.DBGOPTIN;
Suppress_all_code_breakpoints _that_are_outside_ELRANGE;
IF (CR_DBGOPTIN = 0) 
THEN
Suppress_all_code_breakpoints_that_overlap_with_ELRANGE;CR_SAVE_TF := RFLAGS.TF;RFLAGS.TF := 0;Suppress_monitor_trap_flag for the source of the execution of the enclave;Suppress any pending debug exceptions;Suppress any pending MTF VM exit;
ELSE
IF RFLAGS.TF = 1
THEN pend a single-step #DB at the end of EENTER; FI;
IF the “monitor trap flag” VM-execution control is set
THEN pend an MTF VM exit at the end of EENTER; FI;
FI;
IF ((CPUID.(EAX=7H, ECX=0):EDX[CET_IBT] = 1)  OR (CPUID.(EAX=7H, ECX=0):ECX[CET_SS] = 1)
THEN
(* Save enclosing application CET state into save registers *) CR_SAVE_IA32_U_CET := IA32_U_CET(* Setup enclave CET state *) IF CPUID.(EAX=07H, EC X=00h):ECX[CET_SS] = 1 
THEN
CR_SAVE_SSP := SSP SSP := TMP_SSP
FI; 
IA32_U_CET := TMP_IA32_U_CET;
FI;Flush_linear_context;
Allow_front_end_to_beg in_fetch_at_new_RIP;
RFLAGS.TF is cleared on opt-out entry.Vol. 3D 38-111INTEL® SGX INSTRUCTION REFERENCES
#GP(0) If DS:RBX is not page aligned.
If the enclave is not initialized.If part or all of the FS or GS segment specifie d by TCS is outside the DS segment or not prop-
erly aligned.
If the thread is not in the INACTIVE state.If CS, DS, ES or SS bases are not all zero.
If executed in enclave mode.
If any reserved field in the TCS FLAG is set.If the target address is not within the CS segment.
If CR4.OSXSAVE = 0 and SECS.ATTRIBUTES.XFRM ≠ 3.
If CR4.OSXSAVE = 1and SECS.ATTRIBUTES.XFRM is not a subset of XCR0.
If SECS.ATTRIBUTES.AEXNOTIFY ≠ TCS.FLAGS.AEXNOTIFY and TCS.FLAGS.DBGOPTIN = 0.
If DS:RBX does not point to a valid TCS.
If one or more pages of the current SSA frame ar e not readable/writable, or do not resolve to 
a valid PT_REG EPC page.
If the enclave is not initialized.If the thread is not in the INACTIVE state.
If CS, DS, ES or SS bases are not all zero.
If executed in enclave mode.If part or all of the FS or GS segment specifie d by TCS is outside the DS segment or not prop-
If the target address is not canonical.If CR4.OSFXSR = 0.
If CR4.OSXSAVE = 1and SECS.ATTRIBUTES.XFRM is not a subset of XCR0.If SECS.ATTRIBUTES.AEXNOTIFY ≠ TCS.FLAGS.AEXNOTIFY and TCS.FLAGS.DBGOPTIN = 0.
If DS:RBX does not point to a valid TCS.If one or more pages of the current SSA frame ar e not readable/writable, or do not resolve to 
a valid PT_REG EPC page.38-112 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EEXIT—Exits an Enclave
The ENCLU[EEXIT] instruction exits the currently executing enclave and branches to the location specified in RBX. 
RCX receives the current AEP. If RBX is not within the CS  (32-bit mode) or is not canonical (64-bit mode) a #GP(0) 
results.
EEXIT Memory Parameter Semantics
If RBX specifies an address that is inside the enclave, th e instruction will complete normally. The fetch of the next 
instruction will occur in non-enclave mode, but will attempt to fetch from inside the enclave. This fetch returns a 
fixed data pattern.
If secrets are contained in any registers, it is resp onsibility of enclave software to clear those registers.
If XCR0 was modified on enclave entry, it is restored to the value it had at the time of the most recent EENTER or 
ERESUME.
If the enclave is opt-out, RFLAGS.TF is loaded  from the value previously saved on EENTER. 
Code and data breakpoints are unsuppressed.Performance monitoring counters are unsuppressed.
EAX = 04H
ENCLU[EEXIT]IR V/V SGX1 This leaf function is  used to exit an enclave.
IR EEXIT (In) Target address outside the enclave (In) Address of the current AEP (Out)
Target Address
 Non-Enclave read and execute access
Table 38-64.  Base Concurrency Restrictions of EEXIT
EEXIT Concurrent
Table 38-65.  Additional Concurrency Restrictions of EEXIT
EEXIT Concurrent Concurrent ConcurrentVol. 3D 38-113INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EEXIT Operational Flow
IF (TMP_MODE64 = 1)
THEN 
IF (RBX is not canonical) THEN #GP(0); FI;
ELSE
IF (RBX > CS limit) THEN #GP(0); FI;
FI;
TMP_RIP := CRIP;
RIP := RBX;
(* Return current AEP in RCX *)
FS.selector := CR_SAVE_FS.selector;FS.base := CR_SAVE_FS.base;FS.limit := CR_SAVE_FS.limit;FS.access_rights := CR _SAVE_FS.access_rights;
GS.selector := CR_SAVE_GS.selector;GS.base := CR_SAVE_GS.base;GS.limit := CR_SAVE_GS.limit;GS.access_rights := CR _SAVE_GS.access_rights;
XCR0 := CR_SAVE__XCR0;
FI;
Unsuppress_all_code_b reakpoints_that_ar e_outside_ELRANGE;
THEN
UnSuppress_all_code_b reakpoints_that_over lap_with_ELRANGE;
Restore suppre ssed breakpoint matches;
RFLAGS.TF := CR_SAVE_TF;UnSuppress_montior_trap_flag;UnSuppress_LBR_Generation;UnSuppress_ performance monitoring _activity;
Restore performance monitoring counter AnyThread demo tion to MyThread in en clave back to AnyThread
FI;
THEN Pend Single-Step #DB at the end of EEXIT;
FI;Name Type Size (Bits) Description
TMP_RIP Effective Address 32/64 Saved copy of CRIP for use when creating LBR.38-114 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
THEN pend a MTF VM exit at the end of EEXIT;
FI;
THEN
(* Record PREVSSP *) IF (IA32_U_CET.SH_STK_EN == 1) 
THEN CR_TCS_PA.PREVSSP = SSP; FI; 
FI;
IF ((CPUID.(EAX=7H, ECX=0):EDX[CET_IBT] = 1) OR (CPUID.(EAX=7, ECX=0):ECX[CET_SS] = 1)
THEN 
(* Restore enclosing app’s CET st ate from the save registers *) 
IA32_U_CET := CR_SAVE_IA32_U_CET; 
IF CPUID.(EAX=07H, EC X=00h):ECX[CET_SS] = 1
THEN SSP := CR_SAVE_SSP; FI; 
(* Update enclosing app’s TRACKER if enclosing app has indirect branch tracking enabled *) 
IF (CR4.CET = 1 AND IA32_U_CET.ENDBR_EN = 1) 
THEN 
IA32_U_CET.TRACKER := WAIT_FOR_ENDBRANCH; IA32_U_CET.SUPPRESS := 0 
FI;
FI;
CR_TCS_PA.STATE := INACTIVE;
(* Assure consistent translations *)
Flush_linear_context;
RFLAGS.TF is restored from the value previously saved in EENTER or ERESUME.
If RBX is outside the CS segment.

FI;
THEN
FI;
THEN 
THEN 
FI;
FI;
If RBX is not canonical.
#PF(error code) If a page fault occurs in accessing memory operands.Vol. 3D 38-115INTEL® SGX INSTRUCTION REFERENCES
EGETKEY—Retrieves a Cryptographic Key 
The ENCLU[EGETKEY] instruction returns a 128-bit secret  key from the processor specific key hierarchy. The 
register RBX contains the effective address of a KEYREQUE ST structure, which the inst ruction interprets to deter-
mine the key being requested. The Requesting Keys sectio n below provides a description of the keys that can be 
requested. The RCX register contains the effective addre ss where the key will be returned. Both the addresses in 
RBX & RCX should be locations inside the enclave. 
EGETKEY derives keys using a processor unique value to cr eate a specific key based on a number of possible 
inputs. This instruction leaf can only be executed inside an enclave.
EEGETKEY Memory Pa rameter Semantics
After validating the operands, the instruction determines wh ich key is to be produced and performs the following 
actions:
•The instruction assembles the derivation data for the key based on the Table 38-66.
•Computes derived key using the derivation data and package specific value.
•Outputs the calculated key to the address in RCX.
The instruction fails with #GP(0) if the operands are not properly aligned. Successful co mpletion of the instruction 
will clear RFLAGS.{ZF, CF, AF, OF, SF, PF}. The instruction re turns an error code if the user tries to request a key 
based on an invalid CPUSVN or ISVSVN (when the user re quest is accepted, see the table below), requests a key 
for which it has not been granted the attribute to request, or requests a key that is not supported by the hardware. These checks may be performed in any order. Thus, an indication by error number of one cause (for example, 
invalid attribute) does not imply that there are not also other errors. Different processors may thus give different 
error numbers for the same Enclave. The correctness of so ftware should not rely on the order resulting from the 
checks documented in this section. In such cases the ZF flag is set and the corresponding error bit (SGX_IN-
VALID_SVN, SGX_INVALID_ATTRIBUTE, SGX_INVALID_KEYNAME)  is set in RAX and the data at the address spec-
ified by RCX is unmodified.
Requesting KeysThe KEYREQUEST structure (see Section 35.18.1) identifies  the key to be provided. The Keyrequest.KeyName field 
identifies which type of key is requested. 
Deriving KeysKey derivation is based on a combinat ion of the enclave specific values (s ee Table 38-66) and a processor key. 
Depending on the key being requested a field may either be  included by definition or the value may be included 
from the KeyRequest. A “yes” in Table 38-66 indicates the va lue for the field is included from its default location, 
identified in the source row, and a “request” indicates th e values for the field is included from its corresponding 
KeyRequest field. Opcode/
EAX = 01H
ENCLU[EGETKEY]IR V/V SGX1 This leaf function retrieves a cryptographic key.
IR EGETKEY (In) Return error code (Out) Address to a KEYREQUEST (In) Address of the OUTPUTDATA (In)
KEYREQUEST OUTPUTDATA
 Enclave read access  Enclave write access38-116 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Keys that permit the specification of a CPU or ISV's code's , or enclave configuration's SVNs have additional require-
ments. The caller may not request a key for an SVN beyond the current CPU, ISV or enclave configuration's SVN, 
respectively. 
Several keys are access controlled. Access to the Provisioning Key and Provisioning Seal key requires the enclave's 
ATTRIBUTES.PROVISIONKEY be set. The EINITTOKEN Ke y requires ATTRIBUTES.EINITTOKEN_KEY be set and 
SECS.MRSIGNER equal IA32_SGXLEPUBKEYHASH.
Some keys are derived based on a hardcode PKCS padding constant (352 byte string): HARDCODED_PKCS1_5_PADDING[15:0] := 0100H;HARDCODED_PKCS1_5_PADDING[2655:16] := SignExtend330Byte(-1); // 330 bytes of 0FFHHARDCODED_PKCS1_5_PADDING[2815:2656] := 2004000501020403650148866009060D30313000H;
Concurrency RestrictionsTable 38-66.  Key Derivation
Key Name Attributes Owner 
EpochCPU 
SVN ISV SVNISV 
PRODIDISVEXT
PRODIDISVFAM
ILYID MRENCLAVE MRSIGNER CONFIG
IDCONFIGS
VN RAND 
SourceKey 
Dependent ConstantY := 
SECS.ATTRIBUTES and 
SECS.MISCSELECT
andSECS.CET_ATTRIB
UTES;CR_SGX
OWNEREPOCHY := 
CPUSVN Register;R := 
Req.ISVSVN;SECS. 
ISVIDSECS.IS
VEXTPRODIDSECS.IS
VFAMILYIDSECS. 
MRENCLAVESECS. 
MRSIGNERSECS.CO
NFIGIDSECS.CO
NFIGSVNReq. 
KEYID
R := AttribMask & 
UTES;R := 
Req.CPUSVN;
EINITTOKEN Yes Request Yes Request Request Yes No No No Yes No No Request
Report Yes Yes Yes Yes No No No No Yes No Yes Yes Request
Seal Yes Request Yes Request Request Request Request Request Request Request Request Request RequestProvisioning Yes Request No Request Request Yes No No No Yes No No Yes
Provisioning 
SealYes Request No Request Request Request Request Request No Yes Request Request Yes
Table 38-67.  EGETKEY Return Value in RAX
 Error Code (see Table 38-4) Value Description
No Error 0 EGETKEY successful.SGX_INVALID_ATTRIBUTE The KEYREQUEST contains a KEYNAME for which the enclave is not authorized.SGX_INVALID_CPUSVN If KEYREQUEST.CPUSVN is an unsupported platforms CPUSVN value.SGX_INVALID_ISVSVN If KEYREQUEST software SVN (ISVSVN or CONFIGSVN) is greater than the 
enclave's corresponding SVN.
SGX_INVALID_KEYNAME If KEYREQUEST.KEYNAME is an unsupported value.
Table 38-68.  Base Concurre ncy Restrictions of EGETKEY
OUTPUTDATA [DS:RCX] ConcurrentVol. 3D 38-117INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EGETKEY Operational Flow
(* Make sure KEYREQUEST is properly aligned and inside the current enclave *)
IF ( (DS:RBX is not 512Byte aligned) or (DS:RBX is not within CR_ELRANGE) ) 
(* Make sure DS:RBX is an EPC ad dress and the EPC page is valid *)
IF ( (DS:RBX does not resolve to an EPC address) or (EPCM(DS:RBX).VALID = 0) ) 
(* Check page parameters for correctness *)
IF ( (EPCM(DS:RBX).PT ≠ PT_REG) or (EPCM(DS:RBX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or (EPC M(DS:RBX).PENDING = 1) or
(EPCM(DS:RBX).MODIFIED = 1) or (EPCM(DS:RBX).ENCLAVEADDRESS ≠ (DS:RBX & ~0FFFH) ) or (EPCM(DS:RBX).R = 0) ) 
THEN #PF(DS:RBX); 
FI;
(* Make sure OUTPUTDATA is properly aligned and inside the current enclave *)
IF ( (DS:RCX is not 16Byte aligned) or  (DS:RCX is not wi thin CR_ELRANGE) ) 
(* Make sure DS:RCX is an EPC ad dress and the EPC page is valid *)
IF ( (DS:RCX does not resolv e to an EPC address) or (EPCM(DS:RCX).VALID = 0) ) Table 38-69.  Additional Concur rency Restrictions of EGETKEY
EGETKEY KEYREQUEST 
[DS:RBX]Concurrent Concurrent Concurrent
OUTPUTDATA 
[DS:RCX]Concurrent Concurrent Concurrent
TMP_CURRENTSECS Address of the SECS for the currently executing enclave.
TMP_KEYDEPENDENCIES Temp space for key derivation.TMP_ATTRIBUTES 128 Temp Space for the calc ulation of the sealable Attributes.
TMP_ISVEXTPRODID 16 bytes Tem p Space for ISVEXTPRODID.
TMP_ISVPRODID 2 bytes Tem p Space for ISVPRODID.
TMP_ISVFAMILYID 16 bytes Tem p Space for ISVFAMILYID.
TMP_CONFIGID 64 bytes Temp Space for CONFIGID.
TMP_CONFIGSVN 2 bytes Temp Space for CONFIGSVN.TMP_OUTPUTKEY 128 Temp Space for the calculation of the key.38-118 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
IF (EPCM(DS:RCX).BLOCKED = 1) 
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM( DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or (EPCM(DS:RCX).PENDING = 1) or
(EPCM(DS:RCX).MODIFIED = 1) or  (EPCM(DS:RCX). ENCLAVEADDRESS ≠ (DS:RCX & ~0FFFH) ) or (EPCM(DS:RCX).W = 0) ) 
THEN #PF(DS:RCX); 
FI;
(* Verify RESERVED spaces in KEYREQUEST are valid *)
IF ( (DS:RBX).RESERVED ≠ 0) or (DS:RBX.KEYPOLICY.RESERVED ≠ 0) ) 
TMP_CURRENTSECS := CR_ACTIVE_SECS;(* Verify that CONFIGSVN & New Policy bits are not used if KSS is not enabled *)
IF ((TMP_CURRENTSECS.ATTRIBUTES.KSS == 0) AND ((DS:RBX.KEYPOLICY & 0x003C ≠ 0) OR (DS:RBX.CONFIGSVN > 0)))
(* Determine which enclave attributes that mu st be included in the key. Attributes that must always  be include INIT & DEBUG *)

FI;
REQUIRED_SEALING_MASK[127:0] := 00000000 00000000 00000000 00000003H;TMP_ATTRIBUTES := (DS:RBX.ATTRIBUTEMASK | REQUIR ED_SEALING_MASK) & TMP_CURRENTSECS.ATTRIBUTES;
(* Compute MISCSELECT fields to be included *)
TMP_MISCSELECT := DS:RBX.MISCMASK & TMP_CURRENTSECS.MISCSELECT
(* Compute CET_ATTRIBUTES fields to be included *)
THEN TMP_CET_ATTRIBUTES := DS:RBX.CET_ATTRIBUT ES_ MASK & TMP_CURRENTSECS.CET_ATTRIBUTES; FI;
TMP_KEYDEPENDENCIES := 0;
CASE (DS:RBX.KEYNAME)
SEAL_KEY:
IF (DS:RBX.CPUSVN is beyond current CPU configuration)
THEN
FI;IF (DS:RBX.ISVSVN > TMP_CURRENTSECS.ISVSVN)
THEN
RFLAGS.ZF := 1;RAX := SGX_INVALID_ISVSVN;GOTO EXIT;
FI;IF (DS:RBX.CONFIGSVN > TMP_CURRENTSECS.CONFIGSVN)
THEN
FI;
(*Include enclave identity?*)Vol. 3D 38-119INTEL® SGX INSTRUCTION REFERENCES
TMP_MRENCLAVE := 0;
IF (DS:RBX.KEYPOLICY.MRENCLAVE = 1)
THEN TMP_MRENCLAVE := TM P_CURRENTSECS.MRENCLAVE;
FI;(*Include enclave author?*)TMP_MRSIGNER := 0;IF (DS:RBX.KEYPOLICY.MRSIGNER = 1)
THEN TMP_MRSIGNER := TMP_CURRENTSECS.MRSIGNER;
FI;
(* Include enclave product family ID? *)    TMP_ISVFAMILYID := 0;    IF (DS:RBX.KEYP OLICY.ISVFAMILYID = 1)
        THEN TMP_ISVFAMILYI D := TMP_CURRENTSECS.ISVFAMILYID;
FI;
    (* Include enclave product ID? *)
    TMP_ISVPRODID := 0;    IF (DS:RBX.KEYPOLICY.NOISVPRODID = 0)        TMP_ISVPRODID := TMP_CURRENTSECS.ISVPRODID;
FI;
    (* Include enclave Config ID? *)
    TMP_CONFIGID := 0;    TMP_CONFIGSVN := 0;    IF (DS:RBX.KE YPOLICY.CONFIGID = 1)
        TMP_CONFIGID := TMP_CURRENTSECS.CONFIGID;
        TMP_CONFIGSVN := DS:RBX.CONFIGSVN; 
FI;
    (* Include enclave extended product ID? *)
    TMP_ISVEXTPRODID := 0;    IF (DS:RBX.KEYPOL ICY.ISVEXTPRODID = 1 )
        TMP_ISVEXTPRODID := TMP_CURRENTSECS.ISVEXTPRODID;
    FI;
//Determine values key is based on
TMP_KEYDEPENDENCIES.KEYNAME := SEAL_KEY;TMP_KEYDEPENDENCIES.ISVFAM ILYID := TMP_ISVFAMILYID;
TMP_KEYDEPENDENCIES. ISVEXTPRODID := TMP_ISVEXTPRODID;
TMP_KEYDEPENDENCIES.ISVP RODID := TMP_ISVPRODID;
TMP_KEYDEPENDENCIES.ISVSVN := DS:RBX.ISVSVN;TMP_KEYDEPENDENCIES.SGXOWNEREPOCH := CR_SGXOWNEREPOCH;TMP_KEYDEPENDENCIES.ATTRIBUTES := TMP_ATTRIBUTES;TMP_KEYDEPENDENCIES.ATTRIBUTESMASK := DS:RBX.ATTRIBUTEMASK;TMP_KEYDEPENDENCIES.MREN CLAVE := TMP_MRENCLAVE;
TMP_KEYDEPENDENCIES.MRSIGNER := TMP_MRSIGNER;TMP_KEYDEPENDENCIES.KEYID := DS:RBX.KEYID;TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES := CR_SEAL_FUSES;TMP_KEYDEPENDENCIES.CPUSVN := DS:RBX.CPUSVN;TMP_KEYDEPENDENCIES.PADDING := TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT := TMP_MISCSELECT;TMP_KEYDEPENDENCIES.MISCMASK := ~DS:RBX.MISCMASK;TMP_KEYDEPENDENCIES.KEYPOLICY := DS:RBX.KEYPOLICY;TMP_KEYDEPENDENCIES.CONF IGID := TMP_CONFIGID;38-120 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
TMP_KEYDEPENDENCIES.CONF IGSVN := TMP_CONFIGSVN;
THEN
TMP_KEYDEPENDENCIES.CET_ATTRIBUTES := TMP_CET_ATTRIBUTES;TMP_KEYDEPENDENCIES.CET_ATTRIBUTES _M ASK := DS:RBX.CET_ATTRIBUTES _MASK;
FI;BREAK;
REPORT_KEY:
//Determine values key is based onTMP_KEYDEPENDENCIES.KEYNAME := REPORT_KEY;TMP_KEYDEPENDENCIES.ISVFAMILYID := 0;TMP_KEYDEPENDENCIES. ISVEXTPRODID := 0;
TMP_KEYDEPENDENCIES.ISVPRODID := 0;TMP_KEYDEPENDENCIES.ISVSVN := 0;TMP_KEYDEPENDENCIES.SGXOWNER EPOCH := CR_SGXOWNEREPOCH;
TMP_KEYDEPENDENCIES.ATTRIBUTES := TMP_CURRENTSECS.ATTRIBUTES;
TMP_KEYDEPENDENCIES.ATTRIBUTESMASK := 0;TMP_KEYDEPENDENCIES.MRENCLAVE := TMP_CURRENTSECS.MRENCLAVE;
TMP_KEYDEPENDENCIES.MRSIGNER := 0;TMP_KEYDEPENDENCIES.KEYID := DS:RBX.KEYID;TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES := CR_SEAL_FUSES;TMP_KEYDEPENDENCIES.CPUSVN := CR_CPUSVN;TMP_KEYDEPENDENCIES.PADDING := HARDCODED_PKCS1_5_PADDING ;
TMP_KEYDEPENDENCIES.MISCSELECT := TMP_CURRENTSECS.MISCSELECT;TMP_KEYDEPENDENCIES.MISCMASK := 0;TMP_KEYDEPENDENCIES.KEYPOLICY := 0;TMP_KEYDEPENDENCIES.CONFIGID := TMP_CURRENTSECS.CONFIGID;
TMP_KEYDEPENDENCIES.CONFIGSVN := TMP_CURRENTSECS.CONFIGSVN;IF (CPUID.(EAX=12H, ECX=1):EAX[6] = 1)
THEN
TMP_KEYDEPENDENCIES.CET_ATTRIBUTES := TMP_CURRENTSECS.CET_ATTRIBUTES;
FI;BREAK;
EINITTOKEN_KEY:
(* Check ENCLAVE has EINITTOKEN Key capability *)IF (TMP_CURRENTSECS.ATTRIBUTES.EINITTOKEN_KEY = 0)
THEN 
FI;IF (DS:RBX.CPUSVN is beyond current CPU configuration)
THEN 
THEN
FI;Vol. 3D 38-121INTEL® SGX INSTRUCTION REFERENCES
(* Determine values key is based on *)
TMP_KEYDEPENDENCIES.KEYNAME := EINITTOKEN_KEY;TMP_KEYDEPENDENCIES.ISVFAMILYID := 0;TMP_KEYDEPENDENCIES. ISVEXTPRODID := 0;
TMP_KEYDEPENDENCIES.ISVPRODID := TMP_CURRENTSECS.ISVPRODID
TMP_KEYDEPENDENCIES.ISVSVN := DS:RBX.ISVSVN;TMP_KEYDEPENDENCIES.SGXOWNEREPOCH := CR_SGXOWNEREPOCH;TMP_KEYDEPENDENCIES.ATTRIBUTES := TMP_ATTRIBUTES;TMP_KEYDEPENDENCIES.ATTRIBUTESMASK := 0;TMP_KEYDEPENDENCIES.MRENCLAVE := 0;TMP_KEYDEPENDENCIES.MRSIGNER := TMP_CURRENTSECS.MRSIGNER;TMP_KEYDEPENDENCIES.KEYID := DS:RBX.KEYID; TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES := CR_SEAL_FUSES;TMP_KEYDEPENDENCIES.CPUSVN := DS:RBX.CPUSVN;TMP_KEYDEPENDENCIES.PADDING := TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT := TMP_MISCSELECT;TMP_KEYDEPENDENCIES.MISCMASK := 0;TMP_KEYDEPENDENCIES.KEYPOLICY := 0;TMP_KEYDEPENDENCIES.CONFIGID := 0;TMP_KEYDEPENDENCIES.CONFIGSVN := 0;IF (CPUID.(EAX=12H, ECX=1):EAX[6] = 1)
THEN
TMP_KEYDEPENDENCIES.CET_ATTRIBUTES := TMP_CET_ATTRIBUTES;TMP_KEYDEPENDENCIES.CET_ATTRIBUTES _MASK := 0;
FI;BREAK;
PROVISION_KEY: (* Check ENCLAVE has PROVISIONING capability *)
IF (TMP_CURRENTSECS.ATTRI BUTES.PROVISIONKEY = 0) 
THEN
THEN
THEN
FI;(* Determine values key is based on *)TMP_KEYDEPENDENCIES.KEYNAME := PROVISION_KEY;TMP_KEYDEPENDENCIES.ISVFAMILYID := 0;TMP_KEYDEPENDENCIES. ISVEXTPRODID := 0;
TMP_KEYDEPENDENCIES.ISVPRODID := TMP_CURRENTSECS.ISVPRODID;
TMP_KEYDEPENDENCIES.ISVSVN := DS:RBX.ISVSVN;TMP_KEYDEPENDENCIES.SGXOWNEREPOCH := 0;TMP_KEYDEPENDENCIES.ATTRIBUTES := TMP_ATTRIBUTES;38-122 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
TMP_KEYDEPENDENCIES.ATTRIBUTESMA SK := DS:RBX.ATTRIBUTEMASK;
TMP_KEYDEPENDENCIES.MRENCLAVE := 0;TMP_KEYDEPENDENCIES.MRSIGNER := TMP_CURRENTSECS.MRSIGNER;TMP_KEYDEPENDENCIES.KEYID := 0;TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES := 0;TMP_KEYDEPENDENCIES.CPUSVN := DS:RBX.CPUSVN;TMP_KEYDEPENDENCIES.PADDING := TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT := TMP_MISCSELECT;TMP_KEYDEPENDENCIES.MISCMASK := ~DS:RBX.MISCMASK;TMP_KEYDEPENDENCIES.KEYPOLICY := 0;TMP_KEYDEPENDENCIES.CONFIGID := 0;IF (CPUID.(EAX=12H, ECX=1):EAX[6] = 1)
THEN
FI;BREAK;
PROVISION_SEAL_KEY:
(* Check ENCLAVE has PROVISIONING capability *)IF (TMP_CURRENTSECS.ATTRI BUTES.PROVISIO NKEY = 0) 
THEN
THEN
THEN
FI;
(* Include enclave product family ID? *)    TMP_ISVFAMILYID := 0;    IF (DS:RBX.KEYPOLICY.ISVFAMILYID = 1)        THEN TMP_ISVFAMILYI D := TMP_CURRENTSECS.ISVFAMILYID;
FI;
FI;
    TMP_CONFIGID := 0;    TMP_CONFIGSVN := 0;    IF (DS:RBX.KEYPOLICY.CONFIGID = 1)        TMP_CONFIGID := TMP_CURRENTSECS.CONFIGID;Vol. 3D 38-123INTEL® SGX INSTRUCTION REFERENCES
FI;
    TMP_ISVEXTPRODID := 0;    IF (DS:RBX.KEYP OLICY.ISVEXTPRODID = 1)
    FI;
TMP_KEYDEPENDENCIES.KEYNAME := PROVISION_SEAL_KEY;TMP_KEYDEPENDENCIES.ISVFAM ILYID := TMP_ISVFAMILYID;
TMP_KEYDEPENDENCIES.ISVSVN := DS:RBX.ISVSVN;TMP_KEYDEPENDENCIES.SGXOWNEREPOCH := 0;TMP_KEYDEPENDENCIES.ATTRIBUTES := TMP_ATTRIBUTES;TMP_KEYDEPENDENCIES.ATTRIBUTESMASK := DS:RBX.ATTRIBUTEMASK;TMP_KEYDEPENDENCIES.MRENCLAVE := 0;TMP_KEYDEPENDENCIES.MRSIGNER := TMP_CURRENTSECS.MRSIGNER;TMP_KEYDEPENDENCIES.KEYID := 0;TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES := CR_SEAL_FUSES;TMP_KEYDEPENDENCIES.CPUSVN := DS:RBX.CPUSVN;TMP_KEYDEPENDENCIES.PADDING := TMP_CURRENTSECS.PADDING;

TMP_CONFIGSVN := DS:RBX.CONFIGSVN; 
FI;
    FI;
TMP_KEYDEPENDENCIES.MISCSELECT := TMP_MISCSELECT;TMP_KEYDEPENDENCIES.MISCMASK := ~DS:RBX.MISCMASK;TMP_KEYDEPENDENCIES.KEYPOLICY := DS:RBX.KEYPOLICY;TMP_KEYDEPENDENCIES.CONF IGID := TMP_CONFIGID;
TMP_KEYDEPENDENCIES.CONFIGSVN := TMP_CONFIGSVN;IF (CPUID.(EAX=12H, ECX=1):EAX[6] = 1)
THEN
FI;BREAK;
DEFAULT:
(* The value of KEYNAME is invalid *)RFLAGS.ZF := 1;RAX := SGX_INVALID_KEYNAME;GOTO EXIT:
ESAC;
(* Calculate the final derived key an d output to the address in RCX *)
TMP_OUTPUTKEY := derivekey(TMP_KEYDEPENDENCIES);DS:RCX[15:0] := TMP_OUTPUTKEY;RAX := 0;RFLAGS.ZF := 0;
EXIT:
RFLAGS.CF := 0;RFLAGS.PF := 0;RFLAGS.AF := 0;RFLAGS.OF := 0;RFLAGS.SF := 0;38-124 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
ZF is cleared if successful, otherwise ZF is set. CF, PF, AF, OF, SF are cleared.
If a memory operand effective addr ess is outside the current enclave.
If an effective address is not properly aligned.
If an effective address is outside the DS segment limit.If KEYREQUEST format is invalid.
If an effective address is not canonical.
If KEYREQUEST format is invalid.
#PF(error code) If a page fault occurs in accessing memory operands.Vol. 3D 38-125INTEL® SGX INSTRUCTION REFERENCES
EMODPE—Extend an EPC Page Permissions  
This leaf function extends the access rights associated wi th an existing EPC page in the running enclave. THE RWX 
bits of the SECINFO parameter are treated as a permission s mask; supplying a value that does not extend the page 
permissions will have no effect. This instruction leaf  can only be executed when inside the enclave. 
page. The table below provides additi onal information on the memory para meter of the EMODPE leaf function.
EMODPE Memory Parameter Semantics
EMODPE Faulting Conditions
EAX = 06H
ENCLU[EMODPE]IR V/V SGX2 This leaf function extends th e access rights of an existing EPC 
page.
IR EMODPE (In) Address of a SECINFO (In) Address of the destination EPC page (In)
The EPC page is locked by another thread. RBX does not contain an effective address in an EPC page in the running enclave.
The EPC page is not valid. RCX does not contain an effective address of an EPC page in the running enclave.SECINFO contains an invalid request.
Table 38-70.  Base Concurrency Restrictions of EMODPE
Table 38-71.  Additional Concurrency Restrictions of EMODPE
SECINFO [DS:RBX] Concurrent Concurrent Concurrent38-126 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EMODPE Operational Flow
IF ((DS:RBX is not within CR_ELRANGE) or (DS:RCX is not within CR_ELRANGE) )
IF ( (EPCM(DS:RBX).VALID = 0) or (EPCM( DS:RBX).R = 0) or (EPCM(DS:RBX).PENDING ≠ 0) or (EPCM(DS:RBX).MODIFIED ≠ 0) or
(EPCM(DS:RBX).BLOCKED ≠ 0) or (EPCM(DS:RBX).PT ≠ PT_REG) or (EPCM(DS:RBX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
(EPCM(DS:RBX).ENCLAVEADDRESS ≠ (DS:RBX & ~0xFFF)) )
IF (SCRATCH_SECINFO reserved fields are not zero ) 
(* Check security attributes of the EPC page *)
IF ( (EPCM(DS:RCX).VALID = 0)  or (EPCM(DS:RCX).PENDING ≠ 0) or (EPCM(DS:RCX).MODIFIED ≠ 0) or 
(EPCM(DS:RCX).BLOCKED ≠ 0) or (EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) )
(* Re-Check security attributes of the EPC page *)
(EPCM(DS:RCX).PT ≠ PT_REG) or (EPCM(DS:RCX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or
IF ( (EPCM(DS:RCX).R = 0) and (SCRATCH_SECINFO .FLAGS.R = 0) and (SCRATCH_SECINFO.FLAGS.W ≠ 0) ) 
THEN #GP(0); FI;Name Type Size (bits) Description
SCRATCH_SECINFO SECINFO 512 Scratch storage for holding the contents of DS:RBX.Vol. 3D 38-127INTEL® SGX INSTRUCTION REFERENCES
EPCM(DS:RCX).R := EPCM(DS:RCX) .R | SCRATCH_SECINFO.FLAGS.R;
EPCM(DS:RCX).W := EPCM(DS:RCX).W | SCRATCH_SECINFO.FLAGS.W;EPCM(DS:RCX).X := EPCM(DS:RCX) .X | SCRATCH_SECINFO.FLAGS.X;
None
If a memory operand effective addre ss is outside the DS segment limit.
#PF(error code) If a page fault occurs in accessing memory operands.38-128 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EREPORT—Create a Cryptograp hic Report of the Enclave 
This leaf function creates a cryptographic REPORT that descr ibes the contents of the enclave. This instruction leaf 
can only be executed when inside the enclave. The crypto graphic report can be used by other enclaves to deter-
mine that the enclave is running on the same platform.
RBX contains the effective address of the MRENCLAVE va lue of the enclave that will authenticate the REPORT 
output, using the REPORT key delivered by EGETKEY command for that enclave.  RCX contains the effective address 
of a 64-byte REPORTDATA structure, which allows the caller of the instruction to associate data with the enclave 
from which the instruction is called. RDX contains the addr ess where the REPORT will be output by the instruction.
EREPORT Memory Parameter Semantics
This instruction leaf perform the following: 
1. Validate the 3 operands (RBX, RCX, RDX) are inside the enclave.
2. Compute a report key for the target enclave, as indicated by the value located in RBX(TARGETINFO).
3. Assemble the enclave SECS data to complete the REPORT  structure (including the data provided using the RCX 
(REPORTDATA) operand).
4. Computes a cryptographic hash over REPORT structure.5. Add the computed hash to the REPORT structure.
6. Output the completed REPORT structur e to the address in RDX (OUTPUTDATA). 
The instruction fails if the operands are not properly aligned.CR_REPORT_KEYID, used to provide key wearout protection, is populated with a statistically unique value on boot 
of the platform by a trusted entity within the SGX TCB.
EREPORT Faulting ConditionsOpcode/
EAX = 00H
ENCLU[EREPORT]IR V/V SGX1 This leaf function creates a cryptographic report  of the enclave.
IR EREPORT (In)Address of TARGETINFO 
(In)Address of REPORTDATA 
(In)Address where the REPORT is 
written to in an OUTPUTDATA (In)
TARGETINFO REPORTDATA OUTPUTDATA
Read access by Enclave Read access by Enclave Read/Write access by Enclave 
An effective address not properly aligned. An memory address does not resolve in an EPC page.
If accessing an invalid EPC page. If the EPC page is blocked.May page fault.Vol. 3D 38-129INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EREPORT Operational Flow
(* Address verification for TARGETINFO (RBX) *)
IF ( (DS:RBX is not 512Byte Aligned) or (DS:RBX is not within CR_ELRANGE) )

EAX = 00H
Operation
IF (EPCM(DS:RBX).VALID = 0)
(EPCM(DS:RBX).MODIFIED = 1) or (EPCM(DS:RBX).ENCLAVEADDRESS ≠ (DS:RBX & ~0FFFH) ) or (EPCM(DS:RBX).R = 0) ) Table 38-72.  Base Concurre ncy Restrictions of EREPORT
EREPORT TARGETINFO [DS:RBX] Concurrent
Table 38-73.  Additional Concurrency Restrictions of EREPORT
REPORTDATA 
[DS:RDX]Concurrent Concurrent Concurrent
TMP_ATTRIBUTES  32 Physical address of SECS of  the enclave to which source operand belongs.
TMP_CURRENTSECS Address of the SECS for the currently executing enclave.TMP_KEYDEPENDENCIES Temp space for key derivation.
TMP_REPORTKEY  128 REPORTKEY generated by the instruction.
TMP_REPORT  371238-130 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
FI;
(* Verify RESERVED spaces in TARGETINFO are valid *)
IF (DS:RBX.RESERVED != 0)
(* Address verification for REPORTDATA (RCX) *)
IF ( (DS:RCX is not 128Byte Aligned) or  (DS:RCX is not within CR_ELRANGE) )
(EPCM(DS:RCX).MODIFIED = 1) or  (EPCM(DS:RCX). ENCLAVEADDRESS ≠ (DS:RCX & ~0FFFH) ) or (EPCM(DS:RCX).R = 0) ) 
FI;
(* Address verification for OUTPUTDATA (RDX) *)
IF ( (DS:RDX is not 512Byte Aligned) or (DS:RDX is not within CR_ELRANGE) )
IF (EPCM(DS:RDX).VALID = 0)
IF (EPCM(DS:RDX).BLOCKED = 1) 
IF ( (EPCM(DS:RDX).PT ≠ PT_REG) or (EPCM(DS:RDX).ENCLAVESECS ≠ CR_ACTIVE_SECS) or (EPCM(DS:RCX).PENDING = 1) or
(EPCM(DS:RCX).MODIFIED = 1) or  (EPCM(DS:RDX).ENCLAVEADDRESS ≠ (DS:RDX & ~0FFFH) ) or (EPCM(DS:RDX).W = 0) ) 
THEN #PF(DS:RDX); 
FI;
(* REPORT MAC needs to be  computed over data whic h cannot be modified *)
TMP_REPORT.CPUSV N := CR_CPUSVN;
TMP_REPORT.ISVFAMILYID := TMP_CURRENTSECS.ISVFAMILYID;TMP_REPORT.ISVEXTPRODID := TM P_CURRENTSECS.ISVEXTPRODID;
TMP_REPORT.ISVPRODID := TMP_CURRENTSECS.ISVPRODID;
TMP_REPORT.ISVSVN := TM P_CURRENTSECS.ISVSVN;
TMP_REPORT.ATTRIBUTES := TMP_CURRENTSECS.ATTRIBUTES;TMP_REPORT.REPORTDAT A := DS:RCX[511:0];
TMP_REPORT.MRENCLAVE := TMP_CURRENTSECS.MRENCLAVE;Vol. 3D 38-131INTEL® SGX INSTRUCTION REFERENCES
TMP_REPORT.MRSIGNER := TM P_CURRENTSECS.MRSIGNER;
TMP_REPORT.MRRESERVED := 0;TMP_REPORT.KEYID[255:0] := CR_REPORT_KEYID;TMP_REPORT.MISCSELECT := TMP_CURRENTSECS.MISCSELECT;TMP_REPORT.CONFIGID := TMP_CURRENTSECS.CONFIGID;
TMP_REPORT.CONFIGSVN := TMP_CURRENTSECS.CONFIGSVN;IF (CPUID.(EAX=12H, ECX=1):EAX[6] = 1)
THEN TMP_REPORT.CET_ATTRIBUTES := TMP_CURRENTSECS.CET_ATTRIBUTES; FI;
(* Derive the report key *)
TMP_KEYDEPENDENCIES.KEYNAME := REPORT_KEY;TMP_KEYDEPENDENCIES.ISVFAMILYID := 0;TMP_KEYDEPENDENCIES.ISVEXTPRODID := 0;TMP_KEYDEPENDENCIES.ISVPRODID := 0;TMP_KEYDEPENDENCIES.ISVSVN := 0;TMP_KEYDEPENDENCIES.SGXOWNER EPOCH := CR_SGXOWNEREPOCH;
TMP_KEYDEPENDENCIES.ATTRIBUTES := DS:RBX.ATTRIBUTES;TMP_KEYDEPENDENCIES.ATTRIBUTESMASK := 0;TMP_KEYDEPENDENCIES.MRENCLAV E := DS:RBX.M EASUREMENT;
TMP_KEYDEPENDENCIES.MRSIGNER := 0;TMP_KEYDEPENDENCIES.KEYID := TMP_REPORT.KEYID;TMP_KEYDEPENDENCIES.SEAL_KEY_FUSES := CR_SEAL_FUSES;TMP_KEYDEPENDENCIES.CPUSVN := CR_CPUSVN;TMP_KEYDEPENDENCIES.PADDING := TMP_CURRENTSECS.PADDING;
TMP_KEYDEPENDENCIES.MISCSELECT := DS:RBX.MISCSELECT;TMP_KEYDEPENDENCIES.MISCMASK := 0;TMP_KEYDEPENDENCIES.KEYPOLICY := 0;TMP_KEYDEPENDENCIES.CONFIGID := DS:RBX.CONFIGID;TMP_KEYDEPENDENCIES.CONFIG SVN := DS:RBX .CONFIGSVN;
THEN
TMP_KEYDEPENDENCIES.CET_ATTRIBUTES := DS:RBX.CET_ATTRIBUTES;TMP_KEYDEPENDENCIES.CET_ATTRIBUTES _MASK := 0;
FI;
(* Calculate the derived key*)
TMP_REPORTKEY := derivekey(TMP_KEYDEPENDENCIES);
(* call cryptographi c CMAC function, CMAC data are not including MAC&KEYID *)
TMP_REPORT.MAC := cmac(TMP_REP ORTKEY, TMP_REPORT[3071:0] );
DS:RDX[3455: 0] := TMP_REPORT;
None
If the address in RCS is ou tside the DS segment limit.
If a memory operand is not in the current enclave.
#PF(error code) If a page fault occurs in accessing memory operands.38-132 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
If RCX is non-canonical form.If a memory operand is not properly aligned.
#PF(error code) If a page fault occurs in accessing memory operands.Vol. 3D 38-133INTEL® SGX INSTRUCTION REFERENCES
ERESUME—Re-Enters an Enclave
The ENCLU[ERESUME] instruction resumes execution of an enclave that was interrupted due to an exception or 
interrupt, using the machine state previously stored in the SSA.
ERESUME Memory Parameter Semantics
The instruction faults if any of the following occurs: 
The following operations are performed by ERESUME:
•RSP and RBP are saved in the current SSA frame on EENTER and are automatically restored on EEXIT or an 
asynchronous exit due to any Interrupt event.
EENTER (see Section 40.2.3). 
•All code breakpoints that do not overlap with ELRANGE are also suppressed. If the entry is an opt-out entry, all code and data breakpoints that over lap with the ELRANGE are suppressed.Opcode/
EAX = 03H
ENCLU[ERESUME]IR V/V SGX1 This leaf function is used to re-enter an enclave after an inter-
rupt.
Op/En RAX RBX RCX
IR ERESUME (In) Address of a TCS (In) Address of AEP (In)
TCS
 Enclave read/write access
TCS pointed to by RBX is not valid or available or 
locked.Current 32/64 mode does not match the enclave mode in 
The SECS is in use by another enclave. Either of TCS-specified FS and GS segment is not a subset of the current DS 
segment.
Any one of DS, ES, CS, SS is not zero. If XSAVE available, CR4.OSXSAVE = 0, but SECS.ATTRIBUTES.XFRM ≠ 3.
CR4.OSFXSR ≠ 1. If CR4.OSXSAVE = 1, SECS.ATTRIBUTES.XFRM is not a subset of XCR0.
Offsets 520-535 of the XSAVE area not 0. The bit vector stored  at offset 512 of the XSAVE area must be a subset of 
SECS.ATTRIBUTES.XFRM.
The SSA frame is not valid or in use. If SECS.ATTRIBUTES.AEXNOTIFY ≠ TCS.FLAGS.AEXNOTIFY and 
TCS.FLAGS.DBGOPTIN = 0.38-134 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
— PEBS is suppressed.
— AnyThread counting on other threads is demoted to  MyThread mode and IA32_PERF_GLOBAL_STATUS[60] 
on that thread is set.
Operation
Temp Variables in ERESUME Operational Flow

Operation
IF (TMP_MODE64 = 0 and (DS not usable or ( ( DS[S ] = 1) and (DS[bit 11] = 0) and DS[bit 10] = 1))))Table 38-74.  Base Concurrency Restrictions of ERESUME
ERESUME TCS [DS:RBX] Shared #GP
Table 38-75.  Additional Concur rency Restrictions of ERESUME
ERESUME TCS [DS:RBX] Concurrent Concurrent Concurrent
TMP_FSBASE Effective Address 32/64 Prop osed base addre ss for FS segment.
TMP_GSBASE Effective Address 32/64 Prop osed base addre ss for FS segment.
TMP_FSLIMIT Effective Address 32/64 Highest legal address in proposed FS segment.
TMP_GSLIMIT Effective Address 32/64 Highest legal address in proposed GS segment.TMP_TARGET Effective Address 32/64 Address of first instruction inside enclave at which execution is to resume.
TMP_SECS Effective Address 32/64 Physical address of SECS for this enclave.
TMP_SSA Effective Address 32/64 Address of current SSA frame.TMP_XSIZE integer 64 Size of XSAVE area based on SECS.ATTRIBUTES.XFRM.
TMP_GPR Effective Address 32/64 Address of the GPR area within the current SSA frame.TMP_BRANCH_RECORD LBR Record From/to addre sses to be pushed onto the LBR stack.
TMP_NOTIFY Boolean 1 When set to 1,  deliver an AEX notification.Vol. 3D 38-135INTEL® SGX INSTRUCTION REFERENCES
THEN 
FI;
IF (TMP_MODE64 = 1 and (CS:RCX is not canonical))
IF ( (EPCM(DS:RBX).ENCLAVEADDRESS ≠ DS:RBX) or (EPCM(DS:RBX).PT ≠ PT_TCS))
IF ( ( (DS:RBX).OFSBASE is not 4KByte Aligned) or ( (DS:RBX).OGSBASE is not 4KByte Aligned))
(* Make sure that the FLAG S field in the TCS does not have any reserved bits set *)
IF (the enclave is not already initialized) 38-136 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
(* make sure the logical processor's operating mode matches the enclave *)
IF ( (TMP_MODE64 ≠ TMP_SECS.ATTRIBUTES.MODE64BIT))
THEN 
IF (TMP_SECS.AT TRIBUTES.XFRM ≠ 03H) THEN #GP(0); FI;
ELSE
IF ( (TMP_SECS.ATTR IBUTES.XFRM & XCR0) ≠ TMP_SECS.ATTRIBUTES.XFRM) THEN #GP(0); FI;
FI;
IF ( (DS:RBX).CSSA.FLAGS.DBGOPTIN = 0) and (DS:RBX).CSSA.FLAGS.AEXNOTIFY ≠ TMP_SECS.ATTRIBUTES.AEXNOTIFY))
(* Make sure the SSA contains at least one active frame *)
IF ( (DS:RBX).CSSA = 0) 
TMP_SSA := (DS:RBX).OSSA + TMP_SECS.BASEADDR + 4096 * TMP_SECS.SSAFRAMESIZE * ( (DS:RBX).CSSA - 1);TMP_XSIZE := compute_XSAVE_frame_ size(TMP_SECS.ATTRIBUTES.XFRM);
(* Check page is read/write accessible *)Check that DS:TMP_SSA_PAGE is read/write accessible; If a fault occurs, release locks,  abort and deliver that fault;
≠ DS:TMPSSA_PAGE) or (EPCM(DS:TMP_SSA_PAGE).PT ≠ PT_REG) or
ENDFOR
Check that DS:TMP_SSA_PAGE is read/write accessible; 
If a fault occurs, release locks, abort and deliver that fault;IF (DS:TMP_GPR does no t resolve to EPC page) 
IF (EPCM(DS:TMP_GPR).VALID = 0) Vol. 3D 38-137INTEL® SGX INSTRUCTION REFERENCES
(EPCM(DS:TMP_GPR).ENCLAVESECS ≠ EPCM(DS:RBX).ENCLAVESECS) or 
(EPCM(DS:TMP_GPR).R = 0) or (EPCM(DS:TMP_GPR).W = 0))THEN #PF(DS:TMP_GPR); FI;
THEN 
FI;
IF ((DS:RBX).FLAGS.AEXNOTIFY = 1) and (DS:TMP_GPR.AEXNOTIFY[0] = 1))
THEN
TMP_NOTIFY := 1;
ELSE
TMP_NOTIFY := 0;
FI;
IF (TMP_NOTIFY = 1)
THEN
IF ((DS:RBX).CSSA ≥ (DS:RBX).NSSA)
TMP_SSA := TMP_SSA + 4096 * TMP_SECS.SSAFRAMESIZE;
TMP_XSIZE := compute_XSAVE_frame_ size(TMP_SECS.ATTRIBUTES.XFRM);
FOR EACH TMP_SSA_PAGE = TMP_ SSA to TMP_SS A + TMP_XSIZE
IF ((EPCM(DS:TMP_SSA_PAGE).ENCLAVEADDRESS 
≠ DS:TMP_SSA_PAGE) or
(EPCM(DS:TMP_SSA_PAGE).ENCLAVESECS ≠ EPCM(DS:RBX).ENCLAVESECS) or
ENDFOR38-138 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
If a fault occurs; release locks, abort and deliver that fault;
IF (DS:TMP_GPR does not resolve to EPC page) 
IF ((EPCM(DS:TMP_GPR).PENDING = 1) or  (EPCM(DS:TMP_GPR).MODIFIED = 1))
IF ((EPCM(DS:TMP_GPR).ENCLAVEADDRESS ≠ DS:TMP_GPR) or
(EPCM(DS:TMP_GPR).R = 0) or (EPCM(DS:TMP_GPR).W = 0))
THEN 
FI;
CR_GPR_PA := Physical_Address (DS: TMP_GPR);TMP_TARGET := (DS:RBX).OENTRY + TMP_SECS.BASEADDR;
ELSE
TMP_TARGET := (DS:TMP_GPR).RIP;
FI;
THEN 
ELSE
FI;
(* Check proposed FS/GS segments fall within DS *)
THEN 
TMP_GSBASE := (DS:RBX).OGSBASE + TMP_SECS.BASEADDR;TMP_GSLIMIT := (DS:RBX).OGSBASE + TMP_SECS.BASEADDR + (DS:RBX).GSLIMIT;(* if FS wrap-aro und, make sure DS has no holes*)
IF (TMP_FSLIMIT < TMP_FSBASE)
THEN 
ELSE
THEN Vol. 3D 38-139INTEL® SGX INSTRUCTION REFERENCES
ELSE
FI;
ELSE
THEN
TMP_FSBASE := (DS:RBX).OFSBASE + TMP_SECS.BASEADDR;TMP_GSBASE := (DS:RBX).OGSBASE + TMP_SECS.BASEADDR;
ELSE

FI;
THEN 
ELSE
FI;
THEN 
THEN 
ELSE
ELSE
FI;
ELSE
THEN
ELSE
 TMP_FSBASE := DS:TMP_GPR.FSBASE; TMP_GSBASE := DS:TMP_GPR.GSBASE;
FI;IF ((TMP_FSBASE is not canonical) or (TMP_GSBASE is not canonical))
FI;
IF (DS:RBX.STATE = ACTIVE))
TMP_IA32_U_CET := 0
TMP_SSP := 0
THEN
IF ( CR4.CET = 0 ) 
THEN 
(* If part does not support CET or CET has not been enabled and enclave requires CET then fail *) IF (TMP_SECS.CET_ATTRIBUTES 
≠ 0 OR TMP_SECS.CET_LEG_BITMAP_OFFSET ≠ 0) #GP(0); FI; 
FI;(* If indirect branch tracking or shadow  stacks enabled but CET state save area is not 16B aligned then fail ERESUME *) 
IF (TMP_SECS.CET_ATTRIBUTES.SH _STK_EN = 1 OR TMP_SECS.CET_ATTRIBUTES.ENDBR_EN = 1) 
THEN 
IF (DS:RBX.OCETSSA is not 16B aligned) #GP(0); FI; 
FI;
IF (TMP_SECS.CET_ATTRIBUTES.SH_STK_EN OR TMP_SECS.CET_ATTRIBUTES.ENDBR_EN) 
THEN
(* Setup CET state from SECS, no te tracker goes to IDLE *) 
TMP_IA32_U_CET = TMP_SE CS.CET_ATTRIBUTES; 
IF (TMP_IA32_U_CET.LEG_IW_EN = 1 AND TMP_IA32_U_CET.ENDBR_EN = 1) 
THEN 
TMP_IA32_U_CET := TMP_IA32_U_CET + TMP_SECS.BASEADDR;TMP_IA32_U_CET := TMP_IA32_U_CET + TMP_SECS.CET_LEG_BITMAP_BASE; 
FI;
THEN
TMP_CET_SAVE_AREA = DS:RBX .OCETSSA + TMP_SECS.BASEADDR + (DS:RBX.CSSA) * 16;
ELSE
TMP_CET_SAVE_AREA = DS:RBX.OCETSSA + TMP_ SECS.BASEADDR + (DS:RBX.CSSA - 1) * 16;
FI;38-140 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
If fault occurs release locks, abort and deliver fault
IF ((DS:TMP_CET_SAVE_PAGE Does NOT RESOLVE TO EPC PAGE) OR  (EPCM(DS:TMP_CET_SAVE_PAGE).VALID = 0) OR  (EPCM(DS:TMP_CET_SAVE_ PAGE).PENDING = 1) OR 
 (EPCM(DS:TMP_CET_SAVE_PAGE).MODIFIED = 1) OR  (EPCM(DS:TMP_CET_SAVE_PAGE).BLOCKED = 1) OR  (EPCM(DS:TMP_CET_SAVE_PAGE).R = 0) OR  (EPCM(DS:TMP_CET_SAVE_PAGE).W = 0) OR  (EPCM(DS:TMP_CET_SAV E_PAGE).ENCLAVEADDRESS 
 (EPCM(DS:TMP_CET_SAVE_PAGE).PT ≠ PT_SS_REST) OR 
THEN 
#PF(DS:TMP_CET_SAVE_PAGE); 
FI;
THEN
THEN TMP_SSP = TCS.PREVSSP; FI;
ELSE
TMP_SSP = CR_CET_SAVE_AREA_PA.SSP TMP_IA32_U_CET.TRACKER = CR _CET_SAVE_AREA_PA.TRACKER; 
TMP_IA32_U_CET.SUPPRESS = CR _CET_SAVE_AREA_PA.SUPPRESS;
IF ( (TMP_MODE64 = 1 AND TMP_SSP is not canonical) OR
 (TMP_MODE64 = 0 AND (TMP_SSP & 0xFFFFFFFF00000000) 
≠ 0) OR
(TMP_SSP is not 4 byte aligned) OR(TMP_IA32_U_CET.TRACKER = WAIT_FOR_ENDBRAN CH AND TMP_IA32_U_CET.SUPPRESS = 1) OR
(CR_CET_SAVE_AREA_PA.Reserved 
≠ 0) ) #GP(0); FI;
FI;
FI;
FI;
IF (TMP_NOTIFY = 0)
THEN
(* SECS.ATTRIBUTES.XFRM selects the features to be saved. *)
(* CR_XSAVE_PAGE_n: A list of 1 or more physical address of pages that contain the XSAVE area. *)XRSTOR(TMP_MODE64, SECS.ATTRI BUTES.XFRM, CR_XSAVE_PAGE_n);
IF (XRSTOR failed with #GP) 
THEN
DS:RBX.STATE := INACTIVE;#GP(0);
FI;
FI;
CR_ACTIVE_SECS := TMP_SECS;CR_ELRANGE := (TMP_SECS.BASEADDR, TMP_SECS.SIZE);Vol. 3D 38-141INTEL® SGX INSTRUCTION REFERENCES
(* Save sate for possible AEXs *)
THEN
THEN 
FI;
FI;
RIP := TMP_TARGET;IF (TMP_NOTIFY = 1)
THEN
RCX := RIP;RAX := (DS:RBX).CSSA;(* Save the outside RSP and RBP so they can be restored on interrupt or EEXIT *)
DS:TMP_SSA.U_RSP := RSP; DS:TMP_SSA.U_RBP := RBP;
ELSE
Restore_GPRs from DS:TMP_GPR;
(*Restore the RFLAGS values from SSA*)
RFLAGS.CF := DS:TMP_GPR.RFLAGS.CF;RFLAGS.PF := DS:T MP_GPR.RFLAGS.PF;
RFLAGS.AF := DS:T MP_GPR.RFLAGS.AF;
RFLAGS.ZF := DS:T MP_GPR.RFLAGS.ZF;
RFLAGS.SF := DS:T MP_GPR.RFLAGS.SF;
RFLAGS.DF := DS:TMP_GPR.RFLAGS.DF;RFLAGS.OF := DS:T MP_GPR.RFLAGS.OF;
RFLAGS.NT := DS:TMP_GPR.RFLAGS.NT;RFLAGS.AC := DS:T MP_GPR.RFLAGS.AC;
RFLAGS.ID := DS:TMP_GPR.RFLAGS.ID;RFLAGS.RF := DS:T MP_GPR.RFLAGS.RF;
RFLAGS.VM := 0;IF (RFLAGS.IOPL = 3) 
THEN RFLAGS.IF := DS:T MP_GPR.RFLAGS.IF; FI;
IF (TCS.FLAGS.OPTIN = 0) 38-142 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
THEN RFLAGS.TF := 0; FI;
THEN
FI;
(* Pop the SSA stack*)
(DS:RBX).CSSA := (DS:RBX).CSSA -1;
FI;
GS.limit := DS:RBX.GSLIMIT;GS.type := 0001b;GS.W := DS.W;GS.S := 1;GS.DPL := DS.DPL;GS.G := 1;GS.B := 1;GS.P := 1;GS.AVL := DS.AVL;GS.L := DS.L;GS.unusable := 0;GS.selector := 0BH;
Suppress all code breakpoints that are outside ELRANGE;
THEN
Suppress all code breakpoints that overlap with ELRANGE;CR_SAVE_TF := RFLAGS.TF;RFLAGS.TF := 0;Suppress any MTF VM exits during execution of the enclave;Clear all pending debug exceptions;Clear any pending MTF VM exit;
ELSEVol. 3D 38-143INTEL® SGX INSTRUCTION REFERENCES
THEN
THEN pend a single-step #DB at the end of ERESUME; FI;
THEN pend an MTF VM exit at the end of ERESUME; FI;
ELSE
Clear all pending debug exceptions;Clear pending MTF VM exits;
FI;
FI;
THEN
(* Save enclosing application CET state into save registers *) CR_SAVE_IA32_U_CET := IA32_U_CET (* Setup enclave CET state *) IF CPUID.(EAX=07H, EC X=00h):ECX[CET_SS] = 1
THEN
CR_SAVE_SSP := SSP SSP := TMP_SSP;
FI; IA32_U_CET := TMP_IA32_U_CET;
FI;
(* Assure consiste nt translations *)
Flush_linear_context;Clear_Monitor_FSM;Allow_front_end_to_begin_fetch_at_new_RIP;
RFLAGS.TF is cleared on opt-out entry
If executed in enclave mode.If part or all of the FS or GS segment specified by TCS is outside the DS segment.
If any reserved field in the TCS FLAG is set.
If the target address is not within the CS segment.If CR4.OSFXSR = 0.
If CR4.OSXSAVE = 1and SECS.ATTRIBUTES.XFRM is not a subset of XCR0.If SECS.ATTRIBUTES.AEXNOTIFY 
≠ TCS.FLAGS.AEXNOTIFY and TCS.FLAGS.DBGOPTIN = 0.
a valid PT_REG EPC page.38-144 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
a valid PT_REG EPC page.Vol. 3D 38-145INTEL® SGX INSTRUCTION REFERENCES
38.5 INTEL® SGX VIRTUALIZATI ON LEAF FUNCTION REFERENCE
Leaf functions available with the ENCLV instruction mnemonic  are covered in this section. In general, each instruc-
tion leaf requires EAX to specify the leaf function index an d/or additional implicit registers specifying leaf-specific 
input parameters. An instruction operand encoding table provides details of ea ch implicit register usage and asso-

table.38-146 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EDECVIRTCHILD—Decrement VIRTCHILDCNT in SECS 
This instruction decrements the SECS VIRTCHILDCNT field.  This instruction can only be executed when current 
privilege level is 0.
EDECVIRTCHILD Memory Parameter Semantics
EDECVIRTCHILD Faulting Conditions
EAX = 00H
ENCLV[EDECVIRTCHILD]IR V/V EAX[5] This leaf function decrements the SECS VIRTCHILDCNT field.
IR EDECVIRTCHILD (In) Return error code (Out) Address of an enclave page (In) Address of an SECS page (In)
EPCPAGE SECS
A memory operand effective address is outside the DS segment 
limit (32b mode).A page fault occurs in a ccessing memory operands.
DS segment is unusable (32b mode). RBX does not refer to an enclave page (REG, TCS, TRIM, SECS).
A memory address is in a non-canonical form (64b mode). RCX does not refer to an SECS page.A memory operand is not properly aligned. RBX does no t refer to an enclave page  associated with SECS 
referenced in RCX.
Table 38-76.  Base Concurrency Restrictions of EDECVIRTCHILD
EDECVIRTCHILD Target [DS:RBX] Shared SGX_EPC_PAGE_
CONFLICT
SECS [DS:RCX] ConcurrentVol. 3D 38-147INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EDECVIRTCHILD Operational Flow
EDECVIRTCHILD Return Value in RAX
(* check alignment of DS:RBX *)
IF (DS:RBX is not 4K aligned) THEN    #GP(0); FI;
(* check DS:RBX is an linear  address of an EPC page *)
IF (DS:RBX does not reso lve within an EPC) THEN
    #PF(DS:RBX, PFEC.SGX); FI;
(* check DS:RCX is an linear address of an EPC page *)
    #PF(DS:RCX, PFEC.SGX); FI;
(* Check the EPCPAGE for concurrency *)
IF (EPCPAGE is being modified) THEN    RFLAGS.ZF = 1;    RAX = SGX_EPC_PAGE_CONFLICT;    goto DONE;FI;
(* check that the EPC page is valid *)
IF (EPCM(DS:RBX).VALID = 0) THEN    #PF(DS:RBX, PFEC.SGX); FI;
(* check that the EPC page has the correct type and that the back poin ter matches the pointer passed as the pointer to parent * )
IF ((EPCM(DS:RBX).PAGE_TYPE = PT_REG) or    (EPCM(DS:RBX).PAGE_TYPE = PT_TCS) orTable 38-77.  Additional Concurrency Restrictions of EDECVIRTCHILD
EDECVIRTCHILD Target [DS:RBX] Concurrent Concurrent Concurrent
TMP_SECS  Physical Address 64 Physical address of the SECS of the page being modified.
TMP_VIRTCHILDCNT Integer 64 Number of virtual child pages.
Error Value Description
No Error 0 EDECVIRTCHILD Successful.SGX_EPC_PAGE_CONFLICT Failure due to concurrent operation of another SGX instruction.
SGX_INVALID_COUNTER Attempt to decrem ent counter that is already zero.38-148 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
    (EPCM(DS:RBX).PAGE_TYPE = PT_TRIM) or
(EPCM(DS:RBX).PAGE_TYPE = PT_SS_FIRST) or(EPCM(DS:RBX).PAGE_TYPE = PT_SS_REST))
THEN
    (* get the SECS of DS:RBX *)    TMP_SECS := Addres s of SECS for (DS:RBX);
ELSE IF (EPCM(DS:RBX).PA GE_TYPE = PT_SECS) THEN
    (* get the physical address of DS:RBX *)    TMP_SECS := Physical_Address(DS:RBX);ELSE     (* EDECVIRTCHILD called on page of incorrect type *)
IF (TMP_SECS ≠ Physical_Address(DS:RCX)) THEN
    #GP(0); FI;
(* Atomically decrement virtchild counter and check for underflow *)
Locked_Decrement(SECS(TMP_SECS).VIRTCHILDCNT);IF (There was an underflow) THEN    Locked_Increment(SECS(TMP_SECS).VIRTCHILDCNT);    RFLAGS.ZF := 1;    RAX := SG X_INVALID_COUNTER;
    goto DONE;FI;
RAX := 0;
DONE:
(* clear flags *)RFLAGS.CF := 0;RFLAGS.PF := 0;RFLAGS.AF := 0;RFLAGS.OF := 0;RFLAGS.SF := 0;
ZF is set if EDECVIRTCHILD fails due to concurrent operat ion with another SGX instruction, or if there is a VIRT-
CHILDCNT underflow. Otherwise cleared.
RBX does not refer to an enclave page associated with SECS referenced in RCX.
If RBX does not refer to an enclave page (REG, TCS, TRIM, SECS).
If RCX does not refer to an SECS page.Vol. 3D 38-149INTEL® SGX INSTRUCTION REFERENCES
If a memory operand is not properly aligned.RBX does not refer to an enclave page associated with SECS referenced in RCX.
If RBX does not refer to an enclave page (REG, TCS, TRIM, SECS).If RCX does not refer to an SECS page.38-150 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
EINCVIRTCHILD—Increment VI RTCHILDCNT in SECS 
This instruction increments the SECS VIRTCHILDCNT field. This instruction can only be executed when the current 
The content of RCX is an effective address of an EPC pa ge. The DS segment is used to create a linear address. 
EINCVIRTCHILD Memory Parameter Semantics
EINCVIRTCHILD Faulting Conditions
EAX = 01H
ENCLV[EINCVIRTCHILD]IR V/V EAX[5] This leaf function increments the SECS VIRTCHILDCNT field.
IR EINCVIRTCHILD (In) Return error code (Out) Address of an enclave page (In) Address of an SECS page (In)
Table 38-78.  Base Concurrency Restrictions of EINCVIRTCHILD
EINCVIRTCHILD Target [DS:RBX] Shared SGX_EPC_PAGE_
CONFLICT
SECS [DS:RCX] ConcurrentVol. 3D 38-151INTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in EINCVI RTCHILD Operational Flow
EINCVIRTCHILD Return Value in RAX
IF ((EPCM(DS:RBX).PAGE_TYPE = PT_REG) or    (EPCM(DS:RBX).PAGE_TYPE = PT_TCS) or    (EPCM(DS:RBX).PAGE_TYPE = PT_TRIM) or
(EPCM(DS:RBX).PAGE_TYP E = PT_SS_FIRST) or
(EPCM(DS:RBX).PAGE_TYPE = PT_SS_REST))Table 38-79.  Additional Concurrency Restrictions of EINCVIRTCHILD
EINCVIRTCHILD Target [DS:RBX] Concurrent Concurrent Concurrent
No Error 0 EINCVIRTCHILD Successful.
SGX_EPC_PAGE_CONFLICT Failure due to concurrent operation of another SGX instruction.38-152 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
THEN

THEN
    (* get the physical address of DS:RBX *)    TMP_SECS := Physical_Address(DS:RBX);ELSE     (* EINCVIRTCHILD called on page of incorrect type *)
(* Atomically incremen t virtchild counter *)
Locked_Increment(SECS(TMP_SECS).VIRTCHILDCNT);
RAX := 0;
DONE:
ZF is set if EINCVIRTCHILD fails due to concurrent op eration with another SGX instruction; otherwise cleared.
If DS segment is unusable.If a memory operand is not properly aligned.
If RCX does not refer to an SECS page.
If RCX does not refer to an SECS page.Vol. 3D 38-153INTEL® SGX INSTRUCTION REFERENCES
ESETCONTEXT—Set the ENCLAV ECONTEXT Field in SECS 
The ESETCONTEXT leaf overwrites the ENCLAVECONTEXT field in the SECS. ECREATE and ELD of an SECS set the 
ENCLAVECONTEXT field in the SECS to  the address of the SECS (for acce ss later in ERDINFO). The ESETCONTEXT 
instruction allows a VMM to overwrite the default context value if necessary, for example, if the VMM is emulating 
ECREATE or ELD on behalf of the guest. 
The content of RCX is an effective addr ess of the SECS page to be updated, RDX contains the address pointing to 
the value to be stored in the SECS. Th e DS segment is used to create linear address. Segment override is not 
The instruction fails if: 
•The operand is not properly aligned.
•RCX does not refer to an SECS page.
ESETCONTEXT Memory Parameter Semantics
ESETCONTEXT Faulting Conditions
EAX = 02H
ENCLV[ESETCONTEXT]IR V/V EAX[5] This leaf function sets the ENCLAVECONTEXT field in SECS.
Op/En EAX RCX RDX
IR ESETCONTEXT (In) Return error code (Out)Address of the destination EPC page 
(In, EA)Context Value (In, EA)
EPCPAGE CONTEXT
Read access permitted by En clave Read/Write access permitted by Non Enclave
limit (32b mode).A memory operand is not properly aligned.
DS segment is unusable (32b mode). A page fault occurs in accessi ng memory operands.
Table 38-80.  Base Concurrenc y Restrictions of ESETCONTEXT
ESETCONTEXT SECS [DS:RC X] Shared SGX_EPC_PAGE_
CONFLICT38-154 Vol. 3DINTEL® SGX INSTRUCTION REFERENCES
Operation
Temp Variables in ESETCONTEXT Operational Flow
ESETCONTEXT Return Value in RAX
 (* check that EPCPAGE (DS:RCX) is the address of an EPC page *)
IF (DS:RCX does not reso lve within an EPC)THEN 
(* check alignment of the CONTEXT field (RDX) *)
IF (DS:RDX is not 8Byte Aligned) THEN    #GP(0); FI;
 (* Load CONTEXT into local variable *)
TMP_CONTEXT := DS:RDX
IF (EPC page is being modified) THEN    RFLAGS.ZF := 1;    RFLAGS.CF := 0;    RAX := SGX_EPC_PAGE_CONFLICT;    goto DONE;FI;
IF (EPCM(DS:RCX).VALID = 0) THEN    #PF(DS:RCX, PFEC.SGX);FI;
(* check EPC page is an SECS page *)Table 38-81.  Additional Concurrency Restrictions of ESETCONTEXT
ESETCONTEXT SECS [DS:RCX] Concurrent Concurrent Concurrent
TMP_CONTEXT CONTEXT 64 Data Value of CONTEXT.
No Error 0 ESETCONTEXT Successful.SGX_EPC_PAGE_CONFLICT Failure due to concur rent operation of another SGX instruction.Vol. 3D 38-155INTEL® SGX INSTRUCTION REFERENCES
IF (EPCM(DS:RCX).PT is not PT_SECS) THEN
    #PF(DS:RCX, PFEC.SGX);FI;
(* load the context value into SECS(DS:RCX).ENCLAVECONTEXT *)
SECS(DS:RCX).ENCLAVECONTEXT := TMP_CONTEXT;
RAX := 0;
DONE:
ZF is set if ESETCONTEXT fails due to concurrent oper ation with another SGX instruction; otherwise cleared.
CF, PF, AF, OF, and SF are cleared.
#PF(error code) If a page fault occurs in accessing memory operands.38-156 Vol. 3DINTEL® SGX INSTRUCTION REFERENCESVol. 3D 39-1INTEL® SGX INTERACTIONS WITH IA 32 AND INTEL® 64 ARCHITECTURE
CHAPTER 39
Intel® SGX provides Intel® Architecture with a collection of enclave instructions for creating protected execution 
environments on processors supporting IA32 and Intel® 64 architectures. These Intel SGX instructions are 
designed to work with legacy software and th e various IA32 and Intel 64 modes of operation.
39.1 INTEL® SGX AVAILABILITY  IN VARIOUS PROCESSOR MODES
The Intel SGX extensions (see Table 34-1) are available only  when the processor is executing in protected mode of 
operation. Additionally, the extensions are not available in System Management Mode (SMM) of operation or in 
Virtual 8086 (VM86) mode of operation. Finally, all leaf  functions of ENCLU and EN CLS require CR0.PG enabled.
The exact details of exceptions resulting from illegal mode s and their priority are listed in the reference pages of 
ENCLS and ENCLU.
39.2 IA32_FEATURE_CONTROL
IA32_FEATURE_CONTROL MSR provides tw o new bits related to two aspects of Intel SGX: using the instruction 
extensions and launch control configuration.
39.2.1 Availability of Intel SGX 
IA32_FEATURE_CONTROL[bit 18] allows BIOS to control the availability of Intel SGX extensions. For Intel SGX 
extensions to be available on a logical processor, bit 18 in the IA32_FEATURE_CONTROL MSR on that logical 
processor must be set, and IA32_FEATURE_CONTROL MSR on th at logical processor must be locked (bit 0 must be 
set). See Section 34.7.1 for additional details. OS is expect ed to examine the value of bit 18 prior to enabling Intel 
SGX on the thread, as the settings of  bit 18 is not reflected by CPUID.
39.2.2 Intel SGX Launch Control Configuration
The IA32_SGXLEPUBKEYHASHn MSRs used to configure author ized launch enclaves' MRSIGNER digest value. They 
are present on logical processors that support the coll ection of SGX1 leaf functions (i.e., CPUID.(EAX=12H, 
ECX=00H):EAX[0] = 1) and that CP UID.(EAX=07H, ECX=00H):ECX[30] = 1. IA32_FEATURE_CONTROL[bit 17] 
allows to BIOS to enable write access to these MSRs. If IA32_FEATURE_CONTROL.LE_WR (bit 17) is set to 1 and 
IA32_FEATURE_CONTROL is locked on that logical pr ocessor, IA32_SGXLEPUBKEYHASH MSRs on that logical 
processor are writeable. If this bit 17 is not set or  IA32_FEATURE_CONTROL is not locked, IA32_SGXLEPUBKEY-
HASH MSRs are read only. See Section 36.1.4 for additional details.
39.3 INTERACTIONS WITH SEGMENTATION
39.3.1 Scope of Interaction
Intel SGX extensions are available only when the processor is executing in a protected mode operation (see Section 
39.1 for Intel SGX availability in various processor modes) . Enclaves abide by all the segmentation policies set up 
by the OS, but they can be more restrictive than the OS.
Intel SGX interacts with segmentation at two levels: 
•The Intel SGX instruction (see the enclave instruction in Table 34-1).39-2 Vol. 3DINTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
•While executing inside an enclave (legacy instructions and enclave instructions permitted inside an enclave).
39.3.2 Interactions of Intel® SGX Instructions  with Segment, Operand, and Addressing 
Prefixes

Prefixes
All the memory operands used by the Intel SGX instructio ns are interpreted as offsets within the data segment 
(DS). The segment-override prefix on Intel SGX instructions is ignored.
Operand size is fixed for each enclave instruction. The op erand-size prefix is reserved, and results in a #UD excep-
tion if used.
All address sizes are determined by the operating mode of the processor. The address-size  prefix is ignored. This 
implies that while operating in 64-bit mode of operation, the address size is always 64 bits, and while operating in 
32-bit mode of operation, the address size is always 32 bits. Additionally, when operating in 16-bit addressing, 
memory operands used by enclave instructions use 32 bit addressing; the value of CS.D is ignored.
39.3.3 Interaction of Intel® SGX Instructions with Segmentation
All leaf functions of ENCLU and ENCLS instructions requir e that the DS segment be usable, and be an expand-up 
segment. Failing this check results in generation of a #GP(0) exception.
The Intel SGX leaf functions used for entering the en clave (ENCLU[EENTER] and EN CLU[ERESUME]) operate as 
follows:
•All usable segment registers except for FS and GS have a zero base. 
•The contents of the FS/GS segment registers (includi ng the hidden portion) is saved in the processor.
•New FS and GS values compatible with enclave security are loaded from the TCS
•The linear ranges and access rights available under the newly-loaded FS and GS must abide to OS policies by 
ensuring they are subsets of the linear-address ra nge and access rights available for the DS segment.
•The CS segment mode (64-bit, compatible, or 32 bit mo des) must be consistent with the segment mode for 
which the enclave was created, as indicated by the SE CS.ATTRIBUTES.MODE64 bit, and that the CPL of the 
logical processor is 3
An exit from the enclave either via ENCLU[EEXIT] or via an AEX restores the saved values of FS/GS segment regis-
ters.
39.3.4 Interactions of Enclave Execution with Segmentation
During the course of execution, enclave code abides by all segmentation policies as dictated by IA32 and Intel 64 
Architectures, and generates appropriate exceptions on violations.
Additionally, any attempt by software executing inside an  enclave to modify the processor's segmentation state 
(e.g., via MOV seg register, POP seg register, LDS, far jump, etc; excluding WRFSBASE/WRGSBASE) results in the 
generation of a #UD. See Section 36.6.1 for more information.
Upon enclave entry via the EENTER leaf function, FS is loaded from the (TCS.O FSBASE + SECS.BASEADDR) and 
TCS.FSLIMIT fields and GS is loaded from the (TCS.OGSBASE + SECS.BASEADDR) and TCS.GSLIMIT fields. 
Execution of WRFSBASE and WRGSBASE from inside a 64-bi t enclave is allowed. The processor will save the new 
values into the current SSA frame on an asynchronous exit (AEX) and restore them back on enclave entry via 
ENCLU[ERESUME] instruction.
39.4 INTERACTIONS WITH PAGING
Intel SGX instructions are available only when the processo r is executing in a protected mode of operation. Addi-
tionally, all Intel SGX leaf functions ex cept for EDBGRD and EDBGWR are availa ble only if paging is enabled. Any 
attempt to execute these leaf functions with paging disabl ed results in an invalid-opcode exception (#UD). As with Vol. 3D 39-3INTEL® SGX INTERACTIONS WITH IA 32 AND INTEL® 64 ARCHITECTURE
segmentation, enclaves abide by all the paging policies set up by the OS, but they can be more restrictive than the 
OS.
All the memory operands passed into Intel SGX instructions  are interpreted as offsets within the DS segment, and 
the linear addresses generated by combining these offsets with DS segment register are subject to paging-based 
access control if paging is enabled at the ti me of the execution of the leaf function.
Since the ENCLU[EENTER] and ENCLU[ERESUME] can only be executed when paging is enabled, and since paging 
cannot be disabled by software running inside an enclave (recall that enclaves always run with CPL = 3), enclave execution is always subject to paging-based access contro l. The Intel SGX access control itself is implemented as 
an extension to the existing paging modes. See Section 35.5 for details.
Execution of Intel SGX instructions may set accessed and dirty flags on accesses to EPC pages that do not fault 
even if the instruction later causes a fault for some other reason. 
39.5 INTERACTIONS WITH VMX
Intel SGX functionality (including SGX1 and SGX2) can be made available to software running in either VMX root 
operation or VMX non-root operation, as long as the pr ocessor is using a legal mode of operation (see Section 
39.1). 
A VMM has the flexibility to configure a VMCS to permit a gu est to use any subset of the ENCLS leaf functions. Avail-
ability of the ENCLU leaf functions in VMX non-root oper ation has the same requirement as ENCLU leaf functions 
outside of a virtualized environment.
Details of the VMCS control to allow VMM to configure supp ort of Intel SGX in VMX non-root operation is described 
in Section 39.5.1
39.5.1 VMM Controls to Configure Guest Support of Intel® SGX
Intel SGX capabilities are primarily exposed to the software via the CPUID instruction. VMMs can virtualize CPUID 
instruction to expose/hide this capability to/from guests.
Some of Intel SGX resources are exposed/controlled vi a model-specific registers (see Section 34.7). VMMs can 
virtualize these MSRs for the guests using the MSR bitmaps referenced by pointers in the VMCS.
The VMM can partition the Enclave Page Cache, and assign various partitions to (a subset of) its guests via the 
usual memory-virtualization techniques such as pa ging or the extended page table mechanism (EPT).
The VMM can set the “enable ENCLS exiting” VM-execution co ntrols to cause a VM exit when the ENCLS instruction 
is executed in VMX non-root operation. If the “enable ENCLS exiting” control is 0, all of the ENCLS leaf functions are 
permitted in VMX non-root operation. If the “enable ENCLS exiting” control is 1, execution of ENCLS leaf functions 
in VMX non-root operation is governed by consulting the bits in a new 64-bit VM-execution control field called the 
ENCLS-exiting bitmap (Each bit in the bitmap corresponds to an ENCLS leaf function with an EAX value that is iden-
tical to the bit’s position). When bits in the “ENCLS-exit ing bitmap” are set, attempts to execute the corresponding 
ENCLS leaf functions in VMX non-root operation causes VM  exits. The checking for these VM exits occurs immedi-
ately after checking that CPL = 0.
39.5.2 Interactions with the Exte nded Page Table Mechanism (EPT)
Intel SGX instructions are fully compatible with the extended page-table mechanism (EPT; see Section 29.3).
the linear addresses generated by combining these offsets wi th DS segment register are subject to paging and EPT. 
As with paging, enclaves abide by all the policies set up by the VMM.
The Intel SGX access control itself is implemented as an ex tension to paging and EPT, and may be more restrictive. 
See Section 39.4 for details of this extension.
An execution of an Intel SGX instruction may set acce ssed and dirty flags for EPT (when enabled; see Section 
29.3.5) on accesses to EPC pages that do not fault or cause VM exits even if the instruction later causes a fault or 
VM exit for some other reason. 39-4 Vol. 3DINTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
39.5.3 Interactions with APIC Virtualization
This section applies to Intel SGX in VMX non-root oper ation when the “virtualize APIC accesses” VM-execution 
A memory access by an enclave instruction that implicitly uses a cached physical address is never checked for 
overlap with the APIC-access page. Such accesses never cause APIC-access VM exits and are never redirected to 
the virtual-APIC page. Implicit  memory accesses can only be made to the SECS, the TCS, or the SSA of an enclave 
(see Section 35.5.3.2). 
An explicit Enclave Access (a linear memory access which is either from within an enclav e into its ELRANGE, or an 
access by an Intel SGX instruction that is expected to be in the EPC) that overlaps with the APIC-access page 
causes a #PF exception (APIC page is expected to be outside of EPC). 
Non-Enclave accesses made either by an Intel SGX instruct ion or by a logical processor inside an enclave to an 
address that without SGX would have caused redirection to the virtual-APIC page instead cause an APIC-access VM exit. 
Other than implicit accesses made by Intel SGX instructions, guest-physical and physical accesses are not consid-
ered “enclave accesses”; consequently, such accesses resu lt in undefined behavior if these accesses eventually 
reach EPC. This applies to any non-enclave physical accesses.
While a logical processor is executing inside an enclave, an attempt to execute an instruction outside of ELRANGE

While a logical processor is executing inside an enclave, an attempt to execute an instruction outside of ELRANGE 
results in a #GP(0), even if the linear address would tran slate to a physical address that overlaps the APIC-access 
page. 
39.5.4 Interactions with VT and SGX concurrency
In some cases, a VMM is required to handle conflicts be tween its own operation and a guest operation on EPC pages 
that are present in both guest and VMM address space. Th ese conflict would otherwise cause the guest to experi-
ence an unexpected behavior (vs. running directly on the h/w). These conflict cases are:
•ETRACK/ETRACKC failure due to Entry Epoch Object Lock conflict or reference tracking check failure.
•EPC Page Resource conflict.
A new exit reason is defined for all those cases: SGX_CONFL ICT (value 71). The VMCS exit qualification field details 
the specific case as follows:
This SGX_CONFLICT exiting behavior is controlled by a VM execution control called ENABLE_EPC_VIRTUALIZA-
TION_EXTENSIONS (bit 29 of the secondary processor control field).
Details for various SGX_CONFLICT VMEXIT cases are provided in the following sections.Table 39-1.  SGX Conflict Exit Qualification
Bits Size (bits) Name Description
15:0 16 Code Exit qualification code. The following values are defined:
0: TRACKING_RESOURCE_CONFLICT
1: TRACKING_REFERENCE_CONFLICT2: EPC_PAGE_CONFLICT_EXCEPTION
3: EPC_PAGE_CONFLICT_ERROR
Other: Reserved
31:16 16 Error Error code. Applicable only if the exit  qualification code is EPC_PAGE_CONFLICT_ERROR; 
contains the error code that would be returned in RAX if the instruction was executed on 
bare metal platform or if the ENABLE_E PC_VIRTUALIZATION_EXTE NSIONS bit in the 
secondary processor cont rol field is not set. In other cases this field is reserved as 0.
63:32 32 Reserved Always 0.Vol. 3D 39-5INTEL® SGX INTERACTIONS WITH IA 32 AND INTEL® 64 ARCHITECTURE
39.5.5 Virtual Child Tracking
SGX oversubscription support adds the ability to a ssociate virtual children with each enclave using the 
ENCLV[EINCVIRTCHILD] and ENCLV[EDECVIRTCHILD] instruct ions. The VMM enables checking of the virtual child 
count by EREMOVE and EWB in guests with a new VM ex ecution control called ENABLE_EPC_VIRTUALIZATION_EX-
TENSIONS.
When in VMX non-root operation and the ENABLE_EPC _VIRTUALIZATION_EXTENSIONS  control enabled, the 
following instructions change their behavior:
•EWB and EREMOVE return the SGX_CHILD_PRESENT error code if any virtual or physical children are 
associated with the enclave.
•ERDINFO set STATUS.CHILDPRESENT if any virtual or physical children are associated with the enclave.
39.5.6 Handling EPCM Entry Lock Conflicts
When performing paging within a VMM, it is possible for a contention on the EPC page to happen in the following 
case:
•The VMM performs an ELDB/ELDU/ELDB C/ELDUC of an enclave page, and th e guest attempts to perform some 
SGX instruction (e.g., EREMOVE) where th e same SECS parent page is required.
A similar conflict may occur if the VMM uses EINCVIRTCHIL D or EDECVIRTCHILD pointing to an SECS page. In all 
other cases where a SGX instruction executed by the VMM the applicable EPC page should not be mapped to the 
guest, thus no resource conflict occurs.
This conflicting situation can cause the guest's instructio n to fail and cause guest instability. To help the VMM 
manage such conflicts, the SGX VMM paging extensions in troduce a new VM-Exit that will be triggered whenever 
the guest encounters a resource conflict.
The exit reason is SGX_CONFLICT. The exit qualification field is used to distinguish the two kinds of resource 
conflicts:
•A value of EPCM_RESOURCE_CONFLICT_EXCEPTION (2) in th e exit qualification code field indicates that a 
resource conflict occurred that would result in a #GP. In th at case, the exit qualification error field is set to zero.
•A value of EPC_PAGE_CONFLICT_ERROR (3) in the exit qualification code field indicates that a resource conflict 
occurred that would result in an error code being return in RAX. In that case, the exit qualification error field is set to SGX_EPC_ PAGE_CONFLICT. 
The Guest Linear Address and Guest Physical Address fi elds are set to the guest linear and guest physical 
addresses respectively of the EPC page on which the co nflict occurred. The VMM may determine which instruction 
induced the exit by reading RAX. The exit also  populates the VM-exit instruction length field.
The VMM can determine whether the conflict may be due to its own operation, e.g., by setting a per-enclave busy 
indicator before executing ELD*, and clearing it afterwar ds. In that case, the VMM can handle an SGX Conflict 
(EPCM_PAGE_CONFLICT_*) exit by resuming guest executio n at the same instruction, allowing the guest to re-
execute the instruction. The VMM may also take steps to th rottle its own paging thread to reduce contention with 
the guest.
If the VMM determines that the conflict is not due to its own operation, it may inject a #GP (in case of EPC_PAGE_-
CONFLICT_EXCEPTION), or emulate an error code as the guest instruction would return (in case of EPC_PAGE_-
CONFLICT_ERROR) by setting ZF and copying the error va lue provided in the exit qualification to guest RAX.
To gracefully handle resource contention on the VMM side, the VMM should use the new ELDBC and ELDUC instruc-
tions. These are similar to ELDB and ELDU respectively, ex cept that on EPC resource contention they return an 
SGX_EPC_PAGE_CONFLICT error instead of issuing a #GP. In case of an error, the VMM can retry the instruction, 
possibly throttling the guest to assure progress.
When using EDECVIRTCHILD and EINCVIRTCHILD, the VMM sh ould preferably point to the enclave child page, not 
to the SECS page, avoiding re source conflict on the SECS. If the VMM choos es to point to the SECS page, it should 
handle conflicts in the same way as handling the ELD* case.39-6 Vol. 3DINTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
39.5.7 Context Tracking
The ENCLAVECONTEXT field in the SECS is available for use by the VMM to track context information associated 
with that enclave, such as the GPA of the SECS in the contex t of the appropriate guest. This field is initialized by the 
successful execution of ECREATE and ELD of an SECS page . The value stored in the ENCLAVECONTEXT field will be 
the translation of the target page address produced by paging (GPA in VMMs that have EPTs turned on). VMMs may 
override this default value by calling the ENCLV[ESETCONTEX T] instruction, which allows the VMM to store an arbi-
trary 64-bit value in the ENCLAVECONTEXT field. The V MM may later access the ENCLAVECONTEXT field by calling 
ENCLS[ERDINFO] on any member page of the enclave, including the SECS.
For nested virtualization cases, the lowest level VMM ca n make SGX oversubscription instructions higher level 
guest VMMs. In that case the lower level VMM can simply inject #GP to higher level VMMs when attempting to 
execute these instructions. 
However, if VMMs expose SGX oversubscription instruct ions to higher level VMMs, then VMMs have to use 
ENCLV[ESETCONTEXT] instruction to properly manage th e ENCLAVECONTEXT field of SECS during paging opera-
tions. That may involve emulating ECREATE, ELD, ESETCO NTEXT, and ERDINFO instructions apart from managing 
ENCLAVECONTEXT values.
39.6 INTEL® SGX INTERACTIONS WI TH ARCHITECTURALLY-VISIBLE EVENTS
All architecturally visible events (excep tions, interrupts, SMI, NMI, INIT, VM exit) can be detected while inside an 
enclave and will cause an asynchronous enclave exit if th ey are not blocked. Addition ally, INT3, and the SignalTX-
TMsg[SENTER] (i.e., GETSEC[SENTER]’s rendezvous ev ent message) events also cause asynchronous enclave 
exits. Note that SignalTXTMsg[SEX IT] (i.e., GETSEC[SEXIT]’s teardown message) does not cause an AEX. 
On an AEX, information about the event causing the AEX is stored in the SSA (see Section 37.4 for details of AEX). 
The information stored in the SSA only describes the first event that triggered the AEX. If parsing/delivery of the 
first event results in detection of further events (e.g., VM exit, double fault, etc.), then the event information in the 
SSA is not updated to reflect these subsequently detected events. 
39.7 INTERACTIONS WITH THE PROCESSOR EXTENDED STATE AND 
MISCELLANEOUS STATE
39.7.1 Requirements and Architecture Overview
Processor extended states are the ISA features that ar e enabled by the settings of CR4.OSXSAVE and the XCR0 
register. Processor extended states are normally saved/restored by software via XSAVE/XRSTOR instructions. 
Details of discovery of processor extended states and mana gement of these states are described in Chapter 13 of 
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. 
Additionally, the following requirements apply to Intel SGX:
•On an AEX, the Intel SGX architecture must protect the processor extended state and miscellaneous state by 
saving them in the enclave’s state-save area (SSA), and clear the secrets from the processor extended state 
that is used by an enclave.

that is used by an enclave. 
•Intel SGX architecture must verify that the SSA frame size  is large enough to contain all the processor extended 
states and miscellaneous state used by the enclave.
•Intel SGX architecture must ensure that enclaves can only use processor extended state that is enabled by 
system software in XCR0. 
•Enclave software should be able to discover only those processor extended state and miscellaneous state for 
which such protection is enabled.
•The processor extended states that are enabled inside the enclave must be approved by the enclave developer:
— Certain processor extended state (e.g., Memory Prot ection Extensions, see Appendix E, “Intel® Memory 
Protection Extensions,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1) Vol. 3D 39-7INTEL® SGX INTERACTIONS WITH IA 32 AND INTEL® 64 ARCHITECTURE
modify the behavior of th e legacy ISA software. If such features are enabled for enclaves that do not 
understand those features, then such a configuration co uld lead to a compromise of the enclave's security. 
•The processor extended states that are enabled inside th e enclave must form an inte gral part of the enclave's 
identity. This requirement has two implications:
— Service providers may decide to assign different trust level to the same enclave depending on the ISA 
features the enclave is using.
To meet these requirements, the Intel SGX architecture de fines a sub-field called X-Feature Request Mask (XFRM) 
in the ATTRIBUTES field of the SECS. On enclave creation  (ENCLS[ECREATE] leaf functi on), the required SSA frame 
size is calculated by the processor from the list of enab led extended and miscellaneous states and verified against 
the actual SSA frame size de fined by SECS.SSAFRAMESIZE. 
On enclave entry, after verifying that XFRM is only enablin g features that are already enabled in XCR0, the value in 
the XCR0 is saved internally by the processor, and is repl aced by the XFRM. On enclave exit, the original value of 
XCR0 is restored. Consequently, while inside the enclave,  the processor extended states enabled in XFRM are in 
enabled state, and those that are disabled in XFRM are in disabled state. 
The entire ATTRIBUTES field, including the XFRM subfield is  integral part of enclave's identity (i.e., its value is 
included in reports generated by ENCLU[EREPORT], and select bits from this field can be included in key-derivation 
for keys obtained via the ENCLU[EGETKEY] leaf function).
Enclave developers can create their enclave to work with certain features and fallback to another code path in case 
those features aren't available (e.g., optimize for AVX and fallback to SSE). For this purpose Intel SGX provides the 
following fields in SIGSTRUCT: AT TRIBUTES, ATTRIBUTESMASK, MISCSELECT , and MISCMASK. EINIT ensures that 
the final SECS.ATTRIBUTES and SECS.MISCSELECT comply wi th the enclave developer's requirements as follows:
SIGSTRUCT.ATTRIBUTES & SIGSTRUCT.ATTRIBUTEMASK  = SECS.ATTRIBUTES & SIGSTRUCT.ATTRIBUTEMASK
SIGSTRUCT.MISCSELECT & SIGSTRUCT.MISCMASK = SECS.MISCSELECT & SIGSTRUCT.MISCMASK.On an asynchronous enclave exit, the processor extended  states enabled by XFRM are saved in the current SSA 
frame, and overwritten by synthetic state (see Section 37.3  for the definition of the synthetic state). When the 
interrupted enclave is resumed via the ENCLU[ERESUME] leaf function, the saved state for processor extended 
states enabled by XFRM is restored.
39.7.2 Relevant Fields in  Various Data Structures
39.7.2.1  SECS.ATTRIBUTES.XFRM
The ATTRIBUTES field of the SECS data structure (see Section 35.7) contains a sub-field called XSAVE-Feature 
Request Mask (XFRM). Software populates this field at the time of enclave creation according to the features that 
are enabled by the operating system an d approved by the enclave developer.
Intel SGX architecture guarantees that during enclave exec ution, the processor extended state configuration of the 
processor is identical to what is required by the XFRM su b-field. All the processor extended states enabled in XFRM 
are saved on AEX from the enclave and restored on ERESUME.
The XFRM sub-field has the same layout as XCR0, and has consistency requirements that are similar to those for 
XCR0. Specifically, the consistency requirements on XFRM values depend on the processor implementation and the 
set of features enabled in CR4.
Legal values for SECS.ATTRIBUTES.XFRM conform to these requirements:
•XFRM[1:0] must be set to 0x3. 
•If the processor does not support XSAVE, or if the sy stem software has not enabled XSAVE, then XFRM[63:2] 
must be zero. 
•If the processor does support XSAVE, XFRM must contai n a value that would be legal if loaded into XCR0.
The various consistency requirements are enforced at different times in the enclave's life cycle, and the exact 
enforcement mechanisms are elaborated in Section 39.7.3 through Section 39.7.6.
On processors not supporting XSAVE, software should in itialize XFRM to 0x3. On pr ocessors supporting XSAVE, 
software should initialize XFRM to be a subset of XCR0 that would be present at the time of enclave execution. 39-8 Vol. 3DINTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
Because bits 0 and 1 of XFRM must always be set, the use of Intel SGX requires that SSE be enabled (CR4.OSFXSR 
= 1).
39.7.2.2  SECS.SSAFRAMESIZE
The SSAFRAMESIZE field in the SECS data structure sp ecifies the number of pages which software allocated1 for 
each SSA frame, including both the GPRSGX area, MISC ar ea, the XSAVE area (x87 and XMM states are stored in 
the latter area), and optionally padding between the MISC  and XSAVE area. The GPRSGX area must hold all the 
general-purpose registers and additional Intel SGX specif ic information. The MISC area must hold the Miscella-
neous state as specified by SECS.MISCSELECT, the XSAVE ar ea holds the set of processor extended states specified 
by SECS.ATTRIBUTES.XFRM (see Section 35.9 for the layo ut of SSA and Section 39.7.3 for ECREATE's consistency 
checks). The SSA is always in non-compacted format.
If the processor does not support XSAVE, the XSAVE area w ill always be 576 bytes; a copy of XFRM (which will be 
set to 0x3) is saved at offset 512 on an AEX.
If the processor does support XSAVE,  the length of the XSAVE area depends on SECS.ATTRIBUTES.XFRM. The 
length would be equal to what CPUID.(EAX=0DH, ECX= 0):EBX would return if XCR0 were set to XFRM. The 
following pseudo code illustrates how software can calculat e this length using XFRM as the input parameter without 
modifying XCR0:
offset = 576;
size_last_x = 0;
For x=2 to 63
IF (XFRM[x] != 0) Then
tmp_offset = CPUID.(EAX=0 DH, ECX= x):EBX[31:0];
IF (tmp_offset >= offset + size_last_x) Then
offset = tmp_offset;size_last_x = CPUID.(EAX=0DH, ECX= x):EAX[31:0];
FI;
FI;EndFor
return (offset + size_last_x); (*  compute_xsav e_size(XFRM) , see “ECREATE—Create an SECS page in the Enclave 
Page Cache”*)
Where the non-zero bits in XFRM are a subset of non-zero bit fields in XCR0.The size of the MISC region depends on the setting of SECS.MISCSELECT and can be calculated using the layout 
information described in Section 35.9.2
39.7.2.3  XSAVE Area in SSA
The XSAVE area of an SSA frame begins at offset 0 of the frame.
39.7.2.4  MISC Area in SSA
The MISC area of an SSA frame is positioned immediately before the GPRSGX region.
39.7.2.5  SIGSTRUCT Fields
Intel SGX provides the flexibility for an enclave developer to choose the enclave's code path according to the 
features that are enabled on the platform (e.g., optimi ze for AVX and fallback to SSE). See Section 39.7.1 for 
details.
1. It is the responsibility of the enclave to actually allocate this memory.Vol. 3D 39-9INTEL® SGX INTERACTIONS WITH IA 32 AND INTEL® 64 ARCHITECTURE
SIGSTRUCT includes the following fields:
SIGSTRUCT.ATTRIBUTES, SIGSTRUCT.ATTRIBUTEMASK, SIGSTRUCT.MISCSELECT, SIGSTRUCT.MISCMASK.
39.7.2.6  REPORT.ATTRIBUTES .XFRM and REPORT.MISCSELECT
The processor extended states and miscellaneous states that  are enabled inside the enclave form an integral part 
of the enclave's identity and are therefore included in the enclave's report, as provided by the ENCLU[EREPORT] 
leaf function. The REPORT structure includes th e enclave's XFRM and MISCSELECT configurations.
39.7.2.7  KEYREQUEST
An enclave developer can specify which bits out of XFRM  and MISCSELECT ENCLU[EGETKEY] should include in the 
derivation of the sealing key by specifying ATTRIB UTESMASK and MISCMASK in the KEYREQUEST structure.
39.7.3 Processor Extended States and ENCLS[ECREATE]
The ECREATE leaf function of the ENCLS instruction enforc es a number of consistency checks described earlier. The 
execution of ENCLS[ECREATE] leaf function resu lts in a #GP(0) in any of the following cases:
•SECS.ATTRIBUTES.XFRM[1:0] is not 3. 
•The processor does not support XSAVE and any of the following is true: 
— SECS.ATTRIBUTES.XFRM[63:2] is not 0.
—S E C S . S S A F R A M E S I Z E  i s  0 .
•The processor supports XSAVE and any of the following is true:

— XSETBV would fault on an attempt to load XFRM into XCR0. — XFRM[63]=1. 
— The SSAFRAME is too small to hold requir ed, enabled states (see Section 39.7.2.2).
39.7.4 Processor Extended States and ENCLU[EENTER]
39.7.4.1  Fault Checking
The EENTER leaf function of the ENCLU instruction en forces a number of consistency requirements described 
earlier. The execution of the ENCLU[EENTER] leaf functi on results in a #GP(0) in any of the following cases:
•If CR4.OSFXSR=0. 
•If The processor supports XSAVE and either of the following is true:
— CR4.OSXSAVE=0 and SECS.ATTRIBUTES.XFRM is not 3. 
— (SECS.ATTRIBUTES.XFRM & XCR0) != SECS.ATTRIBUTES.XFRM
39.7.4.2  State Loading
If ENCLU[EENTER] is successful, the current value of XCR0  is saved internally by th e processor and replaced by 
SECS.ATTRIBUTES.XFRM.39-10 Vol. 3DINTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
39.7.5 Processor Extend ed States and AEX
39.7.5.1  State Saving
On an AEX, processor extended states are saved into the XSAVE area of the SSA frame in a compatible format with 
XSAVE that was executed with EDX:EAX = SECS.ATTRIBUTES.XFRM, with the memory operand being the XSAVE 
area, and (for 64-bit enclaves) as if REX.W=1. The XSTATE _BV part of the XSAVE header  is saved with 0 for every 
bit that is 0 in XFRM. Other bits may be saved as 0 if the state saved is initialized.
Note that enclave entry ensures that if CR4.OSXSAVE is set to 0, then SECS.ATTRIBUTES.XFRM is set to 3. It 
should also be noted that it is not possibl e to enter an enclave with FXSAVE disabled. 
39.7.5.2  State Synthesis
After saving the extended state, the processor restores XCR0  to the value it held at the time of the most recent 
enclave entry.
The state of features corresponding to bits set in XFRM is synthesized. In general, these states are initialized. 
Details of state synthesis on AEX are documented in Section 37.3.1.
39.7.6 Processor Extended States and ENCLU[ERESUME]
39.7.6.1  Fault Checking
The ERESUME leaf function of the ENCLU instruction en forces a number of consistency requirements described 
earlier. Specifically, the ENCLU[ERESUME] leaf function  results in a #GP(0) in any of the following cases: 
•CR4.OSFXSR=0.
•The processor supports XSAVE and either of the following is true:
— (SECS.ATTRIBUTES.XFRM & XCR0) != SECS.ATTRIBUTES.XFRM.
A successful execution of ENCLU[ERESUME] loads state from  the XSAVE area of the SSA frame in a fashion similar 
to that used by the XRSTOR instruction. Data in the XSAVE area that would cause the XRSTOR instruction to fault 
will cause the ENCLU[ERESUME] leaf function to fault. Ex amples include, but are not restricted to the following:
•A bit is set in the XSTATE_BV field and clear in XFRM. 
•The required bytes in the header are not clear. 
•Loading data would set a reserved bit in MXCSR.
Any of these conditions will cause ERES UME to fault, even if CR4.OSXSAVE=0. 
39.7.6.2  State Loading
If ENCLU[ERESUME] is successful, the current value of XCR0  is saved internally by th e processor and replaced by 
State is loaded from the XSAVE area of the SSA fram e as if the XRSTOR instruction were executed with 
XCR0=XFRM, EDX:EAX = XFRM, with the memory operand be ing the XSAVE area, and (for  64-bit enclaves) as if 
REX.W=1. 
ENCLU[ERESUME] ensures that a subsequent execution of XS AVEOPT inside the enclave will operate properly (e.g., 
by marking all state as modified).
39.7.7 Processor Extended States and ENCLU[EEXIT]
The ENCLU[EEXIT] leaf function does not perform any X- feature specific consistency checks, nor performs any 
state synthesis. It is the responsibility of enclave software to clear any sensitive data from the registers before Vol. 3D 39-11INTEL® SGX INTERACTIONS WITH IA 32 AND INTEL® 64 ARCHITECTURE
executing EEXIT. However, successful execution of the ENCL U[EEXIT] leaf function restores XCR0 to the value it 
held at the time of the most recent enclave entry. 
39.7.8 Processor Extended States and ENCLU[EREPORT]
The ENCLU[EREPORT] leaf function creates the MAC-prot ected REPORT structure that reports on the enclave’s 
identity. ENCLU[EREPORT] includes in the report the values of SECS.ATTRIBUTES.XFRM and SECS.MISCSELECT.
39.7.9 Processor Extended States and ENCLU[EGETKEY]
The ENCLU[EGETKEY] leaf function returns a cryptographi c key based on the information provided by the KEYRE-
QUEST structure. Intel SGX pr ovides the means for isolation between differe nt operating conditions by allowing an 
enclave developer to select which bits out of XFRM and MI SCSELECT need to be included  in the derivation of the 
keys.
39.8 INTERACTIONS WITH SMM
39.8.1 Availability of Intel®  SGX instructions in SMM
Enclave instructions are not available in SMM, and any a ttempt to execute ENCLS or ENCLU instructions inside SMM 
results in an invalid-opcode exception (#UD).
39.8.2 SMI while Inside an Enclave
If the logical processor executing inside an enclave receiv es an SMI, the logical processor exits the enclave asyn-
chronously. The response to an SMI received while exec uting inside an enclave depends on whether the dual-
monitor treatment is enabled. For detailed discussion of  transfer to SMM, see Chapter 32, “System Management 
Mode‚” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C.
If the logical processor executing inside an enclave receiv es an SMI when dual-monitor treatment is not enabled, 
the logical processor exits the enclave asynchronously, and transfers the control to the SMM handler. In addition to 
saving the synthetic architectural state to the SMRAM Stat e Save Map (SSM), the logical processor also sets the 
“Enclave Interruption” bit in the SMRAM SSM (bit position 1 in SMRAM field at offset 7EE0H). 
If the logical processor executing inside an enclave receiv es an SMI when dual-monitor treatment is enabled, the 
logical processor exits the enclave asynchronously, and transfers the control to the SMM monitor via SMM VM exit. 
The SMM VM exit sets the “Enclave Interruption” bit in th e Exit Reason (see Table 39-2) and in the Guest Interrupt-
ibility State field (see Table 39-3) of the SMM VMCS.
39.8.3 SMRAM Synthetic State of AEX Triggered by SMI
All processor registers saved in the SMRAM have the same synthetic values listed in Section 37.3. Additional SMRAM fields that are treated specially on SMI are:
Table 39-2.  SMRAM Synthetic States on Asynchronous Enclave Exit
Position Field Value Writable
SMRAM Offset 07EE0H.Bit 1 ENCLAVE_INTERRUPTION Set to 1 if exit occurred in enclave mode No39-12 Vol. 3DINTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
39.9 INTERACTIONS OF INIT, SIPI, AND WAIT-FOR-SIPI WITH INTEL® SGX
INIT received inside an enclave, while the logical processo r is not in VMX operation, causes the logical processor to 
exit the enclave asynchronously. After the AEX, the processo r's architectural state is initialized to “Power-on” state 
(Table 9.1 in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). If the logical processor 
is BSP, then it proceeds to execute the BIOS initialization code. If the logical processor is an AP, it enters wait-for-
SIPI state. 
INIT received inside an enclave, while the logical proce ssor (LP) is in VMX root operation, follows regular Intel 
Architecture behavior and is blocked.
INIT received inside an enclave, while the logical proce ssor is in VMX non-root operation, causes an AEX. Subse-
quent to the AEX, the INIT causes a VM exit with the En clave Interruption bit in the exit-reason field in the VMCS. 
A processor cannot be inside an enclave in the wait-for-S IPI state. Consequently, a SIPI received while inside an 
enclave is lost.
Intel SGX does not change the behavior of the processor in the wait-for-SIPI state.The SGX-related processor states after INIT-SIPI-SIPI is as follows:
•EPC Settings: Unchanged
•EPCM: Unchanged
•CPUID.LEAF_12H.*: Unchanged
•ENCLAVE_MODE: 0 (LP exits enclave asynchronously)
•MEE state: Unchanged
Software should be aware that following INIT-SIPI-SIPI, the EPC might contain valid pages and should take appro-
priate measures such as initialize th e EPC with the EREMOVE leaf function. 
39.10 INTERACTIONS WITH DMA
DMA is not allowed to access any Processor Reserved Memory.
39.11 INTERACTIONS WITH TXT
39.11.1 Enclaves Created Prior to Execution of GETSEC
Enclaves which have been created before the GETSEC[SENTER] leaf function are available for execution after the 
successful completion of GETSEC[SENTER] and the corresp onding SINIT ACM. Actions that a TXT Launched Envi-
ronment performs in preparation to execute code in the Launched Environment, also applies to enclave code that 
would run after GETSEC[SENTER].
39.11.2 Interaction of GETSEC with Intel® SGX
All leaf functions of the GETSEC instruct ion are illegal inside an enclave, and results in an invalid-opcode exception 
(#UD).

(#UD).
Responding Logical Processors (RLP) which are executing inside an enclave at the time a GETSEC[SENTER] event 
occurs perform an AEX from the enclave and then enter the Wait-for-SIPI state. 
RLP executing inside an enclave at the time of GETSEC[S EXIT], behave as defined fo r GETSEC[SEXIT]-that is, the 
RLPs pause during execution of SEXIT and resume after the completion of SEXIT.
The execution of a TXT launch does not affect In tel SGX configuration or security parameters.Vol. 3D 39-13INTEL® SGX INTERACTIONS WITH IA 32 AND INTEL® 64 ARCHITECTURE
39.11.3 Interactions with Authenticated Code Modules (ACMs)
Intel SGX only allows launching ACMs with an Intel SGX SVN that is at the same level or higher than the expected 
Intel SGX SVN. The expected Intel SGX SVN is specified by  BIOS and locked down by the processor on the first 
successful execution of an Intel SGX instruction that doesn’ t return an error code. Intel SGX provides interfaces for 
system software to discover whether a non faulting Intel SGX instruction has been executed, and evaluate the suit-
ability of the Intel SGX SVN value of any ACM that is  expected to be launched by the OS or the VMM. 
These interfaces are provided through a read-only MSR called the IA32_SGX_SVN_STATUS MSR (MSR address 
500h). The IA32_SGX_SVN_STATUS MSR has the format shown in Table 39-3.
OS/VMM that wishes to launch an architectural ACM such as SINIT is expected to read the IA32_SGX_SVN_STATUS 
MSR to determine whether the ACM can be launched or a new ACM is needed:
•If either the Intel SGX SVN of the ACM is greater th an the value reported by IA32_SGX_SVN_STATUS, or the 
lock bit in the IA32_SGX_SVN_STATUS is not set,  then the OS/VMM can safely launch the ACM.
•If the Intel SGX SVN value reported in the correspondi ng component of the IA32_SGX_SVN_STATUS is greater 
than the Intel SGX SVN value in the ACM's header, an d if bit 0 of IA32_SGX_SVN_STATUS is 1, then the 
OS/VMM should not launch that version of the ACM. It sh ould obtain an updated version of the ACM either from 
the BIOS or from an external resource. 
However, OSVs/VMMs are strongly advised to update their version of the ACM any time they detect that the Intel 
SGX SVN of the ACM carried by the OS/VMM is lower than  that reported by IA32_SGX_SVN_STATUS MSR, irrespec-
tive of the setting of the lock bit.
39.12 INTERACTIONS WITH CACHING OF LINEAR-ADDRESS TRANSLATIONS 
Entering and exiting an enclave causes the logical processor to flush all the global linear-address context as well as 
the linear-address context associated with the current VPID and PCID. The MONITOR FSM is also cleared.
39.13 INTERACTIONS WITH INTEL®  TRANSACTIONAL SYNCHRONIZATION 
EXTENSIONS (INTEL® TSX)
1. ENCLU or ENCLS instructions inside an HLE region will  cause the flow to be aborted and restarted non-specula-
tively. ENCLU or ENCLS instructions inside an RTM region will cause the flow to be aborted and transfer control to 
the fallback handler.
2. If XBEGIN is executed inside an enclave, the processor does NOT check whether the address of the fallback 
handler is within the enclave.
3. If an RTM transaction is executing inside an enclave and there is an attempt to fetch an instruction outside the 
enclave, the transaction is aborted and control is tran sferred to the fallback handler. No #GP is delivered.Table 39-3.  Layout of the IA32_SGX_SVN_STATUS MSR
Bit Position Name ACM Module ID Value
0 Lock N.A. • If 1, indicates that a non-faulting Intel SGX instruction has been 
executed, consequently, launching a properly signed ACM but with Intel SGX SVN value less than the BIOS specified Intel SGX SVN threshold 
would lead to an TXT shutdown. 
• If 0, indicates that the processor will allow a properly  signed ACM to 
launch irrespective of the Intel SGX SVN value of the ACM.
15:1 RSVD N.A. 023:16 SGX_SVN_SINIT SINIT AC M • If CPUID.01H:ECX.SMX =1, this field reflects the expected threshold of 
Intel SGX SVN for the SINIT ACM. 
• If CPUID.01H:ECX.SMX =0, this field is reserved (0).
63:24 RSVD N.A. 039-14 Vol. 3DINTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
4. If an RTM transaction is executing inside an enclave and there is a data access to an address within the enclave 
that denied due to EPCM content (e.g., to a page belong ing to a different enclave), the transaction is aborted and 
control is transferred to the fallback handler. No #GP is delivered.
5. If an RTM transaction executing inside an enclave abor ts and the address of the fallback handler is outside the 
enclave, a #GP is delivered after the abort (EIP  reported is that of the fallback handler).
39.13.1 HLE and RTM Debug
RTM debug will be suppressed on opt-out enclave entry. After opt-out entry, the logical processor will behave as if 
IA32_DEBUG_CTL[15]=0. Any #DB detected inside an RTM transaction region will just cause an abort with no 
exception delivered. 
After opt-in entry, if either DR7[11] = 0 OR IA32_DEBU GCTL[15] = 0, any #DB or #BP detected inside an RTM 
transaction region will just cause an abort with no exception delivered. 
After opt-in entry, if DR7[11] = 1 AND IA32_DEBUGCTL[15 ] = 1, any #DB or #BP detected inside an RTM transla-
tion will 
•terminate speculative execution, 
•set RIP to the address of the XBEGIN instruction, and 
•be delivered as #DB (implying an Intel SGX AEX; any #BP is converted to #DB). 
•DR6[16] will be cleared, indicating RTM debug (if the #DB causes a VM exit, DR6 is not modified but bit 16 of 
the pending debug exceptions field in the VMCS will be set).
39.14 INTEL® SGX INTERA CTIONS WITH S STATES
Whenever an Intel SGX enabled processor enters S3-S5 state,  enclaves are destroyed. This is due to the EPC being 
destroyed when power down occurs. It is the application ru ntime’s responsibility to re-instantiate an enclave after 
a power transition for which the enclaves were destroyed.
39.15 INTEL® SGX INTERACTIONS WITH  MACHINE CHECK ARCHITECTURE (MCA)
39.15.1 Interactions with MCA Events
All architecturally visible machine check events (#MC and CM CI) that are detected while inside an enclave cause an 
asynchronous enclave exit.
Any machine check exception (#MC) that occurs after Intel SGX is first enables causes Intel SGX to be disabled, 
(CPUID.SGX_Leaf.0:EAX[SGX1] == 0). It cann ot be enabled until after the next reset.
39.15.2 Machine Check Enables (IA32_MCi_CTL)
All supported IA32_MCi_CTL bits for all the machine ch eck banks must be set for Intel SGX to be available 
(CPUID.SGX_Leaf.0:EAX[SGX1] == 1). Any act of clearing bi ts from '1 to '0 in any of the IA32_MCi_CTL register 
may disable Intel SGX (set CPUID.SGX_Leaf.0 :EAX[SGX1] to 0) until the next reset.
39.15.3 CR4.MCE
CR4.MCE can be set or cleared with no interactions with Intel SGX.Vol. 3D 39-15INTEL® SGX INTERACTIONS WITH IA 32 AND INTEL® 64 ARCHITECTURE
39.16 INTEL® SGX INTERACTIONS WITH PROTECTED MODE VIRTUAL 
ENCLS[EENTER] modifies neither EFLAGS.VIP nor EFLAGS.VIF.
ENCLS[ERESUME] loads EFLAGS in a manner  similar to that of an execution of IRET with CPL = 3. This means that 
ERESUME modifies neither EFLAGS.VIP nor EFLAGS.VIF re gardless of the value of th e EFLAGS image in the SSA 
frame. 
AEX saves EFLAGS.VIP and EFLAGS.VIF unmodified into the EFLAGS image in the SSA frame. AEX modifies neither 
EFLAGS.VIP nor EFLAGS.VIF after saving EFLAGS. 
If CR4.PVI = 1, CPL = 3, EFLAGS.VM = 0, IOPL < 3, EFLAGS.VIP = 1, and EFLAGS.VIF = 0, execution of STI causes 
a #GP fault. In this case, STI modifies neither EFLAGS.I F nor EFLAGS.VIF. This behavior applies without change 
within an enclave (where CPL is always 3). Note that, if IOPL = 3, STI always sets EFLAGS.IF without fault; 
CR4.PVI, EFLAGS.VIP, and EFLAGS.VIF are neit her consulted nor modified in this case. 
39.17 INTEL SGX INTERACTIO N WITH PROTECTION KEYS
SGX interactions with PKRU are as follows:
•CPUID.(EAX=12H, ECX=1):ECX.PKRU indicates whethe r SECS.ATTRIBUTES.XFRM.PKRU can be set. If 
SECS.ATTRIBUTES.XFRM.PKRU is set, then PKRU is saved and cleared as part of AEX and is restored as part of 
ERESUME. If CR4.PKE is set, an enclave can ex ecute RDPKRU and WRKRU independent of whether 
SECS.ATTRIBUTES.XFRM.PKRU is set.
SGX interactions with domain permission checks are as follows:
1) If CR4.PKE is not set, then legacy and SGX permission checks are not effected.
2) If CR4.PKE is set, then domain permission ch ecks are applied to all non-enclave access and 
enclave accesses to user pages in addition to legacy and SGX permission checks at a higher 
priority than SGX permission checks.
3) Implicit accesses aren't subject to domain permission checks.39-16 Vol. 3DINTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTUREVol. 3D 40-1ENCLAVE CODE DEBUG AND PROFILING
CHAPTER 40
Intel® SGX is architected to provide protection for production enclaves and permit enclave code developers to use

CHAPTER 40
Intel® SGX is architected to provide protection for production enclaves and permit enclave code developers to use 
an SGX-aware debugger to effectively debug a non-producti on enclave (debug enclave). Intel SGX also allows a 
non-SGX-aware debugger to debug non-enclave portions of  the application without getting confused by enclave 
40.1 CONFIGURATION AND CONTROLS
40.1.1 Debug Enclave vs. Production Enclave
The SECS of each enclave pr ovides a bit, SECS.ATTRIBUTES.DEBUG, in dicating whether the enclave is a debug 
enclave (if set) or a production enclave (if 0). If th is bit is set, software outside the enclave can use 
EDBGRD/EDBGWR to access the EPC memory of the enclave.  The value of DEBUG is no t included in the measure-
ment of the enclave and therefore doesn't require an al ternate SIGSTRUCT to be generated to debug the enclave.
The ATTRIBUTES field in the SECS is reported in the enclave's attestation, and is included in the key derivation. 
Enclave secrets that were protected by the enclave using Intel SGX keys when it ran as a production enclave will 
not be accessible by the debug enclave. A debugger ne eds to be aware that special debug content might be 
required for a debug enclave to run in a meaningful way. 
EPC memory belonging to a debug enclave can be accesse d via the EDBGRD/EDBGWR leaf functions (see Section 
38.4), while that belonging to a non-debug enclav e cannot be accessed by these leaf functions.
40.1.2 Tool-Chain Opt-in
The TCS.FLAGS.DBGOPTIN bit controls interactions of cert ain debug and profiling featur es with enclaves, including 
code/data breakpoints, TF, RF, monitor trap flag, BTF, LBRs, BTM, BTS, Intel Processor Trace, and performance 
monitoring. This bit is forced to zero when EPC pages ar e added via EADD. A debugger can set this bit via EDBGWR 
to the TCS of a debug enclave.
An enclave entry through a TCS with the TCS.FLAGS.DBGOPTIN set to 0 is called an opt-out entry . Conversely, an 
enclave entry through a TCS with TCS.FLAGS.DBGOPTIN set to 1 is called an opt-in entry .
40.1.3 Debugging an Enclave That Uses  Asynchronous Enclave Exit Notify
Whenever an opt-in enclave entry is used to perform encl ave code debugging or profi ling, the debugger or profiling 
tool may clear TCS.FLAGS.AEXNOTIFY to prevent AEX notifi cations from being delivered at each interrupt, break-
point, trap, or other exception.
40.2 SINGLE STEP DEBUG
40.2.1 Single Stepping ENCLS Instruction Leafs
If the RFLAGS.TF bit is set at the beginning of ENCLS, th en a single-step debug exception is pending as a trap-class 
exception on the instruction boundary immediately after the ENCLS instruction. Additionally, if the instruction is 
executed in VMX non-root operation and the “monitor trap  flag” VM-execution control is 1, an MTF VM exit is 
pending on the instruction boundary immediately after the instruction if the instruction does not fault.40-2 Vol. 3DENCLAVE CODE DEBUG AND PROFILING
40.2.2 Single Stepping ENCLU Instruction Leafs
The interactions of the unprivileged Inte l SGX instruction ENCLU are leaf dependent.
An enclave entry via EENTER/ERESUME leaf  functions of the ENCLU, in certain cases, may mask the RFLAGS.TF bit, 
and mask the setting of the “monitor trap flag” VM-execution  control. In such situations, an exit from the enclave, 
either via the EEXIT leaf function or via an AEX unmask s the RFLAGS.TF bit and the “m onitor trap flag” VM-execu-
tion control. The details of this masking/unmasking  and the pending of single stepping events across 
EENTER/ERESUME/EEX IT/AEX are covered in detail in Section 40.2.3.
If the EFLAGS.TF bit is set at the beginning of EREPORT or  EGETKEY leafs, and if the EFLAGS.TF is not masked by 
the preceding enclave entry, then a single-step debug ex ception is pending on the instruction boundary immedi-
ately after the ENCLU instruction. Addi tionally, if the instruction is executed in VMX non-root operation and the 
“monitor trap flag” VM-execution control is 1, and if the monitor trap flag is not masked by the preceding enclave 
entry, then an MTF VM exit is pending on the in struction boundary immediately after the instruction.
If the instruction under consideration results in a fault, then the control flow goes to the fault handler, and no 
single-step debug exception is asserted. In such a situation, if the instruction is executed in VMX non-root opera-
tion and the “monitor trap flag” VM-execution control is 1, an MTF VM exit is pending after the delivery of the fault 
(or any nested exception). No MTF VM exit occurs if another VM exit occurs before reaching that boundary on which 
an MTF VM exit would be pending.
40.2.3 Single-Stepping Enclave Entry with Opt-out Entry
40.2.3.1  Single Stepping without AEX
Figure 40-1 shows the most common case for single-stepping after an opt-out entry.
In this scenario, if the RFLAGS.TF bit is set at the time of  the enclave entry, then a single step debug exception is 
pending on the instruction boundary after EEXIT. Additionally, if the enclave is executing in VMX non-root operation 
and the “monitor trap flag” VM-execution control is 1, an  MTF VM exit is pending on the instruction boundary after 
EEXIT.
The value of the RFLAGS.TF bit at the en d of EEXIT is the same as the value of  RFLAGS.TF at the time of the enclave 
entry.
40.2.3.2  Single Step Preempte d by AEX Due to Non-SMI Event
Figure 40-2 shows the interaction of single stepping wi th AEX due to a non-SMI event after an opt-out entry.Figure 40-1.  Single Stepping with Opt-out Entry - No AEXSMIEENTER
Inst1
RFLAGS.TF
VMCS.MTFERESUME
Inst2 Inst3 EEXIT Inst4
TF/MTF
Handler
Higher PriorityHandlerINIT
#MC Single-Step #DB Pending
MTF VM Exit PendingVol. 3D 40-3ENCLAVE CODE DEBUG AND PROFILING
In this scenario, if the enclave is executing in VMX non- root operation and the “monitor trap flag” VM-execution 
control is 1, an MTF VM exit is pending on the instruction boundary after the AEX. No MTF VM exit occurs if another 
VM exit happens before reaching that instruction boundary. 
The value of the RFLAGS.TF bit at the end of AEX is the sa me as the value of RFLAGS.TF at the time of the enclave 
entry.
40.2.4 RFLAGS.TF Treatment on AEX
The value of EFLAGS.TF at the end of AEX from an opt-out enclave is same as the value of EFLAGS.TF at the time 
of the enclave entry. The value of EFLAGS.TF at the en d of AEX from an opt-in enclave is unmodified. The 
EFLAGS.TF saved in GPR portion of the SSA on an AEX is  0. For more detail see EENTER and ERESUME in Chapter 5.
40.2.5 Restriction on Setting of TF after an Opt-Out Entry
Enclave entered through an opt-out entry is not allowed to  set EFLAGS.TF. The POPF instruction forces RFLAGS.TF 
to 0 if the enclave was entered through opt-out entry.
40.2.6 Trampoline Code Considerations
Any AEX from the enclave which results in the RFLAGS.TF =1  on the reporting stack will result in a single-step #DB 
after the first instruction of the trampoline code if the trampoline is entered using the IRET instruction.
40.3 CODE AND DATA BREAKPOINTS
40.3.1 Breakpoint Suppression
Following an opt-out entry:
•Instruction breakpoints are suppressed during execution in an enclave. 
•Data breakpoints are not triggered on accesse s to the address range defined by ELRANGE.
•Data breakpoints are triggered on accesses to addresses outside the ELRANGEFigure 40-2.  Single Stepping with Opt-out Entry -A EX Due to Non-SMI Event Before Single-Step BoundaryEvent Inside EnclaveEENTER
Inst1
RFLAGS.TF
TF/MTF
Handler
AEXHandlerSingle-Step #DB Pending
MTF VM Exit PendingAEX
Higher Priority
Handler40-4 Vol. 3DENCLAVE CODE DEBUG AND PROFILING
Following an opt-in entry instruction and data breakpoints are not suppressed.
The processor does not report any matches on debug breakpoints that are suppressed on enclave entry. However, 
the processor does not clear any bits in DR6 that were already set at the time of the enclave entry.
40.3.2 Reporting of Instruction Breakpoint  on Next Instruction on a Debug Trap
A debug exception caused by the single-step execution mode  or when a data breakpoint condition was met causes 
the processor to perform an AEX. Following such an AEX, the processor reports in the debug status register (DR6) 
matches of the new instruction pointer (the AEP address) in a breakpoint address register setup to detect instruc-tion execution.
40.3.3 RF Treatment on AEX
RF flag value saved in SSA is the same as what would have  been pushed on stack if the exception or event causing 
the AEX occurred when executing outside an enclave (see Sect ion 18.3.1.1). Following an AEX, the RF flag is 0 in 
the synthetic state. 
40.3.4 Breakpoint Matching in Intel® SGX Instruction Flows
Implicit accesses made by Intel SGX instructions to EPC regions do not trigger data breakpoints. Explicit accesses 
made by ENCLS[ECREATE], ENCLS[EADD], ENCLS[EEXTEND], ENCLS[EINIT], ENCLS[EREMOVE], 
ENCLS[ETRACK], ENCLS[EBLOCK], ENCLS[EPA], ENCLS[ EWB], ENCLS[ELD], ENCLS[ED BGRD], ENCLS[EDBGWR], 
ENCLU[EENTER], and ENCLU[ERESUME] to the EPC operands do not trigger data breakpoints.

Explicit accesses made by the Intel SGX instructions (ENCLU[EGETKEY] and ENCLU[EREPORT]) executed by an 
enclave following an opt-in entry, trigger data breakpoint s on accesses to their EPC operands. All Intel SGX instruc-
tions trigger data breakpoints on accesses to their non-EPC operands. 
40.4 CONSIDERATION OF THE INT1 AND INT3 INSTRUCTIONS
This section considers the operation of the INT1 and INT3 instructions when executed inside an enclave. These are 
the instructions with opcodes F1 and CC, respectively, and not INT n (with opcode CD) with value 1 or 3 for n.
40.4.1 Behavior of INT1 and INT3 Inside an Enclave
An execution of either INT1 or INT3 inside an enclave resu lts in a fault-class exception. Following an opt-out entry, 
execution of either instruction results in an invalid-opcode exception (#UD). Following opt-in entry, INT1 results in 
a debug exception (#DB) and INT3 delivers a breakpoint exception (#BP). The normal requirement for INT3 (that 
the CPL not be greater than the DPL of descriptor 3 in the IDT) is not enforced.
Because execution of INT1 or INT3 inside an enclave results in a fault, the RIP saved in the SSA on AEX references 
the INT1 or INT3 instruction (and not the following instru ction). The RIP value saved on the stack (or in the TSS or 
VMCS) is that of the AEP.
If execution of INT1 or INT3 inside an enclave causes a VM exit, the event type in th e VM-exit interruption informa-
tion field indicates a hardware exception (type 3),1 and the VM-exit instruction length field is saved as zero.
40.4.2 Debugger Considerations
A debugger using INT3 inside an enclave should account for the modified behavior described in Section 40.4.1. Because INT3 is fault-like inside an enclave, the RIP saved in the SSA on AEX is that of the INT3 instruction. Conse-
1. INT1 would normally indicate a privileged software exception (type 5), and INT3 would normally indicate a software exception (type 
6).Vol. 3D 40-5ENCLAVE CODE DEBUG AND PROFILING
quently, the debugger must not decrement SSA.RIP for #BP coming from an enclave to re-execute the instruction 
at the RIP of the INT3 instructio n on a subsequent enclave entry. 
40.4.3 VMM Considerations
As described in Section 40.4.1, execution of INT3 inside an enclave delivers #BP with “interruption type” of 3. A 
VMM that re-injects #BP into the guest should establis h the VM-entry interruption information field using data 
saved into the appropriate VMCS fields by the VM exit  incident to the #BP (as recommended in the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 3C).
VMMs that create the VM-entry interruption information base d solely on the exception vector should take care to 
use event type 3 (instead of 6) when they detect a VM exit  incident to enclave mode that is due to an exception 
with vector 3.
40.5 BRANCH TRACING
40.5.1 BTF Treatment
When software enables single-stepping on branches then:
•Following an opt-in entry using EENTER the processor generates a single step debug exception. 
•Following an EEXIT the processor generates a single-step debug exception
Enclave entry using ERESUME (opt-in or opt-out) and an AEX from the enclave do not cause generation of the 
single-step debug exception.
40.5.2 LBR Treatment
40.5.2.1  LBR Stack on Opt-in Entry
Following an opt-in entry into an enclave, last branch recording facilities if enabled continued to store branch 
records in the LBR stack MSRs as follows:
•On enclave entry using EENTER/ERE SUME, the processor push the addr ess of EENTER/ERESUME instruction 
into MSR_LASTBRANCH_n_FROM_IP, and the destin ation address of the EENTER/ERESUME into 
MSR_LASTBRANCH_n_TO_IP. 
•On EEXIT, the processor pushes the address of EEXIT  instruction into MSR_LAST BRANCH_n_FROM_IP, and the 
address of EEXIT destination into MSR_LASTBRANCH_n_TO_IP. 
•On AEX, the processor pushes RIP saved in the SSA into MSR_LASTBRANCH_n_FROM_IP, and the address of 
AEP into MSR_LASTBRANCH_n_TO_IP. 
•For every branch inside the enclave, a branch record is pushed on the LBR stack.
Figure 40-3 shows an example of LBR stack manipulation after an opt-in entry. Every arrow in this picture indicates 
a branch record pushed on the LBR stac k. The “From IP” of the branch record  contains the linear address of the 
instruction located at the start of the arrow, while the “To IP” of the branch record contains the linear address of the 
instruction at the end of the arrow. 40-6 Vol. 3DENCLAVE CODE DEBUG AND PROFILING
40.5.2.2  LBR Stack on Opt-out Entry
An opt-out entry into an enclave suppresses last branch re cording facilities, and enclave exit after an opt-out entry 
un-suppresses last branch recording facilities.
Opt-out entry into an enclave does not push any record on LBR stack.If last branch recording facilities were enabled at the ti me of enclave entry, then EE XIT following such an enclave 
entry pushes one record on LBR stack. The MSR_LASTBRAN CH_n_FROM_IP of such record holds the linear address 
of the instruction (EENTER or ERESUME) that  was used to enter the enclave, while the 
MSR_LASTBRANCH_n_TO_IP of such record holds linear address of the destination of EEXIT. 
Additionally, if last branch recording facilities were enable d at the time of enclave entry, then an AEX after such an 
entry pushes one record on LBR stack, before pushing re cord for the event causing the AEX if the event pushes a 
record on LBR stack. The MSR_LASTBRANCH_n_FROM_IP of the new record holds linear address of the instruction 
(EENTER or ERESUME) that was used to enter the encl ave, while MSR_LASTBRANCH_n_TO_IP of the new record 
holds linear address of the AEP. If the event caus ing AEX pushes a record on LBR stack, then the 
MSR_LASTBRANCH_n_FROM_IP for that reco rd holds linear address of the AEP.
Figure 40-4 shows an example of LBR stack manipulation afte r an opt-out entry. Every arrow in this picture indi-
cates a branch record pushed on the LBR stack. The “From IP” of the branch record contains the linear address of 
the instruction located at the start of the arrow, while th e “To IP” of the branch record contains the linear address 
of the instruction at the end of the arrow.Figure 40-3.  LBR Stack Interaction with Opt-in EntryInst1
BR2 Inst3
EEXITInst4
AEPEENTER
Inst4
IRETOS
Inst4AEPAEP
ERESUME
BR5 Inst6
Inst7FaultVol. 3D 40-7ENCLAVE CODE DEBUG AND PROFILING
40.5.2.3  Mispredict Bit, Record Type, and Filtering
All branch records resulting from In tel SGX instructions/AEXs are reported as predicted branches, and conse-
quently, bit 63 of MSR_LASTBRANCH_n_FROM_IP for such records is set. Branch records due to these Intel SGX 
operations are always non-HLE/non-RTM records. 
EENTER, ERESUME, EEXIT, and AEX are considered to be  far branches. Consequently, bit 8 in MSR_LBR_SELECT 
controls filtering of the new records introduced by Intel SGX.
40.6 INTERACTION WITH PERFORMANCE MONITORING 
40.6.1 IA32_PERF_GLOBA L_STATUS Enhancement
On processors supporting Intel SGX, the IA32_PERF_GLOBA L_STATUS MSR provides a bit indicator, known as “Anti 
Side-channel Interference” (ASCI) at bit position 60. If th is bit is 0, the performance monitoring data in various 
performance monitoring counters are accumulated normally  as defined by relevant architectural/microarchitec-
tural conditions. If the ASCI bit is set, the contents in va rious performance monitoring counters can be affected by 
the direct or indirect consequence of Intel SGX prot ection of enclave code executing in the processor. 
40.6.2 Performance Monitoring with Opt-in Entry
An opt-in enclave entry allow performance monitoring logi c to observe the contribution  of enclave code executing 
in the processor. Thus the contents of performance monitoring counters does not distinguish between contribution 
originating from enclave code or otherwise. All counters, events, precise events, etc. continue to work as defined 
in the IA32/Intel 64 Software Developer Manual. Consequently, bit 60 of IA32_PERF_GLOBAL_STATUS MSR is not set.Figure 40-4.  LBR Stack Interaction with Opt-out EntryInst1
BR2 Inst3
AEPEENTER
IRETOS
ERESUME
BR5 Inst6
Inst7Fault40-8 Vol. 3DENCLAVE CODE DEBUG AND PROFILING
40.6.3 Performance Monitoring with Opt-out Entry
In general, performance monitoring activities are suppresse d when entering an opt-out enclave. This applies to all 
thread-specific, configured performance monitoring, except for the cycle-counting fixed counter, IA32_FIXED_CTR1 and IA32_FIXED_CTR2. Upon entering an opt-out enclave, IA32_FIXED_CTR0, IA32_PMCx will 
stop accumulating counts. Additionally, if PEBS is configur ed to capture PEBS record fo r this thread, PEBS record 
generation will also be suppressed. Consequently , bit 60 of IA32_PERF_GLOBAL_STATUS MSR is set.
Performance monitoring on the siblin g thread may also be affected. Any one of IA32_FIXED_CTRx or IA32_PMCx 
on the sibling thread configured to monitor thread-specifi c eventing logic with AnyThr ead =1 is demoted to count

BR2 Inst3
AEPEENTER
IRETOS
ERESUME
BR5 Inst6
on the sibling thread configured to monitor thread-specifi c eventing logic with AnyThr ead =1 is demoted to count 
only MyThread while an opt-out enclave is executing on the other thread.
40.6.4 Enclave Exit and Performance Monitoring
When a logical processor exits an enclave, either via ENCL U[EEXIT] or via AEX, all performance monitoring activity 
(including PEBS) on that logical proces sor that was suppressed is unsuppressed. 
Any counters that were de moted from AnyThread to MyThread on th e sibling thread are promoted back to 
AnyThread.
40.6.5 PEBS Record Generation on Intel® SGX Instructions
All leaf functions of the ENCLS instruct ion report “Eventing RIP” of the ENCLS instruction if a PEBS record is gener-
ated at the end of the instruction execution. Additiona lly, the EGETKEY and EREPORT leaf functions of the ENCLU 
instruction report “Eventing RIP” of the ENCLU instruction if  a PEBS record is generated at the end of the instruction 
If the EENTER and ERESUME leaf functions are performing  an opt-in entry report “E venting RIP” of the ENCLU 
instruction if a PEBS record is generated at the end of th e instruction execution. On the other hand, if these leaf 
functions are performing an opt-out entry, then these leaf  functions result in PEBS being suppressed, and no PEBS 
record is generated at the end of these instructions.
A PEBS record is generated if there is a PEBS event pe nding at the end of EEXIT (d ue to a counter overflowing 
during enclave execution or during EEXIT execution). This PEBS record contains the architectural state of the 
logical processor at the end of EEXIT. If the enclave was en tered via an opt-in entry, th en this record reports the 
“Eventing RIP” as the linear address of the ENCLU[EEXIT] instruction. If the enclave was entered via an opt-out 
entry, then the record reports the “Eventing RIP” as the linear address of the ENCLU[EENTER/ERESUME] instruc-
tion that performed the last enclave entry. 
A PEBS record is generated after the AE X if there is a PEBS event pending at the end of AEX (due to a counter over-
flowing during enclave execution or during AEX execution) . This PEBS record contains the synthetic state of the 
logical processor that is established at  the end of AEX. For opt-in entry, th is record has the EVENTING_RIP set to 
the RIP saved in the SSA. For opt-out entry, the record has the EVENTING_RIP set to the linear address of EENTER/ERESUME used for the last enclave entry.
If the enclave was entered via an opt-in entry, then this record reports the “Eventing RIP” as the linear address in 
the SSA of the enclave (a.k.a., the “E venting LIP” inside the enclave). If the enclave was entered via an opt-out 
tion that performed the last enclave entry.
A second PEBS event may be pended during the Enclave Ex iting Event (EEE). If the PEBS event is taken at the end 
of delivery of the EEE then the “Eve nting RIP” in this second PEBS reco rd is the linear address of the AEP.
40.6.6 Exception-Handling on PE BS/BTS Loads/Stores after AEX
As noted in Section 18.4.9.2, recording in the BTS buffer or  in the PEBS buffer may not operate properly if accesses 
to any of the DS save area sections cause page faults or VM  exits. Such page faults or VM exits, if they occur, are 
delivered immediately to the OS or VMM, and generation of a BTS or PEBS record is skipped and may leave the 
buffers in a state where they have a partial BTS or PEBS records. 
However, any events that are detected during PEBS/BTS re cord generation at the end of AEX and before delivering 
the Enclave Exiting Event (EEE) cannot be reported immediat ely to the OS/VMM, as an event window is not open at Vol. 3D 40-9ENCLAVE CODE DEBUG AND PROFILING
the end of AEX. Consequently, fault-like events such as page faults, EPT faults, EPT mis-configuration, and 
accesses to APIC-access page detected on stores to the PEBS/BTS buffer are not reported, and generation of the PEBS and/or BTS record at the end of AEX is aborted (thi s may leave the buffers in a state where they have partial 
PEBS or BTS records). Trap-like events detected on stor es to the PEBS/BTS buffer (such as debug traps) are 
pended until the next instruction boundary, where they  are handled according to the architecturally defined 
priority. The processor continues the handling of the Enclav e Exiting Event (SMI, NMI, interrupt, exception delivery, 
VM exit, etc.) after aborting th e PEBS/BTS record generation. 
40.6.6.1  Other Interactions with Performance Monitoring
For opt-in entry, EENTER, ERESUME, EEXIT, and AEX are all treated as predicted far branches, and any counters 
that are counting such branches are incremented by 1 as a part of retirement of these instructions. Retirement of 
these instructions is also counted in any counters configured to count instructions retired.
For opt-out entry, execution inside an enclave is treate d as a single predicted bran ch, and all branch-counting 
performance monitoring counters are incremented accordingly. Additionally, such execution is also counted as a 
single instruction, and all performance monitoring counters counting instructions are incremented accordingly.
Enclave entry does not affect any performance monitoring counters shared between cores. 40-10 Vol. 3DENCLAVE CODE DEBUG AND PROFILINGVol. 3D A-1APPENDIX A
The ability of a processor to support VMX operat ion and related instructions is indicated by 
CPUID.1:ECX.VMX[bit 5] = 1. A value 1 in this bit indicates support for VMX features.
Support for specific features detailed in Chapter 27 and other VMX chapters is determined by reading values from 
a set of capability MSRs. These MSRs are indexed starting  at MSR address 480H. VMX capability MSRs are read-
only; an attempt to write them (with WRMSR) produces a general-protection exception (#GP(0)). They do not exist 
on processors that do not support VMX operation; an attempt to read them (with RDMSR) on such processors 
produces a general-protection exception (#GP(0)).
A.1 BASIC VMX INFORMATION
The IA32_VMX_BASIC MSR (index 480H) co nsists of the following fields:
•Bits 30:0 contain the 31-bit VMCS revision identifier used by the processor. Processors that use the same VMCS 
revision identifier use the same size for VMCS regions (see subsequent item on bits 44:32).1
•Bit 31 is always 0.
•Bits 44:32 report the number of bytes that software should allocate for the VMXON region and any VMCS 
region. It is a value greater than 0 and at most 4096 (bit 44 is set if and only if bits 43:32 are clear).
•Bit 48 indicates the width of the physical addresses th at may be used for the VMXON region, each VMCS, and 
data structures referenced by pointers in a VMCS (I/O  bitmaps, virtual-APIC page , MSR areas for VMX transi-
tions). If the bit is 0, these addresses are limited to the processor’s physical-address width.2 If the bit is 1, 
these addresses are limited to 32 bits. This bit is alwa ys 0 for processors that support Intel 64 architecture.
•If bit 49 is read as 1, the logical processor suppor ts the dual-monitor treatment of system-management 
interrupts and system-management mode. See Se ction 32.15 for details of this treatment.
•Bits 53:50 report the memory type that should be us ed for the VMCS, for data structures referenced by 
pointers in the VMCS (I/O bitmaps,  virtual-APIC page, MSR areas for VMX transitions), and for the MSEG 
header. If software needs to access these data structures (e.g., to modify the contents of the MSR bitmaps), it 
can configure the paging structures to map them into the linear-address space. If it does so, it should establish mappings that use the memory type reported bits 53:50 in this MSR.
3
As of this writing, all processors that support VMX oper ation indicate the write-back  type. The values used are 
given in Table A-1.
1. Earlier versions of this manual specified that the VMCS revisi on identifier was a 32-bit field in bits 31:0 of this MSR. For a ll proces-
sors produced prior to this change , bit 31 of this MSR was read as 0.
2. On processors that support In tel 64 architecture, the pointer must not set bits beyond the processor's physical address width .
3. Alternatively, software may map any of these regions or struct ures with the UC memory type. (This may be necessary for the MS EG 
header.) Doing so is discouraged unless nece ssary as it will cause the performance of software accesses to those structures to suf-
fer.Table A-1.  Memory Types Recommended for VMCS and Related Data Structures
Value(s) Field
0 Uncacheable (UC)
1–5 Not used
6 Write Back (WB)7–15 Not usedA-2 Vol. 3DVMX CAPABILITY REPORTING FACILITY
•If bit 54 is read as 1, the processor reports informatio n in the VM-exit instruction-information field on VM exits 
due to execution of the INS and OUTS instructions (see Sect ion 28.2.5). This reporting is done only if this bit is 
read as 1.
•Bit 55 is read as 1 if any VMX controls that default to 1 may be cleared to 0. See Appendix A.2 for details. It also

read as 1.
•Bit 55 is read as 1 if any VMX controls that default to 1 may be cleared to 0. See Appendix A.2 for details. It also 
reports support for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, IA32_VMX_TRUE_PROC-
BASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2, Appendix A.4, and Appendix A.5 for details.
•If bit 56 is read as 1, software can use VM entry to deliv er a hardware exception with or without an error code, 
regardless of vector (see Section 27.2.1.3).
•The values of bits 47:45 and bits 63:57 are reserved and are read as 0.
A.2 RESERVED CONTROLS AND DEFAULT SETTINGS
As noted in Chapter 27, “VM Entries‚” certain VMX controls ar e reserved and must be set to a specific value (0 or 1) 
determined by the processor. The specific value to which a reserved control must be set is its default setting . 
Software can discover the default setting of a reserved control by consulting the appropriate VMX capability MSR 
(see Appendix A.3 through Appendix A.5).
Future processors may define new functionality for one or  more reserved controls. Such processors would allow 
each newly defined control to be set either to 0 or to 1. Software that does not desire a control’s new functionality 
should set the control to its default setting. For that reason, it is useful for software to  know the default settings of 
the reserved controls.
Default settings partition the various controls into the following classes:
•Always-flexible . These have never been reserved.
•Default0 . These are (or have been) reserv ed with a default setting of 0.
•Default1 . They are (or have been) reserved with a default setting of 1.
As noted in Appendix A.1, a logical processor uses bi t 55 of the IA32_VMX_BASIC MSR to indicate whether any of 
the default1 controls may be 0:
•If bit 55 of the IA32_VMX_BASIC MSR is read as 0, all the default1 controls are reserved and must be 1. 
VM entry will fail if any of these controls are 0 (see Section 27.2.1).
•If bit 55 of the IA32_VMX_BASIC MSR is read as 1, not all the default1 controls are reserved, and some (but 
not necessarily all) may be 0. The CPU supports four (4) new VMX capability MSRs: 
IA32_VMX_TRUE_PINBASED_CTLS, IA32_VMX_TRUE_PROC BASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and 
IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3 through Appendix A.5 for details. (These MSRs are not 
supported if bit 55 of the IA32_VMX_BASIC MSR is read as 0.)
A.3 VM-EXECUTION CONTROLS
There are separate capability MSRs for the pin-based VM-execution controls, the primary processor-based VM-execution controls, the secondary processor-based VM-exe cution controls, and the tertiary processor-based VM-
execution controls. These are described in Appendix A.3.1,  Appendix A.3.2, Appendix A.3.3, and Appendix A.3.4, 
A.3.1  Pin-Based VM-Execution Controls
The IA32_VMX_PINBASED_CTLS MSR (index 481H ) reports on the allowed settings of most  of the pin-based 
VM-execution controls (see Section 25.6.1):
•Bits 31:0 indicate the allowed 0-settings  of these controls. VM entry allows control X (bit X of the pin-based 
VM-execution controls) to be 0 if bit X in the MSR is cleare d to 0; if bit X in the MSR is  set to 1, VM entry fails if 
control X is 0.Vol. 3D A-3VMX CAPABILITY REPORTING FACILITY
Exceptions are made for the pin-based VM-execution controls in the default1 class (see Appendix A.2). These 
are bits 1, 2, and 4; the corresponding bits of the IA32_VMX_PINBASED_CTLS MSR are always read as 1. The 
treatment of these controls by VM entry is de termined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any pin-based VM-execution control in 
the default1 class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PINBASED_CTLS MSR (see 
below) reports which of the pin-based VM-execution controls in the default1 class can be 0 on VM entry.
•Bits 63:32 indicate the allowed 1-settings  of these controls. VM entry allows control X to be 1 if bit 32+X in 
the MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
If bit 55 in the IA32_VMX_BASIC MSR is read as 1,  the IA32_VMX_TRUE_PINBASED_CTLS MSR (index 48DH) 
reports on the allowed settings of all of the pin-based VM-execution controls:
•Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X to be 0 if bit X in the MSR 
is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0. There are no exceptions.
•Bits 63:32 indicate the allowed 1-settings of these controls . VM entry allows control X to be 1 if bit 32+X in the 
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.
It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the pin-
based VM-execution controls:
•If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the pin-based 
VM-execution controls is contained in  the IA32_VMX_PINBASED_CTLS MSR. (The 
IA32_VMX_TRUE_PINBASED_CTLS MSR is not supported.)
•If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the pin-based 
VM-execution controls is contained in the IA32_VMX_ TRUE_PINBASED_CTLS MSR. Assuming that software 
knows that the default1 class of pin-based VM-execution co ntrols contains bits 1, 2, and 4, there is no need for 
software to consult the IA32_VMX_PINBASED_CTLS MSR.
A.3.2  Primary Processor-Based VM-Execution Controls
The IA32_VMX_PROCBASED_CTLS MSR (index 482H) reports on the allowed settings of most  of the primary 
processor-based VM-execution controls (see Section 25.6.2):
•Bits 31:0 indicate the allowed 0-settings of these cont rols. VM entry allows control X (bit X of the primary 
processor-based VM-execution controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to 
1, VM entry fails if control X is 0.
Exceptions are made for the primary processor-based VM-execution controls in the default1 class (see 
Appendix A.2). These are bits 1, 4–6, 8, 13–16, and 26; the corresponding bits of the IA32_VMX_PROC-
BASED_CTLS MSR are always read as 1. The treatment of  these controls by VM entry is determined by bit 55 
in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any of the primary processor-based VM-
execution controls in the default1 class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as  1, the IA32_VMX_TRUE_PROCBASED_CTLS MSR (see 
below) reports which of the primary processor-based VM-execution controls in the default1 class can be 0 
on VM entry.
If bit 55 in the IA32_VMX_BASIC MSR is read as 1,  the IA32_VMX_TRUE_PROCBASED_CTLS MSR (index 48EH) 
reports on the allowed settings of all of the primary processor-based VM-execution controls:
It is necessary for software to consult only one of th e capability MSRs to determin e the allowed settings of the 
primary processor-based VM-execution controls:A-4 Vol. 3DVMX CAPABILITY REPORTING FACILITY
•If bit 55 in the IA32_VMX_BASIC MSR is read as 0, a ll information about the allowed settings of the primary 
processor-based VM-execution controls is contai ned in the IA32_VMX_PROCBASED_CTLS MSR. (The 
IA32_VMX_TRUE_PROCBASED_CTLS MSR is not supported.)
•If bit 55 in the IA32_VMX_BASIC MSR is read as 1, a ll information about the allowed settings of the primary 
processor-based VM-execution controls is contai ned in the IA32_VMX_TRUE_PROCBASED_CTLS MSR. 
Assuming that software knows that the default1 cla ss of primary processor-based VM-execution controls 
contains bits 1, 4–6, 8, 13–16, and 26, there is no need for software to consult the 
IA32_VMX_PROCBASED_CTLS MSR.
A.3.3  Secondary Processor-Based VM-Execution Controls
The IA32_VMX_PROCBASED_CTLS2 MSR (index 48BH) report s on the allowed settings of the secondary processor-
based VM-execution controls (see Section 25.6.2). The fo llowing items provide details, including enforcement by 
VM entry:
•Bits 31:0 indicate the allowed 0-settings of these controls . These bits are always 0. This fact indicates that 
VM entry allows each bit of the secondary processor-based VM-execution controls to be 0 (reserved bits must 
be 0)
•Bits 63:32 indicate the allowed 1-settings of these contro ls; the 1-setting is not allowed for any reserved bit.

VM entry:
be 0)
•Bits 63:32 indicate the allowed 1-settings of these contro ls; the 1-setting is not allowed for any reserved bit. 
VM entry allows control X (bit X of the secondary processor-based VM-execution controls) to be 1 if bit 32+X in 
the MSR is set to 1; if bit 32+X in the MSR is cleared to  0, VM entry fails if control X and the “activate secondary 
controls” primary processor-based VM-execution control are both 1.
The IA32_VMX_PROCBASED_CTLS2 MSR exists only on proc essors that support the 1-setting of the “activate 
secondary controls” VM-execution control (only if  bit 63 of the IA32_VMX_PROCBASED_CTLS MSR is 1).
A.3.4  Tertiary Processor-Based VM-Execution Controls
The IA32_VMX_PROCBASED_CTLS3 MSR (index 492H) reports on the allowed 1-settings of the tertiary processor-
based VM-execution controls (see Section 25.6.2); the 1-setting is not allowed for any reserved bit.
VM entry allows control X (bit X of the tertiary processor-based VM-execution controls) to be 1 if bit X in the MSR 
is set to 1; if bit X in the MSR is cleared to 0, VM entry fails if control X and the “activate tertiary controls” primary 
processor-based VM-execution control are both 1.
The IA32_VMX_PROCBASED_CTLS3 MSR exists only on proc essors that support the 1-setting of the “activate 
tertiary controls” VM-execution control (only if bit 49 of the IA32_VMX_PROCBASED_CTLS MSR is 1).
Notice that the organization of this MSR differs from that of IA32_VMX_PROCBASED_CTLS2 (Appendix A.3.3). This 
is because there are 64 tertiary processor-based VM-execution controls, while there were only 32 secondary processor-based VM-execution controls.
A.4 VM-EXIT CONTROLS
There are separate capability MSRs for the primary VM-exi t controls and the secondary VM-exit controls. These are 
described in Appendix A.4.1 and Appendix A.4.2, respectively.
A.4.1  Primary VM-Exit Controls
The IA32_VMX_EXIT_CTLS MSR (index 483H ) reports on the allowed settings of most  of the primary VM-exit 
controls (see Section 25.7.1):
•Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the primary 
VM-exit controls) to be 0 if bit X in the MSR is cleared to 0;  if bit X in the MSR is set to 1, VM entry fails if control 
X is 0.Vol. 3D A-5VMX CAPABILITY REPORTING FACILITY
Exceptions are made for the primary VM-exit controls in the default1 class (see Appendix A.2). These are 
bits 0–8, 10, 11, 13, 14, 16, and 17; the corresponding bits of the IA32_VMX_EXIT_CTLS MSR are always read as 1. The treatment of these controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any primary VM-exit control in the 
default1 class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_EXIT_CTLS MSR (see below) 
reports which of the primary VM-exit controls in the default1 class can be 0 on VM entry.
•Bits 63:32 indicate the allowed 1-settings of these controls . VM entry allows control 32+X to be 1 if bit X in the 
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, th e IA32_VMX_TRUE_EXIT_CTLS MSR (index 48FH) reports on 
the allowed settings of all of the primary VM-exit controls:
primary VM-exit controls:
VM-exit controls is contained in the IA32_VMX_EXIT_C TLS MSR. (The IA32_VMX_TRUE_EXIT_CTLS MSR is not 
supported.)
VM-exit controls is contained in the IA32_VMX_TRUE_EX IT_CTLS MSR. Assuming that software knows that the 
default1 class of primary VM-exit controls contains bi ts 0–8, 10, 11, 13, 14, 16, and 17, there is no need for 
software to consult the IA32_VMX_EXIT_CTLS MSR.
A.4.2  Secondary VM-Exit Controls
The IA32_VMX_EXIT_CTLS2 MSR (index 493H) reports on th e allowed 1-settings of the secondary VM-exit controls 
(see Section 25.7.1); the 1-setting is not allowed for any reserved bit.
VM entry allows control X (bit X of the secondary VM-exit contro ls) to be 1 if bit X in the MSR is set to 1; if bit X in 
the MSR is cleared to 0, VM entry fails if control X and th e “activate secondary controls” primary VM-exit control are 
both 1.
The IA32_VMX_EXIT_CTLS2 MSR exists only on processors that support the 1-setting of the “activate secondary 
controls” VM-exit control (only if bit 63 of the IA32_VMX_EXIT_CTLS MSR is 1).
Notice that the organization of this MSR differs from that of IA32_VMX_EXIT_CTLS (Appendix A.4.1). This is 
because there are 64 secondary VM-exit controls, whil e there were only 32 primary VM-exit controls.
A.5 VM-ENTRY CONTROLS
The IA32_VMX_ENTRY_CTLS MSR (index 484H) reports on the allowed settings of most  of the VM-entry controls 
(see Section 25.8.1):
•Bits 31:0 indicate the allowed 0-settings of these contro ls. VM entry allows control X (bit X of the VM-entry 
controls) to be 0 if bit X in the MSR is cleared to 0; if bi t X in the MSR is set to 1, VM entry fails if control X is 0.
Exceptions are made for the VM-entry controls in the de fault1 class (see Appendix A.2). These are bits 0–8 and 
12; the corresponding bits of the IA32_VMX_ENTRY_CTLS MSR are always read as 1. The treatment of these 
controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any VM-entry control in the default1 
class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_ENTRY_CTLS MSR (see below) 
reports which of the VM-entry controls in  the default1 class can be 0 on VM entry.A-6 Vol. 3DVMX CAPABILITY REPORTING FACILITY
•Bits 63:32 indicate the allowed 1-settings of these controls . VM entry fails if bit X is 1 in the VM-entry controls 
and bit 32+X is 0 in this MSR.
If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_ENTRY_CTLS MSR (index 490H) reports 
on the allowed settings of all of the VM-entry controls:
•Bits 31:0 indicate the allowed 0-settings of these controls . VM entry allows control X to be 0 if bit X in the MSR 
It is necessary for software to consult only one of th e capability MSRs to determine the allowed settings of the 
VM-entry controls:
•If bit 55 in the IA32_VMX_BASIC MSR is read as 0, a ll information about the allowed settings of the VM-entry 
controls is contained in the IA32_VMX_ENTRY_CTL S MSR. (The IA32_VMX_TRUE_ENTRY_CTLS MSR is not 
•If bit 55 in the IA32_VMX_BASIC MSR is read as 1, a ll information about the allowed settings of the VM-entry 
controls is contained in the IA32_VMX_TRUE_ENTRY_CT LS MSR. Assuming that software knows that the 
default1 class of VM-entry controls contains bits 0–8 and 12, there is no need for software to consult the 
IA32_VMX_ENTRY_CTLS MSR.
A.6 MISCELLANEOUS DATA
The IA32_VMX_MISC MSR (index 485H) consists of the following fields:
•Bits 4:0 report a value X that specifies the relationship between the rate of the VMX-preemption timer and that 
of the timestamp counter (TSC). Specifically, the VMX-pree mption timer (if it is active) counts down by 1 every 
time bit X in the TSC changes due to a TSC increment.
•If bit 5 is read as 1, VM exits store the value of IA32_EF ER.LMA into the “IA-32e mode guest” VM-entry control; 
see Section 28.2 for more details. This bit is read as 1 on any logical processor that supports the 1-setting of 
the “unrestricted guest” VM-execution control.
•Bits 8:6 report, as a bitmap, the activity states supported by the implementation:
— Bit 6 reports (if set) the support for activity state 1 (HLT).
— Bit 7 reports (if set) the support for activity state 2 (shutdown).— Bit 8 reports (if set) the support for activity state 3 (wait-for-SIPI).
If an activity state is not supported, the implementation causes a VM entry to fail if it attempts to establish that 
activity state. All implementations support VM entry to activity state 0 (active).
•If bit 14 is read as 1, Intel® Processor Trace (Intel PT) can be used in VMX operation. If the processor supports

•If bit 14 is read as 1, Intel® Processor Trace (Intel PT) can be used in VMX operation. If the processor supports 
Intel PT but does not allow it to be used in VMX oper ation, execution of VMXON clears IA32_RTIT_CTL.TraceEn 
(see “VMXON—Enter VMX Operation” in Chapter 31 ); any attempt to write IA32_RTIT_CTL while in VMX 
operation (including VMX root operation) causes a general-protection exception.
•If bit 15 is read as 1, the RDMSR instruction can be  used in system-management mode (SMM) to read the 
IA32_SMBASE MSR (MSR address 9EH). See Section 32.15.6.3.
•Bits 24:16 indicate the number of CR3-target values supported by the processor. This number is a value 
between 0 and 256, inclusive (bit 24 is set if and only if bits 23:16 are clear).
•Bits 27:25 is used to compute the recommended maximum number of MSRs that should appear in the VM-exit 
MSR-store list, the VM-exit MSR-load list, or the VM-entry  MSR-load list. Specifically, if the value bits 27:25 of 
IA32_VMX_MISC is N, then 512 * (N + 1) is the recommen ded maximum number of MSRs to be included in 
each list. If the limit is exceeded, undefined processor behavior may result (including a machine check during 
the VMX transition).
•If bit 28 is read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 (see Section 32.14.4).
•If bit 29 is read as 1, software can use VMWRITE to write to any supported field in the VMCS; otherwise, 
VMWRITE cannot be used to modify VM-exit information fields.Vol. 3D A-7VMX CAPABILITY REPORTING FACILITY
•If bit 30 is read as 1, VM entry allows injection of a software interrupt, software exception, or privileged 
software exception with an instruction length of 0.
•Bits 63:32 report the 32-bit MSEG revision identifier used by the processor.
•Bits 13:9 and bit 31 are reserved and are read as 0.
A.7 VMX-FIXED BITS IN CR0
The IA32_VMX_CR0_FIXED0 MSR (index 486H) and IA32_VMX_CR0_FIXED1 MSR (index 487H) indicate how bits 
in CR0 may be set in VMX operation. They report on bits in  CR0 that are allowed to be 0 and to be 1, respectively, 
in VMX operation. If bit X is 1 in IA32_VMX_CR0_FIXED0, then  that bit of CR0 is fixed to 1 in VMX operation. Simi-
larly, if bit X is 0 in IA32_VMX_CR0_FIXED1, then that bit of CR0 is fixed to 0 in VMX operation. It is always the case 
that, if bit X is 1 in IA32_VMX_CR0_FIXED0, then that bit is also 1 in IA32_VMX_CR0_FIXED1; if bit X is 0 in 
IA32_VMX_CR0_FIXED1, then that bit is also 0 in IA32_VMX _CR0_FIXED0. Thus, each bit in CR0 is either fixed to 
0 (with value 0 in both MSRs), fixed to 1 (1 in both MSRs), or flexible (0 in IA32_VMX_CR0_FIXED0 and 1 in 
IA32_VMX_CR0_FIXED1).
A.8 VMX-FIXED BITS IN CR4
The IA32_VMX_CR4_FIXED0 MSR (index 488H) and IA32_VMX_CR4_FIXED1 MSR (index 489H) indicate how bits 
in CR4 may be set in VMX operation. They report on bits in  CR4 that are allowed to be 0 and 1, respectively, in VMX 
operation. If bit X is 1 in IA32_VMX_CR4_FIXED0, then that bit of CR4 is fixed to 1 in VMX operation. Similarly, if 
bit X is 0 in IA32_VMX_CR4_FIXED1, then that bit of CR4 is fixed to 0 in VMX operation. It is always the case that, 
if bit X is 1 in IA32_VMX_CR4_FIXED0, then that bit is also 1 in IA32_VMX_CR4_FIXED1; if bit X is 0 in 
IA32_VMX_CR4_FIXED1, then that bit is also 0 in IA32_VMX _CR4_FIXED0. Thus, each bit in CR4 is either fixed to 
0 (with value 0 in both MSRs), fixed to 1 (1 in both MSRs), or flexible (0 in IA32_VMX_CR4_FIXED0 and 1 in 
IA32_VMX_CR4_FIXED1).
A.9 VMCS ENUMERATION
The IA32_VMX_VMCS_ENUM MSR (index 48AH) provides inform ation to assist software in enumerating fields in 
the VMCS.
As noted in Section 25.11.2, each field in the VMCS is associated with a 32-bit encoding which is structured as 
follows:
•Bits 31:15 are reserved (must be 0).
•Bits 14:13 indicate the field’s width.
•Bit 12 is reserved (must be 0).
•Bits 11:10 indicate the field’s type.
•Bits 9:1 is an index field that distinguishes di fferent fields with the same width and type.
•Bit 0 indicates access type.
IA32_VMX_VMCS_ENUM indicates to software the highest in dex value used in the encoding of any field supported 
by the processor:
•Bits 9:1 contain the highest index value used for any VMCS encoding.
•Bit 0 and bits 63:10 are reserved and are read as 0.A-8 Vol. 3DVMX CAPABILITY REPORTING FACILITY
A.10 VPID AND EPT CAPABILITIES
The IA32_VMX_EPT_VPID_CAP MSR (index 48CH) reports information about the capabilities of the logical 
processor with regard to virtual-processor identifiers (VPIDs, Section 29.1) and extended page tables (EPT, Section 
29.3):
•If bit 0 is read as 1, the processor supports execute-only  translations by EPT. This support allows software to 
configure EPT paging-structure entries in which bits 1:0 are clear (indicating that data accesses are not 
allowed) and bit 2 is set (indicating that instruction fetches are allowed).1 
•Bit 6 indicates support for a page-walk length of 4.
•Bit 7 indicates support for a page-walk length of 5.
•If bit 8 is read as 1, the logical processor allows soft ware to configure the EPT paging-structure memory type 
to be uncacheable (UC); see Section 25.6.11.
•If bit 14 is read as 1, the logical processor allows soft ware to configure the EPT paging-structure memory type 
to be write-back (WB).
•If bit 16 is read as 1, the logical processor allows software to configure a EPT PDE to map a 2-Mbyte page (by 
setting bit 7 in the EPT PDE). 
•If bit 17 is read as 1, the logical processor allows soft ware to configure a EPT PDPTE to map a 1-Gbyte page (by 
setting bit 7 in the EPT PDPTE). 
•Support for the INVEPT instruction (see Chapter 31 and Section 29.4.3.1):
— If bit 20 is read as 1, the INVEPT instruction is supported.— If bit 25 is read as 1, the single -context INVEPT type is supported.
— If bit 26 is read as 1, the all- context INVEPT type is supported.
•If bit 21 is read as 1, accessed and dirty flags for EPT are supported (see Section 29.3.5).
•If bit 22 is read as 1, the processor reports advanced VM-exit information for EPT violations (see Section 
28.2.1). This reporting is done only if this bit is read as 1.
•If bit 23 is read as 1, supervisor shadow-sta ck control is supported (see Section 29.3.3.2).
•Support for the INVVPID instruction (see Chapter 31 and Section 29.4.3.1):
— If bit 32 is read as 1, the INVVPID instruction is supported.
— If bit 40 is read as 1, the individu al-address INVVPID type is supported.
— If bit 41 is read as 1, the single-context INVVPID type is supported.
— If bit 42 is read as 1, the all- context INVVPID type is supported.
— If bit 43 is read as 1, the single-context-r etaining-globals INVVPID type is supported.
•Bits 53:48 enumerate the maximum HLAT prefix size. It is expected that any processor that supports the 1-
setting of the “enable HLAT” VM-execution control will enumerate this value as 1. See Section 4.5.1.
•Bits 5:1, bits 13:9, bit 15, bits 19:18, bit 24, bits 31:27, bits 39:33, bits 47:44, and bits 63:54 are reserved 
and are read as 0.
The IA32_VMX_EPT_VPID_CAP MSR exists only on processors  that support the 1-setting of the “activate secondary 
controls” VM-execution control (only if bit 63 of the IA32_VMX_PROCBASED_CTLS MSR is 1) and that support 
either the 1-setting of the “enable EPT” VM-execution control (only if bit 33 of the IA32_VMX_PROCBASED_CTLS2 
MSR is 1) or the 1-setting of the “enable VPID ” VM-execution control (only if bit 37 of the 
IA32_VMX_PROCBASED_CTLS2 MSR is 1).
1. If the “mode-based execute control for EPT”  VM-execution control is 1,  setting bit 0 indicates also  that software may also co nfigure 
EPT paging-structure entries in which bits 1:0 are both clear and in which bit 10  is set (indicating a translation that can be used to 
fetch instructions from a supervisor-mode linear address or a user-mode linear address).Vol. 3D A-9VMX CAPABILITY REPORTING FACILITY
A.11 VM FUNCTIONS
The IA32_VMX_VMFUNC MSR (index 491H) reports on th e allowed settings of the VM-function controls (see 
Section 25.6.14). VM entry allows bit X of the VM-function controls  to be 1 if bit X in the MSR is set to 1; if bit X in 
the MSR is cleared to 0, VM entry fails if bit X of the VM -function controls, the “activate secondary controls” primary 
processor-based VM-execution control, and the “enable VM functions” secondary processor-based VM-execution 
control are all 1.
The IA32_VMX_VMFUNC MSR exists only on processors th at support the 1-setting of the “activate secondary 
controls” VM-execution control (only if bit 63 of the IA 32_VMX_PROCBASED_CTLS MSR is 1) and the 1-setting of 
the “enable VM functions” secondary processor-based VM-execution control (only if bit 45 of the IA32_VMX_PROCBASED_CTLS2 MSR is 1).A-10 Vol. 3DVMX CAPABILITY REPORTING FACILITYVol. 3D B-1APPENDIX B
Every component of the VMCS is encoded by a 32-bit field that can be used by VMREAD and VMWRITE. Section 
25.11.2 describes the structure of the encoding space (t he meanings of the bits in each 32-bit encoding).

25.11.2 describes the structure of the encoding space (t he meanings of the bits in each 32-bit encoding). 
This appendix enumerates all fields in the VMCS and thei r encodings. Fields are grouped by width (16-bit, 32-bit, 
etc.) and type (guest-s tate, host-state, etc.).
B.1 16-BIT FIELDS
A value of 0 in bits 14:13 of an encoding indicates a 16-bi t field. Only guest-state areas and the host-state area 
contain 16-bit fields. As noted in Section 25.11.2, each 16-b it field allows only full access, meaning that bit 0 of its 
encoding is 0. Each such encoding is thus an even number.
B.1.1  16-Bit Control Fields
A value of 0 in bits 11:10 of an encoding indicates a contro l field. These fields are dist inguished by their index value 
in bits 9:1. Table B-1 enumerates the 16-bit control fields.
B.1.2  16-Bit Guest-State Fields
A value of 2 in bits 11:10 of an encoding indicates a field in the guest-state area. These fields are distinguished by 
their index value in bits 9:1. Table B-2 enumerates 16-bit guest-state fields.Table B-1.  Encoding for 16-Bit Control Fi elds (0000_00xx_xxxx_xxx0B)
Field Name Index Encoding
Virtual-processor identifier (VPID)1
NOTES:
1. This field exists only on proces sors that support the 1- setting of the “enable VP ID” VM-execution control.000000000B 00000000H
Posted-interrupt notification vector2
2. This field exists only on processors  that support the 1-setting of the “process posted interr upts” VM-execu tion control.000000001B 00000002H
EPTP index3
3. This field exists only on processo rs that support the 1-setting of the “E PT-violation #VE” VM -execution control.000000010B 00000004H
HLAT prefix size4
4. This field exists only on proces sors that support the 1- setting of the “enable HL AT” VM-execution control.000000011B 00000006H
Last PID-pointer index5
5. This field exists only on processo rs that support the 1-setting of the “I PI virtualization” VM-execution control.000000100B 00000008H
Table B-2.  Encodings for 16-Bit Guest-State Fields  (0000_10xx_xxxx_xxx0B)
Guest ES selector 000000000B 00000800H
Guest CS selector 000000001B 00000802H
Guest SS selector 000000010B 00000804HGuest DS selector 000000011B 00000806H
Guest FS selector 000000100B 00000808HB-2 Vol. 3DFIELD ENCODING IN VMCS
B.1.3  16-Bit Host-State Fields
A value of 3 in bits 11:10 of an encoding indicates a field in the host-state area. These fields are distinguished by 
their index value in bits 9:1. Table B-3 enumerates the 16-bit host-state fields.
B.2 64-BIT FIELDS
A value of 1 in bits 14:13 of an encoding indicates a 64-bit  field. There are 64-bit fields only for controls and for 
guest state. As noted in Section 25.11.2, every 64-bit fi eld has two encodings, which differ on bit 0, the access 
type. Thus, each such field has an even encoding for full access and an odd encoding for high access.
B.2.1  64-Bit Control Fields
A value of 0 in bits 11:10 of an encoding indicates a contro l field. These fields are distinguished by their index value 
in bits 9:1. Table B-4 enumerates the 64-bit control fields.Guest GS selector 000000101B 0000080AH
Guest LDTR selector 000000110B 0000080CHGuest TR selector 000000111B 0000080EH
Guest interrupt status
1000001000B 00000810H
PML index2000001001B 00000812H
Guest UINV3000001010B 00000814H
NOTES:
1. This field exists only on processors that support the 1-se tting of the “virtual-interrupt delivery” VM-execution control.
2. This field exists only on proce ssors that support the 1- setting of the “enable PM L” VM-execution control.
3. This field exists only on processors that support the 1-setti ng of either the “cle ar UINV” VM-exit control or the “load UINV ” VM-entry 
control.
Table B-3.  Encodings for 16-Bit Ho st-State Fields (0000_11xx_xxxx_xxx0B)
Host ES selector 000000000B 00000C00H
Host CS selector 000000001B 00000C02HHost SS selector 000000010B 00000C04HHost DS selector 000000011B 00000C06H
Host FS selector 000000100B 00000C08H
Host GS selector 000000101B 00000C0AHHost TR selector 000000110B 00000C0CH
Table B-4.  Encodings for 64-Bit  Control Fields (0010_00xx_xxxx_xxxAb)
Address of I/O bitmap A (full)
000000000B00002000H
Address of I/O bitmap A (high) 00002001H
Address of I/O bitmap B (full)
000000001B00002002H
Address of I/O bitmap B (high) 00002003HTable B-2.  Encodings for 16-Bit Guest-St ate Fields (0000_10 xx_xxxx_xxx0B) (Contd.)
Field Name Index EncodingVol. 3D B-3FIELD ENCODING IN VMCS
Address of MSR bitmaps (full)1
000000010B00002004H
Address of MSR bitmaps (high)100002005H
VM-exit MSR-store address (full)
000000011B00002006H
VM-exit MSR-stor e address (high) 00002007H
VM-exit MSR-load  address (full)
000000100B00002008H
VM-exit MSR-load address (high) 00002009H
VM-entry MSR-load  address (full)
000000101B0000200AH
VM-entry MSR-load address (high) 0000200BH
Executive-VMCS pointer (full)
000000110B0000200CH
Executive-VMCS pointer (high) 0000200DH
PML address (full)2
000000111B0000200EH
PML address (high)20000200FH
TSC offset (full)
000001000B00002010H
TSC offset (high) 00002011H
Virtual-APIC address (full)3
000001001B00002012H
Virtual-APIC address (high)300002013H
APIC-access address (full)4
000001010B00002014H
APIC-access address (high)400002015H
Posted-interrupt descriptor address (full)5
000001011B00002016H
Posted-interrupt descriptor address (high)500002017H
VM-function controls (full)6
000001100B00002018H
VM-function controls (high)600002019H
EPT pointer (EPTP; full)7
000001101B0000201AH
EPT pointer (EPTP; high)70000201BH
EOI-exit bitmap 0 (EOI_EXIT0; full)8
000001110B0000201CH
EOI-exit bitmap 0 (EOI_EXIT0; high)80000201DH
EOI-exit bitmap 1 (EOI_EXIT1; full)8
000001111B0000201EH
EOI-exit bitmap 1 (EOI_EXIT1; high)80000201FH
EOI-exit bitmap 2 (EOI_EXIT2; full)8
000010000B00002020H
EOI-exit bitmap 2 (EOI_EXIT2; high)800002021H
EOI-exit bitmap 3 (EOI_EXIT3; full)8
000010001B00002022H
EOI-exit bitmap 3 (EOI_EXIT3; high)800002023H
EPTP-list address (full)9
000010010B00002024H
EPTP-list address (high)900002025H
VMREAD-bitmap address (full)10
000010011B00002026H
VMREAD-bitmap address (high)1000002027H
VMWRITE-bitmap address (full)10
000010100B00002028H
VMWRITE-bitmap address (high)1000002029HTable B-4.  Encodings for 64-Bit Cont rol Fields (0010_00 xx_xxxx_xxxAb) (Contd.)
Field Name Index EncodingB-4 Vol. 3DFIELD ENCODING IN VMCS
Virtualization-exception information address (full)11
000010101B0000202AH
Virtualization-exception information address (high)110000202BH
XSS-exiting bitmap (full)12
000010110B0000202CH
XSS-exiting bitmap (high)120000202DH
ENCLS-exiting bitmap (full)13
000010111B0000202EH
ENCLS-exiting bitmap (high)130000202FH
Sub-page-permission-t able pointer (full)14
000011000B00002030H
Sub-page-permission-table pointer (high)1400002031H
TSC multiplier (full)15
000011001B00002032H
TSC multiplier (high)1500002033H
Tertiary processor-based VM-execution controls (full)16
000011010B00002034H
Tertiary processor-based VM-execution controls (high)1600002035H
ENCLV-exiting bitmap (full)17
000011011B00002036H
ENCLV-exiting bitmap (high)1700002037H
Low PASID directory address (full)18
000011100B00002038H
Low PASID directory address (high)1800002039H
High PASID directory address (full)18
000011101B0000203AH
High PASID directory address (high)180000203BH
Shared EPT pointer (full)19
000011110B0000203CH
Shared EPT pointer (high)190000203DH
PCONFIG-exiting bitmap (full)20
000011111B0000203EH
PCONFIG-exiting bitmap (high)200000203FH
Hypervisor-managed linear-address translation pointer (HLATP; full)21
000100000B00002040H
HLATP (high)2100002041H
PID-pointer table address (full)22
000100001B00002042H
PID-pointer table address (high)2200002043H
Secondary VM-exit controls (full)23
000100010B00002044H
Secondary VM-exit controls (high)2300002045H
IA32_SPEC_CTRL mask (full)24
000100101B0000204AH
IA32_SPEC_CTRL mask (high)240000204BH
IA32_SPEC_CTRL shadow (full)24
000100110B0000204CH
IA32_SPEC_CTRL shadow (high)240000204DH
NOTES:
1. This field exists only on processors that support th e 1-setting of the “use MSR bi tmaps” VM-execution control.
3. This field exists only on processo rs that support the 1-setti ng of the “use TPR shad ow” VM-execution control.
4. This field exists only on processors  that support the 1- setting of the “virtualize APIC accesses” VM-exe cution control.
5. This field exists only on processors that support the 1-se tting of the “process  posted interrupts” VM-execution control.
6. This field exists only on processors  that support the 1-setting  of the “enable VM functi ons” VM-execution control.
7. This field exists only on proce ssors that support the 1- setting of the “enable EP T” VM-execution control.Table B-4.  Encodings for 64-Bit Co ntrol Fields (0010_ 00xx_xxxx_xxxAb) (Contd.)
Field Name Index EncodingVol. 3D B-5FIELD ENCODING IN VMCS
B.2.2  64-Bit Read-Only Data Field
A value of 1 in bits 11:10 of an encoding indicates a read -only data field. These fields are distinguished by their

A value of 1 in bits 11:10 of an encoding indicates a read -only data field. These fields are distinguished by their 
index value in bits 9:1. There is only one such 64-bit field as given in Table B-5.(As with other 64-bit fields, this one 
has two encodings.)
B.2.3  64-Bit Guest-State Fields
their index value in bits 9:1. Table B-6 enumerates the 64-bit guest-state fields.8. This field exists only on processors that support the 1-se tting of the “virtual-interrupt delivery” VM-exe cution control.
9. This field exists only on proce ssors that support the 1-se tting of the “EPTP switching” VM-function control.
10. This field exists only on processo rs that support the 1-setti ng of the “VMCS shadowing” VM-execution control.
11. This field exists only on processo rs that support the 1-setti ng of the “EPT-violation #VE” VM-execution control.
12. This field exists only on processors  that support the 1-setting  of the “enable XSAVES/XRSTORS” VM-execution control.
13. This field exists only on processors  that support the 1-setting  of the “enable ENCLS exiting” VM-execution control.
14. This field exists only on processors that support the 1-setting of  the “sub-page write permissions for EPT” VM-execution co ntrol.
15. This field exists only on processo rs that support the 1-setti ng of the “use TSC scalin g” VM-execution control.
16. This field exists only on processors that support the 1-setting of  the “activate tertiary cont rols” VM-execution control.
17. This field exists only on processors  that support the 1-setting  of the “enable ENCLV exiting” VM-execution control.
18. This field exists only on processo rs that support the 1-setti ng of the “PASID translat ion” VM-execu tion control.
19. This field exists only on proces sors that support the 1- setting of the “s hared-EPTP” VM-execution control.
20. This field exists only on processo rs that support the 1-setti ng of the “enable PCONFIG” VM-execution control.
21. This field exists only on proces sors that support the 1- setting of the “enable HL AT” VM-execution control.
22. This field exists only on processo rs that support the 1-setti ng of the “IPI virtualiza tion” VM-execu tion control.
23. This field exists only on processors  that support the 1-setting  of the “activate secondary controls” VM-exit control.
24. This field exists only on processors  that support the 1-setting of the “virtualize IA32_SPEC_CTRL” VM-execution control.
Table B-5.  Encodings for 64-Bit Re ad-Only Data Fiel d (0010_01xx_xxxx_xxxAb)
Guest-physical address (full)1
NOTES:
1. This field exists only on proce ssors that support the 1-setting of the “enable EPT” VM-execution control.000000000B00002400H
Guest-physical address (high)100002401H
Table B-6.  Encodings for 64-Bit Guest-State Fields  (0010_10xx_xxxx_xxxAb)
VMCS link pointer (full)
000000000B00002800H
VMCS link pointer (high) 00002801H
Guest IA32_DEBUGCTL (full)
000000001B00002802H
Guest IA32_DEBUGCTL (high) 00002803H
Guest IA32_PAT (full)1
000000010B00002804H
Guest IA32_PAT (high)100002805H
Guest IA32_EFER (full)2
000000011B00002806H
Guest IA32_EFER (high)200002807HB-6 Vol. 3DFIELD ENCODING IN VMCS
B.2.4  64-Bit Host-State Fields
their index value in bits 9:1. Table B-7 enumerates the 64-bit control fields.Guest IA32_PERF_GLOBAL_CTRL (full)3
000000100B00002808H
Guest IA32_PERF_GLOBAL_CTRL (high)300002809H
Guest PDPTE0 (full)4
000000101B0000280AH
Guest PDPTE0 (high)40000280BH
Guest PDPTE1 (full)4
000000110B0000280CH
Guest PDPTE1 (high)40000280DH
Guest PDPTE2 (full)4
000000111B0000280EH
Guest PDPTE2 (high)40000280FH
Guest PDPTE3 (full)4
000001000B00002810H
Guest PDPTE3 (high)400002811H
Guest IA32_BNDCFGS (full)5
000001001B00002812H
Guest IA32_BNDCFGS (high)500002813H
Guest IA32_RTIT_CTL (full)6
000001010B00002814H
Guest IA32_RTIT_CTL (high)600002815H
Guest IA32_LBR_CTL (full)7
000001011B00002816H
Guest IA32_LBR_CTL (high)700002817H
Guest IA32_PKRS (full)8
000001100B00002818H
Guest IA32_PKRS (high)800002819H
NOTES:
1. This field exists only on processors th at support either the 1-setting  of the “load IA32_PAT” VM-e ntry control or that of th e “save 
2. This field exists only on processors th at support either the 1-setting  of the “load IA32_EFER” VM-entry control or that of t he “save 
3. This field exists only on processors  that support the 1- setting of the “load IA32_PERF_ GLOBAL_CTRL” VM-entry control.
4. This field exists only on proce ssors that support the 1- setting of the “enable EP T” VM-execution control.
5. This field exists only on processors th at support either the 1-setting  of the “load IA32_BNDCFGS” VM-entry control or that o f the 
“clear IA32_BNDCFGS” VM-exit control.
6. This field exists only on processors th at support either the 1-setting  of the “load IA32_RTIT_CTL” VM-entry control or that of the 
“clear IA32_RTIT_CTL” VM-exit control.
7. This field exists only on processors that support either th e 1-setting of the “loa d IA32_LBR_CTL” VM-entry control or that o f the
“clear IA32_LBR_CTL” VM-exit control.
8. This field exists only on proc essors that support  the 1-setting of the “loa d PKRS” VM-entry control.
Table B-7.  Encodings for 64-Bit Host-State Fields  (0010_11xx_xxxx_xxxAb)
Host IA32_PAT (full)1
000000000B00002C00H
Host IA32_PAT (high)100002C01HTable B-6.  Encodings for 64-Bit Guest- State Fields (0010_ 10xx_xxxx_xxxAb) (Contd.)
Field Name Index EncodingVol. 3D B-7FIELD ENCODING IN VMCS
B.3 32-BIT FIELDS
A value of 2 in bits 14:13 of an encoding indicates a 32-bit field. As noted in Section 25.11.2, each 32-bit field 
allows only full access, meaning that bit 0 of its encodi ng is 0. Each such encoding is thus an even number.
B.3.1  32-Bit Control Fields
in bits 9:1. Table B-8 enumerates the 32-bit control fields.Host IA32_EFER (full)2
000000001B00002C02H
Host IA32_EFER (high)200002C03H
Host IA32_PERF_GLOBAL_CTRL (full)3
000000010B00002C04H
Host IA32_PERF_GL OBAL_CTRL (high)300002C05H
Host IA32_PKRS (full)4
000000011B00002C06H
Host IA32_PKRS (high)400002C07H
NOTES:
1. This field exists only on proc essors that suppor t the 1-setting of the “loa d IA32_PAT” VM-exit control.
2. This field exists only on proc essors that suppor t the 1-setting of the “loa d IA32_EFER” VM-exit control.
3. This field exists only on processors  that support the 1-setting  of the “load IA32_PERF_GLOBAL_CTRL” VM-exit control.
4. This field exists only on proc essors that support th e 1-setting of the “loa d PKRS” VM-exit control.
Table B-8.  Encodings for 32-Bit Control Fields (0100_00xx_xxxx_xxx0B)
Pin-based VM-execution controls 000000000B 00004000HPrimary processor-based VM-execution controls 000000001B 00004002H
Exception bitmap 000000010B 00004004H
Page-fault error-code mask 000000011B 00004006HPage-fault error-code match 000000100B 00004008H
CR3-target count 000000101B 0000400AH
Primary VM-exit controls 000000110B 0000400CHVM-exit MSR-store count 000000111B 0000400EH
VM-exit MSR-load count 000001000B 00004010H
VM-entry controls 000001001B 00004012HVM-entry MSR-load count 000001010B 00004014H
VM-entry interruption-information field 000001011B 00004016H
VM-entry exception error code 000001100B 00004018HVM-entry instruction length 000001101B 0000401AH
TPR threshold
1000001110B 0000401CH
Secondary processor-based VM-execution controls2000001111B 0000401EH
PLE_Gap3000010000B 00004020HTable B-7.  Encodings for 64-Bit Host-State  Fields (0010_11 xx_xxxx_xxxAb) (Contd.)
Field Name Index EncodingB-8 Vol. 3DFIELD ENCODING IN VMCS
B.3.2  32-Bit Read-Only Data Fields
index value in bits 9:1. Table B-9 enumerates the 32-bit read-only data fields.
B.3.3  32-Bit Guest-State Fields
their index value in bits 9:1. Table B-10 enumerates the 32-bit guest-state fields.PLE_Window3000010001B 00004022H
Instruction-ti meout control4000010010B 00004024H
NOTES:
1. This field exists only on processo rs that support the 1-setti ng of the “use TPR shad ow” VM-execution control.
2. This field exists only on processors that support the 1-se tting of the “activate secondary controls” VM-execution control.
3. This field exists only on processo rs that support the 1-setti ng of the “PAUSE-loop exiting” VM-execution control.
4. This field exists only on processors  that support the 1-setting  of the “instruction timeout” VM-execution control.
Table B-9.  Encodings for 32-Bit Read -Only Data Fields (0100_01xx_xxxx_xxx0B)
VM-instruction error 000000000B 00004400HExit reason 000000001B 00004402H

NOTES:
VM-exit interruption information 000000010B 00004404H
VM-exit interruption error code 000000011B 00004406HIDT-vectoring information field 000000100B 00004408HIDT-vectoring error code 000000101B 0000440AH
VM-exit instruction length 000000110B 0000440CH
VM-exit instruction information 000000111B 0000440EH
Table B-10.  Encodings for 32-Bit Gu est-State Fields (0100_10xx_xxxx_xxx0B)
Guest ES limit 000000000B 00004800H
Guest CS limit 000000001B 00004802H
Guest SS limit 000000010B 00004804HGuest DS limit 000000011B 00004806H
Guest FS limit 000000100B 00004808H
Guest GS limit 000000101B 0000480AHGuest LDTR limit 000000110B 0000480CH
Guest TR limit 000000111B 0000480EH
Guest GDTR limit 000001000B 00004810HGuest IDTR limit 000001001B 00004812H
Guest ES access rights 000001010B 00004814HTable B-8.  Encodings for 32-Bit Cont rol Fields (0100_00xx_xxxx_xxx0B) (Contd.)
Field Name Index EncodingVol. 3D B-9FIELD ENCODING IN VMCS
The limit fields for GDTR and IDTR are defined to be 32 bits  in width even though these fields are only 16-bits wide 
in the Intel 64 and IA-32 architectures. VM entry ensures that  the high 16 bits of both these fields are cleared to 0.
B.3.4  32-Bit Host-State Field
A value of 3 in bits 11:10 of an encoding indicates a field in the host-state area. There is only one such 32-bit field 
as given in Table B-11.
B.4 NATURAL-WIDTH FIELDS
A value of 3 in bits 14:13 of an encoding indicates a natura l-width field. As noted in Section 25.11.2, each of these 
fields allows only full access, meaning that bit 0 of its en coding is 0. Each such encoding is thus an even number.
B.4.1  Natural-Width Control Fields
in bits 9:1. Table B-12 enumerates the natural-width control fields.Guest CS access rights 000001011B 00004816H
Guest SS access rights 000001100B 00004818HGuest DS access rights 000001101B 0000481AH
Guest FS access rights 000001110B 0000481CH
Guest GS access rights 000001111B 0000481EHGuest LDTR access rights 000010000B 00004820H
Guest TR access rights 000010001B 00004822H
Guest interruptibility state 000010010B 00004824HGuest activity state 000010011B 00004826H
Guest SMBASE 000010100B 00004828H
Guest IA32_SYSENTER_CS 000010101B 0000482AHVMX-preemption  timer value
1000010111B 0000482EH
NOTES:
1. This field exists only on processors that support the 1-setti ng of the “activate VMX-preemption timer” VM-execution control.
Table B-11.  Encoding for 32-Bit Host-State Field (0100_11xx_xxxx_xxx0B)
Host IA32_SYSENTER_CS 000000000B 00004C00H
Table B-12.  Encodings for Natural-Wi dth Control Fields (0110_00xx_xxxx_xxx0B)
CR0 guest/host mask 000000000B 00006000H
CR4 guest/host mask 000000001B 00006002H
CR0 read shadow 000000010B 00006004HCR4 read shadow 000000011B 00006006HTable B-10.  Encodings for 32-Bit Guest- State Fields (0100_ 10xx_xxxx_xxx0B) (Contd.)
Field Name Index EncodingB-10 Vol. 3DFIELD ENCODING IN VMCS
B.4.2  Natural-Width Read-Only Data Fields
index value in bits 9:1. Table B-13 enumerates the natural-width read-only data fields.
B.4.3  Natural-Width Guest-State Fields
their index value in bits 9:1. Table B-14 enumerates the natural-width guest-state fields.CR3-target value 0 000000100B 00006008H
CR3-target value 1 000000101B 0000600AHCR3-target value 2 000000110B 0000600CH
CR3-target value 3
1000000111B 0000600EH
NOTES:
1. If a future implementa tion supports more than 4 CR3-target values, they will be encoded consecutively following the 4 encodi ngs 
given here.
Table B-13.  Encodings for Natural-Width Read-Only Data Fields  (0110_01xx_xxxx_xxx0B)
Exit qualification 000000000B 00006400H
I/O RCX 000000001B 00006402H
I/O RSI 000000010B 00006404H
I/O RDI 000000011B 00006406H
I/O RIP 000000100B 00006408H
Guest-linear address 000000101B 0000640AH
Table B-14.  Encodings for Natural-Widt h Guest-State Fields  (0110_10xx_xxxx_xxx0B) 
Guest CR0 000000000B 00006800H
Guest CR3 000000001B 00006802HGuest CR4 000000010B 00006804H
Guest ES base 000000011B 00006806H
Guest CS base 000000100B 00006808HGuest SS base 000000101B 0000680AH
Guest DS base 000000110B 0000680CH
Guest FS base 000000111B 0000680EHGuest GS base 000001000B 00006810H
Guest LDTR base 000001001B 00006812H
Guest TR base 000001010B 00006814HGuest GDTR base 000001011B 00006816HTable B-12.  Encodings for Natural-Width Control Fields (0110_ 00xx_xxxx_xxx0B) (Contd.)
Field Name Index EncodingVol. 3D B-11FIELD ENCODING IN VMCS
The base-address fields for ES, CS, SS, and DS in the guest- state area are defined to be natural-width (with 64 bits 
on processors supporting Intel 64 architecture) even though these fields are only 32-bits wide in the Intel 64 archi-
tecture. VM entry ensures that the high 32 bits of these fields are cleared to 0.
B.4.4  Natural-Width Host-State Fields
their index value in bits 9:1. Table B-15 enumerates the natural-width host-state fields.Guest IDTR base 000001100B 00006818H
Guest DR7 000001101B 0000681AHGuest RSP 000001110B 0000681CH
Guest RIP 000001111B 0000681EH
Guest RFLAGS 000010000B 00006820HGuest pending debug exceptions 000010001B 00006822H
Guest IA32_SYSENTER_ESP 000010010B 00006824H
Guest IA32_SYSENTER_EIP 000010011B 00006826HGuest IA32_S_CET
1000010100B 00006828H
Guest SSP1000010101B 0000682AH
Guest IA32_INTERRUPT_SSP_TABLE_ADDR1000010110B 0000682CH
NOTES:
1. This field is supported only on pr ocessors that support the 1-setting of the “load CET state” VM-entry control.
Table B-15.  Encodings for Natural-Widt h Host-State Fields  (0110_11xx_xxxx_xxx0B) 
Host CR0 000000000B 00006C00H
Host CR3 000000001B 00006C02HHost CR4 000000010B 00006C04H
Host FS base 000000011B 00006C06H
Host GS base 000000100B 00006C08HHost TR base 000000101B 00006C0AH
Host GDTR base 000000110B 00006C0CH
Host IDTR base 000000111B 00006C0EHHost IA32_SYSENTER_ESP 000001000B 00006C10H
Host IA32_SYSENTER_EIP 000001001B 00006C12H
Host RSP 000001010B 00006C14HHost RIP 000001011B 00006C16H
Host IA32_S_CET
1
NOTES:
1. This field is supported only on pr ocessors that support the 1-setting of the “load CE T state” VM-exit control.000001100B 00006C18H
Host SSP1000001101B 00006C1AH
Host IA32_INTERRUPT_SSP_TABLE_ADDR1000001110B 00006C1CHTable B-14.  Encodings for Natu ral-Width Guest-State Fields (0110_10xx_xxxx_xxx0B)  (Contd.)
Field Name Index EncodingB-12 Vol. 3DFIELD ENCODING IN VMCSVol. 3D C-1APPENDIX C
VMX BASIC EXIT REASONS
Every VM exit writes a 32-bit exit reason to the VMCS (s ee Section 25.9.1). Certain VM-entry failures also do this 
(see Section 27.8). The low 16 bits of the exit-reason fiel d form the basic exit reason which provides basic informa-
tion about the cause of the VM exit or VM-entry failure.
Table C-1 lists values for basic exit reasons and explains their meaning. Entries apply to VM exits, unless otherwise 
noted.
Table C-1.  Basic Exit Reasons 
Basic Exit 
Reason Description
0 Exception or non-maskable interrupt (NMI).  Either:
1: Guest software caused an exception and the bit in the exception bitmap associated with exception’s vector was 
1. This case includes executions of BOUND that cause #BR, executions of INT1 (they cause #DB), executions of 
INT3 (they cause #BP), executions of INTO that cause #OF, and executions of UD0, UD1, and UD2 (they cause 
#UD).
2: An NMI was delivered to the logical processor and the “NMI exiting” VM-execution control was 1.
1 External interrupt.  An external interrupt arrived and the “external-interrupt exiting” VM-execution control was 1.
2 Triple fault.  The logical processor encountered an exception whil e attempting to call the double-fault handler and 
that exception did not itself cause a VM exit due to the exception bitmap.
3 INIT signal.  An INIT signal arrived
4 Start-up IPI (SIPI). A SIPI arrived while the logical processor was in the “wait-for-SIPI” state.
5 I/O system-management interrupt (SMI). An SMI arrived immediately after retirement of an I/O instruction and 
caused an SMM VM exit (see Section 32.15.2).
6 Other SMI. An SMI arrived and caused an SMM VM exit (see Section 32.15.2) but not immediately after retirement of 
an I/O instruction.
7 Interrupt window.  At the beginning of an instruct ion, RFLAGS.IF was 1; events were  not blocked by STI or by MOV 
SS; and the “interrupt-window exiting” VM-execution control was 1.
8 NMI window.  At the beginning of an instruction, there was no virtual-NMI blocking; events were not blocked by MOV

8 NMI window.  At the beginning of an instruction, there was no virtual-NMI blocking; events were not blocked by MOV 
SS; and the “NMI-window exiting” VM-execution control was 1.
9 Task switch.  Guest software atte mpted a task switch.
10 CPUID.  Guest software attempted to execute CPUID.
11 GETSEC. Guest software attempted to execute GETSEC.
12 HLT. Guest software attempted to execute HLT and the “HLT exiting” VM-execution control was 1.
13 INVD. Guest software attemp ted to execute INVD.
14 INVLPG. Guest software attempted to execute INVLPG and the “INVLPG exiting” VM-execution control was 1.
15 RDPMC.  Guest software attempte d to execute RDPMC and the “RDPMC exiting” VM-execution control was 1.
16 RDTSC. Guest software atte mpted to execute RDTSC and the “RDTSC exiting” VM-executi on control was 1.
17 RSM. Guest software a ttempted to execute RSM in SMM.
18 VMCALL.  VMCALL was executed either by guest software (cau sing an ordinary VM exit) or by the executive monitor 
(causing an SMM VM exit; see Section 32.15.2).
19 VMCLEAR.  Guest software attemp ted to execute VMCLEAR.
20 VMLAUNCH. Guest software attempted to execute VMLAUNCH.
21 VMPTRLD. Guest software attempted to execute VMPTRLD.
22 VMPTRST.  Guest software  attempted to execute VMPTRST.C-2 Vol. 3DVMX BASIC EXIT REASONS
23 VMREAD.  Guest software attemp ted to execute VMREAD.
24 VMRESUME. Guest software attempted to execute VMRESUME.
25 VMWRITE. Guest software attempte d to execute VMWRITE.
26 VMXOFF. Guest software attemp ted to execute VMXOFF.
27 VMXON. Guest software attemp ted to execute VMXON.
28 Control-register accesses. Guest software attempted to  access CR0, CR3, CR4, or  CR8 using CLTS, LMSW, or 
MOV CR and the VM-execution cont rol fields indicate that a VM exit should occur (see Section 26.1 for details). This 
basic exit reason is not used for trap-like VM exits following  executions of the MOV to CR8 instruction when the “use 
TPR shadow” VM-execution contro l is 1. Such VM exits inst ead use basic exit reason 43.
29 MOV DR. Guest software attempted a MOV to or from a debug register and the “MOV-DR exiting” VM-execution 
control was 1.
30 I/O instruction. Guest software a ttempted to execute an I/ O instruction and either:
1: The “use I/O bitmaps” VM-execution control was 0 and th e “unconditional I/O exiting” VM-execution control was 1.
2: The “use I/O bitmaps” VM-execution control was 1 and a bit in the I/O bitm ap associated with one of the ports 
accessed by the I/O instruction was 1.
31 RDMSR.  Guest software attempted to  execute RDMSR and either:
1: The “use MSR bitmaps” VM -execution control was 0.
2: The value of RCX is neither in the range 00000000H – 00001FFFH nor in the range C0000000H – C0001FFFH.3: The value of RCX was in the range 00000000H – 00001FFFH and the n
th bit in read bitmap for low MSRs is 1, 
where n was the value of RCX.
4: The value of RCX is in the range C0000000H – C0001FFFH and the nth bit in read bitmap for high MSRs is 1, where 
n is the value of RCX & 00001FFFH.
32 WRMSR. Guest software attempted to execute WRMSR and either:
th bit in write bitmap for low MSRs is 1, 
4: The value of RCX is in the range C0000000H – C0001FFFH and the nth bit in write bitmap for high MSRs is 1, 
where n is the value of RCX & 00001FFFH.
33 VM-entry failure due to invalid guest state. A VM entry failed one of the checks identified in Section 27.3.1.
34 VM-entry failure due to MSR loading.  A VM entry failed in an attempt to load MSRs. See Section 27.4.
36 MWAIT. Guest software atte mpted to execute MWAIT and the “MWAIT exiting” VM-execution control was 1.
37 Monitor trap flag.  A VM exit occurred due to the 1-setting of the “monitor trap flag” VM-execution control (see 
Section 26.5.2) or VM entry injected  a pending MTF VM exit as part of VM entry (see  Section 27.6.2).
39 MONITOR. Guest software a ttempted to execute MONITOR and the “MONITOR exiting” VM-execution control was 1.
40 PAUSE. Either guest software  attempted to execute PAUSE and the “PAUSE  exiting” VM-execution control was 1 or 
the “PAUSE-loop exiting” VM-execution control was 1 and guest software executed a PAUSE loop with execution time exceeding PLE_Window (see Section 26.1.3).
41 VM-entry failure due to machine-check event.  A machine-check event occurred during VM entry (see Section 
27.9).
43 TPR below threshold. The logical processor determined that the value of bits 7:4 of the byte at offset 080H on the 
virtual-APIC page was below that of the TPR threshold VM -execution control field while the “use TPR shadow” VM-
execution control was 1 either as part of TPR virtualization (Section 30.1.2) or VM entry (Section 27.7.7).
44 APIC access.  Guest software attempted to access memory at a physical address on the APIC-access page and the 
“virtualize APIC accesses”  VM-execution control wa s 1 (see Section 30.4).
45 Virtualized EOI.  EOI virtualization was performed for a virtual in terrupt whose vector inde xed a bit set in the EOI-
exit bitmap.Table C-1.  Basic Exit Reasons  (Contd.)
Basic Exit 
Reason DescriptionVol. 3D C-3VMX BASIC EXIT REASONS
46 Access to GDTR or IDTR.  Guest software attempted to execute LGDT, LI DT, SGDT, or SIDT and the “descriptor-table 
exiting” VM-executi on control was 1.
47 Access to LDTR or TR.  Guest software attemp ted to execute LLDT, LTR, SLDT, or STR and the “descriptor-table 
48 EPT violation.  An attempt to access memory with  a guest-physical address was disallowed by the configuration of 
the EPT paging structures.
49 EPT misconfiguration.  An attempt to access memory with a guest-physical address encountered a misconfigured 
EPT paging-structure entry.
50 INVEPT.  Guest software attemp ted to execute INVEPT.
51 RDTSCP. Guest software attempted to execut e RDTSCP and the “enable RDTSCP” an d “RDTSC exiting” VM-execution 
controls were both 1.
52 VMX-preemption timer expired.  The preemption timer counted down to zero.
53 INVVPID.  Guest software attemp ted to execute INVVPID.
54 WBINVD or WBNOINVD.  Guest software atte mpted to execute WBINVD or WBNOINVD and the “WBINVD exiting” 
VM-execution control was 1.
55 XSETBV.  Guest software attemp ted to execute XSETBV.
56 APIC write.  Guest software completed a write to  the virtual-APIC page that must  be virtualized by VMM software 
(see Section 30.4.3.3).
57 RDRAND.  Guest software a ttempted to execute RDRAND and the “RDRAND exiting” VM-execution control was 1.
58 INVPCID. Guest software attempted to execute INVPCID an d the “enable INVPCID” and “INVLPG exiting” 
VM-execution contro ls were both 1.
59 VMFUNC.  Guest software invoked a VM functi on with the VMFUNC instruction an d the VM function either was not 
enabled or generated a function-spe cific condition causing a VM exit.
60 ENCLS.  Guest software a ttempted to execute ENCLS, “enable ENCLS exitin g” VM-execution contro l was 1, and either 
(1) EAX < 63 and the correspondi ng bit in the ENCLS-exiting bitmap is 1; or (2) EAX ≥ 63 and bit 63 in the ENCLS-
exiting bitmap is 1.
61 RDSEED.  Guest software attempted to execute RDSEED and the “RDSEED exitin g” VM-execution control was 1.
62 Page-modification log full.  The processor attempte d to create a page-modification log entry and the value of the 
PML index was not in the range 0–511.
63 XSAVES. Guest software attempted to execute XSAVES, the “e nable XSAVES/XRSTORS” was 1, and a bit was set in 
the logical-AND of the following three values: EDX:EAX, the IA32_XSS MSR, and the XSS-exiting bitmap.
64 XRSTORS. Guest software attempted to execute XRSTORS, the “enable XSAVES/XRSTORS” wa s 1, and a bit was set 
in the logical-AND of the following three values: EDX:EAX, the IA32_XSS MSR, and the XSS-exiting bitmap.
65 PCONFIG.  Guest software atte mpted to execute PCONFIG, “e nable PCONFIG” VM-execution control was 1, and either 
(1) EAX < 63 and the correspondi ng bit in the PCONFIG-exitin g bitmap is 1; or (2) EAX ≥ 63 and bit 63 in the 
PCONFIG-exiting bitmap is 1.
66 SPP-related event.  The processor attempted to determine an access’s sub-page write permission and encountered 
an SPP miss or an SPP misconfiguration. See Section 29.3.4.2.
67 UMWAIT. Guest software attempted to execute UMWAIT and the “enable user wait and pause” and “RDTSC exiting” 
68 TPAUSE. Guest software attempted to execut e TPAUSE and the “enable user wait and pause” and “RDTSC exiting” 
69 LOADIWKEY.  Guest software atte mpted to execute LOADIWKEY and the “LOADIWKEY exiting” VM-execution control 
was 1.Table C-1.  Basic Exit Reasons  (Contd.)
Basic Exit 
Reason DescriptionC-4 Vol. 3DVMX BASIC EXIT REASONS
70 ENCLV. Guest software attemp ted to execute ENCLV, the “enable ENCLV exiting” VM-execution control was 1, and 
either (1) EAX < 63 and the corresponding bit in the ENCLV-exiting bitmap is 1; or (2) EAX ≥ 63 and bit 63 in the

Basic Exit 
either (1) EAX < 63 and the corresponding bit in the ENCLV-exiting bitmap is 1; or (2) EAX ≥ 63 and bit 63 in the 
ENCLV-exiting bitmap is 1.
72 ENQCMD PASID translation failure.  A VM exit occurred during PASID translation because the present bit was clear 
in a PASID-directory entry, the valid bit was clear in a PA SID-table entry, or one of th e entries set a reserved bit.
73 ENQCMDS PASID translation failure. A VM exit occurred during PASID translation because the present bit was clear 
74 Bus lock. The processor asserted a bus lock while the “bus-lock detection” VM -execution contro l was 1. (Such 
VM exits will also set bit 26 of the exit-reason field.)
75 Instruction timeout. The “instruction ti meout” VM-execution control was 1 an d certain operations prevented the 
processor from reaching an instruction boundary within the amount of time specifie d by the instruction-timeout 
control.
76 SEAMCALL.  Guest software attempted to execute SEAMCALL.1
77 TDCALL. Guest software attempted to execute TDCALL.1
NOTES:
1. For more information on the SEAMCALL and TDCALL instructions , refer to the “Intel® Trust Doma in CPU Architectural Extensions  
Specification,” available here: https://c drdv2.intel.com/v1/d l/getContent/733582.Table C-1.  Basic Exit Reasons  (Contd.)
Basic Exit 
Reason DescriptionIntel® 64 and IA-32 Architectures Software
Volume 4: Model-Specific Registers
NOTE:  The Intel 64 and IA-32 Archit ectures Software Developer's Ma nual consists of four volumes:
Order Number:  335592-082US
names and brands may be claimed as the property of others.Vol. 4 iiiCONTENTS
PAGE
CHAPTER 1
1.2 OVERVIEW OF THE MODEL-SPECIFIC REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.2 Reserved Bits and Software Compatibility  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.4 Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.5 Segmented Addressing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.6 Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3.7 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
CHAPTER 2
MODEL-SPECIFIC REGISTERS (MSRS)
2.1 ARCHITECTURAL MSRS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .  2-64
2.3 MSRS IN THE 45 NM AND 32 NM INTEL ATOM® PROCESSOR FAMILY  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-81
2.4 MSRS IN INTEL PROCESSORS BASED ON SILVERMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-94
2.4.1 MSRs with Model-Specific Behavior in the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-110
2.4.2 MSRs in Intel Atom® Processors Based on Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-113
2.5 MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . .  2-115
2.6 MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT PLUS MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . .  2-141
2.7 MSRS IN INTEL ATOM® PROCESSORS BASED ON TREMONT MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .  2-146
2.8 MSRS IN PROCESSORS BASED ON NEHALEM MICROARCHITECTURE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-148
2.8.1 Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .2-170
2.8.2 Additional MSRs in the Intel® Xeon® Processor 7500 Series  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-172
2.9 MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES BASED ON WESTMERE MICROARCHITECTURE  . . . . . . . . . . . . . . .  2-192
2.10 MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY BASED ON WESTMERE MICROARCHITECTURE. . . . . . . . . . . . . . . . . .  2-1932.11 MSRS IN THE INTEL® PROCESSOR FAMILY BASED ON SANDY BRIDGE MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . .  2-196
2.11.1 MSRs in the 2nd Generation Intel® Core™ Processor Family Based on Sandy Bridge Microarchitecture. . . . . . . . . . . . .  .2-218
2.11.2 MSRs in the Intel® Xeon® Processor E5 Family Based on Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . .  . . . . . . .2-224
2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .2-229

2.12 MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY BASED ON IVY BRIDGE MICROARCHITECTURE. . .  2-235
2.12.1 MSRs in the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E Microarchitecture. . . . . . . . . . . . . . . .2-238
2.12.2 Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family. . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .2-250
2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-253
2.13 MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS BASED ON HASWELL MICROARCHITECTURE . . . . . . . . . . .  2-2592.13.1 MSRs in the 4th Generation Intel® Core™ Processor Family Based on Haswell Microarchitecture . . . . . . . . . . . . . . .  . . . .2-264
2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-275
2.14 MSRS IN THE INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . .  2-276
2.14.1 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family  . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .2-289
2.15 MSRS IN THE INTEL® CORE™ M PROCESSORS AND THE 5TH GENERAT ION INTEL® CORE™ PROCESSORS . . . . . . . . . . . . . .  2-305
2.16 MSRS IN THE INTEL® XEON® PROCESSOR E5 V4 FAMILY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-309
2.16.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-319
2.16.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .2-323
2.17 MSRS IN THE 6TH—13TH GENERATI ON INTEL® CORE™ PROCESSORS, 1ST—5T H GENERATION INTEL® XEON® SCALABLE 
PROCESSOR FAMILIES, INTEL® CORE™ ULTRA 7 PROCESSORS , 8TH GENERATION INTEL® CO RE™ I3 PROCESSORS, AND 
INTEL® XEON® E PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-330
2.17.1 MSRs Introduced in 7th Generation and 8th Generation In tel® Core™ Processors Based on Kaby Lake Microarchitecture 
and Coffee Lake Microarchitecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-354
2.17.2 MSRs Specific to 8th Generation Intel® Core™ i3 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-356
2.17.3 MSRs Introduced in 10th Generation Intel® Core™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .2-362
2.17.4 MSRs Introduced in the 11th Generation Intel® Core™ Proc essors based on Tiger Lake Microarchitecture . . . . . . . . . .2 -366
2.17.5 MSRs Introduced in the 12th an d 13th Generation Intel®  Core™ Processors Supporting Performance Hybrid 
Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-369
2.17.6 MSRs Introduced in the Intel® Xeon® Scalable Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-379
2.17.7 MSRs Specific to the 3rd Generation Intel® Xeon® Scalable Processor Family Based on Ice Lake Microarchitecture . .2-396CONTENTS
ivVol. 4PAGE
2.17.8 MSRs Specific to the 4th and 5th Generation Intel® Xeon® Scalable Processor Families. . . . . . . . . . . . . . . . . . .  . . . . . . . . .2-398
2.17.9 MSRs Introduced in the Intel® Core™ Ultra 7 Processor Supporting Performance Hybrid Architecture . . . . . . . . . . . . . .2-409
2.18 MSRS IN THE INTEL® XEON PHI™ PROCESSOR 3200/5 200/7200 SERIES AND THE INTEL® XEON PHI™ PROCESSOR 
7215/7285/7295 SERIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-432
2.19 MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .  2-453
2.19.1 MSRs Unique to Intel® Xeon® Processor MP with L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .2-479
2.20 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-480
2.21 MSRS IN THE PENTIUM M PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-491
2.22 MSRS IN THE P6 FAMILY PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-498
2.23 MSRS IN PENTIUM PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-508Vol. 4 vCONTENTS
PAGE
FIGURES
Figure 1-1. Bit and Byte Order  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7CONTENTS
viVol. 4PAGE
TABLES
Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table 2-2. IA-32 Architectural MSRs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
Table 2-5. MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel 
Value of 06_27H2-93
Table 2-6.  MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures). . . . . . . . . . . . . . . . . . .  . . . . . . . 2-94
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .2-105
Table 2-8. Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel Value of 
06_37H, 06_4AH, 06_5AH, or 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-110
Table 2-9. Specific MSRs Supported by the Intel Atom® Processor E3000 Series with a CPUID Signature DisplayFamily_DisplayModel 
Value of 06_37H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-111
Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series with a CPUID Signature DisplayFamily_DisplayModel 
Value of 06_4DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-112
Table 2-11.  MSRs in Intel Atom® Processors Based on Airmont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-113
Table 2-12.  MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-115
Table 2-13.  MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-141
Table 2-14.  MSRs in Intel Atom® Processors Based on Tremont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-146
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .2-148
Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .2-170

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-172
Table 2-18. Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture . . . . . . . . . . . . . . . . .  . . . . . .2-192
Table 2-19. Additional MSRs Supported by the Intel® Xeon® Processor E7 Family. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .2-194
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture. . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .2-196
Table 2-21. MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture) . . . . . . . . . . . . .2-219
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .2-220
Table 2-23. Additional MSRs Supported by the Intel® Xeon® Proces sors E5 Family Based on Sandy Bridge Microarchitecture 2-224
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . .2-229
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge Microarchitecture . .2-235
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Pr oduct Family (Ivy Bridge-E Microarchitecture)  . . . . . . . . . 2-238
Table 2-27. Additional MSRs Supported by the Intel® Xe on® Processor E7 v2 Family with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .2-250
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-254
Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures . . . . . . . . . . . .2-259
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture). . . . . . . . . . . . . . . . . . . . . . .2-264
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a 
CPUID Signature DisplayFamily_Disp layModel Value of 06_45H2-275
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .2-276
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-290
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .2-305
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors . . . . . . . . . . 2-307
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family 
Based on Broadwell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .2-309
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processo r D with a CPUID Signature Disp layFamily_DisplayModel Value 
of 06_56H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-320
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processo rs with a CPUID Signature Disp layFamily_DisplayModel Value 
of 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-323
Table 2-39. Additional MSRs Supported by the 6th—13th Generation  Intel® Core™ Processors, 1st— 5th Generation Intel® Xeon® 
Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3  Processors, and Intel® Xeon® 
E Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-331
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Ge neration, and 8th Generation Intel® Core™ Processors, and 8th 
generation Intel® Core™ i3 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-352
Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby Lake 
Microarchitecture and Coffee Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-354
Table 2-42. Additional MSRs Supported by the 8th Generati on Intel® Core™ i3 Processors Based on Cannon Lake 
Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-356
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture. . . . . . . . . . . . . 2-360
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) . . . . . . . . . . . . .  . . . .2-363
Table 2-45. Additional MSRs Supported by the 11th Gene ration Intel® Core™ Processors Based on Tiger Lake 
Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-366
Table 2-46. Additional MSRs Supported by the 12th and 13th Ge neration Intel® Core™ Processors Supporting Performance 
Hybrid Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-370Vol. 4 viiCONTENTS
PAGE
Table 2-47. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor P-core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-374
Table 2-48. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor E-core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-375
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . 2-376
Table 2-50. MSRs Supported by the Intel® Xe on® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel 
Value of 06_55H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-379
Table 2-51. MSRs Supported by the 3rd Ge neration Intel® Xeon® Scalable Processor Family with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-396
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-398
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultr a 7 Processors Supporting Performance Hybrid Architecture2-409
Table 2-54. MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 2-430
Table 2-55. MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 2-431
Table 2-56. Selected MSRs Supported by In tel® Xeon Phi™ Processors with a CPUI D Signature DisplayF amily_DisplayModel 
Value of 06_57H or 06_85H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-432
Table 2-57. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_85H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-451
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 2-453

Table 2-59. MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-479
Table 2-60. MSRs Unique to Intel® Xeon® Processor 7100 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 2-480
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processo rs, and Dual-Core Intel® Xeon® Processor LV. . . . . . . . . . .  . . . . 2-480
Table 2-62. MSRs in Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-491
Table 2-63. MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-498
Table 2-64. MSRs in the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-509CONTENTS
viii Vol. 4PAGEVol. 4 1-1CHAPTER 1
The Intel® 64 and IA-32 Architectures Software Developer’s Ma nual, Volume 4: Model-Specific Registers (order 
number 335592) is part of a set that describes the architecture and programming environment of Intel® 64 and IA-
32 architecture processors. Other volumes in this set are:
253665).
Volume 3B, and the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, address the 
programming environment for classes of softwa re that host operating systems. The Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 4, describes th e model-specific registers of Intel 64 and IA-32 proces-
sors.
include: 
•Intel® Core™ 2 Extreme QX6000 series1-2 Vol. 4ABOUT THIS MANUAL
•Intel® Xeon® Scalable Processor Family
•9th generation Intel® Core™ processorsVol. 4 1-3ABOUT THIS MANUAL
•13th generation Intel® Core™ processors 

The Intel Atom® processor Z8000 series is based on the Airmont microarchitecture.1-4 Vol. 4ABOUT THIS MANUAL
1.2 OVERVIEW OF THE MO DEL-SPECIFIC REGISTERS 
manuals and documentation of interest to programmers and hardware designers.Vol. 4 1-5ABOUT THIS MANUAL
Chapter 2 — Model-Specif ic Registers (MSRs). Lists the MSRs available in Intel processors, and describes their 
NOTE
Figure 1-1.  Bit and Byte OrderByte 3HighestData Structure 
28
24
20
1612
8
40Address
Byte Offset1-6 Vol. 4ABOUT THIS MANUAL
where:
E, and F.
arise.
The processor uses byte addressing. This means memory  is organized and accessed as a sequence of bytes.

E, and F.
arise.
Segment-register:Byte-addressFor example, the following segment address identifies the byte at address FF79H in th e segment pointed by the DS 
register:
DS:FF79H
CS:EIPVol. 4 1-7ABOUT THIS MANUAL
#GP(0)Figure 1-2.  Syntax for CPUID, CR, and MSR Data PresentationInput value for EAX register
Value (or range) of output1-8 Vol. 4ABOUT THIS MANUAL
See also: 
•Intel® 64 and IA-32 Architectures Software Developer’s Manual (in one, four, or ten volumes):
https://software.intel.com/sites/default/files/article/147714/51534-developing-multithreaded-applica-
tions.pdf
•Performance Monitoring Unit Sharing Guide:http://software.intel.com/file/30388
http://www.intel.com/technology/platform-technology/hyper-threading/index.htmVol. 4 2-1CHAPTER 2
This chapter lists MSRs across Intel processor families. All MSRs listed can be read with the RDMSR and written with 
the WRMSR instructions. The scope of an MSR defines the set of processors that access the same MSR with RDMSR 
and WRMSR. Thread-scope MSRs are unique to every logical processor. Core-scope MSRs are shared by the threads 
in the same core; similarly for module-scope, die-scope, and package-scope.
When a processor package contains a single die, die- scope and package-scope are synonymous. When a package 
contains multiple die, they are distinct. 
NOTE
For information on hierarchical level types supporte d, refer to the CPUID Leaf 1FH definition for the 
actual level type numbers: “V2 Extended Topology Enumeration Leaf” in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volu me 2A. Also see Section 9.9.1, “Hierarchical 
Mapping of Shared Resources,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Register addresses are given in both hexadecimal and decimal. The register name is the mnemonic register name 
and the bit description describes individual bits in registers.
Model specific registers and its bit-fields may be supported for a finite range of processor families/models. To distin-
guish between different processor family and/or models, so ftware must use CPUID.01H leaf function to query the 
combination of DisplayFamily and DisplayModel to dete rmine model-specific availability of MSRs (see CPUID 
instruction in Chapter 3, “Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 2A). Table 2-1 lists the signatur e values of DisplayFamily and DisplayModel for various 
processor families or processor number series.
Table 2-1.  CPUID Signature Values  of DisplayFamily_DisplayModel 
DisplayFamily_DisplayModel Processo r Families/Processor Number Series
06_85H Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series based on Knights Mill microarchitecture
06_57H Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series based on Knights Landing microarchitecture
06_AAH Intel® Core™ Ultra 7 processors  supporting Meteor Lake pe rformance hybrid architecture
06_CFH 5th generation Intel® Xeon® Scalable Processor Fa mily based on Emerald Rapids microarchitecture
06_8FH 4th generation Intel® Xeon® Scalable Processor Fa mily based on Sapphire Rapids microarchitecture
06_BAH, 06_B7H, 06_BFH 13th generation Intel® Core™ processors supporti ng Raptor Lake performance hybrid architecture
06_97H, 06_9AH 12th generation Intel® Core™ processors suppor ting Alder Lake performance hybrid architecture
06_8CH, 06_8DH 11th generation Intel® Core™ processors  based on Tiger Lake microarchitecture
06_A7H 11th generation Intel® Core™ processors based on Rocket Lake  microarchitecture
06_7DH, 06_7EH 10th generation Intel® Core™ processors  based on Ice Lake  microarchitecture
06_A5H, 06_A6H 10th generation Intel® Core™ processors based on Comet Lake microarchitecture
06_66H Intel® Core™ processors based on Cannon Lake microarchitecture
06_8EH, 06_9EH 7th generation Intel® Core™ processors based on Kaby Lake microarchitecture, 8th and 9th generation 
Intel® Core™ processors based on Coffee Lake microarchitecture, Intel® Xeon® E processors based on Coffee Lake microarchitecture
06_6AH, 06_6CH 3rd generation Intel® Xeon® Scalable Processor Family based on Ice Lake microarchitecture
06_55H Intel® Xeon® Scalable Processor Fa mily based on Skylake microarchitecture, 2nd generation Intel® 
Xeon® Scalable Processor Family based on Cascade Lake product, and 3rd ge neration Intel® Xeon® 
Scalable Processor Family based on Cooper Lake product2-2 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
06_4EH, 06_5EH 6th generation Intel Core processors and Intel Xeon processor E3-1500m v5 product family and E3-
1200 v5 product family based on Skylake microarchitecture

06_56H Intel Xeon processor D-1500 product family based on Broadwell microarchitecture
06_4FH Intel Xeon processor E5 v4 Family based on Broadw ell microarchitecture, Intel Xeon processor E7 v4 
Family, Intel Core i7-69xx Processor Extreme Edition
06_47H 5th generation Intel Core processors, Intel Xeon processor E3-1200 v4 product family based on 
Broadwell micr oarchitecture
06_3DH Intel Core M-5xxx Processor, 5th generation Intel Core processors based on Broadwell 
06_3FH Intel Xeon processor E5-4600/2600/1600 v3 product families, Intel Xeon processor E7 v3 product 
families based on Hasw ell-E microarchitecture, Intel Core i7-59xx Processor Extreme Edition
06_3CH, 06_45H, 06_46H 4th Generation Intel Core processor and Intel Xeon processor E3-1200 v3 product family based on 
Haswell microarchitecture
06_3EH Intel Xeon processor E7-8800/4800/2800 v2 product families based on Ivy Bridge-E 
06_3EH Intel Xeon processor E5-2600/1600 v2 product families and Intel Xeon processor E5-2400 v2 
product family based on Ivy Bridge-E microarchitecture, Intel Core i7-49xx Processor Extreme Edition
06_3AH 3rd Generation Intel Core Processor and Intel Xeon processor E3-1200 v2 product family based on Ivy 
Bridge microa rchitecture
06_2DH Intel Xeon processor E5 Family based on Sandy Bridge microarchitecture, Intel Core i7-39xx 
Processor Extreme Edition
06_2FH Intel Xeon Processor E7 Family
06_2AH Intel Xeon processor E3-1200 product family; 2nd Generation Intel Core i7, i5, i3 Processors 2xxx 
Series
06_2EH Intel Xeon processor 7500, 6500 series
06_25H, 06_2CH Intel Xeon processors 3600, 5600 series, Intel Core i7, i5, and i3 Processors
06_1EH, 06_1FH Intel Core i7 and i5 Processors
06_1AH Intel Core i7 Processor, Intel Xeon processor 3400, 3500, 5500 series
06_1DH Intel Xeon processor MP 7400 series
06_17H Intel Xeon processor 3100, 3300, 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000 
series
06_0FH Intel Xeon processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad processor 6000 series, 
Intel Core 2 Extreme 6000 series, Intel Core 2 Duo 4000, 5000, 6000, 7000 series processors, Intel 
Pentium dual-core processors
06_0EH Intel Core Duo, Intel Core Solo processors
06_86H, 06_96H, 06_9CH Intel Atom® processors, Intel® Cele ron® processors, Intel® Pentium® processors, and Intel® Pentium® 
Silver processors based on Tremont Microarchitecture
06_7AH Intel Atom processors based on Goldmont Plus microarchitecture
06_5FH Intel Atom processors based on Goldmont microarchitecture (Denverton)
06_5CH Intel Atom processors based on Goldmont microarchitecture
06_4CH Intel Atom processor X7-Z8000 and X5-Z8000 series based on Airmont microarchitecture
06_5DH Intel Atom processor X3-C3000 based on Silvermont microarchitecture
06_5AH Intel Atom processor Z3500 series
06_4AH Intel Atom processor Z3400 seriesTable 2-1.  CPUID Signature Values of  DisplayFamily_DisplayModel  (Contd.)
DisplayFamily_DisplayModel Processor Families/Processor Number SeriesVol. 4 2-3MODEL-SPECIFIC REGISTERS (MSRS)
2.1 ARCHITECTURAL MSRS
Many MSRs have carried over from one generation of IA- 32 processors to the next and to Intel 64 processors. A 
subset of MSRs and associated bit fields, which do not ch ange on future processor gene rations, are now considered 
architectural MSRs. For historical reasons (beginning with the Pentium 4 processor), these “architectural MSRs” were given the prefix “IA32_”. Table 2-2 lists the architec tural MSRs, their addresses, their current names, their 
names in previous IA-32 processors, and bit fields that are considered architectural. MSR addresses outside Table 
2-2 and certain bit fields in an MSR address that may overlap with architectural MSR addresses are model-specific. Code that accesses a model-specific MSR and that is execut ed on a processor that does not support that MSR will 
generate an exception.
Architectural MSR or individual bit fields in an architec tural MSR may be introduced or transitioned at the granu-
larity of certain processor family/model or the presence of certain CPUID feature flags. The right-most column of 
Table 2-2 provides information on the introduction of each  architectural MSR or its individual fields. This informa-
tion is expressed either as signature values of “DF_DM” (see Table 2-1) or via CPUID flags.
Certain bit field position may be related to the maximum physical address width, the value of which is expressed 
as “MAXPHYADDR” in Table 2-2. “MAXPHYADDR” is reported by CPUID.8000_0008H leaf.
MSR address range between 40000000H - 4000FFFFH is marked  as a specially reserved range. All existing and 
future processors will not implement any features using any MSR in this range.06_37H Intel Atom processor E3000 series, Z3600 series, Z3700 series
06_4DH Intel Atom processor C2000 series
06_36H Intel Atom processor S1000 Series
06_1CH, 06_26H, 06_27H, 
06_35H, 06_36HIntel Atom processor family, Intel Atom processor D2000, N2000, E2000, Z2000, C1000 series
0F_06H Intel Xeon processor 7100, 5000 Series, Intel Xeon Processor MP, Intel Pentium 4, Pentium D 
0F_03H, 0F_04H Intel Xeon processor, Intel Xeon processo r MP, Intel Pentium 4, Pentium D processors
0F_02H Intel Xeon Processor, In tel Xeon processor MP, In tel Pentium 4 processors
0F_0H, 0F_01H Intel Xeon Processor, In tel Xeon processor MP, In tel Pentium 4 processors
06_7H, 06_08H, 06_0AH, 
06_0BHIntel Pentium 
III Xeon processor, Intel Pentium III processor
06_03H, 06_05H Intel Pentium II Xeon processor, Intel Pentium II processor 
06_01H Intel Pentium Pro processor 
05_01H, 05_02H, 05_04H Intel Pentium processor,  Intel Pentium processo r with MMX Technology
The Intel® Quark™ SoC X1000 processor ca n be identified by the signature of DisplayFamily_Displa yModel = 05_09H and 
SteppingID = 0
Table 2-2.  IA-32 Architectural MSRs
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Register Address: 0H, 0  IA32_P5_MC_ADDR (P5_MC_ADDR)
See Section 2.23, “MSRs in Pentium Processors.” Pentium Processor (05_01H)
Register Address: 1H, 1 IA32_P5_MC_TYPE (P5_MC_TYPE)
See Section 2.23, “MSRs in Pentium Processors.” DF_DM = 05_01HTable 2-1.  CPUID Signature Values of  DisplayFamily_Disp layModel  (Contd.)
DisplayFamily_DisplayMod el Processor Families/Pro cessor Number Series2-4 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination.” 0F_03H
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER (TSC)
See Section 18.17, “Time-Stamp Counter.” 05_01H
Register Address: 17H, 23 IA32_PLATFORM_ID (MSR_PLATFORM_ID)
Platform ID (R/O) 
The operating system can use this MSR to determine “slot” information for the processor and the 
proper microcode update to load.06_01H
49:0 Reserved.
52:50 Platform ID (R/O) 
Contains information concerning the intended platform for the 
52 51 50
0 0 0 Processor Flag 0
0 0 1 Processor Flag 10 1 0 Processor Flag 2
0 1 1 Processor Flag 3
1 0 0 Processor Flag 4 1 0 1 Processor Flag 5
1 1 0 Processor Flag 6
1 1 1 Processor Flag 7
63:53 Reserved.
Register Address: 1BH, 27 IA32_APIC_BASE (APIC_BASE)
This register holds the APIC base  address, permitting the relocation of the APIC memory map. See 
Section 11.4.4, “Local APIC Status and Location,”  and Section 11.4.5, “Relocating the Local APIC 
Registers.”06_01H
7:0 Reserved.
8B S P  F l a g  ( R / W )9R e s e r v e d .
10 Enable x2APIC mode. 06_1AH
11 APIC Global Enable (R/W)(MAXPHYADDR -1):12 APIC Base (R/W)
63: MAXPHYADDR Reserved.
Register Addr ess: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W) If any one enumeration condition 
for defined bit field holds.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-5MODEL-SPECIFIC REGISTERS (MSRS)
0 Lock bit (R/WO): (1 = locked). 
When set, locks this MSR from being wr itten; writes to this bit will result 
in GP(0).
Note: Once the Lock bit is  set, the contents of th is register cannot be 
modified. Therefore the lock bit must be set after configuring support for Intel Virtualization Technology and prior to transferring control to an 
option ROM or the OS. Hence, once the Lock bit is set, the entire 
IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD is not deasserted.If any one enumeration condition 
for defined bit field position greater than bit 0 holds.
1 Enable VMX inside SMX operation (R/WL) This bit enables a system 
executive to use VMX in conjunction with SMX to suppor t Intel® Trusted 
Execution Technology.
BIOS must set this bi t only when the CPUID function 1 returns VMX 
feature flag and SMX feature flag set (ECX bits 5 and 6 respectively).If CPUID.01H:ECX[5] = 1 && 
CPUID.01H:ECX[6] = 1

in GP(0).
2 Enable VMX outside SMX operation (R/WL) This bit enables VMX for a 
system executive that does not require SMX.
BIOS must set this bit only when the CPUID function 1 returns the VMX 
feature flag set (ECX bit 5).If CPUID.01H:ECX[5] = 1 
7:3 Reserved.
14:8 SENTER Local Function Enables (R/W L) When set, each bit in the field 
represents an enable control for a corresponding SENTER function. This 
field is supported only if CPUID.1:ECX.[bit 6] is set.If CPUID.01H:ECX[6] = 1
15 SENTER Global Enable (R/WL)
This bit must be set to enable SE NTER leaf functions. This bit is 
supported only if CPUID.1:ECX.[bit 6] is set.If CPUID.01H:ECX[6] = 1
16 Reserved.
17 SGX Launch Control Enable (R/WL)
This bit must be set to enable runt ime re-configuration of SGX Launch 
Control via the IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): 
ECX[30] = 1
18 SGX Global Enable (R/WL)
This bit must be set to en able SGX leaf functions. If CPUID.(EAX=07H, ECX=0H): 
EBX[2] = 1
19 Reserved.
20 LMCE On (R/WL)
When set, system software can program the MSRs associated with LMCE 
to configure delivery of some machine check exceptions to a single 
logical processor. If IA32_MCG_CAP[27] = 1
63:21 Reserved.
Register Address: 3BH, 59 IA32_TSC_ADJUST
Per Logical Processor TSC Adjust (R/Write  to clear) If CPUID.(EAX=07H, ECX=0H): 
EBX[1] = 1
63:0 THREAD_ADJUST 
Local offset value of the IA32_TSC fo r a logical processor. Reset value is 
zero. A write to IA32_TSC will modify the local offset in 
IA32_TSC_ADJUST an d the content of IA32_TSC, but does not affect the 
internal invariant TSC hardware. Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-6 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 48H, 72 IA32_SPEC_CTRL
Speculation Control (R/W)
The MSR bits are defined as logical processor scop e. On some core implem entations, the bits may 
impact sibling logical processors on the same core.
This MSR has a value of 0 after reset and is unaffected by INIT# or SIPI#.If any one of the enumeration 
conditions for defined bit field 
positions holds.
0 Indirect Branch Restricted Speculation (IBRS). Restricts speculation of 
indirect branch.If CPUID.(EAX=07H, 
ECX=0):EDX[26]=1
1 Single Thread Indirect Branch Predictors (STIBP). Prevents indirect 
branch predictions on a ll logical processors on  the core from being 
controlled by any sibling logica l processor in the same core.If CPUID.(EAX=07H, 
ECX=0):EDX[27]=1
2 Speculative Store Bypass Disable (SSBD) delays speculative execution of 
a load until the addresses fo r all older stores are known.If CPUID.(EAX=07H, 
ECX=0):EDX[31]=1
3 IPRED_DIS_U
If 1, enables IPRED_DIS control for CPL3.If CPUID.(EAX=07H, 
ECX=2):EDX[1]=1
4 IPRED_DIS_S
If 1, enables IPRED_DIS control for CPL0/1/2.If CPUID.(EAX=07H, 
5 RRSBA_DIS_U
If 1, disables RRSBA behavior for CPL3. If CPUID.(EAX=07H, 
ECX=2):EDX[2]=1
6 RRSBA_DIS_S
If 1, disables RRSBA behavior for CPL0/1/2.If CPUID.(EAX=07H, 
7P S F D
If 1, disables Fast Stor e Forwarding Predictor. Note that setting bit 2 
(SSBD) also disables this.If CPUID.(EAX=07H, 
ECX=2):EDX[0]=1
8 DDPD_U
If 1, disables the Data Dependent Prefetcher that examines data values 
in memory while CPL = 3. Note that setting bit 2 (SSBD)  also disables 
this.If CPUID.(EAX=07H, 
ECX=2):EDX[3]=1
9R e s e r v e d .
10 BHI_DIS_S
When ‘1, enables BHI_DIS_S behavior.If CPUID.(EAX=07H, 
ECX=2):EDX[4]=1
63:11 Reserved.
Register Address: 49H, 73 IA32_PRED_CMD
Prediction Command (WO)
Gives software a way to i ssue commands that affect the state of predictors.If any one of the enumeration 
conditions for defined bit field positions holds.
0 Indirect Branch Prediction Barrier (IBPB) If CPUID.(EAX=07H, 
63:1 Reserved.
Register Address: 4EH, 78 IA32_PPIN_CTL
Protected Processor Inventory Number En able Control (R/W) If CPUID.(EAX=07H, 
ECX=01H):EBX[0]=11Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-7MODEL-SPECIFIC REGISTERS (MSRS)
0L o c k O u t  ( R / W O )
If 0, indicates that further writ es to IA32_PPIN_CTL is allowed.
If 1, indicates that further writes  to IA32_PPIN_CTL is disallowed. 
Writing 1 to this bit is only permi tted if the Enable_ PPIN bit is clear.
The Privileged System Software Inventory Agent should read 
IA32_PPIN_CTL[bit 1] to determ ine if IA32_PPIN is accessible.
The Privileged System Software Inventory Agent is not expected to 
write to this MSR.
1E n a b l e _ P P I N  ( R / W )
If 1, indicates that IA32_PPIN is accessible using RDMSR.If 0, indicates that IA 32_PPIN is inaccessible using RDMSR. Any attempt 
to read IA32_PPIN will cause #GP.
63:2 Reserved.
Register Address: 4FH, 79 IA32_PPIN
Protected Processor Inventory Number (R/O) If CPUID.(EAX=07H, 
ECX=01H):EBX[0]=11
63:0 Protected Processor Inventory Number (R/O)
A unique value within a given CPUID family/model/stepping signature 
that a privileged inventory initialization agent can access to identify each 
physical processor, when access to IA32_PPIN is enabled. Access to 
IA32_PPIN is permitted only if IA32_PPIN_CTL[bits 1:0] = ‘10b’.
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG (BIOS_UPDT_TRIG)
BIOS Update Trigger (W)
Executing a WRMSR instruction to this MSR causes  a microcode update to  be loaded into the 
processor. See Section 10.11.6, “Microcode Update Loader.”
A processor may prevent writing to  this MSR when loading guest st ates on VM entries or saving 
guest states on VM exits.06_01H
Register Address: 7AH, 122 IA32_FEATURE_ACTIVATION
Feature Activation (R/W)
Implements Feature Activation command. WRMSR to this address activates all 'activatable' 
features on this thread.
0 Reserved.
1K L
Keylocker feature activation.
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID (BIOS_SIGN/BBL_CR_D3)
BIOS Update Signature (R/W)
Returns the microcod e update signature following the execution of CPUID.01H.
31:0 Reserved.
Register Address: 8CH, 140 IA32_SGXLEPUBKEYHASH0Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-8 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
IA32_SGXLEPUBKEYHASH[63:0] (R/W)
Bits 63:0 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, 
the default value is the digest of Intel’s signing key.Read permitted If 
CPUID.(EAX=12H,ECX=0H): EAX[0]=1 && CPUID.(EAX=07H, 
ECX=0H):ECX[30]=1.
Write permitted if 
CPUID.(EAX=12H,ECX=0H): 
EAX[0]=1 && 
IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] 
= 1.
Register Address: 8DH, 141 IA32_SGXLEPUBKEYHASH1
IA32_SGXLEPUBKEYHASH[127:64] (R/W)
Bits 127:64 of the SHA256 digest of the SIGSTR UCT.MODULUS for SGX Launch Enclave. On reset, 
the default value is the digest of Intel’s signing key.Same comment in MSR listing for 
IA32_SGXLEPUBKEYHASH0 (MSR 
address 8CH, 140) applies here.
Register Address: 8EH, 142 IA32_SGXLEPUBKEYHASH2
IA32_SGXLEPUBKEYHASH[191:128] (R/W)
Bits 191:128 of the SHA256 digest of the SI GSTRUCT.MODULUS for SGX Launch Enclave. On 
reset, the default value is the digest of Intel’s signing key.Same comment in MSR listing for 
Register Address: 8FH, 143 IA32_SGXLEPUBKEYHASH3
IA32_SGXLEPUBKEYHASH[255:192] (R/W)
Bits 255:192 of the SHA256 digest of the SI GSTRUCT.MODULUS for SGX Launch Enclave. On 
Register Address: 9BH, 155 IA32_SMM_MONITOR_CTL
SMM Monitor Configuration (R/W) If CPUID.01H: ECX[5]=1 || 
CPUID.01H: ECX[6] = 1
0V a l i d  ( R / W )
1R e s e r v e d .2 Controls SMI unblocking by VMXOFF (see Section 32.14.4). If IA32_VMX_MISC[28]
11:3 Reserved.
31:12 MSEG Base (R/W)63:32 Reserved.
Register Address: 9EH, 158 IA32_SMBASE
Base address of the logical processor’s SMRAM  image (R/O, SMM only). If IA32_VMX_MISC[15]
Register Address: BCH, 188 IA32_MISC_PACKAGE_CTLS
Power Filtering Control (R/W)
This MSR has a value of 0 after reset and is unaffected by INIT# or SIPI#.If IA32_ARCH_CAPABILITIES
[10] = 1
0 ENERGY_FILTERING_ENABLE (R/W)
If set, RAPL MSRs report filtered processor power consumption data.
This bit can be changed from 0 to 1, but cannot be changed from 1 to 0. 
After setting, all attempts to clear it  are ignored until the next processor 
reset.If IA32_ARCH_CAPABILITIES
[11] = 1
Register Address: BDH, 189 IA32_XAPIC_DISABLE_STATUSTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-9MODEL-SPECIFIC REGISTERS (MSRS)

[10] = 1
[11] = 1
xAPIC Disable Status (R/O) If CPUID.(EAX-07H, 
ECX=0):EDX[29]=1 and IA32_ARCH_CAPABILITIES [21] = 
1
0 LEGACY_XAPIC_DISABLED
When set, indicates that the local APIC is in x2APIC mode 
(IA32_APIC_BASE.EXTD = 1) an d that attempts to clear 
IA32_APIC_BASE.EXTD will fail (e.g., WRMSR will #GP). 
Register Address: C1H, 193 IA32_PMC0 (PERFCTR0)
General Performance Counter 0 (R/W) If CPUID.0AH: EAX[15:8] > 0
Register Address: C2H, 194 IA32_PMC1 (PERFCTR1)
General Performance Counter 1 (R/W) If CPUID.0AH: EAX[15:8] > 1
Register Address: C3H, 195 IA32_PMC2 
General Performance Counter 2 (R/W) If CPUID.0AH: EAX[15:8] > 2
Register Address: C4H, 196 IA32_PMC3 
General Performance Counter 3 (R/W) If CPUID.0AH: EAX[15:8] > 3
Register Address: C5H, 197 IA32_PMC4
General Performance Counter 4 (R/W) If CPUID.0AH: EAX[15:8] > 4
Register Address: C6H, 198 IA32_PMC5 
General Performance Counter 5 (R/W) If CPUID.0AH: EAX[15:8] > 5
Register Address: C7H, 199 IA32_PMC6
General Performance Counter 6 (R/W) If CPUID.0AH: EAX[15:8] > 6
Register Address: C8H, 200 IA32_PMC7
General Performance Counter 7 (R/W) If CPUID.0AH: EAX[15:8] > 7
Register Address: CFH, 207 IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register If CPUID.(EAX=07H, 
ECX=0):EDX[30] = 1 
63:0 Reserved. No architecturally defined bits.
Register Address: E1H, 225 IA32_UMWAIT_CONTROL
UMWAIT Control (R/W)
0 C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert 
to C0.1.
1 Reserved.
31:2 Determines the maximum time in TSC-quanta  that the processor can 
reside in either C0.1 or C0.2. A zero value indicates no maximum time. 
The maximum time value is a 32-bit value where the upper 30 bits come 
from this field and the lower two bits are zero.
Register Address: E7H, 231 IA32_MPERF
TSC Frequency Clock Counter (R/Write to clear) If CPUID.06H: ECX[0] = 1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-10 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
63:0 C0_MCNT: C0 TSC Frequency Clock Count
Increments at fixed interval (relative to TSC freq.) when the logical 
processor is in C0. 
Cleared upon overflow / wr ap-around of IA32_APERF. 
Register Address: E8H, 232 IA32_APERF
Actual Performance Clock Counter (R/Write to clear) If CPUID.06H: ECX[0] = 163:0 C0_ACNT: C0 Actual Frequency Clock Count
Accumulates core clock counts at th e coordinated clock frequency, when 
the logical processor is in C0. 
Cleared upon overflow / wrap-around of IA32_MPERF.
Register Address: FEH, 254 IA32_MTRRCAP (MTRRcap)
MTRR Capability (R/O)
See Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”06_01H
7:0 VCNT: The number of variable memory type ranges in the processor.
8 Fixed range MTRRs are supported when set.9R e s e r v e d .
10 WC Supported when set.
11 SMRR Supported when set.12 PRMRR supported when set.
63:13 Reserved.
Register Address: 10AH, 266 IA32_ARCH_CAPABILITIES
Enumeration of Architectural Features (R/O) If CPUID.(EAX=07H, 
ECX=0):EDX[29]=1
0 RDCL_NO: The processor is not susc eptible to Rogue Data Cache Load 
(RDCL).
1 IBRS_ALL: The processor supports enhanced IBRS.
2 RSBA: The processor supports RSB Alternate. Alternative branch 
predictors may be used by RET instru ctions when the RSB is empty. SW 
using retpoline may be affected by this behavior.
3 SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor need not 
flush the L1D on VM entry.
4 SSB_NO: Processor is not suscep tible to Speculative Store Bypass.
5 MDS_NO: Processor is not suscepti ble to Microarchitectural Data 
Sampling (MDS).
6 IF_PSCHANGE_MC_NO: The processor is not susceptible to a machine 
check error due to modifying the size of a code page without TLB 
invalidation.
7 TSX_CTRL: If 1, indicates pr esence of IA32_TSX_CTRL MSR.
8 TAA_NO: If 1, processor is not affected by TAA.
9 MCU_CONTROL: If 1, the processor supports the IA32_MCU_CONTROL 
MSR.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-11MODEL-SPECIFIC REGISTERS (MSRS)
10 MISC_PACKAGE_CTLS: The processor supports 
IA32_MISC_PACKAGE_CTLS MSR.
11 ENERGY_FILTERING_CTL: The proce ssor supports setting and reading 
the IA32_MISC_PACKAGE_CTLS[0] (ENERGY_FILTERING_ENABLE) bit.
12 DOITM: If 1, the processor supports Data Operand Independent Timing 
Mode. 
13 SBDR_SSDP_NO: The processor is not affected by either the Shared 
Buffers Data Read (SBDR) vulnerability or the Sideband Stale Data Propagator (SSDP).
14 FBSDP_NO: The processor is not affected by the Fill Buffer Stale Data 
Propagator (FBSDP).
15 PSDP_NO: The processor is not affected by vulnerabilities involving the 
Primary Stale Data Propagator (PSDP).
17 FB_CLEAR: If 1, the processor supports overwrite of fill buffer values as 
part of MD_CLEAR operations  with the VERW instruction.
18 FB_CLEAR_CTRL: If 1, the proces sor supports the IA32_MCU_OPT_CTRL 
MSR and allows software to set bit 3 of that MSR (FB_CLEAR_DIS).
19 RRSBA: A value of 1 indicates the processor may have the RRSBA 
alternate prediction behavior, if not disabled by RRSBA_DIS_U or 
RRSBA_DIS_S.
20 BHI_NO: A value of 1 indicates BHI_NO branch prediction behavior, 
regardless of the value of IA32_ SPEC_CTRL[BHI_DIS_S] MSR bit.
21 XAPIC_DISABLE_STATUS: Enumerates that the 
IA32_XAPIC_DISABLE_STATUS MSR ex ists, and that bit 0 specifies 
whether the legacy xAPIC is disabled and APIC state is locked to x2APIC.
22 Reserved.
23 OVERCLOCKING_STATUS: If set, the IA32_OVERCLOCK ING_STATUS MSR 
exists.
24 PBRSB_NO: If 1, the processor is not affected by issues related to Post-
Barrier Return Stack Buffer Predictions.
63:25 Reserved.
Register Address: 10BH, 267 IA32_FLUSH_CMD
Flush Command (WO)
Gives software a way to invalidate structures with finer granularity than other architectural 
methods.If any one of the enumeration 
0 L1D_FLUSH: Writeback and invalidate th e L1 data cache. If CPUID.(EAX=07H, 
ECX=0):EDX[28]=1
Register Address: 10FH, 271 IA32_TSX_FORCE_ABORT
TSX Force Abort If CPUID.(EAX=07H, 
ECX=0):EDX[13]=1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-12 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
0 RTM_FORCE_ABORT
If 1, all RTM transactions  abort with EAX code 0.R/W, Default: 0
If CPUID.(EAX=07H,ECX=0): 
EDX[11]=1, bit 0 is always 1 and 
writes to change it are ignored.
If SDV_ENABLE_RTM is 1, bit 0 is 
always 0 and writes to change it 
1 TSX_CPUID_CLEAR
When set, CPUID.(EAX=0 7H,ECX=0):EBX[11]=0 and 
CPUID.(EAX=07H,ECX=0):EBX[4]=0.R/W, Default: 0
Can be set only if 
CPUID.(EAX=07H,ECX=0): EDX[11]=1 or if 
SDV_ENABLE_RTM is 1.
2S D V _ E N A B L E _ R T M
When set, CPUID.(EAX =07H,ECX=0):EDX[11]=0 and the processor may 
not force abort RTM. This unsupporte d mode should only be used for 
software development and not for production usage. R/W, Default: 0
If 0, can be set only if 
CPUID.(EAX=07H,ECX=0): 
EDX[11]=1.
63:3 Reserved.
Register Address: 122H, 290 IA32_TSX_CTRL
IA32_TSX_CTRL Thread scope. Not architecturally 
serializing.
Available when 
CPUID.ARCH_CAP(EAX=7H, ECX = 
0):EDX[29] = 1 and IA32_ARCH_CAPABILITIES.bit 7 = 
1.
0R T M _ D I S A B L E
When set to 1,  XBEGIN will always ab ort with EAX code 0.
When set to 1, CPUID.07H.EBX.RTM [b it 11] and CPUID.07H.EBX.HLE [bit 
4] report 0.
When set to 0 and the SKU supports TSX, thes e bits will return 1.
Register Address: 123H, 291 IA32_MCU_OPT_CTRL
Microcode Update Option Control (R/W) If CPUID.(EAX=07H, 
ECX=0):EDX[9]=1 or 
IA32_ARCH_CAPABILITIES [18] = 1 or IA32_ARCH_CAPABILITIES. 
FB_CLEAR_CTRL=1
0 RNGDS_MITG_DIS (R/W)
If 0 (default), SRBDS mitigation is enabled for RDRAND and RDSEED.
If 1, SRBDS mitigation is disabled for RDRAND and RDSEED executed 
outside of Intel SGX enclaves.If CPUID.(EAX=07H, 
ECX=0):EDX[9]=1
1 RTM_ALLOW
If 0, XBEGIN will always abort with EAX code 0. 
If 1, XBEGIN behavior depends on the value of 
IA32_TSX_CTRL[ RTM_DISABLE].Read/Write
Setting RTM_LOCKED prevents 
writes to this bit.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-13MODEL-SPECIFIC REGISTERS (MSRS)
2R T M _ L O C K E D
When 1, RTM_ALLOW is locked at zero, writes to RTM_ALLOW will be 
ignored.Read-Only status bit.
3F B _ C L E A R _ D I S
If 1, prevents the VERW instruct ion from performing an FB_CLEAR 
action.If IA32_ARCH_CAPABILITIES. 
4 GDS_MITG_DIS
If 0, the Gather Data Sa mpling mitigation is en abled (patch load time 
default).
If 1 on all threads for a given core, th e Gather Data Sampli ng mitigation is 
disabled.
5G D S _ M I T G _ L O C K
If 0, not locked, and GDS_MITG_DIS is under OS control.If 1, locked and GDS_MITG_DIS is forced to 0 (wri tes are ignored).
63:6 Reserved.

default).
disabled.
Register Address: 174H, 372 IA32_SYSENTER_CS
SYSENTER_CS_MSR (R/W) 06_01H
15:0 CS Selector.31:16 Not used. Can be read and written.
63:32 Not used. Writes ignored; reads
return zero.
Register Address: 175H, 373 IA32_SYSENTER_ESP
SYSENTER_ESP_MSR (R/W) 06_01H
Register Address: 176H, 374 IA32_SYSENTER_EIP
SYSENTER_EIP_MSR (R/W) 06_01H
Register Address: 179H, 377 IA32_MCG_CAP (MCG_CAP) 
Global Machine Check Capability (R/O) 06_01H
7:0 Count: Number of reporting banks.
8 MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
9 MCG_EXT_P: Extended machine check state registers are present if this 
bit is set.
10 MCP_CMCI_P: Support for corrected MC error event is present. 06_01H
11 MCG_TES_P: Threshold-based error stat us register are present if this bit 
is set.
15:12 Reserved.
23:16 MCG_EXT_CNT: Number of extended machine check state registers 
present.
24 MCG_SER_P: The processor supports software error recovery if this bit is 
set.
25 Reserved.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-14 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
26 MCG_ELOG_P: Indicates that the processor allows platform firmware to 
be invoked when an error is detected  so that it may provide additional 
platform specific information in an  ACPI format “Generic Error Data 
Entry” that augments th e data included in machine check bank registers.06_3EH
27 MCG_LMCE_P: Indicates that the proc essor supports ex tended state in 
IA32_MCG_STATUS and associated MS R necessary to configure Local 
Machine Check Exception (LMCE).06_3EH
63:28 Reserved.
Register Address: 17AH, 378 IA32_MCG_STATUS (MCG_STATUS)
Global Machine Check Status (R/W) 06_01H0 RIPV. Restart IP valid. 06_01H1 EIPV. Error IP valid. 06_01H
2 MCIP. Machine chec k in progress. 06_01H
3 LMCE_S. If IA32_MCG_CAP.LMCE_P[27] =163:4 Reserved.
Register Address: 17BH, 379 IA32_MCG_CTL (MCG_CTL)
Global Machine Check Control (R /W) If IA32_MCG_CAP.CTL_P[8] =1
Register Address: 180H −185H, 384 −389 N/A
Reserved 06_0EH2
Register Address: 186H, 390 IA32_PERFEVTSEL0 (PERFEVTSEL0)
Performance Event Select Register 0 (R/W) If CPUID.0AH: EAX[15:8] > 0
7:0 Event Select: Selects a performance event logic unit.
15:8 UMask: Qualifies the microarchitect ural condition to detect on the 
selected event logic.
16 USR: Counts while in privilege level is not ring 0.17 OS: Counts while in privilege level is ring 0.
18 Edge: Enables edge detection if set.
19 PC: Enables pin control.20 INT: Enables interrup t on counter overflow.
21 AnyThread: When set to 1, it enables counting the associated event 
conditions occurring ac ross all logical processo rs sharing a processor 
core. When set to 0, the counter only increments the associated event conditions occurrin g in the logical processor which programmed the MSR.
22 EN: Enables the corresponding performance counter to commence 
counting when th is bit is set.
23 INV: Invert the CMASK.31:24 CMASK: When CMASK is not zero, the corresponding performance 
counter increments each cycle if the event count is greater than or equal 
to the CMASK.
63:32 Reserved.
Register Address: 187H, 391 IA32_PERFEVTSEL1 (PERFEVTSEL1)Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-15MODEL-SPECIFIC REGISTERS (MSRS)
Performance Event Select Register 1 (R/W) If CPUID.0AH: EAX[15:8] > 1
Register Address: 188H, 392 IA32_PERFEVTSEL2 
Performance Event Select Register 2 (R/W) If CPUID.0AH: EAX[15:8] > 2
Register Address: 189H, 393 IA32_PERFEVTSEL3
Performance Event Select Register 3 (R/W) If CPUID.0AH: EAX[15:8] > 3
Register Address: 18AH, 394 IA32_PERFEVTSEL4 
Performance Event Select Register 4 (R/W) If CPUID.0AH: EAX[15:8] > 4
Register Address: 18BH, 395 IA32_PERFEVTSEL5 
Performance Event Select Register 5 (R/W) If CPUID.0AH: EAX[15:8] > 5
Register Address: 18CH, 396 IA32_PERFEVTSEL6
Performance Event Select Register 6 (R/W) If CPUID.0AH: EAX[15:8] > 6
Register Address: 18DH, 397 IA32_PERFEVTSEL7
Performance Event Select Register 7 (R/W) If CPUID.0AH: EAX[15:8] > 7
Register Address: 18AH −194H, 394 −404 N/A
Reserved. 06_0EH3
Register Address: 195H, 405 IA32_OVERCLOCKING_STATUS
Overclocking Status (R/O)
IA32_ARCH_CAPABILITIES[ bit 23] enumerates support for this MSR.
0 Overclocking Utilized
Indicates if specific forms of overclocking have been enabled on this boot 
or reset cycle: 0 indica tes no, 1 indicates yes.
1 Undervolt Protection
Indicates if the “Dynamic OC Undervolt Protection” security feature is 
active: 0 indicates disabled, 1indicates enabled.
2 Overclocking Secure Status
Indicates that overclocking  capabilities have been unlocked by BIOS, with 
or without overclocking: 0 indicate s Not Secured, 1 indicates Secure.
63:4 Reserved.
Register Address: 196H −197H, 406 −407 N/A
Register Address: 198H, 408 IA32_PERF_STATUS
Current Performance Status (R/O)
See Section 15.1.1, “Software Interface For Initiating Performance State Transitions.”0F_03H
15:0 Current Performance State Value.
63:16 Reserved.
Register Address: 199H, 409 IA32_PERF_CTL
Performance Control MSR (R/W)
Software makes a request for a new Performance state (P-State) by writing this MSR. See 
Section 15.1.1, “Software Interface For Initiating Performance State Transitions.”0F_03HTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-16 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
15:0 Target performance State Value.
31:16 Reserved.
32 Intel® Dynamic Acceleration  Technology Engage (R/W)
When set to 1: Diseng ages Intel Dynamic Acce leration Technology.06_0FH (Mobile only)
63:33 Reserved.
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation Control (R/W)
See Section 15.8.3, “Software Controlled Clock Modulation.”If CPUID.01H:EDX[22] = 1
0 Extended On-Demand Clock Modulation Duty Cycle. If CPUID.06H:EAX[5] = 1
3:1 On-Demand Clock Modulation Duty Cycle: Specific encoded values for 
target duty cycle modulation.If CPUID.01H:EDX[22] = 1
4 On-Demand Clock Modulation Enable: Set 1 to enable modulation. If CPUID.01H:EDX[22] = 1
63:5 Reserved.
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
Enables and disables the generation of an interrupt on temperature transitions detected with the 
processor’s therma l sensors and thermal monitor. 
See Section 15.8.2, “Thermal Monitor.”If CPUID.01H:EDX[22] = 1
0 High-Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1
1 Low-Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1
2 PROCHOT# Interrupt Enable If CPUID.01H:EDX[22] = 1
3 FORCEPR# Interrupt Enable If CPUID.01H:EDX[22] = 14 Critical Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1
7:5 Reserved.
14:8 Threshold #1 Value I f CPUID.01H:EDX[22] = 1
15 Threshold #1 Interrupt Enable If CPUID.01H:EDX[22] = 1
22:16 Threshold #2 Value If CPUID.01H:EDX[22] = 1
23 Threshold #2 Interrupt Enable If CPUID.01H:EDX[22] = 124 Power Limit Notification Enable If CPUID.06H:EAX[4] = 1
25 Hardware Feedback Notification Enable If CPUID.06H:EAX[24] = 1
63:26 Reserved.
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Status Information (R/O)
Contains status information about the proce ssor’s thermal sensor and automatic thermal 
monitoring facilities. 
0 Thermal Status (R/O) If CPUID.01H:EDX[22] = 1
1 Thermal Status Log (R/W) If CPUID.01H:EDX[22] = 1
2 PROCHOT # or FORCEPR# event (R/O) If CPUID.01H:EDX[22] = 1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-17MODEL-SPECIFIC REGISTERS (MSRS)
3 PROCHOT # or FORCEPR# log (R/WC0) If CPUID.01H:EDX[22] = 1
4 Critical Temperature Status (R/O) If CPUID.01H:EDX[22] = 1
5 Critical Temperature Status log (R/WC0) If CPUID.01H:EDX[22] = 1
6 Thermal Threshold #1 Status (R/O) If CPUID.01H:ECX[8] = 1
7 Thermal Threshold #1 log (R/WC0) If CPUID.01H:ECX[8] = 1
8 Thermal Threshold #2 Status (R/O) If CPUID.01H:ECX[8] = 19 Thermal Threshold #2 log (R/WC0) If CPUID.01H:ECX[8] = 1
10 Power Limitation Status (R/O) If CPUID.06H:EAX[4] = 1
11 Power Limitation log (R/WC0) If CPUID.06H:EAX[4] = 112 Current Limit Status (R/O) If CPUID.06H:EAX[7] = 113 Current Limit log (R/WC0) If CPUID.06H:EAX[7] = 1
14 Cross Domain Limit Status (R/O) If CPUID.06H:EAX[7] = 1
15 Cross Domain Limit log (R/WC0) If CPUID.06H:EAX[7] = 122:16 Digital Readout (R/O) If CPUID.06H:EAX[0] = 1
26:23 Reserved.
30:27 Resolution in Degrees Celsius (R/O) If CPUID.06H:EAX[0] = 131 Reading Valid (R/O) If CPUID.06H:EAX[0] = 1
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)  
Allows a variety of processor functions to be enabled and disabled.
0F a s t - S t r i n g s  E n a b l e

When set, the fast-strings feature (for REP MOVS and REP STORS) is 
enabled (default). When clear, fast-strings are disabled.0F_0H
2:1 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W) 
1 = Setting this bit enab les the thermal control circuit (TCC) portion of 
the Intel Thermal Monitor feature.  This allows the processor to 
automatically reduce power consumption in response to TCC 
activation.
0 = Disabled.
Note: In some products clearing this  bit might be ignored in critical 
thermal conditions, and TM1, TM2, and adaptive ther mal throttling will 
still be activated.
The default value of this field varies with product. See respective tables 
where default value is listed. 0F_0H
6:4 Reserved.
7 Performance Monitoring Available (R) 
1 = Performance monitoring enabled.
0 = Performance monitoring disabled.0F_0H
10:8 Reserved.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-18 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
11 Branch Trace Storage Unavailable (R/O)
1 = Processor doesn’t support branch trace storage (BTS).
0 = BTS is supported.0F_0H
12 Processor Event Based Sampli ng (PEBS) Unavailable (R/O) 
1 = PEBS is not supported.
0 = PEBS is supported. 06_0FH
15:13 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
0= Enhanced Intel SpeedStep Technology disabled.
1 = Enhanced Intel SpeedS tep Technology enabled.If CPUID.01H: ECX[7] =1
17 Reserved.
18 ENABLE MONITOR FSM (R/W)
When this bit is set to 0, the MONITOR feature flag is not set 
(CPUID.01H:ECX[bit 3] = 0). This in dicates that MONI TOR/MWAIT are not 
Software attempts to execute MONITOR/MWAIT will cause #UD when 
this bit is 0.
When this bit is set to 1 (default),  MONITOR/MWAIT are supported 
(CPUID.01H:ECX[bit 3] = 1).
If the SSE3 feature flag ECX[0] is not set (CPUID.01H:E CX[bit 0] = 0), the 
OS must not attempt to al ter this bit. BIOS must leave it in the default 
state. Writing this bit when the SSE3 feature flag is set to 0 may 
generate a #GP exception.0F_03H
21:19 Reserved.
22 Limit CPUID Maxval (R/W)
When this bit is set to 1, CPUI D.00H returns a maximum value in 
EAX[7:0] of 2.
BIOS should contain a setup question that allows users to specify when 
the installed OS does not suppor t CPUID functions greater than 2.
Before setting this bit, BIOS must execute the CPUID.0H and examine 
the maximum value returned in EAX[7:0]. If the maximum value is 
greater than 2, this  bit is supported.
Otherwise, this bit is not supported.  Setting this bit when the maximum 
value is not greater than 2 may generate a #GP exception.
Setting this bit may cause unexpect ed behavior in software that 
depends on the availability of  CPUID leaves greater than 2.0F_03H
23 xTPR Message Disable (R/W)
When set to 1, xTPR me ssages are disabled. xTPR  messages are optional 
messages that allow the processor to inform the chipset of its priority.If CPUID.01H:ECX[14] = 1
63:24 Reserved.
Note: Some older processors defined one of these bits as a disable for 
the execute-disable feature of paging. If a processor supports this bit, 
this information is provided in the model-specific tables. See Table 2-3 for the definition  of this bit.
Register Address: 1B0H, 432 IA32_ENERGY_PERF_BIASTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-19MODEL-SPECIFIC REGISTERS (MSRS)
Performance Energy Bias Hint (R/W) If CPUID.6H:ECX[3] = 1
3:0 Power Policy Preference: 
0 indicates preference to highest performance.
15 indicates preference to maximize energy saving.
Register Address: 1B1H, 433 IA32_PACKAGE_THERM_STATUS
Package Thermal Status Information (R/O)
Contains status information about the package’s thermal sensor. 
See Section 15.9, “Package Level Thermal Management.”If CPUID.06H: EAX[6] = 1
0 Pkg Thermal Status (R/O)
1 Pkg Thermal Status Log (R/W)
2 Pkg PROCHOT # event. (R/O)3P k g  P R O C H O T  #  l o g .  ( R / W C 0 )
4 Pkg Critical Temperature Status. (R/O)
5 Pkg Critical Temperature Status Log. (R/WC0)6 Pkg Thermal Threshold #1 Status. (R/O)
7 Pkg Thermal Threshold #1 Log. (R/WC0)
8 Pkg Thermal Threshold #2 Status. (R/O)9 Pkg Thermal Threshold #1 Log. (R/WC0)
10 Pkg Power Limitation Status. (R/O)
11 Pkg Power Limitation Log. (R/WC0)15:12 Reserved.
22:16 Pkg Digital Readout. (R/O)
25:23 Reserved.26 Hardware Feedback Interface Structure Change Status. If CPUID.06H:EAX.[19] = 1
63:27 Reserved.
Register Address: 1B2H, 434 IA32_PACKAGE_THERM_INTERRUPT
Pkg Thermal Interrupt Control (R/W)
Enables and disables the generation of an interr upt on temperature transi tions detected with the 
package’s thermal sensor. 
0P k g  H i g h - T e m p e r a t u r e  Interrupt Enable.
1 Pkg Low-Temperature Interrupt Enable.2 Pkg PROCHOT# Interrupt Enable.
3 Reserved.
4 Pkg Overheat Interrupt Enable.7:5 Reserved.
14:8 Pkg Threshold #1 Value.
15 Pkg Threshold #1 Interrupt Enable.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-20 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
22:16 Pkg Threshold #2 Value.
23 Pkg Threshold #2 Interrupt Enable.
24 Pkg Power Limit Notification Enable.25 Hardware Feedback Interrupt Enable. If CPUID.06H:EAX.[19] = 1
Register Address: 1C4H, 452 IA32_XFD
Extended Feature Disable Control (R/W)
Controls which XSAVE-enabled features are temporarily disabled.See Section 13.14 of the Intel
Volume 1. If CPUID.(EAX=0DH,ECX=1): 
EAX[4] = 1
Register Address: 1C5H, 453 IA32_XFD_ERR
Extended Feature Disable Error Code (R/W)
Reports which XSAVE-enabled features caused a fault due to being disabled.
See Section 13.14 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1.If CPUID.(EAX=0DH,ECX=1): 
EAX[4] = 1
Register Address: 1D9H, 473 IA32_DEBUGCTL (MSR_DEBUGCTLA, MSR_DEBUGCTLB)
Trace/Profile Resource Control (R/W) 06_0EH
0 LBR: Setting this bit to 1 enables th e processor to record a running trace 
of the most recent branches taken by the processor in the LBR stack.06_01H
1 BTF: Setting this bit to 1 enables the processor to treat EFLAGS.TF as 
single-step on branches  instead of single-s tep on instructions.06_01H
2 BLD: Enable OS bus-lock detection. See Section 18.3.1.6 of the Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 3B.If (CPUID.(EAX=07H, 
ECX=0):ECX[24] = 1)
5:3 Reserved.
6 TR: Setting this bit to 1 enables branch trace me ssages to be sent. 06_0EH
7 BTS: Setting this bit enables branch trace mess ages (BTMs) to be logged 
in a BTS buffer.06_0EH
8 BTINT: When clear, BTMs are logged in  a BTS buffer in circular fashion. 
When this bit is set, an  interrupt is generated by  the BTS facility when 
the BTS buffer is full.06_0EH
9 1: BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. 06_0FH
10 BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. 06_0FH
11 FREEZE_LBRS_ON_PMI: When set, th e LBR stack is frozen on a PMI 
request.If CPUID.01H: ECX[15] = 1 && 
CPUID.0AH: EAX[7:0] > 1
12 FREEZE_PERFMON_ON_PMI: When set,  each ENABLE bit of the global 
counter control MSR are frozen (address 38FH) on a PMI request.If CPUID.01H: ECX[15] = 1 && 
13 ENABLE_UNCORE_PMI: When set, enables the logica l processor to 
receive and generate PMI on behalf of the uncore.06_1AH
14 FREEZE_WHILE_SMM: When set, fr eezes perfmon an d trace messages 
while in SMM.If  IA32_PERF_CAPABILITIES[12] 
= 1
15 RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If (CPUID.(EAX=07H, 
ECX=0):EBX[11] = 1)Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-21MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1DDH, 477 IA32_LER_FROM_IP
Last Event Record Sour ce IP Register (R/W)
63:0 FROM_IP
The source IP of the recorded bran ch or event, in  canonical form.Reset Value: 0
Register Address: 1DEH, 478 IA32_LER_TO_IP
Last Event Record Destin ation IP Register (R/W)
63:0 TO_IP
The destination IP of the recorded branch or event, in canonical form.Reset Value: 0
Register Address: 1E0H, 480 IA32_LER_INFO
Last Event Record Info Register (R/W)55:0 Undefined, may be zero or non-zero . Writes of non- zero values do not 
fault, but reads may re turn a different value.Reset Value: 0
59:56 BR_TYPE
The branch type recorded by this LBR. Encodings match those of 
IA32_LBR_x_INFO.Reset Value: 0
60 Undefined, may be zero or non-zero. Writes of non- zero values do not 
61 TSX_ABORT
This LBR record is a TSX abort. On processors that do not support Intel®

63:0 TO_IP
This LBR record is a TSX abort. On processors that do not support Intel® 
TSX (CPUID.07H.EBX.HLE[bit 4]=0 and CPUID.07H.EBX.RTM[bit 11]=0), 
this bit is undefined.Reset Value: 0
62 IN_TSX
This LBR record records a branch that retired during a TSX transaction. 
On processors that do not support Intel® TSX (CPUID.07H.EBX.HLE[bit 
4]=0 and CPUID.07H.EBX.RTM[bit 11]=0), this bit is undefined.Reset Value: 0
63 MISPRED
The recorded branch ta ken/not-taken resolution (for conditional 
branches) or target (for any indirect branch, including RETs) was mispredicted.Reset Value: 0
Register Address: 1F2H, 498 IA32_SMRR_PHYSBASE
SMRR Base Address (Wri teable only in SMM) 
Base address of SMM memory range.If IA32_MTRRCAP.SMRR[11] = 1
7:0 Type. Specifies memory type of the range.
11:8 Reserved.
31:12 PhysBase
SMRR physical Base Address.
Register Address: 1F3H, 499 IA32_SMRR_PHYSMASK
SMRR Range Mask (Writeable only in SMM) 
Range Mask of SMM memory range.If IA32_MTRRCAP[SMRR] = 1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-22 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
10:0 Reserved.
11 Valid
Enable range mask.
31:12 PhysMask
SMRR address range mask.
Register Address: 1F8H, 504 IA32_PLATFORM_DCA_CAP
DCA Capability (R) If CPUID.01H: ECX[18] = 1 
Register Address: 1F9H, 505 IA32_CPU_DCA_CAP
If set, CPU supports Prefetch-Hin t type. If CPUID.01H: ECX[18] = 1 
Register Address: 1FAH, 506 IA32_DCA_0_CAP
DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1 
0 DCA_ACTIVE: Set by HW when DCA is  fuse-enabled and no defeatures 
are set.
2:1 TRANSACTION
6:3 DCA_TYPE10:7 DCA_QUEUE_SIZE
12:11 Reserved.
16:13 DCA_DELAY: Writes will update the register but have no HW side-effect.
23:17 Reserved.
24 SW_BLOCK: SW can request DC A block by setting this bit.
25 Reserved.26 HW_BLOCK: Set when DCA is bloc ked by HW (e.g., CR0.CD = 1).
31:27 Reserved.
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0 (MTRRphysBase0)
See Section 12.11.2.3, “Variable Ra nge MTRRs.” If IA32_MTRRCAP[7:0] > 0
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
MTRRphysMask0 If IA32_MTRRCAP[7:0] > 0
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
 MTRRphysBase1 If IA32_MTRRCAP[7:0] > 1
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
 MTRRphysMask1 If IA32_MTRRCAP[7:0] > 1
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
 MTRRphysBase2 If IA32_MTRRCAP[7:0] > 2
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
 MTRRphysMask2 If IA32_MTRRCAP[7:0] > 2
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
MTRRphysBase3 If IA32_MTRRCAP[7:0] > 3Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-23MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
MTRRphysMask3 If IA32_MTRRCAP[7:0] > 3
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
MTRRphysBase4 If IA32_MTRRCAP[7:0] > 4
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
MTRRphysMask4 If IA32_MTRRCAP[7:0] > 4
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
MTRRphysBase5 If IA32_MTRRCAP[7:0] > 5
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
MTRRphysMask5 If IA32_MTRRCAP[7:0] > 5
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
MTRRphysBase6 If IA32_MTRRCAP[7:0] > 6
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
MTRRphysMask6 If IA32_MTRRCAP[7:0] > 6
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
MTRRphysBase7 If IA32_MTRRCAP[7:0] > 7
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
MTRRphysMask7 If IA32_MTRRCAP[7:0] > 7
Register Address: 210H, 528 IA32_MTRR_PHYSBASE8
MTRRphysBase8 If IA32_MTRRCAP[7:0] > 8
Register Address: 211H, 529 IA32_MTRR_PHYSMASK8
MTRRphysMask8 If IA32_MTRRCAP[7:0] > 8
Register Address: 212H, 530 IA32_MTRR_PHYSBASE9
MTRRphysBase9 If IA32_MTRRCAP[7:0] > 9
Register Address: 213H, 531 IA32_MTRR_PHYSMASK9
MTRRphysMask9 If IA32_MTRRCAP[7:0] > 9
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
MTRRfix64K_00000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
MTRRfix16K_80000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
MTRRfix16K_A0000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000 (MTRRfix4K_C0000)
See Section 12.11.2.2, “Fixed Range MTRRs.” If CPUID.01H: EDX.MTRR[12] =1
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
MTRRfix4K_C8000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-24 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
MTRRfix4K_D0000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
MTRRfix4K_D8000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
MTRRfix4K_E0000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
MTRRfix4K_E8000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
MTRRfix4K_F0000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1
Register Address: 277H, 631 IA32_PAT
IA32_PAT (R/W) If CPUID.01H: EDX.MTRR[16] =1
2:0 PA0
10:8 PA115:11 Reserved.
18:16 PA2
23:19 Reserved.26:24 PA3
34:32 PA439:35 Reserved.
42:40 PA5
47:43 Reserved.50:48 PA6
55:51 Reserved.
58:56 PA763:59 Reserved.
Register Address: 280H, 640 IA32_MC0_CTL2
MSR to enable/disable CMCI ca pability for bank 0. (R/W)
See Section 16.3.2.5, “IA32_MC i_CTL2 MSRs.”If IA32_MCG_CAP[10] = 1 && 
IA32_MCG_CAP[7:0] > 0 
14:0 Corrected error count threshold.
29:15 Reserved.
30 CMCI_EN
63:31 Reserved.
Register Address: 281H, 641 IA32_MC1_CTL2Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-25MODEL-SPECIFIC REGISTERS (MSRS)
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 && 
IA32_MCG_CAP[7:0] > 1
Register Address: 282H, 642 IA32_MC2_CTL2
IA32_MCG_CAP[7:0] > 2
Register Address: 283H, 643 IA32_MC3_CTL2
IA32_MCG_CAP[7:0] > 3
Register Address: 284H, 644 IA32_MC4_CTL2
IA32_MCG_CAP[7:0] > 4
Register Address: 285H, 645 IA32_MC5_CTL2
IA32_MCG_CAP[7:0] > 5
Register Address: 286H, 646 IA32_MC6_CTL2
IA32_MCG_CAP[7:0] > 6
Register Address: 287H, 647 IA32_MC7_CTL2
IA32_MCG_CAP[7:0] > 7
Register Address: 288H, 648 IA32_MC8_CTL2
IA32_MCG_CAP[7:0] > 8
Register Address: 289H, 649 IA32_MC9_CTL2
IA32_MCG_CAP[7:0] > 9
Register Address: 28AH, 650 IA32_MC10_CTL2
IA32_MCG_CAP[7:0] > 10
Register Address: 28BH, 651 IA32_MC11_CTL2
IA32_MCG_CAP[7:0] > 11
Register Address: 28CH, 652 IA32_MC12_CTL2
IA32_MCG_CAP[7:0] > 12
Register Address: 28DH, 653 IA32_MC13_CTL2
IA32_MCG_CAP[7:0] > 13
Register Address: 28EH, 654 IA32_MC14_CTL2
IA32_MCG_CAP[7:0] > 14
Register Address: 28FH, 655 IA32_MC15_CTL2Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-26 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
IA32_MCG_CAP[7:0] > 15
Register Address: 290H, 656 IA32_MC16_CTL2
IA32_MCG_CAP[7:0] > 16
Register Address: 291H, 657 IA32_MC17_CTL2
IA32_MCG_CAP[7:0] > 17
Register Address: 292H, 658 IA32_MC18_CTL2
IA32_MCG_CAP[7:0] > 18
Register Address: 293H, 659 IA32_MC19_CTL2
IA32_MCG_CAP[7:0] > 19
Register Address: 294H, 660 IA32_MC20_CTL2
IA32_MCG_CAP[7:0] > 20
Register Address: 295H, 661 IA32_MC21_CTL2
IA32_MCG_CAP[7:0] > 21
Register Address: 296H, 662 IA32_MC22_CTL2
IA32_MCG_CAP[7:0] > 22
Register Address: 297H, 663 IA32_MC23_CTL2

IA32_MCG_CAP[7:0] > 23
Register Address: 298H, 664 IA32_MC24_CTL2
IA32_MCG_CAP[7:0] > 24
Register Address: 299H, 665 IA32_MC25_CTL2
IA32_MCG_CAP[7:0] > 25
Register Address: 29AH, 666 IA32_MC26_CTL2
IA32_MCG_CAP[7:0] > 26
Register Address: 29BH, 667 IA32_MC27_CTL2
IA32_MCG_CAP[7:0] > 27
Register Address: 29CH, 668 IA32_MC28_CTL2
IA32_MCG_CAP[7:0] > 28
Register Address: 29DH, 669 IA32_MC29_CTL2Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-27MODEL-SPECIFIC REGISTERS (MSRS)
IA32_MCG_CAP[7:0] > 29
Register Address: 29EH, 670 IA32_MC30_CTL2
IA32_MCG_CAP[7:0] > 30
Register Address: 29FH, 671 IA32_MC31_CTL2
IA32_MCG_CAP[7:0] > 31
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
MTRRdefType (R/W) If CPUID.01H: EDX.MTRR[12] =1
2:0 Default Memory Type
9:3 Reserved.
10 Fixed Range MTRR Enable 11 MTRR Enable 
63:12 Reserved.
Register Address: 309H, 777 IA32_FIXED_CTR0
 Fixed-Function Performance Counter 0 (R/W): Count s Instr_Retired.Any. If CPUID.0AH: EDX[4:0] > 0
Register Address: 30AH, 778 IA32_FIXED_CTR1
Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If CPUID.0AH: EDX[4:0] > 1
Register Address: 30BH, 779 IA32_FIXED_CTR2
Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If CPUID.0AH: EDX[4:0] > 2
Register Address: 345H, 837 IA32_PERF_CAPABILITIES
Read Only MSR that enumerates the existence of performance monitoring features. (R/O) If CPUID.01H: ECX[15] = 1
5:0 LBR format
6 PEBS Trap7 PEBSSaveArchRegs
11:8 PEBS Record Format
12 1: Freeze while SMM is supported.13 1: Full width of counter writable via IA32_A_PMCx.
14 PEBS_BASELINE
15 1: Performance metrics available.16 1: PEBS output will be written into the Intel PT trac e stream. If CPUID.0x7.0.EBX[25]=1
63:17 Reserved.
Register Address: 38DH, 909 IA32_FIXED_CTR_CTRL
Fixed-Function Performance Counter Control (R/W)
Counter increments while the results of ANDing respective enable bit in 
IA32_PERF_GLOBAL_CTRL with the corresponding  OS or USR bits in this MSR is true.If CPUID.0AH: EAX[7:0] > 1
0 EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
1 EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-28 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2 AnyThr0: When set to 1, it enables counting the associated event 
core. When set to 0, the counter only increments the associated event 
conditions occurrin g in the logical processor which programmed the MSR.If CPUID.0AH:EAX[7:0] > 2 && 
CPUID.0AH:EDX[15]=0
3 EN0_PMI: Enable PMI when fixed counter 0 overflows.
4 EN1_OS: Enable Fixed Counter 1to count while CPL = 0.5 EN1_Usr: Enable Fixed Counter 1to count while CPL > 0.
6 AnyThr1: When set to 1, it enables counting the associated event 
core. When set to 0, the counter only increments the associated event conditions occurrin g in the logical processor which programmed the MSR.If CPUID.0AH:EAX[7:0] > 2 && 
7 EN1_PMI: Enable PMI when fixed counter 1 overflows.
8 EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.9 EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
10 AnyThr2: When set to 1, it enables counting the associated event 
11 EN2_PMI: Enable PMI when fixed counter 2 overflows.
12 EN3_OS: Enable Fixed Counter 3 to count while CPL = 0.
13 EN3_Usr: Enable Fixed Counter 3 to count while CPL > 0.
14 Reserved.15 EN3_PMI: Enable PMI when fixed counter 3 overflows.
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
Global Performance Counter Status (R/O) If CPUID.0AH: EAX[7:0] > 0 II 
(CPUID.(EAX=07H, ECX=0):EBX[25] = 1 && 
CPUID.(EAX=014H, ECX=0):ECX[0] 
= 1)
0 Ovf_PMC0: Overflow status of IA32 _PMC0. If CPUID.0AH: EAX[15:8] > 0
1 Ovf_PMC1: Overflow status of IA32 _PMC1. If CPUID.0AH: EAX[15:8] > 1
2 Ovf_PMC2: Overflow status of IA32 _PMC2. If CPUID.0AH: EAX[15:8] > 2
3 Ovf_PMC3: Overflow status of IA32 _PMC3. If CPUID.0AH: EAX[15:8] > 3
n Ovf_PMCn: Overflow status of IA32_PMCn. If CPUID.0AH: EAX[15:8] > n
31:n+1 Reserved.32 Ovf_FixedCtr0: Overflow status of IA32 _FIXED_CTR0. If CPUID.0AH: EAX[7:0] > 1
33 Ovf_FixedCtr1: Overflow status of IA32 _FIXED_CTR1. If CPUID.0AH: EAX[7:0] > 1
34 Ovf_FixedCtr2: Overflow status of IA32 _FIXED_CTR2. If CPUID.0AH: EAX[7:0] > 1
47:35 Reserved.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-29MODEL-SPECIFIC REGISTERS (MSRS)
48 OVF_PERF_METRICS: If this bit is set, it indicates that PERF_METRIC 
counter has overflowed and a PMI is triggered; however, an overflow of fixed counter 3 should no rmally happen fi rst. If this bit is clear no 
overflow occurred.
54:49 Reserved.
55 Trace_ToPA_PMI: A PMI occurred du e to a ToPA entry memory buffer 
that was completely filled.If CPUID.(EAX=07H, 
ECX=0):EBX[25] = 1 && 
= 1
57:56 Reserved.
58 LBR_Frz. LBRs are frozen due to:
•I A 3 2 _ D E B U G C T L . F R EEZE_LBR_ON_PMI=1.
• The LBR stack overflowed.If CPUID.0AH: EAX[7:0] > 3
59 CTR_Frz. Performance counters in the core PMU are frozen due to:
• IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI=1.
• One or more core PM U counters overflowed.If CPUID.0AH: EAX[7:0] > 3
60 ASCI: Data in the performance counters in the core PMU may include 
contributions from the dire ct or indirect operation Intel SGX to protect an 
enclave.If CPUID.(EAX=07H, 
ECX=0):EBX[2] = 1
61 Ovf_Uncore: Uncore counter overflow  status. If CPUID.0AH: EAX[7:0] > 2
62 OvfBuf: DS SAVE area Buffer overfl ow status. If CPUID.0AH: EAX[7:0] > 0
63 CondChgd: Status bits of this register have changed. If CPUID.0AH: EAX[7:0] > 0
Register Address: 38FH, 911 IA32_PERF_GLOBAL_CTRL
Global Performance Counter Control (R/W)
Counter increments while the result of ANDing th e respective enable bit in this MSR with the 
corresponding OS or USR bits in the general-purpose or fixed counter control MSR is true.If CPUID.0AH: EAX[7:0] > 0
0 EN_PMC0 If CPUID.0AH: EAX[15:8] > 0
1 EN_PMC1 If CPUID.0AH: EAX[15:8] > 12 EN_PMC2 If CPUID.0AH: EAX[15:8] > 2
n EN_PMCn If CPUID.0AH: EAX[15:8] > n
31:n+1 Reserved.32 EN_FIXED_CTR0 If CPUID.0AH: EDX[4:0] > 0
33 EN_FIXED_CTR1 If CPUID.0AH: EDX[4:0] > 1
34 EN_FIXED_CTR2 If CPUID.0AH: EDX[4:0] > 247:35 Reserved.
48 EN_PERF_METRICS: If this bit is set and fixed counter 3 is effectively 
enabled, built-in performance metrics are enabled.
63:49 Reserved.
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
Global Performance Counter Overflow Contr ol (R/W) If CPUID.0AH: EAX[7:0] > 0 && 
CPUID.0AH: EAX[7:0] <= 3
0 Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > 0Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-30 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
1 Set 1 to Clear Ovf_PMC1 bit. If CPUID.0AH: EAX[15:8] > 1
2 Set 1 to Clear Ovf_PMC2 bit. If CPUID.0AH: EAX[15:8] > 2
n Set 1 to Clear Ovf_PMCn bit. If CPUID.0AH: EAX[15:8] > n31:n Reserved.
32 Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > 0
33 Set 1 to Clear Ovf_FIXED_CTR1 bit. If CPUID.0AH: EDX[4:0] > 134 Set 1 to Clear Ovf_FIXED_CTR2 bit. If CPUID.0AH: EDX[4:0] > 2
54:35 Reserved.
55 Set 1 to Clear Trace_ToPA_PM I bit. If (CPUID.(EAX=07H, 
ECX=0):EBX[25] = 1) && 
IA32_RTIT_CTL.ToPA = 1
60:56 Reserved.
61 Set 1 to Clear Ovf_Uncore bit. 06_2EH
62 Set 1 to Clear OvfBuf bit. If CPUID.0AH: EAX[7:0] > 063 Set 1 to clear CondChgd bit. If CPUID.0AH: EAX[7:0] > 0
Register Address: 390H, 912 IA32_PERF_GLOBAL_STATUS_RESET
Global Performance Counter Overflow Reset Control (R/W) If CPUID.0AH: EAX[7:0] > 3 II 
(CPUID.(EAX=07H, 
CPUID.(EAX=014H, ECX=0):ECX[0] = 1)

0 Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > 01 Set 1 to Clear Ovf_PMC1 bit. If CPUID.0AH: EAX[15:8] > 1
47:35 Reserved.
48 RESET_OVF_PERF_METRICS: If this bit is set, it will clear the status bit in 
the IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS 
counters.
55 Set 1 to Clear Trace_ToPA_ PMI bit. If CPUID.(EAX=07H, 
= 1
58 Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3
59 Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-31MODEL-SPECIFIC REGISTERS (MSRS)
58 Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3
Register Address: 391H, 913 IA32_PERF_GLOBAL_STATUS_SET
Global Performance Counter Overflow Set Co ntrol (R/W) If CPUID.0AH: EAX[7:0] > 3 II 
0 Set 1 to cause Ovf_PMC0 = 1. If CPUID.0AH: EAX[7:0] > 31 Set 1 to cause Ovf_PMC1 = 1. If CPUID.0AH: EAX[15:8] > 12 Set 1 to cause Ovf_PMC2 = 1. If CPUID.0AH: EAX[15:8] > 2
n Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[15:8] > n
31:n Reserved.32 Set 1 to cause Ovf_FIXED_CTR0 = 1. If CPUID.0AH: EAX[7:0] > 3
33 Set 1 to cause Ovf_FIXED_CTR1 = 1. If CPUID.0AH: EAX[7:0] > 3
34 Set 1 to cause Ovf_FIXED_CTR2 = 1. If CPUID.0AH: EAX[7:0] > 347:35 Reserved.
48 SET_OVF_PERF_METRICS: If this bit is set, it will set the status bit in the 
IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS counters.
55 Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.(EAX=07H, 
= 1
58 Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3
59 Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 358 Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3
61 Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3
62 Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 363 Reserved.
Register Address: 392H, 914 IA32_PERF_GLOBAL_INUSE
Indicator that core perfmon interface is in use. (R/O) If CPUID.0AH: EAX[7:0] > 3
0 IA32_PERFEVTSEL0 in use.
1 IA32_PERFEVTSEL1 in use. If CPUID.0AH: EAX[15:8] > 1
2 IA32_PERFEVTSEL2 in use. If CPUID.0AH: EAX[15:8] > 2n IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[15:8] > n
31:n+1 Reserved.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-32 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
32 IA32_FIXED_CTR0 in use.
33 IA32_FIXED_CTR1 in use.
34 IA32_FIXED_CTR2 in use.62:35 Reserved or model specific.
63 PMI in use.
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE
PEBS Control (R/W)
0 Enable PEBS on IA32_PMC0. 06_0FH
3:1 Reserved or model specific.31:4 Reserved.35:32 Reserved or model specific.
63:36 Reserved.
Register Address: 400H, 1024 IA32_MC0_CTL
MC0_CTL If IA32_MCG_CAP.CNT >0
Register Address: 401H, 1025 IA32_MC0_STATUS
MC0_STATUS If IA32_MCG_CAP.CNT >0
Register Address: 402H, 1026 IA32_MC0_ADDR1
MC0_ADDR If IA32_MCG_CAP.CNT >0
Register Address: 403H, 1027 IA32_MC0_MISC
MC0_MISC If IA32_MCG_CAP.CNT >0
Register Address: 404H, 1028 IA32_MC1_CTL
MC1_CTL If IA32_MCG_CAP.CNT >1
Register Address: 405H, 1029 IA32_MC1_STATUS
MC1_STATUS If IA32_MCG_CAP.CNT >1
Register Address: 406H, 1030 IA32_MC1_ADDR2
MC1_ADDR If IA32_MCG_CAP.CNT >1
Register Address: 407H, 1031 IA32_MC1_MISC
MC1_MISC If IA32_MCG_CAP.CNT >1
Register Address: 408H, 1032 IA32_MC2_CTL
MC2_CTL If IA32_MCG_CAP.CNT >2
Register Address: 409H, 1033 IA32_MC2_STATUS
MC2_STATUS If IA32_MCG_CAP.CNT >2
Register Address: 40AH, 1034 IA32_MC2_ADDR1
MC2_ADDR If IA32_MCG_CAP.CNT >2
Register Address: 40BH, 1035 IA32_MC2_MISC
MC2_MISC If IA32_MCG_CAP.CNT >2
Register Address: 40CH, 1036 IA32_MC3_CTLTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-33MODEL-SPECIFIC REGISTERS (MSRS)
MC3_CTL If IA32_MCG_CAP.CNT >3
Register Address: 40DH, 1037 IA32_MC3_STATUS
MC3_STATUS If IA32_MCG_CAP.CNT >3
Register Address: 40EH, 1038 IA32_MC3_ADDR1
MC3_ADDR If IA32_MCG_CAP.CNT >3
Register Address: 40FH, 1039 IA32_MC3_MISC
MC3_MISC If IA32_MCG_CAP.CNT >3
Register Address: 410H, 1040 IA32_MC4_CTL
MC4_CTL If IA32_MCG_CAP.CNT >4
Register Address: 411H, 1041 IA32_MC4_STATUS
MC4_STATUS If IA32_MCG_CAP.CNT >4
Register Address: 412H, 1042 IA32_MC4_ADDR1
MC4_ADDR If IA32_MCG_CAP.CNT >4
Register Address: 413H, 1043 IA32_MC4_MISC
MC4_MISC If IA32_MCG_CAP.CNT >4
Register Address: 414H, 1044 IA32_MC5_CTL
MC5_CTL If IA32_MCG_CAP.CNT >5
Register Address: 415H, 1045 IA32_MC5_STATUS
MC5_STATUS If IA32_MCG_CAP.CNT >5
Register Address: 416H, 1046 IA32_MC5_ADDR1
MC5_ADDR If IA32_MCG_CAP.CNT >5
Register Address: 417H, 1047 IA32_MC5_MISC
MC5_MISC If IA32_MCG_CAP.CNT >5
Register Address: 418H, 1048 IA32_MC6_CTL
MC6_CTL If IA32_MCG_CAP.CNT >6
Register Address: 419H, 1049 IA32_MC6_STATUS
MC6_STATUS If IA32_MCG_CAP.CNT >6
Register Address: 41AH, 1050 IA32_MC6_ADDR1
MC6_ADDR If IA32_MCG_CAP.CNT >6
Register Address: 41BH, 1051 IA32_MC6_MISC
MC6_MISC If IA32_MCG_CAP.CNT >6
Register Address: 41CH, 1052 IA32_MC7_CTL
MC7_CTL If IA32_MCG_CAP.CNT >7
Register Address: 41DH, 1053 IA32_MC7_STATUS
MC7_STATUS If IA32_MCG_CAP.CNT >7
Register Address: 41EH, 1054 IA32_MC7_ADDR1
MC7_ADDR If IA32_MCG_CAP.CNT >7Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-34 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 41FH, 1055 IA32_MC7_MISC
MC7_MISC If IA32_MCG_CAP.CNT >7
Register Address: 420H, 1056 IA32_MC8_CTL
MC8_CTL If IA32_MCG_CAP.CNT >8
Register Address: 421H, 1057 IA32_MC8_STATUS
MC8_STATUS If IA32_MCG_CAP.CNT >8
Register Address: 422H, 1058 IA32_MC8_ADDR1
MC8_ADDR If IA32_MCG_CAP.CNT >8
Register Address: 423H, 1059 IA32_MC8_MISC
MC8_MISC If IA32_MCG_CAP.CNT >8
Register Address: 424H, 1060 IA32_MC9_CTL
MC9_CTL If IA32_MCG_CAP.CNT >9
Register Address: 425H, 1061 IA32_MC9_STATUS
MC9_STATUS If IA32_MCG_CAP.CNT >9
Register Address: 426H, 1062 IA32_MC9_ADDR1
MC9_ADDR If IA32_MCG_CAP.CNT >9
Register Address: 427H, 1063 IA32_MC9_MISC
MC9_MISC If IA32_MCG_CAP.CNT >9
Register Address: 428H, 1064 IA32_MC10_CTL
MC10_CTL If IA32_MCG_CAP.CNT >10
Register Address: 429H, 1065 IA32_MC10_STATUS
MC10_STATUS If IA32_MCG_CAP.CNT >10
Register Address: 42AH, 1066 IA32_MC10_ADDR1
MC10_ADDR If IA32_MCG_CAP.CNT >10
Register Address: 42BH, 1067 IA32_MC10_MISC
MC10_MISC If IA32_MCG_CAP.CNT >10
Register Address: 42CH, 1068 IA32_MC11_CTL
MC11_CTL If IA32_MCG_CAP.CNT >11
Register Address: 42DH, 1069 IA32_MC11_STATUS
MC11_STATUS If IA32_MCG_CAP.CNT >11
Register Address: 42EH, 1070 IA32_MC11_ADDR1
MC11_ADDR If IA32_MCG_CAP.CNT >11
Register Address: 42FH, 1071 IA32_MC11_MISC
MC11_MISC If IA32_MCG_CAP.CNT >11
Register Address: 430H, 1072 IA32_MC12_CTL
MC12_CTL If IA32_MCG_CAP.CNT >12
Register Address: 431H, 1073 IA32_MC12_STATUSTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-35MODEL-SPECIFIC REGISTERS (MSRS)
MC12_STATUS If IA32_MCG_CAP.CNT >12
Register Address: 432H, 1074 IA32_MC12_ADDR1
MC12_ADDR If IA32_MCG_CAP.CNT >12
Register Address: 433H, 1075 IA32_MC12_MISC
MC12_MISC If IA32_MCG_CAP.CNT >12
Register Address: 434H, 1076 IA32_MC13_CTL
MC13_CTL If IA32_MCG_CAP.CNT >13
Register Address: 435H, 1077 IA32_MC13_STATUS
MC13_STATUS If IA32_MCG_CAP.CNT >13
Register Address: 436H, 1078 IA32_MC13_ADDR1
MC13_ADDR If IA32_MCG_CAP.CNT >13
Register Address: 437H, 1079 IA32_MC13_MISC
MC13_MISC If IA32_MCG_CAP.CNT >13
Register Address: 438H, 1080 IA32_MC14_CTL
MC14_CTL If IA32_MCG_CAP.CNT >14
Register Address: 439H, 1081 IA32_MC14_STATUS
MC14_STATUS If IA32_MCG_CAP.CNT >14
Register Address: 43AH, 1082 IA32_MC14_ADDR1
MC14_ADDR If IA32_MCG_CAP.CNT >14
Register Address: 43BH, 1083 IA32_MC14_MISC
MC14_MISC If IA32_MCG_CAP.CNT >14
Register Address: 43CH, 1084 IA32_MC15_CTL
MC15_CTL If IA32_MCG_CAP.CNT >15
Register Address: 43DH, 1085 IA32_MC15_STATUS
MC15_STATUS If IA32_MCG_CAP.CNT >15
Register Address: 43EH, 1086 IA32_MC15_ADDR1
MC15_ADDR If IA32_MCG_CAP.CNT >15
Register Address: 43FH, 1087 IA32_MC15_MISC
MC15_MISC If IA32_MCG_CAP.CNT >15
Register Address: 440H, 1088 IA32_MC16_CTL
MC16_CTL If IA32_MCG_CAP.CNT >16

Register Address: 441H, 1089 IA32_MC16_STATUS
MC16_STATUS If IA32_MCG_CAP.CNT >16
Register Address: 442H, 1090 IA32_MC16_ADDR1
MC16_ADDR If IA32_MCG_CAP.CNT >16
Register Address: 443H, 1091 IA32_MC16_MISC
MC16_MISC If IA32_MCG_CAP.CNT >16Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-36 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 444H, 1092 IA32_MC17_CTL
MC17_CTL If IA32_MCG_CAP.CNT >17
Register Address: 445H, 1093 IA32_MC17_STATUS
MC17_STATUS If IA32_MCG_CAP.CNT >17
Register Address: 446H, 1094 IA32_MC17_ADDR1
MC17_ADDR If IA32_MCG_CAP.CNT >17
Register Address: 447H, 1095 IA32_MC17_MISC
MC17_MISC If IA32_MCG_CAP.CNT >17
Register Address: 448H, 1096 IA32_MC18_CTL
MC18_CTL If IA32_MCG_CAP.CNT >18
Register Address: 449H, 1097 IA32_MC18_STATUS
MC18_STATUS If IA32_MCG_CAP.CNT >18
Register Address: 44AH, 1098 IA32_MC18_ADDR1
MC18_ADDR If IA32_MCG_CAP.CNT >18
Register Address: 44BH, 1099 IA32_MC18_MISC
MC18_MISC If IA32_MCG_CAP.CNT >18
Register Address: 44CH, 1100 IA32_MC19_CTL
MC19_CTL If IA32_MCG_CAP.CNT >19
Register Address: 44DH, 1101 IA32_MC19_STATUS
MC19_STATUS If IA32_MCG_CAP.CNT >19
Register Address: 44EH, 1102 IA32_MC19_ADDR1
MC19_ADDR If IA32_MCG_CAP.CNT >19
Register Address: 44FH, 1103 IA32_MC19_MISC
MC19_MISC If IA32_MCG_CAP.CNT >19
Register Address: 450H, 1104 IA32_MC20_CTL
MC20_CTL If IA32_MCG_CAP.CNT >20
Register Address: 451H, 1105 IA32_MC20_STATUS
MC20_STATUS If IA32_MCG_CAP.CNT >20
Register Address: 452H, 11061106 IA32_MC20_ADDR1
MC20_ADDR If IA32_MCG_CAP.CNT >20
Register Address: 453H, 1107 IA32_MC20_MISC
MC20_MISC If IA32_MCG_CAP.CNT >20
Register Address: 454H, 1108 IA32_MC21_CTL
MC21_CTL If IA32_MCG_CAP.CNT >21
Register Address: 455H, 1109 IA32_MC21_STATUS
MC21_STATUS If IA32_MCG_CAP.CNT >21
Register Address: 456H, 1110 IA32_MC21_ADDR1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-37MODEL-SPECIFIC REGISTERS (MSRS)
MC21_ADDR If IA32_MCG_CAP.CNT >21
Register Address: 457H, 1111 IA32_MC21_MISC
MC21_MISC If IA32_MCG_CAP.CNT >21
Register Address: 458H, 1112 IA32_MC22_CTL
MC22_CTL If IA32_MCG_CAP.CNT >22
Register Address: 459H, 1113 IA32_MC22_STATUS
MC22_STATUS If IA32_MCG_CAP.CNT >22
Register Address: 45AH, 1114 IA32_MC22_ADDR1
MC22_ADDR If IA32_MCG_CAP.CNT >22
Register Address: 45BH, 1115 IA32_MC22_MISC
MC22_MISC If IA32_MCG_CAP.CNT >22
Register Address: 45CH, 1116 IA32_MC23_CTL
MC23_CTL If IA32_MCG_CAP.CNT >23
Register Address: 45DH, 1117 IA32_MC23_STATUS
MC23_STATUS If IA32_MCG_CAP.CNT >23
Register Address: 45EH, 1118 IA32_MC23_ADDR1
MC23_ADDR If IA32_MCG_CAP.CNT >23
Register Address: 45FH, 1119 IA32_MC23_MISC
MC23_MISC If IA32_MCG_CAP.CNT >23
Register Address: 460H, 1120 IA32_MC24_CTL
MC24_CTL If IA32_MCG_CAP.CNT >24
Register Address: 461H, 1121 IA32_MC24_STATUS
MC24_STATUS If IA32_MCG_CAP.CNT >24
Register Address: 462H, 1122 IA32_MC24_ADDR1
MC24_ADDR If IA32_MCG_CAP.CNT >24
Register Address: 463H, 1123 IA32_MC24_MISC
MC24_MISC If IA32_MCG_CAP.CNT >24
Register Address: 464H, 1124 IA32_MC25_CTL
MC25_CTL If IA32_MCG_CAP.CNT >25
Register Address: 465H, 1125 IA32_MC25_STATUS
MC25_STATUS If IA32_MCG_CAP.CNT >25
Register Address: 466H, 1126 IA32_MC25_ADDR1
MC25_ADDR If IA32_MCG_CAP.CNT >25
Register Address: 467H, 1127 IA32_MC25_MISC
MC25_MISC If IA32_MCG_CAP.CNT >25
Register Address: 468H, 1128 IA32_MC26_CTL
MC26_CTL If IA32_MCG_CAP.CNT >26Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-38 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 469H, 1129 IA32_MC26_STATUS
MC26_STATUS If IA32_MCG_CAP.CNT >26
Register Address: 46AH, 1130 IA32_MC26_ADDR1
MC26_ADDR If IA32_MCG_CAP.CNT >26
Register Address: 46BH, 1131 IA32_MC26_MISC
MC26_MISC If IA32_MCG_CAP.CNT >26
Register Address: 46CH, 1132 IA32_MC27_CTL
MC27_CTL If IA32_MCG_CAP.CNT >27
Register Address: 46DH, 1133 IA32_MC27_STATUS
MC27_STATUS If IA32_MCG_CAP.CNT >27
Register Address: 46EH, 1134 IA32_MC27_ADDR1
MC27_ADDR If IA32_MCG_CAP.CNT >27
Register Address: 46FH, 1135 IA32_MC27_MISC
MC27_MISC If IA32_MCG_CAP.CNT >27
Register Address: 470H, 1136 IA32_MC28_CTL
MC28_CTL If IA32_MCG_CAP.CNT >28
Register Address: 471H, 1137 IA32_MC28_STATUS
MC28_STATUS If IA32_MCG_CAP.CNT >28
Register Address: 472H, 1138 IA32_MC28_ADDR1
MC28_ADDR If IA32_MCG_CAP.CNT >28
Register Address: 473H, 1139 IA32_MC28_MISC
MC28_MISC If IA32_MCG_CAP.CNT >28
Register Address: 474H, 1140 IA32_MC29_CTL
MC29_CTL If IA32_MCG_CAP.CNT >29
Register Address: 475H, 1141 IA32_MC29_STATUS
MC29_STATUS If IA32_MCG_CAP.CNT >29
Register Address: 476H, 1142 IA32_MC29_ADDR
MC29_ADDR If IA32_MCG_CAP.CNT >29
Register Address: 477H, 1143 IA32_MC29_MISC
MC29_MISC If IA32_MCG_CAP.CNT >29
Register Address: 478H, 1144 IA32_MC30_CTL
MC30_CTL If IA32_MCG_CAP.CNT >30
Register Address: 479H, 1145 IA32_MC30_STATUS
MC30_STATUS If IA32_MCG_CAP.CNT >30
Register Address: 47AH, 1146 IA32_MC30_ADDR
MC30_ADDR If IA32_MCG_CAP.CNT >30
Register Address: 47BH, 1147 IA32_MC30_MISCTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-39MODEL-SPECIFIC REGISTERS (MSRS)
MC30_MISC If IA32_MCG_CAP.CNT >30
Register Address: 47CH, 1148 IA32_MC31_CTL
MC31_CTL If IA32_MCG_CAP.CNT >31
Register Address: 47DH, 1149 IA32_MC31_STATUS
MC31_STATUS If IA32_MCG_CAP.CNT >31
Register Address: 47EH, 1150 IA32_MC31_ADDR
MC31_ADDR If IA32_MCG_CAP.CNT >31
Register Address: 47FH, 1151 IA32_MC31_MISC
MC31_MISC If IA32_MCG_CAP.CNT >31
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Appendix A.1, “Basic VMX Information.”If CPUID.01H:ECX.[5] = 1
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pi n-Based VM-Execution Controls (R/O)
See Appendix A.3.1, “Pin-Bas ed VM-Execution Controls.”If CPUID.01H:ECX.[5] = 1
Register Address: 482H, 1154 IA32_VMX_PRO CBASED_CTLS
Capability Reporting Register of Primary Pr ocessor-Based VM-Execu tion Controls (R/O)
See Appendix A.3.2, “Primary Processor-Based VM-Execution Controls.”If CPUID.01H:ECX.[5] = 1
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of  Primary VM-Exit Controls (R/O)
See Appendix A.4.1, “Primary VM-Exit Controls.”If CPUID.01H:ECX.[5] = 1
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-Entry Controls (R/O)
See Appendix A.5, “VM-Entry Controls.”If CPUID.01H:ECX.[5] = 1
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data.”If CPUID.01H:ECX.[5] = 1
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Appendix A.7, “VMX -Fixed Bits in CR0.”If CPUID.01H:ECX.[5] = 1
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Appendix A.8, “VMX -Fixed Bits in CR4.”If CPUID.01H:ECX.[5] = 1
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Appendix A.8, “VMX -Fixed Bits in CR4.”If CPUID.01H:ECX.[5] = 1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-40 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of  VMCS Field Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration.”If CPUID.01H:ECX.[5] = 1
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3.3, “Secondary Proc essor-Based VM-Execution Controls.”If ( CPUID.01H:ECX.[5] && 
IA32_VMX_PROCBASED_CTLS[63
])
Register Address: 48CH, 1164 IA32_VMX_EPT_VPID_CAP
Capability Reporting Regist er of EPT and VPID (R/O)
See Appendix A.10, “VPID and EPT Capabilities.”If ( CPUID.01H:ECX.[5] && 
] && ( 
IA32_VMX_PROCBASED_CTLS2[3
3] || 
IA32_VMX_PROCBASED_CTLS2[37]) )
Register Address: 48DH, 1165 IA32_VMX_TRUE_PINBASED_CTLS
Capability Reporting Register of Pin-Ba sed VM-Execution Flex Controls (R/O)
See Appendix A.3.1, “Pin-Based VM-Execution Controls.”If ( CPUID.01H:ECX.[5] && 
IA32_VMX_BASIC[55] )
Register Address: 48EH, 1166 IA32_VMX_TRUE_PROCBASED_CTLS
Capability Reporting Register of Primary Proc essor-Based VM-Execution Flex Controls (R/O)
See Appendix A.3.2, “Primary Proc essor-Based VM-Exe cution Controls.”If( CPUID.01H:ECX.[5] && 

])
] && ( 
3] || 
Register Address: 48FH, 1167 IA32_VMX_TRUE_EXIT_CTLS
Capability Reporting Register of VM-Exit Flex Controls (R/O)
See Appendix A.4, “VM-Exit Controls.”If( CPUID.01H:ECX.[5] && 
Register Address: 490H, 1168 IA32_VMX_TRUE_ENTRY_CTLS
Capability Reporting Register of VM-Entry Flex Controls (R/O)
See Appendix A.5, “VM-Entry Controls.”If( CPUID.01H:ECX.[5] && 
Register Address: 491H, 1169 IA32_VMX_VMFUNC
Capability Reporting Register of VM-Function Controls (R/O) If( CPUID.01H:ECX.[5] && 
] && IA32_VMX_PROCBASED_CTLS2[4
5])
Register Address: 492H, 1170 IA32_VMX_PROCBASED_CTLS3
Capability Reporting Register of Tertiary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3.4, “Tertiary Proc essor-Based VM-Execution Controls.”If ( CPUID.01H:ECX.[5] && 
IA32_VMX_PROCBASED_CTLS[49
])
Register Address: 493H, 1171 IA32_VMX_EXIT_CTLS2
Capability Reporting Register of Secondary VM-Exit Controls (R/O)
See Appendix A.4.2, “Secondary VM-Exit Controls.”If ( CPUID.01H:ECX.[5] && 
IA32_VMX_EXIT_CTLS[63])
Register Address: 4C1H, 1217 IA32_A_PMC0
Full Width Writable IA32_PMC0 Alias (R /W) (If CPUID.0AH: EAX[15:8] > 0) &&
IA32_PERF_CAPABILITIES[13] = 1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-41MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 4C2H, 1218 IA32_A_PMC1
Full Width Writable IA32_PM C1 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 1) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4C3H, 1219 IA32_A_PMC2
Full Width Writable IA32_PM C2 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 2) &&
Register Address: 4C4H, 1220 IA32_A_PMC3
Full Width Writable IA32_PM C3 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 3) &&
Register Address: 4C5H, 1221 IA32_A_PMC4
Full Width Writable IA32_PM C4 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 4) &&
Register Address: 4C6H, 1222 IA32_A_PMC5
Full Width Writable IA32_PM C5 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 5) &&
Register Address: 4C7H, 1223 IA32_A_PMC6
Full Width Writable IA32_PM C6 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 6) &&
Register Address: 4C8H, 1224 IA32_A_PMC7
Full Width Writable IA32_PM C7 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 7) &&
Register Address: 4D0H, 1232 IA32_MCG_EXT_CTL
Allows software to signal some  MCEs to only a single logica l processor in the system. (R/W)
See Section 16.3.1.4, “I A32_MCG_EXT_CTL MSR.”If IA32_MCG_CAP.LMCE_P =1
0 LMCE_EN
Register Address: 500H, 1280 IA32_SGX_SVN_STATUS
Status and SVN Threshold of SGX Support for ACM (R/O) If CPUID.(EAX=07H, ECX=0H): 
EBX[2] = 1
0 Lock. See Section 39.11.3, “Interactions 
with Authenticate d Code Modules 
(ACMs).”
15:1 Reserved.
23:16 SGX_SVN_SINIT See Section 39.11.3, “Interactions 
(ACMs).”
Register Address: 560H, 1376 IA32_RTIT_OUTPUT_BASETable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-42 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Trace Output Base Register (R/W) If ((CPUID.(EAX=07H, 
ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0):ECX[0] 
= 1) || 
(CPUID.(EAX=14H,ECX=0):ECX[2] = 1) ) )
6:0 Reserved.MAXPHYADDR
4-1:7 Base physical address.
63:MAXPHYADDR Reserved.
Register Address: 561H, 1377 IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Po inters Register (R/W ) If ((CPUID.(EAX=07H, 
ECX=0):EBX[25] = 1) && ( 
(CPUID.(EAX=14H,ECX=0):ECX[0] 
= 1) || (CPUID.(EAX=14H,ECX=0):ECX[2] 
= 1) ) )
6:0 Reserved.
31:7 MaskOrTableOffset.63:32 Output Offset.
Register Address: 570H, 1392 IA32_RTIT_CTL
Trace Control Register (R /W) If (CPUID.(EAX=07H, 
ECX=0):EBX[25] = 1)
0T r a c e E n1 CYCEn If (CPUID.(EAX=07H, 
ECX=0):EBX[1] = 1)
2O S
3U s e r
4 PwrEvtEn If (CPUID.(EAX=07H, 
ECX=1):EBX[5] = 1)
5 FUPonPTW If (CPUID.(EAX=07H, 
ECX=1):EBX[4] = 1)
6F a b r i c E n I f  ( C P U I D . ( E A X = 0 7 H ,  
ECX=0):ECX[3] = 1)
7 CR3Filter If (CPUID.(EAX=14H, 
ECX=0):EBX[0] = 1)
8T o P A9 MTCEn If (CPUID.(EAX=07H, 
ECX=0):EBX[3] = 1)
10 TSCEn
11 DisRETC
12 PTWEn If (CPUID.(EAX=07H, 
13 BranchEnTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-43MODEL-SPECIFIC REGISTERS (MSRS)
17:14 MTCFreq. If (CPUID.(EAX=07H, 
18 Reserved, must be zero.
22:19 CycThresh If (CPUID.(EAX=07H, 
23 Reserved, must be zero.
27:24 PSBFreq If (CPUID.(EAX=07H, 
30:28 Reserved, must be zero.31 EventEn If (CPUID.(EAX=14H, 
ECX=0):EBX[7] = 1)
35:32 ADDR0_CFG If (CPUID.(EAX=07H, 
ECX=1):EAX[2:0] > 0)
39:36 ADDR1_CFG If (CPUID.(EAX=07H, 
ECX=1):EAX[2:0] > 1)
43:40 ADDR2_CFG If (CPUID.(EAX=07H, 
ECX=1):EAX[2:0] > 2)
47:44 ADDR3_CFG If (CPUID.(EAX=07H, 
ECX=1):EAX[2:0] > 3)
54:48 Reserved, must be zero.55 DisTNT If (CPUID.(EAX=14H, 
ECX=0):EBX[8] = 1)
56 InjectPsbPmiOnEnable If (CPUID.(EAX=07H, 
ECX=1):EBX[6] = 1)
63:57 Reserved, must be zero.
Register Address: 571H, 1393 IA32_RTIT_STATUS
Tracing Status Register (R/W) If (CPUID.(EAX=07H, 
0 FilterEn (writes ignore d). If (CPUID.(EAX=07H, 
ECX=0):EBX[2] = 1)
1 ContexEn (writes ignored).2 TriggerEn (writes ignored).
4E r r o r5S t o p p e d
6 PendPSB If (CPUID.(EAX=07H, 
ECX=0):EBX[6] = 1)
7 PendToPAPMI If (CPUID.(EAX=07H, 
31:8 Reserved, must be zero.
48:32 PacketByteCnt If (CPUID.(EAX=07H, 
ECX=0):EBX[1] > 3)Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-44 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 572H, 1394 IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W) If (CPUID.(EAX=07H, 
4:0 Reserved.63:5 CR3[63:5] value to match.
Register Address: 580H, 1408 IA32_RTIT_ADDR0_A
Region 0 Start Address (R/W) If (CPUID.(EAX=07H, 
47:0 Virtual Address.63:48 SignExt_VA
Register Address: 581H, 1409 IA32_RTIT_ADDR0_B
Region 0 End Address (R/W) If (CPUID.(EAX=07H, 
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 582H, 1410 IA32_RTIT_ADDR1_A
Region 1 Start Address (R/W) If (CPUID.(EAX=07H, 
Register Address: 583H, 1411 IA32_RTIT_ADDR1_B
Region 1 End Address (R/W) If (CPUID.(EAX=07H, 
Register Address: 584H, 1412 IA32_RTIT_ADDR2_A
Region 2 Start Address (R/W) If (CPUID.(EAX=07H, 
Register Address: 585H, 1413 IA32_RTIT_ADDR2_B
Region 2 End Address (R/W) If (CPUID.(EAX=07H, 
Register Address: 586H, 1414 IA32_RTIT_ADDR3_A
Region 3 Start Address (R/W) If (CPUID.(EAX=07H, 
47:0 Virtual Address.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-45MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 587H, 1415 IA32_RTIT_ADDR3_B
Region 3 End Address (R/W) If (CPUID.(EAX=07H, 
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W) 
Points to the linear addr ess of the first byte of the DS buffer management area, which is used to 
manage the BTS and PEBS buffers.
See Section 20.6.3.4, “Debug  Store (DS) Mechanism.”If( CPUID.01H:EDX.DS[21] = 1 
63:0 The linear address of the first byte of the DS buffer management area, if 
IA-32e mode is active.
31:0 The linear address of the first byte of the DS buffer management area, if 
not in IA-32e mode.
63:32 Reserved if not in IA-32e mode.
Register Address: 6A0H, 1696 IA32_U_CET
Configure User Mode CET (R/W) Bits 1:0 are defined if 
CPUID.(EAX=07H, 
ECX=0H):ECX.CET_SS[07] = 1. 
Bits 5:2 and bits 63:10 are defined 
if CPUID.(EAX=07H, 
ECX=0H):EDX.CET_IBT[20] = 1.
0 SH_STK_EN: When set to 1, en able shadow stacks at CPL3.
1 WR_SHSTK_EN: When set to 1, enables the WRSSD/WRSSQ instructions.
2 ENDBR_EN: When set to 1, enab les indirect branch tracking.
3 LEG_IW_EN: Enable legacy compatibil ity treatment for indirect branch 
tracking.
4 NO_TRACK_EN: When set to 1, enables use of no-track prefix for indirect 
branch tracking.
5 SUPPRESS_DIS: When set to 1, disa bles suppression of CET indirect 
branch tracking on legacy compatibility.
9:6 Reserved; must be zero.
10 SUPPRESS: When set to 1, indirect branch tracking is suppressed. This bit 
can be written to 1 only if TRACKER is written as IDLE.

tracking.
11 TRACKER: Value of the indirect bran ch tracking state machine. Values: 
IDLE (0), WAIT_F OR_ENDBRANCH(1).
63:12 EB_LEG_BITMAP_BASE: Linear address bits 63:12 of a legacy code page 
bitmap used for legacy compatibility when indirect branch tracking is 
enabled.
If the processor does not support Inte l 64 architecture, these fields have 
only 32 bits; bits 63:32 of the MSRs  are reserved. On processors that 
support Intel 64 architecture this va lue cannot represent a non-canonical 
address. In protected mode, only 31:0 are used.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-46 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Addre ss: 6A2H, 1698 IA32_S_CET
Configure Supervisor Mode CET (R/W) See IA32_U_CET (6A0H) for 
reference; similar format.
Register Addre ss: 6A4H, 1700 IA32_PL0_SSP
Linear address to be loaded into SSP on  transition to privilege level 0. (R/W)
If the processor does not support Intel 64 architecture, these fields have only  32 bits; bits 63:32 
of the MSRs are reserved. On processors that support Intel 64 architectu re this value cannot 
represent a non-canonical address. In protected mo de, only 31:0 are loaded. Bits 1:0 of the MSR 
must be 0. Transitions to privilege le vel 0 will check that bit 2 is also 0.If CPUID.(EAX=07H, 
ECX=0H):ECX.CET_SS[07] = 1
Register Addre ss: 6A5H, 1701 IA32_PL1_SSP
Linear address to be loaded into SSP on  transition to privilege level 1. (R/W)
must be 0. Transitions to privilege level 1 from a higher privilege level will check that bit 2 is also 
0.If CPUID.(EAX=07H, 
Register Addre ss: 6A6H, 1702 IA32_PL2_SSP
Linear address to be loaded into SSP on  transition to privilege level 2. (R/W)
must be 0. Transitions to privilege level 2 from a higher privilege level will check that bit 2 is also 
Register Addre ss: 6A7H, 1703 IA32_PL3_SSP
Linear address to be loaded into SSP on  transition to privilege level 3. (R/W)
must be 0.If CPUID.(EAX=07H, 
Register Addre ss: 6A8H, 1704 IA32_INTERRUPT_SSP_TABLE_ADDR
Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using 
the IST index (when not 0) from th e interrupt gate descriptor. (R/W)
This MSR is not present on processors that do no t support Intel 64 architec ture. This field cannot 
represent a non-canonical address. If CPUID.(EAX=07H, 
Register Address: 6E0H, 1760 IA32_TSC_DEADLINE
TSC Target of Local APIC’s TSC Deadline Mode (R/W) If CPUID.01H:ECX.[24] = 1 
Register Address: 6E1H, 1761 IA32_PKRS
Specifies the PK permissions associated  with each protection domain for supervisor pages (R/W) If CPUID.(EAX=07H, 
ECX=0H):ECX.PKS [31] = 1
31:0 For domain i (i between 0 and 15), bits 2i and 2i+1 contain the AD and 
WD permissions, respectively.
Register Address: 770H, 1904 IA32_PM_ENABLE
Enable/disable HWP (R/W) I f CPUID.06H:EAX.[7] = 1 Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-47MODEL-SPECIFIC REGISTERS (MSRS)
0H W P _ E N A B L E  ( R / W 1 - O n c e )
See Section 15.4.2, “Enabling HWP.”If CPUID.06H:EAX.[7] = 1 
Register Address: 771H, 1905 IA32_HWP_CAPABILITIES
HWP Performance Range Enumeratio n (R/O) If CPUID.06H:EAX.[7] = 1 
7:0 Highest_Performance 
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.”If CPUID.06H:EAX.[7] = 1 
15:8 Guaranteed_Performance 
23:16 Most_Efficient_Performance 
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities”.If CPUID.06H:EAX.[7] = 1 
31:24 Lowest_Performance 
Register Address: 772H, 1906 IA32_HWP_REQUEST_PKG
Power Management Control Hints for All Logical Proce ssors in a Package (R/W) If CPUID.06H:EAX.[11] = 1 
7:0 Minimum_Performance  
See Section 15.4.4, “Managing HWP.”If CPUID.06H:EAX.[11] = 1 
15:8 Maximum_Performance 
23:16 Desired_Performance 
31:24 Energy_Performance_Preference 
See Section 15.4.4, “Managing HWP.”If CPUID.06H:EAX.[11] = 1 && 
CPUID.06H:EAX.[10] = 1
41:32 Activity_Window  
CPUID.06H:EAX.[9] = 1
63:42 Reserved.
Register Address: 773H, 1907 IA32_HWP_INTERRUPT
Control HWP Native Interrupts (R/W) If CPUID.06H:EAX.[8] = 1 
0 EN_Guaranteed_Performance_Change
See Section 15.4.6, “HWP Notifications.”If CPUID.06H:EAX.[8] = 1 
1E N _ E x c u r s i o n _ M i n i m u m
Register Address: 774H, 1908 IA32_HWP_REQUEST
Power Management Control Hints to a Logica l Processor (R/W) If CP UID.06H:EAX.[7] = 1
7:0 Minimum_Performance
See Section 15.4.4, “Managing HWP.”If CPUID.06H:EAX.[7] = 1 Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-48 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
15:8 Maximum_Performance  
See Section 15.4.4, “Managing HWP.”If CPUID.06H:EAX.[7] = 1 
23:16 Desired_Performance  
31:24 Energy_Performance_Preference  
See Section 15.4.4, “Managing HWP.”If CPUID.06H:EAX.[7] = 1 && 
CPUID.06H:EAX.[10] = 1 
CPUID.06H:EAX.[9] = 1 
42 Package_Control  
CPUID.06H:EAX.[11] = 1 
63:43 Reserved.
Register Address: 775H, 1909 IA32_PECI_HWP_REQUEST_INFO
IA32_PECI_HWP_REQUEST_INFO
7:0 Minimum Performance (MINIMUM_PERFORMANCE): Used by OS to read 
the latest value of PECI  minimum performance input. Default value is 0.
15:8 Maximum Performance (MAXIMUM_PER FORMANCE): Used by OS to read 
the latest value of PECI maximum pe rformance input. Default value is 0.
23:16 Reserved.31:24 Energy Performance Preference 
(ENERGY_PERFORMANCE_PREFERENCE): Used by OS to read the latest value of PECI Energy Performance Preference input. Default value is 0.
59:32 Reserved.60 EPP PECI Override  (EPP_PECI_OVERRIDE):
Indicates whether PECI is currently overriding the Energy Performance 
Preference input. If set to ‘1’, PECI is overriding the Energy Performance 
Preference input. If clear (0), OS has control over Energy Performance 
Preference input. Default value is 0.
61 Reserved.
62 Max PECI Override (MAX_PECI_OVERRIDE):
Indicates whether PECI is currently overriding the Maximum 
Performance input. If set to ‘1’, PECI is overriding the Maximum 
Performance input. If clear (0), OS has control over Maximum 
Performance input. Default value is 0.
63 Min PECI Override (MIN_PECI_OVERRIDE):
Indicates whether PECI is currently overriding the Minimum Performance 
input. If set to ‘1’, PE CI is overriding the Minimum Performance input. If 
clear (0), OS has control over Mini mum Performance input. Default value 
is 0.
Register Address: 776H, 1910 IA32_HWP_CTL
IA32_HWP_CTL If CPUID.06H:EAX.[22] = 1 Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-49MODEL-SPECIFIC REGISTERS (MSRS)
0 PKG_CTL_POLARITY 
Defines which HWP Request MSR is used whether Thread level or 
package level. When package MSR is used, the thread MSR valid bits 
define which thread MSR fields override the package.
Default value is 0.If CPUID.06H:EAX.[22] = 1 
Register Address: 777H, 1911 IA32_HWP_STATUS
Log bits indicating changes to Guaranteed & excu rsions to Minimum (R/W) If CPUID.06H:EAX.[7] = 1 
0 Guaranteed_Performance_Change (R/WC0)
See Section 15.4.5, “HWP Feedback.”If CPUID.06H:EAX.[7] = 1

is 0.
See Section 15.4.5, “HWP Feedback.”If CPUID.06H:EAX.[7] = 1 
2 Excursion_To_Minimum (R/WC0)
Register Address: 802H, 2050 IA32_X2APIC_APICID
x2APIC ID Register (R/O) I f CPUID.01H:ECX[21] = 1 && 
IA32_APIC_BASE.[10] = 1
Register Address: 803H, 2051 IA32_X2APIC_VERSION
x2APIC Version Register (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 808H, 2056 IA32_X2APIC_TPR
x2APIC Task Priority Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 80AH, 2058 IA32_X2APIC_PPR
x2APIC Processor Priori ty Register (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 80BH, 2059 IA32_X2APIC_EOI
x2APIC EOI Register (W/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 80DH, 2061 IA32_X2APIC_LDR
x2APIC Logical Destination Register  (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 80FH, 2063 IA32_X2APIC_SIVR
x2APIC Spurious Interrupt Vector Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 810H, 2064 IA32_X2APIC_ISR0
x2APIC In-Service Register Bits 31 :0 (R/O) If CPUID.01 H:ECX.[21] = 1 && 
Register Address: 811H, 2065 IA32_X2APIC_ISR1
x2APIC In-Service Register Bits 63:32 (R/O) If CPUID.01H:ECX.[21] = 1 && 
IA32_APIC_BASE.[10] = 1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-50 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 812H, 2066 IA32_X2APIC_ISR2
x2APIC In-Service Regist er Bits 95:64 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 813H, 2067 IA32_X2APIC_ISR3
x2APIC In-Service Register Bits 127:96 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 814H, 2068 IA32_X2APIC_ISR4
x2APIC In-Service Regist er Bits 159:128 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 815H, 2069 IA32_X2APIC_ISR5
x2APIC In-Service Regist er Bits 191:160 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 816H, 2070 IA32_X2APIC_ISR6
x2APIC In-Service Regist er Bits 223:192 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 817H, 2071 IA32_X2APIC_ISR7
x2APIC In-Service Regist er Bits 255:224 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 818H, 2072 IA32_X2APIC_TMR0
x2APIC Trigger Mode Register Bits 31 :0 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 819H, 2073 IA32_X2APIC_TMR1
x2APIC Trigger Mode Register Bits 63 :32 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 81AH, 2074 IA32_X2APIC_TMR2
x2APIC Trigger Mode Register Bits 95 :64 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 81BH, 2075 IA32_X2APIC_TMR3
x2APIC Trigger Mode Register Bits 12 7:96 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 81CH, 2076 IA32_X2APIC_TMR4
x2APIC Trigger Mode Register Bits 15 9:128 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 81DH, 2077 IA32_X2APIC_TMR5
x2APIC Trigger Mode Register Bits 19 1:160 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 81EH, 2078 IA32_X2APIC_TMR6
x2APIC Trigger Mode Register Bits 223: 192 (R/O) If ( CPUID.01H:ECX.[21] = 1 && 
IA32_APIC_BASE.[10] = 1)
Register Address: 81FH, 2079 IA32_X2APIC_TMR7
x2APIC Trigger Mode Register Bits 25 5:224 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Bit Fields MSR/Bit Description CommentVol. 4 2-51MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 820H, 2080 IA32_X2APIC_IRR0
x2APIC Interrupt Request Re gister Bits 31:0 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 821H, 2081 IA32_X2APIC_IRR1
x2APIC Interrupt Request Re gister Bits 63:32 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 822H, 2082 IA32_X2APIC_IRR2
x2APIC Interrupt Request Re gister Bits 95:64 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 823H, 2083 IA32_X2APIC_IRR3
x2APIC Interrupt Request Re gister Bits 127:96 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 824H, 2084 IA32_X2APIC_IRR4
x2APIC Interrupt Request Re gister Bits 159:128 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 825H, 2085 IA32_X2APIC_IRR5
x2APIC Interrupt Request Re gister Bits 191:160 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 826H, 2086 IA32_X2APIC_IRR6
x2APIC Interrupt Request Re gister Bits 223:192 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 827H, 2087 IA32_X2APIC_IRR7
x2APIC Interrupt Request Re gister Bits 255:224 (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 828H, 2088 IA32_X2APIC_ESR
x2APIC Error Status Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 82FH, 2095 IA32_X2APIC_LVT_CMCI
x2APIC LVT Corrected Machine Check Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 830H, 2096 IA32_X2APIC_ICR
x2APIC Interrupt Command Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 832H, 2098 IA32_X2APIC_LVT_TIMER
x2APIC LVT Timer Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 833H, 2099 IA32_X2APIC_LVT_THERMAL
x2APIC LVT Thermal Sensor Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 834H, 2100 IA32_X2APIC_LVT_PMI
x2APIC LVT Performance Monitor Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Bit Fields MSR/Bit Description Comment2-52 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 835H, 2101 IA32_X2APIC_LVT_LINT0
x2APIC LVT LINT0 Register (R/W ) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 836H, 2102 IA32_X2APIC_LVT_LINT1
x2APIC LVT LINT1 Register (R/W ) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 837H, 2103 IA32_X2APIC_LVT_ERROR
x2APIC LVT Error Register (R/W ) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 838H, 2104 IA32_X2APIC_INIT_COUNT
x2APIC Initial Count Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 839H, 2105 IA32_X2APIC_CUR_COUNT
x2APIC Current Count Register (R/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 83EH, 2110 IA32_X2APIC_DIV_CONF
x2APIC Divide Configuration Register (R/W) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 83FH, 2111 IA32_X2APIC_SELF_IPI
x2APIC Self IPI Register (W/O) If CPUID.01H:ECX.[21] = 1 && 
Register Address: 981H, 2433 IA32_TME_CAPABILITY
Memory Encryption Capability MSR If CPUID.07H:ECX.[13] = 1
0 Support for AES-XTS 128-bit encryption algorithm.
(NIST standard)
1 Support for AES-XTS 128-bit encr yption with inte grity algorithm.
2 Support for AES-XTS 256-bit encryption algorithm.
29:3 Reserved.
30 SUPPORT_IA32_TME _CLEAR_SAVED_KEY
Support for the IA32_TM E_CLEAR_SAVED_KEY MSR.
31 TME encryption bypass supported.35:32 MK_TME_MAX_KEYID_BITS
Number of bits which can be alloca ted for usage as ke y identifiers for 
multi-key memory encryption.
4 bits allow for a maximum value of 15, which could address 32K keys.
Zero if TME-MK is not supported.
50:36 MK_TME_MAX_KEYS
Indicates the maximum number of keys which are available for usage.This value may not be a power of 2.
KeyID 0 is specially reserved and is  not accounted fo r in this field.
63:51 Reserved.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-53MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 982H, 2434 IA32_TME_ACTIVATE
Memory Encryption  Activation MSR
This MSR is used to lock the MS Rs listed below. Any write to th e following MSRs will be ignored 
after they are locked. The lock  is reset when CPU is reset.
• IA32_TME_ACTIVATE
• IA32_TME_EXCLUDE_MASK
• IA32_TME_EXCLUDE_BASENote that IA32_TME_EXCLUDE_M ASK and IA32_TME_EXCLUDE_BASE must be configured before 
IA32_TME_ACTIVATE.If CPUID.07H:ECX.[13] = 1
0 Lock R/O – Will be set upon success ful WRMSR (or first SMI); written 
value ignored.
1 Hardware Encryption Enable
This bit also enables TME-MK; TME-MK cannot be enabled without 
enabling encryption hardware.
2K e y  S e l e c t
0: Create a new TME key (expected cold/warm boot).
1: Restore the TME key from stor age (Expected when resume from 
standby).
3 Save TME Key for Standby

standby).
3 Save TME Key for Standby 
Save key into storage to be us ed when resume from standby.
Note: This may not be supported in all processors.
7:4 TME Policy/Encryption Algorithm
Only algorithms enumerated in IA32_TME_CAPABILITY are allowed.
For example: 
0000 – AES-XTS-128.0001 – AES-XTS-128 with integrity.
0010 – AES-XTS-256.
Other values are invalid.
30:8 Reserved.
31 TME Encryption Bypass Enable
When encryption hardware is enabled:
• Total Memory Encryption is enabled using a CPU generated ephemeral 
key based on a hardware random number generator when this bit is 
set to 0.
• Total Memory Encryption is bypassed (no encryption/decryption for 
KeyID0) when this bit is set to 1. 
Software must inspect Hardware Encryption Enable (bit 1) and TME 
encryption bypass Enable (bit 31) to determine if TME encryption is 
enabled.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-54 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
35:32 MK_TME_KEYID_BITS
Reserved if TME-MK is not enumerated, otherwise:The number of key identifier bits to allocate to TME-MK usage. Similar to 
enumeration, this is an encoded value.
Writing a value greater than MK_T ME_MAX_KEYID_BITS will result in 
#GP.
Writing a non-zero value to this field will #GP if bit 1 of EAX (Hardware 
Encryption Enable) is not also set to ‘1, as encryp tion hardware must be 
enabled to use TME-MK.
Example: To support 255 keys, this field would be set to a value of 8.
47:36 Reserved.
63:48 MK_TME_CRYPTO_ALGS
Reserved if TME-MK is not enumerated, otherwise:
Bit 48: AES-XTS 128.Bit 49: AES-XTS 128 with integrity.
Bit 50: AES-XTS 256.
Bit 63:51: Reserved (#GP)Bitmask for BIOS to set which encr yption algorithms  are allowed for 
TME-MK, would be later enforced by the key loading ISA (‘1 = allowed).
Register Address: 983H, 2435 IA32_TME_EXCLUDE_MASK
Memory Encryption Exclude Mask If CPUID.07H:ECX.[13] = 110:0 Reserved.
11 Enable: When set to ‘1’, then TME_EXCLUDE_BASE and 
TME_EXCLUDE_MASK are used to define an exclusion region for 
TME/TME-MK (for KeyID=0).
MAXPHYSADDR-1:12 TMEEMASK: This field indicates the bits that must match TMEEBASE in 
order to qualify as a TME/TME-MK (f or KeyID=0) exclusion memory range 
access.
63:MAXPHYSADDR Reserved ; must be zero.
Register Address: 984H, 2436 IA32_TME_EXCLUDE_BASE
Memory Encryption Exclude Base IF CPUID.07H:ECX.[13] = 1
11:0 Reserved.MAXPHYSADDR-1:12 TMEEBASE: Base physical addr ess to be excluded for TME/TME-MK (for 
KeyID=0) encryption.
Register Address: 985H, 2437 IA32_UINTR_RR
User Interrupt Request Register (R/W) IF CPUID.07H.01H:EDX[13]=1
63:0 UIRR
Bitmap of requested user interrupt vectors.
Register Address: 986H, 2438 IA32_UINTR_HANDLER
User Interrupt Handler Address (R/W) IF CPUID.07H.01H:EDX[13]=1Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-55MODEL-SPECIFIC REGISTERS (MSRS)
63:0 UIHANDLER
User interrupt handler linear address.
Register Address: 987H, 2439 IA32_UINTR_STACKADJUST
User Interrupt Stack Adjustment (R/W) IF CPUID.07H.01H:EDX[13]=1
0L O A D _ R S P
User interrupt stack mode.
2:1 Reserved.63:3 STACK_ADJUST
Stack adjust value.
Register Address: 988H, 2440 IA32_UINTR_MISC
User-Interrupt Target-Table Size and Notifica tion Vector (R/W) If CPUID.07H.01H:EDX[13]=1
31:0 UITTSZ
The highest index of a valid entry in the user-interrupt target table. Valid 
entries are indices 0. .UITTSZ (inclusive).
39:32 UINV
User-interrupt notification vector.
63:40 Reserved.
Register Address: 989H, 2441 IA32_UINTR_PD
User Interrupt PID Address (R/W) If CPUID.07H.01H:EDX[13]=15:0 Reserved.
63:6 UPIDADDR
User-interrupt notification processing  accesses a UPID at this linear 
address.
Register Address: 98AH, 2442 IA32_UINTR_TT
User-Interrupt Target Table (R/W) If CPUID.07H.01H:EDX[13]=1
0 SENDUIPI_ENABLE
User-interrupt target table is valid.
3:1 Reserved.63:4 UITTADDR
User-interrupt target table base linear address.
Register Address: 990H, 2448 IA32_COPY_STATUS5
Status of Most Recent Platform to  Local or Local to Platform Copies  (R/O) If ((CPUID.1 9H:EBX[4] = 1) && 
(CPUID.(07H,0).ECX[23] = 1))
0 IWKEY_COPY_SUCCESSFUL
Status of most recent copy  to or from IWKeyBackup.If ((CPUID.19H:EBX[4] = 1) && 
Register Address: 991H, 2449 IA32_IWKEYBACKUP_STATUS5
Information about IWKeyBackup Register  (R/O) If ((CPUID.19H:EBX[4] = 1) && 
(CPUID.(07H,0).ECX[23] =1))Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-56 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
0B a c k u p / R e s t o r e  V a l i d
Cleared when a write to IWKeyBackup is initiated, and then set when the 
latest write of IWKeyBac kup has been written to storage that persists 
across S3/S4 sleep state. If S3/S4 is entered between when an 
IWKeyBackup write occurs and when th is bit is set, then IWKeyBackup 
may not be recovered after S3/S4 ex it. During S3/S4 sleep state exit 
(system wake up), this bit is cleared. It is set again when IWKeyBackup is 
restored from persistent storage and thus available to be copied to IWKey using IA32_COPY_PLATFORM_TO_LOCAL MSR. Another write to 
IWKeyBackup (via IA32_COPY_LOCAL_TO_PLATFORM MSR) may fail if a 
previous write has not yet set this bit.IF ((CPUID.19H:EBX[4] = 1) && 
(CPUID.(07H,0).ECX[23] =1))
1R e s e r v e d .
2 Backup Key Storage Read/Write Error
Updated prior to backup/restore valid being set. Set when an error is 
encountered while backing up or restoring a key to persistent storage.IF ((CPUID.19H:EBX[4] = 1) && 
3 IWKeyBackup Consumed
Set after the previous backup operation has been consumed by the 
platform. This does not indicate that the system  is ready for a second 
IWKeyBackup write as the previous IWKeyBackup write may still need to set Backup/restore valid.IF ((CPUID.19H:EBX[4] = 1) && 
Register Address: 9FBH, 2555 IA32_TME_CLEAR_SAVED_KEY
IA32_TME_CLEAR_S AVED_KEY (W/O)
0 TME_CLEAR_SAVED_KEY
Clear saved TME keys.
Register Address: C80H, 3200 IA32_DEBUG_INTERFACE
Silicon Debug Feature Control (R/W) If CPUID.01H:ECX.[11] = 1 
0E n a b l e  ( R / W )
BIOS set 1 to enable Silicon debug features. Default is 0.If CPUID.01H:ECX.[11] = 1 
29:1 Reserved.
30 Lock (R/W): If 1, locks any further ch ange to the MSR. The lock bit is set 
automatically on the first SMI assertion even if not explicitly set by BIOS. 
Default is 0.If CPUID.01H:ECX.[11] = 1 
31 Debug Occurred (R/O): This  “sticky bit” is set by hardware to indicate the 
status of bit 0. Default is 0.If CPUID.01H:ECX.[11] = 1 
Register Address: C81H, 3201 IA32_L3_QOS_CFG
L3 QOS Configuration (R/W) If (CPUID.(EAX=10H, 
ECX=1):ECX.[2] = 1)
Set 1 to enable L3 CAT masks and COS to operate in Code and Data 
Prioritization (CDP) mode.
63:1 Reserved. Attempts to  write to reserved bits result in a #GP(0).Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-57MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: C82H, 3202 IA32_L2_QOS_CFG
L2 QOS Configuration (R/W) If (CPUID.(EAX=10H, 
ECX=2):ECX.[2] = 1)
Set 1 to enable L2 CAT masks and COS to operate in Code and Data 
63:1 Reserved. Attempts to write to reserved bits result in a #GP(0).
Register Address: C83H, 3203 IA32_L3_IO_QOS_CFG
L3 I/O QOS Configuration (R/W)
This MSR is used to enable the I/O RDT features.If (CPUID.(EAX=0FH, 
ECX=1):EAX.[10:9] = 1)
0 L3 I/O RDT Allocation Enable.
1 L3 I/O RDT Monitoring Enable.63:2 Reserved.
Register Address: C8DH, 3213 IA32_QM_EVTSEL
Monitoring Event Select Regi ster (R/W) If (CPUID.(EAX=07H, 
ECX=0):EBX.[12] = 1)
7:0 Event ID: ID of a supported monitoring event to report via IA32_QM_CTR.31: 8 Reserved.
N+31:32 Resource Monitoring ID: ID for mo nitoring hardware to  report monitored 
data via IA32_QM_CTR.N = Ceil (Log
2 (CPUID.(EAX= 0FH, 
ECX=0H).EBX[31:0] +1))
63:N+32 Reserved.
Register Address: C8EH, 3214 IA32_QM_CTR
Monitoring Counter Register (R/O) If (CPUID.(EAX=07H, 
61:0 Resource Monitored Data.
62 Unavailable: If 1, indicates data for this RMID is not available or not 
monitored for this resource or RMID.
63 Error: If 1, indicates an unsupported RMID or event type was written to 
IA32_PQR_QM_EVTSEL.
Register Address: C8FH, 3215 IA32_PQR_ASSOC
Resource Association Register  (R/W) If ((CPUID.(EAX=07H, 
ECX=0):EBX[12] =1) or 
ECX=0):EBX[15] =1))
N-1:0 Resource Monitoring ID (R/W): ID for monitoring hardware to track 
internal operation, e.g., memory access.N = Ceil (Log2 (CPUID.(EAX= 0FH, 
31:N Reserved.

63:32 COS (R/W): The class of service (COS) to enforce (on writes); returns the 
current COS when read.If ( CPUID.(EAX=07H, 
ECX=0):EBX.[15] = 1 )
Register Address: C90H −D8FH, 3216 −3471 Reserved MSR Address Space for CAT Mask Registers
See Section 18.19.4.1, “Enumeration and Detection Support of Cache Allocation Technology.”Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-58 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: C90H, 3216 IA32_L3_MASK_0
L3 CAT Mask for COS0 (R/W) If (CPUID.(EAX=10H, 
ECX=0H):EBX[1] != 0)
31:0 Capacity Bit Mask (R/W)
Register Address: C90H+n, 3216+n IA32_L3_MASK_n
L3 CAT Mask for COSn (R/W) n = CPUID.(EAX=10H, 
ECX=1H):EDX[15:0]
Register Address: D10H −D4FH, 3344 −3407 Reserved MSR Address Space for L2 CAT Mask Registers
See Section 18.19.4.1, “Enumeration and Detect ion Support of Cache Allocation Technology.”
Register Address: D10H, 3344 IA32_L2_MASK_0
L2 CAT Mask for COS0 (R/W) If (CPUID.(EAX=10H, 
ECX=0H):EBX[2] != 0)
Register Address:  D10H+n, 3344+n IA32_L2_MASK_n
L2 CAT Mask for COSn (R/W) n = CPUID.(EAX=10H, 
ECX=2H):EDX[15:0]
Register Address: D90H, 3472 IA32_BNDCFGS
Supervisor State of MPX Configuration (R/W) If (CPUID.(EAX=07H, 
ECX=0H):EBX[14] = 1)
0 EN: Enable Intel MPX in supervisor mode.
1 BNDPRESERVE: Preserve the boun ds registers for near branch 
instructions in the absence of the BND prefix.
11:2 Reserved, must be zero.63:12 Base Address of Bound Directory.
Register Address: D91H, 3473 IA32_COPY_LOCAL_TO_PLATFORM5
Copy Local State to Platform Stat e (W) IF ((CPUID.19H:EBX[4] = 1) && 
ECX=0H).ECX[23] = 1))
0I W K e y B a c k u p
Copy IWKey to IWKeyBackup.IF ((CPUID.19H:EBX[4] = 1) && 
Register Address: D92H, 3474 IA32_COPY_PLATFORM_TO_LOCAL5Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-59MODEL-SPECIFIC REGISTERS (MSRS)
Copy Platform State to Local Stat e (W) IF ((CPUID.19H:EBX[4] = 1) && 
(CPUID.(EAX=07H, ECX=0H).ECX[23] = 1))
Copy IWKeyBackup to IWKey.IF ((CPUID.19H:EBX[4] = 1) && 
Register Address: D93H, 3475 IA32_PASID
Process Address Space Identifier. (R/W)
19:0 Process address space identifier (PASID). Specifies the PASID of the 
currently running software thread.
30:20 Reserved.
31 Valid. Execution of ENQCMD caus es a #GP if this bit is clear.
Register Address: DA0H, 3488 IA32_XSS
Extended Supervisor State Mask (R/W) If( CPUID.(0DH, 1):EAX.[3] = 1 
7:0 Reserved.8P T  S t a t e  ( R / W )
9 Reserved. 
10 PASID State (R/W)11 CET_U State (R/W)
12 CET_S State (R/W)
13 HDC State (R/W)14 UINTR State (R/W)
15 LBR State (R/W)
16 HWP State (R/W)63:17 Reserved. 
Register Address: DB0H, 3504 IA32_PKG_HDC_CTL
Package Level Enable/disable HDC (R/W) If CPUID.06H:EAX.[13] = 1 
0H D C _ P k g _ E n a b l e  ( R / W )
Force HDC idling or wake up HDC-idle d logical processors in the package. 
See Section 15.5.2, “Packa ge level Enabling HDC.”If CPUID.06H:EAX.[13] = 1 
Register Address: DB1H, 3505 IA32_PM_CTL1
Enable/disable HWP (R/W) I f CPUID.06H:EAX.[13] = 1 
0 HDC_Allow_Block (R/W)
Allow/Block this logical processor for package level HDC control. See 
Section 15.5.3.If CPUID.06H:EAX.[13] = 1 
Register Address: DB2H, 3506 IA32_THREAD_STALLTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-60 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Per-Logical_Processor_ID HDC Idle Resi dency (R/0) If CPUID.06H:EAX.[13] = 1 
63:0 Stall_Cycle_Cnt (R/W)
Stalled cycles due to HDC forced id le on this logica l processor. See 
Section 15.5.4.1.If CPUID.06H:EAX.[13] = 1 
Register Address: 1200H −121FH, 4608 −4639 IA32_LBR_x_INFO
Last Branch Record Entr y X Info Register (R/W)
An attempt to read or write IA32_LBR_x_INFO such that x ≥ IA32_LBR_DEPTH.DEPTH will #GP.
15:0 CYC_CNT
The elapsed CPU cycles (saturating) since the last LBR was recorded. See 
Section 18.1.3.3.Reset Value: 0
55:16 Undefined, may be zero or non-zero . Writes of non- ze ro values do not 
The branch type recorded by this LBR. Encodings:
0000B: COND
0001B: JMP Indirect0010B: JMP Direct
0011B: CALL Indirect
0100B: CALL Direct0101B: RET
011xB: Reserved
1xxxB: Other BranchReset Value: 0
60 CYC_CNT_VALID
CYC_CNT value is valid. See Section 19.1.3.3.Reset Value: 0
This LBR record is a TSX abort. On processors that do not support Intel 
this bit is  undefined.Reset Value: 0
62 IN_TSX
On processors that do not support Intel TSX (CPUID.07H.EBX.HLE[bit 4]=0 and CPUID.07H.EBX.RTM[bit 11]=0), this bit is undefined.Reset Value: 0
63 MISPRED
The recorded branch dire ction (conditional branch) or target (indirect 
branch) was mispredicted.Reset Value: 0
Register Addre ss: 1406H, 5126 IA32_MCU_CONTROL
MCU Control (R/W)
Controls the behavior of the Microcode Up date Trigger MSR, IA32_BIOS_UPDT_TRIG.If CPUID.07H.0H:EDX[29]=1 && 
MSR.IA32_ARCH_CAPABILITIES.M
CU_CONTROL=1
0L O C K
Once set, further writes to this MS R will cause a #GP(0) fault. Bypassed 
during SMM if EN_SMM_B YPASS (bit 2) is set.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-61MODEL-SPECIFIC REGISTERS (MSRS)
1 DIS_MCU_LOAD
If this bit is set on a given logical processor, then any subsequent 
attempts to load a microcode update  by that logical processor will be 
silently dropped (WRMSR 0x79 has no effect).
2 EN_SMM_BYPASS
If set, then writes to IA32_MCU _CONTROL are allowed during SMM 
regardless of the LOCK bit. This en ables BIOS to Opt-In to the SMM 
Bypass functionality.
Register Address: 14CEH, 5326 IA32_LBR_CTL
Last Branch Record Enabling and Configuration Register (R/W)
0L B R E n
When set, enables LBR recording.Reset Value: 0
1O S
When set, allows LBR recording when CPL == 0.Reset Value: 0
2U S R
When set, allows LBR re cording when CPL != 0.Reset Value: 0
3 CALL_STACK
When set, records bran ches in call-stack mode . See Section 19.1.2.4.Reset Value: 0
15:4 Reserved. Reset Value: 0
16 COND
When set, records taken conditional branches. See Section 19.1.2.3.
17 NEAR_REL_JMP
When set, records near relative JMPs. See Section 19.1.2.3.
18 NEAR_IND_JMP
When set, records near indire ct JMPs. See Section 19.1.2.3.
19 NEAR_REL_CALL
When set, records near relative CALLs. See Section 19.1.2.3.
20 NEAR_IND_CALL
When set, records near indirect CALLs. See Section 19.1.2.3.
21 NEAR_RET
When set, records near RETs. See Section 19.1.2.3.
22 OTHER_BRANCH
When set, records other branches. See Section 19.1.2.3.
Register Address: 14CFH, 5327 IA32_LBR_DEPTH
Last Branch Record  Maximum Stack Depth Register (R/W)Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-62 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
N:0 DEPTH
The number of LBRs to be used fo r recording. Supported values are 
indicated by the bitmap in CPUID.(EAX=01CH,ECX=0):EAX[7:0]. The reset 
value will match the maximum supported by the CPU. Writes of 
unsupported values will #GP fault.Reset Value: Varies
63:N+1 Reserved. Reset Value: 0
Register Address: 1500H −151FH, 5376 −5407 IA32_LBR_x_FROM_IP
Last Branch Record entry X source IP register (R/W). 
An attempt to read or write IA 32_LBR_x_FROM_IP such that x ≥ IA32_LBR_DEPTH.DEPTH will 
#GP.
The source IP of the recorded branch or event, in canonical form. Writes 
to bits above MAXLINADDR-1 are ignored.Reset Value: 0
Register Address: 1600H −161FH, 5632 −5663 IA32_LBR_x_TO_IP
Last Branch Record Entry X De stination IP Register (R/W)
An attempt to read or write IA32_LBR_x_TO_IP such that x ≥ IA32_LBR_DEPTH.DEPTH will #GP.
63:0 TO_IP
The destination IP of the recorded br anch or event, in canonical form. 
Writes to bits above MA XLINADDR-1 are ignored.Reset Value: 0
Register Address: 17D0H, 6096 IA32_HW_FEEDBACK_PTR
Hardware Feedback Interface Pointer If CPUID.06H:EAX.[19] = 1
When set to 1, in dicates a valid pointer is programmed into the ADDR 
field of the MSR.
11:1 Reserved.
(MAXPHYADDR-1):12 ADDR (R/W)
Physical address of the page frame of the first page of the hardware 
feedback interface structure.

#GP.
63:0 TO_IP
Register Address: 17D1H, 6097 IA32_HW_FEEDBACK_CONFIG
Hardware Feedback Interface Configuration If CPUID.06H:EAX.[19] = 10 Enable (R/W) 
When set to 1, enables the hardware feedback interface.
Register Address: 17D2H, 6098 IA32_THREAD_FEEDBACK_CHAR
Thread Feedback Characteristics (R/O) If CPUID.06H:EAX.[23] = 17:0 Application Class ID, pointing into  the Intel Thread Director structure.
62:8 Reserved.Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-63MODEL-SPECIFIC REGISTERS (MSRS)
63 Valid bit. When set to 1 the OS Schedu ler can use the Class ID (in bits 7:0) 
for its scheduling decisions.
If this bit is 0, the Class ID field should be ignored. It is recommended that 
the OS uses the last known Class ID  of the software thread for its 
scheduling decisions.
Register Address: 17D4H, 6100 IA32_HW_FEEDBACK_THREAD_CONFIG
Hardware Feedback Thread Configuration (R/W)
0 Enables Intel Thread Director. When se t to 1, logical processor scope Intel 
Thread Director is enabled. Default is 0 (disabled).
Register Address: 17DAH, 6106 IA32_HRESET_ENABLE
History Reset Enable (R/W)
0 Enable reset of the Intel Thread Director history.
31:1 Reserved for other capabilities that can be reset by the HRESET 
Register Address: 1B01H, 6913 IA32_UARCH_MISC_CTL
IA32_UARCH_MISC_CTL If 
IA32_ARCH_CAPABILITIES[12]=1
0 Data Operand Independent Timing Mode (DOITM). If 
Register Address: 4000_0000H −4000_00FFH Reserved MSR Address Space
All existing and future processors wi ll not implement MSRs  in this range.
Register Address: C000_0080H IA32_EFER
Extended Feature Enables If ( CPUID.80000001H:EDX.[20] || 
CPUID.80000001H:EDX.[29])
0 SYSCALL Enable: IA32_EFER.SCE (R/W)
9 Reserved.
10 IA-32e Mode Active: IA32_EFER.LMA (R) 
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0082H IA32_LSTARTable 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description Comment2-64 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.2 MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY
Table 2-3 lists model-specific registers (MSRs) for the Inte l Core 2 processor family and for Intel Xeon processors 
based on Intel Core microarchitecture, architectural MSR addresses are also included in Table 2-3. These proces-
sors have a CPUID Signature DisplayFamily_Dis playModel value of 06_0FH, see Table 2-1. 
MSRs listed in Table 2-2 and Table 2-3 are also supported by processors based on the Enhanced Intel Core microar-
chitecture. Processors based on the Enhanced Intel Core  microarchitecture have a CPUID Signature DisplayFami-
ly_DisplayModel value of 06_17H. IA-32e Mode System Ca ll Target Address (R/W)
Target RIP for the called procedure when SYSCALL is executed in 64-bit mode.If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0083H IA32_CSTAR
IA-32e Mode System Ca ll Target Address (R/W)
Not used, as the SYSCALL instruction is not recognized in compatibility mode.If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W) I f CPUID.80000001:EDX.[29] = 1
Register Address: C000_0100H IA32_FS_BASE
Map of BASE Address of FS (R/W ) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W ) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Ad dress of GS (R/W) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0103H IA32_TSC_AUX
Auxiliary TSC (R/W) If CPUID.80000001H: EDX[27] = 1 
or CPUID.(EAX=7,ECX=0):ECX[bit 22] = 1
31:0 AUX: Auxiliary signature of TSC.63:32 Reserved.
NOTES:
1. Some older processors may have supported this MSR as model-specific and do not enumerate it with CPUID.
2. In processors based on Intel NetBurst® microarchitecture, MS R addresses 180H-197H are supporte d, software must treat them as  
model-specific. Starting with Intel Core Duo processors, MS R addresses 180H-185H, 188H-197H are reserved.
3. The *_ADDR MSRs may or ma y not be present; this depends on flag settings in IA32_MC i_STATUS. See Section 16.3.2.3 and Section 
16.3.2.4 for more information.
4. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].
5. Further details on Key Locker and usage of this MSR can be found here:
https://software.intel.co m/content/www/us/en/devel op/download/intel-key-lo cker-specification.html .Table 2-2.  IA-32 Architectural MSRs (Contd.)
Bit Fields MSR/Bit Description CommentVol. 4 2-65MODEL-SPECIFIC REGISTERS (MSRS)
The column “Shared/Unique” applies to multi-core proce ssors based on Intel Core microarchitecture. “Unique” 
means each processor core has a separate MSR, or a bi t field in an MSR governs only a core independently. 
“Shared” means the MSR or the bit field in an MSR ad dress governs the operation of both processor cores. 
Table 2-3.  MSRs in Processors Base d on Intel® Core™ Microarchitecture
Register Address: Hex,  Decimal Register Name
Register Information / Bit Fields Bit DescriptionShared/
Unique
Register Address: 0H, 0 IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.” Unique
Register Address: 1H, 1 IA32_P5_MC_TYPE
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Unique
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and Table 2-2. Unique
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R) 
See Table 2-2.Shared
Register Address: 17H, 23 MSR_PLATFORM_ID
Model Specific Platform ID (R) Shared
7:0 Reserved.12:8 Maximum Qualified Ratio (R) 
The maximum allowed bus ratio.
49:13 Reserved.
52:50 See Table 2-2.
Register Address: 1BH, 27 IA32_APIC_BASE
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Unique
Register Address: 2AH, 42 MSR_EBL_CR_POWERON
Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates current processor configuration.Shared
1 Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processors implement R/W. 
2 Response Error Checking Enable (R/W)
Note: Not all processo r implements R/W. 
3M C E R R #  D r i v e  E n a b l e  ( R / W )  
Note: Not all processors implement R/W. 2-66 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
4 Address Parity Enable (R/W)
5 Reserved.
6 Reserved.7 BINIT# Driver Enable (R/W)
8 Output Tri-state Enabled (R/O)
9E x e c u t e  B I S T  ( R / O )
10 MCERR# Observation Enabled (R/O)
11 Intel TXT Capable Chipset. (R/O)
1 = Present; 0 = Not Present.
12 BINIT# Observation Enabled (R/O)
13 Reserved.
14 1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes.
15 Reserved.
17:16 APIC Cluster ID (R/O)18 N/2 Non-Integer Bus Ratio (R/O)
0 = Integer ratio; 1 = Non-integer ratio.
21: 20 Symmetric Arbitration ID (R/O)
26:22 Integer Bus Frequency Ratio (R/O)
Register Address: 3AH, 58 MSR_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
See Table 2-2.Unique
3S M R R  E n a b l e  ( R / W L )
When this bit is set and the lock bit is set, this make s the SMRR_PHYS_BASE 
and SMRR_PHYS_MASK registers read visible and writeable while in SMM.Unique
Register Address: 40H, 64 MSR_LASTBRAN CH_0_FROM_IPTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
UniqueVol. 4 2-67MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record  0 From IP (R/W)
One of four pairs of last br anch record registers on the last branch re cord stack. The From_IP part of the stack 
contains pointers to the so urce instructio n. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.5.Unique
Register Address: 41H, 65 MSR_LASTBRAN CH_1_FROM_IP
Last Branch Record  1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.Unique
Register Address: 42H, 66 MSR_LASTBRAN CH_2_FROM_IP
Last Branch Record  2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP. Unique
Register Address: 43H, 67 MSR_LASTBRAN CH_3_FROM_IP

Last Branch Record  3 From IP (R/W)
Register Address: 60H, 96 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
One of four pairs of last branch record registers on the last branch record stack.  This To_IP part of the stack contains 
pointers to the destination instruction.Unique
Register Address: 61H, 97 MSR_LASTBRANCH_1_TO_IP
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP. Unique
Register Address: 62H, 98 MSR_LASTBRANCH_2_TO_IP
Last Branch Record 2 To IP (R/W)
Register Address: 63H, 99 MSR_LASTBRANCH_3_TO_IP
Last Branch Record 3 To IP (R/W)
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W) 
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
Register Address: A0H, 160 MSR_SMRR_PHYSBASE
System Management Mode Base Address register (WO in SMM)
Model-specific implementation of SMRR-like interface, read visible and write only in SMM.Unique
11:0 Reserved.
31:12 PhysBase: SMRR physical Base Address.Table 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
Unique2-68 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: A1H, 161 MSR_SMRR_PHYSMASK
System Management Mode Physical Address Mask register (WO in SMM)
11 Valid: Physical address base and range mask are valid.
31:12 PhysMask: SMRR physical address range mask.
Register Address: C1H, 193 IA32_PMC0
Performance Counter Register
Register Address: C2H, 194 IA32_PMC1
Register Address: CDH, 205 MSR_FSB_FREQ
Scaleable Bus Speed (R/O)
This field indicates the intended scalable bus clock speed for processors based on Intel Core microarchitecture.Shared
2:0 • 101B: 100 MHz (FSB 400)
• 001B: 133 MHz (FSB 533)
• 011B: 167 MHz (FSB 667)
• 010B: 200 MHz (FSB 800)• 000B: 267 MHz (FSB 1067)
• 100B: 333 MHz (FSB 1333)
133.33 MHz should be utilized if pe rforming calculation with System Bus 
Speed when encoding is 001B. 
166.67 MHz should be utilized if pe rforming calculation with System Bus 
Speed when encoding is 011B.
266.67 MHz should be utilized if pe rforming calculation with System Bus 
Speed when encoding is 000B.
333.33 MHz should be utilized if pe rforming calculation with System Bus 
Speed when encoding is 100B.
This field indicates the intended scalable bus clock speed for processors based on Enhanced Intel Core 
microarchitecture.SharedTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
UniqueVol. 4 2-69MODEL-SPECIFIC REGISTERS (MSRS)
• 011B: 167 MHz (FSB 667)• 010B: 200 MHz (FSB 800)
• 000B: 267 MHz (FSB 1067)
• 100B: 333 MHz (FSB 1333)• 110B: 400 MHz (FSB 1600)
Speed when encoding is 110B.
Speed when encoding is 111B.
Maximum Performance Frequency Clock Count (R/W) 
Actual Performance Frequency Clock Count (R/W) 
Register Address: FEH, 254 IA32_MTRRCAP
See Table 2-2. Unique
11 SMRR Capability Using MSR 0A0H and 0A1H (R) Unique
Register Address: 176H, 374 IA32_SYSENTER_EIPSee Table 2-2. Unique
Register Address: 179H, 377 IA32_MCG_CAP
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status Unique
0R I P V
When set, bit indicates that the instruction addr essed by the instruction 
pointer pushed on the stack (when the machine check was generated) can be used to restart the program. If clea red, the program cannot be reliably 
restarted.Table 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
Unique2-70 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
1E I P V
pointer pushed on the st ack (when the machine check was generated) is 
directly associated with the error.
2M C I P
When set, bit indicates th at a machine check has been generated. If a second 
machine check is detected while this bit is still set, the processor enters a shutdown state. Software  should write this bit to 0 after processing a 
machine check exception.
Register Address: 186H, 390 IA32_PERFEVTSEL0
Register Address: 187H, 391 IA32_PERFEVTSEL1
See Table 2-2. Shared
Register Address: 198H, 408 MSR_PERF_STATUS
Current performance status. See Section 15.1.1, “Software In terface For Initiating Perfor mance State Transitions.” Shared
15:0 Current Performance State Value
30:16 Reserved.
31 XE Operation (R/O).
If set, XE operation is en abled. Default is cleared.
39:32 Reserved.44:40 Maximum Bus Ratio (R/O)
Indicates maximum bus ratio configured for the processor.
45 Reserved.
46 Non-Integer Bus Ratio (R/O)
Indicates non-integer bus ratio is enabled. Applie s processors based on 
Enhanced Intel Core microarchitecture.
63:47 Reserved.
Clock Modulation (R/W) 
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.Unique
Register Address: 19BH, 411 IA32_THERM_INTERRUPTTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
UniqueVol. 4 2-71MODEL-SPECIFIC REGISTERS (MSRS)
Thermal Interrupt Control (R/W) 
Thermal Monitor Status (R/W) 
Register Address: 19DH, 413 MSR_THERM2_CTL
Thermal Monitor 2 Control Unique
15:0 Reserved.16 TM_SELECT (R/W) 
Mode of automati c thermal monitor:
0 = Thermal Monitor 1 (the rmally-initiated on-die modulation of the stop-
clock duty cycle).
1 = Thermal Monitor 2 (thermally-initiated frequency transitions).
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no 
effect. Neither TM1 nor TM2 are enabled.
Enable Misc. Processor Features (R/W) 
Allows a variety of processor func tions to be enabled and disabled.
0 Fast-Strings Enable
8 Reserved.
9 Hardware Prefetcher Disable (R/W)
When set, disables the hardware prefetcher operation on streams of data. 
When clear (default), enables the prefetch queue.
Disabling of the hardware prefetcher may impact processor performance.
10 FERR# Multiplexi ng Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending break event 
within the processor.
0 =  Indicates compatible FERR# signaling behavior.
This bit must be set to 1 to su pport XAPIC interrupt model usage.Shared
11 Branch Trace Storag e Unavailable (R/O) 
See Table 2-2.SharedTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
Unique2-72 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
12 Processor Event Based Sa mpling Unavailable (R/O) 
13 TM2 Enable (R/W)
When this bit is set (1 ) and the thermal sensor indicates that the die 
temperature is at the pr e-determined threshold, the Thermal Monitor 2 
mechanism is engaged. TM2 will reduce the bus to core ratio and voltage 
according to the value last written to MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not change the VID 
signals or the bus to core ratio when the processor enters a thermally 
managed state. 
The BIOS must enable this feature if th e TM2 feature flag (CPUID.1:ECX[8]) is

The BIOS must enable this feature if th e TM2 feature flag (CPUID.1:ECX[8]) is 
set; if the TM2 feature flag is not set,  this feature is no t supported and BIOS 
must not alter the contents  of the TM2 bit location. 
The processor is operating out of specification if both this bit and the TM1 bit 
are set to 0.Shared
15:14 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W) 
18 ENABLE MONITOR FSM (R/W) 
19 Adjacent Cache Line Prefetch Disable (R/W) 
When set to 1, the proc essor fetches the cache li ne that contains data 
currently required by the processor. When set to 0, the processor fetches cache lines that comprise a ca che line pair (128 bytes).
Single processor platforms should not se t this bit. Server platforms should set 
or clear this bit based on platform performance observed in validation and testing. 
BIOS may contain a setup option that  controls the setti ng of this bit.Shared
20 Enhanced Intel SpeedStep Technology Select Lock (R/WO)
When set, this bit causes the fo llowing bits to become read-only:
• Enhanced Intel SpeedStep Technology Select Lock (this bit).
• Enhanced Intel SpeedStep Technology Enable bit.
The bit must be set before an Enhanced Intel SpeedStep Technology 
transition is requested. Th is bit is cleared on reset.Shared
21 Reserved.
22 Limit CPUID Maxval (R/W) 
23 xTPR Message Disable (R/W) 
33:24 Reserved.Table 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
UniqueVol. 4 2-73MODEL-SPECIFIC REGISTERS (MSRS)
34 XD Bit Disable (R/W)
When set to 1, the Execute Disable Bit fe ature (XD Bit) is disabled and the XD 
Bit extended feature flag will be clear (CPUID.80000001H: EDX[20]=0).
When set to a 0 (default), the Execute Disable Bit feature (if available) allows 
the OS to enable PAE paging and take advantage of data only pages.
BIOS must not alter the contents of this bit location if XD bi t is not supported. 
Writing this bit to 1 when the XD Bit extended feature flag is set to 0 may 
generate a #GP exception.Unique
36:35 Reserved.
37 DCU Prefetcher Disable (R/W)
When set to 1, the DCU L1 data cache prefetcher is disabled. The default 
value after reset is 0. BIOS may write ‘1’ to disable this feature. 
The DCU prefetcher is an L1 data cache prefetcher. When the DCU prefetcher 
detects multiple loads from  the same line done within a time limit, the DCU 
prefetcher assumes the next line will be required. The next line is prefetched 
in to the L1 data cach e from memory or L2.Unique
38 IDA Disable (R/W)
When set to 1 on pr ocessors that support IDA, th e Intel Dynamic Acceleration 
feature (IDA) is disabled and the IDA_Enable feature flag will be cleared (CPUID.06H: EAX[1]=0).
When set to a 0 on proce ssors that support IDA, CPUID.06H: EAX[1] reports 
the processor’s support of IDA is enabled.
Note: The power-on default value is used  by BIOS to detect hardware support 
of IDA. If the power- on default value is 1, IDA is available in the processor. If 
the power-on de fault value is 0, IDA is not available.Shared
39 IP Prefetcher Disable (R/W)
When set to 1, the IP prefetcher is disa bled. The default value after reset is 0. 
BIOS may write ‘1’ to disable this feature. 
The IP prefetcher is an L1 data cache prefetcher. The IP prefetcher looks for 
sequential load history to determine whether to prefetch the next expected data into the L1 cach e from memory or L2.Unique
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record  Stack TOS (R/W) 
Contains an index (bits 0-3) that  points to the MSR co ntaining the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).Unique
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W) 
Register Address: 1DDH, 477 MSR_LER_FROM_LIPTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
Unique2-74 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Last Exception Record From Linear IP (R/W) 
Contains a pointer to the last branch instruction that th e processor executed prior to the last exception that was 
generated or the last in terrupt that was handled.Unique
Register Address: 1DEH, 478 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R/W) 
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last 
exception that was generated or the last interrupt th at was handled. Unique
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7Table 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
UniqueVol. 4 2-75MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
Default Memory Types (R/W) 
Fixed-Function Performance Counter Register 0 (R/W) 
Fixed-Function Performance Counter Register 1 (R/W) 
See Table 2-2.UniqueTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
Unique2-76 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Fixed-Function Performance Counter Register 2 (R/W) 
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Unique
Register Address: 345H, 837 MSR_PERF_CAPABILITIES
R/O. This applies to processors that do no t support architectural perfmon version 2. Unique
5:0 LBR Format. See Table 2-2.6 PEBS Record Format.7 PEBSSaveArchRegs. See Table 2-2.
63:8 Reserved.
Fixed-Function-Counter Control Register (R/W) 
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 38EH, 910 MSR_PERF_GLOBAL_STATUS
See Section 20.6.2.2, “Global Co unter Control Facilities.” Unique
Register Address: 38FH, 911 MSR_PERF_GLOBAL_CTRL
Register Address: 390H, 912 MSR_PERF_GLOBAL_OVF_CTRL
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Unique
0 Enable PEBS on IA32_PMC0. (R/W)
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” Unique

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 402H, 1026 IA32_MC0_ADDRTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
UniqueVol. 4 2-77MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or contains no address if  the ADDRV flag in the 
IA32_MC0_STATUS register is clear. 
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.Unique
Register Address: 406H, 1030 IA32_MC1_ADDR
The IA32_MC1_ADDR register is either not implemented or contains no address if  the ADDRV flag in the 
IA32_MC1_STATUS register is clear. 
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” 
The IA32_MC2_ADDR register is either not implemented or contains no address if  the ADDRV flag in the 
IA32_MC2_STATUS register is clear. 
Register Address: 40CH, 1036 IA32_MC4_CTL
Register Address: 40DH, 1037 IA32_MC4_STATUS
Register Address: 40EH, 1038 IA32_MC4_ADDR
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the 
MSR_MC4_STATUS register is clear. 
Register Address: 410H, 1040 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.”
Register Address: 411H, 1041 IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 412H, 1042 IA32_MC3_ADDRTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
Unique2-78 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the 
MSR_MC3_STATUS register is clear. 
Register Address: 413H, 1043 IA32_MC3_MISC
Machine Check Error Reporting Register: Contains additional information describing the machine-check error if the 
MISCV flag in the IA32_MCi _STATUS register is set.Unique
Machine Check Error Reporting Register: Controls signaling of  #MC for errors produced by a particular hardware unit 
(or group of hardware units).Unique
Machine Check Error Reporting Register: Contains information related to a machine-check error if its VAL (valid) flag is 
set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicit ly writing 0s to them; writing 1s to them 
causes a general-protection exception.Unique
Register Address: 416H, 1046 IA32_MC5_ADDR
Machine Check Error Reporting Register: Contains the address of  the code or data memory location that produced the 
machine-check error if the ADDRV flag in the IA32_MCi_STATUS register is set.Unique
Register Address: 419H, 1045 IA32_MC6_STATUS
Applies to Intel Xeon processor 7400 series (proce ssor signature 06_1D) only. See Section 16.3.2.2, 
“IA32_MCi_STATUS MSRS,” and Chapter 24.Unique
Reporting Register of Basic VMX Capabilities (R/O) 
See Table 2-2. See Appendix A.1, “Basic VMX Information.”Unique
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O) 
See Table 2-2. See Appendix A.3, “VM-Execution Controls.”Unique
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Pr ocessor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”Unique
Capability Reporting Register of VM-Exit Controls (R/O) 
See Table 2-2. See Appendix A.4, “VM-Exit Controls.”Unique
Capability Reporting Register of VM-Entry Controls (R/O) 
See Table 2-2. See Appendix A.5, “VM-Entry Controls.”Unique
Register Address: 485H, 1157 IA32_VMX_MISCTable 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
UniqueVol. 4 2-79MODEL-SPECIFIC REGISTERS (MSRS)
Reporting Register of Miscellaneous VMX Capabilities (R/O) 
See Table 2-2. See Appendix A.6, “Miscellaneous Data.”Unique
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) 
See Table 2-2. See Appendix A.7,  “VMX-Fixed Bits in CR0.”Unique
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) 
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) 
See Table 2-2. See Appendix A.8,  “VMX-Fixed Bits in CR4.”Unique
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) 
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 2-2. See Appendix A.9, “VMCS Enumeration.”Unique
DS Save Area (R/W)
See Table 2-2. See Section 20.6.3.4, “Debug Store (DS) Mechanism.”Unique
Register Address: 107CCH, 67532 MSR_EMON_L3_CTR_CTL0
GBUSQ Event Control/Co unter Register (R/W)
Applies to Intel Xeon processor 7400 series (proce ssor signature 06_1D) only. See Section 18.2.2.Unique
Register Address: 107CDH, 67533 MSR_EMON_L3_CTR_CTL1
Register Address: 107CEH, 67534 MSR_EMON_L3_CTR_CTL2
GSNPQ Event Control/Counter Register (R/W)
Register Address: 107CFH, 67535 MSR_EMON_L3_CTR_CTL3
Register Address: 107D0H, 67536 MSR_EMON_L3_CTR_CTL4Table 2-3.  MSRs in Processors Based on  Intel® Core™ Microarchitecture (Contd.)
Unique2-80 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
FSB Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (pro cessor signature 06_1D) only. See Section 18.2.2.Unique
Register Address: 107D1H, 67537 MSR_EMON_L3_CTR_CTL5
Register Address: 107D2H, 67538 MSR_EMON_L3_CTR_CTL6
Register Address: 107D3H, 67539 MSR_EMON_L3_CTR_CTL7
Register Address: 107D8H, 67544 MSR_EMON_L3_GL_CTL
L3/FSB Common Control Register (R/W)
Extended Feature Enables

System Call Target Address (R/W)
Register Address: C000_0082H IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
System Call Flag Mask (R/W)
Map of BASE Address of FS (R/W)
Map of BASE Address of GS (R/W)
Swap Target of BASE Address of GS (R/W) 
UniqueVol. 4 2-81MODEL-SPECIFIC REGISTERS (MSRS)
2.3 MSRS IN THE 45 NM AND 32 NM INTEL ATOM® PROCESSOR FAMILY
Table 2-4 lists model-specific registers (MSRs) for 45 nm and 32 nm Intel Atom processors, architectural MSR 
addresses are also included in Table 2-4. These proce ssors have a CPUID Signature DisplayFamily_DisplayModel 
value of 06_1CH, 06_26H, 06_27H, 06_3 5H, or 06_36H; see Table 2-1. 
The column “Shared/Unique” applies to logical processors sharing the same core in processors based on the Intel 
Atom microarchitecture. “Unique” means each logical pr ocessor has a separate MSR, or a bit field in an MSR 
governs only a logical processor. “Shared” means the MSR or the bit field in an MSR address governs the operation 
of both logical processors in the same core.
Table 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Unique
See Section 2.23, “MSRs in Pentium Processors.” Shared
See Section 18.17, “Time-Stamp Counter,” and see Table 2-2. Unique
12:8 Maximum Qualified Ratio (R) 
Processor Hard Power-On Configuration (R/W) 
Always 0. 
Always 0.2-82 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
3 AERR# Drive Enable (R/W) 
Always 0.
4 BERR# Enable for initiator bus requests (R/W)
Always 0. 
Always 0.
1 = Enabled; 0 = Disabled. 
10 AERR# Observation Enabled (R/O)
Always 0.
11 Reserved.12 BINIT# Observation Enabled (R/O)
Always 0.
15 Reserved.17:16 APIC Cluster ID (R/O)
Always 00B.
19: 18 Reserved.
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64Processor (R/W)
Register Address: 40H, 64 MSR_LASTBRAN CH_0_FROM_IP
One of eight pairs of last branch reco rd registers on the last branch record  stack. The From_IP part of the stack 
contains pointers to the source instruction. See also:
• Section 18.5.UniqueTable 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
UniqueVol. 4 2-83MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 44H, 68 MSR_LASTBRAN CH_4_FROM_IP
Last Branch Record  4 From IP (R/W)
Register Address: 45H, 69 MSR_LASTBRAN CH_5_FROM_IP
Last Branch Record  5 From IP (R/W)
Register Address: 46H, 70 MSR_LASTBRAN CH_6_FROM_IP
Last Branch Record  6 From IP (R/W)
Register Address: 47H, 71 MSR_LASTBRAN CH_7_FROM_IP
Last Branch Record  7 From IP (R/W)
One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains 
Register Address: 64H, 100 MSR_LASTBRANCH_4_TO_IP
Last Branch Record 4 To IP (R/W)
Register Address: 65H, 101 MSR_LASTBRANCH_5_TO_IPTable 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Unique2-84 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record  5 To IP (R/W)
Register Address: 66H, 102 MSR_LASTBRANCH_6_TO_IP
Last Branch Record  6 To IP (R/W)
Register Address: 67H, 103 MSR_LASTBRANCH_7_TO_IP
Last Branch Record  7 To IP (R/W)
Performance counter register
This field indicates the intended scalable bus clock speed for processors based on Intel Atom microarchitecture.Shared
2:0 • 111B: 083 MHz (FSB 333)
• 101B: 100 MHz (FSB 400)
• 011B: 167 MHz (FSB 667)133.33 MHz should be utilized if pe rforming calculation with System Bus 
Register Address: FEH, 254 IA32_MTRRCAPTable 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
UniqueVol. 4 2-85MODEL-SPECIFIC REGISTERS (MSRS)
Memory Type Range Register (R) 
Register Address: 11EH, 281 MSR_BBL_CR_CTL3
Control Register 3
Used to configure the L2 Cache.Shared
0 L2 Hardware Enabled (R/O)
1 = Indicates the L2 is hardware-enabled.
0 = Indicates the L2 is hardware-disabled.
7:1 Reserved.
8L 2  E n a b l e d  ( R / W )  
1 = L2 cache has been initialized.
0 = Disabled (default).
Until this bit is set, the processor wi ll not respond to the WBINVD instruction 
or the assertion of the FLUSH# input.
22:9 Reserved.23 L2 Not Present (R/O) 
0 = L2 Present.
1 = L2 Not Present.

0R I P V
pointer pushed on the stack (when the machine check was generated) can be 
used to restart the program. If clea red, the program cannot be reliably 
restarted.
1E I P V
pointer pushed on the stack (when the machine check was generated) is 
directly associated with the error.Table 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Unique2-86 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2M C I P
machine check is detected while this bit is still set, the processor enters a 
shutdown state. Software  should write this bit to 0 after processing a 
Performance Status Shared
39:16 Reserved.44:40 Maximum Bus Ratio (R/O)
63:45 Reserved.
Thermal Monitor 2 Control Shared
15:0 Reserved.Table 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
UniqueVol. 4 2-87MODEL-SPECIFIC REGISTERS (MSRS)
16 TM_SELECT (R/W) 
Allows a variety of processor func tions to be enabled and disabled.Unique
2:1 Reserved.3 Automatic Thermal Control Circuit Enable (R/W) 
See Table 2-2. Default value is 0.Unique
9 Reserved.10 FERR# Multiplexi ng Enable (R/W)
When this bit is set (1) and the th ermal sensor indica tes that the die 
temperature is at the pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage 
according to the value last written to MSR_TH ERM2_CTL bits 15:0.
When this bit is cleared (0, default), the processor does not change the VID 
signals or the bus to core ratio wh en the processor enters a thermally 
set; if the TM2 feature flag is not set,  this feature is not supported and BIOS 
are set to 0.SharedTable 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Unique2-88 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
The bit must be set before an Enhanced  Intel SpeedStep Tech nology transition 
is requested. This bit is cleared on reset.Shared
33:24 Reserved.
34 XD Bit Disable (R/W) 
See Table 2-3.Unique
63:35 Reserved.
Contains an index (bits 0-2) that  points to the MSR co ntaining the most recent branch record.
Register Address: 1DDH, 477 MSR_LER_FROM_LIP
Last Exception Record From Linear IP (R) 
Last Exception Record To Linear IP (R) 
This area contains a pointer to the targ et of the last branch instruction that the processor executed prior to the last 
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0Table 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
UniqueVol. 4 2-89MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. SharedTable 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Unique2-90 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Shared
Fixed-Function-Counter Control Register (R/W)

Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)Table 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
UniqueVol. 4 2-91MODEL-SPECIFIC REGISTERS (MSRS)
0 Enable PEBS on IA32_PMC0 (R/W)
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” Shared
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Shared
Register Address: 402H, 1026 IA32_MC0_ADDR
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.Shared
Register Address: 40CH, 1036 IA32_MC3_CTL
Register Address: 40EH, 1038 IA32_MC3_ADDR
Register Address: 412H, 1042 IA32_MC4_ADDRTable 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Unique2-92 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”Unique
See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”Unique
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2Table 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
UniqueVol. 4 2-93MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-5 lists model-specific registers (MSRs) that are specific to Intel Atom® processor with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_27H. Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
Table 2-5.  MSRs Supported by Intel Atom® Processors  with a CPUID Signature Di splayFamily_DisplayModel 
Value of 06_27H 
Register Information / Bit Fields Bit Description Scope
Register Address: 3F8H, 1016 MSR_PKG_C2_RESIDENCY
Package C2 Residency
Note: C-state values are proce ssor specific C-state code na mes, unrelated to MWAIT extension C-state parameters or 
ACPI C-States.PackageTable 2-4.  MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Unique2-94 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.4 MSRS IN INTEL PROCESSO RS BASED ON SILVERMONT 
MICROARCHITECTURE
Table 2-6 lists model-specific registers (MSRs) common to Intel processors based on the Silvermont microarchitec-
ture. These processors have a CPUID Signature Displa yFamily_DisplayModel value of 06_37H, 06_4AH, 06_4DH, 
06_5AH, or 06_5DH; see Table 2-1. The MSRs listed in Table 2-6 are also common to processors based on the 
Airmont microarchitecture and newer microarchitectures for next generation Intel Atom processors.
Table 2-7 lists MSRs common to processors based on the Silvermont and Airmont microarchitectures, but not 
newer microarchitectures.
Table 2-8, Table 2-9, and Table 2-10 lists MSRs that are mo del-specific across processors based on the Silvermont 
In the Silvermont microarchitecture, the scope column in dicates the following: “Core” means each processor core 
has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field 
is shared by a subset of the processor cores in the physic al package. The number of processor cores in this subset 
is model specific and may differ between different processo rs. For all processors based on Silvermont microarchi-
tecture, the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration can be used 
to figure out which processors are in the same module. “Package” means all processor cores in the physical 
package share the same MSR or bit interface.63:0 Package C2 Residency Counter (R/O)

Time that this package is in processor-specific C2 states since last reset. 
Counts at 1 Mhz frequency.Package
Register Address: 3F9H, 1017 MSR_PKG_C4_RESIDENCY
Package C4 Residency
Note: C-state values are proce ssor specific C-state code na mes, unrelated to MWAIT exte nsion C-state parameters or 
ACPI C-States.Package
63:0 Package C4 Residency Counter. (R/O)
Time that this package is in processor-specific C4 states since last reset. 
Register Address: 3FAH, 1018 MSR_PKG_C6_RESIDENCY
Package C6 Residency
63:0 Package C6 Residency Counter. (R/O)
Time that this package is in processor-specific C6 states since last reset. 
Table 2-6.   MSRs Common to Intel Atom® Proc essors (Silvermont and Ne wer Microarchitectures) 
See Section 2.23, “MSRs in Pentium Processors.” Module
Register Address: 1H, 1 IA32_P5_MC_TYPETable 2-5.  MSRs Supported by Intel Atom® Processors  (Contd.)with a CPUI D Signature DisplayF amily_DisplayModel 
Value of 06_27H  (Contd.)
Register Address: Hex, Decimal Reg ister Name (Former Register Name)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-95MODEL-SPECIFIC REGISTERS (MSRS)
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Core
See Section 18.17, “Time-Stamp Counter,” and Table 2-2. Core
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Core
Writes ignored.Module
63:0 Reserved.
Register Address: 34H, 52 MSR_SMI_COUNT
SMI Counter (R/O) Core
31:0 SMI Count (R/O) 
Running count of SMI events since last RESET.
See Table 2-2.Core
Register Address: E4H, 228 MSR_PMG_IO_CAPTURE_BASE
Power Management IO Redirection in C-state (R/W) 
See http://biosbits.org.Module
15:0 LVL_2 Base Address (R/W) 
Specifies the base address vi sible to software for IO redirection. If IO MWAIT 
Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port 
address redirection is enabled, this is the IO port address reported to the 
OS/software.Table 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Microarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description Scope2-96 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
18:16 C-state Range (R/W) 
Specifies the encoding value of the maximum C-State code name to be 
included when IO read to MW AIT redirection is enabled by 
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
100b - C4 is the max C-State to include110b - C6 is the max C-State to include
111b - C7 is the max C-State to include
63:19 Reserved.
Register Address: 13CH, 316 MSR_FEATURE_CONFIG
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.Core
1:0 AES Configuration (RW-L) 
Upon a successful read of this MSR, the configuration of AES instruction 
sets availability is as follows:
11b: AES instructions are not available until next RESET.Otherwise, AES instructions are available.
Note: AES instruction set is not available if read is unsuccessful. If the 
configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b.
See Table 2-2. Core
Global Machine Check Status CoreTable 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Micr oarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-97MODEL-SPECIFIC REGISTERS (MSRS)
0R I P V
pointer pushed on the stack (when the machine check was generated) can 
be used to restart the pr ogram. If cleared, the program cannot be reliably 
1E I P V
2M C I P
When set, bit indicates that a machine check has been generated. If a 
second machine check is de tected while this bit is still set, the processor 
enters a shutdown state. Software should write this  bit to 0 after 
processing a machine check exception.
7:0 Event Select
15:8 UMask
16 USR17 OS
18 Edge
19 PC20 INT
22 EN23 INV
31:24 CMASK
See Table 2-2. Module
IA32_CLOCK_MODULATION MSR was origin ally named IA32_THERM_CONTROL MSR.Core
Register Address: 19BH, 411 IA32_THERM_INTERRUPTTable 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Microarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description Scope2-98 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target Package
15:0 Reserved.
23:16 Temperature Target (R) 
The default thermal throttling or PR OCHOT# activation temperature in 
degrees C. The effective temperature for thermal throttling or PROCHOT# 
activation is “Temperature  Target” + “Target Offset”.
29:24 Target Offset (R/W) 
Specifies an offset in degrees C to adjust the throttling and PROCHOT# 
activation temperature from th e default target specified in 
TEMPERATURE_TARGET (bits 23:16).
63:30 Reserved.
Register Address: 1A6H, 422 MSR_OFFCORE_RSP_0
Offcore Response Event Sele ct Register (R/W) Module
Register Address: 1A7H, 423 MSR_OFFCORE_RSP_1
Register Address: 1B0H, 432 IA32_ENERGY_PERF_BIAS
generated or the last in terrupt that was handled.Core
exception that was generated or the last interrupt th at was handled. Core
See Table 2-2. CoreTable 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Micr oarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-99MODEL-SPECIFIC REGISTERS (MSRS)

Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000Table 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Microarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description Scope2-100 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Core
See Table 2-2. See Section 20.6.2.2, “G lobal Counter Control Facilities.” Core
Register Address: 3FDH, 1021 MSR_CORE_C6_RESIDENCYTable 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Micr oarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-101MODEL-SPECIFIC REGISTERS (MSRS)
ACPI C-States.Core
63:0 CORE C6 Residency Counter (R/O)
Value since last reset that  this core is in proces sor-specific C6 states. 
Counts at the TSC Frequency.
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” Module
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Module
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.Module
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” CoreTable 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Microarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description Scope2-102 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 412H, 1042 IA32_MC4_ADDR
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Package
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.Package
See Appendix A.1, “Basic VMX Information.”Core
See Appendix A.3, “VM-Execution Controls.”Core
See Table 2-2.See Appendix A.4, “VM-Exit Controls.”Core
See Table 2-2.See Appendix A.5, “VM-Entry Controls.”Core
See Table 2-2.See Appendix A.6, “Miscellaneous Data.”Core
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0Table 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Micr oarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-103MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2.See Appendix A.7, “VMX -Fixed Bits  in CR0.”Core
See Appendix A.8, “VMX -Fixed Bits  in CR4.”Core
See Appendix A.9, “VMCS Enumeration.”Core
Register Address: 48CH, 1164 IA32_VMX_EPT_VPID_ENUM
Capability Reporting Register of EPT and VPID (R/O) 
Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)

Capability Reporting Register of Primary Proc essor-based VM-Execution Flex Controls (R/O)
Register Address: 491H, 1169 IA32_VMX_FMFUNC
Capability Reporting Register of VM-Function Controls (R/O)
See Table 2-2.CoreTable 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Microarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description Scope2-104 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”Core
Register Address: 660H, 1632 MSR_CORE_C1_RESIDENCY
63:0 CORE C1 Residency Counter. (R/O)
Value since last reset that  this core is in processor-specific C1 states. 
Counts at the TSC frequency.
TSC Target of Local APIC’s TSC Deadline Mode (R/W) 
Register Address: C000_0103H IA32_TSC_AUXTable 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Micr oarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-105MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-7 lists model-specific registers (MSRs) that are common to Intel Atom® processors based on the Silver-
mont and Airmont microarchitectures but not newer microarchitectures.AUXILIARY TSC Signature (R/W) 
Table 2-7.  MSRs Common to the Silver mont and Airmont Microarchitectures 
Model Specific Platform ID (R) Module
7:0 Reserved.13:8 Maximum Qualified Ratio (R) 
49:13 Reserved.52:50 See Table 2-2.
0L o c k  ( R / W L )  
2 Enable VMX outside SMX operation (R/WL) 
• Section 18.5 and record format in Section 18.4.8.1.Core
See description of MSR_LASTBRANCH_0_FROM_IP.Core
See description of MSR_LASTBRANCH_0_FROM_IP. Core
See description of MSR_LASTBRANCH_0_FROM_IP.CoreTable 2-6.   MSRs Common to Intel Atom® Processors  (Silvermont and Newer Microarchitectures)  (Contd.)
Register Information / Bit Fields Bit Description Scope2-106 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record  0 To IP (R/W)
One of eight pairs of last branch record registers on the last branch  record stack. The To_IP pa rt of the stack contains 
pointers to the destination instruction.Core
Last Branch Record  1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP. Core
Last Branch Record  2 To IP (R/W)
Last Branch Record  3 To IP (R/W)
Last Branch Record  4 To IP (R/W)
Register Address: 65H, 101 MSR_LASTBRANCH_5_TO_IP
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information: Contains power management and other model specific features enumeration. See 
http://biosbits.org.Package
7:0 Reserved.Table 2-7.  MSRs Common to the Silvermont  and Airmont Microarchitectures  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-107MODEL-SPECIFIC REGISTERS (MSRS)
15:8 Maximum Non-Turbo Ratio (R/O) 
This is the ratio of the maximum freq uency that does not require turbo. 
Frequency = ratio * Scalable Bus Frequency.Package
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W) 
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or 
ACPI C-States.
2:0 Package C-State Limit (R/W) 
Specifies the lowest processor-specific C-state code name (consuming the 
least power) for the package. The de fault is set as factory-configured 
package C-state limit.
The following C-state code name encodings are supported:
000b: C0 (no package C-sate support)001b: C1 (Behavior is the same as 000b)
100b: C4
110b: C6111b: C7 (Silvermont only)
9:3 Reserved.10 I/O MWAIT Redirect ion Enable (R/W) 
When set, will map IO_read instructions  sent to IO register specified by 
MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11 Reserved.15 CFG Lock (R/WO) 
When set, locks bits 15:0 of this regist er until next reset.
Used to configure the L2 Cache.Module
1 = If the L2 is hardware-enabled.
0 = Indicates if the L2 is hardware-disabled.
Until this bit is set the processor will not respond to the WBINVD instruction 
22:9 Reserved.Table 2-7.  MSRs Common to the Silvermont  and Airmont Microarchitectures  (Contd.)
Register Information / Bit Fields Bit Description Scope2-108 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
23 L2 Not Present (R/O) 
Enable Misc. Proce ssor Features (R/W) 
See Table 2-2. Default value is 0.Module
10:8 Reserved.
11 Branch Trace Storage Unavailable (R/O) 
See Table 2-2.Module

See Table 2-3.Core
37:35 Reserved.Table 2-7.  MSRs Common to the Silvermont  and Airmont Microarchitectures  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-109MODEL-SPECIFIC REGISTERS (MSRS)
38 Turbo Mode Disable (R/W)
When set to 1 on processors that su pport Intel Turbo B oost Technology, the 
turbo mode feature is disabled and the IDA_Enable feature flag will be 
cleared (CPUID.06H: EAX[1]=0).
the processor’s support of turbo mode is enabled.
Note: The power-on default value is used by BIOS to detect hardware 
support of turbo mo de. If the power-on default value is 1, turbo mode is 
available in the processor. If the power-on default value is 0, turbo mode is 
not available.Module
63:39 Reserved.
Register Address: 1C8H, 456 MSR_LBR_SELECT
Last Branch Record Filter ing Select Register (R/W) 
See Section 18.9.2, “Filtering of Last Branch Records.”Core
0C P L _ E Q _ 0
1 CPL_NEQ_0
2J C C
3 NEAR_REL_CALL4 NEAR_IND_CALL
5 NEAR_RET
6N E A R _ I N D _ J M P7 NEAR_REL_JMP
8 FAR_BRANCH
63:9 Reserved.
See MSR_LASTBRANCH_0_FROM_IP.Core
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Core
See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Core0 Enable PEBS for precise event on IA32_PMC0 (R/W)
63:0 Package C6 Residency Counter (R/O)
Value since last reset that  this package is in proc essor-specific C6 states. 
Counts at the TSC Frequency.Table 2-7.  MSRs Common to the Silvermont  and Airmont Microarchitectures  (Contd.)
Register Information / Bit Fields Bit Description Scope2-110 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.4.1  MSRs with Model-Specific Behavi or in the Silvermont Microarchitecture
Table 2-8 lists MSRs that are specific to the Intel Atom® processor E3000 Series (CPUID Signature 
DisplayFamily_DisplayModel value of 06_37H) an d Intel Atom processors (CPUID Signature 
DisplayFamily_DisplayModel value of 06_4AH, 06_5AH, or 06_5DH). Register Address: 664H, 1636 MSR_MC6_RESIDENCY_COUNTER
Module C6 Residency Counter (R/0) 
Note: C-state values are processor specif ic C-state code names, unrelated to MWAIT extension C-state parameters or 
ACPI C-States.Module
63:0 Time that this module is in module-specific C6 states since last reset. Counts 
at 1 Mhz frequency.
Table 2-8.  Specific MSRs Supported by Intel Atom® Proc essors with a CPUID Signatur e DisplayFamily_DisplayModel 
Value of 06_37H, 06_4AH, 06_5AH, or 06_5DH 
This field indicates the intended scalable bus clock speed for processors based on Silvermont microarchitecture.Module
2:0 • 100B: 080.0 MHz 
• 000B: 083.3 MHz 
• 001B: 100.0 MHz • 010B: 133.3 MHz 
• 011B: 116.7 MHz 
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers used in RAPL Interfaces (R/O) 
See Section 15.10.1, “RAPL Interfaces.”Package
3:0 Power Units
Power related information (in milliWatts) is based on the multiplier,   2^PU; 
where PU is an unsigned integer repres ented by bits 3:0.  Default value is 
0101b, indicating power unit is in 32 milliWatts increment.
7:4 Reserved.12:8 Energy Status Units
Energy related information (in microJoules) is based on the multiplier, 2^ESU; 
where ESU is an unsigned integer represented by bits 12:8. Default value is 
00101b, indicating energy unit is in 32 microJoules increment.
19:16 Time Unit
The value is 0000b, indicating  time unit is in one second.
63:20 Reserved.
Register Address: 610H, 1552 MSR_PKG_POWER_LIMIT
PKG RAPL Power Limit Control (R/W) PackageTable 2-7.  MSRs Common to the Silvermont  and Airmont Microarchitectures  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-111MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-9 lists model-specific registers (MSRs) that are specific to the Intel Atom® processor E3000 Series (CPUID 
Signature DisplayFamily_DisplayModel value of 06_37H).14:0 Package Power Limit #1 (R/W)
See Section 15.10.3, “Package RAPL Domain,” and MSR_RAPL_POWER_UNIT 
in Table 2-8. 
15 Enable Power Limit #1 (R/W)
See Section 15.10.3, “Package RAPL Domain.”
16 Package Clamping Limitation #1 (R/W)
23:17 Time Window for Power Limit #1 (R/W)
In unit of second. If 0 is specified in  bits [23:17], defa ults to 1 second 
window.
Register Address: 611H, 1553 MSR_PKG_ENERGY_STATUS
PKG Energy Status (R/O) 
See Section 15.10.3, “Package RAPL Domain ,” and MSR_RAPL_POWER_UNIT in Table 2-8.Package
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O) 
See Section 15.10.4, “PP0/PP1 RAPL Domain s,” and MSR_RAPL_POWER_UNIT in Table 2-8.Package
Table 2-9.  Specific MSRs Suppor ted by the Intel Atom® Processor E3000 Series with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_37H
Register Address: 668H, 1640 MSR_CC6_DEMOTION_POLICY_CONFIG
Core C6 Demotion Policy Config MSR Package
63:0 Controls per-core C6 demotion policy. Writing a value of 0 disables core 
level HW demo tion policy.
Register Address: 669H, 1641 MSR_MC6_DEMOTION_POLICY_CONFIG
Module C6 Demotion Policy Config MSR Package
63:0 Controls module (i.e., two cores sharing the second-level cache) C6 
demotion policy. Writing a value of 0 disables module level HW demotion 
policy.
Register Address: 664H, 1636 MSR_MC6_RESIDENCY_COUNTER
63:0 Time that this module is in module -specific C6 states since last reset. 
Counts at 1 Mhz frequency.Table 2-8.  Specific MSRs Supported by Intel Atom® Proc essors with a CPUI D Signature DisplayF amily_DisplayModel 
Value of 06_37H, 06_4AH, 06_5AH, or 06_5DH  (Contd.)
Register Information / Bit Fields Bit Description Scope2-112 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-10 lists model-specific registers (MSRs) that are specific to Intel Atom® processor C2000 Series (CPUID 
Signature DisplayFamily_Displ ayModel value of 06_4DH). 
Table 2-10.  Specific MSRs Supported by Intel At om® Processor C2000 Series  with a CPUID Signature 
DisplayFamily_DisplayMod el Value of 06_4DH 
Register Address: 1A4H, 420 MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W) 
0 L2 Hardware Prefetcher Disable (R/W) 
If 1, disables the L2 hardware prefetcher, which fetches additional lines of 
code or data in to the L2 cache.Core
2 DCU Hardware Prefetcher Disable (R/W) 
If 1, disables the L1 data cache prefetcher, which fetches the next cache 
line into L1 data cache.Core
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode (R/W) Package
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active. Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active. Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.Package
39:32 Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.Package
47:40 Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.Package
55:48 Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 core active.Package
63:56 Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 core active.Package

Power related information (i n milliWatts) is based on the multiplier,   2^PU; 
7:4 Reserved.Vol. 4 2-113MODEL-SPECIFIC REGISTERS (MSRS)
2.4.2  MSRs in Intel Atom® Processo rs Based on Airmont Microarchitecture
Intel Atom processor X7-Z8000 and X5-Z8000 series are ba sed on the Airmont microarchitecture. These proces-
sors support MSRs listed in Table 2-6, Table 2-7, Tabl e 2-8, and Table 2-11. These processors have a CPUID 
Signature DisplayFamily_DisplayMode l value of 06_4CH; see Table 2-1. 12:8 Energy Status Units. 
Energy related information (in microJoules) is based on the multiplier, 
2^ESU; where ESU is an unsigned integer represented by bits 12:8. 
Default value is 00101b, indicating energy unit is in  32 microJoules 
The value is 0000b, indicating time unit is in one second.
PKG RAPL Power Limit Control (R/W) 
See Section 15.10.3, “Package RAPL Domain.”Package
Register Address: 66EH, 1646 MSR_PKG_POWER_INFO
PKG RAPL Parameter (R/0) Package
14:0 Thermal Spec Power (R/0)
The unsigned integer value is the equivalent of the thermal specification 
power of the package domain. The unit of this field is specified by the “Power Units” field of MSR_RAPL_POWER_UNIT.
63:15 Reserved.
Table 2-11.   MSRs in Intel Atom® Proces sors Based on Airmont Microarchitecture
This field indicates the intended sc alable bus clock speed for processors based on Airmont microarchitecture.Module
3:0 • 0000B: 083.3 MHz 
• 0001B: 100.0 MHz 
• 0010B: 133.3 MHz 
• 0011B: 116.7 MHz • 0100B: 080.0 MHz 
• 0101B: 093.3 MHz 
• 0110B: 090.0 MHz • 0111B: 088.9 MHz 
• 1000B: 087.5 MHz 
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROLTable 2-10.  Specific MSRs Supported by Intel At om® Processor C2000 Series  with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_4DH  (Contd.)
Register Information / Bit Fields Bit Description Scope2-114 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Specifies the lowest proc essor-specific C-state co de name (consuming the 
least power) for the package. The de fault is set as fa ctory-configured 
000b: No limit001b: C1 
010b: C2 
110b: C6
111b: C7 
10 I/O MWAIT Redirect ion Enable (R/W) 
14:11 Reserved.
15 CFG Lock (R/WO) 
When set, locks bits 15:0 of th is register until next reset.
Specifies the base address visible to software for IO redirection. If IO 
MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO 
port address redirection is enabled, this is the IO port address reported to 
the OS/software.
included when IO read to MWAIT redirection is enabled by 
000b - C3 is the max C-State to include.001b - Deep Power Down Tech nology is the max C-State.
010b - C7 is the max C-State to include.
Register Address: 638H, 1592 MSR_PP0_POWER_LIMIT
PP0 RAPL Power Limit Control (R/W) PackageTable 2-11.   MSRs in Intel Atom® Processors  Based on Airmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-115MODEL-SPECIFIC REGISTERS (MSRS)
2.5 MSRS IN INTEL ATOM® PROC ESSORS BASED ON GOLDMONT 
Intel Atom processors based on the Goldmont microarchitecture support MSRs listed in Table 2-6 and Table 2-12. 
These processors have a CPUID Signature DisplayFam ily_DisplayModel value of 06_5CH; see Table 2-1. 
In the Goldmont microarchitecture, the scope column in dicates the following: “Core” means each processor core 
has a separate MSR, or a bit field not shared with anothe r processor core. “Module” means the MSR or the bit field 
is model specific and may differ betw een different processors. For all processors based on Goldmont microarchitec-
ture, the L2 cache is also shared between cores in a modu le and thus CPUID leaf 04H enumeration can be used to 
figure out which processors are in the same module. “Pac kage” means all processor cores in the physical package 
share the same MSR or bit interface.14:0 PP0 Power Limit #1 (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains,” and 
MSR_RAPL_POWER_UNIT in Table 2-8. 
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
16 Reserved.23:17 Time Window for Power Limit #1 (R/W)
Specifies the time durati on over which the average power must remain 
below PP0_POWER_LIMIT #1(14:0). Supported Encodings:
0x0: 1 second time duration.
0x1: 5 second time duration (Default).
0x2: 10 second time duration.
0x3: 15 second time duration.0x4: 20 second time duration.
0x5: 25 second time duration.
0x6: 30 second time duration.0x7: 35 second time duration.
0x8: 40 second time duration.
0x9: 45 second time duration.0xA: 50 second time duration.
0xB-0x7F - reserved.
Table 2-12.   MSRs in Intel Atom® Proces sors Based on Goldmont Microarchitecture
52:50 See Table 2-2.Table 2-11.   MSRs in Intel Atom® Processors Based on Airmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-116 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
1 Enable VMX inside SMX operation (R/WL) 
14:8 SENTER local func tions enables (R/WL) 
15 SENTER global functions enable (R/WL) 18 SGX global functions enable (R/WL) 
Per-Core TSC ADJUST (R/W)
Register Address: C3H, 195 IA32_PMC2
Register Address: C4H, 196 IA32_PMC3
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.Package
Frequency = ratio * 100 MHz.Package
27:16 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O) 
When set to 1, indicate s that Programmable Ratio Limit for Turbo mode is 
enabled. When set to 0, indicate s Programmable Ratio Limit for Turbo 
mode is disabled.Package
29 Programmable TDP Limit for Turbo Mode (R/O) 
When set to 1, indicates that TDP Li mit for Turbo mode is programmable. 
When set to 0, indicates TDP Limit for Turbo mode is not programmable.Package
30 Programmable TJ OFFSET (R/O) 
When set to 1, indicates that MS R_TEMPERATURE_TARGET.[27:24] is 
valid and writable to specify a temperature offset.Package
39:31 Reserved.Table 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-117MODEL-SPECIFIC REGISTERS (MSRS)
47:40 Maximum Efficiency Ratio (R/O) 
This is the minimum ratio (maximum efficiency) that the processor can 
operate, in units of 100MHz.Package
63:48 Reserved.
C-State Configuration Control (R/W)

Note: C-state values are proce ssor specific C-state code names, unrelated to MWAIT extension C- state parameters or 
See http://biosbits.org.Core
3:0 Package C-State Limit (R/W) 
Specifies the lowest processor-specific  C-state code name (consuming the 
0000b: No limit0001b: C1 
0010b: C3 
0011b: C60100b: C7
0101b: C7S
0110b: C80111b: C9
1000b: C10 
Register Address: 17DH, 381 MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability enhancement. Accessible only while in SMM.Core
57:0 Reserved.
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM co de access restrictio n is supported and 
the MSR_SMM_FEATURE_CONTROL is supported.
59 Long_Flow_Indication (SMM-RO)
If set to 1 indicates that  the SMM long flow indica tor is supported and the 
MSR_SMM_DELAYED is supported.
63:60 Reserved.Table 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-118 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 188H, 392 IA32_PERFEVTSEL2
See Table 2-2. Default value is 1.Package
See Table 2-2.Package
37:35 Reserved.Table 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-119MODEL-SPECIFIC REGISTERS (MSRS)
When set to 1 on processors that support Intel Turbo Boost Technology, 
the turbo mode feature is disabled and the IDA_Enable feature flag will be 
clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors th at support IDA, CPUID.06H: EAX[1] 
reports the processo r’s support of turbo mode is enabled.
available in the processor. If the power-on default value is 0, turbo mode 
is not available.Package
Miscellaneous Feature Control (R/W) 0 L2 Hardware Prefetcher Disable (R/W) 
code or data into the L2 cache.Core
Register Address: 1AAH, 426 MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control
Various model specific features en umeration. See h ttp://biosbits.org.Package
0 EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced Intel Speedstep 
Technology request from processor co res. When 1, disables hardware 
coordination of Enhanced Intel Speedstep Technology requests.
21:1 Reserved.22 Thermal Interrupt Coordination Enable (R/W) 
If set, then thermal interrupt on one core is routed to all cores.
Maximum Ratio Limit of Turbo Mode by Core Groups (R/W)
Specifies Maximum Ratio Limit for each Core Group. Max ratio for groups with more cores must decrease 
monotonically.
For groups with less than 4 cores, the max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must be 
22 or less. For groups with more than 5 cores, the max ratio must be 16 or less.Package
7:0 Maximum Ratio Limit for Active Cores in Group 0
Maximum turbo ratio limit wh en the number of active cores is less than or 
equal to the Group 0 threshold. PackageTable 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-120 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
15:8 Maximum Ratio Limit for Active Cores in Group 1
Maximum turbo ratio limit when the number  of active cores is less than or 
equal to the Group 1 threshold, and greater than the Group 0 threshold. Package
23:16 Maximum Ratio Limit fo r Active Cores in Group 2
equal to the Group 2 threshold, and greater than the Group 1 threshold. Package
31:24 Maximum Ratio Limit fo r Active Cores in Group 3
equal to the Group 3 threshold, and greater than the Group 2 threshold. Package
39:32 Maximum Ratio Limit fo r Active Cores in Group 4
equal to the Group 4 threshold, and greater than the Group 3 threshold. Package
47:40 Maximum Ratio Limit fo r Active Cores in Group 5
equal to the Group 5 threshold, and greater than the Group 4 threshold. Package
55:48 Maximum Ratio Limit fo r Active Cores in Group 6
equal to the Group 6 threshold, and greater than the Group 5 threshold. Package
63:56 Maximum Ratio Limit fo r Active Cores in Group 7
equal to the Group 7 threshold, and greater than the Group 6 threshold. Package
Register Address: 1AEH, 430 MSR_TURBO_GROUP_CORECNT
Group Size of Active Cores fo r Turbo Mode Operation (R/W)
Writes of 0 threshold is ignored.Package
7:0 Group 0 Core Count Threshold
Maximum number of active cores to operate under the Group 0 Max Turbo 
Ratio limit. Package
15:8 Group 1 Core Count Threshold
Maximum number of active cores to operate under the Group 1 Max Turbo 
Ratio limit. Must be greater than the Group 0 Core Count.Package
23:16 Group 2 Core Count Threshold
Maximum number of active cores to operate under the Group 2 Max Turbo 
Ratio limit. Must be greater than the Group 1 Core Count.Package
31:24 Group 3 Core Count Threshold
Maximum number of active cores to operate under the Group 3 Max Turbo 
Ratio limit. Must be greater than the Group 2 Core Count.Package
39:32 Group 4 Core Count Threshold
Maximum number of active cores to operate under the Group 4 Max Turbo 
Ratio limit. Must be greater than the Group 3 Core Count.Package
47:40 Group 5 Core Count Threshold
Maximum number of active cores to operate under the Group 5 Max Turbo 
Ratio limit. Must be greater than the Group 4 Core Count.PackageTable 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-121MODEL-SPECIFIC REGISTERS (MSRS)
55:48 Group 6 Core Count Threshold
Maximum number of active cores to operate under the Group 6 Max Turbo 
Ratio limit. Must be  greater than the Group 5 Core Count.Package
63:56 Group 7 Core Count Threshold
Maximum number of active cores to operate under the Group 7 Max Turbo 
Ratio limit. Must be grea ter than the Group 6 Core  Count, and not less than 
the total number of processor cores in the package. E.g., specify 255.Package
0C P L _ E Q _ 0
2J C C3 NEAR_REL_CALL
4 NEAR_IND_CALL
5 NEAR_RET6N E A R _ I N D _ J M P
7 NEAR_REL_JMP
8 FAR_BRANCH9 EN_CALL_STACK
63:10 Reserved.
Contains an index (bits 0-4) that  points to the MSR co ntaining the most recent branch record.

0C P L _ E Q _ 0
Register Address: 1FCH, 508 MSR_POWER_CTL
Power Control Register
1 C1E Enable (R/W) 
When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced 
Intel SpeedStep Technology operating point when all execution cores enter MWAIT (C1).Package
See Table 2-2. CoreTable 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-122 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: IA32_MTRR_PHYSMASK9
213H, 531 See Table 2-2. Core
Register Address: IA32_MC0_CTL2
280H, 640 See Table 2-2. Module
Register Address: IA32_MC1_CTL2
281H, 641 See Table 2-2. Module
Register Address: IA32_MC2_CTL2
282H, 642 See Table 2-2. Core
See Table 2-2. Package
Register Address: 300H, 768 MSR_SGXOWNEREPOCH0
Lower 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package.Package
63:0 Lower 64 bits of an 128-bit extern al entropy value for key derivation of 
an enclave.
Register Address: 301H, 769 MSR_SGXOWNEREPOCH1
Upper 64 Bit CR_SGXOWNEREPOCH (W)
63:0 Upper 64 bits of an 128-bit extern al entropy value for key derivation of 
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.” Core
0O v f _ P M C 0  
1O v f _ P M C 1  2O v f _ P M C 2  
3O v f _ P M C 3  
31:4 Reserved.32 Ovf_FixedCtr0 
33 Ovf_FixedCtr1 
34 Ovf_FixedCtr2 54:35 Reserved.
55 Trace_ToPA_PMITable 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-123MODEL-SPECIFIC REGISTERS (MSRS)
58 LBR_Frz
59 CTR_Frz60 ASCI
61 Ovf_Uncore 
62 Ovf_BufDSSAVE 63 CondChgd 
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.” Core0 Set 1 to clear Ovf_PMC0.1 Set 1 to clear Ovf_PMC1.
2 Set 1 to clear Ovf_PMC2.
3 Set 1 to clear Ovf_PMC3.31:4 Reserved.
32 Set 1 to clear Ovf_FixedCtr0.
33 Set 1 to clear Ovf_FixedCtr1.34 Set 1 to clear Ovf_FixedCtr2.
55 Set 1 to clear Trace_ToPA_PMI. 57:56 Reserved.
58 Set 1 to clear LBR_Frz. 
59 Set 1 to clear CTR_Frz. 60 Set 1 to clear ASCI. 
61 Set 1 to clear Ovf_Uncore.
62 Set 1 to clear Ovf_BufDSSAVE.63 Set 1 to clear CondChgd.
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.” Core0 Set 1 to cause Ovf_PMC0 = 1.
1 Set 1 to cause Ovf_PMC1 = 1.
2 Set 1 to cause Ovf_PMC2 = 1.3 Set 1 to cause Ovf_PMC3 = 1.
31:4 Reserved.
32 Set 1 to cause Ovf_FixedCtr0 = 1.33 Set 1 to cause Ovf_FixedCtr1 = 1.
34 Set 1 to cause Ovf_FixedCtr2 = 1.
54:35 Reserved.Table 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-124 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
55 Set 1 to cause Trace_ToPA_PMI = 1.
58 Set 1 to cause LBR_Frz = 1.59 Set 1 to cause CTR_Frz = 1.
60 Set 1 to cause ASCI = 1.
61 Set 1 to cause Ovf_Uncore.62 Set 1 to cause Ovf_BufDSSAVE.
63 Reserved.
See Table 2-2 and Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Core
0 Enable PEBS trigger and recording fo r the programmed event (precise or 
otherwise) on IA32_PMC0. (R/W)
Register Address: 3F8H, 1016 MSR_PKG_C3_RESIDENCY
63:0 Package C3 Residency Counter (R/O)
Value since last reset that  this package is in processor-specific C3 states. 
Count at the same frequency as the TSC.
Register Address: 3F9H, 1017 MSR_PKG_C6_RESIDENCY
Value since last reset that  this package is in processor-specific C6 states. 
Register Address: 3FCH, 1020 MSR_CORE_C3_RESIDENCY
63:0 CORE C3 Residency Counter (R/O)
Value since last reset that  this core is in processor-specific C3 states. 
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. PackageTable 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-125MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 4E0H, 1248 MSR_SMM_FEATURE_CONTROL
Enhanced SMM Feature Control (SMM-RW)
Reports SMM capability Enhancement. Accessible only while in SMM.Package
0L o c k  ( S M M - R W O )
When set to ‘1’ locks this re gister from further changes.
2 SMM_Code_Chk_En (SMM-RW)
This control bit is available only if MSR_SMM_MCA_CAP[58] == 1. When 
set to ‘0’ (default) none of the logical processors are prevented from executing SMM code outside the ranges defined by the SMRR. 
When set to ‘1’ any logical processo r in the package that attempts to 
execute SMM code not with in the ranges defined by the SMRR will assert 
an unrecoverable MCE.
Register Address: 4E2H, 1250 MSR_SMM_DELAYED
SMM Delayed (SMM-RO)
Reports the interruptible state of all logical processors in the package. Available only while in SMM and 
MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.Package
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its state in a long flow of internal 
operation which delays servicing an interrupt. The corresponding bit will 
be set at the start of long events such as: Microcode Update Load, C6, 
WBINVD, Ratio Change, Throttle. 
The bit is automatically cleared at the end of each long event. The reset 
value of this field is 0.
Only bit positions below N = CPUID. (EAX=0BH, ECX=PKG_LVL):EBX[15:0] 
can be updated.
63:N Reserved.
Register Address: 4E3H, 1251 MSR_SMM_BLOCKED
SMM Blocked (SMM-RO)
Reports the blocked state of all logical processors in the package. Available only while in SMM.PackageTable 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-126 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Each bit represents a processor core of  its blocked state to service an SMI. 
The corresponding bit will be set if the logical processor is in one of the 
following states: Wait For SIPI or SENTER Sleep. 
The reset value of this field is 0FFFH.Only bit positions below N = CPUI D.(EAX=0BH, ECX=PKG_ LVL):EBX[15:0] 
Status and SVN Threshold of SGX Support for ACM (R/O) Core0L o c k
See Section 39.11.3, “Interactions with Authenticate d Code Modules 
(ACMs).”
15:1 Reserved.23:16 SGX_SVN_SINIT
(ACMs).”
Register Address: 560H, 1376 IA32_RTIT_OUTPUT_BASE
Trace Output Base  Register (R/W)

(ACMs).”
(ACMs).”
Register Address: 561H, 1377 IA32_RTIT_OUTPU T_MASK_PTRS
Trace Output Mask Poin ters Register (R/W) 
Trace Control Register (R/W) Core
0T r a c e E n
1 CYCEn2O S
3U s e r
6:4 Reserved, must be zero.7C R 3 F i l t e r
8T o P A
Writing 0 will #GP if also setting TraceEn.
9M T C E n
10 TSCEn11 DisRETC
12 Reserved, must be zero.
13 BranchEn17:14 MTCFreqTable 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-127MODEL-SPECIFIC REGISTERS (MSRS)
22:19 CycThresh
23 Reserved, must be zero.27:24 PSBFreq
31:28 Reserved, must be zero.
35:32 ADDR0_CFG39:36 ADDR1_CFG
63:40 Reserved, must be zero.
Tracing Status Register (R/W) Core
0F i l t e r E n
Writes ignored.
1C o n t e x E n
2 TriggerEn
3 Reserved
4E r r o r  ( R / W )
5S t o p p e d31:6 Reserved, must be zero.
48:32 PacketByteCnt
63:49 Reserved, must be zero.
Trace Filter CR3 Match Register (R/W) Core
4:0 Reserved63:5 CR3[63:5] value to match.
Region 0 Start Address (R/W) Core
63:0 See Table 2-2. 
Region 0 End Address (R/W) Core
Region 1 Start Address (R/W) Core
Region 1 End Address (R/W) Core
63:0 See Table 2-2. Table 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-128 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Power related information (in Watts) is in unit of 1W/2^PU; where PU is an 
unsigned integer represented by bi ts 3:0. Default value is 1000b, 
indicating power unit is in  3.9 milliWatts increment.
Energy related information (in Joules) is  in unit of 1Joule/ (2^ESU); where 
ESU is an unsigned integer represented by bits 12:8. Default value is 
01110b, indicating energy unit is in 61 microJoules.
Time related information (in seconds) is in unit of 1S/2^TU; where TU is an 
unsigned integer represented by bits 19:16. Default value is 1010b, indicating power unit is in 0.977 millisecond.
Register Address: 60AH, 1546 MSR_PKGC3_IRTL
Package C3 Interrupt Response Limit (R/W) 
9:0 Interrupt Response Time Limit (R/W) 
Specifies the limit that sh ould be used to decide if the package should be 
put into a package C3 state. 
12:10 Time Unit (R/W) 
Specifies the encoding value of time unit of the interru pt response time 
limit. See Table 2-20 for supported time unit encodings. 
14:13 Reserved.
15 Valid (R/W) 
Indicates whether the values in bits 12:0 are valid and can be used by the 
processor for package C-sate management. 
Register Address: 60BH, 1547 MSR_PKGC_IRTL1
Package C6/C7S Interrupt Response Limit 1 (R/W) 
This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or 
C7S state. 
ACPI C-states.Package
put into a package C6 or C7S state. Table 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-129MODEL-SPECIFIC REGISTERS (MSRS)
Specifies the encoding value of time unit of the interrupt response time 
limit. See Table 2-20 for supported time unit encodings.
14:13 Reserved.15 Valid (R/W) 
Register Address: 60CH, 1548 MSR_PKGC_IRTL2
Package C7 Interrupt Re sponse Limit 2 (R/W) 
This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C7 
state. 
put into a package C7 state. 
Register Address: 60DH, 1549 MSR_PKG_C2_RESIDENCY
63:0 Package C2 Residency Counter (R/O)
Value since last reset that  this package is in proc essor-specific C2 states. 
Register Address: 613H, 1555 MSR_PKG_PERF_STATUS
PKG Perf Status (R/O) 
Register Address: 614H, 1556 MSR_PKG_POWER_INFO
PKG RAPL Parameters (R/W) PackageTable 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-130 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
14:0 Thermal Spec Power (R/W) 
30:16 Minimum Power (R/W) 
31 Reserved.
46:32 Maximum Power (R/W) 
47 Reserved.54:48 Maximum Time Window (R/W) 
Specified by 2^Y * (1.0 + Z/4.0) * Time_Unit, where “Y” is the unsigned 
integer value represented by bits 52:48, “Z” is an unsigned integer 
represented by bits 54:53. “Time_Unit” is specified by the “Time Units” field of MSR_RAPL_POWER_UNIT.
63:55 Reserved.
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W) 
See Section 15.10.5, “DRAM RAPL Domain.”Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O) 
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O) 
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W) 
Register Address: 632H, 1586 MSR_PKG_C10_RESIDENCY
63:0 Package C10 Resi dency Counter (R/O)
Value since last reset that the entire SOC is in an S0i3 state. Count at the 
same frequency as the TSC.
See Section 15.10.4, “PP0/PP1 RAPL Domains.”Package
Register Address: 641H, 1601 MSR_PP1_ENERGY_STATUS
PP1 Energy Status (R/O) 
Register Address: 64CH, 1612 MSR_TURBO_ACTIVATION_RATIOTable 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-131MODEL-SPECIFIC REGISTERS (MSRS)
ConfigTDP Control (R/W) Package
7:0 MAX_NON_TURBO _RATIO (RW/L)
System BIOS can program this field. 
31 TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of th is register is locked until a reset. 
Register Address: 64FH, 1615 MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
(Frequency refers to processor core frequency.)Package
0P R O C H O T  S t a t u s  ( R 0 )
When set, processor core frequency is reduced below the operating 
system request due to assertion of external PROCHOT.

1 Thermal Status (R0)
When set, frequency is reduced below the operating system request due 
to a thermal event.
2 Package-Level Power Limiting PL1 Status (R0)
to package-level po wer limiting PL1.
3 Package-Level PL2 Power Limiting Status (R0)
to package-level po wer limiting PL2.
8:4 Reserved.9 Core Power Limiting Status (R0)
to domain-level power limiting.
10 VR Therm Alert Status (R0)
to a thermal alert from  the Voltage Regulator.
11 Max Turbo Limit Status (R0)
to multi-core turbo limits.
12 Electrical Design Point Status (R0)
to electrical design po int constraints (e.g., maximum electrical current 
consumption).
13 Turbo Transition Attenuation Status (R0)
to Turbo transition atte nuation. This prevents performance degradation 
due to frequent operating ratio changes.
14 Maximum Efficiency Frequency Status (R0)
When set, frequency is reduced below the maximum efficiency frequency.
15 Reserved.Table 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-132 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
16 PROCHOT Log 
When set, indicates that the PROCHOT Status bit has asserted since the 
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log 
When set, indicates that the Thermal Status bit has asserted since the log 
bit was last cleared.
18 Package-Level PL1 Power Limiting Log 
When set, indicates that  the Package Level PL1 Power Limiting Status bit 
has asserted since the lo g bit was last cleared.
19 Package-Level PL2 Power Limiting Log
When set, indicates that  the Package Level PL2 Power Limiting Status bit 
24:20 Reserved.
25 Core Power Limiting Log 
When set, indicates that the Core Power Limiting Status bit has asserted 
since the log bit was last cleared.
26 VR Therm Alert Log 
When set, indicates that the VR Ther m Alert Status bit has asserted since 
the log bit was last cleared.
27 Max Turbo Limit Log
When set, indicate s that the Max Turbo Limit St atus bit has asserted since 
28 Electrical Design Point Log 
When set, indicates that the EDP Status bit has a sserted since the log bit 
was last cleared.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Tr ansition Attenuation Status bit has 
asserted since the log bit was last cleared.
30 Maximum Efficiency Frequency Log 
When set, indicates that  the Maximum Efficiency Frequency Status bit has 
Register Address: 680H, 1664 MSR_LASTBRAN CH_0_FROM_IPTable 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-133MODEL-SPECIFIC REGISTERS (MSRS)
One of 32 pairs of last branch record re gisters on the last branch record stack. The From_IP part of the stack contains 
pointers to the source instruction. See also:
• Section 18.6 and record format in Section 18.4.8.1.Core
0:47 From Linear Address (R/W)
62:48 Signed extension of bits 47:0.
63 Mispred
Register Address: 681H, 1665 MSR_LASTBRAN CH_1_FROM_IP
Register Address: 682H, 1666 MSR_LASTBRAN CH_2_FROM_IP
Register Address: 683H, 1667 MSR_LASTBRAN CH_3_FROM_IP
Register Address: 684H, 1668 MSR_LASTBRAN CH_4_FROM_IP
Register Address: 685H, 1669 MSR_LASTBRAN CH_5_FROM_IP
Register Address: 686H, 1670 MSR_LASTBRAN CH_6_FROM_IP
Register Address: 687H, 1671 MSR_LASTBRAN CH_7_FROM_IP
Register Address: 688H, 1672 MSR_LASTBRAN CH_8_FROM_IP
Last Branch Record  8 From IP (R/W)
Register Address: 689H, 1673 MSR_LASTBRAN CH_9_FROM_IP
Last Branch Record  9 From IP (R/W)
Register Address: 68AH, 1674 MSR_LASTBRANCH_10_FROM_IP
Last Branch Record 10 From IP (R/W)
Register Address: 68BH, 1675 MSR_LASTBRANCH_11_FROM_IPTable 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-134 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 11 From IP (R/W)
Register Address: 68CH, 1676 MSR_LASTBRANCH_12_FROM_IP
Last Branch Record 12 From IP (R/W)
Register Address: 68DH, 1677 MSR_LASTBRANCH_13_FROM_IP
Last Branch Record 13 From IP (R/W)
Register Address: 68EH, 1678 MSR_LASTBRANCH_14_FROM_IP
Last Branch Record 14 From IP (R/W)
Register Address: 68FH, 1679 MSR_LASTBRANCH_15_FROM_IP
Last Branch Record 15 From IP (R/W)
Register Address: 690H, 1680 MSR_LASTBRANCH_16_FROM_IP
Last Branch Record 16 From IP (R/W)
Register Address: 691H, 1681 MSR_LASTBRANCH_17_FROM_IP
Last Branch Record 17 From IP (R/W)
Register Address: 692H, 1682 MSR_LASTBRANCH_18_FROM_IP
Last Branch Record 18 From IP (R/W)
Register Address: 693H, 1683 MSR_LASTBRANCH_19_FROM_IP
Last Branch Record  19From IP (R/W)
Register Address: 694H, 1684 MSR_LASTBRANCH_20_FROM_IP
Last Branch Record 20 From IP (R/W)
Register Address: 695H, 1685 MSR_LASTBRANCH_21_FROM_IP
Last Branch Record 21 From IP (R/W)
Register Address: 696H, 1686 MSR_LASTBRANCH_22_FROM_IP
Last Branch Record 22 From IP (R/W)
Register Address: 697H, 1687 MSR_LASTBRANCH_23_FROM_IP
Last Branch Record 23 From IP (R/W)
Register Address: 698H, 1688 MSR_LASTBRANCH_24_FROM_IPTable 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-135MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 24 From IP (R/W)
Register Address: 699H, 1689 MSR_LASTBRANCH_25_FROM_IP
Last Branch Record 25 From IP (R/W)
Register Address: 69AH, 1690 MSR_LASTBRANCH_26_FROM_IP
Last Branch Record 26 From IP (R/W)
Register Address: 69BH, 1691 MSR_LASTBRANCH_27_FROM_IP
Last Branch Record 27 From IP (R/W)
Register Address: 69CH, 1692 MSR_LASTBRANCH_28_FROM_IP
Last Branch Record 28 From IP (R/W)
Register Address: 69DH, 1693 MSR_LASTBRANCH_29_FROM_IP
Last Branch Record 29 From IP (R/W)

Register Address: 69EH, 1694 MSR_LASTBRANCH_30_FROM_IP
Last Branch Record 30 From IP (R/W)
Register Address: 69FH, 1695 MSR_LASTBRANCH_31_FROM_IP
Last Branch Record 31 From IP (R/W)
Register Address: 6C0H, 1728 MSR_LASTBRANCH_0_TO_IP
One of 32 pairs of last branch  record registers on the last branch record stack. The To_IP part of the stack contains 
pointers to the Destination instruction and elapsed cycles from last LBR update. See Section 18.6.Core
0:47 Target Linear Address (R/W)
63:48 Elapsed cycles from last update to the LBR.
Register Address: 6C1H, 1729 MSR_LASTBRANCH_1_TO_IP
Register Address: 6C2H, 1730 MSR_LASTBRANCH_2_TO_IP
Register Address: 6C3H, 1731 MSR_LASTBRANCH_3_TO_IP
Register Address: 6C4H, 1732 MSR_LASTBRANCH_4_TO_IPTable 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-136 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6C5H, 1733 MSR_LASTBRANCH_5_TO_IP
Register Address: 6C6H, 1734 MSR_LASTBRANCH_6_TO_IP
Register Address: 6C7H, 1735 MSR_LASTBRANCH_7_TO_IP
Register Address: 6C8H, 1736 MSR_LASTBRANCH_8_TO_IP
Last Branch Record  8 To IP (R/W)
Register Address: 6C9H, 1737 MSR_LASTBRANCH_9_TO_IP
Last Branch Record  9 To IP (R/W)
Register Address: 6CAH, 1738 MSR_LASTBRAN CH_10_TO_IP
Last Branch Record  10 To IP (R/W)
Register Address: 6CBH, 1739 MSR_LASTBRAN CH_11_TO_IP
Last Branch Record  11 To IP (R/W)
Register Address: 6CCH, 1740 MSR_LASTBRAN CH_12_TO_IP
Last Branch Record  12 To IP (R/W)
Register Address: 6CDH, 1741 MSR_LASTBRAN CH_13_TO_IP
Last Branch Record  13 To IP (R/W)
Register Address: 6CEH, 1742 MSR_LASTBRAN CH_14_TO_IP
Last Branch Record  14 To IP (R/W)
Register Address: 6CFH, 1743 MSR_LASTBRAN CH_15_TO_IP
Last Branch Record  15 To IP (R/W)
Register Address: 6D0H, 1744 MSR_LASTBRAN CH_16_TO_IP
Last Branch Record  16 To IP (R/W)
Register Address: 6D1H, 1745 MSR_LASTBRAN CH_17_TO_IPTable 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-137MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record  17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.Core
Register Address: 6D2H, 1746 MSR_LASTBRANCH_18_TO_IP
Last Branch Record  18 To IP (R/W)
Register Address: 6D3H, 1747 MSR_LASTBRANCH_19_TO_IP
Last Branch Record  19To IP (R/W)
Register Address: 6D4H, 1748 MSR_LASTBRANCH_20_TO_IP
Last Branch Record  20 To IP (R/W)
Register Address: 6D5H, 1749 MSR_LASTBRANCH_21_TO_IP
Last Branch Record  21 To IP (R/W)
Register Address: 6D6H, 1750 MSR_LASTBRANCH_22_TO_IP
Last Branch Record  22 To IP (R/W)
Register Address: 6D7H, 1751 MSR_LASTBRANCH_23_TO_IP
Last Branch Record  23 To IP (R/W)
Register Address: 6D8H, 1752 MSR_LASTBRANCH_24_TO_IP
Last Branch Record  24 To IP (R/W)
Register Address: 6D9H, 1753 MSR_LASTBRANCH_25_TO_IP
Last Branch Record  25 To IP (R/W)
Register Address: 6DAH, 1754 MSR_LASTBRANCH_26_TO_IP
Last Branch Record  26 To IP (R/W)
Register Address: 6DBH, 1755 MSR_LASTBRANCH_27_TO_IP
Last Branch Record  27 To IP (R/W)
Register Addres s: 6DCH, 1756 MSR_LASTBRANCH_28_TO_IP
Last Branch Record  28 To IP (R/W)
Register Address: 6DDH, 1757 MSR_LASTBRANCH_29_TO_IP
Last Branch Record  29 To IP (R/W)
Register Addres s: 6DEH, 1758 MSR_LASTBRANCH_30_TO_IPTable 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-138 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record  30 To IP (R/W)
Register Address: 6DFH, 1759 MSR_LASTBRAN CH_31_TO_IP
Last Branch Record  31 To IP (R/W)
x2APIC ID register (R/O) Core
x2APIC Version register (R/O) Core
x2APIC Task Priority register (R/W) Core
x2APIC Processor Priority register (R/O) Core
x2APIC EOI register (W/O) Core
x2APIC Logical Destin ation register (R/O) Core
x2APIC Spurious Interrupt Vector register (R/W) Core
x2APIC In-Service  register bits [31:0] (R/O) Core
x2APIC In-Service register bits [63:32] (R/O) Core
x2APIC In-Service register bits [95:64] (R/O) Core
x2APIC In-Service register bits [127:96] (R/O) Core
x2APIC In-Service register bits [159:128] (R/O) Core
x2APIC In-Service register bits [191:160] (R/O) Core
x2APIC In-Service register bits [223:192] (R/O) Core
x2APIC In-Service register bits [255:224] (R/O) Core
x2APIC Trigger Mode register bits [31:0] (R/O) Core
Register Address: 819H, 2073 IA32_X2APIC_TMR1Table 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-139MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC Trigger Mode register bits [63:32] (R/O) Core
x2APIC Trigger Mode register bits [95:64] (R/O) Core
x2APIC Trigger Mode register bits [127:96] (R/O) Core
x2APIC Trigger Mode register bits [159:128] (R/O) Core
x2APIC Trigger Mode register bits [191:160] (R/O) Core
x2APIC Trigger Mode register bits [223:192] (R/O) Core
x2APIC Trigger Mode register bits [255:224] (R/O) Core
x2APIC Interrupt Request regi ster bits [31:0] (R/O) Core
x2APIC Interrupt Request regi ster bits [63:32] (R/O) Core
x2APIC Interrupt Request regi ster bits [95:64] (R/O) Core
x2APIC Interrupt Request regist er bits [127:96] (R/O) Core
x2APIC Interrupt Request regist er bits [159:128] (R/O) Core
x2APIC Interrupt Request regist er bits [191:160] (R/O) Core
x2APIC Interrupt Request regist er bits [223:192] (R/O) Core
x2APIC Interrupt Request regist er bits [255:224] (R/O) Core
x2APIC Error Status register (R/W) Core

x2APIC LVT Corrected Machine Check Interrupt register (R/W) Core
x2APIC Interrupt Comma nd register (R/W) Core
x2APIC LVT Timer Interrupt register (R/W) CoreTable 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-140 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC LVT Thermal Sensor Interrupt register (R/W) Core
x2APIC LVT Performance Mo nitor register (R/W) Core
x2APIC LVT LINT0 register (R/W) Core
x2APIC LVT LINT1 register (R/W) Core
x2APIC LVT Error register (R/W) Core
x2APIC Initial Coun t register (R/W) Core
x2APIC Current Count register (R/O) Core
x2APIC Divide Configuration register (R/W) Core
x2APIC Self IPI register (W/O) Core
Resource Associatio n Register (R/W) Core
33:32 COS (R/W)63: 34 Reserved.
Register Address: D10H, 3344 IA32_L2_QOS_MASK_0
L2 Class Of Service Mask - COS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.Module
0:7 CBM: Bit vector of available L2 ways for COS 0 enforcement.
Register Address: D11H, 3345 IA32_L2_QOS_MASK_1
L2 Class Of Service Mask - COS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.Module
Register Address: D12H, 3346 IA32_L2_QOS_MASK_2
L2 Class Of Service Mask - COS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.Module
63:8 Reserved.Table 2-12.   MSRs in Intel Atom® Processors Based on Gold mont Microarchi tecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-141MODEL-SPECIFIC REGISTERS (MSRS)
2.6 MSRS IN INTEL ATOM® PROCE SSORS BASED ON GOLDMONT PLUS 
Intel Atom processors based on the Goldmont Plus microarc hitecture support MSRs listed in Table 2-6, Table 2-12, 
and Table 2-13. These processors have a CPUID Signatur e DisplayFamily_DisplayModel value of 06_7AH; see Table 
2-1. For an MSR listed in Table 2-13 that also appears in the model-specific tables of prior generations, Table 2-13 
supersede prior generation tables.
In the Goldmont Plus microarchitecture, the scope column indicates the following: “Core” means each processor 
core has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit 
field is shared by a subset of the processor cores in the physical package. The number of processor cores in this 
subset is model specific and may differ between different processors. For all processors based on Goldmont Plus 
microarchitecture, the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration 
can be used to figure out which processors are in the same module. “Package” means all processor cores in the 
physical package share the same MSR or bit interface.Register Address: D13H, 3347 IA32_L2_QOS_MASK_3
L2 Class Of Service Mask - COS 3 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.Package
0:19 CBM: Bit vector of available L2 ways for COS 3 enforcement.
See Table 2-6, and Table 2-12 for MSR definitions applicable to processors with a CPUID Signatur e DisplayFamily_DisplayModel va lue 
of 06_5CH. 
Table 2-13.   MSRs in Intel Atom® Processors  Based on Goldmont Pl us Microarchitecture
14:8 SENTER local functi ons enables (R/WL) 
15 SENTER global functions enable (R/WL) 
This bit must be set to enable runtime reconfiguration of SGX Launch 
Control via IA32_SGXLEPUBKEYHASHn MSR. 
Valid if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.Table 2-12.   MSRs in Intel Atom® Processors  Based on Goldmont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-142 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
18 SGX global functions enable (R/WL) 
Register Address: 8CH, 140 IA32_SGXLEPUBKEYHASH0
(R/W) See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Core
otherwise) on IA32_PMC0. 
1 Enable PEBS trigger and recording fo r the programmed event (precise or 
otherwise) on IA32_PMC1.
2 Enable PEBS trigger and recording fo r the programmed event (precise or 
otherwise) on IA32_PMC2.
3 Enable PEBS trigger and recording fo r the programmed event (precise or 
otherwise) on IA32_PMC3.
31:4 Reserved.32 Enable PEBS trigger and recording for IA32_FIXED_CTR0.
33 Enable PEBS trigger and recording for IA32_FIXED_CTR1.
34 Enable PEBS trigger and recording for IA32_FIXED_CTR2.63:35 Reserved.
0T r a c e E n
1 CYCEn
2O S3U s e r
4P w r E v t E n
5F U P o n P T W6F a b r i c E n
7C R 3 F i l t e r
8T o P A
9M T C E n10 TSCEnTable 2-13.   MSRs in Intel Atom® Processors Ba sed on Goldmont Plus Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-143MODEL-SPECIFIC REGISTERS (MSRS)
11 DisRETC
12 PTWEn
13 BranchEn17:14 MTCFreq
22:19 CycThresh23 Reserved, must be zero.
27:24 PSBFreq
31:28 Reserved, must be zero.35:32 ADDR0_CFG39:36 ADDR1_CFG
Register Address: 680H, 1664 MSR_LASTBRAN CH_0_FROM_IP
One of the three MSRs th at make up the first entry of the 32-entry LBR stack. The From_IP part of the stack contains 
• Section 18.7, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus 
Microarchitecture.”Core
Register Address: 681H −69FH, 1665 −
1695MSR_LASTBRANCH_ i_FROM_IP
Last Branch Record i From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP; i = 1-31.Core
One of the three MSRs that make up th e first entry of the 32-entry LBR stack. The To_IP part of the stack contains 
pointers to the Destination instruction. See also:
Register Address: 6C1H −6DFH, 1729 −
1759MSR_LASTBRANCH_ i_TO_IP
Last Branch Record i To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP; i = 1-31. Core
Register Address: DC0H, 3520 MSR_LASTBRANCH_INFO_0
Last Branch Record 0 Addi tional Information (R/W)
One of the three MSRs that make up the first entry of the 32-entry LB R stack. This part of the stack contains flag and 
elapsed cycle information. See also:
• Section 18.9.1, “LBR Stack.”Core
Register Address: DC1H, 3521 MSR_LASTBRANCH_INFO_1
Last Branch Record 1 Addi tional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.CoreTable 2-13.   MSRs in Intel Atom® Processors Ba sed on Goldmont Plus Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-144 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DC2H, 3522 MSR_LASTBRANCH_INFO_2
Last Branch Record 2 Addi tional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0. Core

Register Address: DC3H, 3523 MSR_LASTBRANCH_INFO_3
Last Branch Record 3 Addi tional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.Core
Register Address: DC4H, 3524 MSR_LASTBRANCH_INFO_4
Last Branch Record 4 Addi tional Information (R/W)
Register Address: DC5H, 3525 MSR_LASTBRANCH_INFO_5
Last Branch Record 5 Addi tional Information (R/W)
Register Address: DC6H, 3526 MSR_LASTBRANCH_INFO_6
Last Branch Record 6 Addi tional Information (R/W)
Register Address: DC7H, 3527 MSR_LASTBRANCH_INFO_7
Last Branch Record 7 Addi tional Information (R/W)
Register Address: DC8H, 3528 MSR_LASTBRANCH_INFO_8
Last Branch Record 8 Addi tional Information (R/W)
Register Address: DC9H, 3529 MSR_LASTBRANCH_INFO_9
Last Branch Record 9 Addi tional Information (R/W)
Register Address: DCAH, 3530 MSR_LASTBRANCH_INFO_10
Last Branch Record 10 Additional Information (R/W)
Register Address: DCBH, 3531 MSR_LASTBRANCH_INFO_11
Last Branch Record 11 Additional Information (R/W)
Register Address: DCCH, 3532 MSR_LASTBRANCH_INFO_12
Last Branch Record 12 Additional Information (R/W)
Register Address: DCDH, 3533 MSR_LASTBRANCH_INFO_13
Last Branch Record 13 Additional Information (R/W)
Register Address: DCEH, 3534 MSR_LASTBRANCH_INFO_14
Last Branch Record 14 Additional Information (R/W)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-145MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DCFH, 3535 MSR_LASTBRANCH_INFO_15
Last Branch Record 15 Additional Information (R/W)
Register Address: DD0H, 3536 MSR_LASTBRANCH_INFO_16
Last Branch Record 16 Additional Information (R/W)
Register Address: DD1H, 3537 MSR_LASTBRANCH_INFO_17
Last Branch Record 17 Additional Information (R/W)
Register Address: DD2H, 3538 MSR_LASTBRANCH_INFO_18
Last Branch Record 18 Additional Information (R/W)
Register Address: DD3H, 3539 MSR_LASTBRANCH_INFO_19
Last Branch Record 19 Additional Information (R/W)
Register Address: DD4H, 3520 MSR_LASTBRANCH_INFO_20
Last Branch Record 20 Additional Information (R/W)
Register Address: DD5H, 3521 MSR_LASTBRANCH_INFO_21
Last Branch Record 21 Additional Information (R/W)
Register Address: DD6H, 3522 MSR_LASTBRANCH_INFO_22
Last Branch Record 22 Additional Information (R/W)
Register Address: DD7H, 3523 MSR_LASTBRANCH_INFO_23
Last Branch Record 23 Additional Information (R/W)
Register Address: DD8H, 3524 MSR_LASTBRANCH_INFO_24
Last Branch Record 24 Additional Information (R/W)
Register Address: DD9H, 3525 MSR_LASTBRANCH_INFO_25
Last Branch Record 25 Additional Information (R/W)
Register Address: DDAH, 3526 MSR_LASTBRANCH_INFO_26
Last Branch Record 26 Additional Information (R/W)
Register Address: DDBH, 3527 MSR_LASTBRANCH_INFO_27
Last Branch Record 27 Additional Information (R/W)
Register Information / Bit Fields Bit Description Scope2-146 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.7 MSRS IN INTEL ATOM® PR OCESSORS BASED ON TREMONT 
Processors based on the Tremont microarchitecture support  MSRs listed in Table 2-6, Table 2-12, Table 2-13, and 
Table 2-14. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_86H, 06_96H, or 
06_9CH; see Table 2-1. For an MSR listed in Table 2-14 that also appears in the model-specific tables of prior 
generations, Table 2-14 supersede prior generation tables.
In the Tremont microarchitecture, the scope column indicates the following: “Core” means each processor core has 
a separate MSR, or a bit field not shar ed with another processor core. “Module” means the MSR or the bit field is 
shared by a subset of the processor cores in the physical package. The number of processor cores in this subset is 
model specific and may differ between different processors. For all processors based on Tremont microarchitecture, 
the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration can be used to figure out which processors are in the same module. “Package” means all processor cores in the physical package share 
the same MSR or bit interface.Register Address: DDCH, 3528 MSR_LASTBRANCH_INFO_28
Last Branch Record 28 Additional Information (R/W)
Register Address: DDDH, 3529 MSR_LASTBRANCH_INFO_29
Last Branch Record 29 Additional Information (R/W)
Register Address: DDEH, 3530 MSR_LASTBRANCH_INFO_30
Last Branch Record 30 Additional Information (R/W)
Register Address: DDFH, 3531 MSR_LASTBRANCH_INFO_31
Last Branch Record 31 Additional Information (R/W)
See Table 2-6, Table 2-12, and Table 2-13 for MSR definiti ons applicable to processors with a CPUID Signature 
DisplayFamily_DisplayMod el value of 06_7AH. 
Table 2-14.   MSRs in Intel Atom® Proces sors Based on Tremont Microarchitecture
Register Address: 33H, 51 MSR_MEMORY_CTRL
Memory Control Register Core
28:0 Reserved.
29 SPLIT_LOCK_DISABLE
If set to 1, a split lock wi ll cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
30 Reserved.
Register Address: CFH, 207 IA32_CORE_CAPABILITIESTable 2-13.   MSRs in Intel Atom® Processors Ba sed on Goldmont Plus Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-147MODEL-SPECIFIC REGISTERS (MSRS)
IA32 Core Capabilities Register
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.Core
4:0 Reserved.
5 SPLIT_LOCK_DISABLE_SUPPORTED 
When read as 1, soft ware can set bit 29 of MSR_MEMORY_CTRL (MSR 
address 33H).
Register Address: 2A0H, 672 MSR_PRMRR_BASE_0
Processor Reserved Memory Range Register - Physical Base Control Register (R/W) Core
2:0 MEMTYPE: PRMRR BASE Memory Type.3 CONFIGURED: PRMRR BASE Configured.
11:4 Reserved.
51:12 BASE: PRMRR Base Address.63:52 Reserved.
(R/W) See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Coren:0 Enable PEBS trigger and recording fo r the programmed event (precise or 
otherwise) on IA32_PMCx. The maximu m value n can be determined from 
CPUID.0AH:EAX[15:8].
31:n+1 Reserved.
32+m:32 Enable PEBS trigger and recordin g for IA32_FIXED_CTRx. The maximum 
value m can be determined from CPUID.0AH:EDX[4:0].
59:33+ m Reserved.
60 Pend a PerfMon Interrupt (P MI) after each PEBS event.
62:61 Specifies PEBS output destination. Encodings:
00B: DS Save Area.
01B: Intel PT trace output. Supported if 
IA32_PERF_CAPABILITIES.PEBS _OUTPUT_PT_AVAIL[16] and 
CPUID.07H.0.EBX[25] are set.
Register Address: 1309H −130BH, 
4873−4875MSR_RELOAD_FIXED_CTRx
Reload value for IA32_FIXED_CTRx (R/W)
47:0 Value loaded into IA32_FIXED_CTR x when a PEBS record is generated 
while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT = 01B in 
IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.
Register Address: 14C1H −14C4H, 
5313−5316MSR_RELOAD_PMCxTable 2-14.   MSRs in Intel Atom® Processors Based on Trem ont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-148 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.8 MSRS IN PROCESSORS BASED ON NEHALEM MICROARCHITECTURE
Table 2-15 lists model-specific registers (MSRs) that ar e common for Nehalem microarchitecture. These include the

Table 2-15 lists model-specific registers (MSRs) that ar e common for Nehalem microarchitecture. These include the 
Intel Core i7 and i5 processor family. These processors have a CPUID Signature DisplayFamily_DisplayModel value 
of 06_1AH, 06_1EH, 06_1FH, or 06_2EH; see Table 2-1. A dditional MSRs specific to processors with a CPUID 
Signature DisplayFamily_DisplayModel value of 06_1AH, 06_1EH, or 06_1FH are listed in Table 2-16. Some MSRs 
listed in these tables are used by BIOS. More inform ation about these MSR can be found at http://biosbits.org.
The column “Scope” represents the package/core/thread scope  of individual bit field of an MSR. “Thread” means 
this bit field must be programmed on each logical proc essor independently. “Core” means the bit field must be 
programmed on each processor core independently, logical pr ocessors in the same core will be affected by change 
of this bit on the other logical processor in the same core. “Package” means the bit field must be programmed once 
for each physical package. Change of a bit filed with a pack age scope will affect all logical processors in that phys-
ical package.Reload value for IA32_PMCx (R/W) Core
47:0 Value loaded into IA 32_PMCx when a PEBS reco rd is generated while 
PEBS_EN_PMCx = 1 and PEBS_OUTPU T = 01B in IA32_PEBS_ENABLE, 
and PMCx is overflowed.
See Table 2-6, Table 2-12, Table 2-13, and Table 2-14 for MSR definitions applicable to processors with a CPUID Signature 
DisplayFamily_DisplayMod el value of 06_86H. 
Table 2-15.  MSRs in Processors Based on Nehalem Microarchitecture
See Section 2.23, “MSRs in Pentium Processors.” Thread
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Thread
See Section 18.17, “Time-Stamp Counter,” and Table 2-2. Thread
Model Specific Platform ID (R) Package
52:50 See Table 2-2.63:53 Reserved.
Register Address: 1BH, 27 IA32_APIC_BASETable 2-14.   MSRs in Intel Atom® Processors  Based on Tremont Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-149MODEL-SPECIFIC REGISTERS (MSRS)
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Thread
SMI Counter (R/O) Thread
See Table 2-2.Thread
This is the ratio of the frequency that invariant TSC runs at. The invariant 
TSC frequency can be computed by multiplying this ratio by 133.33 MHz.Package
When set to 1, indicates that Programmable Ratio Limit for Turbo mode is 
enabled. When set to 0, indicates Programmable Ratio Limit for Turbo 
mode is disabled.PackageTable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-150 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
29 Programmable TDC-TDP Limit for Turbo Mode (R/O) 
When set to 1, indicates that TDC and TDP Limits for Turbo mode are 
programmable. When set to 0, indicates TDC and TDP Limits for Turbo 
mode are not programmable.Package
39:30 Reserved.
47:40 Maximum Effici ency Ratio (R/O) 
operate, in units of 133.33MHz.Package
ACPI C-States. See http://biosbits.org.Core
010b: C3
011b: C6100b: C7
101b and 110b: Reserved
111: No package C-state limit.Note: This field cannot be used to limit package C-state to C3.
23:16 Reserved.
24 Interrupt filtering enable (R/W) 
When set, processor cores in a deep C-State will wake only when the event 
message is destined for that core. When  0, all processor cores in a deep C-
State will wake for an event message.
25 C3 state auto demo tion enable (R/W) 
When set, the processor will conditio nally demote C6/C7 requests to C3 
based on uncore auto-demote information.Table 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-151MODEL-SPECIFIC REGISTERS (MSRS)
26 C1 state auto demo tion enable (R/W) 
When set, the processor will conditionally demote C3/C6/C7 requests to C1 
based on uncore auto-demote information.
27 Enable C3 Undemotion (R/W)28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)
30 Package C State Undemotion Enable (R/W)63:31 Reserved.
000b - C3 is the max C-State to include.001b - C6 is the max C-State to include.
See Table 2-2. Thread
See Table 2-2. ThreadTable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-152 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Global Machine Check Status Thread
0R I P V
1E I P V
2M C I P
When set, bit indicates that a mach ine check has been generated. If a 
second machine check is detected while this bit is still set, the processor 
enters a shutdown state. Software should write this bit to 0 after 

0R I P V
1E I P V
2M C I P
7:0 Event Select15:8 UMask
16 USR
17 OS18 Edge
19 PC
20 INT21 AnyThread
22 EN
23 INV31:24 CMASK
15:0 Current Performance State Value.Table 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-153MODEL-SPECIFIC REGISTERS (MSRS)
IA32_CLOCK_MODULATION MSR was origin ally named IA32_THERM_CONTROL MSR.Thread
3:1 On demand Clock Modulation Duty Cycle (R/W)
4 On demand Clock Modulation Enable (R/W)63:5 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 1.Thread
18 ENABLE MONITOR FSM. (R/W) See Table 2-2. Thread
21:19 Reserved.Table 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-154 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-3.Thread
37:35 Reserved.
the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
available in the processor. If the power- on default value is 0, turbo mode is 
not available.Package
Temperature Target Thread
15:0 Reserved.23:16 Temperature Target (R) 
The minimum temperature at which PROCHOT# will be asserted. The value 
is degrees C.
1 L2 Adjacent Cache Line Prefetcher Disable (R/W) 
If 1, disables the adjacent cache line prefetcher, which fetches the cache 
line that comprises a cach e line pair (128 bytes).Core
3 DCU IP Prefetcher Disable (R/W) 
If 1, disables the L1 data cache IP prefetcher, which uses sequential load 
history (based on instruction pointer of previous loads) to determine 
whether to prefetch additional lines.Core
Register Address: 1A6H, 422 MSR_OFFCORE_RSP_0Table 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-155MODEL-SPECIFIC REGISTERS (MSRS)
Offcore Response Event Select Register (R/W) Thread
Various model specific features en umeration. See h ttp://biosbits.org.
coordination of Enhanced Intel Speedstep Technology requests.Package
1 Energy/Performance Bias Enable (R/W) 
This bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible 
to software with Ring 0 privileges. This bit’s status (1 or 0) is also reflected 
by CPUID.(EAX=06h):ECX[3].Thread
Register Address: 1ACH, 428 MSR_TURBO_POWER_CURRENT_LIMIT
See http://biosbits.org.14:0 TDP Limit (R/W) 
TDP limit in 1/8 Watt granularity.Package
15 TDP Limit Override Enable (R/W) 
A value = 0 indicates override is not active; a value = 1 indicates override is 
active.Package
30:16 TDC Limit (R/W) 
TDC limit in 1/8 Amp granularity.Package
31 TDC Limit Override Enable (R/W) 
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.R/W if MSR_PLATFORM_INFO.[28] = 1.Package
Register Address: 1C8H, 456 MSR_LBR_SELECTTable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-156 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Section 18.9.2, “Filtering  of Last Bran ch Records.”Core
0C P L _ E Q _ 0
4N E A R _ I N D _ C A L L
5 NEAR_RET6N E A R _ I N D _ J M P7 NEAR_REL_JMP
See MSR_LASTBRANCH_0_FROM_IP (at 680H).Thread
generated or the last in terrupt that was handled.Thread
This area contains a pointer to  the target of the last  branch instruction that the processor executed prior to the last 
exception that was generated or the last interrupt th at was handled. Thread
63:2 Reserved.Table 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-157MODEL-SPECIFIC REGISTERS (MSRS)

Register Address: 212H, 530 IA32_MTRR_PHYSBASE9Table 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-158 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 281H, 641 IA32_MC1_CTL2
See Table 2-2. CoreTable 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-159MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Thread
5:0 LBR Format
6 PEBS Record Format
7 PEBSSaveArchRegs
11:8 PEBS_REC_FORMAT
12 SMM_FREEZE
See Table 2-2. See Section 20.6.2.2, “Glo bal Counter Control Facilities.” Thread
Provides single-bit status used by soft ware to query the overflow condition of each performance counter. (R/O) ThreadTable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-160 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
61 UNC_Ovf
Uncore overflowed if 1.
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Allows software  to clear counter overflow 
conditions on any combination of fixed-function PMCs (IA32_FIXED_CTRx) or general-purpose PMCs via a single WRMSR.Thread
(R/W) Thread
61 CLR_UNC_Ovf
Set 1 to clear UNC_Ovf.
See Section 20.3.1.1.1, “Processor Event Based Sampling (PEBS).” Thread
0 Enable PEBS on IA32_PMC0 (R/W)1 Enable PEBS on IA32_PMC1 (R/W)
2 Enable PEBS on IA32_PMC2 (R/W)
3 Enable PEBS on IA32_PMC3 (R/W)31:4 Reserved.
32 Enable Load Latency on IA32_PMC0 (R/W)
33 Enable Load Latency on IA32_PMC1 (R/W)34 Enable Load Latency on IA32_PMC2 (R/W)
35 Enable Load Latency on IA32_PMC3 (R/W)
Register Address: 3F6H, 1014 MSR_PEBS_LD_LAT
See Section 20.3.1.1.2, “Load Latency Performance Monitoring Facility.” Thread
15:0 Minimum threshold latency value of tagged load operation that will be 
counted. (R/W)
ACPI C-States.PackageTable 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-161MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 3FAH, 1018 MSR_PKG_C7_RESIDENCY
63:0 Package C7 Residency Counter (R/O)
Value since last reset that  this package is in proc essor-specific C7 states. 
Value since last reset that this core is in processor-specific C3 states. Count 
at the same frequency as the TSC.
Register Address: 3FDH, 1021 MSR_CORE_C6_RESIDENCY
Value since last reset that this core is in processor-specific C6 states. Count 
See Section 16.3.2.4, “IA32_MC i_MISC MSRs.” Package
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.PackageTable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-162 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)

See Section 16.3.2.4, “IA32_MC i_MISC MSRs.” Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” CoreTable 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-163MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 41EH, 1054 IA32_MC7_ADDR
Register Address: 422H, 1058 IA32_MC8_ADDR
See Table 2-2 and Appendix A.1, “Basic VMX Information.”Thread
Capability Reporting Register of Pin-based VM-execution Controls (R/O) 
See Table 2-2 and Appendix A.3, “VM-Execution Controls.”Thread
See Appendix A.3, “VM-Execution Controls.”Thread
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLSTable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-164 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2 and Appendix A.4, “VM-Exit Controls.”Thread
See Table 2-2 and Appendix A.5, “VM-Entry Controls.”Thread
See Table 2-2 and Appendix A.6, “Miscellaneous Data.”Thread
See Table 2-2 and Appendix A.7,  “VMX-Fixed Bi ts in CR0.”Thread
See Table 2-2 and Appendix A.8,  “VMX-Fixed Bi ts in CR4.”Thread
See Table 2-2 and Appendix A.9, “VMCS Enumeration.”Thread
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”Thread
One of sixteen pairs of last branch record regi sters on the last branch record st ack. The From_IP part of the stack 
• See Section 18.9.1 and record format in Section 18.4.8.1.Thread
See description of MSR_LASTBRANCH_0_FROM_IP.Thread
Register Address: 682H, 1666 MSR_LASTBRAN CH_2_FROM_IPTable 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-165MODEL-SPECIFIC REGISTERS (MSRS)
See description of MSR_LASTBRANCH_0_FROM_IP. Thread
Register Address: 68BH, 1675 MSR_LASTBRANCH_11_FROM_IP
Register Address: 68FH, 1679 MSR_LASTBRANCH_15_FROM_IPTable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-166 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
One of sixteen pairs of last br anch record registers on the last branch record stack. This part of the stack contains 
pointers to the destination instruction.Thread
See description of MSR_LASTBRANCH_0_TO_IP. Thread

Register Address: 6C4H, 1732 MSR_LASTBRANCH_4_TO_IP
See description of MSR_LASTBRANCH_0_TO_IP. ThreadTable 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-167MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6CCH, 1740 MSR_LASTBRANCH_12_TO_IP
Register Address: 6CDH, 1741 MSR_LASTBRANCH_13_TO_IP
Register Address: 6CEH, 1742 MSR_LASTBRANCH_14_TO_IP
Register Address: 6CFH, 1743 MSR_LASTBRANCH_15_TO_IP
x2APIC ID Register (R/O) Thread
x2APIC Version Register (R/O) Thread
x2APIC Task Priori ty Register (R/W) Thread
x2APIC Processor Priority Register (R/O) Thread
x2APIC EOI Register (W/O) Thread
x2APIC Logical Destin ation Register (R/O) Thread
x2APIC Spurious Interrupt Vector Register (R/W) Thread
x2APIC In-Service Register Bits [31:0] (R/O) Thread
x2APIC In-Service Register Bits [63:32] (R/O) Thread
x2APIC In-Service Register Bits [95:64] (R/O) Thread
x2APIC In-Service Register Bits [127:96] (R/O) Thread
x2APIC In-Service Register Bits [159:128] (R/O) Thread
x2APIC In-Service Register Bits [191:160] (R/O) ThreadTable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-168 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC In-Service Register Bits [223:192] (R/O) Thread
x2APIC In-Service Register Bits [255:224] (R/O) Thread
x2APIC Trigger Mode Register Bits [31:0] (R/O) Thread
x2APIC Trigger Mode Register Bits [63:32] (R/O) Thread
x2APIC Trigger Mode Register Bits [95:64] (R/O) Thread
x2APIC Trigger Mode Register Bits [127:96] (R/O) Thread
x2APIC Trigger Mode Register Bits [159:128] (R/O) Thread
x2APIC Trigger Mode Register Bits [191:160] (R/O) Thread
x2APIC Trigger Mode Register Bits [223:192] (R/O) Thread
x2APIC Trigger Mode Register Bits [255:224] (R/O) Thread
x2APIC Interrupt Request Register Bits [31:0] (R/O) Thread
x2APIC Interrupt Request Register Bits [63:32] (R/O) Thread
x2APIC Interrupt Request Register Bits [95:64] (R/O) Thread
x2APIC Interrupt Request Register Bits [127:96] (R/O) Thread
x2APIC Interrupt Request Regist er Bits [159:128] (R/O) Thread
x2APIC Interrupt Request Regist er Bits [191:160] (R/O) Thread
x2APIC Interrupt Request Regist er Bits [223:192] (R/O) Thread
x2APIC Interrupt Request Regist er Bits [255:224] (R/O) Thread
Register Address: 828H, 2088 IA32_X2APIC_ESRTable 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-169MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC Error Status Register (R/W) Thread
x2APIC LVT Corrected Machine Check Interrupt Register (R/W) Thread
x2APIC Interrupt Command Register (R/W) Thread
x2APIC LVT Timer Interrupt Register (R/W) Thread
x2APIC LVT Thermal Sensor Interrupt Register (R/W) Thread
x2APIC LVT Performance Monitor Register (R/W) Thread
x2APIC LVT LINT0 Register (R/W) Thread
x2APIC LVT LINT1 Register (R/W) Thread
x2APIC LVT Error Register (R/W) Thread
x2APIC Initial Coun t Register (R/W) Thread
x2APIC Current Count Register (R/O) Thread
x2APIC Divide Configuration Register (R/W) Thread
x2APIC Self IPI Register (W/O) Thread
Extended Feature Enables 
System Call Target Address (R/W) 
IA-32e Mode System Call Target Address (R/W) 
System Call Flag Mask (R/W) 
Register Address: C000_0100H IA32_FS_BASETable 2-15.  MSRs in Processors Base d on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-170 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.8.1  Additional MSRs in the Inte l® Xeon® Processor 5500 and 3400 Series
The Intel Xeon Processor 5500 and 3400 series supports addi tional model-specific registers listed in Table 2-16. 
These MSRs also apply to the Intel Core i7 and i5 processor family with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_1A H, 06_1EH, or 06_1FH; see Table 2-1. Map of BASE Address of FS (R/W) 
Map of BASE Address of GS (R/W) 
AUXILIARY TSC Signature (R/W) 
See Table 2-2 and Section 18.17.2, “IA32_ TSC_AUX Register and RDTSCP Support.” Thread
Table 2-16.  Additional MS Rs in the Intel® Xeon® Pr ocessor 5500 and 3400 Series
Actual maximum turbo frequency is multiplied by 133.33MHz. 
(Not available in model 06_2EH.)Package
7:0 Maximum Turbo Ratio Limit 1C (R/O) 
Maximum Turbo mode ratio li mit with 1 core active. 
15:8 Maximum Turbo Ratio Limit 2C (R/O) 
Maximum Turbo mode ratio limit with 2 cores active. 
23:16 Maximum Turbo Ratio Limit 3C (R/O)

23:16 Maximum Turbo Ratio Limit 3C (R/O) 
Maximum Turbo mode ratio limit with 3 cores active. 
31:24 Maximum Turbo Ratio Limit 4C (R/O) 
Maximum Turbo mode ratio limit with 4 cores active. 
Register Address: 301H, 769 MSR_GQ_SNOOP_MESF
 MSR_GQ_SNOOP_MESF Package
0F r o m  M  t o  S  ( R / W )
1F r o m  E  t o  S  ( R / W )2 From S to S (R/W)
3F r o m  F  t o  S  ( R / W )
4F r o m  M  t o  I  ( R / W )Table 2-15.  MSRs in Proc essors Based on Nehalem Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-171MODEL-SPECIFIC REGISTERS (MSRS)
5F r o m  E  t o  I  ( R / W )
6F r o m  S  t o  I  ( R / W )
7F r o m  F  t o  I  ( R / W )63:8 Reserved.
Register Address: 391H, 913 MSR_UNCORE_PERF_GLOBAL_CTRL
See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.” Package
Register Address: 392H, 914 MSR_UNCORE_PERF_GLOBAL_STATUS
Register Address: 393H, 915 MSR_UNCORE_PERF_GLOBAL_OVF_CTRL
Register Address: 394H, 916 MSR_UNCORE_FIXED_CTR0
Register Address: 395H, 917 MSR_UNCORE_FIX ED_CTR_CTRL
Register Address: 396H, 918 MSR_UNCORE_ADDR_OPCODE_MATCH
See Section 20.3.1.2.3, “Uncore Address/Opcode Match MSR.” Package
Register Address: 3B0H, 960 MSR_UNCORE_PMC0
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3B1H, 961 MSR_UNCORE_PMC1
Register Address: 3B2H, 962 MSR_UNCORE_PMC2
Register Address: 3B3H, 963 MSR_UNCORE_PMC3
Register Address: 3B4H, 964 MSR_UNCORE_PMC4
Register Address: 3B5H, 965 MSR_UNCORE_PMC5
Register Address: 3B6H, 966 MSR_UNCORE_PMC6
Register Address: 3B7H, 967 MSR_UNCORE_PMC7
Register Address: 3C0H, 944 MSR_UNCORE_PERFEVTSEL0
Register Address: 3C1H, 945 MSR_UNCORE_PERFEVTSEL1
Register Address: 3C2H, 946 MSR_UNCORE_PERFEVTSEL2Table 2-16.  Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-172 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.8.2  Additional MSRs in the Intel® Xeon® Processor 7500 Series
The Intel Xeon Processor 7500 series supports MSRs listed  in Table 2-15 (except MSR address 1ADH) and additional 
model-specific registers listed in Table 2-17.  These processors have a CPUID Signature 
DisplayFamily_DisplayModel value of 06_2EH.See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C3H, 947 MSR_UNCORE_PERFEVTSEL3
Register Address: 3C4H, 948 MSR_UNCORE_PERFEVTSEL4
Register Address: 3C5H, 949 MSR_UNCORE_PERFEVTSEL5
Register Address: 3C6H, 950 MSR_UNCORE_PERFEVTSEL6
Register Address: 3C7H, 951 MSR_UNCORE_PERFEVTSEL7
Table 2-17.  Additional MSRs in the Intel® Xe on® Processor 7500 Series
Register Address: Hex,  Decimal Register Name (Former Register Name)
Reserved. Attempt to read/write will cause #UD. Package
Register Address: 28FH, 655 IA32_MC15_CTL2
See Table 2-2. PackageTable 2-16.  Additional MSRs in the Intel® Xeon® Processor 5500 an d 3400 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-173MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 394H, 816 MSR_W_PMON_FIXED_CTR
Uncore W-box perfmon fixed counter. Package
Register Address: 395H, 817 MSR_W_PMON_FIXED_CTR_CTL
Uncore U-box perfmon fixed counter control MSR. Package
Register Address: 426H, 1062 IA32_MC9_ADDR
Register Address: 42AH, 1066 IA32_MC10_ADDR
Register Address: 42EH, 1070 IA32_MC11_ADDR
Register Address: 42FH, 1071 IA32_MC11_MISCTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-174 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 431H, 1073 IA32_MC12_STATUS
Register Address: 432H, 1074 IA32_MC12_ADDR
Register Address: 436H, 1078 IA32_MC13_ADDR
Register Address: 43AH, 1082 IA32_MC14_ADDR
Register Address: 43EH, 1086 IA32_MC15_ADDR

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-175MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 442H, 1090 IA32_MC16_ADDR
Register Address: 446H, 1094 IA32_MC17_ADDR
Register Address: 44AH, 1098 IA32_MC18_ADDR
Register Address: 44EH, 1102 IA32_MC19_ADDR
Register Address: 452H, 1106 IA32_MC20_ADDR
Register Address: 454H, 1108 IA32_MC21_CTLTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-176 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 456H, 1110 IA32_MC21_ADDR
Register Address: C00H, 3072 MSR_U_PMON_GLOBAL_CTRL
Uncore U-box perfmon global control MSR. Package
Register Address: C01H, 3073 MSR_U_PMON_GLOBAL_STATUS
Uncore U-box perfmon global status MSR. Package
Register Address: C02H, 3074 MSR_U_PMON_GLOBAL_OVF_CTRL
Uncore U-box perfmon global overflow control MSR. Package
Register Address: C10H, 3088 MSR_U_PMON_EVNT_SEL
Uncore U-box perfmon event select MSR. Package
Register Address: C11H, 3089 MSR_U_PMON_CTR
Uncore U-box perfmon counter MSR. Package
Register Address: C20H, 3104 MSR_B0_PMON_BOX_CTRL
Uncore B-box 0 perfmon loca l box control MSR. Package
Register Address: C21H, 3105 MSR_B0_PMON_BOX_STATUS
Uncore B-box 0 perfmon loca l box status MSR. Package
Register Address: C22H, 3106 MSR_B0_PMON_BOX_OVF_CTRL
Uncore B-box 0 perfmon local bo x overflow control MSR. Package
Register Address: C30H, 3120 MSR_B0_PMON_EVNT_SEL0
Uncore B-box 0 perfmon ev ent select MSR. Package
Register Address: C31H, 3121 MSR_B0_PMON_CTR0
Uncore B-box 0 pe rfmon counter MSR. Package
Register Address: C32H, 3122 MSR_B0_PMON_EVNT_SEL1
Register Address: C33H, 3123 MSR_B0_PMON_CTR1
Register Address: C34H, 3124 MSR_B0_PMON_EVNT_SEL2
Register Address: C35H, 3125 MSR_B0_PMON_CTR2
Register Address: C36H, 3126 MSR_B0_PMON_EVNT_SEL3
Uncore B-box 0 perfmon ev ent select MSR. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-177MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: C37H, 3127 MSR_B0_PMON_CTR3
Uncore B-box 0 perfmon counter MSR. Package
Register Address: C40H, 3136 MSR_S0_PMON_BOX_CTRL
Uncore S-box 0 perfmon loca l box control MSR. Package
Register Address: C41H, 3137 MSR_S0_PMON_BOX_STATUS
Uncore S-box 0 perfmon local box status MSR. Package
Register Address: C42H, 3138 MSR_S0_PMON_BOX_OVF_CTRL
Uncore S-box 0 perfmon local bo x overflow control MSR. Package
Register Address: C50H, 3152 MSR_S0_PMON_EVNT_SEL0
Uncore S-box 0 perfmon event select MSR. Package
Register Address: C51H, 3153 MSR_S0_PMON_CTR0
Uncore S-box 0 perfmon counter MSR. Package
Register Address: C52H, 3154 MSR_S0_PMON_EVNT_SEL1
Register Address: C53H, 3155 MSR_S0_PMON_CTR1
Register Address: C54H, 3156 MSR_S0_PMON_EVNT_SEL2
Register Address: C55H, 3157 MSR_S0_PMON_CTR2
Register Address: C56H, 3158 MSR_S0_PMON_EVNT_SEL3
Register Address: C57H, 3159 MSR_S0_PMON_CTR3
Register Address: C60H, 3168 MSR_B1_PMON_BOX_CTRL
Uncore B-box 1 perfmon loca l box control MSR. Package
Register Address: C61H, 3169 MSR_B1_PMON_BOX_STATUS
Uncore B-box 1 perfmon local box status MSR. Package
Register Address: C62H, 3170 MSR_B1_PMON_BOX_OVF_CTRL
Uncore B-box 1 perfmon local bo x overflow control MSR. Package
Register Address: C70H, 3184 MSR_B1_PMON_EVNT_SEL0
Uncore B-box 1 perfmon event select MSR. Package
Register Address: C71H, 3185 MSR_B1_PMON_CTR0
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C72H, 3186 MSR_B1_PMON_EVNT_SEL1
Register Address: C73H, 3187 MSR_B1_PMON_CTR1Table 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-178 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore B-box 1 pe rfmon counter MSR. Package
Register Address: C74H, 3188 MSR_B1_PMON_EVNT_SEL2
Uncore B-box 1 perfmon ev ent select MSR. Package
Register Address: C75H, 3189 MSR_B1_PMON_CTR2
Register Address: C76H, 3190 MSR_B1_PMON_EVNT_SEL3
Uncore B-box 1vperfmon ev ent select MSR. Package
Register Address: C77H, 3191 MSR_B1_PMON_CTR3
Register Address: C80H, 3120 MSR_W_PMON_BOX_CTRL
Uncore W-box perfmon loca l box control MSR. Package
Register Address: C81H, 3121 MSR_W_PMON_BOX_STATUS
Uncore W-box perfmon local box status MSR. Package
Register Address: C82H, 3122 MSR_W_PMON_BOX_OVF_CTRL
Uncore W-box perfmon local box overflow control MSR. Package
Register Address: C90H, 3136 MSR_W_PMON_EVNT_SEL0
Uncore W-box perfmon event select MSR. Package
Register Address: C91H, 3137 MSR_W_PMON_CTR0
Uncore W-box perfmon counter MSR. Package
Register Address: C92H, 3138 MSR_W_PMON_EVNT_SEL1
Register Address: C93H, 3139 MSR_W_PMON_CTR1
Register Address: C94H, 3140 MSR_W_PMON_EVNT_SEL2
Register Address: C95H, 3141 MSR_W_PMON_CTR2
Register Address: C96H, 3142 MSR_W_PMON_EVNT_SEL3
Register Address: C97H, 3143 MSR_W_PMON_CTR3
Register Address: CA0H, 3232 MSR_M0_PMON_BOX_CTRL
Uncore M-box 0 perfmon loca l box control MSR. Package
Register Address: CA1H, 3233 MSR_M0_PMON_BOX_STATUS
Uncore M-box 0 perfmon loca l box status MSR. Package
Register Address: CA2H, 3234 MSR_M0_PMON_BOX_OVF_CTRL
Uncore M-box 0 perfmon local bo x overflow control MSR. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-179MODEL-SPECIFIC REGISTERS (MSRS)
Register Addres s: CA4H, 3236 MSR_M0_PMON_TIMESTAMP
Uncore M-box 0 perfmon time stamp unit select MSR. Package
Register Addres s: CA5H, 3237 MSR_M0_PMON_DSP
Uncore M-box 0 perfmon DSP unit select MSR. Package
Register Addres s: CA6H, 3238 MSR_M0_PMON_ISS

Uncore M-box 0 perfmon ISS unit select MSR. Package
Register Addres s: CA7H, 3239 MSR_M0_PMON_MAP
Uncore M-box 0 perfmon MAP unit select MSR. Package
Register Addres s: CA8H, 3240 MSR_M0_PMON_MSC_THR
Uncore M-box 0 perfmon MIC THR select MSR. Package
Register Addres s: CA9H, 3241 MSR_M0_PMON_PGT
Uncore M-box 0 perfmon PGT unit select MSR. Package
Register Address: CAAH, 3242 MSR_M0_PMON_PLD
Uncore M-box 0 perfmon PLD unit select MSR. Package
Register Address: CABH, 3243 MSR_M0_PMON_ZDP
Uncore M-box 0 perfmon ZDP unit select MSR. Package
Register Address: CB0H, 3248 MSR_M0_PMON_EVNT_SEL0
Uncore M-box 0 perfmon event select MSR. Package
Register Address: CB1H, 3249 MSR_M0_PMON_CTR0
Uncore M-box 0 perfmon counter MSR. Package
Register Address: CB2H, 3250 MSR_M0_PMON_EVNT_SEL1
Register Address: CB3H, 3251 MSR_M0_PMON_CTR1
Register Address: CB4H, 3252 MSR_M0_PMON_EVNT_SEL2
Register Address: CB5H, 3253 MSR_M0_PMON_CTR2
Register Address: CB6H, 3254 MSR_M0_PMON_EVNT_SEL3
Register Address: CB7H, 3255 MSR_M0_PMON_CTR3
Register Address: CB8H, 3256 MSR_M0_PMON_EVNT_SEL4
Register Address: CB9H, 3257 MSR_M0_PMON_CTR4
Register Address: CBAH, 3258 MSR_M0_PMON_EVNT_SEL5Table 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-180 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore M-box 0 perfmon ev ent select MSR. Package
Register Address: CBBH, 3259 MSR_M0_PMON_CTR5
Register Address: CC0H, 3264 MSR_S1_PMON_BOX_CTRL
Uncore S-box 1 perfmon loca l box control MSR. Package
Register Address: CC1H, 3265 MSR_S1_PMON_BOX_STATUS
Uncore S-box 1 perfmon loca l box status MSR. Package
Register Address: CC2H, 3266 MSR_S1_PMON_BOX_OVF_CTRL
Uncore S-box 1 perfmon local bo x overflow control MSR. Package
Register Address: CD0H, 3280 MSR_S1_PMON_EVNT_SEL0
Uncore S-box 1 perfmon ev ent select MSR. Package
Register Address: CD1H, 3281 MSR_S1_PMON_CTR0
Uncore S-box 1 pe rfmon counter MSR. Package
Register Address: CD2H, 3282 MSR_S1_PMON_EVNT_SEL1
Register Address: CD3H, 3283 MSR_S1_PMON_CTR1
Register Address: CD4H, 3284 MSR_S1_PMON_EVNT_SEL2
Register Address: CD5H, 3285 MSR_S1_PMON_CTR2
Register Address: CD6H, 3286 MSR_S1_PMON_EVNT_SEL3
Register Address: CD7H, 3287 MSR_S1_PMON_CTR3
Register Address: CE0H, 3296 MSR_M1_PMON_BOX_CTRL
Uncore M-box 1 perfmon loca l box control MSR. Package
Register Address: CE1H, 3297 MSR_M1_PMON_BOX_STATUS
Uncore M-box 1 perfmon loca l box status MSR. Package
Register Address: CE2H, 3298 MSR_M1_PMON_BOX_OVF_CTRL
Uncore M-box 1 perfmon local bo x overflow control MSR. Package
Register Address: CE4H, 3300 MSR_M1_PMON_TIMESTAMP
Uncore M-box 1 perfmon time stamp unit select MSR. Package
Register Address: CE5H, 3301 MSR_M1_PMON_DSP
Uncore M-box 1 perfmon DSP unit select MSR. Package
Register Address: CE6H, 3302 MSR_M1_PMON_ISS
Uncore M-box 1 perfmon ISS unit select MSR. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-181MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: CE7H, 3303 MSR_M1_PMON_MAP
Uncore M-box 1 perfmon MAP unit select MSR. Package
Register Address: CE8H, 3304 MSR_M1_PMON_MSC_THR
Uncore M-box 1 perfmon MIC THR select MSR. Package
Register Address: CE9H, 3305 MSR_M1_PMON_PGT
Uncore M-box 1 perfmon PGT unit select MSR. Package
Register Address: CEAH, 3306 MSR_M1_PMON_PLD
Uncore M-box 1 perfmon PLD unit select MSR. Package
Register Address: CEBH, 3307 MSR_M1_PMON_ZDP
Uncore M-box 1 perfmon ZDP unit select MSR. Package
Register Address: CF0H, 3312 MSR_M1_PMON_EVNT_SEL0
Uncore M-box 1 perfmon event select MSR. Package
Register Address: CF1H, 3313 MSR_M1_PMON_CTR0
Uncore M-box 1 perfmon counter MSR. Package
Register Address: CF2H, 3314 MSR_M1_PMON_EVNT_SEL1
Register Address: CF3H, 3315 MSR_M1_PMON_CTR1
Register Address: CF4H, 3316 MSR_M1_PMON_EVNT_SEL2
Register Address: CF5H, 3317 MSR_M1_PMON_CTR2
Register Address: CF6H, 3318 MSR_M1_PMON_EVNT_SEL3
Register Address: CF7H, 3319 MSR_M1_PMON_CTR3
Register Address: CF8H, 3320 MSR_M1_PMON_EVNT_SEL4
Register Address: CF9H, 3321 MSR_M1_PMON_CTR4
Register Address: CFAH, 3322 MSR_M1_PMON_EVNT_SEL5
Register Address: CFBH, 3323 MSR_M1_PMON_CTR5
Register Address: D00H, 3328 MSR_C0_PMON_BOX_CTRL
Uncore C-box 0 perfmon loca l box control MSR. Package
Register Address: D01H, 3329 MSR_C0_PMON_BOX_STATUSTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-182 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 0 perfmon loca l box status MSR. Package
Register Address: D02H, 3330 MSR_C0_PMON_BOX_OVF_CTRL
Uncore C-box 0 perfmon local bo x overflow control MSR. Package
Register Address: D10H, 3344 MSR_C0_PMON_EVNT_SEL0
Uncore C-box 0 perfmon ev ent select MSR. Package
Register Address: D11H, 3345 MSR_C0_PMON_CTR0
Uncore C-box 0 pe rfmon counter MSR. Package
Register Address: D12H, 3346 MSR_C0_PMON_EVNT_SEL1
Register Address: D13H, 3347 MSR_C0_PMON_CTR1
Register Address: D14H, 3348 MSR_C0_PMON_EVNT_SEL2
Register Address: D15H, 3349 MSR_C0_PMON_CTR2
Register Address: D16H, 3350 MSR_C0_PMON_EVNT_SEL3
Register Address: D17H, 3351 MSR_C0_PMON_CTR3
Register Address: D18H, 3352 MSR_C0_PMON_EVNT_SEL4
Register Address: D19H, 3353 MSR_C0_PMON_CTR4
Register Address: D1AH, 3354 MSR_C0_PMON_EVNT_SEL5
Register Address: D1BH, 3355 MSR_C0_PMON_CTR5
Register Address: D20H, 3360 MSR_C4_PMON_BOX_CTRL
Uncore C-box 4 perfmon loca l box control MSR. Package
Register Address: D21H, 3361 MSR_C4_PMON_BOX_STATUS
Uncore C-box 4 perfmon loca l box status MSR. Package
Register Address: D22H, 3362 MSR_C4_PMON_BOX_OVF_CTRL
Uncore C-box 4 perfmon local bo x overflow control MSR. Package
Register Address: D30H, 3376 MSR_C4_PMON_EVNT_SEL0
Uncore C-box 4 perfmon ev ent select MSR. Package
Register Address: D31H, 3377 MSR_C4_PMON_CTR0
Uncore C-box 4 pe rfmon counter MSR. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-183MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D32H, 3378 MSR_C4_PMON_EVNT_SEL1
Uncore C-box 4 perfmon event select MSR. Package
Register Address: D33H, 3379 MSR_C4_PMON_CTR1
Uncore C-box 4 pe rfmon counter MSR. Package
Register Address: D34H, 3380 MSR_C4_PMON_EVNT_SEL2
Register Address: D35H, 3381 MSR_C4_PMON_CTR2
Register Address: D36H, 3382 MSR_C4_PMON_EVNT_SEL3
Register Address: D37H, 3383 MSR_C4_PMON_CTR3
Register Address: D38H, 3384 MSR_C4_PMON_EVNT_SEL4
Register Address: D39H, 3385 MSR_C4_PMON_CTR4
Register Address: D3AH, 3386 MSR_C4_PMON_EVNT_SEL5
Register Address: D3BH, 3387 MSR_C4_PMON_CTR5

Register Address: D40H, 3392 MSR_C2_PMON_BOX_CTRL
Uncore C-box 2 perfmon loca l box control MSR. Package
Register Address: D41H, 3393 MSR_C2_PMON_BOX_STATUS
Uncore C-box 2 perfmon loca l box status MSR. Package
Register Address: D42H, 3394 MSR_C2_PMON_BOX_OVF_CTRL
Uncore C-box 2 perfmon local bo x overflow control MSR. Package
Register Address: D50H, 3408 MSR_C2_PMON_EVNT_SEL0
Uncore C-box 2 perfmon event select MSR. Package
Register Address: D51H, 3409 MSR_C2_PMON_CTR0
Uncore C-box 2 pe rfmon counter MSR. Package
Register Address: D52H, 3410 MSR_C2_PMON_EVNT_SEL1
Register Address: D53H, 3411 MSR_C2_PMON_CTR1
Register Address: D54H, 3412 MSR_C2_PMON_EVNT_SEL2
Register Address: D55H, 3413 MSR_C2_PMON_CTR2Table 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-184 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D56H, 3414 MSR_C2_PMON_EVNT_SEL3
Uncore C-box 2 perfmon ev ent select MSR. Package
Register Address: D57H, 3415 MSR_C2_PMON_CTR3
Register Address: D58H, 3416 MSR_C2_PMON_EVNT_SEL4
Register Address: D59H, 3417 MSR_C2_PMON_CTR4
Register Address: D5AH, 3418 MSR_C2_PMON_EVNT_SEL5
Register Address: D5BH, 3419 MSR_C2_PMON_CTR5
Register Address: D60H, 3424 MSR_C6_PMON_BOX_CTRL
Uncore C-box 6 perfmon loca l box control MSR. Package
Register Address: D61H, 3425 MSR_C6_PMON_BOX_STATUS
Uncore C-box 6 perfmon loca l box status MSR. Package
Register Address: D62H, 3426 MSR_C6_PMON_BOX_OVF_CTRL
Uncore C-box 6 perfmon local bo x overflow control MSR. Package
Register Address: D70H, 3440 MSR_C6_PMON_EVNT_SEL0
Uncore C-box 6 perfmon ev ent select MSR. Package
Register Address: D71H, 3441 MSR_C6_PMON_CTR0
Uncore C-box 6 pe rfmon counter MSR. Package
Register Address: D72H, 3442 MSR_C6_PMON_EVNT_SEL1
Register Address: D73H, 3443 MSR_C6_PMON_CTR1
Register Address: D74H, 3444 MSR_C6_PMON_EVNT_SEL2
Register Address: D75H, 3445 MSR_C6_PMON_CTR2
Register Address: D76H, 3446 MSR_C6_PMON_EVNT_SEL3
Register Address: D77H, 3447 MSR_C6_PMON_CTR3
Register Address: D78H, 3448 MSR_C6_PMON_EVNT_SEL4
Uncore C-box 6 perfmon ev ent select MSR. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-185MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D79H, 3449 MSR_C6_PMON_CTR4
Register Address: D7AH, 3450 MSR_C6_PMON_EVNT_SEL5
Uncore C-box 6 perfmon event select MSR. Package
Register Address: D7BH, 3451 MSR_C6_PMON_CTR5
Register Address: D80H, 3456 MSR_C1_PMON_BOX_CTRL
Uncore C-box 1 perfmon loca l box control MSR. Package
Register Address: D81H, 3457 MSR_C1_PMON_BOX_STATUS
Uncore C-box 1 perfmon loca l box status MSR. Package
Register Address: D82H, 3458 MSR_C1_PMON_BOX_OVF_CTRL
Uncore C-box 1 perfmon local bo x overflow control MSR. Package
Register Address: D90H, 3472 MSR_C1_PMON_EVNT_SEL0
Uncore C-box 1 perfmon event select MSR. Package
Register Address: D91H, 3473 MSR_C1_PMON_CTR0
Uncore C-box 1 pe rfmon counter MSR. Package
Register Address: D92H, 3474 MSR_C1_PMON_EVNT_SEL1
Register Address: D93H, 3475 MSR_C1_PMON_CTR1
Register Address: D94H, 3476 MSR_C1_PMON_EVNT_SEL2
Register Address: D95H, 3477 MSR_C1_PMON_CTR2
Register Address: D96H, 3478 MSR_C1_PMON_EVNT_SEL3
Register Address: D97H, 3479 MSR_C1_PMON_CTR3
Register Address: D98H, 3480 MSR_C1_PMON_EVNT_SEL4
Register Address: D99H, 3481 MSR_C1_PMON_CTR4
Register Address: D9AH, 3482 MSR_C1_PMON_EVNT_SEL5
Register Address: D9BH, 3483 MSR_C1_PMON_CTR5
Register Address: DA0H, 3488 MSR_C5_PMON_BOX_CTRLTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-186 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 5 perfmon loca l box control MSR. Package
Register Address: DA1H, 3489 MSR_C5_PMON_BOX_STATUS
Uncore C-box 5 perfmon loca l box status MSR. Package
Register Address: DA2H, 3490 MSR_C5_PMON_BOX_OVF_CTRL
Uncore C-box 5 perfmon local bo x overflow control MSR. Package
Register Address: DB0H, 3504 MSR_C5_PMON_EVNT_SEL0
Uncore C-box 5 perfmon ev ent select MSR. Package
Register Address: DB1H, 3505 MSR_C5_PMON_CTR0
Uncore C-box 5 pe rfmon counter MSR. Package
Register Address: DB2H, 3506 MSR_C5_PMON_EVNT_SEL1
Register Address: DB3H, 3507 MSR_C5_PMON_CTR1
Register Address: DB4H, 3508 MSR_C5_PMON_EVNT_SEL2
Register Address: DB5H, 3509 MSR_C5_PMON_CTR2
Register Address: DB6H, 3510 MSR_C5_PMON_EVNT_SEL3
Register Address: DB7H, 3511 MSR_C5_PMON_CTR3
Register Address: DB8H, 3512 MSR_C5_PMON_EVNT_SEL4
Register Address: DB9H, 3513 MSR_C5_PMON_CTR4
Register Address: DBAH, 3514 MSR_C5_PMON_EVNT_SEL5
Register Address: DBBH, 3515 MSR_C5_PMON_CTR5
Register Address: DC0H, 3520 MSR_C3_PMON_BOX_CTRL
Uncore C-box 3 perfmon loca l box control MSR. Package
Register Address: DC1H, 3521 MSR_C3_PMON_BOX_STATUS
Uncore C-box 3 perfmon loca l box status MSR. Package
Register Address: DC2H, 3522 MSR_C3_PMON_BOX_OVF_CTRL
Uncore C-box 3 perfmon local bo x overflow control MSR. Package
Register Address: DD0H, 3536 MSR_C3_PMON_EVNT_SEL0
Uncore C-box 3 perfmon ev ent select MSR. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-187MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DD1H, 3537 MSR_C3_PMON_CTR0
Uncore C-box 3 pe rfmon counter MSR. Package
Register Address: DD2H, 3538 MSR_C3_PMON_EVNT_SEL1
Uncore C-box 3 perfmon event select MSR. Package
Register Address: DD3H, 3539 MSR_C3_PMON_CTR1
Register Address: DD4H, 3540 MSR_C3_PMON_EVNT_SEL2
Register Address: DD5H, 3541 MSR_C3_PMON_CTR2
Register Address: DD6H, 3542 MSR_C3_PMON_EVNT_SEL3
Register Address: DD7H, 3543 MSR_C3_PMON_CTR3
Register Address: DD8H, 3544 MSR_C3_PMON_EVNT_SEL4
Register Address: DD9H, 3545 MSR_C3_PMON_CTR4
Register Address: DDAH, 3546 MSR_C3_PMON_EVNT_SEL5
Register Address: DDBH, 3547 MSR_C3_PMON_CTR5
Register Address: DE0H, 3552 MSR_C7_PMON_BOX_CTRL
Uncore C-box 7 perfmon loca l box control MSR. Package
Register Address: DE1H, 3553 MSR_C7_PMON_BOX_STATUS
Uncore C-box 7 perfmon loca l box status MSR. Package
Register Address: DE2H, 3554 MSR_C7_PMON_BOX_OVF_CTRL
Uncore C-box 7 perfmon local bo x overflow control MSR. Package
Register Address: DF0H, 3568 MSR_C7_PMON_EVNT_SEL0
Uncore C-box 7 perfmon event select MSR. Package
Register Address: DF1H, 3569 MSR_C7_PMON_CTR0
Uncore C-box 7 pe rfmon counter MSR. Package
Register Address: DF2H, 3570 MSR_C7_PMON_EVNT_SEL1

Register Address: DF3H, 3571 MSR_C7_PMON_CTR1
Register Address: DF4H, 3572 MSR_C7_PMON_EVNT_SEL2Table 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-188 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 7 perfmon ev ent select MSR. Package
Register Address: DF5H, 3573 MSR_C7_PMON_CTR2
Register Address: DF6H, 3574 MSR_C7_PMON_EVNT_SEL3
Register Address: DF7H, 3575 MSR_C7_PMON_CTR3
Register Address: DF8H, 3576 MSR_C7_PMON_EVNT_SEL4
Register Address: DF9H, 3577 MSR_C7_PMON_CTR4
Register Address: DFAH, 3578 MSR_C7_PMON_EVNT_SEL5
Register Address: DFBH, 3579 MSR_C7_PMON_CTR5
Register Address: E00H, 3584 MSR_R0_PMON_BOX_CTRL
Uncore R-box 0 perfmon loca l box control MSR. Package
Register Address: E01H, 3585 MSR_R0_PMON_BOX_STATUS
Uncore R-box 0 perfmon loca l box status MSR. Package
Register Address: E02H, 3586 MSR_R0_PMON_BOX_OVF_CTRL
Uncore R-box 0 perfmon local bo x overflow control MSR. Package
Register Address: E04H, 3588 MSR_R0_PMON_IPERF0_P0
Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR. Package
Register Address: E05H, 3589 MSR_R0_PMON_IPERF0_P1
Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR. Package
Register Address: E06H, 3590 MSR_R0_PMON_IPERF0_P2
Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR. Package
Register Address: E07H, 3591 MSR_R0_PMON_IPERF0_P3
Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR. Package
Register Address: E08H, 3592 MSR_R0_PMON_IPERF0_P4
Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR. Package
Register Address: E09H, 3593 MSR_R0_PMON_IPERF0_P5
Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR. Package
Register Address: E0AH, 3594 MSR_R0_PMON_IPERF0_P6
Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR. Package
Register Address: E0BH, 3595 MSR_R0_PMON_IPERF0_P7
Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-189MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E0CH, 3596 MSR_R0_PMON_QLX_P0
Uncore R-box 0 perfmon QLX unit Port 0 select MSR. Package
Register Address: E0DH, 3597 MSR_R0_PMON_QLX_P1
Uncore R-box 0 perfmon QLX unit Port 1 select MSR. Package
Register Address: E0EH, 3598 MSR_R0_PMON_QLX_P2
Uncore R-box 0 perfmon QLX unit Port 2 select MSR. Package
Register Address: E0FH, 3599 MSR_R0_PMON_QLX_P3
Uncore R-box 0 perfmon QLX unit Port 3 select MSR. Package
Register Address: E10H, 3600 MSR_R0_PMON_EVNT_SEL0
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E11H, 3601 MSR_R0_PMON_CTR0
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E12H, 3602 MSR_R0_PMON_EVNT_SEL1
Register Address: E13H, 3603 MSR_R0_PMON_CTR1
Register Address: E14H, 3604 MSR_R0_PMON_EVNT_SEL2
Register Address: E15H, 3605 MSR_R0_PMON_CTR2
Register Address: E16H, 3606 MSR_R0_PMON_EVNT_SEL3
Register Address: E17H, 3607 MSR_R0_PMON_CTR3
Register Address: E18H, 3608 MSR_R0_PMON_EVNT_SEL4
Register Address: E19H, 3609 MSR_R0_PMON_CTR4
Register Address: E1AH, 3610 MSR_R0_PMON_EVNT_SEL5
Register Address: E1BH, 3611 MSR_R0_PMON_CTR5
Register Address: E1CH, 3612 MSR_R0_PMON_EVNT_SEL6
Register Address: E1DH, 3613 MSR_R0_PMON_CTR6
Register Address: E1EH, 3614 MSR_R0_PMON_EVNT_SEL7Table 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-190 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore R-box 0 perfmon ev ent select MSR. Package
Register Address: E1FH, 3615 MSR_R0_PMON_CTR7
Register Address: E20H, 3616 MSR_R1_PMON_BOX_CTRL
Uncore R-box 1 perfmon loca l box control MSR. Package
Register Address: E21H, 3617 MSR_R1_PMON_BOX_STATUS
Uncore R-box 1 perfmon loca l box status MSR. Package
Register Address: E22H, 3618 MSR_R1_PMON_BOX_OVF_CTRL
Uncore R-box 1 perfmon local bo x overflow control MSR. Package
Register Address: E24H, 3620 MSR_R1_PMON_IPERF1_P8
Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR. Package
Register Address: E25H, 3621 MSR_R1_PMON_IPERF1_P9
Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR. Package
Register Address: E26H, 3622 MSR_R1_PMON_IPERF1_P10
Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR. Package
Register Address: E27H, 3623 MSR_R1_PMON_IPERF1_P11
Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR. Package
Register Address: E28H, 3624 MSR_R1_PMON_IPERF1_P12
Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR. Package
Register Address: E29H, 3625 MSR_R1_PMON_IPERF1_P13
Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR. Package
Register Address: E2AH, 3626 MSR_R1_PMON_IPERF1_P14
Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR. Package
Register Address: E2BH, 3627 MSR_R1_PMON_IPERF1_P15
Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR. Package
Register Address: E2CH, 3628 MSR_R1_PMON_QLX_P4
Uncore R-box 1 perfmon QLX uni t Port 4 select MSR. Package
Register Address: E2DH, 3629 MSR_R1_PMON_QLX_P5
Uncore R-box 1 perfmon QLX uni t Port 5 select MSR. Package
Register Address: E2EH, 3630 MSR_R1_PMON_QLX_P6
Uncore R-box 1 perfmon QLX uni t Port 6 select MSR. Package
Register Address: E2FH, 3631 MSR_R1_PMON_QLX_P7
Uncore R-box 1 perfmon QLX uni t Port 7 select MSR. Package
Register Address: E30H, 3632 MSR_R1_PMON_EVNT_SEL8
Uncore R-box 1 perfmon ev ent select MSR. Package
Register Address: E31H, 3633 MSR_R1_PMON_CTR8
Uncore R-box 1 perfmon counter MSR. PackageTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-191MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E32H, 3634 MSR_R1_PMON_EVNT_SEL9
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E33H, 3635 MSR_R1_PMON_CTR9
Uncore R-box 1 perfmon counter MSR. Package
Register Address: E34H, 3636 MSR_R1_PMON_EVNT_SEL10
Register Address: E35H, 3637 MSR_R1_PMON_CTR10
Register Address: E36H, 3638 MSR_R1_PMON_EVNT_SEL11
Register Address: E37H, 3639 MSR_R1_PMON_CTR11
Register Address: E38H, 3640 MSR_R1_PMON_EVNT_SEL12
Register Address: E39H, 3641 MSR_R1_PMON_CTR12
Register Address: E3AH, 3642 MSR_R1_PMON_EVNT_SEL13
Register Address: E3BH, 3643 MSR_R1_PMON_CTR13
Uncore R-box 1perfmon counter MSR. Package
Register Address: E3CH, 3644 MSR_R1_PMON_EVNT_SEL14
Register Address: E3DH, 3645 MSR_R1_PMON_CTR14
Register Address: E3EH, 3646 MSR_R1_PMON_EVNT_SEL15
Register Address: E3FH, 3647 MSR_R1_PMON_CTR15
Register Address: E45H, 3653 MSR_B0_PMON_MATCH
Uncore B-box 0 perfmon local box match MSR. Package
Register Address: E46H, 3654 MSR_B0_PMON_MASK
Uncore B-box 0 perfmon local box mask MSR. Package
Register Address: E49H, 3657 MSR_S0_PMON_MATCH
Uncore S-box 0 perfmon local box match MSR. Package
Register Address: E4AH, 3658 MSR_S0_PMON_MASK
Uncore S-box 0 perfmon local box mask MSR. Package
Register Address: E4DH, 3661 MSR_B1_PMON_MATCHTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description Scope2-192 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.9 MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES BASED ON 
WESTMERE MICROARCHITECTURE

The Intel® Xeon® Processor 5600 Series is based on Westmere microarchitecture and supports the MSR interfaces 
listed in Table 2-15, Table 2-16, plus additional MSRs liste d in Table 2-18. These MSRs apply to the Intel Core i7, i5, 
and i3 processor family with a CPUI D Signature DisplayFamily_DisplayModel value of 06_25H or 06_2CH; see Table 
2-1.Uncore B-box 1 perfmon lo cal box match MSR. Package
Register Address: E4EH, 3662 MSR_B1_PMON_MASK
Uncore B-box 1 perfmon lo cal box mask MSR. Package
Register Address: E54H, 3668 MSR_M0_PMON_MM_CONFIG
Uncore M-box 0 perfmon local box addr ess match/mask config MSR. Package
Register Address: E55H, 3669 MSR_M0_PMON_ADDR_MATCH
Uncore M-box 0 perfmon local box address match MSR. Package
Register Address: E56H, 3670 MSR_M0_PMON_ADDR_MASK
Uncore M-box 0 perfmon local box address mask MSR. Package
Register Address: E59H, 3673 MSR_S1_PMON_MATCH
Uncore S-box 1 perfmon lo cal box match MSR. Package
Register Address: E5AH, 3674 MSR_S1_PMON_MASK
Uncore S-box 1 perfmon lo cal box mask MSR. Package
Register Address: E5CH, 3676 MSR_M1_PMON_MM_CONFIG
Uncore M-box 1 perfmon local box addr ess match/mask config MSR. Package
Register Address: E5DH, 3677 MSR_M1_PMON_ADDR_MATCH
Uncore M-box 1 perfmon local box address match MSR. Package
Register Address: E5EH, 3678 MSR_M1_PMON_ADDR_MASK
Uncore M-box 1 perfmon local box address mask MSR. Package
Table 2-18.  Additional MSRs Supported by Intel®  Processors Based on We stmere Microarchitecture 
Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.CoreTable 2-17.  Additional MSRs in the Inte l® Xeon® Processor 75 00 Series (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-193MODEL-SPECIFIC REGISTERS (MSRS)
2.10 MSRS IN THE INTEL® XEON® PROC ESSOR E7 FAMILY BASED ON WESTMERE 
The Intel® Xeon® Processor E7 Family is based on the Westmere microarchitecture and supports the MSR inter-
faces listed in Table 2-15 (except MSR address 1ADH), Tabl e 2-16, plus additional MSRs listed in Table 2-19. These 
processors have a CPUID Signature Disp layFamily_DisplayModel value of 06_2FH.1:0 AES Configuration (RW-L) 
set availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.Note, AES instruction set is not available if read is unsuccessful. If the 
configuration is not 01b, AES instructions can be mis-configured if a 
privileged agent unintentionally writes 11b.
See Table 2-2. PackageTable 2-18.  Additional MSRs Supported by Intel® Proc essors Based on Westmere Microarchitecture  (Contd.)
Register Information / Bit Fields Bit Description Scope2-194 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-19.  Additional MSRs Supported by the Intel® Xeon® Processor E7 Family
Upon a successful read of this MSR, the configuration of AES instruction set 
availability is as follows:
Otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If the 
Offcore Response Event Sele ct Register (R/W) Thread
Register Address: F40H, 3904 MSR_C8_PMON_BOX_CTRL
Uncore C-box 8 perfmon loca l box control MSR. Package
Register Address: F41H, 3905 MSR_C8_PMON_BOX_STATUS
Uncore C-box 8 perfmon loca l box status MSR. Package
Register Address: F42H, 3906 MSR_C8_PMON_BOX_OVF_CTRL
Uncore C-box 8 perfmon local bo x overflow control MSR. Package
Register Address: F50H, 3920 MSR_C8_PMON_EVNT_SEL0
Uncore C-box 8 perfmon ev ent select MSR. Package
Register Address: F51H, 3921 MSR_C8_PMON_CTR0
Uncore C-box 8 pe rfmon counter MSR. Package
Register Address: F52H, 3922 MSR_C8_PMON_EVNT_SEL1
Register Address: F53H, 3923 MSR_C8_PMON_CTR1
Register Address: F54H, 3924 MSR_C8_PMON_EVNT_SEL2
Register Address: F55H, 3925 MSR_C8_PMON_CTR2
Register Address: F56H, 3926 MSR_C8_PMON_EVNT_SEL3
Uncore C-box 8 perfmon ev ent select MSR. PackageVol. 4 2-195MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: F57H, 3927 MSR_C8_PMON_CTR3
Register Address: F58H, 3928 MSR_C8_PMON_EVNT_SEL4
Uncore C-box 8 perfmon event select MSR. Package
Register Address: F59H, 3929 MSR_C8_PMON_CTR4
Register Address: F5AH, 3930 MSR_C8_PMON_EVNT_SEL5
Register Address: F5BH, 3931 MSR_C8_PMON_CTR5
Register Address: FC0H, 4032 MSR_C9_PMON_BOX_CTRL
Uncore C-box 9 perfmon loca l box control MSR. Package
Register Address: FC1H, 4033 MSR_C9_PMON_BOX_STATUS
Uncore C-box 9 perfmon loca l box status MSR. Package
Register Address: FC2H, 4034 MSR_C9_PMON_BOX_OVF_CTRL
Uncore C-box 9 perfmon local bo x overflow control MSR. Package
Register Addres s: FD0H, 4048 MSR_C9_PMON_EVNT_SEL0
Uncore C-box 9 perfmon event select MSR. Package
Register Addres s: FD1H, 4049 MSR_C9_PMON_CTR0
Uncore C-box 9 pe rfmon counter MSR. Package
Register Addres s: FD2H, 4050 MSR_C9_PMON_EVNT_SEL1
Register Addres s: FD3H, 4051 MSR_C9_PMON_CTR1
Register Addres s: FD4H, 4052 MSR_C9_PMON_EVNT_SEL2
Register Addres s: FD5H, 4053 MSR_C9_PMON_CTR2
Register Addres s: FD6H, 4054 MSR_C9_PMON_EVNT_SEL3
Register Addres s: FD7H, 4055 MSR_C9_PMON_CTR3
Register Addres s: FD8H, 4056 MSR_C9_PMON_EVNT_SEL4
Register Addres s: FD9H, 4057 MSR_C9_PMON_CTR4
Register Address: FDAH, 4058 MSR_C9_PMON_EVNT_SEL5Table 2-19.  Additional MSRs Supported by the Intel® Xeon® Processor E7 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-196 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.11 MSRS IN THE INTEL® PROCESSO R FAMILY BASED ON SANDY BRIDGE 
Table 2-20 lists model-specific registers (MSRs) that are common to the Intel® processor family based on Sandy 
Bridge microarchitecture. These processors have a CP UID Signature DisplayFamily_DisplayModel value of 06_2AH 
or 06_2DH; see Table 2-1. Additional MSRs sp ecific to processors with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_2AH are listed in Table 2-21.Uncore C-box 9 perfmon ev ent select MSR. Package
Register Address: FDBH, 4059 MSR_C9_PMON_CTR5
Table 2-20.  MSRs Supported by  Intel® Processors Based on Sandy Bridge Microarchitecture

See Section 18.17, “Time-Stamp Counter,” and see Table 2-2. Thread
Count SMIs.
1 Enable VMX Inside SMX Operation (R/WL) 
2 Enable VMX Outside SMX Operation (R/WL) Table 2-19.  Additional MSRs Supported by the Intel® Xeon® Processor E7 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-197MODEL-SPECIFIC REGISTERS (MSRS)
14:8 SENTER Local Functions Enables (R/WL) 
15 SENTER Global Functions Enable (R/WL) 
Performance Counter Register 
Performance Counter Register (if core not shared by threads) Core
Register Address: C6H, 198 IA32_PMC5
This is the ratio of the frequency th at invariant TSC runs at. Frequency = 
ratio * 100 MHz.Package
mode is disabled.PackageTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-198 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
When set to 1, indicate s that TDP Limit for Turbo mode is programmable. 
When set to 0, indicate s TDP Limit for Turbo mode is not programmable.Package
operate, in un its of 100MHz.Package
least power) for the package. The default is set as factory-configured package C-state limit.
000b: C0/C1 (no package C-sate support)001b: C2
010b: C6 no retention
011b: C6 retention100b: C7
101b: C7s
111: No package C-state limitNote: This field cannot be used to limit package C-state to C3.
9:3 Reserved.10 I/O MWAIT Redirection Enable (R/W) 
When set, will map IO_read instructions  sent to IO regi ster specified by 
24:16 Reserved.
25 C3 State Auto Demo tion Enable (R/W) 
26 C1 State Auto Demo tion Enable (R/W) 
When set, the processor wi ll conditionally demote C3 /C6/C7 requests to C1 
27 Enable C3 Undemotion (R/W) 
When set, enables undemo tion from demoted C3.Table 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-199MODEL-SPECIFIC REGISTERS (MSRS)
28 Enable C1 Undemotion (R/W) 
When set, enables undemo tion from demoted C1.
63:29 Reserved.
MWAIT Redirection is enabled, reads to this address will be consumed by 
the power management logic and decoded to MWAIT instructions. When IO 
18:16 C-State Range (R/W) 
Actual Performance Frequency Clock Count (R/W)
See Table 2-2. ThreadTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-200 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
0R I P V
When set, bit indicates that the instruction addressed by the instruction 
pointer pushed on the stack (when th e machine check wa s generated) can 
be used to restart the program. If cleared, the program cannot be reliably 
1E I P V
pointer pushed on the stack (when the machine check was generated) is directly associated with the error.
2M C I P
Register Address: 18AH, 394 IA32_PERFEVTSEL4
See Table 2-2. If CPUID.0AH:EAX[15:8] > 4. Core
Register Address: 18BH, 395 IA32_PERFEVTSEL5
See Table 2-2. If CPUID.0AH:EAX[15:8] > 5. Core
See Table 2-2. If CPUID.0AH:EAX[15:8] > 6. Core

2M C I P
See Table 2-2. If CPUID.0AH:EAX[15:8] > 7. Core
Register Address: 198H, 408 IA32_PERF_STATUSTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-201MODEL-SPECIFIC REGISTERS (MSRS)
Performance Status Package
47:32 Core Voltage (R/O)
P-state core voltage can be computed by
MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
See Table 2-2.IA32_CLOCK_MODULATION MSR was origin ally named IA32_THERM_CONTROL MSR.Thread
3:0 On demand Clock Modulation Duty Cycle (R/W)
In 6.25% increment.
0 Thermal Status (R/O) 
1 Thermal Status Log (R/WC0) 
2 PROTCHOT # or FORCEPR# Status (R/O) 
3 PROTCHOT # or FORCEPR# Log (R/WC0) 
4 Critical Temperature Status (R/O) 
5 Critical Temperature Status Log (R/WC0) 
6 Thermal Threshold #1 Status (R/O) 
See Table 2-2.Table 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-202 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
7 Thermal Threshold #1 Log (R/WC0) 
8 Thermal Threshold #2 Status (R/O) 
9 Thermal Threshold #2 Log (R/WC0) 
10 Power Limitation Status (R/O) 
11 Power Limitation Log (R/WC0) 
15:12 Reserved.22:16 Digital Readout (R/O) 
30:27 Resolution in Degrees Celsius (R/O) 
31 Reading Valid (R/O) 
0F a s t - S t r i n g s  E n a b l e  
6:1 Reserved.
10:8 Reserved
21:19 Reserved.Table 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-203MODEL-SPECIFIC REGISTERS (MSRS)
available in the processor. If the power-on default value is 0, turbo mode is not available.Package
Temperature Target Unique
Register Address: 1A6H, 422 MSR_OFFCORE_RSP_0Table 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-204 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Various model specific features enumeration. See http://biosbits.org.
See Section 18.9.2, “Filtering  of Last Bran ch Records.”Thread
0C P L _ E Q _ 0
1 CPL_NEQ_02J C C
3 NEAR_REL_CALL
4N E A R _ I N D _ C A L L5 NEAR_RET
6N E A R _ I N D _ J M P
7 NEAR_REL_JMP8 FAR_BRANCH
0 LBR: Last Branch Record
1B T F
5:2 Reserved.6 TR: Branch Trace
7 BTS: Log Branch Trace Message to BTS buffer
8B T I N TTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-205MODEL-SPECIFIC REGISTERS (MSRS)
9B T S _ O F F _ O S
10 BTS_OFF_USER
11 FREEZE_LBR_ON_PMI12 FREEZE_PERFMON_ON_PMI
13 ENABLE_UNCORE_PMI
14 FREEZE_WHILE_SMM63:15 Reserved.
Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was 
exception that was generated or the last interrupt that was handled. Thread
See http://biosbits.org. Core
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4Table 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-206 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)

Register Information / Bit Fields Bit Description ScopeVol. 4 2-207MODEL-SPECIFIC REGISTERS (MSRS)
Always 0 (CMCI not supported). Package
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2 and Section 18.4.1, “IA32_DEBUGCTL MSR.” Thread
6 PEBS Record Format. Table 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-208 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.” 0O v f _ P M C 0  T h r e a d
1O v f _ P M C 1  T h r e a d
2O v f _ P M C 2  T h r e a d3O v f _ P M C 3  T h r e a d
4 Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4) Core
5 Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5) Core6 Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6) Core
7 Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7) Core
31:8 Reserved.32 Ovf_FixedCtr0 Thread
33 Ovf_FixedCtr1 Thread
34 Ovf_FixedCtr2 Thread60:35 Reserved.
61 Ovf_Uncore Thread
62 Ovf_BufDSSAVE Thread63 CondChgd Thread
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.” Thread0 Set 1 to enable PMC0 to count. Thread
1 Set 1 to enable PMC1 to count. Thread
2 Set 1 to enable PMC2 to count. Thread3 Set 1 to enable PMC3 to count. Thread
4 Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > 4). Core
5 Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > 5). Core6 Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > 6). Core
7 Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > 7). CoreTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-209MODEL-SPECIFIC REGISTERS (MSRS)
31:8 Reserved.
32 Set 1 to enable Fixe dCtr0 to count. Thread
33 Set 1 to enable Fixe dCtr1 to count. Thread
34 Set 1 to enable Fixe dCtr2 to count. Thread
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.”
0 Set 1 to clear Ovf_PMC0. Thread
1 Set 1 to clear Ovf_PMC1. Thread2 Set 1 to clear Ovf_PMC2. Thread3 Set 1 to clear Ovf_PMC3. Thread
4 Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). Core
5 Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). Core6 Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). Core
7 Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). Core
31:8 Reserved.32 Set 1 to clear Ovf_FixedCtr0. Thread
33 Set 1 to clear Ovf_FixedCtr1. Thread
34 Set 1 to clear Ovf_FixedCtr2. Thread60:35 Reserved.
61 Set 1 to clear Ovf_Uncore. Thread
62 Set 1 to clear Ovf_BufDSSAVE. Thread63 Set 1 to clear CondChgd. Thread
See Section 20.3.1.1.1, “Processor Event Based Sampling (PEBS).” Thread0 Enable PEBS on IA32_PMC0. (R/W)
1 Enable PEBS on IA32_PMC1. (R/W)
2 Enable PEBS on IA32_PMC2. (R/W)3 Enable PEBS on IA32_PMC3. (R/W)
32 Enable Load Latency on IA32_PMC0. (R/W)33 Enable Load Latency on IA32_PMC1. (R/W)
34 Enable Load Latency on IA32_PMC2. (R/W)
35 Enable Load Latency on IA32_PMC3. (R/W)62:36 Reserved.
63 Enable Precise Store (R/W)
Register Address: 3F6H, 1014 MSR_PEBS_LD_LATTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-210 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
15:0 Minimum threshold late ncy value of tagged load  operation that will be 
Value since last rese t that this package is in pr ocessor-specific C3 states. 
Value since last rese t that this package is in pr ocessor-specific C6 states. 
Value since last rese t that this package is in pr ocessor-specific C7 states. 
Value since last reset that this core is  in processor-specific C3 states. Count 
Value since last reset that this core is  in processor-specific C6 states. Count 
Register Address: 3FEH, 1022 MSR_CORE_C7_RESIDENCY
63:0 CORE C7 Residency Counter (R/O)
Value since last reset that this core is  in processor-specific C7 states. Count 
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” CoreTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-211MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Core

0 PCU Hardware Error (R/W) 
When set, enables si gnaling of PCU hardware detected errors. 
1 PCU Controller Error (R/W) 
When set, enables si gnaling of PCU controller detected errors.
2 PCU Firmware Error (R/W) 
When set, enables signaling of PCU firmware detected errors.Table 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-212 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Capability Reporting Register of VMCS Field Enumeration (R/O) 
See Appendix A.3, “VM-Execution Controls.”ThreadTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-213MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2Thread
Register Address: 60AH, 1546 MSR_PKGC3_IRTLTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-214 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
limit. The following time unit encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns101b: 33554432 ns
Register Address: 60BH, 1547 MSR_PKGC6_IRTL
Package C6 Interrupt Response Limit (R/W) 
This MSR defines the budget allocated for the package to exit  from a C6 to a C0 state, where an interr upt request can 
be delivered to the core and serviced. Additional core-exit latency may be applicable depending on the actual C-state 
the core is in. 
put into a package C6 state. 
000b: 1 ns001b: 32 ns
011b: 32768 ns100b: 1048576 ns
101b: 33554432 ns
processor for package C-sate management. Table 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-215MODEL-SPECIFIC REGISTERS (MSRS)
Value since last reset that  this package is in processor-specific C2 states. 
PKG RAPL Parameters (R/W) 
PP0 RAPL Power Limit Control (R/W) 

One of sixteen pairs of la st branch record re gisters on the last branch record stac k. This part of the stack contains 
• Section 18.9.1 and record format in Section 18.4.8.1.Thread
See description of MSR_LASTBRANCH_0_FROM_IP.ThreadTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-216 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6C2H, 1730 MSR_LASTBRANCH_2_TO_IPTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-217MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 5 To IP (R/W)
Last Branch Record 6 To IP (R/W)
Last Branch Record 7 To IP (R/W)
Last Branch Record 8 To IP (R/W)
Last Branch Record 9 To IP (R/W)
Register Address: 6CFH, 1743 MSR_LASTBRAN CH_15_TO_IPTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-218 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.11.1  MSRs in the 2nd Genera tion Intel® Core™ Processor Fa mily Based on Sandy Bridge 
Table 2-21 and Table 2-22 list model-specific registers (M SRs) that are specific to the 2nd generation Intel® Core™ 
processor family based on the Sandy Bridge microarc hitecture. These processors have a CPUID Signature 
DisplayFamily_DisplayModel value of 06_2AH; see Table 2-1. Last Branch Record  15 To IP (R/W)
Register Address: 802H −83FH, 2050 −
2111X2APIC MSRs
Swap Target of BASE Address of GS (R/W)
AUXILIARY TSC Signature (R/W)
See Table 2-2 and Section 18.17.2, “IA32_ TSC_AUX Register and RDTSCP Support.” ThreadTable 2-20.  MSRs Supported by Intel® Processors  Based on Sandy Bridge Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-219MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-21.  MSRs Supported by the 2nd Generation Inte l® Core™ Processors (Sandy  Bridge Microarchitecture)
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.Package
Maximum turbo ratio limi t of 1 core active. Package
Maximum turbo ratio limi t of 2 core active. Package
Maximum turbo ratio limi t of 3 core active.Package
Maximum turbo ratio limi t of 4 core active.Package
Register Address: 60CH, 1548 MSR_PKGC7_IRTL
Package C7 Interrupt Response Limit (R/W) 
This MSR defines the budget allocated for the package to exit  from a C7 to a C0 state, where interrupt request can be 
delivered to the core and serviced. Additional core-exit late ncy may be applicable depending on the actual C-state the 
core is in. 
Note: C-state values are processor specific C-state code na mes, unrelated to MWAIT exte nsion C-state parameters or 
Specifies the limit that should be used  to decide if the package should be 
Specifies the encoding value of time unit of the interr upt response time 
limit. The following time un it encodings are supported:
Indicates whether the values in bits 12:0 are valid and can be used by 
the processor for package C-sate management. 
PP0 Energy Status (R/O)

core is in. 
Register Address: 63AH, 1594 MSR_PP0_POLICY2-220 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-22 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel 
value of 06_2AH.PP0 Balance Policy (R/W) 
Register Address: 640H, 1600 MSR_PP1_POWER_LIMIT
PP1 RAPL Power Limit Control (R/W) 
Register Address: 642H, 1602 MSR_PP1_POLICY
PP1 Balance Policy (R/W) 
See Table 2-20, Table 2-21, and Table 2-22 for MSR defini tions applicable to processors with a CPUID Signature 
DisplayFamily_DisplayMod el value of 06_2AH. 
Table 2-22.  Uncore PMU MSRs Supported by  2nd Generation Intel® Core™ Processors 
Register Address: 391H, 913 MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control Package
0 Slice 0 select.1 Slice 1 select.
2 Slice 2 select.
3 Slice 3 select.4 Slice 4 select.
18:5 Reserved.
29 Enable all uncore counters.30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
Register Address: 392H, 914 MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status Package
0 Fixed counter overflowed.1 An ARB counter overflowed.
2 Reserved.
3 A CBox counter overflowed (on any slice).63:4 Reserved.Table 2-21.  MSRs Supported by the 2nd Generation Inte l® Core™ Processors (Sandy Bridge Microarchitecture) 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-221MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 394H, 916 MSR_UNC_PERF _FIXED_CTRL
Uncore Fixed Counter Control (R/W) Package
19:0 Reserved.20 Enable overflow propagation.
22 Enable counting.63:23 Reserved.
Register Address: 395H, 917 MSR_UNC_PERF _FIXED_CTR
Uncore Fixed Counter Package
47:0 Current count.63:48 Reserved.
Register Address: 396H, 918 MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O) Package3:0 Report the number of C-Box units with performance counters, including 
processor cores and processor graphics.
Register Address: 3B0H, 946 MSR_UNC_ARB_PERFCTR0
Uncore Arb Unit, Performance Counter 0 Package
Register Address: 3B1H, 947 MSR_UNC_ARB_PERFCTR1
Uncore Arb Unit, Performance Counter 1 Package
Register Address: 3B2H, 944 MSR_UNC_ARB_PERFEVTSEL0
Uncore Arb Unit, Counter 0 Event Select MSR Package
Register Address: 3B3H, 945 MSR_UNC_ARB_PERFEVTSEL1
Uncore Arb unit, Counter 1 Event Select MSR Package
Register Address: 700H, 1792 MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR Package
Register Address: 701H, 1793 MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR Package
Register Address: 702H, 1794 MSR_UNC_CBO_0_PERFEVTSEL2
Uncore C-Box 0, Counter 2 Event Select MSR Package
Register Address: 703H, 1795 MSR_UNC_CBO_0_PERFEVTSEL3
Uncore C-Box 0, Counter 3 Event Select MSR Package
Register Address: 705H, 1797 MSR_UNC_CBO_0_UNIT_STATUS
Uncore C-Box 0, Unit Status for Counter 0-3 Package
Register Address: 706H, 1798 MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0 Package
Register Address: 707H, 1799 MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1 PackageTable 2-22.  Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors  (Contd.)
Register Information / Bit Fields Bit Description Scope2-222 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 708H, 1800 MSR_UNC_CBO_0_PERFCTR2
Uncore C-Box 0, Performance Counter 2 Package
Register Address: 709H, 1801 MSR_UNC_CBO_0_PERFCTR3
Uncore C-Box 0, Performance Counter 3 Package
Register Address: 710H, 1808 MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR Package
Register Address: 711H, 1809 MSR_UNC_CBO_1_PERFEVTSEL1
Uncore C-Box 1, Counter 1 Event Select MSR Package
Register Address: 712H, 1810 MSR_UNC_CBO_1_PERFEVTSEL2
Uncore C-Box 1, Counter 2 Event Select MSR Package
Register Address: 713H, 1811 MSR_UNC_CBO_1_PERFEVTSEL3
Uncore C-Box 1, Counter 3 Event Select MSR Package
Register Address: 715H, 1813 MSR_UNC_CBO_1_UNIT_STATUS
Uncore C-Box 1, Unit Status for Counter 0-3 Package
Register Address: 716H, 1814 MSR_UNC_CBO_1_PERFCTR0
Uncore C-Box 1, Performance Counter 0 Package
Register Address: 717H, 1815 MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1 Package
Register Address: 718H, 1816 MSR_UNC_CBO_1_PERFCTR2
Uncore C-Box 1, Performance Counter 2 Package
Register Address: 719H, 1817 MSR_UNC_CBO_1_PERFCTR3
Uncore C-Box 1, Performance Counter 3 Package
Register Address: 720H, 1824 MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR Package
Register Address: 721H, 1825 MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR Package
Register Address: 722H, 1826 MSR_UNC_CBO_2_PERFEVTSEL2
Uncore C-Box 2, Counter 2 Event Select MSR Package
Register Address: 723H, 1827 MSR_UNC_CBO_2_PERFEVTSEL3
Uncore C-Box 2, Counter 3 Event Select MSR Package
Register Address: 725H, 1829 MSR_UNC_CBO_2_UNIT_STATUS
Uncore C-Box 2, Unit Status for Counter 0-3 Package
Register Address: 726H, 1830 MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0 Package
Register Address: 727H, 1831 MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1 Package
Register Address: 728H, 1832 MSR_UNC_CBO_3_PERFCTR2Table 2-22.  Uncore PMU MSRs Supported by 2nd Generation Intel® Core ™ Processors  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-223MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 3, Performance Counter 2 Package
Register Address: 729H, 1833 MSR_UNC_CBO_3_PERFCTR3
Uncore C-Box 3, Performance Counter 3 Package
Register Address: 730H, 1840 MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR Package
Register Address: 731H, 1841 MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR Package
Register Address: 732H, 1842 MSR_UNC_CBO_3_PERFEVTSEL2
Uncore C-Box 3, Counter 2 Event Select MSR Package
Register Address: 733H, 1843 MSR_UNC_CBO_3_PERFEVTSEL3
Uncore C-Box 3, counter 3 Event Select MSR Package
Register Address: 735H, 1845 MSR_UNC_CBO_3_UNIT_STATUS
Uncore C-Box 3, Unit Status for Counter 0-3 Package
Register Address: 736H, 1846 MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0 Package
Register Address: 737H, 1847 MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1 Package
Register Address: 738H, 1848 MSR_UNC_CBO_3_PERFCTR2
Register Address: 739H, 1849 MSR_UNC_CBO_3_PERFCTR3
Register Address: 740H, 1856 MSR_UNC_CBO_4_PERFEVTSEL0
Uncore C-Box 4, Counter 0 Event Select MSR Package
Register Address: 741H, 1857 MSR_UNC_CBO_4_PERFEVTSEL1
Uncore C-Box 4, Counter 1 Event Select MSR Package
Register Address: 742H, 1858 MSR_UNC_CBO_4_PERFEVTSEL2
Uncore C-Box 4, Counter 2 Event Select MSR Package
Register Address: 743H, 1859 MSR_UNC_CBO_4_PERFEVTSEL3
Uncore C-Box 4, Counter 3 Event Select MSR Package
Register Address: 745H, 1861 MSR_UNC_CBO_4_UNIT_STATUS
Uncore C-Box 4, Unit status for Counter 0-3 Package
Register Address: 746H, 1862 MSR_UNC_CBO_4_PERFCTR0
Uncore C-Box 4, Performance Counter 0 Package
Register Address: 747H, 1863 MSR_UNC_CBO_4_PERFCTR1
Uncore C-Box 4, Performance Counter 1 Package
Register Address: 748H, 1864 MSR_UNC_CBO_4_PERFCTR2
Uncore C-Box 4, Performance Counter 2 PackageTable 2-22.  Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors  (Contd.)
Register Information / Bit Fields Bit Description Scope2-224 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.11.2  MSRs in the Intel® Xeon® Proces sor E5 Family Based on Sandy Bridge 
Table 2-23 lists additional model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5 Family 
based on Sandy Bridge microarchitecture. These processo rs have a CPUID Signature DisplayFamily_DisplayModel 
value of 06_2DH, and also support MSRs listed in Table 2-20 and Table 2-24. Register Address: 749H, 1865 MSR_UNC_CBO_4_PERFCTR3
Uncore C-Box 4, Performance Counter 3 Package
Table 2-23.  Additional MSRs Supported by the Intel®  Xeon® Processors E5 Family Based on Sandy Bridge 
Register Address: 17FH, 383 MSR_ERROR_CONTROL
MC Bank Error Configuration (R/W) Package
1 MemError Log Enable (R/W) 
When set, enables IMC status bank to  log additional in fo in bits 36:32.

R/O if MSR_PLATFORM_INFO.[28] = 0. R/W if MSR_PLATFORM_INFO.[28] = 1.Package
Maximum turbo ratio limit of 2 cores active. Package
Maximum turbo ratio limit of 3 cores active.Package
Maximum turbo ratio limit of 4 cores active.Package
Maximum turbo ratio limit of 5 cores active.Package
Maximum turbo ratio limit of 6 cores active.Package
Maximum turbo ratio limit of 7 cores active.Package
Maximum turbo ratio limit of 8 cores active.Package
See Table 2-2. PackageTable 2-22.  Uncore PMU MSRs Supported by 2nd Generation Intel® Core ™ Processors  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-225MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 39CH, 924 MSR_PEBS_NUM_ALT
ENABLE_PEBS_NUM_ALT (R/W) Package
0 ENABLE_PEBS_NUM_ALT (R/W)
Write 1 to enable alternate PEBS counting logic for specific events 
requiring additional configuration, see https://perfmon-e vents.intel.com/ .
63:1 Reserved, must be zero.
Register Address: 415H, 1045 IA32_MC5_STATUSTable 2-23.  Additional MSRs Supported by the Intel®  Xeon® Processors E5 Family Based on Sandy Bridge 
Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-226 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.4, “IA32_MC i_MISC MSRs.” PackageTable 2-23.  Additional MSRs Supported by the Intel®  Xeon® Processors E5 Family Based on Sandy Bridge 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-227MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 43AH, 1082 IA32_MC14_ADDRTable 2-23.  Additional MSRs Supported by the Intel®  Xeon® Processors E5 Family Based on Sandy Bridge 
Register Information / Bit Fields Bit Description Scope2-228 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)

See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” PackageTable 2-23.  Additional MSRs Supported by the Intel®  Xeon® Processors E5 Family Based on Sandy Bridge 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-229MODEL-SPECIFIC REGISTERS (MSRS)
2.11.3  Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family
Intel Xeon Processor E5 family is based on the Sandy Bridge microarchitecture. The MSR-based uncore PMU inter-
faces are listed in Table 2-24. For complete details of th e uncore PMU, refer to the Intel Xeon Processor E5 Product 
Family Uncore Performance Monitoring Guide. These processors have a CPUID Signature 
DisplayFamily_DisplayModel value of 06_2DH.Register Address: 44DH, 1101 IA32_MC19_STATUS
Package RAPL Perf Status (R/O) Package
See Table 2-20, Table 2-23, and Table 2-24 for MSR defini tions applicable to processors with a CPUID Signature 
DisplayFamily_DisplayMod el value of 06_2DH. 
Table 2-24.  Uncore PMU MSRs in Intel® Xeon® Processor E5 Family
Register Address: C08H, 3080 MSR_U_PMON_UCLK_FIXED_CTL
Uncore U-box UCLK Fixed Counter Control Package
Register Address: C09H, 3081 MSR_U_PMON_UCLK_FIXED_CTRTable 2-23.  Additional MSRs Supported by the Intel®  Xeon® Processors E5 Family Based on Sandy Bridge 
Register Information / Bit Fields Bit Description Scope2-230 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore U-box UCLK Fixed Counter Package
Register Address: C10H, 3088 MSR_U_PMON_EVNTSEL0
Uncore U-box Perfmon Event Select for U-box Counter 0 Package
Register Address: C11H, 3089 MSR_U_PMON_EVNTSEL1
Uncore U-box Perfmon Event Select for U-box Counter 1 Package
Register Address: C16H, 3094 MSR_U_PMON_CTR0
Uncore U-box Perfmon Counter 0 Package
Register Address: C17H, 3095 MSR_U_PMON_CTR1
Uncore U-box Perfmon Counter 1 Package
Register Address: C24H, 3108 MSR_PCU_PMON_BOX_CTL
Uncore PCU Perfmon for PC U-box-wide Control Package
Register Address: C30H, 3120 MSR_PCU_PMON_EVNTSEL0
Uncore PCU Perfmon Event Sele ct for PCU Counter 0 Package
Register Address: C31H, 3121 MSR_PCU_PMON_EVNTSEL1
Uncore PCU Perfmon Event Sele ct for PCU Counter 1 Package
Register Address: C32H, 3122 MSR_PCU_PMON_EVNTSEL2
Uncore PCU Perfmon Event Sele ct for PCU Counter 2 Package
Register Address: C33H, 3123 MSR_PCU_PMON_EVNTSEL3
Uncore PCU Perfmon Event Sele ct for PCU Counter 3 Package
Register Address: C34H, 3124 MSR_PCU_PMON_BOX_FILTER
Uncore PCU Perfmon box-wide Filter Package
Register Address: C36H, 3126 MSR_PCU_PMON_CTR0
Uncore PCU Perfmon Counter 0 Package
Register Address: C37H, 3127 MSR_PCU_PMON_CTR1
Uncore PCU Perfmon Counter 1 Package
Register Address: C38H, 3128 MSR_PCU_PMON_CTR2
Uncore PCU Perfmon Counter 2 Package
Register Address: C39H, 3129 MSR_PCU_PMON_CTR3
Uncore PCU Perfmon Counter 3 Package
Register Address: D04H, 3332 MSR_C0_PMON_BOX_CTL
Uncore C-box 0 Perfmon Local Box Wide Control Package
Register Address: D10H, 3344 MSR_C0_PMON_EVNTSEL0
Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 0 Package
Register Address: D11H, 3345 MSR_C0_PMON_EVNTSEL1
Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 1 Package
Register Address: D12H, 3346 MSR_C0_PMON_EVNTSEL2
Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 2 PackageTable 2-24.  Uncore PMU MSRs in Inte l® Xeon® Processor E5 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-231MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D13H, 3347 MSR_C0_PMON_EVNTSEL3
Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 3 Package
Register Address: D14H, 3348 MSR_C0_PMON_BOX_FILTER
Uncore C-box 0 Perfmon Box Wide Filter Package
Register Address: D16H, 3350 MSR_C0_PMON_CTR0
Uncore C-box 0 Perfmon Counter 0 Package
Register Address: D17H, 3351 MSR_C0_PMON_CTR1
Uncore C-box 0 Perfmon Counter 1 Package
Register Address: D18H, 3352 MSR_C0_PMON_CTR2
Uncore C-box 0 Perfmon Counter 2 Package
Register Address: D19H, 3353 MSR_C0_PMON_CTR3
Uncore C-box 0 Perfmon Counter 3 Package
Register Address: D24H, 3364 MSR_C1_PMON_BOX_CTL
Uncore C-box 1 Perfmon Local Box Wide Control Package
Register Address: D30H, 3376 MSR_C1_PMON_EVNTSEL0
Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 0 Package
Register Address: D31H, 3377 MSR_C1_PMON_EVNTSEL1
Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 1 Package
Register Address: D32H, 3378 MSR_C1_PMON_EVNTSEL2
Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 2 Package
Register Address: D33H, 3379 MSR_C1_PMON_EVNTSEL3
Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 3 Package
Register Address: D34H, 3380 MSR_C1_PMON_BOX_FILTER
Uncore C-box 1 Perfmon Box Wide Filter Package
Register Address: D36H, 3382 MSR_C1_PMON_CTR0
Uncore C-box 1 Perfmon Counter 0 Package
Register Address: D37H, 3383 MSR_C1_PMON_CTR1
Uncore C-box 1 Perfmon Counter 1 Package
Register Address: D38H, 3384 MSR_C1_PMON_CTR2
Uncore C-box 1 Perfmon Counter 2 Package
Register Address: D39H, 3385 MSR_C1_PMON_CTR3
Uncore C-box 1 Perfmon Counter 3 Package
Register Address: D44H, 3396 MSR_C2_PMON_BOX_CTL
Uncore C-box 2 Perfmon Local Box Wide Control Package
Register Address: D50H, 3408 MSR_C2_PMON_EVNTSEL0
Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 0 Package
Register Address: D51H, 3409 MSR_C2_PMON_EVNTSEL1Table 2-24.  Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-232 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 1 Package
Register Address: D52H, 3410 MSR_C2_PMON_EVNTSEL2
Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 2 Package
Register Address: D53H, 3411 MSR_C2_PMON_EVNTSEL3
Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 3 Package
Register Address: D54H, 3412 MSR_C2_PMON_BOX_FILTER
Uncore C-box 2 Perfmon Box Wide Filter Package
Register Address: D56H, 3414 MSR_C2_PMON_CTR0
Uncore C-box 2 Perfmon Counter 0 Package
Register Address: D57H, 3415 MSR_C2_PMON_CTR1
Uncore C-box 2 Perfmon Counter 1 Package
Register Address: D58H, 3416 MSR_C2_PMON_CTR2
Uncore C-box 2 Perfmon Counter 2 Package
Register Address: D59H, 3417 MSR_C2_PMON_CTR3
Uncore C-box 2 Perfmon Counter 3 Package
Register Address: D64H, 3428 MSR_C3_PMON_BOX_CTL
Uncore C-box 3 Perfmon Local Box Wide Control Package
Register Address: D70H, 3440 MSR_C3_PMON_EVNTSEL0
Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 0 Package
Register Address: D71H, 3441 MSR_C3_PMON_EVNTSEL1
Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 1 Package
Register Address: D72H, 3442 MSR_C3_PMON_EVNTSEL2
Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 2 Package
Register Address: D73H, 3443 MSR_C3_PMON_EVNTSEL3
Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 3 Package
Register Address: D74H, 3444 MSR_C3_PMON_BOX_FILTER
Uncore C-box 3 Perfmon Box Wide Filter Package
Register Address: D76H, 3446 MSR_C3_PMON_CTR0
Uncore C-box 3 Perfmon Counter 0 Package
Register Address: D77H, 3447 MSR_C3_PMON_CTR1
Uncore C-box 3 Perfmon Counter 1 Package
Register Address: D78H, 3448 MSR_C3_PMON_CTR2
Uncore C-box 3 Perfmon Counter 2 Package
Register Address: D79H, 3449 MSR_C3_PMON_CTR3
Uncore C-box 3 Perfmon Counter 3 Package
Register Address: D84H, 3460 MSR_C4_PMON_BOX_CTL
Uncore C-box 4 Perfmon Local Box Wide Control PackageTable 2-24.  Uncore PMU MSRs in Inte l® Xeon® Processor E5 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-233MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D90H, 3472 MSR_C4_PMON_EVNTSEL0

Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 0 Package
Register Address: D91H, 3473 MSR_C4_PMON_EVNTSEL1
Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 1 Package
Register Address: D92H, 3474 MSR_C4_PMON_EVNTSEL2
Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 2 Package
Register Address: D93H, 3475 MSR_C4_PMON_EVNTSEL3
Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 3 Package
Register Address: D94H, 3476 MSR_C4_PMON_BOX_FILTER
Uncore C-box 4 Perfmon Box Wide Filter Package
Register Address: D96H, 3478 MSR_C4_PMON_CTR0
Uncore C-box 4 Perfmon Counter 0 Package
Register Address: D97H, 3479 MSR_C4_PMON_CTR1
Uncore C-box 4 Perfmon Counter 1 Package
Register Address: D98H, 3480 MSR_C4_PMON_CTR2
Uncore C-box 4 Perfmon Counter 2 Package
Register Address: D99H, 3481 MSR_C4_PMON_CTR3
Uncore C-box 4 Perfmon Counter 3 Package
Register Address: DA4H, 3492 MSR_C5_PMON_BOX_CTL
Uncore C-box 5 Perfmon Local Box Wide Control Package
Register Address: DB0H, 3504 MSR_C5_PMON_EVNTSEL0
Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 0 Package
Register Address: DB1H, 3505 MSR_C5_PMON_EVNTSEL1
Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 1 Package
Register Address: DB2H, 3506 MSR_C5_PMON_EVNTSEL2
Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 2 Package
Register Address: DB3H, 3507 MSR_C5_PMON_EVNTSEL3
Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 3 Package
Register Address: DB4H, 3508 MSR_C5_PMON_BOX_FILTER
Uncore C-box 5 Perfmon Box Wide Filter Package
Register Address: DB6H, 3510 MSR_C5_PMON_CTR0
Uncore C-box 5 Perfmon Counter 0 Package
Register Address: DB7H, 3511 MSR_C5_PMON_CTR1
Uncore C-box 5 Perfmon Counter 1 Package
Register Address: DB8H, 3512 MSR_C5_PMON_CTR2
Uncore C-box 5 Perfmon Counter 2 Package
Register Address: DB9H, 3513 MSR_C5_PMON_CTR3Table 2-24.  Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-234 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 5 Perfmon Counter 3 Package
Register Address: DC4H, 3524 MSR_C6_PMON_BOX_CTL
Uncore C-box 6 Perfmon Local Box Wide Control Package
Register Address: DD0H, 3536 MSR_C6_PMON_EVNTSEL0
Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 0 Package
Register Address: DD1H, 3537 MSR_C6_PMON_EVNTSEL1
Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 1 Package
Register Address: DD2H, 3538 MSR_C6_PMON_EVNTSEL2
Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 2 Package
Register Address: DD3H, 3539 MSR_C6_PMON_EVNTSEL3
Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 3 Package
Register Address: DD4H, 3540 MSR_C6_PMON_BOX_FILTER
Uncore C-box 6 Perfmon Box Wide Filter Package
Register Address: DD6H, 3542 MSR_C6_PMON_CTR0
Uncore C-box 6 Perfmon Counter 0 Package
Register Address: DD7H, 3543 MSR_C6_PMON_CTR1
Uncore C-box 6 Perfmon Counter 1 Package
Register Address: DD8H, 3544 MSR_C6_PMON_CTR2
Uncore C-box 6 Perfmon Counter 2 Package
Register Address: DD9H, 3545 MSR_C6_PMON_CTR3
Uncore C-box 6 Perfmon Counter 3 Package
Register Address: DE4H, 3556 MSR_C7_PMON_BOX_CTL
Uncore C-box 7 Perfmon Local Box Wide Control Package
Register Address: DF0H, 3568 MSR_C7_PMON_EVNTSEL0
Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 0 Package
Register Address: DF1H, 3569 MSR_C7_PMON_EVNTSEL1
Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 1 Package
Register Address: DF2H, 3570 MSR_C7_PMON_EVNTSEL2
Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 2 Package
Register Address: DF3H, 3571 MSR_C7_PMON_EVNTSEL3
Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 3 Package
Register Address: DF4H, 3572 MSR_C7_PMON_BOX_FILTER
Uncore C-box 7 Perfmon Box Wide Filter Package
Register Address: DF6H, 3574 MSR_C7_PMON_CTR0
Uncore C-box 7 Perfmon Counter 0 Package
Register Address: DF7H, 3575 MSR_C7_PMON_CTR1
Uncore C-box 7 Perfmon Counter 1 PackageTable 2-24.  Uncore PMU MSRs in Inte l® Xeon® Processor E5 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-235MODEL-SPECIFIC REGISTERS (MSRS)
2.12 MSRS IN THE 3RD GENERATION IN TEL® CORE™ PROCESSOR FAMILY BASED 
ON IVY BRIDGE MICROARCHITECTURE
The 3rd generation Intel® Core™ processor family and the Intel® Xeon® processor E3-1200v2 product family 
based on Ivy Bridge microarchitecture support the MSR inte rfaces listed in Table 2-20, Table 2-21, Table 2-22, and 
Table 2-25. These processors have a CPUID Signat ure DisplayFamily_DisplayModel value of 06_3AH. Register Address: DF8H, 3576 MSR_C7_PMON_CTR2
Uncore C-box 7 Perfmon Counter 2 Package
Register Address: DF9H, 3577 MSR_C7_PMON_CTR3
Uncore C-box 7 Perfmon Counter 3 Package
Table 2-25.  Additional MSRs Supported by 3rd Genera tion Intel® Core™ Processors Based on Ivy Bridge 
This is the ratio of the frequency that invariant TSC runs at. Frequency = 
When set to 1, indicates that Progra mmable Ratio Limit for Turbo mode is 
enabled. When set to 0,  indicates Programmable Ratio Limit for Turbo 
When set to 1, indicate s that TDP Limit for Turb o mode is programmable. 
When set to 0, indicates that TDP Limit for Turbo mode is not programmable.Package
31:30 Reserved.
32 Low Power Mode Su pport (LPM) (R/O) 
When set to 1, indicates that LPM is  supported. When set to 0, indicates 
LPM is not supported.Package
34:33 Number of ConfigTDP Levels (R/O) 
00: Only Base TDP level available.
01: One additional TDP level available.
02: Two additional TDP level available.
03: ReservedPackage
39:35 Reserved.Table 2-24.  Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-236 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
55:48 Minimum Operating Ratio (R/O) 
Contains the minimum supported operating ratio in units of 100 MHz.Package
63:56 Reserved.
Note: C-state values are processor spec ific C-state code names, unrelated 
to MWAIT extension C-state parameters or ACPI C-States.
101b: C7s
When set, will map IO_read instructions sent to IO register specified by 
24:16 Reserved
25 C3 State Auto Demotion Enable (R/W) 
26 C1 State Auto Demotion Enable (R/W) 
When set, the processor will conditio nally demote C3/C6/C7 requests to 
C1 based on uncore auto-demote information.
When set, enables undemo tion from demoted C3.Table 2-25.  Additional MSRs Supported by 3rd Genera tion Intel® Core™ Processors Based on Ivy Bridge 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-237MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 648H, 1608 MSR_CONFIG_TDP_NOMINAL
Base TDP Ratio (R/O) Package
7:0 Config_TDP_Base
Base TDP level ratio to be used for th is specific processor (in units of 100 
MHz). 
Register Address: 649H, 1609 MSR_CONFIG_TDP_LEVEL1
ConfigTDP Level 1 ratio and power level (R/O) Package
14:0 PKG_TDP_LVL1
Power setting for ConfigTDP Level 1.
15 Reserved.23:16 Config_TDP_LVL1_Ratio

MHz). 
ConfigTDP level 1 ratio to be used for this specific processor. 
31:24 Reserved.
46:32 PKG_MAX_PWR_LVL1
Max Power setting allowed for ConfigTDP Level 1.
47 Reserved.
62:48 PKG_MIN_PWR_LVL1
MIN Power setting allowed for ConfigTDP Level 1.
Register Address: 64AH, 1610 MSR_CONFIG_TDP_LEVEL2
ConfigTDP Level 2 ratio and power level (R/O) Package
14:0 PKG_TDP_LVL2
Power setting for ConfigTDP Level 2.
15 Reserved.23:16 Config_TDP_LVL2_Ratio
ConfigTDP level 2 ratio to be used for this specific processor. 
46:32 PKG_MAX_PWR_LVL2
Max Power setting allowed for ConfigTDP Level 2.
47 Reserved.Table 2-25.  Additional MSRs Supported by 3rd Genera tion Intel® Core™ Processors Based on Ivy Bridge 
Register Information / Bit Fields Bit Description Scope2-238 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.12.1  MSRs in the Intel® Xeon® Processor E5  v2 Product Family Based on Ivy Bridge-E 
Table 2-26 lists model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5 v2 Product 
Family (based on Ivy Bridge-E microarchitect ure). These processors have a CPUID Signature 
DisplayFamily_DisplayModel value of 06_3EH; see Table 2- 1. These processors supports the MSR interfaces listed 
in Table 2-20 and Table 2-26. 62:48 PKG_MIN_PWR_LVL2
MIN Power setting allowed for ConfigTDP Level 2.
Register Address: 64BH, 1611 MSR_CONFIG_TDP_CONTROL
1:0 TDP_LEVEL (RW/L)
30:2 Reserved.31 Config_TDP_Lock (RW/L)
Register Address: 64CH, 1612 MSR_TURBO_ACTIVATION_RATIO
7:0 MAX_NON_TURBO_RATIO (RW/L)
31 TURBO_ACTIVATION _RATIO_Lock (RW/L)
See Table 2-20, Table 2-21, and Table 2-22 for other MSR defi nitions applicable to proce ssors with a CPUID Signature 
DisplayFamily_DisplayMod el value of 06_3AH.
Table 2-26.  MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: 4EH, 78 IA32_PPIN_CTL (MSR_PPIN_CTL)
Protected Processor Inventory Numb er Enable Control (R/W) Package
1 Enable_PPIN (R/W)
63:2 Reserved.Table 2-25.  Additional MSRs Supported by 3rd Genera tion Intel® Core™ Processors Based on Ivy Bridge 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-239MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 4FH, 79 IA32_PPIN (MSR_PPIN)
Protected Processor Invent ory Number (R/O) Package
22:16 Reserved.
23 PPIN_CAP (R/O)
When set to 1, indicates that Protec ted Processor Inventory Number (PPIN) 
capability can be enabled for a privileged system inventory agent to read 
PPIN from MSR_PPIN.
When set to 0, PPIN capability is not supported. An attempt to access 
MSR_PPIN_CTL or MSR_PPIN will cause #GP.Package
27:24 Reserved.
enabled. When set to 0, indicates Pr ogrammable Ratio Limit for Turbo mode 
is disabled.Package
When set to 1, indicates that MSR_ TEMPERATURE_TARGET.[27:24] is valid 
and writable to specify a temperature offset.Package
39:31 Reserved.
ACPI C-states. See http://biosbits.org.CoreTable 2-26.  MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description Scope2-240 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
The following C-state code name encodings are supported:000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.
Global Machine Check Capability (R/O) Thread
7:0 Count
8 MCG_CTL_P9 MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P15:12 Reserved.
23:16 MCG_EXT_CNT
24 MCG_SER_P25 Reserved.
26 MCG_ELOG_P
0 Reserved.1 MemError Log Enable (R/W) 
63:2 Reserved.Table 2-26.  MSRs Supported by  the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-241MODEL-SPECIFIC REGISTERS (MSRS)
15:0 Reserved.23:16 Temperature Target (R/O) 
The minimum temperature at which PR OCHOT# will be asserted. The value 
27:24 TCC Activation Offset (R/W) 
Specifies a temperature offset in degrees C from the temperature target 
(bits 23:16). PROCHOT# will assert at the offset target temperature. Write 
is permitted only if MSR_PLATFORM_INFO.[30] is set.
Register Address: 1AEH, 430 MSR_TURBO_RATIO_LIMIT1
7:0 Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active. Package
15:8 Maximum Ratio Limit for 10C
Maximum turbo ratio limi t of 10 core active. Package
23:16 Maximum Ratio Limit for 11C
Maximum turbo ratio limi t of 11 core active.Package
31:24 Maximum Ratio Limit for 12C
Maximum turbo ratio limi t of 12 core active.Package
See Table 2-2. PackageTable 2-26.  MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description Scope2-242 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)

Register Address: 297H, 663 IA32_MC23_CTL2IA32_MC23_CTL2
See Section 16.3.2.1, “IA32_MC i_CTL MSRs,” through Section 16.3.2.4, “IA32_MC i_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI module.Package
Bank MC5 reports MC errors from the Intel QPI module.PackageTable 2-26.  MSRs Supported by  the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-243MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC6 reports MC errors from the integrated I/O module.Package
Banks MC7 and MC 8 report MC e rrors from the two home agents.Package
Banks MC7 and MC 8 report MC e rrors from the two home agents.PackageTable 2-26.  MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description Scope2-244 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Banks MC9 through MC 16 report MC errors from ea ch channel of the integr ated memory controllers.Package
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” 
Bank MC11 reports MC errors fr om a specific channel of the integrated memory controller.Package
Bank MC11 reports MC errors fr om a specific channel of the integrated memory controller.PackageTable 2-26.  MSRs Supported by  the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-245MODEL-SPECIFIC REGISTERS (MSRS)

Banks MC9 through MC 16 report MC errors from ea ch channel of the integr ated memory controllers.PackageTable 2-26.  MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description Scope2-246 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.PackageTable 2-26.  MSRs Supported by  the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-247MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.PackageTable 2-26.  MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description Scope2-248 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package

Register Address: 45AH, 1114 IA32_MC22_ADDR
Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Register Address: 45EH, 1118 IA32_MC23_ADDR
Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Register Address: 462H, 1122 IA32_MC24_ADDR
Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.PackageTable 2-26.  MSRs Supported by  the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-249MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Register Address: 466H, 1126 IA32_MC25_ADDR
Register Address: 467H, 1127 IA32_MC2MISC
Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Register Address: 46AH, 1130 IA32_MC26_ADDR
Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Register Address: 46EH, 1134 IA32_MC27_ADDR
Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.PackageTable 2-26.  MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description Scope2-250 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.12.2  Additional MSRs Supported by the Intel® Xeon®  Processor E7 v2 Family
The Intel® Xeon® processor E7 v2 family (based on Ivy Bridge-E microarchitecture) with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_3EH supports the MSR interfaces listed in Table 2-20, Table 2-26, and 
Table 2-27. Register Address: 471H, 1137 IA32_MC28_STATUS
Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Register Address: 472H, 1138 IA32_MC28_ADDR
See Table 2-20, for other MSR definitions applicable to Intel Xeon processor E5 v2 with a CPUID Signature 
DisplayFamily_DisplayMod el value of 06_3EH. 
Table 2-27.  Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature 
DisplayFamily_DisplayMod el Value of 06_3EH 
Register Address: 3AH, 58 IA32_FEATURE_CONTROLTable 2-26.  MSRs Supported by  the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-251MODEL-SPECIFIC REGISTERS (MSRS)
2 Enable VMX Outside SMX Operation (R/WL) 14:8 SENTER Local Functions Enables (R/WL) 
7:0 Count

7:0 Count
24 MCG_SER_P63:25 Reserved.
Global Machine Check Status (R/W) Thread
0R I P V
1E I P V
2M C I P3L M C E  S i g n a l e d
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.Package
Maximum turbo ratio limi t of 9 core active. Package
Maximum turbo ratio li mit of 10core active. Package
Maximum turbo ratio limi t of 12 core active.PackageTable 2-27.  Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Fami ly with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_3EH  (Contd.)
Register Information / Bit Fields Bit Description Scope2-252 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
39:32 Maximum Rati o Limit for 13C
Maximum turbo ratio limi t of 13 core active.Package
47:40 Maximum Rati o Limit for 14C
Maximum turbo ratio limi t of 14 core active.Package
55:48 Maximum Rati o Limit for 15C
Maximum turbo ratio limi t of 15 core active.Package
62:56 Reserved.
63 Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration1 specified in 
MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration (Default).Package
Register Address: 29DH, 669 IA32_MC29_CTL2
See Section 20.3.1.1.1, “Processor Event Based Sampling (PEBS).” Threadn:0 Enable PEBS on IA32_PMCx. (R/W)
32+m:32 Enable Load Latency on IA32_PMCx. (R/W)
63:33+ m Reserved.
Misc MAC Information of  Integrated I/O (R/O) 
See Section 16.3.2.4.Package
5:0 Recoverable Address LSB
8:6 Address Mode
15:9 Reserved.
31:16 PCI Express Requestor ID39:32 PCI Express Segment Number
Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.PackageTable 2-27.  Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-253MODEL-SPECIFIC REGISTERS (MSRS)
2.12.3  Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families
Intel Xeon Processor E5 v2 and E7 v2 families are base d on the Ivy Bridge-E microarchitecture. The MSR-based 
uncore PMU interfaces are listed in Table 2-24 and Table 2-28. For complete detail of the uncore PMU, refer to Intel Register Address: 476H, 1142 IA32_MC29_ADDR
Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Register Address: 47BH, 1147 IA32_MC30_MISC
Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.Package
Register Address: 47FH, 1147 IA32_MC31_MISC
See Table 2-20, Table 2-26 for other MSR definitions applicab le to Intel Xeon processor E7  v2 with a CPUID Signature 
DisplayFamily_DisplayMod el value of 06_3AH. 
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher tha n the 
factory-set configuration is dependent on features specific to the processor and the platform.Table 2-27.  Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Fami ly with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-254 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Xeon Processor E5 v2 Product Family Uncore Performa nce Monitoring Guide. These processors have a CPUID 
Signature DisplayFamily_Dis playModel value of 06_3EH.
Table 2-28.  Uncore PMU MSRs in the Intel®  Xeon® Processor E5 v2  and E7 v2 Families
Register Address: C00H, 3072 MSR_PMON_GLOBAL_CTL
Uncore Perfmon Per-Socket Global Control Package
Register Address: C01H, 3073 MSR_PMON_GLOBAL_STATUS
Uncore Perfmon Per-Socket Global Status Package
Register Address: C06H, 3078 MSR_PMON_GLOBAL_CONFIG
Uncore Perfmon Per-Socket Global Configuration Package
Register Address: C15H, 3093 MSR_U_PMON_BOX_STATUS
Uncore U-box Perfmon U-Box Wide Status Package
Register Address: C35H, 3125 MSR_PCU_PMON_BOX_STATUS
Uncore PCU Perfmon Box Wide Status Package
Register Address: D1AH, 3354 MSR_C0_PMON_BOX_FILTER1
Uncore C-Box 0 Perfmon Box Wide Filter1 Package
Register Address: D3AH, 3386 MSR_C1_PMON_BOX_FILTER1
Uncore C-Box 1 Perfmon Box Wide Filter1 Package
Register Address: D5AH, 3418 MSR_C2_PMON_BOX_FILTER1
Uncore C-Box 2 Perfmon Box Wide Filter1 Package
Register Address: D7AH, 3450 MSR_C3_PMON_BOX_FILTER1
Uncore C-Box 3 Perfmon Box Wide Filter1 Package
Register Address: D9AH, 3482 MSR_C4_PMON_BOX_FILTER1
Uncore C-Box 4 Perfmon Box Wide Filter1 Package
Register Address: DBAH, 3514 MSR_C5_PMON_BOX_FILTER1
Uncore C-Box 5 Perfmon Box Wide Filter1 Package
Register Address: DDAH, 3546 MSR_C6_PMON_BOX_FILTER1
Uncore C-Box 6 Perfmon Box Wide Filter1 Package
Register Address: DFAH, 3578 MSR_C7_PMON_BOX_FILTER1
Uncore C-Box 7 Perfmon Box Wide Filter1 Package
Register Address: E04H, 3588 MSR_C8_PMON_BOX_CTL
Uncore C-Box 8 Perfmon Local Box Wide Control Package
Register Address: E10H, 3600 MSR_C8_PMON_EVNTSEL0
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 0 Package
Register Address: E11H, 3601 MSR_C8_PMON_EVNTSEL1
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 1 Package
Register Address: E12H, 3602 MSR_C8_PMON_EVNTSEL2
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 2 Package
Register Address: E13H, 3603 MSR_C8_PMON_EVNTSEL3Vol. 4 2-255MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 3 Package
Register Address: E14H, 3604 MSR_C8_PMON_BOX_FILTER
Uncore C-Box 8 Perfmon Box Wide Filter Package

Register Address: E16H, 3606 MSR_C8_PMON_CTR0
Uncore C-Box 8 Perfmon Counter 0 Package
Register Address: E17H, 3607 MSR_C8_PMON_CTR1
Uncore C-Box 8 Perfmon Counter 1 Package
Register Address: E18H, 3608 MSR_C8_PMON_CTR2
Uncore C-Box 8 Perfmon Counter 2 Package
Register Address: E19H, 3609 MSR_C8_PMON_CTR3
Uncore C-Box 8 Perfmon Counter 3 Package
Register Address: E1AH, 3610 MSR_C8_PMON_BOX_FILTER1
Uncore C-Box 8 Perfmon Box Wide Filter1 Package
Register Address: E24H, 3620 MSR_C9_PMON_BOX_CTL
Uncore C-Box 9 Perfmon Local Box Wide Control Package
Register Address: E30H, 3632 MSR_C9_PMON_EVNTSEL0
Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 0 Package
Register Address: E31H, 3633 MSR_C9_PMON_EVNTSEL1
Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 1 Package
Register Address: E32H, 3634 MSR_C9_PMON_EVNTSEL2
Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 2 Package
Register Address: E33H, 3635 MSR_C9_PMON_EVNTSEL3
Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 3 Package
Register Address: E34H, 3636 MSR_C9_PMON_BOX_FILTER
Uncore C-Box 9 Perfmon Box Wide Filter Package
Register Address: E36H, 3638 MSR_C9_PMON_CTR0
Uncore C-Box 9 Perfmon Counter 0 Package
Register Address: E37H, 3639 MSR_C9_PMON_CTR1
Uncore C-Box 9 Perfmon Counter 1 Package
Register Address: E38H, 3640 MSR_C9_PMON_CTR2
Uncore C-Box 9 Perfmon Counter 2 Package
Register Address: E39H, 3641 MSR_C9_PMON_CTR3
Uncore C-Box 9 Perfmon Counter 3 Package
Register Address: E3AH, 3642 MSR_C9_PMON_BOX_FILTER1
Uncore C-Box 9 Perfmon Box Wide Filter1 Package
Register Address: E44H, 3652 MSR_C10_PMON_BOX_CTL
Uncore C-Box 10 Perfmon Lo cal Box Wide Control PackageTable 2-28.  Uncore PMU MSRs in the Intel® Xeon ® Processor E5 v2  and E7 v2 Families (Contd.)
Register Information / Bit Fields Bit Description Scope2-256 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E50H, 3664 MSR_C10_PMON_EVNTSEL0
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 0 Package
Register Address: E51H, 3665 MSR_C10_PMON_EVNTSEL1
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 1 Package
Register Address: E52H, 3666 MSR_C10_PMON_EVNTSEL2
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 2 Package
Register Address: E53H, 3667 MSR_C10_PMON_EVNTSEL3
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 3 Package
Register Address: E54H, 3668 MSR_C10_PMON_BOX_FILTER
Uncore C-Box 10 Perfmon Box Wide Filter Package
Register Address: E56H, 3670 MSR_C10_PMON_CTR0
Uncore C-Box 10 Perfmon Counter 0 Package
Register Address: E57H, 3671 MSR_C10_PMON_CTR1
Uncore C-Box 10 Perfmon Counter 1 Package
Register Address: E58H, 3672 MSR_C10_PMON_CTR2
Uncore C-Box 10 Perfmon Counter 2 Package
Register Address: E59H, 3673 MSR_C10_PMON_CTR3
Uncore C-Box 10 Perfmon Counter 3 Package
Register Address: E5AH, 3674 MSR_C10_PMON_BOX_FILTER1
Uncore C-Box 10 Perfmon Box Wide Filter1 Package
Register Address: E64H, 3684 MSR_C11_PMON_BOX_CTL
Uncore C-Box 11 Perfmon Lo cal Box Wide Control Package
Register Address: E70H, 3696 MSR_C11_PMON_EVNTSEL0
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 0 Package
Register Address: E71H, 3697 MSR_C11_PMON_EVNTSEL1
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 1 Package
Register Address: E72H, 3698 MSR_C11_PMON_EVNTSEL2
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 2 Package
Register Address: E73H, 3699 MSR_C11_PMON_EVNTSEL3
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 3 Package
Register Address: E74H, 3700 MSR_C11_PMON_BOX_FILTER
Uncore C-Box 11 Perfmon Box Wide Filter Package
Register Address: E76H, 3702 MSR_C11_PMON_CTR0
Uncore C-Box 11 Perfmon Counter 0 Package
Register Address: E77H, 3703 MSR_C11_PMON_CTR1
Uncore C-Box 11 Perfmon Counter 1 Package
Register Address: E78H, 3704 MSR_C11_PMON_CTR2Table 2-28.  Uncore PMU MSRs in the Intel® Xeon ® Processor E5 v2 and E7  v2 Families (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-257MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 11 Perfmon Counter 2 Package
Register Address: E79H, 3705 MSR_C11_PMON_CTR3
Uncore C-Box 11 Perfmon Counter 3 Package
Register Address: E7AH, 3706 MSR_C11_PMON_BOX_FILTER1
Uncore C-Box 11 Perfmon Box Wide Filter1 Package
Register Address: E84H, 3716 MSR_C12_PMON_BOX_CTL
Uncore C-Box 12 Perfmon Lo cal Box Wide Control Package
Register Address: E90H, 3728 MSR_C12_PMON_EVNTSEL0
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 0 Package
Register Address: E91H, 3729 MSR_C12_PMON_EVNTSEL1
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 1 Package
Register Address: E92H, 3730 MSR_C12_PMON_EVNTSEL2
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 2 Package
Register Address: E93H, 3731 MSR_C12_PMON_EVNTSEL3
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 3 Package
Register Address: E94H, 3732 MSR_C12_PMON_BOX_FILTER
Uncore C-Box 12 Perfmon Box Wide Filter Package
Register Address: E96H, 3734 MSR_C12_PMON_CTR0
Uncore C-Box 12 Perfmon Counter 0 Package
Register Address: E97H, 3735 MSR_C12_PMON_CTR1
Uncore C-Box 12 Perfmon Counter 1 Package
Register Address: E98H, 3736 MSR_C12_PMON_CTR2
Uncore C-Box 12 Perfmon Counter 2 Package
Register Address: E99H, 3737 MSR_C12_PMON_CTR3
Uncore C-Box 12 Perfmon Counter 3 Package
Register Address: E9AH, 3738 MSR_C12_PMON_BOX_FILTER1
Uncore C-Box 12 Perfmon Box Wide Filter1 Package
Register Addres s: EA4H, 3748 MSR_C13_PMON_BOX_CTL
Uncore C-Box 13 Perfmon Lo cal Box Wide Control Package
Register Address: EB0H, 3760 MSR_C13_PMON_EVNTSEL0
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 0 Package
Register Address: EB1H, 3761 MSR_C13_PMON_EVNTSEL1
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 1 Package
Register Address: EB2H, 3762 MSR_C13_PMON_EVNTSEL2
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 2 Package
Register Address: EB3H, 3763 MSR_C13_PMON_EVNTSEL3
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 3 PackageTable 2-28.  Uncore PMU MSRs in the Intel® Xeon ® Processor E5 v2  and E7 v2 Families (Contd.)
Register Information / Bit Fields Bit Description Scope2-258 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: EB4H, 3764 MSR_C13_PMON_BOX_FILTER
Uncore C-Box 13 Perfmon Box Wide Filter Package
Register Address: EB6H, 3766 MSR_C13_PMON_CTR0
Uncore C-Box 13 Perfmon Counter 0 Package
Register Address: EB7H, 3767 MSR_C13_PMON_CTR1
Uncore C-Box 13 Perfmon Counter 1 Package
Register Address: EB8H, 3768 MSR_C13_PMON_CTR2
Uncore C-Box 13 Perfmon Counter 2 Package
Register Address: EB9H, 3769 MSR_C13_PMON_CTR3
Uncore C-Box 13 Perfmon Counter 3 Package
Register Address: EBAH, 3770 MSR_C13_PMON_BOX_FILTER1
Uncore C-Box 13 Perfmon Box Wide Filter1 Package
Register Address: EC4H, 3780 MSR_C14_PMON_BOX_CTL
Uncore C-Box 14 Perfmon Lo cal Box Wide Control Package
Register Address: ED0H, 3792 MSR_C14_PMON_EVNTSEL0
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 0 Package
Register Address: ED1H, 3793 MSR_C14_PMON_EVNTSEL1
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 1 Package
Register Address: ED2H, 3794 MSR_C14_PMON_EVNTSEL2
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 2 Package
Register Address: ED3H, 3795 MSR_C14_PMON_EVNTSEL3
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 3 Package
Register Address: ED4H, 3796 MSR_C14_PMON_BOX_FILTER
Uncore C-Box 14 Perfmon Box Wide Filter Package
Register Address: ED6H, 3798 MSR_C14_PMON_CTR0
Uncore C-Box 14 Perfmon Counter 0 Package
Register Address: ED7H, 3799 MSR_C14_PMON_CTR1
Uncore C-Box 14 Perfmon Counter 1 Package
Register Address: ED8H, 3800 MSR_C14_PMON_CTR2
Uncore C-Box 14 Perfmon Counter 2 Package
Register Address: ED9H, 3801 MSR_C14_PMON_CTR3
Uncore C-Box 14 Perfmon Counter 3 Package
Register Address: EDAH, 3802 MSR_C14_PMON_BOX_FILTER1
Uncore C-Box 14 Perfmon Box Wide Filter1 PackageTable 2-28.  Uncore PMU MSRs in the Intel® Xeon ® Processor E5 v2 and E7  v2 Families (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-259MODEL-SPECIFIC REGISTERS (MSRS)
2.13 MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS BASED ON 
HASWELL MICROARCHITECTURE
The 4th generation Intel® Core™ processor family and the Intel® Xeon® processor E3-1200v3 product family 
(based on Haswell microarchitecture), with a CPUID Signature DisplayFamily_Dis playModel value of 06_3CH, 
06_45H, or 06_46H, support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and Table 2-29. For 
an MSR listed in Table 2-20 that also appears in Table 2-29, Table 2-29 supersedes Table 2-20.
The MSRs listed in Table 2-29 also apply to processors based on Haswell-E microarchitecture (see Section 2.14).

Table 2-29.  Additional MSRs Supported by Processors  Based on the Haswell and Haswell-E Microarchitectures
Per-Logical-Processor TSC ADJUST (R/W)
01: One additional TDP level available.02: Two additional TDP level available.
03: Reserved.Package
39:35 Reserved.
63:56 Reserved.2-260 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Performance Event Select for Counter 0 (R/W)
Supports all fields described inTable 2-2 and the fields below.Thread
32 IN_TX: See Section 20.3.6.5.1.
When IN_TX (bit 32) is set, AnyThr ead (bit 21) should be cleared to 
prevent incorrect results.
Performance Event Select for Counter 1 (R/W)
Performance Event Select for Counter 2 (R/W)
33 IN_TXCP: See Section 20.3.6.5.1.
When IN_TXCP=1 & IN_TX=1 and in sa mpling, a spurious PMI may occur 
and transactions may continuously abort near overflow conditions. 
Software should favor using IN_TXC P for counting over sampling. If 
sampling, software should  use large “sample-after” value after clearing 
the counter configured to use IN_TXC P and also always reset the counter 
even when no overflow condition was reported. 
Performance Event Select for Counter 3 (R/W)
32 IN_TX: See Section 20.3.6.5.1
Last Branch Record Filtering Select Re gister (R/W) Thread
0C P L _ E Q _ 01C P L _ N E Q _ 0
2J C C
5 NEAR_RET
6 NEAR_IND_JMP7 NEAR_REL_JMPTable 2-29.  Additional MSRs Supported by Processors Based on the Haswell and Ha swell-E Microarchitectures 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-261MODEL-SPECIFIC REGISTERS (MSRS)
9 EN_CALL_STACK
1B T F5:2 Reserved.6T R :  B r a n c h  T r a c e
7 BTS: Log Branch Trace Message to BTS Buffer
8B T I N T9 BTS_OFF_OS
14 FREEZE_WHILE_SMM15 RTM_DEBUG
Register Address: 60BH, 1548 MSR_PKGC_IRTL1
Package C6/C7 Interrupt Response Li mit 1 (R/W) 
This MSR defines the interrupt response time limit used by the processor to  manage a transition to a package C6 or 
C7 state. The latency programmed in this register is for the shorter-latency sub C-states used by an MWAIT hint to a C6 or C7 state.
9:0 Interrupt Response  Time Limit (R/W) 
put into a package C6 or C7 state. 
the processor for package C-sate management. Table 2-29.  Additional MSRs Supported by Processors Based on the Haswell and Ha swell-E Microarchitectures 
Register Information / Bit Fields Bit Description Scope2-262 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Package C6/C7 Interrupt Response Limit 2 (R/W) 
C7 state. The latency programmed in this register is for the longer-latency sub C-states used by an MWAIT hint to a C6 
or C7 state.
Note: C-state values are processor specific C-state code na mes, unrelated to MWAIT extension C-state parameters or 
9:0 Interrupt response  time limit (R/W) 
Specifies the limi t that should be used to deci de if the package should be 
limit. See Table 2-20 for supp orted time unit encodings.
MHz). 
ConfigTDP Level 1 Ratio and Power Level (R/O) Package14:0 PKG_TDP_LVL1
23:16 Config_TDP_LVL1_Ratio
ConfigTDP level 1 ratio to be used for this specific processor. Table 2-29.  Additional MSRs Supported by Processors Based on the Haswell and Ha swell-E Microarchitectures 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-263MODEL-SPECIFIC REGISTERS (MSRS)
62:47 PKG_MIN_PWR_LVL1
ConfigTDP Level 2 Ratio and Power Level (R/O) Package
23:16 Config_TDP_LVL2_Ratio
62:47 PKG_MIN_PWR_LVL2
Silicon Debug Feature Control (R/W)

See Table 2-2.PackageTable 2-29.  Additional MSRs Supported by Processors Based on the Haswell and Ha swell-E Microarchitectures 
Register Information / Bit Fields Bit Description Scope2-264 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.13.1  MSRs in the 4th Generation Intel®  Core™ Processor Family Based on Haswell 
Table 2-30 lists model-specific registers (MSRs) that are specific to the 4th generation Intel® Core™ processor 
family and the Intel® Xeon® processor E3-1200 v3 product family (based on Haswell microarchitecture). These 
processors have a CPUID Signature DisplayFamily_Displa yModel value of 06_3CH, 06_45H, or 06_46H; see Table 
2-1. 
Table 2-30.  MSRs Supported by 4th Generation In tel® Core™ Processors (H aswell Microarchitecture)
ACPI C-states. See http://biosbits.org.Core
3:0 Package C-State Limit (R/W)
Specifies the lowest processor- specific C-state code name 
(consuming the least power) for the package. The default is set 
as factory-conf igured package C-state limit.
The following C-state code name encodings are supported:0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C30011b: C6
0100b: C7
0101b: C7sPackage C states C7 are not available to processors with a 
CPUID Signature DisplayFamily_ DisplayModel value of 06_3CH.
9:4 Reserved.
10 I/O MWAIT Redirection Enable (R/W)14:11 Reserved
15 CFG Lock (R/WO)
24:16 Reserved.25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
Reports SMM capability Enhancement. Accessible only while in SMM.Thread
If set to 1, indicates that th e SMM code access restriction is 
supported and the MSR_SMM_FEATURE_CONTROL is supported.Vol. 4 2-265MODEL-SPECIFIC REGISTERS (MSRS)
If set to 1, indicates that th e SMM long flow indicator is 
supported and the MSR_SMM_DELAYED is supported.
63:60 Reserved.
0 Core 0 select.
1 Core 1 select.
2 Core 2 select.3 Core 3 select.
18:4 Reserved.
0 Fixed counter overflowed.1A n  A R B  c o u n t e r  o v e r f l o w e d .
3 A CBox counter overflowed (on any slice).63:4 Reserved.
Register Address: 394H, 916 MSR_UNC_PERF_FIXED_CTRL
19:0 Reserved.
20 Enable overflow propagation.
21 Reserved.Table 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitect ure) (Contd.)
Register Information / Bit Fields Bit Description Scope2-266 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
22 Enable counting.
Register Address: 395H, 917 MSR_UNC_PERF_FIXED_CTR
47:0 Current count.
Uncore C-Box Configuration Information (R/O) Package
3:0 Encoded number of C-Bo x, derive value by “-1“.
Uncore Arb Unit, Counter 1 Event Select MSR Package
1 Core 1 select.2 Core 2 select.
3 Core 3 select.
18:4 Reserved.29 Enable all un core counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.63:32 Reserved.
Reports SMM capability Enhancement. Accessible only while in SMM.PackageTable 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-267MODEL-SPECIFIC REGISTERS (MSRS)
This control bit is available on ly if MSR_SMM_MCA_CAP[58] == 
1. When set to ‘0’ (default) none  of the logical processors are 
prevented from executing SMM code outside the ranges defined 
by the SMRR. 
When set to ‘1’ any logical processor in the package that 
attempts to execute SMM code not within the ranges defined 
by the SMRR will assert  an unrecoverable MCE.
Each bit represents a logical processor of its state in a long flow 
of internal operation which delays servicing an interrupt. The corresponding bit will be set at the start of long events such as: 
Microcode Update Load, C6, WBINVD, Ratio Change, Throttle. 
The bit is automatically cleared at the end of each long event. 
The reset value of this field is 0.
Only bit positions belo w N = CPUID.(EAX=0BH, 
ECX=PKG_LVL):EBX[15:0] can be updated.
Reports the blocked state of all logical processors in the package. Available only while in SMM.Package
Each bit represents a logical processor of its blocked state to 
service an SMI. The corresponding bit will be set if the logical 
processor is in one of the following states: Wait For SIPI or SENTER Sleep. 
The reset value of this field is 0FFFH.
Unit Multipliers Used in RAPL Interfaces (R/O) Package
7:4 Reserved. PackageTable 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitect ure) (Contd.)
Register Information / Bit Fields Bit Description Scope2-268 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
12:8 Energy Status Units
Energy related information (in Joules) is based on the multiplier, 
1/2^ESU; where ESU is an unsigned integer represented by bits 
12:8. Default value is 0EH (or 61 micro-joules).Package
15:13 Reserved. Package
19:16 Time Units
Register Address: 690H, 1680 MSR_CORE_PERF_LIMIT_REASONS
0 PROCHOT Status (R0)
When set, processor core frequency is reduced below the 
operating system request due to assertion of external 
PROCHOT.

PROCHOT.
When set, frequency is reduced below the operating system 
request due to a thermal event.
3:2 Reserved.
4 Graphics Driver Status (R0)
request due to Processor Graphics driver override.
5 Autonomous Utilization-Based Frequency Control Status (R0)
request because the processor has detected that utilization is 
low.
6 VR Therm Alert Status (R0)
request due to a thermal aler t from the Voltage Regulator.
7 Reserved.Table 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-269MODEL-SPECIFIC REGISTERS (MSRS)
8 Electrical Design Point Status (R0)
request due to electrical desi gn point constraints (e.g., 
maximum electrical current consumption).
9 Core Power Limiting Status (R0)
request due to domain-level power limiting.
10 Package-Level Power Limiting PL1 Status (R0)
request due to package-level power limiting PL1.
11 Package-Level PL2 Power Limiting Status (R0)
request due to package-level power limiting PL2.
12 Max Turbo Limit Status (R0)
request due to multi- core turbo limits.
request due to Turbo transition  attenuation. This prevents 
performance degradation due to frequent operating ratio changes.
15:14 Reserved.16 PROCHOT Log 
When set, indicates that the PR OCHOT Status bit has asserted 
When set, indicates that the Th ermal Status bit has asserted 
19:18 Reserved.20 Graphics Driver Log 
When set, indicates that the Gr aphics Driver Status bit has 
21 Autonomous Utilization-Based Frequency Control Log 
When set, indicates that the Autonomous Utilization-Based 
Frequency Control Status bit has asserted since the log bit was last cleared.
22 VR Therm Alert Log 
When set, indicates that the VR Therm Alert Status bit has 
This log bit will remain set until cleared by software writing 0.Table 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitect ure) (Contd.)
Register Information / Bit Fields Bit Description Scope2-270 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
23 Reserved.
24 Electrical Design Point Log 
When set, indicates th at the EDP Status bit has asserted since 
This log bit will remain set unti l cleared by software writing 0.
When set, indicates that the Core  Power Limiting Status bit has 
26 Package-Level PL1 Power Limiting Log 
When set, indicates that the Package Level PL1 Power Limiting 
Status bit has asserted since the log bit was last cleared.
27 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting 
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has 
When set, indicates that th e Turbo Transition Attenuation 
Register Address: 6B0H, 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Processor Graphics (R/W)
(Frequency refers to processor graphics frequency.)Package
request due to assertion of external PROCHOT.
5 Autonomous Utilization-Based Frequency Control Status (R0) 
low.Table 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-271MODEL-SPECIFIC REGISTERS (MSRS)
7 Reserved.8 Electrical Design Point Status (R0)
9 Graphics Power Limiting Status (R0)
19:18 Reserved.
20 Graphics Driver Log 
Frequency Control Status bit has asserted since the log bit was 
last cleared.
23 Reserved.Table 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitect ure) (Contd.)
Register Information / Bit Fields Bit Description Scope2-272 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6B1H, 1713 MSR_RING_PERF_LIMIT_REASONS

Indicator of Frequency Clipping in the Ring Interconnect (R/W)
(Frequency refers to ring interconnect in the uncore.)Package
5:2 Reserved.6 VR Therm Alert Status (R0)
request due to electrical design point constraints (e.g., 
maximum electrical current consumption).Table 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-273MODEL-SPECIFIC REGISTERS (MSRS)
15:12 Reserved.16 PROCHOT Log 
When set, indicates that the ED P Status bit has asserted since 
When set, indicates th at the Core Power Limiting Status bit has 
Register Information / Bit Fields Bit Description Scope2-274 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 0, Performance Counter 1 Package
Register Address: 721H, 1824 MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 3, Counter 0 Event Select MSR PackageTable 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-275MODEL-SPECIFIC REGISTERS (MSRS)
2.13.2  Additional Residency MSRs Supported in 4th Generation Intel® Core™  Processors
The 4th generation Intel® Core™ processor family (based on Haswell microarchitecture) with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_4 5H supports the MSR interfaces listed in Table 2-20, Table 2-21, Table 
2-29, Table 2-30, and Table 2-31. Register Address: 731H, 1841 MSR_UNC_CBO_3_PERFEVTSEL1
See Table 2-20, Table 2-21, Table 2-22, Table 2-25, and Table 2-29 for other MSR definitions applicable to processors with a CP UID 
Signature DisplayFamily_DisplayMod el value of 063CH or 06_46H. 
Table 2-31.  Additional Residency MSRs Supported by  4th Generation Intel® Core™ Processors with a 
CPUID Signature DisplayFamily_ DisplayModel Value of 06_45H
Register Address: Hex, Decimal Register Name
0001b: C2
0100b: C7
0101b: C7s0110b: C8
0111b: C9
1000b: C10
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved.15 CFG Lock (R/WO)
24:16 Reserved.Table 2-30.  MSRs Supported by 4th Generation Intel®  Core™ Processors (Haswell Microarchitect ure) (Contd.)
Register Information / Bit Fields Bit Description Scope2-276 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.14 MSRS IN THE INTEL® XEON® PR OCESSOR E5 V3 AND E7 V3 PRODUCT 
FAMILY
The Intel® Xeon® processor E5 v3 family and the Intel® Xeon® processor E7 v3 family are based on Haswell-E 
microarchitecture (CPUID Signature DisplayFamily_DisplayModel value of 06_3F). These processors support the MSR interfaces listed in Table 2-20, Table 2-29, and Table 2-32. 25 C3 State Auto Demotion Enable (R/W)
Register Address: 630H, 1584 MSR_PKG_C8_RESIDENCY
59:0 Package C8 Residency Counter (R/O)
Value since last reset that this packag e is in processor-specific C8 states. 
Register Address: 631H, 1585 MSR_PKG_C9_RESIDENCY
59:0 Package C9 Residency Counter (R/O)
Value since last reset that this packag e is in processor-specific C9 states. 

59:0 Package C10 Residency Counter (R/O)
Value since last reset that  this package is in proc essor-specific C10 states. 
See Table 2-20, Table 2-21, Table 2-22, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with a CP UID 
Signature DisplayFamily_Disp layModel value of 06_45H.
Table 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Address: 35H, 53 MSR_CORE_THREAD_COUNTTable 2-31.  Additional Residency MSRs Supported by  4th Generation Intel® Core™ Processors with a 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-277MODEL-SPECIFIC REGISTERS (MSRS)
Configured State of Enabled Processor Core Count and Logical Processor Count (R/O)
• After a Power-On RESET, enumerates factory configuration of the number of processor cores and logical 
processors in the physical package.
• Following the sequence of (i) BIOS modified a Configuration Mask which selects a subset of processor cores to be 
active post RESET and (ii) a RESET ev ent after the modifi cation, enumerates the current configuration of enabled 
processor core count and logical processor count in the physical package.Package
15:0 THREAD_COUNT (R/O)
The number of logical processors that are currently enabled (by either 
factory configuration or BIOS configuration) in the physical package.
31:16 Core_COUNT (R/O)
The number of processor cores that are currently enabled (by either factory 
configuration or BIOS configuration) in the physical package.
Register Address: 53H, 83 MSR_THREAD_ID_INFO
A Hardware Assigned ID for the Logical Processor (R/O) Thread
7:0 Logical_Processor_ID (R/O)
An implementation-specific numerical value physically assigned to each 
logical processor. This ID is not related to Initia l APIC ID or x2APIC ID, it is 
unique within a physical package.
ACPI C-states.
2:0 Package C-State Limit (R/W)
000b: C0/C1 (no package C-state support)
001b: C2010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the processor are 
9:3 Reserved.10 I/O MWAIT Redirection Enable (R/W)
15 CFG Lock (R/WO)24:16 Reserved.
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)Table 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description Scope2-278 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)30 Package C State Undemotion Enable (R/W)
7:0 Count
8 MCG_CTL_P9M C G _ E X T _ P10 MCP_CMCI_P
11 MCG_TES_P
15:12 Reserved.23:16 MCG_EXT_CNT
24 MCG_SER_P
25 MCG_EM_P26 MCG_ELOG_P
If set to 1, indicates that  the SMM code access rest riction is supported and a 
host-space interface available to SMM handler.
If set to 1, indicates th at the SMM long flow indi cator is supported and a 
When set, enables IMC status bank to  log additional info in bits 36:32.
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.PackageTable 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description ScopeVol. 4 2-279MODEL-SPECIFIC REGISTERS (MSRS)
Maximum turbo ratio limi t of 5 core active.Package
Maximum turbo ratio limi t of 6 core active.Package
Maximum turbo ratio limi t of 7 core active.Package
Maximum turbo ratio limi t of 8 core active.Package
39:32 Maximum Ratio Limit for 13C
47:40 Maximum Ratio Limit for 14C
55:48 Maximum Ratio Limit for 15C
63:56 Maximum Ratio Limit for16C
Maximum turbo ratio limi t of 16 core active.Package
Register Address: 1AFH, 431 MSR_TURBO_RATIO_LIMIT2
7:0 Maximum Ratio Limit for 17C
Maximum turbo ratio limi t of 17 core active. PackageTable 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description Scope2-280 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
15:8 Maximum Ratio Limit for 18C
Maximum turbo ratio limi t of 18 core active. Package
62:16 Reserved. Package
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1, and MSR_TURBO_RATIO_LIMIT2.
Bank MC5 reports MC errors from the Intel QPI 0 module.Package

Bank MC7 reports MC errors from the home agent HA 0.Package
Register Address: 41EH, 1054 IA32_MC7_ADDRTable 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description ScopeVol. 4 2-281MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC8 reports MC errors from the home agent HA 1.Package
Register Address: 42BH, 1067 IA32_MC10_MISCTable 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description Scope2-282 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 438H, 1080 IA32_MC14_CTLTable 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description ScopeVol. 4 2-283MODEL-SPECIFIC REGISTERS (MSRS)

Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9, 
CBo12, CBo15.PackageTable 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description Scope2-284 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
CBo12, CBo15.Package
Bank MC18 reports MC errors from the fo llowing pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7, 
CBo10, CBo13, CBo16.Package
Bank MC19 reports MC errors from the fo llowing pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8, 
CBo11, CBo14, CBo17.Package
Register Address: 44FH, 1103 IA32_MC19_MISCTable 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description ScopeVol. 4 2-285MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC20 reports MC errors from the Intel QPI 1 module.Package
Bank MC21 reports MC errors from the Intel QPI 2 module.Package
7:4 Reserved. Package
Energy related information (in Joules) is based on the multiplier, 1/2^ESU; 
0EH (or 61 micro-joules).Package
63:20 Reserved.Table 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description Scope2-286 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Energy Consumed by DRAM devices. Package
31:0 Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM 
RAPL mode 0 (Direct VR).
Register Address: 61EH, 1566 MSR_PCIE_PLL_RATIO
Configuration of PCIE PLL Relative to BCLK(R/W) Package1:0 PCIE Ratio (R/W)
00b: Use 5:5 mapping for100MHz operation (default).01b: Use 5:4 mapping for125MHz operation.
10b: Use 5:3 mapping for166MHz operation.
11b: Use 5:2 mapping for250MHz operation.Package
2L P L L  S e l e c t  ( R / W )
If 1, use configured setting of PCIE Ratio.Package
3L O N G  R E S E T  ( R / W )
If 1, wait an additional time-out  before re-locking Gen2/Gen3 PLLs.Package
Register Address: 620H, 1568 MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W) 
Out of reset, the min_ra tio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to 
these fields allows software to co ntrol the minimum and the maximum frequency that hardware will select.Package
6:0 MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
7 Reserved.
14:8 MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
Reserved (R/O) 
Reads return 0.PackageTable 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family

Register Information / Bit Fields Bit Description ScopeVol. 4 2-287MODEL-SPECIFIC REGISTERS (MSRS)
When set, processor core  frequency is reduced below the operating system 
request due to assertio n of external PROCHOT.
When set, frequency is reduced below the operating system request due to 
a thermal event.
2 Power Budget Management Status (R0) 
PBM limit
3 Platform Configuration Services Status (R0) 
PCS limit
4 Reserved.5 Autonomous Utilization-Based Frequency Control Status (R0) 
When set, frequency is reduced below the operating system request 
because the processor has detected that utilization is low.
a thermal alert from the Voltage Regulator.
electrical design point constraints (e.g., maximum electrical current 
10 Multi-Core Turbo Status (R0) 
Multi-Core Turbo limits.
13 Core Frequency P1 Status (R0) 
When set, frequency is reduced below max non-turbo P1.
14 Core Max N-Core Turbo Frequency Limiting Status (R0) 
When set, frequency is reduced below max n-core turbo frequency.
15 Core Frequency Limiting Status (R0) 
When set, frequency is reduced below the operating system request.
When set, indicates that the PROCHOT Status bit ha s asserted since the log 
This log bit will remain  set until cleared by  software writing 0.Table 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description Scope2-288 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
This log bit will remain  set until cleared by  software writing 0.
18 Power Budget Management Log 
When set, indicates that the PBM Stat us bit has asserted since the log bit 
19 Platform Configuration Services Log 
When set, indicates that the PCS Stat us bit has asserted since the log bit 
20 Reserved.21 Autonomous Utilization-Based Frequency Control Log 
When set, indicates that the AUBFC Status bit has a sserted since the log bit 
23 Reserved.24 Electrical Design Point Log 
When set, indicates that the EDP Stat us bit has asserted since the log bit 
25 Reserved.
26 Multi-Core Turbo Log 
When set, indicates that the Multi-Core Turbo Status bit has asserted since 
28:27 Reserved.
29 Core Frequency P1 Log
When set, indicates that  the Core Frequency P1 Status bit has asserted 
30 Core Max N-Core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency Limiting 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-289MODEL-SPECIFIC REGISTERS (MSRS)
2.14.1  Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
The Intel Xeon Processor E5 v3 and E7 v3 families ar e based on Haswell-E microarchitecture. The MSR-based 
uncore PMU interfaces are listed in Table 2-33. For comp lete details of the uncore PMU, refer to the Intel Xeon 
Processor E5 v3 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3FH.31 Core Frequency Limiting Log
When set, indicates th at the Core Frequency Limiting Status bit has 
Monitoring Event Select Register (R/W)
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.Thread
7:0 EventID (R/W)
Event encoding:
0x0: No monitoring.
0x1: L3 occupancy monitoring.All other encoding reserved.
31:8 Reserved.41:32 RMID (R/W)
Monitoring Counter Register (R/O)
61:0 Resource Monitored Data 
63 Error: If 1, indicates an unsupported  RMID or event type was written to 
Resource Associatio n Register (R/W) Thread
9:0 RMID 
63: 10 Reserved.
See Table 2-20 and Table 2-29 for other MSR definitions applicable to processors with a CPUID Signature DisplayFamily_DisplayMo del 
value of 06_3FH.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher tha n the fac-
tory-set configuration is dependent on features specific to the processor and the platform.Table 2-32.  Additional MSRs Supported by  the Intel® Xeon® Processor E5 v3 Family
Register Information / Bit Fields Bit Description Scope2-290 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33.  Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
Register Address: 700H, 1792 MSR_PMON_GLOBAL_CTL
Register Address: 701H, 1793 MSR_PMON_GLOBAL_STATUS
Register Address: 702H, 1794 MSR_PMON_GLOBAL_CONFIG
Register Address: 703H, 1795 MSR_U_PMON_UCLK_FIXED_CTL
Uncore U-Box UCLK Fixed Counter Control Package
Register Address: 704H, 1796 MSR_U_PMON_UCLK_FIXED_CTR
Uncore U-Box UCLK Fixed Counter Package
Register Address: 705H, 1797 MSR_U_PMON_EVNTSEL0
Uncore U-Box Perfmon Event Select for U-Box Counter 0 Package
Register Address: 706H, 1798 MSR_U_PMON_EVNTSEL1
Uncore U-Box Perfmon Event Select for U-Box Counter 1 Package
Register Address: 708H, 1800 MSR_U_PMON_BOX_STATUS
Uncore U-Box Perfmon U-Box Wide Status Package
Register Address: 709H, 1801 MSR_U_PMON_CTR0
Uncore U-Box Perfmon Counter 0 Package
Register Address: 70AH, 1802 MSR_U_PMON_CTR1
Uncore U-Box Perfmon Counter 1 Package
Register Address: 710H, 1808 MSR_PCU_PMON_BOX_CTL
Uncore PCU Perfmon for PC U-Box-Wide Control Package
Register Address: 711H, 1809 MSR_PCU_PMON_EVNTSEL0
Register Address: 712H, 1810 MSR_PCU_PMON_EVNTSEL1
Register Address: 713H, 1811 MSR_PCU_PMON_EVNTSEL2
Register Address: 714H, 1812 MSR_PCU_PMON_EVNTSEL3
Register Address: 715H, 1813 MSR_PCU_PMON_BOX_FILTER
Uncore PCU Perfmon Box-Wide Filter Package
Register Address: 716H, 1814 MSR_PCU_PMON_BOX_STATUS
Register Address: 717H, 1815 MSR_PCU_PMON_CTR0
Register Address: 718H, 1816 MSR_PCU_PMON_CTR1Vol. 4 2-291MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 719H, 1817 MSR_PCU_PMON_CTR2
Register Address: 71AH, 1818 MSR_PCU_PMON_CTR3
Register Address: 720H, 1824 MSR_S0_PMON_BOX_CTL
Uncore SBo 0 Perfmon for SBo 0 Box-Wide Control Package
Register Address: 721H, 1825 MSR_S0_PMON_EVNTSEL0

Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 0 Package
Register Address: 722H, 1826 MSR_S0_PMON_EVNTSEL1
Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 1 Package
Register Address: 723H, 1827 MSR_S0_PMON_EVNTSEL2
Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 2 Package
Register Address: 724H, 1828 MSR_S0_PMON_EVNTSEL3
Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 3 Package
Register Address: 725H, 1829 MSR_S0_PMON_BOX_FILTER
Uncore SBo 0 Perfmon Box-Wide Filter Package
Register Address: 726H, 1830 MSR_S0_PMON_CTR0
Uncore SBo 0 Perfmon Counter 0 Package
Register Address: 727H, 1831 MSR_S0_PMON_CTR1
Uncore SBo 0 Perfmon Counter 1 Package
Register Address: 728H, 1832 MSR_S0_PMON_CTR2
Uncore SBo 0 Perfmon Counter 2 Package
Register Address: 729H, 1833 MSR_S0_PMON_CTR3
Uncore SBo 0 Perfmon Counter 3 Package
Register Address: 72AH, 1834 MSR_S1_PMON_BOX_CTL
Uncore SBo 1 Perfmon for SBo 1 Box-Wide Control Package
Register Address: 72BH, 1835 MSR_S1_PMON_EVNTSEL0
Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 0 Package
Register Address: 72CH, 1836 MSR_S1_PMON_EVNTSEL1
Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 1 Package
Register Address: 72DH, 1837 MSR_S1_PMON_EVNTSEL2
Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 2 Package
Register Address: 72EH, 1838 MSR_S1_PMON_EVNTSEL3
Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 3 Package
Register Address: 72FH, 1839 MSR_S1_PMON_BOX_FILTER
Uncore SBo 1 Perfmon Box-Wide Filter PackageTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-292 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 730H, 1840 MSR_S1_PMON_CTR0
Uncore SBo 1 Perfmon Counter 0 Package
Register Address: 731H, 1841 MSR_S1_PMON_CTR1
Uncore SBo 1 Perfmon Counter 1 Package
Register Address: 732H, 1842 MSR_S1_PMON_CTR2
Uncore SBo 1 Perfmon Counter 2 Package
Register Address: 733H, 1843 MSR_S1_PMON_CTR3
Uncore SBo 1 Perfmon Counter 3 Package
Register Address: 734H, 1844 MSR_S2_PMON_BOX_CTL
Uncore SBo 2 Perfmon for SBo 2 Box-Wide Control Package
Register Address: 735H, 1845 MSR_S2_PMON_EVNTSEL0
Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 0 Package
Register Address: 736H, 1846 MSR_S2_PMON_EVNTSEL1
Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 1 Package
Register Address: 737H, 1847 MSR_S2_PMON_EVNTSEL2
Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 2 Package
Register Address: 738H, 1848 MSR_S2_PMON_EVNTSEL3
Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 3 Package
Register Address: 739H, 1849 MSR_S2_PMON_BOX_FILTER
Uncore SBo 2 Perfmon Box-Wide Filter Package
Register Address: 73AH, 1850 MSR_S2_PMON_CTR0
Uncore SBo 2 Perfmon Counter 0 Package
Register Address: 73BH, 1851 MSR_S2_PMON_CTR1
Uncore SBo 2 Perfmon Counter 1 Package
Register Address: 73CH, 1852 MSR_S2_PMON_CTR2
Uncore SBo 2 Perfmon Counter 2 Package
Register Address: 73DH, 1853 MSR_S2_PMON_CTR3
Uncore SBo 2 Perfmon Counter 3 Package
Register Address: 73EH, 1854 MSR_S3_PMON_BOX_CTL
Uncore SBo 3 Perfmon for SBo 3 Box-Wide Control Package
Register Address: 73FH, 1855 MSR_S3_PMON_EVNTSEL0
Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 0 Package
Register Address: 740H, 1856 MSR_S3_PMON_EVNTSEL1
Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 1 Package
Register Address: 741H, 1857 MSR_S3_PMON_EVNTSEL2
Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 2 Package
Register Address: 742H, 1858 MSR_S3_PMON_EVNTSEL3Table 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-293MODEL-SPECIFIC REGISTERS (MSRS)
Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 3 Package
Register Address: 743H, 1859 MSR_S3_PMON_BOX_FILTER
Uncore SBo 3 Perfmon Box-Wide Filter Package
Register Address: 744H, 1860 MSR_S3_PMON_CTR0
Uncore SBo 3 Perfmon Counter 0 Package
Register Address: 745H, 1861 MSR_S3_PMON_CTR1
Uncore SBo 3 Perfmon Counter 1 Package
Register Address: 746H, 1862 MSR_S3_PMON_CTR2
Uncore SBo 3 Perfmon Counter 2 Package
Register Address: 747H, 1863 MSR_S3_PMON_CTR3
Uncore SBo 3 Perfmon Counter 3 Package
Register Address: E00H, 3584 MSR_C0_PMON_BOX_CTL
Uncore C-Box 0 Perfmon for Box-Wide Control Package
Register Address: E01H, 3585 MSR_C0_PMON_EVNTSEL0
Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 0 Package
Register Address: E02H, 3586 MSR_C0_PMON_EVNTSEL1
Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 1 Package
Register Address: E03H, 3587 MSR_C0_PMON_EVNTSEL2
Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 2 Package
Register Address: E04H, 3588 MSR_C0_PMON_EVNTSEL3
Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 3 Package
Register Address: E05H, 3589 MSR_C0_PMON_BOX_FILTER0
Uncore C-Box 0 Perfmon Box Wide Filter 0 Package
Register Address: E06H, 3590 MSR_C0_PMON_BOX_FILTER1
Uncore C-Box 0 Perfmon Box Wide Filter 1 Package
Register Address: E07H, 3591 MSR_C0_PMON_BOX_STATUS
Uncore C-Box 0 Perfmon Box Wide Status Package
Register Address: E08H, 3592 MSR_C0_PMON_CTR0
Uncore C-Box 0 Perfmon Counter 0 Package
Register Address: E09H, 3593 MSR_C0_PMON_CTR1
Uncore C-Box 0 Perfmon Counter 1 Package
Register Address: E0AH, 3594 MSR_C0_PMON_CTR2
Uncore C-Box 0 Perfmon Counter 2 Package
Register Address: E0BH, 3595 MSR_C0_PMON_CTR3
Uncore C-Box 0 Perfmon Counter 3 Package
Register Address: E10H, 3600 MSR_C1_PMON_BOX_CTL
Uncore C-Box 1 Perfmon for Box-Wide Control PackageTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-294 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E11H, 3601 MSR_C1_PMON_EVNTSEL0
Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 0 Package
Register Address: E12H, 3602 MSR_C1_PMON_EVNTSEL1
Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 1 Package
Register Address: E13H, 3603 MSR_C1_PMON_EVNTSEL2
Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 2 Package
Register Address: E14H, 3604 MSR_C1_PMON_EVNTSEL3
Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 3 Package
Register Address: E15H, 3605 MSR_C1_PMON_BOX_FILTER0
Uncore C-Box 1 Perfmon Box Wide Filter 0 Package
Register Address: E16H, 3606 MSR_C1_PMON_BOX_FILTER1
Register Address: E17H, 3607 MSR_C1_PMON_BOX_STATUS
Uncore C-Box 1 Perfmon Box Wide Status Package
Register Address: E18H, 3608 MSR_C1_PMON_CTR0
Uncore C-Box 1 Perfmon Counter 0 Package
Register Address: E19H, 3609 MSR_C1_PMON_CTR1
Uncore C-Box 1 Perfmon Counter 1 Package
Register Address: E1AH, 3610 MSR_C1_PMON_CTR2
Uncore C-Box 1 Perfmon Counter 2 Package
Register Address: E1BH, 3611 MSR_C1_PMON_CTR3
Uncore C-Box 1 Perfmon Counter 3 Package
Register Address: E20H, 3616 MSR_C2_PMON_BOX_CTL
Uncore C-Box 2 Perfmon for Box-Wide Control Package
Register Address: E21H, 3617 MSR_C2_PMON_EVNTSEL0
Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 0 Package
Register Address: E22H, 3618 MSR_C2_PMON_EVNTSEL1
Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 1 Package
Register Address: E23H, 3619 MSR_C2_PMON_EVNTSEL2
Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 2 Package
Register Address: E24H, 3620 MSR_C2_PMON_EVNTSEL3
Uncore C-Box 2 Perfmon Event select for C-Box 2 Counter 3 Package
Register Address: E25H, 3621 MSR_C2_PMON_BOX_FILTER0
Uncore C-Box 2 Perfmon Box Wide Filter 0 Package
Register Address: E26H, 3622 MSR_C2_PMON_BOX_FILTER1
Register Address: E27H, 3623 MSR_C2_PMON_BOX_STATUSTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-295MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 2 Perfmon Box Wide Status Package
Register Address: E28H, 3624 MSR_C2_PMON_CTR0
Uncore C-Box 2 Perfmon Counter 0 Package
Register Address: E29H, 3625 MSR_C2_PMON_CTR1
Uncore C-Box 2 Perfmon Counter 1 Package
Register Address: E2AH, 3626 MSR_C2_PMON_CTR2
Uncore C-Box 2 Perfmon Counter 2 Package
Register Address: E2BH, 3627 MSR_C2_PMON_CTR3
Uncore C-Box 2 Perfmon Counter 3 Package
Register Address: E30H, 3632 MSR_C3_PMON_BOX_CTL
Uncore C-Box 3 Perfmon for Box-Wide Control Package
Register Address: E31H, 3633 MSR_C3_PMON_EVNTSEL0
Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 0 Package
Register Address: E32H, 3634 MSR_C3_PMON_EVNTSEL1
Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 1 Package
Register Address: E33H, 3635 MSR_C3_PMON_EVNTSEL2
Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 2 Package
Register Address: E34H, 3636 MSR_C3_PMON_EVNTSEL3
Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 3 Package
Register Address: E35H, 3637 MSR_C3_PMON_BOX_FILTER0
Uncore C-Box 3 Perfmon Box Wide Filter 0 Package

Register Address: E36H, 3638 MSR_C3_PMON_BOX_FILTER1
Register Address: E37H, 3639 MSR_C3_PMON_BOX_STATUS
Uncore C-Box 3 Perfmon Box Wide Status Package
Register Address: E38H, 3640 MSR_C3_PMON_CTR0
Uncore C-Box 3 Perfmon Counter 0 Package
Register Address: E39H, 3641 MSR_C3_PMON_CTR1
Uncore C-Box 3 Perfmon Counter 1 Package
Register Address: E3AH, 3642 MSR_C3_PMON_CTR2
Uncore C-Box 3 Perfmon Counter 2 Package
Register Address: E3BH, 3643 MSR_C3_PMON_CTR3
Uncore C-Box 3 Perfmon Counter 3 Package
Register Address: E40H, 3648 MSR_C4_PMON_BOX_CTL
Uncore C-Box 4 Perfmon for Box-Wide Control Package
Register Address: E41H, 3649 MSR_C4_PMON_EVNTSEL0
Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 0 PackageTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-296 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E42H, 3650 MSR_C4_PMON_EVNTSEL1
Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 1 Package
Register Address: E43H, 3651 MSR_C4_PMON_EVNTSEL2
Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 2 Package
Register Address: E44H, 3652 MSR_C4_PMON_EVNTSEL3
Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 3 Package
Register Address: E45H, 3653 MSR_C4_PMON_BOX_FILTER0
Uncore C-Box 4 Perfmon Box Wide Filter 0 Package
Register Address: E46H, 3654 MSR_C4_PMON_BOX_FILTER1
Register Address: E47H, 3655 MSR_C4_PMON_BOX_STATUS
Uncore C-Box 4 Perfmon Box Wide Status Package
Register Address: E48H, 3656 MSR_C4_PMON_CTR0
Uncore C-Box 4 Perfmon Counter 0 Package
Register Address: E49H, 3657 MSR_C4_PMON_CTR1
Uncore C-Box 4 Perfmon Counter 1 Package
Register Address: E4AH, 3658 MSR_C4_PMON_CTR2
Uncore C-Box 4 Perfmon Counter 2 Package
Register Address: E4BH, 3659 MSR_C4_PMON_CTR3
Uncore C-Box 4 Perfmon Counter 3 Package
Register Address: E50H, 3664 MSR_C5_PMON_BOX_CTL
Uncore C-Box 5 Perfmon for Box-Wide Control Package
Register Address: E51H, 3665 MSR_C5_PMON_EVNTSEL0
Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 0 Package
Register Address: E52H, 3666 MSR_C5_PMON_EVNTSEL1
Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 1 Package
Register Address: E53H, 3667 MSR_C5_PMON_EVNTSEL2
Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 2 Package
Register Address: E54H, 3668 MSR_C5_PMON_EVNTSEL3
Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 3 Package
Register Address: E55H, 3669 MSR_C5_PMON_BOX_FILTER0
Uncore C-Box 5 Perfmon Box Wide Filter 0 Package
Register Address: E56H, 3670 MSR_C5_PMON_BOX_FILTER1
Uncore C-Box 5 Perfmon Box Wide Filter 1 Package
Register Address: E57H, 3671 MSR_C5_PMON_BOX_STATUS
Uncore C-Box 5 Perfmon Box Wide Status Package
Register Address: E58H, 3672 MSR_C5_PMON_CTR0Table 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-297MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 5 Perfmon Counter 0 Package
Register Address: E59H, 3673 MSR_C5_PMON_CTR1
Uncore C-Box 5 Perfmon Counter 1 Package
Register Address: E5AH, 3674 MSR_C5_PMON_CTR2
Uncore C-Box 5 Perfmon Counter 2 Package
Register Address: E5BH, 3675 MSR_C5_PMON_CTR3
Uncore C-Box 5 Perfmon Counter 3 Package
Register Address: E60H, 3680 MSR_C6_PMON_BOX_CTL
Uncore C-Box 6 Perfmon for Box-Wide Control Package
Register Address: E61H, 3681 MSR_C6_PMON_EVNTSEL0
Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 0 Package
Register Address: E62H, 3682 MSR_C6_PMON_EVNTSEL1
Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 1 Package
Register Address: E63H, 3683 MSR_C6_PMON_EVNTSEL2
Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 2 Package
Register Address: E64H, 3684 MSR_C6_PMON_EVNTSEL3
Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 3 Package
Register Address: E65H, 3685 MSR_C6_PMON_BOX_FILTER0
Uncore C-Box 6 Perfmon Box Wide Filter 0 Package
Register Address: E66H, 3686 MSR_C6_PMON_BOX_FILTER1
Uncore C-Box 6 Perfmon Box Wide Filter 1 Package
Register Address: E67H, 3687 MSR_C6_PMON_BOX_STATUS
Uncore C-Box 6 Perfmon Box Wide Status Package
Register Address: E68H, 3688 MSR_C6_PMON_CTR0
Uncore C-Box 6 Perfmon Counter 0 Package
Register Address: E69H, 3689 MSR_C6_PMON_CTR1
Uncore C-Box 6 Perfmon Counter 1 Package
Register Address: E6AH, 3690 MSR_C6_PMON_CTR2
Uncore C-Box 6 Perfmon Counter 2 Package
Register Address: E6BH, 3691 MSR_C6_PMON_CTR3
Uncore C-Box 6 Perfmon Counter 3 Package
Register Address: E70H, 3696 MSR_C7_PMON_BOX_CTL
Uncore C-Box 7 Perfmon for Box-Wide Control Package
Register Address: E71H, 3697 MSR_C7_PMON_EVNTSEL0
Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 0 Package
Register Address: E72H, 3698 MSR_C7_PMON_EVNTSEL1
Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 1 PackageTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-298 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E73H, 3699 MSR_C7_PMON_EVNTSEL2
Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 2 Package
Register Address: E74H, 3700 MSR_C7_PMON_EVNTSEL3
Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 3 Package
Register Address: E75H, 3701 MSR_C7_PMON_BOX_FILTER0
Uncore C-Box 7 Perfmon Box Wide Filter 0 Package
Register Address: E76H, 3702 MSR_C7_PMON_BOX_FILTER1
Uncore C-Box 7 Perfmon Box Wide Filter 1 Package
Register Address: E77H, 3703 MSR_C7_PMON_BOX_STATUS
Uncore C-Box 7 Perfmon Box Wide Status Package
Register Address: E78H, 3704 MSR_C7_PMON_CTR0
Uncore C-Box 7 Perfmon Counter 0 Package
Register Address: E79H, 3705 MSR_C7_PMON_CTR1
Uncore C-Box 7 Perfmon Counter 1 Package
Register Address: E7AH, 3706 MSR_C7_PMON_CTR2
Uncore C-Box 7 Perfmon Counter 2 Package
Register Address: E7BH, 3707 MSR_C7_PMON_CTR3
Uncore C-Box 7 Perfmon Counter 3 Package
Register Address: E80H, 3712 MSR_C8_PMON_BOX_CTL
Register Address: E81H, 3713 MSR_C8_PMON_EVNTSEL0
Register Address: E82H, 3714 MSR_C8_PMON_EVNTSEL1
Register Address: E83H, 3715 MSR_C8_PMON_EVNTSEL2
Register Address: E84H, 3716 MSR_C8_PMON_EVNTSEL3
Register Address: E85H, 3717 MSR_C8_PMON_BOX_FILTER0
Uncore C-Box 8 Perfmon Box Wide Filter 0 Package
Register Address: E86H, 3718 MSR_C8_PMON_BOX_FILTER1
Uncore C-Box 8 Perfmon Box Wide Filter 1 Package
Register Address: E87H, 3719 MSR_C8_PMON_BOX_STATUS
Uncore C-Box 8 Perfmon Box Wide Status Package
Register Address: E88H, 3720 MSR_C8_PMON_CTR0
Register Address: E89H, 3721 MSR_C8_PMON_CTR1Table 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-299MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E8AH, 3722 MSR_C8_PMON_CTR2
Register Address: E8BH, 3723 MSR_C8_PMON_CTR3
Register Address: E90H, 3728 MSR_C9_PMON_BOX_CTL
Register Address: E91H, 3729 MSR_C9_PMON_EVNTSEL0
Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 0 Package
Register Address: E92H, 3730 MSR_C9_PMON_EVNTSEL1
Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 1 Package
Register Address: E93H, 3731 MSR_C9_PMON_EVNTSEL2
Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 2 Package
Register Address: E94H, 3732 MSR_C9_PMON_EVNTSEL3
Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 3 Package
Register Address: E95H, 3733 MSR_C9_PMON_BOX_FILTER0
Uncore C-Box 9 Perfmon Box Wide Filter 0 Package
Register Address: E96H, 3734 MSR_C9_PMON_BOX_FILTER1
Uncore C-Box 9 Perfmon Box Wide Filter 1 Package
Register Address: E97H, 3735 MSR_C9_PMON_BOX_STATUS
Uncore C-Box 9 Perfmon Box Wide Status Package
Register Address: E98H, 3736 MSR_C9_PMON_CTR0
Register Address: E99H, 3737 MSR_C9_PMON_CTR1
Register Address: E9AH, 3738 MSR_C9_PMON_CTR2
Register Address: E9BH, 3739 MSR_C9_PMON_CTR3
Register Addres s: EA0H, 3744 MSR_C10_PMON_BOX_CTL
Uncore C-Box 10 Perfmon Lo cal Box Wide Control Package
Register Addres s: EA1H, 3745 MSR_C10_PMON_EVNTSEL0
Register Addres s: EA2H, 3746 MSR_C10_PMON_EVNTSEL1

Register Addres s: EA3H, 3747 MSR_C10_PMON_EVNTSEL2
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 2 PackageTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-300 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: EA4H, 3748 MSR_C10_PMON_EVNTSEL3
Register Address: EA5H, 3749 MSR_C10_PMON_BOX_FILTER0
Uncore C-Box 10 Perfmon Box Wide Filter 0 Package
Register Address: EA6H, 3750 MSR_C10_PMON_BOX_FILTER1
Uncore C-Box 10 Perfmon Box Wide Filter 1 Package
Register Address: EA7H, 3751 MSR_C10_PMON_BOX_STATUS
Uncore C-Box 10 Perfmon Box Wide Status Package
Register Address: EA8H, 3752 MSR_C10_PMON_CTR0
Register Address: EA9H, 3753 MSR_C10_PMON_CTR1
Uncore C-Box 10 perfmon Counter 1 Package
Register Address: EAAH, 3754 MSR_C10_PMON_CTR2
Register Address: EABH, 3755 MSR_C10_PMON_CTR3
Register Address: EB0H, 3760 MSR_C11_PMON_BOX_CTL
Uncore C-Box 11 Perfmon Local Box Wide Control Package
Register Address: EB1H, 3761 MSR_C11_PMON_EVNTSEL0
Register Address: EB2H, 3762 MSR_C11_PMON_EVNTSEL1
Register Address: EB3H, 3763 MSR_C11_PMON_EVNTSEL2
Register Address: EB4H, 3764 MSR_C11_PMON_EVNTSEL3
Uncore C-box 11 Perfmon Event Select for C-Box 11 Counter 3 Package
Register Address: EB5H, 3765 MSR_C11_PMON_BOX_FILTER0
Uncore C-Box 11 Perfmon Box Wide Filter 0 Package
Register Address: EB6H, 3766 MSR_C11_PMON_BOX_FILTER1
Uncore C-Box 11 Perfmon Box Wide Filter 1 Package
Register Address: EB7H, 3767 MSR_C11_PMON_BOX_STATUS
Uncore C-Box 11 Perfmon Box Wide Status Package
Register Address: EB8H, 3768 MSR_C11_PMON_CTR0
Register Address: EB9H, 3769 MSR_C11_PMON_CTR1
Register Address: EBAH, 3770 MSR_C11_PMON_CTR2Table 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-301MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: EBBH, 3771 MSR_C11_PMON_CTR3
Register Address: EC0H, 3776 MSR_C12_PMON_BOX_CTL
Register Address: EC1H, 3777 MSR_C12_PMON_EVNTSEL0
Register Address: EC2H, 3778 MSR_C12_PMON_EVNTSEL1
Register Address: EC3H, 3779 MSR_C12_PMON_EVNTSEL2
Register Address: EC4H, 3780 MSR_C12_PMON_EVNTSEL3
Register Address: EC5H, 3781 MSR_C12_PMON_BOX_FILTER0
Uncore C-Box 12 Perfmon Box Wide Filter 0 Package
Register Address: EC6H, 3782 MSR_C12_PMON_BOX_FILTER1
Uncore C-Box 12 Perfmon Box Wide Filter 1 Package
Register Address: EC7H, 37833783 MSR_C12_PMON_BOX_STATUS
Uncore C-Box 12 Perfmon Box Wide Status Package
Register Address: EC8H, 3784 MSR_C12_PMON_CTR0
Register Address: EC9H, 3785 MSR_C12_PMON_CTR1
Register Address: ECAH, 3786 MSR_C12_PMON_CTR2
Register Address: ECBH, 3787 MSR_C12_PMON_CTR3
Register Addres s: ED0H, 3792 MSR_C13_PMON_BOX_CTL
Uncore C-Box 13 Pe rfmon local box wide  control. Package
Register Addres s: ED1H, 3793 MSR_C13_PMON_EVNTSEL0
Register Addres s: ED2H, 3794 MSR_C13_PMON_EVNTSEL1
Register Addres s: ED3H, 3795 MSR_C13_PMON_EVNTSEL2
Register Addres s: ED4H, 3796 MSR_C13_PMON_EVNTSEL3
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 3 PackageTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description Scope2-302 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: ED5H, 3797 MSR_C13_PMON_BOX_FILTER0
Uncore C-Box 13 Perfmon Box Wide Filter 0 Package
Register Address: ED6H, 3798 MSR_C13_PMON_BOX_FILTER1
Uncore C-Box 13 Perfmon Box Wide Filter 1 Package
Register Address: ED7H, 3799 MSR_C13_PMON_BOX_STATUS
Uncore C-Box 13 Perfmon Box Wide Status Package
Register Address: ED8H, 3800 MSR_C13_PMON_CTR0
Register Address: ED9H, 3801 MSR_C13_PMON_CTR1
Register Address: EDAH, 3802 MSR_C13_PMON_CTR2
Register Address: EDBH, 3803 MSR_C13_PMON_CTR3
Register Address: EE0H, 3808 MSR_C14_PMON_BOX_CTL
Uncore C-Box 14 Perfmon Local Box Wide Control Package
Register Address: EE1H, 3809 MSR_C14_PMON_EVNTSEL0
Register Address: EE2H, 3810 MSR_C14_PMON_EVNTSEL1
Register Address: EE3H, 3811 MSR_C14_PMON_EVNTSEL2
Register Address: EE4H, 3812 MSR_C14_PMON_EVNTSEL3
Register Address: EE5H, 3813 MSR_C14_PMON_BOX_FILTER
Uncore C-Box 14 Perfmon Box Wide Filter 0 Package
Register Address: EE6H, 3814 MSR_C14_PMON_BOX_FILTER1
Uncore C-Box 14 Perfmon Box Wide Filter 1 Package
Register Address: EE7H, 3815 MSR_C14_PMON_BOX_STATUS
Uncore C-Box 14 Perfmon Box Wide Status Package
Register Address: EE8H, 3816 MSR_C14_PMON_CTR0
Register Address: EE9H, 3817 MSR_C14_PMON_CTR1
Register Address: EEAH, 3818 MSR_C14_PMON_CTR2
Register Address: EEBH, 3819 MSR_C14_PMON_CTR3Table 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-303MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: EF0H, 3824 MSR_C15_PMON_BOX_CTL
Uncore C-Box 15 Perfmon Lo cal Box Wide Control Package
Register Address: EF1H, 3825 MSR_C15_PMON_EVNTSEL0
Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 0 Package
Register Address: EF2H, 3826 MSR_C15_PMON_EVNTSEL1
Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 1 Package
Register Address: EF3H, 3827 MSR_C15_PMON_EVNTSEL2
Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 2 Package
Register Address: EF4H, 3828 MSR_C15_PMON_EVNTSEL3
Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 3 Package
Register Address: EF5H, 3829 MSR_C15_PMON_BOX_FILTER0
Uncore C-Box 15 Perfmon Box Wide Filter 0 Package
Register Address: EF6H, 3830 MSR_C15_PMON_BOX_FILTER1
Uncore C-Box 15 Perfmon Box Wide Filter 1 Package
Register Address: EF7H, 3831 MSR_C15_PMON_BOX_STATUS
Uncore C-Box 15 Perfmon Box Wide Status Package
Register Address: EF8H, 3832 MSR_C15_PMON_CTR0
Uncore C-Box 15 Perfmon Counter 0 Package
Register Address: EF9H, 3833 MSR_C15_PMON_CTR1
Uncore C-Box 15 Perfmon Counter 1 Package
Register Address: EFAH, 3834 MSR_C15_PMON_CTR2
Uncore C-Box 15 Perfmon Counter 2 Package
Register Address: EFBH, 3835 MSR_C15_PMON_CTR3
Uncore C-Box 15 Perfmon Counter 3 Package
Register Address: F00H, 3840 MSR_C16_PMON_BOX_CTL
Uncore C-Box 16 Perfmon for Box-Wide Control Package
Register Address: F01H, 3841 MSR_C16_PMON_EVNTSEL0
Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 0 Package
Register Address: F02H, 3842 MSR_C16_PMON_EVNTSEL1
Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 1 Package
Register Address: F03H, 3843 MSR_C16_PMON_EVNTSEL2
Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 2 Package
Register Address: F04H, 3844 MSR_C16_PMON_EVNTSEL3
Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 3 Package
Register Address: F05H, 3845 MSR_C16_PMON_BOX_FILTER0
Uncore C-Box 16 Perfmon Box Wide Filter 0 PackageTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)

Register Information / Bit Fields Bit Description Scope2-304 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: F06H, 3846 MSR_C16_PMON_BOX_FILTER1
Uncore C-Box 16 Perfmon Box Wide Filter 1 Package
Register Address: F07H, 3847 MSR_C16_PMON_BOX_STATUS
Uncore C-Box 16 Perfmon Box Wide Status Package
Register Address: F08H, 3848 MSR_C16_PMON_CTR0
Uncore C-Box 16 Perfmon Counter 0 Package
Register Address: F09H, 3849 MSR_C16_PMON_CTR1
Uncore C-Box 16 Perfmon Counter 1 Package
Register Address: F0AH, 3850 MSR_C16_PMON_CTR2
Uncore C-Box 16 Perfmon Counter 2 Package
Register Address: F0BH, 3851 MSR_C16_PMON_CTR3
Uncore C-Box 16 Perfmon Counter 3 Package
Register Address: F10H, 3856 MSR_C17_PMON_BOX_CTL
Uncore C-Box 17 Perfmon for Box-Wide Control Package
Register Address: F11H, 3857 MSR_C17_PMON_EVNTSEL0
Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 0 Package
Register Address: F12H, 3858 MSR_C17_PMON_EVNTSEL1
Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 1 Package
Register Address: F13H, 3859 MSR_C17_PMON_EVNTSEL2
Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 2 Package
Register Address: F14H, 3860 MSR_C17_PMON_EVNTSEL3
Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 3 Package
Register Address: F15H, 3861 MSR_C17_PMON_BOX_FILTER0
Uncore C-Box 17 Perfmon Box Wide Filter 0 Package
Register Address: F16H, 3862 MSR_C17_PMON_BOX_FILTER1
Uncore C-Box 17 Perfmon Box Wide Filter1 Package
Register Address: F17H, 3863 MSR_C17_PMON_BOX_STATUS
Uncore C-Box 17 Perfmon Box Wide Status Package
Register Address: F18H, 3864 MSR_C17_PMON_CTR0
Uncore C-Box 17 Perfmon Counter 0 Package
Register Address: F19H, 3865 MSR_C17_PMON_CTR1
Uncore C-Box 17 Perfmon Counter 1 Package
Register Address: F1AH, 3866 MSR_C17_PMON_CTR2
Uncore C-Box 17 Perfmon Counter 2 Package
Register Address: F1BH, 3867 MSR_C17_PMON_CTR3
Uncore C-Box 17 Perfmon Counter 3 PackageTable 2-33.  Uncore PMU MSRs in the Inte l® Xeon® Processor E5 v3 Family (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-305MODEL-SPECIFIC REGISTERS (MSRS)
2.15 MSRS IN THE INTEL® CORE™ M PROCESSORS AND THE 5TH GENERATION 
INTEL® CORE™ PROCESSORS
The Intel® Core™ M-5xxx processors, 5th generation Intel® Core™ Processors, and the Intel® Xeon® Processor 
E3-1200 v4 family are based on Broadwell microarchitecture. The Intel® Core™ M-5xxx processors and 5th gener-
ation Intel® Core™ Processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3DH. The Intel® 
Xeon® Processor E3-1200 v4 family and 5th generation Intel® Core™ Processors have a CPUID Signature 
DisplayFamily_DisplayModel value of 06_47H. Processors  with a CPUID Signature DisplayFamily_DisplayModel 
value of 06_3DH or 06_47H support the MSR interfaces lis ted in Table 2-20, Table 2-21, Table 2-22, Table 2-25, 
Table 2-29, Table 2-30, Table 2-34, and Table 2-35. For an MS R listed in Table 2-35 that also appears in the model-
specific tables of prior generations, Table 2-35 supersedes prior generation tables.
Table 2-34 lists MSRs that are common to processors based on the Broadwell microarchitectures (including CPUID 
Signature DisplayFamily_DisplayModel valu es of 06_3DH, 06_47H, 06_4FH, and 06_56H).
Table 2-34.  Additional MSRs Common to Proc essors Based on Broadwell Microarchitectures
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.” Thread
0O v f _ P M C 0  
3O v f _ P M C 3  
31:4 Reserved32 Ovf_FixedCtr0 
55 Trace_ToPA_PMI
See Section 33.2.7.2, “Table of Physical Addresses (ToPA).”
61 Ovf_Uncore 62 Ovf_BufDSSAVE 
63 CondChgd 
0 Set 1 to clear Ovf_PMC0.
1 Set 1 to clear Ovf_PMC1.2 Set 1 to clear Ovf_PMC2.
3 Set 1 to clear Ovf_PMC3.
31:4 Reserved.32 Set 1 to clear Ovf_FixedCtr0.
33 Set 1 to clear Ovf_FixedCtr1.
34 Set 1 to clear Ovf_FixedCtr2 2-306 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
55 Set 1 to clear Trace_ToPA_PMI. See Se ction 33.2.7.2, “Table of Physical 
Addresses (ToPA).”
61 Set 1 to clear Ovf_Uncore.62 Set 1 to clea r Ovf_BufDSSAVE.
63 Set 1 to clear CondChgd.
Trace Output Base  Register (R/W) Thread
MAXPHYADDR1-1:7 Base physical address.
Trace Output Mask Pointe rs Register (R/W) Thread
6:0 Reserved.31:7 MaskOrTableOffset
63:32 Output Offset.
Trace Control Register (R/W) Thread
0 TraceEn
1 Reserved, must be zero.2O S
3U s e r
8T o P A
9 Reserved, must be zero.
13 Reserved; writing 0 will #GP if also setting TraceEn.63:14 Reserved, must be zero.
Tracing Status Register (R/W) Thread
0 Reserved, writes ignored.
1 ContexEn, writes ignored.
2 TriggerEn, writes ignored.Table 2-34.  Additional MSRs Common to Processors Based on Broadwell Microarchitectures
Register Information / Bit Fields Bit Description ScopeVol. 4 2-307MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-35 lists MSRs that are specific to Intel Core M processors and 5th Generation Intel Core Processors.3 Reserved
5S t o p p e d63:6 Reserved, must be zero.
Trace Filter CR3 Match Register (R/W) Thread
63:5 CR3[63:5] value to match.
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to 
these fields allows software to control the minimum and the maximum frequency that hardware will select.Package
NOTES:
1. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].
Table 2-35.  Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
ACPI C-states. See http://biosbits.org.CoreTable 2-34.  Additional MSRs Common to Proc essors Based on Broadwell Microarchitectures
Register Information / Bit Fields Bit Description Scope2-308 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
0001b: C2
0100b: C7
0101b: C7s
0110b: C8
0111b: C91000b: C10
9:4 Reserved.10 I/O MWAIT Redirection Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)27 Enable C3 Undemotion (R/W)
29 Enable Package C-State Auto-Demotion (R/W)30 Enable Package C-State Undemotion (R/W)
23:16 Maximum Ra tio Limit for 3C
31:24 Maximum Ra tio Limit for 4C
39:32 Maximum Ra tio Limit for 5C
Maximum turbo ratio li mit of 5core active.PackageTable 2-35.  Additional MSRs  Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Information / Bit Fields Bit Description ScopeVol. 4 2-309MODEL-SPECIFIC REGISTERS (MSRS)
2.16 MSRS IN THE INTEL® XE ON® PROCESSOR E5 V4 FAMILY
The MSRs listed in Table 2-36 are available and common to the Intel® Xeon® Processor D Product Family (CPUID

The MSRs listed in Table 2-36 are available and common to the Intel® Xeon® Processor D Product Family (CPUID 
Signature DisplayFamily_DisplayModel valu e of 06_56H) and to the Intel Xeon processors E5 v4 and E7 v4 families 
(CPUID Signature DisplayFamily_DisplayModel value of  06_4FH). These processors are based on Broadwell 
See Section 2.16.1 for lists of tables of MSRs that are supported by the Intel® Xeon® Processor D Family.47:40 Maximum Ratio Limit for 6C
Maximum turbo ratio li mit of 6core active.Package
See Table 2-20, Table 2-21, Table 2-22, Table 2-25, Table 2-29, Table 2-30, and Table 2-34 for other MSR definitions applicable  to 
processors with a CPUID Signature DisplayFamily_DisplayModel value of 06_3DH.
Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processo r D and the Intel® Xeon® Processor E5 v4 Family 
Based on Broadwell Microarchitecture 
63:2 Reserved
See Table 2-26.Package
22:16 Reserved.Table 2-35.  Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Information / Bit Fields Bit Description Scope2-310 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
111b: No Package C state limits. All C states supported by the processor 
are available.
15 CFG Lock (R/WO)16 Automatic C-State Conversion Enable (R/W)
If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6).
24:17 Reserved.
29 Package C State Demotion Enable (R/W)Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family 
Based on Broadwell Microarchitecture  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-311MODEL-SPECIFIC REGISTERS (MSRS)
30 Package C State Undemotion Enable (R/W)
7:0 Count
11 MCG_TES_P15:12 Reserved23:16 MCG_EXT_CNT
If set to 1, indicates th at the SMM code access restriction is supported and 
a host-space interface available to SMM handler.
See Table 2-2.Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processo r D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description Scope2-312 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
12 Current Limit Status (R/O) 
13 Current Limit Log (R/WC0) 
14 Cross Domain Limit Status (R/O) 
15 Cross Domain Limit Log (R/WC0) 
22:16 Digital Readout (R/O) 
26:23 Reserved.30:27 Resolution in Degrees Celsius (R/O) 
23:16 Temperature Target (R/O) 
See Table 2-26.
See Table 2-26.Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-313MODEL-SPECIFIC REGISTERS (MSRS)
7:0 Maximum Ratio Limit for 1C Package
15:8 Maximum Ratio Limit for 2C Package
23:16 Maximum Ratio Limit for 3C Package
31:24 Maximum Ratio Limit for 4C Package39:32 Maximum Ratio Limit for 5C Package47:40 Maximum Ratio Limit for 6C Package
55:48 Maximum Ratio Limit for 7C Package
63:56 Maximum Ratio Limit for 8C Package
7:0 Maximum Ratio Limit for 9C Package
15:8 Maximum Ratio Limit for 10C Package23:16 Maximum Ratio Limit for 11C Package
31:24 Maximum Ratio Limit for 12C Package
39:32 Maximum Ratio Limit for 13C Package47:40 Maximum Ratio Limit for 14C Package
55:48 Maximum Ratio Limit for 15C Package
63:56 Maximum Ratio Limit for 16C Package
where ESU is an unsigned integer represented by bits 12:8. Default value 
is 0EH (or 61 micro-joules).Package
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMITTable 2-36.  Additional MSRs Common to  the Intel® Xeon® Processo r D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description Scope2-314 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Energy consumed by DRAM devices.Package
Uncore Ratio Limit (R/W)

Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing 
to these fields allows software to  control the minimum and the maximum frequency that hardware will select.Package
Reads return 0.Package
system request due to asse rtion of external PROCHOT.
to PBM limit.Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-315MODEL-SPECIFIC REGISTERS (MSRS)
to PCS limit.
to electrical design po int constraints (e .g., maximum electrical current 
9 Reserved.10 Multi-Core Turbo Status (R0) 
to Multi-Core Turbo limits.
12:11 Reserved.13 Core Frequency P1 Status (R0) 
When set, indicates that  the PROCHOT Status bit has asserted since the 
When set, indicates that the PBM Status bit has asserted since the log bit 
When set, indicates that the PCS Status bit has asserted since the log bit 
This log bit will remain  set until cleared by  software writing 0.Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processo r D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description Scope2-316 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
20 Reserved.
When set, indicates that  the AUBFC Status bit has asserted since the log 
When set, indicates that the VR Therm Alert Status bit has asserted since 
When set, indicates that the Multi-Core  Turbo Status bit has asserted since 
31 Core Frequency Limiting Log
When set, indicates that  the Core Frequency Limiting Status bit has 
See Section 15.4.2, “Enabling HWP.” Package
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.” Thread
See Section 15.4.4, “Managing HWP.” Thread
7:0 Minimum Performance (R/W)15:8 Maximum Performance (R/W)Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-317MODEL-SPECIFIC REGISTERS (MSRS)
23:16 Desired Performance (R/W)
See Section 15.4.5, “HWP Feedback.” Thread
1:0 Reserved.
2 Excursion to Minimum (R/O)63:3 Reserved.
0x00: No monitoring.0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.
0x03: Local memory bandwidth monitoring.All other encoding reserved.
9:0 RMID 
31:10 Reserved.51:32 COS (R/W)
63: 52 Reserved.
Register Address: C90H, 3216 IA32_L3_QOS_MASK_0
L3 Class Of Service Mask - COS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.Package
0:19 CBM: Bit vector of available L3 ways for COS 0 enforcement.
Register Address: C91H, 3217 IA32_L3_QOS_MASK_1
L3 Class Of Service Mask - COS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.Package
0:19 CBM: Bit vector of available L3 ways for COS 1 enforcement.
Register Address: C92H, 3218 IA32_L3_QOS_MASK_2Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processo r D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description Scope2-318 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
L3 Class Of Service Mask - COS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.Package
0:19 CBM: Bit vector of available L3 ways for COS 2 enforcement.
Register Address: C93H, 3219 IA32_L3_QOS_MASK_3
L3 Class Of Service Mask - COS 3 (R/W)
0:19 CBM: Bit vector of available L3 ways for COS 3 enforcement.
Register Address: C94H, 3220 IA32_L3_QOS_MASK_4
L3 Class Of Service Mask - COS 4 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4.Package
0:19 CBM: Bit vector of available L3 ways for COS 4 enforcement.
Register Address: C95H, 3221 IA32_L3_QOS_MASK_5
L3 Class Of Service Mask - COS 5 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5.Package
0:19 CBM: Bit vector of available L3 ways for COS 5 enforcement.
Register Address: C96H, 3222 IA32_L3_QOS_MASK_6
L3 Class Of Service Mask - COS 6 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6.Package
0:19 CBM: Bit vector of available L3 ways for COS 6 enforcement.
Register Address: C97H, 3223 IA32_L3_QOS_MASK_7
L3 Class Of Service Mask - COS 7 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7.Package
0:19 CBM: Bit vector of available L3 ways for COS 7 enforcement.
Register Address: C98H, 3224 IA32_L3_QOS_MASK_8
L3 Class Of Service Mask - COS 8 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8.Package
0:19 CBM: Bit vector of available L3 ways for COS 8 enforcement.
Register Address: C99H, 3225 IA32_L3_QOS_MASK_9
L3 Class Of Service Mask - COS 9 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9.Package

0:19 CBM: Bit vector of available L3 ways for COS 9 enforcement.Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-319MODEL-SPECIFIC REGISTERS (MSRS)
2.16.1  Additional MSRs Supported in the Intel® Xeon®  Processor D Product Family
The MSRs listed in Table 2-37 are available to Intel® Xeon® Processor D Product Family (CPUID Signature 
DisplayFamily_DisplayModel va lue of 06_56H). The Intel® Xeon® processor D product family is based on Broadwell 
microarchitecture and supports the MSR interfaces listed  in Table 2-20, Table 2-29, Table 2-34, Table 2-36, and 
Table 2-37. 63:20 Reserved.
Register Address: C9AH, 3226 IA32_L3_QOS_MASK_10
L3 Class Of Service Mask - COS 10 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=10.Package
0:19 CBM: Bit vector of available L3 ways for COS 10 enforcement.
Register Address: C9BH, 3227 IA32_L3_QOS_MASK_11
L3 Class Of Service Mask - COS 11 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=11.Package
0:19 CBM: Bit vector of available L3 ways for COS 11 enforcement.
Register Address: C9CH, 3228 IA32_L3_QOS_MASK_12
L3 Class Of Service Mask - COS 12 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=12.Package
0:19 CBM: Bit vector of available L3 ways for COS 12 enforcement.
Register Address: C9DH, 3229 IA32_L3_QOS_MASK_13
L3 Class Of Service Mask - COS 13 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=13.Package
0:19 CBM: Bit vector of available L3 ways for COS 13 enforcement.
Register Address: C9EH, 3230 IA32_L3_QOS_MASK_14
L3 Class Of Service Mask - COS 14 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=14.Package
0:19 CBM: Bit vector of available L3 ways for COS 14 enforcement.
Register Address: C9FH, 3231 IA32_L3_QOS_MASK_15
L3 Class Of Service Mask - COS 15 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=15.Package
0:19 CBM: Bit vector of available L3 ways for COS 15 enforcement.
63:20 Reserved.Table 2-36.  Additional MSRs Common to  the Intel® Xeon® Processo r D and the Intel® Xeon® Processor E5 v4 Family 
Register Information / Bit Fields Bit Description Scope2-320 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37.  Additional MSRs Supported by In tel® Xeon® Processor D with a CPUID Signature 
DisplayFamily_DisplayM odel Value of 06_56H
Register Address: 1ACH, 428 MSR_TURBO_RATIO_LIMIT3
Config Ratio Limit of Turbo Mode
62:0 Reserved. Package
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1.
Bank MC7 reports MC errors from the home agent HA 0.PackageVol. 4 2-321MODEL-SPECIFIC REGISTERS (MSRS)
Banks MC9 through MC 10 report MC errors from ea ch channel of the integr ated memory controllers.Package
Bank MC17 reports MC errors from the following pair of CBo/ L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9, 
Register Address: 445H, 1093 IA32_MC17_STATUSTable 2-37.  Additional MSRs Supported by In tel® Xeon® Processor D with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-322 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)

Register Address: 44FH, 1103 IA32_MC19_MISCTable 2-37.  Additional MSRs Supported by In tel® Xeon® Processor D with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-323MODEL-SPECIFIC REGISTERS (MSRS)
2.16.2  Additional MSRs Supported in Intel® Xeon®  Processors E5 v4 and E7 v4 Families
The MSRs listed in Table 2-37 are available to the Intel® Xeon® Processor E5 v4 and E7 v4 Families (CPUID 
Signature DisplayFamily_DisplayModel value of 06_4FH). The Intel® Xeon® processor E5 v4 family is based on 
Broadwell microarchitecture and supports the MSR interfac es listed in Table 2-20, Table 2-21, Table 2-29, Table 
2-34, Table 2-36, and Table 2-38. See Section 16.3.2.1, “IA32_MC i_CTL MSRs,” through Section 16.3.2.4, “IA32_MC i_MISC MSRs.”
See Table 2-20, Table 2-29, Table 2-34, and Table 2-36 for other MS R definitions applicable to processors with a CPUID Signatur e 
DisplayFamily_DisplayMod el value of 06_56H. 
NOTES:
factory-set configuration is dependent on features specific to the processor and the platform.
Table 2-38.  Additional MSRs Supported by In tel® Xeon® Processors with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_4FH
MSR_TURBO_RATIO_LIMIT, MS R_TURBO_RATIO_LIMIT1, and 
MSR_TURBO_RATIO_LIMIT2.
See Table 2-2. PackageTable 2-37.  Additional MSRs Supported by In tel® Xeon® Processor D with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-324 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC6 reports MC errors from the integrated I/O module.PackageTable 2-38.  Additional MSRs Supported by In tel® Xeon® Processors with a CPUID Signature 
DisplayFamily_DisplayM odel Value of 06_4FH
Register Information / Bit Fields Bit Description ScopeVol. 4 2-325MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 425H, 1061 IA32_MC9_STATUSTable 2-38.  Additional MSRs Supported by In tel® Xeon® Processors with a CPUID Signature 

Register Information / Bit Fields Bit Description Scope2-326 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Banks MC9 through MC 16 report MC errors from ea ch channel of the integr ated memory controllers.PackageTable 2-38.  Additional MSRs Supported by In tel® Xeon® Processors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-327MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 43EH, 1086 IA32_MC15_ADDRTable 2-38.  Additional MSRs Supported by In tel® Xeon® Processors with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-328 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)

Register Address: 449H, 1097 IA32_MC18_STATUSTable 2-38.  Additional MSRs Supported by In tel® Xeon® Processors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-329MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 454H, 1108 IA32_MC21_CTLTable 2-38.  Additional MSRs Supported by In tel® Xeon® Processors with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-330 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.17 MSRS IN THE 6TH —13TH GENERATION INTEL® CORE™ PROCESSORS, 
1ST—5TH GENERATION INTEL® XEON® SCALABLE PROCESSOR FAMILIES, 
INTEL® CORE™ ULTRA 7 PROCESSORS, 8TH GENERATION INTEL® CORE™ I3 
PROCESSORS, AND INTEL® XEON® E PROCESSORS
6th generation Intel® Core™ processors are based on Skylake microarchitecture and have a CPUID Signature 
DisplayFamily_DisplayModel value of 06_4EH or 06_5EH. 
The Intel® Xeon® Scalable Processor Family based on the Skylak e microarchitecture, the 2nd generation Intel® 
Xeon® Scalable Processor Family based on the Cascade Lake product, and the 3rd generation Intel® Xeon® Scal-
able Processor Family based on the Cooper Lake produc t all have a CPUID Signature DisplayFamily_DisplayModel 
value of 06_55H. 
7th generation Intel® Core™ processors are based on the Kaby Lake microarchitecture, 8th generation and 9th 
generation Intel® Core™ processors, and Intel® Xeon® E processors are based on Coffee Lake microarchitecture; 
these processors have a CPUID Signature DisplayF amily_DisplayModel value of 06_8EH or 06_9EH. 
8th generation Intel® Core™ i3 processors are based on Cannon Lake microarchitecture and have a CPUID Signa-
ture DisplayFamily_DisplayModel value of 06_66H. 
10th generation Intel® Core™ processors are based on Comet Lake microarchitecture (with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_A5H or 06_A6H) an d Ice Lake microarchitecture (with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_7DH or 06_7EH). See Section 16.3.2.1, “IA32_MC i_CTL MSRs,” through Section 16.3.2.4, “IA32_MC i_MISC MSRs.”
Cache Allocation Te chnology Configuration (R/W) Package
0 CAT Enable. Set 1 to enable Cache Allocation  Technology.
63:1 Reserved.See Table 2-20, Table 2-21, Table 2-29, and Table 2-30 for other MS R definitions applicable to processors with a CPUID Signatur e 
DisplayFamily_DisplayMod el value of 06_45H.
NOTES:
tory-set configuration is dependent on features specific to the processor and the platform.Table 2-38.  Additional MSRs Supported by In tel® Xeon® Processors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-331MODEL-SPECIFIC REGISTERS (MSRS)
11th generation Intel® Core™ processors are based on Tiger Lake microarchitecture and have a CPUID Signature 
DisplayFamily_DisplayModel value of 06_8CH or 06_8DH.
The 3rd generation Intel® Xeon® Scalable Processor Family is based on Ice Lake microarchitecture and has a 
CPUID Signature DisplayFamily_DisplayModel value of 06_6AH or 06_6CH.
12th generation Intel® Core™ processors supporting the Alder Lake performance hybrid architecture have a CPUID 
Signature DisplayFamily_DisplayModel value of 06_97H or 06_9AH.
13th generation Intel® Core™ processors supporting the Raptor Lake performance hybrid architecture have a 
CPUID Signature DisplayFamily_DisplayMod el value of 06_BAH , 06_B7H, or 06_BFH.
The 4th generation Intel® Xeon® Scalable Processor Family is based on Sapphire Rapids microarchitecture and has 
a CPUID Signature DisplayFamily_DisplayModel value of 06_8FH.
The 5th generation Intel® Xeon® Scalable Processor Family is based on Emerald Rapids microarchitecture and has 
a CPUID Signature DisplayFamily _DisplayModel value of 06_CFH.
The Intel® Core™ Ultra 7 processor is based on Meteor Lake  hybrid architecture and has a CPUID Signature 
DisplayFamily_DisplayModel value of 06_AAH.
These processors support the MSR interfaces listed in Ta ble 2-20, Table 2-21, Table 2-25, Table 2-29, Table 2-35, 
and Table 2-391. For an MSR listed in Table 2-39 that also appears in the model-specific tables of prior generations, 
Table 2-39 supersede prior generation tables.
Tables 2-40 through 2-52 list additional supported MSR inte rfaces for specific processors; see each table for addi-
The notation of “Platform” in the Scope column (with respect to MSR_PLATFORM_ENERGY_COUNTER and 
MSR_PLATFORM_POWER_LIMIT) is limited to the power-deli very domain and the specif ics of the power delivery 
integration may vary by platfo rm vendor’s implementation.

1. MSRs at the following addresses are not su pported in the 12th generation Intel Core processor E-core: 3F7H. MSRs at the follo wing 
addresses are not supported in the 12th ge neration Intel Core processor E-core or P-core: 652H, 653H, 6 55H, 656H, DB0H, DB1H, 
DB2H, and D90H. Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Intel® Xeon® Scalable Processor Families , Intel® Core™ Ultra 7 Processors, 8th Ge neration Intel® Core™ i3 Processors, 
and Intel® Xeon® E Processors
MTRR Capability (R/O, Architectural)
See Table 2-2.2-332 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
6 Thermal threshold #1 Status (R/O) 
7 Thermal threshold #1 Log (R/WC0) 
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1PackageTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors, 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-333MODEL-SPECIFIC REGISTERS (MSRS)
Contains an index (bits 0-4) that  points to the MSR co ntaining the most recent branch record.Thread
1C 1 E  E n a b l e  ( R / W )  
When set to ‘1’, will enable the CP U to switch to th e Minimum Enhanced 
Intel SpeedStep Technology operating point when all execution cores enter 
MWAIT (C1).Package
18:2 Reserved.
19 Disable Energy Efficiency Optimization (R/W) 
Setting this bit disables the P-Stat es energy efficiency optimization. 
Default value is 0. Disable/enable the energy efficiency optimization in P-
State legacy mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the turbo range or into  PERF_MIN_CTL value if  it is not zero 
set. In HWP mode (IA32_PM_ENABLE[ HWP_ENABLE] == 1), has an effect 
between the OS desi red or OS maximize to the OS minimize performance 
setting.
20 Disable Race to Halt  Optimization (R/W) 
Setting this bit disables the Race to  Halt optimization  and avoids this 
optimization limitati on to execute below the most efficient frequency ratio. 
Default value is 0 for processors that  support Race to Halt optimization.
63:0 Lower 64 bits of an 128-bit external entropy value for key derivation of an 
enclave.
Register Address: 301H, 769 MSR_SGXOWNEREPOCH1Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-334 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
63:0 Upper 64 bits of an 1 28-bit external entropy value for key derivation of an 
enclave.
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.” 
0 Ovf_PMC0 Thread1 Ovf_PMC1 Thread2 Ovf_PMC2 Thread
3 Ovf_PMC3 Thread
4 Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4) Thread5 Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5) Thread
6 Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6) Thread
7 Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7) Thread31:8 Reserved.
32 Ovf_FixedCtr0 Thread
33 Ovf_FixedCtr1 Thread34 Ovf_FixedCtr2 Thread
54:35 Reserved
55 Trace_ToPA_PMI Thread57:56 Reserved.
58 LBR_Frz Thread
59 CTR_Frz Thread60 ASCI Thread
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.”0 Set 1 to clear Ovf_PMC0. Thread
1 Set 1 to clear Ovf_PMC1. Thread
2 Set 1 to clear Ovf_PMC2. Thread3 Set 1 to clear Ovf_PMC3. Thread
4 Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). Thread
5 Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). Thread6 Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). ThreadTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-335MODEL-SPECIFIC REGISTERS (MSRS)
7 Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). Thread
32 Set 1 to clear Ovf_FixedCtr0. Thread33 Set 1 to clear Ovf_FixedCtr1. Thread
34 Set 1 to clear Ovf_FixedCtr2. Thread
54:35 Reserved.55 Set 1 to clear Trace_ToPA_PMI. Thread57:56 Reserved.
58 Set 1 to clear LBR_Frz. Thread
59 Set 1 to clear CTR_Frz. Thread60 Set 1 to clear ASCI. Thread
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.”0 Set 1 to cause Ovf_PMC0 = 1. Thread
1 Set 1 to cause Ovf_PMC1 = 1. Thread
2 Set 1 to cause Ovf_PMC2 = 1. Thread3 Set 1 to cause Ovf_PMC3 = 1. Thread
4 Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4). Thread
5 Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5). Thread6 Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6). Thread
7 Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7). Thread
31:8 Reserved.32 Set 1 to cause Ovf_FixedCtr0 = 1. Thread
33 Set 1 to cause Ovf_FixedCtr1 = 1. Thread
34 Set 1 to cause Ovf_FixedCtr2 = 1. Thread54:35 Reserved.
55 Set 1 to cause Trace_ToPA_PMI = 1. Thread
57:56 Reserved.58 Set 1 to cause LBR_Frz = 1. Thread
59 Set 1 to cause CTR_Frz = 1. Thread
60 Set 1 to cause ASCI = 1. Thread61 Set 1 to cause Ovf_Uncore. Thread
62 Set 1 to cause Ovf_BufDSSAVE. ThreadTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-336 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 3F7H, 1015 MSR_PEBS_FRONTEND
FrontEnd Precise Event Condition Select (R/W) Thread
2:0 Event Code Select 3 Reserved4 Event Code Select High
19:8 IDQ_Bubble_Length Specifier22:20 IDQ_Bubble_Width Specifier
Status and SVN Threshold of SGX Support for ACM (R/O) Thread
0L o c k
See Section 39.11.3, “Interaction s with Authentica ted Code Modules 
(ACMs).”
23:16 SGX_SVN_SINIT

0L o c k
(ACMs).”
(ACMs).”
Trace Output Mask Poin ters Register (R/W)
0 TraceEn1C Y C E n
2O S
3U s e r6:4 Reserved, must be zero.
7C R 3 F i l t e rTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-337MODEL-SPECIFIC REGISTERS (MSRS)
8T o P A
9M T C E n
10 TSCEn
11 DisRETC12 Reserved, must be zero.
13 BranchEn
17:14 MTCFreq18 Reserved, must be zero.22:19 CycThresh
27:24 PSBFreq31:28 Reserved, must be zero.
35:32 ADDR0_CFG
39:36 ADDR1_CFG63:40 Reserved, must be zero.
0 FilterEn, writes ignored.
2 TriggerEn, writes ignored.3 Reserved
4:0 Reserved63:5 CR3[63:5] value to match
Region 0 Start Address (R/W) Thread
Region 0 End Address (R/W) ThreadTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-338 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Region 1 Start Address (R/W) Thread
Region 1 End Address (R/W) Thread
Register Address: 64DH, 1613 MSR_PLATFORM_ENERGY_COUNTER
Platform Energy Counter (R/O)
This MSR is valid only if both platfo rm vendor hardware implementation and BIOS enablement support it. This MSR 
will read 0 if not valid.Platform
31:0 Total energy consumed by all devices in the platform that receive power 
from integrated power delivery mechan ism, included platform devices are 
processor cores, SOC, memory, add-on or peripheral devices that get powered directly from the platform power delivery means. The energy 
units are specified in the MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
Register Address: 64EH, 1614 MSR_PPERF
Productive Performance Count (R/O) Thread
63:0 Hardware’s view of  workload scalability. See Section 15.4.5.1.
to assertion of external PROCHOT.
4 Residency State Regulation Status (R0)
to residency state regulation limit.
5 Running Average Thermal Limit Status (R0)
to Running Average Thermal Limit (RATL).Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-339MODEL-SPECIFIC REGISTERS (MSRS)
to a thermal alert from a proc essor Voltage Regulator (VR).
7 VR Therm Design Current Status (R0)
to VR thermal desi gn current limit.
8O t h e r  S t a t u s  ( R 0 )
to electrical or other constraints.
9 Reserved.10 Package/Platform-Level Power Limiting PL1 Status (R0)
to package/platform-level power limiting PL1.
11 Package/Platform-Level PL2 Power Limiting Status (R0)
to package/platform-level power limiting PL2/PL3.
20 Residency State Regulation Log 
When set, indicates that  the Residency State Regulation Status bit has 
21 Running Average Thermal Limit Log 
When set, indicates that the RATL Stat us bit has asserted  since the log bit 
This log bit will remain  set until cleared by  software writing 0.Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-340 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
23 VR Thermal Design Current Log 
When set, indicates that the VR TDC Status bit has asserted since the log 
24 Other Log 
When set, indicates that the Other Status bit has asserted since the log bit 
25 Reserved.26 Package/Platform-Level PL1 Power Limiting Log 
When set, indicates that the Package or Platform Level PL1 Power Limiting 
27 Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Packag e or Platform Level PL2/PL3 Power 
Limiting Status bit has asserted since the log bit was last cleared.
When set, indicates that the Turbo Tr ansition Atte nuation Status bit has 
Register Address: 652H, 1618 MSR_PKG_HDC_CONFIG
HDC Configuration (R/W) Package
2:0 PKG_Cx_Monitor
Configures Package Cx state threshold for 
MSR_PKG_HDC_DEEP_RESIDENCY.
63: 3 Reserved.
Register Address: 653H, 1619 MSR_CORE_HDC_RESIDENCY
Core HDC Idle Residency (R/O) Core
63:0 Core_Cx_Duty_Cycle_Cnt
Register Address: 655H, 1621 MSR_PKG_HDC_SHAL LOW_RESIDENCYTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 

Register Information / Bit Fields Bit Description ScopeVol. 4 2-341MODEL-SPECIFIC REGISTERS (MSRS)
Accumulate the cycles the pack age was in C2 state and at least one logical processor was in forced idle (R/O) Package
63:0 Pkg_C2_Duty_Cycle_Cnt
Register Address: 656H, 1622 MSR_PKG_HDC_DEEP_RESIDENCY
Package Cx HDC Idle Residency (R/O) Package
63:0 Pkg_Cx_Duty_Cycle_Cnt
Register Address: 658H, 1624 MSR_WEIGHTED_CORE_C0
Core-count Weighted C0 Residency (R/O) Package
63:0 Increment at the same rate as the TSC. The increment each cycle is 
weighted by the number of processor cores in the package that reside in C0. If N cores are simultaneously in C0, then each cycle the counter 
increments by N. 
Register Address: 659H, 1625 MSR_ANY_CORE_C0
Any Core C0 Residency (R/O) Package
63:0 Increment at the same rate as the TSC. The increment each cycle is one if 
any processor core in the package is in C0. 
Register Address: 65AH, 1626 MSR_ANY_GFXE_C0
Any Graphics Engine C0 Residency (R/O) Package
any processor graphic device’s compute engines are in C0. 
Register Address: 65BH, 1627 MSR_CORE_GFXE_OVERLAP_C0
Core and Graphics Engine Overlapped C0 Residency (R/O) Package
at least one compute engine of the processor graphics is in C0 and at least 
one processor core in the package is also in C0. 
Register Address: 65CH, 1628 MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W-L) 
Allows platform BIOS to limit power consumption of the pl atform devices to the specified values. The Long Duration 
power consumption is specified via Platform_Power_Limit_1  and Platform_Power_Limit_1 _Time. The Short Duration 
power consumption limit is specified via the Platform_Pow er_Limit_2 with duration chosen by the processor. 
The processor implements an exponential-weighted algorithm in the placement of the time windows.Platform
14:0 Platform Power Limit #1
Average Power limit value which the platform must not exceed over a time 
window as specified by Power_Limit_1_TIME field. 
The default value is the Thermal Design Power (TDP) and varies with 
product skus. The unit is sp ecified in MSR_RAPLPOWER_UNIT.
15 Enable Platform Power Limit #1
When set, enables the processor to apply control policy such that the 
platform power does not exceed Plat form Power limit #1  over the time 
window specified by Power Limit #1 Time Window.Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-342 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
16 Platform Clamping Limitation #1
When set, allows the processor to go  below the OS requested P states in 
order to maintain the power below specified Platform Power Limit #1 
value. 
This bit is writeable only when CPUID (EAX=6):EAX[4] is set.
23:17 Time Window for Platform Power Limit #1
Specifies the duration of the time window over which Platform Power 
Limit 1 value should be maintained for sustained long duration. This field is 
made up of two numbers from the following equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]The maximum allowed value in this field is defined in 
MSR_PKG_POWER_IN FO[PKG_MAX_WIN].
The default value is 0DH, an d the unit is specified in 
MSR_RAPL_POWER_UNIT[Time Unit].
31:24 Reserved.46:32 Platform Power Limit #2
Average Power limit value which the platform must not exceed over the 
Short Duration time window chosen by the processor. 
The recommended default value is 1. 25 times the Long Duration Power 
Limit (i.e., Platform Power Limit # 1).
47 Enable Platform Power Limit #2
platform power does not exceed Plat form Power limit #2  over the Short 
Duration time window.
48 Platform Clamping Limitation #2
order to maintain the power below specified Platform Power Limit #2 value. 
62:49 Reserved.63 Lock. Setting this bit will lock all other bits of this MSR until system RESET.
One of 32 triplets of la st branch record re gisters on the last branch record stac k. This part of the stack contains 
• Section 18.12.Thread
Register Address: 692H, 1682 MSR_LASTBRANCH_18_FROM_IPTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-343MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 698H, 1688 MSR_LASTBRANCH_24_FROM_IP
See description of MSR_LASTBRANCH_0_FROM_IP.ThreadTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-344 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
When set, frequency is reduced due to assertion of external PROCHOT.
When set, frequency is reduced due to a thermal event.
4:2 Reserved.
5 Running Average Thermal Limit Status (R0) 
When set, frequency is reduced due to running average thermal limit. 
When set, frequency is reduced due to a thermal alert from a processor 
Voltage Regulator.
7 VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
When set, frequency is reduced due to electrical or other constraints.
10 Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced due to package/platform-level power 
limiting PL1.
limiting PL2/PL3.
12 Inefficient Operation Status (R0)
When set, processor graphics frequency is operating below target 
15:13 Reserved.16 PROCHOT Log

15:13 Reserved.16 PROCHOT Log 
When set, indicates that the PROCHO T Status bit has a sserted since the 
20:18 Reserved.Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-345MODEL-SPECIFIC REGISTERS (MSRS)
When set, indicates that  the OTHER Status bit has asserted since the log 
26 Package/Platform-Level PL1 Power Limiting Log 
When set, indicates that  the Package/Platform Level PL1 Power Limiting 
When set, indicates that  the Package/Platform Level PL2 Power Limiting 
28 Inefficient Operation Log
When set, indicates that the Inefficient Operation Status bit has asserted 
When set, frequency is reduced due to running average thermal limit. Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-346 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
When set, frequency is reduced due to package/Platform-level power 
15:12 Reserved 
20:18 Reserved.
When set, indicates that the OTHER Status bit has asserted since the log 
25 Reserved.Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-347MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6D0H, 1744 MSR_LASTBRANCH_16_TO_IP
One of 32 triplets of last br anch record registers on the last branch record stack. This part of the stack contains 
pointers to the destination instruction. See also:
Register Address: 6D1H, 1745 MSR_LASTBRANCH_17_TO_IP
See description of MSR_LASTBRANCH_0_TO_IP.Thread
See description of MSR_LASTBRANCH_0_TO_IP.ThreadTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-348 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6DCH, 1756 MSR_LASTBRANCH_28_TO_IP
Register Address: 6DEH, 1758 MSR_LASTBRANCH_30_TO_IP
Register Address: 6DFH, 1759 MSR_LASTBRANCH_31_TO_IP
See Section 15.4.4, “Managing HWP.” Package

See Section 15.4.6, “HWP Notifications.” Thread
7:0 Minimum Performance (R/W)
15:8 Maximum Performance (R/W)23:16 Desired Performance (R/W)
31:24 Energy/Performance Preference (R/W)
41:32 Activity Window (R/W)42 Package Control (R/W)Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-349MODEL-SPECIFIC REGISTERS (MSRS)
See Section 15.5.2, “Package level Enabling HDC.” Package
See Section 15.5.3, “Logical-Processor Level HDC Control.” Thread
Register Address: DB2H, 3506 IA32_THREAD_STALL
See Section 15.5.4.1, “IA32_THREAD_STALL.” Thread
Register Address: DC0H, 3520 MSR_LBR_INFO_0
One of 32 triplet of last bran ch record registers on the last branch record stack. This part of the stack contains flag, 
TSX-related and elapsed cycle information. See also:
• Section 18.9.1, “LBR Stack.”Thread
Register Address: DC1H, 3521 MSR_LBR_INFO_1
See description of MSR_LBR_INFO_0.Thread
Register Address: DC2H, 3522 MSR_LBR_INFO_2
See description of MSR_LBR_INFO_0. Thread
Register Address: DC3H, 3523 MSR_LBR_INFO_3
Register Address: DC4H, 3524 MSR_LBR_INFO_4
Register Address: DC5H, 3525 MSR_LBR_INFO_5
Register Address: DC6H, 3526 MSR_LBR_INFO_6
Register Address: DC7H, 3527 MSR_LBR_INFO_7Table 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-350 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DC8H, 3528 MSR_LBR_INFO_8
Register Address: DC9H, 3529 MSR_LBR_INFO_9
Register Address: DCAH, 3530 MSR_LBR_INFO_10
Register Address: DCBH, 3531 MSR_LBR_INFO_11
Register Address: DCCH, 3532 MSR_LBR_INFO_12
Register Address: DCDH, 3533 MSR_LBR_INFO_13
Register Address: DCEH, 3534 MSR_LBR_INFO_14
Register Address: DCFH, 3535 MSR_LBR_INFO_15
Register Address: DD0H, 3536 MSR_LBR_INFO_16
Register Address: DD1H, 3537 MSR_LBR_INFO_17
Register Address: DD2H, 3538 MSR_LBR_INFO_18
Register Address: DD3H, 3539 MSR_LBR_INFO_19
See description of MSR_LBR_INFO_0.ThreadTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-351MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DD4H, 3540 MSR_LBR_INFO_20
Register Address: DD5H, 3541 MSR_LBR_INFO_21
Register Address: DD6H, 3542 MSR_LBR_INFO_22
Register Address: DD7H, 3543 MSR_LBR_INFO_23
Register Address: DD8H, 3544 MSR_LBR_INFO_24
Register Address: DD9H, 3545 MSR_LBR_INFO_25
Register Address: DDAH, 3546 MSR_LBR_INFO_26
Register Address: DDBH, 3547 MSR_LBR_INFO_27
Register Address: DDCH, 3548 MSR_LBR_INFO_28
Register Address: DDDH, 3549 MSR_LBR_INFO_29
Register Address: DDEH, 3550 MSR_LBR_INFO_30
Register Address: DDFH, 3551 MSR_LBR_INFO_31
See description of MSR_LBR_INFO_0.ThreadTable 2-39.  Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Proc essors, 1st—5th Generation 
Register Information / Bit Fields Bit Description Scope2-352 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-40 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel 
value of 06_4EH, 06_5EH, 06_8EH, 06_9EH, or 06_66H.
Table 2-40.  Uncore PMU MSRs Supported by 6th Genera tion, 7th Generation, and 8th Generation Intel® Core™ 
Processors, and 8th generation  Intel® Core™ i3 Processors
43:0 Current count.63:44 Reserved.
Uncore C-Box Configuration Information (R/O) Package3:0 Specifies the number of C-Box units with progra mmable counters 
(including processor cores and processor graphics).

Register Address: 711H, 1809 MSR_UNC_CBO_1_PERFEVTSEL1Vol. 4 2-353MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E01H, 3585 MSR_UNC_PERF_GLOBAL_CTRL
0 Slice 0 select.
1 Slice 1 select.2 Slice 2 select.
3 Slice 3 select.
4S l i c e  4 s e l e c t .18:5 Reserved.
29 Enable all un core counters.
30 Enable wake on PMI.31 Enable Freezing counter when overflow.
Register Address: E02H, 3586 MSR_UNC_PERF_GLOBAL_STATUS
0 Fixed counter overflowed.
1 An ARB counter overflowed.Table 2-40.  Uncore PMU MSRs Supported by 6th Genera tion, 7th Generation, and 8t h Generation Intel® Core™ 
Register Information / Bit Fields Bit Description Scope2-354 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.17.1  MSRs Introduced in 7th Generation and 8th Generation Intel® Core™ Processors Based 
on Kaby Lake Microarchitecture  and Coffee Lake Microarchitecture
Table 2-41 lists additional MSRs for 7th generation and 8t h generation Intel Core processors with a CPUID Signa-
ture DisplayFamily_DisplayModel value of 06_8EH or 06_9EH.  For an MSR listed in Table 2-41 that also appears in 
the model-specific tables of prior generations,  Table 2-41 supersedes prior generation tables.2 Reserved.
3 A CBox counter overflowed (on any slice).
Table 2-41.  Additional MSRs Supported by the 7th Genera tion and 8th Generation Inte l® Core™ Processors Based 
on Kaby Lake Microarchitecture an d Coffee Lake Microarchitecture 
Register Address: 80H, 128 MSR_TRACE_HUB_STH_ACPIBAR_BASE
NPK Address Used by AET Messages (R/W) Package
0L o c k  B i t
If set, this MSR cannot be re-written anymore. Lo ck bit has to be set in 
order for the AET packets to be directed to NPK MMIO. 
17:1 Reserved.
63:18 ACPIBAR_BASE_ADDRESS 
AET target address in NPK MMIO space. 
Register Address: 1F4H, 500 MSR_PRMRR_PHYS_BASE
2:0 MemType
PRMRR BASE MemType.
45:12 Base
PRMRR Base Address.
63:46 Reserved.
Register Address: 1F5H, 501 MSR_PRMRR_PHYS_MASK
Processor Reserved Memory Range Register - Physical Mask Control Register (R/W) Core
9:0 Reserved.
10 Lock
Lock bit for the PRMRR.
11 VLD
Enable bit for the PRMRR.
45:12 Mask
PRMRR MASK bits.Table 2-40.  Uncore PMU MSRs Supported by 6th Genera tion, 7th Generation, and 8th Generation Intel® Core™ 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-355MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1FBH, 507 MSR_PRMRR_VALID_CONFIG
Valid PRMRR Configurations (R/W) Core
0 1M supported MEE size.
4:1 Reserved.
5 32M supported MEE size.6 64M supported MEE size.
7 128M supported MEE size.
Register Address: 2F4H, 756 MSR_UNCORE_PRMRR_PHYS_BASE1
(R/W)
The PRMRR range is used to protect the processor reserved memory from unauthorized reads and writes. Any IO 
access to this range is aborted. This register controls  the location of the PRMRR rang e by indicating its starting 
address. It functions in tandem with the PRMRR mask register.Package
PAWIDTH-1:12 Range Base
This field corresponds to bits PAWIDTH-1:12 of the base address memory 
range which is allocated to PRMRR memory.
63:PAWIDTH Reserved.
Register Address: 2F5H, 757 MSR_UNCORE_PRMRR_PHYS_MASK1
(R/W)
This register controls the size of the PRMRR range by indicating whic h address bits must match the PRMRR base 
register value.Package
10 Lock
Setting this bit locks all writeable settin gs in this register, including itself.
11 Range_En
Indicates whether the PRMRR range is enabled and valid.
38:12 Range_Mask
This field indicates which address bits must match PRMRR base in order 
to qualify as an PRMRR access.
Register Address: 620H, 1568 MSR_RING_RATIO_LIMIT
Ring Ratio Limit (R/W)
This register provides Min/Max Ratio Limits for the LLC and Ring.Package
6:0 MAX_Ratio
7 Reserved.Table 2-41.  Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based 
on Kaby Lake Microarchitecture and Co ffee Lake Microarchitecture  (Contd.)
Register Information / Bit Fields Bit Description Scope2-356 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.17.2  MSRs Specific to 8th Genera tion Intel® Core™ i3 Processors 
Table 2-42 lists additional MSRs for 8th generation Intel Core i3 processors with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_66H. For an MSR listed in Table 2-42 that also appears in the model-
specific tables of prior generations, Table 2-42 supersede prior generation tables.14:8 MIN_Ratio
Writing to this field controls the mi nimum possible ratio of the LLC/Ring.
NOTES:
1. This MSR is specific to 7th generation and 8th generation Intel® Core™ processors.
Table 2-42.  Additional MSRs Supported by th e 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake  Microarchitecture
Control via IA32_SGXLEPUBKEYHASHn MSR.
Available only if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
18 SGX Global Functions Enable (R/WL) 
Register Address: 350H, 848 MSR_BR_DETECT_CTRL
Branch Monitoring Global Control (R/W)
0 EnMonitoring
Global enable for branch monitoring.
1E n E x c e p t
Enable branch monitoring even t signaling on threshold trip. 
The branch monitoring event handler is signaled via the existing PMI 
signaling mechanism as programmed from the corresponding local APIC 
LVT entry.Table 2-41.  Additional MSRs Supported by the 7th Genera tion and 8th Generation Inte l® Core™ Processors Based 
on Kaby Lake Microarchi tecture and Coffee Lake Mi croarchitecture  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-357MODEL-SPECIFIC REGISTERS (MSRS)
2E n L B R F r z
Enable LBR freeze on threshold trip. This will cause the LBR frozen bit 
58 to be set in IA32_PERF_GL OBAL_STATUS when a triggering 
condition occurs and this bit is enabled.
3D i s a b l e I n G u e s t
When set to ‘1’, branch  monitoring, event tri ggering and LBR freeze 
actions are disabled when operating at VMX non-root operation.
7:4 Reserved.
17:8 WindowSize
Window size defined by WindowCntSel. Values 0 – 1023 are supported.
Once the Window counter reaches the WindowSize count both the 
Window Counter and all Branch Monitoring Counters are cleared.
23:18 Reserved.
25:24 WindowCntSel
Window event count select:
‘00 = Instructions retired.
‘01 = Branch instructions retired‘10 = Return instructions retired.
‘11 = Indirect branch instructions retired.
26 CntAndMode
When set to ‘1’, the overall bran ch monitoring event triggering 
condition is true only if all enabled counters’ threshold conditions are true. 
When ‘0’, the threshol d tripping condition is true if any enabled 
counters’ threshold is true.
Register Address: 351H, 849 MSR_BR_DETECT_STATUS
Branch Monitoring Global Status (R/W)0 Branch Monitoring Event Signaled
When set to '1', Branch Monitoring event signaling is blocked until this

When set to '1', Branch Monitoring event signaling is blocked until this 
bit is cleared by software.
1L B R s V a l i d
This status bit is set to ‘1’ if th e LBR state is considered valid for 
sampling by branch monitoring software.
7:2 Reserved.
8C n t r H i t 0
Branch monitoring counter #0 threshol d hit. This status bit is sticky 
and once set requires clearing by software. Counter operation 
continues independent of the state of the bit.
9C n t r H i t 1
Branch monitoring counter #1 threshol d hit. This status bit is sticky 
continues independent of the state of the bit.Table 2-42.  Additional MSRs Supported by th e 8th Generation Intel®  Core™ i3 Processors
Based on Cannon Lake Mi croarchitecture (Contd.)
Register Information / Bit Fields Bit Description Scope2-358 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
15:10 Reserved.
Reserved for additional branch mo nitoring counters threshold hit 
status.
25:16 CountWindow
The current value of the window counter. The count value is frozen on 
a valid branch monitoring triggering condition. This is a 10-bit unsigned 
value.
31:26 Reserved.
Reserved for future extension of CountWindow.
39:32 Count0
The current value of counter 0 updated after each occurrence of the 
event being counted. The count value is frozen on a valid branch 
monitoring triggering condition (in which case CntrHit0 will also be set). This is an 8-bit signed  value (2’s complement).
Heuristic events which only increment will saturate and freeze at 
maximum value 0xFF (256).
RET-CALL event counter saturate at maximum value 0x7F (+127) and 
minimum value 0x80 (-128).
47:40 Count1
The current value of counter 1 updated after each occurrence of the 
event being counted. The count value is frozen on a valid branch monitoring triggering condition (in which case CntrHit1 will also be set). 
This is an 8-bit signed  value (2’s complement).
Register Address: 354H −355H, 852 −853 MSR_BR_DETECT_COUNTER_CONFIG_i
Branch Monitoring Detect Counter Configuration (R/W)0C n t r E n
Enable counter.
7:1 CntrEvSel
Event select (other values #GP)‘0000000 = RETs.
‘0000001 = RET-CALL bias.
‘0000010 = RET mispredicts.‘0000011 = Branch (all) mispredicts.
‘0000100 = Indirect branch mispredicts.
‘0000101 = Far branch instructions.
14:8 CntrThreshold
Threshold (an unsigned value of 0 to 127 supported). The value 0 of 
counter threshold will result in event signaled after every instruction. 
#GP if threshold is < 2.Table 2-42.  Additional MSRs Supported by th e 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-359MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel 
value of 06_66H.15 MispredEventCnt
Mispredict events counting behavior:
‘0 = Mispredict events are counted in a window.
‘1 = Mispredict events are counted based on a consec utive occurrence. 
CntrThreshold is treated as # of consecutive mispredicts. This control bit only applies to events specif ied by CntrEvSel that involve a 
prediction (0000010, 0000011, 0000100). Setting this bit for other 
events is ignored.
Package C3 Residency Counter (R/O) Package
63:0 Note: C-state values are processor specific C-state code names, 
unrelated to MWAIT exte nsion C-state parameters or ACPI C-states.
14:8 MIN_Ratio
Writing to this field controls th e minimum possible ratio of the 
LLC/Ring.
Core C1 Residency Counter (R/O) Core
63:0 Value since last reset for the Core C1 residency. Counter rate is the 
Max Non-Turbo frequency (same as TSC). This counter counts in case both of the core's threads are in an idle state and at least one of the 
core's thread residency is  in a C1 state or in one of its sub states. The 
counter is updated only after a core  C state exit. Note: Always reads 0 
if core C1 is unsupported. A value of zero indicates that this processor 
does not support core C1 or ne ver entered core C1 level state.
Register Address: 662H, 1634 MSR_CORE_C3_RESIDENCY
Core C3 Residency Counter (R/O) Core
63:0 Will always return 0.Table 2-42.  Additional MSRs Supported by th e 8th Generation Intel®  Core™ i3 Processors
Register Information / Bit Fields Bit Description Scope2-360 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43.  Uncore PMU MSRs Support ed by Intel® Core™ Processors Base d on Cannon Lake Microarchitecture
21 Reserved
Register Address: 702H, 1794 MSR_UNC_CBO_0_PERFCTR0
Register Address: 703H, 1795 MSR_UNC_CBO_0_PERFCTR1
Register Address: 708H, 1800 MSR_UNC_CBO_1_PERFEVTSEL0
Register Address: 709H, 1801 MSR_UNC_CBO_1_PERFEVTSEL1
Register Address: 70AH, 1802 MSR_UNC_CBO_1_PERFCTR0Vol. 4 2-361MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 70BH, 1803 MSR_UNC_CBO_1_PERFCTR1
Register Address: 710H, 1808 MSR_UNC_CBO_2_PERFEVTSEL0
Register Address: 711H, 1809 MSR_UNC_CBO_2_PERFEVTSEL1
Register Address: 712H, 1810 MSR_UNC_CBO_2_PERFCTR0
Register Address: 713H, 1811 MSR_UNC_CBO_2_PERFCTR1
Register Address: 718H, 1816 MSR_UNC_CBO_3_PERFEVTSEL0
Register Address: 719H, 1817 MSR_UNC_CBO_3_PERFEVTSEL1
Register Address: 71AH, 1818 MSR_UNC_CBO_3_PERFCTR0
Register Address: 71BH, 1819 MSR_UNC_CBO_3_PERFCTR1
Register Address: 720H, 1824 MSR_UNC_CBO_4_PERFEVTSEL0
Register Address: 721H, 1825 MSR_UNC_CBO_4_PERFEVTSEL1
Register Address: 722H, 1826 MSR_UNC_CBO_4_PERFCTR0
Register Address: 723H, 1827 MSR_UNC_CBO_4_PERFCTR1
Register Address: 728H, 1832 MSR_UNC_CBO_5_PERFEVTSEL0
Uncore C-Box 5, Counter 0 Event Select MSR Package
Register Address: 729H, 1833 MSR_UNC_CBO_5_PERFEVTSEL1
Uncore C-Box 5, Counter 1 Event Select MSR Package
Register Address: 72AH, 1834 MSR_UNC_CBO_5_PERFCTR0
Uncore C-Box 5, Performance Counter 0 Package
Register Address: 72BH, 1835 MSR_UNC_CBO_5_PERFCTR1
Uncore C-Box 5, Performance Counter 1 Package
Register Address: 730H, 1840 MSR_UNC_CBO_6_PERFEVTSEL0
Uncore C-Box 6, Counter 0 Event Select MSR PackageTable 2-43.  Uncore PMU MSRs Support ed by Intel® Core™ Processors Base d on Cannon Lake Microarchitecture

Register Information / Bit Fields Bit Description Scope2-362 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.17.3  MSRs Introduced in 10th Ge neration Intel® Core™ Processors 
Table 2-44 lists additional MSRs for 10th generati on Intel Core processors with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_7DH or 06_7EH. For an MSR listed in Table 2-44 that also appears in the 
model-specific tables of prior generations, Table 2-44 supersede prior generation tables.Register Address: 731H, 1841 MSR_UNC_CBO_6_PERFEVTSEL1
Uncore C-Box 6, Counter 1 Event Select MSR Package
Register Address: 732H, 1842 MSR_UNC_CBO_6_PERFCTR0
Uncore C-Box 6, Performance Counter 0 Package
Register Address: 733H, 1843 MSR_UNC_CBO_6_PERFCTR1
Uncore C-Box 6, Performance Counter 1 Package
Register Address: 738H, 1848 MSR_UNC_CBO_7_PERFEVTSEL0
Uncore C-Box 7, Counter 0 Event Select MSR Package
Register Address: 739H, 1849 MSR_UNC_CBO_7_PERFEVTSEL1
Uncore C-Box 7, Counter 1 Event Select MSR Package
Register Address: 73AH, 1850 MSR_UNC_CBO_7_PERFCTR0
Uncore C-Box 7, Performance Counter 0 Package
Register Address: 73BH, 1851 MSR_UNC_CBO_7_PERFCTR1
Uncore C-Box 7, Performance Counter 1 Package
1 Slice 1 select.
2 Slice 2 select.3 Slice 3 select.
4S l i c e  4 s e l e c t .
18:5 Reserved.29 Enable all uncore counters.
1 An ARB counter overflowed.
2 Reserved.3 A CBox counter overflowed (on any slice).
63:4 Reserved.Table 2-43.  Uncore PMU MSRs Support ed by Intel® Core™ Processors Base d on Cannon Lake Microarchitecture
Register Information / Bit Fields Bit Description ScopeVol. 4 2-363MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44.  MSRs Supported by the 10th Generation In tel® Core™ Processors (Ice  Lake Microarchitecture) 
28:0 Reserved.29 SPLIT_LOCK_DISABLE
See Section 9.1.2.3, “Featu res to Disable Bus Locks.”
30 Reserved.31 Reserved.
Register Address: 49H, 73 IA32_PREDICT_CMD
Register Address: 8CH, 140 IA32_SGXLEPU BKEYHASH0
Register Address: 8DH, 141 IA32_SGXLEPU BKEYHASH1
Register Address: 8EH, 142 IA32_SGXLEPU BKEYHASH2
Register Address: 8FH, 143 IA32_SGXLEPU BKEYHASH3
Register Address: A0H, 160 MSR_BIOS_MCU_ERRORCODE
BIOS MCU ERRORCODE (R/O)
This MSR indicates if WRMSR 0x79 failed to configure PRM memory and gives a hint to debug BIOS.Package
15:0 Error Codes (R/O) Package
30:16 Reserved.31 MCU Partial Success (R/O)
When set to 1, WRMSR 0x 79 skipped part of the functionality during 
BIOS.Thread
Register Address: A5H, 165 MSR_FIT_BIOS_ERROR
FIT BIOS ERROR (R/W)
Report error codes for debug in case the processo r failed to parse the Firmware Table in BIOS.
Can also be used to log BIOS in formation.Thread
7:0 Error Codes (R/W)
Error codes for debug.
15:8 Entry Type (R/W)
Failed FIT entry type.
16 FIT MCU Entry (R/W)
FIT contains MCU entry.2-364 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
62:17 Reserved.
63 LOCK (R/W)
When set to 1, writes to  this MSR will be skipped.
Register Address: 151H, 337 MSR_BIOS_DONE
BIOS Done (R/WO) Thread
0 BIOS Done Indication (R/WO)
Set by BIOS when it fi nishes programming the processor and wants to 
lock the memory configuration from changes by software that is running 
on this thread.
Writes to the bit will be ignored if EAX[0] is 0.Thread
1P a c k a g e  B I O S  D o n e  Indication (R/O)
When set to 1, all threads in the package have bit 0 of this MSR set.Package
31:2 Reserved.
Register Address: 1F1H, 497 MSR_CRASHLOG_CONTROL
Write Data to a Crash Log Configuration Thread
0 CDDIS: CrashDump_Disable
If set, indicates that Crash Dump is disabled.
2:0 MEMTYPE: PRMRR BA SE Memory Type.
3 CONFIGURED: PRMRR BASE Configured.11:4 Reserved.
51:12 BASE: PRMRR Base Address.
63:52 Reserved.
Register Address: 30CH, 780 IA32_FIXED_CTR3
Fixed-Function Performance Counter Register 3 (R/W)
Bit definitions are the same as found in IA32_FIXED_CTR0, offset 309H. See Table 2-2.Thread
Register Address: 329H, 809 MSR_PERF_METRICS
Performance Metrics (R/W)
Reports metrics directly. Software can check (and/or expose to its guests) the availability of PERF_METRICS feature 
using IA32_PERF_CAPABILITIES.PER F_METRICS_AVAILABLE (bit 15).Thread
7:0 Retiring. Percent of utilized slots by  uops that eventually retire (commit).
15:8 Bad Speculation. Percent of wasted slots due to incorrect speculation, 
covering utilized by uops that do not retire, or recovery bubbles 
(unutilized slots).
23:16 Frontend Bound. Percent of unutilized slots where front-end did not 
deliver a uop while back-end is ready.Table 2-44.  MSRs Supported by the 10th  Generation Intel® Core™ Processors (Ice Lake Micr oarchitecture)  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-365MODEL-SPECIFIC REGISTERS (MSRS)
31:24 Backend Bound. Percent of unutilized slots where a uop was not delivered 
to back-end due to lack  of back-end resources.
Register Address: 3F2H, 1010 MSR_PEBS_DATA_CFG
PEBS Data Configuration (R/W)
Provides software the capabili ty to select data groups of interest and thus reduce the record  size in memory and 
record generation latency. Hence, a PEBS record's size an d layout vary based on the selected groups. The MSR also 
allows software to select LBR depth for branch data records.Thread
0 Memory Info.
Setting this bit will capture memory  information such as the linear 
address, data source and latency of the memory access in the PEBS 
record.
1G P R s .
Setting this bit will capture the conten ts of the General Purpose registers 
2X M M s .
Setting this bit will capture the conten ts of the XMM registers in the PEBS 
record.
3L B R s .
Setting this bit will capture LBR TO, FROM, and INFO in the PEBS record.
23:4 Reserved.
31:24 LBR Entries.
Set the field to the desi red number of entries - 1. For example, if the 
include 32 LBR entries, set the LBR_entries field to 31 (0x1F). To ensure all PEBS records are 16-byte aligned,  software can use LBR_entries that 
is multiple of 3.
Register Address: 541H, 1345 MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W) Core
0 L1 Scrubbing Enable
When set to 1, en able L1 scrubbing.
31:1 Reserved.
Register Address: 657H, 1623 MSR_FAST_UNCORE_MSRS_CTL
Fast WRMSR/RDMSR Control MSR (R/W) Thread
3:0 FAST_ACCESS_ENABLE:
Bit 0: When set to '1', provides a hi nt for the hardware to enable fast 
access mode for the IA32_HWP_REQUEST MSR. 
This bit is sticky and is cleaned by the hardware only during reset time. 
This bit is valid only if FAST_UNCOR E_MSRS_CAPABILITY[0]  is set. Setting 
this bit will cause CPUID[6].EAX[18] to be set.
Register Address: 65EH, 1630 MSR_FAST_UNCORE_MSRS_STATUS
Indication of Uncore MSRs, Post Write Activates ThreadTable 2-44.  MSRs Supported by the 10th  Generation Intel® Core™ Processors (Ice Lake Micr oarchitecture)  (Contd.)
Register Information / Bit Fields Bit Description Scope2-366 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.17.4  MSRs Introduced in the 11th Generation Intel® Core™ Processors based on Tiger Lake 
Table 2-45 lists additional MSRs for 11th generati on Intel Core processors with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_8CH or 06_8DH. The MSRs listed in Table 2-44 are also supported by 
these processors. For an MSR listed in Table 2-45 that also appears in the model-specific tables of prior genera-
tions, Table 2-45 supersedes prior generation tables.0 Indicates whether the CPU is still in the middle of writing 
IA32_HWP_REQUEST MSR, even after the WRMSR instruction has retired. 
A value of 1 indicates the last wr ite of IA32_HWP_REQUEST is still 
ongoing. 
A value of 0 indicates the last write of IA32_HWP_REQUEST is visible 
outside the logical processor.
Software can use the status of this bit to avoid overwriting 
IA32_HWP_REQUEST.
Register Address: 65FH, 1631 MSR_FAST_UNCORE_MSRS_CAPABILITY
Fast WRMSR/RDMSR Enumeration MSR (R/O) Thread3:0 MSRS_CAPABILITY:

ongoing. 
Bit 0: If set to ‘1’, hardware supports the fa st access mode for the 
IA32_HWP_REQUEST MSR.
Table 2-45.  Additional MSRs Supported by the 11th Ge neration Intel® Core™ Processors Based on Tiger Lake 
Microarchitecture 
BIOS MCU ERRORCODE (R/O) Package
15:0 Error Codes
Register Address: A7H, 167 MSR_BIOS_DEBUG
BIOS DEBUG (R/O)
This MSR indicates if WRMSR 79H failed to configure PRM memory and gives a hint to debug BIOS.Thread
30:0 Reserved.Table 2-44.  MSRs Supported by the 10th  Generation Intel® Core™ Processors (Ice Lake Micr oarchitecture)  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-367MODEL-SPECIFIC REGISTERS (MSRS)
31 MCU Partial Success 
When set to 1, WRMSR 79H skipped part of the func tionality during 
BIOS.
IA32 Core Capabilities Register (R/O)
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior. Package
2 FUSA_SUPPORTED
3 RSM_IN_CPL0_ONLY
When set to 1, the RSM instruction is only allowed in CPL0 (#GP 
triggered in any CPL != 0). 
When set to 0, then  any CPL may execute the RSM instruction.
4 Reserved.5S P L I T _ L O C K _ D I SABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL 
(MSR address 33H).
31:6 Reserved.
IA32_VMX_PROCBASED_CTLS3
This MSR enumerates the allowed 1-settings of the third set of processor-based contro ls. Specifically, VM entry 
allows bit X of the tertiary processor-base d VM-execution controls to be 1 if and only if bit X of the MSR is set to 1. 
If bit X of the MSR is cleared to 0, VM  entry fails if control X and the “activ ate tertiary controls” primary processor-
based VM-execution control are both 1.Core
0L O A D I W K E Y
This control determines whether executions of LOADIWKEY cause VM 
exits.
Register Address: 601H, 1537 MSR_VR_CURRENT_CONFIG
Power Limit 4 (PL4)
Package-level maximum power limit (in Watts).  It is a proactive, instantaneous limit.Package
12:0 PL4 Value
PL4 value in 0.125 A increments. This field is locked by 
VR_CURRENT_CONFIG[LOCK]. When th e LOCK bit is set to 1b, this 
field becomes Read Only.
30:13 Reserved.
31 Lock Indication (LOCK)
This bit will lock the CURRENT_LIMIT settings in this register and will 
also lock this setting. This me ans that once set to 1b, the 
CURRENT_LIMIT setting and this bit become Read Only until the next 
Warm Reset.Table 2-45.  Additional MSRs Supported by the 11th Ge neration Intel® Core™ Processors Based on Tiger Lake 
Microarchitect ure  (Contd.)
Register Information / Bit Fields Bit Description Scope2-368 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
62:32 Not in use.
Configure User Mode CET (R/W) 
Register Address: 6A2H, 1698 IA32_S_CET
Configure Supervisor Mode CET (R/W)
Register Address: 6A4H, 1700 IA32_PL0_SSP
Linear address to be loaded  into SSP on transition to  privilege level 0. (R/W)
Register Address: 6A5H, 1701 IA32_PL1_SSP
Linear address to be loaded  into SSP on transition to  privilege level 1. (R/W)
Register Address: 6A6H, 1702 IA32_PL2_SSP
Linear address to be loaded  into SSP on transition to  privilege level 2. (R/W)
Register Address: 6A7H, 1703 IA32_PL3_SSP
Linear address to be loaded  into SSP on transition to  privilege level 3. (R/W)
Register Address: 6A8H, 1704 IA32_INTERRUPT _SSP_TABLE_ADDR
Linear address of a table of seven shadow stack pointers th at are selected in IA-32e mode using the IST index (when 
not 0) from the interrup t gate descriptor. (R/W)
Register Address: 990H, 2448 IA32_COPY_STATUS1
Register Address: 991H, 2449 IA32_IWKEYBACKUP_STATUS1
See Table 2-2. Platform
Register Address: C82H, 3202 IA32_L2_QOS_CFGTable 2-45.  Additional MSRs Supported by the 11th Ge neration Intel® Core™ Processors Based on Tiger Lake 
Microarchitecture  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-369MODEL-SPECIFIC REGISTERS (MSRS)
2.17.5  MSRs Introduced in th e 12th and 13th Generation Intel®  Core™ Processors Supporting 
Performance Hybrid Architecture
Table 2-46 lists additional MSRs for 12th and 13th gene ration Intel Core processors with a CPUID Signature 
DisplayFamily_DisplayModel value of  06_97H, 06_9AH, 06_BAH, 06_B7H, or 06_BFH. Table 2-47 lists the MSRs 
unique to the processor P-core. Table 2-48 lists the MSRs unique to the processor E-core. 
The MSRs listed in Table 2-441 and Table 2-45 are also supported by thes e processors. For an MSR listed in Table 
2-46, Table 2-47, or Table 2-48 that also appears in the model-specific tables of prior generations, Table 2-46, 
Table 2-47, and Table 2-48 supersede prior generation tables. IA32_CR_L2_QOS_CFG
This MSR provides software an enumeration of the paramete rs that L2 QoS (Intel RDT)  support in any particular 
implementation.Core
0C D P _ E N A B L E
When set to 1, it will enable the co de and data priori tization for the 
L2 CAT/Intel RDT feature. 
When set to 0, code and data prioritization is di sabled for L2 CAT/Intel 
RDT. See Chapter 18, “Debug, Branch Profile, TSC, and Intel® Resource 
Director Technology (Intel® RDT) Features‚” for further details on CDP.
Register Address: D10H −D17H, 3220 −3351 IA32_L2_QOS_MASK_[0-7]
IA32_CR_L2_QOS_MASK_[0-7]
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug , Branch Profile, TSC, and 
Intel® Resource Director Tech nology (Intel® RDT) Features.”Package
19:0 WAYS_MASK
Setting a 1 in this bit X allows threads with CL OS <n> (where N is [0-
7]) to allocate to way X in the ML C. Ones are only allowed to be 
written to ways that phys ically exist in the MLC 
(CPUID.4.2:EBX[31:22] will indicate this). 
Writing a 1 to a value beyond the highest way or a non-contiguous 
set of 1s will cause a #GP on the WRMSR to this MSR.
Register Address: D91H, 3473 IA32_COPY_LOCAL_TO_PLATFORM1
Register Address: D92H, 3474 IA32_COPY_PLATFORM_TO_LOCAL1
NOTES:
1. Further details on Key Locker and usage of this MSR can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html .
1. MSRs at the following addresses are not su pported in the 12th and 13th generation Intel Core processor E-core: 30CH, 329H, 54 1H, 
and 657H. The MSR at address 657H is not supported in th e 12th and 13th generation Intel Core processor P-core.Table 2-45.  Additional MSRs Supported by the 11th Ge neration Intel® Core™ Processors Based on Tiger Lake 
Register Information / Bit Fields Bit Description Scope2-370 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46.  Additional MSRs  Supported by the 12th and 13th Generati on Intel® Core™ Proc essors Supporting 
Performance Hybrid Architecture 
26:0 Reserved.27 UC_STORE_THROTTLE
If set to 1, when enabled, the processor will only allow one in-
progress UC store at a time.
28 UC_LOCK_DISABLE
If set to 1, a UC lock wi ll cause a #GP(0) exception.
IA32_ARCH_CAPABILITIES[bit 10] en umerates support for this MSR.
General Performance Counter 6 (R/W)
General Performance Counter 7 (R/W)
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1. 
0 STLB_QOS_SUPPORTED

When set to 1, the STLB QoS fe ature is supported and the STLB 
QoS MSRs (1A8FH -1A97H) are acce ssible. When set to 0, access 
to these MSRs will #GP.
2 FUSA_SUPPORTED3 RSM_IN_CPL0_ONLY
When set to 0, then  any CPL may execute the RSM instruction.Vol. 4 2-371MODEL-SPECIFIC REGISTERS (MSRS)
4 UC_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 28 of MSR_MEMORY_CTRL 
5 SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL.
6 SNOOP_FILTER_QOS_SUPPORTED
When set to 1, the Snoop Filter Qos Mask MSRs are supported. 
When set to 0, access to these MSRs will #GP.
7 UC_STORE_THROTTLING_SUPPORTED
When set 1, UC Store throttl e capability exist through 
MSR_MEMORY_CTRL (33H) bit 27.
Enumeration of Architectural Features (R/O)
See Table 2-20. Core
IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR. See Table 2-2.Package
Register Address: 1ADH, 429 MSR_PRIMARY_TURBO_RATIO_LIMIT
Primary Maximum Turb o Ratio Limit (R/W)
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1. Specifies Maximum Ratio Limit for each 
group. Maximum ratio for groups with mo re cores must decrease monotonically.Package
7:0 MAX_TURBO_GROUP_0:
Maximum turbo ratio limi t with 1 core active.
15:8 MAX_TURBO_GROUP_1:
Maximum turbo ratio limi t with 2 cores active.
23:16 MAX_TURBO_GROUP_2:
Maximum turbo ratio limi t with 3 cores active.
31:24 MAX_TURBO_GROUP_3:
Maximum turbo ratio limi t with 4 cores active.
39:32 MAX_TURBO_GROUP_4:
Maximum turbo ratio limi t with 5 cores active.Table 2-46.  Additional MS Rs Supported by the 12th and 13th Genera tion Intel® Core™ Pr ocessors Supporting 
Performance Hybrid Architecture  (Contd.)
Register Information / Bit Fields Bit Description Scope2-372 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
47:40 MAX_TURBO_GROUP_5:
Maximum turbo ratio limi t with 6 cores active.
55:48 MAX_TURBO_GROUP_6:
Maximum turbo ratio limi t with 7 cores active.
63:56 MAX_TURBO_GROUP_7:
Maximum turbo ratio limi t with 8 cores active.
Full Width Writable IA32_PMC6 Alias (R/W)
Full Width Writable IA32_PMC7 Alias (R/W)
Register Address: 650H, 1616 MSR_SECONDARY_TURBO_RATIO_LIMIT
Secondary Maximum Turbo Ratio Limit (R/W)
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1.
Specifies Maximum Ratio Limit for each group. Maximu m ratio for groups with more cores must decrease 
monotonically.Package
Maximum turbo ratio limi t with 5 cores active.
ACPI C-States.ModuleTable 2-46.  Additional MSRs  Supported by the 12th and 13th Generati on Intel® Core™ Proc essors Supporting 
Performance Hybrid Ar chitecture  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-373MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table 2-47 are unique to the 12th and 13 th generation Intel Core processor P-core. These MSRs 
are not supported on the processor E-core.63:0 Time that this module is in mo dule-specific C6 states since last 
reset. Counts at 1 Mhz frequency.
Specifies the PK permissions associated with ea ch protection domain for supervisor pages (R/W)
Memory Encryption Capability MSR
Last Branch Record  Maximum Stack Depth Register (R/W)
Register Address: 1500H −151FH, 5376 −5407IA32_LBR_x_FROM_IP
Last Branch Record Entry X Source IP Register (R/W)
Register Address: 1600H −161FH, 5632 −5663IA32_LBR_x_TO_IP
Thread Feedback Characteristics (R/O)
See Table 2-2.Table 2-46.  Additional MS Rs Supported by the 12th and 13th Genera tion Intel® Core™ Pr ocessors Supporting 
Register Information / Bit Fields Bit Description Scope2-374 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-47.  MSRs Supported by 12th and 13 th Generation Intel® Core™ Processor P-core
Register Address: 1A4H, 420 MSR_PREFETCH_CONTROL
Prefetch Disable Bits (R/W)
0 L2_HARDWARE_PRE FETCHER_DISABLE
If 1, disables the L2 hardware prefetcher, which fetches additional 
lines of code or data  into the L2 cache.
1 L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE
If 1, disables the adjacent cache line prefetcher, which fetches the 
cache line that comp rises a cache line pair (128 bytes).
2 DCU_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L1 data cache prefetcher, which fetches the next 
cache line into L1 data cache.
3 DCU_IP_PREFETCHER_DISABLE
If 1, disables the L1 data cache IP prefetcher, which uses sequential 
load history (based on instruction pointer of previous loads) to determine whether to prefetch additional lines.
4 Reserved.5A M P _ P R E F E T C H _ D I S A B L E
If 1, disables the L2 Adaptive Multipath Probability (AMP) prefetcher.
FrontEnd Precise Event Condition Select (R/W) 
See Table 2-39.Thread
Register Address: 540H, 1344 MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W) Thread
0 WB_MEM_STRM_LD_DISABLE 
Disable streaming behavior for MOVNTDQA loads to WB memory 
type. If set, these accesses will be  treated like regular cacheable 
loads (Data will be cached).
Core Microarchitectur e Control MSR (R/W)
See Table 2-44.Core
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] ≥ 0.
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and 
Intel® Resource Director Tech nology (Intel® RDT) Features.”CoreVol. 4 2-375MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table 2-48 are unique to the 12th and 13th generation Intel Core processor E-core. These MSRs 
are not supported on the processor P-core.
Table 2-49 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel 
value of 06_97H, 06_9AH, 06_BAH, 06_B7H, or 06_BFH.19:0 WAYS_MASK
Setting a 1 in this bit X allows threads with CLOS <n> (where N is [0-
Table 2-48.  MSRs Supported by 12th and 13th Generation Intel® Core™ Processor E-core
Register Address: D10H −D1FH, 3220 −3359 IA32_L2_QOS_MASK_[0-15]
IA32_CR_L2_QOS_MASK_[0-15]

Intel® Resource Director Tech nology (Intel® RDT) Features.”Module
Setting a 1 in this bit X allows threads with CLOS  <n> (where N 
is [0-7]) to allocate to way X in the MLC. Ones are only allowed to 
be written to ways that ph ysically exist in the MLC 
Writing a 1 to a value beyond the highest way or a non-
contiguous set of 1s will cause a #GP on the WRMSR to this MSR.
Register Address: 1309H −130BH, 4873
−4875MSR_RELOAD_FIXED_CTRx
47:0 Value loaded into IA32_FIXED_CTRx when a PEBS record is 
generated while PEBS_EN_FIXE Dx = 1 and PEBS_OUTPUT = 
01B in IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.
Register Address: 14C1H −14C6H, 5313 −5318 MSR_RELOAD_PMCx
Reload value for IA32_PMCx (R/W) Core
47:0 Value loaded into IA32_PMCx wh en a PEBS record is generated 
while PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE, and PMCx is overflowed.
63:48 Reserved.Table 2-47.  MSRs Supported by 12th and 13 th Generation Intel® Core™ Processor P-core
Register Information / Bit Fields Bit Description Scope2-376 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-49.  Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
3:0 Specifies the number of C-Box units with progra mmable counters 
Register Address: 2000H, 8192 MSR_UNC_CBO_0_PERFEVTSEL0
Register Address: 2001H, 8193 MSR_UNC_CBO_0_PERFEVTSEL1
Register Address: 2002H, 8194 MSR_UNC_CBO_0_PERFCTR0
Register Address: 2003H, 8195 MSR_UNC_CBO_0_PERFCTR1
Register Address: 2008H, 8200 MSR_UNC_CBO_1_PERFEVTSEL0
Register Address: 2009H, 8201 MSR_UNC_CBO_1_PERFEVTSEL1
Register Address: 200AH, 8202 MSR_UNC_CBO_1_PERFCTR0
Register Address: 200BH, 8203 MSR_UNC_CBO_1_PERFCTR1
Register Address: 2010H, 8208 MSR_UNC_CBO_2_PERFEVTSEL0
Register Address: 2011H, 8209 MSR_UNC_CBO_2_PERFEVTSEL1
Register Address: 2012H, 8210 MSR_UNC_CBO_2_PERFCTR0
Register Address: 2013H, 8211 MSR_UNC_CBO_2_PERFCTR1
Register Address: 2018H, 8216 MSR_UNC_CBO_3_PERFEVTSEL0
Register Address: 2019H, 8217 MSR_UNC_CBO_3_PERFEVTSEL1
Register Address: 201AH, 8218 MSR_UNC_CBO_3_PERFCTR0
Register Address: 201BH, 8219 MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1 PackageVol. 4 2-377MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 2020H, 8224 MSR_UNC_CBO_4_PERFEVTSEL0
Register Address: 2021H, 8225 MSR_UNC_CBO_4_PERFEVTSEL1
Register Address: 2022H, 8226 MSR_UNC_CBO_4_PERFCTR0
Register Address: 2023H, 8227 MSR_UNC_CBO_4_PERFCTR1
Register Address: 2028H, 8232 MSR_UNC_CBO_5_PERFEVTSEL0
Register Address: 2029H, 8233 MSR_UNC_CBO_5_PERFEVTSEL1
Register Address: 202AH, 8234 MSR_UNC_CBO_5_PERFCTR0
Register Address: 202BH, 8235 MSR_UNC_CBO_5_PERFCTR1
Register Address: 2030H, 8240 MSR_UNC_CBO_6_PERFEVTSEL0
Uncore C-Box 6, Counter 0 Event Select MSR Package
Register Address: 2031H, 8241 MSR_UNC_CBO_6_PERFEVTSEL1
Register Address: 2032H, 8242 MSR_UNC_CBO_6_PERFCTR0
Register Address: 2033H, 8243 MSR_UNC_CBO_6_PERFCTR1
Register Address: 2038H, 8248 MSR_UNC_CBO_7_PERFEVTSEL0
Register Address: 2039H, 8249 MSR_UNC_CBO_7_PERFEVTSEL1
Register Address: 203AH, 8250 MSR_UNC_CBO_7_PERFCTR0
Register Address: 203BH, 8251 MSR_UNC_CBO_7_PERFCTR1
Register Address: 2040H, 8256 MSR_UNC_CBO_8_PERFEVTSEL0
Uncore C-Box 8, Counter 0 Event Select MSR Package
Register Address: 2041H, 8257 MSR_UNC_CBO_8_PERFEVTSEL1
Uncore C-Box 8, Counter 1 Event Select MSR Package
Register Address: 2042H, 8258 MSR_UNC_CBO_8_PERFCTR0Table 2-49.  Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Information / Bit Fields Bit Description Scope2-378 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 8, Performance Counter 0 Package
Register Address: 2043H, 8259 MSR_UNC_CBO_8_PERFCTR1
Uncore C-Box 8, Performance Counter 1 Package
Register Address: 2048H, 8264 MSR_UNC_CBO_9_PERFEVTSEL0
Uncore C-Box 9, Counter 0 Event Select MSR Package
Register Address: 2049H, 8265 MSR_UNC_CBO_9_PERFEVTSEL1
Uncore C-Box 9, Counter 1 Event Select MSR Package
Register Address: 204AH, 8266 MSR_UNC_CBO_9_PERFCTR0
Uncore C-Box 9, Performance Counter 0 Package
Register Address: 204BH, 8267 MSR_UNC_CBO_9_PERFCTR1
Uncore C-Box 9, Performance Counter 1 Package
Register Address: 2FD0H, 12240 MSR_UNC_ARB_0_PERFEVTSEL0
Uncore Arb Unit 0, Counter  0 Event Select MSR Package
Register Address: 2FD1H, 12241 MSR_UNC_ARB_0_PERFEVTSEL1
Uncore Arb Unit 0, Counter  1 Event Select MSR Package
Register Address: 2FD2H, 12242 MSR_UNC_ARB_0_PERFCTR0
Uncore Arb Unit 0, Performance Counter 0 Package
Register Address: 2FD3H, 12243 MSR_UNC_ARB_0_PERFCTR1
Uncore Arb Unit 0, Performance Counter 1 Package
Register Address: 2FD4H, 12244 MSR_UNC_ARB_0_PERF_STATUS
Uncore Arb Unit 0, Performance Status Package
Register Address: 2FD5H, 12245 MSR_UNC_ARB_0_PERF_CTRL
Uncore Arb Unit 0, Performance Control Package
Register Address: 2FD8H, 12248 MSR_UNC_ARB_1_PERFEVTSEL0
Uncore Arb Unit 1, Counter  0 Event Select MSR Package
Register Address: 2FD9H, 12249 MSR_UNC_ARB_1_PERFEVTSEL1
Uncore Arb Unit 1, Counter  1 Event Select MSR Package
Register Address: 2FDAH, 12250 MSR_UNC_ARB_1_PERFCTR0
Uncore Arb Unit 1, Performance Counter 0 Package
Register Address: 2FDBH, 12251 MSR_UNC_ARB_1_PERFCTR1
Uncore Arb Unit 1, Performance Counter 1 Package
Register Address: 2FDCH, 12252 MSR_UNC_ARB_1_PERF_STATUS
Uncore Arb Unit 1, Performance Status Package
Register Address: 2FDDH, 12253 MSR_UNC_ARB_1_PERF_CTRL
Uncore Arb Unit 1, Performance Control Package
Register Address: 2FDEH, 12254 MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W) PackageTable 2-49.  Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Information / Bit Fields Bit Description ScopeVol. 4 2-379MODEL-SPECIFIC REGISTERS (MSRS)
2.17.6  MSRs Introduced in the Inte l® Xeon® Scalable Processor Family 
The Intel® Xeon® Scalable Processor Family (CPUID Signature DisplayFamily_DisplayModel value of 06_55H) 
supports the MSRs listed in Table 2-50.19:0 Reserved.
21 Reserved.22 Enable counting.
Register Address: 2FDFH, 12255 MSR_UNC_PERF _FIXED_CTR
43:0 Current count.
63:44 Reserved.
Register Address: 2FF0H, 12272 MSR_UNC_PERF_GLOBAL_CTRL
4 Slice 4 select.18:5 Reserved.
Register Address: 2FF2H, 12274 MSR_UNC_PERF_GLOBAL_STATUS
1 An ARB counter overflowed.2 Reserved.
Table 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
DisplayFamily_DisplayMod el Value of 06_55H 

Register Address: 3AH, 58 IA32_FEATURE_CONTROLTable 2-49.  Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Information / Bit Fields Bit Description Scope2-380 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
18 SGX Global Functions Enable (R/WL) 20 LMCE_ENABLED (R/WL) 63:21 Reserved.
Protected Processor Inventory Number (R/O) Package63:0 Protected Processor Inventory Number (R/O)
39:31 Reserved.Table 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_55H  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-381MODEL-SPECIFIC REGISTERS (MSRS)
The following C-state code name encodings are supported:000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)011b: C6 (retention)
111b: No Package C state limits. All C states supp orted by the processor 
16 Automatic C-State Conversion Enable (R/W)
25 C3 State Auto Demotion Enable (R/W)26 C1 State Auto Demotion Enable (R/W)
28 Enable C1 Undemotion (R/W)29 Package C State Demotion Enable (R/W)
7:0 Count.8 MCG_CTL_P
9 MCG_EXT_P
10 MCP_CMCI_P11 MCG_TES_PTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-382 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
24 MCG_SER_P25 MCG_EM_P
If set to 1 indicates that the SMM co de access restriction is supported and 
a host-space interface is available to SMM handler.
If set to 1 indicates that the SMM lo ng flow indicator is supported and a 
host-space interface is available to SMM handler.
See Table 2-2.Table 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-383MODEL-SPECIFIC REGISTERS (MSRS)
This register defines the ratio limits. RATIO[0:7] must be populated in ascending order. RATIO[i+1] must be less than 
or equal to RATIO[i]. Entries with RATIO[ i] will be ignored. If any of the rules above are broken, the configuration is 
silently rejected. If the programmed ratio is: 
• Above the fused ratio for that co re count, it will be clipped to the fuse limits (assuming !OC).
• Below the min supported ratio, it will be clipped.Package
7:0 RATIO_0
Defines ratio limits.
15:8 RATIO_1
Defines ratio limits.Table 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-384 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
23:16 RATIO_2
31:24 RATIO_3
39:32 RATIO_4
47:40 RATIO_5
55:48 RATIO_6
63:56 RATIO_7
Register Address: 1AEH, 430 MSR_TURBO_RATI O_LIMIT_CORES
This register defines the active core ranges for each frequency point. NUMCORE[0:7] must be populated in ascending 
order. NUMCORE[i+1] must be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored. The last valid entry must have NUMCORE >= the number of cores in the SKU. If any of the rules above are broken, the configuration 
is silently rejected.Package
7:0 NUMCORE_0
Defines the active core ranges for each frequency point.
15:8 NUMCORE_1
23:16 NUMCORE_2
31:24 NUMCORE_3
39:32 NUMCORE_4
47:40 NUMCORE_5
55:48 NUMCORE_6
63:56 NUMCORE_7
See Table 2-2. CoreTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-385MODEL-SPECIFIC REGISTERS (MSRS)

Bank MC0 reports MC errors from the IFU module.CoreTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-386 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC0 reports MC errors from the IFU module.Core
Bank MC1 reports MC errors from the DCU module.Core
Bank MC2 reports MC errors from the DTLB module.Core
Bank MC3 reports MC errors from the MLC module.Core
Register Address: 40DH, 1037 IA32_MC3_STATUSTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-387MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC4 reports MC errors from the PCU module.Package
Bank MC5 reports MC errors from a link interconnect module.Package
Bank MC6 reports MC errors from the integrated I/O module.PackageTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-388 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC7 reports MC errors from the M2M 0.Package
Bank MC8 reports MC errors from the M2M 1.Package
Banks MC9 - MC11 report MC errors from the CHA.Package
Register Address: 426H, 1062 IA32_MC9_ADDRTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 

Register Information / Bit Fields Bit Description ScopeVol. 4 2-389MODEL-SPECIFIC REGISTERS (MSRS)
Banks MC12 report MC errors from each channel of a link in terconnect module.Package
Banks MC12 report MC errors from each channel of a link in terconnect module.PackageTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-390 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Banks MC12 report MC errors  from each channel of a link interconnect module.Package
Banks MC13 through MC 18 report MC errors  from the integrated memory controllers.Package
Register Address: 43FH, 1087 IA32_MC15_MISCTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-391MODEL-SPECIFIC REGISTERS (MSRS)

Banks MC13 through MC 18 report MC errors  from the integrated memory controllers.PackageTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-392 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Bank MC19 reports MC errors from a link interconnect module.Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFOTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-393MODEL-SPECIFIC REGISTERS (MSRS)
Out of reset, the min_ratio an d max_ratio fields represent the widest possib le range of uncore frequencies. Writing to 
Event encoding:0x00: No monitoring.
0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.0x03: Local memory bandwidth monitoring.
All other encoding reserved.
41:32 RMID (R/W)63:42 Reserved.
9:0 RMID 
31:10 Reserved.
51:32 COS (R/W)63: 52 Reserved.
63:20 Reserved.Table 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-394 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: C92H, 3218 IA32_L3_QOS_MASK_2
L3 Class Of Service Mask - COS 3 (R/W).
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8.PackageTable 2-50.  MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-395MODEL-SPECIFIC REGISTERS (MSRS)
0:19 CBM: Bit vector of available L3 ways for COS 9 enforcement.
Register Information / Bit Fields Bit Description Scope2-396 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.17.7  MSRs Specific to  the 3rd Generation Intel® Xeon® Sc alable Processor Family Based on 
Ice Lake Microarchitecture
The 3rd generation Intel® Xeon® Scalable Processor Family based on Ice Lake microarchitecture (CPUID Signature 
DisplayFamily_DisplayModel value of 06_6AH or 06_6 CH) support the MSRs listed in Table 2-51.
Table 2-51.  MSRs Supported by the 3rd Generation Intel®  Xeon® Scalable Processor Family with a CPUID Signature 
DisplayFamily_DisplayModel Va lue of 06_6AH or 06_6CH 
Register Address: 612H, 1554 MSR_PACKAGE_ENERGY_TIME_STATUS
Package energy consumed by the entire CPU (R/W) Package

31:0 Total amount of energy consumed since last reset.63:32 Total time elapsed when the energy was last updated. This is a monotonic 
increment counter with au to wrap back to zero after overflow. Unit is 
10ns.
Allows software to set power limits for the DRAM domain and measurement attribut es associated with each limit. Package
14:0 DRAM_PP_PWR_LIM:
Power Limit[0] for DDR domain. Units = Watts, Format = 11.3, Resolution = 
0.125W, Range = 0-2047.875W.
15 PWR_LIM_CTRL_EN:
Power Limit[0] enable bit for DDR domain.
16 Reserved.23:17 CTRL_TIME_WIN:
Power Limit[0] time window Y value,  for DDR domain. Actual time_window 
for RAPL is: 
(1/1024 seconds) * (1+(x/4)) * (2^y)
62:24 Reserved.
63 PP_PWR_LIM_LOCK:
When set, this entire register becomes read-only. This bit will typically be 
set by BIOS during boot.
DRAM Power Parameters (R/W) PackageVol. 4 2-397MODEL-SPECIFIC REGISTERS (MSRS)
14:0 Spec DRAM Power (DRAM_TDP):
The Spec power allowed for DRAM. The TDP setting istypical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
30:16 Minimal DRAM Power (DRAM_MIN_PWR):
The minimal power setting allowed for DRAM. Lower
values will be clamped to this value. The minimum
setting is typical (not guaranteed).
The units for this value are defined inMSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
31 Reserved.46:32 Maximal Package Power (DRAM_MAX_PWR):
The maximal power setting allowed for DRAM. Highervalues will be clamped to this value. The maximum
47 Reserved.54:48Maximal Time Window (DRAM_MAX_WIN):
The maximal time window allowed for the DRAM.Higher values will be clamped to this value.x = PKG_MAX_WIN[54:53]
y = PKG_MAX_WIN[52:48]
The timing interval window is a floating-point number given by 1.x *power(2,y).The unit of measurement is defined in
MSR_DRAM_POWER_INFO_UNIT[TIME_UNIT].
62:55 Reserved.
63LOCK:
Lock bit to lock the register.
See Table 2-2.Table 2-51.  MSRs Supported by the 3rd Generation Intel®  Xeon® Scalable Processor Family with a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH  (Contd.)
Register Information / Bit Fields Bit Description Scope2-398 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.17.8  MSRs Specific to the 4th and 5th Genera tion Intel® Xeon® Scal able Processor Families
The 4th generation Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture (CPUID 
Signature DisplayFamily_DisplayModel value of 06_8FH) and the 5th generation Intel® Xeon® Scalable Processor 
Family based on Emerald Rapids microarchitecture (C PUID Signature DisplayFamily_DisplayModel value of 
06_CFH) both support the MSRs listed in Section 2.17, “MSRs In the 6th—13th Generation Intel® Core™ Proces-
sors, 1st—5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Gener-
ation Intel® Core™ i3 Processors, and Intel® Xeon® E Proc essors,” including Table 2-52. For an MSR listed in Table 
2-52 that also appears in the model-specific tables of prior generations, Table 2-52 supersedes prior generation 
tables.
Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Inte l® Xeon® Scalable Processor Families
(CPUID Signature DisplayF amily_DisplayModel Values of 06_8FH and 06_CFH)
Memory Control Register (R/W) Core
27:0 Reserved.28 UC_LOCK_DISABLE
See Table 2-45.Thread
IA32 Core Capabilities Register (R/W)
This MSR provides an architectural enumeration function for model-specific behavior. Core
0 Reserved: returns zero.
1 Reserved: returns zero.
2 INTEGRITY_CAPABILITIES
When set to 1, the processor supp orts MSR_INTEGRIT Y_CAPABILITIES. 
Indicates that RSM will only be allo wed in CPL0 and will #GP for all non-
CPL0 privilege levels.
When read as 1, software can se t bit 28 of MSR_MEMORY_CTRL (MSR 
address 33H).Vol. 4 2-399MODEL-SPECIFIC REGISTERS (MSRS)
6 Reserved: returns zero.
Indicates that the snoop filter quality of service  MSRs are supported on 
this core. This is based on the existence of a non-inclusive cache and the L2/MLC QoS feature supported.
63:8 Reserved: returns zero.
Register Address: EDH, 237 MSR_RAR_CONTROL
RAR Control (R/W) Thread
63:32 Reserved.31 ENABLE
RAR events are recognized. When RAR is not enabled, RARs are dropped.
30 IGNORE_IF
Allow RAR servicing at the RLP rega rdless of the valu e of RFLAGS.IF.
29:0 Reserved.
Register Address: EEH, 238 MSR_RAR_ACTION_VECTOR_BASE
Pointer to RAR Action Vector (R/W) Thread
MAXPHYADDR-1:6 VECTOR_PHYSICAL_ADDRESS
Pointer to the physical address of the 64B aligned RAR action vector.
5:0 Reserved.
Register Address: EFH, 239 MSR_RAR_PAYLOAD_TABLE_BASE
Pointer to Base of RAR Payload Table (R/W) Thread
MAXPHYADDR-1:12 TABLE_PHYSICAL_ADDRESS
Pointer to the base physical address of the 4K aligned RAR payload table.
Register Address: F0H, 240 MSR_RAR_INFO
Read Only RAR Information (RO) Thread
63:38 Always zero.37:32 Table Max Index
Maximum supported payload table index.
31:0 Supported payload type bitmap. A value of 1 in bit position [i] indicates 
that payload type [i] is supported.
Register Address: 105H, 261 MSR_CORE_BISTTable 2-52.  Additional MSRs  Supported by the 4th and 5th Generation Intel® Xeon® Scalable  Processor Families
(CPUID Signature DisplayFamil y_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Information / Bit Fields Bit Description Scope2-400 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Core BIST (R/W)
Controls Array BIST activation and status checking as part of FUSA.Core
31:0 BIST_ARRAY 
Bitmap indicating which arrays to run BIST on (WRITE).Bitmap indicating which ar rays were not processed, i.e., completion mask 
(READ).
39:32 BANK
Array bank of the [least si gnificant set bit] array in dicated in EAX to start 
BIST(WRITE). 
Array bank interrupte d or failed (READ).
47:40 DWORD
Array dword of the [least significant set bit] arra y indicated in EAX to 
start BIST (WRITE). 
Array dword interrupted or failed (READ).
62:48 Reserved.63 CTRL_RESULT
Indicates whether WRMSR should signal Machine-Check upon BIST-error 
(WRITE).
BIST result PASS(0)/FAIL (1) of the (least sign ificant set bit) array 
indicated in EAX (READ).
Prefetch Disable Bits (R/W)0 L2_HARDWARE_PREFETCHER_DISABLE
code or data into the L2 cache.
1 L2_ADJACENT_CACHE_LIN E_PREFETCHER_DISABLE
line that comprises a cach e line pair (128 bytes).
line into L1 data cache.
whether to prefetch additional lines.
4 Reserved.
5 AMP_PREFETCH_DISABLE

63:6 Reserved.Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Inte l® Xeon® Scalable Processor Families
Register Information / Bit Fields Bit Description ScopeVol. 4 2-401MODEL-SPECIFIC REGISTERS (MSRS)
Primary Maximum Turbo Ratio Limit (R/W)
See Table 2-46.Package
Register Address: 1AEH, 430 MSR_TURBO_RATIO_LIMIT_CORES
See Table 2-50. Package
Extended Feature Detect (R/W)
XFD Error Code (R/W)
Register Address: 2C2H, 706 MSR_COPY_SCAN_HASHES
COPY_SCAN_HASHES (W) Die
63:0 SCAN_HASH_ADDR
Contains the linear address of the SCAN Test HASH Binary loaded into 
memory.
Register Address: 2C3H, 707 MSR_SCAN_HASHES_STATUS
SCAN_HASHES_STATUS (R/O)
15:0 CHUNK_SIZE
Chunk size of the test in KB.Die
23:16 NUM_CHUNKS
Total number of chunks.Die
31:24 Reserved: all zeros.
39:32 ERROR_CODE
The error-code refers to th e LP that runs WRMSR(2C2H).
0x0: No error reported.
0x1: Attempt to copy scan-hashes when copy already in progress.
0x2: Secure Memory not set up correctly.
0x3: Scan-image header Image_info.ProgramID doesn't match 
RDMSR(2D9H)[31:24], or scan-image header Processor-Signature doesn't match F/M/S, or scan-image header Processor-Flags doesn't match 
PlatformID.
0x4: Reserved0x5: Integrity check failed.
0x6: Re-install of scan test image attempted when cu rrent scan test 
image is in use by other LPs.Thread
50:40 Reserved: se t to all zeros.
62:51 MAX_CORE_LIMIT
Maximum Number of cores that can run Intel® In-field Scan simultaneously 
minus 1.
0 means 1 core at a time.DieTable 2-52.  Additional MSRs  Supported by the 4th and 5th Generation Intel® Xeon® Scalable  Processor Families
Register Information / Bit Fields Bit Description Scope2-402 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
63 Valid
Valid bit is set when COPY_SCAN_HA SHES has completed successfully.Die
Register Address: 2C4H, 708 MSR_AUTHENTICATE _AND_COPY_CHUNK
AUTHENTICATE_AND _COPY_CHUNK (W) Die
7:0 CHUNK_INDEX
Chunk Index, should be less than th e total number of chunks defined by 
NUM_CHUNKS (MSR_SCAN_HASHES_STATUS[23:16]).
63:8 CHUNK_ADDR
Bits 63:8 of 256B aligned Linear address of scan chunk in memory.
Register Address: 2C5H, 709 MSR_CHUNKS_AUTHENTICATION_STATUS
CHUNKS_AUTHENTICATION_STATUS (R/O)
7:0 VALID_CHUNKS
Total number of Valid (authenticated) chunks.Die
15:8 TOTAL_CHUNKS
31:16 Reserved: all zeros.
The error code refers to th e LP that runs WRMSR(2C4H).
0x1: Attempt to authen ticate a CHUNK which is already marked as 
authentic or is curre ntly being installe d by another core.
0x2: CHUNK authentication  error. HASH of chunk did not match expected 
value.Thread
63:40 Reserved: se t to all zeros.
Register Address: 2C6H, 710 MSR_ACTIVATE_SCAN
ACTIVATE_SCAN (W) Thread
7:0 CHUNK_START_INDEX
Indicates chunk index to start from.
15:8 CHUNK_STOP_INDEX
Indicates what chunk index to stop at (inclusive).
62:32 THREAD_WAIT_DELAY
TSC based delay to allow threads to rendezvous.
63 SIGNAL_MCE
If 1, then on scan-error log MC in MC4_STATUS and signal MCE if machine 
check signaling enabled in MC4_CTL[0]. 
If 0, then no logging/no signaling.
Register Address: 2C7H, 711 MSR_SCAN_STATUS
SCAN_STATUS (R/O)Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Inte l® Xeon® Scalable Processor Families
Register Information / Bit Fields Bit Description ScopeVol. 4 2-403MODEL-SPECIFIC REGISTERS (MSRS)
7:0 CHUNK_NUM
SCAN Chunk that was reached.Core
Indicates what chunk index to stop at (inclusive). Maps to same field in 
WRMSR(ACTIVATE_SCAN).Core
31:16 Reserved: return all zeros.
0x0: No error.0x1: SCAN operation did not start. Other thread did not join in time.
0x2: SCAN operation did not start. Interrupt occurred prior to threads 
rendezvous.
0x3: SCAN operation did not start. Power Management conditions are 
inadequate to run In tel In-field Scan.
0x4: SCAN operation did not start. Non-valid chunks in the range 
CHUNK_STOP_INDEX : CHUNK_START_INDEX.
0x5: SCAN operation did not start. Mismatch in arguments between 
threads T0/T1.
0x6: SCAN operation did not start. Core not capable of performing SCAN 
currently.
0x8: SCAN operation did not star t. Exceeded number of Logical 
Processors (LP) allowed to run In tel In-field Scan concurrently. 
MAX_CORE_LIMIT exceeded.
0x9: Interrupt occurred. Scan operation aborted prematurely, not all 
chunks requested have been executed.Thread
61:40 Reserved: return all zeros.
62 SCAN_CONTROL_ERROR
Scan-System-Controller malfunction.Core
63 SCAN_SIGNATURE_ERROR
Core failed SCAN-SIGNATURE checking for this chunk. Core
Register Address: 2C8H, 712 MSR_SCAN_MODULE_ID
SCAN_MODULE_ID (R/O) Module
31:0 RevID of the currently installed scan test image. Maps to Revision field in 
external header (offset 4).
63:32 Reserved: return all zeros.
Register Address: 2C9H, 713 MSR_LAST_SAF_WP
LAST_SAF_WP (R/O) Core
31:0 LAST_WP
Provides information about the core when the last 
WRMSR(ACTIVATE_SCAN) was executed. Available only if enumerated in MSR_INTEGRITY_CAPABILITIES[10:9].
Register Address: 2D9H, 729 MSR_INTEGRITY_CAPABILITIESTable 2-52.  Additional MSRs  Supported by the 4th and 5th Generation Intel® Xeon® Scalable  Processor Families
Register Information / Bit Fields Bit Description Scope2-404 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
INTEGRITY_CAPABILITIES (R/O) Module
0S T A R T U P _ S C A N _ B I S T
When set, supports Intel In-field Scan.
3:1 Reserved: return all zeros.
4 PERIODIC_SCAN_BIST
23:5 Reserved: return all zeros.31:24 ID of the scan programs supporte d for this part. WRMSR(2C2H) verifies 
this value against the corresponding value in the scan-image header, i.e., 
Image_info.
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.Package
See Table 2-2. 
Thread Microarchitectural Control (R/W)
See Table 2-47.Thread
Register Address: 64DH, 1613 MSR_PLATFORM_ENERGY_STATUS
Platform Energy Status (R/O) Package
31:0 TOTAL_ENERGY_CONSUMED
Total energy consumption in J (32.0), in 10nsec units. Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Inte l® Xeon® Scalable Processor Families
Register Information / Bit Fields Bit Description ScopeVol. 4 2-405MODEL-SPECIFIC REGISTERS (MSRS)
63:32 TIME_STAMP
Time stamp (U32.0).
Platform Power Limit Control (R/W-L) Package
16:0 POWER_LIMIT_1
The average power limit value that the platform must not exceed over a 
time window as specified by the Power_Limit_1_TIME field.
product skus. The unit is specified in MSR_RAPL_POWER_UNIT.
17 POWER_LIMIT_1_EN
When set, the processor ca n apply control policies such that the platform

When set, the processor ca n apply control policies such that the platform 
average power does not exceed the Power_Limit_1 value over an exponential weighted moving average of the time window. 
18 CRITICAL_POWER_CLAMP_1
When set, the processor can go below the OS-requested P States to 
maintain the power below the specified Power_Limit_1 value.
25:19 POWER_LIMIT_1_TIME
This indicates the time  window over which the Power_Limit_1 value 
should be maintained. 
This field is made up of two numbers from the following equation:
Time Window = (float) (( 1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in 
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, and the unit is specified in 
48:32 POWER_LIMIT_2
This is the Duration Power limit valu e that the platform must not exceed.
The unit is specified in MSR_RAPL_POWER_UNIT.
49 Enable Platform Power Limit #2
platform power does not exceed Platform Power limit #2 over the Short Duration ti me window.
50 Platform Clamping Limitation #2
When set, allows the processor to go below the OS requested P states in 
order to maintain the power below specified Platform Power Limit #2 
value. 
57:51 POWER_LIMIT_2_TIME
This indicates the time  window over which the Power_Limit_2 value 
should be maintained.
This field has the same format as the POWER_LIMIT_1_TIME field.Table 2-52.  Additional MSRs  Supported by the 4th and 5th Generation Intel® Xeon® Scalable  Processor Families
Register Information / Bit Fields Bit Description Scope2-406 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
62:58 Reserved.
63 LOCK 
Setting this bit will lock all other bi ts of this MSR until system RESET.
Register Address: 665H, 1637 MSR_PLATFORM_POWER_INFO
Platform Power Information (R/W) Package
16:0 MAX_PPL1
Maximum PP L1 value. The unit is specified in MSR_RAPL_POWER_UNIT.
31:17 MIN_PPL1
Minimum PP L1 value.
48:32 MAX_PPL2
Maximum PP L2 value.The unit is specified in MSR_RAPL_POWER_UNIT.
55:49 MAX_TW
Maximum time window.
63 LOCK 
Register Address: 666H, 1638 MSR_PLATFORM_RAPL_SOCKET_PERF_STATUS
Platform RAPL Socket Performance Status (R/O) Package
31:0 Count of limited performanc e due to platform RAPL limit.
Configure User Mode CET (R/W)
Register Address: 6A7H, 1703 IA32_PL3_SSPTable 2-52.  Additional MSRs Supported by the 4th and 5th Generation Inte l® Xeon® Scalable Processor Families
Register Information / Bit Fields Bit Description ScopeVol. 4 2-407MODEL-SPECIFIC REGISTERS (MSRS)
Register Addres s: 6A8H, 1704 IA32_INTERRUPT_SSP_TABLE_ADDR
Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using the IST index (when 
not 0) from the interrupt  gate descriptor. (R/W)
User Interrupt Request Register (R/W)
User Interrupt Hand ler Address (R/W)
User Interrupt Stack Adjustment (R/W)
User-Interrupt Target-Table Size and Notification Vector (R/W)
User Interrupt PID Address (R/W)
User-Interrupt Target Table (R/W)
Uncore B-box 1 perfmon event select MSR. PackageTable 2-52.  Additional MSRs  Supported by the 4th and 5th Generation Intel® Xeon® Scalable  Processor Families
Register Information / Bit Fields Bit Description Scope2-408 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: C73H, 3187 MSR_B1_PMON_CTR1
Uncore B-box 1vperfmo n event select MSR. Package
Register Address: C90H −C9EH, 3216 −
3230IA32_L3_QOS_MASK_0 through IA32_L3_QOS_MASK_14
Register Address: D10H −D17H, 3344 −
3351IA32_L2_QOS_MASK_[0-7]
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] ≥ 0. See Table 2-2.Core
Register Address: 1200H −121FH, 4608 −
4639IA32_LBR_x_INFO
Register Address: 1406H, 5126 IA32_MCU_CONTROL
Register Address: 1500H −151FH, 5376 −
5407IA32_LBR_x_FROM_IP
Last Branch Record  Entry X Source IP Register (R/W)
See Table 2-2.Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Inte l® Xeon® Scalable Processor Families
Register Information / Bit Fields Bit Description ScopeVol. 4 2-409MODEL-SPECIFIC REGISTERS (MSRS)
2.17.9  MSRs Introduced in the Intel® Core™ Ultra 7 Processor Supporting Performance Hybrid 
Table 2-53 lists additional MSRs for the Intel Core Ultra 7 processor with a CPUID Signature DisplayFamily_Display-
Model value of 06_AAH. Table 2-54 lists the MSRs unique to  the processor P-core. Table 2-55 lists the MSRs unique 
to the processor E-core. Register Address: 1600H −161FH, 5632 −
5663IA32_LBR_x_TO_IP
Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Architecture 
26:0 Reserved.
27 UC_STORE_THROTTLE
If set to 1, a UC lock will cause a #GP(0) exception.
Implements Feature Activation  command. WRMSR to this address activates all 'activatable' features on this thread.
MSR_TRACE_HUB_STH_ACPIBAR_BASE (R/W)
This register is used by BIOS to program Trace Hub STH base address that will be used by AET messages.Thread
0L O C K
Lock bit. If set, this  MSR cannot be re-writt en anymore. The lock

0L O C K
Lock bit. If set, this  MSR cannot be re-writt en anymore. The lock 
bit has to be set in order for the AET packets to be directed to 
Trace Hub MMIO.
17:1 Reserved.Table 2-52.  Additional MSRs  Supported by the 4th and 5th Generation Intel® Xeon® Scalable  Processor Families
Register Information / Bit Fields Bit Description Scope2-410 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
45:18 ADDRESS
AET target address in Trace Hub MMIO space.
C-State Configuration (R/W) Core
3:0 PKG_C_STATE_LIMIT
(consuming the least po wer) for the package.
The default is set as factory-configured package C-state limit.
The following C-state code name encodings may be supported:
0000b: C0/C1 (no package C-state support)
0001b: C20010b: C3
0011b: C6
0100b: C70101b: C7s
0110b: C8
7:4 MAX_CORE_C_STATE
Possible values are: 0000
−reserved; 0001 −C1; 0010 −C3, 
0011−C6.
9:8 Reserved.
10 IO_MWAIT_RED IRECTION_ENABLE
When set, will map IO_read instru ctions sent to IO registers 
PMG_IO_BASE_ADDR.PMB0+0/1/2 to  MWAIT(C2,3,4) instructions; 
applies to deepc4 too.
15 CFG_LOCK
When set, locks bits 15 :0 of this register for further writes, until 
the next reset occurs.
25 C3_STATE_AUTO_ DEMOTION_ENABLE
When set, processor will conditio nally demote C6/C7 requests to 
C3 based on uncore auto-demote information.
26 C1_STATE_AUTO_ DEMOTION_ENABLE
When set, processor will conditio nally demote C3/C6/C7 requests 
to C1 based on uncore auto-demote information.
27 ENABLE_C3_UNDEMOTION
Enable Un-Demotion from Demoted C3.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Architecture  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-411MODEL-SPECIFIC REGISTERS (MSRS)
28 ENABLE_C1_UNDEMOTION
Enable Un-Demotion from Demoted C1.
29 ENABLE_PKGC_AUTODEMOTION
Enable Package C-State Auto-Demotion. It enables use of the 
history of past package C-state depth and residence, as a factor in 
determining C-State depth.
30 ENABLE_PKGC_UNDEMOTION
Enable Package C-State Un-Demotion. It enables considering 
cases where demotion was the inco rrect decision in determining 
C-State depth.
31 TIMED_MWAIT_ENABLE
When set, enables Timed MWAIT feature. MWAIT would #GP on 
attempts to do setup MWAIT ti mer if this bit is not set.
Register Address: E4H, 228 MSR_IO_CAPTURE_BASE
IO Capture Base (R/W)
Power Management IO Redirection in C-state. See http://biosbits.org.Core
15:0 LVL_2_BASE_ADDRESS
Specifies the base address visible to  software for IO redirection. If 
MSR_PKG_CST_CONFIG_CONTROL .IO_MWAIT_REDIRECTION_ENA
BLE, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO 
port address redirection is enabled, this is the IO port address 
reported to the OS/software.
18:16 CST_RANGE
Specifies the encoding value of the maximum C-State code name 
to be included when IO read to  MWAIT redirection is enabled by 
BLE:
000b
−C3 is the max C-State to include.
001b−C6 is the max C-State to include.
010b−C7 is the max C-State to include.
AES Feature Configuration (R/W) Core
0A E S N I _ L O C K
Once this bit is set, writes to this register wi ll not be allowed.
1A E S N I _ D I S A B L E
This bit disables Advanced Encryption Standard feature on this 
processor core. To disable AES, BIOS will write '11 to this MSR on 
every core.
Register Address: 140H, 320 MSR_FEATURE_ENABLESTable 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-412 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Feature Enable (R/W)
Miscellaneous enables for thread specific features.Thread
0 CPUID_GP_ON_CPL_GT_0
Causes CPUID to #GP if CPL gr eater than 0 and not in SMM.
Temperature Target (R/W)
Legacy register holding temperature related constants for Platform use.Package
6:0 TCC Offset Time Window
Describes the RATL averaging time window.
7 TCC Offset Clamping Bit
When enabled will allow RATL throttling below P1.
15:8 Temperature Control Offset
Fan Temperature Target Offset (a.k.a. T-Control) indicates the 
relative offset from the Therma l Monitor Trip Temperature at 
which fans should be engaged. 
23:16 TCC Activation Temperature
The minimum temperature at whic h PROCHOT# will be asserted. 
The value is degrees C.
30:24 TCC Activation Offset
Specifies a temperature offset in degrees C from the temperature 
target (bits 23:16). PROCHOT# will assert at the offset target temperature. Write is permitted only if 
MSR_PLATFORM_INFO[30] is set.
31 LOCKED
When set, this entire re gister becomes read-only.
PREFETCH Control (R/W)
Prefetch disable bits.Thread
If 1, disables the L2 hardware prefetcher, which fetches 
additional lines of code or  data into the L2 cache.
cache line into L1 data cache.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-413MODEL-SPECIFIC REGISTERS (MSRS)
If 1, disables the L1 data cache IP prefetcher, which uses 
sequential load history (based on instruction pointer of previous 
loads) to determine whether to  prefetch additional lines.
4 DCU_NEXT_PAGE_P REFETCH_DISABLE
If 1, disables Next Page prefetcher.
5A M P _ P R E F E T C H _ D I S A B L E
If 1, disables L2 Adaptive Multipath Probability (AMP) prefetcher.
6 LLC_PAGE_PREFETCH_DISABLE
If 1, disables the LLC Page prefetcher.
7A O P _ P R E F E T C H _ D I S A B L E
8 STREAM_PREFETCH_CODE_FETCH_DISABLE
OFFCORE_RSP_0 (R/W)
Offcore Response Ev ent Select RegisterThread
0 TRUE_DEMAND_CACHE_LOAD
Demand Data Rd = DCU reads (inclu des partials) that is not tagged 
homeless.
1D E M A N D _ R F O
Demand Instruction fetch = IFU Fetc hes. ItoM or RFO that is not 
tagged homeless. 
2 DEMAND_CODE_READ
Demand Instruction fetch = IFU Fetches. CRd or CRd_UC.
3 CORE_MODIFIED_WRITEBACK
WBMtoI or WBMtoE.
4 HW_PREFETCH_MLC_LOAD
L2 prefetcher requests triggered by reads from MEC (except 
those triggered by I-side).
5 HW_PREFETCH_MLC_RFO
L2 prefetcher requests triggered by RFOs.
6 HW_PREFETCH_MLC_CODE
L2 prefetcher requests triggered by I-side requests.
7 HW_PREFETCH _LLC_LOAD
LLC prefetch requests triggered by DRd.
8 HW_PREFETCH_LLC_RFO
LLC prefetch requests triggered by RFO.
9 HW_PREFETCH_LLC_CODE
LLC prefetch requests triggered by CRd.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-414 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
10 L1_HWPREFETCH
Covers Hardware PFRFO, PFNEAR,  PFMED, PFFAR, PFHW, PFNTA, 
PFNPP, PFIPP including the homeless versions.
11 ALL_STREAMING_STORE
Write Combining. WCiL or WCiLF.
12 CORE_NON_MODIFIED_WB
WBEFtoI or WBEFtoE.
13 LLC_PREFETCH
LLC prefetch of load/code/RFO.
14 L1_SWPREFETCH
Covers Software PFRF O, PFNEAR, PFMED, PF FAR, PFHW, PFNTA, 
15 OTHER
Includes CLFlush, CLFlushOPT, CLDemote, CLWB, Enqueue 
SetMonitor, PortIn, IntA, Lock, Spli tLock, Unlock, SpCyc, ClrMonitor, 
PortOut, IntPriUp, IntLog, IntPhy, EOI, RdCurr, WbStoI, LLCWBInv, 
LLCInv, NOP, PCOMMIT.
16 ANY_RESP
Match on any response.
17 SUPPLIER_NONE
No Supplier Details.  DATA_PRE [6:3] = 0.
18 LLC_HIT_M_STATE
LLC/L3, M-state, DATA_PRE [6:3] = 2.
19 LLC_HIT_E_STATE
LLC/L3, E-state, DATA_PRE [6:3] = 4.
20 LLC_HIT_S_STATE
LLC/L3, S-state, DATA_PRE [6:3] = 6.
21 LLC_HIT_F_STATE
LLC/L3, F-state, DATA_PRE [6:3] = 8.
22 FAR_MEM_LOCAL
Far Memory, Local, DATA_PRE [6:3] = 1.
23 FAR_MEM_REMOTE_0_HOP
Far Memory, Remote 0-hop, DATA_PRE [6:3] = 3.
24 FAR_MEM_REMOTE_1_HOP
Far Memory, Remote 1-hop, DATA_PRE [6:3] = 5.
25 FAR_MEM_REMOTE_2_PLUS_HOP
Far Memory, Rem 2+ hop, DATA_PRE [6:3] = 7.
26 NEAR_MEM_MISS_LOCAL_NODE
LLC Miss Local Node. Near Memo ry, Local DATA_PRE [6:3] = E.

15 OTHER
27 NEAR_MEM_REMOTE_0_HOP
Near Memory, Remote 0-hop, DATA_PRE [6:3] = BTable 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-415MODEL-SPECIFIC REGISTERS (MSRS)
28 NEAR_MEM_REMOTE_1_HOP
Near Memory, Remote 1-hop, DATA_PRE [6:3] = D.
29 NEAR_MEM_REMOTE_2_PLUS_HOP
Near Memory, Remote 2+ hop, DATA_PRE [6:3] = F.
30 SPL_HIT
Snoop Info: SPL-hit, DATA_PRE [2:0] = 6.
31 SNOOP_NONE
No details as to Snoo p-related info. Snoop Info: None, DATA_PRE 
[2:0] = 0.
32 NOT_NEEDED
No snoop was needed to satisf y the request. Snoop Info: Not 
needed, DATA_PRE [2:0] = 1.
33 MISS
No snoop was needed to satisfy the request. Snoop Info: Miss, 
DATA_PRE [2:0] = 2.
34 HIT_NO_FWD
A snoop was needed and it Hits in at least one snooped cache. Hit 
denotes a cache-line was valid be fore snoop effect. Snoop Info: 
Hit No Fwd, DATA_PRE [2:0] = 3.
35 HIT_EF_WITH_FWD
A snoop was needed and data was Forwarded from a remote 
socket. Snoop Info: Hit EF w/Fwd, DATA_PRE [2:0] = 4.
36 HITM
A snoop was needed and it HitMed in local or remote cache. HitM 
denotes a cache-line was modified before snoop effect. Snoop 
Info: HitM, DATA_PRE [2:0] = 5.
37 NON_DRAM
Target was non-DRAM system address. Snoop Info: HitM, 
DATA_PRE [2:0] = 5.
38 GO_ERR
GO-ERR, RspData[3:0] = 0100.
39 GO_NO_GO
GO-NoGO, RspData[3:0] = 0111.
40 INPKG_MEM_LOCAL
In-package Memory, Loca l, DATA_PRE [6:3] = 9.
41 INPKG_MEM_NONLOCAL
In-package Memory, Non-Lo cal, DATA_PRE [6:3] = C.
43:42 Reserved.44 UC_LOAD
PRd or UCRdF.
45 UC_STORE
WiL.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-416 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
46 PARTIAL_STREAMING_STORES
WCiL.
47 FULL_STREAMING_STORES
WCiLF.
48 L1_MODIFIED_WB
EVICTION EXTTYPE from MEC.
49 L2_MODIFIED_WB
50 PSMI
MemPushWr_NS (PSMI only).
51 ITOM
ItoM.
OFFCORE_RSP_1 (R/W)
Offcore Response Event Select Register. See MSR_OFFCORE_RSP_0 (at1A6H).Thread
Miscellaneous Power Management Control (R/W)
Various model-specific features enumeration. See http://biosbits.org.Package
1 ENABLE_HWP_VOTING_RIGHT
When set (1), The CPU will take in to account thread HWP requests 
for threads that have voting rights  only (ignores thread requests 
if they do not have voting rights). When reset(0), The CPU will 
take into account all thread HWP requests, even for threads that 
don't have voting righ ts. Setting this bit wi ll cause the HWP Base 
feature bit to be reported in CPUID as present; clearing will cause 
it to be reported as non-present.
5:2 Reserved.
6 ENABLE_HWP
Setting this bit will cause the HWP Base feature bit to report as 
present in CPUID; clearing this bit will cause CPUID to report the 
feature as non-present.
7 ENABLE_HWP_INTERRUPT
Setting this bit will cause the HWP Interrupt feature 
CPUID[6].EAX[8] bit to report as present; clearing will report as 
non-present.
8 ENABLE_OUT_OF_BAND_AUTONOMOUS
Setting this bit will cause the HWP Autonomous feature bit to 
report as present; clearing will report as non-present.
11:9 Reserved.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-417MODEL-SPECIFIC REGISTERS (MSRS)
12 ENABLE_HWP_EPP
Enable HWP EPP. Setting this  bit (1) will cause the HWP 
CPUID[6].EAX[10] Energy Performance Preference bit to report 
as present (1); clearing wi ll report as non-present (0).
13 LOCK
Setting this bit will prevent the BI OS specific bits from changing 
until the next reset. i.e., only Bi ts [0,22] which are meant for OS 
use can be changed once the LOCK bit is set.
63:14 Reserved.
Crash Log Control (R/W)
Write data to a Crash Log configuration.Thread
0 CDDIS
CrashDump_Disable: If set, indica tes that Crash Du mp is disabled.
1E N _ G P R S
Collect GPRs on a crash dump. On ly meaningful when CDDIS is 
zero.
2E N _ G P R S _ I N _ S M M
Collect GPRs in SMM on a cras h dump. Only meaningful when 
CDDIS is zero. EN_GPRS wi ll override this control,Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-418 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
3 TRIPLE_FAULT_SHUTDOWN
Collect a crash log on a triple fault shutdo wn. Only meaningful 
when CDDIS is zero.
Processor Reserved Memory Range Re gister - Physical Mask (R/W) Core
9:0 Reserved.10 LOCK
Once set, this bit prevents so ftware from modifying the PRMRR.
11 VALID
This bit serves as the enable for the PRMRR; the PRMRR must be 
LOCKed before it can be enabled.
19:12 Reserved.
45:20 MASK
PRMRR Address Mask.
Power Control Register (R/W)
See http://biosbits.org.Package
0 ENABLE_BIDIR_PROCHOT
Used to enable or disable the response to PROCHOT# input.
When set/enabled, the platform can force the CPU to throttle to a 
lower power condition such as Pn/Pm by asserting prochot#. 
When clear/disabled (default), the CPU ignores the status of the 
prochot input signal.
1C 1 E _ E N A B L E
When set to '1', will enable th e CPU to switch to the Minimum 
Enhanced Intel SpeedStep Techno logy operating point when all 
execution cores enter MWAIT (C1).
2 SAPM_IMC_C2_POLICY
This bit determines if self-refresh activation is allowed when 
entering Package C2 Stat e. If it is set to 0b, PCODE will keep the 
FORCE_SR_OFF bit asserted in Package C2 State and allow its 
negation according to the defined latency ne gotiations with the 
PCH and Display Engine in Package C3 and deeper states. Otherwise, self-refresh is allowed in Package C2 State.
3F A S T _ B R K _ S N P _ E N
This bit controls the VID swin g rate for the OTHER_SNP_WAKE 
events that are detected by the iMPH. This is the event that is 
detected by the iMPH when a non-DMI snoopable request is observed while UCLK domain is not functional.
0b: Use slow VID swing rate.
1b: Use fast VID swing rate.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-419MODEL-SPECIFIC REGISTERS (MSRS)
17:4 Reserved.
18 PWR_PERF_PLTFRM_OVR
Power performance platform override.
19 EE_TURBO_DISABLE
Setting this bit disa bles the P-States energy efficiency 
optimization. Default value is 0. Disable/enable the energy 
efficiency optimization in P-State legacy mode (when 
IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the 
turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an 
effect between the OS desired or OS maximize to the OS minimize 
performance setting.
20 RTH_DISABLE
Setting this bit disables  the Race to Halt op timization and avoids 
this optimization limi tation to execute below the most efficient 
frequency ratio. Default value is 0 for processors that support Race to Halt optimization.
21 DIS_PROCHOT_OUT
Prochot output disable.
22 PROCHOT_RESPONSE
Prochhot configurable response enable.
23 VR_THERM_ALERT _DISABLE_LOCK
When set to 1, locks PROCHOT relate d bits of this MSR. Once set, 
a reset is required to clear this bit.
24 VR_THERM_A LERT_DISABLE
When set to 1, disables the VR_THERMAL_ALERT signaling.
25 DISABLE_RING_EE
Disable Ring EE.
26 DISABLE_SA_OPTIMIZATION
Disable SA optimization.
27 DISABLE_OOK
Disable OOK.
28 DISABLE_AUTONOMOUS
Disable HWP autonomous mode.

29 Reserved.
30 CSTATE_PREWAKE_DISABLE
C-state pre-wake disable.
2:0 MEMTYPE
Memory type for PRMRR accesses.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-420 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
3C O N F I G U R E D
PRMRR base configured.
19:4 Reserved.
45:20 BASE
PRMRR base address.
MC29_CTL. See Table 2-2. Package
MC29_STATUS. See Table 2-2. Package
MC29_ADDR. See Table 2-2. Package
MC29_MISC. See Table 2-2. Package
MC30_CTL. See Table 2-2. Package
MC30_STATUS. See Table 2-2. Package
MC30_ADDR. See Table 2-2. Package
MC30_MISC. See Table 2-2. Package
MC31_CTL. See Table 2-2. Package
MC31_STATUS. See Table 2-2. Package
MC31_ADDR. See Table 2-2. Package
MC31_MISC. See Table 2-2. Package
Enhanced SMM Feature Control (R/W)
Reports SMM capability enhancement.Package
0L O C K
When set, locks this regi ster from further changes.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-421MODEL-SPECIFIC REGISTERS (MSRS)
1 SMM_CPU_SAVE_EN
If 0, SMI/RSM will save/r estore state in SMRAM
If 1, SMI/RSM will save/r estore state from SRAM.
2 SMM_CODE_CHK_EN
When clear (default) none of the logical processors are prevented 
from executing SMM code outside the ranges defined by the 
SMRR. When set, any logical processor in the package that attempts to execute SMM code no t within the ranges defined by 
the SMRR will assert an unrecoverable MCE.
Register Address: 601H, 1537 MSR_VR_CURRE NT_CONFIG
Power Limit 4 (PL4) (R/W)
15:0 CURRENT_LIMIT
PL4 Value in 0.125 A increments. This field is locked by 
MSR_VR_CURRENT_C ONFIG.LOCK. When the LO CK bit is set to 1, 
this field becomes Read Only.
31 LOCK
This bit will lock the CURRENT_LIMIT settings in  this register and 
will also lock this setting. This means that once set to 1, the 
CURRENT_LIMIT setting and this bit become Read Only until the 
next Warm Reset.
Min/Max Ratio Limits for Uncore LLC and Ring.Package
6:0 MAX_CLR_RATIO
Maximum allowed ratio for the Ring and Last Level Cache (LLC).
14:8 MIN_CLR_RATIO
Minimum allowed ratio for the Ring and Last Level Cache (LLC).
MSR_PP0_POWER_LIMIT (R/W)
PP0 RAPL power unit control.Package
14:0 IA_PP_PWR_LIM
This is the power li mitation on the IA  cores power plane.
The unit of measurement is defined in 
PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-422 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
15 PWR_LIM_CTRL_EN
This bit must be set in order to  limit the power of the IA cores 
power plane.
0b: IA cores power plane powe r limitation is disabled.
1b: IA cores power plane power limitation is enabled.
16 PP_CLAMP_LIM
Power Plane Clamping limita tion; allow going below P1.
0b: PBM is limited between P1 and P0.
1b: PBM can go below P1.
23:17 CTRL_TIME_WIN
x = CTRL_TIME_WIN[23:22]y = CTRL_TIME_WIN[21:17]
The timing interval window is Floating Point number given by 1.x 
* power(2,y).
PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT].
The maximal time window is bounded by 
PACKAGE_POWER_SKU_ MSR[PKG_MAX_WIN]. The minimum time 
window is 1 unit of measurement (as defined above).
30:24 Reserved.
31 PP_PWR_LIM_LOCK
When set, all settings in this register are locked and are treated as 
Read Only.
Core Performance Limit Reasons 
Indicator of Frequency Clipping in Processor Cores. (Frequency refers to processor core frequency.)Package
0P R O C H O T  ( R / O )
PROCHOT Status. When set, frequency is reduced below the 
operating system request due to assertion of external PROCHOT.
1 THERMAL (R/O)
Thermal Status. When set, frequency is reduced below the 
operating system request due to a thermal event.
4 RSR_LIMIT (R/O)
Residency State Regulation Status. When set, frequency is 
reduced below the operating system request due to residency 
state regulation limit.
5 RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is 
reduced below the operating system request due to Running 
Average Thermal Limit (RATL).Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-423MODEL-SPECIFIC REGISTERS (MSRS)
6 VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced below the 
operating system request due to a thermal alert from a processor 
Voltage Regulator (VR).
7V R _ T D C  ( R / O )
VR Therm Design Current Status. When set, frequency is reduced 
below the operating system request due to VR thermal design current limit.
8O T H E R  ( R / O )
Other Status. When set, frequency is reduced below the operating 
system request due to electrical or other constraints.
10 PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set, 
frequency is reduced below the operating system request due to package/platform-level power limiting PL1.
11 PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set, 
frequency is reduced below the operating system request due to 
package/platform-level power limiting PL2/PL3.
12 MAX_TURBO_LIMIT (R/O)
Max Turbo Limit Status. When set, frequency is reduced below 
the operating system request due to multi-core turbo limits.
13 TURBO_ATTEN (R/O)
Turbo Transition Attenuation Status. When set, frequency is 
reduced below the operating system request due to Turbo 
transition attenuation. This prevents performance degradation due to frequent operating ratio changes.
15:14 Reserved.16 PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicate s that the PROCHOT Status bit 
has asserted since the log bit was last cleared. This log bit will 
remain set until cleared by software writing 0.
17 THERMAL_LOG (R/W)
Thermal Log When set, indicates that the Thermal Status bit has 
asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
19:18 Reserved.20 RSR_LIMIT_LOG (R/W)
Residency State Regulation Log. When set, indi cates that the 
Residency State Regulation Status  bit has asserted since the log 
bit was last cleared. This log bi t will remain set until cleared by 
software writing 0.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-424 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
21 RATL_LOG (R/W)
Running average thermal limit Log, RW, When set by PCODE 
indicates that Running averag e thermal limit has cause IA 
frequency clipping. Software should  write to this bit to clear the 
status in this bit.
22 VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert 
Status bit has asserted since the log bit was last cleared. This log 
bit will remain set until clea red by software writing 0.
23 VR_TDC_LOG (R/W)
VR Thermal Design Current Log. Wh en set, indicates that the VR 
TDC Status bit has asserted since the log bit was last cleared. This 
log bit will remain set until cl eared by software writing 0.
24 OTHER_LOG (R/W)
Other Log. When set, indicates that the Other Status bit has 
asserted since the log bit was last cleared. This log bit will remain 
set until cleared by software writing 0.
25 Reserved.26 PBM_PL1_LOG (R/W)

Package/Platform-Level PL1 Power Limiting Log. When set, 
indicates that the Package or Platform Level PL1 Power Limiting 
27 PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set, 
indicates that the Package or Platform Level PL2/PL3 Power 
Limiting Status bit has asserted si nce the log bit was last cleared. 
28 MAX_TURBO_LIMIT_LOG (R/W)
Max Turbo Limit Log. When set, in dicates that the Max Turbo Limit 
29 TURBO_ATTEN_LOG (R/W)
Turbo Transition Attenuation Log.  When set, indi cates that the 
Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bi t will remain set until cleared by 
software writing 0.
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1.Specifies Maximum Ratio Limit for each group. Maximu m ratio for groups with more cores must decrease 
Maximum turbo ratio limi t with 1 core active.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-425MODEL-SPECIFIC REGISTERS (MSRS)
Platform Power Limit Control (R/W)
power consumption is specified via Pl atform_Power_Limit_1 and Platform_Pow er_Limit_1_Time. Th e Short Duration 
power consumption limit is specified via the Platform_Power _Limit_2 with duration chos en by the processor. The 
processor implements an exponential-weighted algorithm in the placement of the time windows.Package
14:0 POWER_LIMIT_1
Average Power limit value which the platform must not exceed 
over a time window as specifie d by Power_Limit_1_TIME field. 
The default value is the Thermal Design Power (a.k.a TDP) and 
varies with product skus. The unit is specified in MSR_RAPLPOWER_UNIT.
15 POWER_LIMIT_1_EN
When set, enables the processor to  apply control policy such that 
the platform power does not exce ed Platform Power limit 1 over 
the time window specified by Power Limit 1 Time Window.
16 CRITICAL_POWER_CLAMP_1
When set, allows the processor to go below the OS requested P 
states in order to maintain the power below specified Platform 
Power Limit 1 value.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-426 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
23:17 POWER_LIMIT_1_TIME
Specifies the duration of the ti me window over which Platform 
Power Limit 1 value should be maintained for sustained long 
duration. This field is made up of two numbers from the following 
equation: 
The default value is 0DH, The unit is specified in 
MSR_RAPLPOWER_UNIT[Time Unit]
46:32 POWER_LIMIT_2
over the Short Duration time window chosen by the processor. 
The recommended default value is 1.25 times the Long Duration Power Limit (i.e., Platform Power Limit 1).
47 POWER_LIMIT_2_EN
the platform power does not exce ed Platform Power limit 2 over 
the Short Duration time window.
48 CRITICAL_POWER_CLAMP_2
states in order to ma intain the power below specified Platform 
Power Limit 2 value.
62:49 Reserved.
63 LOCK
Setting this bit will lock all othe r bits of this MSR until system 
RESET.
Register Address: 6BOH, 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS
MSR_GRAPHICS_PERF_LIMIT_REASONS 
Indicator of Frequency Clipping in the Processor Graphics. (Frequency refers to processor graphics frequency.)Package
PROCHOT Status. When set, frequency is reduced due to 
assertion of external PROCHOT.
Thermal Status. When set, frequency is reduced due to a thermal 
event.
reduced due to running average thermal limit.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-427MODEL-SPECIFIC REGISTERS (MSRS)
VR Therm Alert Status. When set, frequency is reduced due to a 
thermal alert from a proc essor Voltage Regulator.
VR Thermal Design Current Status. When set, frequency is 
reduced due to VR TDC limit.
Other Status. When set, frequency is reduced due to electrical or 
other constraints.
9 Reserved.10 PBM_PL1 (R/O)
frequency is reduced due to package/platform-level power 
frequency is reduced due to package/platform-level power limiting PL2/PL3.
12 INEFFICIENT_OPERATION (R/O)
Inefficient Operation Status. When set, processor graphics 
frequency is operating below target frequency.
16 PROCHOT_LOG (R/W)
Thermal Log. When set, indicates that the Thermal Status bit has 
Running Average Thermal Limit Log. When set, indicates that the 
RATL Status bit has asserted sinc e the log bit was last cleared. 
VR Therm Alert Log. When set, in dicates that the VR Therm Alert 
VR Thermal Design Current Log. Wh en set, indicate s that the VR 
Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software 
writing 0.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-428 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Other Log. When set, indicates that the OTHER Status bit has 
26 PBM_PL1_LOG (R/W)
indicates that the Package/Plat form Level PL1 Power Limiting 
Status bit has asserted since the log bit was last cleared. This log bit will remain set until clea red by software writing 0.
indicates that the Package/Plat form Level PL2 Power Limiting 
28 INEFFICIENT_OPERATION_LOG (R/W)
Inefficient Operation Log. When se t, indicates that  the Inefficient 
Operation Status bit has assert ed since the log bit was last 
cleared. This log bit will remain set until cleared by software 
writing 0.
MSR_RING_PERF_LIMIT_REASONS

writing 0.
Indicator of Frequency Clipping in the Ring Interconnect. (Frequency refers to ring interconnect in the uncore.)Package
event.
reduced due to running average thermal limit.
thermal alert from a processor Voltage Regulator.
other constraints.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-429MODEL-SPECIFIC REGISTERS (MSRS)
frequency is reduced due to package/platform-level power limiting PL1.
15:12 Reserved.16 PROCHOT_LOG (R/W)
20:18 Reserved.21 RATL_LOG (R/W)
Therm Alert Status bit has asserted since the log bit was last 
writing 0.
indicates that the Package/Platform Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log 
bit will remain set until clea red by software writing 0.Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description Scope2-430 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table 2-54 are unique to the Intel Core Ultra 7 processor P-core. These MSRs are not supported 
on the processor E-core.27 PBM_PL2_LOG (R/W)
IA32_TME_CLEAR_SAVED_KEY (R/W)
Register Address: 9FFH, 2559 MSR_CORE_MKTME_ACTIVATE
MSR_CORE_MKTME_ACTIVATE (R/O)
MSR to read TME_ACTIVA TE[MK_TME_KEYID_BITS].Core
35:32 READ_MK_TME_KEYID_BITS
This value will be returned on a RDMSR, but must be zero on a 
WRMSR.
Table 2-54.  MSRs Supported by the In tel® Core™ Ultra 7 Processor P-core 
Fixed-Function Performance Counter 3 (R/W) Thread47:0 FIXED_COUNTER
Top-down Microarchitecture Analysis unhalted number of available 
slots counter.
This register provides built-in support for Top-down Micro- architecture Analysis (TMA) me trics. It exposes the four 
TMA Level 1 metrics where the lower 32 bits are divided into four 8 bit fields, each of wh ich is an integer percentage 
of the total TOPDOWN.SLOTS (as reported by fixed counter 3).Thread
7:0 RETIRING
Percent of utilized by uops th at eventually retire (commit).
15:8 BAD_SPECULATION
Percent of Wasted due to incorrect speculation, covering Utilized by 
uops that do not reti re, or Recovery Bubbles (unutilized slots).Table 2-53.  Additional MSRs  Supported by the Intel® Core™ Ultra 7 Pr ocessors Supporting Performance Hybrid 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-431MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table 2-48 are unique to the Intel Core Ultra 7 processor E-core. These MSRs are not supported 
on the processor P-core.23:16 FRONTEND_BOUND
Percent of Unutilized slots where Front-end did not deliver a uop 
while Back-end is ready.
31:24 BACKEND_BOUND
Percent of Unutilized slots where a uop was not delivered to Back-
end due to lack of Back-end resources.
39:32 MULTI_UOPS
Frontend bound.
47:40 BRANCH_MISPREDICTS
55:48 FRONTEND_LATENCY
63:56 MEMORY_BOUND
Thread Microarchitect ural Control (R/W)
Core Microarchitecture Control MSR (R/W)
Table 2-55.  MSRs Supported by the In tel® Core™ Ultra 7 Processor E-core 
Register Address: 4F0H, 1264 MSR_SAF_CTRL
SAF Control (W/O)
Extension to SAF.Package
0 INVALIDATE_CURRENT_STRIDE
Invalidate all chunks in current stride.
Register Address: D18H −D1FH, 3352 −3359 IA32_L2_MASK_[8-15]
IA32_L2_MASK_[8-15] (R/W)
15:0 WAY_MASK
Capacity Bit Mask. Available ways vectors for class of service of 
IA core. '1 in bit indicates alloca tion to the way is allowed. '0 
indicates allocation to the way is not allowed.Table 2-54.  MSRs Supported by the Intel®  Core™ Ultra 7 Processor P-core  (Contd.)
Register Information / Bit Fields Bit Description Scope2-432 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.18 MSRS IN THE INTEL® XEON PH I™ PROCESSOR 3200/5200/7200 SERIES 
AND THE INTEL® XEON PHI™ PR OCESSOR 7215/7285/7295 SERIES
The Intel® Xeon Phi™ processor 3200, 5200, 7200 series, with a CPUID Signature DisplayFamily_DisplayModel 
value of 06_57H, supports the MSR interfaces listed in Table 2-56. These processors are based on the Knights 
Landing microarchitecture. The Intel® Xeon Phi™ processor 7215, 7285, 7295 series, with a CPUID Signature 
DisplayFamily_DisplayModel value of 06_85H, supports the MSR interfaces listed in Table 2-56 and Table 2-57. 
These processors are based on the Knights Mill microarc hitecture. Some MSRs are shared between a pair of 
processor cores, and the scope is marked as module.31:16 Reserved.
Reload value for IA 32_FIXED_CTRx (R/W) Thread
generated while PE BS_EN_FIXEDx = 1 and PEBS_OUTPUT = 
Register Address: 14C1H −14C8H, 5313 −5320 MSR_RELOAD_PMCx
Reload value for IA32_PMCx (R/W) Thread
47:0 Value loaded into IA32_PMCx when a PEBS record is generated 
Register Address: 1A8EH, 6798 MSR_STLB_FILL_TRANSLATION
STLB Fill Translation (W/O)
STLB QoS MSR to fill translations into STLB.Core
3:0 CLOS
Class of service to use for the fill.
10 X
Set to 1 when LA is to  an executable page.
11 RW
Set to 1 when LA is to a writeable page.
63:12 LA
Logical address to use for fill.
Table 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
DisplayFamily_DisplayModel Va lue of 06_57H or 06_85H 

3:0 CLOS
10 X
11 RW
63:12 LA
Register Address: 0H, 0 IA32_P5_MC_ADDRTable 2-55.  MSRs Supported by the Intel®  Core™ Ultra 7 Processor E-core  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-433MODEL-SPECIFIC REGISTERS (MSRS)
See Section 9.10.5, “Monitor/Mwait Address Range Determination.” See Table 2-2. Thread
31:0 SMI Count (R/O) 63:32 Reserved.
0L o c k .  ( R / W L )  
2 Enable VMX outside SMX operation. (R/WL) 
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIGTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
DisplayFamily_DisplayModel Value of 06_57H or 06_85H  (Contd.)
Register Information / Bit Fields Bit Description Scope2-434 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
This is the ratio of th e frequency that invariant TSC runs at. Frequency 
= ratio * 100 MHz.Package
When set to 1, indicate s that Programmable Ratio Limit for Turbo mode 
is enabled. When set to 0, indicate s Programmable Ratio Limit for Turbo 
When set to 1, indicates that  TDP Limit for Turbo mode is 
programmable. When set to 0, indicates TDP Limit for Turbo mode is 
not programmable.Package
C-State Configuration Control (R/W) PackageTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-435MODEL-SPECIFIC REGISTERS (MSRS)
Specifies the lowest C-state for the package. This feature does not limit 
the processor core C-state. The power-on default value from bit[2:0] of 
this register reports the deepest package C-state the processor is 
capable to support when manufactured. It is recommended that BIOS always read the power-on default valu e reported from this bit field to 
determine the supported deepest C-state on the processor and leave it 
as default withou t changing it.
000b - C0/C1 (No package C-state support)
001b - C2
010b - C6 (non retention)*
011b - C6 (Retention)*
100b - Reserved101b - Reserved
110b - Reserved
111b - No package C-state limit. All C-States supported by the 
processor are available.
Note: C6 retention mode  provides more power saving than C6 non-
retention mode. Limiting the package to C6 non retention mode does prevent the MSR_PKG_C6_RESIDENCY counter (MSR 3F9h) from being 
incremented.
10 I/O MWAIT Redirection Enable (R/W) 
When set, will map IO_read instruct ions sent to IO  registers at 
MSR_PMG_IO_CAPTURE_BASE[15:0] to MWAIT instructions.
15 CFG Lock (R/O) 
When set, locks bits [15: 0] of this register for further writes until the 
next reset occurs.
When set, the processor will condit ionally demote C3/C6/C7 requests 
27 Reserved.
28 C1 State Auto Unde motion Enable (R/W) 
When set, enables Undemo tion from Demoted C1.
29 PKG C-State Auto Demotion Enable (R/W) 
When set, enables Package C state demotion.
Power Management IO Capture Base (R/W) TileTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-436 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Microcode will compar e IO-read zone to this ba se address to determine 
if an MWAIT(C2/3/4) needs to be issued instead of the IO-read. Should 
be programmed to the chip set Plevel_2 IO address.
22:16 C-State Range (R/W) 
The IO-port block size in which IO-redirection will be executed (0-127). 
Should be programmed based on the number of LVLx registers existing in the chipset.
Upon a successful read  of this MSR, the configuration of AES 
instruction set availabi lity is as follows:
Otherwise, AES instructions are available.Note, the AES instruction set is not av ailable if read is unsuccessful. If 
the configuration is not 01b, AES instructions can be mis-configured if a 
Register Address: 140H, 320 MISC_FEATURE_ENABLES
MISC_FEATURE_ENABLES Thread
1 User Mode MONITOR and MWAIT (R/W) 
If set to 1, the MONITOR and MWAIT instructions do not cause invalid-
opcode exceptions when executed with CPL > 0 or in virtual-8086 
mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and 
if EAX indicates a C-state other than C0 or C1, the instruction operates 
as if EAX indicated the C-state C1.
See Table 2-2. ThreadTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-437MODEL-SPECIFIC REGISTERS (MSRS)
31:0 Bank Support (SMM-RO)
One bit per MCA bank. If the bit is set, that bank supports Enhanced 
MCA (Default all 0; do es not support EMCA).
55:32 Reserved.
56 Targeted SMI (SMM-RO)
Set if targeted SMI is supported.
57 SMM_CPU_SVRSTR (SMM-RO)
Set if SMM SRAM save/restore feature is supported.
58 SMM_CODE_ACCESS_CHK (SMM-RO)
Set if SMM code access ch eck feature is supported.
Performance Monitoring Event Select Register (R/W)
7:0 Event Select.
15:8 UMask.
16 USR.17 OS.
18 Edge.
19 PC.20 INT.
21 AnyThread.

18 Edge.
22 EN.23 INV.Table 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-438 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
31:24 CMASK.
1 Thermal Status Log (R/WC0) 2 PROTCHOT # or FORCEPR# Status (R/O) 
4 Critical Temperature Status (R/O) 5 Critical Temperature Status Log (R/WC0) 
7 Thermal Threshold #1 Log (R/WC0) 8 Thermal Threshold #2 Status (R/O) 
10 Power Limitation Status (R/O) 11 Power Limitation Log (RWC0) 
22:16 Digital Readout (R/O) 26:23 Reserved.
31 Reading Valid (R/O) 63:32 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLETable 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-439MODEL-SPECIFIC REGISTERS (MSRS)
Allows a variety of processor func tions to be enabled and disabled.Thread
3 Automatic Thermal Contro l Circuit Enable (R/W) 
10:8 Reserved.11 Branch Trace Storage Unavailable (R/O) 12 Processor Event Based Sa mpling Unavailable (R/O) 
16 Enhanced Intel SpeedStep Technology Enable (R/W) 18 ENABLE MONITOR FSM (R/W) 
22 Limit CPUID Maxval (R/W) 23 xTPR Message Disable (R/W) 
See Table 2-3.
37:35 Reserved.38 Turbo Mode Disable (R/W)
23:16 Temperature Target (R) 29:24 Target Offset (R/W) 
0 DCU Hardware Prefetcher Disable (R/W) 
If 1, disables the L1 data cache prefetcher.Core
1 L2 Hardware Prefetcher Disable (R/W) 
If 1, disables the L2 hardware prefetcher.Core
Offcore Response Event Select Register (R/W) SharedTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-440 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Offcore Response Event Sele ct Register (R/W) Shared
Maximum Ratio Limit of Turbo Mode for Groups of Cores (R/W) Package
7:1 Maximum Number of  Cores in Group 0
Number active processor cores which operates under the maximum 
ratio limit for group 0. Package
15:8 Maximum Ratio Limit for Group 0
Maximum turbo ratio limi t when the number of active cores are not 
more than the group 0 maximum core count. Package
20:16 Number of Incremental Cores Added to Group 1
Group 1, which includes the specified number of additional cores plus 
the cores in group 0, operates under the group 1 turbo max ratio limit = 
“group 0 Max ratio limit” - “group ratio delta for group 1”.Package
23:21 Group Ratio Delta for Group 1
An unsigned integer specifying the ratio decrement rela tive to the Max 
ratio limit to Group 0.Package
28:24 Number of Incremental Cores Added to Group 2
Group 2, which includes the specified number of additional cores plus all 
the cores in group 1, operates under the group 2 turbo max ratio limit = 
“group 1 Max ratio limit” - “group ratio delta for group 2”.Package
31:29 Group Ratio Delta for Group 2
ratio limit for Group 1.Package
36:32 Number of Incremental Cores Added to Group 3
Group 3, which includes the specified number of additional cores plus all 
the cores in group 2, operates under the group 3 turbo max ratio limit = 
“group 2 Max ratio limit” - “group ratio delta for group 3”.Package
39:37 Group Ratio Delta for Group 3
ratio limit for Group 2.Package
44:40 Number of Incremental Cores Added to Group 4
Group 4, which includes the specified number of additional cores plus all 
the cores in group 3, operates under the group 4 turbo max ratio limit = 
“group 3 Max ratio limit” - “group ratio delta for group 4”.Package
47:45 Group Ratio Delta for Group 4
ratio limit for Group 3.Package
52:48 Number of Incremental Cores Added to Group 5
Group 5, which includes the specified number of additional cores plus all 
the cores in group 4, operates under the group 5 turbo max ratio limit = 
“group 4 Max ratio limit” - “group ratio delta for group 5”.PackageTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-441MODEL-SPECIFIC REGISTERS (MSRS)
55:53 Group Ratio Delta for Group 5
ratio limit for Group 4.Package
60:56 Number of Incremental Cores Added to Group 6
Group 6, which includes the specified number of additional cores plus all 
the cores in group 5, operates under the group 6 turbo max ratio limit = 
“group 5 Max ratio limit” - “group ratio delta for group 6”.Package
63:61 Group Ratio Delta for Group 6
ratio limit for Group 5.Package
See Section 18.9.2, “Filtering of Last Branch Records.”Thread
0C P L _ E Q _ 0
2J C C
5 NEAR_RET
6 NEAR_IND_JMP7 NEAR_REL_JMP
See MSR_LASTBRANCH_0_FROM_IP.Thread
Debug Control (R/W) Thread
0L B R
Setting this bit to 1 en ables the processor to re cord a running trace of 
the most recent branches taken by the processor in the LBR stack.Table 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-442 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
1B T F
Setting this bit to 1 en ables the processor to tr eat EFLAGS.TF as single-
step on branches instead of single-step on instructions.
5:2 Reserved.6T R
Setting this bit to 1 enables branch trace messages to be sent.
7B T S
Setting this bit enables branch trace messages (BTMs) to be logged in a 
BTS buffer.
8B T I N T
When clear, BTMs are logged in a BT S buffer in circular fashion. When 
this bit is set, an interrupt is ge nerated by the BTS facility when the 
BTS buffer is full.
9 BTS_OFF_OS
When set, BTS or BTM is skipped if CPL = 0.
10 BTS_OFF_USR
When set, BTS or BTM is skipped if CPL > 0.
11 FREEZE_LBRS_ON_PMI
When set, the LBR stack is  frozen on a PMI request.
12 FREEZE_PERFMON_ON_PMI
When set, each ENABLE bit of the gl obal counter control MSR are frozen 
(address 3BFH) on  a PMI request.
14 FREEZE_WHILE_SMM
When set, freezes perfmon and trace messages while in SMM.
31:15 Reserved.
Last Exception Record fr om Linear IP (R) Thread
Last Exception Record to Linear IP (R) Thread

7B T S
8B T I N T
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1Table 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-443MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. CoreTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-444 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Package
Register Information / Bit Fields Bit Description ScopeVol. 4 2-445MODEL-SPECIFIC REGISTERS (MSRS)
Note: C-state values are processor specific C-state code names, unrelated to  MWAIT extension C-state 
parameters or ACPI C-states.Package
63:0 Package C6 Residency Counter (R/O) Package
63:0 Package C7 Residency Counter (R/O) Package
Register Address: 3FCH, 1020 MSR_MC0_RESIDENCY
parameters or ACPI C-states.Module
63:0 Module C0 Residency Counter (R/O)
Register Address: 3FDH, 1021 MSR_MC6_RESIDENCY
63:0 Module C6 Residency Counter (R/O) Module
Register Address: 3FFH, 1023 MSR_CORE_C6_RESIDENCY
parameters or ACPI C-states.Core
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” CoreTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-446 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection 
exception.Core
Unit Multipliers Used in RAPL Interfaces (R/O) Package3:0 Power Units
1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules).Package
See Section 15.10.1, “RAPL Interfaces.”PackageTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-447MODEL-SPECIFIC REGISTERS (MSRS)

Base TDP Ratio (R/O)
See Table 2-25.PackageTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-448 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
ConfigTDP Level 1 ratio and power level (R/O)
See Table 2-25.Package
ConfigTDP Level 2 ratio and power level (R/O)
ConfigTDP Control (R/W)
Register Address: 64CH, 1612 MSR_TURBO_ACTI VATION_RATIO
1 Thermal Status (R0)5:2 Reserved.
x2APIC Task Priority Register (R/W) Thread
x2APIC Logical Destination Register (R/O) ThreadTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-449MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC Spurious Interrupt Ve ctor Register (R/W) Thread
x2APIC In-Service Register Bits [3 1:0] (R/O) Thread
x2APIC In-Service Register Bits [191:160] (R/O) Thread
x2APIC Trigger Mode Register  Bits [127:96] (R/O) Thread
x2APIC Trigger Mode Register  Bits [159:128] (R/O) Thread
x2APIC Trigger Mode Register  Bits [191:160] (R/O) Thread
x2APIC Trigger Mode Register  Bits [223:192] (R/O) Thread
x2APIC Trigger Mode Register  Bits [255:224] (R/O) Thread
x2APIC Interrupt Request Regist er Bits [31:0] (R/O) Thread
Register Address: 821H, 2081 IA32_X2APIC_IRR1Table 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-450 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC LVT Performance Moni tor Register (R/W) Thread
x2APIC Divide Configurati on Register (R/W) ThreadTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon Phi™ Proc essors with a CPUID Signature 
Register Information / Bit Fields Bit Description ScopeVol. 4 2-451MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57 lists model-specific registers that are supported by the Intel® Xeon Phi™ processor 7215, 7285, 7295 
series based on the Knights Mill microarchitecture.Register Address: 83FH, 2111 IA32_X2APIC_SELF_IPI
See Table 2-2 Thread
Table 2-57.  Additional MSRs Supported by the Inte l® Xeon Phi™ Processor 7215, 7285, 7295 Series 
with a CPUID Signature DisplayFamil y_DisplayModel Value of 06_85H 
SMM Monitor Configuration (R/W)
This MSR is readable only if VMX is en abled, and writeable only if VMX is enabled and in SMM mode, and is used to 
configure the VMX MSEG base address. See Table 2-2.Core
Register Address: 480H, 1152 IA32_VMX_BASICTable 2-56.  Selected MSRs Suppo rted by Intel® Xeon  Phi™ Processors wi th a CPUID Signature 
Register Information / Bit Fields Bit Description Scope2-452 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)

Capability Reporting Register of Primary Proc essor-based VM-execution Controls (R/O) Core
Capability Reporting Register of VM-exit Controls (R/O) 
Capability Reporting Register of VM-entry Controls (R/O) 
Capability Reporting Register of EPT and VPID (R/O)
Register Address: 48DH, 1165 IA32_VMX_TRUE_PINBASED_CTLSTable 2-57.  Additional MSRs Supported by the Inte l® Xeon Phi™ Processor 7215, 7285, 7295 Series 
with a CPUID Signature Disp layFamily_DisplayModel Va lue of 06_85H  (Contd.)
Register Information / Bit Fields Bit Description ScopeVol. 4 2-453MODEL-SPECIFIC REGISTERS (MSRS)
2.19 MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS
Table 2-58 lists MSRs (architectural and model-specific) that are defined across processor generations based on 
Intel NetBurst microarchitecture. The processor can be identified by its CPUID signatures of DisplayFamily 
encoding of 0FH, see Table 2-1.
•MSRs with an “IA32_” prefix are designated as “architect ural.” This means that the functions of these MSRs and 
their addresses remain the same for succeeding families of IA-32 processors.
•MSRs with an “MSR_” prefix are model specific with respect to address functionalities. The column “Model 
Availability” lists the model encoding value(s) within the Pentium 4 and Intel Xeon processor family at the 
specified register address. The model encoding valu e of a processor can be queried using CPUID. See 
“CPUID—CPU Identification” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 2A.Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)
Table 2-58.  MSRs in the Pentium®  4 and Intel® Xeon® Processors 
Register Information / Bit Fields Bit DescriptionModel 
AvailabilityShared/
Unique1
See Section 2.23, “MSRs in Pentium Pr ocessors.” 0, 1, 2, 3, 4, 6 Shared
See Section 2.23, “MSRs in Pentium Pr ocessors.” 0, 1, 2, 3, 4, 6 Shared 
Register Address: 6H, 6 IA32_MONITOR_FILTER_LINE_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination.” 3, 4, 6 Shared
Time Stamp Counter
See Table 2-2.0, 1, 2, 3, 4, 6 UniqueTable 2-57.  Additional MSRs Supported by the Inte l® Xeon Phi™ Processor 7215, 7285, 7295 Series 
Register Information / Bit Fields Bit Description Scope2-454 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
On earlier processors, only the lower 32 bits are wr itable. On any write to th e lower 32 bits, the upper 
32 bits are cleared. For processor family 0FH, models 3 and 4: all 64 bits are writable.
See Table 2-2.The operating system can use this MSR to determ ine “slot” information fo r the processor and the 
proper microcode update to load.0, 1, 2, 3, 4, 6 Shared
APIC Location an d Status (R/W)
See Table 2-2. See Section 11.4.4, “Local APIC Status and Location.”0, 1, 2, 3, 4, 6 Unique
Register Address: 2AH, 42 MSR_EBC_HARD_POWERON
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features.
(R) Indicates current pr ocessor configuration.0, 1, 2, 3, 4, 6 Shared
0O u t p u t  T r i - s t a t e  E n a b l e d  ( R )
Indicates whether tr i-state output is enabled (1) or disabled (0) as 
set by the strapping of SMI#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address 
bus signal is asserted.
1 Execute BIST (R) 
Indicates whether the execution of the BIST is enabled (1) or 
disabled (0) as set by the strapping of INIT#. The value in this bit is written on the deassertion of RESET#; the bit is  set to 1 when 
the address bus sign al is asserted.
2 In Order Queue Depth (R)
Indicates whether the in order queue depth for the system bus is 
1 (1) or up to 12 (0) as set by the strapping of A7#. The value in 
this bit is written on the deassert ion of RESET#; the bit is set to 
1 when the address bus signal is asserted.
3 MCERR# Observation Disabled (R)
Indicates whether MCERR# observation is enabled (0) or disabled 
(1) as determined by the strapping of A9#. The value in this bit is written on the deassertion of RE SET#; the bit is set to 1 when 
4 BINIT# Observation Enabled (R)
Indicates whether BINIT# observation is enabled (0) or disabled 
(1) as determined by the strapping of A10#. The value in this bit is written on the deassertion of RESET#; the bit is  set to 1 when 
6:5 APIC Cluster ID (R) 
Contains the logical APIC  cluster ID value as set by the strapping 
of A12# and A11#. The logical clus ter ID value is written into the 
field on the deassertion of RESET# ; the field is set to 1 when the 
address bus signal is asserted.Table 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-455MODEL-SPECIFIC REGISTERS (MSRS)
7 Bus Park Disable (R) 
Indicates whether bus park is enabled (0) or disabled (1) as set by 
the strapping of A15#. The value in this bit is written on the 
deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.
11:8 Reserved.13:12 Agent ID (R) 
Contains the logical ag ent ID value as set by the strapping of 
BR[3:0]. The logical ID value is  written into the field on the 
deassertion of RESET#; the field is  set to 1 when the address bus 
signal is asserted.
Register Address: 2BH, 43 MSR_EBC_SOFT_POWERON
Processor Soft Power-On Configuration (R/W) 
Enables and disables processor features.0, 1, 2, 3, 4, 6 Shared
0 RCNT/SCNT On Request Encoding Enable (R/W) 
Controls the driving of RCNT/SCN T on the request encoding. Set 
to enable (1); clear to disabled (0, default).
1 Data Error Checking Disable (R/W) 
Set to disable system data bus pa rity checking; clear to enable 
parity checking.
2 Response Error Checking Disable (R/W) 
Set to disable (default); clear to enable. 
3 Address/Request Error Checking Disable (R/W) 
Set to disable (default); clear to enable.
4 Initiator MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator bus requests (default); 
clear to enable. 
5 Internal MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator internal errors 
(default); clear to enable. 
6 BINIT# Driver Disable (R/W) 
Set to disable BINIT# driver (default); clear to enable driver.
63:7 Reserved.
Register Address: 2CH, 44 MSR_EBC_FREQUENCY_ID
Processor Frequency Configuration
The bit field layout of this MSR varies according to  the MODEL value in the CPUID version information. 
The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or 
greater than 2. 
(R) The field Indicates the current processor frequency configuration.2,3, 4, 6 Shared
15:0 Reserved.Table 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)

Unique12-456 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
18:16 Scalable Bus Speed (R/W)
Indicates the intended  scalable bus speed:
Encoding Scalable Bus Speed
000B 100 MHz (Model 2)
000B 266 MHz (Model 3 or 4)
001B 133 MHz
010B 200 MHz011B 166 MHz
100B 333 MHz (Model 6)
133.33 MHz should be utilized if performing calculation with 
System Bus Speed when encoding is 001B. 
166.67 MHz should be utilized if performing calculation with 
System Bus Speed when encoding is 011B.
266.67 MHz should be utilized if performing calculation with 
System Bus Speed when encoding is 000B and model encoding = 
3 or 4.
333.33 MHz should be utilized if performing calculation with 
System Bus Speed when encoding is 100B and model encoding = 
6.
23:19 Reserved.31:24 Core Clock Frequency to System Bus Frequency Ratio (R)
The processor core clock freque ncy to system bus frequency 
ratio observed at the de-a ssertion of the reset pin.
Processor Frequency Configuration (R) 
The bit field layout of this MSR varies according to  the MODEL value of the CPUID version information. 
This bit field layout applies to Pentium 4 and Xe on Processors with MODE L encoding less than 2.
Indicates current processor frequency configuration.0, 1 Shared
20:0 Reserved.
23:21 Scalable Bus Speed (R/W)
Encoding  Scalable Bus Speed
000B 100 MHz
All others values reserved.
Control Features in IA-32 Processor (R/W)
(If CPUID.01H:ECX.[bit 5])3, 4, 6 Unique
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIGTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-457MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2.0, 1, 2, 3, 4, 6 Shared
See Table 2-2.0, 1, 2, 3, 4, 6 Unique
See Table 2-2.3, 4, 6 Unique
MTRR Information
See Section 12.11.1, “MTRR Feature Identification.”0, 1, 2, 3, 4, 6 Unique
CS Register Target for CPL 0 Code (R/W)
See Table 2-2 and Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and 
SYSEXIT Instructions.”0, 1, 2, 3, 4, 6 Unique
Stack Pointer for CPL 0 Stack (R/W)
CPL 0 Code Entry Point (R/W)
Machine Check Capabilities (R)
See Table 2-2 and Section 16.3.1.1, “IA32_MCG_CAP MSR.”0, 1, 2, 3, 4, 6 Unique
Machine Check Status (R)
See Table 2-2 and Section 16.3.1.2, “IA32_MCG_STATUS MSR.”0, 1, 2, 3, 4, 6 Unique
Register Address: 17BH, 379 IA32_MCG_CTL
Machine Check Feature Enable (R/W)
See Table 2-2 and Section 16.3.1.3, “IA32_MCG_CTL MSR.”
Register Address: 180H, 384 MSR_MCG_RAX
Machine Check EAX/RAX Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in 
non-64-bit modes at the time of the error, bits 63-32 do not 
contain valid data.
Register Address: 181H, 385 MSR_MCG_RBXTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-458 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Machine Check EBX/RBX Save State
Register Address: 182H, 386 MSR_MCG_RCX
Machine Check ECX/RCX Save State
Register Address: 183H, 387 MSR_MCG_RDX
Machine Check EDX/RDX Save State
Register Address: 184H, 388 MSR_MCG_RSI
Machine Check ESI/RSI Save State
Register Address: 185H, 389 MSR_MCG_RDI
Machine Check EDI/RDI Save State
Register Address: 186H, 390 MSR_MCG_RBP
Machine Check EBP/RBP Save State
Register Address: 187H, 391 MSR_MCG_RSP
Machine Check ESP/RSP Save State
Register Address: 188H, 392 MSR_MCG_RFLAGSTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-459MODEL-SPECIFIC REGISTERS (MSRS)
Machine Check EFLAGS/RFLAG Save State
Register Address: 189H, 393 MSR_MCG_RIP
Machine Check EIP/RIP Save State
Register Address: 18AH, 394 MSR_MCG_MISC
Machine Check Miscellaneous
0D S
When set, the bit indi cates that a page assist or page fault 
occurred during DS norm al operation. The processors response is 
to shut down. 
The bit is used as an aid for debugging DS handling code. It is the 
responsibility of the user (BIOS or  operating system) to clear this 
bit for normal operation.
Register Address: 18BH −18FH, 
395−399MSR_MCG_RESERVED1 −MSR_MCG_RESERVED5
Reserved.
Register Address: 190H, 400 MSR_MCG_R8
Machine Check R8
63:0 Registers R8-15 (and the associated state-save MSRs) exist only 
in Intel 64 processors. These registers contain valid information 
only when the processor is operating in 64-bit mode at the time 
of the error.
Register Address: 191H, 401 MSR_MCG_R9
Machine Check R9D/R9
only when the processor is operating in 64-bit mode at the time of the error.
Register Address: 192H, 402 MSR_MCG_R10
Machine Check R10
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”0, 1, 2, 3, 4, 6 UniqueTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-460 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
63:0 Registers R8-15 (and  the associated state-save MSRs) exist only

63:0 Registers R8-15 (and  the associated state-save MSRs) exist only 
only when the processor is operat ing in 64-bit mode at the time 
Register Address: 193H, 403 MSR_MCG_R11
Machine Check R11
Register Address: 194H, 404 MSR_MCG_R12
Machine Check R12
Register Address: 195H, 405 MSR_MCG_R13
Machine Check R13
Register Address: 196H, 406 MSR_MCG_R14
Machine Check R14
in Intel 64 processors. These registers contain valid information only when the processor is operat ing in 64-bit mode at the time 
Register Address: 197H, 407 MSR_MCG_R15
Machine Check R15
See Table 2-2. See Section 15.1, “Enhanced Intel Speedstep® Technology.” 3, 4, 6 Unique
See Table 2-2. See Section 15.1, “Enhanced Intel Speedstep® Technology.” 3, 4, 6 UniqueTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-461MODEL-SPECIFIC REGISTERS (MSRS)
Thermal Monitor Control (R/W)
See Table 2-2 and Section 15.8.3, “Software Controlled Clock Modulation.”0, 1, 2, 3, 4, 6 Unique
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.0, 1, 2, 3, 4, 6 Unique
Thermal Monitor Status (R/W)
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.0, 1, 2, 3, 4, 6 Shared
Thermal Monitor 2 ControlFor Family F, Model 3 processors: When read, specif ies the value of the target TM2 transition last 
written. When set, it sets the next target va lue for TM2 transition. 3 Shared
For Family F, Model 4 and Model 6 processors: When read, specifies the value of the target TM2 
transition last written. Writes may cause #GP exceptions.4, 6 Shared
Enable Miscellaneous Proc essor Features (R/W) 0, 1, 2, 3, 4, 6 Shared
0 Fast-Strings Enable. See Table 2-2.1 Reserved.
2 x87 FPU Fopcode Compatibility Mode Enable
3T h e r m a l  M o n i t o r  1  E n a b l e
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.
4S p l i t - L o c k  D i s a b l e
When set, the bit causes an #AC exception to be issued instead 
of a split-lock cycle. Operating sy stems that set this bit must align 
system structures to avoi d split-lock scenarios. 
When the bit is clear (default), normal split-locks are issued to the 
bus.
This debug feature is specific to the Pentium 4 processor.
6 Third-Level Cache Disable (R/W)
When set, the third-level cache is disabled; when clear (default) 
the third-level cache is enabled. This flag is reserved for processors that do not ha ve a third-level cache. 
Note that the bit controls only th e third-level cache; and only if 
overall caching is enab led through the CD flag of control register 
CR0, the page-level cache controls, and/or the MTRRs.
See Section 12.5.4, “Disabling and Enabling the L3 Cache.”
7 Performance Monitoring Available (R)
See Table 2-2.Table 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-462 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
8 Suppress Lock Enable
When set, assertion of LOCK on  the bus is suppr essed during a 
Split Lock access. When  clear (default), LOCK is not suppressed.
9 Prefetch Queue Disable
When set, disables the prefetch queue. When clear (default), 
enables the prefetch queue.
10 FERR# Interrupt Reporting Enable (R/W) 
When set, interrupt reporting th rough the FERR# pin is enabled; 
when clear, this interrupt re porting function is disabled. 
When this flag is set and the processor is in  the stop-clock state 
(STPCLK# is asserted), assertin g the FERR# pin signals to the 
processor that an interrupt (suc h as, INIT#, BINIT#, INTR, NMI, 
SMI#, or RESET#) is pending and that the processor should return to normal operation to handle the interrupt.
This flag does not affect the no rmal operation of the FERR# pin 
(to indicate an unmask ed floating-point error) when the STPCLK# 
pin is not asserted.
11 Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R)
When set, the processor does no t support branch trace storage 
(BTS); when clear, BTS is supported.
12 PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable 
(R)
When set, the proce ssor does not support processor event-based 
sampling (PEBS); when cl ear, PEBS is supported.
When this bit is set (1) and the thermal sens or indicates that the 
die temperature is at the pre-determined threshold, the Thermal 
Monitor 2 mechanism is engaged. TM2 will reduce the bus to core 
ratio and voltage according to  the value last written to 
MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, defaul t), the processor does not change 
the VID signals or the bus to core ratio when the processor 
enters a therma l managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 after executing 
CPUID with EAX = 1, then this fe ature is not supported and BIOS 
must not alter the contents of th is bit location. The processor is 
operating out of spec if both th is bit and the TM 1 bit are set to 
disabled states.3
17:14 Reserved.
See Table 2-2.3, 4, 6Table 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-463MODEL-SPECIFIC REGISTERS (MSRS)
When set to 1, the processor fe tches the cache li ne of the 128-
byte sector containing currently required data . When set to 0, the 
processor fetches both ca che lines in the sector.
Single processor platforms shou ld not set this bit. Server 
platforms should set or clear this bit based on platform 
performance observed in validation and testing. 
BIOS may contain a setu p option that controls  the setting of this 
bit.
21:20 Reserved.
22 Limit CPUID MAXVAL (R/W) 
Setting this can cause unexpected behavior to software that 
depends on the availability of  CPUID leaves greater than 3.3, 4, 6
24 L1 Data Cache Context Mode (R/W) 
When set, the L1 data cache is placed in shared mode; when clear 
(default), the cache is placed in adaptive mode. This bit is only 
enabled for IA-32 processors that  support Intel Hyper-Threading 
Technology. See Section 12.5.6, “L1 Data Cache Context Mode.”
When L1 is running in adaptive mode and CR3s are identical, data 
in L1 is shared across logical processors. Otherwise, L1 is not shared and cache us e is competitive.
If the Context ID feature flag (ECX [10]) is set to 0 after executing 
CPUID with EAX = 1, the ability to switch modes is not supported. 
BIOS must not alter the conten ts of IA32_MISC_ENABLE[24].
33:25 Reserved.34 XD Bit Disable (R/W)
Register Address: 1A1H, 417 MSR_PLATFORM_BRV
Platform Feature Requirements (R) 3, 4, 6 Shared17:0 Reserved.
18 PLATFORM Requirements
When set to 1, indi cates the processor has specific platform 
requirements. The details of the platform requirements are listed in the respective data sheets of the processor.

Register Address: 1D7H, 471 MSR_LER_FROM_LIPTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-464 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Contains a pointer to the last branch instructio n that the processor executed prior to the last 
exception that was generated or th e last interrupt that was handled.
See Section 18.13.3, “Last Exception Records.”0, 1, 2, 3, 4, 6 Unique
31:0 From Linear IP
Linear address of the last branch instruction. 
Register Address: 1D7H, 471 MSR_LER_FROM_LIP
63:0 From Linear IP
Linear address of the last branch instruction (If IA-32e mode is 
active). Unique
Register Address: 1D8H, 472 MSR_LER_TO_LIP
This area contains a pointer to the target of the last branch instruction that the processor executed 
prior to the last exception that was genera ted or the last interru pt that was handled.
Linear address of the target of the last branch instruction. 
Linear address of the target of the last branch instruction (If IA-
32e mode is active).Unique
Register Address: 1D9H, 473 MSR_DEBUGCTLA
Controls how several debug features are used. Bit definitions are discussed in the referenced section.
See Section 18.13.1, “MSR_DEBUGCTLA MSR.”0, 1, 2, 3, 4, 6 Unique
Register Address: 1DAH, 474 MSR_LASTBRANCH_TOS
Last Branch Record  Stack TOS (R/O) 
Contains an index (0-3 or 0-15) th at points to the top of the last branch record stack (that is, that 
points the index of the MSR containing the most recent branch record).
See Section 18.13.2, “LBR Stack for Processors Based on Intel NetBurst® Microarchitecture,” and 
addresses 1DBH-1DEH and 680H-68FH.0, 1, 2, 3, 4, 6 Unique
Register Address: 1DBH, 475 MSR_LASTBRANCH_0
Last Branch Re cord 0 (R/O) 
One of four last bran ch record registers on the la st branch record stack. It  contains pointers to the 
source and destination instruction for one of the last  four branches, exceptions , or interrupts that the 
processor took.
MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, 
models 0H-02H. They have be en replaced by the MSRs at 680H-68FH and 6C0H-6CFH. 
See Section 18.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based 
on Skylake Microarchitecture.”0, 1, 2 UniqueTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-465MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1DCH, 476 MSR_LASTBRANCH_1
Last Branch Record 1
See description of the MSR_LASTBRANCH_0 MSR at 1DBH.0, 1, 2 Unique
Register Address: 1DDH, 477 MSR_LASTBRANCH_2
Last Branch Record 2
Register Address: 1DEH, 478 MSR_LASTBRANCH_3
Last Branch Record 3
Variable Range Base MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”0, 1, 2, 3, 4, 6 Shared
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs”.0, 1, 2, 3, 4, 6 Shared
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4Table 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-466 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”0, 1, 2, 3, 4, 6 Shared
See Section 12.11.2.2, “Fixed Range MTRRs”.0, 1, 2, 3, 4, 6 Shared
See Section 12.11.2.2, “Fixed Range MTRRs”.0, 1, 2, 3, 4, 6 SharedTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-467MODEL-SPECIFIC REGISTERS (MSRS)
Page Attribute Table
See Section 12.11.2.2, “Fixed Range MTRRs.”0, 1, 2, 3, 4, 6 Unique
See Table 2-2 and Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”0, 1, 2, 3, 4, 6 Shared
Register Address: 300H, 768 MSR_BPU_COUNTER0
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 301H, 769 MSR_BPU_COUNTER1
Register Address: 302H, 770 MSR_BPU_COUNTER2
Register Address: 303H, 771 MSR_BPU_COUNTER3
Register Address: 304H, 772 MSR_MS_COUNTER0
Register Address: 305H, 773 MSR_MS_COUNTER1
Register Address: 306H, 774 MSR_MS_COUNTER2
Register Address: 307H, 775 MSR_MS_COUNTER3
Register Address: 308H, 776 MSR_FLAME_COUNTER0Table 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)

Unique12-468 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
See Section 20.6.3.2, “Performance Co unters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 309H, 777 MSR_FLAME_COUNTER1
Register Address: 30AH, 778 MSR_FLAME_COUNTER2
Register Address: 30BH, 779 MSR_FLAME_COUNTER3
Register Address: 30CH, 780 MSR_IQ_COUNTER0
Register Address: 30DH, 781 MSR_IQ_COUNTER1
Register Address: 30EH, 782 MSR_IQ_COUNTER2
Register Address: 30FH, 783 MSR_IQ_COUNTER3
Register Address: 310H, 784 MSR_IQ_COUNTER4
Register Address: 311H, 785 MSR_IQ_COUNTER5
Register Address: 360H, 864 MSR_BPU_CCCR0
See Section 20.6.3.3, “CCCR MSRs .” 0, 1, 2, 3, 4, 6 Shared
Register Address: 361H, 865 MSR_BPU_CCCR1
Register Address: 362H, 866 MSR_BPU_CCCR2
Register Address: 363H, 867 MSR_BPU_CCCR3
Register Address: 364H, 868 MSR_MS_CCCR0
Register Address: 365H, 869 MSR_MS_CCCR1
Register Address: 366H, 870 MSR_MS_CCCR2
Register Address: 367H, 871 MSR_MS_CCCR3
Register Address: 368H, 872 MSR_FLAME_CCCR0
See Section 20.6.3.3, “CCCR MSRs .” 0, 1, 2, 3, 4, 6 SharedTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-469MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 369H, 873 MSR_FLAME_CCCR1
Register Address: 36AH, 874 MSR_FLAME_CCCR2
Register Address: 36BH, 875 MSR_FLAME_CCCR3
Register Address: 36CH, 876 MSR_IQ_CCCR0
Register Address: 36DH, 877 MSR_IQ_CCCR1
Register Address: 36EH, 878 MSR_IQ_CCCR2
Register Address: 36FH, 879 MSR_IQ_CCCR3
Register Address: 370H, 880 MSR_IQ_CCCR4
Register Address: 371H, 881 MSR_IQ_CCCR5
Register Address: 3A0H, 928 MSR_BSU_ESCR0
See Section 20.6.3.1, “ESCR MSRs .” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A1H, 929 MSR_BSU_ESCR1
Register Address: 3A2H, 930 MSR_FSB_ESCR0
Register Address: 3A3H, 931 MSR_FSB_ESCR1
Register Address: 3A4H, 932 MSR_FIRM_ESCR0
Register Address: 3A5H, 933 MSR_FIRM_ESCR1
Register Address: 3A6H, 934 MSR_FLAME_ESCR0
Register Address: 3A7H, 935 MSR_FLAME_ESCR1
Register Address: 3A8H, 936 MSR_DAC_ESCR0
Register Address: 3A9H, 937 MSR_DAC_ESCR1Table 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-470 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 3AAH, 938 MSR_MOB_ESCR0
Register Address: 3ABH, 939 MSR_MOB_ESCR1
Register Address: 3ACH, 940 MSR_PMH_ESCR0
Register Address: 3ADH, 941 MSR_PMH_ESCR1
Register Address: 3AEH, 942 MSR_SAAT_ESCR0
Register Address: 3AFH, 943 MSR_SAAT_ESCR1
Register Address: 3B0H, 944 MSR_U2L_ESCR0
Register Address: 3B1H, 945 MSR_U2L_ESCR1
Register Address: 3B2H, 946 MSR_BPU_ESCR0
Register Address: 3B3H, 947 MSR_BPU_ESCR1
Register Address: 3B4H, 948 MSR_IS_ESCR0
Register Address: 3B5H, 949 MSR_IS_ESCR1
Register Address: 3B6H, 950 MSR_ITLB_ESCR0
Register Address: 3B7H, 951 MSR_ITLB_ESCR1
Register Address: 3B8H, 952 MSR_CRU_ESCR0
Register Address: 3B9H, 953 MSR_CRU_ESCR1
Register Address: 3BAH, 954 MSR_IQ_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
This MSR is not available on later processors. It is only available on processo r family 0FH,  models 01H-
02H.0, 1, 2 SharedTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-471MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 3BBH, 955 MSR_IQ_ESCR1
This MSR is not available on later processors. It is only available on processo r family 0FH, models 01H-
02H.0, 1, 2 Shared
Register Address: 3BCH, 956 MSR_RAT_ESCR0
Register Address: 3BDH, 957 MSR_RAT_ESCR1
Register Address: 3BEH, 958 MSR_SSU_ESCR0
Register Address: 3C0H, 960 MSR_MS_ESCR0
Register Address: 3C1H, 961 MSR_MS_ESCR1
Register Address: 3C2H, 962 MSR_TBPU_ESCR0
Register Address: 3C3H, 963 MSR_TBPU_ESCR1
Register Address: 3C4H, 964 MSR_TC_ESCR0
Register Address: 3C5H, 965 MSR_TC_ESCR1
Register Address: 3C8H, 968 MSR_IX_ESCR0
Register Address: 3C9H, 969 MSR_IX_ESCR1
Register Address: 3CAH, 970 MSR_ALF_ESCR0
Register Address: 3CBH, 971 MSR_ALF_ESCR1
Register Address: 3CCH, 972 MSR_CRU_ESCR2
Register Address: 3CDH, 973 MSR_CRU_ESCR3
Register Address: 3E0H, 992 MSR_CRU_ESCR4
Register Address: 3E1H, 993 MSR_CRU_ESCR5Table 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-472 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 3F0H, 1008 MSR_TC_PRECISE_EVENT
Processor Event Based Sampling (PEBS) (R/W)

Processor Event Based Sampling (PEBS) (R/W) 
Controls the enabling of processor event sampling and replay tagging. 0, 1, 2, 3, 4, 6 Shared
12:0 See https://perfmon-e vents.intel.com/ .
23:13 Reserved.
24 UOP Tag 
Enables replay tagging when set.
25 ENABLE_PEBS_MY_THR (R/W)
Enables PEBS for the target logical processor when set; disables 
PEBS when clear (default). 
See Section 20.6.4.3, “IA32_PEBS_ENABLE MSR,” for an 
explanation of the target logical processor. 
This bit is called ENABLE_PEBS in IA-32 processors that do not 
support Intel Hyper-Threading Technology.
26 ENABLE_PEBS_OTH_THR (R/W)
PEBS when clear (default).
This bit is reserved for IA-32 proc essors that do not support Intel 
Hyper-Threading Technology.
Register Address: 3F2H, 1010 MSR_PEBS_MATRIX_VERT
See https://perfmon-e vents.intel.com/ . 0, 1, 2, 3, 4, 6 Shared
See Section 16.3.2.1, “IA32_MC i_CTL MSRs.” 0, 1, 2, 3, 4, 6 Shared
See Section 16.3.2.2, “IA32_MCi_STATUS  MSRS.” 0, 1, 2, 3, 4, 6 Shared
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in 
the IA32_MC0_STATUS register is clear. 
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.0, 1, 2, 3, 4, 6 Shared
Register Address: 403H, 1027 IA32_MC0_MISCTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-473MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.4, “IA32_MC i_MISC MSRs.”
The IA32_MC0_MISC MSR is either not implemented or  does not contain additi onal information if the 
MISCV flag in the IA32_MC0_STATUS register is clear. 
When not implemented in the processor, all read s and writes to this MSR will cause a general-
The IA32_MC1_ADDR register is either not implemente d or contains no addre ss if the ADDRV flag in 
the IA32_MC1_STATUS register is clear. 
The IA32_MC1_MISC MSR is either not implemented or  does not contain additi onal information if the 
MISCV flag in the IA32_MC1_STATUS register is clear. 
protection exception.Shared
The IA32_MC2_ADDR register is either not implemente d or contains no addre ss if the ADDRV flag in 
the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes 
to this MSR will cause a general-protection exception.
The IA32_MC2_MISC MSR is either not implemented or  does not contain additi onal information if the 
MISCV flag in the IA32_MC2_STATUS register is clear. 
Register Address: 40EH, 1038 IA32_MC3_ADDRTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-474 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
The IA32_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in 
the IA32_MC3_STATUS register is clear. 
The IA32_MC3_MISC MSR is either not implemented or  does not contain additional information if the 
MISCV flag in the IA32_MC3_S TATUS register is clear. 
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in 
the IA32_MC4_STATUS register is clear. 
See Section 16.3.2.4, “IA32_MC i_MISC MSRs.” 
The IA32_MC2_MISC MSR is either not implemented or  does not contain additional information if the 
MISCV flag in the IA32_MC4_S TATUS register is clear. 
See Table 2-2 and Appendix A.1, “Basic VMX Information.”3, 4, 6 Unique
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)
See Table 2-2 and Appendix A.3, “VM-Execution Controls.”3, 4, 6 Unique
See Appendix A.3, “VM-Execution Controls,” and Table 2-2.3, 4, 6 Unique
Capability Reporting Register of VM-Exit Controls (R/O)
See Appendix A.4, “VM-Exit Controls,” and Table 2-2.3, 4, 6 Unique
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLSTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-475MODEL-SPECIFIC REGISTERS (MSRS)
See Appendix A.5, “VM-Entry Controls,” and Table 2-2.3, 4, 6 Unique
See Appendix A.6, “Miscellaneous Data,” and Table 2-2.3, 4, 6 Unique
See Appendix A.7, “VMX-Fixed Bits in CR0,” and Table 2-2.3, 4, 6 Unique
See Appendix A.8, “VMX-Fixed Bits in CR4,” and Table 2-2.3, 4, 6 Unique
See Appendix A.9, “VMCS Enumeration,” and Table 2-2.3, 4, 6 Unique
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”0, 1, 2, 3, 4, 6 Unique
Register Address: 680H, 1664 MSR_LASTBRANCH_0_FROM_IP
Last Branch Record 0 (R/W) 
One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part

One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part 
of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or 
interrupts taken by the processor.
The MSRs at 680H-68FH, 6C 0H-6CfH are not available in processor releases before family 0FH, model 
03H. These MSRs replace MSRs previously located at 1DBH-1DEH. which performed the same function for early releases. 
on Skylake Microarchitecture.”3, 4, 6 Unique
Register Address: 681H, 1665 MSR_LASTBRANCH_1_FROM_IP
See description of MSR_LASTBRANCH_0 at 680H.3, 4, 6 Unique
Register Address: 682H, 1666 MSR_LASTBRANCH_2_FROM_IPTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-476 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 683H, 1667 MSR_LASTBRANCH_3_FROM_IP
Register Address: 684H, 1668 MSR_LASTBRANCH_4_FROM_IP
Last Branch Record 4
Register Address: 685H, 1669 MSR_LASTBRANCH_5_FROM_IP
Last Branch Record 5
Register Address: 686H, 1670 MSR_LASTBRANCH_6_FROM_IP
Last Branch Record 6
Register Address: 687H, 1671 MSR_LASTBRANCH_7_FROM_IP
Last Branch Record 7
Register Address: 688H, 1672 MSR_LASTBRANCH_8_FROM_IP
Last Branch Record 8
Register Address: 689H, 1673 MSR_LASTBRANCH_9_FROM_IP
Last Branch Record 9
Last Branch Record 10
Last Branch Record 11
Last Branch Record 12
Last Branch Record 13
Last Branch Record 14
See description of MSR_LASTBRANCH_0 at 680H.3, 4, 6 UniqueTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-477MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 15
One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part 
of the stack contains pointers to the destination instruction for one of the last 16 branches, 
exceptions, or interrupts that the processor took.
See description of MSR_LASTBRANCH_0 at 6C0H.3, 4, 6 Unique
Register Address: 6CAH, 1738 MSR_LASTBRANCH_10_TO_IPTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-478 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6CBH, 1739 MSR_LASTBRANCH_11_TO_IP
See Table 2-2.3, 4, 6 UniqueTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique1Vol. 4 2-479MODEL-SPECIFIC REGISTERS (MSRS)
2.19.1  MSRs Unique to Intel® Xeon® Processor MP with L3 Cache
The MSRs listed in Table 2-59 apply to Intel® Xeon® Processor MP with up to 8MB level three cache. These proces-
sors can be detected by enumerating the deterministic ca che parameter leaf of CPUID instruction (with EAX = 4 as 
input) to detect the presence of the third level cache,  and with CPUID reporting fa mily encoding 0FH, model 
encoding 3 or 4 (see CPUID instruction for more details).
The MSRs listed in Table 2-60 apply to Intel® Xeon® Processor 7100 series. These processors can be detected by 
enumerating the deterministic cache parameter leaf of CP UID instruction (with EAX = 4 as input) to detect the NOTES
1. For HT-enabled processors, there may be more than one logical processors per physical unit. If an MSR is Shared, this means that 
one MSR is shared between logical processors. If an MSR is un ique, this means that each logical processor has its own MSR.
Table 2-59.  MSRs Unique to 64-bit Intel® Xeon ® Processor MP with Up to an 8 MB L3 Cache
Register Address: Hex Register Name
Register InformationModel 
Unique
Register Address: 107CCH MSR_IFSB_BUSQ0
IFSB BUSQ Event Control and Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bi t Intel® Xeon® Processor MP with Up to 8-MByte 
L3 Cache.”3, 4 Shared
Register Address: 107CDH MSR_IFSB_BUSQ1
IFSB BUSQ Event Control and Counter Register (R/W) 3, 4 Shared
Register Address: 107CEH MSR_IFSB_SNPQ0
IFSB SNPQ Event Control and Counter Register (R/W) 
Register Address: 107CFH MSR_IFSB_SNPQ1
IFSB SNPQ Event Control and Counter Register (R/W) 3, 4 Shared
Register Address: 107D0H MSR_EFSB_DRDY0
EFSB DRDY Event Control and Counter Register (R/W) 
Register Address: 107D1H MSR_EFSB_DRDY1
EFSB DRDY Event Control and Counter Register (R/W) 3, 4 Shared
Register Address: 107D2H MSR_IFSB_CTL6
IFSB Latency Event Con trol Register (R/W)

Register Address: 107D3H MSR_IFSB_CNTR7
IFSB Latency Event Counter Register (R/W) 
L3 Cache.” 3, 4 SharedTable 2-58.  MSRs in the Pentium® 4 and Intel® Xeon® Pr ocessors  (Contd.)
Unique12-480 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
presence of the third level cache, and with CPUID report ing family encoding 0FH, model encoding 6 (See CPUID 
instruction for more details.). The performance monitoring  MSRs listed in Table 2-60 are shared between logical 
processors in the same core, but are replicated for each core.
2.20 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS
Model-specific registers (MSRs) for Intel Core Solo, Inte l Core Duo processors, and Dual-core Intel Xeon processor 
LV are listed in Table 2-61. The column “Shared/Unique” applies to Intel Core Duo processor. “Unique” means each processor core has a separate MSR, or a bit field in an MSR governs only a core indepe ndently. “Shared” means the 
MSR or the bit field in an MSR address gove rns the operation of both processor cores.Table 2-60.  MSRs Unique to In tel® Xeon® Processor 7100 Series
Unique
Register Address: 107CCH MSR_EMON_L3_CTR_CTL0
GBUSQ Event Control and Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3 
Cache.”6S h a r e d
Register Address: 107CDH MSR_EMON_L3_CTR_CTL1
GBUSQ Event Control and Counter Register (R/W) 6 Shared
Register Address: 107CEH MSR_EMON_L3_CTR_CTL2
GSNPQ Event Control and Counter Register (R/W) 
Register Address: 107CFH MSR_EMON_L3_CTR_CTL3
GSNPQ Event Control and Counter Register (R/W) 6 Shared
Register Address: 107D0H MSR_EMON_L3_CTR_CTL4
FSB Event Control and Counter Register (R/W) 
Register Address: 107D1H MSR_EMON_L3_CTR_CTL5
FSB Event Control and Counter Register (R/W) 6 Shared
Register Address: 107D2H MSR_EMON_L3_CTR_CTL6
Register Address: 107D3H MSR_EMON_L3_CTR_CTL7
Table 2-61.  MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Information / Bit Fields Bit DescriptionShared/ 
Unique
Register Address: 0H, 0 P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors,” and Table 2-2. Unique
Register Address: 1H, 1 P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors,” and Table 2-2. UniqueVol. 4 2-481MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. The operating system can use this MSR to determine “slot” information for the processor and the proper 
microcode update to load.Shared
Note: Not all processor implements R/W.
6: 5 Reserved.
7 BINIT# Driver Enable (R/W)
8O u t p u t  T r i - s t a t e  E n a b l e d  ( R / O )
11 Reserved.
1 = Enabled; 0 = Disabled.Table 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
Unique2-482 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
13 Reserved
1 = 1 MByte; 0 = 4 GBytes
17:16 APIC Cluster ID (R/O)
18 System Bus Frequency (R/O)
0 = 100 MHz.
1 = Reserved.
19 Reserved.21: 20 Symmetric Arbitration ID (R/O)
26:22 Clock Frequency Ratio (R/O)
Control Features in IA-32 Processor (R/W) 
Register Address: 40H, 64 MSR_LASTBRANCH_0
Last Branch Re cord 0 (R/W)
One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32 
hold the ‘to’ address. See also:
• Section 18.15, “Last Branch, Interrupt, and Ex ception Recordin g (Pentium M Processors).”Unique
Register Address: 41H, 65 MSR_LASTBRANCH_1
Last Branch Re cord 1 (R/W)
See description of MSR_LASTBRANCH_0.Unique
Register Address: 42H, 66 MSR_LASTBRANCH_2
Last Branch Re cord 2 (R/W)
See description of MSR_LASTBRANCH_0. Unique
Register Address: 43H, 67 MSR_LASTBRANCH_3
Last Branch Re cord 3 (R/W)
Register Address: 44H, 68 MSR_LASTBRANCH_4
Last Branch Re cord 4 (R/W)
Register Address: 45H, 69 MSR_LASTBRANCH_5
Last Branch Re cord 5 (R/W)
Register Address: 46H, 70 MSR_LASTBRANCH_6
Last Branch Re cord 6 (R/W)
Register Address: 47H, 71 MSR_LASTBRANCH_7Table 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
UniqueVol. 4 2-483MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 7 (R/W)
BIOS Update Trigger Register (W)
This field indicates the scalable bus clock speed.Shared
133.33 MHz should be utilized if performing calculation with System Bus Speed 
when encoding is 101B. 
166.67 MHz should be utilized if performing calculation with System Bus Speed 
when encoding is 001B.
Maximum Performance Frequency Clock Count (R/W)
0 = Indicates if the L2 is hardware-disabled.Table 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
Unique2-484 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
8 L2 Enabled (R/W) 
Until this bit is set the pr ocessor will not respond to the WBINVD instruction or 
the assertion of the FLUSH# input.
22:9 Reserved.
0R I P V
When set, this bit indica tes that the instruction ad dressed by the instruction

0R I P V
When set, this bit indica tes that the instruction ad dressed by the instruction 
pointer pushed on the st ack (when the machine check was generated) can be 
used to restart the pr ogram. If this bit is cleared, the program cannot be reliably 
1E I P V
2M C I P
When set, this bit indicate s that a machine check has been generated. If a second 
shutdown state. Software should write th is bit to 0 after pr ocessing a machine 
check exception.
63:3 Reserved
Register Address: 198H, 408 IA32_PERF_STATUSTable 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
UniqueVol. 4 2-485MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2 and Section 15.8.2, “Thermal Monitor.”Unique
See Table 2-2 and Section 15.8.2, “Thermal Monitor”.Unique
0 = Thermal Monitor 1 (therm ally-initiated on-die modu lation of the stop-clock 
duty cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency transitions)If bit 3 of the IA32_MISC_ENABLE register  is cleared, TM_SELECT has no effect. 
Neither TM1 nor TM 2 will be enabled.
Enable Miscellaneous Pr ocessor Features (R/W) 
2:0 Reserved.3 Automatic Thermal Contro l Circuit Enable (R/W) 
10 FERR# Multiplexing Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending break event within 
the processor 
0 =  Indicates compatible FERR# signaling behavior
See Table 2-2.SharedTable 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
Unique2-486 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
12 Reserved.
When this bit is set (1) an d the thermal sensor indicate s that the die temperature 
is at the pre-determined threshold,  the Thermal Monitor 2 mechanism is 
engaged. TM2 will reduce the bus to core ratio and voltage according to the value 
last written to MSR_TH ERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not change th e VID signals 
or the bus to core ratio when the processor enters a thermal managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 
1, then this feature is not supported and BIOS must not alter the contents of this 
bit location. The processor is operating ou t of spec if both this bit and the TM1 
bit are set to disabled states.Shared
1 = Enhanced Intel SpeedStep Technology enabledShared
Setting this bit may cause be havior in software that de pends on the availability 
of CPUID leaves greater than 2.Shared
33:23 Reserved.
See Table 2-3.Shared
Controls how several debug features are used. Bit definitions are discussed in Table 2-2.Unique
This area contains a pointer to  the target of the last branch instruction that the processor executed prior to the last 
Register Address: 200H, 512 MTRRphysBase0Table 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
UniqueVol. 4 2-487MODEL-SPECIFIC REGISTERS (MSRS)
Memory Type Range Registers Unique
Register Address: 201H, 513 MTRRphysMask0
Register Address: 202H, 514 MTRRphysBase1
Register Address: 203H, 515 MTRRphysMask1
Register Address: 204H, 516 MTRRphysBase2
Register Address: 205H, 517 MTRRphysMask2
Register Address: 206H, 518 MTRRphysBase3
Register Address: 207H, 519 MTRRphysMask3
Register Address: 208H, 520 MTRRphysBase4
Register Address: 209H, 521 MTRRphysMask4
Register Address: 20AH, 522 MTRRphysBase5
Register Address: 20BH, 523 MTRRphysMask5
Register Address: 20CH, 524 MTRRphysBase6
Register Address: 20DH, 525 MTRRphysMask6
Register Address: 20EH, 526 MTRRphysBase7
Register Address: 20FH, 527 MTRRphysMask7
Register Address: 250H, 592 MTRRfix64K_00000
Register Address: 258H, 600 MTRRfix16K_80000
Register Address: 259H, 601 MTRRfix16K_A0000
Memory Type Range Registers UniqueTable 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
Unique2-488 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 268H, 616 MTRRfix4K_C0000
Register Address: 269H, 617 MTRRfix4K_C8000
Register Address: 26AH, 618 MTRRfix4K_D0000
Register Address: 26BH, 619 MTRRfix4K_D8000
Register Address: 26CH, 620 MTRRfix4K_E0000
Register Address: 26DH, 621 MTRRfix4K_E8000
Register Address: 26EH, 622 MTRRfix4K_F0000
Register Address: 26FH, 623 MTRRfix4K_F8000
Default Memory Types (R/W)
See Table 2-2 and Section 12.11. 2.1, “IA32_MTRR_DEF_TYPE MSR.”Unique
IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will 
cause a general-protection exception.Unique
IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will 
Register Address: 408H, 1032 IA32_MC2_CTLTable 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)

UniqueVol. 4 2-489MODEL-SPECIFIC REGISTERS (MSRS)
IA32_MC2_STATUS register is clear. When not implemented in  the processor, all reads an d writes to this MSR will 
Register Address: 40CH, 1036 MSR_MC4_CTL
Register Address: 40DH, 1037 MSR_MC4_STATUS
Register Address: 40EH, 1038 MSR_MC4_ADDR
MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause 
a general-protection exception.Unique
Register Address: 410H, 1040
IA32_MC3_CTL See Section 16.3.2.1, “IA32_MC i_CTL MSRs.”
Register Address: 411H, 1041
IA32_MC3_STATUS See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 412H, 1042 MSR_MC3_ADDR
MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause 
Register Address: 413H, 1043 MSR_MC3_MISC
Machine Check Error Reporting Register - contains addition al information describing the machine-check error if the 
MISCV flag in the IA32_MCi_STATUS register is set.Unique
Register Address: 414H, 1044 MSR_MC5_CTL
Machine Check Error Reporting Register - controls signaling of  #MC for errors produced by a particular hardware unit 
Register Address: 415H, 1045 MSR_MC5_STATUS
Machine Check Error Reporting Register - co ntains information related to a machine-check error if its VAL (valid) flag is 
set. Software is respon sible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them 
Register Address: 416H, 1046 MSR_MC5_ADDR
Machine Check Error Reporting Register - contains the address of the code or data memory location that produced the 
Register Address: 417H, 1047 MSR_MC5_MISCTable 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
Unique2-490 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Machine Check Error Reporting Register - contains additional information describing the machine-check error if the 
See Table 2-2 and Appendix A.1, “Basic VMX Information.” (If CPUID.01H:ECX.[bit 5])Unique
Register Address: 481H, 1153 IA32_VMX_PIN BASED_CTLS
See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX.[bit 5])Unique
See Appendix A.4, “VM-Exit Controls.” (If CPUID.01H:ECX.[bit 5])Unique
See Appendix A.5, “VM-Entry Cont rols.” (If CPUID.01H:ECX.[bit 5])Unique
See Appendix A.6, “Miscellaneous Data.” (If CPUID.01H:ECX.[bit 5])Unique
See Appendix A.7, “VMX-Fixed Bits in CR0.” (If CPUID.01H:ECX.[bit 5])Unique
See Appendix A.8, “VMX-Fixed Bits in CR4.” (If CPUID.01H:ECX.[bit 5])Unique
See Appendix A.9, “VMCS Enumerat ion.” (If CPUID.01H:ECX.[bit 5])Unique
See Appendix A.3, “VM-Execution Controls.” (If CPUI D.01H:ECX.[bit 5] and IA32_VMX_PROCBASED_CTLS[bit 63])Unique
Register Address: 600H, 1536 IA32_DS_AREATable 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
UniqueVol. 4 2-491MODEL-SPECIFIC REGISTERS (MSRS)
2.21 MSRS IN THE PENTIUM M PROCESSOR
Model-specific registers (MSRs) for the Pentium M processo r are similar to those described in Section 2.22 for P6 
family processors. The following tabl e describes new MSRs and MSRs whose behavior has changed on the Pentium 
M processor. DS Save Area (R/W) 
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”Unique
31:0 DS Buffer Management Area
Linear address of the first byte of the DS buffer management area.
10:0 Reserved.11 Execute Disable Bit Enable63:12 Reserved.
Table 2-62.  MSRs in Pentium M Processors
Register Information / Bit Fields Bit Description
See Section 2.23, “MSRs in Pentium Processors.”
See Section 18.17, “Time-Stamp Counter,” and see Table 2-2.
Platform ID (R)
See Table 2-2.The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load .
(R/W) Enables and disables processor features.(R) Indicates current pr ocessor configuration.
0 Reserved.1 Data Error Checking Enable (R)
Always 0 on the Pentium M processor.Table 2-61.  MSRs in Intel® Core™ Solo , Intel® Core™ Duo Processors, and Dual-C ore Intel® Xeon® Processor LV (Contd.)
Unique2-492 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2 Response Error Checking Enable (R)
Always 0 on the Pentium M processor.
3 MCERR# Drive Enable (R) 
4 Address Parity Enable (R)
6:5 Reserved.7 BINIT# Driver Enable (R)
Always 00B on the Pentium M processor.
0 = 100 MHz.
Register Address: 40H, 64 MSR_LASTBRANCH_0Table 2-62.  MSRs in Pent ium M Processors (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-493MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 0 (R/W)

0 = 100 MHz.
One of 8 last branch  record registers on the last branch  record stack: bits 31-0 hold the ‘from’ address and bits 63-32 hold th e to 
address. 
See also:
• Section 18.15, “Last Branch, Interrupt, and Ex ception Recordin g (Pentium M Processors).”
Last Branch Record 1 (R/W)
See description of MSR_LASTBRANCH_0.
Last Branch Record 2 (R/W)
See description of MSR_LASTBRANCH_0. 
Last Branch Record 3 (R/W)
Last Branch Record 4 (R/W)
Last Branch Record 5 (R/W)
Last Branch Record 6 (R/W)
Register Address: 47H, 71 MSR_LASTBRANCH_7
Register Address: 119H, 281 MSR_BBL_CR_CTL
Control Register
Used to program L2 commands to  be issued via cache configur ation accesses mechanism. Also receives L2 lookup response.
Used to configure the L2 Cache.
4:1 Reserved.Table 2-62.  MSRs in Pent ium M Processors (Contd.)
Register Information / Bit Fields Bit Description2-494 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
5 ECC Check Enable (R/O)
This bit enables ECC checking on the cach e data bus. ECC is always generated on 
write cycles. 
1 = Enabled.
For the Pentium M processor, ECC checking on the cache data bus is always enabled.
7:6 Reserved.
Until this bit is set the pr ocessor will not respond to th e WBINVD instruction or the 
assertion of the FLUSH# input.
Read-only register that provides information about the machine-check architecture of the processor. 7:0 Count (R/O)
Indicates the number of hardware unit error reporting banks available in the 
8 IA32_MCG_CTL Present (R/O)
1 = Indicates that the processor implemen ts the MSR_MCG_CTL register found at 
MSR 17BH.
0 = Not supported.
Global Machine Check Status
0R I P V
When set, this bit indicates that the instruction addressed by the instruction pointer 
pushed on the stack (when the machine chec k was generated) can be used to restart 
the program. If this bit is  cleared, the program cannot be reliably restarted.
1E I P V
pushed on the stack (when the machine check was generated) is directly associated 
with the error.
2M C I P
When set, this bit indicates that a machin e check has been generated. If a second 
machine check is detected while this bit is still set, the processor enters a shutdown 
state. Software should write this bit to 0 after processing a machine check exception.
Register Address: 198H, 408 IA32_PERF_STATUSTable 2-62.  MSRs in Pent ium M Processors (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-495MODEL-SPECIFIC REGISTERS (MSRS)
Clock Modulation (R/W). 
See Table 2-2 and Section 15.8.3, “Software Controlled Clock Modulation.”
See Table 2-2 and Section 15.8.2, “Thermal Monitor.”
Thermal Monitor 2 Control
0 = Thermal Monitor 1 (thermally-initiated on -die modulation of the stop-clock duty 
cycle)
1 = Thermal Monitor 2 (thermally-i nitiated freque ncy transitions)
If bit 3 of the IA32 _MISC_ENABLE register is clea red, TM_SELECT has no effect. 
Neither TM1 nor TM2 will be enabled.
Enable Miscellaneous Pr ocessor Features (R/W)
2:0 Reserved.
1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel 
Thermal Monitor feature. This allows processor clocks to  be automatically 
modulated based on the processor's thermal sensor operation. 
0 = Disabled (default). The automatic thermal control circuit enable bit determin es if the thermal control 
circuit (TCC) will be activated when th e processor's internal thermal sensor 
determines the processor is  about to exceed its maximum operating temperature.
When the TCC is activated and TM1 is enabled, the processors clocks will be forced to 
a 50% duty cycle. BIOS mu st enable this feature.
The bit should not be confus ed with the on-demand therma l control circuit enable bit.
6:4 Reserved.7 Performance Monitoring Available (R) 
0 = Performance monitoring disabled.Table 2-62.  MSRs in Pent ium M Processors (Contd.)
Register Information / Bit Fields Bit Description2-496 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
1 = FERR# asserted by the processor to indicate a pending break event within the 
This bit must be set to 1 to su pport XAPIC interrupt model usage.
Branch Trace Storage Unavailable (R/O)
1 = Processor doesn’t support branch trace storage (BTS)
0 = BTS is supported
12 Processor Event Based Sampling Unavailable (R/O) 
1 = Processor does not support proc essor event based sampling (PEBS); 
0 = PEBS is supported. The Pentium M processor does not support PEBS.
1 = Enhanced Intel SpeedS tep Technology enabled.
On the Pentium M processo r, this bit may be conf igured to be read-only.
22:17 Reserved.
When set to 1, xTPR messages are disabled. xTPR messages are optional messages 
that allow the processor to in form the chipset of its priori ty. The default is processor 
specific.
Contains an index (bits 0-3) that points to the MSR contai ning the most recent branch record. See also:
• MSR_LASTBRANCH_0_FROM_IP (at 40H).
Register Address: 1D9H, 473 MSR_DEBUGCTLB
See Section 18.15, “Last Branch , Interrupt, and Exception Reco rding (Pentium M Processors).”
Register Address: 1DDH, 477 MSR_LER_TO_LIP
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last excepti on that 
was generated or the last interrupt that was handled.
See Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors),” and Section 18.16.2, “Last Branch and 
Last Exception MSRs.”
Register Address: 1DEH, 478 MSR_LER_FROM_LIPTable 2-62.  MSRs in Pent ium M Processors (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-497MODEL-SPECIFIC REGISTERS (MSRS)
Contains a pointer to the last branch instruction that the proce ssor executed prior to the last exception that was generated or  the 
last interrupt that was handled.
See Section 18.15, “Last Branch, Interrupt,  and Exception Recording (Pen tium M Processors),” and Sect ion 18.16.2, “Last Branch and 
Sets the memory type for the regions of physic al memory that are not mapped by the MTRRs. 
See Section 12.11.2.1, “I A32_MTRR_DEF_TYPE MSR.”
See Section 14.3.2.3., “IA32_MCi_ADDR MSRs”.

See Section 14.3.2.3., “IA32_MCi_ADDR MSRs”. 
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register 
is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register 
See Chapter 16.3.2.2, “I A32_MCi_STATUS MSRS.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register 
Register Address: 40EH, 1038 MSR_MC4_ADDRTable 2-62.  MSRs in Pent ium M Processors (Contd.)
Register Information / Bit Fields Bit Description2-498 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.22 MSRS IN THE P6 FAMILY PROCESSORS
The following MSRs are defined for the P6 family processors. The MSRs in this table that are shaded are available 
only in the Pentium II and Pentium III processors. Beginning with the Pentium 4 processor, some of the MSRs in this 
list have been designated as “architectural” and have ha d their names changed. See Table 2-2 for a list of the archi-
tectural MSRs.See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains  no address if the ADDRV flag in the MSR_MC4_STATUS register 
Register Address: 410H, 1040 MSR_MC3_CTL
Register Address: 411H, 1041 MSR_MC3_STATUS
The MSR_MC3_ADDR register is either not implemented or contains  no address if the ADDRV flag in the MSR_MC3_STATUS register 
See Table 2-2.Points to the DS buffer manageme nt area, which is used to manage the BTS and PEBS buffers. See Section 20.6.3.4, “Debug Store 
(DS) Mechanism.”
Linear address of the first byte of  the DS buffer management area.
Table 2-63.  MSRs in the P6 Family Processors 
Register Address: 10H, 16 TSC
See Section 18.17, “Time-Stamp Counter.”
The operating system can use this MSR to de termine “slot” information for the processo r and the proper microcode update to load .
49:0 Reserved.Table 2-62.  MSRs in Pent ium M Processors (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-499MODEL-SPECIFIC REGISTERS (MSRS)
52:50 Platform Id (R)
Contains information concerning the intended platform for the processor. 52 51 50
56:53 L2 Cache Latency Read.59:57 Reserved.
60 Clock Frequency Ratio Read.
63:61 Reserved.
Register Address: 1BH, 27 APIC_BASE
Section 11.4.4, “Local APIC Status and Location.”
7:0 Reserved.8 Boot Strap Processor Indicator Bit
1 = BSP
10:9 Reserved.
11 APIC Global Enable Bi t - Permanent till reset
31:12 APIC Base Address.63:32 Reserved.
Register Address: 2AH, 42 EBL_CR_POWERON
Processor Hard Power-On Configuration 
(R/W) Enables and disables processor features, an d (R) indicates current processor configuration.
0R e s e r v e d1
2 Response Error Checking Enable FRCERR Observation Enable (R/W)
3 AERR# Drive Enable (R/W)
4B E R R #  E n a b l e  f o r  I n i t i a tor Bus Requests (R/W)
0 = Disabled.Table 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bi t Fields Bit Description2-500 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
5R e s e r v e d .
6 BERR# Driver Enable for Initiator Internal Errors (R/W)
8 Output Tri-state Enabled (R)
9E x e c u t e  B I S T  ( R )
10 AERR# Observation Enabled (R)
11 Reserved.12 BINIT# Observation Enabled (R)
13 In Order Queue Depth (R)
1 = 1.
0 = 8.
14 1-MByte Power on Reset Vector (R)
1 = 1MByte.
0 = 4GBytes.
 15 FRC Mode Enable (R)
 17:16 APIC Cluster ID (R)
19:18 System Bus Frequency (R)
00 = 66MHz.
10 = 100Mhz.01 = 133MHz.
11 = Reserved.
21: 20 Symmetric Arbitration ID (R)25:22 Clock Frequency Ratio (R)
26 Low Power Mode Enable (R/W)
27 Clock Frequency Ratio63:28 Reserved.
1
Register Address: 33H, 51 MSR_TEST_CTRLTable 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-501MODEL-SPECIFIC REGISTERS (MSRS)
Test Control Register
30 Streaming Buffer Disable31 Disable LOCK#
Assertion for split locked access.
Register Address: 79H, 121 BIOS_UPDT_TRIG
BIOS Update Trigger Register.
Register Address: 88H, 136 BBL_CR_D0[63:0]
Chunk 0 data register D[63:0]: used to write to and read from the L2.
Register Address: 89H, 137 BBL_CR_D1
Chunk 1 data register D[63:0]: used to write to and read from the L2.
Register Address: 8AH, 138 BBL_CR_D2
Chunk 2 data register D[63:0]: used to write to and read from the L2.
Register Address: 8BH, 139 BIOS_SIGN/BBL_CR_D3
BIOS Update Signature Register or Chunk 3 data register D[63:0].
Used to write to and read from th e L2 depending on the usage model.
Register Address: C1H, 193 PerfCtr0 (PERFCTR0)
Register Address: C2H, 194 PerfCtr1 (PERFCTR1)
Register Address: FEH, 254 MTRRcap
Memory Type Range Registers
Register Address: 116H, 278 BBL_CR_ADDR 
Address register: used to send specified address (A31-A3) to L2 during cache initialization accesses.
2:0 Reserved; set to 0.31:3 Address bits [35:3].
Register Address: 118H, 280 BBL_CR_DECC
Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
Register Address: 119H, 281 BBL_CR_CTL 
Control register: used to program L2 commands to be  issued via cache configur ation accesses mechanism. Al so receives L2 lookup 
response.Table 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bi t Fields Bit Description2-502 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
4:0 L2 Command:
01100 = Data Read w/ LRU update (RLU).
01110 = Tag Read w/ Data Read (TRR).
01111 = Tag Inquire (TI).
00010 = L2 Control Register Read (CR).00011 = L2 Control Register Write (CW).
010 + MESI encode = Tag Wr ite w/ Data Read (TWR).
111 + MESI encode = Tag Write w/ Data Write (TWW).100 + MESI encode = Tag Write (TW).
6:57 State to L29:8 Reserved.
11:10 Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11
Way to L2
13:12 Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00
Way from L2
15:14 State from L2.
16 Reserved.17 L2 Hit.
18 Reserved.
20:19 User supplied ECC.21 Processor number: 
2
Disable = 1.
Enable = 0.
Reserved.
63:22 Reserved.
Register Address: 11AH, 282 BBL_CR_TRIG
Trigger register: used to initiate a cache config uration accesses access, Wr ite only with Data = 0.
Register Address: 11BH, 283 BBL_CR_BUSY
Busy register: indicates when a cach e configuration accesses L2 command is in progress. D[0] = 1 = BUSY.

Way to L2
Way from L2
2
Enable = 0.
Reserved.
Register Address: 11EH, 286 BBL_CR_CTL3
Control register 3: used to configure the L2 Cache.
0 L2 Configured (read/write).4:1 L2 Cache Latency (read/write).
5 ECC Check Enable (read/write).
6 Address Parity Check Enable (read/write).7 CRTN Parity Check Enable (read/write).
8 L2 Enabled (read/write).Table 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-503MODEL-SPECIFIC REGISTERS (MSRS)
10:9 L2 Associativity (read only):
00 = Direct Mapped.
01 = 2 Way.
10 = 4 Way.
12:11 Number of L2 banks (read only).
17:13 Cache size per bank (read/write):
00001 = 256 KBytes.
00010 = 512 KBytes.00100 = 1 MByte.
01000 = 2 MBytes.
10000 = 4 MBytes.
18 Cache State error checking enable (read/write).19 Reserved.
22:20 L2 Physical Address Range support:
111 = 64 GBytes.
110 = 32 GBytes.101 = 16 GBytes.
100 = 8 GBytes.
011 = 4 GBytes.010 = 2 GBytes.
001 = 1 GByte.
000 = 512 MBytes.
23 L2 Hardware Disable (read only).
24 Reserved.
25 Cache bus fraction (read only).63:26 Reserved.
Register Address: 174H, 372 SYSENTER_CS_MSR
CS register target for CPL 0 code
Register Address: 175H, 373 SYSENTER_ESP_MSR
Stack pointer for CPL 0 stack
Register Address: 176H, 374 SYSENTER_EIP_MSR
CPL 0 code entry point
Register Address: 179H, 377 MCG_CAP
Machine Check Global Control Register
Register Address: 17AH, 378 MCG_STATUS
Machine Check Error Reporting Register - cont ains information related to a machine-check error if its VAL (valid) flag is set. Software 
is responsible for clearing IA32_MCi_STATUS MSRs by explicitly wr iting 0s to them; writing 1s to  them causes a general-protecti on 
Register Address: 17BH, 379 MCG_CTL
Machine Check Error Reporting Register - controls signaling of #M C for errors produced by a particular hardware unit (or group of 
hardware units).
Register Address: 186H, 390 PerfEvtSel0 (EVNTSEL0)Table 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bi t Fields Bit Description2-504 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Performance Event Select Register 0 (R/W)
Refer to Performance Counter section for a list of event encodings.
15:8 UMASK (Unit Mask)
Unit mask regi ster set to 0 to enab le all count options.
16 USER
Controls the counting of events at  Privilege levels of 1, 2, and 3.
17 OS
Controls the counting of events at Privilege level of 0.
18 E
Occurrence/Duration Mode Select:1 = Occurrence.
0 = Duration.
19 PC
Enabled the signaling of performance counter overflow via BP0 pin.
20 INT
Enables the signaling of counter overflow via input to APIC:1 = Enable.
0 = Disable.
22 ENABLE
Enables the counting of performa nce events in both counters:
1 = Enable.
23 INV
Inverts the result of the CMASK condition:1 = Inverted.
0 = Non-Inverted.
31:24 CMASK (Counter Mask)
Register Address: 187H, 391 PerfEvtSel1 (EVNTSEL1)
Performance Event Select for Counter 1 (R/W)7:0 Event Select
16 USER
17 OS
Controls the counting of events at Privilege level of 0.Table 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-505MODEL-SPECIFIC REGISTERS (MSRS)
18 E
Occurrence/Duratio n Mode Select:
1 = Occurrence.
19 PC
20 INT
Enables the signaling of counter overflow via input to APIC.1 = Enable.
23 INV
Inverts the result of the CMASK condition.
1 = Inverted.
Register Address: 1D9H, 473 DEBUGCTLMSR
Enables last branch, interr upt, and exception recording; taken branch breakpoints; the breakpoint reporting pins; and trace mes sages. 
This register can be written to using the WRMSR instruction, wh en operating at privilege level 0 or when in real-address mode.
0 Enable/Disable Last Branch Records
1B r a n c h  T r a p  F l a g2 Performance Monitoring/Break Point Pins
3 Performance Monitoring/Break Point Pins
4 Performance Monitoring/Break Point Pins5 Performance Monitoring/Break Point Pins
6 Enable/Disable Execution Trace Messages
31:7 Reserved.
Register Address: 1DBH, 475 LASTBRANCHFROMIP
32-bit register for recording the instruction pointers for the last  branch, interrupt, or exceptio n that the processor took pri or to a 
debug exception being generated.
Register Address: 1DCH, 476 LASTBRANCHTOIP
Register Address: 1DDH, 477 LASTINTFROMIP
Last INT from IP
Register Address: 1DEH, 478 LASTINTTOIP
Last INT to IP
Register Address: 200H, 512 MTRRphysBase0
Memory Type Range RegistersTable 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bi t Fields Bit Description2-506 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 269H, 617 MTRRfix4K_C8000Table 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-507MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 2FFH, 767 MTRRdefType
2:0 Default memory type10 Fixed MTRR enable
11 MTRR Enable
Register Address: 400H, 1024 MC0_CTL
Register Address: 401H, 1025 MC0_STATUS
15:0 MC_STATUS_MCACOD 
31:16 MC_STATUS_MSCOD 
57 MC_STATUS_DAM58 MC_STATUS_ADDRV 
59 MC_STATUS_MISCV 
60 MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is hardcoded to 1.)
61 MC_STATUS_UC 
62 MC_STATUS_O
63 MC_STATUS_V
Register Address: 402H, 1026 MC0_ADDR
Register Address: 403H, 1027 MC0_MISC
Defined in MCA architecture but not impl emented in the P6 family processors.
Register Address: 404H, 1028 MC1_CTLTable 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bi t Fields Bit Description2-508 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)
2.23 MSRS IN PENTIUM PROCESSORS
The following MSRs are defined for the Pentium proc essors. The P5_MC_ADDR, P5_MC_TYPE, and TSC MSRs 
(named IA32_P5_MC_ADDR, IA32_P5_MC_TYPE, and IA32 _TIME_STAMP_COUNTER in the Pentium 4 processor) 
are architectural; that is, code that accesses these regist ers will run on Pentium 4 and P6 family processors without 
generating exceptions (see Section 2.1, “Architectural  MSRs”). The CESR, CTR0, and CTR1 MSRs are unique to

generating exceptions (see Section 2.1, “Architectural  MSRs”). The CESR, CTR0, and CTR1 MSRs are unique to 
Pentium processors; code that accesses these registers will generate exceptions on Pentium 4 and P6 family 
processors.Register Address: 405H, 1029 MC1_STATUS
Bit defini tions same as MC0_STATUS.
Register Address: 406H, 1030 MC1_ADDR
Register Address: 407H, 1031 MC1_MISC
Defined in MCA architecture  but not implemented in th e P6 family processors.
Register Address: 408H, 1032 MC2_CTL
Register Address: 409H, 1033 MC2_STATUS
Register Address: 40AH, 1034 MC2_ADDR
Register Address: 40BH, 1035 MC2_MISC
Register Address: 40CH, 1036 MC4_CTL
Register Address: 40DH, 1037 MC4_STATUS
Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.
Register Address: 40EH, 1038 MC4_ADDR
Defined in MCA architectu re but not implemented in  P6 Family processors.
Register Address: 40FH, 1039 MC4_MISC
Register Address: 410H, 1040 MC3_CTL
Register Address: 411H, 1041 MC3_STATUS
Register Address: 412H, 1042 MC3_ADDR
Register Address: 413H, 1043 MC3_MISC
NOTES
1. Bit 0 of this register has been redefined several time s, and is no longer used in P6 family  processors.
2. The processor number feature may be disabled by setting bit 21  of the BBL_CR_CTL MSR (model-specific register address 119h) t o 
“1”. Once set, bit 21 of the BB L_CR_CTL may not be cleared. This bit is write-once. The processor number feature will be disabl ed 
until the processor is reset.
3. The Pentium III processor will prevent FSB frequency overclocki ng with a new shutdown  mechanism. If the FSB frequency selecte d 
is greater than the internal FSB frequency the processor will shutdown. If the FSB selected is less than the internal FSB frequ ency 
the BIOS may choose to use bit 11 to implement its own shutdown policy.Table 2-63.  MSRs in the P6 Family Processors  (Contd.)
Register Information / Bit Fields Bit DescriptionVol. 4 2-509MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-64.  MSRs in the Pentium Processor
Register Address: Hex, Decimal
Register Name
Register Information
See Section 16.10.2, “Pentium Processor Machine-Check Exception Handling.”
Register Address: 11H, 17 CESR
See Section 20.6.9.1, “Control and Event Select Register (CESR).”
Register Address: 12H, 18 CTR0
Section 20.6.9.3, “Events Counted.”
Register Address: 13H, 19 CTR1
Section 20.6.9.3, “Events Counted.”2-510 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -1INDEX
Numerics
0000 , Vol.1-B-41
128-bit
packed byte integers data type , Vol.1-4-9
packed double-precision floating-point
data type , Vol.1-4-9
packed doubleword integers data type , Vol.1-4-9
packed quadword integers data type , Vol.1-4-9
packed SIMD data types , Vol.1-4-8
packed single-precision floating-point
data type , Vol.1-4-9, Vol.1-10-5
packed word integers data type , Vol.1-4-9
MADD , Vol.2-5-201, Vol.2-5-219
MSUB , Vol.2-5-250, Vol.2-5-265
16-bit
address size , Vol.1-3-9
operand size , Vol.1-3-9
16-bit code, mixing with 32-bit code , Vol.3-22-1
286 processor , Vol.1-2-1
32-bit
32-bit code, mixing with 16-bit code , Vol.3-22-1
32-bit physical addressing
overview , Vol.3-3-6
36-bit physical addressing
64-bit
packed byte integers data type , Vol.1-4-8, Vol.1-9-3
packed doubleword integers data type , Vol.1-4-8
packed doubleword integers data types , Vol.1-9-3
packed word integers data type , Vol.1-4-8, Vol.1-9-3
sub-mode of IA-32e , Vol.1-3-1
address calculation , Vol.1-3-10
address size , Vol.1-3-19
address space , Vol.1-3-5
BOUND instruction , Vol.1-7-18
branch behavior , Vol.1-6-12
byte register limitation , Vol.1-3-13
call gates , Vol.3-5-14
CALL instruction , Vol.1-6-12, Vol.1-7-17
canonical address , Vol.1-3-10
CMPS instruction , Vol.1-7-20
CMPXCHG16B instruction , Vol.1-7-5
code segment descriptors , Vol.3-5-3, Vol.3-10-12
control and debug registers , Vol.2-2-12
control registers , Vol.3-2-13
CR8 register , Vol.3-2-13
D flag , Vol.3-5-4
data types , Vol.1-7-2
debug registers , Vol.3-2-7
DEC instruction , Vol.1-7-8
decimal arithmetic instructions , Vol.1-7-10
default operand and address sizes , Vol.1-3-2
default operand size , Vol.2-2-12
descriptors , Vol.3-5-3, Vol.3-5-5
direct memory-offset MOVs , Vol.2-2-11
DPL field , Vol.3-5-4
exception handling , Vol.3-6-19
exceptions , Vol.1-6-19
external interrupts , Vol.3-11-31
far pointer , Vol.1-4-7
fast system calls , Vol.3-5-22
feature list , Vol.1-2-20
GDTR register , Vol.1-3-6, Vol.3-2-12, Vol.3-2-13
general purpose encodings , Vol.1-B-18
GP faults, causes of , Vol.3-6-42
IDTR register , Vol.1-3-6, Vol.3-2-12
immediates , Vol.2-2-11
INC instruction , Vol.1-7-8
initialization process , Vol.3-2-8, Vol.3-10-11instruction pointer , Vol.1-3-10, Vol.1-3-18
instructions introduced , Vol.1-5-37
interrupt and trap gates , Vol.3-6-19
interrupt controller , Vol.3-11-31
interrupt descriptors , Vol.3-2-5
interrupt handling , Vol.3-6-19
interrupt stack table , Vol.3-6-22
interrupts , Vol.1-6-19
introduction , Vol.1-2-20, Vol.1-3-1, Vol.1-7-1, Vol.2-2-7
IRET instruction , Vol.1-7-18, Vol.3-6-21
I/O instructions , Vol.1-7-20
JCC instruction , Vol.1-6-12, Vol.1-7-17
JCXZ instruction , Vol.1-6-12, Vol.1-7-17
JMP instruction , Vol.1-6-12, Vol.1-7-17
L flag , Vol.3-3-12, Vol.3-5-4
LAHF instruction , Vol.1-7-22
LDTR register , Vol.1-3-6
legacy modes , Vol.1-2-20
LODS instruction , Vol.1-7-20
logical address translation , Vol.3-3-7
LOOP instruction , Vol.1-6-12, Vol.1-7-17
machine instructions , Vol.1-B-1
memory models , Vol.1-3-9
memory operands , Vol.1-3-21
MMX technology , Vol.1-9-2
MOV CRn , Vol.3-2-13, Vol.3-11-31
MOVS instruction , Vol.1-7-20
MOVSXD instruction , Vol.1-7-8
near pointer , Vol.1-4-7
null segment checking , Vol.3-5-6
operand addressing , Vol.1-3-24
operand size , Vol.1-3-19
operands , Vol.1-3-21
paging , Vol.3-2-6
POPF instruction , Vol.1-7-22
promoted instructions , Vol.1-3-2
PUSHA, PUSHAD, POPA, POPAD , Vol.1-7-7
PUSHF instruction , Vol.1-7-22
PUSHFD instruction , Vol.1-7-22
reading counters , Vol.3-2-27
reading & writing MSRs , Vol.3-2-27
real address mode , Vol.1-3-9
reg (reg) field , Vol.1-B-4
register operands , Vol.1-3-21
registers and mode changes , Vol.3-10-12
REP prefix , Vol.1-7-20
RET instruction , Vol.1-6-12, Vol.1-7-17
REX prefix , Vol.1-3-2, Vol.1-3-12, Vol.1-3-19
REX prefixes , Vol.2-2-7, Vol.1-B-2
RFLAGS register , Vol.1-7-22, Vol.3-2-11
RIP register , Vol.1-3-10
RIP-relative addressing , Vol.1-3-18, Vol.1-3-24, Vol.2-2-12
SAHF instruction , Vol.1-7-22
SCAS instruction , Vol.1-7-20
segment descriptor tables , Vol.3-3-16, Vol.3-5-3
segment loading instructions , Vol.3-3-9
segment registers , Vol.1-3-15
segmentation , Vol.1-3-9, Vol.1-3-22
segments , Vol.3-3-5
SIMD encodings , Vol.1-B-37
special instruction encodings , Vol.1-B-61
SSE extensions , Vol.1-10-3
SSE2 extensions , Vol.1-11-3
SSE3 extensions , Vol.1-12-1
SSSE3 extensions , Vol.1-12-1
stack behavior , Vol.1-6-4
stack switching , Vol.3-5-19, Vol.3-6-21
STOS instruction , Vol.1-7-20
summary table notation , Vol.2-3-8
SYSCALL and SYSRET , Vol.3-2-7, Vol.3-5-22
SYSENTER and SYSEXIT , Vol.3-5-21
system registers , Vol.3-2-7INDEX
Index-2 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4task gate , Vol.3-8-19
task priority , Vol.3-2-20, Vol.3-11-31
task register , Vol.3-2-13
TR register , Vol.1-3-6
TSS
stack pointers , Vol.3-8-19
x87 FPU , Vol.1-8-1
See also: IA-32e mode, compatibility mode
8086
emulation, support for , Vol.3-21-1
processor, exceptions and interrupts , Vol.3-21-6
8086 processor , Vol.1-2-1
8086/8088 processor , Vol.1-23-7
8087 math coprocessor , Vol.1-23-7
8088 processor , Vol.1-2-1
82489DX , Vol.1-23-27, Vol.1-23-28
Local APIC and I/O APICs , Vol.3-11-4
A
A20M# signal , Vol.3-21-2, Vol.1-23-34, Vol.3-24-4
AAA instruction , Vol.1-7-9, Vol.2-3-19, Vol.2-3-21
AAD instruction , Vol.1-7-10, Vol.2-3-21
AAM instruction , Vol.1-7-10, Vol.2-3-23
AAS instruction , Vol.1-7-10, Vol.2-3-25
Aborts
description of , Vol.3-6-5
restarting a program or task after , Vol.3-6-6
AC (alignment check) flag, EFLAGS register , Vol.1-3-17, Vol.3-2-11, 
Vol.3-6-50, Vol.1-23-6
Access rights
checking , Vol.3-2-24
checking caller privileges , Vol.3-5-26
description of , Vol.3-5-24
invalid values , Vol.1-23-19
Access rights, segment descriptor , Vol.1-6-8, Vol.1-6-13
ADC instruction , Vol.1-7-8, Vol.2-3-27, Vol.2-3-610, Vol.3-9-4
ADD instruction , Vol.1-7-8, Vol.2-3-19, Vol.2-3-32, Vol.2-3-317, 
Vol.2-3-610, Vol.3-9-4

A
Aborts
ADDPD instruction , Vol.1-11-6, Vol.2-3-34
ADDPS- Add Packed Single-Precision Floating-Point Values , Vol.2-3-37
ADDPS instruction , Vol.1-10-8
Address
size prefix , Vol.3-22-1
space, of task , Vol.3-8-16
Address size attribute
code segment , Vol.1-3-18
description of , Vol.1-3-18
of stack , Vol.1-6-3
Address sizes , Vol.1-3-9
Address space
64-bit mode , Vol.1-3-1, Vol.1-3-5
compatibility mode , Vol.1-3-1
overview of , Vol.1-3-2
physical , Vol.1-3-6
Address translation
in real-address mode , Vol.3-21-2
logical to linear , Vol.3-3-7
Addressing methods
RIP-relative , Vol.2-2-12
Addressing modes
assembler , Vol.1-3-24
base, Vol.1-3-22, Vol.1-3-23, Vol.1-3-24
base plus displacement , Vol.1-3-23
base plus index plus displacement , Vol.1-3-23
base plus index time scale plus displacement , Vol.1-3-23, Vol.1-3-24
displacement , Vol.1-3-22, Vol.1-3-23, Vol.1-3-24
effective address , Vol.1-3-23
immediate operands , Vol.1-3-20
index , Vol.1-3-22, Vol.1-3-24index times scale plus displacement , Vol.1-3-23
register operands , Vol.1-3-20, Vol.1-3-21
RIP-relative addressing , Vol.1-3-18, Vol.1-3-24
scale factor , Vol.1-3-22, Vol.1-3-24
specifying a segment selector , Vol.1-3-21
specifying an offset , Vol.1-3-22
specifying offsets in 64-bit mode , Vol.1-3-24
Addressing, segments , Vol.2-1-7, Vol.3-1-8, Vol.4-1-6
ADDSD- Add Scalar Double-Precision Floating-Point Values , Vol.2-3-40
ADDSD instruction , Vol.1-11-6, Vol.2-3-40
ADDSS- Add Scalar Single-Precision Floating-Point Values , Vol.2-3-42
ADDSS instruction , Vol.1-10-8
ADDSUBPD instruction , Vol.1-5-23, Vol.1-12-4, Vol.2-3-44
ADDSUBPS instruction , Vol.1-5-23, Vol.1-12-4, Vol.2-3-46
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag , 
Vol.2-3-49
Advanced media boost , Vol.1-2-11
Advanced power management
C-state and Sub C-state , Vol.3-15-35
MWAIT extensions , Vol.3-15-35
See also: thermal monitoring
Advanced programmable interrupt contro ller (see I/O APIC or Local APIC)
advanced smart cache , Vol.1-2-10
AESDEC128KL—Perform Ten Rounds of AES Decryption Flow Using 
128-Bit Key , Vol.2-3-53
AESDEC256KL—Perform 14 Rounds of AE S Decryption Flow Using 256-Bit 
Key, Vol.2-3-55
AESDECLAST—Perform Last Round of an AES Decryption Flow , Vol.2-3-57
AESDEC—Perform One Round of an AES Decryption Flow , Vol.2-3-51
AESDECWIDE128KL—Perform Ten Rounds of AES Decryption Flow on 8 
Blocks with 128-Bit Key , Vol.2-3-59
AESDECWIDE256KL—Perform 14 Rounds of AES Decryption Flow on 8 
Blocks with 256-Bit Key , Vol.2-3-61
AESENC128KL—Perform Ten Rounds of  AES Encryption Flow Using 
128-Bit Key , Vol.2-3-65
AESENC256KL—Perform 14 Rounds of AE S Encryption Flow Using 256-Bit 
Key, Vol.2-3-67
AESENCLAST—Perform Last Round of an AES Encryption Flow , Vol.2-3-69
AESENC—Perform One Round of an AES Encryption Flow , Vol.2-3-63
AESENCWIDE128KL—Perform Ten Rounds of AES Encryption Flow on 8 
Blocks with 128-Bit Key , Vol.2-3-71
AESENCWIDE256KL—Perform 14 Rounds of AES Encryption Flow on 8 
Blocks with 256-Bit Key , Vol.2-3-73
AESIMC—Perform the AES InvMixColumn Transformation , Vol.2-3-75
AESKEYGENASSIST - AES Round Key Generation Assist , Vol.2-3-76
AF (adjust) flag, EFLAGS register , Vol.1-3-16, Vol.1-A-1
AH register , Vol.1-3-12
AL register , Vol.1-3-12
Alignment
check exception , Vol.3-2-11, Vol.3-6-50, Vol.1-23-11, Vol.1-23-21
checking , Vol.3-5-27
words, doublewords, quadwords , Vol.1-4-2
AM (alignment mask) flag
CR0 control register , Vol.3-2-15, Vol.1-23-18
AND instruction , Vol.1-7-10, Vol.2-3-78, Vol.2-3-610, Vol.3-9-4
ANDNPD instruction , Vol.1-11-7
ANDNPS- Bitwise Logical AND NOT of Packed Single Precision 
Floating-Point Values , Vol.2-3-90
ANDNPS instruction , Vol.1-10-9
ANDPD- Bitwise Logical AND of Packed  Double Precision Floating-Point 
Values , Vol.2-3-81
ANDPD instruction , Vol.1-11-7, Vol.2-3-80
ANDPS- Bitwise Logical AND of Packed Single Precision Floating-Point 
Values , Vol.2-3-84
ANDPS instruction , Vol.1-10-9
APIC, Vol.3-11-40, Vol.3-11-41
APIC bus
arbitration mechanism and protocol , Vol.3-11-26, Vol.3-11-33
bus message format , Vol.3-11-34, Vol.3-11-47
diagram of , Vol.3-11-2, Vol.3-11-3
EOI message format , Vol.3-11-15, Vol.3-11-47Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -3INDEX
nonfocused lowest priority message , Vol.3-11-49
short message format , Vol.3-11-48
SMI message , Vol.4-32-2
status cycles , Vol.3-11-50
structure of , Vol.3-11-3
See also
local APIC
APIC flag, CPUID instruction , Vol.3-11-7
APIC ID , Vol.3-11-40, Vol.3-11-44, Vol.3-11-46
APIC (see I/O APIC or Local APIC)Arctangent, x87 FPU operation
, Vol.1-8-20, Vol.2-3-415
Arithmetic instructions, x87 FPU , Vol.1-8-25
ARPL instruction , Vol.2-3-93, Vol.3-2-24, Vol.3-5-27
not supported in 64-bit mode , Vol.3-2-24
Assembler, addressing modes , Vol.1-3-24
Asymmetric processing model , Vol.1-12-1
Atomic operations
automatic bus locking , Vol.3-9-3
effects of a locked operation on internal processor caches , Vol.3-9-6
guaranteed, description of , Vol.3-9-2
overview of , Vol.3-9-1, Vol.3-9-3
software-controlled bus locking , Vol.3-9-4
At-retirement
counting , Vol.3-20-101, Vol.3-20-117
events , Vol.3-20-101, Vol.3-20-106, Vol.3-20-107, Vol.3-20-117, 
Vol.3-20-121
authenticated code execution mode , Vol.1-6-3
Auto HALT restart
field, SMM , Vol.4-32-14
SMM, Vol.4-32-14
Automatic bus locking , Vol.3-9-3
Automatic thermal monitoring mechanism , Vol.3-15-36
AX register , Vol.1-3-12
B
B (busy) flag
TSS descriptor , Vol.3-8-5, Vol.3-8-11, Vol.3-8-16
B (default size) flag, segment descriptor , Vol.1-3-18
B (default stack size) flag
segment descriptor , Vol.3-22-1, Vol.1-23-33
B0-B3 (BP condition detected) flags
DR6 register , Vol.3-18-4
Backlink (see Previous task link)Base address fields, segment descriptor
, Vol.3-3-10
Base (operand addressing) , Vol.1-3-22, Vol.1-3-23, Vol.1-3-24, Vol.2-2-3
Basic execution environment , Vol.1-3-2
Basic programming environment , Vol.1-7-1
B-bit, x87 FPU status word , Vol.1-8-5
BCD integers
packed , Vol.1-4-10, Vol.2-3-317, Vol.2-3-319, Vol.2-3-365, 
Vol.2-3-367
relationship to status flags , Vol.1-3-17
unpacked , Vol.1-4-9, Vol.1-7-9, Vol.2-3-19, Vol.2-3-21, Vol.2-3-23, 
Vol.2-3-25
x87 FPU encoding , Vol.1-4-10
BD (debug register access detected) flag, DR6 register , Vol.3-18-11
BEXTR—Bit Field Extract , Vol.2-3-95
BH register , Vol.1-3-12
Bias value
numeric overflow , Vol.1-8-29
numeric underflow , Vol.1-8-30
Biased exponent , Vol.1-4-13
Biasing constant, for floating-point numbers , Vol.1-4-6
Binary numbers , Vol.1-1-7, Vol.2-1-7, Vol.3-1-8, Vol.4-1-6
Binary-coded decimal (see BCD)BINIT# signal
, Vol.3-2-26
BIOS role in microcode updates , Vol.3-10-38
Bit field , Vol.1-4-7
Bit order , Vol.1-1-6, Vol.2-1-5, Vol.3-1-7, Vol.4-1-5
BL register , Vol.1-3-12BLENDPD — Blend Packed Double Precision Floating-Point Values , 
Vol.2-3-96
BLENDPS — Blend Packed Single Precision Floating-Point Values , 
Vol.2-3-98
BLSI-Extract Lowest Set Isolated Bit , Vol.2-3-105
BLSMSK - Get Mask Up to Lowest Set Bit , Vol.2-3-106
BLSR —Reset Lowest Set Bit , Vol.2-3-107
BNDCL—Check Lower Bound , Vol.2-3-108
BNDCU/BNDCN—Check Upper Bound , Vol.2-3-110
BNDLDX—Load Extended Bounds Using Address Translation , Vol.2-3-112
BNDMK—Make Bounds , Vol.2-3-115
BNDMOV—Move Bounds , Vol.2-3-117
BNDSTX—Store Extended Bounds Using Address Translation , Vol.2-3-120
bootstrap processor , Vol.1-6-16, Vol.1-6-21, Vol.1-6-29, Vol.1-6-30
BOUND instruction , Vol.1-6-18, Vol.1-7-18, Vol.1-7-23, Vol.2-3-123, 
Vol.3-2-5, Vol.3-6-4, Vol.3-6-30
BOUND range exceeded exception (#BR) , Vol.1-6-19, Vol.2-3-123, 
Vol.3-6-30
BOUND—Check Array Index Against Bounds , Vol.2-3-123
BP register , Vol.1-3-12
BP0#, BP1#, BP2#, and BP3# pins , Vol.3-18-39, Vol.3-18-41
Branch
control transfer instructions , Vol.1-7-14
hints, Vol.1-11-13
on EFLAGS register status flags , Vol.1-7-15, Vol.1-8-6
on x87 FPU condition codes , Vol.1-8-6, Vol.1-8-20
prediction , Vol.1-2-8
Branch hints , Vol.2-2-2
Branch record
branch trace message , Vol.3-18-15
IA-32e mode , Vol.3-18-23
saving , Vol.3-18-17, Vol.3-18-27, Vol.3-18-28, Vol.3-18-36
saving as a branch trace message , Vol.3-18-15
structure , Vol.3-18-37
structure of in BTS buffer , Vol.3-18-21
Branch trace message (see BTM)Branch trace store (see BTS)Brand information
, Vol.2-3-254
processor brand index , Vol.2-3-256
processor brand string , Vol.2-3-254
Breakpoint exception (#BP) , Vol.3-6-4, Vol.3-6-28, Vol.3-18-11
Breakpoints
data breakpoint , Vol.3-18-6
data breakpoint exception conditions , Vol.3-18-10
description of , Vol.3-18-1
DR0-DR3 debug registers , Vol.3-18-4
example , Vol.3-18-6
exception , Vol.3-6-28
field recognition , Vol.3-18-6, Vol.3-18-7
general-detect exception condition , Vol.3-18-10
instruction breakpoint , Vol.3-18-6
instruction breakpoint exception condition , Vol.3-18-9
I/O breakpoint exception conditions , Vol.3-18-10
LEN0 - LEN3 (Length) fields
DR7 register , Vol.3-18-6
R/W0-R/W3 (read/write) fields

DR7 register , Vol.3-18-5
single-step exception condition , Vol.3-18-11
task-switch exception condition , Vol.3-18-11
BS (single step) flag, DR6 register , Vol.3-18-4
BSF instruction , Vol.1-7-14, Vol.2-3-125
BSP flag, IA32_APIC_BASE MSR , Vol.3-11-8
BSR instruction , Vol.1-7-14, Vol.2-3-127
BSWAP instruction , Vol.1-7-4, Vol.2-3-129, Vol.1-23-4
BT instruction , Vol.1-3-15, Vol.1-3-16, Vol.1-7-14, Vol.2-3-130
BT (task switch) flag, DR6 register , Vol.3-18-4, Vol.3-18-11
BTC instruction , Vol.1-3-15, Vol.1-3-16, Vol.1-7-14, Vol.2-3-132, 
BTF (single-step on branches) flag
DEBUGCTLMSR MSR , Vol.3-18-41
BTMs (branch trace messages)
description of , Vol.3-18-15INDEX
Index-4 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4enabling , Vol.3-18-13, Vol.3-18-25, Vol.3-18-26, Vol.3-18-36, 
Vol.3-18-38, Vol.3-18-39
TR (trace message enable) flag
MSR_DEBUGCTLA MSR , Vol.3-18-36
MSR_DEBUGCTLB MSR , Vol.3-18-13, Vol.3-18-38, Vol.3-18-39
BTR instruction , Vol.1-3-15, Vol.1-3-16, Vol.1-7-14, Vol.2-3-134, 
BTS buffer
description of , Vol.3-18-20
introduction to , Vol.3-18-12, Vol.3-18-15
records in , Vol.3-18-21
setting up , Vol.3-18-25
structure of , Vol.3-18-21, Vol.3-18-23, Vol.3-20-21
BTS instruction , Vol.1-3-15, Vol.1-3-16, Vol.1-7-14, Vol.2-3-136, 
BTS (branch trace store) facilities
availability of , Vol.3-18-35
BTS_UNAVAILABLE flag,
IA32_MISC_ENABLE MSR , Vol.3-18-20, Vol.4-2-462
introduction to , Vol.3-18-12
setting up BTS buffer , Vol.3-18-25
writing an interrupt service routine for , Vol.3-18-26
BTS_UNAVAILABLE , Vol.3-18-20
Built-in self-test (BIST)
description of , Vol.3-10-1
performing , Vol.3-10-5
Bus
errors detected with MCA , Vol.3-16-27
hold, Vol.1-23-35
locking , Vol.3-9-3, Vol.1-23-35
BX register , Vol.1-3-12
Byte, Vol.1-4-1
Byte order , Vol.1-1-6, Vol.2-1-5, Vol.3-1-7, Vol.4-1-5
BZHI —Zero High Bits Starting with Specified Bit Position , Vol.2-3-138
C
C (conforming) flag, segment descriptor , Vol.3-5-11
C1 flag, x87 FPU status word , Vol.1-8-4, Vol.1-8-26, Vol.1-8-29, 
Vol.1-8-30, Vol.1-23-8, Vol.1-23-14
C2 flag, x87 FPU status word , Vol.1-8-5, Vol.1-23-8
Cache and TLB information , Vol.2-3-247
Cache control , Vol.3-12-20
adaptive mode, L1 Data Cache , Vol.3-12-18
cache management instructions , Vol.3-12-17, Vol.3-12-18
cache mechanisms in IA-32 processors , Vol.1-23-30
caching terminology , Vol.3-12-5
CD flag, CR0 control register , Vol.3-12-10, Vol.1-23-19
choosing a memory type , Vol.3-12-8
CPUID feature flag , Vol.3-12-18
flags and fields , Vol.3-12-10
flushing TLBs , Vol.3-12-19
G (global) flag
page-directory entries , Vol.3-12-13
page-table entries , Vol.3-12-13
internal caches , Vol.3-12-1
MemTypeGet() function , Vol.3-12-29
MemTypeSet() function , Vol.3-12-31
MESI protocol , Vol.3-12-5, Vol.3-12-9
methods of caching available , Vol.3-12-6
MTRR initialization , Vol.3-12-29
MTRR precedences , Vol.3-12-28
MTRRs, description of , Vol.3-12-20
multiple-processor considerations , Vol.3-12-32
NW flag, CR0 control register , Vol.3-12-13, Vol.1-23-19
operating modes , Vol.3-12-12
overview of , Vol.3-12-1
page attribute table (PAT) , Vol.3-12-33
PCD flag
CR3 control register , Vol.3-12-13
page-directory entries , Vol.3-12-13, Vol.3-12-33
page-table entries , Vol.3-12-13, Vol.3-12-33PGE (page global enable) flag, CR4 control register , Vol.3-12-13
precedence of controls , Vol.3-12-13
preventing caching , Vol.3-12-16
protocol , Vol.3-12-9
PWT flag
page-directory entries , Vol.3-12-33
page-table entries , Vol.3-12-33
remapping memory types , Vol.3-12-29
setting up memory ranges with MTRRs , Vol.3-12-22
shared mode, L1 Data Cache , Vol.3-12-18
variable-range MTRRs , Vol.3-12-23, Vol.3-12-25
Cache Inclusiveness , Vol.2-3-219
Caches , Vol.3-2-7
cache hit , Vol.3-12-5
cache line , Vol.3-12-5
cache line fill , Vol.3-12-5
cache write hit , Vol.3-12-5
description of , Vol.3-12-1
enabling , Vol.3-10-7
management, instructions , Vol.3-2-25, Vol.3-12-17
Caches, invalidating (flushing) , Vol.2-3-532, Vol.1-6-3
cache, smart , Vol.1-2-4
Caching
cache control protocol , Vol.3-12-9
cache management instructions , Vol.3-12-17
implicit caching , Vol.3-12-19
L1 (level 1) cache , Vol.3-12-4
L2 (level 2) cache , Vol.3-12-4
L3 (level 3) cache , Vol.3-12-4
self-modifying code, effect on , Vol.3-12-18, Vol.1-23-30
snooping , Vol.3-12-6
store buffer , Vol.3-12-20
TLBs , Vol.3-12-5
UC (strong uncacheable) memory type , Vol.3-12-6
UC- (uncacheable) memory type , Vol.3-12-6
WB (write back) memory type , Vol.3-12-7
WC (write combining) memory type , Vol.3-12-7
WP (write protected) memory type , Vol.3-12-7
write-back caching , Vol.3-12-6
WT (write through) memory type , Vol.3-12-7
Call gate , Vol.1-6-8
Call gates
16-bit, interlevel return from , Vol.1-23-33
accessing a code segment through , Vol.3-5-15
description of , Vol.3-5-13
for 16-bit and 32-bit code modules , Vol.3-22-1
IA-32e mode , Vol.3-5-14
introduction to , Vol.3-2-4
mechanism , Vol.3-5-15
privilege level checking rules , Vol.3-5-16
CALL instruction , Vol.1-3-18, Vol.1-6-3, Vol.1-6-4, Vol.1-6-8, Vol.1-7-15, 
Vol.1-7-22, Vol.2-3-139, Vol.3-2-5, Vol.3-3-8, Vol.3-5-10, Vol.3-5-15, Vol.3-5-20, Vol.3-8-2, Vol.3-8-9, Vol.3-8-11, Vol.3-22-5
Caller access privileges, checking , Vol.3-5-26
Calls
16 and 32-bit code segments , Vol.3-22-3
controlling operand-size attribute , Vol.3-22-5
returning from , Vol.3-5-20
Calls (see Procedure calls)Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -5INDEX
Canonical address , Vol.1-3-10
GETSEC , Vol.1-6-3
Capability MSRs
See VMX capability MSRs
Catastrophic shutdown detector
Thermal monitoring
catastrophic shutdown detector , Vol.3-15-37
catastrophic shutdown detector , Vol.3-15-36
CBW instruction , Vol.1-7-7, Vol.2-3-156
CC0 and CC1 (counter control) fields, CESR MSR (Pentium processor) , 
Vol.3-20-137
CD (cache disable) flag, CR0 control register , Vol.3-2-15, Vol.3-10-7, 
Vol.3-12-10, Vol.3-12-12, Vol.3-12-13, Vol.3-12-16, Vol.3-12-32, Vol.1-23-18, Vol.1-23-19, Vol.1-23-30
CDQ instruction , Vol.1-7-7, Vol.2-3-316
CDQE instruction , Vol.2-3-156
Celeron processor
description of , Vol.1-2-2
CESR (control and event select) MSR (Pentium processor) , Vol.3-20-136, 
CF (carry) flag, EFLAGS register , Vol.1-3-16, Vol.1-A-1, Vol.2-3-32, 
Vol.2-3-130, Vol.2-3-132, Vol.2-3-134, Vol.2-3-136, Vol.2-3-158, Vol.2-3-174, Vol.2-3-321, Vol.2-3-502, Vol.2-3-507, Vol.2-4-146, Vol.2-4-528, Vol.2-4-602, Vol.2-4-628, Vol.2-4-631, Vol.2-4-674
CH register , Vol.1-3-12
CL register , Vol.1-3-12
CLC instruction , Vol.1-3-16, Vol.1-7-21, Vol.2-3-158
CLD instruction , Vol.1-3-17, Vol.1-7-21, Vol.2-3-159
CLFLSH feature flag, CPUID instruction , Vol.3-10-8
CLFLUSH instruction , Vol.1-11-12, Vol.2-3-162, Vol.2-3-164, Vol.3-2-16, 
Vol.3-10-8, Vol.3-12-17
CPUID flag , Vol.2-3-246
CLI instruction , Vol.1-19-4, Vol.2-3-166, Vol.3-6-7
Clocks
counting processor clocks , Vol.3-20-138
Hyper-Threading Technology , Vol.3-20-138
nominal CPI , Vol.3-20-138
non-halted clockticks , Vol.3-20-138
non-halted CPI , Vol.3-20-138
non-sleep Clockticks , Vol.3-20-138
time stamp counter , Vol.3-20-138
CLTS instruction , Vol.2-3-170, Vol.3-2-24, Vol.3-5-24, Vol.3-26-2, 
Vol.3-26-7
Cluster model, local APIC , Vol.3-11-24
CMC instruction , Vol.1-3-16, Vol.1-7-21, Vol.2-3-174
CMOVcc flag , Vol.2-3-246
CMOVcc instructions , Vol.1-7-3, Vol.1-7-4, Vol.2-3-175, Vol.1-23-4
CMP instruction , Vol.1-7-8, Vol.2-3-179
CMPPD- Compare Packed Double-Precision Floating-Point Values , 
Vol.2-3-181
CMPPD instruction , Vol.1-11-7
CMPPS- Compare Packed Single-Precision Floating-Point Values , 
Vol.2-3-188
CMPPS instruction , Vol.1-10-9
CMPS instruction , Vol.1-3-17, Vol.1-7-18, Vol.2-3-195, Vol.2-4-555
CMPSB instruction , Vol.2-3-195
CMPSD- Compare Scalar Double-P recision Floating-Point Values , 
Vol.2-3-199
CMPSD instruction , Vol.1-11-7, Vol.2-3-195
CMPSQ instruction , Vol.2-3-195
CMPSS- Compare Scalar Single-Precision Floating-Point Values , 
Vol.2-3-203
CMPSS instruction , Vol.1-10-9
CMPSW instruction , Vol.2-3-195
CMPXCHG instruction , Vol.1-7-4, Vol.2-3-208, Vol.2-3-610, Vol.3-9-4, 
Vol.1-23-4
CMPXCHG16B instruction , Vol.1-7-5, Vol.2-3-210
CPUID bit , Vol.2-3-244
CMPXCHG8B instruction , Vol.1-7-4, Vol.2-3-210, Vol.3-9-4, Vol.1-23-5
CPUID flag , Vol.2-3-246Code modules
16 bit vs. 32 bit , Vol.3-22-1
mixing 16-bit and 32-bit code , Vol.3-22-1
sharing data, mixed-size code segs , Vol.3-22-3
transferring control, mixed-size code segs , Vol.3-22-3
Code segment , Vol.1-3-14

Code segments
accessing data in , Vol.3-5-9
accessing through a call gate , Vol.3-5-15
description of , Vol.3-3-12
descriptor format , Vol.3-5-2
descriptor layout , Vol.3-5-2
direct calls or jumps to , Vol.3-5-10
paging of , Vol.3-2-6
pointer size , Vol.3-22-4
privilege level checks
transferring control between code segs , Vol.3-5-10
COMISD- Compare Scalar Ordered Double-Precision Floating-Point Values 
and Set EFLAGS , Vol.2-3-213
COMISD instruction , Vol.1-11-7
COMISS- Compare Scalar Ordered Single-Precision Floating-Point Values 
and Set EFLAGS , Vol.2-3-215
COMISS instruction , Vol.1-10-9
Compare
compare and exchange , Vol.1-7-4
integers , Vol.1-7-8
real numbers, x87 FPU , Vol.1-8-19
strings , Vol.1-7-18
IA-32 architecture , Vol.1-23-1
software , Vol.3-1-7, Vol.4-1-5
Compatibility mode
address space , Vol.1-3-1
branch functions , Vol.1-6-12
call gate descriptors , Vol.1-6-12
code segment descriptor , Vol.3-5-3
code segment descriptors , Vol.3-10-12
CS.L and CS.D , Vol.3-10-12
debug registers , Vol.3-2-25
EFLAGS register , Vol.3-2-11
exception handling , Vol.3-2-5
gates , Vol.3-2-4
GDTR register , Vol.3-2-12, Vol.3-2-13
global and local descriptor tables , Vol.3-2-4
IDTR register , Vol.3-2-12
interrupt handling , Vol.3-2-5
introduction , Vol.1-2-20, Vol.1-3-1, Vol.2-2-7
memory management , Vol.3-2-6
operation , Vol.3-10-12
see 64-bit modesegment loading instructions
, Vol.3-3-9
segmentation , Vol.1-3-22
summary table notation , Vol.2-3-9
switching to , Vol.3-10-12
SYSCALL and SYSRET , Vol.3-5-22
system flags , Vol.3-2-11
system registers , Vol.3-2-7
See also: 64-bit mode, IA-32e modeSee also: IA-32e mode, 64-bit mode
Compatibility, software
, Vol.1-1-6, Vol.2-1-6INDEX
Index-6 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4Condition code flags, EFLAGS register , Vol.2-3-175
Condition code flags, x87 FPU status word
branching on , Vol.1-8-6
compatibility information , Vol.1-23-8
conditional moves on , Vol.1-8-6
description of , Vol.1-8-4
flags affected by instructions , Vol.2-3-14
interpretation of , Vol.1-8-5
setting , Vol.2-3-451, Vol.2-3-453, Vol.2-3-455
use of , Vol.1-8-19
Conditional jump , Vol.2-3-548
Conditional moves, x87 FPU condition codes , Vol.1-8-6
Conforming code segment , Vol.2-3-582
Conforming code segments
accessing , Vol.3-5-12
C (conforming) flag , Vol.3-5-11
description of , Vol.3-3-13
Constants (floating point) , Vol.1-8-17
Constants (floating point), loading , Vol.2-3-405
Context, task (see Task state)Control registers
, Vol.1-3-5, Vol.3-2-13
CR0, Vol.3-2-13
CR1 (reserved) , Vol.3-2-13
CR2, Vol.3-2-13
CR3 (PDBR) , Vol.3-2-6, Vol.3-2-13
CR4, Vol.3-2-13
description of , Vol.3-2-13
introduction to , Vol.3-2-6
overview of , Vol.1-3-4
Control registers, moving values to and from , Vol.2-4-39
Coprocessor segment
overrun exception , Vol.3-6-35, Vol.1-23-12
Core microarchitecture , Vol.1-2-10, Vol.1-2-12, Vol.1-2-13
core microarchitecture , Vol.1-2-10, Vol.1-2-12
Core Solo and Core Duo , Vol.1-2-4
Cosine, x87 FPU operation , Vol.1-8-20, Vol.2-3-381, Vol.2-3-433
Counter mask field
PerfEvtSel0 and PerfEvtSel1 MS Rs (P6 family processors) , Vol.3-20-5, 
Vol.3-20-135
CPL, Vol.2-3-166, Vol.2-5-152
description of , Vol.3-5-7
field, CS segment selector , Vol.3-5-2
CPUID instruction , Vol.2-3-217, Vol.2-3-246
36-bit page size extension , Vol.2-3-246
APIC on-chip , Vol.2-3-246
availability , Vol.1-23-5
basic CPUID information , Vol.2-3-218
cache and TLB characteristics , Vol.2-3-218
CLFLUSH flag , Vol.1-11-12, Vol.2-3-246
CLFLUSH instruction cache line size , Vol.2-3-242
CMOVcc feature flag , Vol.1-7-3
CMPXCHG16B flag , Vol.2-3-244
CMPXCHG8B flag , Vol.2-3-246
control register flags , Vol.3-2-20
CPL qualified debug store , Vol.2-3-243
debug extensions, CR4.DE , Vol.2-3-246
debug store supported , Vol.2-3-247
detecting features , Vol.1-23-2
determine support for , Vol.1-3-17
deterministic cache parameters leaf , Vol.2-3-218, Vol.2-3-221, 
Vol.2-3-223, Vol.2-3-224, Vol.2-3-225, Vol.2-3-226, Vol.2-3-227, Vol.2-3-228, Vol.2-3-229, Vol.2-3-230, Vol.2-3-231, Vol.2-3-232, Vol.2-3-237
earlier processors , Vol.1-20-1
extended function information , Vol.2-3-238
feature information , Vol.2-3-245
FPU on-chip , Vol.2-3-246
FSAVE flag , Vol.2-3-247
FXRSTOR flag , Vol.2-3-247
FXSAVE-FXRSTOR flag , Vol.1-10-14
IA-32e mode available , Vol.2-3-239input limits for EAX , Vol.2-3-240
L1 Context ID , Vol.2-3-244
local APIC physical ID , Vol.2-3-242
machine check architecture , Vol.2-3-246
machine check exception , Vol.2-3-246
memory type range registers , Vol.2-3-246
MMX feature flag , Vol.1-9-8
MONITOR feature information , Vol.2-3-251
MONITOR/MWAIT flag , Vol.2-3-243
MONITOR/MWAIT leaf , Vol.2-3-219, Vol.2-3-220, Vol.2-3-224, 
Vol.2-3-225, Vol.2-3-226, Vol.2-3-232, Vol.2-3-237, Vol.2-3-238
MWAIT feature information , Vol.2-3-251
page attribute table , Vol.2-3-246
page size extension , Vol.2-3-246
performance monitoring features , Vol.2-3-252
physical address bits , Vol.2-3-240
physical address extension , Vol.2-3-246
power management , Vol.2-3-251, Vol.2-3-252, Vol.2-3-253, 
Vol.2-3-254
processor brand index , Vol.2-3-242, Vol.2-3-254
processor brand string , Vol.2-3-239, Vol.2-3-254
processor identification , Vol.1-20-1
processor serial number , Vol.2-3-218, Vol.2-3-246
processor type field , Vol.2-3-241
RDMSR flag , Vol.2-3-246
returned in EBX , Vol.2-3-242
returned in ECX & EDX , Vol.2-3-242
self snoop , Vol.2-3-247
serializing instructions , Vol.3-9-18
serializing use , Vol.1-19-5
SpeedStep technology , Vol.2-3-243
SS2 extensions flag , Vol.2-3-247
SSE extensions flag , Vol.2-3-247
SSE feature flag , Vol.1-10-1, Vol.1-10-6
SSE2 feature flag , Vol.1-11-1, Vol.1-12-5
SSE3 extensions flag , Vol.2-3-243
SSE3 feature flag , Vol.1-12-5
SSSE2 feature flag , Vol.1-12-9, Vol.1-12-19, Vol.1-12-24
SSSE3 extensions flag , Vol.2-3-243
summary of , Vol.1-7-23
syntax for data , Vol.3-1-9, Vol.4-1-7
SYSENTER flag , Vol.2-3-246
SYSEXIT flag , Vol.2-3-246
thermal management , Vol.2-3-251, Vol.2-3-252, Vol.2-3-253, 
thermal monitor , Vol.2-3-243, Vol.2-3-247
time stamp counter , Vol.2-3-246
using CPUID , Vol.2-3-217
vendor ID string , Vol.2-3-240
version information , Vol.2-3-218, Vol.2-3-251
virtual 8086 Mode flag , Vol.2-3-246
virtual address bits , Vol.2-3-240
WRMSR flag , Vol.2-3-246
CQO instruction , Vol.2-3-316
CR0 control register , Vol.2-4-647, Vol.1-23-8
state following processor reset , Vol.3-10-2
CR1 control register (reserved) , Vol.3-2-13
CR2 control register
CR3 control register (PDBR)
associated with a task , Vol.3-8-1, Vol.3-8-3
in TSS , Vol.3-8-4, Vol.3-8-17
loading during initialization , Vol.3-10-10
page directory base address , Vol.3-2-6
page table base address , Vol.3-2-5
CR4 control registerCombined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -7INDEX
enabling control functions , Vol.1-23-2
inclusion in IA-32 architecture , Vol.1-23-18
VMX usage of , Vol.3-24-3
CR8 register , Vol.3-2-7
64-bit mode , Vol.3-2-13
compatibility mode , Vol.3-2-13
task priority level bits , Vol.3-2-20
when available , Vol.3-2-13
CS register , Vol.1-3-13, Vol.1-3-14, Vol.2-3-140, Vol.2-3-517, 
Vol.2-3-539, Vol.2-3-554, Vol.2-4-36, Vol.2-4-393, Vol.1-23-11
state following initialization , Vol.3-10-5
C-state , Vol.3-15-35
CTI instruction , Vol.1-7-22
CTR0 and CTR1 (performance count ers) MSRs (Pentium processor) , 
Vol.3-20-136, Vol.3-20-138
Current privilege level (see CPL)
Current stack , Vol.1-6-1, Vol.1-6-3
CVTDQ2PD- Convert Packed Doubleword Integers to Packed 
Double-Precision Floating-Point Values , Vol.2-3-266
CVTDQ2PD instruction , Vol.1-11-10, Vol.2-3-263
CVTDQ2PS- Convert Packed Doubleword Integers to Packed 
Single-Precision Floating-Point Values , Vol.2-3-270
CVTDQ2PS instruction , Vol.1-11-10
CVTPD2DQ- Convert Packed Double-Precision Floating-Point Values to 
Packed Doubleword Integers , Vol.2-3-273
CVTPD2DQ instruction , Vol.1-11-10
CVTPD2PI instruction , Vol.1-11-10, Vol.2-3-277
CVTPD2PS- Convert Packed Double-Precision Floating-Point Values to 
Packed Single-Precision Floating-Point Values , Vol.2-3-278
CVTPD2PS instruction , Vol.1-11-9
CVTPI2PD instruction , Vol.1-11-10, Vol.2-3-282
CVTPI2PS instruction , Vol.1-10-11, Vol.2-3-283
CVTPS2DQ- Convert Packed Single Pr ecision Floating-Point Values to 
Packed Signed Doubleword Integer Values , Vol.2-3-284
CVTPS2DQ instruction , Vol.1-11-10

CVTPS2PD instruction , Vol.1-11-9
CVTPS2PI instruction , Vol.1-10-11, Vol.2-3-290
CVTSD2SI- Convert Scalar Double Precision Floating-Point Value to 
Doubleword Integer , Vol.2-3-291
CVTSD2SI instruction , Vol.1-11-10
CVTSD2SS instruction , Vol.1-11-9
CVTSI2SD instruction , Vol.1-11-10
CVTSI2SS- Convert Doubleword Integer to Scalar Single-Precision 
Floating-Point Value , Vol.2-3-297
CVTSI2SS instruction , Vol.1-10-11
CVTSS2SD- Convert Scalar Single-Precision Floating-Point Value to Scalar 
Double-Precision Floating-Point Value , Vol.2-3-299
CVTSS2SD instruction , Vol.1-11-9
CVTSS2SI- Convert Scalar Single-Precision Floating-Point Value to 
Doubleword Integer , Vol.2-3-301
CVTSS2SI instruction , Vol.1-10-11
CVTTPD2DQ- Convert with Truncation Packed Double-Precision 
Floating-Point Values to Packed Doubleword Integers , 
Vol.2-3-303
CVTTPD2DQ instruction , Vol.1-11-10
CVTTPD2PI instruction , Vol.1-11-10, Vol.2-3-307
CVTTPS2DQ- Convert with Truncation Packed Single-Precision 
Floating-Point Values to Packed Signed Doubleword Integer Values
, Vol.2-3-308
CVTTPS2DQ instruction , Vol.1-11-10
CVTTPS2PI instruction , Vol.1-10-11, Vol.2-3-311
CVTTSD2SI- Convert with Truncation Scalar Double-Precision 
Floating-Point Value to Signed Integer , Vol.2-3-312
CVTTSD2SI instruction , Vol.1-11-10
CVTTSS2SI- Convert with Truncation Scal ar Single-Precision Floating-Point 
Value to Integer , Vol.2-3-314
CVTTSS2SI instruction , Vol.1-10-11
CWD instruction , Vol.1-7-7, Vol.2-3-316CWDE instruction , Vol.1-7-7, Vol.2-3-156
CX register , Vol.1-3-12
C/C++ compiler intrinsics
compiler functional equivalents , Vol.1-C-1
composite , Vol.1-C-14
description of , Vol.2-3-12
lists of , Vol.1-C-1
simple , Vol.1-C-2
D
D (default operation size) flag
D (default operation size) flag, segment descriptor , Vol.2-4-397
D (default size) flag, segment descriptor , Vol.1-6-2, Vol.1-6-3
DAA instruction , Vol.1-7-9, Vol.2-3-317
DAS instruction , Vol.1-7-9, Vol.2-3-319
Data breakpoint exception conditions , Vol.3-18-10
Data movement instructions , Vol.1-7-2
Data pointer, x87 FPU , Vol.1-8-9
Data registers, x87 FPU , Vol.1-8-1
Data segment , Vol.1-3-14
Data segments
expand-down type , Vol.3-3-11
privilege level checking when accessing , Vol.3-5-8
Data types
128-bit packed SIMD , Vol.1-4-8
64-bit mode , Vol.1-7-2
64-bit packed SIMD , Vol.1-4-8
alignment , Vol.1-4-2
BCD integers , Vol.1-4-9, Vol.1-7-9
bit field , Vol.1-4-7
byte, Vol.1-4-1
doubleword , Vol.1-4-1
floating-point , Vol.1-4-4
fundamental , Vol.1-4-1
integers , Vol.1-4-3
numeric , Vol.1-4-2
operated on by GP instructions , Vol.1-7-1, Vol.1-7-2
operated on by MMX technology , Vol.1-9-3
operated on by SSE extensions , Vol.1-10-5
operated on by SSE2 extensions , Vol.1-11-3
operated on by x87 FPU , Vol.1-8-13
operated on in 64-bit mode , Vol.1-4-7
packed bytes , Vol.1-9-3
packed doublewords , Vol.1-9-3
packed SIMD , Vol.1-4-8
packed words , Vol.1-9-3
pointers , Vol.1-4-6
quadword , Vol.1-4-1, Vol.1-9-3
signed integers , Vol.1-4-4
strings , Vol.1-4-8
unsigned integers , Vol.1-4-3
word , Vol.1-4-1
DAZ (denormals-are-zeros) flag
MXCSR register , Vol.1-10-5
DE (debugging extensions) flag, CR4 control register , Vol.3-2-17, 
Vol.1-23-18, Vol.1-23-20
DE (denormal operand exception) flag
MXCSR register , Vol.1-11-15
x87 FPU status word , Vol.1-8-5, Vol.1-8-28
Debug exception (#DB) , Vol.3-6-7, Vol.3-6-25, Vol.3-8-5, Vol.3-18-7, 
Vol.3-18-14, Vol.3-18-42
Debug registers
64-bit mode , Vol.1-3-5
legacy modes , Vol.1-3-4
Debug registers, moving value to and from , Vol.2-4-42
Debug store (see DS)DEBUGCTLMSR MSR
, Vol.3-18-40, Vol.3-18-42, Vol.4-2-505INDEX
Index-8 Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4Debugging facilities
breakpoint exception (#BP) , Vol.3-18-1
debug exception (#DB) , Vol.3-18-1
DR6 debug status register , Vol.3-18-1
DR7 debug control register , Vol.3-18-1
exceptions , Vol.3-18-7
INT3 instruction , Vol.3-18-2
last branch, interrupt, and exception recording , Vol.3-18-2, 
Vol.3-18-12
masking debug exceptions , Vol.3-6-7
overview of , Vol.3-18-1
performance-monitoring counters , Vol.3-20-1
registers
description of , Vol.3-18-2
loading , Vol.3-2-25
RF (resume) flag, EFLAGS , Vol.3-18-1
see DS (debug store) mechanismT (debug trap) flag, TSS
, Vol.3-18-1
TF (trap) flag, EFLAGS , Vol.3-18-1
DEC instruction , Vol.1-7-8, Vol.2-3-321, Vol.2-3-610, Vol.3-9-4
Decimal integers, x87 FPU , Vol.1-4-10
Deeper sleep , Vol.1-2-4
Denormal number (see Denormalized finite number)Denormal operand exception (#D)
, Vol.1-23-10
overview of , Vol.1-4-20
SSE and SSE2 extensions , Vol.1-11-15
x87 FPU , Vol.1-8-27
Denormalization process , Vol.1-4-15
Denormalized finite number , Vol.1-4-5, Vol.1-4-14, Vol.2-3-455
Denormalized operand , Vol.1-23-12
Denormals-are-zero
DAZ flag, MXCSR register , Vol.1-10-5, Vol.1-11-2, Vol.1-11-3, 
Vol.1-11-20
mode , Vol.1-10-5, Vol.1-11-20
Detecting and Enabling SMX
level 2 , Vol.1-6-1
Device-not-available exception (#NM) , Vol.3-2-16, Vol.3-2-24, 
Vol.3-6-32, Vol.3-10-7, Vol.1-23-11, Vol.1-23-12
DF (direction) flag, EFLAGS register , Vol.1-3-17, Vol.1-A-1, Vol.2-3-159, 
Vol.2-3-196, Vol.2-3-511, Vol.2-3-612, Vol.2-4-110, Vol.2-4-178, Vol.2-4-604, Vol.2-4-661
DFR
Destination Format Register , Vol.3-11-38, Vol.3-11-41, Vol.3-11-46
DH register , Vol.1-3-12
DI register , Vol.1-3-12
Digital media boost , Vol.1-2-4
Digital readout bits , Vol.3-15-43, Vol.3-15-46
Displacement (operand addressing) , Vol.1-3-22, Vol.1-3-23, Vol.1-3-24, 
Vol.2-2-3
DIV instruction , Vol.1-7-9, Vol.2-3-323, Vol.3-6-24
Divide , Vol.1-4-21
Divide by zero exception (#Z)
x87 FPU , Vol.1-8-28
Divide configuration register, local APIC , Vol.3-11-17
Divide error exception (#DE) , Vol.2-3-323
Divide-error exception (#DE) , Vol.3-6-24, Vol.1-23-21
DIVPD- Divide Packed Double-Precision Floating-Point Values , Vol.2-3-326
DIVPD instruction , Vol.1-11-6
DIVPS- Divide Packed Single-Precision Floating-Point Values , Vol.2-3-329
DIVPS instruction , Vol.1-10-8
DIVSD- Divide Scalar Double-Precision Floating-Point Values , Vol.2-3-332
DIVSD instruction , Vol.1-11-6
DIVSS- Divide Scalar Single-Precision Floating-Point Values , Vol.2-3-334
DIVSS instruction , Vol.1-10-8
DL register , Vol.1-3-12
DM (denormal operand exception) mask bit
x87 FPU control word , Vol.1-8-7
Double-extended-precision FP format , Vol.1-4-4Double-fault exception (#DF) , Vol.3-6-33, Vol.1-23-27
Double-precision floating-point format , Vol.1-4-4
Doubleword , Vol.1-4-1
DPL (descriptor privilege level) field, segment descriptor , Vol.3-3-11, 
Vol.3-5-2, Vol.3-5-4, Vol.3-5-7
DR0-DR3 breakpoint-address registers , Vol.3-18-1, Vol.3-18-4, 
Vol.3-18-39, Vol.3-18-41, Vol.3-18-42
DR4-DR5 debug registers , Vol.3-18-4, Vol.1-23-20
DR6 debug status register , Vol.3-18-4
B0-B3 (BP detected) flags , Vol.3-18-4
BD (debug register access detected) flag , Vol.3-18-4
BS (single step) flag , Vol.3-18-4
BT (task switch) flag , Vol.3-18-4
debug exception (#DB) , Vol.3-6-25
reserved bits , Vol.1-23-20
DR7 debug control register , Vol.3-18-4
G0-G3 (global breakpoint enable) flags , Vol.3-18-5
GD (general detect enable) flag , Vol.3-18-5
GE (global exact breakpoint enable) flag , Vol.3-18-5
L0-L3 (local breakpoint enable) flags , Vol.3-18-5
LE local exact breakpoint enable) flag , Vol.3-18-5
LEN0-LEN3 (Length) fields , Vol.3-18-5
R/W0-R/W3 (read/write) fields , Vol.3-18-5, Vol.1-23-20
DS feature flag, CPUID instruction , Vol.3-18-19, Vol.3-18-35, 
Vol.3-18-38, Vol.3-18-40
DS register , Vol.1-3-13, Vol.1-3-14, Vol.2-3-195, Vol.2-3-588, 
Vol.2-3-612, Vol.2-4-110, Vol.2-4-178
DS save area , Vol.3-18-21, Vol.3-18-22, Vol.3-18-23
DS (debug store) mechanism
availability of , Vol.3-20-111
description of , Vol.3-20-111
DS feature flag, CPUID instruction , Vol.3-20-111
DS save area , Vol.3-18-19, Vol.3-18-22
IA-32e mode , Vol.3-18-22
interrupt service routine (DS ISR) , Vol.3-18-26
setting up , Vol.3-18-24
Dual-core technology
architecture , Vol.3-9-32
introduction , Vol.1-2-18
logical processors supported , Vol.3-9-25
MTRR memory map , Vol.3-9-33
multi-threading feature flag , Vol.3-9-25
performance monitoring , Vol.3-20-125
specific features , Vol.1-23-4
Dual-monitor treatment , Vol.4-32-19
DX register , Vol.1-3-12
Dynamic data flow analysis , Vol.1-2-8
Dynamic execution , Vol.1-2-7, Vol.1-2-10, Vol.1-2-12, Vol.1-2-13
D/B (default operation size/default st ack pointer size and/or upper bound) 
flag, segment descriptor , Vol.3-3-11, Vol.3-5-4
E
E (edge detect) flag
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family) , Vol.3-20-4
E (edge detect) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family 
processors) , Vol.3-20-134
E (expansion direction) flag
segment descriptor , Vol.3-5-2, Vol.3-5-4
E (MTRRs enabled) flag
IA32_MTRR_DEF_TYPE MSR , Vol.3-12-23
EAX register , Vol.1-3-11, Vol.1-3-12

E
EBP register , Vol.1-3-11, Vol.1-3-12, Vol.1-6-3, Vol.1-6-7
EBX register , Vol.1-3-11, Vol.1-3-12
ECX register , Vol.1-3-11, Vol.1-3-12
EDI register , Vol.1-3-11, Vol.1-3-12, Vol.2-4-604, Vol.2-4-661, 
Vol.2-4-665
EDX register , Vol.1-3-11, Vol.1-3-12
Effective address , Vol.1-3-23, Vol.2-3-595
EFLAGS register
condition codes , Vol.1-B-1, Vol.2-3-177, Vol.2-3-373, Vol.2-3-378Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -9INDEX
cross-reference with instructions , Vol.1-A-1
description of , Vol.1-3-15
identifying 32-bit processors , Vol.1-23-6
instructions that operate on , Vol.1-7-21
new flags , Vol.1-23-6
overview , Vol.1-3-11
part of basic programming environment , Vol.1-7-1
popping , Vol.2-4-401
popping on return from interrupt , Vol.2-3-539
pushing , Vol.2-4-521
pushing on interrupts , Vol.2-3-517
restoring from stack , Vol.1-6-7
saved in TSS , Vol.3-8-4
saving , Vol.2-4-590
saving on a procedure call , Vol.1-6-7
status flags , Vol.1-8-6, Vol.1-8-7, Vol.1-8-19, Vol.2-3-179, 
Vol.2-3-551, Vol.2-4-612, Vol.2-4-703
system flags , Vol.3-2-9
use with CMOVcc instructions , Vol.1-7-3
EIP register , Vol.2-3-140, Vol.2-3-517, Vol.2-3-539, Vol.2-3-554, 
Vol.1-23-11
relationship to CS register , Vol.1-3-14
saved in TSS , Vol.3-8-5
EM (emulation) flag
CR0 control register , Vol.3-2-16, Vol.3-6-32, Vol.3-10-6, Vol.3-10-7, 
Vol.3-13-1, Vol.1-14-3
EMMS instruction , Vol.1-9-8, Vol.1-9-9, Vol.2-3-341, Vol.3-13-3
ENCODEKEY128—Encode 128-Bit Key , Vol.2-3-342
ENCODEKEY256—Encode 256-Bit Key , Vol.2-3-344
Encodings
See machine instructions, opcodes
ENDBR32—Terminate an Indirect Branch in 32-bit and Compatibility Mode
, Vol.2-3-346
Enhanced Intel Deeper Sleep , Vol.1-2-4
Enhanced Intel SpeedStep Technology
ACPI 3.0 specification , Vol.3-15-1
IA32_APERF MSR , Vol.3-15-2
IA32_MPERF MSR , Vol.3-15-2
IA32_PERF_CTL MSR , Vol.3-15-1
IA32_PERF_STATUS MSR , Vol.3-15-1
introduction , Vol.3-15-1
multiple processor cores , Vol.3-15-1
performance transitions , Vol.3-15-1
P-state coordination , Vol.3-15-1
ENTER instruction , Vol.1-6-20, Vol.1-7-21, Vol.2-3-354
GETSEC , Vol.1-6-3, Vol.1-6-10, Vol.1-5-39
EOI
End Of Interrupt register , Vol.3-11-38
Error code , Vol.3-17-3, Vol.3-17-7, Vol.3-17-10, Vol.3-17-13, 
Vol.3-17-15
architectural MCA , Vol.3-17-1, Vol.3-17-3, Vol.3-17-7, Vol.3-17-10, 
Vol.3-17-13, Vol.3-17-15
decoding IA32_MCi_STATUS , Vol.3-17-1, Vol.3-17-3, Vol.3-17-7, 
Vol.3-17-10, Vol.3-17-13, Vol.3-17-15
exception, description of , Vol.3-6-17
external bus , Vol.3-17-1, Vol.3-17-3, Vol.3-17-7, Vol.3-17-10, 
memory hierarchy , Vol.3-17-3, Vol.3-17-7, Vol.3-17-10, Vol.3-17-13, 
pushing on stack , Vol.1-23-32
watchdog timer , Vol.3-17-1, Vol.3-17-3, Vol.3-17-7, Vol.3-17-10, 
Error numbers
VM-instruction error field , Vol.3-31-31
Error signals , Vol.1-23-11Error-reporting bank registers , Vol.3-16-2
ERROR#
input , Vol.1-23-16
output , Vol.1-23-16
ES register , Vol.1-3-13, Vol.1-3-14, Vol.2-3-588, Vol.2-4-178, 
Vol.2-4-604, Vol.2-4-665
ES (exception summary) flag
x87 FPU status word , Vol.1-8-31
ES0 and ES1 (event select) fields, CESR MSR (Pentium processor) , 
ESC instructions, x87 FPU , Vol.1-8-15
ESI register , Vol.1-3-11, Vol.1-3-12, Vol.2-3-195, Vol.2-3-612, 
Vol.2-4-110, Vol.2-4-178, Vol.2-4-661
ESP register , Vol.1-3-12, Vol.2-3-140
ESP register (stack pointer) , Vol.1-3-11, Vol.1-6-3
ESR
Error Status Register , Vol.3-11-39
ET (extension type) flag, CR0 control register , Vol.3-2-15, Vol.1-23-8
Event select field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family 
processors) , Vol.3-20-4, Vol.3-20-98, Vol.3-20-134
Events
at-retirement , Vol.3-20-117
at-retirement (Pentium 4 processor) , Vol.3-20-106
non-retirement (Pentium 4 processor) , Vol.3-20-106
EVEX.R , Vol.2-3-5
Exception flags, x87 FPU status word , Vol.1-8-5
Exception handler
calling , Vol.3-6-11
defined , Vol.3-6-1
flag usage by handler procedure , Vol.3-6-17
machine-check exception handler , Vol.3-16-28
machine-check exceptions (#MC) , Vol.3-16-28
machine-error logging utility , Vol.3-16-28
procedures , Vol.3-6-12
protection of handler procedures , Vol.3-6-16
task, Vol.3-6-17, Vol.3-8-2
Exception handlers
overview of , Vol.1-6-12
SIMD floating-point exceptions , Vol.1-D-1
SSE and SSE2 extensions , Vol.1-11-18
typical actions of a FP exception handler , Vol.1-4-24
x87 FPU , Vol.1-8-31
Exception priority, floating-point exceptions , Vol.1-4-23
Exception-flag masks, x87 FPU control word , Vol.1-8-7
64-bit mode , Vol.1-6-19
alignment check , Vol.1-23-11
BOUND range exceeded (#BR) , Vol.2-3-123
classifications , Vol.3-6-5
compound error codes , Vol.3-16-21
conditions checked during a task switch , Vol.3-8-13
coprocessor segment overrun , Vol.1-23-12
description of , Vol.1-6-12, Vol.3-2-5, Vol.3-6-1
device not available , Vol.1-23-12
double fault , Vol.3-6-33
error code , Vol.3-6-17
execute-disable bit , Vol.3-5-32
floating-point error , Vol.1-23-12
general protection , Vol.1-23-12
handler , Vol.1-6-12
handler mechanism , Vol.3-6-12
handler procedures , Vol.3-6-12
handling , Vol.3-6-11
handling in real-address mode , Vol.3-21-4
handling in SMM , Vol.4-32-11
handling in virtual-8086 mode , Vol.3-21-11
handling through a task gate in virtual-8086 mode , Vol.3-21-14
handling through a trap or interrupt gate in virtual-8086 mode , 
Vol.3-21-12
IA-32e mode , Vol.3-2-5
IDT, Vol.3-6-9
implicit call to handler , Vol.1-6-1INDEX
Index-10 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4in real-address mode , Vol.1-6-18
initializing for protected-mode operation , Vol.3-10-10
invalid-opcode , Vol.1-23-5
masking when switching stack segments , Vol.3-6-8
MCA error codes , Vol.3-16-20
MMX instructions , Vol.3-13-1
notation , Vol.1-1-8, Vol.2-1-7, Vol.3-1-10, Vol.4-1-7
overflow exception (#OF) , Vol.2-3-517
overview of , Vol.3-6-1
priority of , Vol.1-23-22
priority of, x87 FPU exceptions , Vol.1-23-10
reference information on all exceptions , Vol.3-6-23
reference information, 64-bit mode , Vol.3-6-19
restarting a task or program , Vol.3-6-5
returning from , Vol.2-3-539
segment not present , Vol.1-23-12
simple error codes , Vol.3-16-20
sources of , Vol.3-6-4
summary of , Vol.3-6-2
vectors , Vol.3-6-1
Executable , Vol.3-3-11
Execute-disable bit capability
conditions for , Vol.3-5-30
CPUID flag , Vol.3-5-30
detecting and enabling , Vol.3-5-30
exception handling , Vol.3-5-32
page-fault exceptions , Vol.3-6-44
protection matrix for IA-32e mode , Vol.3-5-31
protection matrix for legacy modes , Vol.3-5-31
reserved bit checking , Vol.3-5-31
GETSEC , Vol.1-6-3, Vol.1-6-5
Exit-reason numbers
VM entries & exits , Vol.1-C-1
Expand-down data segment type , Vol.3-3-11
Exponent, extracting from floating-point number , Vol.2-3-470
Exponent, floating-point number , Vol.1-4-11
Extended signature table , Vol.3-10-31
extended signature table , Vol.3-10-31
External bus errors, detected with machine-check architecture , 
Vol.3-16-27
Extract exponent and significand, x87 FPU operation , Vol.2-3-470
EXTRACTPS- Extract packed floating-point values , Vol.2-3-357
F
F2XM1 instruction , Vol.1-8-21, Vol.2-3-359, Vol.2-3-470, Vol.1-23-13
FABS instruction , Vol.1-8-17, Vol.2-3-361
FADD instruction , Vol.1-8-17, Vol.2-3-362
FADDP instruction , Vol.1-8-17, Vol.2-3-362
Family 06H , Vol.3-17-1
Family 0FH , Vol.3-17-1
microcode update facilities , Vol.3-10-28
Far call
description of , Vol.1-6-4
operation , Vol.1-6-5
Far pointer
16-bit addressing , Vol.1-3-9
32-bit addressing , Vol.1-3-9
64-bit mode , Vol.1-4-7
description of , Vol.1-3-7, Vol.1-4-6
legacy modes , Vol.1-4-6
Far pointer, loading , Vol.2-3-588
Far return operation , Vol.1-6-5
Far return, RET instruction , Vol.2-4-558
Faults
restarting a program or task after , Vol.3-6-5
FBLD instruction , Vol.1-8-16, Vol.2-3-365
FBSTP instruction , Vol.1-8-16, Vol.2-3-367
FCHS instruction , Vol.1-8-17, Vol.2-3-369
FCLEX instruction , Vol.2-3-371FCLEX/FNCLEX instructions , Vol.1-8-5
FCMOVcc instructions , Vol.1-8-7, Vol.1-8-16, Vol.2-3-373, Vol.1-23-4
FCOM instruction , Vol.1-8-6, Vol.1-8-18, Vol.2-3-375
FCOMI instruction , Vol.1-8-7, Vol.1-8-18, Vol.2-3-378, Vol.1-23-4
FCOMIP instruction , Vol.1-8-7, Vol.1-8-18, Vol.2-3-378, Vol.1-23-4
FCOMP instruction , Vol.1-8-6, Vol.1-8-18, Vol.2-3-375
FCOMPP instruction , Vol.1-8-6, Vol.1-8-18, Vol.2-3-375
FCOS instruction , Vol.1-8-5, Vol.1-8-20, Vol.2-3-381, Vol.1-23-13
FDECSTP instruction , Vol.2-3-383
FDIV instruction , Vol.1-8-17, Vol.2-3-384, Vol.1-23-11, Vol.1-23-12
FDIVP instruction , Vol.1-8-17, Vol.2-3-384
FDIVR instruction , Vol.1-8-17, Vol.2-3-387
FDIVRP instruction , Vol.1-8-17, Vol.2-3-387

Faults
FE (fixed MTRRs enabled) flag, IA32_MTRR_DEF_TYPE MSR , Vol.3-12-23
Feature
determination, of processor , Vol.1-23-2
information, processor , Vol.1-23-2
Feature determination, of processor , Vol.1-20-1
Feature information, processor , Vol.2-3-217
FFREE instruction , Vol.2-3-390
FIADD instruction , Vol.1-8-17, Vol.2-3-362
FICOM instruction , Vol.1-8-6, Vol.1-8-18, Vol.2-3-391
FICOMP instruction , Vol.1-8-6, Vol.1-8-18, Vol.2-3-391
FIDIV instruction , Vol.1-8-17, Vol.2-3-384
FIDIVR instruction , Vol.1-8-17, Vol.2-3-387
FILD instruction , Vol.1-8-16, Vol.2-3-393
FIMUL instruction , Vol.1-8-17, Vol.2-3-411
FINCSTP instruction , Vol.2-3-395
FINIT instruction , Vol.2-3-396
FINIT/FNINIT instructions , Vol.1-8-5, Vol.1-8-7, Vol.1-8-8, Vol.1-8-23, 
Vol.2-3-426, Vol.1-23-8, Vol.1-23-16
FIST instruction , Vol.1-8-16, Vol.2-3-398
FISTP instruction , Vol.1-8-16, Vol.2-3-398
FISTTP instruction , Vol.1-5-23, Vol.1-12-3, Vol.2-3-401
FISUB instruction , Vol.1-8-17, Vol.2-3-445
FISUBR instruction , Vol.1-8-17, Vol.2-3-448
FIX (fixed range registers supported) flag, IA32_MTRRCAPMSR , 
Vol.3-12-22
Fixed-range MTRRs
description of , Vol.3-12-23
Flags
Flat memory model , Vol.1-3-7, Vol.1-3-13
Flat segmentation model , Vol.3-3-3
FLD instruction , Vol.1-8-16, Vol.2-3-403, Vol.1-23-14
FLD1 instruction , Vol.1-8-17, Vol.2-3-405
FLDCW instruction , Vol.1-8-7, Vol.1-8-23, Vol.2-3-407
FLDENV instruction , Vol.1-8-5, Vol.1-8-9, Vol.1-8-11, Vol.1-8-23, 
Vol.2-3-409, Vol.1-23-12
FLDL2E instruction , Vol.1-8-17, Vol.2-3-405, Vol.1-23-14
FLDL2T instruction , Vol.1-8-17, Vol.2-3-405, Vol.1-23-14
FLDLG2 instruction , Vol.1-8-17, Vol.2-3-405, Vol.1-23-14
FLDLN2 instruction , Vol.1-8-17, Vol.2-3-405, Vol.1-23-14
FLDPI instruction , Vol.1-8-17, Vol.2-3-405, Vol.1-23-14
FLDSW instruction , Vol.1-8-23
FLDZ instruction , Vol.1-8-17, Vol.2-3-405
Floating point instructions
machine encodings , Vol.1-B-61
Floating-point data types
biasing constant , Vol.1-4-6
denormalized finite number , Vol.1-4-5
description of , Vol.1-4-4
double extended precision format , Vol.1-4-4, Vol.1-4-5
double precision format , Vol.1-4-4, Vol.1-4-5
half precision format , Vol.1-4-5
infinites , Vol.1-4-5
normalized finite number , Vol.1-4-5
single precision format , Vol.1-4-4, Vol.1-4-5
SSE extensions , Vol.1-10-5
storing in memory , Vol.1-4-6
x87 FPU , Vol.1-8-13Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -11INDEX
zeros , Vol.1-4-5
Floating-point error exception (#MF) , Vol.1-23-12
Floating-point exception handlers
typical actions , Vol.1-4-24
Floating-point exceptions
denormal operand exception (#D) , Vol.1-4-20, Vol.1-8-28, 
Vol.1-11-15, Vol.1-C-1, Vol.1-23-10
divide by zero exception (#Z) , Vol.1-4-21, Vol.1-8-28, Vol.1-11-15, 
Vol.1-C-1
exception conditions , Vol.1-4-20
exception priority , Vol.1-4-23
inexact result (precision) exception (#P) , Vol.1-4-22, Vol.1-8-30, 
Vol.1-11-16, Vol.1-C-1
invalid operation exception (#I) , Vol.1-4-20, Vol.1-8-26, Vol.1-11-14
invalid operation (#I) , Vol.1-23-14
invalid-operation exception (#IA) , Vol.1-C-1
invalid-operation exception (#IS) , Vol.1-C-1
invalid-operation exception (#I) , Vol.1-C-1
numeric overflow exception (#O) , Vol.1-4-21, Vol.1-8-28, 
Vol.1-11-15, Vol.1-C-1
numeric overflow (#O) , Vol.1-23-10
numeric underflow exception (#U) , Vol.1-4-22, Vol.1-8-29, 
numeric underflow (#U) , Vol.1-23-10
saved CS and EIP values , Vol.1-23-11
SSE and SSE2 SIMD , Vol.2-3-16
summary of , Vol.1-4-19, Vol.1-C-1
typical handler actions , Vol.1-4-24
x87 FPU , Vol.2-3-16
Floating-point format
biased exponent , Vol.1-4-13
description of , Vol.1-8-13
exponent , Vol.1-4-11
fraction , Vol.1-4-11
indefinite , Vol.1-4-5
QNaN floating-point indefinite , Vol.1-4-17
real number system , Vol.1-4-11
sign, Vol.1-4-11
significand , Vol.1-4-11
Floating-point numbers
defined , Vol.1-4-11
encoding , Vol.1-4-5
Flushing
caches , Vol.2-3-532, Vol.1-6-3
TLB entry , Vol.2-3-534
Flush-to-zero
FTZ flag, MXCSR register , Vol.1-10-4, Vol.1-11-2
mode , Vol.1-10-4
FLUSH# pin , Vol.3-6-3
FMA operation , Vol.1-14-22, Vol.1-14-23
FMUL instruction , Vol.1-8-17, Vol.2-3-411
FMULP instruction , Vol.1-8-17, Vol.2-3-411
FNCLEX instruction , Vol.2-3-371
FNINIT instruction , Vol.2-3-396
FNOP instruction , Vol.1-8-23, Vol.2-3-414
FNSAVE instruction , Vol.2-3-426, Vol.3-13-4
FNSTCW instruction , Vol.2-3-439
FNSTENV instruction , Vol.2-3-409, Vol.2-3-441
FNSTSW instruction , Vol.2-3-443
Focus processor, local APIC , Vol.3-11-26
Fopcode compatibility mode , Vol.1-8-10
FORCEPR# log , Vol.3-15-43, Vol.3-15-46
FORCPR# interrupt enable bit , Vol.3-15-44
FPATAN instruction , Vol.1-8-20, Vol.1-8-21, Vol.2-3-415, Vol.1-23-13
FPREM instruction , Vol.1-8-5, Vol.1-8-18, Vol.1-8-21, Vol.2-3-417, 
Vol.1-23-8, Vol.1-23-11, Vol.1-23-12, Vol.1-23-13
FPREM1 instruction , Vol.1-8-5, Vol.1-8-18, Vol.1-8-21, Vol.2-3-419, 
Vol.1-23-8, Vol.1-23-13
FPTAN instruction , Vol.1-8-5, Vol.2-3-421, Vol.1-23-8, Vol.1-23-13
Fraction, floating-point number , Vol.1-4-11FRNDINT instruction , Vol.1-8-18, Vol.2-3-423
FRSTOR instruction , Vol.1-8-5, Vol.1-8-9, Vol.1-8-11, Vol.1-8-23, 
Vol.2-3-424, Vol.3-13-4, Vol.1-23-11, Vol.1-23-12
FS register , Vol.1-3-13, Vol.1-3-14, Vol.2-3-588
FSAVE instruction , Vol.2-3-426, Vol.3-13-3, Vol.3-13-4
FSAVE/FNSAVE instructions , Vol.1-8-4, Vol.1-8-5, Vol.1-8-9, Vol.1-8-11, 
Vol.1-8-23, Vol.2-3-424, Vol.1-23-11, Vol.1-23-14
FSCALE instruction , Vol.1-8-21, Vol.2-3-429, Vol.1-23-12
FSIN instruction , Vol.1-8-5, Vol.1-8-20, Vol.2-3-431, Vol.1-23-13
FSINCOS instruction , Vol.1-8-5, Vol.1-8-20, Vol.2-3-433, Vol.1-23-13
FSQRT instruction , Vol.1-8-18, Vol.2-3-435, Vol.1-23-11, Vol.1-23-12
FST instruction , Vol.1-8-16, Vol.2-3-437
FSTCW instruction , Vol.2-3-439
FSTCW/FNSTCW instructions , Vol.1-8-7, Vol.1-8-23
FSTENV instruction , Vol.2-3-441, Vol.3-13-3
FSTENV/FNSTENV instructions , Vol.1-8-4, Vol.1-8-9, Vol.1-8-11, 
Vol.1-8-23, Vol.1-23-14
FSTP instruction , Vol.1-8-16, Vol.2-3-437
FSTSW instruction , Vol.2-3-443
FSTSW/FNSTSW instructions , Vol.1-8-4, Vol.1-8-23
FSUB instruction , Vol.1-8-17, Vol.2-3-445
FSUBP instruction , Vol.1-8-17, Vol.2-3-445
FSUBR instruction , Vol.1-8-17, Vol.2-3-448
FSUBRP instruction , Vol.1-8-17, Vol.2-3-448
FTAN instruction , Vol.1-23-8
FTST instruction , Vol.1-8-6, Vol.1-8-18, Vol.2-3-451
FUCOM instruction , Vol.1-8-18, Vol.2-3-453, Vol.1-23-13
FUCOMI instruction , Vol.1-8-7, Vol.1-8-18, Vol.2-3-378, Vol.1-23-4
FUCOMIP instruction , Vol.1-8-7, Vol.1-8-18, Vol.2-3-378, Vol.1-23-4
FUCOMP instruction , Vol.1-8-18, Vol.2-3-453, Vol.1-23-13
FUCOMPP instruction , Vol.1-8-6, Vol.1-8-18, Vol.2-3-453, Vol.1-23-13
FWAIT instruction , Vol.3-6-32
FXAM instruction , Vol.1-8-4, Vol.1-8-19, Vol.2-3-455, Vol.1-23-14
FXCH instruction , Vol.1-8-16, Vol.2-3-457
FXRSTOR instruction , Vol.1-5-14, Vol.1-8-12, Vol.1-10-14, Vol.1-11-23, 
Vol.2-3-459, Vol.3-2-18, Vol.3-2-19, Vol.3-10-8, Vol.3-13-3, Vol.3-13-4, Vol.1-14-2, Vol.1-14-6
CPUID flag , Vol.2-3-247
FXSAVE instruction , Vol.1-5-14, Vol.1-8-12, Vol.1-10-14, Vol.1-11-23, 
Vol.2-3-462, Vol.2-5-722, Vol.2-5-723, Vol.1-6-32, Vol.1-6-45, Vol.1-6-50, Vol.1-6-54, Vol.1-6-57, Vol.1-6-60, Vol.1-6-63, Vol.1-6-66, Vol.3-2-18, Vol.3-2-19, Vol.3-10-8, Vol.3-13-3, Vol.3-13-4, Vol.1-14-2, Vol.1-14-6
FXSR feature flag, CPUID instruction , Vol.3-10-8
FXTRACT instruction , Vol.1-8-18, Vol.2-3-429, Vol.2-3-470, Vol.1-23-10, 
Vol.1-23-14
FYL2X instruction , Vol.1-8-21, Vol.2-3-472
FYL2XP1 instruction , Vol.1-8-21, Vol.2-3-474
G
segment descriptor , Vol.3-3-10, Vol.3-3-11, Vol.3-5-2, Vol.3-5-4
G0-G3 (global breakpoint enable) flags
Gate descriptors
call gates , Vol.3-5-13
Gates , Vol.3-2-4
IA-32e mode , Vol.3-2-4
GD (general detect enable) flag
DR7 register , Vol.3-18-5, Vol.3-18-10
GDT
description of , Vol.3-2-3, Vol.3-3-15
index field of segment selector , Vol.3-3-7
initializing , Vol.3-10-10INDEX
Index-12 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4paging of , Vol.3-2-6
pointers to exception/interrupt handlers , Vol.3-6-12
segment descriptors in , Vol.3-3-9
selecting with TI flag of segment selector , Vol.3-3-7
task switching , Vol.3-8-9
task-gate descriptor , Vol.3-8-8
TSS descriptors , Vol.3-8-5
use in address translation , Vol.3-3-6
GDT (global descriptor table) , Vol.2-3-600, Vol.2-3-603
GDTR register , Vol.1-3-4, Vol.1-3-6
description of , Vol.3-2-3, Vol.3-2-6, Vol.3-2-12, Vol.3-3-15
IA-32e mode , Vol.3-2-4, Vol.3-2-12
limit, Vol.3-5-5
storing , Vol.3-3-15
GDTR (global descriptor table register) , Vol.2-3-600, Vol.2-4-617
GE (global exact breakpoint enable) flag

GDT
General purpose registers
64-bit mode , Vol.1-3-5, Vol.1-3-13
description of , Vol.1-3-11
overview of , Vol.1-3-2, Vol.1-3-5
parameter passing , Vol.1-6-7
using REX prefix , Vol.1-3-13
General-detect exception condition , Vol.3-18-10
General-protection exception (#GP) , Vol.3-3-12, Vol.3-5-6, Vol.3-5-7, 
Vol.3-5-11, Vol.3-5-12, Vol.3-6-9, Vol.3-6-16, Vol.3-6-41, Vol.3-8-5, Vol.3-18-3, Vol.1-23-12, Vol.1-23-21, Vol.1-23-34, Vol.1-23-35
General-purpose instructions
64-bit encodings , Vol.1-B-18
64-bit mode , Vol.1-7-1
basic programming environment , Vol.1-7-1
data types operated on , Vol.1-7-1, Vol.1-7-2
description of , Vol.1-7-1
non-64-bit encodings , Vol.1-B-7
origin of , Vol.1-7-1
programming with , Vol.1-7-1
summary of , Vol.1-5-5, Vol.1-7-2
General-purpose registers
moving value to and from , Vol.2-4-36
popping all , Vol.2-4-397
pushing all , Vol.2-4-519
General-purpose registers, saved in TSS , Vol.3-8-4
GETSEC , Vol.1-6-1, Vol.1-6-2, Vol.1-6-5
Global control MSRs , Vol.3-16-2
Global descriptor table register (see GDTR)Global descriptor table (see GDT)GS register
, Vol.1-3-13, Vol.1-3-14, Vol.2-3-588
H
HADDPD instruction , Vol.1-5-24, Vol.1-12-4, Vol.2-3-483, Vol.2-3-484
HADDPS instruction , Vol.1-5-23, Vol.1-12-4, Vol.2-3-486
HALT state
relationship to SMI interrupt , Vol.4-32-3, Vol.4-32-14
Hardware Lock Elision (HLE) , Vol.1-16-2
Hardware reset
processor state after reset , Vol.3-10-2
state of MTRRs following , Vol.3-12-20
value of SMBASE following , Vol.4-32-4
Hexadecimal numbers , Vol.1-1-7, Vol.2-1-7, Vol.3-1-8, Vol.4-1-6
high-temperature interrupt enable bit , Vol.3-15-44, Vol.3-15-47
HITM# line , Vol.3-12-6
HLT instruction , Vol.2-3-489, Vol.3-2-26, Vol.3-5-24, Vol.3-6-34, 
Vol.3-26-2, Vol.4-32-14
Horizontal processing model , Vol.1-12-1
HSUBPD instruction , Vol.1-5-24, Vol.1-12-5, Vol.2-3-492
HSUBPS instruction , Vol.1-5-23, Vol.1-12-4, Vol.2-3-495
HT Technologyfirst processor , Vol.1-2-3
implementing , Vol.1-2-17
introduction , Vol.1-2-16
architectural state of a logical processor , Vol.3-9-33
architecture description , Vol.3-9-27
caches , Vol.3-9-31
debug registers , Vol.3-9-30
description of , Vol.3-9-25, Vol.1-23-3, Vol.1-23-4
detecting , Vol.3-9-36, Vol.3-9-37, Vol.3-9-42, Vol.3-9-43
executing multiple threads , Vol.3-9-27
execution-based timing loops , Vol.3-9-54
external signal compatibility , Vol.3-9-32
halting logical processors , Vol.3-9-53
handling interrupts , Vol.3-9-27
HLT instruction , Vol.3-9-48
IA32_MISC_ENABLE MSR , Vol.3-9-30, Vol.3-9-33
initializing IA-32 processors with , Vol.3-9-26
introduction of into the IA-32 architecture , Vol.1-23-3, Vol.1-23-4
local a , Vol.3-9-28
local APIC
functionality in logical processor , Vol.3-9-29
logical processors, identifying , Vol.3-9-39
machine check architecture , Vol.3-9-29
managing idle and blocked conditions , Vol.3-9-48
mapping resources , Vol.3-9-34
memory ordering , Vol.3-9-30
microcode update resources , Vol.3-9-30, Vol.3-9-33, Vol.3-10-35
MP systems , Vol.3-9-27
MTRRs , Vol.3-9-29, Vol.3-9-33
multi-threading support , Vol.3-9-25
PAT, Vol.3-9-29
PAUSE instruction , Vol.3-9-48, Vol.3-9-49
performance monitoring , Vol.3-20-120, Vol.3-20-125
performance monitoring counters , Vol.3-9-30, Vol.3-9-33
placement of locks and semaphores , Vol.3-9-54
required operating system support , Vol.3-9-51
scheduling multiple threads , Vol.3-9-54
self modifying code , Vol.3-9-31
serializing instructions , Vol.3-9-30
spin-wait loops
PAUSE instructions in , Vol.3-9-51, Vol.3-9-53
thermal monitor , Vol.3-9-32
TLBs , Vol.3-9-31
I
IA-32 architecture
history of , Vol.1-2-1
introduction to , Vol.1-2-1
IA-32 Intel architecture
compatibility , Vol.1-23-1
processors , Vol.1-23-1
IA32e mode
IA-32e mode
CPUID flag , Vol.2-3-239
data structures and initialization , Vol.3-10-11
debug store areadescriptors
, Vol.3-2-4
exceptions during initialization , Vol.3-10-12
feature-enable register , Vol.3-2-7
IA32_EFER MSR , Vol.3-2-7, Vol.3-5-30
initialization process , Vol.3-10-11Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -13INDEX
interrupts and exceptions , Vol.3-2-5
introduction , Vol.1-2-20, Vol.2-2-7, Vol.2-2-13, Vol.2-2-21, 
Vol.2-2-36
IRET instruction , Vol.3-6-21
logical address , Vol.3-3-7
MOV CRn , Vol.3-10-11
MTRR calculations , Vol.3-12-27
NXE bit , Vol.3-5-30
page level protection , Vol.3-5-30
PDE tables , Vol.3-5-31
PDP tables , Vol.3-5-31
PML4 tables , Vol.3-5-31
PTE tables , Vol.3-5-31
registers and data structures , Vol.3-2-1
see 64-bit mode
see compatibility modesegment descriptor tables
, Vol.3-3-16, Vol.3-5-3
segment descriptors , Vol.3-3-9
segmentation , Vol.1-3-22, Vol.3-3-5
system descriptors , Vol.3-3-14
task switching , Vol.3-8-19
task-state segments , Vol.3-2-5
terminating mode operation , Vol.3-10-12
See also: 64-bit mode, compatibility mode
IA32_APIC_BASE MSR , Vol.3-9-19, Vol.3-9-20, Vol.3-11-5, Vol.3-11-7, 
Vol.3-11-8, Vol.4-2-454
IA32_BIOS_SIGN_ID MSR , Vol.4-2-457
IA32_BIOS_UPDT_TRIG MSR , Vol.4-2-456
IA32_CLOCK_MODULATION MSR , Vol.3-9-32, Vol.3-15-7, Vol.3-15-14, 
Vol.3-15-15, Vol.3-15-16, Vol.3-15-17, Vol.3-15-18, Vol.3-15-21, Vol.3-15-22, Vol.3-15-23, Vol.3-15-24, Vol.3-15-40, Vol.3-15-41, Vol.3-15-43, Vol.3-15-51, Vol.3-15-52, Vol.3-15-53, Vol.3-15-54, Vol.3-15-55, Vol.4-2-70, Vol.4-2-86, Vol.4-2-97, Vol.4-2-153, Vol.4-2-201, Vol.4-2-438, Vol.4-2-460, Vol.4-2-461, Vol.4-2-485, Vol.4-2-495
IA32_CTL MSR , Vol.4-2-457
IA32_DEBUGCTL MSR , Vol.3-28-29, Vol.4-2-464
IA32_DS_AREA MSR , Vol.3-18-19, Vol.3-18-20, Vol.3-18-24, 
Vol.3-20-104, Vol.3-20-119, Vol.4-2-475
IA32_EFER MSR , Vol.3-2-7, Vol.3-2-8, Vol.3-5-30, Vol.3-28-29
IA32_FEATURE_CONTROL MSR , Vol.3-24-3
IA32_KernelGSbase MSR , Vol.3-2-7
IA32_LSTAR MSR , Vol.3-2-7, Vol.3-5-22
IA32_MCG_CAP MSR , Vol.3-16-2, Vol.3-16-28, Vol.4-2-457
IA32_MCG_CTL MSR , Vol.3-16-2, Vol.3-16-4
IA32_MCG_EAX MSR , Vol.3-16-12
IA32_MCG_EBP MSR , Vol.3-16-12
IA32_MCG_EBX MSR , Vol.3-16-12
IA32_MCG_ECX MSR , Vol.3-16-12
IA32_MCG_EDI MSR , Vol.3-16-12
IA32_MCG_EDX MSR , Vol.3-16-12
IA32_MCG_EFLAGS MSR , Vol.3-16-12
IA32_MCG_EIP MSR , Vol.3-16-12
IA32_MCG_ESI MSR , Vol.3-16-12
IA32_MCG_ESP MSR , Vol.3-16-12
IA32_MCG_MISC MSR , Vol.3-16-12, Vol.4-2-459
IA32_MCG_R10 MSR , Vol.3-16-13, Vol.4-2-459
IA32_MCG_R11 MSR , Vol.3-16-13, Vol.4-2-460
IA32_MCG_R12 MSR , Vol.3-16-13
IA32_MCG_R13 MSR , Vol.3-16-13
IA32_MCG_R14 MSR , Vol.3-16-13
IA32_MCG_R15 MSR , Vol.3-16-13, Vol.4-2-460IA32_MCG_R8 MSR , Vol.3-16-13
IA32_MCG_R9 MSR , Vol.3-16-13
IA32_MCG_RAX MSR , Vol.3-16-12, Vol.4-2-457
IA32_MCG_RBP MSR , Vol.3-16-12
IA32_MCG_RBX MSR , Vol.3-16-12, Vol.4-2-457
IA32_MCG_RCX MSR , Vol.3-16-12
IA32_MCG_RDI MSR , Vol.3-16-12
IA32_MCG_RDX MSR , Vol.3-16-12
IA32_MCG_RESERVEDn MSR , Vol.3-16-12
IA32_MCG_RFLAGS MSR , Vol.3-16-12, Vol.4-2-458
IA32_MCG_RIP MSR , Vol.3-16-12, Vol.4-2-459
IA32_MCG_RSI MSR , Vol.3-16-12
IA32_MCG_RSP MSR , Vol.3-16-12
IA32_MCG_STATUS MSR , Vol.3-16-2, Vol.3-16-4, Vol.3-16-28, 
Vol.3-16-30, Vol.3-28-3
IA32_MCi_ADDR MSR , Vol.3-16-9, Vol.3-16-30, Vol.4-2-472
IA32_MCi_CTL , Vol.3-16-5
IA32_MCi_CTL MSR , Vol.3-16-5, Vol.4-2-472
IA32_MCi_MISC MSR , Vol.3-16-9, Vol.3-16-11, Vol.3-16-12, Vol.3-16-30, 
Vol.4-2-472
IA32_MCi_STATUS MSR , Vol.3-16-6, Vol.3-16-28, Vol.3-16-30, 
decoding for Family 06H , Vol.3-17-1
decoding for Family 0FH , Vol.3-17-1, Vol.3-17-3, Vol.3-17-7, 
IA32_MISC_ENABLE MSR , Vol.1-8-10, Vol.3-15-1, Vol.3-15-37, 
Vol.3-18-20, Vol.3-18-35, Vol.3-20-104, Vol.4-2-461
IA32_MPERF MSR , Vol.3-15-1, Vol.3-15-2
IA32_MTRRCAP MSR , Vol.3-12-21, Vol.3-12-22, Vol.4-2-457
IA32_MTRR_DEF_TYPE MSR , Vol.3-12-22
IA32_MTRR_FIXn, fixed ranger MTRRs , Vol.3-12-23
IA32_MTRR_PHYS BASEn MTRR , Vol.4-2-465
IA32_MTRR_PHYSBASEn MTRR , Vol.4-2-465
IA32_MTRR_PHYSMASKn MTRR , Vol.4-2-465
IA32_P5_MC_ADDR MSR , Vol.4-2-453
IA32_P5_MC_TYPE MSR , Vol.4-2-453
IA32_PAT_CR MSR , Vol.3-12-34
IA32_PEBS_ENABLE MSR , Vol.3-20-102, Vol.3-20-104, Vol.3-20-119, 
IA32_PLATFORM_ID , Vol.4-2-65, Vol.4-2-81, Vol.4-2-148, Vol.4-2-196, 
Vol.4-2-433, Vol.4-2-454, Vol.4-2-481, Vol.4-2-491, Vol.4-2-498
IA32_STAR MSR , Vol.3-5-22
IA32_STAR_CS MSR , Vol.3-2-7
IA32_STATUS MSR , Vol.4-2-457
IA32_SYSCALL_FLAG_MASK MSR , Vol.3-2-7

IA32_SYSENTER_CS MSR , Vol.3-5-21, Vol.3-5-22, Vol.3-28-23, 
Vol.4-2-457
IA32_SYSENTER_EIP MSR , Vol.3-5-21, Vol.4-2-457
IA32_SYSENTER_ESP MSR , Vol.3-5-21, Vol.3-28-29, Vol.4-2-457
IA32_TERM_CONTROL MSR , Vol.4-2-70, Vol.4-2-86, Vol.4-2-97, 
Vol.4-2-153, Vol.4-2-201
IA32_THERM_INTERRUPT MSR , Vol.3-15-39, Vol.3-15-41, Vol.3-15-42, 
Vol.3-15-44, Vol.4-2-461
low-temperature interrupt enable bit , Vol.3-15-44, Vol.3-15-47
overheat interrupt enable bit , Vol.3-15-44, Vol.3-15-47
THERMTRIP# interrupt enable bit , Vol.3-15-44, Vol.3-15-47
threshold #1 interrupt enable bit , Vol.3-15-44, Vol.3-15-47
threshold #1 value , Vol.3-15-44, Vol.3-15-47
threshold #2 interrupt enable , Vol.3-15-44, Vol.3-15-47
threshold #2 value , Vol.3-15-44, Vol.3-15-47
IA32_THERM_STATUS MSR , Vol.3-15-41, Vol.3-15-42, Vol.4-2-461
digital readout bits , Vol.3-15-43, Vol.3-15-46
out-of-spec status bit , Vol.3-15-43, Vol.3-15-46
out-of-spec status log , Vol.3-15-43, Vol.3-15-46
PROCHOT# or FORCEPR# event bit , Vol.3-15-42, Vol.3-15-46
PROCHOT# or FORCEPR# log , Vol.3-15-43, Vol.3-15-46
resolution in degrees , Vol.3-15-43INDEX
Index-14 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4thermal status bit , Vol.3-15-42, Vol.3-15-45
thermal status log , Vol.3-15-42, Vol.3-15-46
thermal threshold #1 log , Vol.3-15-43, Vol.3-15-46
thermal threshold #1 status , Vol.3-15-43, Vol.3-15-46
thermal threshold #2 log , Vol.3-15-43, Vol.3-15-46
thermal threshold #2 status , Vol.3-15-43, Vol.3-15-46
validation bit , Vol.3-15-43
IA32_TIME_STAMP_COUNTER MSR , Vol.4-2-453
IA32_VMX_BASIC MSR , Vol.3-25-3, Vol.1-A-1, Vol.1-A-2, Vol.4-2-78, 
Vol.4-2-92, Vol.4-2-102, Vol.4-2-163, Vol.4-2-212, Vol.4-2-474, Vol.4-2-490
IA32_VMX_CR0_FIXED0 MSR , Vol.1-A-7, Vol.4-2-79, Vol.4-2-92, 
Vol.4-2-102, Vol.4-2-164, Vol.4-2-212, Vol.4-2-475, Vol.4-2-490
IA32_VMX_CR0_FIXED1 MSR , Vol.1-A-7, Vol.4-2-79, Vol.4-2-92, 
Vol.4-2-103, Vol.4-2-164, Vol.4-2-212, Vol.4-2-475, Vol.4-2-490
IA32_VMX_CR4_FIXED0 MSR , Vol.1-A-7, Vol.4-2-79, Vol.4-2-92, 
IA32_VMX_CR4_FIXED1 MSR , Vol.1-A-7, Vol.4-2-79, Vol.4-2-92, 
Vol.4-2-103, Vol.4-2-164, Vol.4-2-212, Vol.4-2-213, Vol.4-2-475, Vol.4-2-490
IA32_VMX_ENTRY_CTLS MSR , Vol.1-A-2, Vol.1-A-5, Vol.1-A-6, 
Vol.4-2-78, Vol.4-2-92, Vol.4-2-102, Vol.4-2-164, Vol.4-2-212, Vol.4-2-474, Vol.4-2-490
IA32_VMX_EXIT_CTLS MSR , Vol.1-A-2, Vol.1-A-4, Vol.1-A-5, Vol.4-2-78, 
IA32_VMX_MISC MSR , Vol.3-25-6, Vol.3-27-3, Vol.3-27-13, Vol.4-32-26, 
Vol.1-A-6, Vol.4-2-78, Vol.4-2-92, Vol.4-2-102, Vol.4-2-164, Vol.4-2-212, Vol.4-2-475, Vol.4-2-490
IA32_VMX_PINBASED_CTLS MSR , Vol.1-A-2, Vol.1-A-3, Vol.4-2-78, 
IA32_VMX_PROCBASED_CTLS MSR , Vol.3-25-10, Vol.1-A-2, Vol.1-A-3, 
Vol.1-A-4, Vol.1-A-5, Vol.1-A-8, Vol.1-A-9, Vol.4-2-78, Vol.4-2-79, Vol.4-2-92, Vol.4-2-102, Vol.4-2-103, Vol.4-2-163, Vol.4-2-164, Vol.4-2-212, Vol.4-2-213, Vol.4-2-261, Vol.4-2-474, Vol.4-2-490
IA32_VMX_VMCS_ENUM MSR , Vol.1-A-7, Vol.4-2-475
ICR
Interrupt Command Register , Vol.3-11-38, Vol.3-11-41, Vol.3-11-47
ID (identification) flag
EFLAGS register , Vol.3-2-11, Vol.1-23-6
ID (identification) flag, EFLAGS register , Vol.1-3-17
IDIV instruction , Vol.1-7-9, Vol.2-3-498, Vol.3-6-24, Vol.1-23-21
IDT
64-bit mode , Vol.3-6-19
call interrupt & exception-handlers from , Vol.3-6-11
change base & limit in real-address mode , Vol.3-21-5
description of , Vol.3-6-9
handling NMIs during initialization , Vol.3-10-9
initializing protected-mode operation , Vol.3-10-10
initializing real-address mode operation , Vol.3-10-8
introduction to , Vol.3-2-5
limit, Vol.1-23-27
structure in real-address mode , Vol.3-21-5
task switching , Vol.3-8-10
types of descriptors allowed , Vol.3-6-10
use in real-address mode , Vol.3-21-4
IDT (interrupt descriptor table) , Vol.2-3-518, Vol.2-3-600
IDTR register , Vol.1-3-4, Vol.1-3-6
description of , Vol.3-2-12, Vol.3-6-9
IA-32e mode , Vol.3-2-12
loading in real-address mode , Vol.3-21-5
storing , Vol.3-3-16
IDTR (interrupt descriptor table register) , Vol.2-3-600, Vol.2-4-643IE (invalid operation exception) flag
MXCSR register , Vol.1-11-14
x87 FPU status word , Vol.1-8-5, Vol.1-8-26, Vol.1-8-27, Vol.1-23-8
IEEE Standard 754 , Vol.1-4-4, Vol.1-4-11, Vol.1-8-1
IEEE Standard 754 for Binary Floating-Point Arithmetic , Vol.1-23-9, 
Vol.1-23-10, Vol.1-23-12, Vol.1-23-13, Vol.1-23-14
IF (interrupt enable) flag
EFLAGS register , Vol.1-3-17, Vol.1-6-13, Vol.1-19-4, Vol.1-A-1, 
Vol.3-2-10, Vol.3-2-11, Vol.3-6-7, Vol.3-6-10, Vol.3-6-17, Vol.3-21-4, Vol.3-21-19, Vol.4-32-11
IF (interrupt enable) flag, EFLAGS register , Vol.2-3-166, Vol.2-4-662
IM (invalid operation exception) mask bit
Immediate operands , Vol.1-3-20, Vol.2-2-3
IMUL instruction , Vol.1-7-9, Vol.2-3-501
IN instruction , Vol.1-5-9, Vol.1-7-20, Vol.1-19-3, Vol.2-3-505, 
Vol.3-9-16, Vol.1-23-35, Vol.3-26-2
INC instruction , Vol.1-7-8, Vol.2-3-507, Vol.2-3-610, Vol.3-9-4
Indefinite
description of , Vol.1-4-17, Vol.1-14-18
floating-point format , Vol.1-4-5, Vol.1-4-13
integer , Vol.1-4-4, Vol.1-8-14
packed BCD integer , Vol.1-4-11
QNaN floating-point , Vol.1-4-17
Index field, segment selector , Vol.3-3-7
Index (operand addressing) , Vol.1-3-22, Vol.1-3-23, Vol.1-3-24, 
Vol.2-2-3
Inexact result (precision)
exception (#P), overview , Vol.1-4-22
exception (#P), SSE-SSE2 extensions , Vol.1-11-16
exception (#P), x87 FPU , Vol.1-8-30
on floating-point operations , Vol.1-4-18
Infinity control flag, x87 FPU control word , Vol.1-8-8
Infinity, floating-point format , Vol.1-4-5, Vol.1-4-15
INIT interrupt , Vol.3-11-3
INIT pin , Vol.1-3-15
Initial-count register, local APIC , Vol.3-11-16
Initialization
built-in self-test (BIST) , Vol.3-10-1, Vol.3-10-5
CS register state following , Vol.3-10-5
EIP register state following , Vol.3-10-5
example , Vol.3-10-14
first instruction executed , Vol.3-10-5
hardware reset , Vol.3-10-1
IA-32e mode , Vol.3-10-11
IDT, protected mode , Vol.3-10-10
IDT, real-address mode , Vol.3-10-8
Intel486 SX processor and In tel 487 SX math coprocessor , 
Vol.1-23-16
location of software-initialization code , Vol.3-10-5
machine-check initialization , Vol.3-16-19
model and stepping information , Vol.3-10-5
multitasking environment , Vol.3-10-10, Vol.3-10-11
overview , Vol.3-10-1
paging , Vol.3-10-10
protected mode , Vol.3-10-9
real-address mode , Vol.3-10-8
RESET# pin , Vol.3-10-1
setting up exception- and interrupt-handling facilities , Vol.3-10-10
x87 FPU , Vol.3-10-5
Initialization x87 FPU , Vol.2-3-396
initiating logical processor , Vol.1-6-4, Vol.1-6-5, Vol.1-6-10, Vol.1-6-21, 
Vol.1-6-22
INIT# pin , Vol.3-6-3, Vol.3-10-1
INIT# signal , Vol.3-2-26, Vol.3-24-4
Input/output (see I/O)
INS instruction , Vol.1-5-9, Vol.1-7-20, Vol.1-19-3, Vol.2-3-511, 
Vol.2-4-555, Vol.3-18-10
INSB instruction , Vol.2-3-511
INSD instruction , Vol.2-3-511Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -15INDEX
INSERTPS- Insert Scalar Single-Precision Floating-Point Value , Vol.2-3-514
instruction encodings , Vol.1-B-58, Vol.1-B-64, Vol.1-B-70
Instruction format
base field , Vol.2-2-3
description of reference information , Vol.2-3-1
displacement , Vol.2-2-3
immediate , Vol.2-2-3
index field , Vol.2-2-3
Mod field , Vol.2-2-3
ModR/M byte , Vol.2-2-3
opcode , Vol.2-2-3
operands , Vol.2-1-6
prefixes , Vol.2-2-1
reg/opcode field , Vol.2-2-3
r/m field , Vol.2-2-3
scale field , Vol.2-2-3
SIB byte , Vol.2-2-3
See also: machine instructions, opcodes
Instruction operands , Vol.1-1-7, Vol.3-1-8, Vol.4-1-6
Instruction pointer
EIP register , Vol.1-3-11, Vol.1-3-18
RIP register , Vol.1-3-18
RIP, EIP, IP compared , Vol.1-3-10
x87 FPU , Vol.1-8-9
Instruction prefixes
effect on SSE and SSE2 instructions , Vol.1-11-25
REX prefix , Vol.1-3-2, Vol.1-3-12
Instruction reference, nomenclature , Vol.2-3-1
Instruction set
binary arithmetic instructions , Vol.1-7-8
bit scan instructions , Vol.1-7-14
bit test and modify instructions , Vol.1-7-14
byte-set-on-condition instructions , Vol.1-7-14
cacheability control instructions , Vol.1-5-19, Vol.1-5-22
comparison and sign change instruction , Vol.1-7-8
data movement instructions , Vol.1-7-2
decimal arithmetic instructions , Vol.1-7-9
EFLAGS cross-reference , Vol.1-A-1
EFLAGS instructions , Vol.1-7-21
exchange instructions , Vol.1-7-4
FXSAVE and FXRSTOR instructions , Vol.1-5-14
general-purpose instructions , Vol.1-5-5
grouped by processor , Vol.1-5-2
increment and decrement instructions , Vol.1-7-8
instruction ordering instructions , Vol.1-5-19, Vol.1-5-22

I/O instructions , Vol.1-5-9, Vol.1-7-20
logical instructions , Vol.1-7-10
MMX instructions , Vol.1-5-15, Vol.1-9-5
multiply and divide instructions , Vol.1-7-9
processor identification instruction , Vol.1-7-23
repeating string operations , Vol.1-7-19
rotate instructions , Vol.1-7-13
segment register instructions , Vol.1-7-22
shift instructions , Vol.1-7-10
SIMD instructions, introduction to , Vol.1-2-14
software interrupt instructions , Vol.1-7-17
SSE instructions , Vol.1-5-17
SSE2 instructions , Vol.1-5-19
stack manipulation instructions , Vol.1-7-5
string operation instructions , Vol.1-7-18
summary , Vol.1-5-1
system instructions , Vol.1-5-31, Vol.1-5-36
test instruction , Vol.1-7-14
type conversion instructions , Vol.1-7-7
x87 FPU and SIMD state management instructions , Vol.1-5-14
x87 FPU instructions , Vol.1-5-11
Instruction set, reference , Vol.2-3-1
Instruction-breakpoint exception condition , Vol.3-18-9
new instructions , Vol.1-23-4obsolete instructions , Vol.1-23-5
privileged , Vol.3-5-23
serializing , Vol.3-9-17, Vol.3-9-30, Vol.1-23-16
supported in real-address mode , Vol.3-21-3
system , Vol.3-2-7, Vol.3-2-23
INSW instruction , Vol.2-3-511
INS/INSB/INSW/INSD instruction , Vol.3-26-2
INT 3 instruction , Vol.2-3-517, Vol.3-2-5, Vol.3-6-28, Vol.3-18-7
INT instruction , Vol.1-6-18, Vol.1-7-23, Vol.3-2-5, Vol.3-5-10
INT n instruction , Vol.3-3-8, Vol.3-6-1, Vol.3-6-4, Vol.3-18-11
INT (APIC interrupt enable) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 
family processors) , Vol.3-20-5, Vol.3-20-135
INT15 and microcode updates , Vol.3-10-42
INT3 instruction , Vol.3-3-8, Vol.3-6-4
Integers
description of , Vol.1-4-3
indefinite , Vol.1-4-4, Vol.1-8-14
signed integer encodings , Vol.1-4-4
signed, description of , Vol.1-4-4
unsigned integer encodings , Vol.1-4-3
unsigned, description of , Vol.1-4-3
Integer, storing, x87 FPU data type , Vol.2-3-398
Intel 287 math coprocessor , Vol.1-23-7
Intel 387 math coprocessor system , Vol.1-23-7
Intel 487 SX math coprocessor , Vol.1-23-7, Vol.1-23-16
Intel 64 architecture
64-bit mode , Vol.1-3-1
64-bit mode instructions , Vol.1-5-37
address space , Vol.1-3-6
data types , Vol.1-4-1
definition of , Vol.4-1-4
executing calls , Vol.1-6-1
general purpose instructions , Vol.1-7-1
generations , Vol.1-2-20
IA32e mode , Vol.1-3-1
instruction format , Vol.2-2-1
introduction , Vol.1-2-20
memory organization , Vol.1-3-6, Vol.1-3-8
relation to IA-32 , Vol.4-1-4
See also: IA-32e mode
Intel 8086 processor , Vol.1-23-7
Intel Advanced Digital Media Boost , Vol.1-2-4, Vol.1-2-11
Intel Advanced Smart Cache , Vol.1-2-10
Intel Advanced Thermal Manager , Vol.1-2-4
Intel Core 2 Extreme processor family , Vol.1-2-4, Vol.1-2-18
Intel Core Duo processor , Vol.1-2-4, Vol.1-2-18
Intel Core microarchitecture , Vol.1-2-4, Vol.1-2-10, Vol.1-2-12, 
Vol.1-2-13, Vol.1-2-18
Intel Core Solo and Duo processors
model-specific registers , Vol.4-2-480
Intel Core Solo and Intel Core Duo processors
event mask (Umask) , Vol.3-20-96, Vol.3-20-97
last branch, interrupt, exception recording , Vol.3-18-38
notes on P-state transitions , Vol.3-15-1
performance monitoring , Vol.3-20-96, Vol.3-20-97
sub-fields layouts , Vol.3-20-96, Vol.3-20-97
time stamp counters , Vol.3-18-42
Intel Core Solo processor , Vol.1-2-4
Intel Dynamic Power Coordination , Vol.1-2-4
Intel NetBurst microarchitecture , Vol.1-1-3, Vol.2-1-3, Vol.3-1-3, 
Vol.4-1-3
description of , Vol.1-2-8
introduction , Vol.1-2-8
Intel Pentium D processor , Vol.1-2-18
Intel Pentium processor Extreme Edition , Vol.1-2-18
Intel Smart Cache , Vol.1-2-4
Intel Smart Memory Access , Vol.1-2-4, Vol.1-2-11
Intel software network link , Vol.1-1-9, Vol.2-1-9, Vol.3-1-11, Vol.4-1-8
Intel SpeedStep Technology
See: Enhanced Intel SpeedStep TechnologyINDEX
Index-16 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4Intel Transactional Synchronization , Vol.1-15-3, Vol.1-16-1
Intel VTune Performance Analyzer
related information , Vol.1-1-9, Vol.2-1-9, Vol.3-1-10, Vol.4-1-8
Intel Wide Dynamic Execution , Vol.1-2-4, Vol.1-2-10, Vol.1-2-12, 
Vol.1-2-13
Intel Xeon processor , Vol.1-1-1, Vol.2-1-1, Vol.3-1-1, Vol.4-1-1
description of , Vol.1-2-3
last branch, interrupt, and exception recording , Vol.3-18-35
time-stamp counter , Vol.3-18-42
Intel Xeon processor 5100 series , Vol.1-2-4, Vol.1-2-18
Intel Xeon processor MP
with 8MB L3 cache , Vol.3-20-125, Vol.3-20-127
Intel286 processor , Vol.1-23-7
Intel386 DX processor , Vol.1-23-7
Intel386 processor , Vol.1-2-1
Intel386 SL processor , Vol.3-2-7
Intel486 DX processor , Vol.1-23-7
Intel486 processor
Intel486 SX processor , Vol.1-23-7, Vol.1-23-16
Intel® Trusted Execution Technology , Vol.1-6-3
Inter-privilege level
call, CALL instruction , Vol.2-3-139
return, RET instruction , Vol.2-4-558
Inter-privilege level call
description of , Vol.1-6-7
operation , Vol.1-6-8
Interprivilege level calls
call mechanism , Vol.3-5-15
stack switching , Vol.3-5-17
Inter-privilege level return
Interprocessor interrupt (IPIs) , Vol.3-11-1
Interprocessor interrupt (IPI)
in MP systems , Vol.3-11-1
interrupt , Vol.3-6-13
Interrupt Command Register , Vol.3-11-38
Interrupt command register (ICR), local APIC , Vol.3-11-19
Interrupt gate , Vol.1-6-13
Interrupt gates
clearing IF flag , Vol.3-6-7, Vol.3-6-17
difference between interrupt and trap gates , Vol.3-6-17
handling a virtual-8086 mode interrupt or exception through , 
in IDT , Vol.3-6-10
introduction to , Vol.3-2-4, Vol.3-2-5
layout of , Vol.3-6-10
Interrupt handler , Vol.1-6-12
automatic bus locking , Vol.1-23-35
control transfers between 16-  and 32-bit code modules , Vol.3-22-6
destination , Vol.3-11-26
distribution mechanism, local APIC , Vol.3-11-25
enabling and disabling , Vol.3-6-6
handling multiple NMIs , Vol.3-6-6
handling through a task gate in virtual-8086 mode , Vol.3-21-14handling through a trap or interrupt gate in virtual-8086 mode , 
IA-32e mode , Vol.3-2-5, Vol.3-2-12
IDTR, Vol.3-2-12
implicit call to an interrupt handler
procedure , Vol.1-6-13
implicit call to an interrupt handler task , Vol.1-6-18
implicit call to interrupt handler procedure , Vol.1-6-13
implicit call to interrupt handler task , Vol.1-6-18
in real-address mode , Vol.1-6-18
interrupt descriptor table register (see IDTR)interrupt descriptor table (see IDT)list of
, Vol.3-6-2, Vol.3-21-6
local APIC , Vol.3-11-1
maskable , Vol.1-6-13
maskable hardware interrupts , Vol.3-2-10
masking maskable hardware interrupts , Vol.3-6-7
message signalled interrupts , Vol.3-11-34
on-die sensors for , Vol.3-15-36
priority , Vol.3-11-28
propagation delay , Vol.1-23-27
real-address mode , Vol.3-21-6
software , Vol.2-3-517, Vol.3-6-58
sources of , Vol.3-11-1
thermal monitoring , Vol.3-15-36
user defined , Vol.3-6-1, Vol.3-6-58
valid APIC interrupts , Vol.3-11-15
virtual-8086 mode , Vol.3-21-6
INTn instruction , Vol.1-7-17, Vol.2-3-517
INTO instruction , Vol.1-6-18, Vol.1-7-18, Vol.1-7-23, Vol.2-3-517, 
Vol.3-2-5, Vol.3-3-8, Vol.3-6-4, Vol.3-6-29, Vol.3-18-11
Intrinsics
list of , Vol.1-C-1
INTR# pin , Vol.3-6-2, Vol.3-6-7
Invalid arithmetic operand exception (#IA)
description of , Vol.1-8-27
masked response to , Vol.1-8-27
Invalid opcode exception (#UD) , Vol.3-2-16, Vol.3-6-31, Vol.3-6-53, 
Vol.3-13-1, Vol.3-18-4, Vol.1-23-5, Vol.1-23-11, Vol.1-23-20, Vol.1-23-21, Vol.4-32-3
Invalid operation exception (#I)
overview , Vol.1-4-20
SSE and SSE2 extensions , Vol.1-11-14
x87 FPU , Vol.1-8-26
Invalid TSS exception (#TS) , Vol.3-6-36, Vol.3-8-6
Invalid-operation exception, x87 FPU , Vol.1-23-11, Vol.1-23-14
INVD instruction , Vol.2-3-532, Vol.3-2-25, Vol.3-5-24, Vol.3-12-17, 
INVLPG instruction , Vol.2-3-534, Vol.3-2-25, Vol.3-5-24, Vol.1-23-4, 
Vol.3-26-3
IOPL (I/O privilege level) field
EFLAGS register , Vol.1-3-17, Vol.1-19-3
IOPL (I/O privilege level) field, EFLAGS register , Vol.2-3-166
description of , Vol.3-2-10
on return from exception, interrupt handler , Vol.3-6-13

sensitive instructions in virtual-8086 mode , Vol.3-21-10
virtual interrupt , Vol.3-2-11
IPI (see interprocessor interrupt)Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -17INDEX
IRET instruction , Vol.1-3-18, Vol.1-6-17, Vol.1-6-18, Vol.1-7-15, 
Vol.1-7-23, Vol.1-19-4, Vol.2-3-539, Vol.3-3-8, Vol.3-6-7, Vol.3-6-13, Vol.3-6-17, Vol.3-6-21, Vol.3-8-10, Vol.3-8-11, Vol.3-9-18, Vol.3-21-5, Vol.3-21-19, Vol.3-26-8
IRETD instruction , Vol.2-3-539, Vol.3-2-10, Vol.3-9-18
IRR
Interrupt Request Register , Vol.3-11-39, Vol.3-11-41, Vol.3-11-47
IRR (interrupt request register), local APIC , Vol.3-11-30
ISR
In Service Register , Vol.3-11-38, Vol.3-11-41, Vol.3-11-47
I/O
address space , Vol.1-19-1
breakpoint exception conditions , Vol.3-18-10
in virtual-8086 mode , Vol.3-21-10
instruction restart flag
SMM revision identifier field , Vol.4-32-15
instruction restart flag, SMM revision identifier field , Vol.4-32-15
instruction serialization , Vol.1-19-5
instructions , Vol.1-5-9, Vol.1-7-20, Vol.1-19-3
IO_SMI bit , Vol.4-32-12
I/O permission bit map, TSS , Vol.3-8-5
I/O privilege level (see IOPL)map base
, Vol.1-19-4
map base address field, TSS , Vol.3-8-5
permission bit map , Vol.1-19-4
ports , Vol.1-3-4, Vol.1-19-1, Vol.1-19-2, Vol.1-19-3, Vol.1-19-5
restarting following SMI interrupt , Vol.4-32-15
saving I/O state , Vol.4-32-12
sensitive instructions , Vol.1-19-3
SMM state save map , Vol.4-32-12
I/O APIC , Vol.3-11-26
bus arbitration , Vol.3-11-26
description of , Vol.3-11-1
external interrupts , Vol.3-6-3
information about , Vol.3-11-1
interrupt sources , Vol.3-11-2
local APIC and I/O APIC , Vol.3-11-2, Vol.3-11-3
overview of , Vol.3-11-1
valid interrupts , Vol.3-11-15
See also: local APIC
J
J-bit, Vol.1-4-11
Jcc instructions , Vol.1-3-17, Vol.1-3-18, Vol.1-7-15, Vol.2-3-548
JMP instruction , Vol.1-3-18, Vol.1-7-15, Vol.1-7-22, Vol.2-3-553, 
Vol.3-2-5, Vol.3-3-8, Vol.3-5-10, Vol.3-5-15, Vol.3-8-2, Vol.3-8-9, Vol.3-8-11
Jump operation , Vol.2-3-553
K
KEN# pin , Vol.3-12-13, Vol.1-23-36
L
L0-L3 (local breakpoint enable) flags
L1 (level 1) cache , Vol.1-2-7, Vol.1-2-9
caching methods , Vol.3-12-6
description of , Vol.3-12-4
effect of using write-through memory , Vol.3-12-9
introduction of , Vol.1-23-30
invalidating and flushing , Vol.3-12-17
MESI cache protocol , Vol.3-12-9
shared and adaptive mode , Vol.3-12-18
L2 (level 2) cache , Vol.1-2-7, Vol.1-2-9
disabling , Vol.3-12-17
effect of using write-through memory , Vol.3-12-9introduction of , Vol.1-23-30
L3 (level 3) cache
disabling and enabling , Vol.3-12-13, Vol.3-12-17
introduction of , Vol.1-23-31
LAHF instruction , Vol.1-3-15, Vol.1-7-21, Vol.2-3-581
LAR instruction , Vol.2-3-582, Vol.3-2-25, Vol.3-5-24
Larger page sizes
support for , Vol.1-23-19
Last branch
interrupt & exception recording
description of , Vol.2-4-573, Vol.3-18-12, Vol.3-18-27, 
Vol.3-18-29, Vol.3-18-31, Vol.3-18-32, Vol.3-18-33, Vol.3-18-36, Vol.3-18-38, Vol.3-18-39, Vol.3-18-40
record stack , Vol.3-18-18, Vol.3-18-19, Vol.3-18-27, Vol.3-18-28, 
Vol.3-18-35, Vol.3-18-36, Vol.3-18-38, Vol.3-18-40, Vol.4-2-464, Vol.4-2-475
record top-of-stack pointer , Vol.3-18-18, Vol.3-18-28, Vol.3-18-35, 
Vol.3-18-39, Vol.3-18-40
Last instruction opcode, x87 FPU , Vol.1-8-10
LastBranchFromIP MSR , Vol.3-18-41, Vol.3-18-42
LastBranchToIP MSR , Vol.3-18-41, Vol.3-18-42
LastExceptionFromIP MSR , Vol.3-18-37, Vol.3-18-39, Vol.3-18-41, 
Vol.3-18-42
LastExceptionToIP MSR , Vol.3-18-37, Vol.3-18-39, Vol.3-18-41, 
LBR (last branch/interrupt/exc eption) flag, DEBUGCTLMSR MSR , 
Vol.3-18-14, Vol.3-18-35, Vol.3-18-41, Vol.3-18-42
LDDQU instruction , Vol.1-5-23, Vol.1-12-3, Vol.2-3-585
LDMXCSR instruction , Vol.1-10-12, Vol.1-11-24, Vol.2-3-587, 
Vol.2-4-535, Vol.1-6-7
LDR
Logical Destination Register , Vol.3-11-41, Vol.3-11-45, Vol.3-11-46
LDS instruction , Vol.1-7-23, Vol.2-3-588, Vol.3-3-8, Vol.3-5-8
LDT
associated with a task , Vol.3-8-3
description of , Vol.3-2-3, Vol.3-2-5, Vol.3-3-15
index into with index field of segment selector , Vol.3-3-7
pointer to in TSS , Vol.3-8-5
pointers to exception and interrupt handlers , Vol.3-6-12
segment selector field, TSS , Vol.3-8-16
selecting with TI (table indicator) flag of segment selector , Vol.3-3-7
setting up during initialization , Vol.3-10-10
LDT (local descriptor table) , Vol.2-3-603
LDTR register , Vol.1-3-4, Vol.1-3-6
description of , Vol.3-2-3, Vol.3-2-5, Vol.3-2-6, Vol.3-2-12, Vol.3-3-15
LDTR (local descriptor table register) , Vol.2-3-603, Vol.2-4-645
LE (local exact breakpoint  enable) flag, DR7 register , Vol.3-18-5, 
Vol.3-18-10
LEA instruction , Vol.1-7-23, Vol.2-3-595
LEAVE instruction , Vol.1-6-20, Vol.1-6-24, Vol.1-7-21, Vol.2-3-597
LEN0-LEN3 (Length) fields, DR7 register , Vol.3-18-5, Vol.3-18-6
LES instruction , Vol.1-7-23, Vol.2-3-588, Vol.3-3-8, Vol.3-5-8, 
Vol.3-6-31
LFENCE instruction , Vol.1-11-12, Vol.2-3-599, Vol.3-2-16, Vol.3-9-7, 
Vol.3-9-16, Vol.3-9-17, Vol.3-9-18
LFS instruction , Vol.2-3-588, Vol.3-3-8, Vol.3-5-8INDEX
Index-18 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4LGDT instruction , Vol.2-3-600, Vol.3-2-24, Vol.3-5-23, Vol.3-9-18, 
Vol.3-10-10, Vol.1-23-20
LGS instruction , Vol.1-7-23, Vol.2-3-588, Vol.3-3-8, Vol.3-5-8
LIDT instruction , Vol.2-3-600, Vol.3-2-24, Vol.3-5-24, Vol.3-6-9, 
Vol.3-9-18, Vol.3-10-9, Vol.3-21-5, Vol.1-23-27
Limit checking
description of , Vol.3-5-4
pointer offsets are within limits , Vol.3-5-25
Limit field, segment descriptor , Vol.3-5-2, Vol.3-5-4
Linear address , Vol.1-3-7
description of , Vol.3-3-6
IA-32e mode , Vol.3-3-7
Linear address space , Vol.3-3-6
defined , Vol.1-3-7, Vol.3-3-1
maximum size , Vol.1-3-7
of task , Vol.3-8-17
Link (to previous task) field, TSS , Vol.3-6-17
Linking tasks
mechanism , Vol.3-8-15
modifying task linkages , Vol.3-8-16
LINT pins
function of , Vol.3-6-2
LLDT instruction , Vol.2-3-603, Vol.3-2-24, Vol.3-5-23, Vol.3-9-18
LMSW instruction , Vol.2-3-605, Vol.3-2-24, Vol.3-5-24, Vol.3-26-3, 
Vol.3-26-8
Load effective address operation , Vol.2-3-595
LOADIWKEY—Load Internal Wrapping Key , Vol.2-3-607
Local APIC , Vol.3-11-38
64-bit mode , Vol.3-11-32
APIC_ID value , Vol.3-9-34
arbitration over the APIC bus , Vol.3-11-26
arbitration over the system bus , Vol.3-11-26
block diagram , Vol.3-11-4
cluster model , Vol.3-11-24
CR8 usage , Vol.3-11-32
current-count register , Vol.3-11-16
detecting with CPUID , Vol.3-11-7
DFR (destination format register) , Vol.3-11-24
divide configuration register , Vol.3-11-17
enabling and disabling , Vol.3-11-7
external interrupts , Vol.3-6-2
features
Pentium 4 and Intel Xeon , Vol.1-23-28
Pentium and P6 , Vol.1-23-28
focus processor , Vol.3-11-26
global enable flag , Vol.3-11-8
IA32_APIC_BASE MSR , Vol.3-11-8
initial-count register , Vol.3-11-16
internal error interrupts , Vol.3-11-1
interrupt command register (ICR) , Vol.3-11-19
interrupt destination , Vol.3-11-26
interrupt distribution mechanism , Vol.3-11-25
IRR (interrupt request register) , Vol.3-11-30
I/O APIC , Vol.3-11-1
local APIC and 82489DX , Vol.1-23-28
local vector table (LVT) , Vol.3-11-12
logical destination mode , Vol.3-11-23
LVT (local-APIC version register) , Vol.3-11-11
mapping of resources , Vol.3-9-34
MDA (message destination address) , Vol.3-11-23
performance-monitoring counter , Vol.3-20-136
physical destination mode , Vol.3-11-23
receiving external interrupts , Vol.3-6-2
register address map , Vol.3-11-6, Vol.3-11-38
shared resources , Vol.3-9-34
SMI interrupt , Vol.4-32-2
spurious interrupt , Vol.3-11-32spurious-interrupt vector register , Vol.3-11-8
state after a software (INIT) reset , Vol.3-11-10
state after INIT-deassert message , Vol.3-11-11
state after power-up reset , Vol.3-11-10
state of , Vol.3-11-33
SVR (spurious-interrupt vector register) , Vol.3-11-8
timer , Vol.3-11-16
timer generated interrupts , Vol.3-11-1
TMR (trigger mode register) , Vol.3-11-30
version register , Vol.3-11-11
Local descriptor table register (see LDTR)Local descriptor table (see LDT)Local vector table (LVT)
description of
, Vol.3-11-12
thermal entry , Vol.3-15-39
Local x2APIC , Vol.3-11-31, Vol.3-11-41, Vol.3-11-46
Local xAPIC ID , Vol.3-11-41

LOCK prefix , Vol.2-3-28, Vol.2-3-33, Vol.2-3-78, Vol.2-3-132, 
Vol.2-3-134, Vol.2-3-136, Vol.2-3-208, Vol.2-3-321, Vol.2-3-507, Vol.2-3-610, Vol.2-4-163, Vol.2-4-166, Vol.2-4-168, Vol.2-4-602, Vol.2-4-674, Vol.1-6-23, Vol.1-6-28, Vol.1-6-36, Vol.3-2-26, Vol.3-6-31, Vol.3-9-1, Vol.3-9-3, Vol.3-9-4, Vol.3-9-16, Vol.1-23-35
LOCK signal , Vol.1-7-4
Locked (atomic) operations
bus locking , Vol.3-9-3
effects on caches , Vol.3-9-6
loading a segment descriptor , Vol.1-23-20
on IA-32 processors , Vol.1-23-35
overview of , Vol.3-9-1
Locking operation , Vol.2-3-610
LOCK# signal , Vol.3-2-26, Vol.3-9-1, Vol.3-9-3, Vol.3-9-4, Vol.3-9-6
LODS instruction , Vol.1-3-17, Vol.1-7-18, Vol.2-3-612, Vol.2-4-555
LODSB instruction , Vol.2-3-612
LODSD instruction , Vol.2-3-612
LODSQ instruction , Vol.2-3-612
LODSW instruction , Vol.2-3-612
Log epsilon, x87 FPU operation , Vol.1-8-21, Vol.2-3-472
Log (base 2), x87 FPU operation , Vol.2-3-474
Logical address , Vol.1-3-7
Logical address space, of task , Vol.3-8-18
Logical destination mode, local APIC , Vol.3-11-23
Logical processors
per physical package , Vol.3-9-25
Logical x2APIC ID , Vol.3-11-46
LOOP instructions , Vol.1-7-16, Vol.2-3-615
LOOPcc instructions , Vol.1-3-17, Vol.1-7-16, Vol.2-3-615
LSL instruction , Vol.2-3-618, Vol.3-2-25, Vol.3-5-25
LSS instruction , Vol.1-7-23, Vol.2-3-588, Vol.3-3-8, Vol.3-5-8
LTR instruction , Vol.2-3-621, Vol.3-2-24, Vol.3-5-24, Vol.3-8-7, 
Vol.3-9-18, Vol.3-10-11
LVT (see Local vector table)
LZCNT - Count the Number of Leading Zero Bits , Vol.2-3-623
M
Machine check architecture
description , Vol.2-3-246
Machine check registers , Vol.1-3-4
Machine instructions
64-bit mode , Vol.1-B-1
condition test (tttn) field , Vol.1-B-6
direction bit (d) field , Vol.1-B-6
floating-point instruction encodings , Vol.1-B-61
general description , Vol.1-B-1Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -19INDEX
general-purpose encodings , Vol.1-B-7–Vol.1-B-37
legacy prefixes , Vol.1-B-1
MMX encodings , Vol.1-B-38–Vol.1-B-41
opcode fields , Vol.1-B-2
operand size (w) bit , Vol.1-B-4
P6 family encodings , Vol.1-B-41
Pentium processor family encodings , Vol.1-B-37
reg (reg) field , Vol.1-B-3, Vol.1-B-4
REX prefixes , Vol.1-B-2
segment register (sreg) field , Vol.1-B-5
sign-extend (s) bit , Vol.1-B-5
SIMD 64-bit encodings , Vol.1-B-37
special 64-bit encodings , Vol.1-B-61
special fields , Vol.1-B-2
special-purpose register (eee) field , Vol.1-B-5
SSE encodings , Vol.1-B-42–Vol.1-B-47
SSE2 encodings , Vol.1-B-47–Vol.1-B-56
SSE3 encodings , Vol.1-B-57–Vol.1-B-58
SSSE3 encodings , Vol.1-B-58–Vol.1-B-60
VMX encodings , Vol.1-B-112, Vol.1-B-113
See also: opcodes
Machine status word, CR0 register , Vol.2-3-605, Vol.2-4-647
Machine-check architecture
availability of MCA and exception , Vol.3-16-19
compatibility with Pentium processor , Vol.3-16-1
CPUID flags , Vol.3-16-19
error codes , Vol.3-16-20, Vol.3-16-21
error-reporting bank registers , Vol.3-16-2
error-reporting MSRs , Vol.3-16-5
extended machine check state MSRs , Vol.3-16-12
external bus errors , Vol.3-16-27
first introduced , Vol.1-23-22
global MSRs , Vol.3-16-2
initialization of , Vol.3-16-19
introduction of in IA-32 processors , Vol.1-23-36
logging correctable errors , Vol.3-16-29, Vol.3-16-31, Vol.3-16-35
machine-check exception (#MC) , Vol.3-16-1
MSRs , Vol.3-16-2
overview of MCA , Vol.3-16-1
Pentium processor exception handling , Vol.3-16-29
Pentium processor style error reporting , Vol.3-16-13
writing machine-check software , Vol.3-16-27, Vol.3-16-28
Machine-check exception (#MC) , Vol.3-6-52, Vol.3-16-1, Vol.3-16-19, 
Vol.3-16-28, Vol.1-23-21, Vol.1-23-36
Mapping of shared resources , Vol.3-9-34
Maskable hardware interrupts
description of , Vol.3-6-3
handling with virtual interrupt mechanism , Vol.3-21-15
masking , Vol.3-2-10, Vol.3-6-7
Maskable interrupts , Vol.1-6-13
Masked responses
denormal operand exception (#D) , Vol.1-4-20, Vol.1-8-28
divide by zero exception (#Z) , Vol.1-4-21, Vol.1-8-28
inexact result (precision) exception (#P) , Vol.1-4-23, Vol.1-8-30
invalid arithmetic operation (#IA) , Vol.1-8-27
invalid operation exception (#I) , Vol.1-4-20
numeric overflow exception (#O) , Vol.1-4-21, Vol.1-8-29
numeric underflow exception (#U) , Vol.1-4-22, Vol.1-8-29
stack overflow or underflow
exception (#IS) , Vol.1-8-27
MASKMOVDQU instruction , Vol.1-11-12, Vol.1-11-25, Vol.2-4-42
MASKMOVQ instruction , Vol.1-10-12, Vol.1-11-25
Masks, exception-flags
MXCSR register , Vol.1-10-4
MAXPD instruction , Vol.1-11-6
MAXPD- Maximum of Packed Double-Precision Floating-Point Values , 
Vol.2-4-12
MAXPS instruction , Vol.1-10-8MAXPS- Maximum of Packed Single-Precision Floating-Point Values , 
Vol.2-4-15
MAXSD instruction , Vol.1-11-6
MAXSD- Return Maximum Scalar Double-Precision Floating-Point Value , 
Vol.1-15-3, Vol.2-4-18
MAXSS instruction , Vol.1-10-9
MAXSS- Return Maximum Scalar Single-Precision Floating-Point Value , 
Vol.2-4-20
MCA flag, CPUID instruction , Vol.3-16-19
MCE flag, CPUID instruction , Vol.3-16-19
MCE (machine-check enable) flag
CR4 control register , Vol.3-2-18, Vol.1-23-18
MDA (message destination address)
local APIC , Vol.3-11-23
measured environment , Vol.1-6-1
Measured Launched Environment , Vol.1-6-1, Vol.1-6-25
Memory , Vol.3-12-1
flat memory model , Vol.1-3-7
management registers , Vol.1-3-4
memory type range registers (MTRRs) , Vol.1-3-4
modes of operation , Vol.1-3-9
organization , Vol.1-3-6, Vol.1-3-7
real address mode memory model , Vol.1-3-7, Vol.1-3-8
segmented memory model , Vol.1-3-7
virtual-8086 mode memory model , Vol.1-3-7, Vol.1-3-8
Memory management
overview , Vol.3-3-1
paging , Vol.3-3-1, Vol.3-3-2
registers , Vol.3-2-11
segments , Vol.3-3-1, Vol.3-3-2, Vol.3-3-7
Memory operands
64-bit mode , Vol.1-3-21
legacy modes , Vol.1-3-21
Memory ordering
in IA-32 processors , Vol.1-23-34
overview , Vol.3-9-6
processor ordering , Vol.3-9-6
strengthening or weakening , Vol.3-9-16
write ordering , Vol.3-9-6
Memory type range registers (see MTRRs)Memory types
caching methods, defined
, Vol.3-12-6
choosing , Vol.3-12-8
MTRR types , Vol.3-12-21
selecting for Pentium III and Pentium 4 processors , Vol.3-12-15
selecting for Pentium Pro and Pentium II processors , Vol.3-12-14
UC (strong uncacheable) , Vol.3-12-6
UC- (uncacheable) , Vol.3-12-6
WB (write back) , Vol.3-12-7
WC (write combining) , Vol.3-12-7
WP (write protected) , Vol.3-12-7
writing values across pages with different memory types , Vol.3-12-16
WT (write through) , Vol.3-12-7
Memory-mapped I/O , Vol.1-19-2
MESI cache protocol , Vol.3-12-5, Vol.3-12-9
Message address register , Vol.3-11-34
Message data register format , Vol.3-11-35
Message signalled interrupts
message address register , Vol.3-11-34
message data register format , Vol.3-11-34
MFENCE instruction , Vol.1-11-12, Vol.1-11-25, Vol.2-4-22, Vol.3-2-16, 
Vol.3-9-7, Vol.3-9-16, Vol.3-9-17, Vol.3-9-18
(see Intel NetBurst microarchitecture)(see P6 family microarchitecture)
Microcode update facilities
authenticating an update
, Vol.3-10-37
BIOS responsibilities , Vol.3-10-38INDEX
Index-20 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4calling program responsibilities , Vol.3-10-39
checksum , Vol.3-10-33
family 0FH processors , Vol.3-10-28
field definitions , Vol.3-10-28
format of update , Vol.3-10-28
function 00H presence test , Vol.3-10-42
function 01H write microcode update data , Vol.3-10-43
function 02H microcode update control , Vol.3-10-46
function 03H read microcode update data , Vol.3-10-47
general description , Vol.3-10-28
HT Technology , Vol.3-10-35
INT 15H-based interface , Vol.3-10-42
overview , Vol.3-10-27
process description , Vol.3-10-28
processor identification , Vol.3-10-32
processor signature , Vol.3-10-32
return codes , Vol.3-10-48
update loader , Vol.3-10-34
update signature and verification , Vol.3-10-36
update specifications , Vol.3-10-37
VMX non-root operation , Vol.3-26-12
MINPD instruction , Vol.1-11-6
MINPD- Minimum of Packed Double-Precision Floating-Point Values , 
Vol.2-4-23
MINPS instruction , Vol.1-10-9
MINPS- Minimum of Packed Single-Precision Floating-Point Values , 
Vol.2-4-26
MINSD instruction , Vol.1-11-7
MINSD- Return Minimum Scalar Double-Precision Floating-Point Value , 
Vol.2-4-29
MINSS instruction , Vol.1-10-9
MINSS- Return Minimum Scalar Single-Precision Floating-Point Value , 
Vol.2-4-31
Mixing 16-bit and 32-bit code
in IA-32 processors , Vol.1-23-33
overview , Vol.3-22-1
MLE, Vol.1-6-1
MMX instruction set
arithmetic instructions , Vol.1-9-6

comparison instructions , Vol.1-9-7
conversion instructions , Vol.1-9-7
data transfer instructions , Vol.1-9-6
EMMS instruction , Vol.1-9-8
logical instructions , Vol.1-9-7
overview , Vol.1-9-5
shift instructions , Vol.1-9-8
MMX instructions
CPUID flag for technology , Vol.2-3-247
encodings , Vol.1-B-38
MMX registers
description of , Vol.1-9-2
MMX technology
64-bit mode , Vol.1-9-2
64-bit packed SIMD data types , Vol.1-4-8
compatibility mode , Vol.1-9-2
compatibility with FPU architecture , Vol.1-9-8
data types , Vol.1-9-3
debugging MMX code , Vol.3-13-5
detecting MMX technology with CPUID instruction , Vol.1-9-8
effect of instruction prefixes on MMX instructions , Vol.1-9-11
effect of MMX instructions on pe nding x87 floating-point exceptions , 
Vol.3-13-5
emulation of the MMX instruction set , Vol.3-13-1
exception handling in MMX code , Vol.1-9-11
exceptions that can occur when executing MMX instructions , 
Vol.3-13-1
IA-32e mode , Vol.1-9-2
instruction set , Vol.1-5-15, Vol.1-9-5
interfacing with MMX code , Vol.1-9-10
introduction of into the IA-32 architecture , Vol.1-23-2introduction to , Vol.1-9-1
memory data formats , Vol.1-9-3
mixing MMX and floating-point instructions , Vol.1-9-10
MMX registers , Vol.1-9-2
programming environment (overview) , Vol.1-9-1
register aliasing , Vol.3-13-1
register mapping , Vol.1-9-11
saturation arithmetic , Vol.1-9-4
SIMD execution environment , Vol.1-9-4
state , Vol.3-13-1
state, saving and restoring , Vol.3-13-3
system programming , Vol.3-13-1
task or context switches , Vol.3-13-4
transitions between x87 FPU - MMX code , Vol.1-9-9
updating MMX technology routines using 128-bit SIMD integer 
instructions , Vol.1-11-24
using MMX code in a multitasking operating system environment , 
Vol.1-9-10
using the EMMS instruction , Vol.1-9-9
using TS flag to control saving of MMX state , Vol.1-14-7
wraparound mode , Vol.1-9-4
Mod field, instruction format , Vol.2-2-3
Mode switching
real-address and protected mode , Vol.3-10-13
to SMM , Vol.4-32-2
Model and stepping information, follow ing processor initialization or reset
, Vol.3-10-5
Model & family information , Vol.2-3-251
Model-specific registers (see MSRs)
Modes of operation
memory models used with , Vol.1-3-9
overview , Vol.1-3-1, Vol.1-3-5
protected mode , Vol.1-3-1
real address mode , Vol.1-3-1
system management mode (SMM) , Vol.1-3-1
Modes of operation (see Operating modes)ModR/M byte
, Vol.2-2-3
16-bit addressing forms , Vol.2-2-5
32-bit addressing forms of , Vol.2-2-6
description of , Vol.2-2-3
MONITOR instruction , Vol.1-5-24, Vol.1-12-5, Vol.2-4-33, Vol.3-26-3
CPUID flag , Vol.2-3-243
feature data , Vol.2-3-251
Moore’s law , Vol.1-2-20
MOV instruction , Vol.1-7-3, Vol.1-7-22, Vol.2-4-35, Vol.3-3-8, Vol.3-5-8
MOV instruction (control registers) , Vol.2-4-39, Vol.2-4-61, Vol.2-4-63
MOV instruction (debug registers) , Vol.2-4-42, Vol.2-4-52
MOV (control registers) instructions , Vol.3-2-24, Vol.3-5-24, Vol.3-9-18, 
Vol.3-10-13
MOV (debug registers) instructions , Vol.3-2-25, Vol.3-5-24, Vol.3-9-18, 
Vol.3-18-11
MOVAPD instruction , Vol.1-11-5, Vol.1-11-23
MOVAPD- Move Aligned Packed Double-Precision Floating-Point Values , 
Vol.2-4-44
MOVAPS instruction , Vol.1-10-7, Vol.1-11-23
MOVAPS- Move Aligned Packed Single-Precision Floating-Point Values , 
Vol.2-4-48
MOVD instruction , Vol.1-9-6, Vol.2-4-52
MOVDDUP instruction , Vol.1-5-24, Vol.1-12-3
MOVDDUP- Replicate Double FP Values , Vol.2-4-58
MOVDQ2Q instruction , Vol.1-11-11, Vol.2-4-77
MOVDQA instruction , Vol.1-11-11, Vol.1-11-23
MOVDQA- Move Aligned Packed Integer Values , Vol.2-4-65
MOVDQU instruction , Vol.1-11-11, Vol.1-11-23
MOVDQU- Move Unaligned Packed Integer Values , Vol.2-4-70
MOVHLPS - Move Packed Single-Precision Floating-Point Values High to 
Low, Vol.2-4-78
MOVHLPS instruction , Vol.1-10-8
MOVHPD instruction , Vol.1-11-6Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -21INDEX
MOVHPD- Move High Packed Double-Precision Floating-Point Values , 
Vol.2-4-80
MOVHPS instruction , Vol.1-10-8
MOVHPS- Move High Packed Single-Precision Floating-Point Values , 
Vol.2-4-82
MOVLHPS instruction , Vol.1-10-8
MOVLPD instruction , Vol.1-11-6
MOVLPD- Move Low Packed Double-Precision Floating-Point Values , 
Vol.2-4-86
MOVLPS instruction , Vol.1-10-7
MOVLPS- Move Low Packed Single-Precision Floating-Point Values , 
Vol.2-4-88
MOVMSKPD instruction , Vol.1-11-6, Vol.2-4-90
MOVMSKPS instruction , Vol.1-10-8, Vol.2-4-92
MOVNTDQ instruction , Vol.1-11-12, Vol.1-11-25, Vol.2-4-109, Vol.3-9-7, 
Vol.3-12-17
MOVNTDQ- Store Packed Integers Using Non-Temporal Hint , Vol.2-4-96
MOVNTI instruction , Vol.1-11-12, Vol.1-11-25, Vol.2-4-109, Vol.3-2-16, 
Vol.3-9-7, Vol.3-12-17
MOVNTPD instruction , Vol.1-11-12, Vol.1-11-25, Vol.3-9-7, Vol.3-12-17
MOVNTPD- Store Packed Double-Preci sion Floating-Point Values Using 
Non-Temporal Hint , Vol.2-4-100
MOVNTPS instruction , Vol.1-10-12, Vol.1-11-25, Vol.3-9-7, Vol.3-12-17
MOVNTPS- Store Packed Single-Precision Floating-Point Values Using 
Non-Temporal Hint , Vol.2-4-102
MOVNTQ instruction , Vol.1-10-12, Vol.1-11-25, Vol.2-4-104, Vol.3-9-7, 
MOVQ instruction , Vol.1-9-6, Vol.2-4-52, Vol.2-4-105
MOVQ2DQ instruction , Vol.1-11-11, Vol.2-4-108
MOVS instruction , Vol.1-3-17, Vol.1-7-18, Vol.2-4-110, Vol.2-4-555
MOVSB instruction , Vol.2-4-110
MOVSD instruction , Vol.1-11-6, Vol.1-11-23, Vol.2-4-110
MOVSD- Move or Merge Scalar Double-Precision Floating-Point Value , 
Vol.2-4-114
MOVSHDUP instruction , Vol.1-5-24, Vol.1-12-3
MOVSHDUP- Replicate Single FP Values , Vol.2-4-117
MOVSLDUP instruction , Vol.1-5-24, Vol.1-12-3
MOVSLDUP- Replicate Single FP Values , Vol.2-4-120
MOVSQ instruction , Vol.2-4-110
MOVSS instruction , Vol.1-10-7, Vol.1-11-23
MOVSS- Move or Merge Scalar Single-Precision Floating-Point Value , 
Vol.2-4-123
MOVSW instruction , Vol.2-4-110
MOVSX instruction , Vol.1-7-8, Vol.2-4-126
MOVSXD instruction , Vol.1-7-8, Vol.2-4-126
MOVUPD instruction , Vol.1-11-6, Vol.1-11-23
MOVUPD- Move Unaligned Packed Double-Precision Floating-Point Values , 
Vol.2-4-128
MOVUPS instruction , Vol.1-10-6, Vol.1-10-7, Vol.1-11-23
MOVUPS- Move Unaligned Packed Single-Precision Floating-Point Values , 
Vol.2-4-132
MOVZX instruction , Vol.1-7-8, Vol.2-4-136
MP (monitor coprocessor) flag
CR0 control register , Vol.3-2-16, Vol.3-2-17, Vol.3-6-32, Vol.3-10-6, 
Vol.3-10-7, Vol.3-13-1, Vol.1-23-8
MS-DOS compatibility mode , Vol.1-8-32
MSR
Model Specific Register , Vol.3-11-37, Vol.3-11-38
MSRs , Vol.1-3-4
architectural , Vol.4-2-3
description of , Vol.3-10-7
list of , Vol.4-2-1
machine-check architecture , Vol.3-16-2
P6 family processors , Vol.4-2-498
Pentium 4 processor , Vol.4-2-64, Vol.4-2-81, Vol.4-2-235, 
Vol.4-2-259, Vol.4-2-275, Vol.4-2-453, Vol.4-2-479
Pentium processors , Vol.4-2-508, Vol.4-2-509
reading and writing , Vol.3-2-20, Vol.3-2-22, Vol.3-2-27
reading & writing in 64-bit mode , Vol.3-2-27
MSRs (model specific registers)reading , Vol.2-4-537
MSR_DEBUBCTLB MSR , Vol.3-18-13, Vol.3-18-30, Vol.3-18-38, 
Vol.3-18-40
MSR_DEBUGCTLA MSR , Vol.3-18-13, Vol.3-18-19, Vol.3-18-25, 
Vol.3-18-26, Vol.3-18-35, Vol.3-20-5, Vol.3-20-9, Vol.3-20-38, Vol.3-20-50, Vol.3-20-77, Vol.3-20-81, Vol.3-20-87, Vol.3-20-101, Vol.3-20-102, Vol.4-2-464
MSR_DEBUGCTLB MSR , Vol.3-18-13, Vol.3-18-38, Vol.3-18-39, 
Vol.4-2-73, Vol.4-2-88, Vol.4-2-98, Vol.4-2-156, Vol.4-2-204, Vol.4-2-261, Vol.4-2-441, Vol.4-2-486, Vol.4-2-496
MSR_EBC_FREQUENCY_ID MSR , Vol.4-2-455, Vol.4-2-456
MSR_EBC_HARD_POWERON MSR , Vol.4-2-454
MSR_EBC_SOFT_POWERON MSR , Vol.4-2-455
MSR_IFSB_CNTR7 MSR , Vol.3-20-127
MSR_IFSB_CTRL6 MSR , Vol.3-20-127
MSR_IFSB_DRDY0 MSR , Vol.3-20-126
MSR_IFSB_DRDY1 MSR , Vol.3-20-126
MSR_IFSB_IBUSQ0 MSR , Vol.3-20-126
MSR_IFSB_IBUSQ1 MSR , Vol.3-20-126
MSR_IFSB_ISNPQ0 MSR , Vol.3-20-126
MSR_IFSB_ISNPQ1 MSR , Vol.3-20-126
MSR_LASTBRANCH _TOS , Vol.4-2-464
MSR_LASTBRANCH_0_TO_IP , Vol.4-2-477
MSR_LASTBRANCH_n MSR , Vol.3-18-19, Vol.3-18-36, Vol.3-18-37, 
Vol.4-2-464
MSR_LASTBRANCH_n_FROM_IP MSR , Vol.3-18-18, Vol.3-18-19, 
Vol.3-18-36, Vol.3-18-37, Vol.4-2-475
MSR_LASTBRANCH_n_TO_IP MSR , Vol.3-18-18, Vol.3-18-19, 
Vol.3-18-36, Vol.3-18-37
MSR_LASTBRANCH_n_TO_LIP MSR , Vol.4-2-477
MSR_LASTBRANCH_TOS MSR , Vol.3-18-36, Vol.3-18-37
MSR_LER_FROM_LIP MSR , Vol.3-18-37, Vol.3-18-39, Vol.4-2-463, 
MSR_LER_TO_LIP MSR , Vol.3-18-37, Vol.3-18-39, Vol.4-2-464
MSR_PEBS_MATRIX_VERT MSR , Vol.4-2-472
MSR_PLATFORM_BRV , Vol.4-2-463, Vol.4-2-464, Vol.4-2-465, 
Vol.4-2-466, Vol.4-2-467, Vol.4-2-468, Vol.4-2-469, Vol.4-2-470, Vol.4-2-471, Vol.4-2-472, Vol.4-2-473, Vol.4-2-474, Vol.4-2-475, Vol.4-2-476, Vol.4-2-477, Vol.4-2-478
MTRR feature flag, CPUID instruction , Vol.3-12-21
MTRRcap MSR , Vol.3-12-21
MTRRfix MSR , Vol.3-12-23
MTRRs , Vol.1-3-4, Vol.3-9-16
base & mask calculations , Vol.3-12-26, Vol.3-12-27
cache control , Vol.3-12-13

description of , Vol.3-10-8, Vol.3-12-20
dual-core processors , Vol.3-9-33
enabling caching , Vol.3-10-7
feature identification , Vol.3-12-21
fixed-range registers , Vol.3-12-23
IA32_MTRRCAP MSR , Vol.3-12-21
initialization of , Vol.3-12-29
large page size considerations , Vol.3-12-33
logical processors , Vol.3-9-33
mapping physical memory with , Vol.3-12-21
memory types and their properties , Vol.3-12-21
precedence of cache controls , Vol.3-12-13
precedences , Vol.3-12-28
programming interface , Vol.3-12-29
state of following a hardware reset , Vol.3-12-20
variable-range registers , Vol.3-12-23, Vol.3-12-25
MUL instruction , Vol.1-7-9, Vol.2-3-23, Vol.2-4-146
MULPD instruction , Vol.1-11-6INDEX
Index-22 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4MULPD- Multiply Packed Double-Precision Floating-Point Values , 
Vol.2-4-148
MULPS instruction , Vol.1-10-8
MULPS- Multiply Packed Single-Precision Floating-Point Values , 
Vol.2-4-151
MULSD instruction , Vol.1-11-6
MULSD- Multiply Scalar Double-Precision Floating-Point Values , 
Vol.2-4-154
MULSS instruction , Vol.1-10-8
MULSS- Multiply Scalar Single-Precision Floating-Point Values , Vol.2-4-156
Multi-byte no operation , Vol.2-4-163, Vol.2-4-165, Vol.1-B-13
Multi-core technology , Vol.1-2-18
See multi-threading support
Multiple-processor management
guaranteed atomic operations , Vol.3-9-2
initialization
MP protocol , Vol.3-9-19
procedure , Vol.3-9-55
memory ordering , Vol.3-9-6
SMM considerations , Vol.4-32-16
Multiple-processor system
local APIC and I/O APICs, Pentium 4 , Vol.3-11-3
local APIC and I/O APIC, P6 family , Vol.3-11-3
Multisegment model , Vol.3-3-4
Multitasking
initialization for , Vol.3-10-10, Vol.3-10-11
initializing IA-32e mode , Vol.3-10-11
linking tasks , Vol.3-8-15
mechanism, description of , Vol.3-8-2
overview , Vol.3-8-1
setting up TSS , Vol.3-10-10
setting up TSS descriptor , Vol.3-10-10
Multi-threading capability , Vol.1-2-18
Multi-threading support
logical processors per package , Vol.3-9-25
microcode updates , Vol.3-9-33
performance monitoring counters , Vol.3-9-33
programming considerations , Vol.3-9-34
See also: Hyper-Threading Technology and dual-core technology
MULX - Unsigned Multiply Without Affecting Flags , Vol.2-4-158
MVMM , Vol.1-6-1, Vol.1-6-5, Vol.1-6-37
MWAIT instruction , Vol.1-5-24, Vol.1-12-5, Vol.2-4-160, Vol.3-26-3
power management extensions , Vol.3-15-35
MXCSR register , Vol.1-11-16, Vol.3-6-53, Vol.3-10-8, Vol.1-14-6
denormals-are-zero (DAZ) flag , Vol.1-10-5, Vol.1-11-2, Vol.1-11-3
description , Vol.1-10-3
flush-to-zero flag (FTZ) , Vol.1-10-4
FXSAVE and FXRSTOR instructions , Vol.1-11-23
LDMXCSR instruction , Vol.1-11-24
load and store instructions , Vol.1-10-12
RC field , Vol.1-4-18
saving on a procedure or function call , Vol.1-11-23
SIMD floating-point mask and flag bits , Vol.1-10-4
SIMD floating-point rounding control field , Vol.1-10-4
state management instructions , Vol.1-5-19, Vol.1-10-12
STMXCSR instruction , Vol.1-11-24
writing to while preventing gene ral-protection exceptions (#GP) , 
Vol.1-11-21
N
NaNs
description of , Vol.1-4-13, Vol.1-4-15encoding of , Vol.1-4-5, Vol.1-4-14
SNaNs vs. QNaNs , Vol.1-4-15
NaN, compatibility, IA-32 processors , Vol.1-23-9
NaN. testing for , Vol.2-3-451
NE (numeric error) flag
CR0 control register , Vol.3-2-15, Vol.3-6-48, Vol.3-10-6, Vol.3-10-7, 
Vol.1-23-8, Vol.1-23-18
Near
Near call
operation , Vol.1-6-4
Near pointer
Near return operation , Vol.1-6-4
NEG instruction , Vol.1-7-8, Vol.2-3-610, Vol.2-4-163, Vol.3-9-4
NetBurst microarchitecture (see Intel NetBurst microarchitecture)
NMI interrupt , Vol.3-2-26, Vol.3-11-3
description of , Vol.3-6-2
handling during initialization , Vol.3-10-9
masking , Vol.1-23-27
receiving when processor is shutdown , Vol.3-6-34
reference information , Vol.3-6-27
vector , Vol.3-6-2
NMI# pin , Vol.3-6-2, Vol.3-6-27
No operation , Vol.2-4-163, Vol.2-4-165, Vol.1-B-12
Nomenclature, used in in struction reference pages , Vol.2-3-1
Nominal CPI method , Vol.3-20-139
Non-arithmetic instructions, x87 FPU , Vol.1-8-25
Nonconforming code segments
accessing , Vol.3-5-11
Non-halted clockticks , Vol.3-20-139
setting up counters , Vol.3-20-139
Non-Halted CPI method , Vol.3-20-139
Nonmaskable interrupt (see NMI)Non-number encodings, floating-point format
, Vol.1-4-13
Non-precise event-based sampling
defined , Vol.3-20-107
used for at-retirement counting , Vol.3-20-117
Non-retirement events , Vol.3-20-106
Non-sleep clockticks , Vol.3-20-139
Non-temporal data
caching of , Vol.1-10-12
description , Vol.1-10-12
temporal vs. non-temporal data , Vol.1-10-12
Non-waiting instructions, x87 FPU , Vol.1-8-24, Vol.1-8-32
NOP instruction , Vol.1-7-23, Vol.2-4-165
Normalized finite number , Vol.1-4-5, Vol.1-4-13, Vol.1-4-14
NOT instruction , Vol.1-7-10, Vol.2-3-610, Vol.2-4-166, Vol.3-9-4
Notation
bit and byte order , Vol.1-1-6, Vol.2-1-5, Vol.3-1-7, Vol.4-1-5
conventions , Vol.3-1-7, Vol.4-1-5
exceptions , Vol.1-1-8, Vol.2-1-7, Vol.3-1-10, Vol.4-1-7
hexadecimal and binary numbers , Vol.1-1-7, Vol.2-1-7, Vol.3-1-8, 
Vol.4-1-6
instruction operands , Vol.1-1-7, Vol.2-1-6
operands , Vol.3-1-8, Vol.4-1-6
notational conventions , Vol.1-1-6
reserved bits , Vol.1-1-6, Vol.2-1-6, Vol.3-1-7, Vol.4-1-5
segmented addressing , Vol.1-1-7, Vol.2-1-7, Vol.3-1-8, Vol.4-1-6
Notational conventions , Vol.2-1-5
NT (nested task) flag
EFLAGS register , Vol.3-2-10, Vol.3-8-10, Vol.3-8-11, Vol.3-8-15
NT (nested task) flag, EFLAGS register , Vol.1-3-17, Vol.1-A-1, 
Vol.2-3-539Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -23INDEX
Null segment selector, checking for , Vol.3-5-6
Numeric overflow exception (#O) , Vol.1-23-10
overview , Vol.1-4-21
x87 FPU , Vol.1-8-4, Vol.1-8-28
Numeric underflow exception (#U) , Vol.1-23-10
overview , Vol.1-4-22
SSE and SSE2 extensions , Vol.1-11-16
x87 FPU , Vol.1-8-4, Vol.1-8-29
NV (invert) flag, PerfEvtSel0 MSR
(P6 family processors) , Vol.3-20-5, Vol.3-20-135
NW (not write-through) flag
CR0 control register , Vol.3-2-15, Vol.3-10-7, Vol.3-12-12, 
Vol.3-12-13, Vol.3-12-16, Vol.3-12-32, Vol.1-23-18, Vol.1-23-19, Vol.1-23-30
O
Obsolete instructions , Vol.1-23-5, Vol.1-23-15
OE (numeric overflow exception) flag
MXCSR register , Vol.1-11-16
x87 FPU status word , Vol.1-8-5, Vol.1-8-29
OF flag, EFLAGS register , Vol.3-6-29
OF (carry) flag, EFLAGS register , Vol.2-3-502
OF (overflow) flag
EFLAGS register , Vol.1-3-16, Vol.1-6-18
OF (overflow) flag, EFLAGS register , Vol.1-A-1, Vol.2-3-32, Vol.2-3-517, 
Vol.2-4-146, Vol.2-4-602, Vol.2-4-628, Vol.2-4-631, Vol.2-4-674
Offset (operand addressing, 64-bit mode) , Vol.1-3-24
Offset (operand addressing) , Vol.1-3-22
OM (numeric overflow exception) mask bit
x87 FPU control word , Vol.1-8-7, Vol.1-8-29
On die digital thermal sensor , Vol.3-15-42
relevant MSRs , Vol.3-15-42
sensor enumeration , Vol.3-15-42
On-Demand
clock modulation enable bits , Vol.3-15-40
On-demand
clock modulation duty cycle bits , Vol.3-15-40
On-die sensors , Vol.3-15-36
Opcode format , Vol.2-2-3
Opcodes
addressing method codes for , Vol.1-A-1
extensions , Vol.1-A-17
extensions tables , Vol.1-A-18
group numbers , Vol.1-A-17
integers
one-byte opcodes , Vol.1-A-7
two-byte opcodes , Vol.1-A-7
key to abbreviations , Vol.1-A-1
look-up examples , Vol.1-A-3, Vol.1-A-17, Vol.1-A-20
ModR/M byte , Vol.1-A-17
one-byte opcodes , Vol.1-A-3, Vol.1-A-7
opcode maps , Vol.1-A-1
operand type codes for , Vol.1-A-2
register codes for , Vol.1-A-3
superscripts in tables , Vol.1-A-6
two-byte opcodes , Vol.1-A-4, Vol.1-A-5, Vol.1-A-7
undefined , Vol.1-23-5
VMX instructions , Vol.1-B-112, Vol.1-B-113
x87 ESC instruction opcodes , Vol.1-A-20
Operand
addressing, modes , Vol.1-3-19
instruction , Vol.1-1-7
size attribute , Vol.1-3-18
sizes, Vol.1-3-9, Vol.1-3-19
x87 FPU instructions , Vol.1-8-15
Operands , Vol.2-1-6
instruction , Vol.3-1-8, Vol.4-1-6operand-size prefix , Vol.3-22-1
Operating modes
64-bit mode , Vol.3-2-7
compatibility mode , Vol.3-2-7
IA-32e mode , Vol.3-2-7, Vol.3-2-8
introduction to , Vol.3-2-7
protected mode , Vol.3-2-7

integers
Operand
SMM (system management mode) , Vol.3-2-7
transitions between , Vol.3-2-8
virtual-8086 mode , Vol.3-2-8
VMX operation
enabling and entering , Vol.3-24-3
OR instruction , Vol.1-7-10, Vol.2-3-610, Vol.2-4-168, Vol.3-9-4
Ordering I/O , Vol.1-19-5
ORPD instruction , Vol.1-11-7
ORPS- Bitwise Logical OR of Packed Si ngle Precision Floating-Point Values
, Vol.2-4-173
ORPS instruction , Vol.1-10-9
OS (operating system mode) flag
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 only) , Vol.3-20-4, 
Vol.3-20-134
OSFXSR (FXSAVE/FXRSTOR support) flag
CR4 control register , Vol.3-2-18, Vol.3-10-8, Vol.1-14-2
OSXMMEXCPT flag
control register CR4 , Vol.1-11-18
OSXMMEXCPT (SIMD floating-point exception support) flag, CR4 control 
register , Vol.3-2-18, Vol.3-6-53, Vol.3-10-8, Vol.1-14-3
OUT instruction , Vol.1-5-9, Vol.1-7-20, Vol.1-19-3, Vol.2-4-176, 
Vol.3-9-16, Vol.3-26-2
Out-of-spec status bit , Vol.3-15-43, Vol.3-15-46
Out-of-spec status log , Vol.3-15-43, Vol.3-15-46
OUTS instruction , Vol.1-5-9, Vol.1-7-20, Vol.1-19-3, Vol.2-4-178, 
Vol.2-4-555
OUTSB instruction , Vol.2-4-178
OUTSD instruction , Vol.2-4-178
OUTSW instruction , Vol.2-4-178
OUTS/OUTSB/OUTSW/OUTSD instruction , Vol.3-18-10, Vol.3-26-2
Overflow exception (#OF) , Vol.1-6-18, Vol.2-3-517, Vol.3-6-29
Overflow, x87 FPU stack , Vol.1-8-26
Overheat interrupt enable bit , Vol.3-15-44, Vol.3-15-47
P
P (present) flag
page-directory entry , Vol.3-6-44
page-table entry , Vol.3-6-44
segment descriptor , Vol.3-3-11
P5_MC_ADDR MSR , Vol.3-16-13, Vol.3-16-29, Vol.4-2-65, Vol.4-2-81, 
Vol.4-2-94, Vol.4-2-148, Vol.4-2-196, Vol.4-2-432, Vol.4-2-480, Vol.4-2-491, Vol.4-2-498, Vol.4-2-509
P5_MC_TYPE MSR , Vol.3-16-13, Vol.3-16-29, Vol.4-2-65, Vol.4-2-81, 
Vol.4-2-94, Vol.4-2-148, Vol.4-2-196, Vol.4-2-433, Vol.4-2-480, Vol.4-2-491, Vol.4-2-498, Vol.4-2-509
P6 family microarchitecture
description of , Vol.1-2-7
history of , Vol.1-2-2
P6 family processors
compatibility with FP software , Vol.1-23-7
description of , Vol.1-1-1, Vol.2-1-1, Vol.3-1-1, Vol.4-1-1
last branch, interrupt, and exception recording , Vol.3-18-40
machine encodings , Vol.1-B-41
MSR supported by , Vol.4-2-498
P6 family microarchitecture , Vol.1-2-7
PABSB instruction , Vol.1-5-25, Vol.1-12-7, Vol.2-4-182, Vol.2-4-196, 
Vol.2-5-144, Vol.2-5-541, Vol.2-5-552, Vol.2-5-567
PABSD instruction , Vol.1-12-8, Vol.2-4-182, Vol.2-4-196, Vol.2-5-144, 
Vol.2-5-541, Vol.2-5-552, Vol.2-5-567
PABSW instruction , Vol.1-5-25, Vol.1-12-8, Vol.2-4-182, Vol.2-4-196, 
Packed
BCD integer indefinite , Vol.1-4-11INDEX
Index-24 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4BCD integers , Vol.1-4-10
bytes , Vol.1-9-3
doublewords , Vol.1-9-3
SIMD data types , Vol.1-4-8
SIMD floating-point values , Vol.1-4-8
SIMD integers , Vol.1-4-8
words , Vol.1-9-3
PACKSSDW instruction , Vol.2-4-188
PACKSSWB instruction , Vol.1-9-7, Vol.2-4-188
PACKUSWB instruction , Vol.1-9-7, Vol.2-4-201
PADDB instruction , Vol.1-9-6
PADDB/PADDW/PADDD/PADDQ - Add Packed Integers , Vol.2-4-206
PADDD instruction , Vol.1-9-6
PADDQ instruction , Vol.1-11-11
PADDSB instruction , Vol.1-9-7, Vol.2-4-213
PADDSW instruction , Vol.1-9-7, Vol.2-4-213
PADDUSB instruction , Vol.1-9-7, Vol.2-4-217
PADDUSW instruction , Vol.1-9-7, Vol.2-4-217
PADDW instruction , Vol.1-9-6
PAE paging
feature flag, CR4 register , Vol.3-2-18, Vol.3-2-19
flag, CR4 control register , Vol.3-3-6, Vol.1-23-18, Vol.1-23-19
Page attribute table (PAT)
compatibility with earlier IA-32 processors , Vol.3-12-36
detecting support for , Vol.3-12-34
IA32_PAT MSR , Vol.3-12-34
introduction to , Vol.3-12-33
memory types that can be encoded with , Vol.3-12-34
MSR, Vol.3-12-13
precedence of cache controls , Vol.3-12-14
programming , Vol.3-12-35
selecting a memory type with , Vol.3-12-35
Page directories , Vol.3-2-6
Page directory
base address (PDBR) , Vol.3-8-5
overview , Vol.3-3-2
Page directory pointers , Vol.3-2-6
Page frame (see Page)Page tables
, Vol.3-2-6
Page-directory entries , Vol.3-12-5
Page-fault exception (#PF) , Vol.3-4-54, Vol.3-6-44, Vol.1-23-21
Pages
disabling protection of , Vol.3-5-1
enabling protection of , Vol.3-5-1
PG flag, CR0 control register , Vol.3-5-1
split, Vol.1-23-15
Page-table entries , Vol.3-12-5, Vol.3-12-19
Paging
combining segment and page-level protection , Vol.3-5-29
combining with segmentation , Vol.3-3-5
defined , Vol.3-3-1
IA-32e mode , Vol.3-2-6
initializing , Vol.3-10-10
large page size MTRR considerations , Vol.3-12-33
mapping segments to pages , Vol.3-4-54
page-fault exception , Vol.3-6-44, Vol.3-6-55, Vol.3-6-56
page-level protection , Vol.3-5-2, Vol.3-5-3, Vol.3-5-27
page-level protection flags , Vol.3-5-28
virtual-8086 tasks , Vol.3-21-7
PALIGNR instruction , Vol.1-5-26, Vol.1-12-8, Vol.2-4-221
PAND instruction , Vol.1-9-7, Vol.2-4-224
PANDN instruction , Vol.1-9-7, Vol.2-4-227
Parameter
passing, between 16- and 32-bit call gates , Vol.3-22-6translation, between 16- and 32-bit code segments , Vol.3-22-6
Parameter passing
argument list , Vol.1-6-7
on stack , Vol.1-6-7
on the stack , Vol.1-6-7
through general-purpose registers , Vol.1-6-7
x87 FPU register stack , Vol.1-8-3
XMM registers , Vol.1-11-23
GETSEC , Vol.1-6-4
PAUSE instruction , Vol.1-11-12, Vol.2-4-230, Vol.3-2-16, Vol.3-26-3
PAVGB instruction , Vol.1-10-11, Vol.2-4-231
PAVGW instruction , Vol.2-4-231
PBi (performance monitoring/breakpoint pins) flags, DEBUGCTLMSR MSR , 
Vol.3-18-39, Vol.3-18-41
PC (pin control) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family 
processors) , Vol.3-20-4, Vol.3-20-135
PC (precision) field, x87 FPU control word , Vol.1-8-7
PC0 and PC1 (pin control) fields, CESR MSR (Pentium processor) , 
PCD pin (Pentium processor) , Vol.3-12-13
PCD (page-level cache disable) flag
CR3 control register , Vol.3-2-17, Vol.3-12-13, Vol.1-23-18, 
Vol.1-23-30
page-directory entries , Vol.3-10-7, Vol.3-12-13, Vol.3-12-33
page-table entries , Vol.3-10-7, Vol.3-12-13, Vol.3-12-33, 
Vol.1-23-31
PCE flag, CR4 register , Vol.2-4-542
PCE (performance monitoring counter enable) flag, CR4 control register , 
Vol.3-2-18, Vol.3-5-24, Vol.3-20-109, Vol.3-20-135
PCE (performance-monitoring counter enable) flag, CR4 control register , 
Vol.1-23-18
PCMPEQB instruction , Vol.1-9-7, Vol.2-4-245
PCMPEQD instruction , Vol.1-9-7, Vol.2-4-245
PCMPEQW instruction , Vol.1-9-7, Vol.2-4-245
PCMPGTB instruction , Vol.1-9-7, Vol.2-4-258
PCMPGTD instruction , Vol.1-9-7, Vol.2-4-258
PCMPGTW instruction , Vol.1-9-7, Vol.2-4-258
PDBR (see CR3 control register)
PDEP - Parallel Bits Deposit , Vol.2-4-277
PE (inexact result exception) flag , Vol.1-11-16
MXCSR register , Vol.1-4-18
x87 FPU status word , Vol.1-4-18, Vol.1-8-4, Vol.1-8-5, Vol.1-8-30
PE (protection enable) flag, CR0 control register , Vol.3-2-17, Vol.3-5-1, 
Vol.3-10-10, Vol.3-10-13, Vol.4-32-9
PE (protection enable) flag, CR0 register , Vol.2-3-605
PEBS records , Vol.3-18-23
PEBS (precise event-based sampling) facilities
availability of , Vol.3-20-119
description of , Vol.3-20-107, Vol.3-20-119
DS save area , Vol.3-18-19
PEBS buffer , Vol.3-18-20, Vol.3-20-119
PEBS records , Vol.3-18-19, Vol.3-18-22
writing a PEBS interrupt service routine , Vol.3-20-120
writing interrupt service routine , Vol.3-18-26
PEBS_UNAVAILABLE flag
Pending break enable , Vol.2-3-247
Pentium 4 processor , Vol.1-1-1, Vol.2-1-1, Vol.3-1-1, Vol.4-1-1
description of , Vol.1-2-3, Vol.1-2-4
MSRs supported , Vol.4-2-64, Vol.4-2-81, Vol.4-2-94, Vol.4-2-113, 
Vol.4-2-115, Vol.4-2-141, Vol.4-2-146, Vol.4-2-453, Vol.4-2-479
Pentium 4 processor supporting Hyper-Threading Technology
Pentium II processor , Vol.1-1-3, Vol.2-1-3, Vol.3-1-3, Vol.4-1-3
Pentium II Xeon processor
description of , Vol.1-2-2Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -25INDEX
Pentium III processor , Vol.1-1-3, Vol.2-1-3, Vol.3-1-3, Vol.4-1-3
Pentium III Xeon processor
Pentium M processor
instructions supported , Vol.1-2-3
last branch, interrupt, and exception recording , Vol.3-18-39
MSRs supported by , Vol.4-2-491
Pentium Pro processor , Vol.1-1-3, Vol.2-1-3, Vol.3-1-3, Vol.4-1-3
Pentium processor , Vol.1-1-1, Vol.2-1-1, Vol.3-1-1, Vol.1-23-7, Vol.4-1-1
compatibility with MCA , Vol.3-16-1

MSR supported by , Vol.4-2-508
performance-monitoring counters , Vol.3-20-136
Pentium processor Extreme Edition
introduction , Vol.1-2-4
Pentium processor family processors
machine encodings , Vol.1-B-37
Pentium processor with MMX technology , Vol.1-2-2
PerfCtr0 and PerfCtr1 MSRs
(P6 family processors) , Vol.3-20-134, Vol.3-20-135
PerfEvtSel0 and PerfEvtSel1 MSRs
(P6 family processors) , Vol.3-20-134
PerfEvtSel0 and PerfEvtSel1 MS Rs (P6 family processors) , Vol.3-20-134
Performance events
architectural , Vol.3-20-1
Intel Core Solo and Intel Core Duo processors , Vol.3-20-1
non-architectural , Vol.3-20-1
Pentium 4 and Intel Xeon processors , Vol.3-18-35
Pentium M processors , Vol.3-18-39
Performance monitoring counters , Vol.1-3-4
Performance state , Vol.3-15-1
Performance-monitoring counters
counted events (Pentium processors) , Vol.3-20-138
CPUID inquiry for , Vol.2-3-252
description of , Vol.3-20-1, Vol.3-20-2
interrupt , Vol.3-11-1
introduction of in IA-32 processors , Vol.1-23-37
monitoring counter overflow (P6 family processors) , Vol.3-20-136
overflow, monitoring (P6 family processors) , Vol.3-20-136
overview of , Vol.3-2-7
P6 family processors , Vol.3-20-133
Pentium II processor , Vol.3-20-133
Pentium Pro processor , Vol.3-20-133
Pentium processor , Vol.3-20-136
reading , Vol.3-2-26, Vol.3-20-135
setting up (P6 family processors) , Vol.3-20-134
software drivers for , Vol.3-20-135
starting and stopping , Vol.3-20-135
PEXT - Parallel Bits Extract , Vol.2-4-279
PEXTRW instruction , Vol.1-10-11, Vol.2-4-284
PF (parity) flag, EFLAGS register , Vol.1-3-16, Vol.1-A-1
PG (paging) flag
CR0 control register , Vol.3-2-15, Vol.3-5-1
PG (paging) flag, CR0 control register , Vol.3-10-10, Vol.3-10-13, 
Vol.1-23-32, Vol.4-32-9
PGE (page global enable) flag, CR4 control register , Vol.3-2-18, 
Vol.3-12-13, Vol.1-23-18, Vol.1-23-19
PHADDD instruction , Vol.1-5-25, Vol.1-12-7, Vol.2-4-287
PHADDSW instruction , Vol.1-5-24, Vol.1-12-7, Vol.2-4-291
PHADDW instruction , Vol.1-5-24, Vol.1-12-7, Vol.2-4-287
PH—Fused Multiply-Add of Packed FP16 Values , Vol.2-5-201
PH—Fused Multiply-Subtract of Packed FP16 Values , Vol.2-5-250
PHSUBD instruction , Vol.1-5-25, Vol.1-12-7, Vol.2-4-295
PHSUBSW instruction , Vol.1-5-25, Vol.1-12-7, Vol.2-4-298
PHSUBW instruction , Vol.1-5-25, Vol.1-12-7, Vol.2-4-295PhysBase field, IA32_MTRR_PHYSBASEn MTRR , Vol.3-12-24, 
Vol.3-12-26
Physical
memory , Vol.1-3-6
Physical address extension
introduction to , Vol.3-3-6
Physical address space
4 GBytes , Vol.3-3-6
64 GBytes , Vol.3-3-6
addressing , Vol.3-2-6
IA-32e mode , Vol.3-3-6
mapped to a task , Vol.3-8-17
mapping with variable-range MTRRs , Vol.3-12-23, Vol.3-12-25
Physical destination mode, local APIC , Vol.3-11-23
PhysMask
IA32_MTRR_PHYSMASKn MTRR , Vol.3-12-24, Vol.3-12-26
Pi, Vol.2-3-405
PINSRW instruction , Vol.1-10-11, Vol.2-4-303, Vol.2-4-431
Pi, x87 FPU constant , Vol.1-8-21
PM (inexact result exception) mask bit
x87 FPU control word , Vol.1-8-7, Vol.1-8-30
PM0/BP0 and PM1/BP1 (performance-m onitor) pins (Pentium processor) , 
Vol.3-20-136, Vol.3-20-137, Vol.3-20-138
PMADDUBSW instruction , Vol.1-5-25, Vol.1-12-8, Vol.2-4-305
PMADDUDSW instruction , Vol.2-4-305
PMADDWD instruction , Vol.1-9-7, Vol.2-4-308
PMAXSW instruction , Vol.1-10-11
PMAXUB instruction , Vol.1-10-11
PMINSW instruction , Vol.1-10-11
PMINUB instruction , Vol.1-10-11
PML4 tables , Vol.3-2-6
PMOVMSKB instruction , Vol.1-10-11
PMULHRSW instruction , Vol.1-5-25, Vol.1-12-8, Vol.2-4-369
PMULHUW instruction , Vol.1-10-12, Vol.2-4-373
PMULHW instruction , Vol.2-4-377
PMULLW instruction , Vol.2-4-385
PMULUDQ instruction , Vol.1-11-11, Vol.2-4-389
Pointer data types , Vol.1-4-6, Vol.1-4-7
Pointers
code-segment pointer size , Vol.3-22-4
far pointer , Vol.1-4-6
limit checking , Vol.3-5-25
near pointer , Vol.1-4-6
validation , Vol.3-5-24
POP instruction , Vol.1-6-1, Vol.1-6-2, Vol.1-7-6, Vol.1-7-22, 
Vol.2-4-392, Vol.3-3-8
POPA instruction , Vol.1-6-7, Vol.1-7-6, Vol.2-4-397
POPAD instruction , Vol.2-4-397
POPF instruction , Vol.1-3-15, Vol.1-6-7, Vol.1-7-21, Vol.1-19-4, 
Vol.2-4-401, Vol.3-6-7, Vol.3-18-11
POPFD instruction , Vol.1-3-15, Vol.1-6-7, Vol.1-7-21, Vol.2-4-401
POPFQ instruction , Vol.2-4-401
POR instruction , Vol.1-9-7, Vol.2-4-405
Power consumption
software controlled clock , Vol.3-15-36, Vol.3-15-40
Power coordination , Vol.1-2-4
Precise event-based sampling (see PEBS)PREFETCHh instruction
, Vol.2-4-408, Vol.3-2-16, Vol.3-12-17
PREFETCHh instructions , Vol.1-10-13, Vol.1-11-25
PREFETCHWT1—Prefetch Vector Data In to Caches with Intent to Write 
and T1 Hint , Vol.2-4-412
Prefixes
Address-size override prefix , Vol.2-2-2
branch hints , Vol.2-2-2
instruction, description of , Vol.2-2-1
legacy prefix encodings , Vol.1-B-1INDEX
Index-26 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4LOCK , Vol.2-2-1, Vol.2-3-610
Operand-size override prefix , Vol.2-2-2
REP or REPE/REPZ , Vol.2-2-1
REPNE/REPNZ , Vol.2-2-1
REP/REPE/REPZ/REPNE/REPNZ , Vol.2-4-554
REX prefix encodings , Vol.1-B-2
Segment override prefixes , Vol.2-2-2
Previous task link field, TSS , Vol.3-8-5, Vol.3-8-15, Vol.3-8-16
Privilege levels
checking when accessing data segments , Vol.3-5-8
checking, for call gates , Vol.3-5-15
checking, when transferring program control between code segments , 
Vol.3-5-10
description of , Vol.1-6-8, Vol.3-5-6
inter-privilege level calls , Vol.1-6-7
protection rings , Vol.1-6-8, Vol.3-5-8
stack switching , Vol.1-6-14
Privileged instructions , Vol.3-5-23
Procedure calls
far call , Vol.1-6-4
for block-structured languages , Vol.1-6-20
inter-privilege level call , Vol.1-6-8
linking , Vol.1-6-3
near call , Vol.1-6-4
overview , Vol.1-6-1
return instruction po inter (EIP register) , Vol.1-6-3
saving procedure state information , Vol.1-6-7
stack , Vol.1-6-1
stack switching , Vol.1-6-8
to exception handler procedure , Vol.1-6-13
to exception task , Vol.1-6-18
to interrupt handler procedure , Vol.1-6-13
to interrupt task , Vol.1-6-18
to other privilege levels , Vol.1-6-7
types of , Vol.1-6-1
Processor families
06H, Vol.3-17-1
0FH, Vol.3-17-1
Processor identification
earlier Intel architecture processors , Vol.1-20-1
early processors , Vol.1-20-1
notes on where to start , Vol.1-20-1
using CPUID , Vol.1-20-1
using CPUID instruction , Vol.1-20-1
Processor management
initialization , Vol.3-10-1
microcode update facilities , Vol.3-10-27
See also: multiple-processor management
Processor ordering, description of , Vol.3-9-6
Processor state information, saving , Vol.1-6-7
PROCHOT# log , Vol.3-15-43, Vol.3-15-46
Protected mode
IDT initialization , Vol.3-10-10
initialization for , Vol.3-10-9
I/O, Vol.1-19-3
memory models used , Vol.1-3-9
mixing 16-bit and 32-bit code modules , Vol.3-22-1
mode switching , Vol.3-10-13
overview , Vol.1-3-1
PE flag, CR0 register , Vol.3-5-1
switching to , Vol.3-5-1, Vol.3-10-13
system data structures required during initialization , Vol.3-10-9
Protection
combining segment & page-level , Vol.3-5-29
disabling , Vol.3-5-1
enabling , Vol.3-5-1
flags used for page-level protection , Vol.3-5-2, Vol.3-5-3
flags used for segment-level protection , Vol.3-5-2IA-32e mode , Vol.3-5-3
of exception, interrupt-handler procedures , Vol.3-6-16
overview of , Vol.3-5-1
page level , Vol.3-5-1, Vol.3-5-27, Vol.3-5-28, Vol.3-5-30
page level, overriding , Vol.3-5-29
read/write, page level , Vol.3-5-28
segment level , Vol.3-5-1
user/supervisor type , Vol.3-5-28
Protection rings , Vol.1-6-8, Vol.3-5-8
PSADBW instruction , Vol.1-10-12, Vol.2-4-412
PSE (page size extension) flag
CR4 control register , Vol.3-2-17, Vol.3-12-20, Vol.1-23-18, 
Vol.1-23-19
PSE-36 page size extension , Vol.3-3-6
Pseudo-functions
VMfail , Vol.3-31-2
VMfailInvalid , Vol.3-31-2
VMfailValid , Vol.3-31-2
VMsucceed , Vol.3-31-2
Pseudo-infinity , Vol.1-23-9
Pseudo-NaN , Vol.1-23-9
Pseudo-zero , Vol.1-23-9
PSHUFB instruction , Vol.1-5-25, Vol.1-12-8, Vol.2-4-416
PSHUFD instruction , Vol.1-11-11, Vol.2-4-420
PSHUFHW instruction , Vol.1-11-11, Vol.2-4-424
PSHUFLW instruction , Vol.1-11-11, Vol.2-4-427
PSHUFW instruction , Vol.1-10-12, Vol.1-11-11, Vol.2-4-430
PSIGNB instruction , Vol.2-4-431
PSIGNB/W/D instruction , Vol.1-5-25, Vol.1-12-8
PSIGND instruction , Vol.2-4-431
PSIGNW instruction , Vol.2-4-431
PSLLD instruction , Vol.1-9-8, Vol.2-4-437
PSLLDQ instruction , Vol.1-11-11, Vol.2-4-435
PSLLQ instruction , Vol.1-9-8, Vol.2-4-437
PSLLW instruction , Vol.1-9-8, Vol.2-4-437
PSRAD instruction , Vol.2-4-449
PSRAW instruction , Vol.2-4-449
PSRLD instruction , Vol.2-4-461
PSRLDQ instruction , Vol.1-11-11, Vol.2-4-459
PSRLQ instruction , Vol.2-4-461
PSRLW instruction , Vol.2-4-461
P-state , Vol.3-15-1

PSUBB instruction , Vol.1-9-6, Vol.2-4-473
PSUBD instruction , Vol.1-9-6, Vol.2-4-473
PSUBQ instruction , Vol.1-11-11, Vol.2-4-481
PSUBSB instruction , Vol.1-9-7, Vol.2-4-484
PSUBSW instruction , Vol.1-9-7, Vol.2-4-484
PSUBUSB instruction , Vol.1-9-7, Vol.2-4-488
PSUBUSW instruction , Vol.1-9-7, Vol.2-4-488
PSUBW instruction , Vol.1-9-6, Vol.2-4-473
PTEST- Packed Bit Test , Vol.2-3-576
PUNPCKHBW instruction , Vol.1-9-7, Vol.2-4-496
PUNPCKHDQ instruction , Vol.1-9-7, Vol.2-4-496
PUNPCKHQDQ instruction , Vol.1-11-11, Vol.2-4-496
PUNPCKHWD instruction , Vol.1-9-7, Vol.2-4-496
PUNPCKLBW instruction , Vol.1-9-7, Vol.2-4-506
PUNPCKLDQ instruction , Vol.1-9-7, Vol.2-4-506
PUNPCKLQDQ instruction , Vol.1-11-11, Vol.2-4-506
PUNPCKLWD instruction , Vol.1-9-7, Vol.2-4-506
PUSH instruction , Vol.1-6-1, Vol.1-6-2, Vol.1-7-5, Vol.1-7-22, 
Vol.2-4-516, Vol.1-23-7
PUSHA instruction , Vol.1-6-7, Vol.1-7-5, Vol.2-4-519
PUSHAD instruction , Vol.2-4-519
PUSHF instruction , Vol.1-3-15, Vol.1-6-7, Vol.1-7-21, Vol.2-4-521, 
Vol.3-6-7, Vol.1-23-7
PUSHFD instruction , Vol.1-3-15, Vol.1-6-7, Vol.1-7-21, Vol.2-4-521
PVI (protected-mode virtual interrupts) flag
CR4 control register , Vol.3-2-11, Vol.3-2-17, Vol.1-23-18
PWT pin (Pentium processor) , Vol.3-12-13
PWT (page-level write-through) flagCombined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -27INDEX
page-table entries , Vol.3-10-7, Vol.3-12-33, Vol.1-23-31
PXOR instruction , Vol.1-9-7, Vol.2-4-523
Q
QNaN floating-point indefinite , Vol.1-4-5, Vol.1-4-17, Vol.1-8-14
QNaNs
description of , Vol.1-4-15
effect on COMISD and UCOMISD , Vol.1-11-7
encodings , Vol.1-4-5
operating on , Vol.1-4-16
rules for generating , Vol.1-4-16
using in applications , Vol.1-4-16
QNaN, compatibility, IA-32 processors , Vol.1-23-9
Quadword , Vol.1-4-1, Vol.1-9-3
Quiet NaN (see QNaN)
R
R8D-R15D registers , Vol.1-3-12
R8-R15 registers , Vol.1-3-12
RAX register , Vol.1-3-12
RBP register , Vol.1-3-12, Vol.1-6-4
RBX register , Vol.1-3-12
RC (rounding control) field
MXCSR register , Vol.1-4-18, Vol.1-10-4
x87 FPU control word , Vol.1-4-18, Vol.1-8-8
RC (rounding control) field, x87 FPU control word , Vol.2-3-398, 
Vol.2-3-405, Vol.2-3-437
RCL instruction , Vol.1-7-13, Vol.2-4-526
RCPPS instruction , Vol.1-10-8, Vol.2-4-531
RCPSS instruction , Vol.1-10-8, Vol.2-4-533
RCR instruction , Vol.1-7-13, Vol.2-4-526
RCX register , Vol.1-3-12
RDI register , Vol.1-3-12
RDMSR instruction , Vol.2-4-537, Vol.2-4-550, Vol.3-2-20, Vol.3-2-22, 
Vol.3-2-27, Vol.3-5-24, Vol.3-18-37, Vol.3-18-41, Vol.3-18-43, Vol.3-20-109, Vol.3-20-134, Vol.3-20-135, Vol.3-20-136, Vol.1-23-5, Vol.1-23-36, Vol.3-26-4, Vol.3-26-9
RDPMC instruction , Vol.2-4-540, Vol.2-4-542, Vol.1-6-11, Vol.3-2-26, 
Vol.3-5-24, Vol.3-20-109, Vol.3-20-134, Vol.3-20-135, Vol.1-23-4, Vol.1-23-18, Vol.1-23-37, Vol.3-26-4
in 64-bit mode , Vol.3-2-27
RDRAND , Vol.1-7-24
RDTSC instruction , Vol.2-4-544, Vol.2-4-550, Vol.2-4-552, Vol.3-2-26, 
Vol.3-5-24, Vol.3-18-43, Vol.1-23-5, Vol.3-26-4, Vol.3-26-10
RDX register , Vol.1-3-12
reading sensors , Vol.3-15-42
Read/write
protection, page level , Vol.3-5-28
rights, checking , Vol.3-5-25
Real address mode
handling exceptions in , Vol.1-6-18
handling interrupts in , Vol.1-6-18
memory model , Vol.1-3-7, Vol.1-3-8
memory model used , Vol.1-3-9
not in 64-bit mode , Vol.1-3-9
Real numbers
continuum , Vol.1-4-11
encoding , Vol.1-4-13, Vol.1-4-14
notation , Vol.1-4-12, Vol.1-14-18
system , Vol.1-4-11
Real-address mode
8086 emulation , Vol.3-21-1
address translation in , Vol.3-21-2description of , Vol.3-21-1
exceptions and interrupts , Vol.3-21-6
IDT initialization , Vol.3-10-8
IDT, changing base and limit of , Vol.3-21-5
IDT, structure of , Vol.3-21-5
IDT, use of , Vol.3-21-4
initialization , Vol.3-10-8
instructions supported , Vol.3-21-3
interrupt and exception handling , Vol.3-21-4
interrupts , Vol.3-21-6
native 16-bit mode , Vol.3-22-1
overview of , Vol.3-21-1
registers supported , Vol.3-21-3
switching to , Vol.3-10-14
Recursive task switching , Vol.3-8-16
Register operands
legacy modes , Vol.1-3-20
Register stack, x87 FPU , Vol.1-8-1
Registers
64-bit mode , Vol.1-3-12, Vol.1-3-15
control registers , Vol.1-3-4
CR in 64-bit mode , Vol.1-3-5
debug registers , Vol.1-3-4
EFLAGS register , Vol.1-3-11, Vol.1-3-15
general purpose registers , Vol.1-3-11
instruction pointer , Vol.1-3-11
machine check registers , Vol.1-3-4
memory management registers , Vol.1-3-4
MMX registers , Vol.1-3-2, Vol.1-9-2
MTRRs , Vol.1-3-4
performance monitoring counters , Vol.1-3-4
REX prefix , Vol.1-3-12
segment registers , Vol.1-3-11, Vol.1-3-13
x87 FPU registers , Vol.1-8-1
XMM registers , Vol.1-3-2, Vol.1-10-3
Reg/opcode field, instruction format , Vol.2-2-3
Related literature , Vol.1-1-9, Vol.2-1-8, Vol.3-1-10, Vol.4-1-8
Remainder, x87 FPU operation , Vol.2-3-419
REP/REPE/REPZ/REPNE/REPNZ
prefixes , Vol.1-7-19, Vol.1-19-3
REP/REPE/REPZ/REPNE/REPNZ prefixes , Vol.2-3-196, Vol.2-3-512, 
Vol.2-4-178, Vol.2-4-554
Requested privilege level (see RPL)
Reserved
use of reserved bits , Vol.2-1-6
Reserved bits , Vol.1-1-6, Vol.3-1-7, Vol.1-23-2, Vol.4-1-5
RESET pin , Vol.1-3-15
RESET# pin , Vol.3-6-3, Vol.1-23-16
RESET# signal , Vol.3-2-26
Resolution in degrees , Vol.3-15-43
Responding logical processor , Vol.1-6-4
responding logical processor , Vol.1-6-4, Vol.1-6-5
Restarting program or task, following an exception or interrupt , Vol.3-6-5
Restricting addressable domain , Vol.3-5-28
RET instruction , Vol.1-3-18, Vol.1-6-3, Vol.1-6-4, Vol.1-7-15, Vol.1-7-22, 
Vol.2-4-558, Vol.3-5-10, Vol.3-5-20, Vol.3-22-6
Return instruction pointer , Vol.1-6-3
Returning
from a called procedure , Vol.3-5-20
from an interrupt or exception handler , Vol.3-6-13
Returns, from procedure calls
exception handler, return from , Vol.1-6-13
far return , Vol.1-6-5
inter-privilege level return , Vol.1-6-8
interrupt handler, return from , Vol.1-6-13
near return , Vol.1-6-4INDEX
Index-28 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4REX prefixes , Vol.1-3-2, Vol.1-3-12, Vol.1-3-19
addressing modes , Vol.2-2-9
and INC/DEC , Vol.2-2-8
encodings , Vol.2-2-8, Vol.1-B-2
field names , Vol.2-2-9
ModR/M byte , Vol.2-2-8
overview , Vol.2-2-7
REX.B , Vol.2-2-8
REX.R , Vol.2-2-8
REX.W , Vol.2-2-8
special encodings , Vol.2-2-11
RF (resume) flag
EFLAGS register , Vol.3-2-10, Vol.3-6-7
RF (resume) flag, EFLAGS register , Vol.1-3-17, Vol.1-A-1
RFLAGS , Vol.1-3-18
RFLAGS register , Vol.1-7-22
See EFLAGS register
RIP register , Vol.1-6-4
relation to EIP , Vol.1-7-2
RIP-relative addressing , Vol.2-2-12
ROL instruction , Vol.1-7-13, Vol.2-4-526
ROR instruction , Vol.1-7-13, Vol.2-4-526
RORX - Rotate Right Logical Without Affecting Flags , Vol.2-4-571
Rounding
modes, floating-point operations , Vol.1-4-18, Vol.2-4-573
modes, x87 FPU , Vol.1-8-8
toward zero (truncation) , Vol.1-4-18
Rounding control (RC) field
MXCSR register , Vol.1-4-18, Vol.1-10-4, Vol.2-4-573
x87 FPU control word , Vol.1-4-18, Vol.1-8-8, Vol.2-4-573
Rounding, round to integer, x87 FPU operation , Vol.2-3-423
ROUNDPD- Round Packed Double-Precision Floating-Point Values , 
Vol.2-4-675
RPL
description of , Vol.3-3-8, Vol.3-5-8
field, segment selector , Vol.3-5-2
RPL field , Vol.2-3-93
RSI register , Vol.1-3-12
RSM instruction , Vol.2-4-581, Vol.3-2-26, Vol.3-9-18, Vol.1-23-5, 
Vol.3-26-4, Vol.4-32-1, Vol.4-32-2, Vol.4-32-3, Vol.4-32-13, Vol.4-32-15, Vol.4-32-18
RSP register , Vol.1-3-12, Vol.1-6-4
RSQRTPS instruction , Vol.1-10-8, Vol.2-4-583
RSQRTSS instruction , Vol.1-10-8, Vol.2-4-585
RsvdZ , Vol.3-11-40
R/m field, instruction format , Vol.2-2-3
R/S# pin , Vol.3-6-3
R/W (read/write) flag
page-directory entry , Vol.3-5-1, Vol.3-5-2, Vol.3-5-28
page-table entry , Vol.3-5-1, Vol.3-5-2, Vol.3-5-28
DR7 register , Vol.3-18-5, Vol.1-23-20
S
segment descriptor , Vol.3-3-11, Vol.3-3-12, Vol.3-5-2, Vol.3-5-5
Safer Mode Extensions , Vol.1-6-1
SAHF instruction , Vol.1-3-15, Vol.1-7-21, Vol.2-4-590
SAL instruction , Vol.1-7-10, Vol.2-4-592
SAR instruction , Vol.1-7-11, Vol.2-4-592
Saturation arithmetic (MMX instructions) , Vol.1-9-4
SBB instruction , Vol.1-7-8, Vol.2-3-610, Vol.2-4-601, Vol.3-9-4
Scalar operations
defined , Vol.1-10-7, Vol.1-11-5
scalar double-precision FP operands , Vol.1-11-5
scalar single-precision FP operands , Vol.1-10-7
Scale (operand addressing) , Vol.1-3-22, Vol.1-3-23, Vol.1-3-24, Vol.2-2-3
Scale, x87 FPU operation , Vol.1-8-21, Vol.2-3-429
Scaling bias value , Vol.1-8-29, Vol.1-8-30Scan string instructions , Vol.2-4-604

S
SCAS instruction , Vol.1-3-17, Vol.1-7-18, Vol.2-4-555, Vol.2-4-604
SCASB instruction , Vol.2-4-604
SCASD instruction , Vol.2-4-604
SCASW instruction , Vol.2-4-604
Segment
defined , Vol.1-3-7
descriptor, segment limit , Vol.2-3-618
limit, Vol.2-3-618
maximum number , Vol.1-3-7
registers, moving values to and from , Vol.2-4-36
selector, RPL field , Vol.2-3-93
Segment descriptors
access rights , Vol.3-5-24
access rights, invalid values , Vol.1-23-19
base address fields , Vol.3-3-10
code type , Vol.3-5-2
data type , Vol.3-5-2
description of , Vol.3-2-4, Vol.3-3-9
DPL (descriptor privilege level) field , Vol.3-3-11, Vol.3-5-2
D/B (default operation size/default stack pointer size and/or upper 
bound) flag , Vol.3-3-11, Vol.3-5-4
E (expansion direction) flag , Vol.3-5-2, Vol.3-5-4
G (granularity) flag , Vol.3-3-11, Vol.3-5-2, Vol.3-5-4
limit field , Vol.3-5-2, Vol.3-5-4
loading , Vol.1-23-20
P (segment-present) flag , Vol.3-3-11
S (descriptor type) flag , Vol.3-3-11, Vol.3-3-12, Vol.3-5-2, Vol.3-5-5
segment limit field , Vol.3-3-10
system type , Vol.3-5-2
tables , Vol.3-3-14
TSS descriptor , Vol.3-8-5, Vol.3-8-6
type field , Vol.3-3-10, Vol.3-3-12, Vol.3-5-2, Vol.3-5-5
type field, encoding , Vol.3-3-14
when P (segment-present) flag is clear , Vol.3-3-11
Segment limit
field, segment descriptor , Vol.3-3-10
Segment not present exception (#NP) , Vol.3-3-11
Segment override prefixes , Vol.1-3-21
Segment registers
64-bit mode , Vol.1-3-15, Vol.1-3-22, Vol.1-7-2
default usage rules , Vol.1-3-21
description of , Vol.1-3-11, Vol.1-3-13, Vol.3-3-8
IA-32e mode , Vol.3-3-9
Segment selector
description of , Vol.1-3-7, Vol.1-3-13
segment override prefixes , Vol.1-3-21
specifying , Vol.1-3-21
Segment selectors
description of , Vol.3-3-7
index field , Vol.3-3-7
null, Vol.3-5-6
null in 64-bit mode , Vol.3-5-6
RPL field , Vol.3-3-8, Vol.3-5-2
TI (table indicator) flag , Vol.3-3-7
Segmented addressing , Vol.2-1-7, Vol.3-1-8, Vol.4-1-6
Segmented memory model , Vol.1-1-7, Vol.1-3-7, Vol.1-3-13
Segment-not-present exception (#NP) , Vol.3-6-38
Segments
64-bit mode , Vol.3-3-5
basic flat model , Vol.3-3-3
code type , Vol.3-3-12
combining segment, page-level protection , Vol.3-5-29
combining with paging , Vol.3-3-5
compatibility mode , Vol.3-3-5
data type , Vol.3-3-12
enabling protection of , Vol.3-5-1Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -29INDEX
mapping to pages , Vol.3-4-54
multisegment usage model , Vol.3-3-4
protected flat model , Vol.3-3-3
segment-level protection , Vol.3-5-2, Vol.3-5-3
segment-not-present exception , Vol.3-6-38
system , Vol.3-2-4
types, checking access rights , Vol.3-5-24
typing , Vol.3-5-5
using , Vol.3-3-2
wraparound , Vol.1-23-34
SELF IPI register , Vol.3-11-38
Self Snoop , Vol.2-3-247
Self-modifying code, effect on caches , Vol.3-12-18
GETSEC , Vol.1-6-2, Vol.1-6-4, Vol.1-6-5
SENTER sleep state , Vol.1-6-10
Serialization of I/O instructions , Vol.1-19-5
Serializing , Vol.3-9-17
Serializing instructions , Vol.1-19-5
CPUID , Vol.3-9-17
HT technology , Vol.3-9-30
non-privileged , Vol.3-9-17
privileged , Vol.3-9-17
SETcc instructions , Vol.1-3-17, Vol.1-7-14, Vol.2-4-611
SF (sign) flag, EFLAGS register , Vol.1-3-16, Vol.1-A-1, Vol.2-3-32
SF (stack fault) flag, x87 FPU status word , Vol.1-8-6, Vol.1-8-26, 
Vol.1-23-8
SFENCE instruction , Vol.1-10-14, Vol.1-11-12, Vol.1-11-25, Vol.2-4-616, 
Vol.3-2-16, Vol.3-9-7, Vol.3-9-16, Vol.3-9-17, Vol.3-9-18
SGDT instruction , Vol.2-4-617, Vol.3-2-24, Vol.3-3-15
SHAF instruction , Vol.2-4-590
Shared resources
mapping of , Vol.3-9-34
SH—Fused Multiply-Add of Scalar FP16 Values , Vol.2-5-219
SH—Fused Multiply-Subtract of Scalar FP16 Values , Vol.2-5-265
Shift instructions , Vol.2-4-592
SHL instruction , Vol.1-7-10, Vol.2-4-592
SHLD instruction , Vol.1-7-12, Vol.2-4-628
SHR instruction , Vol.1-7-11, Vol.2-4-592
SHRD instruction , Vol.1-7-12, Vol.2-4-631
Shuffle instructions
SSE extensions , Vol.1-10-9
SSE2 extensions , Vol.1-11-7
SHUFPD - Shuffle Packed Double Precision Floating-Point Values , 
Vol.2-4-634, Vol.2-4-675
SHUFPD instruction , Vol.1-11-7
SHUFPS - Shuffle Packed Single Precision Floating-Point Values , 
Vol.2-4-639
Shutdown
resulting from double fault , Vol.3-6-34
resulting from out of IDT limit condition , Vol.3-6-34
SI register , Vol.1-3-12
32-bit addressing forms of , Vol.2-2-7, Vol.2-2-21
SIDT instruction , Vol.2-4-617, Vol.2-4-643, Vol.3-2-24, Vol.3-3-16, 
Vol.3-6-9
Signaling NaN (see SNaN)
Signed
infinity , Vol.1-4-15
integers, description of , Vol.1-4-4
integers, encodings , Vol.1-4-4
zero, Vol.1-4-14
Significand, extracting from floating-point number , Vol.2-3-470
Significand, of floating-point number , Vol.1-4-11
Sign, floating-point number , Vol.1-4-11
SIMD floating-point exception (#XM) , Vol.1-11-18, Vol.3-2-18, 
Vol.3-6-53, Vol.3-10-8
SIMD floating-point exceptions
denormal operand exception (#D) , Vol.1-11-15
description of , Vol.3-6-53, Vol.1-14-5
divide-by-zero (#Z) , Vol.1-11-15exception conditions , Vol.1-11-14
exception handlers , Vol.1-D-1
handler , Vol.1-14-3
inexact result exception (#P) , Vol.1-11-16
invalid operation exception (#I) , Vol.1-11-14
list of , Vol.1-11-13
numeric overflow exception (#O) , Vol.1-11-15
numeric underflow exception (#U) , Vol.1-11-16
precision exception (#P) , Vol.1-11-16
software handling , Vol.1-11-18
summary of , Vol.1-C-1
support for , Vol.3-2-18
writing exception handlers for , Vol.1-D-1
SIMD floating-point exceptions, unmasking, effects of , Vol.2-3-587, 
SIMD floating-point flag bits , Vol.1-10-4
SIMD floating-point mask bits , Vol.1-10-4
SIMD (single-instruction, multiple-data)
execution model , Vol.1-2-2, Vol.1-9-4
instructions , Vol.1-2-14, Vol.1-5-19, Vol.1-10-7
MMX instructions , Vol.1-5-15
operations, on packed double-pre cision floating-point operands , 
Vol.1-11-4
operations, on packed single-precision floating-point operands , 
Vol.1-10-6
packed data types , Vol.1-4-8
SSE2 instructions , Vol.1-11-4, Vol.1-12-2, Vol.1-12-6
Sine, x87 FPU operation , Vol.1-8-20, Vol.2-3-431, Vol.2-3-433
Single-precision floating-point format , Vol.1-4-4
Single-stepping
breakpoint exception condition , Vol.3-18-11
on branches , Vol.3-18-14
on exceptions , Vol.3-18-14
on interrupts , Vol.3-18-14
TF (trap) flag, EFLAGS register , Vol.3-18-11
SINIT , Vol.1-6-4
SLDT instruction , Vol.2-4-645, Vol.3-2-24
Sleep , Vol.1-2-4
SLTR instruction , Vol.3-3-16
Smart cache , Vol.1-2-4
Smart memory access , Vol.1-2-11
smart memory access , Vol.1-2-4
SMBASE
default value , Vol.4-32-4
relocation of , Vol.4-32-14
SMI handler
description of , Vol.4-32-1
execution environment for , Vol.4-32-9
exiting from , Vol.4-32-3
VMX treatment of , Vol.4-32-16
SMI interrupt , Vol.3-2-26, Vol.3-11-3
description of , Vol.4-32-1, Vol.4-32-2
priority , Vol.4-32-3
switching to SMM , Vol.4-32-2
synchronous and asynchronous , Vol.4-32-12
SMI# pin , Vol.3-6-3, Vol.4-32-2, Vol.4-32-15
SMM
asynchronous SMI , Vol.4-32-12
auto halt restart , Vol.4-32-14
executing the HLT instruction in , Vol.4-32-14
handling exceptions and interrupts , Vol.4-32-11
I/O instruction restart , Vol.4-32-15
I/O state implementation , Vol.4-32-12
native 16-bit mode , Vol.3-22-1INDEX
Index-30 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4overview , Vol.1-3-1
overview of , Vol.4-32-1
revision identifier , Vol.4-32-13
revision identifier field , Vol.4-32-13
switching to , Vol.4-32-2
switching to from other operating modes , Vol.4-32-2
synchronous SMI , Vol.4-32-12
default RSM treatment , Vol.4-32-18
default SMI delivery , Vol.4-32-17
dual-monitor treatment , Vol.4-32-19
overview , Vol.4-32-2
protecting CR4.VMXE , Vol.4-32-19
RSM instruction , Vol.4-32-18
SMM monitor , Vol.4-32-2
SMM VM exits , Vol.3-28-1, Vol.4-32-19
SMM-transfer VMCS , Vol.4-32-19
SMM-transfer VMCS pointer , Vol.4-32-19
VMCS pointer preservation , Vol.4-32-17
VMX-critical state , Vol.4-32-17
SMRAM
caching , Vol.4-32-8
state save map , Vol.4-32-4
structure of , Vol.4-32-4
SMSW instruction , Vol.2-4-647, Vol.3-2-24, Vol.3-26-10
SNaNs
typical uses of , Vol.1-4-15
SNaN, compatibility, IA-32 processors , Vol.1-23-9, Vol.1-23-14
Snooping mechanism , Vol.3-12-6
Software compatibility , Vol.1-1-6
Software controlled clock
modulation control bits , Vol.3-15-40
power consumption , Vol.3-15-36, Vol.3-15-40
Software interrupts , Vol.3-6-4
Software-controlled bus locking , Vol.3-9-4
SP register , Vol.1-3-12

SMRAM
SNaNs
Speculative execution , Vol.1-2-7, Vol.1-2-9
Spin-wait loops
programming with PAUSE instruction , Vol.1-11-12
Split pages , Vol.1-23-15
Spurious interrupt, local APIC , Vol.3-11-32
SQRTPD instruction , Vol.1-11-6
SQRTPD- Square Root of Double-Precision Floating-Point Values , 
SQRTPD—Square Root of Double-Precision Floating-Point Values , 
Vol.2-4-649
SQRTPS instruction , Vol.1-10-8
SQRTPS- Square Root of Single-Precision Floating-Point Values , 
Vol.2-4-652
SQRTSD - Compute Square Root of Scal ar Double-Precision Floating-Point 
Value , Vol.2-4-655, Vol.2-4-675
SQRTSD instruction , Vol.1-11-6
SQRTSS - Compute Square Root of Scal ar Single-Precision Floating-Point 
Value , Vol.2-4-657
SQRTSS instruction , Vol.1-10-8
Square root, Fx87 PU operation , Vol.2-3-435
SS register , Vol.1-3-13, Vol.1-3-14, Vol.1-6-1, Vol.2-3-588, Vol.2-4-36, 
Vol.2-4-393
SSE extensions
128-bit packed single-precision data type , Vol.1-10-5
64-bit mode , Vol.1-10-3
64-bit SIMD integer instructions , Vol.1-10-11
branching on arithmetic operations , Vol.1-11-24
cacheability control instructions , Vol.1-10-12
cacheability hint instructions , Vol.1-11-25
cacheability instruction encodings , Vol.1-B-47caller-save requirement for procedure and function calls , Vol.1-11-24
checking for SSE and SSE2 support , Vol.1-11-19
checking for with CPUID , Vol.1-14-2
checking support for FXSAVE/FXRSTOR , Vol.1-14-2
comparison instructions , Vol.1-10-9
compatibility mode , Vol.1-10-3
compatibility of SIMD and x87 FPU floating-point data types , 
Vol.1-11-22
conversion instructions , Vol.1-10-11
CPUID feature flag , Vol.3-10-8
data movement instructions , Vol.1-10-7
data types , Vol.1-10-5, Vol.1-12-1
denormals-are-zeros mode , Vol.1-10-5
divide by zero exception (#Z) , Vol.1-11-15
EM flag , Vol.3-2-16
emulation of , Vol.1-14-6
exceptions , Vol.1-11-13
facilities for automatic saving of state , Vol.1-14-6, Vol.1-14-7
floating-point encodings , Vol.1-B-42
floating-point format , Vol.1-4-11
flush-to-zero mode , Vol.1-10-4
generating SIMD FP exceptions , Vol.1-11-16
handling combinations of masked and unmasked exceptions , 
Vol.1-11-18
handling masked exceptions , Vol.1-11-17
handling SIMD floating-point exceptions in software , Vol.1-11-18
handling unmasked exceptions , Vol.1-11-18
instruction encodings , Vol.1-B-42
instruction prefixes, effect on SSE and SSE2 instructions , Vol.1-11-25
instruction set , Vol.1-5-17, Vol.1-10-6
integer instruction encodings , Vol.1-B-46
interaction of SIMD and x87 FPU floating-point exceptions , 
interaction of SSE and SSE2 instructions with x87 FPU and MMX 
instructions , Vol.1-11-22
interfacing with SSE and SSE2 procedures and functions , Vol.1-11-23
intermixing packed and scalar floating-point
and 128-bit SIMD integer instructions
and data ....................., Vol.1-11-22
introduction , Vol.1-2-2
introduction of into the IA-32 architecture , Vol.1-23-3
logical instructions , Vol.1-10-9
masked responses to invalid arithmetic operations , Vol.1-11-14
memory ordering encodings , Vol.1-B-47
memory ordering instruction , Vol.1-10-14
MMX technology compatibility , Vol.1-10-5
MXCSR register , Vol.1-10-3
MXCSR state management instructions , Vol.1-10-12
non-temporal data, operating on , Vol.1-10-12
packed 128-Bit SIMD data types , Vol.1-4-8
packed and scalar floating-point instructions , Vol.1-10-6
programming environment , Vol.1-10-2
providing exception handlers for , Vol.1-14-4, Vol.1-14-5
providing operating system support for , Vol.1-14-1
restoring SSE and SSE2 state , Vol.1-11-21
REX prefixes , Vol.1-10-3
saving and restoring state , Vol.1-14-6
saving SSE and SSE2 state , Vol.1-11-21
saving state on task, context switches , Vol.1-14-6
saving XMM register state on a procedure or function call , Vol.1-11-23
shuffle instructions , Vol.1-10-9
SIMD floating-point exception conditions , Vol.1-11-14
SIMD floating-point exception cross reference , Vol.1-C-3
SIMD Floating-point exception (#XM) , Vol.3-6-53Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -31INDEX
SIMD floating-point exception (#XM) , Vol.1-11-18
SIMD floating-point exceptions , Vol.1-11-13
SSE and SSE2 conversion instruction chart , Vol.1-11-9
SSE feature flag, CPUID instruction , Vol.1-11-20
SSE2 compatibility , Vol.1-10-5
system programming , Vol.1-13-23
unpack instructions , Vol.1-10-9
updating MMX technology routines
using128-bit SIMD integer instructions , Vol.1-11-24
using TS flag to control saving of state , Vol.1-14-7
x87 FPU compatibility , Vol.1-10-5
XMM registers , Vol.1-10-3
SSE feature flag
CPUID instruction , Vol.1-14-2
SSE feature flag, CPUID instruction , Vol.1-11-20, Vol.1-12-5
descriptions of , Vol.1-10-6
SIMD floating-point exception cross-reference , Vol.1-C-3
summary of , Vol.1-5-17
SSE2 extensions
128-bit packed single-precision
data type , Vol.1-11-3
128-bit packed single-precision data type , Vol.1-12-1
128-bit SIMD integer instruction
extensions , Vol.1-11-11
64-bit and 128-bit SIMD integer instructions , Vol.1-11-11
64-bit mode , Vol.1-11-3
arithmetic instructions , Vol.1-11-6
branch hints , Vol.1-11-13
cacheability control instructions , Vol.1-11-12
cacheability instruction encodings , Vol.1-B-56
caller-save requirement for procedure and function calls , Vol.1-11-24
comparison instructions , Vol.1-11-7
compatibility mode , Vol.1-11-3
conversion instructions , Vol.1-11-9
data movement instructions , Vol.1-11-5
data types , Vol.1-11-3, Vol.1-12-1
denormals-are-zero mode , Vol.1-11-3
floating-point encodings , Vol.1-B-48
generating SIMD floating-point exceptions , Vol.1-11-16
instruction set , Vol.1-5-19
instructions , Vol.1-11-4, Vol.1-12-2, Vol.1-12-6
integer instruction encodings , Vol.1-B-52
Vol.1-11-18interaction of SSE and SSE2 instructions with x87 FPU and MMX 
intermixing packed and scalar floa ting-point and 128-bit SIMD integer 
instructions and data , Vol.1-11-22
logical instructions , Vol.1-11-7
memory ordering instructions , Vol.1-11-12
MMX technology compatibility , Vol.1-11-3
packed and scalar floating-point instructions , Vol.1-11-4
programming environment , Vol.1-11-2
REX prefixes , Vol.1-11-3
shuffle instructions , Vol.1-11-7
SIMD floating-point exception cross reference , Vol.1-C-5
SIMD Floating-point exception (#XM) , Vol.3-6-53
SSE compatibility , Vol.1-11-3
SSE2 feature flag, CPUID instruction , Vol.1-11-20
unpack instructions , Vol.1-11-7

using TS flag to control saving state , Vol.1-14-7
x87 FPU compatibility , Vol.1-11-3
SSE2 feature flag
SSE2 feature flag, CPUID instruction , Vol.1-11-20, Vol.1-12-5
SSE2 instructions
descriptions of , Vol.1-11-4, Vol.1-12-2, Vol.1-12-6
SIMD floating-point exception cross-reference , Vol.1-C-5
summary of , Vol.1-5-19
SSE3
SSE3 extensions
64-bit mode , Vol.1-12-1
asymmetric processing , Vol.1-12-1
compatibility mode , Vol.1-12-1
DNA exceptions , Vol.1-12-9
emulation , Vol.1-12-10
enabling support in a system executive , Vol.1-12-5, Vol.1-12-18
event mgmt instruction encodings , Vol.1-B-57
example verifying SS3 support , Vol.3-9-46, Vol.3-9-49, Vol.3-15-2
exceptions , Vol.1-12-9
floating-point instruction encodings , Vol.1-B-57
guideline for packed addition/subtraction instructions , Vol.1-12-6
horizontal addition/subtraction instructions , Vol.1-12-4
horizontal processing , Vol.1-12-1
instruction that addresses cache line splits , Vol.1-5-23
instruction that improves X87-FP integer conversion , Vol.1-5-23INDEX
Index-32 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4instructions for horizontal addition/subtraction , Vol.1-5-23
instructions for packed addition/subtraction , Vol.1-5-23
instructions that enhance LOAD/MOVE/DUPLICATE , Vol.1-5-24
instructions that improve synchronization between agents , Vol.1-5-24
integer instruction encodings , Vol.1-B-57, Vol.1-B-58
LOAD/MOVE/DUPLICATE enhancement instructions , Vol.1-12-3
MMX technology compatibility , Vol.1-12-1
numeric error flag and IGNNE# , Vol.1-12-9
packed addition/subtraction instructions , Vol.1-12-4
programming environment , Vol.1-12-1
REX prefixes , Vol.1-12-1
SIMD floating-point exception cross reference , Vol.1-C-7, Vol.1-C-8
specialized 120-bit load instruction , Vol.1-12-3
SSE compatibility , Vol.1-12-1
SSE2 compatibility , Vol.1-12-1
x87 FPU compatibility , Vol.1-12-1
SSE3 feature flag
SSE3 instructions
descriptions of , Vol.1-12-2
SIMD floating-point exception
cross-reference , Vol.1-C-7, Vol.1-C-8
summary of , Vol.1-5-23
SSSE3 extensions , Vol.1-B-58, Vol.1-B-64, Vol.1-B-70
checking for support , Vol.1-12-9
data types , Vol.1-12-1
enabling support in a system executive , Vol.1-12-9
horizontal add/subtract instructions , Vol.1-12-7
multiply and add packed instructions , Vol.1-12-8
packed absolute value instructions , Vol.1-12-7
packed align instruction , Vol.1-12-8
packed multiply high instructions , Vol.1-12-8
packed shuffle instruction , Vol.1-12-8
SSSE3 instructions
descriptions of , Vol.1-12-6
summary of , Vol.1-5-24
Stack
64-bit mode , Vol.1-3-5, Vol.1-6-4
64-bit mode behavior , Vol.1-6-19
address-size attribute , Vol.1-6-3
alignment , Vol.1-6-2
alignment of stack pointer , Vol.1-6-2
current stack , Vol.1-6-1, Vol.1-6-3
description of , Vol.1-6-1
EIP register (return instruction pointer) , Vol.1-6-3
maximum size , Vol.1-6-1
number allowed , Vol.1-6-1
passing parameters on , Vol.1-6-7
popping values from , Vol.1-6-1
procedure linking information , Vol.1-6-3
pushing values on , Vol.1-6-1
return instruction pointer , Vol.1-6-3
SS register , Vol.1-6-1
stack segment , Vol.1-3-14, Vol.1-6-1stack-frame base pointer, EBP register , Vol.1-6-3
switching
on calls to interrupt and exception handlers , Vol.1-6-14
on inter-privilege level calls , Vol.1-6-10, Vol.1-6-17
privilege levels , Vol.1-6-8
width , Vol.1-6-2
Stack fault exception (#SS) , Vol.3-6-40
Stack fault, x87 FPU , Vol.1-23-8, Vol.1-23-13
Stack pointers
privilege level 0, 1, and 2 stacks , Vol.3-8-5
size of , Vol.3-3-11
Stack segments
privilege level check when loading SS register , Vol.3-5-10
size of stack pointer , Vol.3-3-11
Stack switching
exceptions/interrupts when switching stacks , Vol.3-6-8
IA-32e mode , Vol.3-6-21
inter-privilege level calls , Vol.3-5-17
Stack-fault exception (#SS) , Vol.1-23-34
Stacks
error code pushes , Vol.1-23-32
faults , Vol.3-6-40
for privilege levels 0, 1, and 2 , Vol.3-5-17
interlevel RET/IRET
from a 16-bit interrupt or call gate , Vol.1-23-33
interrupt stack table, 64-bit mode , Vol.3-6-22
management of control transfers for
16- and 32-bit procedure calls , Vol.3-22-4
operation on pushes and pops , Vol.1-23-32
pointers to in TSS , Vol.3-8-5
stack switching , Vol.3-5-17, Vol.3-6-21
usage on call to exception
or interrupt handler , Vol.1-23-33
Stack, pushing values on , Vol.2-4-516
Stack, x87 FPU
stack fault , Vol.1-8-6
stack overflow and underflow exception (#IS) , Vol.1-8-4, Vol.1-8-26
Status flags
EFLAGS register , Vol.1-3-16, Vol.1-8-6, Vol.1-8-7, Vol.1-8-19
Status flags, EFLAGS register , Vol.2-3-177, Vol.2-3-179, Vol.2-3-373, 
Vol.2-3-378, Vol.2-3-551, Vol.2-4-612, Vol.2-4-703
STC instruction , Vol.1-3-16, Vol.1-7-21, Vol.2-4-660
STD instruction , Vol.1-3-17, Vol.1-7-21, Vol.2-4-661
Stepping information , Vol.2-3-251
Stepping information, following processor initialization or reset , 
Vol.3-10-5
STI instruction , Vol.1-7-22, Vol.1-19-4, Vol.2-4-662, Vol.3-6-7
Sticky bits , Vol.1-8-5
STMXCSR instruction , Vol.1-10-12, Vol.1-11-24, Vol.2-4-664
Store buffer
characteristics of , Vol.3-12-4
description of , Vol.3-12-5, Vol.3-12-20
location of , Vol.3-12-1
operation of , Vol.3-12-20
STOS instruction , Vol.1-3-17, Vol.1-7-19, Vol.2-4-555, Vol.2-4-665
STOSB instruction , Vol.2-4-665
STOSD instruction , Vol.2-4-665
STOSQ instruction , Vol.2-4-665
STOSW instruction , Vol.2-4-665
STPCLK# pin , Vol.3-6-3
STR instruction , Vol.2-4-668, Vol.3-2-24, Vol.3-3-16, Vol.3-8-7
Streaming SIMD extensions 2 (see SSE2 extensions)Streaming SIMD extensions (see SSE extensions)String data type
, Vol.1-4-8
String instructions , Vol.2-3-195, Vol.2-3-511, Vol.2-3-612, Vol.2-4-110, 
Vol.2-4-178, Vol.2-4-604, Vol.2-4-665
Strong uncached (UC) memory type
description of , Vol.3-12-6
effect on memory ordering , Vol.3-9-17Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -33INDEX
use of , Vol.3-10-8, Vol.3-12-8
ST(0), top-of-stack register , Vol.1-8-3
Sub C-state , Vol.3-15-35
SUB instruction , Vol.1-7-8, Vol.2-3-25, Vol.2-3-319, Vol.2-3-610, 
Vol.2-4-673, Vol.3-9-4
SUBPD- Subtract Packed Double Precision Floating-Point Values , 
SUBPD- Subtract Packed Double-P recision Floating-Point Values , 
SUBPS- Subtract Packed Single-Precision Floating-Point Values , 
Vol.2-4-678
SUBSD- Subtract Scalar Double-Precision Floating-Point Values , 
Vol.2-4-681
SUBSS- Subtract Scalar Single-P recision Floating-Point Values , 
Vol.2-4-683
Superscalar microarchitecture
P6 family microarchitecture , Vol.1-2-2
P6 family processors , Vol.1-2-7
Pentium 4 processor , Vol.1-2-9
Pentium Pro processor , Vol.1-2-2
Pentium processor , Vol.1-2-2
Supervisor mode
description of , Vol.3-5-28
U/S (user/supervisor) flag , Vol.3-5-28
SVR (spurious-interrupt vect or register), local APIC , Vol.3-11-8, 
Vol.1-23-28
SWAPGS instruction , Vol.2-4-685, Vol.3-2-7
SYSCALL instruction , Vol.2-4-687, Vol.3-2-7, Vol.3-5-22
SYSENTER instruction , Vol.2-4-690, Vol.3-3-8, Vol.3-5-10, Vol.3-5-20, 
Vol.3-5-21
SYSENTER_CS_MSR , Vol.3-5-21
SYSENTER_EIP_MSR , Vol.3-5-21
SYSENTER_ESP_MSR , Vol.3-5-21
SYSEXIT instruction , Vol.2-4-693, Vol.3-3-8, Vol.3-5-10, Vol.3-5-20, 
SYSRET instruction , Vol.2-4-696, Vol.3-2-7, Vol.3-5-22
System
architecture , Vol.3-2-1, Vol.3-2-2
data structures , Vol.3-2-2
instructions , Vol.3-2-7, Vol.3-2-23
registers in IA-32e mode , Vol.3-2-7
registers, introduction to , Vol.3-2-6
segment descriptor, layout of , Vol.3-5-2
segments, paging of , Vol.3-2-6
System management mode (see SMM)System programming
, Vol.3-13-1
SSE/SSE2/SSE3 extensions , Vol.1-13-23
System-management mode (see SMM)
T
T (debug trap) flag, TSS , Vol.3-8-5
Tangent, x87 FPU operation , Vol.1-8-20, Vol.2-3-421
Task gate , Vol.1-6-18
Task gates
descriptor , Vol.3-8-8
executing a task , Vol.3-8-2

System
T
Task gates
Vol.3-21-14
introduction for IA-32e , Vol.3-2-4
referencing of TSS descriptor , Vol.3-6-17
Task management , Vol.3-8-1
data structures , Vol.3-8-3
Task register , Vol.1-3-4, Vol.3-3-16description of , Vol.3-2-13, Vol.3-8-1, Vol.3-8-7
IA-32e mode , Vol.3-2-13
initializing , Vol.3-10-11
loading , Vol.2-3-621
storing , Vol.2-4-668
Task state segment (see TSS)
Task switch
CALL instruction , Vol.2-3-139
return from nested task, IRET instruction , Vol.2-3-539
Task switching
description of , Vol.3-8-3
exception condition , Vol.3-18-11
operation , Vol.3-8-10
preventing recursive task switching , Vol.3-8-16
saving MMX state on , Vol.3-13-4
saving SSE/SSE2/SSE3 state
on task or context switches , Vol.1-14-6
T (debug trap) flag , Vol.3-8-5
Tasks
address space , Vol.3-8-16
description of , Vol.3-8-1
exception handler , Vol.1-6-18
exception-handler task , Vol.3-6-11
executing , Vol.3-8-2
Intel 286 processor tasks , Vol.1-23-37
interrupt handler , Vol.1-6-18
interrupt-handler task , Vol.3-6-11
interrupts and exceptions , Vol.3-6-17
linking , Vol.3-8-15
logical address space , Vol.3-8-18
management , Vol.3-8-1
mapping linear and physical address space , Vol.3-8-17
restart following an exception or interrupt , Vol.3-6-5
state (context) , Vol.3-8-2, Vol.3-8-3
structure , Vol.3-8-1
switching , Vol.3-8-3
task management data structures , Vol.3-8-3
Temporal data , Vol.1-10-12
TEST instruction , Vol.1-7-14, Vol.2-4-703, Vol.2-5-718
TF (trap) flag, EFLAGS register , Vol.1-3-17, Vol.1-A-1, Vol.3-2-9, 
Vol.3-6-17, Vol.3-18-11, Vol.3-18-13, Vol.3-18-36, Vol.3-18-38, Vol.3-18-39, Vol.3-18-41, Vol.3-21-4, Vol.3-21-19, Vol.4-32-11
Thermal Monitor , Vol.1-2-4
Thermal Monitor 2 , Vol.2-3-243
advanced power management , Vol.3-15-35
automatic , Vol.3-15-37
automatic thermal monitoring , Vol.3-15-36
catastrophic shutdown detector , Vol.3-15-36, Vol.3-15-37
clock-modulation bits , Vol.3-15-40
detection of facilities , Vol.3-15-41
Enhanced Intel SpeedStep Technology , Vol.3-15-1
IA32_MPERF MSR , Vol.3-15-1
IA32_THERM_INTERRUPT MSR , Vol.3-15-42
IA32_THERM_STATUS MSR , Vol.3-15-42
interrupt enable/disable flags , Vol.3-15-39
interrupt mechanisms , Vol.3-15-36
MWAIT extensions for , Vol.3-15-35
on die sensors , Vol.3-15-36, Vol.3-15-42
overview of , Vol.3-15-1, Vol.3-15-36
performance state transitions , Vol.3-15-38
sensor interrupt , Vol.3-11-1
setting thermal thresholds , Vol.3-15-42
software controlled clock modulation , Vol.3-15-36, Vol.3-15-40
status flags , Vol.3-15-38
status information , Vol.3-15-38, Vol.3-15-39INDEX
Index-34 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4stop clock mechanism , Vol.3-15-36
thermal monitor 1 (TM1) , Vol.3-15-37
thermal monitor 2 (TM2) , Vol.3-15-37
TM flag, CPUID instruction , Vol.3-15-41
Thermal status bit , Vol.3-15-42, Vol.3-15-45
Thermal status log bit , Vol.3-15-42, Vol.3-15-46
Thermal threshold #1 log , Vol.3-15-43, Vol.3-15-46
Thermal threshold #1 status , Vol.3-15-43, Vol.3-15-46
Thermal threshold #2 log , Vol.3-15-43, Vol.3-15-46
Thermal threshold #2 status , Vol.3-15-43, Vol.3-15-46
thread timeout indicator , Vol.3-17-3, Vol.3-17-7, Vol.3-17-10, 
Threshold #1 interrupt enable bit , Vol.3-15-44, Vol.3-15-47
Threshold #1 value , Vol.3-15-44, Vol.3-15-47
Threshold #2 interrupt enable , Vol.3-15-44, Vol.3-15-47
Threshold #2 value , Vol.3-15-44, Vol.3-15-47
TI (table indicator) flag, segment selector , Vol.3-3-7
Time Stamp Counter , Vol.2-3-246
Timer, local APIC , Vol.3-11-16
Time-stamp counter
counting clockticks , Vol.3-20-139
description of , Vol.3-18-42
IA32_TIME_STAMP_COUNTER MSR , Vol.3-18-42
RDTSC instruction , Vol.3-18-42
reading , Vol.3-2-26
TSC flag , Vol.3-18-42
TSD flag , Vol.3-18-42
Time-stamp counter, reading , Vol.2-4-550, Vol.2-4-552
TLB entry, invalidating (flushing) , Vol.2-3-534
TLBs
description of , Vol.3-12-1, Vol.3-12-5
flushing , Vol.3-12-19
invalidating (flushing) , Vol.3-2-25
relationship to PGE flag , Vol.1-23-19
relationship to PSE flag , Vol.3-12-20
TM1 and TM2
See: thermal monitoring , Vol.3-15-37
TMR
Trigger Mode Register , Vol.3-11-31, Vol.3-11-39, Vol.3-11-41, 
Vol.3-11-47
TMR (Trigger Mode Register), local APIC , Vol.3-11-30
TOP (stack TOP) field
x87 FPU status word , Vol.1-8-2, Vol.1-9-9
TPR
Task Priority Register , Vol.3-11-38, Vol.3-11-41
DEBUGCTLMSR MSR , Vol.3-18-13, Vol.3-18-36, Vol.3-18-38, 
Trace cache , Vol.1-2-9, Vol.3-12-4, Vol.3-12-5
Transcendental instruction accuracy , Vol.1-8-21, Vol.1-23-8, Vol.1-23-14
Translation lookaside buffer (see TLB)
Trap gate , Vol.1-6-13
Trap gates
Traps
Truncation
description of , Vol.1-4-18
with SSE-SSE2 conversion instructions , Vol.1-4-18
Trusted Platform Module , Vol.1-6-5
TS (task switched) flagCR0 control register , Vol.3-2-15, Vol.3-2-24, Vol.3-6-32, Vol.3-13-1, 
Vol.1-14-3, Vol.1-14-7
TS (task switched) flag, CR0 register , Vol.2-3-170
TSD (time-stamp counter disable) flag
CR4 control register , Vol.3-2-17, Vol.3-5-24, Vol.3-18-43, 
TSS
16-bit TSS, structure of , Vol.3-8-18
32-bit TSS, structure of , Vol.3-8-3
64-bit mode , Vol.3-8-19
CR3 control register (PDBR) , Vol.3-8-4, Vol.3-8-17
description of , Vol.3-2-4, Vol.3-2-5, Vol.3-8-1, Vol.3-8-3
EFLAGS register , Vol.3-8-4
EFLAGS.NT , Vol.3-8-15
EIP, Vol.3-8-5
floating-point save area , Vol.1-23-12
format in 64-bit mode , Vol.3-8-19
general-purpose registers , Vol.3-8-4
initialization for multitasking , Vol.3-10-10
interrupt stack table , Vol.3-8-19
invalid TSS exception , Vol.3-6-36
IRET instruction , Vol.3-8-15
I/O map base , Vol.1-19-4
I/O map base address field , Vol.3-8-5, Vol.1-23-29
I/O permission bit map , Vol.1-19-4, Vol.3-8-5, Vol.3-8-19
LDT segment selector field , Vol.3-8-5, Vol.3-8-16
link field , Vol.3-6-17
order of reads/writes to , Vol.1-23-29
pointed to by task-gate descriptor , Vol.3-8-8
previous task link field , Vol.3-8-5, Vol.3-8-15, Vol.3-8-16
privilege-level 0, 1, and 2 stacks , Vol.3-5-17
referenced by task gate , Vol.3-6-17
saving state of EFLAGS register , Vol.1-3-15
segment registers , Vol.3-8-4
task register , Vol.3-8-7
using 16-bit TSSs in a 32-bit environment , Vol.1-23-29
virtual-mode extensions , Vol.1-23-29
TSS descriptor
B (busy) flag , Vol.3-8-5
busy flag , Vol.3-8-16
structure of , Vol.3-8-5, Vol.3-8-6
TSS segment selector
field, task-gate descriptor , Vol.3-8-8
writes , Vol.1-23-29
TSS, relationship to task register , Vol.2-4-668
Type
checking , Vol.3-5-5
field, IA32_MTRR_DEF_TYPE MSR , Vol.3-12-22
field, IA32_MTRR_PHYSBASEn MTRR , Vol.3-12-24, Vol.3-12-26
field, segment descriptor , Vol.3-3-10, Vol.3-3-12, Vol.3-3-14, 
Vol.3-5-2, Vol.3-5-5
of segment , Vol.3-5-5
TZCNT - Count the Number of Trailing Zero Bits , Vol.2-4-713
U
UCOMISD - Unordered Compare Scalar Double-Precision Floating-Point 
Values and Set EFLAGS , Vol.2-4-715
UCOMISD instruction , Vol.1-11-7, Vol.2-4-713
UCOMISS - Unordered Compare Scalar Single-Precision Floating-Point 
Values and Set EFLAGS , Vol.2-4-717
UCOMISS instruction , Vol.1-10-9
UD2 instruction , Vol.1-7-24, Vol.2-4-719, Vol.1-23-4
UE (numeric underflow exception) flag
UM (numeric underflow exception) mask bitCombined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -35INDEX
Uncached (UC-) memory type , Vol.3-12-8
Uncached (UC) memory type (see St rong uncached (UC) memory type)
Undefined opcodes , Vol.1-23-5
Undefined, format opcodes , Vol.2-3-451
Underflow
FPU exception
(see Numeric underflow exception)
numeric, floating-point , Vol.1-4-14
x87 FPU stack , Vol.1-8-26
Underflow, x87 FPU stack , Vol.1-8-26
Unit mask field, PerfEvtSel0 and Perf EvtSel1 MSRs (P6 family processors)
, Vol.3-20-4, Vol.3-20-8, Vol.3-20-10, Vol.3-20-11,

Underflow
, Vol.3-20-4, Vol.3-20-8, Vol.3-20-10, Vol.3-20-11, 
Vol.3-20-12, Vol.3-20-14, Vol.3-20-25, Vol.3-20-27, Vol.3-20-34, Vol.3-20-35, Vol.3-20-36, Vol.3-20-54, Vol.3-20-56, Vol.3-20-99, Vol.3-20-100, Vol.3-20-101, Vol.3-20-134, Vol.3-20-143, Vol.3-20-144, Vol.3-20-145, Vol.3-20-146, Vol.3-20-150
Un-normal number , Vol.1-23-9
Unordered values , Vol.2-3-375, Vol.2-3-451, Vol.2-3-453
Unpack instructions
UNPCKHPD instruction , Vol.1-11-8
UNPCKHPD- Unpack and Interleave High Packed Double-Precision 
Floating-Point Values , Vol.2-4-726
UNPCKHPS instruction , Vol.1-10-10
UNPCKHPS- Unpack and Interleave High Packed Single-Precision 
Floating-Point Values , Vol.2-4-730
UNPCKLPD instruction , Vol.1-11-8
UNPCKLPD- Unpack and Interleave Low Packed Double-Precision 
Floating-Point Values , Vol.2-4-734
UNPCKLPS instruction , Vol.1-10-10
UNPCKLPS- Unpack and Interleave Low Packed Single-Precision 
Floating-Point Values , Vol.2-4-738
Unsigned integers
range of , Vol.1-4-3
types , Vol.1-4-3
Unsupported , Vol.1-8-14
floating-point formats, x87 FPU , Vol.1-8-14
x87 FPU instructions , Vol.1-8-24
User mode
User-defined interrupts , Vol.3-6-1, Vol.3-6-58
USR (user mode) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family 
processors) , Vol.3-20-4, Vol.3-20-8, Vol.3-20-10, 
Vol.3-20-11, Vol.3-20-12, Vol.3-20-25, Vol.3-20-27, Vol.3-20-34, Vol.3-20-35, Vol.3-20-36, Vol.3-20-54, Vol.3-20-56, Vol.3-20-99, Vol.3-20-100, Vol.3-20-101, Vol.3-20-134, Vol.3-20-143, Vol.3-20-144, Vol.3-20-145, Vol.3-20-146, Vol.3-20-150
U/S (user/supervisor) flag
page-table entries , Vol.3-21-8
V
V (valid) flag
VADDPH—Add Packed FP16 Values , Vol.2-5-5
VADDSH—Add Scalar FP16 Values , Vol.2-5-7
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors , Vol.2-5-8
Variable-range MTRRs, description of , Vol.3-12-23, Vol.3-12-25
VBLENDMPD/VBLENDMPS—Blend Floa t64/Float32 Vectors Using an 
OpMask Control , Vol.2-5-11
VBROADCAST—Load with Broadcast Floating-Point Data , Vol.2-5-13
VCMPPH—Compare Packed FP16 Values , Vol.2-5-21
VCMPSH—Compare Scalar FP16 Values , Vol.2-5-23VCNT (variable range registers count) field, IA32_MTRRCAP MSR , 
VCOMISH—Compare Scalar Ordere d FP16 Values and Set EFLAGS , 
Vol.2-5-25
VCOMPRESSPD—Store Sparse Packed Double Precision Floating-Point 
Values Into Dense Memory , Vol.2-5-27
VCOMPRESSPS—Store Sparse Packed Single Precision Floating-Point 
Values Into Dense Memory , Vol.2-5-29
VCVTDQ2PH—Convert Packed Signed Doubleword Integers to Packed 
FP16 Values , Vol.2-5-31
VCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 
Data, Vol.2-5-33
VCVTNEPS2BF16—Convert Packed Single Data to Packed BF16 Data , 
Vol.2-5-35
VCVTPD2PH—Convert Packed Double Precision FP Values to Packed FP16 
Values , Vol.2-5-37
VCVTPD2QQ—Convert Packed Double Pr ecision Floating-Point Values to 
Packed Quadword Integers , Vol.2-5-39
VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to 
Packed Unsigned Doubleword Integers , Vol.2-5-41
VCVTPD2UQQ—Convert Packed Double Precision Floating-Point Values to 
Packed Unsigned Quadword Integers , Vol.2-5-43
VCVTPH2DQ—Convert Packed FP16 Values to Signed Doubleword 
Integers , Vol.2-5-45
VCVTPH2PD—Convert Packed FP16 Values to FP64 Values , Vol.2-5-47
VCVTPH2QQ—Convert Packed FP16 Values to Signed Quadword Integer 
Values , Vol.2-5-53
VCVTPH2UDQ—Convert Packed FP16 Values to Unsigned Doubleword 
Integers , Vol.2-5-55
VCVTPH2UQQ—Convert Packed FP16 Values to Unsigned Quadword 
Integers , Vol.2-5-57
VCVTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers , 
Vol.2-5-59
VCVTPH2W—Convert Packed FP16 Values to Signed Word Integers , 
Vol.2-5-61
VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP Value , 
Vol.2-5-63
VCVTPS2PHX—Convert Packed Single Precision Floating-Point Values to 
Packed FP16 Values , Vol.2-5-67
VCVTPS2UDQ—Convert Packed Single Pr ecision Floating-Point Values to 
Packed Unsigned Doubleword Integer Values , Vol.2-5-71
VCVTPS2UQQ—Convert Packed Single Pr ecision Floating-Point Values to 
Packed Unsigned Quadword Integer Values , Vol.2-5-74
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double 
Precision Floating-Point Values , Vol.2-5-76
VCVTQQ2PH—Convert Packed Signed Quadword Integers to Packed FP16 
Values , Vol.2-5-78
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single 
Precision Floating-Point Values , Vol.2-5-80
VCVTSD2SH—Convert Low FP64 Value to an FP16 Value , Vol.2-5-82
VCVTSD2USI—Convert Scalar Double Precision Floating-Point Value to 
Unsigned Doubleword Integer , Vol.2-5-83
VCVTSH2SD—Convert Low FP16 Value to an FP64 Value , Vol.2-5-85
VCVTSH2SI—Convert Low FP16 Value to Signed Integer , Vol.2-5-86
VCVTSH2SS—Convert Low FP16 Value to FP32 Value , Vol.2-5-87
VCVTSH2USI—Convert Low FP16 Value to Unsigned Integer , Vol.2-5-88
VCVTSI2SH—Convert a Signed Doubleword/Quadword Integer to an FP16 
Value , Vol.2-5-89
VCVTSS2SH—Convert Low FP32 Value to an FP16 Value , Vol.2-5-91
VCVTSS2USI—Convert Scalar Single Precision Floating-Point Value to 
Unsigned Doubleword Integer , Vol.2-5-92
VCVTTPD2QQ—Convert With Truncation Packed Double Precision 
Floating-Point Values to Packed Quadword Integers , Vol.2-5-94
VCVTTPD2UDQ—Convert With Truncation Packed Double Precision 
Floating-Point Values to Packed Unsigned Doubleword Integers
, Vol.2-5-96
VCVTTPD2UQQ—Convert With Truncation Packed Double Precision 
Floating-Point Values to Packed Unsigned Quadword Integers , 
Vol.2-5-98
VCVTTPH2DQ—Convert with Truncation Packed FP16 Values to Signed 
Doubleword Integers , Vol.2-5-100INDEX
Index-36 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4VCVTTPH2QQ—Convert with Truncation Packed FP16 Values to Signed 
Quadword Integers , Vol.2-5-102
VCVTTPH2UDQ—Convert with Truncation Packed FP16 Values to 
Unsigned Doubleword Integers , Vol.2-5-104
VCVTTPH2UQQ—Convert with Truncation Packed FP16 Values to 
Unsigned Quadword Integers , Vol.2-5-106
VCVTTPH2UW—Convert Packed FP16 Va lues to Unsigned Word Integers , 
Vol.2-5-108
VCVTTPH2W—Convert Packed FP16 Values to Signed Word Integers , 
Vol.2-5-110
VCVTTPS2QQ—Convert With Truncation Packed Single Precision 
Floating-Point Values to Packed Signed Quadword Integer Values
, Vol.2-5-116
VCVTTPS2UDQ—Convert With Truncation Packed Single Precision 
Floating-Point Values to Packed Unsigned Doubleword Integer Values
, Vol.2-5-114
VCVTTPS2UQQ—Convert With Truncation Packed Single Precision 
Floating-Point Values to Packed Unsigned Quadword Integer Values
VCVTTSD2USI—Convert With Truncation Scalar Double Precision 
Floating-Point Value to Unsigned Integer , Vol.2-5-118
VCVTTSH2SI—Convert with Truncation Low FP16 Value to a Signed 
Integer , Vol.2-5-119
VCVTTSH2USI—Convert with Truncation Low FP16 Value to an Unsigned 
Integer , Vol.2-5-120
VCVTTSS2USI—Convert With Truncation Scalar Single Precision 
Floating-Point Value to Unsigned Integer , Vol.2-5-121
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed 
Double Precision Floating-Point Values , Vol.2-5-122
VCVTUDQ2PH—Convert Packed Unsigned Doubleword Integers to Packed 
FP16 Values , Vol.2-5-124
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed 
Single Precision Floating-Point Values , Vol.2-5-126
VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed 
Double Precision Floating-Point Values , Vol.2-5-128
VCVTUQQ2PH—Convert Packed Unsigned Quadword Integers to Packed 
FP16 Values , Vol.2-5-130
VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed 
Single Precision Floating-Point Values , Vol.2-5-134
VCVTUSI2SD—Convert Unsigned Inte ger to Scalar Double Precision 
Floating-Point Value , Vol.2-5-136
VCVTUSI2SH—Convert Unsigned Doubleword Integer to an FP16 Value , 
Vol.2-5-132
VCVTUSI2SS—Convert Unsigned Integer to Scalar Single Precision 
Floating-Point Value , Vol.2-5-138
VCVTUW2PH—Convert Packed Unsigned Word Integers to FP16 Values , 
Vol.2-5-140
VCVTW2PH—Convert Packed Signed Word Integers to FP16 Values , 
Vol.2-5-142
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on 
Unsigned Bytes , Vol.2-5-144
VDIVPH—Divide Packed FP16 Values , Vol.2-5-147
VDIVSH—Divide Scalar FP16 Values , Vol.2-5-149
VDPBF16PS—Dot Product of BF16 Pairs Accumulated Into Packed Single 
Precision , Vol.2-5-150
Vectors
exceptions , Vol.3-6-1
interrupts , Vol.3-6-1
VERR instruction , Vol.2-5-152, Vol.3-2-25, Vol.3-5-25
VERR/VERW—Verify a Segment for Reading or Writing , Vol.2-5-158
Version information, processor , Vol.2-3-217
VERW instruction , Vol.2-5-152, Vol.3-2-25, Vol.3-5-25
VEX, Vol.2-3-3
VEXP2PS—Approximation to the Exponential 2^x of Packed 
Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error
, Vol.1-6-10
VEXPANDPD—Load Sparse Packed Double  Precision Floating-Point Values

Vectors
VEXPANDPD—Load Sparse Packed Double  Precision Floating-Point Values 
From Dense Memory , Vol.2-5-154
VEXPANDPS—Load Sparse Packed Single Precision Floating-Point Values 
From Dense Memory , Vol.2-5-156VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/
VEXTRACTF64x4— Extract Packed Floating-Point Values , 
Vol.2-5-158
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VE
XTRACTI64x4—Extract Packed Integer Values , Vol.2-5-164
VEX.B , Vol.2-3-3
VEX.L , Vol.2-3-3, Vol.2-3-4
VEX.mmmmm , Vol.2-3-3
VEX.pp , Vol.2-3-4
VEX.R , Vol.2-3-4
VEX.W , Vol.2-3-3
VEX.X , Vol.2-3-3
VFCMADDCPH/VFMADDCPH—Complex Multiply and Accumulate FP16 
Values , Vol.2-5-170
VFCMADDCSH/VFMADDCSH—Complex Mu ltiply and Accumulate Scalar 
FP16 Values , Vol.2-5-173
VFCMULCPH/VFMULCPH—Complex Multiply FP16 Values , Vol.2-5-175
VFCMULCSH/VFMULCSH—Complex Multiply Scalar FP16 Values , 
Vol.2-5-178
VFIXUPIMMPD—Fix Up Special Packed Float64 Values , Vol.2-5-180
VFIXUPIMMPS—Fix Up Special Packed Float32 Values , Vol.2-5-184
VFIXUPIMMSD—Fix Up Special Scalar Float64 Value , Vol.2-5-188
VFIXUPIMMSS—Fix Up Special Scalar Float32 Value , Vol.2-5-191
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of 
Packed Double Precision Floating-Point Values , Vol.2-5-194
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of 
Packed Single Precision Floating-Point Values , Vol.2-5-210
VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of 
Scalar Double Precision Floating-Point Values , Vol.2-5-216
VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of 
Scalar Single Precision Floating-Point Values , Vol.2-5-222
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused 
Multiply-Alternating Add/Subtract of Packed Double Precision Floating-Point Values
, Vol.2-5-225
VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH—Fused 
Multiply-Alternating Add/Subt ract of Packed FP16 Values , 
Vol.2-5-232
VFMADDSUB132PS/VFMADDSUB213P S/VFMADDSUB231PS—Fused 
Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
, Vol.2-5-237
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused 
Multiply-Subtract of Packed Double Precision Floating-Point Values
, Vol.2-5-244
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS— Fused 
Multiply-Subtract of Packed Single-Precision Floating-Point Values
, Vol.2-5-256
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD— Fused 
Multiply-Subtract of Scalar Double-Precision Floating-Point Values
, Vol.2-5-262
VFMSUB132SS/VFMSUB213SS/VFMSUB231S S—Fused Multiply-Subtract 
of Scalar Single-Precision Floating-Point Values , Vol.2-5-268
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused 
Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
, Vol.2-5-271
VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH—Fused 
Multiply-Alternating Subtrac t/Add of Packed FP16 Values , 
Vol.2-5-278
VFMSUBADD132PS/VFMSUBADD 213PS/VFMSUBADD231PS—Fused 
Multiply-Alternating Subtract/Add of Packed Single Precision Floating-Point Values
, Vol.2-5-283
VFNMADD132PD/VFMADD213PD/VFMADD231PD —Fused Negative 
Multiply-Add of Packed Double-Precision Floating-Point Values , 
Vol.2-5-291
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative 
Multiply-Add of Packed Single-Precision Floating-Point Values , 
Vol.2-5-298
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative 
Multiply-Add of Scalar Double-Precision Floating-Point Values , 
Vol.2-5-304
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative 
Multiply-Add of Scalar Single Precision Floating-Point Values , 
Vol.2-5-307Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -37INDEX
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative 
, Vol.2-5-310
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative 
Multiply-Subtract of Packed Single Precision Floating-Point Values
, Vol.2-5-317
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative 
, Vol.2-5-323
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative 
Multiply-Subtract of Scalar Single Precision Floating-Point Values
, Vol.2-5-326
VFPCLASSPD—Tests Types of  Packed Float64 Values , Vol.2-5-329
VFPCLASSPH—Test Types of Packed FP16 Values , Vol.2-5-332
VFPCLASSPS—Tests Types of Packed Float32 Values , Vol.2-5-335
VFPCLASSSD—Tests Type of a Scalar Float64 Value , Vol.2-5-337
VFPCLASSSH—Test Types of Scalar FP16 Values , Vol.2-5-339
VFPCLASSSS—Tests Type of a Scalar Float32 Value , Vol.2-5-340
VGATHERDPD/VGATHERQPD—Gather  Packed Double Precision 
Floating-Point Values Using Signed Dword/Qword Indices , 
Vol.2-5-342
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with 
Signed Dword , Vol.2-5-350
VGATHERDPS/VGATHERQPS—Gather Pack ed SP FP values Using Signed 
Dword/Qword Indices , Vol.2-5-346
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QP
D - Sparse Prefetch Packed SP /DP Data Values with Signed 
Dword, Signed Qword Indices Using T1 Hint , Vol.1-6-14
VGATHERQPS/VGATHERQPD—Gather Pack ed Single, Packed Double with 
Signed Qword Indices , Vol.2-5-353
VGETEXPPD—Convert Exponents of Packed Double Precision 
Floating-Point Values to Double  Precision Floating-Point Values
, Vol.2-5-356
VGETEXPPH—Convert Exponents of Pa cked FP16 Values to FP16 Values , 
Vol.2-5-359
VGETEXPPS—Convert Exponents of Packed  Single Precision Floating-Point 
Values to Single Precision Floating-Point Values , Vol.2-5-362
VGETEXPSD—Convert Exponents of Scalar Double Precision Floating-Point 
Value to Double Precision Floating-Point Value , Vol.2-5-366
VGETEXPSH—Convert Exponents of Scalar FP16 Values to FP16 Values , 
Vol.2-5-368
VGETEXPSS—Convert Exponents of Scalar Single Precision Floating-Point 
Value to Single Precision Floating-Point Value , Vol.2-5-370
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas From 
Float64 Vector , Vol.2-5-372
VGETMANTPH—Extract FP16 Vector of Normalized Mantissas from FP16 
Vector , Vol.2-5-376
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas From 
Float32 Vector , Vol.2-5-380
VGETMANTSD—Extract Float64 of Normalized Mantissas From Float64 
Scalar , Vol.2-5-383
VGETMANTSH—Extract FP16 of Normal ized Mantissa from FP16 Scalar , 
Vol.2-5-385
VGETMANTSS—Extract Float32 Vector  of Normalized Mantissa From 
Float32 Vector , Vol.2-5-387
VIF (virtual interrupt) flag
EFLAGS register , Vol.3-2-11, Vol.1-23-6, Vol.1-23-7
VIF (virtual interrupt) flag, EFLAGS register , Vol.1-3-17
VINSERTF128/VINSERTF32x4/VINSER TF64x2/VINSERTF32x8/VINSERT
F64x4—Insert Packed Floating-Point Values , Vol.2-5-389
VINSERTI128/VINSERTI32x4/VINSER TI64x2/VINSERTI32x8/VINSERTI64
x4—Insert Packed Integer Values , Vol.2-5-393
VIP (virtual interrupt pending) flag
EFLAGS register , Vol.1-3-17, Vol.3-2-11, Vol.1-23-6, Vol.1-23-7
Virtual 8086 mode
description of , Vol.1-3-17
Virtual Machine Monitor , Vol.1-6-1
Virtual memory , Vol.3-2-6, Vol.3-3-1, Vol.3-3-2
Virtual-8086 mode
description of , Vol.3-21-5emulating 8086 operating system calls , Vol.3-21-18
enabling , Vol.3-21-6
entering , Vol.3-21-8
exception and interrupt handling overview , Vol.3-21-11
exceptions and interrupts, handling through a task gate , Vol.3-21-14
exceptions and interrupts, handling through a trap or interrupt gate , 
handling exceptions and interrupts through a task gate , Vol.3-21-14
introduction to , Vol.3-2-8
IOPL sensitive instructions , Vol.3-21-10
I/O-port-mapped I/O , Vol.3-21-11
leaving , Vol.3-21-9
memory mapped I/O , Vol.3-21-11
paging of virtual-8086 tasks , Vol.3-21-7
protection within a virtual-8086 task , Vol.3-21-8
special I/O buffers , Vol.3-21-11
structure of a virtual-8086 task , Vol.3-21-7
virtual I/O , Vol.3-21-10
VM flag, EFLAGS register , Vol.3-2-10
Virtual-8086 tasks
paging of , Vol.3-21-7
protection within , Vol.3-21-8
structure of , Vol.3-21-7
VM entries
basic VM-entry checks , Vol.3-27-2
checking guest state
control registers , Vol.3-27-8
debug registers , Vol.3-27-8
descriptor-table registers , Vol.3-27-12
MSRs , Vol.3-27-8
non-register state , Vol.3-27-13
RIP and RFLAGS , Vol.3-27-12
segment registers , Vol.3-27-10
checks on controls, host-state area , Vol.3-27-2
registers and MSRs , Vol.3-27-7
segment and descriptor-table registers , Vol.3-27-7
VMX control checks , Vol.3-27-2
exit-reason numbers , Vol.1-C-1
loading guest state , Vol.3-27-15
control and debug registers, MSRs , Vol.3-27-15
RIP, RSP, RFLAGS , Vol.3-27-17
segment & descriptor-table registers , Vol.3-27-17
loading MSRs , Vol.3-27-18
failure cases , Vol.3-27-18
VM-entry MSR-load area , Vol.3-27-18
overview of failure conditions , Vol.3-27-1
overview of steps , Vol.3-27-1
VMLAUNCH and VMRESUME , Vol.3-27-1
See also: VMCS, VMM, VM exits
VM exits
architectural state
existing before exit , Vol.3-28-1
updating state before exit , Vol.3-28-1
basic VM-exit information fields , Vol.3-28-4
basic exit reasons , Vol.3-28-4
exit qualification , Vol.3-28-4
exception bitmap , Vol.3-28-1
exceptions (faults, traps, and aborts) , Vol.3-26-5

VM exits
external interrupts , Vol.3-26-6
IA-32 faults and VM exits , Vol.3-26-1
INITs , Vol.3-26-6
instructions that cause:
conditional exits , Vol.3-26-2
unconditional exits , Vol.3-26-2
interrupt-window exiting , Vol.3-26-7
non-maskable interrupts (NMIs) , Vol.3-26-6
page faults , Vol.3-26-6
start-up IPIs (SIPIs) , Vol.3-26-6INDEX
Index-38 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4task switches , Vol.3-26-6
See also: VMCS, VMM, VM entries
VM (virtual 8086 mode) flag, EFLAGS register , Vol.1-3-17, Vol.2-3-539
VM (virtual-8086 mode) flag
EFLAGS register , Vol.3-2-8, Vol.3-2-10
VMASKMOV—Conditional SIMD Packed Loads and Stores , Vol.2-5-397
VMAXPH—Return Maximum of Packed FP16 Values , Vol.2-5-400
VMAXSH—Return Maximum of Scalar FP16 Values , Vol.2-5-402
VMCALL instruction , Vol.1-5-38, Vol.1-5-39, Vol.3-31-1
VMCLEAR instruction , Vol.1-5-38, Vol.1-5-39, Vol.3-31-1
VMCS
error numbers , Vol.3-31-31
field encodings , Vol.3-1-7, Vol.1-B-1
16-bit guest-state fields , Vol.1-B-1
16-bit host-state fields , Vol.1-B-2
32-bit control fields , Vol.1-B-1, Vol.1-B-7
32-bit guest-state fields , Vol.1-B-8
32-bit read-only data fields , Vol.1-B-8
64-bit control fields , Vol.1-B-2
64-bit guest-state fields , Vol.1-B-5, Vol.1-B-6
natural-width control fields , Vol.1-B-9
natural-width guest-state fields , Vol.1-B-10
natural-width host-state fields , Vol.1-B-11
natural-width read-only data fields , Vol.1-B-10
format of VMCS region , Vol.3-25-2
guest-state area , Vol.3-25-3
guest non-register state , Vol.3-25-6
guest register state , Vol.3-25-4
host-state area , Vol.3-25-3, Vol.3-25-8
introduction , Vol.3-25-1
migrating between processors , Vol.3-25-29
software access to , Vol.3-25-29
VMCS data , Vol.3-25-2, Vol.3-26-21
VMCS pointer , Vol.3-25-1
VMCS region , Vol.3-25-1
VMCS revision identifier , Vol.3-25-2, Vol.3-26-21
VM-entry control fields , Vol.3-25-3, Vol.3-25-23
entry controls , Vol.3-25-23
entry controls for event injection , Vol.3-25-24
entry controls for MSRs , Vol.3-25-24
VM-execution control fields , Vol.3-25-3, Vol.3-25-9
controls for CR8 accesses , Vol.3-25-15
CR3-target controls , Vol.3-25-14
exception bitmap , Vol.3-25-14
I/O bitmaps , Vol.3-25-14
masks & read shadows CR0 & CR4 , Vol.3-25-14
pin-based controls , Vol.3-25-9
processor-based controls , Vol.3-25-10, Vol.3-25-21
time-stamp counter offset , Vol.3-25-14
VM-exit control fields , Vol.3-25-3, Vol.3-25-21
exit controls for MSRs , Vol.3-25-22
VM-exit information fields , Vol.3-25-3, Vol.3-25-25
basic exit information , Vol.3-25-26, Vol.1-C-1
basic VM-exit information , Vol.3-25-26
exits due to instruction execution , Vol.3-25-28
exits due to vectored events , Vol.3-25-27
exits occurring during event delivery , Vol.3-25-27
VM-instruction error field , Vol.3-25-29
VM-instruction error field , Vol.3-27-1, Vol.3-31-31
VMREAD instruction
VMWRITE instruction
VMX-abort indicator , Vol.3-25-2, Vol.3-26-21
See also: VM entries, VM exits, VMM, VMX
VME (virtual-8086 mode extensions) flag, CR4 control register , 
Vol.3-2-11, Vol.3-2-17, Vol.1-23-18
VMINPH—Return Minimum of Packed FP16 Values , Vol.2-5-404
VMINSH—Return Minimum Scalar FP16 Value , Vol.2-5-406
VMLAUNCH instruction , Vol.1-5-38, Vol.1-5-39, Vol.3-31-1
VMM, Vol.1-6-1
VM exits , Vol.3-28-1See also: VMCS, VM entries, VM exits, VMX
VMOVSH—Move Scalar FP16 Value , Vol.2-5-408
VMOVW—Move Word , Vol.2-5-410
VMPTRLD instruction , Vol.1-5-38, Vol.3-31-1
VMPTRST instruction , Vol.1-5-38, Vol.1-5-39, Vol.3-31-1
VMREAD instruction , Vol.1-5-38, Vol.1-5-39, Vol.3-31-1
field encodings , Vol.1-B-1
VMRESUME instruction , Vol.1-5-38, Vol.1-5-39, Vol.3-31-1
VMULPH—Multiply Packed FP16 Values , Vol.2-5-411
VMULSH—Multiply Scalar FP16 Values , Vol.2-5-413
VMWRITE instruction , Vol.1-5-38, Vol.1-5-39, Vol.3-31-1
VMX
A20M# signal , Vol.3-24-4
capability MSRs
overview , Vol.3-24-2, Vol.1-A-1
IA32_VMX_BASIC MSR , Vol.3-25-3, Vol.1-A-1, Vol.1-A-2, 
Vol.4-2-78, Vol.4-2-92, Vol.4-2-102, Vol.4-2-163, Vol.4-2-212, Vol.4-2-474, Vol.4-2-490
IA32_VMX_CR4_FIXED0 MSR , Vol.4-2-79, Vol.4-2-92, 
IA32_VMX_CR4_FIXED1 MSR , Vol.4-2-79, Vol.4-2-92, 
IA32_VMX_EXIT_CTLS MSR , Vol.1-A-2, Vol.1-A-4, Vol.1-A-5, 
IA32_VMX_MISC MSR , Vol.3-25-6, Vol.3-27-3, Vol.3-27-13, 
Vol.4-32-26, Vol.1-A-6, Vol.4-2-78, Vol.4-2-92, Vol.4-2-102, Vol.4-2-164, Vol.4-2-212, Vol.4-2-475, Vol.4-2-490
IA32_VMX_PINBASED_CTLS MSR , Vol.1-A-2, Vol.1-A-3, 
IA32_VMX_PROCBASED_CTLS MSR , Vol.3-25-10, Vol.1-A-2, 
Vol.1-A-3, Vol.1-A-4, Vol.1-A-5, Vol.1-A-8, Vol.1-A-9, Vol.4-2-78, Vol.4-2-79, Vol.4-2-92, Vol.4-2-102, Vol.4-2-103, Vol.4-2-163, Vol.4-2-164, Vol.4-2-212, Vol.4-2-213, Vol.4-2-261, Vol.4-2-474, Vol.4-2-490
IA32_VMX_VMCS_ENUM MSR , Vol.4-2-475
CPUID instruction , Vol.3-24-2, Vol.1-A-1
CR4 control register , Vol.3-24-3
CR4 fixed bits , Vol.1-A-7
entering operation , Vol.3-24-3
guest software , Vol.3-24-1
INIT# signal , Vol.3-24-4
instruction set , Vol.1-5-38, Vol.3-24-2
introduction , Vol.1-2-20, Vol.3-24-1
microcode update facilities , Vol.3-26-12
non-root operation , Vol.3-24-1
event blocking , Vol.3-26-13
instruction changes , Vol.3-26-7
overview , Vol.3-26-1
task switches not allowed , Vol.3-26-13
see VM exits
operation restrictions , Vol.3-24-3
root operation , Vol.3-24-1
SMM
CR4.VMXE reserved , Vol.4-32-19
VMCS pointer , Vol.4-32-17Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -39INDEX
testing for support , Vol.3-24-2
Virtual machine monitor (VMM) , Vol.1-2-20
virtualization , Vol.1-2-20
virtual-machine control structure (VMCS) , Vol.3-24-2
virtual-machine monitor (VMM) , Vol.3-24-1
VM entries and exits , Vol.3-24-1
VM exits , Vol.3-28-1
VMCS pointer , Vol.3-24-2
VMM life cycle , Vol.3-24-2
VMXOFF instruction , Vol.3-24-3
VMXON instruction , Vol.3-24-3
VMXON pointer , Vol.3-24-3
VMXON region , Vol.3-24-3
See also:VMM, VMCS, VM entries, VM exits
VMXOFF instruction , Vol.1-5-38, Vol.3-24-3, Vol.3-31-1
VMXON instruction , Vol.1-5-38, Vol.3-24-3, Vol.3-31-1
VP2INTERSECTD/VP2INTERSECTQ—Compute Intersection Between 
DWORDS/QUADWORDS to a Pair of Mask Registers , 
Vol.2-5-414
VPBLENDD—Blend Packed Dwords , Vol.2-5-416
VPBLENDMB/VPBLENDMW—Blend Byte/W ord Vectors Using an Opmask 
Control , Vol.2-5-418
VPBLENDMD/VPBLENDMQ—Blend Int32/ Int64 Vectors Using an OpMask 
Control , Vol.2-5-420
VPBROADCASTB/W/D/Q—Load With Broadcast Integer Data From General 
Purpose Register , Vol.2-5-423
VPBROADCAST—Load Integer and Broadcast , Vol.2-5-426
VPBROADCASTM—Broadcast Mask to Vector Register , Vol.2-5-435
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask , Vol.2-5-437
VPCMPD/VPCMPUD—Compare Packed Integer Values Into Mask , 
Vol.2-5-440
VPCMPQ/VPCMPUQ—Compare Packed Integer Values into Mask , 
Vol.2-5-443
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask , 
Vol.2-5-446
VPCOMPRESSB/VCOMPRESSW—Store Spar se Packed Byte/Word Integer 
Values Into Dense Memory/Register , Vol.2-5-449
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values Into 
Dense Memory/Register , Vol.2-5-452
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values Into 
Dense Memory/Registe , Vol.2-5-454
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed 
Dword/Qword Values Into Dense Memory/ Register , 
Vol.2-5-456
VPDPBUSD—Multiply and Add Unsigned and Signed Bytes , Vol.2-5-459
VPDPBUSDS—Multiply and Add Unsigned and Signed Bytes With 
Saturation , Vol.2-5-461
VPDPWSSD—Multiply and Add Signed Word Integers , Vol.2-5-463
VPDPWSSDS—Multiply and Add Signed  Word Integers With Saturation , 
Vol.2-5-465
VPERM2F128—Permute Floating-Point Values , Vol.2-5-467
VPERM2I128—Permute Integer Values , Vol.2-5-469
VPERMB—Permute Packed Bytes Elements , Vol.2-5-471
VPERMD/VPERMW—Permute Packed Doubleword/Word Elements , 
Vol.2-5-473
VPERMI2B - Full Permute of Bytes fr om Two Tables Overwriting the Index
, Vol.1-6-6
VPERMI2B—Full Permute of Bytes From  Two Tables Overwriting the Index
, Vol.2-5-476
VPERMI2W/D/Q/PS/PD—Full Permute Fr om Two Tables Overwriting the 
Index , Vol.2-5-478
VPERMILPD—Permute In-Lane of Pairs of  Double Precision Floating-Point

VPERMILPD—Permute In-Lane of Pairs of  Double Precision Floating-Point 
Values , Vol.2-5-484
VPERMILPS—Permute In-Lane of Quadruples of Single Precision 
Floating-Point Values , Vol.2-5-489
VPERMPD—Permute Double Precision Floating-Point Elements , 
Vol.2-5-494
VPERMPS—Permute Single Precision Floating-Point Elements , 
Vol.2-5-497
VPERMQ—Qwords Element Permutation , Vol.2-5-500VPERMT2B—Full Permute of Bytes From  Two Tables Overwriting a Table
, Vol.2-5-503
VPERMT2W/D/Q/PS/PD—Full Permute Fr om Two Tables Overwriting One 
Table , Vol.2-5-505
VPEXPANDB/VPEXPANDW—Expand Byte/Word Values , Vol.2-5-510
VPEXPANDD—Load Sparse Packed Doubleword Integer Values From 
Dense Memory/Register , Vol.2-5-513
VPEXPANDQ—Load Sparse Packed Quad word Integer Values From Dense 
Memory/Register , Vol.2-5-515
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With 
Signed Dword Indices , Vol.2-5-521
VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed 
Dword/Qword Indices , Vol.2-5-517
VPGATHERDQ/VPGATHERQQ—Gather Packed Qword values Using Signed 
Dword/Qword Indices , Vol.2-5-524
VPGATHERQD/VPGATHERQQ—Gather Pack ed Dword, Packed Qword with 
Signed Qword Indices , Vol.2-5-528
VPLZCNTD/Q—Count the Number of Lead ing Zero Bits for Packed Dword, 
Packed Qword Values , Vol.2-5-531
VPMADD52HUQ—Packed Multiply of Unsigned 52-Bit Unsigned Integers 
and Add High 52-Bit Products to 64-Bit Accumulators , 
Vol.2-5-534
VPMADD52LUQ—Packed Multiply of Unsigned 52-Bit Integers and Add the 
Low 52-Bit Products to Qword Accumulators , Vol.2-5-536
VPMASKMOV—Conditional SIMD Integer Packed Loads and Stores , 
Vol.2-5-538
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector 
Register to a Mask , Vol.2-5-541
VPMOVDB/VPMOVSDB/VPMOVUSDB - Down Convert DWord to Byte , 
Vol.2-5-544
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte , 
VPMOVDW/VPMOVSDW/VPMOVUSDW - Down Convert DWord to Word , 
Vol.2-5-548
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word , 
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask 
Register to a Vector Register , Vol.2-5-552
VPMOVQB/VPMOVSQB/VPMOVUSQB - Down Convert QWord to Byte , 
Vol.2-5-555
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte , 
VPMOVQD/VPMOVSQD/VPMOVUSQD - Down Convert QWord to DWord , 
Vol.2-5-559
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord , 
VPMOVQW/VPMOVSQW/VPMOVUSQW - Down Convert QWord to Word , 
Vol.2-5-563
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word , 
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte , 
Vol.2-5-567
VPMULTISHIFTQB – Select Packed Unaligned Bytes from Quadword Source
, Vol.2-5-415
VPMULTISHIFTQB—Select Packed Unaligned Bytes From Quadword 
Sources , Vol.2-5-571
VPOPCNT—Return the Count of Number of Bits Set to 1 in 
BYTE/WORD/DWORD/QWORD , Vol.2-5-573
VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate Left , Vol.2-5-576
VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate Right , Vol.2-5-580
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter 
Packed Dword, Packed Qword with Signed Dword, Signed 
Qword Indices , Vol.2-5-584
VPSHLD—Concatenate and Shift Packed Data Left Logical , Vol.2-5-588
VPSHLDV—Concatenate and Variable Shift Packed Data Left Logical , 
Vol.2-5-591
VPSHRD—Concatenate and Shift Packed Data Right Logical , Vol.2-5-594
VPSHRDV—Concatenate and Variable Shift Packed Data Right Logical , 
Vol.2-5-597
VPSHUFBITQMB—Shuffle Bits From Quadword Elements Using Byte 
Indexes Into Mask , Vol.2-5-600INDEX
Index-40 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical , 
Vol.2-5-601
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic , 
Vol.2-5-606
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical , 
Vol.2-5-611
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic , Vol.2-5-616
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set 
Mask , Vol.2-5-619
VPTESTNMB/W/D/Q—Logical NAND and Set , Vol.2-5-622
VRANGEPD—Range Restriction Calculation for Packed Pairs of Float64 
Values , Vol.2-5-625
VRANGESD—Range Restriction Calculatio n From a Pair of Scalar Float64 
Values , Vol.2-5-632
VRANGESS—Range Restriction Calculatio n From a Pair of Scalar Float32 
Values , Vol.2-5-635
VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values
, Vol.2-5-638
VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values , 
Vol.2-5-642
VRCP14SD—Compute Approximate Recipr ocal of Scalar Float64 Value , 
Vol.2-5-640
VRCP14SS—Compute Approximate Recipr ocal of Scalar Float32 Value , 
Vol.2-5-644
VRCP28SD—Approximation to the Recipr ocal of Scalar Double-Precision 
Floating-Point Value with Less Than 2^-28 Relative Error , 
VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision 
Vol.1-6-26
VRCPPH—Compute Reciprocals of Packed FP16 Values , Vol.2-5-646
VRCPSH—Compute Reciprocal of Scalar FP16 Value , Vol.2-5-648
VREDUCEPD—Perform Reduction Tran sformation on Packed Float64 
Values , Vol.2-5-649
VREDUCEPH—Perform Reduction Transf ormation on Packed FP16 Values
, Vol.2-5-652
VREDUCEPS—Perform Reduction Tran sformation on Packed Float32 
Values , Vol.2-5-661
VREDUCESD—Perform a Reduction Tran sformation on a Scalar Float64 
Value , Vol.2-5-657
VREDUCESH—Perform Reduction Transf ormation on Scalar FP16 Value , 
Vol.2-5-659
VREDUCESS—Perform a Reduction Tran sformation on a Scalar Float32 
Value , Vol.2-5-661
VRNDSCALEPD—Round Packed Float64 Va lues to Include a Given Number 
of Fraction Bits , Vol.2-5-663
VRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of 
Fraction Bits , Vol.2-5-666
VRNDSCALEPS—Round Packed Float32 Va lues to Include a Given Number 
of Fraction Bits , Vol.2-5-669
VRNDSCALESD—Round Scalar Float64 Va lue to Include a Given Number of 
Fraction Bits , Vol.2-5-672
VRNDSCALESH—Round Scalar FP16 Valu e to Include a Given Number of 
Fraction Bits , Vol.2-5-674
VRNDSCALESS—Round Scalar Float32 Va lue to Include a Given Number of 
Fraction Bits , Vol.2-5-676
VRSQRT14PD—Compute Approximate Re ciprocals of Square Roots of 
Packed Float64 Values , Vol.2-5-678
VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of 
Packed Float32 Values , Vol.2-5-682
VRSQRT14SD—Compute Approximate Recipr ocal of Square Root of Scalar 
Float64 Value , Vol.2-5-680
VRSQRT14SS—Compute Approximate Recipr ocal of Square Root of Scalar 
Float32 Value , Vol.2-5-684
VRSQRT28PS—Approximation to the Reci procal Square Root of Packed 
Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
, Vol.1-6-32
VRSQRT28SD—Approximation to the Reci procal Square Root of Scalar 
Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
, Vol.1-6-30VRSQRT28SS—Approximation to the Reci procal Square Root of Scalar 
Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error
, Vol.1-6-34
VRSQRTPH—Compute Reciprocals of Sq uare Roots of Packed FP16 Values
, Vol.2-5-686
VRSQRTSH—Compute Approximate Recipr ocal of Square Root of Scalar 
FP16 Value , Vol.2-5-688
VSCALEFPD—Scale Packed Float64 Values With Float64 Values , 
Vol.2-5-689
VSCALEFPH—Scale Packed FP16 Values with FP16 Values , Vol.2-5-692
VSCALEFPS—Scale Packed Float 32 Values With Float32 Values , 
Vol.2-5-694
VSCALEFSD—Scale Scalar Float64 Values With Float64 Values , 
Vol.2-5-697
VSCALEFSH—Scale Scalar FP16 Values with FP16 Values , Vol.2-5-699
VSCALEFSS—Scale Scalar Float32 Value With Float32 Value , Vol.2-5-701
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter 
Packed Single, Packed Double with Signed Dword and Qword Indices
, Vol.2-5-703
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF
1QPD—Sparse Prefetch Packed SP /DP Data Values with Signed 
Dword, Signed Qword Indices Using T1 Hint with Intent to Write
, Vol.1-6-38
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed 
Values at 128-Bit Granularity , Vol.2-5-707
VSQRTPH—Compute Square Root of Packed FP16 Values , Vol.2-5-712
VSQRTSH—Compute Square Root of Scalar FP16 Value , Vol.2-5-714
VSUBPH—Subtract Packed FP16 Values , Vol.2-5-715
VSUBSH—Subtract Scalar FP16 Value , Vol.2-5-717
VTESTPD/VTESTPS—Packed Bit Test , Vol.2-5-718
VUCOMISH—Unordered Compare Scal ar FP16 Values and Set EFLAGS , 
Vol.2-5-721
VZEROALL—Zero XMM, YMM, and ZMM Registers , Vol.2-5-722
VZEROUPPER—Zero Upper Bits of YMM and ZMM Registers , Vol.2-5-723
W
Waiting instructions, x87 FPU , Vol.1-8-24
WAIT/FWAIT instructions , Vol.1-8-23, Vol.1-8-31, Vol.1-6-2, Vol.3-6-32, 
Vol.1-23-8, Vol.1-23-15, Vol.1-23-16
WB (write back) memory type , Vol.3-9-17, Vol.3-12-7, Vol.3-12-8
WB (write-back) pin (Pentium processor) , Vol.3-12-13
WBINVD instruction , Vol.1-6-3, Vol.1-6-5, Vol.3-2-25, Vol.3-5-24, 
Vol.3-12-16, Vol.3-12-17, Vol.1-23-4
WBINVD/INVD bit , Vol.2-3-219
WB/WT# pins , Vol.3-12-13
WC buffer (see Write combining (WC) buffer)
WC memory type , Vol.1-10-12
WC (write combining)
flag, IA32_MTRRCAP MSR , Vol.3-12-22
memory type , Vol.3-12-7, Vol.3-12-8
wide dynamic execution , Vol.1-2-4
Word , Vol.1-4-1

W
WP (write protect) flag
CR0 control register , Vol.3-2-15, Vol.3-5-28, Vol.1-23-18
Wraparound mode (MMX instructions) , Vol.1-9-4
Write
hit, Vol.3-12-5
Write combining (WC) buffer , Vol.3-12-4, Vol.3-12-8
Write-back and invalidate caches , Vol.1-6-3
Write-back caching , Vol.3-12-6
WRMSR instruction , Vol.1-6-9, Vol.3-2-20, Vol.3-2-22, Vol.3-2-27, 
Vol.3-5-24, Vol.3-9-18, Vol.3-18-35, Vol.3-18-40, Vol.3-18-43, Vol.3-20-109, Vol.3-20-134, Vol.3-20-135, Vol.3-20-136, Vol.1-23-5, Vol.1-23-36
WT (write through) memory type , Vol.3-12-7, Vol.3-12-8
WT# (write-through) pin (Pentium processor) , Vol.3-12-13Combined Volumes 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Index -41INDEX
X
x2APIC ID , Vol.3-11-40, Vol.3-11-41, Vol.3-11-44, Vol.3-11-46
x2APIC Mode , Vol.3-11-31, Vol.3-11-37, Vol.3-11-38, Vol.3-11-40, 
Vol.3-11-41, Vol.3-11-44, Vol.3-11-45, Vol.3-11-46
x87 FPU
64-bit mode , Vol.1-8-1
checking for pending x87 FPU exceptions , Vol.1-6-2
compatibility mode , Vol.1-8-1
compatibility with IA-32 x87 FPUs and math coprocessors , Vol.1-23-7
configuring the x87 FPU environment , Vol.3-10-6
constants , Vol.2-3-405
control word , Vol.1-8-7
data pointer , Vol.1-8-9
data registers , Vol.1-8-1
device-not-available exception , Vol.3-6-32
effects of MMX instructions on x87 FPU state , Vol.3-13-3
effects of MMX, x87 FPU, FXSAVE, and FXRSTOR instructions on x87 
FPU tag word , Vol.3-13-3
error signals , Vol.1-23-11
execution environment , Vol.1-8-1
floating-point data types , Vol.1-8-13
fopcode compatibility mode , Vol.1-8-10
IEEE Standard 754 , Vol.1-8-1
initialization , Vol.2-3-396, Vol.3-10-5
instruction opcodes , Vol.1-A-20
instruction pointer , Vol.1-8-9
instruction set , Vol.1-8-15
instruction synchronization , Vol.1-23-15
last instruction opcode , Vol.1-8-10
overview of registers , Vol.1-3-2
programming , Vol.1-8-1
register stack , Vol.1-8-1
register stack, aliasing with MMX registers , Vol.3-13-2
register stack, parameter passing , Vol.1-8-3
registers , Vol.1-8-1
save and restore state instructions , Vol.1-5-14
saving registers , Vol.1-11-23
setting up for software emulation of x87 FPU functions , Vol.3-10-6
state , Vol.1-8-11
state, image , Vol.1-8-11, Vol.1-8-12
state, saving , Vol.1-8-11, Vol.1-8-12
status register , Vol.1-8-4
tag word , Vol.1-8-8
transcendental instruction accuracy , Vol.1-8-21
using TS flag to control saving of x87 FPU state , Vol.1-14-7
x87 floating-point error exception (#MF) , Vol.3-6-48
x87 FPU control word
compatibility, IA-32 processors , Vol.1-23-9
description of , Vol.1-8-7
exception-flag mask bits , Vol.1-8-7
infinity control flag , Vol.1-8-8
loading , Vol.2-3-407, Vol.2-3-409
precision control (PC) field , Vol.1-8-7
RC field , Vol.2-3-398, Vol.2-3-405, Vol.2-3-437
restoring , Vol.2-3-424
rounding control (RC) field , Vol.1-4-18, Vol.1-8-8
saving , Vol.2-3-426, Vol.2-3-441
storing , Vol.2-3-439
x87 FPU data pointer , Vol.2-3-409, Vol.2-3-424, Vol.2-3-426, 
Vol.2-3-441
x87 FPU exception handling
description of , Vol.1-8-31
floating-point exception summary , Vol.1-C-1
native mode , Vol.1-8-32
x87 FPU floating-point error exception (#MF) , Vol.3-6-48
x87 FPU floating-point exceptionsdenormal operand exception , Vol.1-8-28
division-by-zero , Vol.1-8-28
exception conditions , Vol.1-8-26
exception summary , Vol.1-C-1
inexact-result (precision) , Vol.1-8-30
invalid arithmetic operand , Vol.1-8-26, Vol.1-8-27
numeric overflow , Vol.1-8-28
numeric underflow , Vol.1-8-29
software handling , Vol.1-8-31
stack overflow , Vol.1-8-4, Vol.1-8-26
stack underflow , Vol.1-8-4, Vol.1-8-26
summary of , Vol.1-8-24
synchronization , Vol.1-8-30
x87 FPU instruction pointer , Vol.2-3-409, Vol.2-3-424, Vol.2-3-426, 
x87 FPU instructions
arithmetic vs. non-arithmetic instructions , Vol.1-8-25
basic arithmetic , Vol.1-8-17
comparison and classification , Vol.1-8-18
control , Vol.1-8-23
data transfer , Vol.1-8-15
exponential , Vol.1-8-21
load constant , Vol.1-8-17
logarithmic , Vol.1-8-21
operands , Vol.1-8-15
overview , Vol.1-8-15
save and restore state , Vol.1-8-23
scale , Vol.1-8-21
transcendental , Vol.1-8-21
transitions between x87 FPU and MMX code , Vol.1-9-9
trigonometric , Vol.1-8-20
unsupported , Vol.1-8-24
x87 FPU last opcode , Vol.2-3-409, Vol.2-3-424, Vol.2-3-426, 
x87 FPU status word
condition code flags , Vol.1-8-4, Vol.2-3-375, Vol.2-3-391, 
Vol.2-3-451, Vol.2-3-453, Vol.2-3-455, Vol.1-23-8
DE flag , Vol.1-8-28
exception flags , Vol.1-8-5
loading , Vol.2-3-409
OE flag , Vol.1-8-28
PE flag , Vol.1-8-4
saving , Vol.2-3-426, Vol.2-3-441, Vol.2-3-443
stack fault flag , Vol.1-8-6
TOP field , Vol.1-8-2, Vol.2-3-395
top of stack (TOP) pointer , Vol.1-8-4
x87 FPU flags affected by instructions , Vol.2-3-14
x87 FPU tag word , Vol.1-8-8, Vol.1-9-9, Vol.2-3-409, Vol.2-3-424, 
Vol.2-3-426, Vol.2-3-441, Vol.1-23-9
XABORT - Transaction Abort , Vol.1-6-17
XADD instruction , Vol.1-7-4, Vol.2-3-610, Vol.1-6-23, Vol.3-9-4, 
xAPIC , Vol.3-11-38, Vol.3-11-40
determining lowest priority processor , Vol.3-11-25
interrupt control register , Vol.3-11-21
introduction to , Vol.3-11-4
message passing protocol on system bus , Vol.3-11-33
new features , Vol.1-23-28
spurious vector , Vol.3-11-32
using system bus , Vol.3-11-4
xAPIC Mode , Vol.3-11-31, Vol.3-11-37, Vol.3-11-41, Vol.3-11-44, 
Vol.3-11-46
XCHG instruction , Vol.1-7-4, Vol.2-3-610, Vol.1-6-28, Vol.3-9-3, 
Vol.3-9-4, Vol.3-9-16
XCR0 , Vol.1-14-15, Vol.1-6-66, Vol.1-6-67, Vol.3-2-19
XEND - Transaction End , Vol.1-6-30
XFEATURE_ENALBED_MASK , Vol.1-15-4INDEX
Index-42 Combined Volumes 1, 2A, 2B , 2C, 2D, 3A, 3B, 3C, 3D, and 4XGETBV , Vol.1-6-32, Vol.1-6-45, Vol.1-6-50, Vol.1-B-41, Vol.3-2-19, 
Vol.3-2-23, Vol.3-2-24
XLAB instruction , Vol.1-6-34
XLAT instruction , Vol.1-6-34
XLAT/XLATB instruction , Vol.1-7-23
XMM registers
parameters passing in , Vol.1-11-23
XMM registers, saving , Vol.1-14-6
XOR instruction , Vol.1-7-10, Vol.2-3-610, Vol.1-6-36, Vol.3-9-4
XORPD- Bitwise Logical XOR of Packed  Double Precision Floating-Point 
Values , Vol.1-6-38
XORPD instruction , Vol.1-11-7
XORPS- Bitwise Logical XOR of Packed Single Precision Floating-Point 
Values , Vol.2-5-723, Vol.1-6-41
XORPS instruction , Vol.1-10-9
XRSTOR , Vol.1-14-15, Vol.1-15-1, Vol.1-15-4, Vol.1-B-41
XSAVE , Vol.1-14-15, Vol.1-14-20, Vol.1-14-25, Vol.1-14-31, 
Vol.1-14-32, Vol.1-15-1, Vol.1-15-4, Vol.1-15-8, Vol.1-6-32, Vol.1-6-48, Vol.1-6-49, Vol.1-6-52, Vol.1-6-53, Vol.1-6-54, Vol.1-6-55, Vol.1-6-56, Vol.1-6-57, Vol.1-6-58, Vol.1-6-59, Vol.1-6-60, Vol.1-6-62, Vol.1-6-63, Vol.1-6-65, Vol.1-6-66, Vol.1-6-67, Vol.1-B-41, Vol.3-2-19, Vol.1-14-7, Vol.1-14-8, Vol.1-14-9, Vol.1-14-10
XSETBV , Vol.1-6-60, Vol.1-6-66, Vol.1-B-41, Vol.3-2-19, Vol.3-2-21, 
Vol.3-2-23, Vol.3-2-27
XTEST - Test If In Transactional Execution , Vol.1-6-69
Z
ZE (divide by zero exception) flag
ZE (divide by zero exception) flag bit
Zero, floating-point format , Vol.1-4-5, Vol.1-4-14
ZF flag, EFLAGS register , Vol.3-5-25
ZF (zero) flag, EFLAGS register , Vol.1-3-16, Vol.1-A-1, Vol.2-3-208, 
Vol.2-3-582, Vol.2-3-615, Vol.2-3-618, Vol.2-4-555, Vol.2-5-152
ZM (divide by zero exception) mask bit
x87 FPU control word , Vol.1-8-7, Vol.1-8-28
VF, Vol.2-5-201, Vol.2-5-219, Vol.2-5-250, Vol.2-5-265Document Number: 252046-074
Intel® 64 and IA-32 Architectures
Software Developer’s Manual  
Documentation Changes
Notice:  The Intel® 64 and IA-32 architectures may contain design defects or errors known as errata 
that may cause the product to deviate from publishe d specifications. Current characterized errata are 
documented in the specification updates.2I n t e l® 64 and IA-32 Architectures Software De veloper’s Manual Documentation Changes
Your costs and results may vary. 
concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any 
patent claim thereafter drafted which in cludes subject matter disclosed herein.
All product plans and roadmaps are subject to change without notice.

The products described may co ntain design defects or e rrors known as errata whic h may cause the product to 
deviate from published sp ecifications. Current ch aracterized errata are available on request.
Intel disclaims all express and implie d warranties, including without limitation, the implied warranties of 
merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from 
course of performance, course of  dealing, or usage in trade.
Code names are used by Intel to iden tify products, technologies, or servic es that are in development and not 
publicly available. These are not “commercial” na mes and not intended to function as trademarks.
No license (express or implied, by esto ppel or otherwise) to any intellectual  property rights is granted by this 
document, with the sole exception that  a) you may publish an unmodified co py and b) code included in this 
document is licensed subject to the Zero-Clause BSD open source license (0BSD), https://opensource.org/
licenses/0BSD . You may create software implem entations based on this document  and in compliance with the 
foregoing that are intended to execute on the Intel produc t(s) referenced in this docu ment. No rights are granted 
to create modifications or de rivatives of this document.
© Intel Corporation. Intel, the Intel logo, and other In tel marks are trademarks of Intel Corporation or its 
subsidiaries. Other names and brands may be claimed as the pr operty of others.Intel® 64 and IA-32 Architectures Software De veloper’s Manual Documentation Changes 3
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Summary Tables of Changes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Documentation Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Revision History
4I n t e l® 64 and IA-32 Architectures Software De veloper’s Manual Documentation Changes
-001 • Initial release November 2002
-002•  Added 1-10 Documentation Changes.
• Removed old Documentation Changes items that already have been 
incorporated in the published Software Developer’s manualDecember 2002
-003• Added 9 -17 Documentation Changes.
• Removed Documentation Change #6 - References to bits Gen and Len 
Deleted.
• Removed Documentation Change #4 - VIF Information Added to CLI 
DiscussionFebruary 2003
-004• Removed Documentation changes 1-17.
•Added Documentation changes 1-24.June 2003
-005• Removed Documentation Changes 1-24.
• Added Documentation Changes 1-15.September 2003
-006 • Added Documentation Changes 16- 34. November 2003
-007• Updated Documentation ch anges 14, 16, 17, and 28.
• Added Documentation Changes 35-45.January 2004
-008• Removed Documentation Changes 1-45.
• Added Documentation Changes 1-5.March 2004
-009 • Added Documentation Changes 7-27. May 2004
-010• Removed Documentation Changes 1-27.
• Added Documentation Changes 1.August 2004
-011 • Added Documentation Changes 2-28. November 2004
-012• Removed Documentation Changes 1-28.
• Added Documentation Changes 1-16.March 2005
-013• Updated title.
• There are no Documentation Changes for this revision of the 
document.July 2005
-014 • Added Documentation Changes 1-21. September 2005
-015• Removed Documentation Changes 1-21.
• Added Documentation Changes 1-20.March 9, 2006
-016 • Added Documentation changes 21-23. March 27, 2006
-017• Removed Documentation Changes 1-23.
• Added Documentation Changes 1-36.September 2006
-018 • Added Documentation Changes 37-42. October 2006
-019• Removed Documentation Changes 1-42.
• Added Documentation Changes 1-19.March 2007
-020 • Added Documentation Changes 20-27. May 2007
-021• Removed Documentation Changes 1-27.
• Added Documentation Changes 1-6November 2007
-022• Removed Documentation Changes 1-6
• Added Documentation Changes 1-6August 2008
-023• Removed Documentation Changes 1-6
• Added Documentation Changes 1-21March 2009Revision History
Intel® 64 and IA-32 Architectures Software De veloper’s Manual Documentation Changes 5
-024• Removed Documentation Changes 1-21
• Added Documentation Changes 1-16June 2009
-025• Removed Documentation Changes 1-16
• Added Documentation Changes 1-18September 2009
-026• Removed Documentation Changes 1-18
• Added Documentation Changes 1-15December 2009
-027• Removed Documentation Changes 1-15
• Added Documentation Changes 1-24March 2010
-028• Removed Documentation Changes 1-24
• Added Documentation Changes 1-29June 2010
-029• Removed Documentation Changes 1-29
• Added Documentation Changes 1-29September 2010
-030• Removed Documentation Changes 1-29
• Added Documentation Changes 1-29January 2011
-031• Removed Documentation Changes 1-29
• Added Documentation Changes 1-29April 2011
-032• Removed Documentation Changes 1-29
• Added Documentation Changes 1-14May 2011
-033• Removed Documentation Changes 1-14
• Added Documentation Changes 1-38October 2011
-034• Removed Documentation Changes 1-38
• Added Documentation Changes 1-16December 2011
-035• Removed Documentation Changes 1-16
• Added Documentation Changes 1-18March 2012
-036• Removed Documentation Changes 1-18
• Added Documentation Changes 1-17May 2012
-037• Removed Documentation Changes 1-17
• Added Documentation Changes 1-28August 2012
-038• Removed Documentation Changes 1-28
• Add Documentation Changes 1-22January 2013
-039• Removed Documentation Changes 1-22
• Add Documentation Changes 1-17June 2013
-040• Removed Documentation Changes 1-17
• Add Documentation Changes 1-24September 2013
-041• Removed Documentation Changes 1-24
• Add Documentation Changes 1-20February 2014
-042• Removed Documentation Changes 1-20
• Add Documentation Changes 1-8February 2014
-043• Removed Documentation Changes 1-8
• Add Documentation Changes 1-43June 2014
-044• Removed Documentation Changes 1-43
• Add Documentation Changes 1-12September 2014
-045• Removed Documentation Changes 1-12
• Add Documentation Changes 1-22January 2015
-046• Removed Documentation Changes 1-22
• Add Documentation Changes 1-25April 2015
-047• Removed Documentation Changes 1-25
• Add Documentation Changes 1-19June 2015Revision Desc ription DateRevision History
6I n t e l® 64 and IA-32 Architectures Software De veloper’s Manual Documentation Changes
-048• Removed Documentation Changes 1-19
• Add Documentation Changes 1-33September 2015
-049• Removed Documentation Changes 1-33
• Add Documentation Changes 1-33December 2015
-050• Removed Documentation Changes 1-33
• Add Documentation Changes 1-9April 2016
-051• Removed Documentation Changes 1-9
• Add Documentation Changes 1-20June 2016
-052• Removed Documentation Changes 1-20
• Add Documentation Changes 1-22September 2016
-053• Removed Documentation Changes 1-22
• Add Documentation Changes 1-26December 2016
-054• Removed Documentation Changes 1-26
• Add Documentation Changes 1-20March 2017
-055• Removed Documentation Changes 1-20
• Add Documentation Changes 1-28July 2017
-056• Removed Documentation Changes 1-28
• Add Documentation Changes 1-18October 2017
-057• Removed Documentation Changes 1-18
• Add Documentation Changes 1-29December 2017
-058• Removed Documentation Changes 1-29
• Add Documentation Changes 1-17March 2018
-059• Removed Documentation Changes 1-17
• Add Documentation Changes 1-24May 2018
-060• Removed Documentation Changes 1-24
• Add Documentation Changes 1-23November 2018
-061• Removed Documentation Changes 1-23
• Add Documentation Changes 1-21January 2019
-062• Removed Documentation Changes 1-21
• Add Documentation Changes 1-28May 2019
-063• Removed Documentation Changes 1-28
• Add Documentation Changes 1-34October 2019
-064• Removed Documentation Changes 1-34
• Add Documentation Changes 1-36May 2020
-065• Removed Documentation Changes 1-36
• Add Documentation Changes 1-31November 2020
-066• Removed Documentation Changes 1-31
• Add Documentation Changes 1-24April 2021
-067• Removed Documentation Changes 1-24
• Add Documentation Changes 1-30June 2021
-068• Removed Documentation Changes 1-30
• Add Documentation Changes 1-29December 2021
-069• Removed Documentation Changes 1-29
• Add Documentation Changes 1-18April 2022
-070• Removed Documentation Changes 1-18
• Add Documentation Changes 1-41December 2022
-071• Removed Documentation Changes 1-41
• Add Documentation Changes 1-23March 2023Revision Description DateRevision History
Intel® 64 and IA-32 Architectures Software De veloper’s Manual Documentation Changes 7
§-072• Removed Documentation Changes 1-23
• Add Documentation Changes 1-19June 2023
-073• Removed Documentation Changes 1-19
• Add Documentation Changes 1-19September 2023
-074• Removed Documentation Changes 1-19
• Add Documentation Changes 1-20December 2023Revision Desc ription DateRevision History
8I n t e l® 64 and IA-32 Architectures Software De veloper’s Manual Documentation Changes

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 7Preface
This document is an update to the specifications contained in the Affected Documents  table below. This 
document is a compilation of device and documentation errata, specification clarifications and changes. It is 
intended for hardware system manufacturers and software  developers of applications, operating systems, or 
tools.
Affected Documents
Nomenclature
Documentation Changes  include typos, errors, or omissions from the current published specifications. These 
will be incorporated in any new release of the specification.Document TitleDocument Number/
Location
Intel® 64 and IA-32 Architec tures Software Developer’s Manual,  Volume 1: Basic Architecture 253665
Intel® 64 and IA-32 Archit ectures Software Developer’s Manua l, Volume 2A: Instruction Set 
Reference, A-L253666
Intel® 64 and IA-32 Archit ectures Software Developer’s Manua l, Volume 2B: Instruction Set 
Reference, M-U253667
Intel® 64 and IA-32 Archit ectures Software Developer’s Manua l, Volume 2C: Instruction Set 
Reference, V326018
Intel® 64 and IA-32 Archit ectures Software Developer’s Manua l, Volume 2D: Instruction Set 
Reference, W-Z334569
Intel® 64 and IA-32 Architecture s Software Developer’s Ma nual, Volume 3A: System 
Programming Guide, Part 1253668
Intel® 64 and IA-32 Architecture s Software Developer’s Ma nual, Volume 3B: System 
Programming Guide, Part 2253669
Intel® 64 and IA-32 Architecture s Software Developer’s Ma nual, Volume 3C: System 
Programming Guide, Part 3326019
Intel® 64 and IA-32 Architecture s Software Developer’s Ma nual, Volume 3D: System 
Programming Guide, Part 4332831
Intel® 64 and IA-32 Archit ectures Software Developer’s Manua l, Volume 4: Model Specific 
Registers335592Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 8Summary Tables of Changes
The following table indicates documentat ion changes which apply to the Intel® 64 and IA-32 architectures. This 
table uses the following notations:
Codes Used in Summary Tables
A violet  change bar to left of table row indicates this erratum is either new or modified from the previous version 
of the document.
No. DOCUMENTATION CHANGES
1 Updates to Chapter 1, Volume 1
2 Updates to Chapter 13, Volume 1
3 Updates to Chapter 1, Volume 2A
4 Updates to Chapter 2, Volume 2A
5 Updates to Chapter 3, Volume 2A
6 Updates to Chapter 4, Volume 2B
7 Updates to Chapter 5, Volume 2C
8 Updates to Chapter 1, Volume 3A
9 Updates to Chapter 2, Volume 3A
10 Updates to Chapter 9, Volume 3A
11 Updates to Chapter 12, Volume 3A
12 Updates to Chapter 16, Volume 3B
13 Updates to Chapter 19, Volume 3B
14 Updates to Chapter 23, Volume 3B
15 Updates to Chapter 25, Volume 3C
16 Updates to Chapter 27, Volume 3C
17 Updates to Chapter 28, Volume 3C
18 Updates to Chapter 32, Volume 3C
19 Updates to Chapter 1, Volume 4
20 Updates to Chapter 2, Volume 4Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 9Documentation Changes
Changes to the Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes follow, and are listed 
by chapter. Only chapters with chan ges are included in this document.Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 10Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 111. Updates to Chapter 1, Volume 1
Change bars and violet  text show changes to Chapter 1 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1: Basic Architecture.
------------------------------------------------------------------------------------------
Changes to this chapter: 
• Added the 5th generation Intel® Xeon® Scalable Processor Family and the Intel® Core™ Ultra 7 processors to 
the list of supported processors in Section 1.1, “I ntel® 64 and IA-32 Processors Covered in this Manual.”Vol. 1 1-1CHAPTER 1
include: 

code.
sions.
register.
able. 
28
24
20
16
12
8
40Address
NOTE
where:
arise.
DS:FF79H
CS:EIP

DS:FF79H
CS:EIP
#GP(0)
See also: 
tions.pdf
http://www.intel.com/technology/platform-technology/hyper-threading/index.htmIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 132. Updates to Chapter 13, Volume 1
Change bars and violet  text show changes to  Chapter 13 of the Intel® 64 and IA-32 Architectures Software 
Changes to this chapter:
• XFD updates made to Section 13.13, “Memory Access es by the XSAVE Feature Set,” and Section 13.14, 
“Extended Feature Disable (XFD).” Vol. 1 13-1CHAPTER 13
state ).

state ).

IA32_XSS.
NOTE
details:
in XCR0:
XCR0[18:17] have value 00b coming out of RESET. As noted in Section 13.2, a processor allows software to set

XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384

XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
where i≥ 2.
4.
As noted in Section 13.1, the XSAVE feature set manages AVX state as user state component 2. Thus, AVX state is

state.

above.
1.
•If the instruction mask and XSAVE area used by XRSTORS indicates that the user-interrupt state component

1.
cases:
MSR.
MSR.

bitmap):

accesses.
which it may omit saving state components that are in thei r initial configuration) and the modified optimization (by

accesses.
—w= CPL;
accesses.
The operation of XSAVES is similar to that of XSAVEC. The main differences are (1) X SAVES can be executed only

accesses.
occurs.
•w= CPL;
occurs.
accesses.
0 or 1.

0 or 1.
also 1.
an instruction in the XSAVE feature set. An execution of an instruction in the XSAVE feature set may access any byte of any state component on which that execution operates even when saving a state component is omitted 
ations if XCR0[ i]=  0 . )  In compacted format, the IA32_XFD MSR does not impact the computation of XCOMP_BV by  
#NM.)
in its initial state):  it saves bit i of XSTATE_BV field of the XSAVE header as 0;  in addition, XSAVE saves the 
modify the IA32_XFD_ERR MSR. Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 133. Updates to Chapter 1, Volume 2A
Developer’s Manual, Volume 2A: Instruction Set Reference, A-L.
the list of supported processors in Section 1.1, “I ntel® 64 and IA-32 Processors Covered in this Manual.”Vol. 2A 1-1CHAPTER 1

include: 
Some 11th generation Intel® Core™ processors are based on the Tiger Lake microarchitecture, and some are

REFERENCE
2C.
NOTE
where:
28
24
20
16
12
8
40
Address
E, and F.
arise.

E, and F.
arise.
register:
DS:FF79H
CS:EIP
#GP(0)
See also: 
tions.pdf
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm1-10 Vol. 2AABOUT THIS MANUALIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 134. Updates to Chapter 2, Volume 2A
Change bars and violet  text show changes to Chapter 2 of the Intel® 64 and IA-32 Architectures Software 
• Updated Section 2.2.1, “REX Prefixes,” to clarify th at only one meaningful REX prefix is allowed per 
• Corrected two inaccurate cross-references in Sect ion 2.3.12, “Vector SIB (VSIB) Memory Addressing.” 
Previously, this section contained two references to Table 2-3; the correct table is Table 2-13.Vol. 2A 2-1CHAPTER 2
•Group 1
data of
1, 2, or 4
of 1, 2, or 4
AVX)”.
•Group 2
•Group 3
•Group 4
ronment. See “LOCK—Assert LOCK# Signal Prefix” in Chapte r 3, “Instruction Set Reference, A-L,” for a description

•Group 3
•Group 4
behavior.
behavior.
bullet).
RM 000
REG = 001
NOTES:
r8(/r)
BP
1
[BX+SI]
[BX+DI]
[BP+SI]
[BP+DI]
2
[BX]00 000
3
001
41
49
51
59
61
69
71
79
B1

[BX+SI]
[BX+DI]
[BP+SI]
[BP+DI]
2
[BX]00 000
3
001
41
49
51
59
61
69
71
79
B1
NOTES:
r8(/r)
[EAX]
1
disp322
3
F9
NOTES:
r32
0000ECX
1001EDX
2010EBX
3011ESP
4100[*]
5101ESI
6110EDI
7111
[EAX]
[EAX*2]
[EAX*4]
[EAX*8]
CF
of the extended registers  or uses a 64-bit operand. If a REX prefix is used when it has no meaning, it is ignored, as 
Only one meaningful  REX prefix is allowed per inst ruction. If used, the REX prefix  byte must immediately precede 
byte.
of 1, 2, or 4 
2, Grp 3, 
Grp 4
- 7:4 0100
≠11reg r/m
rrr bbb
REX PREFIX  
11reg r/m
rrr bbb

≠11reg r/m
rrr bbb
REX PREFIX  
11reg r/m
rrr bbb
r/m
100reg
rrrscale
ssSIB Byte
REX PREFIX  
Rrrrbase
Bbbbbbb
Xxxxindex
xxx
REX PREFIX  
Bbbbreg
bbb
Table 2-6.
ModR/M or 
NOTES:

as 0000B.
 vvvv10 32
L  7
R X BByte 1
m-mmmm: W
vvvv10 32
L 7
00: None
01: 66
10: F3
ignored.
existing programs the VEX 2nd byte, bits [7:6] must be 11 b. To achieve this, the VEX payload bits are selected to

ignored.
NOTES:
operand.
operand.)
1 256-bit
00B None
01B 66
10B F3
a mechanism that is cognizant of which bits to set. (E.g.,  an OS mechanism that sets the save/restore mask bits

00B None
01B 66
10B F3
15 bytes.
Table 2-13  shows the 32-bit VSIB addressing form. It is organi zed to give 256 possible values of the SIB byte (in 
mode (when address size override prefix is used, but the value of VEX.B is not shown in Table 2-13 ). In 32-bit 
r32
R13D
1
5101
NOTES:
R15D7111
VR0/VR8
VR0/VR8
VR3/VR11
001010
011
4850
58
4951
59
4A52
5A
4B53
5B
4C54
5C
4D55
5D
4E56
5E
4F57
5F
676F777F
VR0/VR8
VR0/VR8
CA
NOTE
NOTE
Type 1AVX,
Type 2AVX,
Type 3AVX,
Type 4AVX,
alignedNo
Type 5AVX, 
Type 7AVX, 
(V)CVTPD2PS, (V)CVTPS2D Q, (V)CVTTPD2DQ, (V)CV TTPS2DQ, (V)DIVPD, (V)DIVPS, (V)DPPD*, (V)DPPS*,

Type 1AVX,
Type 2AVX,
Type 3AVX,
Type 4AVX,
alignedNo
Type 5AVX, 
Type 7AVX, 
(V)SUBPS
VSTMXCSR
Type 1
Type 2
Type 3
Type 5
Exception 
present)
Type 3
Type 8
Type 11
Exception
Real
ments.
Page Fault 
Exception
Real

Page Fault 
Exception
Real
ments.
FFFFH.
Page Fault 
Exception
Real
NOTES:
ments.
FFFFH.
Page Fault 
Exception
Real
ments.
FFFFH.
Page Fault 
Exception
Real
ments.
Page Fault 
Real
Exception
Real
Exception
Real
ments.
FFFFH.
prefix.
Exception
Real

prefix.
Exception
Real
? ‘100b’.
ments.
FFFFH.
Exception
Real
ments. 
FFFFH.
NOTES:
RXBR ’ 0 m m m
W vvvv1 p p
P[15:8]
— Redirect L’L field (P[22:21]) as static rounding cont rol for floating-point instructions with rounding

41
NOTES:
NOTES:
32bit 0 4 4 4
64bit 1 8 8 8
EVEX encodes an embedded broadcast functionality that is  supported on many vector instructions with 32-bit

#UD)NA
NOTES:
NOTES:

NOTES:
Type 
E7NM.128
NOTES:

NOTES:
Exception
Real
Page Fault 
Exception
Real
ments.
Page Fault 
Exception
Real
Page Fault 
class E3.
Exception
Real
Exception
Real
ments.
FFFFH.

ments.
FFFFH.
Exception
Real
Exception
Real
ments.
FFFFH.
Exception
Real
Exception
Real
FFFFH.
Exception
Real
Exception
Real

Exception
Real
ments.
E7NM.
Exception
Real
Exception
Real
Exception
Real
FFFFH.
Exception
Real
Exception
Real
Exception
Real

Exception
Real
Exception
Real
ments.
FFFFH.
Exception
Real
TYPE K21
Exception
Real
Exception
Real
FFFFH.
≠ 1.

Class Description2-72 Vol. 2AINSTRUCTION FORMATIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 135. Updates to Chapter 3, Volume 2A
Change bars and violet  text show changes to Chapter 7 of the Intel® 64 and IA-32 Architectures Software 
• Updated the CPUID instruction to remove “ECX = 0” fr om the Last Branch Records Information Leaf (1CH) 
listing because this leaf does not support sub-leaves.
• Updated the CPUID instruction to ad d the enumeration of INVD execution prevention after BIOS Done.
• Updated the INVD instruction to add BIOS Done addition s to the description and exception sections. Added an 
exception to Real-Address Mode Exceptions regarding reserved memory protections.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-L
CPUID
2 
See also:  
En64-Bit 
EDX “ineI”
NOTES: 
Leaf 1FH.
NOTES: 
04H NOTES:
cache.
NOTES:

states.
set.
NOTE:
CPUID.1A.EAX

(IBPB).
NOTE:
07H NOTES:
ported.
07H NOTES:
1).
0BH NOTES:
The sub-leaves of CPUID leaf 0BH describe an ordered hierarchy of logical processors starting from the

1).
0BH NOTES:
Hierarchy
NOTES:
0DH NOTES:
XCR0. 
NOTES:
zero.
0DH NOTES:
0FH NOTES:
0FH NOTES:

0FH NOTES:
10H NOTES:
10H NOTES:
10H NOTES:
10H NOTES:
12H NOTES:
12H NOTES:
12H NOTES:
Memory.
Memory. 
14H NOTES:
ponent.

ponent.
15H NOTES:
NOTES:
17H NOTES:
NOTES:
17H NOTES:
18H NOTES:
ture. 
18H NOTES:
ture. 
Bit 03: Reserved.Bit 04: If 1, the platform supports the Key Locker MSRs (IA32_COPY_LOCAL_TO_PLATFORM,

1AH NOTES:
NOTE:
1CH NOTE:
value.
1DH NOTES:
1EH NOTE:
1FH NOTES:
Hierarchy
... Tile 4
NOTES:

NOTES:
40000000H
− 
NOTES:
EBX
ECX
EBXECX
EBX
EBX
ECX
ECX
specific.
EBX
ECX
EBX
ECX
NOTES:
NOTE
EAX
ID
NOTE

NOTE
ECX
AES
device.
EDX
PTEs. 
32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in

EBX 0H
ECX 0H
the programming facilities and the architectural performa nce events available in the processor. The details are

FI;
To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input

nated.
“”
“”“nI  ”
“P )R”
Function
Extended
String Not
“ UPC”
“0051”
“\0zHM”
"zHG", or 
"zHT"
Substring
If "zHG"
Operation
EAX = 0:
BREAK;EAX 
= 1H:
processor
1
1
NOTES:
BREAK;EAX 
= 2H:
BREAK;EAX 
= 3H:
BREAKEAX
 = 4H:
BREAK;EAX 
= 5H:
BREAK;EAX 
= 6H:
BREAK;EAX
 = 7H:
BREAK;EAX 
= 8H:
BREAK;EAX 
= 9H:
BREAK;EAX 
= AH:
BREAK
EAX = BH:
BREAK;EAX 
= CH:
BREAK;EAX 
= DH:
BREAK;EAX 
= EH:
BREAK;EAX 
= FH:
BREAK;EAX 
= 10H:
BREAK;EAX 
= 12H:
BREAK;EAX 
= 14H:
EDX := Intel Processor Trace Enumeration Leaf;

ECX := Intel Resource Director Technology Monitoring Enumeration Leaf; 
BREAK;EAX 
= 10H:
BREAK;EAX 
= 12H:
BREAK;EAX 
= 14H:
BREAK;EAX 
= 15H:
BREAK;EAX 
= 16H:
BREAK;EAX 
= 17H:
BREAK;EAX 
= 18H:
BREAK;
EAX = 19H:
BREAK;EAX
 = 1AH:
BREAK;EAX
 = 1BH:
BREAK;EAX
 = 1CH:
BREAK;EAX
 = 1DH:
BREAK;EAX
 = 1EH:
BREAK;EAX
 = 1FH:
BREAK;EAX
 = 20H:
EAX 
BREAK;EAX 
BREAK;EAX
BREAK;EAX
BREAK;EAX 
BREAK;EAX
BREAK;EAX
BREAK;EAX
BREAK;EAX
BREAK;
ESAC;
None.
tion results in an invalid opcode (#UD) exception being generated.INVD—Invalidate Internal CachesINSTRUCTION SET REFERENCE, A-L
signal.
® 
Operation
NOTES:
En64-Bit 
#GP(0) If CPUID.(EAX=07H, ECX=1H):EAX[30] = 1 an d bit 0 is set in MSR_BIOS_DONE (MSR 

En64-Bit 
Same exceptions as in protected mode.Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 136.Updates to Chapter 4, Volume 2B
Change b ars and vio let text show changes to Chapter 4 of the Intel® 64 and IA-32 Architectures Software  
Develo per’s Manual, Volume 2B: Inst ruction Set Reference, M-U.  
--------------------------------------------------- ---------------------------------------
• Updated the PREFETCHW instruc tion table to match the “Op/En” column value to the correct value in the  
Instruction Operand Encoding table. Previously, this table erroneously listed a value of ‘A’ ins tead of the  
correct value of ‘M.’PREFETCHW—Prefetch Data Into Cach es in Anticipation of a WriteINSTRUCTION SET REFERENCE, M-U
ignored.
Operation
None.
0F 0D /1
write.
#UD If the LOCK prefix is used.Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 237. Updates to Chapter 5, Volume 2C
Change bars and violet  text show changes to Chapter 5 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2C: Instruction Set Reference, V.
• Updated the VPBLENDD instruction to use “dword” instead of “word” since the instruction operates on dwords.
• Updated the VGETMANTSS instruction to change “V ector” to “Scalar” in the instruction title.
• Updated the VFCMADDCPH/VFMADDCPH instructions to co rrect the description box for both the normal and
complex conjugate forms. They errone ously reported the opposite descriptions and needed a wording change.
• Updated the VFCMADDCSH/VFMADDCSH instructions to co rrect the description box for both the normal and
complex conjugate forms. They erroneously reported th e opposite descriptions and needed a wording change.
Removed two duplicate intrinsics for the VFCMADDCSH instruction and added two missing intrinsics for the
VFMADDCSH instruction.
• Updated the VFCMULCPH/VFMULCPH instructions to co rrect the description box for both the normal and
• Updated the VFCMULCSH/VFMULCSH instructions to co rrect the description box for both the normal and
complex conjugate forms. They errone ously reported the opposite descriptions and needed a wording change.VFCMADDCPH/VFMADDCPH—Complex Multiply and Accumulate FP16 ValuesINSTRUCTION SET REFERENCE, V
En64/32 
Bit Mode 
xmm2 and complex conjugate of  
ELSE:
ELSE:

ELSE:
Operation
En64/32 
Bit Mode 
xmm2 and complex conj ugate of xmm3/m32, add 
values.
Operation
ELSE:

values.
Operation
ELSE:
En64/32 
Bit Mode 
ELSE:
Operation
KL := VL / 32
En64/32 
Bit Mode 
VFMULCSH xmm1{k1}{z}, xmm2,

Operation
KL := VL / 32
En64/32 
Bit Mode 
KL := VL / 32
#UD If (dest_reg == src1_reg) or (dest_reg == src2_reg).VGETMANTSS—Extract Float32 Vector of No rmalized Mantissa From Float32 ScalarINSTRUCTION SET REFERENCE, V
5-384 Vol. 2CVGETMANTSS—Extract Float32 Vector of Normalized Mantissa From Float32 Scalar
operand) to single-precision floating-point value with th e mantissa normalization and sign control specified by the 
where:
The GetMant() function follows Table 5-8 when dealing with floating-point special numbers.If writemasking is used, the low doub leword element of the destination operand is conditionally updated depending 
En64/32 
Bit Mode 
Feature 
xmm3/m32{sae}, imm8AV / V A V X 5 1 2 F E x t r a c t  t h e  n o r m a l i z e d  mantissa from the low float32 
Vol. 2C 5-385Operation
// getmant_fp32(src, sign_con trol, normalization_interval) is defined in the operation section of VGETMANTPS
getmant_fp32(src, sign_contr ol, normalization_interval)
ELSE 
FI
VGETMANTSS __m128 _mm_mask_getmant_ss(__m128 s, __mmas k8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);VGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum intv, enum sgn, int r);VGETMANTSS __m128 _mm_mask_getmant_round_ss( __m128 s, __mmask8 k, __m128 a, __m1 28 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_maskz_getmant_round_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
See Table 2-47, “Type E3 Class Exception Conditions.”VPBLENDD—Blend Packed DwordsINSTRUCTION SET REFERENCE, V
5-412 Vol. 2CVPBLENDD—Blend Packed Dwords
mask that determines whether the corresponding dword  in the destination is copied from the source. If a bit in the 
mask, corresponding to a dword , is “1", then the dword  is copied, else the dword  is unchanged.
Operation
En64/32
xmm1.
VPBLENDD ymm1, ymm2, ymm3/m256, imm8RVMI V/V AVX2 Select dwords from ymm2 and ymm3/m256 from

En64/32
xmm1.
ymm1.
Vol. 2C 5-413VPBLENDD (VEX.128 encoded version)
None.
#UD If VEX.W = 1.Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 238. Updates to Chapter 1, Volume 3A
Developer’s Manual, Volume 3A: System Programming Guide, Part 1.
the list of supported processors in Section 1.1, “I ntel® 64 and IA-32 Processors Covered in this Manual.”Vol. 3A 1-1CHAPTER 1
253665).
include: 

sors.
(AEX).
NOTE
where:

where:
E, and F.
arise.
28
24
20
16
12
8
40Address
register:
DS:FF79H
CS:EIP
#GP(0)
See also: 
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm1-12 Vol. 3AABOUT THIS MANUALIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 239. Updates to Chapter 2, Volume 3A
• Updated Figure 2-7, “Control Registers,” to add the LA57 bit to the CR4 register (bit 12).Vol. 3A 2-1CHAPTER 2
32e mode.

32e mode.
Code
StackCode
StackCode
Stack
Code
Data
Call-Gate
Interrupt
Vector
Task Gate
Current
Code
Data
StackTask
TSS
Current
Code
StackCode
StackCode
Stack
Call-Gate
PML4
Interrupt
Vector
Page Table
Pg. Dir.
IST
expanded. 
NULL.
a TSS is specified by its descriptor.

or
RSMSMI#
Reset Mode
IA-32e
See**
IA32_EFER
1.
R
FI
DA
CV
M
0C
FA
FP
F1D
FI
FT
FS
FZ
FN
T0 0V
I
PV
I
FO
FI
O
P
L

0C
FA
FP
F1D
FI
FT
FS
FZ
FN
T0 0V
I
PV
I
FO
FI
O
P
L
GDTR
0
Task
mode. 
#GP(0).
mode.
The control registers are summarized below, and each archit ecturally defined control field in these control registers

#GP(0).
mode.
for CR0).
mode. 
M
E
PS
M
A PV
M
EP
V
IT
S
DD
EPS
EP
A
EM
C
EP
G
EP
C
EU
M
I
PL
A
57V
M
X
ES
M
X
EP
C
I
D
EK
P
K
E
P
W
TP
C
CR1
T
SE
TN
EW
PA
MP
EM
PE
MN
WC
DP
GCR0
ReservedC
E
TP
K
S
31 (63)                                                                                                                                                                                                                                                                   0 
31 (63)                                                                                                                                                                                                                                                                   0 
I
N
T
CR0.PG
CR0.CD
occur.
CR0.NW
CR0.AM
CR0.WP
CR0.NE
CR0.ET
set.
CR0.TS

CR0.EM
TS flags.
CR0.MP
CR0.PE
CR3.PCD 
1 or 5-level paging if CR4.PCIDE=1.
CR3.PWT
CR4.VME
CR4.PVI
CR4.TSD
CR4.DE
CR4.PSE
1. Earlier versions of this manual used the term “IA-32e paging” to identify 4-level paging.2-18 Vol. 3ASYSTEM ARCHITECTURE OVERVIEW
CR4.PAE
CR4.MCE
CR4.PGE
CR4.PCE
NOTE

NOTE
CR4.UMIP
CR4.LA57
CR4.VMXE
CR4.SMXE
CR4.PCIDE
CR4.KL
1 
CR4.SMEP
CR4.SMAP
CR4.PKE
1. Software can check CPUID.19H:EBX.AESKLE[bit 0] after setting CR 4.KL to determine whether the AES Key Locker instructions have  
CR4.CET
CR4.PKS
CR4.UINTR
CR8.TPL
used. 
ZMM7).

ZMM7).
register:
DW
D0A
D1W
D10A
DW
D2A
D3W
D32A
DW
D4A
D5W
D54A
DW
D6A
D7W
D76A
DW
D8A
D9W
D98A
DW
D
10A
D
11W
D
11 10A
DW
D
12A
D
13W
D
13 12A
DW
D
14A
D
15W
D
1, 5No
RDMSR
The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level) of a segment selector to match that of

ogy.
below:
L3 Cache
Uncore

Section 2.6).2-28 Vol. 3ASYSTEM ARCHITECTURE OVERVIEWIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1310.Updates to Chapter 9, Volume 3A
Change bars and violet  text show changes to Chapter 9 of the Intel® 64 and IA-32 Architectures Software 
• Added a statement to Section 9.1.2.3, “Features to Di sable Bus Locks,” to indicate processor behavior when 
both bus lock features are enabled. Vol. 3A 9-1CHAPTER 9
data.
NOTE

NOTE
tion.
present.
NOTE
NOTE
Because bus locks may adversely affect performance in certain situations, processors may support two features

NOTE
multiple cache lines causes an alignment-check exception (#AC) with a zero error code.1 The locked access does 
not occur.
1. Other alignment-check exceptions  occur only if CR0.AM = 1, EFLAGS.AC = 1, and CPL = 3. The alignment-check exceptions resulting 
ELIHW;
In a single-processor system for memo ry regions defined as write-back cacheable, the memory-ordering model

with an execution of the CLFLUSHOPT instruction that flushes a cache line other than the one being written.1 
sequence.
1. Earlier versions of this manual specified that writes to memory may be reordered with executions of the CLFLUSH instruction. No 
NOTE
Write A.3
Write A.1
Write B.2
Write A.2
Write B.2

example:
example:
store.

r3 = 1.
rupted.
block. 

instruction stream, but does not affect store operations.1
1. Specifically, LFENCE does not execute until all prior instruct ions have completed locally, and no later instruction begins ex ecution 

control register, with the exception of MOV CR81), MOV (to debug register), WBINVD, and WRMSR2.
memory subsystem. They do not serialize the instruction execution stream:3
Caches.”)
1. MOV CR8 is not defined architecturally as a serializing instruction.
2. An execution of WRMSR to any non-serializing MSR is not serializing. Non-serializing MSRs include the following: IA32_SPEC_CT RL 
3. LFENCE does provide some guarantees on instruction ordering. It does not execute until all pr ior instructions have completed locally, 
message) from the BSP processor. Upon receiving a SIPI message, an AP executes the BIOS AP configuration code,

AP).
system. 
<06H):
10. Converts the base address of the 4-KByte page for the AP’s bootup code into 8-bit vector. The 8-bit vector

systems.
2-bit physical package identifier (which can also be though t of as a socket identifier). In systems that configure

ID. 
1Figure 9-2.  Interpretation of APIC ID in Early MP Systems0
•Addressable IDs for processor cores in the same Package1 (CPUID.(EAX=4, ECX=02):EAX[31:26] + 
1 = Y) — Indicates the maximum number of addressable IDs attributable to processor cores (Y) in the physical 
package.
steps:
1. Operating system and BIOS may implement features that reduce the number of logical processors available in a platform to appl ica-
1. Software must check CPUID for its support of leaf 4 when implementing support for multi-core. If CPUID leaf 4 is not availabl e at run-
2. Maximum number of cores in the physical package must be queried by executing CPUID with EAX=4 and a valid ECX input value. 
symmetric multiprocessing (SMP) techniques. For example,  the operating-system can use a time-slice or load

pointer)
State
State
sors.

NOTE
•Caches.
selected.

NOTE

NOTE
DIE_ID
TILE_ID
MODULE_ID
CORE_ID
Q
R
CORE
LOGICAL 
PROCESSOR
Q_ID
R_ID
CORE_ID
NOTE
cores.
//
software)
//
return 0;
}
{
//
ECX++;
}
 
return -1;

//
ECX++;
}
 
return -1;
3H 1H 0H 1H
6H 3H 0H 0H
7H 3H 0H 1H
NOTE:
CORE_ID
2H 0H 1H 0H
5H 1H 0H 1H
0H 0H 0H 0H
1H 0H 0H 1H
4H 0H 2H 0H
7H 0H 3H 1H
12H 1H 1H 0H
15H 1H 2H 1H
Software can gather the initial APIC_IDs for each logical processor supported by the operating system at runtime1 
2:EAX[31:26], and CPUID.43:EAX[25:14]. The algorithms below assume the 
1. As noted in Section 9.6 and Section 9.9.3, the number of logica l processors supported by the OS at runtime may be less than t he 
2. Maximum number of addressable ID for processor cores in a phys ical processor is obtained by executing CPUID with EAX=4 and a 
3. Maximum number addressable ID for processor cores sharing the target cache leve l is obtained by executing CPUID with EAX = 4 
package. This size parameters can be used to derive  the width of an extraction bitmask to enumerate the

{
}return 0;
}
cores.
{
return 0;
}
{
return -1;
}
{
}
{
{
}
{
}
__asm {
}
}
{
}
CPUID.
If there is need to distinguish between PACKAGE_ ID and CLUSTER_ID, PACKAGE_ID can be extracted

CPUID.
}
//system.
}
}
}
}
The PAUSE instruction can improves the performance of pr ocessors supporting Intel Hyper-Threading Technology

try {
_asm {
}
monitor)
MWAIT. 
processors, chipsets, and the BIOS is required (system coherence line size may depend on the chipset used in the system; the size could be different from the processor’s moni tor triggering area). The BIOS is responsible to set the

Get_Lock:
Continue:
WHILE (1) {
ELSE {
}
}
HLT
}
WHILE (1) {
ELSE {
MWAIT}
}
}
{S T I
HLT
}
reason, halting idle logical processors optimizes the performance.1 If all logical processors within a physical 
WHILE (1) {
ELSE {
}
}
STI
1. Excessive transitions into  and out of the HALT state could also incur perfor mance penalties. Operatin g systems should evaluat e the 
}
}
able:
supported). In processors based on Intel NetBurst microa rchitecture (which support 128-byte sector consisting of

able:
AP).
APIC ID). 
(Hex)
(000)10
NOTE:
APIC Bus
•The MP initialization protocol will be executed by processors even if they fail their BIST sequences.9-58 Vol. 3AMULTIPLE-PROCESSOR MANAGEMENTIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1311.Updates to Chapter 12, Volume 3A

Change bars and violet  text show changes to  Chapter 12 of the Intel® 64 and IA-32 Architectures Software 
• Updates to Section 12.11.8, “MTRR Considerations in  MP Systems,” and Section 12.12.4, “Programming the 
PAT.” Vol. 3A 12-1CHAPTER 12
Data Cache
Memory
Data Cache
Cache
line size.

entries).
NOTES:
When operating in an MP system, IA-32 processors (beginni ng with the Intel486 processor) and Intel 64 processors

NOTE
Processor
The size and structure of the WC buffer is not architectu rally defined. For the Intel Core 2 Duo, Intel Atom, Intel

tures. 
and various bits within control registers and page- and directory-table entries that control the caching system

program.
caching
C
DCR3
W
T
C
DCR0
N
W
C
DP
W
TG1CR4
G
E
pages
A
T
Yes
YesYes
Yes
Yes
Yes
YesYes
Yes
YesYes
Yes
Yes
Yes
YesYes
Yes
Yes
Yes
Yes
YesYes
Yes
Yes
YesYes
Yes
Yes
Yes
YesYes
Yes
Yes
Yes
Yes
NoYes
Yes
Yes
Yes
NOTES:
NOTES
caching used in specific regions of physical memory . Any of the caching types described in Section 12.3,

rules:
UC X X UC
WC 0 0 WC
0 1 WC
1 0 WC
11 U C
WT 0 X WT
1X U C
WP 0 0 WP
0 1 WP
1 0 WC
11 U C
WB 0 0 WB
01 W T1X U C
NOTE:
UC UC UC1
UC- UC1
WC WC
WT UC1
WB UC1
WP UC1
WC UC UC2
UC- WC
WC WC
WT UC2,3
WB WC
WP UC2,3
WT UC UC2
UC- UC2
WC WC
WT WT
WB WT
WP WP3
WB UC UC2
UC- UC2
WC WC
WT WT
WB WB
below.
NOTES
2
UC- WC3
WC WC
WT WT3
WB WP
WP WP
NOTES: 

2
UC- WC3
WC WC
WT WT3
WB WP
WP WP
NOTES: 
levels.
shared).

PAE flag.
NOTE
NOTE:
7FFFFH
256 KBytes

NOTE:
7FFFFH
256 KBytes
clear.
values. 
ReservedW
C7 1011
VCNTF
I
X89
register.
register.
ReservedF
E7 1011
Type89 12
E
9C000
BC000
C7000
CF000
D7000
DF000
E7000
EF000
F7000
FF000

D7000
DF000
E7000
EF000
F7000
FF000
NOTE
63 0
63 0
Reserved
supports 36-bit physical address size, then bit PhysMask consists of bits 35:12, and
bits 63:36 are reserved.12-26 Vol. 3AMEMORY CACHE CONTROL
follows:
63 0
63 0
Type31
tics:

rules:
boundary.
MTRRs:
is used.
used.
is used.
THEN
FI;
ROF;
FI;
returned.
THEN
FI;
is not 0.
THEN
FI;
THEN
FI;
FI;
BEGIN
FI;
END
BEGIN
END
partially valid MTRR setup. The algorithm disables caching by setting the CD flag and clearing the NW flag in control

FI;
BEGIN
FI;
END
BEGIN
END
CPUID.01H:EDX.SS[bit 27] as 1) , this step may be  unnecessary. However, if there are changes for which self-
6. If either  the PGE or PCIDE  flag is set in control register CR4, flush all TLBs by clearing one or both of these flags.
7. If the PGE and PCIDE flags are  both clear in control register CR4, flush all TLBs by executing a MOV from control 
13.Restore the values of the  PGE and/or PCIDE flags  in control register CR4, if cleared in Step 6 (above).

NOTE:
ated.
tains the consistency of the processor caches and translation lookaside buffers (TLB) . It requires the OS to invali-
require flushing of the processor caches in certain situations . This can be  accomplished in various ways, including 
the sequence below or  by following the procedure specified in Se ction 12.11.8, “MTRR Considerations in MP 
Systems.” (See Section 4.10.4, “Invalidation of TLBs and Pa ging-Structure Caches” for additional background 
information.)  Also note that in a multi-processor environment, it  is the software's responsibility to resolve differ-
000 P A T 0
001 P A T 1
100 P A T 4
101 P A T 5
110 P A T 6
111 P A T 7
PAT2 UC-
PAT5 WT
1.If the PCIDE or PGE flag is set in CR4, flush TLBs by clearing one of those flags (then restore the flag via a 
2.In the case that there are changes to memory-type mapp ings for which cache self-snooping behavior would be 
present.
the PAT.Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1312.Updates to Chapter 16, Volume 3B
Change bars and violet  text show changes to  Chapter 16 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3B: System Programming Guide, Part 2.
• Updated Section 16.3.1.2, “IA32_MCG_STATUS MSR,” to clarify that writing to an y of the IA32_MCG_STATUS 
MSR's reserved bits with a value other than 0 would result in #GP. Previously, the word “reserved” was not 
specified here.
• Updated Section 16.3.2.2.1, “Overwrite Rules for Machine Check Overflow,” to clarify that the overwrite rules 
are not limited to cache events.Vol. 3B 16-1CHAPTER 16

errors:
63 063
0
63 063
0
63 063
0 63
0 63
Where:
Count
Where:
set will cause the processor to enter a shutdown state. For information on processor behavior in the shutdown

Where:
E
I
PVM
C
I
PR
I
PV
RIPV—Restart IP valid flagLMCE_S—Local machine c heck exception signaledVol. 3B 16-5MACHINE-CHECK ARCHITECTURE
where
Reserved1
LMCE_EN - system software c ontrol to enable/disable LMCE16-6 Vol. 3BMACHINE-CHECK ARCHITECTURE
NOTE
NOTE
Where:
E
E
01E
E
0
2E
E
0
0EE
61E
E
62E
E

P
CA E
V
A
LO
V
E
Count
*** When IA32_MCG_CAP[11] or IA32_MCG_CAP[24] are not set, these bits are reserved, or
* When IA32_MCG_CAP[25] (MCG_EMC_P) is set, bit 37 is not part of “Other Information”.Firmware updated error status indicator (37)*16-8 Vol. 3BMACHINE-CHECK ARCHITECTURE
from an earlier event  – that is, what to do if the valid bit for an MC bank already is set to 1. When more than one 
structure posts events in a given bank, these rules specif y whether a new event will overwrite a previous posting or 
recoverable error address in IA32_MCi_ADDR should be ignored.

basis. 
NOTES:

ELSE
FI
FI;
THEN
FI
THEN
ELSE 
FI;
THEN
FI; AR 
FI; UC
FI; VAL 
THEN
FI;
THEN
THEN
THEN
FI;
THEN
FI;
OD;
THEN
DO
THEN
THEN 
ELSE 
THEN
FI;
FI;
FI;
THEN
FI;
THEN
CONTINUE:
OD;
FI;Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1313.Updates to Chapter 19, Volume 3B
Change bars and violet  text show changes to  Chapter 19 of the Intel® 64 and IA-32 Architectures Software 
• Updated four references to the Last Branch Records In formation Leaf (1CH) to remove “ECX = 0” since this 
leaf does not support sub-leaves.Vol. 3B 19-1CHAPTER 19
NOTE
records that are available is indicated in CPUID.1CH:EAX[7:0] . The number of LBR records available varies across 
CPUID.1CH:EAX[7:0] .
mation.
in CPUID.1CH:EAX[7:0] .

NOTES:
all zeros.
base address, while LIP includes the CS base address. Which IP type is used is indicated in CPUID.1CH:EAX[bit 31] .
19-3.
0000B COND

VM exits.
19.2 MSRS
MSRs.
behavior.
03FH.19-8 Vol. 3BLAST BRANCH RECORDSIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1314.Updates to Chapter 23, Volume 3B
Change bars and violet  text show changes to  Chapter 23 of the Intel® 64 and IA-32 Architectures Software 
• Corrected information in Sect ion 23.18.9, “Obsolete Instructions and Undefined Opcodes.”
• Corrected the “device not available” exception called out in Section 23.20.2, “Intel486 SX Processor and Intel 
487 SX Math Coprocessor Initialization.” Previously, this  exception was listed as #NH in the documentation. 
The correct exception is #NM.Vol. 3B 23-1CHAPTER 23
Signature Values of DisplayFamily_DisplayModel” in Chap ter 2, “Model-Specific Registers (MSRs),” of the Intel®

sions.

see Note 1
•FPREM1.
NOTES:
mode)
PUSH BP
register by the PUSHF instruction, by interrupts, and by exceptions is different with the 32-bit IA-32 processors

PUSH BP
ation.
always examine the value in the register, not the value in its tag. The FSTENV, FSAVE, and FXSAVE (Pentium III 
exception (#I) is generated only upon encountering a SN aN, except for the FCOM, FIST, and FBSTP instructions,

® 64 and 
bit x87 FPUs continues to execute in cases where the 16-bit IA-32 math coprocessors trap. The reason for this

tion.
•DDC8H  through DDCFH  - Behaves the same as FXCH, D9C8H through D9CFH.
stack POP.
Intel
reset. 
Upon hardware reset or execution of the FINIT/FNINIT inst ruction, the Intel 387 math coprocessor signals an error

reset. 
fninit
This initialization will cause any floating-point instru ction to generate a device not available exception ( #NM), inter-
EM 1 0
MP 0 1
ignore TS.
test TS.
ignore TS.
switches.
and DR5”).
Paging”).
The CD and NW flags in control register CR0 were introd uced in the Intel486 processor. In the P6 family and

Exception
Real
Exception
Real
ments.
FFFFH
Exception
Real
#MF1
NOTES:
ments.
FFFFH
Exception
Real
ments.
Exception
Real
NOTES:
ments.
2
Exception
Real

Exception
Real
jump instruction immediately after any write that modifies an instruction. The P6 family and Pentium processors, however, check whether a write may modify an instruction that has been prefetched for execution. This check is

I/O Map
NOTE
as 0s. 
If a call or interrupt is made from a 32-bit stack environm ent through a 16-bit gate, only 16 bits of the old ESP can

of 1 byte.
nating the possibility of reordering read cycles on th e Intel486 processor. The Pentium processor does check its

the Intel
counters.

lists all the events that can be counted for architectural perfor-
counters.
EAX 040404
   00000000H
   00000000H
   00000000H
Only—
    Undefined
    Undefined
NOTES: 
Register Pentium 4 Processor Pentium  Pro Processor Pentium Processor23-40 Vol. 3BARCHITECTURE COMPATIBILITYIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1415.Updates to Chapter 25, Volume 3C
Change bars and violet  text show changes to  Chapter 25 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 3C: System Programming Guide, Part 3.
• Updated Section 25.9.1, “Basic VM-Exit Information,” to  add bits 25 and 26 to the VMCS Exit Reason field.Vol. 3C 25-1CHAPTER 25
VMCS.
•The VMCS link pointer field in the current VMCS (see Sect ion 25.4.2) is itself the address of a VMCS. If VM entry

VMCS.
Clear
Active
Current
Launched
Active
Current
VMCLEAR X
CL
VMCLEAR X
Anything
dix A.1.
tecture).

dix A.1.
tecture).
control.
error.
Bit 

reasons.
4E n c l a v e  
NOTES:
Bit 
1
12 Enabled 
Bit 
NOTES:
Bit 

control.
VM exits.
controlsThis control determines whether the secondar y processor-based VM-execution controls are

VM exits.
controls.
20 Enable 
30.1.6.
execution of an I/O instruction causes a VM exit if any bit in the I/O bitmaps corresponding to a port it accesses is

control.
•Write bitmap for low MSRs (located at the MSR-bitmap address plus 2048) . This contains one bit for each

Bit 
NOTES:
26.5.7.2.

26.5.7.2.
Bit 
63:N1
NOTES:
Bit 
1
NOTES:
25.7.2.
VM exits. 
VM exit.
12 Load 
VM exit.
VM exit.
controls.
VM exits.

VM exits.
30 Save 
exit.
also 0.
NOTES:
25.8.3.
VM entry.1
18 Load 
NOTES:
fields:
—F o r  e x c e p t i o n s ,  t h e  deliver-error-code bit  (bit 11) determines whether delivery pushes an error code on

fields:
the stack.
— Bit 16 is always cleared to 0.
—Bit 25 is set to 1 if the “prematurely busy shadow st ack” VM-exit control is 1 and the VM exit caused a 
—Bit 26 is set to 1 if the VM exit occurred after assertio n of a bus lock while the “V MM bus-lock detection” VM-
•Exit qualification  (64 bits; 32 bits on processors that do not support Intel 64 architecture). This field contains
additional information about the cause of VM exits due to the following: debug exceptions; page-fault
exceptions; start-up IPIs (SIPIs); task switches; IN VEPT; INVLPG;INVVPID; LGDT; LIDT; LLDT; LTR; SGDT;
1. Software can discover whether these fields can be written by reading the VMX capability MSR IA32_VMX_MISC (see Appendix A.6) .Table 25-18.  Format of Exit Reason
16 Always cleared to 0.
24:17 Not currently defined.
25 A VM exit saves this bit as 1 to indicate  that  the VM exit caused a shadow  stack to become prematurely busy.
28 Pending MTF VM exit.
29 VM exit from VMX root operation.
1: Not used
ation:

ation:
1: Not used
31 Valid
9:1 Index
0: control
0: 16-bit
1: 64-bit
2: 32-bit
•Access type. Bit 0 must be 0 for all fields except for 64-bit fields (those with field-width 1; see above). A

ignored.
VMCS.
2. If IA32_VMX_BASIC[48] is read as 1, the VMXON pointer mu st not set any bits in the ra nge 63:32; see Appendix A.1.25-34 Vol. 3CVIRTUAL MACHINE CONTROL STRUCTURESIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1416.Updates to Chapter 27, Volume 3C
Change bars and violet  text show changes to  Chapter 27 of the Intel® 64 and IA-32 Architectures Software 
• Added information regarding user interrupts to Sectio n 27.3.21, “Loading Guest Control Registers, Debug 
Registers, and MSRs.” Vol. 3C 27-1CHAPTER 27
VM ENTRIES
2. The control and host-state areas of the VMCS are checke d to ensure that they are proper for supporting VMX

VM ENTRIES
ways:
numbers.

30.1.1).
checks:
must be 0.
width.
1
0000H.
non-zero:

non-zero:
A.1.
non-zero:
A.1.
hold:
non-zero:
A.1.
must be 0.
set.
be 0.
must hold:

must hold:
address.
cleared.
must be 0.
6
set.
register.
1

register.
1
control:
•SS.
0.1
TSS).
•RFLAGS.
is not 0.2

NOTE
must be 0.
27.3.1).

—If the “load UINV” VM-entry control is 1, UINV is load ed with the low 8 bits of the UINV field. UINV is 
•CS.

1 
(such as the exception bitmap) that would cause a VM exit if the event had occurred in VMX non-root operation. In contrast, a ne sted

VM exits.

VM exits.
VM entry.
VM entry.

27.3.1.
27.4).

option is used only if VM entry is able to load all guest state.Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1417.Updates to Chapter 28, Volume 3C
Change bars and violet  text show changes to  Chapter 28 of the Intel® 64 and IA-32 Architectures Software 
• Updated the information regarding the TPAUSE and UMWAIT  instructions in Section 28.2.5, “Information for 
VM Exits Due to Instruction Execution,” including addi ng Table 28-13, “Format of the VM-Exit Instruction-
Information Field as Used for TPAUSE and UMWAIT.” Vol. 3C 28-1CHAPTER 28
VM EXITS
pending.

MOV SS.
FIELDS

NOTES:
1
0=  M O V  t o  C R
1 = memory
0=  R A X
1=  R C X
4=  R S P
7=  R D I

0=  M O V  t o  C R
1 = memory
0=  R A X
1=  R C X
4=  R S P
7=  R D I
0 = RAX
1=  R C X
2=  R D X
5=  R B P
0=  1 - b y t e
The guest linear-address field is valid for all EPT violatio ns except those resulting fr om an attempt to load the

address.
NOTES:
below).
— For VM exits that set both bit 31 (valid) and bit 11 (err or code valid) in the VM-exit interruption-information

IRET.
3 for n.
normally.
— For VM exits due to attempts to effect a task swit ch via instruction executio n. These are VM exits that

1
—For VM exits due to attempts to execute TPAUSE or  UMWAIT, the field has the format is given in 
0: 16-bit
1: 32-bit
0: ES
1: CS2: SS
3: DS
4: FS
5: GS
0: 16-bit
1: 32-bit
0: ES
1: CS
2: SS3: DS
4: FS
5: GS
0=  R A X
3=  R B X
6=  R S I
0: 16-bit
1: 32-bit
0: 16-bit
1: 32-bit
0: ES
1: CS2: SS
3: DS
4: FS5: GS
0=  R A X
1=  R C X
2=  R D X
5=  R B P
0: SGDT
6:3 Reg1:
0=  R A X
1=  R C X
2=  R D X
5=  R B P
0: 16-bit
1: 32-bit
0: ES
1: CS2: SS
3: DS
4: FS5: GS

0: ES
1: CS2: SS
3: DS
4: FS5: GS
0: SLDT
3: LTR
2:0 Undefined.6:3 Operand register (destination register ):
0=  R A X
3=  R B X
6=  R S I
0: 16-bit
2:0 Undefined.6:3 Operand register (source register):
0=  R A X
3=  R B X
6=  R S I
 
0: 16-bit
1: 32-bit
0: ES
1: CS2: SS
3: DS
4: FS5: GS
0=  R A X
1=  R C X
2=  R D X
5=  R B P
0=  R A X
1=  R C X
4=  R S P
5=  R B P
6=  R S I
0: 16-bit
1: 32-bit
0: ES
1: CS
2: SS3: DS
4: FS
5: GS
field.
—C S .
—S S .
unusable.

—C S .
—S S .
unusable.
16 bits.
mode.
“SPP-related event.” When due to TAPT or PEBS, thes e VM exits (with the exception of those due to EPT

28.7.

28.7.
1
always 0.
•D/B.
•G.
PDPTEs.

PDPTEs.
MSR).
1

and with UIRR ≠ 0; otherwise, no pending us er interrupt is recognized.Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1418.Updates to Chapter 32, Volume 3C
Change bars and violet  text show changes to  Chapter 32 of the Intel® 64 and IA-32 Architectures Software 
• Updated the information regarding CR4 in  Section 32.15.6.5, “Loading Host State,” to add that LA57 is cleared 
in addition to MCE, PGE, CET, and PCIDE. Vol. 3C 32-1CHAPTER 32
NOTES
and SMM.”
SMM.
NOTES
MODES

in SMM.
NOTE
32.4 SMRAM
save area.
 
Offset 
1No
NOTE:

1No
NOTE:
them.
NOTES
Offset 
1No
NOTE:
Offset 
first. 
NOTES

General-purpose registers UndefinedEFLAGS 00000002H
behavior. 
below.

below.
•001 – Byte
•010 – Word
31 0
IN DX 0001
ture.
INS 0011
OUTS 0010
7EFCH
31 0
0
0
110
1
If the I/O instruction restart field contains the value 00H when the RSM instruction is executed, then the processor

7EF8H
0 15
00H
00H00H
enter SMM;
THEN
THEN
FI;
1
saved)
THEN
1
THEN

saved)
THEN
1
THEN
FI;
FI;
32.15.5).
follow.

0=  1 - b y t e
1=  2 - b y t e
3=  4 - b y t e
VMCS:
checks:
•If the executive-VMCS pointer field does not contain the VMXON pointer (the VM entry enters VMX non-root

VM entry.
fiers. These identifiers enable software to avoid us ing an MSEG header formatted for one processor on a

code. 
end in SMM.
header.
ignored).
•CR4 is set as follows:—M C E ,  P G E ,  C E T ,  P C I D E , and LA57  are cleared.
•GDTR.base is set to the sum of the MSEG base addre ss and the GDTR base-offset field in the MSEG header

4.
(MSRs),” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4.Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 2119.Updates to Chapter 1, Volume 4
Developer’s Manual, Volume 4: Model-Specific Registers.
the list of supported processors in Section 1.1, “I ntel® 64 and IA-32 Processors Covered in this Manual.”Vol. 4 1-1CHAPTER 1
253665).

253665).
sors.
include: 

NOTE
28
24
20
1612
8
40Address
where:
E, and F.
arise.
register:
DS:FF79H

See also: 
tions.pdf
http://www.intel.com/technology/platform-technology/hyper-threading/index.htmIntel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 1320.Updates to Chapter 2, Volume 4
•C h a p t e r  1 :  
— Added the 5th generation Intel® Xeon® Scalable Processor Family and the Intel® Core™ Ultra 7 processor 
to the list of supported processors in Section 1.1, “Intel® 64 and IA-32 Processors Covered in this Manual.”
•C h a p t e r  2 :
to Table 2-1, “CPUID Signature Values of DisplayFamily_DisplayModel.”
— Added the following architectural MSRs: 
• IA32_FEATURE_ACTIVATION (7AH)• IA32_MC29_CTL (474H)
• IA32_MC29_STATUS (475H)
• IA32_MC29_ADDR (476H)• IA32_MC29_MISC (477H)
• IA32_MC30_CTL (478H)
• IA32_MC30_STATUS (479H)• IA32_MC30_ADDR (47AH)
• IA32_MC30_MISC (47BH)
• IA32_MC31_CTL (47CH)• IA32_MC31_STATUS (47DH)
• IA32_MC31_ADDR (47EH)
• IA32_MC31_MISC (47FH)•I A 3 2 _ T M E _ C L E A R _ S A V E D _ K E Y  ( 9 F B H )
— Updated the IA32_MCG_STATUS MSR (17AH) to show th e MSR is R/W, not R/W0 as previously indicated.
— Updated the IA32_TME_CAPABILITY MSR (981H) to add bit 30 details.— Added the 5th generation Intel
® Xeon® Scalable Processor Family and the Intel® Core™ Ultra 7 
processors to Section 2.17, “MSRs In the 6th-13th Generation Intel® Core™ Processors, 1st-5th 
Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation 
Intel® Core™ i3 Processors, and Intel® Xeon® E Processors.” 
— Added the 5th generation Intel® Xeon® Scalable Processor Family to Section 2.17.8, “MSRs Specific to the 
4th and 5th Generation Intel® Xeon® Scalable Processor Families.”
— Added Section 2.17.9, “MSRs Introduced in the Intel® Core™ Ultra 7 Processor Supporting Performance 
Hybrid Architecture.”
— Updated the layout of the MSR tables. No information was changed in the update.
— Removed MSR index.— Typo corrections as necessary. If the correction does  not change the meaning of the material, it is not 
marked with change bars or violet font.Vol. 4 2-1CHAPTER 2
NOTE

Series
series
06_0BHIntel Pentium III Xeon processor, Intel Pentium III processor
52 51 50
in GP(0).

in GP(0).
ECX[30] = 1
EBX[2] = 1
EBX[1] = 1
7P S F D
8 DDPD_U
1K L
= 1.
[10] = 1
[11] = 1
1

[10] = 1
[11] = 1
1
to C0.1.
(RDCL).
Mode. 
exists.
1.
default).
disabled.

default).
disabled.
bit is set.
is set.
present.
set.
Global Machine Check Status ( R/W)0 6 _ 0 1 H
0 RIPV. Restart IP valid. 06_01H1 EIPV. Error IP valid. 06_01H
When set, the fast-strings feature (for REP MOVS and REP STORS) is

EAX[4] = 1
EAX[4] = 1
= 1
63:0 TO_IP
62 IN_TSX

63:0 TO_IP
62 IN_TSX
63 MISPRED
11 Valid
are set.
2:0 PA0
18:16 PA2
42:40 PA5
30 CMCI_EN

See Section 18.19.4.1, “Enumeration and Detect ion Support of Cache Allocation Technology.”Table 2-2.  IA-32 Architectural MSRs (Contd.)
See Section 18.19.4.1, “Enumeration and Detection Support of Cache Allocation Technology.”
62 IN_TSX
63 MISPRED
0L O C K
0L B R E n
1O S
2U S R
16 COND
N:0 DEPTH
#GP.
63:0 TO_IP

010b: C2 
110b: C6
111b: C7 
See Section 15.10.4, “PP0 /PP1 RAPL Domains,” and 

0R I P V
1E I P V
2M C I P
16 USR
19 PC
22 EN
See Section 18.9.2, “Filtering  of Last Branch Records.”Core
0C P L _ E Q _ 0

2M C I P
See Section 18.9.2, “Filtering  of Last Branch Records.”Thread
0C P L _ E Q _ 0
1B T F

7:0 Count
Global Machine Check Status ( R/W) Thread
0R I P V
1E I P V
NOTES:

1ST—5TH  GENERATION INTEL® XEON® SC ALABLE PROCESSOR FAMILIES, 
INTEL® CORE™ ULTRA 7 PROCESSORS , 8TH GENERATION INTEL® CORE™ I3 
NOTES:

DB2H, and D90H. Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
Intel® Xeon® Scalable Processor Families,  Intel® Core™ Ultra 7 Processors,  8th Generation Intel® Core™ i3 Processors, 
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1PackageTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
setting.
enclave.
Register Address: 301H, 769 MSR_SGXOWNEREPOCH1Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
enclave.
5 Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). Thread6 Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). ThreadTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
62 Set 1 to cause Ovf_BufDSSAVE. ThreadTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
0L o c k
(ACMs).”

0L o c k
(ACMs).”
(ACMs).”
2O S
7C R 3 F i l t e rTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
8T o P A
9M T C E n
10 TSCEn
Region 0 End Address (R/W) ThreadTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
to Running Average Thermal Limit (RATL).Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
This log bit will remain  set until cleared by  software writing 0.Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
Register Address: 655H, 1621 MSR_PKG_HDC_SHAL LOW_RESIDENCYTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 

window specified by Power Limit #1 Time Window.Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
value. 
Register Address: 692H, 1682 MSR_LASTBRANCH_18_FROM_IPTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
See description of MSR_LASTBRANCH_0_FROM_IP.ThreadTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 

20:18 Reserved.Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
When set, frequency is reduced due to running average thermal limit. Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
25 Reserved.Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
See description of MSR_LASTBRANCH_0_TO_IP.ThreadTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 

41:32 Activity Window (R/W)42 Package Control (R/W)Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
Register Address: DC7H, 3527 MSR_LBR_INFO_7Table 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 
See description of MSR_LBR_INFO_0.ThreadTable 2-39.  Additional MSRs Supported by the 6t h—13th Generation Intel® Core™ Processors, 1st— 5th Generation 

10ns.
63LOCK:
2.17.8  MSRs Specific to the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
Signature DisplayFamily_Display Model value of 06_8FH) and the 5th generation Intel® Xeon® Scalable Processor 
06_CFH) both support the MSRs listed in Section 2.17, “MSRs In  the 6th—13th Generation Intel® Core™ Proces-
tables.
Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
(CPUID Signature DisplayFamily_Di splayModel Values of 06_8FH and 06_CFH )
Register Address: 105H, 261 MSR_CORE_BISTTable 2-52.  Additional MS Rs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
(CPUID Signature DisplayFamily_Di splayModel Values of 06_8FH and 06_CFH ) (Contd.)
(READ).
39:32 BANK
(WRITE).

63:6 Reserved.Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
memory.
minus 1.
0 means 1 core at a time.DieTable 2-52.  Additional MS Rs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
63 Valid
SCAN_STATUS (R/O)Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
Register Address: 2D9H, 729 MSR_INTEGRITY_CAPABILITIESTable 2-52.  Additional MS Rs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
Total energy consumption in J (32.0), in 10nsec units. Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families

value. 
This field has the same format as the POWER_LIMIT_1_TIME field.Table 2-52.  Additional MS Rs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
63 LOCK 
63 LOCK 
Register Address: 6A7H, 1703 IA32_PL3_SSPTable 2-52.  Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
Uncore B-box 1 perfmon event select MSR. PackageTable 2-52.  Additional MS Rs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
See Table 2-2.Table 2-52.  Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
2.17.9  MSRs Introduced in the Inte l® Core™ Ultra 7 Processor Su pporting Performance Hybrid 
Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
0L O C K

0L O C K
17:1 Reserved.Table 2-52.  Additional MS Rs Supported by the 4th and 5th Generation Intel® Xeon ® Scalable Processor Families
0011b: C6
0110b: C8
0011−C6.
Enable Un-Demotion from Demoted C3.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
BLE:
000b
Register Address: 140H, 320 MSR_FEATURE_ENABLESTable 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
31 LOCKED
cache line into L1 data cache.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
homeless.
LLC prefetch requests triggered by CRd.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
15 OTHER

15 OTHER
Near Memory, Remote 0-hop, DATA_PRE [6:3] = BTable 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
30 SPL_HIT
[2:0] = 0.
33 MISS
36 HITM
38 GO_ERR
WiL.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
WCiL.
WCiLF.
50 PSMI
51 ITOM
ItoM.
11:9 Reserved.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
13 LOCK
0 CDDIS
1E N _ G P R S
zero.
CDDIS is zero. EN_GPRS wi ll override this control,Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
11 VALID
45:20 MASK
1b: Use fast VID swing rate.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 

Memory type for PRMRR accesses.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
45:20 BASE
0L O C K
When set, locks this regi ster from further changes.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
31 LOCK
PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
Read Only.
Average Thermal Limit (RATL).Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
software writing 0.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 

Maximum turbo ratio limi t with 1 core active.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
Power Limit 1 value.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
equation: 
63 LOCK
RESET.
event.
reduced due to running average thermal limit.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
writing 0.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
writing 0.

writing 0.
event.
other constraints.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
writing 0.
bit will remain set until clea red by software writing 0.Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporting Performance Hybrid 
WRMSR.
Table 2-54.  MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core 
uops that do not reti re, or Recovery Bubbles (unutilized slots).Table 2-53.  Additional MSRs Supported by the Intel® Core™ Ul tra 7 Processors Supporti ng Performance Hybrid 
Table 2-55.  MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core 
indicates allocation to the way is not allowed.Table 2-54.  MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core  (Contd.)
3:0 CLOS
10 X
11 RW
63:12 LA

3:0 CLOS
10 X
11 RW
63:12 LA
Register Address: 0H, 0 IA32_P5_MC_ADDRTable 2-55.  MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core  (Contd.)
001b - C2
18 Edge.

NOTES
Section 20.6.9.3, “Events Counted.”2-510 Vol. 4MODEL-SPECIFIC REGISTERS (MSRS)  
 
White Paper  
 
AMD MEMORY ENCRYPTION  
October 18 , 2021 
David Kaplan , Jeremy Powell, Tom Woller    
DISCLAIMER  
The information contained herein is for informational purposes only, and is subject to change without notice. While every 
precaution has been taken in the preparation of this document, it may contain technical inaccuracies, omissions and 
typographical erro rs, and AMD is under no obligation to update or otherwise correct this information. Advanced Micro Devices, 
Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this document, 
and assumes no liability of any kind, including the implied warranties of noninfringement, merchantability or fitness for 
particular purposes, with respect to the operation or use of AMD hardware, software or other products described herein. No 
license, including implied or arisin g by estoppel, to any intellectual property rights is granted by this document. Terms and 
limitations applicable to the purchase or use of AMD’s products are as set forth in a signed agreement between the parties or  in 
AMD's Standard Terms and Conditions o f Sale.  
 
AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names 
used in this publication are for identification purposes only and may be trademarks of their respective companies.  
 
© 2021  Advanced Micro Devices, Inc. All rights reserved.  
    
 The need for practical security in modern computing systems is greater than ever.  The increase in 
system complexity, growth of the cloud, and advent of new technologies are all con tributing  to a computing 
environment that is difficult yet critical to protect.  AMD recognizes these serious challenges and has 
developed  new memory  encryption technologies that are designed to  address these needs across a variety of 
systems.   
 Secure Me mory Encryption (SME)  defin es a simple and  efficient  architectural capability for main 
memory encryption.  While memory encryption technologies have been used previously in various 
specialized products and industries, SME is a general purpose mechanism tha t is flexible, integrated into the 
CPU architecture , scalable from embedded to high -end server workloads , and requires no application 
software modifications . 
 Main memory encryption can be utilized to protect a system against a variety of attacks.  While data 
is typically encrypted today when stored on disk, it is stored in DRAM  in the clear .  This can leave the data 
vulnerable to snooping by unauthorized  administrators or software or by hardware probing.  New non -volatile 
memory technology (NVDIMM) exacerbates this problem since an NVDIMM chip can be physically removed 
from a system with the data intact, similar to a hard drive.  Without encryption any stored information  such  as 
sensitive data, passwords, or secret keys  can be easily compromised.  
 Secure Encrypted Virtualization (SEV)  integrates main memory encryption capabilities with the 
existing AMD -V virtualization architecture to support encrypted virtual machines.   Encrypt ing virtual machines 
can help  protect them not only from physical threats but also from other virtual machines  or even the 
hypervisor itself.  SEV thus represents a new virtualization security paradigm that  is particularly applicable to 
cloud computing where virtual machines need not fully trust the hypervisor and administrator of their host 
system.   As with SME, no application software modifications are required to support SEV.  
 This document present s a technical overview of the SME and SEV and describe s how they  can be 
utilized by operating system  (OS) , hypervisor  (HV) , and gue st virtual machine (VM)  software in a variety of 
different environments  to protect data in DRAM .       
SME Technical Overview  
 Main memory encryption is performed via dedicated 
hardware in the on-die memory controllers.  Each controller 
includes a high performance Advanced Encryption Standard 
(AES) engine that encrypts data  when it is writt en to DRAM, 
and decrypts  it when read as shown in Figure 1: Memory 
Encryption Behavior .  The encryption of data is done with a 
128-bit key in a  mode w hich utilizes an additional physical 
address -based tweak to protect against cipher -text block move 
attacks.  
The encryption key used by the AES engine with SME 
is randomly generated on each sy stem reset and is not visible 
to any software running on the CPU cores.  This key is managed 
entirely by the AMD Secure  Processor  (AMD -SP), a 32-bit 
microcontroller (ARM ® Cortex ®-A5) that functions as a 
dedicated security subsystem integrated within the AMD SOC .   The key is generated using the onboard NIST 
SP 800 -90 compliant hardware random number generator  and is  stored in dedicated hardware registers  where 
it is never exposed outside the SOC in the clear.  Unlike the SEV mode described later , SME does not require 
the software  running on the CPU cores to participate in key management.  
 The control over which pages of memory are encrypted is controlled  via the OS or HV in the software 
manag ed page tables .  After memory 
encryption is enabled, physical address bit 47 
(aka the C-bit, as in  enCrypted ) is utilized to 
mark if a memory page is protected .  The OS 
or HV sets  bit 47 of a physical address to 1 in 
the page table entry (PTE) to indicate the 
page should be encrypted, causing accesses 
to that memory to be automatically 
encrypted and decrypted by the AES engine 
in the memory controller.  
 The encryption and decryption of memory 
through the AES engine does incur  a small 
amount of additional latency for DRAM memory accesses.  The impact of this latency to software is very 
dependent on the system workload but  is estimated  to have a very small overall effect on system performance .  
If only a subset of memory is encrypted, the performance impact will be less as u nencrypted accesses generally

The control over which pages of memory are encrypted is controlled  via the OS or HV in the software 
If only a subset of memory is encrypted, the performance impact will be less as u nencrypted accesses generally 
incur no additional latency.  Figure 1: Memory Encryption Behavior  
Physical Address 0
Memory47 0Unencrypted
Physical Address 1
Memory47 0Encrypted
C-bit C-bit
Figure 2: Address Mapping  
CPU
AES Decrypt
AES EncryptDataPTE C-bitMemory Read
CPUDataPTE C-bitDRAM
DRAMMemory Write  
SME Use Models  
 This section discuss es two different example models by which software can utilize the SME feature.  In 
the first model, all of DRAM is encrypted while in the second, only a select region (corresponding to guest VMs) 
is encrypted.  
Full Memory Encryption  
 Full memory encryption is a simple yet compelli ng model for many computing systems, especially 
when physical attacks on the system are of concern, including  government data centers and/or  smaller or 
remote enterprise data centers that have more limited physical security.   With full memory encryption, a ll 
DRAM contents are encrypted utilizing the random key which provides strong protection against cold boot, 
DRAM interface snooping, and similar types of attacks.  For systems with NVDIMM, full memory encryption 
also provides protection against an attacker  removing a memory module and attempting to extract its 
contents.  
 Supporting full memory encryption with SME is accomplished  by either the OS or HV setting  the C -bit 
in all DRAM physical address es in all the page tables.  This should include both instruct ion and data pages, as 
well as the pages corresponding to the page tables themselves.  In essence, the OS or HV software may view 
the system as having DRAM that starts at address 0x8000_0000_0000.  In the case of a HV setting the C -bit to 
encrypt all physic al memory , all the VMs  controlled by the HV are encrypted along with the HV and use the 
same encryption key. 
 Note that DMA to memory encrypted via SME is supported.  From a device standpoint, an encrypted 
memory access is just a normal memory access with bit 47 set.  
Partial Memory Encryption  
 The use o f the C -bit in the page tables  provides the flexibility for the OS or HV to  selectively encrypt 
only a subset of memory if it desires.  Doing so still provides physical protection of the encrypted memory, bu t 
can also be used to improve performance on non -sensitive data.  In addition, the choice of encrypted vs. 
unencrypted memory can be used to provide a layer of isolation for critical workloads.     
 One example of this isolation would be a system 
which only marks memory used by guest VMs as 
encrypted.  This can be done without any modification 
to the guest VMs  whatsoever.  By setting the C -bit in all 
the nested  page table entries corresponding to DRAM  
(as shown in Figure 3: Encrypted VMs ), the hypervisor 
enables  encryption for the VM memory  only.  
 Such a scenario could be used to protect VMs 
against  a rogue machine administrator.  While the 
administrator would have access to the hardware and 
host system , they would not be able to inspect guest 
VM data even with memory scanning utilities.  
SME Special Considerations  
 SME provides a straightforward meth od for software to  encrypt some or all memory pages.  There are 
some important special programming considerations however that must be taken into account when working 
with encrypted memory.  
 The primary consideration is that hardware does not manage cohere ncy between encrypted and 
unencrypted copies the same page.  Therefore, software must be careful when modifying the C -bit of pages 
and ensure that i f the C -bit of a page needs to be modified, that page must be flushed from the CPU caches 
prior to the page table modification.  
 Worth noting is that it is allowed for  devices to issue DMA to encrypted memory but like with CPU 
accesses, they must set bit 47 of the physical address which is not possible on some 32 -bit legacy devices.  To 
compensate, software can utilize the IOMMU to re -map device request addresses to  addresses  with the C -bit 
set. 
 Additional technical details of the SME feature can be found in the latest copy of the AMD 
Programmer’s Manual (APM) volume 2.  
Transparent SME  
 While SME provides a lot of flexibility for managing main memory encryption, it does require support 
in the OS/ HV. Transparent SME (TSME) is an option for systems that desire to have the physical protection of 
SME decoupled from the OS/HV .  In TSME, all memory is encrypted regardless of the value of the C -bit on any 
particular page.  This mode provides a simple method to enable encryption without requiring software 
modifications.  
 TSME can be enabled via a BIOS setting on supported plat forms.  
DRAM
Encrypted DRAMHost Virtual Address Guest Virtual Address
Host Physical AddressGuest Physical Address
Host Physical Address 0C-bit
1C-bitFigure 3: Encrypted VMs    
Intro to SEV:  Complexity and Consolidation  
With advances in both hardware and software, computing systems today are more complex than 
ever.  The size and functionality of software, especially the most privileged kernel -level software responsible 
for security in the system, has increased dramatically.  The Linux kernel for instance has grown from less than 
200k lines of code to almost 22 million lines today.   
 This evolution has also led to more 
consolidation than ever before allowing 
systems to perform more tasks and do more 
work on the same hardware.  This 
consolidation has led to many positive results 
such as the cloud, and virtual data centers on 
which anyon e can buy affordable compute 
time.   
 Yet both complexity and consolidation 
have a generally negative effect on the security 
of a system.  Complex software is harder to verify and is more likely to have  bugs which hackers could exploit.  
A typical Linux system loads close to 5.5MB of kernel code into memory which must be bug -free to avoid 
compromising the system.  
Consolidated systems can also negatively impact security by increasing the attack surface, allowing 
many different pieces of software to use the same hardware and share resources like memory.  This 
combination yields a security model which relies on a large amount 
of privileged bug -free code, which coupled with a large attack 
surface provides an  increased possibility for intrusions.  
To counter these forces, Secure Encrypted Virtualization  is a 
new feature being added to the AMD architecture which is designed 
to better deal with the complexity and isolation needs of modern 
systems.  SEV enhances isolation through the use of cryptography, 
encrypting code and data and enables an entirely new security 
model where code can be cryptographically protected from higher 
privileged code such as a hypervis or. 
SEV Security Model  
 Traditional computing  systems have operated using a ring -based security model.  In this model, high 
privilege code has full access to the resources at its level and of all lower privileged levels.   Figure 4: Kernel Code Size  
Program 
code/data
SEV security 
layer
Existing CPU 
security 
layer
Figure 5: Security Layers  05101520Lines of code 
(Millionis)
VersionLinux Kernel lines of code  
In the SEV model, code executing at different levels (namely 
hypervisor  vs guest) is isolated so neither has access to the 
resources of the other.  Even though the hypervisor level is 
traditionally “more privileged” than the guest level, SEV 
separates these levels through cryptographic isolation.  This 
provides additional security for lower privileged code, 
without requiring tr ust in the high privileged code on which 
the less privileged code is dependent upon for startup and 
execution.  Communication between hypervisor and guest is 
still possible, but those communication paths are tightly controlled.  
Consequently, SEV technology  is built around a threat model where an attacker is assumed to have 
access to not only execute user level privileged code on the target machine, but can potentially execute 
malware at the higher privileged hypervisor level as well.  The attacker may also have physical access to the 
machine including to the DRAM chips themselves.  In all these cases, SEV provides additional assurances to 
help protect the guest virtual machine code and data from the attacker.  Note that SEV does not protect 
against denial -of-service attacks  against the guest . 
SEV Use Cases  
 Built around the concept of hardware VMs , SEV can be used to enhance security in a variety of use 
cases.  Due to its use of main memory encryption, SEV provides the all of the same security benefits as SME  
for physical attack protection  described earlier .  In addition, SEV can be used to protect  environments such as 
the following.  
Cloud  
 The growth of the cloud and in particular Infrastructure as a Service (IaaS) 
data centers has made computational power both cheap and affordable.  This 
growth does not come without security challenges however, as cloud 
infrastructure/personnel m ay not always be trustworthy.  This can be

Cloud  
infrastructure/personnel m ay not always be trustworthy.  This can be 
particularly true when dealing with sensitive data, such as health records or 
trade secrets.  Furthermore, the sharing of hardware amongst multiple 
customers can raise security concerns for owners of many types of  workloads.  
Despite the best efforts of software designers, there have been many 
examples of cases where this isolation has failed, leading to the compromise of 
sensitive code or data.   
 SEV can be used to increase the level of security in these IaaS clou ds by providing better security 
isolation, rooted in the hardware itself.  While existing security technologies like Microsoft’s BitLocker ® and 
LUKS can protect data -at-rest in hard drives, SEV protects data -in-use enabling customer workloads to be 
protect ed cryptographically from each other as well as protected from the hosting software.  Even a n 
Guest Guest HypervisorTraditional 
ModelAMD SEV 
Model
CloudEncrypted 
VM
Encrypted 
VMHosting 
SoftwareFigure 6: SEV Security Model  
Figure 7: Encrypted VMs in the 
Cloud   
administrator with malicious intentions  at a cloud data center would not be able to access the data in a 
hosted VM. 
Sandboxing  
 Through the use of the hardware VM constructs, SEV is 
built ar ound an idea of secure sandbox environments where 
software can  execute and is protected from all other software on 
the system.  The se sandboxes can be as big as a  full VM with its 
own disk and OS, but they can also be small and used for more fine -
grained isolation.  For example, SEV hardware could be used to 
cryptographically isolate Docker containers from the host system to 
better protect confidential data.   
SEV Architecture  
Technical Overview  
 SEV is an extension to the AMD -V architecture which supports running 
multiple VMs  under  the control of  a hypervisor.  When enabled, SEV hardware tags 
all code and d ata with its VM ASID which indicates  which VM the data originated 
from or is intended for.  This tag is kept with the data at all times when inside the 
SOC, and prevents that data from being used by anyone other than the owner.  
 While the tag protects VM data inside the SOC, AES with 128 bit encryption 
protects data outside the SOC.  When data leaves or enters  the SOC, it is 
encrypted /decrypted  respectively by hardware with a key based on the associated 
tag. 
 Each VM as well as the hypervisor is associated with a tag, and consequently 
an associated encryption key.  Because of the tag and memory encr yption, data is 
restricted to only the VM using that tag .  If that data is accessed by anyone else, including the hypervisor, 
they will only be able to see the data in its encrypted form.  This provides strong cryptographic isolation 
between the VMs, as well as between the VMs and the hypervisor.   
Encrypted Me mory  
 SEV uses the same high performance memory encryption engine as the SME feature described 
earlier.  It also uses the same C -bit in the page tables to mark pages as encrypted, although with some 
additional restrictions.  
 One of the key features of SEV is that guest VMs  are able to choose which data memory pages they 
would like to be private .  This choice is done using the standard CPU page tables, and is fully controlled by the 
guest.  Private memory is encrypted with the guest -specific key, while share d memory may be encrypted with 
the hypervisor key.  This feature allows VMs  to mark selected pages of memory data they want to keep 
AMD SEV Sandboxing
App A App C App B
Figure 8: Sandboxing  
Figure 9: SEV Architecture    
confidential  (private), and others to be used for communication with other VMs 
or the hypervisor.  In a typical arrangement,  the guest would map all  of its code 
and data as private , except for specific shared pages that it chooses  to expose .  
For security, SEV hardware does require certain types of memory (includi ng 
instruction pages and page tables) to always be private to protect the VM.    
 An example communication configuration is shown in  Figure 10.  In this 
example, the SEV -enabled guest and hypervisor communicate through memory 
that both entities mark as shared .  All other guest memory is encrypted with 
the guest’s key (which the HV c annot use).  Any memory the HV does not use 
for direct guest communication is encrypted using the SME feature described 
earlier.  
Key Management  
 The security of SEV is highly dependent o n the security of the memory 
encryption keys.  Exposure to malicious entities, such as a malicious or buggy 
hypervisor, can endanger the SEV protected guest.  While the hypervisor must 
manage the guest and its resources, the hypervisor must never gain knowle dge of the memory encryption 
keys themselves. The SEV  firmware that runs within the AMD -SP provides a secure  key management 
interface to accomplish this.  The hypervisor uses this interface to  enable SEV for secure guests and perform 
common hypervisor activ ities such as launching, running, snapshotting, migrating, and debugging a guest.  
To protect SEV enabled guests, the firmware  assists in the enforcement of  three main security 
properties:  authenticity of the platform, a ttestation of a launched guest , and the c onfidentiality of the guest’s 
data . 
Authenticating the platform prevents malicious software or a 
rogue device from masquerading as a legitimate platform. The authenticity  
of the platform is proven with its identity key. This key is signed by AMD to 
demonstrate that the platform is an authent ic AMD platform with SEV 
capabilities. It is also signed by the owner of the platform to show  who 
administers  and owns  the machine  to the owners of guests or to other 
instances of the firmware on remote platforms .  
Attestation of the guest launch proves to  guest owners that their 
guests securely launched with SEV enabled. A signature of various components  of the SEV related guest 
state —including  initial contents of  memory —is provided by the firmware to the guest owner to verify that 
the guest is in the expe cted state. With this attestation, a guest owner can ensure  that the hypervisor  did not 
interfere with the initialization of SEV  before transmitting confidential information to the guest . 
An example of this process is shown in Figure 12.  Initially, the guest owner provides the guest image 
to the cloud system.  The SEV firmware assists in launching the guest and provides a measurement back to 
Guest
Memory
(Private)Page Tables
(Private)Data Memory 
(Private)
Data Memory 
(Shared)
HV
Memory
(SME Encrypted)Memory 
(Shared)Figure 10: Guest/HV 
Communication Example  
Figure 11: Authenticating the Firmware  
SEV Firmware
Identity 
KeyAMD
Platform 
Owner  
the guest owner.  If the guest owner deems this 
measurement correct, they in turn provide additional secrets 
(such as a disk decryption key) to the running guest allowing 
it to proceed with start -up. 
Confidentiality of the guest is accomplished by 
encrypting memory with a memory encryption key that only 
the SEV firmware knows. The SEV management interface 
does not allow the memory encryption key —or any o ther 
secret SEV state —to be exported outside of the firmware without  properly  authenticating the recipient.  This 
prevents the hypervisor from gaining access to the keys and consequently the guest’s data.  
The interface also provides a mechanism to migrate the guest data to another SEV capable platform. 
During this operation, the guest’s memory contents remains encrypted during transmiss ion. Once the remote 
platform is authenticated, the SEV firmware sends the guest’s memory encryption keys securely so the 
remote platform can run the guest itself.  This transport mechanism allows a hypervisor to implement 
migration and snapshot functions securely with SEV enabled.  
SEV Software Implications  
Hypervisor  
As with traditional virtualization , SEV continues to rely o n the hypervisor for many VM functions such 
as device emulation  and scheduling , but reduces the reliance on the hypervisor for security.  A guest running 
with SEV enabled still uses the hypervisor as needed, but is able to protect itself by marking memory pages as 
private when they are not intended to be shared outside the VM.  
 During runtime t he hypervis or communicates with the AMD -SP in order to coordinate the 
management of memory encryption keys.  This communication is done via the AMD -SP driver and invo lves 
tasks such as  informing the AMD -SP when a VM is about to be run, thus allowing the AMD -SP to load the 
appropriate encryption key into the AES -128 encryption engine.  The hypervisor also communicates with the 
AMD -SP to establish a secure mechanism to perform guest attestation , perform migration, etc.  
 Although the hypervisor has control over the ASID used to run a VM and select the encryption key, 
this is not considered a security  concern  since  a loaded encryption key is meaningless unless the guest was

this is not considered a security  concern  since  a loaded encryption key is meaningless unless the guest was  
already encrypted with that key.  If the incorrect key is ever loaded  or the wrong ASID is used for a guest , the 
first instruction fetch of that guest will fail as memory will be decrypted with the wrong key, causing junk 
data to be executed (and very lik ely causing a fault).  
Guest  
 The OS in an SEV -enabled guest must be aware of this new hardware feature and configure its page 
tables appropriately.  This may be done in a similar method as the SME full memory encryption mode where 
most DRAM addresses are c onfigured to have the C -bit (bit 47) set to 1.  Figure 12: Guest Attestation  Example  
3. MeasurementGuest 
Owner
Guest4. Disk Decryption KeySEV 
Firmware1. Guest Image
2. Launch  
 One important consideration  for an SEV -enabled guest is that DMA into guest encrypted memory is 
not allowed by the SEV hardware for security reasons.  All DMA, whether from a real hardware or a HV 
emulated de vice, must occur to shared guest memory.  The guest OS can therefore choose to allocate 
memory pages for DMA  as shared (C-bit clear) , or may copy data to/from a special buffer (aka “bounce 
buffer”) for DMA purposes.  Some operating system s have existing su pport for bounce buffers which may be 
used for this purpose, such as the swiotlb Linux functionality.  
 Finally, it should be noted that multi -core guests are supported with SEV  and data can be shared 
amongst those cores with no additional performance penal ty.  The hypervisor  must simply use the same ASID 
for all virtual CPU instances  for a particular guest . 
SEV Special Considerations  
 Many of the special considerations listed earlier regarding SME functionality also apply to SEV.  In 
particular, a s with SME, a page must be flushed from the cache prior to accessing it with a different C -bit.  
Also,  prior to replacing a hardware memory en cryption key, the hypervisor  software must perform a full 
cache flush to ensure any modified data using that key has been written back to DRAM.  
 Finally, since the C -bit is only controllable by the guest OS when operating in 64 -bit or 32 -bit PAE 
mode, in a ll other modes the SEV hardware forces the C -bit to a 1.  This allows a guest OS to start running 
encrypted code immediately and then transition into its final mode securely.  
Conclusion  
 The two memory encryption featu res presented in this document  represe nt major steps forward in 
general purpose computer security that may be utilized in a variety of environments.  
The Secure Memory Encryption technology is a flexible yet powerful  architectural feature which allows 
for main memory encryption for an operating  system or hypervisor .  This document has explained a few specific 
use models for memory encryption, including full memory encryption , selective  encryption , and transparent 
encryption .  All models provide new  protection s against physical hardware attacks, and can in some cases  be 
used to help protect systems from rogue administrators.  Other use models are likely possible as well and can 
provide additional options and performance/security tradeoffs.   No application software changes are required 
for SME, and  with the appropriate operating system or hypervisor modifications, all applications in a system 
can be protected.  
Additionally, VM security can be enhanced with Secure Encrypted Virtualization, which supports 
running encrypted guests that a hypervisor can not directly access.  This provides new protections not only for 
cloud users but also for cloud hosters who wish to limit their visibility into customer data.  Based on AMD -V 
technology, SEV can be used in both cloud and Docker -type models and provides a n ew security model for 
virtualiz ed environments.  Like the SME technology, no application software changes are required to guest VMs  
and VMs  encryption is performed  quickly and transparently with dedicated hardware engines.   
  
Device Attestation Model in 
Confidential Computing 
Environment  
 
February  202 3 
 
 Disclaimers    
2        Document Number:  351998 -003    
 
Disclaimers  
future product. Contact your Intel representative to obtain the latest Intel p roduct specifications and 
roadmaps.  
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You may not use or facilitate the use of this docu ment in connection with any infringement or other 
This document contains in formation on products, services and/or processes in development. All 
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Corporation or its subsidiaries.  Other names and brands might be claimed as the property of others.  
 
 Table  of Contents    
3        Document Number:  351998 -003    
Overview  ................................ ................................ ................................ ................................ ................................ ............  5 
1     General Attestation Model  ................................ ................................ ................................ ................................ . 7 
2     Device Attestation  ................................ ................................ ................................ ................................ .................  9 
Device Evidence and Evidence Reporting  ................................ ................................ ................................ .... 10 
Device Referenc e Integrity Manifest (RIM)  ................................ ................................ ................................ ... 11 
Device Appraisal Policy  ................................ ................................ ................................ ................................ ........ 12 
Device Identification and Authentication  ................................ ................................ ................................ ..... 13 
PSK Based Authentication  ................................ ................................ ................................ ................................ .. 14 
Device Local Attestation Flow  ................................ ................................ ................................ ...........................  15 
Device Remote Attestation Flow  ................................ ................................ ................................ ......................  17 
Background Check Model  ................................ ................................ ................................ ..............................  17 
Passport Model  ................................ ................................ ................................ ................................ ...................  19 
3     TVM Remote Attestation  ................................ ................................ ................................ ................................ . 21 
TVM Remote Attestation with Device Local Attestation  ................................ ................................ ........ 21 
TVM Remote Attestation with Device Remote Attestation  ................................ ................................ ... 22 
4     Device Mutual Attestation  ................................ ................................ ................................ ...............................  23 
Mutual Authentication in Secure Session ................................ ................................ ................................ ..... 23

Mutual Authentication in Secure Session ................................ ................................ ................................ ..... 23 
Attested SPDM  ................................ ................................ ................................ ................................ .........................  24 
Two -Phase Authentications  ................................ ................................ ................................ ...............................  26 
5     Device Firmware Update  ................................ ................................ ................................ ................................ .. 28 
Runtime Update Control Policy  ................................ ................................ ................................ ........................  29 
Secure Update Policy  ................................ ................................ ................................ ................................ ............  30 
Evide nce Reporting Policy  ................................ ................................ ................................ ................................ .. 32 
Evidence Collection Time  ................................ ................................ ................................ ................................ .... 34 
Update Notification Policy  ................................ ................................ ................................ ................................ .. 36 
Channel Reset Policy  ................................ ................................ ................................ ................................ .............  38 
Runtime Update Attestation  ................................ ................................ ................................ ..............................  39 
6     Summary  ................................ ................................ ................................ ................................ ................................  41 Table  of Contents    
4        Document Number:  351998 -003    
Appendix A: Mapping to Intel® TDX Connect  ................................ ................................ ................................ .. 42 
Device Attestation – Evidence Obtaining and Reporting  ................................ ................................ ....... 42 
Device Attestation – Evidence Verification  ................................ ................................ ................................ .. 42 
Device Local Verification  ................................ ................................ ................................ ................................ . 42 
Device Remote Verification  ................................ ................................ ................................ ............................  43 
References ................................ ................................ ................................ ................................ ................................ ...... 44 
Standards  ................................ ................................ ................................ ................................ ................................ ... 44 
Web Resources  ................................ ................................ ................................ ................................ ........................  46 
 
  Overview    
5        Document Number:  351998 -003    
Overview  
Virtualization -based Trusted Execution Environments (TEEs) are used to host confidential 
computing workloads that are isolated from hosting environment s, such as if the virtual 
machine monitor ( VMM ) is untrusted. In this document , such TEEs are re ferred to as Trusted 
Execution Environment VMs (TVMs) to distinguish them from traditional virtual machines  
(VMs) . 
When a portion of a device  such as a TEE Device Interface  (TDI) is assigned to a virtual 
machine ( VM), the system must  establish and maintain a trusted execution environment for 
the composition. A TDI is the unit of assignment for an IO -virtualization capable device or a 
Virtual Function (VF) when using single Root IO virtualization (SR -IOV).  
In a host environment , we us e TEE security manager (TSM) to indicate the logic trust 
computing base (TCB)  component to enforce the security policy. The TSM could be inside of  a 
TVM, or the TSM  could be a component outside of  the TVM and trusted by the TVM.  
Inside the device, we use Device Security Manager (DSM) to indicate the logic TCB component 
to enforce the security policy. The TSM should set  up a secure communicat ion channel with 
the DSM to get the device information and manage the device interface.  
This document describe s a fra mework to establish a trust relationship between the TVM and 
the device  with the help of TSM and DSM . As such , the device becomes a trusted device that 
can be included in the trust computing base ( TCB ) of the TVM.  Specifically, the document  
describe s mechanism s in the TVM  to: 
- Obtain  the identity of the device , such as the device certificate . 
- Obtain the evidence in the device, such as measurements of firmware and 
configuration . 
- Report the verifi able  evidence to an appraiser or verifier . 
- Verify  if the evidence represented by the identity follows the policy, such as 
match ing the latest one . 
This white paper  focuses  on how the verifier  is built  in the TVM , and how it can obtain 
information needed from the trusted device to perform  the necessary ac tions  described 
previously . Overview    
6        Document Number:  351998 -003    
Note : The definition for “trus ted” is different from “secure .” According to the Trusted 
Computing Group (TCG) definition, an entity can be trusted if it always behaves in the 
expected manner for the intended purpose. A trusted VM might not be  a secure VM : 
- If a VM has a known vulnerability that will expose a secret key, this VM is called a 
trusted VM but not a secure VM.  
- Similarly, a trusted device might not be a secure device. If a device is known to use 
a fixed value when  a true random number is required, t his device is called a trusted 
device but not a secure device.  
Defining  a secure VM or a secure device is out side the  scope of this document because the 
definition is highly dependent  upon the security requirement.  
The organization of this white paper  is as follows:   
• Chapter 1 will revisit the general attestation model .  
• Chapter 2 will describe the device attestation model  in TVM .  
• Chapter 3 will describe the remote attestation to a TVM and device s by a third -party.   
• Chapter 4 will discuss the mutual attestation flow  - a device may want to attest a TVM 
in some special use case .   
• Chapter 5 discusses  the device firmware update support.  
• Appendix  A will map th e method described in this white paper  to the Intel TDX 
archite cture . 
  1     General Attestation Model    
7        Document Number:  351998 -003    
1     General Attestation Model  
Many standa rdization  bodies  are defining an attestation  model , such as  the National Institute 
of Standards and Technology ( NIST ), the Trusted Computing Group ( TCG ), and the Internet 
Engineering Task Force ( IETF ). Figure 1 -1 shows the general attestation data flow  defined by 
the IETF Remote Attestation Procedures (RATS) working group  in RFC 9334 . 
 
Figure 1 -1: IETF RATS Attestation Data Flow  (RFC  9334)  
 
Let’s clarify some term s here  and give an example  of platform attestation.  
Role:  
1) Attester : The entity that provides verifiable evidence to an appraiser.  Example : a 
trusted platform module (TPM) and a platform firmware . 
2) Verifier : The entity that c ompares  available  evidence with the reference manifest 
according to the appraisal policy.  Example : an attestation agent in the operating 
system . 
3) Relying Party : The entity that decides how to use the attestation result. Example: a  
management component to decide if the platfo rm is allowed to access to an internal 
network.  
4) Endorser : The entity that provides the endorsement to help the appraiser verif y the 
authenticity of the evidence.  Example: a platform manufacture r. 
5) Reference Provider : The entity that provides the reference manifest to help the 
appraiser compare with  the evidence.  Example: a platform manufacturer  and a device 
manufacture r. 
Artifact:  
1     General Attestation Model    
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1) Evidence : The property or the state of a component . It usually means measurement . 
Example: a set of TPM platform configuration register s (PCR s) and a TCG event log . 
2) Endorsement : The security statement from the endorser.  Example: a platform  
certificate . 
3) Reference Manifest : The reference property or state of a component from the 
reference provider.  Example: a set of  platform reference measurement  for PCRs or the 
TCG event log . 
4) Appraisal Policy : A set of rules to inform  the appraiser how to verify the evidence.  
Example: A) a rule that requires all PCR matches ; B) a rule that requires a subset of PCR

Artifact:  
Example: A) a rule that requires all PCR matches ; B) a rule that requires a subset of PCR 
match es; C) a rule that requires a subset of TCG event log match es. 
Attestation/Reporting : The presentation of verifiable evidence to an appraiser , which could 
be local attestation if the attester and appraiser roles are in same entity . It could also be  
remote attestation if the attester in one entity need s to convey the evidence to an appraiser in 
a different entity, such as  a remote server . Example: using  the TPM Quote command to report 
the platform configuration register (PCR) signed with the TPM attestation key . 
  2     Device Attest ation    
9        Document Number:  351998 -003    
2     Device Attestation  
Now, we need  to resolve the problem: If a device function is assigned to a  TEE for the 
confidential computing workload , how  do we attest th e physical device ? Here the term 
“assign” means that there is  a trusted relationship between the TEE and the physical  device, so 
the TEE can offload any confidential data to the device function - TEE Devi ce Interface (TDI) . 
The TDI could be a physical function (PF), a virtual function (VF), or an Assignable Device 
Interface (ADI) . 
Figure 2-1 shows an example of how to map figure 1 -1 to the TVM device local  attestation 
model.  
 
Figure 2-1: Device  Local Attestation Model  
The following  are examples of roles and artifacts.  
Role:  
1) Atteste r: a trusted execution environment (TEE) security manager (TSM) . 
2) Verifier : a trusted execution environment (TEE) local verifier . 
3) Relying Party : a trusted execution environment (TEE) device  manager (T DM). 
4) Endorser : a device root certificate authority  (CA) , or a device manufacturer.  
5) Reference Provider : a device manufacturer.  
Artifact:  
1) Evidence : a set of measurements from the device , the DICE certificate  which includes 
the measurement s, and the evidence manifest . 
2) Endorsement : a device root CA certificate , or a device certificate chain.  
3) Reference : a device reference measurement  and reference manifest . 
2     Device Attestation    
10        Document Number:  351998 -003    
4) Appraisal Policy : a rule that requires  all measurements  to match so that any device 
update will cause verification failure . 
Attestation/Reporting  Example : using the Secure Protocol and Data Model (SPDM) 
GET_MEASUREMENTS command to report device measurements with a digital signature 
signed with the device private key . For the Device Identity Composition Engine ( DICE)  device, 
the signing  key is a  device  alias key.  
The e ndorsement, reference manifest , and appraisal policy can be built in the TVM/TSM or be 
input at runtime. If they are input at runtime, these artifacts shall be measured to a TEE 
measurement register (MR) as part of TEE attestation.  
Device Evidence and Evid ence Repor ting 
Distr ibuted Management Task Force (DMTF) defines a Secure Protocol and Data Model (SPDM)  
that can be used to identify a device, authenticate a device,  and collect device measurement s. 
A TSM may  use the  SPDM GET_MEASUREMENTS  command  to collect device measurements.  
This can include measurement s for the immutable ROM , mutable firmware, hardware 
configuration (e.g. straps ), firmware configuration  (e.g. configurable policy ), debug mode , boot  
mode, version / secure version number , etc.  
The measurement is signed with the SPDM device private key. As such, the TSM use s the 
device public key to verify the integrity of the measurements record.  
If the device does not support an asymmetric cryptography algorithm such as digital 
signature, the T SM may use the pre -shared key (PSK). The PSK shall be provisioned to the 
device and TSM with confidentiality  and integrity  consideration.  
For example, only an authorized owner is allowed  to provision the device PSK. The TSM 
should be encrypted at rest and only be  decrypted when it is inside of TEE , or when the PSK is 
derived from secure communication between the verifier and the device . 
A TSM may use  the SPDM PSK _EXCHANGE  command to authenticate the device and get the 
device measurements.  This may be a summary measurement for all component s, or a 
summary measurement for the TCB.  The device returns the response data with Hash -based 
Message Authentication Code (HMAC). As such, the TSM use s its own PSK to verify the 
integrity of the message data.  
If the dev ice supports Device Identity Composition Engine ( DICE),  the device may also return a 
DICE certificate in the SPDM GET_CERTIFICATE  command, where the DICE certificate includes 
DICE TCB information. A TSM verif ies the digital signature of the DICE certificat e with the 
device certificate.  
If a certificate chain includes DICE T CB information, the n the verifier shall use the 
measurement in the TCB information  instead of the SPDM measurement. This is because in 2     Device Attestation    
11        Document Number:  351998 -003    
DICE use case s, the SPDM responder is the firmware layer  and is not trusted when firmware 
reports its own measurement.  
Table 2 -1. Evidence and Collection  (Example)  
Evidence  Reporting  Device Capability  Cryptography  
SPDM 
Measurements  SPDM 
GET_MEASUREMENTS  with 
digital signature  SPDM  with 
Asymmetric  Asymmetric  
SPDM  
summary  
Measurements  SPDM PSK_EXCHANGE  
with HMAC  SPDM  with Symmetric  Symmetric  
DICE TCB Info  SPDM GET_CERTIFICATE  
with digital signature  DICE and SPDM  with 
 
In order to describe the content of the measurement s, the device may report a measurement 
manifest, which is an evidence  manifest.  The evidence manifest should be presented to the 
verifier together with the evidence.  
Device Reference Integrity Manifest  (RIM)  
The device reference integrity manifest  (RIM)  shall be published by a device vendor , such as:  
• a software ID (SWID) tag defined in ISO/IEC 19770 -2 and NISTIR  8060 ;  
• a concise SWID (CoSWID) tag defined by the ITEF Security Automation and 
Continuous Monitoring  (SACM ) working group ; or  
• a concise RIM (CoRIM) defined by the IETF Remote Attestation Procedures (RATS) 
working group.  
The SWID -based RIM is defined by TCG in  the RIM-Information model (IM), and the CoSWID  
based RIM, or CoRIM , is defined by RATS.  The SWID tag uses Extensible Markup Language 
(XML ) format, while the CoSWID tag, or CoRIM , uses JavaScript Object Notation  (JSON ) or 
Concise Binary Object Representation  (CBOR ) encoding.  Both SWID and CoSWID can be used 
in platform attestation use cas es according to the TCG  RIM IM specification . 
The “CoSWID ” tag is designed to represent  software  components . However, a device may 
need to present some hardware component information.  As such, t he device may use a 
concise module  identifier  (CoMID) to describe the hardware component  and provide a 
counterpart to CoSWID.   2     Device Attestation    
12        Document Number:  351998 -003    
The software stored in a hardware module can be referred to as firmware. The firmware may 
be presented as CoSWID or a CoMID based upon the implementation . Both Co SWID and 
CoMID can be included in a CoRIM  provided by the device manufacturer . 
The device manu facture may choose to support either CoSWID or CoMID,  or both. For a device  
with layered architecture, such as DICE , the CoRIM is a good  choice. The support RIM may be a 
binary presentation, such as an SPDM Measurement Block returned by SPDM 
GET_MEASUREMENT,  an SPDM Measurement Summary Hash returned by SPDM 
CHALLENGE/KEY_EXCHANGE/PSK_EXCHANGE, or DICE TCB info returned by SPDM 
GET_CERTIFIC ATE.  
 
Device Appraisal Policy  
Appraisal policy defines how the verifier verifies the evidence against the RIM.  Different 
solution s may use different appraisal polic ies. Table 2 -2 shows example appraisal policies . 
Table 2 -2. Appraisal Policy (Example s) 
Case  Rule  Consequence  Use Case  
1 All measurements shall 
match  RIM.  Any device change will cause 
verification failure . 
Device change shall be together with 
appraisal policy update.  No update is 
allowed.  
(High assurance 
platform. ) 
2 Immutable ROM and 
mutable firmware 
measurement match 
RIM.  Device configuration change will not 
cause verification failure.  Configuration 
change  is 
allowed . 
3 Device TCB 
measurement s shall 
match RIM.  A non-TCB d evice mutable firmware 
change will not cause verification 
failure . Non -TCB 
change is 
allowed . 
4 Device certificate chain 
shall match  the trust 
anchor  (root CA or 
intermediate CA) . Any device TCB or mutable firmware 
failure . Device firmware 
change is 
allowed.  
5 Device root CA 
certificate  shall match  
the device root CA 
certificate  list. Any device change or even device 
certificate  reprovision will not cause 
verification failure , as long as the 
device certificate is signed by the root 
CA certificate.  Device iden tity 
change is 
allowed.  2     Device Attestation

allowed.  
change  is 
allowed . 
change is 
allowed . 
change is 
allowed.  
change is 
allowed.  2     Device Attestation    
13        Document Number:  351998 -003    
 
Open Policy Agent (OPA) defines a policy language  called  “Rego ” that can be used to describe 
the appraisal policy.  For example, the OPA Rego policy receives a nested JSON object  input  
with three attributes (“evidence ,” “endorsement ,” and “reference” ) as the input , and generate s 
an attestation result in another JSON object as the output . 
Device Identification and Authentication  
Before attestation, the TSM may need s to identify and authenticate a device.  The SPD M 
GET_CERTIFICATE command can be used for identification. SPDM  CHALLENGE command  or 
KEY_EXCHANGE command can used for authentication , because they require the device 
certificate chain is included in the  message  transcript for digital signature verification . The 
difference is that SPDM CHALLENGE command  is one time action, while KEY_EXCHANGE  
command can be used to establish an SPDM secure session  for further protocols  such as 
IDE_KM or TDISP . SPDM GET_MEASUREMENT command can also be used to verify the owner 
of the device private key, but it cannot be used prove the owner of the device certificate chain, 
because the device certificate chain is not in the message transcript of measurement.  Figur e 2-
2 shows an example.  
 
Figure 2-2: Device Authentication  Flow  
 
Step 1 : A VMM launches a TVM with a TSM.  The T VM or TSM  may or may not include a trust 
anchor list as part of endorsement , such as a root certificate list , or an intermediate certificate 
list. If the trust anchor  certificate list is present, it shall be measured together with the TVM or 
TSM.  
14        Document Number:  351998 -003    
Step 2 : The VMM may optionally input a trust anchor list to the TVM  or TSM , as part of 
additional endorsement . This additional trust anchor list is not trusted and shall be measured 
to a TEE dynamic Measurement Register (MR) . 
Step 3: The T VM or TSM should  extend the policy —trust anchor list into a TEE measurement 
register (MR) and record an event log. The MR could be a static MR to record the laun ching 
time state, or a dynamic MR to record TEE runtime state , based on when the policy is input . 
The MR and event log are presented as part of evidence for the whole TEE.  
Step 4: The TSM uses the SPDM GET_CERTIFICATE  command  to retrieve the device certificate 
chain  and verifies the certificate chain with the trust anchor list. If the verification passes, then 
the TSM uses the SPDM KEY_EXCHANGE command to authenticate the device  and establish a 
secure SPDM session .  
The TSM ge nerates a nonce  and sends  it to the device, then the device signs the data with the 
nonce using its private key and returns the data back. The TSM verifies the digital signature 
with the leaf certificate in the device certificate chain . 
Step 5: The T VM or TSM should  extend the authority -matched trust anchor  and optional 
device certificate chain  into the TEE MR and record an event log. Care must be taken that the 
trust anchor  is the device “class” information , with all devices in this class having the same 
class information . And  the device certificate chain may be  the device “instance” information , 
with  each device having it s Unique Data S ecret (UDS) information there.  The “class” 
information and “instance” information should be put into different MRs. 
 
PSK Based Authentication  
A device may only support  a symmetric cryptography algorithm, but not support asymmetric 
cryptography algorithm s such as digital signature. In such case, the TEE may use pre -shared 
key (PSK) based authentication  by using SPDM PSK_EXCHANGE . Figure 2 -3 shows an 
example.  
 2     Device Attestation    
15        Document Number:  351998 -003    
 
Figure 2-3: PSK based Authentication and Attestation  Flow  
Step 1: A VMM launches a TVM with a TSM . The TVM or TSM may or may not include  a PSK 
hint. If the PSK is stored in the device secure storage, t he PSK hint may be used as an identifier 
to specify which PSK will  be used. If the PSK is not stored in the device, t he PSK hint may also 
be used to derive the PSK , for example , together with the unique device secret (UDS).  
Step 2: The VMM may optionally input the PSK hint  to the TVM  or TSM . 
Step 3: The T VM or TSM should  extend the PSK hint  into a TEE measurement register (MR) 
and record an event log . 
Step 4: The TSM may have a PSK  provisioned inside of  the TSM. If the PSK is not provision ed, 
then the TSM may communicate with a PSK server to retrieve the PSK in a secure 
communication channel.  Significantly, the PSK se rver shall do TEE authentication /attestation  
to ensure that the T SM is trusted before pass ing the PSK to the T SM. 
Step 5: Now that the TSM has retrieved the PSK , it uses  the SPDM  PSK_EXCHANGE  comm and 
to authenticate the device . The TSM generates a random number and sends it to the device, 
which  performs HMAC on the random number with the device PSK and returns the data back. 
Then the  TSM verifies the HMAC with the TSM PSK . 
 
Device Local Attestation  Flow  
Now the TVM can perform local attestation for the device. Figure 2 -4 shows an example.  
16        Document Number:  351998 -003    
 
Figure 2-4: Device Local Attestation  Flow  
Step 1: The TSM collects the evidence from the device as discussed in the previous section. 
Such as the SPDM  GET_MEASUREMENTS  command for devices with asymmetric 
cryptography support, or the SPDM PSK_EXCHANGE  command for devices with symmetric 
cryptography support only. The TSM may accept a nonce from the local verifier to prove the 
freshness of the evidence . TSM shall perform necessary integrity checks on the evidence (such 
as digital signature), to ensure that data is fresh and has not been tampered with. The TSM 
then passes the information to the verifier in the TVM.  
Step 2: The T VM gets a RIM manifest. The RI M manifest may be included in a device, passed 
from the VMM , or embedded in the TVM. The T VM gets a device RIM according to the RIM 
manifest. Again, there are multiple possibilities. The device RIM may  be received from the 
device vendor server at runtime, passed from the VMM , or embedded in the TVM.  
Step 3: The T VM should  extend the policy – device RIM into TEE MR and record an event log. If 
the appraisal policy is input, it shall also be extended. For example, a list of object identifier s 
(OID) to  check with.  
Step 4: The device verifier in the TVM can appraise the evidence with the RIM collected with 
the appraisal policy we discussed in the previous section.  
Step 5: When the device verifier in the  TVM checks  the device identity, it should extend the 
authority , such as the device root certificate as a trust anchor  to the TEE MR , and record  it in 
the event log.  
Step 6: The device verifier in the TVM may  extend the device runtime measurement to TEE MR 
and record the event log , together with device info rmatio n such as device type, device 
location, vendor ID, device ID, class code, etc. 
17        Document Number:  351998 -003    
Device Remote  Attestation Flow  
The TVM can also support device remote  attestation if there is a remote device verifier . We 
will describe two topology patterns  defined in RFC 9334  – Background Check model and 
Passport model.  
Background  Check  Model  
Figure 2 -5 shows the attestation Background Check Model  defined. The relying party gets the 
evidence from the attester, then the relying party communicates with the ver ifier and get s the 
attestation  result  directly.  
 
Figure 2-5: Device  Remote  Attestation  Background Check Model  
 
Figure 2 -6 shows an example.  
18        Document Number:  351998 -003    
 
Figure 2-6: Device Remote  Attestation  Flow  - Background Check Model  
 
Step 1: (Same as the local attestation) The TSM collects the evidence from the device as 
discussed in the previous section. The TSM may accept a nonce from the remote verifier to 
prove the freshness of the evidence. TSM shall perform necessary integrity checks o n the 
evidence (such as digital signature), to ensure that data is fresh and has not been tampered 
with. The TSM then passes the information to the TVM.  
Step 2: The TVM should extend the remote device verifier information into TEE MR and record 
an event lo g, such as the uniform resource locator  (URL) of the remote device verifier.  
Step 3: The TVM sends the evidence to the remote device verifier.  
Step 4: The remote  device verifier gets a device RIM from the deice vendor server. This should 
happen at runtime to ensure the freshness of the manifest. Caching is also possible to 
improve the performance of verification.  
Step 5: The remote device verifier can appraise the evidence with the RIM collected with the 
appraisal policy.

appraisal policy.  
Step 6: The remote  device verifier  returns  the attestation result to the TVM.  
 
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Passport Model  
Figure 2 -7 shows the attestation Passport  Model defined. After t he attester provides the 
evidence  to the verifier, the attester gets the attestation result directly from the verifier. Then 
the attester can just provide attestation result to the relying part.  
 
Figure 2-7: Device  Remote  Attestation  Passport  Model  
 
Figure 2 -8 shows an example.  It is similar to the one in background check model.  The 
difference is that it is TSM that communicates with the verifier and get the attestation result.  
Then the TSM can present the attestation result to the TVM directly.  
2     Devic e Attestation    
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Figure 2-8: Device Remote  Attestation  Flow  - Background Check Model  
 
3     TVM Remote Attestation    
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3     TVM Remote Attestation  
TVM Remote Attestation with Device  Local  Attestation  
For a given T VM, a third -party  TVM remote verifier may perform remote attestation for the 
TVM, TSM , and device , to verify if the TVM  perform ed a  trusted  boot  and verifie d the device  
locally . Figure 3-1 shows an example.  
 
Figure 3-1: TVM Remove Attestation with Device Local  Attestation  
Step 1: The TVM remote verifier collects the evidence in the TEE measurement register  (MR)  
and event log from the TEE attester . The MR and event log include the information on the 
TVM itself , the TSM , and the trusted device used in the TVM . This can includ e the policy 
(device RIM, trusted anchor list), the authority (matched trust anchor), device class information 
(measurement), and device instance information (certificate chain) . 
Step 2: The TVM remote verifier performs a TVM remote attestation for the MR and event log. 
This step is TEE -specific. For example, this could be a TEE quote  verification . 
Step 3: The TVM remote verifier gets the reference integrity manifest (RIM) from TVM provide r, 
TSM provider , and the device provider.  The TVM RIM , TSM RIM , and device RIM are provided 
by different vendor s. The TSM RIM and device RIM may be referred  to in the TVM RIM, based 
on the TVM policy.  
Step 4: The TVM remote verifier may have its own appraisal policy for the TVM , TSM , and the 
trusted device.  
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TVM  Remot e Attestation with Device Remote Attestation  
A third -party TVM remote verifier may also perform remote attestation for the TVM that  
perform ed a trusted boot and verified the device remotely . Figure 3-2 shows an example.  
 
Figure 3-2: TVM Remove Attestation with Device Remove Attestation  
Step 1: The TVM remote verifier collects the evidence in the TEE measurement register (MR) 
and event log from the TEE attester. The MR and event log include the information on the 
TVM itself, the TSM, and the remote device verifier information . 
Step 2: The  TVM remote verifier performs a TVM remote attestation for the MR and event log. 
This step is TEE -specific. For example, this could be a TEE quote verification.  
Step 3: The TVM remote verifier gets the reference integrity manifest (RIM) from TVM provider, 
TSM provider, and the device remote verifier provider. The TVM RIM, TSM RIM, and device  
remote verifier  information are provided by different vendors. The TSM RIM and device 
remote verifier information may be referred to in the TVM RIM, based on the TVM po licy. 
Step 4: The TVM remote verifier may have its own appraisal policy for the TVM, TSM, and the 
trusted device  remote verifier . 
 
4     Device Mutual Attestation    
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4     Device Mutual Attestation  
Attestation is performed  because  a TEE need s to verify that a device before the TEE decides  to 
offload the workload to the device. In most cases, this is good enough. However, a special  
device may want to verify the TEE or the host platform to decide if the device wants to accept 
the offload ing.  
For example , a C loud Service Provider (CSP)  can build a special accelerator and only accept 
the workload from a set of special CSP specific service TDs  or host platform . This can be 
achieved  by mutual authentication . 
Mutual Authentication  in Secure Session  
Mutual authentication (also known as two -way authentication) means that both entities need  
to authenticate each other at the same time in an authentication protocol before the secure 
session is established.  For example, the network transport layer security (TLS) protocol or the 
SPDM protocol suppo rt mutual authentication.  
When a TVM authenticates the device, the device can also authenticate the TVM . The device 
need s a way to identify the T VM and verify the TVM information, such as a certificate , TEE 
measurement , or TEE quote . The SPDM Key Exchange process (K EY_EXCHANGE  + FINISH  
command) with encapsulated GET_CERTIFICATE can be used to support the mutual 
authentication. Figure 4-1 shows an example.  
 
Figure 4-1: TEE Authentication  
Step 0: A T SM can initiate the SPDM Key Exchange process to set up  a secure session with the 
device.  
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Step 1: The device returns SPDM Key Exchange with a mutual authentication flag to indicate 
that mutual authentication is required to set  up the secure session. Then the DSM sends the 
SPDM GET_CER TIFICATE command to collect the T VM information.  The TSM will start the 
Attested SPDM flow. We will discuss  the general Attested SPDM  in more detail in the next 
section.  
Step 2: The TSM collects the TE E measurement register (MR) in a TEE report from the CP U. 
The TEE report may include both TEE and host platform information , such as CPU version or 
secure version number ( SVN ). 
Step 3: The TSM may optionally get the TEE quote based on the TEE MR  and report . A special 
quoting TEE can help do that work. In some scenario s, a TEE quote must be used because the 
TEE report may only be verified in  the local machine. Only a TEE quote can support remote 
Step 4: Once the TSM gets the TEE quote, the TSM can put the information into a TEE  
certificate  with a special Object ID (OID) . The TEE certificate can be a  self-signed  ephemeral 
certificate generated at runtime.  Then the TSM returns the TEE certificate with the embedded 
TEE quote to the device.  Technically, the TSM can embed any  data th at is required from the 
device based on the policy, such as the TEE event log.  
Step 5: After the device gets the TEE certificate, the device obtains the TEE  quote from the 
TEE certificate. The device should verify the TEE certificate, TEE quote, TEE report , TEE 
measurement , CPU SVN , or any TEE specific data  or platform specific data  based on its policy.  
Only after the verification pass  can the device continue the secure session setup flow wi th the 
TSM.  
Attest ed SPDM  
The flow outline d previously  is not a traditional  SPDM mutual authentication flow.  A variant 
called Attest ed SPDM, which is similar to Attest ed TLS, is an SPDM session that integrates the 
remote attestation validation as part of t he SPDM session establishment.  Once established, 
the Attested SPDM  guarantees that an attested connecting party is running inside a TEE with 
expected identity.  
In the traditional SPDM flow, both entities use an X.509  certificate chain as their identity 
information. This certificate chain is transferred to the peer via an SPDM CERTIFICATE 
response.  One entity  can then verify the digital signature from  the other one by using the 
public key in the leaf certificate . Figur e 4-4 shows the SPDM mutual authentication flow.  4     Device Mutual Attestation    
25        Document Number:  351998 -003    
 
Figure 4-4: SPDM Mutual Authentication Flow  
The Attested SPDM uses a transient self -signed X.509 certificate that represents the identity. 
This certificate is bound to the specific TEE via TEE -specific inf ormation such as a TEE 
attestation quote.  Figure 4 -5 shows one example.  
 
Figure 4-5: Attested SPDM Mutual Authentication Flow  
The TEE certificate can be generated with the following flow outline : 
Step 1: When a TEE need s to provide a TEE certificate, the TEE generate s a transient self-
signed public/private keypair . 
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Step 2: The TEE calculates the hash of the public key and use s the public key hash as  input to 
get the TEE report. The TEE report includes the measurement of the TEE, and host platform 
information , such as the CPU SVN . The TEE report can be used as TEE identity.  
Step 3: The TEE sends the TEE report to a quoting TEE to get the TEE quote . The TEE quote is 
used as TEE evidence.

used as TEE evidence.  
Step 4: The TEE embeds the TEE evidence (TEE quote ) into the TEE certificate with a specific 
Object ID (OID).  
Step 5: The TEE can send the TEE certificate to the peer.  
The peer should  verify the TEE certificate  per the following : 
Certificat e Validation  
The verifier checks  the signature of the self -signed TEE certificate to confirm  whether  the 
attestation TEE evidence (TEE quote) is genuine and unmodified.  
Evidence Validat ion 
The verifier e xtract s the TEE evidence from the TEE certificate and perform s TEE evidence 
validation , such as TEE quote verification  based upon a n evidence  verification policy . 
Identity Validat ion 
The verifier v alidate s the TEE identity  (TEE measurement , SVN ) based upon an identity 
verification policy , such as the reference measurement or SVN . 
Host Platform Validat ion 
The verifier may validate the host platform information,  based on a platform verification 
policy, such as the CPU  SVN , or platform certificate.  
Only after all verification s are  passed  can both entities know that the peer is  the intended 
party.   
 
Two -Phase Authentications  
In the mutual authentication model, the device only authenticates the TSM because it is the 
TSM that sets up the communication with the device. The device cannot authenticate a full 
TEE, because the full TEE might not be ready at that moment.  
If a device wants to authenticate a full TEE, then we may use  two-phase authentications.  
1) Phase 1: The TSM attests the device and provides the evidence to the TEE. Then the 
TEE relies on a policy to decide if it can accept  the device. This is discussed in Chapter 
2 and Chapter 3.  
2) Phase 2: After a TEE is fully launched, t he device collects evidence from the TEE  and 
attests it. Or the TEE can collect the evidence by itself and present  that to the device. 4     Device Mutual Attestation    
27        Document Number:  351998 -003    
The device  relies on its own appraisal policy to determine if the device accepts the TEE. 
This could be a normal TEE  attestation flow  such as a TEE Quote , or another  
mechanism  such as password -based  authentication , token -based  authentication , etc.  
Care must be taken that th e two-phase authentication is bound in one secure session.  For 
example, phase 1 is the one -way authentication secure session, and phase 2 happens inside of 
this secure session.  
  5     Device Firmware Update    
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5     Device Firmware  Update  
A trusted device may support  a firmware update. The device root -of-trust for update (RTU) 
shall follow NIST SP800 -193 to ensure that the new firmware image is always authenticated, 
and the new image has an equal or high er security version number  (SVN)  to prevent  a rollback 
attack.  
A typical d evice includes  hardware immutable read -only memory (ROM) and mutable 
firmware on the non -volatile  (NV)  storage , such as NOR flash  or NAND flash , and runs firmware 
code in the system random -access memory  (RAM) , such as static RAM  (SRAM ) or dynamic RA M 
(DRAM) . The immutable ROM is not updatable. The mutable firmware in NV storage and 
system RAM is updatable. Let’s clarify some term s for device  update s. 
• Firmware NV Storage  Update : the device updates  the mutable firmware on the NV 
storage. This  will not touch the run time firmware code in  the RAM.  The NV storage 
change might  not take effect until the device performs a  reset.  
• Firmware Update Activat ion: the device update s the runtime firmware code in th e 
RAM  after firmware NV storage is updated.  
o Activation After Reset : the device trigger s a reset to finish activation , such as a 
device function reset , or a device system reset . This is usually with rolling 
firmware support.  
o Runtime Activation : the device does  not need to trigger a reset  to finish 
activation . The system running state is kept during activation.  
• Firmware Live  Patch : the device updates the runtime firmware code in t he RAM 
without updating NV storage.  However, a  device reset will discard those patches and 
roll back  the firmware into  the old state.  
o Live Patch with Activation : the device is required to trigger an activation to 
make the new patched image take effect.  
o Live Patch without Activation : the device uses the new patched image 
• Firmware Update Lock : the device is configured to reject any firmware update request 
until it is unlocked.  
A traditional device may only support  the firmware NV storage update and firmware update 
activation  after a device reset.  Some devices may be allowed to  activ ate the new image at 
runtime without a device  reset. Some devices may  support live patching, where part of the 
firmware may be patched without reset.  This no -reset-update feature may be used in data 
center cloud VMM environment, where the TVM may keep a secure connection to a virtual 
device  current  when the physical device is patched.  5     Device Firmware Update    
29        Document Number:  351998 -003    
Runtime Update Control Policy  
A device may choose how to support a runtime update with or without reset, based on device 
capability and policy.   
• SPDM - Measurement Freshness Capability  (MEAS_FRESH_CAP)  is defined in  the 
SPDM 1.0 specification. This indicates whether the device is able to return a fresh 
measurement  as follows.  
o No Fresh Measurement : the device only returns the measurements computed 
during last time reset.  
o Fresh Measurement : the device can recompute all measurement s and always 
return the fresh measurement s. 
• SPDM - Session Policy ( Termination Policy ) is defined in the  SPDM 1.2 specification . 
When a secure session is created between the device and the TSM , the TSM can 
indicate that a session termination policy after the firmware is  updated : 
o Unconditional Termination : the device shall unconditionally terminate the 
session when the runtime update has taken effect . 
o Device  Controlled Termination : the device is allowed to decide whether to 
keep the session or terminate it based on the device policy.  For example, a 
session is k ept when SVN is the same  or terminated when  SVN is updated.  
• Trusted Device Interface Security Protocol (TDISP) - Interface Lock Policy  
(NO_FW_UPDATE)  is defined in the PCI-SIG TDISP specification. When a TSM requests 
the device to lock the interface, the TSM can indicate  the firmware update policy:  
o No Firmware Update : the device is not allowed to update firmware. The TSM 
shall stop the interface, unlock the device, then perform the firmware update.  
o Firmware Update : the device is allowed to update firmware at runtime.  
In a usual confidential computing environment  with device support , a VMM is the resource 
manager and decides the final update control policy (allow runtime update or not)  for the 
device . The TSM is policy enforcement and report s the final decision to the TVM  honestly . The 
TVM verifies the final update control policy for the device , and decide s whether it is 
acceptable or not.  
Ideally, the TVM should provide the preferred update control policy to the VMM as a hint, such 
as in a TEE manifest . If there are multiple TVMs requiring different update control policies , the 
VMM may  carefully isolate them and let them attach to different devices .  
If a TVM  wants to support  a runtime update without SPDM session termination, then the TVM 
shal l let the TSM  or TSM -RoT choose “Firmware Update” in  the TDISP  Lock Policy and “Device 
Controlled Termination” in the SPDM  session policy.  See Table 5 -1. 
Table  5-1. Runtime Update Control Policy  and Impact  
SPDM  Session  
TerminationPolicy  TDISP  
NO_FW_UPDATE  Result  5     Device Firmware Update    
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0 (Unconditional 
Termination)  0 (Firmware  Update ) No runtime update support.  
An u pdate will cause session termination.  
Termination)  1 (No Firmware  
Update ) No runtime update support.  
An update will cause session termination 
before device interface lock.  
Any u pdate is not allowed after device 
interface lock.  
1 (Device Controlled 
Termination)  0 (Firmware  Update ) Runtime update is allowed . 
or sess ion alive . This is controlled by the 
device.  
Update ) Runtime update is allowed before device 
or session alive  before device interface 
lock . This is controlled by the device.  
Any update is not allowed after device 
 
Secur e Update  Policy  
NIST SP800 -193 defines the Platform Firmware Resiliency Guidelines. The firmware update 
should prevent  a rollback attack. Usually this is achiev ed by verifying a secure version number 
(SVN). Please note the following term definitions .

device.  
 
(SVN). Please note the following term definitions .  
• Secure Version Number (SVN) is a special version to indicate the security property of 
the firmware. See Figure 5 -1. 
o Birth  SVN  is the SVN in the device at launch . This is a fixed value  and cannot be 
changed even after a runtime firmware update.  It may  only be change d after a 
device re set. 
o Current SVN  is the SVN for the current running firmware.  The current SVN shall 
always be bigger than or equal to the birth SVN. This is a dynamic value. The 
current SVN becomes the update SVN after a runtime update.  
o Update SVN is the SVN in the firmwa re update package.  This is a fixed value for 
the update  package.  5     Device Firmware Update    
31        Document Number:  351998 -003    
 
Figure 5 -1: Device Firmware SVN  
• Rollback : Ideally, a new firmware version should be higher than the current firmware 
version. In some special cases, if the latest firmware version is found to be having 
stability issue s, then the owner of the platform or the device may choose to roll back  
the firmware to an older version.   
o The best practice is that firmware should only be allowed to perform a 
functional rollback, but not a security rollback . Rollback protection means that 
the attacker cannot  install an old firmware with known vulnerabilities.  As such, 
it is of great importan ce to protect the current SVN storage.  Usually, it is in 
tamper -proof non-volatile storage. Only an authorized entity is allowed to 
update the SVN.  
• SVN Commit  is a special step to update  the current SVN to the update SVN after a 
runtime firmware update. Th ere are two ways to commit SVN.  
o Immediate SVN Commit : after runtime firmware update, the current SVN is 
changed to  the update SVN immediately.  In this mode, the firmware may be 
updated to an older version, but it cannot be updated to an older SVN . 
o Delayed SVN Commit : the current SVN is NOT changed to the update SVN 
immediately after  a firmware update,  as the firmware may be in a middle state 
to do some device -specific function self -test to ensure that the new firmware 
image is  good enough. After the self-test, the update SVN is committed to the 
current SVN.  This mode can help the firmware rollback in case of functional 
issue s in any new firmware image , even if the SVN is higher  in the new image . 
With the definitions above , we can define the SVN Update Policy , which describes  how  to 
control the SVN checking.  
• Birth  SVN Mode : the device uses the policy  “Update SVN >= Birth SVN ” to verify the 
update package . As such, partial rollback (update SVN < current SVN) is acceptable.  
With this mode,  a device can roll back  to an old image if the new update image has 
function issue s. However, it might not be a secure solution . 
5     Device Firmware Update    
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• Incremental S VN Mode : the device uses the policy “ Update SVN >= Current SVN ” to 
verify the update package.  As such, no rollback is acceptable.  This is the best practice.  
If the device has function issue s after  a runtime update, it needs another way to roll 
back  to an o ld image  – for example, delay ing the SVN commit until after function 
verification.  
People should understand the P ros and C ons for the two SVN Update Polic ies. 
Evidence  Report ing Policy  
After the device is update d, the device may need  to report the  new  identity (certificate) and 
the new measurement information . The device may choose  an evidence  report ing policy  that 
describes how the device report s the new identity and new measurement.  
• Birth Mode : the device does not generate a new identi ty or measurement. It still 
reports the initial  identity and measurement at launch.  The initial  measurement could  
be the Secure Version Number (S VN). This is known as create time SVN.  
• Refresh Mode : the device generates  the current  identity and measurement based on 
the current  firmware image. It reports the current  identity and measurement . The 
current SVN  is known as report time SVN . 
• History Mode  (Ledger Mode) : the device generates  a new identity and measurement 
based upon the new firmware image , and it also keeps a copy of the old data . It reports 
the new identity and measurement , as well as the old measurement s as the history  
data , which is also known as a ledger . A simple led ger may only include the initial 
measurement and latest measurement. A full ledger may include the measurements of 
all update d firmware version s. 
This evidence reporting policy is similar to the SPDM Measurement Freshness Capability  (No 
Fresh Measurement vs. Fresh Measurement ), and the concept is extended to the device 
Some devices may implement Device Identity Composition Engine ( DICE) . In this case, the leaf 
certificate is an alias that contains the device identity information  and the  firmwar e 
measurement  (such as firmware hash) . If a layer (N)  firmware is updated, then its alias 
certificate shall be regenerated by layer (N -1) firmware . A reset may be required in this case  
because the layer (N -1) firmware might not exist anymore . This is the Refresh Mode .  
The TSM shall also use SPDM GET_CERTIFICATE to get the latest device certificate chain and 
SPDM GET_MEASUREMENT to get the latest device measurement. Then the TSM verif ies them  
against the appraisal policy.  Care need s to be taken that  the device reset happens  in a very 
short time period  (such as 10 m icrosecond s) to keep the hardware bus communication alive.  
Otherwise, the device might be considered in an error state and the hardware communication  
is broken.  5     Device Firmware Update    
33        Document Number:  351998 -003    
The new device measurement record may keep adding the hash of the new firmware as the 
new record and keep the old record as is. As such, the update history is maintained. This is the 
History Mode  (Ledger Mode) .  
History Mode is the best way to provide all information to a verifier , because the verifier can 
determine whether an intermediate vulnerable version has been used and updated later.  
Without the history, this information is missing.   
A device may only have  a limited measurement record index . For example, the TPM 
specification  only defines 24 platform configuration registers (PCR s) and the SPDM 
specification defines 254 measurement indexes . As such,  the device may use the hash extend 
function to measure all data into one dedicate d runtime update measurement slot, and use an 
event log to record all history data.  
If a device is not DICE compatible and it does not support SPDM Fresh Measurement 
capability, then it may use the Birth Mode  to support runtime update.  However, the TSM 
need s be aware that the collected evidence might NOT match the running firmware.  
The TSM need s to trust  that the DSM always updates the device firmware  with better or at 
least equal security by performing an SVN check.  However, the verifier has no way to know the 
current value or history.  
Besides evidence, the T SM and TVM  may collect other device information . For example:  
• TDISP – CAPABILITIES  includes the capabilities supported by the device, such as DSM 
capability flags, type of TDISP request message , lock interface flags, device address 
bits, or number of outstanding TDI SP requests . 
• TDISP – DEVICE_INTERFACE_REPORT  includes the runtime capabilities and setting s. 
o Capability  includes the  MMIO range attribute IS_MEM_ATTR_UPDATABLE.  
o Runtime setting s include  firmware update permission , Address Translation 
Service ( ATS ) state, Page Request Service ( PRS) state, Message Signaled 
Interrupt Extension (MSI_X ) control, Lightweight Notification Requester (LNR ) 
control, Transaction Layer Packet ( TLP) Processing Hints ( TPH ) control, and 
MMIO range report.  
The TVM may verify these  before accepting the device.  A device firmware runtime update 
should not impact the runtime setting in the DEVICE_INTERFACE_REPORT.  Since the TSM 
need s to send LOCK_DEVICE_INTERFACE to the DSM, the locked device interface should not 
be updated.  See Table 5-2. 
 
Table 5 -2. Updatable Device Information Summary  
Category  Example  Runtime Updat able  Info Report  5     Device Firmware Update    
34        Document Number:  351998 -003    
SPDM Certificate  X.509 Certificate  
(DICE or non -DICE)  Updatable . 
Equal or better 
security.  SPDM CERTIFICATE  
SPDM Measurement 
Code Hash of ROM,  
Hash of firmware,  
Firmware Version,  
Firmware SVN  Updatable . 
security.  SPDM 
MEASUREMENTS  
Data Hardware Fuse,  
Firmware Policy 
Config,  
Debug Mode,  
Device State ( Normal, 
Recovery)  Updatable . 
TDISP Capability  DSM capability flags,  
Lock interface flags Updatable . 
Equal or more 
capability.  TDISP CAPABILITIES  
TDISP Device 
Interface Report

Config,  
Interface Report 
Capability  MMIO range attribute  Updatable . 
capability.  TDISP 
INTERFACE_REPORT  
Runtime Setting  Firmware update 
permission,  
MSI_X control,  
MMIO range report  Not updatable . TDISP 
 
Evidence Collection Time  
The TSM need s to collect the device evidence and let  the TVM verify . If a runtime update is 
allowed, the device evidence may be changed at any time. Basically, the TSM may perform the 
evidence collection at the following point s: 
• Device  Connection Time : after the TSM sets up SPDM connection with the devic e 
(SPDM GET_VERSION) , it can collect the SPDM  certificate and  measurement s. This is 
called  connection  evidence  info.  
• Device  Secure Session Crea tion  Time : when the TSM sets up a new SPDM session 
with the device  (SPDM KE Y_EXCHANGE /PSK_EXCHANGE ), it can collect the SPDM 
certificate and measurement s inside of the session. This is  session evidence  info. 
Different session s may have different session evidence, if the TSM allows the device 
runtime update.  
• Device Interface Creation Time : inside of an SPDM session, a VMM may create 
multiple device interfaces and use the TDISP protocol  to manage the interface.  Once 
an interface  is created  (TDISP GET_VERSION ), the VMM may ask the TSM to collect the 
evidence info. This  is called interface creation evidence . Even in one SPDM session, 5     Device Firmware Update    
35        Document Number:  351998 -003    
different interface s may be associated with different evidence, if  the TSM allows the 
deice runtime update in a session.  
• Device Interface Lock Time : a TVM or VMM  may ask the T SM to collect t he evidence 
after the device interface is locked  (TDISP LOCK_DEVICE_INTERTFACE) . We call this 
interface lock evidence , which is very similar to interface creation evidence. The only 
difference is that the TSM need s to ensure the interface is  locked.   
• Device Update Time :  if a TVM or VMM knows that the device is  updated, they  may ask 
the TSM to collect the evidence again.  This evidence is called update fresh evidence . 
The collection action might not be immediately triggered after the device up date. 
There might be a delay based upon the refresh policy.  Care mu st be taken that the 
TVM has a way to guarantee the freshness  of the collected evidence, such as a nonce. 
The TSM shall collect and return both the evidence and the nonce to the TVM.  
If a TVM need s to offload the work to a device after device interface lock and device 
verification, then the best way is to get the interface lock evidence  for the device . This  is when  
the TVM can ensure that the device configuration and security guarantee are locked . The TVM 
may also collect the update fresh evidence  based on policy .  
One policy  example  is that  a cloud orchestrator may trigger a device firmware update and ask 
every TVM to refresh their device evidence. Another example is  when  the TVM creates a 
weekly task  every Sunday morning  to trigger the evidence collection , and verifies it based on 
the latest reference integrity manifest (RIM) .  
In case the device verification fails after collecti ng the refreshed device evidence, the TVM may 
perform a device  failure action , such as stop ping  and detach ing the device interface , or 
teardown  of itself immediately . 
Figure 5 -2 shows an example of device evidence (SVN) collected at different time s. The device 
is updated periodically and its SVN is increased , so the  SVN  collected at different time s is 
different.  The TVM can make the final decision about which SVN  is to  be used for verification.  
Note: Each device interface may be associate d with a different device SVN , even for the same 
device.  In figure  5-2, interface -A has locked evidence SVN -3, while interface -B has SVN -5 and 
interface -C has SVN -6. After refresh, the interface -A may see SVN -{3,4,5} , interface -B can only 
see SVN -5, and interface -C can see  SVN -{6,7}  in refresh with History Mode. 5     Device Firmware Update    
36        Document Number:  351998 -003    
 
Figure 5 -2: Device SVN collection example  
 
Update Notification Policy  
In case of device support for Refresh Mode , the device need s have a way to notify the TSM  
that the device update happened.  The device may  choose Update Notification Policy . The 
device may notify the TSM that a new update image is present and  gives the TSM a chance  to 
send the collect ed evidence again  or even pre -authorize the update.  See Figure 5 -3. 
• No Notification / Silence Mode : the  device does not send any notification to the TSM.  
• Passive Notification / Poll Mode : the device does not actively notify  the TSM. 
However, if the TSM starts communicating with the device, the device will return the 
firmware update notification.  
• Active Notification  / Interrupt Mode : the  device actively notifies the TSM after update , 
e.g., an event notification  mechanism . 
• Pre-Authorization Notification / Interrupt Mode : the  device actively notifies the TSM 
before  update  and ask s the host to authoriz e the new device firmware image . This 
gives the host -side software a chance to evaluate the new image based upon the host -
side device update policy  instead of the device -side device update policy . The host 
software need s to collect new image information (such as SVN or measurement) and 
send the pre -authentication res ult (accept or reject)  back to the device. Only after all 
host software allows the new image and the device allows the new image  will the 
update  happen.  
• Out of band ( OOB ) Pre-Authorization : instead of the device notifying the TSM, the 
host -side software may  get the new device firmware image information from the OOB 
channel (not in the SPDM session)  and evaluate the new image . If host -side software  
37        Document Number:  351998 -003    
decides to accept the new image, the host software can communicate with the TSM 
and let  the TSM send  an approval  message  to the device.  
• The approval message shall include the new device firmware information, such as a 
hash of the new firmware image, new firmware measurement and /or the new device 
certificate . As such , the device RTU knows that only the particular new firmware image 
is authorized by the host.  
 
Figure  5-3: Update Notification Policy  
Care must be taken that the notification happens  in a secure session . As such, the TSM can 
have a way to detect if the attacker in the middle drops the notification packet.  
38        Document Number:  351998 -003    
Channel  Reset Policy  
After  a TSM establishes a secure connection with a DSM, the TSM may use  this channel to 
manage the  device. For example, the TSM should use the integrity and data encryption (IDE) 
key management (IDE_KM) protocol to set up  the IDE key for a Peripheral Component 
Interconnection ( PCI) or Compute Express Link ( CXL) device  to secure the device physical link .  
The TSM should use the  Trusted  Device Interface  Security Protocol (TDISP ) to manage a TDI 
of a physical device  that supports scalable IO virtualization. These IDE_KM  protocol  or TDISP s 
are application protocols based upon the SPDM secure session.  
A TSM may use TDISP  to attach , detach , or lock  a device interface to a TVM in a trusted 
manner . The TSM may also use TDISP  to start  or stop the device  DMA or lock the firmware 
update.  Again , let’s clarify some terms for device communication.  See Figure 5-4. 
• Management Channel  is a secure c ommunication between  the TSM and DSM to allow 
the TSM to manage the DSM, such as TDISP  protocol on top o f an SPDM  secure 
session.  
• Data Channel  is the data transfer between the TVM and device  interfac e, such as 
memory mapped input/output ( MMIO ) and Direct Memory Access (DMA) . 
 
Figure  5-4: Communication Channel  between TVM and Device  
Based on different device update mechanisms, we may use a different  level reset . See table 5-
3. 
Table  5-3: Communication Channel Reset in Device Update  
Level  Channel Reset  Description  Example  
0 No Channel 
Reset  The device is not reset. The management 
channel between the TSM and DSM is kept. Firmware Live Path  
39        Document Number:  351998 -003    
The data transfer between the TVM and 
device interface is also kept.  
1 Data Channel  
channel between  the TSM a nd DSM is kept. 
The data transfer needs to be stopped and 
started again.  Firmware NV 
Storage Update + 
Runtime Activation  
2 Management 
and Data 
Channel  Reset  The device is reset after update. The 
management channel between  the TSM and 
DSM need s to be reestablished. The data 
transfer needs to be stopped and started 
again.  Firmware NV 
Activation After

3. 
and Data 
Activation After 
Reset  
 
The TEE environment may need to perform the attestation again once the device update 
happens.  
 
Runtime Update Attestation  
Device Update with Management and Data Channel Reset  
If the TVM knows that the device is reset,  and it need s to reestablish the management channel 
such as SPDM/ TDISP  and the data channel for MMIO and DMA.  
The T SM shall  collect the evidence again (such as via SPDM GET_CERTIFICATE and 
GET_MEASUREMENT ) and perform the verification according to the appraisal policy.  These 
steps are same as in the normal de vice startup.  
Device Update with Data Channel Reset  
If a device update  does not need  a reset, the management channel can be kept.  The SPDM 
session and TDISP  protocol are alive after the update.  
If a TSM still wants to perform attestation for the device after update, the TSM shall set 
NO_FW_UPDATE  policy  in TDISP  LOCK_INTERFA CE_REQUEST . The device firmware update 
request will be rejected  from  the device interface in CONFIG_LOCKED state. The VMM shall 
detach this device interface from TVM and move it to CONFIG_UNLOCKED  state to perform a 
device firmware update.  
The VMM will then attach the device again, and the TSM shall  follow normal flow  to collect the 
evidence and perform the verification according to its appraisal policy. The SPDM session is 
kept,  and the TSM may  skip the step to reestablish the SPDM secure session.  
In some rare case s, a device update may only involve a configuration change  that does not 
have a secure version number (SVN) associated with  it. In such case s, the device shall set the 
device interface to ERROR state.  5     Device Firmware Update    
40        Document Number:  351998 -003    
The device interface will then be detached from the TVM.  Again, the VMM may attack the 
device and the TSM shall follow the normal verification process mentioned previously . The 
configuration change shall be reflected in the new SPDM measurement.  
Device Update without Channel Reset  
In an aggre ssive device live patching, the device may choose to keep both the management 
channel and data channel . The DSM  may choose Birth Mode to report the  old certificate and 
measurement  collected at launch time. In this case, the DSM shall remove the SPDM 
MEAS_FRESH_CAP flag  to warn the T VM that collects the evidence.  
The DSM may also choose Refresh Mode with or without history to always report the fresh 
certificate and measurement  with the SPDM MEAS_FRESH_CAP flag . If the update happens, 
the DSM or out of band ( OOB ) mechanism may notify the T VM on the measurement change, 
then the TVM can collect the evidence again and perform  the verification process.  
However, th ere is a race condition w indow . Before the TSM performs verification, the device 
may already transfer data to the TVM.  This shall only be support ed when the DSM follows 
NIST SP800 -193 to perform a known good update  - such as with  a digital signature check, 
revocation list check, higher or equal SVN , etc.  
Device Update with pre-authorization  
If the device supports pre -authorization, then the DSM or OOB mechanism shall send a 
notification event to the TSM before the update happens.  The TSM may  collect the new image 
evidence information (such as measurement or SVN)  and perform the verification based upon 
the update appraisal policy  before the device updates the firmware .  
If the final result is PASS, then the TSM can send the pre-author ization result “APPROVE”  -
otherwise the TSM should send “REJECT”.  The DSM should follow the pre -authorization to 
perform the update or drop the update.  If the VMM must update the device, the VMM can 
choose to detach the device from the TVM. I f the device  must  update based upon its own 
policy, the device should disconnect with the TSM . 
  6     Summary    
41        Document Number:  351998 -003    
6     Summary  
In this  white paper , we discussed the device attestation in TEE  confidential computing . In a 
generic device attestation model, the TSM collect s the device identity (such as certificate 
chain) and evidence  (such as measurement) . After which  a verifier in the TVM verifies the 
evidence based on the endorsement  (such as root certificate) , the reference value (such as 
reference measurement ) and the  policy .  
The TVM may perform the local attestation as described previously . The remote part y may 
perform the remote attestation for the TVM, TSM , and the device.  As a special use case, the 
device may want to perform  attestation to the TVM/TSM , which can be done via mutual 
attestation or two-phase  attestation . Finally, the device may perform update s, and the 
TVM/TSM may need to perform attestation again after the update.   
  Appendix  A: Mapping to Intel® TDX Connect    
42        Document Number:  351998 -003    
Appendix A: Mapping to Intel ® TDX  Connect  
Intel ® Trust Domain Extensions (TDX) is a confidential computing architecture.  Intel ® TDX 
architecture may support device I/O with software protection mechanism s. Intel ® TDX  Connect 
support s device I/O with hardware protection mechanism s. The following section  provides a 
high -level summary of Intel ® TDX  mapping for the method descr ibed in this white paper. For 
more detail s on Intel ® TDX, please refer to the Intel ® TDX architecture specification.  Table A -1 
shows the generic term inology mapping for Intel ® TDX.  
Table A -1. Terminology Mapping  for Intel TDX  
Term  Intel ® TDX 1.0 /1.5  Intel ® TDX  Connect  Description  
TEE-IO Device I/O with 
software protection  Device I/O with 
hardware protection  The definition for 
confidential 
computing with I/O 
device.  
TEE Virtual 
Machine (TVM)  Tenant  Trust Domain 
(TD)  Tenant Trust Domain 
(TD)  The trusted virtual 
machine . 
TEE Security 
Manager (TSM)  Security Manager  in 
Tenant TD (or) a 
dedicate TD to 
provide service  TDX Module + T EE-IO 
provisioning agent 
(TPA)  The trust policy 
enforcer on the host . 
 
Device Attestation  – Evidence Obtaining  and Reporting  
Device evidence obtaining and report ing is done by  the TSM. In Intel ® TDX 1.0/1.5, the TSM is 
a special security manager in tenant TD or a dedicate d TD to provide service . In Intel ® TDX  
Connect , the TSM is the T EE-IO provisioning agent (TPA) which is an extension of  TDX Mod ule. 
For example, t he TPA  may  issue SPDM GET_CERTIFICATE and GET_MEASURMENTS to the 
DSM , to collect the device certificate chain s and measurement s and verify their digital 
signature. Intel TSM  provides a secure mechanism to pass the device certificate chains and 
measurement s to a verifier in the tenant TD.  
Device Attestation – Evidence Verificati on 
The tenant TD may include  a local verifier or communicate with a remote verifier.  
Device Local Verification  
First, t he verifier in the tenant TD should refer to a set of trust anchor s (a root CA certificate or 
an intermediate certificate) to determine whether the DICE certificate chain can be trusted.  It 
should also refer to device certificate revocation lists (CRLs) to ensure that the device 
certificate chain is  not revoked.  Appendix  A: Mapping to Intel® TDX Connect    
43        Document Number:  351998 -003    
Second, the verifier should r efer to  the device reference integrity manifest (RIM) to verif y the 
device measurement  record.  For a DICE device, the verifier should use the measurement data 
in DICE TCB info.  
The reference data could be provisioned in the local tenant TD, or it could be retrieved f rom a 
trusted entity such as cloud orchestrator from the network . 
Device Remote Verification  
The tenant TD may pass the device certificate and measurement to a remote verifier , as 
described in  the Background Check Model.  Later the remote verifier needs to  return the 
verification result to the tenant TD.  
  References    
44        Document Number:  351998 -003    
Standards  
[ISO-SWID ] ISO/IEC 19770 -2:2015 Part 2: Software Identification Tag  
[NIST -800-193] NIST, SP 800 -193: Platform Firmware Resiliency Guidelines , 
https://csrc.nist.gov/publications/sp800   
[NIST -800-155] NIST, SP 800 -155: BIOS Integrity Measurement Guidelines  (draft) , 
https://csrc.nist.gov/ publications/sp800   
[NIST -SWID ] NIST:  Software -Identification -SWID , https://csrc.nist.gov/projects/Software -
Identification -SWID   
[NIST -8060 ] NISTI R 8060  Guidelines for the Creation of Interoperable SWID Tags , 
https://csrc.nist.gov/publications/detail/nistir/8060/final   
[IETF -RATS ] IETF, RATS: Remote Attestation Procedures Architecture, 
[IETF -ATTS ] IETF, RATS: Reference Interaction Models for Remote Attestation  
Procedures , https://datatracker.ietf.org/doc/draft -ietf-rats-reference -interaction -models/   
[IETF -EAT] IETF, RATS: The Entity Attestation Token (EAT) , 
https://datatracker.ietf.org/doc /draft -ietf-rats-eat/

https://datatracker.ietf.org/doc /draft -ietf-rats-eat/   
[IETF -TPM ] IETF, RATS: TPM -based Network Device Remote Integrity Verification , 
https://datatracker.ietf.org/doc/draft -ietf-rats-tpm-based -network -device -attest/  
[IETF -COSWID -EXT] IETF, RATS:  Reference Integrity Measurement Extension for Concise 
[IETF -CORIM ] IETF, RATS: Concise Reference Integrity Manifest  (CoRIM) , 
https://datatracker.ietf.org/doc/draft -ietf-rats-corim/    
[IETF -COS WID] IETF, SACM, Concise Software Identification Tags  (CoSWID) , 
[IETF -TLS] IETF, RFC8446: The Transport Layer Security (TLS) Protocol Version 1.3,  
https://tools.ietf.org/html/rfc8446   
[TCG -TPM2 -KEY] TCG, TPM 2.0 Keys for Device Identity and Attestation , 
https://trustedcomputinggroup.org/resource/tpm -2-0-keys -for-device -identity -and-
attestation/   References    
45        Document Number:  351998 -003    
[TCG -RIMIM ] TCG, Reference Integrity Manifest (RIM) inf ormation Model , 
https://trustedcomputinggroup.org/resource/tcg -reference -integrity -manifest -rim-
information -model/  
[TCG -PCRIM ] TCG, PC Client  Reference Integrity Manifest (RIM) Specification , 
https://trustedcomputinggroup.org/resource/tcg -pc-client -reference -integrity -manifest -
specification/   
[TCG -FIM] TCG, PC Client Platform Firmware Integrity Measurement  (FIM) , 
https://trustedcomputinggroup.org/resource/tcg -pc-client -platform -firmware -integrity -
measurement/   
[TCG -PLAT -CERT ] TCG, PC Client Platform Certificate Profile , 
https://trustedcomputinggroup.org/resource/tcg -platform -certificate -profile/    
[TCG -DICE -LAYERING ] TCG, DICE Layering Architecture, 
[TCG -DICE -ATT S] TCG, DICE Attestation  Architecture, 
https://trustedcomputinggroup.org/resource/dice -attestation -architecture/  
[TCG -DICE -CERT ] TCG, DICE Certificate Profiles, 
https://trustedcomputinggroup.org/re source/dice -certificate -profiles/  
[TCG -DICE -SYM ] TCG, DICE Symmetric Identity Based Device Attestation, 
https://trustedcomputinggroup.org/resource/symme tric-identity -based -device -attestation/   
[TCG -DICE -Endorsement ] TCG, DICE Endorsement Architecture for Devices ,  
https://trustedcomputinggroup.org/resource/dice -endorsement -architecture -for-devices -v1-
0-r0-38/ 
[TCG -TAP -USE ] TCG, Trusted Attestation Protocol (TAP) Use Cases  for TPM 1.2 and 2.0 and 
DICE,  https://trustedcomputinggrou p.org/resource/tcg -trusted -attestation -protocol -tap-use-
cases -for-tpm-families -1-2-and-2-0-and-dice/   
[TCG -EVENT -LOG ] TCG, Canonical Event Log Format, 
https://trustedcom putinggroup.org/resource/canonical -event -log-format/     
[DMTF -0274 ] DMTF, DSP0274: Security Protocol and Data Model (SPDM) Specification,  
https://www.dmtf.org/dsp/DSP0274   
[DMTF -2058 ] DMTF, DSP2058: Security  Protocol and Data Model (SPDM) Architecture 
Whitepaper , https://www.dmtf.org/dsp/DSP2058   
[PCI-PCIE ] PCI,  PCI Express Base 6.0 Specification, https://members.pcisig.com/wg/PCI -
SIG/document/18363   
[PCI-TDISP ] PCI, Trusted  Device Interface Security Protocol ( TDISP ) ECN, 
https://members.pcisig.com/wg/PCI -SIG/document/18255   References    
46        Document Number:  351998 -003    
[CXL-CXL] CXL, CXL 3.0 Specification, https://www.computeexpresslink.org/   
[OCP -SIOV] OCP , Scalable I /O virtualization, https://www.opencompute.org/documents/ocp -
scalable -io-virtualization -technical -specificati on-revision -1-v1-2-pdf   
[INTEL -TDX ] Intel, Intel Trust Domain Extensions (TDX), 
[RISCV -APTEE ] RISCV, RISCV AP TEE, https://github.com/riscv -non-isa/riscv -ap-
tee/blob/main/specification/attestation.adoc   
 
Web Resource s 
[CCC -HWTEE ] Confidential Computing Consortium, Hardware -Based Trusted Execution for 
Applications and Data , https://confidentialcomputing.io/whitepaper -01-latest/   
[CCC -CCDD ] Confidential Computing Consortium, Confidential Computing Deep Dive v1.0, 
https://confide ntialcomputing.io/whitepaper -02-latest/   
[TPM -ATTS ] TPM Remote Attestation Best Known Methods, https://tpm2 -
software.github.io/tpm2 -tss/getting -started/2019/12/18/Remote -Attestation.html  
[ANDROID -ATTS ] Android Key Stone, 
https://source.android.com/security/keystore/attestation   
[RATLS ] Integrating Remote Attestation with Transport Layer Security ( RA-TLS), 
[OPENENCLAVE ] open enclave, https://github.com/openenclave/openenclave   
[OPENENCLAVE -RATLS ] attested TLS, 
https://github.com/openenclave/openenclave/blob/master/samples/attested_tls/AttestedTLS
README.md   
[OPA ] open policy agent (OPA), https://www.openpolicyagent.org/   
[OPA -REGO ] open p olicy language (Rego), 
https://www.openpolicyagent.org/docs/latest/policy -language/   
[INTOTO ] in-toto, https://in -toto.io/   
 
Intel® Trust Domain Extensions (Intel® TDX) Module  
Base Architecture Specification  
 
348549 -003US 
Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 2 of 153 
without notice.  Intel does not guarantee the availability of these interfaces in any future product.  Contact your Intel 
This document contains information on products, services and/or processes in development.  All information provided 15 
  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 3 of 153 
SECTION 1: INTRODUCTION AND OVERVIEW  ................................ ................................ ................................ ...............  11 
1. About this Document  ................................ ................................ ................................ ................................ ...........  12 
1.1. Scope of this Document  ................................ ................................ ................................ ................................ ...... 12 
1.2. Document Organization  ................................ ................................ ................................ ................................ ...... 12 5 
1.3. Glossary ................................ ................................ ................................ ................................ ...............................  13 
1.4. Notation  ................................ ................................ ................................ ................................ ..............................  16 
1.4.1.  Requirement and Definition Commitment Levels  ................................ ................................ ......................  16

1.4.1.  Requirement and Definition Commitment Levels  ................................ ................................ ......................  16 
1.5. References  ................................ ................................ ................................ ................................ ...........................  16 
1.5.1.  Intel Public Documents  ................................ ................................ ................................ ...............................  16 10 
1.5.2.  Intel  TDX Public Documents  ................................ ................................ ................................ ........................  17 
2. Overview of Intel® Trust Domain Extensions ................................ ................................ ................................ ........  18 
2.1. Intel TDX Module Lifecycle  ................................ ................................ ................................ ................................ .. 18 
2.1.1.  Boot -Time Configuration and Intel TDX Module Loading  ................................ ................................ ...........  18 
2.1.2.  Intel TDX Module Initialization, Enumeration and Configuration  ................................ ...............................  18 15 
2.2. Guest TD Life Cycle Overview  ................................ ................................ ................................ ..............................  19 
2.2.1.  Guest TD Build ................................ ................................ ................................ ................................ .............  19 
2.2.2.  Guest TD Execution  ................................ ................................ ................................ ................................ ..... 19 
2.2.3.  Guest TD Management during its Run -Time  ................................ ................................ ...............................  19 
2.3. Intel TDX Operation Modes and Transitions  ................................ ................................ ................................ .......  20 20 
2.4. Guest TD Private Memory Protection  ................................ ................................ ................................ .................  21 
 Memory Encryption  ................................ ................................ ................................ ............................  21 
2.4.2.  Address Translation  ................................ ................................ ................................ ................................ .... 21 
2.5. Guest TD State Protection  ................................ ................................ ................................ ................................ ... 22 
2.6. Intel TDX I/O Model ................................ ................................ ................................ ................................ .............  22 25 
2.7. Measurement and Attestation  ................................ ................................ ................................ ............................  23 
2.8. Intel TDX Managed Control Structures  ................................ ................................ ................................ ...............  23 
2.9. Intel TDX Interface Functions  ................................ ................................ ................................ ..............................  24 
2.9.1.  Host -Side (SEAMCALL Leaf) Interface Functions  ................................ ................................ .........................  24 
2.9.2.  Guest -Side (TDCALL Leaf) Interface Functions  ................................ ................................ ............................  26 30 
3. Software Use Cases  ................................ ................................ ................................ ................................ ..............  28 
3.1. Intel TDX Module Lifecycle  ................................ ................................ ................................ ................................ .. 28 
3.1.1.  Intel TDX Module Platform -Scope First -Time Initialization  ................................ ................................ .........  28 
3.1.2.  Intel TDX Module Shutdown and Update  ................................ ................................ ................................ ... 28 
 Intel TDX Module Reload  ................................ ................................ ................................ ....................  29 35 
 Intel TDX Module Update  ................................ ................................ ................................ ...................  29 
3.2. TD Build  ................................ ................................ ................................ ................................ ...............................  29 
3.3. TD Run Time  ................................ ................................ ................................ ................................ ........................  31 
3.3.1.  Private Memory Management  ................................ ................................ ................................ ....................  31 
 Dynamic Page Addition (Shared to Private Conversion)  ................................ ................................ ..... 31 40 
 Dynamic Page Removal (Private to Shared Conversion)  ................................ ................................ ..... 32 
 Page Promotion (Mapping Merge)  ................................ ................................ ................................ ..... 34 
 Page Demotion (Mapping Split)  ................................ ................................ ................................ ..........  35 
 GPA Range Unblock ................................ ................................ ................................ .............................  36 
3.3.2.  Guest TD Execution  ................................ ................................ ................................ ................................ ..... 37 45 
 TD VCPU First -Time Invocation  ................................ ................................ ................................ ...........  37 
 TD VCPU Entry, Exit on TDG.VP.VMCALL and Re -Entry  ................................ ................................ .......  37 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 4 of 153 
 TD VCPU Entry, Exit on Asynchronous Event and Re -Entry  ................................ ................................  38 
 Guest -Side Functions  ................................ ................................ ................................ ..........................  38 
 TD VCPU Rescheduling (Migration to Another LP)  ................................ ................................ ..............  39 
3.4. TD Destruction  ................................ ................................ ................................ ................................ ....................  40 
SECTION 2: INTEL TDX MODULE ARCHITECTURE SPECIFICATION  ................................ ................................ .................  42 5 
4. Intel TDX Module Lifecycle:  Enumeration, Initialization and Shutdown  ................................ ..............................  43 
4.1. Overview  ................................ ................................ ................................ ................................ .............................  43 
4.1.1.  Intel TDX Module Lifecycle State Machine  ................................ ................................ ................................ . 43 
4.1.2.  Platform Compatibility and Configuration Checking  ................................ ................................ ..................  44 
 Overview  ................................ ................................ ................................ ................................ .............  44 10 
 CPU Configuration  ................................ ................................ ................................ ...............................  44 
 MSR Sampling and Checks  ................................ ................................ ................................ ..................  44 
 CPUID Sampling, Checks and Enumeration  ................................ ................................ .........................  44 
4.1.3.  Physical Memory Configuration Overview ................................ ................................ ................................ .. 44 
 Intel TDX ISA Background:  Convertible Memory Ranges (CMRs)  ................................ ......................  45 15 
 TDMRs and PAMT Arrays Configuration  ................................ ................................ .............................  45 
4.2. Intel TDX Module Initialization Interface  ................................ ................................ ................................ ............  47

MSR Sampling and Checks  ................................ ................................ ................................ ..................  44 
4.2. Intel TDX Module Initialization Interface  ................................ ................................ ................................ ............  47 
4.2.1.  Global Initialization:  TDH.SYS.INIT  ................................ ................................ ................................ .............  47 
4.2.2.  LP-Scope Initialization:  TDH.SYS.LP.INIT  ................................ ................................ ................................ .... 47 
4.2.3.  TDX Module Enumeration:  TDH.SYS.RD/RDALL and TDH.SYS.INFO  ................................ ...........................  47 20 
4.2.4.  TDH.SYS.CONFIG:  TDX Module Global Configuration  ................................ ................................ ................  47 
4.2.5.  TDH.SYS.KEY.CONFIG:  Key Configuration (per Package)  ................................ ................................ ............  48 
4.2.6.  State Restoration after TD -Preserving TDX Module Update:  TDH.SYS.UPDATE  ................................ ........  48 
4.3. TDMR and PAMT Initialization  ................................ ................................ ................................ ............................  48 
4.4. Intel TDX Module Shutdown  ................................ ................................ ................................ ...............................  48 25 
4.4.1.  Shutdown Initiated by the Host VMM (as Part of Module Update)  ................................ ...........................  48 
4.4.2.  Shutdown Initiated by a Fatal Error  ................................ ................................ ................................ ............  49 
4.5. Intel TDX Module Handoff Data  ................................ ................................ ................................ ..........................  49 
5. Memory Encryption Key Management  ................................ ................................ ................................ .................  51 
5.1. Objectives  ................................ ................................ ................................ ................................ ............................  51 30 
5.2. Background:  HKID Space Partitioning  ................................ ................................ ................................ ................  51 
5.3. WBINVD Domains  ................................ ................................ ................................ ................................ ...............  52 
5.4. Key Management Tables  ................................ ................................ ................................ ................................ .... 52 
5.5. Combined Key Management State  ................................ ................................ ................................ .....................  53 
5.6. Key Management Sequences  ................................ ................................ ................................ ..............................  54 35 
5.6.1.  Intel TDX Module Initialization:  Setting an Ephemeral Key and Reserving an HKID for Intel TDX Data  .... 54 
5.6.2.  TD Creation, Keys Assignment and Configuration  ................................ ................................ ......................  54 
5.6.3.  TD Keys Reclamation, TLB and Cache Flush  ................................ ................................ ................................  55 
6. TD Non -Memory State (Metadata) and Control Structures  ................................ ................................ ..................  56 
6.1. Overview  ................................ ................................ ................................ ................................ .............................  56 40 
6.1.1.  Opaque vs. Private vs. Shared Control Structures  ................................ ................................ ......................  56 
6.1.2.  Scope of Control Structures  ................................ ................................ ................................ ........................  56 
6.2. TD-Scope Control Structures  ................................ ................................ ................................ ...............................  56 
6.2.1.  TDR (Trust Domain Root)  ................................ ................................ ................................ ............................  57 
6.2.2.  TDCS  (Trust Domain Control Structure)  ................................ ................................ ................................ ...... 57 45 
6.3. TD VCPU -Scope Control Structures  ................................ ................................ ................................ .....................  57 
6.3.1.  Trust Domain Virtual Processor State (TDVPS)  ................................ ................................ ...........................  57 
 Physical View of TDVPS:  TDVPR/TDCX  ................................ ................................ ...............................  58 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 5 of 153 
 Logical View of TDVPS  ................................ ................................ ................................ .........................  58 
6.3.2.  Non -Protected Control Structures:  Shared EPT and VMCS Auxiliary Control Structures  ..........................  59 
6.4. TD Non -Memory State (Metadata) Access Functions  ................................ ................................ .........................  59 
6.5. Concurrency Restrictions and Enforcement  ................................ ................................ ................................ ........  59 
7. TD Life Cycle Management  ................................ ................................ ................................ ................................ ... 60 5 
7.1. TD Life Cycle State Machine  ................................ ................................ ................................ ................................  60 
7.2. OP_STATE:  TD Operation Secondary -Level State Machine  ................................ ................................ ................  60 
7.3. TD Creation and Configuration Sequence  ................................ ................................ ................................ ...........  61 
7.4. VCPU Creation and Initialization Sequence  ................................ ................................ ................................ .........  62 
7.5. TD Teardown Sequence  ................................ ................................ ................................ ................................ .......  63 10 
8. Physical Memory Management  ................................ ................................ ................................ ...........................  64 
8.1. Trust Domain Memory Region s (TDMRs) and Physical Address Metadata Tables (PAMTs) ...............................  64 
8.2. TDMR Details  ................................ ................................ ................................ ................................ ......................  64 
8.3. PAMT Details  ................................ ................................ ................................ ................................ .......................  64 
8.3.1.  PAMT Entry  ................................ ................................ ................................ ................................ .................  64 15 
8.3.2.  PAMT Blocks and PAMT Arrays  ................................ ................................ ................................ ...................  65 
8.3.3.  PAMT Page Types  ................................ ................................ ................................ ................................ ........  66 
8.3.4.  PAMT Hierarchy  ................................ ................................ ................................ ................................ ..........  66 
8.4. Adding Physical Pages  ................................ ................................ ................................ ................................ .........  67 
8.4.1.  Server Platforms:  Preventing Cache Line Aliasing by Flushing Cache Lines  ................................ ...............  67 20 
8.4.2.  Adding Pages not Mapped to the Guest TD  ................................ ................................ ................................  67 
8.4.3.  Adding Pages and Mapping to the Guest TD’s GPA  ................................ ................................ ....................  67 
8.5. Reclaiming Physical Pages  ................................ ................................ ................................ ................................ .. 67 
8.5.1.  Server Platforms:  Required Cache Flush and Initialization by the Host VMM  ................................ ...........  67 
8.5.2.  Reclaiming Pages not Mapped to the Guest TD’s GPA Space  ................................ ................................ ..... 68 25

8.5.2.  Reclaiming Pages not Mapped to the Guest TD’s GPA Space  ................................ ................................ ..... 68 25 
 Reclaiming TD Pages in TD_TEARDOWN State  ................................ ................................ ...................  68 
8.5.3.  Reclaiming Physical Pages as Part of TD Private Memory Management  ................................ ....................  68 
9. TD Private Memory Management  ................................ ................................ ................................ ........................  69 
9.1. Overview  ................................ ................................ ................................ ................................ .............................  69 
9.2. Secure EPT Entry  ................................ ................................ ................................ ................................ .................  70 30 
9.2.1.  Overview  ................................ ................................ ................................ ................................ .....................  70 
9.2.2.  SEPT Entry State Diagrams  ................................ ................................ ................................ ..........................  71 
9.3. Secure EPT Walk  ................................ ................................ ................................ ................................ ..................  72 
9.4. Secure EPT Induced TD Exits  ................................ ................................ ................................ ................................  72 
9.5. Secure EPT Induced Exceptions  ................................ ................................ ................................ ...........................  73 35 
9.6. Secure EPT Concurrency  ................................ ................................ ................................ ................................ ...... 73 
9.7. Introduction to TLB Tracking  ................................ ................................ ................................ ...............................  74 
9.8. Secure EPT Build and Update:  TDH.MEM.SEPT.ADD  ................................ ................................ ..........................  75 
9.9. Adding TD Private Pages during TD Build Time:  TDH.MEM.PAGE.ADD  ................................ .............................  76 
9.10.  Dynamically Adding TD Private Pages  ................................ ................................ ................................ ............  77 40 
9.10.1.  Overview  ................................ ................................ ................................ ................................ .....................  77 
9.10.2.  PENDING Page Addition by the Host VMM:  TDH.MEM.PAGE.AUG  ................................ ...........................  77 
9.10.3.  PENDING Page Acceptance by the Guest TD:  TDG.MEM.PAGE.ACCEPT  ................................ ....................  78 
 Description  ................................ ................................ ................................ ................................ ..........  78 
 TDG.MEM.PAGE.ACCEPT Concurrency  ................................ ................................ ...............................  80 45 
9.10.4.  Guest TD (L1) Access to a PENDING Page  ................................ ................................ ................................ ... 80 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 6 of 153 
Section 1:  Introduction and Overview  9.11.  Page Merge:  TDH.MEM.PAGE.PROMOTE  ................................ ................................ ................................ ...... 81 
9.12.  Page Split:  TDH.MEM.PAGE.DEMOTE  ................................ ................................ ................................ ............  82 
9.13.  Relocating TD Private Pages:  TDH.MEM.PAGE.RELOCATE  ................................ ................................ ............  84 
9.14.  Removing TD Private Pages:  TDH.MEM.PAGE.REMOVE  ................................ ................................ ................  85 
9.15.  Removing a Secure EPT Page:  TDH.MEM.SEPT.REMOVE  ................................ ................................ ...............  85 5 
9.16.  Unblocking a GPA Range:  TDH.MEM.RANGE.UNBLOCK  ................................ ................................ ................  85 
10. TD VCPU  ................................ ................................ ................................ ................................ ...........................  87 
10.1.  VCPU Transitions  ................................ ................................ ................................ ................................ .............  87 
10.1.1.  Initial TD Entry, Asynchronous TD Exit and Subsequent TD Entry  ................................ ..............................  87 
10.1.2.  Synchronous TD Exit and Subsequent TD Entry  ................................ ................................ ..........................  88 10 
10.1.3.  VCPU Activity State Machine  ................................ ................................ ................................ ......................  88 
10.2.  TD VCPU TLB Address Space Identifier (ASID)  ................................ ................................ ................................ . 90 
10.2.1.  TD ASID Components  ................................ ................................ ................................ ................................ .. 90 
10.2.2.  INVEPT by the Host VMM for Managing the Shared EPT  ................................ ................................ ...........  90 
10.3.  VCPU -to-LP Association  ................................ ................................ ................................ ................................ ... 91 15 
10.3.1.  Non -Coherent Caching  ................................ ................................ ................................ ................................  91 
10.3.2.  Intel TDX Functions for VCPU -LP Association and Dis -Association  ................................ .............................  91 
10.3.3.  Performance Considerations  ................................ ................................ ................................ ......................  91 
11. CPU Virtualization (Non -Root Mode Operation)  ................................ ................................ ...............................  92 
11.1.  Initial State  ................................ ................................ ................................ ................................ ......................  92 20 
11.1.1.  Overview  ................................ ................................ ................................ ................................ .....................  92 
11.1.2.  Initial State of Guest TD GPRs  ................................ ................................ ................................ .....................  92 
11.1.3.  Initial State of CRs  ................................ ................................ ................................ ................................ .......  92 
11.1.4.  Initial State of Segment Registers  ................................ ................................ ................................ ...............  93 
11.1.5.  Initial State of MSRs  ................................ ................................ ................................ ................................ .... 93 25 
11.2.  Guest TD Run Time Environment Enumeration  ................................ ................................ ...............................  93 
11.3.  CPU Mode Restrictions  ................................ ................................ ................................ ................................ .... 94 
11.4.  Instructions Restrictions  ................................ ................................ ................................ ................................ .. 94 
11.4.1.  Unconditionally Blocked Instructions  ................................ ................................ ................................ .........  94 
 Instructions that Cause a #UD Unconditionally  ................................ ................................ ..................  94 30 
 Instructions that Cause a #VE Unconditionally  ................................ ................................ ...................  94 
 Instructions that Cause a #UD or #VE Depending on Feature Enabling  ................................ ..............  95 
 Other Cases of Unconditionally Blocked Instructions  ................................ ................................ .........  95 
11.4.2.  Conditionally Blocked Instructions  ................................ ................................ ................................ .............  95 
11.4.3.  Other Exception Cases  ................................ ................................ ................................ ................................  95 35

Instructions that Cause a #UD Unconditionally  ................................ ................................ ..................  94 30 
11.4.3.  Other Exception Cases  ................................ ................................ ................................ ................................  95 35 
11.5.  Extended Feature Set  ................................ ................................ ................................ ................................ ...... 95 
11.5.1.  Allowed Extended Features Control  ................................ ................................ ................................ ...........  95 
11.5.2.  Extended State Isolation  ................................ ................................ ................................ .............................  95 
11.5.3.  Extended Features Execution Control  ................................ ................................ ................................ .........  95 
11.6.  CR Handling  ................................ ................................ ................................ ................................ .....................  98 40 
11.6.1.  CR0 ................................ ................................ ................................ ................................ ..............................  98 
11.6.2.  CR4 ................................ ................................ ................................ ................................ ..............................  98 
11.7.  MSR Virtualization  ................................ ................................ ................................ ................................ ..........  99 
11.7.1.  Overview  ................................ ................................ ................................ ................................ .....................  99 
11.7.2.  MSR Configuration by the Host VMM  ................................ ................................ ................................ .........  99 45 
11.8.  CPUID Virtualization  ................................ ................................ ................................ ................................ ...... 100 
11.8.1.  CPUID Configuration by the Host VMM  ................................ ................................ ................................ .... 100 
 Fine Grained Control of CPU Extended Features Enumeration  ................................ ........................  100 
 Configurable Family/Model/Stepping (CPUID(1).EAX) Enumeration  ................................ ................  100 
11.8.2.  Guest TD Control of CPUID Virtualization  ................................ ................................ ................................ . 101 50 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 7 of 153 
 Unconditional #VE for all CPUID Leaves and Sub -Leaves  ................................ ................................ .. 101 
 CPUID Leaf/Sub -leaf Specific Control  ................................ ................................ ................................  101 
11.8.3.  CPUID Configuration & Checks at Guest TD Migration  ................................ ................................ .............  101 
11.9.  Interrupt Handling and APIC Virtualization ................................ ................................ ................................ ... 102 
11.9.1.  Virtual APIC Mode  ................................ ................................ ................................ ................................ ..... 102 5 
11.9.2.  Virtual APIC Access by Guest TD  ................................ ................................ ................................ ...............  102 
11.9.3.  Implicit APIC Write #VE  ................................ ................................ ................................ .............................  103 
11.9.4.  Posted Interrupts  ................................ ................................ ................................ ................................ ...... 103 
11.9.5.  Pending Virtual Interrupt Delivery Indication  ................................ ................................ ...........................  104 
11.9.6.  Cross -TD-VCPU IPI  ................................ ................................ ................................ ................................ ..... 105 10 
11.9.7.  Virtual NMI Injection  ................................ ................................ ................................ ................................ . 105 
11.10.  Virtualization Exception (#VE)  ................................ ................................ ................................ .......................  105 
11.10.1.  Virtualization Exception Information  ................................ ................................ ................................ .... 105 
11.10.2.  #VE Injection by the CPU due to EPT Violations  ................................ ................................ ...................  106 
11.10.3.  #VE Injected by the Intel TDX Module  ................................ ................................ ................................ .. 106 15 
11.11.  GPA Space, Secure and Shared Extended Page Tables (EPTs)  ................................ ................................ .......  106 
11.11.1.  GPAW -Relate EPT Violations  ................................ ................................ ................................ .................  107 
11.11.2.  EPT Violation Mutated into #VE  ................................ ................................ ................................ ............  107 
11.12.  Prevention of TD -Induced Denial of Service  ................................ ................................ ................................ .. 107 
11.12.1.  Bus Lock Detection by the TD OS  ................................ ................................ ................................ ..........  107 20 
11.12.2.  Impact of MSR_MEMORY _CTRL (MSR 0x33)  ................................ ................................ ........................  107 
11.12.3.  Bus Lock TD Exit  ................................ ................................ ................................ ................................ .... 107 
11.12.4.  Instruction Timeout TD Exit  ................................ ................................ ................................ ..................  108 
11.13.  Time Stamp Counter (TSC)  ................................ ................................ ................................ ............................  108 
11.13.1.  TSC Virtualization  ................................ ................................ ................................ ................................ .. 108 25 
11.13.2.  TSC Deadline  ................................ ................................ ................................ ................................ .........  108 
11.14.  Supervisor Protection Keys (PKS)  ................................ ................................ ................................ ...................  109 
11.15.  Intel ® Total Memory Encryption (Intel ® TME) and Multi -Key Total Memory Encryption (MKTME)  ..............  109 
11.15.1.  TME Virtualization  ................................ ................................ ................................ ................................ . 109 
11.15.2.  MKTME Virtualization  ................................ ................................ ................................ ...........................  109 30 
11.16.  Virtualization of Machine Check Capabilities and Controls  ................................ ................................ ..........  109 
11.17.  Transactional Synchronization Extensions (TSX)  ................................ ................................ ...........................  110 
11.18.  Management of Idle and Blocked Conditions  ................................ ................................ ...............................  110 
11.18.1.  HLT Instruction  ................................ ................................ ................................ ................................ ...... 110 
11.18.2.  PAUSE Instruction and PAUSE -Loop Exiting  ................................ ................................ ..........................  110 35 
11.18.3.  MONITOR and MWAIT Instructions  ................................ ................................ ................................ ...... 111 
11.18.4.  WAITPKG:  TPAUSE, UMONITOR and UMWAIT Instructions  ................................ ................................  111 
11.19.  Other Changes in SEAM Non -Root Mode  ................................ ................................ ................................ ...... 111 
11.19.1.  CET ................................ ................................ ................................ ................................ ........................  111 
11.19.2.  Tasking  ................................ ................................ ................................ ................................ ..................  111 40

11.19.2.  Tasking  ................................ ................................ ................................ ................................ ..................  111 40 
12. Measurement and Attestation  ................................ ................................ ................................ .......................  112 
12.1.  TD Measurement  ................................ ................................ ................................ ................................ ..........  112 
12.1.1.  MRTD:  Build -Time Measurement Register  ................................ ................................ ..............................  112 
12.1.2.  RTMR:  Run -Time Measurement Registers  ................................ ................................ ...............................  112 
12.2.  TD Measurement Reporting  ................................ ................................ ................................ ..........................  112 45 
12.3.  Local Report Verification  ................................ ................................ ................................ ...............................  113 
12.4.  Creating Attestations  ................................ ................................ ................................ ................................ .... 114 
12.4.1.  Overview  ................................ ................................ ................................ ................................ ...................  114 
12.4.2.  Intel SGX -Based Attestation  ................................ ................................ ................................ ......................  114 
 Quote Signing Key for SGX -Based Attestation  ................................ ................................ ..................  115 50 
12.5.  TCB Recovery  ................................ ................................ ................................ ................................ .................  115 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 8 of 153 
Section 1:  Introduction and Overview  12.5.1.  TD Preserving TDX Module Update Implications  ................................ ................................ ......................  115 
13. Service TDs  ................................ ................................ ................................ ................................ .....................  116 
13.1.  Overview  ................................ ................................ ................................ ................................ .......................  116 
13.2.  Service TD Binding  ................................ ................................ ................................ ................................ .........  116 
13.2.1.  Service TD Binding Table in the Target TD’s TDCS  ................................ ................................ ....................  116 5 
13.2.2.  SERVTD_BINDING_STATE:  Service TD Binding State  ................................ ................................ ................  117 
13.2.3.  SERVTD_TYPE:  Service TD Binding Type  ................................ ................................ ................................ ... 117 
13.2.4.  SERVTD_ATTR:  Service TD Binding Attributes  ................................ ................................ ..........................  117 
 INSTANCE_BINDING:  Class vs. Instance Binding  ................................ ................................ ..............  117 
 MIGRATABLE_BINDING:  Binding Migratability  ................................ ................................ ................  117 10 
 IGNORE_TDINFO:  TDINFO Component Filtering  ................................ ................................ ..............  118 
13.2.5.  SERVTD_UUID:  Service TD Instance Identifier  ................................ ................................ .........................  118 
13.2.6.  Service TD’s Binding SERVTD_INFO_HASH Calculation  ................................ ................................ .............  118 
13.2.7.  Target TD’s SERVTD_HASH Calculation  ................................ ................................ ................................ ..... 118 
 SERVTD_HASH Calculation on Finalization of TD Build  ................................ ................................ ..... 119 15 
 SERVTD_HASH Calculation on TD Import  ................................ ................................ ..........................  119 
 SERVTD_HASH Calculation Method  ................................ ................................ ................................ .. 119 
13.2.8.  TDH.SERVTD.PREBIND:  Pre -Binding a Service TD ................................ ................................ .....................  119 
13.2.9.  TDH.SERVTD.BIND:  Binding a Service TD  ................................ ................................ ................................ . 120 
13.2.10.  Binding Handle  ................................ ................................ ................................ ................................ ...... 120 20 
13.3.  Target TD Metadata Access by a Service TD  ................................ ................................ ................................ . 120 
13.3.1.  TDG.SERVTD.RD/WR:  Metadata Read/Write Interface Functions  ................................ ...........................  120 
13.3.2.  Metadata Access Error Handling  ................................ ................................ ................................ ...............  121 
13.3.3.  Cross -TD Concurrency Handling:  Maintaining Host -Side Priority  ................................ ............................  121 
 Problem Description  ................................ ................................ ................................ .........................  121 25 
 Solution  ................................ ................................ ................................ ................................ .............  122 
14. I/O Support (without TDX Connect)  ................................ ................................ ................................ ...............  123 
14.1.  Overview  ................................ ................................ ................................ ................................ .......................  123 
14.2.  Paravirtualized I/O  ................................ ................................ ................................ ................................ ........  123 
14.3.  MMIO Emulation and Emulated Devices  ................................ ................................ ................................ ...... 123 30 
14.4.  Direct Device Assignment (DDA) and SRIOV  ................................ ................................ ................................ . 123 
14.5.  IOMMU – DMA Remapping  ................................ ................................ ................................ ..........................  123 
14.6.  Shared Virtual Memory (SVM)  ................................ ................................ ................................ ......................  124 
15. Debug and Profiling Architecture  ................................ ................................ ................................ ...................  125 
15.1.  On-TD Debug  ................................ ................................ ................................ ................................ .................  125 35 
15.1.1.  Overview  ................................ ................................ ................................ ................................ ...................  125 
15.1.2.  Generic Debug Handling  ................................ ................................ ................................ ...........................  125 
 Context Switch  ................................ ................................ ................................ ................................ .. 125 
 IA32_DEBUGCTL MSR Virtualization  ................................ ................................ ................................ . 125 
15.1.3.  Debug Feature -Specific Handling  ................................ ................................ ................................ ..............  126 40 
15.2.  On-TD Performance Monitoring  ................................ ................................ ................................ ...................  127 
15.2.1.  Overview  ................................ ................................ ................................ ................................ ...................  127 
15.2.2.  Performance Monitoring CPUID Virtualization  ................................ ................................ .........................  127 
15.2.3.  Performance Monitoring MSRs  ................................ ................................ ................................ ................  128 
 Overview  ................................ ................................ ................................ ................................ ...........  128 45

 Overview  ................................ ................................ ................................ ................................ ...........  128 45 
15.2.4.  Performance Monitoring Interrupts (PMIs)  ................................ ................................ ..............................  128 
15.3.  Off-TD Debug  ................................ ................................ ................................ ................................ ................  129 
15.3.1.  Modifying Debuggable TD’s State, Controls and Memory  ................................ ................................ ........  129 
15.3.2.  Preventing Guest TD Corruption of DRs ................................ ................................ ................................ .... 130 
15.4.  Uncore Performance Monitoring Interrupts (Uncore PMIs)  ................................ ................................ ..........  130 50 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 9 of 153 
Section 1:  Introduction and Overview  16. Memory Integrity Protection and Machine Check Handling  ................................ ................................ ...........  131 
16.1.  Overview  ................................ ................................ ................................ ................................ .......................  131 
16.2.  TDX Memory Integrity Protection Background  ................................ ................................ .............................  131 
16.2.1.  Server Platforms Memory Integrity Protection  ................................ ................................ ........................  131 
 Server Platforms:  Cryptographic Integrity (Ci) vs. Logical Integrity (Li), MAC and TD Owner  ..........  131 5 
 Server Platforms:  MAC and TD Owner Update on Memory Writes  ................................ .................  132 
 Server Platforms Memory Reads:  Integrity and TD Owner Bit Checks, Poison Generation and Poison 
Consumption  ................................ ................................ ................................ ................................ .........................  132 
16.2.2.  Server Platforms Memory Writes:  No Integrity nor TD Owner Bit Checks  ................................ ..............  133 
16.2.3.  Memory Integrity Error Logging, Machine Checks and Unbreakable Shutdowns  ................................ .... 134 10 
16.3.  Machine Check Architecture (MCA) Background  ................................ ................................ ..........................  134 
16.3.1.  Uncorrected Machine Check Error ................................ ................................ ................................ ............  134 
16.3.2.  Corrected Machine Check Interrupt (CMCI)  ................................ ................................ .............................  134 
16.3.3.  Machine Check System Management Interrupt (MSMI)  ................................ ................................ ..........  134 
16.3.4.  Local Machine Check Event (LMCE)  ................................ ................................ ................................ ..........  135 15 
16.4.  Recommended MCA Platform Configuration for TDX  ................................ ................................ ...................  135 
16.5.  Handling Machine Check Events during Guest TD Operation  ................................ ................................ .......  135 
16.5.1.  Machine Check Events Delivered as an #MC Exception (Recommended)  ................................ ................  135 
16.5.2.  Machine Check Events Delivered as an MSMI (Not Recommended)  ................................ .......................  136 
16.5.3.  LMCE Disabled (Not Recommended)  ................................ ................................ ................................ ........  137 20 
16.5.4.  Machine Check Events Delivered as a CMCI  ................................ ................................ .............................  137 
16.6.  Handling MCE during Intel TDX Module Operation  ................................ ................................ ......................  137 
17. Side Channel Attack Mitigation Mechanisms  ................................ ................................ ................................ . 138 
17.1.  Checking and Virtualization of CPU Side Channel Protection Mechanisms Enumeration  .............................  138 
17.1.1.  IA32_ARCH_CAPABILITIES MSR  ................................ ................................ ................................ ................  138 25 
17.1.2.  CPUID  ................................ ................................ ................................ ................................ ........................  139 
17.2.  Branch Prediction Side Channel Attacks Mitigation Mechanisms  ................................ ................................  139 
17.3.  Single -Step and Zero -Step Attacks Mitigation Mechanisms  ................................ ................................ .........  140 
17.3.1.  Description  ................................ ................................ ................................ ................................ ................  140 
17.3.2.  Host VMM Expected Behavior  ................................ ................................ ................................ ..................  140 30 
17.3.3.  Guest TD Interface and Expected Guest TD Operation  ................................ ................................ .............  140 
18. General Aspects of the Intel TDX Interface Functions  ................................ ................................ .....................  142 
18.1.  Concurrency Restrictions and Enforcement  ................................ ................................ ................................ .. 142 
18.1.1.  Explicit Concurrency Restrictions  ................................ ................................ ................................ ..............  142 
18.1.2.  Implicit Concurrency Restrictions  ................................ ................................ ................................ .............  142 35 
18.1.3.  Transactions  ................................ ................................ ................................ ................................ ..............  143 
18.1.4.  Concurrency Restrictions with Host Priority  ................................ ................................ .............................  143 
 Overview  ................................ ................................ ................................ ................................ ...........  143 
 Host -Side (SEAMCALL) Operation  ................................ ................................ ................................ ..... 143 
 Guest -Side (TDCALL) Operation  ................................ ................................ ................................ ........  143 40 
 Host Priority Busy Timeout  ................................ ................................ ................................ ...............  143 
18.2.  Memory and Resource Operands Access  ................................ ................................ ................................ ...... 144 
18.2.1.  Overview  ................................ ................................ ................................ ................................ ...................  144 
 Access Semantics  ................................ ................................ ................................ ..............................  144 
 Explicit vs. Implicit Access  ................................ ................................ ................................ .................  144 45 
 Memory Operand Address Specification  ................................ ................................ ..........................  145 
 Memory Type  ................................ ................................ ................................ ................................ .... 145 
 Actual Memory Access vs. Memory Reference ................................ ................................ .................  145 
 Summary Table  ................................ ................................ ................................ ................................ . 146 
18.3.  Register Operands and CPU State Convention  ................................ ................................ ..............................  146 50 
18.3.1.  Overview:  Regular vs. Transition Leaf Functions  ................................ ................................ .....................  146 
18.3.2.  Interface Function Leaf and Version Numbers  ................................ ................................ .........................  146 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 10 of 153

Actual Memory Access vs. Memory Reference ................................ ................................ .................  145 
November 2023   . Page 10 of 153 
Section 1:  Introduction and Overview  18.3.3.  CPU State Preservation Convention ................................ ................................ ................................ ..........  147 
 TDH.VP.ENTER  ................................ ................................ ................................ ................................ ... 147 
 Other Interface Functions  ................................ ................................ ................................ .................  147 
18.3.4.  Transition Cases:  TD Entry and Exit  ................................ ................................ ................................ ..........  147 
 TD Entry: TDH.VP.ENTER  ................................ ................................ ................................ ...................  147 5 
 TD Synchronous Exit:  TDG.VP.VMCALL  ................................ ................................ ............................  148 
18.4.  Interface Function Completion Status  ................................ ................................ ................................ ...........  148 
18.4.1.  Least Detailed Level:  Success/Warning/Error  ................................ ................................ ..........................  148 
18.4.2.  Medium Detailed Level:  Class, Recoverability and Fatality  ................................ ................................ ...... 148 
18.4.3.  Most Detailed Level  ................................ ................................ ................................ ................................ .. 149 10 
18.5.  TD, VM and VCPU Identification  ................................ ................................ ................................ ...................  149 
18.6.  Metadata Access Interface  ................................ ................................ ................................ ...........................  149 
18.6.1.  Introduction  ................................ ................................ ................................ ................................ ..............  149 
18.6.2.  Metadata Fields and Elements  ................................ ................................ ................................ .................  150 
18.6.3.  Arrays of Metadata Fields  ................................ ................................ ................................ .........................  150 15 
18.6.4.  Metadata Field Sequences  ................................ ................................ ................................ ........................  151 
18.6.5.  Metadata Lists  ................................ ................................ ................................ ................................ ...........  152 
18.7.  Latency of the Intel TDX Interface Functions  ................................ ................................ ................................  153 
18.8.  DRNG Entropy Errors  ................................ ................................ ................................ ................................ ..... 153 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 11 of 153 
 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 12 of 153 
This document describes the architecture of the Intel ® Trust Domain Extensions  (Intel ® TDX) module , implemented using  
the Intel TDX Instruction Set Architecture (ISA) extension s, for confidential execution of Trust Domains in an untrusted 
hosted cloud environment . 5 
 TDX Module  
 TDX Module  
 TDX Module  
 TDX Module  
 TDX Module  
 
This document is a work in progress and is subject to change based on customer feedback and internal analysis.  This 
occur.  
The document has the following  main sections:  
• Section 1 contains an introduction to the document and an overview of the Intel TDX module . 
• Section 2 contains the Intel TDX module  architecture specification.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 13 of 153 
Table 1.2:  Intel TDX Glossary  
for 
ABI Application 
Binary 
Interface  No A programming interface defined at the binary level (i.e., instruction opcode and 
CPU registers ).  The Intel TDX module  interface is specified as an ABI.  
ACM  Authenticated 
Code Module  No A code module that is designed to be loaded, verified and executed by the CPU i n 
on-chip memory (CRAM).  
N/A  Accessible 
(Memory)  No Memory whose content is readable and/or writeable (e.g., TD private memory is 
accessible to the guest TD).  
N/A  Addressable 
(Memory)  No Memory that can be referred to by its address.  The content of addressable 
memory might  not necessar ily be accessible (e.g., TDCS is not accessible to the 
host VMM).  
CMR  Convertible 
Memory Range  Yes A range of physical memory  configured b y BIOS and verified by MCHECK .  MCHECK 
verification is intended to help ensure that a CMR may  be used to hold TDX 
memory pages encrypted with a private HKID .   
N/A  Enlightened  
OS No A TD OS is considered enlightened if it is aware that  it is running as a TD (see 
Paravirtualization).  
EPxE  Extended 
Paging 
Structures 
Cache  No The CPU’s cache of EPT intermediate translations (as opposed to TLB, which 
caches full LA or GPA to HPA translations).  
GPA  Guest Physical 
Address  No An address viewed  as a physical address , from a guest VM’s point of view.  A GPA 
is subject to further translation (by EPT) to produce an HPA.  
N/A  Hidden  No A resource or a data structure that is not directly addressable by software (except 
the Intel TDX module ). 
HKID  Host Key ID Yes When MKTME  is activated, HKID is a key identifier for an encryption key used by 
one or more memory controller s on the platform.  
N/A  Host VMM  Yes The VMM that serves as a host to guest TDs.  The term “host” is used to 
differentiate between the “host VMM”  and future VMMs that may be nested 
within TDs.  
HPA  Host Physical 
Address  No A physical address at the host VMM level.  This is the actual physical address used 
by the hardware (e.g., caches).   See also PA.  
KD Key Domain  Yes Represents the control state associated with an ephemeral TDX key  resource .  Key 
domains are managed as a resource by the host VMM with the security attributes 
of the lifecycle of a key domain for Trust Domains (TDs) is enforced by the Intel 
TDX Module .  A TD is assigned to a single Key Domain.  
KET Key Encryption 
Table  Yes A table held by each MKTME  encryption engine , intended  for holding encryption 
key information , indexed by HKID.  
KOT  Key Ownership

KOT  Key Ownership 
Table  Yes An internal, hidden  table held by the Intel TDX module , intended  for controlling 
the assignment of HKIDs to TDs.  
MBZ  Must Be Zero  No Normally used to indicate that reserved fields must contain 0.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 14 of 153 
Section 1:  Introduction and Overview  Acronym  Full Name  New 
for 
MKTME  Multi -Key TME  No This SoC capability adds support to the TME to allow software to use  one or more  
separate keys for encryption of volatile or persistent memory encryption.  When 
used with TDX,  it can provide confidentiality via separate keys for memory used  by 
TDs.  MKTME  can be used with and without TDX  extensions.1 
MRTD  Measurement 
of Trust 
Domain  Yes The SHA -384 measurement of a TD accumulated during TD build.  
NP-
SEAMLDR  Non -Persistent 
SEAM Loader  Yes An ACM intended to load an Intel P -SEAMLDR module into the SEAM range.  
P-
SEAMLDR  Persistent 
SEAM Loader  Yes A SEAM module intended to install (load or update) Intel TDX modules into SEAM 
range.  
PA Physical 
Address  No The physical address used by the hardware (e.g., caches).  See also HPA.  
PAMT  Physical 
Address 
Metadata 
Table  Yes An internal, hidden data structure used by the Intel TDX module , which is intended  
to hold the metadata of physical pages.  
PV Para -
Virtualization  No A virtualization technique where the VM can be  aware it is being virtualized (as 
opposed to running directly on hardware ). 
RTMR  Run -Time 
Measurement 
Register  Yes A SHA -384 measurement register that can be updated during TD run-time.  
SEAM  Secure 
Arbitration 
Mode  Yes See TDX ISA.  
SEAMRR  SEAM Range 
Register  Yes A range register used by the BIOS to help configure the SEAM memory range, 
where the Intel TDX  module is loaded and executed.  
Service 
TD Service TD  Yes A Trust Domain (TD) VM used to provide a dedicated service/utility.  Extends the 
TCB of the tenant TD it provides the service to.  Migration TD (MigTD) is an 
example Service TD.  
SEPT  Secure EPT  Yes An Extended Page Table for GPA -to-HPA translation of TD private HPA.  A Secure 
EPT is designed to be encrypted with the TD’s ephemeral private key.  SEPT pages 
are allocated by the host VMM via Intel TDX functions, but their content is  
intended to be  hidden and is not architectural.  
Intel®  
SGX  Intel®  
Software 
Guard 
Extensions  No An Intel CPU mode and ISA extension s that support operation and man agement of 
Intel®  SGX enclaves . 
SoC System on 
Chip  No A whole system, including cores, uncore, interconnects etc., packaged as a single 
device.  
 
1 In this document, the term “MK -TME” is used to mean both the feature and the encryption engine itself.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 15 of 153 
for 
SPA System 
Physical 
TD Trust Domain  Yes Trust Domains (TDs) are designed to be hardware isolated Virtual Machines ( VMs ) 
deployed using Intel® Trust Domain Extensions (Intel® TDX) . 
TD OS  Trust Domain 
Operating 
System  Yes The guest operating system that runs in  a TD.  
TD VM  TD Virtual 
Machine  Yes Same as TD  
N/A  TD Private 
Memory 
(Access)  Yes TD Private Memory is designed to hold TD private content, encrypted by the CPU 
using the TD ephemeral key . 
N/A  TD Shared 
Memory 
(Access)  Yes TD Shared memory is designed to hold content accessible to the TD and the host 
software (and/or other TDs) .  TD shared memory may be  encrypted using MKTME  
keys managed by the VMM.  
Control 
Structure  Yes Multi -page control structure for a TD.  TDCS pages are allocated by the host VMM 
via Intel TDX  functions, but their content is intended to be non-architectural  and 
not directly accessible to software.  
TDCX  Trust Domain 
Control 
Extension  Yes 4KB physical pages that are intended to hold parts of  a multi -page control 
TDR  Trust Domain 
Root  Yes The r oot control structure for a TD.  The TDR page is allocated by the host VMM 
via Intel TDX  functions, but its content is intended to be non -architectural  and not 
directly accessible to software.  
TDMR  Trust Domain 
Memory Range  Yes A range of memory, configured by the host VMM, that is covered by PAMT and is 
intended  to hold TD private memory and TD control structures.  
TDVPS  Trust Domain 
Virtual 
Processor 
State  Yes A multi-page s tructure for holding a TD Virtua l CPU (VCPU) state.  TDVPS pages are 
allocated  by the host VMM  via Intel TDX  functions, but their content is intended to 
be non -architectural  and not directly accessible to software.  
TDVPR  Trust Domain 
Virtual 
Processor Root  Yes A 4KB physical page that is intended to be the root (first) page of a TDVPS.  
Intel®  
TDX  Intel®  Trust 
Domain 
Extensions  Yes An architecture, based on the TDX Instruction Set Architecture (ISA) extensions 
and the Intel TDX module , which support s operation and man agement of Trust 
Domains . 
TDX ISA  Intel®  TDX 
Architecture  Yes Intel CPU Instruction Set Architecture (ISA) extension s that support the Intel TDX 
module: an isolated software module that facilitates the operation and 
man agement of Trust Domains . 
TEE Trusted 
Execution 
Environment  No An isolated processing environment in which software  can be securely executed 
irrespective of the rest of the system . Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 16 of 153 
for 
TME  Intel®  Total 
Memory 
Encryption  No A memory encryption/decryption engine using an ephemeral platform key 
designed to encrypt memory contents exposed externally from the SOC .  
N/A  WBINVD 
Domain  No A set of LPs for which a single WBINVD or WBNOINVD instruction, and the 
TDH.PHYMEM.CACHE.WB and TDH.SYS.CACHE.WB interface function s, apply . 
XFAM  Extended 
Features 
Allowed Mask  Yes A mask of CPU extended features (in XCR0 format) that the TD is allowed to use.  
This section describes the notation used in this document.  
1.4.1.  Requirement and Definition Commitment Levels  
When specifying requirements or definitions, the level of commitment is specified following the convention of RFC 2119:  
Key words for use in RFCs to indicate Requirement Levels , as described in the following table:  5 
Table 1.3:  Requirement and Definition Commitment Levels  
Must  “Must ”, "Required " or " Shall " mean s that the definition is an absolute requirement of the 
Must Not  “Must Not ” or "Shall Not " mean s that the definition is an absolute prohibition of the 
Should  “Should ”, or the adjective " Recommended ", mean s that there may exist valid reasons in 
particular circumstances to ignore a particular item, but the full implications must be 
understood and carefully weighed before choosing a different course.  
Should Not  “Should Not ”, or the phrase " Not Recommended " mean s that there may exist valid reasons in 
particular circumstances when the particular behavior is acceptable or even useful, but the full 
implications should be understood,  and the case must be carefully weighed before 
implementing any behavior described with this label.  
May  “May ”, or the adjective " Optional ", mean s that an item is discretionary .  An implementation 
may choose to include the item , while another may omit the same item, because of various 
reasons.  
 
Table 1.4:  Intel Public Documents  10 
Intel SDM  Intel® 64 and IA -32 Architectures  
Software Developer’s Manual  325462 -078US, 
December 202 2 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 17 of 153 
Section 1:  Introduction and Overview  Reference  Document  Version & Date  
ISA Extensions  Intel® Architecture  
Instruction Set Extensions and Future Features  
Programming Reference  319433 -047, 
December  2022 
Error Reporting 
through EMCA2  RAS Integration and Validation Guide fo r the Intel Xeon 
Processor – Error Reporting through EMCA Gen 2  April 2015  
Key Locker Spec  Intel Key Locker Specification   Sept 2020  
FRED  Flexible Return and Event Delivery (FRED)   May 2022  
 
Table 1.5:  Intel TDX Public Documents  
TDX Web Page  Intel® Trust Domain Extensions (Intel® TDX)  
Note:   Most documents below are on this web page   
TDX Overview  An introductory overview of the Intel TDX technology  February 2023  
TDX  Arch Extensions

TDX  Arch Extensions  
Spec  A specification of Intel CPU architectural support for Intel TDX  May 2021  
TDX Loader  Spec  A specification of how a VMM loads the Intel TDX Module on a 
platform  March 2022  
MKTMEi Spec  Intel® Architecture Memory Integrity Specification  Rev. 1.0, March 2020  
TDX Module Base 
Spec  Overview and base architecture specification of the Intel TDX 
Module version 1.5  March 2023  
TD Migration Spec  Overview and architecture specification of the TD Migration 
feature of the Intel TDX Module version 1.5  March 2023  
TD Partitioning Spec  Overview and Architecture Specification for TD partitioning of 
the TDX Module version 1.5   March 2023  
TDX Module ABI 
Spec  Application Binary Interface (ABI) specification of the Intel TDX 
Incompatibilities  Description of the incompatibilities between TDX 1.0 and TDX 
1.4/1.5 that may impact the host VMM and/or guest TDs  March 2023  
TDX GHCI Spec  Specification of the software interface between the Guest OS 
(Tenant and Service TD VMs) and the VMM required for 
enabling Intel TDX version 1.5  July 2022  
MigTD Design Guide  A design guide on how to design and implement a Migration 
TD for TDX 1.5 Live migration  October 2021  
TDX Developers 
Guide  Intel® TDX Guidance for Developers  March 2023  
TDX Guest Kernel 
Hardening  Intel® TDX Guest Kernel Hardening Documentation  March 2023  
November 2023   . Page 18 of 153 
Section 1:  Introduction and Overview  2. Overview of  Intel®  Trust Domain Extensions  
Intel®  Trust Domain Extensions ( Intel®  TDX)  refers to an Intel technology that extends Virtual Machines Extensions (VMX)  
and Multi -Key Total Memory Encryption (MKTME)  with a new kind of virtual machine guest called  a Trust Domain (TD) .  
A TD  runs in a CPU mode that is designed to protect the confidentiality of its memory contents and its CPU state from 
any other software, including the hosting Virtual Machine Monitor (VMM), unless explicitly shared by the TD itself.  5 
The TDX solution is built using a combination of Intel ® Virtual Machine Extensions (VMX) and Multi -Key Total Memory 
Encryption (MK -TME), as extended by the Intel®  Trust Domain Extensions Instruction Set Architecture ( Intel TDX ISA) .  
An attested software module called the Intel TDX module  is designed to implement the TDX architecture.  
The platform is managed by a  TDX-aware host VMM .  As shown in Figure 2.1 below , a host VMM can launch and manage 
both guest TDs and legacy guest  VMs .  The host  VMM maintains all legacy functionality  from  the legacy  VMs’ perspective ; 10 
it is restricted only wit h regard to the TDs it manages . 
5TDX-Aware Host VMMHost VMM managed access 
control, enhanced with MK -TMEIntel TDX module managed access control,  
leveraging MK-TME and Secure EPT
TDX-
Drivers
Intel TDX
Host-Side
TDX-
Drivers
Intel TDX
Guest -Side InterfaceLegacy VM
Drivers
Guest -Side Interface
 
Figure 2.1:  Intel ® Trust Domain Extension Components  Overview  
2.1. Intel TDX Module  Lifecycle  
2.1.1.  Boot -Time  Configuration  and Intel TDX Module  Loading  15 
1. BIOS should activate MKTME with TDX private key IDs, configure the SEAMRR registers and prepares a table of 
Convertible Memory Regions (CMRs)  – memory regions that can hold TD -private memory pages.  
2. BIOS or OS should then install P -SEAMLDR by launching the NP -SEAMLDR ACM.  
3. BIOS or OS can retrieve the trusted platform topology and CMR information, as previously checked by MCHECK, using 
P-SEAMLDR’s SEAMINFO API .  Based on the above, the host VMM should then decide on a set of Trust Domain 20 
Memory Regions (TDMRs).  TDMR is a region of convertible memory that may contain some reserved sub -regions.  
4. The host VMM can then load the Intel TDX module using P -SEAMLDR’s INSTALL API.  
2.1.2.  Intel TDX Module  Initialization, Enumeration and Configuration  
1. After loading the Intel TDX module , the host VMM should call the TDH.SYS. INIT function to globally initialize the 
module.  25 
2. The host VMM should then call the TDH.SYS.LP.INIT  function on each logical processor.  TDH.SYS.LP.INIT  is intended 
to initialize the module within the scope  of the Logical Processor (LP).  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 19 of 153 
Section 1:  Introduction and Overview  3. The host VMM should t hen call the TDH.SYS.RD/RD ALL or TDH.SYS. INFO function to enumerate the Intel TDX module  
functionality and parameters ; it should  retrieve the trusted platform topology and CMR information as previously 
checked  by MCHECK.  
4. The host VMM should then call the TDH.SYS.RD/RDALL or TDH .SYS.INFO function to enumerate the Intel TDX module 
functionality and parameters.  If not done already, the host VMM can retrieve the trusted platform topology and 5 
CMR information , as previously checked by MCHECK, and decide on the set of TDMRs . 
5. The host VMM should then call the TDH.SYS. CONFIG function and pass TDMR information with other configuration 
information.  TDH.SYS. CONFIG is intended to check  the configuration information vs. the Intel TDX module’s  trusted 
internal data.  
6. The host VMM should then call the TDH.SYS.KEY.CONFIG  function per package.  TDH.SYS.KEY.CONFIG  is intended to 10 
configure a CPU -generated random key that is used as the Intel TDX module ’s global private key.  
7. The host VMM should then use the TDH.SYS.TDMR.INIT  function to initialize the TDMRs and their associated control 
The Intel TDX module  lifecycle is detailed in Chapter  4. 
2.2. Guest TD Life Cycle  Overview  15 
2.2.1.  Guest TD Build  
The host VMM  can create a new guest TD by allocating and initializing a TD Root (TDR) control structure using the 
TDH.MNG.CREATE  function.  As an input to TDH.MNG.CREATE , the host VMM  assigns the TD with a memory protection 
key identifier, also known as  a Host Key ID (HKID).  The HKID can be used by the CPU to tag memory accesses done by the 
TD and by the multi -key total memory encryption engine s (MKTMEs ) to select the encryption/decryption keys – the keys 20 
themselves are designed to not be exposed to the host VMM .  The VMM should then program  the HKID and encryption 
key into the MKTME encryption engines  using the TDH.MNG.KEY.CONFIG  function on each package . 
Once the TD is assigned a key, the host VMM  can build the TD Control Structure (TDCS) by adding control structure  pages, 
using the TDH.MNG.ADDCX  function, and initialize using the TDH.MNG.INIT  function.  It can then build the Secure EPT 
tree using the TDH.MEM.SEPT.ADD  function and add  the initial set of TD-private pages  using the TDH.MEM.PAGE.ADD  25 
function .  These pages typically contain Virtual BIOS  code and data along with some clear pages for stacks and heap.   
Most of the guest TD code and data is dynamically loaded at a later stage.   The guest TD can extend  run-time 
measurement registers, designed to be securely maintained by the Intel TDX module , for the added contents using the 
TDH.MR.EXTEND  function.  
The host VMM  can then create and initialize TD Virtual CPUs (VCPUs).  After creating each VCPU using the TDH.VP.CREATE  30 
function, the VMM allocates a set of pages to hold the VCPU state ( in a structure called TDVPS) using the TDH.VP.ADDCX  
function.  The host VMM can  then initialize the VCPU using the TDH.VP.INIT  function.  
After the initial set of pages is added and extended, the VMM can finalize  the TD measurement using the 
TDH.MR.FINALIZE  function.  
2.2.2.  Guest TD Execution  35 
The host VMM  may enter the TD (launch the TD for the first time or  resume a previously intercepted TD execution) using 
the TDH.VP.ENTER  function .  The Intel TDX module  is designed to load CPU state from the TDV PS structure and perform 
VM entry to go into  SEAM -root mode.  
When TD exit is triggered, the Intel TDX module  is designed to save CPU state into the TDVPS  structure , load the CPU 
state saved on TD entry , and switch back to non-SEAM  root mode  (SEAMRET ) at the instruction following SEAMCALL .  The 40 
VMM  can then inspect the TD exit information  in General Purpose Registers ( GPRs ). 
2.2.3.  Guest TD Management during its Run -Time  
During TD lifetime, the VMM  might need to dynamically control the TD and manage the resources assigned to it.  The 
Intel TDX module  provides the VMM  with functions to support scenarios such as : 
• Adding and removing TD pages.  45 
• Changing page mapping sizes.  
• Reclaiming the HKIDs from a TD and  assigning them to another TD.

• Reclaiming the HKIDs from a TD and  assigning them to another TD.  
• Destroying an existing TD.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 20 of 153 
Section 1:  Introduction and Overview  2.3. Intel TDX Operation Modes  and Transitions  
The Intel TDX module  is designed to provide two main  new  logical  modes of operation built upon the new SEAM root 
and non -root CPU modes added to the Intel VMX architecture:  logical TDX Root Mode , and logical TDX Non -Root Mode .  
Figure 2.2 below  shows the Intel TDX logical modes and transitions (in red) on top of the CPU architectural modes.  
DefaultVMXOFF VMXON
Host VMM
Legacy VM
VM
Exit
Parallel VMM
Parallel VM
Opt-out SMMOpt-in SMM
Opt-out SMMParallel VM Entry
Parallel VM Exit
(SMI, VMCALL)
 Intel
TDX Module
SEAMRETSEAMCALLVM
Entry VM
EntryVM
ExitVMX
Non -Root
VMX
Root
Out of
VMXSMM SEAM Legacy VMX
VM
ExitVM
Entry
TD ExitTD
Entry
Host -Side
FunctionGuest -Side
FunctionLogical TDX Non -Root
Logical 
TDX Root
TD
 5 
Figure 2.2:  Overview of Intel TDX Modes & Transitions based on VMX and SEAM Modes and Transitions  
The following table adds more details.  
Table 2.1:  Overview of Intel TDX Modes  
Intel TDX 
Logical Mode  Intel VMX Mode  SEAM Mode  Description  
Logical TDX 
Root  VMX Root  Non -SEAM 
(mostly) , 
SEAM Root 
Mode (during 
host -side Intel 
TDX functions  
execution ) TDX root  mode is  mostly  identical to  the legacy VMX root operation  
mode .   It is generally used for host VMM operation.  
Host -side Intel TDX  functions, triggered by SEAMCALL, are provided 
by the Intel TDX module .  Logically, host -side functions run in TDX 
root mode , though the CPU’s SEAM mode is on . 
Logical TDX  
Non -Root  VMX Non -Root  
(mostly) , 
VMX Root 
(during guest -
side Intel TDX 
flows  execution ) SEAM  TDX non -root  mode is used for TD guest operation.  TDX non -root 
operation is similar to legacy VMX non -root operation, with 
changes and  restrictions to better ensure  that no other software or 
hardware ha s direct visibi lity of the TD memory and state.  
The changes in TDX non -root mode vs. legacy VMX non -root 
operation are implement ed by: 
• The CPU running in SEAM non -root mode .  This modifies the 
address translation to support Secure EPT and usage of private 
HKIDs, and it also modifies the VMX operation (entry, exit, 
etc.).  
• The Intel TDX module , acting as the root  VMM for the guest 
TD, using VMX and SEAM to virtualize the CPU behavior and 
emulate the required TDX non -root behavior.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 21 of 153 
Section 1:  Introduction and Overview  Intel TDX 
Guest -side Intel TDX  flows , triggered by a VM Exit, are provided by 
the Intel TDX module .  Logically, guest -side functions run in TDX 
non-root mode , though the CPU runs VMX root mode.  
TDX non -root operation is described in Chapter  11. 
 
Intel TDX transitions  between TDX root operation and TDX non -root operation include TD Entries , from logical TDX root 
to logical TDX non-root mode , and TD Exits  from logical TDX non-root to logical TDX root mode.  A TD Exit might  be 
asynchronous , triggered by some external event (e.g., external interrupt or SMI) or an exception, or it might  be 
synchronous , triggered by a TDCALL (TDG.VP.VMCALL ) function . 5 
2.4. Guest TD Private  Memory Protection  
 Memory Encryption  
The Intel TDX module  helps protect guest TD private memory using memory encryption and integrity protection as 
enabled  by the CPU’s MKTME and TDX ISA  features.  The Intel TDX module  adds key management functionality  to help 
enforce its security objectives.  10 
Memory encryption is designed to be performed by encryption engines that reside at each memory controller.  An 
encryption engine holds a table of encryption keys, known as the Key Encryption Table (KET).  An encryption key is 
selected for each memory transaction based on a Host  Key Identifier (HKID)  that should be provided with the transaction.  
In the first generation of MKTME , HKID is “stolen” from the physical address by allocating a configurable number of bits 
from the top of the physical address.  TDX ISA  is designed to further partition t he HKID space into shared HKIDs  for legacy 15 
MKTME accesses and private HKIDs  for SEAM -mode -only  accesses.  Future generations might  choose to express HKID 
differently.  
During SEAM  non-root operation, memory accesses can be qualified as either shared or private, based on the value of a 
new SHARED bit in the Guest Physical Address (GPA).  Shared accesses are intended to behave as legacy memory accesses 
and use the upper bits of the host physical address as an HKID, which must be from the range allocated to legacy MKTME.   20 
Private accesses use the guest TD’s private  HKID . 
The host -side Intel TDX functions help provide the means for the host VMM  to manage HKID assignment to guest TDs, 
configure the memory encryption engines , etc., while better assuring proper operation to help maintain the TDX’s 
security objectives.   By design, t he host VMM does not have access to the encryption keys.  
Key management is described in Chapter  4. 25 
2.4.2.  Address Translation  
Guest Physical Address (GPA) space is divided into private and shared sub-spaces, determined by the SHARED bit of GPA.   
As designed, t he CPU translates shared GPAs using the Shared EPT, which resides in host VMM memory .  The Shared EPT  
is directly managed by the host VMM – the same as with legacy VMX.  
As designed, t he CPU translates private GPAs using a separate Secure EPT.  The Secure EPT pages are encrypted and 30 
integrity -protected with the TD’s ephemeral private key.  The Secure EPT is not intended to be directly accessible by any 
software other than  the Intel TDX module , nor by any devices.  Secure EPT can be managed indirectly by the host VMM, 
using Intel TDX functions.  The Intel TDX module  helps ensure that the Secure EPT security properties are kept.  At the 
end of translation, the CPU sets the HKID bits in the HPA to the TD’s assigned HKID.  
TD private memory management is described in Chapter  9. 35 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 22 of 153 
TD0
CR3 Private Code/data
Private Code/dataGuest Physical Address
Shared Data
CPU PMH
Extended
Page Tables
(Secure EPT )Shared Extended
(Shared EPT )Guest Physical Address (GPA)
Physical 
Address + 
HKIDTD Private 
HKIDShared GPA Space
Memory encrypted with a 
key shared with VMMPrivate GPA Space
TD private key
YesNoGPA.SHAREDHPA Space
Physical Memory 
Pages
 
Figure 2.3:  Secure EPT Concept  
2.5. Guest TD State Protection  
Intel TDX helps protect the confidentiality and integrity of a guest TD and the state of its Virtual CPUs ( VCPUs ) with the 
following mechanisms:  5 
Protected Control 
Structures  TD-scope and TD VCPU -scope control structures, which hold guest TD metadata and TD VCPU 
state, are not directly accessible to any software  (besides the Intel TDX module ) or devices .  As 
designed, the control structures are encrypted and integrity -protected with a private key and 
managed by Intel TDX function s.  TD control structures are described in Chapter  6. 
VCPU State on TD 
Transitions  On asynchronous TD exits, which usually happen due to external events , the CPU state is saved 
to the VCPU control structures, and a synthetic state is loaded  into the CPU registers .  On the 
following TD Entry, the CPU state is restored from the protected control structures.  
On synchronous TD -initiated exit , using the TDCALL( TDG.VP.VMCALL ) function , selected  GPR 
and XMM state can be  passed as -is to the host VMM .  On the following TD entry, that state can 
be passed back as -is to the guest TD.  
2.6. Intel TDX I/O Model  
The TD guest can use the following I /O models:  
• Paravirtualized devices  
• Paravirtualized devices with MMIO emulation  
• Direct assignment of devices to a TD  10 
The Intel TDX architecture does not provide specific mechanisms for trusted I /O.  Any integrity or confidentiality 
protection of data submitted to or received from physical or emulated devices must be done by the guest software using 
cryptography.  
Intel TDX I/O is detailed in Chapter  13. Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 23 of 153 
Section 1:  Introduction and Overview  2.7. Measurement and Attestation  
As designed, d uring TD launch, the initial contents and configuration of the TD are recorded by the Intel TDX module .  In 
addition, run -time measurement registers can be used by the guest TD software, e.g., to measure a boot process.  At run -
time, the Intel TDX architecture  reuses the Intel ® Software Guard Extensions (Intel ® SGX) attestation infrastructure to 
provide support for attesting to these measurements as described below.  5

provide support for attesting to these measurements as described below.  5 
Intel TDX attestation is intended to be used in two phases:  
1. Software within the guest TD can use  the TDCALL( TDG.MR.REPORT ) function  to request the Intel TDX module  to 
generate an integrity protected  TDREPORT structure .  The Intel TDX ISA provides support for enabling the Intel TDX 
module  to create this structure that includes the TD’s measurements, the Intel TDX module ’s measurements, and a 
value provided by the  guest  TD software.  This will typically be an asymmetric key that the attestation verifier can 10 
use to establish a secure channel or protect sensitive data to be sent to the TD software.  
2. An Intel SGX Quoting Enclave, written specifically to support  quoting Intel TDX TDs, uses a new ENCLU instruction 
leaf, EVERIFYREPORT2 , to help  check  the integrity of the TDG.MR.REPORT .  If it passes, the Quoting Enclave  can use 
a certified quote signing key to sign a quote containing the guest TD’s measurements and the additional data being 
quoted.  15 
The Quoting Enclave can run anywhere on the platform where Intel SGX is supported.  
Note:   Running  Intel  SGX enclaves within a guest TD is not supported.  
3
Intel Confidential3TD Quoting Enclave Trust Domain1) TDREPORT
(TDCALL Leaf)2) EVERIFYTDREPORT 2
(Instruction) TDREPORT
(MAC)TDQUOTE
(Signed)
TDCS
Quote KeyMAC Key MAC KeyVM 
Data/Key
 
Figure 2.4:  TD Attestation  
TD measurement and attestation is described in Chapter  12. 20 
2.8. Intel TDX Managed  Control Structures  
As designed, t he Intel TDX module  hold s and manages a set of control structures that are not directly accessible to 
software (except the Intel TDX module  itself).  The controls structures are encrypted with private keys  and HKIDs, and 
their content is only accessible in SEAM mode .  Most control structures are addressable by the host VMM , which is 
responsible for allocating the memory to hold them.  25 
The Intel TDX module  uses control structures to help manage TD -private memory, t ransitions into and out of logical TDX 
non-root operation (TD entries and TD exits) , as well as processor behavior in SEAM  non-root operation.  
Table 2.2:  TDX-Managed  Control Structures  Overview  
Scope  Name  Meaning  Description  
Table  Designed to c ontrol private HKID assignment.   KOT is internal to 
the Intel TDX module , intended not to be directly accessible  to 
any other software . 
Metadata Table  PAMT is designed to hold m etadata of each page in a Trust 
Domain Memory Range (TDMR).  It controls assignment of 
physical pages to guest TDs , etc.  The PAMT is intended not to 
be directly accessible to software.  It resides in memory  
allocated by the host VMM on TDX initialization.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 24 of 153 
Section 1:  Introduction and Overview  Scope  Name  Meaning  Description  
Guest TD  TDR Trust Domain 
Root  TDR is intended to be the r oot control structure of a guest TD.   
It controls the key management and build/teardown process.   
The TDR is not intended to be directly accessible to software.  It 
resides in memory allocated  by the  host  VMM , via Intel TDX 
interface functions . 
Control Structure  TDCS is intended to control the operation of a guest TD as a 
whole.   The TDCS is not intended to be directly accessible to 
software.  It resides in memory allocated  by the  host  VMM , via 
Intel TDX  interface functions . 
SEPT  Secure EPT  Secure EPT is an  Extended Page Table (EPT) tree, managed by 
the TDX module, and used to help securely manage address 
translation for the TD private pages.   The SEPT is not intended 
to be directly accessible to software.  SEPT pages reside in 
memory  allocated  by the  host VMM  via Intel TDX interface 
functions . 
Guest TD 
State  The TDVPS help s control the operation and hold the state of a 
guest TD virtual processor.  It holds the TD VMCS and its 
auxiliary  structures as well as other non -VMX control and state 
fields.   The TDVPS is not intended to be directly accessible to 
software.  It resides in memory  allocated  by the  host  VMM , via 
 
Intel TDX control structures are described in Chapter  6. 
2.9. Intel TDX Interface  Functions  
The Intel TDX module  implements  function s that are triggered by executing two TDX instruction s: 
SEAMCALL  The instruction used by  the host  VMM  to invoke host -side TDX  interface  function s.  The desired interface 5 
function  is selected by an input operand ( leaf number , in RAX).   Host -side interface function names start 
with TDH (Trust Domain Host).  
TDCALL  The instruction used by the guest TD software  (in SEAM  non-root mode)  to invoke guest -side TDX 
function s.  The desired interface function  is selected by an input operand ( leaf number , in RAX).   Guest -
side interface function names start with TDG (Trust Domain Guest).  10 
Intel TDX interface function details are described in the [ TDX Module ABI Spec ]. 
2.9.1.  Host -Side (SEAMCALL Leaf) Interface  Functions  
Table 2.3:  Host -Side (SEAMCALL Leaf) Interface  Functions  
Intel TDX Module Management  TDH.SYS.CONFIG  45 Globally configure the Intel TDX module  
Intel TDX Module Management  TDH.SYS.INFO  32 Get Intel TDX module information  
Intel TDX Module Management  TDH.SYS.INIT  33 Globally initialize the Intel TDX module  
Intel TDX Module Management  TDH.SYS.KEY.CONFIG  31 Configure the Intel TDX global private key on the 
current package  
Intel TDX Module Management  TDH.SYS.LP.INIT  35 Initialize the Intel TDX module per logical processor  
Intel TDX Module Management  TDH.SYS.LP.SHUTDOWN  44 Does nothing; provided for backward compatibility  
Intel TDX Module Management  TDH.SYS.RD  34 Read a TDX Module global -scope metadata field  
Intel TDX Module Management  TDH.SYS.RDALL  37 Read all host -readable TDX Module global -scope 
metadata fields  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 25 of 153 
Section 1:  Introduction and Overview  Class  Interface Function Name  Leaf 
Intel TDX Module Management  TDH.SYS.SHUTDOWN  52 Shutdown the Intel TDX module and prepare handoff 
data  
Intel TDX Module Management  TDH.SYS.TDMR.INIT  36 Partially initialize a Trust Domain Memory Region 
(TDMR)  
Intel TDX Module Management  TDH.SYS.UPDATE  53 Populate Intel TDX module state from handoff data  
TD Management  TDH.MNG.ADDCX  1 Add a control structure page to a TD  
TD Management  TDH.MNG.CREATE  9 Create a guest TD and its TDR root page  
TD Management  TDH.MNG.INIT  21 Initialize per -TD control structures  
TD Management  TDH.MNG.KEY.CONFIG  8 Configure the TD private key on a single package  
TD Management  TDH.MNG.KEY.FREEID  20 Mark the guest TD’s HKID as free  
TD Management  TDH.MNG.KEY.RECLAIMID  27 Does nothing; provided for backward compatibility  
TD Management  TDH.MNG.RD  11 Read TD metadata  
TD Management  TDH.MNG.VPFLUSHDONE  19 Check all of a guest TD’s VCPUs have been flushed by 
TDH.VP.FLUSH  
TD Management  TDH.MNG.WR  13 Write TD metadata  
VCPU Scope  TDH.VP.ADDCX  4 Add a control structure page to a TD VCPU  
VCPU Scope  TDH.VP.CREATE  10 Create a guest TD VCPU and its TDVPR root page  
VCPU Scope  TDH.VP.INIT  22 Initialize the per -VCPU control structures  
VCPU Scope  TDH.VP.RD  26 Read VCPU metadata  
VCPU Scope  TDH.VP.WR  43 Write VCPU metadata  
Physical Memory Management  TDH.PHYMEM.CACHE.WB  40 Write back the contents of the cache on a package  
Physical Memory Management  TDH.PHYMEM.PAGE.RDMD  24 Read the metadata of a page in a TDMR  
Physical Memory Management  TDH.PHYMEM.PAGE.RECLAIM  28 Reclaim a physical memory page owned by a TD (i.e., 
TD private page, Secure EPT page or a control structure 
page)  
Physical Memory Management  TDH.PHYMEM.PAGE.WBINVD  41 Write back and invalidate all cache lines associated 
with the specified memory page and HKID  
Private Memory Management  TDH.MEM.PAGE.ADD  2 Add a 4KB private page to a TD during TD build time  
Private Memory Management  TDH.MEM.PAGE.AUG  6 Dynamically add a 4KB private page to an initialized TD  
Private Memory Management  TDH.MEM.PAGE.RELOCATE  5 Relocate a 4KB mapped page from its HPA to another

page)  
Private Memory Management  TDH.MEM.RD  12 Read from private memory of a debuggable guest TD  
Private Memory Management  TDH.MEM.TRACK  38 Increment the TD’s TLB tracking counter  
Private Memory Management  TDH.MEM.WR  14 Write to private memory of a debuggable guest TD  
Measurement and Attestation  TDH.MR.EXTEND  16 Extend the guest TD measurement register during TD 
build  
Measurement and Attestation  TDH.MR.FINALIZE  17 Finalize the guest TD measurement register  
Service TD  TDH.SERVTD.BIND  48 Bind a service TD to a target TD  
Service TD  TDH.SERVTD.PREBIND  49 Pre-bind a service TD to a target TD  
Migration  TDH.MIG.STREAM.CREATE  96 Create a migration stream  
Migration Export  TDH.EXPORT.ABORT  64 Abort an export session  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 26 of 153 
Migration Export  TDH.EXPORT.BLOCKW  65 Block a TD private page for writing  
Migration Export  TDH.EXPORT.MEM  68 Export a list of TD private pages contents and/or 
cancellation requests  
Migration Export  TDH.EXPORT.PAUSE  70 Pause the exported TD  
Migration Export  TDH.EXPORT.RESTORE  66 Restore a list of TD  private 4KB pages’ Secure EPT entry 
states after an export abort  
Migration Export  TDH.EXPORT.STATE.IMMUTABLE  72 Start an export session and export the TD's immutable 
state  
Migration Export  TDH.EXPORT.STATE.TD  73 Export the TD's mutable state  
Migration Export  TDH.EXPORT.STATE.VP  74 Export a VCPU mutable state  
Migration Export  TDH.EXPORT.TRACK  71 End the current in -order export phase epoch and either 
start a new epoch or start the out -of-order export 
phase  
Migration Export  TDH.EXPORT.UNBLOCKW  75 Unblock a page that has been blocked for writing  
Migration Import  TDH.IMPORT.ABORT  80 Abort an import session  
Migration Import  TDH.IMPORT.COMMIT  82 Commit the import session and allow the imported TD 
to run  
Migration Import  TDH.IMPORT.END  81 End an i mpo rt session  
Migration Import  TDH.IMPORT.MEM  83 Import a list of TD private pages contents and/or 
cancellation requests based on a migration bundle in 
shared memory  
Migration Import  TDH.IMPORT.STATE.IMMUTABLE  85 Start an import session and import the TD's immutable 
state  
Migration Import  TDH.IMPORT.STATE.TD  86 Import the TD's mutable state  
Migration Import  TDH.IMPORT.STATE.VP  87 Import a VCPU mutable state  
Migration Import  TDH.IMPORT.TRACK  84 End the current in -order import phase epoch and either 
start a new epoch or start the out -of-order import 
phase  
 
2.9.2.  Guest -Side (TDCALL Leaf) Interface  Functions  
Table 2.4:  Guest -Side (TDCALL Leaf) Interface  Functions  
Intel TDX Module Management  TDG.SYS.RD  11 Read a TDX Module global -scope metadata field  
Intel TDX Module Management  TDG.SYS.RDALL  12 Read all gust -readable TDX Module global -scope 
metadata fields  
TD Management  TDG.VM.RD  7 Read a TD -scope metadata field  
TD Management  TDG.VM.WR  8 Write a TD -scope metadata field  
VCPU Scope  TDG.VP.CPUIDVE.SET  5 Control delivery of #VE on CPUID instruction execution  
VCPU Scope  TDG.VP.INFO  1 Get TD execution environment information  
L2 VM  
VCPU Scope  TDG.VP.RD  9 Read a VCPU -scope metadata field  
VCPU Scope  TDG.VP.VEINFO.GET  3 Get Virtualization Exception Information for the recent 
#VE exception  
VCPU Scope  TDG.VP.VMCALL  0 Call a host VM service  
VCPU Scope  TDG.VP.WR  10 Write a VCPU -scope metadata field  
page  
Private Memory Management  TDG.MEM.PAGE.ATTR.WR  24 Write the attributes of a private page  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 27 of 153 
Measurement and Attestation  TDG.MR.REPORT  4 Creates a cryptographic report of the TD  
Measurement and Attestation  TDG.MR.RTMR.EXTEND  2 Extend a TD run -time measurement register  
Measurement and Attestation  TDG.MR.VERIFYREPORT  22 Verify a cryptographic report of a TD, generated on the 
current platform  
Service TD  TDG.SERVTD.RD  18 Read a target TD metadata field  
Service TD  TDG.SERVTD.WR  20 Write a target TD metadata field  
November 2023   . Page 28 of 153 
Section 1:  Introduction and Overview  3. Software Use Cases  
This chapter summarizes the software use cases ( also known as  software flows) used with the Intel TDX module . 
3.1. Intel TDX Module  Lifecycle  
3.1.1.  Intel TDX Module  Platform -Scope  First -Time Initialization  
This sequence is intended to be  used by the host VMM to initialize  the Intel TDX module  at the platform scope . 5 
Table 3.1:  Typical Intel TDX Module  Platform -Scope First -Time Initialization  Sequence  
Phase   Intel TDX  Function  Scope  Execute On  Description  
Boot  1 N/A Platform  Each core  BIOS configures Convertible Memory  Regions  
(CMRs)  and activates MKTME ; MCHECK checks  
them and securely stores the information.  
P-SEAMLDR 
Loading  2 N/A Platform  One of the 
BSPs  BIOS or  OS launches the NP -SEAMLDR ACM, 
which loads the Intel P -SEAMLDR module.  
Intel TDX 
Module 
Loading  3 SEAMLDR.INSTALL  Platform  Each  LP, 
serially  VMM calls the Intel P-SEAMLDR module with 
“load” scenario to install the first TDX module.   
The TDX module is installed when 
SEAMLDR.INSTALL is called on the last LP.  
Intel TDX 
Module  
Initialization  4 TDH.SYS. INIT  Platform  Any one LP  Perform global initialization of the Intel TDX 
module . 
5 TDH.SYS.LP.INIT  LP Each LP  Perform LP -scope, core -scope and package -
scope initialization, checking  and configuration 
of the platform and the Intel TDX module . 
Enumeration 
and 
Configuration  6 TDH.SYS.RD * or 
TDH.SYS. INFO  Platform  Any 
initialized LP Retrieve Intel TDX module  information and 
convertible memory (CMR) information . 
7 TDH.SYS. CONFIG  Platform  Any one LP  Configure the Intel TDX module  with TDMR and 
PAMT setup . 
8 N/A Package  Each Package  If any MODIFIED cache lines may exist for the 
PAMT ranges, flush them to memory using, e.g., 
WBINVD.  
9 TDH.SYS.KEY.CONFIG  Package  Each Package  Configure the Intel TDX global private key used 
for encrypting PAMT and TDR on the hardware 
(other TD -scope control structures are 
encrypted with their respective TD’s ephemeral 
private keys).  
At this point any Intel TDX function may be executed on any LP.  
Memory 
Initialization  10 TDH.SYS.TDMR.INIT  
(multiple)  Platform  One or more 
LPs Called multiple times to gradually initialize the 
PAMT structure for each TDMR .   
Once each 1GB block of TDMR has been initialized by TDH.SYS.TDMR.INIT, it can be used to hold TD -
private pages.  
 
3.1.2.  Intel TDX Module Shutdown and Update  
This sequence is intended to be used by the host VMM to gracefully shut down the Intel TDX module and install a new 
Intel TDX module .  There are 2 scenarios:  10 
• Reload scenario – guest TDs’ context and memory are lost.  
• Update scenario - guest TDs’ context and memory are preserved.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 29 of 153 
 Intel TDX Module Reload  
In the reload scenario, the previous TDX module in SEAM range is erased when the next TDX module is installed.  Since 
in this scenario the previous module can’t pass any information to the next TDX module, the next TDX module starts 
afresh, and all guest T Ds’ context and memory out of SEAM range becomes effectively inaccessible.  
Table 3.2:  TDX Module Reload Sequence  5 
P-SEAMLDR  1 SEAMLDR.INSTALL with 
“load” scenario  Platform  All LPs  Installs the next TDX module, regardless of the 
previous TDX module.  
Next TDX

Next TDX 
module  The initialization sequence continues in the same way as described in 3.1.1 above , steps 3 to 8.  
 
 Intel TDX Module Update  
In the update scenario, the previous TDX module in SEAM range is not fully erased; the previous TDX module can be asked 
to leave “handoff data” in a specific location of the SEAM range, so that the next TDX module would be able to initialize 
itself from th is handoff data.  The next TDX module can thus keep supporting guest TDs’ context and memory.  10 
Table 3.3:  TDX Module TD -Preserving Update Sequence  
Previous 
TDX 
Module  1 TDH.SYS.SHUTDOWN  Platform  Selected LP  Prepare handoff data and mark the TDX 
module’s global state as “shutdown”.  
P-SEAMLDR  2 SEAMLDR.INSTALL with 
“update” scenario  Platform  All LPs , 
serially  Install the next TDX module without clearing the 
handoff data.  
Next TDX 
Module  3 TDH.SYS.INIT  Platform  Selected LP  Perform global initialization of the Intel TDX 
module.  
4 TDH.SYS.LP.INIT  LP All LPs  Perform  LP-scope, core -scope  and package -
scope initialization s, checking  and configuration 
5 TDH.SYS.UPDATE  Platform  Selected LP  Populate internal variables from handoff data .  
Mark  the TDX module’s global state as “ready”.  
At this point  any Intel TDX  function  may be executed on any LP  (don’t call TDH.SYS.CONFIG, 
TDH.SYS.KEY.CONFIG and TDH.SYS.TDMR.INIT).  
In particular, TDs created by previous TDX modules can be re -entered.  
 
3.2. TD Build  
The following sequence is intended to be used by the  host VMM to build a TD.  
Table 3.4:  Typical TD Build Sequence  15 
 Step   Description  SEAMCALL Leaf 
Function s 
A TD Creation  
and Key 
Resource 
Assignment  1 The host VMM  finds/allocates a free HKID for the new TD . TDH.MNG.CREATE  
TDH.MNG.KEY.CONFIG  2 The host VMM  allocates a 4K B page for the TDR in TDMR .  If any 
MODIFIED cache lines may exist for this page, the host VMM flushes 
them to memory using, e.g., CLFLUSHOPT or 
TDH.PHYMEM.PAGE.WBINVD.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 30 of 153 
Section 1:  Introduction and Overview   Step   Description  SEAMCALL Leaf 
Function s 
3 The host VMM  creates the  new TD by calling the TDH.MNG.CREATE  
function ( passing HPA of the TDR page) .  This  initializes the target TDR 
page . 
4 The TD  host VMM  configures the MKTME  hardware with the TD’s 
private key by calling the TDH.MNG.KEY.CONFIG  function on each  
package . 
5 At this point, the TD private memory is accessible.  The VMM can use 
Intel TDX  interface functions to create control structures and TD private 
pages as described below.  
B TDCS 
Memory 
Allocation 
and TD 
Initialization  1 The host VMM allocates multiple 4KB TDCX pages for TDCS.  The 
number of required TDCX pages is enumerated by TDH.SYS.RD * or 
TDH.SYS. INFO.   If any MODIFIED cache lines may exist for these pages, 
the host VMM flushes them to memory using, e.g., CLFLUSHOPT or 
TDH.PHYMEM.PAGE.WBINVD.  TDH.MNG.ADDCX  
TDH.MNG.INIT  
2 For each TDCX page, the host VMM calls the TDH.MNG.ADDCX  function 
(passing HPA of TDCX) to add the page to the TD.  
3 The host VMM builds a TD_PARAMS structure.  For example, the TD 
configuration parameters can be obtained from a TD manifest supplied 
by the TD owner.  
4 The host VMM calls the TDH.MNG.INIT  function (passing the 
TD_PARAMS structure) to initialize the TD.  
C Virtual 
Processor 
Creation and 
(Executed per 
each VCPU)  1 The host VMM allocates target pages for the VCPU’s TDVPR and TDCX  
pages in TDMR in the context of a TD.  The number of required TDCX  
pages is enumerated by TDH.SYS.RD * or TDH.SYS. INFO.   If any 
MODIFIED cache lines may exist for these pages, the host VMM flushes 
TDH.PHYMEM.PAGE.WBINVD.  TDH.VP.CREATE  
TDH.VP.ADDCX  
TDH.VP.INIT  
TDH.VP.WR  
2 The host VMM creates  a new TD virtual CPU by calling the 
TDH.VP.CREATE  function (passing the HPA of the new TDVPR page  and 
its owner TDR page).  
3 For each TDCX  page, t he host VMM  calls the TDH.VP.ADDCX  function 
(passing the HPA of the new TDCX  page  and its parent TDVPR page) . 
4 The host VMM  initializes the TD VCPU by calling the TDH.VP.INIT  
function (passing the HPA of its TDVPR page) .  It also passes a single 64b 
parameter that is later passed to  the VBIOS in the initial value of RCX .  
This parameter can be used as a pointer to a configuration structure in 
shared memory.  
5 The host VMM  allocates Shared EPT for each VP . 
6 The host  VMM uses the TDH.VP.WR  function to write to the TD VMCS 
Shared EPTP field . 
7 The host VMM may modif y a few TD VMCS execution control fields 
using TDH.VP.WR . 
D TD Boot 
Memory 
Setup  1 The host VMM  loads the TD boot image to its memory .  The boot image 
contains code and data pages that typically include a virtual BIOS, OS 
boot loader, configuration , etc. TDH.MEM.SEPT.ADD  
TDH.MEM.PAGE.ADD  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 31 of 153 
Function s 
2 The host VMM builds the TD Secure EPT by allocat ing physical pages 
and calling  the TDH.MEM.SEPT.ADD  function  multiple times .  If any 
TDH.PHYMEM.PAGE.WBINVD.  TDH.MR.EXTEND  
3 The host  VMM allocates the initial set of physical pages for the TD boot 
image and maps them  into host address space .  If any MODIFIED cache 
lines may exist for these pages, the host VMM flushes them to memory 
using, e.g., CLFLUSHOPT or TDH.PHYMEM.PAGE.WBINVD.  
4 For each TD page:  
1. The host VMM specifies a TDR as a parameter and calls the 
TDH.MEM.PAGE.ADD  function .  It copies the contents from the TD 
image page into the target TD page which is encrypted with the TD 
ephemeral key.  TDH.MEM.PAGE.ADD  also extends the TD 
measurement with the page GPA.  
2. The host VMM extends the TD measurement with the contents of 
the new page by calling the TDH.MR.EXTEND  function on each 256 -
byte chunk of the new TD page.  
E TD 
Finalization  1 The host VMM calls the TDH.MR.FINALIZE  function, which finalizes the 
TD measurement.  TDH.MR.FINALIZE  
2 At this point, the TD is finalized.  
• Its measurement cannot  be modified anymore (except the run -time 
measurement registers).  
• TD VCPUs can be entered using SEAMCALL( TDH.VP.ENTER ). 
 
3.3. TD Run Time  
3.3.1.  Private Memory Management  
 Dynamic Page Addition  (Shared  to Private Conversion)  
The following sequence is intended to be used by the host VMM to dynamically a dd a page to a guest TD . 5 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 32 of 153 
Request GPA Range Allocation
TD Exit
TDH.MEM.SEPT.ADD(TDR, GPA, level)
Build S -EPT tree as required
TDH.MEM.PAGE.AUG(TDR, GPA)
Add one or more 4KB pages as requested
Return TDVMCALL output
VM entry
TDG.MEM.PAGE.ACCEPT(GPA)
For every 4KB page that was added 
Figure 3.1:  Typical Dynamic Page Addition  Sequence  
 
Table 3.5:  Typical Dynamic Page Addition (Shared to Private Conversion)  Sequence  
Phase   Side  Intel TDX  Function  Scope  Execute 
On Description  
Request  1 TD TDG.VP.VMCALL  TD Any LP  Optional software protocol:  Request 
GPA range allocation.  
Page 
Addition  2 VMM  TDH.MEM.SEPT.ADD  TD Any LP If required, update the Secure EPT.  
3 VMM  TDH.MEM.PAGE.AUG  
(multiple)  TD Any LP Add one or more new 4KB or 2MB 
At this point, the new page is pending acceptance by the guest TD and cannot  be accessed by it yet.  
4 VMM  TDH.VP.ENTER  TD Any LP  Optional software protocol:  Return 
TDG.VP.VMCALL  result.  
Page 
Acceptance  5 TD TDG.MEM.PAGE.ACCEPT  
(multiple)  TD Any LP  Accept the new pending page(s).  
Content of each page is zeroed out.  
At this point, the new page can be accessed by the guest TD.  
 5 
 Dynamic Page Removal (Private to Shared Conversion)  
The following sequence is intended to be used by the host VMM to dynamically remove a page from a guest TD.  Dynamic 
page removal  is detailed in 0. Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 33 of 153 
Intel TDX 
ModuleHost VMM Guest TD
Release GPA Range
TD Exit (TDVMCALL)
Return TDG.VP.VMCALL output
VM Entry
TDH.MEM.RANGE.BLOCK(TDR, GPA, level)
For every page to be removed
TDH.MEM.TRACK(TDR)
IPI
VM Exit (external interrupt)
TD Exit (external interrupt)
VM Entry
TDH.MEM.PAGE.REMOVE(TDR, GPA, level)
TDH.PHYMEM.PAGE.WBINVD(HPA, HKID)

Page 
 5 
Intel TDX 
VM Entry
IPI
VM Entry
For every page, before it is re -allocated to any s/wTLB Tracking Sequence
 
Figure 3.2:  Typical Dynamic Page Removal  Sequence  
 
Table 3.6:  Typical Dynamic Page Removal (Private to Shared Conversion)  Sequence  
Ballooning 
Notification  1 TD TDG.VP.VMCALL  TD Any LP  Optional software protocol:  Release 
GPA range.  
2 VMM  TDH.VP.ENTER  TD Any LP  Optional software protocol:  Return 
TLB 
Tracking 
Sequence  3 VMM  TDH.MEM.RANGE.BLOCK  
(multiple)  TD Any LP Block private pages from further address 
4 VMM  TDH.MEM.TRACK  TD Any o ne 
LP Increment the TD’s TLB epoch.  
5 VMM  N/A TD Multiple 
LPs Send an IPI, causing TD exit on any 
remote LP associated with a VCPU.  
Subsequent TDH.VP.ENTER  will flush 
TLB.  
Page 
Removal  6 VMM  TDH.MEM.PAGE.REMOVE  
(multiple)  TD Any LP  Server:  Clear Secure EPT entry.  Mark 
the physical page as free.  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 34 of 153 
Section 1:  Introduction and Overview  Phase   Side  Intel TDX  Function  Scope  Execute 
Cache 
Flushing  & 
Content Init  Before re -allocating any of the removed pages to any use, the host VMM should ensure none of the cache 
lines of the removed pages are in the MODIFIED state to avoid corruption due to cache line aliasing.  This is 
done using one of the following methods:  
7a VMM  Server:  
TDH.PHYMEM.PAGE.WBINVD 
(multiple)  TD Any one 
LP Server:  Flush the cache lines of the 
removed page(s).  
7b VMM  WBNOINVD  Platform  One LP 
per 
WBINVD
domain2 Globally write back all caches.  
7c VMM  WBINVD  Platform  One LP 
per 
WBINVD
domain3 Globally write back and invalidate all 
caches.  
8 VMM  MOVDIR64B  Page  Any LP  Initialize the physical page content for 
use with a new shared HKID.  
 
 Page Promotion ( Mapping Merge)  
Page size promotion is intended to be used by the host VMM to merge 512 pages mapped as 4KB or 2MB into a single 
page mapped as 2MB or 1GB , respectively.  It is detailed  in 9.11 . 
Intel TDX 
TDH.MEM.PAGE.PROMOTE(TDR, GPA, level)
For the removed S -EPT page, before it is
 re-allocated to any s/wTLB Tracking Sequence (not detailed here)
 5 
Figure 3.3:  Typical Page Promotion  Sequence  
 
2 Some CPUs may require running WBNOINVD per a set of LPs that is smaller than the set of all LPs in a package . 
3 Some CPUs may require running WBINVD per a set of LPs that is smaller than the set of all LPs in a package . Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 35 of 153 
Section 1:  Introduction and Overview  Table 3.7:  Typical Page Promotion ( Mapping Merge)  Sequence  
Phase   Intel TDX  Function  Scope  Execute On Description  
TLB 
Tracking 
Sequence  1 TDH.MEM.RANGE.BLOCK  TD Any LP Block the GPA range to be merged from 
further address translation.  
2 TDH.MEM.TRACK  TD Any o ne LP  Increment the TD’s TLB epoch.  
3 N/A TD Multiple LPs  Send an IPI, causing TD exit on any remote 
LP associated with a VCPU.  Subsequent 
TDH.VP.ENTER  will flush TLB.  
Promotion  4 TDH.MEM.PAGE.PROMOTE  TD Any LP  Merge small pages in the GPA range into a 
large page.  
Cache 
Flushing  & 
Content 
Init 5 Server:  
TDH.PHYMEM.PAGE.WBINVD  TD Any LP  Server:  Flush the removed Secure EPT 
page’s cache lines.  
Client:    Client:  This operation is performed by the 
TDX module  
6 MOVDIR64B  Page  Any LP  Initialize the physical page content for use 
with a new shared HKID.  
 
 Page Demotion ( Mapping Split)  
Page size demotion  is intended to be used by the host VMM to split a page mapped as 1GB or 2MB into 512 pages mapped 
as 2MB or 4KB , respectively.  It  is detailed  in 9.12 . 5 
Intel TDX 
TDH.MEM.PAGE.DEMOTE(
TDR, GPA, level, new S -EPT page)TLB Tracking Sequence (not detailed here)
 
Figure 3.4:  Typical Page Demotion  Sequence  
November 2023   . Page 36 of 153 
Section 1:  Introduction and Overview  Table 3.8:  Typical Page Demotion ( Mapping Split)  Sequence  
TLB 
Tracking 
Sequence  1 TDH.MEM.RANGE.BLOCK  TD Any LP Block private large page from further 
address translation.  
3 N/A TD Multiple LPs  Send an IPI, causing TD exit on any 
TLB.  
Demotion  4 TDH.MEM.PAGE.DEMOTE  TD Any LP  Split the large page into multiple small 
pages.  
 
 GPA Range Unblock  
GPA range unblock is intended to be used when  a range has been blocked , for example, for  page removal, but the host 
VMM decides to cancel the operation.  Unblock is detailed in 0. 5 
Intel TDX 
TDH.MEM.RANGE.UNBLOCK(TDR, GPA, level)TLB Tracking Sequence (not detailed here)
 
Figure 3.5:  Typical GPA Range Unblock  Sequence  
 
Table 3.9:  Typical GPA Range Unblock  Sequence  
TLB 
Tracking 
Sequence  1 TDH.MEM.RANGE.BLOCK  
(multiple)  TD Any LP Block private GPA range from further address 
translation . 
2 TDH.MEM.TRACK  TD Any o ne LP  Increment the TD’s TLB epoch . 
3 N/A TD Multiple LPs  Send an IPI, causing TD exit on any remote LP 
associated with a VCPU.  Subsequent 
Unblocking  4 TDH.MEM.RANGE.UNBLOCK  TD Any LP  Remove the private GPA range blocking . 
 10 Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 37 of 153 
Section 1:  Introduction and Overview  3.3.2.  Guest TD Execution  
 TD VCPU First -Time Invocation  
Table 3.10:  Typical TD VCPU First -Time Invocation  Sequence  
Phase   Side  Intel TDX  
Function  Scope  Execute 
Entering TD 
VCPU (First 
Time)  1 VMM  N/A LP LP x Save VMM LP state not preserved across TD Entry 
to TD exit . 
2 VMM  TDH.VP.ENTER  VCPU/LP  LP x Restore initial LP state, as set by TDH.VP.INIT , from 
TDVPS and enter SEAM  non-root mode . 
TD VCPU 
Initial 
Execution  TD software (VBIOS) starts execution in 32 -bit protected mode with no paging . 
3 TD N/A VCPU/LP  LP x  TD software parses initial information in GPR, 
builds page tables and switches to 64 -bit mode . 
TD software (VBIOS) now executes in 64 -bit mode . 
Enumeration  4 TD TDG.VP.INFO  VCPU/LP  LP x  TD software retrieves basic TD and execution 
environment information . 
5 TD TDG.MR.REPORT  VCPU/LP  LP x  TD software retrieves additional TD information . 
TD continues execution in SEAM  non-root mode . 
 
 TD VCPU Entry, Exit on TDG.VP.VMCALL  and Re -Entry  5 
Table 3.11:  Typical TD Entry, Exit on TDG.VP.VMCALL  and Re -Entry  Sequence  
TD Entry  1 VMM  N/A LP LP x Save VMM LP state not preserved across TD Entry 
to TD exit . 
2 VMM  TDH.VP.ENTER  VCPU/LP  LP x Restore LP state from TDVPS and enter SEAM  
non-root mode . 
TD executes in TDX non -root mode . 
Software 
Protocol over 
TDG.VP.VMCALL  3 TD TDG.VP.VMCALL  VCPU/LP  LP x  Exit SEAM  non-root mode, save LP state to TDVPS , 
and set synthetic state (except most GPRs and all 
XMMs) . 
4 VMM  N/A LP LP x  Optionally: Restore VMM LP state saved before 
TDH.VP.ENTER . 
5 VMM  N/A LP LP x  Perform TDG.VP.VMCALL  function, as determined 
by the TD -VMM software contract (out of the 
scope for this document) . 
6 VMM  N/A LP LP x Save VMM LP state not preserved across TD Entry 
to TD exit . 
7 VMM  TDH.VP.ENTER  VCPU/LP  LP x Restore LP state from TDVPS (except most GPRs 
and all XMMs) .  Enter SEAM  non-root mode . Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 38 of 153 
Section 1:  Introduction and Overview  Phase   Side  Intel TDX  
8 TD N/A VCPU/LP  LP x Parse TDG.VP.VMCALL  output operands as 
determined by TD  – VMM  software contract . 
TD Execution  TD continues execution in SEAM  non-root mode . 
 
 TD VCPU Entry, Exit on Asynchronous Event and Re -Entry  
Table 3.12:  Typical TD Entry, Exit on Asynchronous Event and Re -Entry  Sequence  
TD Entry  1 VMM  N/A LP LP x Save LP state not preserved across TD Entry to TD exit.  
2 VMM  TDH.VP.ENTER  VCPU/LP  LP x Restore LP state from TDVPS .  Enter SEAM  non-root 
mode.  
TD executes in TDX non -root mode.  
Async . TD 
Exit and Re -
Entry  3 TD N/A VCPU/LP  LP x  Asynchronous event (interrupt, exception, EPT 
violation, etc.) causes TD exit.  Save LP state to TDVPS 
and set synthetic state.  
4 VMM  N/A LP LP x  Restore any required LP state saved by the VMM 
before TDH.VP.ENTER .

mode.  
Async . TD 
before TDH.VP.ENTER . 
5 VMM  N/A LP LP x  Handle the asynchronous event.  
6 VMM  N/A LP LP x Save VMM LP state not preserved across TD Entry to 
TD exit.  
7 VMM  TDH.VP.ENTER  VCPU/LP  LP x Restore LP state from TDVPS and enter SEAM  non-root 
mode.  
TD 
Execution  TD continues execution in SEAM  non-root mode.  
 
 Guest -Side Functions  5 
TDG.MR.REPORT
VM entryVM entry
Async. TD Exit (EPT Violation)
 
Figure 3.6:  Typical Guest -Side Function Sequences  
November 2023   . Page 39 of 153 
Section 1:  Introduction and Overview  Table 3.13:  Typical Guest -Side Functions  Sequences  
Case   Side  Intel TDX  
Guest -Side 
Function 
Returns to 
Guest TD  TD executes in SEAM  non-root mode  
1 TD TDG.MR.REPORT  VCPU/LP  LP x  The gu est TD VM exits to  the Intel TDX module , which   
handles the guest -side function and re -enters the TD.  
TD continues execution in SEAM  non-root mode  
Function 
Causes 
Async. TD 
Exit 2 TD TDG.MR.REPORT  VCPU/LP  LP x  The guest TD exits to the Intel TDX module , which 
handles the guest -side function, but an asynchronous 
event (e.g., EPT violation, etc.) causes TD exit.  
3 VMM  N/A LP LP x  Optional:  The host VMM restores the VMM LP state 
saved before TDH.VP.ENTER . 
4 VMM  N/A LP LP x  The host VMM handles the asynchronous event.  
5 VMM  N/A LP LP x The host VMM saves any VMM LP state not preserved 
across TD Entry to TD exit.  
6 VMM  TDH.VP.ENTER  VCPU/LP  LP x The Intel TDX module  restores LP state from TDVPS 
and enter s SEAM  non-root mode.  
 
 TD VCPU Rescheduling (Migration to Another LP)  
The Intel TDX module is designed to allow a  TD VCPU to be associated with  at most one LP at any time.  The host VMM 
must explicitly break this association in order to migrate the VCPU to another LP . 5 
Table 3.14:  Typical VCPU Migration to Another LP  Sequence  
Phase   Intel TDX  
Function  Scope  Execute On Description  
Old 
VCPU→LP 
Association  1 Any VCPU -specific 
SEAMCALL leaf  VCPU  Old LP  Any VCPU -specific SEAMCALL leaf (e.g., TDH.VP.INIT , 
TDH.VP.ENTER , TDH.VP.RD , etc.) creates an 
association between the current LP and the VCPU.  
Breaking 
Old 
VCPU→LP 
Association  2 TDH.VP.FLUSH  VCPU  Old LP  Break the VCPU -LP association:  flush the VCPU’s TD 
VMCS to TDVPS memory and flush the VCPU’s TLB 
ASID.  
At this point the VCPU is not associated with any LP . 
New 
VCPU→LP 
Association  3 Any VCPU -specific 
SEAMCALL leaf  VCPU  New LP  Create a new VCPU -LP association . 
November 2023   . Page 40 of 153 
Section 1:  Introduction and Overview  3.4. TD Destruction  
The following sequence is intended to be used by the host VMM to destroy a TD and reclaim all its resources.  
Intel TDX 
IPI
TDH.PHYMEM.CACHE.WB(RESUME)
SuccessTDH.VP.FLUSH(TDVPR)
On all LPs associated with the TD
TDH.MNG.VPFLUSHDONE(TDR)
TDH.PHYMEM.CACHE.WB(START)
Interrupted
 
Figure 3.7:  Typical TD Destruction Sequence Step A:  Stopping and Flushing Out  
 5 
Intel TDX 
TDH.MNG.KEY.FREEID(TDR)
loop
For each private page, S -EPT page and control structure page except TDR
TDH.PHYMEM.PAGE.RECLAIM(Page HPA)
TDH.PHYMEM.PAGE.RECLAIM(TDR)
TDH.PHYMEM.PAGE.WBINVD(TDR, HKID)
 
Figure 3.8:  Typical TD Destruction Sequence Step B:  Resource Reclamation  Intel® TDX Module Base Spec  Section 1:  Introduction and Overview  348549 -003US  
November 2023   . Page 41 of 153 
Section 1:  Introduction and Overview  Table 3.15:  Typical TD Destruction  Sequence  
 Step   Description  SEAMCALL Leaf Function s 
A TD Stopping 
and Flushing 
Out 1 The host VMM  selects a TD to destroy.  It sends a virtual 
interrupt to the TD to shut down gracefully.  TDH.VP.FLUSH  
TDH.MNG.VPFLUSHDONE  
TDH.PHYMEM.CACHE.WB  2 The host VMM  broadcasts inter -processor interrupts (IPIs) and 
must  ensure TD exit on all logical processors.  
3 The host VMM  calls the TDH.VP.FLUSH  function  on all LPs 
associated with a TD VCPU to flush the TLBs and cached TD VMCS 
associated with a TD VCPU on those LPs . 
4 The host VMM  calls the TDH.MNG.VPFLUSHDONE  function .  It 
checks  that above step executed for all  the TD’s VCPUs are 
associated with an LP . 
5 The host VMM  calls the TDH.PHYMEM.CACHE.WB  function  on 
each WBINVD domain  to write back to memory  the TD contents 
from all caches . 
TDH.PHYMEM.CACHE.WB  is interruptible by external events.  The 
host VMM should restart it if it indicates it was interrupted, until 
6 At this point, no address translations or cache lines may exist for 
this TD except for the TDR page .   
B Resource 
Reclamation  1 The host VMM calls the TDH.MNG.KEY.FREEID  function .  It marks 
the HKID used by the TD as available for other TDs.  TDH.MNG.KEY.FREEID  
 2 For each physical page in TDMR allocated to the TD (TD private 
pages, Secure EPT pages, and control structures except TDR), the 
host VMM calls the TDH.PHYMEM.PAGE.RECLAIM function to 
mark the page as free and initializes its content using 
MOVDIR64B.  
3 The host VMM calls the TDH.PHYMEM.PAGE.RECLAIM  function to 
mark the TDR page as free.  The function checks  that all other TD 
physical pages have been reclaimed before.  
4 Before allocating the reclaimed TDR physical page to any use, the 
host VMM calls TDH.PHYMEM.PAGE.WBINVD to flush its cache 
lines and initializes its content using MOVDIR64B.  
 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 42 of 153 
Section 2:  Intel TDX Module Architecture Specification  SECTION  2: 
INTEL  TDX MODULE ARCHITECTURE SPECIFICATION  
November 2023   . Page 43 of 153 
Section 2:  Intel TDX Module Architecture Specification  4. Intel TDX Module Lifecycle:  Enumeration, Initialization and Shutdown  
This chapter discusses the design of the Intel TDX module life cycle:  how its capabilities are enumerated by the host 
VMM, how it is initialized, how it is configured and how it is shut down.  
4.1. Overview  
TDX module lifecycle use cases are described in 3.1. 5 
4.1.1.  Intel TDX Module Lifecycle  State Machine  
The Intel TDX lifecycle  state machine  helps track the module’s life cycle through the initialization sequence and shutdown.  
SYSINIT_PENDING
Intel TDX module is 
pending global 
initalization
SYS_READY
readySYSINIT_DONE
Intel TDX module 
global initialization 
doneTDH.SYS.CONFIG
[All LPs
initialized]TDH.SYS.INITTDH.SYS.LP.INITTDH.SYS.INFO or
TDH.SYS.RD/RDM
[LP initialized]
SYS_SHUTDOWN
has been shut down.
TDH.SYS.SHUTDOWNTDH.SYS.TDMR.INITTDH.SYS.KEY.CONFIG
[Non -last package]
All other
 SEAMCALL
leaf functionsSYSCONFIG_DONE
global configuration 
done
TDH.SYS.KEY.CONFIG
[Last package]TDH.SYS.UPDATE
[All LPs initialized]
 
Figure 4.1:  Intel TDX Module Lifecycle State Machine  on Server Platforms  
 10 
Table 4.1:  Intel TDX Module Lifecycle States  
State Name  Description  Allowed SEAMCALL Leaf Functions  
SYSINIT_PENDING  TDH.SYS.INIT has not been called 
yet. TDH.SYS.INIT  
SYSINIT_DONE  TDH.SYS.INIT has completed 
successfully.  TDH.SYS.LP.INIT must 
be called on each LP.  TDH.SYS.LP.INIT  
TDH.SYS.RD* (if current LP has been initialized)  
TDH.SYS.INFO (if current LP has been initialized)  
TDH.SYS.CONFIG (if all LPs have been initialized)  
TDH.SYS.UPDATE (if all LPs have been initialized)  
SYSCONFIG_DONE  TDH.SYS.CONFIG has completed 
successfully.  
TDH.MNG.KEY.CONFIG must be 
called on each package.  TDH.SYS.KEY.CONFIG  
TDH.SYS.RD*  
TDH.SYS.INFO  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 44 of 153 
Section 2:  Intel TDX Module Architecture Specification  State Name  Description  Allowed SEAMCALL Leaf Functions  
SYS_READY  The Intel TDX module is ready for 
use.  Any 
SYS_SHUTDOWN  Shutdown operation has been 
initiated.   No new host -side 
interface functions can be called.  None  
 
4.1.2.  Platform Compatibility and Configuration Checking  
 Overview  
The Intel TDX module  is built assuming a certain set of core and platform features.  Most platform configuration required 
to support the Intel TDX module is checked by MCHECK.  However, some configuration is designed to be checked by the 5 
Intel TDX module.  During the initialization process, the Intel TDX module is designed to check that the platform on which

use.  Any 
 
 Overview  
Intel TDX module.  During the initialization process, the Intel TDX module is designed to check that the platform on which 
it is running is compatible with this core and platform feature set and/or that the same set of features is provided across 
the platf orm.  Some of the checks are done per core, and some are done per package.  Most of the details are part of the 
Intel TDX module detailed design.  
 CPU Configuration  10 
During platform boot, MCHECK verifies all logical CPUs to ensure they meet TDX’s security and certain functionality 
requirements, and MCHECK passes the following CPU configuration information to the NP -SEAMLDR, P -SEAMLDR and 
the TDX Module:  
• Total number of logical processors in the platform.  
• Total number of installed packages in the platform.  15 
• A table of per -package CPU family, model and stepping etc. identification, as enumerated by CPUID(1).EAX.  
The above information is static and does not change after platform boot and MCHECK run.  
Note:  TDX doesn’t support adding or removing CPUs from TDX security perimeter, as checked my MCHECK.   BIOS 
should prevent CPUs from being hot -added or hot -removed after platform boots.  
The TDX module performs additional checks of the CPU’s configuration and supported features, by reading MSRs and 20 
CPUID information as described in the following sections.  
 MSR Sampling and Checks  
TDH.SYS.INIT reads and checks the contents of some MSRs.  In many cases, the MSR value read by TDH.SYS.INIT is also 
checked for consistency (i.e., having the same values) by TDH.SYS.LP.INIT.  In other cases, TDH.SYS.LP.INIT may perform 
additional checks.  25 
 CPUID Sampling, Checks and Enumeration  
Note:  CPUID virtualization is described in 11.8 . 
The TDH.SYS.INIT and TDH.SYS.LP.INIT functions  sample CPUID leaf and sub -leaf return values.  This is intended to check 
compatibility with the Intel TDX module and with any guest TD operation.  If any of these checks fail, Intel TDX module  
initialization is designed to fail.   30 
The TDH.SYS.RD, TDH.SYS.R DALL  and TDH.SYS.INFO functions may be called by the host VMM to enumerate the directly 
configurable and allowable CPUID fields.  
4.1.3.  Physical Memory Configuration Overview  
Configuration of the physical memory available to the Intel TDX module (TDMRs) and its associated metadata (PAMT 
arrays) is done using the TDH.SYS.CONFIG function.  35 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 45 of 153 
Section 2:  Intel TDX Module Architecture Specification  
 Intel TDX ISA Background:  Convertible Memory Ranges (CMRs)  
A 4KB memory page is  defined as  convertible  if it can be used to hold a n Intel  TDX private memory page or any Intel TDX 
control structure pages while helping guarantee Intel TDX security properties (i.e., if it can be converted  from a Shared 
page to a private  page).  
Convertible Memory Ranges  (CMRs ) are defined as contiguous convertible physical address ranges, declared by BIOS.  5 
CMRs are checked by MCHECK during platform boot to help ensure their configuration matches TDX security.  All memory 
within each CMR must be convertible and must be present when checked by MCHECK during platform boot.  CMRs are 
static and do not change aft er platform boot and checking by MCHECK.  
Note:  The above definition implies that TDX does not support hot -plugin or hot -removal of convertible memory.  BIOS 
should prevent hot removal  of convertible memory after platform boot.  10 
CMRs have the following characteristics:  
• CMR  configuration is “soft” – no h ardware range registers are used.  
• Each CMR  defines a single conti guous physical address range.  
• All the memory within each CMR is convertible, and it must comply with the rules checked by MCHECK.  
• Each CMR  has its own size.   CMR size is a multiple of 4KB, and it is not required to be a power of two . 15 
• CMRs c annot overlap with each other . 
• CMR s must reside within the effective physical address range of the platform (after considering  the most significant 
PA bits stolen for Key IDs).  
• CMR s are configured  at platform  scope  (no separate configuration  per package).  
• The maximum number of CMR s is implementation  specific .  It is not explicitly enumerated; it is deduced from 20 
Family/Model/Stepping information provided by CPUID.  
o The maximum number of CMRs is 32.  
• CMRs are available on systems with TDX ISA  capabilities , as enumerated by  bit 5 of the 
IA32_VMX_PROCBASED_CTLS3 MSR.  
• CMR configuration  is checked  by MCHECK and cannot  be modified afterwards.  25 
MCHECK stores the CMR table, and other platform topology information, in a pre -defined location in SEAM range, so it 
can be read later and trusted by the P -SEAMLDR module.  On TDX module installation, P -SEAMLDR copies MCHECK data 
to another page in the SEA M range, which is accessible by the Intel TDX module.  
 TDMRs and PAMT Arrays Configuration  
TDMRs and PAMTs are described in 8.1.  This section provides an overview of their configuration and their relationships 30 
to CMRs.  
4.1.3.2.1.  Background:  Reserved Areas within TDMRs  
As described in 8.1, the Intel TDX module physical memory management is done using PAMT Blocks – each holding the 
metadata of a 1GB block of TDMR.  This implies that TDMR granularity must be 1GB.  
However, there is a requirement for the host VMM to be able to allocate memory at granularities smaller than 1GB.  This 35 
is especially important in systems that have a relatively small amount of memory.  
To support the two requirements above, the Intel TDX module’s design allows arbitrary reserved areas within TDMRs.  
Reserved areas are still covered by PAMT.  However, during initialization their respective PAMT entries are marked with 
a PT_RSVD page type,  so pages in reserved areas are not used by the Intel TDX module for allocating privately encrypted 
memory pages (but they can be used for PAMT areas, see below).  40 
Only the non -reserved parts of a TDMR are required to be inside CMRs.  
4.1.3.2.2.  Background:  Three PAMT Areas  
As described in 8.1, a logical PAMT Block is composed of 1 PAMT_1G entry, 512 PAMT_2M entries and 5122 PAMT_4K 
entries.  Thus, the overall size of a PAMT Block, and as a result of the whole PAMT, is not a power of 2.  
However, the host VMM may only be able to allocate memory buffers for PAMT in sizes that are a power of 2.  45 
To enable this, buffers for PAMT_1G entries, PAMT_2M entries and PAMT_4K entries are allocated separately.  As a 
result, if the host VMM allocates a TDMR whose size is a power of 2, its three respective PAMT areas will also have sizes 
that are a power of 2 . 
PAMT areas are required to be inside CMRs because PAMT is encrypted with a private HKID.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 46 of 153 
Physical Memory Space
CMR 1
CMR 0CMR 3
CMR 2
TDMR 0Reserved
ReservedTDMR 1
ReservedTDMR 2Reserved
1GB-Aligned1GB-Aligned1GB-Aligned1GB-Aligned
1GB-Aligned
PAMT_4K 0
PAMT_4K 1
PAMT_4K 2PAMT_2M 0PAMT_1G 0PAMT_2M 1PAMT_1G 1
PAMT_1G 2
PAMT_2M 2AvailableAvailable
AvailableAvailable
 
Figure 4.2:  Example of Convertible Memory Ranges (CMRs) vs. Trust Domain Memory Regions (TDMRs)  
4.1.3.2.3.  Configuration Rules  
In addition to the rules described in 8.1, the following rules apply to TDMR configuration as related to CMRs:  
• Any non -reserved 4KB page within a TDMR must be convertible – i.e., it must be within a CMR.  5 
• Reserved areas within a TDMR need not be within a CMR.  
Three PAMT areas must be configured for each TMDR – one for each physical page size controlled by PAMT:  
• Area for PAMT_4K entries  
• Area for PAMT_2M entries  
• Area for PAMT_1G entries  10 
PAMT areas have the following attributes:  
• A PAMT area size is directly proportional to the TDMR with which it is associated.  The size ratio is enumerated by 
TDH.SYS.RD/RD ALL or TDH.SYS.INFO.  Note that the size ratio may be different for each of the 3 PAMT array types.  
• A PAMT area must reside in convertible memory – i.e., each PAMT area page must be a CMR page.  
• PAMT areas must not overlap with TDMR  non-reserved areas; however, they may reside within TDMR reserved areas 15 
(as long as these are convertible).  
• PAMT areas must not overlap with each other.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 47 of 153 
Section 2:  Intel TDX Module Architecture Specification  4.2. Intel TDX Module Initialization Interface  
4.2.1.  Global Initialization:  TDH.SYS.INIT  
TDH.SYS.INIT is intended to globally initialize the Intel TDX module.  It works as follows:  
1. Initialize Intel TDX module global data.  
2. Sample and check  platform features that need to be checked for platform -wide compatibility – i.e., the Intel TDX 5

2. Sample and check  platform features that need to be checked for platform -wide compatibility – i.e., the Intel TDX 5 
module  supports several options, but they must be the same across platform.  These are later checked on each LP.  
3. Sample and check the platform configuration on the current LP.  For example, TDH.SYS.INIT samples SMRR and 
SMRR2, checks they are locked and do not overlap any CMR, and stores their values to be checked later on each LP.  
4. Set the system state to SYSINIT_DONE.  
For a detailed description of TDH.SYS.INIT, see the [ TDX Module ABI Spec ]. 10 
4.2.2.  LP-Scope Initialization:  TDH.SYS.LP.INIT  
TDH.SYS.LP.INIT is intended to perform LP -scope, core -scope and package -scope initialization of the Intel TDX module.  It 
can be called only after TDH.SYS.INIT completes successfully, and it can run concurrently on multiple LPs.  At a high level, 
TDH.SYS.L P.INIT works as follows:  
1. Do a global EPT flush (INVEPT type 2).  15 
2. Initialize Intel TDX module LP -scope data.  
3. Check features and configuration compatibility and uniformity – once per LP, core or package, depending on the 
scope of the checked feature or configuration:  
3.1. Check features compatibility with the Intel TDX module.  
3.2. Check configuration uniformity.  20 
For a detailed description of TDH.SYS.LP.INIT, see the [ TDX Module ABI Spec ]. 
4.2.3.  TDX Module Enumeration:  TDH.SYS.RD /RDALL and TDH.SYS.INFO  
Once an LP has bee n initialized, the host VMM can call TDH.SYS.RD, TDH.SYS.RDALL or TDH.SYS.INFO on that LP to help 
enumerate the Intel TDX module capabilities and platform configuration.   
TDH.SYS.RD  and TDH.SYS.RDALL are the recommended enumeration methods.  They enable the host VMM to read the 25 
values of TDX module global metadata fields, enumerating the TDX module capabilities.  The list of fields is described in 
the [ TDX Module ABI Spec ]. 
To read all host readable TDX Module fields, the host VMM can invoke TDH.SYS.RDALL.  This function returns the 
information as a metadata list.  
To read a single TDX Module field, TDH.SYS.RD can be invoked.  It returns the next host -readable field identifier, thus it 30 
can also be used to enumerate the TDX Module by calling it in a loop, starting from field identifier value of 0, until it 
returns a next field identifier value of 0.  
TDH.SYS.INFO is provided for backward compatibility with previous TDX module versions:  
• Intel TDX module capabilities are enumerated in the returned TDSYSINFO_STRUCT (see the [ TDX Module ABI Spec ]). 
• Convertible Memory Ranges (CMRs), as previously set by BIOS and checked by MCHECK, are enumerated in the 35 
returned CMR_INFO table.  
For a detailed description of interface functions and metadata fields, see the [ TDX Module ABI Spec ]. 
4.2.4.  TDH.SYS.CONFIG:  TDX Module Global Configuration  
After performing global and LP -scope initialization, t he host VMM can call TDH.SYS. CONFIG to globally configure the Intel 
TDX module , providing the following information:  40 
• TDMR and PAMT Table, where each entry contains  a TDMR base address , size and c orresponding PAMT reserved 
area base address and size .  Refer to 8.1 for definition of TDMRs.  
• The HKID  to be used by the Intel TDX module  for its global private key, used for encrypting PAMT and TDRs.  
For a detailed description of  the table format (TDMR_INFO) and TDH.SYS. CONFIG, see the [ TDX Module ABI Spec ]. Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 48 of 153 
Section 2:  Intel TDX Module Architecture Specification  4.2.5.  TDH.SYS.KEY.CONFIG:  Key Configuration  (per Package)    
After performing global configuration, the host VMM calls TDH.SYS.KEY.CONFIG to perform package -scope configuration 
of the Intel TDX module’s global private key on the hardware.  
For a detailed description of TDH.SYS.KEY.CONFIG, see the [ TDX Module ABI Spec ]. 
4.2.6.  State Restoration  after TD -Preserving TDX Module Update:  TDH.SYS.UPDATE  5 
When updating the TDX module, the host VMM can calls TDH.SYS.UPDATE after initializing the new TDX module on all 
LPs, so that the new TDX module will update itself with the handoff data prepared by a call to the TDH.SYS.SHUTDOWN 
API on the previous TDX mod ule.  This allows “old” TDs, which were created by previous TDX module(s), to keep running 
under the supervision of the new TDX module.  
If TDH.SYS.UPDATE returns successfully, the TDX module is ready, and TDH.SYS.CONFIG and TDH.SYS.KEY.CONFIG cannot 10 
(and need not) be called anymore.  
If TDH.SYS.UPDATE returns error, then the host VMM can continue with the non -update sequence (TDH.SYS.CONFIG, 
TDH.SYS.KEY.CONFIG etc.).  In this case all existing TDs are lost.  Alternatively, the host VMM can request the P -SEAMLDR 
to update to another TDX module.  If that update is successful , existing TDs are preserved.  
For a detailed description of TDH.SYS.UPDATE, see the [ TDX Module ABI Spec ]. 15 
4.3. TDMR and PAMT Initialization  
TDMR and PAMT initialization procedure is designed to be performed during VMM run -time , after VMM boot.  The host 
VMM should be able to work normally while initialization takes place, at any time using memory that has already been 
initialized.  At a high level, TDMR initialization has the following characteristics:  
• Initialization is performed gradually.  20 
• Initialization function TDH.SYS.TDMR.INIT adheres to the latency rules of most Intel TDX functions – i.e., they take 
no more than a predefined number of clock cycles.  
• Initialization function TDH.SYS.TDMR.INIT can run concurrently on multiple LPs  if each concurrent flow initializes a 
different TDMR . 
• After each 1GB page of a TDMR has been initialized, that 1GB page becomes available for use by any Intel TDX 25 
function that creates a private TD page or a control structure page – e.g., TDH.MEM.PAGE.ADD, TDH.VP.ADDCX, etc.  
For each TDMR, the VMM should execute a loop of TDH.SYS.TDMR.INIT  providing the TDMR start address (at 1GB 
granularity)  as an input.  
TDH.SYS.TDMR.INIT initializes an (implementation -defined) number of PAMT entries.  The maximum number of PAMT 
entries to be initialized is designed to avoid latency issues.  Initialization uses direct writes (MOVDIR64B).  30 
Once the PAMT for each 1GB block of TDMR has been fully initialized, TDH.SYS.TDMR.INIT marks that 1GB block as ready 
for use; that means 4KB pages in this 1GB block may be converted to private pages – e.g., by TDH.MEM.PAGE.ADD.  This 
can be done concurrent ly with adding and initializing other TDMRs.  
For a detailed description of TDH.SYS.TDMR.INIT, see the [ TDX Module ABI Spec ]. 
4.4. Intel TDX Module Shutdown  35 
4.4.1.  Shutdown Initiated by the Host VMM (as Part of Module Update)  
The host VMM can initiate Intel TDX module shutdown at any time by calling the TDH.SYS.SHUTDOWN function.  This is 
intended for use as part of updating the Intel TDX module without going through a warm or cold reset sequence.  
TDH.SYS.SHUTDOWN is designed to set state variables to block all SEAMCALL leaf functions.   
TDH.SYS.SHUTODWN also prepares handoff data in a designated area in SEAM range called handoff data range.  The 40 
handoff data contains any TDX module state (in SEAM range) required to preserve old TDs across TDX module updates.  
This includes (but not limited to) Key Ownership Table (KOT) and TDMR management table.  When a new TDX module is 
installed using the “updat e” scenario, the P -SEAMLDR module preserves (doesn’t wipe -out) the handoff data range.  The 
new TDX module can then update itself (when the TDH.SYS.UPDATE function is called) from that handoff data.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 49 of 153 
Section 2:  Intel TDX Module Architecture Specification  4.4.2.  Shutdown Initiated by a Fatal Error  
By design, fatal errors during Intel TDX module execution cause an immediate SEAM shutdown.  Subsequent SEAMCALLs 
on any LP fail with a VMfailInvalid indication (RFLAGS.CF set to 1).  This situation can only be recovered by a platform 
reset.  
4.5. Intel TDX Module Handoff Data  5 
In order to preserve TDs across Intel TDX module updates, the old TDX module’s TDH.SYS.SHUTDOWN function prepares 
handoff data in the handoff data region, to be consumed by the new TDX module’s TDH.SYS.UPDATE function.  The 
handoff data contains all variab les maintained inside SEAM range (i.e., module’s global and local data) related to TD 
management.  Note that TD code, data and metadata pages residing out of SEAM range need not be passed, since the 
DRAM contents and MKTME state are not impacted.  10 
Since it’s possible – and normally expected – that the new TDX module would differ from the old TDX module it’s 
replacing, it’s necessary that the new TDX module will understand the syntax and semantics of all TD metadata – either 
in the handoff data range  and out of SEAM range – that the old TDX module left behind, including PAMT, Secure EPTs,

reset.  
in the handoff data range  and out of SEAM range – that the old TDX module left behind, including PAMT, Secure EPTs, 
TDRs, TDCS and TDVPS pages.  To support that, a handoff protocol is needed.  
The handoff protocol is based on the notion of Handoff Version  (HV) – an unsigned 16 -bit number which identifies the 15 
contents, syntax and semantics of all TD metadata fields, in the handoff data region and out of SEAM range, that the old 
TDX module passes to the new TDX module.  The TDX module may understand one or more HVs.  This allows the new 
module to consume handoff  data prepared by an older TD module and “upgrade” it with new contents (e.g., put data in 
TDVPS fields that were previously reserved).  
In preparation to TD -preserving TDX module update, the host VMM calls the TDH.SYS.SHUTDOWN function with 20 
“requested HV” parameter.  If the TDX module understands the requested HV and was not built as “non -downgradable” 
(see below), then the TDH.SYS.SHUTDOWN prepares  handoff data with the requested syntax and semantics in the 
handoff data region ; it marks the handoff data region as valid with the requested HV (see [P -SEAMLDR FAS] for the 
structure of the 64 -bit handoff data region’s header that contains this information).  
After P -SEAMLDR updated the TDX module in SEAM range, the host VMM initializes the new TDX module, and calls its 25 
TDH.SYS.UPDATE function which consumes  the handoff data and marks it as invalid.  
Specifically, each TDX module is built with the following constants:  
Table 4.2:  TDX Module Handoff Constants  
Name  Meaning  Description  
MODULE_HV  Module Handoff Version  Handoff version that this TDX module works with  
MIN_UPDATE_HV  Minimum Updatable 
Handoff Version  The “oldest” HV this TDX module understands  
NO_DOWNGRADE  No-Downgrade Flag  A non -zero value indicates that this TDX module cannot 
“downgrade” the data is leaves behind to a lower handoff 
version  
 
The above constants must satisfy the inequality 0 <= MIN_UPDATE_HV  <= MODULE_HV.  If 30 
MIN_UPDATE_HV  < MODULE_HV, then this TDX module can consume (in TDH.SYS.UPDATE) older handoff data (i.e., data 
whose syntax/semantics has lower HV than the syntax/semantics this TDX module was built to work with).  In addition, 
if the NO_DOWNGRADE flag is zero, them this TDX module can generate (in TDH.SYS.SHUTDOWN) older handoff data.  
The following table illustrates this protocol with several examples . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 50 of 153 
Section 2:  Intel TDX Module Architecture Specification  Table 4.3:  TDX Module Handoff Protocol Examples  
Old TDX M odule’s 
Parameters  New TDX M odule’s 
Parameters  Requested HV 
to Old TDX 
Module’s 
TDH.SYS.  
SHUDOWN  HV of Handoff 
Data Prepared 
by Old TDX 
Module  Module Update by P -
SEAMLDR  New TDX M odule’s 
TDH.SYS.UPDATE 
Action  
MODULE_HV=10  
MIN_UPDATE_HV=10  
NO_DOWNGRADE=0  MODULE_HV=10  
NO_DOWNGRADE=0  10 10 Installed  Consume as is  
NO_DOWNGRADE=0  11 None 
(shutdown 
failed – 
requested HV 
is too large)  Not installed (invalid 
handoff data)  
Note: the host VMM 
can install using 
“Load” scenario  Fail (invalid handoff 
data)  
should re -configure 
the new TDX module 
(TDs are not 
preserved)  
NO_DOWNGRADE=0  9 None 
(shutdown 
failed – 
is too small)  Not installed (invalid 
data)  
NO_DOWNGRADE=0  MODULE_HV=11  
NO_DOWNGRADE=0  10 10 Installed  Upgrade to 11 and 
consume  
MODULE_HV=11  
NO_DOWNGRADE=0  10 10 
(downgraded ) Installed  Consume as is  
NO_DOWNGRADE=0  11 11 Not installed (HV -
incompatible module)  
“Load” scenario.  Fail (invalid handoff 
data)  
preserved).  
NO_DOWNGRADE=1  MODULE_HV=10  
NO_DOWNGRADE=0  10 Shutdown 
failure (can’t 
downgrade)  Not installed (invalid 
data)  
preserved).  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 51 of 153 
Section 2:  Intel TDX Module Architecture Specification  5. Memory Encryption Key Management  
5.1. Objectives  
The main goal of Intel TDX key management is to enable the VMM  to perform the following:  
• Manage HKID  space as a limited platform resource, assigning HKID s to TDs and reclaiming them as required.  
• Enable the Intel TDX module  to use a global ephemeral key for encrypting its data (e.g., PAMT).  5 
• Enable  each TD to use its own ephemeral key.  
The Intel TDX interface functions  are designed to provide the required building blocks and help ensure  that software 
cannot  perform operations that are not compliant with TDX security objec tives, as follows:  
1. Help ensure  that only HKID values that have been configured for TDX private memory encryption keys can be 
assigned to TDs, and that those HKID values cannot  be used by non -TD software or devices.  10 
2. Prevent assignment of the same HKID to more than one TD.  
3. At the time  an HKID  is assigned to a TD, there must be no modified  cache lines  – at any level , for any core  – for that 
HKID .  All such cache lines that may have held modified data have been written to memory (if required) .  Note that 
this requirement applies only to TDX private HKID and not to legacy MKTME  HKIDs.  
4. TD memory may be accessed, and the TD may run, only when the following condition s are met:  15 
4.1. An HKID has been assigned for the TD’s ephemeral key . 
4.2. The encryption key ha s been configured for all the TD’s  ephemeral  HKID , on all crypto engines , on all packages.  
5.2. Background:  HKID Space Partitioning  
Since the same MKTME encryption engines and the same set of encryption keys are used for legacy MKTME operation 
and for TDX operation, TDX ISA  enables the enumeration and partitioning of the activated HKID space between the two 20 
technologies.  As designed, t he encryption keys and their associated HKIDs are divided into three ranges , as shown in 
Table 5.1 below .  The values of NUM_ HKID_KEYS and NUM_TDX_PRIV_KEYS are read from the 
IA32_MKTME_KEYID_PARTITIONING MSR (0x87).  
Private HKIDs and private keys are designed to be  fully controlled by the Intel TDX module  and are the subject of this 
chapter.  25 
Table 5.1:  HKID Space Partitioning  
 HKID  Key 
Shared 
HKIDs  0 Legacy TME key, shared  
1 Legacy MKTME key #1  
2 Legacy MKTME key #2  
… … 
NUM_ HKID_KEYS  Last legacy MKTME key  
Private 
HKIDs  NUM_ HKID_KEYS + 1  Private key of a specific TD  
NUM_ HKID_KEYS + 2  Private key of a specific TD  
NUM_ HKID_KEYS + 3  Private key of a specific TD  
… … 
NUM_ HKID_KEYS + NUM_TDX_PRIV_KIDS  Private key of a specific TD  
November 2023   . Page 52 of 153 
Section 2:  Intel TDX Module Architecture Specification  5.3. WBINVD Domains  
TDX memory encryption key management requires flushing caches.  The TDH. SYS.CACHE.WB  and 
TDH.PHYMEM.CACHE.WB  interface function s (as well as the CPU instructions WBINVD and WBNOINVD) flush caches in 
a WBINVD domain .  The extent of this domain depends on the CPU architecture.  For older processors, a WBINVD 
domains includes all LPs single package.  For newer processors, a WBINVD domain may include a group of LPs within a 5 
package.  TDX operations that involve TDH.SYS.CACHE.WB or TDH.PHYMEM.CACHE.WB requires it to be executed on one 
LP per WBINVD domain in the platform.  
The host VMM can determine whether the processor’s WBINVD domains are less than a whole package using 
TDH.SYS.RD* to read TDX_FEATURES0.WBINVD_DOMAINS (bit 15).  If the value of this bit is 0, then each package is a 
single WBINVD domain.  10 
 
5.4. Key Management Tables  
The CPU and the Intel TDX module  maintain several tables for key management.  No table is intended to be directly 
accessible by software; the tables are used by the Intel TDX function s.  The tables help the Intel TDX module  track the 
proper operation of the software and help achieve the Intel TDX security objectives.  15 
Table 5.2:  Key Management Tables  
Table  Scope  Description  
Key Encryption 
Table (KET)  Package  KET is an abstraction of the CPU micro -architectural hardware table for

Table (KET)  Package  KET is an abstraction of the CPU micro -architectural hardware table for 
configuring the memory encryption engines.  The KET is indexed by HKID.  All 
crypto engines on a package are configured the same way.  
KET is part of the legacy MKTME architecture.  Intel TDX ISA partitions KET to 
shared and private ranges, as described in 5.2 above . 
• A KET entry in private HKIDs range is configured per package by the host 
VMM using the SEAMCALL(TDH.MNG.KEY.CONFIG) function.  
• A KET entry in the shared HKID range is configured by software per package 
directly, using the PCONFIG instruction.  
KeyID 
Ownership 
Table (KOT)  Platform  KOT is an Intel TDX module hidden table for managing the TDX HKIDs inventory.  
It is used for assigning HKIDs to TDs, revoking HKIDs from TDs and controlling 
cache flush.  
KOT is indexed by HKID.  
TD Key 
Management 
Fields  TD TD-scope key management fields are held in TDR.  They include the key state, 
ephemeral private HKID and key information, and a bitmap for tracking key 
configuration.  
 
Figure 5.1 below  provides a n abstract, high -level picture of how the tables are related.  Detailed discussion is provided in 
the following sections.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 53 of 153 
HKID
8
HKID Key
0 TME Key
1 MKTME Key
… …
8 TDX Key
9 TDX Key
10 TDX Key (N/A)
11 TDX Key (N/A)
… …
64 TDX Key (N/A)HKID
8
Package -Scope
Key Encryption Tables (KET)
In each crypto engine, per memory 
controller, multiple per packageGlobal -Scope KeyID Ownership Table (KOT)
Internal to the Intel TDX moduleLifecycle State HKID
TD_KEYS _CONFIGURED 8TD-Scope Key Information
In TDR
TD 1VCPU -Scope Private KeyID
In TD VMCS
CPU uses this value to setup h/w on TD entry
HKID State
0 N/A
1 N/A
… …
8 HKID_ASSIGNED
9 HKID_FLUSHED
10 HKID_FREE
11 HKID_FREE
… …
64 HKID_ASSIGNEDLifecycle State HKID
TD_HKID _ASSIGNED 64TD-Scope Key Information
In TDR
TD 2
Lifecycle State HKID
TD_BLOCKED 9TD-Scope Key Information
In TDR
TD 3HKID Key
0 TME Key
1 MKTME Key
… …
8 TDX Key
9 TDX Key
… …
64 TDX Key (N/A)HKID Key
0 TME Key
1 MKTME Key
… …
8 TDX Key
9 TDX Key
… …
8
 
Figure 5.1:  Overview of the Key Management State at TD -Scope, LP -Scope, Package -Scope and Global -Scope  
5.5. Combined Key Management State  
Key management state is composed of two state variables:  
• Per-HKID KOT Entry S tate  is designed to control how  the inventory of private HKIDs is managed using the KOT . 5 
• Per-TD Life Cycle S tate  is designed , among other things, to control how  TD keys are configured on the hardware and 
the process of shutting down a TD . 
The combined key management state is intended to affect whether the TD private memory is accessible , whether its 
contents may be cached , whether private GPA -to-HPA address translations are allowed and whether such translations 
may be cached.  10 
Table 5.3 below  lists the  designed  combined key management state values and their meaning.  Figure 5.2 below  shows a 
simplified diagram of the combined key state.  Refer also to the key management sequences described in 5.6. 
Table 5.3:  Combined TD Key Management States  
TD Life Cycle  State  KOT Entry (HKID) 
State   Private Memory 
Access  S-EPT 
Translations  Comments  
New  Cached  New  Cached  
N/A  HKID_FREE  No No No No HKID not assigned to TD  
TD_HKID_ASSIGNED  HKID_ASSIGNED  No No No No TD private k ey not configured  
TD_KEYS_CONFIGURED  TD TD TD TD TD build and execution  
TD_BLOCKED  HKID_FLUSHED  No TD No No TD private m emory access  is 
blocked , TD may not run  
TD_TEARDOWN  N/A (HKID_FREE)  No No No No TD has no HKID  
N/A  HKID_RESERVED  Global  Global  N/A N/A HKID for Intel TDX global data  
November 2023   . Page 54 of 153 
Section 2:  Intel TDX Module Architecture Specification   
HKID_ASSIGNED HKID_FREE
HKID_FLUSHEDTDH.MNG.CREATETD_HKID_
ASSIGNED
configuredTD_KEYS_
CONFIGURED
TD build and 
executionTDH.MNG.KEY.CONFIG
[last package]TDH.MNG.KEY.CONFIG
[non -last package]
TDH.MNG.VPFLUSHDONE
TDH.MNG.KEY.FREEID
TDH.PHYMEM.PAGE.RECLAIM
(non -TDR)TD doesn't exist
TD_BLOCKED
TD may not run, TD 
private memory 
access blocked
TDH.PHYMEM.CACHE.WBTDH.VP.ENTER
TDH.VP.FLUSH
 
Figure 5.2:  Simplified Combined TD Key Management State Diagram  
Chapter  7 discusses TD life cycle management and zooms -in into the TD_KEYS_CONFIGURED state, detailing its secondary 
sub-states  that control TD operation and TD migration.  5 
5.6. Key Management Sequences  
5.6.1.  Intel TDX Module  Initialization:  Setting an Ephemeral Key and Reserving  an HKID for Intel TDX Data  
This sequence is described as part of the Intel TDX module initialization sequence in 3.1. 
5.6.2.  TD Creation, Keys Assignment and Configuration  
This sequence is intended to be used by the host VMM  to create a new TD, select HKIDs from the global pool in KOT and 10 
assign them to the TD, and configure the TD keys on the hardware.  
Refer also to the software flow discussion in 3.2. 
Table 5.4:  Typical TD Creation, Keys Assignment and Configuration  (TD-Scope and KOT -Scope)  Sequence  
 Intel TDX  Function  Scope  Execute On Description  
1 TDH.MNG.CREATE  TD One LP  Assign the TD’s private HKID.  
2 TDH.MNG.KEY.CONFIG  TD Each package  Configure the TD’s random ephemeral key on the 
package . 
November 2023   . Page 55 of 153 
Section 2:  Intel TDX Module Architecture Specification  5.6.3.  TD Keys Reclamation, TLB and Cache Flush  
This sequence is intended to be used by the host VMM to reclaim the HKIDs assigned to a TD and return them to the 
global pool in KOT.  At the end of this sequence, the HKIDs should be  free to be assigned to a nother  TD. 
The cache flush operation is long.  Since it is designed to run at global scope and is decoupled from any TD, the  host  VMM 
may choose to implement it in a lazy fashion, i.e., wait until a certain number of HKIDs in the KOT pool become 5 
RECLAIMED.  This is especially important since TDH.PHYMEM.CACHE.WB  operates on all cache lines regardless of HKID.  
To avoid long latencies, TDH.PHYMEM.CACHE.WB  is designed to be  interruptible.  The host VMM is expected to repeat 
the execution of this instruction until it returns a success indication.  
Refer also to the software flow discussion in 3.4. 
Table 5.5:  Typical TLB and Cache Flush  (TD-Scope and KOT -Scope)  Sequence  10 
As a preparation, the host VMM avoids any VCPU -specific SEAMCALL function (i.e., TDH.VP.ENTER , TDH.VP.INIT , 
TDH.VP.RD  and TDH.VP.WR ) and waits until no VCPU is running.  
1 TDH.VP.FLUSH  TD 
VCPU  One each LP 
associated 
with a TD 
VCPU  Flush the VCPU’s TD VMCS to TDVPS memory and  
flush the VCPU’s TLB ASID.  
2 TDH.MNG.VPFLUSHDONE  TD, KOT  One LP  Check  all the VCPUs have been flushed.  
3 TDH.PHYMEM.CACHE.WB  KOT  Each WBINVD 
domain4 Write back cache hierarchy, at least for the HKIDs 
marked as TLB_FLUSHED.  The instruction 
execution time is long; it is interruptible by 
external events and may be restarted until 
completed.  
4 TDH.MNG.KEY.FREEID  TD, KOT  One LP  Mark TD’s HKID as FREE.  
 
4 Enumerated by CPU during Intel TDX module initialization, see 4.1.2.4 . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 56 of 153 
Section 2:  Intel TDX Module Architecture Specification  6. TD Non -Memory State (Metadata)  and Control Structures  
This chapter discusses the guest TD control structures  that hold non -memory state (metadata) and how they are intended 
TDCSTDCSTDXTD-scope
TDCX Page
* VMM may 
maintain a single 
copy per TD, shared 
by all VCPUs
Shared
EPT
TreeVCPU -scope*
VMCS Ancillary
Control StructuresVCPU -scope*
VMCS Auxiliary
Control StructuresShared:
TD-scope
TDVPSVCPU -scope
TDVPRTDVPRTDCX PageTDVPR PageSecure EPT TreeTD-scope
SEPT_PAGESEPT_PAGESEPT Page
TDVPRTDVPRMIGSC Page
Migration Stream Contexts
 5 
Figure 6.1:  Guest TD  Control Structures  Overview  (Not Including TD Partitioning and TDX Connect)  
All guest TD control structures reside in memory pages that are allocated by the host VMM from the pre -configured 
TDMRs.  Guest TD control structure pages are  addressable by the host VMM.  
6.1.1.  Opaque vs. Private vs. Shared Control Structures  
Control structures  are divided to two classes:  10

TDCX Page
* VMM may 
Shared
EPT
TD-scope
 5 
Control structures  are divided to two classes:  10 
• Shared control structures  are intended to be directly managed by the host VMM  and are encrypted with a shared 
HKID.  The Intel TDX module  architecture only describes the shared control structures that might directly impact its 
operation.  The host VMM may hold additional control structures.  
• Private control structures  are mapped to the guest TD’s GPA space and are directly accessible by it.  
• Opaque control structures  are not intended to be directly accessible to any software (except the Intel TDX module ) 15 
or DMA .  They are intended to be managed via Intel TDX module  function s.  Generally speaking, the host VMM is not 
aware of the exact format of opaque control structures.  Opaque control structures ’ memory pages are intended to 
be encrypted with a private HKID . 
6.1.2.  Scope of Control Structures  
Guest TD control structures have two possible scopes:  20 
• TD-scope control structures  are intended to a pply for a guest TD as a whole.  
• TD VCPU -scope control structures  are intended to a pply for a single virtual CPU of a guest TD.  
6.2. TD-Scope  Control Structure s 
TD-scope control structures include TDR and TDCS, discussed below, and Secure EPT, discussed in Chapter  9. Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 57 of 153 
Section 2:  Intel TDX Module Architecture Specification  6.2.1.  TDR (Trust Domain Root)  
TDR is the root control structure of a  guest  TD.  As designed, TDR is encrypted using the Intel TDX global private HKID.  It 
holds a minimal set of state variables that enable guest TD control even during times when the TD’s private HKID is not 
known, or when the TD’s key management state does not permit access to memory encrypted using the TD’s private key.  
TDR occupies a single 4KB naturally aligned page of memory.  It is designed to be the first TD page to be allocated and 5 
the last to be removed.  Its physical address serves as a unique identifier of the TD , as long as  any TD page or control 
structure resides in memory . 
At a high level, TDR holds the following information:  
• Fields designed to  control guest  TD build and teardown process . 
• Fields designed to manag e memory encryption keys . 10 
6.2.2.  TDCS  (Trust Domain Control Structure)  
TDCS is the main  control structure of a  guest  TD.  As designed, TDCS is encrypted using the guest TD’s ephemeral private 
key.  TDCS is  a multi -page logical structure composed of multiple TDCX physical pages.  
At a high level, TDCS holds the following information:  
• Fields designed to  control the TD operation as a whole  (e.g., a counter of the number of VCPUs currently running).  15 
• Fields designed to  control the TD’s execution control (debuggability, CPU features available to the TD, etc.).  
• Fields related to TD measurement.  
• EPTP:  as designed, a p ointer (HPA) to the TD’s secure EPT root  page and EPT attributes.  
• MSR bitmaps, designed to be used by all the TD’s VCPUs.  
• As designed, t he secure EPT root page.  20 
• A page filled with zero s, designed to be used in cases where the Intel TDX module  needs a read -only constant -0 page 
encrypted with the TD’s private key.  
TDCS may hold forward links to the following control structures:  
• Secure EPT pages.  
• Migration Stream Context (MIGSC) pages.  25 
6.3. TD VCPU -Scope  Control Structures  
6.3.1.  Trust Domain Virtual Processor State (TDVPS)  
Trust Domain Virtual Processor State (TDVPS)  is the root control structure of a TD VCPU.  It helps the Intel TDX module 
control the operation of the VCPU and  holds the VCPU state  while the VCPU is not running .  TDVPS is a single logical 
control structure composed of multiple physical 4KB pages . 30 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 58 of 153 
TDVPS TDVPS
TD VCPU
Management Fields
(mapped to TDVPR 
page)
TD VMCS
(not mapped in linear 
address space)TD VMCS Auxiliary Info
• Virtual APIC Page
• VE Info TD VCPU State
• GPRs
• CRs, DRs, MSRs
• Extended StateTDVPR Page
TDCX Page
TDCX PageTDCX Page
TDCX Page
Logical View Physical View
 
Figure 6.2:  High Level Logical and Physical View of TDVPS  
 Physical View  of TDVPS:  TDVPR/ TDCX  
TDVPS is designed to be opaque to software and DMA access, accessible only by using the Intel TDX module  function s.  
From the VMM  perspective, TDVPS is composed of multiple 4KB pages, where each page may reside in arbitrary locations 5 
in convertible memory.  
Trust Domain Virtual Processor Root ( TDVPR ) is the  4KB root page of TDVPS.  Its physical address serves as a unique 
identifier of the VCPU (as long as it resides in memory).  
Trust Domain Control structure  eXtension ( TDCX) 4KB pages  extend TDVPR to help provide enough physical space  for 
the logical TDVPS structure.  10 
The TDVPR and TD CX pages are designed to be encrypted with the TD’s ephemeral private key.  They are addressable by 
the host VMM , which  is responsible for allocating  memory to hold them.  
The required number of 4KB TDVPR/TD CX pages  in TDVPS  is enumerated to the VMM  by the TDH.SYS.RD * or 
TDH.SYS. INFO function (see 4.2.3 ). 
 Logical  View of TDVPS  15 
Logically , TDVPS is organized as a single large data structure.   At a high level, i t is composed of the following parts:  
VMX (with TDX ISA  Extensions) Standard Control Structures  
• TD VMCS  
• TD VMCS auxiliary structures, such as virtual APIC page, virtualization exception information, etc.  Note that MSR 
bitmaps are held as part of TDCS  because they are meant to have the same value for all VCPUs of the same TD . 20 
The TDX design does not require some of the VMX control structures (notably, the Shared EPT) to be protected.  They are 
described below.  
Proprietary Fields  
• TD VCPU Management fields designed to  manage the operation of the VCPU  
• TD VCPU State field s designed to  hold most of the VPCU state (except state that is saved to the TD VMCS) when the 25 
VCPU is not running  
TDVPS organization and format are detailed in  the [ TDX Module ABI Spec ]. Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 59 of 153 
Section 2:  Intel TDX Module Architecture Specification  6.3.2.  Non -Protected Control Structures:  Shared EPT and VMCS Auxiliary  Control Structures  
Several VMX control structures are directly managed and access ed by the  host  VMM .  These control structures are 
pointed to by fields in the TD VMCS .  The Intel TDX module  checks  that the pointers conf orm to the shared -access HPA 
semantics (see  18.2.1.1 ). 
Non -protected control structures include:  5 
• Shared EPT tree  
• Posted interrupt descriptor  
6.4. TD Non -Memory State (Metadata) Access Functions  
As set of interface functions is provided to enable host VMM and guest TD access to TD non -memory state (metadata).  
These functions employ metadata abstraction , using field code to abstract the actual control structure format.  The 10 
generic metadata access interface  mechanisms are described in 18.6 .  
Table 6.1:  TD Non -Memory State (Metadata) Single Field Access Functions  
Side  Scope  Control Structures  Intel TDX Functions  
Host VMM  
(SEAMCALL)  TD TDR and TDCS  TDH.MNG.RD, TDH.MNG.WR  
VCPU  TDVPS (including TD VMCS)  TDH.VP.RD, TDH.VP.WR  
Guest TD  
(TDCALL)  TD TDR and TDCS  TDG.VM.RD, TDG.VM.WR  
VCPU  TDVPS (including TD VMCS)  TDG.VP.RD, TDG.VP.WR  
 
Access to control structure fields using the provided interface functions (down to the bit granularity, if required) depends 
on whether the TD is debuggable (ATTRIBUTES.DEBUG bit is 1) or not.  15 
In many cases, control structure field access means more than just reading or writing the field content.  For example:  
• When a field that contains an HPA is written, its value is checked not to overlap the SEAMRR range.  
• In some cases, there may be inter -dependency between fields.  When such fields are written, multiple checks may 
need to be done and some actions may need to be taken.  
• For some fields, the internal format and/or value may be different than what is visible externally.  20 
For details  about the TDX module’s metadata access interface , see  18.6 . 
6.5. Concurrency Restrictions and Enforcement  
A general description of concurrency restriction is provided in 18.1 .   
Normally, exclusive or shared access is acquired, if needed, for the  typically short duration of function flows.  A TD VCPU 
execution is an exception case.  Shared access to TDCS and TDVPS is acquired on TD Entry and released on TD Exit.  This 25 
implies that SEAMCALL( TDH.VP.ENTER ) function, all TDCALL functions, and asynchronous TD Exit have implicit shared 
access to TDCS and TDVPS.

access to TDCS and TDVPS.  
This mechanism helps protect running VCPUs against concurrent function s that may try to change their governing control 
structures.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 60 of 153 
Section 2:  Intel TDX Module Architecture Specification  7. TD Life Cycle  Management  
This chapter discusses guest TD life cycle management.  
7.1. TD Life Cycle State Machine  
The TD Life Cycle state machine controls the overall TD build, run -time and destruction process.  It operates in conjunction 
with the HKID state machine, as described in 5.5.  Figure 7.1 below  shows the TD Life Cycle state diagram.  5 
[non -last
package]
Sub-State
 
Figure 7.1:  High -Level TD Life Cycle State Diagram  
Most of the TD lifetime is spent in the TD_KEYS_CONFIGURED state .  Within that state , a secondary -level state machine 
control s the overall TD operation and migration . 
7.2. OP_STATE:  TD Operation Secondary -Level State Machine  10 
The TD Operation state machine controls sub -states of the TD Life Cycle’s TD_KEYS_CONFIGURED state.  It shown in 
Figure 7.2 below .  This document describes the baseline states:  UNALLOCATED, UNINITIALIZED, INITIALIZED and 
RUNNABLE.  Other states and transitions highlighted in red lines support TD migration and are described in the [TD 
Migration Spec].  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 61 of 153 
TD memory 
TRACK
[in-order done]PAUSED_EXPORT
export
TRACK
ABORT
(MigTD)
TRACK
[in-order
not done]
TRACK
[in-order
not done]
COMMIT
RUNNABLE
be done
STATE.
IMMUTABLE
STATE.
IMMUTABLE
ABORT
TRACK
[in-order
TRACK
[in-order
 
Figure 7.2:  TD Operation State Machine (Sub -States of TD_KEYS_CONFIGURED)  
7.3. TD Creation  and Configuration Sequence  
The following sequence is intended to be used by the host VMM to create a new TD.  Note that only the general aspects 
of TD  creation  are described here.  Other aspects, such as key management, are described in other chapters.  5 
TD configuration is done by TDH.MNG.INIT.  This interface function receives a TD_PARAMS input structure, which 
contains the following main sections:  
• ATTRIBUTES and XFAM, which specify the set of TD attributes (e.g., whether the TD is debuggable) and CPU features 
the TD may use (e.g., whether AVX2 is available to the TD).  
• Other TD configuration parameters, such as the number of L2 VMs the TD contains.  10 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 62 of 153 
Section 2:  Intel TDX Module Architecture Specification  • A set of user -provided measurement fields that will appear in the TD’s TDREPORT_STRUCT.  
• Virtual CPUID and virtual MSR configuration  for the TD.  
For a detailed description of TD_PARAMS and its fields, see the [ABI Spec].  
Table 7.1:  Typical TD Creation Sequence  5 
 Intel TDX Function  Inputs  Description  
1 N/A N/A If any MODIFIED cache lines may exist for the 
physical pages to be written below (TDR, TDCS, 
Secure EPT root page), flush them to memory 
using, e.g., CLFLUSH (possibly on multiple LPs).  
This is required to avoid corruption due to cache 
line aliasing.  
2 TDH.MNG.CREATE  TDR page PA  Create the TDR and generate the TD’s random 
ephemeral key.  
3 Multiple  See 5.6.2  Assign an HKID and  configure the TD’s random 
ephemeral key on all packages, as described in 
5.6.2 . 
4 TDH.MNG.ADDCX 
(multiple)  • Owner TDR PA  
• TDCX page PA  Run multiple times to add the required number of 
TDCX pages.  
5 TDH.MNG.INIT  • Owner TDR PA  
• TD initialization parameters  Initialize the TD state in TDR and TDCS.  
At this point the TD is initialized.  Private memory pages can be added as described in Chapter 9.  VCPUs can be 
created and initialized as described below.  
 
7.4. VCPU Creation and Initialization Sequence  
VCPU creation and initialization is only allowed during TD build time.  
The following sequence is intended to be used by the host VMM to create a new TD VCPU.  After this sequence is done, 
the TD VCPU may be entered on an LP (assuming other conditions are met).  10 
Table 7.2:  Typical TD VCPU Creation and Initialization Sequence  
physical pages to be written below (TDVPR, TDCX ), 
flush them to memory (e.g.,  using CLFLUSH – 
possibly on multiple LPs).  This is required to avoid 
corruption from cache line aliasing.  
2 TDH.VP.CREATE  • TDVPR page PA  
• Owner TDR PA  Create the VCPU and its TDVPR page.  
3 TDH.VP.ADDCX  
(multiple)  • TDCX page PA  
• Parent TDVPR PA  Run multiple times to add the required number of 
TDCX  pages as an extension to a parent TDVPR.  
4 TDH.VP.INIT  • TDVPR PA  
• VMM -provided identifier  Initialize the VCPU state.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 63 of 153 
Section 2:  Intel TDX Module Architecture Specification   Intel TDX Function  Inputs  Description  
5 TDH.VP.WR  • TDVPR page PA  
• Field code  
• New field value  
• Write mask  The host VMM typically writes one or more of the 
following TD VCPU’s VMCS controls:  
• Shared EPTP  
• Posted -interrupts descriptor address, posted -
interrupts notification vector and process 
posted interrupt  
• bus-lock detection  
• notification exiting and notify window  
For details, see the [ TDX Module ABI Spec ]. 
 
7.5. TD Teardown  Sequence  
The following sequence is intended to be used by the host VMM to tear down a TD.  Note that only the general aspects 
of TD  teardown are described here.  Other aspects, such as key management, are described in other chapters.   See also 
the discussion of physical page reclamation in 8.5. 5 
Table 7.3:  Typical TD Teardown Sequence  
1 Multiple  See 5.6.3  Reclaim the HKID, and flush TLB and cache, 
as described in 5.6.3 . 
2 TDH.PHYMEM.PAGE.RECLAIM  
(multiple)  TD page or control structure 
PA Remove all TD private pages and control 
structure pages and  mark them as PT_NDA 
in the PAMT.  
3 TDH.PHYMEM.PAGE.RECLAIM  TDR PA  Remove the TDR page and  mark it as 
PT_NDA in the PAMT.  
4 TDH.PHYMEM.PAGE.WBINVD  TDR PA  Flush MODIFIED cache lines:  this is required 
to avoid corruption due to cache line 
aliasing.  Note that all cache lines for all 
other TD pages must have been flushed 
before the TDR page was reclaimed.  
November 2023   . Page 64 of 153 
Section 2:  Intel TDX Module Architecture Specification  8. Physical Memory  Management  
This chapter describes how the Intel TDX module  manages memory as a set of physical pages.  
8.1. Trust Domain Memory Region s (TDMRs) and Physical Address Metadata Tables (PAMTs)

8.1. Trust Domain Memory Region s (TDMRs) and Physical Address Metadata Tables (PAMTs)  
Trust Domain Memory Region  (TDMR)  is defined as  a range of  convertible memory pages.   TDMRs are set by the host 
VMM, based on the CMR information previously checked by MCHECK.  5 
Each TDMR is define d as controlled by a (logically) single Physical Address Metadata Table (PAMT) .  The PAMT structure 
is discussed in 8.3 below .  PAMT tables reside in VMM -allocated memory, and they are designed to be  encrypted with 
the Intel TDX global private HKID.  The required size of PAMT memory, as a function of TDMR size, is enumerated to the 
VMM by TDH.SYS.RD/RD ALL or TDH.SYS. INFO.  
Typically, a fter the  host  VMM initializes the Intel TDX module  (TDH.SYS. INIT and TDH.SYS.LP.INIT ), it configures the TDMRs 10 
and their respective PAM Ts using TDH.SYS. CONFIG .  It then  would  gradually initialize the TDMRs using 
TDH.SYS.TDMR.INIT .  For a detailed description of the typical Intel TDX module  initialization and configuration  sequence , 
see Chapter  4. 
8.2. TDMR  Details  
The following list includes defin itions of  the characteristics of a TDMR:  15 
• TDMR  configuration is "soft"  – no hardware range registers are used.  
• Each TDMR  defines a single physical address range.  
• Each TDMR has its own size which must be a multiple of 1GB.   TDMR  size is not required to be a power of two . 
• A TDMR must be aligned on 1GB.  
• TDMRs c annot overlap with each other . 20 
• TDMRs may contain reserved areas.  This effectively allows the host VMM to flexibly configure TDMRs based on the 
VMM’s  own consideration of system memory allocation – without being impacted by the 1GB granularity of the 
TDMR size.  
o A reserved area must be aligned on 4KB, and its size must be a multiple of 4KB.  
o The number of reserved areas that may be configured per TDMR is enumerated by TDH.SYS.RD/RD ALL or 25 
TDH.SYS. INFO.  
• TDMR memory, except for reserved areas, must be convertible as checked  by MCHECK (i.e., every TDMR page must 
reside within a CMR).  
• There is no requirement for TMDRs to cover all CMRs.  
• TDMR s are configured  at platform  scope  (no separate configuration  per package).  30 
• The maximum number of TDMR s is Intel TDX module  implementation  specific .  It is enumerated to the host VMM 
using the TDH.SYS.RD/RD ALL or TDH .SYS. INFO function, as described below.  
8.3. PAMT Details  
The Physical Address Metadata Table (PAMT) is designed to track the metadata of every physical page in TDMR.  A page 
metadata  include s page type, page size, assignment to a TD, and other attributes.  35 
The PAMT is used by the Intel TDX module  to help  enforce the following properties:  
Page Attributes  A physical page in TDMR has a well -defined set of attributes, such as page type and page size.  
Single TD Assignment  A physical page in TDMR can be assigned to at most one TD.  
Secure EP T Consistency  The page size of any private TD page , mapped in Secure EPT , match es its page size attribute in 
PAMT.  40 
8.3.1.  PAMT Entry  
Note:  The description below is provided at a high level.  Implementation details may differ.  
A PAMT entry is designed to hold metadata for a single physical page.  The page size may be 4KB, 2MB or 1GB depending 
on the PAMT  level (see 8.3.2 below ). Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 65 of 153 
Section 2:  Intel TDX Module Architecture Specification  Table 8.1:  High -Level View of a PAMT  Entry  
PT PT indicates the type of page intended to be associated with this PAMT 
entry.  See Table 8.3 below  for details.  
OWNER  OWNER is designed to contain bits 51:12 of the physical address of the 
TD’s TDR page.  
This field can be applicable in all cases when a page is assigned to the 
Intel TDX module at this PAMT level or at a higher level.  See Table 8.3 
below  for details.  
BEPOCH  By design, the value of TDCS. TD_EPOCH as sampled by  
TDH.MEM.RANGE.BLOCK  
This field is intended to be applicable only if PT is PT_REG or PT_EPT.  See 
9.7 for a detailed discussion.  
 
8.3.2.  PAMT Blocks  and PAMT Arrays  
For each  1GB of  TDMR  physical memory , there is a corresponding PAMT Block.  A PAMT B lock is logically  arranged in a 
three -level tree structure  of PAMT Entries , as shown in Figure 8.1 below .  Levels 0 through 2 (PAMT_4K, PAMT_2M and 5 
PAMT_1G ) correspond to 4KB, 2MB and 1GB physical TDMR pages , respectively.    
Physically, for each TDMR the  design includes three  arrays of PAMT entries, one for each PAMT level.  This aims  to simplify 
VMM memory allocation .  A logical PAMT Block has one entry from the PAMT_1G array, 512 entries from the PAMT_2M 
array, and 5122 entries from the PAMT_4K array.  
5110
1,023512
262,143261,632
…5110
10
0x001FF0000x00000000
0x00200000
0x003FF000
0x3FE00000
0x3FFFF0000x00000000 0x00000000
0x3FE00000Level 2
PAMT_1GLevel 1
PAMT_2MLevel 0
PAMT_4K
 10 
Figure 8.1:  Typical Example of a PAMT Block Hierarch y for a  1GB TDMR Block  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 66 of 153 
Section 2:  Intel TDX Module Architecture Specification  8.3.3.  PAMT Page Types  
Table 8.2 below  describes the PAMT page types:  
Table 8.2:  PAMT Page Types  
Page Type  PAMT 
Level  Associated TDX 
Page  Description  
PT_NDA  Any Depending on PT 
at higher PAMT 
level  (if any ) The physical page is Not Directly Assigned  to the Intel TDX 
module at this size (4K, 2M or 1G) and PAMT level.  
This page may be part of a larger page that is assigned to the 
Intel TDX module at a higher level, or this page may contain 
smaller pages that are assigned to the Intel TDX module at lower 
levels.  See Table 8.3 below  for details.  
PT_RSVD  PAMT_4K  None  The physical page is reserved for non -TDX usage.  The Intel TDX 
module will not allow converting this page to any other page 
type.  The page can be used by the host VMM for any purpose.  
PT_RSVD is used for implementing reserved areas within TDMRs.  
See 4.1.3.2.1  for details.  
PT_REG  Any TD private page  The physical page at this PAMT level (4K, 2M or 1G) holds TD 
private memory and is mapped in the guest TD GPA space by the 
Secure EPT.  
PT_TDR  PAMT_4K  TDR  TDR control structure page  
PT_TDCX  PAMT_4K  TDCX  One 4KB physical page of a multi -page control structure  
PT_TDVPR  PAMT_4K  TDVPR  Root page of the multi -page TDVPS control structure  
PT_EPT  PAMT_4K  Secure EPT  Secure EPT page  
 
8.3.4.  PAMT Hierarchy  5 
Table 8.3 below  shows the page type (PT) of PAMT entries at the three  levels of hierarchy, depending on whether the 
page is assigned to the Intel TDX module  manages the page , whether the page  is mapped i n secure EPT , and the mapping 
size.    
Table 8.3:  PAMT Hierarchy and Page Types  
Intel TDX Module Management  PAMT Entry Page Type  
Assigned 
to TDX?  Physical 
Page 
Size  GPA Mapping 
Size  (Secure 
EPT Level)  PAMT_1G 
(Level 2)  PAMT_2M 
(Level 1)  PAMT_4K 
(Level 0)  
No 4KB  N/A  PT_NDA  PT_NDA  PT_RSVD  
No 4KB  N/A  PT_NDA  PT_NDA  PT_NDA  
Yes 4KB  None  PT_NDA  PT_NDA  PT_TDR, 
PT_TDCX, 
PT_TDVPR, 
PT_EPT  
Yes 4KB  4KB ( Level 0)  PT_NDA  PT_NDA  PT_REG  
Yes 2MB  2MB ( Level 1)  PT_NDA  PT_REG  PT_NDA  
Yes 1GB  1GB ( Level 2)  PT_REG  PT_NDA  PT_NDA  
 10 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 67 of 153 
Section 2:  Intel TDX Module Architecture Specification  Note the following:  
• A 4KB page is considered free (i.e., not assigned to TDX) if its PAMT.PT at all three PAMT levels is PT_NDA.  Any 
function that attempts to assigns an HPA to TDX (e.g., TDH.MEM.PAGE.ADD ) is designed to check  this.  
• In all other cases, PAMT.PT is different than PT_NDA in only one of the three PAMT levels.  
• When a page is mapped by Secure EPT  at 4KB, 2MB or 1GB GPA mapping size , it is managed by the Intel TDX module  5 
as a physical page of the same size.   Secure EPT is described in Chapter  9. 
• PT_RSVD  pages can not be used by the Intel TDX module .  They are used for implementing reserved areas within 
TDMRs.  See 4.1.3.2.1  for details.  
8.4. Adding Physical Pages  
8.4.1.  Server Platforms:  Preventing Cache Line Aliasing  by Flushing Cache Lines  10 
Before adding a physical page, the host VMM is responsible for making sure no MODIFIED cache lines exist for that page.  
The host VMM can flush cache lines to memory – e.g.,  using CLFLUSH (only for pages containing data encrypted with a 
shared HKID – the VMM cannot  directly use an HPA with a private HKID), or TDH.PHYMEM.PAGE.WBINVD  (for pages 
containing data encrypted with any HKID, as long as the page is within a TDMR).  Flushing cache lines to memory is 
required to avoid corruption due to cache line aliasing.  15 
8.4.2.  Adding Pages not Mapped to the Guest TD  
By design, TD control structure pages TDR, TDC X and TDVPR are not mapped to the guest TD’s GPA space, and they are

By design, TD control structure pages TDR, TDC X and TDVPR are not mapped to the guest TD’s GPA space, and they are 
only managed using their HPA.  The function s TDH.MNG.CREATE , TDH.MNG.ADDCX , TDH.VP.CREATE  and TDH.VP.ADDCX  
are designed to add 4KB control structure pages PT_TDR, PT_TDCX  and PT_TDVPR , respectively.  The overall process is 
described in 7.3 and 7.4. 20 
8.4.3.  Adding Pages and Mapping to the Guest TD ’s GPA  
The following page types are associated with a guest TD’s GPA:  
• Guest TD private pages  
• Secure EPT pages are mapped to the guest TD’s GPA space.  
Those pages  are added given their HPA and the required  GPA.  The function s TDH.MEM.PAGE.ADD , TDH.MEM.PAGE.AUG , 25 
TDH.MEM.PAGE.RELOCATE  and TDH.IMPORT.MEM add a PT_REG  page, and the function s TDH.MEM.SEPT.ADD  and 
TDH.MEM.PAGE.DEMOTE  add a 4KB PT_E PT page .  TD private memory management functions are  described in Chapter  
9.  This section describes only the ir physical page management aspects . 
8.5. Reclaiming Physical Pages  
8.5.1.  Server Platforms:  Required Cache Flush and Initialization by the Host VMM  30 
Once a physical page is reclaimed from a TD, it should be free for use by the host VMM for any purpose, provided that 
the operations described below are done.  
Cache Flush  
To help avoid stability issues caused by cache line aliasing, the host VMM should also ensure that no cache lines 
associated with the removed page are in a Modified state , before the page is reused for any purpose . 35 
• During the TD’s lifetime, this can be done by calling TDH.PHYMEM.PAGE.WBINVD.  
• If the TD has been torn down and is in the in TD_TEARDOWN state, cache has already been flushed by 
TDH.PHYSMEM.CACHE.WB as part of the teardown sequence, so no further operation is required – except for the 
TDR page as descried below.  
Page Initialization  40 
Before the physical page is used for anything except TD private memory page or TDX control structure page, the host 
VMM should initialize it using MOVDIR64B.  This helps ensure that no content encrypted with a private HKID remains for 
that physical page, w hich may result in an integrity violation or TD bit mismatch detection when later being read using a 
shared HKID.  For details, see Ch. 16. Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 68 of 153 
Section 2:  Intel TDX Module Architecture Specification  If the page is to be used as a new TD private memory page or TDX control structure page, this initialization is not required 
since the TDX module will initialize the page.  
8.5.2.  Reclaiming Pages not Mapped to the Guest TD ’s GPA Space  
There are two cases where pages are not considered as mapped to the guest TD:  
• Control structure pages are not mapped to the guest TD . 5 
• In TD_TEARDOWN  state, as described below, no mapping is in effect . 
 Reclaiming TD Pages in TD_TEARDOWN  State  
As part of the TD teardown process, the VMM needs to put the TD into a TD_TEARDOWN  state , as described in 7.4.  This 
is a non -recoverable state where TD keys have been reclaimed , all address translations  and caches have been flushed, 
and the TD private memory and control structures (except TDR) are no longer accessible.  10 
By design, i n the TD_TEARDOWN state, all TD pages are effectively unmapped.  Secure EPT is not accessible, and no GPA -
to-HPA mapping can be used.  The host VMM must treat all the TD private pages and control structure pages as physical 
memory and reclaim them using th e TDH.PHYMEM.PAGE.RECLAIM  function in any order, as long as the TDR page is the 
last one to be reclaimed.  
For TDR page, the intention  is for the host VMM to call TDH.PHYMEM.PAGE.WBINVD  after calling 15 
TDH.PHYMEM.PAGE.RECLAIM .  This is required to avoid corruption due to cache line aliasing because the TDR page has 
still been accessed and modified, even when the TD was in TD_TEARDOWN state.  
8.5.3.  Reclaiming Physical Pages as Part of TD Private Memory Management  
Functions such as TDH.MEM.PAGE.REMOVE  and TDH.MEM.PAGE.PROMOTE  are designed to remove TD private pages 
and Secure EPT pages, respectively.  By design, t hey first make sure the pages are no longer accessible using a GPA, then 20 
they mark the physical page as free.  This is described in Chapter  9; this section only highlights the physical page 
reclamation.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 69 of 153 
Section 2:  Intel TDX Module Architecture Specification  9. TD Private Memory Management  
This chapter described how the Intel TDX module  helps manage TD private memory and guest -physical address (GPA) 
9.1. Overview  
Intel TDX ISA  introduced the concept of private GPA vs. shared GPA , depending on the GPA.SHARED bit .   In SEAM non- 5 
root mode , the controlling VMCS has two EPT pointer fields:  
• The legacy EPT pointer is used for translating the guest TD’s memory accesses using a private GPA  (i.e., 
GPA.SHARED  == 0). 
• A new Shared EPT pointer is used for translating the guest TD’s memory accesses using shared GPAs (i.e., 
GPA.SHARED  == 1). 10 
A new GPAW execution control determines the position of the SHARED bit in the GPA, and a new HKID execution control 
defines the HKID used for accessing TD private memory.  
TD0
CPU PMH
Extended
Physical 
Address + 
Pages
 
Figure 9.1:  Secure EPT Concept  
The Intel TDX module  maintains a single Secure EPT structure per TD.  Secure EPT pages are designed to be opaque; they 15 
reside in ordinary memory, and they are encrypted and integrity -protected with the TD’s ephemeral private key.  The 
Intel TDX module  does not  map Secure EPT pages to the guest TD GPA space.  Thus, Secure EPT is effectively not accessible 
by any software besides the Intel TDX module , nor by any devices.  Any such access using shared HKID to Secure EPT  can 
lead to data corruption that triggers integrity check failure leading to a machine check fault.  
Secure EPT i s intended to be  managed indirectly by the host VMM using Intel TDX functions.  The Intel TDX module  helps 20 
ensure that the Secure EPT is managed correctly.  
The CPU translates shared GPAs using the Shared EPT which resides in host VMM memory .  The translation uses a shared 
HKID, and it is directly managed by the host VMM, just as with legacy VMX.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 70 of 153 
Section 2:  Intel TDX Module Architecture Specification  9.2. Secure EPT Entry  
9.2.1.  Overview  
From the CPU perspective, Secure EPT has the same structure as a legacy VMX EPT.  
For the purpose of private memory management, the Intel TDX module hold a state value in each Secure EPT entry.  This 
state value is encoded by multiple bits.   5 
Table 9.1:  Secure EPT Entry State  High Level Description  
State Name  Description  
FREE  Secure EPT entry does not map a GPA range.  
REMOVED  Secure EPT entry is of a removed page  
NL_MAPPED  Secure EPT entry maps a private GPA range which is accessible by 
the guest TD.  
NL_BLOCKED  Secure EPT entry maps a private GPA range, but new address 
translations to that range are blocked.  
MAPPED  Secure EPT entry maps a private GPA page which is accessible by 
BLOCKED  Secure EPT entry maps a private GPA page but new address 
BLOCKEDW  Secure EPT entry maps a private GPA page, but new address 
translations for write operations to that range are blocked.  
EXPORTED_BLOCKEDW  Secure EPT entry maps a private page that has been blocked for 
writing and exported.  
EXPORTED_DIRTY  Secure EPT entry maps a private page that was exported but  is not 
blocked for writing and its content and/or attributes may have since 
been modified.  
EXPORTED_DIRTY_BLOCKEDW  Secure EPT entry maps a private page that was previously exported, 
its content and/or attributes may have since been modified and 
then it was blocked for writing .   
PENDING  Secure EPT entry maps a 4KB or a 2MB page that has been 
dynamically added to the guest TD using TDH.MEM.PAGE.AUG and 
is pending acceptance by the guest TD using 
TDG.MEM.PAGE.ACCEPT.  This page is not yet accessible by the 
guest TD.  
PENDING_BLOCKED  Secure EPT entry is both pending and blocked.  
PENDING_BLOCKEDW  Secure EPT entry is both pending and blocked for writing.  
PENDING_EXPORTED_BLOCKEDW  Secure EPT entry is both pending and exported.  
PENDING_EXPORTED_DIRTY  Secure EPT entry is both pending and exported and  is not blocked 
for writing.

guest TD.  
for writing.  
PENDING_EXPORTED_DIRTY_BLOCKEDW  Secure EPT entry is both pending and exported and  is blocked for 
writing.  
 
Secure EPT entry is opaque; the host VMM may not access it directly.  The host VMM may read a Secure EPT entry 
information using the TDH.MEM.SEPT.RD interface function.  In addition, multiple other interface functions return the 
same information in case of  an error that is related to a Secure EPT entry.  For details, see the [ TDX Module ABI Spec ]. 10 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 71 of 153 
Section 2:  Intel TDX Module Architecture Specification  9.2.2.  SEPT Entry State Diagrams  
The figures below show partial state diagrams for the basic memory management operation for a leaf and a non -leaf 
SEPT entry.  
Note:  The diagrams below are partial.  SEPT entry state diagrams for TD migration are provided in the [TD Migration 
Spec].   SEPT entry state diagrams for TD partitioning  are provided in the [ TD Partitioning  Spec].  5 
TDH.MEM.PAGE.REMOVEFREE
TD
PENDING
TD acceptanceTDH.MEM.PAGE.ADD
TDH.MEM.PAGE.AUGTDH.MEM.PAGE.DEMOTE /
PINNED_BLOCKED_COUNT --,
Entry becomes NL_MAPPEDTDH.MEM.PAGE.PROMOTE[non -leaf NL_MAPPED entry] /
Previous non -leaf entry becomes MAPPED
Diagram
Entry becomes NL_MAPPEDTDH.MEM.PAGE.DEMOTE /
Diagram
DiagramTDH.MEM.PAGE.REMOVE /
PINNED_BLOCKED_COUNT --BLOCKED
blockedTDH.MEM.RANGE.BLOCK /
PINNED_BLOCKED_COUNT++
is blockedTDH.MEM.RANGE.
BLOCKTDH.MEM.PAGE.PROMOTE /
PINNED_BLOCKED_COUNT --
Entry becomes NL_MAPPED
TDH.MEM.PAGE.DEMOTE [TD is paused] /
Entry becomes NL_MAPPEDTDH.MEM.RANGE.UNBLOCK /
UNBLOCKTDG.MEM.PAGE.ACCEPT
 
Figure 9.2:  Secure EPT Leaf Entry Basic Operation Partial State Diagram  
 
FREE
pageNL_MAPPED
IO_BLOCKED_COUNT --,
TDH.MEM.SEPT.REMOVE[all entries are FREE] /
PINNED_BLOCKED_COUNT --NL_BLOCKED
TDH.MEM.RANGE.UNBLOCK /
 
Figure 9.3:  Secure EPT Non -Leaf Entry Basic Operation Partial State Diagram  10 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 72 of 153 
Section 2:  Intel TDX Module Architecture Specification  9.3. Secure EPT Walk  
Host -side (SEAMCALL)  Intel TDX function s that manage TD private memory usually accept GPA and Level parameters .  
They  perform a Secure  EPT walk  which locates the target Secure EPT entry.  
If the Secure EPT walk is completed successfully, the Intel TDX  function  may operate on the located Secure EPT entry.  
Otherwise, the function  typically returns the last visited EPT entry and its level to the host VMM.  5 
Guest -side (TDCALL) Intel TDX functions  typically  perform an EPT  walk similar to the EPT walk done by the CPU.  Only the 
GPA is provided as an input, and the function may walk the Shared EPT or the Secure EPT, depending on the specific 
function and the GPA’s SHARED bit.  
9.4. Secure  EPT Induced TD Exits  
Intel SDM, Vol. 3, 26.2.1  Basic VM-Exit Information  10 
Guest TD memory access to a non -present private GPA  causes , in most cases,  an asynchronous TD exit with an EPT 
Violation exit reason.  As discussed in 9.2 above , a non -present GPA is a ny private GPA for which there is  either no Secure 
EPT entry, or the Secure EPT entry is not in the MAPPED  state.  
Secure EPT -induced TD exits may also be triggered during a guest -side local flow, performing some function on behalf of 
the guest TD, and executed by the Intel TDX module.  15 
On EPT violation TD exit, VM exit information is provided to the host VMM.  This helps the VMM analyze  the reason for 
the EPT violation and take proper action.  
Table 9.2:  EPT Violation TD Exit Cases  and Possible Host VMM Actions  
Reason  May be Indicated by  Possible Host VMM Action  
Page is not mapped to the 
TD GPA space  • Exit qualification bits 6:3 value is  
0. 
• Extended exit qualification TYPE 
(bits 3:0) value is NULL (0).  
• The host VMM knows, based on 
its internal data, that either the 
page or a Secure EPT page that 
maps it has not been allocated to 
the TD . The host VMM may use this as a trigger for 
dynamic memory allocation 
(TDH.MEM.PAGE.AUG) or for a post -copy 
migration import (see [TD Migration Spec]).  
Page is BLOCKED or GPA 
range is NL_BLOCKED  • Exit qualification bits 6:3 value is  
0. 
its internal data, that the page or 
a Secure EPT page that maps it 
has been blocked.  The host VMM may resume the TD 
(TDH.VP.ENTER), possibly after taking some 
action (e.g., TDH.MEM.PAGE.PROMOTE) for 
which the page has been blocked.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 73 of 153 
Section 2:  Intel TDX Module Architecture Specification  Reason  May be Indicated by  Possible Host VMM Action  
Page is PENDING  or 
PENDING_EXPORTED_DIRTY  • Exit qualification bits 6:3 value is  
0. 
(bits 3:0) value is  
PENDING_EPT_VIOLATION ( 6).5 
its internal data, that the page 
has been assigned to the TD using 
TDH.MEM.PAGE.AUG.  This happens if the TD is configured to TD -exit 
(instead of a #VE) on an EPT violation due to 
accessing a PENDING page.  It normally 
indicates an error condition; the host VMM 
may decide to tear the TD down.  
Configuration is by  
ATTRIBUTES.SEPT_VE_DISABLE . 
If CONFIG_FLAGS.FLEXIBLE_PENDING_VE is 1, 
then the guest TD may select the desired 
behavior.  
Page is blocked for writing  
(*BLOCKEDW)  • Exit qualification bit 1 value is 1, 
indicating a write access, and bit 
4 is 0, indicating write blocking.  
has been blocked for writing using 
TDH.EXPORT.BLOCKW  The host VMM may unblock the page 
(TDH.EXPORT.UNBLOCKW).  for details, see 
[TD Migration Spec].  
EPT violation  during 
PENDING page acceptance 
(TDG.MEM.PAGE.ACCEPT ) • Extended exit qualification TYPE 
(bits 3:0) value is ACCEPT ( 1). 
• See the discussion in 9.10 below  
and the [ABI Spec] for details . Depending on the information provided in the 
extended exit qualification, the host VMM 
may demote the page, add an SEPT page, add 
a page or retry the operation after the page is 
not blocked.  
See the discussion in 9.10 below  and the [ABI 
Spec] definition of TDG.MEM.PAGE.ACCEPT 
for details.  
EPT violation during 
TDG.MEM.PAGE.ATTR.WR  • Extended exit qualification TYPE 
(bits 3:0) value is ATTR_WR (5).  Depending on the information provided in the 
may demote the page or add an L2 SEPT page.  
See the [ABI Spec] definition of 
TDG.MEM.PAGE.ATTR.WR for details.  
EPT violation caused by 
guest -side interface 
function failure of 
GPA→HPA translation  • Extended exit qualification TYPE 
(bits 3:0) value is GPA_DETAILS 
(2). Similar to the above cases where the page is 
not mapped, is blocked or is blocked for 
writing, except that more information is 
provided in the extended exit qualification . 
By design, since secure EPT is fully controlled by the TDX module, an EPT misconfiguration on a private GPA indicates a 
TDX module bug and is handled as a fatal error.  
9.5. Secure EPT Induced Exceptions  
Guest TD memory access, with any GPA bit at position higher than the SHARED bit but lower than MAXPA set to 1, causes 
a #PF exception.  See 11.11.1 . 5 
See 9.10.4 below  for details of handling guest TD memory access to a private GPA for which the Secure EPT entry state is 
PENDING or PENDING_EXPORTED_DIRTY . 
9.6. Secure EPT Concurrency  
Secure EPT concurrency rules are designed to allow concurrent operations on multiple Secure EPT entries.   Secure EPT 
concurrency is controlled by the following mechanisms:  10 
• An exclusive/shared lock on the whole Secure EPT tree.

• An exclusive/shared lock on the whole Secure EPT tree.  
• A mutex on each Secure EPT entry, controlling host -side (SEAMCALL) access.  
 
5 Availability of this indication is enumerated by TDX_FEATURES0.PENDING_EPT_VIOLATION_V2 (bit 16), readable by TDH.SYS.RD*.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 74 of 153 
Section 2:  Intel TDX Module Architecture Specification  • A mutex on each Secure EPT entry, controlling guest -side (TDCALL) access.  
Host -Side (SEAMCALL) Interface Functions  
• TDX module interface functions that use GPA as an input acquire a shared lock  on the whole Secure EPT tree of the 
target TD to help prevent changes to the tree while they execute.  
• Most interface functions that use GPA as an input acquire an exclusive host -side lock on the Secure EPT entry or 5 
entries which they use.  An exception to this is TDH.MEM.SEPT.RD, which just reads a Secure EPT entry and does not 
use it to actually access memory.  
• In specific cases where a Secure EPT entry update may collide with a concurrent update done by the guest TD, host -
side interface functions update the Secure EPT entry as a transaction, using atomic compare and exchange operation.  
• Host -side interface functions that obtain exclusive access to the whole Secure EPT tree, such as 10 
TDH.MEM.SEPT.REMOVE, are considered as implicitly having exclusive access to each of its entries.  
• Host -side interface functions that obtain exclusive access to the TDR page (and thus, to the whole TD), such as 
TDH.MEM.PAGE.ADD, are considered as implicitly having exclusive access to the Secure EPT tree and each of its 
entries.  
Guest -Side (TDCALL) Interface Functions  15 
Guest -side TDX module interface functions that need to translate a GPA to an HPA emulate the CPU’s top -down EPT walk 
• Guest -side interface functions have no concurrency restrictions on the whole Secure EPT tree.  
• Guest -side interface functions that need to update a Secure EPT entry (currently, only TDG.MEM.PAGE.ACCEPT) 
acquire an exclusive guest -side lock on that entry.  This lock is only checked by other similar guest -side functions, 20 
but not by host -side functions.  Thus, Secure EPT entry update is done as a transaction, using atomic compare and 
exchange operation.  
9.7. Introduction to TLB Tracking  
The goal of TLB tracking is to be able to prove  (when needed ) that no logical processor holds any cached Secure EPT 
address translations to a given TD private GPA range .  TLB tracking  is required  when removing a mapped TD private page 25 
(TDH.MEM.PAGE.REMOVE ) or when changing the page mapping size (TDH.MEM.PAGE.PROMOTE ), etc.  
Cached address translations include implicit address translations (TLB) and paging structure translations (PxE) held by the 
CPU.  In addition, GPAs that are translated by the TDX module to HPA and written to VMX control structure fields, to be 
read by the CPU, are also considered cached address translation.  
Conditions when TLB Tracking is not Required  30 
TLB tracking is not required when the TD’s OP_STATE implies that no TD VCPU may run at the time GPA mapping 
operation modification (e.g., TDH.MEM.PAGE.REMOVE) is done.  The only OP_STATE  values  when TD VCPUs may run are 
the following:  
• RUNNABLE  
• LIVE_EXPORT  35 
• LIVE_IMPORT  
In addition, TLB tracking is not required if the GPA range’s Secure EPT entry state implies that no cached address 
translations may exist for that Secure EPT entry.   This applies to the following SEPT entry states (see the [ TDX Module ABI 
Spec ] for details):  
• EXPORTED_BLOCKEDW, PENDING_EXPORTED_BLOCKEDW:  The page has been exported by TDH.EXPORT.MEM and 40 
it is blocked for writing.  
• FREE, REMOVED:  The page has been removed (e.g., by TDH.MEM.PAGE.REMOVE).  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 75 of 153 
Section 2:  Intel TDX Module Architecture Specification  GPA Range TLB Tracking Sequence  
This sequence is intended to be used by the host VMM to help guarantee no EPT TLB entries exist to a set of GPA ranges.  
Intel TDX 
IPI
VM Entry
 
Figure 9.4:  Typical TLB Tracking Sequence  
The sequence  typically  includes five steps:  5 
1. Execute TDH.MEM.RANGE.BLOCK  on each GPA range, blocking subsequent creation of TLB translation to that range.  
Note that cached translations may still exist  at this stage.  
2. Execute TDH.MEM.TRACK , advancing the TD’s epoch counter.  
3. Send an Inter -Processor Interrupt (IPI) to each Remote Logical Processor (RLP) on which any of the TD’s VCPUs is 
currently scheduled.  10 
When each of the TD VCPUs has been inactive at least once following TDH.MEM.TRACK, the target GPA ranges are 
considered tracked.  Even though some LPs may still hold TLB entries to the target GPA ranges, the following  TD entry to 
each of the TD VCPUs is d esigned to flush them.  
Note:  If the host VMM counts the number of active VCPUs, and following TDH.MEM.TRACK this number is 0, the host 15 
VMM may skip the IPIs – all VCPUs are already considered tracked.  
5. Normally, the host VMM on each RLP will treat the TD exit as spurious and will immediately re -enter the TD.  
9.8. Secure  EPT Build  and Update :  TDH.MEM.SEPT.ADD  
The host VMM can use the TDH.MEM.SEPT.ADD  function  to add a  Secure EPT  page to a guest TD .  TDH.MEM.SEPT.ADD  
inputs are : 20 
• Target TD, identified by its TDR HPA  
• Destination physical page  for the new Secure EPT table  
• Mapping information :  GPA and EPT level  
At a high level, TDH.MEM.SEPT.ADD  works as follows:  
1. Check  the TD keys are configured . 25 
2. Check  the destination physical page is marked as free  in the PAMT . 
3. Perform a S ecure EPT walk to locate the S ecure EPT non -leaf entry  which will become the parent entry that map s 
the new S ecure EPT page.   To help prevent  re-maps, TDH.MEM.SEPT.ADD  checks  the mapping does not already exist, 
else it aborts the operation.  
4. Initialize  the target page  to zero using the target TD ’s private HKID  and direct writes (MOVDIR64B) . 30 
5. Update the parent S ecure EPT entry  to map the page as MAPPED . 
6. Update the  page’s  PAMT entry with the PT_EPT page type and the TDR PA as the OWNER.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 76 of 153 
Section 2:  Intel TDX Module Architecture Specification  The Secure EPT’s root page (EPML4 or EPML5, depending on whether the host VMM uses 4 -level or 5 -level EPT) does not 
need to be explicitly added.  It is created during TD initialization (TDH.MNG.INIT) and is stored as part of TDCS.  On each 
VCPU initialization, TDH.VP.INIT  copies  the address of the Secure EPT root page to the VCPU’s TD VMCS’ s EPTP field  
clearing the HKID bits to 06.   
The following example  illustrates the build process of a 4-level Secure  EPT hierarchy:  5 
1. The host VMM calls TDH.MNG.CREATE (TDR_PA = T DR 0) to create the TD . 
2. The host VMM calls TDH.MNG.ADDCX (TDR_PA = T DR 0, DST_PA = TDCX_PAGE_PA) multiple times to allocate pages 
for TDCS.  One of those pages will be used to host the Secure EPT root page D 0. 
3. Host VMM calls TDH.MNG.INIT (TDR_PA = T DR 0) to initialize the TD and set an EPML4 page  in one of the previously 
added TDCX page s as the Secure EPT root page .  This up dates TDCS. EPTP . 10 
4. TDH.VP.INIT  of each VPCU copies TDCS. EPTP  to the TD VMCS’ s EPTP field . 
5. Host VMM calls TDH.MEM.SEPT.ADD (TDR_PA = TDR 0, DST_PA = D 1, GPA = G 0, LVL= 3) to add an EPDPT page . 
6. Host VMM calls TDH.MEM.SEPT.ADD (TDR_PA = TDR 0, DST_PA = D 2, GPA = G 0, LVL= 2) to add an EPD page . 
7. Host VMM calls TDH.MEM.SEPT.ADD (TDR_PA = TDR 0, DST_PA = D 3, GPA = G 0, LVL= 1) to add an EPT page . 
TDCS
EPML4 EPDPT
PA = D 1
NL_MAPPEDEPD EPTEPTP = D 0
PA = D 2
NL_MAPPEDPA = D 3
NL_MAPPED
OWNER = TDR0
PT = PT_TDCXPAMT Entry for D0
PT = PT_EPTPAMT Entry for D1
PT = PT_EPTPAMT Entry for D2
PT = PT_EPTPAMT Entry for D3Step 3
TDH.MNG.INITStep 5
TDH.MEM.SEPT.ADDStep 6
TDH.MEM.SEPT.ADDStep 7
TDH.MEM.SEPT.ADD
TD VMCS
EPTP = D 0TD VMCS
EPTP = D 0Step 4
TDH.VP .INIT
 15 
Figure 9.5:  Typical Secure EPT Hierarchy Build Process  
To help avoid stability issues caused by cache line aliasing, the VMM should ensure  that no cache lines associated with 
the added physical SEPT page are in a Modified state, before calling TDH.MEM.PAGE.AUG.  This is typically  done b y calling 
TDH.PHYMEM.PAGE.WBINVD.  
9.9. Adding TD Private  Pages during TD Build T ime:  TDH.MEM.PAGE.ADD  20 
Adding TD private pages with arbitrary content is allowed only during TD build time (before TDH.MR.FINALIZE ).  The host

TDCS
PA = D 1
PA = D 2
NL_MAPPED
TD VMCS
 15 
Adding TD private pages with arbitrary content is allowed only during TD build time (before TDH.MR.FINALIZE ).  The host 
VMM adds and maps 4KB private pages to a guest TD using TDH.MEM.PAGE.ADD  with the following inputs:  
• Target TD, identified by its TDR physical address  
• Source page physical address  
• Destination page physical address  25 
• Destination page GPA  
At a high level, TDH.MEM.PAGE.ADD  works as follows:  
1. Check  the TD has not been initialized.  
 
6 The CPU adds the TD’s private HKID on EPT walks.  Having HKID as 0 allows the host VMM to use INVEPT, for managing the usage of 
shared EPT which shares the ASID with the TD’s secure EPT (see 
 ). Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 77 of 153 
Section 2:  Intel TDX Module Architecture Specification  2. Check  the TD keys are configured.  
3. Check  the destination physical page is marked as free in the PAMT.  
4. Perform a Secure EPT walk to locate the parent Secure EPT leaf entry that is going to map the new TD private page.  
To help prevent re -maps, TDH.MEM.PAGE.ADD  checks  the mapping does not already exist, else it aborts the 
operation.  5 
5. Copy the source page to the destination page using the target TD’s private HKID and direct writes (MOVDIR64B).  
6. Update the previously located parent Secure EPT leaf entry to map the page as MAPPED . 
7. Update the TD measurement with the new page GPA (as described in  12.1.1 ). 
8. Update the PAMT entry with the PT_REG page type and the TDR PA as the OWNER.  
PA = D 1
NL_MAPPEDEPD EPT
PA = D 2
NL_MAPPED
PT = PT_EPTPAMT Entry for D0
PT = PT_EPTPAMT Entry for D3New 4KB TD Private 
Page
PA = D 4
MAPPED
PT = PT_REGPAMT Entry for D4TDH.MEM.PAGE.ADD
 10 
Figure 9.6:  Typical Sequence for Adding a TD Private Page during TD Build Time  
the added physical page are in a Modified state, before calling TDH.MEM.PAGE.A DD.  This is typically done by calling 
TDH.PHYMEM.PAGE.WBINVD . 
9.10. Dynamically Adding TD Private Pages  15 
9.10.1.  Overview  
Dynamically adding TD private pages after the guest TD has been initialized is typically done as a three -step process:  
• The host VMM can update Secure EPT using TDH.MEM.SEPT.ADD  and TDH.MEM.SEPT.REMOVE . 
• The host VMM adds and maps a 4KB  or a 2MB  TD private page using TDH.MEM.PAGE.AUG .  This page is not 
measured .  The Secure EPT entry state for that added page is PENDING . 20 
• The guest TD must accept the page before it can access it, using TDG.MEM.PAGE.ACCEPT .  The page content is zeroed 
out. 
This process is designed to help prevent attacks where the host VMM could remove arbitrary pages from the guest TD’s 
GPA space (using TDH.MEM.PAGE.REMOVE ) and replace them with zeroed -out pages . 
A guest TD attempt to access a page that has been dynamically added by TDH.MEM.PAGE.AUG but has not yet been 25 
accepted by TDH.MEM.PAGE.ACCEPT results in a #VE exception.  
Refer also to the software flow described in 3.3.1.1 . 
9.10.2.  PENDING Page Addition by the Host VMM:  TDH.MEM.PAGE.AUG  
The host VMM can add and map 4KB and 2MB private pages  to a guest TD in a non -present and pending state using 
TDH.MEM.PAGE.AUG , with the following inputs:  30 
• Destination page physical address  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 78 of 153 
Section 2:  Intel TDX Module Architecture Specification  • Destination page GPA  
At a high level, TDH.MEM.PAGE.AUG  works as follows:  
1. Check  the TD keys are configured.  
2. Check  that the TD has either been initialized (by TDH.MNG .INIT) and no migration session is in progress, or that 
migration is in progress, but the TD is runnable (live export or import).  5 
To help prevent  re-maps, TDH.MEM.PAGE.AUG  checks  the mapping does not already exist, else it aborts the 
5. Update the previously located parent Secure EPT leaf entry to map the page as PENDING . 10 
6. Update the PAMT entry with the PT_REG page type and the TDR PA as the OWNER.  
Note that TDH.MEM.PAGE.AUG  does not need to access the destination page itself; the page  is initialized later on by 
TDG.MEM.PAGE.ACCEPT . 
PA = D 1
NL_MAPPEDEPD
EPTPA = D 2
NL_MAPPEDPA = D 4
NL_MAPPED
PT = PT_EPTPAMT Entry for D4New 4KB TD Private 
Page
(Non -Initialized)
PA = D 5
PENDING
PT = PT_REG4KB PAMT Entry for D5TDH.MEM.PAGE.AUG
(4KB)New 2MB TD 
Private Page
(Non -Initialized)TDH.MEM.PAGE.AUG
(2MB)
PA = D 3
PENDING
PT = PT_REG2MB PAMT Entry for D3
 
Figure 9.7:  Host VMM Adding a  4KB or a 2MB  TD Private Page  15 
the added physical page are in a Modified state, before calling TDH.MEM.PAGE.AUG.  This can be done be calling 
9.10.3.  PENDING Page Acceptance by the Guest TD:  TDG.MEM.PAGE.ACCEPT  
 Description  20 
The guest TD can accept a dynamically added 4KB or 2MB page using TDG.MEM.PAGE.ACCEPT with the page GPA and 
size inputs.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 79 of 153 
Section 2:  Intel TDX Module Architecture Specification  At a high level, TDG.MEM.PAGE.ACCEPT works as follows:  
1. Perform a Secure EPT walk to locate the parent Secure EPT leaf entry that maps the TD private page, and handle the 
walk results as described in the table below.  
Table 9.3:  TDG.MEM.PAGE.ACCEPT SEPT Walk Cases  
SEPT Walk Terminal Entry  TDG.MEM.PAGE.ACCEPT 
Operation  Typical Software Handling  
Level  Leaf or 
Non -
Leaf  State  
Higher 
than 
requested  Leaf  Guest -accessible, i.e., 
MAPPED or 
EXPORTED_DIRTY  (e.g. , 
2MB PTE present for a 4KB 
request) .   Return a status code indicating a 
success, with a warning that the 
page is already present and 
mapped at a level higher than 
requested.  Option 1:  This is OK, the host VMM 
did not use the memory released 
by the TD.  
Option 2:  This is a guest bug; the 
status code  helps debugging it. 
Not guest -accessible and 
not FREE (e.g. , 2MB PTE 
pending  for a 4KB request).  TD exit with EPT violation  
indicating  the error SEPT entry 
level and state, and the guest -
requested accept level.  See the 
[TDX Module ABI Spec ]. The host  VMM demotes  the page 
to match the requested accept size ,  
It then re -enters the guest TD.  
TDG.MEM.PAGE.ACCEPT is re -
invoked.  
Non -
Leaf Not guest -accessible  
(e.g.,  blocked  PDE for a 4KB 
request).  TD exit with EPT violation  
[TDX Module ABI Spec ]. This may be used as a guest TD 
request from the host VMM to add 
a page.  The host VMM adds SEPT 
pages ( TDH.MEM.SEPT.ADD ) and 
the requested page  
(TDH.MEM.PAGE.AUG) .  It then  
resumes the guest.  
Same as 
requested  Non -
Leaf Other than FREE (e.g.,  
requested 2M B entry is 
mapped to a EPT page 
instead of being a leaf)  Return a status code indicating a 
size mismatch error . The g uest falls  back to accept the 
range using 4K size.  
Leaf  Guest -accessible, i.e., 
MAPPED or 
EXPORTED_DIRTY  Return a status code indicating a 
page is already present . Option 1:  This is OK, the host VMM 
by the TD.  
Not PENDING nor 
PENDING_EXPORTED_DIRTY  TD exit with EPT violation  
[TDX Module ABI Spec ]. The host VMM resolves the 
blocking (e.g., completes the 
memory management operation 
that required blocking) and 
FREE  TD exit with EPT violation  
a page.  The hosts VMM adds the 
requested page  
(TDH.MEM.PAGE.AUG)  and 
PENDING  Complete the operation as 
described below.  Success  
 5 
If passed:  
Note:  Since initializing a 2MB page may take a long time, TDG.MEM.PAGE.ACCEPT is interruptible and resumable.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US

 5 
If passed:  
Note:  Since initializing a 2MB page may take a long time, TDG.MEM.PAGE.ACCEPT is interruptible and resumable.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 80 of 153 
Section 2:  Intel TDX Module Architecture Specification  2. If all the above checks pass, loop until done or interrupted:  
2.1. Initialize the next 4KB chunk of the page to zero using the target TD’s private HKID and direct writes 
(MOVDIR64B).  
2.2. If the whole page has been initialized, update the parent Secure EPT entry to set its state to SEPT_PRESENT.  
2.3. Else, if there is a pending interrupt, resume the guest TD without updating RIP and any GPR.  The CPU may 5 
handle the interrupt, causing a TD exit.  When the TD is resumed, TDH.MEM.PAGE.ACCEPT will re -invoked.  
PA = D 1
EPTPA = D 2
NL_MAPPED4KB TD Private Page
(Initialized to 0)
PA = D 5
MAPPEDTDG.MEM.PAGE.ACCEPT
(4KB)2MB TD Private 
Page
(Initialized to 0)TDG.MEM.PAGE.ACCEPT
(2MB)
PA = D 3
MAPPED
 
Figure 9.8:  Guest TD Accepting a 4KB or 2MB Pending TD Private Page  
 TDG.MEM.PAGE.ACCEPT Concurrency  
Guest -Side  10 
TDG.MEM.PAGE.ACCEPT prevents the guest TD from concurrently accepting the same page by multiple threads.  
TDG.MEM.PAGE.ACCEPT may also encounter a concurrent host -side operation, such as TDH.MEM.RANGE.BLOCK, that 
attempts to update the same Secure EPT entr y.  In such cases, an error is returned to the guest TD, indicating that the 
Secure EPT entry is busy.  
Host -Side  15 
TDG.MEM.PAGE.ACCEPT does not prevent host -side operation, such as TDH.MEM.RANGE.BLOCK, from concurrently 
modifying the Secure EPT entry.  TDG.MEM.PAGE.ACCEPT updates the entry using a locked compare and exchange 
operation.  If the update failed, a TD Exit is caused, with an EPT Violation exit reason and an indication that the violation 
is due to TDG.MEM.PAGE.ACCEPT.  For details, see the TDH.VP.ENTER definition in the [ TDX Module ABI Spec ]. 
9.10.4.  Guest TD (L1) Access to a PENDING Page  20 
The behavior in case of guest TD access to a page in a PENDING or PENDING_EXPORTED_DIRTY page is summarized in 
the table below.   This only applies to L1.  L2 VM access to a PENDING pages always results in an L2 →L1 exit.  
• #VE is useful for implementing an accept -on-demand policy.  It can be used by the guest TD to trigger a 
TDG.MEM.PAGE.ACCEPT of the PENDING page.  
• TD Exit is useful for guest TD implementations that only map memory that has been accepted into the linear address 25 
spaces.  For such implementations, an access to a PENDING page indicates a fatal error.  The host VMM typically 
tears the TD down when this happens.  
The combinations of configuration flags allow the host VMM to establish a static policy or  allow the guests TD to decide 
on the policy.  
Enumeration:  Availability of CONFIG_FLAGS.FLEXIBLE_PENDING_VE and TDCS.TD_CTLS.PENDING_VE_DISABLE is 30 
enumerated by TDX_FEATURES0.PENDING_EPT_VIOLATION_V2 (bit 16), readable by TDH.SYS.RD*.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 81 of 153 
Section 2:  Intel TDX Module Architecture Specification  Table 9.4:  Guest TD (L1) Access to a PENDING Page  
Configuration by the Host VMM  (TD_PARAMS Input 
to TDH.MNG.INIT)  Configuration by the 
Guest TD  Behavior on Guest TD 
Access of a PENDING 
Page  ATTRIBUTES.  
SEPT_VE_DISABLE  CONFIG_FLAGS.  
FLEXIBLE_PENDING_VE  TDCS.TD _CTLS . 
PENDING_VE_DISABLE  
0 0 0 #VE 
1 0 #VE 
1 TD Exit  (EPT Violation)  
1 0 1 TD Exit  (EPT Violation)  
1 0 #VE 
 
9.11. Page Merge :  TDH.MEM.PAGE.PROMOTE  
The host VMM can merge the mapping of 512 consecutive 4KB or 2MB pages to a single 2MB or 1GB page, respectively.  
To do that, the host VMM should  first perform the TLB tracking protocol on the large (2MB or 1GB) GPA range.  5 
The host VMM should first  call TDH.MEM.RANGE.BLOCK  which operates on the EPT page for the large range (EPT for 
2MB, EPD for 1GB).  TDH.MEM.RANGE.BLOCK  marks the parent EPT entry for that EPT page as BLOCKED  and records the 
TD epoch in the PAMT entry of the EPT page .  Figure 9.9 below  shows the situation after TDH.MEM.RANGE.BLOCK  blocked 
a 2MB GPA range.  
EPD
NL_MAPPED
PT = PT_EPTPAMT_4K Entry
PT = PT_EPT
BEPOCH setPAMT_4K Entry4KB TD Private Page 
@ PA XPA = X
MAPPED
PT = PT_REG512 Consecutive PAMT_4K Entries4KB TD Private Page
@ PA X + 511*4KEPT
PA = X + 511*4K
MAPPED
PT = PT_REG512 Consecutive 4KB TD Private Pages
PAMT 2MB Sub -BlockOWNER = TDR0
PT = PT_NODEPAMT_2M Entry2MB Range
@ PA X
 10 
Figure 9.9:  Typical State after  Blocking a Range of 512 Consecutive 4KB TD Private Pages  
Typically, t he host VMM then calls TDH.MEM.TRACK  and performs a round of IPIs .  After that, there should be no active 
address translation to the large (2MB or 1GB) GPA range.  
The actual merge is done by TDH.MEM.PAGE.PROMOTE  which has the following inputs:  
• The large range GPA  15 
• The large page level (2MB or 1GB)  
At a high level, TDH.MEM.PAGE.PROMOTE  works as follows:  
1. Check  the TLB tracking condition for the large range GPA (i.e., the EPT or EPD page for that range).  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 82 of 153 
Section 2:  Intel TDX Module Architecture Specification  2. Check  that all 512 entries of that EPT or EPD page are in the MAPPED  state and point to leaf pages whose physical 
address is contiguous within the same 2MB or 1GB range.  
If all checks pass, TDH.MEM.PAGE.PROMOTE  does the following:  
3. Mark all the PAMT_4K or PAMT_2M entries of the small  leaf pages (4KB or 2MB, respectively) as PT_NDA.  
4. Mark the PAMT_2M or PAMT_1G entry of the merged large (2MB or 1GB, respectively) pages as PT_REG.  5 
5. Set the parent EPT entry to point to the merged large page and  mark it as present.  
6. Reclaim the original SEPT physical page as described in 8.5.3 . 
Server Platforms:  The host VMM should flush the  former EPT or EPD physical page’s cache lines and initialize its content 
before it is reused, as described in 8.5.1 . 
Figure 9.10 below  shows a typical 2MB merged page after TDH.MEM.PAGE.PROMOTE . 10 
PAMT 2MB Sub -BlockEPD Former EPT
MAPPED
PT = PT_REGPAMT_2M Entry4KB Unmapped
Page
@ PA X
OWNER = N/A
PT = PT_FREE512 Consecutive PAMT_4K Entries4KB Unmapped
Page
@ PA X + 511*4K
OWNER = N/A
PT = PT_FREE2MB TD Private 
Page
@ PA X
OWNER = N/A
PT = PT_FREEPAMT_4K Entry
 
Figure 9.10:  Typical State of a 2MB TD Private Page after TDH.MEM.PAGE.PROMOTE  
Refer also to the software flow described in 3.3.1.3 . 
9.12. Page Split :  TDH.MEM.PAGE.DEMOTE  
The host VMM can split the mapping of a single 2MB or 1GB page to 512 consecutive 4KB or 2MB pages, respectively.  To 15 
do that, the host VMM should  first perform the TLB tracking protocol on the large (2MB or 1GB) page.  
The host VMM should first call TDH.MEM.RANGE.BLOCK  on the large page.  TDH.MEM.RANGE.BLOCK  marks the parent 
EPT entry for that page as BLOCKED  and records the TD epoch in the PAMT entry of the page .  Figure 9.11 below  shows 
the typical situation after TDH.MEM.RANGE.BLOCK  blocked a 1GB large page . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 83 of 153 
PAMT 1GB BlockEPDPT
BLOCKED
PT = PT_REG
BEPOCH setPAMT_1G Entry2MB Unmapped
Page
@ PA X
OWNER = N/A
PT = PT_NODE512 Consecutive PAMT_2M Entries2MB Unmapped
Page
@ PA X + 511*2M
OWNER = N/A
PT = PT_NODE1GB TD Private Page
@ PA X 
Figure 9.11:  Typical State after Blocking a 1GB Page  
Typically, t he host VMM then calls TDH.MEM.TRACK  and performs a round of IPIs.  After that, there should be no active 
address translation to the large (2MB or 1GB) page.  
The actual split is done by TDH.MEM.PAGE.DEMOTE  which has the following inputs:  5 
• The large page GPA  
• The physical address of a free page that will be used for a new EPT or EPD page  
At a high level, TDH.MEM.PAGE.DEMOTE  works as follows:  
1. Check  the TLB tracking condition for the large page.  10 
2. Check  that the physical page for the new EPT or EPD is marked as free in the PAMT.  
If all checks pass, TDH.MEM.PAGE.DEMOTE  does the following:  
3. Mark the PAMT_2M or PAMT_1G entry of the large (2MB or 1GB respectively) page as PT_NDA.  
4. Mark all the PAMT_4K or PAMT_2M entries of the small (4KB or 2MB respectively) consecutive leaf pages as PT_REG.  
5. Initialize the new SEPT  page with 512 EPT entries pointing to the 512 consecutive leaf pages.  15 
6. Mark the new SEPT  page’s PAMT entry as PT_EPT.  
7. Set the parent EPT entry to point to the new EPT or EPD page.

7. Set the parent EPT entry to point to the new EPT or EPD page.  
Figure 9.12 below  shows the typical state of a  1GB GPA range  after TDH.MEM.PAGE.DEMOTE . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 84 of 153 
EPDPT
NL_MAPPED
PT = PT_EPTPAMT_4K Entry2MB TD Private 
Page
@ PA XPA = X
MAPPED
PT = PT_REG512 Consecutive PAMT_2M Entries2MB TD Private 
Page
@ PA X + 511*2MEPD
PA = X + 511*2M
MAPPED
PT = PT_REG512 Consecutive 2MB TD Private Pages
PAMT 1GB BlockOWNER = N/A
PT = PT_NODEPAMT_1G Entry1GB Range
@ PA X 
Figure 9.12:  Typical State of a 1GB TD Private Range after TDH.MEM.PAGE.DEMOTE  
TDH.MEM.PAGE.DEMOTE supports demotion of PENDING pages.  
Refer also to the software flow described in 3.3.1.4 . 
9.13. Relocating TD Private Pages:  TDH.MEM.PAGE.RELOCATE  5 
The host VMM can relocate a 4KB TD private page to another HPA using TDH.MEM.PAGE.RELOCATE .  This is useful for, 
e.g., physical address space de -fragmentation.  The host VMM must first perform the TLB tracking protocol on the page.  
The host VMM  should  first call TDH.MEM.RANGE.BLOCK  on the target page.  TDH.MEM.RANGE.BLOCK  marks the parent 
EPT entry for that page as BLOCKED  (if it was MAPPED ) or PENDING _BLOCKED (if it was PENDING ) and records the TD 
epoch in the PAMT entry of the page.  10 
address translation to target page.  
The actual relocation is done by TDH.MEM.PAGE.RELOCATE  which has the following inputs:  
• The page GPA  
• The target  HPA to which the page will be relocated  15 
At a high level, TDH.MEM.PAGE.RELOCATE  works as follows:  
2. Check  the TD has been initialized.  
3. Check  the target  physical page is marked as free in the PAMT.  
4. Perform a Secure EPT walk to locate the parent Secure EPT leaf entry that maps the TD private page.  Check  that the 20 
entry has been blocked and get the current HPA.  
5. Check  the TLB tracking condition for the page.  
If all checks pass, TDH.MEM.PAGE.RELOCATE  does the following:  
6. Copy the current physical page to the target  physical page using direct writes (MOVDIR64B).  
7. Reclaim the old physical page as described in 8.5.3 . 25 
8. Mark the PAMT entry of the target  page as PT_ REG.  
9. Update the Secure EPT entry with the new physical page HPA.   Set its state to MAPPED  or PENDING  depending on 
whether its previous state was BLOCKED  or PENDING _BLOCKED, respectively.  
Server Platforms:  The host VMM should flush the  old physical page’s cache lines and initialize its content before it is 
reused, as described in 8.5.1 . 30 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 85 of 153 
Section 2:  Intel TDX Module Architecture Specification  9.14. Removing TD Private Pages :  TDH.MEM.PAGE.REMOVE  
The host VMM can remove  TD private pages using TDH.MEM.PAGE.REMOVE , freeing them for any use .  4KB, 2MB and 
1MB pages can be removed – no demotion is required for large pages.  The host VMM should  first perform the TLB 
tracking protocol on the page.  
The host VMM should first call TDH.MEM.RANGE.BLOCK  on the target page.  TDH.MEM.RANGE.BLOCK  marks the parent 5 
epoch in the PAMT entry of the page.  
The actual removal is done by TDH.MEM.PAGE.REMOVE  which has the following inputs:  10 
• The page level ( 4KB, 2MB or 1GB)  
At a high level, TDH.MEM.PAGE.REMOVE  works as follows:  
1. Check  the TLB tracking condition for the page.  
2. Check  that the mapping size of the page fits the input parameter.  15 
If all checks pass, TDH.MEM.PAGE.REMOVE  does the following:  
3. Mark the EPT entry for the target page as FREE . 
4. Reclaim the physical page as described in 8.5.3 . 
Server Platforms:  The host VMM should flush the  physical page’s cache lines and initialize its content before it is 
reused, as described in 8.5.1 . 20 
Refer also to the software flow described in 3.3.1.2 .  
9.15. Removing a Secure EPT Page :  TDH.MEM.SEPT.REMOVE  
The host VMM can remove a Secure EPT page using TDH.MEM.SEPT.REMOVE , freeing it for any use, provided all its 
entries are FREE .  The host VMM should  first perform the TLB tracking protocol on the page.  
The host VMM should first call TDH.MEM.RANGE.BLOCK  on the Secure EPT page.  TDH.MEM.RANGE.BLOCK  marks the 25 
parent EPT entry for that page as BLOCKED  and records the TD epoch in the PAMT entry of the page.  
Typically, th e host VMM then calls TDH.MEM.TRACK  and performs a round of IPIs.  After that, there should be no active 
address translation to GPA range presented by the Secure EPT page to be removed.  
The actual removal is done by TDH.MEM.SEPT.REMOVE  which has the following inputs:  
• The Secure EPT page GPA  30 
• The EPT level  
At a high level, TDH.MEM.SEPT.REMOVE  works as follows:  
2. Check  that the mapping size of the page fits the input parameter.  
3. Check  that all 512 entries of the Secure EPT page are PT_NDA.  35 
If all checks pass, TDH.MEM.SEPT.REMOVE  does the following:  
5. Mark the EPT entry for the Secure EPT page as FREE . 
Server Platforms:  The host VMM should flush the  physical page’s cache lines and initialize its content before it is reused, 
as described in 8.5.1 . 40 
9.16. Unblocking a GPA Range :  TDH.MEM.RANGE.UNBLOCK  
The host VMM can unblock previously blocked TD private GPA ranges using TDH.MEM.RANGE.UNBLOCK , returning them 
to their original state.  4KB, 2MB and 1MB GPA ranges can be unblocked.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 86 of 153 
Section 2:  Intel TDX Module Architecture Specification  The host VMM should first complete the TLB tracking protocol on the GPA range.  It typically  calls TDH.MEM.TRACK  and 
performs a round of IPIs.  After that, there should be no active address translation to target page.  
The actual unblocking is done by TDH.MEM.RANGE.UNBLOCK  which has the following inputs : 
• The GPA  
• The GPA range  level ( 4KB, 2MB or 1GB)  5 
At a high level, TDH.MEM.RANGE.UNBLOCK  works as follows:  
1. Check  the TLB tracking condition for the GPA range . 
2. Check  that the mapping size of the GPA range  fits the input parameter.  
If all checks pass, TDH.MEM.RANGE.UNBLOCK  does the following:  
3. Mark the EPT entry for the target GPA as MAPPED  (if it was BLOCKED ) or PENDING  (if it was PENDING _BLOCKED).   10 
Refer also to the software flow described in 3.3.1.5 . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 87 of 153 
Section 2:  Intel TDX Module Architecture Specification  10. TD VCPU  
This chapter discusse s multiple items related to TD VCPUs.  
10.1. VCPU Transitions  
This section describes transitions between running in the host VMM, TDX module and guest TD VCPU.  
Note:  Additional transitions that are applicable to partitioned TDs are discussed in the [TD Partitioning Spec].  5 
(Logical)
(Logical)VCPU
Handler
SEAMCALL 
Entry 
Point
VMRESUME
VM Exit
SEAMCALL
from TDVPS 
(after
TD State 
from TDVPSNormal
TDVPS
(incl.
 TD VMCS)LP-Scope 
SEAM VMCS)
VMX Non -Root Mode VMX Root ModeSave TD State to 
XMM)
 
Figure 10.1:  TD VCPU Transitions Overview  
10.1.1.  Initial TD Entry, Asynchronous TD Exit and Subsequent TD Entry  
On the i nitial TD entry  to a TD VCPU , the TDX module  restores the initial TD VCPU state from TDVPS (including TD VMCS).   
Following a successful TDH.VP.ENTER, asynchronous TD exit may happen as a result of events such as interrupts, EPT 10 
violations etc.  In such case, the TDX module saves the TD VCPU state into TDVPS (including TD VMCS).  Most of the host 
VMM VCPU state that may have been used by the TD is initialized.  For a detailed description of VMM state following 
TDH.VP.ENTER, see the [ TDX Module ABI Spec ].

SEAMCALL
from TDVPS 
(after
TD State 
TDVPS
(incl.
SEAM VMCS)
XMM)
 
TDH.VP.ENTER, see the [ TDX Module ABI Spec ]. 
On the subsequent TD entry following an asynchronous TD exit, the TDX module restores the TD VCPU state from TDVPS 
(including TD VMCS).  The host VMM does not impact the VCPU state except in one case: a trap -like asynchronous TD 15 
exit from a guest -side interface function  may indicate that the host VMM can apply a recoverability hint in the following 
TD entry .  In this case, the host VMM provides a recoverability hist to the guest TD, which is combined into the guest -side 
interface function’s completion status  returned in RAX . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 88 of 153 
TDX
ModuleTD VCPU
Host 
VMM1.Save selected host VMM CPU 
state
2.Associate VCPU
from TDVPS
4.VMLAUNCH/VMRESUME1.Examine exit reason, decide 
2.Save non -VMCS CPU state in 
TDVPS
3.Init or restore host VMM 
CPU stateVM
exitVM
entry
SEAMRET
TDH.VP.ENTERHandle TD Exit 
(e.g., interrupt)
 
Figure 10.2:  Example of Asynchronous TD Exit and TD Resumption  
10.1.2.  Synchronous TD Exit and Subsequent TD Entry  
TDG.VP.VMCALL provides a channel for the guest TD to communicate with the host VMM.  5 
The guest TD can initiate a synchronous TD exit by invoking TDG.VP.VMCALL.  The RCX input parameter of selects the 
GPRs (from RBX, RDX, RBP, RDI, RSI and R8 through R15) and XMM registers whose value is passed through to the host 
VMM as the output of TDH.V P.ENTER.  RCX itself is passed as -is to the output of TDH.VP.ENTER.  Other CPU state 
components, including GPRs and XMM registers not selected by RCX, are saved in TDVPS and set to fixed values.    
On the subsequent TDH.VP.ENTER, the RCX value that was used for TDG.VP.VMCALL selects the GPRs (from RBX, RDX, 10 
RBP, RDI, RSI and R8 through R15) and XMM registers whose value is passed through to the guest TD.  Other CPU state 
components, including GPRs and XMM registers not selected by RCX, are restored from RCX.  
For details, see the TDH.VP.ENTER and TDG.VP.VMCALL definitions in the [ TDX Module ABI Spec ]. 
 
TDX
ModuleTDVCPU
Host 
state
from TDVPS, pass through 
selected GPRs and XMMs
on synchronous TD exit
TDVPS, pass through 
exitVM
entry
SEAMRET
TDH.VP.ENTERHandle TD 
Request and 
Prepare a 
ResponseTDG.VP.VMCALLHandle VMM
Respon sePrepare a 
Request
 15 
Figure 10.3:  Example of Synchronous TD Exit and TD Resumption  
10.1.3.  VCPU Activity State Machine  
The VCPU activity state machine, controlled by TDVPS.VCPU_STATE  as shown in Table 10.1 below  and shown in Figure 
10.4 below , helps ensure  the following:   
• A VCPU can be entered  only when its logical TDVPS control structure , composed of TDVPR and TDCX  pages , is 20 
available  in memory and has been initialized by TDH. VP.INIT or successfully imported by TDH.IMPORT.STATE.VP.  
• A VCPU can be entered only if its state is consistent ( no non -recoverable TD exit happened).  
• TD entry is done properly, depending on whether it is the first entry or on the last TD exit type.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 89 of 153 
Section 2:  Intel TDX Module Architecture Specification  Table 10.1:  TDVPS.VCPU_STATE Definition  
VCPU_UNINITIALIZED  VCPU has not been initialized yet by TDH.VP.INIT.  
VCPU_IMPORT  The VCPU state has been incompletely imported.  
VCPU_READY  The VCPU is ready to be executed.  
VCPU_ACTIVE  VCPU is active ( logical TDX non -root mode) on some LP.  
For a partitioned TD, a VCPU is considered active regardless of 
whether it executes in the L1 VM or one of the L2 VMs.  For details, 
see the [TD Partitioning Spec].  
VCPU_DISABLED  VCPU is being torn down.  
 
TD Entry and TD Exit transitions normally toggle between the VCPU_READY state and the VCPU_ACTIVE state, except 
when a non -recoverable VCPU TD Exit ( due to a Triple Fault) transitions to a VCPU_DISABLED state.  
TDH.VP.CREATE
VCPU_READY
TD VCPU may be enteredVCPU_ACTIVE
TD VCPU running on an LPTDH.VP.ENTER
TDH.VP.ADDCX TDH.VP.INIT
TD Exit
TD Exit
 [non -recoverable
VCPU state]
VCPU_DISABLED
TD VCPU is disabledVCPU_UNINITIALIZED
TD VCPU has not been 
initialized
VCPU_IMPORT
TD VCPU is being importedTDH.IMPORT.STATE.VP
[interrupted]
TDH.IMPORT.STATE.VP
[success]Partitioned TD:
L1→L2 VM Entry,
L2→L1 VM Exit
[VCPU_DISABLED]
 5 
Figure 10.4:  VCPU Activity State Machine  
LAST_TD_EXIT  
In the VCPU_READY and VCPU_IMPORT states, a LAST_TD_EXIT sub -state indicates what was the last TD exit and how a 
subsequent TD entry should be done.  
Table 10.2:  TDVPS.LAST_TD_EXIT Definition  10 
Name  Description  
ASYNC_FAULT  Last TD exit was due to an asynchronous event (non -TDG.VP.VMCALL) which caused a fault -
like exit, i.e., the VCPU state is as if the guest instruction has not been executed.  VCPU 
state has been fully saved on TD exit and will be restored on the next TD entry.  
ASYNC_TRAP  Last TD exit was due to an asynchronous event  that happen as part of a guest -side interface 
function  (non -TDG.VP.VMCALL) which caused a trap -like exit, i.e., the VCPU state is as if the 
guest instruction has been executed.  VCPU state has been fully saved on TD exit and will be 
restored on the next TD entry.  On the next TD entry, the host VMM provides t he guest with 
a recoverability hint.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 90 of 153 
Section 2:  Intel TDX Module Architecture Specification  Name  Description  
TDVMCALL  Last TD exit was due to a TDG.VP.VMCALL.  On the next TD entry, most GPR and all XMM 
state will be forwarded to the guest TD from the host VMM.  
 
CURR_VM  
For a partitioned TD, CURR_VM indicates the current VM index for the VCPU.  For details, see the [TD Partitioning Spec].  
10.2. TD VCPU TLB Address Space Identifier (ASID)  
Non-root mode cached address translations are tagged with unique Address Space Identifiers (ASIDs).  The goal of TD 5 
ASIDs is to reduce the need to flush TLB entries on TD Entry and TD Exit due the associated performance costs as a result 
of the flushing.  
10.2.1.  TD ASID Components  
Table 10.3 below  shows a high -level view of the components of the TD ASID.  The exact structure is micro -architectural.  
Table 10.3:  TD ASID  10 
Field  Size 
(Bits)  Description and TDX Usage  
SEAM  1 This is an implicit bit 16 of VPID not directly visible to software.  It is set to 1 by the 
CPU in SEAM mode.  This bit prevents overlap with legacy (non -TDX)  ASIDs.  
VPID  16 The TDX module assigns a platform unique VPID for each TD.  
If a TD is partitioned, the TDX module assigns a platform unique VPID for each VM in 
that TD.  See the [TD Partitioning Spec] for details.  
 
EPTP  40 Bits [51:12] of the EPTP, which for a TD points to the Secure  EPT root – HKID bits are 
cleared to 0  
Note that EPTP is unique per TD and is used as an ASID component for both Secure 
EPT and Shared EPT  translations caching.  
PCID  16 Same as legacy PCID  
 
Note:  All VCPUs of the same TD share the same ASID.  Consequently, whenever TDH.VP.ENTER is invoked on a certain 
LP, with a VCPU that is different than the last one that executed on that LP, the TDX module flushed cached TLB 
translations for the TD, using INVEP T. 
10.2.2.  INVEPT by the Host VMM for Managing the Shared EPT  15 
The same ASID based on the TD’s EPTP is used for caching both secure and shared EPT translations (remember:  EPTP is 
the HPA of the secure  EPT root page).  Thus, to flush shared EPT translations, the host VMM uses INVEPT specifying the 
TD’s EPTP, not its Shared EPTP.  The host VMM can obtain the value of EPTP from the TD VMCSs using TDH.VP.RD . 
If a TD is partitioned, then to flush shared EPT translations for each L2 VM, the host VMM uses INVEPT specifying that L2 
VM’s EPTP, not its Shared EPTP.  The host VMM can obtain the value of EPTP from the L2 VMCSes using TDH.VP.RD.  20 
An alternative method the host VMM may use is to do TLB tracking similar to how it’s done for Secure EPT, i.e., execute 
TDH.MEM.TRACK and a round of IPI.  Contrary to Secure EPT, this is not enforced by the TDX module.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 91 of 153 
Section 2:  Intel TDX Module Architecture Specification  10.3. VCPU -to-LP Association  
10.3.1.  Non -Coherent Caching  
Some TD VCPU state is non -coherently cached.  This includes:  
• Address translations (TLB/PxE entries) must be explicitly flushed in case they may be stale.

• Address translations (TLB/PxE entries) must be explicitly flushed in case they may be stale.  
• TD VMCS is cached by the CPU.  VMX architecture requires making a VMCS current by VMPTRLD before using it with 5 
most VMX instructions, and then explicitly writing it to memory and making it non -current by VMCLEAR before the 
VMCS memory image can be handled (e.g., by making it current on another LP).  
This non -coherent caching implies that some explicit and/or implicit operations are done to help guarantee correctness.   
This is described in the following sections.  
10.3.2.  Intel TDX Functions  for VCPU -LP Association and Dis -Association  10 
ASSOC_LPID = LP2
• LP2's current/working 
VMCS is VCPU x VMCS
• Cached address 
translations & paging 
structures may exist
• TD's HKID may not be 
freed TDH.VP.INIT
on LP2
TDH.VP.FLUSHASSOC_LPID = None
• VCPU x VMCS is not 
current/working VMCS 
on any LP
• No VCPU x cached 
address translations & 
paging structures on 
any LPASSOC_LPID = LP1
• LP1's current/working 
freed TDH.VP.ENTER
on LP2
Any other 
VCPU -specific
interface function
on LP2TDH.VP.INIT
on LP1
on LP1
Any other 
on LP1
TDH.VP.FLUSHTDH.VP.ENTER
on LP2
Any other
on LP2Any other
on LP1TDH.VP.ENTER
on LP1
 
Figure 10.5:  VCPU Association  State Machine  
The following Intel TDX module  mechanisms are designed to help ensure  correct and secure operation:  
• TD VCPU to LP association is many -to-one.  A TD VCPU can be  associated with at most one LP at any given time.   An 
LP may be associated with multiple VCPUs.  15 
• VCPU to LP association is implicitly done by any VCPU -specific SEAMCALL flow, including TDH.VP.ENTER .  Those flows 
check that the VCPU is either already associated with the current LP or is not associated with any LP.  
• If the host VMM wishes to associate a VCPU with another LP, it must explicitly flush the VCPU state on the LP currently 
associated with it using TDH.VP.FLUSH .  This function flushes  TLB for the TD ASID  and extended paging structure 
(EPxE) caches using INVEPT .  It flush es the VMCS cache using  VMCLEAR.  For details, see the [ TDX Module ABI Spec ]. 20 
• If the VMM wishes to reclaim the TD ’s private HKID, thus making the TDVPS memory inaccessible, it must explicitly 
flush the VCPU state on the LP currently associated with it.  This is described in 5.5. 
10.3.3.  Performance Considerations  
• Migrating VCPUs between LPs is costly.  As described above, it involves flushing address translation caches, paging 
structure caches and VMCS cache.  The host VMM should minimize that for best performance.  25 
• Address translation and paging structure caches are flushed at TD -scope on the current LP.  Th is flushing  impacts the 
(possibly non -typical) case where multiple VCPUs of the same TD are associated with a single LP.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 92 of 153 
Section 2:  Intel TDX Module Architecture Specification  11. CPU Virtualization ( Non -Root Mode Operation ) 
11.1. Initial State  
Intel SDM, Vol. 3, 9.1.1  Processor State after Reset  
11.1.1.  Overview  5 
As designed, m ost of the TD VCPU initial state is the same as the processor architectural state after INIT.   However, there 
are some differences:  
• The TD VCPU starts its life in protected (32 -bit) non -paged mode, not in real mode.  It is allowed only to switch to 
64b mode.  This impacts the initial state of segment registers, CRs and MSRs.  Mode restrictions in SEAM  non-root 
mode are described below . 10 
• The IA32_EFER MSR is initialized to support the CPU modes described below . 
• The initial values of some GPRs provide some basic information to the guest TD as described in 11.1.2 below .  This 
information should be sufficient for the vBIOS to set up paging tables and switch as soon as possible to 64b mode, 
where it can use the TDCALL leaf functions.  
See also the TDVPS fields and TD VMCS guest state area in the [ TDX Module ABI Spec ]. 15 
11.1.2.  Initial State of Guest TD GPRs  
As designed, the following initial state is different than the architectural INIT state:  
Table 11.1:  Initial Values of GPRs Different from their Architectural INIT Values  
Register  Bits Initial Value  
RBX 5:0 GPAW, the effective GPA width (in bits) for this TD ( do not  confuse with MAXPA)  – 
SHARED bit is at GPA bit GPAW -1 
Only GPAW values 48 and 52 are possible . 
63:6  Reserved:  set to 0  
RCX, R8  63:0  The value of RCX and R8 is p rovided as an input to TDH.VP.INIT (the same value in both 
GPRs).  No checking is done on this value; the intention is for vBIOS to read R CX 
immediately after the first TDH.VP.ENTER  and use the RCX value  appropriately as set by 
software convention.  
RDX  31:0  Set to the virtualized Family/Model/Stepping returned by CPUID(1).EAX .  The value is 
calculated by TDH.SYS.INIT as to have the minimum Stepping ID across all packages . 
63:32  Reserved:  set to 0  
RSI 31:0  Virtual CPU index, starting from 0 and allocated sequentially on each successful 
RIP 63:0  Set to 0xFFFFFFF0 (i.e., 4GB - 16B)  
 
11.1.3.  Initial State of CRs  20 
• CR0 is initialized to 0x0021 – bits PE (0) and NE (5) are set to 1, and all other bits are cleared to 0.  See 11.6.1  for 
details.  
• CR4 is initialized to 0x2040 – bits MCE (6) and VMXE (13) are set to 1, and all other bits are cleared to 0.  Note that 
the virtualized value of VMXE is 0, due to the setting of the TD VMCS “CR4 guest/host mask” and “CR4 read shadow” 25 
controls.  See 11.6.2  for details.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 93 of 153 
Section 2:  Intel TDX Module Architecture Specification  11.1.4.  Initial State of Segment Registers  
• CS, DS, ES, FS, GS and SS are initialized with a base of 0 and limit of 0xFFFFFFFF.  
• LDTR, TR and GDTR are initialized with a base of 0 and limit of 0xFFFF.  
• IDTR is initialized as invalid (limit of 0).  5 
11.1.5.  Initial State of MSRs  
• IA32_EFER is initialized to 0x901  – SCE (bit 0) , LME (bit 8) and NXE (bit 11) are set to 1 , and all other bits are 
cleared to 0.  10 
11.2. Guest TD Run Time Environment Enumeration  
Guest software can be designed to run either as a TD, as a legacy virtual machine , or directly on the CPU, based on 
enumeration of its run -time environment.  Figure 11.1 below  shows a typical flow used by guest software.  
TDX-SpecificCPUID(0).EAX >= 0x21Vendor ID ==
“IntelTDX ” ?
Y
Continue as a Legacy GuestCPUID(0x400000xx)NNot Intel TDXNCPUID(0)
CPUID(1)Intel?
ECX[31]Y
1Non-IntelN
0 Not Para -
VirtualizedLegacyLegend
TDCALL(TDG.VP.INFO)
TDCALL(TDG.SYS.RD*)
TDCALL(TDG.VM.RD*)
TDCALL(TDG.VP.RD*)CPUID(0x21, 0x0)Get vendor ID (EBX:EDX:ECX) 
and max sub-leaf (EAX)TDX
Y
Enumerate TD configuration
 
Figure 11.1:  Typical Run -Time Environment Enumeration by a Guest TD  15 
CPUID leaf 0x21 emulation is done by the Intel TDX module.  Sub -leaf 0 returns the values shown below.  Other sub -
leaves return 0 in EAX/EBX/ECX/EDX. 
Table 11.2:  TDX Enumeration by CPUID(0x21,0)  
GPR  Value (Hex)  Description  
EAX 0x00000000  Maximum sub -leaf number  
EBX 0x65746E49  “Inte” 
ECX 0x20202020  “    “ 
EDX  0x5844546C  “lTDX” 
November 2023   . Page 94 of 153 
Section 2:  Intel TDX Module Architecture Specification  Once the guest software discover s that it runs as a TD, it can use TDG.VP.INFO to get basic information.  It can also use 
the metadata read functions TDG.SYS.RD*, TDG.VM.RD* and TDG.VP.RD*.  
11.3. CPU Mode Restrictions  
Intel SDM, Vol. 3, 2.2  Modes of Operation  
Intel SDM, Vol. 3, 9.8.5  Initializing IA -32e Mode  5 
A TD OS running in SEAM  non-root mode is required to be a 64-bit OS.  The Intel TDX module helps enforce this with the 
restrictions described below . 
Table 11.3:  CPU Mode Restrictions in SEAM  Non -Root Mode  10 
Restriction  Description  
Modes  In SEAM  non-root mode, the CPU is allowed to run in the following modes:  
• Protected mode (32 -bit) with no paging (CR0.PG  == 0)

• Protected mode (32 -bit) with no paging (CR0.PG  == 0) 
• IA-32e mode with 4 -level or 5 -level paging (CR0.PG  == 1), with the sub -modes 
controlled by CS.L:  
To achieve this, CR0.PE and IA32_EFER.LME are enforced to 1, as described in the 
following sections.  
Enabled  The guest TD run s in Normal Cache Mode . 
sections.  
 
11.4. Instructions Restrictions  
The Intel TDX module  is designed to block certain instructions from executing in TDX non-root mode.  Execution of those 
instructions results in a VM exit to the Intel TDX module, which then injects an exception to the guest TD.  This exception 
can be #UD, a #GP(0) or, in case where no Intel64 architectural exception can be used, a #VE (described in 11.10 ). 15 
11.4.1.  Unconditionally Blocked Instructions  
 Instructions that Cause a #UD  Unconditionally  
• Most  VMX instructions:  INVEPT, INVVPID, VMCLEAR, VMFUNC, VMLAUNCH, VMPTRLD, VMPTRST, VMREAD, 
VMRESUME, VMWRITE, VMXOFF, VMXON  20 
• RSM  
• GETSEC  
• SEAMCALL , SEAMRET  
 Instructions that Cause a #VE Unconditionally  
• String I/O (INS*, OUTS*), IN, OUT  25 
• HLT 
• VMCALL  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 95 of 153 
 Instructions that Cause a #UD or #VE  Depending on Feature Enabling  
• PCONFIG (see 11.15 ) 
 Other Cases  of Unconditionally Blocked Instructions  
• Guest TD execution of ENQCMDS when CPL is 0 results in a #UD.  Otherwise,  it results in a #GP(0).  5 
11.4.2.  Conditionally Blocked Instructions  
Execution of some instructions may be conditionally blocked, depending on which CPU features are configured and 
available for the TD, as described in the following sections.  
11.4.3.  Other Exception Cases  
In many cases, instructions are not blocked but yet may cause exceptions due to other conditions.  For example, following 10 
is a very partial list:  
• CPUID may cause a #VE if the CPUID leaf and sub -leaf are not virtualized by the TDX module.  
• RDMSR and WRMSR may cause a #GP(0) if an MSR is virtualized as non -existing, or a #VE if an MSR is not virtualized.  
11.5. Extended Feature Set  
Intel SDM, Vol. 1, 13  Managing State Using the XSAVE Feature Set  15 
Intel SDM, Vol. 3, 13  System Programming for Instruction Set Extensions and Processor Extended State  
11.5.1.  Allowed Extended Features Control  
At the guest TD scope, TDCS.XFAM (Extended Features Allowed Mask)  is provided as an input during guest TD build 
process.  XFAM  is a 64b mask , using the state -component bitmap  format used by extended state ISA (XSAVE, XRSTOR, 
XCR0, IA32_XSS etc.) , which specifies the set of extended features the TD is allowed to use.  20 
XFAM is checked to be compliant with the set of extended features supported by the CPU, as enumerated by CPUID and 
the allowed bit combinations, as shown in  Table 11.4 below . 
11.5.2.  Extended State Isolation  
The Intel TDX module  helps ensure  that any guest TD extended state is saved and isolated from the host VMM across TD 
exit and entry.  It is the VMM’s responsibility to save its own extended state across TD entry and exit.  25 
• Before TDH.VP.ENTER , the host VMM should save (e.g., using XSAVES) any extended state that the guest TD VCPU is 
allowed to use (per XFAM) and the host VMM expects to need after TDH.VP.ENTER  is complete.  
• The TDH.VP.ENTER  function loads the extended state that the TD VCPU is allowed to use, per XFAM, from the VCPU’s 
TDVPS.  An exception to this is when TDH.VP.ENTER  follows a previous TDG.VP.VMCALL  – in the case TDH.VP.ENTER  
does not load the XMM state (corresponding to XFAM bit 1) from TDVPS ; it passes it directly from the host VMM.  30 
• On an asynchronous TD exit, the Intel TDX module  saves the extended state that the TD VCPU was allowed to use, 
per XFAM, to the VCPU’s TDVPS.  It then clears the extended state.  
• On TDG.VP.VMCALL , the Intel TDX module  works similarly, but it selectively does not clear some of  the XMM register 
state (corresponding to XFAM bit 1).  Th at XMM state is passed directly to the host VMM.  
• On completion of TDH.VP.ENTER  (following TD exit), the VMM may restore any extended state that it saved before 35 
11.5.3.  Extended Features Execution Control  
The Intel TDX module  is designed to prohibit the guest TD from using any extended feature not allowed by XFAM.   Many 
extended state features are controlled by XCR0 and IA32_XSS MSR.  Other features are controlled by CR4 or by specific 
MSRs.  40 
XCR0 and 
IA32_XSS MSR  On XSETBV , which attempts to write to XCR0, and o n WRMSR of IA32_XSS , the TDX module emulates 
the architectural behavior of the CPU.  The following cases cause a #GP(0):  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 96 of 153 
Section 2:  Intel TDX Module Architecture Specification  • The new value is not natively valid  for XCR0 or IA32_XSS (it sets reserved bits, sets bits for 
features not recognized by the Intel TDX module , or uses invalid  bit combinations).  
• The new value has any bits set that are not allowed by XFAM.  
 
CR4 On MOV to CR4, the guest TD attempts to set bits not allowed according to XFAM will cause a #GP(0).  
 
Other MSRs  The guest TD attempts to write or read certain MSRs that are not enabled according to XFAM can 
cause a #GP(0) or a #VE, as described below.  
 
The following table describes how a guest TD executes each of the extended features.  
Table 11.4:  Extended Features Enumeration and Execution Control  
Bits U/S Feature  Enumeration7 XFAM 
Value  Description  
0 U FP Always available  1 Always enabled  
1 U SSE Always available  1 Always enabled  
2 U AVX  CPUID(0xD,  0x0).EAX [2] 
CPUID(0x7,  0x0).EBX[2]  
CPUID(0x7,  0x0).ECX[10:9]  
CPUID(0x7,  0x1).EAX[5]  
CPUID(0xD, 0x2).*  0 or 1  Execution is directly c ontrolled by XCR0 . 
4:3 U MPX  CPUID(0xD,  0x0).EAX [4:3]  
CPUID(0x7 , 0x0).EBX[14]  
CPUID(0xD, 0x3).*  
CPUID(0xD, 0x4).*  00 MPX is being deprecated.  
 
7:5 U AVX 512 CPUID(0xD,  0x0).EAX[7:5]  
CPUID(0x7,  0x0).EBX[ 31:30, 
28:26, 21, 17:16 ]  
CPUID(0x7,  0x0).ECX[14 , 
12:11, 6, 1 ]  
CPUID(0x7,  0x0).EDX[8]  
CPUID(0xD, 0x5).*  
CPUID(0xD, 0x6).*  
CPUID(0xD, 0x7).*  000 or 
111 Execution is directly controlled by XCR0.  AVX 512 
may be enabled only if AVX is enabled – i.e., 
XFAM[7:5] may be set to 111 only when XFAM[2] is 
set to 1.  
8 S PT (RTIT)  CPUID(0xD,  0x1).ECX[8]  
CPUID(0x7,  0x0).EBX[25]  
CPUID(0x14).*  
CPUID(0xD, 0x8).*  0 or 1  Execution is controlled by IA32_RTIT_CTL.  If PT is 
enabled by XFAM, the guest TD is allowed access to 
all IA32_RTIT_* MSRs.  Otherwise, any access causes 
#GP(0).  
9 U PK CPUID(0xD,  0x0).EAX[9]  
CPUID(0xD, 0x9).*  0 or 1  Execution is controlled by CR4.PKE (bit 22).  If PK is 
disabled by XFAM, the guest TD is disallowed from 
setting CR4.PKE.  An attempt to set this bit causes a 
#GP(0).  
 
7 An extended feature controlled by bits N:M is available if all bits in the range N:M returned by CPUID are set to 1.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 97 of 153 
Section 2:  Intel TDX Module Architecture Specification  Bits U/S Feature  Enumeration7 XFAM 
10 S ENQCMD 
(PASID)  CPUID(0xD,  0x1).ECX[10]  
CPUID(0xD, 0xA).*  0 Execution is controlled by IA32_PASID MSR . 
There is no direct I/O from guest TDs.  ENQCMD and 
ENQCMDS from the guest TD are not supported and 
cause a #UD or #GP(0) (see 11.4.1.4 ).  Access to 
IA32_PASID causes a #GP(0).  
 
12:11  S CET CPUID(0xD,  0x1).ECX[12:11]  
CPUID(0xD, 0xB).*  
CPUID(0xD, 0xC).*  00 or 
11 Execution is controlled by CR4.CET (bit 23).  If CET is 
setting CR4.CET.  An attempt to set this bit causes a 
#GP(0).   
 
13 S HDC  CPUID(0xD,  0x1).ECX[13]  
CPUID(0xD, 0xD).*  0 Hardware Duty Cycle is controlled by package -scope 
IA32_PKG_HDC_CTL and LP -scope  IA32_PM_CTL1 
MSRs . 
HDC is disabled.  Any guest TD access to the above 
MSRs causes a #VE.  
14 S ULI CPUID(0xD,  0x1).ECX[14]  
CPUID(0x7,  0x0).EDX[5]  
CPUID(0xD, 0xE).*  0 or 1  Execution is controlled by CR4.UINT R (bit 25).  If ULI 
is disabled by XFAM, then:  
• The guest TD is disallowed from setting CR4.ULI.  
An attempt to set this bit causes a #GP(0).  
• The guest TD is disallowed access to all 
IA32_UINT R_* MSRs.  Any access causes a 
#GP(0).  
15 S LBR CPUID(0xD,  0x1).ECX[15]

#GP(0).   
 
MSRs . 
#GP(0).  
15 S LBR CPUID(0xD,  0x1).ECX[15]  
CPUID(0x7,  0x0).EDX[19]  
CPUID(0xD, 0xF).*  
CPUID(0x1C).*  0 or 1  Execution is controlled by IA32_LBR_CTL.  If LBR is 
disabled by XFAM, the guest TD is disallowed access 
to all IA32_LBR_* MSRs.  Any access causes a #GP(0).  
 
16 S HWP  CPUID(0xD,  0x1).ECX[16]  
CPUID(0xD, 0x10).*  0 Execution of Hardware -Controlled Performance State 
is controlled by IA32_HWP  MSRs . 
This feature is disabled.  Access to any of the above 
18:17  U AMX  CPUID(0xD,  0x0).EAX[18:17]  
CPUID(0xD, 0x11).*  
CPUID(0xD, 0x12).*  00 or 
11 Advanced Matrix Extensions ( AMX ) is directly 
controlled by XCR0 . 
19 U APX  CPUID(0x7, 0x1).EDX[21]  
CPUID(0xD,0).EAX[19]  0 or 1  Execution is controlled by CR4.APX (bit 19).  If APX is 
setting CR4.APX.  An attempt to set this bit causes a 
#GP(0).  
November 2023   . Page 98 of 153 
Section 2:  Intel TDX Module Architecture Specification  11.6. CR Handling  
11.6.1.  CR0 
 
Figure 11.2:  CR0  
From the guest TD’s point of view, as virtualized by the Intel TDX module, CR0 bits PE (0) and N E (5) are  always set to 1 , 
and bits NW (29) and CD (30) are always cleared to 0.  10 
Guest TD write s to CR0 are handled by the Intel TDX module as follows:  
• Writes to CR0 that are architecturally invalid  (such as attempts to set bits that must be 0 ) or writes to CR0 that set 
architecturally invalid  bit combinations, result in a #GP(0).  
• Writes to CR0 that are architecturally invalid , but not permitted by the TDX architecture (such as clearing CR0.CD) 
result in a #VE.  15 
• Other writes are allowed.  
For TD migration, the same rules are used for checking the imported value of guest CR0.   Any violation results in a failed 
import.  
11.6.2.  CR4 
Intel SDM, Vol. 3, 24.6.6  Guest/Host Masks and Read Shadows for CR0 and CR4  20 
If a CPU feature is not enabled for the guest TD, the guest TD’s attempt to set the corresponding CR4 bit can result in a 
#GP(0):  
1. Depending on the TD’s XFAM, guest TD modification of CR4 bits PKE (22), CET (23) and UINT R (25) is prevented .  Any 
guest TD attempt to change those bits results in a # GP(0) . 
2. If the TD’s ATTRIBUTES.KL  is 0, guest TD attempts  to set bit KL (19) results in a #GP(0) . 25 
3. If the TD’s ATTRIBUTES.PKS is 0, guest TD attempts to set bit PKS (24) results in a #GP(0).  See 11.14 below . 
4. If the TD’s virtual value of CPUID(7,1).EAX[6] (LASS) is 0, the TD is not allowed to use LASS, and guest TD attempts to 
set bit LASS (27) results in a #GP(0).   
In addition, a ny guest TD attempts to modify  any of the architecturally reserved CR4 bits, or to set architectural -invalid  
bit combinations,  can result in a #GP(0).  30 
From the guest TD’s point of view, t he following bits are virtualized as fixed by Intel TDX module .  Guest TD attempts to 
modify their values result in a #VE:  
• CR4 bit MCE  (6) is fixed  to 1. 
• CR4 bits VMXE  (13) and SMXE (14)  are fixed  to 0.    
For TD migration, the same rules are used for checking the imported value of guest CR4.  Any violation results in a failed 35 
import.  
Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 99 of 153 
Section 2:  Intel TDX Module Architecture Specification  11.7. MSR Virtualization  
11.7.1.  Overview  
From the guest TD’s point of view, as virtualized by the Intel TDX module, MSRs are divided into the following categories:  
• MSRs that are context -switched on TD entry and exit – guest TD access to such MSRs may be full, partial or none  
• MSRs that are not context -switched, but guest TD access is read -only  5 
• MSRs that are not context -switched, and are inaccessible to the guest TD  
MSR behavior can be  either fixed or dependent on the TD configuration via the XFAM , ATTRIBUTES and CPUID 
configuration parameters.  The host VMM has no direct interface to configure specific MSR behavior (e.g., it cannot  set 
a specific MSR to TD exit on write).  Instead, guest TD access violations to MSRs can cause a #GP(0) in most cases where 
the MSR is enumerated as inaccessible by the Intel TDX module  via CPUID virtualization.  In other cases, guest TD access 10 
violations to MSRs can cause a #VE.  A guest TD that wishes to access an MSR that is not allowed by the Intel TDX module  
should  do so via explicit requests from the host VMM using TDCALL(TD G.VP. VMCALL). 
A detailed list of MSR virtualization is provided in the [ TDX Module ABI Spec ]. 
11.7.2.  MSR Configuration by the Host VMM  
For a few MSRs, the virtualized values of some bit field returned to the guest TD when executing RDMSR can be configured 15 
by the host VMM.   Configuration is done as an input to TDH.MNG.INIT.  
Table 11.5:  Host VMM Configurable MSR Field Virtualization  
MSR Bit 
Configuration  Description  
ALLOW_DIRECT  An MSR bit’s virtual value can be configured as follows:  
• Allowed by the host VMM, i.e., reflects the native value returned by the CPU.  
• Forced to 0 by the host VMM, regardless of its native values.  
FORCE_DIRECT  An MSR bit’s virtual value can be configured as follows:  
• Forced to 1 by the host VMM, regardless of whether or not supported by the CPU.  
 
For details, see the TD_PARAMS definition in the [ABI Spec].  
Implication on TD Migration  20 
The virtual MSR values calculated on TDH.MNG.INIT are stored in TDCS .  If the TD is migrated, the values are  exported by 
TDH.EXPORT.STATE.IMMUTABLE and checked on import to the destination TD by TDH.IMPORT.STATE.IMMUTABLE to be 
compatible with the destination platform.  
For MSR bits that are configurable as ALLOW_DIRECT, an imported value of 0 is always allowed, regardless of the 
destination CPU’s native value.  25 
For MSR bits that are configurable as FORCE_DIRECT, an imported value of 1 is always allowed, regardless of the 
destination CPU’s native value.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 100 of 153 
Section 2:  Intel TDX Module Architecture Specification  11.8. CPUID Virtualization  
11.8.1.  CPUID Configuration by the Host VMM  
For some CPUID leaves and sub -leaves, the virtualized bit fields of CPUID return values  (in guest EAX/EBX/ECX/EDX ) are 
configurable by the host VMM.  For such cases, the Intel TDX module  architecture defines two  virtualization types:  
Table 11.6:  Host VMM Configurable CPUID Field Virtualization  5 
CPUID Field 
Virtualization  Description  Comments  
As 
Configur ed Bit fields  for which  the host VMM 
configure s the value seen by the guest TD.  
Configuration is done on TDH.MNG.INIT .  
As 
Configured (if 
Native)  Bit fields for which the host VMM 
configures the value such that the guest 
TD either sees their native value or a 
value of 0.  Configuration is done on 
TDH.MNG.INIT . If a CPUID  bit enumerates a CPU feature, and the 
feature is natively supported, then t he feature can 
either be allowed by the host VMM, or it will be 
effectively deprecated  for the guest TD.  
 
The above CPUID fields can be  specified by the host VMM at guest TD initialization time TDH.MNG.INIT  using the 
TD_PARAMS input structure of TDH.MNG.INIT .  TDH.MNG.INIT  and its input TD_PARAMS structure are described in the 
[TDX Module ABI Spec ].  Configuration is further classified as follows:  
Table 11.7:  CPUID Configuration by the TD_PARAMS Input of TDH.MNG.INIT  10 
TD_PARAMS 
Section  Description  Notes  
CPUID_CONFIG  Bit fields configurable directly based on a configuration 
table  Some bit fields are 
configurable by both 
CPUID_CONFIG and either 
XFAM or ATTRIBUTES.  See 
the discussion below.  XFAM  Bit fields configurable based on the guest TD’s XFAM  
XFAM control of extended features virtualization is 
described in 11.5 . 
ATTRIBUTES  Bit fields  configurable based on the guest TD’s ATTRIBUTES  
Other  Bits fields configurable based on some other field of 
TD_PARAMS   
 
A detailed list of CPUID virtualization is provided in the [ TDX Module ABI Spec ].  For any valid  CPUID leaf / sub -leaf 
combination that is not listed, the Intel TDX module injects a #VE.  
The host VMM should always consult the list of directly configurable  CPUID leaves and sub -leaves , as enumerated by 
TDH.SYS.RD/RD ALL or TDH.SYS. INFO, described in 4.1.2.4 . 15 
 Fine Grained Control of CPU Extended Features Enumeration  
Some CPUID bit fields are configurable based on both CPUID_CONFIG and either XFAM or ATTRIBUTES sections of

TD_PARAMS   
 
Some CPUID bit fields are configurable based on both CPUID_CONFIG and either XFAM or ATTRIBUTES sections of 
TD_PARAMS.  This is intended to support fine-grained virtualization of sub -features of extended features .  For example:  
• The host VMM can configure the TDX module to virtualize some AVX512 as available, but to virtualize other AVX512 
instructions as unavailable.  20 
 Configurable Family/Model/Stepping (CPUID(1).EAX) Enumeration  
By default, the CPU’s Family/Model/Stepping value, as enumerated to the guest TD by CPUID(1).EAX, is set to the native 
value of the platform.  In a multi -package platform, the stepping value is the minimum of all the packages’ native values.   25 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 101 of 153 
Section 2:  Intel TDX Module Architecture Specification  If CPUID(1).EAX is enumerated by the TDX module as configurable, then the host VMM can select the default 
configuration by setting  CPUID(1).EAX in TD_PARAMS.CPUD_CONFIG input to TDH.MNG.INIT to all -0. 
If supported by the TDX module, then if the is migratable (ATTRIBUTES.MIGRATABLE is 1) , the value of CPUID(1).EAX may 
be configured by the host VMM as described below.   This allows the host VMM to create migration pools containing 
multiple CPU types.   As with all configurable features, the host VMM would need to be careful an configure the migratable 5 
TDs virtual F amily /Model /Stepping  values to be recognizable by all platforms in the migration pool.  
Enumeration  TDX module support of CPUID(1).EAX configuration is enumerated by  the global metadata field  
TDX_FEATURES0.FMS_CONFIG (bit 17), which is readable by the host VMM using TDH.SYS.RD*.  For 
details, see the [ABI Spec].  
The TDX module allows the host VMM to configure Family/Model/Stepping to one of a specific set of values.  Those 10 
values are known to the TDX module as CPUs, each conforming to the following criteria:  
• There’s a TDX module version that support the CPU denoted by the Family/Model/Stepping value.  
• The CPU denoted by the Family/Model/Stepping value is “not newer” than the current (native) CPU at the time of 
TD initialization, in a sense that it does not implement any security feature that is not implemented by the current 
CPU.  E.g., that CPU does no t implement some side channel mitigation that the current CPU does not implement.  15 
The specific list of family/model/stepping values is provided by the following global metadata fields), readable by the 
host VMM using TDH.SYS.RD*:  
ALLOWED_FMS  A list of 32 -bit values in CPUID(1).EAX Family/Model/Stepping format.  For each, the allowed Family 
and Model fields are specified.  The Stepping value is the maximum allowed value.  
DISALLOWED_FMS  A list of 32 -bit fields in CPUID(1).EAX Family/Model/Stepping format, listing explicitly disallowed 20 
F/M/S settings.  
11.8.2.  Guest TD Control of CPUID Virtualization  
 Unconditional #VE for all CPUID Leaves and Sub -Leaves  
The guest TD may toggle  on or off the unconditional injection of #VE on all CPUID leaves and sub -leaves , per VCPU.   That 25 
can be done in supervisor mode ( CPL = = 0) and/or user mode ( CPL > 0 ).   For example, this enables the TD OS to control 
CPUID as seen by drivers or by user -level code . 
The guest TD may do this by writing to the VCPU -scope metadata fields CPUID_SUPERVISOR_VE and CPUID_USER_VE 
using TDG.VP.WR.  
For backward compatibility, the guest TD may use  TDG.VP.CPUIDVE.SET , described in the [ TDX Module ABI Spec ]. 30 
 CPUID Leaf/Sub -leaf Specific Control  
A finer grained control is provided per CPUID leaf and sub -leaf that is virtualized by the TDX module.  The guest TD may 
configure the following, per VCPU:  
• #VE injection instead of the normal CPUID virtualization is the guest executed CPUID in supervisor mode ( CPL = = 0). 
• #VE injection instead of the normal CPUID virtualization is the guest executed CPUID in user mode ( CPL > 0 ). 35 
The guest TD may do this by writing to the VCPU -scope metadata field array CPUID_CONTROL using TDG.VP.WR.  
11.8.3.  CPUID Configuration & Checks at Guest TD Migration  
The CPUID virtualization configuration stored in TDCS is exported by TDH.EXPORT.STATE.IMMUTABLE and checked on 
import to the destination TD by TDH.IMPORT.STATE.IMMUTABLE to be compatible with the destination platform.  
CPUID fields that are virtualized as fixed values (defined as “FIXED”), are based on some calculation (defined as 40 
“ASSIGNED”) or that their value depends on the underlying CPU capabilities (defined as “ALLOWED” or “DIRECT”) must 
retain the same value across migration.  
CPUID fields that are virtualized as pass -through (defined as “NATIVE”) are considered fixed once exported and are 
checked for compatibility on import.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 102 of 153 
Section 2:  Intel TDX Module Architecture Specification  11.9. Interrupt Handling and APIC Virtualizati on 
Intel SDM, Vol. 3, 29  APIC Virtualization and Virtual Interrupts  
11.9.1.  Virtual APIC Mode  
• Guest TDs must use x2APIC mode.  xAPIC mode (using memory mapped APIC access) is not allowed.  5 
• Guest TD attempts to RDMSR or WRMSR t he IA32_APIC_BASE MSR cause a #VE to the guest TD.  The guest TD cannot  
disable the APIC.  
11.9.2.  Virtual APIC Access by Guest TD  
Intel SDM, Vol. 3, 30.5 Virtualizing MSR -Based APIC Access  
Guest TDs are allowed access to a subset of the virtual APIC registers, which are virtualized by the CPU as described in 10 
[Intel SDM, Vol. 3,  30.5].  Access to other registers  can cause a #VE .  The guest TD is expected to use a software  protocol 
over TDG.VP.VMCALL  to request such operations from the host VMM.  
#VE
#VE
#VE
#VE
#VEVAPIC AccessVAPIC Access
 
Figure 11.3:  Virtual APIC Access by Guest TD  
 15 
Table 11.8:  x2APIC MSRs (0x800 – 0x8FF) Processing  
MSR Range  MSR Name(s)  Description  Access  On RDMSR  On WRMSR  
0x802  IA32_X2APIC_APICID  APIC ID  RO #VE #VE 
0x803  IA32_X2APIC_VERSION  APIC Version  RO #VE #VE 
0x808  IA32_X2APIC_TPR  Task Priority  RW Read from VAPIC 
page  Write to VAPIC page, 
TPR virtualization  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 103 of 153 
Section 2:  Intel TDX Module Architecture Specification  MSR Range  MSR Name(s)  Description  Access  On RDMSR  On WRMSR  
0x80A  IA32_X2APIC_PPR  Processor Priority  RO Read from VAPIC 
page  #GP(0)  
0x80B  IA32_X2APIC_EOI  End Of Interrupt  WO Read from VAPIC 
EOI virtualization  
0x80D  IA32_X2APIC_LDR  Local Destination  RO #VE #VE 
0x80F  IA32_X2APIC_SIVR  Spurious Interrupt 
Vector  RW #VE #VE 
0x810 -0x817  IA32_X2APIC_ISR0 - 
IA32_X2APIC_ISR7  In-Service  RO Read from VAPIC 
0x818 -0x81F  IA32_X2APIC_TMR0 - 
IA32_X2APIC_TMR7  Trigger Mode  RO Read from VAPIC 
0x820 -0x827  IA32_X2APIC_IRR0 - 
IA32_X2APIC_IRR7  Interrupt Request  RO Read from VAPIC 
0x828  IA32_X2APIC_ESR  Error Status  RW #VE #VE 
0x830  IA32_X2APIC_ICR  Interrupt Command  RW #VE #VE 
0x82F, 
0x832 -0x837, 
0x83A  IA32_X2APIC_LVT_*  Local Vector Table  RW #VE #VE 
0x838  IA32_X2APIC_ INIT _COUNT  APIC Timer  RW #VE #VE 
0x839  IA32_X2APIC_ CUR _COUNT  RO #VE #VE 
0x83E  IA32_X2APIC_DIV_CONF  RW #VE #VE 
0x83F  IA32_X2APIC_SELF_IPI  Self IPI  WO Read from VAPIC 
self-IPI virtualization  
0x838 -0x83D  Reserved  N/A None  #VE #VE 
Other  Reserved  N/A None  #GP(0)  #GP(0)  
 
11.9.3.  Implicit APIC Write #VE  
The following guest operations result in an APIC write VM exit to the TDX module.  The VM exit is trap -like, i.e., it happens 
after the instruction has been executed:  
• WRMSR of IA32_X2APIC_SELF_IPI with EAX[7:4] set to 0, i.e., an interrupt vector value smaller than 16.  5 
• Executing SENDUIPI to send a user -level interrupt.  
In all such cases, the TDX module injects a #VE exception back to the guest TD, with the exit reason indicating an APIC 
write and bits 11:0 of the exit qualification set to the page offset of the write access . 
11.9.4.  Posted  Interrupts  
Intel SDM, Vol. 3, 29 .6 Posted -Interrupt Processing  10 
Non -NMI  interrupt injection into the guest  TD by the host VMM  or the IOMMU can be  done through the posted -interrupt 
mechanism.   If there are pending interrupts in the posted -interrupt descriptor (PID) , the VMM can post a self IPI with the 
notify vector prior to TD entry.    
• The posted -interrupt descriptor (PID) resides in a shared page, directly accessible by the host VMM.  The VMM must

• The posted -interrupt descriptor (PID) resides in a shared page, directly accessible by the host VMM.  The VMM must 
set the TD VMCS’ s “posted -interrupt descriptor address” control (using the TDH.VP.WR  function) to the PA and 15 
shared HKID of the posted -interrupt descriptor.  
• The host VMM must set the TD VMCS’ s “posted -interrupt notification vector” control using the TDH.VP.WR  function.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 104 of 153 
Section 2:  Intel TDX Module Architecture Specification  • To post pending interrupts in the PID, the host VMM can generate  a self IPI with the notif ication  vector prior to TD 
entry.  
When a posted -interrupt notification  vector is recognized in SEAM  non-root mode, the CPU process es the posted -
interrupt descriptor as described in the [Intel SDM].  
If needed, th e guest TD may use a software protocol over TDCALL (TDG.VP.VMCALL ) to ask the VMM to stop interrupt 5 
delivery through the PID . 
Security Implications of Posted Interrupts  
A malicious host VMM or a device may post any virtual interrupt vector in the range 255:31 at any time.  The guest TD 
should be able to process such interrupts without confusing it with a software interrupt that uses the same vector 
number.   The TD’s interrupt handler  for vector V, which expects a software interrupt,  can read the virtual APIC's ISR 10 
register  by reading the applicable IA32_X 2APIC _ISRx  MSRs (0x81 7:0x810 ).  It can check that ISR[ V] is indeed 0 for the 
specific vector.  
TD Migration Implications of Posted Interrupts  
The TD VMCS posted interrupt execution controls are reset to their initial values when the TD is migrated.  The host VMM 
on the destination platform must set them in order to use posted interrupts.  15 
Intel
TDX
Host VMMTDH.VP.
ENTERVM entry
(RFLAGS.IF = 1)
Write notification 
vector NV to x2APIC 
Self IPI MSRPost Interrupt 
Vector PV:
Set PID.PIR[PV]  
and PID.ONNotification
Interrupt 
vector NVPosted interrupt 
vector PV handling
Assumption: 
RFLAGS.IF = 0Interrupt 
Handler
 
Figure 11.4:  Typical Sequence for Posted Interrupt Injection to the Current LP  
TD Partitioning Implications of Posted Interrupts  
Posted interrupts handling for partitioned TDs is discussed in the [TD Partitioning Spec].  
11.9.5.  Pending Virtual Interrupt Delivery Indication  20 
The host VMM can detect whether a virtual interrupt is pending delivery to a VCPU in the Virtual APIC page, using 
TDH.VP.RD to read the VCPU_STATE_DETAILS TDVPS field.  
The typical use case is when the guest TD VCPU indicates to the host VMM, using TDG.VP.VMCALL, that it has no work to 
do and can be halted.  The guest TD is expected to pass an “interrupt blocked” flag.  The guest TD is expected to set this 
flag to 0 if an d only if RFLAGS.IF is 1 or the TDCALL instruction that invokes TDG.VP.VMCALL immediately follows an STI 25 
instruction.  If the “interrupt blocked” flag is 0, the host VMM can determine whether to re -schedule the guest TD VCPU  
based on VCPU_STATE_DETAILS.  
For further details, see the TDVPS definition in the [ TDX Module ABI Spec ]. Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 105 of 153 
Section 2:  Intel TDX Module Architecture Specification  11.9.6.  Cross -TD-VCPU IPI  
To perform a cross -VCPU IPI, the guest TD ILP should request an operation from the host VMM using TDG.VP.VMCALL.  
The VMM would then inject the requested virtual interrupt into the guest TD’s RLPs using the posted interrupt 
mechanism, as described in 11.9.4 above .  This is an untrusted operation; thus, the TD needs to track its completion.  
11.9.7.  Virtual NMI Injection  5 
The host VMM can request the Intel TDX module  to inject a  virtual NMI into a guest TD VCPU  using the TDH.VP.WR  
function , by setting the PEND_NMI TDVPS field to 1.  This can be done only when the VCPU is not active (a VCPU can be 
associated with at most one LP).  Following that, the host VMM can call TDH.VP.ENTER  to run the VCPU; the Intel TDX 
module  will attempt to inject the NMI as soon as possible.  
The host VMM can use TDH.VP.RD  to read PEND_NMI and get the status of virtual NMI injection.  A value of 0 indicates 10 
that virtual NMI has been injected into the guest TD VCPU.  The host VMM also may choose to clear PEND_NMI before it 
is injected.  
11.10.  Virtualization Exception  (#VE) 
Intel SDM, Vol.  3, 24.9.4  Information for VM Exits Due to Instruction Execution  
Intel SDM, Vol. 3, 25.5.6  Virtualization Exceptions  15 
Intel SDM, Vol.  3, 27.2.5  Information for VM Exits Due to Instruction Execution  
The Intel TDX module  extends the VMX architectural definition  of #VE.  It injects #VE into the guest TD in multiple cases 
where an operation is not allowed by TDX, but an architectural exception (e.g., #GP(0)) is not applicable.  Such cases 
include disallowed instruction executions, disallowed MSR accesses, many CPUID leaves, etc.  
The intended usage is for the TDX -enlightened guest TD OS to have a #VE handler.  By analyzing the #VE information, the 20 
handler would be able to emulate  the requested operation for non -enlightened parts of the guest TD – e.g.,  drivers and 
applications.  
11.10.1.  Virtualization Exception Information  
The virtualization -exception information area  (VE_INFO) is maintained as part of TDVPS .  It is not intended to be directly 
accessible by the guest TD.   Instead, the  #VE information can be retrieved using the TDG.VP.VEINFO.GET  function  (see 25 
the [ TDX Module ABI Spec ]).  This is a simple way to help ensure  the availability and privacy of this area.  
Table 11.9:  Virtualization Exception Information Area (VE_INFO) , based on [Intel SDM, Vol. 3, Table 2 4-1] 
Section  Field  Offset 
(Bytes)  Size 
(Bytes)  Description  
Architectural  EXIT_REASON  0  4 The value that would have been saved into the VMCS as an exit 
reason if a VM exit had occurred  instead of the virtualization 
exception . 
VALID  4  4 0 indicates that VE_INFO has no valid contents.  
The CPU and the Intel TDX module  will not update VE_INFO if 
VALID is not 0.  
After updating VE_INFO, the CPU and the Intel TDX module  
write 0xFFFFFFFF to the VALID field.  
EXIT_  
QUALIFICATION  8  8 The value that would have been saved into the VMCS as an exit 
qualification if a VM exit  had occurred instead of the 
virtualization exception . 
GLA  16  8 The value that would have been saved into the VMCS as a 
guest -linear address if a VM exit  had occurred instead of the 
GPA  24  8 The value that would have been saved into the VMCS as a 
guest -physical address if a VM  exit had occurred instead of the 
virtualization exception . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 106 of 153 
Section 2:  Intel TDX Module Architecture Specification  Section  Field  Offset 
EPTP_INDEX  32  2 The current value of the EPTP index VM -execution control  
Non -
Architectural  
(EXIT_REASON is 
not EPT 
Violation)  INSTR UCTION_  
LENGTH  Non -
arch.  4 The 32 -bit value that would have been saved into the VMCS as 
VM-exit instruction length if a legacy VM exit had occurred 
instead of the virtualization exception.  
INSTR UCTION_  
INFORMATION  Non -
VM-exit instruction information  if a legacy VM exit had occurred 
 
The architectural section format for VE_INFO is as defined in the [Intel SDM], and it is used directly by the CPU when it 
injects a #VE (see 11.10.2 below ).  VE_INFO can also be used for #VE injected by the Intel TDX module .  Some VE_INFO 
fields are applicable only for some exit reasons.  
VE_INFO’s non -architectural section is only applicable for TDX -extended #VE (injected by the TDX module), where 5 
EXIT_REASON is not EPT violation  (48).  It should be ignored for EPT violations converted by the CPU to #VE.  See below 
VE_INFO.VALID  is initialized to 0, and it is set to 0xFFFFFFFF when a #VE is injected to the guest TD.   When handling a 
#VE, the guest TD retrieve s the #VE information using the TDG.VP.VEINFO.GET  function (see the [ TDX Module ABI Spec ]).  
TDG.VP.VEINFO.GET  checks  that VE_INFO.VALID is  0xFFFFFFFF .  After reading the information, it sets VE_INFO.VALID  to 10 
0. 
11.10.2.  #VE Inject ion by the CPU due to EPT Violations  
EPT Violation mutation to #VE is enabled unconditionally for SEAM  non-root operation.  The Intel TDX module  sets the 
TD VMCS EPT-violation #VE  VM-execution control to 1.  
For shared memory accesses (i.e., when GPA.SHARED  == 1), as with legacy VMX, the VMM  can choose which pages are 15 
eligible for #VE mutation based on the value of the Shared EPTE bit 63.  
For private memory accesses (GPA.SHARED  == 0), an EPT Violation causes a TD Exit  in most cases, except when the Secure

0. 
For private memory accesses (GPA.SHARED  == 0), an EPT Violation causes a TD Exit  in most cases, except when the Secure 
EPT entry state is PENDING  (an exception to this is described in 11.11.1 below ).  If ATTRIBUTES.SEPT_VE_DISABLE is 0, 
the Intel TDX module sets the Secure EPT entry’s Suppress VE bit (63) to 0 if the entry’s state is PENDING .  It sets that bit 
to 1 for all other entry states.  20 
11.10.3.  #VE Injected by the Intel TDX Module  
#VE may be injected by the Intel TDX module in several cases:  
• Emulation of the architectural #VE injection on EPT violation, done by a guest -side Intel TDX module flow that 
performs an EPT walk.  
• As a result of guest TD execution of a disallowed instruction (see 11.4 above ), a disallowed MSR access (see 11.7 25 
above ), or CPUID virtualization (see 11.8 above ). 
• A notification to the guest TD about anomalous behavior (e.g., too many EPT violations reported on the same TD 
VCPU instruction without making progress).  This kind of #VE is raised only if the guest TD enabled the specific 
notification (using TDG.VM.WR to  write the TDCS.NOTIFY_ENABLES field) and when a #VE can be injected.  See 17.3  
for details.  30 
If, when attempting to inject a #VE, the Intel TDX module discovers that the guest TD has not yet retrieved the information 
for a previous #VE (i.e., VE_INFO.VALID is not 0), the TDX module injects a #DF into the guest TD to indicate a #VE overrun.  
11.11.  GPA Space, Secure and Shared Extended Page Tables  (EPTs)  
EPT is enabled in SEAM  non-root mode .  SEAM  non-root mode uses two EPTs:  Secure EPT  and Shared EPT.  
EPT level is the same for both Secure and Shared EPT.  If the guest TD’s GPA width is greater than  48 bits (TDCS. GPAW  is 35 
1), then 5-level EPT trees  are used .  Otherwise, 4 -level EPT trees can be  used.  
For further Secure EPT details, refer to Chapter  9. Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 107 of 153 
Section 2:  Intel TDX Module Architecture Specification  EPT violations and misconfigurations generally cause a TD Exit , except for the cases described below.  
11.11.1.  GPAW -Relate EPT Violations  
GPA bits higher than the SHARED bit are considered reserved and must be 0 .  Address translation with any of the reserved 
bits set to 1 cause a #PF with PFEC (Page Fault Error Code) RSVD bit set . 
11.11.2.  EPT Violation Mutated into #VE  5 
An EPT violation is converted into #VE in the following cases:  
• For Secure EPT, if the EPT entry state is PENDING . 
• For Shared EPT, if the EPT entry has been configured by host VMM  deliver EPT violations to the guest TD as #VE 
exception s for usages such as MMIO, as described in 11.10 above . 
11.12.  Prevention  of TD -Induced Denial of Service  10 
VMs, including TDs, can exploit Intel ISA characteristics to cause performance and functional Denial of Service (DOS) to 
the VMM.  The Intel architecture has several mechanisms that help prevent such DOS cases.  This section describes how 
those mechanisms are used in the context of TDX.  
11.12.1.  Bus Lock Detection by the TD OS  
The guest  TD OS can enable debug exception traps due to bus locks by setting IA32_DEBUGCTL.BUS_LOCK_DETECT bit  15 
(2), which is disabled by default.   When enabled, the feature works identically to how it functions in legacy VMX non -root 
mode or in non -VMX mode.  The IA32_DEBUGCTL MSR and DR6 are part of the state that is saved and restored on VM 
exit and VM entry , respectively.  If the delivery of #DB was pre -empted by a trap -like VM exit , then the pending debug 
exceptions  (including due to BUS_LOCK_DETECT if pending ) are saved in TD VMCS and restored on subsequent VM Entry.  
For fault -like VM Exit due to conditions su ch as EPT violation and EPT misconfiguration that are encountered during 20 
execution of an instruction, there is no pending debug exception recorded, including the bus lock debug exception.  
11.12.2.  Impact of MSR_ MEMORY _CTRL (MSR 0x33)  
The host VMM can set bits in MSR_ MEMORY _CTRL (MSR 0x33 , formerly named MSR_TEST_CTRL ) to cause exceptions in 
VMs (including TDs) in case of bus locks:  
• Bit 28 (UC_LOCK_DISABLE):  If this bit is set to 1, a UC load lock will trigger a fault which depends on the CPU:  25 
o Older CPUs will generate a #GP(0) fault.   This is enumerated by IA32_CORE_CAPABILITIES[4] value of 1 and 
CPUID(7,2).EDX[6] value of 0.  
o Newer CPUs will generate an #AC(0)  fault.   This is enumerated by IA32_CORE_CAPABILITIES[4] value of 0 and 
CPUID(7,2).EDX[6] value of 1.  
• Bit 29 (SPLIT_LOCK_DISABLE ):  If set to 1, a split lock will trigger an #AC fault.  30 
MSR 0x33 is not virtualizable; it is a core -scope MSR and may be modified by the host VMM on one SMT thread while 
another SMT thread is running a TD VCPU.  The TDX module does not allow a guest TD to access this MSR (a #VE is 
generated).  
To avoid any security issues, a correctly written TD OS should always b e ready to handle #AC and #GP(0) faults  if the TD 
software might cause UC locks or split locks.  35 
11.12.3.  Bus Lock TD E xit 
Bus lock TD exit is disabled by default.  The host VMM can enable the TD VMCS “bus -lock detection” VM execution control 
using the TDH.VP.WR function . 
Bus Lock VM Exit Reason (74)  
If “bus -lock detection” is enabled, then if the processor detects that one or more bus locks were caused by the instruction 40 
that was executed , then  the processor generates a bus lock  VM exit (exit reason 74).  This VM exit is trap -like, i.e., it is 
delivered following  the execution of that instruction  that caused it .  The Intel TDX module  then completes a TD exit  with 
the exit information provided in the VM exit.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 108 of 153 
Section 2:  Intel TDX Module Architecture Specification  Bus Lock Detected Bit (26) in VM Exit Reason  
If delivery of bus lock  VM exit was pre -empted by a higher priority VM exit (e.g., EPT Misconfiguration, EPT Violation, 
etc.) , then the procession sets a “bus lock detected” notification bit (bit 26) in the exit reason.  The Intel TDX module  
reflects t his bit to the host VMM on TD exit.  
11.12.4.  Instruction Timeout  TD Exit 5 
Instruction Timeout  TD exit  is disabled by default.  The host VMM can write the TD VCMS “ Instruction Timeout Control ” 
and “ Instruction Timeout ” execution controls using the TDH.VP.WR  function .  If enabled and configured, then if the 
processor detects a no -commit case, the processor causes a notification VM exit (exit reason 75) which the Intel TDX 
module  converts to the TD exit.  
The conditions that cause an instruction timeout  TD exit are the same as those in legacy VMX non -root mode.  An example 10 
of such a case is the nested #AC exception.  If an #AC exception occurs during the delivery of a previous #AC exception, 
then the CPU may get into an endless loop of #AC without responding to external events.  
Bit 0 (VM context invalid) of the exit qualification indicates whether the guest TD context is corrupted and not valid in 
the TD VMCS .  If this bit is set to 1, then it is a non -recoverable situation; thus , the Intel TDX module  marks the  TD as 
disabled to help  prevent further TD entry .  If no TD context corruption occurred  (exit qualification bit 0 is cleared to 0) , 15 
then the TD may be resumed normally.  
11.13.  Time Stamp Counter  (TSC)  
Intel SDM, Vol. 3, 18.17  Time -Stamp Counter  
Intel SDM, Vol. 3, 24.6.5  Time -Stamp Counter Offset and Multiplier  20 
Intel SDM, Vol. 3, 25.3  Changes to Instruction Behavior in VMX Non -Root Operation  
11.13.1.  TSC Virtualization  
For virtual time stamp counter (TSC) values read by guest TDs, the Intel TDX module  is designed to achieve  the following:  
• Virtual TSC values are consistent among all the TD’s VCPUs at the level supported by the CPU, see below.  
• The virtual TSC value for any single VCPU is monotonously incrementing (except roll over from 264-1 to 0).  25 
• The virtual TSC frequency is determined by TD configuration.  
The host VMM is required to do the following:  
• Set up the same IA32_TSC_ADJUST values on all LPs before initializing the Intel TDX module . 
• Make sure IA32_TSC_ADJUST is not modified from its initial value before calling SEAMCALL.  
The Intel TDX module  checks  the above as part of TDH.VP.ENTER  and any other SEAMCALL leaf function that reads TSC.  30 
The virtualized TSC is designed to have the following characteristics:  
• The virtual TSC frequency is specified by the host VMM as an input to TDH.MNG.INIT  in units of 25MHz – it can be 
between 4 and 400 (corresponding to a range of 100MHz  to 10GHz).  
• The virtual TSC starts counting from 0 at TDH.MNG.INIT  time.  
• TSC parameters are enumerated to the guest TD by CPUID(0x15).   35 
• Guest TDs are not allowed to modify the TSC.  WRMSR attempts of IA32_TIME_STAMP_COUNTER result in a #VE.

• Guest TDs are not allowed to modify the TSC.  WRMSR attempts of IA32_TIME_STAMP_COUNTER result in a #VE.  
• Guest TDs are not allowed to access IA32_TSC_ADJUST because its value is meaningless to them.  WRMSR or RDMSR 
attempts result in a #VE.  
• RDTSCP is supported.  This instruction returns the contents of the IA32_TSC_AUX MSR in RCX.  the Intel TDX module  
allows the guest TD to access that MSR and context -switches it on TD entry and exit as part of the VCPU state in 40 
TDVPS.  
11.13.2.  TSC Deadline  
Guest TDs are not allowed to access the IA32_TSC_DEADLINE MSR directly.  Virtualization of IA32_TSC_DEADLINE 
depends on the virtual value of CPUID(1).EXC[24] bit (TSC Deadline).  The host VMM may configure (as an input to 
TDH.MNG.INIT) virtual CPUID(1).EXC[24] to be a constant 0 or allow it to be 1  if the CPU’s native value is 1 . 45 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 109 of 153 
Section 2:  Intel TDX Module Architecture Specification  • If the virtual value of CPUID(1).EXC[24] is 0, IA32_TSC_DEADLINE is virtualized as non -existent.  WRMSR or RDMSR 
attempts result in a #GP(0).  
• If the virtual value of CPUID(1).EXC[24] is 1, WRMSR or RDMSR attempts result in a #VE.  This enables the TD’s #VE 
handler to para -virtualize the TSC deadline functionality, e.g., by requesting an (untrusted) service from the host 
VMM.  5 
11.14.  Supervisor Protection Keys (PKS)  
By design, g uest TD usage of Supervisor Protection Keys (PKS) is controlled by the ATTRIBUTES.PKS bit (see the [ TDX 
Module ABI Spec ]).  When PKS is supported by the CPU and ATTRIBUTES.PKS is set to 1, the following features are 
available to the guest TD:  
• CPUID virtualization enumerates PKS availability to the guest TD.  10 
• Guest TDs may enable PKS by setting CR4. PKS flag.  
• Guest TDs may access the PKS state  using the IA32_PKRS MSR.  
Note:  Enumeration of User Mode Protection Keys (PKU) availability to the guest TD is configured as part of the 
configuration of virtual CPUID(7,0).ECX[3].  
11.15.  Intel ® Total Memory Encryption ( Intel ® TME) and Multi -Key Total Memory Encryption 15 
(MKTME)  
supports para -virtualiz ation of this ISA , as described below.  
11.15.1.  TME Virtualization  
TME is enumerated by CPUID(0x7, 0x0).ECX[13] .  The host VMM can configure the virtualization of this bit as enabled or 20 
disabled on TDH.MNG.INIT .  If enabled, then a guest TD access to the IA32_TME_* MSRs (0x981 – 0x984) causes  a #VE , 
allowing the guest TD’s #VE handler to emulate the desired operation .  Else, guest TD access to those MSRs causes  a 
#GP(0) . 
11.15.2.  MKTME Virtualization  
MKTME is enumerated by CPUID(0x7, 0x0).EDX[18] .  The host VMM can configure the virtualization of this bit as enabled 25 
or disabled on TDH.MNG.INIT .  If enabled, then the following operations cause a #VE (e.g., the guest TD #VE handler can 
then communicate with the host VMM over TDG.VP.VMCALL  to request the desired operation):  
• Guest TD access to the IA32_MKTME_PARTITIONING MSR (0x87)  
• PCONFIG execution by the guest TD  
If the host VMM configured CPUID(0x7, 0x0).EDX[18]  virtualized value as 0 , then:  30 
• Guest TD access to the IA32_MKTME_PARTITIONING MSR (0x87 ) causes  a #GP(0).  
• PCONFIG execution by the guest TD  causes  a #UD.  
11.16.  Virtualization of Machine Check Capabilities and Controls  
Although the guest TD is not allowed to handle machine check event, the following virtualization is used in order to allow 
possible pare -virtualization behavior, e.g., future handling of MCE by the TD.  35 
• The values of CPUID(1).EDX[7] (MCE) and CPUID(1).EDX[14] (MCA), as seen by the guest TD, are 1.  
• The value of CR4[6] (MCE), as seen by the guest TD, is 1.  Guest TD attempt to set this bit to 0 results in a #VE.  
• Guest TD accesses to MSRs 0x179 (IA32_MCG_CAP), MSRs 0x17A, 0x17B, 0x4D0 (IA32_MCG_*), MSRs 0x281 through 
0x29D  (IA32_MCx_CTL2) and MSRs 0x400 through 0x473 (IA32_MCx_*) result in a #VE.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 110 of 153 
Section 2:  Intel TDX Module Architecture Specification  11.17.  Transactional Synchronization Extensions  (TSX)  
Intel SDM, Vol. 1, 16  Programming with Intel TSX  
The host VMM can enable TSX for a TD by configuring the following CPUID bits as enabled in the TD_PARAMS input to 
TDH.MNG.INIT:  
• CPUID(7,0).EBX[4] (HLE)  5 
• CPUID(7,0).EBX[11] (RTM)  
The virtual values of the above bits, as seen by the guest TD, are the bitwise AND of the real values enumerated by the 
CPU and of the configuration values.  To enable TSX for guest TDs, TDX requires the following conditions to be true:  
• The virtual values of the HLE and the RTM bits are the same, either 0 or 1.  
• The CPU supports the IA32_TSX_CTRL MSR (as enumerated by IA32_ARCH_CAPABILITIES[7]).  10 
Note:  If the real value of the HLE bit and the RTM bit are different, the host VMM must configure both virtual values 
as 0.  
If TSX is enabled for the guest TD:  
• IA32_TSX_CTRL is accessible by the TD.  
• On TD exit : 15 
o IA32_TSX_CTRL is cleared  to 0.  
o On CPUs that support IA32_TSX_STORE_ADDRESS (MSR 0xF3D), as indicated by 
IA32_PERF_CAPABILITIES.TSX_ADDRESS[18] , if the TD’s ATTRIBUTES.PERFMON is 1 then 
IA32_TSX_STORE_ADDRESS is cleared to 0.  
The host VMM is responsible for restoring these MSRs to their desired values, if applicable.  20 
If TSX is disabled for the guest TD:  
• CPUID(7,0).EBX bits 4 and 11 are virtualized as 0.  
• IA32_TSX_CTRL is virtualized as non -existent:  IA32_ARCH_CAPABILITIES bit 7 is virtualized as 0, and TD access results 
in a #GP(0).  
• If IA32_TSX_CTRL is supported by the CPU, then XBEGIN, XEND and XABORT instructions execution by the TD cause 25 
a #UD . 
11.18.  Management of Idle and Blocked Conditions  
11.18.1.  HLT Instruction  
HLT executed by a guest TD results in a #VE.  The TD’s #VE handler may notify the host VMM (using TDG.VP.VMCALL), 30 
which may schedule other software to execute on the current LP.  
11.18.2.  PAUSE Instruction and PAUSE -Loop Exiting  
Guest TDs can execute PAUSE.  However, modern enlightened guests use a VMM -provided service (hypercall) instead of 
PAUSE loops – this is the expected usage for Intel TDX.  35 
For TDs running in debug mode (ATTRIBUTES.DEBUG is 1), the host VMM may set the guest TD’s “PAUSE -loop exiting” 
VM-execution control, using TDH.VP.WR.  
“PAUSE -loop exiting” allows the  VMM to request an exit if the guest (in ring 0) executes PAU SE in a loop (e.g., busy -wait).  
This is intended to help avoid cases where a guest thread loops, waiting for another thread that is not currently scheduled 
by the VMM.   40 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 111 of 153 
Section 2:  Intel TDX Module Architecture Specification  11.18.3.  MONITOR and MWAIT Instructions  
Execution of MONITOR or MWAIT by a guest TD results in a #VE exception.   The TD’s #VE handler may handle this by 
calling some host VMM service (using TDG.VP.VMCALL).  
However, the host VMM may configure the guest TD to allow MONITOR/MWAIT, using the CPUID configuration table 5 
which is part the TD_PARAMS input to TDH.MNG.INIT.  Configuring the virtual value of CPUID(1).ECX[3] to 1 also enable s 
the TD to execute MONITOR and MWAIT.  
11.18.4.  WAITPKG:  TPAUSE, UMONITOR and UMWAIT Instructions  
The host VMM may allow guest TDs to use the TPAUSE, UMONITOR and UMWAIT instructions, if the CPU supports them, 
by configuring the virtual value of CPUID(7,0).ECX[5] (WAITPKG) to 1 using the CPUID configuration table which is part 10 
the TD_PARAMS input to TDH.MNG.INIT.  Enabling CPUID(7,0).ECX[5] also enables TD access to IA32_UMWAIT_CONTROL 
(MSR 0xE1).  
If not allowed, then TD execution of TPAUSE, UMONITOR or UMWAIT results in a #UD, and access to 
IA32_UMWAIT_CONTROL results in a #GP(0).  
11.19.  Other Changes in SEAM  Non -Root Mode  15 
11.19.1.  CET 
Intel SDM, Vol. 1, 17.2.3  Supervisor Shadow Stack Token  
Guest TDs should execute CPUID(7,1) and use the CET_SSS bit value returned in EDX[18] as an indication of whether 
supervisor shadow stack can be enabled.  The TDX module virtualizes CPUID(7,1).EDX[18] as 0 if  certain supervisor 
shadow -stack pushes might cause VM exits , indicating to the guest TD that it should refrain from enabling supervisor 20 
shadow stack .  For details, see the [Intel SDM].  
11.19.2.  Tasking  
Any task switch results in a VM exit to the Intel TDX module  (this is a fixed -1 exit) which then performs a TD exit to the 
host VMM.

host VMM.  
The VMM is expected not to reenter the TD VCPU since this case is non -recoverable; the instruction that caused the task 25 
switch ( CALL, JMP or IRET ) will re -execute and cause another VM exit.  If the task switch was incident al to an exception 
delivery , then the VM  entry  following TDH.VP.ENTER  will reattempt the delivery and cause another task switch VM exit.  
The expected  response from the VMM is to terminate this TD.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 112 of 153 
Section 2:  Intel TDX Module Architecture Specification  12. Measurement and Attestation  
12.1. TD Measurement  
• MRTD  helps  provide s tatic measurement of the TD build process and the initial contents of the TD.  
• RTMR  is an  array of general -purpose measurement registers made available to the TD software to enable  measuring 5 
additional logic and data loaded into the TD at run -time.  
12.1.1.  MRTD:  Build -Time Measurement Register  
The Intel TDX module  measures the TD during the build process .  The measurement register TDCS. MRTD is a SHA384 
digest of the build process, designed  as follows:  10 
• TDH.MNG.INIT  begins the process by initializing the digest.  
• TDH.MEM.PAGE.ADD  adds a TD private page to the TD and inserts its properties  (GPA) into the MRTD digest 
calculation . 
• Control structure pages (TDR, T DCX and TDVPR) and Secure EPT pages are not measured.  
• For pages whose data contribute to the TD, that data should be included in the TD measurement via 15 
TDH.MR.EXTEND .  TDH.MR.EXTEND  inserts the data contained in those pages  and its GPA,  in 256 -byte chunks , into 
the digest calculation.  If a page will be wiped and initialized by TD code, the loader may opt not to measure the 
initial contents of the page with TDH.MR.EXTEND . 
• The measurement is then completed by TDH.MR.FINALIZE .  Once completed, further TDH.MEM.PAGE.ADD s or 
TDEXTENDs will fail.  20 
MRTD extension by GPA uses a 128B buffer which includes the GPA and the leaf function  name for uniqueness.  
12.1.2.  RTMR:  Run -Time Measurement Registers  
The RTMR array is initialized to zero on build, and it can be extended at run -time by the guest TD using the 
TDCALL( TDG.MR.RTMR.EXTEND ) leaf.  The syntax of the RTMR registers is designed to be similar to that of TPM PCRs, 
where a register’s value after TDG.MR.RTMR.EXTEND (index=i, value=x) is:  25 
RTMR[i] = SHA384(RTMR[i] || x);  
Four  RTMR registers are provided.  
Typical expected usage is for TPM emulation during guest TD OS secure boot by the VBIOS.  
12.2. TD Measurement Reporting  
TD attestation is initiated from inside the TD by calling TDG.MR.REPORT  and specifying a REPORTDATA value.  30 
TDG.MR.REPORT  creates a TDREPORT _STRUCT  structure containing the TD measurements, initial configuration of the TD 
that was locked at finalization  (TDH.MR.FINALIZE ), the Intel TDX module  measurements, and the REPORTDATA value.  
TDREPORT _STRUCT  structure and TDG.MR.REPORT  are detailed in  the [ TDX Module ABI Spec ]. 
TDREPORT_STRUCT  is HMAC ’ed using an HMAC key that is designed to be accessible  only  to the CPU.  This helps protect 
the integrity of the structure and , by design, can only be verified on the local platform via the TDG.MR.VERIFYREPORT 35 
interface function or the SGX ENCLU(EVERIFYREPORT2)  instruction .  By design, TDREPORT _STR UCT cannot be verified off 
platform ; it first must be converted into signed Quotes, as described in  12.4 below . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 113 of 153 
TDREPORT_STRUCT
XFAM
MRTD
MRCONFIGID
MROWNER
RTMR0..RTMR3
SERVTD_HASH
LAYERSIGROOT*
LAYERSIGNER*
LAYERPRODID*
MRCONFIGSVN*
MROWNERCONFIGSVN*TDINFO_STRUCTMRSEAM
MRSEAMSIGNER
TEE_TCB_SVNs
ATTRIBUTESTEE_TCB_INFO
REPORTTYPE(TDX)
CPUSVN
TEE_TCB_INFO_HASH
TD_INFO_HASH
REPORTDATA
MACREPORTMAC STRUCTSHA384
SHA384Quote
*Only for TDINFO2_STRUCT, if supported by the TDX Module
 
Figure 12.1:  TD Measurement Reporting  
The REPORTYPE field of REPORTMACSTRUCT indicates that this is a TDX report (TYPE  == 0x81) and whether 
SERVTD_HASH contains a valid hash of service TDs (VERSION  == 1) or 0 (VERSION  == 0).  For details, see Ch. 13 and the 
[ABI Spec].  5 
12.3. Local Report Verification  
A TD can verify a report generated by another TD on the same platform using the TDG.MR.VERIFYREPORT interface 
function.  Internally, TDG.MR.VERIFYREPORT executes the SEAMVERIFYREPORT instruction, which uses the same HMAC 
key, accessible only to the CPU, th at was used for generating TDREPORT_STRUCT.  
Reporting Trust Domain
 Verifying Trust Domain
CPUMAC Key
Intel TDX
Module
SEAMDB_REPORT
SEAM 
+ TD Info)
TDCS
SEAM 
REPORT
(MACed)
+ TD Info)
TDG.MR.VERIFYREPORT 
Function
SEAMVERIFYREPORT
InstructionREPORTMAC
STRUCT
 10 
Figure 12.2:  High -Level View of Local Report Verification  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 114 of 153 
Section 2:  Intel TDX Module Architecture Specification  Local Report Verification Failure  
Local report verification may fail i n cases where the MAC key , held by the CPU , has changed between the generation of 
the TDREPORT by TDG.MR.REPORT and its verification by TDG.MR.VERIFYREPORT.  Some examples are:  
• After report generation by TDG.MR.REPORT, both the reporting TD and the verifying TD have been migrated to a 
different platform.   Both TDs are not directly aware of the migration.  5 
• After report generation by TDG.MR.REPORT, either the CPU microcode has been updated or the TDX module has 
been updated using the TD -preserving update process.  Both TDs are not directly aware of the TDX module update.  
To account for the above cases, the following  is recommended in case of local report verification failure .  The verifying 
TD should  ask for a fresh report to be generated.  T he reporting TD should then g enerate a  new report , using 
TDG.MR.REPORT, and send it to the verifying TD to be verified  using  TDG.MR.VERIFYREPORT .  This can be repeated  10 
several times (e.g., 3 – 5 times)  and/or coordinated with the host VMM.  
12.4. Creating Attestations  
12.4.1.  Overview  
To create a remotely verifiable attestation, the TDREPORT_STRUCT  should  be converted into a Quote signed by a certified 
Quote signing key.   The following models are supported from creating a Quote:  15 
• Platforms that support Intel SGX can support Quoting Enclaves producing either TDX or SGX Quotes.  A TD Quoting 
Enclave, when available, will produce legacy quotes for TDX.  
12.4.2.  Intel SGX-Based Attestation  
The Intel SGX attestation architecture is designed to provide facilities for multiple Quoting Enclaves from multiple 
providers.  This is intended to allow the host to instantiate a Quoting Enclave for Intel SGX attestations and another 20 
Quoting Enclave for TD attestation without interference  — i.e., each provider can supply its own quoting enclave, and 
the quoting enclave for Intel SGX and for Intel TDX may be separate; the design does not require the quoting enclave to 
run inside the TD.  
Host VMM
CPU
MAC Key
Quote
(Signed)
Intel TDX
Module
SEAM 
+ TD Info)
TDCS
SEAM 
REPORT
(MACed)
+ TD Info)
 
Figure 12.3:  High -Level View of the Intel SGX-Based TD Attestation  25 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 115 of 153 
Section 2:  Intel TDX Module Architecture Specification  Quote generation using a quoting enclave is typically performed as follows:  
1. Guest TD invokes the TDCALL (TDG.MR.REPORT ) function . 
2. The TDX module uses the SEAMOPS(SEAMDB_REPORT) instruction to create MAC ’ed TDREPORT_STRUCT  with the 
Intel TDX module measurements from CPU and TD measurements from TDCS.  
3. Guest TD uses TDCALL( TDG.VP.VMCALL ) to request that TDREPORT_STRUCT  be converted into Quote.  5 
4. The TD Quoting enclave uses EVERIFYREPORT 2 to check  the TDREPORT_STRUCT .  This allows the Quoting Enclave to 
check  the report without requiring direct access to the CPU’s HMAC key.  Once the integrity of the 
TDREPORT_STRUCT  has been verified, the TD Quoting Enclave signs the TDREPORT_STRUCT  body with an ECDSA 384 
signing key.  
EVERIFYREPORT Failure  10 
Report verification may fail is cases where the MAC key, held by the CPU, has changed between the generation of the

Report verification may fail is cases where the MAC key, held by the CPU, has changed between the generation of the 
TDREPORT by TDG.MR.REPORT and its verification by EVERIFYREPORT.  Some examples are:  
• After report generation by TDG.MR.REPORT, the reporting TD has been migrated to a different platform.  The 
reporting TD is not directly aware of the migration.  
• After report generation by TDG.MR.REPORT, either the CPU microcode has been updated or the TDX module has 15 
been updated using the TD -preserving update process.  The reporting TD is not directly aware of the TDX module 
update.  
To account for the above cases, the following is recommended in case of report verification failure.  The Quoting Enclave 
should ask for a fresh report to be generated.  The reporting TD should then generate a new report, using 
TDG.MR.REPORT, and send it to the Quoting Enclave to be  verif ied using EVERIFYREPORT.  This can be repeated several 20 
times (e.g., 3 – 5 times) and/or coordinated with the host VMM.  
 Quote Signing Key  for SGX -Based Attestation  
The Intel SGX infrastructure provides primitives and a certificate infrastructure to allow Quoting Enclaves to certify their 
own Quoting Key s.  The Intel SGX Provisioning Certification Enclave (PCE) uses  an Intel -Certified ECDSA -256 signing key 
to issue certificates to Quoting Enclaves for their attestation keys.  Intel offers a service to allow third  parties to download 25 
these certificates.  
Typically, o n first launch, the TD Quoting Enclave generates a random ECDSA 384-bit quoting key.   It then contacts the 
Provisioning Certification Enclave which uses its signing key to sign the new quoting key’s public key.  
Note that the TD Quoting Enclave uses an ECDSA 384 bit key, while the PCE certifies it with an ECDSA -256 key.  This is 
due to limitations of the SPR platform.  30 
12.5. TCB Recovery  
The Intel TDX architecture has several levels of TCB:  
• CPU HW level, which includes microcode patch, ACMs and PFAT  
• Intel TDX module  software  
• Attestation Enclaves which include the TD Quoting Enclave and Provisioning Certification Enclave  35 
The TCB Recovery story is different for each level.  The existing SGX TCB Recovery model for CPU level items applies in 
the same way with TDX and SGX.  The model requires a restart of the platform to take effect.   The Intel TDX module  can 
be unloaded and reloaded to reflect an upgraded Intel TDX module .  The enclaves can be upgraded at run -time, but if the 
PCE is upgraded, the design requires a new certificate to be downloaded . 
12.5.1.  TD Preserving TDX Module Update Implications  40 
TEE_TCB_INFO fields TEE_TCB_SVN and MRSEAM reflect the TDX module at the time of TD creation.   
TEE_TCB_INFO.TEE_TCB_SVN2 reflects the current TDX module at the time TDG.MR.REPORT is called.  
The underlying assumption s are:  
• TD preserving update can only happen to a more secure TDX module.  
• Microcode updates can only happen to a more secure microcode.  45 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 116 of 153 
Section 2:  Intel TDX Module Architecture Specification  13. Service TDs 
13.1. Overview  
One or  more  service TD s may be  bound to a target TD .  Service TD binding relationship has the following characteristics:  
• A service TD has a type  (SERVTD_TYPE) . 
• A service TD may read and/or write certain target TD metadata .  Access permission to target TD metadata fields 5 
depends on SERVTD_TYPE . 
• Unsolicited service TD binding  is done without target TD approval.   The target TD needs not be aware of the binding.  
o Binding  10 
• Service TD to target TD binding relationship is many -to-many  
• A service TD may itself be a target TD to other service TDs.  15 
Typical Unsolicited Service TD Binding and Metadata Access Use Case  
1. Optional Pre -Binding:   During target TD build, before calling TDH.MR.FINALIZE, the host VMM calls 
TDH. SERVTD.PREBIND  to write the binding fields (SERVTD_HASH etc.) in the target TD’s service TD table.  
2. Binding:   Sometime later, the host VMM calls TDH.SERVTD.BIND to bind the service TD.  It gets back a binding handle.   
The VMM communicates the binding handle, target TD_UUID and other binding parameters to the service TD.  20 
3. Metadata Access:   The service TD uses TDG.SERVTD.RD/WR * to access target TD metadata.  
4. Rebinding:   May be required due to, e.g. ,  both target TD and service TD have been migrated  or a new service TD 
instance replaces the original one .  The host VMM calls  TDH.SERVTD.BIND to rebind the service TD.  It gets back a 
binding handle.   The VMM communicates the binding handle, target TD_UUID and other binding parameters to the 
service TD.  25 
13.2. Service TD Binding  
(per SERVTD_ATTR)]TDH.SERVTD.BINDTDH.SERVTD.PREBIND
[OP_STATE in 
{UNINITIALIZED, INITIALIZED}]
 
Figure 13.1:  Service TD Binding State Machine  
13.2.1.  Service TD Binding Table in the Target TD’s TDCS  
The target TD’s TDCS holds a service TD binding table.  Each row (binding slot) in the table contains the following fields, 30 
which are detailed in the following sections:  
• SERVTD_BINDING_STATE  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 117 of 153 
Section 2:  Intel TDX Module Architecture Specification  • SERVTD_INFO_HASH  
• SERVTD_TYPE  
• SERVTD_ATTR  
• SERVTD_UUID  
The available number of slots in the table is enumerated by TDH.SYS.RD*.  5 
13.2.2.  SERVTD_BINDING_STATE :  Service TD Binding State  
SERVTD_BINDING_STATE  indicates the state of the service TD binding slot.  It has the following values:  
Table 13.1:  SERVTD_BINDING_STATE  Definition  
Value  Name  Meaning  
0 NOT_BOUND  No service TD is bound .  The binding fields in this slot are N/A . 
1 PRE_BOUND  No service TD is bound.  SERVTD_INFO_HASH , SERVTD_TYPE and SERVTD_ATTR have 
been set.  They will be included in SERVTD_HASH calculation and be checked on any 
following binding.  
2 BOUND  A service TD is bound.  SERVTD_UUID, SERVTD_INFO_HASH , SERVTD_TYPE and 
SERVTD_ATTR have been set and be checked on any following binding.  
SERVTD_INFO_HASH , SERVTD_TYPE will be included in SERVTD_HASH calculation 
and be checked on any following binding.  
 
13.2.3.  SERVTD_TYPE:  Service TD Binding Type  10 
A service TD implements one or more SERVTD_TYPEs .  A specific SERVTD_TYPE is specified per binding; the same service 
TD may be bound multiple times if it implements more than one SERVTD_TYPE.  
SERVTD_TYPE controls the following:  
• The target TD metadata fields that the service TD may read and/or write.  
• Whether or not multiple bindings of this SERVTD_TYPE can exist at the same time for a specific target TD.  15 
SERVTD_TYPE values supported by the TDX module are defined in the [ TDX Module ABI Spec ]. 
13.2.4.  SERVTD_ATTR:  Service TD Binding Attributes  
SERVTD_ATTR is a set of service TD binding attributes.  It includes the following fields:  
Unsolicited Binding (SOLICITED_BINDING == 0)  
With unsolicited binding , service TD binding is done without target TD awareness , but is reflected in the target TD’s 20 
TDREPORT . 
 INSTANCE_BINDING:  Class vs. Instance Binding  
Specifies whether a specific Service TD instance or a class of a service TD is bound.  
Class Binding (INSTANCE_BINDING == 0)  
With class binding , rebinding can be done with any TD with the same SERVTD_INFO_HASH , SERVTD_TYPE and 25 
SERVTD_ATTR as the original binding.  Those parameters are migrated  when the target TD is migrated.   SERVTD_UUID  is 
not checked; it is updated by rebinding.  
Instance Binding (INSTANCE_BINDING == 1)  
With instance binding , rebinding can be done with the same TD instance (same SERVTD_UUID) .  SERVTD_INFO_HASH , 
SERVTD_TYPE and SERVTD_ATTR must also be the same as the original binding . 30 
 MIGRATABLE_BINDING:  Binding  Migratability  
Specifies whether a service TD binding can be migrated.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 118 of 153 
Section 2:  Intel TDX Module Architecture Specification  Non -Migratable Binding (MIGRATABLE_BINDING == 0)  
With non -migratable binding, only some of the  binding state of the service TD is migrated.  A different service TD may be 
bound at the destination platform, subject to the conditions described below . 
SERVTD_BINDING_STATE , SERVTD_TYPE  and SERVTD_ATTR are exported  as part of  the TD’s mutable state.  
When importing the target TD’s mutable state  to the destination platform : 5

When importing the target TD’s mutable state  to the destination platform : 5 
1. If the imported SERVTD_BINDING_STATE is NOT_BOUND, then the other imported service TD fields ( SERVTD_TYPE , 
SERVTD_TYPE and SERVTD_ATTR ) are ignored.  
2. Else (imported SERVTD_BINDING_STATE is PRE_BOUND or BOUND) : 
2.1. If there is already a PRE_ BOUND or BOUND service TD at this binding slot , then the SERVTD_TYPE and 
SERVTD_ATTR must match.  The other imported fields for that binding slot are ignored.  10 
If SERVTD_TYPE or SERVTD_ATTR don’t match, import fails.  
Note:   This is the case used for  Migration TD . 
In all cases, if the imported SERVTD_TYPE allows only a single instance of that type , no other service TD slot may have a 
PRE_BOUND or BOUND service TD of the same SERVTD_TYPE.  
 IGNORE_TDINFO:  TDINFO Component Filtering  15 
IGNORE_TDINFO is a  bit array which determine s which component of the service TD’s TDINFO_STRUCT field is included 
in the calculation of SERVTD_INFO_HASH .  For details see 13.2.6 below . 
13.2.5.  SERVTD_UUID:  Service TD Instance Identifier  
TD_UUID is a 256 -bit random number that serves as a universally unique identifier of a TD.  TD_UUID is created by 
TDH.MNG.CREATE and is stored in the TD’s TDR.  When a service TD is bound to a target TD, its TD_UUID is stored in the 20 
target TD’s service TD table slot’s SERVTD_UUID field.  
13.2.6.  Service TD’s Binding SERVTD_INFO_HASH  Calculation  
For the purpose of service TD binding, a SHA384 hash of the service TD’s measurable attribute is calculated in a similar 
way to the calculation done by TDG.MR.REPORT (see 12.2 ), except that filtering is applies based on the binding 
SERVTD_ATTR:  25 
• The SERVTD_ATTR.IGNORE_TDINFO selects which TDINFO_STRUCT field is ignored (a value of 0 is used in the 
calculation).  
XFAM
MRTD
MROWNER
RTMR0
RTMR1
RTMR2
RTMR3
SERVTD_HASHService TD’s 
TDINFO_STRUCT
SHA384Slot SERVTD_
BINDING _
STATESERVTD_
INFO _
HASHSERVTD_
TYPESERVTD_
ATTR
0
1
…
N-1Service TD Binding Table in Target TD’s TDCSFilter by 
SERVTD_ATTR.
IGNORE_TDINFO
Filter by 
PLATFORM_
BINDING
 
Figure 13.2:  SERVTD_INFO_HASH  Calculation  
13.2.7.  Target TD’s SERVTD_HASH Calculation  30 
SERVTD_HASH is a single field that summarizes all the service TDs bound or pre -bound to the target TD  in an unsolicited 
mode.  SERVTD_HASH is calculated on TD build and on TD import.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 119 of 153 
 SERVTD_HASH Calculation o n Finalization of TD Build  
On TD build,  SERVTD_HASH is calculated by TDH.MR.FINALIZE.  At that time, the binding information for all bound or pre -
bound service TDs is known.  
 SERVTD_HASH Calculation on TD Import  
On TD import , SERVTD_HASH  is recalculated by TDH.IMPORT.STATE.IMMUTABLE.  In case of non -migratable service TD 5 
binding, the imported binding information is checked but does not replace the existing binding information.  E.g., the 
Migration TD bound on the source platform may have a different INFO_HASH than that of the Migration TD bound on 
the destination platform.   The recalculated SERVTD_HASH reflects the service TDs bound on the destination platform.  
The reason for this recalculation is to narrow down the TCB for the migrated TD attestation.  E.g., suppose the Migration 
TD on either or both sides are malicious and can forge any migration information.  Even in this case the target TD’s 10 
attestation is based on information collected by the TDX module.  It is independent on any TD and reflects the true 
identity of the service TDs bound to the target TD.  
 SERVTD_HASH Calculation Method  
SERVTD_HASH is calculated as follows:  
1. Get all service TD binding slots whose SERVTD_BINDING_STATE is not NOT_BOUND.  15 
2. Sort by SERVTD_TYPE  as the primary key, SERVTD_INFO_HASH as a secondary key ( if multiple service TDs of the same 
type are bound ). 
3. Concatenate SERVTD_INFO_HASH, SERVTD_TYPE and SERVTD_ATTR of each slot  
4. Concatenate all slots.  
5. Calculate SHA384.  20 
Slot SERVTD_
BINDING _
INFO _
ATTR
0
1
…
N-1Sort by 
SERVTD_
TYPESHA384ATTRIBUTES
XFAM
MRTD
MROWNER
RTMR0
RTMR1
RTMR2
RTMR3
SERVTD_HASHTarget TD’s 
Service TDs Binding Table in Target TD’s TDCS
 
Figure 13.3:  SERVTD_HASH Calculation  
13.2.8.  TDH.SERVTD. PREBIND:  Pre-Binding  a Service TD  
TDH.SERVTD.BIND is used by the host VMM to bind a service TD.  It is detailed in the [ TDX Module ABI Spec ]. 
Inputs  25 
• Target TD’s TDR HPA  
• SERVTD_INFO_HASH  
• Service TD Index (slot number  in the target TD’s binding table)  30 
Operation  
• Check that the target TD’s measurements have not been finalized (by TDH.MR.FINALIZE).  
• Check that no service TD is already bound in the given slot number . 
• Store the service TD’s SERVTD_INFO_HASH , SERVTD_TYPE  and SERVTD_ATTR . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 120 of 153 
Section 2:  Intel TDX Module Architecture Specification  13.2.9.  TDH.SERVTD.BIND:  Binding a Service TD  
TDH.SERVTD.BIND is used by the host VMM to bind a service TD.   It is detailed in  the [ TDX Module ABI Spec ]. 
Binding Scenarios  
Initial Binding:  No pre -binding has been done;  initial  service TD binding can only be done before TDH.MR.FINALIZE 
of the target TD . 5 
Late Initial Binding:  Pre-binding has been done ;  initial service TD binding can be done at any time.  
SERVTD_INFO_HASH  and SERVTD_ATTR must match.  
Rebinding:  Binding has been done;  r ebinding conditions depend on SERVTD_ATTR as described before . 
Inputs  
• Target TD’s TDR HPA  10 
• Service TD’s TDR HPA  – NULL_PA ( -1) if pre -binding is requested  
• Service TD Index (slot number  in the target TD’s binding table)  
Outputs  15 
• Binding Handle  (described below)  
Operation  
• Calculate the service TD’s SERVTD_INFO_HASH . 
• Check binding conditions vs. the target TD’s binding table . 
• Store the service TD’s SERVTD_INFO_HASH , SERVTD_TYPE, SERVTD_ATTR and SERVTD_UUID in the target TD’s 20 
binding table . 
• Calculate the binding handle as f(service TD’s TD_UUID, target TD’s TDR HPA, slot number ). 
13.2.10.  Binding Handle  
The binding handle is used as a shortcut , to quickly identify both the target TD and the binding slot .  It should be noted 
that the t arget TD identity is verified by its TD_UUID ; the binding handle does not replace it .  The binding handle is not a 25 
secret . 
The binding h andle is calculated from  the following variables , using a simple addition:  
• Least significant 64 bits of SERV TD_UUID  – this serves to obfuscate the handle,  so the service TD does not use HPA 
or slot number directly.  
• Target TD’s TDR HPA ( platform -specific unique identifier of the target TD)  30 
• Target TD’s binding slot number  
Given the handle, the TDX module can reconstruct TDR_HPA and binding slot number . 
The binding handle is platform -specific and must be recreated after migration.  This may be triggered when the service 
TD attempts to access target TD metadata using TDG.SERVTD.RD/WR* and an error is returned.  
13.3. Target TD Metadata Access by a Service TD  35 
13.3.1.  TDG.SERVTD.RD/WR:  Metadata Read/Write Interface Functions  
TDG.SERVTD.RD  and TDG.SERVTD.WR  are similar to other  metadata access functions, e.g.:  
• Host -side:  TDH.MNG.RD/WR  
• Guest -side:  TDG.VM.RD/WR  
Refer to 18.6  for a description of the TDX module metadata interface.  40 
Inputs  
• Target TD_UUID, uniquely identifying the target TD  
• Binding handle , identifies the binding slot and a shortcut for identifying the target TD  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 121 of 153 
Section 2:  Intel TDX Module Architecture Specification  • A single metadata field ID or metadata field list 
Output  
• For a single field access:  Field value  
Operation  
1. Calculate the target TD’s TDR HPA and binding slot number  from the binding handle . 5 
2. Check that the target TD_UUID is the same as specified . 
2.1. A special case (used by Migration TDs) is when the binding had been done on destination platform before the 
TD was imported.  In this case the target TD_UUID is overwritten at the beginning of import, as part of the TD’s 
immutable state import by TDH.IMPORT.STATE.IMMUTABLE.  The pre -import TD_UUID is saved in the target 
TD’s TDCS.  If the specified target TD_UUID d oesn’t match the actual value, but matches the pre -import value, 10 
a status code is returned to the service TD, with the updated TD_UUID.  
3. Get the binding parameters from the target TD’s service TD table binding slot.  
4. Check that the service TD’s TD_UUID is equal to the target TD’s bind slot’s SERV TD_UUID .

Output  
Operation  
4. Check that the service TD’s TD_UUID is equal to the target TD’s bind slot’s SERV TD_UUID . 
5. Access the metadata (similar to other metadata access operations) . 
13.3.2.  Metadata Access Error Handling  15 
TDG.SERVTD.RD/WR  interface functions  run in the context of the service TD but  access the target TD’s control structures.  
This introduces an opportunity for the service TD to create a denial -of-service to the host VMM, which is handled as 
Local Errors (in the Service TD Context ) 
Local errors that only impact  the service TD context are normally , as in other TDCALL flows .  These include, e.g., the 20 
following cases:  
• Errors such as incorrect serv ice TD state result in an error code returned to the caller service TD . 
• EPT violations when accessing the service TD’s memory cause a fault -like TD exit ;  The VMM may resolve the situation 
(e.g., TDH.EXPORT. UNBLOCKW if the service TD is being live-migrated) and resume the service TD . 
Cross -TD Errors  25 
Cross -TD errors impact the target TD.  For example, e rrors may happen due to target TD state , e.g., the target TD may be 
migrated or may be torn down.  The service TD may not be aware of the target TD state when invoking the interface 
function . 
Cross -TD errors cause a trap -like TD exit:  
1. TDG.SERVTD.RD/WR* flow sets output operands  (e.g., completion status returned in RAX) and advances the virtual 30 
CPU state to the next service TD guest instruction , but TD -exits immediately before resuming the guest TD . 
2. The host VMM may take action to detect denial of service, e.g., the guest calling TDG.SERVTD.RD/WR* in a tight loop.  
3. The host VMM may let the service TD resolve the situation by resuming it , using TDH.VP.ENTER.  On TD entry, t he 
service TD get s the status code as returned by TDG.SERVTD.RD*/WR* . 
13.3.3.  Cross -TD Concurrency Handling :  Maintaining Host -Side Priority  35 
 Problem Description  
Host VMM access to the target TD have a higher priority than service TD access to that target TD.  This help s mitigate 
denial -of-service cases such as when the s ervice TD loops on TDG.SERV.RD/WR *, locking target TD resource s and 
preventing the host VMM from doing host -side operations that require access to such resources.  
Applicable target TD resources  are, e.g.:  40 
• TDG.SERV.RD/WR  locks the target TD’s TDR in a shared mode, to help ensure  that the target TD is available 
throughout  the guest -side flow.   This may interfere with c ritical host -side operations (e.g., disabling a TD) that require  
locking that target TD’s TDR in an exclusive mode.  
• TDG.SERV.RD/WR  locks the target TD’s TDCS.OP_STATE  to help ensure  that OP_STATE doesn’t change in a way that 
prevents access during the guest -side flow .  This may interfere with c ritical host -side operations (e.g., pausing a TD 45 
during export) that require  locking that target TD’s OP_STATE in an exclusive  mode.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 122 of 153 
Section 2:  Intel TDX Module Architecture Specification  We currently assume that guest -side flows can only acquire locks in shared mode; thus, they only compete with the host -
side flows acquiring locks in exclusive mode.  
 Solution  
A new HOST_PRIORITY flag is added to shared/exclusive lock s protecting resources that may be accessed by the host 
VMM and a guest service TD.   For details, see 18.1.4 . 5 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 123 of 153 
Section 2:  Intel TDX Module Architecture Specification  14. I/O Support  (without TDX Connect)  
This chapter specifies the  Intel  TDX I/O  model  (for TDX Module versions and platforms that don’t support TDX Connect).  
14.1. Overview  
Intel TDX architecture does not prescribe a specific software convention to perform I/O from the guest TD.  Guest TD 
providers have many choices to provide I/O to the guest.  The common I/O models are emulated devices, para -virtualized 5 
devices, SRIOV devices and Direct Device assignments.  Guest TD providers can choose to offer the combinations of I/O 
models based on the workload and use case.  To virtualize MMIO, the following options can be utilized:  
• Para -Virtualized Drivers  can replace MMIO accesses with TDG.VP.VMCALL  to invoke VMM provided MMIO 
emulation functions.  
• MMIO Emulation by #VE Handlers  can use non-para -virtualized drive rs in the guest TD , with the emulation 
performed by the #VE handler.   EPT and #VE mechanism s can be  used to reflect violations to the #VE handler in 
the guest TD on access to virtual MMIO ranges .  These violations can invoke VMM -provided  MMIO emulation 
functions through TDG.VP.VMCALL .  In this model, the #VE handler is expected to emulate the faulting instruction 
in the guest TD.  
14.2. Paravirtualized I/O 
Para -virtualization (e.g., using virtio APIs in KVM, etc.) helps provide a mechanism for the guest TD to use devices on the 
host machine that are owned and managed by the VMM.  The guest TD drivers can use the TDG.VP.VMCALL  function to 10 
invoke the functions provided by the VMM to perform I/O.  The TD drivers must ensure that the data buffers passed 
to/from functions invoked using TDG.VP.VMCALL  are placed in the TD’s shared memory space.  
14.3. MMIO Emulation  and Emulated Devices  
An alternate technique that the guest TD may employ to invoke VMM functions for I/O is to emulate MMIO access from 
legacy device drivers.  To support this use model, the VMM may enable reflection of EPT violation to emulated MMIO 15 
guest physical addresses as virtualization exceptions (#VE), as described  in 11.10 .  A #VE exception handler in the guest 
TD OS can emulate the instruction causing the #VE, and as part of the emulation, it can invoke the I/O functions provided 
by the VMM using TDCALL( TDG.VP.VMCALL ).  Similar to the paravirtualized I/O model, the TD software must ensure that 
the data buffers passed to/from functions invoked using TDG.VP.VMCALL  are placed in the TD’s shared memory space.  
14.4. Direct Device Assignment  (DDA) and SRIOV  20 
The VMM may assign devices directly to the guest TD.  The addresses mapping the MMIO resources of such devices must 
be mapped in the shared memory space of the TD.  When submitting data buffers to these devices, the guest TD must 
locate the data buffers in  shared memory such that the directly assigned device can move data in/out of such buffers 
using DMA.  The data buffers placed in shared memory should be programmed in IOMMU page tables.  
The SRIOV virtual function devices assigned to guest TD also follow the DDA guidelines stated above with respect to 25 
MMIO and data buffers.  The control plane of the virtual function would use the soft or hard mechanism to configure the 
virtual functions:  
• The soft mechanism would use para -virtualization to configure the virtual function.  
• The hard mechanism would use hardware mailboxes accessed using MMIO in the shared memory region.  
14.5. IOMMU – DMA Remapping  30 
The IOMMU uses the VT -d remapping tables to translate GPA in the DMA from device to a n HPA .  The VT -d remapping 
tables will reflect the mapping of memory used by I/O devices in the guest TD.  The programming of the VT -d remapping 
tables and manag ement will be done by the VMM.  
Only shared GPA memory should be mapped in the VT -d tables:  
• If the result of the translation results in a physical address with a TD private key ID, then the IOMMU will abort the 35 
transaction and report a VT -d DMA remapping failure.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 124 of 153 
Section 2:  Intel TDX Module Architecture Specification  • If the GPA in the transaction that is input to the IOMMU is private (SHARED bit is 0), then the IOMMU may abort the 
transaction and report a VT -d DMA remapping failure, even if the translated physical address is with a non -private 
HKID.  This is intended t o support debug wherein a TD or VMM could program a bad GPA into the device.  
14.6. Shared Virtual Memory (SVM)  
Shared Virtual Memory enables applications to access buffers directly accessed by the devices.  The VT -d tables  help  5 
provide the mechanism to map application buffers using the first level  and second -level page tables to provide 
applications access to the same memory accessed by devices.  
SVM should be avoided  because VT-d tables can only map shared memory.    Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 125 of 153 
Section 2:  Intel TDX Module Architecture Specification  15. Debug and Profiling Architecture  
The Intel TDX module  debug architecture includes the following debug facilities:  
On-TD Debug : Facilities for debugging a guest TD using software that runs inside the TD  
Off-TD Debug : Facilities for debugging a guest TD, configured in debug mode, using software that runs outside the TD

Off-TD Debug : Facilities for debugging a guest TD, configured in debug mode, using software that runs outside the TD  
15.1. On-TD Debug  5 
15.1.1.  Overview  
On-TD debug means that the TD software is using CPU debug capabilities.  A debug agent inside the guest TD can use 
available CPU debug features and – if needed – interact with external debug entities (e.g., a debugger running in a VM 
on the same platform, or a debugger running on another platform) via standard I/O interfaces.  The Intel TDX module is 10 
designed to virtualize and isolate TD debug capabilities from the host VMM and software.  On -TD debug can be used for 
production or debug TDs – i.e., regardless of the guest TD’s ATTRIBUTES.DEBUG state.  
Guest TDs are allowed to use almost all architectural debug features supported by the processor , e.g.: 
• Single stepping  
• Code, data and I/O breakpoints  15 
• INT3  
• Bus lock detection  
• DR access detection  
• TSX debug  
However, the TDX architecture does not allow guest TDs to toggle IA32_DEBUGCTL uncore PMI enabling bit (13) . 20 
Guest TDs are allowed to use almost all architectural tracing features, e.g.: 
• LBR (if allowed by the TD’s XFAM, see 11.5 ) 
• PT (if allowed by the TD’s XFAM, see 11.5 ) 
• BTS 
• PEBS  25 
• PERF_METRICS  
However, the TDX architecture does not allow guest TDs to use BTM.  
15.1.2.  Generic Debug Handling  
 Context Switch  
By design, t he Intel TDX module  context -switch es all debug/tracing state that the guest TD is allowed to use.  30 
• DR0-3, DR6 and IA32_DS_AREA MSR are context -switched in TDH.VP.ENTER  and TD  exit flows.  
• RFLAGS, IA32_DEBUGCTL MSR and DR7 are saved and cleared on VM exits  from the guest TD and restored on VM 
entry to the guest TD.  
• Pending debug traps are natively saved on VM exits from the guest TD and reloaded on VM entries using the TD 
VMCS PDE field.  35 
Intel SDM, Vol. 3, 17.4.1  IA32_DEBUGCTL MSR  
By design, IA32_DEBUGCTL  access by the guest TD is restricted as follows : 
• Guest TD attempt s to set any of the architecturally reserved  bits 63:1 6 and 5: 3 result in a #GP (0). 
• Guest TD attempts to set bit 14 (FREEZE_WHILE_SMM) to 1 when the virtual value of  IA32_PERF_CAPABILITIES[12] 40 
(FREEZE_WHILE_SMM_SUPPORTED)  is 0 results in a #GP(0).  See 15.2 below  for Performance Monitoring details.  
• Guest TD attempts to set bit 15 (RTM_DEBUG) to 1 when the virtual value of  CPUID(7,0).EBX[11] (RTM) is 0 results 
in a #GP(0).  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 126 of 153 
Section 2:  Intel TDX Module Architecture Specification  • Guest TD attempt s to set TDX-disallowed values result in  a #VE .  This includes the following cases:  
o Enable Uncore PMI by setting bit 13 to 1 (see 15.4 below ). 
o Enable BTM by setting bits 7:6 to 0x1  (see details in 15.1.3 below ). 
• Uncore PMI is virtualized as disabled; bit 13 is read as 0 (see 15.4 below ). 
15.1.3.  Debug Feature -Specific Handling  5 
The following table discusses how specific debug features are handled.  
Table 15.1:  Debug Feature -Specific Handling  
Hardware 
Breakpoints  • DR7, DR0 -3 and DR6  No special handling :  DRs are context -switched . 
General Detect  • DR7 bit 13 (GD)  No special handling :  DR7 is context -switched . 
• IA32_DEBUGCTL bit 15 (RTM)  No special handling :  DR7 and IA32_DEBUGCTL are 
context -switched . 
Single Stepping  • RFLAGS bit s 18 (Trap Flag) and  
• IA32_DEBUGCTL bit 1 (BTF)  No special handling :  RFLAGS and IA32_DEBUGCTL are 
Bus-Lock 
(BUS_LOCK_DETECT ) No spec ial handling:  IA32_DEBUGCTL is context -
switched . 
Software 
Breakpoints (INT1, 
INT3)  None  No special handling :  software  breakpoints are stateless . 
and 7 (BTS)  Not allowed :  when a guest TD at tempts to set 
IA32_DEBUGCTL[7:6] to 0x1, the Intel TDX module  injects  
a #VE (see 15.1.2 above ). 
0x1.  
(BTS) • IA32_DEBUGCTL bits 6 (TR), 7 
(BTS_OFF_OS)  and 10 
(BTS_OFF_USR)  No special handling :  IA32_DEBUGCTL and IA32_DS_AREA 
are context -switched.  
Note s:   
• The guest TD  can configure BTS to raise PMI on buff er 
are virtualized by the host VMM, the guest TD should 
be ready to handle spu rious, delayed and dropped 
PMIs.  See Perfmon discussion in 15.2 below . 
• BTS may allow the guest TD to hang the machine if 
BTS record generation causes a #PF or a #GP(0), 
because the act of getting to the exception handler 
may deliver another BTS.  It is highly recommended 
that the host VMM enables  instruction timeout  TD 
exit, as described in 0. 
• Requires VMM ’s consent on 
TD_PARAMS .XFAM[8]  to 1  PT state handling  as part of the extended feature set 
state is discussed in 11.5 . 
•  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 127 of 153 
Section 2:  Intel TDX Module Architecture Specification  Debug Feature  How the Feature is Controlled  Handling  
Arch itectural Last 
Branch Record s 
TD_PARAMS .XFAM[ 15] to 1  LBR state handling  as part of the extended feature set 
Non -Arch itectural  
LBRs  • IA32_DEBUGCTL bit 0 (LBR)  Guest TD attempt to set IA32_DEBUGCTL[ 0] is ignored by 
the CPU . 
 
15.2. On-TD Performance Monitoring  
Intel SDM, Vol. 3, 18  Performance Monitoring  
15.2.1.  Overview  
If the TDX module supports on -TD performance monitoring, then t he host VMM controls whether a guest TD can use the 5 
performance monitoring ISA using the TD’s ATTRIBUTES.PERFMON bit – part of the TD_PARAMS input to TDH.MNG.INIT  
(see the [ TDX Module ABI Spec ]). 
By design, i f a guest TD is allowed to use performance monitoring , then : 
• The guest TD enumerates native architectural Perfmon capabilities via CPUID leaf 0x0A. 
• The guest  TD is allowed to use all Perfmon ISA .  This includes  executing  the RDPMC instruction and accessing  Perfmon 10 
MSRs  (see 15.2.3 below ). 
• Perfmon state is context -switched by the Intel TDX module  across TD entry and exit transitions . 
Context -switching the Perfmon state has a performance impact.  TD entry and exit latencies are longer than when a guest 
TD is not allowed to use Perfmon.  
By design, i f a guest TD is not allowed to use performance monitoring , then : 15 
• The guest TD enumerates  no architectural Perfmon capabilities .  CPUID leaf 0x0A returns all 0s.  
• The guest TD is not allowed to use Perfmon ISA , including RDPMC.  
• Perfmon state is not context -switched across TD entry and exit transitions.  
Regardless of Perfmon enabling , per the design:  
• IA32_DS_AREA MSR is context -switched across TD entry and exit transitions.  20 
• Counter freeze control ( IA32_ DEBUGCTL bit 12) is context -switched across TD entry and exit transitions.  
• The u ncore PMI enable bit ( IA32_ DEBUGCTL bit 13) is preserved  during SEAM mode execution, including Intel TDX 
module  and guest TD execution .  This bit is virtualized to the guest TD as 0, and the TD is prevented from setting it.   
See 15.4 below  for details.  
See also 15.1 above . 25 
The Intel TDX module is designed to support the following performance monitoring capabilities:  
• Architectural performance monitoring version 5, described in [Intel SDM, Vol. 3, 18.2.5)  
• Exactly 8 performance monitoring counters (IA32_PMC0 through IA32_PMC7)  
• Up to  7 fixed counters (IA32_FIXED_CTR0 through IA32_FIXED_CTR 7) 
• Some non -architectural MSRs (see 15.2.3 below ) 30 
• Guest TDs are  not allowed to use Architectural PEBS.  On CPUs where Architectural PEBS is enabled, the host VMM 
must reset all Arch PEBS configuration MSRs (see below) before calling TDH.VP.ENTER on a Perfmon -allowed TD.  
15.2.2.  Performance Monitoring CPUID Virtualization  
CPUID(0xA) is the legacy Perfmon leaf .  CPUID(0x23) is the new Perfmon leaf , supported if CPUID(7,1).EAX[8] is 1 . 
Both leaves are virtualized to the guest TD if ATTRIBUTES.PERFMON is 1.  CPUID(0x23) is virtualized as 0  if the virtual 35 
value of CPUID(7,1).EAX[8] is 0. 
TDX does not  allow the host VMM to directly configure the virtualization of CPUID(0xA) and CPUID(0x23) . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 128 of 153 
Section 2:  Intel TDX Module Architecture Specification  15.2.3.  Performance Monitoring MSRs  
 Overview

 Overview  
The following table s describes TDX handling of MSRs  used by Perfmon : 
Table 15.2:  Performance Monitoring MSRs  
MSR  Comments  Enumeration  Reference  
IA32_PMCx  multiple MSRs  (x < CPUID(0x0A).EAX[15:8] ) 
The Intel TDX module  requires the CPU to 
support 8 counters .  
IA32_A_PMCx  multiple MSRs  Same as IA32_PMCx  [Intel SDM, 
Vol. 3, 
18.2. 6] 
IA32_PERFEVTSELx  multiple MSRs  Same as IA32_PMCx   
IA32_FIXED_CTRx  multiple MSRs  ((x < CPUID(0x0A).EDX[4:0]) || 
 (CPUID(0x0A).ECX[x]  == 1)) 
The Intel TDX module  support s counters 0 
through 6, if supported by the CPU.  [Intel SDM, 
Vol. 3, 
18.2.5.2 ] 
IA32_FIXED_CTR_CTRL     
IA32_PERF_METRICS   IA32_PERF_CAPABILITIES[15]   
IA32_PERF_CAPABILITIES     
MSR_OFFCORE_RSPx  2 MSRs, non-
architectural    
IA32_PERF_GLOBAL_STATUS     
IA32_PERF_GLOBAL_CTRL     
IA32_PERF_GLOBAL_STATUS_RESET  
IA32_PERF_GLOBAL_STATUS_SET  Command MSR s 
– not context -
switched    
IA32_PERF_GLOBAL_INUSE     
 5 
Table 15.3:  Legacy PEBS MSRs  
IA32_PEBS_ENABLE  non-architectural  IA32_M ISC_ENABLE[12]   
MSR_PEBS_DATA_CFG  non-architectural  IA32_MISC_ENABLE[12]   
MSR_PEBS_LD_LAT  non-architectural  IA32_MISC_ENABLE[12]   
MSR_PEBS_FRONTEND  non-architectural  IA32_MISC_ENABLE[12]  
Not supported on E-cores   
 
MSR virtualization is described in 11.7 . 
15.2.4.  Perf ormance Monitoring Interrupts (PMIs)  
By design, w hen a guest  TD is allowed to use Perfmon, it can also configure the counters to raise PMI on overflow.  When 10 
such a TD counter overflows, the physical interrupt or an NMI  configured by the  host  VMM into the local APIC is delivered.  
This interrupt or NMI cause s a VM exit, and it is delivered as a TD exit to the host VMM.  The host VMM is then expected 
to inject the PMI into the guest TD, either as a virtual interrupt using the posted interrupt mechanism (see 11.9.4 ), or as 
virtual NMI  using the NMI injection  interface  (see 11.9.6 ). Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 129 of 153 
Section 2:  Intel TDX Module Architecture Specification  Since the  host  VMM is not trusted, the guest TD must be ready to handle spurious, delayed or dropped PMIs.  Thus, it is 
recommended for the guest TD to use PEBS  instead of  PMIs in order to record TD state at counter overflows.  
Uncore PMIs are discussed in 15.4 below . 
15.3. Off-TD Debug  
A guest TD is defined as debuggable  if its ATTRIBUTES.DEBUG bit is 1.  In this mode, the host VMM can use Intel TDX 5 
module functions to read and modify TD VCPU state and TD private memory, which are not accessible when the TD is 
non-debuggable.  
A debuggable TD is, by nature, untrusted.  Since the TD’s ATTRIBUTES are included in the TDREPORT_STRUCT, the TD’s 
debuggability state is visible to any third party to which the TD attests.  
A debuggable TD can’t be migrated; its ATTRIBUTES.MIGRATABLE bit must be 0.  10 
The applicable Intel TDX module  function s are listed in Table 15.4 below .  Note that some of the function s can access 
non-secret guest TD state regardless of the DEBUG attribute.  The lists of state information that can be read and/or 
written in non -DEBUG and in DEBUG modes are detailed in the referenced sections.  
Table 15.4:  Off -TD Debug Interface  
Intel TDX  Function  ATTRIBUTES.DEBUG = 0  ATTRIBUTES.DEBUG = 1  
TDH.MNG.RD   
TDH.MNG.WR  N/A Access secret and non -secret TD -scope 
state in TDR and TDCS.  
TDH.MEM.SEPT.RD  Read Secure EPT entry  Read Secure EPT entry  
TDH.VP.RD   
TDH.VP.WR  Access non -secret TD VCPU state in 
TDVPS (including TD VMCS)  Access secret and non -secret TD VCPU 
state in TDVPS (including TD VMCS).  
TDH.MEM.WR  
TDH.MEM.RD  N/A Access TD -private memory.  
TDH.PHYMEM.PAGE.RDMD  Read page metadata (PAMT 
information)  Read page metadata (PAMT 
information).  
 15 
15.3.1.  Modifying Debuggable TD’s State, Controls and Memory  
• Read and modify TDVMCS fields that contain guest state, VM entry load controls, VM exit save controls, and VM 
• Read and modify TDVPS fields that contain additional TD VCPU’s state (e.g. , extended register state).  20 
• Read and modify a per -VCPU copy of the TD’s extended feature mask (XFAM), such that more extended register state 
would be saved to TDVPS on TD exit and restore from TDVPS on TD entry.  
This may cause the next VM entry into the TD VCPU to fail due to bad guest state.  It may also generate VM exits that 
wouldn’t have happened otherwise (e.g., VM exit due to a #PF within the TD).  In non -debuggable TD such VM exits are 
not expected, and thus treated as  fatal TD errors that cause a TD exit with a TDX_NON_RECOVERABLE_TD  status .  In 25 
debuggable TDs, however, such VM exits are expected and cause TD exit.  
Specifically, the TDX module handling of TD VM exits works  as follows:  
1. If this TD VM exit might happen on non -debuggable TDs:  
1.1. Do “standard ” handling (may result a TD exit).  
1.2. If an exception is pending to be injected into the TD:  30 
1.2.1.  If the TD is debuggable and its exception bitmap is programmed to intercept that exception:  
1.2.1.1.  TD exit to the VMM, as if the exception has been raised during TD execution.  
1.3. Resume the TD (may inject an exception).  
2. Else (an unexpected VM exit happened) : 
2.1. If the TD is debuggable then TD exit . 35 
2.2. Else handle this as a fatal TD error.   Do non -recoverable TD exit.  
In any case, the security of other guest TDs running in production mode is not impacted.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 130 of 153 
Section 2:  Intel TDX Module Architecture Specification  15.3.2.  Preven ting Guest TD Corruption of DRs  
The off-TD ( host -side) debugger may need to have full control over guest DRs to help prevent their corruption by the 
guest  TD.  To do so, the debugger can do the following:  
• Use TDH.VP.WR  to set the TD VMCS  GUEST_DR7  field ’s Global Detect bit . 
• Set the TD VMCS exception bitmap execution control to intercept debug exceptions . 5 
15.4. Uncore Performance  Monitoring Interrupts (Uncore PMIs)  
By design, n either the Intel TDX module  itself no r its guest TDs are allowed to use Uncore PMIs.  The state of 
IA32_DEBUGCTL MSR bit 13 ( ENABLE_UNCORE_PMI) is preserved across SEAMCALL, SEAM root and non -root mode and 
SEAMRET , except for  very  short time periods  immediately  after SEAMCALL and VM exit . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 131 of 153 
Section 2:  Intel TDX Module Architecture Specification  16. Memory Integrity Protection and Machine Check Handling  
16.1. Overview  
The Intel TDX module ’s memory integrity protection and machine c heck handling are designed to answer address the 
following security objective s: 
• Corruption of TD private data or Intel TDX module memory must be detectable before the decrypted corrupted data 5 
are consumed by the guest TD or by the Intel TDX module.  
• To help improve resistance to brute force attacks, software must not be able to repeatedly  cause memory integrity 
violations during Intel TDX module or guest TD operation.   When an integrity violation is detected, the affected guest 
TD and the key corresponding to its affected HKID must become unusable for normal operation of the TD – i.e., the 
TD may only be torn down.  10 
• Any software except guest TD or TDX module must not be able to speculatively or non -speculatively access TD private 
memory, to detect if a prior corruption attempt was successful in finding an integrity collision or failed and received 
zero -data.  
As a best effort , the TDX module is designed to enable limiting the impact of memory integrity violations in a guest TD 
context to that guest TD, i.e., requiring only that guest TD to be torn down.  However, there are cases where memory 15 
integrity violations result in an unbreakable shutdown of the LP.  
16.2. TDX Memory Integrity Protection Background  
16.2.1.  Server Platforms Memory Integrity Protection  
 Server Platforms:  Cryptographic Integrity (Ci) vs. Logical Integrity (Li), MAC and TD Owner  
TDX architecture aims to provide resiliency against confidentiality and integrity attacks by software .  Towards this goal, 20 
the TDX architecture helps enforce the enabling of memory integrity for all private HKIDs.  It supports two memory 
integrity modes that can be configured on the platform:  
Cryptographic Integrity (Ci)  Memory content is encrypted and protected by a MAC and a TD Owner bit.  
Logical Integrity (Li)  Memory content is encrypted  and protected by a TD Owner bit.  
In both Ci and Li modes, the memory controllers store a 1 -bit TD Owner  metadata each cache  line.  The TD Owner bit is 25

In both Ci and Li modes, the memory controllers store a 1 -bit TD Owner  metadata each cache  line.  The TD Owner bit is 25 
set to 1 for writes with a private HKID and is cleared to 0 for writes with a shared HKID.  The TD Owner bit is covered by 
ECC.   
When Ci mode is enabled, the CPU’s memory controllers compute a 28 -bit integrity check value ( MAC ) for the data (cache 
line) during writes and  store the MAC with the memory as meta -data .  The MAC is calculated over the components  
described in the table below.  The MAC is covered by ECC .   30 
Table 16.1:  Components for MAC Calculation (Ci Mode)  
Component  Description  
Ciphertext Data  512 bits of data being written to memory.  
Encryption Tweak  128-bit encryption tweak, generated by encrypting the physical address with the 128-bit 
per-HKID ephemeral AES -XTS tweak key.  The tweak key is generated on key 
configuration (TDH.SYS.KEY.CONFIG and TDH.MNG.KEY.CONFIG).  
TD Owner Bit  Indicates that the data was written using a private HKID.  
MAC Key  128-bit MAC key, generated by hardware on platform initialization , when BIOS 
configures the IA32_TME_ACTIVATE MSR.  
November 2023   . Page 132 of 153 
 Server Platforms:  MAC and TD Owner Update on Memory Writes  
The MAC and the TD Owner bit are updated on memory writes by the memory controller per the following criteria:  
• If memory write is for a private HKID, the TD Owner bit is set, and integrity information (MAC) is computed and 
stored as meta -data along with ciphertext in memory.  
• Else (write is for a shared HKID), the TD Owner bit is clear, and based on the key configuration, integrity information 5 
(MAC) may be stored along with ciphertext in memory.  
The state diagram below shows the TD Owner bit state changes due to memory state changes.  
Non -
TD TD
Host VMM converts from private 
HKID to shared HKID
(write using shared HKID)TDX module converts from 
shared HKID to private HKID
(write using private HKID)
Write using 
shared HKIDTD or TDX module 
write using private 
HKID
 
Figure 16.1:  Server Platforms:  TD Owner Bit Setting on Write  
 Server Platforms Memory Reads:  Integrity and TD Owner Bit Checks, Poison Generation and Poison 10 
Consumption  
On server platforms, c hecks on memory reads depend on whether Cryptographic Integrity (Ci) is enabled on the platform, 
or Logical Integrity (Li) is used.  This is shown in the tables below.  
• When the memory read transaction uses a private HKID, TD Owner bit mismatch and/or integrity check failure (for 
Ci) result in a new poison generation.  An all -0 data is returned, with a poison indication.  15 
• The poison indication is sticky; it is stored back to memory.  Subsequent read transactions that read a previously 
poisoned memory line return a poison indication regardless of the TD Owner bit or integrity checks.  A sticky poison 
indication is cleared wh en the whole memory line is written; the correct way to do so is by using the MOVDIR64B 
instruction.  
• Any reads of TD private data (TD Owner is 1) done outside SEAM mode (i.e., with a shared HKID) return all -0.  This is 20 
intended to prevent the host VMM from testing malicious ciphertext for a MAC collision, since the VMM will 
deterministically see zeroed data in the cache for speculative accesses, which on subsequent non -speculative 
accesses will cause a machine check even t.  No new poison indication is returned; however, a previous poison 
indication that has been stored in memory may be returned.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 133 of 153 
Section 2:  Intel TDX Module Architecture Specification  Table 16.2:  Server Platforms Checks on Memory Reads in Ci Mode  
HKID 
Type  Integrity 
Enabled 
for HKID  TD 
Owner 
Bit Integrity 
Check  Returned 
Data  New 
Poison  Comments  
Private  Yes 0 N/A 0 Poison  TD bit mismatch failure may be triggered 
if the memory was previously written 
using a shared HKID.  
1 Pass  Decrypted 
data  None  If the memory line has been previously 
poisoned, the read transaction may return 
a poison.  
1 Fail 0 Poison  Integrity check failure may be triggered if 
the memory was previously written using 
a different encryption key.  
Shared  Yes 0 Pass  Decrypted 
a poison.  
0 Fail 0 Poison  Integrity check failure may be triggered if 
1 N/A 0 Poison  TD bit mismatch failure may be triggered 
using a private HKID.  
Shared  No 0 N/A Decrypted 
a poison.  
1 N/A 0 None  If the memory line has been previously 
a poison.  
 
Table 16.3:  Server Platforms Checks on Memory Reads in Li Mode  
HKID 
Enabled 
for HKID  TD 
Owner 
Data  New 
Private  No 0 N/A 0 Poison  TD bit mismatch failure may be triggered 
1 N/A Decrypted 
a poison.  
a poison.  
a poison.  
 
16.2.2.  Server Platforms Memory Writes:  No Integrity nor TD Owner Bit Checks  5 
On server platforms, the TD Owner bit is not checked on memory writes.  It is the responsibility of the host VMM to 
prevent writing to memory that has been assigned as TD private memory.  Failing to do so will result in a memory Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 134 of 153 
Section 2:  Intel TDX Module Architecture Specification  corruption; such corruption will be detected when the guest TD or the TDX module attempts to read that memory, as 
described above.  
The host VMM should always initialize memory that has been used with a private HKID (i.e., TD private memory and TDX 
control structures), and is about to be used with a shared HKID, using a full line write.  The correct way to do so is by 
using the MOVDIR6 4B instruction.  This helps ensure that the TD Owner bit and any stored poison indication are cleared.  5 
16.2.3.  Memory Integrity Error Logging, Machine Checks and Unbreakable Shutdowns  
Memory integrity errors that result in poison generation are logged by the memory controller as UCNA (uncorrected no -
action required) UCR errors  which are signaled via CMCI (if CMCI is enabled) or CSMI (if enabled).  
On a subsequent consumption (read) of the poisoned data by software , there are two possible scenarios:  
Machine Check : In most cases, the c ore determines that the execution can continue , and it treats poison with 10 
fault -like  exception semantics signaled as a n MCE (Machine Check Exception)  or MSMI 
(Machine -check System Management Interrupt) . 
 Handling of machine check events (MCE or MSMI) when executing in a guest TD (in SEAM non -
root mode) and in the Intel TDX module (in SEAM root mode) is described in the following 
sections.  15 
Unbreakable Shutdown : In some cases, the co re determines that execution cannot continue  (e.g., long µCode flows) , 
and it goes into an  unbreakable shutdown . 
An unbreakable shutdown that happens while running in SEAM mode, either in a guest TD or 
in the TDX module, globally marks TDX as disabled – all subsequent SEAMCALL invocations on 
any logical processor of the platform lead to a VMfailInvalid error . 20 
16.3. Machine Check Architecture (MCA) Background  
Intel SDM, Vol. 3, 15  Machine -Check Architecture  
The machine -check architecture (MCA)  provides a mechanism for detecting and reporting hardware (machine) errors.  
These include system bus errors, ECC errors, parity errors, cache errors and TLB errors.  MCA consists of a set of model -
specific registers (MSRs) that are used to set up machine  checking, and it includes additional banks of MSRs used for 25 
recording errors that are detected.  
16.3.1.  Uncorrected Machine Check Error  
The processor signals the detection of an uncorrected machine -check error  by generating a machine -check exception 
(MCE ), which is a fault -like exception.  An MCA  enhancement support s software recovery from certain uncorrected  
recoverable machine check errors.   Poisoned cache line consumption by the guest TD is considered such an error.  The 30 
machine -check exception handler is expected to be implemented in the VMM.  
16.3.2.  Corrected Machine Check Interrupt (CMCI)  
Intel SDM, Vol. 3, 15.5  Corrected Machine Check Error Interrupt

Intel SDM, Vol. 3, 15.5  Corrected Machine Check Error Interrupt  
Processors on which TDX will be supported can also report information on corrected machine -check errors and deliver a 
programmable interrupt for software to respond to MC errors – referred to as corrected machine -check interrupt (CMCI) . 35 
CMCI is delivered as a normal interrupt.  If delivered during guest TD operation, this interrupt causes a VM exit, and Intel 
TDX module performs a TD exit to the host VMM.  If delivered during Intel TDX module operation, this interrupt remains 
pending unti l either SEAMRET to the host VMM or until VM entry to a guest TD.  
16.3.3.  Machine Check System Management Interrupt (MSMI)  
MSMI is part of the Enhanced Machine Check Architecture, Gen. 2 (EMCA2).  With EMCA2 enabled, each machine check 40 
bank can be configured to assert SMI instead of MCE or CMCI.  This is intended to allow the SMM handler to correct the 
error when possible.  For details, see [Error Reporting through EMCA2].  
When the processor observes an SMI while a guest  TD is running (i.e., SEAM non -root  mode ) it causes a VM exit to the 
TDX module  with exit reason set to “ IO SMI ” or “Other SMI” VM exit appropriately .  The observed SMI remains pending 
following the VM exit.  The exit qualification bit 0 is set to 1 if the SMI is a machine check initiated SMI (MSMI).  45 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 135 of 153 
Section 2:  Intel TDX Module Architecture Specification  16.3.4.  Local Machine Check Event (LMCE)  
Intel SDM, Vol. 3, 15.3.1.5  Enabling Local Machine Check  
When system software has enabled LMCE, then hardware will determine if a particular error can be delivered only to a 
single logical processor, instead of being broadcast to all logical processors.  This is the recommended configuration for 
TDX.  5 
16.4. Recommended MCA Platform Configuration for TDX  
The following platform MCA configuration is recommended for TDX:  
• LMCE should be enabled, so that machine check events that happen in the scope of a certain logical processor are 
delivered only to that logical processor.  
• EMCA2 should be disabled, so that the host VMM can handle memory integrity errors by tearing down a single TD, 10 
instead of shutting down the whole platform.  
The following sections provide additional details.  
16.5. Handling Machine Check Events  during Guest TD Operation  
16.5.1.  Machine Check Events Delivered as an #MC Exception (Recommended)  
If EMCA2 is not enabled, the machine check event is delivered as an #MC exception.  With LMCE enabled, the MCE is 15 
delivered only to the logical processor that consumed the poisoned cache line.  
The Intel TDX module configures the MCE events when they occur in a TD guest to cause a VM exit to the Intel TDX 
module.  This includes the following cases:  
• MCE during guest TD operation  
• MCE during a successful VM entry to a guest TD  20 
• MCE during a failed VM exit, where normally execution would remain in the guest TD  
The Intel TDX module  implements this as follows:  
• The Intel TDX module  enforces guest TD CR4.MCE to 1.  
• The Intel TDX module  sets bit 18 (MC) of the TD VMCS Exception Bitmap to 1.  
On VM exit, if the exit reason is Exception or NMI (0), the Intel TDX module reads the TD VMCS’ VM -exit interruption 25 
information  to determine if the VM exit was caused by a #MC (18).  If so, the Intel TDX module  puts the TD in a FATAL 
state, preventing further TD entries.  The TDX module then completes the TD exit flow.  The TDH.VP.ENTER outputs 
indicate the status as TDX_NON_RECOVERABLE_TD_FATAL  and provides the exit reason, exit qualification and exit 
interruption information.  
Note:  The TDX module does not analyze the MCE to determine its source – whether it’s a memory integrity violation 30 
or some other event.  
Based on the TDH.VM.ENTER outputs (exit reason etc.), the host VMM is expected to understand that a Machine Check 
event happened, and that the TD should be torn down.  
The host VMM can reclaim memory assigned to TDs in a FATAL state using the normal TD teardown flow ( TDH.VP.FLUSH , 
TDH.MNG.VPFLUSHDONE, TDH.PHYMEM.CACHE.WB , TDH.MNG.KEY.FREEID , TDH.PHYMEM.PAGE.RECLAIM ). 35 
Note:  The host VMM should not attempt to read the poisoned memory locations.  Doing so results in a poison 
consumption and a n MCE in the VMM context.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 136 of 153 
TD TeardownTDX 
Host VMM1.Examine exit reason (0:  Exception 
or NMI)
2.Examine interruption information 
(vector 18:  #MC)
3.Mark TDasFATA L
TDH.VP .FLUSH
TDH.PHYMEM.CACHE.WB
TDH.PHYMEM.PAGE.RECLAI MTD exitVM 
exit
Write to TD 
Private PageRead attempt 
from TD 
Private PageIntegrity violation 
detected, causing machine 
check event
Determine that the 
TD encountered a 
machine check event 
Figure 16.2:  Example of Handling an MCE in a TD Context  
16.5.2.  Machine Check Events Delivered as an MSMI (Not Recommended)  
If EMCA2 is enabled, the machine check event is delivered as an MSMI.  With LMCE enabled, the MSMI is delivered only 
to the logical processor that consumed the poisoned cache line.  5 
Contrary to non -TDX operation, an SMI that occurs in a TD guest does not immediately invoke the SMM handler.  Instead, 
an SMI causes a VM exit to the Intel TDX module and remains pending.  
On VM exit, if  the exit reason is Other SMI (6), the Intel TDX module reads the TD VMCS’ exit qualification bit 0  to 
determine if the VM exit was caused by a Machine Check that was mutated into an SMI.  If so, the Intel TDX module  puts 
the TD in a FATAL state, preventing further TD entries.  The TDX module then completes the TD exit flow.  The 10 
TDH.VP.ENTER outputs indicate the status as TDX_NON_RECOVERABLE_TD_FATAL  and provides the exit reason and exit 
qualification.  
Note:  The TDX module does not analyze the MCE to determine its source – whether it’s a memory integrity violation 
Once TD exit has completed and the CPU is no longer in SEAM mode, the pending SMI event is taken and the platform’s 15 
SMM handler is invoked.  On RSM, the SMM handler injects an #MC to the host VMM.  
The host VMM needs to understand that the reported machine check event happened during TD execution and may be 
handled by tearing down the TD.  However, this may not be simple to implement.  Thus,  EMCA2 enabling is not 
recommended for TDX . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 137 of 153 
TDX 
Host VMM1.Examine exit reason (6:  Other SMI)
2.Examine exit qualification (bit 0:  1)
3.Mark TD as FATAL
TD exitSMI converted to a 
VM exit
Write to TD 
from TD 
detected, causing MSMI 
event
#MC handle
SMM 
HandlerHandle SMI, 
inject #MC event 
to host VMMSMM 
entryRSM#MC
#MC handler may be 
unaware of the TD exit 
information and unable to 
determine causeSMI delivered immediately 
following SEAMRET
 
Figure 16.3:  Example of Handling an MSMI in a TD Context  
16.5.3.  LMCE Disabled (Not Recommended)  
If LMCE is disabled, then an MCE or MSMI is broadcast to all logical processors on the platform.  Any TD that happens to 
be running will be put in a FATAL state.  5 
Note:  The TDX module does not check the MCE details.  Any MCE that causes a VM exit from a guest TD is considered 
fatal to that TD.  
16.5.4.  Machine Check Events Delivered as a CMCI  
CMCI is treated as a normal interrupt, causing an asynchronous TD exit; there’s no special handling.   
On VM exit, if the exit reason is Exception or NMI (0), the Intel TDX module reads the TD VMCS’ VM -exit interruption 10 
information  to determine if the VM exit was caused by a #MC (18).  If not, the Intel TDX module  completes the TD exit 
flow.  The TDH.VP.ENTER outputs indicate the status as TDX_ SUCCESS and provides the exit reason, exit qualification and 
exit interruption information.  
Based on the TDH.VM.ENTER outputs, the host VMM is expected to process the CMCI interrupt.  
16.6. Handling MCE during Intel TDX Module Operation  15 
Any machine check event that occurs during Intel TDX module operation (in SEAM root mode) forces an unbreakable 
shutdown on a current LP.  Shutdown also globally marks TDX as disabled – all subsequent SEAMCALL invocations on any 
logical processor of the platform lead to a VMfailInvalid  error . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 138 of 153 
Section 2:  Intel TDX Module Architecture Specification  17. Side Channel Attack Mitigation Mechanisms

Section 2:  Intel TDX Module Architecture Specification  17. Side Channel Attack Mitigation Mechanisms  
17.1. Checking and Virtualization of CPU Side Channel Protection Mechanisms  Enumeration  
17.1.1.  IA32_ARCH_CAPABILITIES  MSR  
On TDX module initialization (TDH.SYS.INIT and TDH.SYS.LP.INIT), the TDX module reads the IA32_ARCH_CAPABILITIES 
MSR to check the value of multiple bits, indicating whether the CPU is vulnerable to a list of known attacks.  The TDX 5 
module virtualizes the IA32_ARCH_CAPABILITIES MSR, as see n by guest TDs.  Some of the bits are configurable, to allow 
TD migration between dissimilar platforms.   For more information , refer to 11.7.2  and to the [ABI Spec].  
Table 17.1:  IA32_ARCH_CAPABILITIES MSR Checks and Virtualization  
Bit(s)  Name  Native Value 
Checked  on TDX 
Module Init  Virtual Value as Seen by Guest 
TDs Virtual Value Checked on 
Migration Import  
0 RDCL_NO  1 1 Must be 1  
1 IBRS_ALL  1 1 Must be 1  
2 RSBA  0 0 Must be 0  
3 SKIP_L1DFL_VMENTRY  1 1 Must be 1  
4 SSB_NO  Same on all LPs  Configurable by the host VMM – 
can allow to be 1  May be 1  only  if native is 1  
5 MDS_NO  1 1 Must be 1  
6 IF_PSCHANGE_MC_NO  1 1 Must be 1  
7 TSX_CTRL  Same on all LPs  Configurable by the host VMM – 
allowed to be 1 only if CPUID 
configuration enables TSX  Must be 1 if CPUID 
configuration enables TSX  
8 TAA_NO  1 1 Must be 1  
9 RESERVED  Same on all LPs  0 Must be 0  
10 MISC_PACKAGE_CTRLS  1 0 Must be 0  
11 ENERGY_FILTERING_CTL  1 0 Must be 0  
12 DOITM  1 1 Must be 1  
13 SBDR_SSDP_NO  1 1 Must be 1  
14 FBSDP_NO  1 1 Must be 1  
15 PSDP_NO  1 1 1 
16 RESERVED  Same on all LPs  0 0 
17 FB_CLEAR  Same on all LPs  0 0 
18 FB_CLEAR_CTRL  Same on all LPs  0 0 
19 RRSBA  Same on all LPs  Configurable by the host VMM – 
can force to 1  Must be 1 if native is 1  
20 BHI_NO  Same on all LPs  Configurable by the host VMM – 
can allow to be 1  May be 1 only if native is 1  
21 XAPIC_DISABLE_STATUS  1 1 1 
22 RESERVED  Same on all LPs  0 0 
23 OVERCLOCKING_STATUS  Same on all LPs  0 0 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 139 of 153 
Section 2:  Intel TDX Module Architecture Specification  Bit(s)  Name  Native Value 
24 PBRSB_NO  Same on all LPs  Configurable by the host VMM – 
63:25  RESERVED  Same on all LPs  0 0 
 
17.1.2.  CPUID  
On TDX module initialization (TDH.SYS.INIT and TDH.SYS.LP.INIT), the TDX module reads some CPUID fields to check the 
value of multiple bits, indicating whether the CPU is vulnerable to a list of known attacks.  The TDX module virtualizes the 
CPUID values, as seen by guest TDs.  Some of the bits are configurable, to allow TD migration between dissimilar 5 
platforms.  For more information, refer to 11.8  and to the [ABI Spec].  
Table 17.2:  Checks and Virtualization of Side Channel Related CPUID Fields  
Leaf  Sub-
Leaf  Reg.  Bit Name  Verified on TDX 
TDs 
7 0 EDX  9 MCU_OPT  0 0 
10 MD_CLEAR  1 1 
13 TSX_FORCE_ABORT  0 0 
26 IBRS and IBPB support  1 1 
27 STIBP support  1 1 
28 L1D_FLUSH support  1 1 
29 IA32_ARCH_CAPABILITIES  1 1 
30 IA32_CORE_CAPABILITIES  1 1 
31 SSBD supported  1 1 
2 EDX  0 PSFD supported  1 1 
1 IPRED_CTRL  1 1 
2 RRSBA_CTRL  1 1 
3 DDPD  Same on all LPs  Configurable by the host VMM – 
can allow to be 1  
4 BHI_NO  1  
5 MCDT_NO  Same on all LPs  Configurable by the host VMM – 
 
17.2. Branch Prediction Side Channel Attacks Mitigation Mechanisms  
Branch predictions cached by the CPU before entering a guest TD should not impact the behavior of that TD.  The Intel 10 
TDX module helps ensure  that by applying CPU mechanisms to isolate the branch predictions of each guest TD from 
branch predication done outside its execution.  
In a partitioned TD, the L1 VMM is responsible for isolating indirect branch predictors (IBPs) between the L1 VMM and 
L2 VMMs.  The L1 VMM should issue an indirect branch prediction barrier (IBPB) command to the CPU, by writing the 
IA32_PRED_CMD MSR with t he IBPB bit set, immediately before L1 →L2 VM entry and immediately after L2 →L1 VM exit.  15 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 140 of 153 
Section 2:  Intel TDX Module Architecture Specification  17.3. Single -Step and Zero -Step Attacks Mitigation Mechanisms  
17.3.1.  Description  
Single -step  attacks , zero -step  attacks  and EPT fault attacks are techniques that provide an adversary  with  access to a class 
of powerful, low -noise side channel attacks .  They do so  by exploiting control over hardware such as fine resolution APIC 
timers  and using TDX module memory management interface functions . 5 
• Single -Step Attacks  involve timing pin -based events such as interrupts, NMI, SMI  and INIT to interrupt the  guest  TD 
execution after every instruction executed in the guest TD.  This allows the attacker to examine the state of the 
machine following each instruction execution in interesting regions of code and  use side channels to leak information 
used by that region of code.  
• EPT Fault Attacks  involve causing EPT violations or EPT misconfigurations to infer the control flow of execution inside 10 
a guest  TD.  Such control flow inference coupled with other side channel techniques, such as  branch shadowing, can 
be used as a side channel to leak information from the guest TD. 
• Zero -Step Attacks  involve using an EPT fault on targeted instructions in a  guest  TD with an intent to glean side 
channel information from speculative execution past the faulting instruction.  Such instructions are called “replay 
anchors”, as every resumption of the TD execution leads to the same EPT fault and thus the same speculative 15 
execution with the same stimulus to be replayed repeatedly, such that noise in side -channel observation of that 
speculative execution can be reduced.  
The Intel TDX module provides mechanisms to help assist in mitigating single and zero step attacks : 
• For single step attacks, the TDX module detects when a TD VCPU gets interrupted soon (~4K cycles) after it was 
entered ; it continues to provide execution opportunities to the TD VCPU for a small random number of instructions 20 
before the interruption is delivered to the host VMM.   
• For zero step attacks, the Intel TDX module counts Secure EPT faults that result in a TD exit.  After a pre-determined  
number of such EPT violations occur on the same instruction, the TDX module  starts tracking the GPAs that caused 
Secure EPT faults and fails further host VMM attempts to enter the TD VCPU unless previously faulting private GPAs 
are properly mapped in the Secure EPT.  25 
Note:  For a partitioned TD, EPT violations that happen in the context of L2 VMs may result in a TD exit or in an 
L2→L1 exit.  Only the TD exit cases are counted for the purpose of zero step attack detection.  
17.3.2.  Host VMM Expected Behavior  
No change  is required to the host VMM’s normal memory management behavior:  
• The host VMM should block (TDH.MEM.RANGE.BLOCK) TD private pages and remove them 30 
(TDH.MEM.PAGE.REMOVE) only after the guest TD has explicitly relin quished the ownership of that page through a 
software protocol  between the VMM and the TD .  Such a protocol is implemented by t he balloon driver mechanism 
employed by guest Linux kernel to allow the host VMM to overcommit a guest VM assigned memory.  
• The host VMM can block TD private pages and perform the following GPA -to-HPA mapping updates without 
coordination with the guest TD:  35 
o Physical page relocation (TDH.MEM.PAGE.RELOCATE)  
o Mapping merge or split (TDH.MEM.PAGE.PROMOTE, TDH.MEM.PAGE.DEMOTE)  
o Unblock (TDH.MEM.RANGE.UNBLOCK)  
A guest TD VCPU attempt to access such pages while they are blocked results in an EPT violation TD exit.  A well -
behaved host VMM should not re -enter the TD until the mapping operation is done.  Failing to do so will immediately 40 
result in another EPT violation and the TD VCPU won’t make any progress.  
• The host VMM can block TD private pages for writing (TDH.EXPORT.BLOCKW) as part of TD migration.  A guest TD 
VCPU attempt to write to such pages while they are blocked for writing results in an EPT violation TD exit.  A well -
behaved host VMM should not re -enter the TD VCPU before unblocking the page (TDH.EXPORT.UNBLOCKW).  Failing 
to do so will immediately result in another EPT violation and the TD VCPU won’t make any progress.  45 
17.3.3.  Guest TD Interface and Expected Guest TD Operation  
The TDX module provides the  guest  TD with a notification facility, by which the guest TD can get notified when excessive 
Secure EPT violations are raised by the same TD instruction.  This mechanism allows the guest TD to employ its own

Secure EPT violations are raised by the same TD instruction.  This mechanism allows the guest TD to employ its own 
policies.  The guest TD enables this notification by setting bit 0 of TDCS.NOTIFY_ENABLES field, using TDG.VM.WR.  If this 
bit is set, then when more than a pre -determined number of Secure EPT violations are detected on the same instruction,  50 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 141 of 153 
Section 2:  Intel TDX Module Architecture Specification  • If the EPT violation happened when L1 was running (i.e., the TD is not partitioned, or L1 VMM was running) the TDX 
module injects a #VE exception, with the EPT violation details.  
• If the TD is partitioned, and the EPT violation happened when an L2 VM was running, the TDX module induces an 
L2→L1 exit.  The EPT violation details are provided in the exit information.  
As part of its normal memory management behavior, the guest TD should track its GPA space allocation and should only 5 
accept (TDG.MEM.PAGE.ACCEPT) PENDING pages that it expects to be added (TDH.MEM.PAGE.AUG) by the host VMM.  
Failing to do so would make the TD vulnerable to attacks, e.g., the host VMM could zero -out a page by removing it and 
adding a new one at the same G PA. 
Thus, when the guest TD attempts to access a page and a #VE is raised indicating an EPT violation, the expected guest 
TD’s #VE handler behavior is as follows:  10 
• If this page is not known to the guest TD as owned by it, i.e., it was not added at TD build time (TDH.MEM.PAGE.ADD) 
and has not been added dynamically (TDH.MEM.PAGE.AUG) and accepted (TDG.MEM.PAGE.ACCEPT), the guest TD 
can accept this page normally.  
• Otherwise, this may indicate an attack and the guest TD can employ its own policy.  For example, the guest TD may 
halt if this page is one of the pages expected to be resident when a security critical workload is executing .  15 
Alternatively, it may  signal the current running application so that the application would employ application -specific 
defenses.  
The guest TD’s #VE handler, as well as its virtual NMI handler, should not have any secrets that are susceptible to leakage.  
The Intel TDX module does not provide protection against attacks when accessing shared  pages.   The guest TD should 
treat shared memory access as  communicating with a potential attacker, and not  do any secure processing while 20 
accessing to shared memory . Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 142 of 153 
Section 2:  Intel TDX Module Architecture Specification  18. General Aspect s of the Intel TDX Interface  Functions  
18.1. Concurrency Restrictions and Enforcement  
18.1.1.  Explicit Concurrency Restrictions  
Intel TDX functions may specify concurrency restrictions on accessing one or more resources, as described below.  In 
most cases, the restriction applies for the duration of the instruction execution.  However, in some cases, the restriction 5 
applies for a longer duration.  For example , TDH.VP.ENTER  requires shared access to the TD -scope logical control 
structures TDR and TDCS , and it also requires shared access  to TDVP S – the VCPU -scope logical control structure which 
applies during logical TDX non -root operation through TD Exit.  
Table 18.1:  Concurrency Restrictions  of Intel TDX Functions  or Flows  
Concurrency 
Restriction  Description  Example s 
Exclusive 
Access  During the period when an LP has an exclusive access 
to a certain resource, any attempt by another LP to 
concurrently execute an  instruction that requires 
either an exclusive or a shared access to the same 
resource will fail . • TDH.VP.CREATE  requires an 
exclusive access to the TDVP R 
page.  
Shared 
Access  During the period when an LP has a shared access to a 
certain resource, any attempt by another LP to 
concurrently execute an instruction that requires an 
exclusive access to the same resource will fail .  No 
such restriction exists  on another LP that attempts to 
concurrently execute an instruction that requires a 
shared access.  • TDH.VP.CREATE  requires a shared 
access to the TDR page.  
• TDH.PHYMEM.CACHE.WB  requires 
a shared access to the KOT.  
Software is expected to comply with the specified concurrency restrictions.  The Intel TDX module  helps enforce them 10 
(using internal  locks) for proper TDX operation.  
Table 18.2:  Concurrency Restrictions Cross -Table  
  Logical Processor Y  
 Concurrency 
Restriction  Exclusive  Shared  None  
Logical 
Processor 
X Exclusive  Not Allowed  Not Allowed  Allowed  
Shared  Not Allowed  Allowed  Allowed  
None  Allowed  Allowed  Allowed  
 
Intel TDX functions  do not  wait on a resource that requires an exclusive or a shared access .  If the resource is busy , the 
function  fails immediately . 15 
18.1.2.  Implicit Concurrency Restrictions  
In some cases, Intel TDX functions and whole flows (e.g., TD Entry through TD Exit) may have implicit  exclusive or shared 
access to resources.  This means that the access restriction is implied by the architecture, but no direct enforcement is 
made by the flow itself.  
An important case is logical TDX non -root mode.  TDH.VP.ENTER  acquires shared locks on the TD’s TDR and TDCS control 20 
structures and on the VCPU’s TDVPS control structure.  These shared locks are released only on TD exit.  Thus, during all 
the time the LP is in the logical TDX non -root mode, including during TDCALL leaf functions, the LP has implicit shared 
access to TDVP S, TDR and TDCS.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 143 of 153 
Section 2:  Intel TDX Module Architecture Specification  18.1.3.  Transactions  
In some cases, Intel TDX module flows update some state as a transaction.  They first read the current state, then do 
some calculations and eventually attempt to update the state using an atomic operation (e.g., LOCK CMPXCHG) to check 
that the state has no t changed and set its new value.  If that check fails, an Intel TDX module interface function may fail 
with a TDX_OPERAND_BUSY status.  5 
18.1.4.  Concurrency  Restrictions with Host Priority  
 Overview  
Host priority is a variant on explicit concurrency restrictions, where the host VMM side is given priority  over guest TD 
side.  A new HOST_PRIORITY flag is added to locks protecting resources that may be accessed by the host VMM and a 
guest TD.  Both mutexes and shared/exclusive locks can be enhanced with host priority.  10 
 Host -Side (SEAMCALL ) Operation  
The host VMM is expected to retry host -side operations that fail with a TDX_OPERAND_BUSY  status.  The host priority 
mechanism helps guarantee that at most after a limited time (the longest guest -side TDX module flow) there will be no 
contention with a guest TD attempting to acquire access to the same resource.  
Lock operations process the HOST_PRIORITY bit as follows:  15 
• A SEAMCALL ( host -side) function that fails to acquire a lock sets the lock’s  HOST_PRIORITY bit  and returns a 
TDX_OPERAND_BUSY status to the host VMM.   It is the host VMM’s responsibility to re -attempt the SEAMCALL 
function until is succeeds; otherwise, the HOST_PRIORITY bit remains set, preventing the guest TD from acquiring 
the lock.  
• A SEAMCALL ( host -side) function that succeeds to acquire a lock clears the lock’s HOST_PRIORITY bit . 20 
 Guest -Side (TDCALL ) Operation  
A TDCALL (guest -side) function that attempt to acquire a lock fails if HOST_PRIORITY is set to 1; a TDX_OPERAND_BUSY 
status is returned to t he guest .  The guest is expected to retry the operation.  
Guest -side TDCALL flows that acquire a host priority lock have a n upper bound on the host -side latency for that lock ; once 
a lock is acquired, the flow either releases within a fixed upper time bound, or periodically monitor the HOST_PRIORITY 25 
flag to see if the host is attempting to acquire the lock . 
 Host Priority Busy Timeout  
Once a host -side operation failed with a TDX_OPERAND_BUSY status, the host VMM should retry this operation until it 
no longer fails with the same TDX_OPERAND_BUSY status.  Otherwise, the guest TD may be stuck trying to acquire a lock 
where the HOST_PRIORIT Y bit is set.  30 
The TDX module implements a timeout mechanism for guest -side host priority lock acquisition failures.  If the guest TD 
loops on a TDCALL (guest -side) function that fails with TDX_OPERAND_BUSY  due to HOST_PRIORITY value of 1 for more 
than a configurable timeout, the TDX module initiates a trap -like TD exit with a TDX_HOST_PRIORITY_BUSY_TIMEOUT  
status.  It is expected that this will never happen with a properly operating host VMM.  However, it is still possible for th e 
host VMM to resolve the lock contention by calling the SEAMCALL function that previously failed with a 35 
TDX_OPERAND_BUSY status until successful, and then re -entering the guest TD by calling TDH.VP.ENTER with the

TDX_OPERAND_BUSY status until successful, and then re -entering the guest TD by calling TDH.VP.ENTER with the 
HOST_RECOVERABILITY_HINT  bit cleared to 0 .  For details, see the [ TDX Module ABI Spec ]. 
The host priority timeout’s default value is 1 second.  It is configurable between 10 msec to 100 seconds by using 
TDH.MNG.WR to update TDCS. HP_LOCK_TIMEOUT .   Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 144 of 153 
Section 2:  Intel TDX Module Architecture Specification  18.2. Memory and Resource Operands Access  
Intel SDM, Vol. 3, 11.5.2  Precedence of Cache Controls  
Intel SDM, Vol. 3, 11.11  Memory Type Range Registers (MTRRs)  
Intel SDM, Vol. 3, 11.12  Page Attribute Table (PAT)  
18.2.1.  Overview  5 
In this section , we discuss Intel TDX functions’ memory and resource operands access from the following  perspectives:  
• Access semantics (shared, private, opaque and hidden)  
• Explicit vs. implicit accesses  
• Operand address specification ( host -physical address, guest -physical address)  
• Actual memory access (read or write) vs. memory reference  10 
 Access Semantics  
Access semantics, as used in this document, convey the intended purpose of the access.  Intel TDX functions  are designed 
to use one of the following access semantics when accessing their memory and/or platform resource parameters:  
Table 18.3:  Access Semantics  Definition  
Access 
Semantics  Description  Intel TDX Module  Usage  
Shared  Memory is accessed using one of the shared HKIDs (in 
the range 0 to MAX_MKTME_HKIDS  - 1).  This is mostly  
used for memory parameters accessed by the VMM.  • Source page of 
TDH.MEM.PAGE.ADD  
• Memory operands of TDCALL leaf 
functions  
Private  The memory is mapped in the TD’s private GPA space.  
Memory accessed using the target TD’s private HKID (in 
the range MAX_MKTME_HKIDS  - 1 to MAX_HKIDS  - 1). 
Such memory pages can be mapped in the TD’s private 
GPA space .   • TD private pages  
• Secure EPT pages  
Opaque  Memory is addressable by the host VMM, but its content 
is not directly accessible to software or devices.  Memory 
is encrypted using either the Intel TDX  global private key 
(for TDR) or the TD’s ephemeral private key (for other 
control structures).  • TDR  
• TDCX  
• TDVPR  
Hidden  Access is to a n Intel TDX module  internal resource.  That 
resource is not directly addressable as a memory 
operand to software or devices.  • KOT  
• WBT  
 15 
Note that on guest -side (TDCALL) functions, shared vs. private semantics is determined by the GPA provided as an 
operand to the function.  A specific TDCALL leaf function may or may not impose a private or a shared access – e.g., 
TDG.MEM.PAGE.ACCEPT  requires a private GPA, while TDG.MR.REPORT  may work with either a private GPA or a shared 
GPA.  
 Explicit vs. Implicit Access  20 
An explicit memory access  is defined as an a ccess where the memory location  is provided as explicit operand to an Intel 
TDX function.  The address may be provided directly in a GPR or indirectly via some address field in a  software -accessible 
memory  data structure . 
The HKID for accessing the memory can be inferred by the instruction – implicitly or explicitly from the explicitly provided 
access.  25 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 145 of 153 
Section 2:  Intel TDX Module Architecture Specification  An implicit memory access  is defined as an a ccess to a platform physical memory address, or to some other resource, 
that is not passed as  an operand of an instruction  (either directly or indirectly) but is  implied by use of the Intel TDX 
function .  TDX architecture helps guarantee that an implicit access is performed correctly , or a proper error action is 
taken.  
 Memory Operand Address Specification  5 
Host -side Intel TDX functions (SEAMCALL leaf functions ) memory operands are specified using  their  host -physical address 
(HPA), their guest -physical address (GPA) , or when a GPA -to-HPA mapping is done (e.g., TDH.MEM.PAGE.ADD ) by both 
HPA and GPA . 
In most cases, HPA for private or opaque access semantics must specified with all HKID bits set to 0. 
Guest -side Intel TDX functions ( TDCALL leaf functions ) memory operands are  specified using their guest -physical address 10 
(GPA). 
 Memory Type  
18.2.1.4.1.  Memory Type for Private and Opaque Accesses  
The memory type for private  and opaque  access  semantics, which use a private HKID,  is WB.   
18.2.1.4.2.  Memory Type for Shared Accesses  15 
Intel SDM, Vol. 3, 28.2.7.2  Memory Type Used for Translated Guest -Physical Addresses  
The memory type for shared  access semantics, which use a shared HKID, is determined as described below.  Note that 
this is different from  the way memory type is determined by the hardware during non -root mode operation.  Rather, i t 
is a best -effort approximation that is designed to still allow the host VMM some control over memory type.  
• For shared access during host -side (SEAMCALL) flows , the memory type is determined by MTRRs.  20 
• For shared access during guest -side flows (VM exit from the guest TD) , the memory type is determined by a 
combination of the Shared EPT and MTRRs.  
o If the memory type determined during Shared EPT walk is WB, then the effective memory type for the access is 
determined by MTRRs.  
o Else,  the effective memory type for the access is UC.  25 
 Actual Memory Access  vs. Memory Reference  
In some cases, Intel TDX functions only reference  memory – i.e., use its address, but no actual access is done.  
In other cases, Intel TDX functions access  the memory – i.e., perform read or write (but not execute) operations.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 146 of 153 
 Summary Table  
Table 18.4:  Memory Access Summary  
Explicit/  
Implicit  Intel TDX  
Function  Access 
Semantics  Address 
Operand  HKID Derivation  Memory 
Type  Example  
Explicit  Host -Side 
(SEAMCALL 
Leaf)  Shared  HPA  Derived  HPA 
operand’s HKID 
bits From MTRR  SRCPAGE operand of 
Private  HPA  TD’s HKID  WB Target page of 
GPA  TD’s HKID  WB CHUNK operand of 
TDH.MR.EXTEND  
HPA and 
GPA  TD’s HKID  WB Target page of 
Opaque  HPA  TD’s HKID or Intel 
TDX global HKID  WB TDVP R operand of 
TDADDVP R 
(TDCALL 
Leaf)  Shared  GPA  From Shared EPT From 
Shared EPT 
and MTRR  REPORTDATA operand of 
TDG.MR.REPORT  
Private  GPA  TD’s HKID  WB Target page of 
TDG.MEM.PAGE.ACCEPT  
Implicit  All Private/ 
Opaque  N/A TD’s HKID or Intel 
TDX global HKID  WB TDCS access by 
TDH.VP.ENTER  
Hidden  N/A N/A N/A KOT access by 
 
18.3. Register Operands and CPU State Conventio n  
Intel SDM, Vol. 3, 24.9  VM-Exit Information Fields  5 
Intel SDM, Vol. 3, App. C  VMX Basic Exit Reasons  
18.3.1.  Overview:  Regular vs. Transition Leaf Functions  
Intel TDX functions can be divided into transition functions and non -transition functions.  
The non-transition functions  are where SEAMCALL and TDCALL leaf functions behave  as emulated CPU instructions from 
the perspective of the host VMM and the guest TD, respectively.  In those cases, the meaning of input and output register 10 
operands is straightforward – similar to CPU instructions.  
Transition cases  are SEAMCALL( TDH.VP.ENTER ) and TDCALL( TDG.VP.VMCALL ) leaf functions, where a full cycle (until start 
of the next instruction) includes TD transitions to the guest TD or host VMM, respectively, and back to the host VMM or 
guest TD, respectively.  In those cases, we look at the functions from the point of vi ew of the caller.  The meaning of input 
and output register operands is more complicated.  15 
Both cases are  explained in the following sections and in the function  reference sections.  
18.3.2.  Interface Function Leaf and Version Numbers  
Interface functions are selected by a leaf number, provided in RAX.  A version number enables supporting multiple 
versions of the same function, if required for backward compatibility.   Unless otherwise specified, the default version 
number is 0.  20 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 147 of 153 
Section 2:  Intel TDX Module Architecture Specification  Table 18.5:  Intel TDX Interface Functions Leaf and Version Numbers in RAX  
Bits Field  Description  
15:0  Leaf Number  Selects the  SEAMCALL or TDCALL interface function  
23:16  Version Number  Selects the  SEAMCALL or TDCALL interface function version  
63:24  Reserved  Must be 0  
 
18.3.3.  CPU State Preservation  Convention  
 TDH.VP.ENTER  
TDH.VP.ENTER  is a special case.  In addition to explicit output operands discussed in 0 below , TDH.VP.ENTER  is not 5

TDH.VP.ENTER  is a special case.  In addition to explicit output operands discussed in 0 below , TDH.VP.ENTER  is not 5 
designed to preserve the extended CPU state that the TD may use according to TDCS.XFAM.  
The host VMM is expected to save any state it needs before calling TDH.VP.ENTER .  Details are provided in the 
TDH.VP.ENTER  leaf function definition (see the [ TDX Module ABI Spec ]). 
 Other Interface Functions  
All Intel TDX functions except TDH.VP.ENTER are designed to preserve the CPU state not explicitly defined as output.  10 
Most interface functions preserve the AVX, AVX2 and AVX512 state.  There are some exceptions, as described in the 
specific function definitions  (see the [ABI Spec]) : 
• TDG.VP.VMCALL may use some XMM registers to pass information to and from the host VMM.  
• Some interface functions may reset AVX, AVX2 and AVX512 state and/or the APX state (if the CPU supports it) to the 
architectural INIT state.  15 
18.3.4.  Transition Cases:  TD Entry and Exit  
 TD Entry: TDH.VP.ENTER  
Transfer of Host VMM  State to TD Guest  
By design, in the case of a TDH.VP.ENTER  leaf function that follows a previous TDG.VP.VMCALL , the RCX input parameter 
of  the previous TDG.VP.VMCALL  is used as a bitmap.  It selects the GPRs (from RBX, RDX, RBP, RDI, RSI and R8 through 20 
R15) and XMM registers whose value is transferred to the guest TD as -is.  RAX is set to 0.   See the TDG.VP.VMCALL  
description in the [ TDX Module ABI Spec ]. 
The rest of the  CPU state is restored from the TD VCPU state as saved on TDG.VP.VMCALL . 
Output State (Back to the Host VMM)  
On completion of TDH.VP.ENTER , a success – indicated by the ERROR bit (RAX[63]) being 0 – means that TD Entry into 25 
the TD guest was successful.  The TD guest ran for some time and then exited to the Intel TDX module .  That exit can be 
due to execution of TDG.VP.VMCAL L) or due to an asynchronous exit (e.g., an EPT Violation).  The Intel TDX module  then 
executes SEAMRET, transferring control to the instruction following TDH.VP.ENTER .  In this case, the DETAILS field 
(RAX[31:0]) format is  designed to be  the same as the VMX Exit reason . 
If the completion of TDH.VP.ENTER  (i.e., exit from the TD guest) was due to TDCALL( TDG.VP.VMCALL ), then the RCX input 30 
parameter of  TDG.VP.VMCALL  is designed to be used as a bitmap.  It selects the GPRs (from RBX, RDX, RBP, RDI, RSI and 
R8 through R15) and XMM registers whose value is passed to the host VMM as the output of TDH.VP.ENTER .  RCX itself 
is passed as -is to the output of TDH.VP.ENTER , and RAX[31:0] indicates the VMCALL  exit reason (see below).  See the 
TDG.VP.VMCALL  description in the [ TDX Module ABI Spec ]. 
If the completion of TDH.VP.ENTER  was due to another reason, then other VMX -like Exit Information fields are provided 35 
in other GPRs.  Details are provided in the TDH.VP.ENTER  leaf function definition (see the [ TDX Module ABI Spec ]). 
By design, a ny GPRs and extended states that do not return values as described above are set to synthetic values.  If the 
VMM uses any of the m, it must explicitly save them before TDH.VP.ENTER  and restore them afterward.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 148 of 153 
 TD Synchronous Exit:  TDG.VP.VMCALL  
Transfer of TD Guest State to Host VMM   
In the case of a TDG.VP.VMCALL  leaf function, the RCX input parameter of TDG.VP.VMCALL  is designed to be used as a 
bitmap.  It selects the GPRs (from RBX, RDX, RDI, RSI and R8 through R15) and XMM registers whose value is passed to 
the host VMM as the output of TDH.VP.ENTER .  RCX itself is passed as -is to the output of TDH.VP.ENTER . 5 
RAX provides TDH.VP.ENTER  completion status (see above ).  All other CPU state  component s, including GPRs and XMM 
registers not selected by RCX, are saved in TDVPS and set to fixed values (see  the [ TDX Module ABI Spec ]).  The value of 
RCX itself is also saved to TDVPS.    
Output State (Back to the Guest TD) 
On completion of TDG.VP.VMCALL , a success – indicated by the ERROR bit (RAX[63]) being 0 – means that a SEAMRET 10 
into the VMM was successful.  The VMM ran for some and then executed TDH.VP.ENTER  successfully (possibly on another 
LP).  The Intel TDX module  executed VMRESUME successfully, transferring control to the instruction following TDCALL.  
In this case,  the RCX input parameter of TDG.VP.VMCALL  is designed to be  used as a bitmap.  It selects the GPRs (from 
RBX, RDX, RDI, RSI and R8 through R15) and XMM registers whose value reflects their state as input to TDH.VP.ENTER .  
All other CPU states, including GPRs and XMM registers not selected by RCX, are restored from TDVPS.  15 
18.4. Interface Function Completion Status  
Intel TDX function completion status is returned in RAX.  The status is structured to provide as many details to software 
about error conditions as practically possible.  At the same time, the status enables software to ignore details that it does  
not need .  Software may parse the completion status at three detail levels, as described below.  
18.4.1.  Least Detailed Level:  Success/Warning/Error  20 
At this simplest level, software can differentiate among  three cases:  
Table 18.6:  Intel TDX Interface Functions Completion Status in RAX at the Least Detailed Level  
RAX Value  Meaning  Description  
0 Success  Function completed successfully  
Positive  
(0x00000000_00000001 
– 0x7FFFFFFF_FFFFFFFF)  Informational  / 
Warning  Function completed successfully, but with some informational 
or warning code – e.g., TDH.PHYMEM.PAGE.RECLAIM of a TDCX 
page that is already not VALID  
Negative  
(0x80000000_00000000 
– 0xFFFFFFFF_FFFFFFFF)  Error  Function aborted due to some error  
 
18.4.2.  Medium Detailed Level:  Class, Recoverability and Fatality  
At this level, software can understand the following information:  25 
Table 18.7:  Intel TDX Interface Functions Completion Status in RAX at the Medium Detailed Level  
CLASS  Class of the function completion status  
ERROR  Indicates that the i nstruction was aborted due to error  
NON_RECOVERABLE  Recoverability hint – in case of error, i ndicates that the error is probably not 
recoverable.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 149 of 153 
FATAL  Fatality hint – applicable only for SEAMCALL  (TDH.*), i ndicates that the TD 
entered a state where it can only be torn down.  
HOST_RECOVERABILITY_HINT  As a TDH.VP.ENTER output, indicates a TDCALL (TDG.*) that resulted in a trap -
like TD exit for which the host VMM needs to provide a recoverability hint in 
the following TD entry.  
As a TDCALL (TDG.*) output, indicates that the host VMM provided a hint that 
the error is probably not recoverable.  
 
18.4.3.  Most Detailed Level  
At this level, software can understand more details of an error that happened  – e.g., if TDH.VP.ADDCX  fails, software may 
understand if it is due to a wrong number of TDCX  pages or due to the VCPU already being initialized.  
Refer to the [ TDX Module ABI Spec ] for a detailed definition of function completion status.  5 
 
18.5. TD, VM and VCPU Identification  
Table 18.8:  TD and VCPU Identification  
Identifier  Format  Details  
TD Handle  TDR HPA  While residing in memory, a TD is uniquely identifier by the TDR page 
HPA , serving as the TD handle  input operand of TDX module host -side 
interface functions.  TDR HPA may change when, e.g., a TD is migrated.  
TD Universally 
Unique I dentifier  256-bit 
integer  TD_UUID serves as a globally unique TD identifier, randomly created 
when the TD is created.  TD_UUID survives migration.  
VCPU Handle  TDVPR HPA  While residing in memory, an VCPU is uniquely identifier by the TDVPR 
page HPA , serving as the VCPU  handle  input operand of TDX module 
host -side interface functions.  TDVPR HPA may change when, e.g., a TD 
is migrated.  
VCPU Index  16-bit integer  A sequential VCPU index is assigned when the VCPU is created.  VCPU 
index survives migration.  
VM Index  16-bit integer  VM index identifies a VM within a TD.  
• VM index 0 identifies the L1 VMM.  
• VM indices higher than 0 identify L2 VMs.  
 
18.6. Metadata Access Interface  10 
18.6.1.  Introduction  
Metadata access interface  is the architecture that allows representing TD X metadata , i.e., TD non -memory state and TDX 
module control state,  in a way that is independent of the way it is stored .  It does this by hiding  the memory format  of 
TDX control structures  and a llow ing abstraction of data , as follows:  
• The actual fields stored in the TD control structures may be different than their abstracted  representation.  E.g., a 15 
TDVPS field may be provided as a GPA to TDH.VP.WR, while internally stored as an HPA.

TDVPS field may be provided as a GPA to TDH.VP.WR, while internally stored as an HPA.  
• Access to a TD metadata field may trigger some operation .  E.g., writing the TD VMCS’s “p osted -interrupt descriptor 
address ” control triggers the verification of related control and may enable posted interrupt handling.  
• TD metadata fields may be completely virtual , i.e., there may be no actual control structure fields represented by 
them . 20 Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 150 of 153 
Section 2:  Intel TDX Module Architecture Specification  Metadata abstraction  is used in the following cases:  
• Read of TDX Module information by the host VMM and guest TD using the following SEAMCALL and TDCALL 
functions:  
o Single Field Read:  TDH.SYS.RD, TDG.SYS.RD  
o All Fields Read:  TDH.SYS.RDALL, TDG.SYS.RDALL  5 
• Read and write of TDR, TDCS and TDVPS control structures by the host VMM using the following SEAMCALL functions:  
o Single Field Access:  TDH.MNG.RD, TDH.MNG.WR , TDH.VP.RD, TDH.VP.WR  
• Read and write of TDR, TDCS and TDVPS control structures by the guest TD using the following TDCALL functions:  
o Single Field Access:  TDG.VM.RD, TDG.VM.WR, TDG.VP.RD, TDG.VP.WR  
• Read and write of TDR and TDCS a service TD using the following TDCALL functions:  10 
o Single Field Access:  TDG.SERVTD.RD, TDG.SERVTD.WR  
• For TD migration , export and import of TD metadata by the host VMM using the following SEAMCALL functions:  
o State Export:  TDH.EXPORT.STATE.IMMUTABLE, TDH.EXPORT.STATE.TD, TDH.EXPORT.STATE.VP  
o State Import:  TDH.IMPORT.STATE.IMMUTABLE, TDH.IMPORT.STATE.TD , TDH.IMPORT.STATE.VP  
18.6.2.  Metadata Fields  and Elements  15 
Metadata fields are identified by field identifiers  (MD_FIELD_ID) .  A field identifier contains a FIELD_CODE  and other 
information .  A detailed description and MD_FIELD_ID values are defined in tables provided in the [ TDX Module ABI Spec ].  
Metadata fields size may be up to 128 bytes.  
For the purpose of metadata abstraction interface , fields are divided into multiple field elements ; the size of each 
element can be 1, 2, 4 or  8 bytes.  Elements in a field have  consecutive field codes , incremented by 1 or 2 as encoded in 20 
by the field identifier’s INC_SIZE.  
Figure 18.1 below  shows an e xample  of a SHA384 fields (e.g., TDCS. MRCONFIGID ), whose size is 48B .  When access using 
the metadata access functions, th is field is divided into six 8 -byte elements.  
  Element 0  Element 1  Element 2  Element 3  Element 4  Element 5  
FIELD_ CODE  X X + 1 X + 2 X + 3 X + 4 X + 5 
Content  Bytes 7:0  Bytes 15:8  Bytes 23:16  Bytes 31:24  Bytes 39:32  Bytes 4 7:40 
Figure 18.1:  Example of a 48 Byte TDCS.MRCONFIGID Field Composed of Six 8 Byte Elements  
A detailed definition of a field identifier is provided in the [ TDX Module ABI Spec ]. 25 
18.6.3.  Arrays of Metadata Fields  
Metadata fields can be organized in arrays.  Figure 18.2 below  shows an example of an array of 4 fields, each composed 
of 1 element.  In this case, fields in the array have consecutive field codes, incremented by 1 or 2 as encoded in by the 
field identifier’s INC_SIZE field.  
Array 
Index  Field 
Code  Content  
0 X + 0  Array[0]  
1 X + 1  Array[ 1] 
2 X + 2  Array[ 2] 
3 X + 3  Array[ 3] 
Figure 18.2:  Example of an Array of 4 Single -Element Fields  30 
Figure 18.3 below  shows an example where each field is composed of multiple elements.  TDCS.RTMR is such a case.  The 
base FIELD_ID of each field in the array is incremented by the number of elements in each field, multiplied by  1 or 2 as 
encoded in by the field identifie r’s INC_SIZE field.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 151 of 153 
Section 2:  Intel TDX Module Architecture Specification  Array 
Index Base 
FIELD_ID  Element 0’s 
FIELD_ID  Element 1’s 
FIELD_ID  Element 2’s 
FIELD_ID  Element 3’s 
FIELD_ID  Element 4’s 
FIELD_ID  Element 5’s 
FIELD_ID  
0 X + 0 X + 0 X + 1 X + 2 X + 3 X + 4 X + 5 
1 X + 6 X + 6 X + 7 X + 8 X + 9 X + 10 X + 11 
2 X + 12 X + 12 X + 13 X + 14 X + 15 X + 16 X + 17 
3 X + 18 X + 18 X + 19 X + 20 X + 21 X + 22 X + 23 
Figure 18.3:  Example of an Array of Four 48 Byte  TDCS.RTMR Fields, Each Composed of  6 Elements  
18.6.4.  Metadata Field Sequences  
Field sequences  contain one or more whole metadata fields , each composed of one or more elements .   A sequence is 
composed of a sequence  header and one or more values.  
• All fields in a sequence have the same CONTEXT_CODE, CLASS_CODE and field size (i.e., the same number of 5 
elements and the same element size).  
• Each element is a sequence occupies 8 bytes, even if its size is 1, 2 or 4 bytes.  When a sequence is used as an output 
of the TDX module, the upper bytes beyond the element size are zeroed out .  When a sequence is used as an input 
of the TDX module, the upper bytes are ignored.  
• The FIELD_CODE s of each element  in a sequence are consecutive.  10 
• A field sequence may contain a write mask , which applies to each element  value  in the sequence .  This is applicable 
when the sequence is used for writing bit fields, e.g., VMCS execution controls.  
• A sequence always contains whole fields, i.e., if a field is composed of multiple elements, the sequence contains all 
of them.  
A field sequence header  contains the initial field code and other information – for a detailed description see the [ TDX 15 
←−−−−−−−−−−−−−−−−−  64 bits −−−−−−−−−−−−−−−− −→ 
SEQUENCE_HEADER(LAST_ FIELD_IN_SEQUENCE  = 0) 
FIELD[0] / ELEMENT[0]  
FIELD[0] / ELEMENT[1]  
 
FIELD[0] / ELEMENT[LAST_ELEMENT_IN_FIELD]  
Figure 18.4:  Example of a Metadata Field Sequence with One Field Composed of Multiple Elements  
November 2023   . Page 152 of 153 
Section 2:  Intel TDX Module Architecture Specification  ←−−−−−−−−−−−−−−−−−  64 bits −−−−−−−−−−−−−−−− −→ 
SEQUENCE_HEADER(LAST_ FIELD_IN_SEQUENCE  = 1) 
 
FIELD[1] / ELEMENT[0]  
FIELD[1] / ELEMENT[1]  
 
FIELD[1] / ELEMENT[LAST_ELEMENT_IN_FIELD]  
Figure 18.5:  Example of a Metadata Field Sequence with 2 Fields Composed of Multiple Elements  
 
SEQUENCE_HEADER(LAST_ FIELD_IN_SEQUENCE  = 7) 
FIELD[2] / ELEMENT[0]  
 
FIELD[7] / ELEMENT[0]  
Figure 18.6:  Example of a Metadata Field Sequence with 7 Fields Composed of a Single Element  
 
SEQUENCE_HEADER(LAST_ FIELD_IN_SEQUENCE  = 3, 
WRITE_MASK_VALID = 1) 
WRITE_MASK  
FIELD[3] / ELEMENT[0]  
Figure 18.7:  Example of a Metadata Field Sequence with a Write Mask  5 
18.6.5.  Metadata Lists  
A metadata list is composed of a list header and one or more field sequences.  The list header specifies list buffer size in 
bytes and the number of sequences.   Metadata lists are used, e.g., for exporting VCPU metadata by 
THD.EXPORT.STATE.VP.  Intel® TDX Module Base Spec  Section 2:  Intel TDX Module Architecture Specification  348549 -003US  
November 2023   . Page 153 of 153 
Section 2:  Intel TDX Module Architecture Specification  List Header  LIST_HEADER(SIZE = s, NUM_SEQUENCES = 3)  
Multi -Field  
Sequence  SEQUENCE_HEADER(LAST_ FIELD_IN_SEQUENCE  = 2) 
FIELD[ 2] / ELEMENT[0]  
 FIELD[ 2] / ELEMENT[1]  
Single -Field  
Sequence  SEQUENCE_HEADER( LAST_ FIELD_IN_SEQUENCE  = 0) 
 FIELD[0] / ELEMENT[1]  
Sequence with a 
Write Mask  SEQUENCE_HEADER( LAST_ FIELD_IN_SEQUENCE  = 3, 
WRITE_MASK_VALID = 1)  
FIELD[ 3] / ELEMENT[0]  
Figure 18.8:  Metadata List Example  
The metadata list header format is defined in the [ TDX Module ABI Spec ]. 
18.7. Latency of the Intel TDX Interface Functions  
The Intel TDX module runs with interrupts disabled (including NMI and SMI).  To support proper system responsiveness, 
most TDX module interface functions are designed to have a short latency.  However, there are infrequent cases where 5 
the latency of some interface functions may be longer than normal, as listed below.  
• Host -side interface functions that are invoked a limited number of times during TDX module lifecycle.  The interface 
functions below are known to have longer than normal latencies:  
o TDH.SYS.INIT  
o TDH.SYS.LP.INIT  10 
o TDH.SYS.KEY.CONFIG  
• Host -side interface functions that are invoked a limited number of times during TD lifetime.  The interface functions 
below are known to have longer than normal latencies:  
o TDH.MNG.KEY.CONFIG  
o TDH.MNG.INIT  15

o TDH.MNG.INIT  15 
o TDH.VP.INIT  
• TDH.VP.ENTER may have a long latency if the single/zero step attack mitigation (described in 17.3 ) is activated due 
to a suspected attack.  
18.8. DRNG Entropy Errors  
Multiple TDX module interface functions may use the CPU’s digital random number generation (DRNG) facility, via the 20 
RDSEED, RDRAND and PCONFIG instructions.  Such interface functions may fail on entropy errors due to the inability of 
the DRNG to generate random values at the requested rate, returning a TDX_RND_NO_ENTROPY or a similar status code.  
This may happen where,  e.g., software running on other LPs in the same package also executes RDSEED at a high rate.  
  
Architecture Application Binary Interface (ABI) 
Reference Specification  
 
348551 -003US 
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November 2023  . Page 2 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Notices and Disclaimers  
   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 3 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table of Contents  
1. About this Document  ................................ ................................ ................................ ................................ ............  7 
1.1. Scope of this Document  ................................ ................................ ................................ ................................ ........  7 
1.2. Glossary ................................ ................................ ................................ ................................ ................................ . 7 
1.3. Notation  ................................ ................................ ................................ ................................ ................................  7 5 
1.4. References  ................................ ................................ ................................ ................................ .............................  8 
2. CPU Virtualization Tables  ................................ ................................ ................................ ................................ ...... 9 
2.1. MSR Virtualization  ................................ ................................ ................................ ................................ ................  9 
2.2. CPUID Virtualization  ................................ ................................ ................................ ................................ ..............  9 
3. Data Types  ................................ ................................ ................................ ................................ ...........................  10 10 
3.1. Interface Function Completion Status  ................................ ................................ ................................ .................  10 
3.1.1.  Function Completion Status Structure  ................................ ................................ ................................ ........  10 
3.1.2.  Function Completion Status Code Classes (Bits 47:40)  ................................ ................................ ...............  11 
3.1.3.  Function Completion Status Codes and Operand IDs  ................................ ................................ .................  11 
3.2. Basic Crypto Types  ................................ ................................ ................................ ................................ ..............  11 15 
3.3. TDX Module Configuration, Enumeration and Initialization Types  ................................ ................................ ..... 12 
3.3.1.  CPUID_CONFIG ................................ ................................ ................................ ................................ ............  12 
3.3.2.  TDX Module Version  ................................ ................................ ................................ ................................ ... 12 
3.3.3.  Global -Scope (TDX Module) Metadata  ................................ ................................ ................................ .......  12 
3.3.3.1.  TDX Features Enumeration  ................................ ................................ ................................ .................  13 20 
3.3.3.2.  Global Metadata Fields  ................................ ................................ ................................ .......................  15 
3.3.4.  CMR_INFO  ................................ ................................ ................................ ................................ ...................  15 
3.3.5.  TDSYSINFO_STRUCT  ................................ ................................ ................................ ................................ .... 15 
3.3.6.  TDMR_INFO  ................................ ................................ ................................ ................................ ................  17 
3.4. TD Parameter Types  ................................ ................................ ................................ ................................ ............  19 25 
3.4.1.  ATTRIBUTES  ................................ ................................ ................................ ................................ .................  19 
3.4.2.  XFAM  ................................ ................................ ................................ ................................ ...........................  21 
3.4.3.  CONFIG_FLAGS  ................................ ................................ ................................ ................................ ............  21 
3.4.4.  CPUID_VALUES  ................................ ................................ ................................ ................................ ............  22 
3.4.5.  TD_PARAMS  ................................ ................................ ................................ ................................ ................  23 30 
3.5. Physical Memory Management Types  ................................ ................................ ................................ ................  25 
3.5.1.  PAMT Page Type (PT) Values  ................................ ................................ ................................ ......................  25 
3.5.2.  Physical Page Size ................................ ................................ ................................ ................................ ........  26 
3.6. TD Private Memory Management Data Types:  Secure EPT  ................................ ................................ ...............  26 
3.6.1.  Secure EPT Levels  ................................ ................................ ................................ ................................ ........  26 35

3.6.1.  Secure EPT Levels  ................................ ................................ ................................ ................................ ........  26 35 
3.6.2.  Secure EPT Entry Information as Returned by TDX Module Functions ................................ .......................  26 
3.6.2.1.  Returned L1  Secure EPT Entry Content  ................................ ................................ ...............................  26 
3.6.2.2.  Returned L2 Secure EPT Entry Content  ................................ ................................ ...............................  27 
3.6.2.3.  Additional  Returned Secure EPT Information  ................................ ................................ .....................  28 
3.6.3.  GPA_ATTR:  GPA Attributes  ................................ ................................ ................................ ........................  30 40 
3.6.3.1.  GPA Attributes Rules  ................................ ................................ ................................ ...........................  31 
3.6.4.  GLA List  ................................ ................................ ................................ ................................ .......................  31 
3.6.4.1.  GLA_LIST_ENTRY  ................................ ................................ ................................ ................................ . 31 
3.6.4.2.  GLA_LIST  ................................ ................................ ................................ ................................ .............  31 
3.6.4.3.  GLA_LIST_INFO:  GLA List GPA and Additional Information  ................................ ...............................  31 45 
3.7. TD Entry and Exit  Types  ................................ ................................ ................................ ................................ ...... 32 
3.7.1.  Extended Exit Qualification  ................................ ................................ ................................ .........................  32 
3.8. L2 VM Transition Types  ................................ ................................ ................................ ................................ .......  33 
3.8.1.  L2_ENTER_GUEST_STATE  ................................ ................................ ................................ ...........................  33  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 4 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3.9. Measurement and Attestation Types  ................................ ................................ ................................ ..................  34 
3.9.1.  CPUSVN  ................................ ................................ ................................ ................................ .......................  34 
3.9.2.  TDREPORT_STRUCT  ................................ ................................ ................................ ................................ ..... 34 
3.9.3.  TEE_TCB_INFO (Reference)  ................................ ................................ ................................ .........................  35 
3.9.4.  TEE_TCB_SVN (Reference)  ................................ ................................ ................................ ..........................  35 5 
3.9.5.  REPORTMACSTRUCT (Reference)  ................................ ................................ ................................ ...............  35 
3.9.6.  REPORTTYPE (Reference)  ................................ ................................ ................................ ............................  36 
3.9.7.  TDINFO_STRUCT  ................................ ................................ ................................ ................................ .........  37 
3.10.  Metadata Access Types  ................................ ................................ ................................ ................................ ... 38 
3.10.1.  MD_FIELD_ID:  Metadata Field Identifier / Sequence Header  ................................ ................................ ... 38 10 
3.10.2.  Meaning of Field Codes ................................ ................................ ................................ ...............................  39 
3.10.3.  Class Codes ................................ ................................ ................................ ................................ ..................  41 
3.10.3.1.  TDX Module Global Scope Field Class Codes  ................................ ................................ ......................  41 
3.10.3.2.  TD-Scope (TDR and TDCS) Field Class Codes  ................................ ................................ .......................  41 
3.10.3.3.  VCPU -Scope (TDVPS) Field Class Codes  ................................ ................................ ..............................  42 15 
3.10.4.  Order of Field Identifiers  ................................ ................................ ................................ .............................  42 
3.10.5.  MD_LIST_HEADER:  Metadata List Header  ................................ ................................ ................................ . 42 
3.10.6.  Private Page List  ................................ ................................ ................................ ................................ ..........  43 
3.10.7.  HPA_AND_SIZE:  HPA and Size of a Buffer  ................................ ................................ ................................ .. 43 
3.10.8.  HPA_AND_LAST:  HPA and Last Byte Index of a Page -Aligned Buffer  ................................ .........................  43 20 
3.11.  Service TD Types  ................................ ................................ ................................ ................................ ..............  44 
3.11.1.  SERVTD_BINDING_TABLE:  Service TD Binding Table  ................................ ................................ .................  44 
3.11.2.  SERVTD_BINDING_STATE:  Service TD Binding State  ................................ ................................ ..................  44 
3.11.3.  SERVTD_TYPE:  Service TD Binding Type  ................................ ................................ ................................ ..... 44 
3.11.4.  SERVTD_ATTR:  Service TD Binging Attributes  ................................ ................................ ............................  45 25 
3.12.  Migration Types  ................................ ................................ ................................ ................................ ..............  46 
3.12.1.  MBMD:  Migration Bundle Metadata  ................................ ................................ ................................ .........  46 
3.12.1.1.  Generic MBMD Structure  ................................ ................................ ................................ ....................  46 
3.12.1.2.  TD-Scope Immutable Non -Memory State MBMD Fields  ................................ ................................ .... 47 
3.12.1.3.  TD-Scope Mutable Non -Memory State MBMD Fields  ................................ ................................ ........  47 30 
3.12.1.4.  VCPU -Scope Mutable Non -Memory State MBMD Fields  ................................ ................................ .... 47 
3.12.1.5.  TD Private Memory MBMD Fields  ................................ ................................ ................................ .......  47 
3.12.1.6.  Epoch Token MBMD Fields  ................................ ................................ ................................ .................  48 
3.12.1.7.  Abort Token MBMD Fields  ................................ ................................ ................................ ..................  48 
3.12.1.8.  TD Migration Protocol Version Compatibility  ................................ ................................ .....................  48 35 
3.12.2.  GPA List  ................................ ................................ ................................ ................................ .......................  48 
3.12.2.1.  GPA_LIST_INFO:  HPA, First and Last Entries of a GPA List  ................................ ................................ . 48 
3.12.2.2.  GPA List Entry  ................................ ................................ ................................ ................................ ...... 49 
3.12.2.3.  GPA List Entry Details  ................................ ................................ ................................ ..........................  49 
3.12.2.4.  TD Migration Protocol Version Compatibility  ................................ ................................ .....................  51 40 
3.12.3.  Memory Migration Buffers List  ................................ ................................ ................................ ...................  52

3.12.3.  Memory Migration Buffers List  ................................ ................................ ................................ ...................  52 
3.12.3.1.  Migration Buffers List Entry  ................................ ................................ ................................ ................  52 
3.12.4.  Page Attributes List  ................................ ................................ ................................ ................................ ..... 52 
3.12.5.  Memory Migration Page MAC List  ................................ ................................ ................................ ..............  52 
3.12.6.  Non -Memory State Migration Buffers List  ................................ ................................ ................................ .. 52 45 
3.12.6.1.  PAGE_LIST_INFO:  HPA and Attributes of a Page List  ................................ ................................ .........  52 
4. TD Metadata (Non -Memory State)  ................................ ................................ ................................ ......................  54 
4.1. TD-Scope Metadata  ................................ ................................ ................................ ................................ ............  54 
4.1.1.  TDR ................................ ................................ ................................ ................................ ..............................  54 
4.1.2.  TDCS  ................................ ................................ ................................ ................................ ............................  54 50 
4.1.2.1.  TDCS.TD_CTLS  ................................ ................................ ................................ ................................ ..... 55 
4.2. TDVPS:  VCPU -Scope Metadata  ................................ ................................ ................................ ..........................  55 
4.2.1.  Overview  ................................ ................................ ................................ ................................ .....................  56 
4.2.2.  TDVPS (excluding TD VMCS)  ................................ ................................ ................................ .......................  56 
4.2.3.  TD (L1) VMCS and L2 VMCS  ................................ ................................ ................................ ........................  56 55 
4.2.3.1.  TD VMCS CR4 Guest/Host Mask  ................................ ................................ ................................ .........  56  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
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Intel TDX Application Binary Interface (ABI) Reference  5. Interface Functions  ................................ ................................ ................................ ................................ ..............  58 
5.1. How to Read the Interface Function Definitions  ................................ ................................ ................................ . 58 
5.2. Common Algorithms Used by Multiple Interface Functions  ................................ ................................ ................  58 
5.2.1.  VCPU Association with an LP  ................................ ................................ ................................ ......................  58 
5.2.2.  Metadata Access  ................................ ................................ ................................ ................................ .........  59 5 
5.2.2.1.  Single Metadata Field Read  ................................ ................................ ................................ ................  59 
5.2.2.2.  Single Metadata Field Write  ................................ ................................ ................................ ...............  59 
5.2.2.3.  Multiple Metadata Fields Write based on a Metadata List  ................................ ................................  59 
5.3. Host -Side (SEAMCALL) Interface Functions  ................................ ................................ ................................ .........  61 
5.3.1.  SEAMCALL Instruction (Common)  ................................ ................................ ................................ ...............  61 10 
5.3.2.  TDH.EXPORT.ABORT Leaf  ................................ ................................ ................................ ............................  64 
5.3.3.  TDH.EXPORT.BLOCKW Leaf  ................................ ................................ ................................ .........................  67 
5.3.4.  TDH.EXPORT.MEM Leaf  ................................ ................................ ................................ ..............................  70 
5.3.5.  TDH.EXPORT.PAUSE Leaf  ................................ ................................ ................................ ............................  75 
5.3.6.  TDH.EXPORT.RESTORE Leaf  ................................ ................................ ................................ ........................  77 15 
5.3.7.  TDH.EXPORT.STATE.IMMUTABLE Leaf  ................................ ................................ ................................ ........  80 
5.3.8.  TDH.EXPORT.STATE.TD Leaf  ................................ ................................ ................................ ........................  85 
5.3.9.  TDH.EXPORT.STATE.VP Leaf  ................................ ................................ ................................ ........................  89 
5.3.10.  TDH.EXPORT.TRACK Leaf  ................................ ................................ ................................ ............................  93 
5.3.11.  TDH.EXPORT.UNBLOCKW Leaf  ................................ ................................ ................................ ....................  96 20 
5.3.12.  TDH.IMPORT.ABORT Leaf  ................................ ................................ ................................ ...........................  99 
5.3.13.  TDH.IMPORT.COMMIT Leaf  ................................ ................................ ................................ ......................  102 
5.3.14.  TDH.IMPORT.END Leaf  ................................ ................................ ................................ ..............................  104 
5.3.15.  TDH.IMPORT.MEM Leaf  ................................ ................................ ................................ ............................  106 
5.3.16.  TDH.IMPORT.STATE.IMMUTABLE Leaf  ................................ ................................ ................................ ..... 113 25 
5.3.17.  TDH.IMPORT.STATE.TD Leaf  ................................ ................................ ................................ .....................  118 
5.3.18.  TDH.IMPORT.STATE.VP Leaf  ................................ ................................ ................................ .....................  122 
5.3.19.  TDH.IMPORT.TRACK Leaf  ................................ ................................ ................................ ..........................  126 
5.3.20.  TDH.MEM.PAGE.ADD Leaf  ................................ ................................ ................................ ........................  129 
5.3.21.  TDH.MEM.PAGE.AUG Leaf  ................................ ................................ ................................ ........................  132 30 
5.3.22.  TDH.MEM.PAGE.DEMOTE Leaf  ................................ ................................ ................................ .................  135 
5.3.23.  TDH.MEM.PAGE.PROMOTE Leaf  ................................ ................................ ................................ ...............  141 
5.3.24.  TDH.MEM.PAGE.RELOCATE Leaf  ................................ ................................ ................................ ...............  147 
5.3.25.  TDH.MEM.PAGE.REMOVE Leaf  ................................ ................................ ................................ .................  150 
5.3.26.  TDH.MEM.RANGE.BLOCK Leaf  ................................ ................................ ................................ ..................  153 35 
5.3.27.  TDH.MEM.RANGE.UNBLOCK Leaf  ................................ ................................ ................................ .............  156 
5.3.28.  TDH.MEM.RD Leaf  ................................ ................................ ................................ ................................ .... 159 
5.3.29.  TDH.MEM.SEPT.ADD Leaf  ................................ ................................ ................................ .........................  162 
5.3.30.  TDH.MEM.SEPT.RD Leaf  ................................ ................................ ................................ ............................  168

5.3.30.  TDH.MEM.SEPT.RD Leaf  ................................ ................................ ................................ ............................  168 
5.3.31.  TDH.MEM.SEPT.REMOVE Leaf  ................................ ................................ ................................ ..................  172 40 
5.3.32.  TDH.MEM.TRACK Leaf  ................................ ................................ ................................ ..............................  176 
5.3.33.  TDH.MEM.WR Leaf  ................................ ................................ ................................ ................................ ... 178 
5.3.34.  TDH.MIG.STREAM.CREATE Leaf  ................................ ................................ ................................ ................  181 
5.3.35.  TDH.MNG.ADDCX Leaf  ................................ ................................ ................................ ..............................  183 
5.3.36.  TDH.MNG.CREATE Leaf  ................................ ................................ ................................ .............................  185 45 
5.3.37.  TDH.MNG.INIT Leaf  ................................ ................................ ................................ ................................ ... 187 
5.3.38.  TDH.MNG.KEY.CONFIG Leaf  ................................ ................................ ................................ ......................  190 
5.3.39.  TDH.MNG.KEY.FREEID Leaf  ................................ ................................ ................................ .......................  192 
5.3.40.  TDH.MNG.KEY.RECLAIMID Leaf (Deprecated)  ................................ ................................ ..........................  194 
5.3.41.  TDH.MNG.RD Leaf  ................................ ................................ ................................ ................................ ..... 195 50 
5.3.42.  TDH.MNG.VPFLUSHDONE Leaf  ................................ ................................ ................................ .................  198 
5.3.43.  TDH.MNG.WR Leaf  ................................ ................................ ................................ ................................ .... 200 
5.3.44.  TDH.MR.EXTEND Leaf  ................................ ................................ ................................ ...............................  202 
5.3.45.  TDH.MR.FINALIZE Leaf  ................................ ................................ ................................ ..............................  205 
5.3.46.  TDH.PHYMEM.CACHE.WB Leaf  ................................ ................................ ................................ .................  207 55 
5.3.47.  TDH.PHYMEM.PAGE.RDMD Leaf  ................................ ................................ ................................ ..............  210 
5.3.48.  TDH.PHYMEM.PAGE.RECLAIM Leaf  ................................ ................................ ................................ ..........  212 
5.3.49.  TDH.PHYMEM.PAGE.WBINVD Leaf  ................................ ................................ ................................ ...........  215  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 6 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.50.  TDH.SERVTD.BIND Leaf  ................................ ................................ ................................ .............................  217 
5.3.51.  TDH.SERVTD.PREBIND Leaf  ................................ ................................ ................................ .......................  220 
5.3.52.  TDH.SYS.CONFIG Leaf  ................................ ................................ ................................ ................................  223 
5.3.53.  TDH.SYS.INFO Leaf  ................................ ................................ ................................ ................................ .... 226 
5.3.54.  TDH.SYS.INIT Leaf  ................................ ................................ ................................ ................................ ...... 228 5 
5.3.55.  TDH.SYS.KEY.CONFIG Leaf  ................................ ................................ ................................ .........................  231 
5.3.56.  TDH.SYS.LP.INIT Leaf  ................................ ................................ ................................ ................................ . 233 
5.3.57.  TDH.SYS.LP.SHUTDOWN Leaf (Deprecated)  ................................ ................................ .............................  236 
5.3.58.  TDH.SYS.RD Leaf  ................................ ................................ ................................ ................................ ........  237 
5.3.59.  TDH.SYS.RDALL Leaf  ................................ ................................ ................................ ................................ .. 239 10 
5.3.60.  TDH.SYS.SHUTDOWN Leaf  ................................ ................................ ................................ ........................  241 
5.3.61.  TDH.SYS.TDMR.INIT Leaf  ................................ ................................ ................................ ...........................  243 
5.3.62.  TDH.SYS.UPDATE Leaf  ................................ ................................ ................................ ...............................  245 
5.3.63.  TDH.VP.ADDCX Leaf  ................................ ................................ ................................ ................................ .. 247 
5.3.64.  TDH.VP.CREATE Leaf  ................................ ................................ ................................ ................................ . 249 15 
5.3.65.  TDH.VP.ENTER Leaf  ................................ ................................ ................................ ................................ ... 251 
5.3.66.  TDH.VP.FLUSH Leaf  ................................ ................................ ................................ ................................ ... 261 
5.3.67.  TDH.VP.INIT Leaf  ................................ ................................ ................................ ................................ .......  263 
5.3.68.  TDH.VP.RD Leaf  ................................ ................................ ................................ ................................ .........  266 
5.3.69.  TDH.VP.WR Leaf  ................................ ................................ ................................ ................................ ........  269 20 
5.4. Guest -Side (TDCALL) Interface Functions  ................................ ................................ ................................ ..........  272 
5.4.1.  TDCALL Instruction (Common)  ................................ ................................ ................................ ..................  272 
5.4.2.  TDG.MEM.PAGE.ACCEPT Leaf  ................................ ................................ ................................ ...................  274 
5.4.3.  TDG.MEM.PAGE.ATTR.RD Leaf  ................................ ................................ ................................ .................  277 
5.4.4.  TDG.MEM.PAGE.ATTR.WR Leaf  ................................ ................................ ................................ ................  279 25 
5.4.5.  TDG.MR.REPORT Leaf  ................................ ................................ ................................ ...............................  283 
5.4.6.  TDG.MR.RTMR.EXTEND Leaf  ................................ ................................ ................................ .....................  285 
5.4.7.  TDG.MR.VERIFYREPORT  ................................ ................................ ................................ ............................  287 
5.4.8.  TDG.SERVTD.RD Leaf  ................................ ................................ ................................ ................................ . 289 
5.4.9.  TDG.SERVTD.WR Leaf ................................ ................................ ................................ ................................  293 30 
5.4.10.  TDG.SYS.RD Leaf  ................................ ................................ ................................ ................................ ........  298 
5.4.11.  TDG.SYS.RDALL Leaf  ................................ ................................ ................................ ................................ .. 300 
5.4.12.  TDG.VM.RD Leaf ................................ ................................ ................................ ................................ ........  302 
5.4.13.  TDG.VM.WR Leaf  ................................ ................................ ................................ ................................ ...... 304

5.4.13.  TDG.VM.WR Leaf  ................................ ................................ ................................ ................................ ...... 304 
5.4.14.  TDG.VP.CPUIDVE.SET Leaf  ................................ ................................ ................................ ........................  306 35 
5.4.15.  TDG.VP.ENTER Leaf  ................................ ................................ ................................ ................................ ... 308 
5.4.16.  TDG.VP.INFO Leaf  ................................ ................................ ................................ ................................ ..... 314 
5.4.17.  TDG.VP.INVEPT Leaf  ................................ ................................ ................................ ................................ .. 316 
5.4.18.  TDG.VP.INVGLA Leaf  ................................ ................................ ................................ ................................ . 318 
5.4.19.  TDG.VP.RD Leaf  ................................ ................................ ................................ ................................ .........  321 40 
5.4.20.  TDG.VP.VEINFO.GET Leaf  ................................ ................................ ................................ ..........................  323 
5.4.21.  TDG.VP.VMCALL Leaf  ................................ ................................ ................................ ................................  325 
5.4.22.  TDG.VP.WR Leaf  ................................ ................................ ................................ ................................ ........  328 
  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 7 of 329 
Intel TDX Application Binary Interface (ABI) Reference  1. About this Document  
This document describes the Application Binary I nterface (ABI) of the Intel ® Trust Domain Extensions  (Intel ® TDX) module , 
implemented using  the Intel TDX Instruction Set Architecture (ISA) extension s, for confidential execution of Trust Domains 
in an untrusted hosted cloud environment . 5 
 TDX Module  
 TDX Module  
 TDX Module  
 TDX Module  
 TDX Module  
 
occur.  
See the [ TDX Module Base Spec ].  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 8 of 329 
Intel TDX Application Binary Interface (ABI) Reference  1.4. References  
November 2023  . Page 9 of 329 
Intel TDX Application Binary Interface (ABI) Reference  2. CPU Virtualization Tables  
2.1. MSR Virtualization  
MSR virtualization information is provided in a separate JSON format file msr_virtualization.json . 
2.2. CPUID Virtualization  
CPUID virtualization information is provided in a separate JSON format file cpuid _virtualization.json . 5  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 10 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3. Data Types  
This section describes data types that are designed to be used by the Intel TDX module . 
3.1. Interface Function Completion Status  
Note:  This section provides a high -level overview of function completion status, as defined.  Implementation details 
may differ.  5 
A high -level  definition of the interface functions completion status is provided  in the [ TDX Module Base Spec ]. 
3.1.1.  Function Completion Status Structure  
Table 3.1:  Intel TDX Interface Functions Completion Status (Returned in RAX) Definition  
63 ERROR  Interface function  aborted due to error.  
0: Indicates that the function completed successfully – possibly with 
some warnings.  
1: Indicates that the function aborted due to some error.  
62 NON_RECOVERABLE  Recoverability hint – applicable only when ERROR is 1.  
0: Indicates that the function may possibly be retried after some 
conditions have been corrected.  
FAILED_IMPORT.  
59:48  RESERVED  Reserved – set to 0  
• MSR index  
• CMR index  
• TDMR index   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 11 of 329 
Intel TDX Application Binary Interface (ABI) Reference   
3.1.2.  Function Completion Status Code Classes (Bits 47:40)  
Table 3.2:  Function Completion Status Code Classes (Bits 47:40) Definition  
Class ID  Class Name  Description  
0 General  General function completion status  
1 Invalid Operand  An invalid operand value has been provided, e.g., HKID is out of range, 
HPA overlaps SEAMRR, GPA is not private, etc.  
2 Resource Busy  Resource is busy, there is a concurrency conflict.  
3 Page Metadata  Page metadata (in PAMT) are incorrect, e.g., page type is wrong.  
4 Dependent Resources  The state of dependent resources is incorrect, e.g., there are TD pages 
while trying to reclaim a TDR page.  
5 Intel TDX Module State  The Intel TDX module  state is incorrect.  
6 TD State  The state of the TD is incorrect, e.g., it has not been initialized yet.  
7 TD VCPU State  The state of the TD VCPU is incorrect, e.g., it is corrupted.  
8 Key Management  The status code is related to key management, e.g., keys are not 
configured.  
9 Platform  The status code is related to platform configuration or state.  
10 Physical Memory  The status code is related to physical memory.  
11 Guest TD Memory  The status code is related to guest TD memory.  
12 Metadata  The status code is related to metadata (global scope, TD scope or VCPU 
scope)  
13 Service TD  The status code is related to a service TD  
14 Migration  The status code is related to TD migration  
15 TDX I/O  The status code is related to TDX I/O  
16 Measurement  The status code is related to TDX measurement

scope)  
16 Measurement  The status code is related to TDX measurement  
17 TD Partitioning  The status code is related to TD partitioning  
255  Reserved   Reserved for use by host VMM or guest TD software  
This value is never used by the TDX module.  
 
3.1.3.  Function Completion Status Codes  and Operand IDs  5 
Interface functions completion status codes and operand IDs are provided in a separate JSON format file 
interface_functions_completion_status .json . 
3.2. Basic Crypto Types  
Table 3.3:  Basic Crypto Types  
Name  Size 
SHA384_HASH  48 384-bit buffer containing the result of a SHA384 hash calculation  
KEY128  16 128-bit key   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 12 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Name  Size 
KEY256  32 256-bit key  
 
3.3. TDX Module Configuration, Enumeration and Initialization Types  
Note:  This section describes configuration, enumeration and initialization types, as defined.  Implementation may 
differ.  
3.3.1.  CPUID_CONFIG  5 
CPUID_CONFIG is designed to enumerate how the host VMM may configure the virtualization done by the Intel TDX 
module for a single CPUID leaf and sub -leaf.  An array of CPUID_CONFIG entries is used for the Intel TDX module 
enumeration by TDH.SYS.INFO.  
Table 3.4:  CPUID_ CONFIG  Definition  
LEAF  0 4 EAX input value to CPUID  
SUB_LEAF  4 4 ECX input value to CPUID  
A value of -1 indicates a CPUID leaf with no sub -leaves.  
EAX  8 4 Enumeration of the configurable virtualization of the value returned by CPUID in 
EAX:  a value of 1 in any of the bits indicates that the host VMM is allowed to 
configure that bit  
EBX 12 4 Enumeration of the configurable virtualization of the value returned by CPUID in 
EBX:  a value of 1 in any of the bits indicates that the host VMM is allowed to 
ECX 16 4 Enumeration of the configurable virtualization of the value returned by CPUID in 
ECX:  a value of 1 in any of the bits indicates that the host VMM is allowed to 
EDX  20 4 Enumeration of the configurable virtualization of the value returned by CPUID in 
EDX:  a value of 1 in any of the bits indicates that the host VMM is allowed to 
 10 
3.3.2.  TDX Module Version  
The TDX module version number is enumerated as four fields:  
• MINOR_VERSION  
• MAJOR_VERSION  
• UPDATE_VERSION  15 
• INTERNAL_VERSION  
Each of the fields is a 16 -bit unsigned integer.  The version number can be written as 
<Major>.<Minor>.<Update>.<Internal>, e.g., 1.5.05.01.  
3.3.3.  Global -Scope (TDX Module) Metadata  
TDX module global scope fields provide enumeration information about the Intel TDX module.  They are used with the 20 
TDH.SYS.RD, TDH.SYS.RDALL, TDG.SYS.RD and TDG.SYS.RDALL functions.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 13 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3.3.3.1.  TDX Features Enumeration  
The main enumeration of features supported by the TDX module is provided by the TDX_FEATURES array of 64 -bit 
metadata fields.  The number of fields is enumerated by NUM_TDX_FEATURES . 
The TDX module features of TDX 1.0 are considered a baseline.  TDX_FEATURES enumerate features beyond that baseline.  
Table 3.5:  TDX_FEATURES0 Definition  5 
0 TD_MIGRATION  The TDX module supports TD migration.  Further information is provided 
by the Migration fields.  
1 TD_PRESERVING  The TDX module supports TD preserving updates.  Further information is 
provided by the TDX Module Handoff metadata fields.  
2 SERVICE_TD  The TDX module supports Service TDs.  Further information is provided by 
the Service TD fields.  
3 ENHANCED_METADATA  The TDX module supports enhanced metadata interface functions:  
• Version 1 of previously existing functions:  TDH.MNG.RD, TDH.VP.RD  
and TDG.VM.RD . 
• New functions:  TDH.SYS.RD, TDH.SYS.RDALL, TDG.SYS.RD, 
TDG.SYS.RDALL, TDG.VP.RD /WR.  
4 RELAXED_MEM_M NG The TDX module’s memory management requirements are relaxed vs. TDX 
1.0: 
• Many interface functions allow concurrent memory management 
operations  by exclusively locking specific Secure EPT entries instead 
of the whole Secure EPT tree:  
o TDH.MEM.PAGE.AUG/DEMOTE/PROMOTE/RELOCATE/REMOVE  
o TDH.MEM.SEPT.ADD  
• TLB tracking (e.g., TDH.MEM.RANGE.BLOCK followed by 
TDH.MEM.TRACK and IPIs) may be skipped if the TD’s OP_STATE is 
such that the TD can’t be running, i.e., in the following cases:  
o On normal TD build, the TD’s measurement has not yet been 
finalized by TDH.MR.FINALIZED.  
o The TD has been paused for export by TDH.EXPORT.PAUSE, and 
export has not been aborted by TDH.EXPOR.ABORT.  
o On import, TD execution has been enabled by 
TDH.IMPORT.COMMIT or TDH.IMPORT.END.  
5 CPUID_VIRT_ GUEST_ CTRL  Guest TD may request that on certain CPUID leaves/sub -leaves a #VE will 
always be injected, using the TDG.VP.RD/WR to access the TDVPS’ 
CPUID_CONTROL fields.  
6 TDX_ CONNECT  The TDX module and the CPU support TDX Connect . 
7 TD_PARTITIONING  The TDX module supports TD partitioning : 
• New interface functions:  TDG.MEM,PAGE.ATTR.RD/WR, 
TDG.VP.ENTER, TDG.VP.INVEPT, TDG.VP.INVGLA  
• Version 1 of existing interface functions:  TDH.MEM.PAGE.PROMOTE, 
TDH.MEM.SEPT.ADD, TDH.MEM.SEPT.REMOVE  
• Backward -compatible u pdates to existing  interface functions, with 
new input and/or output operands . 
8 LOCAL_ATTESTATION  The TDX module supports local attestation : 
• New interface function:  TDG.MR.VERIFYREPORT   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 14 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Bit(s) Name  Description  
9 TD_ENTRY_ENHANCEMENTS  The TDX module supports the following TD entry enhancements:  
• HOST_RECOVERABILITY_HINT:  On  trap -like asynchronous TD exit, bit 
60 of the TDH.VP.ENTER completion status (returned in RAX) may be  
set to 1 .  In this case, the host VMM may set the following TD entry’s 
input value of RCX ’ HOST_RECOVERABILITY_HINT bit; this bit is copied 
to the guest RAX bit 60, which the guest interprets as part of a 
TDCALL completion status.   
10 HOST_PRIORITY_LOCKS  The TDX module implements host -priority locks to avoid denial -of-service 
by guest TDs.  This requires the host VMM to retry operations that fail 
with a TDX_OPERAND_BUSY status.  
11 CONFIG_IA32_ARCH_CAPABILITIES  The TDX module allows the host VMM to configure the virtualization of 
IA32_ARCH_CAPABILITIES MSR.  
12 TDX_SEAL_KEYS  The TDX module supports signed TDs and seal keys bound to new TD 
• New TD_PARAMS fields  
• New interface functions:  TDG.MR.ASSIGNSVNS , TDG. MR.KEY.GET  
13 S4 The TDX module supports state hibernation and restoration across S4 CPU 
state:  
• New interface function:  TDH.SYS.S4_END  
• New input flag to TDH.EXPORT/IMPORT.STATE.IMMUTABLE  
14 ACT The TDX module manages memory access control using the CPU’s Access 
Control Table (ACT).  This implies the following:  
• Changes to the TDX module initialization sequence, including new 
interface function s TDH.SYS.PHYMEM.INIT and TDH. SYS.CACHE.WB.  
• Changes to memory management, including a new interface function 
TDH. PHY MEM.PAGE.RELEASE.  
15 WBINVD_DOMAINS  TDH.PHYMEM.CACHE.WB and TDH.SYS.CACHE.WB need to be called per 
WBINVD domain that might be different than a whole package.  WBINVD 
domains are enumerated with the WBINVD_DOMAIN* metadata fields.  
16 PENDING_EPT_VIOLATION_V2  The TDX module supports enhanced handling of EPT violation on guest TD 
access to PENDING pages:  
• Decision on whether a #VE is injected to the guest TD can be guest 
configurable.  
• Extended exit qualification is provided to the host VMM.  
• EPT violation on L2 VM access to a PENDING page always causes an 
L2→L1 exit.  
17 FMS_CONFIG  The TDX module supports configuration of virtual CPUID(1).EAX 
(Family/Model/Stepping) value for migratable TDs.  
18 NO_RBP_MOD  The TDX module supports a TD configuration where RBP is never modified 
by any host -side (SEAMCALL) and guest -side (TDCALL) interface function.  
This is configured by TD_PARAMS.CONFIG_FLAGS.NO_RBP_MOD (see 
3.4.3 ). 
19 L2_TLB_INV D_OPT  The TDX module supports additional address translation invalidation 
modes on TDG.VP.ENTER.  
20 TOPOLOGY_ENUM  The TDX module supports virtual topology enumeration and configuration 
of CPUID(0xB), CPUID(0x1F) and x2APIC ID.  
63:21 RESERVED  Set to 0  
November 2023  . Page 15 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3.3.3.2.  Global Metadata Fields  
Global metadata information is provided in a separate JSON format file global_metadata .json . 
3.3.4.  CMR_INFO  
CMR_INFO is designed to provide information about a Convertible Memory Range (CMR), as configured by BIOS and 
checked and stored securely by MCHECK.  5

3.4.3 ). 
checked and stored securely by MCHECK.  5 
Note:  CMR_INFO and TDH.SYS.INFO are provided for backward compatibility.  TDH.SYS.RDALL is the recommended 
method to read Intel TDX module information.  See also 3.3.3 above . 
Table 3.6:  CMR_INFO Entry Definition  
Name  Offset 
(Bytes)  Type  Size 
CMR_BASE  0 Physical 
Address  8 Base address of the CMR:  since a CMR is aligned on 4KB, bits 
11:0 are 0.  
CMR_SIZE  8 Integer  8 Size of the CMR, in bytes:  since a CMR is aligned on 4KB, bits 
11:0 are 0.  
A value of 0 indicates a null entry.  
 
TDH.SYS.INFO leaf function returns an array of CMR_INFO entries.  The CMRs are sorted from the lowest base address to 10 
the highest base address, and they are non -overlapping.  
3.3.5.  TDSYSINFO_STRUCT  
TDSYSINFO_STRUCT is designed to provide enumeration information about the Intel TDX module.  It  is an output of the 
TDH.SYS.INFO leaf function . 
Note:  TDSYSINFO_STRUCT and TDH.SYS.INFO are provided for backward compatibility.  TDH.SYS.RDALL is the 15 
recommended method to read Intel TDX module information.  See also 3.3.3 above . 
TDSYSINFO_STRUCT’s size is 1024B.  
Table 3.7:  TDSYSINFO_STRUCT Definition  
Section  Field Name  Offset 
Intel TDX 
Module 
Info  ATTRIBUTES  0 Bitmap  4 Module attributes  
Bits 30:0  Reserved – set to 0  
Bit 31  0 indicates a 
production module.  
 1 indicates a debug 
module.  
VENDOR_ID  4 Integer  4 0x8086 for Intel  
BUILD_DATE  8 BCD  4 Intel TDX module build data – in 
yyyymmdd BCD format (each 
digit occupies 4 bits)  
BUILD_NUM  12 Integer  2 Build number of the Intel TDX 
module  
MINOR_VERSION  14 Integer  2 Minor version number of the 
Intel TDX module   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
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Intel TDX Application Binary Interface (ABI) Reference  Section  Field Name  Offset 
MAJOR_VERSION  16 Integer  2 Major version number of the 
Intel TDX module  
SYS_RD  18 Boolean  1 A non -0 value indicates that the 
information in this structure is 
incomplete.  TDH.SYS.RD or 
TDH.SYS.RDALL should be used 
to obtain TDX module 
RESERVED  19 N/A 13 This field is reserved for 
enumerating future Intel TDX 
module capabilities.  
Set to 0  
Memory 
Info  MAX_TDMRS  32 Integer  2 The maximum number of 
TDMRs supported  
 
MAX_RESERVED_  
PER_TDMR  34 Integer  2 The maximum number of 
reserved areas per TDMR  
 
PAMT_ENTRY_  
SIZE  36 Integer  2 The size of a PAMT entry – 
determines the number of bytes 
that need to be reserved for the 
three PAMT areas:  
• PAMT_1G (1 entry per 1GB 
of TDMR)  
• PAMT_2M (1 entry per 2MB 
of TDMR)  
• PAMT_4K (1 entry per 4KB 
of TDMR)  
RESERVED  38 N/A 10 Set to 0  
Control 
Struct Info  TDCS_BASE_SIZE  48 Integer  2 Base value for the number of 
bytes required to hold TDCS  
 
RESERVED  50 N/A 2 Reserved for additional TDCS 
enumeration  
Set to 0  
TDVPS_BASE_SIZE  52 Integer  2 Base value for the number of 
bytes required to hold TDVPS  
RESERVED  54 N/A 10 Set to 0  
TD 
Capabilities  ATTRIBUTES_  
FIXED0  64 Bitmap  8 If any certain bit is 0 in 
ATTRIBUTES_FIXED0, it must be 
0 in any TD’s ATTRIBUTES.  The 
value of this field reflects the 
Intel TDX module capabilities 
and configuration and CPU 
capabilities.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 17 of 329 
ATTRIBUTES_  
FIXED1  72 Bitmap  8 If any certain bit is 1 in 
ATTRIBUTES_FIXED1, it must be 
1 in any TD’s ATTRIBUTES.  The 
capabilities.  
XFAM_FIXED0  80 Bitmap  8 If any certain bit is 0 in 
XFAM_FIXED0, it must be 0 in 
any TD’s XFAM.  
XFAM_FIXED1  88 Bitmap  8 If any certain bit is 1 in 
XFAM_FIXED1, it must be 1 in 
RESERVED  96 N/A 32 Set to 0  
NUM_CPUID_  
CONFIG  128 Integer  4 Number of the following 
CPUID_CONFIG entries  
CPUID_CONFIG[0]  132 CPUID_  
CONFIG  24 Enumeration of the CPUID 
leaves/sub -leaves that contain 
bit fields whose virtualization by 
the Intel TDX module is either:  
• Directly configurable 
(CONFIG_DIRECT) by the 
host VMM  
• Bits that the host VMM may 
allow to be 1 
(ALLOW_DIRECT) and their 
native value, as returned by 
the CPU, is 1.  
See 3.3.1  for details.  
Note that the virtualization of 
many CPUID bit fields not 
enumerated in this list is 
configurable indirectly via the 
XFAM and ATTRIBUTES assigned 
to a TD by the host VMM.      
CPUID_  
CONFIG[last]   CPUID_  
CONFIG  24 
Reserved  RESERVED   N/A  Fills up to the structure size 
(1024B) – set to 0  
 
3.3.6.  TDMR_INFO  
TDMR_INFO is designed to provide information about a single Trust Domain Memory Region (TDMR) and its associated 
PAMT.  It is used as an input to TDH.SYS.CONFIG.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 18 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 3.8:  TDMR_INFO Entry Definition  
TDMR_BASE  0 Physical 
Address  8 Base address of the TDMR (HKID bits must be 0):  since a 
TDMR is aligned on 1GB, bits 29:0 are always 0.  
TDMR_SIZE  8 Integer  8 Size of the TDMR, in bytes:  must be greater than 0 and a 
whole multiple of 1GB (i.e., bits 29:0 are always 0).  
PAMT_1G_BASE  16 Physical 
Address  8 Base address of the PAMT_1G range associated with the 
above TDMR (HKID bits must be 0):  since a PAMT range is 
aligned on 4KB, bits 11:0 are always 0.  
PAMT_1G_SIZE  24 Integer  8 Size of the PAMT_1G range associated with the above TDMR:  
since a PAMT range is aligned on 4KB, bits 11:0 are always 0.  
PAMT_2M_BASE  32 Physical 
Address  8 Base address of the PAMT_2M range associated with the 
PAMT_2M_SIZE  40 Integer  8 Size of the PAMT_2M range associated with the above TDMR:  
PAMT_4K_BASE  48 Physical 
Address  8 Base address of the PAMT_4K range associated with the above 
TDMR (HKID bits must be 0):  since a PAMT range is aligned on 
4KB, bits 11:0 are always 0.  
PAMT_4K_SIZE  56 Integer  8 Size of the PAMT_4K range associated with the above TDMR:  
RESERVED_OFFSET[0]  64 Integer  8 • Offset of reserved range 0 within the TDMR:  since a 
reserved range is aligned on 4KB, bits 11:0 are always 0.  
RESERVED_SIZE[0]  72 Integer  8 Size of reserved range 0 within the TDMR:  
• A size of 0 indicates a null entry.  All following reserved 
range entries must also be null.  
• Since a reserved range is aligned on 4KB, bits 11:0 are 
always 0.  
     
RESERVED_OFFSET[N -1] 64 + 
16*(N -1) 
 Integer  8 Offset of the last reserved range within the TDMR.  
 
RESERVED_SIZE[N -1] 72 + 
16*(N -1) 
 Integer  8 Size of the last reserved range within the TDMR.  
 
Notes:  
• The number of reserved areas within a TDMR is enumerated by TDX Module’s MAX_RESREVED_PER_TDMR metadata 
field, which can be read using TDH.SYS.RD, TDH.SYS.RDALL or TDH.SYS.RDM.  For details, see 3.3.5 3.3.3 . 5 
• For backward compatibility, this value is also enumerated by TDSYSINFO_STRUCT.MAX_RESREVED_PER_TDMR (see 
3.3.5 ). 
• Within each TDMR entry, all reserved areas must be sorted from the lowest offset to the highest offset, and they 
must not overlap with each other.  
• All TDMRs and PAMTs must be contained within CMRs.  10  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 19 of 329 
Intel TDX Application Binary Interface (ABI) Reference  • A PAMT area must not overlap with another PAMT area (associated with any TDMR), and it must not overlap with 
non-reserved areas of any TDMR.  PAMT areas may reside within reserved areas of TDMRs.  
3.4. TD Parameter  Types  
Note:  This section describes TD parameter types, as defined.  Implementation details may differ.  
3.4.1.  ATTRIBUTES  5 
ATTRIBUTES is  defined as  a 64b field that specifies various attested guest TD attributes.  ATTRIBUTES is provided by the 
host VMM as a guest TD initialization parameter as part of TD_PARAMS.  It is reported to the guest TD by TDG.VP.INFO , 
TDG.VM.RD*  and as part of TDREPORT_STRUCT  returned by TDG.MR.REPORT .  ATTRIBUTES is migrated to a destination 
platform as part of the immutable TD state export by TDH.EXPORT.STATE.IMMUTABLE and import by 
TDH.IMPORT.STATE.IMMUTABLE.  10 
The ATTRIBUTES bits are divided into four  groups, as shown in the table below , according to their impact on TD security:  
• If any bit in the TUD group is set to 1, the guest TD is under off -TD debug and is untrusted.

• If any bit in the TUD group is set to 1, the guest TD is under off -TD debug and is untrusted.  
• Bits in the TUP group indicate features that impact security and trust.  It is up to the remote verifier to decide whether 
the impact on TD trustworthiness is acceptable.  
• Bits in the SEC group indicate features that may impact TD security but  are not considered as impacting TD trust.   Bits 15 
in the SEC group may have a positive or a negative impact on the TD security if set, as specified in the table.  
• Bits in the OTHER group indicate feature that are attested but do not impact TD security.  
The table below  shows the whole set of ATTRIBUTES bits that have been defined.  However, the following must be noted:  
• Some versions of the TDX module may not support some of the ATTRIBUTES bits.  E.g., for a TDX Module that does 
not support TD Migration, the MIGRATABLE bit must always be 0.  20 
• Some of the ATTRIBUTES bits depend on CPU support.  E.g., for a CPU does not support Key Locker, the KL bit must 
be 0.  
Notes  
• The host VMM can determine the supported set of ATTRIBUTES bits by reading the ATTRIBUTES_FIXED0 and 
ATTRIBUTES_FIXED1 fields  using TDH.SYS.RD /RDALL . 25 
• The attestation infrastructure may evaluate a TD’s ATTRIBUTES based on the negative or positive security impact of 
each bit.  For example, if a new version of the TDX module uses the currently reserved bit 25, the attestation 
infrastructure can know that t his bit has a negative security impact when set, even without knowing the meaning of 
the bit.  
• TD configuration that does not need to be attested (normally because it doesn’t impact TD security) is not included 30 
in ATTRIBUTES.  See the definition of CONFIG_FLAGS, CPUID configuration and other fields of TD_PARAMS in the 
Table 3.9:  ATTRIBUTES Definition  
Bits Group  Description  Bits Bit Name  TD 
Security 
Impact 
if 1 Description  
3:0 TUD  TD Under Debug  
If any of the bits 
in this group are 
set to 1, the guest 
TD is untrusted.  0 DEBUG  Negative  Guest TD runs in off -TD debug mode.  Its VCPU 
state and private memory are accessible by the 
host VMM.  
3:1 RESERVED  Negative  Reserved for future TUD flags – must be 0  
15:4  TUP  TD Under 
Profiling  4 HGS_PLUS_PROF  Negative  The TD participates in HGS+ operation.   HGS+ 
monitors the TD operation as part of the whole 
system.  
This bit may be set, if supported by the TDX 
module,  regardless on CPU support.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 20 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Bits Group  Description  Bits Bit Name  TD 
Security 
Impact 
The TD is subject 
to profiling,  
which may expose 
side channel 
information to 
untrusted entities . 5 PERF_PROF  Negative  The TD participates in system profiling using 
performance monitoring counters.   Those counters 
are not context -switched on TD entry and exit; they 
monitor the TD operation as part of the whole 
system.  
module,  regardless on CPU support.  
6 PMT_PROF  Negative  The TD participates in system profiling using core 
out-of-band telemetry.   Core telemetry monitors 
the TD operation as part of the whole system.  
module, regardless of CPU support.  
15:7  RESERVED  Negative  Reserved for future TUP  flags – must be 0  
31:16  SEC Security  
Attributes that 
may impact TD 
security  22:16  RESERVED_P  Positive  Reserved for future SEC flags that will indicate 
positive impact on TD security.  
• As an input to TDH.MN.INIT, must be 0 . 
• Attestation verifiers may allow any value.  
26:23  RESERVED _N Negative  Reserved for future SEC flags that will indicate 
negative impact on TD security – must be 0  
27 LASS  Positive  TD is allowed to use Linear Address Space 
Separation.  
This bit may only be set if both the TDX module and 
the CPU support LASS.  
28 SEPT_VE_DISABLE  Negative  Disable EPT violation conversion to #VE on guest 
TD access of PENDING pages  
29 MIGRATABLE  Negative  TD is migratable (using a Migration TD) . 
This bit may only be set if the TDX module supports 
TD Migration.  
30 PKS Positive  TD is allowed to use Supervisor Protection Keys . 
the CPU support PKS.  
31 KL Positive  TD is allowed to use Key  Locker . 
the CPU support Key Locker.  
55:32  RESERVED  Reserved  55:32  RESERVED  None  Reserved for future expansion of the SEC group - 
must be 0 
63:56  OTHER  Attributes that are 
attested but do 
not impact TD 
security  61:32  RESERVED  None  Reserved for future OTHER flags – must be 0  
62 TPA  None  The TD is a TDX Connect Provisioning Agent.  
the CPU support TDX Connect.  
63 PERFMON  None  TD is allowed to use Perfmon and PERF_METRICS 
November 2023  . Page 21 of 329 
Security 
Impact 
This bit may only be set if the TDX Module supports 
Performance Monitoring virtualization.  
 
3.4.2.  XFAM  
Intel SDM, Vol. 1, 13  Managing State Using the XSAVE Feature Set  
Intel TDX module  extended state handling is described in the [ TDX Module Base Spec ]. 5 
XFAM (eXtended Features Available Mask) is defined as a 64b bitmap, which has the same format as XCR0 or IA32_XSS 
MSR.  XFAM determines the set of extended features available for use by the guest TD.  XFAM is provided by the host 
VMM as a guest TD initialization parameter as part of TD_PARAMS.  It is reported  to the guest TD by CPUID (0x0D, 0x01)  
and as part of TDREPORT_STRUCT  returned by TDG.MR.REPORT . 
The Intel TDX module  and the Intel® Architecture impose some rules on how the bits of XFAM may be set .  See the [ TDX 10 
Module Base Spec ] for details.  
Support of XFAM bits depend on CPU support and TDX module support.  The supported bit values can be enumerated by 
reading the XFAM_FIXED_0 and XFAM_FIXED_1 fields using TDH.SYS.RD /RDALL . 
3.4.3.  CONFIG_FLAGS  
CONFIG_FLAGS is a set of TD configuration flags.  15  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 22 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 3.10:  TD_PARAMS_STRUCT.CONFIG_FLAGS Definition  
0 GPAW  GPAW (Guest Physical Address Width1) controls the position of the SHARED 
bit in GPA.  It is copied to each TD VMCS and L2 VMCS GPAW  execution 
control on TDH.VP.INIT  and TDH.IMPORT.STATE.VP.  
0: GPA.SHARED bit is GPA[47]  
1: GPA.SHARED bit is GPA[51]  
A value of 1 can only be specified if EPTP_CONTROLS[5:3] is specified as 4 
(i.e., 5 -level EPT).  For details, see the [ TDX Arch Extensions Spec ]. 
1 FLEXIBLE_PENDING_VE  Controls the guest TD’s ability to change the PENDING page access behavior 
from its default value:  
0:       The guest TD cannot change the behavior set by 
ATTRIBUTES.SEPT_VE_DISABLE.  
1:       The guest TD can change the default behavior set by 
Enumeration:  Availability of FLEXIBLE_PENDING_VE is enumerated by 
TDX_FEATURES0.PENDING_EPT_VIOLATION_V2 (bit 16) and 
by CONFIG_PARAMS_FIXED0/1, readable using TDH.SYS.RD*.  
 
2 NO_RBP_MOD  Controls whether RBP value can be modified by TDG.VP.VMCALL and 
TDH.VP.ENTER : 
0:       RBP can be used as an input to TDG.VP.VMCALL.  The value provided 
by the guest TD is used as an output of TDH.VP.ENTER.  The value 
provided by the host TD to the following TDH.VP.ENTER is used as an 
output of TDG.VP.VMCALL . 
1:       RBP can’t be used as an input to TDG.VP.VMCALL.  TDG.VP.VMCALL 
preserves the guest TD’s value of RBP.  TDH.VP.ENTER preserves the 
host VMM’s value of RBP . 
TDX_FEATURES0.NO_RBP_MOD (bit 18) and by 
CONFIG_PARAMS_FIXED0/1, readable using TDH.SYS.RD*.  
63:3 RESERVED  Must be 0  
 
3.4.4.  CPUID_ VALUES  
CPUID_VALUES  is defined as a 128b structure composed of four 32b fields representing the values returned by CPUID in 
registers EAX, EBX, ECX and EDX.  An array of CPUID_RET is used during guest TD configuration by TDH.MNG.INIT . 5 
Table 3.11:  CPUID_VALUES Definition  
EAX  0 4 Value returned by CPUID in EAX  
EBX 4 4 Value returned by CPUID in EBX  
ECX 8 4 Value returned by CPUID in ECX  
 
1 The name is misleading, since the GPA width is not determined by GPAW.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 23 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Field  Offset 
EDX  12 4 Value returned by CPUID in EDX  
 
3.4.5.  TD_PARAMS

3.4.5.  TD_PARAMS  
TD_PARAMS  is provided as an input to TDH.MNG.INIT , and some of its fields are included in the TD report .  The format 
of this  structure is valid for a specific MAJOR_VERSION of the Intel TDX module , as reported by TDH.SYS.RD/RD ALL or 
TDH.SYS. INFO.  5 
TD_PARAMS’ size is 1024 B. 
Table 3.12:  TD _PARAMS  Definition  
(Bytes)  Description  Included in 
TDREPORT ? 
ATTRIBUTES  0 64b bitmap ( see 
3.4.1 ) 8 TD attributes:  the value set in this field must 
comply with ATTRIBUTES_FIXED0 and 
ATTRIBUTES_FIXED1 enumerated by 
TDH.SYS.RD/RD ALL or TDH.SYS. INFO.  Yes 
XFAM  8 64b bitmap in 
XCR0 format  8 Extended Features Available Mask:  indicates 
the extended state features allowed for the 
TD.  XFAM’s format is the same as XCR0 and 
IA32_XSS MSR.  The value set in this field 
must satisfy the following conditions:  
• Natively valid  value for XCR0 and 
IA32_XSS (does not contain reserved bits, 
features not supported by the CPU, or 
invalid  bit combinations)  
• Complies with XFAM_FIXED0 and 
XFAM_FIXED1 as enumerated by 
MAX_VCPUS  16 Unsigned 16b 
Integer  2 Maximum number of VCPUs  
Must be higher than 0.  No 
NUM_L2_VMS  18 Unsigned 8b 
Integer  1 Number of L2 VMs  
May be between 0 and 3.  A value of 0 
indicates no TD Partitioning is supported.  No 
MSR_CONFIG_CTLS  19 8b bitmap  1 MSR configuration controls:  No 
Bit Description  
0 Indicates that TD configuration 
should use the  
IA32_ARCH_CAPABILITIES_CONFIG 
field below  
Other  Reserved, m ust be 0  
RESERVED  20 N/A 4 Must be 0  No 
EPTP_CONTROLS  24 EPTP  8 Control bits of EPTP – copied to each TD 
VMCS on TDH.VP.INIT : 
Bits 2:0  Memory type – must be 110 (WB)  No  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 24 of 329 
TDREPORT ? 
Bits 5:3  EPT level – 1 less than the EPT page -
walk length .  Must be either 3 or 4 .  
Must comply with the EPT page -
walk length supported by the CPU.  
Bits 63:6  Reserved – must be 0  
CONFIG_FLAGS  32 64b bitmap  
 8 Non -measured TD -scope execution controls .  
See 3.4.3 above  for details.  No 
TSC_FREQUENCY  40 16b unsigned 
integer  2 TD-scope virtual TSC frequency in units of 
25MHz – must be between 4 and 400.  No 
RESERVED  42 N/A 38 Must be 0  No 
MRCONFIGID  80 SHA384_HASH  48 Software -defined ID for non -owner -defined 
configuration of the guest TD – e.g., run -time 
or OS configuration  Yes 
MROWNER  128 SHA384_HASH  48 Software -defined ID for the guest TD’s owner  Yes 
MROWNERCONFIG  176 SHA384_HASH  48 Software -defined ID for owner -defined 
configuration of the guest TD – e.g., specific 
to the workload rather than the run -time or 
OS Yes 
IA32_ARCH_  
CAPABILITIES_CONFIG  224 64b bitmap  8 Configuration of IA32_ARCH_CAPABILITIES 
MSR virtualization (if enabled by 
MSR_CONFIG_CTLS above).  Configuration 
capabilities are enumerated by the 
IA32_ARCH_CAPABILITIES_CONFIG_MASK .  
which can be read by TDH.SYS.RD/RDALL.  No 
MRCONFIG SVN  232 16b unsigned 
integer  2 SVN corresponding to MRCONFIGID  
Support of this field is enumerated by 
TDX_FEATURES0.TDX_SEAL_KEYS (bit 12).  If 
not supported, this field must be 0.  Yes 
MROWNERCONFIGSVN  234 16b unsigned 
integer  2 SVN corresponding to MROWNERCONFIG  
RESERVED  236 N/A 20 Must be 0  No 
CPUID_CONFIG[0]  256 CPUID_VALUES  16 Direct configuration of CPUID leaves/sub -
leaves virtualization:  the number and order 
of entries must be equal to the number and 
order of directly configurable or allowable 
CPUID leaves/sub -leaves reported by 
TDH.SYS.RD/RD ALL or TDH.SYS. INFO.  Note 
that the leaf and sub -leaf numbers are 
implicit.  
Only bits that have been reported as 1 by 
TDH.SYS.RD/RD ALL or TDH.SYS. INFO may be 
set to 1.  No 
 
CPUID_CONFIG[n -1]  CPUID_VALUES  16  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 25 of 329 
TDREPORT ? 
Note that the virtualization of many CPUID bit 
fields not enumerated in this list is 
configurable indirectly, via the XFAM and 
ATTRIBUTES fields.  
RESERVED   N/A  Fills up to TD_PARAMS size (1024B) – must be 
0 No 
 
3.5. Physical Memory Management Types  
Note:  This section describes physical memory types, as defined.  Implementation may differ.  
PAMT entry and PT (page type) are defined in the [ TDX Module Base Spec ]. 
3.5.1.  PAMT Page Type (PT) Values  5 
Some PT values are applicable only when enumerated by certain TDX_FEATURES bits (see 3.3.3.1 ).  If a certain PT value 
is not applicable, then it is considered reserved.  For a detailed description of the page types, refer to the [Base Spec] . 
Table 3.13:  PAMT Page Type Values  
Page Type  Value  TDX_FEATURES 
Enumeration   
PT_NDA  0 N/A The physical page is Not Directly Assigned  to the Intel 
PT_RSVD  1 N/A The physical page is reserved for non -TDX usage.  
PT_PR  2 ACT (bit 14)  The physical page holds a page that is pending release.  
PT_REG  3 N/A The physical page holds TD private memory.  
PT_TDR  4 N/A The physical page holds the TD Root (TDR) control 
PT_TDCX  5 N/A The physical page holds a TD control structure.  
PT_TDVPR  6 N/A The physical page holds a TD VCPU Root (TDVPR) page.  
RESERVED  7 N/A Reserved  
PT_EPT  8 N/A The physical page holds a Secure EPT page.  
PT_DEVIFCS_R  9 TDX_CONNECT 
(bit 6)  The physical page holds a DEVIFCS structure  
PT_DEVIF_NR  10 TDX_CONNECT 
(bit 6)  The physical page holds a DEVIFCS internal data  
PT_IOMMU_MT  11 TDX_CONNECT 
(bit 6)  The physical page holds an I/O (IOMMU/IDE/SPDM) data  
PT_MMIO_MT  12 TDX_CONNECT 
(bit 6)  The physical page holds a n MMIO metadata table  
PT_DEVIFMT  13 TDX_CONNECT 
(bit 6)  The physical page holds a DEVIF metadata table  
RESERVED  Other  N/A Reserved  
November 2023  . Page 26 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3.5.2.  Physical Page Size  
Three physical page size levels (4KB, 2MB and 1GB) are defined.  
Table 3.14:  Page Size  Definition  
Page Size  Associated 
Physical Page Size  Value  
PS_1G  1GB  2 
PS_2M  2MB  1 
PS_4K  4KB 0 
 
3.6. TD Private Memory Management Data Types :  Secure EPT  5 
Intel SDM, Vol. 3, 28.2.2  EPT Translation Mechanism  
Note:  This section describes private memory management types, as defined.  Implementation may differ.  
3.6.1.  Secure EPT Level s 
Secure EPT level definition is identical to  legacy VMX EPT level definition.  As a rule, an EPT entry at level L maps a GPA 
range whose size is 212+9*L. 10 
Table 3.15:  EPT Levels  Definition  
Level  0 1 2 3 4 5 (5-Level EPT Only)  
GPA Range Size  4KB 2MB  1GB  512GB  256TB  16PB2 
Child Physical 
Page Size  4KB 2MB  1GB  N/A N/A N/A 
EPT Page Type  N/A EPT EPD  EPDPT  EPML4  EPML5  
Parent EPT 
Entry Type  EPTE EPDE  EPDPTE  EPML4E  EPML5E  (5-level EPT) or 
VMCS.EPTP (4 -level EPT)  VMCS.EPTP  
GPA Offset B its 20:12  29:21  38:30  47:3 9 51:48  (5-level EPT only)  N/A 
 
3.6.2.  Secure EPT Entry Information as Returned by TDX Module Functions  
Many Intel TDX module functions return Secure EPT entry information.  This information is returned in the formats 
detailed below, which may be different that the actual Secure EPT format as maintained by the TDX module in memory.  15 
Note:  The returned Secure EPT information is subject to change with new versions of TDX.  
3.6.2.1.  Returned L1 Secure EPT Entry Content  
The returned L1 secure EPT entry format is detailed below.  It may be different that the actual Secure EPT format as 
maintained by the TDX module in memory.  
 
2 Only the lower half is available as TD private GPA space, because the SHARED bit must be 0   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 27 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 3.16:  L1 Secure EPT Entry Content as Returned by TDX Interface Functions  
L1 Secure EPT Entry Field  Value Returned in RCX  
(per Entry State Returned in RDX)  
MSB  LSB Size  Short 
Name  Full Name  Enabled  Non -FREE  
Leaf  Non -FREE 
Non -Leaf  FREE  
0 0 1 R Read  N/A R R 0 
1 1 1 W Write  N/A W W 0 
2 2 1 X / Xs Execute  N/A X X 0 
5 3 3 MT Memory Type  N/A MT 0 0 
6 6 1 IPAT  Ignore PAT  N/A IPAT  0 0 
7 7 1 PS Leaf  N/A 1 0 0 
8 8 1 A Accessed  No 0 0 0 
9 9 1 D Dirty  No 0 0 0 
10 10 1 Xu Execute (User)  No 0 0 0 
11 11 1 Ignored  Ignored  N/A 0 0 0 
51 12 40 HPA[51:12]  Host Physical Address [51:12]  N/A HPA[51:12]  HPA[51:12]  0 
57 57 1 VGP  Verify Guest Paging  No 0 0 0

57 57 1 VGP  Verify Guest Paging  No 0 0 0 
58 58 1 PWA  Paging -Write Access  No 0 0 0 
59 59 1 Ignored  Ignored  N/A 0 0 0 
60 60 1 SSS Supervisor Shadow Stack  No 0 0 0 
61 61 1 SPP Check Sub -Page Permissions  No 0 0 0 
62 62 1 Ignored  Ignored  N/A 0 0 0 
63 63 1 SVE Suppress #VE  Yes SVE 0 1 
 
For L1 SEPT entries, t he R, W and X access permission bits’ values depend on the SEPT entry state:  
• For leaf entries in the MAPPED and EPORTED_DIRTY states, and non -leaf entries in the NL_MAPPED state, RWX  = 111.  
• For leaf entries in the BLOCKED, PENDING* and REMOVED states, non -leaf entries in the NL_BLOCKED state  and FREE 5 
entries , RWX  = 000.  
• For leaf entries in the *BLOCKED W* states, RWX  = 101.  
3.6.2.2.  Returned L2 Secure EPT Entry Content  
The returned L2 secure EPT entry format is detailed below.  It may be different that the actual L2 Secure EPT format as 
maintained by the TDX module in memory.  10 
Table 3.17:  L2 Secure EPT Entry Content as Returned by TDX Interface Functions  
L2 Secure EPT Entry Field  Value Returned in RCX  
Name  Full Name  Enabled  Non -FREE 
2 2 1 Xs Execute  N/A Xs Xs 0 
5 3 3 MT Memory Type  N/A MT 0 0  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 28 of 329 
Intel TDX Application Binary Interface (ABI) Reference  L2 Secure EPT Entry Field  Value Returned in RCX  
10 10 1 Xu Execute (User)  No Xu Xu 0 
57 57 1 VGP  Verify Guest Paging  No 0 / VGP  0 0 
58 58 1 PWA  Paging -Write Access  No 0 / PWA  0 0 
60 60 1 SSS Supervisor Shadow Stack  No 0 / SSS  0 0 
 
For L2 SEPT entries, the R, W, Xs and Xu access permission bits’ values depend on the L2 SEPT entry state and on the TD’s 
ATTRIBUTE.DEBUG value:  
• For leaf entries in the L2_MAPPED state : 
o If ATTRIBUTES.DEBUG is 0 , then RWXsXu = 1111  and VGP, PWA and SSS are cleared to 0.  5 
o Else, the real value s of RWXsXu and of VGP, PWA and SSS are  returned.  
• For leaf entries in the L2_BLOCKED state:  
o If ATTRIBUTES.DEBUG is 0, then RWXsXu = 0000 and VGP, PWA and SSS are cleared to 0.  
o Else, then RWXsXu = 0000 and GP, PWA and SSS are returned.  
• For non -leaf entries in the L2_NL_MAPPED state, RWXsXu  = 1111.  10 
• For non -leaf entries in the L2_NL_BLOCKED state and L2_FREE entries, RWXsXu  = 0000. 
3.6.2.3.  Additional  Returned Secure EPT Information  
Additional information for secure EPT entries is returned as defined below.   Some SEPT entry state values are applicable 
only when enumerated by certain TDX_FEATURES bits (see 3.3.3.1 ).  If a certain SEPT entry state value is not applicable, 
then it is considered reserved.  15 
Table 3.18:  Additional Secure EPT Entry Information Returned by TDX Interface Functions  
2:0 Level  Level of the returned Secure EPT entry – see 3.6.1 above  
7:3 Reserved  Set to 0  
15:8  State  The TDX state of the Secure EPT entry – see Table 3.19 below  
17:16  VM Index of the VM for which the SEPT information is returned  
63:1 8 Reserved  Set to 0  
November 2023  . Page 29 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 3.19:  Secure L1 EPT Entry TDX State Returned by TDX Interface Functions  
L1 SEPT Entry State Name  Public 
State 
Number  TDX_FEATURES 
Enumeration  Description  
FREE  0 N/A L1 Secure EPT entry does not map a GPA range.  
REMOVED  5 TD_MIGRATION  L1 Secure EPT entry is of a removed page  
NL_MAPPED  132 N/A L1 Secure EPT entry maps a private GPA range 
which is accessible by the guest TD.  
NL_BLOCKED  129 N/A L1 Secure EPT entry maps a private GPA range, but 
new address translations to that range are blocked.  
MAPPED  4 N/A L1 Secure EPT entry maps a private GPA page which 
is accessible by the guest TD.  
BLOCKED  1 N/A L1 Secure EPT entry maps a private GPA page but 
BLOCKEDW  8 TD_MIGRATION  L1 Secure EPT entry maps a private GPA page, but 
new address translations for write operations to 
that range are blocked.  
EXPORTED_BLOCKEDW  9 TD_MIGRATION 
or S4  L1 Secure EPT entry maps a private page that has 
been blocked for writing and exported.  
EXPORTED_DIRTY  11 TD_MIGRATION  L1 Secure EPT entry maps a private page that was 
exported but  is not blocked for writing and its 
content and/or attributes may have since been 
modified.  
EXPORTED_DIRTY_BLOCKEDW  12 TD_MIGRATION  L1 Secure EPT entry maps a private page that was 
previously exported, its content and/or attributes 
may have since been modified and then it was 
blocked for writing .   
PENDING  2 N/A L1 Secure EPT entry maps a 4KB or a 2MB page that 
has been dynamically added to the guest TD using 
TDH.MEM.PAGE.AUG and is pending acceptance by 
the guest TD using TDG.MEM.PAGE.ACCEPT.  This 
page is not yet accessible by the guest TD.  
PENDING_BLOCKED  3 N/A L1 Secure EPT entry is both pending and blocked.  
PENDING_BLOCKEDW  16 TD_MIGRATION  L1 Secure EPT entry is both pending and blocked 
PENDING_EXPORTED_BLOCKEDW  17 TD_MIGRATION 
or S4  L1 Secure EPT entry is both pending and exported.  
PENDING_EXPORTED_DIRTY  19 TD_MIGRATION  L1 Secure EPT entry is both pending and exported 
and is not blocked for writing.  
PENDING_EXPORTED_DIRTY_BLOCKEDW  20 TD_MIGRATION  Secure EPT entry is both pending and exported and  
is blocked for writing.  
MMIO_MAPPED  32 TDX_CONNECT  Secure EPT entry maps a private MMIO page which 
MMIO_BLOCKED  33 TDX_CONNECT  Secure EPT entry maps a private MMIO page, but 
new address translations to that page are blocked.  
MMIO_PENDING  34 TDX_CONNECT  Secure EPT entry maps a 4KB, 2MB or 1GB MMIO 
page that is pending acceptance by the guest TD 
using TDG.MMIO.ACCEPT.  This page is not yet 
accessible by the guest TD.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 30 of 329 
Intel TDX Application Binary Interface (ABI) Reference  L1 SEPT Entry State Name  Public 
State 
MMIO_PENDING_BLOCKED  35 TDX_CONNECT  Secure EPT entry for an MMIO page is both 
pending and blocked.  
 
Table 3.20:  Secure L2 EPT Entry TDX State Returned by TDX Interface Functions  
L2 SEPT Entry State Name  Public State 
L2_FREE  64 TD_PARTITIONING  L2 Secure EPT entry does not map a GPA range.  
L2_NL_MAPPED  196 TD_PARTITIONING  L2 Secure EPT entry maps a private GPA range which is 
accessible by the L2 VM.  
L2_NL_BLOCKED  193 TD_PARTITIONING  L2 Secure EPT entry maps a private GPA range, but new 
address translations to that range are blocked.  
L2_MAPPED  68 TD_PARTITIONING  L2 Secure EPT entry maps a private GPA page which is 
L2_BLOCKED  65 TD_PARTITIONING  L2 Secure EPT entry maps a private GPA page but new 
L2_MMIO_MAPPED  96 TD_PARTITIONING  
and TDX_CONNECT  L2 Secure EPT entry maps a private MMIO page which is 
L2_MMIO_BLOCKED  97 TD_PARTITIONING  
and TDX_CONNECT  L2 Secure EPT entry maps a private MMIO page, but new 
address translations to that page are blocked.  
 
3.6.3.  GPA_ ATTR :  GPA Attributes  
GPA_ATTR  specif ies the settable attributes of a page .  It is used as an input of TDG.MEM.PAGE. ATTR .WR , as an output of 5 
TDG.PAGE.ATTR.WR, and for migration (TDH.EXPORT.MEM and TDH.IMPORT.MEM) and, if the TD is in debug mode, for 
returning of L2 attributes by TDH.MEM.SEPT.RD.  
GPA_ATTR is an array of four GPA_ATTR_SINGLE_VM 16-bit entries:  
Table 3.21:  GPA_ATTR:  GPA Attributes (all VMs) Definition  
Bits VM 
Index  Bits Description  
15:0  0 15:0  GPA attributes for L1 (all -0 for migration)  
31:16  1 31:24  GPA attributes for L2 VM #1  
47:32  2 47:32  GPA attributes for L2 VM # 2 
63:48  3 63:48  GPA attributes for L2 VM # 3 
 10 
Table 3.22:  GPA_ATTR_SINGLE_VM:  GPA Attributes (Single VM) Definition  
Bit(s)  Size  Attribute 
Type  Name  Description  TDG.MEM.PAGE.  
ATTR.RD/WR Access  Used for Migration  
L1  L2 L1 L2 
0 1 Intel64  R Read  None  RW No Yes 
1 1 Intel64  W Write  None  RW No Yes 
2 1 Intel64  Xs Execute (Supervisor)  None  RW No Yes 
3 1 Intel64  Xu Execute (User)  None  RW No Yes  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US

Bits VM 
 10 
L1  L2 L1 L2 
3 1 Intel64  Xu Execute (User)  None  RW No Yes  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 31 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Bit(s)  Size  Attribute 
L1  L2 L1 L2 
4 1 Intel64  VGP  Verify Guest Paging  None  RW No Yes 
5 1 Intel64  PWA  Paging -Write Access  None  RW No Yes 
6 1 Intel64  SSS Supervisor Shadow Stack  None  RW No Yes 
7 1 Intel64  RESERVED  Reserved  None  None  No No 
13:8  6 N/A RESERVED   None  None  No No 
14 1 TDX  RESERVED   None  None  No No 
15 1 TDX  VALID  Indicates that the other bits are 
valid .  If its value is 0, other fields 
are reserved and must be 0.  RW RW No Yes 
 
3.6.3.1.  GPA Attributes Rules  
The TDX module enforces the following rules to help ensure that GPA attributes will not cause an EPT Misconfiguration 
(see [Intel SDM, Vol. 3, 28.3.3.1]):  
• If VALID is 0, all other bits must be 0  5 
• Reserved bits must be 0.  
• If bit W is 1, bit R must be 1  
• If bit PWA is 1, bit R must be 1 (regardless of the VMCS “EPT paging -write control” VM -execution control . 
The TDX module checks, on TDH.SYS.INIT, that the CPU supports setting Xs or Xu when R is 0.  
3.6.4.  GLA List  10 
GLA lists are used by TDG.VP.INVGLA . 
3.6.4.1.  GLA_LIST_ENTRY  
GLA_LIST_ENTRY  species a range of consecutive guest linear addresses , each aligned on 4KB.  
Table 3.23:  GLA_LIST_ENTRY  Definition  
11:0  LAST_ GLA_INDEX  Index of the last 4KB -aligned linear address  to be processed  
63:12  BASE_GL A Bits 63:12 of the guest linear address of the first 4KB page to be processed  
 15 
3.6.4.2.  GLA_LIST  
A GLA_LIST is an array of up to 512 GLA_LIST_ENTRIES.  
3.6.4.3.  GLA_LIST_INFO:  GLA List G PA and Additional Information   
GPA_LIST_INFO is a 64b structure used as a GPR input and output operand of TDG.VP.INVGLA .  It provides the GPA of the 
GLA list page in private memory, the index of the first entry and the number of entries to be processed.  20 
Table 3.24:  GLA_LIST_INFO  
8:0 FIRST_ENTRY  Index of the first entry of the list to be processed   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 32 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Bits Name  Description  
11:9  RESERVED  Reserved:  must be 0  
51:12  LIST_GPA  Bits 51:12 of the guest physical address of the G LA list page, which must be a 
private GPA  
61:52 NUM_ENTRIES  Number of entries in the GLA list  to be processed , must be between 0 through 512  
63:62 RESERVED  Reserved:  must be 0  
 
3.7. TD Entry and Exit  Types  
3.7.1.  Extended Exit Qualification  
Extended Exit Qualification is a 64 -bit field returned by TDH.VP.ENTER for asynchronous TD exits with an architectural 
VMX exit reasons.  It contains additional non -VMX, TDX -specific information.  5 
Table 3.25:  Extended Exit Qualification  
3:0 TYPE  Extended exit qualification type  
Value  Name  Description  
0 NONE  No extended exit qualification  
1 ACCEPT  Extended e xit qualification for an EPT 
violation during TDG.MEM.PAGE.ACCEPT  
2 GPA_DETAILS  Extended e xit qualification for an EPT 
violation caused by guest -side interface 
function failure of GPA →HPA translation  
3 TD_ENTRY_MSR_LOAD_FAILURE  Extended e xit qualification for failures of 
TD entry due to loading guest MSR state  
4 TD_ENTRY_XSTATE_LOAD_FAILURE  Extended e xit qualification for failures of 
TD entry due to loading guest extended 
state  
5 ATTR_WR  Extended e xit qualification for an EPT 
violation during TDG.MEM.PAGE.ATTR.WR  
6 PENDING_EPT_VIOLATION3 Extended e xit qualification for an EPT 
violation due to guest TD access to a 
PENDING page  
Other  Reserved   
31:4  Reserved  Set to 0  
63:32  INFO  TYPE -specific information  
TYPE  Value  
NONE  0 
ACCEPT  See the table below  
GPA_DETAILS  See the table below  
TD_ENTRY_MSR_LOAD_FAILURE  MSR index  
 
3 Availability of this indication is enumerated by TDX_FEATURES0.PENDING_EPT_VIOLATION_V2 (bit 16), readable by TDH.SYS.RD*.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 33 of 329 
TD_ENTRY_XSTATE_LOAD_FAILURE  0 
ATTR_WR  See the table below  
PENDING_EPT_VIOLATION  0 
Reserved  0 
 
Table 3.26:  Extended Exit Qualification INFO Field (Bits 63:32) when TYPE is ACCEPT  or ATTR_WR  
34:32  REQ_SEPT_LEVEL  SEPT level requested as an input to TDG.MEM.PAGE.ACCEPT  or 
TDG.MEM.PAGE.ATTR.WR  
37:35  ERR_SEPT_LEVEL  SEPT level in which TDG.MEM.PAGE.ACCEPT or TDG.MEM.PAGE.ATTR.WR 
detected an error  
45:38  ERR_SEPT_STATE  The TDX state of the Secure EPT entry where TDG.MEM.PAGE.ACCEPT or 
TDG.MEM.PAGE.ATTR.WR detected an error – see Table 3.19 above  
46 ERR_SEPT_IS_LEAF  Indicates that the SEPT entry where TDG.MEM.PAGE.ACCEPT or 
TDG.MEM.PAGE.ATTR.WR detected an error is a leaf entry  
63:47  Reserved  Set to 0  
 
Table 3.27:  Extended Exit Qualification INFO Field (Bits 63:32) when TYPE is GPA_DETAILS  
34:32  Reserved  Set to 0  
37:35  ERR_SEPT_LEVEL  Level  where the Secure EPT walk error occurred  
51:38 Reserved  Set to 0  
53:52  VM_INDEX  Virtual machine index for which Secure EPT walk error occurred  
63:54 Reserved  Set to 0  
 5 
3.8. L2 VM Transition Types  
3.8.1.  L2_ENTER_GUEST_STATE  
L2_ENTER_GUEST_STATE  is used as input and output of TDG.VP.ENTER.  It is an array of general -purpose ( GPR) register 
values, organized according to their architectural number , with additional values of RFLAG, RIP and SSP.  
Table 3.28:  L2_ENTER_GUEST_STATE Definition  10 
Offset (Bytes)  Size (Bytes)  Name  Description  
0 8 RAX   
8 8 RCX   
16 8 RDX   
24 8 RBX   
32 8 RSP  
40 8 RBP    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 34 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Offset (Bytes)  Size (Bytes)  Name  Description  
48 8 RSI   
56 8 RDI   
64 8 R8   
72 8 R9   
80 8 R10   
88 8 R11   
96 8 R12   
104 8 R13   
112 8 R14   
120 8 R15   
128 8 RFLAGS   
136 8 RIP  
144 8 SSP  
152 2 GUEST_INTERRUPT_STATUS  Bits 7:0:  RVI 
Bits 15:7:  SVI 
 
3.9. Measurement and Attestation Types  
Note:  This section describes measurement and attestation types, as defined.  Implementation may differ.  
3.9.1.  CPUSVN  
CPUSVN is a 16B Security Version Number of the CPU.  5 
• There is a single CPUSVN used for SGX and TDX.  
• CPUSVN contents are considered micro -architectural .  CPUSVN is composed of fields for PR_RESET_SVN, 
R_LAST_PATCH_SVN, SINIT, BIOS ACM, Boot Guard ACM and BIOS Guard NP -PPPE module.  
3.9.2.  TDREPORT_STRUCT  
TDREPORT_STRUCT  is the output of the TDG.MR.REPORT  function .  TDREPORT_STRUCT  is composed of a generic MAC 10 
structure (REPORTMACSTRUCT, see 3.9.5 below ), a TEE_TCB_INFO structure and a TDX -specific  TEE info structure 
(TDINFO_STRUCT , see  3.9.7 below ). 
The overall size of TDREPORT_STRUCT  depends on its version, as specified in REPORTMACSTRUCT.REPORTTYPE.VERSION:  
• For REPORTTYPE.VERSION values of 0 and 1, TDREPORT_STRUCT’s size is 1024 bytes.  
Table 3.29:  TDREPORT_STRUCT  Definition  15 
REPORTMACSTRUCT  0 REPORTMACSTRUCT  256 REPORTMACSTRUCT for the TDG.MR.REPORT  
TEE_TCB_ INFO  256 TEE_TCB_ INFO_STRUCT  239 Additional attestable elements in the TD’s TCB are 
not reflected in the REPORTMACSTRUCT.CPUSVN 
– includes the Intel TDX module  measurements.  
RESERVED  495 N/A 17 Reserved – contains 0   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 35 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Name  Offset 
TDINFO  512 TDINFO_STRUCT  See 
3.9.7  Structure containing the TD’s attestable 
properties . 
• The hash of this structure is found in  
REPORTMACSTRUCT.TEE_INFO_HASH.  
• Size is determined by 
REPORTMACSTRUCT.REPORTTYPE.VERSION.  
See 3.9.7  for details.  
 
3.9.3.  TEE_TCB_INFO (Reference)  
TEE_TCB_INFO is defined in the [ TDX Arch Extensions Spec ].  The definition below is provided for reference.   Some details 
which are not applicable for TDX have been eliminated.  
The size of TEE_TCB_INFO is 239 bytes.  5 
Table 3.30:  TEE_TCB_INFO Definition  
VALID  0 8 Indicates which TEE_TCB_INFO fields are valid.  
• 1 in the ith significant bit reflects that the 8 bytes starting at 
offset (8 * i) are valid  
• 0 in the ith significant bit reflects that either 8 bytes starting at 
offset (8 * i) is not populated or reserved and is set to zero.  
Set to 0x301FF . 
TEE_TCB_SVN  8 16 TEE_TCB_SVN of the TDX module that created the TD.  
MRSEAM  24 48 The measurement of the TDX module that created the TD . 
MRSIGNERSEAM  72 48 Set to all 0’s.  
ATTRIBUTES  120 8 Set to all 0’s.

ATTRIBUTES  120 8 Set to all 0’s.  
TEE_TCB_SVN2  128 16 TEE_TCB_SVN of the current TDX module . 
RESERVED  144 95 Set to all 0’s.  
3.9.4.  TEE_TCB_SVN (Reference)  
TEE_TCB_SVN is defined in the [ TDX Arch Extensions Spec ].  The definition below is provided for reference.  
 
TDX_MODULE_SVN_MINOR  0 1 TDX module  minor  SVN  
TDX_MODULE_SVN_MAJOR  1 1 TDX module major SVN  
SEAM_LAST_PATCH_SVN  2 1 Microcode SE_SVN at the time the TDX module was loaded  
RESERVED  3 13 Must be Zero  
3.9.5.  REPORTMACSTRUCT  (Reference)  10 
Note:  REPORTMACS TRUCT is defined in the [ TDX Arch Extensions Spec ]; the definition below is provided for reference.  
REPORTMACSTRUCT is the first field in  the TEE report structure .  It is common to Intel’s Trusted Execution Environment s 
(TEEs ) – e.g., SGX and TDX.  In the TDX architecture , that  is TDREPORT_STRUCT .  REPORTMACSTRUCT is MAC -protected  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 36 of 329 
Intel TDX Application Binary Interface (ABI) Reference  and contains hash es of the remainder of the report structure which includes the TEE’s measurements , and where 
applicable, the measurements of additional TCB elements not reflected in REPORTMACSTRUCT.CPUSVN – e.g., a SEAM’s 
measurements.   
Software verifying a TEE report structure (for TDX, this includes TEE_TCB_INFO_STRUCT and TDINFO_STRUCT ) should 
check the following:  5 
1. Check that REPORTMACSTRUCT.TEE_INFO_HASH equals SHA384( TDINFO_STRUCT ). 
2. If REPORTMACSTRUCT.TEE_TCB_INFO_HASH is not 0, check that R EPORTMACSTRUCT.TEE_TCB_INFO_HASH  equals 
SHA384( TEE_TCB_INFO ). 
If all checks pass, the measurements in the structure describe a TEE on this platform.  
The size of REPORTMACSTRUCT is 256B. 10 
Table 3.31:  REPORTMACSTRUCT  Definition  
(Bytes)  Description  MAC  
REPORT TYPE  0 REPORTTYPE  4 Type Header Structure  Yes 
RESERVED  4  12 Must be zero  Yes 
CPUSVN  16 CPUSVN  16 CPU SVN  Yes 
TEE_TCB_INFO_HASH  32 SHA384_HASH  48 For TDX, SHA384 of TEE_TCB_ INFO  Yes 
TEE_INFO_HASH  80 SHA384_HASH  48 SHA384 of  TEE_INFO:   a  TEE-specific  info 
structure ( TDINFO_STRUCT  or SGXINFO) or 
0 if no TEE is represented  Yes 
REPORTDATA  128  64 A set of data used for communication 
between the caller and the targe t. Yes 
RESERVED  192  32 Must be zero  Yes 
MAC  224  32 The MAC over the REPORTMACSTRUCT 
with model -specific MAC  No 
 
3.9.6.  REPORTTYPE  (Reference)  
Note:   REPORTTYPE is defined in the [ TDX Arch Extensions Spec ]; the definition below is provided for reference.  
REPORTTYPE indicates the reported Trusted Execution Environment (TEE) type, sub -type and version.  15 
The size of REPORTTYPE  is 4B. 
Table 3.32:  TDX-Specific REPORTTYPE  Definition  
(Bytes)  Description  Value  
TYPE  0 1 Trusted Execution 
Environment 
(TEE) Type  
 0x00:  SGX 
0x7F -0x01:  Reserved (TEE implemented by CPU)  
0x80:  Reserved (TEE implemented by a SEAM 
module)  
0x81:  TDX  
0xFF -0x82:  Reserved (TEE implemented by a SEAM 
module)  
SUBTYPE  1 1 TYPE -specific 
subtype  0: Standard TDX report   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 37 of 329 
Other:  Reserved  
VERSION  2 1 TYPE -specific 
version.  
 For TDX, VERSION may have the following values:  
0: There are no bound nor pre -bound service TDs.  
TDINFO_STRUCT.SERVTD_HASH is not used (its 
value is 0).  
1:    TDINFO_STRUCT.SERVTD_HASH is used.  
RESERVED  3 1 Must be zero  0 
 
3.9.7.  TDINFO_STRUCT  
TDINFO_STRUCT  is defined as the TDX -specific TEE_INFO  part of TDG.MR.REPORT .  It contains the measurements and 
initial configuration of the TD th at was locked at initialization and a set of measurement registers that are run -time 
extendable.   These values are copied from the TDCS by the TDG.MR.REPORT  function .  Refer to the [ TDX Module Base 5 
Spec ] for additional details.  
TDINFO_STRUCT  is composed of  a base set of fields and an extension.  The content of the extension and the overall  size 
of TDINFO_STRUCT  depend on the report version, as specified in REPORTMACSTRUCT.REPORTTYPE.VERSION:  
• For REPORTTYPE.VERSION values of 0 and 1, TDREPORT_STRUCT’s size is 512 bytes.  
 10 
Table 3.33:  Overall TDINFO_STRUCT Definition  
(Bytes)  Size (Bytes)  Description  
TDINFO_BASE  0 448 Base TDINFO fields  
TDINFO_EXTENSION  448 The extension field depends on REPORTMACSTRUCT.REPORTTYPE.VERSION:  
REPORTTYPE.VERSION  Size  Description  
0, 1 64 Reserved, must be zero  
 
TDINFO _BASE  
Table 3.34:  TDINFO_ BASE  Definition  
(Bytes)  Type  Size (Bytes)  Description  
ATTRIBUTES  0  8 TD’s ATTRIBUTES  
XFAM  8  8 TD’s XFAM  
MRTD  16 SHA384_HASH  48 Measurement of the initial contents of the TD  
MRCONFIGID  64 SHA384_HASH  48 Software -defined ID for non -owner -defined 
configuration of the guest TD – e.g., run -time or OS 
configuration  
MROWNER  112 SHA384_HASH  48 Software -defined ID for the guest TD’s owner  
MROWNERCONFIG  160 SHA384_HASH  48 Software -defined ID for owner -defined configuration of 
the guest TD – e.g., specific to the workload rather than 
the run -time or OS   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 38 of 329 
RTMR  208 SHA384_HASH  4 * 48  Array of 4 run-time extendable measurement registers  
SERVTD_HASH  400 SHA384_HASH  48 If is one or more bound or pre -bound service TDs, 
SERVTD_HASH is the SHA384 h ash of the 
TDINFO_STRUCTs of those service TDs bound . 
Else, SERVTD_HASH is 0.  
 
3.10. Metadata Access  Types  
Note:  This section describes control structure field access types, as defined.  Implementation may differ.  
Metadata access  is described in the [ TDX Module Base Spec ]. 
3.10.1.  MD_FIELD_ID:  Metadata Field Identifier / Sequence Header  5 
MD_FIELD_ID is used for two purposes:  
Metadata Field Identifier : Used for specifying a single element of a metadata field  
Metadata Sequence Header : Used a s the header of a metadata  field sequence  
Lists of metadata field identifiers for global -scope metadata, TD -scope metadata and VCPU -scope metadata are provided 
in Ch. 4.  The metadata tables provide a base identifier .  The table below specifies which components of MD_FIELD_ID 10 
are taken from the base identifier; other components need to be specified as required . 
Table 3.35:  MD_FIELD_ID ( Metadata Field Identifier / Sequence Header ) Definition  
Bits Size  Name  From 
Metadata 
Tables ’ 
Base Field 
ID Single -
Element 
or 
Sequence  
Header  Description  
23:0  24 FIELD_CODE  Yes Both  For a single -element  identifier, identifies the element that is being 
accessed.  
For a metadata sequence header, identifies the first field that is 
being accessed in a sequence.  
31:24  8 RESERVED  No Both  Must be 0  
33:32  2 ELEMENT_SIZE_CODE  Yes Both  Size of a single element of a metadata field : 
0: 8 bits  
1: 16 bits  
2: 32 bits  
3: 64 bits  
For backward compatibility, TDH.MNG.RD, TDH.MNG.WR, 
TDH.VP.RD and TDH.VP.WR version 0 ignore this field and use a 
default value based on the field code.  
37:34  4 LAST_ELEMENT_  
IN_FIELD  No Sequence 
Header  Number of elements in a metadata field, minus 1  
For a single -element identifier, the value  is 0.  
This field is ignored when used as input to TD*.S YS.RDALL.  
46:38  9 LAST_FIELD_  
IN_SEQUENCE  No Sequence 
Header  Number of fields in a sequence, minus 1  
For a single -element  identifier, the value  is 0.  
49:47  3 RESERVED  Yes Both  Must be 0   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 39 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Bits Size  Name  From 
Metadata 
Tables ’ 
Base Field 
ID Single -
Element 
or 
Sequence  
50 1 INC_SIZE  Yes Sequence 
Header  For a single -element  identifier, INC_SIZE is ignored.  
For a sequence header, INC_SIZE specifies how FIELD_CODE is 
incremented when accessing consecutive elements in a sequence:  
0: Increment FIELD_CODE by 1 for each element.  
1: Increment FIELD_CODE by 2 for each element.  
INC_SIZE is designed to support VMCS field encoding, where bit 0 
(access type) is always 0 for full access.  
51 1 WRITE_MASK_VALID  No Both  Indicates that a write mask is provided together with the write 
value.  
For backward compatibility, single -element metadata write 
interface functions (e.g., TDH.MNG.WR, TDH.VP.WR etc.)  and use 
an implicit value of 1.  
This field is ignored by metadata read interface functions.  
54:52  3 CONTEXT_CODE  Yes Both  Specifies the context of the field:

Metadata 
Tables ’ 
Base Field 
ID Single -
Element 
or 
Sequence  
value.  
54:52  3 CONTEXT_CODE  Yes Both  Specifies the context of the field:  
0: Platform (whole Intel TDX module)  
1: TD 
2: TD VCPU  
All m etadata read and write interface functions (e.g., 
TDH.MNG.RD, TDH.MNG.WR, TDH.VP.RD, TDG.SYS.RDALL etc.) 
ignore this field when used as an input; they  use an implicit value.  
55 1 RESERVED  Yes Both  Must be 0  
61:56  6 CLASS_CODE  Yes Both  Identifies the class of the fields being accessed  
Class codes are defined in 3.10.3 . 
62 1 RESERVED  Yes Both  Must be 0  
63 1 NON_ARCH  Yes Both  Specifies forward compatibility, i.e., whether this field identifier 
will maintain their definition in a compatible way throughout Intel 
TDX module updates.  
0: Field identifier will maintain forward compatibility.  
1: Field identifier may not maintain forward compatibility.  
 
3.10.2.  Meaning of Field Codes  
For some field classes, field codes have an architectural meaning, as shown below.  For other classes, field codes are 
arbitrarily assigned.  
Table 3.36:  Meaning of Field  Codes  5 
Field Class  Field Code Meaning  Reference  
VMCS  Field code is the architectural VMCS field code.  The “HIGH” access type (for 
accessing the upper 32b of 64b fields) is not supported.  [Intel SDM, Vol. 3, 
24.11.2 and App. 
B] Bits Name  Description  
23:16  RESERVED  Must be 0   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 40 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Field Class  Field Code Meaning  Reference  
15:0  VMCS_FIELD_CODE  Bits 15:0 of the architectural VMCS field code  
Note:  Bits 32:16 of the VMCS field code are 
implicitly 0.  
MSR Bitmap  Offset (in 8B units) from the beginning of the architectural MSR bitmaps page  [Intel SDM, Vol. 3, 
24.6.9]  
Secure EPT 
Root  Offset (in 8B units) from the beginning of the page   
Page  Offset (in 8B units) from the beginning of the architectural virtual APIC page 
structure  [Intel SDM, Vol. 3, 
29.1]  
CPUID  Config  Each field contains two 64 -bit element, with the values returned by CPUID for 
the leaf and sub -leaf, as follows:  
Element 0[31:0]:   EAX Element 0[63:32]:   EBX 
Element 1[31:0]:  ECX  Element 1[63:32]:  EDX  
The field code is  packed as shown below:   
23:17  RESERVED  Must be 0  
16 LEAF_31  Leaf number bit 31  
15:9 LEAF_6_0  Leaf number bit 6:0  
Note:  Leaf bits 30:7 are implicitly 0.  
8 SUBLEAF_NA  Sub-leaf not applicable flag  
7:1 SUBLEAF_6_0  Sub-leaf number bits 6:0  
If SUBLEAF_NA is 1, then SUBLEAF_6_0 is all -1. 
Note:  Sub-leaf bits 31:7 are implicitly 0.  
0 ELEMENT_I  Element index within field  
GPR State  Architectural GPR number   
MSR State  Architectural MSR index, packed as shown below:   
Bits Description  
23:14 Reserved, must be 0  
13 Bit 31 (equal to bit 30) of the architectural MSR index  
12:0  Bits 12:0 of the architectural MSR index  
Extended State  Offset (in 8B units) from the beginning of the page extended state buffer   
Other  Arbitrary field identifiers   
November 2023  . Page 41 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3.10.3.  Class Codes  
3.10.3.1.  TDX Module Global Scope Field Class Codes  
TDX Module global scope field classes are defined as follows:  
Table 3.37:  TDX Module Global Scope Field Class  Codes  Definition  
Class Code  Field Class Name  
0 Platform Info  
8 TDX Module Version  
9 TDX Module Handoff  
10 TDX Module Info  
16 CMR Info  
17 TDMR Info  
24 TD Control Structures  
25 TD Configurability  
26 Memory Management  
27 Measurement  
32 Migration  
33 Service TD  
34 TD Partitioning  
48 TDX Connect  
 5 
3.10.3.2.  TD-Scope ( TDR and TDCS ) Field Class  Codes  
TD-scope  field classes are defined as follows:  
Table 3.38:  TD Scope (TD R and TDCS ) Field Class  Codes  Definition  
Class Code  Control Structure  Field Class Name  
0 TDR  TD Management  
1 TDR  Key Management  
2 TDR  TD Preserving  
3 TDR  TDX I/O  
16 TDCS  TD Management  
17 TDCS  Execution Controls  
18 TDCS  TLB Epoch Tracking  
19 TDCS  Measurement  
20 TDCS  CPUID  
21 TDCS  Zero Page  
22 TDCS  Virt. MSR Values  
24 TDCS  Migration  
25 TDCS  Service TD   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 42 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Class Code  Control Structure  Field Class Name  
26 TDCS  MIGSC Links  
27 TDCS  TDX I/O  
32 TDCS  MSR Bitmaps  
33 TDCS  Secure EPT Root  
37 TDCS  L2 Secure EPT Root [1]  
41 TDCS  L2 Secure EPT Root [2]  
45 TDCS  L2 Secure EPT Root [3]  
 
3.10.3.3.  VCPU -Scope ( TDVPS ) Field Class  Code s 
TDVPS field classes are defined as follows:  
Table 3.39:  TD VCPU Scope (TDVPS) Field Class  Codes  Definition  
0 TD VMCS  
1 VAPIC  
2 VE_INFO  
16 Guest GPR State  
17 Guest State  
18 Guest Ext. State  
19 Guest MSR State  
32 Management  
33 CPUID Control  
34 EPT Violation Log  
36 VMCS[1]  
37 MSR Bitmaps[1]  
38 MSR Bitmaps Shadow[1]  
44 VMCS[2]  
45 MSR Bitmaps[2]  
46 MSR Bitmaps Shadow[2]  
52 VMCS[3]  
 5 
3.10.4.  Order of Field Identifiers  
For usages such as TD migration, there is a need to define strict ordering between field identifiers.  For this purpose, we 
consider field identifiers to be orders by the following fields:  
1. CONTEXT_CODE  
2. CLASS_CODE  10 
3. FIELD_CODE  
3.10.5.  MD_LIST_HEADER:  Metadata List Header  
MD_LIST_HEADER is defined  below.  The size of MD_LIST_HEADER is 64 bits.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 43 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 3.40:  MD_LIST_HEADER Definition  
15:0  LIST_BUFF_SIZE  The size of memory buffer containing the list  
The buffer may be larger than the actual space occupied by the list; in this case 
the excess buffer space is ignored or read and may be overwritten on write.  
31:16  NUM_SEQUENCES  The number of metadata field sequences in the list.  
63:32  RESERVED  Reserved, set to 0  
 
3.10.6.  Private Page List  
A private page list specifies a list of HPAs of 4KB pages that are, or will become, TD private pages.  The list may have up 
to 512 64 -bit entries, each containing a 4KB -aligned HPA (HKID bits must be 0) of a page.  The list is contained in a single 5 
4KB page and must be aligned on 4KB.  The page list may contain null entries, indicated by the INVALID bit.  
Table 3.41:  Private Page List Entry  
11:0  RESERVED  Reserved:  must be 0 (unless bit 63 indicates an invalid entry)  
51:12  HPA  Bits 51:12 of the host physical address (HKID bits must be 0) of the 
migration buffer page  
62:52  RESERVED  Reserved:  must be 0 (unless bit 63 indicates an invalid entry)  
63 INVALID  A value of 1 indicates that this entry is invalid  
 
3.10.7.  HPA_AND_SIZE:  HPA and Size of a Buffer  
HPA_AND_SIZE is a 64-bit structure used to provide a buffer host physical address and size details.  10 
Table 3.42:  HPA_AND_SIZE  
51:0 HPA  Bits 51: 0 of the host physical address (including HKID bits) of the buffer   
63:52  SIZE  Size of the buffer, in bytes  
 
3.10.8.  HPA_AND_LAST:  HPA and Last Byte Index of a Page -Aligned Buffer  
HPA_AND_LAST is a 64 -bit structure used to provide a 4KB aligned buffer host physical address and size details.  
Table 3.43:  HPA_AND_LAST  15 
11:0  LAST  Index of the last byte in the buffer  
51:12  HPA  Bits 51:12 of the host physical address (including HKID bits) of the 4KB -
aligned buffer   
63:52  RESERVED  Reserved:  must be 0  
November 2023  . Page 44 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3.11. Service TD  Types  
3.11.1.  SERVTD_BINDING_TABLE:  Service TD Binding Table  
SERVTD_BINDING_TABLE is a table of service TD binding information, held in the TDCS.  For details, see the [TDX Module 
Base Spec].  
Table 3.44:  Service TD Binding Entry Definition  5 
Field  Type  Offset 
STATE  SERVTD_BINDING_STATE  0 1 See below and [TDX Module Base Spec]  
Reserved   1 1 Must be 0  
TYPE  SERVTD_TYPE  2 2 See below and [TDX Module Base Spec]  
Reserved   4 4 Must be 0  
ATTR  SERVTD_TYPE  8 8 See below and [TDX Module Base Spec]  
UUID  256-bit blob  16 32 See [TDX Module Base Spec]  
INFO_HASH  SHA384 _HASH  48 48 See [TDX Module Base Spec]  
Reserved   96 32 Must be 0  
TD-Preserving Update TDX Module Handoff Compatibility  
SERVTD_BINDING_TABLE is preserved in memory across TD -preserving updates.  The table below specifies the 
MODULE_HV versions for which the above MIGSC definition is appliable.  
Table 3.45:  SERVTD_BINDING_TABLE Compatibility with TD Preserving Updates  
Module Handoff Version  Value  
Minimum MODULE_HV  0 
Maximum MODULE_HV  0 
 10

 10 
3.11.2.  SERVTD_BINDING_STATE:  Service TD Binding State  
SERVTD_BINDING_STATE indicates the state of the service TD binding slot.  For details, see the [TDX Module Base Spec].  
Table 3.46:  SERVTD_BINDING_STATE Values  
Value  Name  
0 NOT_BOUND  
1 PRE_BOUND  
2 BOUND  
 
3.11.3.  SERVTD_TYPE:  Service TD Binding Type  15 
SERVTD_TYPE  is a 16 -bit field which specifies  the binding  type of a service TD.   For details, see the [TDX Module Base 
Spec].  
Table 3.47:  SERVTD_TYPE Definition  
Value  Meaning  Multiple Bindings  Metadata Access  
0 Migration TD  No Migration session key  
Other  Reserved  N/A N/A  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 45 of 329 
3.11.4.  SERVTD_ATTR:  Service TD Binging Attributes  
SERVTD_ATTR is a 64 -bit field which specifies binding attributes of a service TD.   For details, see the [TDX Module Base 
Spec].  
Table 3.48:  SERVTD_ATTR Definition  5 
0 INSTANCE_BINDING  0: Class Binding:   Rebinding can be done with any TD with the same 
SERVTD_INFO_HASH , SERVTD_TYPE and SERVTD_ATTR as the 
original binding.  Those parameters are migrated.  
1: Instance Binding:   Rebinding can be done with the same TD 
instance (same SERVTD_UUID), using the same SERVTD_TYPE and 
SERVTD_ATTR as the original binding . 
1 RESERVED  
 Must be 0  
 
2 RESERVED  
 Must be 0  
 
3 RESERVED  
 Must be 0  
 
31:4 RESERVED  Must be 0  
32 IGNORE_ATTRIBUTES  If set to 1, a value of 0 is used instead of the service TD’s ATTRIBUTES 
field when calculating SERVTD_INFO_HASH  
33 IGNORE_XFAM  If set to 1, a value of 0 is used instead of the service TD’s XFAM field 
when calculating SERVTD_INFO_HASH  
34 IGNORE_MRTD  If set to 1, a value of 0 is used instead of the service TD’s MRTD field 
35 IGNORE_MRCONFIGID  If set to 1, a value of 0 is used instead of the service TD’s MRCONFIGID 
36 IGNORE_MROWNER  If set to 1, a value of 0 is used instead of the service TD’s MROWNER 
37 IGNORE_MROWNERCONFIG  If set to 1, a value of 0 is used instead of the service TD’s MROWNER 
38 IGNORE_RTMR0  If set to 1, a value of 0 is used instead of the service TD’s RTMR0 field 
39 IGNORE_RTMR1  If set to 1, a value of 0 is used instead of the service TD’s RTMR1 field 
40 IGNORE_RTMR2  If set to 1, a value of 0 is used instead of the service TD’s RTMR2 field 
41 IGNORE_RTMR3  If set to 1, a value of 0 is used instead of the service TD’s RTMR3 field 
42 IGNORE_SERVTD_HASH  If set to 1, a value of 0 is used instead of the service TD’s 
SERVTD_HASH field when calculating SERVTD_INFO_HASH  
Other  RESERVED  Must be 0  
November 2023  . Page 46 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3.12. Migration  Types  
3.12.1.  MBMD:  Migration Bundle Metadata  
MBMD is composed of a common header and a variable type -specific information.  
3.12.1.1.  Generic MBMD Structure  
Table 3.49:  Generic MBMD Structure  Definition  5 
Field  Offset  
(Bytes)  Size  
(Bytes)  Description  Included 
In MAC  Included 
in IV  
SIZE  0 2 Overall size of the MBMD structure, in bytes  Yes No 
MIG_VERSION  2 2 Migration protocol version  
Changes in MBMB format, other migration bundle 
components format or migration protocol sequence 
require updating the protocol version.  
Migration protocol version is set by the MigTD before 
migration session starts . Yes No 
MIGS_INDEX  4 2 Index of the migration stream used for migrating this 
migration bundle  As 0  Yes 
MB_TYPE  6 1 The type of information being migrated:  
0: TD-scope  immutable non-memory state  
1: TD-scope mutable non-memory state  
2: VCPU -scope mutable non-memory state  
3–15: Reserved  
16: TD private memory  
17–31: Reserved  
32: Epoch token  
33: Abort token  
Other:  Reserved  Yes No 
RESERVED  7 1 Reserved, must be 0  Yes No 
MB_COUNTER  8 4 Per-stream migration bundle counter  
Starts from 0 on each migration epoch  start, 
incremented by 1 on each MBMD export to the 
associated stream.  Yes No 
MIG_EPOCH  12 4 Migration epoch  
Starts from 0 on migration session start, incremented 
by 1 on each epoch token.  
A value of 0x FFFFFFFF  indicates out -of-order phase.  Yes No 
IV_COUNTER  16 8 Monotonously incrementing counter, used as a 
component in the AES -GCM IV  As 0  Yes 
Type -Specific 
Information  24 Variable  Variable -sized additional information for each specific 
type of MBMD  Yes No 
MAC  24+V 16 AES-256-GCM MAC over other MBMD fields and any 
associated migration data (all the migration pages)  No No 
November 2023  . Page 47 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3.12.1.2.  TD-Scope Immutable Non -Memory State MBMD Fields  
Table 3.50:  TD -Scope Immutable Non -Memory State MBMD Fields Definition  
in IV  
NUM_ F_MIGS  24 2 Maximum number of forward migration streams that 
will be used  Yes No 
RESERVED  26 2 Reserved, must be 0  Yes No 
NUM_SYS_MD_PAGES  28 1 Number of pages in the page list used for migrating 
TDX module metadata  Yes No 
RESERVED  29 3 Reserved, must be 0  Yes No 
 
3.12.1.3.  TD-Scope Mutable Non -Memory State MBMD Fields  
Table 3.51:  TD -Scope Mutable Non -Memory State MBMD Fields Definition  5 
in IV  
RESERVED  24 8 Reserved, must be 0  Yes No 
 
3.12.1.4.  VCPU -Scope Mutable Non -Memory State MBMD Fields  
Table 3.52:  VCPU -Scope Mutable Non -Memory State MBMD Fields Definition  
in IV  
VP_INDEX  24 2 Virtual CPU index  Yes No 
RESERVED  26 6 Reserved, must be 0  Yes No 
 
3.12.1.5.  TD Private Memory  MBMD Fields  10 
Table 3.53:  TD Private Memory MBMD Type -Specific Fields Definition  
in IV  
NUM_GPAS  24 2 Number of entries in the GPA list  Yes No 
GPA_LIST_ATTRIBUTES  26 1 Attributes of the GPA list, see Table 3.54 below  Yes No 
RESERVED  27 5 Reserved, must be 0  Yes No 
 
Table 3.54:  GPA_LIST_ATTRIBUTES  
2:0 FORMAT  GPA list format  
0 GPA_ONLY  A GPA list page is provided  
1 GPA_AND_ ATTR  A GPA list page and a page attributes list  page 
are provided   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 48 of 329 
Other  RESERVED  Reserved  
7:3 RESERVED  Reserved:  must be 0  
 
3.12.1.6.  Epoch Token MBMD Fields  
Table 3.55:  Epoch Token MBMD Fields Definition  
in IV  
TOTAL_MB  24 8 The total number of migration bundles, including the 
current one, which have been exported since the 
beginning of the migration session  Yes No 
 
3.12.1.7.  Abort Token MBMD Fields  5 
Table 3.56:  Abort Token MBMD Fields Definition  
in IV  
 
3.12.1.8.  TD Migration Protocol Version  Compatibility  
The table below specifies the TD migration protocol  versions for which the above MBMD definition is appliable.  
Table 3.57:  MBMD Compatibility with TD Migration Versions  10 
TD Migration Version  Minimum  Maximum  
Export version  0 0 
Import version  0 0 
 
3.12.2.  GPA List  
A GPA list specifies a list of GPAs to migrated by TDH.EXPORT.MEM  and TDH.IMPORT.MEM , blocked for writing by 
TDH.EXPORT.BLOCKW or reset to their original SEPT entry state by TDH.EXPORT.RESTORE .  GPA list may have up to 512 
entries, is contained in a single 4KB page and must be aligned on 4KB.   The GPA list may contain null entries, as indicated 15 
by OPERATION field’s value set to 0 (NOP).  
3.12.2.1.   GPA_ LIST_INFO :  HPA , First and Last Entries of a GPA List  
GPA_LIST_INFO  is a 64b structure used as a GPR input and output operand of multiple migration interface functions, e.g., 
TDH.EXPORT.MEM.  It provides the HPA of the GPA list page in shared memory , and the index of the first entry and last 
entries to be processed . 20 
Table 3.58:  GPA_LIST_INFO  
0 GPA_ONLY  A GPA list page is provided   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 49 of 329

November 2023  . Page 49 of 329 
1 GPA_AND_L2_ATTR  A GPA list page and an L2 page attributes list page 
are provided.  This format is only used by 
TDH.EXPORT.MEM and TDH.IMPORT.MEM.  
11:3  FIRST_ENTRY  Index of the first entry of the list to be processed  
51:12  HPA  Bits 51:12 of the host physical address (including HKID) of the GPA list page, which 
must be a shared HPA  
54:52  RESERVED  Reserved:  must be 0  
63:55  LAST_ENTRY  Index of the last entry in the GPA list  
 
3.12.2.2.  GPA List Entry  
Table 3.59 below  shows the format of a GPA list entry as used.  The GPA list entry format is designed so that the output 
of TDH.EXPORT.BLOCKW can be used directly with TDH.EXPORT.MEM, and the output of TDH.EXPORT.MEM can be used 
directly with TDH.IMPORT.MEM.  5 
Table 3.59:  GPA List Entry Definition  
Bit(s)  Size  Name  Description  TDH.EXPORT.BLOCKW  TDH.EXPORT.MEM  TDH.IMPORT.MEM  TDH.EXPORT.RESTORE  
In Out In Out In Out In Out 
1:0 2 LEVEL  Mapping level 
(size)  Must be 0 
(4KB)  Unmod.  Must be 0 
(4KB)  Unmod.  
2 1 PENDING  See below  Ignored  Unmod.  Ignored  Yes Yes Unmod.  Ignored  Unmod.  
6:3 4 RESERVED  Reserved  Must be 0  Unmod.  Must be 0  Unmod.  Must be 0  Unmod.  Must be 0  Unmod.  
9:7 3 L2_MAP  See below  Ignored  Unmod.  Ignored  Yes Yes Unmod.  Ignore  Unmod.  
11:10  2 MIG_TYPE  See below  Yes Unmod.  Yes Unmod.  Yes Unmod.  Yes Unmod.  
51:12  40 GPA  Guest Physical 
Address bits 
51:12  Yes Unmod.  Yes Unmod.  Yes Unmod.  Yes Unmod.  
53:52  2 OPERATION  See below  Yes Yes Yes Yes Yes Yes Yes Yes 
55:54  2 RESERVED  Reserved  Must be 0  Unmod.  Must be 0  Unmod.  Must be 0  Unmod.  Must be 0  Unmod.  
60:56  5 STATUS  See below  Ignored  Yes Ignored  Yes Ignored  Yes Ignored  Yes 
63:61  3 RESERVED  Reserved  Must be 0  Unmod.  Must be 0  Unmod.  Must be 0  Unmod.  Must be 0  Unmod.  
 
3.12.2.3.  GPA List Entry Details  
GPA List Details:  LEVEL  
Reserved for future support of page sizes other than 4KB.  10 
GPA List Details:  PENDING  
Table 3.60:  PENDING Values Definition  
0 MAPPED  SEPT entry is MAPPED  
1 PENDING  SEPT entry is PENDING  
November 2023  . Page 50 of 329 
Intel TDX Application Binary Interface (ABI) Reference  GPA List Details:  L2_MAP  
A bitmap with indicates whether the page is mapped in one or more L2 VM.  This field is provided as part of the GPA list 
entry to enable the host VMM to prepare L2 SEPT pages before invoking TDH.IMPORT.MEM.  
GPA List Details:  OPERATION  
The following tables describe the meaning of OPERATION, as used for each applicable interface function.  Note that the 5 
OPERATION definitions for TDH.EXPORT.BLOCKW, TDH.EXPORT.MEM and TDH.IMPORT.MEM are designed to be 
compatible, so that the same GPA list can be used for all of them.  
Table 3.61:  OPERATION Values  Definition  for TDH.EXPORT.BLOCKW  
Value  Input  Output  
Name  Description  Name  Description  
0 NOP  No operation  NOP  Not blocked for writing  
1 BLOCKW  Block for writing  BLOCKW  Blocked for writing  
2 NOP  No operation  NOP  Not blocked for writing  
3 BLOCKW  Block for writing  BLOCKW  Blocked for writing  
 
Table 3.62:  OPERATION Values Definition  for TDH.EXPORT.MEM  10 
0 NOP  No operation  NOP  Not exported  
1 MIGRATE  Export  MIGRATE  Initial export during this migration 
session or following a CANCEL  
2 CANCEL  Cancel previous export  CANCEL  Cancellation of a previous export  
3 MIGRATE  Export  REMIGRATE  Re-export of updated content or 
attributes  
 
Table 3.63:  OPERATION Values Definition for TDH. IMPORT.MEM  
0 NOP  No operation  NOP  Not imported  
1 MIGRATE  Initial import during this migration 
session or following a CANCEL  MIGRATE  Imported  
2 CANCEL  Cancel previous import  CANCEL  Removed previous import  
3 REMIGRATE  Re-import of updated page content 
or attributes  REMIGRATE  Imported  
 
Table 3.64:  OPERATION Values Definition for TDH.EXPORT.RESTORE  
0 NOP  No operation  NOP  Not restored  
1 RESTORE  Restore SEPT entry to non -
migration state  RESTORE  Restored  
2 NOP  Reserved  NOP  Not restored   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 51 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Value  Input  Output  
3 RESTORE  Restore SEPT entry to non -
 
GPA List Details:  MIG_TYPE  
Table 3.65:  MIG_TYPE Values Definition  
0 PAGE_4K  4KB private memory page  
Other  RESERVED  Reserved for future types  
 
GPA List Details:  STATUS  5 
Table 3.66:  STATUS Values Definition  
0 SUCCESS  GPA list entry was processed successfully  
1 SKIPPED  GPA list entry was skipped because NOP was requested  
2 SEPT_WALK_FAILED  Secure EPT walk failed for the requested GPA  
3 SEPT_ENTRY_BUSY _HOST_PRIORITY  Secure EPT entry was busy .  The host VMM should retry 
the operation until successful.  
4 SEPT_ENTRY_STATE_INCORRECT  Secure EPT entry state was incorrect for the requested 
operation and the TD’s OP_STATE  
5 TLB_TRACKING_NOT_DONE  TLB tracking was not done for the requested GPA  
6 OP_STATE_INCORRECT  The TD’s OP_STATE was incorrect for the requested 
operation and Secure EPT entry state  
7 MIGRATED_IN_CURRENT_EPOCH  Requested GPA has already been migrated during the 
current migration epoch  
8 MIG_BUFFER_NOT_AVAILABLE  Required migration buffer was not provided  
9 NEW_PAGE_NOT_AVAILABLE  Required new TD page was not provided  
10 INVALID_PAGE_MAC  Page MAC was invalid  
11 DISALLOWED_IMPORT_OVER_REMOVED  Page import over a removed page is not allowed  
12 TD_PAGE_BUSY _HOST_PRIORITY  TD page was busy .  The host VMM should retry the 
operation until successful.  
13 L2_SEPT_WALK_FAILED  L2 Secure EPT walk failed for the requested GPA  
14 ATTR_LIST_ENTRY_INVALID  The L2 attributes list entry is invalid  
15 GPA_LIST_ENTRY_INVALID  The GPA list entry is invalid  
31-16 Reserved  Reserved  
 
3.12.2.4.  TD Migration Protocol Version Compatibility  
The table below specifies the TD migration protocol versions for which the above GPA List definition is appliable.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 52 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 3.67:  GPA List Compatibility with TD Migration Versions  
3.12.3.  Memory Migration Buffers List  
A memory migration buffer list specifies a list of HPAs of 4KB pages in shared memory, to be used as output by 
TDH.EXPORT.MEM  and as input by TDH.IMPORT.MEM .  The list may have up to 512 64 -bit entries, each containing a 4KB -
aligned HPA (including HKID bits) of a page in shared memory.  The list is contained in a single 4KB page and must be 5 
aligned on 4KB.  The page list may contain null entries, indicated by the INVALID bit.  
3.12.3.1.  Migration Buffers List Entry  
Table 3.68:  Migration Buffers List Entry  
51:12  HPA  Bits 51:12 of the host physical address (including HKID) of the migration 
buffer page, which must be a shared HPA  
 
3.12.4.  Page Attributes List 10 
A page attributes list  specifies a list of page aliases, to be used as output by TDH.EXPORT.MEM and as input by 
TDH.IMPORT.MEM.  The list must contain an entry for each respective GPA list entry used with the same interface 
functions.  The list may have up to 512 64 -bit entries , in page L2 attributes format as defined in 3.6.3 .  The list is contained 
in a single 4KB page and must be aligned on 4KB.  
3.12.5.  Memory Migration Page MAC List  15 
A page MAC list specifies a list of MACs over  4KB migrated pages , their GPA list entries  and (if applicable) page L2 
attributes list entries , to be used as output by TDH.EXPORT.MEM and as input by TDH.IMPORT.MEM .  The list must 
contain an entry for each respective GPA list entry used with the same interface functions.  The list may have up to 256 
128-bit entries, each containing a single AES -GMAC -256 of a migrated page.  The list is contained in a single 4KB page and 
must be aligned on 4KB.  20 
3.12.6.  Non -Memory State Migration Buffers List  
A non -memory state migration buffer list specifies a list of HPAs of 4KB pages in shared memory, to be used as output by

A non -memory state migration buffer list specifies a list of HPAs of 4KB pages in shared memory, to be used as output by 
TDH.EXPORT.STATE.* and as input by TDH.IMPORT.STATE.*.  The list may have up to 512 64 -bit entries, each containing 
a 4KB -aligned HPA ( including HKID bits) of a page in shared memory.  The list is contained in a single 4KB page and must 
be aligned on 4KB.  25 
3.12.6.1.  PAGE_LIST_INFO:  HPA and Attributes of a Page List  
PAGE_LIST_INFO is a 64b structure used as a GPR input and output operand of multiple migration interface functions, 
e.g., TDH.EXPORT.STATE.TD.  It provides the HPA of the migration buffers list page in shared memory, and the index of 
the last entry to be p rocessed.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 53 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 3.69:  PAGE_LIST_INFO  
11:0  RESERVED  Reserved:  must be 0  
51:12  HPA  Bits 51:12 of the host physical address (including HKID) of the page  list, 
which must be a shared HPA  
63:55  LAST_ ENTRY  Index of the last entry in the page list  
November 2023  . Page 54 of 329 
Intel TDX Application Binary Interface (ABI) Reference  4. TD Metadata (Non -Memory State)  
This chapter describes the details of TD metadata, a.k.a. non -memory state or control state . 
4.1. TD-Scope Metadata  
TD-scope control structures TDR and TDCS are described the [ TDX Module Base Spec ]. 
Information about TDR and TDCS is provided in a separate JSON format file td_scope_metadata .json . 5 
4.1.1.  TDR  
Note:  This section describes TDR, as defined.  Implementation may differ.  
TDR is the root control structure of a guest TD.  TDR is encrypted using the Intel TDX global private HKID.  It contains the 
minimal set of fields that allow TD management operation when the guest TD’s private ephemeral HKID is not known yet 
or when the TD’s key state is such that memory encrypted with the guest TD’s private ephemeral key i s not accessible.  10 
TDR occupies a single 4KB naturally aligned page of memory.  It is the first TD page to be allocated and the last to be 
removed.   None of the state in the TDR is migrated – it is locally initialized on the destination platform for a migrated TD.  
TRD fields are divided into the following classes:  
Table 4.1:  TDR Field Classes  Definition  
Field Class  Description  
TD Management  These fields are used to manage the TDR page, its descendent TD private memory 
pages and control structure pages.  
Key Management  These fields are used by the Intel TDX module  to manage memory encryption keys.  
See the [ TDX Module Base Spec ] for details.  
TD Preserving  These fields are used by the Intel TDX module  to manage the TD across TD 
preserving updates.  
 15 
4.1.2.  TDCS  
Note:  This section describes TDCS, as defined.  Implementation may differ.  
TDCS complements TDR as the logical control structure of a guest  TD.  TDCS is encrypted with the guest TS’s ephemeral 
private key.  It controls the guest TD operation and holds the state t hat is global to all the TD’s VCPUs.   TDCS state fields 
are initialized either via TDH.MNG.INIT, or via TDH.IMPORT.STATE.IMMUTABLE – the latter when the TD is the target for 20 
migration.  
TDCS fields are divided into the following classes:  
Table 4.2:  TDCS Field Classes  Definition  
TD Management  These fields are used to manage the TDCS, its descendent TD private memory pages 
and control structure pages.  
TD Execution Control  Control the execution of the guest TD:  some TD execution control fields are 
provided as an input to TDH.MNG.INIT , and some of those are included in the 
TDG.MR.REPORT . 
TLB Epoch Tracking  Track the TLB epoch of the guest TD – see the [ TDX Module Base Spec ] for details  
Measurement  TD measurement registers and associated fields – see the [ TDX Module Base Spec ] 
for details  
Migration  TDCS fields that control TD migration  
MIGSC Links  Links to Migration Stream Context pages   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 55 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Field Class  Description  
Service TD  TDCS fields that control Service TD binding and operation  
MSR Bitmaps  MSR bitmaps that control VM exit from the guest TD on RDMSR/WRMSR are 
common to all TD VCPUs and thus are stored as part of TDCS.  
Secure EPT Root Page  The root page (PML5 or PML4) of the secure EPT  
L2 Secure EPT 
Root[3:1]  The root pages (PML5 or PML4) of the secure EPTs associated with L2 VM 1, 2 and 3  
 
Following is some information about specific VMCS fields that is too extensive to provide in the JSON format files.  
4.1.2.1.  TDCS.TD_CTLS  
TD_CTLS is a bitmap of TD controls that may be modified during TD run time . 
Table 4.3:  TDCS.TD_CTLS Definition  5 
0 PENDING_VE_DISABLE  Control s the way guest TD access to a PENDING page is processed:  
0 (default) : An EPT violation due to guest TD access to a PENDING page 
results in a #VE.  
1: An EPT violation due to guest TD access to a PENDING page 
results in a TD exit.  
The above applies only to L1.  L2 VM access to a PENDING pages always 
results in an L2 →L1 exit.  
PENDING_VE_DISABLE’s initial value is copied from the TD’s 
ATTRIBUTES.SEPT_VE_DISABLE.  If the TD’s 
CONFIG_FLAGS.FLEXISBLE_PENDING_VE is 1, the TD is allowed to modify 
PENDING_VE_DISABLE using TDG.VM.WR.  
Enumeration:  Availability  of PENDING_VE_DISABLE is enumerated by 
TDX_FEATURES0.PENDING_EPT_VIOLATION_V2 (bit 16).  
1 ENUM _TOPOLOGY  Controls the enumeration of virtual  platform topology:  
0 (default) : Guest TD execution of CPUID(0xB) or CPUID(0x1F) results in a 
#VE.  C PUID(1).EBX[31:24] return s the least significant 8 bits of 
the VCPU index .  RDMSR of IA32_X2APIC_APICID (0x802) results 
in #VE.  
1: Guest TD execution of CPUID(0xB) or CPUID(0x1F) returns the 
virtual topology information configured by the host VMM.  
CPUID(1).EBX[31:24] return s the least significant 8 bits of the 
virtual x2APIC_ID configured by the host VMM.  RDMSR of 
IA32_X2APIC_APICID (0x802) return s the virtual x2APIC_ID.  
ENUM_TOPOLOGY can only be set to 1 if x2APIC_ID has been properly 
configured with unique values for each  VCPU .  The guest TD can read 
TDCS. TOPOLOGY_ENUM_CONFIGURED  using TDG.VM.RD to check that.  
Enumeration:  Availability  of ENUM _TOPOLOGY is enumerated by 
TDX_FEATURES0. TOPOLOGY_ENUM  (bit 20). 
63:2 RESERVED  Must be 0  
 
4.2. TDVPS:  VCPU -Scope Metadata  
Note:  This section describes TDVPS, as defined.  Implementation may differ.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 56 of 329 
Intel TDX Application Binary Interface (ABI) Reference  TDVPS is described in the [ TDX Module Base Spec ]. 
Information about TDVPS is provided in a separate JSON format file  vcpu_scope_metadata .json . 
4.2.1.  Overview  
Logically, in the Intel TDX module ’s linear address space, TDVPS is a single structure that holds the state and control 
information for a single TD VCPU.  The state is loaded to the LP on TD Entry and saved on TD exits . 5 
Physically, TDVPS is composed of a root page (TDVPR) and multiple extension pages ( TDCX ).   The pages need not be 
contiguous in physical memory.  
TDVPS is initialized by TDH. VP.INIT.  For an TD being migrated, TDVPS is imported by TDH.IMPORT.STATE.VP, which 
initializes some state fields and migrates some fields from the source TD VPS state.  
TDVPS fields are divided into the following classes:  10 
Table 4.4:  TDVPS Field Classes  Definition  
VCPU Management  These fields are used to manage the TDVPS and the TD VCPU . 
TD VMCS  The TD VCPU’s L1 VM architectural VMCS  
VAPIC  The TD VCPU’s Virtual APIC page  
VE_INFO  Holds Virtualization Exception (#VE) information  
Guest GPR State  TD VCPU’s general -purpose register state  
Guest MSR State  TD VCPU’s MSR state  
Guest Extended  State  TD VCPU’s extended state  
VMCS[3:1]  VMCS pages of L2 VM 1, 2 and 3  
MSR Bitmaps[3:1]  MSR bitmap pages of L2 VM 1, 2 and 3  
MSR Bitmaps Shadow[3:1]  MSR bitmap shadow pages of L2 VM 1, 2 and 3  
 
4.2.2.  TDVPS (excluding TD VMCS)  
4.2.3.  TD (L1) VMCS  and L2 VMCS  15 
Intel SDM, 24  Virtual Machine Control Structures  
Note:  This section describes VMCS usage, as defined.  Implementation may differ.  
TD (L1) VMCS  and L2 VMCS are  VMX -format VMCS (with TDX ISA  extension s) that are stored as part of TDVPS.  
Most of the i nformation about TD VMCS  and L2 VMCS  is provided in separate JSON format file s td_vmcs .json  and 
l2_vmcs.json . 20 
Following is some information about specific VMCS field s that is too extensive to provide in the JSON format files.  
4.2.3.1.  TD VMCS CR4 Guest/Host Mask  
Table 4.5:  TD VMCS CR4 Guest/Host Mask  
Bit Name  Value  Description

Bit Name  Value  Description  
6 MCE  1 Owned by the Intel TDX module  
13 VMXE  1 Owned by the Intel TDX module  
14 SMXE  1 Owned by the Intel TDX module   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 57 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Bit Name  Value  Description  
19 KL ~TDCS.ATTRIBUTES.KL  Intercept writes to CR4 if KeyLocker is not 
enabled  
22 PKE ~TDCS.XFAM[9]  Intercept writes to CR4 If PK is not enabled  
24 PKS ~TDCS.ATTRIBUTES.PKS  Intercept writes to CR4 if PKS is not enabled  
25 UINTR  ~TDCS.XFAM[14]  Intercept writes to CR4 if ULI is not enabled  
27 LASS  ~TDCS.ATTRIBUTES.LASS  Intercept writes to CR4 if LASS is not enabled  
Any bit set to 1 in IA32_VMX_CR4_FIXED0 
(i.e., a bit whose value must be 1)  1 Intercept writes of illegal values to CR4  
Any bit set to 0 in IA32_VMX_CR4_FIXED1 
(i.e., a bit whose value must be 0)  1 Intercept writes of illegal values to CR4  
Bits known to the Intel TDX module as 
reserved (bits 63:33, 31:29, 26 and bit 15)  1 Intercept writes of illegal values to CR4  
Other bits  0  
November 2023  . Page 58 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5. Interface Function s 
5.1. How to Read the Interface Function De finitions  
Note:  The description below is provided at a high level.  Actual details, order of checks, returned status codes, etc. may 
vary.  
A table of operands is provided for any function  that has explicit and/or implicit memory operands  or implicit resources .  5 
Table 5.1 below  describes how to read it.  Most of the background is detailed in the [ TDX Module Base Spec ]. 
Table 5.1:  How to Read the  Operands Information  Tables  
Explicit/  
Implicit  Reg. Ref Type  Resource  Resource 
Type  Access  Access 
Semantics  Alignment 
Check  Concurrency Restrictions  
Resource  Contain. 
2MB  Contain. 
1GB  
The 
operand 
may be 
specified 
explicitly 
or may 
be 
implicit  Register 
used as 
a 
pointer 
to the 
operand  How the 
operand is 
referenced:  
HPA , GPA , 
GPA and 
level  or 
index  Resource 
(memory 
or CPU 
internal) 
for this 
operand  Data type 
of the 
resource, 
as defined 
in Chapter  
3 or 
Chapter  4 Type of 
memory 
or 
resource 
access:  
R, RW, 
or Ref   Shared, 
Private, 
Opaque or 
Hidden  Required 
alignment 
of the 
operand  Concurrency restrictions are 
described in the [TDX Module Base 
Spec ]. 
For explicit memory accesses using 
HPA, there are additional 
concurrency restriction s on the 
1GB and 2MB blocks  that contain 
the accessed HPA .  For other types 
of accesses, only the operand 
concurrency is applicable.  
Shared(h) and Exclusive(h) 
indicate shared access with host -
side priority.  
Sh./Ex.(h) indicates either shared 
or exclusive access with host -side 
priority, depending on the 
platform type  
• On server platforms, access is 
shared . 
• On client platforms, access is 
exclusive . 
Shared(i) and Exclusive(i) indicate 
that the resource is implicitly 
restricted.  
 
5.2. Common Algorithms  Used by Multiple Interface Functions  
This section describes common algorithms  that are used by multiple interface functions.  10 
5.2.1.  VCPU Association with an LP  
The following algorithm is used for associating the current VCPU with the current LP.  It is used with VCPU -specific host -
side interface functions such as TDH.VP.ENTER, TDH.VP.RD etc.  
1. Check that the VCPU has been initialized and is not being torn down.  
2. Atomically check that the VCPU is not associated with another LP and  associate it with the current LP.  15 
3. If this is a new association, and the TD’s ephemeral HKID has changed since last association, update all TD VMCS 
physical pointers and the TD HKID execution control.  
4. Update the TD VMCS host state fields with any Intel TDX module LP -specific values.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 59 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.2.2.  Metadata Access  
5.2.2.1.  Single Metadata Field Read  
The following algorithm is used when reading a single metadata field based on a provided field identifier.  This algorithm 
is used by TDH.MNG.RD, TDH.VP.RD and TDG.VM.RD, TDG.VP.RD.  
Note:  The description below is provided at a high level.  Actual details, order of checks, returned status codes, etc. may 5 
vary.  
1. Check that the field identifier is valid and d erive a read  mask  depending on whether this algorithm is used by a host -
side or a guest -side interface function, and whether the TD runs in debug mode (ATTRIBUTES.DEBUG is 1).  
2. If the read  mask is 0, then fail; the field in not readable . 
If the above checks passed : 10 
3. Read the field value  from the control structure  using the proper method per field class.  
4. Mask the field value with the read mask derived above and  return the resulting value.  
4.1. In some cases, special handling is required.  E.g., the field value may need to be translated to another format, 
or some other action may be needed.  
5.2.2.2.  Single Metadata Field Write  15 
The following algorithm is used when writing a single metadata field based on provided field identifier, input value and 
write mask.  This algorithm is used by TDH.MNG.WR, TDH.VP.WR, TDG.VM.WR and TDG.VP.WR.  
vary.  
1. Check that the field identifier is valid and d erive the field attributes (read mask, write mask) depending on whether 20 
this algorithm is used by a host -side or a guest -side interface function, and whether the TD runs in debug mode 
(ATTRIBUTES.DEBUG is 1).  
2. If the write  mask is 0, then fail, the field in not writable.  
If passed : 
3. Calculate an effective write mask:  25 
3.1. If a write mask is provided as an input, d erive the effective write mask by bitwise -anding the write mask derived 
above with the write mask provided as an input . 
3.2. Else, the effective write mask is the write mask derived above . 
4. If the effective write mask is 0, then fail, the field in not writable.  
If passed:  30 
5. Read the old field value  from the control structure  using the proper method per field class . 
6. Calculate a new field value based on the input value and the effective write mask, and write  to the control structure  
using the proper method per field class . 
6.1. In some cases, special handling is required.  E.g., the new field value may need to be checked for validity, or 
some other action may be needed.  35 
If passed:  
7. Mask the old field value with the read mask derived above, and return the resulting value.  
5.2.2.3.  Multiple Metadata Fields Write based on a Metadata List  
The following algorithm  is used when writing multiple metadata fields based on a provided metadata list.   This algorithm 
is used by TDH.IMPORT.STATE.*.  40 
vary.  
1. Check the list header to be valid (NUM_SEQUENCES > 0).  
If passed : 
2. For each sequence in the list:  45 
2.1. Check that the list did not cross 4KB page boundary.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 60 of 329 
Intel TDX Application Binary Interface (ABI) Reference  2.2. Read the sequence header and check it is valid.  
If the above checks passed:  
2.3. For each field in the sequence:  
2.3.1.  Check that the list did not cross 4KB page boundary.  
2.3.2.  Check that the field identifier is valid and d erive a write  mask  depending on whether this algorithm is used 5 
by a host -side or a guest -side interface function, and whether the TD runs in debug mode 
2.3.3.  If the write  mask is 0, then fail, the field in not writable . 
If the above checks passed : 
2.3.4.  Calculate  an effective write mask:  10 
2.3.4.1.  If a write mask is provided for each field in the current sequence, d erive the effective write mask 
by bitwise -anding the write mask derived above with the write mask provided with the field . 
2.3.4.2.  Else, the effective write mask is the write mask derived above . 
2.3.5.  If the effective write mask is 0, then fail, the field in not writable.  
If passed:  15 
2.3.6.  Read the existing field value  from the control structure  using the proper method per field class.  
2.3.7.  Calculate a new field value based on the input value and the effective write mask, and w rite to the control 
structure  using the proper method per field class . 
2.3.7.1.  In some cases, special handling is required.  E.g., the new field value may need to be check ed for 
validity, or some other action may be needed.  20 
November 2023  . Page 61 of 329

November 2023  . Page 61 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3. Host -Side ( SEAMCALL ) Interface  Functions  
The SEAMCALL  instruction enters the Intel TDX module .  It is designed to call host -side Intel TDX functions , either local or 
a TD entry to a guest TD , as selected by RAX.  
5.3.1.  SEAMCALL  Instruction (Common)  
This section describes the common functionality of SEAMCALL .  Leaf functions are described in the following sections . 5 
Table 5.2:  SEAMCALL  Input Operands Definition  
RAX  Leaf and version numbers, as defined in the [ TDX Module Base Spec ].  See Table 5.4 below  for 
SEAMCALL leaf numbers.  
15:0  Leaf Number  Selects the SEAMCALL interface function  
23:16  Version Number  Selects the SEAMCALL interface function version  
Other  See individual SEAMCALL leaf functions . 
 
Table 5.3:  SEAMCALL Out put Operands Definition  
RAX  Instruction return  code , indicating the outcome of execution of the instruction .  See the [ TDX 
 
Table 5.4:  SEAMCALL Instruction  Leaf Number s Definition  10 
Leaf 
# Interface Function Name  Description  
0 TDH.VP.ENTER  Enter TDX non-root operation  
1 TDH.MNG.ADDCX  Add a control structure page to a TD  
2 TDH.MEM.PAGE.ADD  Add a 4KB private page to a TD during TD build time  
3 TDH.MEM.SEPT.ADD  Add and map a 4KB Secure EPT page to a TD  
4 TDH.VP.ADDCX  Add a control structure page to a TD VCPU  
5 TDH.MEM.PAGE.RELOCATE  Relocate a 4KB mapped page from its HPA to another  
6 TDH.MEM.PAGE.AUG  Dynamically add a 4KB private page to an initialized TD  
7 TDH.MEM.RANGE.BLOCK  Block a TD private GPA range  
8 TDH.MNG.KEY.CONFIG  Configure the TD private key on a single package  
9 TDH.MNG.CREATE  Create a guest TD and its TDR root page  
10 TDH.VP.CREATE  Create a guest TD VCPU and its TDVPR root page  
11 TDH.MNG.RD  Read TD metadata  
12 TDH.MEM.RD  Read from private memory of a debuggable guest TD  
13 TDH.MNG.WR  Write TD metadata  
14 TDH.MEM.WR  Write to private memory of a debuggable guest TD  
15 TDH.MEM.PAGE.DEMOTE  Split a 2MB or a 1GB private TD page mapping into 512 4KB or 2MB page 
mappings respectively  
16 TDH.MR.EXTEND  Extend the guest TD measurement register during TD build  
17 TDH.MR.FINALIZE  Finalize the guest TD measurement register   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 62 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Leaf 
18 TDH.VP.FLUSH  Flush the address translation caches and cached TD VMCS associated with a TD 
VCPU  
19 TDH.MNG.VPFLUSHDONE  Check all of a guest TD’s VCPUs have been flushed by TDH.VP.FLUSH  
20 TDH.MNG.KEY.FREEID  Mark the guest TD’s HKID as free  
21 TDH.MNG.INIT  Initialize per -TD control structures  
22 TDH.VP.INIT  Initialize the per -VCPU control structures  
23 TDH.MEM.PAGE.PROMOTE  Merge 512 consecutive 4KB or 2MB private TD page mappings into one 2MB or 
1GB page mapping respectively  
24 TDH.PHYMEM.PAGE.RDMD  Read the metadata of a page in a TDMR  
25 TDH.MEM.SEPT.RD  Read a Secure EPT entry  
26 TDH.VP.RD  Read VCPU metadata  
27 TDH.MNG.KEY.RECLAIMID  Does nothing; provided for backward compatibility  
28 TDH.PHYMEM.PAGE.RECLAIM  Reclaim a physical memory page owned by a TD (i.e., TD private page, Secure EPT 
page or a control structure page)  
29 TDH.MEM.PAGE.REMOVE  Remove a private page from a guest TD  
30 TDH.MEM.SEPT.REMOVE  Remove a Secure EPT page from a TD  
31 TDH.SYS.KEY.CONFIG  Configure the Intel TDX global private key on the current package  
32 TDH.SYS.INFO  Get Intel TDX module information  
33 TDH.SYS.INIT  Globally initialize the Intel TDX module  
34 TDH.SYS.RD  Read a TDX Module global -scope metadata field  
35 TDH.SYS.LP.INIT  Initialize the Intel TDX module per logical processor  
36 TDH.SYS.TDMR.INIT  Partially initialize a Trust Domain Memory Region (TDMR)  
37 TDH.SYS.RDALL  Read all host -readable TDX Module global -scope metadata fields  
38 TDH.MEM.TRACK  Increment the TD’s TLB tracking counter  
39 TDH.MEM.RANGE.UNBLOCK  Remove the blocking of a TD private GPA range  
40 TDH.PHYMEM.CACHE.WB  Write back the contents of the cache on a package  
41 TDH.PHYMEM.PAGE.WBINVD  Write back and invalidate all cache lines associated with the specified memory 
page and HKID  
43 TDH.VP.WR  Write VCPU metadata  
44 TDH.SYS.LP.SHUTDOWN  Does nothing; provided for backward compatibility  
45 TDH.SYS.CONFIG  Globally configure the Intel TDX module  
48 TDH.SERVTD.BIND  Bind a service TD to a target TD  
49 TDH.SERVTD.PREBIND  Pre-bind a service TD to a target TD  
52 TDH.SYS.SHUTDOWN  Shutdown the Intel TDX module and prepare handoff data  
53 TDH.SYS.UPDATE  Populate Intel TDX module state from handoff data  
64 TDH.EXPORT.ABORT  Abort an export session  
65 TDH.EXPORT.BLOCKW  Block a TD private page for writing  
66 TDH.EXPORT.RESTORE  Restore a list of TD private 4KB pages’ Secure EPT entry states after an export 
abort  
68 TDH.EXPORT.MEM  Export a list of TD private pages contents and/or cancellation requests  
70 TDH.EXPORT.PAUSE  Pause the exported TD  
71 TDH.EXPORT.TRACK  End the current in -order export phase epoch and either start a new epoch or start 
the out -of-order export phase  
72 TDH.EXPORT.STATE.IMMUTABLE  Start an export session and export the TD's immutable state  
73 TDH.EXPORT.STATE.TD  Export the TD's mutable state  
74 TDH.EXPORT.STATE.VP  Export a VCPU mutable state  
75 TDH.EXPORT.UNBLOCKW  Unblock a page that has been blocked for writing  
80 TDH.IMPORT.ABORT  Abort an import session  
81 TDH.IMPORT.END  End an import session  
82 TDH.IMPORT.COMMIT  Commit the import session and allow the imported TD to run  
83 TDH.IMPORT.MEM  Import a list of TD private pages contents and/or cancellation requests based on a 
migration bundle in shared memory  
84 TDH.IMPORT.TRACK  End the current in -order import phase epoch and either start a new epoch or start 
the out -of-order import phase   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 63 of 329 
85 TDH.IMPORT.STATE.IMMUTABLE  Start an import session and import the TD's immutable state  
86 TDH.IMPORT.STATE.TD  Import the TD's mutable state  
87 TDH.IMPORT.STATE.VP  Import a VCPU mutable state  
96 TDH.MIG.STREAM.CREATE  Create a migration stream  
 
Instruction Description  
vary.  
On entry, the Intel TDX module  performs the checks listed below  at a high level .  Errors cause a SEAMRET with RAX set 5 
to the proper completion status code.  
1. The leaf number in RAX is supported by the Intel TDX module . 
2. If the Intel TDX module ’s state is not SYS_READY, only TDH.SYS.RD *, TDH .SYS. INFO, TDH.SYS. INIT, TDH.SYS.LP.INIT , 
TDH.SYS. CONFIG, TDH.SYS.KEY.CONFIG  and TDH.SYS. SHUTDOWN leaf functions are allowed.  Those leaf function s 
then perform other initialization state checks.  10 
If all checks pass, the Intel TDX module  calls the leaf function according to the leaf number in RAX.  See the following 
sections for individual leaf function details.  
Completion Status Codes  
Table 5.5:  SEAMCALL  Completion Status Codes (Returned in RAX) Definition  
Completion  Status  Code  Description  
TDX_SUCCESS  SEAMCALL  is successful . 
TDX_SYS_SHUTDOWN   
  15  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 64 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.2.  TDH.EXPORT.ABORT Leaf  
TDH.EXPORT.ABORT aborts an export session and allows the source TD to resume normal operation, depending on export 
state and an abort token received from the destination platform.  
Table 5.6:  TDH.EXPORT.ABORT Input Operands Definition  
RAX  SEAMCALL instruction leaf number and version, see 5.3.1  
Must be 0  
RCX HPA of the source TD’s TDR page (HKID bits must be 0)  
R8 If an abort token is available, R8 provides the HPA and size of memory of an MBMD structure in 
memory, as described below.  
Otherwise, R8’s value must be 0.  
51:0  HPA  Bits 51:0 of the host physical address (including HKID bits)  
63:52  Size Size of the memory buffer containing MBMD, in bytes  
R10 Migration stream index:  
15:0  MIGS_INDEX  Migration stream index – must be 0  
63:16  RESERVED  Reserved:  must be 0  
 5

Must be 0  
 5 
Table 5.7:  TDH.EXPORT.ABORT Output Operands Definition  
RAX  SEAMCALL instruction return code,  see 5.3.1  
 
Leaf Function Description  
vary.  10 
TDH.EXPORT.ABORT aborts an export session.  If successful, i.e., the target TD does not  run, the source TD becomes 
runnable.  If called during the out -of-order phase, an abort token received from the destination platform is required.  
Enumeration:  Availability of TDH. EXPORT.ABORT is enumerated by TDX_FEATURES0.TD_MIGRATION (bit 0), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.EXPORT.ABORT returns a 15 
TDX_OPERAND_INVALID(RAX) status.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 65 of 329 
Intel TDX Application Binary Interface (ABI) Reference  To understand the table and text below, please refer to the [ TDX Module Base Spec ] chapter discussing general aspects 
of the Intel TDX Module API . 
Table 5.8:  TDH.EXPORT.ABORT Operands Information Definition  
Explicit/  
Implicit  Reg.  Ref 
Type  Resource  Resource 
Semantics  Align 
Operand  Contain. 
1GB  
Explicit  RCX HPA  TDR page  TDR  R Opaque  4KB Shared  Shared  Shared  
Explicit  R8 HPA  MBMD buffer  MBMD  R Shared  128B  None  None  None  
Explicit  R10 Index  Mig. Stream 
context  Mig. 
Stream 
context  RW Opaque  N/A Exclusive  N/A N/A 
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  N/A Shared(i)  N/A N/A 
Implicit  N/A N/A TDCS.OP_STATE  OP_STATE  RW Opaque  N/A Exclusive  N/A N/A 
Implicit  N/A N/A Migration 
context  N/A RW Opaque  N/A Exclusive  N/A N/A 
 
TDH.EXPORT.ABORT checks the memory operands per the table above when applicable during its flow.  The text below 5 
does not explicitly mention those checks, except when necessary.  
The function checks the following conditions:  
1. The TDR page metadata in PAMT must be correct (PT must be PT_TDR).  
2. The TD is not in a FATAL state (TDR.FATAL is FALSE).  
3. The TD keys are configured on the hardware (TDR.LIFECYCLE_STATE is TD_KEYS_CONFIGURED).  10 
4. TDCS has been allocated ( TDR.NUM_TDCX is the required number ). 
5. An export session is in progress but has not been committed yet:  TDCS.OP_STATE  is LIVE_EXPORT, PAUSED_EXPORT 
or POST_EXPORT.  
6. The migration stream index is 0. 
If successful, the function does the following:  15 
7. If the export session is in the post -copy phase (TDCS.OP_STATE is POST_EXPORT):  
7.1. Check that the buffer provided for MBMD is large enough.  
7.2. Copy the MBMD into a temporary buffer.  
7.3. Check the MBMD fields . 
If passed:  20 
7.4. If the migration stream  has not been initialized, initialize it.  
7.5. Build the 96b IV for this migration bundle by concatenating the stream index and the MBMD’s IV_COUNTER.  
7.6. Calculate MAC based on the MAC’ed fields of MBMD and check that its value is the same as the MBMD’s MAC 
field’s value.  
8. Else (the export session is in the pre -copy phase – TDCS.OP_STATE  is LIVE_EXPORT or PAUSED_EXPORT):  25 
8.1. Check that the MBMD HPA and size provided in R8 is 0.  
8.2. Check that the migration stream index provided in R10 is 0.  
If passed:  
9. Terminate the export session:  
9.1. Set all migration st reams’ INITIALIZED and ENABLED flags to FALSE.  30 
9.2. Set TDCS.OP_STATE to RUNNABLE.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 66 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Completion Status Codes  
Table 5.9:  TDH.EXPORT.ABORT Completion Status Codes (Returned in RAX) Definition  
Completion Status Code  Description  
TDX_INCORRECT_MBMD_MAC   
TDX_INVALID_MBMD   
TDX_OP_STATE_INCORRECT   
TDX_OPERAND_ADDR_RANGE_ERROR   
TDX_OPERAND_BUSY   
TDX_OPERAND_INVALID   
TDX_OPERAND_PAGE_METADATA_INCORRECT   
TDX_SUCCESS  Operation is successful  
TDX_SYS_NOT_READY   
TDX_TD_FATAL   
TDX_TD_KEYS_NOT_CONFIGURED   
TDX_TDCS_NOT_ALLOCATED   
 
November 2023  . Page 67 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.3.  TDH.EXPORT.BLOCKW Leaf  
Block a list of TD private 4KB pages for writing  and for attributes modification.  
Table 5.10:  TDH.EXPORT.BLOCKW Input Operands Definition  
Operand  Name  Description  
RAX  Leaf and 
Version  SEAMCALL instruction leaf number and version, see 5.3.1  
Must be 0  
RCX GPA_LIST_INFO  GPA_LIST_INFO:  HPA of a GPA list page in shared memory, and first and last 
entries to process, as defined in 3.12.2  
FORMAT must be GPA_ONLY.  
RDX  TDR  HPA of the source TD’s TDR page (HKID bits must be 0)  
 
Table 5.11:  TDH.EXPORT.BLOCKW Output Operands Definition  5 
RAX  STATUS  SEAMCALL instruction return code,  see 5.3.1  
RCX GPA_LIST_INFO  Same as the input value, except that FIRST_ENTRY is updated to the index of the 
next entry to be processed.  
If all entries have been processed, FIRST_ENTRY is updated to 
(LAST_ENTRY  + 1) Modulo  512.  
Other   Unmodified  
 
vary.  
For each 4KB page in the GPA list, if a blocking operation has been requested, TDH.EXPORT.BLOCKW finds the Secure EPT 10 
entry for the provided page.  If the entry state is correct ( MAPPED, PENDING, EXPORTED_DIRTY or 
PENDING_EXPORTED_DIRTY ), TDH.EXPORT.BLOCKW  blocks it  for writing , by saving and clearing the W bit and  setting 
the Secure EPT entry state (to BLOCKEDW, PENDING_BLOCKEDW,  EXPORTED_DIRTY_BLOCKEDW or 
PENDING_EXPORTED_DIRTY_BLOCKEDW respectively ).  It records the current TD’s TLB epoch in the  TD’s global 
BW_ EPOCH and  marks the GPA list entry as ready for export.   If the TD is partitioned, TDH.EXPORT.BLOCKW also blo cks 15 
any L2 SEPT entries mapping the 4KB page.  
Enumeration:  Availability of TDH. EXPORT.BLOCKW is enumerated by TDX_FEATURES0.TD_MIGRATION (bit 0), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.EXPORT.BLOCKW returns a 
TDX_OPERAND_INVALID(RAX) status.  
List Entry Error:  If a page can’t be blocked for writing, TDH.EXPORT.BLOCKW marks its GPA list entry as unsuccessful .  20 
List processing is not aborted, it continues to the next entry, if applicable.   The return status in RAX 
indicates the number of such cases encountered during operation.  
Interruptibility:  TDH.EXPORT.BLOCKW is interruptible.  If a pending interrupt is detected during operation, 
TDH.EXPORT.BLOCKW returns with a  TDX_INTERRUP TED_R ESUMABLE status in RAX.  RCX is updated  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 68 of 329 
Intel TDX Application Binary Interface (ABI) Reference  with the next list entry index to process, so the host BMM may re -invoke TDH.EXPORT.BLOCKW 
immediately after handling the interrupt.  
To understand the table and text below, please refer to the [ TDX Module Base Spec ] chapter discussing general aspects 
Table 5.12:  TDH. EXPORT .BLOCKW Memory Operands Information  5 
Explicit/  
1GB  
Explicit  RCX HPA  GPA List page  GPA_LIST  RW Shared  4KB None  None  None  
Explicit  RDX  HPA  TDR page  TDR  R Opaque  4KB Shared  Shared  Shared  
Explicit  N/A GPA  TD private 
page s (via GPA 
list) Block  None  Private  4KB None  None  None  
Implicit  N/A N/A TDCS.OP_STATE  OP_STATE  R Opaque  N/A Shared  N/A N/A 
context  N/A RW Opaque  N/A None  N/A N/A 
Implicit  N/A GPA  L1 Secure EPT 
tree  N/A RW Private  N/A Shared  N/A N/A 
entry  SEPT 
Entry  RW Private  N/A Exclusive(h)  N/A N/A 
Implicit  N/A GPA  L2 Secure EPT 
trees  N/A RW Private  N/A Shared(i)  N/A N/A 
entries  SEPT 
Entry  RW Private  N/A Exclusive(i)  N/A N/A 
 
TDH.MEM.RANGE.BLOCKW checks the memory operands per the table above when applicable during its flow.  The text 
below does not explicitly mention those checks, except when necessary.  
1. The TDR page metadata in PAMT must be correct (PT must be PT_TDR).  10 
2. The TD is not in a FATAL state (TDR.FATAL is FALSE).

entry  SEPT 
 
3. The TD keys are configured on the hardware (TDR.LIFECYCLE_STATE is TD_KEYS_CONFIGURED).  
4. TDCS is allocated ( TDR.NUM_TDCX is the required number ). 
5. Export session is in the in -order phase and the TD has not been paused yet ( TDCS. OP_STATE is LIVE_EXPORT).  
If passed, process the GPA list:  15 
Note:  Error conditions that impact a single GPA list entry do not cause an abort of TDH.EXPORT.BLOCKW.  Instead, the 
GPA list entry is updates with a proper status code, and the corresponding migration buffer list entry is marked 
as invalid.  
6. For each entry in the GPA list , starting with RCX.FIRST_ENTRY and ending with RCX.LAST_ENTRY, if OPERATION 
indicates a BLOCKW request:  20 
6.1. Check the GPA list entry fields value.  
If passed:  
6.2. Walk the L1 Secure EPT based on the GPA operand and find the Secure EPT entry to be blocked.  
6.3. Check the Secure EPT entry state:  it should be either of MAPPED, PENDING, EXPORTED_DIRTY or 
PENDING_EXPORTED_DIRTY.  25  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 69 of 329 
Intel TDX Application Binary Interface (ABI) Reference  6.4. If passed, update the SEPT entry and record the TD epoch:  
6.4.1.  Save the original value of SEPT.W into SEPT.TDW.  
6.4.2.  Clear SEPT.W.  
6.4.3.  Atomically set the SEPT entry  state to BLOCKEDW, PENDING_BLOCKEDW,  
EXPORTED_DIRTY_BLOCKEDW or PENDING_EXPORTED_DIRTY_BLOCKEDW as appropriate.  5 
6.4.4.  If the page state is MAPPED or EXPORTED_DIRTY, then for each L2 mapping of  the page:  
6.4.4.1.  Walk the L2 SEPT tree based on the GPA operand and find the L2 Secure EPT entry to be 
blocked for writing.  
6.4.4.2.  Save the original value of SEPT.W into SEPT.TDW.  
6.4.4.3.  Clear SEPT.W.  10 
6.4.4.4.  Set the L2 SEPT entry state to L2_BLOCKED  
Note:  If the page state is one of the PENDING* states, then the L2 SEPT entry state is already 
L2_BLOCKED, no change is required.  
6.4.5.  Copy  the TD’s epoch (TDCS.TD_EPOCH) to TDCS.BW_EPOCH . 
6.5. Else:  15 
6.5.1.  Set the GPA list entry’s OPERATION field to NOP and STATUS field to the applicable status.  
6.6. If this is not the last entry in the list, and there is a pending interrupt, terminate TDH.EXPORT.BLOCKW with a 
TDX_INTERRUPTED_RESUMABLE status.  
Table 5.13:  TDH.EXPORT.BLOCKW Completion Status Codes (Returned in RAX) Definitio n 20 
TDX_EPT_ENTRY_STATE_INCORRECT   
TDX_EPT_WALK_FAILED   
TDX_OPERAND_BUSY  Operation encountered a busy operand, indicated by the lower 
32 bits of the status.  In many cases, this can be resolved by 
retrying the operation.  
TDX_SUCCESS  Operation is successful.  
Note:  Processing of some GPA list entries may have encountered 
errors, but this did not cause an abort of the overall 
operation.  The number such errors is reported in the lower 
32 bits of the completion status.  
 
November 2023  . Page 70 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.4.  TDH. EXPORT .MEM  Leaf  
TDH.EXPORT.MEM  exports a list of TD private pages contents and/or cancellation requests and prepares a migration 
bundle in shared memory.  
Table 5.14:  TDH.EXPORT.MEM  Input Operands Definition  
RAX  Leaf and Version  SEAMCALL instruction leaf number and version, see 5.3.1  
Must be 0  
RCX GPA_LIST_INFO  HPA of a GPA list page in shared memory, and first and last entries to process, as 
defined in 3.12.2  
On a new invocation, FIRST_ENTRY must be 0.  On a resumed invocation, 
FIRST_ENTRY must be the index of the next GPA list entry to export.  
R8 MBMD  HPA and size of memory of a memory buffer to use for MBMD:  
R9 MIG_BUFF_LIST  HPA (including HKID bits) of a migration buffer list in shared memory, corresponding 
to the GPA list pointed by RCX – see 3.12.3 . 
R10 MIG_STREAM  Migration stream and resume flag:  
15:0  MIGS_INDEX  Migration stream index  
62:16  RESERVED  Reserved:  must be 0  
63 RESUME  0: This is a new invocation  
1: This is resumption of a previously interrupted 
operation  
R11 MAC_LIST_0  HPA (including HKID bits) of a MAC list in shared memory, corresponding to the first 
256 entries of the GPA list pointed by RCX – see 3.12.3 . 
If GPA_LIST_INFO.FIRST_ENTRY >= 256, then MAC_LIST_0 is ignored.  
R12 MAC_LIST_1  HPA (including HKID bits) of a MAC list in shared memory, corresponding to the last 
If GPA_LIST_INFO.LAST_ENTRY < 256, then MAC_LIST_1 is ignored.  
R14 ATTRIB_LIST  If GPA_LIST_INFO.FORMAT is GPA_AND_L2_ATTR, then R14 contains the HPA 
(including HKID bits) of a page attributes list in shared memory – see 3.12.4 . 
Else, R14 is ignored.  
 5  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 71 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.15:  TDH.EXPORT.MEM  Output Operands Definition  
RCX GPA_LIST_INFO  Same as the input value, except that FIRST_ENTRY is updated to the index of the next 
entry to be processed.  
RDX  NUM_EXPORTED  If TDH.EXPORT.MEM is successful , RDX returns the n umber of exported 4KB migration 
buffers , including : 
• The GPA list page  
• One or  two MAC pages  (depending on GPA_LIST_INFO.FIRST_ENTRY and 
GPA_LIST_INFO.LAST_ENTRY  
• Up to 512 encrypted memory pages  
If TDH.EXPORT.MEM is not successful,  RDX is unmodified.  
AVX, AVX2 
and 
AVX512 
state   May be reset to the architectural INIT state  
 
vary.  5 
Enumeration:  Availability of TDH. EXPORT.MEM is enumerated by either TDX_FEATURES0.TD_MIGRATION (bit 0) 
or TDX_FEATURES0.S4 (bit 13), readable by TDH.SYS.RD* (see 3.3.3.1 ), being set to 1.  If not 
supported, calling TDH.EXPORT.MEM returns a TDX_OPERAND_INVALID(RAX) status.  
TDH.EXPORT.MEM  exports a list of up to 512 TD private 4KB page s as a migration bundle, which includes an MBMD , set 
of 4KB pages encrypted with the migration session key , a 4KB page containing the GPA list , an optional 4KB containing 10 
page attributes list , and two 4KB pages containing page MACs . 
A GPA list is provided as an input.  For each page in the list, the requested operation may be either  of the following:  
• Export the page  (applies also to  re-export ing a previously exported page ). 
• Cancel a previous page export.  
It is also possible to skip entries in the list by requesting no operation for specific entries.  The GPA list format is described 15 
in 3.12.2 .  It is designed to be compatible with the output of TDH.EXPORT.BLOCKW  and the input of 
TDH.EXPORT.RESTORE.  
A list of 4KB page buffers is provided as an input.  In case no data is exported (PENDING page, page cancellation or some 
state error) TDH.EXPORT.PAGE marks the applicable list entry as invalid.  
Blocking and TLB Tracking:  If the TD may be running, the exported pages  must be blocked and TLB tracked.  Else (e.g., 20 
the TD has been paused for export), no blocking and tracking is required.  
Export  Error:  If a page can’t be exported, TDH.EXPORT.MEM marks its GPA list entry as unsuccessful, but 
does not abort.  It continues to the next entry, if applicable.  The return status in RAX 
Interruptibility:  TDH.EXPORT.MEM is interruptible.  If a pending interrupt is detected during operation, 25 
TDH.EXPORT.MEM returns with a TDX_INTERRUP TED_R ESUMABLE status in RAX.  RCX is 
updated with the next list entry index to process, so the host VMM may re -invoke 
TDH.EXPORT.MEM immediately after handling the interrupt, keeping the same inputs 
except setting R10.RESUME to 1.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 72 of 329

November 2023  . Page 72 of 329 
Table 5.16:  TDH.EXPORT.MEM  Operands Information Definition  
Explicit/  
1GB  
Explicit  R8 HPA  Memory to use 
for MBMD  MBMD  RW Shared  128B  None  None  None  
Explicit  R9 HPA  Migration 
buffer  list PAGE_LIST  RW Shared  4KB None  None  None  
Stream 
Explicit  R11 HPA  MAC list page 1  MAC list  RW Shared  4KB None  None  None  
Explicit  R12 HPA  MAC list page 2  MAC list  RW Shared  4KB None  None  None  
Explicit  R14 HPA  attributes list 
page  page 
attributes  R Shared  4KB None  None  None  
list) Blob R Private  4KB None  None  None  
Explicit  N/A HPA  Migration 
buffer  pages 
(via page list)  Blob  RW Shared  4KB None  None  None  
context  N/A RW Opaque  N/A Shared  N/A N/A 
entry  SEPT 
 
TDH.EXPORT.MEM  checks the memory operands per the table above when applicable during its flow.  The text below 5 
1. The TDR page metadata in PAMT must be correct (PT must be PT_TDR).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 73 of 329 
Intel TDX Application Binary Interface (ABI) Reference  2. The TD is not in a FATAL state (TDR.FATAL is FALSE).  
3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE is TD_KEYS_CONFIGURED).  
5. An export session is in progress . 
6. The migration stream index is lower than TDCS.NUM_MIGS.  5 
7. The buffer provided for MBMD is large enough.  
If successful, the function does the following:  
8. If the RESUME input flag is 0, indicating that this is a new (not resumed) invocation of TDH.EXPORT.MEM : 
8.1. If the migration  stream has not been initialized, initialize it.  
8.2. Increment the migration stream context’s IV_COUNTER  10 
8.3. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s 
IV_COUNTER.  
8.4. Build a local copy of the MBMD.  
8.5. Calculate the MBMD  MAC.  
8.6. Write the MBMD to memory.  15 
9. Else (this is a resumption of a previously interrupted TDH.EXPORT.MEM ): 
9.1. Check that the migration stream has been initialized.  
9.2. Check that the stream context’s INTERRUPTED_FUNC contains TDH.EXPORT.MEM ’s leaf number.  
9.3. Check that the current inputs are the same as saved in the stream context when the function was interrupted.  
If passed , process the GPA list:  20 
Note:  Error conditions that impact a single GPA list entry do not cause an abort of TDH.EXPORT.MEM.  Instead, the 
10. For each entry in the GPA list, starting with RCX.FIRST_ENTRY and ending with RCX.LAST_ENTRY:  
10.1. If no operation is requested, mark the corresponding migration buffer list entry as invalid and continue to the 25 
next GPA list entry.  
10.2. Check the GPA list entry fields value.  
If passed:  
10.3. Walk the L1 SEPT tree based on the GPA and level operands and find the leaf entry for the page.  
10.4. Check that the SEPT entry state is allowed for page export . 30 
10.5. If the TD is running (TDCS.OP_STATE is LIVE_EXPORT) and TLB tracking is required, check TLB tracking vs. 
TDCS.BW_EPOCH set previously by TDH.EXPORT.BLOCKW.  
10.6. Check that the requested operation is allowed in the current export phase.  
10.7. Check that the requested operation is allowed for the current SEPT entry state.  
10.8. If the  page has any L2 mappings , check that a page attributes list has been provided (GPA_LIST_INFO.FORMAT 35 
is GPA_AND_ATTR).  
Note:  TDH.EXPORT.MEM does not check that the page has not been exported in the current migration epoch 
during the in -order phase.  This is checked when the page is imported by TDH.IMPORT.MEM.  
10.9. If passed:  
10.9.1.  For each L2 mapping of the page:  40 
10.9.1.1.  Walk the L2  SEPT based on the GPA and level operands and find the leaf entry for the 
page (if any).  
10.9.2.  Update the page attributes list entry.  
10.9.3.  Update the L1 SEPT entry state, GPA list entry and migration buffer list entry.  
10.10.  Else:  45 
10.10.1.  Update the GPA list entry and migration buffer list entry  with error status.  
10.10.2.  For each L2 mapping of the page:  
10.10.2.1.  Walk the L2  SEPT based on the GPA and level operands and find the leaf entry for the 
10.10.3.  Update the page attributes list entry.  50 
10.11.  Increment the migration stream context’s IV_COUNTER  
10.12.  Build the 96b IV for this page  by concatenating 0 as the direction bit, the stream index and the stream 
context’s IV_COUNTER.  
10.13.  Accumulate page MAC based on the GPA list entry.  
10.14.  If a page attributes list has been provided, accumulate MAC based on the page attributes list entry.  55  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 74 of 329 
Intel TDX Application Binary Interface (ABI) Reference  10.15.  If the page content is to be exported, encrypt the TD private page into the migration buffer and accumulate 
MAC.  
10.16.  Write the page MAC to the MAC list.  
10.17.  If this is not the last round and there is a pending interrupt : 
10.17.1.  Save intermediate state in the  migration  stream context.  5 
10.17.2.  Terminate TDH.EXPORT.MEM  with a TDX_INTERRUPTED_RESUMABLE status.  
10.18.  Else, advance to the next entry in the GPA list, if applicable.  
11. Once the GPA list has been fully processed, update the migration stream next MB counter field.  
Table 5.17:  TDH.EXPORT.MEM  Completion Status Codes (Returned in RAX) Definition  10 
TDX_INTERRUPTED_RESUMABLE   
TDX_INVALID_RESUMPTION   
TDX_MIGRATION_STREAM_STATE_INCORRECT   
TDX_OPERAND_PAGE_INVALID   
November 2023  . Page 75 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.5.  TDH.EXPORT.PAUSE Leaf  
TDH.EXPORT.PAUSE starts the TDX -enforced blackout  period  on the source platform, where the source TD is pause d. 
Table 5.18:  TDH.EXPORT.PAUSE Input Operands Definition  
Must be 0  
RCX HPA of Source TD TDR page  (HKID bits must be 0)  
 
Table 5.19:  TDH.EXPORT.PAUSE Output Operands Definitions  5 
 
vary.  
TDH.EXPORT.PAUSE starts the Live Migration Blackout period  on the source platform.  10 
Enumeration:  Availability of TDH. EXPORT.PAUSE is enumerated by either TDX_FEATURES0.TD_MIGRATION (bit 
0) or TDX_FEATURES0.S4 (bit 13), readable by TDH.SYS.RD* (see 3.3.3.1 ), being set to 1.  If not 
supported, calling TDH.EXPORT.PAUSE returns a TDX_OPERAND_INVALID(RAX) status.

Must be 0  
 
vary.  
supported, calling TDH.EXPORT.PAUSE returns a TDX_OPERAND_INVALID(RAX) status.  
of the Intel TDX Module API . 15 
Table 5.20:  TDH.EXPORT.PAUSE Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDR page  TDR  R Opaque  4KB Exclusive  Shared  Shared  
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  N/A Exclusive(i)  N/A N/A 
Implicit  N/A N/A TDCS.OP_STATE  OP_STATE  RW Opaque  N/A Exclusive(i)  N/A N/A 
context  N/A RW Opaque  N/A Exclusive(i)  N/A N/A 
Implicit  N/A N/A TDCS Epoch 
Tracking Fields  N/A RW Opaque  N/A Exclusive (i) N/A N/A 
November 2023  . Page 76 of 329 
Intel TDX Application Binary Interface (ABI) Reference  TDH.EXPORT.PAUSE checks the memory operands per the table above when applicable during its flow.  The text below 
2. The TD is not in a FATAL state (TDR.FATAL is FALSE).  5 
5. TDCS.OP_STATE is LIVE_EXPORT.  
Note:  All TD VCPUs have stopped executing  and no other TD -specific SEAMCALL is running.  This is implicit, since 
TDH.EXPORT.PAUSE has an exclusive access to TDR and TDCS.  10 
6. Increment the TD’s epoch counter (TDCS.TD_EPOCH).  
Note:  This allows memory management operations to skip the need for blocking and TLB tracking while the TD is 
paused.  If  the export session is aborted, the first TDH.VP.ENTER on each VCPU will flush TLB.  
7. Set the TDCS.OP_STATE to PAUSED_EXPORT.  15 
Table 5.21:  TDH.EXPORT.PAUSE Completion Status Codes (Returned in RAX) Definition  
November 2023  . Page 77 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.6.  TDH.EXPORT.RESTORE Leaf  
TDH.EXPORT.RESTORE restores a list of TD private 4KB pages ’ Secure EPT entry state s after an export abort.  
Table 5.22:  TDH.EXPORT.RESTORE Input Operands Definition  
Must be 0  
FORMAT must be GPA_ONLY . 
 
Table 5.23:  TDH.EXPORT.RESTORE Output Operands Definition  5 
RCX GPA_LIST_INFO  Same as the input value, except that FIRST_ENTRY is updated to the index of 
the next entry to be processed.  
 
vary.  
TDH.EXPORT.RESTORE restores a list of TD private 4KB pages’ Secure EPT entry states after an aborted export session.  It  10 
reverts each  L1 Secure EPT entry and any applicable L2 Secure EPT entries to their  original non -exported state.  
Enumeration:  Availability of TDH. EXPORT.RESTORE is enumerated by TDX_FEATURES0.TD_MIGRATION (bit 0), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.EXPORT.RESTORE returns a 
List Entry Error:  If a page’s Secure EPT entry can’t be restored, TDH.EXPORT.RESTORE marks its GPA list entry as 15 
unsuccessful .  List process is  not abort ed; i t continues to the next entry, if applicable.  The return status 
in RAX indicates the number of such cases encountered during operation.  
Interruptibility:  TDH.EXPORT.RESTORE is interruptible.  If a pending interrupt is detected during operation, 
TDH.EXPORT.RESTORE returns with a TDX_INTERRUP TED_RSUMABLE status in RAX.  RCX is updated 
with the next list entry index to process, so the host VMM may re -invoke TDH.EXPORT.RESTORE 20 
of the Intel TDX Module API .  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 78 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.24:  TDH.EXPORT.RESTORE Operands Information Definition  
Explicit/  
1GB  
entry  SEPT 
 
TDH.EXPORT.RESTORE checks the memory operands per the table above when applicable during its flow.  The text 
The function checks the following conditions:  5 
5. TDCS. OP_STATE is RUNNABLE.  10 
If passed, process the GPA list:  
Note:  Error conditions that impact a single GPA list entry do not cause an abort of TDH.EXPORT.RESTORE.  Instead, the 
6. For each entry in the GPA list, starting with RCX.FIRST_ENTRY and ending with RCX.LAST_ENTRY, if OPERATION 15 
indicates a RESTORE request:  
If passed:  
6.2. Walk the L1 SEPT based on the GPA and level operands and find the leaf entry for the page.  
6.3. Check that the SEPT entry state is one of the EXPORTED_* or PENDING_EXPORTED_* states.  20 
6.4. If passed, update the SEPT entry:  
6.4.1.  Atomically decrement TDCS.MIG_COUNT.  
6.4.2.  If the SEPT state is one of the *_DIRTY* states, atomically decrement TDCS.DIRTY_CO UNT. 
6.4.3.  If the SEPT state is one of the PENDING_* states, update it to PENDING.  Else, update it to MAPPED.  
6.4.4.  If the page has any L2 mappings, and the SEPT state was one of the non -PENDING but BLOCKEDW 25 
states, then for each L2 SEPT:   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 79 of 329 
Intel TDX Application Binary Interface (ABI) Reference  6.6.1.1.  Walk the L2 SEPT tree based on the GPA operand and find the Secure EPT entry to be 
blocked.  
6.6.1.2.  If found:  
6.6.1.2.1.  Save the original value of SEPT.W into SEPT.TDW.  
6.6.1.2.2.  Clear SEPT.W.  5 
6.5. Else:  
6.6. If this is not the last entry in the list, and there is a pending interrupt, terminate TDH.EXPORT. RESTORE  with a 
Completion Status Codes  10 
Table 5.25:  TDH.EXPORT.RESTORE Completion Status Codes (Returned in RAX) Definition  
TDX_OPERAND_ADDR_RANGE_ERROR

blocked.  
6.5. Else:  
November 2023  . Page 80 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.7.  TDH.EXPORT.STATE.IMMUTABLE Leaf  
TDH.EXPORT.STATE.IMMUTABLE starts a new export session and exports the TD’s immutable state as a multi -page 
migration bundle.  
S4:  TDH.EXPORT.STATE.IMMUTABLE is also used for starting a new S4 hibernation session.  
Table 5.26:  TDH.EXPORT.STATE.IMMUTABLE Input Operands Definition  5 
Must be 0  
RCX TDR  Source TD handle and flags  
0 EXPORT_TYPE  0: TD Export  
1: S4 Hibernat ion 
11:1  Reserved  Must be 0  
51:12 TDR HPA  HPA[51:12] of the source TD’s TDR page (HKID bits 
must be 0)  
63:52  Reserved  Must be 0  
51:0  HPA  Bits 51:0 of the host physical address (including 
HKID bits)  
63:52  Size Size of the memory buffer containing MBMD, in 
bytes  
R9 PAGE_LIST_INFO  Migration buffers list information – see 3.12.6.1  
PAGE_LIST_INFO.FIRST_ENTRY must be 0.  
62:16 RESERVED  Reserved:  must be 0  
operation  
November 2023  . Page 81 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.27:  TDH.EXPORT.STATE.IMMUTABLE Output Operands Definition  
RDX  NUM_EXPORTED  Number of exported 4KB migration buffers  
AVX, AVX2 
and 
AVX512 
 
vary.  5 
TDH.EXPORT.STATE.IMMUTABLE starts a new export session.  It exports the TD’s immutable state as a migration bundle, 
which includes an MBMD and a set of 4KB pages, encrypted with the migration session key.  The migration bundle is 
protected by a MAC that is  stored in the MBMD.  
Enumeration:  Availability of TDH. EXPORT.STATE.IMMUTABLE is enumerated by either 
TDX_FEATURES0.TD_MIGRATION (bit 0) or TDX_FEATURES0.S4 (bit 13), readable by TDH.SYS.RD* 10 
(see 3.3.3.1 ), being set to 1.  If not supported, calling TDH.EXPORT.STATE.IMMUTABLE returns a 
Interruptibility:  TDH.EXPORT.STATE.IMMUTABLE is interruptible.  The host VMM is expected to invoke it in a loop 
until it returns with either a success indication or with a non -recoverable error indication.  
To understand the table and text below, please refer to the [ TDX Module Base Spec ] chapter discussing general aspects 15 
Table 5.28:  TDH.EXPORT.STATE.IMMUTABLE Operands Information Definition  
Explicit/  
1GB  
Explicit  R9 HPA  Page list  PAGE_LIST  RW Shared  4KB None  None  None  
Explicit  R10 N/A Mig. Stream 
Stream 
Explicit  N/A HPA  Destination 
pages (via page 
list) Blob  RW Shared  4KB None  None  None  
context  N/A RW Opaque  N/A Exclusive  N/A N/A  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 82 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Explicit/  
1GB  
Implicit  N/A N/A PL.S4_STATE  N/A RW Hidden  N/A Exclusive  N/A N/A 
 
TDH.EXPORT.STATE.IMMUTABLE checks the memory operands per the table above when applicable during its flow.  The 
text below does not explicitly mention those checks, except when necessary.  
1. The TDR page metadata in PAMT must be correct (PT must be PT_TDR).  5 
5. The TD build and measurement have been finalized, or the TD has been imported, and no export session is in progress 
(TDCS.OP_STATE is either RUNNABLE or LIVE_IMPORT).  10 
6. The TD is migratable:  TDCS.ATTRIBUTES.MIGRATABLE is set to 1.  
7. Any previous aborted export session has been cleaned up:  TDCS.MIG_COUNT is 0.  
8. MIGS_INDEX is 0.  
9. The buffer provided for MBMD is large enough.  
10. The number of pages in the page list is large enough to hold the exported state.  15 
Note:  The required number of pages is enumerated by TDH.SYS.RD *. 
11. If the RESUME input flag is 0, indicating that this is a new invocation of TDH.EXPORT.STATE.IMMUTABLE (not a 
resumption of a previously interrupted one):  
11.1. If EXPORT_TYPE is 0 (TD export):  20 
11.1.1.  Check that a valid migration decryption key has been set by the Migration TD.  If this is not the first 
migration session, then the migration key must have been set after the previous migration session has 
started.  
Note:  There is no explicit check that a migration TD is bound; this is implied by the above check.  
If passed:  25 
11.2. Initialize the migration context in TDCS:  
11.2.1.  Copy the migration keys to working migration keys that will be used throughout the export session.  
If passed:  
11.2.2.  Set all migration streams’ INITIALIZED flags to 0 and ENABLED flags to 1.  
11.3. Initialize the current migration stream.  30 
11.4. Increment the migration stream context’s IV_COUNTER.  
11.5. Build the 96b IV for this migration bundle by concatenating 0 as the direction bit, the stream index and the 
stream context’s IV_COUNTER.  
11.6. Build the MBMD in the migration stream context.  
11.7. Accumulate MAC in the stream context based on the MAC’ed fields of MBMD.  35 
12. Else (this is a resumption of a previously interrupted TDH.EXPORT.STATE.IMMUTABLE):  
12.1. Check that the resumption is valid:  
12.1.1.  The stream context indicates there’s a valid interruption state.  
12.1.2.  The current SEAMCALL leaf number and the PAGE_OR_LIST operand have the same value as  in the 
interruption state.  40 
12.2. Check that the migration stream is enabled.  
12.3. Restore the previously saved page list index from the migration context.  
12.4. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s 
If passed:  45 
13. Repeat exporting 4KB pages until all immutable state is exported or until a pending interrupt is detected:  
13.1. Get the 4KB next page HPA from it from the page list.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 83 of 329 
Intel TDX Application Binary Interface (ABI) Reference  13.2. Dump the next set of metadata fields as a metadata list of field sequences, into an internal temporary 4KB 
buffer.  
13.3. Use the migration key and the migration stream context to e ncrypt the 4KB internal buffer  into the destination 
data page  and update the MAC  calculation.  
13.4. If all immutable state has been exported:  5 
13.4.1.  Write the accumulated MAC to the MBMD in the stream context.  
13.4.2.  Write the MBMD to the memory buffer provided by the host VMM.  
13.4.3.  Mark the migration stream context’s interrupted state as invalid.  
13.4.4.  Increment the migration stream context’s NEXT_MB_COUNTER . 
13.4.5.  Set TDCS.TOTAL_MB to 1.  10

buffer.  
13.4.5.  Set TDCS.TOTAL_MB to 1.  10 
13.4.6.  Set TDCS.OP_STATE to LIVE_EXPORT.  
13.4.7.  Clear TDCS.DIRTY_COUNT to 0.  
13.4.8.  Terminate TDH.EXPORT.STATE.IMMUTABLE with a TDX_SUCCESS status.  
13.5. Else, if there is a pending interrupt:  
13.5.1.  Save the interruption state to the stream context  15 
13.5.2.  Terminate TDH.EXPORT.STATE.IMMUTABLE with a TDX_INTERRUPTED_RESUMABLE status.  
Table 5.29:  TDH.EXPORT.STATE.IMMUTABLE Completion Status Codes (Returned in RAX) Definition  
TDX_MAX_EXPORTS_EXCEEDED   
TDX_METADATA_LIST_OVERFLOW   
TDX_MIGRATION_SESSION_KEY_NOT_SET   
TDX_MIN_MIGS_NOT_CREATED   
TDX_PREVIOUS_EXPORT_CLEANUP_INCOMPLETE   
TDX_RND_NO_ENTROPY  Failed to generate a random migration encryption key.  This 
is typically caused by an entropy error of the CPU's random 
number generator, and may be impacted by RDSEED, 
RDRAND or PCONFIG executing on other LPs.  The operation 
should be retried.  
TDX_TD_NOT_MIGRATABLE    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 84 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Completion Status Code  Description  
November 2023  . Page 85 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.8.  TDH.EXPORT.STATE.TD Leaf  
TDH.EXPORT.STATE.TD exports a paused TD’s mutable state as a multi -page migration bundle.  
Table 5.30:  TDH.EXPORT.STATE.TD Input Operands Definition  
Must be 0  
RCX TDR  HPA of the source TD’s TDR page (HKID bits must be 0)  
operation  
 
Table 5.31:  TDH.EXPORT.STATE.TD Output Operands Definition  5 
AVX, AVX2 
and 
AVX512 
November 2023  . Page 86 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Leaf Function Description  
vary.  
TDH.EXPORT.STATE.TD exports the TD’s mutable state as a migration bundle, which includes an MBMD and a set of 4KB 
pages, encrypted with the migration session key.  The migration bundle is protected by a MAC that is stored in the MBMD.  5 
The TD must have been paused by a TDH.EXPORT.PAUSE.  
Enumeration:  Availability of TDH. EXPORT.STATE.TD is enumerated by either TDX_FEATURES0.TD_MIGRATION (bit 
supported, calling TDH.EXPORT.STATE.TD returns a TDX_OPERAND_INVALID(RAX) status.  
Interruptibility:  TDH.EXPORT.STATE.TD is interruptible.  The host VMM is expected to invoke it in a loop until it 10 
returns with either a success indication or with a non -recoverable error indication.  
Table 5.32:  TDH.EXPORT.STATE.TD Operands Information Definition  
Explicit/  
1GB  
Explicit  R9 HPA  Page list  PAGE_LIST  R Shared  4KB None  None  None  
Stream 
Implicit  N/A N/A TDCS.OP_STATE  OP_STATE  R Opaque  N/A Exclusive(h)  N/A N/A 
 15 
TDH.EXPORT.STATE.TD checks the memory operands per the table above when applicable during its flow.  The text below 
2. The TD is not in a FATAL state (TDR.FATAL is FALSE).  20 
5. An export session is in progress, and the TD has been paused:  TDCS.OP_STATE is PAUSED_EXPORT.  
6. Migration stream index is 0.  
7. The migration stream  is enabled and initialized.  25 
8. The buffer provided for MBMD is large enough.  
9. The number of pages in the page list is large enough to hold the exported state.  
Note:  The required number of pages is enumerated by TDH.SYS.RD *.  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 87 of 329 
Intel TDX Application Binary Interface (ABI) Reference  If successful, the function does the following:  
10. If the RESUME input flag is 0, indicating that this is a new invocation of TDH.EXPORT.STATE.TD (not a resumption of 
a previously interrupted one):  
10.1. Increment the migration stream context’s IV_COUNTER.  
10.2. Build the 96b IV for this migration bundle by concatenating 0 as the direction bit, the stream index (0) and the 5 
10.3. Build the MBMD in the migration stream context.  
10.4. Accumulate MAC in the stream context based on the MAC’ed fields of MBMD.  
11. Else (this is a resumption of a previously interrupted TDH.EXPORT.STATE.TD):  
11.1. Check that the resumption is valid:  10 
11.1.1.  The stream context indicates there’s a valid interruption state.  
11.1.2.  The current SEAMCALL leaf number and the PAGE_OR_LIST operand have  the same value as in the 
interruption state.  
11.2. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s 
IV_COUNTER.  15 
11.3. Restore the previously saved page list index from the migration context.  
If passed:  
12. Repeat exporting 4KB pages until all mutable TD state is exported or until a pending interrupt is detected:  
12.1. Get the 4KB next page HPA from it from the page list.  
12.2. Dump  the next set of metadata fields as a metadata list of field sequences, into an internal temporary 4KB 20 
buffer.  
12.3. Use the migration key and the migration stream context to e ncrypt the 4KB internal buffer  into the destination 
12.4. If all TD state has been exported:  
12.4.1.  Write the accumulated MAC to the MBMD in the stream context.  25 
12.4.2.  Write the MBMD to the memory buffer provided by the host VMM.  
12.4.3.  Mark the migration stream context’s interrupted state as invalid.  
12.4.4.  Increment the migration stream context’s NEXT_MB_COUNTER . 
12.4.5.  Increment TDCS.TOTAL_MB.  
12.4.6.  Terminate TDH.EXPORT.STATE.TD with a TDX_SUCCESS status.  30 
12.5. Else, if there is a pending interrupt:  
12.5.1.  Save the interruption state to the stream context  
12.5.2.  Terminate TDH.EXPORT.STATE.TD with a TDX_INTERRUPTED_RESUMABLE status.  
Table 5.33:  TDH.EXPORT.STATE.TD Completion Status Codes (Returned in RAX) Definition  35 
TDX_OPERAND_INVALID

TDX_OPERAND_PAGE_METADATA_INCORRECT    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
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November 2023  . Page 89 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.9.  TDH.EXPORT.STATE.VP Leaf  
TDH.EXPORT.STATE.VP exports a paused TD’s VCPU mutable state as a multi -page migration bundle.  
Table 5.34:  TDH.EXPORT.STATE.VP Input Operands Definition  
Must be 0  
RCX TDVPR  HPA of the source TD VCPU’s TDVPR page (HKID bits must be 0)  
51:0  HPA  Bits 51:0 of the host physical address (including HKID 
bits)  
operation  
 
Table 5.35:  TDH.EXPORT.STATE.VP Output Operands Definition  5 
AVX, AVX2 
and 
AVX512 
November 2023  . Page 90 of 329 
vary.  
TDH.EXPORT.STATE.VP exports a TD’s VCPU mutable state as a migration bundle, which includes an MBMD and a set of 
4KB pages, encrypted with the migration session key.  The migration bundle is protected by a MAC that is stored in the 5 
MBMD.  The TD must have been paused by a TDH.EXPORT.PAUSE.  
Enumeration:  Availability of TDH. EXPORT.STATE.VP is enumerated by either TDX_FEATURES0.TD_MIGRATION (bit 
supported, calling TDH.EXPORT.STATE.  
VP returns a TDX_OPERAND_INVALID(RAX) status.  10 
Interruptibility:  TDH.EXPORT.STATE.VP is interruptible.  The host VMM is expected to invoke it in a loop until it 
returns with either a success indication or with a non-recoverable error indication.  
VCPU Association : TDH.EXPORT.VP associates the TD VCPU with the current LP.  This requires that the VCPU will not be 
associated with another LP – for details, see the [ TDX Module Base Spec ]. 
Table 5.36:  TDH.EXPORT.STATE.VP Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDVPR page  TDVPS  RW Opaque  4KB Exclusive  Shared  Shared  
Stream 
Implicit  N/A HPA  TDR page  TDR  R Opaque  N/A Shared  N/A N/A 
 
TDH.EXPORT.STATE.VP checks the memory operands per the table above when applicable during its flow.  The text below 
does not explicitly mention those checks, except when necessary.  20 
1. The TDVPR page metadata in PAMT must be correct ( PT must be PT_TD VPR). 
4. TDCS is allocated ( TDR.NUM_TDCX is the required number ). 25 
6. Migration stream index is lower than TDCS.NUM_MIGS.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 91 of 329 
Intel TDX Application Binary Interface (ABI) Reference  7. The migration stream  is enabled . 
If successful, the function does the following:  5 
10. Associate the VCPU with the current LP, and update TD VMCS using the algorithm described in 5.2.1 . 
If passed:  
11. If the RESUME input flag is 0, indicating that this is a new invocation of TDH.EXPORT.STATE.VP (not a resumption of 
11.1. If the migration stream  has not been initialized, initialize it.  10 
11.2. Increment the migration stream context’s IV_COUNTER.  
11.3. Build the MBMD in the migration stream context.  
11.4. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s 
11.5. Accumulate MAC in the stream context based on the MAC’ed fields of MBMD . 15 
12. Else (this is a resumption of a previously interrupted TDH.EXPORT.STATE.VP):  
12.1.2.  The current SEAMCALL leaf number, and the TDVPR HPA  and PAGE_OR_LIST operands are the same as 
in the interruption state.  20 
12.2. Increment the migration stream context’s IV_COUNTER.  
13.1. Get the 4KB next page HPA from it from the page list.  
13.2. Dump  the next set of metadata fields as a metadata list of field sequences, into an internal temporary 4KB 25 
buffer.  
13.4. If all VCPU state has been exported:  
13.4.1.  Write the accumulated MAC to the MBMD in the stream context.  30 
13.4.5.  Increment TDCS.TOTAL_MB.  
13.4.6.  Terminate TDH.EXPORT.STATE.VP with a TDX_SUCCESS status.  35 
13.5.1.  Save the interruption state to the stream context  
13.5.2.  Terminate TDH.EXPORT.STATE.VP with a TDX_INTERRUPTED_RESUMABLE status.  
Table 5.37:  TDH.EXPORT.STATE.VP Completion Status Codes (Returned in RAX) Definition  40 
TDX_OPERAND_INVALID    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 92 of 329 
TDX_VCPU_ALREADY_EXPORTED   
November 2023  . Page 93 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.10.  TDH. EXPORT .TRACK Leaf  
TDH.EXPORT.TARCK e nds the current in -order export phase epoch and either start s a new epoch or start s the out -of-

order export phase.  Generate an epoch token to be exported to the destination platform.  
Table 5.38:  TDH.EXPORT.TRACK Input Operands Definition  
Must be 0  
R8 HPA and size of memory of a memory buffer to use for MBMD:  
R10 Migration stream and flags:  
63 IN_ORDER_DONE  Indicates that the in -order export phase is done  
 5 
Table 5.39:  TDH.EXPORT.TRACK Output Operands Definition  
AVX, AVX2 
and 
AVX512 
state  May be reset to the architectural INIT state  
 
vary.  10 
Enumeration:  Availability of TDH. EXPORT.TRACK is enumerated by either TDX_FEATURES0.TD_MIGRATION (bit 0) 
supported, calling TDH.EXPORT.TRACK returns a TDX_OPERAND_INVALID(RAX) status.  
If R10.IN_ORDER_DONE is 0, TDH.EXPORT.TRACK starts a new export epoch.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 94 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Else (R10. IN_ORDER_DONE is 1 ), TDH.EXPORT.TRACK checks that no memory exported so far needs to be re -exported.  If 
so, it ends the in -order export phase and starts the out -of-order phase.   
In both cases, TDH.EXPORT.TRACK generates an epoch token, to be exported on the specified migration stream.  
of the Intel TDX Module API . 5 
Table 5.40:  TDH.EXPORT.TRACK Operands Information Definition  
Explicit/  
1GB  
Stream 
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  N/A Shared (i) N/A N/A 
 
TDH.EXPORT.TRACK checks the memory operands per the table above when applicable during its flow.  The text below 
The function checks the following conditions:  10 
5. An export session is in the in -order phase:  TDCS.OP_STATE is either LIVE_EXPORT or PAUSED_EXPORT . 15 
7. The migration stream is initialized . 
9. If R10.IN_ORDER_DONE is 0:  20 
9.1. Increment TDCS.MIG_EPOCH  
10. Else (R10.IN_ORDER_DONE is 1):  
10.1. Check that an export session is in the in -order phase and the TD has been paused:  TDCS.OP_STATE is 
PAUSED_EXPORT.  
10.2. Check that TDCS.DIRTY_COUNT is 0, indicating that no unexported newer versions of any memory page 25 
exported so far remain.  Memory pages that have not yet been exported may remain and  may later be exported 
(out -of-order).  
If passed:  
10.3. Start the out -of-order phase:  
10.3.1.  Set TDCS.OP_STATE  to POST_EXPORT.  30 
10.3.2.  Set TDCS.MIG_EPOCH to 0xFFFFFFFF . 
11. Increment the migration stream context’s IV_COUNTER.  
12. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s IV_COUNTER.  
13. Create an epoch  token MBMD  with the following fields:  
13.1. The number of the new epoch that have just begun.  Bit 63 indicates the beginning of the out-of-order phase.  35  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 95 of 329 
Intel TDX Application Binary Interface (ABI) Reference  13.2. The total n umber of migration bundles (including the current one) that have been exported in the current 
migration session.  
14. Accumulate MAC based on the MAC’ed fields of MBMD and write to the MBMD’s MAC field’s value.  
15. Write the MBMD to the provided memory buffer.  
Completion Status Codes  5 
Table 5.41:  TDH.EXPORT. TRACK  Completion Status Codes (Returned in RAX) Definition  
TDX_EXPORTED_DIRTY_PAGES_REMAIN   
TDX_MIGRATION_EPOCH_OVERFLOW   
November 2023  . Page 96 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.11.  TDH.EXPORT.UNBLOCKW Leaf  
Remove the write -blocking of a 4KB TD private page  previously blocked by TDH.EXPORT.BLOCKW.  
Table 5.42:  TDH.EXPORT.UNBLOCKW Input Operands Definition  
Must be 0  
RCX EPT mapping information : 
2:0 Level  Level of the Secure EPT entry that maps the page to be blocked for 
writing – see 3.6.1 :  must be 0 (4KB)  
11:3  Reserved  Reserved:  must be 0  
51:12  GPA  Bits 51:12 of the GPA to be unblocked for writing  
63:52  Reserved  Reserved:  must be 0  
RDX  Host physical address of the parent TDR page  (HKID bits must be 0)  
 
Table 5.43:  TDH.EXPORT.UNBLOCKW Output Operands Definition  5 
RCX Extended error information part 1  
In case of EPT walk error, Secure EPT entry where the error was detected  
In other cases, RCX returns 0  
RDX  Extended error information part 2  
In case of EPT walk error, EPT level where the error was detected  
In other cases, RDX returns 0  
 
vary.  
TDH.EXPORT.UNBLOCKW finds the write blocked Secure EPT entry for the given GPA and level.  It verifies that the entry 10 
has been blocked for writing and TLB tracking has been done, then marks the entry as non -blocked for writing (MAPPED, 
PENDING, EXPORTED_DIRTY or PENDING_EXPORTED_DIRTY as appropriate).   If the page has any L2 mappings, 
TDH.EXPORT.UNBLOCKW unblocks them.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 97 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Enumeration:  Availability of TDH. EXPORT.UNBLOCKW is enumerated by TDX_FEATURES0.TD_MIGRATION (bit 0), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.EXPORT.UNBLOCKW returns a 
Table 5.44:  TDH.EXPORT.UNBLOCKW Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX GPA 
and 
Level  Secure EPT 
page or TD 
private page  Blob  None  Private  212+9*L evel 
Bytes  None  None  None  
Implicit  N/A N/A Migration

Explicit/  
1GB  
and 
page or TD 
Implicit  N/A GPA  L1 Secure EPT  
entry  SEPT 
 
TDH.EXPORT.UNBLOCKW checks the memory operands per the table above when applicable during its flow.  The text 
5. Either of the following is true:  15 
5.1. An export session is in progress . 
5.2. The TD is allowed to run ( TDCS. OP_STATE is either RUNNABLE, LIVE EXPORT, PAUSED_EXPORT or 
POST_EXPORT).  In these states, TDH.EXPORT.UNBLOCKW is used to clean up after an aborted export session.  
6. The specified level is 0 (4KB) . 
If successful, the function does the following:  20 
7. Walk the Secure EPT based on the GPA operand and find the Secure EPT page or TD private page to be unblocked 
8. Check the Secure EPT entry state is blocked for writing:  BLOCKEDW, PENDING_BLOCKEDW, 
EXPORTED_DIRTY_BLOCKEDW or PENDING_EXPORTED_DIRTY_BLOCKEDW.  
9. If the TD is allowed to run, c heck that TLB tracking was done.  25  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 98 of 329 
Intel TDX Application Binary Interface (ABI) Reference  If passed:  
10. If the page state is not one of the PENDING* states:  
10.1. Restore the original value of SEPT.W from SEPT.TDW . 
11. If the page has not been exported ( Secure EPT entry state is BLOCKEDW or PENDING_BLOCKEDW ), unblock the 
Secure EPT entry for writing by atomically setting its state to MAPPED or PENDING, respectively.  5 
12. Else (Secure EPT entry state is EXPORTED_DIRTY_BLOCKEDW or PENDING_EXPORTED_DIRTY_BLOCKEDW):  
12.1. Unblock the Secure EPT entry for writing by atomically setting its state to EXPORTED_DIRTY or 
PENDING_EXPORTED_DIRTY, respectively.  
12.2. Atomically increment TDCS.DIRTY_COUNT.  
13. If the updated page state is MAPPED or EXPORTED_DIRTY, then for each L2 mapping of the page:  10 
13.1. Walk the L2 SEPT tree based on the GPA operand and find the L2 Secure EPT entry to be unblocked for 
writing.  
13.2. Restore the original value of SEPT.W from SEPT.TDW.  
13.3. Set the L2 SEPT entry state to L2_MAPPED  
Note:  If the updated page state is one of the PENDING* states, then the L2 SEPT entry state is already L2_BLOCKED, 15 
no change is required.  
Table 5.45:  TDH.EXPORT.UNBLOCKW Completion Status Codes (Returned in RAX) Definition  
TDX_NOT_WRITE_BLOCKED   
TDX_SUCCESS  TDH.EXPORT. UNBLOCK W is successful  
TDX_TLB_TRACKING_NOT_DONE   
November 2023  . Page 99 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.12.  TDH. IMPORT .ABORT Leaf  
Abort an import session; after this the target TD can only be destroyed.  Generate an abort token that is to be consumed 
by the source platform.  
Table 5.46:  TDH.IMPORT.ABORT Input Operands Definition  
Must be 0  
RCX HPA of the source TD’s TDR page  (HKID bits must be 0)  
R10 Migration stream index – must be 0  
 5 
Table 5.47:  TDH.IMPORT.ABORT Output Operands Definition  
AVX, AVX2 
and 
AVX512 
 
vary.  10 
TDH.IMPORT.ABORT generates an abort token MBMD and sets the destination TD’s OP_STATE to IMPORT_FAILED.  In 
this state, the destination TD will not  run; it can only be destroyed.  This is indicated by the FATAL bit (61) of the 
completion status returned in RAX.  
Enumeration:  Availability of TDH. IMPORT.ABORT is enumerated by TDX_FEATURES0.TD_MIGRATION (bit 0), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.IMPORT.ABORT returns a 15 
November 2023  . Page 100 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.48:  TDH.IMPORT.ABORT Operands Information Definition  
Explicit/  
1GB  
Stream 
 
TDH.IMPORT.ABORT checks the memory operands per the table above when applicable during its flow.  The text below 
5. An import session is in progress but has not been committed yet  (TDCS.OP_STATE is one of MEMORY_IMPORT, 10 
STATE_IMPORT, POST_IMPORT or FAILED_IMPORT ). 
8. Set TDCS.OP_STATE to FAILED_IMPORT.  15 
9. If the migration stream has not been initialized, initialize it . 
10. Increment the stream context’s IV_COUNTER.  
11. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s IV_COUNTER.  
12. Create an abort token MBMD.  
13. Accumulate MAC based on the MAC’ed fields of MBMD and write to the MBMD’s MAC field’s value.  20 
14. Write the MBMD to the provided memory buffer.  
15. Increment the stream context’s NEXT_MB_COUNTER.  
Table 5.49:  TDH.IMPORT.ABORT Completion Status Codes (Returned in RAX) Definition  
November 2023  . Page 101 of 329 
November 2023  . Page 102 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.13.  TDH.IMPORT.COMMIT Leaf  
Commit an import session and allow the imported TD to run.  
Table 5.50:  TDH.IMPORT.COMMIT Input Operands Definition  
15:0  Leaf Number  Selects the SEAMCALL interface function

Must be 0  
 
Table 5.51:  TDH.IMPORT.COMMIT Output Operands Definition  5 
RAX  SEAMCALL instruction return code, see 5.3.1  
 
vary.  
TDH.IMPORT.COMMIT commits an import session and allows the important TD to run.  Post -copy memory import may 10 
continue.  
Enumeration:  Availability of TDH. IMPORT.COMMIT is enumerated by TDX_FEATURES0.TD_MIGRATION (bit 0), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.IMPORT.COMMIT returns a 
Table 5.52:  TDH.IMPORT.COMMIT Operands Information Definition  
Explicit/  
1GB  
 
TDH.IMPORT.COMMIT checks the memory operands per the table above when applicable during its flow.  The text below 
does not explicitly mention those checks, except when necessary.  20  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 103 of 329 
Intel TDX Application Binary Interface (ABI) Reference  The function checks the following conditions:  
4. TDCS is allocated (TDR.NUM_TDCX is the required number).  5 
5. An import session is in the out -of-order phase:  TDCS.OP_STATE is POST_IMPORT.  
6. Set TDCS.OP_STATE to LIVE_IMPORT.  
Table 5.53:  TDH.IMPORT.COMMI T Completion Status Codes (Returned in RAX) Definition  10 
November 2023  . Page 104 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.14.  TDH.IMPORT.END Leaf  
End an import session.  
Table 5.54:  TDH.IMPORT. END  Input Operands Definition  
Must be 0  
63:24  Reserved  Must be 0 
 
Table 5.55:  TDH.IMPORT. END  Output Operands Definition  5 
 
vary.  
TDH.IMPORT. END  ends  an import session and allows the important TD to run  (if not already allowed by 10 
TDH.IMPORT.COMMIT) . 
Enumeration:  Availability of TDH. IMPORT.END is enumerated by either TDX_FEATURES0.TD_MIGRATION (bit 0) or 
TDX_FEATURES0.S4 (bit 13), readable by TDH.SYS.RD* (see 3.3.3.1 ), being set to 1.  If not supported, 
calling TDH.IMPORT.END returns a TDX_OPERAND_INVALID(RAX) status.  
Table 5.56:  TDH.IMPORT. END  Operands Information Definition  
Explicit/  
1GB  
 
TDH.IMPORT. END  checks the memory operands per the table above when applicable during its flow.  The text below 
November 2023  . Page 105 of 329 
5. An import session is in the out -of-order phase.  
6. Set TDCS.OP_STATE to RUNNABLE . 
Table 5.57:  TDH.IMPORT. END  Completion Status Codes (Returned in RAX) Definition  10 
November 2023  . Page 106 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.15.  TDH.IMPORT.MEM  Leaf  
TDH.IMPORT.MEM imports a list of TD private pages contents and/or cancellation requests based on a migration bundle 
in shared memory.  
Table 5.58:  TDH.IMPORT.MEM  Input Operands Definition  
Must be 0  
On a new invocation, FIRST_ENTRY must be 0.  On a resumed invocation, FIRST_ENTRY 
must be the index of the next GPA list entry to export.  
RDX  TDR  HPA of the destination TD’s TDR page (HKID bits must be 0)  
R8 MBMD  HPA and size of memory of an MBMD structure in memory:  
R9 MIG_BUFF_LIST  HPA (including HKID bits) of a migration buffer list in shared memory, corresponding to 
the GPA list pointed by RCX – see 3.12.3 . 
No migration buffers are required for PENDING pages and for migration cancellation 
requests.  The list entries for such pages are skipped.  
operation  
R12 MAC_LIST_1  HPA (including HKID bits) of a MAC list in shared memory, corresponding to the last 256 
entries of the GPA list pointed by RCX – see 3.12.3 . 
If GPA_LIST_INFO.LAST_ENTRY < 256, then MAC_LIST_1 is ignored.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 107 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Operand  Name  Description  
R13 PAGE_LIST  If in-place import is requested for all pages imported for the first -time in the current 
import session, or for the first -time after a previous import cancellation, R13 should be 
set to NULL_PA (all 1’s).  
Otherwise, if some pages are to be imported in a non -in-place mode, R13 should be set

operation  
Otherwise, if some pages are to be imported in a non -in-place mode, R13 should be set 
to the HPA (including HKID bits) of a destination page list in shared memory, 
corresponding to the GPA list pointed by RCX – see 3.10.6 .  The page list allows 
selecting in -place or non -in-place import for each page imported for the first -time in 
the current import session, or for the first -time after a previous import cancellation : 
• To select in -place import, the page list entry’s INVALID bit should be set to 1 (it is 
possible to set the whole entry to NULL_PA).  
• To select non -in-place import, the page list entry should be set to the HPA 
(including HKID) of the page to become a new TD private page . 
R14 ATTRIB_LIST  If GPA_LIST_INFO.FORMAT is GPA_AND_L2_ATTR, then R14 contains the HPA (including 
HKID bits) of a page L2 attributes list in shared memory – see 3.12.4 . 
 
Table 5.59:  TDH.IMPORT.MEM  Output Operands Definition  
AVX, AVX2 
and 
AVX512 
 
vary.  
TDH.IMPORT.MEM  imports a list of up to 512 TD private 4KB pages based on a migration bundle, which includes an 
MBMD, set of 4KB pages encrypted with the migration session key, a 4KB page containing the GPA and attributes list , an 
optional 4KB containing page attributes list , and two 4KB pages containing page MACs.  
For each page in the migration bundle’s GPA list, the requested operation may either be to import the page, to re -import 10 
a newer version of the page (after a previous import) or to cancel a previous page import.  It is also possible to skip entri es 
in the l ist by requesting no operation for specific entries.  The GPA list format is described in 3.12.2 .   
Enumeration:  Availability of TDH. IMPORT.MEM is enumerated by either 
TDX_FEATURES0.TD_MIGRATION (bit 0) or TDX_FEATURES0.S4 (bit 13), readable by 
TDH.SYS.RD* (see 3.3.3.1 ), being set to 1.  If not supported, calling TDH.IMPORT.MEM 15 
returns a TDX_OPERAND_INVALID(RAX) status.  
Re-Import:  Re-import is only allowed during  the in -order import phase .  Th e imported pages replace 
an older version of the same pages, as long as the SEPT entry state is compatible:  
• If the old SEPT state is PENDING, it may be overwritten by a new version that is either 
PENDING or MAPPED.  20  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 108 of 329 
Intel TDX Application Binary Interface (ABI) Reference  • If the old SEPT state is MAPPED, it may be overwritten by a newer version that is 
MAPPED.  
Page attributes (e.g., RWX etc.) of a new page version may be different than those of a 
previously imported version.  
If the out -of-order import phase, the imported pages may not overwrite an older version 5 
of the same pages.  
In-Place Import:  First -time import of a page during the current import session, or following a previous 
import cancellation, may be done in -place; the same physical pages that are provided as 
input are converted to TD private pages.  Alternatively, a list of 4KB pages to b e used as 
the destination TD new private pages may be provided.  In any case, either a migration 10 
buffer or a new page must be provided, even if the imported page is PENDING and no 
content is imported.  
Re-import of a page is always done over the TD private page that holds the previously 
imported version.  
Import  Abort : In many cases, an error during import aborts the import session because the memory 15 
state of the imported TD can’t be guaranteed to be correct.  
If the import session has not been committed yet (by THD.IMPORT.COMMIT) and not yet 
entered the LIVE_IMPORT state where the TD is allowed to run, a failed 
TDH.IMPORT.MEM is considered fatal to the import session (except in cases where the 
imported TD state  has not been modified).  The target TD is marked as IMPORT_FAILED 20 
and, by design, will not  run.  This is indicated by the FATAL bit (61) of the completion status 
returned in RAX.  
If the import session has been committed and the entered the LIVE_IMPORT state where 
the TD is allowed to run, then a failed TDH.IMPORT.MEM terminates the import session 
(except in cases where the imported TD state has not been modified) but does not impac t 25 
the TD’s ability to run.  This is indicated by the FATAL bit (61) of the completion status 
returned in RAX . 
Interruptibility:  TDH.IMPORT.MEM is interruptible.  If a pending interrupt is detected during operation, 
TDH.IMPORT.MEM returns with a TDX_INTERRUP TED_RSUMABLE status in RAX.  RCX is 
updated with the next list entry index to process, so the host VMM may re -invoke 30 
TDH.IMPORT.MEM immediately after handling the interrupt, keeping the same inputs 
except setting R10.RESUME to 1.  
New Page Cache Flush : For each page that is imported for the first time (i.e., MIGRATE operation) not in -place , 
the host VMM should ensure that no cache lines associated with the separately provided 
physical page that is to be converted to a new TD private page are in a Modified state, as 35 
described in the [Base Spec].  
 This is not required for pages that are imported in -place.  It is also not required for re-
import (i.e., REMIGRATE  operation ). 
Removed Page Cache Flush:  After any private pages have been removed by a CANCEL operation, the host VMM should 
flush the  physical pages’ cache lines and initialize their content before they are reused, as 40 
Table 5.60:  TDH.IMPORT.MEM  Operands Information Definition  
Explicit/  
1GB  
Explicit  RDX  HPA  TDR page  TDR  RW Opaque  4KB Shared  Shared  Shared   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 109 of 329 
1GB  
Explicit  R8 HPA  MBMD  MBMD  R Shared  128B  None  None  None  
buffer list  PAGE_LIST  R Shared  4KB None  None  None  
Stream 
Explicit  R11 HPA  MAC list page 1  MAC list  R Shared  4KB None  None  None  
Explicit  R12 HPA  MAC list page 2  MAC list  R Shared  4KB None  None  None  
Explicit  R13 HPA  Destination 
page list  Blob  RW Private  4KB Exclusive  Shared  Shared  
Explicit  R14 HPA  L2 attributes 
list page  L2 page 
pages (via GPA 
list) Blob  None  Private  4KB None  None  None  
buffer pages 
list) Blob  RW Private  4KB Exclusive  Shared  Shared  
Implicit  N/A N/A TDCS.OP_STATE  OP_STATE  RW Opaque  N/A Shared  N/A N/A 
Entry  RW Private  N/A Exclusive  N/A N/A 
 
TDH.IMPORT.MEM  checks the memory operands per the table above when applicable during its flow.  The text below 
3. The TD keys are configured on the hardware (TDR.LIFECYCLE_STATE is TD_KEYS_CONFIGURED).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 110 of 329 
Intel TDX Application Binary Interface (ABI) Reference  4. TDCS is allocated ( TDR.NUM_TDCX is the required number ). 
5. An import session is in progress.

5. An import session is in progress.  
6. The migration stream index is lower than TDCS.NUM_MIGS.  
7. If the RESUME input flag is 0, indicating that this is a new (not resumed) invocation of TDH.IMPORT.MEM : 5 
7.1. Initialize the migration stream if not done so far . 
7.2. Copy the MBMD into a temporary buffer . 
If passed:  
7.4. Build the 96b IV for this migration bundle by concatenating 0 as the direction bit, the stream index and MBMD’s 10 
MB_COUNTER.  
7.5. Check the  MAC based on the MAC’ed fields of MBMD.  
8. Else (this is a resumption of a previously interrupted TDH.IMPORT.MEM ): 
8.1. Check that the stream context’s INTERRUPTED_FUNC contains TDH.IMPORT.MEM ’s leaf number.  
8.2. Check that the current inputs are the same as saved in the stream context when the function was interrupted.  15 
Note:  Error conditions that impact a single GPA list entry, but do not cause an import session about, do not cause an 
abort of TDH.IMPORT.MEM.  Instead, the GPA list entry is updates with a proper status code.  
9. For each entry in the GPA list, starting with RCX.FIRST_ENTRY and ending with RCX.LAST_ENTRY:  
9.1. Increment the migration stream context’s IV_COUNTER  20 
9.2. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s 
9.3. Accumulate page MAC based on the GPA list entry.  
9.4. If a page L2 attributes list was provided, accumulate page MAC based on the page L2 attributes list entry.  
9.5. If no operation is requested:  25 
9.5.1.  Check that the calculated MAC value is equal to the provided page MAC  value . 
If passed:  
9.5.2.  Mark the corresponding new page list entry (if available) as invalid and continue to the next GPA list 
entry.  
9.6. Walk the SEPT based on the GPA and level operands and find the leaf entry for the page.  30 
9.7. Check that the SEPT entry state is allowed for page import.  
9.8. If import is in the out -of-order phase, check that the requested operation in first -time import.  
9.9. If the requested operation if import or re -import, and the page state is not PENDING, check that a migration 
buffer is provided, and its address is a valid shared address.  
9.10. If the requested operation is first -time migrate : 35 
9.10.1.  Check that the SEPT entry state is either FREE or REMOVED.  
9.10.2.  If the SEPT entry state is REMOVED, check that the has not been removed in the current migration 
epoch.  
If passed:  
9.10.3.  If no new page list entry is provided, and a migration buffer is provided, this indicates in -place import.  40 
If the page is not PENDING, copy the migration buffer content to a temporary buffer.  The migration 
buffer page will become the new TD private page.  
9.10.4.  Else, check that the new page list entry is a valid shared HPA.  
9.10.5.  If the page is not PENDING, decrypt the migration buffer or temporary buffer into the new TD page.  
Use direct writes (MOVDIR64B ) and  accumulate MAC.  45 
9.10.6.  Check that the calculated MAC value is equal to the provided page MAC value.  
If passed:  
9.10.7.  Update the new TD page PAMT entry; record the current migration epoch value in PAMT.BEPOCH.  
9.10.8.  Update the SEPT entry.  
9.10.9.  If a page L2 attributes list was provided, then for each valid L2 attributes entry in the in the page 50 
attributes list entry:  
9.10.9.1.  Check that the alias VM index is not higher than TDCS.NUM_L2VMS   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 111 of 329 
Intel TDX Application Binary Interface (ABI) Reference  9.10.9.2.  Walk the L2 SEPT based on the GPA and level operands and find the FREE entry for the 
page alias.  
9.10.9.3.  Update the L2 SEPT entry based on the page L2 attributes list entry and the new TD page 
HPA.  
9.11. Else, if the requested operation is re -migrate:  5 
9.11.1.  Check that the SEPT entry state is either MAPPED or PENDING.  
9.11.2.  Using the page’s PAMT.BEPOCH, check that the page has not been imported in the current migration 
epoch.  
If passed:  
9.11.3.  Record the current migration epoch value in PAMT.BEPOCH.  10 
9.11.4.  If the page is not PENDING, decrypt the migration buffer or temporary buffer into the new TD page.  
Use direct writes (MOVDIR64B ) and  accumulate MAC.  
9.11.5.  Check that the calculated MAC value is equal to the provided page MAC value.  
If passed:  
9.11.6.  For each existing L2 page mapping  or, if a page attributes list was provided, each valid L2 page 15 
attributes entry  in the page attributes list entry:  
9.11.6.1.  In the page attributes list entry (if provided), check that the alias VM index is not higher 
than TDCS.NUM_L2VMS  
9.11.6.2.  Walk the L2 SEPT based on the GPA and level operands and find the leaf entry for the L2 
page.  20 
9.11.6.3.  Update the L2 SEPT entry based on the page attributes list entry (if provided).  If there is 
an existing  L2 page mapping  and no new L2 page attributes were  provided, set the L2 SEPT 
entry state to L2_FREE.  
9.11.7.  Update the SEPT entry.  
9.12. Else, if the requested operation is migration cancel:  25 
9.12.1.  Check that the SEPT entry state indicates that the page has been exported.  
9.12.2.  Calculate MAC over the GPA list entry and check that the value is equal to the provided page MAC 
value.  
9.12.3.  Using the page’s PAMT.BEPOCH, check that the page has not been imported in the current migration 
epoch.  30 
If passed:  
9.12.4.  For each existing L2 mapping of the page:  
9.12.4.1.  Walk the L2 SEPT based on the GPA and level operands and find the leaf entry for the page.  
9.12.4.2.  Set the L2 SEPT entry state to L2_FREE.  
9.12.5.  Update the SEPT entry; set the state to REMOVED and record the current migration epoch in the HPA.  35 
9.12.6.  Update the PAMT entry of the canceled page to PT_NDA.  
9.13. If this is not the last round and there is a pending interrupt:  
9.13.1.  Save intermediate state in the migration stream context.  
9.13.2.  Terminate TDH.EXPORT.MEM with a TDX_INTERRUPTED_RESUMABLE status.  
9.14. Else, advance to the next entry in the GPA list, if applicable.  40 
10. Once the GPA list has been fully processed , update the migration stream expected MB counter field.  
Table 5.61:  TDH.IMPORT.MEM  Completion Status Codes (Returned in RAX) Definition  
TDX_DISALLOWED_IMPORT_OVER_REMOVED   
TDX_IMPORT_MISMATCH   
TDX_INVALID_MBMD    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 112 of 329 
TDX_INVALID_PAGE_MAC   
TDX_MIGRATED_IN_CURRENT_EPOCH   
November 2023  . Page 113 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.16.  TDH.IMPORT.STATE. IMMUTABLE  Leaf  
TDH.IMPORT.STATE.IMMUTABLE starts a new import session and exports the TD’s immutable state as a multi -page 
Table 5.62:  TDH.IMPORT.STATE.IMMUTABLE Input Operands Definition  
Must be 0  
RCX TDR  Destination TD handle and flags  
0 Import Type  0: TD Import  
1: S4 Resumption  
51:12 TDR HPA  HPA[51:12] of the destination  TD’s TDR page (HKID bits 
must be 0)  
bits)  
63 RESUME  0: This is a new invocation

Must be 0  
must be 0)  
bits)  
operation  
November 2023  . Page 114 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.63:  TDH.IMPORT.STATE.IMMUTABLE Output Operands Definition  
RCX EXTENDED_  
ERROR_INFO1  In case of an interruption, as indicated by RAX returning 
TDX_INTERRUPTED_RESUMABLE, RCX is unmodified.  
In case of an error related to non-memory state field import, as indicated by RAX, 
RCX contains the offending field identifier .  See the status codes table below.  
In other cases, RCX returns 0.  
RDX  EXTENDED_  
ERROR_INFO2  In case of an interruption, as indicated by RAX returning 
TDX_INTERRUPTED_RESUMABLE, RDX is unmodified.  
In other cases, RDX returns 0.  
AVX, AVX2 
and 
AVX512 
 
vary.  5 
TDH.IMPORT.STATE.IMMUTABLE starts a new import session.  It imports the TD’s immutable state migration bundle 
previously exported by TDH.EXPORT.STATE.IMMUTABLE.   The migration bundle includes an MBMD and a set of 4KB 
pages.  
TD immutable state is verified by TDH.IMPORT.STATE.IMMUTABLE against target platform capabilities and Intel TDX 
module version, capabilities and configuration.  The checks are similar, but not identical, to the TD_PARAMS checks done 10 
on the source platform by TDH.MNG.INIT.  
Enumeration:  Availability of TDH. IMPORT.STATE.IMMUTABLE is enumerated by either 
TDX_FEATURES0.TD_MIGRATION (bit 0) or TDX_FEATURES0.S4 (bit 13), readable by TDH.SYS.RD* 
(see 3.3.3.1 ), being set to 1.  If not supported, calling TDH.IMPORT.STATE.IMMUTABLE returns a 
TDX_OPERAND_INVALID(RAX) status.  15 
Interruptibility:  TDH.IMPORT.STATE.IMMUTABLE is interruptible.  The host VMM is expected to invoke it in a loop 
until it returns with either a success indication or with a non-recoverable error indication.  
Import Abort:  A failed TDH.IMPORT.STATE.IMMUTABLE marks (except in cases where the imported TD state has 
not been modified)  the target TD as IMPORT_FAILED; by design, it will not run.  This is indicated by 
the FATAL bit (61) of the completion status returned in RAX.  20 
Table 5.64:  TDH.IMPORT.STATE.IMMUTABLE Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDR page  TDR  RW Opaque  4KB Exclusive  Shared  Shared  
Explicit  R8 HPA  MBMD  MBMD  R Shared  128B  None  None  None   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 115 of 329 
1GB  
Stream 
Explicit  N/A HPA  Source pages 
(via page list)  Blob  R Shared  4KB None  None  None  
 
TDH.IMPORT.STATE.IMMUTABLE checks the memory operands per the table above when applicable during its flow.  The 
5. The TD has not been initialized (TDCS.OP_STATE is UNINITIALIZED).  
6. A Migration TD has been bound to the source TD, and no migration session is in progress:  Migration Session State is 10 
MIG_TD_BOUND.  
7. The migration stream index is 0.  
8. The buffer provided for MBMD is large enough and fits within a 4KB page.  
9. If the RESUME input flag is 0, indicating this is a new invocation of TDH.IMPORT.STATE.IMMUTABLE (not a 15 
9.1. If IMPORT_TYPE is 0 (TD import):  
9.1.1.  Check that a valid migration decryption key has been set by the Migration TD.  If this is not the first 
started.  20 
If passed:  
9.2. Initialize the migration context in TDCS:  
9.2.1.  Copy the migration keys to working migration keys that will be used throughout the import session.  
9.2.2.  Generate a new migration encryption key, to be used in the next migration session.  25 
If passed:  
9.2.3.  Set all migration streams’ INITIALIZED flag to 0 and ENABLED flags to 1.  
9.3. Initialize the current migration stream.  
9.4. Copy the MBMD into the migration context.  
9.5. Check the MBMD fields . 30 
If passed:  
9.6. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s 
IV_COUNTER.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 116 of 329 
Intel TDX Application Binary Interface (ABI) Reference  9.7. Accumulate MAC based on the MAC’ed fields of MBMD.  
10. Else (this is a resumption of a previously interrupted TDH.IMPORT.STATE.IMMUTABLE):  
10.1. Check that the resumption is valid:  
10.1.1.  The stream context indicates there’s a valid interruption state.  
10.1.2.  The current SEAMCALL leaf number and the PAGE_OR_LIST operand are the same as in the interruption 5 
state.  
10.2. Check that the migration stream is enabled.  
10.3. Restore the previously saved page list index from the migration context.  
If passed:  
11. Repeat importing 4KB pages until all immutable state is imported or until a pending interrupt is detected:  10 
11.1. Get the 4KB next page HPA from it from the page list.  
11.2. Use the migration key and the migration stream context to de crypt the 4KB internal buffer  into an internal 
temporary 4KB buffer  and update the MAC  calculation.  
11.3. Parse the metadata list and write the control structure fields using the algorithm described in 5.2.2.3 .  Check 
each TDR or TDCS field for compatibility.  15 
If passed:  
11.4. If all metadata lists have been imported:  
11.4.1.  Check that the accumulated MAC value is equal to the saved MBMD’s MAC value.  
11.4.2.  Check that all global, TDR and TDCS metadata fields required to be imported by 
TDH.IMPORT.STATE.IMMUTABLE have indeed been imported.  20 
11.4.3.  Do validity checks of TDR and TDCS metadata fields that can only be checked at this stage . 
11.4.4.  Initialize TDR and TDCS fields that need to be initialized at the beginning of the import session.  
11.4.5.  Mark the migration stream context’s interrupted state as invalid.  
11.4.6.  Increment the migration stream context’s EXPECTED_MB_COUNTER . 
11.4.7.  Set TDCS.TOTAL_MB to 1.  25 
11.4.8.  Set TDCS.OP_STATE to MEMORY_IMPORT.  
11.4.9.  Terminate TDH.IMPORT.STATE.IMMUTABLE with a TDX_SUCCESS status.  
11.5. Else, if there is a pending interrupt:  
11.5.1.  Save the interruption state to the stream context  
11.5.2.  Terminate TDH.IMPORT.STATE.IMMUTABLE with a TDX_INTERRUPTED_RESUMABLE status.  30 
Table 5.65:  TDH.IMPORT.STATE.IMMUTABLE Completion Status Codes (Returned in RAX) Definition  
TDX_INVALID_METADATA_LIST_HEADER   
TDX_METADATA_FIELD_ID_INCORRECT  Field ID or sequence header is return ed in RCX  
TDX_METADATA_FIELD_NOT_WRITABLE  Field ID is return ed in RCX  
TDX_METADATA_FIELD_VALUE_NOT_VALID  Field ID is return ed in RCX  
TDX_NUM_MIGS_HIGHER_THAN_CREATED    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 117 of 329

November 2023  . Page 117 of 329 
TDX_REQUIRED_METADATA_FIELD_MISSING  Required f ield ID is return ed in RCX  
TDX_RND_NO_ENTROPY  Failed to generate a random migration encryption key.  This is 
typically caused by an entropy error of the CPU's random 
number generator, and may be impacted by RDSEED, RDRAND 
or PCONFIG executing on other LPs.  The operation should be 
retried.  
TDX_X2APIC_ID_INVALID   
TDX_X2APIC_ID_NOT_UNIQUE   
November 2023  . Page 118 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.17.  TDH.IMPORT.STATE.TD Leaf  
TDH.IMPORT.STATE.TD imports the TD -scope mutable state as a multi -page migration bundle.  
Table 5.66:  TDH.IMPORT.STATE.TD Input Operands Definition  
Must be 0  
RCX TDR  HPA of Destination TD TDR page (HKID bits must be 0)  
operation  
 
Table 5.67:  TDH.IMPORT.STATE.TD Output Operands Definition  5 
RCX contains the offending field identifier.   See the status codes table below.  
ERROR_INFO 2 In case of an interruption, as indicated by RAX returning 
In other cases, RDX returns 0.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 119 of 329 
AVX, AVX2 
and 
AVX512 
 
vary.  
TDH.IMPORT.STATE.TD imports the TD -scope mutable state migration bundle previously exported by 5 
TDH.EXPORT.STATE.TD.   The migration bundle includes an MBMD and a set of 4KB pages.  
TD-scope mutable state is verified by TDH.IMPORT.STATE.TD against target platform capabilities and Intel TDX module 
version, capabilities and configuration.  
Enumeration:  Availability of TDH. IMPORT.STATE.TD is enumerated by either TDX_FEATURES0.TD_MIGRATION (bit 
0) or TDX_FEATURES0.S4 (bit 13), readable by TDH.SYS.RD* (see 3.3.3.1 ), being set to 1.  If not 10 
supported, calling TDH.IMPORT.STATE.TD returns a TDX_OPERAND_INVALID(RAX) status.  
Interruptibility:  TDH.IMPORT.STATE.TD is interruptible.  The host VMM is expected to invoke it in a loop until it 
Import Abort:  A failed TDH.IMPORT.STATE.TD marks (except in cases where the imported TD state has not been 
modified ) the target TD as IMPORT_FAILED; by design, it will not  run.  This is indicated by the FATAL 15 
bit (61) of the completion status returned in RAX.  
Table 5.68:  TDH.IMPORT.STATE.VP Operands Information Definition  
Explicit/  
1GB  
Stream 
Implicit  N/A N/A Service TD 
bindings table  N/A R Hidden  N/A Exclusive(i)  N/A N/A 
 20  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 120 of 329 
Intel TDX Application Binary Interface (ABI) Reference  TDH.IMPORT.STATE.TD checks the memory operands per the table above when applicable during its flow.  The text below 
5. An import session is in progress, but TD -scope mutable state has not been imported yet (TDCS.OP_STATE is 
MEMORY_IMPORT).  
6. The migration stream index is 0.  10 
7. The migration stream is enabled.  
9. If the RESUME input flag is 0, indicating this is a new invocation of TDH.IMPORT.STATE.TD (not a resumption of a 
previously interrupted one):  15 
9.1. Copy the MBMD into the migration context.  
9.2. Check the MBMD fields . 
If passed:  
9.3. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s 
IV_COUNTER.  20 
9.4. Accumulate MAC based on the MAC’ed fields of MBMD.  
10.1.2.  The current SEAMCALL leaf number and the PAGE_OR_LIST operand are the same as in the interruption 25 
state.  
10.2. Restore the previously saved page list index from the migration context.  
If passed:  
11. Repeat importing 4KB pages until all immutable state is imported or until a pending interrupt is detected:  
11.1. Get the 4KB next page HPA from it from the page list.  30 
each TDR or TDCS field for compatibility.  
If passed:  35 
11.4.2.  Check that all TDR and TDCS fields required to be imported by TDH.IMPORT.STATE.TD have indeed been 
imported.  
11.4.3.  Initialize TDR and TDCS fields that need to be initialized at the end of the import session.  40 
11.4.4.  Mark the migration stream context’s interrupted state as invalid.  
11.4.5.  Increment the migration stream context’s EXPECTED_MB_COUNTER . 
11.4.6.  Increment TDCS.TOTAL_MB.  
11.4.7.  Set TDCS.OP_STATE to STATE_IMPORT.  
11.4.8.  Terminate TDH.IMPORT.STATE.TD with a TDX_SUCCESS status.  45 
11.5.2.  Terminate TDH.IMPORT.STATE.TD with a TDX_INTERRUPTED_RESUMABLE status.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 121 of 329 
Table 5.69:  TDH.IMPORT.STATE.TD Completion Status Codes (Returned in RAX) Definition

imported.  
Table 5.69:  TDH.IMPORT.STATE.TD Completion Status Codes (Returned in RAX) Definition  
November 2023  . Page 122 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.18.  TDH.IMPORT.STATE.VP Leaf  
TDH.IMPORT.STATE.VP imports the VCPU -scope mutable state as a multi -page migration bundle.  
Table 5.70:  TDH.IMPORT.STATE.VP Input Operands Definition  
Operand   Description  
Must be 0  
RCX TDVPR  HPA of the destination  TD VCPU’s TDVPR page (HKID bits must be 0)  
operation  
 
Table 5.71:  TDH.IMPORT.STATE.VP Output Operands Definition  5 
November 2023  . Page 123 of 329 
AVX, AVX2 
and 
AVX512 
 
vary.  
TDH.IMPORT.STATE.VP imports the VCPU -scope mutable state migration bundle previously exported by 5 
TDH.EXPORT.STATE.VP.   The migration bundle includes an MBMD and a set of 4KB pages.  
VCPU -scope mutable state is verified by TDH.IMPORT.STATE.VP against target platform capabilities and Intel TDX module 
Enumeration:  Availability of TDH. IMPORT.STATE.VP is enumerated by either TDX_FEATURES0.TD_MIGRATION (bit 
supported, calling TDH.IMPORT.STATE.VP returns a TDX_OPERAND_INVALID(RAX) status.  
Interruptibility:  TDH.IMPORT.STATE.VP is interruptible.  The host VMM is expected to invoke it in a loop until it 
Import Abort:  A failed TDH.IMPORT.STATE.VP marks (except in cases where the imported TD state has not been 
S4:  S4 Resumption Abort:  In addition to aborting the import of the current TD, an  abort of an S4 resumption session 
also generates a new S4 anti -replay nonce, preventing a new S4 resumption session from 
starting.  
VCPU Association : TDH.IMPORT.VP associates the TD VCPU with the current LP.  This requires that the VCPU will not be 20 
Table 5.72:  TDH.IMPORT.STATE.VP Operands Information Definition  
Explicit/  
1GB  
Stream 
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  N/A Shared(i)  N/A N/A  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 124 of 329 
1GB  
 
TDH.IMPORT.STATE.VP checks the memory operands per the table above when applicable during its flow.  The text below 
1. The TDVPR page metadata in PAMT must be correct ( PT must be PT_TD VPR). 5 
5. An import session is in progress and TD -scope mutable state has been imported (TDCS.OP_STATE is STATE_IMPORT).  
6. The migration stream index is lower than TDCS.NUM_MIGS.  10 
7. The number of pages allocated to this TDVPS is correct.  
8. The VCPU has not been initialized yet (TDVPS. VCPU_ STATE is VCPU_UNINITIALIZED).  
10. Associate the VCPU with the current LP, and update TD VMCS using the algorithm described in 5.2.1 . 15 
If passed:  
11. If the RESUME input flag is 0, indicating this is a new invocation of a previously interrupted TDH.IMPORT.STATE.VP 
(not a resumption of a previously interrupted one):  
11.1. Copy the MBMD into the migration context.  
11.2. Check the MBMD fields . 20 
If passed:  
11.3. Build the 96b IV for this migration bundle by concatenating the stream index and the stream context’s 
11.4. Accumulate MAC based on the MAC’ed fields of MBMD.  
11.5. Atomically increment the TD’s migrated VCPU counter (TDCS.NUM_ MIGRATED_ VCPUS), and check that 25 
number of VCPUs (TDCS. NUM _VCPUS) has not been exceeded.  
12. Else (this is a resumption of a previously interrupted TDH.IMPORT.STATE.VP):  
12.1.2.  The current SEAMCALL leaf number and the PAGE_OR_LIST operand are the same as in the interruption 30 
state.  
If passed:  
13. Repeat importing 4KB pages until all TD -scope state is imported or until a pending interrupt is detected:  
13.2. Use the migration key and the migration stream context to de crypt the 4KB internal buffer  into an internal 35 
13.3. Parse the metadata list and write the control structure fields using the algorithm described in 5.2.2.3 .  Check 
each TDVPS field for compatibility.  
If passed:  
13.4. If all metadata lists have been imported:  40 
13.4.1.  Check that the accumulated MAC value is equal to the saved MBMD’s MAC value.  
13.4.2.  Check that all TDVPS  fields required to be imported by TDH.IMPORT.STATE.VP have indeed been 
imported.

state.  
If passed:  
If passed:  
imported.  
13.4.3.  Initialize TDVPS fields that need to be initialized at the end of the import session.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 125 of 329 
Intel TDX Application Binary Interface (ABI) Reference  13.4.4.  Mark the migration stream context’s interrupted state as invalid.  
13.4.5.  Increment the migration stream context’s EXPECTED_MB_COUNTER . 
13.4.6.  Increment TDCS.TOTAL_MB.  
13.4.7.  Terminate TDH.IMPORT.STATE.VP with a TDX_SUCCESS status.  
13.5. Else, if there is a pending interrupt:  5 
13.5.2.  Terminate TDH.IMPORT.STATE.VP with a TDX_INTERRUPTED_RESUMABLE status.  
Table 5.73:  TDH.IMPORT.STATE.VP Completion Status Codes (Returned in RAX) Definition  
TDX_ALL_VCPUS_IMPORTED   
TDX_VCPU_STATE_INCORRECT   
  10  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 126 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.19.  TDH.IMPORT.TRACK Leaf  
TDH.IMPORT.TRACK consumes an epoch token received from the source platform.  It ends the current in -order import 
phase epoch and either starts a new epoch or starts the out-of-order import phase.  
Table 5.74:  TDH.IMPORT.TRACK Input Operands Definition  
Must be 0  
R8 HPA and size of memory of an MBMD structure in memory:  
 5 
Table 5.75:  TDH.IMPORT.TRACK Output Operands Definition  
AVX, AVX2 
and 
AVX512 
 
vary.  10 
TDH.IMPORT. TRACK  parses an epoch token received from the source platform.  It checks that the epoch number indicated 
by the token is correct, and that all migration bundles indicated by the token have been received.  
If successful, it ends the current import epoch, and as indicated by the epoch token either starts a new epoch or starts 
the out -of-order import phase . 
Enumeration:  Availability  of TDH. IMPORT.TRACK is enumerated by either TDX_FEATURES0.TD_MIGRATION 15 
(bit 0) or TDX_FEATURES0.S4 (bit 13), readable by TDH.SYS.RD* (see 3.3.3.1 ), being set to 1.  
If not supported, calling TDH.IMPORT.TRACK returns a TDX_OPERAND_INVALID(RAX) status.  
Import Abort:  A failure may mark  the target TD as IMPORT_FAILED; by design, it will not run.   This is 
indicated by the FATAL bit (61) of the completion status returned in RAX.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 127 of 329 
Table 5.76:  TDH.IMPORT. TRACK  Operands Information Definition  
Explicit/  
1GB  
Stream 
 
TDH.IMPORT. TRACK  checks the memory operands per the table above when applicable during its flow.  The text below 5 
5. An import session is in the in -order phase :  TDCS.OP_STATE is either MEMORY_IMPORT or STATE_IMPORT.  
6. An import session is in progress and the TD -scope state has been imported:  TDCS.OP_STATE is STATE_IMPORT.  
7. The migration stream index is 0. 
8. The migration stream is initialized.  15 
10. Copy the MBMD into a temporary buffer.  
11. Check the MBMD fields:  
11.1. Check that SIZE is large enough.  20 
11.2. Check that MB_TYPE indicates a n epoch  token.  
11.3. Check that MIGS_INDEX is 0. 
11.4. Check that the MB_COUNTER value is equal to the migration stream’s EXPECTED_RX_COUNTER.  
11.5. Check that MIG_EPOCH  is higher than TDCS.MIG_EPOCH.  
11.6. Check that TOTAL_MB is equal to TDCS. TOTAL _MB  + 1. 25 
11.7. Check that reserved fields are 0.  
If passed:  
13. Accumulate MAC based on the MAC’ed fields of MBMD and check that the value is the same as the MBMD’s MAC 
field’s value.  30 
If passed:  
14. If the MIG_EPOCH value provided in the MBMD is 0xFFFFFFFF, indicating the start of out -of-order phase:  
14.1. Check that all VCPUs have been imported  
If passed:  
14.2. Start the out -of-order import phase:  set TDCS.OP_STATE to POST_IMPORT.  35  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 128 of 329 
Intel TDX Application Binary Interface (ABI) Reference  15. Set the stream context’s EXPECTED_ MB _COUNTER  to 1.  
16. Increment TDCS.TOTAL_MB.  
17. Set TDCS.MIG_EPOCH to the MIG_EPOCH value provided in the MBMD.  
Table 5.77:  TDH.IMPORT. TRACK  Completion Status Codes (Returned in RAX) Definition  5 
TDX_SOME_VCPUS_NOT_MIGRATED   
November 2023  . Page 129 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.20.  TDH.MEM.PAGE.ADD  Leaf  
Add a 4KB private page to a TD, mapped to the specified GPA , filled with the given page image and encrypted using the 
TD ephemeral key , and update the TD measurement w ith the page properties.  
Table 5.78:  TDH.MEM.PAGE.ADD  Input Operands Definition  
Must be 0  
2:0 Level  Level of the EPT entry that will map the new page – see 3.6.1 :  must be 
0 
11:3  Reserved  Reserved :  must be 0  
51:12  GPA  Bits 51:12 of the guest physical address to be mapped for the new 
Secure EPT page  
63:52  Reserved  Reserved:  must be 0

Must be 0  
0 
R8 Host physical address of the target page to be added to the TD  (HKID bits must be 0)  
R9 Host physical address (including HKID bits) of the source page image  
 5 
Table 5.79:  TDH.MEM.PAGE.ADD  Output Operands Definition  
RAX  SEAMCALL instruction return code – see 5.3.1  
In case of EPT walk error, Secure EPT entry architectural content where the error was detected – 
see 3.6.2  
The architectural content represents how the Secure EPT maps a private memory page or a Secure 
EPT page and  may be different than the actual contents of the Secure EPT entry.  Software should 
consult the Secure EPT information returned in RDX.  
In case of EPT walk error, Secure EPT entry level and state where the error was detected – see 
3.6.2  
November 2023  . Page 130 of 329 
vary.  
TDH.MEM.PAGE.ADD  adds a 4KB private page to a TD and maps it to the provided GPA.  It copies the provided source 
page image to specified physical page  using the TD’s ephemeral private key and updates the TD measurement with the 5 
page properties.  TDH.MEM.PAGE.ADD  is used during TD build before the TD is initialized.  
In-Place Add:  It is allowed  to set the TD page HPA in R8 to the same address as the source page HPA in R9.  In this 
case the source page is converted to be a TD private page.  
Cache Flush : Before calling TDH.MEM.PAGE.ADD, the host VMM should ensure that no cache lines associated with 
the added physical page are in a Modified state, as described in the [Base Spec].  10 
Table 5.80:  TDH.MEM.PAGE.ADD  Operands Information Definition  
Explicit/  
Implicit  Reg. Ref 
1GB  
Explicit  RCX GPA  TD private page  
(GPA)4 Blob  RW Private  4KB N/A N/A N/A 
Explicit  RDX  HPA  TDR page  Blob  RW Opaque  4KB Exclusive  Shared  Shared  
Explicit  R8 HPA  TD private page  
(HPA)4 Blob  RW Private  4KB Exclusive  Shared  Shared  
Explicit  R9 HPA  Source page  Blob  R Shared  4KB None  None  None  
Implicit  N/A GPA  Secure EPT tree  N/A RW Private  N/A Exclusive(i)  N/A N/A 
Implicit  N/A GPA  Secure EPT 
entry  SEPT 
 
TDH.MEM.PAGE.ADD  checks the memory operands per the table above when applicable during its flow.  The text below 15 
does not explicitly mention those checks, except when necessary . 
1. The TD R page metadata in PAMT must be correct (PT must be PT_TDR). 
2. The TD is not in a FATAL state (TDR.FATAL is FALSE) . 
3. The TD keys are configured on the hardware  (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED ). 20 
4. The TD must have been initialized but not finalized (TDR.NUM_TDCX is the required number  and TDCS.OP_STATE is 
INITIALIZED ). 
5. The target  page metadata in PAMT must be correct (PT must be PT_NDA ). 
If successful, the function  does  the following:  
6. Walk the Secure EPT based on the GPA operand and  find the leaf EPT entry for the 4KB page . 25 
If the Secure EPT entry is marked as FREE , the function does the following:  
7. On server platforms:  Copy  the source image  to the target TD page usin g the TD’s ephemeral private HKID , and direct 
write (MOVDIR64B) . 
 
4 RCX and R8 denote the same TD private page operand, using HPA and GPA respectively   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 131 of 329 
Intel TDX Application Binary Interface (ABI) Reference  8. Update the parent Secure EPT entry with the target page HPA and MAPPED  state . 
9. Extend  TDCS.MR TD with the target page GPA .  Extension is done using SHA384 with a 128B extension buffer 
composed as follows:  
o Bytes 0 through 11 contain the ASCII string “ MEM.PAGE.ADD ”. 
o Bytes 16 through 23 contain the GPA (in little -endian format).  5 
o All the other bytes contain 0.  
10. Increment TDR.CHLDCNT . 
11. Update  the PAMT entry with the PT_REG page type and the TDR physical address as the OWNER.  
Table 5.81:  TDH.MEM.PAGE.ADD  Completion Status Codes (Returned in RAX) Definition  10 
TDX_OPERAND_BUSY  Operation encountered a busy operand, indicated by the 
lower 32 bits of the status.  In many cases, this can be 
resolved by retrying the operation.  
TDX_SUCCESS  TDH.MEM.PAGE.ADD  is successful  
November 2023  . Page 132 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.21.  TDH.MEM.PAGE.AUG Leaf  
Dynamically add a 4KB  or a 2MB  private page to an initialized TD, mapped to the specified GPAs.  
Table 5.82:  TDH.MEM.PAGE.AUG In put Operands Definition  
Must be 0  
2:0 Level  Level of the EPT entry that will map the new page – see 3.6.1 :  must 
be 0 (4KB) or 1 (2MB)  
RDX  Host physical address of the parent TDR page (HKID bits must be 0)  
R8 Host physical address of the target page to be added to the TD (HKID bits must be 0)  
 
Table 5.83:  TDH.MEM.PAGE.AUG Out put Operands Definition  5 
see 3.6.2  
3.6.2  
November 2023  . Page 133 of 329 
vary.  
TDH.MEM.PAGE.AUG adds a 4KB or a 2MB private page to a TD and maps it to the provided GPA.  The new page is 
mapped in a pending state and can be accessed only by the guest TD after it accepts it using 5 
TDCALL(TDG.MEM.PAGE.ACCEPT).  TDH.MEM.PAGE.AUG does not initialize the new page and does not update the TD 
Cache Flush : Before calling TDH.MEM.PAGE.AUG, the host VMM should ensure that no cache lines associated with 
the added physical page are in a Modified state, as described in the [Base Spec].  
To understand the table and text below, please refer to the [ TDX Module Base Spec ] chapter discussing general aspects 10 
Table 5.84:  TDH.MEM.PAGE.AUG Operands Information Definition  
Explicit/  
Implicit  Register  Ref 
1GB  
Explicit  RCX GPA  TD private page 
(GPA)5 Blob  None  Private  212+9*Level 
Bytes  N/A N/A N/A 
Explicit  RDX  HPA  TDR page  TDR  RW Opaque  4KB Shared  Shared  Shared  
Explicit  R8 HPA  TD private page 
(HPA)5 Blob  None  Private  212+9*Level 
Bytes  Exclusive  Shared6 Shared

Explicit/  
1GB  
Bytes  Exclusive  Shared6 Shared  
Implicit  N/A GPA  Secure EPT tree  N/A RW Private  N/A Shared  N/A N/A 
entry  SEPT 
 
TDH.MEM.PAGE.AUG checks the memory operands per the table above when applicable during its flow.  The text below 
does not explicitly mention those checks, except when necessary.  15 
3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED).  
4. The TD must be in one of the following states : 20 
4.1. The TD has been initialized locally by TDH.MNG.INIT and no migration session is in progress  
4.2. An export session is in progress its live export phase; TDH.EXPORT.PAUSE has not been invoked yet.  
4.3. An import session is in its live import phase, initiated by TDH.IMPORT.COMMIT.  
5. The target page metadata in PAMT must be correct (PT must be PT_NDA  for the entire 4KB or 2MB range ). 
If successful, the function does the following:  25 
6. Walk the Secure EPT based on the GPA operand and  find the leaf EPT entry for the 4KB or 2MB page.  
7. Update the parent Secure EPT entry with the target page HPA and PENDING  state.  
8. Atomically increment TDR.CHLDCNT by 1 (for a 4KB page) or by 512 (for a 2MB page).  
 
5 RCX and R8 denote the same TD private page operand, using HPA and GPA respectively  
6 Applicable for 4KB pages only   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 134 of 329 
Intel TDX Application Binary Interface (ABI) Reference  9. Update  the PAMT entry with the PT_REG page type and the TDR physical address as the OWNER.  
Table 5.85:  TDH.MEM.PAGE.AUG Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MEM.PAGE.AUG is successful.  
November 2023  . Page 135 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.22.  TDH.MEM.PAGE.DEMOTE Leaf  
Split a large private TD page (2MB or 1GB) into 512 small pages (4KB or 2MB,  respectively).  
Table 5.86:  TDH.MEM.PAGE.DEMOTE In put Operands Definition  
Must be 0  
2:0 Level  Level of the Secure EPT entry that maps the large page to be split:  
either 1 (2MB) or 2 (1GB) – see 3.6.1  
51:12  GPA  Bits 51:12 of the guest physical address of the large page to be 
split  
Depending on the level, the following least significant bits must be 
0: 
Level 1 (2MB):  Bits 20:12  
Level 2 (1GB):  Bits 29:12  
RDX  TD handle and flags:  
0 L2_SEPT_ADD_MODE  New L2 SEPT pages addition mode:  
0 DENSE  New L2 SEPT pages are added, if provided by R9, 
R10 or R11.  
1 SPARSE  New L2 SEPT pages are added, if provided by R9, 
R10 or R11, but only for L2 VMs where the L1 
VMM has created a page alias (using 
TDG.MEM.PAGE.ATTR.WR).  
In both cases, a new L2 SEPT must be provided for L2 VMs where a 
page alias exists . 
This bit is ignored if the TD has no L2 VMs.  
11:1  Reserved  Reserved:  must be 0  
51:12  TDR_HPA  Bits 51:12 of the host physical address of the parent TDR page 
(HKID bits must be 0)  
63:52  Reserved  Reserved:  must be 0   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 136 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Operand  Description  
R8 Host physical address of the new L1 Secure EPT page to be added to the TD  (HKID bits must be 0)  
R9 If the number of L2 VMs is >= 1, R9 contains the host physical address of the new Secure EPT page 
to be added to L2 VM #1’s SEPT tree (HKID bits must be 0).  
Else (the number of L2 VMs is 0), R9 is ignored.  
If the value of R9 is NULL_PA ( -1), no new SEPT page is added to L2 VM #1’s SEPT.  If the demoted 
TD private page has an L2 page alias for L2 VM #1, this is an error.  
Else, bit 63 of R9 is ignored.  If L2_SEPT_ADD_MODE  is 1, the new SEPT page is only used if the 
demoted TD private page has an L2 page alias for L2 VM #1.  Else, the new SEPT page is always 
used.  
R10 If the number of L2 VMs is >= 2, R10 contains the host physical address of the new Secure EPT page 
to be added to L2 VM #2’s SEPT tree (HKID bits must be 0).  
Else (the number of L2 VMs is 0 or 1), R10 is ignored.  
If the value of R10 is NULL_PA ( -1), no new SEPT page is added to L2 VM #2’s SEPT.  If the demoted 
TD private page has an L2 page alias for L2 VM #2, this is an error.  
Else, bit 63 of R10 is ignored.  If L2_SEPT_ADD_MODE is 1, the new SEPT page is only used if the 
demoted TD private page has an L2 page alias for L2 VM #2.  Else, the new SEPT page is always 
used.  
R11 If the number of L2 VMs is >= 3, R11 contains the host physical address of the new Secure EPT page 
to be added to L2 VM #3’s SEPT tree (HKID bits must be 0).  
Else (the number of L2 VMs is 0, 1 or 2), R11 is ignored.  
If the value of R11 is NULL_PA ( -1), no new SEPT page is added to L2 VM #3’s SEPT.  If the demoted 
TD private page has an L2 page alias for L2 VM #3, this is an error.  
Else, bit 63 of R1 1 is ignored.  If L2_SEPT_ADD_MODE is 1, the new SEPT page is only used if the 
demoted TD private page has an L2 page alias for L2 VM #3.  Else, the new SEPT page is always 
used.  
 
Table 5.87:  TDH.MEM.PAGE.DEMOTE Out put Operands Definition  
RCX In case of an interruption, as indicated by RAX returning TDX_INTERRUPTED_RESTARTABLE, RCX is 
unmodified.  
Else, RCX returns extended error information part 1.   
see 3.6.2  
EPT page ; it may be different than the actual contents of the Secure EPT entry.  Software should 
RDX  In case of an interruption, as indicated by RAX returning TDX_INTERRUPTED_RESTARTABLE, RDX is 
Else, RDX returns extended error information part 2.  
3.6.2  
November 2023  . Page 137 of 329 
R9 If TDH.MEM.PAGE.DEMOTE terminated successfully, the number of L2 VMs is >= 1 and the page 
whose HPA was provided in R9 was not used as an SEPT page for any reason, R9 is updated with 
bit 63 set to 1.  
Else, R9 is unmodified.  
R10 If TDH.MEM.PAGE.DEMOTE terminated successfully, the number of L2 VMs is >= 2 and the page 
whose HPA was provided in R10 was not used as an SEPT page for any reason, R10 is updated with 
Else, R10 is unmodified.  
R11 If TDH.MEM.PAGE.DEMOTE terminated successfully, the number of L2 VMs is >= 3 and the page 
whose HPA was provided in R11 was not used as an SEPT page for any reason, R11 is updated with 
Else, R11 is unmodified.  
 
vary.  
TDH.MEM.PAGE.DEMOTE splits a large TD private page (2MB or 1GB) into 512 small pages (4KB or 2MB, respectively) 5 
and adds a new Secure EPT page to map those small pages .  If the large page is mapped in any L2 SEPTs, 
TDH.MEM.PAGE.DEMOTE splits those mapping and adds new L2 Secure EPT pages to map the demoted page.

vary.  
TDH.MEM.PAGE.DEMOTE splits those mapping and adds new L2 Secure EPT pages to map the demoted page.  
Blocking and TLB Tracking:  If the TD may be running, the demoted page must be blocked and TLB tracked.  Else (e.g., 
TDH.MR.FINALIZE has not yet been executed, or the TD has been paused for export), no 
blocking and tracking is required.  10 
L2 SEPT Population:  TDH.MEM.PAGE.DEMOTE supports multiple host VMM policies for populating the L2 SEPT 
trees.   
• Dense mode is when the host VMM maintains an L2 SEPT page for each L1 SEPT page.  
This mode is selected by setting L2_SEPT_ADD_MODE to 0.  
• Sparse mode is when the host VMM only maintains an L2 SEPT page for a certain L1 15 
SEPT page on demand, i.e., when there’s a need to map a TD private page in an L2 VM’s 
GPA space.  This mode is selected by setting L2_SEPT_ADD_MODE to 0.   The host VMM 
provides new SEPT pages,  but they are only used is a page alias exists for the relevant 
L2 VM.  
The host VMM may also choose to maintain L2 SEPT tree s only for a subset of the L2 VMs 20 
(e.g., if a TD is created with a certain number of L2 VMs but not all of them are currently in 
use).  The host  VMM can do so by providing NULL_PA as the new SEPT page(s) HPA.  
Interruptibility:  TDH.MEM.PAGE.DEMOTE is interruptible but not resumable.  If a pending interrupt is 
detected during operation, TDH.MEM.PAGE.DEMOTE returns with a 
TDX_INTERRUP TED_RESTARTABLE status in RAX.  No demote operation is done and no 25 
output operands except RAX are modified.  
In such case, TDH.MEM.PAGE.DEMOTE should be invoked in a loop until it terminates 
successfully.  The host VMM should be designed to avoid cases where interrupt storms 
prevent successful completion of TDH.MEM.PAGE.DEMOTE.  
Cache Flush : Before calling TDH.MEM.PAGE.DEMOTE, the host VMM should ensure that no cache lines 30 
associated with the added SEPT physical pages are in a Modified state, as described in the 
[Base Spec].  
The table below shows the values of the SEPT HPA arguments in R9 – R11 when no error occurs (RAX returns 
TDX_SUCCESS).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 138 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.88:  Meaning of TDH.MEM.PAGE.DEMOTE’s SEPT HPA Arguments on Input and Output (No Error)  
Value  R9 – R11 on Input  R9 – R11 on Output  
NULL_PA ( -1) No new SEPT page to add   Unmodified  
Bits 62:0:  Valid HPA, HKID bits are 0  
Bit 63:  0 Bits 62:0:  HPA of new SEPT page to 
add 
Bit 63:  Ignored  TDH.MEM.PAGE.DEMOTE 
terminated successfully and the 
new SEPT page has been added  
Bit 63:  1 TDH.MEM.PAGE.DEMOTE 
new SEPT page has not been added  
 
Table 5.89:  TDH.MEM.PAGE.DEMOTE Operands Information Definition  5 
Explicit/  
Type  Resource Name  Resource 
1GB  
and 
Level  TD private page 
to split  Blob  None  Private  212+9*level 
bytes  Exclusive  None  None  
Explicit  R8 HPA  New Secure 
EPT page  SEPT_PAGE  RW Private  4KB Exclusive  Shared  Shared  
Explicit  R9, 
R10, 
R11 HPA  New L2 Secure 
EPT pages  SEPT_PAGE  RW Private  4KB Exclusive  Shared  Shared  
Tree  N/A RW Private  N/A Shared  N/A N/A 
entry  SEPT Entry  RW Private  N/A Exclusive  N/A N/A 
Trees  N/A RW Private  N/A Shared(i)  N/A N/A 
entries  SEPT Entry  RW Private  N/A Exclusive(i)  N/A N/A 
 
TDH.MEM.PAGE.DEMOTE checks the memory operands per the table above when applicable during its flow.  The text 
4. The TD must have been initialized ( TDR.NUM_TDCX is the required number  and TDCS.OP_STATE is  either INITIALIZED 
or RUNNING).  
5. The specified page level is either 1 (2MB) or 2 (1GB).  See 3.6.1  for a definition of EPT level.  15  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 139 of 329 
6. Walk the L1 Secure EPT based on the GPA operand and locate the large TD private page to be demoted.  
7. If the TD may run (its OP_STATE in either RUNNING, LIVE_EXPORT or LIVE_IMPORT):  
7.1. Check the Secure EPT entry:  It must be a leaf BLOCKED or PENDING_BLOCKED entry.  
7.2. Check that TLB tracking has been done, based on the large TD page’s PAMT.BEPOCH.  5 
Else:  
7.3. Check the Secure EPT entry:  It must be a leaf MAPPED, BLOCKED, PENDING or PENDING_BLOCKED entry.  
If passed:  
8. Check that the new SEPT page metadata in PAMT is correct (PT must be PT_NDA).  
9. Check that the new L2 SEPT pages metadata in PAMT is correct (PT must be PT_NDA).  10 
If passed:  
10. Split the large TD private page PAMT entry into 512 PAMT entries at the lower level:  
10.1. Set the parent PAMT_2M or PAMT_1G entry state to PT_NDA.  
10.2. Set the 512 child PAMT4K or PAMT_2M entries respectively to PT_REG.  
11. Initialize the new Secure EPT page’s 512 entries to MAPPED (if the original page was MAPPED or BLOCKED) or 15 
PENDING (if the original page was PENDING or PENDING_BLOCKED) pointing to the 512 consecutive small pages 
above.  Use the TD’s ephemeral private HKID and direct write (MOVDIR64B).  
12. Atomically set the original  Secure EPT entry to NL_MAPPED  non-leaf entry pointing to the new Secure EPT page.  
13. For each L2 VM, if L2_SEPT_ADD_MODE is 0 or there is an L2 mapping of the page to be demoted:  
13.1. Walk the L2 Secure EPT based on the GPA operand and  locate the L2 Secure EPT parent entry of the page to be 20 
demoted.  
Note:  If there is a n L2 mapping of the  page, this walk should not fail.  The L2 SEPT entry state is implicit:  It 
must be a leaf, mapped (L2_MAPPED) or blocked (L2_BLOCKED) entry.  Else, the walk may fail – for this 
reason the update is done below only if all SEPT walks succeeded.  
14. For each L2 VM:  
14.1. If there is an L2 mapping of  the page to be demoted:  
14.1.1.  Initialize the new L2 Secure EPT page’s 512 entries to L2_MAPPED (if the original page was MAPPED or 
BLOCKED) or PENDING (if the original page was PENDING or PENDING_BLOCKED) pointing to the 512 
consecutive small pages above.  Use the TD’s ephemeral private HKID and direct write (MOVDIR64B).  30 
14.2. Else, if L2_SEPT_ADD_MODE is 0: 
14.2.1.  Initialize the new L2 Secure EPT page’s 512 entries to L2_FREE.  Use the TD’s ephemeral private HKID 
and direct write (MOVDIR64B).  
14.3. Atomically set the original L2 Secure EPT entry to NL_MAPPED non -leaf entry pointing to the new L2 Secure EPT 
page.  35 
15. Atomically increment TDR.CHLDCNT by 1.  
15.1. Note that CHLDCNT counts the number of 4KB pages.  The change is due only to the addition of the new Secure 
EPT page.  
16. Update  the PAMT entry of the new Secure -EPT page with the PT_EPT page type and the TDR physical address as the 
OWNER.  40 
17. For each L2 VM:  
17.1. If there was an L2 mapping of the page and the new L2 SEPT page was used:  
17.1.1.  Update the PAMT entry of each new L2 SEPT page with the PT_EPT page type and the TDR physical 
address as the OWNER.  
17.1.2.  Atomically increment TDR.CHLDCNT by 1.  45 
Else:  
17.1.3.  Set bit 63 of the applicable output GPR (R9, R10 or R11) to 1, indicating that this page was not used as 
an SEPT page.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 140 of 329 
Table 5.90:  TDH.MEM.PAGE.DEMOTE Completion Status Codes (Returned in RAX) Definition  
TDX_GPA_RANGE_NOT_BLOCKED   
TDX_INTERRUPTED_RESTARTABLE  TDH.MEM.PAGE.DEMOTE’s operation has been interrupted 
by an external event; it may be restarted (from its 
beginning) by calling it again.  
TDX_L2_SEPT_PAGE_NOT_PROVIDED   
TDX_L2_SEPT_WALK_FAILED   
lower 32 bits of the status.  In many cases, this can be

Else:  
TDX_SUCCESS  TDH.MEM.PAGE.DEMOTE is successful.  
November 2023  . Page 141 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.23.  TDH.MEM.PAGE.PROMOTE Leaf  
Merge 512 consecutive small private TD pages (4KB or 2MB) into one large page (2MB or 1GB, respectively).  
Table 5.91:  TDH.MEM.PAGE.PROMOTE In put Operands Definition  
Versions 0 and 1 are supported.   See enumeration details below.  
RCX EPT mapping information:  
2:0 Level  Level of the Secure EPT entry that will map the merged large page:  
either 1 (2MB) or 2 (1GB) (see 3.6.1 ) 
51:12  GPA  Bits 51:12 of the guest physical address of the merged large page  
Depending on the level, the following least significant bits must be 0:  
 
Table 5.92:  TDH.MEM.PAGE.PROMOTE Out put Operands Definition  5 
RCX If TDH.MEM.PAGE.PROMOTE succeeded, RCX returns the HPA of the removed SEPT page  (HKID bits 
are set to 0).  
In case of an interruption, as indicated by RAX returning TDX_INTERRUPTED_RESTARTABLE, RCX is 
see 3.6.2  
In other cases, RCX returns 0.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 142 of 329 
Else, RDX returns extended  error information part 2 . 
3.6.2  
R9 If TDH.MEM.PAGE.PROMOTE version is 1 or higher:  
• If L2 VM #1’s L2 SEPT page has been removed, R9 returns the HPA of that SEPT page  (HKID bits 
• Else, R9 returns NULL_PA ( -1). 
R10 If TDH.MEM.PAGE.PROMOTE version is 1 or higher:  
• If L2 VM #2’s L2 SEPT page has been removed, R10 returns the HPA of that SEPT page  (HKID 
bits are set to 0).  
• Else, R10 returns NULL_PA ( -1). 
R11 If TDH.MEM.PAGE.PROMOTE version is 1 or higher:  
• If L2 VM #3’s L2 SEPT page has been removed, R11 returns the HPA of that SEPT page  (HKID 
• Else, R11 returns NULL_PA ( -1). 
 
vary.  
TDH.MEM.PAGE.PROMOTE  merges 512 private pages, which are consecutive both in the HPA space and in the GPA space.  5 
The L1 SEPT page and all existing L2 SEPT pages at the requested GPA and level are removed . 
All merged private pages must have the same Secure EPT leaf entry attributes and state, which must be either MAPPED 
or PENDING.   All merged private pages must have the same set of L2 mappings and L2 attributes.  
Enumeration:  Availability of TDH. MEM.PAGE.PROMOTE version 1 is enumerated by 
TDX_FEATURES0.TD_PARTITIONING (bit 7), readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not 10 
supported, calling TDH.MEM.PAGE.PROMOTE with a version number higher than 0 returns 
a TDX_OPERAND_INVALID(RAX) status.  
Blocking and TLB Tracking:  If the TD may be running, the promoted GPA range must be blocked and TLB tracked.  Else 
(e.g., TDH.MR.FINALIZE has not yet been executed, or the TD has been paused for export), 
no blocking and tracking is required.  15 
Interruptibility:  TDH.MEM.PAGE.PROMOTE is interruptible but not resumable.  If a pending interrupt is 
detected during operation, TDH.MEM.PAGE.PROMOTE returns with a 
TDX_INTERRUP TED_RESTARTABLE status in RAX.  No promote  operation is done and no 
output operands except RAX are modified.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 143 of 329 
Intel TDX Application Binary Interface (ABI) Reference  In such case, TDH.MEM.PAGE.PROMOTE should be invoked in a loop until it terminates 
prevent successful completion of TDH.MEM.PAGE.PROMOTE.  
Cache Flush and Init:  After the SEPT page s have been removed, the host VMM should flush the physical pages ’ 
cache lines and initialize their  content before they are  reused, as described in the [Base 5 
Spec].  
The table below shows the values of the SEPT HPA output arguments in RCX and R9 – R11 when version 1 or higher is 
selected and no error occurs (RAX returns TDX_SUCCESS).  
Table 5.93:  Meaning of TDH.MEM.PAGE.PROMOTE’s SEPT HPA Arguments on Output (No Error)  
Value  RCX on Output  R9 – R11 on Output  
NULL_PA ( -1) N/A  No removed SEPT page for this L2 
VM 
Valid HPA  Removed L1 SEPT page  Removed L2 SEPT page  
 10 
November 2023  . Page 144 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.94:  TDH.MEM.PAGE.PROMOTE Operands Information Definition  
Explicit/  
1GB  
and 
Level  Removed 
Secure EPT 
page  SEPT_PAGE  R Private  212+9*Level 
Bytes  Exclusive  None  None  
Implicit  N/A HPA  Merged HPA 
range  Blob  None  Private  N/A Exclusive  None  None  
Implicit  N/A GPA  Large page L1 
Secure EPT 
Implicit  N/A GPA  Small pages L1 
Secure EPT 
entries  SEPT Entry  RW Private  N/A Exclusive  N/A N/A 
Implicit  N/A GPA  L2 Large page 
Secure EPT 
entry  SEPT Entry  RW Private  N/A Exclusive(i)  N/A N/A 
Implicit  N/A GPA  L2 Small pages 
Secure EPT 
 
TDH.MEM.PAGE.PROMOTE checks the memory operands per the table above when applicable during its flow.  The text 
4. The TD must have been initialized  or its metadata has been imported  (TDR.NUM_TDCX is the required number  and 
TDCS.OP_STATE is  either INITIALIZED , RUNNING , *_EXPORT, POST_IMPORT or LIVE_IMPORT ). 10 
5. The specified merged page level is either 1 (2MB) or 2 (1GB) – see 3.6.1  for a definition of EPT level.  
6. Walk the Secure EPT based on the GPA operand and  locate the Secure EPT parent entry of the GPA range to be 
promoted to a merged large page.  
7. Get the HPA of the Secure EPT page, which currently maps the GPA range to be promoted, from the Secure EPT 15 
above.  Get its PAMT entry.  
8. If the TD may run (its OP_STATE in either RUNNING, LIVE_EXPORT or LIVE_IMPORT):  
8.1. Check  the Secure EPT entry:   It must be a non -leaf, blocked (NL_ BLOCKED ) entry.

8.1. Check  the Secure EPT entry:   It must be a non -leaf, blocked (NL_ BLOCKED ) entry.  
8.2. Check  that TLB tracking has been done, based on the above Secure EPT page’s PAMT.BEPOCH.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 145 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Else:  
8.3. Check the Secure EPT entry:  It must be a non -leaf, mapped (NL_MAPPED) or blocked (NL_BLOCKED) entry.  
If passed:  
9. Scan the content of the above Secure EPT page and check  all 512 entries:  
9.1. They are leaf entries (this also implies that the corresponding pages are PT_REG).  5 
9.2. Their state is  either MAPPED  or PENDING . 
9.3. They have  contiguous HPA mapping aligned to the promoted range size.  
9.4. They have L2 mappings for the same set of L2 VMs.  
10. For each L2 VM:  
10.1. Walk the L2 Secure EPT based on the GPA operand and  locate the L2 Secure EPT parent entry of the GPA range 10 
to be promoted to a merged large page.  
10.2. If L2 mapping was found above to exist for this L2 VM:  
10.2.1.  The above SEPT walk should not fail.  The L2 SEPT entry state is implicit:  It must be a non -leaf, mapped 
(NL_MAPPED) or blocked (NL_BLOCKED) entry.  
10.2.2.  Scan the content of the above L2 Secure EPT page and check all 512 entries:  15 
10.2.2.1.  They should all have the same L2 attributes.  
10.2.2.2.  The following are implicit:  All L2 SEPT entries are leaf entries, they all have the same state, 
and they have contiguous HPA mapping aligned to the promoted range size.  
10.3. Else (L2 mapping was not fo und above to exist for this L2 VM):  
10.3.1.  The walk may fail; this is not considered an error.  20 
10.3.2.  If the walk succeeded, it implicitly arrives at an empty SEPT page.  
If successful, the above checks imply that:  
• The 2MB or 1GB GPA range to be promoted has a corresponding single HPA range and a single PAMT entry 
(PAMT_2M or PAMT_1G, respectively) owned by the current guest TD, and its current PAMT.PT is PAMT_NDA.  
• The 512 child PAMT entries (PAMT_2M or PAMT_4K, respectively) of the above are owned by the current guest TD, 25 
and their PAMT.PT is PAMT_REG.  
The function then does the following:  
11. Merge the corresponding 512 physical pages into a single larger physical page:  
11.1. Set the small page (PAMT_4K or PAMT_2M) entries state to PT_NDA.  
11.2. Set the parent (PAMT_2M or PAMT_1G  respectively) entry to PT_REG.  30 
12. Atomically set the promoted Secure EPT entry to MAPPED  or PENDING (depending on the small pages’ Secure EPT 
entry state) leaf entry pointing to the merged HPA range.  
13. Remove the Secure EPT page that previously mapped the 512 physical pages:  
13.1. Atomically decrement TDR.CHLDCNT by 1.  
13.1.1.  Note that CHLDCNT counts the number of 4KB pages.  The change is due only to the removal of the 35 
Secure EPT page.  
13.2. Update  the PAMT entry of the removed Secure EPT page to PT_NDA.  
14. For each L2 VM where L2 mapping was found above to exist:  
14.1. Remove the Secure EPT page that previously mapped the 512 physical pages:  
14.1.1.  Atomically decrement TDR.CHLDCNT by 1.  40 
14.1.2.  Update the PAMT entry of the removed Secure EPT page to PT_NDA.  
Table 5.95:  TDH.MEM.PAGE.PROMOTE Completion Status Codes (Returned in RAX) Definition  
TDX_EPT_INVALID_PROMOTE_CONDITIONS   
TDX_INTERRUPTED_RESTARTABLE  TDH.MEM.PAGE.PROMOTE’s operation has been interrupted 
beginning) by calling it again.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 146 of 329 
TDX_SUCCESS  TDH.MEM.PAGE.PROMOTE  is successful . 
November 2023  . Page 147 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.24.  TDH.MEM.PAGE.RELOCATE Leaf  
Relocate a 4KB mapped page from its current host physical address to another.  
Table 5.96:  TDH.MEM.PAGE.RELOCATE In put Operands Definition  
Must be 0  
2:0 Level  Level of the Secure EPT entry that maps the private page to be 
relocated, must be 0 (i.e., 4KB) (see 3.6.1 ). 
51:12  GPA  Bits 51:12 of the guest physical address of the private page to be 
relocated  
R8 Host physical address of the relocated page target  (HKID bits must be 0)  
 
Table 5.97:  TDH.MEM.PAGE.RELOCATE Out put Operands Definition  5 
RCX If TDH.MEM.PAGE.RELOCATE succeeded, RCX returns the HPA of the old physical page that has 
been removed  (HKID bits are set to 0).  
see 3.6.2  
3.6.2  
November 2023  . Page 148 of 329 
vary.  
TDH.MEM.PAGE.RELOCATE  replaces a mapped 4KB page mapping target HPA by moving the current page content to a 
new target HPA and updating the Secure -EPT mapping to the new target HPA.  On successful operation, the previous 5 
mapped HPA target is marked is free in the PAMT.  
Blocking and TLB Tracking:  If the TD may be running, the relocated page must be blocked and TLB tracked.  Else (e.g., 
blocking and tracking is required.  
New Page Cache Flush : Before calling TDH.MEM.PAGE.RELOCATE, the host VMM should ensure that no cache 10 
lines associated with the new physical page are in a Modified state, as described in the 
Removed Page Cache Flush:  After the page has been relocated, the host VMM should flush the  old physical page’s 
cache lines and initialize its content before it is reused, as described in the [Base Spec].  
Table 5.98:  TDH.MEM.PAGE.RELOCATE  Operands Information Definition  
Explicit/  
1GB  
and 
Level  TD private page  Blob  R Private  4KB Exclusive  None  None  
Explicit  RDX HPA  TDR page  TDR R Opaque  4KB Shared  Shared  Shared  
Explicit  R8 HPA  Target physical 
page  Blob  RW Private  4KB Exclusive  Shared  Shared  
tree N/A RW Private  N/A Shared  N/A N/A 
entry  SEPT 
Entry  RW Private  N/A Exclusive
(i) N/A N/A 
 
TDH.MEM.PAGE.RELOCATE  checks the memory operands per the table above when applicable during its flow.  The text 
below does not explicitly mention those checks, except when necessary . 20 
1. The TDR page metadata in PAMT must be correct (PT must be PT_TDR) .

entry  SEPT 
(i) N/A N/A 
 
1. The TDR page metadata in PAMT must be correct (PT must be PT_TDR) . 
4. The TD must have been initialized ( TDR.NUM_TDCX is the required number  and TDCS.OP_STATE is  either INITIALIZED 25 
5. The target page metadata in PAMT must be correct (PT must be PT_NDA).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 149 of 329 
6. Walk the Secure EPT based on the GPA operand and level and find the currently mapped HPA.  
7. If TLB tracking is required (based on the Secure EPT entry state and the TD’s OP_STATE):  
7.1. Check that the SEPT entry is BLOCKED or PENDING_BLOCKED.  
7.2. Check that TLB tracking was done.  5 
Else:  
7.3. Check that the SEPT entry is MAPPED, BLOCKED, BLOCKEDW, EXPORTED*, PENDING, PENDING_BLOCKED, 
PENDING_BLOCKEDW or PENDING_EXPORTED*.  
8. Check  that the currently mapped HPA is different than the target HPA . 
If successful, the function does the following:  10 
9. If the page state is  not one of the PENDING* states , copy the currently mapped page content  to the target page, 
using the TD’s ephemeral private HKID and direct writes (MOVDIR64B).  
10. Free the currently mapped HPA by setting its PAMT.PT to PT_NDA.  
11. Update the target page’s PAMT entry with the PT_REG page type and the TDR physical address as the OWNER.  
12. Update the Secure EPT entry : 15 
12.1. Set the HPA to point to the target page.  
12.2. Unblock the SEPT entry:  i f its state was BLOCKED or PENDING_BLOCKED, update it to MAPPED  or PENDING , 
respectively.  
13. For each L2 VM where the page has l2 mapping:  
13.1. Walk the L2 Secure EPT based on the GPA operand and find the leaf L2 SEPT entry mapping the page to be 20 
relocated.  
13.2. Update the L2 Secure EPT entry:  
13.2.1.  Set the HPA to point to the target page.  
13.2.2.  If the updated L1 SEPT entry state is one of the PENDING* states, set the L2 SEPT entry state to 
L2_BLOCKED.  Else, set the L2 SEPT entry state to L2_MAPPED.  25 
Table 5.99:  TDH.MEM.PAGE.RELOCATE  Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MEM.PAGE.RELOCATE is successful  
November 2023  . Page 150 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.25.  TDH.MEM.PAGE.REMOVE Leaf  
Remove a GPA -mapped 4KB, 2MB or 1GB private page from a TD.  
Table 5.100:  TDH.MEM.PAGE.REMOVE In put Operands Definition  
Must be 0  
removed:   either 0 (4KB), 1 (2MB) or 2 (1GB) – see 3.6.1 . 
removed  
 
Table 5.101:  TDH.MEM.PAGE.REMOVE Out put Operands Definition  5 
RCX If TDH.MEM.PAGE.REMOVE succeeded, RCX returns the HPA of the removed page  (HKID bits are 
set to 0) . 
see 3.6.2  
3.6.2  
November 2023  . Page 151 of 329 
vary.  
TDH.MEM.PAGE.REMOVE  removes a 4KB, 2MB or 1GB private page from the TD’s Secure EPT tree  (marks the SEPT entry 
as FREE) .  If the page is mapped in any L2 Secure EPT, the applicable L2 SEPT entries are marked as L2_FREE.  On successful 5 
operation, TDH.MEM.PAGE.REMOVE marks the physical page as free in PAMT.   
Blocking and TLB Tracking:  If the TD may be running, the removed page must be blocked and TLB tracked.  Else (e.g., 
Cache Flush and Init : After the page has been removed, the host VMM should flush the  physical page’s cache lines 10 
and initialize its content before it is reused, as described in the [Base Spec].  
Table 5.102:  TDH.MEM.PAGE.REMOVE Operands Information Definition  
Explicit/  
1GB  
and 
Level  TD private page  Blob  R Private  212+9*L evel 
entry  SEPT 
 15 
TDH.MEM.PAGE.REMOVE checks the memory operands per the table above when applicable during its flow.  The text 
4. The TD must be in one of the following states:  
4.1. The TD has been initialized locally by TDH.MNG.INIT.  
4.2. An import session is in progress , and either the out-of-order phase has started (TDH.IMPORT.TRACK has been 
successfully executed with an Epoch Token MBMD indicating a MIG_EPOCH value of 0xFFFFFFFF), or import has 25 
failed.  
5. The specified level is either 0 (4KB), 1 (2MB) or 2 (1GB) – see 3.6.1  for a definition of EPT level.  
If successful:  
6. Walk the Secure EPT based on the GPA operand and  find the leaf entry of the page to be removed.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 152 of 329 
Intel TDX Application Binary Interface (ABI) Reference  7. If TLB tracking is required (based on the Secure EPT entry state and the TD’s OP_STATE) : 
7.1. Check  that the SEPT entry is BLOCKED  or PENDING _BLOCKED.  
7.2. Check  that TLB tracking was done.  
Else:  
7.3. Check that the SEPT entry is MAPPED, BLOCKED, BLOCKEDW, PENDING, PENDING_BLOCKED or 5 
PENDING_BLOCKEDW.  
8. For each L2 VM where the page is mapped:  
8.1. Walk the L2 Secure EPT based on the GPA operand and find the page mapping to be removed.  
8.2. Set the L2 SEPT entry state to L2_FREE.  10 
9. If an import session is in progress:  
9.1. Set the SEPT entry state to REMOVED.  
9.2. Record the migration epoch in the SEPT entry.  
Else:  
9.3. Set the SEPT entry state to FREE.  15 
10. On server platforms:  Atomically decrement TDR.CHLDCNT by 1, 512 or 5122 depending on the removed TD private 
page size (4KB, 2MB or 1GB, respectively).

Else:  
Else:  
page size (4KB, 2MB or 1GB, respectively).  
11. On server platforms:  Free the physical page:   Set the PAMT entry of the removed TD private page to PT_NDA.  
Table 5.103:  TDH. PHYMEM.PAGE.REMOVE Completion Status Codes (Returned in RAX) Definition  20 
TDX_SUCCESS  TDH.MEM.PAGE.REMOVE  is successful . 
November 2023  . Page 153 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.26.  TDH.MEM.RANGE.BLOCK Leaf  
Block a TD private GPA range (i.e., a Secure EPT page or a TD private page) at any level (4KB, 2MB, 1GB, 512GB, 256TB, 
etc.) from creating new GPA -to-HPA address translations.  
Table 5.104:  TDH.MEM.RANGE.BLOCK In put Operands Definition  
Must be 0  
2:0 Level  Level of the Secure EPT entry that maps the GPA range to be blocked – 
see 3.6.1  
Level must between 0 and 3 for a 4 -level EPT or between 0 and 4 for a 
5-level EPT.  
51:12  GPA  Bits 51:12 of the GPA range to be blocked  
Level 0 ( EPTE): None  
Level 1 ( EPDE):  Bits 20:12  
Level 2 ( EPD PTE):  Bits 29:12  
Level 3 (EPML4E):  Bits 38:12  
Level 4 ( EPML 5E): Bits 47:12  
 5 
Table 5.105:  TDH.MEM.RANGE.BLOCK Out put Operands Definition  
see 3.6.2  
November 2023  . Page 154 of 329 
3.6.2  
 
vary.  
TDH.MEM.RANGE.BLOCK finds the Secure EPT entry for the given GPA and level, and it marks it as blocked ( BLOCKED  or 5 
PENDING _BLOCKED as appropriate).  It records the current TD’s TLB epoch in the PAMT entry of the physical Secure EPT 
page or TD private page mapped by the blocked Secure EPT entry.  
Table 5.106:  TDH.MEM.RANGE.BLOCK Operands Information Definition  10 
Explicit/  
1GB  
and 
page or TD 
private page  Blob  None  Private  212+9*Level 
tree  N/A RW Private  N/A Exclusive  N/A N/A 
entry  SEPT 
Entry  RW Private  N/A Exclusive( h) N/A N/A 
trees  N/A RW Private  N/A Exclusive(i)  N/A N/A 
 
TDH.MEM.RANGE.BLOCK checks the memory operands per the table above when applicable during its flow.  The text 
1. The TDR page metadata in PAMT must be correct (PT must be PT_TDR).  15 
5. The specified level is of an EPT entry – i.e., 0 to 3 for 4 -level EPT or 0 to 4 for 5 -level EPT.  See 3.6.1  for a definition of 20 
EPT level.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 155 of 329 
6. Walk the Secure EPT based on the GPA operand and  find the Secure EPT entry to be blocked.  
7. Check  the Secure EPT entry is not free and not blocked (its state should be  NL_MAPPED, MAPPED  or PENDING ). 
If passed:  
8. Block the Secure EPT entry.  Set its state to NL_BLOCKED (if it was NL_MAPPED), BLOCKED  (if it was MAPPED ) or 5 
PENDING _BLOCKED (if it was PENDING ). 
9. For each L2 VM where there is an SEPT entry for the given GPA and level:  
9.1. Walk the L2 Secure EPT based on the GPA and level operand and find the L2 SEPT entry to be blocked.  
9.2. If the L1 SEPT entry is a leaf entry, then set the L2 SEPT entry state to L2_BLOCKED and save its attributes.  Note 
that if the page was blocked for writing, then the W bit has already been saved.  10 
9.3. Else (L1 SEPT entry is a non -leaf, mapping an SEPT page), set the non -leaf L2 SEPT entry state to NL_BLOCKED.  
Note:  There is no need to write TD_EPOCH to the L2 SEPT page’s PAMT.  Blocked epoch is implicit from the 
L1 SEPT page.  
If passed:  
10. Read the TD’s epoch (TDCS.TD_EPOCH ) and  write it to the PAMT entry of the blocked Secure EPT page or TD private 15 
page (PAMT.BEPOCH).  
Table 5.107:  TDH.MEM.RANGE.BLOCK Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MEM.RANGE.BLOCK is successful.  
November 2023  . Page 156 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.27.  TDH.MEM.RANGE.UNBLOCK Leaf  
Remove the blocking of a TD private GPA range (i.e., a Secure EPT page or a TD private page), at any level (4KB, 2MB, 
1GB, 512GB, 256TB etc.) previously blocked by TDH.MEM.RANGE.BLOCK.  
Table 5.108:  TDH.MEM.RANGE.UNBLOCK In put Operands Definition  
Must be 0  
2:0 Level  Level of the Secure EPT entry that maps the GPA range to be unblocked 
– see 3.6.1  
51:12  GPA  Bits 51:12 of the guest physical address range to be unblocked  
 5

Must be 0  
– see 3.6.1  
 5 
Table 5.109:  TDH.MEM.RANGE.UNBLOCK Out put Operands Definition  
see 3.6.2  
November 2023  . Page 157 of 329 
3.6.2  
 
vary.  
TDH.MEM.RANGE.UNBLOCK finds the blocked Secure EPT entry for the given GPA and level.  It checks  that the entry has 5 
been blocked and TLB tracking has been done, and then it marks the entry as non -blocked ( MAPPED  or PENDING  as 
appropriate).  
Blocking and TLB Tracking:  If the TD may be running, the unblocked GPA range must be blocked and TLB tracked.  Else 
no blocking and tracking is required.  10 
Table 5.110:  TDH.MEM.RANGE.UNBLOCK Operands Information Definition  
Explicit/  
1GB  
and 
page or TD 
entry  SEPT 
tree  N/A RW Private  N/A Exclusive(i)  N/A N/A 
 
TDH.MEM.RANGE.UNBLOCK checks the memory operands per the table above when applicable during its flow.  The text 15 
3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED).  20  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 158 of 329 
Intel TDX Application Binary Interface (ABI) Reference  4. The TD must have been initialized ( TDR.NUM_TDCX is the required number  and TDCS.OP_STATE is  either INITIALIZED 
5. The specified level is of an EPT entry (i.e., 0 to 3 for 4 -level EPT or 0 to 4 for 5 -level EPT) – see 3.6.1  for a definition 
of EPT level.  
6. Walk the Secure EPT based on the GPA operand and  find the Secure EPT page or TD private page to be unblocked.  
7. Check  the page’s parent Secure EPT entry is blocked ( NL_BLOCKED, BLOCKED  or PENDING _BLOCKED).  
8. If TLB tracking is required (based on the Secure EPT entry state and the TD’s OP_STATE):  
8.1. Check that TLB tracking was done.  
9.1. Walk the L2 Secure EPT based on the GPA operand and find the L2 SEPT entry to be unblocked.  
9.2. If the updated L1 SEPT entry is a leaf entry, and its state is not one of the PENDING* states, set the L2 SEPT 
entry state to L2_MAPPED and restore the L2 SEPT attributes.  
9.3. Else (L1 SEPT entry is a non -leaf, mapping an SEPT page), set the non -leaf L2 SEPT entry state to NL_MAPPED.  15 
10. Unblock the Secure EPT entry.  Atomically set its state to NL_MAPPED (if it was NL_BLOCKED), MAPPED  (if it was 
BLOCKED ) or PENDING  (if it was PENDING _BLOCKED).  
Table 5.111:  TDH.MEM.RANGE.UNBLOCK Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MEM.RANGE.UNBLOCK  is successful . 
  20  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 159 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.28.  TDH.MEM.RD  Leaf  
Read a 64b chunk from a debuggable guest TD private memory . 
Table 5.112:  TDH.MEM.RD Input Operands Definition  
Must be 0  
RCX The guest physical address of a naturally aligned 8 -byte chunk of a guest TD private  page  
 
Table 5.113:  TDH.MEM.RD Output Operands Definition  5 
see 3.6.2  
3.6.2  
R8 Content of the memory chunk  
In case of an error, as indicated by RAX, R8 returns 0  
 
vary.  
TDH.MEM.RD reads a 64b chunk from a debuggable guest TD private memory . 10 
November 2023  . Page 160 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.114:  TDH.MEM.RD  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX GPA  TD private 
memory  Blob  R Private  8B None  None  None  
Implicit  N/A GPA  Secure EPT tree  N/A R Private  N/A Shared  N/A N/A 
entry  SEPT 
Entry  R Private  N/A Exclusive  N/A N/A 
 
TDH.MEM.RD checks the memory operands per the table above when applicable during its flow.  The text below does 
not explicitly mention those checks, except when necessary.  
3. The TD keys are configured on the hardware (TDR.KEY_STATE is TD_KEYS_CONFIGURED).  
4. TDCS must have been initialized (TDR.INIT is TRUE).  
5. The TD is debuggable (TDCS.ATTRIBUTES.DEBUG is 1).  10 
6. Walk the Secure EPT based on the GPA operand and find the leaf entry.

entry  SEPT 
 
6. Walk the Secure EPT based on the GPA operand and find the leaf entry.  
7. Check that the Secure EPT entry state is PRESENT.  
If passed:  
8. Read the content of the memory chunk.  15 
Table 5.115:  TDH.MEM.RD Completion Status Codes (Returned in RAX) Definition  
TDX_EPT_ENTRY_NOT_PRESENT   
TDX_SUCCESS   
TDX_TD_NON_DEBUG    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 161 of 329 
November 2023  . Page 162 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.29.  TDH.MEM.SEPT.ADD  Leaf  
Add and map 4KB L1 and L2 Secure EPT page s to a TD.  
Table 5.116:  TDH.MEM.SEPT.ADD  Input Operands Definition  
 
2:0 Level  Level of the non-leaf Secure EPT entry that will map the new Secure 
EPT page – see 3.6.1  
Level must between 1 and 3 for a 4 -level EPT or between 1 and 4 for a 
51:12  GPA  Bits 51:12 of the guest physical address of to be mapped for the new 
Level 1 (EPT):  Bits 20:12  
Level 2 (EPD):  Bits 29:12  
Level 3 (EPDPT):  Bits 38:12  
Level 4 (EPML4):  Bits 47:12  
0 ALLOW_EXISTING  Flags that TDH.MEM.SEPT.ADD should not fail if an SEPT page to be 
added already exists in the L1 or L2 SEPT tree.  Instead, it should just 
return an indication in the output operand, as described below.  
51:12  TDR_HPA  Bits 51:12 of the host physical address of the parent TDR page (HKID 
bits must be 0)  
R8 Host physical address of the new L1 Secure EPT page to be added to the TD (HKID bits must be 0)  
For TDH.MEM.SEPT.ADD version 1 or higher:  
• If the value of R8 is NULL_PA ( -1), no L1 SEPT page is added.  
• Else, bit 63 of R8 is ignored.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 163 of 329 
R9 For TDH.MEM.SEPT.ADD version 1 or higher, R9 specifies the HPA of a new L2 VM #1 Secure EPT 
page to be added to the TD (HKID bits must be 0).  
• If the value of R9 is NULL_PA ( -1), no L2 VM #1 SEPT page is added.  
• Else, bit 63 of R9 is ignored.  
R10 For TDH.MEM.SEPT.ADD version 1 or higher, R10 specifies the HPA of a new L2 VM #2 Secure EPT 
• If the value of R10 is NULL_PA ( -1), no L2 VM #2 SEPT page is added.  
• Else, bit 63 of R10 is ignored.  
R11 For TDH.MEM.SEPT.ADD version 1 or higher, R11 specifies the HPA of a new L2 VM #3 Secure EPT 
• If the value of R11 is NULL_PA ( -1), no L2 VM #3 SEPT page is added.  
• Else, bit 63 of R11 is ignored.  
 
Table 5.117:  TDH.MEM.SEPT.ADD  Output Operands Definition  
RCX In case of an interruption, as indicated by RAX returning TDX_INTERRUPTED_RESUMABLE, RCX is 
see 3.6.2  
RDX  In case of an interruption, as indicated by RAX returning TDX_INTERRUPTED_RESUMABLE, RDX is 
3.6.2  
R8 For TDH.MEM.SEPT.ADD version 1 or higher:  
• If a provided L1 SEPT page has been added, R8 returns NULL_PA ( -1). 
• Else, if an L1 SEPT page already exists, bit 63 of R8 is set to 1, other bits are unmodified.  
• Else, bit 63 of R8 is cleared to 0, other bits are unmodified.  
For TDH.MEM.SEPT.ADD version 0, R8 is unmodified.  
R9 For TDH.MEM.SEPT.ADD version 1 or higher:  
• If a provided L2 VM #1 SEPT page has been added, R9 returns NULL_PA ( -1). 
• Else, if an L2 VM #1 SEPT page already exists, bit 63 of R9 is set to 1, other bits are 
• Else, bit 63 of R9 is cleared to 0, other bits are unmodified.  
For TDH.MEM.SEPT.ADD version 0, R9 is unmodified.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 164 of 329 
R10 For TDH.MEM.SEPT.ADD version 1 or higher:  
• If a provided L2 VM #2 SEPT page has been added, R10 returns NULL_PA ( -1). 
• Else, if an L2 VM #2 SEPT page already exists, bit 63 of R10 is set to 1, other bits are 
• Else, bit 63 of R10 is cleared to 0, other bits are unmodified.  
For TDH.MEM.SEPT.ADD version 0, R10 is unmodified.  
R11 For TDH.MEM.SEPT.ADD version 1 or higher:  
• If a provided L2 VM #3 SEPT page has been added, R11 returns NULL_PA ( -1). 
• Else, if an L2 VM #3 SEPT page already exists, bit 63 of R11 is set to 1, other bits are 
• Else, bit 63 of R11 is cleared to 0, other bits are unmodified.  
For TDH.MEM.SEPT.ADD version 0, R11 is unmodified.  
 
vary.  
TDH.MEM.SEPT.ADD adds a set of 4KB Secure EPT pages to a TD and maps them to the provided GPA and level.   SEPT 5 
pages can be added to the main (L1) SEPT tree and/or to one or more of the L2 VMs’ SEPT trees.  TDH.MEM.SEPT.ADD  
initializes the SEPT pages to hold 512 free entries using the TD’s ephemeral private key.   
L2 SEPT trees may not be deeper than the L1 SEPT tree.  To add an L2 SEPT page at some level, there must either already 
be an L1 SEPT page at that level, or an L1 SEPT page at that level is being added by the current TDH.MEM.SEPT.ADD 
invocation.  10 
Enumeration:  Availability of TDH. MEM.SEPT.ADD version 1 is enumerated by TDX_FEATURES0.TD_PARTITIONING (bit 
7), readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.MEM.SEPT.ADD with a version 
number higher than 0 returns a TDX_OPERAND_INVALID(RAX) status.  
Interruptibility:  TDH.MEM.SEPT.ADD is interruptible.  If a pending interrupt is detected during operation, 
TDH.MEM.SEPT.ADD returns with a TDX_INTERRUP TED_RESUMABLE status in RAX.  The SEPT page HPA 15 
values in R8, R9, R10 and R11 are updated.  
TDH.MEM.SEPT.ADD is designed to be invoked in a loop until all required SEPT pages have been added:  
1. Call TDH.MEM.SEPT.ADD.  
2. While RAX indicates TDX_INTERRUP TED_RESUMABLE:  
2.1. Call TDH.MEM.SEPT.ADD with the GPR values as returned by the previous call.  20 
2.2. If an error indication other than TDX_INTERRUPTED_RESUMABLE is returned, abort.  
The table below shows the values of the SEPT HPA arguments in R8 – R11 when version 1 or higher is 
selected and no error occurs (RAX returns TDX_SUCCESS or TDX_INTERRUPTED_RESUMABLE).  
Table 5.118:  Meaning of TDH.MEM.SEPT.ADD’s SEPT HPA Arguments on Input and Output (Version > 0, No Error)  
Value  R8 – R11 on Input  R8 – R11 on Output  
NULL_PA ( -1) No new SEPT page to add  New SEPT page has been added  
add 
Bit 63:  Ignored  N/A 
Bit 63:  1 SEPT page already exists, new SEPT 
page has not been used  
 25  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 165 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Atomicity:  Unless terminated with a TDX_INTERRUP TED_RESUMABLE indication, TDH.MEM.SEPT.ADD either fully 
succeeds in adding the requested SEPT pages or  doesn’t add any page.  
In case of an interrupt (TDX_INTERRRUPTED_RESUMABLE), if the host VMM invokes

add 
In case of an interrupt (TDX_INTERRRUPTED_RESUMABLE), if the host VMM invokes 
TDH.MEM.SEPT.ADD in a loop as described above and  doesn’t initiate other operations that impact 
TDH.MEM.SEPT.ADD (e.g., TDH.MEM.RANGE.BLOCK), then this atomicity still holds at the end of the 5 
loop.  
Cache Flush : Before calling TDH.MEM.SEPT.ADD, the host VMM should ensure that no cache lines associated with 
the added SEPT physical pages are in a Modified state, as described in the [Base Spec].  
of the Intel TDX Module API . 10 
Table 5.119:  TDH.MEM.SEPT.ADD  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX GPA  
and 
page  (GPA)7 SEPT_PAGE  RW Private  212+9*Level 
Explicit  R8 HPA  Secure EPT 
page  (HPA)7 SEPT_PAGE  RW Private  4KB Exclusive  Shared  Shared  
 
TDH.MEM.SEPT.ADD  checks the memory operands per the table above when applicable during its flow.  The text below 
The function checks the following conditions:  15 
3. The TD keys are configured on the hardware ( TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED ). 
4. The TD must have been initialized by TDH.MNG.INIT and not paused by THH.EXPORT.PAUSE, or an import session is 
in progress, started by TDH.IMPORT.STATE.IMMUTABLE and not failed . 20 
5. The specified level is of an EPT non -leaf entry  – i.e., 1 to 3 for 4 -level EPT or 1 to 4 for 5 -level EPT.  See 3.6.1  for a 
definition of EPT level.  
 
7 RCX and R8 denote the same Secure EPT page operand, using HPA and GPA respectively   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 166 of 329 
6. SEPT physical pages checks:  
6.1. Check that no non -NULL_PA address has been provided in R9, R10 or R11 for a non -existing L2 VM.  
6.2. If the version number indicated in RAX is 1 or higher, check and lock the new SEPT physical pages:  
6.2.1.  For each of the SEPT page HPAs provided in R8, R9, R10 and R11, if the value is not NULL_PA, lock the 5 
PAMT entry and check that the page metadata is correct (PT must be PT_NDA).  
6.3. Else (version is 0):  
6.3.1.  For the L1 SEPT page HPA provided in R8, lock the PAMT entry and check that the page metadata is 
correct (PT must be PT_NDA).  
If passed:  10 
7. SEPT trees walk and state checks:  
7.1. Walk the L1 Secure EPT based on the requested GPA and level and find the SEPT entry.  
If L1 SEPT walk succeeded:  
7.2. If requested to add an L1 SEPT page (i.e., R8 is a not a NULL_PA):  
7.2.1.  The L1 SEPT entry state should either be FREE,  15 
7.2.2.  Or, if ALLOW_EXISTING is 1, the L1 SEPT entry state can be NL_MAPPED (i.e., there’s already an L1 
SEPT page at the requested level).  In this case, mark the return value in R8 to indicate that the new L1 
SEPT page was not used.  
7.2.3.  On other L1 SEPT entry states, abort with an error indication in RAX.  
7.3. Else (no L1 SEPT page is to be added):  20 
7.3.1.  Check that an L1 SEPT page exists (the L1 SEPT entry state is NL_MAPPED).  
If passed:  
7.4. If the version number indicated in RAX is 1 or higher, then for each L2 VM do the following:  
7.4.1.  Walk the L2 Secure EPT based on the requested GPA and level and find the L2 SEPT entry.  
If L2 SEPT walk succeeded:  25 
7.4.2.  The L2 SEPT entry state should either be L2_FREE,  
7.4.3.  Or, if ALLOW_EXISTING is 1, the L2 SEPT entry state can be L2_NL_MAPPED (i.e., there’s already an L2 
SEPT page at the requested level).  In this case, mark the return value in R9, R10 or R11 to indicate that 
the new SEPT page was not used.  
7.4.4.  On other L2 SEPT entry states, abort with an error indication in RAX.  30 
If passed:  
8. SEPT page additions:  
8.1. If the L1 SEPT entry state is FREE:  
8.1.1.  Initialize the new L1 Secure EPT page, indicating 512 entries in the FREE state, using the TD’s ephemeral 
private HKID and direct writes (MOVDIR64B).  35 
8.1.2.  Update the parent L1 Secure EPT entry with the new Secure EPT page HPA and NL_MAPPED state.  
8.1.3.  Increment TDR.CHLDCNT.  
8.1.4.  Update the new Secure EPT page’s PAMT entry with the PT_EPT page type and the TDR physical 
8.1.5.  If the version number indicated in RAX is 1 or higher, set the returned value of R8 to NULL_PA, 40 
indicating that a new SEPT page has been added.  
If passed:  
8.2. If the version number indicated in RAX is 1 or higher, then for each L2 VM do the following:  
8.2.1.  If the L2 SEPT entry state is L2_FREE:  
8.2.1.1.  If an interrupt is pending, abort with a TDX_INTERRUPTED_RESUMABLE status.  45 
8.2.1.2.  Initialize the new L2 Secure EPT page, indicating 512 entries in the L2_FREE state, using the 
TD’s ephemeral private HKID and direct writes (MOVDIR64B).  
8.2.1.3.  Update the parent Secure EPT entry with the new Secure EPT page HPA and NL_MAPPED state.  
8.2.1.4.  Increment TDR.CHLDCNT.  
8.2.1.5.  Update the new L2 Secure EPT page’s PAMT entry with the PT_EPT page type and the TDR 50 
physical address as the OWNER.  
8.2.1.6.  Set the returned value of R9, R10 or R11 to NULL_PA, indicating that a new L2 SEPT page has 
been added.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 167 of 329 
Table 5.120:  TDH.MEM.SEPT.ADD  Completion Status Codes (Returned in RAX) Definition  
TDX_INTERRUPTED_RESUMABLE  TDH.MEM.SEPT.ADD’s operation has been interrupted by an 
external event; it may be resumed from the point it was 
interrupted by calling it again.  
TDX_L2_SEPT_ENTRY_NOT_FREE   
TDX_SUCCESS  TDH.MEM.SEPT.ADD is successful  
November 2023  . Page 168 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.30.  TDH.MEM.SEPT.RD Leaf  
Read a Secure EPT entry.  
Table 5.121:  TDH.MEM.SEPT.RD In put Operands Definition  
RCX GPA Mapping  EPT mapping information : 
2:0 Level  Level of the Secure EPT entry to read – see 3.6.1  
Level must between 0 and 3 for a 4 -level EPT or between 0 
and 4 for a 5 -level EPT.  
51:12  GPA  Bits 51:12 of the guest physical address for the Secure EPT 
entry to read  
Depending on the level, the following least significant bits 
must be 0:  
63:52 Reserved  Reserved:  must be 0  
RDX  TD Handle 
and Flags  TD handle and flags:  
0 READ_L2_ATTR  Flags that L2 attributes should be returned in R8  
51:12  HPA  Bits 51:12 of the host physical address of the parent TDR 
page (HKID bits must be 0)  
 
Table 5.122:  TDH.MEM.SEPT.RD Out put Operands Definition  5 
RAX  Status  SEAMCALL instruction return code – see 5.3.1   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 169 of 329

must be 0:  
 
November 2023  . Page 169 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Operand   Description  
RCX SEPT Entry  Secure EPT entry architectural content – see 3.6.2  
The architectural content represents how the Secure EPT maps a private memory page 
or a Secure EPT page; it may be different than the actual contents of the Secure EPT 
entry.  Software should consult the Secure EPT information returned in RDX.  
• In case of successful operation, the requested entry’s architectural content is 
returned.  
• In case of EPT walk error, the architectural content of the Secure EPT entry where 
the error was detected is returned.  
RDX  SEPT Level 
and State  Secure EPT entry level and state – see 3.6.2  
• In case of successful operation, the requested entry’s information is returned.  
• In case of EPT walk error, the information of the Secure EPT entry where the error 
was detected is returned.  
R8 L2 Attributes  If the TD’s ATTRIBUTES.DEBUG is 1 and READ_L2_ATTR is 1, R8 returns the L2 
attributes of the applicable L2 SEPT entries, in the format defined in 3.6.3 . 
Else, R8 is unmodified.  
 
vary.  
TDH.MEM.SEPT.RD reads a Secure EPT entry.  If the TD’s ATTRIBUTES.DEBUG is 1, then TDH.MEM.SEPT.RD can return the 5 
page’s L2 attributes.  
Table 5.123:  TDH.MEM.SEPT.RD Operands Information Definition  
Explicit/  
1GB  
and 
entry  SEPT_ENTRY  R Private  212+9*Level 
Tree  N/A R Private  N/A Shared  N/A N/A 
Tree  N/A R Private  N/A Shared(i)  N/A N/A  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 170 of 329 
1GB  
 
TDH.MEM.SEPT.RD checks the memory operands per the table above when applicable during its flow.  The text below 
5. The specified level is of an EPT entry  (i.e., 0 to 3 for 4 -level EPT or 0 to 4 for 5 -level EPT) – see 3.6.1  for a definition 10 
6. If READ_L2_ATTR is set, check that TDCS.ATTRIBUTES.DEBUG is 1.  
If passed:  
7. Walk the L1 Secure EPT based on the GPA and level operand and find the Secure EPT entry.  15 
8. Read the L1 Secure EPT entry contents.  
9. If READ_L2_ATTR is set:  
9.1. If the L1 SEPT entry is a leaf entry, then for each L2 VM where the page is mapped  
9.1.1.  Walk the L2 SEPT based on the GPA and level operand and find the L2 SEPT entry.  
9.1.2.  Read the leaf L2 SEPT entry and build the L2 attributes to be returned.  20 
9.2. If the L1 SEPT entry is a non -leaf entry, then for each L2 VM:  
9.2.1.  Walk the L2 SEPT based on the GPA and level operand, and find the non -leaf L2 SEPT entry, if any.  
9.2.2.  Read the non -leaf L2 SEPT entry and build the L2 attributes to be returned.  
9.3. Else (the L1 SEPT entry is FREE):  
9.3.1.  Return 0 as the L2 attributes.  25 
Table 5.124:  TDH.MEM.SEPT.RD Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MEM.SEPT.RD  is successful . 
TDX_SYS_SHUTDOWN    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
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November 2023  . Page 172 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.31.  TDH.MEM.SEPT.REMOVE Leaf  
Remove an empty L1 Secure EPT page and any associated L2 SEPT pages from a TD.  
Table 5.125:  TDH.MEM.SEPT.REMOVE In put Operands Definition  
Versions 0 and 1 are supported.   See the enumeration details below.  
2:0 Level  Level of the non -leaf Secure EPT entry that maps the Secure EPT page 
to be removed – see 3.6.1  
Level must be between 1 and 3 for a 4 -level EPT or between 1 and 4  for 
a 5-level EPT.  
51:12  GPA  Bits 51:12 of the guest physical address for the Secure EPT page to be 
removed  
 
Table 5.126:  TDH.MEM.SEPT.REMOVE Out put Operands Definition  5 
RCX If TDH.MEM.SEPT.REMOVE succeeded, RCX returns the HPA of the removed SEPT page  (HKID bits 
are set to 0) . 
see 3.6.2  
November 2023  . Page 173 of 329 
3.6.2  
R9 If TDH.MEM.SEPT.REMOVE version is 1 or higher:  
R10 If TDH.MEM.SEPT.REMOVE version is 1 or higher:  
bits are set to 0) . 
R11 If TDH.MEM.SEPT.REMOVE version is 1 or higher:  
 
vary.  
TDH.MEM.SEPT.REMOVE removes an empty Secure EPT page or pages, with all 512 entries marked as FREE, from the 5 
TD’s Secure EPT trees.  
The L1 SEPT page and all existing L2 SEPT pages at the requested GPA and level are removed.  
On successful operation, it TDH.MEM.SEPT.REMOVE marks the removed 4KB physical pages as free in PAMT.

vary.  
On successful operation, it TDH.MEM.SEPT.REMOVE marks the removed 4KB physical pages as free in PAMT.  
Enumeration:  Availability of TDH. MEM.SEPT.REMOVE version 1 is enumerated by 
supported, calling TDH.MEM.SEPT.REMOVE with a version number higher than 0 returns a 
Blocking and TLB Tracking:  If the TD may be running, the removed GPA range must be blocked and TLB tracked.  Else 
Atomicity:  TDH.MEM.SEPT.REMOVE either fully succeeds in removing the requested SEPT pages or 
doesn’t remove any page.  
Cache Flush and Init:  After the SEPT pages have been removed, the host VMM should flush the  physical pages’ 
cache lines and initialize their content before they are reused, as described in the [Base 
Spec].  20 
November 2023  . Page 174 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.127:  TDH.MEM.SEPT.REMOVE Operands Information Definition  
Explicit/  
1GB  
and 
Tree  N/A RW Private  N/A Exclusive  N/A N/A 
entry  SEPT Entry  RW Private  N/A Exclusive( h) N/A N/A 
Trees  N/A RW Private  N/A Exclusive(i)  N/A N/A 
 
TDH.MEM.SEPT.REMOVE checks the memory operands per the table above when applicable during its flow.  The text 
3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD _KEYS_CONFIGURED).  
4. The TD must either have been initialized by TDH.MNG.INIT, or an import session has begun by 
5. The specified level is of a non -leaf EPT entry (i.e., 1 to 3 for 4 -level EPT or 1 to 4 for 5 -level EPT) – see 3.6.1  for a 
6. Walk the L1 Secure EPT based on the GPA operand and  find the non-leaf SEPT entry of the SEPT  page to be removed.  
7. If TLB tracking is required (based on the Secure EPT entry state and the TD’s OP_STATE):  15 
7.1. Check  the L1 Secure EPT entry is a non-leaf blocked ( NL_BLOCKED ) entry.  
8. Scan the L1 Secure EPT page content and check  all 512 entries are FREE . 
If passed:  
9. For each L2 VM:  20 
9.1. Walk the L2 Secure EPT based on the GPA and level operand and find the applicable non -leaf SEPT entry.  
9.2. If an L2 SEPT entry was found, and its state is not FREE:  
9.2.1.  Atomically decrement TDR.CHLDCNT.  
9.2.2.  Set the PAMT entry of the removed L2 SEPT page to PT_NDA.  
9.2.3.  Set the parent L2 Secure EPT entry to FREE.  25 
If passed:  
10. Set the parent L1 Secure EPT entry to FREE.  
11. Atomically decrement TDR.CHLDCNT.  
12. Set the PAMT entry of the removed L1 Secure EPT page to PT_NDA.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 175 of 329 
Table 5.128:  TDH.MEM.SEPT.REMOVE Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MEM.SEPT.REMOVE  is successful . 
 
November 2023  . Page 176 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.32.  TDH.MEM.TRACK Leaf  
Increment the TD’s TLB epoch counter.  
Table 5.129:  TDH.MEM.TRACK In put Operands Definition  
Must be 0  
RCX The physical address of the parent TDR page  (HKID bits must be 0)  
 
Table 5.130:  TDH.MEM.TRACK Out put Operands Definition  5 
 
vary.  
TDH.MEM.TRACK increments the TD’s TLB epoch counter.  10 
Table 5.131:  TDH.MEM.TRACK Operands Information Definition  
Explicit/  
1GB  
Implicit  N/A N/A TDCS structure  TDR  RW Opaque  4KB Shared(i)  N/A N/A 
Tracking Fields  N/A RW Opaque  N/A Exclusive  N/A N/A 
 
In addition to the memory operand checks per the table above, the function checks the following:  15 
1. The TDR page metadata in PAMT must be correct ( PT must be PT_TD R). 
4. The TD must have been initialized ( by TDH.MNG.INIT or TDH.IMPORT.STATE.IMMUTABLE ).  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 177 of 329 
Intel TDX Application Binary Interface (ABI) Reference  If successful, the function does the following as a critical section, protected by exclusively locking the TDCS epoch trackin g 
fields TD_EPOCH and REFCOUNT.  A concurrent TDH.VP.ENTER may cause this locking to fail with a TDX_OPERAND_BUSY 
status code ; in this case the caller is expected to retry TDH.MEM.TRACK.  
5. Lock the TDCS epoch tracking fields in exclusive mode.  
6. Check  that the TD’s previous epoch’s REFCOUNT is 0.  This helps ensure  that no REFCOUNT information will be lost 5 
when TD_EPOCH is incremented in the next step.  
7. If successful, increment the TD’s epoch counter (TDCS.TD_EPOCH).  
8. Release the exclusive mode locking of the epoch tracking fields.  
Table 5.132:  TDH.MEM.TRACK Completion Status Codes (Returned in RAX) Definition  10 
Note the special case where the indicated operand is 
TLB_EPOCH.  This may happen due to a conflict with 
TDH.VP.ENTER.  The host VMM should retry 
TDX_PREVIOUS_TLB_EPOCH_BUSY   
TDX_SUCCESS  TDH.MEM.TRACK is successful.  
November 2023  . Page 178 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.33.  TDH.MEM.WR  Leaf  
Write a 64b chunk from a debuggable guest TD private memory . 
Table 5.133:  TDH.MEM.WR Input Operands Definition  
Bits Field  Description

Must be 0  
R8 Data to be written to memory  
 
Table 5.134:  TDH.MEM.WR Output Operands Definition  5 
RCX Secure EPT entry architectural content – see 3.6.2  
• In case of successful operation, the requested entry’s architectural content is returned.  
• In case of EPT walk error, the architectural content of the Secure EPT entry where the error 
RDX  Secure EPT entry level and state – see 3.6.2  
• In case of EPT walk error, the information of the Secure EPT entry where the error was 
detected is returned.  
R8 Previous content of the memory chunk  
 
vary.  
TDH.MEM.WR writes a 64b chunk to a debuggable guest TD private memory . 10  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 179 of 329 
Table 5.135:  TDH.MEM. WR Operands Information Definition  
Explicit/  
1GB  
memory  Blob  RW Private  8B None  None  None  
entry  SEPT 
 
TDH.MEM.WR checks the memory operands per the table above when applicable during its flow.  The text below does 5 
3. The TD keys are configured on the hardware (TDR.KEY_STATE is TD_KEYS_CONFIGURED).  10 
5. The TD is debuggable (TDCS.ATTRIBUTES.DEBUG is 1).  
7. Check that the Secure EPT entry state is PRESENT.  15 
If passed:  
8. Read the content of the memory chunk.  
9. Write the new content of the memory chunk.  
Table 5.136:  TDH.MEM.WR Completion Status Codes (Returned in RAX) Definition  20 
TDX_TD_FATAL    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
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November 2023  . Page 181 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.34.  TDH.MIG.STREAM.CREATE Leaf  
Create a Migration Stream and its MIGSC control structure . 
Table 5.137:  TDH.MIG.STREAM.CREATE Input Operands Definition  
Must be 0  
RCX The physical address of a page where MIGSC will be created  
RDX  The physical address of the owner TDR page  (HKID bits must be 0)  
 
Table 5.138:  TDH.MIG.STREAM.CREATE Output Operands Definition  5 
 
vary.  
TDH.MIG.STREAM.CREATE creates a new Migration Stream and its MIGSC control structure.  This function can be invoked 10 
at any time after the TDCS pages have been allocated.  
TDH.MIG.STREAM.CREATE can only be successfully invoked if no migration session is in progress.  
Cache Flush : Before calling TDH.MIG.STREAM.CREATE, the host VMM should ensure that no cache lines associated 
with the added MIGSC physical page are in a Modified state, as described in the [Base Spec].  
Table 5.139:  TDH.MIG.STREAM.CREATE Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  MIGSC page  MIGSC  RW Opaque  4KB Exclusive  Shared  Shared  
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  4KB Shared(i)  N/A N/A 
Implicit  N/A N/A TDCS.OP_STATE  OP_STATE  RW Opaque  N/A Exclusive(h)  N/A N/A 
November 2023  . Page 182 of 329 
1GB  
Implicit  N/A N/A Mig. Stream 
Stream 
context  RW Opaque  N/A Exclusive (i) N/A N/A 
 
In addition to the explicit memory operand checks per the table above, the function checks the following conditions:  
3. The TD keys are configured on the hardware (TDR.LIFECYCLE_STATE is TD_KEYS_CONFIGURED).  5 
4. TDCS pages have been allocated (TDR.NUM_TDCX is the required number).  
5. No migration session is in progress (TDCS.OP_STATE is none of *_EXPORT or *_IMPORT).  
6. The MIGSC page metadata in PAMT is correct (PT is PT_NDA).  
7. The number of already created migration streams is lower than the maximum allowed.  
8. Increment the number of migration streams (TDCS.NUM_MIG_STREAMS).  
9. Initialize the MIGSC page contents using direct write (MOVDIR64B).  
10. Initialize the applicable forward link entry in TDCS (TDCS.MIGSC_LINK):  
o Set MIGSC_PA to the MIGSC page HPA.  
o Clear the INITIALIZED and ENABLED flags.  15 
11. Atomically increment TDR.CHLDCNT.  
12. Initialize the MIGSC page metadata in PAMT (Set PT to PT_TDCX, OWNER to the TDR HPA).  
Table 5.140:  TDH.MIG.STREAM.CREATE Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MIG.STREAM.CREATE  is successful . 
 20 
November 2023  . Page 183 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.35.  TDH.MNG.ADDCX Leaf  
Add a TDC S physical  page to a guest TD.

 20 
Add a TDC S physical  page to a guest TD.  
Table 5.141:  TDH.MNG.ADDCX In put Operands Definition  
Must be 0  
RCX The physical address of a page where TDCX will be added  (HKID bits must be 0)  
 
Table 5.142:  TDH.MNG.ADDCX Out put Operands Definition  5 
 
vary.  
TDH.MNG.ADDCX adds a TDC S physical  page , which is a child of the specified TDR.  10 
Cache Flush : Before calling TDH.MNG.ADDCX, the host VMM should ensure that no cache lines associated with the 
added TDCS physical page are in a Modified state, as described in the [Base Spec].  
Table 5.143:  TDH.MNG.ADDCX Operands Information Definition  15 
Explicit/  
1GB  
Explicit  RCX HPA  TDCX page  Blob  RW Opaque  4KB Exclusive  Shared  Shared  
Explicit  RDX  HPA  TDR page  TDR  RW Opaque  4KB Exclusive  Shared  Shared  
 
3. The number of TDCX pages (TDR.NUM_TDCX) is smaller than the required number.  20 
4. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS _CONFIGURED).  
5. The new TDCX page metadata in PAMT must be correct (PT must be PT_NDA).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 184 of 329 
6. Initialize the TDCX page contents using direct writes (MOVDIR64B).  
7. Set the TDCX pointer entry in the TDR.TDCX_PA array.  
8. Increment TDR.NUM_TDCX.  
9. If TDR.NUM_TDCX is equal to the required number of TDCX pages : 5 
9.1. Mark the TD as uninitialized (set TDCS.OP_STATE to UNINITIALIZED).  
9.2. Generate a migration encryption key, to be used in the next migration session.  
If failed:  
9.3. Decrement TDR.NUM_TDCX.  
Table 5.144:  TDH.MNG.ADDCX Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MNG.ADDCX is successful  
TDX_TDCX_NUM_INCORRECT   
November 2023  . Page 185 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.36.  TDH.MNG.CREATE Leaf  
Create a new guest TD and its TDR root page . 
Table 5.145:  TDH.MNG.CREATE In put Operands Definition  
Must be 0  
RCX The physical address of a page where TDR will be created  (HKID bits must be 0)  
RDX  Bits Name  Description  
15:0  HKID  The TD’s ephemeral private HKID  
63:16  Reserved  Reserved:  must be 0  
 
Table 5.146:  TDH.MNG.CREATE Out put Operands Definition  5 
 
vary.  
TDH.MNG.CREATE creates a TDR page  which is the root page of a new guest TD.  10 
Cache Flush : Before calling TDH.MNG.CREATE, the host VMM should ensure that no cache lines associated with the 
new TDX physical page are in a Modified state, as described in the [Base Spec].  
Table 5.147:  TDH.MNG.CREATE Operands Information Definition  15 
Explicit/  
1GB  
Implicit  N/A N/A KOT  KOT  N/A Hidden  N/A Exclusive  N/A N/A 
 
1. The TDR page metadata in PAMT must be correct (PT must be PT_NDA).  
2. The value of the specified HKID must be in the range configured for TDX.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 186 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3. The KOT entry for the specified HKID must be marked as HKID_FREE . 
4. Zero out the TDR page contents using direct write (MOVDIR64B).  
5. Initialize the key management fields.  
6. Initialize the state variables.  5 
7. Initialize the TD management fields . 
8. Initialize the TD preserving fields (handoff version and current SEAMDB entry’s index/nonce pair).  
9. Mark the KOT entry for the specified HKID as HKID_ ASSIGNED.  
10. Initialize the TDR page metadata in PAMT.  
Table 5.148:  TDH.MNG.CREATE Completion Status Codes (Returned in RAX) Definition  
TDX_HKID_NOT_FREE   
TDX_RND_NO_ENTROPY  Random TD_UUID generation (e.g., RDRAND or RDSEED) 
failed because the hardware random number generator did 
not have enough entropy.  The host VMM should retry the 
TDX_SUCCESS  TDH.MNG.CREATE  is successful . 
November 2023  . Page 187 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.37.  TDH.MNG.INIT Leaf  
Initialize TD -scope control structures TDR and TDCS.  
Table 5.149:  TDH.MNG.INIT In put Operands Definition  
Must be 0  
RCX The physical address of a TDR page  (HKID bits must be 0)  
RDX  The physical address (including HKID bits) of an input TD_PARAMS_STRUCT   
 
Table 5.150:  TDH.MNG.INIT Out put Operands Definition  5 
RCX Extended error information  
In case of a TD_PARAMS_STRUCT.CPUID_CONFIG error, RCX returns the applicable CPUID 
information as shown below.  
In all other cases, RCX returns 0.  
31:0  LEAF  CPUID leaf number  
63:32  SUBLEAF  CPUID sub -leaf number:  if sub -leaf is not applicable, value is -1 
(0xFFFFFFFF).  
 
Leaf Function Latency  
TDH.MNG.INIT execution time may be longer than most TDX module interface functions execution time.  No interrupts 
(including NMI and SMI) are processed by the logical processor during that time.  
Leaf Function Description  10 
vary.  
TDH.MNG.INIT initializes the TD -scope control structures TDR and TDCS based on a set of TD parameters provided as 
input.

vary.  
input.  
November 2023  . Page 188 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.151:  TDH.MNG.INIT Operands Information Definition  
Explicit/  
1GB  
Explicit  RDX  HPA  TD Parameters  TD_PARAMS  R Shared  1024B  None  N/A N/A 
 
4. All the required TDCS pages have been added (by TDH.MNG.ADDCX) but the TD has not have been initialized 
(TDCS.OP_STATE is UNINITIALIZED).  
5. Set the TDCS TD management fields to their initial values.  10 
6. Read the input parameters structure fields.  
7. Check the input parameters and initialize the TDCS logical structure.  
7.1. Check  that ATTRIBUTES and XFAM bits that must be fixed -0 or fixed -1 are set correctly.  
7.2. Check  XFAM bit groups that must have certain values (e.g., AVX bits 7:5).  
7.3. Check the other input parameters.  See the definition of TD_PARAMS in 3.4.5  for details.  15 
If passed:  
8. Initialize EPTP to point to TDCS.SEPT_ROOT.  
9. Initialize the MSR bitmaps based on ATTRIBUTES and XFAM.  
10. Initialize the TDCS measurement fields.  
11. Mark the TD as initialized (set TDCS.OP_STATE to INITIALIZED ). 20 
Table 5.152:  TDH.MNG.INIT Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MNG.INIT is successful.  
TDX_TD_KEYS_NOT_CONFIGURED    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
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November 2023  . Page 190 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.38.  TDH.MNG.KEY.CONFIG  Leaf  
Configure the TD ephemeral private key on a single package.  
Table 5.153:  TDH.MNG.KEY.CONFIG  Input Operands Definition  
Must be 0  
 
Table 5.154:  TDH.MNG.KEY.CONFIG  Output Operands Definition  5 
 
TDH.MNG.KEY.CONFIG execution time may be longer than most TDX module interface functions execution time.  No 
interrupts (including NMI and SMI) are processed by the logical processor during that time.  
vary.  
TDH.MNG.KEY.CONFIG  configures the TD’s ephemeral private key on a single package.  
Table 5.155:  TDH.MNG.KEY.CONFIG  Operands Information  
Explicit/  
1GB  
Implicit  N/A N/A KETs on current 
package  N/A N/A Hidden  N/A Exclusive  N/A N/A 
 
In addition to the memory operand checks per the table above , the function  checks the following conditions:  
2. The TD is not in a FATAL state (TDR.FATAL is FALSE) . 20 
3. HKID has been  assigned to the TD; TDR.LIFECYCLE_STATE  is TD_HKID_ASSIGNED .  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 191 of 329 
Intel TDX Application Binary Interface (ABI) Reference  If successful, the function  does  the following:  
4. Configure the TD ephemeral private key on the package.  
4.1. This operation may fail due to a conflict with a concurrent TDH.MNG.KEY.CONFIG  or PCONFIG running on the 
same package.  
4.2. A CPU -generated random key is used .  The operation may fail d ue to lack of entropy.  5 
5. If the key has been configured on all the packages, s et TDR.LIFECYCLE_STATE  to TD_KEYS_CONFIGURED . 
Table 5.156:  TDH.MNG.KEY.CONFIG  Completion Status Codes (Returned in RAX) Definition  
TDX_KEY_CONFIGURED   
TDX_KEY_GENERATION_FAILED  Failed to generate a random key.  This is typically caused by 
an entropy error of the CPU's random number generator, 
and may be impacted by RDSEED, RDRAND or PCONFIG 
executing on other LPs.  The operation should be retried.  
TDX_ LIFECYCLE_STATE _INCORRECT   
Specifically, key configuration may fail due to a concurrently 
running PCONFIG instruction.  
TDX_SUCCESS  TDH.MNG.KEY.CONFIG  is successful . 
 
November 2023  . Page 192 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.39.  TDH.MNG.KEY.FREEID Leaf  
End the platform cache flush sequence and  mark applicable HKIDs in KOT as free.  
Table 5.157:  TDH.MNG.KEY.FREEID In put Operands Definition  
Must be 0  
 
Table 5.158:  TDH.MNG.KEY.FREEID Out put Operands Definition  5 
 
vary.  
TDH.MNG.KEY.FREEID ends the platform cache flush sequence for the HKIDs associated with the specified TD after 10 
TDH.PHYMEM.CACHE.WB has been executed on all the required WBINVD domains .  It marks the TD’s HKIDs in KOT as 
free, and the TD itself as being torn down.  
Table 5.159:  TDH.MNG.KEY.FREEID Operands Information Definition  15 
Explicit/  
1GB  
 
In addition to the memory operand checks per the table above, the function checks the following conditions:  
2. TLB and VMCS caches associated with the HKID have been flushed, and no memory associated with this HKID may 
be accessed:  20 
2.1. TDR.LIFECYCLE_STATE is TD_BLOCKED.  
2.2. The KOT entry for the TD’s private HKID is marked as HKID_ FLUSHED . 
2.3. The KOT entry for the TD’s private HKID indicates that TDH.PHYMEM.CACHE.WB has been executed on all

Explicit/  
1GB  
 
2.3. The KOT entry for the TD’s private HKID indicates that TDH.PHYMEM.CACHE.WB has been executed on all 
applicable packages or cores.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 193 of 329 
3. Mark the KOT entry as HKID_ FREE.  
4. Set TDR.LIFECYCLE_STATE  to TD_TEARDOWN.  
Table 5.160:  TDH.MNG.KEY.FREEID Completion Status Codes (Returned in RAX) Definition  5 
TDX_SUCCESS  TDH.MNG.KEY.FREEID is successful.  
TDX_WBCACHE_NOT_COMPLETE   
November 2023  . Page 194 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.40.  TDH.MNG.KEY.RECLAIMID Leaf  (Deprecated)  
This function is deprecated; it is provided for backward compatibility.  
Table 5.161:  TDH.MNG.KEY.RECLAIMID In put Operands Definition  
Must be 0  
 
Table 5.162:  TDH.MNG.KEY.RECLAIMID Out put Operands Definition  5 
 
vary.  
TDH.MNG.KEY.RECLAIMID  is provided for backward compatibility.  It does not do anything except returning a constant 10 
TDX_SUCCESS status.  
Table 5.163:  TDH.MNG.KEY.RECLAIMID Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MNG.KEY.RECLAIMID is successful.  
November 2023  . Page 195 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.41.  TDH.MNG.RD  Leaf  
Read a TD -scope metadata field ( control structure field ) of a TD.  
Table 5.164:  TDH.MNG.RD  Input Operands  Definition  
Version number m ay be 0 or 1 .  See the enumeration details below.  
RDX  Field identifier  – see 3.10  
The LAST_ELEMENT_IN_FIELD and LAST_FIELD_IN_SEQUENCE components of the field identifier 
must be 0.  
WRITE_MASK_VALID, INC_SIZE, CONTEXT_CODE and ELEMENT_SIZE_CODE  components of the field 
identifier are ignored.  
For TDH.MNG.RD version 1 or higher, a value of -1 is a special case:  it is not a valid field identifier; 
in this case the first readable field identifier is returned in RDX.  
 
Table 5.165:  TDH.MNG.RD  Output Operands Definition  5 
RDX  For TDH.MNG.RD version 0, RDX is unmodified.  
For TDH.MNG.RD version 1 or higher:  
• If the input field identifier was -1, RDX returns the first readable field identifier.  
Else, in  case of an error, RDX returns -1.  On success, RDX returns the next readable field identifier.  
A value of -1 indicates no next field identifier is available.  
R8 Contents of the field  
In case of no success , as indicated by RAX, R8 returns 0.  
 
vary.  
TDH.MNG.RD  reads  a TD -scope metadata field ( control structure field ) of a TD.  10 
Enumeration:  Availability of TDH. MNG.RD version 1 is enumerated by TDX_FEATURES0.ENHANCED_METADATA (bit 
3), readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.MNG.RD with a version number 
higher than 0 returns a TDX_OPERAND_INVALID(RAX) status.  
If version 1 or higher is specified in RAX, RDX returns the next host -side readable field identifier.  This may be used by the 
host VMM to dump the host readable TD metadata.  To read all the available fields, the host VMM can invoke 15  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 196 of 329 
Intel TDX Application Binary Interface (ABI) Reference  TDH.MNG.RD in a loop, starting with field identifier -1 as an input, until RDX returns -1.  A status code of 
TDX_METADATA_FIELD_SKIP indicates that the returned value is not applicable.  
Table 5.166:  TDH.MNG.RD  Operands Information Definition  5 
Explicit/  
1GB  
 
In addition to the memory operand checks per the table above, the function checks the following  conditions : 
3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED ). 10 
4. All the required TDCS pages have been added ( TDR.NUM_TDCX is the required number ). 
If the above checks pass ed: 
5. Read the control structure field using the algorithm described in 5.2.2.1 . 
Table 5.167:  TDH.MNG.RD  Completion Status Codes (Returned in RAX) Definition  15 
TDX_METADATA_FIELD_ID_INCORRECT   
TDX_METADATA_FIELD_NOT_READABLE   
TDX_METADATA_FIELD_SKIP  Indicates that the field value being read is not applicable 
and needs to be skipped.  If called in a loop, use RDX as the 
identifier of the next field to be read, if any.  
TDX_METADATA_FIRST_FIELD_ID_IN_CONTEXT  Indicates that the first field ID in context is returned  
TDX_SUCCESS  TDH.MNG.RD is successful.  
November 2023  . Page 197 of 329 
November 2023  . Page 198 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.42.  TDH.MNG.VPFLUSHDONE Leaf  
Check  that none of the TD’s VCPUs are associated with an LP.  
Table 5.168:  TDH.MNG.VPFLUSHDONE In put Operands Definition  
Must be 0  
 
Table 5.169:  TDH.MNG.VPFLUSHDONE  Output Operands Definition  5 
 
vary.  
TDH.MNG.VPFLUSHDONE  checks  that none of the TD’s VCPUs are associated with an LP, and it then prepares for cache 10 
flushing by TDH.PHYMEM.CACHE.WB . 
Table 5.170:  TDH.MNG.VPFLUSHDONE Operands Information  
Explicit/  
1GB  
Explicit  RCX HPA  TDR page  TDR  RW Opaque  4KB Exclusive  Shared  Shared

vary.  
Explicit/  
1GB  
Implicit  N/A N/A TDCS structure  TDCS  R Opaque  N/A Exclusive(i)  N/A N/A 
Implicit  N/A N/A TDCS.OP_STATE  OP_STATE  None  Opaque  N/A Exclusive(i)  N/A N/A 
 15 
2. TDR.LIFECYCLE_STATE is either TD_HKID_ASSIGNED or TD_KEYS_CONFIGURED.  
3. The KOT entry for the TD’s assigned HKID in the list must be marked as HKID_ ASSIGNED . 
4. None of the TD’s VCPUs are associated with an LP (either the TD has not been initialized by TDH.MNG.INIT, or 20 
TDCS.NUM_ASSOC_VCPUS is 0).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 199 of 329 
5. Set a bitmap in the KOT entry to track the required subsequent TDH.PHYMEM.CACHE.WB  operations.  
6. Set TD R.LIFECYCLE_STATE to TD_BLOCKED.  
7. Mark the KOT entry as HKID_FLUSHED.  
Table 5.171:  TDH.MNG.VPFLUSHDONE Completion Status Codes (Returned in RAX) Definition  
TDX_FLUSHVP_NOT_DONE   
TDX _LIFECYCLE_STATE _INCORRECT   
TDX_SUCCESS  TDH.MNG.VPFLUSHDONE is successful.  
 
November 2023  . Page 200 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.43.  TDH.MNG.WR  Leaf  
Write a TD -scope metadata field ( control structure field ) of a TD.  
Table 5.172:  TDH.MNG.WR  Input Operands  Definitions  
Must be 0  
RDX  Field identifier – see 3.10  
must be 0.  
R8 Data to write to the field  
R9 A 64b write mask to indicate which bits of the value in R8 are to be written to the field  
 
Table 5.173:  TDH.MNG.WR  Output Operands Definition  5 
R8 Previous content of the field  
In case of an error, as indicated by RAX, R8 returns 0.  
 
vary.  
TDH.MNG.WR  writes a TD -scope metadata field ( control structure field ) of a TD.   The value (R8) is  written as specified by 10 
the write mask (R9).  Writing is subject to the field’s internal write mask (per the TD’s ATTRIBUTES.DEBUG bit).  Writing 
of specific fields is also subject to additional rules.  
Table 5.174:  Metadata Field Write Rules  
Write Mask Bit in R9  Internal Write Mask Bit  Value Bit in R8  
0 N/A Silently ignored  
1 0 Must be the same as the current field’s bit  
1 1 Written to the current field’s bit  
of the Intel TDX Module API . 15  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 201 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.175:  TDH.MNG.WR  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDR page  TDR  RW Opaque  4KB Shared  Shared  Shared  
 
1. The TDR page metadata in PAMT must be correct (PT must be PT_TDR)  
2. The TD is not in a FATAL state (TDR.FATAL is FALSE)  5 
3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED ) 
4. All the required TDCS pages have been added (TDR.NUM_TDCX is the required number).  
5. Write the control structure field and return its old value, using the algorithm described in 5.2.2.2 . 
Table 5.176:  TDH.MNG.WR  Completion Status Codes (Returned in RAX) Definition  
TDX_METADATA_FIELD_NOT_WRITABLE   
TDX_METADATA_FIELD_VALUE_NOT_VALID   
TDX_METADATA_WR_MASK_NOT_VALID   
TDX_SUCCESS  TDH.MNG.WR is successful.  
TDX_TD_NON_DEBUG   
November 2023  . Page 202 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.44.  TDH.MR.EXTEND Leaf  
Extend the MRTD measurement register in the TDCS with the measurement of the indicated chunk of a TD page . 
Table 5.177:  TDH.MR.EXTEND In put Operands Definition  
Must be 0  
RCX The GPA  of the TD page chunk to be measured  
RDX  The physical address of the  TDR page of the target TD  (HKID bits must be 0)  
 
Table 5.178:  TDH.MR.EXTEND Out put Operands Definition  5 
 
vary.  
TDH.MR.EXTEND u pdates the MRTD measurement register in the TDCS with the measurement of the indicated chunk of 10 
a TD private page.   For pages  whose contents need to be measured , once the page is copied into the TD memory area, 
the host VMM will call TDH.MR.EXTEND multiple times  to measure the pages contents into MRTD.   TDEXEND can be 
executed only before TDH.MR.FINALIZE . 
Note:  TDH.MR.EXTEND works on a 256B chunk of a page, not on a full page, due to instruction latency considerations.  
November 2023  . Page 203 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.179:  TDH.MR.EXTEND Operands Information Definition  
Explicit/  
1GB  
chunk  Blob  R Private  256B  None  None  None  
Explicit  RDX  HPA  TDR page  TDR  R Opaque  4KB Exclusive  Shared  Shared  
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  4KB Exclusive(i)  N/A N/A 
Implicit  N/A GPA  Secure EPT tree  N/A R Private  N/A Exclusive(i)  N/A N/A 
entry  SEPT 
Entry  RW Private  N/A Exclusive (i) N/A N/A 
 
In addition to the memory operand checks per the table above, the function checks the following:  
2. The TD is not in a FATAL state (TDR.FATAL is FALSE).  5

Explicit/  
1GB  
entry  SEPT 
 
4. The TD must have been initialized but not finalized ( TDR.NUM_TDCX is the required number  and TDCS.OP_STATE is 
5. The page must be mapped and accessible in the Secure EPT.  
6. Update the TD measurement in TDCS based on the chunk’s GPA and contents.  
7. Extend TDCS.MRTD with the chunk’s GPA and contents.  Extension is done using SHA384, with three 128B extension 
buffers.  The first extension buffer is composed as follows:  
o Bytes 0 through 8 contain the ASCII string “MR.EXTEND”.  
o Bytes 16 through 23 contain the GPA (in little -endian format).  15 
The other two extension buffers contain the chunk’s contents.  
Table 5.180:  TDH.MR.EXTEND Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MR.EXTEND  is successful . 
TDX_SYS_NOT_READY    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 204 of 329 
 
November 2023  . Page 205 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.45.  TDH.MR.FINALIZE Leaf  
TDH.MR.FINALIZE completes measurement of the initial TD contents and mark s the TD as ready to run.  
Table 5.181:  TDH.MR.FINALIZE In put Operands Definition  
Must be 0  
 
Table 5.182:  TDH.MR.FINALIZE Out put Operands Definition  5 
 
vary.  
TDH.MR.FINALIZE completes the measurement of the initial TD contents and mark s the TD as finalized.  10 
Table 5.183:  TDH.MR.FINALIZE Operands Information Definition  
Explicit/  
1GB  
 
INITIALIZED ). 20  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 206 of 329 
5. Finalize the TD measurement , i.e., SHA384 calculation of TDCS.MRTD that has been accumulated so far by 
TDH.MEM.PAGE.ADD and TDH.MR.EXTEND.  
6. Calculate TDCS.SERVTD_HASH:  
6.1. Get all service TD binding slots whose SERVTD_BINDING_STATE is not NOT_BOUND.  5 
6.1.1.  If no service TD binding slots apply, set TDCS.SERVTD_HASH to 0.  
6.2. Sort in ascending order by SERVTD_TYPE as the primary key, SERVTD_INFO_HASH as a secondary key (if multiple 
service TDs of the same type are bound).  
6.3. Concatenate SERVTD_INFO_HASH, SERVTD_TYPE and SERVTD_ATTR of each slot  in a temporary buffer:  
6.3.1.  SERVTD_INFO_HASH in bytes 5:0  10 
6.3.2.  SERVTD_TYPE in bytes 7:6  
6.3.3.  SERVTD_ATTR in bytes 15:8  
6.3.4.  Concatenate  all buffers . 
6.3.5.  Calculate SHA384  and store in TDCS.SERVTD_HASH.  
7. Mark  the TD as finalized.  15 
Table 5.184:  TDH.MR.FINALIZE Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.MR.FINALIZE  is successful . 
November 2023  . Page 207 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.46.  TDH.PHYMEM.CACHE.WB Leaf  
TDH.PHYMEM.CACHE.WB is an interruptible and res umable  function to write back the cache hierarchy on a package or a 
core.  
Table 5.185:  TDH.PHYMEM.CACHE.WB In put Operands Definition  
Must be 0  
RCX Command, as described below:  
 0 WB_START_CMD  Start a new TDH.PHYMEM.CACHE.WB  cycle  with no cache 
invalidation.  
 1 WB_RESUME_CMD  Resume a previously interrupted  TDH.PHYMEM.CACHE.WB  cycle  
with no cache invalidation.  
Other   Reserved  
 5 
Table 5.186:  TDH.PHYMEM.CACHE.WB Out put Operands Definition  
 
vary.  10 
TDH.PHYMEM.CACHE.WB writes back the cache hierarchy to memory and updates the KOT state to allow reuse of HKIDs.  
Interruptibility:  TDH.PHYMEM.CACHE.WB is interruptible.  If a pending interrupt is detected during operation, 
TDH.PHYMEM.CACHE.WB returns with a TDX_INTERRUP TED_RESUMABLE status in RAX.  
 The hosts VMM initially calls TDH.PHYMEM.CACHE.WB with RCX indicating WB_START_CMD.  If 
TDH.PHYMEM.CACHE.WB returns TDX_INTERRUPTED_RESUMABLE (or any other recoverable error) 15 
status in RAX, the host VMM should call TDH.PHYMEM.CACHE.WB with RCX indicating 
WB_RESUME_CMD in a loop until it completes its operation, as indicated by TDX_SUCCESS status.  
Warning:  When TDH.PHYMEM.CACHE.WB is interrupted, the CPU still considers this as a cache write -back 
operation in progress.  The host VMM should complete the cache write -back operation by resuming 
TDH.PHYMEM.CACHE.WB (i.e., with RCX indicating WB_RESUME_CMD) until completed successfully.  20 
Failure to do so will result in memory performance impact that would only be resolved by a restart.   
The host VMM should also refrain from executing WBINVD or WBNOINVD while the 
TDH.PHYMEM.CACHE.WB cycle is in progress.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 208 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Other TDH.PHYMEM.CACHE.WB characteristics:  
• TDH.PHYMEM.CACHE.WB does not invalidate cache lines.  
• The function operates on cache lines associated with any HKID.  
• The function is designed to  ensure  write back of at least those cache lines where the state of that HKID (in the KOT) 
was HKID_FLUSHED at the time of the first invocation (RCX == WB_START_CMD).  5 
• Depending on the implementation, the instruction may write back additional cache lines.  
• The scope at which TDH.PHYMEM.CACHE.WB operates (e.g., package or core) is determined at Intel TDX module 
initialization time . 
Table 5.187:  TDH.PHYMEM.CACHE.WB (Implicit) Operands Information  
Explicit/

Explicit/  
1GB  
Implicit  N/A N/A KOT  KOT  N/A Hidden  N/A Shared  N/A N/A 
Implicit  N/A N/A WBT entry for 
current scope  WBT_ENTRY  N/A Hidden  N/A Exclusive  N/A N/A 
 
1. The command value is one of the supported ones.  
2. If the command is to start a new TDH.PHYMEM.CACHE.WB cycle (RCX == 0), then:  15 
2.1. Clear the internally saved interruption state.  
2.2. Scan the KOT:  mark those HKIDs whose state is HKID_FLUSHED in an internal table; only those HKIDs will be 
later marked as written back upon successful completion of TDH.PHYMEM.CACHE.WB.  
2.3. If none of the KOT entries for the requested set of HKIDs (either single or all) is in HKID_FLUSHED state, then 
abort with an informational code (it achieved its goal: write back and invalidate at least the HKIDs that are in 20 
the HKID_FLUSHED state).  
3. Run cache write back operation on the cache hierarchy of the current WBINVD domain .  This operation is long and 
may be interrupted by external events.  
3.1. If a previous TDH.PHYMEM.CACHE.WB has been interrupted, the operation resumes from the interruption 
point which has been recorded.  25 
3.2. In case of interruption, the current point in the write back and invalidation flow and the current HKID are 
recorded.  
4. If the operation has not been interrupted, update the KOT as follows:  
4.1. For each KOT entry, if the entry was marked as HKID_FLUSHED at the start of the TDH.PHYMEM.CACHE.WB 
cycle as discussed above, use the KOT entry’s bitmap to indicate that TDH.PHYMEM.CACHE.WB has been 30 
executed on this package or core.  
Error and Informational Codes  
Table 5.188:  TDH.PHYMEM.CACHE.WB Completion Status Codes (Returned in RAX) Definition  
TDX_INTERRUPTED_RESUMABLE  TDH.PHYMEM.CACHE.WB was interrupted; it is 
recommended to resume it with RCX indicating 
WB_RESUME_CMD  
TDX_NO_HKID_READY_TO_WBCACHE   
November 2023  . Page 209 of 329 
TDX_SUCCESS  TDH.PHYMEM.CACHE.WB  is successful . 
November 2023  . Page 210 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.47.  TDH.PHYMEM.PAGE.RDMD  Leaf  
Read the metadata of a page (or the metadata of the  containing large page) in TDMR.  
Table 5.189:  TDH.PHYMEM.PAGE.RDMD Operands  
Must be 0  
RCX A physical address of a 4KB page in TDMR  (HKID bits must be 0)  
 
Table 5.190:  TDH.PHYMEM.PAGE.RDMD Out put Operands Definition  5 
RCX Page Type (PT) – see 3.5.1  
In case of an error, RCX returns 0.  
RDX  For most PT values, this field returns the HPA of the TD’s TDR control structure page, if applicable 
(HKID bits are set to 0).  
In multiple error cases, as indicated by RAX, RDX returns 0.  In other error cases, RDX still returns 
the OWNER information.  See the completion status codes table below for details.  
R8 Bits Name  Description  
2:0 Size Size of the containing 4KB, 2MB or 1GB page  
63:3  Reserved  Set to 0  
R9 BEPOCH  
In case of an error, as indicated by RAX, R9 returns 0.  
R10 Reserved:  set to 0  
R11 Reserved:  set to 0  
 
vary.  
TDH.PHYMEM.PAGE.RDMD finds the containing page (4KB, 2MB or 2GB) of the given page in TDMR and reads its 10 
metadata from its PAMT entry.  
November 2023  . Page 211 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.191:  TDH.PHYMEM.PAGE.RDMD  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  Target 
page  Blob  None  Opaque / 
Private  4KB Shared  Shared  Shared  
 
If the memory operand checks, per the table above, pass , the function does  the following:  
1. Do a PAMT walk and  find the containing page and its size.  
If passed:  5 
2. Read the PAMT entry.  
Table 5.192:  TDH.PHYMEM.PAGE.RDMD  Completion Status Codes (Returned in RAX) Definition  
TDX_OPERAND_BUSY  Operation encountered a busy operand, indicated by the lower 32 
bits of the status.  In many cases, this can be resolved by retrying the 
TDX_SUCCESS  TDH.PHYMEM.PAGE.RDMD  is successful . 
November 2023  . Page 212 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.48.  TDH.PHYMEM.PAGE.RECLAIM Leaf  
Reclaim a physical 4KB, 2MB or 1GB TD -owned page (i.e., TD private page, Secure EPT page or a control structure page) 
from a TD, given its HPA.  
Table 5.193:  TDH.PHYMEM.PAGE.RECLAIM In put Operands Definition  
Must be 0  
RCX PAGE  The physical address of a 4KB, 2MB or 1GB page to be reclaimed (HKID bits must be 0)  
 5 
Table 5.194:  TDH.PHYMEM.PAGE.RECLAIM Out put Operands Definition  
RAX  STATUS  SEAMCALL instruction return code – see 5.3.1  
RCX PT Page Type (PT) – see 3.5.1  
In multiple error cases, as indicated by RAX, RCX returns 0.  In other error cases, RCX 
still returns the PT information.  See the completion status codes table below for 
details.  
RDX  OWNER  For most PT values, t his field returns the  HPA of the TD’s TDR control structure page , if 
applicable  (HKID bits are set to 0) . 
In multiple error cases , as indicated by RAX, RDX returns 0.  In other error cases, RDX 
still returns the OWNER information.  See the completion status codes table below for 
details.  
R8 SIZE  Bits Name  Description  
2:0 Size Size of the containing 4KB, 2MB or 1GB page – see 3.5.1  
still returns the size information.  See the completion status codes table below for 
details.  
R9  Reserved:  set to 0  
R10  Reserved:  set to 0  
R11  Reserved:  set to 0  
 
vary.  10  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 213 of 329 
Intel TDX Application Binary Interface (ABI) Reference  TDH.PHYMEM.PAGE.RECLAIM  reclaims a TD -owned physical page from the TD.  
TDH.PHYMEM.PAGE.RECLAIM can reclaim pages only if the owner TD is in the TD_TEARDOWN state.  
Cache Flush and Init  After the physical page has been reclaimed, the host VMM should flush its cache lines (required 
only for TDR pages) and initialize its content before it is reused, as described in the [Base Spec].  
To understand the table and text below, please refer to the [ TDX Module Base Spec ] chapter discussing general aspects 5 
Table 5.195:  TDH.PHYMEM.PAGE.RECLAIM Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  Target page  Blob  RW Opaque/ 
Private  4KB, 
2MB 
or 
1GB  Exclusive  Shared  Shared  
Implicit  N/A N/A TDR page8 TDR  RW Opaque  4KB Shared  N/A N/A

Explicit/  
1GB  
2MB 
or 
Implicit  N/A N/A TDR page8 TDR  RW Opaque  4KB Shared  N/A N/A 
 
TDH.PHYMEM.PAGE.RECLAIM checks the memory operands per the table above when applicable during its flow.  The 
text below does not explicitly mention those checks, except when necessary.  10 
The function works as follows:  
1. Check  that the target page metadata in PAMT are correct (PT must not be PT_NDA nor PT_RSVD).  
2. If the target page is not a TDR (PT is not PT_TDR):  
2.1. Get the TDR page (pointed by the target page’s PAMT.OWNER).  
2.2. Check  that the TD is in teardown state (TDR. LIFECYCLE_STATE  is TD_TEARDOWN).  15 
2.3. Atomically decrement TDR.CHLDCNT by 1, 512 or 5122 depending on the removed page size (4KB, 2MB or 1GB, 
respectively) . 
3. Else (target page is a TDR):  
3.1. Check  that the TD is in teardown state (TDR. LIFECYCLE_STATE  is TD_TEARDOWN).  
3.2. Check  that TDR.CHLDCNT is 0.  20 
If passed:  
4. Update  the PAMT entry of the reclaimed page to PT_NDA.  
5. Return the page metadata (as they  were  before PAMT update above).  
Table 5.196:  TDH.PHYMEM.PAGE.RECLAIM Completion Status Codes (Returned in RAX) Definition  25 
Completion Status  Code  Description  
TDX_LIFECYCLE_STATE_INCORRECT  RCX, RDX and R9 return the actual PT, OWNER and SIZE 
If the page is not a TDR page but the owner TDR is busy, 
then RCX, RDX and R9 return the actual PT, OWNER and SIZE 
 
8 Except when TDR is the target page   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 214 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Completion Status  Code  Description  
TDX_OPERAND_INVALID  If the page physical address is not aligned on its size, then 
RCX, RDX and R9 return the actual PT, OWNER and SIZE 
TDX_SUCCESS  TDH.PHYMEM.PAGE.RECLAIM  is successful . 
TDX_TD_ASSOCIATED_PAGES_EXIST  RCX, RDX and R9 return the actual PT, OWNER and SIZE 
November 2023  . Page 215 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.49.  TDH.PHYMEM.PAGE.WBINVD Leaf  
Write back and invalidate all  cache lines associated with the specified memory page and HKID.  
Table 5.197:  TDH.PHYMEM.PAGE.WBINVD In put Operands Definition  
Must be 0  
RCX Physical address (including HKID bits) of a 4KB page in TDMR   
 
Table 5.198:  TDH.PHYMEM.PAGE.WBINVD Out put Operands Definition  5 
 
vary.  
TDH.PHYMEM.PAGE.WBINVD performs cache write back and invalidation on all the cache lines associated with the 10 
specified page and HKID.  The page must not be in use by the Intel TDX module (i.e., not assigned to a TD as a private 
page or a Secure EPT page), nor used as a control structure page.  
It is the responsibility of the host VMM to track which HKID is associated with the target page; the function does not 
check  it. 
Table 5.199:  TDH.PHYMEM.PAGE.WBINVD Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  Target page  Blob  R Private/  
Opaque  4KB Shared  Shared  Shared  
 
1. The target page must be marked in PAMT as not controlled by the Intel TDX module (PT must be PT_NDA).  20 
If successful, the function performs the following:  
2. Write back and invalidate all the cache lines for the given target HPA and HKID.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 216 of 329 
Table 5.200:  TDH.PHYMEM.PAGE.WBINVD Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.PHYMEM.PAGE.WBINVD  is successful . 
November 2023  . Page 217 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.50.  TDH.SERVTD.BIND Leaf  
Bind a service TD to a  target TD . 
Table 5.201:  TDH.SERVTD.BIND Input Operands  Definition  
Must be 0  
RCX The physical address of the target TD’s  TDR page  (HKID bits must be 0)  
RDX The physical address of the service TD’s TDR page  (HKID bits must be 0)  
R8 Index (slot number) in the target TD’s service TD binding table  
R9 SERVTD_TYPE:  Service TD type  
R10 SERVTD_ATTR:  Service TD attributes  
 
Table 5.202:  TDH.SERVTD.BIND Output Operands Definition  5 
RCX Binding handle  
In case of an error, as indicated by RAX, RCX returns 0.  
R10 TD_UUID bits 63:0  
In case of an error, as indicated by RAX, R10 returns 0.  
R11 TD_UUID bits 127:64  
In case of an error, as indicated by RAX, R11 returns 0.  
R12 TD_UUID bits 19 1:128  
In case of an error, as indicated by RAX, R12 returns 0.  
R13 TD_UUID bits 255:19 2 
In case of an error, as indicated by RAX, R13 returns 0.  
AVX, AVX2 
and 
AVX512 
 
vary.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 218 of 329 
Intel TDX Application Binary Interface (ABI) Reference  TDH.SERVTD.BIND binds a service TD to a target TD.  
Enumeration:  Availability of TDH. SERVTD.BIND is enumerated by TDX_FEATURES0.SERVICE_TD (bit 2), readable 
by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TD H.SERVTD.BIND returns a 
Table 5.203:  TDH.SERVTD.BIND  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  Target TD’s TDR 
page  TDR  R Opaque  4KB Shared  Shared  Shared  
Explicit  RDX  HPA  Service TD’s TDR 
Implicit  N/A N/A Target TD’s TDCS 
structure  TDCS  RW Opaque  N/A Shared (i) N/A N/A 
Implicit  N/A N/A Target TD’s 
TDCS.OP_STATE  OP_STATE  RW Opaque  N/A Shared  N/A N/A 
Implicit  N/A N/A Binding table   RW Opaque  N/A Exclusive  None  None  
Implicit  N/A N/A Service TD’s 
TDCS structure  TDCS  RW Opaque  N/A Shared (i) N/A N/A 
TDCS.OP_STATE  OP_STATE  R Opaque  N/A Shared  N/A N/A 
TDCS.RTMR  SHA384_  
HASH  N/A Opaque  N/A Shared  N/A N/A 
 
1. Target TD checks:  10 
1.1. The target TD’s TDR page metadata in PAMT must be correct ( PT must be PT_TD R). 
1.2. The target TD is not in a FATAL state (TDR.FATAL is FALSE).  
1.3. The target TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED).  
1.4. The target TD ’s TDCS pages must have been allocated (TDR.NUM_TDCX is the required number) . 
1.5. The target TD has not been paused for export and is not in the in -order import phase.  15 
2. Service TD checks:

2. Service TD checks:  
2.1. The service TD’s TDR HPA must be different than the target TD’s TDR HPA  
2.2. The service TD’s TDR page metadata in PAMT must be correct ( PT must be PT_TD R). 
2.3. The service TD is not in a FATAL state (TDR.FATAL is FALSE).  
2.4. The service TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED).  20 
2.5. The service TD’s TDCS pages must have been allocated (TDR.NUM_TDCX is the required number) . 
2.6. Either the  service TD’s measurements have been finalized  (by TDH.MR.FINALIZE ) or it is being imported and 
import is in the out -of-order phase.  
3. Binding slot number does not exceed the number of available slots.  
4. SERVTD_TYPE is supported.  25 
5. If only one service TD binding instance is supported by SERVTD_TYPE, no other binding slot whose BINDIND_STATE 
is not NOT_BOUND  may have the same SERVTD_TYPE.  
6. SERVTD_ATTR is supported.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 219 of 329 
Intel TDX Application Binary Interface (ABI) Reference  If the above checks pass ed: 
7. If the binding slot’s SERVTD_BINDING_STATE  is NOT_BOUND  (i.e., this is an initial binding ): 
7.1. Check that the target TD’s measurements have not  been  finalized  (by TDH.MR.FINALIZE ). 
7.2. Copy the provided SERVTD_TYPE and SERVTD_ATTR to the binding slot.  
7.3. Calculate the service TD’s SERVTD_INFO_HASH  and write to the binding slot’s SERVTD_INFO_HASH . 5 
7.4. Copy the SERVTD’s TD_UUID to the binding slot’s SERVTD_UUID.  
8. Else, if the binding slot’s SERVTD_BINDING_STATE  is PRE_BOUND (i.e., this is a late initial binding ): 
8.1. Check that the requested SERVTD_ TYPE  is equal to the binding slot’s SERVTD_ TYPE . 
8.2. Check that the requested SERVTD_ATTR is equal to the binding slot’s SERVTD_ATTR.  
8.3. Calculate the service TD’s SERVTD_INFO_HASH  and check that it is equal to the binding slot’s 10 
SERVTD_INFO_HASH . 
8.4. Copy the SERVTD’s TD_UUID to the binding slot’s SERVTD_UUID.  
9. Else, if the binding slot’s SERVTD_BINDING_STATE  is BOUND (i.e., this is a rebinding ): 
9.1. Check that the requested SERVTD_TYPE is equal to the binding slot’s SERVTD_TYPE.  
9.2. Check that the requested SERVTD_ATTR is equal to the binding slot’s SERVTD_ATTR.  15 
9.3. Calculate the service TD’s SERVTD_INFO_HASH . 
9.4. Check that the service TD’s SERVTD_INFO_HASH is equal to the binding slot’s SERVTD_INFO_HASH.  
9.5. If SERVTD_A TTR.INSTANCE_BINDING is set:  
9.5.1.  Check that the SERVTD’s TD_UUID is equal to the binding slot’s SERVTD_UUID.  
9.6. Else:  20 
9.6.1.  Copy the SERVTD’s TD_UUID to the binding slot’s SERVTD_UUID.  
If passed:  
10. Set the binding slot’s SERVTD_BINDING_STATE  to BOUND.  
11. Calculate and return the binding handle.  
Completion Status Codes  25 
Table 5.204:  TDH.SERVTD.BIND Completion Status Codes (Returned in RAX) Definition  
TDX_SERVTD_ATTR_MISMATCH   
TDX_SERVTD_INFO_HASH_MISMATCH   
TDX_SERVTD_TYPE_MISMATCH   
TDX_SERVTD_UUID_MISMATCH   
TDX_SUCCESS  TDH.SERVTD.BIND  is successful . 
November 2023  . Page 220 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.51.   TDH.SERVTD.PREBIND Leaf  
Pre-bind a service TD to a  target TD . 
Table 5.205:  TDH.SERVTD.PREBIND Input Operands  Definition  
Must be 0  
RDX  The physical address (including HKID bits) of SERVTD_INFO_HASH, the expected SHA384 hash of 
the service TD’s TDINFO_STRUCT  
R9 SERVTD_TYPE:  Expected service TD type  
R10 SERVTD_ATTR:  Expected service TD attributes  
 
Table 5.206:  TDH.SERVTD.PREBIND Output Operands Definition  5 
 
vary.  
TDH.SERVTD.PREBIND pre -binds a service TD to a target TD, by setting its expected binding parameters.  10 
Enumeration:  Availability of TDH. SERVTD.PREBIND is enumerated by TDX_FEATURES0.SERVICE_TD (bit 2), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TD H.SERVTD.PREBIND returns a 
Table 5.207:  TDH.SERVTD.PREBIND  Operands Information Definition  
Explicit/  
1GB  
page  TDR  R Opaque  4KB Shared  Shared  Shared   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 221 of 329 
1GB  
Explicit  RDX  HPA  SERVTD_INFO_  
HASH  SHA384_  
HASH  R Shared  64B N/A N/A N/A 
 
1. The target TD’s TDR page metadata in PAMT must be correct ( PT must be PT_TD R). 
2. The target TD is not in a FATAL state (TDR.FATAL is FALSE).  
3. The target TD keys are configured on the hardware (TDR. LIFECYCLE_STATE is TD_KEYS_CONFIGURED).  5 
4. The target TD’s TDCS pages must have been allocated (TDR.NUM_TDCX is the required number) . 
5. The target TD’s measurements have not been finalized  (by TDH.MR.FINALIZE ). 
6. Binding slot number does not exceed the number of available slots.  
7. SERVTD_TYPE is supported.  
8. If only one service TD binding instance is supported by SERVTD_TYPE, no other binding slot whose BINDIND_STATE 10 
is not NOT_BOUND may have the same SERVTD_TYPE.  
9. SERVTD_ATTR is supported.  
10. The binding slot’s SERVTD_BINDING_STATE is either NOT_BOUND or PRE_BOUND.  
11. Copy the provided SERVTD_TYPE, SERVTD_ATTR and SERVTD_INFO_HASH to the binding slot.  15 
12. Set the binding slot’s SERVTD_BINDING_STATE to PRE_BOUND.  
Table 5.208:  TDH.SERVTD.PREBIND Completion Status Codes (Returned in RAX) Definition  
TDX_SERVTD_ALREADY_BOUND_FOR_TYPE   
TDX_SUCCESS  TDH.SERVTD.PREBIND  is successful . 
November 2023  . Page 222 of 329 
November 2023  . Page 223 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.52.  TDH.SYS.CONFIG Leaf  
Globally configure  the Intel TDX module . 
Table 5.209:  TDH.SYS.CONFIG In put Operands Definition  
Must be 0  
RCX The physical address of an array of pointers, each containing the physical address of a single 
TDMR_INFO entry (see 3.3.3 ). 
The pointer array must be sorted such that TDMR base addresses (TDMR_INFO.TDMR_BASE) are

Must be 0  
The pointer array must be sorted such that TDMR base addresses (TDMR_INFO.TDMR_BASE) are 
sorted from the lowest to the highest base address, and TDMRs do not overlap with each other.  
RDX  The number of pointers in the above buffer, between 1 and 64  
15:0  HKID  Intel TDX global private HKID value  
 
Table 5.210:  TDH.SYS.CONFIG Out put Operands Definition  5 
 
vary.  
TDH.SYS.CONFIG  performs global (platform -scope) configuration  of the Intel TDX module .  This function is intended to be 10 
executed during OS/VMM boot, and thus it has relaxed latency requirements.  
Table 5.211:  TDH.SYS.CONFIG Operands Information Definition  
Explicit/  
Type  Resource  Resource Type  Access  Access 
1GB  
Explicit  RCX HPA  TDMR Info 
Pointers  Array of HPA  R Shared  512B  None  N/A N/A 
Explicit  N/A HPA  TDMR Info  TDMR_INFO  R Shared  512B  None  N/A N/A  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 224 of 329 
1GB  
Implicit  N/A N/A All Intel TDX 
module 
internal 
variables  N/A RW Hidden  N/A Exclusive  N/A N/A 
 
1. Global and LP -scope initialization has been done:  
1.1. PL.SYS_STATE is SYSINIT_DONE.  
1.2. TDH.SYS.LP.INIT has been executed on all LPs.  5 
2. The number of TDMR_INFO entries is at least 1 and does  not exceed the supported number of TDMRs.  
3. Check each physical address of to TDMR_INFO; read the applicable TDMR_INFO entry; check and update the internal 
TDMR_TABLE with TDMR, reserved areas and PAMT setup.  The order of checks is not required to be exactly the 
same as described below.  
o TDMRs must be sorted in an ascending base address order.  10 
o For each TDMR:  
• TDMR base address must be aligned on 1GB.  
• TDMR size must be greater than 0 and a whole multiple of 1GB.  
• Any address within the TDMR must comply with the platform’s maximum PA, and its HKID bits must be 0 . 
• For each PAMT region (1G, 2M and 4K) of each TDMR:  15 
▪ PAMT base address must comply with the alignment requirements.  
▪ Any address within the PAMT range must comply with the platform’s maximum PA, and its HKID bits 
must be 0 . 
▪ The size of each PAMT region must be large enough to contain the PAMT for its associated TDMR.  
• Reserved areas within TDMR must be sorted in an ascending offset order.  20 
• A null reserved area (indicated by a size of 0) may be followed only by other null reserved areas.  
• For each reserved area within TDMR:  
▪ Offset and size must comply with the alignment and granularity requirements.  
▪ Reserved areas must not overlap.  
▪ Reserved areas must be fully contained within their TDMR.  25 
o TDMRs must not overlap with other TDMRs.  
o PAMTs must not overlap with other PAMTs.  
o TDMRs’ non -reserved parts and PAMTs must not overlap (PAMTs may reside within TDMR reserved areas).  
o TDMRs’ non -reserved parts must be contained in convertible memory – i.e., in CMRs.  
o PAMTs must be contained in convertible memory – i.e., in CMRs.  30 
4. Check and set the Intel TDX global private HKID.  The provided HKID must be in the TDX HKID range.  
5. Complete the initialization of the Intel TDX module  at platform scope . 
6. Set PL.SYS_STATE to SYS CONFIG _DONE . 
Completion Status Codes  35 
Table 5.212:  TDH.SYS.CONFIG  Completion Status Codes (Returned in RAX) Definition  
TDX_INVALID_PAMT   
TDX_INVALID_RESERVED_IN_TDMR   
 TDX_INVALID_TDMR   
TDX_NON_ORDERED_RESERVED_IN_TDMR   
TDX_NON_ORDERED_TDMR    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 225 of 329 
TDX_PAMT_OUTSIDE_CMRS   
TDX_PAMT_OVERLAP   
TDX_SUCCESS  TDH.SYS. CONFIG is successful . 
TDX_SYS_BUSY  The operation was invoked when another TDX module operation 
was in progress .  The operation may be retried.  
TDX_SYSINIT_NOT_DONE   
TDX_SYSINITLP_NOT_DONE   
TDX_TDMR_ALREADY_INITIALIZED   
TDX_TDMR_OUTSIDE_CMRS   
November 2023  . Page 226 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.53.  TDH.SYS.INFO Leaf  
Provide information about the Intel TDX module and the convertible memory . 
Note:  TDH.SYS.INFO is provided for backward compatibility.  TDH.SYS.RDALL is the recommended method to read Intel 
TDX module information.  
Table 5.213:  TDH.SYS.INFO In put Operands Definition  5 
Must be 0  
RCX The physical address (including HKID bits) of a buffer where the output TDSYSINFO_STRUCT  will be 
written   
RDX  The number of bytes in the above buffer  
R8 The physical address (including HKID bits) of a buffer where an array of CMR_INFO will be written   
R9 The number of CMR_INFO entries in the above buffer  
 
Table 5.214:  TDH.SYS.INFO Out put Operands Definition  
RDX  The actual number of bytes written to the above buffer  
In case of an error, as indicated by RAX, RDX returns 0.  
R9 The number of CMR_INFO entries actually written to the above buffer  
 
Note:  The description below is provided at a high level.  Actual details, order of checks, returned status codes, etc. may 10 
vary.  
TDH.SYS.INFO provides information about the Intel TDX module and about the memory configuration.  
November 2023  . Page 227 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.215:  TDH.SYS.INFO Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDX system 
information 
structure  TDSYSINFO_STRUCT  RW Shared  1024B  None  N/A N/A 
Explicit  R8 HPA  CMR table  CMR_INFO_ARRAY  RW Shared  512B  None  N/A N/A 
 
1.1. TDH.SYS.INIT has been executed.  5 
1.2. TDH.SYS.LP.INIT has been executed on the current LP.  
2. The number of bytes provided for returning TDSYSINFO_STRUCT  (in RDX) must be at least the size of that structure.  
3. The number of entries provided for returning CMR_INFO_ARRAY (in R9) must be at least the number of CMRs  
supported by TDX . 
If successfu l, the function does the following:  10 
4. Write the TDSYSINFO_ STRUCT and  set RDX to the actual number of bytes written.  
5. Write the CMR_INFO_ARRAY based on the CMR information in SEAMCFG and  set R9 to the number of CMRs.  
Table 5.216:  TDH.SYS.INFO Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.SYS. INFO is successful . 
November 2023  . Page 228 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.54.  TDH.SYS.INIT Leaf  
Globally initialize the Intel TDX module . 
Table 5.217:  TDH.SYS.INIT In put Operands Definition  
23:16  Version 
Number  Selects the SEAMCALL interface function version  
Must be 0  
63:24  Reserved  Must be 0

Must be 0  
RCX Intel TDX module attributes  
63:0 RESERVED  Reserved:  must be 0  
 
Table 5.218:  TDH.SYS.INIT Out put Operands Definition  5 
If RAX returns TDX_INCORRECT_CPUID_VALUE , RCX returns the applicable CPUID information as 
shown below.  In all other cases, RCX returns 0.  
63:32  SUBLEAF  CPUID sub-leaf number:  if sub -leaf is not applicable, value is -1 
If RAX returns TDX_INCORRECT_CPUID_VALUE , RDX returns the value masks as shown below.  A bit 
value of 1 indicates a bit position that was checked  against the required value.  In all other cases, 
RDX returns 0.  
31:0  MASK_EAX  Mask of the value returned by CPUID in EAX   
63:32  MASK_EBX  Mask of the value returned by CPUID in EBX   
R8 Extended error information part 3  
If RAX returns TDX_INCORRECT_CPUID_VALUE , R8 returns the value masks as shown below.  A bit 
R8 returns 0.  
31:0  MASK_ECX  Mask of the value returned by CPUID in ECX    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 229 of 329 
63:32  MASK_EDX  Mask of the value returned by CPUID in EDX   
R9 Extended error information part 4  
If RAX returns TDX_INCORRECT_CPUID_VALUE , R9 returns the expected values as shown below.  In 
all other cases, R9 returns 0.  
31:0  VALUE_EAX  Value expected to be returned by CPUID in EAX   
63:32  VALUE_EBX  Value expected to be returned by CPUID in EBX   
R10 Extended error information part 5  
If RAX returns TDX_INCORRECT_CPUID_VALUE , R10 returns the expected values as shown below.  
In all other cases, R10 returns 0.  
31:0  VALUE_ECX  Value expected to be returned by CPUID in ECX   
63:32  VALUE_EDX  Value expected to be returned by CPUID in EDX   
 
Special Environment Requirements  
If the IA32_TSX_CTRL MSR is supported by the CPU, as enumerated by IA32_ARCH_CAPABILITIES.TSX_CTRL  (bit 7), then  
the values of its following bits must be 0:  
• RTM_DISABLE ( bit 0 ) 5 
• TSX_CPUID_CLEAR (bit 1)  
The IA32_MISC_PACKAGE_CTRL MSR must be supported by the CPU, as enumerated by IA32_ARCH_CAPABILITIES.  
MISC_PACKAGE_CTRL (bit 11).  IA32_MISC_PACKAGE_CTLS.ENERGY_FILTERING_ENABLE  (bit 0) must be set to 1.  
TDH.SYS.INIT execution time may be longer than most TDX module interface functions execution time.  No interrupts 10 
vary.  
TDH.SYS. INIT performs global (platform -scope) initialization of the Intel TDX module .  This function is intended to be 15 
executed during OS/VMM boot and thus it has relaxed latency requirements.  
Table 5.219:  TDH.SYS. INIT Operands Information Definition  
Explicit/  
1GB  
module internal 
November 2023  . Page 230 of 329 
Intel TDX Application Binary Interface (ABI) Reference  In addition to the memory operand checks per the table above, the function checks the following conditions:  
1. Check that PL.SYS_STATE is SYSINIT_PENDING.  
2. Do any global Intel TDX module initializations required for running this flow.  
3. Check the memory operands per the table above.  
4. Check the following conditions (no specific order is implied):  5 
• Enumerate CPU and platform information , and check  Intel TDX module compatibility.   If the Intel TDX module is 
compatible with multiple variants of CPU and platform features, sample the current LP’s features enumeration 
– to be later checked to be the same on all LPs by TDH.SYS.LP.INIT.  Examples of compatibility checks are:  
o The CPU must support any ISA that the Intel TDX module relies upon, such as SHA -NI. 
o The CPU must support the WBINVD scope for which  the Intel TDX module was built.  10 
• Sample and check  the platform configuration on the current LP – to be later checked to be the same on all LPs 
by TDH.SYS.LP.INIT.  For example:  
o Sample SMRR and SMRR2, check  they are locked and do not overlap any CMR, and store their values to be 
checked later on each LP.  
6. Set PL.SYS_STATE to SYSINIT_DONE . 
Table 5.220:  TDH.SYS. INIT Completion Status Codes (Returned in RAX) Definition  
TDX_BOOT_NT4_SET   
TDX_CPUID_LEAF_1F_FORMAT_UNRECOGNIZED   
TDX_CPUID_LEAF_1F_NOT_SUPPORTED   
TDX_ CPUID_LEAF_0D_INCONSISTENT   
TDX_INCORRECT_CPUID_VALUE  Additional information is provided in RCX – R10 
TDX_INCORRECT_MSR_VALUE   
TDX_INVALID_WBINVD_SCOPE   
TDX_RND_NO_ENTROPY  Random number generation (e.g., RDRAND or RDSEED) 
TDX_SMRR_LOCK_NOT_SUPPORTED   
TDX_SMRR_NOT_LOCKED   
TDX_SMRR_NOT_SUPPORTED   
TDX_SMRR_OVERLAPS_CMR   
TDX_SUCCESS  TDH.SYS. INIT is successful . 
TDX_SYS_BUSY  The operation was invoked when another TDX module 
operation was in progress .  The operation may be retried.  
TDX_SYSINIT_NOT_PENDING   
November 2023  . Page 231 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.55.  TDH.SYS.KEY.CONFIG Leaf  
Configure the Intel TDX  global private key on the current package . 
Table 5.221:  TDH.SYS.KEY.CONFIG In put Operands Definition  
Must be 0  
 
Table 5.222:  TDH.SYS.KEY.CONFIG Out put Operands Definition  5 
 
TDH.SYS.KEY.CONFIG execution time may be longer than most TDX module interface functions execution time.  No 
vary.  
TDH.SYS.KEY.CONFIG performs package -scope Intel TDX global private key configuration.  
Table 5.223:  TDH.SYS.KEY.CONFIG  Operands Information  
Explicit/  
1GB  
 
1. Check  that TDH.SYS.CONFIG has completed successfully (PL.SYS_STATE is SYSCONFIG_DONE).  
2. Do the following as an atomic operation (e.g., LOCK BTS) on PL.PKG_CONFIG_BITMAP:  
2.1. Check  the package has not yet been configured.  
2.2. Mark it as configured.  
3. Execute PCONFIG to configure the Intel TDX global private HKID on the package with a CPU -generated random key.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 232 of 329 
Intel TDX Application Binary Interface (ABI) Reference  PCONFIG may fail due to an entropy error or a device busy error.  In these cases, the VMM should retry 
TDH.SYS.KEY.CONFIG.  
4. On server platforms:  If this was the last package on which TDH.SYS.KEY.CONFIG has executed, set PL.STATE to 
SYS_READY.  5 
Completion Status Codes

Table 5.224:  TDH.SYS.KEY.CONFIG  Completion Status Codes (Returned in RAX) Definition  
TDX_KEY_GENERATION_FAILED  Failed to generate a random key.  This is typically caused by an 
entropy error of the CPU's random number generator, and may 
be impacted by RDSEED, RDRAND or PCONFIG executing on 
other LPs.  The operation should be retried.  
TDX_SUCCESS  TDH.SYS.KEY.CONFIG  is successful . 
November 2023  . Page 233 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.56.  TDH.SYS.LP.INIT Leaf  
Initialize the Intel TDX module at the current logical processor scope . 
Table 5.225:  TDH.SYS.LP.INIT In put Operands Definition  
Must be 0  
 
Table 5.226:  TDH.SYS.LP.INIT Out put Operands Definition  5 
If RAX returns TDX_INCONSISTENT_CPUID_FIELD , RCX returns the applicable CPUID information as 
shown below.  
If RAX returns TDX_INCONSISTENT_CPUID_FIELD , RDX returns the value masks as shown below.  A 
bit value of 1 indicates a bit position that was checked  against the same CPUID leaf value checked 
during TDH.SYS.INIT.  
In all other cases, RDX returns 0.  
If RAX returns TDX_INCONSISTENT_CPUID_FIELD , R8 returns the value masks as shown below.  A 
In all other cases, R8 returns 0.  
31:0  MASK_ECX  Mask of the value returned by CPUID in ECX   
63:32  MASK_EDX  Mask of the value returned by CPUID in EDX    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 234 of 329 
 
TDH.SYS.LP.INIT execution time may be longer than most TDX module interface functions execution time.  No interrupts 10 
vary.  
TDH.SYS.LP.INIT  performs LP-scope initialization of the Intel TDX module .  This function is intended to be executed during 15 
OS/VMM boot, and thus it has relaxed latency requirements.  
Table 5.227:  TDH.SYS.LP.INIT  Operands Information  
Explicit/  
1GB  
variables  N/A RW Hidden  N/A Shared  N/A N/A 
 20 
1. TDH.SYS.INIT has completed successfully (PL.SYS_STATE is SYSINIT_DONE).  
2. This is the first invocation of TDH.SYS.LP.INIT on the current LP.  
3. Do a global EPT flush (INVEPT type 2).  25 
4. Initialize the Intel TDX module ’s LP -scope variables.  
5. Check  the compatibility and uniformity of features and configuration.  Once per LP, core or package, depending on 
the scope of the checked feature or configuration:  
5.1. Check  features compatibility with the Intel TDX module.  In cases where the Intel TDX module supports several 
options, check  that the features on the current LP are the same as sampled during TDH.SYS.INIT.  30 
5.2. Check  configuration uniformity.  For example, the SMRR and SMRR2 must be locked and configured in the same 
way as sampled during TDH.SYS.INIT.  
6. Mark the current LP as initialized.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 235 of 329 
Table 5.228:  TDH.SYS.LP.INIT  Completion Status Codes (Returned in RAX) Definition  
TDX_INCONSISTENT_CPUID_FIELD  Additional information is provided in RCX – R8 
TDX_INCONSISTENT_MSR   
TDX_INVALID_PKG_ID   
TDX_RND_NO_ENTROPY  Random number generation (e.g., RDRAND or RDSEED) failed 
because the hardware random number generator did not have 
enough entropy.  The host VMM should retry the operation.  
TDX_SUCCESS  TDH.SYS.LP.INIT is successful.  
was in progress.  The operation may be retried.  
TDX_SYSINITLP_DONE   
 
November 2023  . Page 236 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.57.  TDH.SYS.LP. SHUTDOWN  Leaf  (Deprecated)  
Table 5.229:  TDH.SYS. LP.SHU TDOWN In put Operands Definition  
Must be 0  
 
Table 5.230:  TDH.SYS.LP.SHUTDOWN Out put Operands Definition  5 
 
vary.  
TDH.SYS.LP.SHUTDOWN does nothing.  10 
Table 5.231:  TDH.SYS.LP.SHUTDOWN  Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.SYS.LP.SHUTDOWN  is successful . 
 
November 2023  . Page 237 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.58.  TDH.SYS.RD Leaf  
Read a TDX Module global -scope metadata field.  
Table 5.232:  TDH.SYS.RD Input Operands  Definition  
Must be 0  
RDX  Field identifier – see 3.10   
must be 0.  
A value of -1 is a special case:  it is not a valid field identifier; in this case the first readable field 
identifier is returned in RDX.  
 
Table 5.233:  TDH. SYS.RD Output Operands Definition  5 
RDX  If the input field identifier was -1, RDX returns the first readable field identifier.  
Else, in case of an error, RDX returns -1.  On success, RDX returns the next readable field identifier.  
A value of -1 indicates no next field identifier is available.

Must be 0  
must be 0.  
 
vary.  
TDH.SYS.RD reads a TDX Module global -scope metadata field.  10 
Enumeration:  Availability of TDH. SYS.RD is enumerated by TDSYSINFO_STRUCT.SYS_RD, returned by TDH.SYS.INFO 
(see 3.3.5 ).  It is also enumerated by TDX_FEATURES0.ENHANCED_METADATA (bit 3), readable by 
TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.SYS.RD returns a 
RDX returns the next host -side readable field identifier.  This may be used by the host VMM to enumerate the TDX 15 
Module’s capabilities and configuration.  To read all the available fields, the host VMM can invoke TDH.SYS.RD in a loop, 
starting with field identifier -1 as an input, until RDX returns -1.  A status code of TDX_METADATA_FIELD_SKIP indicates 
that the returned value is not applicable.   Alternatively, the host VMM can use TDH.SYS.RDALL.  
of the Intel TDX Module API . 20  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 238 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.234:  TDH.SYS.RD  Operands Information Definition  
Explicit/  
1GB  
There are no relevant memory operands.  
 
If successfu l, the function does the following:  
2. Read the requested  field using the algorithm described in 5.2.2.1 . 
3. Return the next readable field identifier, or a value of 0 if none exists.  
4. Return the field value . 10 
Table 5.235:  TDH.SYS.RD Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.SYS. RD is successful.  
November 2023  . Page 239 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.59.  TDH.SYS.RDALL Leaf  
Read all host -readable TDX Module global -scope metadata fields.  
Table 5.236:  TDH.SYS.RDALL Input Operands  Definition  
Must be 0  
RDX  The physical address (including HKID bits) of  a 4KB page where a metadata list will be returned  
In case of error, some field value entries might not contain valid data.  
R8 Initial field identifier  – see 3.10  
If R8’s value is -1, then TDG.SYS.RDALL will start from the first global -scope metadata field 
identifier.  
Else, LAST_ELEMENT_IN_FIELD, LAST_FIELD_IN_SEQUENCE, WRITE_MASK_VALID and 
CONTEXT_CODE fields are ignored.   The FIELD_CODE must be the code of the first element of a 
metadata field.  
 
Table 5.237:  TDH.SYS.RDALL Output Operands Definition  5 
R8 Next field identifier.   A value of -1 means all applicable field identifiers have been returned in the 
metadata list.  
In case of an error, as indicated by RAX, R8 returns -1. 
 
vary.  
TDH.SYS.RDALL reads all host -readable TDX Module global -scope metadata fields  into a metadata list in the provided 10 
page.  
If one or more applicable fields do not fit in the provided list buffer, the function can be invoked in a loop, each invocati on 
providing an initial field identifier returned as the next field identifier of the previous invocation, as shown in the follo wing 
example:  
1. NEXT_FIELD_ID = -1 15 
2. Repeat:  
2.1. Set LIST_BUFFER to the next 4K buffer  
2.2. Invoke TD H.SYS.RDALL(RDX = LIST_BUFFER, RDX = NEXT_FIELD_ID)  
2.3. STATUS = RAX, NEXT_FIELD_ID = R8  
Until ((STATUS is a non -recoverable error) or (NEXT_FIELD_ID is -1)) 20 
The function never returns an empty list if there’s no error.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 240 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Enumeration:  Availability of TDH. SYS.RDALL is enumerated by TDSYSINFO_STRUCT.SYS_RD, returned by 
TDH.SYS.INFO (see 3.3.5 ).  It is also enumerated by TDX_FEATURES0.ENHANCED_METADATA (bit 3), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.SYS.RDALL returns a 
Table 5.238:  TDH.SYS.RDALL  Operands Information Definition  
Explicit/  
1GB  
Explicit  RDX  HPA  Metadata list  MD_LIST  RW Shared  4KB None  None  None  
 
1. Global and LP -scope initialization has been done:  10 
1.1. TDH.SYS.INIT has been executed.  
2. Dump the list of next host -readable metadata fields into the provided page.  
Completion Status Codes  15 
Table 5.239:  TDH. SYS.RDALL Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH. SYS.RDALL  is successful . 
November 2023  . Page 241 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.60.  TDH.SYS.SHUTDOWN Leaf  
Initiate  Intel TDX module shutdown and  generate handoff data for the next Intel TDX module . 
Table 5.240:  TDH.SYS.SHUTDOWN Input Operands Definition  
Must be 0  
RCX REQ_HV  Requested handoff version  
 
Table 5.241:  TDH.SYS.SHUTDOWN Output Operands Definition  5 
RAX  Status  SEAMCALL instruction return code – see 5.3.1  
 
vary.  
TDH.SYS.SHUTDOWN initiates  Intel TDX module shutdown and  generates handoff data for the next Intel TDX module .  10 
Following this function, no further TDX module interface functions can be called.  
Table 5.242:  TDH.SYS.SHUTDOWN  Operands Information  
Explicit/  
1GB  
 15 
1. The requested handoff version ( REQ_ HV) is legal : 
1.1. PL.MIN_UPDATE_HV <= HV <= PL.MODULE_HV

vary.  
Explicit/  
1GB  
 15 
1.1. PL.MIN_UPDATE_HV <= HV <= PL.MODULE_HV  
1.2. If PL.NO_DOWNGRADE == 1 then HV == PL.MODULE_HV  
If successful:  20 
2. Set TDX module’s PL.STATE  to SYS_SHUTDOWN  to fail further TDX module interface function calls.  
3. Check that  all other LPs are not executing in SEAM mode.  
4. Prepare handoff data in handoff pages , according to REQ_ HV, from module’s variables.  
5. Mark the handoff data as valid (ready for consumption).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 242 of 329 
Table 5.243:  TDH.SYS.SHUTDOWN  Completion Status Codes (Returned in RAX) Definition  
TDX_OPERAND_INVALID  The requested handoff version is invalid . 
TDX_SUCCESS  TDH.SYS.SHUTDOWN  is successful . 
TDX_SYS_ NOT_READY  TDH.SYS.SHUTDOWN  was called when TDX module ’s lifecycle 
state is not  SYS_READY.  
November 2023  . Page 243 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.61.  TDH.SYS.TDMR.INIT Leaf  
Partially initialize a Trust Domain Memory Region (TDMR) and its associated PAMT . 
Table 5.244:  TDH.SYS.TDMR.INIT In put Operands Definition  
Must be 0  
RCX The physical base address of a TDMR  (HKID bits must be 0)  
 
Table 5.245:  TDH.SYS.TDMR.INIT Out put Operands Definition  5 
RDX  On successful completion, RDX returns the TDMR next -to-initialize address.  This is the physical 
address of the last byte that has been initialized so far, rounded down to 1GB.  
 
vary.  
TDH.SYS.TDMR.INIT partially initializes the metadata (PAMT) associated with a Trust Domain Memory Region (TDMR), 10 
while adhering to latency considerations.  It can run concurrently on multiple LPs as long as each concurrent flow 
initializes a different TDMR.  After each 1GB range of a TDMR has been initialized, that 1GB range becomes available for 
use by any Intel TDX  function that creates a private TD page or a control structure page – e.g., TDH.MEM.PAGE.ADD, 
TDH.VP.ADDCX, etc.  
November 2023  . Page 244 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.246:  TDH.SYS.TDMR.INIT  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDMR  Blob  None  None  1GB  Exclusive  N/A N/A 
Implicit  N/A HPA  PAMT region 
associated with 
TDMR  Blob  RW Hidden  N/A Exclusive  N/A N/A 
 
1. The provided TDMR start address belongs to one of the TDMRs set during TDH.SYS.INIT.  
2. The TDMR has not been completely initialized yet.  5 
3. If the TDMR has been completely initialized, there  is nothing to do.  
Else, the function does the following:  
4. Initialize the next implementation defined un -initialized number of PAMT entries.  The maximum number of PAMT 
entries to be initialized is set to help avoid latency issues.  10 
4.1. PAMT_4K entries associated with a physical address that is within a reserved range are marked with PT_RSVD.  
4.2. Other PAMT_4K entries are marked with PT_NDA.  
4.3. PAMT_2M and PAMT_1G entries are marked with PT_NDA.  
5. If the PAMT for a 1GB block of TDMR has been fully initialized, mark that 1GB block as ready for use.  This means that 
4KB pages in this 1GB block may be converted to private pages – e.g., by SEAMCALL(TDH.MEM.PAGE.ADD).  This can 15 
be done concurrently with initializing other TDMRs.  
6. Return the next -to-initialize address rounded down to 1GB.  This is done so the host VMM will not  attempt to use a 
1GB block that is not fully initialized.  
Table 5.247:  TDH.SYS.TDMR.INIT  Completion Status Codes (Returned in RAX) Definition  20 
TDX_SUCCESS  TDH.SYS.TDMR.INIT  is successful . 
November 2023  . Page 245 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.62.  TDH.SYS.UPDATE Leaf  
Populate Intel TDX module internal variables from the handoff data prepared by the previous Intel TDX module . 
Table 5.248:  TDH.SYS.UPDATE Input Operands Definition  
Must be 0  
 
Table 5.249:  TDH.SYS.UPDATE Output Operands Definition  5 
 
vary.  
Enumeration:  Availability of TDH. SYS.UPDATE is enumerated by TDX_FEATURES0.TD_PRESERVING (bit 1), 10 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.SYS.UPDATE returns a 
TDH.SYS. UPDATE  reads the  handoff data prepared by the previous  Intel TDX module .  The operation may fail in the 
• No valid handoff data  15 
• The old module’s handoff data’s version is too old for the current TDX module  
• The old module’s handoff data’s version is newer than the current TDX module’s handoff data version  
On such failures the host VMM is expected to do one of the following:  
• Request the Persistent SEAMLDR to update to another TDX module ( UPDATE  scenario) .  If that update is successful, 
existing TDs are preserved.  20 
• Keep the current TDX module and continue with the non -update sequence (TDH.SYS.CONFIG, TDH.SYS.KEY.CONFIG 
etc.).  In this case all existing TDs are lost.  
November 2023  . Page 246 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.250:  TDH.SYS.UPDATE  Operands Information  
Explicit/  
1GB  
 
1. The TDX module’s PL.STATE is SYSINIT_DONE.  
2. All LPs have been initialized.  5 
3. The handoff data in memory is valid and its handoff version (HV) is legal.  
4. Populate HV -specific variables within SEAM range from the handoff data.  
5. Mark the handoff data as invalid (consumed).  
6. Set the TDX module’s  PL.STATE to SYS_READY . 10 
Table 5.251:  TDH.SYS.UPDATE Completion Status Codes (Returned in RAX) Definition  
TDX_CONNECT_INVALID_STATE  Applicable only for TDX module and CPUs that support TDX 
Connect  
TDX_SUCCESS  TDH.SYS.UPDATE is successful . 
TDX_SYS_STATE _INCORRECT  TDH.SYS.SHUTDOWN  was called when the TDX module’s 
lifecycle state in not SYSINIT_DONE or some LPs have not yet 
been initialized by TDH.SYS.LP.INIT.  
TDX_ SYS_ INVALID _HANDOFF  The handoff data in SEAM range is invalid.  
 
   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US

Connect  
 
November 2023  . Page 247 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.63.  TDH.VP.ADDCX Leaf  
Add a physical  page to a TDVPS . 
Table 5.252:  TDH.VP.ADDCX In put Operands Definition  
Must be 0  
RCX The physical address of a page where the TDCX  page will be added  (HKID bits must be 0)  
RDX  The physical address of a TDVPR page  (HKID bits must be 0)  
 
Table 5.253:  TDH.VP.ADDCX Out put Operands Definition  5 
 
vary.  
TDH.VP.ADDCX a dds a physical  page to a TDVPS, as a child of a given TDVPR . 10 
Cache Flush : Before calling TDH.VP.ADDCX, the host VMM should ensure that no cache lines associated with the 
added TDVPS physical page are in a Modified state, as described in the [Base Spec].  
Table 5.254:  TDH.VP.ADDCX Operands Information Definition  15 
Explicit/  
1GB  
Explicit  RCX HPA  TDCX  page  Blob  RW Opaque  4KB Exclusive  Shared  Shared  
Explicit  RDX  HPA  TDVPR page  Blob  RW Opaque  4KB Exclusive  Shared  Shared  
Implicit  N/A HPA  TDR page  TDR  RW Opaque  N/A Shared  None  None  
November 2023  . Page 248 of 329 
Intel TDX Application Binary Interface (ABI) Reference  In addition to the explicit memory operand checks per the table above, the function checks the following conditions:  
1. The TDVPR page metadata in PAMT must be correct ( PT must be PT_TDVPR) . 
3. The TD keys are configured on the hardware ( TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED).  
4. The TD has been initialized (by TDH.MNG.INIT).  5 
5. The TD build and measurement must not have been finalized (by TDH.MR.FINALIZE).  
6. The TD VCPU has not been initialized (by TDH.VP.INIT) and is not being torn down (TDVPS. VCPU_ STATE is 
VCPU_UNINITIALIZED).  
7. The new TDCX  page metadata in PAMT must be correct (PT must be PT_NDA).  
8. The maximum number of TDCX  pages per TDVPS  (as enumerated by TDH.SYS.RD * or TDH.SYS .INFO) has not been 10 
exceeded.  
If successful, the function  does the following:  
9. Zero out the TDCX  page contents using direct writes (MOVDIR64B).  
10. Increment the VCPU’s TDCX  counter and  set a pointer in the parent TDVPR page to the new TDCX  page.  
11. Increment TDR.CHLDCNT.  15 
12. Initialize the TDCX  page metadata in PAMT.  
Table 5.255:  TDH.VP.ADDCX Completion Status Codes (Returned in RAX) Definition  
TDX_PAGE_METADATA_INCORRECT   
TDX_SUCCESS  TDH.VP.ADDCX  is successful . 
TDX_ TDCX _NUM_INCORRECT   
 
November 2023  . Page 249 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.64.  TDH.VP.CREATE Leaf  
Create a guest TD VCPU and its TDVPS root page ( TDVP R). 
Table 5.256:  TDH.VP.CREATE In put Operands Definition  
Must be 0  
RCX The physical address of a page where TDVPR will be added  (HKID bits must be 0)  
 
Table 5.257:  TDH.VP.CREATE Out put Operands Definition  5 
 
vary.  
TDH.VP.CREATE begins the build of a new guest TD VCPU.  It adds a TDVPR page as a child of a TDR page.  10 
Cache Flush : Before calling TDH.VP.CREATE, the host VMM should ensure that no cache lines associated with the 
added TDVPR physical page are in a Modified state, as described in the [Base Spec].  
Table 5.258:  TDH.VP.CREATE Operands Information Definition  15 
Explicit/  
1GB  
Explicit  RCX HPA  TDVPR page  Blob  RW Opaque  4KB Exclusive  Shared  Shared  
 
2. The TD is not in a FATAL state (TDR.FATAL is FALSE).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 250 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED).  
4. The TD must either have been initialized but not finalized ( TDR.NUM_TDCX is the required number  and 
TDCS.OP_STATE is INITIALIZED ), or a migration session is in progress as state migration has begun by 
TDH.IMPORT.STATE.TD (OP_STATE is STATE_IMPORT) . 
5. The TDVPR page metadata in PAMT must be correct (PT must be PT_NDA).  5 
6. Zero out the TDVPR page contents using direct write (MOVDIR64B).  
7. Increment TDR.CHLDCNT.  
8. Initialize the TDVP S management fields , which all reside in the TDVPR page.  
9. Initialize the TDVPR page metadata in PAMT.  10 
Table 5.259:  TDH.VP.CREATE Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDH.VP.CREATE  is successful . 
 
November 2023  . Page 251 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.65.  TDH.VP.ENTER  Leaf  
Enter TDX non -root operation.   
From the host VMM’s point of view, TDH.VP.ENTER  is a complex operation that normally involves TD entry followed by a 
TD exit.  Therefore, input and output operands are specified by multiple tables below.  
Inputs  5 
TDH.VP.ENTER output format depends on how the previous TDH.VP.ENTER was terminated.   There are two cases:  
• Initial entry or following a previous asynchronous TD exit 
• Following a previous TDCALL(TDG.VP.VMCALL)  
The following table details TDH.VP.ENTER input operands for initial entry  or following a  previous asynchronous TD exit . 
Table 5.260:  TDH.VP.ENTER  Input Operands Format #1 Definition :  For Initial Entry or Following a Previous  10 
Asynchronous TD Exit  
Must be 0  
RCX VCPU handle and flags  
Bit(s)  Name  Description

Inputs  5 
Must be 0  
11:0  RESERVED  Must be 0  
51:12  TDVPR_HPA  Bits 51:12 of the physical address of the TD VCPU’s TDVPR page 
52 HOST_RECOVERABILITY_  
HINT  Applicable only following a  previous trap -like asynchronous TD 
exit, where bit 60 (HOST_RECOVERABILITY_HINT) of the 
previous TDH.VP.ENTER completion status (returned in RAX) 
was set to 1.  In all other cases this bit must be 0.  
0: The host VMM hints that the guest -side function may 
possibly be retried (e.g., the host may have corrected some 
conditions).  
1: The host VMM hints that the error is probably not 
recoverable.  
This bit is reflected to the guest TD in bit 60 of RAX.  
53 RESUME_L1  For partitioned TDs, i ndicates that the L1 VMM should be 
resumed.  Applicable after TD exits from an L2 VM.  
0: TDH.VP.ENTER resumes the L2 VM it last exited from.  
1: TDH.VP.ENTER resumes L1 VMM, even if the previous TD 
exit was from an L2 VM.  
63:54  RESERVED  Must be 0   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 252 of 329 
The following table details TDH.VP.ENTER input operands for following a  previous synchronous TD exit  
(TDG.VP.VMCALL) . 
Table 5.261:  TDH.VP.ENTER  Input Operands Format #2 Definition :  Following a Previous TDCALL( TDG.VP.VMCALL ) 
RAX  SEAMCALL instruction leaf and version numbers – see 5.3.1  
52 RESERVED  Must be 0  
53 RESUME_L1  For partitioned TDs, indicates that the L1 VMM should be 
63:54  RESERVED  Must be 0  
RBX, RDX, 
RBP, RSI, 
RDI, 
R8 – R15 If the corresponding bit of RCX at the previous TD exit (i.e., previous TDH.VP.ENTER  termination) 
was set to 1, the register value is passed as -is to the guest TD  – see the description of 
TDG.VP.VMCALL  in 5.4.21  for details.  
Else, the register  value is not used as an input.  
If the TD’s CONFIG_FLAGS.NO_RBP_MOD is set to 1, then RBP can’t be used to pass values to the 
guest TD.  See the enumeration note below.  
XMM0 – 
XMM15  If the corresponding bit of RCX at the previous TD exit (i.e., previous TDH.VP.ENTER  termination) 
 5 
Outputs  
TDH.VP.ENTER output format depends on how the function was terminated.   There are multiple cases:  
• Error (No TD Entry)  
• Asynchronous TD exit following a TD entry (with a VMX architectural exit reason)  
• Asynchronous TD exit following a TD entry (with a non-VMX  TD e xit status ) 10 
• Asynchronous TD exit following a TD entry (with  cross -TD exit details)  
• TDCALL(TDG.VP.VMCALL) following a TD entry 
The following table details TDH.VP.ENTER output operands when an error occurs,  and the interface function returns 
without entering the TD . 
Table 5.262:  TDH.VP.ENTER  Output Operands Format #1 Definition :  On Error (No TD Entry)  15 
RAX  Status  SEAMCALL instruction return code  
63 ERROR  Set to 1   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 253 of 329 
47:32  CLASS and 
DETAILS_L1  None of the values detailed in the table below  
Other   See the function completion status definition in 5.3.1 . 
Other  
GPRs  Unmodified  
Extended 
State  Any extended state that the TD is allowed to use (per TDCS.XFAM) may be cleared to its 
architectural INIT state.  
 
The following table details TDH.VP.ENTER output operands when TD entry succeeds, and later an asynchronous TD exit 
occurs due to a VMX architectural exit reason . 
Table 5.263:  TDH.VP.ENTER  Output Operands Format #2 Definition :  On Asynchronous TD Exits  Following a TD Entry  
(with a VMX Architectural Exit Reason)  5 
31:0  DETAILS_L2:  Exit 
Reason  VMCS exit reason  
Note:  Exit reason TDCALL (77) is a special case, 
indicating a synchronous TD exit initiated by 
TDG.VP.VMCALL; see below.  
DETAILS_L1  May have the following values:  
• TDX_SUCCESS, indicating a normal TD exit  
• TDX_NON_RECOVERABLE_VCPU, indicating that 
the VCPU is disabled  
• TDX_NON_RECOVERABLE_TD, indicating that 
the TD is disabled  
• TDX_NON_RECOVERABLE_TD_NON_ACCESSIBLE, 
indicating that the TD is disabled, and its private 
memory can’t be accessed  
• TDX_TD_EXIT_ON_L2_VM_EXIT and 
TDX_TD_EXIT_ON_L2_TO_L1, indicating a debug 
TD exit on L2 transitions  
Other   See the function completion status definition in 
5.3.1 . 
RCX Exit 
Information  Index of the VM from which the TD exit occurred  
31:0  EXIT_QUALIFICATION  VMCS exit qualification bits 31:0  
Note:  VMCS exit qualification bits 63:32 are always 
0. 
When exit is due to an EPT violation, bits 12:7 are 
cleared to 0.  
33:32  VM Index of the VM that was running at the time of TD 
exit 
63:34  RESERVED  Reserved, set to 0  
RDX  Extended 
Exit 
Qualification  Additional non -VMX, TDX -specific information – see 3.7.1   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 254 of 329 
R8 Guest 
Physical 
Address  When exit is due to EPT violation or EPT misconfiguration, format is similar to the 
VMCS guest -physical address, except that bits 11:0 are cleared to 0.  
In other cases, R8 is cleared to 0.  
R9 VM-Exit 
Interruption 
Information  When exit is due to a vectored event, format of bits 31:0 is similar to the VMCS VM -
exit interruption information.  Bits 63:32 are cleared to 0.  
In other cases, R9 is cleared to 0.  
RBX, RBP, 
RSI, RDI, 
R10 – 
R15 None  Cleared to 0  
Extended 
State  Any extended state that the TD is allowed to use (per TDCS.XFAM) is cleared to its architectural INIT 
state.  
 
The following table details TDH.VP.ENTER output operands on when TD entry succeeds, and later an asynchronous TD 
exit occurs with a non -VMX TD exit status  as described below.  
Table 5.264:  TDH.VP.ENTER Output Operands Format #3 Definition :  On Asynchronous TD Exits Following a TD Entry 
(with a non -VMX TD Exit Status)  5 
• TDX_HOST_PRIORITY_BUSY_TIMEOUT  
• TDX_NON_RECOVERABLE_TD_CORRUPTED_MD  
• TDX_TD_EXIT_BEFORE_L2_ENTRY  
5.3.1 . 
RCX Exit 
Information  TD exit information  
31:0  RESERVED  Reserved, set to 0  
exit 
RDX, RBX, 
RSI, RDI, 
R8 – R15 Reserved  Cleared to 0  
Extended 
state.  
 
exit occurs due to a cross -TD operation , i.e., the current TD operating on another TD.  
Table 5.265:  TDH.VP.ENTER Output Operands Format #4 Definition :  On Asynchronous TD Exits Following a TD Entry 
(with Cross -TD Exit Details ) 10 
RAX  Status  SEAMCALL instruction return code   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 255 of 329 
• TDX_CROSS_TD_FAULT, indicating a fault -like 
asynchronous TD exit, with non -VMX cross -TD 
status.  
• TDX_CROSS_TD_TRAP, indicating a trap -like 
status.  
5.3.1 . 
RCX Exit 
32:0  RESERVED  Reserved, set to 0  
exit 
RDX  Cross -TD 
Status  Status code of the error which caused the TD exit, using the same format as TDCALL 
instruction return code  
R8 Target TD  HPA of the TDR page of the TD which was the target of the cross -TD operation  
RBX, RSI, 
RDI, 
R9 – R15 Reserved  Cleared to 0  
Extended

status.  
status.  
5.3.1 . 
RCX Exit 
exit 
RBX, RSI, 
RDI, 
Extended 
state.  
 
The following table details TDH.VP.ENTER output operands on when TD entry succeeds, and later a synchronous TD exit , 
triggered by TDG.VP.VMCALL , occurs.  
Table 5.266:  TDH.VP.ENTER  Output Operands Format #5 Definition :  On TDCALL( TDG.VP.VMCALL ) Following a TD 
Entry  5 
Reason  VMCS exit reason, indicating TDCALL (77)  
DETAILS_L1  Indicating TDX_SUCCESS  
5.3.1 . 
RCX Exit 
Bit(s)  Name  Description   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 256 of 329 
31:0  PARAMS_MASK  Value as passed in to TDCALL(TDG.VP.VMCALL) by 
the guest TD:  indicates which part of the guest TD 
GPR and XMM state is passed as -is to the VMM and 
back.  For details, see the description of 
TDG.VP.VMCALL in 5.4.21 . 
exit 
RBX, RDX, 
RBP, RDI, 
RSI, 
R8 – R15 GPRs  If the corresponding bit in RCX is set to 1, the register value is passed as -is from the 
guest TD’s input to TDG.VP.VMCALL.  
Else, the register value cleared to 0.  
If the TD’s CONFIG_FLAGS.NO_RBP_MOD is set to 1, then RBP can’t be used to pass 
values from the guest TD and is not modified from its input value.  See the 
enumeration note below.  
XMM0 – 
XMM15  XMMs  If the corresponding bit in RCX is set to 1, the register value is passed as -is from the 
Extended 
State 
except 
XMM  Any extended state, except XMM, that the TD is allowed to use (per TDCS.XFAM) is cleared to its 
 
CPU State Preservation Following a Successful TD Entry and a TD Exit  
Following a successful TD entry and a TD exit, some CPU state is modified:  
• Registers DR0, DR1, DR2, DR3, DR6 and DR7 are set to their architectural INIT value.  
• XCR0 is set to the TD’s user -mode feature bits of XFAM  (bits 7:0, 9).  5 
• MSR state preservation across TD entry and exit is detailed in a separate JSON format file msr_preservation.json . 
The value read from IA32_TSC_ADJUST MSR must be the same as it was during TDH.SYS.INIT.  
Guest TD State Loading or VM Entry Failure  
TDH.VP.ENTER may fail loading guest TD state in the cases shown in the table below.  TDH.VP.ENTER returns with 10 
information detailing the failure case.  Such failures may happen due to the following reasons:  
• The TD is being debugged (its ATTRIBUTES.DEBUG bit is set) and the debugger set some wrong guest state value 
using TDH.VP.WR.  For a debuggable TD, the completion status (in RAX[63:32]) is set in such cases to TDX_SUCCESS, 
and the details are provided as d escribed below.  The debugger may update the VCPU state using TDH.VP.WR and 
invoke TDH.VP.ENTER again.  15 
• The TD has been migrated, and some of its state is not compatible with the destination platform.  The TDX module 
does its best effort to check guest state values during import, but there might still be cases where incompatible guest 
TD state gets migrated.   For a non -debuggable TD, the completion status (in RAX[63:32]) is set in such cases to 
TDX_NON_RECOVERABLE_TD, and the details are provided as described below.  The host VMM should tear down 
the TD.  20 
Table 5.267:  Guest State Loading Errors  
Guest State Loading Error  VM Exit Reason in RAX[31:0]  Extended Exit Qualification in RDX  
Error while loading guest MSR 
values from TDVPS  34: VM-entry failure due to MSR 
loading  TD_ENTRY_MSR_LOAD_FAILURE 
with the MSR index   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 257 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Guest State Loading Error  VM Exit Reason in RAX[31:0]  Extended Exit Qualification in RDX  
Error while loading CPU extended 
state from TDVPS  33: VM-entry failure due to invalid 
guest state  TD_ENTRY_XSTATE_LOAD_FAILURE  
VM entry (VMLAUNCH or 
VMRESUME) which loads guest 
state from VMCS  33: VM-entry failure due to invalid 
guest state  NONE  
 
In some cases (e.g., suspected single/zero step attack mitigation), TDH.VP.ENTER execution time may be longer than most 
TDX module interface functions execution time.  No interrupts (including NMI and SMI) are processed by the logical 
processor during that time.  5 
vary.  
TDH.VP.ENTER  enters TDX non -root operation.   It returns immediately if TD entry failed.  If TD entry succeeded, 
TDH.VP.ENTER returns when TD exit is initiated.  10 
For partitioned TDs, the TD VCPU may operate in the L1 VM or one of the L2 VMs, if any.  TD exit may be initiated from 
each of the TD’s VMs.  If last TD exit was from an L2 VM, TDH.VP.ENTER resumes the same L2 VM, unless the RESUME_L1 
input flag is set to 1, instructing TDH.VP.ENTER to resume the L1 VM.  
Enumeration:  Control of RBP usage as an input/output parameter by the TD’s CONFIG_FLAG.NO_RBP_MOD is 
enumerated by TDX_FEATURES0.NO_RBP_MOD (bit 18), readable by TDH.SYS.RD* (see 3.3.3.1 ).  If 15 
not supported, then RBP can be used by TDG.VP.VMCALL to pass information between the guest TD 
and the host VMM, although highly discouraged since it contradicts normal calling conventions ABI.  
VCPU Association : TDH.VP.ENTER  associates the target TD VCPU with the current LP.  This requires that the VCPU will 
not be associated with another LP.  For details, see the [ TDX Module Base Spec ]. 
To understand the table and text below, please refer to the [ TDX Module Base Spec ] chapter discussing general aspects 20 
Table 5.268:  TDH.VP.ENTER  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDVPR page  TDVPS  RW Opaque  4KB Shared (c)9 Shared (c)9 Shared (c)9 
Implicit  N/A HPA  TDR page  TDR  RW Opaque  N/A Shared (c)9 N/A N/A 
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  N/A Shared (i,c)9 N/A N/A 
Implicit  N/A N/A TDCS.OP_STATE  OP_STATE  RW Opaque  N/A Shared (t)10 N/A N/A 
Implicit  N/A N/A TDCS TLB 
Tracking Fields  N/A RW Opaque  N/A Shared (t)10 N/A N/A 
Implicit  N/A N/A SEPT tree  N/A R Opaque  N/A Exclusive(t)10 N/A N/A 
 
9 The shared locking of TDVPS, TDR, TDCS, TDCS.OP_STATE is for the whole duration of running in TDX non -root mode; the locks are 
released on TD exit.  
10 The locking of OP_STATE, SEPT tree and the TLB tracking fields is until before entering TDX non -root mode; the locks are released 
before VM entry into the TD VCPU.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 258 of 329 
Note:  For brevity, some details (e.g., zero -step mitigation) have been omitted.  
3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED ). 5 
4. The TD must have been finalized  and is allowed to run  (TDR.NUM_TDCX is the required number , and TDCS.OP_STATE 
is either RUNNING , LIVE_EXPORT or LIVE_IMPORT ). 
If successful, the function does the following : 
5. Associate the VCPU with the current LP, and update TD VMCS using the algorithm described in 5.2.1 . 
6. If requested to resume into L1:  10 
6.1. Check that the current VM is an L2 VM.  
6.2. Set a sticky flag for resuming into L1.  
If passed:  
7. Update the TLB tracking state.  This is done as a critical section allowing concurrent TDH.VP.ENTER s but no concurrent 
TDH.MEM.TRACK .  A concurrent TDH.MEM.TRACK  may cause this locking to fail; in this case, the caller is expected 15 
to retry TDH.VP.ENTER . 
7.1. Lock the TDCS epoch tracking fields in shared mode.  
7.2. Sample the TD’s epoch counter (TDCS.TD_EPOCH) into the VCPU’s TDVPS.VCPU_EPOCH.  
7.3. Atomically increment the TD’s REFCOUNT that is associated with the sampled epoch 
(TDCS.REFCOUNT[TD_EPOCH  % 2]). 20 
7.4. Release the shared mode locking of the epoch tracking fields.  
8. If TDVPS.VCPU_EPOCH was updated above, and this is not a new VCPU association:

If passed:  
8. If TDVPS.VCPU_EPOCH was updated above, and this is not a new VCPU association:  
8.1. Execute single -context (type 1) INVEPT.  
8.2. Invalidate all soft -translated GPAs.  25 
9. If current VM is an L2 VM:  
9.1. If the sticky flag for resuming into L1 is set:  
9.1.1.  If last TD exit was synchronous (due to TDG.VP.VMCALL):  
9.1.1.1.  Save the host VMM’s GPR and XMM register values into TDVPS.  
9.1.2.  If the sticky flag for resuming into L1 indicates a synchronous TD exit from L2:  30 
9.1.2.1.  Translate the TDG.VP.ENTER guest state GPA.  
If failed, emulate an EPT violation TD exit.  
If passed:  
9.1.2.2.  Write the TDG.VP.ENTER output to memory.  
9.1.3.  Do a virtual L2 →L1 exit:  35 
9.1.3.1.  Update the GPR image in TDVPS to emulate TDG.VP.ENTER output on L2 ->L1 exit . 
9.1.3.2.  Clear the sticky flag.  
9.1.3.3.  Make L1 the current VM.  
10. If entering to an L2 VM, translate soft -translated GPAs, if required . 
If failed, emulate an EPT violation TD exit.  40 
11. If the TD VCPU to be entered is different than the last TD VCPU entered on the current LP, issue an indirect branch 
prediction barrier command to the CPU by writing to the IA32_PRED_CMD MSR with the IBPB bit set . 
12. Set TDVPS.VCPU_STATE to VCPU_ACTIVE.  
13. Restore guest TD state:  
13.1. If previous TD exit was due to a TDG.VP.VMCALL : 45 
13.1.1.  Restore guest XMM and GPR state that is not passed as -is from the host VMM, as controlled by the 
value of guest TD RCX input to TDG.VP.VMCALL . 
13.1.2.  Set guest RAX to 0.  
13.2. Else (TD exit was an asynchronous exit):  
13.2.1.  Restore CPU extended state from TDVPS (per TDCS.XFAM).  50 
13.3. Restore other guest state from TDVPS.  
14. Execute VMLAUNCH or VMRESUME depending on whether the entered VCPU and VM (i.e., the current VMCS) has 
been launched on this LP since the VCPU’s last association with the LP (TDVPS.LAUNCHED[VM]).  
Note:  Logically, from the point of view of the host VMM, a successful TDH.VP.ENTER  is terminated by the next TD exit.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 259 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Completion Status  Codes  
Table 5.269:  TDH.VP.ENTER  Completion Status Codes (Returned in RAX) Definition  
TDX_INCONSISTENT_MSR  IA32_TSC_ADJUST  MSR value is different than the value 
sample by TDH.SYS.INIT.  
TDX_L2_EXIT_HOST_ROUTED_ASYNC   
TDX_L2_EXIT_HOST_ROUTED_TDVMCALL   
TDX_NON_RECOVERABLE_TD  TDH.VP.ENTER launched or resumed TD VCPU operation 
(TDX non -root mode) – followed later by a TD exit.  The TD 
state is non -recoverable – further TD entry is prohibited.  
Exit reason is in RAX bits 31:0.  
TDX_NON_RECOVERABLE_VCPU  TDH.VP.ENTER launched or resumed TD VCPU operation 
VCPU state is non -recoverable – further TD entry to this 
VCPU is prohibited.  Exit reason is in RAX bits 31:0.  
TDH.MEM.TRACK or TDH.EXPORT.PAUSE.  The host VMM 
may retry TDH.VP.ENTER.  
Another special case is where the indicated operand is 
SEPT_TREE.  In some cases, TDH.VP.ENTER may acquire 
exclusive access on the SEPT tree for a short period of time 
and may fail due to a concurrent operation.  The host VMM 
should retry TDH.VP.ENTER.  
TDX_SUCCESS  TDH.VP.ENTER launched or resumed TD VCPU operation 
(TDX non -root mode) – followed later by a TD exit.  Exit 
reason is in RAX bits 31:0.  
TDX_TDCX_NUM_INCORRECT    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 260 of 329 
TDX_TSC_ROLLBACK   
TDX_VCPU_ASSOCIATED   
November 2023  . Page 261 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.66.  TDH.VP.FLUSH Leaf  
Flush the address translation caches and cached TD VMCS associated with a TD VCPU on the current logical processor.  
Table 5.270:  TDH.VP.FLUSH  Input Operands Definition  
Must be 0  
RCX The physical address of a TDVPR page  (HKID bits must be 0)  
 
Table 5.271:  TDH.VP.FLUSH  Output Operands Definition  5 
 
vary.  
TDH.VP.FLUSH  flushes the address translation caches and cached TD VMCS associated with a TD VCPU on the current LP.  10 
It then marks the VCPU as not associated with any LP.  
Table 5.272:  TDH.VP.FLUSH  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDVPR  page  TDVPS  RW Opaque  4KB Exclusive  Shared  Shared  
Implicit  N/A HPA  TDR  page  TDR  R Opaque  N/A Shared  N/A N/A 
 15 
2. TDR. LIFECYCLE_STATE  is TD_KEYS_CONFIGURED.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 262 of 329 
Intel TDX Application Binary Interface (ABI) Reference  3. The current VCPU must be currently  associated with the current LP.  
If the above checks pass, the function does  the following:  
4. For each L2 VM:  
4.1. Flush the TLB context and extended paging structure (EPxE) caches associated with the L2 VM using INVEPT 
single -context invalidation (type 1).  5 
4.2. Flush the cached L2 VMCS content to TDVPS using VMCLEAR.  
5. Flush the TLB context and extended paging structure (EPxE) caches associated with the TD  using INVEPT single -
context invalidation  (type 1).  
6. Flush the cached TD VMCS  content to TDVPS using VMCLEAR.  
7. Mark the current VCP U as not associated with any LP.  10 
8. Atomically decrement (using LOCK XADD) the associated VCPUs counter (TDCS.NUM_ASSOC_VCPUS).  
Table 5.273:  TDH.VP.FLUSH Completion Status Codes (Returned in RAX) Definition  
TDX_ LIFECYCLE_STATE_ INCORRECT   
TDX_SUCCESS  TDH.VP.FLUSH  is successful . 
TDX_VCPU_NOT_ASSOCIATED   
November 2023  . Page 263 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.67.  TDH.VP.INIT Leaf  
Initialize the saved state of a TD VCPU . 
Operands  
Table 5.274:  TDH.VP.INIT In put Operands Definition  
May be 0 or 1  
RDX  Initial value of the guest TD VCPU RCX  
R8 If the version number provided in RAX[23:16] is 0, R8 is ignored.  
Else, R8 provides the following information:  
31:0  X2APIC_ID  VCPU’s virtual x2APIC ID  
63:32  Reserved  Must be 0  
 5 
Table 5.275:  TDH.VP.INIT Out put Operands Definition  
Other  Unmodified

Operands  
May be 0 or 1  
 5 
 
TDH.VP.INIT execution time may be longer than most TDX module interface functions execution time.  No interrupts 
(including NMI and SMI) are processed by the logical processor during that time.  10 
vary.  
TDH.VP.INIT initialize s the saved state of a VCPU in the TDVPR and TDPX pages.  
Enumeration:  TDH.VP.INIT’s support of version 1 or higher is enumerated by TDX_FEATURES0.TOPOLOGY_ENUM 15 
(bit 20), readable by TDH.SYS.RD* (see 3.3.3.1 ), being set to 1.  If not supported, calling TDH.VP.INIT 
with a version number higher than 0 returns a TDX_OPERAND_INVALID(RAX) status.  
VCPU Association : TDH.VP.INIT associates the target TD VCPU with the current LP – for details, see the [ TDX Module 
November 2023  . Page 264 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.276:  TDH.VP.INIT Operands Information Definition  
Explicit/  
1GB  
Implicit  N/A HPA  TDR page  TDR  R Opaque  4KB Shared  N/A N/A 
 
5. The number of pages allocated to this TDVPS is correct.  
6. The TD VCPU has not been initialized (by TDH.VP.INIT) and is not being torn down (TDVPS. VCPU_ STATE is 10 
7. Atomically increment the TD’s VCPU counter (TDCS.NUM_VCPUS), and check that maximum number of VCPUs 
(TDCS.MAX_VCPUS) has not been exceeded.  
8. Assign VCPU_ID, a unique sequential identifier to the VCPU.  
If passed:  
9. Initialize the VCPU state fields in the logical TDVPS structure (TDVPR and TDCX  pages).  
10. Associate the VCPU with the current LP and update the VMCS physical pointers and HKID execution control with the 
TD’s HKID.  20 
11. Set the TDVPS.LAST_TD_EXIT to  ASYNC _FAULT  since the first TD entry is the same as TD entry following an 
asynchronous fault -like TD exit.  
Table 5.277:  TDH.VP.INIT Completion Status Codes (Returned in RAX) Definition  
TDX_MAX_VCPUS_EXCEEDED   
November 2023  . Page 265 of 329 
TDX_SUCCESS  TDH.VP.INIT is successful.  
November 2023  . Page 266 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.68.  TDH.VP.RD Leaf  
Read a VCPU -scope metadata fields ( control structure field ) of a TD.  
Table 5.278:  TDH.VP.RD In put Operands Definition  
must be 0.  
For TDH.VP.RD version 1 or higher, a value of -1 is a special case:  it is not a valid field identifier; in 
this case the first readable field identifier is returned in RDX.  
 
Table 5.279:  TDH.VP.RD Out put Operands Definition  5 
RDX  For TDH.VP.RD version 0, RDX is unmodified.  
For TDH.VP.RD version 1 or higher:  
R8 Field content  
 
vary.  
TDH.VP.RD reads a TDVPS field, given its field code .  Reading is subject to the field’s readability (per the TD’s 10 
ATTRIBUTES.DEBUG bit).  
host VMM to dump the host readable VCPU metadata.  To read all the available fields, the host VMM can invoke 
TDH.VP.RD in a loop,  starting with field identifier -1 as an input, until RDX returns -1.  A status code of 
TDX_METADATA_FIELD_SKIP indicates that the returned value is not applicable . 15  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 267 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Enumeration:  Availability of TDH. VP.RD version 1 is enumerated by TDX_FEATURES0.ENHANCED_METADATA (bit 
3), readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDH.VP.RD with a version number 
VCPU Association : TDH.VP.RD associates the target TD VCPU with the current LP.  This requires that the VCPU will not 
be associated with another LP – for details, see the [ TDX Module Base Spec ]. 5 
Table 5.280:  TDH.VP.RD  Operands Information Definition  
Explicit/  
1GB  
Explicit  RCX HPA  TDVPR  page  TDVPS  RW Opaque  4KB Shared  Shared  Shared  
 
In addition to the memory operand checks per the table above, the function checks the following:  10 
4. The TD must have been initialized (TDR.NUM_TDCX is the required number and TDCS.OP_STATE is  not 
UNALLOCATED nor UNINITIALIZED).  15 
5. The provided field code is valid . 
6. The provided TDVPS field is readable per the TD’s debug attribute (TDCS.ATTRIBUTES.DEBUG).  
7. Associate the VCPU with the current LP, and update TD VMCS  using the algorithm described in 5.2.1 . 
8. Read the control structure field using the algorithm described in 5.2.2.1 . 
Table 5.281:  TDH.VP.RD Completion Status Codes (Returned in RAX) Definition  
identifier of the next field to be read, if any.

resolved by retrying the operation.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 268 of 329 
TDX_SUCCESS  TDH.VP.RD is successful.  
November 2023  . Page 269 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.3.69.  TDH.VP.WR Leaf  
Write a VCPU -scope metadata field ( control structure field ) of a TD.  
Table 5.282:  TDH.VP.WR Input Operands  Definition  
Must be 0  
The LAST_ ELEMENT_IN_FIELD and LAST_FIELD_IN_SEQUENCE  component s of the field identifier 
must be 0.  
WRITE_MASK_VALID , INC_SIZE , CONTEXT_CODE and ELEMENT_SIZE_CODE  components of the field 
R8 64b value to write to the field  
 
Table 5.283:  TDH.VP.WR Out put Operands Definition  5 
 
vary.  
TDH.VP.WR writes a TDVPS field, given its field code .  The value (R8) is  written as specified by the write mask (R9).  Writing 10 
is subject to the field’s internal write mask  (per the TD’s ATTRIBUTES.DEBUG bit) .  Writing of specific fields is also subject 
to additional rules as detailed in 4.2. 
Table 5.284:  Metadata Field Write Rules  
TDH.VP.WR returns the previous content of the field masked by the field’s readability (per the TD’s ATTRIBUTES.DEBUG 
bit). 15  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 270 of 329 
Intel TDX Application Binary Interface (ABI) Reference  VCPU Association : TDH.VP.WR associates the target TD VCPU with the current LP.  This requires that the VCPU will not 
be associated with another LP – for details, see the [ TDX Module Base Spec ]. 
Table 5.285:  TDH.VP.WR  Operands Information Definition  5 
Explicit/  
1GB  
 
3. The TD keys are configured on the hardware (TDR. LIFECYCLE_STATE  is TD_KEYS_ CONFIGURED).  10 
UNALLOCATED nor UNINITIALIZED ). 
6. The provided TDVPS field is writable per the TD’s debug attribute (TDCS.ATTRIBUTES.DEBUG).  
7. Associate the VCPU with the current LP, and update TD VMCS using the algorithm described in 5.2.1 . 
If passed:  
8. Write the control structure field and return  its old value, using the algorithm described in 5.2.2.2 . 
8.1. Writes of some fields are subject to rules, as detailed per field in 4.2 – e.g., the value of fields that contain 
Shared physical address, such as the Shared EPT Pointer, must have a Shared HKID value and must comply with 20 
some alignment rules.  
8.2. In most cases, writes of guest state fields are subject to the same rules as if the write is done by the guest itself 
– e.g., writing to guest CR4 is subject to the rules described in the [ TDX Module Base Spec ].  If the write 
operation is invalid , TDH.VP.WR fails and returns a proper error code.  
8.3. In debug mode (ATTRIBUTES.DEBUG  == 1), there are some TDVPS fields where the TDH.VP.WR does not check 25 
whether the written values are architecturally valid .  It is the responsibility of the host VMM, and failing to do 
so will later cause a VM entry failure leading to a fatal shutdown of the Intel TDX module.  The security of any 
guest TD is not impacted.  
8.4. In other cases, in debug mode (ATTRIBUTES.DEBUG  == 1), TDH.VP.WR allows setting of TDVPS fields to values 
that may impact the correct operation of the TD under debug.  It is the responsibility of the host VMM to take 30 
this into consideration.  
• TDH.VP.WR is allowed to enable BTM by setting guest IA32_DEBUGCTL[7:6] to 0x1.  
• TDH.VP.WR is allowed to modify the state of IA32_DEBUCTL[13] (ENABLE_UNCORE_PMI).  
• TDH.VP.WR is allowed to enable VM exits on exceptions other than MCE by setting the TD VMCS exception 
bitmap execution control.  The Intel TDX module does not take this into account when handling VM exits 35 
that occur during event delivery.  
Table 5.286:  TDH.VP.WR Completion Status Codes (Returned in RAX) Definition  
TDX_METADATA_FIELD_ID_INCORRECT    Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 271 of 329 
TDX_SUCCESS  TDH.VP.WR  is successful . 
TDX_TD_VMCS_FIELD_NOT_INITIALIZED   
TDX_TDVPS_FIELD_NOT_WRITABLE   
November 2023  . Page 272 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4. Guest -Side (T DCALL ) Interface  Functions  
The T DCALL  instruction causes a VM exit to the Intel TDX module .  It is used to call guest -side Intel TDX functions, either 
local or a TD exit to the host VMM, as selected by RAX.  
5.4.1.  TDCALL  Instruction (Common)  
This section describes the common functionality of TDCALL.  Leaf functions are described in the following sections.  As 5 
used by the  Intel TDX module , TDCALL  is allowed  only in 64b mode.  
Table 5.287:  TDCALL In put Operands Definition  
RAX  Leaf and version numbers, as defined in  the [ TDX Module Base Spec ].  See Table 5.289 below  
for TDCALL leaf numbers.  
15:0  Leaf Number  Selects the TDCALL interface function  
23:16  Version Number  Selects the TDCALL interface function version  
Other  See individual TDCALL leaf functions . 
 
Table 5.288:  TDCALL Out put Operands Definition  
RAX  Instruction return  code , indicating the outcome of execution of the instruction  – see the [ TDX 
 10

 10 
Table 5.289:  TDCALL  Instruction Leaf Numbers  Definition  
Leaf 
0 TDG.VP.VMCALL  Call a host VM service  
1 TDG.VP.INFO  Get TD execution environment information  
2 TDG.MR.RTMR.EXTEND  Extend a TD run -time measurement register  
3 TDG.VP.VEINFO.GET  Get Virtualization Exception Information for the recent #VE exception  
4 TDG.MR.REPORT  Creates a cryptographic report of the TD  
5 TDG.VP.CPUIDVE.SET  Control delivery of #VE on CPUID instruction execution  
6 TDG.MEM.PAGE.ACCEPT  Accept a pending private page into the TD  
7 TDG.VM.RD  Read a TD -scope metadata field  
8 TDG.VM.WR  Write a TD -scope metadata field  
9 TDG.VP.RD  Read a VCPU -scope metadata field  
10 TDG.VP.WR  Write a VCPU -scope metadata field  
11 TDG.SYS.RD  Read a TDX Module global -scope metadata field  
12 TDG.SYS.RDALL  Read all gust -readable TDX Module global -scope metadata fields  
18 TDG.SERVTD.RD  Read a target TD metadata field  
20 TDG.SERVTD.WR  Write a target TD metadata field  
22 TDG.MR.VERIFYREPORT  Verify a cryptographic report of a TD, generated on the current platform  
23 TDG.MEM.PAGE.ATTR.RD  Read the GPA mapping and attributes of a TD private page  
24 TDG.MEM.PAGE.ATTR.WR  Write the attributes of a private page  
25 TDG.VP.ENTER  Enter L2 VCPU operation   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 273 of 329 
26 TDG.VP.INVEPT  Invalidate cached EPT translations for selected L2 VMs  
27 TDG.VP.INVGLA  Invalidate cached translations for selected pages in an L2 VM  
 
vary.  
This section  describes how TDCALL leaf functions are implemented by the Intel TDX module . 5 
On VM exit, the Intel TDX module  performs the following checks:  
1. If the CPU mode is not 64b  ((IA32_EFER.LMA == 1)  && (CS.L == 1)) , the Intel TDX module  injects a #GP(0) fault into 
the guest TD . 
2. If the leaf number in RAX is not supported by the Intel TDX module , it returns a TDX_OPERAND_INVALID(0) status 
code in RAX . 10 
If all checks pass, the Intel TDX module  calls the leaf function  according to the leaf number in RAX  – see the following 
Table 5.290:  TDCALL  Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDCALL  is successful . 
TDX_OPERAND_INVALID  Invalid  leaf number  
Other  See individual leaf functions  
November 2023  . Page 274 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.2.  TDG.MEM.PAGE.ACCEPT  Leaf  
Accept a pending private page and initialize it to all-0 using the TD ephemeral private key . 
Table 5.291:  TDG.MEM.PAGE.ACCEPT  Input Operands Definition  
RAX  TDCALL instruction leaf number and version, see 5.4.1  
Must be 0  
2:0 Level  Level of the Secure EPT leaf entry that maps the private page to be 
accepted:   either 0 (4KB) or 1 (2MB) – see  3.6.1 . 
accepted  
 
Table 5.292:  TDG.MEM.PAGE.ACCEPT  Output Operands Definition  5 
RAX  TDCALL instruction return  code – see 5.4.1  
 
vary.  
TDG.MEM.PAGE.ACCEPT a ccept s a pending private page, previously added by TDH.MEM.PAGE.AUG , into the TD.  It 10 
initialize s the page to 0.   If page attributes have been set by the guest TD, using TDG.MEM.PAGE.ATTR.WR, while the 
page was pending, they become effective when the page is accepted.  
SEPT Mapping Size Considerations  
In most cases, the guest TD is unaware of how TD private pages are mapped by the host VMM in SEPT.  However, 
TDG.MEM.PAGE.ACCEPT operation specifies a page mapping size and may fail if the specified size is different than the 15 
actual mapping size.  
• If the page is mapped at a lower level than requested, the function returns TDX_PAGE_SIZE_MISMATCH.  The guest 
may re -invoke TDG.MEM.PAGE.ACCEPT specifying a 4KB page size.  
• If the page is mapped at a higher level than requested, this results in an E PT violation  TD exit, with extended exit 
qualification indicating  the error SEPT entry level and state, and the guest -requested mapping level.  The host VMM 20 
is expected to demote the page, then re -enter the guest TD so TDG.MEM.PAGE.ACCEPT is re -invoked.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 275 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Other Conditions that Prevent Page Acceptance  
• If the page has already been accepted, the function returns TDX_PAGE_ALREADY_ACCEPTED . 
• If the page is not PENDING nor PENDING_EXPORTED_DIRTY, this result in an E PT violation  TD exit, with extended exit 
qualification indicating  the error SEPT entry level and state, and the guest -requested accept level.  
Interruptibility  If, during its execution, TDG.MEM.PAGE.ACCEPT detects that an external interrupt is pending, it may 5 
resume the guest TD with the CPU state unmodified.  The progress so far is recorded in the page’s 
Secure EPT entry.  This allows the external interrupt to be recognized, causing a TD exit or a posted 
interrupt delivery.  Typically, TDG.MEM.PAGE.ACCEPT will be re -invoked and continue its work.  Guest 
TD software is not directly involved.  
Table 5.293 TDG.MEM.PAGE.ACCEPT  Operands Information Definition  
Explicit/  
Check  Concurrency 
Restrictions  
Explicit  RCX GPA  TD private page  Blob  RW Private  212+9*L evel 
Bytes  None  
Implicit  N/A N/A TDR page  TDR  None  Opaque  N/A Shared (i) 
Implicit  N/A N/A TDCS structure  TDCS  R Opaque  N/A Shared (i) 
Implicit  N/A N/A TDVPS structure  TDVPS  RW Opaque  N/A Shared (i) 
Implicit  N/A N/A Secure EPT tree  N/A RW Private  N/A None  
Implicit  N/A GPA  Secure EPT entry  SEPT Entry  RW Private  N/A Exclusive (h) 
 
TDG.MEM.PAGE.ACCEPT checks the memory operands per the table above when applicable during its flow.  The text 
below does not explicitly mention those checks, except when necessary.  15 
In addition to the memory operand checks per the table above, the function does the following (no specific order is 
implied):  
1. Walk the Secure EPT based on the GPA operand   and requested level.   The walk is successful if arrived at a leaf entry 
whose state is PENDING.  In case of error, return a status code or TD exit as described in the [ TDX Module Base Spec ]. 
If successful, do the following:  20 
2. Loop until the whole page has been initialized, or until interrupted:  
2.1. Initialize the next 4KB chunk to 0 using the TD’s ephemeral private HKID and direct writes (MOVDIR64B).  
2.2. If not done and there is a pending interrupt, abort TDG.MEM.PAGE.ACCEPT and resume the guest TD without 
updating RIP and any GPR.   
If done initializing the page, do the following:  25 
3. Set the SEPT  entry to MAPPED . 
4. For each L2 VM where the page is mapped:  
4.1. Walk the L2 Secure EPT based on the GPA operand and  find the L2 SEPT entry for the page  to be accepted.  
4.2. Restore the L2 SEPT entry attributes.  
4.3. Set the L2 SEPT entry state to L2_MAPPED.  30 
Table 5.294:  TDG.MEM.PAGE.ACCEPT  Completion Status Codes (Returned in RAX) Definition  
November 2023  . Page 276 of 329 
TDX_OPERAND_BUSY  Operation encountered a busy operand, indicated by the lower 32 bits of 
the status.  In many cases, this can be resolved by retrying the operation.  
Specifically, it may indicate that a concurrent TDG.MEM.PAGE.ACCEPT is 
using the same Secure EPT entry  
TDX_PAGE_ALREADY_ACCEPTED   
TDX_PAGE_SIZE_MISMATCH  Requested  page size  is 2MB, but the page GPA is not mapped at 2MB size

TDX_PAGE_SIZE_MISMATCH  Requested  page size  is 2MB, but the page GPA is not mapped at 2MB size  
TDX_SUCCESS  TDG.MEM.PAGE.ACCEPT is successful.  
 
November 2023  . Page 277 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.3.  TDG.MEM.PAGE.ATTR.RD Leaf  
Read the GPA mapping and attributes of a TD private page.  
Table 5.295:  TDG.MEM.PAGE.ATTR.RD Input Operands Definition  
RAX  Leaf and Version  TDCALL instruction leaf number and version,  see 5.4.1  
Must be 0  
RCX GPA  Guest physical address  
 
Table 5.296:  TDG.MEM.PAGE.ATTR.RD Output Operands Definition  5 
RAX  STATUS  TDCALL instruction return code – see 5.4.1  
RCX GPA_MAPPING  Actual GPA mapping of the page : 
2:0 LEVEL  Level of the Secure EPT leaf entry that maps the private 
page:   either 0 (4KB), 1 (2MB) or 2 (1GB) – see  3.6.1 . 
11:3  RESERVED  Reserved:  set to  0 
51:12  GPA  Bits 51:12 of the guest physical start address of the 
private page  
are always 0: 
Level 0 (EPTE):  None  
Level 1 (EPDE):  Bits 20:12  
Level 2 (EPDPTE):  Bits 29:12  
61:52 RESERVED  Reserved:  set to  0 
62 PENDING  Flags that the page is PENDING  
63 RESERVED  Reserved:  set to  0 
RDX  GPA_ATTR  Guest -visible p age attributes.  See the GPA_ ATTR  definition in 3.6.3 . 
 
November 2023  . Page 278 of 329 
Intel TDX Application Binary Interface (ABI) Reference  TDH.MEM.PAGE.ATTR.RD reads the GPA mapping and attributes of a TD private page.   Given a GPA (which can be 
anywhere within a page) it returns the actual mapping level – either  0 (4KB), 1 (2MB) or 2 (1GB)  – and the guest -readable 
attributes.  TDH.MEM.PAGE.ATTR.RD  can read the attributes of a PENDING page.  
GPA mapping level is exposed to the guest TD since page acceptance (TDH.MEM.PAGE.ACCEPT) and page attributes 
modifications and L2 page aliases management (TDH.MEM.PAGE.ATTR.WR) are done at mapping granularity.  5 
Enumeration:  Availability of TDG. MEM.PAGE.ATTR.RD is enumerated by TDX_FEATURES0.TD_PARTITIONING (bit 7), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.MEM.PAGE.ATTR.RD returns a 
EPT Violation:  If the requested GPA is not guest -readable and not pending acceptance, TDH.MEM.PAGE.ATTR.RD 
causes an EPT violation TD exit.  10 
of the Intel TDX Module API.  
Table 5.297 TDG.MEM.PAGE.ATTR.RD Memory Operands Information Definition  
Explicit/  
Implicit  Reg.  Addr. 
Explicit  RCX GPA  TD private page  Blob  RW Private  None  None  
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  N/A Shared(i)  
Implicit  N/A N/A Secure EPT tree  N/A R Private  N/A None  
Implicit  N/A N/A L2 Secure EPT tree s N/A RW Private  N/A None  
Implicit  N/A GPA  Secure EPT entr y SEPT Entry  R Private  N/A Exclusive(h)  
Implicit  N/A GPA  L2 Secure EPT entr ies SEPT Entry  RW Private  N/A Exclusive(i)  
 
TDG.MEM.PAGE.ATTR.RD checks the memory operands per the table above when applicable during its flow.  The text 15 
implied):  
1. Check that the requested GPA is  valid.  
2. Walk the L1 Secure EPT based on the GPA operand.  20 
2.1. The walk is successful if arrived at a leaf entry whose state is either guest accessible  (MAPPED , 
EXPORTED_DIRTY , *BLOCKEDW*) or pending but not blocked (PENDING, or PENDING_EXPORTED_*).  
2.2. Else, do an EPT violation TD exit . 
If successful, do the following:  
3. For each L2 page alias to the L1 SEPT entry:  25 
3.1. Walk that L2 VM’s SEPT and locate the page alias L2 SEPT leaf entry.  
3.2. Read the L2 SEPT entry and assemble  the returned attributes.   If the page is pending or blocked for writing, the 
L2 SEPT entry’s original access permission bits are read from their saved locations in the L2 SEPT entry.  
4. Return the page mapping and attributes.  
Completion Status Codes  30 
Table 5.298:  TDG.MEM.PAGE.ATTR.RD Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.MEM.PAGE.ATTR.RD is successful.  
November 2023  . Page 279 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.4.  TDG.MEM.PAGE.ATTR.WR Leaf  
Write  the attributes of a private page.   Create or remove L2 page aliases as required.  
Table 5.299:  TDG.MEM.PAGE.ATTR.WR Input Operands Definition  
Version  TDCALL instruction leaf number and version, see 5.4.1  
Must be 0  
RCX GPA_MAPPING  GPA mapping information:  
2:0 LEVEL  Level of the Secure EPT leaf entry that maps the private page:   
either 0 (4KB), 1 (2MB) or 2 (1GB) – see 3.6.1 . 
11:3  RESERVED  Reserved:  must be 0  
51:12  GPA  Bits 51:12 of the guest physical address of the private page  
must be 0:  
63:5 2 RESERVED  Reserved:  must be 0  
To avoid writing the attributes of a certain VM, all 16 attribute bits 
(GPA_ATTR_SINGLE_VM) for that VM  should be set to 0.  
Attribute bits for non -existent VMs must be 0.  
R8 ATTR_FLAGS  Attributes masks and invalidate EPT flags  
15:0  RESERVED  Must be 0  
30:16  ATTR_MASK1  A bit value of 1 indicates that the applicable attributes bit is 
to be written.   Otherwise, the attributes bit is unmodified.  
Must be 0 if the TD has no VM #1.  
31 INVEPT1  Invalidate EPT for L2 VM #1  
46:32  ATTR_MASK2  A bit value of 1 indicates that the applicable attributes bit is 
Must be 0 if the TD has no VM #2.  
47 INVEPT2  Invalidate EPT for L2 VM #2   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 280 of 329 
62:48  ATTR_MASK3  A bit value of 1  indicates that the applicable attributes bit is 
Must be 0 if the TD has no VM #3.  
63 INVEPT3  Invalidate EPT for L2 VM #3  
 
Table 5.300:  TDG.MEM.PAGE.ATTR.WR Output Operands Definition  
page:   either 0 (4KB), 1 (2MB) or 2 (1GB) – see 3.6.1 . 
51:12  GPA  Bits 51:12 of the guest physical start address of the private 
page  
RDX  GPA_ATTR  On success , if the attribute bits (GPA_ATTR_SINGLE_VM) for a specific VM were 0 on 
input, they remain unmodified.  For other VMs, RDX returns the u pdated guest -visible 
page attributes.  
In case of an error, RDX returns the current value of page attributes when possible.  If 
the current attributes for a certain VM have not been read, that VM’s attributes VALID 
bit returns 0.  
See the GPA_ ATTR  definition in 3.6.3 . 
 
vary.

page  
 
vary.  
TDH.MEM.PAGE.ATTR.WR writes the specified set of  attributes of a TD private page , including L2 page alias attributes .  
Only the bits selected by the attributes mask are update d.  The private page can be either writable by the TD (MAPPED 
or EXPORTED_DIRTY) or pending acceptance (PENDING or PENDING_EXPORTED_DIRTY).   If the page is pending  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 281 of 329 
Intel TDX Application Binary Interface (ABI) Reference  acceptance, the written attributes will become effective when the page is later accepted by the guest TD, using 
TDG.MEM.PAGE.ACCEPT.  
TDH.MEM.PAGE.ATRR.WR ignores any VM’s GPA attributes set whose VALID bit is 0.  
TDH.MEM.PAGE.ATTR.WR creates or removes L2 page aliases as required:  
• If any of the requested L2 attributes VALID bit is set, and the R, W, Xs , Xu and PWA  bits combination has a legal, non - 5 
0 value, then if the L2 page alias does not exist, it is created.   The rules for checking the legal combination of attributes 
bits are described in 3.6.3.1 . 
• If any of the requested L2 attributes VALID bit is set, and the R, W, Xs , Xu and PWA bits are all 0, then if the L2 page 
alias exists, it is removed.  
Note : For the above operation s, the Xu and PWA bits are always considered, regardless of the L2 VMCS setting of the 10 
“mode -based execute control for EPT”  (MBEC)  and “EPT paging -write control” VM-execution control s. 
Enumeration:  Availability of TDG. MEM.PAGE.ATTR.WR is enumerated by TDX_FEATURES0.TD_PARTITIONING (bit 7), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.MEM.PAGE.ATTR.WR returns a 
SEPT Mapping Size Considerations  15 
TDG.MEM.PAGE.ATTR.WR operation specifies a page mapping size and may fail if the specified size is different than the 
may re -invoke TDG.MEM.PAGE.ATTR.WR specifying the actual mapping size as returned in RCX.  20 
qualification indicating  the error SEPT entry level and state, and the guest -requested mapping level.  The host VMM 
is expected to demote the page, then re -enter the guest TD so TDG.MEM.PAGE.ATTR.WR is re -invoked.  
Other  Conditions that P revent Page Attributes Modifications  
• If the page is not guest -writable and is not pending, this result s in an E PT violation  TD exit , indicating a failed write 25 
• If an L2 SEPT walk fails, meaning there’s a missing non -leaf L2 SEPT page, the operation depends on the setting of 
the host writable TDCS field VM_CTLS, which is an array of 4 bitmaps, one per VM (only L2 VMs are applicable).  Bit 
0 controls the operation on L2 SEPT walk fails in TDCALL flows : 
o The default value of 0 means that a TDX_L2_SEPT_WALK_FAILED status is returned to the L1 VMM.  30 
o If the value is 1, the TDX module does an EPT violation TD exit , indicating a failed write operation  exit, with 
extended exit qualification indicating  the error L2 SEPT level and VM index .  The host VMM may then add the 
missing L2 SEPT page using TDH.MEM.SEPT.ADD.  
In any of the above cases, the page attributes are not modified.  
To understand the table and text below, please refer to the [ TDX Module Base Spec ] chapter discussing general aspects 35 
Table 5.301 TDG.MEM.PAGE.ATTR.WR Memory Operands Information Definition  
Explicit/  
Explicit  RCX GPA  TD private page  Blob  RW Private  212+9*Level 
Bytes  None  
Implicit  N/A N/A L1 Secure EPT tree  N/A R Private  N/A None  
Implicit  N/A GPA  L1 Secure EPT entr y SEPT Entry  RW Private  N/A Exclusive(h)   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 282 of 329 
 
TDG.MEM.PAGE.ATTR.WR checks the memory operands per the table above when applicable during its flow.  The text 
implied):  5 
1. Check that the requested GPA and level are  valid.  
2. Check that the requested page attributes and attributes mask operands are valid.  
3. Walk the L1 Secure EPT based on the GPA operand and requested level.  
3.1. The walk is successful if arrived at a leaf entry at the request level, whose state is MAPPED , EXPORTED_DIRTY , 
PENDING or PENDING_EXPORTED_DIRTY.  10 
3.2. Else, if  the page is not mapped at the requested level, return a TDX_ PAGE_SIZE_MISMATCH status.  
3.3. Else, do an EPT violation TD exit , indicating a failed write operation.  
4.1. If an L2 page alias exists:  15 
4.1.1.  Walk that L2 VM’s SEPT and locate the page alias L2 SEPT leaf entry.  
4.1.2.  If the GPA_ATTR’s VALID bit is 1, and RWXsXu bits combined value is a valid, non -0 value, update the L2 
SEPT entry.  If the page is pending, then the L2 SEPT entry’s access permission bits remain 0; their original 
values are stored in their saved locations  in the L2 SEPT entry.  
4.1.3.  If the GPA_ATTR’s VALID bit is 1, and RWXsXu bits combined value is 0, remove the alias by setting the 20 
L2 SEPT entry state to L2_FREE.   Update the L1 SEPT entry to indicate a page alias exists to this page.  
4.2. Else (L2 page alias does not exist), if the GPA_ATTR’s VALID bit is 1, and RWXsXu bits combined value is a valid, 
non-0 value:  
4.2.1.  Walk that L2 VM’s SEPT and locate the page alias L2 SEPT leaf entry.  
4.2.2.  If failed, do an EPT violation TD exit , indicating a failed write operation.  25 
If passed:  
4.2.3.  Create the page alias by writing the SEPT entry with the page HPA and the requested set of attributes 
masked by the attributes mask and  setting its state to L2_MAPPED or L2_BLOCKED, depending on the 
L1 SEPT entry state.  If the page is pending, then the L2 SEPT entry’s access permission bits remain 0; 
their original values are stored in their saved locations in the L2 SEPT entry.  30 
4.2.4.  Update the L1 SEPT entry to indicate a page alias exists to this page.  
Table 5.302:  TDG.MEM.PAGE.ATTR.WR Completion Status Codes (Returned in RAX) Definition  
TDX_PAGE_ATTR_INVALID  The combination of page attributes to be set, after considering  the 
requested attributes, the requested attributes mask and the current 
page attributes, is invalid.  
TDX_PAGE_SIZE_MISMATCH  Requested page size does not match its GPA mapping size  
TDX_SUCCESS  TDG.MEM.PAGE.ATTR.WR is successful.  
November 2023  . Page 283 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.5.  TDG.MR.REPORT  Leaf  
TDG.MR.REPORT c reates a TDREPORT_STRUCT  structure that contains the measurements/configuration information of 
the guest TD that called the function, measurements/configuration information of the Intel TDX module  and a 
REPORTMACSTRUCT . 
Table 5.303:  TDG.MR.REPORT In put Operands Definition  5 
Must be 0  
RCX Guest physical address of newly created report structure.  
• For version 0, the buffer must be aligned on 1024B.  
RDX  64B-aligned guest physical address of additional data to be signed  
7:0 Report sub type  Must be 0  
63:8  Reserved  Reserved:  must be 0  
 
Table 5.304:  TDG.MR.REPORT Out put Operands Definition  
 
vary.

Must be 0  
 
vary.  
This function  creates a TDREPORT_STRUCT  structure that contains the measurements/configuration information of the 
guest TD that called the function, measurements/configuration information of the Intel TDX module  and a 
REPORTMACSTRUCT.  The REPORTMACSTRUCT is integrity -protected with a MAC , and it contains the hash of the 
measurements and configuration as well as additional REPORTDATA provided by the TD software.  15 
The created TDREPORT_STRUCT  version  (REPORTTYPE.VERSION) is the lowest version that contains  all the TD’s reported 
information : 
• If any service TD has been bound or pre -bound (i.e., SERVTD_HASH is not 0), then the version is 1.  
• Else, the version is 0.  
Additional REPORTDATA, a 64 -byte value, is provided by the guest TD to be included in the TDG.MR.REPORT.  20 
Note:  Although not enforced by TDG.MR.REPORT, the guest TD should normally place REPORTDATA in private memory 
to help ensure secure report generation.  
November 2023  . Page 284 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.305:  TDG.MR.REPORT Operands Information Definition  
Explicit/  
Semantics  Align Check  Concurrency 
Explicit  RCX GPA  Output report  TDREPORT_STRUCT  RW Private/ 
Shared  Version 0: 
1024B  None  
Explicit  RDX  GPA  Input report data  REPORTDATA  R Private/ 
Shared  64B None  
Implicit  N/A N/A TDCS structure  TDCS  R Opaque  N/A Shared(i)  
Implicit  N/A N/A TDCS.RTMR  SHA384_HASH  N/A Opaque  N/A Shared  
Implicit  N/A N/A TDVPS structure  TDVPS  None  Opaque  N/A Shared (i) 
 
In addition to the memory operand checks per the table above, the function checks the following conditions (no specific 
order is implied):  
1. R8 must specify report sub type 0.  5 
If passed:  
2. Determine REPORTTYPE.VERSION:  
2.1. If there is any bound or pre -bound service TDs, then REPORTTYPE.VERSION is 1.  
2.2. Else REPORTTYPE.VERSION is 0.  
3. Assemble a REPORTTYPE  structure . 
4. Assemble the output report’s TDINFO _STRUCT  base fields from the TDCS reported fields (ATTRIBUTES, XFAM, MRTD, 
MRCONFIGID, MROWNER, MROWNERCONFIG and RTMRs).  
5. If REPORTTYPE.VERSION is 0, add the SERV_TD hash field as 0, and the RESREVED field.  
6. If REPORTTYPE.VERSION is 1, add the SERV_TD hash field  from TDCS, and the RESREVED field.  15 
7. Calculate a SHA384 hash over TDINFO  (size depends on REPORTTYPE.VERSION).  
8. Execute SEAMDB_REPORT to complete the output report, based on the input report data, the TDINFO  hash 
calculated above, the report type structure and the SEAMDB entry’s index/nonce pair of the TDR.  
9. If SEAMDB_REPORT returns an error (unrecognized index/nonce pair), then mark the TD state as FATAL  and do a TD 
exit with a TDX_NON_RECOVERABLE_TD_CORRUPTED_MD  status code.  20 
10. Write the output report to memory.  
Table 5.306:  TDG.MR.REPORT Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.MR.REPORT  is successful . 
  25  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 285 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.6.  TDG.MR.RTMR.EXTEND  Leaf  
Extend a TDCS.RTMR measurement register.  
Table 5.307:  TDG.MR.RTMR.EXTEND  Input Operands Definition  
Must be 0  
RCX 64B-aligned guest physical address of a 48B extension data  buffer  
RDX  Index of the measurement register to be extended  
 
Table 5.308:  TDG.MR.RTMR.EXTEND  Output Operands Definition  5 
 
vary.  
This function  extends one of the RTMR measurement registers in TDCS with the provided extension data in memory.  10 
Table 5.309 TDG.MR.RTMR.EXTEND  Operands Information Definition  
Explicit/  
Explicit  RCX GPA  EXTEND_DATA  Blob  R Private  64B None  
Implicit  N/A N/A TDCS structure  TDCS  RW Opaque  N/A Shared (i) 
Implicit  N/A N/A TDCS.RTMR  SHA384_HASH  N/A Opaque  N/A Exclusive  
Implicit  N/A N/A TDVPR page  TDVPS  None  Opaque  N/A Shared (i) 
 
In addition to the memory operand checks per the table above, the function checks the following conditions (no specific 15 
1. RDX must contain a valid RTMR index .  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 286 of 329 
2. Extend  the RTMR indexed by RDX with the extension data .  Extension is done by calculating SHA384 hash over a 96B 
buffer , composed as follows:  
o Bytes 0 through 47 contain the current RTMR value.  
o Bytes 48 through 95 contain the extension data.  5 
Table 5.310:  TDG.MR.RTMR.EXTEND  Completion Status Codes (Returned in RAX) Definition  
TDX_OPERAND_BUSY  Operation encountered a busy operand, indicated by the lower 32 bits of the 
status.  In many cases, this can be resolved by retrying the operation.  
TDX_SUCCESS  TDG.MR.RTMR.EXTEND is successful.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 287 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.7.  TDG.MR. VERIFYREPORT  
Verify a cryptographic REPORTMACSTRUCT that describ es the contents of a  TD, to determ ine that it was created on the 
current TEE on the current platform.  
Table 5.311:  TDG.MR.VERIFYREPORT Input Operands Definition  
Must be 0  
RCX 256B-aligned guest physical  address of the REPORTMACSTRUCT to be verified.  
 5 
Table 5.312:  TDG.MR.VERIFYREPORT Output Operands Definition  
 
vary.  10 
TDG.MR.VERIFYREPORT c omputes a MAC over  the provided  REPORTMACSTRUCT structure ; it then  checks that the  
computed value is the same as the MAC field of that structure.  
Enumeration : Availability of TDG. MR.VERIFYREPORT is enumerated by TDX_FEATURES0.LOCAL_ATTESTATION (bit 8), 
readable by TDG.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.MR.VERIFYREPORT returns a 
Retry on Failure : As described in the [Base Spec], there can be cases where report verification fails due to, e.g., microcode 
update or migration of the reporting TD and the verifying TD to another platform.  In such cases it is 
recommended that a fresh report will be generated by the reporting TD, using TDG.MR.REPORT, and 
that TDG.MR.VERIFYREPORT will be called again . 
Table 5.313:  TDG.MR.VERIFYREPORT Operands Information Definition  
Explicit/  
Explicit  RCX GPA  Input report  REPORTMACSTRUCT  R Private  256B  None  
Implicit  N/A N/A TDR page  TDR  None  Opaque  N/A Shared(i)  
Implicit  N/A N/A TDCS.RTMR  SHA384_HASH  N/A Opaque  N/A Shared

Explicit/  
Implicit  N/A N/A TDVPS structure  TDVPS  None  Opaque  N/A Shared(i)   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 288 of 329 
The function performs the memory operand checks per the table above.  
If passed, the function does the following:  
1. Calculate MAC over the input REPORTMACSTRUCT fields that are included in the MAC calculation.  
2. Compare the calculated MAC to the REPORTMACSTRUCT.MAC field are return a proper status.  5 
Table 5.314:  TDG.MR.VERIFYREPORT Completion Status Codes (Returned in RAX) Definition  
TDX_INVALID_CPUSVN  See the above note about retrying the operation.  
TDX_INVALID_REPORTMACSTRUCT  See the above note about retrying the operation.  
TDX_SUCCESS  TDG.MR.VERIFYREPORT  is successful . 
 
November 2023  . Page 289 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.8.  TDG.SERVTD.RD Leaf  
As a service TD, read a metadata field (control structure field) of a target TD.  
Table 5.315:  TDG.SERVTD.RD Input Operands  Definition  
Must be 0  
must be 0.  
WRITE_MASK_VALID, INC_SIZE, CONTEXT_CODE and ELEMENT_SIZE_CODE components of the field 
A value of -1 is a special case:  it  is not a valid field identifier; in this case the first readable field 
R10 Target TD’s TD_UUID bits 63:0  
R11 Target TD’s TD_UUID bits 127:64  
R12 Target TD’s TD_UUID bits 19 1:128  
R13 Target TD’s TD_UUID bits 255:19 2 
 
Table 5.316:  TDG.SERVTD.RD Output Operands Definition  5 
RDX  RDX returns the next readable field identifier.  A value of -1 indicates no next field identifier is 
available.  
If the input field identifier was -1, RDX returns the first readable field identifier.  In case of another 
error, RDX returns -1. 
R10 Updated target TD’s TD_UUID bits 63:0  – see the description below.  
R11 Updated target TD’s TD_UUID bits 127:64  – see the description below.  
R12 Updated target TD’s TD_UUID bits 19 1:128  – see the description below.  
R13 Updated target TD’s TD_UUID bits 255:19 2 – see the description below.  
November 2023  . Page 290 of 329 
vary.  
TDG. SERVTD .RD reads a metadata field (control structure field) of a target TD. 
Enumeration:  Availability of TDG. SERVTD.RD is enumerated by TDX_FEATURES0.SERVICE_TD (bit 2), readable by 5 
TDG.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.SERVTD.RD returns a 
TD_UUID Update:  TD_UUID is updated when the target TD is imported.  If the service TD binding to the target TD 
happened before the target TD was imported, the TD_UUID provided in R13:R10 may no longer be 
correct.  In this case, if the TD_UUID provided in R13:R10 is equal to the pre -import TD_UUID of 10 
the target TD, TDG.SERVTD.RD returns TDX_TARGET_UUID_MISMATCH status in RAX, and updates 
R13:R10 with the imported value of TD_UUID.  The called should retry the operation with the new 
TD_UUID.  
Cross -TD Traps:  Failure to access the metadata of the target TD may result in a cross -TD trap TD exit to the host 
VMM.  This TD exit is trap like, meaning it happens after TDG.SERVTD.RD has completed its 15 
operation.  On the following TDH.VP.ENTER, the host VMM may set a HOST_RECOVERABILITY_HINT  
flag, indicating that TDG.SERVTD.RD may be retried.  From the guest TD’s perspective, this flag 
appears in bit 60 of the status code returned in RAX.  See the [TDX Module Base Spec] for details.  
RDX returns the next host -side readable field identifier.  This may be used by the Service  TD to dump the target TD  
metadata  readable  by the Service TD .  To read all the available fields, the service  TD can invoke TDG. SERVTD .RD in a loop, 20 
that the returned value is not applicable.  
Table 5.317 TDG. SERVTD .RD Operands Information Definition  25 
Explicit/  
1GB  
page (from 
binding handle)  TDR  R Opaque  N/A Shared(h)  Shared(h)  Shared(h)  
Implicit  N/A N/A Service (this) TD’s 
TDR page  TDR  None  Opaque  N/A Shared (i) None  None  
TDCS structure  TDCS  R Opaque  N/A Shared(i)  None  None  
TDVPS structure  TDVPS  None  Opaque  N/A Shared(i)  Shared(i)  Shared(i)  
structure  TDCS  RW Opaque  N/A Shared(i)  None  None  
TDCS.OP_STATE  OP_STATE  RW Opaque  N/A Shared (h) N/A N/A 
Binding table   R Opaque  N/A Shared(h)  None  None  
Implicit  N/A N/A Target TD’s TD 
metadata  N/A R Opaque  N/A None  None  None   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 291 of 329 
If the memory operand checks , per the table above , pass:  
1. Based on the provided binding handle and the current (service) TD’s TD_UUID, calculate the target TD’s TDR HPA and 
binding slot number.  
2. Check that the calculated binding slot number does not exceed target TD’s the number of available slots11. 5 
3. Acquire access to the target TD’s TDR in a shared mode.  
3.1. If failed due to HOST_PRIORITY, do a TD exit.  
4. Check the t arget TD state : 
4.1. The target TD’s TDR page metadata in PAMT must be correct ( PT must be PT_TD R). 
4.2. The target TD is not in a FATAL state (TDR.FATAL is FALSE).  10 
4.3. The target TD keys are configured on the hardware (TDR. LIFECYCLE_STATE is TD_KEYS_CONFIGURED).  
4.4. The target TD’s TDCS pages must have been allocated (TDR.NUM_TDCX is the required number) . 
If passed:  
5. Check that the target TD’s TD_UUID is the same as specified.  
5.1. If failed, and the target TD’s PRE_IMPORT_UUID is the same as the specified TD_UUID, abort and return the 15 
current target TD’s TD_UUID.  
If passed:  
6. Check that the target TD’s binding slot’s SERVTD_BINDING_STATE  is BOUND.  
7. Calculate the current (service) TD’s TD_UUID and check it is equal to  the target TD’s binding slot’s SERVTD_UUID . 
8. Calculate the current (service) TD’s TDINFO_HASH and check it is equal to the target TD’s binding slot’s 20 
SERVTD_TDINFO_HASH.  
If passed:  
9. Read the control structure field using the algorithm described in 5.2.2.1 . 
Table 5.318:  TDG. SERVTD .RD Completion Status Codes (Returned in RAX) Definition  25 
TDX_OP_STATE_INCORRECT  This status code refers to the target TD.  Bit 60 
(HOST_RECOVERABILITY_HINT) contains a hint from the host 
VMM that the error condition has been resolved and the 
service TD can retry the operation.  
TDX_OPERAND_ADDR_RANGE_ERROR  This status code refers to the target TD.  Bit 60 
resolved by retrying the operation.

11 This value is a property of the TDX module and is the same for all TDs.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 292 of 329 
TDX_PAGE_METADATA_INCORRECT  This status code refers to the target TD.  Bit 60 
TDX_SERVTD_INFO_HASH_MISMATCH  This service TD5’s info hash doesn’t match the service TD 
info hash in the target TD’s binding information.  Bit 60 
service TD can retry the ope ration.  
TDX_SERVTD_NOT_BOUND  This service TD is not bound to the target TD.  Bit 60 
TDX_SERVTD_UUID_MISMATCH  This service TD5’s TD_UUID doesn’t match the service TD 
UUID in the target TD’s binding information.  Bit 60 
TDX_SUCCESS  TDG.SERVTD.RD is successful.  
TDX_TARGET_UUID_MISMATCH  The target TD’s TD_UUID value provided in R13:R10 doesn’t 
match the actual value.  
TDX_TARGET_UUID_UPDATED  The target TD’s TD_UUID value provided in R13:R10 doesn’t 
match the current actual value, but it does match the 
TD_UUID that target TD had before it was imported.  In this 
case, the current TD_UUID value is provided in R13:R10 , and 
the operation can be retried.  
TDX_TD_FATAL  This status code refers to the target TD.  Bit 60 
TDX_TD_KEYS_NOT_CONFIGURED  This status code refers to the target TD.  Bit 60 
TDX_TDCS_NOT_ALLOCATED  This status code refers to the target TD.  Bit 60 
November 2023  . Page 293 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.9.  TDG.SERVTD.WR Leaf  
As a service TD, write a metadata field (control structure field) of a target TD.  
Table 5.319:  TDG. SERVTD .WR Input Operands  Definition  
Must be 0  
must be 0.  
 
Table 5.320:  TDG. SERVTD .WR Output Operands Definition  5 
R8 Previous contents of the field  
In case of an error, R8 returns 0.  
R10 Updated target TD’s TD_UUID bits 63:0 – see the description below.  
R11 Updated target TD’s TD_UUID bits 127:64 – see the description below.  
R12 Updated target TD’s TD_UUID bits 19 1:128 – see the description below.  
November 2023  . Page 294 of 329 
vary.  
TDG.SERVTD. WR writes  a metadata field (control structure field) of a target TD.   The value (R8) is  written as specified by 
the write mask (R9).  Writing is subject to the field’s internal write mask (per the TD’s ATTRIBUTES.DEBUG bit).  Writing 5 
Table 5.321:  Metadata Field Write Rules  
 
Enumeration:  Availability of TDG. SERVTD.WR is enumerated by TDX_FEATURES0.SERVICE_TD (bit 2), readable by 
TDG.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.SERVTD.WR returns a 10 
correct.  In this case, if the TD_UUID provided in R13:R10 is equal  to the pre -import TD_UUID of 
the target TD, TDG.SERVTD.WR returns TDX_TARGET_UUID_MISMATCH status in RAX, and updates 15 
TD_UUID.  
VMM.  This TD exit is trap like, meaning it happens after TDG.SERVTD.WR has completed its 
operation.  On the following TDH.VP.ENTER, the host VMM may set a HOST_RECOVERABILITY_HINT  20 
flag, indicating that TDG.SERVTD.WR may be retried.  From the guest TD’s perspective, this flag 
Table 5.322 TDG. SERVTD .WR Operands Information Definition  25 
Explicit/  
1GB  
page (from 
binding handle)  TDR  RW Opaque  N/A Shared(h)  Shared(h)  Shared(h)  
structure  TDCS  RW Opaque  N/A Shared(i)  None  None   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 295 of 329 
1GB  
TDCS.OP_STATE  OP_STATE  R Opaque  N/A Shared (h) N/A N/A 
metadata  N/A RW Opaque  N/A None  None  None  
 
If the memory operand checks, per the table above, pass : 
2. Check that the calculated binding slot number does not exceed target TD’s the number of available slots12. 5 
4. Check the target TD state:  
4.5. The target TD has not been paused for export.  
If passed:  
5. Check that the target TD’s TD_UUID is the same as specified.  15

If passed:  
5. Check that the target TD’s TD_UUID is the same as specified.  15 
5.1. If failed, and the target TD’s PRE_IMPORT_UUID is the same as the specified TD_UUID, abort and return the 
If passed:  
6. Check that the target TD’s binding slot’s SERVTD_BINDING_STATE is BOUND.  
7. Calculate the current (service) TD’s TD_UUID and check it is equal to the target TD’s binding slot’s SERVTD_UUID.  20 
8. Calculate the current (service) TD’s TDINFO_HASH and check it is equal to the target TD’s binding slot’s 
If passed:  
9. Write the control structure field and return its old value, using the algorithm described in 5.2.2.2 . 
Table 5.323:  TDG. SERVTD .WR Completion Status Codes (Returned in RAX) Definition  
 
12 This value is a property of the TDX module and is the same for all TDs.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 296 of 329 
service TD can retry the operatio n. 
TDX_SUCCESS  TDG.SERVTD.WR  is successful . 
TDX_TARGET_UUID_UPDATED  The target TD’s TD_UUID value provided in R13:R10  doesn’t 
service TD can retry the operation.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 297 of 329 
November 2023  . Page 298 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.10.  TDG.SYS.RD Leaf  
Table 5.324:  TDG.SYS.RD  Input  Operands  Definition  
Must be 0  
must be 0.  
 
Table 5.325:  TDG.SYS.RD Output Operands Definition  5 
Else, in case of an error, RDX returns -1.  On success, RDX returns the next readable field 
identifier.  A value of -1 indicates no next field identifier is available.  
 
vary.  
TDG.SYS.RD reads a TDX Module global -scope metadata field.  10 
RDX returns the next guest -side readable field identifier.  This may be used by the guest TD to enumerate the TDX 
Module’s capabilities and configuration.  To read all the available fields, the guest TD can invoke TDG.SYS.RD in a loop, 
that the returned value is not applicable .  Alternatively, the guest TD can use TDG.SYS.RDALL.  
November 2023  . Page 299 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.326 TDG.SYS.RD Operands Information Definition  
Explicit/  
Implicit  N/A N/A TDVPS structure  TDVPS  None  Opaque  N/A Shared(i)  
 
1. Read the requested field using the algorithm described in 5.2.2.1 . 
2. Return the next readable field identifier, or a value of 0 if none exists.  
3. Return the field value.  5 
Table 5.327:  TDG. SYS.RD Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.SYS.RD  is successful . 
November 2023  . Page 300 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.11.  TDG.SYS.RDALL Leaf  
Read all guest -readable TDX module global -scope metadata fields.  
Table 5.328:  TDG.SYS.RDALL Input Operands  Definition  
Must be 0  
RDX  The GPA of  a 4KB buffer  where a metadata list will be returned  
The buffer must be aligned on 4KB.  
In case of error, some field value entries might not contain valid data.

Must be 0  
If R8’s v alue is -1, then  TDG.SYS.RDALL will start from the first global -scope metadata field 
 
Table 5.329:  TDG.SYS.RDALL Output Operands Definition  5 
R8 Next field identifier.  A value of -1 means all applicable field identifiers have been returned in the 
metadata list . 
 
vary.  
TDG.SYS.RDALL reads all host -readable TDX Module global -scope metadata fields into a metadata list in the provided 10 
page.  
If one or more applicable fields do not fit in the provided list buffer , the function can be invoked in a loop, each invocation 
providing an initial field identifier returned as the next field identifier of the previous invocation , as shown in the following 
example:  
2. Repeat:  
2.2. Invoke TDG.SYS.RDALL(RDX = LIST_BUFFER, R DX = NEXT_FIELD_ID)  
Until ((STATUS is a non -recoverable error) or (NEXT_FIELD_ID is -1)) 20  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 301 of 329 
Intel TDX Application Binary Interface (ABI) Reference  The function never returns an empty list if there’s no error.  
Table 5.330:  TDG.SYS.RDALL  Operands Information Definition  
Explicit/  
Explicit  RDX  GPA  Metadata List  MD_LIST  RW Private  4096  None  
 5 
1. Dump all guest -readable metadata fields into the provided list buffer.  
Table 5.331:  TDG.SYS.RDALL Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.SYS.RDALL  is successful . 
November 2023  . Page 302 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.12.  TDG.VM.RD  Leaf  
Read a TD-scope metadata field (control structure field) of a TD.  
Table 5.332:  TDG.VM.RD  Input  Operands  Definition  
RCX Reserved, must be 0  
must be 0.  
For TDG.VM.RD version 1 or higher, a value of -1 is a special case:  it is not a valid field identifier; 
 
Table 5.333:  TDG.VM.RD Output Operands Definition  5 
RAX  TDCALL instruction return code – see 5.4.1  
RDX  For TDG.V M.RD version 0, RDX is unmodified.  
For TDG.VM.RD version 1 or higher : 
• Else, in case of an error, RDX returns -1.  On success, RDX returns the next readable field 
 
vary.  
TDG.VM.RD reads a VM -scope metadata field (control structure field) of a TD.  10 
Enumeration:  Availability of TDG. VM.RD version 1 is enumerated by TDX_FEATURES0.ENHANCED_METADATA (bit 3), 
readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.VM.RD with a version number 
guest TD to dump the guest readable TD metadata.  To read all the available fields, the guest TD can invoke TDG.VM.RD 15  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 303 of 329 
Intel TDX Application Binary Interface (ABI) Reference  in a loop, starting with field identifier -1 as an input, until RDX returns -1.  A status code of TDX_METADATA_FIELD_SKIP 
indicates that the returned value is not applicable.  
Table 5.334 TDG.VM.RD Operands Information Definition  5 
Explicit/  
Implicit  N/A N/A TD metadata (guest -
side access)  N/A R Opaque  N/A Shared  
 
10. Read the control structure field using the algorithm described in 5.2.2.1 . 
Table 5.335:  TDG.VM.RD Completion Status Codes (Returned in RAX) Definition  10 
TDX_SUCCESS  TDG.VM.RD  is successful . 
November 2023  . Page 304 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.13.  TDG.VM.WR  Leaf  
Write a TD-scope metadata field (control structure field) of a TD.  
Table 5.336:  TDG.VM.WR Input Operands  Definition  
Must be 0  
must be 0.  
 
Table 5.337:  TDG.VM.WR Output Operands Definition  5 
 
vary.  
TDG.VM.WR writes a VM -scope metadata field (control structure field) of a TD.   The value (R8) is  written as specified by 10 
Table 5.338:  Metadata Field Write Rules  
Write Mask Bit in R9  Internal Write Mask Bit  Value Bit in R8

vary.  
November 2023  . Page 305 of 329 
Table 5.339 TDG.VM.WR Operands Information Definition  
Explicit/  
Implicit  N/A N/A TDR page  TDR  None  Opaque  N/A Shared  
 
If the memory operand checks, per the table above, pass : 5 
1. Write the control structure field and return its old value, using the algorithm described in 5.2.2.2 . 
Table 5.340:  TDG.VM.WR Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.VM. WR is successful . 
November 2023  . Page 306 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.14.  TDG.VP.CPUIDVE.SET  Leaf  
TDG.VP.CPUIDVE.SET controls unconditional #VE on CPUID execution by the guest TD.  
Note:  TDG.VP.CPUIDVE.SET is provided for backward compatibility.  The guest TD may control the same settings by 
writing to the VCPU -scope metadata fields CPUID_SUPERVISOR_VE and CPUID_USER_VE using TDG.VP.WR.  
Table 5.341:  TDG.VP.CPUIDVE.SET In put Operands Definition  5 
Must be 0  
RCX Controls whether CPUID executed by the guest TD will cause #VE unconditionally  
0 SUPERVISOR  Flags that when CPL is 0, a CPUID executed by the guest TD will cause a 
#VE unconditionally  
1 USER  Flags that when CPL > 0, a CPUID executed by the guest TD will cause a 
63:2  RESERVED  Reserved:  must be 0  
 
Table 5.342:  TDG.VP.CPUIDVE.SET Out put Operands Definition  
 
vary.  
This function  controls whether execution of CPUID by the guest TD, when running in supervisor mode and/or in user 
mode, will unconditionally result in a #VE.  
Table 5.343 TDG.VP.CPUIDVE.SET Operands Information Definition  
Explicit/  
Implicit  N/A N/A TDVPS structure  TDVPS  RW Opaque  N/A Shared (i)  Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 307 of 329 
1. Reserved bits of RCX must be 0.  
2. Update the TDVPS.CPUID_VE flags which control unconditional #VE injection for CPUID for the current VCPU.  
Table 5.344:  TDG.VP.CPUIDVE.SET Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.VP.CPUIDVE.SET is successful.  
 
November 2023  . Page 308 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.15.  TDG.VP.ENTER Leaf  
Enter L2 VCPU operation.   
From the L1 VMM’s point of view, TDG.VP.ENTER is a complex operation that normally involves L1 →L2 VM entry and 
L2→L1 VM exit ; however, it  may fail before L2 VM entry and may also involve TD exits and entries.  Therefore, output 
operands are specified by multiple tables below.  5 
Table 5.345:  TDG.VP.ENTER Input Operands Definition  
RAX  Leaf and Version  TDCALL instruction leaf number and version, see 5.4.1  
Must be 0  
RCX VM_FLAGS  VM identifier  and flags  
1:0 INVD_TRANSLATIONS  Controls how  TDG.VP.ENTER flushes  the TLB context 
and extended paging structure (EPxE) caches 
associated with the L2 VM  before entering the L2 
VCPU  
51:2 Reserved  Reserved:  must be 0  
53:52  VM L2 virtual machine index ( must be 1 or higher)  
63:54  Reserved  Reserved:  must be 0  
RDX  GUEST_STATE_GPA  The GPA of a 256 -bytes aligned L2_ENTER_GUEST_STATE structure - see 3.8.1  for 
details.  
 
Table 5.346:  INVD_TRANSLATION Definition  
Value  Address Translation Invalidation  Underlying Mechanism  Comments  
0 No invalidation  None   
1 Invalidate all TLB entries and extended 
paging -structure translations (EPxE) 
associated with the L2 VM being 
entered  INVEPT single -context invalidation  
(type 1)   
2 Invalidate all TLB entries associated 
with the L2 VM being entered  INVVPID single -context invalidation  
(type 1)  See enumeration 
details below.  
3 Invalidate TLB entries associated with 
the L2 VM being entered, excluding 
global translations  INVVPID single -context invalidation , 
retaining global translations (type 3)  See enumeration 
November 2023  . Page 309 of 329 
Intel TDX Application Binary Interface (ABI) Reference  TDG.VP.ENTER output format depends on how the function was terminated.   
The following table details TDG.VP.ENTER output operands when the interface function returns without entering the L2 
VCPU  due to an error or some other condition . 
Table 5.347:  TDG.VP.ENTER Output Operands Definition on No L2 VM Entry  
• TDX_PENDING_INTERRUPT, indicating that an 
interrupt is pending for L1  
• Any other value not in the table below  
5.4.1  
 5 
The following table details TDG.VP.ENTER output operands when L2 VM entry succeeds, and later an L2 VM exit occurs 
due to a VMX architectural exit reason . 
Table 5.348:  TDG.VP.ENTER Output Operands Definition  on an L2→L1 Exits Following an L1 →L2 Entry  
Reason  L2 VMCS exit reason  
• TDX_SUCCESS, indicating a normal L2 →L1 exit  
• TDX_L2_EXIT_PENDING_INTERRUPT, indicating an 
L2→L1 exit due to an interrupt posted to L1  
• TDX_L2_EXIT_HOST_ROUTED _*, indicati ng a TD 
exit from L2 where the host VMM requested 
resumption of L1  
Other values in the range 0x1100 through 0x111F are 
reserved for future additional status codes that 
indicate an L2 →L1 exit following an L1 →L2 entry.  
Other   See the function completion status definition in 5.4.1  
RCX Exit 
Qualification  exit qualification from L2 VMCS  
RDX  Guest Linear 
Address  guest -linear address from L2 VMCS  
RSI CS Info  CS selector, AR and limit  
Bits Details  
15:0  CS Selector  
31:16  CS AR bit 15:0  
63:32  CS Limit  
RDI CS Base  CS base address   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 310 of 329 
R8 Guest 
Physical 
Address  guest -physical address from L2 VMCS  
 
R9 VM-Exit

RCX Exit 
R8 Guest 
Physical 
 
R9 VM-Exit 
Information  The following information is provided for L2 VM exits due to vectored events.  
In other cases, R9 content should be ignored.  
31:0  VM-Exit Interruption Information  
63:32  VM-Exit Interruption Error Code  
R10 IDT-
Vectoring 
Information  The following information is provided for L2 VM exits that occur during event 
delivery.  
In other cases, R10 content should be ignored.  
31:0  IDT-Vectoring Information  
63:32  IDT-Vectoring Error Code  
R11 VM-Exit 
Information  The following information is provided for L2 VM exits due to instruction execution.  
In other cases, R11 content should be ignored.  
31:0  VM-Exit Instruction Information  
63:32  VM-Exit Instruction Length  
R12 Additional 
Exit 
Information  Additional exit information  
1:0 CPL (from GuestSS.AR.DPL)  
63:2  Reserved, cleared to 0  
R13 Extended 
Exit 
Qualification  Extended exit qualification  
3:0 Extended exit qualification type  
6 PENDING_EPT_VIOLATION  Extended e xit qualification for an EPT 
violation due to L2 VM access to a 
63:4  Reserved, set to 0  
RBX, 
R14 – 
Other 
state  Any state that the L2 VM is allowed to use may be modified.  
 
CPU State Preservation Following a Successful L1 →L2 VM Entry and an L2 →L1 VM Exit  
Following a successful L1 →L2 VM entry and an L2 →L1 VM exit, some CPU state is modified:  
• General purpose register (GPR) values are not preserved.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 311 of 329 
vary.  
TDG.VP.ENTER transitions the VCPU into L2 VM operation.  The function returns either if failed to enter L2 VM or after 
successful entry to L2 VM and then exit from L2 VM.  5 
Enumeration:  Availability of TDG.VP.ENTER is enumerated by TDX_FEATURES0.TD_PARTITIONING (bit 7), readable by 
TDG.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.VP.ENTER returns a 
 Available INVD_TRANSLATION values are enumerated by TDX_FEATURES0.L2_TLB_INVD_OPT (bit 19).  
Availability of PENDING_EPT_VIOLATION indication in R13 is enumerated by 10 
TDX_FEATURES.PENDING_EPT_VIOLATION_V2 (bit 16).  
The following table lists non -error TDG.VP.ENTER termination conditions:  
Table 5.349:  TDG.VP.ENTER Termination Cases  
Case  Status in RAX[63:32]  Description  
Normal  TDX_SUCCESS  L1→L2 entry was successful, followed by an L2 →L1 exit.  L2 VM 
exit information is provided in output GPRs.  
Host Requested 
L2 Exit  TDX_L2_EXIT_HOST_  
ROUTED _ASYNC  L1→L2 entry was successful.  Later, following direct TD exit from 
L2, the host VMM requested resumption of L1.  L2 CPU state is 
updated in the register list.  L2 VM exit information is provided in 
output GPRs.  This information was provided to the host VMM on 
TD exit ; it may or may not be meaningful to the L1 VMM.  
In case of TDG.VP.VMCALL, the L2 CPU state is the state after 
completion of that function, e.g.,  GPR values are as returned by 
the host VMM as inputs to TDH.VP.ENTER.  
This condition is sticky.  I.e., if resumption of L1 encountered a 
problem that required a TD exit (e.g., an EPT violation) the 
following TD entry resumes L1 and provides the same 
TDX_L2_EXIT_HOST_ROUTED status.  
L2 Exit  
following 
TDG.VP.VMCALL  TDX_L2_EXIT_HOST_  
ROUTED _TDVMCALL  L1→L2 entry was successful.  Later, following TDG.VP.VMCALL that 
caused a direct TD exit from L2, the host VMM requested 
resumption of L1 . 
L2 CPU state is updated in the L2_ENTER_GUEST_STATE structure .  
The L2 CPU state is the state after completion of TDG.VP.VMCALL , 
e.g.,  GPR values are as returned by the host VMM as inputs to 
TDH.VP.ENTER.  
L2 VM exit information is provided in output GPRs.  This 
information was provided to the host VMM on the last TD exit ; it 
may or may not be meaningful to the L1 VMM.  
TDX_L2_EXIT_HOST_ROUTED _TDVMCALL  status.   Note that in such 
case the L2 VM exit information reflects, e.g., the EPT violation,  
not the original TDG.VP.VMCALL exit.  
Pending 
Interrupt L2 Exit  TDX_L2_EXIT_PENDING_  
INTERRUPT  L1→L2 entry was successful.  Later, an L2 →L1 exit happened due 
to an interrupt that was posted to L1.  L2 CPU state is updated in 
the register list.  L2 VM exit information is provided in output 
GPRs but is not necessarily meaningful to the L1 VMM (e.g., VM -
exit interruption information is for the  external interrupt that 
triggered the L2 →L1 exit).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 312 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Case  Status in RAX[63:32]  Description  
No L2 Entry  Other  L1→L2 entry was aborted because of some condition, which may 
or may not be an error, as indicated by RAX bit 63.  
E.g., entry may have been aborted due to a pending virtual 
interrupt.  In this case, the L1 VMM typically sets RFLAGS.IF to 1, 
handles the interrupt and then invokes TDG.VP.ENTER again.  
 
Table 5.350:  TDG.VP.ENTER Memory Operands Information Definition  
Explicit/  
Explicit  RDX  GPA  Guest state  L2_ENTER_GUEST_  
STATE  RW Private  256B  None  
 5 
1. VM_FLAGS:  
1.1. VM index must be between 1 and TDCS.NUM_L2_VMS.  
1.2. The reserved fields must be 0.  
2. GUEST_STATE_GPA is a valid private GPA.  10 
If passed:  
3. Check if there is a pending virtual interrupt to L1.  This is indicated by RVI[7:4] > VPPR[7:4].  If so, terminate with a 
TDX_PENDING_INTERRUPT status.  
If no interrupt is pending:  
4. Translate GPAs:  15 
4.1. Translate TDG.VP.ENTER memory output operands GPAs.  Translation needs to be done in one of the following 
cases:  
• The GPA is different than stored in TDVPS from last time TDG.VP.ENTER was called for this VM.  
• The GPA has been blocked since last translated.  
• HPA shadow for this GPA is NULL_PA.  20 
Translation failure leads to an EPT violation TD exit.  
If passed:  
4.2. Translate GPAs of L2 VMCS fields.  Translation needs to be done in one of the following cases:  
• HPA shadow for this GPA is NULL_PA.  25 
If passed:  
5. If INVD_TRANSLATION S is not 0 : 
5.1. Execute INVEPT type 1 , INVVPID type 1 or INVVPID type 3  to flush address translations of the L2 VM.  
6. Read the provided register list  
6.1. Write VMCS -stored register values (e.g., RSP) to the L2 VMCS.  30 
6.2. Load GPR values to the CPU’s GPRs.  
7. Execute VMLAUNCH or VMRESUME depending on whether the entered VCPU and L2 VM (i.e., the current  L2 VMCS) 
has been launched on this LP since the VCPU’s last association with the LP (TDVPS.LAUNCH ED[VM]).   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 313 of 329 
Table 5.351:  TDG.VP.ENTER Completion Status Codes (Returned in RAX) Definition  
TDX_L2_EXIT_HOST_ROUTED _ASYNC  L1→L2 entry succeeded.  Later, following an asynchronous 
TD exit from L2, the host VMM requested resumption of L1.  
TDX_L2_EXIT_HOST_ROUTED _TDVMCALL  L1→L2 entry succeeded.  Later, following a TDG.VP.VMCALL 
TDX_L2_EXIT_PENDING_INTERRUPT  L1→L2 entry succeeded, and later L2 →L1 exit happened due 
to an interrupt that was posted to L1 and is pending.  
TDX_PENDING_INTERRUPT  L1→L2 entry was aborted because an interrupt is pending 
for the L1 VMM.  This indication is returned even if the L1 
VMMs cleared RFLAGS.IF.  
November 2023  . Page 314 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.16.  TDG.VP.INFO Leaf  
Get guest TD execution environment information.

Get guest TD execution environment information.  
Table 5.352:  TDG.VP.INFO In put Operands Definition  
Must be 0  
 
Table 5.353:  TDG.VP.INFO Out put Operands Definition  5 
RAX  TDCALL instruction return  code – see 5.4.1  – returns a constant value of TDX_SUCCESS (0)  
RCX Bits Name  Description  
5:0 GPAW  The effective GPA width (in bits) for this TD ( do not  confuse with MAXPA).  
SHARED bit is at GPA bit GPAW -1. 
63:6  RESERVED  Reserved:  0  
RDX  The TD’s ATTRIBUTES (provided as input to TDH.MNG.INIT)  
31:0  NUM_VCPUS  Number of Virtual CPUs that are usable ( i.e., either active or ready)   
63:32  MAX_VCPUS  TD's maximum number of Virtual CPUs (provided as input to 
TDH.MNG.INIT ) 
R9 Bits Name  Description  
31:0  VCPU_INDEX  Virtual CPU index, starting from 0 and allocated sequentially on each 
successful TDH.VP.INIT  
63:32  RESERVED  Reserved for enumerating future  Intel TDX module capabilities , etc .:  set to 
0 
R10 Bits Name  Description  
0 SYS_RD  Indicates that the TDG.SYS.RD /RDM/RDALL  function s are available.  
Further enumeration can be done using these functions . 
63:1  RESERVED  Reserved – set to 0  
R11 Reserved for enumerating future  Intel TDX module capabilities , etc .:  set to 0  
November 2023  . Page 315 of 329 
vary.  
TDG.VP.INFO provides the TD software with execution environment information – beyond information that is provided 
by CPUID.  5 
Table 5.354:  TDG.VP.INFO Operands Information Definition  
Explicit/  
Implicit  N/A N/A TDVPS structure  TDVPS  R Opaque  N/A Shared (i) 
 
Table 5.355:  TDG.VP.INFO Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.VP.INFO is successful.  
November 2023  . Page 316 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.17.  TDG.VP.INVEPT  Leaf  
Invalidate cached EPT translations for selected L2 VMs.  
Table 5.356:  TDG.VP.INVEPT Input Operands Definition  
Must be 0  
RCX VM index bitmap  
Bit N value of 1 indicates a request to invalidate EPT for VM index N.  N must be between 1 and 
the number of L2 VMs in this TD.  
0 Reserved  Reserved:  must be 0  
1 L2_VM_1  Invalidate EPT for L2 VM #1  
2 L2_VM_2  Invalidate EPT for L2 VM #2  
3 L2_VM_3  Invalidate EPT for L2 VM #3  
63:4 Reserved  Reserved:  must be 0  
 
Table 5.357:  TDG.VP.INVEPT Output Operands Definition  5 
RAX  TDCALL instruction return code  
 
vary.  
TDG.VP.INVEPT executes INVEPT to invalidate the EPT translations of the specified L2 VMs.  10 
Enumeration:  Availability of TDG. VP.INVEPT is enumerated by TDX_FEATURES0.TD_PARTITIONING (bit 7), readable 
by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.VP.INVEPT returns a 
Table 5.358 TDG.VP.RD Operands Information Definition  
Explicit/  
Implicit  N/A N/A TDR page  TDR  None  Opaque  N/A Shared(i)   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 317 of 329 
Implicit  N/A N/A TDVPS structure  TDVPS  R Opaque  N/A Shared(i)  
 
1. Check the validity of the VM index bit mask  
2. Execute INVEPT type 1 (single context invalidation) for the specified L2 VMs’ EPTP.  
Table 5.359:  TDG.VP.INVEPT Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.VP.INVEPT  is successful . 
 
November 2023  . Page 318 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.18.  TDG.VP.INVGLA  Leaf  
Invalidate Guest Linear Address (GLA) mappings in the translation lookaside buffers (TLBs) and paging -structure caches 
for a specified L2 VM and a specified list of 4KB -aligned linear addresses.  
Table 5.360:  TDG.VP.INVGLA  Input Operands Definition  
Number  Selects the TDCALL interface function version  
Must be 0  
RCX VM_AND_FLAGS  VM identifier  and flags  
0 LIST  0: RDX contains a single GLA list entry  
1: RDX contains the GPA and other information of a GLA 
list in memory.  
51:1 Reserved  Reserved:  must be 0  
RDX  GLA_LIST_ENTRY 
or GLA_LIST_INFO  Depending on the LIST flag  in RCX , RDX contains either of the following:  
• A single GLA_LIST_ENTRY , specifying up to 512 consecutive guest linear addresses , 
each aligned on 4KB.  
• GLA_LIST_INFO, specifying  the GPA of a guest linear address (GLA) list in private  
memory.   Each entry in the GLA list specifies up to 512 consecutive guest linear 
addresses , each aligned on 4KB.  GLA_LIST_INFO also specifies the first and last GLA 
list entries to process . 
See 3.6.4  for details.  
 5 
Table 5.361:  TDG.VP.INVGLA  Output Operands Definition  
RAX  Status  TDCALL instruction return code  
or GLA_LIST_INFO  Depending on the LIST flag  provided as input in RCX , RDX contains either of the 
• If LIST was 0, RDX contains the single GLA_LIST_ENTRY provided as an input, 
unmodified . 
• If LIST was 1, RDX contains the GLA_LIST_INFO provided as input, but with the 
FIRST_ENTRY and NUM_ENTRIES fields updated to reflect the number of entries 
processed so far.  If all entries have been processed successfully,  NUM_ENTRIES is 
set to 0.  
November 2023  . Page 319 of 329 
vary.  
TDG.VP.INVGLA  executes INVVPID type 0 to invalidate the cached translations for the specified list of 4KB page Guest 
Linear Addresses (GLA) of the specified L2 VM.  5 
Enumeration:  Availability of TDG. VP.INVGLA is enumerated by TDX_FEATURES0.TD_PARTITIONING (bit 7), readable 
by TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.VP.INVGLA returns a 
Interruptibility  If, during its execution, TDG.VP.INVGLA  detects that an external interrupt is pending, it may resume the 
guest TD with the CPU state unmodified, except for the following:  10 
• GLA_LIST_INFO in RDX is updated to reflect the GLAs processed so far.  
This allows the external interrupt to be recognized, causing a VM exit or a posted interrupt delivery.

vary.  
This allows the external interrupt to be recognized, causing a VM exit or a posted interrupt delivery.  
Typically, TDG.VP.INVGLA  will be re -invoked (since RIP has not changed) and continue its work.  Guest 
Table 5.362 TDG.VP.INVGLA  Operands Information Definition  
Explicit/  
Explicit  RDX  GPA  GLA list page  GLA_LIST  R Private  4096  None  
 
If the memory operand checks, per the table above, pass , the function checks the following conditions (no specific order 
is implied):  20 
1. VM is the index of an existing L2 VM . 
If passed:  
2. If the LIST flag in RCX is 0, process a single GLA_LIST_ENTRY in RDX:  
2.1. With current GLA starting from BASE_GLA, repeat for each page through LAST_PAGE:  
2.1.1.  Execute INVVPID type 0, providing the current GLA and the VM’s VPID . 25 
2.1.2.  Advance the current GLA by 4KB . 
3. Else (LIST flag in RCX is 1), process a GLA list:  
3.1. Check the validity of GLA_LIST_INFO.  
If passed:  
3.2. Translate the GPA list’s GPA.  30 
3.2.1.  On translation error, do a TD exit with an EPT violation indication.  
3.3. Repeat for NUM_ENTRIES from FIRST_ENTRY:  
3.3.1.  Read the current GLA_LIST_ENTRY.  
3.3.2.  Process the current entry as described in the single -entry case above.  
3.3.3.  If there is a pending interrupt and this was not the last entry:  35 
3.3.3.1.  Update RDX to reflect the work done so far:  set FIRST_ENTRY to the index of the next entry and 
NUM_ENTRIES to the remaining number of entries.  
3.3.3.2.  Resume the guest TD without updating RIP or any other state except for RDX.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 320 of 329 
Table 5.363:  TDG.VP.INVGLA  Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.VP.INVGLA  is successful . 
 
November 2023  . Page 321 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.19.  TDG.VP.RD Leaf  
Read a V CPU-scope metadata field (control structure field) of a TD.  
Table 5.364:  TDG.V P.RD Input Operands  
Must be 0  
must be 0.  
 
Table 5.365:  TDG.V P.RD Output Operands Definition  5 
 
vary.  
TDG.V P.RD reads a VCPU-scope metadata field (control structure field) of a TD.  10 
RDX returns the next host -side readable field identifier.  This may be used by the guest TD to dump the guest readable 
VCPU  metadata.  To read all the available fields, the guest TD can invoke TDG.V P.RD in a loop, starting with field identifier 
-1 as an input, until RDX returns -1.  A status code of TDX_METADATA_FIELD_SKIP indicates that the returned value is not 
applicable.  
Enumeration:  Availability of TDG. VP.RD enumerated by TDX_FEATURES0.ENHANCED_METADATA (bit 3), readable by 15 
TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.VP.RD returns a TDX_OPERAND_INVALID(RAX) 
status.   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 322 of 329 
Table 5.366 TDG.V P.RD Operands Information Definition  
Explicit/  
 
1. Read the control structure field using the algorithm described in 5.2.2.1 . 
Table 5.367:  TDG.V P.RD Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.V P.RD is successful . 
November 2023  . Page 323 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.20.  TDG.VP.VEINFO.GET  Leaf  
Intel SDM, Vol. 3, 25.5.6  Virtualization Exceptions  
Get Virtual ization  Exception Information for the recent #VE exception.  5 
Table 5.368:  TDG.VP.VEINFO.GET  Input Operands Definition  
Must be 0  
 
Table 5.369:  TDG.VP.VEINFO.GET  Output Operands Definition  
31:0  Exit Reason  The 32 -bit value that would have been saved into the VMCS as an exit 
reason if a VM exit had occurred instead of the virtualization exception  
63:32  Reserved  Reserved:  0  
RDX  Exit Qualification:  the 64 -bit value that would have been saved into the VMCS as an exit 
qualification if a legacy VM exit had occurred instead of the virtualization exception  
In case of an error, RDX returns 0.  
R8 Guest Linear Address:  the 64 -bit value that would have been saved into the VMCS as a guest -
linear address if a legacy VM exit had occurred instead of the virtualization exception  
R9 Guest Physical Address:  the 64 -bit value that would have been saved into the VMCS as a guest -
physical address if a legacy VM exit had occurred instead of the virtualization exception  
In case of an error, R9 returns 0.  
31:0  VM-exit 
instruction 
length  The 32 -bit value that would have been saved into the VMCS as VM-exit 
instruction length if a legacy VM exit had occurred instead of the 
virtualization exception  
63:32  VM-exit 
information  The 32 -bit value that would have been saved into the VMCS as VM-exit 
instruction information  if a legacy VM exit had occurred instead of the 
virtualization exception   Intel TDX Application Binary Interface (ABI) Reference  348551 -003US  
November 2023  . Page 324 of 329 
The content of R10 is only applicable for TDX -extended #VE (injected by the TDX module), where

The content of R10 is only applicable for TDX -extended #VE (injected by the TDX module), where 
Exit Reason  is not EPT violation  (48) .  It should be ignored for EPT violations converted by the CPU 
to #VE.  
In case of an error, R10 returns 0.  
 
vary.  
TDG.VP.VEINFO.GET  returns the virtualization exception information of a #VE exception that was previously delivered to 5 
Table 5.370:  TDG.VP.VEINFO.GET  Operands Information Definition  
Explicit/  
Implicit  N/A N/A TDCS structure  TDCS  None  Opaque  N/A Shared (i) 
 10 
The function checks the following conditions (no specific order is implied):  
• The VALID field in TDVPS.VE_INFO must non -0 to indicate that a valid virtualization information is available.  
1. Return the EXIT_REASON, EXIT_QUALIFICATION, GLA, GPA, INSTRUCTION_LENGTH and 
INSTRUCTION_INFORMATTION from TDVPS.VE_INFO in GPRs.  15 
2. Clear the VALID field in TDVPS.VE_INFO to 0 to indicate that the virtualization information has been read.  
Table 5.371:  TDG.VP.VEINFO.GET  Completion Status Codes (Returned in RAX) Definition  
TDX_NO_VE_INFO  There is no Virtualization Exception information . 
TDX_SUCCESS  TDG.VP.VEINFO.GET  is successful . 
November 2023  . Page 325 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.21.  TDG.VP.VMCALL  Leaf  
Perform a TD Exit to the host VMM . 
Table 5.372:  TDG.VP.VMCALL  Input Operands Definition  
Must be 0  
RCX A bitmap that controls which part of the guest TD GPR and XMM state is passed as -is to the VMM 
and back  
A bit value of 0 indicates that the corresponding register is saved by the Intel TDX module , 
scrubbed to 0 before SEAMRET to the host VMM, and restored by the Intel TDX module  on the 
following TDH.VP.ENTER . 
A bit value of 1 indicates that the corresponding register is passed as -is to the host VMM, and on 
the following TDH.VP.ENTER , the register value is used as input from the host VMM and passed as -
is to the guest TD.  
The value of RCX is passed to the host VMM.  
15:0  GPR Mask  Controls the transfer of GPR values : 
Bit 0:  RAX  – must be 0  
Bit 1:  RCX – must be 0  
Bit 2:  RDX 
Bit 3:  RBX 
Bit 4:  RSP – must be 0  
Bit 5:  RBP – if the TD’s CONFIG_FLAG.NO_RBP_MOD is 1, then 
this bit must be 0.   See the enumeration note below.  
Bit 6:  RSI 
Bit 7:  RDI 
Bits 15:8:  R15 – R8 
31:16  XMM Mask  Controls the transfer of XMM 15 – XMM 0 register values  
63:32  Reserved  Reserved:  must be 0  
RBX, RDX, 
RBP, RSI, 
RDI, 
R8 – R15 If the corresponding bit in RCX is set to 1, the register v alue passed as -is to the host VMM on 
SEAMRET . 
Else, the register  value is not used as an input and is preserved.  
host VMM.  See the enumeration note below.  
XMM0 – 
XMM15  
 If the corresponding bit in RCX is set to 1, the register value passed as -is to the host VMM on 
SEAMRET.  
November 2023  . Page 326 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Table 5.373:  TDG.VP.VMCALL  Output Operands Definition  
RAX  TDCALL instruction return  code :  returns a constant value of TDX_SUCCESS (0)  
RCX Unmodified  
RBX, RDX, 
RBP, RDI, 
RSI, 
R8 – R15 If the corresponding bit in RCX is set to 1, the register value passed as -is from the host VMM ’s 
SEAMCALL( TDH.VP.ENTER ) input.  
Else, the register  value is unmodified.  
If the TD’s CONFIG_FLAGS.NO_RBP_MOD is set to 1, then RBP can’t be used to pass values from 
the host VMM and is not modified from its input value.  See the enumeration note below.  
XMM0 – 
XMM15  If the corresponding bit in RCX is set to 1, the register value passed as -is from the host VMM’s 
vary.  
TDG.VP.VMCALL  performs a TD exit to the host VMM.  From the VMM’s point of view, this is the termination of a previous 5 
SEAMCALL( TDH.VP.ENTER ).  Selected GPR and XMM state is passed to the VMM host, controlled by RCX as shown above.  
The rest of the  CPU state is saved in TDVPS and replaced with a synthetic state.  
From the guest TD’s point of view, a subsequent SEAMCALL( TDH.VP.ENTER ) from the host VMM terminates the 
TDG.VP.VMCALL  function.  Most GPR state, and  if the value of RCX bit 1 is set, all XMM state, is passed to the TD guest as 
shown above.  10 
enumerated by TDX_FEATURES0.NO_RBP_MOD (bit 18), readable by TDH.SYS.RD* (see 3.3.3.1 ).  If not 
supported, then RBP can be used by TDG.VP.VMCALL to pass information between the guest TD and 
the host VMM, although highly discouraged since it contradicts normal calling conventions ABI . 
L2 VM Details:  TDG.VP.VMCALL may be invoked by an L2 VM, if enabled by the L1 VMM for the current VCPU (by 15 
setting TDVPS.L2_CTLS.ENABLE_TDVMCALL).  If not enabled, then TDG.VP.VMCALL results in an L2 →L1 
exit.  
 On subsequent TD resumption, the host VMM may request resumption into L1 by setting 
TDH.VP.ENTER’s RESUME_L1 flag.  In this case, L1 is resumed (i.e., the TDG.VP.ENTER it has invoked is 
terminated) with a TDX_L2_EXIT_HOST_ROUTED_TDVMCALL status.  The L2 VC PU state reflects the 20 
successful completion of TDG.VP.VMCALL.  
Table 5.374:  TDG.VP.VMCALL  Operands Information Definition  
Explicit/  
November 2023  . Page 327 of 329 
Intel TDX Application Binary Interface (ABI) Reference  1. If invoked from an L2 VM, and TDVPS.L2_CTLS.ENABLE_TDVMCALL is 0, do an L2 →L1 exit.  
2. Save guest TD CPU state to TDVPS (including TD VMCS):  
2.1. Save extended state per TDCS.XFAM.  There is no strict requirement t o save XMM state  that will be passed to 
the host VMM as controlled by RCX.   This state will be overwritten on the next TD entry . 
2.2. Save GPR state.  There is no strict requirement t o save GPR state  that will be passed to the host VMM as 5 
controlled by RCX (but RCX itself must be saved).  T his state will be overwritten on the next TD entry . 
2.3. Advance the saved RIP to the instruction following TDCALL.  
3. Adjust the TDCS TLB tracking counters.  
4. Release the shared locking – acquired on TDH.VP.ENTER  of TDR, TDCS and TDVPS.  
5. Load host VMM state:  10 
5.1. Clear the extended state except XMM (per TDCS.XFAM) to synthetic INIT values.  
5.2. As controlled by RCX, either clear or set to the guest TD’s value the state of XMM0 – XMM15.  
5.3. As controlled by RCX, either clear or set to the guest TD’s value the state of RBX, RDX, RBP, RDI, RSI and R8  – R15.  
5.4. Set RCX to the guest TD’s value.  
5.5. Set RAX to the TDCALL  exit reason.  15 
5.6. Restore other host VMM state – saved during TDH.VP.ENTER . 
6. Execute SEAMRET to return to the host VMM.  
Note:  Logically, from the point of view of the guest TD, TDG.VP.VMCALL  is terminated by the next TDH.VP.ENTER . 
Table 5.375:  TDG.VP.VMCALL  Completion Status Codes (Returned in RAX) Definition  20 

TDX_SUCCESS  TDG.VP.VMCALL  is successful.  TD exit was done, resulting a in a completion of 
SEAMCALL( TDH.VP.ENTER ) on the host VMM side.  Later, the host VMM 
executed SEAMCALL( TDH.VP.ENTER ) again, and execution returned to the 
guest  TD VCPU (in TDX non -root mode) completing TDG.VP.VMCALL . 
 
November 2023  . Page 328 of 329 
Intel TDX Application Binary Interface (ABI) Reference  5.4.22.  TDG.V P.WR Leaf  
Write a V CPU -scope metadata field (control structure field) of a TD.  
Table 5.376:  TDG.V P.WR Input Operands  
Must be 0  
must be 0.  
WRITE_MASK_VALID, INC_SIZE, CONTEXT_CODE and FIELD_SIZE components of the field identifier 
are ignored.  
 
Table 5.377:  TDG.V P.WR Output Operands Definition  5 
 
vary.  
TDG.V P.WR writes a V CPU-scope metadata field (control structure field) of a TD.   The value (R8) is  written as specified by 10 
Table 5.378:  Metadata Field Write Rules  
November 2023  . Page 329 of 329 
Intel TDX Application Binary Interface (ABI) Reference  Enumeration:  Availability of TDG. VP.WR enumerated by TDX_FEATURES0.ENHANCED_METADATA (bit 3), readable by 
TDH.SYS.RD* (see 3.3.3.1 ).  If not supported, calling TDG.VP.WR returns a 
Table 5.379 TDG.VM.WR Operands Information Definition  
Explicit/  
 
Table 5.380:  TDG.V P.WR Completion Status Codes (Returned in RAX) Definition  
TDX_SUCCESS  TDG.V P.WR is successful . 
 Intel®  Trust Domain CPU Architectural Extensions
343754-002US
MAY 2021ii Ref. # 343754-002Intel Corporation (“Intel”) provid es these materials as-is, with no express or implied warranties.
All products, dates, and figures specified are preliminary, ba sed on current expectat ions, and are subject to change without no tice. Intel does
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.
© Intel Corporation. Intel,  the Intel logo, and other Intel marks are trademar ks of Intel Corporation or its subsidiaries. Othe r names and brands
might be claimed as the property of others.Ref. # 343754-002 iiiRevision History
343754-001 Initial release. September 2020
343754-002 Intel Persistent SEAMLDR module support and other updates. May 2021iv Ref. # 343754-002Ref. # 343754-002 vREVISION HISTORY
CHAPTER 1
1.2 Intel® TDX Module and Intel P-SEAMLDR Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-3
1.3 SEAM VMX Root Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-5
1.3.1 TDX Private KeyID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.2 Memory Typing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.3.3 Caching Translation Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.3.4 Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9
1.4 SEAM VMX Non-Root Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1-9
1.4.1 SEAM VMX Non-Root Execution Controls  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.4.2 Guest Physical Address Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.4.3 Linear Address Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.4 Memory Typing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.5 Caching Translations Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.4.6 Virtual Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.5 Operation Outside SEAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
CHAPTER 2 
VMX INSTRUCTION SET EXTENSIONS
2.1 Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-1
2.2 VM Instruction Error Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-2
2.3 Instruction Set Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2-2
SEAMCALL — Call to SEAM VMX Root Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .2-3
SEAMOPS — Invoke SEAM Operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
SEAMRET — Return to Legacy VMX Root Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
TDCALL — Call to VM Monitor from TD Guest. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
VMRESUME/VMLAUNCH — Resume/Launch Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 2-14
CHAPTER 3 
INTEL® SGX INSTRUCTION SET EXTENSIONS
3.1 EVERIFYREPORT2 Leaf Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3-1vi Ref. # 343754-002Ref. # 343754-002 viiTABLES
PAGE
1-1 IA32_SEAMRR_PHYS_BASE MSR and IA32_SEAMRR_PHYS_MASK MSR Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-2 IA32_SGX_SVN_STATUS MSR Layout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1-3 MKTME Programming Interface Extensions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1-4 Encoding KeyID in Physical Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1-5 MSR_INTR_PENDING MSR Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1-6 Encoding KeyID in Physical Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2-1 VM Instruction Error Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2-2 TEE_TCB_SVN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-3 TEE_TCB_INFO Structure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-4 REPORTTYPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-5 REPORTMACSTRUCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-6 SEAMREPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-7 SEAMREPORT Operands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-8 SEAMREPORT Memory Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
3-1 EVERIFYREPORT2 Instruction Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3-2 EVERIFYREPORT2 Memory Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 3-1
3-3 Temp Variables in EVERIFYREPORT2 Operational Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1viii Ref. # 343754-002Ref. # 343754-002 ixFIGURES
PAGE
Figure 1-1. Intel® Trust Domain Extensions Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Figure 1-2. SEAM Range Register Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Figure 1-3. VMX and SEAM Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3x Ref. # 343754-002Ref. # 343754-002 1-1SECURE ARBITRATION MODE (SEAM)
CHAPTER 1
SEAM VMX root operation is designed to host a CPU-attested, software module called the Intel® Trust Domain 
Extensions (Intel® TDX) module to manage virtual machine (VM) guests called Trust Domains (TD) . The Intel 
TDX module implements the functions to build, tear do wn, and start execution of TD VMs. The VMM provides 
memory resources to build the TD, and the Virtual Machin e Monitor (VMM) helps schedule the TD executions using 
the API provided by the Intel TDX module.
SEAM VMX root operation is designed to additionally host a CPU-attested, software module called the Intel 
Persistent SEAMLDR (Intel P-SEAMLDR) module  to load and update the Intel TDX module.
hosting VMM, unless explicitly shared by the TD itself.
The Intel TDX module and the Intel P-SEAMLDR module, that  execute in SEAM VMX-root operation, execute out of 
memory defined by the SEAM range register (SEAMRR). Th e reserved range of memory specified using the SEAM 
range register (SEAMRR) is configured by th e platform owner and programmed by the BIOS.Figure 1-1.  Intel® Trust Domain Extensions ComponentsVM
SEAMRET
SEAMRET1-2 Ref. # 343754-002SECURE ARBITRATION MODE (SEAM)
The SEAMRR range is partitioned into  two sub-ranges by the processor:
•MODULE_RANGE 
The MODULE_RANGE is used to install an Intel TDX-module  that provides functions to build and manage TD VMs. 
The P_SEAMLDR_RANGE is used to install an Intel Persiste nt SEAM loader (P-SEAMLDR) module that is used to 
measure, verify, and install the Intel TDX-module into  the MODULE_RANGE. By desi gn, access to the P-SEAMLDR 
range is restricted to  the P-SEAMLDR module.
Intel provides a non-persistent SEAMLDR (NP-SEAMLDR)  ACM to install an Intel P-SEAMLDR module, in the 
P_SEAMLDR_RANGE of SEAMRR.
The Intel TDX-module in the MODULE_R ANGE is loaded by the P-SEAMLDR.
The SEAM range register details are shown in Figure 1-2.

SEAMRET
The processor transitions from legacy VMX-root operation to SEAM VMX-root operation in response to a SEAMCALL 
instruction invoked by the VMM. The processor transition s out of SEAM VMX-root operation to legacy VMX-root 
operation in response to a SEAMRET instruction.
The RAX register is an input parameter to the SEAMCALL inst ruction. The instruction uses bit 63 of the RAX register 
to determine if the SEAMCALL should transition to software  executing in the MODULE_RANGE (if bit 63 is 0) or the 
P_SEAMLDR_RANGE (if bit 63 is 1). Only one logical processor in the platform can execute from the 
P_SEAMLDR_RANGE at a time, and this is enforced by the SEAMCALL instruction. A SEAMCALL instruction that 
performs a transfer to the P_SEAMLDR enables access to  the P_SEAMLDR_RANGE on that logical processor. A 
SEAMRET instruction invoked by the P_SEAMLDR closes access to the P_SE AMLDR_RANGE and transitions to the 
legacy VMX root operation.
The VMRESUME/VMLAUNCH instructions are used to help transition to the SEAM VMX non-root operation from 
SEAM VMX root operation. VM exits are designed to then exit from the SEAM VMX non-r oot transition to SEAM VMX 
root operation. The transitions are shown in Figure 1-3.Figure 1-2.  SEAM Range Register DetailsSEAMRR.BaseInstall Intel P-SEAMLDRNP-SEAMLDR (ACM)
P_SEAMLDR_RR.LimitMODULE_RANGE P_SEAMLDR_RANGERef. # 343754-002 1-3SECURE ARBITRATION MODE (SEAM)
1.2 INTEL® TDX MODULE AN D INTEL P-SEAMLDR MODULE
The Intel TDX module and the Intel P- SEAMLDR module execute out of a rang e of memory defined using a SEAM 
range register (SEAMRR) interface. By design, access to this range is restricted to SEAM VMX root operation. Code fetches outside of SEAMRR when in SEAM VMX root operatio n are meant to be disallowed and lead to an unbreak-
able shutdown.
If the SEAMRR bit (bit 15) of the IA32_MTRRCAP MSR is  set, the processor suppor ts the SEAMRR interface to 
restrict access to a specified memory address range used  by the Intel TDX module wh en executing in SEAM VMX 
root operation. The SEAM range registers consist of  a pair of MSRs. The IA32_SEAMRR_PHYS_BASE MSR is 
intended to define the 32-MB aligned base address fo r the SEAM memory range. The IA32_SEAMRR_PHYS_MASK 
MSR contains a mask that helps determine the address range protected by the SEAMRR interface. The smallest 
address range that should be specifie d by the SEAM range registers is 32 MB. The intention is that the MSRs may 
be written only by boot BIOS and before the lock bit has been set; an attempt to write them outside of boot BIOS 
or after the lock bit has been set would cause a general-protection exception.Figure 1-3.  VMX and SEAM Transitions
Table 1-1.  IA32_SEAMRR_PHYS_BASE MSR and IA32_SEAMRR_PHYS_MASK MSR Layout 
Register Address
Register Name / Bit Fields Scope Bit Description Comment
Hex Dec
1400H 5120 IA32_SEAMRR_PHYS_BASE Core Secure Arbitration Mode Range 
Register - Physic al Base Control 
RegisterIf IA32_MTRRCAP. SEAMRR 
[15] = 1.
3 When set, indicates the range is 
configured.
24:4 Reserved
(MAXPHYADDR-1):25 SEAMRR base address.
63: MAXPHYADDR ReservedVM Entry
VM Exit
SEAM,  legacy VMX, SMMSMM Guest
VMX Non-Root
SMM Transfer Monitor
VMX Root
Dual monitor treatment not 
activated
Out of VMXSMM Guest Entry
SMM Guest Exit
Dual monitor treatment activated
Dual monitor treatment not activatedVMM
Legacy VMX RootVM
Default
Out of VMXVMXON VMXOFFVM EntryVM ExitSEAM Mode
SEAM
SEAM
VMX RootVM Exit (in SEAM 
mode)VM EntryVM Exit
(SMI)
Memory and state opaque to VMM
SEAM VMX root in TCB of SEAM VMX non-root1-4 Ref. # 343754-002SECURE ARBITRATION MODE (SEAM)
Starting at offset 4K from the SEAMRR base, a 4K page per addressable logical processor ID is used to host a SEAM 
transfer VMCS structure used by the SEAMCALL instruction invoked with RAX[63] set to 0 to aid the transfer from 
legacy VMX-root operation to SEAM VMX-root operatio n as a VM exit to the Intel TDX module. The SEAMRET 
instruction uses this VMCS to aid transfer from the SEAM VMX- root operation back to legacy VMX-root operation as 
a VM entry. The address of the SEAM transfer VMCS fo r a given, logical processor is IA32_SEAMRR_PHYS_BASE + 
4096 + CPUID.B.0.EDX [31:0] * 4096.
In the P_SEAMLDR_RANGE, a 4K page is used to host a P-SEAMLDR transfer VMCS used  by a SEAMCALL instruction 
invoked with RAX[63] set to 1 to aid the transfer from le gacy VMX-root operation to SEAM VMX-root operation as a 
VM exit to the Intel P-SEAMLDR module. SEAMCALL with RA X[63] set to 1 is designed to allow only one logical 
processor to VM exit to the Intel P-SEAMLDR module. Th e Intel P-SEAMLDR module us es the SEAMRET instruction 
to transition to legacy VMX-root operation as  a VM entry using the P-SEAMLDR transfer VMCS.
Intel provides a non-persistent Secure Arbitration Mode Loader (NP-SEAMLDR) ACM to help initialize the SEAM 
range, set up the P-SEAMLDR transf er VMCS structure, and load the Intel P-SEAMLDR module into the 
P_SEAMLDR_RANGE range of memory. The OS can launc h the NP-SEAMLDR ACM using the GETSEC[ENTERACCS] 
instruction if the SEAMRR range enable bit (b it 11) of IA32_SEAMRR_PHYS_MASK MSR is 1. 
The P-SEAMLDR module may be invoked by the VMM to lo ad/update the Intel TDX module in the MODULE_RANGE 
of SEAMRR. The P-SEAMLDR module helps to  initialize the SEAM transfer VMCS structures used for transfer to the 
Intel TDX module and load/update th e Intel TDX module in the MODULE_R ANGE of the SEAMRR. The P-SEAMLDR 
aims to measure and verify the Intel TDX module against its signature structure and record its security version 
number (SVN), measurements, and identity into CPU regi sters that are accessible only to the P-SEAMLDR module.
The SEAMCALL instruction invoked with RAX[63] set to 0 is meant to return VMFailInvalid if invoked when the Intel 
TDX module is not ready for execution. This may be due to i) either the P-SEAMLDR not having been invoked to 
successfully initialize and load the Intel TDX module, ii) the Intel TDX module is being updated, or iii) the Intel TDX 
module is not ready due to entering a shutdown when in SEAM.
The SEAMCALL instruction invoked with RAX[63] set to 1 is meant to return VMFailInvalid if invoked when the Intel 
P-SEAMLDR module is not ready for execution. This may be due to i) either the NP-SEAMLDR not having been 
invoked to successfully initialize and load the Intel P-SEAM LDR module, ii) P-SEAMLDR is itself being updated, or iii) 
the Intel P-SEAMLDR module is not ready du e to entering a shutdown when in SEAM.
The SVN of the NP-SEAMLDR ACM itself  is reported in the IA32_SGX_SVN_STATUS MSR. OS/VMMs that launch an 
ACM such as SINIT or SEAMLDR are expected to read the IA32_SGX_SVN_STATUS MSR to determine whether the 
ACM can be launched or if a new ACM is needed.
•If either the Intel® Software-Guard-Extensions (Intel® SGX) SVN of the ACM value in the ACM's header is 
greater than the value reported by IA32_SGX_SVN_STATUS or the lock bit in the IA32_SGX_SVN_STATUS is 
not set, then the OS/VMM can launch the ACM.
•If the Intel SGX SVN value reported in the corresp onding component of the IA32_SGX_SVN_STATUS MSR is 
greater than the Intel SGX SVN value in the ACM's header, and if bit 0 of the IA32_SGX_SVN_STATUS MSR is 
1, then the OS/VMM would not launch that version of the ACM. It would obtain an updated version of the ACM 
either from the BIOS or from an external resource.1401H 5121 IA32_SEAMRR_PHYS_MASK Core Secure Arbitration Mode Range 
Register - Physical Mask Control RegisterIf IA32_MTRRCAP. SEAMRR 
[15] = 1.
9:0 Reserved
10 Lock bit for the SEAMRR.
11 Enable bit for the SEAMRR.
(MAXPHYADDR-1):25 SEAMRR mask bits.63: MAXPHYADDR ReservedTable 1-1.  IA32_SEAMRR_PHYS_BASE MSR and IA32_SEAMRR_PHYS_MASK MSR Layout (Continued)
Hex DecRef. # 343754-002 1-5SECURE ARBITRATION MODE (SEAM)
SGX SVN of the ACM carried by the OS/VMM is lower th an that reported by the IA32_SGX_SVN_STATUS MSR, 
irrespective of the setting of the lock bit.
1.3 SEAM VMX ROOT OPERATION
The Intel TDX module uses the SEAM VMX root operation to  help arbitrate resource allocation to the TD VMs and 
transition to SEAM VMX non-root oper ations to execute the TD VMs. The Intel TDX module uses Multi-Key, Total-
Memory-Encryption (MKTME) technology to aid protection of the confidentiality and integrity of the TD VMs' private 
memory. The Intel® Architecture Memory Encryption Techno logies Specification is specified at: https://soft-
ware.intel.com/content/dam/develop/external/us/en/documents/multi-key-total-memory-encryption-spec-
753926.pdf .

Leaving VMX operation using VMXOFF or invoking SMM-moni tor using VMCALL instructions is not supported and 
would result in a General-Protection fault (#GP(0)) in SE AM VMX root operation. This section discusses the SEAM 
VMX root operation differences compared to the legacy VMX root operation.
If a logical processor enters a shutdown state when in SEAM VMX root or non-root operation, the processor is 
designed to mark the Intel TDX module and Intel P-SEAMLD R module states as not loaded prior to entering shut-
down, such that all subsequent SEAMCALL invocati ons on any logical processor return VMFailInvalid.Table 1-2.  IA32_SGX_SVN_STATUS MSR Layout 
Hex Dec
400H 1280 IA32_SGX_SVN_STATUS Core Status and SVN Threshold of Intel 
SGX Support for ACM (RO)If CPUID.(EAX=07H,
ECX=0H): EBX[2] = 1.
0 Lock If 1, indicates that a non-faulting 
Intel SGX instruction or SEAMOPS instruction has been 
executed. Consequently, 
launching a proper ly signed ACM 
but with Intel SGX SVN value 
less than the BIOS specified 
Intel SGX SVN threshold would 
lead to an Intel TXT shutdown.
If 0, indicates that the processor 
will allow a properly signed ACM 
to launch irrespective of the 
Intel SGX SVN value of the ACM.
15:1 Reserved
23:16 SGX_SVN_SINIT If CP UID. (EAX=01H, ECX=0H): 
ECX[SMX] =1, this field reflects 
the expected thre shold of Intel 
SGX SVN for the SINIT ACM.
If CPUID. (EAX=01H, ECX=0H): 
ECX[SMX] =0, this field is reserved (0).
63:56 SGX_SVN_SEAMLDR This field reflects the expected 
threshold of In tel SGX SVN for 
the NP-SEAMLDR ACM.
On parts that do not support 
SEAM operation, this field is 
reserved (0).1-6 Ref. # 343754-002SECURE ARBITRATION MODE (SEAM)
1.3.1 TDX Private KeyID
The TD VM private memory contents are meant to be encrypted and integrity protected using the MKTME tech-
nology by associating each TD VM with a different MKTME key identifier (KeyID). Protecting the confidentiality and 
integrity of the TD memory can require that the key associ ated with a KeyID assigned to a TD cannot be tampered 
by untrusted software. Likewise, untrusted software should not be allowed to read or write memory using the 
KeyID assigned to a TD.
Intel Trust Domain Extensions enable reservation of a conf igurable number of KeyIDs as private KeyIDs that can be 
used only in SEAM.
MKTME on an SOC that supports SEAM might support an integrity protected, memory encryption mode. When 
using keys with integrity enabled, the MKTME associates  a message authentication code (MAC) with each cache 
line. By design, when reading a cache line using a KeyID with  integrity enabled, if the MAC stored in the metadata 
does not match the MAC regenerated by the MKTME, then th e cache line is marked poisoned to prevent the data 
from being consumed. Integrity protecte d memory must be initialized before being read, and such initialization 
must be performed using 64-bytes direct-store with 64-byte write atomicity usin g the MOVDIR64B instruction.
The maximum number of KeyIDs supported by the MKTME and the maximum number of upper physical address 
bits that can be configured to be used as KeyIDs ar e enumerated by the IA32_TME_CAPABILITY MSR. As part of 
activating the MKTME, BIOS is mean t to use the IA32_TME_ACTIVATE MSR to configure the number of upper phys-
ical address bits to be used as KeyIDs and thereby activate  the number of KeyIDs that are usable on that platform. 
The partitioning of this activated number of KeyIDs into  shared and TDX private KeyIDs can also be performed by 
the boot BIOS using the IA32_TME_ACTIVATE MSR. The IA32_MKTME_KEYID_PARTITIONING MSR enables reading the KeyID partitioning done by the BIOS. The MK TME programming interface ex tensions are described in 
Table 1-3.
Table 1-3.  MKTME Programming Interface Extensions 
Hex Dec
87H 135 IA32_MKTME_KEYID_PARTI
TIONINGPackage Multi-Key Tota l Memory Encryption 
(MKTME) KeyID Partitioning 
Enumeration MSR
31:0 NUM_MKTME_KIDS
Total Number of activated MKTME 
KeyIDs. If the LOCK field in IA32_TME_ACTIVATE is 0, this field 
reports 0. MKTME KeyIDs span the 
KID range 1 through NUM_MKTME_KIDS.
63:32 NUM_TDX_PRIV_KIDS - Number of 
TDX Private KeyIDs
If the LOCK field in 
IA32_TME_ACTIVATE is 0, this field reports 0. TDX private KeyIDs span 
the range (NUM_MKTME_KIDS + 1) 
through (NUM_MKTME_KIDS + NUM_TDX_PRIV_KIDS).
981H 2433 IA32_TME_CAPABILITY Package Total Memory Encryption (TME) / 
Multi-Key Total Me mory Encryption 
(MKTME) Capability Reporting MSR
0 When set to 1, AES-XTS 128-bit 
encryption algo rithm supported.
1 When set to 1, AES-XTS 128-bit 
encryption with at  least 28-bits of 
integrity algorithm supported.Ref. # 343754-002 1-7SECURE ARBITRATION MODE (SEAM)
The keys for the MKTME KeyID are programmed using th e PCONFIG instruction. The PCONFIG instruction is 
designed to allow key programming fo r TDX private KeyID only in SEAM.
When MKTME is activated, the plan intends the upper bits of platform physical address (starting with the highest 
order bit available as enumerated by the CPUID MAXPA info) be repurposed for usage as a KeyID. When the KeyID 
space is partitioned, the TDX_RESERV ED_KEYID_BITS number of bits, starting with the highest order bit of the 
physical address, is meant to be used to encode TDX privat e KeyID, and, if any of these bits are set, then the KeyID 
specified would be a TDX private KeyID. 
MKTME usage for TD memory protection might require the Intel TDX module to write-back and invalidate caches 
for certain, maintenance operations. For some maintenanc e operations, the Intel TDX module might need to write-
back the caches but not require invalidation of the ca che contents. The WBINVD/WBNOINVD instructions may be 
used by the Intel TDX module to help perform these operations.63:2 See Intel® Architecture Memory 
Encryption Te chnologies 
982H 2434 IA32_TME_ACTIVATE Package Total Memory Encryption (TME) / 
Multi-Key Total Memory Encryption 
(MKTME) Activation MSR
32:0 See Intel® Architecture Memory 
35:32 MK_TME_KEYID_BITS 
The number of KeyID bits to allocate 
to MKTME usage. Like enumeration, 
this is an encoded value. Writing a value greater than 
MK_TME_MAX_KEYID_BITS will 
result in #GP(0). Writing a non-zero value to this field will #GP(0) if bit 1 
of EAX (TME Enable) is not also set 
to 1, as TME must be enabled to use MKTME.
39:36 TDX_RESERVED_KEYID_BITS
The number of physical address bits 
starting at (MAXPHYADDR - 1) that 
are reserved for Intel TDX use to encode TDX private KeyID.The value in this field cannot 
exceed the value in bits 35:32 
of this MSR.
Table 1-4.  Encoding KeyID in Physical Address
PA 
Bits63: MAXPHYADDR(MAXPHYADDR - 1):
(MAXPHYADDR - L)1
NOTES:
1. L represents TDX_RESERVED_KEYID_BITS.(MAXPHYADDR - L - 1):
(MAXPHYADDR - N)2
2. N represents MK_TME_KEYID_BITS.(MAXPHYADDR - N - 1): 0
400H 1280 IA32_SGX_SVN_STATUS Status and SVN Threshold of 
Intel SGX Support for ACM (RO)If CPUID.(EAX=07H,
ECX=0H): EBX[2] = 1.Table 1-3.  MKTME Programming Interface Extensions (Continued)
Hex Dec1-8 Ref. # 343754-002SECURE ARBITRATION MODE (SEAM)
The processor can provide an alternate, cache manage ment interface to SEAM VMX root operation through 
MSR_WBINVDP and MSR_WBNOINVDP. WRMSR to MSR_WB INVDP and MSR_WBNOINVDP can do write-back of 
one cache sub-block specified by software in EDX: EAX.  The WRMSR to MSR_WBINVDP can additionally invalidate 
the specified, cache sub-block. The maximum of cache sub-blocks (NUM_CACHE_SUB_BLOCKS) is meant to be 
read by software using RDMSR to MSR_WBINVDP or MSR_WBNOINVDP. Software should invoke MSR_WBINVDP/MSR_WBNOINVDP with EDX: EAX at least once with a sub-block number between 0 and 
(MAX_CACHE_SUB_BLOCKS - 1) to operate on the entire cach e. Specifying an invalid cache sub-block number, i.e., 
a number greater than or equal to MAX_CACHE_SUB_BLOCKS , can cause a General-Protection fault (#GP(0)). The 
operation of these WRMSR and RDMSR to MSR_WBIN VDP and MSR_WBNOINVDP is designed as follows:
1.3.2 Memory Typing
In SEAM VMX root operation, the determination of memory type for an access is designed as follows:
•If CR0.CD is 1, then the effective memory type is UC. 
•If CR0.CD is 0, then the effective memory type depend s on the physical address that is accessed and the KeyID 
used for the access. 
— If the access is to the SEAMRR, then the MTRRs do not contribute to the memory typing, and the effective, 
memory type for the access is determined by the PAT alone. 
— If the access is to physical memory outside SEAMRR and the access uses a TDX private KeyID, then the 
MTRRs do not contribute to the memory typing. Th e memory type is determined by the PAT alone.

— If the access is to physical memory outside SEAMRR and the access does not use a TDX private KeyID, then 
the memory type for the access is determine based on  the MTRR matching the physical address and the 
PAT.
Special operations that explicitly force a memory type (e.g., fast strings, MOVDIR64, etc.) continue to operate with 
their special memory type as defined by those instructions.
1.3.3 Caching Translation Information
The address translation caching architecture is augmented with an in-SEAM state to support SEAM. When in SEAM 
VMX root operation, in-SEAM is 1. In SEAM VMX root op eration, a logical processor might cache and use cached 
mappings for linear addresses derived from the paging stru cture referenced (directly or indirectly) by the current 
value of CR3 and associate them with:
•Current VPID.
•Current PCID (non-global translations ) or any PCID (global translations).IF RDMSR
     IF inSEAM==0 THEN #GP(0);
     IF invoked from VMX load/store list THEN #GP(0);
     EDX:EAX = MAX_CACHE_SUB_BLOCKS;
ENDIF
IF WRMSR
     IF inSEAM==0 THEN #GP(0);     IF invoked from VMX load/store list THEN #GP(0);
     IF EDX:EAX >= MAX_CA CHE_SUB_BLOCKS THEN #GP(0);
     Flush cache sub-block indexed by EDX:EAX      IF ECX == MSR_WBINVDP THEN Invali date cache sub-block indexed by EDX:EAX;
ENDIFRef. # 343754-002 1-9SECURE ARBITRATION MODE (SEAM)
•Current In-SEAM.
1.3.4 Event Handling
On transition to SEAM VMX root operation, the processor can inhibit NMI and SMI. While inhibited, if these events 
occur, then they are tailored to stay pending and be deli vered when the inhibit state is removed. NMI and external 
interrupts can be uninhibited in SEAM VMX-root operatio n. In SEAM VMX-root operation, MSR_INTR_PENDING can 
be read to help determine status of any pending events.
On transition to SEAM VMX non-root operation using a VM  entry, NMI and INTR inhibit states are, by design, 
updated based on the configuration of the TD VMCS used to perform the VM entry.
SMIs that are incident to SEAM VMX non-root operation or were pending from prior to transition to SEAM VMX non- 
root operation can cause a VM to exit to the SEAM root-m ode operation with the exit reason set to “IO SMI” or 
“Other SMI”. The exit qualification bit 0 is meant to be se t to 1, if the SMI is a machine check initiated SMI (MSMI). 
The SMI would then remain pending following the VM exit.
On transition to legacy VMX root operation using SEAMRE T, the NMI and SMI inhibit state can be restored to the 
inhibit state at the time of the previous SEAMCALL and any pending NMI/SMI would be delivered if not inhibited.
The layout of the MSR_INTR_PENDING is described in Table 1-5.
The reporting of these pending events in MSR_INTR _PENDING is designed not to be affected by:
•EFLAGS.IF.
•NMI blocking.
•SEAM blocking of SMI, or NMI.
•SMI inhibited by SENTER.
•MOV-SS/POP-SS blocking.
•STI blocking.
1.4 SEAM VMX NON-ROOT OPERATION
The TD VMs execute in SEAM VMX non-root operation. This section discusses the SEAM VMX non-root operation 
differences compared to the legacy VMX non-root operation.Table 1-5.  MSR_INTR_PENDING MSR Layout 
Hex Dec
981H 2433 MSR_INTR_PENDING Thread Determine if there are pending 
interrupts or events. (RO)Not allowed in VMX MSR store 
list.
Not readable outside SEAM 
VMX-root operation.
0I N T R  p e n d i n g .1N M I  p e n d i n g .
2 SMI pending.
3 Other/unspecified event pending.4 Other/unspecified event pending.
63:5 Reserved1-10 Ref. # 343754-002SECURE ARBITRATION MODE (SEAM)
1.4.1 SEAM VMX Non-Root Execution Controls
Each TD VM is associated with a VMCS that manages tran sitions into and out of SEAM VMX non-root operation (VM 
entries and VM exits) as well as processor behavior in SEAM VMX non-root operation. 
When in SEAM non-root operation, the processor uses the following, additional controls to help accomplish its aim:
1. Shared EPT Pointer (Shared-EPTP): A 64-bit execution control field (encoding pair 203CH/203DH) to specify 
the Shared-EPT pointer. In SEAM VMX non-root operation,  the plan dictates two EPTs be active: the private EPT 
specified using the EPTP field of the VMCS and a Shared -EPT specified using the Shar ed-EPTP field of the VMCS.
a. Bits 11:0 are reserved.b. Bits (MAXPHYADDR - 1):12 contain bits (MAXPHYADD R - 1):12 of the physical address of the 4-Kbyte 
aligned EPT PML4/PML5 table.
c. Bits 63:MAXPHYADDR are reserved.
2. TD Key identifier (TD-KeyID) (encoding 4026H): A 32-bit execution control field to help specify the TD 
assigned, MKTME KeyID. The processor is meant to us e this TD-KeyID to access EPT paging structures 
referenced by EPTP as the physical ad dresses obtained as a result of tran slation through the EPT referenced by 
the EPTP.
3. Guest Physical Address Width (GPAW): GPAW execution cont rol (bit position 5) in the tertiary, processor-based 
execution controls (encoding 2034H) that, along with the EPT walk levels (4 or 5 level), is used to assist in 
determining the GPA width and thus a SHARED bit position in the GPA. The GPA space of  a TD is partitioned into 
two halves: a shared GPA range and a private GPA range. The GPA range where a SHARED bit is 0 is TD private 
memory, and the EPT determined by the EPTP is used to  help translate the GPA to a physical address. GPA 
loaded into CR3, PDPTRs, and HLAT root pointer are al ways translated using the EPTP. The processor uses the 
TD-KeyID to aid gaining access to the physical address as a result of translation of private GPA. The GPA range 
where a SHARED bit is 1 is TD shared memory, and th e EPT determined by Shared-EPTP is used to help 
translate the GPA to a physical address. The processor uses the KeyID determined from the Shared EPT to aid 
gaining access to the physical address as a result of translation of shared GPA. 
a. When 4-level EPT is active, the SHARED bit position would always be bit 47. b. When 5-level EPT is active, the SHARED bit position woul d be bit 47 if GPAW is 0. Otherwise, else it would 
be bit 51. 
The tertiary, processor-based execution control is designed  to be activated by bit 17 of the primary, processor-
based execution control, and the IA32_VMX_PROCBASED_CT LS3 MSR (index 492H) would then indicate the bits 
that can be set to 1 in the tertiary, processor-based execution control field in the VMCS. Bit position 5 of 
IA32_VMX_PROCBASED_CTLS3 MSR aims to report if the GPAW execution control in tertiary, processor-based 
execution controls field of the VMCS can be set to 1. When the GPAW execution control can be set to 1, the 
processor also supports programming the Shared-EPT P and TD-KeyID execution controls in the VMCS.
These VMCS fields would be ignored by VM entry when not in SEAM VMX root operation.
1.4.2 Guest Physical Address Translation
Transition to SEAM VMX non-root operation is formatted to  require Extended Page Tables (EPT) to be enabled. In 
SEAM VMX non-root operation, there should be two EPTs ac tive: the private EPT specified using the EPTP field of the 
VMCS and a shared EPT sp ecified using the Shared-EPTP field of the VMCS.
When translating a GPA using the shared EPT, an EPT mi sconfiguration can occur if the entry is present and the 
physical address bits in the range (MAXPHYADDR-1) to  (MAXPHYADDR-TDX_RESERVED_KEYID_BITS) are set, i.e., 
if configured with a TDX private KeyID.
If the CPU's maximum physical-address width (MAXPA) is 52 and the guest physical address width is configured to 
be 48, accesses with GPA bits 51:48 not all being 0 can cause an EPT-violation, where such EPT-violations are not 
mutated to #VE, even if the “EPT-violations #VE” execution control is 1.
If the CPU's physical-address width (MAXPA) is less than 48 an d the SHARED bit is configured to be in bit position 
47, GPA bit 47 would be reserved, and GPA bits 46:MAXPA would be reserved. On such CPUs, setting bits 51:48 or 
bits 46:MAXPA in any paging structure can cause a reserved bit page fault on access.Ref. # 343754-002 1-11SECURE ARBITRATION MODE (SEAM)
1.4.3 Linear Address Translation
In SEAM VMX non-root operation, all paging structures us ed to translate linear addresses to GPA should be in 
private GPA space. Setting a SHARED bit to 1 in CR3 or pa ging structures that reference another paging structure 
can cause a reserved bit page fault exception.
In SEAM VMX non-root operation, attempting to execute out of a page in TD shared memory, i.e., page mapped 
with a SHARED bit set to 1, can cause a page fault exception.
1.4.4 Memory Typing
For translated, guest physical accesses, the memory type  should normally be determined based on CR0.CD, PAT 
memory type, and EPT memory type. The EPT memory type  provided by the EPT (shared or private) helps to 
perform the translation.
Special operations that explicitly force a memory type (e.g ., fast strings, MOVDIR64, etc.) are intended to continue 
to operate with their respective, special memory type.

The memory type for accessing VMCS linked data structur es using a TDX private KeyID (MSR bitmaps, VAPIC page, 
etc.) would be UC if CR0.CD is 1. Otherwise, it would be WB. 
1.4.5 Caching Transl ations Information
When in SEAM VMX non-root operations, EPT is intended to  always be in use. Address translation caching architec-
ture is augmented with an additional in-SEAM state to support SEAM. When in SEAM VMX root or VMX non-root 
operation, in-SEAM would be 1 (otherwise, it would be  0) and augment the caching architecture as follows:
•For accesses using linear addresses, the processor can create combined mappings. Combined mappings would 
be derived from the EPT paging structures referenced (directly or indirectly) by the current EP4TA (when 4-
level EPT is active) or current EP5TA (when 5-level EPT is  active). The EPT4TA/EP5TA are from the EPTP field of 
the VMCS. If CR0.PG = 1, the combined mappings can also  be derived from the paging structures referenced 
(directly or indirectly) by the current value of CR3. No combined, paging-structure-cache entries would be 
created if CR0.PG = 0. The combined mappings are associated with:
— Current VPID.— Current PCID (non-global translations) or any PCID (global translations).
— Current EP4TA (when 4-level EPT is active) or current EP5TA (when 5-level EPT is active) from the EPTP 
field of the VMCS.
— Current In-SEAM.
•For guest-physical address accesses, a processor can use guest-physical mappings derived from the EPT 
paging structures referenced (directly or indirectly) by bits 51:12 of the current EPTP or current Shared-EPTP, 
depending on the EPT used to perform the translation. Newly created, guest-physical mappings are associated 
with current EP4TA or current EP5TA from the EPTP field of the VMCS.
Combined and guest-physical mappings obtained through EPT referenced by Shared EPTP are also associated with 
the EP4TA/EP5TA from the EPTP field of the VMCS. To inva lidate guest-physical or combined mappings created in 
SEAM, software (including the VMM executing outside SEAM operation) would use the EPTP (not Shared-EPTP) with 
the KeyID fields of the address set to 0.
INVVPID or INVPCID are designed to invalidate combined mappings created in SEAM only when invoked in SEAM.
1.4.6 Virtual Interrupt Delivery
Virtual interrupt delivery in SEAM VMX non-root operation aims to ignore bits corresponding to vectors 0 through 
30 in the virtual interrupt-request register (VIRR) in the virtual-APIC page when comp uting the requesting, virtual 
interrupt (RVI). These vectors are formatted not to be de livered as virtual interrupts through virtual interrupt 
delivery.1-12 Ref. # 343754-002SECURE ARBITRATION MODE (SEAM)
1.5 OPERATION OUTSIDE SEAM
The physical address bits reserved for encoding TDX privat e KeyID are meant to be treated as reserved bits when 
not in SEAM operation.
When translating a linear address outside SEAM, if any pa ging structure entry has bits reserved for TDX private 
KeyID encoding in the physical address set, then the proc essor helps generate a reserved bit page fault exception.
When translating a guest physical a ddress outside SEAM, if any EPT structure entry has bits reserved for TDX 
private KeyID encoding in the physical address set, then the processor helps generate an EPT misconfiguration.
Instructions that accept physical address operands when invoked with physical addresses that set bits reserved for 
encoding TDX private KeyID are designed to generate  a failure or exception as described in Table 1-6.
Enabling Intel® Processor Trace, by setting TraceEn to 1 in the IA32_RTIT_CTL MSR, causes an operational ToPA 
error if the IA32_RTIT_OUTPUT_BASE MSR was a) programme d with a physical address with TDX private KeyID or 
b) was programmed with a GPA whose translation results in a physical address with TDX private KeyID.
PCONFIG invoked outside SEAM can fail with error code IN VALID_KEYID (encoding 3; KeyID not valid) if the KeyID 
operand is a private KeyID.Table 1-6.  Encoding Ke yID in Physical Address
Instruction Behavior
VMXON VMFailInvalid: the physical  address sets reserved bits.
VMPTRLD VMFail with reason “VMPTRLD with invalid physical address”.
VMCLEAR VMFail with reason “VMCLEAR with invalid physical address”.
VMLAUNCH
VMRESUMETreat any VMCS linked physical address with bits reserved for encoding TDX private 
KeyID set, i.e., specifying a TDX private KeyID as invalid. The treatment is like 
programming these fields with a physical address with bits set beyond the maximum 
physical address width of the processor. Examples of such VMCS fields are MSR bitmap pointer, PML buffer, VAPIC page, etc.
INVEPT VMFail with reason “Invalid operand to INVEPT/INVVPID”.MOV to CR3 General Protection Fault (#GP(0)).
WRMSR Programming control registers and MSRs outs ide SEAM with physical addresses that have 
bits reserved for encoding TDX private KeyID set to 1 are treated as errors and cause a 
#GP(0) exception. Examples of  such MSRs and CRs include:
• IA32_APIC_BASE.
• MTRR, SMRR, and PRMRR ba se and mask registers.
• IA32_HW_FEEDBACK_PTR.
• IA32_TME_EXCLUDE_BASE.Ref. # 343754-002 2-1VMX INSTRUCTION SET EXTENSIONS
CHAPTER 2
Instructions described in this document follow th e general documentation convention established in Intel® 64 and 
IA-32 Architectures Software Developer’s Manual Volume 2A . Additionally, some instructions use notation conven-
tions as described below. 
2.1 CONVENTIONS
The operation sections for the VMX instructions in Sectio n 2.3 use the pseudo-function VMexit, which indicates that 
the logical processor performs a VM exit.
The operation sections also use the pseudo-functions VMsucceed, VMfail, VMfailInvalid, and VMfailValid. These 
pseudo-functions can signal instruction success or failure by se tting or clearing bits in RFLAGS and, in some cases, 
by writing the VM-instruction error field. The follo wing pseudocode fragments detail these functions:
CF := 0;
PF := 0;AF := 0;ZF := 0;SF := 0;OF := 0;
FI;
VMfailValid(ErrorNumber):// executed only if there is a current VMCS
CF := 0;
PF := 0;AF := 0;ZF := 1;SF := 0;OF := 0;
Set the VM-instruction error field to ErrorNumber;
The different VM-instruction error numbers are enumerat ed in Section 2.2, “VM Instruction Error Numbers”.2-2 Ref. # 343754-002VMX INSTRUCTION SET EXTENSIONS
2.2 VM INSTRUCTION ERROR NUMBERS
For certain error conditions, the VM-instr uction error field is loaded with an error number to indicate the source of 
the error. Table 2-1 lists VM instruction error numbers.
2.3 INSTRUCTION SET REFERENCETable 2-1.  VM Instruction Error Numbers
Error
1 VMCALL executed in VMX root operation.
2 VMCLEAR with invalid physical address.3 VMCLEAR with VMXON pointer.4 VMLAUNCH with non-clear VMCS.5 VMRESUME with non-launched VMCS.6 VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME).7 VM entry with invalid control field(s)
1,2.
NOTES:
1. VM-entry checks on control fields and host-state fields can be  performed in any order. Thus, an indication by error number o f one 
cause does not imply that there are not also other errors. Different processors might give different error numbers for the same  
VMCS.
2. Error number 7 is not designed to be used  for VM entries that return from SMM that fail due to invalid VM -execution control fi elds in 
the executive VMCS. Error number 25 is intended to be used for these cases.8 VM entry with invalid host-state field(s)1.
9 VMPTRLD with invalid physical address.10 VMPTRLD with VMXON pointer.11 VMPTRLD with incorrect VMCS revision identifier.12 VMREAD/VMWRITE from/to unsupported VMCS component.13 VMWRITE to read-only VMCS component.15 VMXON executed in VMX root operation.16 VM entry with invalid executive-VMCS pointer
1.
17 VM entry with non-launched executive VMCS1.
18 VM entry with executive-VMCS pointer not VMXON pointer (whe n attempting to deactivate th e dual-monitor treatment of 
SMIs and SMM)1.
19 VMCALL with non-clear VMCS (when a ttempting to activate the dual-monitor treatment of SMIs and SMM).
20 VMCALL with invalid VM-exit control fields.22 VMCALL with incorrect MSEG revision iden tifier (when attempti ng to activate the dual-monitor  treatment of SMIs and SMM).
23 VMXOFF under dual-monitor treatment of SMIs and SMM.
24 VMCALL with invalid SMM-monitor features (when attempting to activate the dual-monitor treatment of SMIs and SMM).
25 VM entry with invalid VM-execution control fields in executive VMCS (w hen attempting to return from SMM)
1,2.
26 VM entry with events blocked by MOV SS.28 Invalid operand to INVEPT/INVVPID.Ref. # 343754-002 2-3VMX INSTRUCTION SET EXTENSIONS
SEAMCALL — Call to SEAM VMX Root Operation
The SEAMCALL instruction uses RAX register bit 63 to dete rmine if the request is to transition to the Intel P-

1,2.
SEAMLDR module (if bit 63 is 1) or the Intel TDX module (if bit 63 is 0).
When invoked in legacy VMX-root operation with RAX bit 63 set to 0, this instruction can cause a VM exit (exit 
reason 4CH - SEAMCALL) to the Intel TDX module in SEAM  VMX root operation using the SEAM transfer VMCS of 
the logical processor on which the instruction was invoked.  These SEAM transfer VMCS are in the module range of 
the SEAMRR. Bit 29 of the exit reason (VM exit from VM X root operation) would be set to 1 on such VM exits.
When invoked in legacy VMX-root operation with RAX bit 63 set to 1, this instruction can cause a VM exit (exit 
reason 4CH - SEAMCALL) to the Intel P-SEAMLDR module in SEAM VMX root operatio n using the SEAM transfer 
VMCS in the P-SEAMLDR range. Only one logical processo r in the system, at a time, can exit to the Intel P-
SEAMLDR module and the SEAMCALL instruction enfo rces this property through a mutex called 
P_SEAMLDR_MUTEX.
When invoked in SEAM VMX non-root operation or legacy VMX non-root operation, this  instruction can cause a VM 
exit (exit reason 4CH - SEAMCALL). Bit 29 of the exit reason  (VM exit from VMX root operation) will be set to 0 on 
such VM exits.
SEAMCALL invokes an indirect branch  control mechanism that establishes a barrier, preventing software that 
executed before the SEAMCA LL from controlling the predicted targets of indirect branches executed after 
SEAMCALL on the same logical processor.
Operation
IF not in VMX operation or inSMM or inSEAM or ((IA32_EFER.LMA & CS.L) == 0)
     THEN #UD;ELSIF in VMX non-root operation     THEN VMexit(“basic reason” = SEAMCALL,                   “VM exit from VMX root operation” (bit 29) = 0);
ELSIF CPL > 0 or IA32_SEAMRR_MASK.VALID == 0 or “events blocking by MOV-SS”     THEN #GP(0);SEAM_CVP = (SEAMRR.BASE + 4K) + CPUID.B.0.EDX[31:0] * 4K// Certain events/conditions that could affect security of SEAM could disable SEAM executionIF If RAX[63] == 0 AND “Intel TDX module not loaded  or disabled”
     THEN VMfailInvalidIf RAX[63] == 1    THEN        Acquire P_SEAMLDR_MUTEX        IF P_SEAMLDR_MUTEX acquisition failed             THEN VMFailInvalid        IF “Intel Persistent SEAMLDR module not loaded/or disabled” 
            THEN               Release P_SEAMLDR_MUTEX               VMFailInvalidOpcode/
EnDescription
66 0F 01 CF
SEAMCALLZO Call to SEAM VMX root operation.
ZO NA NA NA NA2-4 Ref. # 343754-002VMX INSTRUCTION SET EXTENSIONS
           FI;
        inP_SEAMLDR = 1        SEAM_CVP = P_SEAMLDR_CVP    FI;
RFLAGS.{CF, OF, SF, PF, AF, ZF} = 0
// Exiting from legacy VMX root operation
inSEAM = 1SEAM_CVP.VMCS_link_pointer = current-VMCScurrent-VMCS = SEAM_CVPSave VMM state in current-VMCS  based on its VM-exit controls
Save event inhibits in VMM interruptibility status - SMI inhibit, NMI inhibitLoad/force SEAM state based on VM-exit controls and host-state area// Further details of the operation of the VM-exit appear in Chapter 27 “VM Exits” of Intel® 64 and IA-32 Architectures Softwar e 
// Developer's Manual Volume 3, System Programming Guide
Inhibit SMI and NMIcurrent-VMCS.exi t_reason.basic_reason = SEAMCALL
current-VMCS.exit_reason.”VM exit from VMX root operation” (bit 29) = 1current-VMCS.exit_qualification = 0
The operation section uses the pseudo-functions VMsucc eed and VMfailInvalid. See the operation section and 
Section 2.1.
#UD The SEAMCALL instruction is not design ed to be recognized in protected mode.
#UD The SEAMCALL instruction is not designed to be recognized in real-address mode.
#UD The SEAMCALL instruction is not designed  to be recognized in virtual-8086 mode.
#UD The SEAMCALL instruction is not designed  to be recognized in  compatibility mode.
                If IA32_SEAMRR_MASK.VALID is 0.
                       If events are being blocked by MOV SS.#UD If executed outside VMX operation.
If executed in SEAM VMX root operation.
                       If logical processor is in SMM.
If IA32_VMX_PROCBASED_CTLS3[5] is 0.Ref. # 343754-002 2-5VMX INSTRUCTION SET EXTENSIONS
SEAMOPS — Invoke SEAM Operations
The SEAMOPS instruction is used to help execute SE AM-specific operations in SEAM VMX root operation.
The SEAMOPS instruction is designed to only be executed  by privileged software running in SEAM VMX root opera-
tion and invoke leaf functions for performing the requested functionality. Software would select the leaf function by 
setting the appropriate value in regist er RAX. Other registers might have leaf-specific purposes. The instruction 
would be used only in 64-bit mode.
Two leaf functions are currently defined:
•CAPABILITIES (RAX == 0): Returns a bitmap of the supported SEAMOPS leaves.
•SEAMREPORT (RAX == 1): Generate SEAMREPORT structure.
The instruction is formatted to return the outcome of ex ecution of leaf-specific function in RAX register. Leaf 
specific functions might return information in additional GPR.
SEAMOPS is intended to lock CRPL_CPUSVN and BIOS_SE_ SVN, if CRPL_CPUSVN is not already locked, if the 
SEAMREPORT leaf is enabled. Once locked, the CPU help s prevent any further modifications to these registers. 
Thus, CRPL_CPUSVN might be locked by either the first, non-faulting Intel SGX instruction or the first, SEAMOPS 
instruction that executes with SEAMREPORT_ENABLED, i.e., the CAPABILITIES leaf  reports support for the 
SEAMREPORT leaf.
Operation
IF inSEAM==0 or ((IA32_EFER.LMA & CS.L) == 0) or in VMX non-root operation or lock-prefix-used 
     THEN #UD;ELSIF CPL > 0     THEN #GP(0);IF SEAMREPORT_ENABLED == 1 and CRPL_CPUSVN not locked     Lock CRPL_CPUSVN and BIOS_SE_SVNENDIFSWITCH RAX    CASE 0: RAX = SEAMREPORT_ENABLED ? 0x3 : 0x 1;break; // SEAMREPORT (leaf 1) is supported if 
                                                                                           // only  if SEAMREPORT enabled
    DEFAULT: #GP(0); break;ENDSWITCH
None.
#UD The SEAMOPS instruction is not designed  to be recognized in protected mode.
#UD The SEAMOPS instruction is not designed  to be recognized in real-address mode.Opcode/
66 0F 01 CE
SEAMOPSZO Invoke SEAM specific operations.
ZO NA NA NA NA2-6 Ref. # 343754-002VMX INSTRUCTION SET EXTENSIONS
#UD The SEAMOPS instruction is not designed  to be recognized in virtual-8086 mode.
#UD The SEAMOPS instruction is not designed to be recognized in compatibility mode.
#GP(0):  If CPL > 0.
                Illegal leaf function specified in RAX.
                Leaf specific exceptions.
If any leaf-specific memory operand is in CS, DS, ES, FS, or GS segment and memory address 
is non-canonical.
#SS(0): If any leaf-specific memory operand is in SS segment and memory address is non-canonical.#UD: If not in SEAM root operation.
If IA32_VMX_PROCBASED_CTLS3[5] is 0.
#PF(PFEC): If a page fault occurs in a ccessing a leaf-specific memory operand.
SEAMOPS Data Structures
Table 2-2.  TEE_TCB_SVN
NameOffset 
SEAM 0 2 Intel TDX module SVN.
RESERVED 2 14 Must be zero.
Table 2-3.  TEE_TCB_INFO Structure
VALID 0 8 Indicates TEE_TCB_INFO fields which are valid.
• 1 in the i-th significant bit refl ects that the 8 bytes starting at 
offset (8 * i) are valid.
• 0 in the i-th significant bit reflec ts that either 8 bytes starting at 
offset (8 * i) is not populated or reserved, and is set to zero.
TEE_TCB_SVN 8 16 TE E_TCB_SVN array.
MRSEAM 24 48 Measurement of the Intel TDX module.MRSIGNERSEAM 72 48 Measurement of TDX module signer if valid.ATTRIBUTES 120 8 Additional configuration ATTRIBUTES if valid.RESERVED 128 111 Must be zero.Ref. # 343754-002 2-7VMX INSTRUCTION SET EXTENSIONS
Table 2-4.  REPORTTYPE
TYPE 0 1 TEE Type
0x00: SGX
0x7F - 0x01: RESERVED
0xFF - 0x80: SEAM DefinedNote: Bit 7 defines eith er hardware implementation (0) or Intel TDX 
module implementation (1).
SUBTYPE 1 1 TYPE-specific subtype.VERSION 2 1 TYPE-specific version. Must be 0 for Intel SGX.RESERVED 3 1 Must be zero.
Table 2-5.  REPORTMACSTRUCT
(Bytes)Description MAC
REPORTTYPE 0 4 Type Header Structure Y
RESERVED 4 12 Must be zero. YCPUSVN 16 16 CPUSVN YTEE_TCB_INFO_HASH 32 48 SHA384 of TEE_TCB_INFO YTEE_INFO_HASH 80 48 SHA384 of TEE_INFO (or 0x00 if no TEE is represented) YREPORTDATA 128 64 A set of data used for communication between the caller 
and the target.Y
RESERVED 192 32 Must be zero. Y
MAC 224 32 The MAC over the REPORTMACSTRUCT with report-type 
specific MAC key.N
Table 2-6.  SEAMREPORT

0x00: SGX
REPORTMACSTRUCT 0 256 REPORTMAC Structure for REPORT.
TEE_TCB_INFO 256 239 TEE_TCB_INFO whose HASH is  found in the REPORTMACSTRUCT.2-8 Ref. # 343754-002VMX INSTRUCTION SET EXTENSIONS
SEAMOPS Leaf Functions
SEAMREPORT Leaf
Helps create a SEAMREPORT structure that contains th e measurements/configuration information of the SEAM 
and, when invoked on behalf of a TEE, it includes  the TEE measurements. The SEAMREPORT operands are 
described in Table 2-7.
SEAMREPORT Leaf Description
This instruction is used by the Intel TDX module and he lps create a report, SEAMREPORT, of the Intel TDX module 
or a TEE (e.g., TD) hosted by the Intel TDX module . The SEAMREPORT structure can contain the measure-
ments/configuration information of the TEE, the Intel TDX module, and any additional components in the TEE TCB. 
The SEAMREPORT has a REPORTMACSTRUCT that is designed to be integrity protected with a MAC that covers the 
TEE_TCB_INFO_HASH, the TE E_INFO_HASH (when provided), and the REPORTDATA. The TEE_TCB_INFO_HASH is 
meant as the SHA384 hash of the TEE_TCB_INFO structur e, which reflects the measurement/configuration of the 
SEAM and other elements in the TCB of all instances of T EE hosted by the SEAM. The VALID field contains an array 
of flags that can indicate which fields have been populated,  as not all fields apply to all reports. When used by the 
Intel TDX module to create a TEE report, the TEE_INFO_H ASH is expected to be a SHA384 hash of measurement 
and configuration of the TEE being re ported. When used to report just the Intel TDX module, TEE_INFO_HASH 
might be a string of zeros.
The Intel TDX module can select the report type values, ho wever, all valid values for REPORTTYPE.TYPE should have 
the high order bit set to 1. Failure to set this bit will result in a SEAM_INVALID_REPORT_TYPE error. The Intel TDX 
module additionally helps provide the REPORTDATA, a 64-byte value to be incl uded in the SEAMREPORT and, even-
tually, the quote. This aids the caller of the instruction in  associating data with the Intel TDX module or the TEE it 
reports.
To assist verification of the integrity of the SEAMREPORT , software should help verify any hashes present in the 
report. The REPORTMACSTRUCT.TEE_TCB_ INFO_HASH should match the hash of SEAMREPORT.TEE_TCB_INFO. If 
the REPORTMACSTRUCT.TEE_INFO_HASH is non-zero, it shou ld match the hash of the separate, TEE_INFO struc-
ture. By design, if either value does not match,  the report has been tampered. Software uses 
ENCLU[EVERIFYREPORT2] to help verify the integrity of the REPORTMACSTRUCT itself.Table 2-7.  SEAMREPORT Operands
Operand In / Out Description
RAXIn 1 (SEAMOPS instruction leaf number).
Out Leaf-specific return code.
RCX In 1024B-aligned linear address, of newly created SEAMREPORT structures.RDX In Report Type Header in the low order 32 bits. Upper 32 bits must be zero.
R8 In 64B-aligned linear address of REPORTDATA to be signed.
R9 In 64B-aligned linear address of  TEE_INFO_HASH to be signed.
Table 2-8.  SEAMREPORT Memory Operands
Explicit / 
ImplicitLinear Address Name Access 
PermissionsAlignment Concurrency 
Restrictions
Explicit RCX SEAMREPORT RW 1024B NoneExplicit R8 REPORTDATA R 64B NoneExplicit R9 TEE_INFO_HASH R 64B NoneRef. # 343754-002 2-9VMX INSTRUCTION SET EXTENSIONS
SEAMREPORT Leaf Operation
// Temporary Variables setup with input register operands
SEAMREPORT *tmp_seamreport_la = RCX;    // Linear address of SEAMREPORTuint64_t                  tmp_report_type = RDX;        // Report typevoid              *tmp_reportdata_la = R8;       // Linear address of REPORTDATA
SHA384_HASH_t *tmp_tee_info_hash_la = R9 ; // Linear address of TEE_INFO_HASH
KEY256_t               tmp_report_key;                   // 256b report key
RAX = SEAM_SUCCESS;
RFLAGS.{ZF, CF, PF, AF, OF, SF} = 0;
// Ensure SEAMREPORT pointer is 1024B aligned and read/write accessible
IF ( tmp_seamreport_la is not 1024B aligned) #GP(0);<< tmp_seamreport_la must be read/write accessible>>
// Ensure TEE_INFO_HASH pointer is 64B aligned and read accessible
IF ( tmp_tee_info_hash_la is not 64B aligned) #GP(0);<< tmp_tee_info_hash_la mu st be read accessible>>
// Ensure REPORTDATA pointer is 64B aligned and read accessible
IF ( tmp_reportdata_la is not 64B aligned) #GP(0);<< tmp_reportdata_la must be read accessible>>
// Check reserved bit in REPORT TYPE and that TYPE reflects SEAM implementation
IF ((tmp_report_type & 0xFFFFFFFFFF000000) != 0) || (tmp_report_type & 0x0000000000000080) == 0)){
RAX = SEAM_INVALID_REPORT_TYPE;RFLAGS.ZF = 1;GOTO END;
}
// Create SEAMREPORT in a temporary buffer
tmp_seamreport = 0;tmp_seamreport.REPORTMACSTRUCT.REP ORTTYPE = tmp_report_type[31:0];
tmp_seamreport.REPORTMAC STRUCT.RESERVED = 0x00;
tmp_seamreport.REPORTMACST RUCT.CPUSVN = CRPL_CPUSVN;
// Populate TEE_TCB_INFO depend ing on the Intel TDX module type
tmp_seamreport.TEE_TCB_INFO.TEE_TCB_S VN = CRPL_TEE_TCB_INFO.TEE_TCB_SVN;
tmp_seamreport.TEE_TCB_INFO.MRSEA M = CRPL_TEE_TCB_INFO.MRSEAM;
IF (<Intel SEAM>){
tmp_seamreport.TEE_TCB_INFO.VALID = 111111111b;
}ELSE{
tmp_seamreport.TEE_TCB_INFO.VALID = 1111111111111111b;tmp_seamreport.TEE_TCB_INFO.MRSIGNERSEA M = CRPL_TEE_TCB_INFO.MRSIGNERSEAM;
tmp_seamreport.TEE_TCB_INFO.ATTRIBUTES  = CRPL_TEE_TCB_I NFO.ATTRIBUTES;
}tmp_seamreport.REPORTMACSTRUCT.TEE_TCB_INFO_H ASH = SHA384(tmp_seamreport.TEE_TCB_INFO);2-10 Ref. # 343754-002VMX INSTRUCTION SET EXTENSIONS
// Copy TEE_INFO_HASH an d REPORTDATA from memory
tmp_seamreport.REPORTMACSTRUCT.TEE_ INFO_HASH = *tmp_tee_info_hash_la;
tmp_seamreport.REPORTMACSTRUCT.R EPORTDATA = *tmp_reportdata_la;
// Compute MAC on the first 224B of REPORTMACSTRUCT
tmp_report_key = CR_REPORT_KEY2;tmp_seamreport.REPORTMACSTRUCT.MAC = HMAC-SHA256(tmp_report_key, &tmp _seamreport.REPORTMACSTRUCT, 224);
 
// Copy out report to memory*tmp_seamreport_la = tmp_seamreport;
END:
ZF: Set if failed due to an error (see error co des below); otherwise, it is cleared to zero.
CF, PF, AF, OF, SF: Cleared to zero.
Error Codes
•SEAM_SUCCESS (0x00): SE AMREPORT is successful.
•SEAM_INVALID_REPORT_TYPE (0x01): Invalid report type.
#GP(0): If a memory address is non-canonical form.
#PF(fault-code): If a page fault occurs in accessing memory operands.Ref. # 343754-002 2-11VMX INSTRUCTION SET EXTENSIONS
SEAMRET — Return to Legacy VMX Root Operation
This instruction helps the SEAM VMX root software exit fr om SEAM VMX root operation and resume execution of the 
VMM software in legacy VMX root operation.
SEAMRET from the P-SEAMLDR clears the current VMCS st ructure pointed to by the current-VMCS pointer. A VMM 
that invokes the P-SEAMLDR using SEAMCALL must relo ad the current-VMCS, if re quired, using the VMPTRLD 
Operation
IF inSEAM==0 or ((IA32_EFER.LMA & CS.L ) == 0) or in VMX non-root operation
     THEN #UD;ELSIF CPL > 0     THEN #GP(0);ELSIF current-VMCS po inter is not valid
     THEN VMfailInvalid;Check settings of VMX contro ls and host-state area;
IF invalid settings    THEN          VMfailValid(VM entry with invalid VMX-control field(s)) or
         VMfailValid(VM entry with invalid host-state field(s)) as appropriate;
    ELSE         Attempt to load guest stat e including event inhibits (NMI, SMI, etc.) 
         and PDPTRs as ap propriate based on entry controls;
         Clear ad dress-range monitoring;
         IF failure in checking guest state or PDPTRs
             THEN VM entry fails //  see Section 26.8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volum e 3C
             ELSE                Attempt to load MSRs from VM-e ntry MSR-load area;
                IF failure                    THEN VM entry fails // see Section 26.8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manua l Volume 3C
                    ELSE
current-VMCS = current-VMCS.VMCS-link-pointerIF inP_SEAMLDR == 1
THEN
            If curr ent-VMCS != FFFFFFFF_FFFFFFFFH
                   THEN                        Ensure da ta for VMCS referenced by  current-VMC is in memory
                        Initialize implem entation-specific data in all VM CS referenced by current-VMCS
                        Set launch state of VMCS referenced by current-VMCS to “clear”
                    current-VMCS = FFFFFFFF_FFFFFFFFH
               FI;           inP_SEAMLDR = 0Opcode/
66 0F 01 CD
SEAMRETZO Return to legacy VMX root operation from SEAM VMX root operation.
ZO NA NA NA NA2-12 Ref. # 343754-002VMX INSTRUCTION SET EXTENSIONS
           Release P_SEAMLDR_MUTEX
    FI;
 inSEAM = 0 // Closes SEAMRR access
VM entry succeeds;
                FI;         FI;FI;
// Further details of the operation of the VM-entry appear in Ch apter 26 of the Intel® 64 and IA-32 Architectures Software Deve loper’s 
Manual Volume 3C.
The operation section uses the pseudo-functions VMsucceed, VMfail(ErrorNum ber), VMfailInvalid, and

Initialize implem entation-specific data in all VM CS referenced by current-VMCS
66 0F 01 CD
    FI;
                FI;         FI;FI;
The operation section uses the pseudo-functions VMsucceed, VMfail(ErrorNum ber), VMfailInvalid, and 
VMfailValid(ErrorNumber). See the operation section and Section 2.1. See Section 2.2 for error numbers. The 
following error numbers can be repo rted by SEAMRET: 7, 8, and 26.
#UD The SEAMRET instruction is not designed  to be recognized in protected mode.
#UD The SEAMRET instruction is not designed  to be recognized in real-address mode.
#UD The SEAMRET instruction is not designed  to be recognized in virtual-8086 mode.
#UD The SEAMRET instruction is not designed to be recognized in compatibility mode.
#UD If logical processor is no t in SEAM VMX root operation.
If IA32_VMX_PROCBASED_CTLS3[5] is 0.Ref. # 343754-002 2-13VMX INSTRUCTION SET EXTENSIONS
TDCALL — Call to VM Monitor from TD Guest
This instruction is designed to allow guest privileged so ftware to make a call for service into a VM monitor. The 
details of the programming interface for such calls are In tel TDX module-specific; this instruction can cause a VM 
exit, registering the appropriate, exit reason. Use of th is instruction outside VMX non-root operation can cause 
#UD fault.
Operation
IF not in VMX non-root operation THEN #UD;
ELSIF CPL > 0 THEN #GP(0);ELSE VM exit with  exit reason TDCALL (4DH) and zero exit qualification
None.
#UD If logical processor is not in VMX non-root operation.
If IA32_VMX_PROCBASED_CTLS3[5] is 0.Opcode/
66 0F 01 CC
TDCALLZO Call to VM monitor by  causing a VM exit.
ZO NA NA NA NA2-14 Ref. # 343754-002VMX INSTRUCTION SET EXTENSIONS
VMRESUME/VMLAUNCH — Resume/Launch Virtual Machine
The following additional actions can be performed by VMRESUME/VMLAUNCH in SEAM VMX root operation:
1. If the “enable EPT” VM-execution control is 0, then  cause a VM entry failure due to invalid control field.
2. Shared-EPTP execution control must not set any reserved bits.Ref. # 343754-002 3-1INTEL® SGX INSTRUCT ION SET EXTENSIONS
CHAPTER 3
The ENCLU instruction defines a new leaf, EVERIFYREPORT2, that can be used to help verify the MAC on reports 
generated using SEAMOPS[SEAMREPORT]. CPUID leaf 12, su b-leaf 0, EAX bit 7 is set to 1 to help enumerate 
support for the EVERIFYREPORT2 leaf of ENCLU. The EVERIF YREPORT2 instruction layout is described in Table 3-1.
3.1 EVERIFYREPORT2 LEAF DESCRIPTION
This enclave mode instruction enables verification of a cryptographic REPORTMACSTRUCT that describes the 
contents of a TD, and the REPORTMACSTRUCT can be used to determine that the TEE described in the TDREPORT 
was running on the same platform.
The instruction flow is designed as follows:
1. Verify alignment requirements of the operands.2. Validate the operand (RBX) is inside the enclave.
3. Compute a MAC over REPORTMACSTRUCT structure.
4. Determine if the computed MAC matches the MA C attached to the REPORTMACSTRUCT structure.
OperationTable 3-1.  EVERIFYREPORT2 Instruction Layout
Instruction EAX RBX RCX RDX
EVERIFYREPORT2 08H REPORTMACSTRUCT 
Opcode /
EAX = 08H
ENCLU[EVERIFYREPORT2]Verifies a cryptographic repo rt of the TD. RBX holds the address of a REPORTMACSTRUCT.
Table 3-2.  EVERIFYREPORT2 Memory Parameter Information
Memory Parameter Permissions Semantics
[RBX]REPORTMACSTRUCT R Enclave Access
Table 3-3.  Temp Variables in EVERIFYREPORT2 Operational Flow
Variable Name Type Size DescriptionTMP_CURRENTSECS Effective Address 32/64 Bytes The address of the SECS for the currently executing 
enclave.
TMP_REPORTMACSTRUCT REPORTMACSTRUCT 256 By tes Cryptographic Report of the TEE.
TMP_MAC MAC 32 Bytes MAC over REPORT calculated by instruction.3-2 Ref. # 343754-002INTEL® SGX INSTRUCTION SET EXTENSIONS
// check alignment of  REPORTMACSTRUCT
IF (DS:RBX is not 256 Byte aligned) #GP(0);
// check to see if REPORTMACSTRUCT is inside the current enclave
IF (DS:RBX is not within CR_ELRANGE) #GP(0);
// make sure DS:RBX is read accessible
<< DS:RBX should be read accessible >>
// read EPCM VALID, PENDING, MODIFIED, BLOCKED, PT, R, W, X, and ENCLAVESECS 
// fields atomically check that DS:RBX is a valid and accessible EPC pageIF ((DS:RBX does not reso lve to an EPC address) OR
    (EPCM(DS:RBX).VALID = 0) OR    (EPCM(DS:RBX).PENDING = 1) OR     (EPCM(DS:RBX).MODIFIED = 1) OR    (EPCM(DS:RBX ).BLOCKED = 1) OR
    (EPCM(DS:RBX).R is 0) OR    (EPCM(DS:RBX).PT != PT_REG) OR    (EPCM(DS:RBX).ENCLAVESECS != CR_ACTIVE_SECS) OR    (EPCM(DS:RBX).ENCLAVEA DDRESS != (DS:RBX & ~0xFFF)))
{    #PF(DS:RBX);}
// Create local/protected copy of REPORTMACSTRUCT
TMP_REPORTMACSTRUCT[255:0B] = DS:RBX[255:0B];
// Verify REPORTMACSTRUCT header
IF ((TMP_REPORTMACSTRUCT.TYPE != 0x81) OR   // TDX implemented by Intel TDX module    (TMP_REPORTMACSTRUCT.REPORTTYPE.SUBTYPE != 0x00) OR    (TMP_REPORTMACSTRUCT.R EPORTTYPE.VERSION != 0x00) OR
    (TMP_REPORTMACST RUCT.RESERVED != 0))
{       RFLAGS.ZF = 1;       RAX = SGX_ INVALID_REPORTMACSTRUCT;
       goto EXIT;}
// Verify CPUSVN is a valid value
IF (TMP_REPORTMACSTRUCT.CPUSVN is unsupported by the CPU) {      RFLAGS.ZF = 1;      RAX = SG X_INVALID_CPUSVN;
      goto EXIT}
// Verify MAC on REPORTMACSTRUCT
TMP_MAC = MAC(CR_REPORT_KEY2, TMP_ REPORTMACSTRUCT[223:0B], 224);
IF (TMP_MAC != TMP_REPORTMACSTRUCT.MAC){    RFLAGS.ZF = 1;    RAX = SGX_INVALID_REPORTMACSTRUCT;    goto EXIT}RAX=0;Ref. # 343754-002 3-3INTEL® SGX INSTRUCT ION SET EXTENSIONS
RFLAGS.ZF=0;
EXIT:
RFLAGS.CF=0;RFLAGS.PF=0;RFLAGS.AF=0;RFLAGS.OF=0;RFLAGS.SF=0;
None.
•SGX_INVALID_CPUSVN (32): If REPORTMACSTRUCT.CPUSVN is an unsupported value.
•SGX_INVALID_REPORTMACSTRUCT (28): REPORTMACSTRUCT included illegal values or MAC verification 
failed.
If the DS segment is unusable.
#PF(fault-code) If a page fault occurs in accessing memory operands.3-4 Ref. # 343754-002INTEL® SGX INSTRUCTION SET EXTENSIONS 
 Copyright © 2023 Intel Corporation.  All rights reserved.   
 
Intel® TDX Connect Architecture 
Specification 
 
354629 001-US 
March 2023  
Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 2 of 40 Notices and Disclaimers 
Intel Corporation (“Intel”) provides these materials as-is, with no express or implied warranties. 
representative to obtain the latest Intel product specifications and roadmaps. 5 
deviate from published specifications.  Current, characterized errata are available on request. 
or simulated.  Your costs and results might vary. 
No product or component can be absolutely secure. 10 
concerning Intel products described herein.  You agree to grant Intel a non-exclusive, royalty-free license to any patent 
claim thereafter drafted that includes the subject matter disclosed herein. 
No license (express, implied, by estoppel, or otherwise) to any intellectual-property rights is granted by this document. 
obtained by calling 1-800-548-4725 or by visiting http://www.intel.com/design/literature.htm.  
Other names and brands might be claimed as the property of others.   20 
  Intel® TDX Connect Architecture  354629 001-US

  Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 3 of 40 Table of Contents 
Contents 
 ..................................................................................................................................................................................... 1  
Notices and Disclaimers  .............................................................................................................................................. 2  
Chapter 1:  About This Document  ........................................................................................................................... 4  5 
1.1. Scope of this Document  ......................................................................................................................................... 4  
1.2. Document Organization  ........................................................................................................................................ 5  
1.3. Glossary ................................................................................................................................................................ 5  
1.4. Notation ................................................................................................................................................................ 7  
1.5. Specification References  ....................................................................................................................................... 8  10 
Chapter 2:  Introduction  .......................................................................................................................................... 9  
2.1. IO Virtualization with TDX vs. TDX Connect  ..................................................................................................... 10  
2.2. System Overview  ................................................................................................................................................. 11  
2.3. Security Model  .................................................................................................................................................... 12  
2.4. Capabilities and Features  ................................................................................................................................... 13  15 
2.4.1. TEE-IO Transactions and Requirements  .................................................................................................... 14  
2.4.1. Standard and Device Interoperability  .......................................................................................................... 16  
2.4.2. Device (DSM) and Host (TSM) Requirements  ........................................................................................... 21  
Chapter 3:  Architecture Overview  ........................................................................................................................ 23  
3.1. TEE-IO Capable Device and DSM  ..................................................................................................................... 23  20 
3.2. Integrity and Data Encryption  ............................................................................................................................ 24  
3.3. Trusted IO Access Controls  ................................................................................................................................ 26  
3.3.1. Trusted MMIO Security Objectives  ............................................................................................................ 26  
3.3.1. Secure MMIO Management ........................................................................................................................ 29  
3.3.2. Trusted DMA Security Objectives  .............................................................................................................. 30  25 
3.3.3. Trusted DMA Translation  ........................................................................................................................... 32  
3.4. TDX Module Extensions for TDX Connect and TEE-IO Support  ....................................................................... 35  
3.4.1. Discovery and Enabling of TDX Connect on TDX host platform  .............................................................. 35  
3.4.2. SPDM Management and the Intel TDX Connect TEE-IO provisioning agent (TPA) TD  .......................... 36  
3.4.3. IDE Setup  .................................................................................................................................................... 38  30 
3.4.4. TDI Assignment to TD  ............................................................................................................................... 39  
 Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 4 of 40 Chapter 1:  About This Document 
1.1. Scope of this Document 
This document describes Intel® TDX Connect architecture for CPU host side implementation of TDISP 1.0 (PCI-SIG) 
standard as extension of Intel VTd and Intel TDX Architectures. 
Intel TDX Connect architecture supports TDI assignment of external PCIe devices using SR-IOV (Single Root I/O 5 
Virtualization) and Direct Device (DDA) models. This is the first generation of Intel TDX Connect architecture and 
its scope does not include support for advanced VTd, PCIe or CXL features. 
This document is part of the Intel TDX Connect Architecture Specification Set , which includes the following 
documents: 
Table 1.1:  TDX Connect Architecture Specification Set 10 
 Document Name Reference Description 
 Intel® TDX Connect Architecture [TDX Connect Spec] System architecture overview and 
specification for Intel® TDX Connect 
 Intel® TDX Module 2.0 Module Base 
Architecture [TDX Module Base 
Spec] TDX module 2.0 base architecture 
overview and specification 
 Intel® TDX Module TDX Connect 
Architecture [TDX Module TDX 
Connect Spec] Architecture overview and specification for 
TDX module support for Intel® TDX 
Connect 
 Intel® TDX Module 2.0 Module 
ABI Reference [TDX Module ABI 
Spec] Detailed TDX module 2.0 Application 
Binary Interface (ABI) reference 
specification, covering the entire TDX 
module architecture 
 Intel® TDX Connect TEE-IO provisioning 
agent (TPA) Architecture [TPA Spec] Detailed specification for the Intel® TDX 
Connect TEE-IO provisioning agent (TPA) 
 Intel® TDX Connect SW Guide [TDX Connect 
Software Guide] Software guide for enabling VMM and OS 
with Intel® TDX Connect 
 Intel® TDX Connect Device Attestation 
Guide [TDX Connect 
Attestation Guide] An introductory overview of the device 
attestation for confidential computing and 
compatible with Intel® TDX Connect 
 Intel® TDX 2.0 Guest-Hypervisor 
Communication Interface [TDX GHCI 2.0] Specification of the software interface 
between the Guest OS (Tenant, Service TD 
VMs, and Architectural TD VMs) and the 
VMM required for enabling Intel TDX 
Module 2.0 
 Intel® TDX Connect TEE-IO Device Guide [TDX Connect TEE-
IO Device Guide] An introductory overview on how to build 
TEE-IO device for confidential computing 
compliant with PCIe TDISP 1.0 and 
 
document does not imply any product commitment from Intel to anything in terms of features and/or behaviors. 
Note: The contents of this document are accurate to the best of Intel’s knowledge as of the date of publication, though 
Intel does not represent that such information will remain as described indefinitely in light of future research 15 
and design implementations.  Intel does not commit to update this document in real time when such changes 
occur. Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 5 of 40 1.2. Document Organization 
The document has multiple chapters: 
 Chapter 2 contains the Intel® TDX Connect introduction and overview 
 Chapter 3 contains the Intel® TDX Connect architecture 
1.3. Glossary 5 
Table 1.2:  Intel TDX Glossary for TDX Connect 
Acronym Full Name Description 
ACS Access Control 
Service PCIe ACS defines a set of control points within a PCI Express topology 
to determine whether a TLP is to be routed normally, blocked, or 
redirected. ACS is applicable to RCs, Switches, and Multi-function 
Devices (See [PCIe Base spec]) 
ATS Address Translation 
Service ATS is a PCIe extended capability which uses a request-completion 
protocol between a Device and a root complex (RC) to provide  
translation services. In addition, a new AT field is defined within the  
memory read and memory write TLP to enable the RC to determine 
whether a given request has been  translated or not via the ATS 
protocol (See [PCIe Base spec]) 
CMA/SPDM Component 
Measurement and 
Authentication Component Measurement and Authentication/SPDM (CMA/SPDM) 
defines optional security features based on the adaptation of the data 
objects and underlying protocol defined in [SPDM]. These provide

objects and underlying protocol defined in [SPDM]. These provide 
mechanisms to perform security exchanges (where this term is used 
generically to refer to all defined capabilities of [SPDM]) with a 
component, or device/function (See [PCIe Base spec] and [SPDM Spec]) 
CPL Completion Completion PCIe TLP. All read, non-posted write, DMWR, and AtomicOp 
requests require Completion. Completions include a Completion header 
that, for some types of Completions, will be followed by some number 
of DWs of data (See [PCIe Base spec]) 
DOE Data Object 
Exchange Data Object Exchange (DOE) is a PCIe optional mechanism for system 
firmware/software to perform data object exchanges with a function or 
RCRB. Software discovers DOE support via the Data Object Exchange 
(DOE) extended capability structure (See [PCIe Base spec]) 
DSM Device Security 
Manager Device Security Manager (DSM) is a logical entity in the device that may 
be admitted into the TCB for a TVM by the TSM and enforces security 
policies on the device (See [TDISP spec]) 
FLR Function Level 
Reset FLR is a PCIe optional mechanism which enables software to quiesce 
and reset endpoint hardware with function-level granularity (See [PCIe 
Base spec]) 
 
IDE Integrity & Data 
Encryption Extended PCIe capability for Integrity & Data Encryption (IDE) for 
confidentiality, integrity, and replay protection of PCIe transport layer 
packets (See [PCIe IDE spec]) 
IDE_KM IDE Key 
Management IDE Key Management (IDE_KM) protocol builds upon [SPDM] and 
[Secured-SPDM], and can be used over multiple transports (See [PCIe 
IDE spec]) 
IOMMU Input–Output 
Memory 
Management Unit CPU-RC Input-Output Memory Management Unit (IOMMU) that 
translates device virtual addresses to physical addresses Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 6 of 40 Acronym Full Name Description 
KCBAR Key Config Bar Intel CPU implementation of PCIe IDE key configuration interface (See 
[Intel RC IDE Programing Guide]) 
RC Root Complex PCIe root of an I/O hierarchy that connects the CPU/memory 
subsystem to the I/O. RC may support one or more PCI Express Ports. 
Each interface defines a separate hierarchy domain (See [PCIe IDE 
spec]) 
RP Root Port A PCIe port on a root complex that maps a portion of a hierarchy 
through an associated virtual PCI-PCI bridge (See [PCIe Base spec]) 
EP End Point Function that can be the Requester or Completer of a PCI Express. 
Endpoints are classified as either legacy, PCI Express, or root complex 
Integrated Endpoints RCiEPs (See [PCIe Base spec]) 
SPDM Secure Protocol and 
Data Model The Security Protocol and Data Model (SPDM) Specification which 
defines messages, data objects, and sequences for performing message 
exchanges between devices over a variety of transport and physical 
media. (See [SPDM spec]) 
TCB Trusted Computing 
Base A trusted computing base (TCB) is everything in a computing system 
that provides a secure environment for operations. This includes its 
hardware, firmware, software, operating system, physical locations, 
built-in security controls, and prescribed security and safety 
procedures. 
TDI TEE Device 
Interface The unit of assignment for an IO-virtualization capable device. For 
example, a TDI may be an entire device, a non-IOV Function, or a VF 
(See [TDISP spec]) 
TEE Trusted Execution 
Environment A secure area of a main processor. It guarantees code and data loaded 
inside to be protected with respect to confidentiality and integrity. 
 
TEE-IO Trusted Execution 
Environment for IO 
devices A conceptual framework for establishing and managing Trusted 
Execution Environments (TEEs) that include a composition of resources 
from one or more devices (See [TDISP spec]) 
TSM TEE Security 
Manager The TEE security manager (TSM) is a logical entity in a host that is in 
the TCB for a TVM and enforces security policies on the host (See 
[TDISP spec]) 
TVM TEE Virtual Machine A Trusted Execution Environment Virtual Machine as defined in the TEE 
Device Interface Security Protocol (TDISP) reference architecture 
March 2023  Page 7 of 40 1.4. Notation 
When specifying requirements or definitions, the level of commitment is specified following the convention of RFC-2119 
keywords for use in RFCs to indicate Requirement Levels, as described in the following table: 
Table 1.3:  Requirement and Definition Commitment Levels 
Keyword Description 
Must “Must”, "Required " or "Shall" means that the definition is an absolute 
Must Not “Must Not ” or "Shall Not " means that the definition is an absolute 
prohibition of the specification.  
 
Should “Should”, or the adjective " Recommended ", means that there may 
exist valid reasons in particular circumstances to ignore a particular 
item, but the full implications must be understood and carefully 
weighed before choosing a different course.  
 
Should Not “Should Not ”, or the phrase " Not Recommended " means that there 
may exist valid reasons in particular circumstances when a particular 
behavior is acceptable or even useful, but the full implications should 
be understood, and the case must be carefully weighed before 
May “May”, or the adjective " Optional ", means that an item is 
discretionary. An implementation may choose to include the item, 
while another may omit the same item, because of various reasons.  
  5 Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 8 of 40 1.5. Specification References 
Table 1.4:  Specification References 
Document Name Reference Version & Date 
Intel® 64 and IA-32 Architectures Software Developer’s Manual 
Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 [Intel SDM]  325462-078US, 
December 2022 
Intel® Virtualization Technology for Directed I/O Architecture 
Specification [Intel VTd]  319433-040, 
June 2020 
Root Complex IDE Key Configuration Unit - Software 
Programming Guide [Intel RC-IDE Guide]  732838-001, 
June 2022 
PCI Express Base Specification Revision 5.0, Version 1.0 [PCIe Base Spec] Rev 5.0 Ver 1.0, 
May 2019 
ECN - Data Object Exchange [DOE Spec] Rev 1.1, 
 September 2022 
TEE Device Interface Security Protocol (TDISP) [TDISP Spec] Rev 1.0 
July 2022 
Integrity and Data Encryption (IDE) – Revision A [IDE Spec] Rev A, 
October 2021 
Security Protocol and Data Model (SPDM) Specification [SPDM Spec] Ver 1.2.1, 
June 2022 
Secured Messages using SPDM Specification [Secure SPDM Msg] Ver 1.1, 
May 2022 
 
March 2023  Page 9 of 40 Chapter 2:  Introduction 
2.1 IO Virtualization  
IO virtualization refers to the virtualization and sharing of I/O devices across multiple VMs or container instances. There 
are multiple existing approaches for IO virtualization that may be broadly classified as either software-based or hardware-
assisted. 5 
With software based I/O virtualization, the hypervisor exposes a virtual device, such as a Network Inter- face Controller 
(NIC), to a VM. A software device model in the hypervisor or host OS emulates the behavior of the virtual device. The 
device model translates from virtual device commands to physical device commands before forwarding to the physical 
device. 
Modern processors provide features to reduce virtualization overhead that may be utilized by VMMs to allow VMs direct 10 
access to hardware resources. 
This includes capabilities for direct memory access (DMA) and interrupt remapping and isolation that can be utilized to 
minimize the overheads of IO virtualization. 
Specifically, Intel supports the following hardware assisted IO virtualization schemes for direct data movement without 
needing software assistance: 15 
• Direct Device Assignment: Assignment of entire device to a VM 
• Single Root I/O virtualization (SR-IOV): Assignment of a device virtualized function. 
• Scalable I/O virtualization (S-IOV): Assignment of low-level device interfaces composed by the VMM virtualize a 
device. 
  20 Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 10 of 40 2.1. IO Virtualization with TDX vs. TDX Connect 
Base Intel® TDX hardware prohibits devices from directly accessing TD private memory. Therefore, only software-based 
IO virtualization is supported. The untrusted hypervisor exposes a virtual device, such as a Network Interface Controller 
(NIC), to a TD using shared (untrusted) synthetic IO and para-virtualized device interfaces managed by the VMM (See 
[TDX Module Base Spec] “I/O support” section). 5 
The software-based IO model is slow because the communication between the TD and the device is done through shared 
memory bounce-buffers which require the TD guest to copy and encrypt back and forth the data between the private 
memory buffers of applications running inside the TD and the shared IO buffer used by the device. 
For some IO use cases, such as networking and storage, TD may employ software based cryptographic techniques for

device. 
For some IO use cases, such as networking and storage, TD may employ software based cryptographic techniques for 
data protection, however this approach suffers from performance overhead vs. VTd direct IO virtualization low latency 10 
and high throughout. Besides the performance overhead, the cryptographic data protection does not allow the TD to 
offload computation to legacy GPU or FPGA accelerators and requires them to be in the TCB of the TD and properly 
protect its secret data. 
 
 Figure 2.1:  IO Virtualization with Intel® TDX vs. Intel® TDX Connect 15 
Intel® TDX Connect is designed to improve IO virtualization for a TD TEE in two aspects: 
• Functionality : Remove the need for TD and devices to use shared buffer for private data including the need to 
establish a secure transport-level session with the device (typically done using a proprietary protocol to adjust 
specific device data processing and transformation needs). 
• Performance : Remove the additional resources and work needed for the data copy-encrypt or copy-decrypt back 20 
and forth between the shared TD-Device buffer and the private TD memory greatly improving the workload 
performance (with respect to bandwidth and latency). 
Intel TDX Connect architecture introduces trusted device assignment to a TD, extending its TD Trusted Compute Base 
(TCB) and to a TEE-IO Device Interface (TDI) while protecting its data in: 
• CPU: Extending Intel TDX hardware with private MMIO and DMA access control and data isolation 25 
• Transport : End to end data protection using PCIe selective IDE streams 
• Device: Extending the TDX module with SPDM, IDE and TDISP support allowing TDs to extend their TEE and TCB 
only to TEE-IO devices they choose to trust 
March 2023  Page 11 of 40 2.2. System Overview 
The host platform hardware may include one or more sockets each with multiple-cores, memory controllers and IO hubs. 
The cores and the IO hubs share a coherent system cache and fabric which is connected to the system memory with 
memory controllers implementing Intel® Multi-Key TME (TME-MK) encryption engine.  
Each IO hub includes an IOMMU and related logic for connecting devices to the coherent fabric within the SOC. A subset 5 
of the IO hubs may include PCIe root-complexes and that are used to connect discrete PCIe devices, while others may 
only support within-package integrated devices. 
The integrated devices are not included in the Intel TDX Connect scope while (a subset of) the discrete PCIe root-complex 
IO hubs have Intel TDX Connect support with bifurcated RPs that may support PCIe IDE extended capability.  
 10 
Figure 2.2:  TDX Connect System Model 
Each PCIe root complex may be connected using bifurcated PCIe link downstream root port to the endpoint device 
directly or via any topology of bridges and switches.  
The devices under a PCIe root-complex could include TDISP-compliant and/or regular PCIe devices. A TDISP-compliant 
device could host one or more TEE-IO Device Interfaces (TDI) which could be assigned to a single TD at any point-in time 15 
a time or alternatively, as regular device interface (e.g., VF) which can be assigned to TDs (via shared memory) or to 
regular VMs. 
The platform system software resembles that of a platform with TDX support. It includes a hypervisor that may host one 
or more VMs and may include an installed TDX Module with Intel TDX Connect support.  
March 2023  Page 12 of 40 2.3. Security Model 
Intel TDX Connect Security Model consists of the following key concepts: 
1. Only the TD owner can decide which TEE-IO device interface (TDI) is trustworthy 
2. TDI may use DMA to access TD private memory only allowed if the TD explicitly allowed it and only while its 
exclusively assigned to that TD 5 
3. TD may use trusted access (TEE-TLP) to TDI MMIO space only if the TD is the current owner of that TDI. 
The Intel TDX Connect trust model requires  each TD to explicitly accept a device into its trust boundary. Device being 
trusted by one TD does not imply that it is in trust boundary of other TDs that have not accepted the device into their 
trust boundary.  
According to TDISP, such a device is in the trust boundary of all TDs that have accepted it into their trust boundary, and 10 
it must maintain per-TD isolation per TDI (e.g., VF). 
A single TDI cannot be shared between TDs, however, a multi-function device (supports multiple TDIs) can be trusted by 
multiple TD-VMs and use a single IDE selective stream to secure the data-path between the CPU host and the TEE-IO 
endpoint device. 
Intel TDX Connect TCB does not include switches and bridges, therefore it is required by the host VMM to setup selective 15 
IDE stream to guarantee end-to-end IDE protection between TD-VM running on the host CPU, and the TDI running on the 
TEE-IO device.  
The below diagram illustrates the Intel TDX Connect trust relationship in which: 
- The TDX Connect host platform and TSM are trusted by all TD-VMs 
- Device-1 is trusted by both TD-VMs since TDI-VF 1 and TDI-VF 2 are assigned to TD-VM 1 and TD-VM 2 respectively 20 
- Device-2 is not trusted by any TD-VM because VF 3  not assigned to any TDI-VM 
- Device-3 is only trusted by TD-VM 1 because TDI-VF 4 is assigned to TD-VM 1 
- Selective IDE stream used to protect the interconnect between the host CPU and the device, the bridges and 
switches use IDE pass-through mode and are not assumed to be trusted by any TD-VM 
 25 
 
Figure 2.3:  TDX Connect Security Model TEE-IO 
Device 1
TDI-VF1TDI-VF2EPTD-VM1TD-VM2
Bridges/SwitchesRP
IDE Stream 1
TEE-IO 
Device 3
TDI-VF4EPIDE Stream 2
Responsible for TDI Isolation and SecurityResponsible for TD-VMIsolation and Security
Device 2
VF3EPTrusted by 
allTD-VMsTDX Connect
Host (+TSM)
Trusted by
TD-VM1and
byTD-VM2Trusted by
TD-VM1(only)Nottrusted
by any TD-VMNottrusted by any TD-VMIntel® TDX Connect Architecture  354629 001-US  
March 2023  Page 13 of 40 2.4. Capabilities and Features 
The following table describes the capabilities and features in scope of Intel TDX Connect architecture. 
Table 2-1: Intel TDX Connect Supported Capabilities and Features 
Focus Area Feature or Capability Intel 
TDX 
Connect 
Support Details 
PCIe IDE Link IDE stream No Using Link IDE streams is enabled for legacy devices 
but not for TEE-IO devices 
Selective IDE stream Yes Up to 4 IDE stream per root complex with number 
IDE stream register blocks per RP depends on per RP 
bifurcation. 
Bifurcation Selective Link 
1x16 4 1 
2x8 3 1 
4x4 1 1 
8x2 N/A N/A 
16x1 N/A N/A 
 
Trusted 
MMIO TD to TEE-IO device Limited Limited to MMIO high (above 4GB) 
Peer-to-Peer Limited Only via-host IOMMU and root complex. Direct 
access via bridges and switches depends on Intel 
TDX Connect ATS support (see below) 
Trusted DMA TEE-IO Device to TD 
Memory Yes Device may access TD private or shared memory 
ATS Trusted Address Translation 
and Translated Requests No Intel TDX Connect threat model requires Secure-ATS 
to ensure translated requests can only access system 
memory of the TDs who accepted them into their 
TCB. This is a future extension for Intel TDX Connect 
Nested 
IOMMU 
Translations Support for TDs to setup 
first level page tables to 
enable DMA access control 
or SVM No  
PF, FV 
Assignment Assignment of PF and VF 
(SR-IOV) Yes  
SVM Trusted PRS Support No  
Scalable IOV 
Support Assignment of Scalable IOV 
R2 Device Support  No  
CXL Type 1,2 Support for CXL devices 
participating host memory 
coherency No TEE-IO standard and requirements for CXL Type 1 
and 2 devices are immature. This may be a future 
Intel TDX Connect extension. 
CXL Type 3 Support for CXL memory 
buffer devices N/A This feature is out of scope for this Intel TDX 
Connect specification and will be described in other 
TDX future specifications. 
March 2023  Page 14 of 40 2.4.1. TEE-IO Transactions and Requirements 
The table below refers to transaction and configuration requirements with respect to TEE-IO transactions from TDs and 
to TDI private MMIO, from TDI to its TD owner private memory or P2P between TDI to another TDI or non-TD device   
assigned to a TD.  
Table 2-2: Trusted Transactions and Requirements 5 
Requirement Requirement Details 
[TXN-1] TEE-IO Enabling  Intel TDX Connect architecture must ensure TEE-IO transactions are only 
allowed if IOMMU has been enabled for Intel TDX Connect. 
[TXN-2] TEE-IO MMIO Decode 
Consistency Intel TDX Connect architecture must check prior to Intel TDX Connect 
enabling per PCIe root complex (and IOMMU) that the untrusted 
platform software configuration of MMIO decoding is locked (cannot be 
modified) and consistent (source to target routing is configured in all 
SOC registers to prevent misrouting of TEE-IO transactions). 
[TXN-3] TEE-IO DMA Decode 
enabling per PCIe root complex (and IOMMU) that the untrusted

platform software configuration of system memory decoding is locked 
(cannot be modified) and consistent (source to target routing is 
configured in all SOC registers to prevent misrouting of TEE-IO 
transactions). 
[TXN-4] TEE-IO IDE and SPDM Intel TDX Connect architecture must ensure TEE-IO transactions are only 
allowed via root complex, and root ports are enabled and configured 
with IDE selective streams using IDE_KM over SPDM session established 
with TEE-IO devices by the Intel TDX Connect TSM (TDX Module and 
TPA). 
[TXN-5] TEE-IO MMIO Source Intel TDX Connect may only allow TEE-IO transactions to MMIO from a 
TD or TDI (P2P) using private GPA mapped in the TD Secure-EPT. 
[TXN-6] TEE-IO MMIO Range Host platform software may only configure TEE-IO MMIO routing via 
selective IDE stream using Intel TDX Connect ABI. These IDE streams may 
only be configured with address association registers that enclose the 
associated RP prefetchable memory range and may only select address 
ranges above 4GB. 
[TXN-7] TEE-IO MMIO Target TDSIP defines DSM rules with respect to device TEE/Non-TEE memory 
access. Intel TDX Connect may not enforce any of device TEE vs non-TEE 
memory access control. 
[TXN-8] TEE-IO DMA Source Intel TDX Connect architecture must only allow TEE-IO transactions to TD 
private memory if and only if the TD explicitly accepted the TDI into its 
TCB (using TDISP protocol). The TDI may not access any other TD private 
memory space until properly stopped and reclaimed from its previous TD 
owner. 
[TXN-9] TEE-IO DMA Range and 
Target IOMMU GPA mapping of TDI to TD private memory space must be 
consistent with the TD GPA to HPA mapping and permissions. 
Intel TDX Connect may not support finer control over TDI access 
permissions to TD on the current architecture (e.g., by allowing TD to 
configure IOVA to GVA translation tables). 
[TXN-10]  TEE-IO MSI/X Intel TDX Connect may not support MSI/X TEE-IO transactions 
[TXN-11]  TEE-IO P2P via root 
complex Intel TDX Connect architecture must allow P2P TEE-IO transactions only 
via the root complex and only with non-translated TLP. 
[TXN-12]  TEE-IO P2P Direct Intel TDX Connect architecture may not support direct P2P between TEE-
IO devices and may not allow TDs to generate TDISP P2P configuration 
messages. Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 15 of 40 Requirement Requirement Details 
[TXN-13]  TEE-IO ATS Intel TDX Connect may not support TEE-IO transactions related to PCIe 
ATS: 
- Translation and Device TLB Request and Completions 
- Translated TEE-IO Request 
[TXN-14]  Non-TEE-IO 
Transactions Intel TDX Connect support must support non-TEE transactions and must 
guarantee such transactions would never become a TEE-IO transaction or 
system memory with TDX private memory semantics. 
[TXN-15]  Implicit Non-TEE-IO 
Transactions Intel TDX Connect architecture must guarantee that any access with 
shared semantics (HPA access not using TDX private KeyID) will result 
with non-TEE transaction. 
[TXN-16]  Device P2P TEE-IO 
Access Intel TDX Connect architecture may allow TEE-IO device to perform 
trusted P2P accesses only if request is non-translated, requestor and the 
responder are both TDI assigned and accepted into the TCB of the same 
TD owner and the address on the target TDI is a private HPA (using TDX 
private KeyID). 
March 2023  Page 16 of 40 2.4.1. Standard and Device Interoperability 
The DOE support below refers to the message transport format of messages generated by the TDX module/TPA (i.e., for 
SPDM, IDE_KM and TDISP protocols). Intel TDX Connect host platform does not expose a DOE mailbox (which is required 
by a TEE-IO device but not by the TEE host platform). 
 5 
Table 2-3: DOE Support and Requirements 
Requirement Details 
[DOE-1] Supported DOE 
versions Intel TDX Connect Architecture supports DOE 1.0 with additional 
enhancements for Data Object types added to DOE 1.1. 
[DOE-2] Supported DOE 
object types Vendor-ID Data Object Type 
0001 01 – CMA/SPDM 
0001 02 – Secure CMA/SPDM 
 
[DOE-3] Non-Supported DOE 
object types  Vendor-ID Data Object Type 
0001 00 – DOE Discovery (VMM/OS DOE discovery 
is a device scope feature) 
0001 03 – CMA/SPDM with Connection ID 
0001 04 – Secure CMA/SPDM with Connection ID 
0001 05 – Async Message 
 
March 2023  Page 17 of 40 Table 2-4: SPDM Support and Requirements 
[SPDM-1]  Supported SPDM 
version Intel TDX Connect supports SPDM version 1.2 
[SPDM-2]  Support for SPDM 
session 
establishment, 
management, and 
teardown with 
TDISP-compliant 
devices It must be feasible to establish, use and teardown SPDM sessions with TDISP-
capable devices for use by TDs.  
 
[SPDM-3]  Supported 
granularities for 
SPDM session 
establishment for 
TDIs SPDM does not mandate a specific device granularity for session 
establishment. For example, all the following configurations are allowed 
depending on device support for the DOE mailbox: 
1 device -> N function -> 1 DOE (in function 0 only) -> 1 SPDM. 
1 device -> N function -> N DOE -> N SPDM 
1 device -> N function -> N DOE -> 1 SPDM (other N-1 DOE is used for other purpose)  
1 device -> N function -> N*M DOE (each function has M DOE) -> N SPDM 
[SPDM-4]  Number of SPDM 
sessions per TDISP 
compliant device/ 
device interface This is not mandated by the specification and is dependent on the device. For 
example, the following is allowed: 
1 DOE -> 1 SPDM 
1 DOE -> N SPDM (with DOE connection ID support in DOE 1.1) 
[SPDM-5]  Number of SPDM 
sessions per SoC 256 per IO stack 
[SPDM-6]  Number of 
outstanding SPDM 
requests 
 Intel TDX Connect architecture shall support unlimited number of outstanding 
secure SPDM message requests (per SPDM session). 
[SPDM-7]  List of SPDM 
messages 
supported  Intel TDX Connect supports the following SPDM protocol request and response 
messages:  
SPDM Request SPDM Response 
GET_VERSION VERSION 
GET_CAPABILITIES CAPABILITIES 
NEGOTIATE_ALGORITHMS ALGORITHMES 
GET_DIGESTS DIGESTS 
GET_CERTIFICATE CERTIFICATE 
GET_MEASUREMENTS MEASUREMENTS 
KEY_EXCHANGE KEY_EXCHANGE_RSP 
FINISH FINISH_RSP 
END_SESSION END_SESSION_ACK 
 
[SPDM-8]  SPDM algorithms Intel TDX Connect supports the SPDM algorithms defined in CMA 1.0 and CMA 
1.1. Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 18 of 40 Requirement Details 
[SPDM-9]  List of SPDM 
messages NOT 
supported  Intel TDX Connect does not require any other messages defined in SPDM 
specification. 
 
Table 2-5: IDE Support and Requirements 
[IDE-1] IDE Version 
Support  Intel TDX Connect supports PCI-SIG, IDE Rev A 
[IDE-2] IDE Host 
Enumeration Platform software must enumerate IDE support on both host and endpoint device 
to determine the common IDE supported features for both Intel TDX Connect 
platform and TDISP device. 
 
Intel RC IDE is compatible with TEE-IO but does not support the TEE-IO 
enumeration via IDE-ECAP. Instead, TDX Connect (and host TEE-IO support) shall 
be enumerated using root complex and IDE discovery mechanism (see [Intel RC-
IDE Guide]) and TDX module extended feature enumeration (see [TDX Module ABI 
Spec]). 
[IDE-3] Support for 
Selective and Link 
IDE streams  Intel TDX Connect CPU implements 4 IDE streams on each x16 PCIe hierarchy. 
Number of Link and selective IDE stream registers per RP depends on per RP 
bifurcation: 
1X16 – 1 link IDE, 4 selective IDE configuration registers per port 
2x8 – 1 link IDE, 3 selective IDE configuration registers per port 
4x4 – 1 link IDE, 1 selective IDE configuration registers per port 
8x2 – No link IDE stream, and no selective IDE configuration registers (not usable 
for Intel TDX Connect) 
[IDE-4] IDE selective 
stream For each IDE selective stream, there is one Address and one RID Association 
Register set per IDE stream. For correct binding of selective IDE streams between 
host and endpoint device, the platform software must program same stream IDs 
with equal RID and Address association ranges and symmetric keys using IDE KM 
protocol for all sub stream before setting the IDE enable control. 
[IDE-5] Intel TDX Connect 
Enable/Disable 
and Host IDE 
Register 
Protection To enable Intel TDX Connect, host platform must first enable TDX mode per PCIe 
hierarchy and each enabled RP using Intel TDX Connect ABI. Once Intel TDX 
Connect is enabled, IDE-ECAP and key programming registers must prevent write 
access to platform software and may only allow write access to TDX module 
(SEAM root mode). 
This protection may only be disabled by a platform reset or by platform software 
using Intel TDX Connect ABI (see [Intel TDX Connect Module Spec]) 
[IDE-6] IDE Management 
and Binding with 
SPDM Session Once Intel TDX Connect is enabled, the host platform software must use Intel TDX 
Connect ABI for setting up Link or selective IDE stream and configuring their keys

Register 
Connect ABI for setting up Link or selective IDE stream and configuring their keys 
using IDE KM protocol. Before IDE stream is created and managed using Intel TDX 
Connect ABI, the platform software must establish the SPDM session with an IDE 
device using Intel TDX Connect ABI (see [Intel TDX Connect Module Spec]) 
[IDE-7] IDE stream Setup 
for TDISP vs. non-
TDISP Device Host platform must use selective IDE for TDISP device and may use either Link or 
selective IDE stream for non TDISP device Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 19 of 40 [IDE-8] IDE_KM Protocol 
Support Intel TDX Connect ABI interface for IDE_KM supports the following response 
messages:  
IDE_KM Request IDE_KM Response 
KEY_PROG KP_ACK 
K_SET_GO 
K_SET_STOP 
 
[IDE-9] Selective IDE 
stream Control Selective IDE stream control address association registers must not be 
programmed to include addresses below 4GB (MMIOL) 
[IDE-10] IDE TLP reserved 
bit checking RP-IDE hardware may not implement reserved bit checking for IDE TLP prefix bit 7 
 
March 2023  Page 20 of 40 Table 2-6: TDISP Support and Requirements  
[DISP-1] Supported TDISP version Intel TDX Connect supports TDISP v1.0 
[DISP-2] Supported TDISP Device 
Interface Modes Intel TDX Connect Architecture support full device (PF) and or virtual 
function (VF) assignment to a TD 
[DISP-3] TEE-IO Device Interface 
Assignment life cycle 
management Platform software must enable TEE-IO device interface (TDI) assignment 
to TD trust boundary using Intel TDX Connect ABI. TDISP devices are first 
assigned to TDs at PENDING state. Meaning, TD, and devices cannot 
generate trusted TLP transactions till this assignment is made PRESENT  
by the TD explicitly calling TDX- guest ABIs.  
For more details refer to [Intel TDX Connect Module Spec]. 
[DISP-4] TEE-IO Device Interface 
Removal by Host 
Platform (Graceful) To remove a TDI from a TD and before it can be assigned to another TD, 
the platform software must use Intel TDX Connect ABI to disable the TDI 
device associated selective IDE stream or to transition its TDISP state to 
CONFIG_UNLOCKED. For more details refer to [Intel TDX Connect 
Module Spec]. 
[DISP-5] List of TDISP protocol 
messages supported Intel TDX Connect supports the following TDISP requests and response 
messages: 
TDISP Request TDISP Response 
GET_TDISP_VERSION TDISP_VERSION 
GET_TDISP_CAPABILITIES TDISP_CAPABILITIES 
LOCK_INTERFACE_REQUEST LOCK_INTERFACE_RESPONSE 
GET_DEVICE_INTERFACE_REPORT  INTERFACE_REPORT 
GET_DEVICE_INTERFACE_STATE GET_DEVICE_INTERFACE_STATE  
START_INTERFACE_REQUEST START_INTERFACE_RESPONSE 
STOP_INTERFACE_REQUEST STOP_INTERFACE_RESPONSE 
Other message types are currently not supported. 
[DISP-6] TEE-IO Enumeration Before using Intel TDX Connect ABI, platform software must use TDX ABI 
to enumerate Intel TDX Connect support.  
 
March 2023  Page 21 of 40 2.4.2. Device (DSM) and Host (TSM) Requirements 
Table 2-7: DSM and TEE-IO Device Requirements 
Intel TDX Connect Device Requirements 
[DSM-1] TEE MMIO Ranges Intel TDX Connect architecture does not support TEE-IO transactions to 
MMIO low (< 4GM) or Configuration Space. Device must expose all TEE 
MMIO resources using 64 BARs. IDE selective stream bound to TDI and 
TDI TEE MMIO ranges must be configured to MMIO high ranges. 
[DSM-2] Device Address Width Devices address width (also reported by TDISP capabilities) must be at 
least 52 bits 
[DSM-3] TEE-IO P2P Device may send and handle trusted P2P TLPs only via the root complex 
IOMMU. Intel TDX Connect CPU host does not support setting P2P IDE 
selective streams required for direct P2P via switches (and via the root 
complex). 
[DSM-4] TEE-IO PASID Device must not use PASID for TEE-IO transactions. During TDI 
configuration it is recommended to disable PASID. 
[DSM-5] TEE-IO ATS Device must not use ATS requests for TEE-IO transactions. During TDI 
configuration it is recommended to disable ATS. 
[DSM-6] TEE-IO PRS Device must not use PRS requests for TEE-IO transactions. During TDI 
configuration it is recommended to disable PRS. 
[DSM-7] TEE-IO CXL.mem/cache Device must not use CXL.mem/cache for TEE-IO transactions. During TEE-
IO enabling or TDI configuration it is recommended by the device to 
downgrade the device to use CXL.io TEE-IO transactions or support PCIe 
only mode. 
[DSM-8] TEE-IO MSI/X  Device must not use MSI/X requests for TEE-IO transactions. Device 
configuration logic must not set the MSI/X locking flag as part as device 
interface TDISP lock request. 
Table 2-8: TSM (TDX Module and TPA Requirements) 
[TSM-1] Intel TDX Connect 
Enumeration TDX module must expose platform Intel TDX Connect feature support 
per the entire platform and per specific IOMMU (PCIe hierarchy) 
[TSM-2] Intel TDX Connect 
Mode TDX module must enable VMM dynamic enable/disable Intel TDX 
Connect mode on each root complex instance which has Intel TDX 
Connect support and was configured by BIOS to enable Intel TDX 
Connect  
[TSM-3] IOMMU, PCIe 
Configuration Lock When Intel TDX Connect mode is enabled, TDX module must also enable 
hardware access controls to ensure IOMMU and PCIe registers relevant 
to Intel TDX Connect security cannot be tampered with by untrusted 
software, firmware, and hardware (e.g., devices). 
[TSM-4] SPDM Setup TPA TD and TDX Module must support SPDM session establishment, 
maintenance, and teardown. 
[TSM-5] Attestation TPA TD and TDX Module must support SPDM gathering for device 
certificates, measurements, and policy information. The device 
information can be transported to TVM via untrusted channel, however, 
the TDX module and the TPA must provide means for the TVM to 
validate such device information integrity and freshness. Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 22 of 40 [TSM-6] IDE Setup TDX module must support VMM ability to setup selective (or Link for 
non-TIDSP, IDE only cases) streams with a device using IDE_KM and 
Secure SPDM transport. The Secure SPDM transport must use TPA TD 
established SPDM Session. 
[TSM-7] TDI (FUNCTION_ID) 
Assignment TDX module must support TDI Assignment to TD ensuring each 
FUNCTION_ID may only be assigned to a single TD at a time. TDX module 
must ensure such TDI must is associated with a selective IDE. 
[TSM-8] TDISP Life Cycle 
Support TDX module must provide VMM and TD interface to manage TDI 
assignment according to TDISP protocol. TDX module must restrict VMM 
to only generate TDI lock, stop and get interface state messages.  
TDX module must provide TD interface to manage TDI assignment 
according to TDISP protocol. TDX module must restrict TD to only 
generate TDI get interface report, get interface state, and start interface 
messages. 
TDX module may not support any non-mandatory TDISP protocol 
message type. 
[TSM-9] Private MMIO 
Management TDX module must track each private MMIO, can be assigned at most to a 
single TDI (FUNCTION_ID), and must provide VMM API for assigning 
private MMIO pages to TDI and mapping them to TDs as PENDING. TDX 
module must provide TD interface to verify and enable such MMIO 
mappings (TVM must call TDX module API to accept each MMIO page 
which appears as TEE MMIO range in the device TDISP report). 
[TSM-10]  Private DMA 
Management TDX module must provide trusted DMA mapping management interfaces 
to VMM to manage TEE-IO DMA translation to TD private memory. Such 
VMM interfaces must be mapped as PENDING. TDX module must provide 
TD interface to verify and enable such DMA mappings (TVM must call 
TDX module API to accept each DMA mapping per FUNCTION_ID as it 
appears in TDISP report message. 
[TSM-11]  TDI Teardown TDX Module must enable VMM initiated teardown of TDI bindings from 
a TD. TDX module must support graceful teardown in which TDI is first 
stopped and then removed from a TD. 
For survivability, in case TD or device are not operational, TDX module 
must provide mechanism to teardown TDI resources (e.g., MMIO, DMA 
mappings) from a TD by first disabling the TDISP bound IDE selective 
stream and then reclaiming all TDI resources using the same interfaces 
used for graceful tear down. 
[TSM-12]  TD GPA.S bit 
position  Intel TDX Connect may not allow VMM to configure the GPA.S bit 
position to be other than 52 (MAX_PA). 
[TSM-13]  Support for TD Live 
Migration Intel TDX Connect supports live TD migration co-existence as long as TDI 
are removed before TD live migration begins and cannot be assigned 
during TD live migration. 
[TSM-14]  Support for TDX 
Module Seamless 
Update Intel TDX Connect supports seamless (impact less) TDX module update. 
During TDX module update TD may not be operational however device 
DMA to TD private memory is possible. 
[TSM-15]  Support for TD 
Partitioning Intel TDX Connect supports TD partitioning such that TDI assignment 
from VMM perspective is done to L1 VMM.

from VMM perspective is done to L1 VMM.  
Intel TDX Connect must support L1 TD ability to accept the TDI 
assignment to its own context to the context of one of the L2 VMs. 
March 2023  Page 23 of 40 Chapter 3:  Architecture Overview 
Intel TDX Connect framework is the Intel implementation of TDISP allowing direct assignment through establishment of 
trust between a TD and a TDI hosted by a TDISP compatible device. 
The Intel TDX Connect framework goals are to enable the following: 
- Establishing trust relationship between a TD and a TDISP device. 5 
- Securing the data-path PCIe interconnect between the host and device. 
- Supporting TDISP assignment and removal life cycle in a trusted manner. 
Specifically, this framework defines the following ingredients: 
1. TEE-IO Capable device and DSM (see [TDISP Spec]) 
2. PCIe Integrity and Data Encryption (see [IDE Spec]) 10 
3. CPU hardware access controls to protect and isolate TEE-IO transactions within the host SOC 
4. TDX module extension to support secure TEE-IO Device Setup and direct TDI assignment to TD 
 
Figure 3.1:  Intel TDX Connect Framework Ingredients 
3.1. TEE-IO Capable Device and DSM  15 
TEE-IO capable devices, as defined in the TEE Device Interface Security Protocol (TDISP) specification, must provide the 
following capabilities: 
1. Authentication, Attestation, and Key Negotiation:  Implementation of the DMTF SPDM 1.2 specification for 
runtime authentication, firmware and configuration measurement reporting, and session key negotiation. 
2. Integrity and Data Encryption (IDE):  The Intel TDX Connect-capable devices support the PCIe/CXL IDE extension 20 
to PCIe to provide confidentiality, integrity, and replay protection of data transferred to or from the device. 
3. Secure Life-Cycle Management:  Implement TDISP state machine for tracking and enforcing device interface 
secure life cycle of configuration, lock, reporting and run enabling secure TDI to TD assignment and removal 
according to TEE Device Interface Security Protocol (TDISP) specification. 
4. Data Security:  Support intra-device resource access control with the same quality of isolation and security 25 
properties as the host for data provided to the device by the TD. 
 The authenticity of a device is determined by digital signatures using well-established techniques based on public key 
cryptography. A device proves its identity by generating digital signatures using a private key. The TD can 
cryptographically verify the signatures using the public key associated with that private key. The private key used by the 
device to prove its identity and authenticity is provisioned into the device by its vendors during or after hardware 30 
manufacturing.  
A trusted root certificate authority (CA) generates a root certificate (Root-Cert) provisioned to the TD. This allows the TD 
to verify the validity of the digital signatures generated by the device during runtime authentication. The root CA also 
endorses a per-part public/private key pair indirectly through the certificate chain, where the private key is provisioned Host
VMMLegacy
VM
TDX 
Connect 
HostSPDM 
Bind
(TDCALL)TDX-IO
Guest APIs
(TDCALL)
TDX 
ModuleTPA
TDTD1
TDX-IO SOCTrusted
IOMMU, MMIOPCIe-IDE
Root PortIOMMU & IDE
Programming Interface
TEE-IO
DeviceLegacy
VF
Physical
FunctionDSM
PCIe-IDE
PortTDI2
TDISPTDI1
TDISP
Bridges/
SwitchesSPDM Secure 
Session
(Attestation, 
TDISP & IDE-KM)TD2Trusted 
DMA, MMIO
Selective
IDE StreamIDE Key IDE KeySPDM 
KeySPDM 
Key4
21
3Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 24 of 40 to or generated by the device.  A device carries a certificate chain with the root being the Root-Cert and the leaf being 
the device certificate (Device-Cert), which contains the public key corresponding to its private key. 
At run time, a TD can retrieve the certificate chain(s) from the device and send a unique challenge to the device. The 
device then signs the challenge with the private key. The TD verifies the signature using the public key of the device as 
well as any intermediate public keys within the certificate chain using the root certificate as the trusted anchor. 5 
TEE-IO capable devices also implement measurement registers which hold the cryptographic hash value of the 
firmware/software or configuration data of the device. In response to a request from the TD, the device provides its 
measurements signed with the private key. This allows the TD to establish the identity and measurements of the 
firmware/software/configurations of the device. 
For more details refer to [TDISP Spec] 10 
3.2. Integrity and Data Encryption  
Intel TDX Connect requires the establishment of a secure connection with a device such that: 
1. Data that flows between the TD and a trusted device must remain confidential, have integrity, and be replay- 
protected, using the keys derived by the TSM. 
2. Metadata associated with transfers (e.g., logical addresses of DMA transfers in the TD’s address space) must be 15 
integrity and replay protected. 
PCIe Integrity & Data Encryption (IDE) specification provides confidentiality, integrity, and replay protection for TLPs 
transmitted and received between two Ports. It flexibly supports a variety of use models, while providing broad 
interoperability. The cryptographic mechanisms used by IDE are aligned with industry best practices and can be extended 
as security requirements evolve. The security model considers threats from physical attacks on links, including cases 20 
where an adversary can examine data intended to be confidential, modify TLP contents, reorder and/or delete TLPs, using 
lab equipment, purpose-built interposers, or malicious extension devices. TLPs can be protected as they transit switches, 
extending the security model to address attacks mounted by reprogramming switch routing mechanisms or using 
malicious switches.  
IDE establishes an IDE stream between two ports.  When there are no switches between the Pports, then it is possible to 25 
secure all, or only selected, TLP traffic on the Link.  For cases with and without switches between the ports, it is possible 
to secure selected TLP traffic. 
 
Figure 3.2:  Selective vs. Link IDE streams 
The Intel TDX Connect security architecture excludes switches from the TCB of TD and devices participating in the Intel 30 
TDX Connect framework. To that effect, the Intel TDX Connect architecture exclusively uses the selective IDE streams to 
protect the TLPs flowing between the SOC root complex and the Intel TDX Connect capable endpoint devices. 
TLPs protected by IDE are called IDE TLPs.  All IDE TLPs must use the IDE TLP prefix, which must precede all other end-
end TLP prefixes.  
March 2023  Page 25 of 40  
Figure 3.3: IDE TLP prefix 
IDE uses AES in Galois/Counter Mode (GCM). For IDE TLPs, TLP data payload content forms the “Plaintext”, also known 
as P, as defined in [AES-GCM], and the TLP Header and certain other elements form the “Additional Authenticated Data”, 
also known as A, as defined in [AES-GCM].  The MAC size, also known as t, as defined in [AES-GCM], must be 96b.  5 
When a selective IDE stream is enabled, matching the TC value in its stream Control Register determines that a 
transmitted TLP is associated with it. Additionally: 
- For ID-Routed Messages and Completions, the destination is in the selective IDE RID Association Register block 
within the range between the RID Base and RID Limit 
- For Memory Requests, Requests, the address is in the selective IDE Address Association Register block within 10 
the range between the Memory Base and Memory Limit 
Received TLPs must be processed according to the stream ID indicated in the IDE TLP Prefix.  
The unit of device assignment to a TD is a TEE Device Interface (TDI). The TDI may be a physical function (direct device 
assignment) or SR-IOV virtual function (VF). To assign a device interface to a TD, a selective IDE stream is first established 
with the device and set as a default IDE stream. On the host root port, the selective IDE address association register is 15 
setup with the address range decoded by the device and the RID association register is set up with the requester ID range 
decoded by the device.  
Once the stream has been established between the host root port and the device all address-routed TLPs sent by the 
host CPU where the address matches the address association registers of that stream, including those originated by non-
TD software, are sent as IDE TLPs using the key associated with that stream. Likewise, all ID routed messages and 20 
completions where the destination matches the RID range configured for that stream, including those originating from 
non-TD software, are sent as IDE TLPs using the key associated with that stream.  
When the device generates TLPs, the stream used for those TLPs is determined in a device specific manner. For Intel TDX

When the device generates TLPs, the stream used for those TLPs is determined in a device specific manner. For Intel TDX 
Connect usages, the TDISP lock interface message is used to configure the Default stream ID into the device such that all 
TLPs generated by the device for the TDI are sent as IDE TLPs using the default stream-id. Likewise, once the stream-id is 25 
configured into the TDI, the device only accepts IDE TLPs where the stream-id in the IDE TLP prefix matches the default 
stream-id.  
Note that according to [TDISP Spec], all TDIs hosted by a TEE-IO device must be locked and bound to the same stream-ID 
which is the default stream.  
When the TDI is assigned to a TD and is in TDISP RUN state, it generates TLPs using the default stream and with the T bit 30 
set to 1. Similarly, access to the TDI private MMIO space (TEE-MMIO) must be made using the default IDE stream ID and 
with the T bit set and only when the TDI is in TDISP RUN state. 
Other device interfaces or when TDI is not in RUN state, must set the T bit to 0 and must not allow access to TD private 
resources (such as TEE-MMIO or TD private memory). 
In summary, the Intel TDX Connect architecture uses the PCIe IDE extension as follows: 35 
 Selective IDE streams are used to secure the TLPs flowing between SOC and devices with TD-assigned interfaces. 
Such devices may have some interfaces assigned to TDs and other interfaces assigned to non-TD software. 
 Transactions originated from TDs set the T-bit in the IDE TLP prefix and the devices accept TLPs accessing TD-assigned 
interfaces only if the T-bit is 1. The T-bit helps the device differentiate between TD and non-TD accesses. The TD 
Secure EPT is used to allow access to MMIO address ranges of the device interfaces assigned to that TD. This way, it 40 
prevents one TD from accessing the MMIO address range of other device interfaces assigned to other TDs. 
 Devices generate IDE TLPs with T-bit set to 1 for device interfaces assigned to TDs. The DMA TLPs with T-bit set to 1 
are translated by the IOMMU using trusted DMA translation tables (discussed later) that allow the device interface 
to access its assigned TD’s private memory. The trusted DMA translation tables prevent a TD-assigned device from 
performing DMA to memory of other TDs. 45 
March 2023  Page 26 of 40 3.3. Trusted IO Access Controls 
IDE provides end-to-end protection over the PCIe link and on the edges of the data transport between TD and its assigned 
TDI. The TEE-IO device DSM ensures that DMA access originated from a TDI will use the default IDE stream and will set 
the T bit on the IDE prefix. TDX Connect CPU and TSM access controls provide isolation for private DMA and MMIO 
accesses between TD and its assigned TDI(s) inside the CPU.  5 
3.3.1. Trusted MMIO Security Objectives 
Intel TDX Connect architecture enabling of trusted MMIO access from TD to TDI must cope with the following problems: 
 Malicious Interference 
Non-TD software, other devices not trusted by TD, or another TD maliciously access MMIO range of a TD assigned 
interface. The malicious interference problem is addressed as follows: 10 
- The TDX module must maintain a MMIO page assignment tracker to ensure each MMIO page can only be 
mapped to a single TD via its Secure-EPT. VMM calls TDX module API to map the MMIO space of the assigned 
device interface its TD owner in the TD Secure-EPT. To ensure MMIO space mapping is done correctly and 
exclusively (i.e., no other TD can access the assigned device MMIO space), TD uses the TDX module API to accept 
the MMIO pages exclusively assigned to it in order to ensure no other TD can generate trusted MMIO accesses 15 
(with TDX KeyID) to TD assigned MMIO space. 
- A root complex generates TLPs with T bit set only if the MMIO access was translated through a TD Secure-EPT 
i.e., the access was made with a TDX KeyID. Untrusted software (e.g., Legacy VM, VMM, SMM, BIOS, etc.) cannot 
generate MMIO accesses with a TDX KeyID. For such MMIO accesses, made with shared KeyID, the root complex 
will clear the T bit in the IDE TLP. A device interface who follows TDISP must reject any IDE TLP with T bit set to 20 
0 as unsupported TLPs if they access a TD assigned interface register.  
- Device interface assigned to a TD is locked and bound to an IDE stream. Such device interfaces only accept IDE 
TLPs with T bit set to 1 and received on the stream to which they are bound. All other TLPs are rejected as 
unsupported TLPs. This binding of stream ID and locking of the interface to a TD is done using the TEE Device 
Interface Security Protocol messages (see: [PCI-SIG,TDISP) specification). Unauthorized devices cannot generate 25 
TLPs to access the registers of the TD assigned interface, as these unauthorized devices do not have the IDE 
encryption keys. 
 
Figure 3.4: Malicious Interference attack 30 
 Address remapping attack 
VMM may attempt to cross connect MMIO ranges of two different devices when mapping them into the secure-EPT. A 
variant of the attack involves mapping the MMIO GPA range to DRAM, other device interface MMIO pages or switching 
the order of pages of a contiguous MMIO HPA range.  
For example, as illustrated in the figure below, a malicious host VMM can map GPA3 to point PA4 belongs to another 35 
device or switch the mapping of GPA1 and GPA2 to PA2 and PA1 respectively. 
The remap attacks are addressed by TDX Connect as follows: 
- MCEHCK and TDX module lock and verify BIOS configuration MMIO allocated to of external PCIe devices is 
consistent and deterministic on the entire platform. 
- TDX module maintains MMIO page assignment to TDI tracker.  TDX module host VMM API for MMIO mapping 40 
enforces that MMIO pages can only be mapped as private once and to a TD which is the current owner of the 
TDI.  
March 2023  Page 27 of 40 - As part as TDISP life cycle, the TD receives the device interface configuration report. This report contains the 
private MMIO ranges and offsets (order) in which they must be mapped into the private GPA space of the TD.  
- TDX module exposes API for TD guest to accept MMIO ranges device interface configuration report. The TDX 
module accept API verifies the MMIO pages are mapped as expected by converting the HPA offset to a specific 
HPA and checking it matches the VMM mapping. 5 
 
Figure 3.5: Address remap attack 
 Overlap Attacks 
VMM tries to assign a MMIO range to two devices to exploit any priority decode bugs. The address decoders in the root 
complex could be misconfigured by the BIOS to set up multiple root ports to decode a given MMIO range. The VMM may 10 
set up the decoders in the switches downstream of the root complex to cause such overlaps. The overlap attack is 
addressed as follows: 
- MCHECK and TDX module lock and verify MMIO address decoding between Core, SOC fabric, root complex and 
root ports are consistent and deterministic such that there are no MMIO routing aliases or dropping due to 
overlapped decoding rules to MMCFG, DRAM or other ranges. 15 
- TEE-IO devices must ensure that their BARs do not overlap and treat any BAR re-programming as error when 
their TDI or IDE streams are in locked state (for details see [PCI-SIG, TDISP and IDE]). 
- Intel TDX Connect architecture does not include switches in the trust boundary and setup selective IDE streams 
that are pass through for the switches. This avoids having to trust any configurations in the switches as mis-
programming including creating such overlaps that lead to redirection of encrypted and integrity protected 20 
traffic and thus avoid compromising the confidentiality of the data. Note that denial of service is not a security 
objective. 
- Another flavor of this attack involves reducing MMIO decoding windows to silently drop some of the trusted 
transactions. This attack is addressed by the TDX module locking the root complex and root port MMIO routing 
configuration ranges ensuring selective IDE streams and MMIO pages can only be programmed whiting these 25 
ranges. 
 
Figure 3.6: Overlap Attack 
 
 Redirection Attack 30 
 VMM configures switches to redirect or drop MMIO accesses. The redirection attack is addressed as follows: 
programming including creating such overlaps that lead to redirection of encrypted and integrity protected 
traffic and thus avoids compromising the confidentiality of the data. Note that denial of service is not a security 35 
- A specific way such redirections can be done is by the VMM tampering with the selective IDE stream address 
and ID association registers selective IDE stream. This attack is addressed by the host side IDE access controls 
mechanisms preventing ensuring only the TDX module is able to program the IDE stream registers. 
Intel® TDX Connect Architecture  354629 001-US

March 2023  Page 28 of 40  
Figure 3.7: Redirection Attacks. 
 
 Man-in-the-middle (MITM) 
Attacker, eavesdrop, modifies, replays or injects MMIO request or completion. The MITM attack is addressed as follows: 5 
that are pass through for the switches. This avoids having to trust any configurations in the switches or security 
mechanism around observation interfaces (e.g., debug ports) in the switches. The PCIe transactions between 
the SOC RC and the TEE-IO device are protected by the selective IDE stream encryption which guarantees 
confidentiality, integrity, and replay protection. 10 
 
Figure 3.8: Man-In-The-Middle Attack. 
 
 Malicious device interface programming 
This attack vector involves the VMM pre-configuring a device interface assigned to a TD in a malicious manner. Not 15 
allowing the TD an opportunity to inspect the device interface register configuration before the device interface is made 
operational and allowed to access TD private memories, is problematic. Malicious device interface programming attacks 
are addressed as follows: 
- TDISP management protocol enforces that a TDI starts out in a non-operational form where it does not accept 
any MMIO accesses or generates DMA. The TD owner of the device interfaces is the only entity capable of 20 
generating Secure SPDM message to instruct the device to move into TDISP RUN state. TDX module exposes an 
API to get the TDISP message payloads and measurements required to establish trust and verify the device 
configuration (i.e., DEVICE_INTERFACE_REPORT) thus, the TD can first attest and verify the device configuration 
and only then, initiate a TDISP request to move the device into an operational (TDISP RUN) state. 
 Un-Authorized TD Access 25 
Attacker VMM maps MMIO pages to an aggressor TD. Later, the VMM maps the same MMIO pages to the victim TD 
without first removing the MMIO pages from the aggressor TD or with invalidating the IOTLB. The aggressor TD can use 
the mapped MMIO or the stale IOTLB caches to access to TEE-IO MMIO space currently assigned to the victim TD.  
Unauthorized TD access to device MMIO is addressed as follows: 
- TDX module maintains MMIO assignment and mapping tracking tables in TDX protected memory 30 
- TDX MMIO management APIs ensure MMIO pages are assigned and mapped to a single TD. 
- TDX module exposes API for the TD to “accept” and verify the MMIO ranges are mapped exclusively to its private 
GPA space. TD must accept all the private MMIO pages as they appear in the TDISP report to ensure their 
exclusive assignment and mapping to the TDI and the TD private memory.  
- TDX module does not allow removal of the MMIO mappings while the TDI is assigned to the TD. 35 
- TDX module does not allow assignment of MMIO space to another TDI before all the MMIO pages from the 
previous TDI assignment have been removed and their associated IOTLBs were invalidated. 
March 2023  Page 29 of 40  
Figure 3.9: Un-Authorized TD Access. 
3.3.1. Secure MMIO Management 
To address the trusted MMIO security objectives, TDX module is extended with Secure MMIO management support to 
provide the following security properties: 5 
1. TDI MMIO pages can only be mapped as private to a TD which is the TDI owner 
2. TDI MMIO pages cannot be aliased by more than one GPA address for a TD 
3. TDI MMIO page un-map can only be done after proper TLB invalidation and after the device is in TDISP 
CONFGI_UNLOCKED state 
4. MMIO page cannot be assigned to another TDI and TD unless it was properly and securely removed from 10 
its previous TD 
In addition, the TDX Module must provide the TD with a mechanism to ensure that the MMIO ranges from the TDISP 
report are mapped as private GPA and HPA in the TD Secure-EPT. 
The CPU core is extended to carry a T bit set to 1 when a TD access to MMIO is made using a private GPA and HPA with 
the private TD KeyID. This T bit is carried to the RP and the IDE engine in order to differentiate between trusted and  non-15 
trusted MMIO accesses. For private MMIO access with T bit set, the RP IDE engine ensures the request or completion 
falls into IDE selective stream which is in secure state and leaves the SOC only as encrypted IDE TLP with T bot set in the 
IDE prefix.   
At a high level, the following access control mechanism and rules are designed to enforce trusted MMIO access from TD 
to TDI private MMIO: 20 
1. Before accepting a TDI and requesting its transition into TDISP RUN state, the TD must use TDX module APIs to 
ensure the TDI MMIO ranges are correctly mapped in the TD Secure-EPT by the VMM 
2. TD access to private (GPA) MMIO page is translated to HPA with the TD private KeyID 
3. The SOC routing fabric converts private KeyID as T bit = 1 to the RP 
4. When T  bit is set, the RP IDE engine identifies the transaction as trusted ensuring the TLP is selected by an IDE 25 
selective stream which is in a secure state. The IDE sets the T bit in the TLP IDE prefix 
5. TEE-IO device and TDI must ensure access TEE-MMIO space is only possible when TDI is in TDISP RUN state, 
only using the default IDE stream and with IDE prefix T bit set. 
March 2023  Page 30 of 40  
Figure 3.10:  Secure MMIO access control 
3.3.2. Trusted DMA Security Objectives 
Intel TDX Connect enforces Secure DMA access controls to ensure a TDI may only access TD private memory after: 
1. The TD has accepted the device into its TCB 5 
2. The TDI is in TDISP CONFIG_LOCKED or RUN state (TDI is responsible not to access or accept TD memory accesses 
when it’s not in TDISP RUN state) 
3. The TD has verified the TDI report and explicitly accepted the TDI MMIO pages and trusted DMA mappings 
between the TDI (RID + default PASID) and the TD private memory. 
4. The view of memory as seen by a TD guest must match the view of memory as seen by a device interface 10 
programmed by the TD guests.  
5. The DMA translation tables used for performing the GPA/GPA to PA translations must have integrity such that 
they cannot be tampered with by untrusted software.  
Unlike CPU-originated load/store where the CPU has at one instance of time a single TD that is executing, device- 
originated load/store can occur at any time, even when its TD is not executing. The right translation tables used to 15 
perform the translation are thus obtained from identities carried in the TLPs generated by the device interface itself. 
Intel TDX Connect architecture enabling of trusted DMA access to TD private memory must cope with the following 
problems: 
 ID spoofing 
Attacks using malicious devices spoof RID and/or PASID to reach TD private memory. The RID in the TLP is used to 20 
determine the context table entry and the PASID is used to determine the corresponding PASID table entry. These 
ID spoofing attacks are addressed as follows: 
- Intel TDX Connect architecture restricts TD private memory accesses only to IDE TLPs with T bit set to 1 and 
when the stream-id in the IDE TLP prefix is that of a selective IDE stream. Any TLP which is not an IDE TLP or that 
which does not have the T bit set or where the stream on which it is received is not a selective IDE stream does 25 
not get the access rights to TD private memory.  
- When an IDE TLP prefix is received by the SOC root port, the stream-id in the prefix is used to decrypt and 
authenticate the TLP. Once the TLP has been authenticated, if the T bit is set in the IDE TLP prefix but the stream 
ID on which it was received is not a selective IDE stream then TLP is rejected as an unsupported TLP. If the stream Physical DeviceSecure EPT Secure EPTTD1 TD2 VM
SOC Routing Fabric
PCIe Root PortPrivate
KeyIDPrivate
KeyIDShared
KeyID
T =1 T =1 T = 0
IDE TLP
T=1IDE TLP
T=1IDE TLP
T=0
TDI1TDI2Private
KeyIDEPTPrivate
GPAPrivate
GPAIntel® TDX Connect Architecture  354629 001-US  
March 2023  Page 31 of 40 ID is that of a selective IDE stream but source RID of the TLP does not match that stream RID association register, 
then the TLP is rejected as an unsupported TLP. This ensures that only devices with which a selective IDE stream 
has been established can generate TLP with T bit set to 1 and such devices cannot spoof a RID which is not in the 
RID association register used to setup that stream. 
 5 
Figure 3.11:  ID Spoofing Attack 
 
 Remap attack 
This attack involves remapping GPA to PA or create different mappings seen by the TD compared to mapping seen from 
a device interface assigned to the TD. Remap attacks are addressed as follows: 10 
- TDX-module enforces that the EPT used by the CPU for translating GPA is also linked to the PASID table entries 
for the TD assigned device interfaces.  
- TDX-module enforces that any GPA to PA translation changes is accompanied by a CPU TLB, IOMMU TLB, and

 5 
 
- TDX-module enforces that any GPA to PA translation changes is accompanied by a CPU TLB, IOMMU TLB, and 
device TLB invalidates to address such remap attacks from being caused by a stale translation in any of these 
TLBs. 15 
- TDX-module enforces that the translation caches and TLBs in the IOMMU are tagged with a unique per TD 
domain-ID and that the TD assigned domain-ID cannot be assigned to translation tables setup for untrusted 
legacy VMs or other untrusted software. 
- TDX-module enforces invalidations of CPU, IOMMU, and device TLBs and translation caches before a TD assigned 
domain-ID can be reclaimed and used for other TDs. 20 
 
Figure 3.12:  Remap Attack 
 
 Man-In-The-Middle (MITM) 
Eavesdropping, replaying, tampering with device-2-memory transactions. The MITM attack is addressed as follows: 25 
that are a pass through for the switches. This avoids having to trust any configurations in the switches or security 
mechanism around observation interfaces (e.g., debug ports) in the switches. The IDE TLPs are confidentiality, 
integrity, and replay protected end-to-end between the SOC root port and the Intel TDX Connect capable device. 
The IDE extensions implement a mechanism to detect violation of PCIe producer-consumer ordering rules.  30 
 
March 2023  Page 32 of 40 Figure 3.13:  Man-In-The-Middle Attack 
 
 Confused deputy access attacks 
A trusted device shared by two TDs and one TD instructs the device to access memory mapped to the other TD. The 5 
confused deputy attack is addressed as follows: 
- The security model assumes that a device trusted by two TDs is in the trust boundary of both TDs and the TDs 
rely on the device to not use the incorrect Source ID when generating DMA transactions. 
- TDX-module ensures that each device identified by RID (BDF) is exclusively assigned to a single TD and can be 
mapped in the trusted DMA table scalable-mode context entry and into a single VMM assigned PASID table entry 10 
only to the TD owner of the assigned device.  
- TDX-module implements device assignment to ensure all DMA mappings of a TDI (identified by BDF from 
Function ID) are removed and the required IOTLB invalidations have been correctly done by the VMM before a 
TDI can be reclaimed from a TD and reassigned. 
 15 
Figure 3.14:  Confused Deputy Attack 
 
3.3.3. Trusted DMA Translation 
To meet the trusted DMA access control security objectives, trusted IOMMU hardware extensions provide the following 
capabilities: 20 
1. Trusted DMA translation root table – a second root table address register that is restricted to SEAM SAI. The TDX 
module programs this root table address register with the root of the TDX module managed DMA translation tables 
for TD assigned devices. This allows the TDX module to enforce integrity on DMA translations for TD assigned devices. 
 
2. Trusted invalidation queue – a second invalidation queue address register along with a second head and tail register 25 
that are restricted to SEAM SAI. The TDX-module programs this invalidation queue address register with the address 
of a TDX module managed invalidation queue. This allows the TDX module to manage the IOMMU and device TLB 
invalidations in a trusted manner. 
 
3. IOTLB, PASID cache, and context entry cache are tagged to identify if they were cached from the trusted DMA 30 
translation tables programmed by the TDX-module. 
 
4. Enforcing domain ID partitioning where-in the highest half of the domain-IDs are restricted to be used only in the 
trusted DMA translation tables when TDX mode is enabled. First and second level paging structure cache entries 
created from trusted DMA translation tables are thus differentiated from first and second level paging structure 35 
cache entries from the VMM managed untrusted DMA translation tables. 
March 2023  Page 33 of 40  
 
Figure 3.15:  Trusted DMA and Secure-EPT  
The TDX module manages the DMA trusted page tables separately, while the VMM manages the shared (legacy) DMA 5 
page tables. The trusted and shared page tables are isolated from each other with separate root table address registers. 
The First-stage tables must be in TDX private memory, whereas the second-stage tables (EPT) may either be in TD private 
memory or TD shared memory. Secure EPT are managed by the TDX-module in TD private memory, whereas shared EPT 
is managed by the VMM in TD shared memory. Secure EPT are accessed with a private GPA, whereas shared EPT are 
accessed with a Shared GPA. 10 
For nested translation, the FS table entries must store Private GPAs, and GPA translation must be assigned to SS table 
entries in Secure EPT. 
 
Figure 3-16: IOMMU Trusted DMA Translations 
At a high level, the following access control mechanism and rules are designed to enforce trusted DMA access from TDI 15 
to its owner TD private memory: 
1. TDX module exposes new APIs for trusted DMA management 
2. TD must accept the device into its TCB and accept DMA mapping to its Secure-EPT CoreDRAM
Secure Extended
(Shared EPT)
Physical 
Address + 
PrivateHKIDTLP.T == 1?Device
(TEE-IO)TDI0
Root
ComplexTD0
Core (PMH)GPA.SHARED?N YMMIO or Memory Access
Physical 
Address + 
Shared HKIDDMA (IDE TLP with T bit = 1)
PCIeRP + IDE
Trusted DMA
Remapping Tables
(Trusted DMAR )IOMMUIDE.T == 1?N YGPA, RID, PASID, T bit = 1
SLPTRpoints to 
TD0Secure EPT(Shared) DMA
(DMAR)
Private context or memory. Managed by the TDX module APIs
Shared context or memory. Managed by the VMMRID + PASID walkMK-TME
EngineDevice Mem
Is MMIO?Y NMMIO (IDE TLP with T bit = 1)
SOCIs TDX = 1
March 2023  Page 34 of 40 3. TEE-IO enforces TDI DMA access only allowed in RUN state using the default selective IDE stream with T bit = 1 
4. Host RP IDE engine decrypts and authenticates the TLP passing T bit to IOMMU 
5. The T bit is set in the request, the IOMMU use trusted DMA translation walking the DMA tables managed by the 
TDX module 
6. SOC routing logic carries the T bit using it to ensure that access to memory with TD private KeyID is only allowed 5 
when T bit is set 
 
Figure 3.17:  Trusted DMA access control 
 
Note, the following capabilities are not supported by the current Intel TDX Connect specification and hardware and may 10 
be supported in future Intel TDX Connect extensions: 
1. Address Translation Caching (ATC) – No support for Device-TLBs and caching of translations into device TLBs. 
2. Nested Translation: Trusted DMA access may only use second level translation pointers. Nested translation (first 
and second level) may be supported as part of future Intel TDX Connect extensions. 
3. Shared Virtual Memory (SVM) – No support for trusted page request queue. 15 
  Physical DeviceTD1
IOMMU (Trusted DMA TD.SEPT)
PCIe Root PortT = 1
T =1
TDI1IDE
T=1
Untrusted
DeviceIDE 
AuthenticationSOC Routing Logic (TD private KeyID access check)
TDI2IDE
T=1T =1 T = 0Legacy DMA rootMemory Controller MKTEM Engine (Private TD KeyID)
T = 0Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 35 of 40 3.4. TDX Module Extensions for TDX Connect and TEE-IO Support  
The TDX module extensions for TDX Connect and TEE-IO support fall into three main categories: 
1. Discovery and enabling of TDX Connect on TDX host platform 
2. TEE-IO device management of SPDM session and IDE setup and teardown 
3. TEE-IO Device Interface (TDI) life cycle management of TDI to TD direct assignment and removal 5 
This document provides high-level overview of the following TDX component extensions required to support TDX  
Connect and TEE-IO: 
- BIOS and MCHECK extensions for TDX Connect platform configuration 
- TDX module architecture and ABI extensions (for details refer to [TDX Module TDX Connect Spec]) 
- TDX Connect TEE-IO Provisioning Agent (for details refer to [TPA Spec]) 10 
3.4.1. Discovery and Enabling of TDX Connect on TDX host platform 
The following diagram and sequence describe how TDX Connect is discovered and enabled by the platform BIOS and by 
the host VMM using TDX Module (and MCHECK) extensions:  
1. BIOS uses Intel root complex and IDE enumeration to discover TDX connect as defined by the [Intel RC-IDE 
Guide]. Using the BIOS-MCHECK interface, the BIOS can decide (per IO Hub) which Root Ports shall be enabled 15 
with TDX Connect 
2. MCHECK will checks the platform configuration is supported and can be secured with TDX Connect enabled and 
deliver information about TDX Connect enabling to the TDX module in the SEAM range protected memory 
3. VMM uses intel root complex and IDE enumeration to discover TDX connect as defined by the [Intel RC-IDE 
Guide]. The VMM installs the TDX Module and uses TDX module extended feature enumeration to discover TDX 20 
module support for TDX Connect as defined by [TDX Module ABI Spec]

module support for TDX Connect as defined by [TDX Module ABI Spec] 
4. VMM enables TDX Connect per IO Hub (IOMMU and Root Ports) using TDX module IOMMU configuration API as 
defined in the [TDX Module TDX Connect Spec] and the [TDX Module ABI Spec]. This operation moves VTd, IDE 
and RP Type 1 registers under TDX control and management and enables TDX mode in the IO Hub.  
 25 
Figure 3.18:  Discovery and enabling of TDX Connect 
  VMM
NP/P-SEAM 
loaderInstall
TDX 
ModuleBIOS
MCHECKVerify 
Platform
ConfigurationPlatform and IO 
Enumeration and 
TDX Connect 
Enabled IO-Hubs
InformationTDX module1 2 3 4Call TDX host API to enable 
TDX Connect per IO Hub 
(IOMMU and RPs)Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 36 of 40 3.4.2. SPDM Management and the Intel TDX Connect TEE-IO provisioning agent (TPA) TD 
Intel TDX Connect architecture requires to setup an SPDM session with the TEE-IO device and SPDM secure messages (as 
secure transport) for protecting the IDE_KM messages (see [PCI-SIG, IDE]) and the TDISP messages (see [PCI-SIG, TDISP]) 
used manage the device interface. The TDISP is protected by the Secure Protocol and Data Model (SPDM) secure session. 
SPDM 1.2 key exchange is a computationally intensive function and uses RSA or ECDSA based SIGMA protocol to negotiate 5 
the management session key. The TDX-module by design is not re-entrant and not interruptive. Performing such long 
latency operations in the TDX-module is thus not desirable.  
To avoid performing these long latency operations, the TDX-module delegates this function to a purpose-built TD called 
the Intel TDX Connect TEE-IO provisioning agent (TPA). The TPA TD is differentiated from other TDs by a TPA attribute bit 
set when such TDs are created and by its build time measurement. The TPA TD is launched by the VMM like other TDs 10 
and there is no difference in that process. 
The TDX-module carries the SHA-384 hash of the TDINFO structure of the TPA TD and verifies that the TDINFO of the TPA 
TD matches the expected TDINFO as part of allowing the TPA TD to configure SPDM session keys. Thus, the TPA TD is in 
TCB of all TDs using Intel TDX Connect but is not explicitly reported in their TCB. It is implicitly in the TCB by virtue of the 
TPA TD measurements being authenticated by the TDX-module. 15 
TPA TD uses the SPDM 1.2 protocol for key exchange with the device to negotiate a SPDM 1.2 session key with the device. 
On completion of the SPDM session setup, the TPA TD hands the SPDM session keys and context in addition to TDISP 
version and capabilities of the device to the TDX-module.  
The TPA TD also records the SHA384 hash of a device TEE info structure of the device with which it did the key exchange. 
The TEE info structure is passed by the TPA to the VMM which then passes it to the TD for the attestation of the TEE-IO 20 
device. Since the VMM is not in the TCB, the TDs needs to verify the device TEE info by calculating its hash and then calling 
a TDX-module API function to verify the hash matches the associated device interface context structure. 
The following diagram and sequence describe how SPDM session is established with the TEE-IO device by the VMM using 
the TPA TD: 
1. VMM calls TDX module API to create the SPDM session context structure 25 
2. VMM calls the TPA TD to requesting it to start the SPDM and TDISP negotiation process 
3. The TPA TD negotiation steps include: 
- SPDM negotiation 
- SPDM identification 
- Secure SPDM Session establishment and key exchange 30 
- TDISP negotiation 
On each step SPDM or TDISP protocol message are generated and delivered as follows: 
- TPA TD generates protocol request and uses TD-VMCALL exit to deliver it to the VMM 
- VMM delivers the message to the DSM using DOE mailbox 
- DSM response is picked up by the VMM and delivered back to the TPA TD 35 
March 2023  Page 37 of 40 4. The TPA record the SPDM session context, info hash and the TDISP negotiation version and capabilities in the 
TDX module SPDM context structure 
 
Figure 3.19:  SPDM setup and TDISP negotiation sequence 
For more details refer to the [TDX Module TDX Connect Spec] and the [TPA Spec]. 5 
 
  Store SPDM and TDISP infoDevice 
(DSM)
Allocate TDX module SPDM context structrueTPA TD
(TSM)VMMTDX 
Module
(TSM)
Start SPDM Session 2
SPDM Request (TD-VMCALL)
SPDM ResponseSPDM Request
SPDM Response
4
Return device info1
Save SPDM session, TDISP 
info and device info hash in 
the SPDM context structureDevice Info =
- SPDM_POLICY
- TDISP version and caps
- SPDM_INFORMATION
- SPDM_CERTIFICATE
- SPDM_MEASUREMENGET_VERSION
GET_CAPABILITIES
NEGOTIATE_ALGO
(Negotiation Done)
GET_CERTIFICATES
(Identification Done)
KEY_EXCHANGE
FINISH 
(Session Created)
TDISP.DET_VERSION
TDISP.GET_CAPABILITIES
(TDISP Negotiated)3Intel® TDX Connect Architecture  354629 001-US  
March 2023  Page 38 of 40  
3.4.3. IDE Setup 
The following diagram and sequence describe the initial IDE streams setup done by the VMM using TDX module extension 
which follows the IDE_KM protocol for enabling and setting up the TEE-IO device EP IDE stream: 
1. VMM calls TDX module API to configure the host RP IDE stream control registers (without enable the IDE yet) 5 
2. Per IDE stream Tx/Rx directions sub-streams (PR, NPR, CPL), the VMM calls TDX module IDE_KM request API to 
generate and program the host RP IDE keys returning the corresponding IDE_KM KEY_PROG message. The VMM 
delivers the KEY_PROG message to the device using the DOE mailbox and then, the KP_ACK message from the 
device back to the TDX module using the IDE_KM response API 
3. Per IDE stream Tx/Rx directions sub-streams (PR, NPR, CPL), the VMM calls TDX module IDE_KM request API to 10 
activate the host RP IDE keys returning the corresponding IDE_KM KEY_SET_GO message. The VMM delivers the 
KEY_SET_GO message to the device using the DOE mailbox and then, the K_GOSTOP_ACK message from the 
4. When the VMM receives the last K_GOSTOP_ACK message from the device, it needs to setup the IDE-ECAP 
controls on the device, set the IDE stream Enable bit and check the status bit 15 
5. When VMM feeds the last K_GOSTOP_ACK from the device as described in step 3., the TDX module will implicitly 
set the RP IDE stream Enable bit 
 
Figure 3.20:  IDE setup sequence 
  20 
March 2023  Page 39 of 40 3.4.4. TDI Assignment to TD 
The following diagram and sequence describe the sequence of TDI assignment to a TD done by the VMM using and 
accepted by the TD using TDX module extension: 
1. VMM configures the TDI on the TEE-IO device 
2. VMM calls a TDX module API to assign the TDI FUNCTION_ID to a TD allocating memory for the TDI context 5 
structure 
3. VMM calls the TDX module APIs for building and mapping the trusted DMA page tables into the TD Secure-EPT 
4. VMM calls TDX module APIs for mapping the TDI MMIO ranges into the TD Secure-EPT as PENDING using Private 
GPA space and private HPA (TD Private KeyID) 
5. VMM calls TDX module API for generating TDISP LOCK_INTERFACE_REQUEST. The VMM delivers the request to 10 
the device using the DOE mailbox and feeds back the device LOCK_INTERFACE_REQUEST using TDX API for 
processing and authenticating TDISP responses. 
6. VMM delivers the TPA device info to the TD 
7. TD checks the device information to decide if the device is trust-worthy or not. Then if it chooses to trust the 
device, the TD calculates the hash of the (VMM delivered) device information. The TD then invokes a TDX module 15 
API to verify the hash calculated over the device information matches the one recoded by the TPA TD during the 
SPDM session establishment with the TEE-IO device. 
8. TD initiates a TDISP request for DEVICE_INTERFACE_REPORT, the request is fulfilled by the VMM call to TDX 
Module API to generate TD initiated TDISP request. The VMM delivers the request to the device using the DOE 
mailbox and feeds back the device LOCK_INTERFACE_REPORT message using the TDX module API for processing 20 
and authenticating TDISP responses. Finally, the TD reads the report using TDX module TDISP response API and 
verifies the device report matches the expected configuration. 
9. The TD reads the MMIO ranges from the report and call TDX module API to verify and accept private MMIO 
mappings created by the VMM in step 4. 
10. The TD accepts the PENDING trusted DMA mapping created by the VMM in step 3. 25 
11. The TD initiates a TDISP START_INTERFACE_REQUEST (using same APIs and sequence described in step 8.)  
March 2023  Page 40 of 40  
Figure 3.21:  TDI assignment to TD sequence 
 TD 
(TVM)VMM
Assign FUNCTION_ID and create a TDI context TDX 
(TSM)Device 
(DSM)
Check device info data to 
determine if can be trustedDeliver TPA generated
device info data
Check device
 info data integrity
GET_DEVICE_INTERFACE_REPORT
DEVICE_INTERFACE_REPORT
Accept TDI MMIO

 TD 
(TVM)VMM
(DSM)
Accept TDI MMIO 
pages (from TDI report)9
Accept TDI trusted 
DMA mapping
START_INTERFACE_REQUEST
START_INTERFACE_RESPONSELOCK_INTERFACE_REQUEST
LOCK_INTERFACE_RESPONSECheck FUNCTION_ID is 
not already assignedConfigure TDI 1
2
Map TDI private MMIO (as PENDING) 4Build and map TDI Trusted DMA tables(as PENDING) 3 DMA table entry mapped as 
PENDING with SLPTR aliasing 
the TDI TD owner Secure-EPT 
Check MMIO page is in TDI 
Selective IDE Address Range 
VMM Initiated TDISP
Message
TD Initiated TDISP
Message
Message Sequence5
6
87
Check MMIO mapping 
matches TD expectation 
(per the TDI report) and 
change MMIO mapping 
state to PRESENT
Change trusted DMA 
mapping state to PRESENT10
11 
 
Extensions (Intel® TDX)  1.0 
344426 -006US  
March  202 3 
 
Ref. # 344426 -006US  i Disclaimers  
others.  
  Guest -Hypervisor  Communication Interface (GHCI) Specification for Intel® TDX  1.0 
Ref. # 344426 -006US  ii Table of Contents  
3 TDG.VP.VMCALL Interface  ................................ ................................ ................................ ................................ ... 14 
3.1 TDG.VP.VMCALL<G ETTDVMCALLINFO> ................................ ................................ ................................ .....................  14 
3.2 TDG.VP.VMCALL<M APGPA>  ................................ ................................ ................................ ................................ ..........  15 
3.3 TDG.VP.VMCALL<G ETQUOTE > ................................ ................................ ................................ ................................ ....... 17 
3.4 TDG.VP.VMCALL<R EPORT FATAL ERROR > ................................ ................................ ................................ ....................  20 
3.5 TDG.VP.VMCALL<S ETUP EVENT NOTIFY INTERRUPT > ................................ ................................ ................................  22 
3.6 TDG.VP.VMCALL<I NSTRUCTION .CPUID>  ................................ ................................ ................................ ....................  22 
3.7 TDG.VP.VMCALL<#VE.R EQUEST MMIO>  ................................ ................................ ................................ ....................  23 
3.8 TDG.VP.VMCALL<I NSTRUCTION .HLT>  ................................ ................................ ................................ .........................  25 
3.9 TDG.VP.VMCALL<I NSTRUCTION .IO>  ................................ ................................ ................................ .............................  26 
3.10  TDG.VP.VMCALL<I NSTRUCTION .RDMSR>  ................................ ................................ ................................ ...............  26 
3.11  TDG.VP.VMCALL<I NSTRUCTION .WRMSR>  ................................ ................................ ................................ ..............  27 
3.12  TDG.VP.VMCALL<I NSTRUCTION .WBINVD>  ................................ ................................ ................................ ............  28 
3.13  TDG.VP.VMCALL<I NSTRUCTION .PCONFIG>  ................................ ................................ ................................ ............  28 
4 TD -Guest -Firmware Interfaces  ................................ ................................ ................................ ................................ . 30 
4.1 ACPI  MADT  MULTIPROCESSOR WAKEUP TABLE  ................................ ................................ ................................ ...........  30 
4.2 MEMORY MAP ................................ ................................ ................................ ................................ ................................ ...........  30 
4.3 TD MEASUREMENT  ................................ ................................ ................................ ................................ ................................ .. 33 
4.3.1 TCG -Platform -Event Log  ................................ ................................ ................................ ................................ ..............  33 
4.3.2 EFI_CC_MEASUREMENT_PROTOCOL  ................................ ................................ ................................ ................  33 Guest -Hypervisor  Communication Interface (GHCI) Specification for Intel® TDX  1.0 
Ref. # 344426 -006US  iii 4.3.3 CC -Event Log  ................................ ................................ ................................ ................................ ................................ ... 33 
4.4 STORAGE -VOLUME -KEY DATA ................................ ................................ ................................ ................................ .............  33

4.4 STORAGE -VOLUME -KEY DATA ................................ ................................ ................................ ................................ .............  33 
5 TD -VMM -Communication Scenarios  ................................ ................................ ................................ ......................  35 
5.1 REQUESTING IPIS ................................ ................................ ................................ ................................ ................................ ...... 35 
5.2 TD-MEMORY CONVERSION AND MEMORY BALLOONING  ................................ ................................ ................................ . 35 
5.3 PARAVIRTUALIZED IO ................................ ................................ ................................ ................................ .............................  36 
5.4 TD ATTESTATION  ................................ ................................ ................................ ................................ ................................ ...... 36 
 
 Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
About this Doc ument  
Ref. # 344426 -006US  2 1 About this Document  
utilized for the paravirtualization interface between the TD and the VMM.  This approach helps  
must therefore volunteer information to access IO services, enumerate model -specific CPU 
VMM (informative).  The TD and the VMM are designed to use the subfunctions, which are 
normative and  described in this document.  
TDG.VP.VMCALL leaf used for passing information to the VMM and receiving information from 
the VMM.   
Binary Interface (ABI) between the TD and the VMM for specific operations.  
  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  3 1.3 Glossary  
Table 1-1:  Intel TDX  Glossary  
software.  
Intel TDX 
VMs).  
TDX . 
 
1 In this document, the term “MKTME” means both the feature and the encryption engine itself.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  4 Acronym  Full Name  Description  
3 Intel® Trust Domain Extensions module  1.0 specification  February 2023  
 
Should Not  “Should Not” or the phrase “Not Recommended”  means that there may exist valid 
weighed before  implementing any b ehavior described with this label.  
various  reasons.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  5  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  6 2 TD -VMM Communication  
TD itself.  
As shown in the diagram below, a n Intel TDX -aware  host VMM  can launch and manage both

TD itself.  
TDs it manages . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  7 
Intel TDX
Drivers
Intel
TDX Module
Host-Side
Intel TDX
Drivers
Intel TDX
Drivers
scenarios.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  8 
(due to 
handler
 
Section 3 of this document describes the reference/informative  TDCALL[ TDG.VP. VMCALL ] 
instruction execution, such as IO accesses.  
handling for nested #VE, as descri bed in Intel -SDM Chapter 25.5.6.3 (Delivery of Virtualization 
Exceptions ). The TD OS should avoid instructions that may cause #VE in the #VE handler.  
module  Architecture specification.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  9 2.4 TDCALL  and SEAMCALL  instruction  
TDCALL is the instruction used by the guest TD software (in TDX non -root mode) to invoke 
to the Intel TDX  module  Architecture specification.  
SEAMCALL is the instruction used by the host VMM to invoke host -side TDX functions. For 
Ref. # 344426 -006US  10 Table 2-1: TDG.VP.VMCALL -Input Operands  
module Specification TDG.VP.VMCALL.  
above) . 
Note:  Please be aware that RBP is usually used as a frame pointer 
according to the C language c alling convention. The software 
document shall not use RBP.  
 
Ref. # 344426 -006US  11 Table 2-2: TDG.VP.VMCALL -Output Operands  
software should not use RBP as an input/output parameter and 
should clear BIT5 (RBP) in th e GPR mask in RCX. The API 
 
Ref. # 344426 -006US  12 Table 2-4: TDG.VP.VMCALL -Instruction -execution sub -functions  
 
Ref. # 344426 -006US  13 Table 2-6: TDCALL[TDG.VP.VMCALL] - Sub-function Completion -Status Codes  
TDG.VP.VMCALL_SUCCESS  0x0 TDCALL[TDG.VP.VMCALL] sub-
retried  
TDG.VP.VMCALL _GPA_INUSE  0x80000000 00000001  GPA already mapped  
error  
TDG.VP.VMCALL Interface

retried  
error  
Ref. # 344426 -006US  14 3 TDG.VP.VMCALL  Interface  
Refer to  the Intel TDX  CPU Architecture specification [2] for details of the SEAMCALL and 
[TDG.VP.VMCALL ] interfa ce between the TD and the VMM.  
this specification.  VMMs may provide alternate enumeration schemes using vendor -specific  
supported  by the host VMM .  This register is reserved to extend 
TDG.VP.VMCALL  enumeration in future versions . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  15 Table 3-2: TDG.VP.VMCALL < GetTdVmCallInfo >-Output Operands  
may remove the private page from  the TD by following the “Removing TD Private Pages” 
sequence  in the  Intel TDX -module  specification [3 ] to safely block the mapping (s), flush the 
in the shared -EPT structure and allow the TD to access the page (s) as a shared GPA  (range) . 
Similarly, if the shared page was assigned to any device for use with IO, then the VMM should 
flushed.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  16 The aim is for the  VMM to then follow the sequence specified in “Dynamically Adding TD 
TDH.MEM.PAGE. AUG to add the GP A(s) to the TD as pending , private mapping (s) in the secure -
usable as a private GPA in side the TD.  
Upon  MapGPA  from shared to private, the VMM needs to check if the page is mapped by the 
pages need to be pinned there.  If the VMM provides  a virtual IOMMU (vIOMMU)  or cooperative 
that case,  MapGPA  can: 1) Check  that page is not pinned by  vIOMMU ; 2) Check that the page is 
TDG.VP.VMCALL  specific status code.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  17 Table 3-6: TDG.VP.VMCALL <MapGPA >-Status Codes  
Table 2 -6 TDG.VP.VMCALL  is successful.  The TD 
TDG.VP.V MCALL_ALIGN_ERROR  Alignment error for size or Start GPA.  
Quoting enclave , and, when completed, return the Quote via the same , shared -memory area .   
the Event -notification vec tor registered via the SetupEventNotifyInterrupt TDG.VP.VMCALL ). Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  18 Table 3-7: TDG.VP.VMCALL < GetQuote  >-Input Operands  
Error Code  Value  Description

returned.  
private page.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  19 Table 3-10: TDG.VP.VMCALL<GetQuote> - format of shared GPA  
Status 
Input 
Output 
shared 
consume.  
reason.  
 
Ref. # 344426 -006US  20 The following is a typical execution flow : 
TDG.VP.VMCALL< GetQuote>. The data field should include TDREPORT_STRUCT.  
4) If the input operands and fields in shared GPA are good, the VMM updates status code 
in shared GPA to GE T_QUOTE_IN_FLIGHT and queues the request. Then, 
Quoting Enclave and receives response message from it. 
TDG.VP.VMCALL< SetupEventNotifyInterrupt>.  
TDG.VP.VMCALL<GetQuote> API  allows one TD to issue  multiple requests. This is  
3.4 TDG.VP.VMCALL <Report Fata lError > 
error state , and let the VMM access debugging information .  The output returned by the 
firmware execution , for example) where some instructions like IN/OUT may be avoided to  
prevent causing  a #VE . It may be also use d by the TD guest post -boot when it detects an error 
the shared m emory 4KB region) . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  21 Table 3-12: TDG.VP.VMCALL < ReportFatalError  >-Input Operands  
reserved . 
(R13) . 
string.  
R14, R15, RBX,  RDI, RSI, 
bitmap.  
code(0x 20-0x7e) is filled.  
Table 3-13: TDG.VP.VMCALL <Report FatalError >-Output Operands  
TDG.VP.VMCALL_SUCCESS  See values in Table 2 -6 TDG.VP.VMCALL is successful . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  22 3.5 TDG.VP.VMCALL <SetupEventNotifyInterrupt>  
The host VMM should use SEAMCALL [TDWRVPS] l eaf to inject an interrupt at the requested -
Table 2 -3. 
TDG.VP.VMCALL _INVALID_OPERAND  Invalid operand . 
emulate  CPUID operation, especially for non -architectural , CPUID  leaves . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  23 Table 3-18: TDG.VP.VMCALL <Instruction.CPUID> -Input Operands  
R12  EAX  
R13  ECX  
 
R12  EAX  
R13  EBX  
R14  ECX  
R15  EDX  
 
in the EPT Entries corresponding to these mappings.

R12  EAX  
R13  ECX  
 
R12  EAX  
R13  EBX  
R14  ECX  
R15  EDX  
 
in the EPT Entries corresponding to these mappings.  
the TD may choose to use this TDG.VP.VMCALL  to request MMIO read/write operations.   Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  24 The VMM may emulate the access based on the inputs provided by the TD .  However, note 
used for untrusted IO with other cryptographic protection for the TD data pr ovided by the TD 
itself.  
 
Ref. # 344426 -006US  25 3.8 TDG.VP.VMCALL <Instruction.HLT>  
set. 
Ref. # 344426 -006US  26 3.9 TDG.VP.VMCALL <Instruction.IO>  
Instruction.RDMSR TDG.VP.VMCALL  is used  to help perform RDMSR operation.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  27 Table 3-30: TDG.VP.VMCALL <Instruction.RDMSR> -Input Operands  
Ref. # 344426 -006US  28 Table 3-35: TDG.VP.VMCALL <Instruction.WRMSR> -Status Codes  
 
Table 3-38: TDG.VP.VMCALL< Instruction.WRMSR> -Status Codes  
Instruction.VMCALL PCONFIG is used to help  perform Instruction -PCONFIG operation.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  29 Table 3-39: TDG.VP.VMCALL <Instruction.PCONFIG> -Input Operands  
3. 
spec.  [4] 
 
requested is invalid . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  30 4 TD -Guest -Firmware Interfaces  
bootstrap processor wake up guest -application processors with a mailbox.  The mailbox is 
guest OS send a message to the m. 
For detailed information about the Multiprocessor Wakeup Table, please refer to ACPI 6.4 
specifi cation . 
TDVF yet.  
If a TD-memory region is unaccepted memory and requires  TDCALL [ TDG.MEM.PAGE. ACCEPT]  in the

TDVF yet.  
If a TD-memory region is unaccepted memory and requires  TDCALL [ TDG.MEM.PAGE. ACCEPT]  in the 
TD guest OS, then the  TD owner shall have the  final UEFI -memory map report this region  with 
TDVMCALL<#VE.RequestMMIO>  and not via direct memory read or write.  Accordi ngly, as 
memory -resource descriptors.  
Ref. # 344426 -006US  31 Table 4-1: TDVF -memory map for OS  
Reserved.  
Reserved.  
table.  
RUNTIME -virtual address 
The f ull MMIO should be 
page.  
TDCALL[ TDG.MEM.PAG
E.ACCEPT]  
Ref. # 344426 -006US  32 For a non-UEFI system, the memory map can be reported via E820 table.  Please  refer to ACPI 
TD guest OS, then the TD Shim shall have the final memory map report this region with 
AddressRangeUnaccep ted. 
designed, there is no need to report this region in the final memory map.  
convert to 
 
Ref. # 344426 -006US  33 4.3 TD Measurement  
designed to  report the event log with the same data structure in TCG -Platform -Firmware -
confidential computing (CC)  measurement registe r. 
0 MRTD  
1 RTMR[0]  
2  RTMR[1]  
3  RTMR[2]  
4 RTMR[3]  
 
attestation to be able to fetch a set of storage -volume key (s) from a remote -key server during Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  34 boot and pass the key to the guest kernel.  Also by design, t he key is stored in the memory, 
Please refer to ACPI 6.5 specification . Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  35 5 TD -VMM -Communication Scenarios  
 
Various TD -VMM -communication scenarios require the TD to request that the host generate 
inject an in terrupt into the guest TD’s RLPs using the posted -interrupt mechanism.  This is an 
TD OS may operate on a fixed , private -GPA s pace configured by the host VMM.  Typically,  the 
OS manages a physical -page -frame database for state of (guest) physical -memory allocations.   
The VMM can then TDH.MEM.RANGE. BLOCK, TD H.MEM .TRACK , and TD H.MEM.SEPT.REMOVE  
completion of the TDG.VP.VMCALL  flow can be used by the TD guest to 
mapping as active.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  36 5.3 Paravirt ualized IO  
The TD guest can use paravirtualized -IO interfaces (for example, using virtio API in KVM) 
managed by the VMM.  For this scenario, Virtualized  IO is typical ly enumerated over emulated 
PCIe (port I/O or MMIO).  The TD drivers can help  ensure that the data passed via memory 
referenced in emulated -MMIO accesses are placed in the TD’s shared -GPA -memory space.

Paravirtualized  drivers could pre -allocate a primary -shared buffer during initialization.   
Shared buffers can be deallocated during driver -stack tear -down.  This scenario is optimal , as 
and TDCALL [TDG.MEM.PAGE. ACCEP T] for mapping back as a private -TD page , as described in 
The enlightened -TD-OS-#VE handler can emulate the access causing the #VE by decoding the 
TDCALL [ TDG.VP.VMCALL  <#VE. Requ estMMIO >].  From that point on, like the paravirtualized 
I/O model, the TD software should ensure that data buffers passed via memory referenced by 
Goals of TD At testation are to enable the TD OS to request a TDREPORT that contains version 
trustworthiness of the TD.  Guest -Host Communication Interface (GHCI) Specification for Intel® TDX 1.0 
Ref. # 344426 -006US  37 
Host VMM
CPU
MAC Key
Quote
(Signed)
Intel TDX
Module
SEAM 
+ TD Info)
TDCS
SEAM 
REPORT
(MACed)
+ TD Info) 
 
~~ End of document ~~         
 
[Public]  
 
Secure VM Service Module for 
SEV-SNP Guests  
Guest Communication Interface  
 
 Publication #  58019  Revision:  1.00     
 Issue Date:  July 2023       
         
 [Public]  
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 [Public]  
Acknowledgements  
AMD would like to acknowledge Jon Lange for his work in creating the  initial draft  of the SVSM 
specification.  Thank you, Jon.  
    
6   
 
[Public]  
Contents  
Specification Agreement  ................................ ................................ ................................ ............  3 
Acknowledgements  ................................ ................................ ................................ ...................  5 
1 Abstract  ................................ ................................ ................................ ..............  9 
2 Scope of Document  ................................ ................................ ...........................  10 
3 Environment  ................................ ................................ ................................ ..... 11 
4 Discovery  ................................ ................................ ................................ ..........  12 
4.1 Boot   ................................ ................................ ................................ ...............................  12 
4.2 Post -Boot  ................................ ................................ ................................ .......................  13 
5 Calling Convention  ................................ ................................ ............................  14 
6 Core Protocol  ................................ ................................ ................................ .... 18 
6.1 SVSM_CORE_REMAP_CA Call  ................................ ................................ ........................  18 
6.2 SVSM_CORE_PVALIDATE Call  ................................ ................................ ........................  19 
6.3 SVSM_CORE_CREATE_VCPU Call  ................................ ................................ ...................  20 
6.4 SVSM_CORE_DELETE_VCPU Ca ll ................................ ................................ ....................  21 
6.5 SVSM_CORE_DEPOSIT_MEM Call  ................................ ................................ ..................  22 
6.6 SVSM_CORE_WITHDRAW_MEM Call  ................................ ................................ ............  23 
6.7 SVSM_CORE_QUERY_PROTOCOL Call  ................................ ................................ ...........  24 
6.8 SVSM_CORE_CONFIGURE_VT OM Call  ................................ ................................ ...........  25 
7 Attestation Protocol  ................................ ................................ ..........................  27 
7.1 SVSM_ATTEST_SERVICES Call  ................................ ................................ ........................  27 
7.2 SVSM_ATTEST_SINGLE_SERVICE Call  ................................ ................................ .............  30 
8 vTPM Protocol  ................................ ................................ ................................ .. 33 
8.1 SVSM_VTPM_QUERY Call  ................................ ................................ ..............................  33 
8.2 SVSM_VTPM_CMD Call  ................................ ................................ ................................ . 34 
8.2.1  TPM_SEND_COMMAND  ................................ ................................ ........................  35 
8.3 Service Attestation Data  ................................ ................................ ................................  35 
8.3.1  Service Attestation GUID  ................................ ................................ .......................  35 
8.3.2  SVSM_ATTEST_SERVICES Manifest Data  ................................ ................................  35 
8.3.3  SVSM_ATTEST_ SINGLE_SERVICE Manifest Data  ................................ ....................  36  
 
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 [Public]  
 
List of Tables   
Table 1: Secrets Page Fields  ................................ ................................ ................................ ..........  12 
Table 2: Calling Area  ................................ ................................ ................................ ......................  14 
Table 3: Protocols  ................................ ................................ ................................ .........................  14 
Table 4: Result Codes  ................................ ................................ ................................ ....................  16 
Table 5: Core Protocol Services  ................................ ................................ ................................ ..... 18 
Table 6: PVALIDATE Operation  ................................ ................................ ................................ ...... 19 
Table 7: Deposit Memory Operation  ................................ ................................ .............................  22 
Table 8: Withdraw Memory Operation  ................................ ................................ .........................  24 
Table 9: vTOM Configuration Operation  ................................ ................................ .......................  25 
Table 10: Attestation Protocol Services  ................................ ................................ ........................  27 
Table 11: Attest Services Operation  ................................ ................................ ..............................  28 
Table 12: Services Manif est ................................ ................................ ................................ ..........  29 
Table 13: Attest Single Service Operation  ................................ ................................ .....................  30

Table 13: Attest Single Service Operation  ................................ ................................ .....................  30 
Table 14: Attestation Protocol Services  ................................ ................................ ........................  33 
Table 15: vTPM Common Request/Response S tructure ................................ ................................  34 
Table 16: TPM_SEND_COMMAND Request Structure  ................................ ................................ .. 35 
Table 17: TPM_SEND_COMMAND Response Structure  ................................ ................................  35 
Table 18: vTPM Service Manifest Data Structure  ................................ ................................ ..........  36 
 
8   
 
[Public]  
May 2023  1.00  • Incorporated feedback from 0.62 review  
o Added requirement to zero memory of pages that are being made 
valid via the PVALIDATE call  
March 2023  0.62  • Incorporated feedback from 0.61 review  
o Clarifications around vCPU create and delete  
o Added check for attestation buffer size  
o Document clarifications  
February 2023  0.61  • Incorporated feedback from 0.60 review  
o Updated vTPM attestation information  
o Added single service attestation call  
o Support for returning attestation certificates  
January 2023  0.60  • Attestation protocol added  
• vTPM protocol added  
• Core protocol updates  
August  2022 0.50 • Initial public draft  
  
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 [Public]  
1 Abstract  
AMD’s Secure Encrypted Virtualization with Secure Nested Paging (SEV -SNP) offers powerful and 
flexible support for isolation of a guest V irtual Machine (VM)  state from an untrusted host 
operating system. The VM Permission Level  (VMPL)  feature permits the inclusion of components 
in the guest that can run with a higher privilege than the guest operating system, offering an 
environment for secure, privileged cod e modules to run without interference from the bulk of 
the guest. Such code modules are not part of the guest operating system and may be designed to 
be modular, offering compatibility with a wide variety of guest configurations. For such a 
modular design to be successful, a standard calling convention must exist to permit the guest 
operating system and secure modules to communicate without interference from the untrusted 
host environment. This document defines the standard by which these modules can exist 
together and communicate within a single SNP guest.    
 
10   
 
[Public]  
2 Scope of Document  
This document defines a Secure VM Service Module (SVSM) as an environment that can host 
privileged modules within the guest, and it also defines mechanisms by which a guest operating 
system can determine the presence of the SVSM, the set of services offered by the SVSM, and 
the mechanism by which the guest can communicate with those services.  
This document does not describe the internals of the SVSM. Multiple SVSM implementations are 
enco uraged; this document defines standards by which an SVSM communicates with a guest 
operating system so that multiple SVSM implementations can be compatible with multiple guest 
operating systems.  
This document does not describe the mechanism by which the V irtual Machine Manager (VMM)  
loads the SVSM. That mechanism is assumed to be specific to the host architecture. The SVSM  
and the firmware are  expected to be loaded and measured as part of the initial guest image so 
that the specific identity of the SVSM  and firmware  associated with a guest can be verified 
through measurement and attestation.  It is expected that  the following items will be measured:  
• Items measured at VMPL0  
o SVSM binary  
o SVSM BSP VM Save Area ( VMSA ) as a VMSA page  
o Firmware BSP VMSA as a Normal page  
o Secrets page  
o CPUID page  
• Items measured at VM PL1+ 
o Firmware binary  
The hypervisor can measure additional pages as needed.  
This document does not describe mechanism s by which the VMM communicates with the SVSM 
nor chooses to invoke the SVSM. Those  details are assumed to be specific to the host 
environment, though they could be standardized under a different specification.  
This document does not describe the threading model of the SVSM. Some SVSM 
implementations may choose a separate execution conte xt (a unique VMSA) per guest vCPU, 
while other SVSM implementations may choose a single execution context that services all guest 
vCPUs. The negotiation of threading model s between the SVSM and the host as well as the 
mechanism by which the host indicates which guest vCPU makes a request are assumed to be 
specific to the host environment, though they could be standardized under a different 
specification.   
 
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 [Public]  
3 Environment  
The SVSM is expected to execute in VMPL0 of the guest. To ensure privilege separation for 
security -sensitive services, the bulk of the guest is expected to run at a VMPL other than 0. The 
SVSM must offer services to proxy requests that would normally be made by a guest running at 
VMPL0 but which are architecturally impossible when the guest is  running at a VMPL other than 
0 (e.g. , use of the PVALIDATE instruction and creating VMSA pages using RMPADJUST).  Those 
services form part of the “core protocol .” (See the “Core Protocol ” section on page 17.) 
The SVSM image and its initial data are expected to occupy a contiguous portion of the guest 
physical address (gPA)  space. That memory must be configured with VMPL permissions that 
grant access  to VMPL0 but no t to a  less privileged VMPL (lower privilege VMPL levels have a 
numerically higher number) . The initial SVSM memory configuration must be sufficient to  allow 
the SVSM to initialize and offer all  core protocol  SVSM services. A mechanism is defined by which 
the SVSM can obtain additional memory if required to support additional services that may be 
requested by the guest OS.    
 
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4 Discovery  
4.1 Boot  
When the guest first starts, it is expected to execute in the context of the SVSM before any lower 
VMPL is started. This permit s the SVSM to initialize itself and make itself discoverable.  
The SVSM advertises its presence by writing information into the secrets page, as described in 
the following table. Note that the portions o f the secrets page at byte offsets described here are 
always zeroed during initial construction of the secrets page and reserved for use by the SVSM. 
They will always be 0 for every guest unless they are initialized by the SVSM.  
Table 1: Secrets Page Fields  
Byte 
Offset  Size Field Name  Description  
0x140  8 bytes  SVSM_BASE  Base gPA of the SVSM area. This must be a multiple of 
4 KB. 
0x148  8 bytes  SVSM_SIZE  Number of bytes in the SVSM area. This must be a 
multiple of 4  KB. 
0x150  8 bytes  SVSM_CAA  gPA of an 4KB area used for guest/SVSM 
communication.  
0x158  4 bytes  SVSM_MAX_VERSION  Maximum version of the core protocol supported by 
the SVSM.  
0x15C  1 byte  SVSM_GUEST_VMPL  Indicates the VMPL at which the guest is executing.  
0x15D  3 bytes   Reserved.  
 
Note that the SVSM is expected to zero the portion of the secrets page that contains the  VM 
Platform Communication Key ( VMPCK ) associated with VMPL0, to prevent the guest OS from 
intruding on any conversation between the SVSM and the PSP.  
When the guest OS starts, it must first read the SVSM_SIZE field. If this field is 0, then no SVSM is 
present. If this field is non -0, indicating that an SVSM is present, then the guest must note the 
memory range spanned by the SVSM so that it does not attempt to use any memory in that 
range . (It may, for example, choose to identify that memory as EfiPlatformReserved .) It must use 
the speci fied SVSM_CAA value for use in communication with the SVSM.  
This specification assumes that the initial guest image contains only a single VMSA, used for the 
startup vCPU , whose contents have been measured as part of the guest launch and validated by 
the S VSM before executing the initial guest image . If the guest requires additional VMSAs, they 
should be created dynamically . (See the section “ SVSM_CORE_CREATE_VCPU Call ” on page  20.)  
 
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It is expected that the SVSM will examine the SEV_FEATURES specified for the guest and 
terminate if unsupported features are enabled. For example, if SEV_FEATURES for the guest OS 
has the VmsaRegProt feature enabled, but the SVSM does not have support for accessing such a 
VMSA , then the SVSM can terminate.  
4.2 Post -Boot

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4.2 Post -Boot  
After boot, it may st ill be necessary for guest components that do not have access to the secrets 
page  (e.g., UEFI runtime services invoked after the guest OS has started and taken over the SVSM 
interface)  to perform calls to the SVSM. For those components, an alternate discov ery 
mechanism is required.  
To support separate components, a discovery mechanism is defined that requires specific 
handling of #VC exceptions. It is assumed that if the SVSM was discovered at boot, then the guest 
component that implements the #VC handler i s also aware of the SVSM and the location of its 
Calling Area.  
To discover whether an SVSM is present, the separate component must execute 
CPUID(EAX=8000_001F). This will result in a #VC exception, and the #VC handler is expected to 
set EAX[28]=1 in the re sponse. When the component that executed the CPUID observes 
EAX[28]=1 in the response, it will know that an SVSM is reachable. This CPUID response bit is 
reserved for the purpose of enumerating the presence of an SVSM and will never be set by 
hardware  or in any CPUID data generated by the PSP.  
To discover the location of the SVSM Calling Area, the separate component must read MSR 
C001_F000. This will result in a #VC exception, and the #VC handler is expected to supply the gPA 
of the SVSM Calling Area as the  MSR value. Writes to the MSR are not expected, and the #VC 
handler is not required to handle writes to the MSR. This MSR is reserved for the purpose of 
exposing the gPA of the SVSM Calling Area and will never be implemented in hardware.  
Once the SVSM Call ing Area has been located, the separate component can issue calls to the 
SVSM normally. The separate component should not alter the state of the SVSM in a way that is 
not expected by the remainder of the guest (e.g., no component should issue the 
SVSM_CORE _REMAP_CA command).  
   
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5 Calling Convention  
Each call to the SVSM conveys data through a combination of the SVSM Calling Area (whose 
address was first configured through the SVSM_CAA field of the secrets page) and registers. Use 
of the Calling Area is necessa ry for the SVSM to detect the difference between a call that was 
issued by the guest and a spurious invocation by a poorly behaved host. Registers are used for all 
other parameters.  
The initially configured SVSM Calling Area is a page of memory that lies o utside the initial SVSM 
memory range and has not had its VMPL permissions restricted in any way. The address is 
guaranteed to be aligned to a 4  KB boundary, so the remainder of the page may be used by the 
guest for memory -based parameter passing if desired . 
The contents of the Calling Area are described in the following table : 
Table 2: Calling Area  
Byte 
Offset  Size Name  Description  
0x000  1 byte  SVSM_CALL_PENDING  Indicates whether a call has been requested by the 
guest (0=no call requested, 1=call requested).  
0x001  1 byte  SVSM_MEM_AVAILABLE  Free memory is available to be withdrawn.  
0x002  6 bytes   Reserved. The SVSM is not required to verify that 
these bytes are 0. 
 
Each call is identified by a 32 -bit protocol number and a 32-bit call identifier specific to the 
protocol.  The following protocols are defined:  
Table 3: Protocols  
Protocol Number  Protocol Description  
0 Core  
1 Attestation  
2 vTPM  
0x8000_0000 – 
0x8000_FFFF  Reserved for AMD reference implementation specific protocols  
 
To make a call to the SVSM, the guest OS must load the RAX register with the identifier of the 
call, where bits [63:32] hold the protocol number and bits [31:0] hold the call identifier within 
the protocol. Add itional registers and/or memory may need to be configured with values specific 
to the call being issued. Once all memory and registers have been prepared, the guest OS must  
 
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write a value of 1 to the SVSM_CALL_PENDING field of the Calling Area to indicate i ts readiness 
to issue the call. Finally, the guest OS must execute VMGEXIT to request that the host execute 
the SVSM on behalf of the calling vCPU  (see the Guest -Hypervisor Communicatio n Block 
Standardization  for details.)  
When the SVSM receives the call, it is expected to set VMSA.EFER.SVME=0 for the calling vCPU of 
the guest OS; this ensures that the host cannot attempt to reenter the calling vCPU wh ile SVSM 
call processing is underway . (An attempt to enter the guest would result in a failure due to 
invalid VMSA contents .) The SVSM is then expected to examine the SVSM_CALL_PENDING field 
to determine whether any call was actually requested by the guest  OS; if the host illegally 
entered the SVSM, this field will be 0. In such a case, no action will be taken by the SVSM other 
than setting VMSA.EFER.SVME=1 for the calling vCPU and returning to the guest. In addition, the 
SVSM is expected to examine VMSA .EXITCODE after setting VMSA.EFER.SVME=0 to ensure that 
the guest is on the expected VMGEXIT instruction boundary before proceeding. If the exit code 
does not indicate exiting due to VMGEXIT, the SVSM should reset VMSA.EFER.SVME=1 and take 
no further actio n before returning to the guest.  
Once the SVSM determines that a calling request is legitimate, it will read the value of RAX from 
the VMSA of the requesting vCPU and process the call accordingly. Upon completion of the call, 
the SVSM will set RAX in the V MSA of the requesting vCPU to indicate the result of the call . It will 
clear SVSM_CALL_PENDING in the Calling Area to indicate that the call was completed, set 
VMSA.EFER.SVME=1 for the calling vCPU (only after VMSA.RAX and SVSM_CALL_PENDING fields 
have bee n set), and return to the guest.  
Upon its return, the guest must atomically clear the SVSM_CALL_PENDING field and examine the 
previous value. The guest cannot trust that the host has executed the SVSM call as desired, nor 
can it assume that the host will n ot attempt to execute the SVSM call at an inopportune time, so 
the guest must clear the pending request at the same time that it extracts the previous value for 
examination. If the previous value of SVSM_CALL_PENDING was non -0, the guest knows that the 
SVSM never executed the call and must either retry the call or accept the fact that the host did 
not honor the request to execute the SVSM. If the previous value of SVSM_CALL_PENDING was 0, 
then the guest knows that the call completed and can examine th e value of RAX to determine 
whether the call completed successfully.  
Result values returned in RAX are 32 -bit values ( a 64-bit sign extension is ignored) divided into 
three categories: successful completion with distinct completion information, unsuccessfu l 
completion for a specified reason, and requests for additional memory. Most result codes are 
specific to individual protocols, but a portion of the result space is reserved for common values.  
   
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Table 4: Result Codes  
Result code  Name  Meaning  
0x0000_0000  SVSM_SUCCESS  The call completed successfully.  
0x0000_0000 - 
0x0000_0FFF   Reserved for future use.  
0x0000_1000 - 
0x3FFF_FFFF   Defined by the protocol that was invoked.  
0x4000_0000 - 
0x7FFF_FFFF   Additional memory is required to complete 
the requested operation. Bits 29:0 indicate 
the number of 4  KB pages that are 
required.  
0x8000_0000  SVSM_ERR_INCOMPLETE  The requested call was partially 
performed. The guest must request 
additional processing by setting 
SVSM_CALL_PENDING and invo king the 
SVSM again.  
0x8000_0001  SVSM_ERR_UNSUPPORTED_PROTOCOL  The requested protocol is not supported.  
0x8000_0002  SVSM_ERR_UNSUPPORTED_CALL  The requested call ID is not supported by 
the requested protocol.  
0x8000_0003  SVSM_ERR_INVALID_ADDRESS  A gPA sp ecified as part of a call is invalid.  
0x8000_0004  SVSM_ERR_INVALID_FORMAT  A reserved value was specified in 
SVSM_CALL_PENDING.  
0x8000_0005  SVSM_ERR_INVALID_PARAMETER  One or more invalid parameters were 
specified to a call.  
0x8000_0006  SVSM_ERR_INVALID_REQUEST  The request cannot be supported by the 
protocol handler that was invoked.  
0x8000_0007  SVSM_ERR_BUSY  The request cannot be handled at this 
time, the guest should issue the request 
again.  
0x8000_000 8 - 
0x8000_0FFF   Reserved for fut ure use.  
0x8000_1000 - 
0xFFFF_FFFF   Defined by the protocol that was invoked.  
 
Any input parameters that do not meet the alignment requirement will return the 
SVSM_ERR_INVALID_PARAMETER result value.  
Any input address that results in a fault when accessing the memory at that address will return 
the SVSM_ERR_INVALID_ADDRESS result value.   
 
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again.  
 
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Returning the SVSM_ERR_BUSY result code is implementation dependent and not specifically 
identified in any protocol call description. Any call returning this result  code must not leave the 
system in an intermediate state. Any call returning this result code is expected to either describe 
the progress made or else be idempotent.  
It is expected that any call that returns a result code in the 0x4000_0000 – 0x7FFF_FFFF w ill not 
have left the system in an intermediate state. A ny call returning one of these result codes is 
expected to either describe the progress made  or else be idempotent.    
 
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6 Core Protocol  
All SVSM implementations must support the core protocol, which has the  protocol ID value 0.  
The core protocol is versioned, permitting its extension over time; the initial version of the 
protocol is version 1. Versioning of the core protocol is strictly additive, i.e., all calls present in 
version 1 must be supported by all future implementations. The following table enumerates the 
set of calls supported by the core protocol : 
Table 5: Core Protocol Services  
Call ID  First version 
supported  Name  Function  
0 1 SVSM_CORE_REMAP_CA  Remap the SVSM Calling  Area to a new 
gPA.  
1 1 SVSM_CORE_PVALIDATE  Execute PVALIDATE.  
2 1 SVSM_CORE_CREATE_VCPU  Create a new vCPU.  
3 1 SVSM_CORE_DELETE_VCPU  Delete a vCPU.  
4 1 SVSM_CORE_DEPOSIT_MEM  Deposit additional memory for use by 
the SVSM.  
5 1 SVSM_CORE_WITHDRAW_MEM  Withdraw unused memory no longer 
required by the SVSM.  
6 1 SVSM_CORE_QUERY_PROTOCOL  Query the availability of a certain 
protocol.  
7 1 SVSM_CORE_CONFIGURE_VTOM  Reconfigures the use of vTOM.  
 
6.1 SVSM_CORE_REMAP_CA Call  
This call is use d to request that a new gPA be used for all future communication with the SVSM. It 
affects the Calling Area for calling vCPU only.  
Register  Size 
(Bytes)  Alignment 
(Bytes)  In/Out  Description  
RAX 4  Out Result value  
RCX 8 4 KB  In gPA of the new Calling Area  
 
Upon completion of the call, the SVSM_CALL_PENDING field of the previously configured Calling 
Area is cleared to indicate that the call has completed. In addition, if the call is successful, the 
SVSM will set the SVSM_CALL_PENDING field of the new Calling Area to 0 so that a spurious 
invocation by an uncooperative host cannot trick the SVSM into thinking that another call was 
requested by the guest. The guest can examine RAX to determine whether the call was  
 
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successful. If so, the previously configured C alling Area will no longer be examined by the SVSM 
and can be reused by the guest for any purpose.  
6.2 SVSM_CORE_PVALIDATE Call  
This call is used to request  that the SVSM execute PVALIDATE on behalf of the guest.  
RCX 8 8 In gPA of the list of requested operations  
The list of requested operations is specified according to the format of the following table.  
Table 6: PVALIDATE Operation  
Byte 
Offset  Size 
(Bytes)  Meaning  
0x000  2 Number of entries in the list.  
0x002  2 Index of the next entry in the list to be processed.  
0x004  4 Reserved.  
0x008  8 First entry in the list. Each entry specifies bits as follows:  
Bits 1:0  Value of RCX for the PVALIDATE operation (0=4  KB page, 1=2  MB 
page).  
Bit 2  Value of RDX for the PVALIDATE operation (0=make invalid, 1=make 
valid).  
Bit 3  Ignore EFLAGS.CF warnings  when set to 1. 
Bits 11:4  Reserved.  
Bits 63:12  gPA page number. Note that bits [20:12] must be 0 if the entr y 
describes 2  MB. 
0x010  8 Second entry in the list, if any. Additional list entries follow.  
 
The number of entries in the list must not be so large that the parameter list crosses a 4  KB 
boundary. The number of entries must be at least 1. If  the number o f entries is not within a valid 
range, the call will return SVSM_ERR_INVALID_PARAMETER.  
The index of the next entry to be processed must be strictly less than the number of entries in 
the list ; otherwise, the call will return SVSM_ERR_INVALID_PARAMETER.  
Upon completion of a call, the index of the next entry to be processed will indicate the number 
of entries in the list that have been successfully processed. If the call returns 
SVSM_ERR_INCOMPLE TE, then the SVSM was unable to process the entire list in a single 
operation, and the guest should reload RAX with the correct calling code (RCX will remain   
 
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unmodified during the call) and issue the call again; the SVSM will continue processing based on 
the index of the next entry to be processed. If the call returns any other error, the index of the 
next entry will indicate the index of the entry that failed processing. If the call succeeds, the 
index of the next entry will be equal to the number of entri es in the list.  
The SVSM is expected to check that the guest is not attempting to execute PVALIDATE on a gPA 
that is assigned to the SVSM itself. If the SVSM detects that the guest is attempting to execute 
PVALIDATE on an address that is assigned to the SV SM, the call will return 
SVSM_ERR_INVALID_ADDRESS.  
If an entry sets bit 2=0 (requesting invalidation of the page), the SVSM will first execute 
RMPADJUST to revoke permission for all VMPLs other than VMPL0. This is necessary to ensure 
that subsequent attemp t to validate a page will observe a consistent VMPL permission state 
regardless of whether the host executes RMPUPDATE at any point in time.  
If invocation of a PVALIDATE instruction results in the instruction completing with EFLAGS.CF=1, 
and if the entry t hat provoked the EFLAGS.CF=1 warning did not set the appropriate bit, the call 
will fail with the error code 0x8000_1010.  
If invocation of a PVALIDATE instruction (or RMPADJUST instruction) results in the instruction 
completing with EAX != 0, the call will  fail with an error code in the range 0x8000_1000 through 
0x8000_100F, where the value is equal to (0x8000_1000 + EAX). PVALIDATE is architecturally 
specified to return EAX error codes in the range 0x0000 -0x000F; if PVALIDATE unexpectedly 
returns a value o utside of that range (e.g. , due to architectural expansion of the error code space 
in a future revision), the call will fail with the error code 0x8000_1011.  
If invocation of PVALIDATE completes successfully, and if the entry sets bit 2=1 (requesting 
valid ation of the page), the SVSM will additionally zero out the memory for the page  (this 
ensures no leakage of VMPL0 memory to the lower VMPL if the hypervisor is being malicious)  
and execute RMPADJUST to grant full permission to the VMPL of the vCPU making t he request, 
as well as all more privileged VMPLs (numerically lower or equal to the requesting VMPL).  
6.3 SVSM_CORE_CREATE_VCPU Call  
This call is used to request creation of a new vCPU context.  
RCX 8 4 KB  In gPA of the VMSA  to be created for the vCPU  
RDX 8 4 KB  In gPA of the Calling Area  associated with the vCPU  
R8 4  In APIC ID of the vCPU  
  
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The SVSM will check that both gPA  values specified do not conflict with any existing usage (SVSM 
private pages , any active VMSA address  or any  active  Calling Area address). If a conflict is 
detected, the call will return SVSM_ERR_INVALID_ADDRESS.  
The SVSM will revoke access to every VMPL other than itself to ensure that the VMSA page is not 
tampered with during the process of VMSA validation and assignment . 
The SVSM will  validate the new VMSA:  
• If VMSA.VMPL == 0, the call will return SVSM_ERR_INVALID_PARAMETER.  
• If VMSA.VMPL < vCPU.VMPL, the  call will return SVSM_ERR_INVALID_PARAMETER.  
• If VMSA. EFER.SVME  != 1, the call will return  SVSM_ERR_INVALID_PARAMETER.  
• If VMSA.SEV_FEATURES != startup vCPU  VMSA. SEV_FEATURES, the call will return 
SVSM_ERR_INVALID_PARAMETER.  
If the VMSA checks pass, the SVS M will execute RMPADJUST to turn the page into a VMSA page 
so it can be used immediately. The SVSM will cache the gPA of the  VMSA and the gPA of the  
Calling Area associated with th e target  vCPU for use  in subsequent calls to the SVSM  (register 
input, prot ocol request, etc.).  
Once a page is established as a VMSA page, it is treated as privately owned by the SVSM for the 
purpose of detecting memory usage conflicts. Any call which specifies the gPA of a VMSA page as 
an input gPA will fail with SVSM_ERR_INVALI D_ADDRESS. This is also true of the VMSA of the 
startup vCPU . (This VMSA is not required to be within the initial contiguous range of pages

startup vCPU . (This VMSA is not required to be within the initial contiguous range of pages 
assigned to the SVSM since the guest is expected to know where its own VMSA is located .) 
6.4 SVSM_CORE_DELETE_VCPU Call  
This call is used to delete a vCPU that was previously configured.  
RCX 8 4 KB  In gPA of the VMSA to be deleted  
 
The SVSM will verify that the specified gPA belongs to a known VMSA address . If the gPA is not a 
known VMSA address , the call will return SVSM_ERR_INVALID_PARAMETER.  The startup vCPU 
can never be deleted. If the VMSA is associated with the startup vCPU, the  call will return 
SVSM_ERR_INVALID_PARAMETER.  If the VMPL of the VMSA is less than the VMPL of the 
requester, the call will return SVSM_ERR_INVALID_PARAMETER.    
 
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The SVSM will set VMSA.EFER.SVME  = 0. If the SVSM fails to set VMSA.EFER.SVME to 0  (because 
the V MSA is currently executing), the call will return a result  value  of 0x80001003 (equivalent to 
the FAIL_INUSE error code).  
The SVSM will execute RMPADJUST to convert the page from a VMSA page to a normal page and 
ensure that full access is available to the VMPL of the requesting vCPU and all more privileged 
VMPLs (numerically lower than or equal to the requesting VMPL).  
Once deletion of the vCPU is complete, the previously configured VMSA and Calling Area will no 
longer be examined by the SVSM and can be reu sed by the guest for any purpose.  If the VMSA 
was the VMSA of the requester, the SVSM will not return to the caller.  
6.5 SVSM_CORE_DEPOSIT_MEM Call  
This call can be made to grant additional memory for exclusive use by the SVSM in case it 
requires additional me mory to perform its work. The guest can know when additional memory is 
required because the SVSM will return a status code in the range 0x4nnn_nnnn, indicating the 
number of additional 4  KB pages required.  
The caller is responsible for coordinating calls t o deposit or withdraw memory across all vCPUs.  
RCX 8 8 In gPA of the list of memory pages  
 
The list of memory pages is specified according to the format of the following table.  
Table 7: Deposit Memory Operation  
Byte 
Offset  Size Meaning  
0x000  2 bytes  Number of entries in the list.  
0x002  2 bytes  Index of the next entry in the list to be processed.  
0x004  4 bytes  Reserved.  
0x008  8 bytes  First entry in the list. Each entry specifies bits as follows:  
Bits 1:0  Size of the memory range described by this entry (0=4  KB page, 
1=2 MB page).  
Bits 11:2  Reserved.  
Bits 63:12  gPA page number. Note that bits [20:12] must be 0 if the entry 
0x010  8 bytes  Second entry in the list, if any. Additional list entries follow.   
 
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boundary. The number of entries must be at least 1. If number of entries is not within a valid 
the list ; otherwise, the call will return SVSM_ERR_INVALID_PARAM ETER.  
SVSM_ERR_INCOMPLETE, then the SVSM was unable to process the entire list  in a single 
operation, and the guest should reload RAX with the correct calling code (RCX will remain 
the index of the next entry to be processed. If the call  returns any other error, the index of the 
index of the next entry will be equal to the number of entries in the list.  
For each entry in the list, the SVSM wi ll verify that the memory described is not already private to 
the SVSM and does not overlap any page that has been configured as a Calling Area. If any 
overlap is detected, the call will return SVSM_ERR_INVALID_ADDRESS.  
For each valid entry in the list, th e SVSM will execute RMPADJUST to restrict VMPL permissions 
so that the pages are only accessible to VMPL0, making the pages private to the SVSM.  
The call may return failure with the value of the next entry index not being 0. This indicates that 
some mem ory was successfully deposited with the SVSM, and some was not.  
6.6 SVSM_CORE_WITHDRAW_MEM Call  
This call permits the guest to reclaim memory that was made private to the SVSM but is no 
longer needed by the SVSM. Any SVSM operation that results in free memory that can be 
reclaimed will set the SVSM_MEM_AVAILABLE flag in the Calling Area.  
The caller is responsible for coordinating calls to deposit or withdraw memory across all vCPUs.  
RCX 8 8 In gPA of an area to hold a list of memory pages  
   
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The list of memory pages  is populated by the SVSM and  is specified according to the format of 
the following table.  
Table 8: Withdraw Memory Operation  
Byte 
0x002  6 bytes  Unused.  
0x008  8 bytes x number of entries  List of gPA values of 4 KB pages that are no longer in use.  
 
The maximum number of entries returned is constrained so that the returned list will not cross a 
4 KB boundary. If the parameter page is aligned such that there is no room for any entries (i.e. , 
the parameter page gPA is aligned to a 4  KB boundary plus 0xFF8 bytes), the call will return 
If no memory is available to withdraw, the number of entries will be 0. Unused entries beyond 
the end of the list are not zeroed.  
The SVSM must  execute RMPADJUST for all memory being withdrawn to grant full access to the 
VMPL of the requesting vCPU and to all  more privileged VMPLs (numerically lower  than  or equal 
to the requesting VMPL). Upon completion of the call, the SVSM will no longer access the pages, 
which can then be reused by the guest for any purpose.  
The SVSM_MEM_AVAILABLE flag of the Calling Area o f the startup vCPU may  be updated to 
indicate whether additional memory remains available for withdrawal.  
This call will never return SVSM_ERR_INCOMPLETE. If the SVSM is unable to withdraw all 
available memory, the call must  complete with SVSM_SUCCESS , and the SVSM_MEM_AVAILABLE 
flag of the startup vCPU’s Calling Area will indicate that additional memory remains available for 
withdrawal.  
6.7 SVSM_CORE_QUERY_PROTOCOL Call  
This call is used to determine the availability of a given protocol. Bits [63:32] of regist er RCX 
contain the requested protocol number. Bits [31:0] of register RCX contain the desired version of 
the requested protocol. Upon completion of the call, register RCX is set to indicate availability of 
the requested protocol. If the protocol is unavail able at the requested version, register RCX will 
contain the value 0. If the protocol is available at the requested version, bits [63:32] of register 
RCX will support the maximum supported protocol version number, and bits [31:0] of register 
RCX will su pport the minimum supported protocol version number.   
 
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This call will always return SVSM_SUCCESS since the availability of the protocol is advertised 
through RCX. Querying for the presence of a protocol is not permitted to demand additional 
SVSM memory . (Calls to that protocol may request memory to be deposited .) 
6.8 SVSM_CORE_CONFIGURE_VTOM Call  
This call is used to query or reconfigure the use of vTOM on the calling processor. To support a 
transition between vTOM -based confidentiality and confidentiality determ inations that rely 
exclusively on the Page Table Entry ’s C-bit, this call will also change the guest value of CR3, as 
well as RIP and RSP, to permit a clean transition from one environment to another.  
SVSM_CORE_CONFIGURE_VTOM calls take two forms: query an d configure, as indicated by bit 0 
of RCX . (RCX[0]=1 indicates query, while RCX[0]=0 indicates configure .) The register convention 
for the call s is described in the following table.  
Table 9: vTOM Configuration  Operation  
Register  Contents  
RCX on 
entry  Query  Bit 0  Must be 1. 
Bit 63:1  Must be 0. 
Configure  Bit 0  Must be 0. 
Bit 1  Set to 0 to disable vTOM, or set to 1 to enable vTOM.

RCX on 
Bit 1  Set to 0 to disable vTOM, or set to 1 to enable vTOM.  
Bit 2  If set to 1, will cause VMSA.CR3 to be set to the value in RDX 
upon successful completion of the call.  
Bit 3  If set to 1, will cause VMSA.RIP to be set to the value in R8 
Bit 4  If set to 1, will cause VMSA.RSP to be set to the value in R9 
Bits 11:5  Must be 0. 
Bits 63:12 Bits 63:12 of the desired vTOM value. Must be 0 if vTOM is 
being disabled.  
RCX result  Bit 0  Will be 0. 
Bit 1  Will be 1 if vTOM configuration is supported ; otherwise 0. 
Bits 11:2  Will be 0. 
Bits 19:12  vTOM alignment requirement as a power of two (value of 20 would indicate 
that vTOM must be aligned to a 1  MB boundary).  
Bits 63:20  0. 
RDX 
result  Minimum valid vTOM value if vTOM configuration is supported ; otherwise undefined.  
R8 result  Maximum valid vTOM value if vTOM configuration is supported ; otherwise undefined.  
   
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If the call is successful, vTOM will be reported or reconfigured as requested. If vTOM is being 
reconfigured, then CR3 and RSP will be updated as requested, and execution w ill continue at the 
specified RIP with RAX containing the value SVSM_SUCCESS.  
If the call is unsuccessful, no VMSA changes will occur, and execution will continue at the 
instruction following the VMGEXIT with RAX containing the appropriate error code.  
The call may fail if any reserved bit RCX is set inappropriately; this will result in the call returning 
The SVSM may choose to deny the call if it cannot support the request. For example, the SVSM 
may be unable to reconfigure VTOM if more than a single vCPU has been configured or if the 
requested configuration differs from configurations present on other vCPUs. This will result in 
the call returning SVSM_ERR_INVALID_REQUEST. If the value of vTOM is one that cannot be 
supported by th e hosting environment, then the call will result in SVSM_ERR_INVALID_ADDRESS.   
 
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7 Attestation Protocol  
The attestation protocol has protocol ID value 1. The attestation protocol is versioned, permitting 
its extension over time; the initial version of the attestation protocol is version 1. Versioning of 
the attestation  protocol is strictly additive, i.e., all calls present in version 1 must be supported by 
all future implementations. The following table enumerates the set of calls supported by the 
attestation protocol:  
Table 10: Attestation  Protocol Services  
0 1 SVSM_ATTEST_SERVICES  Retrieve an attestation report for all 
SVSM services (e.g. vTPM, etc.).  
1 1 SVSM_ATTEST_SINGLE_SERVICE  Retrieve an attestation report for a 
single SVSM service  
 
7.1 SVSM_ATTEST_SERVICES Call  
This call is used to request a VMPL0 attestation report that includes a services manifest of the 
services that are running in the SVSM  as part of the report data.  Optionally, a certificate data 
buffer can be supplied. When supplie d, the hypervisor can provide certificate data back to the 
caller when processing the SNP Guest Request used to generate the attestation report.  
RCX 8 8 In gPA of the attestation services operation structure, see 
Table 11: Attest Services Operation  
8  Out Services manifest size (in bytes)  
RDX 8  Out Certificate data size (in bytes)  
R8 8  Out Attestation report size (in bytes)  
 
The inputs associated with the attest services call are specified according to the format of the 
following table.    
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Byte 
(Bytes)  Alignment  
0x000 8 4 KB  Attestation report buffer gPA  
0x008  4  Attestation report buffer size (in bytes)  
0x00C  4  RESERVED – MBZ  
0x010 8  Nonce gPA  
0x01 8 2  Nonce size (in bytes)  
0x01 A 6  RESERVED – MBZ  
0x020 8 4 KB  Services manifest buffer gPA  
0x02 8 4  Services manifest buffer size (in bytes)  
0x02C  4  RESERVED – MBZ  
0x030  8 4 KB  Certificate data buffer gPA  
0x038  4  Certificate data buffer size (in bytes)  
0x03C  4  RESERVED – MBZ  
 
The attest services operation structure must not cross a 4 KB boundary.  If the gPA of the 
structure is such that the structure crosses a 4 KB boundary, the call will return 
The attestation report buffer will be treated as physically contiguous in the guest address space if 
the buffer size is greater th an 4 KB.  
The nonce must not cross a 4 KB boundary. If the nonce crosses a 4 KB boundary, the call will 
return SVSM_ERR_INVALID_PARAMETER.  
The services manifest buffer  will be treated as physically  contiguous in the guest address space  if 
the buffer size is  greater than 4 KB.  
The certificate data buffer is optional. Its presence is indicated by setting the certificate data 
buffer size to a non -0 value. If the certificate data buffer length is non -0, the certificate data 
buffer will be treated as physic ally contiguous in the guest address space if the buffer size is 
greater than 4 KB.  
All gPA values must not be gPA values that are assigned to the SVSM itself. If the SVSM detects 
that the guest is specifying an address that is assigned to the SVSM, the ca ll will return 
The SVSM will assemble a services manifes t that will be used as input to the attestation request . 
Each service will produce a descriptive section for the manife st in a service -defined  format.  If the 
size of the asse mbled services manifest exceeds the size of the supplied services manifest buffer ,  
 
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RCX will be set to the size of the services manifest  (in bytes)  and the call will return 
The services manifest is identified by a 16 -byte GUID , 4-byte length and a 4 -byte services count 
at the beginning of the manifest. The services in the manifest , if any,  are identified in a table 
beginning at offset 24 (0x18) into the manifest. Each service entry consists of a 16 -byte GUID, a 
4-byte offse t from the start of the manifest to the service data, and a 4 -byte length  of the service 
data . A given SVSM binary must produce a services manifest with the services ordered and 
assembled in the same manner across multiple calls to SVSM_ATTEST_SERVICES and  across 
different VM instances.  
Table 12: Services Manifest  
Byte 
0x000  16 Services manifest GUID: 63849ebb -3d92 -4670 -a1ff-58f9c94b87bb  
0x010  4 Services manifest length  
0x014  4 Number of services contained in the manifest  
First service table entry, if any.  
0x018  16 Service GUID  
0x028  4 Service data offset  
0x02C  4 Service data length  
Next service table entry, if any. Additional table service table entries follow.  
0x030   
 
The minimum length of a services manifest (when there are no services present) is 24 (0x18) 
bytes.  
Each service will document its GUID value and the format of its manifest content. It is suggested 
to use the same GUID/offset/length format as is used here.  
The Input REPORT_DATA supplied on the SNP attestation request will be the SHA -512 digest of 
the input nonce and the services manifest, S HA-512(Nonce || Services Manifest).  The input 
VMPL supplied on the SNP attestation request will be 0.  
If a certificate d ata buffer was provided and if the size of the certificate data from the hypervisor 
exceeds the size of the supplied certificate data buffer, RCX will be set to the size of the services 
manifest and RDX will be set to the size of the certificate data (in b ytes) and the call will return 
If the size of the SNP attestation report exceeds the size of the supplied attestation report buffer, 
RCX will be set to the size of the services manifest, RDX will be set to the size of the certif icate   
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data (in bytes , if a certificate buffer was supplied ) and R8 will be set to the size of the attestation 
report (in bytes) and the call will return SVSM_ERR_INVALID_PARAMETER.  
Upon successful completion of the SNP attestation request, the attestation report will be copied 
to the  input  attestation report buffer  gPA, the services manifest will be copied to the input 
services manifest  buffer  gPA, RCX will be set to the size of the services manifest  and, if a 
certificate data buffer was provided, the certificate data will be copied to the input certificate 
data buffer gPA and RDX will be set to the size of the certificate data . Should the SNP attestation

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data buffer gPA and RDX will be set to the size of the certificate data . Should the SNP attestation 
request fail, RAX will be set to 0x8000_1000.  
7.2 SVSM_ATTEST_SINGLE_SERVICE Call  
This call is used to request a VMPL0 attestation report that includes a service manifest for the 
specified service that is running in the SVSM as part of the report data.  
(Bytes)  In/Out  Descri ption  
8  Out Service manifest size (in bytes)  
 
The inputs associated with the attest  single  service call are specified according to the format of 
Table 13: Attest Single Service Operation  
Byte 
0x01 A 6  Reserved  
0x020 8 4 KB  Service manifest buffer gPA  
0x02 8 4  Service manifest buffer size (in bytes)  
0x03C  4  RESERVED – MBZ   
 
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Byte 
0x040 16  GUID of service to attest  
0x050 4  Requested manifest  version  
0x054  4  RESERVED – MBZ  
 
The attest  single  service operation structure must not cross a 4 KB boundary. If the gPA of the 
The attestation report buffer will be treated as physically contig uous in the guest address space if 
the buffer size is greater than 4 KB.  
The service manifest buffer will be treated as physica lly contiguous in the guest address space if 
buffer size to a non -0 value. If the certificate data buffer length is non-0, the certificate data 
buffer will be treated as physically contiguous in the guest address space if the buffer size is 
that the gues t is specifying an address that is assigned to the SVSM, the call will return 
The GUID of the service to be attested needs to be an available service of the  SVSM. If the 
request ed service is not available , the call will return SVS M_ERR_INVALID_PARAMETER.  
The SVSM service must support the version of the manifest requested. If the requested manifest 
version is not supported, the call will return SVSM_ERR_INVALID_PARAMETER.  
The SVSM will assemble a service manifest that will be used a s input to the attestation request. 
The service will produce a descriptive manifest in a service -defined format. If the size of the 
assembled service manifest exceeds the size of the supplied service manifest buffer, R CX will be 
set to the size of the serv ice manifest (in bytes) and the call will return 
the input nonce and the service manifest, SHA -512(Nonce || Service Manifest).  The input  VMPL 
supplied on the SNP attestation request will be 0.    
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If a certificate data buffer was provided and if the size of the certificate data from the hypervisor 
exceeds the size of the supplied certificate data buffer, RCX will be set to the size of the serv ices 
manifest and RDX will be set to the size of the certificate data (in bytes) and the call will return 
RCX will be set to t he size of the services manifest, RDX will be set to the size of the certificate 
to the input attestation report buffer gPA, the service manifest will be copied to the input service 
manifest buffer gPA , RCX will be set to the size of the se rvice manifest , if a certificate data buffer 
was provided, the certificate data will be copied to the input certificate data buffer gPA and RDX 
will be set to the size of the certificate data.  Should the SNP attestation request fail, RAX will be 
set to 0x8 000_1000.   
 
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8 vTPM Protocol  
The vTPM protocol has protocol ID value two.  The vTPM protocol is versioned, permitting its 
extension over time; the initial version of the vTPM protocol is version 1. Versioning of the vTPM 
protocol is strictly additive, i.e., all  calls present in version 1 must be supported by all future 
implementations.  
The vTPM protocol follows the Official TPM 2.0 Reference Implementation (by Microsoft)  
simulator protocol.  
The following table enumerates the set of calls supported by the vTPM protocol:  
Table 14: Attestation Protocol Services  
0 1 SVSM_VTPM_QUERY  Query vTPM  command and feature 
support.  
1 1 SVSM_VTPM_CMD  Execute a TPM command.  
 
8.1 SVSM_VTPM_QUERY Call  
This call is used to query the support provided by the vTPM.  
RCX 8  Out Supported vTPM platform commands  
RDX 8  Out Supported vTPM features  
 
RCX is used to indicate the supported platform command s. For each platform command 
supported by the vTPM, the corresponding bit will be set in RCX. Bits for any unsupported and 
undefine d platform commands must be cleared. The platform command values follow the values 
used by the Official TPM 2.0 Reference Implementation (by Microsoft)  simulator pr otocol.  
RDX is used to indicate support for vTPM features:  
Bit Feature  Description  
63:0  Must -be-0   
 
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8.2 SVSM_VTPM_CMD Call  
This call is used to execut e a vTPM operation . 
RCX 8 4 KB  In gPA of the vTPM request/response  structure  
 
All command request buffers have a common structure as specified by the following table:  
Table 15: vTPM  Common  Request /Response  Structure  
Byte  
0x000  4 In Platform c ommand  
Out Platform c ommand response size  
Each command can build upon this common request/response structure to create a structure 
specific to the command.  The commands that do this are:  
• TPM_SIGNAL_HASH_DATA  
• TPM_SEND_COMMAND  
• TPM_REMOTE_HANDSHAKE  
• TPM_SET_ALTERNATIVE_RESULT  
Only the TPM_SEND_COMMAND will be documented in this specification.  
If a vTPM request/response structure has not been supplied, the call w ill return 
SVSM_ERR_INVALID_PARAMETER.  It is expected that the request/response structure is large 
enough to hold the expected output of the vTPM request. The vTPM request/response buffer will 
be treated as physically contiguous in the guest address space.  
The vTPM request/response structure gPA must not be gPA values that is assigned to the SVSM 
itself. If the SVSM detects that the guest is specifying an address that is assigned to the SVSM, 
the call will return SVSM_ERR_INVALID_ADDRESS.  
If the specified platform command is not supported, the call will return 
SVSM_ERR_INVALID_PARAMETER.   
 
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8.2.1 TPM_SEND_COMMAND  
Execute a TPM command and return the results.  
For TPM_SEND_COMMAND , platform command 8, the request buffer is specified according to 
the format of the following table.  
Table 16: TPM_SEND_COMMAND Request Structure  
Byte 
0x000  4 Platform c ommand  (8) 
0x004  1 Locality  (must -be-0) 
0x005  4 TPM Command size (in bytes)  
0x009  Variable  TPM Command  
 
The response buffer is specified according to the format of the following table.  
Table 17: TPM_SEND_COMMAND Response Structure  
Byte 
0x000  4 Response size (in bytes)  
0x004  Variable  Response

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Byte 
 
Byte 
0x004  Variable  Response  
 
Locality usage for the vTPM is not defined. If a Locality value other than 0 is specified, the call will 
8.3 Service Attestation Data  
8.3.1 Service Attestation GUID  
The vTPM service attestation  GUID is c476f1eb -0123 -45a5 -9641 -b4e7dde5bfe3 . 
8.3.2 SVSM_ATTEST_SERVICES  Manifest Data  
The manifest data used in an SVSM_ATTEST_SERVICES call  is the same format as the manifest 
version 0 format of the SVSM_ATTEST_SINGLE_SERVICE call, see Table 18: vTPM Service  Manifest  
Data Structure  in section 8.3.3.1 .   
 
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8.3.3 SVSM_ATTEST_SINGLE_SERVICE  Manifest Data  
8.3.3.1  Manifest  Version 0  
The manifest data used in an SVSM_ATTEST_SINGLE_SERVICE call for manifest version 0 is 
specified according to the following table.  
Table 18: vTPM Service  Manifest  Data Structure  
Byte 
0x000  Variable  TPMT_PUBLIC structure of the endorsement key